diff --git a/bsp/nxp/lpc/lpc176x/CMSIS/CM3/CoreSupport/core_cm3.c b/bsp/nxp/lpc/lpc176x/CMSIS/CM3/CoreSupport/core_cm3.c deleted file mode 100644 index fcff0d133ca..00000000000 --- a/bsp/nxp/lpc/lpc176x/CMSIS/CM3/CoreSupport/core_cm3.c +++ /dev/null @@ -1,784 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.c - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File - * @version V1.30 - * @date 30. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -__ASM uint32_t __REV16(uint16_t value) -{ - rev16 r0, r0 - bx lr -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -__ASM int32_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -__ASM void __CLREX(void) -{ - clrex -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -__ASM uint32_t __get_BASEPRI(void) -{ - mrs r0, basepri - bx lr -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -__ASM void __set_BASEPRI(uint32_t basePri) -{ - msr basepri, r0 - bx lr -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -__ASM uint32_t __get_FAULTMASK(void) -{ - mrs r0, faultmask - bx lr -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -__ASM void __set_FAULTMASK(uint32_t faultMask) -{ - msr faultmask, r0 - bx lr -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#pragma diag_suppress=Pe940 - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) -{ - __ASM("mrs r0, psp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM("msr psp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) -{ - __ASM("mrs r0, msp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM("msr msp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - __ASM("rev16 r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - __ASM("rbit r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -uint8_t __LDREXB(uint8_t *addr) -{ - __ASM("ldrexb r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - __ASM("ldrexh r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - __ASM("ldrex r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - __ASM("strexb r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - __ASM("strexh r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - __ASM("strex r0, r0, [r1]"); - __ASM("bx lr"); -} - -#pragma diag_default=Pe940 - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) __attribute__( ( naked ) ); -uint32_t __get_PSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, psp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n\t" - "BX lr \n\t" : : "r" (topOfProcStack) ); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) __attribute__( ( naked ) ); -uint32_t __get_MSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, msp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n\t" - "BX lr \n\t" : : "r" (topOfMainStack) ); -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -uint32_t __get_BASEPRI(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -uint32_t __get_PRIMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -uint32_t __get_FAULTMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -uint32_t __get_CONTROL(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -uint32_t __REV(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -int32_t __REVSH(int16_t value) -{ - uint32_t result=0; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -uint8_t __LDREXB(uint8_t *addr) -{ - uint8_t result=0; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - uint16_t result=0; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif diff --git a/bsp/nxp/lpc/lpc176x/CMSIS/CM3/CoreSupport/core_cm3.h b/bsp/nxp/lpc/lpc176x/CMSIS/CM3/CoreSupport/core_cm3.h deleted file mode 100644 index 7ab7b4b4368..00000000000 --- a/bsp/nxp/lpc/lpc176x/CMSIS/CM3/CoreSupport/core_cm3.h +++ /dev/null @@ -1,1818 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V1.30 - * @date 30. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CM3_CORE_H__ -#define __CM3_CORE_H__ - -/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration - * - * List of Lint messages which will be suppressed and not shown: - * - Error 10: \n - * register uint32_t __regBasePri __asm("basepri"); \n - * Error 10: Expecting ';' - * . - * - Error 530: \n - * return(__regBasePri); \n - * Warning 530: Symbol '__regBasePri' (line 264) not initialized - * . - * - Error 550: \n - * __regBasePri = (basePri & 0x1ff); \n - * Warning 550: Symbol '__regBasePri' (line 271) not accessed - * . - * - Error 754: \n - * uint32_t RESERVED0[24]; \n - * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced - * . - * - Error 750: \n - * #define __CM3_CORE_H__ \n - * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced - * . - * - Error 528: \n - * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n - * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced - * . - * - Error 751: \n - * } InterruptType_Type; \n - * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced - * . - * Note: To re-enable a Message, insert a space before 'lint' * - * - */ - -/*lint -save */ -/*lint -e10 */ -/*lint -e530 */ -/*lint -e550 */ -/*lint -e754 */ -/*lint -e750 */ -/*lint -e528 */ -/*lint -e751 */ - - -/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core registers and bitfields - - Cortex-M core peripheral base address - @{ - */ - -#ifdef __cplusplus - extern "C" { -#endif - -#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - -#include /* Include standard types */ - -#if defined (__ICCARM__) - #include /* IAR Intrinsics */ -#endif - - -#ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ -#endif - - - - -/** - * IO definitions - * - * define access restrictions to peripheral registers - */ - -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register - @{ -*/ - - -/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC - memory mapped structure for Nested Vectored Interrupt Controller (NVIC) - @{ - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ -} NVIC_Type; -/*@}*/ /* end of group CMSIS_CM3_NVIC */ - - -/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB - memory mapped structure for System Control Block (SCB) - @{ - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ -/*@}*/ /* end of group CMSIS_CM3_SCB */ - - -/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick - memory mapped structure for SysTick - @{ - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ -/*@}*/ /* end of group CMSIS_CM3_SysTick */ - - -/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM - memory mapped structure for Instrumentation Trace Macrocell (ITM) - @{ - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ - __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ - __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ -/*@}*/ /* end of group CMSIS_CM3_ITM */ - - -/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type - memory mapped structure for Interrupt Type - @{ - */ -typedef struct -{ - uint32_t RESERVED0; - __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ -#else - uint32_t RESERVED1; -#endif -} InterruptType_Type; - -/* Interrupt Controller Type Register Definitions */ -#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ -#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ -#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ - -#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ -#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ - -#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ -#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ -/*@}*/ /* end of group CMSIS_CM3_InterruptType */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) -/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU - memory mapped structure for Memory Protection Unit (MPU) - @{ - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ -#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ -#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ -#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ -#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ -#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ -#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@}*/ /* end of group CMSIS_CM3_MPU */ -#endif - - -/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug - memory mapped structure for Core Debug Register - @{ - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ -/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ - - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ - -#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ -#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_register */ - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#define __enable_fault_irq __enable_fiq -#define __disable_fault_irq __disable_fiq - -#define __NOP __nop -#define __WFI __wfi -#define __WFE __wfe -#define __SEV __sev -#define __ISB() __isb(0) -#define __DSB() __dsb(0) -#define __DMB() __dmb(0) -#define __REV __rev -#define __RBIT __rbit -#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) -#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) -#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) -#define __STREXB(value, ptr) __strex(value, ptr) -#define __STREXH(value, ptr) __strex(value, ptr) -#define __STREXW(value, ptr) __strex(value, ptr) - - -/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ -/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -extern void __CLREX(void); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -#else /* (__ARMCC_VERSION >= 400000) */ - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -#define __CLREX __clrex - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & 1); -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ -#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ - -static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } - -#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ -static __INLINE void __WFI() { __ASM ("wfi"); } -static __INLINE void __WFE() { __ASM ("wfe"); } -static __INLINE void __SEV() { __ASM ("sev"); } -static __INLINE void __CLREX() { __ASM ("clrex"); } - -/* intrinsic void __ISB(void) */ -/* intrinsic void __DSB(void) */ -/* intrinsic void __DMB(void) */ -/* intrinsic void __set_PRIMASK(); */ -/* intrinsic void __get_PRIMASK(); */ -/* intrinsic void __set_FAULTMASK(); */ -/* intrinsic void __get_FAULTMASK(); */ -/* intrinsic uint32_t __REV(uint32_t value); */ -/* intrinsic uint32_t __REVSH(uint32_t value); */ -/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ -/* intrinsic unsigned long __LDREX(unsigned long *); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } -static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } - -static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } - -static __INLINE void __NOP() { __ASM volatile ("nop"); } -static __INLINE void __WFI() { __ASM volatile ("wfi"); } -static __INLINE void __WFE() { __ASM volatile ("wfe"); } -static __INLINE void __SEV() { __ASM volatile ("sev"); } -static __INLINE void __ISB() { __ASM volatile ("isb"); } -static __INLINE void __DSB() { __ASM volatile ("dsb"); } -static __INLINE void __DMB() { __ASM volatile ("dmb"); } -static __INLINE void __CLREX() { __ASM volatile ("clrex"); } - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -extern uint32_t __REV(uint32_t value); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - - -/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface - Core Function Interface containing: - - Core NVIC Functions - - Core SysTick Functions - - Core Reset Functions -*/ -/*@{*/ - -/* ########################## NVIC functions #################################### */ - -/** - * @brief Set the Priority Grouping in NVIC Interrupt Controller - * - * @param PriorityGroup is priority grouping field - * - * Set the priority grouping field using the required unlock sequence. - * The parameter priority_grouping is assigned to the field - * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - (0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - -/** - * @brief Get the Priority Grouping from NVIC Interrupt Controller - * - * @return priority grouping field - * - * Get the priority grouping from NVIC Interrupt Controller. - * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - -/** - * @brief Enable Interrupt in NVIC Interrupt Controller - * - * @param IRQn The positive number of the external interrupt to enable - * - * Enable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - -/** - * @brief Disable the interrupt line for external interrupt specified - * - * @param IRQn The positive number of the external interrupt to disable - * - * Disable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - -/** - * @brief Read the interrupt pending bit for a device specific interrupt source - * - * @param IRQn The number of the device specifc interrupt - * @return 1 = interrupt pending, 0 = interrupt not pending - * - * Read the pending register in NVIC and return 1 if its status is pending, - * otherwise it returns 0 - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - -/** - * @brief Set the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for set pending - * - * Set the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - -/** - * @brief Clear the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for clear pending - * - * Clear the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - -/** - * @brief Read the active bit for an external interrupt - * - * @param IRQn The number of the interrupt for read active bit - * @return 1 = interrupt active, 0 = interrupt not active - * - * Read the active register in NVIC and returns 1 if its status is active, - * otherwise it returns 0. - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - -/** - * @brief Set the priority for an interrupt - * - * @param IRQn The number of the interrupt for set priority - * @param priority The priority to set - * - * Set the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - -/** - * @brief Read the priority for an interrupt - * - * @param IRQn The number of the interrupt for get priority - * @return The priority for the interrupt - * - * Read the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * The returned priority value is automatically aligned to the implemented - * priority bits of the microcontroller. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** - * @brief Encode the priority for an interrupt - * - * @param PriorityGroup The used priority group - * @param PreemptPriority The preemptive priority value (starting from 0) - * @param SubPriority The sub priority value (starting from 0) - * @return The encoded priority for the interrupt - * - * Encode the priority for an interrupt with the given priority group, - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The returned priority value can be used for NVIC_SetPriority(...) function - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** - * @brief Decode the priority of an interrupt - * - * @param Priority The priority for the interrupt - * @param PriorityGroup The used priority group - * @param pPreemptPriority The preemptive priority value (starting from 0) - * @param pSubPriority The sub priority value (starting from 0) - * - * Decode an interrupt priority value with the given priority group to - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The priority value can be retrieved with NVIC_GetPriority(...) function - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - - -/* ################################## SysTick function ############################################ */ - -#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) - -/** - * @brief Initialize and start the SysTick counter and its interrupt. - * - * @param ticks number of ticks between two interrupts - * @return 1 = failed, 0 = successful - * - * Initialise the system tick timer and its interrupt and start the - * system tick timer / counter in free running mode to generate - * periodical interrupts. - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - - - - -/* ################################## Reset function ############################################ */ - -/** - * @brief Initiate a system reset request. - * - * Initiate a system reset request to reset the MCU - */ -static __INLINE void NVIC_SystemReset(void) -{ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ - - - -/* ##################################### Debug In/Output function ########################################### */ - -/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface - Core Debug Interface containing: - - Core Debug Receive / Transmit Functions - - Core Debug Defines - - Core Debug Variables -*/ -/*@{*/ - -extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** - * @brief Outputs a character via the ITM channel 0 - * - * @param ch character to output - * @return character to output - * - * The function outputs a character via the ITM channel 0. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** - * @brief Inputs a character via variable ITM_RxBuffer - * - * @return received character, -1 = no character received - * - * The function inputs a character via variable ITM_RxBuffer. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE int ITM_ReceiveChar (void) { - int ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - * @brief Check if a character via variable ITM_RxBuffer is available - * - * @return 1 = character available, 0 = no character available - * - * The function checks variable ITM_RxBuffer whether a character is available or not. - * The function returns '1' if a character is available and '0' if no character is available. - */ -static __INLINE int ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_definitions */ - -#endif /* __CM3_CORE_H__ */ - -/*lint -restore */ diff --git a/bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/LPC17xx.h b/bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/LPC17xx.h deleted file mode 100644 index 0e485ee985e..00000000000 --- a/bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/LPC17xx.h +++ /dev/null @@ -1,1028 +0,0 @@ -/**************************************************************************//** - * @file LPC17xx.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for - * NXP LPC17xx Device Series - * @version V1.07 - * @date 19. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __LPC17xx_H__ -#define __LPC17xx_H__ - -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ - -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** LPC17xx Specific Interrupt Numbers *******************************************************/ - WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ - TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ - TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ - TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ - TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ - UART0_IRQn = 5, /*!< UART0 Interrupt */ - UART1_IRQn = 6, /*!< UART1 Interrupt */ - UART2_IRQn = 7, /*!< UART2 Interrupt */ - UART3_IRQn = 8, /*!< UART3 Interrupt */ - PWM1_IRQn = 9, /*!< PWM1 Interrupt */ - I2C0_IRQn = 10, /*!< I2C0 Interrupt */ - I2C1_IRQn = 11, /*!< I2C1 Interrupt */ - I2C2_IRQn = 12, /*!< I2C2 Interrupt */ - SPI_IRQn = 13, /*!< SPI Interrupt */ - SSP0_IRQn = 14, /*!< SSP0 Interrupt */ - SSP1_IRQn = 15, /*!< SSP1 Interrupt */ - PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ - RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ - EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ - EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ - EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ - EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ - ADC_IRQn = 22, /*!< A/D Converter Interrupt */ - BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ - USB_IRQn = 24, /*!< USB Interrupt */ - CAN_IRQn = 25, /*!< CAN Interrupt */ - DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ - I2S_IRQn = 27, /*!< I2S Interrupt */ - ENET_IRQn = 28, /*!< Ethernet Interrupt */ - RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */ - MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ - QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ - PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ -} IRQn_Type; - - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/* Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - - -#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ -#include "system_LPC17xx.h" /* System Header */ - - -/******************************************************************************/ -/* Device Specific Peripheral registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/*------------- System Control (SC) ------------------------------------------*/ -typedef struct -{ - __IO uint32_t FLASHCFG; /* Flash Accelerator Module */ - uint32_t RESERVED0[31]; - __IO uint32_t PLL0CON; /* Clocking and Power Control */ - __IO uint32_t PLL0CFG; - __I uint32_t PLL0STAT; - __O uint32_t PLL0FEED; - uint32_t RESERVED1[4]; - __IO uint32_t PLL1CON; - __IO uint32_t PLL1CFG; - __I uint32_t PLL1STAT; - __O uint32_t PLL1FEED; - uint32_t RESERVED2[4]; - __IO uint32_t PCON; - __IO uint32_t PCONP; - uint32_t RESERVED3[15]; - __IO uint32_t CCLKCFG; - __IO uint32_t USBCLKCFG; - __IO uint32_t CLKSRCSEL; - uint32_t RESERVED4[12]; - __IO uint32_t EXTINT; /* External Interrupts */ - uint32_t RESERVED5; - __IO uint32_t EXTMODE; - __IO uint32_t EXTPOLAR; - uint32_t RESERVED6[12]; - __IO uint32_t RSID; /* Reset */ - uint32_t RESERVED7[7]; - __IO uint32_t SCS; /* Syscon Miscellaneous Registers */ - __IO uint32_t IRCTRIM; /* Clock Dividers */ - __IO uint32_t PCLKSEL0; - __IO uint32_t PCLKSEL1; - uint32_t RESERVED8[4]; - __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */ - __IO uint32_t DMAREQSEL; - __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */ - } LPC_SC_TypeDef; - -/*------------- Pin Connect Block (PINCON) -----------------------------------*/ -typedef struct -{ - __IO uint32_t PINSEL0; - __IO uint32_t PINSEL1; - __IO uint32_t PINSEL2; - __IO uint32_t PINSEL3; - __IO uint32_t PINSEL4; - __IO uint32_t PINSEL5; - __IO uint32_t PINSEL6; - __IO uint32_t PINSEL7; - __IO uint32_t PINSEL8; - __IO uint32_t PINSEL9; - __IO uint32_t PINSEL10; - uint32_t RESERVED0[5]; - __IO uint32_t PINMODE0; - __IO uint32_t PINMODE1; - __IO uint32_t PINMODE2; - __IO uint32_t PINMODE3; - __IO uint32_t PINMODE4; - __IO uint32_t PINMODE5; - __IO uint32_t PINMODE6; - __IO uint32_t PINMODE7; - __IO uint32_t PINMODE8; - __IO uint32_t PINMODE9; - __IO uint32_t PINMODE_OD0; - __IO uint32_t PINMODE_OD1; - __IO uint32_t PINMODE_OD2; - __IO uint32_t PINMODE_OD3; - __IO uint32_t PINMODE_OD4; - __IO uint32_t I2CPADCFG; -} LPC_PINCON_TypeDef; - -/*------------- General Purpose Input/Output (GPIO) --------------------------*/ -typedef struct -{ - union { - __IO uint32_t FIODIR; - struct { - __IO uint16_t FIODIRL; - __IO uint16_t FIODIRH; - }; - struct { - __IO uint8_t FIODIR0; - __IO uint8_t FIODIR1; - __IO uint8_t FIODIR2; - __IO uint8_t FIODIR3; - }; - }; - uint32_t RESERVED0[3]; - union { - __IO uint32_t FIOMASK; - struct { - __IO uint16_t FIOMASKL; - __IO uint16_t FIOMASKH; - }; - struct { - __IO uint8_t FIOMASK0; - __IO uint8_t FIOMASK1; - __IO uint8_t FIOMASK2; - __IO uint8_t FIOMASK3; - }; - }; - union { - __IO uint32_t FIOPIN; - struct { - __IO uint16_t FIOPINL; - __IO uint16_t FIOPINH; - }; - struct { - __IO uint8_t FIOPIN0; - __IO uint8_t FIOPIN1; - __IO uint8_t FIOPIN2; - __IO uint8_t FIOPIN3; - }; - }; - union { - __IO uint32_t FIOSET; - struct { - __IO uint16_t FIOSETL; - __IO uint16_t FIOSETH; - }; - struct { - __IO uint8_t FIOSET0; - __IO uint8_t FIOSET1; - __IO uint8_t FIOSET2; - __IO uint8_t FIOSET3; - }; - }; - union { - __O uint32_t FIOCLR; - struct { - __O uint16_t FIOCLRL; - __O uint16_t FIOCLRH; - }; - struct { - __O uint8_t FIOCLR0; - __O uint8_t FIOCLR1; - __O uint8_t FIOCLR2; - __O uint8_t FIOCLR3; - }; - }; -} LPC_GPIO_TypeDef; - -typedef struct -{ - __I uint32_t IntStatus; - __I uint32_t IO0IntStatR; - __I uint32_t IO0IntStatF; - __O uint32_t IO0IntClr; - __IO uint32_t IO0IntEnR; - __IO uint32_t IO0IntEnF; - uint32_t RESERVED0[3]; - __I uint32_t IO2IntStatR; - __I uint32_t IO2IntStatF; - __O uint32_t IO2IntClr; - __IO uint32_t IO2IntEnR; - __IO uint32_t IO2IntEnF; -} LPC_GPIOINT_TypeDef; - -/*------------- Timer (TIM) --------------------------------------------------*/ -typedef struct -{ - __IO uint32_t IR; - __IO uint32_t TCR; - __IO uint32_t TC; - __IO uint32_t PR; - __IO uint32_t PC; - __IO uint32_t MCR; - __IO uint32_t MR0; - __IO uint32_t MR1; - __IO uint32_t MR2; - __IO uint32_t MR3; - __IO uint32_t CCR; - __I uint32_t CR0; - __I uint32_t CR1; - uint32_t RESERVED0[2]; - __IO uint32_t EMR; - uint32_t RESERVED1[12]; - __IO uint32_t CTCR; -} LPC_TIM_TypeDef; - -/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ -typedef struct -{ - __IO uint32_t IR; - __IO uint32_t TCR; - __IO uint32_t TC; - __IO uint32_t PR; - __IO uint32_t PC; - __IO uint32_t MCR; - __IO uint32_t MR0; - __IO uint32_t MR1; - __IO uint32_t MR2; - __IO uint32_t MR3; - __IO uint32_t CCR; - __I uint32_t CR0; - __I uint32_t CR1; - __I uint32_t CR2; - __I uint32_t CR3; - uint32_t RESERVED0; - __IO uint32_t MR4; - __IO uint32_t MR5; - __IO uint32_t MR6; - __IO uint32_t PCR; - __IO uint32_t LER; - uint32_t RESERVED1[7]; - __IO uint32_t CTCR; -} LPC_PWM_TypeDef; - -/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[7]; - __I uint8_t LSR; - uint8_t RESERVED2[7]; - __IO uint8_t SCR; - uint8_t RESERVED3[3]; - __IO uint32_t ACR; - __IO uint8_t ICR; - uint8_t RESERVED4[3]; - __IO uint8_t FDR; - uint8_t RESERVED5[7]; - __IO uint8_t TER; - uint8_t RESERVED6[39]; - __I uint8_t FIFOLVL; -} LPC_UART_TypeDef; - -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[7]; - __I uint8_t LSR; - uint8_t RESERVED2[7]; - __IO uint8_t SCR; - uint8_t RESERVED3[3]; - __IO uint32_t ACR; - __IO uint8_t ICR; - uint8_t RESERVED4[3]; - __IO uint8_t FDR; - uint8_t RESERVED5[7]; - __IO uint8_t TER; - uint8_t RESERVED6[39]; - __I uint8_t FIFOLVL; -} LPC_UART0_TypeDef; - -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[3]; - __IO uint8_t MCR; - uint8_t RESERVED2[3]; - __I uint8_t LSR; - uint8_t RESERVED3[3]; - __I uint8_t MSR; - uint8_t RESERVED4[3]; - __IO uint8_t SCR; - uint8_t RESERVED5[3]; - __IO uint32_t ACR; - uint32_t RESERVED6; - __IO uint32_t FDR; - uint32_t RESERVED7; - __IO uint8_t TER; - uint8_t RESERVED8[27]; - __IO uint8_t RS485CTRL; - uint8_t RESERVED9[3]; - __IO uint8_t ADRMATCH; - uint8_t RESERVED10[3]; - __IO uint8_t RS485DLY; - uint8_t RESERVED11[3]; - __I uint8_t FIFOLVL; -} LPC_UART1_TypeDef; - -/*------------- Serial Peripheral Interface (SPI) ----------------------------*/ -typedef struct -{ - __IO uint32_t SPCR; - __I uint32_t SPSR; - __IO uint32_t SPDR; - __IO uint32_t SPCCR; - uint32_t RESERVED0[3]; - __IO uint32_t SPINT; -} LPC_SPI_TypeDef; - -/*------------- Synchronous Serial Communication (SSP) -----------------------*/ -typedef struct -{ - __IO uint32_t CR0; - __IO uint32_t CR1; - __IO uint32_t DR; - __I uint32_t SR; - __IO uint32_t CPSR; - __IO uint32_t IMSC; - __IO uint32_t RIS; - __IO uint32_t MIS; - __IO uint32_t ICR; - __IO uint32_t DMACR; -} LPC_SSP_TypeDef; - -/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ -typedef struct -{ - __IO uint32_t I2CONSET; - __I uint32_t I2STAT; - __IO uint32_t I2DAT; - __IO uint32_t I2ADR0; - __IO uint32_t I2SCLH; - __IO uint32_t I2SCLL; - __O uint32_t I2CONCLR; - __IO uint32_t MMCTRL; - __IO uint32_t I2ADR1; - __IO uint32_t I2ADR2; - __IO uint32_t I2ADR3; - __I uint32_t I2DATA_BUFFER; - __IO uint32_t I2MASK0; - __IO uint32_t I2MASK1; - __IO uint32_t I2MASK2; - __IO uint32_t I2MASK3; -} LPC_I2C_TypeDef; - -/*------------- Inter IC Sound (I2S) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t I2SDAO; - __IO uint32_t I2SDAI; - __O uint32_t I2STXFIFO; - __I uint32_t I2SRXFIFO; - __I uint32_t I2SSTATE; - __IO uint32_t I2SDMA1; - __IO uint32_t I2SDMA2; - __IO uint32_t I2SIRQ; - __IO uint32_t I2STXRATE; - __IO uint32_t I2SRXRATE; - __IO uint32_t I2STXBITRATE; - __IO uint32_t I2SRXBITRATE; - __IO uint32_t I2STXMODE; - __IO uint32_t I2SRXMODE; -} LPC_I2S_TypeDef; - -/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/ -typedef struct -{ - __IO uint32_t RICOMPVAL; - __IO uint32_t RIMASK; - __IO uint8_t RICTRL; - uint8_t RESERVED0[3]; - __IO uint32_t RICOUNTER; -} LPC_RIT_TypeDef; - -/*------------- Real-Time Clock (RTC) ----------------------------------------*/ -typedef struct -{ - __IO uint8_t ILR; - uint8_t RESERVED0[7]; - __IO uint8_t CCR; - uint8_t RESERVED1[3]; - __IO uint8_t CIIR; - uint8_t RESERVED2[3]; - __IO uint8_t AMR; - uint8_t RESERVED3[3]; - __I uint32_t CTIME0; - __I uint32_t CTIME1; - __I uint32_t CTIME2; - __IO uint8_t SEC; - uint8_t RESERVED4[3]; - __IO uint8_t MIN; - uint8_t RESERVED5[3]; - __IO uint8_t HOUR; - uint8_t RESERVED6[3]; - __IO uint8_t DOM; - uint8_t RESERVED7[3]; - __IO uint8_t DOW; - uint8_t RESERVED8[3]; - __IO uint16_t DOY; - uint16_t RESERVED9; - __IO uint8_t MONTH; - uint8_t RESERVED10[3]; - __IO uint16_t YEAR; - uint16_t RESERVED11; - __IO uint32_t CALIBRATION; - __IO uint32_t GPREG0; - __IO uint32_t GPREG1; - __IO uint32_t GPREG2; - __IO uint32_t GPREG3; - __IO uint32_t GPREG4; - __IO uint8_t RTC_AUXEN; - uint8_t RESERVED12[3]; - __IO uint8_t RTC_AUX; - uint8_t RESERVED13[3]; - __IO uint8_t ALSEC; - uint8_t RESERVED14[3]; - __IO uint8_t ALMIN; - uint8_t RESERVED15[3]; - __IO uint8_t ALHOUR; - uint8_t RESERVED16[3]; - __IO uint8_t ALDOM; - uint8_t RESERVED17[3]; - __IO uint8_t ALDOW; - uint8_t RESERVED18[3]; - __IO uint16_t ALDOY; - uint16_t RESERVED19; - __IO uint8_t ALMON; - uint8_t RESERVED20[3]; - __IO uint16_t ALYEAR; - uint16_t RESERVED21; -} LPC_RTC_TypeDef; - -/*------------- Watchdog Timer (WDT) -----------------------------------------*/ -typedef struct -{ - __IO uint8_t WDMOD; - uint8_t RESERVED0[3]; - __IO uint32_t WDTC; - __O uint8_t WDFEED; - uint8_t RESERVED1[3]; - __I uint32_t WDTV; - __IO uint32_t WDCLKSEL; -} LPC_WDT_TypeDef; - -/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ -typedef struct -{ - __IO uint32_t ADCR; - __IO uint32_t ADGDR; - uint32_t RESERVED0; - __IO uint32_t ADINTEN; - __I uint32_t ADDR0; - __I uint32_t ADDR1; - __I uint32_t ADDR2; - __I uint32_t ADDR3; - __I uint32_t ADDR4; - __I uint32_t ADDR5; - __I uint32_t ADDR6; - __I uint32_t ADDR7; - __I uint32_t ADSTAT; - __IO uint32_t ADTRM; -} LPC_ADC_TypeDef; - -/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ -typedef struct -{ - __IO uint32_t DACR; - __IO uint32_t DACCTRL; - __IO uint16_t DACCNTVAL; -} LPC_DAC_TypeDef; - -/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ -typedef struct -{ - __I uint32_t MCCON; - __O uint32_t MCCON_SET; - __O uint32_t MCCON_CLR; - __I uint32_t MCCAPCON; - __O uint32_t MCCAPCON_SET; - __O uint32_t MCCAPCON_CLR; - __IO uint32_t MCTIM0; - __IO uint32_t MCTIM1; - __IO uint32_t MCTIM2; - __IO uint32_t MCPER0; - __IO uint32_t MCPER1; - __IO uint32_t MCPER2; - __IO uint32_t MCPW0; - __IO uint32_t MCPW1; - __IO uint32_t MCPW2; - __IO uint32_t MCDEADTIME; - __IO uint32_t MCCCP; - __IO uint32_t MCCR0; - __IO uint32_t MCCR1; - __IO uint32_t MCCR2; - __I uint32_t MCINTEN; - __O uint32_t MCINTEN_SET; - __O uint32_t MCINTEN_CLR; - __I uint32_t MCCNTCON; - __O uint32_t MCCNTCON_SET; - __O uint32_t MCCNTCON_CLR; - __I uint32_t MCINTFLAG; - __O uint32_t MCINTFLAG_SET; - __O uint32_t MCINTFLAG_CLR; - __O uint32_t MCCAP_CLR; -} LPC_MCPWM_TypeDef; - -/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ -typedef struct -{ - __O uint32_t QEICON; - __I uint32_t QEISTAT; - __IO uint32_t QEICONF; - __I uint32_t QEIPOS; - __IO uint32_t QEIMAXPOS; - __IO uint32_t CMPOS0; - __IO uint32_t CMPOS1; - __IO uint32_t CMPOS2; - __I uint32_t INXCNT; - __IO uint32_t INXCMP; - __IO uint32_t QEILOAD; - __I uint32_t QEITIME; - __I uint32_t QEIVEL; - __I uint32_t QEICAP; - __IO uint32_t VELCOMP; - __IO uint32_t FILTER; - uint32_t RESERVED0[998]; - __O uint32_t QEIIEC; - __O uint32_t QEIIES; - __I uint32_t QEIINTSTAT; - __I uint32_t QEIIE; - __O uint32_t QEICLR; - __O uint32_t QEISET; -} LPC_QEI_TypeDef; - -/*------------- Controller Area Network (CAN) --------------------------------*/ -typedef struct -{ - __IO uint32_t mask[512]; /* ID Masks */ -} LPC_CANAF_RAM_TypeDef; - -typedef struct /* Acceptance Filter Registers */ -{ - __IO uint32_t AFMR; - __IO uint32_t SFF_sa; - __IO uint32_t SFF_GRP_sa; - __IO uint32_t EFF_sa; - __IO uint32_t EFF_GRP_sa; - __IO uint32_t ENDofTable; - __I uint32_t LUTerrAd; - __I uint32_t LUTerr; - __IO uint32_t FCANIE; - __IO uint32_t FCANIC0; - __IO uint32_t FCANIC1; -} LPC_CANAF_TypeDef; - -typedef struct /* Central Registers */ -{ - __I uint32_t CANTxSR; - __I uint32_t CANRxSR; - __I uint32_t CANMSR; -} LPC_CANCR_TypeDef; - -typedef struct /* Controller Registers */ -{ - __IO uint32_t MOD; - __O uint32_t CMR; - __IO uint32_t GSR; - __I uint32_t ICR; - __IO uint32_t IER; - __IO uint32_t BTR; - __IO uint32_t EWL; - __I uint32_t SR; - __IO uint32_t RFS; - __IO uint32_t RID; - __IO uint32_t RDA; - __IO uint32_t RDB; - __IO uint32_t TFI1; - __IO uint32_t TID1; - __IO uint32_t TDA1; - __IO uint32_t TDB1; - __IO uint32_t TFI2; - __IO uint32_t TID2; - __IO uint32_t TDA2; - __IO uint32_t TDB2; - __IO uint32_t TFI3; - __IO uint32_t TID3; - __IO uint32_t TDA3; - __IO uint32_t TDB3; -} LPC_CAN_TypeDef; - -/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ -typedef struct /* Common Registers */ -{ - __I uint32_t DMACIntStat; - __I uint32_t DMACIntTCStat; - __O uint32_t DMACIntTCClear; - __I uint32_t DMACIntErrStat; - __O uint32_t DMACIntErrClr; - __I uint32_t DMACRawIntTCStat; - __I uint32_t DMACRawIntErrStat; - __I uint32_t DMACEnbldChns; - __IO uint32_t DMACSoftBReq; - __IO uint32_t DMACSoftSReq; - __IO uint32_t DMACSoftLBReq; - __IO uint32_t DMACSoftLSReq; - __IO uint32_t DMACConfig; - __IO uint32_t DMACSync; -} LPC_GPDMA_TypeDef; - -typedef struct /* Channel Registers */ -{ - __IO uint32_t DMACCSrcAddr; - __IO uint32_t DMACCDestAddr; - __IO uint32_t DMACCLLI; - __IO uint32_t DMACCControl; - __IO uint32_t DMACCConfig; -} LPC_GPDMACH_TypeDef; - -/*------------- Universal Serial Bus (USB) -----------------------------------*/ -typedef struct -{ - __I uint32_t HcRevision; /* USB Host Registers */ - __IO uint32_t HcControl; - __IO uint32_t HcCommandStatus; - __IO uint32_t HcInterruptStatus; - __IO uint32_t HcInterruptEnable; - __IO uint32_t HcInterruptDisable; - __IO uint32_t HcHCCA; - __I uint32_t HcPeriodCurrentED; - __IO uint32_t HcControlHeadED; - __IO uint32_t HcControlCurrentED; - __IO uint32_t HcBulkHeadED; - __IO uint32_t HcBulkCurrentED; - __I uint32_t HcDoneHead; - __IO uint32_t HcFmInterval; - __I uint32_t HcFmRemaining; - __I uint32_t HcFmNumber; - __IO uint32_t HcPeriodicStart; - __IO uint32_t HcLSTreshold; - __IO uint32_t HcRhDescriptorA; - __IO uint32_t HcRhDescriptorB; - __IO uint32_t HcRhStatus; - __IO uint32_t HcRhPortStatus1; - __IO uint32_t HcRhPortStatus2; - uint32_t RESERVED0[40]; - __I uint32_t Module_ID; - - __I uint32_t OTGIntSt; /* USB On-The-Go Registers */ - __IO uint32_t OTGIntEn; - __O uint32_t OTGIntSet; - __O uint32_t OTGIntClr; - __IO uint32_t OTGStCtrl; - __IO uint32_t OTGTmr; - uint32_t RESERVED1[58]; - - __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */ - __IO uint32_t USBDevIntEn; - __O uint32_t USBDevIntClr; - __O uint32_t USBDevIntSet; - - __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */ - __I uint32_t USBCmdData; - - __I uint32_t USBRxData; /* USB Device Transfer Registers */ - __O uint32_t USBTxData; - __I uint32_t USBRxPLen; - __O uint32_t USBTxPLen; - __IO uint32_t USBCtrl; - __O uint32_t USBDevIntPri; - - __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */ - __IO uint32_t USBEpIntEn; - __O uint32_t USBEpIntClr; - __O uint32_t USBEpIntSet; - __O uint32_t USBEpIntPri; - - __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/ - __O uint32_t USBEpInd; - __IO uint32_t USBMaxPSize; - - __I uint32_t USBDMARSt; /* USB Device DMA Registers */ - __O uint32_t USBDMARClr; - __O uint32_t USBDMARSet; - uint32_t RESERVED2[9]; - __IO uint32_t USBUDCAH; - __I uint32_t USBEpDMASt; - __O uint32_t USBEpDMAEn; - __O uint32_t USBEpDMADis; - __I uint32_t USBDMAIntSt; - __IO uint32_t USBDMAIntEn; - uint32_t RESERVED3[2]; - __I uint32_t USBEoTIntSt; - __O uint32_t USBEoTIntClr; - __O uint32_t USBEoTIntSet; - __I uint32_t USBNDDRIntSt; - __O uint32_t USBNDDRIntClr; - __O uint32_t USBNDDRIntSet; - __I uint32_t USBSysErrIntSt; - __O uint32_t USBSysErrIntClr; - __O uint32_t USBSysErrIntSet; - uint32_t RESERVED4[15]; - - __I uint32_t I2C_RX; /* USB OTG I2C Registers */ - __O uint32_t I2C_WO; - __I uint32_t I2C_STS; - __IO uint32_t I2C_CTL; - __IO uint32_t I2C_CLKHI; - __O uint32_t I2C_CLKLO; - uint32_t RESERVED5[823]; - - union { - __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ - __IO uint32_t OTGClkCtrl; - }; - union { - __I uint32_t USBClkSt; - __I uint32_t OTGClkSt; - }; -} LPC_USB_TypeDef; - -/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ -typedef struct -{ - __IO uint32_t MAC1; /* MAC Registers */ - __IO uint32_t MAC2; - __IO uint32_t IPGT; - __IO uint32_t IPGR; - __IO uint32_t CLRT; - __IO uint32_t MAXF; - __IO uint32_t SUPP; - __IO uint32_t TEST; - __IO uint32_t MCFG; - __IO uint32_t MCMD; - __IO uint32_t MADR; - __O uint32_t MWTD; - __I uint32_t MRDD; - __I uint32_t MIND; - uint32_t RESERVED0[2]; - __IO uint32_t SA0; - __IO uint32_t SA1; - __IO uint32_t SA2; - uint32_t RESERVED1[45]; - __IO uint32_t Command; /* Control Registers */ - __I uint32_t Status; - __IO uint32_t RxDescriptor; - __IO uint32_t RxStatus; - __IO uint32_t RxDescriptorNumber; - __I uint32_t RxProduceIndex; - __IO uint32_t RxConsumeIndex; - __IO uint32_t TxDescriptor; - __IO uint32_t TxStatus; - __IO uint32_t TxDescriptorNumber; - __IO uint32_t TxProduceIndex; - __I uint32_t TxConsumeIndex; - uint32_t RESERVED2[10]; - __I uint32_t TSV0; - __I uint32_t TSV1; - __I uint32_t RSV; - uint32_t RESERVED3[3]; - __IO uint32_t FlowControlCounter; - __I uint32_t FlowControlStatus; - uint32_t RESERVED4[34]; - __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ - __IO uint32_t RxFilterWoLStatus; - __IO uint32_t RxFilterWoLClear; - uint32_t RESERVED5; - __IO uint32_t HashFilterL; - __IO uint32_t HashFilterH; - uint32_t RESERVED6[882]; - __I uint32_t IntStatus; /* Module Control Registers */ - __IO uint32_t IntEnable; - __O uint32_t IntClear; - __O uint32_t IntSet; - uint32_t RESERVED7; - __IO uint32_t PowerDown; - uint32_t RESERVED8; - __IO uint32_t Module_ID; -} LPC_EMAC_TypeDef; - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* Base addresses */ -#define LPC_FLASH_BASE (0x00000000UL) -#define LPC_RAM_BASE (0x10000000UL) -#define LPC_GPIO_BASE (0x2009C000UL) -#define LPC_APB0_BASE (0x40000000UL) -#define LPC_APB1_BASE (0x40080000UL) -#define LPC_AHB_BASE (0x50000000UL) -#define LPC_CM3_BASE (0xE0000000UL) - -/* APB0 peripherals */ -#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) -#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) -#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) -#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) -#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) -#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) -#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) -#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000) -#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) -#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) -#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000) -#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) -#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) -#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) -#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) -#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) -#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) -#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) -#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) - -/* APB1 peripherals */ -#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) -#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) -#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) -#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) -#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) -#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) -#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) -#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) -#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000) -#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) -#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) -#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) - -/* AHB peripherals */ -#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000) -#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100) -#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120) -#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140) -#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160) -#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180) -#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0) -#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0) -#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0) -#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) - -/* GPIOs */ -#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000) -#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020) -#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040) -#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060) -#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080) - - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) -#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) -#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) -#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) -#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) -#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) -#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) -#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) -#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) -#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) -#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) -#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE ) -#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE ) -#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) -#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) -#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) -#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) -#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) -#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) -#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) -#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) -#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE ) -#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) -#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) -#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE ) -#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) -#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) -#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) -#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) -#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) -#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) -#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) -#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) -#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) -#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) -#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) -#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) -#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) -#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) -#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) -#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) -#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) -#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) -#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) -#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) -#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) -#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) - -#endif // __LPC17xx_H__ diff --git a/bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/arm/startup_LPC17xx.s b/bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/arm/startup_LPC17xx.s deleted file mode 100644 index 66f95d3ba0c..00000000000 --- a/bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/arm/startup_LPC17xx.s +++ /dev/null @@ -1,277 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC17xx.s -; * @purpose: CMSIS Cortex-M3 Core Device Startup File -; * for the NXP LPC17xx Device Series -; * @version: V1.02 -; * @date: 27. July 2009 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2009 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000200 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WDT_IRQHandler ; 16: Watchdog Timer - DCD TIMER0_IRQHandler ; 17: Timer0 - DCD TIMER1_IRQHandler ; 18: Timer1 - DCD TIMER2_IRQHandler ; 19: Timer2 - DCD TIMER3_IRQHandler ; 20: Timer3 - DCD UART0_IRQHandler ; 21: UART0 - DCD UART1_IRQHandler ; 22: UART1 - DCD UART2_IRQHandler ; 23: UART2 - DCD UART3_IRQHandler ; 24: UART3 - DCD PWM1_IRQHandler ; 25: PWM1 - DCD I2C0_IRQHandler ; 26: I2C0 - DCD I2C1_IRQHandler ; 27: I2C1 - DCD I2C2_IRQHandler ; 28: I2C2 - DCD SPI_IRQHandler ; 29: SPI - DCD SSP0_IRQHandler ; 30: SSP0 - DCD SSP1_IRQHandler ; 31: SSP1 - DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL) - DCD RTC_IRQHandler ; 33: Real Time Clock - DCD EINT0_IRQHandler ; 34: External Interrupt 0 - DCD EINT1_IRQHandler ; 35: External Interrupt 1 - DCD EINT2_IRQHandler ; 36: External Interrupt 2 - DCD EINT3_IRQHandler ; 37: External Interrupt 3 - DCD ADC_IRQHandler ; 38: A/D Converter - DCD BOD_IRQHandler ; 39: Brown-Out Detect - DCD USB_IRQHandler ; 40: USB - DCD CAN_IRQHandler ; 41: CAN - DCD DMA_IRQHandler ; 42: General Purpose DMA - DCD I2S_IRQHandler ; 43: I2S - DCD ENET_IRQHandler ; 44: Ethernet - DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer - DCD MCPWM_IRQHandler ; 46: Motor Control PWM - DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface - DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) - - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WDT_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT PWM1_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - EXPORT SPI_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT PLL0_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT EINT0_IRQHandler [WEAK] - EXPORT EINT1_IRQHandler [WEAK] - EXPORT EINT2_IRQHandler [WEAK] - EXPORT EINT3_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT USB_IRQHandler [WEAK] - EXPORT CAN_IRQHandler [WEAK] - EXPORT DMA_IRQHandler [WEAK] - EXPORT I2S_IRQHandler [WEAK] - EXPORT ENET_IRQHandler [WEAK] - EXPORT RIT_IRQHandler [WEAK] - EXPORT MCPWM_IRQHandler [WEAK] - EXPORT QEI_IRQHandler [WEAK] - EXPORT PLL1_IRQHandler [WEAK] - -WDT_IRQHandler -TIMER0_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -UART3_IRQHandler -PWM1_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -I2C2_IRQHandler -SPI_IRQHandler -SSP0_IRQHandler -SSP1_IRQHandler -PLL0_IRQHandler -RTC_IRQHandler -EINT0_IRQHandler -EINT1_IRQHandler -EINT2_IRQHandler -EINT3_IRQHandler -ADC_IRQHandler -BOD_IRQHandler -USB_IRQHandler -CAN_IRQHandler -DMA_IRQHandler -I2S_IRQHandler -ENET_IRQHandler -RIT_IRQHandler -MCPWM_IRQHandler -QEI_IRQHandler -PLL1_IRQHandler - - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - - END diff --git a/bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/gcc/startup_LPC17xx.s b/bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/gcc/startup_LPC17xx.s deleted file mode 100644 index 799ba66d50c..00000000000 --- a/bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/gcc/startup_LPC17xx.s +++ /dev/null @@ -1,228 +0,0 @@ -/** - * startup_LPC17xx.s - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - - .word _sidata - .word _sdata - .word _edata - .word _sbss - .word _ebss - -/* Vector Table */ - - .section ".interrupt_vector" - .globl __interrupt_vector - .type __interrupt_vector, %object - -__interrupt_vector: - .long _estack /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External Interrupts */ - .long WDT_IRQHandler /* 16: Watchdog Timer */ - .long TIMER0_IRQHandler /* 17: Timer0 */ - .long TIMER1_IRQHandler /* 18: Timer1 */ - .long TIMER2_IRQHandler /* 19: Timer2 */ - .long TIMER3_IRQHandler /* 20: Timer3 */ - .long UART0_IRQHandler /* 21: UART0 */ - .long UART1_IRQHandler /* 22: UART1 */ - .long UART2_IRQHandler /* 23: UART2 */ - .long UART3_IRQHandler /* 24: UART3 */ - .long PWM1_IRQHandler /* 25: PWM1 */ - .long I2C0_IRQHandler /* 26: I2C0 */ - .long I2C1_IRQHandler /* 27: I2C1 */ - .long I2C2_IRQHandler /* 28: I2C2 */ - .long SPI_IRQHandler /* 29: SPI */ - .long SSP0_IRQHandler /* 30: SSP0 */ - .long SSP1_IRQHandler /* 31: SSP1 */ - .long PLL0_IRQHandler /* 32: PLL0 Lock (Main PLL) */ - .long RTC_IRQHandler /* 33: Real Time Clock */ - .long EINT0_IRQHandler /* 34: External Interrupt 0 */ - .long EINT1_IRQHandler /* 35: External Interrupt 1 */ - .long EINT2_IRQHandler /* 36: External Interrupt 2 */ - .long EINT3_IRQHandler /* 37: External Interrupt 3 */ - .long ADC_IRQHandler /* 38: A/D Converter */ - .long BOD_IRQHandler /* 39: Brown-Out Detect */ - .long USB_IRQHandler /* 40: USB */ - .long CAN_IRQHandler /* 41: CAN */ - .long DMA_IRQHandler /* 42: General Purpose DMA */ - .long I2S_IRQHandler /* 43: I2S */ - .long ENET_IRQHandler /* 44: Ethernet */ - .long RIT_IRQHandler /* 45: Repetitive Interrupt Timer */ - .long MCPWM_IRQHandler /* 46: Motor Control PWM */ - .long QEI_IRQHandler /* 47: Quadrature Encoder Interface */ - .long PLL1_IRQHandler /* 48: PLL1 Lock (USB PLL) */ - - .size __interrupt_vector, . - __interrupt_vector - -/* Reset Handler */ - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - .fnstart - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - add r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - add r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call the application's entry point.*/ - bl main - bx lr - - .pool - .cantunwind - .fnend - .size Reset_Handler,.-Reset_Handler - - .section ".text" - -/* Exception Handlers */ - - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - B . - .size NMI_Handler, . - NMI_Handler - - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - B . - .size HardFault_Handler, . - HardFault_Handler - - .weak MemManage_Handler - .type MemManage_Handler, %function -MemManage_Handler: - B . - .size MemManage_Handler, . - MemManage_Handler - - .weak BusFault_Handler - .type BusFault_Handler, %function -BusFault_Handler: - B . - .size BusFault_Handler, . - BusFault_Handler - - .weak UsageFault_Handler - .type UsageFault_Handler, %function -UsageFault_Handler: - B . - .size UsageFault_Handler, . - UsageFault_Handler - - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - B . - .size SVC_Handler, . - SVC_Handler - - .weak DebugMon_Handler - .type DebugMon_Handler, %function -DebugMon_Handler: - B . - .size DebugMon_Handler, . - DebugMon_Handler - - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - B . - .size PendSV_Handler, . - PendSV_Handler - - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - B . - .size SysTick_Handler, . - SysTick_Handler - - -/* IRQ Handlers */ - - .globl Default_Handler - .type Default_Handler, %function -Default_Handler: - B . - .size Default_Handler, . - Default_Handler - - .macro IRQ handler - .weak \handler - .set \handler, Default_Handler - .endm - - IRQ WDT_IRQHandler - IRQ TIMER0_IRQHandler - IRQ TIMER1_IRQHandler - IRQ TIMER2_IRQHandler - IRQ TIMER3_IRQHandler - IRQ UART0_IRQHandler - IRQ UART1_IRQHandler - IRQ UART2_IRQHandler - IRQ UART3_IRQHandler - IRQ PWM1_IRQHandler - IRQ I2C0_IRQHandler - IRQ I2C1_IRQHandler - IRQ I2C2_IRQHandler - IRQ SPI_IRQHandler - IRQ SSP0_IRQHandler - IRQ SSP1_IRQHandler - IRQ PLL0_IRQHandler - IRQ RTC_IRQHandler - IRQ EINT0_IRQHandler - IRQ EINT1_IRQHandler - IRQ EINT2_IRQHandler - IRQ EINT3_IRQHandler - IRQ ADC_IRQHandler - IRQ BOD_IRQHandler - IRQ USB_IRQHandler - IRQ CAN_IRQHandler - IRQ DMA_IRQHandler - IRQ I2S_IRQHandler - IRQ ENET_IRQHandler - IRQ RIT_IRQHandler - IRQ MCPWM_IRQHandler - IRQ QEI_IRQHandler - IRQ PLL1_IRQHandler - - .end diff --git a/bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/iar/startup_LPC17xx.s b/bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/iar/startup_LPC17xx.s deleted file mode 100644 index 946c2b6e323..00000000000 --- a/bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/iar/startup_LPC17xx.s +++ /dev/null @@ -1,341 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC17xx.s -; * @purpose: CMSIS Cortex-M3 Core Device Startup File -; * for the NXP LPC17xx Device Series -; * @version: V1.02 -; * @date: 31. July 2009 -; *---------------------------------------------------------------------------- -; * -; * Copyright (C) 2009 ARM Limited. All rights reserved. -; * -; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_IRQHandler ; 16: Watchdog Timer - DCD TIMER0_IRQHandler ; 17: Timer0 - DCD TIMER1_IRQHandler ; 18: Timer1 - DCD TIMER2_IRQHandler ; 19: Timer2 - DCD TIMER3_IRQHandler ; 20: Timer3 - DCD UART0_IRQHandler ; 21: UART0 - DCD UART1_IRQHandler ; 22: UART1 - DCD UART2_IRQHandler ; 23: UART2 - DCD UART3_IRQHandler ; 24: UART3 - DCD PWM1_IRQHandler ; 25: PWM1 - DCD I2C0_IRQHandler ; 26: I2C0 - DCD I2C1_IRQHandler ; 27: I2C1 - DCD I2C2_IRQHandler ; 28: I2C2 - DCD SPI_IRQHandler ; 29: SPI - DCD SSP0_IRQHandler ; 30: SSP0 - DCD SSP1_IRQHandler ; 31: SSP1 - DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL) - DCD RTC_IRQHandler ; 33: Real Time Clock - DCD EINT0_IRQHandler ; 34: External Interrupt 0 - DCD EINT1_IRQHandler ; 35: External Interrupt 1 - DCD EINT2_IRQHandler ; 36: External Interrupt 2 - DCD EINT3_IRQHandler ; 37: External Interrupt 3 - DCD ADC_IRQHandler ; 38: A/D Converter - DCD BOD_IRQHandler ; 39: Brown-Out Detect - DCD USB_IRQHandler ; 40: USB - DCD CAN_IRQHandler ; 41: CAN - DCD DMA_IRQHandler ; 42: General Purpose DMA - DCD I2S_IRQHandler ; 43: I2S - DCD ENET_IRQHandler ; 44: Ethernet - DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer - DCD MCPWM_IRQHandler ; 46: Motor Control PWM - DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface - DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WDT_IRQHandler - SECTION .text:CODE:REORDER(1) -WDT_IRQHandler - B WDT_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:REORDER(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:REORDER(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK UART0_IRQHandler - SECTION .text:CODE:REORDER(1) -UART0_IRQHandler - B UART0_IRQHandler - - PUBWEAK UART1_IRQHandler - SECTION .text:CODE:REORDER(1) -UART1_IRQHandler - B UART1_IRQHandler - - PUBWEAK UART2_IRQHandler - SECTION .text:CODE:REORDER(1) -UART2_IRQHandler - B UART2_IRQHandler - - PUBWEAK UART3_IRQHandler - SECTION .text:CODE:REORDER(1) -UART3_IRQHandler - B UART3_IRQHandler - - PUBWEAK PWM1_IRQHandler - SECTION .text:CODE:REORDER(1) -PWM1_IRQHandler - B PWM1_IRQHandler - - PUBWEAK I2C0_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C0_IRQHandler - B I2C0_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK I2C2_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C2_IRQHandler - B I2C2_IRQHandler - - PUBWEAK SPI_IRQHandler - SECTION .text:CODE:REORDER(1) -SPI_IRQHandler - B SPI_IRQHandler - - PUBWEAK SSP0_IRQHandler - SECTION .text:CODE:REORDER(1) -SSP0_IRQHandler - B SSP0_IRQHandler - - PUBWEAK SSP1_IRQHandler - SECTION .text:CODE:REORDER(1) -SSP1_IRQHandler - B SSP1_IRQHandler - - PUBWEAK PLL0_IRQHandler - SECTION .text:CODE:REORDER(1) -PLL0_IRQHandler - B PLL0_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK EINT0_IRQHandler - SECTION .text:CODE:REORDER(1) -EINT0_IRQHandler - B EINT0_IRQHandler - - PUBWEAK EINT1_IRQHandler - SECTION .text:CODE:REORDER(1) -EINT1_IRQHandler - B EINT1_IRQHandler - - PUBWEAK EINT2_IRQHandler - SECTION .text:CODE:REORDER(1) -EINT2_IRQHandler - B EINT2_IRQHandler - - PUBWEAK EINT3_IRQHandler - SECTION .text:CODE:REORDER(1) -EINT3_IRQHandler - B EINT3_IRQHandler - - PUBWEAK ADC_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC_IRQHandler - B ADC_IRQHandler - - PUBWEAK BOD_IRQHandler - SECTION .text:CODE:REORDER(1) -BOD_IRQHandler - B BOD_IRQHandler - - PUBWEAK USB_IRQHandler - SECTION .text:CODE:REORDER(1) -USB_IRQHandler - B USB_IRQHandler - - PUBWEAK CAN_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN_IRQHandler - B CAN_IRQHandler - - PUBWEAK DMA_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA_IRQHandler - B DMA_IRQHandler - - PUBWEAK I2S_IRQHandler - SECTION .text:CODE:REORDER(1) -I2S_IRQHandler - B I2S_IRQHandler - - PUBWEAK ENET_IRQHandler - SECTION .text:CODE:REORDER(1) -ENET_IRQHandler - B ENET_IRQHandler - - PUBWEAK RIT_IRQHandler - SECTION .text:CODE:REORDER(1) -RIT_IRQHandler - B RIT_IRQHandler - - PUBWEAK MCPWM_IRQHandler - SECTION .text:CODE:REORDER(1) -MCPWM_IRQHandler - B MCPWM_IRQHandler - - PUBWEAK QEI_IRQHandler - SECTION .text:CODE:REORDER(1) -QEI_IRQHandler - B QEI_IRQHandler - - PUBWEAK PLL1_IRQHandler - SECTION .text:CODE:REORDER(1) -PLL1_IRQHandler - B PLL1_IRQHandler - - END diff --git a/bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/system_LPC17xx.c b/bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/system_LPC17xx.c deleted file mode 100644 index f1d93e7712e..00000000000 --- a/bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/system_LPC17xx.c +++ /dev/null @@ -1,539 +0,0 @@ -/**************************************************************************//** - * @file system_LPC17xx.c - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File - * for the NXP LPC17xx Device Series - * @version V1.03 - * @date 07. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#include -#include "LPC17xx.h" - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- Clock Configuration ---------------------------------- -// -// Clock Configuration -// System Controls and Status Register (SCS) -// OSCRANGE: Main Oscillator Range Select -// <0=> 1 MHz to 20 MHz -// <1=> 15 MHz to 24 MHz -// OSCEN: Main Oscillator Enable -// -// -// -// Clock Source Select Register (CLKSRCSEL) -// CLKSRC: PLL Clock Source Selection -// <0=> Internal RC oscillator -// <1=> Main oscillator -// <2=> RTC oscillator -// -// -// PLL0 Configuration (Main PLL) -// PLL0 Configuration Register (PLL0CFG) -// F_cco0 = (2 * M * F_in) / N -// F_in must be in the range of 32 kHz to 50 MHz -// F_cco0 must be in the range of 275 MHz to 550 MHz -// MSEL: PLL Multiplier Selection -// <6-32768><#-1> -// M Value -// NSEL: PLL Divider Selection -// <1-256><#-1> -// N Value -// -// -// -// PLL1 Configuration (USB PLL) -// PLL1 Configuration Register (PLL1CFG) -// F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) -// F_cco1 = F_osc * M * 2 * P -// F_cco1 must be in the range of 156 MHz to 320 MHz -// MSEL: PLL Multiplier Selection -// <1-32><#-1> -// M Value (for USB maximum value is 4) -// PSEL: PLL Divider Selection -// <0=> 1 -// <1=> 2 -// <2=> 4 -// <3=> 8 -// P Value -// -// -// -// CPU Clock Configuration Register (CCLKCFG) -// CCLKSEL: Divide Value for CPU Clock from PLL0 -// <3-256><#-1> -// -// -// USB Clock Configuration Register (USBCLKCFG) -// USBSEL: Divide Value for USB Clock from PLL0 -// <0-15> -// Divide is USBSEL + 1 -// -// -// Peripheral Clock Selection Register 0 (PCLKSEL0) -// PCLK_WDT: Peripheral Clock Selection for WDT -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_TIMER0: Peripheral Clock Selection for TIMER0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_TIMER1: Peripheral Clock Selection for TIMER1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_UART0: Peripheral Clock Selection for UART0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_UART1: Peripheral Clock Selection for UART1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_PWM1: Peripheral Clock Selection for PWM1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_I2C0: Peripheral Clock Selection for I2C0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_SPI: Peripheral Clock Selection for SPI -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_SSP1: Peripheral Clock Selection for SSP1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_DAC: Peripheral Clock Selection for DAC -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_ADC: Peripheral Clock Selection for ADC -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_CAN1: Peripheral Clock Selection for CAN1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 6 -// PCLK_CAN2: Peripheral Clock Selection for CAN2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 6 -// PCLK_ACF: Peripheral Clock Selection for ACF -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 6 -// -// -// Peripheral Clock Selection Register 1 (PCLKSEL1) -// PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_GPIO: Peripheral Clock Selection for GPIOs -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_I2C1: Peripheral Clock Selection for I2C1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_SSP0: Peripheral Clock Selection for SSP0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_TIMER2: Peripheral Clock Selection for TIMER2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_TIMER3: Peripheral Clock Selection for TIMER3 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_UART2: Peripheral Clock Selection for UART2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_UART3: Peripheral Clock Selection for UART3 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_I2C2: Peripheral Clock Selection for I2C2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_I2S: Peripheral Clock Selection for I2S -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_SYSCON: Peripheral Clock Selection for the System Control Block -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_MC: Peripheral Clock Selection for the Motor Control PWM -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// -// -// Power Control for Peripherals Register (PCONP) -// PCTIM0: Timer/Counter 0 power/clock enable -// PCTIM1: Timer/Counter 1 power/clock enable -// PCUART0: UART 0 power/clock enable -// PCUART1: UART 1 power/clock enable -// PCPWM1: PWM 1 power/clock enable -// PCI2C0: I2C interface 0 power/clock enable -// PCSPI: SPI interface power/clock enable -// PCRTC: RTC power/clock enable -// PCSSP1: SSP interface 1 power/clock enable -// PCAD: A/D converter power/clock enable -// PCCAN1: CAN controller 1 power/clock enable -// PCCAN2: CAN controller 2 power/clock enable -// PCGPIO: GPIOs power/clock enable -// PCRIT: Repetitive interrupt timer power/clock enable -// PCMC: Motor control PWM power/clock enable -// PCQEI: Quadrature encoder interface power/clock enable -// PCI2C1: I2C interface 1 power/clock enable -// PCSSP0: SSP interface 0 power/clock enable -// PCTIM2: Timer 2 power/clock enable -// PCTIM3: Timer 3 power/clock enable -// PCUART2: UART 2 power/clock enable -// PCUART3: UART 3 power/clock enable -// PCI2C2: I2C interface 2 power/clock enable -// PCI2S: I2S interface power/clock enable -// PCGPDMA: GP DMA function power/clock enable -// PCENET: Ethernet block power/clock enable -// PCUSB: USB interface power/clock enable -// -// -// Clock Output Configuration Register (CLKOUTCFG) -// CLKOUTSEL: Selects clock source for CLKOUT -// <0=> CPU clock -// <1=> Main oscillator -// <2=> Internal RC oscillator -// <3=> USB clock -// <4=> RTC oscillator -// CLKOUTDIV: Selects clock divider for CLKOUT -// <1-16><#-1> -// CLKOUT_EN: CLKOUT enable control -// -// -// -*/ -#define CLOCK_SETUP 1 -#define SCS_Val 0x00000020 -#define CLKSRCSEL_Val 0x00000001 -#define PLL0_SETUP 1 -#define PLL0CFG_Val 0x00050063 -#define PLL1_SETUP 1 -#define PLL1CFG_Val 0x00000023 -#define CCLKCFG_Val 0x00000003 -#define USBCLKCFG_Val 0x00000000 -#define PCLKSEL0_Val 0x00000000 -#define PCLKSEL1_Val 0x00000000 -#define PCONP_Val 0x042887DE -#define CLKOUTCFG_Val 0x00000000 - - -/*--------------------- Flash Accelerator Configuration ---------------------- -// -// Flash Accelerator Configuration -// FETCHCFG: Fetch Configuration -// <0=> Instruction fetches from flash are not buffered -// <1=> One buffer is used for all instruction fetch buffering -// <2=> All buffers may be used for instruction fetch buffering -// <3=> Reserved (do not use this setting) -// DATACFG: Data Configuration -// <0=> Data accesses from flash are not buffered -// <1=> One buffer is used for all data access buffering -// <2=> All buffers may be used for data access buffering -// <3=> Reserved (do not use this setting) -// ACCEL: Acceleration Enable -// PREFEN: Prefetch Enable -// PREFOVR: Prefetch Override -// FLASHTIM: Flash Access Time -// <0=> 1 CPU clock (for CPU clock up to 20 MHz) -// <1=> 2 CPU clocks (for CPU clock up to 40 MHz) -// <2=> 3 CPU clocks (for CPU clock up to 60 MHz) -// <3=> 4 CPU clocks (for CPU clock up to 80 MHz) -// <4=> 5 CPU clocks (for CPU clock up to 100 MHz) -// <5=> 6 CPU clocks (for any CPU clock) -// -*/ -#define FLASH_SETUP 1 -#define FLASHCFG_Val 0x0000303A - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ - -/*---------------------------------------------------------------------------- - Check the register settings - *----------------------------------------------------------------------------*/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) -#define CHECK_RSVD(val, mask) (val & mask) - -/* Clock Configuration -------------------------------------------------------*/ -#if (CHECK_RSVD((SCS_Val), ~0x00000030)) - #error "SCS: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2)) - #error "CLKSRCSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF)) - #error "PLL0CFG: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) - #error "PLL1CFG: Invalid values of reserved bits!" -#endif - -#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2))) - #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!" -#endif - -#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F)) - #error "USBCLKCFG: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00)) - #error "PCLKSEL0: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300)) - #error "PCLKSEL1: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCONP_Val), 0x10100821)) - #error "PCONP: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) - #error "CLKOUTCFG: Invalid values of reserved bits!" -#endif - -/* Flash Accelerator Configuration -------------------------------------------*/ -#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F)) - #error "FLASHCFG: Invalid values of reserved bits!" -#endif - - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (12000000UL) /* Oscillator frequency */ -#define OSC_CLK ( XTAL) /* Main oscillator frequency */ -#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */ -#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */ - - -/* F_cco0 = (2 * M * F_in) / N */ -#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1) -#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1) -#define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N) -#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1) - -/* Determine core clock frequency according to settings */ - #if (PLL0_SETUP) - #if ((CLKSRCSEL_Val & 0x03) == 1) - #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV) - #elif ((CLKSRCSEL_Val & 0x03) == 2) - #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV) - #else - #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV) - #endif - #else - #if ((CLKSRCSEL_Val & 0x03) == 1) - #define __CORE_CLK (OSC_CLK / __CCLK_DIV) - #elif ((CLKSRCSEL_Val & 0x03) == 2) - #define __CORE_CLK (RTC_CLK / __CCLK_DIV) - #else - #define __CORE_CLK (IRC_OSC / __CCLK_DIV) - #endif - #endif - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ - - -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ - /* Determine clock frequency according to clock register values */ - if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */ - switch (LPC_SC->CLKSRCSEL & 0x03) { - case 0: /* Int. RC oscillator => PLL0 */ - case 3: /* Reserved, default to Int. RC */ - SystemCoreClock = (IRC_OSC * - ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / - ((LPC_SC->CCLKCFG & 0xFF)+ 1)); - break; - case 1: /* Main oscillator => PLL0 */ - SystemCoreClock = (OSC_CLK * - ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / - ((LPC_SC->CCLKCFG & 0xFF)+ 1)); - break; - case 2: /* RTC oscillator => PLL0 */ - SystemCoreClock = (RTC_CLK * - ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / - ((LPC_SC->CCLKCFG & 0xFF)+ 1)); - break; - } - } else { - switch (LPC_SC->CLKSRCSEL & 0x03) { - case 0: /* Int. RC oscillator => PLL0 */ - case 3: /* Reserved, default to Int. RC */ - SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1); - break; - case 1: /* Main oscillator => PLL0 */ - SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); - break; - case 2: /* RTC oscillator => PLL0 */ - SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); - break; - } - } - -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) -{ -#if (CLOCK_SETUP) /* Clock Setup */ - LPC_SC->SCS = SCS_Val; - if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ - while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ - } - - LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */ - -#if (PLL0_SETUP) - LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */ - - LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - - LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */ - - LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */ -#endif - -#if (PLL1_SETUP) - LPC_SC->PLL1CFG = PLL1CFG_Val; - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - - LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ - - LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */ - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */ -#else - LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */ -#endif - - LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */ - LPC_SC->PCLKSEL1 = PCLKSEL1_Val; - - LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ - - LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ -#endif - -#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ - LPC_SC->FLASHCFG = FLASHCFG_Val; -#endif -} diff --git a/bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/system_LPC17xx.h b/bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/system_LPC17xx.h deleted file mode 100644 index d72cb509e04..00000000000 --- a/bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/system_LPC17xx.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************//** - * @file system_LPC17xx.h - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File - * for the NXP LPC17xx Device Series - * @version V1.02 - * @date 08. September 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __SYSTEM_LPC17xx_H -#define __SYSTEM_LPC17xx_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC17xx_H */ diff --git a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/arm_common_tables.h b/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/arm_common_tables.h deleted file mode 100644 index 7a59b5923e9..00000000000 --- a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/arm_common_tables.h +++ /dev/null @@ -1,93 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2013 ARM Limited. All rights reserved. -* -* $Date: 17. January 2013 -* $Revision: V1.4.1 -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -extern const q31_t realCoefAQ31[1024]; -extern const q31_t realCoefBQ31[1024]; -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoefQ31[6144]; -extern const q15_t twiddleCoefQ15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - - -#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) -#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) -#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) -#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/arm_math.h b/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/arm_math.h deleted file mode 100644 index 65304c127d6..00000000000 --- a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7306 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2013 ARM Limited. All rights reserved. -* -* $Date: 17. January 2013 -* $Revision: V1.4.1 -* -* Project: CMSIS DSP Library -* Title: arm_math.h -* -* Description: Public header file for CMSIS DSP Library -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * - * Examples - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * - * The library has been developed and tested with MDK-ARM version 4.60. - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * - * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM0b_math.uvproj - * - arm_cortexM0l_math.uvproj - * - arm_cortexM3b_math.uvproj - * - arm_cortexM3l_math.uvproj - * - arm_cortexM4b_math.uvproj - * - arm_cortexM4l_math.uvproj - * - arm_cortexM4bf_math.uvproj - * - arm_cortexM4lf_math.uvproj - * - * - * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - * Copyright Notice - * - * Copyright (C) 2010-2013 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined (ARM_MATH_CM4) -#include "core_cm4.h" -#elif defined (ARM_MATH_CM3) -#include "core_cm3.h" -#elif defined (ARM_MATH_CM0) -#include "core_cm0.h" -#define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) -#include "core_cm0plus.h" -#define ARM_MATH_CM0_FAMILY -#else -#include "ARMCM4.h" -#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x800000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined __CC_ARM -#define __SIMD32_TYPE int32_t __packed -#define CMSIS_UNUSED __attribute__((unused)) -#elif defined __ICCARM__ -#define CMSIS_UNUSED -#define __SIMD32_TYPE int32_t __packed -#elif defined __GNUC__ -#define __SIMD32_TYPE int32_t -#define CMSIS_UNUSED __attribute__((unused)) -#else -#error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) - -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) - -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - - -#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) -#define __CLZ __clz -#endif - -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) - - static __INLINE uint32_t __CLZ( - q31_t data); - - - static __INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - - } - -#endif - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - - uint32_t out, tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = __CLZ(in) - 1; - } - else - { - signBits = __CLZ(-in) - 1; - } - - /* Convert input sample to 1.31 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = (uint32_t) (in >> 24u); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (q31_t) (((q63_t) in * out) >> 31u); - tempVal = 0x7FFFFFFF - tempVal; - /* 1.31 with exp 1 */ - //out = (q31_t) (((q63_t) out * tempVal) >> 30u); - out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - - } - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - - uint32_t out = 0, tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = __CLZ(in) - 17; - } - else - { - signBits = __CLZ(-in) - 17; - } - - /* Convert input sample to 1.15 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = in >> 8; - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0; i < 2; i++) - { - tempVal = (q15_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFF - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - - - } - -#endif /* end of ARM_MATH_CM0_FAMILY */ - - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE q31_t __QADD8( - q31_t x, - q31_t y) - { - - q31_t sum; - q7_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((q31_t) (r + s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); - t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); - u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); - - sum = - (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | - (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); - - return sum; - - } - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB8( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((r - s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; - t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; - u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; - - sum = - (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & - 0x000000FF); - - return sum; - } - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE q31_t __QADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r + s, 16); - s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE q31_t __SHADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (s >> 1)); - s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r - s, 16); - s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __SHSUB16( - q31_t x, - q31_t y) - { - - q31_t diff; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (s >> 1)); - s = (((x >> 17) - (y >> 17)) << 16); - - diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return diff; - } - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE q31_t __QASX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE q31_t __SHASX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (y >> 17)); - s = (((x >> 17) + (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE q31_t __QSAX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE q31_t __SHSAX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (y >> 17)); - s = (((x >> 17) - (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMUSDX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((short) x * (short) (y >> 16)) - - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE q31_t __SMUADX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((short) x * (short) (y >> 16)) + - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE q31_t __QADD( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x + y); - } - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE q31_t __QSUB( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x - y); - } - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE q31_t __SMLAD( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE q31_t __SMLADX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMLSDX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum - ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE q63_t __SMLALD( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE q63_t __SMLALDX( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) y)) + - ((short) x * (short) (y >> 16)); - } - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE q31_t __SMUAD( - q31_t x, - q31_t y) - { - - return (((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE q31_t __SMUSD( - q31_t x, - q31_t y) - { - - return (-((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - static __INLINE q31_t __SXTB16( - q31_t x) - { - - return ((((x << 24) >> 24) & 0x0000FFFF) | - (((x << 8) >> 8) & 0xFFFF0000)); - } - - -#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] *S points to an instance of the Q7 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] *S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - * @return none - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] *S points to an instance of the Q15 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] *S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] *S points to an instance of the Q31 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] *S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] *S points to an instance of the floating-point FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] *S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q15; - - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - - - } arm_biquad_casd_df1_inst_f32; - - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q31; - - - - /** - * @brief Floating-point matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q31 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point matrix scaling. - * @param[in] *pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] *pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - /** - * @brief Q15 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#ifdef ARM_MATH_CM0_FAMILY - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] *S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @return none - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @return none - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the q15 PID Control structure - * @return none - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - - - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - - - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q31 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q15 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - /** - * @brief Floating-point vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Dot product of floating-point vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - /** - * @brief Dot product of Q7 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - /** - * @brief Dot product of Q15 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Dot product of Q31 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_f32; - - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the Q15 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - * @return none. - */ - - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - - } arm_lms_instance_q31; - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Correlation of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - /** - * @brief Correlation of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /* - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cos output. - * @return none. - */ - - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCcosVal); - - /* - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cosine output. - * @return none. - */ - - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - - - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#ifndef ARM_MATH_CM0_FAMILY - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD(S->A0, in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = __SMLALD(S->A1, (q31_t) *vstate, acc); - -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; - -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - - /** - * @ingroup groupController - */ - - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - */ - - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = - ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - - } - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - */ - - - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; - - } - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * The function implements the forward Park transform. - * - */ - - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - - } - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - - - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - */ - - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] *pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - - } - - } - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] *pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (y >> 20); - } - - - } - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] *pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - - - static __INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - - if(index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (y >> 20u); - - } - - } - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - - float32_t arm_sin_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q31_t arm_sin_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q15_t arm_sin_q15( - q15_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - - float32_t arm_cos_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q31_t arm_cos_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - - static __INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if(in > 0) - { - -// #if __FPU_USED -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - - - - - /** - * @brief floating-point Circular write function. - */ - - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - /** - * @brief Q15 Circular write function. - */ - - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - /** - * @brief Mean value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Mean value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Floating-point complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - /** - * @brief Q31 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - /** - * @brief Floating-point complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[in] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - * @return none. - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - - - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 - || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - - } - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20u); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20u); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return (acc << 2u); - - } - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return (acc >> 36); - - } - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return (acc >> 40); - - } - - /** - * @} end of BilinearInterpolate group - */ - - -#if defined ( __CC_ARM ) //Keil -//SMMLAR - #define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -//SMMLSR - #define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -//SMMULR - #define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -//Enter low optimization region - place directly above function definition - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - -//Exit low optimization region - place directly after end of function definition - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - -//Enter low optimization region - place directly above function definition - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ICCARM__) //IAR - //SMMLA - #define multAcc_32x32_keep32_R(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - - //SMMLS - #define multSub_32x32_keep32_R(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -//SMMUL - #define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - -//Enter low optimization region - place directly above function definition - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - -//Exit low optimization region - place directly after end of function definition - #define LOW_OPTIMIZATION_EXIT - -//Enter low optimization region - place directly above function definition - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__GNUC__) - //SMMLA - #define multAcc_32x32_keep32_R(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - - //SMMLS - #define multSub_32x32_keep32_R(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -//SMMUL - #define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) - - #define LOW_OPTIMIZATION_EXIT - - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - - - - -#ifdef __cplusplus -} -#endif - - -#endif /* _ARM_MATH_H */ - - -/** - * - * End of file. - */ diff --git a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cm0.h b/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cm0.h deleted file mode 100644 index ab31de0ee87..00000000000 --- a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cm0.h +++ /dev/null @@ -1,682 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000 - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cm0plus.h b/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cm0plus.h deleted file mode 100644 index 5cea74e9af3..00000000000 --- a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cm0plus.h +++ /dev/null @@ -1,793 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0P definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ - __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000 - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0 - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1) - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cm3.h b/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cm3.h deleted file mode 100644 index 122c9aa4a8f..00000000000 --- a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cm3.h +++ /dev/null @@ -1,1627 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cm4.h b/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cm4.h deleted file mode 100644 index d65016c7149..00000000000 --- a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,1772 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cm4_simd.h b/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cm4_simd.h deleted file mode 100644 index 83db95b5f11..00000000000 --- a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cm4_simd.h +++ /dev/null @@ -1,673 +0,0 @@ -/**************************************************************************//** - * @file core_cm4_simd.h - * @brief CMSIS Cortex-M4 SIMD Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_SIMD_H -#define __CORE_CM4_SIMD_H - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32) ) >> 32)) - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#include - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#include - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLALD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLALDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLSLD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLSLDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -/* not yet supported */ -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CORE_CM4_SIMD_H */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cmFunc.h b/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cmFunc.h deleted file mode 100644 index 0a18fafc301..00000000000 --- a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cmFunc.h +++ /dev/null @@ -1,636 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cmInstr.h b/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cmInstr.h deleted file mode 100644 index d213f0eed7c..00000000000 --- a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cmInstr.h +++ /dev/null @@ -1,688 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.20 - * @date 05. March 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - uint32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32 - op2)); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_sc000.h b/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_sc000.h deleted file mode 100644 index 1a2a0f2e300..00000000000 --- a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_sc000.h +++ /dev/null @@ -1,813 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup SC000 - @{ - */ - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (0) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000 - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1]; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154]; - __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/* SCB Security Features Register Definitions */ -#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ -#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ - -#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ -#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2]; - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of SC000 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_sc300.h b/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_sc300.h deleted file mode 100644 index cc34d6fc0ee..00000000000 --- a/bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_sc300.h +++ /dev/null @@ -1,1598 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup SC3000 - @{ - */ - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (300) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000 - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/nxp/lpc/lpc176x/CMSIS/License.doc b/bsp/nxp/lpc/lpc176x/CMSIS/License.doc deleted file mode 100644 index b6b8acecc13..00000000000 Binary files a/bsp/nxp/lpc/lpc176x/CMSIS/License.doc and /dev/null differ diff --git a/bsp/nxp/lpc/lpc176x/CMSIS/SConscript b/bsp/nxp/lpc/lpc176x/CMSIS/SConscript deleted file mode 100644 index b024548ee6c..00000000000 --- a/bsp/nxp/lpc/lpc176x/CMSIS/SConscript +++ /dev/null @@ -1,26 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() - -src = ['CM3/DeviceSupport/NXP/LPC17xx/system_LPC17xx.c'] - -# add for startup script -if rtconfig.PLATFORM in ['gcc']: - src += ['CM3/DeviceSupport/NXP/LPC17xx/startup/gcc/startup_LPC17xx.s'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - src += ['CM3/DeviceSupport/NXP/LPC17xx/startup/arm/startup_LPC17xx.s'] -elif rtconfig.PLATFORM in ['iccarm']: - src += ['CM3/DeviceSupport/NXP/LPC17xx/startup/iar/startup_LPC17xx.s'] - -CPPPATH = [cwd + '/CM3/DeviceSupport/NXP/LPC17xx/', - cwd + '/CMSIS/Include'] - -if GetDepend(['RT_USING_BSP_CMSIS']): - CPPPATH += [cwd + '/CM3/CoreSupport'] - src += ['CM3/CoreSupport/core_cm3.c'] - -group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/nxp/lpc/lpc176x/Kconfig b/bsp/nxp/lpc/lpc176x/Kconfig index a918de4a54b..43d24313a1c 100644 --- a/bsp/nxp/lpc/lpc176x/Kconfig +++ b/bsp/nxp/lpc/lpc176x/Kconfig @@ -12,4 +12,5 @@ osource "$PKGS_DIR/Kconfig" config SOC_LPC176 bool select ARCH_ARM_CORTEX_M3 + select PKG_USING_NXP_LPC_DRIVER default y diff --git a/bsp/nxp/lpc/lpc176x/SConstruct b/bsp/nxp/lpc/lpc176x/SConstruct index d01f148c7e7..c131d7f21fa 100644 --- a/bsp/nxp/lpc/lpc176x/SConstruct +++ b/bsp/nxp/lpc/lpc176x/SConstruct @@ -9,6 +9,23 @@ else: sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] from building import * +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "nxp-lpc-series-latest"), + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n==============================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("==============================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread-lpc17xx.' + rtconfig.TARGET_EXT DefaultEnvironment(tools=[]) diff --git a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/CoreSupport/core_cm3.c b/bsp/nxp/lpc/lpc178x/CMSIS/CM3/CoreSupport/core_cm3.c deleted file mode 100644 index 91431ba5170..00000000000 --- a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/CoreSupport/core_cm3.c +++ /dev/null @@ -1,358 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.c - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File - * @version V2.00 - * @date 13. September 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#include - - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ########################## Core Instruction Access ######################### */ - -#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#if (__ARMCC_VERSION < 400677) -__ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#if (__ARMCC_VERSION < 400677) -__ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __CLREX(void) -{ - clrex -} -#endif /* __ARMCC_VERSION */ - - -#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ -/* obsolete */ -#endif - - -/* ########################### Core Function Access ########################### */ - -#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get ISPR Register - - This function returns the content of the ISPR Register. - - \return ISPR Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_IPSR(void) -{ - mrs r0, ipsr - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_APSR(void) -{ - mrs r0, apsr - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_xPSR(void) -{ - mrs r0, xpsr - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_BASEPRI(void) -{ - mrs r0, basepri - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_BASEPRI(uint32_t basePri) -{ - msr basepri, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask Register. - - \return Fault Mask value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_FAULTMASK(void) -{ - mrs r0, faultmask - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set the Fault Mask - - This function assigns the given value to the Fault Mask Register. - - \param [in] faultMask Fault Mask value value to set - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_FAULTMASK(uint32_t faultMask) -{ - msr faultmask, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ -/* obsolete */ -#endif - - - - - - - - - - - - - - - - - diff --git a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/CoreSupport/core_cm3.h b/bsp/nxp/lpc/lpc178x/CMSIS/CM3/CoreSupport/core_cm3.h deleted file mode 100644 index 84214d5deb6..00000000000 --- a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/CoreSupport/core_cm3.h +++ /dev/null @@ -1,1242 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V2.01 - * @date 06. December 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - - -/** \mainpage CMSIS Cortex-M3 - - This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. - It consists of: - - - Cortex-M Core Register Definitions - - Cortex-M functions - - Cortex-M instructions - - The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease - access to the Cortex-M Core - */ - -/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration - @ingroup CMSIS - - List of Lint messages which will be suppressed and not shown: - - not yet checked - . - Note: To re-enable a Message, insert a space before 'lint' * - - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \defgroup CMSIS_core_definitions CMSIS Core Definitions - @ingroup CMSIS - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core - - Cortex-M core Revision Number - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -#include /*!< standard types definitions */ -#include "core_cmInstr.h" /*!< Core Instruction Access */ -#include "core_cmFunc.h" /*!< Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -/* IO definitions (access restrictions to peripheral registers) */ -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - -/*@} end of group CMSIS_core_definitions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** \defgroup CMSIS_core_register CMSIS Core Register - @ingroup CMSIS - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE CMSIS Core - Type definitions for the Cortex-M Core Registers - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC CMSIS NVIC - Type definitions for the Cortex-M NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB CMSIS SCB - Type definitions for the Cortex-M System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPU ID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt / Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) Hard Fault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) Mem Manage Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) Bus Fault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) ISA Feature Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick CMSIS SysTick - Type definitions for the Cortex-M System Timer Registers - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t RELOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t CURR; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IO uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM CMSIS ITM - Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __IO uint32_t IWR; /*!< Offset: (R/W) ITM Integration Write Register */ - __IO uint32_t IRR; /*!< Offset: (R/W) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __IO uint32_t LAR; /*!< Offset: (R/W) ITM Lock Access Register */ - __IO uint32_t LSR; /*!< Offset: (R/W) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_ATBID_Msk (0x7FUL << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_InterruptType CMSIS Interrupt Type - Type definitions for the Cortex-M Interrupt Type Register - @{ - */ - -/** \brief Structure type to access the Interrupt Type Register. - */ -typedef struct -{ - uint32_t RESERVED0; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Control Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1; -#endif -} InterruptType_Type; - -/* Interrupt Controller Type Register Definitions */ -#define IntType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ -#define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define IntType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ -#define IntType_ACTLR_DISFOLD_Msk (1UL << IntType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ - -#define IntType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ -#define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ - -#define IntType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ -#define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ - -/*@}*/ /* end of group CMSIS_InterruptType */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU CMSIS MPU - Type definitions for the Cortex-M Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ -#define MPU_RASR_AP_Msk (7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ -#define MPU_RASR_TEX_Msk (7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENA_Msk (0x1UL << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug CMSIS Core Debug - Type definitions for the Cortex-M Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ -#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface - @ingroup CMSIS - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions - @{ - */ - -/** \brief Set Priority Grouping - - This function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - (0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - This function gets the priority grouping from NVIC Interrupt Controller. - Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - - \return Priority grouping field - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - This function enables a device specific interupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to enable - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - This function disables a device specific interupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to disable - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - This function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Number of the interrupt for get pending - \return 0 Interrupt status is not pending - \return 1 Interrupt status is pending - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - This function sets the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for set pending - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - This function clears the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for clear pending - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - This function reads the active register in NVIC and returns the active bit. - \param [in] IRQn Number of the interrupt for get active - \return 0 Interrupt status is not active - \return 1 Interrupt status is active - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - This function sets the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - Note: The priority cannot be set for every core interrupt. - - \param [in] IRQn Number of the interrupt for set priority - \param [in] priority Priority to set - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - This function reads the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - The returned priority value is automatically aligned to the implemented - priority bits of the microcontroller. - - \param [in] IRQn Number of the interrupt for get priority - \return Interrupt Priority - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - This function encodes the priority for an interrupt with the given priority group, - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The returned priority value can be used for NVIC_SetPriority(...) function - - \param [in] PriorityGroup Used priority group - \param [in] PreemptPriority Preemptive priority value (starting from 0) - \param [in] SubPriority Sub priority value (starting from 0) - \return Encoded priority for the interrupt - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - This function decodes an interrupt priority value with the given priority group to - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The priority value can be retrieved with NVIC_GetPriority(...) function - - \param [in] Priority Priority value - \param [in] PriorityGroup Used priority group - \param [out] pPreemptPriority Preemptive priority value (starting from 0) - \param [out] pSubPriority Sub priority value (starting from 0) - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - This function initiate a system reset request to reset the MCU. - */ -static __INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - This function initialises the system tick timer and its interrupt and start the system tick timer. - Counter is in free running mode to generate periodical interrupts. - - \param [in] ticks Number of ticks between two interrupts - \return 0 Function succeeded - \return 1 Function failed - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->RELOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->CURR = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** \brief ITM Send Character - - This function transmits a character via the ITM channel 0. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \param [in] ch Character to transmit - \return Character to transmit - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - This function inputs a character via external variable ITM_RxBuffer. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \return Received character - \return -1 No character received - */ -static __INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - This function checks external variable ITM_RxBuffer whether a character is available or not. - It returns '1' if a character is available and '0' if no character is available. - - \return 0 No character available - \return 1 Character available - */ -static __INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif - -/*lint -restore */ diff --git a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/CoreSupport/core_cmFunc.h b/bsp/nxp/lpc/lpc178x/CMSIS/CM3/CoreSupport/core_cmFunc.h deleted file mode 100644 index e3d0edb8f37..00000000000 --- a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/CoreSupport/core_cmFunc.h +++ /dev/null @@ -1,844 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V2.01 - * @date 06. December 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H__ -#define __CORE_CMFUNC_H__ - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ -/* ARM armcc specific functions */ - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_CONTROL(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -#if (__ARMCC_VERSION < 400000) -extern void __set_CONTROL(uint32_t control); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get ISPR Register - - This function returns the content of the ISPR Register. - - \return ISPR Register value - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_IPSR(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_APSR(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_xPSR(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_PSP(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -#if (__ARMCC_VERSION < 400000) -extern void __set_PSP(uint32_t topOfProcStack); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_MSP(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -#if (__ARMCC_VERSION < 400000) -extern void __set_MSP(uint32_t topOfMainStack); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_PRIMASK(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -#if (__ARMCC_VERSION < 400000) -extern void __set_PRIMASK(uint32_t priMask); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} -#endif /* __ARMCC_VERSION */ - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_BASEPRI(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -#if (__ARMCC_VERSION < 400000) -extern void __set_BASEPRI(uint32_t basePri); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_FAULTMASK(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -#if (__ARMCC_VERSION < 400000) -extern void __set_FAULTMASK(uint32_t faultMask); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & 1); -} -#endif /* __ARMCC_VERSION */ - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - - #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ -/* IAR iccarm specific functions */ - -#if defined (__ICCARM__) - #include /* IAR Intrinsics */ -#endif - -#pragma diag_suppress=Pe940 - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_irq __enable_interrupt - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_irq __disable_interrupt - - -/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */ -/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */ - - -/** \brief Get ISPR Register - - This function returns the content of the ISPR Register. - - \return ISPR Register value - */ -static uint32_t __get_IPSR(void) -{ - __ASM("mrs r0, ipsr"); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -static uint32_t __get_APSR(void) -{ - __ASM("mrs r0, apsr"); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -static uint32_t __get_xPSR(void) -{ - __ASM("mrs r0, psr"); // assembler does not know "xpsr" -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -static uint32_t __get_PSP(void) -{ - __ASM("mrs r0, psp"); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -static void __set_PSP(uint32_t topOfProcStack) -{ - __ASM("msr psp, r0"); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -static uint32_t __get_MSP(void) -{ - __ASM("mrs r0, msp"); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -static void __set_MSP(uint32_t topOfMainStack) -{ - __ASM("msr msp, r0"); -} - - -/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */ -/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */ - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -static __INLINE void __enable_fault_irq(void) -{ - __ASM ("cpsie f"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -static __INLINE void __disable_fault_irq(void) -{ - __ASM ("cpsid f"); -} - - -/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */ -/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */ -/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */ -/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */ - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -static uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) - __ASM("vmrs r0, fpscr"); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -static void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) - __ASM("vmsr fpscr, r0"); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - -#pragma diag_default=Pe940 - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** \brief Get ISPR Register - - This function returns the content of the ISPR Register. - - \return ISPR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) - uint32_t result; - - __ASM volatile ("MRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) - __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) ); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H__ */ diff --git a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/CoreSupport/core_cmInstr.h b/bsp/nxp/lpc/lpc178x/CMSIS/CM3/CoreSupport/core_cmInstr.h deleted file mode 100644 index fb3c0927fb5..00000000000 --- a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/CoreSupport/core_cmInstr.h +++ /dev/null @@ -1,775 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V2.01 - * @date 06. December 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H__ -#define __CORE_CMINSTR_H__ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ -/* ARM armcc specific functions */ - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#if (__ARMCC_VERSION < 400677) -extern uint32_t __REV16(uint32_t value); -#else /* (__ARMCC_VERSION >= 400677) */ -static __INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#if (__ARMCC_VERSION < 400677) -extern int32_t __REVSH(int32_t value); -#else /* (__ARMCC_VERSION >= 400677) */ -static __INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#if (__ARMCC_VERSION < 400000) -extern void __CLREX(void); -#else /* (__ARMCC_VERSION >= 400000) */ -#define __CLREX __clrex -#endif /* __ARMCC_VERSION */ - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ -/* IAR iccarm specific functions */ - -#include /* IAR Intrinsics */ - -#pragma diag_suppress=Pe940 - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __no_operation - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -static __INLINE void __WFI(void) -{ - __ASM ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -static __INLINE void __WFE(void) -{ - __ASM ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -static __INLINE void __SEV(void) -{ - __ASM ("sev"); -} - - -/* intrinsic void __ISB(void) (see intrinsics.h) */ -/* intrinsic void __DSB(void) (see intrinsics.h) */ -/* intrinsic void __DMB(void) (see intrinsics.h) */ -/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h) */ -/* intrinsic __SSAT (see intrinsics.h) */ -/* intrinsic __USAT (see intrinsics.h) */ - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -static uint32_t __REV16(uint32_t value) -{ - __ASM("rev16 r0, r0"); -} - - -/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */ - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -static uint32_t __RBIT(uint32_t value) -{ - __ASM("rbit r0, r0"); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -static uint8_t __LDREXB(volatile uint8_t *addr) -{ - __ASM("ldrexb r0, [r0]"); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -static uint16_t __LDREXH(volatile uint16_t *addr) -{ - __ASM("ldrexh r0, [r0]"); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h) */ -static uint32_t __LDREXW(volatile uint32_t *addr) -{ - __ASM("ldrex r0, [r0]"); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - __ASM("strexb r0, r0, [r1]"); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - __ASM("strexh r0, r0, [r1]"); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h )*/ -static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - __ASM("strex r0, r0, [r1]"); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -static __INLINE void __CLREX(void) -{ - __ASM ("clrex"); -} - -/* intrinsic unsigned char __CLZ( unsigned long ) (see intrinsics.h) */ - -#endif /* (__CORTEX_M >= 0x03) */ - -#pragma diag_default=Pe940 - - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) static __INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) static __INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) static __INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) static __INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) static __INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) static __INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) -{ - uint32_t result; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint8_t result; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint16_t result; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) -{ - __ASM volatile ("clrex"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) -{ - uint8_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H__ */ diff --git a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/LPC177x_8x.h b/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/LPC177x_8x.h deleted file mode 100644 index 170f73053ed..00000000000 --- a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/LPC177x_8x.h +++ /dev/null @@ -1,1443 +0,0 @@ -/********************************************************************** -* $Id: LPC177x_8x.h 7485 2011-06-03 07:57:16Z sgg06786 $ LPC177x_8x.h 2011-06-02 -*//** -* @file LPC177x_8x.h -* @brief Cortex-M3 Core Peripheral Access Layer Header File for -* NXP LPC177x_8x Series. -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -#ifndef __LPC177x_8x_H__ -#define __LPC177x_8x_H__ - -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ - -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** LPC177x_8x Specific Interrupt Numbers *******************************************************/ - WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ - TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ - TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ - TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ - TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ - UART0_IRQn = 5, /*!< UART0 Interrupt */ - UART1_IRQn = 6, /*!< UART1 Interrupt */ - UART2_IRQn = 7, /*!< UART2 Interrupt */ - UART3_IRQn = 8, /*!< UART3 Interrupt */ - PWM1_IRQn = 9, /*!< PWM1 Interrupt */ - I2C0_IRQn = 10, /*!< I2C0 Interrupt */ - I2C1_IRQn = 11, /*!< I2C1 Interrupt */ - I2C2_IRQn = 12, /*!< I2C2 Interrupt */ - Reserved0_IRQn = 13, /*!< Reserved */ - SSP0_IRQn = 14, /*!< SSP0 Interrupt */ - SSP1_IRQn = 15, /*!< SSP1 Interrupt */ - PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ - RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ - EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ - EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ - EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ - EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ - ADC_IRQn = 22, /*!< A/D Converter Interrupt */ - BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ - USB_IRQn = 24, /*!< USB Interrupt */ - CAN_IRQn = 25, /*!< CAN Interrupt */ - DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ - I2S_IRQn = 27, /*!< I2S Interrupt */ - ENET_IRQn = 28, /*!< Ethernet Interrupt */ - MCI_IRQn = 29, /*!< SD/MMC card I/F Interrupt */ - MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ - QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ - PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ - USBActivity_IRQn = 33, /*!< USB Activity interrupt */ - CANActivity_IRQn = 34, /*!< CAN Activity interrupt */ - UART4_IRQn = 35, /*!< UART4 Interrupt */ - SSP2_IRQn = 36, /*!< SSP2 Interrupt */ - LCD_IRQn = 37, /*!< LCD Interrupt */ - GPIO_IRQn = 38, /*!< GPIO Interrupt */ - PWM0_IRQn = 39, /*!< PWM0 Interrupt */ - EEPROM_IRQn = 40, /*!< EEPROM Interrupt */ -} IRQn_Type; - - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/* Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - - -#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ -//#include "system_LPC177x_8x.h" /* System Header */ - - -/******************************************************************************/ -/* Device Specific Peripheral registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/*------------- System Control (SC) ------------------------------------------*/ -typedef struct -{ - __IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */ - uint32_t RESERVED0[31]; - __IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */ - __IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */ - __I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */ - __O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */ - uint32_t RESERVED1[4]; - __IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */ - __IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */ - __I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */ - __O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */ - uint32_t RESERVED2[4]; - __IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */ - __IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */ - uint32_t RESERVED3[14]; - __IO uint32_t EMCCLKSEL; /*!< Offset: 0x100 (R/W) External Memory Controller Clock Selection Register */ - __IO uint32_t CCLKSEL; /*!< Offset: 0x104 (R/W) CPU Clock Selection Register */ - __IO uint32_t USBCLKSEL; /*!< Offset: 0x108 (R/W) USB Clock Selection Register */ - __IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */ - __IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */ - __IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */ - uint32_t RESERVED4[10]; - __IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */ - uint32_t RESERVED5[1]; - __IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */ - __IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */ - uint32_t RESERVED6[12]; - __IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */ - uint32_t RESERVED7[7]; - __IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */ - __IO uint32_t IRCTRIM; /*!< Offset: 0x1A4 (R/W) Clock Dividers */ - __IO uint32_t PCLKSEL; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Selection Register */ - uint32_t RESERVED8[3]; - __IO uint32_t LCD_CFG; /*!< Offset: 0x1B8 (R/W) LCD Configuration and clocking control Register */ - uint32_t RESERVED9[1]; - __IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */ - __IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */ - __IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */ - __IO uint32_t RSTCON0; /*!< Offset: 0x1CC (R/W) RESET Control0 Register */ - __IO uint32_t RSTCON1; /*!< Offset: 0x1D0 (R/W) RESET Control1 Register */ - uint32_t RESERVED10[2]; - __IO uint32_t EMCDLYCTL; /*!< Offset: 0x1DC (R/W) SDRAM programmable delays */ - __IO uint32_t EMCCAL; /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */ - } LPC_SC_TypeDef; - -/*------------- Pin Connect Block (PINCON) -----------------------------------*/ -typedef struct -{ - __IO uint32_t P0_0; /* 0x000 */ - __IO uint32_t P0_1; - __IO uint32_t P0_2; - __IO uint32_t P0_3; - __IO uint32_t P0_4; - __IO uint32_t P0_5; - __IO uint32_t P0_6; - __IO uint32_t P0_7; - - __IO uint32_t P0_8; /* 0x020 */ - __IO uint32_t P0_9; - __IO uint32_t P0_10; - __IO uint32_t P0_11; - __IO uint32_t P0_12; - __IO uint32_t P0_13; - __IO uint32_t P0_14; - __IO uint32_t P0_15; - - __IO uint32_t P0_16; /* 0x040 */ - __IO uint32_t P0_17; - __IO uint32_t P0_18; - __IO uint32_t P0_19; - __IO uint32_t P0_20; - __IO uint32_t P0_21; - __IO uint32_t P0_22; - __IO uint32_t P0_23; - - __IO uint32_t P0_24; /* 0x060 */ - __IO uint32_t P0_25; - __IO uint32_t P0_26; - __IO uint32_t P0_27; - __IO uint32_t P0_28; - __IO uint32_t P0_29; - __IO uint32_t P0_30; - __IO uint32_t P0_31; - - __IO uint32_t P1_0; /* 0x080 */ - __IO uint32_t P1_1; - __IO uint32_t P1_2; - __IO uint32_t P1_3; - __IO uint32_t P1_4; - __IO uint32_t P1_5; - __IO uint32_t P1_6; - __IO uint32_t P1_7; - - __IO uint32_t P1_8; /* 0x0A0 */ - __IO uint32_t P1_9; - __IO uint32_t P1_10; - __IO uint32_t P1_11; - __IO uint32_t P1_12; - __IO uint32_t P1_13; - __IO uint32_t P1_14; - __IO uint32_t P1_15; - - __IO uint32_t P1_16; /* 0x0C0 */ - __IO uint32_t P1_17; - __IO uint32_t P1_18; - __IO uint32_t P1_19; - __IO uint32_t P1_20; - __IO uint32_t P1_21; - __IO uint32_t P1_22; - __IO uint32_t P1_23; - - __IO uint32_t P1_24; /* 0x0E0 */ - __IO uint32_t P1_25; - __IO uint32_t P1_26; - __IO uint32_t P1_27; - __IO uint32_t P1_28; - __IO uint32_t P1_29; - __IO uint32_t P1_30; - __IO uint32_t P1_31; - - __IO uint32_t P2_0; /* 0x100 */ - __IO uint32_t P2_1; - __IO uint32_t P2_2; - __IO uint32_t P2_3; - __IO uint32_t P2_4; - __IO uint32_t P2_5; - __IO uint32_t P2_6; - __IO uint32_t P2_7; - - __IO uint32_t P2_8; /* 0x120 */ - __IO uint32_t P2_9; - __IO uint32_t P2_10; - __IO uint32_t P2_11; - __IO uint32_t P2_12; - __IO uint32_t P2_13; - __IO uint32_t P2_14; - __IO uint32_t P2_15; - - __IO uint32_t P2_16; /* 0x140 */ - __IO uint32_t P2_17; - __IO uint32_t P2_18; - __IO uint32_t P2_19; - __IO uint32_t P2_20; - __IO uint32_t P2_21; - __IO uint32_t P2_22; - __IO uint32_t P2_23; - - __IO uint32_t P2_24; /* 0x160 */ - __IO uint32_t P2_25; - __IO uint32_t P2_26; - __IO uint32_t P2_27; - __IO uint32_t P2_28; - __IO uint32_t P2_29; - __IO uint32_t P2_30; - __IO uint32_t P2_31; - - __IO uint32_t P3_0; /* 0x180 */ - __IO uint32_t P3_1; - __IO uint32_t P3_2; - __IO uint32_t P3_3; - __IO uint32_t P3_4; - __IO uint32_t P3_5; - __IO uint32_t P3_6; - __IO uint32_t P3_7; - - __IO uint32_t P3_8; /* 0x1A0 */ - __IO uint32_t P3_9; - __IO uint32_t P3_10; - __IO uint32_t P3_11; - __IO uint32_t P3_12; - __IO uint32_t P3_13; - __IO uint32_t P3_14; - __IO uint32_t P3_15; - - __IO uint32_t P3_16; /* 0x1C0 */ - __IO uint32_t P3_17; - __IO uint32_t P3_18; - __IO uint32_t P3_19; - __IO uint32_t P3_20; - __IO uint32_t P3_21; - __IO uint32_t P3_22; - __IO uint32_t P3_23; - - __IO uint32_t P3_24; /* 0x1E0 */ - __IO uint32_t P3_25; - __IO uint32_t P3_26; - __IO uint32_t P3_27; - __IO uint32_t P3_28; - __IO uint32_t P3_29; - __IO uint32_t P3_30; - __IO uint32_t P3_31; - - __IO uint32_t P4_0; /* 0x200 */ - __IO uint32_t P4_1; - __IO uint32_t P4_2; - __IO uint32_t P4_3; - __IO uint32_t P4_4; - __IO uint32_t P4_5; - __IO uint32_t P4_6; - __IO uint32_t P4_7; - - __IO uint32_t P4_8; /* 0x220 */ - __IO uint32_t P4_9; - __IO uint32_t P4_10; - __IO uint32_t P4_11; - __IO uint32_t P4_12; - __IO uint32_t P4_13; - __IO uint32_t P4_14; - __IO uint32_t P4_15; - - __IO uint32_t P4_16; /* 0x240 */ - __IO uint32_t P4_17; - __IO uint32_t P4_18; - __IO uint32_t P4_19; - __IO uint32_t P4_20; - __IO uint32_t P4_21; - __IO uint32_t P4_22; - __IO uint32_t P4_23; - - __IO uint32_t P4_24; /* 0x260 */ - __IO uint32_t P4_25; - __IO uint32_t P4_26; - __IO uint32_t P4_27; - __IO uint32_t P4_28; - __IO uint32_t P4_29; - __IO uint32_t P4_30; - __IO uint32_t P4_31; - - __IO uint32_t P5_0; /* 0x280 */ - __IO uint32_t P5_1; - __IO uint32_t P5_2; - __IO uint32_t P5_3; - __IO uint32_t P5_4; /* 0x290 */ -} LPC_IOCON_TypeDef; - -/*------------- General Purpose Input/Output (GPIO) --------------------------*/ -typedef struct -{ - __IO uint32_t DIR; - uint32_t RESERVED0[3]; - __IO uint32_t MASK; - __IO uint32_t PIN; - __IO uint32_t SET; - __O uint32_t CLR; -} LPC_GPIO_TypeDef; - -typedef struct -{ - __I uint32_t IntStatus; - __I uint32_t IO0IntStatR; - __I uint32_t IO0IntStatF; - __O uint32_t IO0IntClr; - __IO uint32_t IO0IntEnR; - __IO uint32_t IO0IntEnF; - uint32_t RESERVED0[3]; - __I uint32_t IO2IntStatR; - __I uint32_t IO2IntStatF; - __O uint32_t IO2IntClr; - __IO uint32_t IO2IntEnR; - __IO uint32_t IO2IntEnF; -} LPC_GPIOINT_TypeDef; - -/*------------- Timer (TIM) --------------------------------------------------*/ -typedef struct -{ - __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */ - __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */ - __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */ - __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */ - __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */ - __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */ - __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */ - __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */ - __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */ - __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */ - __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */ - __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */ - __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */ - uint32_t RESERVED0[2]; - __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */ - uint32_t RESERVED1[12]; - __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */ -} LPC_TIM_TypeDef; - -/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ -typedef struct -{ - __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */ - __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */ - __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */ - __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */ - __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */ - __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */ - __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */ - __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */ - __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */ - __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */ - __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */ - __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */ - __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */ - __I uint32_t CR2; /*!< Offset: 0x034 Capture Register 2 (R/ ) */ - __I uint32_t CR3; /*!< Offset: 0x038 Capture Register 3 (R/ ) */ - uint32_t RESERVED0; - __IO uint32_t MR4; /*!< Offset: 0x040 Match Register 4 (R/W) */ - __IO uint32_t MR5; /*!< Offset: 0x044 Match Register 5 (R/W) */ - __IO uint32_t MR6; /*!< Offset: 0x048 Match Register 6 (R/W) */ - __IO uint32_t PCR; /*!< Offset: 0x04C PWM Control Register (R/W) */ - __IO uint32_t LER; /*!< Offset: 0x050 Load Enable Register (R/W) */ - uint32_t RESERVED1[7]; - __IO uint32_t CTCR; /*!< Offset: 0x070 Counter Control Register (R/W) */ -} LPC_PWM_TypeDef; - -/*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/ -/* There are three types of UARTs on the chip: -(1) UART0,UART2, and UART3 are the standard UART. -(2) UART1 is the standard with modem capability. -(3) USART(UART4) is the sync/async UART with smart card capability. -More details can be found on the Users Manual. */ - -#if 0 -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[7]; - __I uint8_t LSR; - uint8_t RESERVED2[7]; - __IO uint8_t SCR; - uint8_t RESERVED3[3]; - __IO uint32_t ACR; - __IO uint8_t ICR; - uint8_t RESERVED4[3]; - __IO uint8_t FDR; - uint8_t RESERVED5[7]; - __IO uint8_t TER; - uint8_t RESERVED6[39]; - __I uint8_t FIFOLVL; -} LPC_UART_TypeDef; -#else -typedef struct -{ - union - { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union - { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union - { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[7];//Reserved - __I uint8_t LSR; - uint8_t RESERVED2[7];//Reserved - __IO uint8_t SCR; - uint8_t RESERVED3[3];//Reserved - __IO uint32_t ACR; - __IO uint8_t ICR; - uint8_t RESERVED4[3];//Reserved - __IO uint8_t FDR; - uint8_t RESERVED5[7];//Reserved - __IO uint8_t TER; - uint8_t RESERVED8[27];//Reserved - __IO uint8_t RS485CTRL; - uint8_t RESERVED9[3];//Reserved - __IO uint8_t ADRMATCH; - uint8_t RESERVED10[3];//Reserved - __IO uint8_t RS485DLY; - uint8_t RESERVED11[3];//Reserved - __I uint8_t FIFOLVL; -}LPC_UART_TypeDef; -#endif - - -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[3]; - __IO uint8_t MCR; - uint8_t RESERVED2[3]; - __I uint8_t LSR; - uint8_t RESERVED3[3]; - __I uint8_t MSR; - uint8_t RESERVED4[3]; - __IO uint8_t SCR; - uint8_t RESERVED5[3]; - __IO uint32_t ACR; - uint32_t RESERVED6; - __IO uint32_t FDR; - uint32_t RESERVED7; - __IO uint8_t TER; - uint8_t RESERVED8[27]; - __IO uint8_t RS485CTRL; - uint8_t RESERVED9[3]; - __IO uint8_t ADRMATCH; - uint8_t RESERVED10[3]; - __IO uint8_t RS485DLY; - uint8_t RESERVED11[3]; - __I uint8_t FIFOLVL; -} LPC_UART1_TypeDef; - -typedef struct -{ - union { - __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */ - __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */ - __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */ - }; - union { - __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */ - __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */ - }; - union { - __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */ - __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */ - }; - __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */ - __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */ - __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */ - __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */ - __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */ - __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */ - __IO uint32_t ICR; /*!< Offset: 0x024 irDA Control Register (R/W) */ - __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */ - __IO uint32_t OSR; /*!< Offset: 0x02C Over sampling Register (R/W) */ - __O uint32_t POP; /*!< Offset: 0x030 NHP Pop Register (W) */ - __IO uint32_t MODE; /*!< Offset: 0x034 NHP Mode selection Register (W) */ - uint32_t RESERVED0[2]; - __IO uint32_t HDEN; /*!< Offset: 0x040 Half duplex Enable Register (R/W) */ - uint32_t RESERVED1; - __IO uint32_t SCI_CTRL; /*!< Offset: 0x048 Smart card Interface Control Register (R/W) */ - __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */ - __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */ - __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */ - __IO uint32_t SYNCCTRL; /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */ - __IO uint32_t TER; /*!< Offset: 0x05C Transmit Enable Register (R/W) */ - uint32_t RESERVED2[989]; - __I uint32_t CFG; /*!< Offset: 0xFD4 Configuration Register (R) */ - __O uint32_t INTCE; /*!< Offset: 0xFD8 Interrupt Clear Enable Register (W) */ - __O uint32_t INTSE; /*!< Offset: 0xFDC Interrupt Set Enable Register (W) */ - __I uint32_t INTS; /*!< Offset: 0xFE0 Interrupt Status Register (R) */ - __I uint32_t INTE; /*!< Offset: 0xFE4 Interrupt Enable Register (R) */ - __O uint32_t INTCS; /*!< Offset: 0xFE8 Interrupt Clear Status Register (W) */ - __O uint32_t INTSS; /*!< Offset: 0xFEC Interrupt Set Status Register (W) */ - uint32_t RESERVED3[3]; - __I uint32_t MID; /*!< Offset: 0xFFC Module Identification Register (R) */ -} LPC_UART4_TypeDef; - -/*------------- Synchronous Serial Communication (SSP) -----------------------*/ -typedef struct -{ - __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */ - __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */ - __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */ - __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */ - __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */ - __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */ - __IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */ - __IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */ - __IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */ - __IO uint32_t DMACR; -} LPC_SSP_TypeDef; - -/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ -typedef struct -{ - __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */ - __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */ - __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */ - __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */ - __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */ - __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */ - __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */ - __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */ - __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */ - __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */ - __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */ - __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */ - __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */ - __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */ - __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */ - __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */ -} LPC_I2C_TypeDef; - -/*------------- Inter IC Sound (I2S) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t DAO; - __IO uint32_t DAI; - __O uint32_t TXFIFO; - __I uint32_t RXFIFO; - __I uint32_t STATE; - __IO uint32_t DMA1; - __IO uint32_t DMA2; - __IO uint32_t IRQ; - __IO uint32_t TXRATE; - __IO uint32_t RXRATE; - __IO uint32_t TXBITRATE; - __IO uint32_t RXBITRATE; - __IO uint32_t TXMODE; - __IO uint32_t RXMODE; -} LPC_I2S_TypeDef; - -/*------------- Real-Time Clock (RTC) ----------------------------------------*/ -typedef struct -{ - __IO uint8_t ILR; - uint8_t RESERVED0[7]; - __IO uint8_t CCR; - uint8_t RESERVED1[3]; - __IO uint8_t CIIR; - uint8_t RESERVED2[3]; - __IO uint8_t AMR; - uint8_t RESERVED3[3]; - __I uint32_t CTIME0; - __I uint32_t CTIME1; - __I uint32_t CTIME2; - __IO uint8_t SEC; - uint8_t RESERVED4[3]; - __IO uint8_t MIN; - uint8_t RESERVED5[3]; - __IO uint8_t HOUR; - uint8_t RESERVED6[3]; - __IO uint8_t DOM; - uint8_t RESERVED7[3]; - __IO uint8_t DOW; - uint8_t RESERVED8[3]; - __IO uint16_t DOY; - uint16_t RESERVED9; - __IO uint8_t MONTH; - uint8_t RESERVED10[3]; - __IO uint16_t YEAR; - uint16_t RESERVED11; - __IO uint32_t CALIBRATION; - __IO uint32_t GPREG0; - __IO uint32_t GPREG1; - __IO uint32_t GPREG2; - __IO uint32_t GPREG3; - __IO uint32_t GPREG4; - __IO uint8_t RTC_AUXEN; - uint8_t RESERVED12[3]; - __IO uint8_t RTC_AUX; - uint8_t RESERVED13[3]; - __IO uint8_t ALSEC; - uint8_t RESERVED14[3]; - __IO uint8_t ALMIN; - uint8_t RESERVED15[3]; - __IO uint8_t ALHOUR; - uint8_t RESERVED16[3]; - __IO uint8_t ALDOM; - uint8_t RESERVED17[3]; - __IO uint8_t ALDOW; - uint8_t RESERVED18[3]; - __IO uint16_t ALDOY; - uint16_t RESERVED19; - __IO uint8_t ALMON; - uint8_t RESERVED20[3]; - __IO uint16_t ALYEAR; - uint16_t RESERVED21; - __IO uint32_t ERSTATUS; - __IO uint32_t ERCONTROL; - __IO uint32_t ERCOUNTERS; - uint32_t RESERVED22; - __IO uint32_t ERFIRSTSTAMP0; - __IO uint32_t ERFIRSTSTAMP1; - __IO uint32_t ERFIRSTSTAMP2; - uint32_t RESERVED23; - __IO uint32_t ERLASTSTAMP0; - __IO uint32_t ERLASTSTAMP1; - __IO uint32_t ERLASTSTAMP2; -} LPC_RTC_TypeDef; - -/*------------- Watchdog Timer (WDT) -----------------------------------------*/ -typedef struct -{ - __IO uint8_t MOD; - uint8_t RESERVED0[3]; - __IO uint32_t TC; - __O uint8_t FEED; - uint8_t RESERVED1[3]; - __I uint32_t TV; - uint32_t RESERVED2; - __IO uint32_t WARNINT; - __IO uint32_t WINDOW; -} LPC_WDT_TypeDef; - -/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ -typedef struct -{ - __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */ - __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */ - uint32_t RESERVED0; - __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */ - __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */ - __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */ - __IO uint32_t ADTRM; -} LPC_ADC_TypeDef; - -/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CTRL; - __IO uint32_t CNTVAL; -} LPC_DAC_TypeDef; - -/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ -typedef struct -{ - __I uint32_t CON; - __O uint32_t CON_SET; - __O uint32_t CON_CLR; - __I uint32_t CAPCON; - __O uint32_t CAPCON_SET; - __O uint32_t CAPCON_CLR; - __IO uint32_t TC0; - __IO uint32_t TC1; - __IO uint32_t TC2; - __IO uint32_t LIM0; - __IO uint32_t LIM1; - __IO uint32_t LIM2; - __IO uint32_t MAT0; - __IO uint32_t MAT1; - __IO uint32_t MAT2; - __IO uint32_t DT; - __IO uint32_t CP; - __IO uint32_t CAP0; - __IO uint32_t CAP1; - __IO uint32_t CAP2; - __I uint32_t INTEN; - __O uint32_t INTEN_SET; - __O uint32_t INTEN_CLR; - __I uint32_t CNTCON; - __O uint32_t CNTCON_SET; - __O uint32_t CNTCON_CLR; - __I uint32_t INTF; - __O uint32_t INTF_SET; - __O uint32_t INTF_CLR; - __O uint32_t CAP_CLR; -} LPC_MCPWM_TypeDef; - -/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ -typedef struct -{ - __O uint32_t CON; - __I uint32_t STAT; - __IO uint32_t CONF; - __I uint32_t POS; - __IO uint32_t MAXPOS; - __IO uint32_t CMPOS0; - __IO uint32_t CMPOS1; - __IO uint32_t CMPOS2; - __I uint32_t INXCNT; - __IO uint32_t INXCMP0; - __IO uint32_t LOAD; - __I uint32_t TIME; - __I uint32_t VEL; - __I uint32_t CAP; - __IO uint32_t VELCOMP; - __IO uint32_t FILTERPHA; - __IO uint32_t FILTERPHB; - __IO uint32_t FILTERINX; - __IO uint32_t WINDOW; - __IO uint32_t INXCMP1; - __IO uint32_t INXCMP2; - uint32_t RESERVED0[993]; - __O uint32_t IEC; - __O uint32_t IES; - __I uint32_t INTSTAT; - __I uint32_t IE; - __O uint32_t CLR; - __O uint32_t SET; -} LPC_QEI_TypeDef; - -/*------------- SD/MMC card Interface (MCI)-----------------------------------*/ -typedef struct -{ - __IO uint32_t POWER; - __IO uint32_t CLOCK; - __IO uint32_t ARGUMENT; - __IO uint32_t COMMAND; - __I uint32_t RESP_CMD; - __I uint32_t RESP0; - __I uint32_t RESP1; - __I uint32_t RESP2; - __I uint32_t RESP3; - __IO uint32_t DATATMR; - __IO uint32_t DATALEN; - __IO uint32_t DATACTRL; - __I uint32_t DATACNT; - __I uint32_t STATUS; - __O uint32_t CLEAR; - __IO uint32_t MASK0; - uint32_t RESERVED0[2]; - __I uint32_t FIFOCNT; - uint32_t RESERVED1[13]; - __IO uint32_t FIFO; -} LPC_MCI_TypeDef; - -/*------------- Controller Area Network (CAN) --------------------------------*/ -typedef struct -{ - __IO uint32_t mask[512]; /* ID Masks */ -} LPC_CANAF_RAM_TypeDef; - -typedef struct /* Acceptance Filter Registers */ -{ - ///Offset: 0x00000000 - Acceptance Filter Register - __IO uint32_t AFMR; - - ///Offset: 0x00000004 - Standard Frame Individual Start Address Register - __IO uint32_t SFF_sa; - - ///Offset: 0x00000008 - Standard Frame Group Start Address Register - __IO uint32_t SFF_GRP_sa; - - ///Offset: 0x0000000C - Extended Frame Start Address Register - __IO uint32_t EFF_sa; - - ///Offset: 0x00000010 - Extended Frame Group Start Address Register - __IO uint32_t EFF_GRP_sa; - - ///Offset: 0x00000014 - End of AF Tables register - __IO uint32_t ENDofTable; - - ///Offset: 0x00000018 - LUT Error Address register - __I uint32_t LUTerrAd; - - ///Offset: 0x0000001C - LUT Error Register - __I uint32_t LUTerr; - - ///Offset: 0x00000020 - CAN Central Transmit Status Register - __IO uint32_t FCANIE; - - ///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0 - __IO uint32_t FCANIC0; - - ///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1 - __IO uint32_t FCANIC1; -} LPC_CANAF_TypeDef; - -typedef struct /* Central Registers */ -{ - __I uint32_t TxSR; - __I uint32_t RxSR; - __I uint32_t MSR; -} LPC_CANCR_TypeDef; - -typedef struct /* Controller Registers */ -{ - ///Offset: 0x00000000 - Controls the operating mode of the CAN Controller - __IO uint32_t MOD; - - ///Offset: 0x00000004 - Command bits that affect the state - __O uint32_t CMR; - - ///Offset: 0x00000008 - Global Controller Status and Error Counters - __IO uint32_t GSR; - - ///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture - __I uint32_t ICR; - - ///Offset: 0x00000010 - Interrupt Enable Register - __IO uint32_t IER; - - ///Offset: 0x00000014 - Bus Timing Register - __IO uint32_t BTR; - - ///Offset: 0x00000018 - Error Warning Limit - __IO uint32_t EWL; - - ///Offset: 0x0000001C - Status Register - __I uint32_t SR; - - ///Offset: 0x00000020 - Receive frame status - __IO uint32_t RFS; - - ///Offset: 0x00000024 - Received Identifier - __IO uint32_t RID; - - ///Offset: 0x00000028 - Received data bytes 1-4 - __IO uint32_t RDA; - - ///Offset: 0x0000002C - Received data bytes 5-8 - __IO uint32_t RDB; - - ///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1) - __IO uint32_t TFI1; - - ///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1) - __IO uint32_t TID1; - - ///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1) - __IO uint32_t TDA1; - - ///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1) - __IO uint32_t TDB1; - - ///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2) - __IO uint32_t TFI2; - - ///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2) - __IO uint32_t TID2; - - ///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2) - __IO uint32_t TDA2; - - ///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2) - __IO uint32_t TDB2; - - ///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3) - __IO uint32_t TFI3; - - ///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3) - __IO uint32_t TID3; - - ///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3) - __IO uint32_t TDA3; - - ///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3) - __IO uint32_t TDB3; -} LPC_CAN_TypeDef; - -/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ -typedef struct /* Common Registers */ -{ - __I uint32_t IntStat; - __I uint32_t IntTCStat; - __O uint32_t IntTCClear; - __I uint32_t IntErrStat; - __O uint32_t IntErrClr; - __I uint32_t RawIntTCStat; - __I uint32_t RawIntErrStat; - __I uint32_t EnbldChns; - __IO uint32_t SoftBReq; - __IO uint32_t SoftSReq; - __IO uint32_t SoftLBReq; - __IO uint32_t SoftLSReq; - __IO uint32_t Config; - __IO uint32_t Sync; -} LPC_GPDMA_TypeDef; - -typedef struct /* Channel Registers */ -{ - __IO uint32_t CSrcAddr; - __IO uint32_t CDestAddr; - __IO uint32_t CLLI; - __IO uint32_t CControl; - __IO uint32_t CConfig; -} LPC_GPDMACH_TypeDef; - -/*------------- Universal Serial Bus (USB) -----------------------------------*/ -typedef struct -{ - __I uint32_t Revision; /* USB Host Registers */ - __IO uint32_t Control; - __IO uint32_t CommandStatus; - __IO uint32_t InterruptStatus; - __IO uint32_t InterruptEnable; - __IO uint32_t InterruptDisable; - __IO uint32_t HCCA; - __I uint32_t PeriodCurrentED; - __IO uint32_t ControlHeadED; - __IO uint32_t ControlCurrentED; - __IO uint32_t BulkHeadED; - __IO uint32_t BulkCurrentED; - __I uint32_t DoneHead; - __IO uint32_t FmInterval; - __I uint32_t FmRemaining; - __I uint32_t FmNumber; - __IO uint32_t PeriodicStart; - __IO uint32_t LSTreshold; - __IO uint32_t RhDescriptorA; - __IO uint32_t RhDescriptorB; - __IO uint32_t RhStatus; - __IO uint32_t RhPortStatus1; - __IO uint32_t RhPortStatus2; - uint32_t RESERVED0[40]; - __I uint32_t Module_ID; - - __I uint32_t IntSt; /* USB On-The-Go Registers */ - __IO uint32_t IntEn; - __O uint32_t IntSet; - __O uint32_t IntClr; - __IO uint32_t StCtrl; - __IO uint32_t Tmr; - uint32_t RESERVED1[58]; - - __I uint32_t DevIntSt; /* USB Device Interrupt Registers */ - __IO uint32_t DevIntEn; - __O uint32_t DevIntClr; - __O uint32_t DevIntSet; - - __O uint32_t CmdCode; /* USB Device SIE Command Registers */ - __I uint32_t CmdData; - - __I uint32_t RxData; /* USB Device Transfer Registers */ - __O uint32_t TxData; - __I uint32_t RxPLen; - __O uint32_t TxPLen; - __IO uint32_t Ctrl; - __O uint32_t DevIntPri; - - __I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */ - __IO uint32_t EpIntEn; - __O uint32_t EpIntClr; - __O uint32_t EpIntSet; - __O uint32_t EpIntPri; - - __IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/ - __O uint32_t EpInd; - __IO uint32_t MaxPSize; - - __I uint32_t DMARSt; /* USB Device DMA Registers */ - __O uint32_t DMARClr; - __O uint32_t DMARSet; - uint32_t RESERVED2[9]; - __IO uint32_t UDCAH; - __I uint32_t EpDMASt; - __O uint32_t EpDMAEn; - __O uint32_t EpDMADis; - __I uint32_t DMAIntSt; - __IO uint32_t DMAIntEn; - uint32_t RESERVED3[2]; - __I uint32_t EoTIntSt; - __O uint32_t EoTIntClr; - __O uint32_t EoTIntSet; - __I uint32_t NDDRIntSt; - __O uint32_t NDDRIntClr; - __O uint32_t NDDRIntSet; - __I uint32_t SysErrIntSt; - __O uint32_t SysErrIntClr; - __O uint32_t SysErrIntSet; - uint32_t RESERVED4[15]; - - union { - __I uint32_t I2C_RX; /* USB OTG I2C Registers */ - __O uint32_t I2C_TX; - }; - __IO uint32_t I2C_STS; - __IO uint32_t I2C_CTL; - __IO uint32_t I2C_CLKHI; - __O uint32_t I2C_CLKLO; - uint32_t RESERVED5[824]; - - union { - __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ - __IO uint32_t OTGClkCtrl; - }; - union { - __I uint32_t USBClkSt; - __I uint32_t OTGClkSt; - }; -} LPC_USB_TypeDef; - -/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ -typedef struct -{ - __IO uint32_t MAC1; /* MAC Registers */ - __IO uint32_t MAC2; - __IO uint32_t IPGT; - __IO uint32_t IPGR; - __IO uint32_t CLRT; - __IO uint32_t MAXF; - __IO uint32_t SUPP; - __IO uint32_t TEST; - __IO uint32_t MCFG; - __IO uint32_t MCMD; - __IO uint32_t MADR; - __O uint32_t MWTD; - __I uint32_t MRDD; - __I uint32_t MIND; - uint32_t RESERVED0[2]; - __IO uint32_t SA0; - __IO uint32_t SA1; - __IO uint32_t SA2; - uint32_t RESERVED1[45]; - __IO uint32_t Command; /* Control Registers */ - __I uint32_t Status; - __IO uint32_t RxDescriptor; - __IO uint32_t RxStatus; - __IO uint32_t RxDescriptorNumber; - __I uint32_t RxProduceIndex; - __IO uint32_t RxConsumeIndex; - __IO uint32_t TxDescriptor; - __IO uint32_t TxStatus; - __IO uint32_t TxDescriptorNumber; - __IO uint32_t TxProduceIndex; - __I uint32_t TxConsumeIndex; - uint32_t RESERVED2[10]; - __I uint32_t TSV0; - __I uint32_t TSV1; - __I uint32_t RSV; - uint32_t RESERVED3[3]; - __IO uint32_t FlowControlCounter; - __I uint32_t FlowControlStatus; - uint32_t RESERVED4[34]; - __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ - __I uint32_t RxFilterWoLStatus; - __O uint32_t RxFilterWoLClear; - uint32_t RESERVED5; - __IO uint32_t HashFilterL; - __IO uint32_t HashFilterH; - uint32_t RESERVED6[882]; - __I uint32_t IntStatus; /* Module Control Registers */ - __IO uint32_t IntEnable; - __O uint32_t IntClear; - __O uint32_t IntSet; - uint32_t RESERVED7; - __IO uint32_t PowerDown; - uint32_t RESERVED8; - __IO uint32_t Module_ID; -} LPC_EMAC_TypeDef; - -/*------------- LCD controller (LCD) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t TIMH; /* LCD Registers */ - __IO uint32_t TIMV; - __IO uint32_t POL; - __IO uint32_t LE; - __IO uint32_t UPBASE; - __IO uint32_t LPBASE; - __IO uint32_t CTRL; - __IO uint32_t INTMSK; - __I uint32_t INTRAW; - __I uint32_t INTSTAT; - __O uint32_t INTCLR; - __I uint32_t UPCURR; - __I uint32_t LPCURR; - uint32_t RESERVED0[115]; - __IO uint32_t PAL[128]; - uint32_t RESERVED1[256]; - __IO uint32_t CRSR_IMG[256]; - __IO uint32_t CRSR_CTRL; - __IO uint32_t CRSR_CFG; - __IO uint32_t CRSR_PAL0; - __IO uint32_t CRSR_PAL1; - __IO uint32_t CRSR_XY; - __IO uint32_t CRSR_CLIP; - uint32_t RESERVED2[2]; - __IO uint32_t CRSR_INTMSK; - __O uint32_t CRSR_INTCLR; - __I uint32_t CRSR_INTRAW; - __I uint32_t CRSR_INTSTAT; -} LPC_LCD_TypeDef; - -/*------------- External Memory Controller (EMC) -----------------------------*/ -typedef struct -{ - __IO uint32_t Control; - __I uint32_t Status; - __IO uint32_t Config; - uint32_t RESERVED0[5]; - __IO uint32_t DynamicControl; - __IO uint32_t DynamicRefresh; - __IO uint32_t DynamicReadConfig; - uint32_t RESERVED1[1]; - __IO uint32_t DynamicRP; - __IO uint32_t DynamicRAS; - __IO uint32_t DynamicSREX; - __IO uint32_t DynamicAPR; - __IO uint32_t DynamicDAL; - __IO uint32_t DynamicWR; - __IO uint32_t DynamicRC; - __IO uint32_t DynamicRFC; - __IO uint32_t DynamicXSR; - __IO uint32_t DynamicRRD; - __IO uint32_t DynamicMRD; - uint32_t RESERVED2[9]; - __IO uint32_t StaticExtendedWait; - uint32_t RESERVED3[31]; - __IO uint32_t DynamicConfig0; - __IO uint32_t DynamicRasCas0; - uint32_t RESERVED4[6]; - __IO uint32_t DynamicConfig1; - __IO uint32_t DynamicRasCas1; - uint32_t RESERVED5[6]; - __IO uint32_t DynamicConfig2; - __IO uint32_t DynamicRasCas2; - uint32_t RESERVED6[6]; - __IO uint32_t DynamicConfig3; - __IO uint32_t DynamicRasCas3; - uint32_t RESERVED7[38]; - __IO uint32_t StaticConfig0; - __IO uint32_t StaticWaitWen0; - __IO uint32_t StaticWaitOen0; - __IO uint32_t StaticWaitRd0; - __IO uint32_t StaticWaitPage0; - __IO uint32_t StaticWaitWr0; - __IO uint32_t StaticWaitTurn0; - uint32_t RESERVED8[1]; - __IO uint32_t StaticConfig1; - __IO uint32_t StaticWaitWen1; - __IO uint32_t StaticWaitOen1; - __IO uint32_t StaticWaitRd1; - __IO uint32_t StaticWaitPage1; - __IO uint32_t StaticWaitWr1; - __IO uint32_t StaticWaitTurn1; - uint32_t RESERVED9[1]; - __IO uint32_t StaticConfig2; - __IO uint32_t StaticWaitWen2; - __IO uint32_t StaticWaitOen2; - __IO uint32_t StaticWaitRd2; - __IO uint32_t StaticWaitPage2; - __IO uint32_t StaticWaitWr2; - __IO uint32_t StaticWaitTurn2; - uint32_t RESERVED10[1]; - __IO uint32_t StaticConfig3; - __IO uint32_t StaticWaitWen3; - __IO uint32_t StaticWaitOen3; - __IO uint32_t StaticWaitRd3; - __IO uint32_t StaticWaitPage3; - __IO uint32_t StaticWaitWr3; - __IO uint32_t StaticWaitTurn3; -} LPC_EMC_TypeDef; - -/*------------- CRC Engine (CRC) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t MODE; - __IO uint32_t SEED; - union { - __I uint32_t SUM; - __O uint32_t WR_DATA_DWORD; - __O uint16_t WR_DATA_WORD; - uint16_t RESERVED_WORD; - __O uint8_t WR_DATA_BYTE; - uint8_t RESERVED_BYTE[3]; - }; -} LPC_CRC_TypeDef; - -/*------------- EEPROM Controller (EEPROM) -----------------------------------*/ -typedef struct -{ - __IO uint32_t CMD; /* 0x0080 */ - __IO uint32_t ADDR; - __IO uint32_t WDATA; - __IO uint32_t RDATA; - __IO uint32_t WSTATE; /* 0x0090 */ - __IO uint32_t CLKDIV; - __IO uint32_t PWRDWN; /* 0x0098 */ - uint32_t RESERVED0[975]; - __IO uint32_t INT_CLR_ENABLE; /* 0x0FD8 */ - __IO uint32_t INT_SET_ENABLE; - __IO uint32_t INT_STATUS; /* 0x0FE0 */ - __IO uint32_t INT_ENABLE; - __IO uint32_t INT_CLR_STATUS; - __IO uint32_t INT_SET_STATUS; -} LPC_EEPROM_TypeDef; - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* Base addresses */ -#define LPC_FLASH_BASE (0x00000000UL) -#define LPC_RAM_BASE (0x10000000UL) -#define LPC_PERI_RAM_BASE (0x20000000UL) -#define LPC_APB0_BASE (0x40000000UL) -#define LPC_APB1_BASE (0x40080000UL) -#define LPC_AHBRAM1_BASE (0x20004000UL) -#define LPC_AHB_BASE (0x20080000UL) -#define LPC_CM3_BASE (0xE0000000UL) - -/* APB0 peripherals */ -#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) -#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) -#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) -#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) -#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) -#define LPC_PWM0_BASE (LPC_APB0_BASE + 0x14000) -#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) -#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) -#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) -#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) -#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x2C000) -#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) -#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) -#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) -#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) -#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) -#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) -#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) -#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) - -/* APB1 peripherals */ -#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) -#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) -#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) -#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) -#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) -#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) -#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) -#define LPC_UART4_BASE (LPC_APB1_BASE + 0x24000) -#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) -#define LPC_SSP2_BASE (LPC_APB1_BASE + 0x2C000) -#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) -#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) -#define LPC_MCI_BASE (LPC_APB1_BASE + 0x40000) -#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) - -/* AHB peripherals */ -#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x00100) -#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x00120) -#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x00140) -#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x00160) -#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x00180) -#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x001A0) -#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x001C0) -#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x001E0) -#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x04000) -#define LPC_LCD_BASE (LPC_AHB_BASE + 0x08000) -#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) -#define LPC_CRC_BASE (LPC_AHB_BASE + 0x10000) -#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x18000) -#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x18020) -#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x18040) -#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x18060) -#define LPC_GPIO4_BASE (LPC_AHB_BASE + 0x18080) -#define LPC_GPIO5_BASE (LPC_AHB_BASE + 0x180A0) -#define LPC_EMC_BASE (LPC_AHB_BASE + 0x1C000) - -#define LPC_EEPROM_BASE (LPC_FLASH_BASE+ 0x200080) - - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) -#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) -#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) -#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) -#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) -#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) -#define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE ) -#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) -#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) -#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) -#define LPC_UART4 ((LPC_UART4_TypeDef *) LPC_UART4_BASE ) -#define LPC_PWM0 ((LPC_PWM_TypeDef *) LPC_PWM0_BASE ) -#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) -#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) -#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) -#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) -#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) -#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) -#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) -#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) -#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) -#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) -#define LPC_SSP2 ((LPC_SSP_TypeDef *) LPC_SSP2_BASE ) -#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) -#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) -#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) -#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) -#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) -#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) -#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) -#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) -#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) -#define LPC_MCI ((LPC_MCI_TypeDef *) LPC_MCI_BASE ) -#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) -#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) -#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) -#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) -#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) -#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) -#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) -#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) -#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) -#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) -#define LPC_LCD ((LPC_LCD_TypeDef *) LPC_LCD_BASE ) -#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) -#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) -#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) -#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) -#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) -#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) -#define LPC_GPIO5 ((LPC_GPIO_TypeDef *) LPC_GPIO5_BASE ) -#define LPC_EMC ((LPC_EMC_TypeDef *) LPC_EMC_BASE ) -#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE ) -#define LPC_EEPROM ((LPC_EEPROM_TypeDef *) LPC_EEPROM_BASE ) - -#endif // __LPC177x_8x_H__ diff --git a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_iram_iar.icf b/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_iram_iar.icf deleted file mode 100644 index 7da727d4c7b..00000000000 --- a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_iram_iar.icf +++ /dev/null @@ -1,34 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x10000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x00000000; -define symbol __ICFEDIT_region_RAM_start__ = 0x10000140; -define symbol __ICFEDIT_region_RAM_end__ = 0x1000FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define symbol _AHB_RAM_start__ = 0x20080000; -define symbol _AHB_RAM_end__ = 0x200BFFFF; -define region AHB_RAM_region = mem:[from _AHB_RAM_start__ to _AHB_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { section .intvec }; -place in RAM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in AHB_RAM_region { section USB_RAM }; diff --git a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_irom_iar.icf b/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_irom_iar.icf deleted file mode 100644 index e68e2b0a621..00000000000 --- a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_irom_iar.icf +++ /dev/null @@ -1,35 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x10000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x1000FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define symbol _AHB_RAM_start__ = 0x20080000; -define symbol _AHB_RAM_end__ = 0x200BFFFF; -define region AHB_RAM_region = mem:[from _AHB_RAM_start__ to _AHB_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy with packing = zeros { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { section .intvec }; -place at address mem:0x2FC { section CRPKEY }; -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in AHB_RAM_region { section USB_RAM }; diff --git a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/startup/arm/startup_LPC177x_8x.s b/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/startup/arm/startup_LPC177x_8x.s deleted file mode 100644 index b9edb715c00..00000000000 --- a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/startup/arm/startup_LPC177x_8x.s +++ /dev/null @@ -1,301 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC177x_8x.s -; * @purpose: CMSIS Cortex-M3 Core Device Startup File -; * for the NXP LPC177x_8x Device Series -; * @version: V1.20 -; * @date: 07. October 2010 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2010 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000200 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WDT_IRQHandler ; 16: Watchdog Timer - DCD TIMER0_IRQHandler ; 17: Timer0 - DCD TIMER1_IRQHandler ; 18: Timer1 - DCD TIMER2_IRQHandler ; 19: Timer2 - DCD TIMER3_IRQHandler ; 20: Timer3 - DCD UART0_IRQHandler ; 21: UART0 - DCD UART1_IRQHandler ; 22: UART1 - DCD UART2_IRQHandler ; 23: UART2 - DCD UART3_IRQHandler ; 24: UART3 - DCD PWM1_IRQHandler ; 25: PWM1 - DCD I2C0_IRQHandler ; 26: I2C0 - DCD I2C1_IRQHandler ; 27: I2C1 - DCD I2C2_IRQHandler ; 28: I2C2 - DCD SPIFI_IRQHandler ; 29: SPIFI - DCD SSP0_IRQHandler ; 30: SSP0 - DCD SSP1_IRQHandler ; 31: SSP1 - DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL) - DCD RTC_IRQHandler ; 33: Real Time Clock - DCD EINT0_IRQHandler ; 34: External Interrupt 0 - DCD EINT1_IRQHandler ; 35: External Interrupt 1 - DCD EINT2_IRQHandler ; 36: External Interrupt 2 - DCD EINT3_IRQHandler ; 37: External Interrupt 3 - DCD ADC_IRQHandler ; 38: A/D Converter - DCD BOD_IRQHandler ; 39: Brown-Out Detect - DCD USB_IRQHandler ; 40: USB - DCD CAN_IRQHandler ; 41: CAN - DCD DMA_IRQHandler ; 42: General Purpose DMA - DCD I2S_IRQHandler ; 43: I2S - DCD ENET_IRQHandler ; 44: Ethernet - DCD MCI_IRQHandler ; 45: SD/MMC card I/F - DCD MCPWM_IRQHandler ; 46: Motor Control PWM - DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface - DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) - DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup - DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup - DCD UART4_IRQHandler ; 51: UART4 - DCD SSP2_IRQHandler ; 52: SSP2 - DCD LCD_IRQHandler ; 53: LCD - DCD GPIO_IRQHandler ; 54: GPIO - DCD PWM0_IRQHandler ; 55: PWM0 - DCD EEPROM_IRQHandler ; 56: EEPROM - - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WDT_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT PWM1_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - EXPORT SPIFI_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT PLL0_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT EINT0_IRQHandler [WEAK] - EXPORT EINT1_IRQHandler [WEAK] - EXPORT EINT2_IRQHandler [WEAK] - EXPORT EINT3_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT USB_IRQHandler [WEAK] - EXPORT CAN_IRQHandler [WEAK] - EXPORT DMA_IRQHandler [WEAK] - EXPORT I2S_IRQHandler [WEAK] - EXPORT ENET_IRQHandler [WEAK] - EXPORT MCI_IRQHandler [WEAK] - EXPORT MCPWM_IRQHandler [WEAK] - EXPORT QEI_IRQHandler [WEAK] - EXPORT PLL1_IRQHandler [WEAK] - EXPORT USBActivity_IRQHandler [WEAK] - EXPORT CANActivity_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT SSP2_IRQHandler [WEAK] - EXPORT LCD_IRQHandler [WEAK] - EXPORT GPIO_IRQHandler [WEAK] - EXPORT PWM0_IRQHandler [WEAK] - EXPORT EEPROM_IRQHandler [WEAK] - -WDT_IRQHandler -TIMER0_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -UART3_IRQHandler -PWM1_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -I2C2_IRQHandler -SPIFI_IRQHandler -SSP0_IRQHandler -SSP1_IRQHandler -PLL0_IRQHandler -RTC_IRQHandler -EINT0_IRQHandler -EINT1_IRQHandler -EINT2_IRQHandler -EINT3_IRQHandler -ADC_IRQHandler -BOD_IRQHandler -USB_IRQHandler -CAN_IRQHandler -DMA_IRQHandler -I2S_IRQHandler -ENET_IRQHandler -MCI_IRQHandler -MCPWM_IRQHandler -QEI_IRQHandler -PLL1_IRQHandler -USBActivity_IRQHandler -CANActivity_IRQHandler -UART4_IRQHandler -SSP2_IRQHandler -LCD_IRQHandler -GPIO_IRQHandler -PWM0_IRQHandler -EEPROM_IRQHandler - - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - - END diff --git a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/startup/gcc/startup_LPC177x_8x.s b/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/startup/gcc/startup_LPC177x_8x.s deleted file mode 100644 index df828cc28da..00000000000 --- a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/startup/gcc/startup_LPC177x_8x.s +++ /dev/null @@ -1,269 +0,0 @@ -/*****************************************************************************/ -/* startup_LPC17xx.s: Startup file for LPC17xx device series */ -/*****************************************************************************/ -/* Version: CodeSourcery Sourcery G++ Lite (with CS3) */ -/*****************************************************************************/ - - -/* -//*** <<< Use Configuration Wizard in Context Menu >>> *** -*/ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - - .word _sidata - .word _sdata - .word _edata - .word _sbss - .word _ebss - -/* -// Stack Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - - .equ Stack_Size, 0x00000200 - .section .stack, "w" - .align 3 - .globl __cs3_stack_mem - .globl __cs3_stack_size -__cs3_stack_mem: - .if Stack_Size - .space Stack_Size - .endif - .size __cs3_stack_mem, . - __cs3_stack_mem - .set __cs3_stack_size, . - __cs3_stack_mem - -/* Vector Table */ - - .section .interrupt_vector - .globl __cs3_interrupt_vector_cortex_m - .type __cs3_interrupt_vector_cortex_m, %object - -__cs3_interrupt_vector_cortex_m: - .long _estack /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External Interrupts */ - .long WDT_IRQHandler /* 16: Watchdog Timer */ - .long TIMER0_IRQHandler /* 17: Timer0 */ - .long TIMER1_IRQHandler /* 18: Timer1 */ - .long TIMER2_IRQHandler /* 19: Timer2 */ - .long TIMER3_IRQHandler /* 20: Timer3 */ - .long UART0_IRQHandler /* 21: UART0 */ - .long UART1_IRQHandler /* 22: UART1 */ - .long UART2_IRQHandler /* 23: UART2 */ - .long UART3_IRQHandler /* 24: UART3 */ - .long PWM1_IRQHandler /* 25: PWM1 */ - .long I2C0_IRQHandler /* 26: I2C0 */ - .long I2C1_IRQHandler /* 27: I2C1 */ - .long I2C2_IRQHandler /* 28: I2C2 */ - .long SPIFI_IRQHandler /* 29: SPIFI */ - .long SSP0_IRQHandler /* 30: SSP0 */ - .long SSP1_IRQHandler /* 31: SSP1 */ - .long PLL0_IRQHandler /* 32: PLL0 Lock (Main PLL) */ - .long RTC_IRQHandler /* 33: Real Time Clock */ - .long EINT0_IRQHandler /* 34: External Interrupt 0 */ - .long EINT1_IRQHandler /* 35: External Interrupt 1 */ - .long EINT2_IRQHandler /* 36: External Interrupt 2 */ - .long EINT3_IRQHandler /* 37: External Interrupt 3 */ - .long ADC_IRQHandler /* 38: A/D Converter */ - .long BOD_IRQHandler /* 39: Brown-Out Detect */ - .long USB_IRQHandler /* 40: USB */ - .long CAN_IRQHandler /* 41: CAN */ - .long DMA_IRQHandler /* 42: General Purpose DMA */ - .long I2S_IRQHandler /* 43: I2S */ - .long ENET_IRQHandler /* 44: Ethernet */ - .long MCI_IRQHandler /* 45: SD/MMC Card */ - .long MCPWM_IRQHandler /* 46: Motor Control PWM */ - .long QEI_IRQHandler /* 47: Quadrature Encoder Interface */ - .long PLL1_IRQHandler /* 48: PLL1 Lock (USB PLL) */ - .long USBActivity_IRQHandler /* 49: USB Activity */ - .long CANActivity_IRQHandler /* 50: CAN Activity */ - .long UART4_IRQHandler /* 51: UART4 */ - .long SSP2_IRQHandler /* 52: SSP2 */ - .long LCD_IRQHandler /* 53: LCD */ - .long GPIO_IRQHandler /* 54: GPIO */ - .long PWM0_IRQHandler /* 55: PWM0 */ - .long EEPROM_IRQHandler /* 56: EEPROM */ - - .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m - - -/* Reset Handler */ - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - .fnstart -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - add r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - add r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call the application's entry point.*/ - bl main - bx lr - - .pool - .cantunwind - .fnend - .size Reset_Handler,.-Reset_Handler - - .section ".text" - -/* Exception Handlers */ - - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - B . - .size NMI_Handler, . - NMI_Handler - - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - B . - .size HardFault_Handler, . - HardFault_Handler - - .weak MemManage_Handler - .type MemManage_Handler, %function -MemManage_Handler: - B . - .size MemManage_Handler, . - MemManage_Handler - - .weak BusFault_Handler - .type BusFault_Handler, %function -BusFault_Handler: - B . - .size BusFault_Handler, . - BusFault_Handler - - .weak UsageFault_Handler - .type UsageFault_Handler, %function -UsageFault_Handler: - B . - .size UsageFault_Handler, . - UsageFault_Handler - - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - B . - .size SVC_Handler, . - SVC_Handler - - .weak DebugMon_Handler - .type DebugMon_Handler, %function -DebugMon_Handler: - B . - .size DebugMon_Handler, . - DebugMon_Handler - - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - B . - .size PendSV_Handler, . - PendSV_Handler - - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - B . - .size SysTick_Handler, . - SysTick_Handler - - -/* IRQ Handlers */ - - .globl Default_Handler - .type Default_Handler, %function -Default_Handler: - B . - .size Default_Handler, . - Default_Handler - - .macro IRQ handler - .weak \handler - .set \handler, Default_Handler - .endm - - IRQ WDT_IRQHandler - IRQ TIMER0_IRQHandler - IRQ TIMER1_IRQHandler - IRQ TIMER2_IRQHandler - IRQ TIMER3_IRQHandler - IRQ UART0_IRQHandler - IRQ UART1_IRQHandler - IRQ UART2_IRQHandler - IRQ UART3_IRQHandler - IRQ PWM1_IRQHandler - IRQ I2C0_IRQHandler - IRQ I2C1_IRQHandler - IRQ I2C2_IRQHandler - IRQ SPIFI_IRQHandler - IRQ SSP0_IRQHandler - IRQ SSP1_IRQHandler - IRQ PLL0_IRQHandler - IRQ RTC_IRQHandler - IRQ EINT0_IRQHandler - IRQ EINT1_IRQHandler - IRQ EINT2_IRQHandler - IRQ EINT3_IRQHandler - IRQ ADC_IRQHandler - IRQ BOD_IRQHandler - IRQ USB_IRQHandler - IRQ CAN_IRQHandler - IRQ DMA_IRQHandler - IRQ I2S_IRQHandler - IRQ ENET_IRQHandler - IRQ MCI_IRQHandler - IRQ MCPWM_IRQHandler - IRQ QEI_IRQHandler - IRQ PLL1_IRQHandler - IRQ USBActivity_IRQHandler - IRQ CANActivity_IRQHandler - IRQ UART4_IRQHandler - IRQ SSP2_IRQHandler - IRQ LCD_IRQHandler - IRQ GPIO_IRQHandler - IRQ PWM0_IRQHandler - IRQ EEPROM_IRQHandler - - .end diff --git a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/startup/iar/startup_LPC177x_8x.s b/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/startup/iar/startup_LPC177x_8x.s deleted file mode 100644 index 1dd622ceaa6..00000000000 --- a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/startup/iar/startup_LPC177x_8x.s +++ /dev/null @@ -1,393 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC177x_8x.s -; * @purpose: CMSIS Cortex-M3 Core Device Startup File -; * for the NXP LPC17xx Device Series -; * @version: V1.03 -; * @date: 09. February 2010 -; *---------------------------------------------------------------------------- -; * -; * Copyright (C) 2010 ARM Limited. All rights reserved. -; * -; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_IRQHandler ; 16: Watchdog Timer - DCD TIMER0_IRQHandler ; 17: Timer0 - DCD TIMER1_IRQHandler ; 18: Timer1 - DCD TIMER2_IRQHandler ; 19: Timer2 - DCD TIMER3_IRQHandler ; 20: Timer3 - DCD UART0_IRQHandler ; 21: UART0 - DCD UART1_IRQHandler ; 22: UART1 - DCD UART2_IRQHandler ; 23: UART2 - DCD UART3_IRQHandler ; 24: UART3 - DCD PWM1_IRQHandler ; 25: PWM1 - DCD I2C0_IRQHandler ; 26: I2C0 - DCD I2C1_IRQHandler ; 27: I2C1 - DCD I2C2_IRQHandler ; 28: I2C2 - DCD SPIFI_IRQHandler ; 29: SPIFI - DCD SSP0_IRQHandler ; 30: SSP0 - DCD SSP1_IRQHandler ; 31: SSP1 - DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL) - DCD RTC_IRQHandler ; 33: Real Time Clock - DCD EINT0_IRQHandler ; 34: External Interrupt 0 - DCD EINT1_IRQHandler ; 35: External Interrupt 1 - DCD EINT2_IRQHandler ; 36: External Interrupt 2 - DCD EINT3_IRQHandler ; 37: External Interrupt 3 - DCD ADC_IRQHandler ; 38: A/D Converter - DCD BOD_IRQHandler ; 39: Brown-Out Detect - DCD USB_IRQHandler ; 40: USB - DCD CAN_IRQHandler ; 41: CAN - DCD DMA_IRQHandler ; 42: General Purpose DMA - DCD I2S_IRQHandler ; 43: I2S - DCD ENET_IRQHandler ; 44: Ethernet - DCD MCI_IRQHandler ; 45: MCI Card - DCD MCPWM_IRQHandler ; 46: Motor Control PWM - DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface - DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) - DCD USBActivity_IRQHandler ; 49: USB Activity Interrupt - DCD CANActivity_IRQHandler ; 50: CAN Activity Interrupt - DCD UART4_IRQHandler ; 51: UART4 - DCD SSP2_IRQHandler ; 52: SSP2 - DCD LCD_IRQHandler ; 53: LCD - DCD GPIO_IRQHandler ; 54: GPIO - DCD PWM0_IRQHandler ; 55: PWM0 - DCD EEPROM_IRQHandler ; 56: EEPROM - - - - -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WDT_IRQHandler - SECTION .text:CODE:REORDER(1) -WDT_IRQHandler - B WDT_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:REORDER(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:REORDER(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK UART0_IRQHandler - SECTION .text:CODE:REORDER(1) -UART0_IRQHandler - B UART0_IRQHandler - - PUBWEAK UART1_IRQHandler - SECTION .text:CODE:REORDER(1) -UART1_IRQHandler - B UART1_IRQHandler - - PUBWEAK UART2_IRQHandler - SECTION .text:CODE:REORDER(1) -UART2_IRQHandler - B UART2_IRQHandler - - PUBWEAK UART3_IRQHandler - SECTION .text:CODE:REORDER(1) -UART3_IRQHandler - B UART3_IRQHandler - - PUBWEAK PWM1_IRQHandler - SECTION .text:CODE:REORDER(1) -PWM1_IRQHandler - B PWM1_IRQHandler - - PUBWEAK I2C0_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C0_IRQHandler - B I2C0_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK I2C2_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C2_IRQHandler - B I2C2_IRQHandler - - PUBWEAK SPIFI_IRQHandler - SECTION .text:CODE:REORDER(1) -SPIFI_IRQHandler - B SPIFI_IRQHandler - - PUBWEAK SSP0_IRQHandler - SECTION .text:CODE:REORDER(1) -SSP0_IRQHandler - B SSP0_IRQHandler - - PUBWEAK SSP1_IRQHandler - SECTION .text:CODE:REORDER(1) -SSP1_IRQHandler - B SSP1_IRQHandler - - PUBWEAK PLL0_IRQHandler - SECTION .text:CODE:REORDER(1) -PLL0_IRQHandler - B PLL0_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK EINT0_IRQHandler - SECTION .text:CODE:REORDER(1) -EINT0_IRQHandler - B EINT0_IRQHandler - - PUBWEAK EINT1_IRQHandler - SECTION .text:CODE:REORDER(1) -EINT1_IRQHandler - B EINT1_IRQHandler - - PUBWEAK EINT2_IRQHandler - SECTION .text:CODE:REORDER(1) -EINT2_IRQHandler - B EINT2_IRQHandler - - PUBWEAK EINT3_IRQHandler - SECTION .text:CODE:REORDER(1) -EINT3_IRQHandler - B EINT3_IRQHandler - - PUBWEAK ADC_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC_IRQHandler - B ADC_IRQHandler - - PUBWEAK BOD_IRQHandler - SECTION .text:CODE:REORDER(1) -BOD_IRQHandler - B BOD_IRQHandler - - PUBWEAK USB_IRQHandler - SECTION .text:CODE:REORDER(1) -USB_IRQHandler - B USB_IRQHandler - - PUBWEAK CAN_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN_IRQHandler - B CAN_IRQHandler - - PUBWEAK DMA_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA_IRQHandler - B DMA_IRQHandler - - PUBWEAK I2S_IRQHandler - SECTION .text:CODE:REORDER(1) -I2S_IRQHandler - B I2S_IRQHandler - - PUBWEAK ENET_IRQHandler - SECTION .text:CODE:REORDER(1) -ENET_IRQHandler - B ENET_IRQHandler - - PUBWEAK MCI_IRQHandler - SECTION .text:CODE:REORDER(1) -MCI_IRQHandler - B MCI_IRQHandler - - PUBWEAK MCPWM_IRQHandler - SECTION .text:CODE:REORDER(1) -MCPWM_IRQHandler - B MCPWM_IRQHandler - - PUBWEAK QEI_IRQHandler - SECTION .text:CODE:REORDER(1) -QEI_IRQHandler - B QEI_IRQHandler - - PUBWEAK PLL1_IRQHandler - SECTION .text:CODE:REORDER(1) -PLL1_IRQHandler - B PLL1_IRQHandler - - PUBWEAK USBActivity_IRQHandler - SECTION .text:CODE:REORDER(1) -USBActivity_IRQHandler - B USBActivity_IRQHandler - - PUBWEAK CANActivity_IRQHandler - SECTION .text:CODE:REORDER(1) -CANActivity_IRQHandler - B CANActivity_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:REORDER(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK SSP2_IRQHandler - SECTION .text:CODE:REORDER(1) -SSP2_IRQHandler - B SSP2_IRQHandler - - PUBWEAK LCD_IRQHandler - SECTION .text:CODE:REORDER(1) -LCD_IRQHandler - B LCD_IRQHandler - - PUBWEAK GPIO_IRQHandler - SECTION .text:CODE:REORDER(1) -GPIO_IRQHandler - B GPIO_IRQHandler - - PUBWEAK PWM0_IRQHandler - SECTION .text:CODE:REORDER(1) -PWM0_IRQHandler - B PWM0_IRQHandler - - PUBWEAK EEPROM_IRQHandler - SECTION .text:CODE:REORDER(1) -EEPROM_IRQHandler - B EEPROM_IRQHandler - - END diff --git a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/system_LPC177x_8x.c b/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/system_LPC177x_8x.c deleted file mode 100644 index 31ead15abf6..00000000000 --- a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/system_LPC177x_8x.c +++ /dev/null @@ -1,466 +0,0 @@ -/********************************************************************** -* $Id: system_LPC177x_8x.c 7485 2011-06-03 07:57:16Z sgg06786 $ system_LPC177x_8x.c 2011-06-02 -*//** -* @file system_LPC177x_8x.c -* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File -* for the NXP LPC177x_8x Device Series -* -* ARM Limited (ARM) is supplying this software for use with -* Cortex-M processor based microcontrollers. This file can be -* freely distributed within development tools that are supporting -* such ARM based processors. -* -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -#include -#include "LPC177x_8x.h" -#include "system_LPC177x_8x.h" - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ -/*--------------------- Clock Configuration ---------------------------------- -// -// Clock Configuration -// System Controls and Status Register (SCS) -// EMC_SHIFT: EMC Shift enable -// <0=> Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit -// <1=> Static CS addresses start at LSB 0 regardless of memory width -// EMC_RESET: EMC Reset disable -// <0=> EMC will be reset by any chip reset -// <1=> Portions of EMC will only be reset by POR or BOR -// EMC_BURST: EMC Burst disable -// MCIPWR_LEVEL: SD card interface signal SD_PWR Active Level selection -// <0=> SD_PWR is active low -// <1=> SD_PWR is active high -// OSCRANGE: Main Oscillator Range Select -// <0=> 1 MHz to 20 MHz -// <1=> 15 MHz to 25 MHz -// OSCEN: Main Oscillator enable -// -// -// Clock Source Select Register (CLKSRCSEL) -// CLKSRC: sysclk and PLL0 clock source selection -// <0=> Internal RC oscillator -// <1=> Main oscillator -// -// -// PLL0 Configuration (Main PLL) -// PLL0 Configuration Register (PLL0CFG) -// PLL out clock = (F_cco / (2 * P)) -// F_cco = (F_in * M * 2 * P) -// F_in must be in the range of 1 MHz to 25 MHz -// F_cco must be in the range of 9.75 MHz to 160 MHz -// MSEL: PLL Multiplier Selection -// M Value -// <1-32><#-1> -// PSEL: PLL Divider Selection -// P Value -// <0=> 1 -// <1=> 2 -// <2=> 4 -// <3=> 8 -// -// -// -// PLL1 Configuration (Alt PLL) -// PLL1 Configuration Register (PLL1CFG) -// PLL out clock = (F_cco / (2 * P)) -// F_cco = (F_in * M * 2 * P) -// F_in must be in the range of 1 MHz to 25 MHz -// F_cco must be in the range of 9.75 MHz to 160 MHz -// MSEL: PLL Multiplier Selection -// M Value -// <1-32><#-1> -// PSEL: PLL Divider Selection -// P Value -// <0=> 1 -// <1=> 2 -// <2=> 4 -// <3=> 8 -// -// -// -// CPU Clock Selection Register (CCLKSEL) -// CCLKDIV: CPU clock (CCLK) divider -// 0: The divider is turned off. No clock will be provided to the CPU -// n: The input clock is divided by n to produce the CPU clock -// <0-31> -// CCLKSEL: CPU clock divider input clock selection -// <0=> sysclk clock -// <1=> PLL0 clock -// -// -// USB Clock Selection Register (USBCLKSEL) -// USBDIV: USB clock (source PLL0) divider selection -// <0=> USB clock off -// <4=> PLL0 / 4 (PLL0 must be 192Mhz) -// <6=> PLL0 / 6 (PLL0 must be 288Mhz) -// USBSEL: USB clock divider input clock selection -// When CPU clock is selected, the USB can be accessed -// by software but cannot perform USB functions -// <0=> CPU clock -// <1=> PLL0 clock -// <2=> PLL1 clock -// -// -// EMC Clock Selection Register (EMCCLKSEL) -// EMCDIV: EMC clock selection -// <0=> CPU clock -// <1=> CPU clock / 2 -// -// -// Peripheral Clock Selection Register (PCLKSEL) -// PCLKDIV: APB Peripheral clock divider -// 0: The divider is turned off. No clock will be provided to APB peripherals -// n: The input clock is divided by n to produce the APB peripheral clock -// <0-31> -// -// -// Power Control for Peripherals Register (PCONP) -// PCLCD: LCD controller power/clock enable -// PCTIM0: Timer/Counter 0 power/clock enable -// PCTIM1: Timer/Counter 1 power/clock enable -// PCUART0: UART 0 power/clock enable -// PCUART1: UART 1 power/clock enable -// PCPWM0: PWM0 power/clock enable -// PCPWM1: PWM1 power/clock enable -// PCI2C0: I2C 0 interface power/clock enable -// PCUART4: UART 4 power/clock enable -// PCRTC: RTC and Event Recorder power/clock enable -// PCSSP1: SSP 1 interface power/clock enable -// PCEMC: External Memory Controller power/clock enable -// PCADC: A/D converter power/clock enable -// PCCAN1: CAN controller 1 power/clock enable -// PCCAN2: CAN controller 2 power/clock enable -// PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable -// PCMCPWM: Motor Control PWM power/clock enable -// PCQEI: Quadrature encoder interface power/clock enable -// PCI2C1: I2C 1 interface power/clock enable -// PCSSP2: SSP 2 interface power/clock enable -// PCSSP0: SSP 0 interface power/clock enable -// PCTIM2: Timer 2 power/clock enable -// PCTIM3: Timer 3 power/clock enable -// PCUART2: UART 2 power/clock enable -// PCUART3: UART 3 power/clock enable -// PCI2C2: I2C 2 interface power/clock enable -// PCI2S: I2S interface power/clock enable -// PCSDC: SD Card interface power/clock enable -// PCGPDMA: GPDMA function power/clock enable -// PCENET: Ethernet block power/clock enable -// PCUSB: USB interface power/clock enable -// -// -// Clock Output Configuration Register (CLKOUTCFG) -// CLKOUTSEL: Clock Source for CLKOUT Selection -// <0=> CPU clock -// <1=> Main Oscillator -// <2=> Internal RC Oscillator -// <3=> USB clock -// <4=> RTC Oscillator -// <5=> unused -// <6=> Watchdog Oscillator -// CLKOUTDIV: Output Clock Divider -// <1-16><#-1> -// CLKOUT_EN: CLKOUT enable -// -// -// -*/ -#define CLOCK_SETUP 1 -#define SCS_Val 0x00000021 -#define CLKSRCSEL_Val 0x00000001 -#define PLL0_SETUP 1 -#define PLL0CFG_Val 0x00000009 -#define PLL1_SETUP 1 -#define PLL1CFG_Val 0x00000023 -#define CCLKSEL_Val (0x00000001|(1<<8)) -#define USBCLK_SETUP 1 -#define USBCLKSEL_Val (0x00000001|(0x02<<8)) -#define EMCCLKSEL_Val 0x00000001 -#define PCLKSEL_Val 0x00000002 -#define PCONP_Val 0x042887DE -#define CLKOUTCFG_Val 0x00000100 - - -/*--------------------- Flash Accelerator Configuration ---------------------- -// -// Flash Accelerator Configuration -// FLASHTIM: Flash Access Time -// <0=> 1 CPU clock (for CPU clock up to 20 MHz) -// <1=> 2 CPU clocks (for CPU clock up to 40 MHz) -// <2=> 3 CPU clocks (for CPU clock up to 60 MHz) -// <3=> 4 CPU clocks (for CPU clock up to 80 MHz) -// <4=> 5 CPU clocks (for CPU clock up to 100 MHz) -// <5=> 6 CPU clocks (for any CPU clock) -// -*/ -#define FLASH_SETUP 1 -#define FLASHCFG_Val 0x00005000 - -/*---------------------------------------------------------------------------- - Check the register settings - *----------------------------------------------------------------------------*/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) -#define CHECK_RSVD(val, mask) (val & mask) - -/* Clock Configuration -------------------------------------------------------*/ -#if (CHECK_RSVD((SCS_Val), ~0x0000003F)) - #error "SCS: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1)) - #error "CLKSRCSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((PLL0CFG_Val), ~0x0000007F)) - #error "PLL0CFG: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) - #error "PLL1CFG: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((CCLKSEL_Val), ~0x0000011F)) - #error "CCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F)) - #error "USBCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001)) - #error "EMCCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F)) - #error "PCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF)) - #error "PCONP: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) - #error "CLKOUTCFG: Invalid values of reserved bits!" -#endif - -/* Flash Accelerator Configuration -------------------------------------------*/ -#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000)) - #warning "FLASHCFG: Invalid values of reserved bits!" -#endif - - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ -/* pll_out_clk = F_cco / (2 × P) - F_cco = pll_in_clk × M × 2 × P */ -#define __M ((PLL0CFG_Val & 0x1F) + 1) -#define __PLL0_CLK(__F_IN) (__F_IN * __M) -#define __CCLK_DIV (CCLKSEL_Val & 0x1F) -#define __PCLK_DIV (PCLKSEL_Val & 0x1F) -#define __ECLK_DIV ((EMCCLKSEL_Val & 0x01) + 1) - -/* Determine core clock frequency according to settings */ -#if (CLOCK_SETUP) /* Clock Setup */ - - #if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0) - #error "Main Oscillator is selected as clock source but is not enabled!" - #endif - - #if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0) - #error "Main PLL is selected as clock source but is not enabled!" - #endif - - #if ((CCLKSEL_Val & 0x100) == 0) /* cclk = sysclk */ - #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */ - #define __CORE_CLK (IRC_OSC / __CCLK_DIV) - #define __PER_CLK (IRC_OSC/ __PCLK_DIV) - #define __EMC_CLK (IRC_OSC/ __ECLK_DIV) - #else /* sysclk = osc_clk */ - #define __CORE_CLK (OSC_CLK / __CCLK_DIV) - #define __PER_CLK (OSC_CLK/ __PCLK_DIV) - #define __EMC_CLK (OSC_CLK/ __ECLK_DIV) - #endif - #else /* cclk = pll_clk */ - #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */ - #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV) - #define __PER_CLK (__PLL0_CLK(IRC_OSC) / __PCLK_DIV) - #define __EMC_CLK (__PLL0_CLK(IRC_OSC) / __ECLK_DIV) - #else /* sysclk = osc_clk */ - #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV) - #define __PER_CLK (__PLL0_CLK(OSC_CLK) / __PCLK_DIV) - #define __EMC_CLK (__PLL0_CLK(OSC_CLK) / __ECLK_DIV) - #endif - #endif - -#else - #define __CORE_CLK (IRC_OSC) - #define __PER_CLK (IRC_OSC) - #define __EMC_CLK (IRC_OSC) -#endif - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ -uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk) */ -uint32_t EMCClock = __EMC_CLK; /*!< EMC Clock Frequency */ -uint32_t USBClock = (48000000UL); /*!< USB Clock Frequency - this value will - be updated after call SystemCoreClockUpdate, should be 48MHz*/ - - -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ - /* Determine clock frequency according to clock register values */ - if ((LPC_SC->CCLKSEL &0x100) == 0) { /* cclk = sysclk */ - if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */ - SystemCoreClock = (IRC_OSC / (LPC_SC->CCLKSEL & 0x1F)); - PeripheralClock = (IRC_OSC / (LPC_SC->PCLKSEL & 0x1F)); - EMCClock = (IRC_OSC / ((LPC_SC->EMCCLKSEL & 0x01)+1)); - } - else { /* sysclk = osc_clk */ - if ((LPC_SC->SCS & 0x40) == 0) { - SystemCoreClock = 0; /* this should never happen! */ - PeripheralClock = 0; - EMCClock = 0; - } - else { - SystemCoreClock = (OSC_CLK / (LPC_SC->CCLKSEL & 0x1F)); - PeripheralClock = (OSC_CLK / (LPC_SC->PCLKSEL & 0x1F)); - EMCClock = (OSC_CLK / ((LPC_SC->EMCCLKSEL & 0x01)+1)); - } - } - } - else { /* cclk = pll_clk */ - if ((LPC_SC->PLL0STAT & 0x100) == 0) { /* PLL0 not enabled */ - SystemCoreClock = 0; /* this should never happen! */ - PeripheralClock = 0; - EMCClock = 0; - } - else { - if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */ - SystemCoreClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->CCLKSEL & 0x1F)); - PeripheralClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->PCLKSEL & 0x1F)); - EMCClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / ((LPC_SC->EMCCLKSEL & 0x01)+1)); - } - else { /* sysclk = osc_clk */ - if ((LPC_SC->SCS & 0x40) == 0) { - SystemCoreClock = 0; /* this should never happen! */ - PeripheralClock = 0; - EMCClock = 0; - } - else { - SystemCoreClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->CCLKSEL & 0x1F)); - PeripheralClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->PCLKSEL & 0x1F)); - EMCClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / ((LPC_SC->EMCCLKSEL & 0x01)+1)); - } - } - } - } - /* ---update USBClock------------------*/ - if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider - { - switch (LPC_SC->USBCLKSEL & 0x1F) - { - case 0: - USBClock = 0; //no clock will be provided to the USB subsystem - break; - case 4: - case 6: - if(LPC_SC->CLKSRCSEL & 0x01) //pll_clk_in = main_osc - USBClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->USBCLKSEL & 0x1F)); - else //pll_clk_in = irc_clk - USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->USBCLKSEL & 0x1F)); - break; - default: - USBClock = 0; /* this should never happen! */ - } - } - else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1) - { - if(LPC_SC->CLKSRCSEL & 0x01) //pll1_clk_in = main_osc - USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1)); - else //pll1_clk_in = irc_clk - USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1)); - } - else - USBClock = 0; /* this should never happen! */ -} - - /* Determine clock frequency according to clock register values */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) -{ -#if (CLOCK_SETUP) /* Clock Setup */ - LPC_SC->SCS = SCS_Val; - if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ - while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ - } - - LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for sysclk/PLL0*/ - -#if (PLL0_SETUP) - LPC_SC->PLL0CFG = PLL0CFG_Val; - LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0 */ -#endif - -#if (PLL1_SETUP) - LPC_SC->PLL1CFG = PLL1CFG_Val; - LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ -#endif - - LPC_SC->CCLKSEL = CCLKSEL_Val; /* Setup Clock Divider */ - LPC_SC->USBCLKSEL = USBCLKSEL_Val; /* Setup USB Clock Divider */ - LPC_SC->EMCCLKSEL = EMCCLKSEL_Val; /* EMC Clock Selection */ - LPC_SC->PCLKSEL = PCLKSEL_Val; /* Peripheral Clock Selection */ - LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ - LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ -#endif - -#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ - LPC_SC->FLASHCFG = FLASHCFG_Val|0x03A; -#endif -#ifdef __RAM_MODE__ - SCB->VTOR = 0x10000000 & 0x3FFFFF80; -#else - SCB->VTOR = 0x00000000 & 0x3FFFFF80; -#endif -} diff --git a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/system_LPC177x_8x.h b/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/system_LPC177x_8x.h deleted file mode 100644 index 763f72c3ee2..00000000000 --- a/bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/system_LPC177x_8x.h +++ /dev/null @@ -1,83 +0,0 @@ -/********************************************************************** -* $Id: system_LPC177x_8x.h 7485 2011-06-03 07:57:16Z sgg06786 $ system_LPC177x_8x.h 2011-06-02 -*//** -* @file system_LPC177x_8x.h -* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File -* for the NXP LPC177x_8x Device Series -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -#ifndef __SYSTEM_LPC177x_8x_H -#define __SYSTEM_LPC177x_8x_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */ -extern uint32_t EMCClock; /*!< EMC Clock */ -extern uint32_t USBClock; /*!< USB Frequency */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (12000000UL) /* Oscillator frequency */ -#define OSC_CLK ( XTAL) /* Main oscillator frequency */ -#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */ -#define IRC_OSC (12000000UL) /* Internal RC oscillator frequency */ -#define WDT_OSC ( 500000UL) /* Internal WDT oscillator frequency */ - - - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC177x_8x_H */ diff --git a/bsp/nxp/lpc/lpc178x/CMSIS/License.doc b/bsp/nxp/lpc/lpc178x/CMSIS/License.doc deleted file mode 100644 index b6b8acecc13..00000000000 Binary files a/bsp/nxp/lpc/lpc178x/CMSIS/License.doc and /dev/null differ diff --git a/bsp/nxp/lpc/lpc178x/CMSIS/SConscript b/bsp/nxp/lpc/lpc178x/CMSIS/SConscript deleted file mode 100644 index a0d35a48537..00000000000 --- a/bsp/nxp/lpc/lpc178x/CMSIS/SConscript +++ /dev/null @@ -1,20 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -src = Glob('*.c') -src = ['CM3/CoreSupport/core_cm3.c', 'CM3/DeviceSupport/NXP/LPC177x_8x/system_LPC177x_8x.c'] -CPPPATH = [cwd + '/CM3/CoreSupport', cwd + '/CM3/DeviceSupport/NXP/LPC177x_8x/'] - -# add for startup script -if rtconfig.PLATFORM in ['gcc']: - src += ['CM3/DeviceSupport/NXP/LPC177x_8x/startup/gcc/startup_LPC177x_8x.s'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - src += ['CM3/DeviceSupport/NXP/LPC177x_8x/startup/arm/startup_LPC177x_8x.s'] -elif rtconfig.PLATFORM in ['iccarm']: - src += ['CM3/DeviceSupport/NXP/LPC177x_8x/startup/iar/startup_LPC177x_8x.s'] - -group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/nxp/lpc/lpc178x/Kconfig b/bsp/nxp/lpc/lpc178x/Kconfig index 8079ffd5d9e..216bdca3748 100644 --- a/bsp/nxp/lpc/lpc178x/Kconfig +++ b/bsp/nxp/lpc/lpc178x/Kconfig @@ -14,6 +14,7 @@ config SOC_LPC178 select ARCH_ARM_CORTEX_M3 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select PKG_USING_NXP_LPC_DRIVER default y source "$(BSP_DIR)/drivers/Kconfig" diff --git a/bsp/nxp/lpc/lpc178x/SConstruct b/bsp/nxp/lpc/lpc178x/SConstruct index 6677545fbb2..caff42aef56 100644 --- a/bsp/nxp/lpc/lpc178x/SConstruct +++ b/bsp/nxp/lpc/lpc178x/SConstruct @@ -10,6 +10,24 @@ else: sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] from building import * +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "nxp-lpc-series-latest"), + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n==============================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("==============================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + + TARGET = 'rtthread-%s.%s' % (rtconfig.BOARD_NAME, rtconfig.TARGET_EXT) DefaultEnvironment(tools=[]) if rtconfig.PLATFORM == 'armcc': diff --git a/bsp/nxp/lpc/lpc408x/Kconfig b/bsp/nxp/lpc/lpc408x/Kconfig index a196d043d0f..1994e0b7f2b 100644 --- a/bsp/nxp/lpc/lpc408x/Kconfig +++ b/bsp/nxp/lpc/lpc408x/Kconfig @@ -14,6 +14,7 @@ config SOC_LPC4088 select ARCH_ARM_CORTEX_M4 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select PKG_USING_NXP_LPC_DRIVER default y source "$(BSP_DIR)/drivers/Kconfig" diff --git a/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/arm_common_tables.h b/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/arm_common_tables.h deleted file mode 100644 index 7245c4f12bb..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/arm_common_tables.h +++ /dev/null @@ -1,35 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 11. November 2010 -* $Revision: V1.0.2 -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern uint16_t armBitRevTable[256]; -extern q15_t armRecipTableQ15[64]; -extern q31_t armRecipTableQ31[64]; -extern const q31_t realCoefAQ31[1024]; -extern const q31_t realCoefBQ31[1024]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/arm_math.h b/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/arm_math.h deleted file mode 100644 index b33ae193707..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7062 +0,0 @@ -/* ---------------------------------------------------------------------- - * Copyright (C) 2010 ARM Limited. All rights reserved. - * - * $Date: 15. July 2011 - * $Revision: V1.0.10 - * - * Project: CMSIS DSP Library - * Title: arm_math.h - * - * Description: Public header file for CMSIS DSP Library - * - * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 - * - * Version 1.0.10 2011/7/15 - * Big Endian support added and Merged M0 and M3/M4 Source code. - * - * Version 1.0.3 2010/11/29 - * Re-organized the CMSIS folders and updated documentation. - * - * Version 1.0.2 2010/11/11 - * Documentation updated. - * - * Version 1.0.1 2010/10/05 - * Production release and review comments incorporated. - * - * Version 1.0.0 2010/09/20 - * Production release and review comments incorporated. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of modules each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Processor Support - * - * The library is completely written in C and is fully CMSIS compliant. - * High performance is achieved through maximum use of Cortex-M4 intrinsics. - * - * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor, - * with the DSP intrinsics being emulated through software. - * - * - * Toolchain Support - * - * The library has been developed and tested with MDK-ARM version 4.21. - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Using the Library - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 depending on the target processor in the application. - * - * Examples - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Building the Library - * - * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\DSP_Lib\Source\ARM folder. - * - arm_cortexM0b_math.uvproj - * - arm_cortexM0l_math.uvproj - * - arm_cortexM3b_math.uvproj - * - arm_cortexM3l_math.uvproj - * - arm_cortexM4b_math.uvproj - * - arm_cortexM4l_math.uvproj - * - arm_cortexM4bf_math.uvproj - * - arm_cortexM4lf_math.uvproj - * - * Each library project have differant pre-processor macros. - * - * ARM_MATH_CMx: - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on cortex-M0 target. - * - * ARM_MATH_BIG_ENDIAN: - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * ARM_MATH_MATRIX_CHECK: - * Define macro for checking on the input and output sizes of matrices - * - * ARM_MATH_ROUNDING: - * Define macro for rounding on support functions - * - * __FPU_PRESENT: - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - * - * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above. - * - * Copyright Notice - * - * Copyright (C) 2010 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - * @ingroup DSP_Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * @ingroup DSP_Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * @ingroup DSP_Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - * @ingroup DSP_Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * @ingroup DSP_Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the #define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - * @ingroup DSP_Functions - */ - -/** - * @defgroup groupController Controller Functions - * @ingroup DSP_Functions - */ - -/** - * @defgroup groupStats Statistics Functions - * @ingroup DSP_Functions - */ -/** - * @defgroup groupSupport Support Functions - * @ingroup DSP_Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * @ingroup DSP_Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - * @ingroup DSP_Lib - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined (ARM_MATH_CM4) - #include "core_cm4.h" -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" -#else -#include "ARMCM4.h" -#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" - #include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#define PI 3.14159265358979f - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x800000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#define __SIMD32(addr) (*(int32_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - - -#if defined (ARM_MATH_CM0) && defined ( __CC_ARM ) -#define __CLZ __clz -#endif - -#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) - - static __INLINE uint32_t __CLZ(q31_t data); - - - static __INLINE uint32_t __CLZ(q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return(count); - - } - -#endif - - /** - * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - - uint32_t out, tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = __CLZ(in) - 1; - } - else - { - signBits = __CLZ(-in) - 1; - } - - /* Convert input sample to 1.31 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = (uint32_t) (in >> 24u); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (q31_t) (((q63_t) in * out) >> 31u); - tempVal = 0x7FFFFFFF - tempVal; - /* 1.31 with exp 1 */ - //out = (q31_t) (((q63_t) out * tempVal) >> 30u); - out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - - } - - /** - * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - - uint32_t out = 0, tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = __CLZ(in) - 17; - } - else - { - signBits = __CLZ(-in) - 17; - } - - /* Convert input sample to 1.15 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = in >> 8; - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0; i < 2; i++) - { - tempVal = (q15_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFF - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0) - - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - - - } - -#endif /* end of ARM_MATH_CM0 */ - - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE q31_t __QADD8( - q31_t x, - q31_t y) - { - - q31_t sum; - q7_t r, s, t, u; - - r = (char) x; - s = (char) y; - - r = __SSAT((q31_t) (r + s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); - t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); - u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); - - sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | - (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); - - return sum; - - } - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB8( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s, t, u; - - r = (char) x; - s = (char) y; - - r = __SSAT((r - s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; - t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; - u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; - - sum = - (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF); - - return sum; - } - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE q31_t __QADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r + s, 16); - s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE q31_t __SHADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (s >> 1)); - s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r - s, 16); - s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __SHSUB16( - q31_t x, - q31_t y) - { - - q31_t diff; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (s >> 1)); - s = (((x >> 17) - (y >> 17)) << 16); - - diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return diff; - } - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE q31_t __QASX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE q31_t __SHASX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (y >> 17)); - s = (((x >> 17) + (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE q31_t __QSAX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE q31_t __SHSAX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (y >> 17)); - s = (((x >> 17) - (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMUSDX( - q31_t x, - q31_t y) - { - - return ((q31_t)(((short) x * (short) (y >> 16)) - - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE q31_t __SMUADX( - q31_t x, - q31_t y) - { - - return ((q31_t)(((short) x * (short) (y >> 16)) + - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE q31_t __QADD( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x + y); - } - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE q31_t __QSUB( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x - y); - } - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE q31_t __SMLAD( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE q31_t __SMLADX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMLSDX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum - ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE q63_t __SMLALD( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE q63_t __SMLALDX( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) y)) + - ((short) x * (short) (y >> 16)); - } - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE q31_t __SMUAD( - q31_t x, - q31_t y) - { - - return (((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE q31_t __SMUSD( - q31_t x, - q31_t y) - { - - return (-((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - - - -#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] *S points to an instance of the Q7 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] *S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - * @return none - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] *S points to an instance of the Q15 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] *S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] *S points to an instance of the Q31 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] *S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] *S points to an instance of the floating-point FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] *S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q15; - - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - - - } arm_biquad_casd_df1_inst_f32; - - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q31; - - - - /** - * @brief Floating-point matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q31 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point matrix scaling. - * @param[in] *pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] *pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t *pData); - - /** - * @brief Q15 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t *pData); - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t *pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - #ifdef ARM_MATH_CM0 - q15_t A1; - q15_t A2; - #else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ - #endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] *S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @return none - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @return none - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the q15 PID Control structure - * @return none - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; - float32_t x1; - float32_t xSpacing; - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - - /** - * @brief Processing function for the Q15 CFFT/CIFFT. - * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Initialization function for the Q15 CFFT/CIFFT. - * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Processing function for the Q31 CFFT/CIFFT. - * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Initialization function for the Q31 CFFT/CIFFT. - * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Processing function for the floating-point CFFT/CIFFT. - * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Initialization function for the floating-point CFFT/CIFFT. - * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - - - /*---------------------------------------------------------------------- - * Internal functions prototypes FFT function - ----------------------------------------------------------------------*/ - - /** - * @brief Core function for the floating-point CFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to the twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_f32( - float32_t * pSrc, - uint16_t fftLen, - float32_t * pCoef, - uint16_t twidCoefModifier); - - /** - * @brief Core function for the floating-point CIFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @param[in] onebyfftLen value of 1/fftLen. - * @return none. - */ - - void arm_radix4_butterfly_inverse_f32( - float32_t * pSrc, - uint16_t fftLen, - float32_t * pCoef, - uint16_t twidCoefModifier, - float32_t onebyfftLen); - - /** - * @brief In-place bit reversal function. - * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. - * @param[in] fftSize length of the FFT. - * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table. - * @param[in] *pBitRevTab points to the bit reversal table. - * @return none. - */ - - void arm_bitreversal_f32( - float32_t *pSrc, - uint16_t fftSize, - uint16_t bitRevFactor, - uint16_t *pBitRevTab); - - /** - * @brief Core function for the Q31 CFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_q31( - q31_t *pSrc, - uint32_t fftLen, - q31_t *pCoef, - uint32_t twidCoefModifier); - - /** - * @brief Core function for the Q31 CIFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_inverse_q31( - q31_t * pSrc, - uint32_t fftLen, - q31_t * pCoef, - uint32_t twidCoefModifier); - - /** - * @brief In-place bit reversal function. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table - * @param[in] *pBitRevTab points to bit reversal table. - * @return none. - */ - - void arm_bitreversal_q31( - q31_t * pSrc, - uint32_t fftLen, - uint16_t bitRevFactor, - uint16_t *pBitRevTab); - - /** - * @brief Core function for the Q15 CFFT butterfly process. - * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef16 points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_q15( - q15_t *pSrc16, - uint32_t fftLen, - q15_t *pCoef16, - uint32_t twidCoefModifier); - - /** - * @brief Core function for the Q15 CIFFT butterfly process. - * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef16 points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_inverse_q15( - q15_t *pSrc16, - uint32_t fftLen, - q15_t *pCoef16, - uint32_t twidCoefModifier); - - /** - * @brief In-place bit reversal function. - * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table - * @param[in] *pBitRevTab points to bit reversal table. - * @return none. - */ - - void arm_bitreversal_q15( - q15_t * pSrc, - uint32_t fftLen, - uint16_t bitRevFactor, - uint16_t *pBitRevTab); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - /** - * @brief Processing function for the Q15 RFFT/RIFFT. - * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure. - * @param[in] *pSrc points to the input buffer. - * @param[out] *pDst points to the output buffer. - * @return none. - */ - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Initialization function for the Q15 RFFT/RIFFT. - * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in] fftLenReal length of the FFT. - * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. - */ - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - /** - * @brief Processing function for the Q31 RFFT/RIFFT. - * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure. - * @param[in] *pSrc points to the input buffer. - * @param[out] *pDst points to the output buffer. - * @return none. - */ - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Initialization function for the Q31 RFFT/RIFFT. - * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure. - * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure. - * @param[in] fftLenReal length of the FFT. - * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. - */ - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - /** - * @brief Initialization function for the floating-point RFFT/RIFFT. - * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure. - * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in] fftLenReal length of the FFT. - * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. - */ - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - /** - * @brief Processing function for the floating-point RFFT/RIFFT. - * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure. - * @param[in] *pSrc points to the input buffer. - * @param[out] *pDst points to the output buffer. - * @return none. - */ - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q31 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q15 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - /** - * @brief Floating-point vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Dot product of floating-point vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - /** - * @brief Dot product of Q7 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - /** - * @brief Dot product of Q15 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Dot product of Q31 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - -/** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_f32; - - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t *pkCoeffs, - float32_t *pvCoeffs, - float32_t *pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t *pkCoeffs, - q31_t *pvCoeffs, - q31_t *pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the Q15 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - * @return none. - */ - - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t *pkCoeffs, - q15_t *pvCoeffs, - q15_t *pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - - } arm_lms_instance_q31; - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t *pCoeffs, - q31_t *pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Correlation of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - /** - * @brief Correlation of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t *pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /* - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cos output. - * @return none. - */ - - void arm_sin_cos_f32( - float32_t theta, - float32_t *pSinVal, - float32_t *pCcosVal); - - /* - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cosine output. - * @return none. - */ - - void arm_sin_cos_q31( - q31_t theta, - q31_t *pSinVal, - q31_t *pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - - - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - - /* Implementation of PID controller */ - - #ifdef ARM_MATH_CM0 - - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0 )* in ; - - #else - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD(S->A0, in); - - #endif - - #ifdef ARM_MATH_CM0 - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0] ; - acc += (q31_t) S->A2 * S->state[1] ; - - #else - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc); - - #endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - - /** - * @ingroup groupController - */ - - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - */ - - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - - } - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - */ - - - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; - - } - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * The function implements the forward Park transform. - * - */ - - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - - } - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - - - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - */ - - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (x - S->x1) / xSpacing; - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if(i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues-1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i +1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0)/(x1-x0)); - - } - - /* returns output value */ - return (y); - } - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] *pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData, - q31_t x, uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20); - - if(index >= (nValues - 1)) - { - return(pYData[nValues - 1]); - } - else if(index < 0) - { - return(pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - - } - - } - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] *pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - if(index >= (nValues - 1)) - { - return(pYData[nValues - 1]); - } - else if(index < 0) - { - return(pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (y >> 20); - } - - - } - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] *pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - - - static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - - if(index >= (nValues - 1)) - { - return(pYData[nValues - 1]); - } - else if(index < 0) - { - return(pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (y >> 20u); - - } - - } - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - - float32_t arm_sin_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q31_t arm_sin_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q15_t arm_sin_q15( - q15_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - - float32_t arm_cos_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q31_t arm_cos_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - - static __INLINE arm_status arm_sqrt_f32( - float32_t in, float32_t *pOut) - { - if(in > 0) - { - -// #if __FPU_USED - #if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); - #else - *pOut = sqrtf(in); - #endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, q31_t *pOut); - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, q15_t *pOut); - - /** - * @} end of SQRT group - */ - - - - - - - /** - * @brief floating-point Circular write function. - */ - - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - /** - * @brief Q15 Circular write function. - */ - - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - /** - * @brief Mean value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Mean value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Floating-point complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - /** - * @brief Q31 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - /** - * @brief Floating-point complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[in] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - * @return none. - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - - - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0 || yIndex > ( S->numCols-1)) - { - return(0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex-1) * S->numCols ; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex-1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - - } - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20u); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20u); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) - { - return(0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return (acc << 2u); - - } - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) - { - return(0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return (acc >> 36); - - } - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) - { - return(0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return (acc >> 40); - - } - - /** - * @} end of BilinearInterpolate group - */ - - - - - - -#ifdef __cplusplus -} -#endif - - -#endif /* _ARM_MATH_H */ - - -/** - * - * End of file. - */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cm0.h b/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cm0.h deleted file mode 100644 index 9d7a19f9ae1..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cm0.h +++ /dev/null @@ -1,665 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - - -/** \mainpage CMSIS Cortex-M0 - - This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. - It consists of: - - - Cortex-M Core Register Definitions - - Cortex-M functions - - Cortex-M instructions - - The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease - access to the Cortex-M Core - */ - -/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions - CMSIS violates following MISRA-C2004 Rules: - - - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \defgroup CMSIS_core_definitions CMSIS Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core - - Cortex-M core Revision Number - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - /* add preprocessor checks */ -#endif - -#include /*!< standard types definitions */ -#include "core_cmInstr.h" /*!< Core Instruction Access */ -#include "core_cmFunc.h" /*!< Core Function Access */ - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000 - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - -/*@} end of group CMSIS_core_definitions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** \defgroup CMSIS_core_register CMSIS Core Register - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE CMSIS Core - Type definitions for the Cortex-M Core Registers - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC CMSIS NVIC - Type definitions for the Cortex-M NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB CMSIS SCB - Type definitions for the Cortex-M System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick CMSIS SysTick - Type definitions for the Cortex-M System Timer Registers - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug CMSIS Core Debug - Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP - and not via processor. Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - This function enables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to enable - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - This function disables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to disable - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - This function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Number of the interrupt for get pending - \return 0 Interrupt status is not pending - \return 1 Interrupt status is pending - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - This function sets the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for set pending - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - This function clears the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for clear pending - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - This function sets the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - Note: The priority cannot be set for every core interrupt. - - \param [in] IRQn Number of the interrupt for set priority - \param [in] priority Priority to set - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - This function reads the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - The returned priority value is automatically aligned to the implemented - priority bits of the microcontroller. - - \param [in] IRQn Number of the interrupt for get priority - \return Interrupt Priority - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - This function initiate a system reset request to reset the MCU. - */ -static __INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - This function initialises the system tick timer and its interrupt and start the system tick timer. - Counter is in free running mode to generate periodical interrupts. - - \param [in] ticks Number of ticks between two interrupts - \return 0 Function succeeded - \return 1 Function failed - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cm3.h b/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cm3.h deleted file mode 100644 index e6b14fc2835..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cm3.h +++ /dev/null @@ -1,1240 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - - -/** \mainpage CMSIS Cortex-M3 - - This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. - It consists of: - - - Cortex-M Core Register Definitions - - Cortex-M functions - - Cortex-M instructions - - The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease - access to the Cortex-M Core - */ - -/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions - * @ingroup CMSIS_Core - CMSIS violates following MISRA-C2004 Rules: - - - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \defgroup CMSIS_core_definitions CMSIS Core Definitions - * @ingroup CMSIS_Core - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core - - Cortex-M core Revision Number - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - /* add preprocessor checks */ -#endif - -#include /*!< standard types definitions */ -#include "core_cmInstr.h" /*!< Core Instruction Access */ -#include "core_cmFunc.h" /*!< Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - -/*@} end of group CMSIS_core_definitions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** \defgroup CMSIS_core_register CMSIS Core Register - * @ingroup CMSIS_Core - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE CMSIS Core - Type definitions for the Cortex-M Core Registers - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC CMSIS NVIC - Type definitions for the Cortex-M NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB CMSIS SCB - Type definitions for the Cortex-M System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB - Type definitions for the Cortex-M System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick CMSIS SysTick - Type definitions for the Cortex-M System Timer Registers - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM CMSIS ITM - Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ -#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU CMSIS MPU - Type definitions for the Cortex-M Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug CMSIS Core Debug - Type definitions for the Cortex-M Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface - * @ingroup CMSIS_Core - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions - @{ - */ - -/** \brief Set Priority Grouping - - This function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - This function gets the priority grouping from NVIC Interrupt Controller. - Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - - \return Priority grouping field - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - This function enables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to enable - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - This function disables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to disable - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - This function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Number of the interrupt for get pending - \return 0 Interrupt status is not pending - \return 1 Interrupt status is pending - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - This function sets the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for set pending - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - This function clears the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for clear pending - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - This function reads the active register in NVIC and returns the active bit. - \param [in] IRQn Number of the interrupt for get active - \return 0 Interrupt status is not active - \return 1 Interrupt status is active - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - This function sets the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - Note: The priority cannot be set for every core interrupt. - - \param [in] IRQn Number of the interrupt for set priority - \param [in] priority Priority to set - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - This function reads the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - The returned priority value is automatically aligned to the implemented - priority bits of the microcontroller. - - \param [in] IRQn Number of the interrupt for get priority - \return Interrupt Priority - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - This function encodes the priority for an interrupt with the given priority group, - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The returned priority value can be used for NVIC_SetPriority(...) function - - \param [in] PriorityGroup Used priority group - \param [in] PreemptPriority Preemptive priority value (starting from 0) - \param [in] SubPriority Sub priority value (starting from 0) - \return Encoded priority for the interrupt - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - This function decodes an interrupt priority value with the given priority group to - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The priority value can be retrieved with NVIC_GetPriority(...) function - - \param [in] Priority Priority value - \param [in] PriorityGroup Used priority group - \param [out] pPreemptPriority Preemptive priority value (starting from 0) - \param [out] pSubPriority Sub priority value (starting from 0) - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - This function initiate a system reset request to reset the MCU. - */ -static __INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - This function initialises the system tick timer and its interrupt and start the system tick timer. - Counter is in free running mode to generate periodical interrupts. - - \param [in] ticks Number of ticks between two interrupts - \return 0 Function succeeded - \return 1 Function failed - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** \brief ITM Send Character - - This function transmits a character via the ITM channel 0. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \param [in] ch Character to transmit - \return Character to transmit - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - This function inputs a character via external variable ITM_RxBuffer. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \return Received character - \return -1 No character received - */ -static __INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - This function checks external variable ITM_RxBuffer whether a character is available or not. - It returns '1' if a character is available and '0' if no character is available. - - \return 0 No character available - \return 1 Character available - */ -static __INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cm4.h b/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cm4.h deleted file mode 100644 index bf022ba67fb..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,1378 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - - -/** \mainpage CMSIS Cortex-M4 - - This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. - It consists of: - - - Cortex-M Core Register Definitions - - Cortex-M functions - - Cortex-M instructions - - Cortex-M SIMD instructions - - The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease - access to the Cortex-M Core - */ - -/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions - CMSIS violates following MISRA-C2004 Rules: - - - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \defgroup CMSIS_core_definitions CMSIS Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core - - Cortex-M core Revision Number - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04) /*!< Cortex core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - /* add preprocessor checks to define __FPU_USED */ - #define __FPU_USED 0 -#endif - -#include /*!< standard types definitions */ -#include /*!< Core Instruction Access */ -#include /*!< Core Function Access */ -#include /*!< Compiler specific SIMD Intrinsics */ - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - -/*@} end of group CMSIS_core_definitions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** \defgroup CMSIS_core_register CMSIS Core Register - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE CMSIS Core - Type definitions for the Cortex-M Core Registers - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC CMSIS NVIC - Type definitions for the Cortex-M NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB CMSIS SCB - Type definitions for the Cortex-M System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB - Type definitions for the Cortex-M System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick CMSIS SysTick - Type definitions for the Cortex-M System Timer Registers - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM CMSIS ITM - Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ -#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU CMSIS MPU - Type definitions for the Cortex-M Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU CMSIS FPU - Type definitions for the Cortex-M Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug CMSIS Core Debug - Type definitions for the Cortex-M Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions - @{ - */ - -/** \brief Set Priority Grouping - - This function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - This function gets the priority grouping from NVIC Interrupt Controller. - Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - - \return Priority grouping field - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - This function enables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to enable - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - This function disables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to disable - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - This function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Number of the interrupt for get pending - \return 0 Interrupt status is not pending - \return 1 Interrupt status is pending - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - This function sets the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for set pending - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - This function clears the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for clear pending - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - This function reads the active register in NVIC and returns the active bit. - \param [in] IRQn Number of the interrupt for get active - \return 0 Interrupt status is not active - \return 1 Interrupt status is active - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - This function sets the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - Note: The priority cannot be set for every core interrupt. - - \param [in] IRQn Number of the interrupt for set priority - \param [in] priority Priority to set - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - This function reads the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - The returned priority value is automatically aligned to the implemented - priority bits of the microcontroller. - - \param [in] IRQn Number of the interrupt for get priority - \return Interrupt Priority - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - This function encodes the priority for an interrupt with the given priority group, - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The returned priority value can be used for NVIC_SetPriority(...) function - - \param [in] PriorityGroup Used priority group - \param [in] PreemptPriority Preemptive priority value (starting from 0) - \param [in] SubPriority Sub priority value (starting from 0) - \return Encoded priority for the interrupt - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - This function decodes an interrupt priority value with the given priority group to - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The priority value can be retrieved with NVIC_GetPriority(...) function - - \param [in] Priority Priority value - \param [in] PriorityGroup Used priority group - \param [out] pPreemptPriority Preemptive priority value (starting from 0) - \param [out] pSubPriority Sub priority value (starting from 0) - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - This function initiate a system reset request to reset the MCU. - */ -static __INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - This function initialises the system tick timer and its interrupt and start the system tick timer. - Counter is in free running mode to generate periodical interrupts. - - \param [in] ticks Number of ticks between two interrupts - \return 0 Function succeeded - \return 1 Function failed - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** \brief ITM Send Character - - This function transmits a character via the ITM channel 0. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \param [in] ch Character to transmit - \return Character to transmit - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - This function inputs a character via external variable ITM_RxBuffer. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \return Received character - \return -1 No character received - */ -static __INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - This function checks external variable ITM_RxBuffer whether a character is available or not. - It returns '1' if a character is available and '0' if no character is available. - - \return 0 No character available - \return 1 Character available - */ -static __INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cm4_simd.h b/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cm4_simd.h deleted file mode 100644 index e7b6765225e..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cm4_simd.h +++ /dev/null @@ -1,701 +0,0 @@ -/**************************************************************************//** - * @file core_cm4_simd.h - * @brief CMSIS Cortex-M4 SIMD Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2010-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_SIMD_H -#define __CORE_CM4_SIMD_H - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - -/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/ -/* intrinsic __SADD8 see intrinsics.h */ -/* intrinsic __QADD8 see intrinsics.h */ -/* intrinsic __SHADD8 see intrinsics.h */ -/* intrinsic __UADD8 see intrinsics.h */ -/* intrinsic __UQADD8 see intrinsics.h */ -/* intrinsic __UHADD8 see intrinsics.h */ -/* intrinsic __SSUB8 see intrinsics.h */ -/* intrinsic __QSUB8 see intrinsics.h */ -/* intrinsic __SHSUB8 see intrinsics.h */ -/* intrinsic __USUB8 see intrinsics.h */ -/* intrinsic __UQSUB8 see intrinsics.h */ -/* intrinsic __UHSUB8 see intrinsics.h */ -/* intrinsic __SADD16 see intrinsics.h */ -/* intrinsic __QADD16 see intrinsics.h */ -/* intrinsic __SHADD16 see intrinsics.h */ -/* intrinsic __UADD16 see intrinsics.h */ -/* intrinsic __UQADD16 see intrinsics.h */ -/* intrinsic __UHADD16 see intrinsics.h */ -/* intrinsic __SSUB16 see intrinsics.h */ -/* intrinsic __QSUB16 see intrinsics.h */ -/* intrinsic __SHSUB16 see intrinsics.h */ -/* intrinsic __USUB16 see intrinsics.h */ -/* intrinsic __UQSUB16 see intrinsics.h */ -/* intrinsic __UHSUB16 see intrinsics.h */ -/* intrinsic __SASX see intrinsics.h */ -/* intrinsic __QASX see intrinsics.h */ -/* intrinsic __SHASX see intrinsics.h */ -/* intrinsic __UASX see intrinsics.h */ -/* intrinsic __UQASX see intrinsics.h */ -/* intrinsic __UHASX see intrinsics.h */ -/* intrinsic __SSAX see intrinsics.h */ -/* intrinsic __QSAX see intrinsics.h */ -/* intrinsic __SHSAX see intrinsics.h */ -/* intrinsic __USAX see intrinsics.h */ -/* intrinsic __UQSAX see intrinsics.h */ -/* intrinsic __UHSAX see intrinsics.h */ -/* intrinsic __USAD8 see intrinsics.h */ -/* intrinsic __USADA8 see intrinsics.h */ -/* intrinsic __SSAT16 see intrinsics.h */ -/* intrinsic __USAT16 see intrinsics.h */ -/* intrinsic __UXTB16 see intrinsics.h */ -/* intrinsic __SXTB16 see intrinsics.h */ -/* intrinsic __UXTAB16 see intrinsics.h */ -/* intrinsic __SXTAB16 see intrinsics.h */ -/* intrinsic __SMUAD see intrinsics.h */ -/* intrinsic __SMUADX see intrinsics.h */ -/* intrinsic __SMLAD see intrinsics.h */ -/* intrinsic __SMLADX see intrinsics.h */ -/* intrinsic __SMLALD see intrinsics.h */ -/* intrinsic __SMLALDX see intrinsics.h */ -/* intrinsic __SMUSD see intrinsics.h */ -/* intrinsic __SMUSDX see intrinsics.h */ -/* intrinsic __SMLSD see intrinsics.h */ -/* intrinsic __SMLSDX see intrinsics.h */ -/* intrinsic __SMLSLD see intrinsics.h */ -/* intrinsic __SMLSLDX see intrinsics.h */ -/* intrinsic __SEL see intrinsics.h */ -/* intrinsic __QADD see intrinsics.h */ -/* intrinsic __QSUB see intrinsics.h */ -/* intrinsic __PKHBT see intrinsics.h */ -/* intrinsic __PKHTB see intrinsics.h */ - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLALD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLALDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLSLD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLSLDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -/* not yet supported */ -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CORE_CM4_SIMD_H */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cmFunc.h b/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cmFunc.h deleted file mode 100644 index 88819f9dd11..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cmFunc.h +++ /dev/null @@ -1,609 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V2.10 - * @date 26. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get ISPR Register - - This function returns the content of the ISPR Register. - - \return ISPR Register value - */ -static __INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -static __INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -static __INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -static __INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -static __INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -static __INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -static __INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** \brief Get ISPR Register - - This function returns the content of the ISPR Register. - - \return ISPR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cmInstr.h b/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cmInstr.h deleted file mode 100644 index 56d5ac75cd5..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cmInstr.h +++ /dev/null @@ -1,586 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - * @ingroup CMSIS_Core - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -static __INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -static __INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) static __INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) static __INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) static __INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) static __INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) static __INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) static __INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) -{ - uint32_t result; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint8_t result; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint16_t result; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) -{ - __ASM volatile ("clrex"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) -{ - uint8_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/LPC177x_8x.h b/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/LPC177x_8x.h deleted file mode 100644 index 5ebe1428d4c..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/LPC177x_8x.h +++ /dev/null @@ -1,1442 +0,0 @@ -/********************************************************************** -* $Id$ LPC177x_8x.h 2011-06-02 -*//** -* @file LPC177x_8x.h -* @brief Cortex-M3 Core Peripheral Access Layer Header File for -* NXP LPC177x_8x Series. -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -#ifndef __LPC177x_8x_H__ -#define __LPC177x_8x_H__ - -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ - -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** LPC177x_8x Specific Interrupt Numbers *******************************************************/ - WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ - TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ - TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ - TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ - TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ - UART0_IRQn = 5, /*!< UART0 Interrupt */ - UART1_IRQn = 6, /*!< UART1 Interrupt */ - UART2_IRQn = 7, /*!< UART2 Interrupt */ - UART3_IRQn = 8, /*!< UART3 Interrupt */ - PWM1_IRQn = 9, /*!< PWM1 Interrupt */ - I2C0_IRQn = 10, /*!< I2C0 Interrupt */ - I2C1_IRQn = 11, /*!< I2C1 Interrupt */ - I2C2_IRQn = 12, /*!< I2C2 Interrupt */ - Reserved0_IRQn = 13, /*!< Reserved */ - SSP0_IRQn = 14, /*!< SSP0 Interrupt */ - SSP1_IRQn = 15, /*!< SSP1 Interrupt */ - PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ - RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ - EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ - EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ - EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ - EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ - ADC_IRQn = 22, /*!< A/D Converter Interrupt */ - BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ - USB_IRQn = 24, /*!< USB Interrupt */ - CAN_IRQn = 25, /*!< CAN Interrupt */ - DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ - I2S_IRQn = 27, /*!< I2S Interrupt */ - ENET_IRQn = 28, /*!< Ethernet Interrupt */ - MCI_IRQn = 29, /*!< SD/MMC card I/F Interrupt */ - MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ - QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ - PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ - USBActivity_IRQn = 33, /*!< USB Activity interrupt */ - CANActivity_IRQn = 34, /*!< CAN Activity interrupt */ - UART4_IRQn = 35, /*!< UART4 Interrupt */ - SSP2_IRQn = 36, /*!< SSP2 Interrupt */ - LCD_IRQn = 37, /*!< LCD Interrupt */ - GPIO_IRQn = 38, /*!< GPIO Interrupt */ - PWM0_IRQn = 39, /*!< PWM0 Interrupt */ - EEPROM_IRQn = 40, /*!< EEPROM Interrupt */ -} IRQn_Type; - - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/* Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - - -#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ -//#include "system_LPC177x_8x.h" /* System Header */ - - -/******************************************************************************/ -/* Device Specific Peripheral registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/*------------- System Control (SC) ------------------------------------------*/ -typedef struct -{ - __IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */ - uint32_t RESERVED0[31]; - __IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */ - __IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */ - __I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */ - __O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */ - uint32_t RESERVED1[4]; - __IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */ - __IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */ - __I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */ - __O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */ - uint32_t RESERVED2[4]; - __IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */ - __IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */ - uint32_t RESERVED3[14]; - __IO uint32_t EMCCLKSEL; /*!< Offset: 0x100 (R/W) External Memory Controller Clock Selection Register */ - __IO uint32_t CCLKSEL; /*!< Offset: 0x104 (R/W) CPU Clock Selection Register */ - __IO uint32_t USBCLKSEL; /*!< Offset: 0x108 (R/W) USB Clock Selection Register */ - __IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */ - __IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */ - __IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */ - uint32_t RESERVED4[10]; - __IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */ - uint32_t RESERVED5[1]; - __IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */ - __IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */ - uint32_t RESERVED6[12]; - __IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */ - uint32_t RESERVED7[7]; - __IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */ - __IO uint32_t IRCTRIM; /*!< Offset: 0x1A4 (R/W) Clock Dividers */ - __IO uint32_t PCLKSEL; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Selection Register */ - uint32_t RESERVED8; - __IO uint32_t PBOOST; /*!< Offset: 0x1B0 (R/W) Power Boost control register */ - uint32_t RESERVED9; - __IO uint32_t LCD_CFG; /*!< Offset: 0x1B8 (R/W) LCD Configuration and clocking control Register */ - uint32_t RESERVED10[1]; - __IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */ - __IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */ - __IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */ - __IO uint32_t RSTCON0; /*!< Offset: 0x1CC (R/W) RESET Control0 Register */ - __IO uint32_t RSTCON1; /*!< Offset: 0x1D0 (R/W) RESET Control1 Register */ - uint32_t RESERVED11[2]; - __IO uint32_t EMCDLYCTL; /*!< Offset: 0x1DC (R/W) SDRAM programmable delays */ - __IO uint32_t EMCCAL; /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */ - } LPC_SC_TypeDef; - -/*------------- Pin Connect Block (PINCON) -----------------------------------*/ -typedef struct -{ - __IO uint32_t P0_0; /* 0x000 */ - __IO uint32_t P0_1; - __IO uint32_t P0_2; - __IO uint32_t P0_3; - __IO uint32_t P0_4; - __IO uint32_t P0_5; - __IO uint32_t P0_6; - __IO uint32_t P0_7; - - __IO uint32_t P0_8; /* 0x020 */ - __IO uint32_t P0_9; - __IO uint32_t P0_10; - __IO uint32_t P0_11; - __IO uint32_t P0_12; - __IO uint32_t P0_13; - __IO uint32_t P0_14; - __IO uint32_t P0_15; - - __IO uint32_t P0_16; /* 0x040 */ - __IO uint32_t P0_17; - __IO uint32_t P0_18; - __IO uint32_t P0_19; - __IO uint32_t P0_20; - __IO uint32_t P0_21; - __IO uint32_t P0_22; - __IO uint32_t P0_23; - - __IO uint32_t P0_24; /* 0x060 */ - __IO uint32_t P0_25; - __IO uint32_t P0_26; - __IO uint32_t P0_27; - __IO uint32_t P0_28; - __IO uint32_t P0_29; - __IO uint32_t P0_30; - __IO uint32_t P0_31; - - __IO uint32_t P1_0; /* 0x080 */ - __IO uint32_t P1_1; - __IO uint32_t P1_2; - __IO uint32_t P1_3; - __IO uint32_t P1_4; - __IO uint32_t P1_5; - __IO uint32_t P1_6; - __IO uint32_t P1_7; - - __IO uint32_t P1_8; /* 0x0A0 */ - __IO uint32_t P1_9; - __IO uint32_t P1_10; - __IO uint32_t P1_11; - __IO uint32_t P1_12; - __IO uint32_t P1_13; - __IO uint32_t P1_14; - __IO uint32_t P1_15; - - __IO uint32_t P1_16; /* 0x0C0 */ - __IO uint32_t P1_17; - __IO uint32_t P1_18; - __IO uint32_t P1_19; - __IO uint32_t P1_20; - __IO uint32_t P1_21; - __IO uint32_t P1_22; - __IO uint32_t P1_23; - - __IO uint32_t P1_24; /* 0x0E0 */ - __IO uint32_t P1_25; - __IO uint32_t P1_26; - __IO uint32_t P1_27; - __IO uint32_t P1_28; - __IO uint32_t P1_29; - __IO uint32_t P1_30; - __IO uint32_t P1_31; - - __IO uint32_t P2_0; /* 0x100 */ - __IO uint32_t P2_1; - __IO uint32_t P2_2; - __IO uint32_t P2_3; - __IO uint32_t P2_4; - __IO uint32_t P2_5; - __IO uint32_t P2_6; - __IO uint32_t P2_7; - - __IO uint32_t P2_8; /* 0x120 */ - __IO uint32_t P2_9; - __IO uint32_t P2_10; - __IO uint32_t P2_11; - __IO uint32_t P2_12; - __IO uint32_t P2_13; - __IO uint32_t P2_14; - __IO uint32_t P2_15; - - __IO uint32_t P2_16; /* 0x140 */ - __IO uint32_t P2_17; - __IO uint32_t P2_18; - __IO uint32_t P2_19; - __IO uint32_t P2_20; - __IO uint32_t P2_21; - __IO uint32_t P2_22; - __IO uint32_t P2_23; - - __IO uint32_t P2_24; /* 0x160 */ - __IO uint32_t P2_25; - __IO uint32_t P2_26; - __IO uint32_t P2_27; - __IO uint32_t P2_28; - __IO uint32_t P2_29; - __IO uint32_t P2_30; - __IO uint32_t P2_31; - - __IO uint32_t P3_0; /* 0x180 */ - __IO uint32_t P3_1; - __IO uint32_t P3_2; - __IO uint32_t P3_3; - __IO uint32_t P3_4; - __IO uint32_t P3_5; - __IO uint32_t P3_6; - __IO uint32_t P3_7; - - __IO uint32_t P3_8; /* 0x1A0 */ - __IO uint32_t P3_9; - __IO uint32_t P3_10; - __IO uint32_t P3_11; - __IO uint32_t P3_12; - __IO uint32_t P3_13; - __IO uint32_t P3_14; - __IO uint32_t P3_15; - - __IO uint32_t P3_16; /* 0x1C0 */ - __IO uint32_t P3_17; - __IO uint32_t P3_18; - __IO uint32_t P3_19; - __IO uint32_t P3_20; - __IO uint32_t P3_21; - __IO uint32_t P3_22; - __IO uint32_t P3_23; - - __IO uint32_t P3_24; /* 0x1E0 */ - __IO uint32_t P3_25; - __IO uint32_t P3_26; - __IO uint32_t P3_27; - __IO uint32_t P3_28; - __IO uint32_t P3_29; - __IO uint32_t P3_30; - __IO uint32_t P3_31; - - __IO uint32_t P4_0; /* 0x200 */ - __IO uint32_t P4_1; - __IO uint32_t P4_2; - __IO uint32_t P4_3; - __IO uint32_t P4_4; - __IO uint32_t P4_5; - __IO uint32_t P4_6; - __IO uint32_t P4_7; - - __IO uint32_t P4_8; /* 0x220 */ - __IO uint32_t P4_9; - __IO uint32_t P4_10; - __IO uint32_t P4_11; - __IO uint32_t P4_12; - __IO uint32_t P4_13; - __IO uint32_t P4_14; - __IO uint32_t P4_15; - - __IO uint32_t P4_16; /* 0x240 */ - __IO uint32_t P4_17; - __IO uint32_t P4_18; - __IO uint32_t P4_19; - __IO uint32_t P4_20; - __IO uint32_t P4_21; - __IO uint32_t P4_22; - __IO uint32_t P4_23; - - __IO uint32_t P4_24; /* 0x260 */ - __IO uint32_t P4_25; - __IO uint32_t P4_26; - __IO uint32_t P4_27; - __IO uint32_t P4_28; - __IO uint32_t P4_29; - __IO uint32_t P4_30; - __IO uint32_t P4_31; - - __IO uint32_t P5_0; /* 0x280 */ - __IO uint32_t P5_1; - __IO uint32_t P5_2; - __IO uint32_t P5_3; - __IO uint32_t P5_4; /* 0x290 */ -} LPC_IOCON_TypeDef; - -/*------------- General Purpose Input/Output (GPIO) --------------------------*/ -typedef struct -{ - __IO uint32_t DIR; - uint32_t RESERVED0[3]; - __IO uint32_t MASK; - __IO uint32_t PIN; - __IO uint32_t SET; - __O uint32_t CLR; -} LPC_GPIO_TypeDef; - -typedef struct -{ - __I uint32_t IntStatus; - __I uint32_t IO0IntStatR; - __I uint32_t IO0IntStatF; - __O uint32_t IO0IntClr; - __IO uint32_t IO0IntEnR; - __IO uint32_t IO0IntEnF; - uint32_t RESERVED0[3]; - __I uint32_t IO2IntStatR; - __I uint32_t IO2IntStatF; - __O uint32_t IO2IntClr; - __IO uint32_t IO2IntEnR; - __IO uint32_t IO2IntEnF; -} LPC_GPIOINT_TypeDef; - -/*------------- Timer (TIM) --------------------------------------------------*/ -typedef struct -{ - __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */ - __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */ - __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */ - __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */ - __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */ - __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */ - __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */ - __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */ - __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */ - __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */ - __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */ - __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */ - __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */ - uint32_t RESERVED0[2]; - __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */ - uint32_t RESERVED1[12]; - __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */ -} LPC_TIM_TypeDef; - -/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ -typedef struct -{ - __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */ - __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */ - __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */ - __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */ - __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */ - __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */ - __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */ - __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */ - __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */ - __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */ - __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */ - __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */ - __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */ - __I uint32_t CR2; /*!< Offset: 0x034 Capture Register 2 (R/ ) */ - __I uint32_t CR3; /*!< Offset: 0x038 Capture Register 3 (R/ ) */ - uint32_t RESERVED0; - __IO uint32_t MR4; /*!< Offset: 0x040 Match Register 4 (R/W) */ - __IO uint32_t MR5; /*!< Offset: 0x044 Match Register 5 (R/W) */ - __IO uint32_t MR6; /*!< Offset: 0x048 Match Register 6 (R/W) */ - __IO uint32_t PCR; /*!< Offset: 0x04C PWM Control Register (R/W) */ - __IO uint32_t LER; /*!< Offset: 0x050 Load Enable Register (R/W) */ - uint32_t RESERVED1[7]; - __IO uint32_t CTCR; /*!< Offset: 0x070 Counter Control Register (R/W) */ -} LPC_PWM_TypeDef; - -/*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/ -/* There are three types of UARTs on the chip: -(1) UART0,UART2, and UART3 are the standard UART. -(2) UART1 is the standard with modem capability. -(3) USART(UART4) is the sync/async UART with smart card capability. -More details can be found on the Users Manual. */ - -#if 0 -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[7]; - __I uint8_t LSR; - uint8_t RESERVED2[7]; - __IO uint8_t SCR; - uint8_t RESERVED3[3]; - __IO uint32_t ACR; - __IO uint8_t ICR; - uint8_t RESERVED4[3]; - __IO uint8_t FDR; - uint8_t RESERVED5[7]; - __IO uint8_t TER; - uint8_t RESERVED6[39]; - __I uint8_t FIFOLVL; -} LPC_UART_TypeDef; -#else -typedef struct -{ - union - { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union - { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union - { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[7];//Reserved - __I uint8_t LSR; - uint8_t RESERVED2[7];//Reserved - __IO uint8_t SCR; - uint8_t RESERVED3[3];//Reserved - __IO uint32_t ACR; - uint8_t RESERVED4[4];//Reserved - __IO uint8_t FDR; - uint8_t RESERVED5[7];//Reserved - __IO uint8_t TER; - uint8_t RESERVED8[27];//Reserved - __IO uint8_t RS485CTRL; - uint8_t RESERVED9[3];//Reserved - __IO uint8_t ADRMATCH; - uint8_t RESERVED10[3];//Reserved - __IO uint8_t RS485DLY; - uint8_t RESERVED11[3];//Reserved -}LPC_UART_TypeDef; -#endif - - -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[3]; - __IO uint8_t MCR; - uint8_t RESERVED2[3]; - __I uint8_t LSR; - uint8_t RESERVED3[3]; - __I uint8_t MSR; - uint8_t RESERVED4[3]; - __IO uint8_t SCR; - uint8_t RESERVED5[3]; - __IO uint32_t ACR; - uint32_t RESERVED6; - __IO uint32_t FDR; - uint32_t RESERVED7; - __IO uint8_t TER; - uint8_t RESERVED8[27]; - __IO uint8_t RS485CTRL; - uint8_t RESERVED9[3]; - __IO uint8_t ADRMATCH; - uint8_t RESERVED10[3]; - __IO uint8_t RS485DLY; - uint8_t RESERVED11[3]; -} LPC_UART1_TypeDef; - -typedef struct -{ - union { - __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */ - __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */ - __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */ - }; - union { - __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */ - __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */ - }; - union { - __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */ - __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */ - }; - __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */ - __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */ - __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */ - __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */ - __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */ - __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */ - __IO uint32_t ICR; /*!< Offset: 0x024 irDA Control Register (R/W) */ - __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */ - __IO uint32_t OSR; /*!< Offset: 0x02C Over sampling Register (R/W) */ - uint32_t RESERVED0[6]; - __IO uint32_t SCI_CTRL; /*!< Offset: 0x048 Smart card Interface Control Register (R/W) */ - __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */ - __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */ - __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */ - __IO uint32_t SYNCCTRL; /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */ - __IO uint32_t TER; /*!< Offset: 0x05C Transmit Enable Register (R/W) */ -} LPC_UART4_TypeDef; - -/*------------- Synchronous Serial Communication (SSP) -----------------------*/ -typedef struct -{ - __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */ - __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */ - __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */ - __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */ - __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */ - __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */ - __IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */ - __IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */ - __IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */ - __IO uint32_t DMACR; -} LPC_SSP_TypeDef; - -/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ -typedef struct -{ - __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */ - __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */ - __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */ - __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */ - __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */ - __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */ - __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */ - __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */ - __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */ - __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */ - __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */ - __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */ - __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */ - __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */ - __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */ - __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */ -} LPC_I2C_TypeDef; - -/*------------- Inter IC Sound (I2S) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t DAO; - __IO uint32_t DAI; - __O uint32_t TXFIFO; - __I uint32_t RXFIFO; - __I uint32_t STATE; - __IO uint32_t DMA1; - __IO uint32_t DMA2; - __IO uint32_t IRQ; - __IO uint32_t TXRATE; - __IO uint32_t RXRATE; - __IO uint32_t TXBITRATE; - __IO uint32_t RXBITRATE; - __IO uint32_t TXMODE; - __IO uint32_t RXMODE; -} LPC_I2S_TypeDef; - -/*------------- Real-Time Clock (RTC) ----------------------------------------*/ -typedef struct -{ - __IO uint8_t ILR; - uint8_t RESERVED0[7]; - __IO uint8_t CCR; - uint8_t RESERVED1[3]; - __IO uint8_t CIIR; - uint8_t RESERVED2[3]; - __IO uint8_t AMR; - uint8_t RESERVED3[3]; - __I uint32_t CTIME0; - __I uint32_t CTIME1; - __I uint32_t CTIME2; - __IO uint8_t SEC; - uint8_t RESERVED4[3]; - __IO uint8_t MIN; - uint8_t RESERVED5[3]; - __IO uint8_t HOUR; - uint8_t RESERVED6[3]; - __IO uint8_t DOM; - uint8_t RESERVED7[3]; - __IO uint8_t DOW; - uint8_t RESERVED8[3]; - __IO uint16_t DOY; - uint16_t RESERVED9; - __IO uint8_t MONTH; - uint8_t RESERVED10[3]; - __IO uint16_t YEAR; - uint16_t RESERVED11; - __IO uint32_t CALIBRATION; - __IO uint32_t GPREG0; - __IO uint32_t GPREG1; - __IO uint32_t GPREG2; - __IO uint32_t GPREG3; - __IO uint32_t GPREG4; - __IO uint8_t RTC_AUXEN; - uint8_t RESERVED12[3]; - __IO uint8_t RTC_AUX; - uint8_t RESERVED13[3]; - __IO uint8_t ALSEC; - uint8_t RESERVED14[3]; - __IO uint8_t ALMIN; - uint8_t RESERVED15[3]; - __IO uint8_t ALHOUR; - uint8_t RESERVED16[3]; - __IO uint8_t ALDOM; - uint8_t RESERVED17[3]; - __IO uint8_t ALDOW; - uint8_t RESERVED18[3]; - __IO uint16_t ALDOY; - uint16_t RESERVED19; - __IO uint8_t ALMON; - uint8_t RESERVED20[3]; - __IO uint16_t ALYEAR; - uint16_t RESERVED21; - __IO uint32_t ERSTATUS; - __IO uint32_t ERCONTROL; - __IO uint32_t ERCOUNTERS; - uint32_t RESERVED22; - __IO uint32_t ERFIRSTSTAMP0; - __IO uint32_t ERFIRSTSTAMP1; - __IO uint32_t ERFIRSTSTAMP2; - uint32_t RESERVED23; - __IO uint32_t ERLASTSTAMP0; - __IO uint32_t ERLASTSTAMP1; - __IO uint32_t ERLASTSTAMP2; -} LPC_RTC_TypeDef; - -/*------------- Watchdog Timer (WDT) -----------------------------------------*/ -typedef struct -{ - __IO uint8_t MOD; - uint8_t RESERVED0[3]; - __IO uint32_t TC; - __O uint8_t FEED; - uint8_t RESERVED1[3]; - __I uint32_t TV; - uint32_t RESERVED2; - __IO uint32_t WARNINT; - __IO uint32_t WINDOW; -} LPC_WDT_TypeDef; - -/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ -typedef struct -{ - __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */ - __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */ - uint32_t RESERVED0; - __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */ - __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */ - __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */ - __IO uint32_t ADTRM; -} LPC_ADC_TypeDef; - -/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CTRL; - __IO uint32_t CNTVAL; -} LPC_DAC_TypeDef; - -/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ -typedef struct -{ - __I uint32_t CON; - __O uint32_t CON_SET; - __O uint32_t CON_CLR; - __I uint32_t CAPCON; - __O uint32_t CAPCON_SET; - __O uint32_t CAPCON_CLR; - __IO uint32_t TC0; - __IO uint32_t TC1; - __IO uint32_t TC2; - __IO uint32_t LIM0; - __IO uint32_t LIM1; - __IO uint32_t LIM2; - __IO uint32_t MAT0; - __IO uint32_t MAT1; - __IO uint32_t MAT2; - __IO uint32_t DT; - __IO uint32_t CP; - __IO uint32_t CAP0; - __IO uint32_t CAP1; - __IO uint32_t CAP2; - __I uint32_t INTEN; - __O uint32_t INTEN_SET; - __O uint32_t INTEN_CLR; - __I uint32_t CNTCON; - __O uint32_t CNTCON_SET; - __O uint32_t CNTCON_CLR; - __I uint32_t INTF; - __O uint32_t INTF_SET; - __O uint32_t INTF_CLR; - __O uint32_t CAP_CLR; -} LPC_MCPWM_TypeDef; - -/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ -typedef struct -{ - __O uint32_t CON; - __I uint32_t STAT; - __IO uint32_t CONF; - __I uint32_t POS; - __IO uint32_t MAXPOS; - __IO uint32_t CMPOS0; - __IO uint32_t CMPOS1; - __IO uint32_t CMPOS2; - __I uint32_t INXCNT; - __IO uint32_t INXCMP0; - __IO uint32_t LOAD; - __I uint32_t TIME; - __I uint32_t VEL; - __I uint32_t CAP; - __IO uint32_t VELCOMP; - __IO uint32_t FILTERPHA; - __IO uint32_t FILTERPHB; - __IO uint32_t FILTERINX; - __IO uint32_t WINDOW; - __IO uint32_t INXCMP1; - __IO uint32_t INXCMP2; - uint32_t RESERVED0[993]; - __O uint32_t IEC; - __O uint32_t IES; - __I uint32_t INTSTAT; - __I uint32_t IE; - __O uint32_t CLR; - __O uint32_t SET; -} LPC_QEI_TypeDef; - -/*------------- SD/MMC card Interface (MCI)-----------------------------------*/ -typedef struct -{ - __IO uint32_t POWER; - __IO uint32_t CLOCK; - __IO uint32_t ARGUMENT; - __IO uint32_t COMMAND; - __I uint32_t RESP_CMD; - __I uint32_t RESP0; - __I uint32_t RESP1; - __I uint32_t RESP2; - __I uint32_t RESP3; - __IO uint32_t DATATMR; - __IO uint32_t DATALEN; - __IO uint32_t DATACTRL; - __I uint32_t DATACNT; - __I uint32_t STATUS; - __O uint32_t CLEAR; - __IO uint32_t MASK0; - uint32_t RESERVED0[2]; - __I uint32_t FIFOCNT; - uint32_t RESERVED1[13]; - __IO uint32_t FIFO[16]; -} LPC_MCI_TypeDef; - -/*------------- Controller Area Network (CAN) --------------------------------*/ -typedef struct -{ - __IO uint32_t mask[512]; /* ID Masks */ -} LPC_CANAF_RAM_TypeDef; - -typedef struct /* Acceptance Filter Registers */ -{ - ///Offset: 0x00000000 - Acceptance Filter Register - __IO uint32_t AFMR; - - ///Offset: 0x00000004 - Standard Frame Individual Start Address Register - __IO uint32_t SFF_sa; - - ///Offset: 0x00000008 - Standard Frame Group Start Address Register - __IO uint32_t SFF_GRP_sa; - - ///Offset: 0x0000000C - Extended Frame Start Address Register - __IO uint32_t EFF_sa; - - ///Offset: 0x00000010 - Extended Frame Group Start Address Register - __IO uint32_t EFF_GRP_sa; - - ///Offset: 0x00000014 - End of AF Tables register - __IO uint32_t ENDofTable; - - ///Offset: 0x00000018 - LUT Error Address register - __I uint32_t LUTerrAd; - - ///Offset: 0x0000001C - LUT Error Register - __I uint32_t LUTerr; - - ///Offset: 0x00000020 - CAN Central Transmit Status Register - __IO uint32_t FCANIE; - - ///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0 - __IO uint32_t FCANIC0; - - ///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1 - __IO uint32_t FCANIC1; -} LPC_CANAF_TypeDef; - -typedef struct /* Central Registers */ -{ - __I uint32_t TxSR; - __I uint32_t RxSR; - __I uint32_t MSR; -} LPC_CANCR_TypeDef; - -typedef struct /* Controller Registers */ -{ - ///Offset: 0x00000000 - Controls the operating mode of the CAN Controller - __IO uint32_t MOD; - - ///Offset: 0x00000004 - Command bits that affect the state - __O uint32_t CMR; - - ///Offset: 0x00000008 - Global Controller Status and Error Counters - __IO uint32_t GSR; - - ///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture - __I uint32_t ICR; - - ///Offset: 0x00000010 - Interrupt Enable Register - __IO uint32_t IER; - - ///Offset: 0x00000014 - Bus Timing Register - __IO uint32_t BTR; - - ///Offset: 0x00000018 - Error Warning Limit - __IO uint32_t EWL; - - ///Offset: 0x0000001C - Status Register - __I uint32_t SR; - - ///Offset: 0x00000020 - Receive frame status - __IO uint32_t RFS; - - ///Offset: 0x00000024 - Received Identifier - __IO uint32_t RID; - - ///Offset: 0x00000028 - Received data bytes 1-4 - __IO uint32_t RDA; - - ///Offset: 0x0000002C - Received data bytes 5-8 - __IO uint32_t RDB; - - ///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1) - __IO uint32_t TFI1; - - ///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1) - __IO uint32_t TID1; - - ///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1) - __IO uint32_t TDA1; - - ///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1) - __IO uint32_t TDB1; - - ///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2) - __IO uint32_t TFI2; - - ///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2) - __IO uint32_t TID2; - - ///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2) - __IO uint32_t TDA2; - - ///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2) - __IO uint32_t TDB2; - - ///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3) - __IO uint32_t TFI3; - - ///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3) - __IO uint32_t TID3; - - ///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3) - __IO uint32_t TDA3; - - ///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3) - __IO uint32_t TDB3; -} LPC_CAN_TypeDef; - -/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ -typedef struct /* Common Registers */ -{ - __I uint32_t IntStat; - __I uint32_t IntTCStat; - __O uint32_t IntTCClear; - __I uint32_t IntErrStat; - __O uint32_t IntErrClr; - __I uint32_t RawIntTCStat; - __I uint32_t RawIntErrStat; - __I uint32_t EnbldChns; - __IO uint32_t SoftBReq; - __IO uint32_t SoftSReq; - __IO uint32_t SoftLBReq; - __IO uint32_t SoftLSReq; - __IO uint32_t Config; - __IO uint32_t Sync; -} LPC_GPDMA_TypeDef; - -typedef struct /* Channel Registers */ -{ - __IO uint32_t CSrcAddr; - __IO uint32_t CDestAddr; - __IO uint32_t CLLI; - __IO uint32_t CControl; - __IO uint32_t CConfig; -} LPC_GPDMACH_TypeDef; - -/*------------- Universal Serial Bus (USB) -----------------------------------*/ -typedef struct -{ - __I uint32_t Revision; /* USB Host Registers */ - __IO uint32_t Control; - __IO uint32_t CommandStatus; - __IO uint32_t InterruptStatus; - __IO uint32_t InterruptEnable; - __IO uint32_t InterruptDisable; - __IO uint32_t HCCA; - __I uint32_t PeriodCurrentED; - __IO uint32_t ControlHeadED; - __IO uint32_t ControlCurrentED; - __IO uint32_t BulkHeadED; - __IO uint32_t BulkCurrentED; - __I uint32_t DoneHead; - __IO uint32_t FmInterval; - __I uint32_t FmRemaining; - __I uint32_t FmNumber; - __IO uint32_t PeriodicStart; - __IO uint32_t LSTreshold; - __IO uint32_t RhDescriptorA; - __IO uint32_t RhDescriptorB; - __IO uint32_t RhStatus; - __IO uint32_t RhPortStatus1; - __IO uint32_t RhPortStatus2; - uint32_t RESERVED0[40]; - __I uint32_t Module_ID; - - __I uint32_t IntSt; /* USB On-The-Go Registers */ - __IO uint32_t IntEn; - __O uint32_t IntSet; - __O uint32_t IntClr; - __IO uint32_t StCtrl; - __IO uint32_t Tmr; - uint32_t RESERVED1[58]; - - __I uint32_t DevIntSt; /* USB Device Interrupt Registers */ - __IO uint32_t DevIntEn; - __O uint32_t DevIntClr; - __O uint32_t DevIntSet; - - __O uint32_t CmdCode; /* USB Device SIE Command Registers */ - __I uint32_t CmdData; - - __I uint32_t RxData; /* USB Device Transfer Registers */ - __O uint32_t TxData; - __I uint32_t RxPLen; - __O uint32_t TxPLen; - __IO uint32_t Ctrl; - __O uint32_t DevIntPri; - - __I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */ - __IO uint32_t EpIntEn; - __O uint32_t EpIntClr; - __O uint32_t EpIntSet; - __O uint32_t EpIntPri; - - __IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/ - __O uint32_t EpInd; - __IO uint32_t MaxPSize; - - __I uint32_t DMARSt; /* USB Device DMA Registers */ - __O uint32_t DMARClr; - __O uint32_t DMARSet; - uint32_t RESERVED2[9]; - __IO uint32_t UDCAH; - __I uint32_t EpDMASt; - __O uint32_t EpDMAEn; - __O uint32_t EpDMADis; - __I uint32_t DMAIntSt; - __IO uint32_t DMAIntEn; - uint32_t RESERVED3[2]; - __I uint32_t EoTIntSt; - __O uint32_t EoTIntClr; - __O uint32_t EoTIntSet; - __I uint32_t NDDRIntSt; - __O uint32_t NDDRIntClr; - __O uint32_t NDDRIntSet; - __I uint32_t SysErrIntSt; - __O uint32_t SysErrIntClr; - __O uint32_t SysErrIntSet; - uint32_t RESERVED4[15]; - - union { - __I uint32_t I2C_RX; /* USB OTG I2C Registers */ - __O uint32_t I2C_TX; - }; - __IO uint32_t I2C_STS; - __IO uint32_t I2C_CTL; - __IO uint32_t I2C_CLKHI; - __O uint32_t I2C_CLKLO; - uint32_t RESERVED5[824]; - - union { - __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ - __IO uint32_t OTGClkCtrl; - }; - union { - __I uint32_t USBClkSt; - __I uint32_t OTGClkSt; - }; -} LPC_USB_TypeDef; - -/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ -typedef struct -{ - __IO uint32_t MAC1; /* MAC Registers */ - __IO uint32_t MAC2; - __IO uint32_t IPGT; - __IO uint32_t IPGR; - __IO uint32_t CLRT; - __IO uint32_t MAXF; - __IO uint32_t SUPP; - __IO uint32_t TEST; - __IO uint32_t MCFG; - __IO uint32_t MCMD; - __IO uint32_t MADR; - __O uint32_t MWTD; - __I uint32_t MRDD; - __I uint32_t MIND; - uint32_t RESERVED0[2]; - __IO uint32_t SA0; - __IO uint32_t SA1; - __IO uint32_t SA2; - uint32_t RESERVED1[45]; - __IO uint32_t Command; /* Control Registers */ - __I uint32_t Status; - __IO uint32_t RxDescriptor; - __IO uint32_t RxStatus; - __IO uint32_t RxDescriptorNumber; - __I uint32_t RxProduceIndex; - __IO uint32_t RxConsumeIndex; - __IO uint32_t TxDescriptor; - __IO uint32_t TxStatus; - __IO uint32_t TxDescriptorNumber; - __IO uint32_t TxProduceIndex; - __I uint32_t TxConsumeIndex; - uint32_t RESERVED2[10]; - __I uint32_t TSV0; - __I uint32_t TSV1; - __I uint32_t RSV; - uint32_t RESERVED3[3]; - __IO uint32_t FlowControlCounter; - __I uint32_t FlowControlStatus; - uint32_t RESERVED4[34]; - __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ - __I uint32_t RxFilterWoLStatus; - __O uint32_t RxFilterWoLClear; - uint32_t RESERVED5; - __IO uint32_t HashFilterL; - __IO uint32_t HashFilterH; - uint32_t RESERVED6[882]; - __I uint32_t IntStatus; /* Module Control Registers */ - __IO uint32_t IntEnable; - __O uint32_t IntClear; - __O uint32_t IntSet; - uint32_t RESERVED7; - __IO uint32_t PowerDown; - uint32_t RESERVED8; - __IO uint32_t Module_ID; -} LPC_EMAC_TypeDef; - -/*------------- LCD controller (LCD) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t TIMH; /* LCD Registers */ - __IO uint32_t TIMV; - __IO uint32_t POL; - __IO uint32_t LE; - __IO uint32_t UPBASE; - __IO uint32_t LPBASE; - __IO uint32_t CTRL; - __IO uint32_t INTMSK; - __I uint32_t INTRAW; - __I uint32_t INTSTAT; - __O uint32_t INTCLR; - __I uint32_t UPCURR; - __I uint32_t LPCURR; - uint32_t RESERVED0[115]; - __IO uint32_t PAL[128]; - uint32_t RESERVED1[256]; - __IO uint32_t CRSR_IMG[256]; - __IO uint32_t CRSR_CTRL; - __IO uint32_t CRSR_CFG; - __IO uint32_t CRSR_PAL0; - __IO uint32_t CRSR_PAL1; - __IO uint32_t CRSR_XY; - __IO uint32_t CRSR_CLIP; - uint32_t RESERVED2[2]; - __IO uint32_t CRSR_INTMSK; - __O uint32_t CRSR_INTCLR; - __I uint32_t CRSR_INTRAW; - __I uint32_t CRSR_INTSTAT; -} LPC_LCD_TypeDef; - -/*------------- External Memory Controller (EMC) -----------------------------*/ -typedef struct -{ - __IO uint32_t Control; - __I uint32_t Status; - __IO uint32_t Config; - uint32_t RESERVED0[5]; - __IO uint32_t DynamicControl; - __IO uint32_t DynamicRefresh; - __IO uint32_t DynamicReadConfig; - uint32_t RESERVED1[1]; - __IO uint32_t DynamicRP; - __IO uint32_t DynamicRAS; - __IO uint32_t DynamicSREX; - __IO uint32_t DynamicAPR; - __IO uint32_t DynamicDAL; - __IO uint32_t DynamicWR; - __IO uint32_t DynamicRC; - __IO uint32_t DynamicRFC; - __IO uint32_t DynamicXSR; - __IO uint32_t DynamicRRD; - __IO uint32_t DynamicMRD; - uint32_t RESERVED2[9]; - __IO uint32_t StaticExtendedWait; - uint32_t RESERVED3[31]; - __IO uint32_t DynamicConfig0; - __IO uint32_t DynamicRasCas0; - uint32_t RESERVED4[6]; - __IO uint32_t DynamicConfig1; - __IO uint32_t DynamicRasCas1; - uint32_t RESERVED5[6]; - __IO uint32_t DynamicConfig2; - __IO uint32_t DynamicRasCas2; - uint32_t RESERVED6[6]; - __IO uint32_t DynamicConfig3; - __IO uint32_t DynamicRasCas3; - uint32_t RESERVED7[38]; - __IO uint32_t StaticConfig0; - __IO uint32_t StaticWaitWen0; - __IO uint32_t StaticWaitOen0; - __IO uint32_t StaticWaitRd0; - __IO uint32_t StaticWaitPage0; - __IO uint32_t StaticWaitWr0; - __IO uint32_t StaticWaitTurn0; - uint32_t RESERVED8[1]; - __IO uint32_t StaticConfig1; - __IO uint32_t StaticWaitWen1; - __IO uint32_t StaticWaitOen1; - __IO uint32_t StaticWaitRd1; - __IO uint32_t StaticWaitPage1; - __IO uint32_t StaticWaitWr1; - __IO uint32_t StaticWaitTurn1; - uint32_t RESERVED9[1]; - __IO uint32_t StaticConfig2; - __IO uint32_t StaticWaitWen2; - __IO uint32_t StaticWaitOen2; - __IO uint32_t StaticWaitRd2; - __IO uint32_t StaticWaitPage2; - __IO uint32_t StaticWaitWr2; - __IO uint32_t StaticWaitTurn2; - uint32_t RESERVED10[1]; - __IO uint32_t StaticConfig3; - __IO uint32_t StaticWaitWen3; - __IO uint32_t StaticWaitOen3; - __IO uint32_t StaticWaitRd3; - __IO uint32_t StaticWaitPage3; - __IO uint32_t StaticWaitWr3; - __IO uint32_t StaticWaitTurn3; -} LPC_EMC_TypeDef; - -/*------------- CRC Engine (CRC) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t MODE; - __IO uint32_t SEED; - union { - __I uint32_t SUM; - struct { - __O uint32_t DATA; - } WR_DATA_DWORD; - - struct { - __O uint16_t DATA; - uint16_t RESERVED; - }WR_DATA_WORD; - - struct { - __O uint8_t DATA; - uint8_t RESERVED[3]; - }WR_DATA_BYTE; - }; -} LPC_CRC_TypeDef; - -/*------------- EEPROM Controller (EEPROM) -----------------------------------*/ -typedef struct -{ - __IO uint32_t CMD; /* 0x0080 */ - __IO uint32_t ADDR; - __IO uint32_t WDATA; - __IO uint32_t RDATA; - __IO uint32_t WSTATE; /* 0x0090 */ - __IO uint32_t CLKDIV; - __IO uint32_t PWRDWN; /* 0x0098 */ - uint32_t RESERVED0[975]; - __IO uint32_t INT_CLR_ENABLE; /* 0x0FD8 */ - __IO uint32_t INT_SET_ENABLE; - __IO uint32_t INT_STATUS; /* 0x0FE0 */ - __IO uint32_t INT_ENABLE; - __IO uint32_t INT_CLR_STATUS; - __IO uint32_t INT_SET_STATUS; -} LPC_EEPROM_TypeDef; - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* Base addresses */ -#define LPC_FLASH_BASE (0x00000000UL) -#define LPC_RAM_BASE (0x10000000UL) -#define LPC_PERI_RAM_BASE (0x20000000UL) -#define LPC_APB0_BASE (0x40000000UL) -#define LPC_APB1_BASE (0x40080000UL) -#define LPC_AHBRAM1_BASE (0x20004000UL) -#define LPC_AHB_BASE (0x20080000UL) -#define LPC_CM3_BASE (0xE0000000UL) - -/* APB0 peripherals */ -#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) -#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) -#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) -#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) -#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) -#define LPC_PWM0_BASE (LPC_APB0_BASE + 0x14000) -#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) -#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) -#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) -#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) -#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x2C000) -#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) -#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) -#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) -#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) -#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) -#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) -#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) -#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) - -/* APB1 peripherals */ -#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) -#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) -#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) -#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) -#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) -#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) -#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) -#define LPC_UART4_BASE (LPC_APB1_BASE + 0x24000) -#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) -#define LPC_SSP2_BASE (LPC_APB1_BASE + 0x2C000) -#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) -#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) -#define LPC_MCI_BASE (LPC_APB1_BASE + 0x40000) -#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) - -/* AHB peripherals */ -#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x00100) -#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x00120) -#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x00140) -#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x00160) -#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x00180) -#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x001A0) -#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x001C0) -#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x001E0) -#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x04000) -#define LPC_LCD_BASE (LPC_AHB_BASE + 0x08000) -#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) -#define LPC_CRC_BASE (LPC_AHB_BASE + 0x10000) -#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x18000) -#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x18020) -#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x18040) -#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x18060) -#define LPC_GPIO4_BASE (LPC_AHB_BASE + 0x18080) -#define LPC_GPIO5_BASE (LPC_AHB_BASE + 0x180A0) -#define LPC_EMC_BASE (LPC_AHB_BASE + 0x1C000) - -#define LPC_EEPROM_BASE (LPC_FLASH_BASE+ 0x200080) - - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) -#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) -#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) -#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) -#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) -#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) -#define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE ) -#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) -#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) -#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) -#define LPC_UART4 ((LPC_UART4_TypeDef *) LPC_UART4_BASE ) -#define LPC_PWM0 ((LPC_PWM_TypeDef *) LPC_PWM0_BASE ) -#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) -#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) -#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) -#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) -#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) -#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) -#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) -#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) -#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) -#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) -#define LPC_SSP2 ((LPC_SSP_TypeDef *) LPC_SSP2_BASE ) -#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) -#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) -#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) -#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) -#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) -#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) -#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) -#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) -#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) -#define LPC_MCI ((LPC_MCI_TypeDef *) LPC_MCI_BASE ) -#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) -#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) -#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) -#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) -#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) -#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) -#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) -#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) -#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) -#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) -#define LPC_LCD ((LPC_LCD_TypeDef *) LPC_LCD_BASE ) -#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) -#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) -#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) -#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) -#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) -#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) -#define LPC_GPIO5 ((LPC_GPIO_TypeDef *) LPC_GPIO5_BASE ) -#define LPC_EMC ((LPC_EMC_TypeDef *) LPC_EMC_BASE ) -#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE ) -#define LPC_EEPROM ((LPC_EEPROM_TypeDef *) LPC_EEPROM_BASE ) - -#endif // __LPC177x_8x_H__ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/LPC407x_8x_177x_8x.h b/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/LPC407x_8x_177x_8x.h deleted file mode 100644 index 9942f382e5b..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/LPC407x_8x_177x_8x.h +++ /dev/null @@ -1,1514 +0,0 @@ -/****************************************************************************************************//** -* $Id$ LPC407x_8x_177x_8x.h 2012-04-25 -*//** - * @file LPC407x_8x_177x_8x.h - * - * @brief CMSIS Cortex-M4 Cortex-M3 Peripheral Access Layer Header File for - * NXP LPC407x_8x_177x_8x. - * @version V0.7 - * @date 20. June 2012 - * @author NXP MCU SW Application Team -* -* Copyright(C) 2012, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -#ifndef __LPC407x_8x_177x_8x_H__ -#define __LPC407x_8x_177x_8x_H__ - - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** LPC407x_8x_177x_8x Specific Interrupt Numbers *******************************************************/ - WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ - TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ - TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ - TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ - TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ - UART0_IRQn = 5, /*!< UART0 Interrupt */ - UART1_IRQn = 6, /*!< UART1 Interrupt */ - UART2_IRQn = 7, /*!< UART2 Interrupt */ - UART3_IRQn = 8, /*!< UART3 Interrupt */ - PWM1_IRQn = 9, /*!< PWM1 Interrupt */ - I2C0_IRQn = 10, /*!< I2C0 Interrupt */ - I2C1_IRQn = 11, /*!< I2C1 Interrupt */ - I2C2_IRQn = 12, /*!< I2C2 Interrupt */ - Reserved0_IRQn = 13, /*!< Reserved */ - SSP0_IRQn = 14, /*!< SSP0 Interrupt */ - SSP1_IRQn = 15, /*!< SSP1 Interrupt */ - PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ - RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ - EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ - EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ - EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ - EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ - ADC_IRQn = 22, /*!< A/D Converter Interrupt */ - BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ - USB_IRQn = 24, /*!< USB Interrupt */ - CAN_IRQn = 25, /*!< CAN Interrupt */ - DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ - I2S_IRQn = 27, /*!< I2S Interrupt */ - ENET_IRQn = 28, /*!< Ethernet Interrupt */ - MCI_IRQn = 29, /*!< SD/MMC card I/F Interrupt */ - MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ - QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ - PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ - USBActivity_IRQn = 33, /*!< USB Activity interrupt */ - CANActivity_IRQn = 34, /*!< CAN Activity interrupt */ - UART4_IRQn = 35, /*!< UART4 Interrupt */ - SSP2_IRQn = 36, /*!< SSP2 Interrupt */ - LCD_IRQn = 37, /*!< LCD Interrupt */ - GPIO_IRQn = 38, /*!< GPIO Interrupt */ - PWM0_IRQn = 39, /*!< 39 PWM0 */ - EEPROM_IRQn = 40, /*!< 40 EEPROM */ - CMP0_IRQn = 41, /*!< 41 CMP0 */ - CMP1_IRQn = 42 /*!< 42 CMP1 */ -} IRQn_Type; - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ -#ifdef CORE_M4 -/* ----------------Configuration of the cm4 Processor and Core Peripherals---------------- */ -#define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ - - -#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ -#else -/* Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - - -#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ - -#endif - -#include "system_LPC407x_8x_177x_8x.h" /*!< LPC408x_7x System */ - - - - -/* ================================================================================ */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================ */ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#elif defined ( __ICCARM__ ) -#pragma language=save -#pragma language=extended -#endif - -/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ -typedef struct /* Common Registers */ -{ - __I uint32_t IntStat; - __I uint32_t IntTCStat; - __O uint32_t IntTCClear; - __I uint32_t IntErrStat; - __O uint32_t IntErrClr; - __I uint32_t RawIntTCStat; - __I uint32_t RawIntErrStat; - __I uint32_t EnbldChns; - __IO uint32_t SoftBReq; - __IO uint32_t SoftSReq; - __IO uint32_t SoftLBReq; - __IO uint32_t SoftLSReq; - __IO uint32_t Config; - __IO uint32_t Sync; -} LPC_GPDMA_TypeDef; - -typedef struct /* Channel Registers */ -{ - __IO uint32_t CSrcAddr; - __IO uint32_t CDestAddr; - __IO uint32_t CLLI; - __IO uint32_t CControl; - __IO uint32_t CConfig; -} LPC_GPDMACH_TypeDef; - -/*------------- System Control (SC) ------------------------------------------*/ -typedef struct -{ - __IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */ - uint32_t RESERVED0[31]; - __IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */ - __IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */ - __I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */ - __O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */ - uint32_t RESERVED1[4]; - __IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */ - __IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */ - __I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */ - __O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */ - uint32_t RESERVED2[4]; - __IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */ - __IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */ - __IO uint32_t PCONP1; /*!< Offset: 0x0C8 (R/W) Power Control for Peripherals Register */ - uint32_t RESERVED3[13]; - __IO uint32_t EMCCLKSEL; /*!< Offset: 0x100 (R/W) External Memory Controller Clock Selection Register */ - __IO uint32_t CCLKSEL; /*!< Offset: 0x104 (R/W) CPU Clock Selection Register */ - __IO uint32_t USBCLKSEL; /*!< Offset: 0x108 (R/W) USB Clock Selection Register */ - __IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */ - __IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */ - __IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */ - uint32_t RESERVED4[10]; - __IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */ - uint32_t RESERVED5[1]; - __IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */ - __IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */ - uint32_t RESERVED6[12]; - __IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */ - uint32_t RESERVED7[7]; - __IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */ - __IO uint32_t IRCTRIM; /*!< Offset: 0x1A4 (R/W) Clock Dividers */ - __IO uint32_t PCLKSEL; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Selection Register */ - uint32_t RESERVED8; - __IO uint32_t PBOOST; /*!< Offset: 0x1B0 (R/W) Power Boost control register */ - __IO uint32_t SPIFICLKSEL; - __IO uint32_t LCD_CFG; /*!< Offset: 0x1B8 (R/W) LCD Configuration and clocking control Register */ - uint32_t RESERVED10[1]; - __IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */ - __IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */ - __IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */ - __IO uint32_t RSTCON0; /*!< Offset: 0x1CC (R/W) RESET Control0 Register */ - __IO uint32_t RSTCON1; /*!< Offset: 0x1D0 (R/W) RESET Control1 Register */ - uint32_t RESERVED11[2]; - __IO uint32_t EMCDLYCTL; /*!< Offset: 0x1DC (R/W) SDRAM programmable delays */ - __IO uint32_t EMCCAL; /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */ - } LPC_SC_TypeDef; -/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ -typedef struct -{ - __IO uint32_t MAC1; /* MAC Registers */ - __IO uint32_t MAC2; - __IO uint32_t IPGT; - __IO uint32_t IPGR; - __IO uint32_t CLRT; - __IO uint32_t MAXF; - __IO uint32_t SUPP; - __IO uint32_t TEST; - __IO uint32_t MCFG; - __IO uint32_t MCMD; - __IO uint32_t MADR; - __O uint32_t MWTD; - __I uint32_t MRDD; - __I uint32_t MIND; - uint32_t RESERVED0[2]; - __IO uint32_t SA0; - __IO uint32_t SA1; - __IO uint32_t SA2; - uint32_t RESERVED1[45]; - __IO uint32_t Command; /* Control Registers */ - __I uint32_t Status; - __IO uint32_t RxDescriptor; - __IO uint32_t RxStatus; - __IO uint32_t RxDescriptorNumber; - __I uint32_t RxProduceIndex; - __IO uint32_t RxConsumeIndex; - __IO uint32_t TxDescriptor; - __IO uint32_t TxStatus; - __IO uint32_t TxDescriptorNumber; - __IO uint32_t TxProduceIndex; - __I uint32_t TxConsumeIndex; - uint32_t RESERVED2[10]; - __I uint32_t TSV0; - __I uint32_t TSV1; - __I uint32_t RSV; - uint32_t RESERVED3[3]; - __IO uint32_t FlowControlCounter; - __I uint32_t FlowControlStatus; - uint32_t RESERVED4[34]; - __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ - __I uint32_t RxFilterWoLStatus; - __O uint32_t RxFilterWoLClear; - uint32_t RESERVED5; - __IO uint32_t HashFilterL; - __IO uint32_t HashFilterH; - uint32_t RESERVED6[882]; - __I uint32_t IntStatus; /* Module Control Registers */ - __IO uint32_t IntEnable; - __O uint32_t IntClear; - __O uint32_t IntSet; - uint32_t RESERVED7; - __IO uint32_t PowerDown; - uint32_t RESERVED8; - __IO uint32_t Module_ID; -} LPC_EMAC_TypeDef; - -/*------------- LCD controller (LCD) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t TIMH; /* LCD Registers */ - __IO uint32_t TIMV; - __IO uint32_t POL; - __IO uint32_t LE; - __IO uint32_t UPBASE; - __IO uint32_t LPBASE; - __IO uint32_t CTRL; - __IO uint32_t INTMSK; - __I uint32_t INTRAW; - __I uint32_t INTSTAT; - __O uint32_t INTCLR; - __I uint32_t UPCURR; - __I uint32_t LPCURR; - uint32_t RESERVED0[115]; - __IO uint32_t PAL[128]; - uint32_t RESERVED1[256]; - __IO uint32_t CRSR_IMG[256]; - __IO uint32_t CRSR_CTRL; - __IO uint32_t CRSR_CFG; - __IO uint32_t CRSR_PAL0; - __IO uint32_t CRSR_PAL1; - __IO uint32_t CRSR_XY; - __IO uint32_t CRSR_CLIP; - uint32_t RESERVED2[2]; - __IO uint32_t CRSR_INTMSK; - __O uint32_t CRSR_INTCLR; - __I uint32_t CRSR_INTRAW; - __I uint32_t CRSR_INTSTAT; -} LPC_LCD_TypeDef; - -/*------------- Universal Serial Bus (USB) -----------------------------------*/ -typedef struct -{ - __I uint32_t Revision; /* USB Host Registers */ - __IO uint32_t Control; - __IO uint32_t CommandStatus; - __IO uint32_t InterruptStatus; - __IO uint32_t InterruptEnable; - __IO uint32_t InterruptDisable; - __IO uint32_t HCCA; - __I uint32_t PeriodCurrentED; - __IO uint32_t ControlHeadED; - __IO uint32_t ControlCurrentED; - __IO uint32_t BulkHeadED; - __IO uint32_t BulkCurrentED; - __I uint32_t DoneHead; - __IO uint32_t FmInterval; - __I uint32_t FmRemaining; - __I uint32_t FmNumber; - __IO uint32_t PeriodicStart; - __IO uint32_t LSTreshold; - __IO uint32_t RhDescriptorA; - __IO uint32_t RhDescriptorB; - __IO uint32_t RhStatus; - __IO uint32_t RhPortStatus1; - __IO uint32_t RhPortStatus2; - uint32_t RESERVED0[40]; - __I uint32_t Module_ID; - - __I uint32_t IntSt; /* USB On-The-Go Registers */ - __IO uint32_t IntEn; - __O uint32_t IntSet; - __O uint32_t IntClr; - __IO uint32_t StCtrl; - __IO uint32_t Tmr; - uint32_t RESERVED1[58]; - - __I uint32_t DevIntSt; /* USB Device Interrupt Registers */ - __IO uint32_t DevIntEn; - __O uint32_t DevIntClr; - __O uint32_t DevIntSet; - - __O uint32_t CmdCode; /* USB Device SIE Command Registers */ - __I uint32_t CmdData; - - __I uint32_t RxData; /* USB Device Transfer Registers */ - __O uint32_t TxData; - __I uint32_t RxPLen; - __O uint32_t TxPLen; - __IO uint32_t Ctrl; - __O uint32_t DevIntPri; - - __I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */ - __IO uint32_t EpIntEn; - __O uint32_t EpIntClr; - __O uint32_t EpIntSet; - __O uint32_t EpIntPri; - - __IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/ - __O uint32_t EpInd; - __IO uint32_t MaxPSize; - - __I uint32_t DMARSt; /* USB Device DMA Registers */ - __O uint32_t DMARClr; - __O uint32_t DMARSet; - uint32_t RESERVED2[9]; - __IO uint32_t UDCAH; - __I uint32_t EpDMASt; - __O uint32_t EpDMAEn; - __O uint32_t EpDMADis; - __I uint32_t DMAIntSt; - __IO uint32_t DMAIntEn; - uint32_t RESERVED3[2]; - __I uint32_t EoTIntSt; - __O uint32_t EoTIntClr; - __O uint32_t EoTIntSet; - __I uint32_t NDDRIntSt; - __O uint32_t NDDRIntClr; - __O uint32_t NDDRIntSet; - __I uint32_t SysErrIntSt; - __O uint32_t SysErrIntClr; - __O uint32_t SysErrIntSet; - uint32_t RESERVED4[15]; - - union { - __I uint32_t I2C_RX; /* USB OTG I2C Registers */ - __O uint32_t I2C_TX; - }; - __IO uint32_t I2C_STS; - __IO uint32_t I2C_CTL; - __IO uint32_t I2C_CLKHI; - __O uint32_t I2C_CLKLO; - uint32_t RESERVED5[824]; - - union { - __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ - __IO uint32_t OTGClkCtrl; - }; - union { - __I uint32_t USBClkSt; - __I uint32_t OTGClkSt; - }; -} LPC_USB_TypeDef; - -/*------------- CRC Engine (CRC) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t MODE; - __IO uint32_t SEED; - union { - __I uint32_t SUM; - struct { - __O uint32_t DATA; - } WR_DATA_DWORD; - - struct { - __O uint16_t DATA; - uint16_t RESERVED; - }WR_DATA_WORD; - - struct { - __O uint8_t DATA; - uint8_t RESERVED[3]; - }WR_DATA_BYTE; - }; -} LPC_CRC_TypeDef; -/*------------- General Purpose Input/Output (GPIO) --------------------------*/ -typedef struct -{ - __IO uint32_t DIR; - uint32_t RESERVED0[3]; - __IO uint32_t MASK; - __IO uint32_t PIN; - __IO uint32_t SET; - __O uint32_t CLR; -} LPC_GPIO_TypeDef; - -typedef struct -{ - __I uint32_t IntStatus; - __I uint32_t IO0IntStatR; - __I uint32_t IO0IntStatF; - __O uint32_t IO0IntClr; - __IO uint32_t IO0IntEnR; - __IO uint32_t IO0IntEnF; - uint32_t RESERVED0[3]; - __I uint32_t IO2IntStatR; - __I uint32_t IO2IntStatF; - __O uint32_t IO2IntClr; - __IO uint32_t IO2IntEnR; - __IO uint32_t IO2IntEnF; -} LPC_GPIOINT_TypeDef; - -/*------------- External Memory Controller (EMC) -----------------------------*/ -typedef struct -{ - __IO uint32_t Control; - __I uint32_t Status; - __IO uint32_t Config; - uint32_t RESERVED0[5]; - __IO uint32_t DynamicControl; - __IO uint32_t DynamicRefresh; - __IO uint32_t DynamicReadConfig; - uint32_t RESERVED1[1]; - __IO uint32_t DynamicRP; - __IO uint32_t DynamicRAS; - __IO uint32_t DynamicSREX; - __IO uint32_t DynamicAPR; - __IO uint32_t DynamicDAL; - __IO uint32_t DynamicWR; - __IO uint32_t DynamicRC; - __IO uint32_t DynamicRFC; - __IO uint32_t DynamicXSR; - __IO uint32_t DynamicRRD; - __IO uint32_t DynamicMRD; - uint32_t RESERVED2[9]; - __IO uint32_t StaticExtendedWait; - uint32_t RESERVED3[31]; - __IO uint32_t DynamicConfig0; - __IO uint32_t DynamicRasCas0; - uint32_t RESERVED4[6]; - __IO uint32_t DynamicConfig1; - __IO uint32_t DynamicRasCas1; - uint32_t RESERVED5[6]; - __IO uint32_t DynamicConfig2; - __IO uint32_t DynamicRasCas2; - uint32_t RESERVED6[6]; - __IO uint32_t DynamicConfig3; - __IO uint32_t DynamicRasCas3; - uint32_t RESERVED7[38]; - __IO uint32_t StaticConfig0; - __IO uint32_t StaticWaitWen0; - __IO uint32_t StaticWaitOen0; - __IO uint32_t StaticWaitRd0; - __IO uint32_t StaticWaitPage0; - __IO uint32_t StaticWaitWr0; - __IO uint32_t StaticWaitTurn0; - uint32_t RESERVED8[1]; - __IO uint32_t StaticConfig1; - __IO uint32_t StaticWaitWen1; - __IO uint32_t StaticWaitOen1; - __IO uint32_t StaticWaitRd1; - __IO uint32_t StaticWaitPage1; - __IO uint32_t StaticWaitWr1; - __IO uint32_t StaticWaitTurn1; - uint32_t RESERVED9[1]; - __IO uint32_t StaticConfig2; - __IO uint32_t StaticWaitWen2; - __IO uint32_t StaticWaitOen2; - __IO uint32_t StaticWaitRd2; - __IO uint32_t StaticWaitPage2; - __IO uint32_t StaticWaitWr2; - __IO uint32_t StaticWaitTurn2; - uint32_t RESERVED10[1]; - __IO uint32_t StaticConfig3; - __IO uint32_t StaticWaitWen3; - __IO uint32_t StaticWaitOen3; - __IO uint32_t StaticWaitRd3; - __IO uint32_t StaticWaitPage3; - __IO uint32_t StaticWaitWr3; - __IO uint32_t StaticWaitTurn3; -} LPC_EMC_TypeDef; - -/*------------- Watchdog Timer (WDT) -----------------------------------------*/ -typedef struct -{ - __IO uint8_t MOD; - uint8_t RESERVED0[3]; - __IO uint32_t TC; - __O uint8_t FEED; - uint8_t RESERVED1[3]; - __I uint32_t TV; - uint32_t RESERVED2; - __IO uint32_t WARNINT; - __IO uint32_t WINDOW; -} LPC_WDT_TypeDef; - -/*------------- Timer (TIM) --------------------------------------------------*/ -typedef struct -{ - __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */ - __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */ - __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */ - __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */ - __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */ - __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */ - __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */ - __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */ - __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */ - __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */ - __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */ - __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */ - __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */ - uint32_t RESERVED0[2]; - __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */ - uint32_t RESERVED1[12]; - __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */ -} LPC_TIM_TypeDef; - - -/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ -typedef struct -{ - __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */ - __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */ - __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */ - __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */ - __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */ - __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */ - __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */ - __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */ - __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */ - __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */ - __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */ - __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */ - __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */ - __I uint32_t CR2; /*!< Offset: 0x034 Capture Register 2 (R/ ) */ - __I uint32_t CR3; /*!< Offset: 0x038 Capture Register 3 (R/ ) */ - uint32_t RESERVED0; - __IO uint32_t MR4; /*!< Offset: 0x040 Match Register 4 (R/W) */ - __IO uint32_t MR5; /*!< Offset: 0x044 Match Register 5 (R/W) */ - __IO uint32_t MR6; /*!< Offset: 0x048 Match Register 6 (R/W) */ - __IO uint32_t PCR; /*!< Offset: 0x04C PWM Control Register (R/W) */ - __IO uint32_t LER; /*!< Offset: 0x050 Load Enable Register (R/W) */ - uint32_t RESERVED1[7]; - __IO uint32_t CTCR; /*!< Offset: 0x070 Counter Control Register (R/W) */ -} LPC_PWM_TypeDef; - -/*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/ -/* There are three types of UARTs on the chip: -(1) UART0,UART2, and UART3 are the standard UART. -(2) UART1 is the standard with modem capability. -(3) USART(UART4) is the sync/async UART with smart card capability. -More details can be found on the Users Manual. */ - -#if 0 -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[7]; - __I uint8_t LSR; - uint8_t RESERVED2[7]; - __IO uint8_t SCR; - uint8_t RESERVED3[3]; - __IO uint32_t ACR; - __IO uint8_t ICR; - uint8_t RESERVED4[3]; - __IO uint8_t FDR; - uint8_t RESERVED5[7]; - __IO uint8_t TER; - uint8_t RESERVED6[39]; - __I uint8_t FIFOLVL; -} LPC_UART_TypeDef; -#else -typedef struct -{ - union - { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union - { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union - { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[7];//Reserved - __I uint8_t LSR; - uint8_t RESERVED2[7];//Reserved - __IO uint8_t SCR; - uint8_t RESERVED3[3];//Reserved - __IO uint32_t ACR; - __IO uint8_t ICR; - uint8_t RESERVED4[3];//Reserved - __IO uint8_t FDR; - uint8_t RESERVED5[7];//Reserved - __IO uint8_t TER; - uint8_t RESERVED8[27];//Reserved - __IO uint8_t RS485CTRL; - uint8_t RESERVED9[3];//Reserved - __IO uint8_t ADRMATCH; - uint8_t RESERVED10[3];//Reserved - __IO uint8_t RS485DLY; - uint8_t RESERVED11[3];//Reserved - __I uint8_t FIFOLVL; -}LPC_UART_TypeDef; -#endif - - -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[3]; - __IO uint8_t MCR; - uint8_t RESERVED2[3]; - __I uint8_t LSR; - uint8_t RESERVED3[3]; - __I uint8_t MSR; - uint8_t RESERVED4[3]; - __IO uint8_t SCR; - uint8_t RESERVED5[3]; - __IO uint32_t ACR; - uint32_t RESERVED6; - __IO uint32_t FDR; - uint32_t RESERVED7; - __IO uint8_t TER; - uint8_t RESERVED8[27]; - __IO uint8_t RS485CTRL; - uint8_t RESERVED9[3]; - __IO uint8_t ADRMATCH; - uint8_t RESERVED10[3]; - __IO uint8_t RS485DLY; - uint8_t RESERVED11[3]; - __I uint8_t FIFOLVL; -} LPC_UART1_TypeDef; - -typedef struct -{ - union { - __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */ - __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */ - __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */ - }; - union { - __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */ - __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */ - }; - union { - __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */ - __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */ - }; - __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */ - __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */ - __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */ - __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */ - __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */ - __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */ - __IO uint32_t ICR; /*!< Offset: 0x024 irDA Control Register (R/W) */ - __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */ - __IO uint32_t OSR; /*!< Offset: 0x02C Over sampling Register (R/W) */ - __O uint32_t POP; /*!< Offset: 0x030 NHP Pop Register (W) */ - __IO uint32_t MODE; /*!< Offset: 0x034 NHP Mode selection Register (W) */ - uint32_t RESERVED0[2]; - __IO uint32_t HDEN; /*!< Offset: 0x040 Half duplex Enable Register (R/W) */ - uint32_t RESERVED1; - __IO uint32_t SCI_CTRL; /*!< Offset: 0x048 Smart card Interface Control Register (R/W) */ - __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */ - __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */ - __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */ - __IO uint32_t SYNCCTRL; /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */ - __IO uint32_t TER; /*!< Offset: 0x05C Transmit Enable Register (R/W) */ - uint32_t RESERVED2[989]; - __I uint32_t CFG; /*!< Offset: 0xFD4 Configuration Register (R) */ - __O uint32_t INTCE; /*!< Offset: 0xFD8 Interrupt Clear Enable Register (W) */ - __O uint32_t INTSE; /*!< Offset: 0xFDC Interrupt Set Enable Register (W) */ - __I uint32_t INTS; /*!< Offset: 0xFE0 Interrupt Status Register (R) */ - __I uint32_t INTE; /*!< Offset: 0xFE4 Interrupt Enable Register (R) */ - __O uint32_t INTCS; /*!< Offset: 0xFE8 Interrupt Clear Status Register (W) */ - __O uint32_t INTSS; /*!< Offset: 0xFEC Interrupt Set Status Register (W) */ - uint32_t RESERVED3[3]; - __I uint32_t MID; /*!< Offset: 0xFFC Module Identification Register (R) */ -} LPC_UART4_TypeDef; -/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ -typedef struct -{ - __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */ - __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */ - __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */ - __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */ - __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */ - __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */ - __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */ - __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */ - __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */ - __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */ - __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */ - __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */ - __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */ - __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */ - __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */ - __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */ -} LPC_I2C_TypeDef; - -/*------------- Real-Time Clock (RTC) ----------------------------------------*/ -typedef struct -{ - __IO uint8_t ILR; - uint8_t RESERVED0[7]; - __IO uint8_t CCR; - uint8_t RESERVED1[3]; - __IO uint8_t CIIR; - uint8_t RESERVED2[3]; - __IO uint8_t AMR; - uint8_t RESERVED3[3]; - __I uint32_t CTIME0; - __I uint32_t CTIME1; - __I uint32_t CTIME2; - __IO uint8_t SEC; - uint8_t RESERVED4[3]; - __IO uint8_t MIN; - uint8_t RESERVED5[3]; - __IO uint8_t HOUR; - uint8_t RESERVED6[3]; - __IO uint8_t DOM; - uint8_t RESERVED7[3]; - __IO uint8_t DOW; - uint8_t RESERVED8[3]; - __IO uint16_t DOY; - uint16_t RESERVED9; - __IO uint8_t MONTH; - uint8_t RESERVED10[3]; - __IO uint16_t YEAR; - uint16_t RESERVED11; - __IO uint32_t CALIBRATION; - __IO uint32_t GPREG0; - __IO uint32_t GPREG1; - __IO uint32_t GPREG2; - __IO uint32_t GPREG3; - __IO uint32_t GPREG4; - __IO uint8_t RTC_AUXEN; - uint8_t RESERVED12[3]; - __IO uint8_t RTC_AUX; - uint8_t RESERVED13[3]; - __IO uint8_t ALSEC; - uint8_t RESERVED14[3]; - __IO uint8_t ALMIN; - uint8_t RESERVED15[3]; - __IO uint8_t ALHOUR; - uint8_t RESERVED16[3]; - __IO uint8_t ALDOM; - uint8_t RESERVED17[3]; - __IO uint8_t ALDOW; - uint8_t RESERVED18[3]; - __IO uint16_t ALDOY; - uint16_t RESERVED19; - __IO uint8_t ALMON; - uint8_t RESERVED20[3]; - __IO uint16_t ALYEAR; - uint16_t RESERVED21; - __IO uint32_t ERSTATUS; - __IO uint32_t ERCONTROL; - __IO uint32_t ERCOUNTERS; - uint32_t RESERVED22; - __IO uint32_t ERFIRSTSTAMP0; - __IO uint32_t ERFIRSTSTAMP1; - __IO uint32_t ERFIRSTSTAMP2; - uint32_t RESERVED23; - __IO uint32_t ERLASTSTAMP0; - __IO uint32_t ERLASTSTAMP1; - __IO uint32_t ERLASTSTAMP2; -} LPC_RTC_TypeDef; - - - -/*------------- Pin Connect Block (PINCON) -----------------------------------*/ -typedef struct -{ - __IO uint32_t P0_0; /* 0x000 */ - __IO uint32_t P0_1; - __IO uint32_t P0_2; - __IO uint32_t P0_3; - __IO uint32_t P0_4; - __IO uint32_t P0_5; - __IO uint32_t P0_6; - __IO uint32_t P0_7; - - __IO uint32_t P0_8; /* 0x020 */ - __IO uint32_t P0_9; - __IO uint32_t P0_10; - __IO uint32_t P0_11; - __IO uint32_t P0_12; - __IO uint32_t P0_13; - __IO uint32_t P0_14; - __IO uint32_t P0_15; - - __IO uint32_t P0_16; /* 0x040 */ - __IO uint32_t P0_17; - __IO uint32_t P0_18; - __IO uint32_t P0_19; - __IO uint32_t P0_20; - __IO uint32_t P0_21; - __IO uint32_t P0_22; - __IO uint32_t P0_23; - - __IO uint32_t P0_24; /* 0x060 */ - __IO uint32_t P0_25; - __IO uint32_t P0_26; - __IO uint32_t P0_27; - __IO uint32_t P0_28; - __IO uint32_t P0_29; - __IO uint32_t P0_30; - __IO uint32_t P0_31; - - __IO uint32_t P1_0; /* 0x080 */ - __IO uint32_t P1_1; - __IO uint32_t P1_2; - __IO uint32_t P1_3; - __IO uint32_t P1_4; - __IO uint32_t P1_5; - __IO uint32_t P1_6; - __IO uint32_t P1_7; - - __IO uint32_t P1_8; /* 0x0A0 */ - __IO uint32_t P1_9; - __IO uint32_t P1_10; - __IO uint32_t P1_11; - __IO uint32_t P1_12; - __IO uint32_t P1_13; - __IO uint32_t P1_14; - __IO uint32_t P1_15; - - __IO uint32_t P1_16; /* 0x0C0 */ - __IO uint32_t P1_17; - __IO uint32_t P1_18; - __IO uint32_t P1_19; - __IO uint32_t P1_20; - __IO uint32_t P1_21; - __IO uint32_t P1_22; - __IO uint32_t P1_23; - - __IO uint32_t P1_24; /* 0x0E0 */ - __IO uint32_t P1_25; - __IO uint32_t P1_26; - __IO uint32_t P1_27; - __IO uint32_t P1_28; - __IO uint32_t P1_29; - __IO uint32_t P1_30; - __IO uint32_t P1_31; - - __IO uint32_t P2_0; /* 0x100 */ - __IO uint32_t P2_1; - __IO uint32_t P2_2; - __IO uint32_t P2_3; - __IO uint32_t P2_4; - __IO uint32_t P2_5; - __IO uint32_t P2_6; - __IO uint32_t P2_7; - - __IO uint32_t P2_8; /* 0x120 */ - __IO uint32_t P2_9; - __IO uint32_t P2_10; - __IO uint32_t P2_11; - __IO uint32_t P2_12; - __IO uint32_t P2_13; - __IO uint32_t P2_14; - __IO uint32_t P2_15; - - __IO uint32_t P2_16; /* 0x140 */ - __IO uint32_t P2_17; - __IO uint32_t P2_18; - __IO uint32_t P2_19; - __IO uint32_t P2_20; - __IO uint32_t P2_21; - __IO uint32_t P2_22; - __IO uint32_t P2_23; - - __IO uint32_t P2_24; /* 0x160 */ - __IO uint32_t P2_25; - __IO uint32_t P2_26; - __IO uint32_t P2_27; - __IO uint32_t P2_28; - __IO uint32_t P2_29; - __IO uint32_t P2_30; - __IO uint32_t P2_31; - - __IO uint32_t P3_0; /* 0x180 */ - __IO uint32_t P3_1; - __IO uint32_t P3_2; - __IO uint32_t P3_3; - __IO uint32_t P3_4; - __IO uint32_t P3_5; - __IO uint32_t P3_6; - __IO uint32_t P3_7; - - __IO uint32_t P3_8; /* 0x1A0 */ - __IO uint32_t P3_9; - __IO uint32_t P3_10; - __IO uint32_t P3_11; - __IO uint32_t P3_12; - __IO uint32_t P3_13; - __IO uint32_t P3_14; - __IO uint32_t P3_15; - - __IO uint32_t P3_16; /* 0x1C0 */ - __IO uint32_t P3_17; - __IO uint32_t P3_18; - __IO uint32_t P3_19; - __IO uint32_t P3_20; - __IO uint32_t P3_21; - __IO uint32_t P3_22; - __IO uint32_t P3_23; - - __IO uint32_t P3_24; /* 0x1E0 */ - __IO uint32_t P3_25; - __IO uint32_t P3_26; - __IO uint32_t P3_27; - __IO uint32_t P3_28; - __IO uint32_t P3_29; - __IO uint32_t P3_30; - __IO uint32_t P3_31; - - __IO uint32_t P4_0; /* 0x200 */ - __IO uint32_t P4_1; - __IO uint32_t P4_2; - __IO uint32_t P4_3; - __IO uint32_t P4_4; - __IO uint32_t P4_5; - __IO uint32_t P4_6; - __IO uint32_t P4_7; - - __IO uint32_t P4_8; /* 0x220 */ - __IO uint32_t P4_9; - __IO uint32_t P4_10; - __IO uint32_t P4_11; - __IO uint32_t P4_12; - __IO uint32_t P4_13; - __IO uint32_t P4_14; - __IO uint32_t P4_15; - - __IO uint32_t P4_16; /* 0x240 */ - __IO uint32_t P4_17; - __IO uint32_t P4_18; - __IO uint32_t P4_19; - __IO uint32_t P4_20; - __IO uint32_t P4_21; - __IO uint32_t P4_22; - __IO uint32_t P4_23; - - __IO uint32_t P4_24; /* 0x260 */ - __IO uint32_t P4_25; - __IO uint32_t P4_26; - __IO uint32_t P4_27; - __IO uint32_t P4_28; - __IO uint32_t P4_29; - __IO uint32_t P4_30; - __IO uint32_t P4_31; - - __IO uint32_t P5_0; /* 0x280 */ - __IO uint32_t P5_1; - __IO uint32_t P5_2; - __IO uint32_t P5_3; - __IO uint32_t P5_4; /* 0x290 */ -} LPC_IOCON_TypeDef; - - - - - - -/*------------- Synchronous Serial Communication (SSP) -----------------------*/ -typedef struct -{ - __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */ - __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */ - __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */ - __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */ - __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */ - __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */ - __IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */ - __IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */ - __IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */ - __IO uint32_t DMACR; -} LPC_SSP_TypeDef; - -/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ -typedef struct -{ - __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */ - __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */ - uint32_t RESERVED0; - __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */ - __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */ - __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */ - __IO uint32_t ADTRM; -} LPC_ADC_TypeDef; - -/*------------- Controller Area Network (CAN) --------------------------------*/ -typedef struct -{ - __IO uint32_t mask[512]; /* ID Masks */ -} LPC_CANAF_RAM_TypeDef; - -typedef struct /* Acceptance Filter Registers */ -{ - ///Offset: 0x00000000 - Acceptance Filter Register - __IO uint32_t AFMR; - - ///Offset: 0x00000004 - Standard Frame Individual Start Address Register - __IO uint32_t SFF_sa; - - ///Offset: 0x00000008 - Standard Frame Group Start Address Register - __IO uint32_t SFF_GRP_sa; - - ///Offset: 0x0000000C - Extended Frame Start Address Register - __IO uint32_t EFF_sa; - - ///Offset: 0x00000010 - Extended Frame Group Start Address Register - __IO uint32_t EFF_GRP_sa; - - ///Offset: 0x00000014 - End of AF Tables register - __IO uint32_t ENDofTable; - - ///Offset: 0x00000018 - LUT Error Address register - __I uint32_t LUTerrAd; - - ///Offset: 0x0000001C - LUT Error Register - __I uint32_t LUTerr; - - ///Offset: 0x00000020 - CAN Central Transmit Status Register - __IO uint32_t FCANIE; - - ///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0 - __IO uint32_t FCANIC0; - - ///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1 - __IO uint32_t FCANIC1; -} LPC_CANAF_TypeDef; - -typedef struct /* Central Registers */ -{ - __I uint32_t TxSR; - __I uint32_t RxSR; - __I uint32_t MSR; -} LPC_CANCR_TypeDef; - -typedef struct /* Controller Registers */ -{ - ///Offset: 0x00000000 - Controls the operating mode of the CAN Controller - __IO uint32_t MOD; - - ///Offset: 0x00000004 - Command bits that affect the state - __O uint32_t CMR; - - ///Offset: 0x00000008 - Global Controller Status and Error Counters - __IO uint32_t GSR; - - ///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture - __I uint32_t ICR; - - ///Offset: 0x00000010 - Interrupt Enable Register - __IO uint32_t IER; - - ///Offset: 0x00000014 - Bus Timing Register - __IO uint32_t BTR; - - ///Offset: 0x00000018 - Error Warning Limit - __IO uint32_t EWL; - - ///Offset: 0x0000001C - Status Register - __I uint32_t SR; - - ///Offset: 0x00000020 - Receive frame status - __IO uint32_t RFS; - - ///Offset: 0x00000024 - Received Identifier - __IO uint32_t RID; - - ///Offset: 0x00000028 - Received data bytes 1-4 - __IO uint32_t RDA; - - ///Offset: 0x0000002C - Received data bytes 5-8 - __IO uint32_t RDB; - - ///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1) - __IO uint32_t TFI1; - - ///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1) - __IO uint32_t TID1; - - ///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1) - __IO uint32_t TDA1; - - ///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1) - __IO uint32_t TDB1; - - ///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2) - __IO uint32_t TFI2; - - ///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2) - __IO uint32_t TID2; - - ///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2) - __IO uint32_t TDA2; - - ///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2) - __IO uint32_t TDB2; - - ///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3) - __IO uint32_t TFI3; - - ///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3) - __IO uint32_t TID3; - - ///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3) - __IO uint32_t TDA3; - - ///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3) - __IO uint32_t TDB3; -} LPC_CAN_TypeDef; - -/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CTRL; - __IO uint32_t CNTVAL; -} LPC_DAC_TypeDef; - - -/*------------- Inter IC Sound (I2S) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t DAO; - __IO uint32_t DAI; - __O uint32_t TXFIFO; - __I uint32_t RXFIFO; - __I uint32_t STATE; - __IO uint32_t DMA1; - __IO uint32_t DMA2; - __IO uint32_t IRQ; - __IO uint32_t TXRATE; - __IO uint32_t RXRATE; - __IO uint32_t TXBITRATE; - __IO uint32_t RXBITRATE; - __IO uint32_t TXMODE; - __IO uint32_t RXMODE; -} LPC_I2S_TypeDef; - - - - - - -/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ -typedef struct -{ - __I uint32_t CON; - __O uint32_t CON_SET; - __O uint32_t CON_CLR; - __I uint32_t CAPCON; - __O uint32_t CAPCON_SET; - __O uint32_t CAPCON_CLR; - __IO uint32_t TC0; - __IO uint32_t TC1; - __IO uint32_t TC2; - __IO uint32_t LIM0; - __IO uint32_t LIM1; - __IO uint32_t LIM2; - __IO uint32_t MAT0; - __IO uint32_t MAT1; - __IO uint32_t MAT2; - __IO uint32_t DT; - __IO uint32_t CP; - __IO uint32_t CAP0; - __IO uint32_t CAP1; - __IO uint32_t CAP2; - __I uint32_t INTEN; - __O uint32_t INTEN_SET; - __O uint32_t INTEN_CLR; - __I uint32_t CNTCON; - __O uint32_t CNTCON_SET; - __O uint32_t CNTCON_CLR; - __I uint32_t INTF; - __O uint32_t INTF_SET; - __O uint32_t INTF_CLR; - __O uint32_t CAP_CLR; -} LPC_MCPWM_TypeDef; - -/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ -typedef struct -{ - __O uint32_t CON; - __I uint32_t STAT; - __IO uint32_t CONF; - __I uint32_t POS; - __IO uint32_t MAXPOS; - __IO uint32_t CMPOS0; - __IO uint32_t CMPOS1; - __IO uint32_t CMPOS2; - __I uint32_t INXCNT; - __IO uint32_t INXCMP0; - __IO uint32_t LOAD; - __I uint32_t TIME; - __I uint32_t VEL; - __I uint32_t CAP; - __IO uint32_t VELCOMP; - __IO uint32_t FILTERPHA; - __IO uint32_t FILTERPHB; - __IO uint32_t FILTERINX; - __IO uint32_t WINDOW; - __IO uint32_t INXCMP1; - __IO uint32_t INXCMP2; - uint32_t RESERVED0[993]; - __O uint32_t IEC; - __O uint32_t IES; - __I uint32_t INTSTAT; - __I uint32_t IE; - __O uint32_t CLR; - __O uint32_t SET; -} LPC_QEI_TypeDef; - -/*------------- SD/MMC card Interface (MCI)-----------------------------------*/ -typedef struct -{ - __IO uint32_t POWER; - __IO uint32_t CLOCK; - __IO uint32_t ARGUMENT; - __IO uint32_t COMMAND; - __I uint32_t RESP_CMD; - __I uint32_t RESP0; - __I uint32_t RESP1; - __I uint32_t RESP2; - __I uint32_t RESP3; - __IO uint32_t DATATMR; - __IO uint32_t DATALEN; - __IO uint32_t DATACTRL; - __I uint32_t DATACNT; - __I uint32_t STATUS; - __O uint32_t CLEAR; - __IO uint32_t MASK0; - uint32_t RESERVED0[2]; - __I uint32_t FIFOCNT; - uint32_t RESERVED1[13]; - __IO uint32_t FIFO[16]; -} LPC_MCI_TypeDef; - - - - - - - - - - -/*------------- EEPROM Controller (EEPROM) -----------------------------------*/ -typedef struct -{ - __IO uint32_t CMD; /* 0x0080 */ - __IO uint32_t ADDR; - __IO uint32_t WDATA; - __IO uint32_t RDATA; - __IO uint32_t WSTATE; /* 0x0090 */ - __IO uint32_t CLKDIV; - __IO uint32_t PWRDWN; /* 0x0098 */ - uint32_t RESERVED0[975]; - __IO uint32_t INT_CLR_ENABLE; /* 0x0FD8 */ - __IO uint32_t INT_SET_ENABLE; - __IO uint32_t INT_STATUS; /* 0x0FE0 */ - __IO uint32_t INT_ENABLE; - __IO uint32_t INT_CLR_STATUS; - __IO uint32_t INT_SET_STATUS; -} LPC_EEPROM_TypeDef; - - -/*------------- COMPARATOR ----------------------------------------------------*/ - -typedef struct { /*!< (@ 0x40020000) COMPARATOR Structure */ - __IO uint32_t CTRL; /*!< (@ 0x40020000) Comparator block control register */ - __IO uint32_t CTRL0; /*!< (@ 0x40020004) Comparator 0 control register */ - __IO uint32_t CTRL1; /*!< (@ 0x40020008) Comparator 1 control register */ -} LPC_COMPARATOR_Type; - - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#elif defined ( __ICCARM__ ) -#pragma language=restore -#endif - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* Base addresses */ -#define LPC_FLASH_BASE (0x00000000UL) -#define LPC_RAM_BASE (0x10000000UL) -#define LPC_PERI_RAM_BASE (0x20000000UL) -#define LPC_APB0_BASE (0x40000000UL) -#define LPC_APB1_BASE (0x40080000UL) -#define LPC_AHBRAM1_BASE (0x20004000UL) -#define LPC_AHB_BASE (0x20080000UL) -#define LPC_CM3_BASE (0xE0000000UL) - -/* APB0 peripherals */ -#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) -#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) -#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) -#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) -#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) -#define LPC_PWM0_BASE (LPC_APB0_BASE + 0x14000) -#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) -#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) -#define LPC_COMPARATOR_BASE (LPC_APB0_BASE + 0x20000) -#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) -#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) -#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x2C000) -#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) -#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) -#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) -#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) -#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) -#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) -#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) -#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) - -/* APB1 peripherals */ -#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) -#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) -#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) -#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) -#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) -#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) -#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) -#define LPC_UART4_BASE (LPC_APB1_BASE + 0x24000) -#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) -#define LPC_SSP2_BASE (LPC_APB1_BASE + 0x2C000) -#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) -#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) -#define LPC_MCI_BASE (LPC_APB1_BASE + 0x40000) -#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) - -/* AHB peripherals */ -#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x00100) -#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x00120) -#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x00140) -#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x00160) -#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x00180) -#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x001A0) -#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x001C0) -#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x001E0) -#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x04000) -#define LPC_LCD_BASE (LPC_AHB_BASE + 0x08000) -#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) -#define LPC_CRC_BASE (LPC_AHB_BASE + 0x10000) -#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x18000) -#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x18020) -#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x18040) -#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x18060) -#define LPC_GPIO4_BASE (LPC_AHB_BASE + 0x18080) -#define LPC_GPIO5_BASE (LPC_AHB_BASE + 0x180A0) -#define LPC_EMC_BASE (LPC_AHB_BASE + 0x1C000) - -#define LPC_EEPROM_BASE (LPC_FLASH_BASE+ 0x200080) - - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) -#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) -#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) -#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) -#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) -#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) -#define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE ) -#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) -#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) -#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) -#define LPC_UART4 ((LPC_UART4_TypeDef *) LPC_UART4_BASE ) -#define LPC_PWM0 ((LPC_PWM_TypeDef *) LPC_PWM0_BASE ) -#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) -#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) -#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) -#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) -#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) -#define LPC_COMPARATOR ((LPC_COMPARATOR_Type *) LPC_COMPARATOR_BASE) -#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) -#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) -#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) -#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) -#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) -#define LPC_SSP2 ((LPC_SSP_TypeDef *) LPC_SSP2_BASE ) -#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) -#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) -#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) -#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) -#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) -#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) -#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) -#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) -#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) -#define LPC_MCI ((LPC_MCI_TypeDef *) LPC_MCI_BASE ) -#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) -#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) -#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) -#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) -#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) -#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) -#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) -#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) -#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) -#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) -#define LPC_LCD ((LPC_LCD_TypeDef *) LPC_LCD_BASE ) -#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) -#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) -#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) -#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) -#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) -#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) -#define LPC_GPIO5 ((LPC_GPIO_TypeDef *) LPC_GPIO5_BASE ) -#define LPC_EMC ((LPC_EMC_TypeDef *) LPC_EMC_BASE ) -#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE ) -#define LPC_EEPROM ((LPC_EEPROM_TypeDef *) LPC_EEPROM_BASE ) - - - -#endif // __LPC407x_8x_177x_8x_H__ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/system_LPC177x_8x.h b/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/system_LPC177x_8x.h deleted file mode 100644 index 464225eca38..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/system_LPC177x_8x.h +++ /dev/null @@ -1,89 +0,0 @@ -/********************************************************************** -* $Id$ system_LPC177x_8x.h 2011-06-02 -*//** -* @file system_LPC177x_8x.h -* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File -* for the NXP LPC177x_8x Device Series -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -#ifndef __SYSTEM_LPC177x_8x_H -#define __SYSTEM_LPC177x_8x_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */ -extern uint32_t EMCClock; /*!< EMC Clock */ -extern uint32_t USBClock; /*!< USB Frequency */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (12000000UL) /* Oscillator frequency */ -#define OSC_CLK ( XTAL) /* Main oscillator frequency */ -#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */ -#define IRC_OSC (12000000UL) /* Internal RC oscillator frequency */ -#define WDT_OSC ( 500000UL) /* Internal WDT oscillator frequency */ - - - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC177x_8x_H */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/system_LPC407x_8x_177x_8x.h b/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/system_LPC407x_8x_177x_8x.h deleted file mode 100644 index 18a54a0d7f5..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/system_LPC407x_8x_177x_8x.h +++ /dev/null @@ -1,89 +0,0 @@ -/********************************************************************** -* $Id$ system_LPC407x_8x_177x_8x.h 2011-06-02 -*//** -* @file system_LPC407x_8x_177x_8x.h -* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File -* for the NXP LPC Device Series -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -#ifndef __SYSTEM_LPC407x_8x_177x_8x_H -#define __SYSTEM_LPC407x_8x_177x_8x_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */ -extern uint32_t EMCClock; /*!< EMC Clock */ -extern uint32_t USBClock; /*!< USB Frequency */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (12000000UL) /* Oscillator frequency */ -#define OSC_CLK ( XTAL) /* Main oscillator frequency */ -#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */ -#define IRC_OSC (12000000UL) /* Internal RC oscillator frequency */ -#define WDT_OSC ( 500000UL) /* Internal WDT oscillator frequency */ - - - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC407x_8x_177x_8x_H */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/ARM/startup_LPC177x_8x.s b/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/ARM/startup_LPC177x_8x.s deleted file mode 100644 index 59cc885de3d..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/ARM/startup_LPC177x_8x.s +++ /dev/null @@ -1,301 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC177x_8x.s -; * @purpose: CMSIS Cortex-M3 Core Device Startup File -; * for the NXP LPC177x_8x Device Series -; * @version: V1.20 -; * @date: 07. October 2010 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2010 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000200 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WDT_IRQHandler ; 16: Watchdog Timer - DCD TIMER0_IRQHandler ; 17: Timer0 - DCD TIMER1_IRQHandler ; 18: Timer1 - DCD TIMER2_IRQHandler ; 19: Timer2 - DCD TIMER3_IRQHandler ; 20: Timer3 - DCD UART0_IRQHandler ; 21: UART0 - DCD UART1_IRQHandler ; 22: UART1 - DCD UART2_IRQHandler ; 23: UART2 - DCD UART3_IRQHandler ; 24: UART3 - DCD PWM1_IRQHandler ; 25: PWM1 - DCD I2C0_IRQHandler ; 26: I2C0 - DCD I2C1_IRQHandler ; 27: I2C1 - DCD I2C2_IRQHandler ; 28: I2C2 - DCD 0 ; 29: reserved, not for SPIFI anymore - DCD SSP0_IRQHandler ; 30: SSP0 - DCD SSP1_IRQHandler ; 31: SSP1 - DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL) - DCD RTC_IRQHandler ; 33: Real Time Clock - DCD EINT0_IRQHandler ; 34: External Interrupt 0 - DCD EINT1_IRQHandler ; 35: External Interrupt 1 - DCD EINT2_IRQHandler ; 36: External Interrupt 2 - DCD EINT3_IRQHandler ; 37: External Interrupt 3 - DCD ADC_IRQHandler ; 38: A/D Converter - DCD BOD_IRQHandler ; 39: Brown-Out Detect - DCD USB_IRQHandler ; 40: USB - DCD CAN_IRQHandler ; 41: CAN - DCD DMA_IRQHandler ; 42: General Purpose DMA - DCD I2S_IRQHandler ; 43: I2S - DCD ENET_IRQHandler ; 44: Ethernet - DCD MCI_IRQHandler ; 45: SD/MMC card I/F - DCD MCPWM_IRQHandler ; 46: Motor Control PWM - DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface - DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) - DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup - DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup - DCD UART4_IRQHandler ; 51: UART4 - DCD SSP2_IRQHandler ; 52: SSP2 - DCD LCD_IRQHandler ; 53: LCD - DCD GPIO_IRQHandler ; 54: GPIO - DCD PWM0_IRQHandler ; 55: PWM0 - DCD EEPROM_IRQHandler ; 56: EEPROM - - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WDT_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT PWM1_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - ;EXPORT SPIFI_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT PLL0_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT EINT0_IRQHandler [WEAK] - EXPORT EINT1_IRQHandler [WEAK] - EXPORT EINT2_IRQHandler [WEAK] - EXPORT EINT3_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT USB_IRQHandler [WEAK] - EXPORT CAN_IRQHandler [WEAK] - EXPORT DMA_IRQHandler [WEAK] - EXPORT I2S_IRQHandler [WEAK] - EXPORT ENET_IRQHandler [WEAK] - EXPORT MCI_IRQHandler [WEAK] - EXPORT MCPWM_IRQHandler [WEAK] - EXPORT QEI_IRQHandler [WEAK] - EXPORT PLL1_IRQHandler [WEAK] - EXPORT USBActivity_IRQHandler [WEAK] - EXPORT CANActivity_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT SSP2_IRQHandler [WEAK] - EXPORT LCD_IRQHandler [WEAK] - EXPORT GPIO_IRQHandler [WEAK] - EXPORT PWM0_IRQHandler [WEAK] - EXPORT EEPROM_IRQHandler [WEAK] - -WDT_IRQHandler -TIMER0_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -UART3_IRQHandler -PWM1_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -I2C2_IRQHandler -;SPIFI_IRQHandler ;not used -SSP0_IRQHandler -SSP1_IRQHandler -PLL0_IRQHandler -RTC_IRQHandler -EINT0_IRQHandler -EINT1_IRQHandler -EINT2_IRQHandler -EINT3_IRQHandler -ADC_IRQHandler -BOD_IRQHandler -USB_IRQHandler -CAN_IRQHandler -DMA_IRQHandler -I2S_IRQHandler -ENET_IRQHandler -MCI_IRQHandler -MCPWM_IRQHandler -QEI_IRQHandler -PLL1_IRQHandler -USBActivity_IRQHandler -CANActivity_IRQHandler -UART4_IRQHandler -SSP2_IRQHandler -LCD_IRQHandler -GPIO_IRQHandler -PWM0_IRQHandler -EEPROM_IRQHandler - - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - - END diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/ARM/startup_LPC407x_8x_177x_8x.s b/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/ARM/startup_LPC407x_8x_177x_8x.s deleted file mode 100644 index bca9de93c87..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/ARM/startup_LPC407x_8x_177x_8x.s +++ /dev/null @@ -1,302 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC407x_8x.s -; * @purpose: CMSIS Cortex-M4 Core Device Startup File -; * for the NXP LPC407x_8x Device Series -; * @version: V1.20 -; * @date: 16. January 2012 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M4 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - ; DCD 0xEFFFF5D6 ; Reserved- vector sum - DCD 0xEFFFF39E ; Reserved- vector sum - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WDT_IRQHandler ; 16: Watchdog Timer - DCD TIMER0_IRQHandler ; 17: Timer0 - DCD TIMER1_IRQHandler ; 18: Timer1 - DCD TIMER2_IRQHandler ; 19: Timer2 - DCD TIMER3_IRQHandler ; 20: Timer3 - DCD UART0_IRQHandler ; 21: UART0 - DCD UART1_IRQHandler ; 22: UART1 - DCD UART2_IRQHandler ; 23: UART2 - DCD UART3_IRQHandler ; 24: UART3 - DCD PWM1_IRQHandler ; 25: PWM1 - DCD I2C0_IRQHandler ; 26: I2C0 - DCD I2C1_IRQHandler ; 27: I2C1 - DCD I2C2_IRQHandler ; 28: I2C2 - DCD 0 ; 29: reserved, not for SPIFI anymore - DCD SSP0_IRQHandler ; 30: SSP0 - DCD SSP1_IRQHandler ; 31: SSP1 - DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL) - DCD RTC_IRQHandler ; 33: Real Time Clock - DCD EINT0_IRQHandler ; 34: External Interrupt 0 - DCD EINT1_IRQHandler ; 35: External Interrupt 1 - DCD EINT2_IRQHandler ; 36: External Interrupt 2 - DCD EINT3_IRQHandler ; 37: External Interrupt 3 - DCD ADC_IRQHandler ; 38: A/D Converter - DCD BOD_IRQHandler ; 39: Brown-Out Detect - DCD USB_IRQHandler ; 40: USB - DCD CAN_IRQHandler ; 41: CAN - DCD DMA_IRQHandler ; 42: General Purpose DMA - DCD I2S_IRQHandler ; 43: I2S - DCD ENET_IRQHandler ; 44: Ethernet - DCD MCI_IRQHandler ; 45: SD/MMC card I/F - DCD MCPWM_IRQHandler ; 46: Motor Control PWM - DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface - DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) - DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup - DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup - DCD UART4_IRQHandler ; 51: UART4 - DCD SSP2_IRQHandler ; 52: SSP2 - DCD LCD_IRQHandler ; 53: LCD - DCD GPIO_IRQHandler ; 54: GPIO - DCD PWM0_IRQHandler ; 55: PWM0 - DCD EEPROM_IRQHandler ; 56: EEPROM - - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WDT_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT PWM1_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - ;EXPORT SPIFI_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT PLL0_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT EINT0_IRQHandler [WEAK] - EXPORT EINT1_IRQHandler [WEAK] - EXPORT EINT2_IRQHandler [WEAK] - EXPORT EINT3_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT USB_IRQHandler [WEAK] - EXPORT CAN_IRQHandler [WEAK] - EXPORT DMA_IRQHandler [WEAK] - EXPORT I2S_IRQHandler [WEAK] - EXPORT ENET_IRQHandler [WEAK] - EXPORT MCI_IRQHandler [WEAK] - EXPORT MCPWM_IRQHandler [WEAK] - EXPORT QEI_IRQHandler [WEAK] - EXPORT PLL1_IRQHandler [WEAK] - EXPORT USBActivity_IRQHandler [WEAK] - EXPORT CANActivity_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT SSP2_IRQHandler [WEAK] - EXPORT LCD_IRQHandler [WEAK] - EXPORT GPIO_IRQHandler [WEAK] - EXPORT PWM0_IRQHandler [WEAK] - EXPORT EEPROM_IRQHandler [WEAK] - -WDT_IRQHandler -TIMER0_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -UART3_IRQHandler -PWM1_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -I2C2_IRQHandler -;SPIFI_IRQHandler ;not used -SSP0_IRQHandler -SSP1_IRQHandler -PLL0_IRQHandler -RTC_IRQHandler -EINT0_IRQHandler -EINT1_IRQHandler -EINT2_IRQHandler -EINT3_IRQHandler -ADC_IRQHandler -BOD_IRQHandler -USB_IRQHandler -CAN_IRQHandler -DMA_IRQHandler -I2S_IRQHandler -ENET_IRQHandler -MCI_IRQHandler -MCPWM_IRQHandler -QEI_IRQHandler -PLL1_IRQHandler -USBActivity_IRQHandler -CANActivity_IRQHandler -UART4_IRQHandler -SSP2_IRQHandler -LCD_IRQHandler -GPIO_IRQHandler -PWM0_IRQHandler -EEPROM_IRQHandler - - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - - END diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/GCC/startup_LPC177x_8x.s b/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/GCC/startup_LPC177x_8x.s deleted file mode 100644 index 5d966a39b33..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/GCC/startup_LPC177x_8x.s +++ /dev/null @@ -1,279 +0,0 @@ -/*****************************************************************************/ -/* startup_LPC17xx.s: Startup file for LPC17xx device series */ -/*****************************************************************************/ -/* Version: CodeSourcery Sourcery G++ Lite (with CS3) */ -/*****************************************************************************/ - - -/* -//*** <<< Use Configuration Wizard in Context Menu >>> *** -*/ - - -/* -// Stack Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - - .equ Stack_Size, 0x00000100 - .section ".stack", "w" - .align 3 - .globl __cs3_stack_mem - .globl __cs3_stack_size -__cs3_stack_mem: - .if Stack_Size - .space Stack_Size - .endif - .size __cs3_stack_mem, . - __cs3_stack_mem - .set __cs3_stack_size, . - __cs3_stack_mem - - -/* -// Heap Configuration -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - - .equ Heap_Size, 0x00001000 - - .section ".heap", "w" - .align 3 - .globl __cs3_heap_start - .globl __cs3_heap_end -__cs3_heap_start: - .if Heap_Size - .space Heap_Size - .endif -__cs3_heap_end: - - -/* Vector Table */ - - .section ".cs3.interrupt_vector" - .globl __cs3_interrupt_vector_cortex_m - .type __cs3_interrupt_vector_cortex_m, %object - -__cs3_interrupt_vector_cortex_m: - .long __cs3_stack /* Top of Stack */ - .long __cs3_reset /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External Interrupts */ - .long WDT_IRQHandler /* 16: Watchdog Timer */ - .long TIMER0_IRQHandler /* 17: Timer0 */ - .long TIMER1_IRQHandler /* 18: Timer1 */ - .long TIMER2_IRQHandler /* 19: Timer2 */ - .long TIMER3_IRQHandler /* 20: Timer3 */ - .long UART0_IRQHandler /* 21: UART0 */ - .long UART1_IRQHandler /* 22: UART1 */ - .long UART2_IRQHandler /* 23: UART2 */ - .long UART3_IRQHandler /* 24: UART3 */ - .long PWM1_IRQHandler /* 25: PWM1 */ - .long I2C0_IRQHandler /* 26: I2C0 */ - .long I2C1_IRQHandler /* 27: I2C1 */ - .long I2C2_IRQHandler /* 28: I2C2 */ - .long 0 /* 29: Reserved, not for SPIFI anymore */ - .long SSP0_IRQHandler /* 30: SSP0 */ - .long SSP1_IRQHandler /* 31: SSP1 */ - .long PLL0_IRQHandler /* 32: PLL0 Lock (Main PLL) */ - .long RTC_IRQHandler /* 33: Real Time Clock */ - .long EINT0_IRQHandler /* 34: External Interrupt 0 */ - .long EINT1_IRQHandler /* 35: External Interrupt 1 */ - .long EINT2_IRQHandler /* 36: External Interrupt 2 */ - .long EINT3_IRQHandler /* 37: External Interrupt 3 */ - .long ADC_IRQHandler /* 38: A/D Converter */ - .long BOD_IRQHandler /* 39: Brown-Out Detect */ - .long USB_IRQHandler /* 40: USB */ - .long CAN_IRQHandler /* 41: CAN */ - .long DMA_IRQHandler /* 42: General Purpose DMA */ - .long I2S_IRQHandler /* 43: I2S */ - .long ENET_IRQHandler /* 44: Ethernet */ - .long MCI_IRQHandler /* 45: SD/MMC Card */ - .long MCPWM_IRQHandler /* 46: Motor Control PWM */ - .long QEI_IRQHandler /* 47: Quadrature Encoder Interface */ - .long PLL1_IRQHandler /* 48: PLL1 Lock (USB PLL) */ - .long USBActivity_IRQHandler /* 49: USB Activity */ - .long CANActivity_IRQHandler /* 50: CAN Activity */ - .long UART4_IRQHandler /* 51: UART4 */ - .long SSP2_IRQHandler /* 52: SSP2 */ - .long LCD_IRQHandler /* 53: LCD */ - .long GPIO_IRQHandler /* 54: GPIO */ - .long PWM0_IRQHandler /* 55: PWM0 */ - .long EEPROM_IRQHandler /* 56: EEPROM */ - - .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m - - - .thumb - - .section ".crp" - .globl CRP_Value -CRP_Value: - .long 0xFFFFFFFF - -/* Reset Handler */ - - .section .cs3.reset,"x",%progbits - .thumb_func - .globl __cs3_reset_cortex_m - .type __cs3_reset_cortex_m, %function -__cs3_reset_cortex_m: - .fnstart -.if (RAM_MODE) -/* Clear .bss section (Zero init) */ - MOV R0, #0 - LDR R1, =__bss_start__ - LDR R2, =__bss_end__ - CMP R1,R2 - BEQ BSSIsEmpty -LoopZI: - CMP R1, R2 - BHS BSSIsEmpty - STR R0, [R1] - ADD R1, #4 - BLO LoopZI -BSSIsEmpty: - LDR R0, =SystemInit - BLX R0 - LDR R0,=main - BX R0 -.else - LDR R0, =SystemInit - BLX R0 - LDR R0,=_start - BX R0 -.endif - .pool - .cantunwind - .fnend - .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m - - .section ".text" - -/* Exception Handlers */ - - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - B . - .size NMI_Handler, . - NMI_Handler - - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - B . - .size HardFault_Handler, . - HardFault_Handler - - .weak MemManage_Handler - .type MemManage_Handler, %function -MemManage_Handler: - B . - .size MemManage_Handler, . - MemManage_Handler - - .weak BusFault_Handler - .type BusFault_Handler, %function -BusFault_Handler: - B . - .size BusFault_Handler, . - BusFault_Handler - - .weak UsageFault_Handler - .type UsageFault_Handler, %function -UsageFault_Handler: - B . - .size UsageFault_Handler, . - UsageFault_Handler - - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - B . - .size SVC_Handler, . - SVC_Handler - - .weak DebugMon_Handler - .type DebugMon_Handler, %function -DebugMon_Handler: - B . - .size DebugMon_Handler, . - DebugMon_Handler - - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - B . - .size PendSV_Handler, . - PendSV_Handler - - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - B . - .size SysTick_Handler, . - SysTick_Handler - - -/* IRQ Handlers */ - - .globl Default_Handler - .type Default_Handler, %function -Default_Handler: - B . - .size Default_Handler, . - Default_Handler - - .macro IRQ handler - .weak \handler - .set \handler, Default_Handler - .endm - - IRQ WDT_IRQHandler - IRQ TIMER0_IRQHandler - IRQ TIMER1_IRQHandler - IRQ TIMER2_IRQHandler - IRQ TIMER3_IRQHandler - IRQ UART0_IRQHandler - IRQ UART1_IRQHandler - IRQ UART2_IRQHandler - IRQ UART3_IRQHandler - IRQ PWM1_IRQHandler - IRQ I2C0_IRQHandler - IRQ I2C1_IRQHandler - IRQ I2C2_IRQHandler -/* IRQ SPIFI_IRQHandler */ - IRQ SSP0_IRQHandler - IRQ SSP1_IRQHandler - IRQ PLL0_IRQHandler - IRQ RTC_IRQHandler - IRQ EINT0_IRQHandler - IRQ EINT1_IRQHandler - IRQ EINT2_IRQHandler - IRQ EINT3_IRQHandler - IRQ ADC_IRQHandler - IRQ BOD_IRQHandler - IRQ USB_IRQHandler - IRQ CAN_IRQHandler - IRQ DMA_IRQHandler - IRQ I2S_IRQHandler - IRQ ENET_IRQHandler - IRQ MCI_IRQHandler - IRQ MCPWM_IRQHandler - IRQ QEI_IRQHandler - IRQ PLL1_IRQHandler - IRQ USBActivity_IRQHandler - IRQ CANActivity_IRQHandler - IRQ UART4_IRQHandler - IRQ SSP2_IRQHandler - IRQ LCD_IRQHandler - IRQ GPIO_IRQHandler - IRQ PWM0_IRQHandler - IRQ EEPROM_IRQHandler - - .end diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/GCC/startup_LPC407x_8x_177x_8x.s b/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/GCC/startup_LPC407x_8x_177x_8x.s deleted file mode 100644 index 7278ca26fad..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/GCC/startup_LPC407x_8x_177x_8x.s +++ /dev/null @@ -1,281 +0,0 @@ -/*****************************************************************************/ -/* startup_LPC17xx.s: Startup file for LPC17xx device series */ -/*****************************************************************************/ -/* Version: CodeSourcery Sourcery G++ Lite (with CS3) */ -/*****************************************************************************/ - - -/* -//*** <<< Use Configuration Wizard in Context Menu >>> *** -*/ - - -/* -// Stack Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - - .equ Stack_Size, 0x00000100 - .section ".stack", "w" - .align 3 - .globl __cs3_stack_mem - .globl __cs3_stack_size -__cs3_stack_mem: - .if Stack_Size - .space Stack_Size - .endif - .size __cs3_stack_mem, . - __cs3_stack_mem - .set __cs3_stack_size, . - __cs3_stack_mem - - -/* -// Heap Configuration -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - - .equ Heap_Size, 0x00001000 - - .section ".heap", "w" - .align 3 - .globl __cs3_heap_start - .globl __cs3_heap_end -__cs3_heap_start: - .if Heap_Size - .space Heap_Size - .endif -__cs3_heap_end: - - -/* Vector Table */ - - .section ".cs3.interrupt_vector" - .globl __cs3_interrupt_vector_cortex_m - .type __cs3_interrupt_vector_cortex_m, %object - -__cs3_interrupt_vector_cortex_m: - .long __cs3_stack /* Top of Stack */ - .long __cs3_reset /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External Interrupts */ - .long WDT_IRQHandler /* 16: Watchdog Timer */ - .long TIMER0_IRQHandler /* 17: Timer0 */ - .long TIMER1_IRQHandler /* 18: Timer1 */ - .long TIMER2_IRQHandler /* 19: Timer2 */ - .long TIMER3_IRQHandler /* 20: Timer3 */ - .long UART0_IRQHandler /* 21: UART0 */ - .long UART1_IRQHandler /* 22: UART1 */ - .long UART2_IRQHandler /* 23: UART2 */ - .long UART3_IRQHandler /* 24: UART3 */ - .long PWM1_IRQHandler /* 25: PWM1 */ - .long I2C0_IRQHandler /* 26: I2C0 */ - .long I2C1_IRQHandler /* 27: I2C1 */ - .long I2C2_IRQHandler /* 28: I2C2 */ - .long 0 /* 29: Reserved, not for SPIFI anymore */ - .long SSP0_IRQHandler /* 30: SSP0 */ - .long SSP1_IRQHandler /* 31: SSP1 */ - .long PLL0_IRQHandler /* 32: PLL0 Lock (Main PLL) */ - .long RTC_IRQHandler /* 33: Real Time Clock */ - .long EINT0_IRQHandler /* 34: External Interrupt 0 */ - .long EINT1_IRQHandler /* 35: External Interrupt 1 */ - .long EINT2_IRQHandler /* 36: External Interrupt 2 */ - .long EINT3_IRQHandler /* 37: External Interrupt 3 */ - .long ADC_IRQHandler /* 38: A/D Converter */ - .long BOD_IRQHandler /* 39: Brown-Out Detect */ - .long USB_IRQHandler /* 40: USB */ - .long CAN_IRQHandler /* 41: CAN */ - .long DMA_IRQHandler /* 42: General Purpose DMA */ - .long I2S_IRQHandler /* 43: I2S */ - .long ENET_IRQHandler /* 44: Ethernet */ - .long MCI_IRQHandler /* 45: SD/MMC Card */ - .long MCPWM_IRQHandler /* 46: Motor Control PWM */ - .long QEI_IRQHandler /* 47: Quadrature Encoder Interface */ - .long PLL1_IRQHandler /* 48: PLL1 Lock (USB PLL) */ - .long USBActivity_IRQHandler /* 49: USB Activity */ - .long CANActivity_IRQHandler /* 50: CAN Activity */ - .long UART4_IRQHandler /* 51: UART4 */ - .long SSP2_IRQHandler /* 52: SSP2 */ - .long LCD_IRQHandler /* 53: LCD */ - .long GPIO_IRQHandler /* 54: GPIO */ - .long PWM0_IRQHandler /* 55: PWM0 */ - .long EEPROM_IRQHandler /* 56: EEPROM */ - - .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m - - - .thumb - - .section ".crp" - .globl CRP_Value -CRP_Value: - .long 0xFFFFFFFF - -/* Reset Handler */ - - .section .cs3.reset,"x",%progbits - .thumb_func - .globl __cs3_reset_cortex_m - .globl Reset_Handler - .type __cs3_reset_cortex_m, %function -__cs3_reset_cortex_m: -Reset_Handler: - .fnstart -.ifdef RAM_MODE -/* Clear .bss section (Zero init) */ - MOV R0, #0 - LDR R1, =__bss_start__ - LDR R2, =__bss_end__ - CMP R1,R2 - BEQ BSSIsEmpty -LoopZI: - CMP R1, R2 - BHS BSSIsEmpty - STR R0, [R1] - ADD R1, #4 - BLO LoopZI -BSSIsEmpty: - LDR R0, =SystemInit - BLX R0 - LDR R0,=main - BX R0 -.else - LDR R0, =SystemInit - BLX R0 - LDR R0,=main - BX R0 -.endif - .pool - .cantunwind - .fnend - .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m - - .section ".text" - -/* Exception Handlers */ - - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - B . - .size NMI_Handler, . - NMI_Handler - - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - B . - .size HardFault_Handler, . - HardFault_Handler - - .weak MemManage_Handler - .type MemManage_Handler, %function -MemManage_Handler: - B . - .size MemManage_Handler, . - MemManage_Handler - - .weak BusFault_Handler - .type BusFault_Handler, %function -BusFault_Handler: - B . - .size BusFault_Handler, . - BusFault_Handler - - .weak UsageFault_Handler - .type UsageFault_Handler, %function -UsageFault_Handler: - B . - .size UsageFault_Handler, . - UsageFault_Handler - - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - B . - .size SVC_Handler, . - SVC_Handler - - .weak DebugMon_Handler - .type DebugMon_Handler, %function -DebugMon_Handler: - B . - .size DebugMon_Handler, . - DebugMon_Handler - - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - B . - .size PendSV_Handler, . - PendSV_Handler - - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - B . - .size SysTick_Handler, . - SysTick_Handler - - -/* IRQ Handlers */ - - .globl Default_Handler - .type Default_Handler, %function -Default_Handler: - B . - .size Default_Handler, . - Default_Handler - - .macro IRQ handler - .weak \handler - .set \handler, Default_Handler - .endm - - IRQ WDT_IRQHandler - IRQ TIMER0_IRQHandler - IRQ TIMER1_IRQHandler - IRQ TIMER2_IRQHandler - IRQ TIMER3_IRQHandler - IRQ UART0_IRQHandler - IRQ UART1_IRQHandler - IRQ UART2_IRQHandler - IRQ UART3_IRQHandler - IRQ PWM1_IRQHandler - IRQ I2C0_IRQHandler - IRQ I2C1_IRQHandler - IRQ I2C2_IRQHandler -/* IRQ SPIFI_IRQHandler */ - IRQ SSP0_IRQHandler - IRQ SSP1_IRQHandler - IRQ PLL0_IRQHandler - IRQ RTC_IRQHandler - IRQ EINT0_IRQHandler - IRQ EINT1_IRQHandler - IRQ EINT2_IRQHandler - IRQ EINT3_IRQHandler - IRQ ADC_IRQHandler - IRQ BOD_IRQHandler - IRQ USB_IRQHandler - IRQ CAN_IRQHandler - IRQ DMA_IRQHandler - IRQ I2S_IRQHandler - IRQ ENET_IRQHandler - IRQ MCI_IRQHandler - IRQ MCPWM_IRQHandler - IRQ QEI_IRQHandler - IRQ PLL1_IRQHandler - IRQ USBActivity_IRQHandler - IRQ CANActivity_IRQHandler - IRQ UART4_IRQHandler - IRQ SSP2_IRQHandler - IRQ LCD_IRQHandler - IRQ GPIO_IRQHandler - IRQ PWM0_IRQHandler - IRQ EEPROM_IRQHandler - - .end diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/IAR/startup_LPC177x_8x.s b/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/IAR/startup_LPC177x_8x.s deleted file mode 100644 index 55f4be7484f..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/IAR/startup_LPC177x_8x.s +++ /dev/null @@ -1,396 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC177x_8x.s -; * @purpose: CMSIS Cortex-M3 Core Device Startup File -; * for the NXP LPC17xx Device Series -; * @version: V1.03 -; * @date: 09. February 2010 -; *---------------------------------------------------------------------------- -; * -; * Copyright (C) 2010 ARM Limited. All rights reserved. -; * -; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_IRQHandler ; 16: Watchdog Timer - DCD TIMER0_IRQHandler ; 17: Timer0 - DCD TIMER1_IRQHandler ; 18: Timer1 - DCD TIMER2_IRQHandler ; 19: Timer2 - DCD TIMER3_IRQHandler ; 20: Timer3 - DCD UART0_IRQHandler ; 21: UART0 - DCD UART1_IRQHandler ; 22: UART1 - DCD UART2_IRQHandler ; 23: UART2 - DCD UART3_IRQHandler ; 24: UART3 - DCD PWM1_IRQHandler ; 25: PWM1 - DCD I2C0_IRQHandler ; 26: I2C0 - DCD I2C1_IRQHandler ; 27: I2C1 - DCD I2C2_IRQHandler ; 28: I2C2 - DCD 0 ; 29: reserved; not for SPIFI anymore - DCD SSP0_IRQHandler ; 30: SSP0 - DCD SSP1_IRQHandler ; 31: SSP1 - DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL) - DCD RTC_IRQHandler ; 33: Real Time Clock - DCD EINT0_IRQHandler ; 34: External Interrupt 0 - DCD EINT1_IRQHandler ; 35: External Interrupt 1 - DCD EINT2_IRQHandler ; 36: External Interrupt 2 - DCD EINT3_IRQHandler ; 37: External Interrupt 3 - DCD ADC_IRQHandler ; 38: A/D Converter - DCD BOD_IRQHandler ; 39: Brown-Out Detect - DCD USB_IRQHandler ; 40: USB - DCD CAN_IRQHandler ; 41: CAN - DCD DMA_IRQHandler ; 42: General Purpose DMA - DCD I2S_IRQHandler ; 43: I2S - DCD ENET_IRQHandler ; 44: Ethernet - DCD MCI_IRQHandler ; 45: MCI Card - DCD MCPWM_IRQHandler ; 46: Motor Control PWM - DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface - DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) - DCD USBActivity_IRQHandler ; 49: USB Activity Interrupt - DCD CANActivity_IRQHandler ; 50: CAN Activity Interrupt - DCD UART4_IRQHandler ; 51: UART4 - DCD SSP2_IRQHandler ; 52: SSP2 - DCD LCD_IRQHandler ; 53: LCD - DCD GPIO_IRQHandler ; 54: GPIO - DCD PWM0_IRQHandler ; 55: PWM0 - DCD EEPROM_IRQHandler ; 56: EEPROM - - - - -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - PUBLIC CRP_Value - RSEG CRPKEY : CODE(2) -CRP_Value - DCD 0xFFFFFFFF -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WDT_IRQHandler - SECTION .text:CODE:REORDER(1) -WDT_IRQHandler - B WDT_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:REORDER(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:REORDER(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK UART0_IRQHandler - SECTION .text:CODE:REORDER(1) -UART0_IRQHandler - B UART0_IRQHandler - - PUBWEAK UART1_IRQHandler - SECTION .text:CODE:REORDER(1) -UART1_IRQHandler - B UART1_IRQHandler - - PUBWEAK UART2_IRQHandler - SECTION .text:CODE:REORDER(1) -UART2_IRQHandler - B UART2_IRQHandler - - PUBWEAK UART3_IRQHandler - SECTION .text:CODE:REORDER(1) -UART3_IRQHandler - B UART3_IRQHandler - - PUBWEAK PWM1_IRQHandler - SECTION .text:CODE:REORDER(1) -PWM1_IRQHandler - B PWM1_IRQHandler - - PUBWEAK I2C0_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C0_IRQHandler - B I2C0_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK I2C2_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C2_IRQHandler - B I2C2_IRQHandler - - ;PUBWEAK SPIFI_IRQHandler - ;SECTION .text:CODE:REORDER(1) -;SPIFI_IRQHandler - ;B SPIFI_IRQHandler - - PUBWEAK SSP0_IRQHandler - SECTION .text:CODE:REORDER(1) -SSP0_IRQHandler - B SSP0_IRQHandler - - PUBWEAK SSP1_IRQHandler - SECTION .text:CODE:REORDER(1) -SSP1_IRQHandler - B SSP1_IRQHandler - - PUBWEAK PLL0_IRQHandler - SECTION .text:CODE:REORDER(1) -PLL0_IRQHandler - B PLL0_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK EINT0_IRQHandler - SECTION .text:CODE:REORDER(1) -EINT0_IRQHandler - B EINT0_IRQHandler - - PUBWEAK EINT1_IRQHandler - SECTION .text:CODE:REORDER(1) -EINT1_IRQHandler - B EINT1_IRQHandler - - PUBWEAK EINT2_IRQHandler - SECTION .text:CODE:REORDER(1) -EINT2_IRQHandler - B EINT2_IRQHandler - - PUBWEAK EINT3_IRQHandler - SECTION .text:CODE:REORDER(1) -EINT3_IRQHandler - B EINT3_IRQHandler - - PUBWEAK ADC_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC_IRQHandler - B ADC_IRQHandler - - PUBWEAK BOD_IRQHandler - SECTION .text:CODE:REORDER(1) -BOD_IRQHandler - B BOD_IRQHandler - - PUBWEAK USB_IRQHandler - SECTION .text:CODE:REORDER(1) -USB_IRQHandler - B USB_IRQHandler - - PUBWEAK CAN_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN_IRQHandler - B CAN_IRQHandler - - PUBWEAK DMA_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA_IRQHandler - B DMA_IRQHandler - - PUBWEAK I2S_IRQHandler - SECTION .text:CODE:REORDER(1) -I2S_IRQHandler - B I2S_IRQHandler - - PUBWEAK ENET_IRQHandler - SECTION .text:CODE:REORDER(1) -ENET_IRQHandler - B ENET_IRQHandler - - PUBWEAK MCI_IRQHandler - SECTION .text:CODE:REORDER(1) -MCI_IRQHandler - B MCI_IRQHandler - - PUBWEAK MCPWM_IRQHandler - SECTION .text:CODE:REORDER(1) -MCPWM_IRQHandler - B MCPWM_IRQHandler - - PUBWEAK QEI_IRQHandler - SECTION .text:CODE:REORDER(1) -QEI_IRQHandler - B QEI_IRQHandler - - PUBWEAK PLL1_IRQHandler - SECTION .text:CODE:REORDER(1) -PLL1_IRQHandler - B PLL1_IRQHandler - - PUBWEAK USBActivity_IRQHandler - SECTION .text:CODE:REORDER(1) -USBActivity_IRQHandler - B USBActivity_IRQHandler - - PUBWEAK CANActivity_IRQHandler - SECTION .text:CODE:REORDER(1) -CANActivity_IRQHandler - B CANActivity_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:REORDER(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK SSP2_IRQHandler - SECTION .text:CODE:REORDER(1) -SSP2_IRQHandler - B SSP2_IRQHandler - - PUBWEAK LCD_IRQHandler - SECTION .text:CODE:REORDER(1) -LCD_IRQHandler - B LCD_IRQHandler - - PUBWEAK GPIO_IRQHandler - SECTION .text:CODE:REORDER(1) -GPIO_IRQHandler - B GPIO_IRQHandler - - PUBWEAK PWM0_IRQHandler - SECTION .text:CODE:REORDER(1) -PWM0_IRQHandler - B PWM0_IRQHandler - - PUBWEAK EEPROM_IRQHandler - SECTION .text:CODE:REORDER(1) -EEPROM_IRQHandler - B EEPROM_IRQHandler - - END diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/IAR/startup_LPC407x_8x_177x_8x.s b/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/IAR/startup_LPC407x_8x_177x_8x.s deleted file mode 100644 index 81a4008c859..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/IAR/startup_LPC407x_8x_177x_8x.s +++ /dev/null @@ -1,419 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC407x_8x.s -; * @purpose: CMSIS Cortex-M4 Core Device Startup File -; * for the NXP LPC40xx Device Series -; * @version: V1.00 -; * @date: September 2012 -; *---------------------------------------------------------------------------- -; * -; * Copyright (C) 2010 ARM Limited. All rights reserved. -; * -; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_IRQHandler ; 16: Watchdog Timer - DCD TIMER0_IRQHandler ; 17: Timer0 - DCD TIMER1_IRQHandler ; 18: Timer1 - DCD TIMER2_IRQHandler ; 19: Timer2 - DCD TIMER3_IRQHandler ; 20: Timer3 - DCD UART0_IRQHandler ; 21: UART0 - DCD UART1_IRQHandler ; 22: UART1 - DCD UART2_IRQHandler ; 23: UART2 - DCD UART3_IRQHandler ; 24: UART3 - DCD PWM1_IRQHandler ; 25: PWM1 - DCD I2C0_IRQHandler ; 26: I2C0 - DCD I2C1_IRQHandler ; 27: I2C1 - DCD I2C2_IRQHandler ; 28: I2C2 - DCD 0 ; 29: Reserved - DCD SSP0_IRQHandler ; 30: SSP0 - DCD SSP1_IRQHandler ; 31: SSP1 - DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL) - DCD RTC_IRQHandler ; 33: Real Time Clock - DCD EINT0_IRQHandler ; 34: External Interrupt 0 - DCD EINT1_IRQHandler ; 35: External Interrupt 1 - DCD EINT2_IRQHandler ; 36: External Interrupt 2 - DCD EINT3_IRQHandler ; 37: External Interrupt 3 - DCD ADC_IRQHandler ; 38: A/D Converter - DCD BOD_IRQHandler ; 39: Brown-Out Detect - DCD USB_IRQHandler ; 40: USB - DCD CAN_IRQHandler ; 41: CAN - DCD DMA_IRQHandler ; 42: General Purpose DMA - DCD I2S_IRQHandler ; 43: I2S - DCD ENET_IRQHandler ; 44: Ethernet - DCD MCI_IRQHandler ; 45: MCI Card - DCD MCPWM_IRQHandler ; 46: Motor Control PWM - DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface - DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) - DCD USBActivity_IRQHandler ; 49: USB Activity Interrupt - DCD CANActivity_IRQHandler ; 50: CAN Activity Interrupt - DCD UART4_IRQHandler ; 51: UART4 - DCD SSP2_IRQHandler ; 52: SSP2 - DCD LCD_IRQHandler ; 53: LCD - DCD GPIO_IRQHandler ; 54: GPIO - DCD PWM0_IRQHandler ; 55: PWM0 - DCD EEPROM_IRQHandler ; 56: EEPROM - - -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WDT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WDT_IRQHandler - B WDT_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK UART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_IRQHandler - B UART0_IRQHandler - - PUBWEAK UART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_IRQHandler - B UART1_IRQHandler - - PUBWEAK UART2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART2_IRQHandler - B UART2_IRQHandler - - PUBWEAK UART3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART3_IRQHandler - B UART3_IRQHandler - - PUBWEAK PWM1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM1_IRQHandler - B PWM1_IRQHandler - - PUBWEAK I2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_IRQHandler - B I2C0_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK I2C2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_IRQHandler - B I2C2_IRQHandler - -; PUBWEAK SPIFI_IRQHandler -; SECTION .text:CODE:REORDER:NOROOT(1) -;SPIFI_IRQHandler -; B SPIFI_IRQHandler - - PUBWEAK SSP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP0_IRQHandler - B SSP0_IRQHandler - - PUBWEAK SSP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP1_IRQHandler - B SSP1_IRQHandler - - PUBWEAK PLL0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PLL0_IRQHandler - B PLL0_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK EINT0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EINT0_IRQHandler - B EINT0_IRQHandler - - PUBWEAK EINT1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EINT1_IRQHandler - B EINT1_IRQHandler - - PUBWEAK EINT2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EINT2_IRQHandler - B EINT2_IRQHandler - - PUBWEAK EINT3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EINT3_IRQHandler - B EINT3_IRQHandler - - PUBWEAK ADC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_IRQHandler - B ADC_IRQHandler - - PUBWEAK BOD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -BOD_IRQHandler - B BOD_IRQHandler - - PUBWEAK USB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USB_IRQHandler - B USB_IRQHandler - - PUBWEAK CAN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN_IRQHandler - B CAN_IRQHandler - - PUBWEAK DMA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA_IRQHandler - B DMA_IRQHandler - - PUBWEAK I2S_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2S_IRQHandler - B I2S_IRQHandler - - PUBWEAK ENET_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ENET_IRQHandler - B ENET_IRQHandler - - PUBWEAK MCI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MCI_IRQHandler - B MCI_IRQHandler - - PUBWEAK MCPWM_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MCPWM_IRQHandler - B MCPWM_IRQHandler - - PUBWEAK QEI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -QEI_IRQHandler - B QEI_IRQHandler - - PUBWEAK PLL1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PLL1_IRQHandler - B PLL1_IRQHandler - - PUBWEAK USBActivity_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USBActivity_IRQHandler - B USBActivity_IRQHandler - - PUBWEAK CANActivity_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CANActivity_IRQHandler - B CANActivity_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK SSP2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP2_IRQHandler - B SSP2_IRQHandler - - PUBWEAK LCD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LCD_IRQHandler - B LCD_IRQHandler - - PUBWEAK GPIO_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_IRQHandler - B GPIO_IRQHandler - - PUBWEAK PWM0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM0_IRQHandler - B PWM0_IRQHandler - - PUBWEAK EEPROM_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EEPROM_IRQHandler - B EEPROM_IRQHandler - -#ifndef SRAM - SECTION .crp:CODE:ROOT(2) - DATA - -/* Code Read Protection -CRP1 0x12345678 - Write to RAM command can not access RAM below 0x10000200. - - Read Memory command: disabled. - - Copy RAM to Flash command: cannot write to Sector 0. - - "Go" command: disabled. - - Erase sector(s) command: can erase any individual sector except - sector 0 only, or can erase all sectors at once. - - Compare command: disabled -CRP2 0x87654321 - Write to RAM command: disabled. - - Copy RAM to Flash: disabled. - - Erase command: only allows erase of all sectors. -CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry - by pulling PIO0_1 LOW is disabled if a valid user code is - present in flash sector 0. -Caution: If CRP3 is selected, no future factory testing can be -performed on the device. -*/ - -#ifndef CRP - #define CRP 0xFFFFFFFF -#endif - - DCD CRP -#endif - END diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC177x_8x.c b/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC177x_8x.c deleted file mode 100644 index ee222aee7ed..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC177x_8x.c +++ /dev/null @@ -1,507 +0,0 @@ -/********************************************************************** -* $Id$ system_LPC177x_8x.c 2011-06-02 -*//** -* @file system_LPC177x_8x.c -* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File -* for the NXP LPC177x_8x Device Series -* -* ARM Limited (ARM) is supplying this software for use with -* Cortex-M processor based microcontrollers. This file can be -* freely distributed within development tools that are supporting -* such ARM based processors. -* -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -#include -#include "LPC177x_8x.h" -#include "system_LPC177x_8x.h" - -#define __CLK_DIV(x,y) (((y) == 0) ? 0: (x)/(y)) - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ -/*--------------------- Clock Configuration ---------------------------------- -// -// Clock Configuration -// System Controls and Status Register (SCS - address 0x400F C1A0) -// EMC Shift Control Bit -// Controls how addresses are output on the EMC address pins for static memories -// <0=> Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit (Bit 0 is 0) -// <1=> Static CS addresses start at LSB 0 regardless of memory width (Bit 0 is 1) -// -// EMC Reset Disable Bit -// If 0 (zero), all registers and functions of the EMC are initialized upon any reset condition -// If 1, EMC is still retained its state through a warm reset -// <0=> Both EMC resets are asserted when any type of chip reset event occurs (Bit 1 is 0) -// <1=> Portions of EMC will only be reset by POR or BOR event (Bit 1 is 1) -// -// EMC Burst Control -// Set to 1 to prevent multiple sequential accesses to memory via EMC static memory chip selects -// <0=> Burst enabled (Bit 2 is 0) -// <1=> Bust disbled (Bit 2 is 1) -// -// MCIPWR Active Level -// Selects the active level for the SD card interface signal SD_PWR -// <0=> SD_PWR is active low (inverted output of the SD Card interface block) (Bit 3 is 0) -// <1=> SD_PWR is active high (follows the output of the SD Card interface block) (Bit 3 is 1) -// -// Main Oscillator Range Select -// <0=> In Range 1 MHz to 20 MHz (Bit 4 is 0) -// <1=> In Range 15 MHz to 25 MHz (Bit 4 is 1) -// -// Main Oscillator enable -// 0 (zero) means disabled, 1 means enable -// -// Main Oscillator status (Read-Only) -// -// -// Clock Source Select Register (CLKSRCSEL - address 0x400F C10C) -// CLKSRC: Select the clock source for sysclk to PLL0 clock -// <0=> Internal RC oscillator (Bit 0 is 0) -// <1=> Main oscillator (Bit 0 is 1) -// -// -// PLL0 Configuration (Main PLL PLL0CFG - address 0x400F C084) -// F_in is in the range of 1 MHz to 25 MHz -// F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz -// PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz -// -// MSEL: PLL Multiplier Value -// M Value -// <1-32><#-1> -// -// PSEL: PLL Divider Value -// P Value -// <0=> 1 -// <1=> 2 -// <2=> 4 -// <3=> 8 -// -// -// PLL1 Configuration (Alt PLL PLL1CFG - address 0x400F C0A4) -// F_in is in the range of 1 MHz to 25 MHz -// F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz -// PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz -// -// MSEL: PLL Multiplier Value -// M Value -// <1-32><#-1> -// -// PSEL: PLL Divider Value -// P Value -// <0=> 1 -// <1=> 2 -// <2=> 4 -// <3=> 8 -// -// -// CPU Clock Selection Register (CCLKSEL - address 0x400F C104) -// CCLKDIV: Select the value for divider of CPU clock (CCLK) -// 0: The divider is turned off. No clock will be provided to the CPU -// n: The input clock is divided by n to produce the CPU clock -// <0-31> -// -// CCLKSEL: Select the input to the divider of CPU clock -// <0=> sysclk clock is used -// <1=> Main PLL0 clock is used -// -// -// USB Clock Selection Register (USBCLKSEL - 0x400F C108) -// USBDIV: USB clock (source PLL0) divider selection -// <0=> Divider is off and no clock provides to USB subsystem -// <4=> Divider value is 4 (The source clock is divided by 4) -// <6=> Divider value is 6 (The source clock is divided by 6) -// -// USBSEL: Select the source for USB clock divider -// When CPU clock is selected, the USB can be accessed -// by software but cannot perform USB functions -// <0=> sysclk clock (the clock input to PLL0) -// <1=> The clock output from PLL0 -// <2=> The clock output from PLL1 -// -// -// EMC Clock Selection Register (EMCCLKSEL - address 0x400F C100) -// EMCDIV: Set the divider for EMC clock -// <0=> Divider value is 1 -// <1=> Divider value is 2 (EMC clock is equal a half of input clock) -// -// -// Peripheral Clock Selection Register (PCLKSEL - address 0x400F C1A8) -// PCLKDIV: APB Peripheral clock divider -// 0: The divider is turned off. No clock will be provided to APB peripherals -// n: The input clock is divided by n to produce the APB peripheral clock -// <0-31> -// -// -// Power Control for Peripherals Register (PCONP - address 0x400F C1C8) -// PCLCD: LCD controller power/clock enable (bit 0) -// PCTIM0: Timer/Counter 0 power/clock enable (bit 1) -// PCTIM1: Timer/Counter 1 power/clock enable (bit 2) -// PCUART0: UART 0 power/clock enable (bit 3) -// PCUART1: UART 1 power/clock enable (bit 4) -// PCPWM0: PWM0 power/clock enable (bit 5) -// PCPWM1: PWM1 power/clock enable (bit 6) -// PCI2C0: I2C 0 interface power/clock enable (bit 7) -// PCUART4: UART 4 power/clock enable (bit 8) -// PCRTC: RTC and Event Recorder power/clock enable (bit 9) -// PCSSP1: SSP 1 interface power/clock enable (bit 10) -// PCEMC: External Memory Controller power/clock enable (bit 11) -// PCADC: A/D converter power/clock enable (bit 12) -// PCCAN1: CAN controller 1 power/clock enable (bit 13) -// PCCAN2: CAN controller 2 power/clock enable (bit 14) -// PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable (bit 15) -// PCMCPWM: Motor Control PWM power/clock enable (bit 17) -// PCQEI: Quadrature encoder interface power/clock enable (bit 18) -// PCI2C1: I2C 1 interface power/clock enable (bit 19) -// PCSSP2: SSP 2 interface power/clock enable (bit 20) -// PCSSP0: SSP 0 interface power/clock enable (bit 21) -// PCTIM2: Timer 2 power/clock enable (bit 22) -// PCTIM3: Timer 3 power/clock enable (bit 23) -// PCUART2: UART 2 power/clock enable (bit 24) -// PCUART3: UART 3 power/clock enable (bit 25) -// PCI2C2: I2C 2 interface power/clock enable (bit 26) -// PCI2S: I2S interface power/clock enable (bit 27) -// PCSDC: SD Card interface power/clock enable (bit 28) -// PCGPDMA: GPDMA function power/clock enable (bit 29) -// PCENET: Ethernet block power/clock enable (bit 30) -// PCUSB: USB interface power/clock enable (bit 31) -// -// -// Clock Output Configuration Register (CLKOUTCFG) -// CLKOUTSEL: Clock Source for CLKOUT Selection -// <0=> CPU clock -// <1=> Main Oscillator -// <2=> Internal RC Oscillator -// <3=> USB clock -// <4=> RTC Oscillator -// <5=> unused -// <6=> Watchdog Oscillator -// -// CLKOUTDIV: Output Clock Divider -// <1-16><#-1> -// -// CLKOUT_EN: CLKOUT enable -// -// -// -*/ - -#define CLOCK_SETUP 1 -#define SCS_Val 0x00000021 -#define CLKSRCSEL_Val 0x00000001 -#define PLL0_SETUP 1 -#define PLL0CFG_Val 0x00000009 -#define PLL1_SETUP 1 -#define PLL1CFG_Val 0x00000023 -#define CCLKSEL_Val 0x00000101 -#define USBCLKSEL_Val 0x00000201 -#define EMCCLKSEL_Val 0x00000001 -#define PCLKSEL_Val 0x00000002 -#define PCONP_Val 0x042887DE -#define CLKOUTCFG_Val 0x00000100 - - -/*--------------------- Flash Accelerator Configuration ---------------------- -// -// Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000) -// FLASHTIM: Flash Access Time -// <0=> 1 CPU clock (for CPU clock up to 20 MHz) -// <1=> 2 CPU clocks (for CPU clock up to 40 MHz) -// <2=> 3 CPU clocks (for CPU clock up to 60 MHz) -// <3=> 4 CPU clocks (for CPU clock up to 80 MHz) -// <4=> 5 CPU clocks (for CPU clock up to 100 MHz) -// <5=> 6 CPU clocks (for any CPU clock) -// -*/ - -#define FLASH_SETUP 1 -#define FLASHCFG_Val 0x00005000 - -/*---------------------------------------------------------------------------- - Check the register settings - *----------------------------------------------------------------------------*/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) -#define CHECK_RSVD(val, mask) (val & mask) - -/* Clock Configuration -------------------------------------------------------*/ -#if (CHECK_RSVD((SCS_Val), ~0x0000003F)) - #error "SCS: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1)) - #error "CLKSRCSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((PLL0CFG_Val), ~0x0000007F)) - #error "PLL0CFG: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) - #error "PLL1CFG: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((CCLKSEL_Val), ~0x0000011F)) - #error "CCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F)) - #error "USBCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001)) - #error "EMCCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F)) - #error "PCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF)) - #error "PCONP: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) - #error "CLKOUTCFG: Invalid values of reserved bits!" -#endif - -/* Flash Accelerator Configuration -------------------------------------------*/ -#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000)) - #warning "FLASHCFG: Invalid values of reserved bits!" -#endif - - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ -/* pll_out_clk = F_cco / (2 × P) - F_cco = pll_in_clk × M × 2 × P */ -#define __M ((PLL0CFG_Val & 0x1F) + 1) -#define __PLL0_CLK(__F_IN) (__F_IN * __M) -#define __CCLK_DIV (CCLKSEL_Val & 0x1F) -#define __PCLK_DIV (PCLKSEL_Val & 0x1F) -#define __ECLK_DIV ((EMCCLKSEL_Val & 0x01) + 1) - -/* Determine core clock frequency according to settings */ -#if (CLOCK_SETUP) /* Clock Setup */ - - #if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0) - #error "Main Oscillator is selected as clock source but is not enabled!" - #endif - - #if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0) - #error "Main PLL is selected as clock source but is not enabled!" - #endif - - #if ((CCLKSEL_Val & 0x100) == 0) /* cclk = sysclk */ - #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */ - #define __CORE_CLK (IRC_OSC / __CCLK_DIV) - #define __PER_CLK (IRC_OSC/ __PCLK_DIV) - #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV) - #else /* sysclk = osc_clk */ - #define __CORE_CLK (OSC_CLK / __CCLK_DIV) - #define __PER_CLK (OSC_CLK/ __PCLK_DIV) - #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV) - #endif - #else /* cclk = pll_clk */ - #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */ - #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV) - #define __PER_CLK (__PLL0_CLK(IRC_OSC) / __PCLK_DIV) - #define __EMC_CLK (__CORE_CLK / __ECLK_DIV) - #else /* sysclk = osc_clk */ - #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV) - #define __PER_CLK (__PLL0_CLK(OSC_CLK) / __PCLK_DIV) - #define __EMC_CLK (__CORE_CLK / __ECLK_DIV) - #endif - #endif - -#else - #define __CORE_CLK (IRC_OSC) - #define __PER_CLK (IRC_OSC) - #define __EMC_CLK (__CORE_CLK) -#endif - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ -uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk) */ -uint32_t EMCClock = __EMC_CLK; /*!< EMC Clock Frequency */ -uint32_t USBClock = (48000000UL); /*!< USB Clock Frequency - this value will - be updated after call SystemCoreClockUpdate, should be 48MHz*/ - - -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ - /* Determine clock frequency according to clock register values */ - if ((LPC_SC->CCLKSEL &0x100) == 0) { /* cclk = sysclk */ - if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */ - SystemCoreClock = __CLK_DIV(IRC_OSC , (LPC_SC->CCLKSEL & 0x1F)); - PeripheralClock = __CLK_DIV(IRC_OSC , (LPC_SC->PCLKSEL & 0x1F)); - EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1)); - } - else { /* sysclk = osc_clk */ - if ((LPC_SC->SCS & 0x40) == 0) { - SystemCoreClock = 0; /* this should never happen! */ - PeripheralClock = 0; - EMCClock = 0; - } - else { - SystemCoreClock = __CLK_DIV(OSC_CLK , (LPC_SC->CCLKSEL & 0x1F)); - PeripheralClock = __CLK_DIV(OSC_CLK , (LPC_SC->PCLKSEL & 0x1F)); - EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1)); - } - } - } - else { /* cclk = pll_clk */ - if ((LPC_SC->PLL0STAT & 0x100) == 0) { /* PLL0 not enabled */ - SystemCoreClock = 0; /* this should never happen! */ - PeripheralClock = 0; - EMCClock = 0; - } - else { - if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */ - uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1); - uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F); - uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F); - uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1; - SystemCoreClock = __CLK_DIV(IRC_OSC * mul , cpu_div); - PeripheralClock = __CLK_DIV(IRC_OSC * mul , per_div); - EMCClock = SystemCoreClock / emc_div; - } - else { /* sysclk = osc_clk */ - if ((LPC_SC->SCS & 0x40) == 0) { - SystemCoreClock = 0; /* this should never happen! */ - PeripheralClock = 0; - EMCClock = 0; - } - else { - uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1); - uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F); - uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F); - uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1; - SystemCoreClock = __CLK_DIV(OSC_CLK * mul , cpu_div); - PeripheralClock = __CLK_DIV(OSC_CLK * mul , per_div); - EMCClock = SystemCoreClock / emc_div; - } - } - } - } - /* ---update USBClock------------------*/ - if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider - { - switch (LPC_SC->USBCLKSEL & 0x1F) - { - case 0: - USBClock = 0; //no clock will be provided to the USB subsystem - break; - case 4: - case 6: - { - uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1); - uint8_t usb_div = (LPC_SC->USBCLKSEL & 0x1F); - if(LPC_SC->CLKSRCSEL & 0x01) //pll_clk_in = main_osc - USBClock = OSC_CLK * mul / usb_div; - else //pll_clk_in = irc_clk - USBClock = IRC_OSC * mul / usb_div; - } - break; - default: - USBClock = 0; /* this should never happen! */ - } - } - else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1) - { - if(LPC_SC->CLKSRCSEL & 0x01) //pll1_clk_in = main_osc - USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1)); - else //pll1_clk_in = irc_clk - USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1)); - } - else - USBClock = 0; /* this should never happen! */ -} - - /* Determine clock frequency according to clock register values */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) -{ -#if (CLOCK_SETUP) /* Clock Setup */ - LPC_SC->SCS = SCS_Val; - if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ - while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ - } - - LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for sysclk/PLL0*/ - -#if (PLL0_SETUP) - LPC_SC->PLL0CFG = PLL0CFG_Val; - LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0 */ -#endif - -#if (PLL1_SETUP) - LPC_SC->PLL1CFG = PLL1CFG_Val; - LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ -#endif - - LPC_SC->CCLKSEL = CCLKSEL_Val; /* Setup Clock Divider */ - LPC_SC->USBCLKSEL = USBCLKSEL_Val; /* Setup USB Clock Divider */ - LPC_SC->EMCCLKSEL = EMCCLKSEL_Val; /* EMC Clock Selection */ - LPC_SC->PCLKSEL = PCLKSEL_Val; /* Peripheral Clock Selection */ - LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ - LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ -#endif - - LPC_SC->PBOOST |= 0x03; /* Power Boost control */ - -#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ - LPC_SC->FLASHCFG = FLASHCFG_Val|0x03A; -#endif -#ifdef __RAM_MODE__ - SCB->VTOR = 0x10000000 & 0x3FFFFF80; -#else - SCB->VTOR = 0x00000000 & 0x3FFFFF80; -#endif - SystemCoreClockUpdate(); -} diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC407x_8x_177x_8x.c b/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC407x_8x_177x_8x.c deleted file mode 100644 index b716d06f629..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC407x_8x_177x_8x.c +++ /dev/null @@ -1,571 +0,0 @@ -/********************************************************************** -* $Id$ system_LPC407x_8x_177x_8x.c 2012-01-16 -*//** -* @file system_LPC407x_8x_177x_8x.c -* @brief CMSIS Cortex-M3, M4 Device Peripheral Access Layer Source File -* for the NXP LPC407x_8x_177x_8x Device Series -* -* ARM Limited (ARM) is supplying this software for use with -* Cortex-M processor based microcontrollers. This file can be -* freely distributed within development tools that are supporting -* such ARM based processors. -* -* @version 1.2 -* @date 20. June. 2012 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2012, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -#include -#include "LPC407x_8x_177x_8x.h" -#include "system_LPC407x_8x_177x_8x.h" - -#define __CLK_DIV(x,y) (((y) == 0) ? 0: (x)/(y)) - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ -/*--------------------- Clock Configuration ---------------------------------- -// -// Clock Configuration -// System Controls and Status Register (SCS - address 0x400F C1A0) -// EMC Shift Control Bit -// Controls how addresses are output on the EMC address pins for static memories -// <0=> Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit (Bit 0 is 0) -// <1=> Static CS addresses start at LSB 0 regardless of memory width (Bit 0 is 1) -// -// EMC Reset Disable Bit -// If 0 (zero), all registers and functions of the EMC are initialized upon any reset condition -// If 1, EMC is still retained its state through a warm reset -// <0=> Both EMC resets are asserted when any type of chip reset event occurs (Bit 1 is 0) -// <1=> Portions of EMC will only be reset by POR or BOR event (Bit 1 is 1) -// -// EMC Burst Control -// Set to 1 to prevent multiple sequential accesses to memory via EMC static memory chip selects -// <0=> Burst enabled (Bit 2 is 0) -// <1=> Bust disbled (Bit 2 is 1) -// -// MCIPWR Active Level -// Selects the active level for the SD card interface signal SD_PWR -// <0=> SD_PWR is active low (inverted output of the SD Card interface block) (Bit 3 is 0) -// <1=> SD_PWR is active high (follows the output of the SD Card interface block) (Bit 3 is 1) -// -// Main Oscillator Range Select -// <0=> In Range 1 MHz to 20 MHz (Bit 4 is 0) -// <1=> In Range 15 MHz to 25 MHz (Bit 4 is 1) -// -// Main Oscillator enable -// 0 (zero) means disabled, 1 means enable -// -// Main Oscillator status (Read-Only) -// -// -// Clock Source Select Register (CLKSRCSEL - address 0x400F C10C) -// CLKSRC: Select the clock source for sysclk to PLL0 clock -// <0=> Internal RC oscillator (Bit 0 is 0) -// <1=> Main oscillator (Bit 0 is 1) -// -// -// PLL0 Configuration (Main PLL PLL0CFG - address 0x400F C084) -// F_in is in the range of 1 MHz to 25 MHz -// F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz -// PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz -// -// MSEL: PLL Multiplier Value -// M Value -// <1-32><#-1> -// -// PSEL: PLL Divider Value -// P Value -// <0=> 1 -// <1=> 2 -// <2=> 4 -// <3=> 8 -// -// -// PLL1 Configuration (Alt PLL PLL1CFG - address 0x400F C0A4) -// F_in is in the range of 1 MHz to 25 MHz -// F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz -// PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz -// -// MSEL: PLL Multiplier Value -// M Value -// <1-32><#-1> -// -// PSEL: PLL Divider Value -// P Value -// <0=> 1 -// <1=> 2 -// <2=> 4 -// <3=> 8 -// -// -// CPU Clock Selection Register (CCLKSEL - address 0x400F C104) -// CCLKDIV: Select the value for divider of CPU clock (CCLK) -// 0: The divider is turned off. No clock will be provided to the CPU -// n: The input clock is divided by n to produce the CPU clock -// <0-31> -// -// CCLKSEL: Select the input to the divider of CPU clock -// <0=> sysclk clock is used -// <1=> Main PLL0 clock is used -// -// -// USB Clock Selection Register (USBCLKSEL - 0x400F C108) -// USBDIV: USB clock (source PLL0) divider selection -// <0=> Divider is off and no clock provides to USB subsystem -// <4=> Divider value is 4 (The source clock is divided by 4) -// <6=> Divider value is 6 (The source clock is divided by 6) -// -// USBSEL: Select the source for USB clock divider -// When CPU clock is selected, the USB can be accessed -// by software but cannot perform USB functions -// <0=> sysclk clock (the clock input to PLL0) -// <1=> The clock output from PLL0 -// <2=> The clock output from PLL1 -// -// -// EMC Clock Selection Register (EMCCLKSEL - address 0x400F C100) -// EMCDIV: Set the divider for EMC clock -// <0=> Divider value is 1 -// <1=> Divider value is 2 (EMC clock is equal a half of input clock) -// -// -// Peripheral Clock Selection Register (PCLKSEL - address 0x400F C1A8) -// PCLKDIV: APB Peripheral clock divider -// 0: The divider is turned off. No clock will be provided to APB peripherals -// n: The input clock is divided by n to produce the APB peripheral clock -// <0-31> -// -// -// SPIFI Clock Selection Register (SPIFICLKSEL - address 0x400F C1B4) -// SPIFIDIV: Set the divider for SPIFI clock -// 0: The divider is turned off. No clock will be provided to the SPIFI -// n: The input clock is divided by n to produce the SPIFI clock -// <0-31> -// -// SPIFISEL: Select the input clock for SPIFI clock divider -// <0=> sysclk clock (the clock input to PLL0) -// <1=> The clock output from PLL0 -// <2=> The clock output from PLL1 -// -// -// Power Control for Peripherals Register (PCONP - address 0x400F C1C8) -// PCLCD: LCD controller power/clock enable (bit 0) -// PCTIM0: Timer/Counter 0 power/clock enable (bit 1) -// PCTIM1: Timer/Counter 1 power/clock enable (bit 2) -// PCUART0: UART 0 power/clock enable (bit 3) -// PCUART1: UART 1 power/clock enable (bit 4) -// PCPWM0: PWM0 power/clock enable (bit 5) -// PCPWM1: PWM1 power/clock enable (bit 6) -// PCI2C0: I2C 0 interface power/clock enable (bit 7) -// PCUART4: UART 4 power/clock enable (bit 8) -// PCRTC: RTC and Event Recorder power/clock enable (bit 9) -// PCSSP1: SSP 1 interface power/clock enable (bit 10) -// PCEMC: External Memory Controller power/clock enable (bit 11) -// PCADC: A/D converter power/clock enable (bit 12) -// PCCAN1: CAN controller 1 power/clock enable (bit 13) -// PCCAN2: CAN controller 2 power/clock enable (bit 14) -// PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable (bit 15) -// PCMCPWM: Motor Control PWM power/clock enable (bit 17) -// PCQEI: Quadrature encoder interface power/clock enable (bit 18) -// PCI2C1: I2C 1 interface power/clock enable (bit 19) -// PCSSP2: SSP 2 interface power/clock enable (bit 20) -// PCSSP0: SSP 0 interface power/clock enable (bit 21) -// PCTIM2: Timer 2 power/clock enable (bit 22) -// PCTIM3: Timer 3 power/clock enable (bit 23) -// PCUART2: UART 2 power/clock enable (bit 24) -// PCUART3: UART 3 power/clock enable (bit 25) -// PCI2C2: I2C 2 interface power/clock enable (bit 26) -// PCI2S: I2S interface power/clock enable (bit 27) -// PCSDC: SD Card interface power/clock enable (bit 28) -// PCGPDMA: GPDMA function power/clock enable (bit 29) -// PCENET: Ethernet block power/clock enable (bit 30) -// PCUSB: USB interface power/clock enable (bit 31) -// -// -// Clock Output Configuration Register (CLKOUTCFG) -// CLKOUTSEL: Clock Source for CLKOUT Selection -// <0=> CPU clock -// <1=> Main Oscillator -// <2=> Internal RC Oscillator -// <3=> USB clock -// <4=> RTC Oscillator -// <5=> unused -// <6=> Watchdog Oscillator -// -// CLKOUTDIV: Output Clock Divider -// <1-16><#-1> -// -// CLKOUT_EN: CLKOUT enable -// -// -// -*/ - -#define CLOCK_SETUP 1 -#define SCS_Val 0x00000020 -#define CLKSRCSEL_Val 0x00000001 -#define PLL0_SETUP 1 -#define PLL0CFG_Val 0x00000009 -#define PLL1_SETUP 1 -#define PLL1CFG_Val 0x00000023 -#define CCLKSEL_Val 0x00000101 -#define USBCLKSEL_Val 0x00000201 -#define EMCCLKSEL_Val 0x00000000 -#define PCLKSEL_Val 0x00000002 -#define SPIFICLKSEL_Val 0x00000002 -#define PCONP_Val 0x042887DE -#define CLKOUTCFG_Val 0x00000100 - -#ifdef CORE_M4 -#define LPC_CPACR 0xE000ED88 - -#define SCB_MVFR0 0xE000EF40 -#define SCB_MVFR0_RESET 0x10110021 - -#define SCB_MVFR1 0xE000EF44 -#define SCB_MVFR1_RESET 0x11000011 -#endif - - -/*--------------------- Flash Accelerator Configuration ---------------------- -// -// Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000) -// FLASHTIM: Flash Access Time -// <0=> 1 CPU clock (for CPU clock up to 20 MHz) -// <1=> 2 CPU clocks (for CPU clock up to 40 MHz) -// <2=> 3 CPU clocks (for CPU clock up to 60 MHz) -// <3=> 4 CPU clocks (for CPU clock up to 80 MHz) -// <4=> 5 CPU clocks (for CPU clock up to 100 MHz) -// <5=> 6 CPU clocks (for any CPU clock) -// -*/ - -#define FLASH_SETUP 1 -#define FLASHCFG_Val 0x00005000 - -/*---------------------------------------------------------------------------- - Check the register settings - *----------------------------------------------------------------------------*/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) -#define CHECK_RSVD(val, mask) (val & mask) - -/* Clock Configuration -------------------------------------------------------*/ -#if (CHECK_RSVD((SCS_Val), ~0x0000003F)) - #error "SCS: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1)) - #error "CLKSRCSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((PLL0CFG_Val), ~0x0000007F)) - #error "PLL0CFG: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) - #error "PLL1CFG: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((CCLKSEL_Val), ~0x0000011F)) - #error "CCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F)) - #error "USBCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001)) - #error "EMCCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F)) - #error "PCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF)) - #error "PCONP: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) - #error "CLKOUTCFG: Invalid values of reserved bits!" -#endif - -/* Flash Accelerator Configuration -------------------------------------------*/ -#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000)) - #error "FLASHCFG: Invalid values of reserved bits!" -#endif - - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ -/* pll_out_clk = F_cco / (2 ?P) - F_cco = pll_in_clk ?M ?2 ?P */ -#define __M ((PLL0CFG_Val & 0x1F) + 1) -#define __PLL0_CLK(__F_IN) (__F_IN * __M) -#define __CCLK_DIV (CCLKSEL_Val & 0x1F) -#define __PCLK_DIV (PCLKSEL_Val & 0x1F) -#define __ECLK_DIV ((EMCCLKSEL_Val & 0x01) + 1) - -/* Determine core clock frequency according to settings */ -#if (CLOCK_SETUP) /* Clock Setup */ - - #if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0) - #error "Main Oscillator is selected as clock source but is not enabled!" - #endif - - #if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0) - #error "Main PLL is selected as clock source but is not enabled!" - #endif - - #if ((CCLKSEL_Val & 0x100) == 0) /* cclk = sysclk */ - #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */ - #define __CORE_CLK (IRC_OSC / __CCLK_DIV) - #define __PER_CLK (IRC_OSC/ __PCLK_DIV) - #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV) - #else /* sysclk = osc_clk */ - #define __CORE_CLK (OSC_CLK / __CCLK_DIV) - #define __PER_CLK (OSC_CLK/ __PCLK_DIV) - #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV) - #endif - #else /* cclk = pll_clk */ - #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */ - #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV) - #define __PER_CLK (__PLL0_CLK(IRC_OSC) / __PCLK_DIV) - #define __EMC_CLK (__CORE_CLK / __ECLK_DIV) - #else /* sysclk = osc_clk */ - #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV) - #define __PER_CLK (__PLL0_CLK(OSC_CLK) / __PCLK_DIV) - #define __EMC_CLK (__CORE_CLK / __ECLK_DIV) - #endif - #endif - -#else - #define __CORE_CLK (IRC_OSC) - #define __PER_CLK (IRC_OSC) - #define __EMC_CLK (__CORE_CLK) -#endif - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ -uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk) */ -uint32_t EMCClock = __EMC_CLK; /*!< EMC Clock Frequency */ -uint32_t USBClock = (48000000UL); /*!< USB Clock Frequency - this value will - be updated after call SystemCoreClockUpdate, should be 48MHz*/ - - -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ - /* Determine clock frequency according to clock register values */ - if ((LPC_SC->CCLKSEL &0x100) == 0) { /* cclk = sysclk */ - if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */ - SystemCoreClock = __CLK_DIV(IRC_OSC , (LPC_SC->CCLKSEL & 0x1F)); - PeripheralClock = __CLK_DIV(IRC_OSC , (LPC_SC->PCLKSEL & 0x1F)); - EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1)); - } - else { /* sysclk = osc_clk */ - if ((LPC_SC->SCS & 0x40) == 0) { - SystemCoreClock = 0; /* this should never happen! */ - PeripheralClock = 0; - EMCClock = 0; - } - else { - SystemCoreClock = __CLK_DIV(OSC_CLK , (LPC_SC->CCLKSEL & 0x1F)); - PeripheralClock = __CLK_DIV(OSC_CLK , (LPC_SC->PCLKSEL & 0x1F)); - EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1)); - } - } - } - else { /* cclk = pll_clk */ - if ((LPC_SC->PLL0STAT & 0x100) == 0) { /* PLL0 not enabled */ - SystemCoreClock = 0; /* this should never happen! */ - PeripheralClock = 0; - EMCClock = 0; - } - else { - if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */ - uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1); - uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F); - uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F); - uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1; - SystemCoreClock = __CLK_DIV(IRC_OSC * mul , cpu_div); - PeripheralClock = __CLK_DIV(IRC_OSC * mul , per_div); - EMCClock = SystemCoreClock / emc_div; - } - else { /* sysclk = osc_clk */ - if ((LPC_SC->SCS & 0x40) == 0) { - SystemCoreClock = 0; /* this should never happen! */ - PeripheralClock = 0; - EMCClock = 0; - } - else { - uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1); - uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F); - uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F); - uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1; - SystemCoreClock = __CLK_DIV(OSC_CLK * mul , cpu_div); - PeripheralClock = __CLK_DIV(OSC_CLK * mul , per_div); - EMCClock = SystemCoreClock / emc_div; - } - } - } - } - /* ---update USBClock------------------*/ - if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider - { - switch (LPC_SC->USBCLKSEL & 0x1F) - { - case 0: - USBClock = 0; //no clock will be provided to the USB subsystem - break; - case 4: - case 6: - { - uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1); - uint8_t usb_div = (LPC_SC->USBCLKSEL & 0x1F); - if(LPC_SC->CLKSRCSEL & 0x01) //pll_clk_in = main_osc - USBClock = OSC_CLK * mul / usb_div; - else //pll_clk_in = irc_clk - USBClock = IRC_OSC * mul / usb_div; - } - break; - default: - USBClock = 0; /* this should never happen! */ - } - } - else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1) - { - if(LPC_SC->CLKSRCSEL & 0x01) //pll1_clk_in = main_osc - USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1)); - else //pll1_clk_in = irc_clk - USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1)); - } - else - USBClock = 0; /* this should never happen! */ -} - - /* Determine clock frequency according to clock register values */ - -#ifdef CORE_M4 - -void fpu_init(void) -{ - // from arm trm manual: -// ; CPACR is located at address 0xE000ED88 -// LDR.W R0, =0xE000ED88 -// ; Read CPACR -// LDR R1, [R0] -// ; Set bits 20-23 to enable CP10 and CP11 coprocessors -// ORR R1, R1, #(0xF << 20) -// ; Write back the modified value to the CPACR -// STR R1, [R0] - - - volatile uint32_t* regCpacr = (uint32_t*) LPC_CPACR; - volatile uint32_t* regMvfr0 = (uint32_t*) SCB_MVFR0; - volatile uint32_t* regMvfr1 = (uint32_t*) SCB_MVFR1; - volatile uint32_t Cpacr; - volatile uint32_t Mvfr0; - volatile uint32_t Mvfr1; - char vfpPresent = 0; - - Mvfr0 = *regMvfr0; - Mvfr1 = *regMvfr1; - - vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1)); - - if(vfpPresent) - { - Cpacr = *regCpacr; - Cpacr |= (0xF << 20); - *regCpacr = Cpacr; // enable CP10 and CP11 for full access - } - -} -#endif - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) -{ -#ifndef __CODE_RED -#ifdef CORE_M4 -fpu_init(); -#endif -#endif - -#if (CLOCK_SETUP) /* Clock Setup */ - LPC_SC->SCS = SCS_Val; - if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ - while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ - } - - LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for sysclk/PLL0*/ - -#if (PLL0_SETUP) - LPC_SC->PLL0CFG = PLL0CFG_Val; - LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0 */ -#endif - -#if (PLL1_SETUP) - LPC_SC->PLL1CFG = PLL1CFG_Val; - LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ -#endif - - LPC_SC->CCLKSEL = CCLKSEL_Val; /* Setup Clock Divider */ - LPC_SC->USBCLKSEL = USBCLKSEL_Val; /* Setup USB Clock Divider */ - LPC_SC->EMCCLKSEL = EMCCLKSEL_Val; /* EMC Clock Selection */ - LPC_SC->SPIFICLKSEL = SPIFICLKSEL_Val; /* SPIFI Clock Selection */ - LPC_SC->PCLKSEL = PCLKSEL_Val; /* Peripheral Clock Selection */ - LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ - LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ -#endif - - LPC_SC->PBOOST |= 0x03; /* Power Boost control */ - -#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ - LPC_SC->FLASHCFG = FLASHCFG_Val|0x03A; -#endif -#ifndef __CODE_RED -#ifdef __RAM_MODE__ - SCB->VTOR = 0x10000000 & 0x3FFFFF80; -#else - SCB->VTOR = 0x00000000 & 0x3FFFFF80; -#endif -#endif - SystemCoreClockUpdate(); -} diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Device/SConscript b/bsp/nxp/lpc/lpc408x/Libraries/Device/SConscript deleted file mode 100644 index bb09284c423..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Device/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -src = Split(''' -NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC407x_8x_177x_8x.c -''') -CPPPATH = [cwd + '/NXP/LPC407x_8x_177x_8x/Include', cwd + '/../CMSIS/Include'] -CPPDEFINES = ['CORE_M4'] - -# add for startup script -if rtconfig.PLATFORM in ['gcc']: - src += ['NXP/LPC407x_8x_177x_8x/Source/Templates/GCC/startup_LPC407x_8x_177x_8x.s'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - src += ['NXP/LPC407x_8x_177x_8x/Source/Templates/ARM/startup_LPC407x_8x_177x_8x.s'] -elif rtconfig.PLATFORM in ['iccarm']: - src += ['NXP/LPC407x_8x_177x_8x/Source/Templates/IAR/startup_LPC407x_8x_177x_8x.s'] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) - -Return('group') diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/SConscript b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/SConscript deleted file mode 100644 index ed77a5ca4fa..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/SConscript +++ /dev/null @@ -1,39 +0,0 @@ -# RT-Thread building script for component - -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -src = Split(''' -source/lpc_adc.c -source/lpc_bod.c -source/lpc_can.c -source/lpc_clkpwr.c -source/lpc_crc.c -source/lpc_dac.c -source/lpc_eeprom.c -source/lpc_emc.c -source/lpc_exti.c -source/lpc_gpdma.c -source/lpc_gpio.c -source/lpc_i2c.c -source/lpc_i2s.c -source/lpc_iap.c -source/lpc_lcd.c -source/lpc_mcpwm.c -source/lpc_nvic.c -source/lpc_pinsel.c -source/lpc_pwm.c -source/lpc_qei.c -source/lpc_rtc.c -source/lpc_ssp.c -source/lpc_systick.c -source/lpc_timer.c -source/lpc_uart.c -source/lpc_wwdt.c -''') -CPPPATH = [cwd + '/include'] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/debug_frmwrk.h b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/debug_frmwrk.h deleted file mode 100644 index dc6bd823a90..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/debug_frmwrk.h +++ /dev/null @@ -1,114 +0,0 @@ -/********************************************************************** -* $Id$ debug_frmwrk.h 2011-06-02 -*//** -* @file debug_frmwrk.h -* @brief Contains some utilities that used for debugging through UART -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -#ifndef __DEBUG_FRMWRK_H_ -#define __DEBUG_FRMWRK_H_ - -#include "lpc_uart.h" - -#define USED_UART_DEBUG_PORT 0 - -#define NUM_SKIPPED_ALLOWED (10) - -#define DBG_GETVAL_IN_DEC (0) -#define DBG_GETVAL_IN_HEX (1) -//#define DBG_GETVAL_IN_CHARS (2) - -#if (USED_UART_DEBUG_PORT == 0) -#define DEBUG_UART_PORT (UART_0) -#elif (USED_UART_DEBUG_PORT == 1) -#define DEBUG_UART_PORT (UART_1) -#elif (USED_UART_DEBUG_PORT == 2) -#define DEBUG_UART_PORT (UART_2) -#elif (USED_UART_DEBUG_PORT == 3) -#define DEBUG_UART_PORT (UART_3) -#elif (USED_UART_DEBUG_PORT == 4) -#define DEBUG_UART_PORT (UART_4) -#else - #error "Invalid UART port selection!" -#endif - -#define _DBG(x) _db_msg(DEBUG_UART_PORT, x) -#define _DBG_(x) _db_msg_(DEBUG_UART_PORT, x) - -#define _DBC(x) _db_char(DEBUG_UART_PORT, x) - -#define _DBD(x) _db_dec(DEBUG_UART_PORT, x) -#define _DBD16(x) _db_dec_16(DEBUG_UART_PORT, x) -#define _DBD32(x) _db_dec_32(DEBUG_UART_PORT, x) - -#define _DBH(x) _db_hex(DEBUG_UART_PORT, x) -#define _DBH16(x) _db_hex_16(DEBUG_UART_PORT, x) -#define _DBH32(x) _db_hex_32(DEBUG_UART_PORT, x) - -#define _DBH_(x) _db_hex_(DEBUG_UART_PORT, x) -#define _DBH16_(x) _db_hex_16_(DEBUG_UART_PORT, x) -#define _DBH32_(x) _db_hex_32_(DEBUG_UART_PORT, x) - -#define _DG _db_get_char(DEBUG_UART_PORT) -#define _DG_NONBLOCK(c) _db_get_char_nonblocking(DEBUG_UART_PORT,c) -#define _DGV(option, numCh, val) _db_get_val(DEBUG_UART_PORT, option, numCh, val) - -//void _printf (const char *format, ...); - -extern void (*_db_msg)(UART_ID_Type UartID, const void *s); -extern void (*_db_msg_)(UART_ID_Type UartID, const void *s); -extern void (*_db_char)(UART_ID_Type UartID, uint8_t ch); -extern void (*_db_dec)(UART_ID_Type UartID, uint8_t decn); -extern void (*_db_dec_16)(UART_ID_Type UartID, uint16_t decn); -extern void (*_db_dec_32)(UART_ID_Type UartID, uint32_t decn); -extern void (*_db_hex)(UART_ID_Type UartID, uint8_t hexn); -extern void (*_db_hex_16)(UART_ID_Type UartID, uint16_t hexn); -extern void (*_db_hex_32)(UART_ID_Type UartID, uint32_t hexn); -extern void (*_db_hex_)(UART_ID_Type UartID, uint8_t hexn); -extern void (*_db_hex_16_)(UART_ID_Type UartID, uint16_t hexn); -extern void (*_db_hex_32_)(UART_ID_Type UartID, uint32_t hexn); - -extern uint8_t (*_db_get_char)(UART_ID_Type UartID); -extern Bool (*_db_get_char_nonblocking)(UART_ID_Type UartID, uint8_t* c); -extern uint8_t (*_db_get_val)(UART_ID_Type UartID, uint8_t option, uint8_t numCh, uint32_t * val); - -uint8_t UARTGetValue (UART_ID_Type UartID, uint8_t option, - uint8_t numCh, uint32_t* val); -void UARTPutChar (UART_ID_Type UartID, uint8_t ch); -void UARTPuts(UART_ID_Type UartID, const void *str); -void UARTPuts_(UART_ID_Type UartID, const void *str); -void UARTPutDec(UART_ID_Type UartID, uint8_t decnum); -void UARTPutDec16(UART_ID_Type UartID, uint16_t decnum); -void UARTPutDec32(UART_ID_Type UartID, uint32_t decnum); -void UARTPutHex (UART_ID_Type UartID, uint8_t hexnum); -void UARTPutHex16 (UART_ID_Type UartID, uint16_t hexnum); -void UARTPutHex32 (UART_ID_Type UartID, uint32_t hexnum); -uint8_t UARTGetChar (UART_ID_Type UartID); -Bool UARTGetCharInNonBlock(UART_ID_Type UartID, uint8_t* c); -void debug_frmwrk_init(void); - -#endif /* __DEBUG_FRMWRK_H_ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc177x_8x_libcfg_default.h b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc177x_8x_libcfg_default.h deleted file mode 100644 index abea52a71cb..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc177x_8x_libcfg_default.h +++ /dev/null @@ -1,156 +0,0 @@ -/********************************************************************** -* $Id$ lpc17xx_libcfg.h 2010-05-21 -*** -* @file lpc17xx_libcfg.h -* @brief Library configuration file -* @version 2.0 -* @date 21. May. 2010 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2010, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -#ifndef _LPC177x_8x_LIBCFG_H_ -#define _LPC177x_8x_LIBCFG_H_ - -#include "lpc_types.h" - - -/************************** DEBUG MODE DEFINITIONS *********************************/ -/* Un-comment the line below to compile the library in DEBUG mode, this will expanse - the "CHECK_PARAM" macro in the FW library code */ - -#define DEBUG - - -/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/ - -/* Comment the line below to disable the specific peripheral inclusion */ - -/* DEBUG_FRAMWORK -------------------- */ -#define _DBGFWK - -/* Clock & Power -------------------- */ -#define _CLKPWR - -/* CRC -------------------- */ -#define _CRC - -/* GPIO ------------------------------- */ -#define _GPIO - -/* NVIC ------------------------------- */ -#define _NVIC - -/* PINSEL ------------------------------- */ -#define _PINSEL - -/* EXTI ------------------------------- */ -#define _EXTI - -/* EMC ------------------------------- */ -#define _EMC - -/* UART ------------------------------- */ -#define _UART - -/* SPI ------------------------------- */ -#define _SPI - -/* SYSTICK --------------------------- */ -#define _SYSTICK - -/* SSP ------------------------------- */ -#define _SSP - - -/* I2C ------------------------------- */ -#define _I2C - -/* TIMER ------------------------------- */ -#define _TIM - -/* WDT ------------------------------- */ -#define _WDT - - -/* GPDMA ------------------------------- */ -#define _GPDMA - - -/* DAC ------------------------------- */ -#define _DAC - -/* ADC ------------------------------- */ -#define _ADC - -/* EEPROM ------------------------------- */ -#define _EEPROM - -/* PWM ------------------------------- */ -#define _PWM - -/* RTC ------------------------------- */ -#define _RTC - -/* I2S ------------------------------- */ -#define _I2S - -/* USB device ------------------------------- */ -#define _USBDEV -#ifdef _USBDEV -#define _USB_DEV_AUDIO -#define _USB_DEV_MASS_STORAGE -#define _USB_DEV_HID -#define _USB_DEV_VIRTUAL_COM -#endif /*_USBDEV*/ - -/* USB Host ------------------------------- */ -#define _USBHost - -/* QEI ------------------------------- */ -#define _QEI - -/* MCPWM ------------------------------- */ -#define _MCPWM - -/* CAN--------------------------------*/ -#define _CAN - -/* EMAC ------------------------------ */ -#define _EMAC - -/* LCD ------------------------------ */ -#define _LCD - -/* MCI ------------------------------ */ -#define _MCI - -/* IAP------------------------------ */ -#define _IAP - -/* BOD------------------------------ */ -#define _BOD -/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/ - - -#endif /* _LPC177x_8x_LIBCFG_H_ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_adc.h b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_adc.h deleted file mode 100644 index 0d0c1df9cfb..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_adc.h +++ /dev/null @@ -1,303 +0,0 @@ -/********************************************************************** -* $Id$ lpc_adc.h 2011-06-02 -*//** -* @file lpc_adc.h -* @brief Contains all macro definitions and function prototypes -* support for ADC firmware library on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup ADC ADC (Analog-to-Digital Converter) - * @ingroup LPC_CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef __LPC_ADC_H_ -#define __LPC_ADC_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC407x_8x_177x_8x.h" -#include "lpc_types.h" - - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Private macros ------------------------------------------------------------- */ -/** @defgroup ADC_Private_Macros ADC Private Macros - * @{ - */ - -/* -------------------------- BIT DEFINITIONS ----------------------------------- */ -/*********************************************************************//** - * Macro defines for ADC control register - **********************************************************************/ - -/** Selects which of the AD0.0:7 pins (channels) is (are) to be sampled and converted */ -#define ADC_CR_CH_SEL(n) ((1UL << n)) - -/** The APB clock (PCLK) is divided by (this value plus one) -* to produce the clock for the A/D */ -#define ADC_CR_CLKDIV(n) ((n<<8)) - -/** Repeated conversions A/D enable bit */ -#define ADC_CR_BURST ((1UL<<16)) - -/** ADC convert in power down mode; if 0, it's in power down mode; if 1, it's in normal -* operation mode */ -#define ADC_CR_PDN ((1UL<<21)) - -/** Start mask bits */ -#define ADC_CR_START_MASK ((7UL<<24)) - -/** Select Start Mode controll the AD Converter in case the Burst bit is 0 (zero) */ -#define ADC_CR_START_MODE_SEL(SEL) ((SEL<<24)) - -/** Start conversion now */ -#define ADC_CR_START_NOW ((1UL<<24)) - -/** Start conversion when the edge selected by bit 27 occurs on P2.10/EINT0 */ -#define ADC_CR_START_EINT0 ((2UL<<24)) - -/** Start conversion when the edge selected by bit 27 occurs on P1.27/CAP0.1 */ -#define ADC_CR_START_CAP01 ((3UL<<24)) - -/** Start conversion when the edge selected by bit 27 occurs on MAT0.1 */ -#define ADC_CR_START_MAT01 ((4UL<<24)) - -/** Start conversion when the edge selected by bit 27 occurs on MAT0.3 */ -#define ADC_CR_START_MAT03 ((5UL<<24)) - -/** Start conversion when the edge selected by bit 27 occurs on MAT1.0 */ -#define ADC_CR_START_MAT10 ((6UL<<24)) - -/** Start conversion when the edge selected by bit 27 occurs on MAT1.1 */ -#define ADC_CR_START_MAT11 ((7UL<<24)) - -/** Start conversion on a falling edge on the selected CAP/MAT signal */ -#define ADC_CR_EDGE ((1UL<<27)) - -/*********************************************************************//** - * Macro defines for ADC Global Data register - **********************************************************************/ - -/** When DONE is 1, this field contains result value of ADC conversion -* (in 12-bit value) */ -#define ADC_GDR_RESULT(n) (((n>>4)&0xFFF)) - -/** These bits contain the channel from which the LS bits were converted */ -#define ADC_GDR_CH(n) (((n>>24)&0x7)) - -/** This bits is used to mask for Channel */ -#define ADC_GDR_CH_MASK ((7UL<<24)) - -/** This bit is 1 in burst mode if the results of one or - * more conversions was (were) lost */ -#define ADC_GDR_OVERRUN_FLAG ((1UL<<30)) - -/** This bit is set to 1 when an A/D conversion completes */ -#define ADC_GDR_DONE_FLAG ((1UL<<31)) - -/*********************************************************************//** - * Macro defines for ADC Interrupt register - **********************************************************************/ - -/** These bits allow control over which A/D channels generate - * interrupts for conversion completion */ -#define ADC_INTEN_CH(n) ((1UL<>4)&0xFFF)) - -/** These bits mirror the OVERRRUN status flags that appear in the - * result register for each A/D channel */ -#define ADC_DR_OVERRUN_FLAG ((1UL<<30)) - -/** This bit is set to 1 when an A/D conversion completes. It is cleared - * when this register is read */ -#define ADC_DR_DONE_FLAG ((1UL<<31)) - -/*********************************************************************//** - * Macro defines for ADC Status register -**********************************************************************/ - -/** These bits mirror the DONE status flags that appear in the result - * register for each A/D channel */ -#define ADC_STAT_CH_DONE_FLAG(n) ((n&0xFF)) - -/** These bits mirror the OVERRRUN status flags that appear in the - * result register for each A/D channel */ -#define ADC_STAT_CH_OVERRUN_FLAG(n) (((n>>8)&0xFF)) - -/** This bit is the A/D interrupt flag */ -#define ADC_STAT_INT_FLAG ((1UL<<16)) - -/*********************************************************************//** - * Macro defines for ADC Trim register -**********************************************************************/ - -/** Offset trim bits for ADC operation */ -#define ADC_ADCOFFS(n) (((n&0xF)<<4)) - -/** Written to boot code*/ -#define ADC_TRIM(n) (((n&0xF)<<8)) - -/** - * @} - */ - - -/* Public Types --------------------------------------------------------------- */ -/** @defgroup ADC_Public_Types ADC Public Types - * @{ - */ - -/*********************************************************************//** - * @brief ADC enumeration - **********************************************************************/ - -/** @brief Channel Selection */ -typedef enum -{ - ADC_CHANNEL_0 = 0, /*!< Channel 0 */ - ADC_CHANNEL_1, /*!< Channel 1 */ - ADC_CHANNEL_2, /*!< Channel 2 */ - ADC_CHANNEL_3, /*!< Channel 3 */ - ADC_CHANNEL_4, /*!< Channel 4 */ - ADC_CHANNEL_5, /*!< Channel 5 */ - ADC_CHANNEL_6, /*!< Channel 6 */ - ADC_CHANNEL_7 /*!< Channel 7 */ -}ADC_CHANNEL_SELECTION; - -/** @brief Type of start option */ -typedef enum -{ - ADC_START_CONTINUOUS = 0, /*!< Continuous mode */ - - ADC_START_NOW, /*!< Start conversion now */ - - ADC_START_ON_EINT0, /*!< Start conversion when the edge selected - * by bit 27 occurs on P2.10/EINT0 */ - ADC_START_ON_CAP01, /*!< Start conversion when the edge selected - * by bit 27 occurs on P1.27/CAP0.1 */ - ADC_START_ON_MAT01, /*!< Start conversion when the edge selected - * by bit 27 occurs on MAT0.1 */ - ADC_START_ON_MAT03, /*!< Start conversion when the edge selected - * by bit 27 occurs on MAT0.3 */ - ADC_START_ON_MAT10, /*!< Start conversion when the edge selected - * by bit 27 occurs on MAT1.0 */ - ADC_START_ON_MAT11 /*!< Start conversion when the edge selected - * by bit 27 occurs on MAT1.1 */ -} ADC_START_OPT; - - -/** @brief Type of edge when start conversion on the selected CAP/MAT signal */ -typedef enum -{ - ADC_START_ON_RISING = 0, /*!< Start conversion on a rising edge - *on the selected CAP/MAT signal */ - ADC_START_ON_FALLING /*!< Start conversion on a falling edge - *on the selected CAP/MAT signal */ -} ADC_START_ON_EDGE_OPT; - -/** @brief* ADC type interrupt enum */ -typedef enum -{ - ADC_ADINTEN0 = 0, /*!< Interrupt channel 0 */ - ADC_ADINTEN1, /*!< Interrupt channel 1 */ - ADC_ADINTEN2, /*!< Interrupt channel 2 */ - ADC_ADINTEN3, /*!< Interrupt channel 3 */ - ADC_ADINTEN4, /*!< Interrupt channel 4 */ - ADC_ADINTEN5, /*!< Interrupt channel 5 */ - ADC_ADINTEN6, /*!< Interrupt channel 6 */ - ADC_ADINTEN7, /*!< Interrupt channel 7 */ - ADC_ADGINTEN /*!< Individual channel/global flag done generate an interrupt */ -}ADC_TYPE_INT_OPT; - -/** @brief ADC Data status */ -typedef enum -{ - ADC_DATA_BURST = 0, /*Burst bit*/ - ADC_DATA_DONE /*Done bit*/ -}ADC_DATA_STATUS; - -/** - * @} - */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup ADC_Public_Functions ADC Public Functions - * @{ - */ - -/* Init/DeInit ADC peripheral ----------------*/ -void ADC_Init(LPC_ADC_TypeDef *ADCx, uint32_t rate); -void ADC_DeInit(LPC_ADC_TypeDef *ADCx); - -/* Enable/Disable ADC functions --------------*/ -void ADC_BurstCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_PowerdownCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_StartCmd(LPC_ADC_TypeDef *ADCx, uint8_t start_mode); -void ADC_ChannelCmd (LPC_ADC_TypeDef *ADCx, uint8_t Channel, FunctionalState NewState); - -/* Configure ADC functions -------------------*/ -void ADC_EdgeStartConfig(LPC_ADC_TypeDef *ADCx, uint8_t EdgeOption); -void ADC_IntConfig (LPC_ADC_TypeDef *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState); - -/* Get ADC information functions -------------------*/ -uint16_t ADC_ChannelGetData(LPC_ADC_TypeDef *ADCx, uint8_t channel); -FlagStatus ADC_ChannelGetStatus(LPC_ADC_TypeDef *ADCx, uint8_t channel, uint32_t StatusType); -uint32_t ADC_GlobalGetData(LPC_ADC_TypeDef *ADCx); -FlagStatus ADC_GlobalGetStatus(LPC_ADC_TypeDef *ADCx, uint32_t StatusType); - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - - -#endif /* LPC_ADC_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_bod.h b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_bod.h deleted file mode 100644 index d5213d7aff7..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_bod.h +++ /dev/null @@ -1,98 +0,0 @@ -/********************************************************************** -* $Id$ lpc_bod.h 2011-12-09 -*//** -* @file lpc_bod.h -* @brief Contain definitions & functions related to BOD. -* @version 1.0 -* @date 09 December. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup BOD BOD (Brown-Out Detector) - * @ingroup LPC_CMSIS_FwLib_Drivers - * @{ - */#ifndef __LPC_BOD_H -#define __LPC_BOD_H -#include "lpc_types.h" -/** @defgroup BOD_Private_Macros BOD Private Macros - * @{ - */ - -/* --------------------- BIT DEFINITIONS -------------------------------------- */ -/********************************************************************** -** Power Mode Control register definitions -**********************************************************************/ -#define BOD_PCON_BODRPM (0x01 << 2) -#define BOD_PCON_BOGD (0x01 << 3) -#define BOD_PCON_BORD (0x01 << 4) - -/********************************************************************** -** Reset Source Identification Register definitions -**********************************************************************/ -#define BOD_RSID_POR (0x01 << 0) -#define BOD_RSID_BODR (0x01 << 3) - -/** - * @} - */ - - /** @defgroup BOD_Public_Types BOD Public Types - * @{ - */ - -/** - * @brief The field to configurate BOD - */ - -typedef struct -{ - uint8_t Enabled; /**< Enable BOD Circuit */ - uint8_t PowerReduced; /**< if ENABLE, BOD will be turned off in Power-down mode or Deep Sleep mode */ - /**< So, BOD can't be used to wake-up from these mode. */ - uint8_t ResetOnVoltageDown; /**< if ENABLE, reset the device when the VDD(REG)(3V3) voltage < the BOD reset trip level */ -}BOD_Config_Type; - -/** - * @} - */ - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup BOD_Public_Functions BOD Public Functions - * @{ - */ -void BOD_Init( BOD_Config_Type* pConfig ); -int32_t BOD_ResetSourceStatus(void); -void BOD_ResetSourceClr(void); -/** - * @} - */ -#endif /* end __LPC_BOD_H */ -/** - * @} - */ - -/***************************************************************************** -** End Of File -******************************************************************************/ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_can.h b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_can.h deleted file mode 100644 index 2eceebeacdd..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_can.h +++ /dev/null @@ -1,1014 +0,0 @@ -/********************************************************************** -* $Id$ lpc_can.h 2011-06-02 -*//** -* @file lpc_can.h -* @brief Contains all macro definitions and function prototypes -* support for CAN firmware library on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup CAN CAN (Controller Area Network) - * @ingroup LPC_CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef __LPC_CAN_H_ -#define __LPC_CAN_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC407x_8x_177x_8x.h" - -#include "lpc_types.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Public Types --------------------------------------------------------------- */ -/** @defgroup CAN_Public_Macros CAN Public Macros - * @{ - */ - -/** Controller ID for CAN1 */ -#define CAN1_CTRL ((uint8_t)(0)) - -/** Controller ID for CAN2 */ -#define CAN2_CTRL ((uint8_t)(1)) - -/** Message(s) Acceptance is enabled */ -#define MSG_ENABLE ((uint8_t)(0)) - -/** Message(s) Acceptance is disabled */ -#define MSG_DISABLE ((uint8_t)(1)) - - -/** - * @} - */ - -/* Private Macros ------------------------------------------------------------- */ -/** @defgroup CAN_Private_Macros CAN Private Macros - * @{ - */ - -/* --------------------- BIT DEFINITIONS -------------------------------------- */ -/*********************************************************************//** - * Macro defines for CAN Mode Register - **********************************************************************/ -/** CAN Reset mode */ -#define CAN_MOD_RM ((uint32_t)(1<<0)) - -/** CAN Listen Only Mode */ -#define CAN_MOD_LOM ((uint32_t)(1<<1)) - -/** CAN Self Test mode */ -#define CAN_MOD_STM ((uint32_t)(1<<2)) - -/** CAN Transmit Priority mode */ -#define CAN_MOD_TPM ((uint32_t)(1<<3)) - -/** CAN Sleep mode */ -#define CAN_MOD_SM ((uint32_t)(1<<4)) - -/** CAN Receive Polarity mode */ -#define CAN_MOD_RPM ((uint32_t)(1<<5)) - -/** CAN Test mode */ -#define CAN_MOD_TM ((uint32_t)(1<<7)) - -/*********************************************************************//** - * Macro defines for CAN Command Register - **********************************************************************/ -/** CAN Transmission Request */ -#define CAN_CMR_TR ((uint32_t)(1)) - -/** CAN Abort Transmission */ -#define CAN_CMR_AT ((uint32_t)(1<<1)) - -/** CAN Release Receive Buffer */ -#define CAN_CMR_RRB ((uint32_t)(1<<2)) - -/** CAN Clear Data Overrun */ -#define CAN_CMR_CDO ((uint32_t)(1<<3)) - -/** CAN Self Reception Request */ -#define CAN_CMR_SRR ((uint32_t)(1<<4)) - -/** CAN Select Tx Buffer 1 */ -#define CAN_CMR_STB1 ((uint32_t)(1<<5)) - -/** CAN Select Tx Buffer 2 */ -#define CAN_CMR_STB2 ((uint32_t)(1<<6)) - -/** CAN Select Tx Buffer 3 */ -#define CAN_CMR_STB3 ((uint32_t)(1<<7)) - -/*********************************************************************//** - * Macro defines for CAN Global Status Register - **********************************************************************/ -/** CAN Receive Buffer Status */ -#define CAN_GSR_RBS ((uint32_t)(1)) - -/** CAN Data Overrun Status */ -#define CAN_GSR_DOS ((uint32_t)(1<<1)) - -/** CAN Transmit Buffer Status */ -#define CAN_GSR_TBS ((uint32_t)(1<<2)) - -/** CAN Transmit Complete Status */ -#define CAN_GSR_TCS ((uint32_t)(1<<3)) - -/** CAN Receive Status */ -#define CAN_GSR_RS ((uint32_t)(1<<4)) - -/** CAN Transmit Status */ -#define CAN_GSR_TS ((uint32_t)(1<<5)) - -/** CAN Error Status */ -#define CAN_GSR_ES ((uint32_t)(1<<6)) - -/** CAN Bus Status */ -#define CAN_GSR_BS ((uint32_t)(1<<7)) - -/** CAN Current value of the Rx Error Counter */ -#define CAN_GSR_RXERR(n) ((uint32_t)((n&0xFF)<<16)) - -/** CAN Current value of the Tx Error Counter */ -#define CAN_GSR_TXERR(n) ((uint32_t)(n&0xFF)<<24)) - -/*********************************************************************//** - * Macro defines for CAN Interrupt and Capture Register - **********************************************************************/ -/** CAN Receive Interrupt */ -#define CAN_ICR_RI ((uint32_t)(1)) - -/** CAN Transmit Interrupt 1 */ -#define CAN_ICR_TI1 ((uint32_t)(1<<1)) - -/** CAN Error Warning Interrupt */ -#define CAN_ICR_EI ((uint32_t)(1<<2)) - -/** CAN Data Overrun Interrupt */ -#define CAN_ICR_DOI ((uint32_t)(1<<3)) - -/** CAN Wake-Up Interrupt */ -#define CAN_ICR_WUI ((uint32_t)(1<<4)) - -/** CAN Error Passive Interrupt */ -#define CAN_ICR_EPI ((uint32_t)(1<<5)) - -/** CAN Arbitration Lost Interrupt */ -#define CAN_ICR_ALI ((uint32_t)(1<<6)) - -/** CAN Bus Error Interrupt */ -#define CAN_ICR_BEI ((uint32_t)(1<<7)) - -/** CAN ID Ready Interrupt */ -#define CAN_ICR_IDI ((uint32_t)(1<<8)) - -/** CAN Transmit Interrupt 2 */ -#define CAN_ICR_TI2 ((uint32_t)(1<<9)) - -/** CAN Transmit Interrupt 3 */ -#define CAN_ICR_TI3 ((uint32_t)(1<<10)) - -/** CAN Error Code Capture */ -#define CAN_ICR_ERRBIT(n) ((uint32_t)((n&0x1F)<<16)) - -/** CAN Error Direction */ -#define CAN_ICR_ERRDIR ((uint32_t)(1<<21)) - -/** CAN Error Capture */ -#define CAN_ICR_ERRC(n) ((uint32_t)((n&0x3)<<22)) - -/** CAN Arbitration Lost Capture */ -#define CAN_ICR_ALCBIT(n) ((uint32_t)((n&0xFF)<<24)) - -/*********************************************************************//** - * Macro defines for CAN Interrupt Enable Register - **********************************************************************/ -/** CAN Receive Interrupt Enable */ -#define CAN_IER_RIE ((uint32_t)(1)) - -/** CAN Transmit Interrupt Enable for buffer 1 */ -#define CAN_IER_TIE1 ((uint32_t)(1<<1)) - -/** CAN Error Warning Interrupt Enable */ -#define CAN_IER_EIE ((uint32_t)(1<<2)) - -/** CAN Data Overrun Interrupt Enable */ -#define CAN_IER_DOIE ((uint32_t)(1<<3)) - -/** CAN Wake-Up Interrupt Enable */ -#define CAN_IER_WUIE ((uint32_t)(1<<4)) - -/** CAN Error Passive Interrupt Enable */ -#define CAN_IER_EPIE ((uint32_t)(1<<5)) - -/** CAN Arbitration Lost Interrupt Enable */ -#define CAN_IER_ALIE ((uint32_t)(1<<6)) - -/** CAN Bus Error Interrupt Enable */ -#define CAN_IER_BEIE ((uint32_t)(1<<7)) - -/** CAN ID Ready Interrupt Enable */ -#define CAN_IER_IDIE ((uint32_t)(1<<8)) - -/** CAN Transmit Enable Interrupt for Buffer 2 */ -#define CAN_IER_TIE2 ((uint32_t)(1<<9)) - -/** CAN Transmit Enable Interrupt for Buffer 3 */ -#define CAN_IER_TIE3 ((uint32_t)(1<<10)) - -/*********************************************************************//** - * Macro defines for CAN Bus Timing Register - **********************************************************************/ -/** CAN Baudrate Prescaler */ -#define CAN_BTR_BRP(n) ((uint32_t)(n&0x3FF)) - -/** CAN Synchronization Jump Width */ -#define CAN_BTR_SJM(n) ((uint32_t)((n&0x3)<<14)) - -/** CAN Time Segment 1 */ -#define CAN_BTR_TESG1(n) ((uint32_t)(n&0xF)<<16)) - -/** CAN Time Segment 2 */ -#define CAN_BTR_TESG2(n) ((uint32_t)(n&0xF)<<20)) - -/** CAN Sampling */ -#define CAN_BTR_SAM(n) ((uint32_t)(1<<23)) - -/*********************************************************************//** - * Macro defines for CAN Error Warning Limit Register - **********************************************************************/ -/** CAN Error Warning Limit */ -#define CAN_EWL_EWL(n) ((uint32_t)(n&0xFF)) - -/*********************************************************************//** - * Macro defines for CAN Status Register - **********************************************************************/ -/** CAN Receive Buffer Status */ -#define CAN_SR_RBS ((uint32_t)(1)) - -/** CAN Data Overrun Status */ -#define CAN_SR_DOS ((uint32_t)(1<<1)) - -/** CAN Transmit Buffer Status 1 */ -#define CAN_SR_TBS1 ((uint32_t)(1<<2)) - -/** CAN Transmission Complete Status of Buffer 1 */ -#define CAN_SR_TCS1 ((uint32_t)(1<<3)) - -/** CAN Receive Status */ -#define CAN_SR_RS ((uint32_t)(1<<4)) - -/** CAN Transmit Status 1 */ -#define CAN_SR_TS1 ((uint32_t)(1<<5)) - -/** CAN Error Status */ -#define CAN_SR_ES ((uint32_t)(1<<6)) - -/** CAN Bus Status */ -#define CAN_SR_BS ((uint32_t)(1<<7)) - -/** CAN Transmit Buffer Status 2 */ -#define CAN_SR_TBS2 ((uint32_t)(1<<10)) - -/** CAN Transmission Complete Status of Buffer 2 */ -#define CAN_SR_TCS2 ((uint32_t)(1<<11)) - -/** CAN Transmit Status 2 */ -#define CAN_SR_TS2 ((uint32_t)(1<<13)) - -/** CAN Transmit Buffer Status 2 */ -#define CAN_SR_TBS3 ((uint32_t)(1<<18)) - -/** CAN Transmission Complete Status of Buffer 2 */ -#define CAN_SR_TCS3 ((uint32_t)(1<<19)) - -/** CAN Transmit Status 2 */ -#define CAN_SR_TS3 ((uint32_t)(1<<21)) - -/*********************************************************************//** - * Macro defines for CAN Receive Frame Status Register - **********************************************************************/ -/** CAN ID Index */ -#define CAN_RFS_ID_INDEX(n) ((uint32_t)(n&0x3FF)) - -/** CAN Bypass */ -#define CAN_RFS_BP ((uint32_t)(1<<10)) - -/** CAN Data Length Code */ -#define CAN_RFS_DLC(n) ((uint32_t)((n&0xF)<<16) - -/** CAN Remote Transmission Request */ -#define CAN_RFS_RTR ((uint32_t)(1<<30)) - -/** CAN control 11 bit or 29 bit Identifier */ -#define CAN_RFS_FF ((uint32_t)(1<<31)) - -/*********************************************************************//** - * Macro defines for CAN Receive Identifier Register - **********************************************************************/ -/** CAN 11 bit Identifier */ -#define CAN_RID_ID_11(n) ((uint32_t)(n&0x7FF)) - -/** CAN 29 bit Identifier */ -#define CAN_RID_ID_29(n) ((uint32_t)(n&0x1FFFFFFF)) - -/*********************************************************************//** - * Macro defines for CAN Receive Data A Register - **********************************************************************/ -/** CAN Receive Data 1 */ -#define CAN_RDA_DATA1(n) ((uint32_t)(n&0xFF)) - -/** CAN Receive Data 2 */ -#define CAN_RDA_DATA2(n) ((uint32_t)((n&0xFF)<<8)) - -/** CAN Receive Data 3 */ -#define CAN_RDA_DATA3(n) ((uint32_t)((n&0xFF)<<16)) - -/** CAN Receive Data 4 */ -#define CAN_RDA_DATA4(n) ((uint32_t)((n&0xFF)<<24)) - -/*********************************************************************//** - * Macro defines for CAN Receive Data B Register - **********************************************************************/ -/** CAN Receive Data 5 */ -#define CAN_RDB_DATA5(n) ((uint32_t)(n&0xFF)) - -/** CAN Receive Data 6 */ -#define CAN_RDB_DATA6(n) ((uint32_t)((n&0xFF)<<8)) - -/** CAN Receive Data 7 */ -#define CAN_RDB_DATA7(n) ((uint32_t)((n&0xFF)<<16)) - -/** CAN Receive Data 8 */ -#define CAN_RDB_DATA8(n) ((uint32_t)((n&0xFF)<<24)) - -/*********************************************************************//** - * Macro defines for CAN Transmit Frame Information Register - **********************************************************************/ -/** CAN Priority */ -#define CAN_TFI_PRIO(n) ((uint32_t)(n&0xFF)) - -/** CAN Data Length Code */ -#define CAN_TFI_DLC(n) ((uint32_t)((n&0xF)<<16)) - -/** CAN Remote Frame Transmission */ -#define CAN_TFI_RTR ((uint32_t)(1<<30)) - -/** CAN control 11-bit or 29-bit Identifier */ -#define CAN_TFI_FF ((uint32_t)(1<<31)) - -/*********************************************************************//** - * Macro defines for CAN Transmit Identifier Register - **********************************************************************/ -/** CAN 11-bit Identifier */ -#define CAN_TID_ID11(n) ((uint32_t)(n&0x7FF)) - -/** CAN 11-bit Identifier */ -#define CAN_TID_ID29(n) ((uint32_t)(n&0x1FFFFFFF)) - -/*********************************************************************//** - * Macro defines for CAN Transmit Data A Register - **********************************************************************/ -/** CAN Transmit Data 1 */ -#define CAN_TDA_DATA1(n) ((uint32_t)(n&0xFF)) - -/** CAN Transmit Data 2 */ -#define CAN_TDA_DATA2(n) ((uint32_t)((n&0xFF)<<8)) - -/** CAN Transmit Data 3 */ -#define CAN_TDA_DATA3(n) ((uint32_t)((n&0xFF)<<16)) - -/** CAN Transmit Data 4 */ -#define CAN_TDA_DATA4(n) ((uint32_t)((n&0xFF)<<24)) - -/*********************************************************************//** - * Macro defines for CAN Transmit Data B Register - **********************************************************************/ -/** CAN Transmit Data 5 */ -#define CAN_TDA_DATA5(n) ((uint32_t)(n&0xFF)) - -/** CAN Transmit Data 6 */ -#define CAN_TDA_DATA6(n) ((uint32_t)((n&0xFF)<<8)) - -/** CAN Transmit Data 7 */ -#define CAN_TDA_DATA7(n) ((uint32_t)((n&0xFF)<<16)) - -/** CAN Transmit Data 8 */ -#define CAN_TDA_DATA8(n) ((uint32_t)((n&0xFF)<<24)) - -/*********************************************************************//** - * Macro defines for CAN Sleep Clear Register - **********************************************************************/ -/** CAN1 Sleep mode */ -#define CAN1SLEEPCLR ((uint32_t)(1<<1)) - -/** CAN2 Sleep Mode */ -#define CAN2SLEEPCLR ((uint32_t)(1<<2)) - -/*********************************************************************//** - * Macro defines for CAN Wake up Flags Register - **********************************************************************/ -/** CAN1 Sleep mode */ -#define CAN_WAKEFLAGES_CAN1WAKE ((uint32_t)(1<<1)) - -/** CAN2 Sleep Mode */ -#define CAN_WAKEFLAGES_CAN2WAKE ((uint32_t)(1<<2)) - -/*********************************************************************//** - * Macro defines for Central transmit Status Register - **********************************************************************/ -/** CAN Transmit 1 */ -#define CAN_TSR_TS1 ((uint32_t)(1)) - -/** CAN Transmit 2 */ -#define CAN_TSR_TS2 ((uint32_t)(1<<1)) - -/** CAN Transmit Buffer Status 1 */ -#define CAN_TSR_TBS1 ((uint32_t)(1<<8)) - -/** CAN Transmit Buffer Status 2 */ -#define CAN_TSR_TBS2 ((uint32_t)(1<<9)) - -/** CAN Transmission Complete Status 1 */ -#define CAN_TSR_TCS1 ((uint32_t)(1<<16)) - -/** CAN Transmission Complete Status 2 */ -#define CAN_TSR_TCS2 ((uint32_t)(1<<17)) - -/*********************************************************************//** - * Macro defines for Central Receive Status Register - **********************************************************************/ -/** CAN Receive Status 1 */ -#define CAN_RSR_RS1 ((uint32_t)(1)) - -/** CAN Receive Status 1 */ -#define CAN_RSR_RS2 ((uint32_t)(1<<1)) - -/** CAN Receive Buffer Status 1*/ -#define CAN_RSR_RB1 ((uint32_t)(1<<8)) - -/** CAN Receive Buffer Status 2*/ -#define CAN_RSR_RB2 ((uint32_t)(1<<9)) - -/** CAN Data Overrun Status 1 */ -#define CAN_RSR_DOS1 ((uint32_t)(1<<16)) - -/** CAN Data Overrun Status 1 */ -#define CAN_RSR_DOS2 ((uint32_t)(1<<17)) - -/*********************************************************************//** - * Macro defines for Central Miscellaneous Status Register - **********************************************************************/ -/** Same CAN Error Status in CAN1GSR */ -#define CAN_MSR_E1 ((uint32_t)(1)) - -/** Same CAN Error Status in CAN2GSR */ -#define CAN_MSR_E2 ((uint32_t)(1<<1)) - -/** Same CAN Bus Status in CAN1GSR */ -#define CAN_MSR_BS1 ((uint32_t)(1<<8)) - -/** Same CAN Bus Status in CAN2GSR */ -#define CAN_MSR_BS2 ((uint32_t)(1<<9)) - -/*********************************************************************//** - * Macro defines for Acceptance Filter Mode Register - **********************************************************************/ -/** CAN Acceptance Filter Off mode */ -#define CAN_AFMR_AccOff ((uint32_t)(1)) - -/** CAN Acceptance File Bypass mode */ -#define CAN_AFMR_AccBP ((uint32_t)(1<<1)) - -/** FullCAN Mode Enhancements */ -#define CAN_AFMR_eFCAN ((uint32_t)(1<<2)) - -/*********************************************************************//** - * Macro defines for Standard Frame Individual Start Address Register - **********************************************************************/ -/** The start address of the table of individual Standard Identifier */ -#define CAN_STT_sa(n) ((uint32_t)((n&1FF)<<2)) - -/*********************************************************************//** - * Macro defines for Standard Frame Group Start Address Register - **********************************************************************/ -/** The start address of the table of grouped Standard Identifier */ -#define CAN_SFF_GRP_sa(n) ((uint32_t)((n&3FF)<<2)) - -/*********************************************************************//** - * Macro defines for Extended Frame Start Address Register - **********************************************************************/ -/** The start address of the table of individual Extended Identifier */ -#define CAN_EFF_sa(n) ((uint32_t)((n&1FF)<<2)) - -/*********************************************************************//** - * Macro defines for Extended Frame Group Start Address Register - **********************************************************************/ -/** The start address of the table of grouped Extended Identifier */ -#define CAN_Eff_GRP_sa(n) ((uint32_t)((n&3FF)<<2)) - -/*********************************************************************//** - * Macro defines for End Of AF Table Register - **********************************************************************/ -/** The End of Table of AF LookUp Table */ -#define CAN_EndofTable(n) ((uint32_t)((n&3FF)<<2)) - -/*********************************************************************//** - * Macro defines for LUT Error Address Register - **********************************************************************/ -/** CAN Look-Up Table Error Address */ -#define CAN_LUTerrAd(n) ((uint32_t)((n&1FF)<<2)) - -/*********************************************************************//** - * Macro defines for LUT Error Register - **********************************************************************/ -/** CAN Look-Up Table Error */ -#define CAN_LUTerr ((uint32_t)(1)) - -/*********************************************************************//** - * Macro defines for Global FullCANInterrupt Enable Register - **********************************************************************/ -/** Global FullCANInterrupt Enable */ -#define CAN_FCANIE ((uint32_t)(1)) - -/*********************************************************************//** - * Macro defines for FullCAN Interrupt and Capture Register 0 - **********************************************************************/ -/** FullCAN Interrupt and Capture (0-31)*/ -#define CAN_FCANIC0_IntPnd(n) ((uint32_t)(1<=0)&&(data <= 0xFFFFFFFF)) - -/** Macro to check frequency value */ -#define PRAM_I2S_FREQ(freq) ((freq>=16000)&&(freq <= 96000)) - -/** Macro to check Frame Identifier */ -#define PARAM_ID_11(n) ((n>>11)==0) /*-- 11 bit --*/ -#define PARAM_ID_29(n) ((n>>29)==0) /*-- 29 bit --*/ - -/** Macro to check DLC value */ -#define PARAM_DLC(n) ((n>>4)==0) /*-- 4 bit --*/ - -/** Macro to check ID format type */ -#define PARAM_ID_FORMAT(n) ((n==STD_ID_FORMAT)||(n==EXT_ID_FORMAT)) - -/** Macro to check Group identifier */ -#define PARAM_GRP_ID(x, y) ((x<=y)) - -/** Macro to check Frame type */ -#define PARAM_FRAME_TYPE(n) ((n==DATA_FRAME)||(n==REMOTE_FRAME)) - -/** Macro to check Control/Central Status type parameter */ -#define PARAM_CTRL_STS_TYPE(n) ((n==CANCTRL_GLOBAL_STS)||(n==CANCTRL_INT_CAP) \ - ||(n==CANCTRL_ERR_WRN)||(n==CANCTRL_STS)) - -/** Macro to check CR status type */ -#define PARAM_CR_STS_TYPE(n) ((n==CANCR_TX_STS)||(n==CANCR_RX_STS) \ - ||(n==CANCR_MS)) - -/** Macro to check AF Mode type parameter */ -#define PARAM_AFMODE_TYPE(n) ((n==CAN_NORMAL)||(n==CAN_ACC_OFF) \ - ||(n==CAN_ACC_BP)||(n==CAN_EFCAN)) - -/** Macro to check Operation Mode */ -#define PARAM_MODE_TYPE(n) ((n==CAN_OPERATING_MODE)||(n==CAN_RESET_MODE) \ - ||(n==CAN_LISTENONLY_MODE)||(n==CAN_SELFTEST_MODE) \ - ||(n==CAN_TXPRIORITY_MODE)||(n==CAN_SLEEP_MODE) \ - ||(n==CAN_RXPOLARITY_MODE)||(n==CAN_TEST_MODE)) - -/** Macro define for struct AF_Section parameter */ -#define PARAM_CTRL(n) ((n==CAN1_CTRL)|(n==CAN2_CTRL)) - -/** Macro define for struct AF_Section parameter */ -#define PARAM_MSG_DISABLE(n) ((n==MSG_ENABLE)|(n==MSG_DISABLE)) - -/**Macro to check Interrupt Type parameter */ -#define PARAM_INT_EN_TYPE(n) ((n==CANINT_RIE)||(n==CANINT_TIE1) \ - ||(n==CANINT_EIE)||(n==CANINT_DOIE) \ - ||(n==CANINT_WUIE)||(n==CANINT_EPIE) \ - ||(n==CANINT_ALIE)||(n==CANINT_BEIE) \ - ||(n==CANINT_IDIE)||(n==CANINT_TIE2) \ - ||(n==CANINT_TIE3)||(n==CANINT_FCE)) - -/** Macro to check AFLUT Entry type */ -#define PARAM_AFLUT_ENTRY_TYPE(n) ((n==FULLCAN_ENTRY)||(n==EXPLICIT_STANDARD_ENTRY)\ - ||(n==GROUP_STANDARD_ENTRY)||(n==EXPLICIT_EXTEND_ENTRY) \ - ||(n==GROUP_EXTEND_ENTRY)) - -/** Macro to check position */ -#define PARAM_POSITION(n) ((n>=0)&&(n<512)) - -/** - * @} - */ - -/* Public Types --------------------------------------------------------------- */ -/** @defgroup CAN_Public_Types CAN Public Types - * @{ - */ - - -/*********************************************************************** - * CAN device configuration commands (IOCTL commands and arguments) - **********************************************************************/ -/** CAN peripheral ID 0 */ -#define CAN_1 0 - -/** CAN peripheral ID 1 */ -#define CAN_2 1 - -/** - * @brief CAN peripheral ID no - */ -typedef enum -{ - CAN_ID_1 = CAN_1, - CAN_ID_2 = CAN_2 -} en_CAN_unitId; - -/** - * @brief CAN ID format definition - */ -typedef enum -{ - STD_ID_FORMAT = 0, /**< Use standard ID format (11 bit ID) */ - EXT_ID_FORMAT = 1 /**< Use extended ID format (29 bit ID) */ -} CAN_ID_FORMAT_Type; - -/** - * @brief AFLUT Entry type definition - */ -typedef enum -{ - FULLCAN_ENTRY = 0, - EXPLICIT_STANDARD_ENTRY, - GROUP_STANDARD_ENTRY, - EXPLICIT_EXTEND_ENTRY, - GROUP_EXTEND_ENTRY, -} AFLUT_ENTRY_Type; - -/** - * @brief Symbolic names for type of CAN message - */ -typedef enum -{ - DATA_FRAME = 0, /**< Data frame */ - REMOTE_FRAME = 1 /**< Remote frame */ -} CAN_FRAME_Type; - -/** - * @brief CAN Control status definition - */ -typedef enum -{ - CANCTRL_GLOBAL_STS = 0, /**< CAN Global Status */ - CANCTRL_INT_CAP, /**< CAN Interrupt and Capture */ - CANCTRL_ERR_WRN, /**< CAN Error Warning Limit */ - CANCTRL_STS /**< CAN Control Status */ -} CAN_CTRL_STS_Type; - -/** - * @brief Central CAN status type definition - */ -typedef enum -{ - CANCR_TX_STS = 0, /**< Central CAN Tx Status */ - CANCR_RX_STS, /**< Central CAN Rx Status */ - CANCR_MS /**< Central CAN Miscellaneous Status */ -} CAN_CR_STS_Type; - -/** - * @brief FullCAN Interrupt Capture type definition - */ -typedef enum -{ - FULLCAN_IC0, /**< FullCAN Interrupt and Capture 0 */ - FULLCAN_IC1 /**< FullCAN Interrupt and Capture 1 */ -}FullCAN_IC_Type; - -/** - * @brief CAN interrupt enable type definition - */ -typedef enum -{ - CANINT_RIE = 0, /**< CAN Receiver Interrupt Enable */ - CANINT_TIE1, /**< CAN Transmit Interrupt Enable */ - CANINT_EIE, /**< CAN Error Warning Interrupt Enable */ - CANINT_DOIE, /**< CAN Data Overrun Interrupt Enable */ - CANINT_WUIE, /**< CAN Wake-Up Interrupt Enable */ - CANINT_EPIE, /**< CAN Error Passive Interrupt Enable */ - CANINT_ALIE, /**< CAN Arbitration Lost Interrupt Enable */ - CANINT_BEIE, /**< CAN Bus Error Inter rupt Enable */ - CANINT_IDIE, /**< CAN ID Ready Interrupt Enable */ - CANINT_TIE2, /**< CAN Transmit Interrupt Enable for Buffer2 */ - CANINT_TIE3, /**< CAN Transmit Interrupt Enable for Buffer3 */ - CANINT_FCE /**< FullCAN Interrupt Enable */ -} CAN_INT_EN_Type; - -/** - * @brief Acceptance Filter Mode type definition - */ -typedef enum -{ - CAN_NORMAL = 0, /**< Normal Mode */ - CAN_ACC_OFF, /**< Acceptance Filter Off Mode */ - CAN_ACC_BP, /**< Acceptance Fileter Bypass Mode */ - CAN_EFCAN /**< FullCAN Mode Enhancement */ -} CAN_AFMODE_Type; - -/** - * @brief CAN Mode Type definition - */ -typedef enum -{ - CAN_OPERATING_MODE = 0, /**< Operating Mode */ - CAN_RESET_MODE, /**< Reset Mode */ - CAN_LISTENONLY_MODE, /**< Listen Only Mode */ - CAN_SELFTEST_MODE, /**< Seft Test Mode */ - CAN_TXPRIORITY_MODE, /**< Transmit Priority Mode */ - CAN_SLEEP_MODE, /**< Sleep Mode */ - CAN_RXPOLARITY_MODE, /**< Receive Polarity Mode */ - CAN_TEST_MODE /**< Test Mode */ -} CAN_MODE_Type; - -/** - * @brief Error values that functions can return - */ -typedef enum -{ - CAN_OK = 1, /**< No error */ - CAN_OBJECTS_FULL_ERROR, /**< No more rx or tx objects available */ - CAN_FULL_OBJ_NOT_RCV, /**< Full CAN object not received */ - CAN_NO_RECEIVE_DATA, /**< No have receive data available */ - CAN_AF_ENTRY_ERROR, /**< Entry load in AFLUT is unvalid */ - CAN_CONFLICT_ID_ERROR, /**< Conflict ID occur */ - CAN_ENTRY_NOT_EXIT_ERROR /**< Entry remove outo AFLUT is not exit */ -} CAN_ERROR; - -/** - * @brief Pin Configuration structure - */ -typedef struct -{ - uint8_t RD; /**< Serial Inputs, from CAN transceivers, should be: - ** For CAN1: - - CAN_RD1_P0_0: RD pin is on P0.0 - - CAN_RD1_P0_21 : RD pin is on P0.21 - ** For CAN2: - - CAN_RD2_P0_4: RD pin is on P0.4 - - CAN_RD2_P2_7: RD pin is on P2.7 - */ - uint8_t TD; /**< Serial Outputs, To CAN transceivers, should be: - ** For CAN1: - - CAN_TD1_P0_1: TD pin is on P0.1 - - CAN_TD1_P0_22: TD pin is on P0.22 - ** For CAN2: - - CAN_TD2_P0_5: TD pin is on P0.5 - - CAN_TD2_P2_8: TD pin is on P2.8 - */ -} CAN_PinCFG_Type; - -/** - * @brief CAN message object structure - */ -typedef struct -{ - uint32_t id; /**< 29 bit identifier, it depend on "format" value - - if format = STD_ID_FORMAT, id should be 11 bit identifier - - if format = EXT_ID_FORMAT, id should be 29 bit identifier - */ - uint8_t dataA[4]; /**< Data field A */ - uint8_t dataB[4]; /**< Data field B */ - uint8_t len; /**< Length of data field in bytes, should be: - - 0000b-0111b: 0-7 bytes - - 1xxxb: 8 bytes - */ - uint8_t format; /**< Identifier Format, should be: - - STD_ID_FORMAT: Standard ID - 11 bit format - - EXT_ID_FORMAT: Extended ID - 29 bit format - */ - uint8_t type; /**< Remote Frame transmission, should be: - - DATA_FRAME: the number of data bytes called out by the DLC - field are send from the CANxTDA and CANxTDB registers - - REMOTE_FRAME: Remote Frame is sent - */ -} CAN_MSG_Type; - -/** - * @brief FullCAN Entry structure - */ -typedef struct -{ - uint8_t controller; /**< CAN Controller, should be: - - CAN1_CTRL: CAN1 Controller - - CAN2_CTRL: CAN2 Controller - */ - uint8_t disable; /**< Disable bit, should be: - - MSG_ENABLE: disable bit = 0 - - MSG_DISABLE: disable bit = 1 - */ - uint16_t id_11; /**< Standard ID, should be 11-bit value */ -} FullCAN_Entry; - -/** - * @brief Standard ID Frame Format Entry structure - */ -typedef struct -{ - uint8_t controller; /**< CAN Controller, should be: - - CAN1_CTRL: CAN1 Controller - - CAN2_CTRL: CAN2 Controller - */ - uint8_t disable; /**< Disable bit, should be: - - MSG_ENABLE: disable bit = 0 - - MSG_DISABLE: disable bit = 1 - */ - uint16_t id_11; /**< Standard ID, should be 11-bit value */ -} SFF_Entry; - -/** - * @brief Group of Standard ID Frame Format Entry structure - */ -typedef struct -{ - uint8_t controller1; /**< First CAN Controller, should be: - - CAN1_CTRL: CAN1 Controller - - CAN2_CTRL: CAN2 Controller - */ - uint8_t disable1; /**< First Disable bit, should be: - - MSG_ENABLE: disable bit = 0) - - MSG_DISABLE: disable bit = 1 - */ - uint16_t lowerID; /**< ID lower bound, should be 11-bit value */ - uint8_t controller2; /**< Second CAN Controller, should be: - - CAN1_CTRL: CAN1 Controller - - CAN2_CTRL: CAN2 Controller - */ - uint8_t disable2; /**< Second Disable bit, should be: - - MSG_ENABLE: disable bit = 0 - - MSG_DISABLE: disable bit = 1 - */ - uint16_t upperID; /**< ID upper bound, should be 11-bit value and - equal or greater than lowerID - */ -} SFF_GPR_Entry; - -/** - * @brief Extended ID Frame Format Entry structure - */ -typedef struct -{ - uint8_t controller; /**< CAN Controller, should be: - - CAN1_CTRL: CAN1 Controller - - CAN2_CTRL: CAN2 Controller - */ - uint32_t ID_29; /**< Extend ID, shoud be 29-bit value */ -} EFF_Entry; - - -/** - * @brief Group of Extended ID Frame Format Entry structure - */ -typedef struct -{ - uint8_t controller1; /**< First CAN Controller, should be: - - CAN1_CTRL: CAN1 Controller - - CAN2_CTRL: CAN2 Controller - */ - uint8_t controller2; /**< Second Disable bit, should be: - - MSG_ENABLE: disable bit = 0(default) - - MSG_DISABLE: disable bit = 1 - */ - uint32_t lowerEID; /**< Extended ID lower bound, should be 29-bit value */ - uint32_t upperEID; /**< Extended ID upper bound, should be 29-bit value */ -} EFF_GPR_Entry; - - -/** - * @brief Acceptance Filter Section Table structure - */ -typedef struct -{ - FullCAN_Entry* FullCAN_Sec; /**< The pointer point to FullCAN_Entry */ - uint8_t FC_NumEntry; /**< FullCAN Entry Number */ - SFF_Entry* SFF_Sec; /**< The pointer point to SFF_Entry */ - uint8_t SFF_NumEntry; /**< Standard ID Entry Number */ - SFF_GPR_Entry* SFF_GPR_Sec; /**< The pointer point to SFF_GPR_Entry */ - uint8_t SFF_GPR_NumEntry; /**< Group Standard ID Entry Number */ - EFF_Entry* EFF_Sec; /**< The pointer point to EFF_Entry */ - uint8_t EFF_NumEntry; /**< Extended ID Entry Number */ - EFF_GPR_Entry* EFF_GPR_Sec; /**< The pointer point to EFF_GPR_Entry */ - uint8_t EFF_GPR_NumEntry; /**< Group Extended ID Entry Number */ -} AF_SectionDef; - -/** - * @} - */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup CAN_Public_Functions CAN Public Functions - * @{ - */ - -/* Init/DeInit CAN peripheral -----------*/ -void CAN_Init(uint8_t canId, uint32_t baudrate); -void CAN_DeInit(uint8_t canId); - -/* CAN messages functions ---------------*/ -Status CAN_SendMsg(uint8_t canId, CAN_MSG_Type *CAN_Msg); -Status CAN_ReceiveMsg(uint8_t canId, CAN_MSG_Type *CAN_Msg); -CAN_ERROR FCAN_ReadObj(CAN_MSG_Type *CAN_Msg); - -/* CAN configure functions ---------------*/ -void CAN_ModeConfig(uint8_t canId, CAN_MODE_Type mode, - FunctionalState NewState); -void CAN_SetAFMode(CAN_AFMODE_Type AFmode); -void CAN_SetCommand(uint8_t canId, uint32_t CMRType); - -/* AFLUT functions ---------------------- */ -CAN_ERROR CAN_SetupAFLUT(AF_SectionDef* AFSection); -CAN_ERROR CAN_LoadFullCANEntry(uint8_t canId, uint16_t ID); -CAN_ERROR CAN_LoadExplicitEntry(uint8_t canId, uint32_t ID, - CAN_ID_FORMAT_Type format); -CAN_ERROR CAN_LoadGroupEntry(uint8_t canId, uint32_t lowerID, - uint32_t upperID, CAN_ID_FORMAT_Type format); -CAN_ERROR CAN_RemoveEntry(AFLUT_ENTRY_Type EntryType, uint16_t position); - -/* CAN interrupt functions -----------------*/ -void CAN_IRQCmd(uint8_t canId, CAN_INT_EN_Type arg, FunctionalState NewState); -uint32_t CAN_IntGetStatus(uint8_t canId); - -/* CAN get status functions ----------------*/ -IntStatus CAN_FullCANIntGetStatus (void); -uint32_t CAN_FullCANPendGetStatus (FullCAN_IC_Type type); -uint32_t CAN_GetCTRLStatus(uint8_t canId, CAN_CTRL_STS_Type arg); -uint32_t CAN_GetCRStatus(CAN_CR_STS_Type arg); - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - -#endif /* LPC_CAN_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_clkpwr.h b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_clkpwr.h deleted file mode 100644 index 5895d9dd590..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_clkpwr.h +++ /dev/null @@ -1,248 +0,0 @@ -/********************************************************************** -* $Id$ lpc_clkpwr.h 2011-06-02 -*//** -* @file lpc_clkpwr.h -* @brief Contains all macro definitions and function prototypes -* support for Clock and Power Control firmware library on -* LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup CLKPWR CLKPWR (Clock Power) - * @ingroup LPC_CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef __LPC_CLKPWR_H_ -#define __LPC_CLKPWR_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC407x_8x_177x_8x.h" -#include "lpc_types.h" -#include "system_LPC407x_8x_177x_8x.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Public Macros -------------------------------------------------------------- */ -/** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros - * @{ - */ - -/******************************************************************** -* Clock Source Selection Definitions -**********************************************************************/ -#define CLKPWR_CLKSRCSEL_IRCOSC ((uint32_t)(0)) -#define CLKPWR_CLKSRCSEL_MAINOSC ((uint32_t)(1)) - -/******************************************************************** -* Clock type/domain Definitions (calculated from input and pre-configuration -* parameter(s) -**********************************************************************/ -#define CLKPWR_CLKTYPE_CPU ((uint32_t)(0)) -#define CLKPWR_CLKTYPE_PER ((uint32_t)(1)) -#define CLKPWR_CLKTYPE_EMC ((uint32_t)(2)) -#define CLKPWR_CLKTYPE_USB ((uint32_t)(3)) - -/******************************************************************** -* Power Control for Peripherals Definitions -**********************************************************************/ -/** LCD controller power/clock control bit */ -#define CLKPWR_PCONP_PCLCD ((uint32_t)(1<<0)) - -/** Timer/Counter 0 power/clock control bit */ -#define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1)) - -/* Timer/Counter 1 power/clock control bit */ -#define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2)) - -/** UART0 power/clock control bit */ -#define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3)) - -/** UART1 power/clock control bit */ -#define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4)) - -/** PWM0 power/clock control bit */ -#define CLKPWR_PCONP_PCPWM0 ((uint32_t)(1<<5)) - -/** PWM1 power/clock control bit */ -#define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6)) - -/** The I2C0 interface power/clock control bit */ -#define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7)) - -/** UART4 power/clock control bit */ -#define CLKPWR_PCONP_PCUART4 ((uint32_t)(1<<8)) - -/** The RTC power/clock control bit */ -#define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9)) - -/** The SSP1 interface power/clock control bit */ -#define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10)) - -/** External Memory controller power/clock control bit */ -#define CLKPWR_PCONP_PCEMC ((uint32_t)(1<<11)) - -/** A/D converter 0 (ADC0) power/clock control bit */ -#define CLKPWR_PCONP_PCADC ((uint32_t)(1<<12)) - -/** CAN Controller 1 power/clock control bit */ -#define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13)) - -/** CAN Controller 2 power/clock control bit */ -#define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14)) - -/** GPIO power/clock control bit */ -#define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15)) - -/** Motor Control PWM */ -#define CLKPWR_PCONP_PCMCPWM ((uint32_t)(1<<17)) - -/** Quadrature Encoder Interface power/clock control bit */ -#define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18)) - -/** The I2C1 interface power/clock control bit */ -#define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19)) - -/** The SSP2 interface power/clock control bit */ -#define CLKPWR_PCONP_PCSSP2 ((uint32_t)(1<<20)) - -/** The SSP0 interface power/clock control bit */ -#define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21)) - -/** Timer 2 power/clock control bit */ -#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22)) - -/** Timer 3 power/clock control bit */ -#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23)) - -/** UART 2 power/clock control bit */ -#define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24)) - -/** UART 3 power/clock control bit */ -#define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25)) - -/** I2C interface 2 power/clock control bit */ -#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26)) - -/** I2S interface power/clock control bit*/ -#define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27)) - -/** SD card interface power/clock control bit */ -#define CLKPWR_PCONP_PCSDC ((uint32_t)(1<<28)) - -/** GP DMA function power/clock control bit*/ -#define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29)) - -/** Ethernet block power/clock control bit*/ -#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30)) - -/** USB interface power/clock control bit*/ -#define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31)) - -/******************************************************************** -* Power Control for Peripherals Definitions -**********************************************************************/ -#define CLKPWR_RSTCON0_LCD ((uint32_t)(0)) -#define CLKPWR_RSTCON0_TIM0 ((uint32_t)(1)) -#define CLKPWR_RSTCON0_TIM1 ((uint32_t)(2)) -#define CLKPWR_RSTCON0_UART0 ((uint32_t)(3)) -#define CLKPWR_RSTCON0_UART1 ((uint32_t)(4)) -#define CLKPWR_RSTCON0_PWM0 ((uint32_t)(5)) -#define CLKPWR_RSTCON0_PWM1 ((uint32_t)(6)) -#define CLKPWR_RSTCON0_I2C0 ((uint32_t)(7)) -#define CLKPWR_RSTCON0_UART4 ((uint32_t)(8)) -#define CLKPWR_RSTCON0_RTC ((uint32_t)(9)) -#define CLKPWR_RSTCON0_SSP1 ((uint32_t)(10)) -#define CLKPWR_RSTCON0_EMC ((uint32_t)(11)) -#define CLKPWR_RSTCON0_ADC ((uint32_t)(12)) -#define CLKPWR_RSTCON0_CAN1 ((uint32_t)(13)) -#define CLKPWR_RSTCON0_CAN2 ((uint32_t)(14)) -#define CLKPWR_RSTCON0_GPIO ((uint32_t)(15)) -#define CLKPWR_RSTCON0_MCPWM ((uint32_t)(17)) -#define CLKPWR_RSTCON0_QEI ((uint32_t)(18)) -#define CLKPWR_RSTCON0_I2C1 ((uint32_t)(19)) -#define CLKPWR_RSTCON0_SSP2 ((uint32_t)(20)) -#define CLKPWR_RSTCON0_SSP0 ((uint32_t)(21)) -#define CLKPWR_RSTCON0_TIM2 ((uint32_t)(22)) -#define CLKPWR_RSTCON0_TIM3 ((uint32_t)(23)) -#define CLKPWR_RSTCON0_UART2 ((uint32_t)(24)) -#define CLKPWR_RSTCON0_UART3 ((uint32_t)(25)) -#define CLKPWR_RSTCON0_I2C2 ((uint32_t)(26)) -#define CLKPWR_RSTCON0_I2S ((uint32_t)(27)) -#define CLKPWR_RSTCON0_SDC ((uint32_t)(28)) -#define CLKPWR_RSTCON0_GPDMA ((uint32_t)(29)) -#define CLKPWR_RSTCON0_ENET ((uint32_t)(30)) -#define CLKPWR_RSTCON0_USB ((uint32_t)(31)) - -#define CLKPWR_RSTCON1_IOCON ((uint32_t)(32)) -#define CLKPWR_RSTCON1_DAC ((uint32_t)(33)) -#define CLKPWR_RSTCON1_CANACC ((uint32_t)(34)) -/** - * @} - */ - -/* External clock variable from system_LPC407x_8x_177x_8x.h */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */ -extern uint32_t EMCClock; /*!< EMC Clock Frequency */ - -/* External clock variable from lpc_clkpwr.h */ -extern uint32_t USBClock; /*!< USB Frequency */ - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions - * @{ - */ - -void CLKPWR_SetCLKDiv(uint8_t ClkType, uint8_t DivVal); -uint32_t CLKPWR_GetCLK(uint8_t ClkType); -void CLKPWR_ConfigPPWR(uint32_t PPType, FunctionalState NewState); -void CLKPWR_ConfigReset(uint8_t PType, FunctionalState NewState); -void CLKPWR_Sleep(void); -void CLKPWR_DeepSleep(void); -void CLKPWR_PowerDown(void); -void CLKPWR_DeepPowerDown(void); - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __LPC_CLKPWR_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_crc.h b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_crc.h deleted file mode 100644 index acbfbd57bd6..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_crc.h +++ /dev/null @@ -1,110 +0,0 @@ -/********************************************************************** -* $Id$ lpc_crc.h 2011-06-02 -*//** -* @file lpc_crc.h -* @brief Contains all macro definitions and function prototypes -* support for CRC firmware library on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup CRC CRC (Cyclic Redundancy Check) - * @ingroup LPC_CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef __LPC__CRC_H_ -#define __LPC__CRC_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC407x_8x_177x_8x.h" -#include "lpc_types.h" - - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Private macros ------------------------------------------------------------- */ -/** @defgroup CRC_Private_Macros CRC Private Macros - * @{ - */ - -/* -------------------------- BIT DEFINITIONS ----------------------------------- */ -/*********************************************************************//** - * Macro defines for CRC mode register - **********************************************************************/ -#define CRC_BIT_RVS_WR (1<<2) -#define CRC_CMPL_WR (1<<3) -#define CRC_BIT_RVS_SUM (1<<4) -#define CRC_CMPL_SUM (1<<5) - - -/** - * @} - */ -/* Private types ------------------------------------------------------------- */ -typedef enum -{ - CRC_POLY_CRCCCITT = 0, /** CRC CCITT polynomial */ - CRC_POLY_CRC16, /** CRC-16 polynomial */ - CRC_POLY_CRC32 /** CRC-32 polynomial */ -}CRC_Type; - -typedef enum -{ - CRC_WR_8BIT = 1, /** 8-bit write: 1-cycle operation */ - CRC_WR_16BIT = 2, /** 16-bit write: 2-cycle operation */ - CRC_WR_32BIT = 4, /** 32-bit write: 4-cycle operation */ -}CRC_WR_SIZE; - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup CRC_Public_Functions CRC Public Functions - * @{ - */ -void CRC_Init(CRC_Type CRCType); -void CRC_Reset(void); -uint32_t CRC_CalcDataChecksum(uint32_t data, CRC_WR_SIZE SizeType); -uint32_t CRC_CalcBlockChecksum(void *blockdata, uint32_t blocksize, CRC_WR_SIZE SizeType); - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - - -#endif /* __LPC_CRC_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_dac.h b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_dac.h deleted file mode 100644 index 1cb376b3c33..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_dac.h +++ /dev/null @@ -1,165 +0,0 @@ -/********************************************************************** -* $Id$ lpc_dac.h 2011-06-02 -*//** -* @file lpc_dac.h -* @brief Contains all macro definitions and function prototypes -* support for DAC firmware library on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup DAC DAC (Digital-to-Analog Converter) - * @ingroup LPC_CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef __LPC_DAC_H_ -#define __LPC_DAC_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC407x_8x_177x_8x.h" - -#include "lpc_types.h" - - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Public Macros -------------------------------------------------------------- */ -/** @defgroup DAC_Private_Macros DAC Private Macros - * @{ - */ - -/** After the selected settling time after this field is written with a -new VALUE, the voltage on the AOUT pin (with respect to VSSA) -is VALUE/1024 × VREF */ -#define DAC_VALUE(n) ((uint32_t)((n&0x3FF)<<6)) - -/** If this bit = 0: The settling time of the DAC is 1 microsecond max, - * and the maximum current is 700 microAmpere - * If this bit = 1: The settling time of the DAC is 2.5 microsecond - * and the maximum current is 350 microAmpere */ -#define DAC_BIAS_EN ((uint32_t)(1<<16)) - -/** Value to reload interrupt DMA counter */ -#define DAC_CCNT_VALUE(n) ((uint32_t)(n&0xffff)) - -/** DCAR double buffering */ -#define DAC_DBLBUF_ENA ((uint32_t)(1<<1)) - -/** DCAR Time out count enable */ -#define DAC_CNT_ENA ((uint32_t)(1<<2)) - -/** DCAR DMA access */ -#define DAC_DMA_ENA ((uint32_t)(1<<3)) - -/** DCAR DACCTRL mask bit */ -#define DAC_DACCTRL_MASK ((uint32_t)(0x0F)) - -/** Macro to determine if it is valid DAC peripheral */ -#define PARAM_DACx(n) (((uint32_t *)n)==((uint32_t *)LPC_DAC)) - -/** Macro to check DAC current optional parameter */ -#define PARAM_DAC_CURRENT_OPT(OPTION) ((OPTION == DAC_MAX_CURRENT_700uA)\ - ||(OPTION == DAC_MAX_CURRENT_350uA)) -/** - * @} - */ -/* Public Types --------------------------------------------------------------- */ -/** @defgroup DAC_Public_Types DAC Public Types - * @{ - */ - -/** - * @brief Current option in DAC configuration option */ -typedef enum -{ - DAC_MAX_CURRENT_700uA = 0, /*!< The settling time of the DAC is 1 us max, - and the maximum current is 700 uA */ - DAC_MAX_CURRENT_350uA /*!< The settling time of the DAC is 2.5 us - and the maximum current is 350 uA */ -} DAC_CURRENT_OPT; - -/** - * @brief Configuration for DAC converter control register */ -typedef struct -{ - - uint8_t DBLBUF_ENA; /**< - - If 0: Disable DACR double buffering - - - If 1: when bit CNT_ENA, enable DACR double buffering feature - */ - uint8_t CNT_ENA; /*!< - - If 0: Time out counter is disable - - -1: Time out conter is enable - */ - uint8_t DMA_ENA; /*!< - - If 0: DMA access is disable - - - If 1: DMA burst request - */ - uint8_t RESERVED; - -} DAC_CONVERTER_CFG_Type; - -/** - * @} - */ - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup DAC_Public_Functions DAC Public Functions - * @{ - */ - -void DAC_Init(uint8_t DAC_Id); -void DAC_UpdateValue (uint8_t DAC_Id, uint32_t dac_value); -void DAC_SetBias (uint8_t DAC_Id,uint32_t bias); -void DAC_ConfigDAConverterControl (uint8_t DAC_Id,DAC_CONVERTER_CFG_Type *DAC_ConverterConfigStruct); -void DAC_SetDMATimeOut(uint8_t DAC_Id,uint32_t time_out); -uint8_t DAC_IsIntRequested(uint8_t DAC_Id); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __LPC_DAC_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_eeprom.h b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_eeprom.h deleted file mode 100644 index 56acda355ee..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_eeprom.h +++ /dev/null @@ -1,152 +0,0 @@ -/********************************************************************** -* $Id$ lpc_eeprom.h 2011-06-02 -*//** -* @file lpc_eeprom.h -* @brief Contains all macro definitions and function prototypes -* support for EEPROM firmware library on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup EEPROM EEPROM (Electrically Erasable Programmable Read-Only Memory) - * @ingroup LPC_CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef __LPC_EEPROM_H_ -#define __LPC_EEPROM_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC407x_8x_177x_8x.h" -#include "lpc_types.h" - - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Private macros ------------------------------------------------------------- */ -/** @defgroup EEPROM_Private_Macros EEPROM Private Macros - * @{ - */ - -/* -------------------------- BIT DEFINITIONS --------------------------------- */ -/*********************************************************************//** - * Macro defines for EEPROM command register - **********************************************************************/ -#define EEPROM_CMD_8_BIT_READ (0) -#define EEPROM_CMD_16_BIT_READ (1) -#define EEPROM_CMD_32_BIT_READ (2) -#define EEPROM_CMD_8_BIT_WRITE (3) -#define EEPROM_CMD_16_BIT_WRITE (4) -#define EEPROM_CMD_32_BIT_WRITE (5) -#define EEPROM_CMD_ERASE_PRG_PAGE (6) - -#define EEPROM_CMD_RDPREFETCH (1<<3) - -#define EEPROM_PAGE_SIZE 64 -#define EEPROM_PAGE_NUM 63 - -/*********************************************************************//** - * Macro defines for EEPROM address register - **********************************************************************/ -#define EEPROM_PAGE_OFFSET(n) (n&0x3F) -#define EEPROM_PAGE_ADRESS(n) ((n&0x3F)<<6) - -/*********************************************************************//** - * Macro defines for EEPROM write data register - **********************************************************************/ -#define EEPROM_WDATA_8_BIT(n) (n&0x000000FF) -#define EEPROM_WDATA_16_BIT(n) (n&0x0000FFFF) -#define EEPROM_WDATA_32_BIT(n) (n&0xFFFFFFFF) - -/*********************************************************************//** - * Macro defines for EEPROM read data register - **********************************************************************/ -#define EEPROM_RDATA_8_BIT(n) (n&0x000000FF) -#define EEPROM_RDATA_16_BIT(n) (n&0x0000FFFF) -#define EEPROM_RDATA_32_BIT(n) (n&0xFFFFFFFF) - -/*********************************************************************//** - * Macro defines for EEPROM power down register - **********************************************************************/ -#define EEPROM_PWRDWN (1<<0) - -#define EEPROM_ENDOF_RW (26) -#define EEPROM_ENDOF_PROG (28) - -/** - * @} - */ - - -/* Public Types --------------------------------------------------------------- */ -/** @defgroup EEPROM_Public_Types EEPROM Public Types - * @{ - */ - -typedef enum -{ - MODE_8_BIT = 0, - MODE_16_BIT, - MODE_32_BIT -}EEPROM_Mode_Type; - - -/** - * @} - */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup EEPROM_Public_Functions EEPROM Public Functions - * @{ - */ - -void EEPROM_Init(void); -void EEPROM_Write(uint16_t page_offset, uint16_t page_address, void* data, EEPROM_Mode_Type mode, uint32_t size); -void EEPROM_Read(uint16_t page_offset, uint16_t page_address, void* data, EEPROM_Mode_Type mode, uint32_t size); -void EEPROM_Erase(uint16_t address); -void EEPROM_PowerDown(FunctionalState NewState); - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - - -#endif /* __LPC_EEPROM_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_emac.h b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_emac.h deleted file mode 100644 index 3d18f31b45d..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_emac.h +++ /dev/null @@ -1,616 +0,0 @@ -/********************************************************************** -* $Id$ lpc_emac.h 2011-06-02 -*//** -* @file lpc_emac.h -* @brief Contains all macro definitions and function prototypes -* support for Ethernet MAC firmware library on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup EMAC EMAC (Ethernet Media Access Controller) - * @ingroup LPC_CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef __LPC_EMAC_H_ -#define __LPC_EMAC_H_ - -#include "LPC407x_8x_177x_8x.h" -#include "lpc_types.h" - - -#ifdef __cplusplus -extern "C" -{ -#endif - -/** @defgroup EMAC_Private_Macros EMAC Private Macros - * @{ - */ - -/* Ethernet MAC register definitions --------------------------------------------------------------------- */ -/* MAC Configuration Register 1 */ -#define EMAC_MAC1_MASK 0xcf1f /*MAC1 register mask*/ -#define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */ -#define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */ -#define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */ -#define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */ -#define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */ -#define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */ -#define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */ -#define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */ -#define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */ -#define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */ -#define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */ - -/* MAC Configuration Register 2 */ -#define EMAC_MAC2_MASK 0x73ff /*MAC2 register mask*/ -#define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */ -#define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */ -#define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */ -#define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */ -#define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */ -#define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */ -#define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */ -#define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */ -#define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */ -#define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */ -#define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */ -#define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */ -#define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */ - -/* Back-to-Back Inter-Packet-Gap Register */ -/** Programmable field representing the nibble time offset of the minimum possible period - * between the end of any transmitted packet to the beginning of the next */ -#define EMAC_IPGT_BBIPG(n) (n&0x7F) - -/** Recommended value for Full Duplex of Programmable field representing the nibble time - * offset of the minimum possible period between the end of any transmitted packet to the - * beginning of the next */ -#define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15)) - -/** Recommended value for Half Duplex of Programmable field representing the nibble time - * offset of the minimum possible period between the end of any transmitted packet to the - * beginning of the next */ -#define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12)) - -/* Non Back-to-Back Inter-Packet-Gap Register */ -/** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */ -#define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F) - -/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */ -#define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12)) - -/** Programmable field representing the optional carrierSense window referenced in - * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */ -#define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8) - -/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */ -#define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C) - -/* Collision Window/Retry Register */ -/** Programmable field specifying the number of retransmission attempts following a collision before - * aborting the packet due to excessive collisions */ -#define EMAC_CLRT_MAX_RETX(n) (n&0x0F) - -/** Programmable field representing the slot time or collision window during which collisions occur - * in properly configured networks */ -#define EMAC_CLRT_COLL(n) ((n&0x3F)<<8) - -/** Default value for Collision Window / Retry register */ -#define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37))) - -/* Maximum Frame Register */ -/** Represents a maximum receive frame of 1536 octets */ -#define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF) -#define EMAC_MAXF_MAXFRMLEN_DEF (0x6000) - -/* PHY Support Register */ -#define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */ -//#define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */ - -/* Test Register */ -#define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */ -#define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */ -#define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */ - -/* MII Management Configuration Register */ -#define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */ -#define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */ -#define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */ -#define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */ -#define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */ - -/* MII Management Command Register */ -#define EMAC_MCMD_READ 0x00000001 /**< MII Read */ -#define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */ - -#define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */ -#define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */ - -/* MII Management Address Register */ -#define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */ -#define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */ - -/* MII Management Write Data Register */ -#define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */ - -/* MII Management Read Data Register */ -#define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */ - -/* MII Management Indicators Register */ -#define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */ -#define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */ -#define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */ -#define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */ - -/* Station Address 0 Register */ -/* Station Address 1 Register */ -/* Station Address 2 Register */ - - -/* Control register definitions --------------------------------------------------------------------------- */ -/* Command Register */ -#define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */ -#define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */ -#define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */ -#define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */ -#define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */ -#define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */ -#define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */ -#define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */ -#define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */ -#define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */ - -/* Status Register */ -#define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */ -#define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */ - -/* Receive Descriptor Base Address Register */ -// - -/* Receive Status Base Address Register */ -// - -/* Receive Number of Descriptors Register */ -// - -/* Receive Produce Index Register */ -// - -/* Receive Consume Index Register */ -// - -/* Transmit Descriptor Base Address Register */ -// - -/* Transmit Status Base Address Register */ -// - -/* Transmit Number of Descriptors Register */ -// - -/* Transmit Produce Index Register */ -// - -/* Transmit Consume Index Register */ -// - -/* Transmit Status Vector 0 Register */ -#define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */ -#define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */ -#define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */ -#define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */ -#define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */ -#define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */ -#define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */ -#define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */ -#define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */ -#define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */ -#define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */ -#define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */ -#define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */ -#define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */ -#define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */ -#define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */ -#define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */ - -/* Transmit Status Vector 1 Register */ -#define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */ -#define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */ - -/* Receive Status Vector Register */ -#define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */ -#define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */ -#define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */ -#define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */ -#define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */ -#define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */ -#define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */ -#define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */ -#define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */ -#define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */ -#define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */ -#define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */ -#define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */ -#define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */ -#define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */ -#define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */ - -/* Flow Control Counter Register */ -#define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */ -#define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */ - -/* Flow Control Status Register */ -#define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */ - - -/* Receive filter register definitions -------------------------------------------------------- */ -/* Receive Filter Control Register */ -#define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */ -#define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */ -#define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */ -#define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */ -#define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/ -#define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */ -#define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */ -#define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */ - -/* Receive Filter WoL Status/Clear Registers */ -#define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */ -#define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */ -#define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */ -#define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */ -#define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */ -#define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */ -#define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */ -#define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */ -#define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */ - -/* Hash Filter Table LSBs Register */ -// - -/* Hash Filter Table MSBs Register */ -// - - -/* Module control register definitions ---------------------------------------------------- */ -/* Interrupt Status/Enable/Clear/Set Registers */ -#define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */ -#define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */ -#define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */ -#define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */ -#define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */ -#define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */ -#define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */ -#define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */ -#define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */ -#define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */ - -/* Power Down Register */ -#define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */ - - -/* Descriptor and status formats ------------------------------------------------------ */ -/* RX and TX descriptor and status definitions. */ - -/* EMAC Memory Buffer configuration for 16K Ethernet RAM */ -#define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */ -#define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */ -#define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */ -#define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */ - -/* EMAC variables located in 16K Ethernet SRAM */ -#define RX_DESC_BASE LPC_PERI_RAM_BASE -#define RX_STAT_BASE (RX_DESC_BASE + EMAC_NUM_RX_FRAG*8) -#define TX_DESC_BASE (RX_STAT_BASE + EMAC_NUM_RX_FRAG*8) -#define TX_STAT_BASE (TX_DESC_BASE + EMAC_NUM_TX_FRAG*8) -#define RX_BUF_BASE (TX_STAT_BASE + EMAC_NUM_TX_FRAG*4) -#define TX_BUF_BASE (RX_BUF_BASE + EMAC_NUM_RX_FRAG*EMAC_ETH_MAX_FLEN) - -/** - * @brief RX Descriptor structure type definition - */ -#define RX_DESC_PACKET(i) (*(uint32_t *)(RX_DESC_BASE + 8*i)) -#define RX_DESC_CTRL(i) (*(uint32_t *)(RX_DESC_BASE+4 + 8*i)) - -/** - * @brief RX Status structure type definition - */ -#define RX_STAT_INFO(i) (*(uint32_t *)(RX_STAT_BASE + 8*i)) -#define RX_STAT_HASHCRC(i) (*(uint32_t *)(RX_STAT_BASE+4 + 8*i)) - -/** - * @brief TX Descriptor structure type definition - */ -#define TX_DESC_PACKET(i) (*(uint32_t *)(TX_DESC_BASE + 8*i)) -#define TX_DESC_CTRL(i) (*(uint32_t *)(TX_DESC_BASE+4 + 8*i)) - -/** - * @brief TX Status structure type definition - */ -#define TX_STAT_INFO(i) (*(uint32_t *)(TX_STAT_BASE + 4*i)) - - -/** - * @brief TX Data Buffer structure definition - */ -#define RX_BUF(i) (RX_BUF_BASE + EMAC_ETH_MAX_FLEN*i) -#define TX_BUF(i) (TX_BUF_BASE + EMAC_ETH_MAX_FLEN*i) - -/* RX Descriptor Control Word */ -#define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */ -#define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */ - -/* RX Status Hash CRC Word */ -#define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */ -#define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */ - -/* RX Status Information Word */ -#define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */ -#define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */ -#define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */ -#define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */ -#define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */ -#define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */ -#define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */ -#define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */ -#define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */ -#define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */ -#define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */ -#define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */ -#define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */ -#define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */ -#define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */ - -/** RX Status Information word mask */ -#define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \ - EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN) - -/* TX Descriptor Control Word */ -#define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */ -#define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */ -#define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */ -#define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */ -#define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */ -#define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */ -#define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */ - -/* TX Status Information Word */ -#define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */ -#define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */ -#define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */ -#define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */ -#define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */ -#define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */ -#define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */ -#define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */ - - -/* DP83848C PHY definition ------------------------------------------------------------ */ - -/** PHY device reset time out definition */ -#define EMAC_PHY_RESP_TOUT 0x100000UL - -/* ENET Device Revision ID */ -#define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */ - - -/* PHY Basic Mode Control Register (BMCR) bitmap definitions */ -#define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */ -//#define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */ - -#define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */ -#define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */ - -#define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */ -#define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */ - - -#define EMAC_PHY_FULLD_100M (EMAC_PHY_BMCR_SPEED_SEL | EMAC_PHY_BMCR_DUPLEX) // Full Duplex 100Mbit -#define EMAC_PHY_HALFD_100M (EMAC_PHY_BMCR_SPEED_SEL | (~ EMAC_PHY_BMCR_DUPLEX)) // Half Duplex 100Mbit -#define EMAC_PHY_FULLD_10M ((~ EMAC_PHY_BMCR_SPEED_SEL) | EMAC_PHY_BMCR_DUPLEX) // Full Duplex 10Mbit -#define EMAC_PHY_HALFD_10M ((~ EMAC_PHY_BMCR_SPEED_SEL) | (~EMAC_PHY_BMCR_DUPLEX)) // Half Duplex 10MBit -#define EMAC_PHY_AUTO_NEG (EMAC_PHY_BMCR_SPEED_SEL | EMAC_PHY_BMCR_AN) // Select Auto Negotiation - - - -/* EMAC PHY status type definitions */ -#define EMAC_PHY_STAT_LINK (0) /**< Link Status */ -#define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */ -#define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */ - -/* EMAC PHY device Speed definitions */ -#define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */ -#define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */ -#define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */ -#define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */ -#define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */ - -/* EMAC User Buffers*/ -#define EMAC_MAX_FRAME_SIZE (0x600) /* 1536 */ -#define EMAC_MAX_FRAME_NUM (2) - -/* EMAC Error Codes */ -#define EMAC_ALIGN_ERR ( 1 << 0) -#define EMAC_RANGE_ERR ( 1 << 1) -#define EMAC_LENGTH_ERR ( 1 << 2) -#define EMAC_SYMBOL_ERR ( 1 << 3) -#define EMAC_CRC_ERR ( 1 << 4) -#define EMAC_RX_NO_DESC_ERR ( 1 << 5) -#define EMAC_OVERRUN_ERR ( 1 << 6) -#define EMAC_LATE_COLLISION_ERR ( 1 << 7) -#define EMAC_EXCESSIVE_COLLISION_ERR ( 1 << 8) -#define EMAC_EXCESSIVE_DEFER_ERR ( 1 << 9) -#define EMAC_UNDERRUN_ERR ( 1 << 10) -#define EMAC_TX_NO_DESC_ERR ( 1 << 11) -#define EMAC_FILTER_FAILED_ERR ( 1 << 12) - - -/** - * @} - */ - - -/**************************** GLOBAL/PUBLIC TYPES ***************************/ - -/** @defgroup EMAC_Public_Types EMAC Public Types - * @{ - */ - -/** - * @brief TX Data Buffer structure definition - */ -typedef struct { - uint32_t ulDataLen; /**< Data length */ - uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */ -} EMAC_PACKETBUF_Type; - -/** - * @brief PHY Configuration structure definition - */ -typedef struct { - uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following: - - EMAC_MODE_AUTO - - EMAC_MODE_10M_FULL - - EMAC_MODE_10M_HALF - - EMAC_MODE_100M_FULL - - EMAC_MODE_100M_HALF - */ -} EMAC_PHY_CFG_Type; - - -/** EMAC Call back function type definition */ -typedef int32_t (PHY_INIT_FUNC)(EMAC_PHY_CFG_Type* pPhyCfg); -typedef int32_t (PHY_RESET_FUNC)(void); -typedef void (EMAC_FRAME_RECV_FUNC)(uint16_t* pData, uint32_t size); -typedef void (EMAC_TRANSMIT_FINISH_FUNC)(void); -typedef void (EMAC_ERR_RECV_FUNC)(int32_t ulErrCode); -typedef void (EMAC_WAKEUP_FUNC)(void); -typedef void (SOFT_INT_FUNC)(void); - -/** - * @brief EMAC configuration structure definition - */ -typedef struct { - EMAC_PHY_CFG_Type PhyCfg; /* PHY Configuration */ - uint8_t bPhyAddr; /* 5-bit PHY Address field */ - uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes - of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5]) - */ - uint16_t nMaxFrameSize; /* maximum frame length */ - PHY_INIT_FUNC *pfnPHYInit; /* point to the funtion which will be called to initialize PHY */ - PHY_RESET_FUNC *pfnPHYReset; /* point to the function which will be called to reset PHY */ - EMAC_FRAME_RECV_FUNC *pfnFrameReceive; /* point to the function which will be called when a frame is received*/ - EMAC_TRANSMIT_FINISH_FUNC* pfnTransmitFinish; /*point to the function which will be called when transmit finished*/ - EMAC_ERR_RECV_FUNC *pfnErrorReceive; /* point to an array of functions which will be called error occur. */ - /* Errors: - EMAC_ALIGN_ERR - EMAC_RANGE_ERR - EMAC_LENGTH_ERR - EMAC_SYMBOL_ERR - EMAC_CRC_ERR - EMAC_RX_NO_DESC_ERR - EMAC_OVERRUN_ERR - EMAC_LATE_COLLISION_ERR - EMAC_EXCESSIVE_COLLISION_ERR - EMAC_EXCESSIVE_DEFER_ERR - EMAC_UNDERRUN_ERR - EMAC_TX_NO_DESC_ERR - */ - EMAC_WAKEUP_FUNC *pfnWakeup; /* point to the function which will be called when receiving wakeup interrupt */ - SOFT_INT_FUNC *pfnSoftInt; /* point to the function which will be called when the interrupt caused by software occurs */ -} EMAC_CFG_Type; - -/** - * @brief EMAC Buffer status definition - */ -typedef enum { - EMAC_BUFF_EMPTY, /* buffer is empty */ - EMAC_BUFF_PARTIAL_FULL, /* buffer contains some packets */ - EMAC_BUFF_FULL, /* buffer is full */ -} EMAC_BUFF_STATUS; - -/** - * @brief EMAC Buffer Index definition - */ - -typedef enum { - EMAC_TX_BUFF, /* transmit buffer */ - EMAC_RX_BUFF, /* receive buffer */ -} EMAC_BUFF_IDX; - -/** - * @} - */ - - -/** @defgroup EMAC_Public_Functions EMAC Public Functions - * @{ - */ - -/** Init/DeInit */ -int32_t EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct); -void EMAC_DeInit(void); - -/** Send/Receive data */ -void EMAC_TxEnable( void ); -void EMAC_RxEnable( void ); -void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState); -int32_t EMAC_CRCCalc(uint8_t frame_no_fcs[], int32_t frame_len); -void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct); - -/** PHY Setup */ -void EMAC_Write_PHY (uint8_t PhyReg, uint16_t Value); -uint16_t EMAC_Read_PHY (uint8_t PhyReg); -void EMAC_SetFullDuplexMode(uint8_t full_duplex); -void EMAC_SetPHYSpeed(uint8_t mode_100Mbps); - -/** Filter */ -void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState); -FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode); -void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState); -IntStatus EMAC_IntGetStatus(uint32_t ulIntType); -EMAC_BUFF_STATUS EMAC_GetBufferSts(EMAC_BUFF_IDX idx); - - -/** - * @} - */ - - - -#ifdef __cplusplus -} -#endif - -#endif /* __LPC_EMAC_DRIVER_H_ */ - -/** - * @} - */ - diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_emc.h b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_emc.h deleted file mode 100644 index 6bcc18d4768..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_emc.h +++ /dev/null @@ -1,549 +0,0 @@ -/********************************************************************** -* $Id$ lpc_emc.h 2011-06-02 -*//** -* @file lpc_emc.h -* @brief Contains all macro definitions and function prototypes -* support for EMC firmware library on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup EMC EMC (External Memory Controller) - * @ingroup LPC_CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef __LPC_EMC_H_ -#define __LPC_EMC_H_ - -#include "lpc_types.h" -#include "LPC407x_8x_177x_8x.h" - - -/** @defgroup EMC_Private_Macros EMC Private Macros - * @{ - */ - -/*********************************************************************** - * EMC Control Register (EMCControl) - **********************************************************************/ -/* Control register mask */ -#define EMC_Control_MASK ((uint32_t )0x07) -/* Control register EMC: Enable control. */ -#define EMC_Control_E ((uint32_t )(1<<0)) -/* Control register EMC: Address mirror control. */ -#define EMC_Control_M ((uint32_t )(1<<1)) -/* Control register EMC: Low-power mode control. */ -#define EMC_Control_L ((uint32_t )(1<<2)) - -/*********************************************************************** - * EMC Status Register (EMCStatus) - **********************************************************************/ -/* Status register mask */ -#define EMC_Status_MASK ((uint32_t )0x07) -/* Status register EMC: Busy. */ -#define EMC_Status_B ((uint32_t )(1<<0)) -/* Status register EMC: Write buffer status. */ -#define EMC_Status_S ((uint32_t )(1<<1)) -/* Status register EMC: Self-refresh acknowledge.. */ -#define EMC_Status_SA ((uint32_t )(1<<2)) - -/*********************************************************************** - * EMC Configuration register (EMCConfig) - **********************************************************************/ -/* EMC Configuration register : Little Endian. */ -#define EMC_Config_Little_Endian_Mode ((uint32_t )(0<<0)) -/* EMC Configuration register : Big Endian. */ -#define EMC_Config_Big_Endian_Mode ((uint32_t )(1<<0)) -/* EMC Configuration: Endian Mask */ -#define EMC_Config_Endian_Mask (0x01<<0) - -/* EMC Configuration register: CLKOUT ratio 1:1. */ -#define EMC_Config_CCLK_1_1 ((uinr32_t)(0<<8)) -/* EMC Configuration register: CLKOUT ratio 1:1. */ -#define EMC_Config_CCLK_1_2 ((uinr32_t)(1<<8)) - -/* EMC Configuration register mask */ -#define EMC_Config_MASK ((uint32_t)(0x101)) - - -/*********************************************************************** - * Dynamic Memory Control register (EMCDynamicControl) - **********************************************************************/ -/* Dynamic Memory Control register EMC: Dynamic memory clock enable. */ -#define EMC_DYNAMIC_CTRL_MEMCLK_EN_POS (0) -#define EMC_DYNAMIC_CTRL_MEMCLK_EN_BMASK (1<>9) & 0x0F) -#define CARD_STATE_IDLE (0) -#define CARD_STATE_READY (1) -#define CARD_STATE_IDENT (2) -#define CARD_STATE_STBY (3) -#define CARD_STATE_TRAN (4) -#define CARD_STATE_DATA (5) -#define CARD_STATE_RCV (6) -#define CARD_STATE_PRG (7) -#define CARD_STATE_DIS (8) - - -/* CID in R2 reponse (Code length is 136 bits) */ -#define MCI_CID_MANUFACTURER_ID_WPOS (24) //pos in word 0 -#define MCI_CID_MANUFACTURER_ID_WBMASK (0xFF) - -#define MCI_CID_OEMAPPLICATION_ID_WPOS (8) //pos in word 0 -#define MCI_CID_OEMAPPLICATION_ID_WBMASK (0xFFFF) - -#define MCI_CID_PRODUCTNAME_ID_H_WPOS (0) //pos in word 0 -#define MCI_CID_PRODUCTNAME_ID_H_WBMASK (0xFF) - -#define MCI_CID_PRODUCTNAME_ID_L_WPOS (0) //pos in word 1 -#define MCI_CID_PRODUCTNAME_ID_L_WBMASK (0xFFFFFFFF) - -#define MCI_CID_PRODUCTREVISION_ID_WPOS (24) //pos in word 2 -#define MCI_CID_PRODUCTREVISION_ID_WBMASK (0xFF) - -#define MCI_CID_PRODUCTSERIALNUM_ID_H_WPOS (0) //pos in word 2 -#define MCI_CID_PRODUCTSERIALNUM_ID_H_WBMASK (0x00FFFFFF) -#define MCI_CID_PRODUCTSERIALNUM_ID_L_WPOS (24) //pos in word 3 -#define MCI_CID_PRODUCTSERIALNUM_ID_L_WBMASK (0xFF) -#define MCI_CID_PRODUCTSERIALNUM_ID_WBMASK (0xFFFFFFFF) - -#define MCI_CID_RESERVED_ID_WPOS (20) //pos in word 3 -#define MCI_CID_RESERVED_ID_WBMASK (0x1F) - -#define MCI_CID_MANUFACTURINGDATE_ID_WPOS (8) //in word 3 -#define MCI_CID_MANUFACTURINGDATE_ID_WBMASK (0x0FFF) - -#define MCI_CID_CHECKSUM_ID_WPOS (1) //in word 3 -#define MCI_CID_CHECKSUM_ID_WBMASK (0x7F) - -#define MCI_CID_UNUSED_ID_WPOS (0) //in word 3 -#define MCI_CID_UNUSED_ID_WBMASK (0x01) - -/* R6 (Published RCA response) */ -#define RCA_RES_CARD_STATUS_POS (0) -#define RCA_RES_CARD_STATUS_MASK (0xFFFF) - -#define RCA_RES_NEW_PUBLISHED_RCA_POS (16) -#define RCA_RES_NEW_PUBLISHED_RCA_MASK (0xFFFF) - -/* R7 (Card interface condition) */ -#define MCI_CMD8_VOLTAGESUPPLIED_POS (8) -#define MCI_CMD8_VOLTAGESUPPLIED_BMASK (0x0F) -#define MCI_CMD8_VOLATAGESUPPLIED_NOT_DEFINED (0) -#define MCI_CMD8_VOLATAGESUPPLIED_27_36 (1) /*2.7 - 3.6V*/ - -#define MCI_CMD8_CHECKPATTERN_POS (0) -#define MCI_CMD8_CHECKPATTERN_BMASK (0xFF) - - -#define MCI_SLOW_RATE (400000) /* 400KHz */ -#define MCI_NORMAL_RATE (20000000) /* 20MHz */ - -#define SD_1_BIT (0) -#define SD_4_BIT (1) - -#define DATA_TIMER_VALUE_R (MCI_NORMAL_RATE/4) // 250ms -#define DATA_TIMER_VALUE_W (MCI_NORMAL_RATE) // 1000ms - -#define DATA_RW_MAX_LEN (0xFFFF) - -#define EXPECT_NO_RESP (0) -#define EXPECT_SHORT_RESP (1) -#define EXPECT_LONG_RESP (2) - -#define MCI_OUTPUT_MODE_PUSHPULL (0) -#define MCI_OUTPUT_MODE_OPENDRAIN (1) - -#define NOT_ALLOW_CMD_TIMER (0) -#define ALLOW_CMD_TIMER (1) - -#define MCI_DISABLE_CMD_TIMER (1<<8) - -/* For the SD card I tested, the minimum block length is 512 */ -/* For MMC, the restriction is loose, due to the variety of SD and MMC -card support, ideally, the driver should read CSD register to find the -speed and block length for the card, and set them accordingly. */ -/* In this driver example, it will support both MMC and SD cards, it -does read the information by send SEND_CSD to poll the card status, -but, it doesn't configure them accordingly. this is not intended to -support all the SD and MMC card. */ - -/* DATA_BLOCK_LEN table - DATA_BLOCK_LEN Actual Size( BLOCK_LENGTH ) - 11 2048 - 10 1024 - 9 512 - 8 256 - 7 128 - 6 64 - 5 32 - 4 16 - 3 8 - 2 4 - 1 2 -*/ -/* This is the size of the buffer of origin data */ -#define MCI_DMA_SIZE (1000UL) -/* This is the area original data is stored or data to be written to the SD/MMC card. */ -#define MCI_DMA_SRC_ADDR LPC_PERI_RAM_BASE -/* This is the area, after reading from the SD/MMC*/ -#define MCI_DMA_DST_ADDR (MCI_DMA_SRC_ADDR + MCI_DMA_SIZE) - - -/* To simplify the programming, please note that, BLOCK_LENGTH is a multiple -of FIFO_SIZE */ -#define DATA_BLOCK_LEN (9) /* Block size field in DATA_CTRL */ -#define BLOCK_LENGTH (1 << DATA_BLOCK_LEN) - /* for SD card, 128, the size of the flash */ - /* card is 512 * 128 = 64K */ -#define BLOCK_NUM 0x80 -#define FIFO_SIZE 16 - -#define BUS_WIDTH_1BIT 0 -#define BUS_WIDTH_4BITS 10 - -/* MCI Status register bit information */ -#define MCI_CMD_CRC_FAIL (1 << 0) -#define MCI_DATA_CRC_FAIL (1 << 1) -#define MCI_CMD_TIMEOUT (1 << 2) -#define MCI_DATA_TIMEOUT (1 << 3) -#define MCI_TX_UNDERRUN (1 << 4) -#define MCI_RX_OVERRUN (1 << 5) -#define MCI_CMD_RESP_END (1 << 6) -#define MCI_CMD_SENT (1 << 7) -#define MCI_DATA_END (1 << 8) -#define MCI_START_BIT_ERR (1 << 9) -#define MCI_DATA_BLK_END (1 << 10) -#define MCI_CMD_ACTIVE (1 << 11) -#define MCI_TX_ACTIVE (1 << 12) -#define MCI_RX_ACTIVE (1 << 13) -#define MCI_TX_HALF_EMPTY (1 << 14) -#define MCI_RX_HALF_FULL (1 << 15) -#define MCI_TX_FIFO_FULL (1 << 16) -#define MCI_RX_FIFO_FULL (1 << 17) -#define MCI_TX_FIFO_EMPTY (1 << 18) -#define MCI_RX_FIFO_EMPTY (1 << 19) -#define MCI_TX_DATA_AVAIL (1 << 20) -#define MCI_RX_DATA_AVAIL (1 << 21) - - -/*********************************************************************** - * MCI Data control register definitions - **********************************************************************/ -/** Data transfer enable */ -#define MCI_DATACTRL_ENABLE_POS (0) -#define MCI_DATACTRL_ENABLE_MASK (0x01) -#define MCI_DATACTRL_ENABLE (1 << MCI_DATACTRL_ENABLE_POS) -#define MCI_DATACTRL_DISABLE (0 << MCI_DATACTRL_ENABLE_POS) - -/** Data transfer direction */ -#define MCI_DATACTRL_DIR_POS (1) -#define MCI_DATACTRL_DIR_MASK (0x01) -#define MCI_DATACTRL_DIR_FROM_CARD (1 << MCI_DATACTRL_DIR_POS) -#define MCI_DATACTRL_DIR_TO_CARD (0 << MCI_DATACTRL_DIR_POS) - - -/** Data transfer mode */ -#define MCI_DATACTRL_XFER_MODE_POS (2) -#define MCI_DATACTRL_XFER_MODE_MASK (0x01) -#define MCI_DATACTRL_XFER_MODE_STREAM (1 << MCI_DATACTRL_XFER_MODE_POS) -#define MCI_DATACTRL_XFER_MODE_BLOCK (0 << MCI_DATACTRL_XFER_MODE_POS) - -/** Enable DMA */ -#define MCI_DATACTRL_DMA_ENABLE_POS (3) -#define MCI_DATACTRL_DMA_ENABLE_MASK (0x01) -#define MCI_DATACTRL_DMA_ENABLE (1 << MCI_DATACTRL_DMA_ENABLE_POS) -#define MCI_DATACTRL_DMA_DISABLE (0 << MCI_DATACTRL_DMA_ENABLE_POS) - -/** Data block length macro */ -#define MCI_DTATCTRL_BLOCKSIZE(n) _SBF(4, (n & 0xF)) - - -#define CMD_INT_MASK (MCI_CMD_CRC_FAIL | MCI_CMD_TIMEOUT | MCI_CMD_RESP_END \ - | MCI_CMD_SENT | MCI_CMD_ACTIVE) - -#define DATA_ERR_INT_MASK (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_TX_UNDERRUN \ - | MCI_RX_OVERRUN | MCI_START_BIT_ERR) - -#define ACTIVE_INT_MASK ( MCI_TX_ACTIVE | MCI_RX_ACTIVE) - -#define FIFO_INT_MASK (MCI_TX_HALF_EMPTY | MCI_RX_HALF_FULL \ - | MCI_TX_FIFO_FULL | MCI_RX_FIFO_FULL \ - | MCI_TX_FIFO_EMPTY | MCI_RX_FIFO_EMPTY \ - | MCI_DATA_BLK_END ) - -#define FIFO_TX_INT_MASK (MCI_TX_HALF_EMPTY ) -#define FIFO_RX_INT_MASK (MCI_RX_HALF_FULL ) - -#define DATA_END_INT_MASK (MCI_DATA_END | MCI_DATA_BLK_END) - -#define ERR_TX_INT_MASK (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_TX_UNDERRUN | MCI_START_BIT_ERR) -#define ERR_RX_INT_MASK (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_RX_OVERRUN | MCI_START_BIT_ERR) - -/* Error code on the command response. */ -#define INVALID_RESPONSE 0xFFFFFFFF - -/** - * @} - */ - - -/** @defgroup MCI_Public_Types MCI Public Types - * @{ - */ - -typedef enum mci_card_state -{ - MCI_CARDSTATE_IDLE = 0, - MCI_CARDSTATE_READY, - MCI_CARDSTATE_IDENDTIFIED, - MCI_CARDSTATE_STBY, - MCI_CARDSTATE_TRAN, - MCI_CARDSTATE_DATA, - MCI_CARDSTATE_RCV, - MCI_CARDSTATE_PRG, - MCI_CARDSTATE_DIS, -}en_Mci_CardState; - - -typedef enum mci_func_error -{ - MCI_FUNC_OK = 0, - MCI_FUNC_FAILED = -1, - MCI_FUNC_BAD_PARAMETERS = -2, - MCI_FUNC_BUS_NOT_IDLE = -3, - MCI_FUNC_TIMEOUT = -3, - MCI_FUNC_ERR_STATE = -4, - MCI_FUNC_NOT_READY = -5, -}en_Mci_Func_Error; - -typedef enum mci_card_type -{ - MCI_SDHC_SDXC_CARD = 3, - MCI_SDSC_V2_CARD = 2, - MCI_MMC_CARD = 1, - MCI_SDSC_V1_CARD = 0, - MCI_CARD_UNKNOWN = -1, -}en_Mci_CardType; - -typedef struct mci_cid -{ - /** Manufacturer ID */ - uint8_t MID; - /** OEM/Application ID */ - uint16_t OID; - /** Product name 8-bits higher */ - uint8_t PNM_H; - /** Product name 32-bits Lower */ - uint32_t PNM_L; - /** Product revision */ - uint8_t PRV; - /** Product serial number */ - uint32_t PSN; - /** reserved: 4 bit */ - uint8_t reserved; - /** Manufacturing date: 12 bit */ - uint16_t MDT; - /** CRC7 checksum: 7 bit */ - uint8_t CRC; - /** not used, always: 1 bit always 1 */ - uint8_t unused; -} st_Mci_CardId; - -typedef struct cmd_info{ - /** Command ID*/ - uint32_t CmdIndex; - /** Command Argument*/ - uint32_t Argument; - /** Expected response: no response, short response or long response */ - uint32_t ExpectResp; - /** Allow timeout */ - uint32_t AllowTimeout; - /** Command Response Info */ - uint32_t *CmdResp; -} st_Mci_CmdInfo; -/** - * @} - */ - - -/** @defgroup MCI_Public_Functions MCI Public Functions - * @{ - */ - -int32_t MCI_Init(uint8_t powerActiveLevel ); -void MCI_SendCmd( st_Mci_CmdInfo* pCmdIf ); -int32_t MCI_GetCmdResp( uint32_t CmdIndex, uint32_t NeedRespFlag, uint32_t *CmdRespStatus ); -int32_t MCI_CmdResp(st_Mci_CmdInfo *pCmdIf); - -void MCI_Set_MCIClock( uint32_t clockrate ); -int32_t MCI_SetBusWidth( uint32_t width ); -int32_t MCI_Acmd_SendOpCond(uint8_t hcsVal); -int32_t MCI_CardInit( void ); -en_Mci_CardType MCI_GetCardType(void); -int32_t MCI_CardReset( void ); -int32_t MCI_Cmd_SendIfCond(void); -int32_t MCI_GetCID(st_Mci_CardId* cidValue); -int32_t MCI_SetCardAddress( void ); -uint32_t MCI_GetCardAddress(void); -int32_t MCI_GetCSD(uint32_t* csdVal); -int32_t MCI_Cmd_SelectCard( void ); -int32_t MCI_GetCardStatus(int32_t* cardStatus); -uint32_t MCI_GetDataXferEndState(void); -uint32_t MCI_GetXferErrState(void); -int32_t MCI_SetBlockLen( uint32_t blockLength ); -int32_t MCI_Acmd_SendBusWidth( uint32_t buswidth ); -int32_t MCI_Cmd_StopTransmission( void ); - -int32_t MCI_Cmd_WriteBlock(uint32_t blockNum, uint32_t numOfBlock); -int32_t MCI_Cmd_ReadBlock(uint32_t blockNum, uint32_t numOfBlock); - -int32_t MCI_WriteBlock(volatile uint8_t* memblock, uint32_t blockNum, uint32_t numOfBlock); -int32_t MCI_ReadBlock(volatile uint8_t* destBlock, uint32_t blockNum, uint32_t numOfBlock); -#if MCI_DMA_ENABLED -void MCI_DMA_IRQHandler (void); -#endif - -/** - * @} - */ - -#endif /* end __LPC_MCI_H_ */ - -/** - * @} - */ - -/**************************************************************************** -** End Of File -****************************************************************************/ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_mcpwm.h b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_mcpwm.h deleted file mode 100644 index 008c4ed6159..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_mcpwm.h +++ /dev/null @@ -1,348 +0,0 @@ -/********************************************************************** -* $Id$ lpc_mcpwm.h 2011-06-02 -*//** -* @file lpc_mcpwm.h -* @brief Contains all macro definitions and function prototypes -* support for Motor Control PWM firmware library on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup MCPWM MCPWM (Motor Control PWM) - * @ingroup LPC_CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef __LPC_MCPWM_H_ -#define __LPC_MCPWM_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC407x_8x_177x_8x.h" -#include "lpc_types.h" - - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Public Macros -------------------------------------------------------------- */ -/** @defgroup MCPWM_Public_Macros MCPWM Public Macros - * @{ - */ - -/** Edge aligned mode for channel in MCPWM */ -#define MCPWM_CHANNEL_EDGE_MODE ((uint32_t)(0)) - -/** Center aligned mode for channel in MCPWM */ -#define MCPWM_CHANNEL_CENTER_MODE ((uint32_t)(1)) - -/** Polarity of the MCOA and MCOB pins: Passive state is LOW, active state is HIGH */ -#define MCPWM_CHANNEL_PASSIVE_LO ((uint32_t)(0)) -/** Polarity of the MCOA and MCOB pins: Passive state is HIGH, active state is LOW */ -#define MCPWM_CHANNEL_PASSIVE_HI ((uint32_t)(1)) - -/* Output Patent in 3-phase DC mode, the internal MCOA0 signal is routed to any or all of - * the six output pins under the control of the bits in this register */ -#define MCPWM_PATENT_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */ -#define MCPWM_PATENT_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */ -#define MCPWM_PATENT_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */ -#define MCPWM_PATENT_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */ -#define MCPWM_PATENT_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */ -#define MCPWM_PATENT_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */ - -/* Interrupt type in MCPWM */ -/** Limit interrupt for channel (0) */ -#define MCPWM_INTFLAG_LIM0 MCPWM_INT_ILIM(0) -/** Match interrupt for channel (0) */ -#define MCPWM_INTFLAG_MAT0 MCPWM_INT_IMAT(0) -/** Capture interrupt for channel (0) */ -#define MCPWM_INTFLAG_CAP0 MCPWM_INT_ICAP(0) - -/** Limit interrupt for channel (1) */ -#define MCPWM_INTFLAG_LIM1 MCPWM_INT_ILIM(1) -/** Match interrupt for channel (1) */ -#define MCPWM_INTFLAG_MAT1 MCPWM_INT_IMAT(1) -/** Capture interrupt for channel (1) */ -#define MCPWM_INTFLAG_CAP1 MCPWM_INT_ICAP(1) - -/** Limit interrupt for channel (2) */ -#define MCPWM_INTFLAG_LIM2 MCPWM_INT_ILIM(2) -/** Match interrupt for channel (2) */ -#define MCPWM_INTFLAG_MAT2 MCPWM_INT_IMAT(2) -/** Capture interrupt for channel (2) */ -#define MCPWM_INTFLAG_CAP2 MCPWM_INT_ICAP(2) - -/** Fast abort interrupt */ -#define MCPWM_INTFLAG_ABORT MCPWM_INT_ABORT - -/** - * @} - */ - -/* Private Macros ------------------------------------------------------------- */ -/** @defgroup MCPWM_Private_Macros MCPWM Private Macros - * @{ - */ - -/*********************************************************************//** - * Macro defines for MCPWM Control register - **********************************************************************/ -/* MCPWM Control register, these macro definitions below can be applied for these - * register type: - * - MCPWM Control read address - * - MCPWM Control set address - * - MCPWM Control clear address - */ -/** Stops/starts timer channel n */ -#define MCPWM_CON_RUN(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*8)+0))) : (0)) -/** Edge/center aligned operation for channel n */ -#define MCPWM_CON_CENTER(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*8)+1))) : (0)) -/** Select polarity of the MCOAn and MCOBn pin */ -#define MCPWM_CON_POLAR(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*8)+2))) : (0)) -/** Control the dead-time feature for channel n */ -#define MCPWM_CON_DTE(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*8)+3))) : (0)) -/** Enable/Disable update of functional register for channel n */ -#define MCPWM_CON_DISUP(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*8)+4))) : (0)) - -/** Control the polarity for all 3 channels */ -#define MCPWM_CON_INVBDC ((uint32_t)((uint32_t)1<<29)) -/** 3-phase AC mode select */ -#define MCPWM_CON_ACMODE ((uint32_t)((uint32_t)1<<30)) -/** 3-phase DC mode select */ -#define MCPWM_CON_DCMODE ((uint32_t)((uint32_t)1<<31)) - -/*********************************************************************//** - * Macro defines for MCPWM Capture Control register - **********************************************************************/ -/* Capture Control register, these macro definitions below can be applied for these - * register type: - * - MCPWM Capture Control read address - * - MCPWM Capture Control set address - * - MCPWM Capture control clear address - */ -/** Enables/Disable channel (cap) capture event on a rising edge on MCI(mci) */ -#define MCPWM_CAPCON_CAPMCI_RE(cap,mci) (((cap < MCPWM_MAX_CHANNEL)&&(mci < MCPWM_MAX_CHANNEL)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+0))) : (0)) -/** Enables/Disable channel (cap) capture event on a falling edge on MCI(mci) */ -#define MCPWM_CAPCON_CAPMCI_FE(cap,mci) (((cap < MCPWM_MAX_CHANNEL)&&(mci < MCPWM_MAX_CHANNEL)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+1))) : (0)) -/** TC(n) is reset by channel (n) capture event */ -#define MCPWM_CAPCON_RT(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<(18+(n)))) : (0)) -/** Hardware noise filter: channel (n) capture events are delayed */ -#define MCPWM_CAPCON_HNFCAP(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<(21+(n)))) : (0)) - -/*********************************************************************//** - * Macro defines for MCPWM Interrupt register - **********************************************************************/ -/* Interrupt registers, these macro definitions below can be applied for these - * register type: - * - MCPWM Interrupt Enable read address - * - MCPWM Interrupt Enable set address - * - MCPWM Interrupt Enable clear address - * - MCPWM Interrupt Flags read address - * - MCPWM Interrupt Flags set address - * - MCPWM Interrupt Flags clear address - */ -/** Limit interrupt for channel (n) */ -#define MCPWM_INT_ILIM(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*4)+0))) : (0)) -/** Match interrupt for channel (n) */ -#define MCPWM_INT_IMAT(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*4)+1))) : (0)) -/** Capture interrupt for channel (n) */ -#define MCPWM_INT_ICAP(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*4)+2))) : (0)) - -/** Fast abort interrupt */ -#define MCPWM_INT_ABORT ((uint32_t)(1<<15)) - -/*********************************************************************//** - * Macro defines for MCPWM Count Control register - **********************************************************************/ -/* MCPWM Count Control register, these macro definitions below can be applied for these - * register type: - * - MCPWM Count Control read address - * - MCPWM Count Control set address - * - MCPWM Count Control clear address - */ -/** Counter(tc) advances on a rising edge on MCI(mci) pin */ -#define MCPWM_CNTCON_TCMCI_RE(tc,mci) (((tc < MCPWM_MAX_CHANNEL)&&(mci < MCPWM_MAX_CHANNEL)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+0))) : (0)) -/** Counter(cnt) advances on a falling edge on MCI(mci) pin */ -#define MCPWM_CNTCON_TCMCI_FE(tc,mci) (((tc < MCPWM_MAX_CHANNEL)&&(mci < MCPWM_MAX_CHANNEL)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+1))) : (0)) -/** Channel (n) is in counter mode */ -#define MCPWM_CNTCON_CNTR(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<(29+n))) : (0)) - -/*********************************************************************//** - * Macro defines for MCPWM Dead-time register - **********************************************************************/ -/** Dead time value x for channel n */ -#define MCPWM_DT(n,x) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)((x&0x3FF)<<(n*10))) : (0)) - -/*********************************************************************//** - * Macro defines for MCPWM Communication Pattern register - **********************************************************************/ -#define MCPWM_CP_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */ -#define MCPWM_CP_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */ -#define MCPWM_CP_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */ -#define MCPWM_CP_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */ -#define MCPWM_CP_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */ -#define MCPWM_CP_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */ - -/*********************************************************************//** - * Macro defines for MCPWM Capture clear address register - **********************************************************************/ -/** Clear the MCCAP (n) register */ -#define MCPWM_CAPCLR_CAP(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<>8)&0x07) -#define RTC_ER_EV2_COUNTER(n) ((n>>16)&0x07) - -/********************************************************************** -* Event Monitor/Recorder TimeStamp register -**********************************************************************/ -#define RTC_ER_TIMESTAMP_SEC(n) (n&0x3F) -#define RTC_ER_TIMESTAMP_MIN(n) ((n>>6)&0x3F) -#define RTC_ER_TIMESTAMP_HOUR(n) ((n>>12)&0x1F) -#define RTC_ER_TIMESTAMP_DOY(n) ((n>>17)&0x1FF) - -/** - * @} - */ - - -/* Public Types --------------------------------------------------------------- */ -/** @defgroup RTC_Public_Types RTC Public Types - * @{ - */ - -/** @brief Time structure definitions for easy manipulate the data */ -typedef struct -{ - /** Seconds Register */ - uint32_t SEC; - /** Minutes Register */ - uint32_t MIN; - /** Hours Register */ - uint32_t HOUR; - /** Day of Month Register */ - uint32_t DOM; - /** Day of Week Register */ - uint32_t DOW; - /** Day of Year Register */ - uint32_t DOY; - /** Months Register */ - uint32_t MONTH; - /** Years Register */ - uint32_t YEAR; -} RTC_TIME_Type; - -/** @brief RTC interrupt source */ -typedef enum -{ - /** Counter Increment Interrupt */ - RTC_INT_COUNTER_INCREASE = RTC_IRL_RTCCIF, - /** The alarm interrupt */ - RTC_INT_ALARM = RTC_IRL_RTCALF, -} RTC_INT_OPT; - - -/** @brief RTC time type option */ -typedef enum -{ - /** Second */ - RTC_TIMETYPE_SECOND = 0, - /** Month */ - RTC_TIMETYPE_MINUTE = 1, - /** Hour */ - RTC_TIMETYPE_HOUR = 2, - /** Day of week */ - RTC_TIMETYPE_DAYOFWEEK = 3, - /** Day of month */ - RTC_TIMETYPE_DAYOFMONTH = 4, - /** Day of year */ - RTC_TIMETYPE_DAYOFYEAR = 5, - /** Month */ - RTC_TIMETYPE_MONTH = 6, - /** Year */ - RTC_TIMETYPE_YEAR = 7, -} RTC_TIMETYPE_Num; - -/** @brief Event Monitor/Recording Input Channel configuration */ -typedef struct -{ - Bool EventOnPosEdge; // Event occurs on positive edge on the channel - Bool IntWake; // Create interrupt and wake-up request if there is an event - Bool GPClear; // Clear GP registers of RTC if there is an event. -} RTC_ER_CHANNEL_Init_Type; - -/** @brief Event Monitor/Recording configuration */ -typedef struct -{ - RTC_ER_CHANNEL_Init_Type InputChannel[RTC_ER_INPUT_CHANNEL_NUM]; - uint32_t Clk; // Sample clock on input channel. (Hz) -} RTC_ER_CONFIG_Type; - -/** @brief Event Monitor/Recording TimeStamp Type */ -typedef struct -{ - /** Seconds Register */ - uint32_t SEC; - /** Minutes Register */ - uint32_t MIN; - /** Hours Register */ - uint32_t HOUR; - /** Day of Year Register */ - uint32_t DOY; -} RTC_ER_TIMESTAMP_Type; - - -/** - * @} - */ - - - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup RTC_Public_Functions RTC Public Functions - * @{ - */ - -void RTC_Init (LPC_RTC_TypeDef *RTCx); -void RTC_DeInit(LPC_RTC_TypeDef *RTCx); -void RTC_ResetClockTickCounter(LPC_RTC_TypeDef *RTCx); -void RTC_Cmd (LPC_RTC_TypeDef *RTCx, FunctionalState NewState); -void RTC_CntIncrIntConfig (LPC_RTC_TypeDef *RTCx, uint32_t CntIncrIntType, \ - FunctionalState NewState); -void RTC_AlarmIntConfig (LPC_RTC_TypeDef *RTCx, uint32_t AlarmTimeType, \ - FunctionalState NewState); -void RTC_SetTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype, uint32_t TimeValue); -uint32_t RTC_GetTime(LPC_RTC_TypeDef *RTCx, uint32_t Timetype); -void RTC_SetFullTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime); -void RTC_GetFullTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime); -void RTC_SetAlarmTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype, uint32_t ALValue); -uint32_t RTC_GetAlarmTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype); -void RTC_SetFullAlarmTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime); -void RTC_GetFullAlarmTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime); -IntStatus RTC_GetIntPending (LPC_RTC_TypeDef *RTCx, uint32_t IntType); -void RTC_ClearIntPending (LPC_RTC_TypeDef *RTCx, uint32_t IntType); -void RTC_CalibCounterCmd(LPC_RTC_TypeDef *RTCx, FunctionalState NewState); -void RTC_CalibConfig(LPC_RTC_TypeDef *RTCx, uint32_t CalibValue, uint8_t CalibDir); -void RTC_WriteGPREG (LPC_RTC_TypeDef *RTCx, uint8_t Channel, uint32_t Value); -uint32_t RTC_ReadGPREG (LPC_RTC_TypeDef *RTCx, uint8_t Channel); - -void RTC_ER_InitConfigStruct(RTC_ER_CONFIG_Type* pConfig); -Status RTC_ER_Init(RTC_ER_CONFIG_Type* pConfig); -Status RTC_ER_Cmd(uint8_t channel, FunctionalState state); -uint8_t RTC_ER_GetEventCount(uint8_t channel); -uint32_t RTC_ER_GetStatus(void); -Bool RTC_ER_WakupReqPending(void); -Bool RTC_ER_GPCleared(void); -Status RTC_ER_GetFirstTimeStamp(uint8_t channel, RTC_ER_TIMESTAMP_Type* pTimeStamp); -Status RTC_ER_GetLastTimeStamp(uint8_t channel, RTC_ER_TIMESTAMP_Type* pTimeStamp); -void RTC_ER_ClearStatus(uint32_t status); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __LPC_RTC_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_spifi_rom_api.h b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_spifi_rom_api.h deleted file mode 100644 index 1dec3f644c8..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_spifi_rom_api.h +++ /dev/null @@ -1,248 +0,0 @@ -/*********************************************************************** -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -#ifndef SPIFI_ROM_API_H -#define SPIFI_ROM_API_H - -#include -/* define the symbol TESTING in the environment if test output desired */ - -/* maintain LONGEST_PROT >= the length (in bytes) of the largest - protection block of any serial flash that this driver handles */ -#define LONGEST_PROT 68 - -typedef uint8_t uc; - -#ifndef NULL -#define NULL ((void *)0) -#endif - -/* protection/sector descriptors */ -typedef struct { - uint32_t base; - uc flags; - int8_t log2; - uint16_t rept; -} protEnt; -/* bits in the flags byte */ -enum {RWPROT=1}; - -/* overall data structure includes # sectors, length of protection reg, - array of descriptors -typedef struct { - uint16_t sectors; - uint16_t protBytes; - protEnt *entries; -} protDesc; */ - -typedef union { - uint16_t hw; - uc byte[2]; -}stat_t; -/* the object that init returns, and other routines use as an operand */ -typedef struct { - uint32_t base, regbase, devSize, memSize; - uc mfger, devType, devID, busy; - stat_t stat; - uint16_t reserved; - uint16_t set_prot, write_prot; - uint32_t mem_cmd, prog_cmd; - uint16_t sectors, protBytes; - uint32_t opts, errCheck; - uc erase_shifts[4], erase_ops[4]; - protEnt *protEnts; - char prot[LONGEST_PROT]; -} SPIFIobj; - -/* operands of program and erase */ -typedef struct { - char *dest; - uint32_t length; - char *scratch; - int32_t protect; - uint32_t options; -} SPIFIopers; - -/* instruction classes for wait_busy */ -typedef enum {stat_inst, block_erase, prog_inst, chip_erase} inst_type; - -/* bits in options operands (MODE3, RCVCLK, and FULLCLK - have the same relationship as in the Control register) */ -#define S_MODE3 1 -#define S_MODE0 0 -#define S_MINIMAL 2 -#define S_MAXIMAL 0 -#define S_FORCE_ERASE 4 -#define S_ERASE_NOT_REQD 8 -#define S_CALLER_ERASE 8 -#define S_ERASE_AS_REQD 0 -#define S_VERIFY_PROG 0x10 -#define S_VERIFY_ERASE 0x20 -#define S_NO_VERIFY 0 -#define S_RCVCLK 0x80 -#define S_INTCLK 0 -#define S_FULLCLK 0x40 -#define S_HALFCLK 0 -#define S_DUAL 0x100 -#define S_CALLER_PROT 0x200 -#define S_DRIVER_PROT 0 - -/* the following values in the first post-address memory command byte work - for all known quad devices that support "no opcode" operation */ -#define NO_OPCODE_FOLLOWS 0xA5 -#define OPCODE_FOLLOWS 0xFF - -/* basic SPI commands for serial flash */ -#define BASE_READ_CMD (CMD_RD<opts (mostly for setMulti) */ -/* used by Winbond: send 0xA3 command so hardware can read faster */ -#define OPT_SEND_A3 1 -/* used by SST: send 0x38 command to enable quad and allow full command set */ -#define OPT_SEND_38 2 -/* used by Winbond and others: read status reg 2, check it, - if necessary write it back with Quad Enable set */ -#define OPT_35_OR02_01 4 -/* used by Atmel: read Configuration register, if necessary set Quad Enable */ -#define OPT_3F_OR80_3E 8 -/* used by Numonyx to set all-quad mode: only for parts that include RSTQIO */ -#define OPT_65_CLR_C0_61 0x10 -/* used by Numonyx: send 0x81 command to write Volatile Configuration Register - to set # dummy bytes and allow XIP mode */ -#define OPT_81 0x20 -/* set for devices without full device erase command (Numonyx type 0x40) */ -#define OPT_NO_DEV_ERASE 0x40 -/* used by Macronix: status reg 2 includes selection between write-protect - in status reg and command-based */ -#define OPT_WPSEL 0x80 -/* set when protection data has been read into the SPIFI object */ -#define OPT_PROT_READ 0x100 -/* set if device needs 4-byte address (and maybe 0x4B command = use 4-byte address) */ -#define OPT_4BAD 0x200 -/* set if setMulti should set the Dual bit in Control reg */ -#define OPT_DUAL 0x400 -/* send "# dummy bits" in C0 command to Winbond */ -#define OPT_C0 0x800 -/* set QE for Chingis */ -#define OPT_05_OR40_01 0x1000 -/* write status does not go busy */ -#define OPT_01_NO_BUSY 0x2000 -/* protection mode bits moved from protMode byte to opts Fri May 13 2011 */ -#define OPT_PROT_STAT 0x4000 -#define OPT_PROT_REG 0x8000 -#define OPT_PROT_CMD3 0x10000 -#define OPT_PROT_CMDE 0x20000 -#define OPT_PROT_MASK 0x3C000 - -#define OPT_ALL_QUAD 0x40000 - -#ifndef OMIT_ROM_TABLE -/* interface to ROM API */ -typedef struct { - int32_t (*spifi_init) (SPIFIobj *obj, uint32_t csHigh, uint32_t options, - uint32_t mhz); - int32_t (*spifi_program) (SPIFIobj *obj, char *source, SPIFIopers *opers); - int32_t (*spifi_erase) (SPIFIobj *obj, SPIFIopers *opers); - /* mode switching */ - void (*cancel_mem_mode)(SPIFIobj *obj); - void (*set_mem_mode) (SPIFIobj *obj); - - /* mid level functions */ - int32_t (*checkAd) (SPIFIobj *obj, SPIFIopers *opers); - int32_t (*setProt) (SPIFIobj *obj, SPIFIopers *opers, char *change, - char *saveProt); - int32_t (*check_block) (SPIFIobj *obj, char *source, SPIFIopers *opers, - uint32_t check_program); - int32_t (*send_erase_cmd) (SPIFIobj *obj, uint8_t op, uint32_t addr); - uint32_t (*ck_erase) (SPIFIobj *obj, uint32_t *addr, uint32_t length); - int32_t (*prog_block) (SPIFIobj *obj, char *source, SPIFIopers *opers, - uint32_t *left_in_page); - uint32_t (*ck_prog) (SPIFIobj *obj, char *source, char *dest, uint32_t length); - - /* low level functions */ - void(*setSize) (SPIFIobj *obj, int32_t value); - int32_t (*setDev) (SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd, - uint32_t prog_cmd); - uint32_t (*cmd) (uc op, uc addrLen, uc intLen, uint16_t len); - uint32_t (*readAd) (SPIFIobj *obj, uint32_t cmd, uint32_t addr); - void (*send04) (SPIFIobj *obj, uc op, uc len, uint32_t value); - void (*wren_sendAd) (SPIFIobj *obj, uint32_t cmd, uint32_t addr, uint32_t value); - int32_t (*write_stat) (SPIFIobj *obj, uc len, uint16_t value); - int32_t (*wait_busy) (SPIFIobj *obj, uc prog_or_erase); -} SPIFI_RTNS; - -#define define_spifi_romPtr(name) const SPIFI_RTNS *name=*((SPIFI_RTNS **)SPIFI_ROM_PTR) -#endif /* OMIT_ROM_TABLE */ - -#ifdef USE_SPIFI_LIB -extern SPIFI_RTNS spifi_table; -#endif /* USE_SPIFI_LIB */ - -/* example of using this interface: -#include "spifi_rom_api.h" -#define CSHIGH 4 -#define SPIFI_MHZ 80 -#define source_data_ad (char *)1234 - - int32_t rc; - SPIFIopers opers; - - define_spifi_romPtr(spifi); - SPIFIobj *obj = malloc(sizeof(SPIFIobj)); - if (!obj) { can't allocate memory } - - rc = spifi->spifi_init (obj, CSHIGH, S_FULLCLK+S_RCVCLK, SPIFI_MHZ); - if (rc) { investigate init error rc } - printf ("the serial flash contains %d bytes\n", obj->devSize); - - opers.dest = where_to_program; - opers.length = how_many_bytes; - opers.scratch = NULL; // unprogrammed data is not saved/restored - opers.protect = -1; // save & restore protection - opers.options = S_VERIFY_PROG; - - rc = spifi->spifi_program (obj, source_data_ad, &opers); - if (rc) { investigate program error rc } -*/ - -/* these are for normal users, including boot code */ -int32_t spifi_init (SPIFIobj *obj, uint32_t csHigh, uint32_t options, uint32_t mhz); -int32_t spifi_program (SPIFIobj *obj, char *source, SPIFIopers *opers); -int32_t spifi_erase (SPIFIobj *obj, SPIFIopers *opers); - -/* these are used by the manufacturer-specific init functions */ -void setSize (SPIFIobj *obj, int32_t value); -int32_t setDev (SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd, uint32_t prog_cmd); -uint32_t read04(SPIFIobj *obj, uc op, uc len); -int32_t write_stat (SPIFIobj *obj, uc len, uint16_t value); -void setProtEnts(SPIFIobj *obj, const protEnt *p, uint32_t protTabLen); - -/* needs to be defined for each platform */ -void pullMISO(int high); - -#ifdef TESTING -/* used by testing code */ -unsigned short getProtBytes (SPIFIobj *obj, unsigned short *sectors); -/* predeclare a debug routine */ -void wait_sample (volatile unsigned *addr, unsigned mask, unsigned value); -#endif - -#endif /* SPIFI_ROM_API_H */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_ssp.h b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_ssp.h deleted file mode 100644 index 65e663d5bcf..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_ssp.h +++ /dev/null @@ -1,422 +0,0 @@ -/********************************************************************** -* $Id$ lpc_ssp.h 2011-06-02 -*//** -* @file lpc_ssp.h -* @brief Contains all macro definitions and function prototypes -* support for SSP firmware library on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup SSP SSP (Synchronous Serial Port) - * @ingroup LPC_CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef __LPC_SSP_H_ -#define __LPC_SSP_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC407x_8x_177x_8x.h" -#include "lpc_types.h" - - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Public Macros -------------------------------------------------------------- */ -/** @defgroup SSP_Public_Macros SSP Public Macros - * @{ - */ - -/*********************************************************************//** - * SSP configuration parameter defines - **********************************************************************/ -/** Clock phase control bit */ -#define SSP_CPHA_FIRST ((uint32_t)(0)) -#define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND - - -/** Clock polarity control bit */ -/* There's no bug here!!! - * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames. - * That means the active clock is in HI state. - * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock - * high between frames. That means the active clock is in LO state. - */ -#define SSP_CPOL_HI ((uint32_t)(0)) -#define SSP_CPOL_LO SSP_CR0_CPOL_HI - -/** SSP master mode enable */ -#define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN -#define SSP_MASTER_MODE ((uint32_t)(0)) - -/** SSP data bit number defines */ -#define SSP_DATABIT_4 SSP_CR0_DSS(4) /*!< Databit number = 4 */ -#define SSP_DATABIT_5 SSP_CR0_DSS(5) /*!< Databit number = 5 */ -#define SSP_DATABIT_6 SSP_CR0_DSS(6) /*!< Databit number = 6 */ -#define SSP_DATABIT_7 SSP_CR0_DSS(7) /*!< Databit number = 7 */ -#define SSP_DATABIT_8 SSP_CR0_DSS(8) /*!< Databit number = 8 */ -#define SSP_DATABIT_9 SSP_CR0_DSS(9) /*!< Databit number = 9 */ -#define SSP_DATABIT_10 SSP_CR0_DSS(10) /*!< Databit number = 10 */ -#define SSP_DATABIT_11 SSP_CR0_DSS(11) /*!< Databit number = 11 */ -#define SSP_DATABIT_12 SSP_CR0_DSS(12) /*!< Databit number = 12 */ -#define SSP_DATABIT_13 SSP_CR0_DSS(13) /*!< Databit number = 13 */ -#define SSP_DATABIT_14 SSP_CR0_DSS(14) /*!< Databit number = 14 */ -#define SSP_DATABIT_15 SSP_CR0_DSS(15) /*!< Databit number = 15 */ -#define SSP_DATABIT_16 SSP_CR0_DSS(16) /*!< Databit number = 16 */ - -/** SSP Frame Format definition */ -/** Motorola SPI mode */ -#define SSP_FRAME_SPI SSP_CR0_FRF_SPI -/** TI synchronous serial mode */ -#define SSP_FRAME_TI SSP_CR0_FRF_TI -/** National Micro-wire mode */ -#define SSP_FRAME_MICROWIRE SSP_CR0_FRF_MICROWIRE - -/*********************************************************************//** - * SSP Status defines - **********************************************************************/ -/** SSP status TX FIFO Empty bit */ -#define SSP_STAT_TXFIFO_EMPTY SSP_SR_TFE -/** SSP status TX FIFO not full bit */ -#define SSP_STAT_TXFIFO_NOTFULL SSP_SR_TNF -/** SSP status RX FIFO not empty bit */ -#define SSP_STAT_RXFIFO_NOTEMPTY SSP_SR_RNE -/** SSP status RX FIFO full bit */ -#define SSP_STAT_RXFIFO_FULL SSP_SR_RFF -/** SSP status SSP Busy bit */ -#define SSP_STAT_BUSY SSP_SR_BSY - -/*********************************************************************//** - * SSP Interrupt Configuration defines - **********************************************************************/ -/** Receive Overrun */ -#define SSP_INTCFG_ROR SSP_IMSC_ROR -/** Receive TimeOut */ -#define SSP_INTCFG_RT SSP_IMSC_RT -/** Rx FIFO is at least half full */ -#define SSP_INTCFG_RX SSP_IMSC_RX -/** Tx FIFO is at least half empty */ -#define SSP_INTCFG_TX SSP_IMSC_TX - -/*********************************************************************//** - * SSP Configured Interrupt Status defines - **********************************************************************/ -/** Receive Overrun */ -#define SSP_INTSTAT_ROR SSP_MIS_ROR -/** Receive TimeOut */ -#define SSP_INTSTAT_RT SSP_MIS_RT -/** Rx FIFO is at least half full */ -#define SSP_INTSTAT_RX SSP_MIS_RX -/** Tx FIFO is at least half empty */ -#define SSP_INTSTAT_TX SSP_MIS_TX - -/*********************************************************************//** - * SSP Raw Interrupt Status defines - **********************************************************************/ -/** Receive Overrun */ -#define SSP_INTSTAT_RAW_ROR SSP_RIS_ROR -/** Receive TimeOut */ -#define SSP_INTSTAT_RAW_RT SSP_RIS_RT -/** Rx FIFO is at least half full */ -#define SSP_INTSTAT_RAW_RX SSP_RIS_RX -/** Tx FIFO is at least half empty */ -#define SSP_INTSTAT_RAW_TX SSP_RIS_TX - -/*********************************************************************//** - * SSP Interrupt Clear defines - **********************************************************************/ -/** Writing a 1 to this bit clears the "frame was received when - * RxFIFO was full" interrupt */ -#define SSP_INTCLR_ROR SSP_ICR_ROR -/** Writing a 1 to this bit clears the "Rx FIFO was not empty and - * has not been read for a timeout period" interrupt */ -#define SSP_INTCLR_RT SSP_ICR_RT - -/*********************************************************************//** - * SSP DMA defines - **********************************************************************/ -/** SSP bit for enabling RX DMA */ -#define SSP_DMA_RX SSP_DMA_RXDMA_EN -/** SSP bit for enabling TX DMA */ -#define SSP_DMA_TX SSP_DMA_TXDMA_EN - -/* SSP Status Implementation definitions */ -#define SSP_STAT_DONE (1UL<<8) /**< Done */ -#define SSP_STAT_ERROR (1UL<<9) /**< Error */ - -/** - * @} - */ - -/* Private Macros ------------------------------------------------------------- */ -/** @defgroup SSP_Private_Macros SSP Private Macros - * @{ - */ - -/* --------------------- BIT DEFINITIONS -------------------------------------- */ -/*********************************************************************//** - * Macro defines for CR0 register - **********************************************************************/ -/** SSP data size select, must be 4 bits to 16 bits */ -#define SSP_CR0_DSS(n) ((uint32_t)((n-1)&0xF)) -/** SSP control 0 Motorola SPI mode */ -#define SSP_CR0_FRF_SPI ((uint32_t)(0<<4)) -/** SSP control 0 TI synchronous serial mode */ -#define SSP_CR0_FRF_TI ((uint32_t)(1<<4)) -/** SSP control 0 National Micro-wire mode */ -#define SSP_CR0_FRF_MICROWIRE ((uint32_t)(2<<4)) -/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the - bus clock high between frames, (0) = low */ -#define SSP_CR0_CPOL_HI ((uint32_t)(1<<6)) -/** SPI clock out phase bit (used in SPI mode only), (1) = captures data - on the second clock transition of the frame, (0) = first */ -#define SSP_CR0_CPHA_SECOND ((uint32_t)(1<<7)) -/** SSP serial clock rate value load macro, divider rate is - PERIPH_CLK / (cpsr * (SCR + 1)) */ -#define SSP_CR0_SCR(n) ((uint32_t)((n&0xFF)<<8)) -/** SSP CR0 bit mask */ -#define SSP_CR0_BITMASK ((uint32_t)(0xFFFF)) - -/*********************************************************************//** - * Macro defines for CR1 register - **********************************************************************/ -/** SSP control 1 loopback mode enable bit */ -#define SSP_CR1_LBM_EN ((uint32_t)(1<<0)) -/** SSP control 1 enable bit */ -#define SSP_CR1_SSP_EN ((uint32_t)(1<<1)) -/** SSP control 1 slave enable */ -#define SSP_CR1_SLAVE_EN ((uint32_t)(1<<2)) -/** SSP control 1 slave out disable bit, disables transmit line in slave - mode */ -#define SSP_CR1_SO_DISABLE ((uint32_t)(1<<3)) -/** SSP CR1 bit mask */ -#define SSP_CR1_BITMASK ((uint32_t)(0x0F)) - -/*********************************************************************//** - * Macro defines for DR register - **********************************************************************/ -/** SSP data bit mask */ -#define SSP_DR_BITMASK(n) ((n)&0xFFFF) - -/*********************************************************************//** - * Macro defines for SR register - **********************************************************************/ -/** SSP status TX FIFO Empty bit */ -#define SSP_SR_TFE ((uint32_t)(1<<0)) -/** SSP status TX FIFO not full bit */ -#define SSP_SR_TNF ((uint32_t)(1<<1)) -/** SSP status RX FIFO not empty bit */ -#define SSP_SR_RNE ((uint32_t)(1<<2)) -/** SSP status RX FIFO full bit */ -#define SSP_SR_RFF ((uint32_t)(1<<3)) -/** SSP status SSP Busy bit */ -#define SSP_SR_BSY ((uint32_t)(1<<4)) -/** SSP SR bit mask */ -#define SSP_SR_BITMASK ((uint32_t)(0x1F)) - -/*********************************************************************//** - * Macro defines for CPSR register - **********************************************************************/ -/** SSP clock prescaler */ -#define SSP_CPSR_CPDVSR(n) ((uint32_t)(n&0xFF)) -/** SSP CPSR bit mask */ -#define SSP_CPSR_BITMASK ((uint32_t)(0xFF)) - -/*********************************************************************//** - * Macro define for (IMSC) Interrupt Mask Set/Clear registers - **********************************************************************/ -/** Receive Overrun */ -#define SSP_IMSC_ROR ((uint32_t)(1<<0)) -/** Receive TimeOut */ -#define SSP_IMSC_RT ((uint32_t)(1<<1)) -/** Rx FIFO is at least half full */ -#define SSP_IMSC_RX ((uint32_t)(1<<2)) -/** Tx FIFO is at least half empty */ -#define SSP_IMSC_TX ((uint32_t)(1<<3)) -/** IMSC bit mask */ -#define SSP_IMSC_BITMASK ((uint32_t)(0x0F)) - -/*********************************************************************//** - * Macro define for (RIS) Raw Interrupt Status registers - **********************************************************************/ -/** Receive Overrun */ -#define SSP_RIS_ROR ((uint32_t)(1<<0)) -/** Receive TimeOut */ -#define SSP_RIS_RT ((uint32_t)(1<<1)) -/** Rx FIFO is at least half full */ -#define SSP_RIS_RX ((uint32_t)(1<<2)) -/** Tx FIFO is at least half empty */ -#define SSP_RIS_TX ((uint32_t)(1<<3)) -/** RIS bit mask */ -#define SSP_RIS_BITMASK ((uint32_t)(0x0F)) - -/*********************************************************************//** - * Macro define for (MIS) Masked Interrupt Status registers - **********************************************************************/ -/** Receive Overrun */ -#define SSP_MIS_ROR ((uint32_t)(1<<0)) -/** Receive TimeOut */ -#define SSP_MIS_RT ((uint32_t)(1<<1)) -/** Rx FIFO is at least half full */ -#define SSP_MIS_RX ((uint32_t)(1<<2)) -/** Tx FIFO is at least half empty */ -#define SSP_MIS_TX ((uint32_t)(1<<3)) -/** MIS bit mask */ -#define SSP_MIS_BITMASK ((uint32_t)(0x0F)) - -/*********************************************************************//** - * Macro define for (ICR) Interrupt Clear registers - **********************************************************************/ -/** Writing a 1 to this bit clears the "frame was received when - * RxFIFO was full" interrupt */ -#define SSP_ICR_ROR ((uint32_t)(1<<0)) -/** Writing a 1 to this bit clears the "Rx FIFO was not empty and - * has not been read for a timeout period" interrupt */ -#define SSP_ICR_RT ((uint32_t)(1<<1)) -/** ICR bit mask */ -#define SSP_ICR_BITMASK ((uint32_t)(0x03)) - -/*********************************************************************//** - * Macro defines for DMACR register - **********************************************************************/ -/** SSP bit for enabling RX DMA */ -#define SSP_DMA_RXDMA_EN ((uint32_t)(1<<0)) -/** SSP bit for enabling TX DMA */ -#define SSP_DMA_TXDMA_EN ((uint32_t)(1<<1)) -/** DMACR bit mask */ -#define SSP_DMA_BITMASK ((uint32_t)(0x03)) - -/** - * @} - */ - - -/* Public Types --------------------------------------------------------------- */ -/** @defgroup SSP_Public_Types SSP Public Types - * @{ - */ - -/** @brief SSP configuration structure */ -typedef struct { - uint32_t Databit; /** Databit number, should be SSP_DATABIT_x, - where x is in range from 4 - 16 */ - uint32_t CPHA; /** Clock phase, should be: - - SSP_CPHA_FIRST: first clock edge - - SSP_CPHA_SECOND: second clock edge */ - uint32_t CPOL; /** Clock polarity, should be: - - SSP_CPOL_HI: high level - - SSP_CPOL_LO: low level */ - uint32_t Mode; /** SSP mode, should be: - - SSP_MASTER_MODE: Master mode - - SSP_SLAVE_MODE: Slave mode */ - uint32_t FrameFormat; /** Frame Format: - - SSP_FRAME_SPI: Motorola SPI frame format - - SSP_FRAME_TI: TI frame format - - SSP_FRAME_MICROWIRE: National Microwire frame format */ - uint32_t ClockRate; /** Clock rate,in Hz */ -} SSP_CFG_Type; - -/** - * @brief SSP Transfer Type definitions - */ -typedef enum { - SSP_TRANSFER_POLLING = 0, /**< Polling transfer */ - SSP_TRANSFER_INTERRUPT /**< Interrupt transfer */ -} SSP_TRANSFER_Type; - -/** - * @brief SPI Data configuration structure definitions - */ -typedef struct { - void *tx_data; /**< Pointer to transmit data */ - uint32_t tx_cnt; /**< Transmit counter */ - void *rx_data; /**< Pointer to transmit data */ - uint32_t rx_cnt; /**< Receive counter */ - uint32_t length; /**< Length of transfer data */ - uint32_t status; /**< Current status of SSP activity */ -} SSP_DATA_SETUP_Type; - - -/** - * @} - */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup SSP_Public_Functions SSP Public Functions - * @{ - */ - -/* SSP Init/DeInit functions --------------------------------------------------*/ -void SSP_Init(LPC_SSP_TypeDef *SSPx, SSP_CFG_Type *SSP_ConfigStruct); -void SSP_DeInit(LPC_SSP_TypeDef* SSPx); - -/* SSP configure functions ----------------------------------------------------*/ -void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct); - -/* SSP enable/disable functions -----------------------------------------------*/ -void SSP_Cmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState); -void SSP_LoopBackCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState); -void SSP_SlaveOutputCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState); -void SSP_DMACmd(LPC_SSP_TypeDef *SSPx, uint32_t DMAMode, FunctionalState NewState); - -/* SSP get information functions ----------------------------------------------*/ -FlagStatus SSP_GetStatus(LPC_SSP_TypeDef* SSPx, uint32_t FlagType); -uint8_t SSP_GetDataSize(LPC_SSP_TypeDef* SSPx); -IntStatus SSP_GetRawIntStatus(LPC_SSP_TypeDef *SSPx, uint32_t RawIntType); -uint32_t SSP_GetRawIntStatusReg(LPC_SSP_TypeDef *SSPx); -IntStatus SSP_GetIntStatus (LPC_SSP_TypeDef *SSPx, uint32_t IntType); - -/* SSP transfer data functions ------------------------------------------------*/ -void SSP_SendData(LPC_SSP_TypeDef* SSPx, uint16_t Data); -uint16_t SSP_ReceiveData(LPC_SSP_TypeDef* SSPx); -int32_t SSP_ReadWrite (LPC_SSP_TypeDef *SSPx, SSP_DATA_SETUP_Type *dataCfg, \ - SSP_TRANSFER_Type xfType); - -/* SSP IRQ function ------------------------------------------------------------*/ -void SSP_IntConfig(LPC_SSP_TypeDef *SSPx, uint32_t IntType, FunctionalState NewState); -void SSP_ClearIntPending(LPC_SSP_TypeDef *SSPx, uint32_t IntType); - - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __LPC_SSP_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_systick.h b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_systick.h deleted file mode 100644 index cca57104e52..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_systick.h +++ /dev/null @@ -1,119 +0,0 @@ -/********************************************************************** -* $Id$ lpc_systick.h 2011-06-02 -*//** -* @file lpc_systick.h -* @brief Contains all macro definitions and function prototypes -* support for SYSTICK firmware library on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup SYSTICK SysTick (System tick timer) - * @ingroup LPC_CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef __LPC_SYSTICK_H_ -#define __LPC_SYSTICK_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC407x_8x_177x_8x.h" -#include "lpc_types.h" - - -#ifdef __cplusplus -extern "C" -{ -#endif - - -/* Private Macros ------------------------------------------------------------- */ -/** @defgroup SYSTICK_Private_Macros SysTick Private Macros - * @{ - */ -/*********************************************************************//** - * Macro defines for System Timer Control and status (STCTRL) register - **********************************************************************/ -#define ST_CTRL_ENABLE ((uint32_t)(1<<0)) -#define ST_CTRL_TICKINT ((uint32_t)(1<<1)) -#define ST_CTRL_CLKSOURCE ((uint32_t)(1<<2)) -#define ST_CTRL_COUNTFLAG ((uint32_t)(1<<16)) - -/*********************************************************************//** - * Macro defines for System Timer Reload value (STRELOAD) register - **********************************************************************/ -#define ST_RELOAD_RELOAD(n) ((uint32_t)(n & 0x00FFFFFF)) - -/*********************************************************************//** - * Macro defines for System Timer Current value (STCURRENT) register - **********************************************************************/ -#define ST_RELOAD_CURRENT(n) ((uint32_t)(n & 0x00FFFFFF)) - -/*********************************************************************//** - * Macro defines for System Timer Calibration value (STCALIB) register - **********************************************************************/ -#define ST_CALIB_TENMS(n) ((uint32_t)(n & 0x00FFFFFF)) -#define ST_CALIB_SKEW ((uint32_t)(1<<30)) -#define ST_CALIB_NOREF ((uint32_t)(1<<31)) - -#define CLKSOURCE_EXT ((uint32_t)(0)) -#define CLKSOURCE_CPU ((uint32_t)(1)) - -/** - * @} - */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup SYSTICK_Public_Functions Systick Public Functions - * @{ - */ - -void SYSTICK_InternalInit(uint32_t time); -void SYSTICK_ExternalInit(uint32_t freq, uint32_t time); - -void SYSTICK_Cmd(FunctionalState NewState); -void SYSTICK_IntCmd(FunctionalState NewState); -uint32_t SYSTICK_GetCurrentValue(void); -void SYSTICK_ClearCounterFlag(void); - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - - -#endif /* __LPC_SYSTICK_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_timer.h b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_timer.h deleted file mode 100644 index acabdfc7090..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_timer.h +++ /dev/null @@ -1,321 +0,0 @@ -/********************************************************************** -* $Id$ lpc_timer.h 2011-06-02 -*//** -* @file lpc_timer.h -* @brief Contains all macro definitions and function prototypes -* support for Timer firmware library on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup TIMER TIM (Timer) - * @ingroup LPC_CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef __LPC_TIMER_H_ -#define __LPC_TIMER_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC407x_8x_177x_8x.h" -#include "lpc_types.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Private Macros ------------------------------------------------------------- */ -/** @defgroup TIM_Private_Macros Timer Private Macros - * @{ - */ - -/* --------------------- BIT DEFINITIONS -------------------------------------- */ -/********************************************************************** -** Interrupt information -**********************************************************************/ -/** Macro to clean interrupt pending */ -#define TIM_IR_CLR(n) _BIT(n) - -/********************************************************************** -** Timer interrupt register definitions -**********************************************************************/ -/** Macro for getting a timer match interrupt bit */ -#define TIM_MATCH_INT(n) (_BIT(n & 0x0F)) -/** Macro for getting a capture event interrupt bit */ -#define TIM_CAP_INT(n) (_BIT(((n & 0x0F) + 4))) - -/********************************************************************** -* Timer control register definitions -**********************************************************************/ -/** Timer/counter enable bit */ -#define TIM_ENABLE ((uint32_t)(1<<0)) -/** Timer/counter reset bit */ -#define TIM_RESET ((uint32_t)(1<<1)) -/** Timer control bit mask */ -#define TIM_TCR_MASKBIT ((uint32_t)(3)) - -/********************************************************************** -* Timer match control register definitions -**********************************************************************/ -/** Bit location for interrupt on MRx match, n = 0 to 3 */ -#define TIM_INT_ON_MATCH(n) (_BIT((n * 3))) -/** Bit location for reset on MRx match, n = 0 to 3 */ -#define TIM_RESET_ON_MATCH(n) (_BIT(((n * 3) + 1))) -/** Bit location for stop on MRx match, n = 0 to 3 */ -#define TIM_STOP_ON_MATCH(n) (_BIT(((n * 3) + 2))) -/** Timer Match control bit mask */ -#define TIM_MCR_MASKBIT ((uint32_t)(0x0FFF)) -/** Timer Match control bit mask for specific channel*/ -#define TIM_MCR_CHANNEL_MASKBIT(n) ((uint32_t)(7<<(n*3))) - -/********************************************************************** -* Timer capture control register definitions -**********************************************************************/ -/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */ -#define TIM_CAP_RISING(n) (_BIT((n * 3))) -/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */ -#define TIM_CAP_FALLING(n) (_BIT(((n * 3) + 1))) -/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */ -#define TIM_INT_ON_CAP(n) (_BIT(((n * 3) + 2))) -/** Mask bit for rising and falling edge bit */ -#define TIM_EDGE_MASK(n) (_SBF((n * 3), 0x03)) -/** Timer capture control bit mask */ -#define TIM_CCR_MASKBIT ((uint32_t)(0x3F)) -/** Timer Capture control bit mask for specific channel*/ -#define TIM_CCR_CHANNEL_MASKBIT(n) ((uint32_t)(7<<(n*3))) - -/********************************************************************** -* Timer external match register definitions -**********************************************************************/ -/** Bit location for output state change of MAT.n when external match - happens, n = 0 to 3 */ -#define TIM_EM(n) _BIT(n) -/** Output state change of MAT.n when external match happens: no change */ -#define TIM_EM_NOTHING ((uint8_t)(0x0)) -/** Output state change of MAT.n when external match happens: low */ -#define TIM_EM_LOW ((uint8_t)(0x1)) -/** Output state change of MAT.n when external match happens: high */ -#define TIM_EM_HIGH ((uint8_t)(0x2)) -/** Output state change of MAT.n when external match happens: toggle */ -#define TIM_EM_TOGGLE ((uint8_t)(0x3)) -/** Macro for setting for the MAT.n change state bits */ -#define TIM_EM_SET(n,s) (_SBF(((n << 1) + 4), (s & 0x03))) -/** Mask for the MAT.n change state bits */ -#define TIM_EM_MASK(n) (_SBF(((n << 1) + 4), 0x03)) -/** Timer external match bit mask */ -#define TIM_EMR_MASKBIT 0x0FFF - -/********************************************************************** -* Timer Count Control Register definitions -**********************************************************************/ -/** Mask to get the Counter/timer mode bits */ -#define TIM_CTCR_MODE_MASK 0x3 -/** Mask to get the count input select bits */ -#define TIM_CTCR_INPUT_MASK 0xC -/** Timer Count control bit mask */ -#define TIM_CTCR_MASKBIT 0xF -#define TIM_COUNTER_MODE ((uint8_t)(1)) - -/** - * @} - */ - - -/* Public Types --------------------------------------------------------------- */ -/** @defgroup TIM_Public_Types Timer Public Types - * @{ - */ - -/*********************************************************************** - * Timer device enumeration -**********************************************************************/ -/** @brief interrupt type */ -typedef enum -{ - TIM_MR0_INT =0, /*!< interrupt for Match channel 0*/ - TIM_MR1_INT =1, /*!< interrupt for Match channel 1*/ - TIM_MR2_INT =2, /*!< interrupt for Match channel 2*/ - TIM_MR3_INT =3, /*!< interrupt for Match channel 3*/ - TIM_CR0_INT =4, /*!< interrupt for Capture channel 0*/ - TIM_CR1_INT =5, /*!< interrupt for Capture channel 1*/ -}TIM_INT_TYPE; - -/** @brief Timer/counter operating mode */ -typedef enum -{ - TIM_TIMER_MODE = 0, /*!< Timer mode */ - TIM_COUNTER_RISING_MODE, /*!< Counter rising mode */ - TIM_COUNTER_FALLING_MODE, /*!< Counter falling mode */ - TIM_COUNTER_ANY_MODE /*!< Counter on both edges */ -} TIM_MODE_OPT; - -/** @brief Timer/Counter prescale option */ -typedef enum -{ - TIM_PRESCALE_TICKVAL = 0, /*!< Prescale in absolute value */ - TIM_PRESCALE_USVAL /*!< Prescale in microsecond value */ -} TIM_PRESCALE_OPT; - -/** @brief Counter input option */ -typedef enum -{ - TIM_COUNTER_INCAP0 = 0, /*!< CAPn.0 input pin for TIMERn */ - TIM_COUNTER_INCAP1, /*!< CAPn.1 input pin for TIMERn */ -} TIM_COUNTER_INPUT_OPT; - -/** @brief Timer/Counter external match option */ -typedef enum -{ - TIM_EXTMATCH_NOTHING = 0, /*!< Do nothing for external output pin if match */ - TIM_EXTMATCH_LOW, /*!< Force external output pin to low if match */ - TIM_EXTMATCH_HIGH, /*!< Force external output pin to high if match */ - TIM_EXTMATCH_TOGGLE /*!< Toggle external output pin if match */ -}TIM_EXTMATCH_OPT; - -/** @brief Timer/counter capture mode options */ -typedef enum { - TIM_CAPTURE_NONE = 0, /*!< No Capture */ - TIM_CAPTURE_RISING, /*!< Rising capture mode */ - TIM_CAPTURE_FALLING, /*!< Falling capture mode */ - TIM_CAPTURE_ANY /*!< On both edges */ -} TIM_CAP_MODE_OPT; - -/** @brief Configuration structure in TIMER mode */ -typedef struct -{ - - uint8_t PrescaleOption; /**< Timer Prescale option, should be: - - TIM_PRESCALE_TICKVAL: Prescale in absolute value - - TIM_PRESCALE_USVAL: Prescale in microsecond value - */ - uint8_t Reserved[3]; /**< Reserved */ - uint32_t PrescaleValue; /**< Prescale value */ -} TIM_TIMERCFG_Type; - -/** @brief Configuration structure in COUNTER mode */ -typedef struct { - - uint8_t CounterOption; /**< Counter Option, should be: - - TIM_COUNTER_INCAP0: CAPn.0 input pin for TIMERn - - TIM_COUNTER_INCAP1: CAPn.1 input pin for TIMERn - */ - uint8_t CountInputSelect; - uint8_t Reserved[2]; -} TIM_COUNTERCFG_Type; - -/** @brief Match channel configuration structure */ -typedef struct { - uint8_t MatchChannel; /**< Match channel, should be in range - from 0..3 */ - uint8_t IntOnMatch; /**< Interrupt On match, should be: - - ENABLE: Enable this function. - - DISABLE: Disable this function. - */ - uint8_t StopOnMatch; /**< Stop On match, should be: - - ENABLE: Enable this function. - - DISABLE: Disable this function. - */ - uint8_t ResetOnMatch; /**< Reset On match, should be: - - ENABLE: Enable this function. - - DISABLE: Disable this function. - */ - - uint8_t ExtMatchOutputType; /**< External Match Output type, should be: - - TIM_EXTMATCH_NOTHING: Do nothing for external output pin if match - - TIM_EXTMATCH_LOW: Force external output pin to low if match - - TIM_EXTMATCH_HIGH: Force external output pin to high if match - - TIM_EXTMATCH_TOGGLE: Toggle external output pin if match. - */ - uint8_t Reserved[3]; /** Reserved */ - uint32_t MatchValue; /** Match value */ -} TIM_MATCHCFG_Type; - -/** @brief Capture Input configuration structure */ -typedef struct { - uint8_t CaptureChannel; /**< Capture channel, should be in range - from 0..1 */ - uint8_t RisingEdge; /**< caption rising edge, should be: - - ENABLE: Enable rising edge. - - DISABLE: Disable this function. - */ - uint8_t FallingEdge; /**< caption falling edge, should be: - - ENABLE: Enable falling edge. - - DISABLE: Disable this function. - */ - uint8_t IntOnCaption; /**< Interrupt On caption, should be: - - ENABLE: Enable interrupt function. - - DISABLE: Disable this function. - */ - -} TIM_CAPTURECFG_Type; - -/** - * @} - */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup TIM_Public_Functions Timer Public Functions - * @{ - */ -/* Init/DeInit TIM functions -----------*/ -void TIM_Init(LPC_TIM_TypeDef *TIMx, TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct); -void TIM_DeInit(LPC_TIM_TypeDef *TIMx); - -/* TIM interrupt functions -------------*/ -void TIM_ClearIntPending(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag); -void TIM_ClearIntCapturePending(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag); -FlagStatus TIM_GetIntStatus(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag); -FlagStatus TIM_GetIntCaptureStatus(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag); - -/* TIM configuration functions --------*/ -void TIM_ConfigStructInit(TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct); -void TIM_ConfigMatch(LPC_TIM_TypeDef *TIMx, TIM_MATCHCFG_Type *TIM_MatchConfigStruct); -void TIM_UpdateMatchValue(LPC_TIM_TypeDef *TIMx,uint8_t MatchChannel, uint32_t MatchValue); -void TIM_ConfigCapture(LPC_TIM_TypeDef *TIMx, TIM_CAPTURECFG_Type *TIM_CaptureConfigStruct); -void TIM_Cmd(LPC_TIM_TypeDef *TIMx, FunctionalState NewState); - -uint32_t TIM_GetCaptureValue(LPC_TIM_TypeDef *TIMx, TIM_COUNTER_INPUT_OPT CaptureChannel); -void TIM_ResetCounter(LPC_TIM_TypeDef *TIMx); - -void TIM_Waitus(uint32_t time); -void TIM_Waitms(uint32_t time); - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __LPC_TIMER_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_types.h b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_types.h deleted file mode 100644 index 72639dc6c53..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_types.h +++ /dev/null @@ -1,211 +0,0 @@ -/********************************************************************** -* $Id$ lpc_types.h 2011-06-02 -*//** -* @file lpc_types.h -* @brief Contains the NXP ABL typedefs for C standard types. -* It is intended to be used in ISO C conforming development -* environments and checks for this insofar as it is possible -* to do so. -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Type group ----------------------------------------------------------- */ -#ifndef __LPC_TYPES_H -#define __LPC_TYPES_H - -/* Includes ------------------------------------------------------------------- */ -#include - -/** @defgroup LPC_Type_Def Data Types Definitions - * @ingroup LPC_CMSIS_FwLib_Drivers - * @{ - */ - -/* Public Types --------------------------------------------------------------- */ -/** @defgroup LPC_Types_Public_Types Basic Public Data Types - * @{ - */ - -/** - * @brief Boolean Type definition - */ -typedef enum {FALSE = 0, TRUE = !FALSE} Bool; - -/** - * @brief Flag Status and Interrupt Flag Status type definition - */ -typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState; -#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET)) - -/** - * @brief Functional State Definition - */ -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE)) - -/** - * @ Status type definition - */ -typedef enum {ERROR = 0, SUCCESS = !ERROR} Status; - - -/** - * Read/Write transfer type mode (Block or non-block) - */ -typedef enum -{ - NONE_BLOCKING = 0, /**< None Blocking type */ - BLOCKING, /**< Blocking type */ -} TRANSFER_BLOCK_Type; - - -/** Pointer to Function returning Void (any number of parameters) */ -typedef void (*PFV)(); - -/** Pointer to Function returning int32_t (any number of parameters) */ -typedef int32_t(*PFI)(); - -/** - * @} - */ - - -/* Public Macros -------------------------------------------------------------- */ -/** @defgroup LPC_Types_Public_Macros Basic Public Macros - * @{ - */ - -/** _BIT(n) sets the bit at position "n" - * _BIT(n) is intended to be used in "OR" and "AND" expressions: - * e.g., "(_BIT(3) | _BIT(7))". - */ -#undef _BIT -/** Set bit macro */ -#define _BIT(n) (1< = (any_expression) & _BITMASK(x), where 0 < x <= 32. - * If "any_expression" results in a value that is larger than can be - * contained in 'x' bits, the bits above 'x - 1' are masked off. When - * used with the _SBF example above, the example would be written: - * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16)) - * This ensures that the value written to a_reg is no wider than - * 16 bits, and makes the code easier to read and understand. - */ -#undef _BITMASK -/* Bitmask creation macro */ -#define _BITMASK(field_width) ( _BIT(field_width) - 1) - -/* NULL pointer */ -#ifndef NULL -#define NULL ((void*) 0) -#endif - -/* Number of elements in an array */ -#define NELEMENTS(array) (sizeof (array) / sizeof (array[0])) - -/* Static data/function define */ -#define STATIC static -/* External data/function define */ -#define EXTERN extern - -#if !defined(MAX) -#define MAX(a, b) (((a) > (b)) ? (a) : (b)) -#endif -#if !defined(MIN) -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) -#endif - -/** - * @} - */ - - -/* Old Type Definition compatibility ------------------------------------------ */ -/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types - * @{ - */ - -/** SMA type for character type */ -typedef char CHAR; - -/** SMA type for 8 bit unsigned value */ -typedef uint8_t UNS_8; - -/** SMA type for 8 bit signed value */ -typedef int8_t INT_8; - -/** SMA type for 16 bit unsigned value */ -typedef uint16_t UNS_16; - -/** SMA type for 16 bit signed value */ -typedef int16_t INT_16; - -/** SMA type for 32 bit unsigned value */ -typedef uint32_t UNS_32; - -/** SMA type for 32 bit signed value */ -typedef int32_t INT_32; - -/** SMA type for 64 bit signed value */ -typedef int64_t INT_64; - -/** SMA type for 64 bit unsigned value */ -typedef uint64_t UNS_64; - -/** 32 bit boolean type */ -typedef Bool BOOL_32; - -/** 16 bit boolean type */ -typedef Bool BOOL_16; - -/** 8 bit boolean type */ -typedef Bool BOOL_8; - -/** - * @} - */ - - -#endif /* __LPC_TYPES_H */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_uart.h b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_uart.h deleted file mode 100644 index f54f08dc1c7..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_uart.h +++ /dev/null @@ -1,710 +0,0 @@ -/********************************************************************** -* $Id$ lpc_uart.h 2011-06-02 -*//** -* @file lpc_uart.h -* @brief Contains all macro definitions and function prototypes -* support for UART firmware library on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup UART UART (Universal Asynchronous Receiver/Transmitter) - * @ingroup LPC_CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef __LPC_UART_H_ -#define __LPC_UART_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC407x_8x_177x_8x.h" -#include "lpc_types.h" - - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Public Macros -------------------------------------------------------------- */ -/** @defgroup UART_Public_Macros UART Public Macros - * @{ - */ - -/** UART time-out definitions in case of using Read() and Write function - * with Blocking Flag mode - */ -#define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL) - -/** - * @} - */ - -/* Private Macros ------------------------------------------------------------- */ -/** @defgroup UART_Private_Macros UART Private Macros - * @{ - */ - -/* Accepted Error baud rate value (in percent unit) */ -#define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */ - - -/* --------------------- BIT DEFINITIONS -------------------------------------- */ -/*********************************************************************//** - * Macro defines for Macro defines for UARTn Receiver Buffer Register - **********************************************************************/ -/** UART Received Buffer mask bit (8 bits) */ -#define UART_RBR_MASKBIT ((uint8_t)0xFF) - -/*********************************************************************//** - * Macro defines for Macro defines for UARTn Transmit Holding Register - **********************************************************************/ -/** UART Transmit Holding mask bit (8 bits) */ -#define UART_THR_MASKBIT ((uint8_t)0xFF) - -/*********************************************************************//** - * Macro defines for Macro defines for UARTn Divisor Latch LSB register - **********************************************************************/ -/** Macro for loading least significant halfs of divisors */ -#define UART_LOAD_DLL(div) ((div) & 0xFF) -/** Divisor latch LSB bit mask */ -#define UART_DLL_MASKBIT ((uint8_t)0xFF) - -/*********************************************************************//** - * Macro defines for Macro defines for UARTn Divisor Latch MSB register - **********************************************************************/ -/** Divisor latch MSB bit mask */ -#define UART_DLM_MASKBIT ((uint8_t)0xFF) -/** Macro for loading most significant halfs of divisors */ -#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) - -/*********************************************************************//** - * Macro defines for Macro defines for UART interrupt enable register - **********************************************************************/ -/** RBR Interrupt enable*/ -#define UART_IER_RBRINT_EN ((uint32_t)(1<<0)) -/** THR Interrupt enable*/ -#define UART_IER_THREINT_EN ((uint32_t)(1<<1)) -/** RX line status interrupt enable*/ -#define UART_IER_RLSINT_EN ((uint32_t)(1<<2)) -/** Modem status interrupt enable */ -#define UART1_IER_MSINT_EN ((uint32_t)(1<<3)) -/** CTS1 signal transition interrupt enable */ -#define UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) -/** Enables the end of auto-baud interrupt */ -#define UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) -/** Enables the auto-baud time-out interrupt */ -#define UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) -/** UART interrupt enable register bit mask */ -#define UART_IER_BITMASK ((uint32_t)(0x307)) -/** UART1 interrupt enable register bit mask */ -#define UART1_IER_BITMASK ((uint32_t)(0x38F)) - - -/*********************************************************************//** - * Macro defines for Macro defines for UART interrupt identification register - **********************************************************************/ -/** Interrupt Status - Active low */ -#define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) -/** Interrupt identification: Receive line status*/ -#define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) -/** Interrupt identification: Receive data available*/ -#define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) -/** Interrupt identification: Character time-out indicator*/ -#define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) -/** Interrupt identification: THRE interrupt*/ -#define UART_IIR_INTID_THRE ((uint32_t)(1<<1)) -/** Interrupt identification: Modem interrupt*/ -#define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) -/** Interrupt identification: Interrupt ID mask */ -#define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) -/** These bits are equivalent to UnFCR[0] */ -#define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) -/** End of auto-baud interrupt */ -#define UART_IIR_ABEO_INT ((uint32_t)(1<<8)) -/** Auto-baud time-out interrupt */ -#define UART_IIR_ABTO_INT ((uint32_t)(1<<9)) -/** UART interrupt identification register bit mask */ -#define UART_IIR_BITMASK ((uint32_t)(0x3CF)) - -/*********************************************************************//** - * Macro defines for Macro defines for UART FIFO control register - **********************************************************************/ -/** UART FIFO enable */ -#define UART_FCR_FIFO_EN ((uint8_t)(1<<0)) -/** UART FIFO RX reset */ -#define UART_FCR_RX_RS ((uint8_t)(1<<1)) -/** UART FIFO TX reset */ -#define UART_FCR_TX_RS ((uint8_t)(1<<2)) -/** UART DMA mode selection */ -#define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3)) -/** UART FIFO trigger level 0: 1 character */ -#define UART_FCR_TRG_LEV0 ((uint8_t)(0)) -/** UART FIFO trigger level 1: 4 character */ -#define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6)) -/** UART FIFO trigger level 2: 8 character */ -#define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) -/** UART FIFO trigger level 3: 14 character */ -#define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) -/** UART FIFO control bit mask */ -#define UART_FCR_BITMASK ((uint8_t)(0xCF)) - -#define UART_TX_FIFO_SIZE (16) - -/*********************************************************************//** - * Macro defines for Macro defines for UART line control register - **********************************************************************/ -/** UART 5 bit data mode */ -#define UART_LCR_WLEN5 ((uint8_t)(0)) -/** UART 6 bit data mode */ -#define UART_LCR_WLEN6 ((uint8_t)(1<<0)) -/** UART 7 bit data mode */ -#define UART_LCR_WLEN7 ((uint8_t)(2<<0)) -/** UART 8 bit data mode */ -#define UART_LCR_WLEN8 ((uint8_t)(3<<0)) -/** UART Two Stop Bits Select */ -#define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2)) -/** UART Parity Enable */ -#define UART_LCR_PARITY_EN ((uint8_t)(1<<3)) -/** UART Odd Parity Select */ -#define UART_LCR_PARITY_ODD ((uint8_t)(0)) -/** UART Even Parity Select */ -#define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4)) -/** UART force 1 stick parity */ -#define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4)) -/** UART force 0 stick parity */ -#define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4)) -/** UART Transmission Break enable */ -#define UART_LCR_BREAK_EN ((uint8_t)(1<<6)) -/** UART Divisor Latches Access bit enable */ -#define UART_LCR_DLAB_EN ((uint8_t)(1<<7)) -/** UART line control bit mask */ -#define UART_LCR_BITMASK ((uint8_t)(0xFF)) - -/*********************************************************************//** - * Macro defines for Macro defines for UART1 Modem Control Register - **********************************************************************/ -/** Source for modem output pin DTR */ -#define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0)) -/** Source for modem output pin RTS */ -#define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1)) -/** Loop back mode select */ -#define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4)) -/** Enable Auto RTS flow-control */ -#define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6)) -/** Enable Auto CTS flow-control */ -#define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7)) -/** UART1 bit mask value */ -#define UART1_MCR_BITMASK ((uint8_t)(0x0F3)) - -/*********************************************************************//** - * Macro defines for Macro defines for UART line status register - **********************************************************************/ -/** Line status register: Receive data ready*/ -#define UART_LSR_RDR ((uint8_t)(1<<0)) -/** Line status register: Overrun error*/ -#define UART_LSR_OE ((uint8_t)(1<<1)) -/** Line status register: Parity error*/ -#define UART_LSR_PE ((uint8_t)(1<<2)) -/** Line status register: Framing error*/ -#define UART_LSR_FE ((uint8_t)(1<<3)) -/** Line status register: Break interrupt*/ -#define UART_LSR_BI ((uint8_t)(1<<4)) -/** Line status register: Transmit holding register empty*/ -#define UART_LSR_THRE ((uint8_t)(1<<5)) -/** Line status register: Transmitter empty*/ -#define UART_LSR_TEMT ((uint8_t)(1<<6)) -/** Error in RX FIFO*/ -#define UART_LSR_RXFE ((uint8_t)(1<<7)) -/** UART Line status bit mask */ -#define UART_LSR_BITMASK ((uint8_t)(0xFF)) - -/*********************************************************************//** - * Macro defines for Macro defines for UART Modem (UART1 only) status register - **********************************************************************/ -/** Set upon state change of input CTS */ -#define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0)) -/** Set upon state change of input DSR */ -#define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1)) -/** Set upon low to high transition of input RI */ -#define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2)) -/** Set upon state change of input DCD */ -#define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3)) -/** Clear To Send State */ -#define UART1_MSR_CTS ((uint8_t)(1<<4)) -/** Data Set Ready State */ -#define UART1_MSR_DSR ((uint8_t)(1<<5)) -/** Ring Indicator State */ -#define UART1_MSR_RI ((uint8_t)(1<<6)) -/** Data Carrier Detect State */ -#define UART1_MSR_DCD ((uint8_t)(1<<7)) -/** MSR register bit-mask value */ -#define UART1_MSR_BITMASK ((uint8_t)(0xFF)) - -/*********************************************************************//** - * Macro defines for Macro defines for UART Scratch Pad Register - **********************************************************************/ -/** UART Scratch Pad bit mask */ -#define UART_SCR_BIMASK ((uint8_t)(0xFF)) - -/*********************************************************************//** - * Macro defines for Macro defines for UART Auto baudrate control register - **********************************************************************/ -/** UART Auto-baud start */ -#define UART_ACR_START ((uint32_t)(1<<0)) -/** UART Auto baudrate Mode 1 */ -#define UART_ACR_MODE ((uint32_t)(1<<1)) -/** UART Auto baudrate restart */ -#define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2)) -/** UART End of auto-baud interrupt clear */ -#define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8)) -/** UART Auto-baud time-out interrupt clear */ -#define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9)) -/** UART Auto Baudrate register bit mask */ -#define UART_ACR_BITMASK ((uint32_t)(0x307)) - -/*********************************************************************//** - * Macro defines for Macro defines for UART IrDA control register - **********************************************************************/ -/** IrDA mode enable */ -#define UART_ICR_IRDAEN ((uint32_t)(1<<0)) -/** IrDA serial input inverted */ -#define UART_ICR_IRDAINV ((uint32_t)(1<<1)) -/** IrDA fixed pulse width mode */ -#define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2)) -/** PulseDiv - Configures the pulse when FixPulseEn = 1 */ -#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) -/** UART IRDA bit mask */ -#define UART_ICR_BITMASK ((uint32_t)(0x3F)) - -/*********************************************************************//** - * Macro defines for Macro defines for UART Fractional divider register - **********************************************************************/ -/** Baud-rate generation pre-scaler divisor */ -#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) -/** Baud-rate pre-scaler multiplier value */ -#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) -/** UART Fractional Divider register bit mask */ -#define UART_FDR_BITMASK ((uint32_t)(0xFF)) - -/*********************************************************************//** - * Macro defines for Macro defines for UART Tx Enable register - **********************************************************************/ -/** Transmit enable bit */ -#define UART_TER_TXEN ((uint8_t)(1<<7)) -/** UART Transmit Enable Register bit mask */ -#define UART_TER_BITMASK ((uint8_t)(0x80)) -/** Transmit enable bit on UART4 */ -#define UART4_TER_TXEN ((uint8_t)(1<<0)) -/** UART4 Transmit Enable Register bit mask */ -#define UART4_TER_BITMASK ((uint8_t)(0x01)) - -/*********************************************************************//** - * Macro defines for Macro defines for UART RS485 Control register - **********************************************************************/ -/** RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled */ -#define UART_RS485CTRL_NMM_EN ((uint32_t)(1<<0)) -/** The receiver is disabled */ -#define UART_RS485CTRL_RX_DIS ((uint32_t)(1<<1)) -/** Auto Address Detect (AAD) is enabled */ -#define UART_RS485CTRL_AADEN ((uint32_t)(1<<2)) -/** If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control */ -#define UART_RS485CTRL_SEL_DTR ((uint32_t)(1<<3)) -/** Enable Auto Direction Control */ -#define UART_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4)) -/** This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. -The direction control pin will be driven to logic "1" when the transmitter has data to be sent */ -#define UART_RS485CTRL_OINV_1 ((uint32_t)(1<<5)) - -/** RS485 control bit-mask value */ -#define UART_RS485CTRL_BITMASK ((uint32_t)(0x3F)) - -/*********************************************************************//** - * Macro defines for Macro defines for UART RS-485 Address Match register - **********************************************************************/ -#define UART_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */ - -/*********************************************************************//** - * Macro defines for Macro defines for UART1 RS-485 Delay value register - **********************************************************************/ -/* Macro defines for UART1 RS-485 Delay value register */ -#define UART_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */ - - -/** - * @} - */ - - -/* Public Types --------------------------------------------------------------- */ -/** @defgroup UART_Public_Types UART Public Types - * @{ - */ - -/** - * @brief UART ID - */ - typedef enum -{ - UART_0 = 0, - UART_1, - UART_2, - UART_3, - UART_4, -} UART_ID_Type; - -/** - * @brief UART Databit type definitions - */ -typedef enum { - UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */ - UART_DATABIT_6, /*!< UART 6 bit data mode */ - UART_DATABIT_7, /*!< UART 7 bit data mode */ - UART_DATABIT_8 /*!< UART 8 bit data mode */ -} UART_DATABIT_Type; - -/** - * @brief UART Stop bit type definitions - */ -typedef enum { - UART_STOPBIT_1 = (0), /*!< UART 1 Stop Bits Select */ - UART_STOPBIT_2, /*!< UART Two Stop Bits Select */ -} UART_STOPBIT_Type; - -/** - * @brief UART Parity type definitions - */ -typedef enum { - UART_PARITY_NONE = 0, /*!< No parity */ - UART_PARITY_ODD, /*!< Odd parity */ - UART_PARITY_EVEN, /*!< Even parity */ - UART_PARITY_SP_1, /*!< Forced "1" stick parity */ - UART_PARITY_SP_0 /*!< Forced "0" stick parity */ -} UART_PARITY_Type; - -/** - * @brief FIFO Level type definitions - */ -typedef enum { - UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */ - UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */ - UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */ - UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */ -} UART_FITO_LEVEL_Type; - -/********************************************************************//** -* @brief UART Interrupt Type definitions -**********************************************************************/ -typedef enum { - UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/ - UART_INTCFG_THRE, /*!< THR Interrupt enable*/ - UART_INTCFG_RLS, /*!< RX line status interrupt enable*/ - UART_INTCFG_MS, /*!< Modem status interrupt enable (UART1 only) */ - UART_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable (UART1 only) */ - UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */ - UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */ -} UART_INT_Type; - -/** - * @brief UART Line Status Type definition - */ -typedef enum { - UART_LINESTAT_RDR = UART_LSR_RDR, /*! the enable bit is enabled */ - uint8_t wdtReset; /**< if ENABLE -> the Reset bit is enabled */ - uint8_t wdtProtect; /**< if ENABLE -> the Protect bit is enabled */ - uint32_t wdtTmrConst; /**< Set the constant value to timeout the WDT */ - uint32_t wdtWarningVal; /**< Set the value to warn the WDT with interrupt */ - uint32_t wdtWindowVal; /**< Set a window vaule for WDT */ -}st_Wdt_Config; - -/** - * @} - */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup WDT_Public_Functions WDT Public Functions - * @{ - */ - -int8_t WWDT_Init(uint32_t TimeOut); -int8_t WWDT_Start(uint32_t TimeOut); -void WWDT_SetMode(uint8_t mode, FunctionalState NewState); -void WWDT_SetTimerConstant(uint32_t constVal); -void WWDT_Enable(FunctionalState NewState); -void WWDT_Cmd(FunctionalState NewState); -int8_t WWDT_SetWarningRaw(uint32_t warnVal); -int8_t WWDT_SetWarning(uint32_t WarnTime); -int8_t WWDT_SetWindowRaw(uint32_t wndVal); -int8_t WWDT_SetWindow(uint32_t WindowedTime); -void WWDT_UpdateTimeOut(uint32_t TimeOut); -FlagStatus WWDT_GetStatus (uint8_t Status); -void WWDT_ClearStatusFlag (uint8_t flag); -void WWDT_ClrTimeOutFlag (void); -void WWDT_FeedStdSeq (void); -void WWDT_Feed (void); -uint32_t WWDT_GetCurrentCount(void); - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __LPC_WWDT_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/lib/spifi_drv_M4.lib b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/lib/spifi_drv_M4.lib deleted file mode 100644 index 0a9c0e2e443..00000000000 Binary files a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/lib/spifi_drv_M4.lib and /dev/null differ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_adc.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_adc.c deleted file mode 100644 index 19a2a2d99f6..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_adc.c +++ /dev/null @@ -1,326 +0,0 @@ -/********************************************************************** -* $Id$ lpc_adc.c 2011-06-02 -*//** -* @file lpc_adc.c -* @brief Contains all functions support for ADC firmware library on -* LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup ADC - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _ADC - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_types.h" -#include "lpc_adc.h" -#include "lpc_clkpwr.h" - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup ADC_Public_Functions - * @{ - */ - -/*********************************************************************//** - * @brief Initial for ADC - * + Set bit PCADC - * + Set clock for ADC - * + Set Clock Frequency - * @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC - * @param[in] rate ADC conversion rate, should be <=200KHz - * @return None - **********************************************************************/ -void ADC_Init(LPC_ADC_TypeDef *ADCx, uint32_t rate) -{ - uint32_t ADCPClk, temp, tmp; - - // Turn on power and clock - CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCADC, ENABLE); - - ADCx->CR = 0; - - //Enable PDN bit - tmp = ADC_CR_PDN; - - // Set clock frequency - ADCPClk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER); - - /* The APB clock (PCLK_ADC0) is divided by (CLKDIV+1) to produce the clock for - * A/D converter, which should be less than or equal to 12.4MHz. - * A fully conversion requires 31 of these clocks. - * ADC clock = PCLK_ADC0 / (CLKDIV + 1); - * ADC rate = ADC clock / 31; - */ - temp = rate * 31; - temp = (ADCPClk * 2 + temp)/(2 * temp) - 1; //get the round value by fomular: (2*A + B)/(2*A) - tmp |= ADC_CR_CLKDIV(temp); - - ADCx->CR = tmp; -} - - -/*********************************************************************//** -* @brief Close ADC -* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC -* @return None -**********************************************************************/ -void ADC_DeInit(LPC_ADC_TypeDef *ADCx) -{ - if (ADCx->CR & ADC_CR_START_MASK) //need to stop START bits before DeInit - ADCx->CR &= ~ADC_CR_START_MASK; - // Clear SEL bits - ADCx->CR &= ~0xFF; - - // Clear PDN bit - ADCx->CR &= ~ADC_CR_PDN; - // Turn on power and clock - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCADC, DISABLE); -} - - -/*********************************************************************//** -* @brief Get Result conversion from A/D data register -* @param[in] channel number which want to read back the result -* @return Result of conversion -*********************************************************************/ -uint32_t ADC_GetData(uint32_t channel) -{ - uint32_t adc_value; - - adc_value = *(uint32_t *)((&LPC_ADC->DR[0]) + channel); - return ADC_GDR_RESULT(adc_value); -} - -/*********************************************************************//** -* @brief Set start mode for ADC -* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC -* @param[in] start_mode Start mode choose one of modes in -* 'ADC_START_OPT' enumeration type definition, should be: -* - ADC_START_CONTINUOUS -* - ADC_START_NOW -* - ADC_START_ON_EINT0 -* - ADC_START_ON_CAP01 -* - ADC_START_ON_MAT01 -* - ADC_START_ON_MAT03 -* - ADC_START_ON_MAT10 -* - ADC_START_ON_MAT11 -* @return None -*********************************************************************/ -void ADC_StartCmd(LPC_ADC_TypeDef *ADCx, uint8_t start_mode) -{ - ADCx->CR &= ~ADC_CR_START_MASK; - ADCx->CR |=ADC_CR_START_MODE_SEL((uint32_t)start_mode); -} - - -/*********************************************************************//** -* @brief ADC Burst mode setting -* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC -* @param[in] NewState -* - 1: Set Burst mode -* - 0: reset Burst mode -* @return None -**********************************************************************/ -void ADC_BurstCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState) -{ - ADCx->CR &= ~ADC_CR_BURST; - if (NewState){ - ADCx->CR |= ADC_CR_BURST; - } -} - -/*********************************************************************//** -* @brief Set AD conversion in power mode -* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC -* @param[in] NewState -* - 1: AD converter is optional -* - 0: AD Converter is in power down mode -* @return None -**********************************************************************/ -void ADC_PowerdownCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState) -{ - ADCx->CR &= ~ADC_CR_PDN; - if (NewState){ - ADCx->CR |= ADC_CR_PDN; - } -} - -/*********************************************************************//** -* @brief Set Edge start configuration -* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC -* @param[in] EdgeOption is ADC_START_ON_RISING and ADC_START_ON_FALLING -* 0:ADC_START_ON_RISING -* 1:ADC_START_ON_FALLING -* @return None -**********************************************************************/ -void ADC_EdgeStartConfig(LPC_ADC_TypeDef *ADCx, uint8_t EdgeOption) -{ - ADCx->CR &= ~ADC_CR_EDGE; - if (EdgeOption){ - ADCx->CR |= ADC_CR_EDGE; - } -} - -/*********************************************************************//** -* @brief ADC interrupt configuration -* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC -* @param[in] IntType: type of interrupt, should be: -* - ADC_ADINTEN0: Interrupt channel 0 -* - ADC_ADINTEN1: Interrupt channel 1 -* ... -* - ADC_ADINTEN7: Interrupt channel 7 -* - ADC_ADGINTEN: Individual channel/global flag done generate an interrupt -* @param[in] NewState: -* - SET : enable ADC interrupt -* - RESET: disable ADC interrupt -* @return None -**********************************************************************/ -void ADC_IntConfig (LPC_ADC_TypeDef *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState) -{ - ADCx->INTEN &= ~ADC_INTEN_CH(IntType); - if (NewState){ - ADCx->INTEN |= ADC_INTEN_CH(IntType); - } -} - -/*********************************************************************//** -* @brief Enable/Disable ADC channel number -* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC -* @param[in] Channel channel number -* @param[in] NewState Enable or Disable -* -* @return None -**********************************************************************/ -void ADC_ChannelCmd (LPC_ADC_TypeDef *ADCx, uint8_t Channel, FunctionalState NewState) -{ - if (NewState == ENABLE) { - ADCx->CR |= ADC_CR_CH_SEL(Channel); - } else { - if (ADCx->CR & ADC_CR_START_MASK) //need to stop START bits before disable channel - ADCx->CR &= ~ADC_CR_START_MASK; - ADCx->CR &= ~ADC_CR_CH_SEL(Channel); - } -} - -/*********************************************************************//** -* @brief Get ADC result -* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC -* @param[in] channel: channel number, should be 0...7 -* @return Data conversion -**********************************************************************/ -uint16_t ADC_ChannelGetData(LPC_ADC_TypeDef *ADCx, uint8_t channel) -{ - uint32_t adc_value; - adc_value = *(uint32_t *) ((&ADCx->DR[0]) + channel); - return ADC_DR_RESULT(adc_value); -} - -/*********************************************************************//** -* @brief Get ADC Chanel status from ADC data register -* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC -* @param[in] channel: channel number, should be 0..7 -* @param[in] StatusType -* 0:Burst status -* 1:Done status -* @return SET / RESET -**********************************************************************/ -FlagStatus ADC_ChannelGetStatus(LPC_ADC_TypeDef *ADCx, uint8_t channel, uint32_t StatusType) -{ - uint32_t temp; - temp = *(uint32_t *) ((&ADCx->DR[0]) + channel); - if (StatusType) - { - temp &= ADC_DR_DONE_FLAG; - } - else - { - temp &= ADC_DR_OVERRUN_FLAG; - } - - if (temp) - { - return SET; - } - else - { - return RESET; - } - -} - -/*********************************************************************//** -* @brief Get ADC Data from AD Global register -* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC -* @return Result of conversion -**********************************************************************/ -uint32_t ADC_GlobalGetData(LPC_ADC_TypeDef *ADCx) -{ - return ((uint32_t)(ADCx->GDR)); -} - -/*********************************************************************//** -* @brief Get ADC Chanel status from AD global data register -* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC -* @param[in] StatusType -* 0:Burst status -* 1:Done status -* @return SET / RESET -**********************************************************************/ -FlagStatus ADC_GlobalGetStatus(LPC_ADC_TypeDef *ADCx, uint32_t StatusType) -{ - uint32_t temp; - - temp = ADCx->GDR; - if (StatusType){ - temp &= ADC_DR_DONE_FLAG; - }else{ - temp &= ADC_DR_OVERRUN_FLAG; - } - if (temp){ - return SET; - }else{ - return RESET; - } -} - -/** - * @} - */ -#endif /*_ADC*/ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_bod.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_bod.c deleted file mode 100644 index 050d12ebdfb..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_bod.c +++ /dev/null @@ -1,119 +0,0 @@ -/********************************************************************** -* $Id$ lpc_bod.c 2011-12-09 -*//** -* @file lpc_bod.c -* @brief Contain functions related to BOD. -* @version 1.0 -* @date 09 December. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup BOD - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _BOD -#include "LPC407x_8x_177x_8x.h" /* LPC407x_8x_177x_8x Peripheral Registers */ -#include "lpc_bod.h" - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup BOD_Public_Functions - * @{ - */ -/*********************************************************************//** - * @brief Initialize BOD control register - * @param[in] pConfig BOD Configuration - * @return None - **********************************************************************/ -void BOD_Init( BOD_Config_Type* pConfig ) -{ - /* Turn on/off BOD. */ - if(pConfig->Enabled == DISABLE) - { - LPC_SC->PCON |= BOD_PCON_BOGD; - return; - } - LPC_SC->PCON &= ~BOD_PCON_BOGD; - - /* Brown-Out Reduced Power Mode */ - if(pConfig->PowerReduced == ENABLE) - { - LPC_SC->PCON |= BOD_PCON_BODRPM; - } - else - { - LPC_SC->PCON &= ~BOD_PCON_BODRPM; - } - - /* Brown-Out Reset */ - if(pConfig->ResetOnVoltageDown == DISABLE) - { - LPC_SC->PCON |= BOD_PCON_BORD; - } - else - { - LPC_SC->PCON &= ~BOD_PCON_BORD; - } - - /* Enable the BOD Interrupt */ - NVIC_EnableIRQ(BOD_IRQn); - - return; -} - - -/*********************************************************************//** - * @brief Get BOD reset source status - * @param[in] None - * @return TRUE/FALSE - **********************************************************************/ -int32_t BOD_ResetSourceStatus( void ) -{ - if((LPC_SC->RSID & BOD_RSID_POR) == 1) - return DISABLE; - return ((LPC_SC->RSID & BOD_RSID_BODR)? ENABLE:DISABLE); -} -/*********************************************************************//** - * @brief Clear BOD reset source bit - * @param[in] None - * @return None - **********************************************************************/ -void BOD_ResetSourceClr( void ) -{ - LPC_SC->RSID |= BOD_RSID_BODR; -} -/** - * @} - */ -#endif /*_BOD */ -/** - * @} - */ -/****************************************************************************** -** End Of File -******************************************************************************/ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_can.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_can.c deleted file mode 100644 index 26776179e40..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_can.c +++ /dev/null @@ -1,2197 +0,0 @@ -/********************************************************************** -* $Id$ lpc_can.c 2011-06-02 -*//** -* @file lpc_can.c -* @brief Contains all functions support for CAN firmware library on -* LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup CAN - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _CAN - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_can.h" -#include "lpc_clkpwr.h" - -/* Private Variables ---------------------------------------------------------- */ -/** @defgroup CAN_Private_Variables CAN Private Variables - * @{ - */ - -FunctionalState FULLCAN_ENABLE; - - -/* Counts number of filters (CAN message objects) used */ -uint16_t CANAF_FullCAN_cnt = 0; -uint16_t CANAF_std_cnt = 0; -uint16_t CANAF_gstd_cnt = 0; -uint16_t CANAF_ext_cnt = 0; -uint16_t CANAF_gext_cnt = 0; - -/* End of Private Variables ----------------------------------------------------*/ -/** - * @} - */ - -/* Private Variables ---------------------------------------------------------- */ -static LPC_CAN_TypeDef* CAN_GetPointer (uint8_t canId); - - -static void can_SetBaudrate (LPC_CAN_TypeDef *CANx, uint32_t baudrate); - -/*********************************************************************//** - * @brief Setting CAN baud rate (bps) - * @param[in] canId point to LPC_CAN_TypeDef object, should be: - * - LPC_CAN1: CAN1 peripheral - * - LPC_CAN2: CAN2 peripheral - * @return The pointer to CAN peripheral that's expected to use - ***********************************************************************/ -static LPC_CAN_TypeDef* CAN_GetPointer (uint8_t canId) -{ - LPC_CAN_TypeDef* pCan; - - switch (canId) - { - case CAN_ID_1: - pCan = LPC_CAN1; - break; - - case CAN_ID_2: - pCan = LPC_CAN2; - break; - - default: - pCan = NULL; - break; - } - - return pCan; -} - - -/*********************************************************************//** - * @brief Setting CAN baud rate (bps) - * @param[in] CANx point to LPC_CAN_TypeDef object, should be: - * - LPC_CAN1: CAN1 peripheral - * - LPC_CAN2: CAN2 peripheral - * @param[in] baudrate: is the baud rate value will be set - * @return None - ***********************************************************************/ -static void can_SetBaudrate (LPC_CAN_TypeDef *CANx, uint32_t baudrate) -{ - uint32_t result = 0; - uint8_t NT, TSEG1, TSEG2; - uint32_t CANPclk = 0; - uint32_t BRP; - - CANPclk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER); - - result = CANPclk / baudrate; - - /* Calculate suitable nominal time value - * NT (nominal time) = (TSEG1 + TSEG2 + 3) - * NT <= 24 - * TSEG1 >= 2*TSEG2 - */ - for(NT = 24; NT > 0; NT = NT-2) - { - if ((result%NT) == 0) - { - BRP = result / NT - 1; - - NT--; - - TSEG2 = (NT/3) - 1; - - TSEG1 = NT -(NT/3) - 1; - - break; - } - } - - /* Enter reset mode */ - CANx->MOD = 0x01; - - /* Set bit timing - * Default: SAM = 0x00; - * SJW = 0x03; - */ - CANx->BTR = (TSEG2 << 20) | (TSEG1 << 16) | (3 << 14) | BRP; - - /* Return to normal operating */ - CANx->MOD = 0; -} -/* End of Private Functions ----------------------------------------------------*/ - - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup CAN_Public_Functions - * @{ - */ - -/********************************************************************//** - * @brief Initialize CAN peripheral with given baudrate - * @param[in] canId The Id of the expected CAN component - * - * @param[in] baudrate: the value of CAN baudrate will be set (bps) - * @return None - *********************************************************************/ -void CAN_Init(uint8_t canId, uint32_t baudrate) -{ - LPC_CAN_TypeDef* pCan = CAN_GetPointer(canId); - - uint16_t i; - - if(canId == CAN_ID_1) - { - /* Turn on power and clock for CAN1 */ - CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCAN1, ENABLE); - } - else if(canId == CAN_ID_2) - { - /* Turn on power and clock for CAN2 */ - CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCAN2, ENABLE); - } - else - { - return; - } - - pCan->MOD = 1; // Enter Reset Mode - pCan->IER = 0; // Disable All CAN Interrupts - pCan->GSR = 0; - - /* Request command to release Rx, Tx buffer and clear data overrun */ - //pCan->CMR = CAN_CMR_AT | CAN_CMR_RRB | CAN_CMR_CDO; - pCan->CMR = (1 << 1) | (1 << 2) | (1 << 3); - - /* Read to clear interrupt pending in interrupt capture register */ - i = pCan->ICR; - pCan->MOD = 0;// Return Normal operating - - //Reset CANAF value - LPC_CANAF->AFMR = 0x01; - - //clear ALUT RAM - for (i = 0; i < 512; i++) - { - LPC_CANAF_RAM->mask[i] = 0x00; - } - - LPC_CANAF->SFF_sa = 0x00; - LPC_CANAF->SFF_GRP_sa = 0x00; - LPC_CANAF->EFF_sa = 0x00; - LPC_CANAF->EFF_GRP_sa = 0x00; - LPC_CANAF->ENDofTable = 0x00; - - LPC_CANAF->AFMR = 0x00; - - /* Set baudrate */ - can_SetBaudrate (pCan, baudrate); -} - -/********************************************************************//** - * @brief CAN deInit - * @param[in] canId The Id of the expected CAN component - * - * @return None - *********************************************************************/ -void CAN_DeInit(uint8_t canId) -{ - if(canId == CAN_ID_1) - { - /* Turn on power and clock for CAN1 */ - CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCAN1, DISABLE); - } - else if(canId == CAN_ID_2) - { - /* Turn on power and clock for CAN1 */ - CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCAN2, DISABLE); - } - - return; -} - -/********************************************************************//** - * @brief Setup Acceptance Filter Look-Up Table - * @param[in] CANAFx pointer to LPC_CANAF_TypeDef - * Should be: LPC_CANAF - * @param[in] AFSection the pointer to AF_SectionDef structure - * It contain information about 5 sections will be install in AFLUT - * @return CAN Error could be: - * - CAN_OBJECTS_FULL_ERROR: No more rx or tx objects available - * - CAN_AF_ENTRY_ERROR: table error-violation of ascending numerical order - * - CAN_OK: ID is added into table successfully - *********************************************************************/ -CAN_ERROR CAN_SetupAFLUT(AF_SectionDef* AFSection) -{ - uint8_t ctrl1,ctrl2; - uint8_t dis1, dis2; - uint16_t SID, ID_temp,i, count = 0; - uint32_t EID, entry, buf; - uint16_t lowerSID, upperSID; - uint32_t lowerEID, upperEID; - - LPC_CANAF->AFMR = 0x01; - - /***** setup FullCAN Table *****/ - if(AFSection->FullCAN_Sec == NULL) - { - FULLCAN_ENABLE = DISABLE; - } - else - { - FULLCAN_ENABLE = ENABLE; - - for(i = 0; i < (AFSection->FC_NumEntry); i++) - { - if(count + 1 > 64) - { - return CAN_OBJECTS_FULL_ERROR; - } - - ctrl1 = AFSection->FullCAN_Sec->controller; - - SID = AFSection->FullCAN_Sec->id_11; - - dis1 = AFSection->FullCAN_Sec->disable; - - entry = 0x00; //reset entry value - - if((CANAF_FullCAN_cnt & 0x00000001)==0) - { - if(count != 0x00) - { - buf = LPC_CANAF_RAM->mask[count-1]; - ID_temp = (buf & 0xE7FF); //mask controller & identifier bits - if(ID_temp > ((ctrl1<<13)|SID)) - { - return CAN_AF_ENTRY_ERROR; - } - } - - entry = (ctrl1<<29)|(dis1<<28)|(SID<<16)|(1<<27); - - LPC_CANAF_RAM->mask[count] &= 0x0000FFFF; - - LPC_CANAF_RAM->mask[count] |= entry; - - CANAF_FullCAN_cnt++; - if(CANAF_FullCAN_cnt == AFSection->FC_NumEntry) //this is the lastest FullCAN entry - count++; - } - else - { - buf = LPC_CANAF_RAM->mask[count]; - ID_temp = (buf >>16) & 0xE7FF; - if(ID_temp > ((ctrl1<<13)|SID)) - { - return CAN_AF_ENTRY_ERROR; - } - - entry = (ctrl1 << 13) | (dis1 << 12) | (SID << 0) | (1 << 11); - - LPC_CANAF_RAM->mask[count] &= 0xFFFF0000; - - LPC_CANAF_RAM->mask[count]|= entry; - - count++; - - CANAF_FullCAN_cnt++; - } - - AFSection->FullCAN_Sec = (FullCAN_Entry *)((uint32_t)(AFSection->FullCAN_Sec)+ sizeof(FullCAN_Entry)); - } - } - - /***** Setup Explicit Standard Frame Format Section *****/ - if(AFSection->SFF_Sec != NULL) - { - for(i=0;i<(AFSection->SFF_NumEntry);i++) - { - if(count + 1 > 512) - { - return CAN_OBJECTS_FULL_ERROR; - } - - ctrl1 = AFSection->SFF_Sec->controller; - - SID = AFSection->SFF_Sec->id_11; - - dis1 = AFSection->SFF_Sec->disable; - - entry = 0x00; //reset entry value - - if((CANAF_std_cnt & 0x00000001)==0) - { - if(CANAF_std_cnt !=0 ) - { - buf = LPC_CANAF_RAM->mask[count-1]; - ID_temp = (buf & 0xE7FF); //mask controller & identifier bits - if(ID_temp > ((ctrl1<<13)|SID)) - { - return CAN_AF_ENTRY_ERROR; - } - } - - entry = (ctrl1<<29)|(dis1<<28)|(SID<<16); - - LPC_CANAF_RAM->mask[count] &= 0x0000FFFF; - - LPC_CANAF_RAM->mask[count] |= entry; - - CANAF_std_cnt++; - if(CANAF_std_cnt == AFSection->SFF_NumEntry)//if this is the last SFF entry - count++; - } - else - { - buf = LPC_CANAF_RAM->mask[count]; - ID_temp = (buf >>16) & 0xE7FF; - if(ID_temp > ((ctrl1<<13)|SID)) - { - return CAN_AF_ENTRY_ERROR; - } - - entry = (ctrl1 << 13) | (dis1 << 12) | (SID << 0); - - LPC_CANAF_RAM->mask[count] &= 0xFFFF0000; - - LPC_CANAF_RAM->mask[count] |= entry; - - count++; - - CANAF_std_cnt++; - } - - AFSection->SFF_Sec = (SFF_Entry *)((uint32_t)(AFSection->SFF_Sec)+ sizeof(SFF_Entry)); - } - } - - /***** Setup Group of Standard Frame Format Identifier Section *****/ - if(AFSection->SFF_GPR_Sec != NULL) - { - for(i=0;i<(AFSection->SFF_GPR_NumEntry);i++) - { - if(count + 1 > 512) - { - return CAN_OBJECTS_FULL_ERROR; - } - - ctrl1 = AFSection->SFF_GPR_Sec->controller1; - - ctrl2 = AFSection->SFF_GPR_Sec->controller2; - - dis1 = AFSection->SFF_GPR_Sec->disable1; - - dis2 = AFSection->SFF_GPR_Sec->disable2; - - lowerSID = AFSection->SFF_GPR_Sec->lowerID; - - upperSID = AFSection->SFF_GPR_Sec->upperID; - - entry = 0x00; - - if(CANAF_gstd_cnt!=0) - { - buf = LPC_CANAF_RAM->mask[count-1]; - ID_temp = buf & 0xE7FF; - if((ctrl1 != ctrl2)||(lowerSID > upperSID)||(ID_temp > ((ctrl1<<13)|lowerSID))) - { - return CAN_AF_ENTRY_ERROR; - } - } - entry = (ctrl1 << 29)|(dis1 << 28)|(lowerSID << 16)| \ - (ctrl2 << 13)|(dis2 << 12)|(upperSID << 0); - LPC_CANAF_RAM->mask[count] = entry; - - CANAF_gstd_cnt++; - - count++; - - AFSection->SFF_GPR_Sec = (SFF_GPR_Entry *)((uint32_t)(AFSection->SFF_GPR_Sec)+ sizeof(SFF_GPR_Entry)); - } - } - - /***** Setup Explicit Extend Frame Format Identifier Section *****/ - if(AFSection->EFF_Sec != NULL) - { - for(i=0;i<(AFSection->EFF_NumEntry);i++) - { - if(count + 1 > 512) - { - return CAN_OBJECTS_FULL_ERROR; - } - - EID = AFSection->EFF_Sec->ID_29; - - ctrl1 = AFSection->EFF_Sec->controller; - - entry = 0x00; //reset entry value - - entry = (ctrl1 << 29)|(EID << 0); - if(CANAF_ext_cnt != 0) - { - buf = LPC_CANAF_RAM->mask[count-1]; -// EID_temp = buf & 0x0FFFFFFF; - if(buf > entry) - { - return CAN_AF_ENTRY_ERROR; - } - } - LPC_CANAF_RAM->mask[count] = entry; - - CANAF_ext_cnt ++; - - count++; - - AFSection->EFF_Sec = (EFF_Entry *)((uint32_t)(AFSection->EFF_Sec)+ sizeof(EFF_Entry)); - } - } - - /***** Setup Group of Extended Frame Format Identifier Section *****/ - if(AFSection->EFF_GPR_Sec != NULL) - { - for(i=0;i<(AFSection->EFF_GPR_NumEntry);i++) - { - if(count + 2 > 512) - { - return CAN_OBJECTS_FULL_ERROR; - } - - ctrl1 = AFSection->EFF_GPR_Sec->controller1; - - ctrl2 = AFSection->EFF_GPR_Sec->controller2; - - lowerEID = AFSection->EFF_GPR_Sec->lowerEID; - - upperEID = AFSection->EFF_GPR_Sec->upperEID; - - entry = 0x00; - - if(CANAF_gext_cnt != 0) - { - buf = LPC_CANAF_RAM->mask[count-1]; -// EID_temp = buf & 0x0FFFFFFF; - if((ctrl1 != ctrl2) || (lowerEID > upperEID) || (buf > ((ctrl1 << 29)|(lowerEID << 0)))) - { - return CAN_AF_ENTRY_ERROR; - } - } - - entry = (ctrl1 << 29)|(lowerEID << 0); - - LPC_CANAF_RAM->mask[count++] = entry; - - entry = (ctrl2 << 29)|(upperEID << 0); - - LPC_CANAF_RAM->mask[count++] = entry; - - CANAF_gext_cnt++; - - AFSection->EFF_GPR_Sec = (EFF_GPR_Entry *)((uint32_t)(AFSection->EFF_GPR_Sec)+ sizeof(EFF_GPR_Entry)); - } - } - - //update address values - LPC_CANAF->SFF_sa = ((CANAF_FullCAN_cnt + 1)>>1)<<2; - - LPC_CANAF->SFF_GRP_sa = LPC_CANAF->SFF_sa + (((CANAF_std_cnt+1)>>1)<< 2); - - LPC_CANAF->EFF_sa = LPC_CANAF->SFF_GRP_sa + (CANAF_gstd_cnt << 2); - - LPC_CANAF->EFF_GRP_sa = LPC_CANAF->EFF_sa + (CANAF_ext_cnt << 2); - - LPC_CANAF->ENDofTable = LPC_CANAF->EFF_GRP_sa + (CANAF_gext_cnt << 3); - - if(FULLCAN_ENABLE == DISABLE) - { - LPC_CANAF->AFMR = 0x00; // Normal mode - } - else - { - LPC_CANAF->AFMR = 0x04; - } - - return CAN_OK; -} -/********************************************************************//** - * @brief Add Explicit ID into AF Look-Up Table dynamically. - * @param[in] canId The Id of the expected CAN component - * - * @param[in] id: The ID of entry will be added - * @param[in] format: is the type of ID Frame Format, should be: - * - STD_ID_FORMAT: 11-bit ID value - * - EXT_ID_FORMAT: 29-bit ID value - * @return CAN Error, could be: - * - CAN_OBJECTS_FULL_ERROR: No more rx or tx objects available - * - CAN_ID_EXIT_ERROR: ID exited in table - * - CAN_OK: ID is added into table successfully - *********************************************************************/ -CAN_ERROR CAN_LoadExplicitEntry(uint8_t canId, uint32_t id, CAN_ID_FORMAT_Type format) -{ - uint32_t buf0 = 0, buf1 = 0; - int16_t cnt1 = 0, cnt2 = 0, bound1 = 0, total = 0; - - /* Acceptance Filter Memory full - return */ - total =((CANAF_FullCAN_cnt + 1) >> 1) + CANAF_FullCAN_cnt * 3 + ((CANAF_std_cnt + 1) >> 1) \ - + CANAF_gstd_cnt + CANAF_ext_cnt + (CANAF_gext_cnt << 1); - - if (total >= 512) - { - //don't have enough space - return CAN_OBJECTS_FULL_ERROR; - } - - /* Setup Acceptance Filter Configuration - Acceptance Filter Mode Register = Off */ - LPC_CANAF->AFMR = 0x00000001; - - /*********** Add Explicit Standard Identifier Frame Format entry *********/ - if(format == STD_ID_FORMAT) - { - id &= 0x07FF; - - id |= canId << 13;/* Add controller number */ - - /* Move all remaining sections one place up - if new entry will increase FullCAN list */ - if ((CANAF_std_cnt & 0x0001) == 0) - { - cnt1 = ((CANAF_FullCAN_cnt+1)>>1)+((CANAF_std_cnt+1)>>1); - - bound1 = total - cnt1; - - buf0 = LPC_CANAF_RAM->mask[cnt1]; - - while(bound1--) - { - cnt1++; - - buf1 = LPC_CANAF_RAM->mask[cnt1]; - - LPC_CANAF_RAM->mask[cnt1] = buf0; - - buf0 = buf1; - } - } - - if (CANAF_std_cnt == 0) - { - cnt2 = (CANAF_FullCAN_cnt + 1)>>1; - - /* For entering first ID */ - LPC_CANAF_RAM->mask[cnt2] = 0x0000FFFF | (id << 16); - } - else if (CANAF_std_cnt == 1) - { - cnt2 = (CANAF_FullCAN_cnt + 1) >> 1; - - /* For entering second ID */ - if (((LPC_CANAF_RAM->mask[cnt2] >> 16)& 0xE7FF) > id) - { - LPC_CANAF_RAM->mask[cnt2] = (LPC_CANAF_RAM->mask[cnt2] >> 16) | (id << 16); - } - else - { - LPC_CANAF_RAM->mask[cnt2] = (LPC_CANAF_RAM->mask[cnt2] & 0xFFFF0000) | id; - } - } - else - { - /* Find where to insert new ID */ - cnt1 = (CANAF_FullCAN_cnt+1)>>1; - - cnt2 = CANAF_std_cnt; - - bound1 = ((CANAF_FullCAN_cnt+1)>>1)+((CANAF_std_cnt+1)>>1); - - while (cnt1 < bound1) - { - /* Loop through standard existing IDs */ - if (((LPC_CANAF_RAM->mask[cnt1] >> 16) & 0xE7FF) > id) - { - cnt2 = cnt1 * 2; - break; - } - - if ((LPC_CANAF_RAM->mask[cnt1] & 0x0000E7FF) > id) - { - cnt2 = cnt1 * 2 + 1; - break; - } - - cnt1++; - } - - /* cnt1 = U32 where to insert new ID */ - /* cnt2 = U16 where to insert new ID */ - - if (cnt1 == bound1) - { - /* Adding ID as last entry */ - /* Even number of IDs exists */ - if ((CANAF_std_cnt & 0x0001) == 0) - { - LPC_CANAF_RAM->mask[cnt1] = 0x0000FFFF | (id << 16); - } - /* Odd number of IDs exists */ - else - { - LPC_CANAF_RAM->mask[cnt1] = (LPC_CANAF_RAM->mask[cnt1] & 0xFFFF0000) | id; - } - } - else - { - buf0 = LPC_CANAF_RAM->mask[cnt1]; /* Remember current entry */ - - if ((cnt2 & 0x0001) == 0) - { - /* Insert new mask to even address*/ - buf1 = (id << 16) | (buf0 >> 16); - } - else - { - /* Insert new mask to odd address */ - buf1 = (buf0 & 0xFFFF0000) | id; - } - - LPC_CANAF_RAM->mask[cnt1] = buf1;/* Insert mask */ - - bound1 = ((CANAF_FullCAN_cnt + 1) >> 1) + ((CANAF_std_cnt+1) >> 1) - 1; - - /* Move all remaining standard mask entries one place up */ - while (cnt1 < bound1) - { - cnt1++; - - buf1 = LPC_CANAF_RAM->mask[cnt1]; - - LPC_CANAF_RAM->mask[cnt1] = (buf1 >> 16) | (buf0 << 16); - - buf0 = buf1; - } - - if ((CANAF_std_cnt & 0x0001) == 0) - { - /* Even number of IDs exists */ - LPC_CANAF_RAM->mask[cnt1+1] = (buf0 <<16) |(0x0000FFFF); - } - } - } - - CANAF_std_cnt++; - - //update address values - LPC_CANAF->SFF_GRP_sa += 0x04 ; - - LPC_CANAF->EFF_sa += 0x04 ; - - LPC_CANAF->EFF_GRP_sa += 0x04; - - LPC_CANAF->ENDofTable += 0x04; - } - - /*********** Add Explicit Extended Identifier Frame Format entry *********/ - else - { - /* Add controller number */ - id |= canId << 29; - - cnt1 = ((CANAF_FullCAN_cnt+1) >> 1) + (((CANAF_std_cnt + 1) >> 1) + CANAF_gstd_cnt); - - cnt2 = 0; - - while (cnt2 < CANAF_ext_cnt) - { - /* Loop through extended existing masks*/ - if (LPC_CANAF_RAM->mask[cnt1] > id) - { - break; - } - - cnt1++;/* cnt1 = U32 where to insert new mask */ - - cnt2++; - } - - buf0 = LPC_CANAF_RAM->mask[cnt1]; /* Remember current entry */ - - LPC_CANAF_RAM->mask[cnt1] = id; /* Insert mask */ - - CANAF_ext_cnt++; - - bound1 = total; - - /* Move all remaining extended mask entries one place up*/ - while (cnt2 < bound1) - { - cnt1++; - - cnt2++; - - buf1 = LPC_CANAF_RAM->mask[cnt1]; - - LPC_CANAF_RAM->mask[cnt1] = buf0; - - buf0 = buf1; - } - - /* update address values */ - LPC_CANAF->EFF_GRP_sa += 4; - - LPC_CANAF->ENDofTable += 4; - } - - if(CANAF_FullCAN_cnt == 0) //not use FullCAN mode - { - LPC_CANAF->AFMR = 0x00;//not use FullCAN mode - } - else - { - LPC_CANAF->AFMR = 0x04; - } - - return CAN_OK; -} - -/********************************************************************//** - * @brief Load FullCAN entry into AFLUT - * @param[in] canId The Id of the expected CAN component - * - * @param[in] id: identifier of entry that will be added - * @return CAN_ERROR, could be: - * - CAN_OK: loading is successful - * - CAN_ID_EXIT_ERROR: ID exited in FullCAN Section - * - CAN_OBJECTS_FULL_ERROR: no more space available - *********************************************************************/ -CAN_ERROR CAN_LoadFullCANEntry (uint8_t canId, uint16_t id) -{ - uint32_t buf0 = 0, buf1 = 0, buf2 = 0; - uint32_t tmp0 = 0, tmp1 = 0, tmp2 = 0; - int16_t cnt1 = 0, cnt2 = 0, bound1 = 0, total = 0; - - /* Acceptance Filter Memory full - return */ - total =((CANAF_FullCAN_cnt + 1) >> 1) + CANAF_FullCAN_cnt*3 + ((CANAF_std_cnt + 1) >> 1) \ - + CANAF_gstd_cnt + CANAF_ext_cnt + (CANAF_gext_cnt << 1); - - //don't have enough space for this fullCAN Entry and its Object(3*32 bytes) - if ((total >= 508) || (CANAF_FullCAN_cnt >= 64)) - { - return CAN_OBJECTS_FULL_ERROR; - } - - /* Setup Acceptance Filter Configuration - Acceptance Filter Mode Register = Off */ - LPC_CANAF->AFMR = 0x00000001; - - /* Add mask for standard identifiers */ - id &= 0x07FF; - - id |= (canId << 13) | (1 << 11); - - /* Move all remaining sections one place up - if new entry will increase FullCAN list */ - if (((CANAF_FullCAN_cnt & 0x0001) == 0)&&(total!=0)) - { - //then remove remaining section - cnt1 = (CANAF_FullCAN_cnt >> 1); - - bound1 = total; - - buf0 = LPC_CANAF_RAM->mask[cnt1]; - - while (bound1--) - { - cnt1++; - - buf1 = LPC_CANAF_RAM->mask[cnt1]; - - LPC_CANAF_RAM->mask[cnt1] = buf0; - - buf0 = buf1; - } - } - if (CANAF_FullCAN_cnt == 0) - { - /* For entering first ID */ - LPC_CANAF_RAM->mask[0] = 0x0000FFFF | (id << 16); - } - else if (CANAF_FullCAN_cnt == 1) - { - /* For entering second ID */ - if (((LPC_CANAF_RAM->mask[0] >> 16)& 0xE7FF) > id) - { - LPC_CANAF_RAM->mask[0] = (LPC_CANAF_RAM->mask[0] >> 16) | (id << 16); - } - else - { - LPC_CANAF_RAM->mask[0] = (LPC_CANAF_RAM->mask[0] & 0xFFFF0000) | id; - } - } - else - { - /* Find where to insert new ID */ - cnt1 = 0; - - cnt2 = CANAF_FullCAN_cnt; - - bound1 = (CANAF_FullCAN_cnt - 1) >> 1; - - while (cnt1 <= bound1) - { - /* Loop through standard existing IDs */ - if (((LPC_CANAF_RAM->mask[cnt1] >> 16) & 0xE7FF) > (id & 0xE7FF)) - { - cnt2 = cnt1 * 2; - break; - } - - - if ((LPC_CANAF_RAM->mask[cnt1] & 0x0000E7FF) > (id & 0xE7FF)) - { - cnt2 = cnt1 * 2 + 1; - break; - } - - cnt1++; - } - /* cnt1 = U32 where to insert new ID */ - /* cnt2 = U16 where to insert new ID */ - - if (cnt1 > bound1) - { - /* Adding ID as last entry */ - /* Even number of IDs exists */ - if ((CANAF_FullCAN_cnt & 0x0001) == 0) - { - LPC_CANAF_RAM->mask[cnt1] = 0x0000FFFF | (id << 16); - } - /* Odd number of IDs exists */ - else - { - LPC_CANAF_RAM->mask[cnt1] = (LPC_CANAF_RAM->mask[cnt1] & 0xFFFF0000) | id; - } - } - else - { - buf0 = LPC_CANAF_RAM->mask[cnt1]; /* Remember current entry */ - - if ((cnt2 & 0x0001) == 0) - { - /* Insert new mask to even address*/ - buf1 = (id << 16) | (buf0 >> 16); - } - else - { - /* Insert new mask to odd address */ - buf1 = (buf0 & 0xFFFF0000) | id; - } - - LPC_CANAF_RAM->mask[cnt1] = buf1;/* Insert mask */ - - bound1 = CANAF_FullCAN_cnt >> 1; - - /* Move all remaining standard mask entries one place up */ - while (cnt1 < bound1) - { - cnt1++; - - buf1 = LPC_CANAF_RAM->mask[cnt1]; - - LPC_CANAF_RAM->mask[cnt1] = (buf1 >> 16) | (buf0 << 16); - - buf0 = buf1; - } - - if ((CANAF_FullCAN_cnt & 0x0001) == 0) - { - /* Even number of IDs exists */ - LPC_CANAF_RAM->mask[cnt1] = (LPC_CANAF_RAM->mask[cnt1] & 0xFFFF0000) - | (0x0000FFFF); - } - } - } - - //restruct FulCAN Object Section - bound1 = CANAF_FullCAN_cnt - cnt2; - - cnt1 = total - (CANAF_FullCAN_cnt)*3 + cnt2*3 + 1; - - buf0 = LPC_CANAF_RAM->mask[cnt1]; - - buf1 = LPC_CANAF_RAM->mask[cnt1+1]; - - buf2 = LPC_CANAF_RAM->mask[cnt1+2]; - - LPC_CANAF_RAM->mask[cnt1]=LPC_CANAF_RAM->mask[cnt1+1]= LPC_CANAF_RAM->mask[cnt1+2]=0x00; - - cnt1+=3; - - while(bound1--) - { - tmp0 = LPC_CANAF_RAM->mask[cnt1]; - - tmp1 = LPC_CANAF_RAM->mask[cnt1+1]; - - tmp2 = LPC_CANAF_RAM->mask[cnt1+2]; - - LPC_CANAF_RAM->mask[cnt1]= buf0; - - LPC_CANAF_RAM->mask[cnt1+1]= buf1; - - LPC_CANAF_RAM->mask[cnt1+2]= buf2; - - buf0 = tmp0; - - buf1 = tmp1; - - buf2 = tmp2; - - cnt1+=3; - } - - CANAF_FullCAN_cnt++; - - //update address values - LPC_CANAF->SFF_sa += 0x04; - - LPC_CANAF->SFF_GRP_sa += 0x04 ; - - LPC_CANAF->EFF_sa += 0x04 ; - - LPC_CANAF->EFF_GRP_sa += 0x04; - - LPC_CANAF->ENDofTable += 0x04; - - LPC_CANAF->AFMR = 0x04; - - return CAN_OK; -} - -/********************************************************************//** - * @brief Load Group entry into AFLUT - * @param[in] canId The Id of the expected CAN component - * - * @param[in] lowerID, upperID: lower and upper identifier of entry - * @param[in] format: type of ID format, should be: - * - STD_ID_FORMAT: Standard ID format (11-bit value) - * - EXT_ID_FORMAT: Extended ID format (29-bit value) - * @return CAN_ERROR, could be: - * - CAN_OK: loading is successful - * - CAN_CONFLICT_ID_ERROR: Conflict ID occurs - * - CAN_OBJECTS_FULL_ERROR: no more space available - *********************************************************************/ -CAN_ERROR CAN_LoadGroupEntry(uint8_t canId, uint32_t lowerID, - uint32_t upperID, CAN_ID_FORMAT_Type format) -{ - uint32_t buf0, buf1, entry1, entry2, LID,UID; - int16_t cnt1, bound1, total; - - if(lowerID > upperID) - return CAN_CONFLICT_ID_ERROR; - - total =((CANAF_FullCAN_cnt+1) >> 1)+ CANAF_FullCAN_cnt*3 +((CANAF_std_cnt + 1) >> 1) \ - + CANAF_gstd_cnt + CANAF_ext_cnt + (CANAF_gext_cnt<<1); - - /* Setup Acceptance Filter Configuration - Acceptance Filter Mode Register = Off */ - LPC_CANAF->AFMR = 0x00000001; - - /*********Add Group of Standard Identifier Frame Format************/ - if(format == STD_ID_FORMAT) - { - if ((total >= 512)) - { - //don't have enough space - return CAN_OBJECTS_FULL_ERROR; - } - - lowerID &=0x7FF; //mask ID - - upperID &=0x7FF; - - entry1 = (canId << 29) | (lowerID << 16) | (canId << 13)|(upperID << 0); - - cnt1 = ((CANAF_FullCAN_cnt+1)>>1) + ((CANAF_std_cnt + 1) >> 1); - - //if this is the first Group standard ID entry - if(CANAF_gstd_cnt == 0) - { - LPC_CANAF_RAM->mask[cnt1] = entry1; - } - else - { - //find the position to add new Group entry - bound1 = ((CANAF_FullCAN_cnt+1)>>1) + ((CANAF_std_cnt + 1) >> 1) + CANAF_gstd_cnt; - - while(cnt1 < bound1) - { - //compare controller first - while((LPC_CANAF_RAM->mask[cnt1] >> 29)< (entry1 >> 29))//increase until meet greater or equal controller - cnt1++; - buf0 = LPC_CANAF_RAM->mask[cnt1]; - if((LPC_CANAF_RAM->mask[cnt1] >> 29)> (entry1 >> 29)) //meet greater controller - { - //add at this position - LPC_CANAF_RAM->mask[cnt1] = entry1; - break; - } - else //meet equal controller - { - LID = (buf0 >> 16)&0x7FF; - UID = buf0 & 0x7FF; - if (upperID <= LID) - { - //add new entry before this entry - LPC_CANAF_RAM->mask[cnt1] = entry1; - break; - } - else if (lowerID >= UID) - { - //load next entry to compare - cnt1 ++; - } - else - return CAN_CONFLICT_ID_ERROR; - } - } - if(cnt1 >= bound1) - { - //add new entry at the last position in this list - buf0 = LPC_CANAF_RAM->mask[cnt1]; - - LPC_CANAF_RAM->mask[cnt1] = entry1; - } - - //remove all remaining entry of this section one place up - bound1 = total - cnt1; - - while(bound1--) - { - cnt1++; - - buf1 = LPC_CANAF_RAM->mask[cnt1]; - - LPC_CANAF_RAM->mask[cnt1] = buf0; - - buf0 = buf1; - } - } - - CANAF_gstd_cnt++; - - //update address values - LPC_CANAF->EFF_sa +=0x04 ; - - LPC_CANAF->EFF_GRP_sa +=0x04; - - LPC_CANAF->ENDofTable +=0x04; - } - - - /*********Add Group of Extended Identifier Frame Format************/ - else - { - if ((total >= 511)) - { - //don't have enough space - return CAN_OBJECTS_FULL_ERROR; - } - - lowerID &= 0x1FFFFFFF; //mask ID - - upperID &= 0x1FFFFFFF; - - entry1 = (canId << 29)|(lowerID << 0); - - entry2 = (canId << 29)|(upperID << 0); - - cnt1 = ((CANAF_FullCAN_cnt+1)>>1) + ((CANAF_std_cnt + 1) >> 1) + CANAF_gstd_cnt + CANAF_ext_cnt; - - //if this is the first Group standard ID entry - if(CANAF_gext_cnt == 0) - { - LPC_CANAF_RAM->mask[cnt1] = entry1; - - LPC_CANAF_RAM->mask[cnt1+1] = entry2; - } - else - { - //find the position to add new Group entry - bound1 = ((CANAF_FullCAN_cnt+1)>>1) + ((CANAF_std_cnt + 1) >> 1) + CANAF_gstd_cnt \ - + CANAF_ext_cnt + (CANAF_gext_cnt<<1); - - while(cnt1 < bound1) - { - while((LPC_CANAF_RAM->mask[cnt1] >>29)< canId) //increase until meet greater or equal controller - cnt1++; - buf0 = LPC_CANAF_RAM->mask[cnt1]; - - buf1 = LPC_CANAF_RAM->mask[cnt1+1]; - if((LPC_CANAF_RAM->mask[cnt1] >> 29)> canId) //meet greater controller - { - //add at this position - LPC_CANAF_RAM->mask[cnt1] = entry1; - LPC_CANAF_RAM->mask[++cnt1] = entry2; - break; - } - else //meet equal controller - { - LID = buf0 & 0x1FFFFFFF; //mask ID - UID = buf1 & 0x1FFFFFFF; - if (upperID <= LID) - { - //add new entry before this entry - LPC_CANAF_RAM->mask[cnt1] = entry1; - LPC_CANAF_RAM->mask[++cnt1] = entry2; - break; - } - else if (lowerID >= UID) - { - //load next entry to compare - cnt1 +=2; - } - else - return CAN_CONFLICT_ID_ERROR; - } - } - if(cnt1 >= bound1) - { - //add new entry at the last position in this list - buf0 = LPC_CANAF_RAM->mask[cnt1]; - - buf1 = LPC_CANAF_RAM->mask[cnt1+1]; - - LPC_CANAF_RAM->mask[cnt1] = entry1; - - LPC_CANAF_RAM->mask[++cnt1] = entry2; - } - - //remove all remaining entry of this section two place up - bound1 = total - cnt1 + 1; - - cnt1++; - - while(bound1>0) - { - entry1 = LPC_CANAF_RAM->mask[cnt1]; - - entry2 = LPC_CANAF_RAM->mask[cnt1+1]; - - LPC_CANAF_RAM->mask[cnt1] = buf0; - - LPC_CANAF_RAM->mask[cnt1+1] = buf1; - - buf0 = entry1; - - buf1 = entry2; - - cnt1 +=2; - - bound1 -=2; - } - } - - CANAF_gext_cnt++; - - //update address values - LPC_CANAF->ENDofTable +=0x08; - } - - LPC_CANAF->AFMR = 0x04; - - return CAN_OK; -} - -/********************************************************************//** - * @brief Remove AFLUT entry (FullCAN entry and Explicit Standard entry) - * @param[in] EntryType: the type of entry that want to remove, should be: - * - FULLCAN_ENTRY - * - EXPLICIT_STANDARD_ENTRY - * - GROUP_STANDARD_ENTRY - * - EXPLICIT_EXTEND_ENTRY - * - GROUP_EXTEND_ENTRY - * @param[in] position: the position of this entry in its section - * Note: the first position is 0 - * @return CAN_ERROR, could be: - * - CAN_OK: removing is successful - * - CAN_ENTRY_NOT_EXIT_ERROR: entry want to remove is not exit - *********************************************************************/ -CAN_ERROR CAN_RemoveEntry(AFLUT_ENTRY_Type EntryType, uint16_t position) -{ - uint16_t cnt, bound, total; - uint32_t buf0, buf1; - - /* Setup Acceptance Filter Configuration - Acceptance Filter Mode Register = Off */ - LPC_CANAF->AFMR = 0x00000001; - - total = ((CANAF_FullCAN_cnt + 1) >> 1) + ((CANAF_std_cnt + 1) >> 1) + \ - + CANAF_gstd_cnt + CANAF_ext_cnt + (CANAF_gext_cnt << 1); - - - /************** Remove FullCAN Entry *************/ - if(EntryType == FULLCAN_ENTRY) - { - if((CANAF_FullCAN_cnt == 0)||(position >= CANAF_FullCAN_cnt)) - { - return CAN_ENTRY_NOT_EXIT_ERROR; - } - else - { - cnt = position >> 1; - - buf0 = LPC_CANAF_RAM->mask[cnt]; - - bound = (CANAF_FullCAN_cnt - position -1)>>1; - - if((position & 0x0001) == 0) //event position - { - while(bound--) - { - //remove all remaining FullCAN entry one place down - buf1 = LPC_CANAF_RAM->mask[cnt+1]; - - LPC_CANAF_RAM->mask[cnt] = (buf1 >> 16) | (buf0 << 16); - - buf0 = buf1; - - cnt++; - } - } - else //odd position - { - while(bound--) - { - //remove all remaining FullCAN entry one place down - buf1 = LPC_CANAF_RAM->mask[cnt+1]; - - LPC_CANAF_RAM->mask[cnt] = (buf0 & 0xFFFF0000)|(buf1 >> 16); - - LPC_CANAF_RAM->mask[cnt+1] = LPC_CANAF_RAM->mask[cnt+1] << 16; - - buf0 = buf1<<16; - - cnt++; - } - } - if((CANAF_FullCAN_cnt & 0x0001) == 0) - { - if((position & 0x0001)==0) - LPC_CANAF_RAM->mask[cnt] = (buf0 << 16) | (0x0000FFFF); - else - LPC_CANAF_RAM->mask[cnt] = buf0 | 0x0000FFFF; - } - else - { - //remove all remaining section one place down - cnt = (CANAF_FullCAN_cnt + 1)>>1; - - bound = total + CANAF_FullCAN_cnt * 3; - - while(bound>cnt) - { - LPC_CANAF_RAM->mask[cnt-1] = LPC_CANAF_RAM->mask[cnt]; - cnt++; - } - - LPC_CANAF_RAM->mask[cnt-1]=0x00; - - //update address values - LPC_CANAF->SFF_sa -= 0x04; - - LPC_CANAF->SFF_GRP_sa -= 0x04 ; - - LPC_CANAF->EFF_sa -= 0x04 ; - - LPC_CANAF->EFF_GRP_sa -= 0x04; - - LPC_CANAF->ENDofTable -= 0x04; - } - - CANAF_FullCAN_cnt--; - - //delete its FullCAN Object in the FullCAN Object section - //remove all remaining FullCAN Object three place down - cnt = total + position * 3; - - bound = (CANAF_FullCAN_cnt - position + 1) * 3; - - while(bound) - { - LPC_CANAF_RAM->mask[cnt]= LPC_CANAF_RAM->mask[cnt+3];; - - LPC_CANAF_RAM->mask[cnt+1]= LPC_CANAF_RAM->mask[cnt+4]; - - LPC_CANAF_RAM->mask[cnt+2]= LPC_CANAF_RAM->mask[cnt+5]; - - bound -= 3; - - cnt += 3; - } - } - } - - /************** Remove Explicit Standard ID Entry *************/ - else if(EntryType == EXPLICIT_STANDARD_ENTRY) - { - if((CANAF_std_cnt == 0)||(position >= CANAF_std_cnt)) - { - return CAN_ENTRY_NOT_EXIT_ERROR; - } - else - { - cnt = ((CANAF_FullCAN_cnt+1) >> 1) + (position >> 1); - - buf0 = LPC_CANAF_RAM->mask[cnt]; - - bound = (CANAF_std_cnt - position - 1) >> 1; - - if((position & 0x0001) == 0) //event position - { - while(bound--) - { - //remove all remaining FullCAN entry one place down - buf1 = LPC_CANAF_RAM->mask[cnt + 1]; - - LPC_CANAF_RAM->mask[cnt] = (buf1 >> 16) | (buf0 << 16); - - buf0 = buf1; - - cnt++; - } - } - else //odd position - { - while(bound--) - { - //remove all remaining FullCAN entry one place down - buf1 = LPC_CANAF_RAM->mask[cnt + 1]; - - LPC_CANAF_RAM->mask[cnt] = (buf0 & 0xFFFF0000) | (buf1 >> 16); - - LPC_CANAF_RAM->mask[cnt + 1] = LPC_CANAF_RAM->mask[cnt + 1] << 16; - - buf0 = buf1<<16; - - cnt++; - } - } - if((CANAF_std_cnt & 0x0001) == 0) - { - if((position & 0x0001)==0) - LPC_CANAF_RAM->mask[cnt] = (buf0 << 16) | (0x0000FFFF); - else - LPC_CANAF_RAM->mask[cnt] = buf0 | 0x0000FFFF; - } - else - { - //remove all remaining section one place down - cnt = ((CANAF_FullCAN_cnt + 1)>>1) + ((CANAF_std_cnt + 1) >> 1); - - bound = total + CANAF_FullCAN_cnt * 3; - - while(bound>cnt) - { - LPC_CANAF_RAM->mask[cnt-1] = LPC_CANAF_RAM->mask[cnt]; - cnt++; - } - - LPC_CANAF_RAM->mask[cnt-1]=0x00; - - //update address value - LPC_CANAF->SFF_GRP_sa -= 0x04 ; - - LPC_CANAF->EFF_sa -= 0x04 ; - - LPC_CANAF->EFF_GRP_sa -= 0x04; - - LPC_CANAF->ENDofTable -= 0x04; - } - - CANAF_std_cnt--; - } - } - - /************** Remove Group of Standard ID Entry *************/ - else if(EntryType == GROUP_STANDARD_ENTRY) - { - if((CANAF_gstd_cnt == 0)||(position >= CANAF_gstd_cnt)) - { - return CAN_ENTRY_NOT_EXIT_ERROR; - } - else - { - cnt = ((CANAF_FullCAN_cnt + 1) >> 1) + ((CANAF_std_cnt + 1) >> 1)+ position + 1; - - bound = total + CANAF_FullCAN_cnt * 3; - - while (cnt < bound) - { - LPC_CANAF_RAM->mask[cnt - 1] = LPC_CANAF_RAM->mask[cnt]; - cnt++; - } - LPC_CANAF_RAM->mask[cnt - 1]=0x00; - } - - CANAF_gstd_cnt--; - - //update address value - LPC_CANAF->EFF_sa -= 0x04; - - LPC_CANAF->EFF_GRP_sa -= 0x04; - - LPC_CANAF->ENDofTable -= 0x04; - } - - /************** Remove Explicit Extended ID Entry *************/ - else if(EntryType == EXPLICIT_EXTEND_ENTRY) - { - if((CANAF_ext_cnt == 0)||(position >= CANAF_ext_cnt)) - { - return CAN_ENTRY_NOT_EXIT_ERROR; - } - else - { - cnt = ((CANAF_FullCAN_cnt + 1) >> 1) + ((CANAF_std_cnt + 1) >> 1)+ CANAF_gstd_cnt + position + 1; - - bound = total + CANAF_FullCAN_cnt * 3; - - while (cntmask[cnt - 1] = LPC_CANAF_RAM->mask[cnt]; - cnt++; - } - LPC_CANAF_RAM->mask[cnt - 1]=0x00; - } - - CANAF_ext_cnt--; - - LPC_CANAF->EFF_GRP_sa -= 0x04; - - LPC_CANAF->ENDofTable -= 0x04; - } - - /************** Remove Group of Extended ID Entry *************/ - else - { - if((CANAF_gext_cnt == 0)||(position >= CANAF_gext_cnt)) - { - return CAN_ENTRY_NOT_EXIT_ERROR; - } - else - { - cnt = total - (CANAF_gext_cnt << 1) + (position << 1); - - bound = total + CANAF_FullCAN_cnt * 3; - - while (cntmask[cnt] = LPC_CANAF_RAM->mask[cnt + 2]; - - LPC_CANAF_RAM->mask[cnt + 1] = LPC_CANAF_RAM->mask[cnt + 3]; - - cnt += 2; - } - } - - CANAF_gext_cnt--; - - LPC_CANAF->ENDofTable -= 0x08; - } - - LPC_CANAF->AFMR = 0x04; - - return CAN_OK; -} - -/********************************************************************//** - * @brief Send message data - * @param[in] canId The Id of the expected CAN component - * - * @param[in] CAN_Msg point to the CAN_MSG_Type Structure, it contains message - * information such as: ID, DLC, RTR, ID Format - * @return Status: - * - SUCCESS: send message successfully - * - ERROR: send message unsuccessfully - *********************************************************************/ -Status CAN_SendMsg (uint8_t canId, CAN_MSG_Type *CAN_Msg) -{ - LPC_CAN_TypeDef* pCan = CAN_GetPointer(canId); - - uint32_t data; - - //Check status of Transmit Buffer 1 - if (pCan->SR & (1 << 2)) - { - /* Transmit Channel 1 is available */ - /* Write frame informations and frame data into its CANxTFI1, - * CANxTID1, CANxTDA1, CANxTDB1 register */ - pCan->TFI1 &= ~ 0x000F0000; - - pCan->TFI1 |= (CAN_Msg->len) << 16; - - if(CAN_Msg->type == REMOTE_FRAME) - { - pCan->TFI1 |= (1 << 30); //set bit RTR - } - else - { - pCan->TFI1 &= ~(1 << 30); - } - - if(CAN_Msg->format == EXT_ID_FORMAT) - { - pCan->TFI1 |= (((uint32_t)1) << 31); //set bit FF - } - else - { - pCan->TFI1 &= ~(((uint32_t)1) << 31); - } - - /* Write CAN ID*/ - pCan->TID1 = CAN_Msg->id; - - /*Write first 4 data bytes*/ - data = (CAN_Msg->dataA[0]) | (((CAN_Msg->dataA[1]))<< 8) | ((CAN_Msg->dataA[2]) << 16) | ((CAN_Msg->dataA[3]) << 24); - - pCan->TDA1 = data; - - /*Write second 4 data bytes*/ - data = (CAN_Msg->dataB[0]) | (((CAN_Msg->dataB[1])) << 8)|((CAN_Msg->dataB[2]) << 16)|((CAN_Msg->dataB[3]) << 24); - - pCan->TDB1 = data; - - /*Write transmission request*/ - pCan->CMR = 0x21; - - return SUCCESS; - } - - //check status of Transmit Buffer 2 - else if((pCan->SR) & (1 << 10)) - { - /* Transmit Channel 2 is available */ - /* Write frame informations and frame data into its CANxTFI2, - * CANxTID2, CANxTDA2, CANxTDB2 register */ - pCan->TFI2 &= ~0x000F0000; - - pCan->TFI2 |= (CAN_Msg->len) << 16; - - if(CAN_Msg->type == REMOTE_FRAME) - { - pCan->TFI2 |= (1 << 30); //set bit RTR - } - else - { - pCan->TFI2 &= ~(1 << 30); - } - - if(CAN_Msg->format == EXT_ID_FORMAT) - { - pCan->TFI2 |= (((uint32_t)1) << 31); //set bit FF - } - else - { - pCan->TFI2 &= ~(((uint32_t)1) << 31); - } - - /* Write CAN ID*/ - pCan->TID2 = CAN_Msg->id; - - /*Write first 4 data bytes*/ - data = (CAN_Msg->dataA[0]) | (((CAN_Msg->dataA[1])) << 8) | ((CAN_Msg->dataA[2]) << 16)|((CAN_Msg->dataA[3]) << 24); - - pCan->TDA2 = data; - - /*Write second 4 data bytes*/ - data = (CAN_Msg->dataB[0]) | (((CAN_Msg->dataB[1])) << 8) | ((CAN_Msg->dataB[2]) << 16) | ((CAN_Msg->dataB[3]) << 24); - - pCan->TDB2 = data; - - /*Write transmission request*/ - pCan->CMR = 0x41; - - return SUCCESS; - } - - //check status of Transmit Buffer 3 - else if (pCan->SR & (1<<18)) - { - /* Transmit Channel 3 is available */ - /* Write frame informations and frame data into its CANxTFI3, - * CANxTID3, CANxTDA3, CANxTDB3 register */ - pCan->TFI3 &= ~0x000F0000; - - pCan->TFI3 |= (CAN_Msg->len) << 16; - - if(CAN_Msg->type == REMOTE_FRAME) - { - pCan->TFI3 |= (1 << 30); //set bit RTR - } - else - { - pCan->TFI3 &= ~(1 << 30); - } - - if(CAN_Msg->format == EXT_ID_FORMAT) - { - pCan->TFI3 |= (((uint32_t)1) << 31); //set bit FF - } - else - { - pCan->TFI3 &= ~(((uint32_t)1) << 31); - } - - /* Write CAN ID*/ - pCan->TID3 = CAN_Msg->id; - - /*Write first 4 data bytes*/ - data = (CAN_Msg->dataA[0]) | (((CAN_Msg->dataA[1])) << 8) | ((CAN_Msg->dataA[2]) << 16) | ((CAN_Msg->dataA[3]) << 24); - - pCan->TDA3 = data; - - /*Write second 4 data bytes*/ - data = (CAN_Msg->dataB[0]) | (((CAN_Msg->dataB[1])) << 8) | ((CAN_Msg->dataB[2]) << 16) | ((CAN_Msg->dataB[3]) << 24); - - pCan->TDB3 = data; - - /*Write transmission request*/ - pCan->CMR = 0x81; - - return SUCCESS; - } - else - { - return ERROR; - } -} - -/********************************************************************//** - * @brief Receive message data - * @param[in] canId The Id of the expected CAN component - * - * @param[in] CAN_Msg point to the CAN_MSG_Type Struct, it will contain received - * message information such as: ID, DLC, RTR, ID Format - * @return Status: - * - SUCCESS: receive message successfully - * - ERROR: receive message unsuccessfully - *********************************************************************/ -Status CAN_ReceiveMsg (uint8_t canId, CAN_MSG_Type *CAN_Msg) -{ - LPC_CAN_TypeDef* pCan = CAN_GetPointer(canId); - - uint32_t data; - - //check status of Receive Buffer - if((pCan->SR &0x00000001)) - { - /* Receive message is available */ - /* Read frame informations */ - CAN_Msg->format = (uint8_t)(((pCan->RFS) & 0x80000000) >> 31); - - CAN_Msg->type = (uint8_t)(((pCan->RFS) & 0x40000000) >> 30); - - CAN_Msg->len = (uint8_t)(((pCan->RFS) & 0x000F0000) >> 16); - - /* Read CAN message identifier */ - CAN_Msg->id = pCan->RID; - - /* Read the data if received message was DATA FRAME */ - if (CAN_Msg->type == DATA_FRAME) - { - /* Read first 4 data bytes */ - data = pCan->RDA; - - *((uint8_t *) &CAN_Msg->dataA[0])= data & 0x000000FF; - - *((uint8_t *) &CAN_Msg->dataA[1])= (data & 0x0000FF00) >> 8;; - - *((uint8_t *) &CAN_Msg->dataA[2])= (data & 0x00FF0000) >> 16; - - *((uint8_t *) &CAN_Msg->dataA[3])= (data & 0xFF000000) >> 24; - - /* Read second 4 data bytes */ - data = pCan->RDB; - - *((uint8_t *) &CAN_Msg->dataB[0])= data & 0x000000FF; - - *((uint8_t *) &CAN_Msg->dataB[1])= (data & 0x0000FF00) >> 8; - - *((uint8_t *) &CAN_Msg->dataB[2])= (data & 0x00FF0000) >> 16; - - *((uint8_t *) &CAN_Msg->dataB[3])= (data & 0xFF000000) >> 24; - - /*release receive buffer*/ - pCan->CMR = 0x04; - } - else - { - /* Received Frame is a Remote Frame, not have data, we just receive - * message information only */ - pCan->CMR = 0x04; /*release receive buffer*/ - - return SUCCESS; - } - } - else - { - // no receive message available - return ERROR; - } - - return SUCCESS; -} - -/********************************************************************//** - * @brief Receive FullCAN Object - * @param[in] CANAFx: CAN Acceptance Filter register, should be: LPC_CANAF - * @param[in] CAN_Msg point to the CAN_MSG_Type Struct, it will contain received - * message information such as: ID, DLC, RTR, ID Format - * @return CAN_ERROR, could be: - * - CAN_FULL_OBJ_NOT_RCV: FullCAN Object is not be received - * - CAN_OK: Received FullCAN Object successful - * - *********************************************************************/ -CAN_ERROR FCAN_ReadObj (CAN_MSG_Type *CAN_Msg) -{ - uint32_t *pSrc, data; - uint32_t interrut_word, msg_idx, test_bit, head_idx, tail_idx; - - interrut_word = 0; - - if (LPC_CANAF->FCANIC0 != 0) - { - interrut_word = LPC_CANAF->FCANIC0; - - head_idx = 0; - - tail_idx = 31; - } - else if (LPC_CANAF->FCANIC1 != 0) - { - interrut_word = LPC_CANAF->FCANIC1; - - head_idx = 32; - - tail_idx = 63; - } - - if (interrut_word != 0) - { - /* Detect for interrupt pending */ - msg_idx = 0; - - for (msg_idx = head_idx; msg_idx <= tail_idx; msg_idx++) - { - test_bit = interrut_word & 0x1; - - interrut_word = interrut_word >> 1; - - if (test_bit) - { - pSrc = (uint32_t *) (LPC_CANAF->ENDofTable + LPC_CANAF_RAM_BASE + msg_idx * 12); - - /* Has been finished updating the content */ - if ((*pSrc & 0x03000000L) == 0x03000000L) - { - /*clear semaphore*/ - *pSrc &= 0xFCFFFFFF; - - /*Set to DatA*/ - pSrc++; - - /* Copy to dest buf */ - data = *pSrc; - - *((uint8_t *) &CAN_Msg->dataA[0])= data & 0x000000FF; - - *((uint8_t *) &CAN_Msg->dataA[1])= (data & 0x0000FF00) >> 8; - - *((uint8_t *) &CAN_Msg->dataA[2])= (data & 0x00FF0000) >> 16; - - *((uint8_t *) &CAN_Msg->dataA[3])= (data & 0xFF000000) >> 24; - - /*Set to DatB*/ - pSrc++; - - /* Copy to dest buf */ - data = *pSrc; - - *((uint8_t *) &CAN_Msg->dataB[0])= data & 0x000000FF; - - *((uint8_t *) &CAN_Msg->dataB[1])= (data & 0x0000FF00) >> 8; - - *((uint8_t *) &CAN_Msg->dataB[2])= (data & 0x00FF0000) >> 16; - - *((uint8_t *) &CAN_Msg->dataB[3])= (data & 0xFF000000) >> 24; - - /*Back to Dat1*/ - pSrc -= 2; - - CAN_Msg->id = *pSrc & 0x7FF; - - CAN_Msg->len = (uint8_t) (*pSrc >> 16) & 0x0F; - - CAN_Msg->format = 0; //FullCAN Object ID always is 11-bit value - - CAN_Msg->type = (uint8_t)(*pSrc >> 30) &0x01; - - /*Re-read semaphore*/ - if ((*pSrc & 0x03000000L) == 0) - { - return CAN_OK; - } - } - } - } - } - - return CAN_FULL_OBJ_NOT_RCV; -} - -/********************************************************************//** - * @brief Get CAN Control Status - * @param[in] canId The Id of the expected CAN component - * - * @param[in] arg: type of CAN status to get from CAN status register - * Should be: - * - CANCTRL_GLOBAL_STS: CAN Global Status - * - CANCTRL_INT_CAP: CAN Interrupt and Capture - * - CANCTRL_ERR_WRN: CAN Error Warning Limit - * - CANCTRL_STS: CAN Control Status - * @return Current Control Status that you want to get value - *********************************************************************/ -uint32_t CAN_GetCTRLStatus (uint8_t canId, CAN_CTRL_STS_Type arg) -{ - LPC_CAN_TypeDef* pCan = CAN_GetPointer(canId); - - switch (arg) - { - case CANCTRL_GLOBAL_STS: - return pCan->GSR; - - case CANCTRL_INT_CAP: - return pCan->ICR; - - case CANCTRL_ERR_WRN: - return pCan->EWL; - - default: // CANCTRL_STS - return pCan->SR; - } -} -/********************************************************************//** - * @brief Get CAN Central Status - * @param[in] CANCRx point to LPC_CANCR_TypeDef, should be: LPC_CANCR - * @param[in] arg: type of CAN status to get from CAN Central status register - * Should be: - * - CANCR_TX_STS: Central CAN Tx Status - * - CANCR_RX_STS: Central CAN Rx Status - * - CANCR_MS: Central CAN Miscellaneous Status - * @return Current Central Status that you want to get value - *********************************************************************/ -uint32_t CAN_GetCRStatus (CAN_CR_STS_Type arg) -{ - switch (arg) - { - case CANCR_TX_STS: - return LPC_CANCR->TxSR; - - case CANCR_RX_STS: - return LPC_CANCR->RxSR; - - default: // CANCR_MS - return LPC_CANCR->MSR; - } -} -/********************************************************************//** - * @brief Enable/Disable CAN Interrupt - * @param[in] canId The Id of the expected CAN component - * - * @param[in] arg: type of CAN interrupt that you want to enable/disable - * Should be: - * - CANINT_RIE: CAN Receiver Interrupt Enable - * - CANINT_TIE1: CAN Transmit Interrupt Enable - * - CANINT_EIE: CAN Error Warning Interrupt Enable - * - CANINT_DOIE: CAN Data Overrun Interrupt Enable - * - CANINT_WUIE: CAN Wake-Up Interrupt Enable - * - CANINT_EPIE: CAN Error Passive Interrupt Enable - * - CANINT_ALIE: CAN Arbitration Lost Interrupt Enable - * - CANINT_BEIE: CAN Bus Error Interrupt Enable - * - CANINT_IDIE: CAN ID Ready Interrupt Enable - * - CANINT_TIE2: CAN Transmit Interrupt Enable for Buffer2 - * - CANINT_TIE3: CAN Transmit Interrupt Enable for Buffer3 - * - CANINT_FCE: FullCAN Interrupt Enable - * @param[in] NewState: New state of this function, should be: - * - ENABLE - * - DISABLE - * @return none - *********************************************************************/ -void CAN_IRQCmd (uint8_t canId, CAN_INT_EN_Type arg, FunctionalState NewState) -{ - LPC_CAN_TypeDef* pCan = CAN_GetPointer(canId); - - if(NewState == ENABLE) - { - if(arg == CANINT_FCE) - { - LPC_CANAF->AFMR = 0x01; - - LPC_CANAF->FCANIE = 0x01; - - LPC_CANAF->AFMR = 0x04; - } - else - pCan->IER |= (1 << arg); - } - else - { - if(arg == CANINT_FCE) - { - LPC_CANAF->AFMR = 0x01; - - LPC_CANAF->FCANIE = 0x01; - - LPC_CANAF->AFMR = 0x00; - } - else - pCan->IER &= ~(1 << arg); - } -} - -/********************************************************************//** - * @brief Setting Acceptance Filter mode - * @param[in] CANAFx point to LPC_CANAF_TypeDef object, should be: LPC_CANAF - * @param[in] AFMode: type of AF mode that you want to set, should be: - * - CAN_NORMAL: Normal mode - * - CAN_ACC_OFF: Acceptance Filter Off Mode - * - CAN_ACC_BP: Acceptance Fileter Bypass Mode - * - CAN_EFCAN: FullCAN Mode Enhancement - * @return none - *********************************************************************/ -void CAN_SetAFMode (CAN_AFMODE_Type AFMode) -{ - switch(AFMode) - { - case CAN_NORMAL: - LPC_CANAF->AFMR = 0x00; - break; - - case CAN_ACC_OFF: - LPC_CANAF->AFMR = 0x01; - break; - - case CAN_ACC_BP: - LPC_CANAF->AFMR = 0x02; - break; - - case CAN_EFCAN: - LPC_CANAF->AFMR = 0x04; - break; - } -} - -/********************************************************************//** - * @brief Enable/Disable CAN Mode - * @param[in] canId The Id of the expected CAN component - * - * @param[in] mode: type of CAN mode that you want to enable/disable, should be: - * - CAN_OPERATING_MODE: Normal Operating Mode - * - CAN_RESET_MODE: Reset Mode - * - CAN_LISTENONLY_MODE: Listen Only Mode - * - CAN_SELFTEST_MODE: Self Test Mode - * - CAN_TXPRIORITY_MODE: Transmit Priority Mode - * - CAN_SLEEP_MODE: Sleep Mode - * - CAN_RXPOLARITY_MODE: Receive Polarity Mode - * - CAN_TEST_MODE: Test Mode - * @param[in] NewState: New State of this function, should be: - * - ENABLE - * - DISABLE - * @return none - *********************************************************************/ -void CAN_ModeConfig(uint8_t canId, CAN_MODE_Type mode, FunctionalState NewState) -{ - LPC_CAN_TypeDef* pCan = CAN_GetPointer(canId); - - switch(mode) - { - case CAN_OPERATING_MODE: - pCan->MOD = 0x00; - break; - - case CAN_RESET_MODE: - if(NewState == ENABLE) - pCan->MOD |= CAN_MOD_RM; - else - pCan->MOD &= ~CAN_MOD_RM; - - break; - - case CAN_LISTENONLY_MODE: - pCan->MOD |=CAN_MOD_RM;//Enter Reset mode - - if(NewState == ENABLE) - pCan->MOD |= CAN_MOD_LOM; - else - pCan->MOD &= ~ CAN_MOD_LOM; - - pCan->MOD &= ~ CAN_MOD_RM;//Release Reset mode - - break; - - case CAN_SELFTEST_MODE: - pCan->MOD |= CAN_MOD_RM;//Enter Reset mode - - if(NewState == ENABLE) - pCan->MOD |= CAN_MOD_STM; - else - pCan->MOD &= ~ CAN_MOD_STM; - - pCan->MOD &= ~ CAN_MOD_RM;//Release Reset mode - - break; - - case CAN_TXPRIORITY_MODE: - if(NewState == ENABLE) - pCan->MOD |= CAN_MOD_TPM; - else - pCan->MOD &= ~ CAN_MOD_TPM; - - break; - - case CAN_SLEEP_MODE: - if(NewState == ENABLE) - pCan->MOD |= CAN_MOD_SM; - else - pCan->MOD &= ~ CAN_MOD_SM; - - break; - - case CAN_RXPOLARITY_MODE: - if(NewState == ENABLE) - pCan->MOD |= CAN_MOD_RPM; - else - pCan->MOD &= ~ CAN_MOD_RPM; - - break; - - case CAN_TEST_MODE: - if(NewState == ENABLE) - pCan->MOD |= CAN_MOD_TM; - else - pCan->MOD &= ~ CAN_MOD_TM; - - break; - } -} -/*********************************************************************//** - * @brief Set CAN command request - * @param[in] canId The Id of the expected CAN component - * - * @param[in] CMRType command request type, should be: - * - CAN_CMR_TR: Transmission request - * - CAN_CMR_AT: Abort Transmission request - * - CAN_CMR_RRB: Release Receive Buffer request - * - CAN_CMR_CDO: Clear Data Overrun request - * - CAN_CMR_SRR: Self Reception request - * - CAN_CMR_STB1: Select Tx Buffer 1 request - * - CAN_CMR_STB2: Select Tx Buffer 2 request - * - CAN_CMR_STB3: Select Tx Buffer 3 request - * @return CANICR (CAN interrupt and Capture register) value - **********************************************************************/ -void CAN_SetCommand(uint8_t canId, uint32_t CMRType) -{ - LPC_CAN_TypeDef* pCan = CAN_GetPointer(canId); - - pCan->CMR |= CMRType; -} - -/*********************************************************************//** - * @brief Get CAN interrupt status - * @param[in] canId The Id of the expected CAN component - * - * @return CANICR (CAN interrupt and Capture register) value - **********************************************************************/ -uint32_t CAN_IntGetStatus(uint8_t canId) -{ - LPC_CAN_TypeDef* pCan = CAN_GetPointer(canId); - - return pCan->ICR; -} - -/*********************************************************************//** - * @brief Check if FullCAN interrupt enable or not - * @param[in] CANAFx point to LPC_CANAF_TypeDef object, should be: LPC_CANAF - * @return IntStatus, could be: - * - SET: if FullCAN interrupt is enable - * - RESET: if FullCAN interrupt is disable - **********************************************************************/ -IntStatus CAN_FullCANIntGetStatus (void) -{ - if (LPC_CANAF->FCANIE) - return SET; - - return RESET; -} - -/*********************************************************************//** - * @brief Get value of FullCAN interrupt and capture register - * @param[in] CANAFx point to LPC_CANAF_TypeDef object, should be: LPC_CANAF - * @param[in] type: FullCAN IC type, should be: - * - FULLCAN_IC0: FullCAN Interrupt Capture 0 - * - FULLCAN_IC1: FullCAN Interrupt Capture 1 - * @return FCANIC0 or FCANIC1 (FullCAN interrupt and Capture register) value - **********************************************************************/ -uint32_t CAN_FullCANPendGetStatus(FullCAN_IC_Type type) -{ - if (type == FULLCAN_IC0) - return LPC_CANAF->FCANIC0; - - return LPC_CANAF->FCANIC1; -} -/* End of Public Variables ---------------------------------------------------------- */ -/** - * @} - */ -#endif /*_CAN*/ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_clkpwr.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_clkpwr.c deleted file mode 100644 index fc416876374..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_clkpwr.c +++ /dev/null @@ -1,326 +0,0 @@ -/********************************************************************** -* $Id$ lpc_clkpwr.c 2011-06-02 -*//** -* @file lpc_clkpwr.c -* @brief Contains all functions support for Clock and Power Control -* firmware library on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup CLKPWR - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _CLKPWR - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_clkpwr.h" - -uint32_t USBFrequency = 0; - - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup CLKPWR_Public_Functions - * @{ - */ - -/*********************************************************************//** - * @brief Set value of each Peripheral Clock Selection - * @param[in] ClkType clock type that will be divided, should be: - * - CLKPWR_CLKTYPE_CPU : CPU clock - * - CLKPWR_CLKTYPE_PER : Peripheral clock - * - CLKPWR_CLKTYPE_EMC : EMC clock - * - CLKPWR_CLKTYPE_USB : USB clock - * @param[in] DivVal Value of divider. This value should be set as follows: - * - CPU clock: DivVal must be in range: 0..31 - * - Peripheral clock: DivVal must be in range: 0..31 - * - EMC clock: DivVal must be: - * + 0: The EMC uses the same clock as the CPU - * + 1: The EMC uses a clock at half the rate of the CPU - * - USB clock: DivVal must be: - * + 0: the divider is turned off, no clock will - * be provided to the USB subsystem - * + 4: PLL0 output is divided by 4. PLL0 output must be 192MHz - * + 6: PLL0 output is divided by 6. PLL0 output must be 288MHz - * @return none - * Note: Pls assign right DivVal, this function will not check if it is illegal. - **********************************************************************/ -void CLKPWR_SetCLKDiv (uint8_t ClkType, uint8_t DivVal) -{ - uint32_t tmp; - switch(ClkType) - { - case CLKPWR_CLKTYPE_CPU: - tmp = LPC_SC->CCLKSEL & ~(0x1F); - tmp |= DivVal & 0x1F; - LPC_SC->CCLKSEL = tmp; - SystemCoreClockUpdate(); //Update clock - break; - case CLKPWR_CLKTYPE_PER: - tmp = LPC_SC->PCLKSEL & ~(0x1F); - tmp |= DivVal & 0x1F; - LPC_SC->PCLKSEL = tmp; - SystemCoreClockUpdate(); //Update clock - break; - case CLKPWR_CLKTYPE_EMC: - tmp = LPC_SC->EMCCLKSEL & ~(0x01); - tmp |= DivVal & 0x01; - LPC_SC->EMCCLKSEL = tmp; - SystemCoreClockUpdate(); //Update clock - break; - case CLKPWR_CLKTYPE_USB: - tmp = LPC_SC->USBCLKSEL & ~(0x1F); - tmp |= DivVal & 0x1F; - LPC_SC->USBCLKSEL |= DivVal & 0x1F; - SystemCoreClockUpdate(); //Update clock - break; - default: - while(1);//Error Loop; - } -} - -/*********************************************************************//** - * @brief Get current clock value - * @param[in] ClkType clock type that will be divided, should be: - * - CLKPWR_CLKTYPE_CPU : CPU clock - * - CLKPWR_CLKTYPE_PER : Peripheral clock - * - CLKPWR_CLKTYPE_EMC : EMC clock - * - CLKPWR_CLKTYPE_USB : USB clock - **********************************************************************/ -uint32_t CLKPWR_GetCLK (uint8_t ClkType) -{ - switch(ClkType) - { - case CLKPWR_CLKTYPE_CPU: - return SystemCoreClock; - - case CLKPWR_CLKTYPE_PER: - return PeripheralClock; - - case CLKPWR_CLKTYPE_EMC: - return EMCClock; - - case CLKPWR_CLKTYPE_USB: - return USBClock; - - default: - while(1);//error loop - } -} - -/*********************************************************************//** - * @brief Configure power supply for each peripheral according to NewState - * @param[in] PPType Type of peripheral used to enable power, - * should be one of the following: - * - CLKPWR_PCONP_PCLCD : LCD - * - CLKPWR_PCONP_PCTIM0 : Timer 0 - * - CLKPWR_PCONP_PCTIM1 : Timer 1 - * - CLKPWR_PCONP_PCUART0 : UART 0 - * - CLKPWR_PCONP_PCUART1 : UART 1 - * - CLKPWR_PCONP_PCPWM0 : PWM 0 - * - CLKPWR_PCONP_PCPWM1 : PWM 1 - * - CLKPWR_PCONP_PCI2C0 : I2C 0 - * - CLKPWR_PCONP_PCUART4 : UART4 - * - CLKPWR_PCONP_PCLCD : LCD - * - CLKPWR_PCONP_PCTIM0 : Timer 0 - * - CLKPWR_PCONP_PCRTC : RTC - * - CLKPWR_PCONP_PCSSP1 : SSP 1 - * - CLKPWR_PCONP_PCEMC : EMC - * - CLKPWR_PCONP_PCADC : ADC - * - CLKPWR_PCONP_PCAN1 : CAN 1 - * - CLKPWR_PCONP_PCAN2 : CAN 2 - * - CLKPWR_PCONP_PCGPIO : GPIO - * - CLKPWR_PCONP_PCMC : MCPWM - * - CLKPWR_PCONP_PCQEI : QEI - * - CLKPWR_PCONP_PCI2C1 : I2C 1 - * - CLKPWR_PCONP_PCSSP2 : SSP 2 - * - CLKPWR_PCONP_PCSSP0 : SSP 0 - * - CLKPWR_PCONP_PCTIM2 : Timer 2 - * - CLKPWR_PCONP_PCTIM3 : Timer 3 - * - CLKPWR_PCONP_PCUART2 : UART 2 - * - CLKPWR_PCONP_PCUART3 : UART 3 - * - CLKPWR_PCONP_PCI2C2 : I2C 2 - * - CLKPWR_PCONP_PCI2S : I2S - * - CLKPWR_PCONP_PCSDC : SDC - * - CLKPWR_PCONP_PCGPDMA : GPDMA - * - CLKPWR_PCONP_PCENET : Ethernet - * - CLKPWR_PCONP_PCUSB : USB - * - * @param[in] NewState New state of Peripheral Power, should be: - * - ENABLE : Enable power for this peripheral - * - DISABLE : Disable power for this peripheral - * - * @return none - **********************************************************************/ -void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - LPC_SC->PCONP |= PPType; - } - else if (NewState == DISABLE) - { - LPC_SC->PCONP &= ~PPType; - } -} - -#if 0 -// nxp21346 -/*********************************************************************//** - * @brief Configure hardware reset for each peripheral according to NewState - * @param[in] PPType Type of peripheral used to enable power, - * should be one of the following: - * - CLKPWR_RSTCON0_LCD : LCD - * - CLKPWR_RSTCON0_TIM0 : Timer 0 - - CLKPWR_RSTCON0_TIM1 : Timer 1 - - CLKPWR_RSTCON0_UART0 : UART 0 - - CLKPWR_RSTCON0_UART1 : UART 1 - - CLKPWR_RSTCON0_PWM0 : PWM 0 - - CLKPWR_RSTCON0_PWM1 : PWM 1 - - CLKPWR_RSTCON0_I2C0 : I2C 0 - - CLKPWR_RSTCON0_UART4 : UART 4 - - CLKPWR_RSTCON0_RTC : RTC - - CLKPWR_RSTCON0_SSP1 : SSP 1 - - CLKPWR_RSTCON0_EMC : EMC - - CLKPWR_RSTCON0_ADC : ADC - - CLKPWR_RSTCON0_CAN1 : CAN 1 - - CLKPWR_RSTCON0_CAN2 : CAN 2 - - CLKPWR_RSTCON0_GPIO : GPIO - - CLKPWR_RSTCON0_MCPWM : MCPWM - - CLKPWR_RSTCON0_QEI : QEI - - CLKPWR_RSTCON0_I2C1 : I2C 1 - - CLKPWR_RSTCON0_SSP2 : SSP 2 - - CLKPWR_RSTCON0_SSP0 : SSP 0 - - CLKPWR_RSTCON0_TIM2 : Timer 2 - - CLKPWR_RSTCON0_TIM3 : Timer 3 - - CLKPWR_RSTCON0_UART2 : UART 2 - - CLKPWR_RSTCON0_UART3 : UART 3 - - CLKPWR_RSTCON0_I2C2 : I2C 2 - - CLKPWR_RSTCON0_I2S : I2S - - CLKPWR_RSTCON0_SDC : SDC - - CLKPWR_RSTCON0_GPDMA : GPDMA - - CLKPWR_RSTCON0_ENET : Ethernet - - CLKPWR_RSTCON0_USB : USB - * - * @param[in] NewState New state of Peripheral Power, should be: - * - ENABLE : Enable power for this peripheral - * - DISABLE : Disable power for this peripheral - * - * @return none - **********************************************************************/ -void CLKPWR_ConfigReset(uint8_t PType, FunctionalState NewState) -{ - if(PType < 32) - { - if(NewState == ENABLE) - LPC_SC->RSTCON0 |=(1<RSTCON0 &=~(1<RSTCON1 |= (1<<(PType - 31)); - else - LPC_SC->RSTCON1 &= ~(1<<(PType - 31)); - } -} -// nxp21346 -#endif - -/*********************************************************************//** - * @brief Enter Sleep mode with co-operated instruction by the Cortex-M3. - * @param[in] None - * @return None - **********************************************************************/ -void CLKPWR_Sleep(void) -{ - LPC_SC->PCON = 0x00; - /* Sleep Mode*/ - __WFI(); -} - - -/*********************************************************************//** - * @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3. - * @param[in] None - * @return None - **********************************************************************/ -void CLKPWR_DeepSleep(void) -{ - /* Deep-Sleep Mode, set SLEEPDEEP bit */ - SCB->SCR = 0x4; - LPC_SC->PCON = 0x00; - /* Deep Sleep Mode*/ - __WFI(); -} - - -/*********************************************************************//** - * @brief Enter Power Down mode with co-operated instruction by the Cortex-M3. - * @param[in] None - * @return None - **********************************************************************/ -void CLKPWR_PowerDown(void) -{ - /* Deep-Sleep Mode, set SLEEPDEEP bit */ - SCB->SCR = 0x4; - LPC_SC->PCON = 0x01; - /* Power Down Mode*/ - __WFI(); -} - - -/*********************************************************************//** - * @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3. - * @param[in] None - * @return None - **********************************************************************/ -void CLKPWR_DeepPowerDown(void) -{ - /* Deep-Sleep Mode, set SLEEPDEEP bit */ - SCB->SCR = 0x4; - LPC_SC->PCON = 0x03; - /* Deep Power Down Mode*/ - __WFI(); -} - -/** - * @} - */ - -#endif /*_CLKPWR*/ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_crc.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_crc.c deleted file mode 100644 index 8d74c052ea8..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_crc.c +++ /dev/null @@ -1,171 +0,0 @@ -/********************************************************************** -* $Id$ lpc_crc.c 2011-06-02 -*//** -* @file lpc_crc.c -* @brief Contains all functions support for CRC firmware library on -* LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _CRC - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_crc.h" -#include "lpc_clkpwr.h" - -/* Private Variables ----------------------------------------------------------- */ -volatile CRC_Type crc_cur_type; - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup CRC_Public_Functions - * @{ - */ -/*********************************************************************//** - * @brief Initialize CRC operation - * @param[in] CRCType CRC standard type, should be: - * - CRC_POLY_CRCCCITT: CRC-CCITT polynomial - * - CRC_POLY_CRC16: CRC-16 polynomial - * - CRC_POLY_CRC32: CRC-32 polynomial - * @return None - **********************************************************************/ -void CRC_Init(CRC_Type CRCType) -{ - if(CRCType == CRC_POLY_CRCCCITT) - { - LPC_CRC->MODE = 0x00; - LPC_CRC->SEED = 0xFFFF; - crc_cur_type = CRC_POLY_CRCCCITT; - } - else if(CRCType == CRC_POLY_CRC16) - { - LPC_CRC->MODE = 0x15; - LPC_CRC->SEED = 0x0000; - crc_cur_type = CRC_POLY_CRC16; - - } - else if(CRCType == CRC_POLY_CRC32) - { - LPC_CRC->MODE = 0x36; - LPC_CRC->SEED = 0xFFFFFFFF; - crc_cur_type = CRC_POLY_CRC32; - } - else - { - //Invalid input parameter - while(1);//error loop - } -} -/*********************************************************************//** - * @brief CRC reset - * @param[in] None - * @return None - **********************************************************************/ -void CRC_Reset(void) -{ - if(crc_cur_type == CRC_POLY_CRCCCITT) - LPC_CRC->SEED = 0xFFFF; - else if (crc_cur_type == CRC_POLY_CRC16) - LPC_CRC->SEED = 0x0000; - else if (crc_cur_type == CRC_POLY_CRC32) - LPC_CRC->SEED = 0xFFFFFFFF; -} - -/*********************************************************************//** - * @brief CRC data checksum calculation - * @param[in] data input data - * @return data checksum result - **********************************************************************/ -uint32_t CRC_CalcDataChecksum(uint32_t data, CRC_WR_SIZE SizeType) -{ - if(SizeType == CRC_WR_8BIT) - LPC_CRC->WR_DATA_BYTE.DATA = (uint8_t)data; - else if(SizeType == CRC_WR_16BIT) - LPC_CRC->WR_DATA_WORD.DATA = (uint16_t)data; - else - LPC_CRC->WR_DATA_DWORD.DATA = data; - return(LPC_CRC->SUM); -} - -/*********************************************************************//** - * @brief CRC block data checksum calculation - * @param[in] blockdata pointer to block input data - * @param[in] blocksize size of block data - * @param[in] SizeType size of data width per write, should be: - - CRC_WR_8BIT : 8-bit write - - CRC_WR_16BIT: 16-bit write - - CRC_WR_32BIT: 32-bit write - * @return block data checksum result - **********************************************************************/ -uint32_t CRC_CalcBlockChecksum(void *block_data, uint32_t block_size, CRC_WR_SIZE data_size) -{ - uint8_t *data = (uint8_t*) block_data; - - while(block_size !=0) { - - switch(data_size) { - - case CRC_WR_8BIT: - { - uint8_t *tmp = data; - LPC_CRC->WR_DATA_BYTE.DATA = *tmp; - data++; - } - break; - case CRC_WR_16BIT: - { - uint16_t *tmp = (uint16_t*)data; - LPC_CRC->WR_DATA_WORD.DATA = *tmp; - data +=2; - } - break; - default: - { - uint32_t *tmp = (uint32_t*)data; - LPC_CRC->WR_DATA_DWORD.DATA = *tmp; - data += 4; - } - break; - } - block_size--; - } - return(LPC_CRC->SUM); -} - -/** - * @} - */ -#endif /*_CRC*/ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_dac.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_dac.c deleted file mode 100644 index 29e126d085c..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_dac.c +++ /dev/null @@ -1,196 +0,0 @@ -/********************************************************************** -* $Id$ lpc_dac.c 2011-06-02 -*//** -* @file lpc_dac.c -* @brief Contains all functions support for DAC firmware library on -* LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup DAC - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _DAC - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_dac.h" -#include "lpc_clkpwr.h" -#include "lpc_pinsel.h" - -/* Private Functions ---------------------------------------------------------- */ - -/*********************************************************************//** - * @brief Get pointer to DAC peripheral - * @param[in] compId Component ID, normally is zero (0). - * @param[in] pinnum Pin number value, should be in range from 0..31 - * @return Pointer to DAC peripheral component - **********************************************************************/ -static LPC_DAC_TypeDef * DAC_GetPointer(uint8_t compId) -{ - LPC_DAC_TypeDef *pComponent = LPC_DAC; - - return pComponent; -} - - - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup DAC_Public_Functions - * @{ - */ - -/*********************************************************************//** - * @brief Initial ADC configuration - * - Maximum current is 700 uA - * - Value to AOUT is 0 - * @param[in] DAC_Id the ID of the DAC component that is using, should be: zero (0) - * @return None - ***********************************************************************/ -void DAC_Init(uint8_t DAC_Id) -{ - /* - * Init DAC pin connect - * AOUT on P0.26 - */ - PINSEL_ConfigPin(0, 26, 2); - - PINSEL_SetAnalogPinMode(0,26,ENABLE); - - //Enable DAC for the pin - PINSEL_DacEnable(0, 26, ENABLE); - - //Set maximum current output as default - DAC_SetBias(DAC_Id, DAC_MAX_CURRENT_700uA); -} - -/*********************************************************************//** - * @brief Update value to DAC - * @param[in] DAC_Id the ID of the DAC component that is using, should be: zero (0) - * @param[in] dac_value : value 10 bit to be converted to output - * @return None - ***********************************************************************/ -void DAC_UpdateValue (uint8_t DAC_Id,uint32_t dac_value) -{ - uint32_t tmp; - - LPC_DAC_TypeDef* pDac = DAC_GetPointer(DAC_Id); - - tmp = pDac->CR & DAC_BIAS_EN; - - tmp |= DAC_VALUE(dac_value); - - // Update value - pDac->CR = tmp; -} - -/*********************************************************************//** - * @brief Set Maximum current for DAC - * @param[in] DAC_Id the ID of the DAC component that is using, should be: zero (0) - * @param[in] bias : 0 is 700 uA - * 1 350 uA - * @return None - ***********************************************************************/ -void DAC_SetBias (uint8_t DAC_Id, uint32_t bias) -{ - LPC_DAC_TypeDef* pDac = DAC_GetPointer(DAC_Id); - - pDac->CR &=~DAC_BIAS_EN; - - if (bias == DAC_MAX_CURRENT_350uA) - { - pDac->CR |= DAC_BIAS_EN; - } -} - -/*********************************************************************//** - * @brief To enable the DMA operation and control DMA timer - * @param[in] DAC_Id the ID of the DAC component that is using, should be: zero (0) - * @param[in] DAC_ConverterConfigStruct pointer to DAC_CONVERTER_CFG_Type - * - DBLBUF_ENA : enable/disable DACR double buffering feature - * - CNT_ENA : enable/disable timer out counter - * - DMA_ENA : enable/disable DMA access - * @return None - ***********************************************************************/ -void DAC_ConfigDAConverterControl (uint8_t DAC_Id, DAC_CONVERTER_CFG_Type *DAC_ConverterConfigStruct) -{ - LPC_DAC_TypeDef* pDac = DAC_GetPointer(DAC_Id); - - pDac->CTRL &= ~DAC_DACCTRL_MASK; - - if (DAC_ConverterConfigStruct->DBLBUF_ENA) - pDac->CTRL |= DAC_DBLBUF_ENA; - - if (DAC_ConverterConfigStruct->CNT_ENA) - pDac->CTRL |= DAC_CNT_ENA; - - if (DAC_ConverterConfigStruct->DMA_ENA) - pDac->CTRL |= DAC_DMA_ENA; -} - -/*********************************************************************//** - * @brief Set reload value for interrupt/DMA counter - * @param[in] DAC_Id the ID of the DAC component that is using, should be: zero (0) - * @param[in] time_out time out to reload for interrupt/DMA counter - * @return None - ***********************************************************************/ -void DAC_SetDMATimeOut(uint8_t DAC_Id, uint32_t time_out) -{ - LPC_DAC_TypeDef* pDac = DAC_GetPointer(DAC_Id); - - pDac->CNTVAL = DAC_CCNT_VALUE(time_out); -} - - -/*********************************************************************//** - * @brief Check the interrupt/DMA counter is occured or not because of the timer counter - * @param[in] DAC_Id the ID of the DAC component that is using, should be: zero (0) - * @return None - ***********************************************************************/ -uint8_t DAC_IsIntRequested(uint8_t DAC_Id) -{ - LPC_DAC_TypeDef* pDac = DAC_GetPointer(DAC_Id); - - //Return the INT_DMA_REQ bit of D/A control register - return (pDac->CTRL & 0x01); -} - - -/** - * @} - */ -#endif /*_DAC*/ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_eeprom.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_eeprom.c deleted file mode 100644 index 039a1d4ed3c..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_eeprom.c +++ /dev/null @@ -1,267 +0,0 @@ -/********************************************************************** -* $Id$ lpc_eeprom.c 2011-06-02 -*//** -* @file lpc_eeprom.c -* @brief Contains all functions support for EEPROM firmware library on -* LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup EEPROM - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _EEPROM - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_eeprom.h" -#include "lpc_clkpwr.h" - -/* Public Functions ----------------------------------------------------------- */ - -/*********************************************************************//** - * @brief Initial EEPROM - * @param[in] None - * @return None - **********************************************************************/ -void EEPROM_Init(void) -{ - uint32_t val, cclk; - LPC_EEPROM->PWRDWN = 0x0; - /* EEPROM is automate turn on after reset */ - /* Setting clock: - * EEPROM required a 375kHz. This clock is generated by dividing the - * system bus clock. - */ - cclk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_CPU); - val = (cclk/375000)-1; - LPC_EEPROM->CLKDIV = val; - - /* Setting wait state */ - val = ((((cclk / 1000000) * 15) / 1000) + 1); - val |= (((((cclk / 1000000) * 55) / 1000) + 1) << 8); - val |= (((((cclk / 1000000) * 35) / 1000) + 1) << 16); - LPC_EEPROM->WSTATE = val; -} - -/*********************************************************************//** - * @brief Write data to EEPROM at specific address - * @param[in] page_offset offset of data in page register(0 - 63) - * page_address page address (0-62) - * mode Write mode, should be: - * - MODE_8_BIT : write 8 bit mode - * - MODE_16_BIT : write 16 bit mode - * - MODE_32_BIT : write 32 bit mode - * data buffer that contain data that will be written to buffer - * count number written data - * @return None - * @note This function actually write data into EEPROM memory and automatically - * write into next page if current page is overflowed - **********************************************************************/ -void EEPROM_Write(uint16_t page_offset, uint16_t page_address, void* data, EEPROM_Mode_Type mode, uint32_t count) -{ - uint32_t i; - uint8_t *tmp8 = (uint8_t *)data; - uint16_t *tmp16 = (uint16_t *)data; - uint32_t *tmp32 = (uint32_t *)data; - - LPC_EEPROM->INT_CLR_STATUS = ((1 << EEPROM_ENDOF_RW)|(1 << EEPROM_ENDOF_PROG)); - //check page_offset - if(mode == MODE_16_BIT){ - if((page_offset & 0x01)!=0) while(1); - } - else if(mode == MODE_32_BIT){ - if((page_offset & 0x03)!=0) while(1); - } - LPC_EEPROM->ADDR = EEPROM_PAGE_OFFSET(page_offset); - for(i=0;iCMD = EEPROM_CMD_8_BIT_WRITE; - LPC_EEPROM -> WDATA = *tmp8; - tmp8++; - page_offset +=1; - } - else if(mode == MODE_16_BIT){ - LPC_EEPROM->CMD = EEPROM_CMD_16_BIT_WRITE; - LPC_EEPROM -> WDATA = *tmp16; - tmp16++; - page_offset +=2; - } - else{ - LPC_EEPROM->CMD = EEPROM_CMD_32_BIT_WRITE; - LPC_EEPROM -> WDATA = *tmp32; - tmp32++; - page_offset +=4; - } - while(!((LPC_EEPROM->INT_STATUS >> EEPROM_ENDOF_RW)&0x01)); - LPC_EEPROM->INT_CLR_STATUS = (1 << EEPROM_ENDOF_RW); - if((page_offset >= EEPROM_PAGE_SIZE)|(i==count-1)){ - //update to EEPROM memory - LPC_EEPROM->INT_CLR_STATUS = (0x1 << EEPROM_ENDOF_PROG); - LPC_EEPROM->ADDR = EEPROM_PAGE_ADRESS(page_address); - LPC_EEPROM->CMD = EEPROM_CMD_ERASE_PRG_PAGE; - while(!((LPC_EEPROM->INT_STATUS >> EEPROM_ENDOF_PROG)&0x01)); - LPC_EEPROM->INT_CLR_STATUS = (1 << EEPROM_ENDOF_PROG); - } - if(page_offset >= EEPROM_PAGE_SIZE) - { - page_offset = 0; - page_address +=1; - LPC_EEPROM->ADDR =0; - if(page_address > EEPROM_PAGE_NUM - 1) page_address = 0; - } - } -} - -/*********************************************************************//** - * @brief Read data to EEPROM at specific address - * @param[in] - * data buffer that contain data that will be written to buffer - * mode Read mode, should be: - * - MODE_8_BIT : read 8 bit mode - * - MODE_16_BIT : read 16 bit mode - * - MODE_32_BIT : read 32 bit mode - * count number read data (bytes) - * @return data buffer that contain data that will be read to buffer - **********************************************************************/ -void EEPROM_Read(uint16_t page_offset, uint16_t page_address, void* data, EEPROM_Mode_Type mode, uint32_t count) -{ - uint32_t i; - uint8_t *tmp8 = (uint8_t *)data; - uint16_t *tmp16 = (uint16_t *)data; - uint32_t *tmp32 = (uint32_t *)data; - - LPC_EEPROM->INT_CLR_STATUS = ((1 << EEPROM_ENDOF_RW)|(1 << EEPROM_ENDOF_PROG)); - LPC_EEPROM->ADDR = EEPROM_PAGE_ADRESS(page_address)|EEPROM_PAGE_OFFSET(page_offset); - if(mode == MODE_8_BIT) - LPC_EEPROM->CMD = EEPROM_CMD_8_BIT_READ|EEPROM_CMD_RDPREFETCH; - else if(mode == MODE_16_BIT){ - LPC_EEPROM->CMD = EEPROM_CMD_16_BIT_READ|EEPROM_CMD_RDPREFETCH; - //check page_offset - if((page_offset &0x01)!=0) - return; - } - else{ - LPC_EEPROM->CMD = EEPROM_CMD_32_BIT_READ|EEPROM_CMD_RDPREFETCH; - //page_offset must be a multiple of 0x04 - if((page_offset & 0x03)!=0) - return; - } - - //read and store data in buffer - for(i=0;i RDATA); - tmp8++; - page_offset +=1; - } - else if (mode == MODE_16_BIT) - { - *tmp16 = (uint16_t)(LPC_EEPROM -> RDATA); - tmp16++; - page_offset +=2; - } - else{ - *tmp32 = (uint32_t)(LPC_EEPROM ->RDATA); - tmp32++; - page_offset +=4; - } - while(!((LPC_EEPROM->INT_STATUS >> EEPROM_ENDOF_RW)&0x01)); - LPC_EEPROM->INT_CLR_STATUS = (1 << EEPROM_ENDOF_RW); - if((page_offset >= EEPROM_PAGE_SIZE) && (i < count - 1)) { - page_offset = 0; - page_address++; - LPC_EEPROM->ADDR = EEPROM_PAGE_ADRESS(page_address)|EEPROM_PAGE_OFFSET(page_offset); - if(mode == MODE_8_BIT) - LPC_EEPROM->CMD = EEPROM_CMD_8_BIT_READ|EEPROM_CMD_RDPREFETCH; - else if(mode == MODE_16_BIT) - LPC_EEPROM->CMD = EEPROM_CMD_16_BIT_READ|EEPROM_CMD_RDPREFETCH; - else - LPC_EEPROM->CMD = EEPROM_CMD_32_BIT_READ|EEPROM_CMD_RDPREFETCH; - } - } -} - -/*********************************************************************//** - * @brief Erase a page at the specific address - * @param[in] address EEPROM page address (0-62) - * @return data buffer that contain data that will be read to buffer - **********************************************************************/ -void EEPROM_Erase(uint16_t page_address) -{ - uint32_t i; - uint32_t count = EEPROM_PAGE_SIZE/4; - - LPC_EEPROM->INT_CLR_STATUS = ((1 << EEPROM_ENDOF_RW)|(1 << EEPROM_ENDOF_PROG)); - - //clear page register - LPC_EEPROM->ADDR = EEPROM_PAGE_OFFSET(0); - LPC_EEPROM->CMD = EEPROM_CMD_32_BIT_WRITE; - for(i=0;iWDATA = 0; - while(!((LPC_EEPROM->INT_STATUS >> EEPROM_ENDOF_RW)&0x01)); - LPC_EEPROM->INT_CLR_STATUS = (1 << EEPROM_ENDOF_RW); - } - - LPC_EEPROM->INT_CLR_STATUS = (0x1 << EEPROM_ENDOF_PROG); - LPC_EEPROM->ADDR = EEPROM_PAGE_ADRESS(page_address); - LPC_EEPROM->CMD = EEPROM_CMD_ERASE_PRG_PAGE; - while(!((LPC_EEPROM->INT_STATUS >> EEPROM_ENDOF_PROG)&0x01)); - LPC_EEPROM->INT_CLR_STATUS = (1 << EEPROM_ENDOF_PROG); -} - -/*********************************************************************//** - * @brief Enable/Disable EEPROM power down mdoe - * @param[in] NewState PowerDown mode state, should be: - * - ENABLE: Enable power down mode - * - DISABLE: Disable power down mode - * @return None - **********************************************************************/ -void EEPROM_PowerDown(FunctionalState NewState) -{ - if(NewState == ENABLE) - LPC_EEPROM->PWRDWN = 0x1; - else - LPC_EEPROM->PWRDWN = 0x0; -} - -#endif /*_EEPROM*/ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_emac.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_emac.c deleted file mode 100644 index 750b487b547..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_emac.c +++ /dev/null @@ -1,1043 +0,0 @@ -/********************************************************************** -* $Id$ lpc_emac.c 2011-06-02 -*//** -* @file lpc_emac.c -* @brief Contains all functions support for Ethernet MAC firmware -* library on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _EMAC - -#include "lpc_emac.h" -#include "lpc_clkpwr.h" -#include "lpc_pinsel.h" - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup EMAC - * @{ - */ - -/************************** PRIVATE VARIABLES *************************/ - - -/* MII Mgmt Configuration register - Clock divider setting */ -const uint8_t EMAC_clkdiv[] = { 4, 6, 8, 10, 14, 20, 28, 36, 40, 44, 48, 52, 56, 60, 64 }; - -/* EMAC Config data */ -static EMAC_CFG_Type EMAC_Configs; - - -/* EMAC local DMA Descriptors */ - - -#ifdef __IAR_SYSTEMS_ICC__ -/* Global Tx Buffer data */ -#pragma data_alignment=4 -static uint16_t saFrameBuffers[EMAC_MAX_FRAME_NUM][EMAC_MAX_FRAME_SIZE]; -#else -/* Global Rx Buffer data */ -static uint16_t __attribute__ ((aligned (4))) saFrameBuffers[EMAC_MAX_FRAME_NUM][EMAC_MAX_FRAME_SIZE]; -#endif -static uint32_t sulCurrFrameSz = 0; -static uint8_t sbCurrFrameID = 0; - -/***************************** PRIVATE FUNCTION *****************************/ -static void EMAC_UpdateRxConsumeIndex(void); -static void EMAC_UpdateTxProduceIndex(void); -static uint32_t EMAC_AllocTxBuff(uint16_t nFrameSize, uint8_t bLastFrame); -static uint32_t EMAC_GetRxFrameSize(void); - - -/*********************************************************************//** - * @brief - * @param[in] - * @return - **********************************************************************/ -void rx_descr_init (void) -{ - unsigned int i; - - for (i = 0; i < EMAC_NUM_RX_FRAG; i++) - { - RX_DESC_PACKET(i) = RX_BUF(i); - RX_DESC_CTRL(i) = EMAC_RCTRL_INT | (EMAC_ETH_MAX_FLEN-1); - RX_STAT_INFO(i) = 0; - RX_STAT_HASHCRC(i) = 0; - } - - /* Set EMAC Receive Descriptor Registers. */ - LPC_EMAC->RxDescriptor = RX_DESC_BASE; - LPC_EMAC->RxStatus = RX_STAT_BASE; - LPC_EMAC->RxDescriptorNumber = EMAC_NUM_RX_FRAG-1; - - /* Rx Descriptors Point to 0 */ - LPC_EMAC->RxConsumeIndex = 0; -} - -/*********************************************************************//** - * @brief - * @param[in] - * @return - **********************************************************************/ -void tx_descr_init (void) -{ - unsigned int i; - - for (i = 0; i < EMAC_NUM_TX_FRAG; i++) - { - TX_DESC_PACKET(i) = TX_BUF(i); - TX_DESC_CTRL(i) = 0; - TX_STAT_INFO(i) = 0; - } - - /* Set EMAC Transmit Descriptor Registers. */ - LPC_EMAC->TxDescriptor = TX_DESC_BASE; - LPC_EMAC->TxStatus = TX_STAT_BASE; - LPC_EMAC->TxDescriptorNumber = EMAC_NUM_TX_FRAG-1; - - /* Tx Descriptors Point to 0 */ - LPC_EMAC->TxProduceIndex = 0; -} - -/*********************************************************************//** - * @brief Set Station MAC address for EMAC module - * @param[in] abStationAddr Pointer to Station address that contains 6-bytes - * of MAC address. - * @return None - **********************************************************************/ -void setEmacAddr(uint8_t abStationAddr[]) -{ - /* Set the Ethernet MAC Address registers */ - LPC_EMAC->SA0 = ((uint32_t)abStationAddr[5] << 8) | (uint32_t)abStationAddr[4]; - LPC_EMAC->SA1 = ((uint32_t)abStationAddr[3] << 8) | (uint32_t)abStationAddr[2]; - LPC_EMAC->SA2 = ((uint32_t)abStationAddr[1] << 8) | (uint32_t)abStationAddr[0]; -} - - -/************************** GLOBAL/PUBLIC FUNCTIONS *************************/ - -/** @defgroup EMAC_Public_Functions - * @{ - */ - -/*********************************************************************//** - * @brief Write data to PHY - * @param[in] PhyReg PHY register address - * @param[in] Value Register Value - * @return None - **********************************************************************/ -void EMAC_Write_PHY (uint8_t PhyReg, uint16_t Value) -{ - unsigned int tout; - - LPC_EMAC->MADR = ((EMAC_Configs.bPhyAddr & 0x1F) << 8 )| (PhyReg & 0x1F); - LPC_EMAC->MWTD = Value; - - /* Wait utill operation completed */ - tout = 0; - - for (tout = 0; tout < EMAC_MII_WR_TOUT; tout++) - { - if ((LPC_EMAC->MIND & EMAC_MIND_BUSY) == 0) - { - break; - } - } -} - -/*********************************************************************//** - * @brief Read data from PHY register - * @param[in] PhyReg PHY register address - * @return Register value - **********************************************************************/ -uint16_t EMAC_Read_PHY (uint8_t PhyReg) -{ - unsigned int tout; - - LPC_EMAC->MADR = ((EMAC_Configs.bPhyAddr & 0x1F) << 8 )| (PhyReg & 0x1F); - LPC_EMAC->MCMD = EMAC_MCMD_READ; - - /* Wait until operation completed */ - tout = 0; - for (tout = 0; tout < EMAC_MII_RD_TOUT; tout++) - { - if ((LPC_EMAC->MIND & EMAC_MIND_BUSY) == 0) - { - break; - } - } - - LPC_EMAC->MCMD = 0; - return (LPC_EMAC->MRDD); -} - -/*********************************************************************//** - * @brief Set Full/Half Duplex Mode - * @param[in] full_duplex 0: Half-duplex, 1: Full-duplex - * @return None - **********************************************************************/ -void EMAC_SetFullDuplexMode(uint8_t full_duplex) -{ - if(full_duplex) - { - LPC_EMAC->MAC2 |= EMAC_MAC2_FULL_DUP; - LPC_EMAC->Command |= EMAC_CR_FULL_DUP; - LPC_EMAC->IPGT = EMAC_IPGT_FULL_DUP; - } - else - { - LPC_EMAC->IPGT = EMAC_IPGT_HALF_DUP; - } -} -/*********************************************************************//** - * @brief Set PHY Speed - * @param[in] mode_100Mbps 0: 10Mbps, 1: 100Mbps - * @return None - **********************************************************************/ -void EMAC_SetPHYSpeed(uint8_t mode_100Mbps) -{ - if(mode_100Mbps) - { - LPC_EMAC->SUPP = EMAC_SUPP_SPEED; - } - else - { - LPC_EMAC->SUPP = 0; - } -} - - -/*********************************************************************//** - * @brief Initializes the EMAC peripheral according to the specified -* parameters in the EMAC_ConfigStruct. - * @param[in] EMAC_ConfigStruct Pointer to a EMAC_CFG_Type structure -* that contains the configuration information for the -* specified EMAC peripheral. - * @return None - * - * Note: This function will initialize EMAC module according to procedure below: - * - Remove the soft reset condition from the MAC - * - Configure the PHY via the MIIM interface of the MAC - * - Select RMII mode - * - Configure the transmit and receive DMA engines, including the descriptor arrays - * - Configure the host registers (MAC1,MAC2 etc.) in the MAC - * - Enable the receive and transmit data paths - * In default state after initializing, Rx Done and Tx Done interrupt are enabled, - * nad all interrupts are also enabled - * (Ref. from LPC17xx UM) - **********************************************************************/ -int32_t EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct) -{ - /* Initialize the EMAC Ethernet controller. */ - volatile int32_t tout, tmp; - - EMAC_Configs = *EMAC_ConfigStruct; - - /* Set up power for Ethernet module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCENET, ENABLE); - - /* Enable P1 Ethernet Pins. */ - - /* Reset all EMAC internal modules */ - LPC_EMAC->MAC1 = EMAC_MAC1_RES_TX | EMAC_MAC1_RES_MCS_TX | EMAC_MAC1_RES_RX | - EMAC_MAC1_RES_MCS_RX | EMAC_MAC1_SIM_RES | EMAC_MAC1_SOFT_RES; - - LPC_EMAC->Command = EMAC_CR_REG_RES | EMAC_CR_TX_RES | EMAC_CR_RX_RES | EMAC_CR_PASS_RUNT_FRM; - - /* A short delay after reset. */ - for (tout = 100; tout; tout--); - - /* Initialize MAC control registers. */ - LPC_EMAC->MAC1 = EMAC_MAC1_PASS_ALL; - LPC_EMAC->MAC2 = EMAC_MAC2_CRC_EN | EMAC_MAC2_PAD_EN; - LPC_EMAC->MAXF = EMAC_ETH_MAX_FLEN; - /* - * Find the clock that close to desired target clock - */ - tmp = CLKPWR_GetCLK(CLKPWR_CLKTYPE_CPU)/ EMAC_MCFG_MII_MAXCLK; - for (tout = 0; tout < sizeof (EMAC_clkdiv); tout++) - { - if (EMAC_clkdiv[tout] >= tmp) - break; - } - - if(tout >= sizeof (EMAC_clkdiv)) - return ERROR; - tout++; - - // Set Frame size - LPC_EMAC->MAXF = EMAC_ConfigStruct->nMaxFrameSize; - - // Write to MAC configuration register and reset - LPC_EMAC->MCFG = EMAC_MCFG_CLK_SEL(tout) | EMAC_MCFG_RES_MII; - - // release reset - LPC_EMAC->MCFG &= ~(EMAC_MCFG_RES_MII); - LPC_EMAC->CLRT = EMAC_CLRT_DEF; - LPC_EMAC->IPGR = EMAC_IPGR_P2_DEF; - - /* Enable Reduced MII interface. */ - LPC_EMAC->Command = EMAC_CR_RMII | EMAC_CR_PASS_RUNT_FRM; - - - // Initilialize PHY - if(EMAC_ConfigStruct->pfnPHYInit != NULL) - { - if(EMAC_ConfigStruct->pfnPHYInit(&EMAC_ConfigStruct->PhyCfg) != SUCCESS) - { - return ERROR; - } - } - - // Set EMAC address - setEmacAddr(EMAC_ConfigStruct->pbEMAC_Addr); - - /* Initialize Tx and Rx DMA Descriptors */ - rx_descr_init (); - tx_descr_init (); - - // Set Receive Filter register: enable broadcast and multicast - LPC_EMAC->RxFilterCtrl = EMAC_RFC_MCAST_EN | EMAC_RFC_BCAST_EN | EMAC_RFC_PERFECT_EN; - - /* Enable Rx Done and Tx Done interrupt for EMAC */ - EMAC_IntCmd((EMAC_INT_RX_OVERRUN | EMAC_INT_RX_ERR | EMAC_INT_RX_FIN \ - | EMAC_INT_RX_DONE | EMAC_INT_TX_UNDERRUN | EMAC_INT_TX_ERR \ - | EMAC_INT_TX_FIN | EMAC_INT_TX_DONE), ENABLE); - - /* Reset all interrupts */ - LPC_EMAC->IntClear = 0xFFFF; - - /* Enable receive and transmit mode of MAC Ethernet core */ - EMAC_TxEnable(); - EMAC_RxEnable(); - - NVIC_EnableIRQ(ENET_IRQn); - - return SUCCESS; -} - - -/*********************************************************************//** - * @brief De-initializes the EMAC peripheral registers to their -* default reset values. - * @param[in] None - * @return None - **********************************************************************/ -void EMAC_DeInit(void) -{ - // Disable all interrupt - LPC_EMAC->IntEnable = 0x00; - - // Clear all pending interrupt - LPC_EMAC->IntClear = (0xFF) | (EMAC_INT_SOFT_INT | EMAC_INT_WAKEUP); - - LPC_EMAC->Command = 0; - - /* TurnOff power for Ethernet module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCENET, DISABLE); -} - -/*********************************************************************//** - * @brief EMAC TX API modules - * @param[in] None - * @return None - **********************************************************************/ -void EMAC_TxEnable( void ) -{ - LPC_EMAC->Command |= EMAC_CR_TX_EN; - return; -} - - -/*********************************************************************//** - * @brief EMAC RX API modules - * @param[in] None - * @return None - **********************************************************************/ -void EMAC_TxDisable( void ) -{ - LPC_EMAC->Command &= ~EMAC_CR_TX_EN; - return; -} - -/*********************************************************************//** - * @brief EMAC RX API modules - * @param[in] None - * @return None - **********************************************************************/ -void EMAC_RxEnable( void ) -{ - LPC_EMAC->Command |= EMAC_CR_RX_EN; - LPC_EMAC->MAC1 |= EMAC_MAC1_REC_EN; - return; -} - -/*********************************************************************//** - * @brief EMAC RX API modules - * @param[in] None - * @return None - **********************************************************************/ -void EMAC_RxDisable( void ) -{ - LPC_EMAC->Command &= ~EMAC_CR_RX_EN; - LPC_EMAC->MAC1 &= ~EMAC_MAC1_REC_EN; - return; -} - -/*********************************************************************//** - * @brief Get the status of given buffer. - * @param[in] idx Buffer index - * @return EMAC_BUFF_AVAILABLE/EMAC_BUFF_FULL/EMAC_BUFF_PARTIAL_FULL - * - **********************************************************************/ -EMAC_BUFF_STATUS EMAC_GetBufferSts(EMAC_BUFF_IDX idx) -{ - uint32_t consume_idx, produce_idx; - uint32_t max_frag_num; - - // Get the consume index, produce index and the buffer size - if(idx == EMAC_TX_BUFF) - { - consume_idx = LPC_EMAC->TxConsumeIndex; - produce_idx = LPC_EMAC->TxProduceIndex; - max_frag_num = LPC_EMAC->TxDescriptorNumber + 1; - } - else - { - consume_idx = LPC_EMAC->RxConsumeIndex; - produce_idx = LPC_EMAC->RxProduceIndex; - max_frag_num = LPC_EMAC->RxDescriptorNumber + 1; - } - - // empty - if(consume_idx == produce_idx) - return EMAC_BUFF_EMPTY; - - // Full - if(consume_idx == 0 && - produce_idx == max_frag_num - 1) - return EMAC_BUFF_FULL; - - // Wrap-around - if(consume_idx == produce_idx + 1) - return EMAC_BUFF_FULL; - - return EMAC_BUFF_PARTIAL_FULL; -} - -/*********************************************************************//** - * @brief Allocate a descriptor for sending frame and get the coressponding buffer address - * @param[in] FrameSize The size of frame you want to send - * @return Address of the TX_DESC_PACKET buffer - **********************************************************************/ - uint32_t EMAC_AllocTxBuff(uint16_t nFrameSize, uint8_t bLastFrame) -{ - uint32_t idx; - uint32_t dp; - volatile uint32_t i; - - idx = LPC_EMAC->TxProduceIndex; - - while(EMAC_GetBufferSts(EMAC_TX_BUFF) == EMAC_BUFF_FULL) - { - for(i = 0; i < 1000000; i++) ; - } - - dp = TX_DESC_PACKET(idx); - - if(bLastFrame) - TX_DESC_CTRL(idx) = ((nFrameSize-1) & EMAC_TCTRL_SIZE) | (EMAC_TCTRL_INT | EMAC_TCTRL_LAST); - else - TX_DESC_CTRL(idx) = ((nFrameSize-1) & EMAC_TCTRL_SIZE) | (EMAC_TCTRL_INT); - - return dp; -} - -/*********************************************************************//** - * @brief Increase the TxProduceIndex (after writting to the Transmit buffer - * to enable the Transmit buffer) and wrap-around the index if - * it reaches the maximum Transmit Number - * @param[in] None - * @return None - **********************************************************************/ -void EMAC_UpdateTxProduceIndex(void) -{ - // Get current Tx produce index - uint32_t idx = LPC_EMAC->TxProduceIndex; - - /* Start frame transmission */ - if (++idx == LPC_EMAC->TxDescriptorNumber + 1) idx = 0; - LPC_EMAC->TxProduceIndex = idx; -} - -/*********************************************************************//** - * @brief Get current status value of receive data (due to TxProduceIndex) - * @param[in] None - * @return Current value of receive data (due to TxProduceIndex) - **********************************************************************/ -uint32_t EMAC_GetTxFrameStatus(void) -{ - uint32_t idx; - - idx = LPC_EMAC->TxProduceIndex; - return (TX_STAT_INFO(idx)); -} - -/*********************************************************************//** - * @brief Write data to Tx packet data buffer at current index due to - * TxProduceIndex - * @param[in] pDataStruct store the address and the size of buffer that saves data. - * @return None - **********************************************************************/ -void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct) -{ - uint16_t* pDest; - uint16_t* pSource = (uint16_t*)pDataStruct->pbDataBuf; - uint32_t size = pDataStruct->ulDataLen; - int32_t frame_num; - uint32_t tmp; - uint32_t max_frame_size = LPC_EMAC->MAXF; - - size = (size + 1) & 0xFFFE; // round Size up to next even number - frame_num = size/max_frame_size; - - if(size == 0) - return; - - while(frame_num >= 0) - { - tmp = (frame_num > 0)? max_frame_size:size; - - if(tmp == 0) - break; - - // Setup descriptors and data - if(frame_num == 0) - pDest = (uint16_t*)EMAC_AllocTxBuff(tmp, 1); // last frame - else - pDest = (uint16_t*)EMAC_AllocTxBuff(tmp, 0); - - // Copy data - while (tmp > 0) - { - *pDest++ = *pSource++; - tmp -= 2; - } - frame_num--; - size -= tmp; - - // Update produce index - EMAC_UpdateTxProduceIndex(); - } -} - - -/*********************************************************************//** - * @brief Get current status value of receive data (due to RxConsumeIndex) - * @param[in] None - * @return Current value of receive data (due to RxConsumeIndex) - **********************************************************************/ -uint32_t EMAC_GetRxFrameStatus(void) -{ - uint32_t idx; - - idx = LPC_EMAC->RxConsumeIndex; - return (RX_STAT_INFO(idx)); -} - - -/*********************************************************************//** - * @brief Get size of current Received data in received buffer (due to - * RxConsumeIndex) - * @param[in] None - * @return Size of received data - **********************************************************************/ -uint32_t EMAC_GetRxFrameSize(void) -{ - uint32_t idx; - - idx = LPC_EMAC->RxConsumeIndex; - - return (((RX_STAT_INFO(idx)) & EMAC_RINFO_SIZE)+1); -} - - -/*********************************************************************//** - * @brief Get the address of TX_DESC_PACKET buffer so that user can access from application - * @param[in] None - * @return Address of the TX_DESC_PACKET buffer - **********************************************************************/ - -uint32_t EMAC_GetRxBuffer(void) -{ - uint32_t idx; - - idx = LPC_EMAC->RxConsumeIndex; - - return RX_DESC_PACKET(idx); - } - - -/*********************************************************************//** - * @brief Increase the RxConsumeIndex (after reading the Receive buffer - * to release the Receive buffer) and wrap-around the index if - * it reaches the maximum Receive Number - * @param[in] None - * @return None - **********************************************************************/ -void EMAC_UpdateRxConsumeIndex(void) -{ - // Get current Rx consume index - uint32_t idx = LPC_EMAC->RxConsumeIndex; - - /* Release frame from EMAC buffer */ - if (++idx == EMAC_NUM_RX_FRAG) idx = 0; - - LPC_EMAC->RxConsumeIndex = idx; -} - -/*********************************************************************//** - * @brief Standard EMAC IRQ Handler. This sub-routine will check - * these following interrupt and call the call-back function - * if they're already installed: - * - Overrun Error interrupt in RX Queue - * - Receive Error interrupt: AlignmentError, RangeError, - * LengthError, SymbolError, CRCError or NoDescriptor or Overrun - * - RX Finished Process Descriptors interrupt (ProduceIndex == ConsumeIndex) - * - Receive Done interrupt: Read received frame to the internal buffer - * - Transmit Under-run interrupt - * - Transmit errors interrupt : LateCollision, ExcessiveCollision - * and ExcessiveDefer, NoDescriptor or Under-run - * - TX Finished Process Descriptors interrupt (ProduceIndex == ConsumeIndex) - * - Transmit Done interrupt - * - Interrupt triggered by software - * - Interrupt triggered by a Wakeup event detected by the receive filter - * @param[in] None - * @return None - **********************************************************************/ -void ENET_IRQHandler(void) -{ - /* EMAC Ethernet Controller Interrupt function. */ - uint32_t int_stat; - int32_t RxLen; - - // Get EMAC interrupt status - while ((int_stat = (LPC_EMAC->IntStatus & LPC_EMAC->IntEnable)) != 0) - { - // Clear interrupt status - LPC_EMAC->IntClear = int_stat; - - if(int_stat & (EMAC_INT_RX_OVERRUN |EMAC_INT_RX_ERR )) - { - uint32_t ulFrameSts = EMAC_GetRxFrameStatus(); - uint32_t ulErrCode = 0; - - ulErrCode |= (ulFrameSts & EMAC_RINFO_CRC_ERR) ? EMAC_CRC_ERR:0; - ulErrCode |= (ulFrameSts & EMAC_RINFO_SYM_ERR) ? EMAC_SYMBOL_ERR:0; - ulErrCode |= (ulFrameSts & EMAC_RINFO_LEN_ERR) ? EMAC_LENGTH_ERR:0; - ulErrCode |= (ulFrameSts & EMAC_RINFO_ALIGN_ERR) ? EMAC_ALIGN_ERR:0; - ulErrCode |= (ulFrameSts & EMAC_RINFO_OVERRUN) ? EMAC_OVERRUN_ERR:0; - ulErrCode |= (ulFrameSts & EMAC_RINFO_NO_DESCR) ? EMAC_RX_NO_DESC_ERR:0; - ulErrCode |= (ulFrameSts & EMAC_RINFO_FAIL_FILT) ? EMAC_FILTER_FAILED_ERR:0; - - if(ulErrCode == 0) - { - /* Note: - * The EMAC doesn't distinguish the frame type and frame length, - * so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, - * it compares the frame type with the max length and gives the - * "Range" error. In fact, this bit is not an error indication, - * but simply a statement by the chip regarding the status of - * the received frame - */ - int_stat &= ~EMAC_INT_RX_ERR; - } - else - { - if(EMAC_Configs.pfnErrorReceive != NULL) - EMAC_Configs.pfnErrorReceive(ulErrCode); - } - } - - if(int_stat & (EMAC_INT_TX_UNDERRUN|EMAC_INT_TX_ERR )) - { - uint32_t ulFrameSts = EMAC_GetTxFrameStatus(); - uint32_t ulErrCode = 0; - - ulErrCode |= (ulFrameSts & EMAC_TINFO_EXCESS_DEF) ? EMAC_EXCESSIVE_DEFER_ERR:0; - ulErrCode |= (ulFrameSts & EMAC_TINFO_EXCESS_COL) ? EMAC_EXCESSIVE_COLLISION_ERR:0; - ulErrCode |= (ulFrameSts & EMAC_TINFO_LATE_COL) ? EMAC_LATE_COLLISION_ERR:0; - ulErrCode |= (ulFrameSts & EMAC_TINFO_UNDERRUN) ? EMAC_UNDERRUN_ERR:0; - ulErrCode |= (ulFrameSts & EMAC_TINFO_NO_DESCR) ? EMAC_TX_NO_DESC_ERR:0; - if(EMAC_Configs.pfnErrorReceive != NULL) - EMAC_Configs.pfnErrorReceive(ulErrCode); - } - - if(int_stat & EMAC_INT_RX_DONE) - { - - /* Packet received. */ - if(EMAC_GetBufferSts(EMAC_RX_BUFF) != EMAC_BUFF_EMPTY) - { - // Get data size - RxLen = EMAC_GetRxFrameSize(); - if(RxLen > 0) - { - // trip out 4-bytes CRC field, note that length in (-1) style format - RxLen -= 3; - - if((EMAC_GetRxFrameStatus() & EMAC_RINFO_ERR_MASK )== 0) - { - uint16_t *pDest = (uint16_t*) &saFrameBuffers[sbCurrFrameID][sulCurrFrameSz]; - uint16_t *pSource = (uint16_t*)EMAC_GetRxBuffer(); - sulCurrFrameSz += RxLen; - - if(sulCurrFrameSz >= EMAC_MAX_FRAME_SIZE) - { - sulCurrFrameSz = 0; - if(EMAC_Configs.pfnErrorReceive != NULL) - EMAC_Configs.pfnErrorReceive(EMAC_LENGTH_ERR); - } - else - { - // Copy data - while (RxLen > 0) - { - *pDest++ = *pSource++; - RxLen -= 2; - } - if(EMAC_GetRxFrameStatus() & EMAC_RINFO_LAST_FLAG) - { - - if(EMAC_Configs.pfnFrameReceive != NULL) - { - EMAC_Configs.pfnFrameReceive((uint16_t*)saFrameBuffers[sbCurrFrameID], sulCurrFrameSz); - } - sulCurrFrameSz = 0; - sbCurrFrameID ++; - if(sbCurrFrameID >= EMAC_MAX_FRAME_NUM) - sbCurrFrameID = 0; - } - /* Release frame from EMAC buffer */ - EMAC_UpdateRxConsumeIndex(); - } - } - } - } - - } - - if(int_stat & EMAC_INT_TX_FIN && (EMAC_Configs.pfnTransmitFinish != NULL)) - { - EMAC_Configs.pfnTransmitFinish(); - } - - if(int_stat & EMAC_INT_SOFT_INT && (EMAC_Configs.pfnSoftInt!= NULL)) - { - EMAC_Configs.pfnSoftInt(); - } - - if(int_stat & EMAC_INT_WAKEUP && (EMAC_Configs.pfnWakeup!= NULL)) - { - EMAC_Configs.pfnWakeup(); - } - - } -} - - -/*********************************************************************//** - * @brief Enable/Disable hash filter functionality for specified destination - * MAC address in EMAC module - * @param[in] dstMAC_addr Pointer to the first MAC destination address, should - * be 6-bytes length, in order LSB to the MSB - * @param[in] NewState New State of this command, should be: - * - ENABLE. - * - DISABLE. - * @return None - * - * Note: - * The standard Ethernet cyclic redundancy check (CRC) function is calculated from - * the 6 byte destination address in the Ethernet frame (this CRC is calculated - * anyway as part of calculating the CRC of the whole frame), then bits [28:23] out of - * the 32 bits CRC result are taken to form the hash. The 6 bit hash is used to access - * the hash table: it is used as an index in the 64 bit HashFilter register that has been - * programmed with accept values. If the selected accept value is 1, the frame is - * accepted. - **********************************************************************/ -void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState) -{ - uint32_t *pReg; - uint32_t tmp; - int32_t crc; - - // Calculate the CRC from the destination MAC address - crc = EMAC_CRCCalc(dstMAC_addr, 6); - // Extract the value from CRC to get index value for hash filter table - crc = (crc >> 23) & 0x3F; - - pReg = (crc > 31) ? ((uint32_t *)&LPC_EMAC->HashFilterH) \ - : ((uint32_t *)&LPC_EMAC->HashFilterL); - tmp = (crc > 31) ? (crc - 32) : crc; - if (NewState == ENABLE) - { - (*pReg) |= (1UL << tmp); - } - else - { - (*pReg) &= ~(1UL << tmp); - } - -} - - -/*********************************************************************//** - * @brief Calculates CRC code for number of bytes in the frame - * @param[in] frame_no_fcs Pointer to the first byte of the frame - * @param[in] frame_len length of the frame without the FCS - * @return the CRC as a 32 bit integer - **********************************************************************/ -int32_t EMAC_CRCCalc(uint8_t frame_no_fcs[], int32_t frame_len) -{ - int i; // iterator - int j; // another iterator - char byte; // current byte - int crc; // CRC result - int q0, q1, q2, q3; // temporary variables - - crc = 0xFFFFFFFF; - - for (i = 0; i < frame_len; i++) - { - byte = *frame_no_fcs++; - for (j = 0; j < 2; j++) - { - if (((crc >> 28) ^ (byte >> 3)) & 0x00000001) - { - q3 = 0x04C11DB7; - } - else - { - q3 = 0x00000000; - } - - if (((crc >> 29) ^ (byte >> 2)) & 0x00000001) - { - q2 = 0x09823B6E; - } - else - { - q2 = 0x00000000; - } - - if (((crc >> 30) ^ (byte >> 1)) & 0x00000001) - { - q1 = 0x130476DC; - } - else - { - q1 = 0x00000000; - } - - if (((crc >> 31) ^ (byte >> 0)) & 0x00000001) - { - q0 = 0x2608EDB8; - } - else - { - q0 = 0x00000000; - } - - crc = (crc << 4) ^ q3 ^ q2 ^ q1 ^ q0; - - byte >>= 4; - } - } - - return crc; -} - -/*********************************************************************//** - * @brief Enable/Disable Filter mode for each specified type EMAC peripheral - * @param[in] ulFilterMode Filter mode, should be: - * - EMAC_RFC_UCAST_EN: all frames of unicast types - * will be accepted - * - EMAC_RFC_BCAST_EN: broadcast frame will be - * accepted - * - EMAC_RFC_MCAST_EN: all frames of multicast - * types will be accepted - * - EMAC_RFC_UCAST_HASH_EN: The imperfect hash - * filter will be applied to unicast addresses - * - EMAC_RFC_MCAST_HASH_EN: The imperfect hash - * filter will be applied to multicast addresses - * - EMAC_RFC_PERFECT_EN: the destination address - * will be compared with the 6 byte station address - * programmed in the station address by the filter - * - EMAC_RFC_MAGP_WOL_EN: the result of the magic - * packet filter will generate a WoL interrupt when - * there is a match - * - EMAC_RFC_PFILT_WOL_EN: the result of the perfect address - * matching filter and the imperfect hash filter will - * generate a WoL interrupt when there is a match - * @param[in] NewState New State of this command, should be: - * - ENABLE - * - DISABLE - * @return None - **********************************************************************/ -void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - LPC_EMAC->RxFilterCtrl |= ulFilterMode; - - if((ulFilterMode & EMAC_RFC_MCAST_HASH_EN) && - ((ulFilterMode & EMAC_RFC_MCAST_EN) == 0)) - { - LPC_EMAC->RxFilterCtrl &= ~EMAC_RFC_MCAST_EN; - } - if((ulFilterMode & EMAC_RFC_UCAST_HASH_EN) && - ((ulFilterMode & EMAC_RFC_UCAST_EN) == 0)) - { - LPC_EMAC->RxFilterCtrl &= ~EMAC_RFC_UCAST_EN; - } - } - else - { - LPC_EMAC->RxFilterCtrl &= ~ulFilterMode; - } -} - -/*********************************************************************//** - * @brief Get status of Wake On LAN Filter for each specified - * type in EMAC peripheral, clear this status if it is set - * @param[in] ulFilterMode WoL Filter mode, should be: - * - EMAC_WOL_UCAST: unicast frames caused WoL - * - EMAC_WOL_UCAST: broadcast frame caused WoL - * - EMAC_WOL_MCAST: multicast frame caused WoL - * - EMAC_WOL_UCAST_HASH: unicast frame that passes the - * imperfect hash filter caused WoL - * - EMAC_WOL_MCAST_HASH: multicast frame that passes the - * imperfect hash filter caused WoL - * - EMAC_WOL_PERFECT:perfect address matching filter - * caused WoL - * - EMAC_WOL_RX_FILTER: the receive filter caused WoL - * - EMAC_WOL_MAG_PACKET: the magic packet filter caused WoL - * @return SET/RESET - **********************************************************************/ -FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode) -{ - if (LPC_EMAC->RxFilterWoLStatus & ulWoLMode) - { - LPC_EMAC->RxFilterWoLClear = ulWoLMode; - - return SET; - } - else - { - return RESET; - } -} - - - - - - -/*********************************************************************//** - * @brief Enable/Disable interrupt for each type in EMAC - * @param[in] ulIntType Interrupt Type, should be: - * - EMAC_INT_RX_OVERRUN: Receive Overrun - * - EMAC_INT_RX_ERR: Receive Error - * - EMAC_INT_RX_FIN: Receive Descriptor Finish - * - EMAC_INT_RX_DONE: Receive Done - * - EMAC_INT_TX_UNDERRUN: Transmit Under-run - * - EMAC_INT_TX_ERR: Transmit Error - * - EMAC_INT_TX_FIN: Transmit descriptor finish - * - EMAC_INT_TX_DONE: Transmit Done - * - EMAC_INT_SOFT_INT: Software interrupt - * - EMAC_INT_WAKEUP: Wakeup interrupt - * @param[in] NewState New State of this function, should be: - * - ENABLE. - * - DISABLE. - * @return None - **********************************************************************/ -void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - LPC_EMAC->IntEnable |= ulIntType; - } - else - { - LPC_EMAC->IntEnable &= ~(ulIntType); - } -} - -/*********************************************************************//** - * @brief Check whether if specified interrupt flag is set or not - * for each interrupt type in EMAC and clear interrupt pending - * if it is set. - * @param[in] ulIntType Interrupt Type, should be: - * - EMAC_INT_RX_OVERRUN: Receive Overrun - * - EMAC_INT_RX_ERR: Receive Error - * - EMAC_INT_RX_FIN: Receive Descriptor Finish - * - EMAC_INT_RX_DONE: Receive Done - * - EMAC_INT_TX_UNDERRUN: Transmit Under-run - * - EMAC_INT_TX_ERR: Transmit Error - * - EMAC_INT_TX_FIN: Transmit descriptor finish - * - EMAC_INT_TX_DONE: Transmit Done - * - EMAC_INT_SOFT_INT: Software interrupt - * - EMAC_INT_WAKEUP: Wakeup interrupt - * @return New state of specified interrupt (SET or RESET) - **********************************************************************/ -IntStatus EMAC_IntGetStatus(uint32_t ulIntType) -{ - if (LPC_EMAC->IntStatus & ulIntType) - { - LPC_EMAC->IntClear = ulIntType; - return SET; - } - else - { - return RESET; - } -} - - - -/** - * @} - */ - -/** - * @} - */ -#endif /*_EMAC*/ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_emc.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_emc.c deleted file mode 100644 index 0ede2221e7c..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_emc.c +++ /dev/null @@ -1,1398 +0,0 @@ -/********************************************************************** -* $Id$ lpc_emc.c 2011-06-02 -*//** -* @file lpc_emc.c -* @brief Contains all functions support for EMC firmware library -* on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _EMC - -#include "lpc_emc.h" -#include "lpc_clkpwr.h" -#include "lpc_pinsel.h" - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup EMC - * @{ - */ - -/** @defgroup EMC_Public_Functions - * @{ - */ - -/********************************************************************* - * @brief Calculate refresh timer (the multiple of 16 CCLKs) - * @param[in] freq - frequency of EMC Clk - * @param[in] time - micro second - * @return None - **********************************************************************/ -uint32_t EMC_SDRAM_REFRESH(uint32_t time) -{ - uint32_t emc_freq = CLKPWR_GetCLK(CLKPWR_CLKTYPE_EMC); - return (((uint64_t)((uint64_t)time * emc_freq)/16000000ull)+1); -} -/********************************************************************* - * @brief Calculate EMC Clock from nano second - * @param[in] time - nano second - * @return None - **********************************************************************/ -uint32_t EMC_NS2CLK(uint32_t time){ - uint32_t emc_freq = CLKPWR_GetCLK(CLKPWR_CLKTYPE_EMC); - return (((uint64_t)time*emc_freq/1000000000ull)); -} - -/********************************************************************* - * @brief Power on EMC Block - * @param[in] None - * @return None - **********************************************************************/ -EMC_FUNC_CODE EMC_PwrOn(void) -{ - // If CPU clock is > 80 MHz, then divide it by two to create the EMC clock - if(CLKPWR_GetCLK(CLKPWR_CLKTYPE_CPU) > 80000000) { - CLKPWR_SetCLKDiv(CLKPWR_CLKTYPE_EMC, 1); // CPU clock / 2 - } else { - CLKPWR_SetCLKDiv(CLKPWR_CLKTYPE_EMC, 0); // Same clock as CPU - } - - // Power on - CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCEMC, ENABLE); - - // Enable - LPC_EMC->Control = EMC_Control_E; - - return EMC_FUNC_OK; -} -/*********************************************************************//** - * @brief Initialize external dynamic memory - * @param[in] pConfig Configuration - * @return EMC_FUNC_OK/EMC_FUNC_INVALID_PARAM/EMC_FUNC_ERR - **********************************************************************/ -EMC_FUNC_CODE DynMem_Init(EMC_DYN_MEM_Config_Type* pConfig) -{ - uint32_t i = 0; - EMC_FUNC_CODE ret = EMC_FUNC_OK; - - /* Pin configuration: - * P2.16 - /EMC_CAS - * P2.17 - /EMC_RAS - * P2.18 - EMC_CLK[0] - * P2.19 - EMC_CLK[1] - * - * P2.20 - EMC_DYCS0 - * P2.21 - EMC_DYCS1 - * P2.22 - EMC_DYCS2 - * P2.23 - EMC_DYCS3 - * - * P2.24 - EMC_CKE0 - * P2.25 - EMC_CKE1 - * P2.26 - EMC_CKE2 - * P2.27 - EMC_CKE3 - * - * P2.28 - EMC_DQM0 - * P2.29 - EMC_DQM1 - * P2.30 - EMC_DQM2 - * P2.31 - EMC_DQM3 - * - * P3.0-P3.31 - EMC_D[0-31] - * P4.0-P4.23 - EMC_A[0-23] - * P5.0-P5.1 - EMC_A[24-25] - * - * P4.25 - EMC_WE - */ - PINSEL_ConfigPin(2,16,1); - PINSEL_ConfigPin(2,17,1); - PINSEL_ConfigPin(2,18,1); - PINSEL_ConfigPin(2,19,1); - PINSEL_ConfigPin(2,20,1); - PINSEL_ConfigPin(2,21,1); - PINSEL_ConfigPin(2,22,1); - PINSEL_ConfigPin(2,23,1); - PINSEL_ConfigPin(2,24,1); - PINSEL_ConfigPin(2,25,1); - PINSEL_ConfigPin(2,26,1); - PINSEL_ConfigPin(2,27,1); - PINSEL_ConfigPin(2,28,1); - PINSEL_ConfigPin(2,29,1); - PINSEL_ConfigPin(2,30,1); - PINSEL_ConfigPin(2,31,1); - - for(i = 0; i < 32; i++) - { - PINSEL_ConfigPin(3,i,1); - PINSEL_ConfigPin(4,i,1); - } - PINSEL_ConfigPin(5,0,1); - PINSEL_ConfigPin(5,1,1); - - - // Power On - ret |= EMC_PwrOn(); - - /*Init SDRAM controller*/ - LPC_SC->EMCDLYCTL |= (8<<0); - /*Set data read delay*/ - LPC_SC->EMCDLYCTL |=(8<<8); - LPC_SC->EMCDLYCTL |= (0x08 <<16); - - ret |= EMC_ConfigEndianMode(EMC_Config_Little_Endian_Mode); - - /* Dynamic memory setting */ - ret |= EMC_DynCtrlSelfRefresh(EMC_DYNAMIC_CTRL_SR_NORMALMODE); - ret |= EMC_DynCtrlPowerDownMode(EMC_DYNAMIC_CTRL_DP_NORMAL); - ret |= EMC_DynCtrlClockEnable(EMC_DYNAMIC_CTRL_CE_ALLCLK_HI); - ret |= EMC_DynCtrlMMC(EMC_DYNAMIC_CTRL_MMC_CLKOUT_ENABLED); - ret |= EMC_DynCtrlClockControl(EMC_DYNAMIC_CTRL_CE_CLKOUT_CONT); - - /* Timing */ - ret |= EMC_SetDynMemoryParameter(EMC_DYN_MEM_REFRESH_TIMER, pConfig->RefreshTime); - ret |= EMC_SetDynMemoryParameter(EMC_DYN_MEM_READ_CONFIG, pConfig->ReadConfig); - ret |= EMC_SetDynMemoryParameter(EMC_DYN_MEM_TRP, pConfig->PrechargeCmdPeriod); - ret |= EMC_SetDynMemoryParameter(EMC_DYN_MEM_TRAS, pConfig->Active2PreChargeTime); - ret |= EMC_SetDynMemoryParameter(EMC_DYN_MEM_TSREX, pConfig->SeftRefreshExitTime); - ret |= EMC_SetDynMemoryParameter(EMC_DYN_MEM_TAPR, pConfig->DataOut2ActiveTime); - ret |= EMC_SetDynMemoryParameter(EMC_DYN_MEM_TDAL, pConfig->DataIn2ActiveTime); - ret |= EMC_SetDynMemoryParameter(EMC_DYN_MEM_TWR, pConfig->WriteRecoveryTime); - ret |= EMC_SetDynMemoryParameter(EMC_DYN_MEM_TRC, pConfig->Active2ActivePeriod); - ret |= EMC_SetDynMemoryParameter(EMC_DYN_MEM_TRFC, pConfig->AutoRefrehPeriod); - ret |= EMC_SetDynMemoryParameter(EMC_DYN_MEM_TXSR, pConfig->ExitSelfRefreshTime); - ret |= EMC_SetDynMemoryParameter(EMC_DYN_MEM_TRRD, pConfig->ActiveBankLatency); - ret |= EMC_SetDynMemoryParameter(EMC_DYN_MEM_TMRD, pConfig->LoadModeReg2Active); - ret |= EMC_DynMemRAS(pConfig->CSn,pConfig->RASLatency); - ret |= EMC_DynMemCAS(pConfig->CSn,pConfig->CASLatency); - - ret |= EMC_DynMemConfigMD(pConfig->CSn,EMC_DYNAMIC_CFG_MEMDEV_SDRAM); - ret |= EMC_DynMemConfigAM(pConfig->CSn, pConfig->AddrBusWidth, pConfig->AddrMap, pConfig->DataWidth, pConfig->ChipSize); - - return ret; -} - -/*********************************************************************//** - * @brief Initialize external static memory - * @param[in] pConfig Configuration - * @return EMC_FUNC_OK/EMC_FUNC_INVALID_PARAM/EMC_FUNC_ERR - **********************************************************************/ -EMC_FUNC_CODE StaticMem_Init(EMC_STATIC_MEM_Config_Type* pConfig) -{ - uint32_t i; - EMC_FUNC_CODE ret = EMC_FUNC_OK; - /* Pin configuration: - * P4.30 - /EMC_CS0 - * P4.31 - /EMC_CS1 - * P2.14 - /EMC_CS2 - * P2.15 - /EMC_CS3 - * - * - * P3.0-P3.31 - EMC_D[0-31] - * P4.0-P4.23 - EMC_A[0-23] - * P5.0-P5.1 - EMC_A[24-25] - * - * P4.24 - /EMC_OE - * P4.25 - /EMC_WE - * - - */ - PINSEL_ConfigPin(2,14,1); - PINSEL_ConfigPin(2,15,1); - - for(i = 0; i < 32; i++) - { - PINSEL_ConfigPin(3,i,1); - PINSEL_ConfigPin(4,i,1); - } - PINSEL_ConfigPin(5,0,1); - PINSEL_ConfigPin(5,1,1); - - // Power On - ret |= EMC_PwrOn(); - - // Configuration - if(pConfig->AddressMirror) - { - LPC_EMC->Control |= EMC_Control_M; - } - - ret |= EMC_StaMemConfigMW(pConfig->CSn,pConfig->DataWidth); - - if(pConfig->PageMode) - ret |= EMC_StaMemConfigPM(pConfig->CSn,EMC_CFG_PM_ASYNC_ENABLE); - else - ret |= EMC_StaMemConfigPM(pConfig->CSn,EMC_CFG_PM_DISABLE); - - if(pConfig->ByteLane) - ret |= EMC_StaMemConfigPB(pConfig->CSn, EMC_CFG_BYTELAND_READ_BITSLOW); - else - ret |= EMC_StaMemConfigPB(pConfig->CSn, EMC_CFG_BYTELAND_READ_BITSHIGH); - - if(pConfig->ExtendedWait) - ret |= EMC_StaMemConfigEW(pConfig->CSn,EMC_CFG_EW_ENABLED); - else - ret |= EMC_StaMemConfigEW(pConfig->CSn,EMC_CFG_EW_DISABLED); - - // Timing - ret |= EMC_SetStaMemoryParameter(pConfig->CSn,EMC_STA_MEM_WAITWEN, pConfig->WaitWEn); - ret |= EMC_SetStaMemoryParameter(pConfig->CSn,EMC_STA_MEM_WAITOEN, pConfig->WaitOEn); - ret |= EMC_SetStaMemoryParameter(pConfig->CSn,EMC_STA_MEM_WAITRD, pConfig->WaitRd); - ret |= EMC_SetStaMemoryParameter(pConfig->CSn,EMC_STA_MEM_WAITPAGE, pConfig->WaitPage); - ret |= EMC_SetStaMemoryParameter(pConfig->CSn,EMC_STA_MEM_WAITWR, pConfig->WaitWr); - ret |= EMC_SetStaMemoryParameter(pConfig->CSn,EMC_STA_MEM_WAITTURN, pConfig->WaitTurn); - - - return ret; -} - -/*********************************************************************//** - * @brief EMC initialize (power on block, config EMC pins). - * @param[in] None - * @return None - **********************************************************************/ -EMC_FUNC_CODE EMC_Init(void) -{ - uint8_t i; - // If CPU clock is > 80 MHz, then divide it by two to create the EMC clock - if(CLKPWR_GetCLK(CLKPWR_CLKTYPE_CPU) > 80000000) { - CLKPWR_SetCLKDiv(CLKPWR_CLKTYPE_EMC, 1); // CPU clock / 2 - } else { - CLKPWR_SetCLKDiv(CLKPWR_CLKTYPE_EMC, 0); // Same clock as CPU - } - - LPC_SC->PCONP |= 0x00000800; - LPC_SC->EMCDLYCTL = 0x00001010; - LPC_EMC->Control = 0x00000001; - LPC_EMC->Config = 0x00000000; - - /* Pin configuration: - * P2.14 - /EMC_CS2 - * P2.15 - /EMC_CS3 - * - * P2.16 - /EMC_CAS - * P2.17 - /EMC_RAS - * P2.18 - EMC_CLK[0] - * P2.19 - EMC_CLK[1] - * - * P2.20 - EMC_DYCS0 - * P2.21 - EMC_DYCS1 - * P2.22 - EMC_DYCS2 - * P2.23 - EMC_DYCS3 - * - * P2.24 - EMC_CKE0 - * P2.25 - EMC_CKE1 - * P2.26 - EMC_CKE2 - * P2.27 - EMC_CKE3 - * - * P2.28 - EMC_DQM0 - * P2.29 - EMC_DQM1 - * P2.30 - EMC_DQM2 - * P2.31 - EMC_DQM3 - * - * P3.0-P3.31 - EMC_D[0-31] - * P4.0-P4.23 - EMC_A[0-23] - * P5.0-P5.1 - EMC_A[24-25] - * - * P4.24 - /EMC_OE - * P4.25 - /EMC_WE - * - * P4.30 - /EMC_CS0 - * P4.31 - /EMC_CS1 - */ - PINSEL_ConfigPin(2,14,1); - PINSEL_ConfigPin(2,15,1); - PINSEL_ConfigPin(2,16,1); - PINSEL_ConfigPin(2,17,1); - PINSEL_ConfigPin(2,18,1); - PINSEL_ConfigPin(2,19,1); - PINSEL_ConfigPin(2,20,1); - PINSEL_ConfigPin(2,21,1); - PINSEL_ConfigPin(2,22,1); - PINSEL_ConfigPin(2,23,1); - PINSEL_ConfigPin(2,24,1); - PINSEL_ConfigPin(2,25,1); - PINSEL_ConfigPin(2,26,1); - PINSEL_ConfigPin(2,27,1); - PINSEL_ConfigPin(2,28,1); - PINSEL_ConfigPin(2,29,1); - PINSEL_ConfigPin(2,30,1); - PINSEL_ConfigPin(2,31,1); - - for(i = 0; i < 32; i++) - { - PINSEL_ConfigPin(3,i,1); - PINSEL_ConfigPin(4,i,1); - } - PINSEL_ConfigPin(5,0,1); - PINSEL_ConfigPin(5,1,1); - - return EMC_FUNC_OK; -} - - -/*********************************************************************//** - * @brief Configure Little Endian/Big Endian mode for EMC - * - * @param[in] endia_mode Endian mode, should be: - * - * - EMC_Config_Little_Endian_Mode: Little-endian mode - * - * - EMC_Config_Big_Endian_Mode : Big-endian mode - * - * @return EMC_FUNC_OK - **********************************************************************/ -EMC_FUNC_CODE EMC_ConfigEndianMode(uint32_t endian_mode) -{ - LPC_EMC->Config &= ~(EMC_Config_Endian_Mask); - LPC_EMC->Config |= (endian_mode&EMC_Config_Endian_Mask); - return EMC_FUNC_OK; -} - -/****************** Group of Dynamic control functions************************/ - -/*********************************************************************//** - * @brief Set the dsvalue for dynamic clock enable bit - * - * @param[in] clock_enable clock enable mode, should be: - * - * - EMC_DYNAMIC_CTRL_CE_SAVEPWR: Clock enable of idle devices - * are deasserted to save power - * - * - EMC_DYNAMIC_CTRL_CE_ALLCLK_HI: All clock enables are driven - * HIGH continuously - * - * @return EMC_FUNC_CODE - **********************************************************************/ -EMC_FUNC_CODE EMC_DynCtrlClockEnable(uint32_t clock_enable) -{ - LPC_EMC->DynamicControl &= ~(EMC_DYNAMIC_CTRL_MEMCLK_EN_BMASK); - LPC_EMC->DynamicControl |= clock_enable & EMC_DYNAMIC_CTRL_MEMCLK_EN_BMASK; - return EMC_FUNC_OK; -} - - -/*********************************************************************//** - * @brief Set the value for dynamic memory clock control: stops or - * runs continuously - * - * @param[in] clock_control clock control mode, should be: - * - * - EMC_DYNAMIC_CTRL_CS_CLKOUT_STOP: CLKOUT stops when all - * SDRAMs are idle and during self-refresh mode - * - * - EMC_DYNAMIC_CTRL_CS_CLKOUT_CONT: CLKOUT runs continuously - * - * @return EMC_FUNC_OK - **********************************************************************/ -EMC_FUNC_CODE EMC_DynCtrlClockControl(int32_t clock_control) -{ - LPC_EMC->DynamicControl &= ~EMC_DYNAMIC_CTRL_CLKCTRL_BMASK; - LPC_EMC->DynamicControl |= clock_control & EMC_DYNAMIC_CTRL_CLKCTRL_BMASK; - return EMC_FUNC_OK; -} - -/*********************************************************************//** - * @brief Switch the Self-refresh mode between normal and self-refresh mode - * - * @param[in] self_refresh_mode self refresh mode, should be: - * - * - EMC_DYNAMIC_CTRL_SR_NORMALMODE: Normal mode - * - * - EMC_DYNAMIC_CTRL_SR_SELFREFRESH: Enter self-refresh mode - * - * @return EMC_FUNC_OK - **********************************************************************/ -EMC_FUNC_CODE EMC_DynCtrlSelfRefresh(uint32_t self_refresh_mode) -{ - LPC_EMC->DynamicControl &= ~EMC_DYNAMIC_CTRL_SELFREFRESH_REQ_BMASK; - LPC_EMC->DynamicControl =self_refresh_mode & EMC_DYNAMIC_CTRL_SELFREFRESH_REQ_BMASK; - return EMC_FUNC_OK; -} - -/*********************************************************************//** - * @brief Enable/disable CLKOUT - * - * @param[in] MMC_val Memory clock control mode, should be: - * - * - EMC_DYNAMIC_CTRL_MMC_CLKOUT_ENABLED: CLKOUT enabled - * - * - EMC_DYNAMIC_CTRL_MMC_CLKOUT_DISABLED: CLKOUT disabled - * - * @return EMC_FUNC_OK - **********************************************************************/ -EMC_FUNC_CODE EMC_DynCtrlMMC(uint32_t MMC_val) -{ - LPC_EMC->DynamicControl &= ~EMC_DYNAMIC_CTRL_MMC_CLKOUTCTRL_BMASK; - LPC_EMC->DynamicControl |=MMC_val & EMC_DYNAMIC_CTRL_MMC_CLKOUTCTRL_BMASK; - return EMC_FUNC_OK; -} - -/*********************************************************************//** - * @brief Issue SDRAM command - * - * @param[in] SDRAM_command Command mode, should be: - * - * - EMC_DYNAMIC_CTRL_SDRAM_NORMAL: Issue SDRAM NORMAL operation command - * - * - EMC_DYNAMIC_CTRL_SDRAM_MODE: Issue SDRAM MODE command - * - * - EMC_DYNAMIC_CTRL_SDRAM_PALL: Issue SDRAM PALL (precharge all) command - * - * - EMC_DYNAMIC_CTRL_SDRAM_NOP: Issue SRAM NOP (no operation) command - * - * @return EMC_FUNC_OK - **********************************************************************/ -EMC_FUNC_CODE EMC_DynCtrlSDRAMInit(uint32_t SDRAM_command) -{ - LPC_EMC->DynamicControl &= ~EMC_DYNAMIC_CTRL_SDRAM_INIT_BMASK; - LPC_EMC->DynamicControl |= SDRAM_command & EMC_DYNAMIC_CTRL_SDRAM_INIT_BMASK; - return EMC_FUNC_OK; -} - -/*********************************************************************//** - * @brief Switch between Normal operation and deep sleep power mode - * - * @param[in] Power_command Low-power SDRAM deep-sleep mode, should be: - * - * - EMC_DYNAMIC_CTRL_DP_NORMAL: Normal operation - * - * - EMC_DYNAMIC_CTRL_DP_DEEPSLEEP: Enter deep-sleep mode - * - * @return EMC_FUNC_OK - **********************************************************************/ -EMC_FUNC_CODE EMC_DynCtrlPowerDownMode(uint32_t Power_command) -{ - LPC_EMC->DynamicControl &= ~EMC_DYNAMIC_CTRL_SDRAM_PWRMODE_BMASK; - LPC_EMC->DynamicControl |= Power_command & EMC_DYNAMIC_CTRL_SDRAM_PWRMODE_BMASK; - return EMC_FUNC_OK; -} - -/*********************************************************************//** - * @brief Set the value of EMC dynamic memory registers - * - * @param[in] par EMC register that will set value, should be: - * - EMC_DYN_MEM_REFRESH_TIMER: Dynamic Refresh register - * - EMC_DYN_MEM_READ_CONFIG: Dynamic Read Config register - * - EMC_DYN_MEM_TRP: Dynamic RP register - * - EMC_DYN_MEM_TRAS: Dynamic RAS register - * - EMC_DYN_MEM_TSREX: Dynamic SREX register - * - EMC_DYN_MEM_TAPR: Dynamic APR register - * - EMC_DYN_MEM_TDAL: Dynamic DAL register - * - EMC_DYN_MEM_TWR: Dynamic WR register - * - EMC_DYN_MEM_TRC: Dynamic RC register - * - EMC_DYN_MEM_TRFC: Dynamic RFC register - * - EMC_DYN_MEM_TXSR: Dynamic XSR register - * - EMC_DYN_MEM_TRRD: Dynamic RRD register - * - EMC_DYN_MEM_TMRD: Dynamic MRD register - * - * @return EMC_FUNC_OK/EMC_FUNC_INVALID_PARAM - **********************************************************************/ -EMC_FUNC_CODE EMC_SetDynMemoryParameter(EMC_DYN_MEM_PAR par, uint32_t val) -{ - switch ( par) - { - case EMC_DYN_MEM_REFRESH_TIMER: - LPC_EMC->DynamicRefresh = EMC_DynamicRefresh_REFRESH(val); - break; - - case EMC_DYN_MEM_READ_CONFIG: - LPC_EMC->DynamicReadConfig = EMC_DynamicReadConfig_RD(val); - break; - - case EMC_DYN_MEM_TRP: - LPC_EMC->DynamicRP = EMC_DynamictRP_tRP(val); - break; - - case EMC_DYN_MEM_TRAS: - LPC_EMC->DynamicRAS = EMC_DynamictRP_tRAS(val); - break; - - case EMC_DYN_MEM_TSREX: - LPC_EMC->DynamicSREX = EMC_DynamictRP_tSREX(val); - break; - - case EMC_DYN_MEM_TAPR: - LPC_EMC->DynamicAPR = EMC_DynamictAPR_tAPR(val); - break; - - case EMC_DYN_MEM_TDAL: - LPC_EMC->DynamicDAL =EMC_DynamictDAL_tDAL(val); - break; - - case EMC_DYN_MEM_TWR: - LPC_EMC->DynamicWR = EMC_DynamictWR_tWR(val); - break; - - case EMC_DYN_MEM_TRC: - LPC_EMC->DynamicRC = EMC_DynamictRC_tRC(val); - break; - - case EMC_DYN_MEM_TRFC: - LPC_EMC->DynamicRFC = EMC_DynamictRFC_tRFC(val); - break; - - case EMC_DYN_MEM_TXSR: - LPC_EMC->DynamicXSR = EMC_DynamictXSR_tXSR(val); - break; - - case EMC_DYN_MEM_TRRD: - LPC_EMC->DynamicRRD = EMC_DynamictRRD_tRRD(val); - break; - - case EMC_DYN_MEM_TMRD: - LPC_EMC->DynamicMRD = EMC_DynamictMRD_tMRD(val); - break; - default: - return EMC_FUNC_INVALID_PARAM; - } - return EMC_FUNC_OK; -} - -/*********************************************************************//** - * @brief Configure the memory device - * - * @param[in] index index number, should be from 0 to 3 - * - * @param[in] mem_dev Memory device, should be: - * - * - EMC_DYNAMIC_CFG_MEMDEV_SDRAM: SDRAM - * - * - EMC_DYNAMIC_CFG_MEMDEV_LOWPWR_SDRAM: Low-power SDRAM - * - * - * @return EMC_FUNC_OK/EMC_FUNC_INVALID_PARAM - **********************************************************************/ -EMC_FUNC_CODE EMC_DynMemConfigMD(uint32_t index , uint32_t mem_dev) -{ - switch (index) - { - case 0: - LPC_EMC->DynamicConfig0 &= ~EMC_DYNAMIC_CFG_MEMDEV_BMASK; - LPC_EMC->DynamicConfig0 |= mem_dev & EMC_DYNAMIC_CFG_MEMDEV_BMASK; - break; - - case 1: - LPC_EMC->DynamicConfig1 &= ~EMC_DYNAMIC_CFG_MEMDEV_BMASK; - LPC_EMC->DynamicConfig1 |= mem_dev & EMC_DYNAMIC_CFG_MEMDEV_BMASK; - break; - - case 2: - LPC_EMC->DynamicConfig2 &= ~EMC_DYNAMIC_CFG_MEMDEV_BMASK; - LPC_EMC->DynamicConfig2 |= mem_dev & EMC_DYNAMIC_CFG_MEMDEV_BMASK; - break; - - case 3: - LPC_EMC->DynamicConfig3 &= ~EMC_DYNAMIC_CFG_MEMDEV_BMASK; - LPC_EMC->DynamicConfig3 |= mem_dev & EMC_DYNAMIC_CFG_MEMDEV_BMASK; - break; - default: - return EMC_FUNC_INVALID_PARAM; - } - return EMC_FUNC_OK; -} - -/*********************************************************************//** - * @brief Map the address for the memory device - * - * @param[in] index index number, should be from 0 to 3 - * - * @param[in] add_mapped address where the memory will be mapped - * - * @return EMC_FUNC_OK - **********************************************************************/ -EMC_FUNC_CODE EMC_DynMemConfigAM(uint32_t index , - uint8_t addr_bus_width, uint8_t addr_map, - uint8_t data_bus_width, - uint16_t chip_size) -{ - const int chip_max_size = 512; // 512Mb - uint8_t data_bus_max_size = 0; - uint32_t add_mapped_p1 = 0x00, add_mapped_p2 = 0x00, add_mapped_p3 = 0x00; - uint32_t tmp = 16, i = 0, j = 0; - - /* Get part 3 of address map */ - switch(addr_bus_width) - { - case 16: - add_mapped_p3 = 0; - data_bus_max_size = 16; - break; - case 32: - add_mapped_p3 = 1; - data_bus_max_size = 32; - break; - default: - return EMC_FUNC_INVALID_PARAM; - } - - /* Get part 2 of address map */ - add_mapped_p2 = EMC_DYNAMIC_CFG_ADD_MAP_P2(addr_map); - - - /* Get part 1 of address map */ - if(chip_size == 16) - { - if(data_bus_width == 8) - add_mapped_p1 = 0; - else if(data_bus_width == 16) - add_mapped_p1 = 1; - else - return EMC_FUNC_INVALID_PARAM; - } - else - { - while(1) - { - i++; - tmp = 16*(0x01 << (i+1)); - if(tmp == chip_size) - { - for(j = 0; (8< data_bus_max_size) - return EMC_FUNC_INVALID_PARAM; - - add_mapped_p1 = (i<<2) + j; - break; - } - if(tmp >= chip_max_size) - { - return EMC_FUNC_INVALID_PARAM; - } - } - } - - switch ( index) - { - case 0: - LPC_EMC->DynamicConfig0 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P1_MASK; - LPC_EMC->DynamicConfig0 |= EMC_DYNAMIC_CFG_ADD_MAP_P1(add_mapped_p1); - LPC_EMC->DynamicConfig0 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P2_MASK; - LPC_EMC->DynamicConfig0 |= EMC_DYNAMIC_CFG_ADD_MAP_P2(add_mapped_p2); - LPC_EMC->DynamicConfig0 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P3_MASK; - LPC_EMC->DynamicConfig0 |= EMC_DYNAMIC_CFG_ADD_MAP_P3(add_mapped_p3); - break; - - case 1: - LPC_EMC->DynamicConfig1 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P1_MASK; - LPC_EMC->DynamicConfig1 |= EMC_DYNAMIC_CFG_ADD_MAP_P1(add_mapped_p1); - LPC_EMC->DynamicConfig1 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P2_MASK; - LPC_EMC->DynamicConfig1 |= EMC_DYNAMIC_CFG_ADD_MAP_P2(add_mapped_p2); - LPC_EMC->DynamicConfig1 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P3_MASK; - LPC_EMC->DynamicConfig1 |= EMC_DYNAMIC_CFG_ADD_MAP_P3(add_mapped_p3); - - break; - - case 2: - LPC_EMC->DynamicConfig2 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P1_MASK; - LPC_EMC->DynamicConfig2 |= EMC_DYNAMIC_CFG_ADD_MAP_P1(add_mapped_p1); - LPC_EMC->DynamicConfig2 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P2_MASK; - LPC_EMC->DynamicConfig2 |= EMC_DYNAMIC_CFG_ADD_MAP_P2( add_mapped_p2); - LPC_EMC->DynamicConfig2 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P3_MASK; - LPC_EMC->DynamicConfig2 |= EMC_DYNAMIC_CFG_ADD_MAP_P3(add_mapped_p3); - - break; - - case 3: - LPC_EMC->DynamicConfig3 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P1_MASK; - LPC_EMC->DynamicConfig3 |= EMC_DYNAMIC_CFG_ADD_MAP_P1(add_mapped_p1); - LPC_EMC->DynamicConfig3 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P2_MASK; - LPC_EMC->DynamicConfig3 |= EMC_DYNAMIC_CFG_ADD_MAP_P2(add_mapped_p2); - LPC_EMC->DynamicConfig3 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P3_MASK; - LPC_EMC->DynamicConfig3 |= EMC_DYNAMIC_CFG_ADD_MAP_P3(add_mapped_p3); - - break; - default: - return EMC_FUNC_INVALID_PARAM; - } - return EMC_FUNC_OK; -} - -/*********************************************************************//** - * @brief Enable/disable the buffer - * - * @param[in] index index number, should be from 0 to 3 - * - * @param[in] buff_control buffer control mode, should be: - * - * - EMC_DYNAMIC_CFG_BUFF_DISABLED: buffer is disabled - * - * - EMC_DYNAMIC_CFG_BUFF_ENABLED: buffer is enable - * - * @return EMC_FUNC_OK/EMC_FUNC_INVALID_PARAM - **********************************************************************/ -EMC_FUNC_CODE EMC_DynMemConfigB(uint32_t index , uint32_t buff_control) -{ - switch ( index) - { - case 0: - LPC_EMC->DynamicConfig0 &= ~EMC_DYNAMIC_CFG_BUFFENABLE_BMASK; - LPC_EMC->DynamicConfig0 |= buff_control & EMC_DYNAMIC_CFG_BUFFENABLE_BMASK; - break; - - case 1: - LPC_EMC->DynamicConfig1 &= ~EMC_DYNAMIC_CFG_BUFFENABLE_BMASK; - LPC_EMC->DynamicConfig1 |= buff_control& EMC_DYNAMIC_CFG_BUFFENABLE_BMASK; - break; - - case 2: - LPC_EMC->DynamicConfig2 &= ~EMC_DYNAMIC_CFG_BUFFENABLE_BMASK; - LPC_EMC->DynamicConfig2 |= buff_control& EMC_DYNAMIC_CFG_BUFFENABLE_BMASK; - break; - - case 3: - LPC_EMC->DynamicConfig3 &= ~EMC_DYNAMIC_CFG_BUFFENABLE_BMASK; - LPC_EMC->DynamicConfig3|= buff_control& EMC_DYNAMIC_CFG_BUFFENABLE_BMASK; - break; - default: - return EMC_FUNC_INVALID_PARAM; - } - return EMC_FUNC_OK; -} - - -/*********************************************************************//** - * @brief Configure write permission: protect or not - * - * @param[in] index index number, should be from 0 to 3 - * - * @param[in] permission permission mode, should be: - * - * - EMC_DYNAMIC_CFG_WR_UNPROTECTED: will not protect - * - * - EMC_DYNAMIC_CFG_WR_PROTECTED: will protect - * - * @return EMC_FUNC_OK - **********************************************************************/ -EMC_FUNC_CODE EMC_DynMemConfigP(uint32_t index , uint32_t permission) -{ - - switch ( index) - { - case 0: - LPC_EMC->DynamicConfig0 &= ~ EMC_DYNAMIC_CFG_WRPROTECT_BMASK; - LPC_EMC->DynamicConfig0 |= permission&EMC_DYNAMIC_CFG_WRPROTECT_BMASK; - break; - - case 1: - LPC_EMC->DynamicConfig1 &= ~ EMC_DYNAMIC_CFG_WRPROTECT_BMASK; - LPC_EMC->DynamicConfig1 |= permission&EMC_DYNAMIC_CFG_WRPROTECT_BMASK; - break; - - case 2: - LPC_EMC->DynamicConfig2 &= ~ EMC_DYNAMIC_CFG_WRPROTECT_BMASK; - LPC_EMC->DynamicConfig2 |= permission&EMC_DYNAMIC_CFG_WRPROTECT_BMASK; - break; - - case 3: - LPC_EMC->DynamicConfig3 &= ~ EMC_DYNAMIC_CFG_WRPROTECT_BMASK; - LPC_EMC->DynamicConfig3 |= permission&EMC_DYNAMIC_CFG_WRPROTECT_BMASK; - break; - default: - return EMC_FUNC_INVALID_PARAM; - } - return EMC_FUNC_OK; -} - -/*********************************************************************//** - * @brief Set value for RAS latency - * - * @param[in] index index number, should be from 0 to 3 - * - * @param[in] ras_val RAS value should be in range: 0..3 - * - * @return EMC_FUNC_OK - **********************************************************************/ -EMC_FUNC_CODE EMC_DynMemRAS(uint32_t index , uint32_t ras_val) -{ - switch ( index) - { - case 0: - LPC_EMC->DynamicRasCas0 &= ~EMC_DYNAMIC_RASCAS_RASCFG_BMASK; - LPC_EMC->DynamicRasCas0 |=( ras_val << EMC_DYNAMIC_RASCAS_RASCFG_POS) - &EMC_DYNAMIC_RASCAS_RASCFG_BMASK; - break; - - case 1: - LPC_EMC->DynamicRasCas1 &= ~EMC_DYNAMIC_RASCAS_RASCFG_BMASK; - LPC_EMC->DynamicRasCas1 |= ( ras_val << EMC_DYNAMIC_RASCAS_RASCFG_POS) - &EMC_DYNAMIC_RASCAS_RASCFG_BMASK; - break; - - case 2: - LPC_EMC->DynamicRasCas2 &= ~EMC_DYNAMIC_RASCAS_RASCFG_BMASK; - LPC_EMC->DynamicRasCas2 |= ( ras_val << EMC_DYNAMIC_RASCAS_RASCFG_POS) - &EMC_DYNAMIC_RASCAS_RASCFG_BMASK; - break; - - case 3: - LPC_EMC->DynamicRasCas3 &= ~EMC_DYNAMIC_RASCAS_RASCFG_BMASK; - LPC_EMC->DynamicRasCas3 |= ( ras_val << EMC_DYNAMIC_RASCAS_RASCFG_POS) - &EMC_DYNAMIC_RASCAS_RASCFG_BMASK; - break; - default: - return EMC_FUNC_INVALID_PARAM; - } - return EMC_FUNC_OK; -} - - -/*********************************************************************//** - * @brief Set value for CAS latency - * - * @param[in] index index number, should be from 0 to 3 - * - * @param[in] ras_val CAS value should be in range: 0..3 - * - * @return EMC_FUNC_OK/EMC_FUNC_INVALID_PARAM - **********************************************************************/ -EMC_FUNC_CODE EMC_DynMemCAS(uint32_t index , uint32_t cas_val) -{ - switch ( index) - { - case 0: - LPC_EMC->DynamicRasCas0 &= ~EMC_DYNAMIC_RASCAS_CASCFG_BMASK; - LPC_EMC->DynamicRasCas0 |= (cas_val<DynamicRasCas1 &= ~EMC_DYNAMIC_RASCAS_CASCFG_BMASK; - LPC_EMC->DynamicRasCas1 |= (cas_val<DynamicRasCas2 &= ~EMC_DYNAMIC_RASCAS_CASCFG_BMASK; - LPC_EMC->DynamicRasCas2 |= (cas_val<DynamicRasCas3 &= ~EMC_DYNAMIC_RASCAS_CASCFG_BMASK; - LPC_EMC->DynamicRasCas3 |= (cas_val<StaticExtendedWait = EMC_StaticExtendedWait_EXTENDEDWAIT(Extended_wait_time_out); - return EMC_FUNC_OK; -} - -/*********************************************************************//** - * @brief Configure the memory width - * - * @param[in] index index number, should be from 0 to 3 - * - * @param[in] mem_width memory width, should be: - * - * - EMC_STATIC_CFG_MW_8BITS: 8-bits - * - * - EMC_STATIC_CFG_MW_16BITS: 16-bits - * - * - EMC_STATIC_CFG_MW_32BITS02: 32-bits - * - * @return EMC_FUNC_OK/EMC_FUNC_INVALID_PARAM - **********************************************************************/ -EMC_FUNC_CODE EMC_StaMemConfigMW(uint32_t index , uint32_t mem_width) -{ - uint32_t mem_width_flg = 0; - switch(mem_width) - { - case 8: - mem_width_flg = EMC_STATIC_CFG_MW_8BITS; - break; - case 16: - mem_width_flg = EMC_STATIC_CFG_MW_16BITS; - break; - case 32: - mem_width_flg = EMC_STATIC_CFG_MW_32BITS; - break; - default: - return EMC_FUNC_INVALID_PARAM; - } - switch ( index) - { - case 0: - LPC_EMC->StaticConfig0 &= ~ EMC_STATIC_CFG_MEMWIDTH_BMASK; - LPC_EMC->StaticConfig0 |= mem_width_flg; - break; - - case 1: - LPC_EMC->StaticConfig1 &= ~ EMC_STATIC_CFG_MEMWIDTH_BMASK; - LPC_EMC->StaticConfig1 |= mem_width_flg; - break; - - case 2: - LPC_EMC->StaticConfig2 &= ~ EMC_STATIC_CFG_MEMWIDTH_BMASK; - LPC_EMC->StaticConfig2 |= mem_width_flg; - break; - - case 3: - LPC_EMC->StaticConfig3 &= ~ EMC_STATIC_CFG_MEMWIDTH_BMASK; - LPC_EMC->StaticConfig3 |= mem_width_flg; - break; - default: - return EMC_FUNC_INVALID_PARAM; - } - return EMC_FUNC_OK; -} -/*********************************************************************//** - * @brief Configure the page mode - * - * @param[in] index index number, should be from 0 to 3 - * - * @param[in] page_mode page mode, should be: - * - * - EMC_CFG_PM_DISABLE: disable - * - * - EMC_CFG_PM_ASYNC_ENABLE: asynchronous page mode enable - * - * @return EMC_FUNC_OK/EMC_FUNC_INVALID_PARAM - **********************************************************************/ -EMC_FUNC_CODE EMC_StaMemConfigPM(uint32_t index , uint32_t page_mode) -{ - switch ( index) - { - case 0: - LPC_EMC->StaticConfig0 &= ~EMC_STATIC_CFG_PAGEMODE_MASK; - LPC_EMC->StaticConfig0 |= page_mode&EMC_STATIC_CFG_PAGEMODE_MASK; - break; - - case 1: - LPC_EMC->StaticConfig1 &= ~EMC_STATIC_CFG_PAGEMODE_MASK; - LPC_EMC->StaticConfig1 |= page_mode&EMC_STATIC_CFG_PAGEMODE_MASK; - break; - - case 2: - LPC_EMC->StaticConfig2 &= ~EMC_STATIC_CFG_PAGEMODE_MASK; - LPC_EMC->StaticConfig2 |= page_mode&EMC_STATIC_CFG_PAGEMODE_MASK; - break; - - case 3: - LPC_EMC->StaticConfig3 &= ~EMC_STATIC_CFG_PAGEMODE_MASK; - LPC_EMC->StaticConfig3 |= page_mode&EMC_STATIC_CFG_PAGEMODE_MASK; - break; - default: - return EMC_FUNC_INVALID_PARAM; - } - return EMC_FUNC_OK; -} - - -/*********************************************************************//** - * @brief Configure the chip select polarity - * - * @param[in] index index number, should be from 0 to 3 - * - * @param[in] pagepol_val_mode page mode, should be: - * - * - EMC_CFG_BYTELAND_PC_ACTIVE_LO: Active LOW ship select - * - * - EMC_CFG_BYTELAND_PC_ACTIVE_HI: Active HIGH chip select - * - * @return EMC_FUNC_OK/EMC_FUNC_INVALID_PARAM - **********************************************************************/ -EMC_FUNC_CODE EMC_StaMemConfigPC(uint32_t index , uint32_t pol_val) -{ - switch ( index) - { - case 0: - LPC_EMC->StaticConfig0 &= ~EMC_STATIC_CFG_CHIPPOLARITY_MASK; - LPC_EMC->StaticConfig0 |= pol_val&EMC_STATIC_CFG_CHIPPOLARITY_MASK; - break; - - case 1: - LPC_EMC->StaticConfig1 &= ~EMC_STATIC_CFG_CHIPPOLARITY_MASK; - LPC_EMC->StaticConfig1 |= pol_val&EMC_STATIC_CFG_CHIPPOLARITY_MASK; - break; - - case 2: - LPC_EMC->StaticConfig2 &= ~EMC_STATIC_CFG_CHIPPOLARITY_MASK; - LPC_EMC->StaticConfig2 |= pol_val&EMC_STATIC_CFG_CHIPPOLARITY_MASK; - break; - - case 3: - LPC_EMC->StaticConfig3 &= ~EMC_STATIC_CFG_CHIPPOLARITY_MASK; - LPC_EMC->StaticConfig3 |= pol_val&EMC_STATIC_CFG_CHIPPOLARITY_MASK; - break; - default: - return EMC_FUNC_INVALID_PARAM; - } - return EMC_FUNC_OK; -} - - -/*********************************************************************//** - * @brief Configure the byte lane state - * - * @param[in] index index number, should be from 0 to 3 - * - * @param[in] pb_val Byte lane state, should be: - * - * - EMC_CFG_BYTELAND_READ_BITSHIGH: For reads all bits - * in BLSn[3:0] are HIGH. - * - * - EMC_CFG_BYTELAND_READ_BITSLOW: For reads all bits - * in BLSn[3:0] are LOW. - * - * @return EMC_FUNC_OK/EMC_FUNC_INVALID_PARAM - **********************************************************************/ -EMC_FUNC_CODE EMC_StaMemConfigPB(uint32_t index , uint32_t pb_val) -{ - switch ( index) - { - case 0: - LPC_EMC->StaticConfig0 &= ~EMC_STATIC_CFG_BYTELAND_MASK; - LPC_EMC->StaticConfig0 |= pb_val&EMC_STATIC_CFG_BYTELAND_MASK; - break; - - case 1: - LPC_EMC->StaticConfig1 &= ~EMC_STATIC_CFG_BYTELAND_MASK; - LPC_EMC->StaticConfig1 |= pb_val&EMC_STATIC_CFG_BYTELAND_MASK; - break; - - case 2: - LPC_EMC->StaticConfig2 &= ~EMC_STATIC_CFG_BYTELAND_MASK; - LPC_EMC->StaticConfig2 |= pb_val&EMC_STATIC_CFG_BYTELAND_MASK; - break; - - case 3: - LPC_EMC->StaticConfig3 &= ~EMC_STATIC_CFG_BYTELAND_MASK; - LPC_EMC->StaticConfig3 |= pb_val&EMC_STATIC_CFG_BYTELAND_MASK; - break; - default: - return EMC_FUNC_INVALID_PARAM; - } - return EMC_FUNC_OK; -} - -/*********************************************************************//** - * @brief Configure the extended wait value - * - * @param[in] index index number, should be from 0 to 3 - * - * @param[in] ex_wait Extended wait mode, should be: - * - * - EMC_CFG_EW_DISABLED: Extended wait disabled. - * - * - EMC_CFG_EW_ENABLED: Extended wait enabled. - * - * @return EMC_FUNC_OK/EMC_FUNC_INVALID_PARAM - **********************************************************************/ -EMC_FUNC_CODE EMC_StaMemConfigEW(uint32_t index , uint32_t ex_wait) -{ - switch ( index) - { - case 0: - LPC_EMC->StaticConfig0 &= ~EMC_STATIC_CFG_EXTWAIT_MASK; - LPC_EMC->StaticConfig0 |= ex_wait&EMC_STATIC_CFG_EXTWAIT_MASK; - break; - - case 1: - LPC_EMC->StaticConfig1 &= ~EMC_STATIC_CFG_EXTWAIT_MASK; - LPC_EMC->StaticConfig1 |= ex_wait&EMC_STATIC_CFG_EXTWAIT_MASK; - break; - - case 2: - LPC_EMC->StaticConfig2 &= ~EMC_STATIC_CFG_EXTWAIT_MASK; - LPC_EMC->StaticConfig2 |= ex_wait&EMC_STATIC_CFG_EXTWAIT_MASK; - break; - - case 3: - LPC_EMC->StaticConfig3 &= ~EMC_STATIC_CFG_EXTWAIT_MASK; - LPC_EMC->StaticConfig3 |= ex_wait&EMC_STATIC_CFG_EXTWAIT_MASK; - break; - default: - return EMC_FUNC_INVALID_PARAM; - } - return EMC_FUNC_OK; -} - -/*********************************************************************//** - * @brief Configure the buffer enable value - * - * @param[in] index index number, should be from 0 to 3 - * - * @param[in] buf_val Buffer mode, should be: - * - * - EMC_CFG_BUF_DISABLED: Buffer disabled. - * - * - EMC_CFG_BUF_ENABLED: Buffer enabled. - * - * @return EMC_FUNC_OK/EMC_FUNC_INVALID_PARAM - **********************************************************************/ -EMC_FUNC_CODE EMC_StaMemConfigB(uint32_t index , uint32_t buf_val) -{ - switch ( index) - { - case 0: - LPC_EMC->StaticConfig0 &= ~EMC_STATIC_CFG_BUFENABLE_MASK; - LPC_EMC->StaticConfig0 |= buf_val&EMC_STATIC_CFG_BUFENABLE_MASK; - break; - - case 1: - LPC_EMC->StaticConfig1 &= ~EMC_STATIC_CFG_BUFENABLE_MASK; - LPC_EMC->StaticConfig1 |= buf_val&EMC_STATIC_CFG_BUFENABLE_MASK; - break; - - case 2: - LPC_EMC->StaticConfig2 &= ~EMC_STATIC_CFG_BUFENABLE_MASK; - LPC_EMC->StaticConfig2 |= buf_val&EMC_STATIC_CFG_BUFENABLE_MASK; - break; - - case 3: - LPC_EMC->StaticConfig3 &= ~EMC_STATIC_CFG_BUFENABLE_MASK; - LPC_EMC->StaticConfig3 |= buf_val&EMC_STATIC_CFG_BUFENABLE_MASK; - break; - default: - return EMC_FUNC_INVALID_PARAM; - } - return EMC_FUNC_OK; -} - -/*********************************************************************//** - * @brief Configure the write permission - * - * @param[in] index index number, should be from 0 to 3 - * - * @param[in] per_val Permission mode, should be: - * - * - EMC_CFG_WRITEPROTECT_DISABLED: Write not protected. - * - * - EMC_CFG_WRITEPROTECT_ENABLED: Write protected. - * - * @return EMC_FUNC_OK/EMC_FUNC_INVALID_PARAM - **********************************************************************/ -EMC_FUNC_CODE EMC_StaMemConfigpP(uint32_t index , uint32_t per_val) -{ - switch ( index) - { - case 0: - LPC_EMC->StaticConfig0 &= ~EMC_STATIC_CFG_WRIEPROTECT_MASK; - LPC_EMC->StaticConfig0 |= per_val&EMC_STATIC_CFG_WRIEPROTECT_MASK; - break; - - case 1: - LPC_EMC->StaticConfig1 &= ~EMC_STATIC_CFG_WRIEPROTECT_MASK; - LPC_EMC->StaticConfig1 |= per_val&EMC_STATIC_CFG_WRIEPROTECT_MASK; - break; - - case 2: - LPC_EMC->StaticConfig2 &= ~EMC_STATIC_CFG_WRIEPROTECT_MASK; - LPC_EMC->StaticConfig2 |= per_val&EMC_STATIC_CFG_WRIEPROTECT_MASK; - break; - - case 3: - LPC_EMC->StaticConfig3 &= ~EMC_STATIC_CFG_WRIEPROTECT_MASK; - LPC_EMC->StaticConfig3 |= per_val&EMC_STATIC_CFG_WRIEPROTECT_MASK; - break; - default: - return EMC_FUNC_INVALID_PARAM; - } - return EMC_FUNC_OK; -} - -/*********************************************************************//** - * @brief Set the value of LPC_EMC static memory registers - * - * @param[in] index index number, should be from 0 to 3 - * - * @param[in] EMC_STA_MEM_PAR Static register, should be: - * - * - EMC_STA_MEM_WAITWEN: StaticWaitWen0 register - * - EMC_STA_MEM_WAITOEN: StaticWaitOen0 register - * - EMC_STA_MEM_WAITRD: StaticWaitRd0 register - * - EMC_STA_MEM_WAITPAGE: StaticWaitPage0 register - * - EMC_STA_MEM_WAITWR: StaticWaitWr0 register - * - EMC_STA_MEM_WAITTURN: StaticWaitTurn0 register - * - * @return EMC_FUNC_OK/EMC_FUNC_INVALID_PARAM - **********************************************************************/ -EMC_FUNC_CODE EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val) -{ - switch (index) - { - case 0: - switch ( par) - { - case EMC_STA_MEM_WAITWEN: - LPC_EMC->StaticWaitWen0 = EMC_StaticWaitWen_WAITWEN(val); - break; - - case EMC_STA_MEM_WAITOEN: - LPC_EMC->StaticWaitOen0 = EMC_StaticWaitOen_WAITOEN(val); - break; - - case EMC_STA_MEM_WAITRD: - LPC_EMC->StaticWaitRd0 = EMC_StaticWaitRd_WAITRD(val); - break; - - case EMC_STA_MEM_WAITPAGE: - LPC_EMC->StaticWaitPage0 = EMC_StaticwaitPage_WAITPAGE(val); - break; - - case EMC_STA_MEM_WAITWR: - LPC_EMC->StaticWaitWr0 = EMC_StaticWaitwr_WAITWR(val); - break; - - case EMC_STA_MEM_WAITTURN: - LPC_EMC->StaticWaitTurn0 =EMC_StaticWaitTurn_WAITTURN(val); - break; - default: - return EMC_FUNC_INVALID_PARAM; - } - break; - - case 1: - switch ( par) - { - case EMC_STA_MEM_WAITWEN: - LPC_EMC->StaticWaitWen1 = EMC_StaticWaitWen_WAITWEN(val); - break; - - case EMC_STA_MEM_WAITOEN: - LPC_EMC->StaticWaitOen1 = EMC_StaticWaitOen_WAITOEN(val); - break; - - case EMC_STA_MEM_WAITRD: - LPC_EMC->StaticWaitRd1 = EMC_StaticWaitRd_WAITRD(val); - break; - - case EMC_STA_MEM_WAITPAGE: - LPC_EMC->StaticWaitPage1 = EMC_StaticwaitPage_WAITPAGE(val); - break; - - case EMC_STA_MEM_WAITWR: - LPC_EMC->StaticWaitWr1 = EMC_StaticWaitwr_WAITWR(val); - break; - - case EMC_STA_MEM_WAITTURN: - LPC_EMC->StaticWaitTurn1 =EMC_StaticWaitTurn_WAITTURN(val); - break; - default: - return EMC_FUNC_INVALID_PARAM; - - } - break; - - case 2: - switch ( par) - { - case EMC_STA_MEM_WAITWEN: - LPC_EMC->StaticWaitWen2 = EMC_StaticWaitWen_WAITWEN(val); - break; - - case EMC_STA_MEM_WAITOEN: - LPC_EMC->StaticWaitOen2 = EMC_StaticWaitOen_WAITOEN(val); - break; - - case EMC_STA_MEM_WAITRD: - LPC_EMC->StaticWaitRd2 = EMC_StaticWaitRd_WAITRD(val); - break; - - case EMC_STA_MEM_WAITPAGE: - LPC_EMC->StaticWaitPage2 = EMC_StaticwaitPage_WAITPAGE(val); - break; - - case EMC_STA_MEM_WAITWR: - LPC_EMC->StaticWaitWr2 = EMC_StaticWaitwr_WAITWR(val); - break; - - case EMC_STA_MEM_WAITTURN: - LPC_EMC->StaticWaitTurn2 =EMC_StaticWaitTurn_WAITTURN(val); - break; - default: - return EMC_FUNC_INVALID_PARAM; - - } - break; - - case 3: - switch ( par) - { - case EMC_STA_MEM_WAITWEN: - LPC_EMC->StaticWaitWen3 = EMC_StaticWaitWen_WAITWEN(val); - break; - - case EMC_STA_MEM_WAITOEN: - LPC_EMC->StaticWaitOen3 = EMC_StaticWaitOen_WAITOEN(val); - break; - - case EMC_STA_MEM_WAITRD: - LPC_EMC->StaticWaitRd3 = EMC_StaticWaitRd_WAITRD(val); - break; - - case EMC_STA_MEM_WAITPAGE: - LPC_EMC->StaticWaitPage3 = EMC_StaticwaitPage_WAITPAGE(val); - break; - - case EMC_STA_MEM_WAITWR: - LPC_EMC->StaticWaitWr3 = EMC_StaticWaitwr_WAITWR(val); - break; - - case EMC_STA_MEM_WAITTURN: - LPC_EMC->StaticWaitTurn3 =EMC_StaticWaitTurn_WAITTURN(val); - break; - default: - return EMC_FUNC_INVALID_PARAM; - } - break; - } - return EMC_FUNC_OK; -} -/** - * @} - */ - - /** - * @} - */ -#endif /*_EMC*/ - - - - - - diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_exti.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_exti.c deleted file mode 100644 index 148267ee8ba..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_exti.c +++ /dev/null @@ -1,162 +0,0 @@ -/********************************************************************** -* $Id$ lpc_exti.c 2011-06-02 -*//** -* @file lpc_exti.c -* @brief Contains all functions support for External Interrupt -* firmware library on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup EXTI - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _EXTI - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_exti.h" - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup EXTI_Public_Functions - * @{ - */ - -/*********************************************************************//** - * @brief Initial for EXT - * - Set EXTINT, EXTMODE, EXTPOLAR registers to default value - * @param[in] None - * @return None - **********************************************************************/ -void EXTI_Init(void) -{ - LPC_SC->EXTINT = 0xF; - LPC_SC->EXTMODE = 0x0; - LPC_SC->EXTPOLAR = 0x0; -} - - -/*********************************************************************//** -* @brief Close EXT -* @param[in] None -* @return None -**********************************************************************/ -void EXTI_DeInit(void) -{ - ; -} - -/*********************************************************************//** - * @brief Configuration for EXT - * - Set EXTINT, EXTMODE, EXTPOLAR register - * @param[in] EXTICfg Pointer to a EXTI_InitTypeDef structure - * that contains the configuration information for the - * specified external interrupt - * @return None - **********************************************************************/ -void EXTI_Config(EXTI_InitTypeDef *EXTICfg) -{ - LPC_SC->EXTINT = 0x0; - EXTI_SetMode(EXTICfg->EXTI_Line, EXTICfg->EXTI_Mode); - EXTI_SetPolarity(EXTICfg->EXTI_Line, EXTICfg->EXTI_polarity); -} - -/*********************************************************************//** -* @brief Set mode for EXTI pin -* @param[in] EXTILine external interrupt line, should be: -* - EXTI_EINT0: external interrupt line 0 -* - EXTI_EINT1: external interrupt line 1 -* - EXTI_EINT2: external interrupt line 2 -* - EXTI_EINT3: external interrupt line 3 -* @param[in] mode external mode, should be: -* - EXTI_MODE_LEVEL_SENSITIVE -* - EXTI_MODE_EDGE_SENSITIVE -* @return None -*********************************************************************/ -void EXTI_SetMode(EXTI_LINE_ENUM EXTILine, EXTI_MODE_ENUM mode) -{ - if(mode == EXTI_MODE_EDGE_SENSITIVE) - { - LPC_SC->EXTMODE |= (1 << EXTILine); - } - else if(mode == EXTI_MODE_LEVEL_SENSITIVE) - { - LPC_SC->EXTMODE &= ~(1 << EXTILine); - } -} - -/*********************************************************************//** -* @brief Set polarity for EXTI pin -* @param[in] EXTILine external interrupt line, should be: -* - EXTI_EINT0: external interrupt line 0 -* - EXTI_EINT1: external interrupt line 1 -* - EXTI_EINT2: external interrupt line 2 -* - EXTI_EINT3: external interrupt line 3 -* @param[in] polarity external polarity value, should be: -* - EXTI_POLARITY_LOW_ACTIVE_OR_FALLING_EDGE -* - EXTI_POLARITY_LOW_ACTIVE_OR_FALLING_EDGE -* @return None -*********************************************************************/ -void EXTI_SetPolarity(EXTI_LINE_ENUM EXTILine, EXTI_POLARITY_ENUM polarity) -{ - if(polarity == EXTI_POLARITY_HIGH_ACTIVE_OR_RISING_EDGE) - { - LPC_SC->EXTPOLAR |= (1 << EXTILine); - } - else if(polarity == EXTI_POLARITY_LOW_ACTIVE_OR_FALLING_EDGE) - { - LPC_SC->EXTPOLAR &= ~(1 << EXTILine); - } -} - -/*********************************************************************//** -* @brief Clear External interrupt flag -* @param[in] EXTILine external interrupt line, should be: -* - EXTI_EINT0: external interrupt line 0 -* - EXTI_EINT1: external interrupt line 1 -* - EXTI_EINT2: external interrupt line 2 -* - EXTI_EINT3: external interrupt line 3 -* @return None -*********************************************************************/ -void EXTI_ClearEXTIFlag(EXTI_LINE_ENUM EXTILine) -{ - LPC_SC->EXTINT |= (1 << EXTILine); -} - -/** - * @} - */ -#endif /*_EXTI*/ -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_gpdma.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_gpdma.c deleted file mode 100644 index 8e8823d3ddd..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_gpdma.c +++ /dev/null @@ -1,453 +0,0 @@ -/********************************************************************** -* $Id$ lpc_gpdma.c 2011-06-02 -*//** -* @file lpc_gpdma.c -* @brief Contains all functions support for GPDMA firmware library -* on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup GPDMA - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _GPDMA - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_gpdma.h" -#include "lpc_clkpwr.h" - -/* Private Variables ---------------------------------------------------------- */ -/** @defgroup GPDMA_Private_Variables GPDMA Private Variables - * @{ - */ - -/** - * @brief Lookup Table of Connection Type matched with - * Peripheral Data (FIFO) register base address - */ -volatile const void *GPDMA_LUTPerAddr[] = { - 0, // Revered - (&LPC_MCI->FIFO), // SD Card - (&LPC_SSP0->DR), // SSP0 Tx - (&LPC_SSP0->DR), // SSP0 Rx - (&LPC_SSP1->DR), // SSP1 Tx - (&LPC_SSP1->DR), // SSP1 Rx - (&LPC_SSP2->DR), // SSP2 Tx - (&LPC_SSP2->DR), // SSP2 Rx - (&LPC_ADC->GDR), // ADC - (&LPC_DAC->CR), // DAC - (&LPC_UART0->/*RBTHDLR.*/THR), // UART0 Tx - (&LPC_UART0->/*RBTHDLR.*/RBR), // UART0 Rx - (&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx - (&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx - (&LPC_UART2->/*RBTHDLR.*/THR), // UART2 Tx - (&LPC_UART2->/*RBTHDLR.*/RBR), // UART2 Rx - (&LPC_TIM0->MR0), // MAT0.0 - (&LPC_TIM0->MR1), // MAT0.1 - (&LPC_TIM1->MR0), // MAT1.0 - (&LPC_TIM1->MR1), // MAT1.1 - (&LPC_TIM2->MR0), // MAT2.0 - (&LPC_TIM2->MR1), // MAT2.1 - (&LPC_I2S->TXFIFO), // I2S Tx - (&LPC_I2S->RXFIFO), // I2S Rx - 0, // Reverse - 0, // Reverse - (&LPC_UART3->/*RBTHDLR.*/THR), // UART3 Tx - (&LPC_UART3->/*RBTHDLR.*/RBR), // UART3 Rx - (&LPC_UART4->/*RBTHDLR.*/THR), // UART4 Tx - (&LPC_UART4->/*RBTHDLR.*/RBR), // UART4 Rx - (&LPC_TIM3->MR0), // MAT3.0 - (&LPC_TIM3->MR1), // MAT3.1 -}; - -/** - * @brief Lookup Table of GPDMA Channel Number matched with - * GPDMA channel pointer - */ -const LPC_GPDMACH_TypeDef *pGPDMACh[8] = { - LPC_GPDMACH0, // GPDMA Channel 0 - LPC_GPDMACH1, // GPDMA Channel 1 - LPC_GPDMACH2, // GPDMA Channel 2 - LPC_GPDMACH3, // GPDMA Channel 3 - LPC_GPDMACH4, // GPDMA Channel 4 - LPC_GPDMACH5, // GPDMA Channel 5 - LPC_GPDMACH6, // GPDMA Channel 6 - LPC_GPDMACH7, // GPDMA Channel 7 -}; -/** - * @brief Optimized Peripheral Source and Destination burst size - */ -const uint8_t GPDMA_LUTPerBurst[] = { - 0, // Reserved - GPDMA_BSIZE_8, // SD Card - GPDMA_BSIZE_4, // SSP0 Tx - GPDMA_BSIZE_4, // SSP0 Rx - GPDMA_BSIZE_4, // SSP1 Tx - GPDMA_BSIZE_4, // SSP1 Rx - GPDMA_BSIZE_4, // SSP2 Tx - GPDMA_BSIZE_4, // SSP2 Rx - GPDMA_BSIZE_1, // ADC - GPDMA_BSIZE_1, // DAC - GPDMA_BSIZE_1, // UART0 Tx - GPDMA_BSIZE_1, // UART0 Rx - GPDMA_BSIZE_1, // UART1 Tx - GPDMA_BSIZE_1, // UART1 Rx - GPDMA_BSIZE_1, // UART2 Tx - GPDMA_BSIZE_1, // UART2 Rx - GPDMA_BSIZE_1, // MAT0.0 - GPDMA_BSIZE_1, // MAT0.1 - GPDMA_BSIZE_1, // MAT1.0 - GPDMA_BSIZE_1, // MAT1.1 - GPDMA_BSIZE_1, // MAT2.0 - GPDMA_BSIZE_1, // MAT2.1 - GPDMA_BSIZE_32, // I2S channel 0 - GPDMA_BSIZE_32, // I2S channel 1 - 0, // Reserved - 0, // Reserved - GPDMA_BSIZE_1, // UART3 Tx - GPDMA_BSIZE_1, // UART3 Rx - GPDMA_BSIZE_1, // UART4 Tx - GPDMA_BSIZE_1, // UART4 Rx - GPDMA_BSIZE_1, // MAT3.0 - GPDMA_BSIZE_1, // MAT3.1 -}; -/** - * @brief Optimized Peripheral Source and Destination transfer width - */ -const uint8_t GPDMA_LUTPerWid[] = { - 0, // Reserved - GPDMA_WIDTH_WORD, // SD Card - GPDMA_WIDTH_BYTE, // SSP0 Tx - GPDMA_WIDTH_BYTE, // SSP0 Rx - GPDMA_WIDTH_BYTE, // SSP1 Tx - GPDMA_WIDTH_BYTE, // SSP1 Rx - GPDMA_WIDTH_BYTE, // SSP2 Tx - GPDMA_WIDTH_BYTE, // SSP2 Rx - GPDMA_WIDTH_WORD, // ADC - GPDMA_WIDTH_BYTE, // DAC - GPDMA_WIDTH_BYTE, // UART0 Tx - GPDMA_WIDTH_BYTE, // UART0 Rx - GPDMA_WIDTH_BYTE, // UART1 Tx - GPDMA_WIDTH_BYTE, // UART1 Rx - GPDMA_WIDTH_BYTE, // UART2 Tx - GPDMA_WIDTH_BYTE, // UART2 Rx - GPDMA_WIDTH_WORD, // MAT0.0 - GPDMA_WIDTH_WORD, // MAT0.1 - GPDMA_WIDTH_WORD, // MAT1.0 - GPDMA_WIDTH_WORD, // MAT1.1 - GPDMA_WIDTH_WORD, // MAT2.0 - GPDMA_WIDTH_WORD, // MAT2.1 - GPDMA_WIDTH_WORD, // I2S channel 0 - GPDMA_WIDTH_WORD, // I2S channel 1 - 0, // Reserved - 0, // Reserved - GPDMA_WIDTH_BYTE, // UART3 Tx - GPDMA_WIDTH_BYTE, // UART3 Rx - GPDMA_WIDTH_BYTE, // UART4 Tx - GPDMA_WIDTH_BYTE, // UART4 Rx - GPDMA_WIDTH_WORD, // MAT3.0 - GPDMA_WIDTH_WORD, // MAT3.1 -}; - -/** - * @} - */ - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup GPDMA_Public_Functions - * @{ - */ - -/********************************************************************//** - * @brief Initialize GPDMA controller - * @param None - * @return None - *********************************************************************/ -void GPDMA_Init(void) -{ - /* Enable GPDMA clock */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCGPDMA, ENABLE); - - // Reset all channel configuration register - LPC_GPDMACH0->CConfig = 0; - LPC_GPDMACH1->CConfig = 0; - LPC_GPDMACH2->CConfig = 0; - LPC_GPDMACH3->CConfig = 0; - LPC_GPDMACH4->CConfig = 0; - LPC_GPDMACH5->CConfig = 0; - LPC_GPDMACH6->CConfig = 0; - LPC_GPDMACH7->CConfig = 0; - - /* Clear all DMA interrupt and error flag */ - LPC_GPDMA->IntTCClear = 0xFF; - LPC_GPDMA->IntErrClr = 0xFF; -} - -/********************************************************************//** - * @brief Setup GPDMA channel peripheral according to the specified - * parameters in the GPDMAChannelConfig. - * @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type - * structure that contains the configuration - * information for the specified GPDMA channel peripheral. - * @return ERROR if selected channel is enabled before - * or SUCCESS if channel is configured successfully - *********************************************************************/ -Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig) -{ - LPC_GPDMACH_TypeDef *pDMAch; - uint32_t tmp1, tmp2; - - if (LPC_GPDMA->EnbldChns & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) { - // This channel is enabled, return ERROR, need to release this channel first - return ERROR; - } - - // Get Channel pointer - pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum]; - - // Reset the Interrupt status - LPC_GPDMA->IntTCClear = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum); - LPC_GPDMA->IntErrClr = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum); - - // Clear DMA configure - pDMAch->CControl = 0x00; - pDMAch->CConfig = 0x00; - - /* Assign Linker List Item value */ - pDMAch->CLLI = GPDMAChannelConfig->DMALLI; - - /* Set value to Channel Control Registers */ - switch (GPDMAChannelConfig->TransferType) - { - // Memory to memory - case GPDMA_TRANSFERTYPE_M2M: - // Assign physical source and destination address - pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr; - pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr; - pDMAch->CControl - = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \ - | GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \ - | GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \ - | GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \ - | GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \ - | GPDMA_DMACCxControl_SI \ - | GPDMA_DMACCxControl_DI \ - | GPDMA_DMACCxControl_I; - break; - // Memory to peripheral - case GPDMA_TRANSFERTYPE_M2P: - case GPDMA_TRANSFERTYPE_M2P_DEST_CTRL: - // Assign physical source - pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr; - // Assign peripheral destination address - pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn]; - pDMAch->CControl - = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \ - | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \ - | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \ - | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \ - | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \ - | GPDMA_DMACCxControl_SI \ - | GPDMA_DMACCxControl_I; - break; - // Peripheral to memory - case GPDMA_TRANSFERTYPE_P2M: - case GPDMA_TRANSFERTYPE_P2M_SRC_CTRL: - // Assign peripheral source address - pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn]; - // Assign memory destination address - pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr; - pDMAch->CControl - = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \ - | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \ - | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \ - | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \ - | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \ - | GPDMA_DMACCxControl_DI \ - | GPDMA_DMACCxControl_I; - break; - // Peripheral to peripheral - case GPDMA_TRANSFERTYPE_P2P: - // Assign peripheral source address - pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn]; - // Assign peripheral destination address - pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn]; - pDMAch->CControl = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \ - | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \ - | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \ - | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \ - | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \ - | GPDMA_DMACCxControl_I; - break; - // Do not support any more transfer type, return ERROR - default: - return ERROR; - } - - /* Re-Configure DMA Request Select for source peripheral */ - if((GPDMAChannelConfig->SrcConn != 8)&&(GPDMAChannelConfig->SrcConn != 9)) - { - if (GPDMAChannelConfig->SrcConn > 15) - { - LPC_SC->DMAREQSEL |= (1<<(GPDMAChannelConfig->SrcConn - 16)); - } else { - LPC_SC->DMAREQSEL &= ~(1<<(GPDMAChannelConfig->SrcConn)); - } - } - - /* Re-Configure DMA Request Select for Destination peripheral */ - if((GPDMAChannelConfig->DstConn != 8)&&(GPDMAChannelConfig->DstConn != 9)) - { - if (GPDMAChannelConfig->DstConn > 15) - { - LPC_SC->DMAREQSEL |= (1<<(GPDMAChannelConfig->DstConn - 16)); - } else { - LPC_SC->DMAREQSEL &= ~(1<<(GPDMAChannelConfig->DstConn)); - } - } - - /* Enable DMA channels, little endian */ - LPC_GPDMA->Config = GPDMA_DMACConfig_E; - while (!(LPC_GPDMA->Config & GPDMA_DMACConfig_E)); - - // Calculate absolute value for Connection number - tmp1 = GPDMAChannelConfig->SrcConn; - tmp1 = ((tmp1 > 15) ? (tmp1 - 16) : tmp1); - tmp2 = GPDMAChannelConfig->DstConn; - tmp2 = ((tmp2 > 15) ? (tmp2 - 16) : tmp2); - - // Configure DMA Channel, enable Error Counter and Terminate counter - pDMAch->CConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \ - | GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \ - | GPDMA_DMACCxConfig_SrcPeripheral(tmp1) \ - | GPDMA_DMACCxConfig_DestPeripheral(tmp2); - - return SUCCESS; -} - - -/*********************************************************************//** - * @brief Enable/Disable DMA channel - * @param[in] channelNum GPDMA channel, should be in range from 0 to 7 - * @param[in] NewState New State of this command, should be: - * - ENABLE. - * - DISABLE. - * @return None - **********************************************************************/ -void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState) -{ - LPC_GPDMACH_TypeDef *pDMAch; - - // Get Channel pointer - pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[channelNum]; - - if (NewState == ENABLE) { - pDMAch->CConfig |= GPDMA_DMACCxConfig_E; - } else { - pDMAch->CConfig &= ~GPDMA_DMACCxConfig_E; - } -} -/*********************************************************************//** - * @brief Check if corresponding channel does have an active interrupt - * request or not - * @param[in] type type of status, should be: - * - GPDMA_STAT_INT: GPDMA Interrupt Status - * - GPDMA_STAT_INTTC: GPDMA Interrupt Terminal Count Request Status - * - GPDMA_STAT_INTERR: GPDMA Interrupt Error Status - * - GPDMA_STAT_RAWINTTC: GPDMA Raw Interrupt Terminal Count Status - * - GPDMA_STAT_RAWINTERR: GPDMA Raw Error Interrupt Status - * - GPDMA_STAT_ENABLED_CH:GPDMA Enabled Channel Status - * @param[in] channel GPDMA channel, should be in range from 0 to 7 - * @return IntStatus status of DMA channel interrupt after masking - * Should be: - * - SET: the corresponding channel has no active interrupt request - * - RESET: the corresponding channel does have an active interrupt request - **********************************************************************/ -IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel) -{ - switch (type) - { - case GPDMA_STAT_INT: //check status of DMA channel interrupts - if (LPC_GPDMA->IntStat & (GPDMA_DMACIntStat_Ch(channel))) - return SET; - return RESET; - case GPDMA_STAT_INTTC: // check terminal count interrupt request status for DMA - if (LPC_GPDMA->IntTCStat & GPDMA_DMACIntTCStat_Ch(channel)) - return SET; - return RESET; - case GPDMA_STAT_INTERR: //check interrupt status for DMA channels - if (LPC_GPDMA->IntErrStat & GPDMA_DMACIntTCClear_Ch(channel)) - return SET; - return RESET; - case GPDMA_STAT_RAWINTTC: //check status of the terminal count interrupt for DMA channels - if (LPC_GPDMA->RawIntErrStat & GPDMA_DMACRawIntTCStat_Ch(channel)) - return SET; - return RESET; - case GPDMA_STAT_RAWINTERR: //check status of the error interrupt for DMA channels - if (LPC_GPDMA->RawIntTCStat & GPDMA_DMACRawIntErrStat_Ch(channel)) - return SET; - return RESET; - default: //check enable status for DMA channels - if (LPC_GPDMA->EnbldChns & GPDMA_DMACEnbldChns_Ch(channel)) - return SET; - return RESET; - } -} - -/*********************************************************************//** - * @brief Clear one or more interrupt requests on DMA channels - * @param[in] type type of interrupt request, should be: - * - GPDMA_STATCLR_INTTC: GPDMA Interrupt Terminal Count Request Clear - * - GPDMA_STATCLR_INTERR: GPDMA Interrupt Error Clear - * @param[in] channel GPDMA channel, should be in range from 0 to 7 - * @return None - **********************************************************************/ -void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel) -{ - if (type == GPDMA_STATCLR_INTTC) // clears the terminal count interrupt request on DMA channel - LPC_GPDMA->IntTCClear = GPDMA_DMACIntTCClear_Ch(channel); - else // clear the error interrupt request - LPC_GPDMA->IntErrClr = GPDMA_DMACIntErrClr_Ch(channel); -} - -/** - * @} - */ - -#endif /* _GPDMA */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_gpio.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_gpio.c deleted file mode 100644 index 84440f69779..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_gpio.c +++ /dev/null @@ -1,905 +0,0 @@ -/********************************************************************** -* $Id$ lpc_gpio.c 2011-06-02 -*//** -* @file lpc_gpio.c -* @brief Contains all functions support for GPIO firmware library -* on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup GPIO - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _GPIO - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_gpio.h" -#include "lpc_clkpwr.h" - -/* definitions ------------------------------------------------------------------- */ -#define GPIO_IS_ENABLED(x) (((x) != 0)? ENABLE:DISABLE) - -/* Private Functions ---------------------------------------------------------- */ - -static LPC_GPIO_TypeDef *GPIO_GetPointer(uint8_t portNum); -static GPIO_HalfWord_TypeDef *FIO_HalfWordGetPointer(uint8_t portNum); -static GPIO_Byte_TypeDef *FIO_ByteGetPointer(uint8_t portNum); - -/*********************************************************************//** - * @brief Get pointer to GPIO peripheral due to GPIO port - * @param[in] portNum Port Number value, should be in range from 0 to 4. - * @return Pointer to GPIO peripheral - **********************************************************************/ -static LPC_GPIO_TypeDef *GPIO_GetPointer(uint8_t portNum) -{ - LPC_GPIO_TypeDef *pGPIO = NULL; - - switch (portNum) - { - case 0: - pGPIO = LPC_GPIO0; - break; - - case 1: - pGPIO = LPC_GPIO1; - break; - - case 2: - pGPIO = LPC_GPIO2; - break; - - case 3: - pGPIO = LPC_GPIO3; - break; - - case 4: - pGPIO = LPC_GPIO4; - break; - - case 5: - pGPIO = LPC_GPIO5; - break; - - default: - break; - } - - return pGPIO; -} - -/*********************************************************************//** - * @brief Get pointer to FIO peripheral in halfword accessible style - * due to FIO port - * @param[in] portNum Port Number value, should be in range from 0 to 4. - * @return Pointer to FIO peripheral - **********************************************************************/ -static GPIO_HalfWord_TypeDef *FIO_HalfWordGetPointer(uint8_t portNum) -{ - GPIO_HalfWord_TypeDef *pFIO = NULL; - - switch (portNum) - { - case 0: - pFIO = GPIO0_HalfWord; - break; - - case 1: - pFIO = GPIO1_HalfWord; - break; - - case 2: - pFIO = GPIO2_HalfWord; - break; - - case 3: - pFIO = GPIO3_HalfWord; - break; - - case 4: - pFIO = GPIO4_HalfWord; - break; - - case 5: - pFIO = GPIO5_HalfWord; - break; - - default: - break; - } - - return pFIO; -} - -/*********************************************************************//** - * @brief Get pointer to FIO peripheral in byte accessible style - * due to FIO port - * @param[in] portNum Port Number value, should be in range from 0 to 4. - * @return Pointer to FIO peripheral - **********************************************************************/ -static GPIO_Byte_TypeDef *FIO_ByteGetPointer(uint8_t portNum) -{ - GPIO_Byte_TypeDef *pFIO = NULL; - - switch (portNum) - { - case 0: - pFIO = GPIO0_Byte; - break; - - case 1: - pFIO = GPIO1_Byte; - break; - - case 2: - pFIO = GPIO2_Byte; - break; - - case 3: - pFIO = GPIO3_Byte; - break; - - case 4: - pFIO = GPIO4_Byte; - break; - - case 5: - pFIO = GPIO5_Byte; - break; - - default: - break; - } - - return pFIO; -} - -/* End of Private Functions --------------------------------------------------- */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup GPIO_Public_Functions - * @{ - */ - - -/* GPIO ------------------------------------------------------------------------------ */ - -/*********************************************************************//** - * @brief Initialize the GPIO component by power on the clock - * supplied to it. - * @return None - * - * Note: - **********************************************************************/ -void GPIO_Init(void) -{ - CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCGPIO, ENABLE); - - return; -} - - -/*********************************************************************//** - * @brief De-initialize the GPIO component by power off the clock - * supplied to it. - * @return None - * - * Note: - **********************************************************************/ -void GPIO_Deinit(void) -{ - CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCGPIO, DISABLE); - - return; -} - - -/*********************************************************************//** - * @brief Set Direction for GPIO port. - * @param[in] portNum Port Number value, should be in range from 0 to 4 - * @param[in] bitValue Value that contains all bits to set direction, - * in range from 0 to 0xFFFFFFFF. - * example: value 0x5 to set direction for bit 0 and bit 1. - * @param[in] dir Direction value, should be: - * - 0: Input. - * - 1: Output. - * @return None - * - * Note: All remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - **********************************************************************/ -void GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir) -{ - LPC_GPIO_TypeDef *pGPIO = GPIO_GetPointer(portNum); - - if (pGPIO != NULL) - { - // Enable Output - if (dir) - { - pGPIO->DIR |= bitValue; - } - // Enable Input - else - { - pGPIO->DIR &= ~bitValue; - } - } -} - - -/*********************************************************************//** - * @brief Set Value for bits that have output direction on GPIO port. - * @param[in] portNum Port number value, should be in range from 0 to 4 - * @param[in] bitValue Value that contains all bits on GPIO to set, - * in range from 0 to 0xFFFFFFFF. - * example: value 0x5 to set bit 0 and bit 1. - * @return None - * - * Note: - * - For all bits that has been set as input direction, this function will - * not effect. - * - For all remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - **********************************************************************/ -void GPIO_SetValue(uint8_t portNum, uint32_t bitValue) -{ - LPC_GPIO_TypeDef *pGPIO = GPIO_GetPointer(portNum); - - if (pGPIO != NULL) - { - pGPIO->SET = bitValue; - } -} - -/*********************************************************************//** - * @brief Clear Value for bits that have output direction on GPIO port. - * @param[in] portNum Port number value, should be in range from 0 to 4 - * @param[in] bitValue Value that contains all bits on GPIO to clear, - * in range from 0 to 0xFFFFFFFF. - * example: value 0x5 to clear bit 0 and bit 1. - * @return None - * - * Note: - * - For all bits that has been set as input direction, this function will - * not effect. - * - For all remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - **********************************************************************/ -void GPIO_ClearValue(uint8_t portNum, uint32_t bitValue) -{ - LPC_GPIO_TypeDef *pGPIO = GPIO_GetPointer(portNum); - - if (pGPIO != NULL) - { - pGPIO->CLR = bitValue; - } -} - -/*********************************************************************//** - * @brief Output to the GPIO pin an expected value - * @param[in] portNum Port number value, should be in range from 0 to 4 - * @param[in] bitValue Value that contains all bits on GPIO to clear, - * in range from 0 to 0xFFFFFFFF. - * example: value 0x5 to clear bit 0 and bit 1. - * @return None - * - * Note: - * - For all bits that has been set as input direction, this function will - * not effect. - * - For all remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - **********************************************************************/ -void GPIO_OutputValue(uint8_t portNum, uint32_t bitMask, uint8_t value) -{ - if (value == 0) - { - GPIO_ClearValue(portNum, bitMask); - } - else - { - GPIO_SetValue(portNum, bitMask); - } - -} - - -/*********************************************************************//** - * @brief Read Current state on port pin that have input direction of GPIO - * @param[in] portNum Port number to read value, in range from 0 to 4 - * @return Current value of GPIO port. - * - * Note: Return value contain state of each port pin (bit) on that GPIO regardless - * its direction is input or output. - **********************************************************************/ -uint32_t GPIO_ReadValue(uint8_t portNum) -{ - LPC_GPIO_TypeDef *pGPIO = GPIO_GetPointer(portNum); - - if (pGPIO != NULL) - { - return pGPIO->PIN; - } - - return (0); -} - -/*********************************************************************//** - * @brief Enable GPIO interrupt (just used for P0.0-P0.30, P2.0-P2.13) - * @param[in] portNum Port number to read value, should be: 0 or 2 - * @param[in] bitValue Value that contains all bits on GPIO to enable, - * in range from 0 to 0xFFFFFFFF. - * @param[in] edgeState state of edge, should be: - * - 0: Rising edge - * - 1: Falling edge - * @return None - **********************************************************************/ -void GPIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState) -{ - if((portNum == 0)&&(edgeState == 0)) - LPC_GPIOINT->IO0IntEnR = bitValue; - else if ((portNum == 2)&&(edgeState == 0)) - LPC_GPIOINT->IO2IntEnR = bitValue; - else if ((portNum == 0)&&(edgeState == 1)) - LPC_GPIOINT->IO0IntEnF = bitValue; - else if ((portNum == 2)&&(edgeState == 1)) - LPC_GPIOINT->IO2IntEnF = bitValue; - else - //Error - while(1); -} - -/*********************************************************************//** - * @brief Get GPIO Interrupt Status (just used for P0.0-P0.30, P2.0-P2.13) - * @param[in] portNum Port number to read value, should be: 0 or 2 - * @param[in] pinNum Pin number, should be: 0..30(with port 0) and 0..13 - * (with port 2) - * @param[in] edgeState state of edge, should be: - * - 0: Rising edge - * - 1: Falling edge - * @return Bool could be: - * - ENABLE: Interrupt has been generated due to a rising - * edge on P0.0 - * - DISABLE: A rising edge has not been detected on P0.0 - **********************************************************************/ -FunctionalState GPIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState) -{ - if((portNum == 0) && (edgeState == 0))//Rising Edge - return GPIO_IS_ENABLED(((LPC_GPIOINT->IO0IntStatR)>>pinNum)& 0x1); - else if ((portNum == 2) && (edgeState == 0)) - return GPIO_IS_ENABLED(((LPC_GPIOINT->IO2IntStatR)>>pinNum)& 0x1); - else if ((portNum == 0) && (edgeState == 1))//Falling Edge - return GPIO_IS_ENABLED(((LPC_GPIOINT->IO0IntStatF)>>pinNum)& 0x1); - else if ((portNum == 2) && (edgeState == 1)) - return GPIO_IS_ENABLED(((LPC_GPIOINT->IO2IntStatF)>>pinNum)& 0x1); - else - //Error - while(1); -} -/*********************************************************************//** - * @brief Clear GPIO interrupt (just used for P0.0-P0.30, P2.0-P2.13) - * @param[in] portNum Port number to read value, should be: 0 or 2 - * @param[in] bitValue Value that contains all bits on GPIO to enable, - * in range from 0 to 0xFFFFFFFF. - * @return None - **********************************************************************/ -void GPIO_ClearInt(uint8_t portNum, uint32_t bitValue) -{ - if(portNum == 0) - LPC_GPIOINT->IO0IntClr = bitValue; - else if (portNum == 2) - LPC_GPIOINT->IO2IntClr = bitValue; - else - //Invalid portNum - while(1); -} - -/* FIO word accessible ----------------------------------------------------------------- */ -/* Stub function for FIO (word-accessible) style */ - -/** - * @brief The same with GPIO_SetDir() - */ -void FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir) -{ - GPIO_SetDir(portNum, bitValue, dir); -} - -/** - * @brief The same with GPIO_SetValue() - */ -void FIO_SetValue(uint8_t portNum, uint32_t bitValue) -{ - GPIO_SetValue(portNum, bitValue); -} - -/** - * @brief The same with GPIO_ClearValue() - */ -void FIO_ClearValue(uint8_t portNum, uint32_t bitValue) -{ - GPIO_ClearValue(portNum, bitValue); -} - -/** - * @brief The same with GPIO_ReadValue() - */ -uint32_t FIO_ReadValue(uint8_t portNum) -{ - return (GPIO_ReadValue(portNum)); -} - -/** - * @brief The same with GPIO_IntCmd() - */ -void FIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState) -{ - GPIO_IntCmd(portNum, bitValue, edgeState); -} - -/** - * @brief The same with GPIO_GetIntStatus() - */ -FunctionalState FIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState) -{ - return (GPIO_GetIntStatus(portNum, pinNum, edgeState)); -} - -/** - * @brief The same with GPIO_ClearInt() - */ -void FIO_ClearInt(uint8_t portNum, uint32_t bitValue) -{ - GPIO_ClearInt(portNum, bitValue); -} -/*********************************************************************//** - * @brief Set mask value for bits in FIO port - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] bitValue Value that contains all bits in to set, - * in range from 0 to 0xFFFFFFFF. - * @param[in] maskValue Mask value contains state value for each bit: - * - 0: not mask. - * - 1: mask. - * @return None - * - * Note: - * - All remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - * - After executing this function, in mask register, value '0' on each bit - * enables an access to the corresponding physical pin via a read or write access, - * while value '1' on bit (masked) that corresponding pin will not be changed - * with write access and if read, will not be reflected in the updated pin. - **********************************************************************/ -void FIO_SetMask(uint8_t portNum, uint32_t bitValue, uint8_t maskValue) -{ - LPC_GPIO_TypeDef *pFIO = GPIO_GetPointer(portNum); - - if(pFIO != NULL) - { - // Mask - if (maskValue) - { - pFIO->MASK |= bitValue; - } - // Un-mask - else - { - pFIO->MASK &= ~bitValue; - } - } -} - - -/* FIO halfword accessible ------------------------------------------------------------- */ - -/*********************************************************************//** - * @brief Set direction for FIO port in halfword accessible style - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper) - * @param[in] bitValue Value that contains all bits in to set direction, - * in range from 0 to 0xFFFF. - * @param[in] dir Direction value, should be: - * - 0: Input. - * - 1: Output. - * @return None - * - * Note: All remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - **********************************************************************/ -void FIO_HalfWordSetDir(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t dir) -{ - GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum); - - if(pFIO != NULL) - { - // Output direction - if (dir) - { - // Upper - if(halfwordNum) - { - pFIO->FIODIRU |= bitValue; - } - // lower - else - { - pFIO->FIODIRL |= bitValue; - } - } - // Input direction - else - { - // Upper - if(halfwordNum) - { - pFIO->FIODIRU &= ~bitValue; - } - // lower - else - { - pFIO->FIODIRL &= ~bitValue; - } - } - } -} - - -/*********************************************************************//** - * @brief Set mask value for bits in FIO port in halfword accessible style - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper) - * @param[in] bitValue Value that contains all bits in to set, - * in range from 0 to 0xFFFF. - * @param[in] maskValue Mask value contains state value for each bit: - * - 0: not mask. - * - 1: mask. - * @return None - * - * Note: - * - All remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - * - After executing this function, in mask register, value '0' on each bit - * enables an access to the corresponding physical pin via a read or write access, - * while value '1' on bit (masked) that corresponding pin will not be changed - * with write access and if read, will not be reflected in the updated pin. - **********************************************************************/ -void FIO_HalfWordSetMask(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t maskValue) -{ - GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum); - - if(pFIO != NULL) - { - // Mask - if (maskValue) - { - // Upper - if(halfwordNum) - { - pFIO->FIOMASKU |= bitValue; - } - // lower - else - { - pFIO->FIOMASKL |= bitValue; - } - } - // Un-mask - else - { - // Upper - if(halfwordNum) - { - pFIO->FIOMASKU &= ~bitValue; - } - // lower - else - { - pFIO->FIOMASKL &= ~bitValue; - } - } - } -} - - -/*********************************************************************//** - * @brief Set bits for FIO port in halfword accessible style - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper) - * @param[in] bitValue Value that contains all bits in to set, - * in range from 0 to 0xFFFF. - * @return None - * - * Note: - * - For all bits that has been set as input direction, this function will - * not effect. - * - For all remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - **********************************************************************/ -void FIO_HalfWordSetValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue) -{ - GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum); - - if(pFIO != NULL) - { - // Upper - if(halfwordNum) - { - pFIO->FIOSETU = bitValue; - } - // lower - else - { - pFIO->FIOSETL = bitValue; - } - } -} - - -/*********************************************************************//** - * @brief Clear bits for FIO port in halfword accessible style - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper) - * @param[in] bitValue Value that contains all bits in to clear, - * in range from 0 to 0xFFFF. - * @return None - * - * Note: - * - For all bits that has been set as input direction, this function will - * not effect. - * - For all remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - **********************************************************************/ -void FIO_HalfWordClearValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue) -{ - GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum); - - if(pFIO != NULL) - { - // Upper - if(halfwordNum) - { - pFIO->FIOCLRU = bitValue; - } - // lower - else - { - pFIO->FIOCLRL = bitValue; - } - } -} - - -/*********************************************************************//** - * @brief Read Current state on port pin that have input direction of GPIO - * in halfword accessible style. - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper) - * @return Current value of FIO port pin of specified halfword. - * Note: Return value contain state of each port pin (bit) on that FIO regardless - * its direction is input or output. - **********************************************************************/ -uint16_t FIO_HalfWordReadValue(uint8_t portNum, uint8_t halfwordNum) -{ - GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum); - - if(pFIO != NULL) - { - // Upper - if(halfwordNum) - { - return (pFIO->FIOPINU); - } - // lower - else - { - return (pFIO->FIOPINL); - } - } - - return (0); -} - - -/* FIO Byte accessible ------------------------------------------------------------ */ - -/*********************************************************************//** - * @brief Set direction for FIO port in byte accessible style - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] byteNum Byte part number, should be in range from 0 to 3 - * @param[in] bitValue Value that contains all bits in to set direction, - * in range from 0 to 0xFF. - * @param[in] dir Direction value, should be: - * - 0: Input. - * - 1: Output. - * @return None - * - * Note: All remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - **********************************************************************/ -void FIO_ByteSetDir(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t dir) -{ - GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum); - - if(pFIO != NULL) - { - // Output direction - if (dir) - { - if (byteNum <= 3) - { - pFIO->FIODIR[byteNum] |= bitValue; - } - } - // Input direction - else - { - if (byteNum <= 3) - { - pFIO->FIODIR[byteNum] &= ~bitValue; - } - } - } -} - -/*********************************************************************//** - * @brief Set mask value for bits in FIO port in byte accessible style - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] byteNum Byte part number, should be in range from 0 to 3 - * @param[in] bitValue Value that contains all bits in to set mask, - * in range from 0 to 0xFF. - * @param[in] maskValue Mask value contains state value for each bit: - * - 0: not mask. - * - 1: mask. - * @return None - * - * Note: - * - All remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - * - After executing this function, in mask register, value '0' on each bit - * enables an access to the corresponding physical pin via a read or write access, - * while value '1' on bit (masked) that corresponding pin will not be changed - * with write access and if read, will not be reflected in the updated pin. - **********************************************************************/ -void FIO_ByteSetMask(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t maskValue) -{ - GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum); - - if(pFIO != NULL) - { - // Mask - if (maskValue) - { - if (byteNum <= 3) - { - pFIO->FIOMASK[byteNum] |= bitValue; - } - } - // Un-mask - else { - if (byteNum <= 3) - { - pFIO->FIOMASK[byteNum] &= ~bitValue; - } - } - } -} - - -/*********************************************************************//** - * @brief Set bits for FIO port in byte accessible style - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] byteNum Byte part number, should be in range from 0 to 3 - * @param[in] bitValue Value that contains all bits in to set, - * in range from 0 to 0xFF. - * @return None - * - * Note: - * - For all bits that has been set as input direction, this function will - * not effect. - * - For all remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - **********************************************************************/ -void FIO_ByteSetValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue) -{ - GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum); - - if (pFIO != NULL) { - if (byteNum <= 3) - { - pFIO->FIOSET[byteNum] = bitValue; - } - } -} - - -/*********************************************************************//** - * @brief Clear bits for FIO port in byte accessible style - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] byteNum Byte part number, should be in range from 0 to 3 - * @param[in] bitValue Value that contains all bits in to clear, - * in range from 0 to 0xFF. - * @return None - * - * Note: - * - For all bits that has been set as input direction, this function will - * not effect. - * - For all remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - **********************************************************************/ -void FIO_ByteClearValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue) -{ - GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum); - - if (pFIO != NULL) - { - if (byteNum <= 3) - { - pFIO->FIOCLR[byteNum] = bitValue; - } - } -} - - -/*********************************************************************//** - * @brief Read Current state on port pin that have input direction of GPIO - * in byte accessible style. - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] byteNum Byte part number, should be in range from 0 to 3 - * @return Current value of FIO port pin of specified byte part. - * Note: Return value contain state of each port pin (bit) on that FIO regardless - * its direction is input or output. - **********************************************************************/ -uint8_t FIO_ByteReadValue(uint8_t portNum, uint8_t byteNum) -{ - GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum); - - if (pFIO != NULL) - { - if (byteNum <= 3) - { - return (pFIO->FIOPIN[byteNum]); - } - } - return (0); -} - -/** - * @} - */ - -#endif /* _GPIO */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_i2c.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_i2c.c deleted file mode 100644 index c466cf655e4..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_i2c.c +++ /dev/null @@ -1,1416 +0,0 @@ -/********************************************************************** -* $Id$ lpc_i2c.c 2011-06-02 -*//** -* @file lpc_i2c.c -* @brief Contains all functions support for I2C firmware library -* on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup I2C - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _I2C - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_i2c.h" -#include "lpc_clkpwr.h" -#include "lpc_pinsel.h" - -/* Private Types -------------------------------------------------------------- */ -/** @defgroup I2C_Private_Types I2C Private Types - * @{ - */ - -/** - * @brief I2C device configuration structure type - */ -typedef struct -{ - uint32_t txrx_setup; /* Transmission setup */ - int32_t dir; /* Current direction phase, 0 - write, 1 - read */ -} I2C_CFG_T; - -/** - * @} - */ - -/* Private Variables ---------------------------------------------------------- */ -/** - * @brief II2C driver data for I2C0, I2C1 and I2C2 - */ -static I2C_CFG_T i2cdat[3]; - -static uint32_t I2C_MasterComplete[3]; -static uint32_t I2C_SlaveComplete[3]; - -static uint32_t I2C_MonitorBufferIndex; - -/* Private Functions ---------------------------------------------------------- */ - -/* Get pointer to expected I2C */ -static LPC_I2C_TypeDef* I2C_GetPointer(en_I2C_unitId compId); - -/* Generate a start condition on I2C bus (in master mode only) */ -static uint32_t I2C_Start (LPC_I2C_TypeDef *I2Cx, I2C_TRANSFER_OPT_Type Opt); - -/* Generate a stop condition on I2C bus (in master mode only) */ -static void I2C_Stop (LPC_I2C_TypeDef *I2Cx, I2C_TRANSFER_OPT_Type Opt); - -/* I2C send byte subroutine */ -static uint32_t I2C_SendByte (LPC_I2C_TypeDef *I2Cx, uint8_t databyte); - -/* I2C get byte subroutine */ -static uint32_t I2C_GetByte (LPC_I2C_TypeDef *I2Cx, uint8_t *retdat, Bool ack); - -/* I2C set clock (hz) */ -static void I2C_SetClock (LPC_I2C_TypeDef *I2Cx, uint32_t target_clock); - -/*--------------------------------------------------------------------------------*/ - -/********************************************************************//** - * @brief Convert from I2C peripheral to number - * @param[in] I2Cx: I2C peripheral selected, should be: - * - LPC_I2C0 - * - LPC_I2C1 - * - LPC_I2C2 - * @return I2C number, could be: 0..2 - *********************************************************************/ -static LPC_I2C_TypeDef* I2C_GetPointer(en_I2C_unitId compId) -{ - LPC_I2C_TypeDef* pI2C; - - switch (compId) - { - case I2C_0: - pI2C = LPC_I2C0; - break; - - case I2C_1: - pI2C = LPC_I2C1; - break; - - case I2C_2: - pI2C = LPC_I2C2; - break; - - default: - pI2C = NULL; - break; - } - - return pI2C; -} - - -/********************************************************************//** - * @brief Generate a start condition on I2C bus (in master mode only) - * @param[in] I2Cx: I2C peripheral selected, should be: - * - LPC_I2C0 - * - LPC_I2C1 - * - LPC_I2C2 - * @param[in] Opt a I2C_TRANSFER_OPT_Type type that selected for - * interrupt or polling mode. - * @return value of I2C status register after generate a start condition - *********************************************************************/ -static uint32_t I2C_Start (LPC_I2C_TypeDef *I2Cx, I2C_TRANSFER_OPT_Type Opt) -{ - // Reset STA, STO, SI - I2Cx->CONCLR = I2C_I2CONCLR_SIC|I2C_I2CONCLR_STOC|I2C_I2CONCLR_STAC; - - // Enter to Master Transmitter mode - I2Cx->CONSET = I2C_I2CONSET_STA; - - if(Opt == I2C_TRANSFER_POLLING) - { - // Wait for complete - while (!(I2Cx->CONSET & I2C_I2CONSET_SI)); - } - - return (I2Cx->STAT & I2C_STAT_CODE_BITMASK); -} - -/********************************************************************//** - * @brief Generate a stop condition on I2C bus (in master mode only) - * @param[in] I2Cx: I2C peripheral selected, should be: - * - LPC_I2C0 - * - LPC_I2C1 - * - LPC_I2C2 - * @param[in] Opt a I2C_TRANSFER_OPT_Type type that selected for - * interrupt or polling mode. - * @return None - *********************************************************************/ -static void I2C_Stop (LPC_I2C_TypeDef *I2Cx, I2C_TRANSFER_OPT_Type Opt) -{ - /* Make sure start bit is not active */ - if (I2Cx->CONSET & I2C_I2CONSET_STA) - { - I2Cx->CONCLR = I2C_I2CONCLR_STAC; - } - - I2Cx->CONSET = I2C_I2CONSET_STO; - - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - - if(Opt == I2C_TRANSFER_POLLING) - { - // wait for stop is sent - while(I2Cx->CONSET & I2C_I2CONSET_STO) - { - if(I2Cx->CONSET & I2C_I2CONSET_SI) - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - } - } -} - -/********************************************************************//** - * @brief Send a byte - * @param[in] I2Cx: I2C peripheral selected, should be: - * - LPC_I2C0 - * - LPC_I2C1 - * - LPC_I2C2 - * @param[in] databyte: number of byte - * @return value of I2C status register after sending - *********************************************************************/ -static uint32_t I2C_SendByte (LPC_I2C_TypeDef *I2Cx, uint8_t databyte) -{ - uint32_t CodeStatus = I2Cx->STAT & I2C_STAT_CODE_BITMASK; - - if((CodeStatus != I2C_I2STAT_M_TX_START) && - (CodeStatus != I2C_I2STAT_M_TX_RESTART) && - (CodeStatus != I2C_I2STAT_M_TX_SLAW_ACK) && - (CodeStatus != I2C_I2STAT_M_TX_DAT_ACK) ) - { - return CodeStatus; - } - - I2Cx->DAT = databyte & I2C_I2DAT_BITMASK; - - I2Cx->CONSET = I2C_I2CONSET_AA; - - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - - return (I2Cx->STAT & I2C_STAT_CODE_BITMASK); -} - -/********************************************************************//** - * @brief Get a byte - * @param[in] I2Cx: I2C peripheral selected, should be: - * - LPC_I2C0 - * - LPC_I2C1 - * - LPC_I2C2 - * @param[out] retdat pointer to return data - * @param[in] ack assert acknowledge or not, should be: TRUE/FALSE - * @return value of I2C status register after sending - *********************************************************************/ -static uint32_t I2C_GetByte (LPC_I2C_TypeDef *I2Cx, uint8_t *retdat, Bool ack) -{ - *retdat = (uint8_t) (I2Cx->DAT & I2C_I2DAT_BITMASK); - - if (ack == TRUE) - { - I2Cx->CONSET = I2C_I2CONSET_AA; - } - else - { - I2Cx->CONCLR = I2C_I2CONCLR_AAC; - } - - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - - return (I2Cx->STAT & I2C_STAT_CODE_BITMASK); -} - -/*********************************************************************//** - * @brief Setup clock rate for I2C peripheral - * @param[in] I2Cx I2C peripheral selected, should be: - * - LPC_I2C0 - * - LPC_I2C1 - * - LPC_I2C2 - * @param[in] target_clock : clock of SSP (Hz) - * @return None - ***********************************************************************/ -static void I2C_SetClock (LPC_I2C_TypeDef *I2Cx, uint32_t target_clock) -{ - uint32_t temp; - - temp = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER) / target_clock; - - /* Set the I2C clock value to register */ - I2Cx->SCLH = (uint32_t)(temp / 2); - - I2Cx->SCLL = (uint32_t)(temp - I2Cx->SCLH); -} - - -/* End of Private Functions --------------------------------------------------- */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup I2C_Public_Functions - * @{ - */ - -/********************************************************************//** - * @brief Initializes the I2Cx peripheral with specified parameter. - * @param[in] I2Cx I2C peripheral selected, should be - * - LPC_I2C0 - * - LPC_I2C1 - * - LPC_I2C2 - * @param[in] clockrate Target clock rate value to initialized I2C - * peripheral (Hz) - * @return None - *********************************************************************/ -void I2C_Init(en_I2C_unitId i2cId, uint32_t clockrate) -{ - uint32_t clkSetting; - - LPC_I2C_TypeDef* I2Cx = I2C_GetPointer(i2cId); - - switch (i2cId) - { - case I2C_0: - clkSetting = CLKPWR_PCONP_PCI2C0; - break; - - - case I2C_1: - clkSetting = CLKPWR_PCONP_PCI2C1; - break; - - case I2C_2: - clkSetting = CLKPWR_PCONP_PCI2C2; - break; - - default: - - return; - } - - CLKPWR_ConfigPPWR (clkSetting, ENABLE); - - /* Set clock rate */ - I2C_SetClock(I2Cx,clockrate); - - /* Set I2C operation to default */ - I2Cx->CONCLR = (I2C_I2CONCLR_AAC | I2C_I2CONCLR_STAC | I2C_I2CONCLR_I2ENC); -} - -/*********************************************************************//** - * @brief De-initializes the I2C peripheral registers to their - * default reset values. - * @param[in] I2Cx I2C peripheral selected, should be - * - LPC_I2C0 - * - LPC_I2C1 - * - LPC_I2C2 - * @return None - **********************************************************************/ -void I2C_DeInit(en_I2C_unitId i2cId) -{ - uint32_t clkSetting; - - LPC_I2C_TypeDef* I2Cx = I2C_GetPointer(i2cId); - - /* Disable I2C control */ - I2Cx->CONCLR = 0xFF; - - switch (i2cId) - { - case I2C_0: - clkSetting = CLKPWR_PCONP_PCI2C0; - break; - - - case I2C_1: - clkSetting = CLKPWR_PCONP_PCI2C1; - break; - - case I2C_2: - clkSetting = CLKPWR_PCONP_PCI2C2; - break; - - default: - - return; - } - - CLKPWR_ConfigPPWR (clkSetting, DISABLE); -} - -/*********************************************************************//** - * @brief Enable or disable I2C peripheral's operation - * @param[in] I2Cx I2C peripheral selected, should be - * - LPC_I2C0 - * - LPC_I2C1 - * - LPC_I2C2 - * @param[in] NewState New State of I2Cx peripheral's operation - * @return none - **********************************************************************/ -void I2C_Cmd(en_I2C_unitId i2cId, en_I2C_Mode Mode, FunctionalState NewState) -{ - LPC_I2C_TypeDef* I2Cx = I2C_GetPointer(i2cId); - - if (NewState == ENABLE) - { - if(Mode != I2C_SLAVE_MODE) - I2Cx->CONSET = I2C_I2CONSET_I2EN; - else - I2Cx->CONSET = I2C_I2CONSET_I2EN | I2C_I2CONSET_AA; - } - else - { - I2Cx->CONCLR = I2C_I2CONCLR_I2ENC; - } -} - -/*********************************************************************//** - * @brief Enable/Disable interrupt for I2C peripheral - * @param[in] I2Cx I2C peripheral selected, should be: - * - LPC_I2C0 - * - LPC_I2C1 - * - LPC_I2C2 - * @param[in] NewState New State of I2C peripheral interrupt in NVIC core - * should be: - * - ENABLE: enable interrupt for this I2C peripheral - * - DISABLE: disable interrupt for this I2C peripheral - * @return None - **********************************************************************/ -void I2C_IntCmd (en_I2C_unitId i2cId, Bool NewState) -{ - IRQn_Type irq; - - switch (i2cId) - { - case I2C_0: - irq = I2C0_IRQn; - break; - - case I2C_1: - irq = I2C1_IRQn; - break; - - case I2C_2: - irq = I2C2_IRQn; - break; - - default: - - return; - } - - if (NewState) - { - NVIC_EnableIRQ(irq); - } - else - { - NVIC_DisableIRQ(irq); - } - - return; -} -/*********************************************************************//** - * @brief Handle I2C Master states. - * @param[in] I2Cx I2C peripheral selected, should be: - * - I2C_0 - * - I2C_1 - * - I2C_2 - * @param[in] CodeStatus I2C state - * @param[in] TransferCfg Pointer to a I2C_S_SETUP_Type structure that - * contains specified information about the - * configuration for master transfer. - * @param[in] Opt a I2C_TRANSFER_OPT_Type type that selected for - * interrupt or polling mode. - * @return It can be - * - I2C_OK - * -I2C_BYTE_RECV - * -I2C_BYTE_SENT - * -I2C_SEND_END - * -I2C_RECV_END - * - I2C_ERR - * - I2C_NAK_RECV - **********************************************************************/ -int32_t I2C_MasterHanleStates(en_I2C_unitId i2cId, - uint32_t CodeStatus, - I2C_M_SETUP_Type *TransferCfg, - I2C_TRANSFER_OPT_Type Opt - ) -{ - LPC_I2C_TypeDef* I2Cx = I2C_GetPointer(i2cId); - uint8_t *txdat; - uint8_t *rxdat; - uint8_t tmp; - int32_t Ret = I2C_OK; - - //get buffer to send/receive - txdat = (uint8_t *) &TransferCfg->tx_data[TransferCfg->tx_count]; - rxdat = (uint8_t *) &TransferCfg->rx_data[TransferCfg->rx_count]; - - switch(CodeStatus) - { - case I2C_I2STAT_M_TX_START: - case I2C_I2STAT_M_TX_RESTART: - //case I2C_I2STAT_M_RX_START: - //case I2C_I2STAT_M_RX_RESTART - // Send data first - if(TransferCfg->tx_count < TransferCfg->tx_length) - { - /* Send slave address + WR direction bit = 0 ----------------------------------- */ - I2C_SendByte(I2Cx, (TransferCfg->sl_addr7bit << 1)); - Ret = I2C_BYTE_SENT; - } - else if (TransferCfg->rx_count < TransferCfg->rx_length) - { - /* Send slave address + RD direction bit = 1 ----------------------------------- */ - I2C_SendByte(I2Cx, ((TransferCfg->sl_addr7bit << 1) | 0x01)); - Ret = I2C_BYTE_SENT; - } - // Clear STA bit after the slave address is sent - I2Cx->CONCLR = I2C_I2CONCLR_STAC; - break; - case I2C_I2STAT_M_TX_SLAW_ACK: - case I2C_I2STAT_M_TX_DAT_ACK: - - if(TransferCfg->tx_count < TransferCfg->tx_length) - { - I2C_SendByte(I2Cx, *txdat); - - txdat++; - - TransferCfg->tx_count++; - - Ret = I2C_BYTE_SENT; - } - else - { - if(TransferCfg->rx_count >= TransferCfg->rx_length) - { - I2C_Stop(I2Cx, Opt); - } - Ret = I2C_SEND_END; - - - } - - break; - case I2C_I2STAT_M_TX_DAT_NACK: - if(TransferCfg->rx_count >= TransferCfg->rx_length) - { - I2C_Stop(I2Cx, Opt); - } - Ret = I2C_SEND_END; - break; - case I2C_I2STAT_M_RX_ARB_LOST: - case I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL: - case I2C_I2STAT_S_TX_ARB_LOST_M_SLA: - //case I2C_I2STAT_M_TX_ARB_LOST: - I2C_Stop(I2Cx, Opt); - Ret = I2C_ERR; - break; - case I2C_I2STAT_M_RX_SLAR_ACK: - if(TransferCfg->rx_length > 1) - I2Cx->CONSET = I2C_I2CONSET_AA; - else - I2Cx->CONCLR = I2C_I2CONCLR_AAC; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - - Ret = I2C_BYTE_RECV; - break; - case I2C_I2STAT_M_RX_DAT_ACK: - if (TransferCfg->rx_count rx_length) - { - if ((TransferCfg->rx_length > 1) && (TransferCfg->rx_count < (TransferCfg->rx_length - 2))) - { - I2C_GetByte(I2Cx, &tmp, TRUE); - - Ret = I2C_BYTE_RECV; - - } - else // the next byte is the last byte, send NACK instead. - { - I2C_GetByte(I2Cx, &tmp, FALSE); - Ret = I2C_BYTE_RECV; - } - *rxdat++ = tmp; - - TransferCfg->rx_count++; - } - else - { - I2C_Stop(I2Cx, Opt); - Ret = I2C_RECV_END; - } - - break; - case I2C_I2STAT_M_RX_DAT_NACK: - I2C_GetByte(I2Cx, &tmp, FALSE); - if (TransferCfg->rx_count < TransferCfg->rx_length) - { - *rxdat++ = tmp; - TransferCfg->rx_count++; - } - I2C_Stop(I2Cx, Opt); - Ret = I2C_RECV_END; - break; - - case I2C_I2STAT_M_RX_SLAR_NACK: - case I2C_I2STAT_M_TX_SLAW_NACK: - case I2C_I2STAT_BUS_ERROR: - // Send STOP condition - I2C_Stop(I2Cx, Opt); - Ret = I2C_ERR; - break; - /* No status information */ - case I2C_I2STAT_NO_INF: - if ((TransferCfg->tx_count tx_length)|| - (TransferCfg->rx_count rx_length)) - { - I2C_Stop(I2Cx, Opt); - Ret = I2C_ERR; - } - else - { - Ret = I2C_RECV_END; - } - break; - default: - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - break; - } - - return Ret; -} - -/*********************************************************************//** - * @brief Handle I2C Slave states. - * @param[in] I2Cx I2C peripheral selected, should be: - * - I2C_0 - * - I2C_1 - * - I2C_2 - * @param[in] CodeStatus I2C state - * @param[in] TransferCfg Pointer to a I2C_S_SETUP_Type structure that - * contains specified information about the - * configuration for master transfer. - * @return It can be - * - I2C_OK - * -I2C_BYTE_RECV - * -I2C_BYTE_SENT - * -I2C_SEND_END - * -I2C_RECV_END - * - I2C_ERR - * - I2C_NAK_RECV - **********************************************************************/ -int32_t I2C_SlaveHanleStates(en_I2C_unitId i2cId, - uint32_t CodeStatus, - I2C_S_SETUP_Type *TransferCfg) -{ - LPC_I2C_TypeDef* I2Cx = I2C_GetPointer(i2cId); - int32_t Ret = I2C_OK; - uint8_t *txdat; - uint8_t *rxdat; - - //get buffer to send/receive - txdat = (uint8_t *) &TransferCfg->tx_data[TransferCfg->tx_count]; - rxdat = (uint8_t *) &TransferCfg->rx_data[TransferCfg->rx_count]; - - switch (CodeStatus) - { - /* Reading phase -------------------------------------------------------- */ - /* Own SLA+R has been received, ACK has been returned */ - case I2C_I2STAT_S_RX_SLAW_ACK: - - /* General call address has been received, ACK has been returned */ - case I2C_I2STAT_S_RX_GENCALL_ACK: - I2Cx->CONSET = I2C_I2CONSET_AA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - break; - /* Arbitration has been lost in Slave Address + R/W bit as bus Master. General Call has - been received and ACK has been returned.*/ - case I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL: - I2Cx->CONSET = I2C_I2CONSET_AA|I2C_I2CONSET_STA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - break; - /* Previously addressed with own SLA; - * DATA byte has been received; - * ACK has been returned */ - case I2C_I2STAT_S_RX_ARB_LOST_M_SLA: - case I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK: - - /* - * All data bytes that over-flow the specified receive - * data length, just ignore them. - */ - if ((TransferCfg->rx_count < TransferCfg->rx_length) && (TransferCfg->rx_data != NULL)) - { - *rxdat++ = (uint8_t)I2Cx->DAT; - - TransferCfg->rx_count++; - - Ret = I2C_BYTE_RECV; - } - if(TransferCfg->rx_count == (TransferCfg->rx_length) ) { - I2Cx->CONCLR = I2C_I2CONCLR_AAC|I2C_I2CONCLR_SIC; - Ret = I2C_BYTE_RECV; - } - else { - I2Cx->CONSET = I2C_I2CONSET_AA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - } - - break; - /* DATA has been received, Only the first data byte will be received with ACK. Additional - data will be received with NOT ACK. */ - case I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK: - if ((TransferCfg->rx_count < TransferCfg->rx_length) && (TransferCfg->rx_data != NULL)) - { - *rxdat++ = (uint8_t)I2Cx->DAT; - - TransferCfg->rx_count++; - - Ret = I2C_BYTE_RECV; - } - I2Cx->CONCLR = I2C_I2CONCLR_AAC|I2C_I2CONCLR_SIC; - break; - - /* Writing phase -------------------------------------------------------- */ - /* Own SLA+R has been received, ACK has been returned */ - case I2C_I2STAT_S_TX_SLAR_ACK: - - /* Data has been transmitted, ACK has been received */ - case I2C_I2STAT_S_TX_DAT_ACK: - /* - * All data bytes that over-flow the specified receive - * data length, just ignore them. - */ - if ((TransferCfg->tx_count < TransferCfg->tx_length) && (TransferCfg->tx_data != NULL)) - { - I2Cx->DAT = *txdat++; - - TransferCfg->tx_count++; - - Ret = I2C_BYTE_SENT; - } - - I2Cx->CONSET = I2C_I2CONSET_AA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - break; - /* Arbitration lost in Slave Address and R/W bit as bus Master. Own Slave Address + Read - has been received, ACK has been returned. */ - case I2C_I2STAT_S_TX_ARB_LOST_M_SLA: - if ((TransferCfg->tx_count < TransferCfg->tx_length) && (TransferCfg->tx_data != NULL)) - { - I2Cx->DAT = *txdat++; - - TransferCfg->tx_count++; - - Ret = I2C_BYTE_SENT; - } - I2Cx->CONSET = I2C_I2CONSET_AA|I2C_I2CONSET_STA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - break; - - case I2C_I2STAT_S_TX_LAST_DAT_ACK: - /* Data has been transmitted, NACK has been received, - * that means there's no more data to send, exit now */ - /* - * Note: Don't wait for stop event since in slave transmit mode, - * since there no proof lets us know when a stop signal has been received - * on slave side. - */ - case I2C_I2STAT_S_TX_DAT_NACK: - I2Cx->CONSET = I2C_I2CONSET_AA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - Ret = I2C_SEND_END; - break; - - /* Previously addressed with own SLA; - * DATA byte has been received; - * NOT ACK has been returned */ - case I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK: - - /* DATA has been received, NOT ACK has been returned */ - case I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK: - I2Cx->CONSET = I2C_I2CONSET_AA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - Ret = I2C_RECV_END; - break; - - /* - * Note that: Return code only let us know a stop condition mixed - * with a repeat start condition in the same code value. - * So we should provide a time-out. In case this is really a stop - * condition, this will return back after time out condition. Otherwise, - * next session that is slave receive data will be completed. - */ - - /* A Stop or a repeat start condition */ - case I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX: - I2Cx->CONSET = I2C_I2CONSET_AA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - Ret = I2C_STA_STO_RECV; - break; - - /* No status information */ - case I2C_I2STAT_NO_INF: - /* Other status must be captured */ - default: - I2Cx->CONSET = I2C_I2CONSET_AA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - break; - - } - - return Ret; -} -/*********************************************************************//** - * @brief General Master Interrupt handler for I2C peripheral - * @param[in] I2Cx I2C peripheral selected, should be: - * - LPC_I2C - * - LPC_I2C1 - * - LPC_I2C2 - * @return None - **********************************************************************/ -void I2C_MasterHandler(en_I2C_unitId i2cId) -{ - LPC_I2C_TypeDef* I2Cx = I2C_GetPointer(i2cId); - uint8_t returnCode; - I2C_M_SETUP_Type *txrx_setup; - int32_t Ret = I2C_OK; - - txrx_setup = (I2C_M_SETUP_Type *) i2cdat[i2cId].txrx_setup; - - returnCode = (I2Cx->STAT & I2C_STAT_CODE_BITMASK); - - // Save current status - txrx_setup->status = returnCode; - - Ret = I2C_MasterHanleStates(i2cId, returnCode, txrx_setup, I2C_TRANSFER_INTERRUPT); - - if(I2C_CheckError(Ret)) - { - if(txrx_setup->retransmissions_count < txrx_setup->retransmissions_max) - { - // Retry - txrx_setup->retransmissions_count ++; - txrx_setup->tx_count = 0; - txrx_setup->rx_count = 0; - // Reset STA, STO, SI - I2C_Start(I2Cx, I2C_TRANSFER_INTERRUPT); - return; - } - else - { - goto s_int_end; - } - } - else if (Ret & I2C_SEND_END) - { - // If no need to wait for data from Slave - if(txrx_setup->rx_count >= (txrx_setup->rx_length)) - { - goto s_int_end; - } - else // Start to wait for data from Slave - { - // Reset STA, STO, SI - I2C_Start(I2Cx, I2C_TRANSFER_INTERRUPT); - return; - } - } - else if (Ret & I2C_RECV_END) - { - goto s_int_end; - } - else - { - return; - } - -s_int_end: - // Disable interrupt - I2C_IntCmd(i2cId, FALSE); - - I2Cx->CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC; - - I2C_MasterComplete[i2cId] = TRUE; - -} - - -/*********************************************************************//** - * @brief General Slave Interrupt handler for I2C peripheral - * @param[in] I2Cx I2C peripheral selected, should be: - * - LPC_I2C0 - * - LPC_I2C1 - * - LPC_I2C2 - * @return None - **********************************************************************/ -void I2C_SlaveHandler (en_I2C_unitId i2cId) -{ - LPC_I2C_TypeDef* I2Cx = I2C_GetPointer(i2cId); - - uint8_t returnCode; - I2C_S_SETUP_Type *txrx_setup; - uint32_t timeout; - int32_t Ret = I2C_OK; - - txrx_setup = (I2C_S_SETUP_Type *) i2cdat[i2cId].txrx_setup; - -handle_state: - - returnCode = (I2Cx->STAT & I2C_STAT_CODE_BITMASK); - // Save current status - txrx_setup->status = returnCode; - - - Ret = I2C_SlaveHanleStates(i2cId, returnCode, txrx_setup); - - if(I2C_CheckError(Ret)) - { - goto s_int_end; - } - else if (Ret & I2C_STA_STO_RECV) - { - if((txrx_setup->tx_count >= (txrx_setup->tx_length)) && - (txrx_setup->rx_count >= (txrx_setup->rx_length))) - { - goto s_int_end; - } - // Temporally lock the interrupt for timeout condition - I2C_IntCmd(i2cId, FALSE); - // enable time out - timeout = I2C_SLAVE_TIME_OUT; - while(1) - { - if (I2Cx->CONSET & I2C_I2CONSET_SI) - { - // re-Enable interrupt - I2C_IntCmd(i2cId, TRUE); - goto handle_state; - } - else - { - timeout--; - if (timeout == 0) - { - // timeout occur, it's really a stop condition - txrx_setup->status |= I2C_SETUP_STATUS_DONE; - goto s_int_end; - } - } - } - } - else if(Ret &I2C_SEND_END) - { - goto s_int_end; - } - else - { - return; - } - -s_int_end: - // Disable interrupt - I2C_IntCmd(i2cId, FALSE); - I2Cx->CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC; - - I2C_SlaveComplete[i2cId] = TRUE; -} - -/*********************************************************************//** - * @brief Transmit and Receive data in master mode - * @param[in] I2Cx I2C peripheral selected, should be: - * - LPC_I2C0 - * - LPC_I2C1 - * - LPC_I2C2 - * @param[in] TransferCfg Pointer to a I2C_M_SETUP_Type structure that - * contains specified information about the - * configuration for master transfer. - * @param[in] Opt a I2C_TRANSFER_OPT_Type type that selected for - * interrupt or polling mode. - * @return SUCCESS or ERROR - * - * Note: - * - In case of using I2C to transmit data only, either transmit length set to 0 - * or transmit data pointer set to NULL. - * - In case of using I2C to receive data only, either receive length set to 0 - * or receive data pointer set to NULL. - * - In case of using I2C to transmit followed by receive data, transmit length, - * transmit data pointer, receive length and receive data pointer should be set - * corresponding. - **********************************************************************/ -Status I2C_MasterTransferData(en_I2C_unitId i2cId, I2C_M_SETUP_Type *TransferCfg, - I2C_TRANSFER_OPT_Type Opt) -{ - LPC_I2C_TypeDef* I2Cx = I2C_GetPointer(i2cId); - - uint32_t CodeStatus; - int32_t Ret = I2C_OK; - - // Reset I2C setup value to default state - TransferCfg->tx_count = 0; - TransferCfg->rx_count = 0; - TransferCfg->status = 0; - - if (Opt == I2C_TRANSFER_POLLING) - { - /* First Start condition -------------------------------------------------------------- */ - TransferCfg->retransmissions_count = 0; -retry: - // Reset I2C setup value to default state - TransferCfg->tx_count = 0; - TransferCfg->rx_count = 0; - - // Start command - CodeStatus = I2C_Start(I2Cx, I2C_TRANSFER_POLLING); - - while(1) // send data first and then receive data from Slave. - { - Ret = I2C_MasterHanleStates(i2cId, CodeStatus, TransferCfg, I2C_TRANSFER_POLLING); - if(I2C_CheckError(Ret)) - { - TransferCfg->retransmissions_count++; - if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){ - // save status - TransferCfg->status = CodeStatus | I2C_SETUP_STATUS_NOACKF; - goto error; - } else { - goto retry; - } - } - else if( (Ret & I2C_BYTE_SENT) || - (Ret & I2C_BYTE_RECV)) - { - // Wait for sending ends/ Wait for next byte - while (!(I2Cx->CONSET & I2C_I2CONSET_SI)); - } - else if (Ret & I2C_SEND_END) // already send all data - { - // If no need to wait for data from Slave - if(TransferCfg->rx_count >= (TransferCfg->rx_length)) - { - break; - } - else - { - I2C_Start(I2Cx, I2C_TRANSFER_POLLING); - } - } - else if (Ret & I2C_RECV_END) // already receive all data - { - break; - } - CodeStatus = I2Cx->STAT & I2C_STAT_CODE_BITMASK; - } - return SUCCESS; -error: - return ERROR; - } - - else if (Opt == I2C_TRANSFER_INTERRUPT) - { - // Setup tx_rx data, callback and interrupt handler - i2cdat[i2cId].txrx_setup = (uint32_t) TransferCfg; - - // Set direction phase, write first - i2cdat[i2cId].dir = 0; - - /* First Start condition -------------------------------------------------------------- */ - // Reset STA, STO, SI - I2C_Start(I2Cx, I2C_TRANSFER_INTERRUPT); - - I2C_IntCmd(i2cId, TRUE); - - return (SUCCESS); - } - - return ERROR; -} - -/*********************************************************************//** - * @brief Receive and Transmit data in slave mode - * @param[in] I2Cx I2C peripheral selected, should be - * - LPC_I2C0 - * - LPC_I2C1 - * - LPC_I2C2 - * @param[in] TransferCfg Pointer to a I2C_S_SETUP_Type structure that - * contains specified information about the - * configuration for master transfer. - * @param[in] Opt I2C_TRANSFER_OPT_Type type that selected for - * interrupt or polling mode. - * @return SUCCESS or ERROR - * - * Note: - * The mode of slave's operation depends on the command sent from master on - * the I2C bus. If the master send a SLA+W command, this sub-routine will - * use receive data length and receive data pointer. If the master send a SLA+R - * command, this sub-routine will use transmit data length and transmit data - * pointer. - * If the master issue an repeat start command or a stop command, the slave will - * enable an time out condition, during time out condition, if there's no activity - * on I2C bus, the slave will exit, otherwise (i.e. the master send a SLA+R/W), - * the slave then switch to relevant operation mode. The time out should be used - * because the return status code can not show difference from stop and repeat - * start command in slave operation. - * In case of the expected data length from master is greater than data length - * that slave can support: - * - In case of reading operation (from master): slave will return I2C_I2DAT_IDLE_CHAR - * value. - * - In case of writing operation (from master): slave will ignore remain data from master. - **********************************************************************/ -Status I2C_SlaveTransferData(en_I2C_unitId i2cId, I2C_S_SETUP_Type *TransferCfg, - I2C_TRANSFER_OPT_Type Opt) -{ - LPC_I2C_TypeDef* I2Cx = I2C_GetPointer(i2cId); - int32_t Ret = I2C_OK; - - uint32_t CodeStatus; - uint32_t timeout; - int32_t time_en; - - // Reset I2C setup value to default state - TransferCfg->tx_count = 0; - TransferCfg->rx_count = 0; - TransferCfg->status = 0; - - // Polling option - if (Opt == I2C_TRANSFER_POLLING) - { - /* Set AA bit to ACK command on I2C bus */ - I2Cx->CONSET = I2C_I2CONSET_AA; - - /* Clear SI bit to be ready ... */ - I2Cx->CONCLR = (I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC|I2C_I2CONCLR_STOC); - - time_en = 0; - timeout = 0; - - while (1) - { - /* Check SI flag ready */ - if (I2Cx->CONSET & I2C_I2CONSET_SI) - { - time_en = 0; - - CodeStatus = (I2Cx->STAT & I2C_STAT_CODE_BITMASK); - - Ret = I2C_SlaveHanleStates(i2cId, CodeStatus, TransferCfg); - if(I2C_CheckError(Ret)) - { - goto s_error; - } - else if(Ret & I2C_STA_STO_RECV) - { - if((TransferCfg->tx_count >= (TransferCfg->tx_length)) && - (TransferCfg->rx_count >= (TransferCfg->rx_length))) - { - goto s_end_stage; - } - time_en = 1; - timeout = 0; - } - else if (Ret & I2C_SEND_END) - { - goto s_end_stage; - } - } - else if (time_en) - { - if (timeout++ > I2C_SLAVE_TIME_OUT) - { - // it's really a stop condition, goto end stage - goto s_end_stage; - } - } - } - -s_end_stage: - /* Clear AA bit to disable ACK on I2C bus */ - I2Cx->CONCLR = I2C_I2CONCLR_AAC; - - // Check if there's no error during operation - // Update status - TransferCfg->status = CodeStatus | I2C_SETUP_STATUS_DONE; - return SUCCESS; - -s_error: - /* Clear AA bit to disable ACK on I2C bus */ - I2Cx->CONCLR = I2C_I2CONCLR_AAC; - - // Update status - TransferCfg->status = CodeStatus; - return ERROR; - } - - else if (Opt == I2C_TRANSFER_INTERRUPT) - { - // Setup tx_rx data, callback and interrupt handler - i2cdat[i2cId].txrx_setup = (uint32_t) TransferCfg; - - // Set direction phase, read first - i2cdat[i2cId].dir = 1; - - // Enable AA - I2Cx->CONSET = I2C_I2CONSET_AA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC; - I2C_IntCmd(i2cId, TRUE); - - return (SUCCESS); - } - - return ERROR; -} - -/*********************************************************************//** - * @brief Set Own slave address in I2C peripheral corresponding to - * parameter specified in OwnSlaveAddrConfigStruct. - * @param[in] I2Cx I2C peripheral selected, should be - * - LPC_I2C0 - * - LPC_I2C1 - * - LPC_I2C2 - * @param[in] OwnSlaveAddrConfigStruct Pointer to a I2C_OWNSLAVEADDR_CFG_Type - * structure that contains the configuration information for the -* specified I2C slave address. - * @return None - **********************************************************************/ -void I2C_SetOwnSlaveAddr(en_I2C_unitId i2cId, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct) -{ - LPC_I2C_TypeDef* I2Cx = I2C_GetPointer(i2cId); - - uint32_t tmp; - - tmp = (((uint32_t)(OwnSlaveAddrConfigStruct->SlaveAddr_7bit << 1)) \ - | ((OwnSlaveAddrConfigStruct->GeneralCallState == ENABLE) ? 0x01 : 0x00))& I2C_I2ADR_BITMASK; - - switch (OwnSlaveAddrConfigStruct->SlaveAddrChannel) - { - case 0: - I2Cx->ADR0 = tmp; - - I2Cx->MASK0 = I2C_I2MASK_MASK((uint32_t) \ - (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue)); - break; - - case 1: - I2Cx->ADR1 = tmp; - - I2Cx->MASK1 = I2C_I2MASK_MASK((uint32_t) \ - (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue)); - break; - - case 2: - I2Cx->ADR2 = tmp; - - I2Cx->MASK2 = I2C_I2MASK_MASK((uint32_t) \ - (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue)); - break; - - case 3: - I2Cx->ADR3 = tmp; - - I2Cx->MASK3 = I2C_I2MASK_MASK((uint32_t) \ - (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue)); - break; - } -} - - -/*********************************************************************//** - * @brief Configures functionality in I2C monitor mode - * @param[in] I2Cx I2C peripheral selected, should be - * - LPC_I2C0 - * - LPC_I2C1 - * - LPC_I2C2 - * @param[in] Monitor configuration. It can include: - * - I2C_I2MMCTRL_ENA_SCL: I2C module can 'stretch' - * the clock line (hold it low) until it has had time to - * respond to an I2C interrupt. - * - I2C_I2MMCTRL_MATCH_ALL: When the I2C is in monitor mode, - * an interrupt will be generated on ANY address received. - * @param[in] NewState New State of this function, should be: - * - ENABLE: Enable this function. - * - DISABLE: Disable this function. - * @return None - **********************************************************************/ -void I2C_MonitorModeConfig(en_I2C_unitId i2cId, uint32_t MonitorCfgType, FunctionalState NewState) -{ - LPC_I2C_TypeDef* I2Cx = I2C_GetPointer(i2cId); - - if (NewState == ENABLE) - { - I2Cx->MMCTRL |= MonitorCfgType; - } - else - { - I2Cx->MMCTRL &= (~MonitorCfgType) & I2C_I2MMCTRL_BITMASK; - } -} - - -/*********************************************************************//** - * @brief Enable/Disable I2C monitor mode - * @param[in] I2Cx I2C peripheral selected, should be - * - LPC_I2C0 - * - LPC_I2C1 - * - LPC_I2C2 - * @param[in] NewState New State of this function, should be: - * - ENABLE: Enable monitor mode. - * - DISABLE: Disable monitor mode. - * @return None - **********************************************************************/ -void I2C_MonitorModeCmd(en_I2C_unitId i2cId, FunctionalState NewState) -{ - LPC_I2C_TypeDef* I2Cx = I2C_GetPointer(i2cId); - - if (NewState == ENABLE) - { - I2Cx->MMCTRL |= I2C_I2MMCTRL_MM_ENA; - I2Cx->CONSET = I2C_I2CONSET_AA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC; - } - else - { - I2Cx->MMCTRL &= (~I2C_I2MMCTRL_MM_ENA) & I2C_I2MMCTRL_BITMASK; - I2Cx->CONCLR = I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC | I2C_I2CONCLR_AAC; - } - - I2C_MonitorBufferIndex = 0; -} - - -/*********************************************************************//** - * @brief Get data from I2C data buffer in monitor mode. - * @param[in] I2Cx I2C peripheral selected, should be - * - LPC_I2C0 - * - LPC_I2C1 - * - LPC_I2C2 - * @return None - * Note: In monitor mode, the I2C module may lose the ability to stretch - * the clock (stall the bus) if the ENA_SCL bit is not set. This means that - * the processor will have a limited amount of time to read the contents of - * the data received on the bus. If the processor reads the DAT shift - * register, as it ordinarily would, it could have only one bit-time to - * respond to the interrupt before the received data is overwritten by - * new data. - **********************************************************************/ -uint8_t I2C_MonitorGetDatabuffer(en_I2C_unitId i2cId) -{ - LPC_I2C_TypeDef* I2Cx = I2C_GetPointer(i2cId); - - return ((uint8_t)(I2Cx->DATA_BUFFER)); -} - -/*********************************************************************//** - * @brief Get data from I2C data buffer in monitor mode. - * @param[in] I2Cx I2C peripheral selected, should be - * - LPC_I2C0 - * - LPC_I2C1 - * - LPC_I2C2 - * @return None - * Note: In monitor mode, the I2C module may lose the ability to stretch - * the clock (stall the bus) if the ENA_SCL bit is not set. This means that - * the processor will have a limited amount of time to read the contents of - * the data received on the bus. If the processor reads the DAT shift - * register, as it ordinarily would, it could have only one bit-time to - * respond to the interrupt before the received data is overwritten by - * new data. - **********************************************************************/ -BOOL_8 I2C_MonitorHandler(en_I2C_unitId i2cId, uint8_t *buffer, uint32_t size) -{ - LPC_I2C_TypeDef* I2Cx = I2C_GetPointer(i2cId); - - BOOL_8 ret=FALSE; - - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - - buffer[I2C_MonitorBufferIndex] = (uint8_t)(I2Cx->DATA_BUFFER); - - I2C_MonitorBufferIndex++; - - if(I2C_MonitorBufferIndex >= size) - { - ret = TRUE; - } - return ret; -} -/*********************************************************************//** - * @brief Get status of Master Transfer - * @param[in] I2Cx I2C peripheral selected, should be: - * - LPC_I2C0 - * - LPC_I2C1 - * - LPC_I2C2 - * @return Master transfer status, could be: - * - TRUE master transfer completed - * - FALSE master transfer have not completed yet - **********************************************************************/ -uint32_t I2C_MasterTransferComplete(en_I2C_unitId i2cId) -{ - uint32_t retval; - - retval = I2C_MasterComplete[i2cId]; - - I2C_MasterComplete[i2cId] = FALSE; - - return retval; -} - -/*********************************************************************//** - * @brief Get status of Slave Transfer - * @param[in] I2Cx I2C peripheral selected, should be: - * - LPC_I2C0 - * - LPC_I2C1 - * - LPC_I2C2 - * @return Complete status, could be: TRUE/FALSE - **********************************************************************/ -uint32_t I2C_SlaveTransferComplete(en_I2C_unitId i2cId) -{ - uint32_t retval; - - retval = I2C_SlaveComplete[i2cId]; - - I2C_SlaveComplete[i2cId] = FALSE; - - return retval; -} - -#endif /*_I2C*/ - -/** - * @} - */ - - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_i2s.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_i2s.c deleted file mode 100644 index 88172c75541..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_i2s.c +++ /dev/null @@ -1,589 +0,0 @@ -/********************************************************************** -* $Id$ lpc_i2s.c 2011-06-02 -*//** -* @file lpc_i2s.c -* @brief Contains all functions support for I2S firmware library -* on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup I2S - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _I2S - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_i2s.h" -#include "lpc_clkpwr.h" - -/* definitions ---------------------------------------------------------- */ -#define I2S_IS_ENABLED(x) ((x)? ENABLE:DISABLE) -/* Private Functions ---------------------------------------------------------- */ - -static uint8_t i2s_GetWordWidth(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode); -static uint8_t i2s_GetChannel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode); - -/********************************************************************//** - * @brief Get I2S wordwidth value - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode is the I2S mode, should be: - * - I2S_TX_MODE = 0: transmit mode - * - I2S_RX_MODE = 1: receive mode - * @return The wordwidth value, should be: 8,16 or 32 - *********************************************************************/ -static uint8_t i2s_GetWordWidth(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode) { - uint8_t value; - - if (TRMode == I2S_TX_MODE) { - value = (I2Sx->DAO) & 0x03; /* get wordwidth bit */ - } else { - value = (I2Sx->DAI) & 0x03; /* get wordwidth bit */ - } - switch (value) { - case I2S_WORDWIDTH_8: - return 8; - case I2S_WORDWIDTH_16: - return 16; - default: - return 32; - } -} - -/********************************************************************//** - * @brief Get I2S channel value - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode is the I2S mode, should be: - * - I2S_TX_MODE = 0: transmit mode - * - I2S_RX_MODE = 1: receive mode - * @return The channel value, should be: 1(mono) or 2(stereo) - *********************************************************************/ -static uint8_t i2s_GetChannel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode) { - uint8_t value; - - if (TRMode == I2S_TX_MODE) { - value = ((I2Sx->DAO) & 0x04)>>2; /* get bit[2] */ - } else { - value = ((I2Sx->DAI) & 0x04)>>2; /* get bit[2] */ - } - if(value == I2S_MONO) return 1; - return 2; -} - -/* End of Private Functions --------------------------------------------------- */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup I2S_Public_Functions - * @{ - */ - -/********************************************************************//** - * @brief Initialize I2S - * - Turn on power and clock - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @return none - *********************************************************************/ -void I2S_Init(LPC_I2S_TypeDef *I2Sx) { - // Turn on power and clock - CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCI2S, ENABLE); - LPC_I2S->DAI = LPC_I2S->DAO = 0x00; -} - -/********************************************************************//** - * @brief Configuration I2S, setting: - * - master/slave mode - * - wordwidth value - * - channel mode - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode transmit/receive mode, should be: - * - I2S_TX_MODE = 0: transmit mode - * - I2S_RX_MODE = 1: receive mode - * @param[in] ConfigStruct pointer to I2S_CFG_Type structure - * which will be initialized. - * @return none - *********************************************************************/ -void I2S_Config(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct) -{ - uint32_t bps, config; - /* Setup clock */ - bps = (ConfigStruct->wordwidth +1)*8; - - /* Calculate audio config */ - config = (bps - 1)<<6 | (ConfigStruct->ws_sel)<<5 | (ConfigStruct->reset)<<4 | - (ConfigStruct->stop)<<3 | (ConfigStruct->mono)<<2 | (ConfigStruct->wordwidth); - - if(TRMode == I2S_RX_MODE){ - LPC_I2S->DAI = config; - }else{ - LPC_I2S->DAO = config; - } -} - -/********************************************************************//** - * @brief DeInitial both I2S transmit or receive - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @return none - *********************************************************************/ -void I2S_DeInit(LPC_I2S_TypeDef *I2Sx) { - // Turn off power and clock - CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCI2S, DISABLE); -} - -/********************************************************************//** - * @brief Get I2S Buffer Level - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode Transmit/receive mode, should be: - * - I2S_TX_MODE = 0: transmit mode - * - I2S_RX_MODE = 1: receive mode - * @return current level of Transmit/Receive Buffer - *********************************************************************/ -uint8_t I2S_GetLevel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode) -{ - - if(TRMode == I2S_TX_MODE) - { - return ((I2Sx->STATE >> 16) & 0xFF); - } - else - { - return ((I2Sx->STATE >> 8) & 0xFF); - } -} - -/********************************************************************//** - * @brief I2S Start: clear all STOP,RESET and MUTE bit, ready to operate - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @return none - *********************************************************************/ -void I2S_Start(LPC_I2S_TypeDef *I2Sx) -{ - //Clear STOP,RESET and MUTE bit - I2Sx->DAO &= ~I2S_DAI_RESET; - I2Sx->DAI &= ~I2S_DAI_RESET; - I2Sx->DAO &= ~I2S_DAI_STOP; - I2Sx->DAI &= ~I2S_DAI_STOP; - I2Sx->DAO &= ~I2S_DAI_MUTE; -} - -/********************************************************************//** - * @brief I2S Send data - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] BufferData pointer to uint32_t is the data will be send - * @return none - *********************************************************************/ -void I2S_Send(LPC_I2S_TypeDef *I2Sx, uint32_t BufferData) -{ - I2Sx->TXFIFO = BufferData; -} - -/********************************************************************//** - * @brief I2S Receive Data - * @param[in] I2Sx pointer to LPC_I2S_TypeDef - * @return received value - *********************************************************************/ -uint32_t I2S_Receive(LPC_I2S_TypeDef* I2Sx) -{ - return (I2Sx->RXFIFO); -} - -/********************************************************************//** - * @brief I2S Pause - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0: transmit mode - * - I2S_RX_MODE = 1: receive mode - * @return none - *********************************************************************/ -void I2S_Pause(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode) { - if (TRMode == I2S_TX_MODE) //Transmit mode - { - I2Sx->DAO |= I2S_DAO_STOP; - } else //Receive mode - { - I2Sx->DAI |= I2S_DAI_STOP; - } -} - -/********************************************************************//** - * @brief I2S Mute - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0: transmit mode - * - I2S_RX_MODE = 1: receive mode - * @return none - *********************************************************************/ -void I2S_Mute(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode) { - if (TRMode == I2S_TX_MODE) //Transmit mode - { - I2Sx->DAO |= I2S_DAO_MUTE; - } else //Receive mode - { - I2Sx->DAI |= I2S_DAI_MUTE; - } -} - -/********************************************************************//** - * @brief I2S Stop - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0: transmit mode - * - I2S_RX_MODE = 1: receive mode - * @return none - *********************************************************************/ -void I2S_Stop(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode) { - if (TRMode == I2S_TX_MODE) //Transmit mode - { - I2Sx->DAO &= ~I2S_DAO_MUTE; - I2Sx->DAO |= I2S_DAO_STOP; - I2Sx->DAO |= I2S_DAO_RESET; - } else //Receive mode - { - I2Sx->DAI |= I2S_DAI_STOP; - I2Sx->DAI |= I2S_DAI_RESET; - } -} -/********************************************************************//** - * @brief Set frequency for I2S - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] Freq is the frequency for I2S will be set. It can range - * from 16-96 kHz(16, 22.05, 32, 44.1, 48, 96kHz) - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0: transmit mode - * - I2S_RX_MODE = 1: receive mode - * @return Status: ERROR or SUCCESS - *********************************************************************/ -Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode) { - uint32_t cclk; - uint8_t channel, wordwidth; - uint32_t x, y; - uint64_t divider; - uint16_t dif; - uint16_t x_divide, y_divide; - uint16_t err, ErrorOptimal = 0xFFFF; - - uint32_t N; - - //get cclk - cclk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_CPU); - - if(TRMode == I2S_TX_MODE) - { - channel = i2s_GetChannel(I2Sx,I2S_TX_MODE); - wordwidth = i2s_GetWordWidth(I2Sx,I2S_TX_MODE); - } - else - { - channel = i2s_GetChannel(I2Sx,I2S_RX_MODE); - wordwidth = i2s_GetWordWidth(I2Sx,I2S_RX_MODE); - } - - /* Calculate X and Y divider - * The MCLK rate for the I2S transmitter is determined by the value - * in the I2STXRATE/I2SRXRATE register. The required I2STXRATE/I2SRXRATE - * setting depends on the desired audio sample rate desired, the format - * (stereo/mono) used, and the data size. - * The formula is: - * I2S_MCLK = CCLK * (X/Y) / 2 - * We have: - * I2S_MCLK = Freq * channel*wordwidth * (I2Sx->TXBITRATE+1); - * So: (X/Y) = (Freq * channel*wordwidth * (I2Sx->TXBITRATE+1))/CCLK*2 - * We use a loop function to chose the most suitable X,Y value - */ - - /* divider is a fixed point number with 16 fractional bits */ - divider = (((uint64_t)Freq *channel*wordwidth * 2)<<16) / cclk; - - /* find N that make x/y <= 1 -> divider <= 2^16 */ - for(N=64;N>0;N--){ - if((divider*N) < (1<<16)) break; - } - - if(N == 0) return ERROR; - - divider *= N; - - for (y = 255; y > 0; y--) { - x = y * divider; - if(x & (0xFF000000)) continue; - dif = x & 0xFFFF; - if(dif>0x8000) err = 0x10000-dif; - else err = dif; - if (err == 0) - { - y_divide = y; - break; - } - else if (err < ErrorOptimal) - { - ErrorOptimal = err; - y_divide = y; - } - } - x_divide = ((uint64_t)y_divide * Freq *(channel*wordwidth)* N * 2)/cclk; - if(x_divide >= 256) x_divide = 0xFF; - if(x_divide == 0) x_divide = 1; - - if (TRMode == I2S_TX_MODE)// Transmitter - { - I2Sx->TXBITRATE = N-1; - I2Sx->TXRATE = y_divide | (x_divide << 8); - } else //Receiver - { - I2Sx->RXBITRATE = N-1; - I2Sx->TXRATE = y_divide | (x_divide << 8); - } - return SUCCESS; -} - -/********************************************************************//** - * @brief I2S set bitrate - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] bitrate value will be set - * bitrate value should be in range: 0 .. 63 - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0: transmit mode - * - I2S_RX_MODE = 1: receive mode - * @return none - *********************************************************************/ -void I2S_SetBitRate(LPC_I2S_TypeDef *I2Sx, uint8_t bitrate, uint8_t TRMode) -{ - if(TRMode == I2S_TX_MODE) - { - I2Sx->TXBITRATE = bitrate; - } - else - { - I2Sx->RXBITRATE = bitrate; - } -} - -/********************************************************************//** - * @brief Configuration operating mode for I2S - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] ModeConfig pointer to I2S_MODEConf_Type will be used to - * configure - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0: transmit mode - * - I2S_RX_MODE = 1: receive mode - * @return none - *********************************************************************/ -void I2S_ModeConfig(LPC_I2S_TypeDef *I2Sx, I2S_MODEConf_Type* ModeConfig, - uint8_t TRMode) -{ - if (TRMode == I2S_TX_MODE) { - I2Sx->TXMODE &= ~0x0F; //clear bit 3:0 in I2STXMODE register - if (ModeConfig->clksel == I2S_CLKSEL_MCLK) { - I2Sx->TXMODE |= 0x02; - } - if (ModeConfig->fpin == I2S_4PIN_ENABLE) { - I2Sx->TXMODE |= (1 << 2); - } - if (ModeConfig->mcena == I2S_MCLK_ENABLE) { - I2Sx->TXMODE |= (1 << 3); - } - } else { - I2Sx->RXMODE &= ~0x0F; //clear bit 3:0 in I2STXMODE register - if (ModeConfig->clksel == I2S_CLKSEL_MCLK) { - I2Sx->RXMODE |= 0x02; - } - if (ModeConfig->fpin == I2S_4PIN_ENABLE) { - I2Sx->RXMODE |= (1 << 2); - } - if (ModeConfig->mcena == I2S_MCLK_ENABLE) { - I2Sx->RXMODE |= (1 << 3); - } - } -} - -/********************************************************************//** - * @brief Configure DMA operation for I2S - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] DMAConfig pointer to I2S_DMAConf_Type will be used to configure - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0: transmit mode - * - I2S_RX_MODE = 1: receive mode - * @return none - *********************************************************************/ -void I2S_DMAConfig(LPC_I2S_TypeDef *I2Sx, I2S_DMAConf_Type* DMAConfig, - uint8_t TRMode) -{ - if (TRMode == I2S_RX_MODE) { - if (DMAConfig->DMAIndex == I2S_DMA_1) { - LPC_I2S->DMA1 = (DMAConfig->depth) << 8; - } else { - LPC_I2S->DMA2 = (DMAConfig->depth) << 8; - } - } else { - if (DMAConfig->DMAIndex == I2S_DMA_1) { - LPC_I2S->DMA1 = (DMAConfig->depth) << 16; - } else { - LPC_I2S->DMA2 = (DMAConfig->depth) << 16; - } - } -} - -/********************************************************************//** - * @brief Enable/Disable DMA operation for I2S - * @param[in] I2Sx: I2S peripheral selected, should be: LPC_I2S - * @param[in] DMAIndex chose what DMA is used, should be: - * - I2S_DMA_1 = 0: DMA1 - * - I2S_DMA_2 = 1: DMA2 - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0: transmit mode - * - I2S_RX_MODE = 1: receive mode - * @param[in] NewState is new state of DMA operation, should be: - * - ENABLE - * - DISABLE - * @return none - *********************************************************************/ -void I2S_DMACmd(LPC_I2S_TypeDef *I2Sx, uint8_t DMAIndex, uint8_t TRMode, - FunctionalState NewState) -{ - if (TRMode == I2S_RX_MODE) { - if (DMAIndex == I2S_DMA_1) { - if (NewState == ENABLE) - I2Sx->DMA1 |= 0x01; - else - I2Sx->DMA1 &= ~0x01; - } else { - if (NewState == ENABLE) - I2Sx->DMA2 |= 0x01; - else - I2Sx->DMA2 &= ~0x01; - } - } else { - if (DMAIndex == I2S_DMA_1) { - if (NewState == ENABLE) - I2Sx->DMA1 |= 0x02; - else - I2Sx->DMA1 &= ~0x02; - } else { - if (NewState == ENABLE) - I2Sx->DMA2 |= 0x02; - else - I2Sx->DMA2 &= ~0x02; - } - } -} - -/********************************************************************//** - * @brief Configure IRQ for I2S - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0: transmit mode - * - I2S_RX_MODE = 1: receive mode - * @param[in] level is the FIFO level that triggers IRQ request - * @return none - *********************************************************************/ -void I2S_IRQConfig(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, uint8_t level) { - if (TRMode == I2S_RX_MODE) { - I2Sx->IRQ |= (level << 8); - } else { - I2Sx->IRQ |= (level << 16); - } -} - -/********************************************************************//** - * @brief Enable/Disable IRQ for I2S - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0: transmit mode - * - I2S_RX_MODE = 1: receive mode - * @param[in] NewState is new state of DMA operation, should be: - * - ENABLE - * - DISABLE - * @return none - *********************************************************************/ -void I2S_IRQCmd(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, FunctionalState NewState) { - - if (TRMode == I2S_RX_MODE) { - if (NewState == ENABLE) - I2Sx->IRQ |= 0x01; - else - I2Sx->IRQ &= ~0x01; - //Enable DMA - - } else { - if (NewState == ENABLE) - I2Sx->IRQ |= 0x02; - else - I2Sx->IRQ &= ~0x02; - } -} - -/********************************************************************//** - * @brief Get I2S interrupt status - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0: transmit mode - * - I2S_RX_MODE = 1: receive mode - * @return FunctionState should be: - * - ENABLE: interrupt is enable - * - DISABLE: interrupt is disable - *********************************************************************/ -FunctionalState I2S_GetIRQStatus(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode) -{ - - if(TRMode == I2S_TX_MODE) - return I2S_IS_ENABLED((I2Sx->IRQ >> 1)&0x01); - else - return I2S_IS_ENABLED((I2Sx->IRQ)&0x01); -} - -/********************************************************************//** - * @brief Get I2S interrupt depth - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0: transmit mode - * - I2S_RX_MODE = 1: receive mode - * @return depth of FIFO level on which to create an irq request - *********************************************************************/ -uint8_t I2S_GetIRQDepth(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode) -{ - - if(TRMode == I2S_TX_MODE) - return (((I2Sx->IRQ)>>16)&0xFF); - else - return (((I2Sx->IRQ)>>8)&0xFF); -} -/** - * @} - */ - -#endif /*_I2S*/ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_iap.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_iap.c deleted file mode 100644 index ceccf365704..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_iap.c +++ /dev/null @@ -1,317 +0,0 @@ -/********************************************************************** -* $Id$ lpc_iap.c 2011-11-21 -*//** -* @file lpc_iap.c - * @brief Contains all functions support for IAP on LPC -* @version 1.0 -* @date 21. November. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _IAP -#include "lpc_iap.h" -#include "lpc_clkpwr.h" - -// IAP Command -typedef void (*IAP)(uint32_t *cmd,uint32_t *result); -IAP iap_entry = (IAP) IAP_LOCATION; -#define IAP_Call iap_entry - -/** @addtogroup IAP_Public_Functions LCD Public Function - * @ingroup IAP - * @{ - */ - - -/*********************************************************************//** - * @brief Get Sector Number - * - * @param[in] adr Sector Address - * - * @return Sector Number. - * - **********************************************************************/ - uint32_t GetSecNum (uint32_t adr) -{ - uint32_t n; - - n = adr >> 12; // 4kB Sector - if (n >= 0x10) { - n = 0x0E + (n >> 3); // 32kB Sector - } - - return (n); // Sector Number -} - -/*********************************************************************//** - * @brief Prepare sector(s) for write operation - * - * @param[in] start_sec The number of start sector - * @param[in] end_sec The number of end sector - * - * @return CMD_SUCCESS/BUSY/INVALID_SECTOR. - * - **********************************************************************/ -IAP_STATUS_CODE PrepareSector(uint32_t start_sec, uint32_t end_sec) -{ - IAP_COMMAND_Type command; - command.cmd = IAP_PREPARE; // Prepare Sector for Write - command.param[0] = start_sec; // Start Sector - command.param[1] = end_sec; // End Sector - IAP_Call (&command.cmd, &command.status); // Call IAP Command - return (IAP_STATUS_CODE)command.status; -} - -/*********************************************************************//** - * @brief Copy RAM to Flash - * - * @param[in] dest destination buffer (in Flash memory). - * @param[in] source source buffer (in RAM). - * @param[in] size the write size. - * - * @return CMD_SUCCESS. - * SRC_ADDR_ERROR/DST_ADDR_ERROR - * SRC_ADDR_NOT_MAPPED/DST_ADDR_NOT_MAPPED - * COUNT_ERROR/SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION - * BUSY - * - **********************************************************************/ -IAP_STATUS_CODE CopyRAM2Flash(uint8_t * dest, uint8_t* source, IAP_WRITE_SIZE size) -{ - uint32_t sec; - IAP_STATUS_CODE status; - IAP_COMMAND_Type command; - - // Prepare sectors - sec = GetSecNum((uint32_t)dest); - status = PrepareSector(sec, sec); - if(status != CMD_SUCCESS) - return status; - - // write - command.cmd = IAP_COPY_RAM2FLASH; // Copy RAM to Flash - command.param[0] = (uint32_t)dest; // Destination Flash Address - command.param[1] = (uint32_t)source; // Source RAM Address - command.param[2] = size; // Number of bytes - command.param[3] = CLKPWR_GetCLK(CLKPWR_CLKTYPE_CPU) / 1000; // CCLK in kHz - IAP_Call (&command.cmd, &command.status); // Call IAP Command - - return (IAP_STATUS_CODE)command.status; // Finished without Errors -} - -/*********************************************************************//** - * @brief Erase sector(s) - * - * @param[in] start_sec The number of start sector - * @param[in] end_sec The number of end sector - * - * @return CMD_SUCCESS. - * INVALID_SECTOR - * SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION - * BUSY - * - **********************************************************************/ -IAP_STATUS_CODE EraseSector(uint32_t start_sec, uint32_t end_sec) -{ - IAP_COMMAND_Type command; - IAP_STATUS_CODE status; - - // Prepare sectors - status = PrepareSector(start_sec, end_sec); - if(status != CMD_SUCCESS) - return status; - - // Erase sectors - command.cmd = IAP_ERASE; // Prepare Sector for Write - command.param[0] = start_sec; // Start Sector - command.param[1] = end_sec; // End Sector - command.param[2] = CLKPWR_GetCLK(CLKPWR_CLKTYPE_CPU) / 1000; // CCLK in kHz - IAP_Call (&command.cmd, &command.status); // Call IAP Command - return (IAP_STATUS_CODE)command.status; -} - -/*********************************************************************//** - * @brief Blank check sector(s) - * - * @param[in] start_sec The number of start sector - * @param[in] end_sec The number of end sector - * @param[out] first_nblank_loc The offset of the first non-blank word - * @param[out] first_nblank_val The value of the first non-blank word - * - * @return CMD_SUCCESS. - * INVALID_SECTOR - * SECTOR_NOT_BLANK - * BUSY - * - **********************************************************************/ -IAP_STATUS_CODE BlankCheckSector(uint32_t start_sec, uint32_t end_sec, - uint32_t *first_nblank_loc, - uint32_t *first_nblank_val) -{ - IAP_COMMAND_Type command; - - command.cmd = IAP_BLANK_CHECK; // Prepare Sector for Write - command.param[0] = start_sec; // Start Sector - command.param[1] = end_sec; // End Sector - IAP_Call (&command.cmd, &command.status); // Call IAP Command - - if(command.status == SECTOR_NOT_BLANK) - { - // Update out value - if(first_nblank_loc != NULL) - *first_nblank_loc = command.result[0]; - if(first_nblank_val != NULL) - *first_nblank_val = command.result[1]; - } - - return (IAP_STATUS_CODE)command.status; -} - -/*********************************************************************//** - * @brief Read part identification number - * - * @param[out] partID Part ID - * - * @return CMD_SUCCESS - * - **********************************************************************/ -IAP_STATUS_CODE ReadPartID(uint32_t *partID) -{ - IAP_COMMAND_Type command; - command.cmd = IAP_READ_PART_ID; - IAP_Call (&command.cmd, &command.status); // Call IAP Command - - if(command.status == CMD_SUCCESS) - { - if(partID != NULL) - *partID = command.result[0]; - } - - return (IAP_STATUS_CODE)command.status; -} - -/*********************************************************************//** - * @brief Read boot code version. The version is interpreted as .. - * - * @param[out] major The major - * @param[out] minor The minor - * - * @return CMD_SUCCESS - * - **********************************************************************/ -IAP_STATUS_CODE ReadBootCodeVer(uint8_t *major, uint8_t* minor) -{ - IAP_COMMAND_Type command; - command.cmd = IAP_READ_BOOT_VER; - IAP_Call (&command.cmd, &command.status); // Call IAP Command - - if(command.status == CMD_SUCCESS) - { - if(major != NULL) - *major = (command.result[0] >> 8) & 0xFF; - if(minor != NULL) - *minor = (command.result[0]) & 0xFF; - } - - return (IAP_STATUS_CODE)command.status; -} - -/*********************************************************************//** - * @brief Read Device serial number. - * - * @param[out] uid Serial number. - * - * @return CMD_SUCCESS - * - **********************************************************************/ -IAP_STATUS_CODE ReadDeviceSerialNum(uint32_t *uid) -{ - IAP_COMMAND_Type command; - command.cmd = IAP_READ_SERIAL_NUMBER; - IAP_Call (&command.cmd, &command.status); // Call IAP Command - - if(command.status == CMD_SUCCESS) - { - if(uid != NULL) - { - uint32_t i = 0; - for(i = 0; i < 4; i++) - uid[i] = command.result[i]; - } - } - - return (IAP_STATUS_CODE)command.status; -} - -/*********************************************************************//** - * @brief compare the memory contents at two locations. - * - * @param[in] addr1 The address of the 1st buffer (in RAM/Flash). - * @param[in] addr2 The address of the 2nd buffer (in RAM/Flash). - * @param[in] size Number of bytes to be compared; should be a multiple of 4. - * - * @return CMD_SUCCESS - * COMPARE_ERROR - * COUNT_ERROR (Byte count is not a multiple of 4) - * ADDR_ERROR - * ADDR_NOT_MAPPED - * - **********************************************************************/ -IAP_STATUS_CODE Compare(uint8_t *addr1, uint8_t *addr2, uint32_t size) -{ - IAP_COMMAND_Type command; - command.cmd = IAP_COMPARE; - command.param[0] = (uint32_t)addr1; - command.param[1] = (uint32_t)addr2; - command.param[2] = size; - IAP_Call (&command.cmd, &command.status); // Call IAP Command - - return (IAP_STATUS_CODE)command.status; -} - -/*********************************************************************//** - * @brief Re-invoke ISP. - * - * @param[in] None. - * - * @return None. - * - **********************************************************************/ -void InvokeISP(void) -{ - IAP_COMMAND_Type command; - command.cmd = IAP_REINVOKE_ISP; - IAP_Call (&command.cmd, &command.status); // Call IAP Command -} - -/** - * @} - */ - - -#endif /*_IAP*/ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_lcd.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_lcd.c deleted file mode 100644 index ea2f6b5cdbb..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_lcd.c +++ /dev/null @@ -1,856 +0,0 @@ -/********************************************************************** -* $Id$ lpc_lcd.c 2011-10-14 -*//** -* @file lpc_lcd.c -* @brief Contains all functions support for LCD firmware library -* on LPC -* @version 1.0 -* @date 14. October. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _LCD - -#include "lpc_clkpwr.h" -#include "lpc_pinsel.h" -#include "lpc_gpio.h" -#include "lpc_lcd.h" - -uint32_t lcd_hsize = 0, lcd_vsize = 0; -uint32_t lcd_cursor_base_addr = 0; -uint32_t lcd_cursor_size = 64; -LCD_Config_Type lcd_config; -static uint8_t bits_per_pixel[] = { 1, 2, 4, 8, 16, 32, 16, 16 }; -uint32_t rect[1024]; - - -static void LCD_SetHorizontalTiming(LCD_HConfig_Type* pConfig); -static void LCD_SetVertialTiming(LCD_VConfig_Type* pConfig); -static void LCD_SetPolarity(LCD_TYPES lcd_type, LCD_POLARITY_Type* pConfig); -static void LCD_CtrlSetup(LCD_Config_Type* pConfig); - -/** @addtogroup LCD_Private_Functions LCD Private Function - * @ingroup LCD - * @{ - */ - - -/*********************************************************************//** - * @brief Init LCD. The input clock is CClk - * - * @param[in] pConfig Configuration Information - * - * @return LCD_FUNC_OK Execute successfully - * LCD_FUNC_ERR Error occurred. - * - **********************************************************************/ -LCD_RET_CODE LCD_Init (LCD_Config_Type* pConfig) -{ - uint8_t clkdiv; - - if(pConfig == NULL) - return LCD_FUNC_ERR; - - if(pConfig->big_endian_byte & !pConfig->big_endian_pixel) - return LCD_FUNC_ERR; - - lcd_config = *pConfig; - - // Assign pins - PINSEL_ConfigPin(0,4,7); - PINSEL_ConfigPin(0,5,7); - PINSEL_ConfigPin(0,6,7); - PINSEL_ConfigPin(0,7,7); - PINSEL_ConfigPin(0,8,7); - PINSEL_ConfigPin(0,9,7); - PINSEL_ConfigPin(1,20,7); - PINSEL_ConfigPin(1,21,7); - PINSEL_ConfigPin(1,22,7); - PINSEL_ConfigPin(1,23,7); - PINSEL_ConfigPin(1,24,7); - PINSEL_ConfigPin(1,25,7); - PINSEL_ConfigPin(1,26,7); - PINSEL_ConfigPin(1,27,7); - PINSEL_ConfigPin(1,28,7); - PINSEL_ConfigPin(1,29,7); - PINSEL_ConfigPin(2,0,7); - PINSEL_ConfigPin(2,1,7); - PINSEL_ConfigPin(2,2,7); - PINSEL_ConfigPin(2,3,7); - PINSEL_ConfigPin(2,4,7); - PINSEL_ConfigPin(2,5,7); - PINSEL_ConfigPin(2,6,7); -#ifdef CORE_M4 - PINSEL_ConfigPin(0,10,7); -#else - PINSEL_ConfigPin(2,7,7); -#endif - PINSEL_ConfigPin(2,8,7); - PINSEL_ConfigPin(2,9,7); - PINSEL_ConfigPin(2,11,7); - PINSEL_ConfigPin(2,12,7); - PINSEL_ConfigPin(2,13,7); - PINSEL_ConfigPin(4,28,7); - PINSEL_ConfigPin(4,29,7); - - //Turn on LCD clock - CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCLCD, ENABLE); - - // Set clock - LPC_LCD->POL &= ~(0x01 << 5); - if( pConfig->panel_clk > 0) { - clkdiv = CLKPWR_GetCLK(CLKPWR_CLKTYPE_CPU) / pConfig->panel_clk - 1; - LPC_SC->LCD_CFG = clkdiv & 0x1F; - LPC_LCD->POL |=(1<<26); - } - - // init Horizontal Timing - LCD_SetHorizontalTiming(&pConfig->hConfig); - - // Init Vertical Timing - LCD_SetVertialTiming(&pConfig->vConfig); - - // Set Polarity - LCD_SetPolarity(pConfig->lcd_type, &pConfig->polarity); - - if(NULL != pConfig->lcd_palette) - { - LCD_SetPalette(pConfig->lcd_palette); - } - - // Set Base address - LCD_SetBaseAddress(LCD_PANEL_UPPER, pConfig->lcd_panel_upper); - LCD_SetBaseAddress(LCD_PANEL_LOWER, pConfig->lcd_panel_lower); - - // Setup - LCD_CtrlSetup(pConfig); - - return LCD_FUNC_OK; - - -} -/*********************************************************************//** - * @brief Horizontal Timing Setting - * - * @param[in] pConfig Configuration Information - * - * @return None. - * - **********************************************************************/ -void LCD_SetHorizontalTiming(LCD_HConfig_Type* pConfig) -{ - LPC_LCD->TIMH = 0; //reset TIMH before set value - LPC_LCD->TIMH |= ((pConfig->hbp - 1)& 0xFF)<<24; - LPC_LCD->TIMH |= ((pConfig->hfp - 1)& 0xFF)<<16; - LPC_LCD->TIMH |= ((pConfig->hsw - 1)& 0xFF)<<8; - LPC_LCD->TIMH |= ((pConfig->ppl/16 - 1)& 0x3F)<<2; - lcd_hsize = pConfig->ppl; -} - -/*********************************************************************//** - * @brief Vertical Timing Setting - * - * @param[in] pConfig Configuration Information - * - * @return None. - * - **********************************************************************/ -void LCD_SetVertialTiming(LCD_VConfig_Type* pConfig) -{ - LPC_LCD->TIMV = 0; //reset TIMV value before setting - LPC_LCD->TIMV |= ((pConfig->vbp)& 0xFF)<<24; - LPC_LCD->TIMV |= ((pConfig->vfp)& 0xFF)<<16; - LPC_LCD->TIMV |= ((pConfig->vsw - 1)& 0x3F)<<10; - LPC_LCD->TIMV |= ((pConfig->lpp - 1)& 0x03FF)<<0; - lcd_vsize = pConfig->lpp; -} - -/*********************************************************************//** - * @brief Polarity Setting - * - * @param[in] pConfig Configuration Information - * @param[in] lcd_type It can be: - * - LCD_STN_MONOCHROME - * - LCD_STN_COLOR - * - LCD_TFT - * - * @return None. - * - **********************************************************************/ -void LCD_SetPolarity(LCD_TYPES lcd_type, LCD_POLARITY_Type* pConfig) -{ - // LCDFP pin is active LOW and inactive HIGH - if(pConfig->invert_vsync) - LPC_LCD->POL |= (1<<11); - else - LPC_LCD->POL &= ~(1<<11); - // LCDLP pin is active LOW and inactive HIGH - if(pConfig->invert_hsync) - LPC_LCD->POL |= (1<<12); - else - LPC_LCD->POL &= ~(1<<12); - // data is driven out into the LCD on the falling edge - if(pConfig->invert_panel_clock) - LPC_LCD->POL |= (1<<13); - else - LPC_LCD->POL &= ~(1<<13); - - // active high - if(pConfig->active_high) { - LPC_LCD->POL &= ~(1<<14); - } - else - { - LPC_LCD->POL |= (1<<14); - } - - LPC_LCD->POL &= ~(0x3FF <<16); - LPC_LCD->POL |= (pConfig->cpl - 1)<<16; - - if(lcd_type == LCD_STN_COLOR || lcd_type == LCD_STN_MONOCHROME) - LPC_LCD->POL |= (pConfig->acb & 0x1F) << 6; - } - -/*********************************************************************//** - * @brief Set base address of frame buffer - * - * @param[in] panel identify which panel is. - * @param[in] pAddress base address of the inputted panel. - * - * @return None. - * - **********************************************************************/ -void LCD_SetBaseAddress(LCD_PANEL panel, uint32_t pAddress) -{ - // Frame Base Address doubleword aligned - if(panel == LCD_PANEL_UPPER) - LPC_LCD->UPBASE = pAddress & ~7UL ; - else - LPC_LCD->LPBASE = pAddress & ~7UL ; -} - -/*********************************************************************//** - * @brief LCD Setup. - * - * @param[in] pConfig Configuration information. - * - * @return None. - * - **********************************************************************/ -void LCD_CtrlSetup(LCD_Config_Type* pConfig) -{ - // disable LCD controller - LPC_LCD->CTRL = 0; - - // bpp - LPC_LCD->CTRL &= ~(0x07 <<1); - LPC_LCD->CTRL |=((pConfig->lcd_bpp & 0x07)<<1); - - if(pConfig->lcd_type == LCD_TFT) { - LPC_LCD->CTRL |= (0x01 << 5); // TFT - } - else { - // Color/Mono - if(pConfig->lcd_type == LCD_STN_COLOR) { - LPC_LCD->CTRL &= ~ (0x01 << 4); // Color - } - else if (pConfig->lcd_type == LCD_STN_MONOCHROME) { - LPC_LCD->CTRL |= (0x01 << 4); // Mono - } - - // STN/TFT - LPC_LCD->CTRL &= ~ (0x01 << 5); // STN - - // Mono4/8 - if(pConfig->lcd_mono8) - LPC_LCD->CTRL |= (0x01 << 6); - else - LPC_LCD->CTRL &= ~(0x01 << 6); - - // Single/dual - if(pConfig->lcd_dual) - LPC_LCD->CTRL |= (0x01 << 7); - else - LPC_LCD->CTRL &= ~(0x01 << 7); - } - - // notmal output - if(pConfig->lcd_bgr) - LPC_LCD->CTRL |= (1<<8); // BGR - else - LPC_LCD->CTRL &= ~(1<<8); // RGB - - // Byte order - if(pConfig->big_endian_byte) - LPC_LCD->CTRL |= (1<<9); - else - LPC_LCD->CTRL &= ~(1<<9); - - // Pixel order - if(pConfig->big_endian_pixel) - LPC_LCD->CTRL |= (1<<10); - else - LPC_LCD->CTRL &= ~(1<<10); - - // disable power - LPC_LCD->CTRL &= ~(1<<11); -} - -/*********************************************************************//** - * @brief Enable/disable LCD Display. - * - * @param[in] bEna 0: disable, 1: enable. - * - * @return None. - * - **********************************************************************/ -void LCD_Enable (Bool bEna) -{ - volatile uint32_t i; - if (bEna) - { - LPC_LCD->CTRL |= (1<<0); - for(i = LCD_PWR_ENA_DIS_DLY; i; i--); - LPC_LCD->CTRL |= (1<<11); - } - else - { - LPC_LCD->CTRL &= ~(1<<11); - for(i = LCD_PWR_ENA_DIS_DLY; i; i--); - LPC_LCD->CTRL &= ~(1<<0); - } -} - - -/*********************************************************************//** - * @brief Set palette. - * - * @param[in] bEna 0: disable, 1: enable. - * - * @return None. - * - **********************************************************************/ -void LCD_SetPalette (const uint8_t* pPallete) -{ - uint32_t i; - uint32_t size = (0x01 << bits_per_pixel[lcd_config.lcd_bpp])/2 ; - uint32_t * pDst = (uint32_t *)LPC_LCD->PAL; - uint32_t * pInput = (uint32_t*) pPallete; - - for (i = 0; i < size; i++) - { - *pDst = *pInput; - pDst++; - pInput++; - } -} -/*********************************************************************//** - * @brief Get word offset for the given pixel - * - * @param[in] x x position of input pixel - * @param[in] y y position of input pixel - * - * @return Offset - * - **********************************************************************/ -uint32_t LCD_GetWordOffset(uint32_t x, uint32_t y) -{ - uint32_t pixel_num = x + y*lcd_hsize; - - return (pixel_num * bits_per_pixel[lcd_config.lcd_bpp])/32; -} -/*********************************************************************//** - * @brief Get bit offset for the given pixel - * - * @param[in] x x position of input pixel - * @param[in] y y position of input pixel - * - * @return Offset - * - **********************************************************************/ -uint32_t LCD_GetBitOffset(uint32_t x, uint32_t y) -{ - uint32_t pixel_num; - uint32_t ofs; - pixel_num = x + y*lcd_hsize; - - ofs = (pixel_num * bits_per_pixel[lcd_config.lcd_bpp])%32; - - if(lcd_config.big_endian_pixel & lcd_config.big_endian_byte) - { - ofs = 32 - bits_per_pixel[lcd_config.lcd_bpp] - ofs; - } - else if (lcd_config.big_endian_pixel & !lcd_config.big_endian_byte) - { - if(bits_per_pixel[lcd_config.lcd_bpp] < 8) - { - ofs = (ofs/8)*8 + (8 - (ofs%8)-bits_per_pixel[lcd_config.lcd_bpp]); - } - } - return ofs; -} - - - -/*********************************************************************//** - * @brief Copy pixel values from image buffer to frame buffer. - * - * @param[in] panel It can be: - * - LCD_PANEL_UPPER - * - LCD_PANEL_LOWER - * @param[in] pPain point to image buffer. - * - * @return None. - * - **********************************************************************/ -void LCD_SetImage(LCD_PANEL panel, const uint8_t *pPain) -{ - volatile uint32_t i; - uint32_t * pWordDst = NULL; - uint8_t* pByteDst = NULL; - uint32_t bytes_num; - - if(panel == LCD_PANEL_UPPER) - pWordDst = (uint32_t*) LPC_LCD->UPBASE; - else - pWordDst = (uint32_t*) LPC_LCD->LPBASE; - - pByteDst = (uint8_t*) pWordDst; - bytes_num = ((lcd_hsize * lcd_vsize) * bits_per_pixel[lcd_config.lcd_bpp]) /8; - - if (NULL == pPain) - { - // clear display memory - for( i = 0; bytes_num > i; i++) - { - *pByteDst++ = 0; - } - } - else - { - // set display memory - for(i = 0; bytes_num > i; i++) - { - *pByteDst++ = *pPain++; - } - } - - for(i = LCD_PWR_ENA_DIS_DLY; i; i--); -} -/*********************************************************************//** - * @brief Draw a pixel on the given panel. - * - * @param[in] panel It can be: - * - LCD_PANEL_UPPER - * - LCD_PANEL_LOWER - * @param[in] X_Left X position. - * @param[in] Y_Up Y position. - * @param[in] color Color which is placed to the given pixel. - * - * @return None. - * - **********************************************************************/ -void LCD_PutPixel (LCD_PANEL panel, uint32_t X_Left, uint32_t Y_Up, LcdPixel_t color) -{ - uint32_t k; - uint32_t * pWordData = NULL; - uint8_t* pByteData = NULL; - uint32_t bitOffset; - uint8_t* pByteSrc = (uint8_t*)&color; - uint8_t bpp = bits_per_pixel[lcd_config.lcd_bpp]; - uint8_t bytes_per_pixel = bpp/8; - uint32_t start_bit; - - if((X_Left >= lcd_hsize)||(Y_Up >= lcd_vsize)) - return; - - if(panel == LCD_PANEL_UPPER) - pWordData = (uint32_t*) LPC_LCD->UPBASE + LCD_GetWordOffset(X_Left,Y_Up); - else - pWordData = (uint32_t*) LPC_LCD->LPBASE + LCD_GetWordOffset(X_Left,Y_Up); - - bitOffset = LCD_GetBitOffset(X_Left,Y_Up); - pByteData = (uint8_t*) pWordData; - pByteData += bitOffset/8; - - start_bit = bitOffset%8; - - if(bpp < 8) - { - uint8_t bit_pos = start_bit; - uint8_t bit_ofs = 0; - for(bit_ofs = 0;bit_ofs > (k+bit_ofs)) & 0x01) << bit_pos; - } - } - else - { - for(k = 0; k < bytes_per_pixel; k++) - { - *(pByteData+ k) = *pByteSrc++; - } - } -} -/*********************************************************************//** - * @brief Place given image to given position. - * - * @param[in] panel It can be: - * - LCD_PANEL_UPPER - * - LCD_PANEL_LOWER - * @param[in] X_Left Start X position. - * @param[in] Y_Up Start Y position. - * @param[in] pBmp Image information. - * @param[in] Mask Mask on pixel values. - * - * @return None. - * - **********************************************************************/ -void LCD_LoadPic (LCD_PANEL panel, uint32_t X_Left, uint32_t Y_Up, - Bmp_t * pBmp, uint32_t Mask) -{ - uint32_t i, j, k, inc; - uint32_t * pWordData = NULL; - uint8_t* pByteData = NULL; - uint32_t bitOffset; - uint8_t* pByteSrc = (uint8_t*) pBmp->pPicStream; - uint32_t X_LeftHold = X_Left; - uint8_t bpp = bits_per_pixel[lcd_config.lcd_bpp]; - uint8_t bytes_per_pixel = bpp/8; - uint8_t pixels_per_byte = 8/bpp; - uint32_t hsize, vsize; - uint32_t start_bit; - - if(pBmp->BytesPP == 0) - pBmp->BytesPP = bytes_per_pixel; - - hsize = pBmp->H_Size; - vsize = pBmp->V_Size; - inc = (pixels_per_byte > 0) ? pixels_per_byte:1; - - for(i = 0; i < vsize; i++) - { - if(panel == LCD_PANEL_UPPER) - pWordData = (uint32_t*) LPC_LCD->UPBASE + LCD_GetWordOffset(X_Left,Y_Up); - else - pWordData = (uint32_t*) LPC_LCD->LPBASE + LCD_GetWordOffset(X_Left,Y_Up); - - bitOffset = LCD_GetBitOffset(X_Left,Y_Up); - pByteData = (uint8_t*) pWordData; - pByteData += bitOffset/8; - - start_bit = bitOffset%8; - - if(pBmp->BytesPP > 0) - pByteSrc = (uint8_t*) pBmp->pPicStream + i*hsize*pBmp->BytesPP; // storage of each line must be word alignment - else - pByteSrc = (uint8_t*) pBmp->pPicStream + (i*hsize*pBmp->BitsPP + 7)/8; // storage of each line must be word alignment - - X_LeftHold = X_Left; - - for(j = 0; j <= hsize; j+= inc) - { - if((X_LeftHold >= lcd_hsize) || (X_LeftHold - X_Left >= hsize)) - break; - if(bpp < 8) - { - uint8_t bit_pos = start_bit; - uint8_t bit_ofs = 0; - for(k = 0; k < 8; k+= bpp) - { - for(bit_ofs = 0;bit_ofs > (k+bit_ofs)) & 0x01) << bit_pos; - } - if(lcd_config.big_endian_byte && lcd_config.big_endian_pixel) - { - if(bit_pos >= bpp*2) - bit_pos -= bpp*2; - else - { - bit_pos = 8-bpp; - if((((uint32_t)pByteData)%4) == 0) - pByteData += 7; // change to next word - else - pByteData--; // change to previous byte - } - } - else if( !lcd_config.big_endian_byte && lcd_config.big_endian_pixel) - { - if(bit_pos >= bpp*2) - bit_pos -= bpp*2; - else - { - bit_pos = 8-bpp; - pByteData++; // change to next byte - } - } - else - { - if(bit_pos >= 8) - { - bit_pos = 0; - pByteData++; // change to next byte - } - - } - X_LeftHold++; - if((X_LeftHold >= lcd_hsize) || - (X_LeftHold - X_Left >= hsize)) - break; - } - pByteSrc++; - continue; - } - else - { - for(k = 0; k < pBmp->BytesPP; k++) - { - *(pByteData+ k) = *pByteSrc++ ^ Mask; - } - if(lcd_config.big_endian_byte) - { - if((uint32_t)pByteData %4 > 0) - pByteData -= bytes_per_pixel; - else - pByteData += 8 - bytes_per_pixel; - } - else - pByteData+= bytes_per_pixel; - X_LeftHold++; - } - } - if(Y_Up++ >= lcd_vsize) - { - break; - } - } -} - -/*********************************************************************//** - * @brief Fill a rectangle. - * - * @param[in] panel It can be: - * - LCD_PANEL_UPPER - * - LCD_PANEL_LOWER - * @param[in] startx Start X position. - * @param[in] endy End X position. - * @param[in] starty Start Y position. - * @param[in] endy End Y position. - * - * @return None. - * - **********************************************************************/ -void LCD_FillRect (LCD_PANEL panel, uint32_t startx,uint32_t endx, - uint32_t starty, uint32_t endy, - LcdPixel_t color) -{ - uint32_t x, xs, xe, ys, ye; - uint8_t bpp, pixels_per_word; - uint32_t word_val, mask; - uint32_t max_vsize = 0; - Bmp_t bitmap; - uint32_t hsize, vsize; - - bpp = bits_per_pixel[lcd_config.lcd_bpp]; - pixels_per_word = 32/bpp; - - mask = 0; - for( x = 0; x < bpp; x++) - mask |= 0x01 << x; - - color &= mask; - - word_val = 0; - for(x = 0; x < pixels_per_word; x++) - word_val |= color << (x*bpp); - - ys = (starty > endy) ? endy : starty; - ye = (starty > endy) ? starty : endy; - - xs = (startx > endx) ? endx : startx; - xe = (startx > endx) ? startx : endx; - - bitmap.BitsPP = bpp; - bitmap.BytesPP = bpp/8; - hsize = xe - xs + 1; - bitmap.H_Size = hsize; - vsize = ye - ys + 1; - bitmap.pPicStream = (uint8_t*)rect; - - max_vsize = ((1024 * 32)/(hsize*bpp)); - - for( x = 0; x < 1024; x++) - { - rect[x] = word_val; - } - - while(1) - { - if(max_vsize >= vsize) - { - bitmap.V_Size = vsize; - LCD_LoadPic(panel,xs,ys, &bitmap, 0); - break; - } - else { - bitmap.V_Size = max_vsize; - vsize -= bitmap.V_Size; - LCD_LoadPic(panel,xs,ys, &bitmap, 0); - ys += max_vsize; - } - } - - -} - -/*********************************************************************//** - * @brief Configure display of cursor. - * - * @param[in] pConfig Configuration information. - * - * @return None. - * - **********************************************************************/ -void LCD_Cursor_Cfg(LCD_Cursor_Config_Type* pConfig) -{ - if(pConfig->size32) { - LPC_LCD->CRSR_CFG &= ~(0x01 << 0); - lcd_cursor_size = 32; - } - else { - LPC_LCD->CRSR_CFG |= (0x01 << 0); - lcd_cursor_size = 64; - } - - if(pConfig->framesync) - LPC_LCD->CRSR_CFG &= ~(0x01 << 1); - else - LPC_LCD->CRSR_CFG |= (0x01 << 1); - - lcd_cursor_base_addr = pConfig->baseaddress; - - LPC_LCD->CRSR_PAL0 = pConfig->palette[0].Red | - pConfig->palette[0].Green << 8 | - pConfig->palette[0].Blue << 16; - LPC_LCD->CRSR_PAL1 = pConfig->palette[1].Red | - pConfig->palette[1].Green << 8 | - pConfig->palette[1].Blue << 16; - -} -/*********************************************************************//** - * @brief Enable/disable cursor display. - * - * @param[in] enable 0: disable, 1: enable. - * @param[in] cursor identify which cursor image is used. - * - * @return None. - * - **********************************************************************/ -void LCD_Cursor_Enable(int enable, int cursor) -{ - if(enable) { - LPC_LCD->CRSR_CTRL |= (1<<0); - LPC_LCD->CRSR_CTRL |= (cursor<<4); - } - else { - LPC_LCD->CRSR_CTRL &= ~(1<<0); - } -} - - -/*********************************************************************//** - * @brief move the cursor to the inputted position. - * - * @param[in] x Position in x-direction. - * @param[in] y Position in y-direction. - * - * @return None. - * - **********************************************************************/ -void LCD_Move_Cursor(int x, int y) -{ - LPC_LCD->CRSR_CLIP = 0; - LPC_LCD->CRSR_XY = 0; - if(0 <= x) - {//no clipping - LPC_LCD->CRSR_XY |= (x & 0x3FF); - } - else - {//clip x - LPC_LCD->CRSR_CLIP |= -x; - } - - if(0 <= y) - {//no clipping - - LPC_LCD->CRSR_XY |= (y << 16); - } - else - {//clip y - LPC_LCD->CRSR_CLIP |= (-y << 8); - } -} - -/*********************************************************************//** - * @brief Set the cursor image. - * - * @param[in] pCursor point to cursor image. - * @param[in] cursor cursor image number. It has no meaning when cursor size is 64x64 - * @param[in] cursor cursor size in words. - * - * @return None. - * - **********************************************************************/ -void LCD_Cursor_SetImage (const uint32_t *pCursor, int cursor, int size) -{ - uint32_t i ; - uint32_t * pDst = (uint32_t *)lcd_cursor_base_addr; - - if(lcd_cursor_size == 32) - pDst += cursor*GET_CURSOR_IMG_SIZE(lcd_cursor_size); - - - for(i = 0; i < size ; i++) - { - *pDst = *pCursor; - pDst++; - pCursor++; - } -} - -/** - * @} - */ - -#endif /*_LCD*/ - - - diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_mci.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_mci.c deleted file mode 100644 index 813d599be29..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_mci.c +++ /dev/null @@ -1,2508 +0,0 @@ -/********************************************************************** -* $Id$ lpc_mci.c 2011-06-02 -*//** -* @file lpc_mci.c -* @brief Contains all functions support for MCI firmware library -* on LPC -* @version 2.0 -* @date 29. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _MCI - -#include "LPC407x_8x_177x_8x.h" -#include "lpc_types.h" -#include "lpc_mci.h" -#include "lpc_gpdma.h" -#include "lpc_clkpwr.h" -#include "lpc_pinsel.h" - -#define DMA_MCI_SIZE BLOCK_LENGTH - -#define MCI_DMA_WRITE_CHANNEL (0) -#define MCI_DMA_READ_CHANNEL (1) - -#define _SHIFT(x) (1 << x) -#define _XSHIFT(x, y) (x << y) - -#define SHIFT_(x) (1 >> x) -#define XSHIFT_(x, y) (x >> y) - -#define MCI_ACMD41_HCS_POS (30) - -#define MCI_PWRCTRL_BMASK (0xC3) - -#define MCI_PWRCTRL_OPENDRAIN_POS (6) -#define MCI_PWRCTRL_OPENDRAIN_NUMBIT (1) -#define MCI_PWRCTRL_OPENDRAIN_BMASK (0x01) - - -volatile uint32_t Mci_Data_Xfer_End = 0; - -volatile uint32_t Mci_Data_Xfer_ERR = 0; - -volatile uint8_t fifo_plane = 0; - -volatile uint32_t CardRCA; - -volatile uint8_t CCS; - -volatile en_Mci_CardType MCI_CardType; - -// Terminal Counter flag, Error Counter flag for Channel 0 -uint32_t dmaWrCh_TermianalCnt, dmaWrCh_ErrorCnt; -uint32_t dmaRdCh_TermianalCnt, dmaRdCh_ErrorCnt; - - -uint32_t MCI_SettingDma(uint8_t* memBuf, uint32_t ChannelNum, uint32_t DMAMode ); - -int32_t MCI_ReadFifo(uint32_t * dest); -int32_t MCI_WriteFifo(uint32_t * src); - -void MCI_TXEnable( void ); -void MCI_RXEnable( void ); -void MCI_TXDisable( void ); -void MCI_RXDisable( void ); - -void MCI_CmdProcess( void ); -void MCI_DataErrorProcess( void ); -void MCI_DataErrorProcess( void ); -void MCI_DATA_END_InterruptService( void ); -void MCI_FIFOInterruptService( void ); - -int32_t MCI_CheckStatus(uint8_t expect_status); - - - -volatile uint8_t* dataSrcBlock = (uint8_t *) MCI_DMA_SRC_ADDR; -volatile uint8_t* dataDestBlock = (uint8_t *) MCI_DMA_DST_ADDR; - -volatile uint32_t txBlockCnt=0, rxBlockCnt=0; - -/** @addtogroup MCI_Private_Functions MCI Private Function - * @ingroup MCI - * @{ - */ - -#if MCI_DMA_ENABLED -/*********************************************************************//** - * @brief Do setting GPDMA for MCI working - * - * @param[in] DMAMode set for the Type of DMA Transfer. It may be memory - * to peripheral (M2P) or peripheral to memory (P2M) - * in MCI working - * - * @param[in] ChannelNum which channel is used for current transfer with - * DMA compent - * - * @param[in] memBuf point to a UINT8 buffer. In 2 cases of DMAMode - * seperated: - * - M2P: it is the source address that hold the - * expected buffer to transfer - * - P2M: it is the destination address that will store - * data that retrieved from the peripheral (the Card in slot) - * - * @return None - * - * @note This is only required if DMA support is enabled - **********************************************************************/ -uint32_t MCI_SettingDma(uint8_t* memBuf, uint32_t ChannelNum, uint32_t DMAMode ) -{ - GPDMA_Channel_CFG_Type GPDMACfg; - - // Transfer size - GPDMACfg.TransferSize = DMA_MCI_SIZE; - // Transfer width - GPDMACfg.TransferWidth = GPDMA_WIDTH_WORD; - // Transfer type - GPDMACfg.TransferType = DMAMode; - // Linker List Item - unused - GPDMACfg.DMALLI = 0; - - /* USB RAM is used for test. - Please note, Ethernet has its own SRAM, but GPDMA can't access - that. GPDMA can access USB SRAM and IRAM. Ethernet DMA controller can - access both IRAM and Ethernet SRAM. */ - GPDMACfg.ChannelNum = ChannelNum; - - if ( DMAMode == GPDMA_TRANSFERTYPE_M2P_DEST_CTRL ) - { - /* Ch0 set for M2P transfer from mempry to MCI FIFO. */ - // Source memory - GPDMACfg.SrcMemAddr = (uint32_t)memBuf; - // Destination memory - GPDMACfg.DstMemAddr = (uint32_t)LPC_MCI->FIFO; - - // Source connection - GPDMACfg.SrcConn = 0; - // Destination connection - GPDMACfg.DstConn = GPDMA_CONN_MCI; - - } - else if ( DMAMode == GPDMA_TRANSFERTYPE_P2M_SRC_CTRL ) - { - /* Ch0 set for P2M transfer from MCI FIFO to memory. */ - // Source memory - GPDMACfg.SrcMemAddr = (uint32_t)LPC_MCI->FIFO; - // Destination memory - GPDMACfg.DstMemAddr = (uint32_t)memBuf; - - // Source connection - GPDMACfg.SrcConn = GPDMA_CONN_MCI; - // Destination connection - GPDMACfg.DstConn = 0; - } - else - { - return ( FALSE ); - } - - // Setup channel with given parameter - GPDMA_Setup(&GPDMACfg); - - // Enable GPDMA channel - GPDMA_ChannelCmd(ChannelNum, ENABLE); - - /* Enable GPDMA interrupt */ - NVIC_EnableIRQ(DMA_IRQn); - - return (TRUE); -} - - -/*********************************************************************//** - * @brief GPDMA interrupt handler sub-routine - * - * @param None - * - * @return None - * - * @note This is only executed if DMA support is enabled - **********************************************************************/ -void MCI_DMA_IRQHandler (void) -{ - // check GPDMA interrupt on channel 0 - if (GPDMA_IntGetStatus(GPDMA_STAT_INT, MCI_DMA_WRITE_CHANNEL)) - { - //check interrupt status on channel 0 - // Check counter terminal status - if(GPDMA_IntGetStatus(GPDMA_STAT_INTTC, MCI_DMA_WRITE_CHANNEL)) - { - // Clear terminate counter Interrupt pending - GPDMA_ClearIntPending (GPDMA_STATCLR_INTTC, MCI_DMA_WRITE_CHANNEL); - - dmaWrCh_TermianalCnt++; - } - if (GPDMA_IntGetStatus(GPDMA_STAT_INTERR, MCI_DMA_WRITE_CHANNEL)) - { - // Clear error counter Interrupt pending - GPDMA_ClearIntPending (GPDMA_STATCLR_INTERR, MCI_DMA_WRITE_CHANNEL); - - dmaWrCh_ErrorCnt++; - } - } - else if (GPDMA_IntGetStatus(GPDMA_STAT_INT, MCI_DMA_READ_CHANNEL)) - { - //check interrupt status on channel 0 - // Check counter terminal status - if(GPDMA_IntGetStatus(GPDMA_STAT_INTTC, MCI_DMA_READ_CHANNEL)) - { - // Clear terminate counter Interrupt pending - GPDMA_ClearIntPending (GPDMA_STATCLR_INTTC, MCI_DMA_READ_CHANNEL); - - dmaRdCh_TermianalCnt++; - } - if (GPDMA_IntGetStatus(GPDMA_STAT_INTERR, MCI_DMA_READ_CHANNEL)) - { - // Clear error counter Interrupt pending - GPDMA_ClearIntPending (GPDMA_STATCLR_INTERR, MCI_DMA_READ_CHANNEL); - - dmaRdCh_ErrorCnt++; - } - } -} -#endif - - -/*********************************************************************//** - * @brief Read data from FIFO (after a transmission with card) to - * a destination buffer - * - * @param[in] *dest The buffer to store the data that read from card - * - * @return MCI_FUNC_OK - *************************************************************************/ -int32_t MCI_ReadFifo(uint32_t * dest) -{ - uint8_t i; - uint8_t start, end; - - if(fifo_plane == 0) - { - start = 0; - end = 7; - } - else - { - start = 8; - end = 15; - } - fifo_plane = (fifo_plane) ? 0:1; - - for (i = start; i <= end; i++) - { - *dest = LPC_MCI->FIFO[i]; - - dest++; - } - - return MCI_FUNC_OK; -} - - -/*********************************************************************//** - * @brief Write data from a source buffer to FIFO for transmission - * - * @param[in] *src The buffer hold the data need to write to card - * - * @return MCI_FUNC_OK - *************************************************************************/ -int32_t MCI_WriteFifo(uint32_t * src) -{ - uint8_t i; - uint8_t start, end; - - if(fifo_plane == 0) - { - start = 0; - end = 7; - } - else - { - start = 8; - end = 15; - } - fifo_plane = (fifo_plane) ? 0:1; - - for (i = start; i <= end; i++) - { - LPC_MCI->FIFO[i] = *src; - - src++; - } - - return MCI_FUNC_OK; -} - - -/*********************************************************************//** - * @brief Enable Transmit data interrupt - * - * @param None - * - * @return None - *************************************************************************/ -void MCI_TXEnable( void ) -{ -#if MCI_DMA_ENABLED - LPC_MCI->MASK0 |= ((DATA_END_INT_MASK)|(ERR_TX_INT_MASK)); /* Enable TX interrupts only */ -#else - LPC_MCI->MASK0 |= ((FIFO_TX_INT_MASK)|(DATA_END_INT_MASK)|(ERR_TX_INT_MASK)); /* FIFO TX interrupts only */ -#endif - - return; -} - - -/*********************************************************************//** - * @brief Disable Transmit data interrupt - * - * @param None - * - * @return None - *************************************************************************/ -void MCI_TXDisable( void ) -{ -#if MCI_DMA_ENABLED - LPC_MCI->MASK0 &= ~((DATA_END_INT_MASK)|(ERR_TX_INT_MASK)); /* Enable TX interrupts only */ -#else - LPC_MCI->MASK0 &= ~((FIFO_TX_INT_MASK)|(DATA_END_INT_MASK)|(ERR_TX_INT_MASK)); /* FIFO TX interrupts only */ -#endif - - return; -} - - -/*********************************************************************//** - * @brief Enable Receive data interrupt - * - * @param None - * - * @return None - *************************************************************************/ -void MCI_RXEnable( void ) -{ -#if MCI_DMA_ENABLED - LPC_MCI->MASK0 |= ((DATA_END_INT_MASK)|(ERR_RX_INT_MASK)); /* Enable RX interrupts only */ -#else - LPC_MCI->MASK0 |= ((FIFO_RX_INT_MASK)|(DATA_END_INT_MASK)|(ERR_RX_INT_MASK)); /* FIFO RX interrupts only */ -#endif - - return; -} - - -/*********************************************************************//** - * @brief Disable Receive data interrupt - * - * @param None - * - * @return None - *************************************************************************/ -void MCI_RXDisable( void ) -{ -#if MCI_DMA_ENABLED - LPC_MCI->MASK0 &= ~((DATA_END_INT_MASK)|(ERR_RX_INT_MASK)); /* Enable TX interrupts only */ -#else - LPC_MCI->MASK0 &= ~((FIFO_RX_INT_MASK)|(DATA_END_INT_MASK)|(ERR_RX_INT_MASK)); /* FIFO TX interrupts only */ -#endif - - return; -} - -/*********************************************************************//** - * @brief Check if the card is in the given state. - *@param expect_status expected status - * @details Continuously get the card status until the card is ready. if its status matches - * with the given state, return with success. Else, return MCI_FUNC_ERR_STATE. - * If the card is still not ready, return MCI_FUNC_NOT_READY. - * - * @param None - * - * @return MCI_FUNC_OK if all success - *************************************************************************/ -int32_t MCI_CheckStatus(uint8_t expect_status) -{ - int32_t respValue, retval = MCI_FUNC_FAILED; - uint32_t retryCnt = 0xFFFF, i; - while (retryCnt > 0) - { - if (MCI_GetCardStatus(&respValue) != MCI_FUNC_OK) - { - break; - } - else - { - /* The only valid state is TRANS per MMC and SD state diagram. - RCV state may be seen, but, it happens only when TX_ACTIVE or - RX_ACTIVE occurs before the WRITE_BLOCK and READ_BLOCK cmds are - being sent, which is not a valid sequence. */ - if(!(respValue & CARD_STATUS_READY_FOR_DATA )) - { - retval = MCI_FUNC_NOT_READY; - } - else if(CARDSTATEOF(respValue) != expect_status) - { - // If card is in prg state, wait until it changes to trans state - // when "operation complete" - if(CARDSTATEOF(respValue) != CARD_STATE_PRG) - { - return MCI_FUNC_ERR_STATE; - } - } - else - { - return MCI_FUNC_OK; - } - } - retryCnt--; - for(i = 0; i < 0x20; i++); - - } - - return retval; -} - - -/*********************************************************************//** - * @brief Called by MCI interrupt handler to simplify the command - * process. - * - * @param None - * - * @return None - * - * @note In card initialization, the commnad interrupts are disabled - *************************************************************************/ -void MCI_CmdProcess( void ) -{ - uint32_t MCIStatus; - - MCIStatus = LPC_MCI->STATUS; - - if ( MCIStatus & MCI_CMD_CRC_FAIL ) - { - LPC_MCI->CLEAR = MCI_CMD_CRC_FAIL; - } - - if ( MCIStatus & MCI_CMD_TIMEOUT ) - { - LPC_MCI->CLEAR = MCI_CMD_TIMEOUT; - } - - /* Cmd Resp End or Cmd Sent */ - if ( MCIStatus & MCI_CMD_RESP_END ) - { - LPC_MCI->CLEAR = MCI_CMD_RESP_END; - } - - if ( MCIStatus & MCI_CMD_SENT ) - { - LPC_MCI->CLEAR = MCI_CMD_SENT; - } - - if ( MCIStatus & MCI_CMD_ACTIVE ) - { - LPC_MCI->CLEAR = MCI_CMD_ACTIVE; - } - - return; -} - - -/*********************************************************************//** - * @brief Called by MCI interrupt handler to manage error on the bus - * - * @param None - * - * @return None - *************************************************************************/ -void MCI_DataErrorProcess( void ) -{ - uint32_t MCIStatus; - - MCIStatus = LPC_MCI->STATUS; - - if ( MCIStatus & MCI_DATA_CRC_FAIL ) - { - LPC_MCI->CLEAR = MCI_DATA_CRC_FAIL; - } - - if ( MCIStatus & MCI_DATA_TIMEOUT ) - { - LPC_MCI->CLEAR = MCI_DATA_TIMEOUT; - } - - /* Underrun or overrun */ - if ( MCIStatus & MCI_TX_UNDERRUN ) - { - LPC_MCI->CLEAR = MCI_TX_UNDERRUN; - } - - if ( MCIStatus & MCI_RX_OVERRUN ) - { - LPC_MCI->CLEAR = MCI_RX_OVERRUN; - } - - /* Start bit error on data signal */ - if ( MCIStatus & MCI_START_BIT_ERR ) - { - LPC_MCI->CLEAR = MCI_START_BIT_ERR; - } - - Mci_Data_Xfer_End = 0; - Mci_Data_Xfer_ERR = MCIStatus; - return; -} - - -/*********************************************************************//** - * @brief Called by MCI interrupt handler. This is the last interrupt - * manipulates the process of the data-block write and read - * to/with card - * - * @details This service is also used with/without DMA support. It simply - * clears the flag messages the in-process data-block transfer - * has been done/ended - * - * @param None - * - * @return None - *************************************************************************/ -void MCI_DATA_END_InterruptService( void ) -{ - uint32_t MCIStatus; - - MCIStatus = LPC_MCI->STATUS; - if ( MCIStatus & MCI_DATA_END ) /* Data end, and Data block end */ - { - LPC_MCI->CLEAR = MCI_DATA_END; - - Mci_Data_Xfer_End = 0; - - Mci_Data_Xfer_ERR = 0; - - MCI_TXDisable(); - - MCI_RXDisable(); - - return; - } - - if ( MCIStatus & MCI_DATA_BLK_END ) - { - LPC_MCI->CLEAR = MCI_DATA_BLK_END; - - //MCI_TXDisable(); - - return; - } - - /* Tx active */ - if ( MCIStatus & MCI_TX_ACTIVE ) - { - - } - - /* Rx active */ - if ( MCIStatus & MCI_RX_ACTIVE ) - { - - } - - return; -} - - -/*********************************************************************//** - * @brief Called by MCI interrupt handler if requiring to using FIFO - * for data transferring. It copy data to/from FIFO register - * from/to a data buffer. - * - * @param None - * - * @return None - * - * @note This function is done without DMA transfer support - **********************************************************************/ -void MCI_FIFOInterruptService( void ) -{ -#if !MCI_DMA_ENABLED - uint32_t MCIStatus; - - MCIStatus = LPC_MCI->STATUS; - - if ( MCIStatus & (FIFO_TX_INT_MASK ) ) - { - /* empty is multiple of 512 block size */ - if ( MCIStatus & MCI_TX_HALF_EMPTY ) - { - //There's no data, return - if(dataSrcBlock == NULL) - return; - - /* write 8 words to fifo */ - MCI_WriteFifo((uint32_t *)&dataSrcBlock[txBlockCnt]); - - txBlockCnt += 32; - } - - if (txBlockCnt == BLOCK_LENGTH) /* block complete */ - { - dataSrcBlock += BLOCK_LENGTH; - - txBlockCnt = 0; - - /* disable FIFO int until next block write */ - //LPC_MCI->MASK0 &= ~(FIFO_TX_INT_MASK); - - /* wait for SD card to complete sending data i.e MCI_DATA_BLK_END interrupt */ - } - } - else if ( MCIStatus & (FIFO_RX_INT_MASK) ) - { - /* if using RX_HALF_FULL remove one ReadFIFO below */ - if ( MCIStatus & MCI_RX_HALF_FULL ) - { - //There's no store data, return - if(dataDestBlock == NULL) - return; - - /* read 8 words from fifo */ - MCI_ReadFifo((uint32_t *)&dataDestBlock[rxBlockCnt]); - - rxBlockCnt += 32; - } - - /* block complete */ - if (rxBlockCnt == BLOCK_LENGTH) - { - dataDestBlock += BLOCK_LENGTH; - - rxBlockCnt = 0; - } - } -#endif - - return; -} - -/*********************************************************************//** - * @brief MCI_IRQHandler is to manage the reasons that cause the - * interrupt. - * - * @details It controls the data-block writing and reading by access - * the FIFO register. - * It handle the state changes on the MCI bus... - * - * @param None - * - * @return None - **********************************************************************/ -void MCI_IRQHandler (void) -{ - uint32_t MCI_Status; - - MCI_Status = LPC_MCI->STATUS; - - /* handle MCI_STATUS interrupt */ - if ( MCI_Status & DATA_ERR_INT_MASK ) - { - MCI_DataErrorProcess(); - - return; - } - - if ( MCI_Status & DATA_END_INT_MASK ) - { - MCI_DATA_END_InterruptService(); - - return; - } - else if ( MCI_Status & FIFO_INT_MASK ) - { - MCI_FIFOInterruptService(); - - return; - } - else if ( MCI_Status & CMD_INT_MASK ) - { - MCI_CmdProcess(); - - return; - } -} - - -/** - * @} - */ - - - -/** @addtogroup MCI_Public_Functions - * @{ - */ - -/*********************************************************************//** - * @brief Set MCI clock rate, during initialization phase < 400K - * during data phase < 20Mhz - * - * @param[in] ClockRate Clock rate to be set (in Hz) - * - * @return None - **********************************************************************/ -void MCI_Set_MCIClock( uint32_t ClockRate ) -{ - volatile uint32_t i; - uint32_t ClkValue = 0; - uint32_t pclk; - - pclk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER); - - ClkValue = (pclk + 2*ClockRate - 1) /(2*ClockRate); - if(ClkValue) - ClkValue -= 1; - - LPC_MCI->CLOCK = (LPC_MCI->CLOCK & ~(0xFF)) | (1 << 8) | ClkValue; - - for ( i = 0; i < 0x10; i++ ); /* delay 3MCLK + 2PCLK before next write */ - - return; -} - - -/**********************************************************************//** - * @brief Set the Width to 1-bit Bus or 4-bit Bus - * - * @param[in] width buswidth expected to set - * - * @return MCI_FUNC_OK in case of success - *************************************************************************/ -int32_t MCI_SetBusWidth( uint32_t width ) -{ - volatile uint32_t i; - uint8_t bus_width = BUS_WIDTH_1BIT; - - if ( width == SD_1_BIT ) - { - LPC_MCI->CLOCK &= ~(1 << 11); /* 1 bit bus */ - } - else if ( width == SD_4_BIT ) - { - LPC_MCI->CLOCK |= (1 << 11);/* 4 bit bus */ - bus_width = BUS_WIDTH_4BITS; - } - - for ( i = 0; i < 0x10; i++ ); /* delay 3MCLK + 2PCLK */ - - if ((MCI_CardType == MCI_SDSC_V1_CARD) || - (MCI_CardType == MCI_SDSC_V2_CARD) || - (MCI_CardType == MCI_SDHC_SDXC_CARD)) - { - if ( MCI_Acmd_SendBusWidth( bus_width ) != MCI_FUNC_OK ) - { - return(MCI_FUNC_FAILED); - } - } - return MCI_FUNC_OK; -} - - -/************************************************************************//** - * @brief Do initialization the MCI block as set its clock, registers, - * setup NVIC for interrupts, configure the pins used for MCI - * function, do initialize the card in slot... - * - * @param[in] powerActiveLevel the power level to activate the card in slot - * - * @return MCI_FUNC_OK in case of success - ***************************************************************************/ -int32_t MCI_Init(uint8_t powerActiveLevel ) -{ - volatile uint32_t i; - - MCI_CardType = MCI_CARD_UNKNOWN; - - // Following block of code added to ensure card VCC drops to zero - // before card is initialized - - // Force all MCI control pins to basic I/O mode - LPC_IOCON->P1_2 &= ~0x1F; /* SD_CLK @ P1.2 */ - LPC_IOCON->P1_3 &= ~0x1F; /* SD_CMD @ P1.3 */ - LPC_IOCON->P1_5 &= ~0x1F; /* SD_PWR @ P1.5 */ - LPC_IOCON->P1_6 &= ~0x1F; /* SD_DAT_0 @ P1.6 */ - LPC_IOCON->P1_7 &= ~0x1F; /* SD_DAT_1 @ P1.7 */ - LPC_IOCON->P1_11 &= ~0x1F; /* SD_DAT_2 @ P1.11 */ - LPC_IOCON->P1_12 &= 0x1F; /* SD_DAT_3 @ P1.12 */ - - // Set all MCI pins to outputs - LPC_GPIO1->DIR |= 0x18EC; - - // Force all pins low (except power control pin) - LPC_GPIO1->CLR = 0x1000; - LPC_GPIO1->CLR = 0x0800; - LPC_GPIO1->CLR = 0x0080; - LPC_GPIO1->CLR = 0x0040; - - LPC_GPIO1->SET = 0x0020; - - LPC_GPIO1->CLR = 0x0008; - LPC_GPIO1->CLR = 0x0004; - - // Crude delay of 50ms at 120MHz - for ( i = 0; i < 0x100000; i++ ); - - LPC_SC->PCONP |= ( 1 << 28 ); /* Enable clock to the MCI block */ - - if ( LPC_MCI->CLOCK & (1 << 8) ) - { - LPC_MCI->CLOCK &= ~(1 << 8); - for ( i = 0; i < 0x10; i++ ); /* delay 3MCLK + 2PCLK */ - } - - if ( LPC_MCI->POWER & 0x02 ) - { - LPC_MCI->POWER = 0x00; - for ( i = 0; i < 0x10; i++ ); /* delay 3MCLK + 2PCLK */ - } - - /* Disable all interrupts for now */ - LPC_MCI->MASK0 = 0; - - //SD_CLK - PINSEL_ConfigPin(1, 2, 2); - - //SD_CMD - PINSEL_ConfigPin(1, 3, 2); - - //SD_PWR - PINSEL_ConfigPin(1, 5, 2); - - //SD_DAT_0 - PINSEL_ConfigPin(1, 6, 2); - - //SD_DAT_1 - PINSEL_ConfigPin(1, 7, 2); - - //SD_DAT_2 - PINSEL_ConfigPin(1, 11, 2); - - //SD_DAT_3 - PINSEL_ConfigPin(1, 12, 2); - - // SD_PWR is active high (follows the output of the SD Card interface block). - if(powerActiveLevel == LOW_LVL) - { - LPC_SC->SCS &= ~ 0x08;//Becase on EA board SD_PWR is active low - } - else - { - LPC_SC->SCS |= 0x08; - } - - //Setting for timeout problem - LPC_MCI->DATATMR = 0x1FFFFFFF; - - /*set up clocking default mode, clear any registers as needed */ - LPC_MCI->COMMAND = 0; - for ( i = 0; i < 0x10; i++ ); /* delay 3MCLK + 2PCLK */ - LPC_MCI->DATACTRL = 0; - for ( i = 0; i < 0x10; i++ ); /* delay 3MCLK + 2PCLK */ - LPC_MCI->CLEAR = 0x7FF; /* clear all pending interrupts */ - - LPC_MCI->POWER = 0x02; /* power up */ - for ( i = 0; i < 0x10; i++ ); /* delay 3MCLK + 2PCLK */ - - - /* delays for the supply output is stable*/ - for ( i = 0; i < 0x80000; i++ ); - - /* During identification phase, the clock should be less than - 400Khz. Once we pass this phase, the normal clock can be set up - to 25Mhz on SD card and 20Mhz on MMC card. */ - MCI_Set_MCIClock(MCI_SLOW_RATE ); - - LPC_MCI->POWER |= 0x01; /* bit 1 is set already, from power up to power on */ - for ( i = 0; i < 0x10; i++ ); /* delay 3MCLK + 2PCLK */ - - NVIC_EnableIRQ(MCI_IRQn); - - MCI_CardInit(); - - /* During the initialization phase, to simplify the process, the CMD related - interrupts are disabled. The DATA related interrupts are enabled when - the FIFOs are used and just before WRITE_BLOCK READ_BLOCK cmds are issues, and - disabled after the data block has been written and read. Please also note, - before WRITE_BLOCK only TX related data interrupts are enabled, and before - READ_BLOCK only RX related data interrupts are enabled. */ - return MCI_FUNC_OK; -} - - -/************************************************************************//** - * @brief Set output in open drain mode or pushpull mode - * - * @param[in] mode the mode going to set - * - * @return None - ***************************************************************************/ -void MCI_SetOutputMode(uint32_t mode) -{ - uint32_t i = 0; - if(mode == MCI_OUTPUT_MODE_OPENDRAIN) - { - /* Set Open Drain output control for MMC */ - LPC_MCI->POWER |= (1 << MCI_PWRCTRL_OPENDRAIN_POS) & MCI_PWRCTRL_BMASK; - } - else - { - /* Clear Open Drain output control for SD */ - LPC_MCI->POWER &= (~(1 << MCI_PWRCTRL_OPENDRAIN_POS) & MCI_PWRCTRL_BMASK); - } - for ( i = 0; i < 0x10; i++ ); /* delay 3MCLK + 2PCLK */ -} - - -/************************************************************************//** - * @brief The routine is used to send a CMD to the card - * - * @param[in] CmdIndex the command to be sent to cards - * - * @param[in] Argument the argument follows the command - * - * @param[in] ExpectResp the response type for the command. They may be: - * - EXPECT_NO_RESP: means no response required - * - EXPECT_SHORT_RESP: means a response in a word needed - * - EXPECT_LONG_RESP: means a response in 4 words needed - * - * @param[in] AllowTimeout allow timeout the command or not - * - * @return None - ***************************************************************************/ -void MCI_SendCmd(st_Mci_CmdInfo* pCmdIf) -{ - volatile uint32_t i; - uint32_t CmdData = 0; - uint32_t CmdStatus; - - uint32_t CmdIndex = pCmdIf->CmdIndex; - uint32_t Argument = pCmdIf->Argument; - uint32_t ExpectResp = pCmdIf->ExpectResp; - uint32_t AllowTimeout = pCmdIf->AllowTimeout; - - /* the command engine must be disabled when we modify the argument - or the peripheral resends */ - while ( (CmdStatus = LPC_MCI->STATUS) & MCI_CMD_ACTIVE ) /* Command in progress. */ - { - LPC_MCI->COMMAND = 0; - for ( i = 0; i < 0x10; i++ ); /* delay 3MCLK + 2PCLK */ - LPC_MCI->CLEAR = CmdStatus | MCI_CMD_ACTIVE; - } - - - /*set the command details, the CmdIndex should 0 through 0x3F only */ - CmdData |= (CmdIndex & 0x3F); /* bit 0 through 5 only */ - - if ( ExpectResp == EXPECT_NO_RESP ) /* no response */ - { - CmdData &= ~((1 << 6) | (1 << 7)); /* Clear long response bit as well */ - } - else if ( ExpectResp == EXPECT_SHORT_RESP ) /* expect short response */ - { - CmdData |= (1 << 6); - } - else if ( ExpectResp == EXPECT_LONG_RESP ) /* expect long response */ - { - CmdData |= (1 << 6) | (1 << 7); - } - - if ( AllowTimeout == ALLOW_CMD_TIMER ) /* allow timeout or not */ - { - CmdData &= ~ MCI_DISABLE_CMD_TIMER; - } - else - { - CmdData |= MCI_DISABLE_CMD_TIMER; - } - - /*send the command*/ - CmdData |= (1 << 10); /* This bit needs to be set last. */ - - // clear status register - LPC_MCI->CLEAR = 0x7FF; - - LPC_MCI->ARGUMENT = Argument; /* Set the argument first, finally command */ - - LPC_MCI->COMMAND = CmdData; - - for ( i = 0; i < 0x10; i++ ); /* delay 3MCLK + 2PCLK */ - - // Wait until command is processed - while(!LPC_MCI->STATUS); - - // Wait until command sent - while(LPC_MCI->STATUS & MCI_CMD_ACTIVE); - - return; -} - - -/************************************************************************//** - * @brief The routine is to get the reponse from card after commands. - * This function is always used in pair of MCI_SendCmd() func - * - * @param[in] ExpectCmdData specify the command of which the data will be - * retrieved. This field should be the same with CmdIndex of - * MCI_SendCmd() function. - * - * @param[in] ExpectResp the response type for the command. They may be: - * - EXPECT_NO_RESP: means no response required - * - EXPECT_SHORT_RESP: means a response in a word needed - * - EXPECT_LONG_RESP: means a response in 4 words needed - * - * @param[out] CmdResp the buffer stored the data replied from cards - * - * @return MCI_FUNC_OK in case of success - ***************************************************************************/ -int32_t MCI_GetCmdResp(uint32_t ExpectCmdData, uint32_t ExpectResp, uint32_t *CmdResp) -{ - uint32_t CmdRespStatus = 0; - uint32_t LastCmdIndex; - uint32_t i = 0; - - if ( ExpectResp == EXPECT_NO_RESP ) - { - return MCI_FUNC_OK; - } - - while (1) - { - // Get the status of the component - CmdRespStatus = LPC_MCI->STATUS; - - if ( CmdRespStatus & (MCI_CMD_TIMEOUT) ) - { - LPC_MCI->CLEAR = CmdRespStatus | MCI_CMD_TIMEOUT; - - LPC_MCI->COMMAND = 0; - LPC_MCI->ARGUMENT = 0xFFFFFFFF; - - for ( i = 0; i < 0x10; i++ ); /* delay 3MCLK + 2PCLK */ - - return (CmdRespStatus); - } - - if ( CmdRespStatus & MCI_CMD_CRC_FAIL ) - { - LPC_MCI->CLEAR = CmdRespStatus | MCI_CMD_CRC_FAIL; - LastCmdIndex = LPC_MCI->COMMAND & 0x003F; - - if ( (LastCmdIndex == CMD1_SEND_OP_COND) || (LastCmdIndex == ACMD41_SEND_APP_OP_COND) - || (LastCmdIndex == CMD12_STOP_TRANSMISSION) ) - { - LPC_MCI->COMMAND = 0; - LPC_MCI->ARGUMENT = 0xFFFFFFFF; - for ( i = 0; i < 0x10; i++ ); /* delay 3MCLK + 2PCLK */ - break; /* ignore CRC error if it's a resp for SEND_OP_COND - or STOP_TRANSMISSION. */ - } - else - { - return (CmdRespStatus); - } - } - else if (CmdRespStatus & MCI_CMD_RESP_END) - { - LPC_MCI->CLEAR = CmdRespStatus | MCI_CMD_RESP_END; - break; /* cmd response is received, expecting response */ - } - - } - - if ((LPC_MCI->RESP_CMD & 0x3F) != ExpectCmdData) - { - /* If the response is not R1, in the response field, the Expected Cmd data - won't be the same as the CMD data in SendCmd(). Below four cmds have - R2 or R3 response. We don't need to check if MCI_RESP_CMD is the same - as the Expected or not. */ - if ((ExpectCmdData != CMD1_SEND_OP_COND) && (ExpectCmdData != ACMD41_SEND_APP_OP_COND) - && (ExpectCmdData != CMD2_ALL_SEND_CID) && (ExpectCmdData != CMD9_SEND_CSD)) - { - CmdRespStatus = INVALID_RESPONSE; /* Reuse error status */ - return (INVALID_RESPONSE); - } - } - - /* Read MCI_RESP0 register assuming it's not long response. */ - if (CmdResp != NULL) - { - if (ExpectResp == EXPECT_SHORT_RESP) - { - *(CmdResp + 0) = LPC_MCI->RESP0; - } - else if (ExpectResp == EXPECT_LONG_RESP) - { - *(CmdResp + 0) = LPC_MCI->RESP0; - *(CmdResp + 1) = LPC_MCI->RESP1; - *(CmdResp + 2) = LPC_MCI->RESP2; - *(CmdResp + 3) = LPC_MCI->RESP3; - } - } - - return MCI_FUNC_OK; -} - - -/************************************************************************//** - * @brief The routine is to send command to cards then get back the - * reponses (if required). - * - * @param[in] CmdIndex the command to be sent to cards - * - * @param[in] Argument the argument follows the command - * - * @param[in] ExpectResp the response type for the command. They may be: - * - EXPECT_NO_RESP: means no response required - * - EXPECT_SHORT_RESP: means a response in a word needed - * - EXPECT_LONG_RESP: means a response in 4 words needed - * - * @param[out] CmdResp the buffer stored the data replied from cards - * - * @param[in] AllowTimeout allow timeout the command or not - * - * @return MCI_FUNC_OK in case of success - ***************************************************************************/ -int32_t MCI_CmdResp(st_Mci_CmdInfo* pCmdIf) -{ - int32_t respStatus; - uint32_t CmdIndex = pCmdIf->CmdIndex; - uint32_t ExpectResp = pCmdIf->ExpectResp; - uint32_t *CmdResp = pCmdIf->CmdResp; - - - MCI_SendCmd(pCmdIf); - - if((CmdResp != NULL) || (ExpectResp != EXPECT_NO_RESP)) - { - respStatus = MCI_GetCmdResp(CmdIndex, ExpectResp, CmdResp); - } - else - { - respStatus = MCI_FUNC_BAD_PARAMETERS; - } - - return respStatus; -} - - -/************************************************************************//** - * @brief To reset the card, the CMD0 is sent and then the card is put - * in idle state. This is the very first command to be sent to - * initialize either MMC or SD card. - * - * @param None - * - * @return Always MCI_FUNC_OK - ***************************************************************************/ -int32_t MCI_CardReset(void) -{ - st_Mci_CmdInfo cmdIf; - /* Because CMD0 command to put the device to idle state does not need response - since, it's only sending commad */ - cmdIf.CmdIndex = CMD0_GO_IDLE_STATE; - cmdIf.Argument = 0x00000000; - cmdIf.ExpectResp = EXPECT_NO_RESP; - cmdIf.AllowTimeout = 0; - cmdIf.CmdResp = 0; - MCI_SendCmd(&cmdIf); - - return MCI_FUNC_OK; -} - - -/************************************************************************//** - * @brief Send CMD1 (SEND_OP_COND) to card. - * - * @param None - * - * @return MCI_FUNC_OK if all success - ****************************************************************************/ -int32_t MCI_Cmd_SendOpCond( void ) -{ - volatile uint32_t i; - uint32_t retryCount; - uint32_t respStatus; - uint32_t respValue[4]; - st_Mci_CmdInfo cmdIf; - int32_t retval = MCI_FUNC_FAILED; - - retryCount = 0x200; /* reset retry counter */ - - cmdIf.CmdIndex = CMD1_SEND_OP_COND; - cmdIf.Argument = OCR_INDEX; - cmdIf.ExpectResp = EXPECT_SHORT_RESP; - cmdIf.AllowTimeout = ALLOW_CMD_TIMER; - cmdIf.CmdResp = (uint32_t *)&respValue[0]; - /* continuously sends until the busy bit is cleared */ - while ( retryCount > 0 ) - { - respStatus = MCI_CmdResp(&cmdIf); - - if(respStatus & MCI_CMD_TIMEOUT) - { - retval = MCI_FUNC_TIMEOUT; - } - else if ((respValue[0] & 0x80000000) == 0) - { - //The card has not finished the power up routine - retval = MCI_FUNC_BUS_NOT_IDLE; - } - else - { - retval = MCI_FUNC_OK; - break; - } - - for ( i = 0; i < 0x20; i++ ); - - retryCount--; - } - - return(retval); -} - - -/************************************************************************//** - * @brief Send CMD8 (SEND_IF_COND) for interface condition to card. - * - * @param None - * - * @return MCI_FUNC_OK if all success - ****************************************************************************/ -int32_t MCI_Cmd_SendIfCond(void) -{ - volatile uint32_t i; - uint32_t retryCount; - uint32_t CmdArgument; - uint32_t respStatus; - uint32_t respValue[4]; - - int32_t retval = MCI_FUNC_FAILED; - - uint8_t voltageSupplied = MCI_CMD8_VOLATAGESUPPLIED_27_36;//in range 2.7-3.6V - uint8_t checkPattern = 0xAA; - st_Mci_CmdInfo cmdIf; - - CmdArgument = (voltageSupplied << MCI_CMD8_VOLTAGESUPPLIED_POS) | (checkPattern << MCI_CMD8_CHECKPATTERN_POS); - - retryCount = 20; - - cmdIf.CmdIndex = CMD8_SEND_IF_COND; - cmdIf.Argument = CmdArgument; - cmdIf.ExpectResp = EXPECT_SHORT_RESP; - cmdIf.AllowTimeout = ALLOW_CMD_TIMER; - cmdIf.CmdResp = (uint32_t *)&respValue[0]; - while ( retryCount > 0 ) - { - respStatus = MCI_CmdResp(&cmdIf); - - if(respStatus & MCI_CMD_TIMEOUT) - { - //Consider as no response - retval = MCI_FUNC_TIMEOUT; - } - else if (((respValue[0]>>MCI_CMD8_CHECKPATTERN_POS) & MCI_CMD8_CHECKPATTERN_BMASK) != checkPattern) - { - return MCI_FUNC_BAD_PARAMETERS; - } - else if (((respValue[0] >> MCI_CMD8_VOLTAGESUPPLIED_POS) & MCI_CMD8_VOLTAGESUPPLIED_BMASK) - != voltageSupplied) - { - return MCI_FUNC_BAD_PARAMETERS; - } - else - { - return MCI_FUNC_OK; - } - - for ( i = 0; i < 0x20; i++ ); - - retryCount--; - } - - return retval; -} - - -/************************************************************************//** - * @brief Send CMD55 (APP_CMD) to indicate to the card that the next - * command is an application specific command rather than a - * standard command. Before an ACMD, call this routine first - * - * @param None - * - * @return MCI_FUNC_OK if all success - ****************************************************************************/ -int32_t MCI_Cmd_SendACMD( void ) -{ - volatile uint32_t i; - uint32_t retryCount; - uint32_t CmdArgument; - uint32_t respStatus; - uint32_t respValue[4]; - st_Mci_CmdInfo cmdIf; - int32_t retval = MCI_FUNC_FAILED; - - if ((MCI_CardType == MCI_SDSC_V1_CARD) || - (MCI_CardType == MCI_SDSC_V2_CARD) || - (MCI_CardType == MCI_SDHC_SDXC_CARD)) - { - CmdArgument = CardRCA; /* Use the address from SET_RELATIVE_ADDR cmd */ - } - else /* if MMC or unknown card type, use 0x0. */ - { - CmdArgument = 0x00000000; - } - - retryCount = 20; - - cmdIf.CmdIndex = CMD55_APP_CMD; - cmdIf.Argument = CmdArgument; - cmdIf.ExpectResp = EXPECT_SHORT_RESP; - cmdIf.AllowTimeout = ALLOW_CMD_TIMER; - cmdIf.CmdResp = (uint32_t *)&respValue[0]; - while ( retryCount > 0 ) - { - respStatus = MCI_CmdResp(&cmdIf); - - if(respStatus != 0) - { - retval = MCI_FUNC_FAILED; - } - else if (respValue[0] & CARD_STATUS_ACMD_ENABLE) - { - retval = MCI_FUNC_OK; - break; - } - else - { - retval = MCI_FUNC_NOT_READY; - } - - for ( i = 0; i < 0x20; i++ ); - - retryCount--; - } - - return retval; -} - - -/************************************************************************//** - * @brief Send ACMD41 (SEND_APP_OP_COND) to Host Capacity Support (HCS) - * information and asks the accessed card to send its operating - * condition (OCR). - * - * @param[in] hcsVal input the Host Capacity Support - * - * @return MCI_FUNC_OK if all success - * - * @note If SEND_APP_OP_COND is timeout, the card in the slot is not MMC - * type, try this combination to see if we can communicate with - * a SD type. - ****************************************************************************/ -int32_t MCI_Acmd_SendOpCond(uint8_t hcsVal) -{ - volatile uint32_t i; - uint32_t retryCount; - uint32_t respStatus, argument; - uint32_t respValue[4]; - st_Mci_CmdInfo cmdIf; - - int32_t retval = MCI_FUNC_FAILED; - - argument = OCR_INDEX | (hcsVal << MCI_ACMD41_HCS_POS); - - /* timeout on SEND_OP_COND command on MMC, now, try SEND_APP_OP_COND - command to SD */ - retryCount = 0x2000; /* reset retry counter */ - - cmdIf.CmdIndex = ACMD41_SEND_APP_OP_COND; - cmdIf.Argument = argument; - cmdIf.ExpectResp = EXPECT_SHORT_RESP; - cmdIf.AllowTimeout = ALLOW_CMD_TIMER; - cmdIf.CmdResp = (uint32_t *)&respValue[0]; - - /* Clear Open Drain output control for SD */ - MCI_SetOutputMode(MCI_OUTPUT_MODE_PUSHPULL); - - /* The host repeatedly issues ACMD41 for at least 1 second or */ - /* until the busy bit are set to 1 */ - while ( retryCount > 0 ) - { - if ((retval = MCI_Cmd_SendACMD()) == MCI_FUNC_OK) - { - respStatus = MCI_CmdResp(&cmdIf); - - if(respStatus & MCI_CMD_TIMEOUT) - { - retval = MCI_FUNC_TIMEOUT; - } - else if (!(respValue[0] & 0x80000000)) - { - retval = MCI_FUNC_BUS_NOT_IDLE; - } - else - { - CCS = (respValue[0]&(1<<30)) ? 1:0; - retval = MCI_FUNC_OK; - break; - } - } - else /* The command isn't accepted by the card.*/ - { - return retval; - } - - for ( i = 0; i < 0x20; i++ ); - - retryCount--; - } - - return retval; -} - -/************************************************************************//** - * @brief Do initialization for the card in the slot - * - * @details Try CMD1 first for MMC, if it's timeout, try CMD55 - * and CMD41 for SD, if both failed, initialization faliure, - * bailout with unknown card type. Otherwise, return the - * card type, either MMC or SD. <<>> - * - * This is followed Figure 4-2: Card Initialization and - * Identification Flow (SD mode) in Physical Layer Simplified - * Specification Version 2.00 document - * - * @param None - * - * @return MCI_FUNC_OK if success - ****************************************************************************/ -int32_t MCI_CardInit( void ) -{ - volatile uint32_t i; - int32_t retval = MCI_FUNC_FAILED; - - MCI_CardType = MCI_CARD_UNKNOWN; - - if (MCI_CardReset() != MCI_FUNC_OK) - { - return MCI_FUNC_FAILED; - } - - /* Clear Open Drain output control for SD */ - MCI_SetOutputMode(MCI_OUTPUT_MODE_PUSHPULL); - - for ( i = 0; i < 0x3000; i++ ); - - retval = MCI_Cmd_SendIfCond(); - - if(retval == MCI_FUNC_BAD_PARAMETERS) - { - //Unknow card is unusable - return retval; - } - - if(retval == MCI_FUNC_OK) /* Ver2.00 or later*/ - { - //Check in case of High Capacity Supporting Host - if ((retval = MCI_Acmd_SendOpCond(1)) == MCI_FUNC_OK) - { - MCI_CardType = MCI_SDSC_V2_CARD;//SDSC - - if(CCS ) - { - MCI_CardType = MCI_SDHC_SDXC_CARD;//SDHC or SDXC - } - - return MCI_FUNC_OK; /* Found the card, it's a hD */ - } - } - - if(retval != MCI_FUNC_OK) /* voltage mismatch (ver2.00)or ver1.X SD Card or not SD Card*/ - { - - //Check in case of Standard Capacity Supporting Host - if ((retval = MCI_Acmd_SendOpCond(0)) == MCI_FUNC_OK) - { - MCI_CardType = MCI_SDSC_V1_CARD;//Support Standard Capacity only - - return MCI_FUNC_OK; /* Found the card, it's a SD */ - } - } - - if(retval != MCI_FUNC_OK) - { - /* Set Open Drain output control for MMC */ - MCI_SetOutputMode(MCI_OUTPUT_MODE_OPENDRAIN); - - for ( i = 0; i < 0x3000; i++ ); - - /* Try CMD1 first for MMC, if it's timeout, try CMD55 and CMD41 for SD, - if both failed, initialization faIlure, bailout. */ - if (MCI_Cmd_SendOpCond() == MCI_FUNC_OK) - { - MCI_CardType = MCI_MMC_CARD; - - return MCI_FUNC_OK; /* Found the card, it's a MMC */ - } - } - - /* tried both MMC and SD card, give up */ - return MCI_FUNC_OK; -} - - -/************************************************************************//** - * @brief Get the type of card that is currently used in the slot - * - * @param None - * - * @return Card Type: MMC Card or SD card - ****************************************************************************/ -en_Mci_CardType MCI_GetCardType(void) -{ - return MCI_CardType; -} - - -/************************************************************************//** - * @brief Get the all the Identifier (CID) of the card by sending the - * CMD2 (ALL_SEND_CID) command. Then parse 4-byte data obtained - * from the card by the CID meaning. - * - * @param[out] cidValue the CID Result after parsing the data from the card - * - * @return MCI_FUNC_OK if all success - ****************************************************************************/ -int32_t MCI_GetCID(st_Mci_CardId* cidValue) -{ - volatile uint32_t i; - uint32_t retryCount; - uint32_t respStatus; - uint32_t respValue[4]; - st_Mci_CmdInfo cmdIf; - - /* This command is normally after CMD1(MMC) or ACMD41(SD). */ - retryCount = 0x200;// 0x20; /* reset retry counter */ - - cmdIf.CmdIndex = CMD2_ALL_SEND_CID; - cmdIf.Argument = 0; - cmdIf.ExpectResp = EXPECT_LONG_RESP; - cmdIf.AllowTimeout = ALLOW_CMD_TIMER; - cmdIf.CmdResp = (uint32_t *)&respValue[0]; - while ( retryCount > 0 ) - { - respStatus = MCI_CmdResp(&cmdIf); - - /* bit 0 and bit 2 must be zero, or it's timeout or CRC error */ - //if ((!(respStatus & MCI_CMD_TIMEOUT)) && (!(respStatus & MCI_CMD_CRC_FAIL))) - if (!(respStatus & MCI_CMD_TIMEOUT)) - { - // Parsing the data retrieved - if(cidValue != NULL) - { - cidValue->MID = (respValue[0] >> MCI_CID_MANUFACTURER_ID_WPOS) & MCI_CID_MANUFACTURER_ID_WBMASK; - - cidValue->OID = (respValue[0] >> MCI_CID_OEMAPPLICATION_ID_WPOS) & MCI_CID_OEMAPPLICATION_ID_WBMASK; - - cidValue->PNM_H = (respValue[0] >> MCI_CID_PRODUCTNAME_ID_H_WPOS) & MCI_CID_PRODUCTNAME_ID_H_WBMASK; - - cidValue->PNM_L = (respValue[1] >> MCI_CID_PRODUCTNAME_ID_L_WPOS) & MCI_CID_PRODUCTNAME_ID_L_WBMASK; - - cidValue->PRV = (respValue[2] >> MCI_CID_PRODUCTREVISION_ID_WPOS) & MCI_CID_PRODUCTREVISION_ID_WBMASK; - - cidValue->PSN = (((respValue[2] >> MCI_CID_PRODUCTSERIALNUM_ID_H_WPOS) & MCI_CID_PRODUCTSERIALNUM_ID_H_WBMASK) << 8) - | ((respValue[3] >> MCI_CID_PRODUCTSERIALNUM_ID_L_WPOS) & MCI_CID_PRODUCTSERIALNUM_ID_L_WBMASK); - - cidValue->reserved = (respValue[3] >> MCI_CID_RESERVED_ID_WPOS) & MCI_CID_RESERVED_ID_WBMASK; - - cidValue->MDT = (respValue[3] >> MCI_CID_MANUFACTURINGDATE_ID_WPOS) & MCI_CID_MANUFACTURINGDATE_ID_WBMASK; - - cidValue->CRC = (respValue[3] >> MCI_CID_CHECKSUM_ID_WPOS) & MCI_CID_CHECKSUM_ID_WBMASK; - - cidValue->unused = (respValue[3] >> MCI_CID_UNUSED_ID_WPOS) & MCI_CID_UNUSED_ID_WBMASK; - - } - - return MCI_FUNC_OK; /* response is back and correct. */ - } - - - for ( i = 0; i < 0x20; i++ ); - - retryCount--; - } - - return MCI_FUNC_TIMEOUT; -} - - -/************************************************************************//** - * @brief Set the address for the card in the slot by sending CMD3 - * (SET_RELATIVE_ADDR) command. To get the address of the card - * currently in used, needs to call MCI_GetCardAddress() - * - * @param None - * - * @return MCI_FUNC_OK if all success - ****************************************************************************/ -int32_t MCI_SetCardAddress( void ) -{ - volatile uint32_t i; - uint32_t retryCount; - uint32_t respStatus; - uint32_t respValue; - uint32_t CmdArgument; - st_Mci_CmdInfo cmdIf; - int32_t retval = MCI_FUNC_FAILED; - - /* If it's a SD card, SET_RELATIVE_ADDR is to get the address - from the card and use this value in RCA, if it's a MMC, set default - RCA addr. 0x00010000. */ - if ((MCI_CardType == MCI_SDSC_V1_CARD) || - (MCI_CardType == MCI_SDSC_V2_CARD) || - (MCI_CardType == MCI_SDHC_SDXC_CARD)) - { - CmdArgument = 0; - } - else /* If it's unknown or MMC_CARD, fix the RCA address */ - { - CmdArgument = 0x00010000; - } - - retryCount = 0x20; /* reset retry counter */ - cmdIf.CmdIndex = CMD3_SET_RELATIVE_ADDR; - cmdIf.Argument = CmdArgument; - cmdIf.ExpectResp = EXPECT_SHORT_RESP; - cmdIf.AllowTimeout = ALLOW_CMD_TIMER; - cmdIf.CmdResp = &respValue; - while ( retryCount > 0 ) - { - /* Send CMD3 command repeatedly until the response is back correctly */ - respStatus = MCI_CmdResp(&cmdIf); - - if(respStatus & MCI_CMD_TIMEOUT) - { - retval = MCI_FUNC_TIMEOUT; - } - else if(!((respValue >> RCA_RES_CARD_STATUS_POS)& CARD_STATUS_READY_FOR_DATA)) - { - retval = MCI_FUNC_NOT_READY; - } - else if((CARDSTATEOF(respValue) != MCI_CARDSTATE_IDENDTIFIED)) - { - retval = MCI_FUNC_ERR_STATE; - } - else - { - CardRCA = (respValue >> RCA_RES_NEW_PUBLISHED_RCA_POS) & RCA_RES_NEW_PUBLISHED_RCA_MASK; /* Save the RCA value from SD card */ - - CardRCA <<= RCA_ARGUMENT_POS; - - MCI_SetOutputMode(MCI_OUTPUT_MODE_PUSHPULL); - - return (MCI_FUNC_OK); /* response is back and correct. */ - } - - for ( i = 0; i < 0x20; i++ ); - - retryCount--; - } - - return retval; -} - - -/************************************************************************//** - * @brief Get the address for the card in the slot - * - * @param None - * - * @return MCI_FUNC_OK if all success - * - * @note This function must be called after MCI_SetCardAddress() executing - ****************************************************************************/ -uint32_t MCI_GetCardAddress(void) -{ - return CardRCA; -} - - -/************************************************************************//** - * @brief Get the Card-Specific Data of in-slot card by sending CMD9 - * (SEND_CSD) command - * - * @param[out] csdVal a buffer stored the value of CSD obtained from the card - * - * @return MCI_FUNC_OK if all success - * - * @note CMD9 (SEND_CSD) command should be sent only at standby state - * (STBY) after CMD3 - ****************************************************************************/ -int32_t MCI_GetCSD(uint32_t* csdVal) -{ - volatile uint32_t i; - uint32_t retryCount; - uint32_t respStatus; - uint32_t respValue[4]; - uint32_t CmdArgument; - st_Mci_CmdInfo cmdIf; - - if ((MCI_CardType == MCI_SDSC_V1_CARD) || - (MCI_CardType == MCI_SDSC_V2_CARD) || - (MCI_CardType == MCI_SDHC_SDXC_CARD)) - { - CmdArgument = CardRCA; - } - else /* if MMC or unknown card type, use default RCA addr. */ - { - CmdArgument = 0x00010000; - } - - retryCount = 0x20; - cmdIf.CmdIndex = CMD9_SEND_CSD; - cmdIf.Argument = CmdArgument; - cmdIf.ExpectResp = EXPECT_LONG_RESP; - cmdIf.AllowTimeout = ALLOW_CMD_TIMER; - cmdIf.CmdResp = (uint32_t *)&respValue[0]; - while ( retryCount > 0 ) - { - /* Check current status */ - if(((MCI_CheckStatus(CARD_STATE_STBY) != MCI_FUNC_OK))) - return MCI_FUNC_ERR_STATE; - - respStatus = MCI_CmdResp(&cmdIf); - - if ( !respStatus ) - { - if(csdVal != NULL) - { - csdVal[0] = respValue[0]; - csdVal[1] = respValue[1]; - csdVal[2] = respValue[2]; - csdVal[3] = respValue[3]; - } - - return (MCI_FUNC_OK); - } - - for ( i = 0; i < 0x20; i++ ); - - retryCount--; - } - - return (MCI_FUNC_FAILED); -} - - -/************************************************************************//** - * @brief Select the card by the specified address. This is done by sending - * out the CMD7 with the address argument to needed card - * - * @param None - * - * @return MCI_FUNC_OK if all success - * - * @note CMD7 (SELECT_CARD) command should be sent after CMD9 ((SEND_CSD). - * The state will be inter-changed between STBY to TRANS by this - * CMD7 command - ****************************************************************************/ -int32_t MCI_Cmd_SelectCard( void ) -{ - volatile uint32_t i; - uint32_t retryCount; - uint32_t respStatus; - uint32_t respValue[4]; - uint32_t CmdArgument; - st_Mci_CmdInfo cmdIf; - int32_t retval = MCI_FUNC_FAILED; - - if ((MCI_CardType == MCI_SDSC_V1_CARD) || - (MCI_CardType == MCI_SDSC_V2_CARD) || - (MCI_CardType == MCI_SDHC_SDXC_CARD)) - { - CmdArgument = CardRCA; - } - else /* if MMC or unknown card type, use default RCA addr. */ - { - CmdArgument = 0x00010000; - } - - retryCount = 0x20; - cmdIf.CmdIndex = CMD7_SELECT_CARD; - cmdIf.Argument = CmdArgument; - cmdIf.ExpectResp = EXPECT_SHORT_RESP; - cmdIf.AllowTimeout = ALLOW_CMD_TIMER; - cmdIf.CmdResp = (uint32_t *)&respValue[0]; - while ( retryCount > 0 ) - { - /* Check current status */ - if(((MCI_CheckStatus(CARD_STATE_STBY) != MCI_FUNC_OK)) && - (MCI_CheckStatus(CARD_STATE_TRAN) != MCI_FUNC_OK) && - (MCI_CheckStatus(CARD_STATE_DATA) != MCI_FUNC_OK) && - (MCI_CheckStatus(CARD_STATE_PRG) != MCI_FUNC_OK) && - (MCI_CheckStatus(CARD_STATE_DIS) != MCI_FUNC_OK)) - return MCI_FUNC_ERR_STATE; - - respStatus = MCI_CmdResp(&cmdIf); - - if(respStatus) - { - retval = MCI_FUNC_FAILED; - } - else if (respValue[0] & CARD_STATUS_ERR_MASK) - { - return MCI_FUNC_BAD_PARAMETERS; - } - else - { - if(((MCI_CheckStatus(CARD_STATE_STBY) != MCI_FUNC_OK)) && - (MCI_CheckStatus(CARD_STATE_TRAN) != MCI_FUNC_OK) && - (MCI_CheckStatus(CARD_STATE_PRG) != MCI_FUNC_OK) && - (MCI_CheckStatus(CARD_STATE_DIS) != MCI_FUNC_OK)) - return MCI_FUNC_ERR_STATE; - return MCI_FUNC_OK; - } - - for ( i = 0; i < 0x20; i++ ); - - retryCount--; - } - - return retval; -} - - -/************************************************************************//** - * @brief Get the status of the card. The return is from the card. - * By sending CMD13 (SEND_STATUS), the status of the card - * will be responded from card addressed - * - * @param[out] cardStatus the status returned from the card - * - * @return MCI_FUNC_OK if all success - ****************************************************************************/ -int32_t MCI_GetCardStatus(int32_t* cardStatus) -{ - volatile uint32_t i; - uint32_t retryCount; - uint32_t respStatus; - uint32_t respValue[4]; - uint32_t CmdArgument; - st_Mci_CmdInfo cmdIf; - int32_t retval = MCI_FUNC_FAILED; - - if(cardStatus == NULL) - return MCI_FUNC_OK; - - if ((MCI_CardType == MCI_SDSC_V1_CARD) || - (MCI_CardType == MCI_SDSC_V2_CARD) || - (MCI_CardType == MCI_SDHC_SDXC_CARD)) - { - CmdArgument = CardRCA; - } - else /* if MMC or unknown card type, use default RCA addr. */ - { - CmdArgument = 0x00010000; - } - - retryCount = 0x20; - cmdIf.CmdIndex = CMD13_SEND_STATUS; - cmdIf.Argument = CmdArgument; - cmdIf.ExpectResp = EXPECT_SHORT_RESP; - cmdIf.AllowTimeout = ALLOW_CMD_TIMER; - cmdIf.CmdResp = (uint32_t *)&respValue[0]; - while ( retryCount > 0 ) - { - respStatus = MCI_CmdResp(&cmdIf); - - if(respStatus) /* only retry if sending command failed */ - { - retval = MCI_FUNC_FAILED; - } - else - { - *cardStatus = respValue[0]; - - return MCI_FUNC_OK; - } - - retryCount--; - for ( i = 0; i < 0x10; i++ ); - } - - return retval; -} - -/************************************************************************//** - * @brief Set the length for the blocks in the next action on data - * manipulation (as read, write, erase). This function is to - * send CMD16 (SET_BLOCK_LEN) to cards. - * - * @param[in] blockLength the value for the length of block will be handled - * - * @return MCI_FUNC_OK if all success - * - * @note CMD16 command should be sent after the card is selected by CMD7 - * (SELECT_CARD). - * In the case of SDHC and SDXC Cards, block length set by CMD16 command doen't - * affect memory read and write commands. Always 512 Bytes fixed block length is - * used. This command is effective for LOCK_UNLOCK command.. - ****************************************************************************/ -int32_t MCI_SetBlockLen(uint32_t blockLength) -{ - volatile uint32_t i; - uint32_t retryCount; - uint32_t respStatus; - uint32_t respValue[4]; - st_Mci_CmdInfo cmdIf; - int32_t retval = MCI_FUNC_FAILED; - - retryCount = 0x20; - cmdIf.CmdIndex = CMD16_SET_BLOCK_LEN; - cmdIf.Argument = blockLength; - cmdIf.ExpectResp = EXPECT_SHORT_RESP; - cmdIf.AllowTimeout = ALLOW_CMD_TIMER; - cmdIf.CmdResp = (uint32_t *)&respValue[0]; - while ( retryCount > 0 ) - { - /* Check current status */ - if((MCI_CheckStatus(CARD_STATE_TRAN) != MCI_FUNC_OK) ) - return MCI_FUNC_ERR_STATE; - - respStatus = MCI_CmdResp(&cmdIf); - - if(respStatus) - { - retval = MCI_FUNC_FAILED; - } - else if (respValue[0] & CARD_STATUS_ERR_MASK) - { - return MCI_FUNC_BAD_PARAMETERS; - } - else - { - return MCI_CheckStatus(CARD_STATE_TRAN); - } - - - for ( i = 0; i < 0x20; i++ ); - - retryCount--; - } - - return retval; -} - - -/************************************************************************//** - * @brief Set bus-width (1 bit or 4 bit) to work with the card by command - * CMD6 (SET_ACMD_BUS_WIDTH). - * - * @param[in] buswidth The value represented for bus-width - * - 0b00: 1-bit bus-width - * - 0b10: 4-bit bus-width - * - * @return MCI_FUNC_OK if all success - * - * @note - * - If SD card is currently in used, it's possible to enable 4-bit - * bus-width instead of 1-bit to speed up. - * - This command can only be transferred during TRANS state. - * - Since, it's a ACMD, CMD55 (APP_CMD) needs to be sent out first - ****************************************************************************/ -int32_t MCI_Acmd_SendBusWidth( uint32_t buswidth ) -{ - volatile uint32_t i; - uint32_t retryCount; - uint32_t respStatus; - uint32_t respValue[4]; - st_Mci_CmdInfo cmdIf; - int32_t retval = MCI_FUNC_FAILED; - - retryCount = 0x20; /* reset retry counter */ - cmdIf.CmdIndex = ACMD6_SET_BUS_WIDTH; - cmdIf.Argument = buswidth; - cmdIf.ExpectResp = EXPECT_SHORT_RESP; - cmdIf.AllowTimeout = ALLOW_CMD_TIMER; - cmdIf.CmdResp = (uint32_t *)&respValue[0]; - while ( retryCount > 0 ) - { - /* The card must be in tran state in order to change the bus width */ - retval = MCI_CheckStatus(CARD_STATE_TRAN); - if(retval!= MCI_FUNC_OK) - return retval; - - if (MCI_Cmd_SendACMD() == MCI_FUNC_OK) - { - respStatus = MCI_CmdResp(&cmdIf); - - if(respStatus) - { - retval = MCI_FUNC_FAILED; - } - else if (respValue[0] & CARD_STATUS_ERR_MASK) - { - return MCI_FUNC_BAD_PARAMETERS; - } - else - { - return MCI_CheckStatus(CARD_STATE_TRAN); - } - } - - for ( i = 0; i < 0x20; i++ ); - - retryCount--; - } - - return retval; -} - - -/************************************************************************//** - * @brief Get the state of data transfer to see if it is ended or not - * - * @param None - * - * @return Transfer state (stored by Mci_Data_Xfer_End variable) - ****************************************************************************/ -uint32_t MCI_GetDataXferEndState(void) -{ - return Mci_Data_Xfer_End; -} -/************************************************************************//** - * @brief Get the error state of the lastest data transfer - * - * @param None - * - * @return Error state (stored by Mci_Data_Xfer_ERR variable) - ****************************************************************************/ -uint32_t MCI_GetXferErrState(void) -{ - return Mci_Data_Xfer_ERR; -} - -/************************************************************************//** - * @brief Stop the current transmission on the bus by sending command CMD12 - * (STOP_TRANSMISSION). In this case, the card may be in a unknown - * state. So that it need a warm reset for normal operation. - * - * @param[in] None - * - * @return MCI_FUNC_OK if all success - ****************************************************************************/ -int32_t MCI_Cmd_StopTransmission( void ) -{ - volatile uint32_t i; - uint32_t retryCount; - uint32_t respStatus; - uint32_t respValue[4]; - st_Mci_CmdInfo cmdIf; - int32_t retval = MCI_FUNC_FAILED; - - /* do nothing when the card is in tran state */ - if(MCI_CheckStatus(CARD_STATE_TRAN) == MCI_FUNC_OK) - { - return MCI_FUNC_OK; - } - - retryCount = 0x20; - cmdIf.CmdIndex = CMD12_STOP_TRANSMISSION; - cmdIf.Argument = 0x00000000; - cmdIf.ExpectResp = EXPECT_SHORT_RESP; - cmdIf.AllowTimeout = ALLOW_CMD_TIMER; - cmdIf.CmdResp = (uint32_t *)&respValue[0]; - while ( retryCount > 0 ) - { - /* Check current status */ - if((MCI_CheckStatus(CARD_STATE_DATA) != MCI_FUNC_OK) && - (MCI_CheckStatus(CARD_STATE_RCV) != MCI_FUNC_OK)) - return MCI_FUNC_ERR_STATE; - - respStatus = MCI_CmdResp(&cmdIf); - - if(respStatus) - { - retval = MCI_FUNC_FAILED; - } - else if (respValue[0] & CARD_STATUS_ERR_MASK) - { - return MCI_FUNC_BAD_PARAMETERS; - } - else - { - if((MCI_CheckStatus(CARD_STATE_PRG) != MCI_FUNC_OK) && - (MCI_CheckStatus(CARD_STATE_TRAN) != MCI_FUNC_OK)) - return MCI_FUNC_ERR_STATE; - return MCI_FUNC_OK; - } - - for ( i = 0; i < 0x20; i++ ); - - retryCount--; - } - - return retval; -} - - -/************************************************************************//** - * @brief Write blocks to card by sending command CMD24 (WRITE_BLOCK) or - * command CMD25 (WRITE_MULTIPLE_BLOCK) followed by the blocks of - * data to be written. - * - * @param[in] blockNum The block number to start writting - * - * @param[in] numOfBlock Determine how many blocks will be written (from the - * starting block) - * - * @return MCI_FUNC_OK if all success - * - * @note These commands should be sent in TRANS state. - ****************************************************************************/ -int32_t MCI_Cmd_WriteBlock(uint32_t blockNum, uint32_t numOfBlock) -{ - volatile uint32_t i; - uint32_t retryCount; - uint32_t respStatus; - uint32_t respValue[4]; - st_Mci_CmdInfo cmdIf; - uint32_t commandID; - - int32_t retval = MCI_FUNC_FAILED; - - if (numOfBlock > 1) - { - commandID = CMD25_WRITE_MULTIPLE_BLOCK; - } - else - { - commandID = CMD24_WRITE_BLOCK; - } - - retryCount = 0x20; - cmdIf.CmdIndex = commandID; - if (MCI_CardType == MCI_SDHC_SDXC_CARD) - { - cmdIf.Argument = blockNum; /* Block Address */ - } - else - { - cmdIf.Argument = blockNum * BLOCK_LENGTH; /* Byte Address */ - } - cmdIf.ExpectResp = EXPECT_SHORT_RESP; - cmdIf.AllowTimeout = ALLOW_CMD_TIMER; - cmdIf.CmdResp = (uint32_t *)&respValue[0]; - - while ( retryCount > 0 ) - { - /* Check current status */ - if((MCI_CheckStatus(CARD_STATE_TRAN) != MCI_FUNC_OK)) - return MCI_FUNC_ERR_STATE; - - respStatus = MCI_CmdResp(&cmdIf); - - if(respStatus) - { - retval = MCI_FUNC_FAILED; - } - else if (respValue[0] & CARD_STATUS_ERR_MASK) - { - return MCI_FUNC_BAD_PARAMETERS; - } - else - { - if((MCI_CheckStatus(CARD_STATE_RCV) != MCI_FUNC_OK) && - (MCI_CheckStatus(CARD_STATE_TRAN) != MCI_FUNC_OK)) - return MCI_FUNC_ERR_STATE; - return MCI_FUNC_OK; - } - - - for ( i = 0; i < 0x20; i++ ); - - retryCount--; - - } - - return retval; /* Fatal error */ -} - - - - -/************************************************************************//** - * @brief Read blocks to card by sending CMD17 (READ_SINGLE_BLOCK) or - * CMD18 (READ_MULTIPLE_BLOCK) commands followed by the blocks of - * data to be read. - * - * @param[in] blockNum The block number to start reading - * - * @param[in] numOfBlock Determine how many blocks will be read (from the - * starting block) - * - * @return MCI_FUNC_OK if all success - * - * @note These commands should be sent in TRANS state. - ****************************************************************************/ -int32_t MCI_Cmd_ReadBlock(uint32_t blockNum, uint32_t numOfBlock) -{ - volatile uint32_t i; - uint32_t retryCount; - uint32_t respStatus; - uint32_t respValue[4]; - uint32_t commandID; - st_Mci_CmdInfo cmdIf; - int32_t retval = MCI_FUNC_FAILED; - - // To Do: Read Multi-Block - if (numOfBlock > 1) - commandID = CMD18_READ_MULTIPLE_BLOCK; - else - commandID = CMD17_READ_SINGLE_BLOCK; - - retryCount = 0x20; - cmdIf.CmdIndex = commandID; - if (MCI_CardType == MCI_SDHC_SDXC_CARD) - { - cmdIf.Argument = blockNum; /* Block Address */ - } - else - { - cmdIf.Argument = blockNum * BLOCK_LENGTH; /* Byte Address */ - } - cmdIf.ExpectResp = EXPECT_SHORT_RESP; - cmdIf.AllowTimeout = ALLOW_CMD_TIMER; - cmdIf.CmdResp = (uint32_t *)&respValue[0]; - while ( retryCount > 0 ) - { - /* Check current status */ - if((MCI_CheckStatus(CARD_STATE_TRAN) != MCI_FUNC_OK)) - return MCI_FUNC_ERR_STATE; - - respStatus = MCI_CmdResp(&cmdIf); - - if(respStatus) - { - retval = MCI_FUNC_FAILED; - } - else if (respValue[0] & CARD_STATUS_ERR_MASK) - { - return MCI_FUNC_BAD_PARAMETERS; - } - else - { - if((MCI_CheckStatus(CARD_STATE_DATA) != MCI_FUNC_OK) && - (MCI_CheckStatus(CARD_STATE_TRAN) != MCI_FUNC_OK)) - return MCI_FUNC_ERR_STATE; - return MCI_FUNC_OK; - } - - - for ( i = 0; i < 0x20; i++ ); - - retryCount--; - - } - - return retval; -} - - -/************************************************************************//** - * @brief Write data at a specific address to starting block with number - * of blocks will be written from first block - * @details - * - At preparation - * - Set MCI data control register, data length and data timeout - * - Send CMD24 (WRITE_BLOCK) or CMD25 (WRITE_MULTIPLE_BLOCK) - * commands to card - * - Enable interupt for MCI component - * - At completion - * - TX_ACTIVE interrupt is occured - * - Write data to FIFO register continuously until the data block - * length is reached - * - * @param[in] *memblock The pointer to location stored required data to be - * written to card - * - * @param[in] blockNum The block number to start writting - * - * @param[in] numOfBlock Determine how many blocks will be written (from the - * starting block) - * - * @return MCI_FUNC_OK if all success - ****************************************************************************/ -int32_t MCI_WriteBlock(volatile uint8_t* memblock, uint32_t blockNum, uint32_t numOfBlock) -{ - volatile uint32_t i; - uint32_t DataCtrl = 0; - - if(BLOCK_LENGTH*numOfBlock > DATA_RW_MAX_LEN) - return MCI_FUNC_BAD_PARAMETERS; - - dataSrcBlock = memblock; - - LPC_MCI->CLEAR = 0x7FF; - - LPC_MCI->DATACTRL = 0; - - for ( i = 0; i < 0x10; i++ ); - - /* Wait the SD Card enters to TRANS state. */ - if (MCI_CheckStatus(CARD_STATE_TRAN) != MCI_FUNC_OK) - return MCI_FUNC_ERR_STATE; - - LPC_MCI->DATATMR = DATA_TIMER_VALUE_W; - - LPC_MCI->DATALEN = BLOCK_LENGTH*numOfBlock; - - Mci_Data_Xfer_End = 1; - Mci_Data_Xfer_ERR = 0; - fifo_plane = 0; - - txBlockCnt = 0; - - MCI_TXEnable(); - - if (MCI_Cmd_WriteBlock(blockNum, numOfBlock) != MCI_FUNC_OK) - { - return ( MCI_FUNC_FAILED ); - } - - //for(blockCnt = 0; blockCnt < numOfBlock; blockCnt++) - { -#if MCI_DMA_ENABLED - MCI_SettingDma((uint8_t*) dataSrcBlock, MCI_DMA_WRITE_CHANNEL, GPDMA_TRANSFERTYPE_M2P_DEST_CTRL); - - /* Write, block transfer, DMA, and data length */ - DataCtrl |= MCI_DATACTRL_ENABLE | MCI_DATACTRL_DIR_TO_CARD - | MCI_DATACTRL_DMA_ENABLE | MCI_DTATCTRL_BLOCKSIZE(DATA_BLOCK_LEN); -#else - /* Write, block transfer, and data length */ - DataCtrl |= MCI_DATACTRL_ENABLE | MCI_DATACTRL_DIR_TO_CARD | MCI_DTATCTRL_BLOCKSIZE(DATA_BLOCK_LEN); -#endif - } - - LPC_MCI->DATACTRL = DataCtrl; - - for ( i = 0; i < 0x10; i++ ); - - return MCI_FUNC_OK; -} - - -/************************************************************************//** - * @brief Read data at a specific address to starting block with number - * of blocks will be read from first block - * - * @details - * - At preparation - * - Set MCI data control register, data length and data timeout - * - Send CMD17 (READ_SINGLE_BLOCK) or CMD18 (READ_MULTIPLE_BLOCK) - * commands to card - * - Enable interupt for MCI component - * - At completion - * - RX_ACTIVE interrupt is occured - * - Read data from FIFO register continuously until the data block - * length is reached to retrieve needed data - * - * @param[in] *destBlock The pointer to location will captured data read - * from card - * - * @param[in] blockNum The block number to start reading - * - * @param[in] numOfBlock Determine how many blocks will be read (from the - * starting block) - * - * @return MCI_FUNC_OK if all success - ****************************************************************************/ -int32_t MCI_ReadBlock(volatile uint8_t* destBlock, uint32_t blockNum, uint32_t numOfBlock) -{ - volatile uint32_t i; - uint32_t DataCtrl = 0; - - if(BLOCK_LENGTH*numOfBlock > DATA_RW_MAX_LEN) - return MCI_FUNC_BAD_PARAMETERS; - - dataDestBlock = destBlock; - - LPC_MCI->CLEAR = 0x7FF; - - LPC_MCI->DATACTRL = 0; - - for ( i = 0; i < 0x10; i++ ); - - /* Wait the SD Card enters to TRANS state. */ - if (MCI_CheckStatus(CARD_STATE_TRAN) != MCI_FUNC_OK) - return MCI_FUNC_ERR_STATE; - - MCI_RXEnable(); - - LPC_MCI->DATATMR = DATA_TIMER_VALUE_R; - - LPC_MCI->DATALEN = BLOCK_LENGTH*numOfBlock; - - Mci_Data_Xfer_End = 1; - Mci_Data_Xfer_ERR = 0; - rxBlockCnt = 0; - fifo_plane = 0; - - - // Start data engine on READ before command to avoid overflow of the FIFO. - { -#if MCI_DMA_ENABLED - MCI_SettingDma((uint8_t*) dataDestBlock, MCI_DMA_READ_CHANNEL, GPDMA_TRANSFERTYPE_P2M_SRC_CTRL); - - /* Write, block transfer, DMA, and data length */ - DataCtrl |= MCI_DATACTRL_ENABLE | MCI_DATACTRL_DIR_FROM_CARD - | MCI_DATACTRL_DMA_ENABLE | MCI_DTATCTRL_BLOCKSIZE(DATA_BLOCK_LEN); -#else - //Retrieving the result after reading the card is done by the FIFO handling for interrupt - - /* Read, enable, block transfer, and data length */ - DataCtrl |= MCI_DATACTRL_ENABLE | MCI_DATACTRL_DIR_FROM_CARD | MCI_DTATCTRL_BLOCKSIZE(DATA_BLOCK_LEN); - -#endif - } - - LPC_MCI->DATACTRL = DataCtrl; - - for ( i = 0; i < 0x10; i++ ); - - if ( MCI_Cmd_ReadBlock(blockNum, numOfBlock) != MCI_FUNC_OK ) - { - return MCI_FUNC_FAILED; - } - - return MCI_FUNC_OK; -} - - -/************************************************************************//** - * @brief Turn off the MCI power by disabling the Power Register for MCI - * - * @param None - * - * @return None - ****************************************************************************/ -void MCI_PowerOff(void) -{ - volatile uint32_t i; - - LPC_MCI->POWER = 0; - - for (i = 0; i < 0x100; i++); - - return; -} - - -/** - * @} - */ - -#endif /*_MCI*/ - -/***************************************************************************** -** End Of File -******************************************************************************/ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_mcpwm.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_mcpwm.c deleted file mode 100644 index 479ec4d9a4f..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_mcpwm.c +++ /dev/null @@ -1,573 +0,0 @@ -/********************************************************************** -* $Id$ lpc_mcpwm.c 2011-06-02 -*//** -* @file lpc_mcpwm.c -* @brief Contains all functions support for Motor Control PWM -* firmware library on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup MCPWM - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _MCPWM - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_mcpwm.h" -#include "lpc_clkpwr.h" - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup MCPWM_Public_Functions - * @{ - */ - -/*********************************************************************//** - * @brief Initializes the MCPWM peripheral - * @param[in] MCPWMx Motor Control PWM peripheral selected, - * Should be: LPC_MCPWM - * @return None - **********************************************************************/ -void MCPWM_Init(LPC_MCPWM_TypeDef *MCPWMx) -{ - /* Turn On MCPWM PCLK */ - CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCMCPWM, ENABLE); - - MCPWMx->CAP_CLR = MCPWM_CAPCLR_CAP(0) | MCPWM_CAPCLR_CAP(1) | MCPWM_CAPCLR_CAP(2); - - MCPWMx->INTF_CLR = MCPWM_INT_ILIM(0) | MCPWM_INT_ILIM(1) | MCPWM_INT_ILIM(2) \ - | MCPWM_INT_IMAT(0) | MCPWM_INT_IMAT(1) | MCPWM_INT_IMAT(2) \ - | MCPWM_INT_ICAP(0) | MCPWM_INT_ICAP(1) | MCPWM_INT_ICAP(2); - - MCPWMx->INTEN_CLR = MCPWM_INT_ILIM(0) | MCPWM_INT_ILIM(1) | MCPWM_INT_ILIM(2) \ - | MCPWM_INT_IMAT(0) | MCPWM_INT_IMAT(1) | MCPWM_INT_IMAT(2) \ - | MCPWM_INT_ICAP(0) | MCPWM_INT_ICAP(1) | MCPWM_INT_ICAP(2); -} - - -/*********************************************************************//** - * @brief Configures each channel in MCPWM peripheral according to the - * specified parameters in the MCPWM_CHANNEL_CFG_Type. - * @param[in] MCPWMx Motor Control PWM peripheral selected - * should be: LPC_MCPWM - * @param[in] channelNum Channel number, should be: 0..2. - * @param[in] channelSetup Pointer to a MCPWM_CHANNEL_CFG_Type structure -* that contains the configuration information for the -* specified MCPWM channel. - * @return None - **********************************************************************/ -void MCPWM_ConfigChannel(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum, - MCPWM_CHANNEL_CFG_Type * channelSetup) -{ - if (channelNum < MCPWM_MAX_CHANNEL) - { - if (channelNum == MCPWM_CHANNEL_0) - { - MCPWMx->TC0 = channelSetup->channelTimercounterValue; - MCPWMx->LIM0 = channelSetup->channelPeriodValue; - MCPWMx->MAT0 = channelSetup->channelPulsewidthValue; - } - else if (channelNum == MCPWM_CHANNEL_1) - { - MCPWMx->TC1 = channelSetup->channelTimercounterValue; - MCPWMx->LIM1 = channelSetup->channelPeriodValue; - MCPWMx->MAT1 = channelSetup->channelPulsewidthValue; - } - else if (channelNum == MCPWM_CHANNEL_2) - { - MCPWMx->TC2 = channelSetup->channelTimercounterValue; - MCPWMx->LIM2 = channelSetup->channelPeriodValue; - MCPWMx->MAT2 = channelSetup->channelPulsewidthValue; - } - else - { - return; - } - - if (channelSetup->channelType == MCPWM_CHANNEL_CENTER_MODE) - { - MCPWMx->CON_SET = MCPWM_CON_CENTER(channelNum); - } - else - { - MCPWMx->CON_CLR = MCPWM_CON_CENTER(channelNum); - } - - if (channelSetup->channelPolarity == MCPWM_CHANNEL_PASSIVE_HI) - { - MCPWMx->CON_SET = MCPWM_CON_POLAR(channelNum); - } - else - { - MCPWMx->CON_CLR = MCPWM_CON_POLAR(channelNum); - } - - if (channelSetup->channelDeadtimeEnable == ENABLE) - { - MCPWMx->CON_SET = MCPWM_CON_DTE(channelNum); - - MCPWMx->DT &= ~(MCPWM_DT(channelNum, 0x3FF)); - - MCPWMx->DT |= MCPWM_DT(channelNum, channelSetup->channelDeadtimeValue); - } - else - { - MCPWMx->CON_CLR = MCPWM_CON_DTE(channelNum); - } - - if (channelSetup->channelUpdateEnable == ENABLE) - { - MCPWMx->CON_CLR = MCPWM_CON_DISUP(channelNum); - } - else - { - MCPWMx->CON_SET = MCPWM_CON_DISUP(channelNum); - } - } -} - - -/*********************************************************************//** - * @brief Write to MCPWM shadow registers - Update the value for period - * and pulse width in MCPWM peripheral. - * @param[in] MCPWMx Motor Control PWM peripheral selected - * Should be: LPC_MCPWM - * @param[in] channelNum Channel Number, should be: 0..2. - * @param[in] channelSetup Pointer to a MCPWM_CHANNEL_CFG_Type structure -* that contains the configuration information for the -* specified MCPWM channel. - * @return None - **********************************************************************/ -void MCPWM_WriteToShadow(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum, - MCPWM_CHANNEL_CFG_Type *channelSetup) -{ - if (channelNum == MCPWM_CHANNEL_0) - { - MCPWMx->LIM0 = channelSetup->channelPeriodValue; - MCPWMx->MAT0 = channelSetup->channelPulsewidthValue; - } - else if (channelNum == MCPWM_CHANNEL_1) - { - MCPWMx->LIM1 = channelSetup->channelPeriodValue; - MCPWMx->MAT1 = channelSetup->channelPulsewidthValue; - } - else if (channelNum == MCPWM_CHANNEL_2) - { - MCPWMx->LIM2 = channelSetup->channelPeriodValue; - MCPWMx->MAT2 = channelSetup->channelPulsewidthValue; - } -} - - - -/*********************************************************************//** - * @brief Configures capture function in MCPWM peripheral - * @param[in] MCPWMx Motor Control PWM peripheral selected - * Should be: LPC_MCPWM - * @param[in] channelNum MCI (Motor Control Input pin) number - * Should be: 0..2 - * @param[in] captureConfig Pointer to a MCPWM_CAPTURE_CFG_Type structure -* that contains the configuration information for the -* specified MCPWM capture. - * @return - **********************************************************************/ -void MCPWM_ConfigCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum, - MCPWM_CAPTURE_CFG_Type *captureConfig) -{ - if (channelNum < MCPWM_MAX_CHANNEL) - { - - if (captureConfig->captureFalling == ENABLE) - { - MCPWMx->CAPCON_SET = MCPWM_CAPCON_CAPMCI_FE(captureConfig->captureChannel, channelNum); - } - else - { - MCPWMx->CAPCON_CLR = MCPWM_CAPCON_CAPMCI_FE(captureConfig->captureChannel, channelNum); - } - - if (captureConfig->captureRising == ENABLE) - { - MCPWMx->CAPCON_SET = MCPWM_CAPCON_CAPMCI_RE(captureConfig->captureChannel, channelNum); - } - else - { - MCPWMx->CAPCON_CLR = MCPWM_CAPCON_CAPMCI_RE(captureConfig->captureChannel, channelNum); - } - - if (captureConfig->timerReset == ENABLE) - { - MCPWMx->CAPCON_SET = MCPWM_CAPCON_RT(captureConfig->captureChannel); - } - else - { - MCPWMx->CAPCON_CLR = MCPWM_CAPCON_RT(captureConfig->captureChannel); - } - - if (captureConfig->hnfEnable == ENABLE) - { - MCPWMx->CAPCON_SET = MCPWM_CAPCON_HNFCAP(channelNum); - } - else - { - MCPWMx->CAPCON_CLR = MCPWM_CAPCON_HNFCAP(channelNum); - } - } -} - - -/*********************************************************************//** - * @brief Clears current captured value in specified capture channel - * @param[in] MCPWMx Motor Control PWM peripheral selected - * Should be: LPC_MCPWM - * @param[in] captureChannel Capture channel number, should be: 0..2 - * @return None - **********************************************************************/ -void MCPWM_ClearCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel) -{ - MCPWMx->CAP_CLR = MCPWM_CAPCLR_CAP(captureChannel); -} - -/*********************************************************************//** - * @brief Get current captured value in specified capture channel - * @param[in] MCPWMx Motor Control PWM peripheral selected, - * Should be: LPC_MCPWM - * @param[in] captureChannel Capture channel number, should be: 0..2 - * @return None - **********************************************************************/ -uint32_t MCPWM_GetCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel) -{ - if (captureChannel == MCPWM_CHANNEL_0) - { - return (MCPWMx->CAP0); - } - else if (captureChannel == MCPWM_CHANNEL_1) - { - return (MCPWMx->CAP1); - } - else if (captureChannel == MCPWM_CHANNEL_2) - { - return (MCPWMx->CAP2); - } - return (0); -} - - -/*********************************************************************//** - * @brief Configures Count control in MCPWM peripheral - * @param[in] MCPWMx Motor Control PWM peripheral selected - * Should be: LPC_MCPWM - * @param[in] channelNum Channel number, should be: 0..2 - * @param[in] countMode Count mode, should be: - * - ENABLE: Enables count mode. - * - DISABLE: Disable count mode, the channel is in timer mode. - * @param[in] countConfig Pointer to a MCPWM_COUNT_CFG_Type structure -* that contains the configuration information for the -* specified MCPWM count control. - * @return None - **********************************************************************/ -void MCPWM_CountConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum, - uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig) -{ - if (channelNum < MCPWM_MAX_CHANNEL) - { - if (countMode == ENABLE) - { - MCPWMx->CNTCON_SET = MCPWM_CNTCON_CNTR(channelNum); - - if (countConfig->countFalling == ENABLE) - { - MCPWMx->CNTCON_SET = MCPWM_CNTCON_TCMCI_FE(countConfig->counterChannel,channelNum); - } - else - { - MCPWMx->CNTCON_CLR = MCPWM_CNTCON_TCMCI_FE(countConfig->counterChannel,channelNum); - } - - if (countConfig->countRising == ENABLE) - { - MCPWMx->CNTCON_SET = MCPWM_CNTCON_TCMCI_RE(countConfig->counterChannel,channelNum); - } - else - { - MCPWMx->CNTCON_CLR = MCPWM_CNTCON_TCMCI_RE(countConfig->counterChannel,channelNum); - } - } - else - { - MCPWMx->CNTCON_CLR = MCPWM_CNTCON_CNTR(channelNum); - } - } -} - - -/*********************************************************************//** - * @brief Start MCPWM activity for each MCPWM channel - * @param[in] MCPWMx Motor Control PWM peripheral selected - * Should be: LPC_MCPWM - * @param[in] channel0 State of this command on channel 0: - * - ENABLE: 'Start' command will effect on channel 0 - * - DISABLE: 'Start' command will not effect on channel 0 - * @param[in] channel1 State of this command on channel 1: - * - ENABLE: 'Start' command will effect on channel 1 - * - DISABLE: 'Start' command will not effect on channel 1 - * @param[in] channel2 State of this command on channel 2: - * - ENABLE: 'Start' command will effect on channel 2 - * - DISABLE: 'Start' command will not effect on channel 2 - * @return None - **********************************************************************/ -void MCPWM_Start(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channel0, - uint32_t channel1, uint32_t channel2) -{ - uint32_t regVal = 0; - - regVal = (channel0 ? MCPWM_CON_RUN(0) : 0) | (channel1 ? MCPWM_CON_RUN(1) : 0) \ - | (channel2 ? MCPWM_CON_RUN(2) : 0); - - MCPWMx->CON_SET = regVal; -} - - -/*********************************************************************//** - * @brief Stop MCPWM activity for each MCPWM channel - * @param[in] MCPWMx Motor Control PWM peripheral selected - * Should be: LPC_MCPWM - * @param[in] channel0 State of this command on channel 0: - * - ENABLE: 'Stop' command will effect on channel 0 - * - DISABLE: 'Stop' command will not effect on channel 0 - * @param[in] channel1 State of this command on channel 1: - * - ENABLE: 'Stop' command will effect on channel 1 - * - DISABLE: 'Stop' command will not effect on channel 1 - * @param[in] channel2 State of this command on channel 2: - * - ENABLE: 'Stop' command will effect on channel 2 - * - DISABLE: 'Stop' command will not effect on channel 2 - * @return None - **********************************************************************/ -void MCPWM_Stop(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channel0, - uint32_t channel1, uint32_t channel2) -{ - uint32_t regVal = 0; - - regVal = (channel0 ? MCPWM_CON_RUN(0) : 0) | (channel1 ? MCPWM_CON_RUN(1) : 0) \ - | (channel2 ? MCPWM_CON_RUN(2) : 0); - - MCPWMx->CON_CLR = regVal; -} - - -/*********************************************************************//** - * @brief Enables/Disables 3-phase AC motor mode on MCPWM peripheral - * @param[in] MCPWMx Motor Control PWM peripheral selected - * Should be: LPC_MCPWM - * @param[in] acMode State of this command, should be: - * - ENABLE. - * - DISABLE. - * @return None - **********************************************************************/ -void MCPWM_ACMode(LPC_MCPWM_TypeDef *MCPWMx, uint32_t acMode) -{ - if (acMode) - { - MCPWMx->CON_SET = MCPWM_CON_ACMODE; - } - else - { - MCPWMx->CON_CLR = MCPWM_CON_ACMODE; - } -} - - -/*********************************************************************//** - * @brief Enables/Disables 3-phase DC motor mode on MCPWM peripheral - * @param[in] MCPWMx Motor Control PWM peripheral selected - * Should be: LPC_MCPWM - * @param[in] dcMode State of this command, should be: - * - ENABLE. - * - DISABLE. - * @param[in] outputInvered Polarity of the MCOB outputs for all 3 channels, - * should be: - * - ENABLE: The MCOB outputs have opposite polarity - * from the MCOA outputs. - * - DISABLE: The MCOB outputs have the same basic - * polarity as the MCOA outputs. - * @param[in] outputPattern A value contains bits that enables/disables the specified - * output pins route to the internal MCOA0 signal, should be: - - MCPWM_PATENT_A0: MCOA0 tracks internal MCOA0 - - MCPWM_PATENT_B0: MCOB0 tracks internal MCOA0 - - MCPWM_PATENT_A1: MCOA1 tracks internal MCOA0 - - MCPWM_PATENT_B1: MCOB1 tracks internal MCOA0 - - MCPWM_PATENT_A2: MCOA2 tracks internal MCOA0 - - MCPWM_PATENT_B2: MCOB2 tracks internal MCOA0 - * @return None - * - * Note: all these outputPatent values above can be ORed together for using as input parameter. - **********************************************************************/ -void MCPWM_DCMode(LPC_MCPWM_TypeDef *MCPWMx, uint32_t dcMode, - uint32_t outputInvered, uint32_t outputPattern) -{ - if (dcMode) - { - MCPWMx->CON_SET = MCPWM_CON_DCMODE; - } - else - { - MCPWMx->CON_CLR = MCPWM_CON_DCMODE; - } - - if (outputInvered) - { - MCPWMx->CON_SET = MCPWM_CON_INVBDC; - } - else - { - MCPWMx->CON_CLR = MCPWM_CON_INVBDC; - } - - MCPWMx->CP = outputPattern; -} - - -/*********************************************************************//** - * @brief Configures the specified interrupt in MCPWM peripheral - * @param[in] MCPWMx Motor Control PWM peripheral selected - * Should be: LPC_MCPWM - * @param[in] ulIntType Interrupt type, should be: - * - MCPWM_INTFLAG_LIM0: Limit interrupt for channel (0) - * - MCPWM_INTFLAG_MAT0: Match interrupt for channel (0) - * - MCPWM_INTFLAG_CAP0: Capture interrupt for channel (0) - * - MCPWM_INTFLAG_LIM1: Limit interrupt for channel (1) - * - MCPWM_INTFLAG_MAT1: Match interrupt for channel (1) - * - MCPWM_INTFLAG_CAP1: Capture interrupt for channel (1) - * - MCPWM_INTFLAG_LIM2: Limit interrupt for channel (2) - * - MCPWM_INTFLAG_MAT2: Match interrupt for channel (2) - * - MCPWM_INTFLAG_CAP2: Capture interrupt for channel (2) - * - MCPWM_INTFLAG_ABORT: Fast abort interrupt - * @param[in] NewState New State of this command, should be: - * - ENABLE. - * - DISABLE. - * @return None - * - * Note: all these ulIntType values above can be ORed together for using as input parameter. - **********************************************************************/ -void MCPWM_IntConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType, FunctionalState NewState) -{ - if (NewState) - { - MCPWMx->INTEN_SET = ulIntType; - } - else - { - MCPWMx->INTEN_CLR = ulIntType; - } -} - - -/*********************************************************************//** - * @brief Sets/Forces the specified interrupt for MCPWM peripheral - * @param[in] MCPWMx Motor Control PWM peripheral selected - * Should be LPC_MCPWM - * @param[in] ulIntType Interrupt type, should be: - * - MCPWM_INTFLAG_LIM0: Limit interrupt for channel (0) - * - MCPWM_INTFLAG_MAT0: Match interrupt for channel (0) - * - MCPWM_INTFLAG_CAP0: Capture interrupt for channel (0) - * - MCPWM_INTFLAG_LIM1: Limit interrupt for channel (1) - * - MCPWM_INTFLAG_MAT1: Match interrupt for channel (1) - * - MCPWM_INTFLAG_CAP1: Capture interrupt for channel (1) - * - MCPWM_INTFLAG_LIM2: Limit interrupt for channel (2) - * - MCPWM_INTFLAG_MAT2: Match interrupt for channel (2) - * - MCPWM_INTFLAG_CAP2: Capture interrupt for channel (2) - * - MCPWM_INTFLAG_ABORT: Fast abort interrupt - * @return None - * Note: all these ulIntType values above can be ORed together for using as input parameter. - **********************************************************************/ -void MCPWM_IntSet(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType) -{ - MCPWMx->INTF_SET = ulIntType; -} - - -/*********************************************************************//** - * @brief Clear the specified interrupt pending for MCPWM peripheral - * @param[in] MCPWMx Motor Control PWM peripheral selected, - * should be: LPC_MCPWM - * @param[in] ulIntType Interrupt type, should be: - * - MCPWM_INTFLAG_LIM0: Limit interrupt for channel (0) - * - MCPWM_INTFLAG_MAT0: Match interrupt for channel (0) - * - MCPWM_INTFLAG_CAP0: Capture interrupt for channel (0) - * - MCPWM_INTFLAG_LIM1: Limit interrupt for channel (1) - * - MCPWM_INTFLAG_MAT1: Match interrupt for channel (1) - * - MCPWM_INTFLAG_CAP1: Capture interrupt for channel (1) - * - MCPWM_INTFLAG_LIM2: Limit interrupt for channel (2) - * - MCPWM_INTFLAG_MAT2: Match interrupt for channel (2) - * - MCPWM_INTFLAG_CAP2: Capture interrupt for channel (2) - * - MCPWM_INTFLAG_ABORT: Fast abort interrupt - * @return None - * Note: all these ulIntType values above can be ORed together for using as input parameter. - **********************************************************************/ -void MCPWM_IntClear(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType) -{ - MCPWMx->INTF_CLR = ulIntType; -} - - -/*********************************************************************//** - * @brief Check whether if the specified interrupt in MCPWM is set or not - * @param[in] MCPWMx Motor Control PWM peripheral selected, - * should be: LPC_MCPWM - * @param[in] ulIntType Interrupt type, should be: - * - MCPWM_INTFLAG_LIM0: Limit interrupt for channel (0) - * - MCPWM_INTFLAG_MAT0: Match interrupt for channel (0) - * - MCPWM_INTFLAG_CAP0: Capture interrupt for channel (0) - * - MCPWM_INTFLAG_LIM1: Limit interrupt for channel (1) - * - MCPWM_INTFLAG_MAT1: Match interrupt for channel (1) - * - MCPWM_INTFLAG_CAP1: Capture interrupt for channel (1) - * - MCPWM_INTFLAG_LIM2: Limit interrupt for channel (2) - * - MCPWM_INTFLAG_MAT2: Match interrupt for channel (2) - * - MCPWM_INTFLAG_CAP2: Capture interrupt for channel (2) - * - MCPWM_INTFLAG_ABORT: Fast abort interrupt - * @return None - **********************************************************************/ -FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType) -{ - return ((MCPWMx->INTF & ulIntType) ? SET : RESET); -} - -/** - * @} - */ - -#endif /*_MCPWM*/ -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_nvic.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_nvic.c deleted file mode 100644 index 3de1316a822..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_nvic.c +++ /dev/null @@ -1,156 +0,0 @@ -/********************************************************************** -* $Id$ lpc_nvic.c 2011-06-02 -*//** -* @file lpc_nvic.c -* @brief Contains all expansion functions support for Nesting -* Vectored Interrupt Controller (NVIC) firmware library -* on LPC. The main NVIC functions are defined -* in core_cm3.h -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup NVIC - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _NVIC - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_nvic.h" - - -/* Private Macros ------------------------------------------------------------- */ -/** @defgroup NVIC_Private_Macros NVIC Private Macros - * @{ - */ - -/* Vector table offset bit mask */ -#define NVIC_VTOR_MASK 0x3FFFFF80 - -/** - * @} - */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup NVIC_Public_Functions - * @{ - */ - - -/*****************************************************************************//** - * @brief De-initializes the NVIC peripheral registers to their default - * reset values. - * @param None - * @return None - * - * These following NVIC peripheral registers will be de-initialized: - * - Disable Interrupt (32 IRQ interrupt sources that matched with LPC178X) - * - Clear all Pending Interrupts (32 IRQ interrupt source that matched with LPC178X) - * - Clear all Interrupt Priorities (32 IRQ interrupt source that matched with LPC178X) - *******************************************************************************/ -void NVIC_DeInit(void) -{ - uint8_t tmp; - - /* Disable all interrupts */ - NVIC->ICER[0] = 0xFFFFFFFF; - NVIC->ICER[1] = 0x00000001; - /* Clear all pending interrupts */ - NVIC->ICPR[0] = 0xFFFFFFFF; - NVIC->ICPR[1] = 0x00000001; - - /* Clear all interrupt priority */ - for (tmp = 0; tmp < 32; tmp++) { - NVIC->IP[tmp] = 0x00; - } -} - -/*****************************************************************************//** - * @brief De-initializes the SCB peripheral registers to their default - * reset values. - * @param none - * @return none - * - * These following SCB NVIC peripheral registers will be de-initialized: - * - Interrupt Control State register - * - Interrupt Vector Table Offset register - * - Application Interrupt/Reset Control register - * - System Control register - * - Configuration Control register - * - System Handlers Priority Registers - * - System Handler Control and State Register - * - Configurable Fault Status Register - * - Hard Fault Status Register - * - Debug Fault Status Register - *******************************************************************************/ -void NVIC_SCBDeInit(void) -{ - uint8_t tmp; - - SCB->ICSR = 0x0A000000; - SCB->VTOR = 0x00000000; - SCB->AIRCR = 0x05FA0000; - SCB->SCR = 0x00000000; - SCB->CCR = 0x00000000; - - for (tmp = 0; tmp < 32; tmp++) { - SCB->SHP[tmp] = 0x00; - } - - SCB->SHCSR = 0x00000000; - SCB->CFSR = 0xFFFFFFFF; - SCB->HFSR = 0xFFFFFFFF; - SCB->DFSR = 0xFFFFFFFF; -} - - -/*****************************************************************************//** - * @brief Set Vector Table Offset value - * @param offset Offset value - * @return None - *******************************************************************************/ -void NVIC_SetVTOR(uint32_t offset) -{ -// SCB->VTOR = (offset & NVIC_VTOR_MASK); - SCB->VTOR = offset; -} - -/** - * @} - */ - -#endif /*_NVIC*/ -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_pinsel.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_pinsel.c deleted file mode 100644 index 61809f5bd67..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_pinsel.c +++ /dev/null @@ -1,540 +0,0 @@ -/********************************************************************** -* $Id$ lpc_pinsel.c 2011-06-02 -*//** -* @file lpc_pinsel.c -* @brief Contains all functions support for Pin-connection block -* firmware library on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup PINSEL - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _PINSEL - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_pinsel.h" - -/* Private Functions ---------------------------------------------------------- */ - -/*********************************************************************//** - * @brief Get pointer to GPIO peripheral due to GPIO port - * @param[in] portnum Port Number value, should be in range from 0..3. - * @param[in] pinnum Pin number value, should be in range from 0..31 - * @return Pointer to GPIO peripheral - **********************************************************************/ -static uint32_t * PIN_GetPointer(uint8_t portnum, uint8_t pinnum) -{ - uint32_t *pPIN = NULL; - pPIN = (uint32_t *)(LPC_IOCON_BASE + ((portnum * 32 + pinnum)*sizeof(uint32_t))); - return pPIN; -} - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup PINSEL_Public_Functions - * @{ - */ - -/*********************************************************************//** - * @brief Get type of a pin. - * @param[in] portnum PORT number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @return Port type: - * - PINSEL_PIN_TYPE_D - * - PINSEL_PIN_TYPE_A - * - PINSEL_PIN_TYPE_I - * - PINSEL_PIN_TYPE_W - * - PINSEL_PIN_TYPE_U - * - PINSEL_PIN_TYPE_UNKNOWN: Invalid pin - **********************************************************************/ -PinSel_PinType PINSEL_GetPinType(uint8_t portnum, uint8_t pinnum) -{ - PinSel_PinType Ret = PINSEL_PIN_TYPE_UNKNOWN; - switch(portnum) - { - case 0: - if((pinnum <=6)|| - ((pinnum >= 10)&&(pinnum <=11))|| - ((pinnum >= 14)&&(pinnum <=22))) - Ret = PINSEL_PIN_TYPE_D; - else if ((pinnum == 12)||(pinnum==13)|| - ((pinnum >= 23)&&(pinnum <=26))) - Ret = PINSEL_PIN_TYPE_A; - else if ((pinnum == 29) || (pinnum==30)|| (pinnum==31)) - Ret = PINSEL_PIN_TYPE_U; - else if ((pinnum == 27) || (pinnum==28)) - Ret = PINSEL_PIN_TYPE_I; - else if ((pinnum == 7) || (pinnum==8)|| (pinnum==9)) - Ret = PINSEL_PIN_TYPE_W; - break; - case 1: - if(pinnum <=29) - Ret = PINSEL_PIN_TYPE_D; - else if ((pinnum == 30) || (pinnum==31)) - Ret = PINSEL_PIN_TYPE_A; - break; - case 2: - case 3: - case 4: - Ret = PINSEL_PIN_TYPE_D; - break; - case 5: - if((pinnum <=1)|| - (pinnum == 4)) - Ret = PINSEL_PIN_TYPE_D; - else if ((pinnum == 2) || (pinnum==3)) - Ret = PINSEL_PIN_TYPE_I; - break; - default: - break; - } - - return Ret; -} - -/*********************************************************************//** - * @brief Setup the pin selection function - * @param[in] portnum PORT number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @param[in] funcnum Function number, should be range: 0..7 - * - 0: Select GPIO (Default) - * - 1: Selects the 1st alternate function - * - 2: Selects the 2nd alternate function - * ... - * - 7: Selects the 7th alternate function - * @return PINSEL Return Code - * - PINSEL_RET_INVALID_PIN - * - PINSEL_RET_OK - **********************************************************************/ -PINSEL_RET_CODE PINSEL_ConfigPin ( uint8_t portnum, uint8_t pinnum, uint8_t funcnum) -{ - uint32_t *pPIN = NULL; - PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum); - - if(type == PINSEL_PIN_TYPE_UNKNOWN) - return PINSEL_RET_INVALID_PIN; - - pPIN = PIN_GetPointer(portnum, pinnum); - *pPIN &= ~IOCON_FUNC_MASK;//Clear function bits - *pPIN |= funcnum&IOCON_FUNC_MASK; - - return PINSEL_RET_OK; -} - - -/*********************************************************************//** - * @brief Setup resistor mode for pin of type D,A,W - * @param[in] portnum PORT number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @param[in] modenum: Mode number, should be in range: 0..3 - - PINSEL_BASICMODE_PLAINOUT: Plain output - - PINSEL_BASICMODE_PULLDOWN: Pull-down enable - - PINSEL_BASICMODE_PULLUP: Pull-up enable - - PINSEL_BASICMODE_REPEATER: Repeater mode - * @return PINSEL Return Code - * - PINSEL_RET_INVALID_PIN - * - PINSEL_RET_NOT_SUPPORT - * - PINSEL_RET_OK - **********************************************************************/ -PINSEL_RET_CODE PINSEL_SetPinMode ( uint8_t portnum, uint8_t pinnum, PinSel_BasicMode modenum) -{ - uint32_t *pPIN = NULL; - PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum); - - if(type == PINSEL_PIN_TYPE_UNKNOWN) - return PINSEL_RET_INVALID_PIN; - if((type != PINSEL_PIN_TYPE_D )&& - (type != PINSEL_PIN_TYPE_A )&& - (type != PINSEL_PIN_TYPE_W)) - return PINSEL_RET_NOT_SUPPORT; - - pPIN = PIN_GetPointer(portnum, pinnum); - *(uint32_t *)pPIN &= ~(IOCON_MODE_MASK);//Clear function bits - *(uint32_t *)pPIN |= (modenum << IOCON_MODE_POS)&IOCON_MODE_MASK; - - return PINSEL_RET_OK; -} - -/*********************************************************************//** - * @brief Setup hysteresis for pin of type D, W - * @param[in] portnum Port number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @param[in] NewState new state of Hysteresis mode, should be: - * - ENABLE: Hysteresis enable - * - DISABLE: Hysteresis disable - * @return PINSEL Return Code - * - PINSEL_RET_INVALID_PIN - * - PINSEL_RET_NOT_SUPPORT - * - PINSEL_RET_OK - **********************************************************************/ -PINSEL_RET_CODE PINSEL_SetHysMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState) -{ - uint32_t *pPIN = NULL; - PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum); - - if(type == PINSEL_PIN_TYPE_UNKNOWN) - return PINSEL_RET_INVALID_PIN; - if((type != PINSEL_PIN_TYPE_D )&& - (type != PINSEL_PIN_TYPE_W)) - return PINSEL_RET_NOT_SUPPORT; - - pPIN = PIN_GetPointer(portnum, pinnum); - if(NewState == DISABLE) - { - *(uint32_t *)pPIN &= ~IOCON_HYS_ENABLE;//Clear hys bits - } - else - *(uint32_t *)pPIN |= IOCON_HYS_ENABLE; - - return PINSEL_RET_OK; -} -/*********************************************************************//** - * @brief Setup input polarity for pin of type A,I,D,W - * @param[in] portnum Port number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @param[in] NewState new state of Invert mode, should be: - * - ENABLE: Input is inverted. - * - DISABLE: Input isn't inverted. - * @return PINSEL Return Code - * - PINSEL_RET_INVALID_PIN - * - PINSEL_RET_NOT_SUPPORT - * - PINSEL_RET_OK - **********************************************************************/ -PINSEL_RET_CODE PINSEL_SetInvertInput(uint8_t portnum, uint8_t pinnum, FunctionalState NewState) -{ - uint32_t *pPIN = NULL; - PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum); - - if(type == PINSEL_PIN_TYPE_UNKNOWN) - return PINSEL_RET_INVALID_PIN; - if(type== PINSEL_PIN_TYPE_U) - return PINSEL_RET_NOT_SUPPORT; - - pPIN = PIN_GetPointer(portnum, pinnum); - if(NewState == DISABLE) - { - *(uint32_t *)pPIN &= ~IOCON_INVERT_INPUT;//Clear hys bits - } - else - *(uint32_t *)pPIN |= IOCON_INVERT_INPUT; - - return PINSEL_RET_OK; -} - -/*********************************************************************//** - * @brief Setup Slew rate for pin of type D,W - * @param[in] portnum Port number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @param[in] NewState new state of Slew rate control, should be: - * - ENABLE: Output slew rate control is enable - * - DISABLE: Output slew rate control is disable - * @return PINSEL Return Code - * - PINSEL_RET_INVALID_PIN - * - PINSEL_RET_NOT_SUPPORT - * - PINSEL_RET_OK - **********************************************************************/ -PINSEL_RET_CODE PINSEL_SetSlewMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState) -{ - uint32_t *pPIN = NULL; - PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum); - - if(type == PINSEL_PIN_TYPE_UNKNOWN) - return PINSEL_RET_INVALID_PIN; - if((type!= PINSEL_PIN_TYPE_D) && - (type!= PINSEL_PIN_TYPE_W)) - return PINSEL_RET_NOT_SUPPORT; - - pPIN = PIN_GetPointer(portnum, pinnum); - if(NewState == DISABLE) - { - *(uint32_t *)pPIN &= ~IOCON_SLEW_ENABLE;//Clear hys bits - } - else - *(uint32_t *)pPIN |= IOCON_SLEW_ENABLE; - - return PINSEL_RET_OK; -} - -/*********************************************************************//** - * @brief Setup I2CMode for only pins that provide special I2C functionality - * @param[in] portnum Port number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @param[in] I2CMode I2C mode, should be: - * - PINSEL_I2CMODE_FAST_STANDARD: Fast mode and standard I2C mode - * - PINSEL_I2CMODE_OPENDRAINIO: Open drain I/O - * - PINSEL_I2CMODE_FASTMODEPLUS: Fast Mode Plus I/O - * @return PINSEL Return Code - * - PINSEL_RET_INVALID_PIN - * - PINSEL_RET_NOT_SUPPORT - * - PINSEL_RET_OK - **********************************************************************/ -PINSEL_RET_CODE PINSEL_SetI2CMode(uint8_t portnum, uint8_t pinnum, PinSel_I2cMode I2CMode) -{ - uint32_t *pPIN = NULL; - PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum); - - if(type == PINSEL_PIN_TYPE_UNKNOWN) - return PINSEL_RET_INVALID_PIN; - if(type != PINSEL_PIN_TYPE_I ) - return PINSEL_RET_NOT_SUPPORT; - - pPIN = PIN_GetPointer(portnum, pinnum); - - switch(I2CMode) - { - // Standard/Fast Mode I2C: HS = HIDRIVE = 0 - case PINSEL_I2CMODE_FAST_STANDARD: - PINSEL_SetI2CFilter(portnum,pinnum,ENABLE); - *(uint32_t *)pPIN &= ~(IOCON_I2CMODE_FASTPLUS); - break; - - // Non-I2C: HS = 1, HIDRIVE = 0 - case PINSEL_I2CMODE_OPENDRAINIO: - PINSEL_SetI2CFilter(portnum,pinnum,DISABLE); - *(uint32_t *)pPIN &= ~(IOCON_I2CMODE_FASTPLUS); - break; - - // Fast Mode Plus I2C: HS = 0, HIDRIVE =1 - case PINSEL_I2CMODE_FASTMODEPLUS: - PINSEL_SetI2CFilter(portnum,pinnum,ENABLE); - *(uint32_t *)pPIN |= (IOCON_I2CMODE_FASTPLUS); - break; - default: - return PINSEL_RET_ERR; - } - - return PINSEL_RET_OK; -} - -/*********************************************************************//** - * @brief Setup Open-drain mode in pin of type D, A, W - * @param[in] portnum Port number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @param[in] NewState new state of Open-drain mode: - * - DISABLE: Normal pin I/O mode - * - ENABLE: Open-drain enable - * @return PINSEL Return Code - * - PINSEL_RET_INVALID_PIN - * - PINSEL_RET_NOT_SUPPORT - * - PINSEL_RET_OK - **********************************************************************/ -PINSEL_RET_CODE PINSEL_SetOpenDrainMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState) -{ - uint32_t *pPIN = NULL; - PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum); - - if(type == PINSEL_PIN_TYPE_UNKNOWN) - return PINSEL_RET_INVALID_PIN; - if((type != PINSEL_PIN_TYPE_D ) && - (type != PINSEL_PIN_TYPE_A ) && - (type != PINSEL_PIN_TYPE_W )) - return PINSEL_RET_NOT_SUPPORT; - - pPIN = PIN_GetPointer(portnum, pinnum); - if(NewState == DISABLE) - { - *(uint32_t *)pPIN &= ~IOCON_OPENDRAIN_MODE;//Clear hys bits - } - else - { - *(uint32_t *)pPIN |= IOCON_OPENDRAIN_MODE; - } - return PINSEL_RET_OK; -} - -/*********************************************************************//** - * @brief Enable the Analog mode for each pin of Type A(default is as Digital pins) - * @param[in] portnum PORT number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @param[in] enable: the state of the pin that is expected to run - - ENABLE: Enable the DAC mode of the pin - - DISABLE: Disable the DAC mode - * @return PINSEL Return Code - * - PINSEL_RET_INVALID_PIN - * - PINSEL_RET_NOT_SUPPORT - * - PINSEL_RET_OK - **********************************************************************/ -PINSEL_RET_CODE PINSEL_SetAnalogPinMode (uint8_t portnum, uint8_t pinnum, uint8_t enable) -{ - uint32_t *pPIN = NULL; - PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum); - - if(type == PINSEL_PIN_TYPE_UNKNOWN) - return PINSEL_RET_INVALID_PIN; - if(type != PINSEL_PIN_TYPE_A ) - return PINSEL_RET_NOT_SUPPORT; - - pPIN = PIN_GetPointer(portnum, pinnum); - - if(enable) - { - *(uint32_t *)pPIN &= ~(IOCON_DIGITIAL_MODE); - } - else - { - *(uint32_t *)pPIN |= IOCON_DIGITIAL_MODE;//Set 7th bit to one - } - - return PINSEL_RET_OK; -} - - - -/*********************************************************************//** - * @brief Choose the DAC mode for pin P0.26 - * @param[in] portnum PORT number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @param[in] enable: the state of the pin that is expected to run - - ENABLE: Enable the DAC mode of the pin - - DISABLE: Disable the DAC mode - * @return PINSEL Return Code - * - PINSEL_RET_INVALID_PIN - * - PINSEL_RET_NOT_SUPPORT - * - PINSEL_RET_OK - **********************************************************************/ -PINSEL_RET_CODE PINSEL_DacEnable (uint8_t portnum, uint8_t pinnum, uint8_t enable) -{ - uint32_t *pPIN = NULL; - - PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum); - - if(type == PINSEL_PIN_TYPE_UNKNOWN) - return PINSEL_RET_INVALID_PIN; - - // This setting is only for DAC pin (output pin) - if(!((portnum == 0) && (pinnum == 26))) - { - return PINSEL_RET_NOT_SUPPORT; - } - - pPIN = PIN_GetPointer(portnum, pinnum); - - if(enable) - { - *(uint32_t *)pPIN |= IOCON_DAC_ENABLE;//Set 16th bit to one - } - else - { - *(uint32_t *)pPIN &= ~IOCON_DAC_ENABLE;//Set 16th bit to one - - } - - return PINSEL_RET_OK; -} - -/*********************************************************************//** - * @brief Control the 10ns glitch filter for pin of type A,W - * @param[in] portnum PORT number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @param[in] enable: the state of the pin that is expected to run - - ENABLE: The noise pulses below approximately 10ns are filtered out - - DISABLE: No input filtering is done. - * @return PINSEL Return Code - * - PINSEL_RET_INVALID_PIN - * - PINSEL_RET_NOT_SUPPORT - * - PINSEL_RET_OK - **********************************************************************/ -PINSEL_RET_CODE PINSEL_SetFilter (uint8_t portnum, uint8_t pinnum, uint8_t enable) -{ - uint32_t *pPIN = NULL; - PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum); - - if(type == PINSEL_PIN_TYPE_UNKNOWN) - return PINSEL_RET_INVALID_PIN; - if((type != PINSEL_PIN_TYPE_A ) && - (type != PINSEL_PIN_TYPE_W )) - return PINSEL_RET_NOT_SUPPORT; - - pPIN = PIN_GetPointer(portnum, pinnum); - - - if(enable) - { - *(uint32_t *)pPIN &= ~(IOCON_10ns_FILTER_DISABLE);//Clear 8th bit to 0 - } - else - { - *(uint32_t *)pPIN |= (IOCON_10ns_FILTER_DISABLE);//Set 8th bit to one - } - - - return PINSEL_RET_OK; -} -/*********************************************************************//** - * @brief Control the 50ns glitch filter for I2C pins (type I) - * @param[in] portnum PORT number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @param[in] enable: the state of the pin that is expected to run - - ENABLE: The noise pulses below approximately 10ns are filtered out - - DISABLE: No input filtering is done. - * @return PINSEL Return Code - * - PINSEL_RET_INVALID_PIN - * - PINSEL_RET_NOT_SUPPORT - * - PINSEL_RET_OK - **********************************************************************/ -PINSEL_RET_CODE PINSEL_SetI2CFilter (uint8_t portnum, uint8_t pinnum, uint8_t enable) -{ - uint32_t *pPIN = NULL; - PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum); - - if(type == PINSEL_PIN_TYPE_UNKNOWN) - return PINSEL_RET_INVALID_PIN; - if(type != PINSEL_PIN_TYPE_I) - return PINSEL_RET_NOT_SUPPORT; - - pPIN = PIN_GetPointer(portnum, pinnum); - - - if(enable) - { - *(uint32_t *)pPIN &= ~(IOCON_HS_MASK);//Clear 8th bit to 0 - } - else - { - *(uint32_t *)pPIN |= (IOCON_I2C_FILTER_DISABLE);//Set 8th bit to one - } - - - return PINSEL_RET_OK; -} - - -/** - * @} - */ -#endif /*_PINSEL*/ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_pwm.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_pwm.c deleted file mode 100644 index a9c79c25c4d..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_pwm.c +++ /dev/null @@ -1,579 +0,0 @@ -/********************************************************************** -* $Id$ lpc_pwm.c 2011-06-02 -*//** -* @file lpc_pwm.c -* @brief Contains all functions support for PWM firmware library -* on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup PWM - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _PWM - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_pwm.h" -#include "lpc_clkpwr.h" - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup PWM_Public_Functions - * @{ - */ - -static LPC_PWM_TypeDef* PWM_GetPointer (uint8_t pwmId); - -/*********************************************************************//** - * @brief Setting CAN baud rate (bps) - * @param[in] canId point to LPC_CAN_TypeDef object, should be: - * - LPC_CAN1: CAN1 peripheral - * - LPC_CAN2: CAN2 peripheral - * @return The pointer to CAN peripheral that's expected to use - ***********************************************************************/ -static LPC_PWM_TypeDef* PWM_GetPointer (uint8_t pwmId) -{ - LPC_PWM_TypeDef* pPwm; - - switch (pwmId) - { - case PWM_0: - pPwm = LPC_PWM0; - break; - - case PWM_1: - pPwm = LPC_PWM1; - break; - - default: - pPwm = NULL; - break; - } - - return pPwm; -} - - -/*********************************************************************//** - * @brief Check whether specified interrupt flag in PWM is set or not - * @param[in] pwmId The Id of the expected PWM component - * - * @param[in] IntFlag: PWM interrupt flag, should be: - * - PWM_INTSTAT_MR0: Interrupt flag for PWM match channel 0 - * - PWM_INTSTAT_MR1: Interrupt flag for PWM match channel 1 - * - PWM_INTSTAT_MR2: Interrupt flag for PWM match channel 2 - * - PWM_INTSTAT_MR3: Interrupt flag for PWM match channel 3 - * - PWM_INTSTAT_MR4: Interrupt flag for PWM match channel 4 - * - PWM_INTSTAT_MR5: Interrupt flag for PWM match channel 5 - * - PWM_INTSTAT_MR6: Interrupt flag for PWM match channel 6 - * - PWM_INTSTAT_CAP0: Interrupt flag for capture input 0 - * - PWM_INTSTAT_CAP1: Interrupt flag for capture input 1 - * @return New State of PWM interrupt flag (SET or RESET) - **********************************************************************/ -IntStatus PWM_GetIntStatus(uint8_t pwmId, uint32_t IntFlag) -{ - LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId); - - return ((pPwm->IR & IntFlag) ? SET : RESET); -} - - - -/*********************************************************************//** - * @brief Clear specified PWM Interrupt pending - * @param[in] pwmId The Id of the expected PWM component - * - * @param[in] IntFlag: PWM interrupt flag, should be: - * - PWM_INTSTAT_MR0: Interrupt flag for PWM match channel 0 - * - PWM_INTSTAT_MR1: Interrupt flag for PWM match channel 1 - * - PWM_INTSTAT_MR2: Interrupt flag for PWM match channel 2 - * - PWM_INTSTAT_MR3: Interrupt flag for PWM match channel 3 - * - PWM_INTSTAT_MR4: Interrupt flag for PWM match channel 4 - * - PWM_INTSTAT_MR5: Interrupt flag for PWM match channel 5 - * - PWM_INTSTAT_MR6: Interrupt flag for PWM match channel 6 - * - PWM_INTSTAT_CAP0: Interrupt flag for capture input 0 - * - PWM_INTSTAT_CAP1: Interrupt flag for capture input 1 - * @return None - **********************************************************************/ -void PWM_ClearIntPending(uint8_t pwmId, uint32_t IntFlag) -{ - LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId); - - pPwm->IR = IntFlag; -} - - - -/*****************************************************************************//** -* @brief Fills each PWM_InitStruct member with its default value: -* - If PWMCounterMode = PWM_MODE_TIMER: -* + PrescaleOption = PWM_TIMER_PRESCALE_USVAL -* + PrescaleValue = 1 -* - If PWMCounterMode = PWM_MODE_COUNTER: -* + CountInputSelect = PWM_COUNTER_PCAP1_0 -* + CounterOption = PWM_COUNTER_RISING -* @param[in] PWMTimerCounterMode Timer or Counter mode, should be: -* - PWM_MODE_TIMER: Counter of PWM peripheral is in Timer mode -* - PWM_MODE_COUNTER: Counter of PWM peripheral is in Counter mode -* @param[in] PWM_InitStruct Pointer to structure (PWM_TIMERCFG_Type or -* PWM_COUNTERCFG_Type) which will be initialized. -* @return None -* Note: PWM_InitStruct pointer will be assigned to corresponding structure -* (PWM_TIMERCFG_Type or PWM_COUNTERCFG_Type) due to PWMTimerCounterMode. -*******************************************************************************/ -void PWM_ConfigStructInit(uint8_t PWMTimerCounterMode, void *PWM_InitStruct) -{ - PWM_TIMERCFG_Type *pTimeCfg; - PWM_COUNTERCFG_Type *pCounterCfg; - - pTimeCfg = (PWM_TIMERCFG_Type *) PWM_InitStruct; - pCounterCfg = (PWM_COUNTERCFG_Type *) PWM_InitStruct; - - if (PWMTimerCounterMode == PWM_MODE_TIMER ) - { - pTimeCfg->PrescaleOption = PWM_TIMER_PRESCALE_USVAL; - pTimeCfg->PrescaleValue = 1; - } - else if (PWMTimerCounterMode == PWM_MODE_COUNTER) - { - pCounterCfg->CountInputSelect = PWM_COUNTER_PCAP1_0; - pCounterCfg->CounterOption = PWM_COUNTER_RISING; - } -} - - -/*********************************************************************//** - * @brief Initializes the pPwm peripheral corresponding to the specified - * parameters in the PWM_ConfigStruct. - * @param[in] pwmId The Id of the expected PWM component - * - * - * @param[in] PWMTimerCounterMode Timer or Counter mode, should be: - * - PWM_MODE_TIMER: Counter of PWM peripheral is in Timer mode - * - PWM_MODE_COUNTER: Counter of PWM peripheral is in Counter mode - * @param[in] PWM_ConfigStruct Pointer to structure (PWM_TIMERCFG_Type or - * PWM_COUNTERCFG_Type) which will be initialized. - * @return None - * Note: PWM_ConfigStruct pointer will be assigned to corresponding structure - * (PWM_TIMERCFG_Type or PWM_COUNTERCFG_Type) due to PWMTimerCounterMode. - **********************************************************************/ -void PWM_Init(uint8_t pwmId, uint32_t PWMTimerCounterMode, void *PWM_ConfigStruct) -{ - LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId); - - PWM_TIMERCFG_Type *pTimeCfg; - PWM_COUNTERCFG_Type *pCounterCfg; - uint64_t clkdlycnt; - - pTimeCfg = (PWM_TIMERCFG_Type *)PWM_ConfigStruct; - pCounterCfg = (PWM_COUNTERCFG_Type *)PWM_ConfigStruct; - - if(pwmId == PWM_0) - { - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCPWM0, ENABLE); - } - else if(pwmId == PWM_1) - { - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCPWM1, ENABLE); - } - else - { - //Trap the error - while(1); - } - - // Get peripheral clock of PWM1 - clkdlycnt = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER); - - // Clear all interrupts pending - pPwm->IR = 0xFF & PWM_IR_BITMASK; - pPwm->TCR = 0x00; - pPwm->CTCR = 0x00; - pPwm->MCR = 0x00; - pPwm->CCR = 0x00; - pPwm->PCR = 0x00; - pPwm->LER = 0x00; - - if (PWMTimerCounterMode == PWM_MODE_TIMER) - { - /* Absolute prescale value */ - if (pTimeCfg->PrescaleOption == PWM_TIMER_PRESCALE_TICKVAL) - { - pPwm->PR = pTimeCfg->PrescaleValue - 1; - } - /* uSecond prescale value */ - else - { - clkdlycnt = (clkdlycnt * pTimeCfg->PrescaleValue) / 1000000; - pPwm->PR = ((uint32_t) clkdlycnt) - 1; - } - - } - else if (PWMTimerCounterMode == PWM_MODE_COUNTER) - { - - pPwm->CTCR |= (PWM_CTCR_MODE((uint32_t)pCounterCfg->CounterOption)) \ - | (PWM_CTCR_SELECT_INPUT((uint32_t)pCounterCfg->CountInputSelect)); - } -} - -/*********************************************************************//** - * @brief De-initializes the PWM peripheral registers to their -* default reset values. - * @param[in] pwmId The Id of the expected PWM component - * - * @return None - **********************************************************************/ -void PWM_DeInit (uint8_t pwmId) -{ - LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId); - - // Disable PWM control (timer, counter and PWM) - pPwm->TCR = 0x00; - - if(pwmId == PWM_0) - { - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCPWM0, DISABLE); - } - else if(pwmId == PWM_1) - { - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCPWM1, DISABLE); - } -} - - -/*********************************************************************//** - * @brief Enable/Disable PWM peripheral - * @param[in] pwmId The Id of the expected PWM component - * - * @param[in] NewState New State of this function, should be: - * - ENABLE: Enable PWM peripheral - * - DISABLE: Disable PWM peripheral - * @return None - **********************************************************************/ -void PWM_Cmd(uint8_t pwmId, FunctionalState NewState) -{ - LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId); - - if (NewState == ENABLE) - { - pPwm->TCR |= PWM_TCR_PWM_ENABLE; - } - else - { - pPwm->TCR &= (~PWM_TCR_PWM_ENABLE) & PWM_TCR_BITMASK; - } -} - - -/*********************************************************************//** - * @brief Enable/Disable Counter in PWM peripheral - * @param[in] pwmId The Id of the expected PWM component - * - * @param[in] NewState New State of this function, should be: - * - ENABLE: Enable Counter in PWM peripheral - * - DISABLE: Disable Counter in PWM peripheral - * @return None - **********************************************************************/ -void PWM_CounterCmd(uint8_t pwmId, FunctionalState NewState) -{ - LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId); - - if (NewState == ENABLE) - { - pPwm->TCR |= PWM_TCR_COUNTER_ENABLE; - } - else - { - pPwm->TCR &= (~PWM_TCR_COUNTER_ENABLE) & PWM_TCR_BITMASK; - } -} - - -/*********************************************************************//** - * @brief Reset Counter in PWM peripheral - * @param[in] pwmId The Id of the expected PWM component - * - * @return None - **********************************************************************/ -void PWM_ResetCounter(uint8_t pwmId) -{ - LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId); - - pPwm->TCR |= PWM_TCR_COUNTER_RESET; - - pPwm->TCR &= (~PWM_TCR_COUNTER_RESET) & PWM_TCR_BITMASK; -} - - -/*********************************************************************//** - * @brief Configures match for PWM peripheral - * @param[in] pwmId The Id of the expected PWM component - * - * @param[in] PWM_MatchConfigStruct Pointer to a PWM_MATCHCFG_Type structure -* that contains the configuration information for the -* specified PWM match function. - * @return None - **********************************************************************/ -void PWM_ConfigMatch(uint8_t pwmId, PWM_MATCHCFG_Type *PWM_MatchConfigStruct) -{ - LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId); - - //interrupt on MRn - if (PWM_MatchConfigStruct->IntOnMatch == ENABLE) - { - pPwm->MCR |= PWM_MCR_INT_ON_MATCH(PWM_MatchConfigStruct->MatchChannel); - } - else - { - pPwm->MCR &= (~ PWM_MCR_INT_ON_MATCH(PWM_MatchConfigStruct->MatchChannel)) \ - & PWM_MCR_BITMASK; - } - - //reset on MRn - if (PWM_MatchConfigStruct->ResetOnMatch == ENABLE) - { - pPwm->MCR |= PWM_MCR_RESET_ON_MATCH(PWM_MatchConfigStruct->MatchChannel); - } - else - { - pPwm->MCR &= (~ PWM_MCR_RESET_ON_MATCH(PWM_MatchConfigStruct->MatchChannel)) \ - & PWM_MCR_BITMASK; - } - - //stop on MRn - if (PWM_MatchConfigStruct->StopOnMatch == ENABLE) - { - pPwm->MCR |= PWM_MCR_STOP_ON_MATCH(PWM_MatchConfigStruct->MatchChannel); - } - else - { - pPwm->MCR &= (~ PWM_MCR_STOP_ON_MATCH(PWM_MatchConfigStruct->MatchChannel)) \ - & PWM_MCR_BITMASK; - } -} - - -/*********************************************************************//** - * @brief Configures capture input for PWM peripheral - * @param[in] pwmId The Id of the expected PWM component - * - * @param[in] PWM_CaptureConfigStruct Pointer to a PWM_CAPTURECFG_Type structure - * that contains the configuration information for the - * specified PWM capture input function. - * @return None - **********************************************************************/ -void PWM_ConfigCapture(uint8_t pwmId, PWM_CAPTURECFG_Type *PWM_CaptureConfigStruct) -{ - LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId); - - if (PWM_CaptureConfigStruct->RisingEdge == ENABLE) - { - pPwm->CCR |= PWM_CCR_CAP_RISING(PWM_CaptureConfigStruct->CaptureChannel); - } - else - { - pPwm->CCR &= (~ PWM_CCR_CAP_RISING(PWM_CaptureConfigStruct->CaptureChannel)) \ - & PWM_CCR_BITMASK; - } - - if (PWM_CaptureConfigStruct->FallingEdge == ENABLE) - { - pPwm->CCR |= PWM_CCR_CAP_FALLING(PWM_CaptureConfigStruct->CaptureChannel); - } - else - { - pPwm->CCR &= (~ PWM_CCR_CAP_FALLING(PWM_CaptureConfigStruct->CaptureChannel)) \ - & PWM_CCR_BITMASK; - } - - if (PWM_CaptureConfigStruct->IntOnCaption == ENABLE) - { - pPwm->CCR |= PWM_CCR_INT_ON_CAP(PWM_CaptureConfigStruct->CaptureChannel); - } - else - { - pPwm->CCR &= (~ PWM_CCR_INT_ON_CAP(PWM_CaptureConfigStruct->CaptureChannel)) \ - & PWM_CCR_BITMASK; - } -} - - -/*********************************************************************//** - * @brief Read value of capture register PWM peripheral - * @param[in] pwmId The Id of the expected PWM component - * - * @param[in] CaptureChannel: capture channel number, should be in - * range 0 to 1 - * @return Value of capture register - **********************************************************************/ -uint32_t PWM_GetCaptureValue(uint8_t pwmId, uint8_t CaptureChannel) -{ - LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId); - - switch (CaptureChannel) - { - case 0: - return pPwm->CR0; - - case 1: - return pPwm->CR1; - - default: - return (0); - } -} - - -/********************************************************************//** - * @brief Update value for each PWM channel with update type option - * @param[in] pwmId The Id of the expected PWM component - * - * @param[in] MatchChannel Match channel - * @param[in] MatchValue Match value - * @param[in] UpdateType Type of Update, should be: - * - PWM_MATCH_UPDATE_NOW: The update value will be updated for - * this channel immediately - * - PWM_MATCH_UPDATE_NEXT_RST: The update value will be updated for - * this channel on next reset by a PWM Match event. - * @return None - *********************************************************************/ -void PWM_MatchUpdate(uint8_t pwmId, uint8_t MatchChannel, - uint32_t MatchValue, uint8_t UpdateType) -{ - LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId); - - switch (MatchChannel) - { - case 0: - pPwm->MR0 = MatchValue; - break; - - case 1: - pPwm->MR1 = MatchValue; - break; - - case 2: - pPwm->MR2 = MatchValue; - break; - - case 3: - pPwm->MR3 = MatchValue; - break; - - case 4: - pPwm->MR4 = MatchValue; - break; - - case 5: - pPwm->MR5 = MatchValue; - break; - - case 6: - pPwm->MR6 = MatchValue; - break; - } - - // Write Latch register - pPwm->LER |= PWM_LER_EN_MATCHn_LATCH(MatchChannel); - - // In case of update now - if (UpdateType == PWM_MATCH_UPDATE_NOW) - { - pPwm->TCR |= PWM_TCR_COUNTER_RESET; - pPwm->TCR &= (~PWM_TCR_COUNTER_RESET) & PWM_TCR_BITMASK; - } -} - - -/********************************************************************//** - * @brief Configure Edge mode for each PWM channel - * @param[in] pwmId The Id of the expected PWM component - * - * @param[in] PWMChannel PWM channel, should be in range from 2 to 6 - * @param[in] ModeOption PWM mode option, should be: - * - PWM_CHANNEL_SINGLE_EDGE: Single Edge mode - * - PWM_CHANNEL_DUAL_EDGE: Dual Edge mode - * @return None - * Note: PWM Channel 1 can not be selected for mode option - *********************************************************************/ -void PWM_ChannelConfig(uint8_t pwmId, uint8_t PWMChannel, uint8_t ModeOption) -{ - LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId); - - // Single edge mode - if (ModeOption == PWM_CHANNEL_SINGLE_EDGE) - { - pPwm->PCR &= (~ PWM_PCR_PWMSELn(PWMChannel)) & PWM_PCR_BITMASK; - } - // Double edge mode - else if (PWM_CHANNEL_DUAL_EDGE) - { - pPwm->PCR |= PWM_PCR_PWMSELn(PWMChannel); - } -} - - - -/********************************************************************//** - * @brief Enable/Disable PWM channel output - * @param[in] pwmId The Id of the expected PWM component - * - * @param[in] PWMChannel PWM channel, should be in range from 1 to 6 - * @param[in] NewState New State of this function, should be: - * - ENABLE: Enable this PWM channel output - * - DISABLE: Disable this PWM channel output - * @return None - *********************************************************************/ -void PWM_ChannelCmd(uint8_t pwmId, uint8_t PWMChannel, FunctionalState NewState) -{ - LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId); - - if (NewState == ENABLE) - { - pPwm->PCR |= PWM_PCR_PWMENAn(PWMChannel); - } - else - { - pPwm->PCR &= (~ PWM_PCR_PWMENAn(PWMChannel)) & PWM_PCR_BITMASK; - } -} - -/** - * @} - */ - -#endif /*_PWM*/ -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_qei.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_qei.c deleted file mode 100644 index 8c098a7b693..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_qei.c +++ /dev/null @@ -1,599 +0,0 @@ -/********************************************************************** -* $Id$ lpc_qei.c 2011-06-02 -*//** -* @file lpc_qei.c -* @brief Contains all functions support for QEI firmware library -* on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup QEI - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _QEI - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_qei.h" -#include "lpc_clkpwr.h" - -/* Private Types -------------------------------------------------------------- */ -/** @defgroup QEI_Private_Types QEI Private Types - * @{ - */ - -/** - * @brief QEI configuration union type definition - */ -typedef union { - QEI_CFG_Type bmQEIConfig; - uint32_t ulQEIConfig; -} QEI_CFGOPT_Type; - -/** - * @} - */ - -LPC_QEI_TypeDef* QEI_GetPointer(uint8_t qeiId); - - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup QEI_Public_Functions - * @{ - */ - -/*********************************************************************//** - * @brief Get the point to typedef of QEI component - * @param[in] qeiId The Id of the expected QEI component - * It should be 0 (zero) always with LPC - * @return None - **********************************************************************/ -LPC_QEI_TypeDef* QEI_GetPointer(uint8_t qeiId) -{ - LPC_QEI_TypeDef* pQei = NULL; - - if(qeiId == 0) - { - pQei = LPC_QEI; - } - - return pQei; -} - - -/*********************************************************************//** - * @brief Resets value for each type of QEI value, such as velocity, - * counter, position, etc.. - * @param[in] qeiId The Id of the expected QEI component - * It should be 0 (zero) always with LPC - * - * @param[in] ulResetType QEI Reset Type, should be one of the following: - * - QEI_RESET_POS: Reset Position Counter - * - QEI_RESET_POSOnIDX: Reset Position Counter on Index signal - * - QEI_RESET_VEL: Reset Velocity - * - QEI_RESET_IDX: Reset Index Counter - * @return None - **********************************************************************/ -void QEI_Reset(uint8_t qeiId, uint32_t ulResetType) -{ - LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId); - - pQei->CON = ulResetType; -} - -/*********************************************************************//** - * @brief Initializes the QEI peripheral according to the specified -* parameters in the QEI_ConfigStruct. -* @param[in] qeiId The Id of the expected QEI component -* It should be 0 (zero) always with LPC -* -* @param[in] QEI_ConfigStruct Pointer to a QEI_CFG_Type structure -* that contains the configuration information for the -* specified QEI peripheral - * @return None - **********************************************************************/ -void QEI_Init(uint8_t qeiId, QEI_CFG_Type *QEI_ConfigStruct) -{ - LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId); - - /* Set up clock and power for QEI module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCQEI, ENABLE); - - // Reset all remaining value in QEI peripheral - - pQei->MAXPOS = 0x00; - pQei->CMPOS0 = 0x00; - pQei->CMPOS1 = 0x00; - pQei->CMPOS2 = 0x00; - pQei->INXCMP0 = 0x00; - pQei->VELCOMP = 0x00; - - pQei->LOAD = 0x00; - pQei->CON = QEI_CON_RESP | QEI_CON_RESV | QEI_CON_RESI; - - pQei->FILTERPHA = 0x00; - pQei->FILTERPHB = 0x00; - pQei->FILTERINX = 0x00; - - // Disable all Interrupt - pQei->IEC = QEI_IECLR_BITMASK; - - // Clear all Interrupt pending - pQei->CLR = QEI_INTCLR_BITMASK; - - // Set QEI configuration value corresponding to its setting up value - pQei->CONF = ((QEI_CFGOPT_Type *)QEI_ConfigStruct)->ulQEIConfig; -} - - -/*********************************************************************//** - * @brief De-initializes the QEI peripheral registers to their - * default reset values. - * @param[in] qeiId The Id of the expected QEI component - * It should be 0 (zero) always with LPC - * - * @return None - **********************************************************************/ -void QEI_DeInit(uint8_t qeiId) -{ - /* Turn off clock and power for QEI module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCQEI, DISABLE); -} - - -/*****************************************************************************//** -* @brief Fills each QIE_InitStruct member with its default value: -* - DirectionInvert = QEI_DIRINV_NONE -* - SignalMode = QEI_SIGNALMODE_QUAD -* - CaptureMode = QEI_CAPMODE_4X -* - InvertIndex = QEI_INVINX_NONE -* @param[in] QIE_InitStruct Pointer to a QEI_CFG_Type structure -* which will be initialized. -* @return None -*******************************************************************************/ -void QEI_GetCfgDefault(QEI_CFG_Type *QIE_InitStruct) -{ - QIE_InitStruct->CaptureMode = QEI_CAPMODE_4X; - QIE_InitStruct->DirectionInvert = QEI_DIRINV_NONE; - QIE_InitStruct->InvertIndex = QEI_INVINX_NONE; - QIE_InitStruct->SignalMode = QEI_SIGNALMODE_QUAD; -} - - -/*********************************************************************//** - * @brief Check whether if specified flag status is set or not - * @param[in] qeiId The Id of the expected QEI component - * It should be 0 (zero) always with LPC - * - * @param[in] ulFlagType Status Flag Type, should be one of the following: - * - QEI_STATUS_DIR: Direction Status - * @return New Status of this status flag (SET or RESET) - **********************************************************************/ -FlagStatus QEI_GetStatus(uint8_t qeiId, uint32_t ulFlagType) -{ - LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId); - - return ((pQei->STAT & ulFlagType) ? SET : RESET); -} - -/*********************************************************************//** - * @brief Get current position value in QEI peripheral - * @param[in] qeiId The Id of the expected QEI component - * It should be 0 (zero) always with LPC - * - * @return Current position value of QEI peripheral - **********************************************************************/ -uint32_t QEI_GetPosition(uint8_t qeiId) -{ - LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId); - - return (pQei->POS); -} - -/*********************************************************************//** - * @brief Set max position value for QEI peripheral - * @param[in] qeiId The Id of the expected QEI component - * It should be 0 (zero) always with LPC - * - * @param[in] ulMaxPos Max position value to set - * @return None - **********************************************************************/ -void QEI_SetMaxPosition(uint8_t qeiId, uint32_t ulMaxPos) -{ - LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId); - - pQei->MAXPOS = ulMaxPos; -} - -/*********************************************************************//** - * @brief Set position compare value for QEI peripheral - * @param[in] qeiId The Id of the expected QEI component - * It should be 0 (zero) always with LPC - * - * @param[in] bPosCompCh Compare Position channel, should be: - * - QEI_COMPPOS_CH_0: QEI compare position channel 0 - * - QEI_COMPPOS_CH_1: QEI compare position channel 1 - * - QEI_COMPPOS_CH_2: QEI compare position channel 2 - * @param[in] ulPosComp Compare Position value to set - * @return None - **********************************************************************/ -void QEI_SetPositionComp(uint8_t qeiId, uint8_t bPosCompCh, uint32_t ulPosComp) -{ - LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId); - uint32_t *tmp; - - tmp = (uint32_t *) (&(pQei->CMPOS0) + bPosCompCh * 4); - *tmp = ulPosComp; -} - -/*********************************************************************//** - * @brief Get current index counter of QEI peripheral - * @param[in] qeiId The Id of the expected QEI component - * It should be 0 (zero) always with LPC - * - * @return Current value of QEI index counter - **********************************************************************/ -uint32_t QEI_GetIndex(uint8_t qeiId) -{ - LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId); - - return (pQei->INXCNT); -} - -/*********************************************************************//** - * @brief Set value for index compare in QEI peripheral - * @param[in] qeiId The Id of the expected QEI component - * It should be 0 (zero) always with LPC - * - * @param[in] ulIndexComp Compare Index Value to set - * @return None - **********************************************************************/ -void QEI_SetIndexComp(uint8_t qeiId, uint32_t ulIndexComp) -{ - LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId); - - pQei->INXCMP0 = ulIndexComp; -} - -/*********************************************************************//** - * @brief Set timer reload value for QEI peripheral. When the velocity timer is - * over-flow, the value that set for Timer Reload register will be loaded - * into the velocity timer for next period. The calculated velocity in RPM - * therefore will be affect by this value. - * @param[in] qeiId The Id of the expected QEI component - * It should be 0 (zero) always with LPC - * - * @param[in] QEIReloadStruct QEI reload structure - * @return None - **********************************************************************/ -void QEI_SetTimerReload(uint8_t qeiId, QEI_RELOADCFG_Type *QEIReloadStruct) -{ - LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId); - uint64_t pclk; - - - if (QEIReloadStruct->ReloadOption == QEI_TIMERRELOAD_TICKVAL) - { - pQei->LOAD = QEIReloadStruct->ReloadValue - 1; - } - else - { -#if 1 - pclk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER); - - pclk = (pclk /(1000000/QEIReloadStruct->ReloadValue)) - 1; - - pQei->LOAD = (uint32_t)pclk; -#else - ld = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER); - - if (ld/1000000 > 0) - { - ld /= 1000000; - ld *= QEIReloadStruct->ReloadValue; - ld -= 1; - } - else - { - ld *= QEIReloadStruct->ReloadValue; - ld /= 1000000; - ld -= 1; - } - - pQei->LOAD = ld; -#endif - } -} - -/*********************************************************************//** - * @brief Get current timer counter in QEI peripheral - * @param[in] qeiId The Id of the expected QEI component - * It should be 0 (zero) always with LPC - * - * @return Current timer counter in QEI peripheral - **********************************************************************/ -uint32_t QEI_GetTimer(uint8_t qeiId) -{ - LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId); - - return (pQei->TIME); -} - -/*********************************************************************//** - * @brief Get current velocity pulse counter in current time period - * @param[in] qeiId The Id of the expected QEI component - * It should be 0 (zero) always with LPC - * - * @return Current velocity pulse counter value - **********************************************************************/ -uint32_t QEI_GetVelocity(uint8_t qeiId) -{ - LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId); - - return (pQei->VEL); -} - -/*********************************************************************//** - * @brief Get the most recently measured velocity of the QEI. When - * the Velocity timer in QEI is over-flow, the current velocity - * value will be loaded into Velocity Capture register. - * @param[in] qeiId The Id of the expected QEI component - * It should be 0 (zero) always with LPC - * - * @return The most recently measured velocity value - **********************************************************************/ -uint32_t QEI_GetVelocityCap(uint8_t qeiId) -{ - LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId); - - return (pQei->CAP); -} - -/*********************************************************************//** - * @brief Set Velocity Compare value for QEI peripheral - * @param[in] qeiId The Id of the expected QEI component - * It should be 0 (zero) always with LPC - * - * @param[in] ulVelComp Compare Velocity value to set - * @return None - **********************************************************************/ -void QEI_SetVelocityComp(uint8_t qeiId, uint32_t ulVelComp) -{ - LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId); - - pQei->VELCOMP = ulVelComp; -} - -/*********************************************************************//** - * @brief Set value of sampling count for the digital filter in - * QEI peripheral - * @param[in] qeiId The Id of the expected QEI component - * It should be 0 (zero) always with LPC - * - * @param[in] ulSamplingPulse Value of sampling count to set - * @return None - **********************************************************************/ -void QEI_SetDigiFilter(uint8_t qeiId, st_Qei_FilterCfg FilterVal) -{ - LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId); - - pQei->FILTERPHA = FilterVal.PHA_FilterVal; - pQei->FILTERPHB = FilterVal.PHB_FilterVal; - pQei->FILTERINX = FilterVal.INX_FilterVal; -} - -/*********************************************************************//** - * @brief Check whether if specified interrupt flag status in QEI - * peripheral is set or not - * @param[in] qeiId The Id of the expected QEI component - * It should be 0 (zero) always with LPC - * - * @param[in] ulIntType Interrupt Flag Status type, should be: - - QEI_INTFLAG_INX_Int: index pulse was detected interrupt - - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt - - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt - - QEI_INTFLAG_DIR_Int: Change of direction interrupt - - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt - - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt - - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the - current position interrupt - - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the - current position interrupt - - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the - current position interrupt - - QEI_INTFLAG_REV_Int: Index compare value is equal to the current - index count interrupt - - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt - - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt - - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt - * @return New State of specified interrupt flag status (SET or RESET) - **********************************************************************/ -FlagStatus QEI_GetIntStatus(uint8_t qeiId, uint32_t ulIntType) -{ - LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId); - - return((pQei->INTSTAT & ulIntType) ? SET : RESET); -} - -/*********************************************************************//** - * @brief Enable/Disable specified interrupt in QEI peripheral - * @param[in] qeiId The Id of the expected QEI component - * It should be 0 (zero) always with LPC - * - * @param[in] ulIntType Interrupt Flag Status type, should be: - - QEI_INTFLAG_INX_Int: index pulse was detected interrupt - - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt - - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt - - QEI_INTFLAG_DIR_Int: Change of direction interrupt - - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt - - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt - - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the - current position interrupt - - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the - current position interrupt - - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the - current position interrupt - - QEI_INTFLAG_REV_Int: Index compare value is equal to the current - index count interrupt - - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt - - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt - - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt - * @param[in] NewState New function state, should be: - * - DISABLE - * - ENABLE - * @return None - **********************************************************************/ -void QEI_IntCmd(uint8_t qeiId, uint32_t ulIntType, FunctionalState NewState) -{ - LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId); - - if (NewState == ENABLE) - { - pQei->IES = ulIntType; - } - else - { - pQei->IEC = ulIntType; - } -} - - -/*********************************************************************//** - * @brief Sets (forces) specified interrupt in QEI peripheral - * @param[in] qeiId The Id of the expected QEI component - * It should be 0 (zero) always with LPC - * - * @param[in] ulIntType Interrupt Flag Status type, should be: - - QEI_INTFLAG_INX_Int: index pulse was detected interrupt - - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt - - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt - - QEI_INTFLAG_DIR_Int: Change of direction interrupt - - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt - - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt - - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the - current position interrupt - - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the - current position interrupt - - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the - current position interrupt - - QEI_INTFLAG_REV_Int: Index compare value is equal to the current - index count interrupt - - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt - - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt - - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt - * @return None - **********************************************************************/ -void QEI_IntSet(uint8_t qeiId, uint32_t ulIntType) -{ - LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId); - - pQei->SET = ulIntType; -} - -/*********************************************************************//** - * @brief Clear (force) specified interrupt (pending) in QEI peripheral - * @param[in] qeiId The Id of the expected QEI component - * It should be 0 (zero) always with LPC - * - * @param[in] ulIntType Interrupt Flag Status type, should be: - - QEI_INTFLAG_INX_Int: index pulse was detected interrupt - - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt - - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt - - QEI_INTFLAG_DIR_Int: Change of direction interrupt - - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt - - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt - - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the - current position interrupt - - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the - current position interrupt - - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the - current position interrupt - - QEI_INTFLAG_REV_Int: Index compare value is equal to the current - index count interrupt - - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt - - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt - - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt - * @return None - **********************************************************************/ -void QEI_IntClear(uint8_t qeiId, uint32_t ulIntType) -{ - LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId); - - pQei->CLR = ulIntType; -} - - -/*********************************************************************//** - * @brief Calculates the actual velocity in RPM passed via velocity - * capture value and Pulse Per Round (of the encoder) value - * parameter input. - * @param[in] qeiId The Id of the expected QEI component - * It should be 0 (zero) always with LPC - * - * @param[in] ulVelCapValue Velocity capture input value that can - * be got from QEI_GetVelocityCap() function - * @param[in] ulPPR Pulse per round of encoder - * @return The actual value of velocity in RPM (Round per minute) - **********************************************************************/ -uint32_t QEI_CalculateRPM(uint8_t qeiId, uint32_t ulVelCapValue, uint32_t ulPPR) -{ - LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId); - - uint64_t rpm, clock, Load, edges; - - // Get current Clock rate for timer input - clock = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER); - - // Get Timer load value (velocity capture period) - Load = (uint64_t)(pQei->LOAD + 1); - - // Get Edge - edges = (uint64_t)((pQei->CONF & QEI_CONF_CAPMODE) ? 4 : 2); - - // Calculate RPM - rpm = ((clock * ulVelCapValue * 60) / (Load * ulPPR * edges)); - - return (uint32_t)(rpm); -} - - -/** - * @} - */ - -#endif /*_QEI*/ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_rtc.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_rtc.c deleted file mode 100644 index 9dd34b72285..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_rtc.c +++ /dev/null @@ -1,998 +0,0 @@ -/********************************************************************** -* $Id$ lpc_rtc.c 2011-06-02 -*//** -* @file lpc_rtc.c -* @brief Contains all functions support for RTC firmware library -* on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup RTC - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _RTC - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_rtc.h" -#include "lpc_clkpwr.h" - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup RTC_Public_Functions - * @{ - */ - -/********************************************************************//** - * @brief Initializes the RTC peripheral. - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @return None - *********************************************************************/ -void RTC_Init (LPC_RTC_TypeDef *RTCx) -{ - /* Set up clock and power for RTC module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCRTC, ENABLE); - - // Clear all register to be default - RTCx->ILR = 0x00; - RTCx->CCR = 0x00; - RTCx->CIIR = 0x00; - RTCx->AMR = 0xFF; - RTCx->CALIBRATION = 0x00; -} - - -/*********************************************************************//** - * @brief De-initializes the RTC peripheral registers to their -* default reset values. - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @return None - **********************************************************************/ -void RTC_DeInit(LPC_RTC_TypeDef *RTCx) -{ - RTCx->CCR = 0x00; - // Disable power and clock for RTC module - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCRTC, DISABLE); -} - -/*********************************************************************//** - * @brief Reset clock tick counter in RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @return None - **********************************************************************/ -void RTC_ResetClockTickCounter(LPC_RTC_TypeDef *RTCx) -{ - RTCx->CCR |= RTC_CCR_CTCRST; - RTCx->CCR &= (~RTC_CCR_CTCRST) & RTC_CCR_BITMASK; -} - -/*********************************************************************//** - * @brief Start/Stop RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] NewState New State of this function, should be: - * - ENABLE: The time counters are enabled - * - DISABLE: The time counters are disabled - * @return None - **********************************************************************/ -void RTC_Cmd (LPC_RTC_TypeDef *RTCx, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - RTCx->CCR |= RTC_CCR_CLKEN; - } - else - { - RTCx->CCR &= (~RTC_CCR_CLKEN) & RTC_CCR_BITMASK; - } -} - - -/*********************************************************************//** - * @brief Enable/Disable Counter increment interrupt for each time type - * in RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] CntIncrIntType: Counter Increment Interrupt type, - * an increment of this type value below will generates - * an interrupt, should be: - * - RTC_TIMETYPE_SECOND - * - RTC_TIMETYPE_MINUTE - * - RTC_TIMETYPE_HOUR - * - RTC_TIMETYPE_DAYOFWEEK - * - RTC_TIMETYPE_DAYOFMONTH - * - RTC_TIMETYPE_DAYOFYEAR - * - RTC_TIMETYPE_MONTH - * - RTC_TIMETYPE_YEAR - * @param[in] NewState New State of this function, should be: - * - ENABLE: Counter Increment interrupt for this - * time type are enabled - * - DISABLE: Counter Increment interrupt for this - * time type are disabled - * @return None - **********************************************************************/ -void RTC_CntIncrIntConfig (LPC_RTC_TypeDef *RTCx, uint32_t CntIncrIntType, \ - FunctionalState NewState) -{ - if (NewState == ENABLE) - { - switch (CntIncrIntType) - { - case RTC_TIMETYPE_SECOND: - RTCx->CIIR |= RTC_CIIR_IMSEC; - break; - case RTC_TIMETYPE_MINUTE: - RTCx->CIIR |= RTC_CIIR_IMMIN; - break; - case RTC_TIMETYPE_HOUR: - RTCx->CIIR |= RTC_CIIR_IMHOUR; - break; - case RTC_TIMETYPE_DAYOFWEEK: - RTCx->CIIR |= RTC_CIIR_IMDOW; - break; - case RTC_TIMETYPE_DAYOFMONTH: - RTCx->CIIR |= RTC_CIIR_IMDOM; - break; - case RTC_TIMETYPE_DAYOFYEAR: - RTCx->CIIR |= RTC_CIIR_IMDOY; - break; - case RTC_TIMETYPE_MONTH: - RTCx->CIIR |= RTC_CIIR_IMMON; - break; - case RTC_TIMETYPE_YEAR: - RTCx->CIIR |= RTC_CIIR_IMYEAR; - break; - } - } - else - { - switch (CntIncrIntType) - { - case RTC_TIMETYPE_SECOND: - RTCx->CIIR &= (~RTC_CIIR_IMSEC) & RTC_CIIR_BITMASK; - break; - case RTC_TIMETYPE_MINUTE: - RTCx->CIIR &= (~RTC_CIIR_IMMIN) & RTC_CIIR_BITMASK; - break; - case RTC_TIMETYPE_HOUR: - RTCx->CIIR &= (~RTC_CIIR_IMHOUR) & RTC_CIIR_BITMASK; - break; - case RTC_TIMETYPE_DAYOFWEEK: - RTCx->CIIR &= (~RTC_CIIR_IMDOW) & RTC_CIIR_BITMASK; - break; - case RTC_TIMETYPE_DAYOFMONTH: - RTCx->CIIR &= (~RTC_CIIR_IMDOM) & RTC_CIIR_BITMASK; - break; - case RTC_TIMETYPE_DAYOFYEAR: - RTCx->CIIR &= (~RTC_CIIR_IMDOY) & RTC_CIIR_BITMASK; - break; - case RTC_TIMETYPE_MONTH: - RTCx->CIIR &= (~RTC_CIIR_IMMON) & RTC_CIIR_BITMASK; - break; - case RTC_TIMETYPE_YEAR: - RTCx->CIIR &= (~RTC_CIIR_IMYEAR) & RTC_CIIR_BITMASK; - break; - } - } -} - - -/*********************************************************************//** - * @brief Enable/Disable Alarm interrupt for each time type - * in RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] AlarmTimeType: Alarm Time Interrupt type, - * an matching of this type value below with current time - * in RTC will generates an interrupt, should be: - * - RTC_TIMETYPE_SECOND - * - RTC_TIMETYPE_MINUTE - * - RTC_TIMETYPE_HOUR - * - RTC_TIMETYPE_DAYOFWEEK - * - RTC_TIMETYPE_DAYOFMONTH - * - RTC_TIMETYPE_DAYOFYEAR - * - RTC_TIMETYPE_MONTH - * - RTC_TIMETYPE_YEAR - * @param[in] NewState New State of this function, should be: - * - ENABLE: Alarm interrupt for this - * time type are enabled - * - DISABLE: Alarm interrupt for this - * time type are disabled - * @return None - **********************************************************************/ -void RTC_AlarmIntConfig (LPC_RTC_TypeDef *RTCx, uint32_t AlarmTimeType, \ - FunctionalState NewState) -{ - if (NewState == ENABLE) - { - switch (AlarmTimeType) - { - case RTC_TIMETYPE_SECOND: - RTCx->AMR &= (~RTC_AMR_AMRSEC) & RTC_AMR_BITMASK; - break; - case RTC_TIMETYPE_MINUTE: - RTCx->AMR &= (~RTC_AMR_AMRMIN) & RTC_AMR_BITMASK; - break; - case RTC_TIMETYPE_HOUR: - RTCx->AMR &= (~RTC_AMR_AMRHOUR) & RTC_AMR_BITMASK; - break; - case RTC_TIMETYPE_DAYOFWEEK: - RTCx->AMR &= (~RTC_AMR_AMRDOW) & RTC_AMR_BITMASK; - break; - case RTC_TIMETYPE_DAYOFMONTH: - RTCx->AMR &= (~RTC_AMR_AMRDOM) & RTC_AMR_BITMASK; - break; - case RTC_TIMETYPE_DAYOFYEAR: - RTCx->AMR &= (~RTC_AMR_AMRDOY) & RTC_AMR_BITMASK; - break; - case RTC_TIMETYPE_MONTH: - RTCx->AMR &= (~RTC_AMR_AMRMON) & RTC_AMR_BITMASK; - break; - case RTC_TIMETYPE_YEAR: - RTCx->AMR &= (~RTC_AMR_AMRYEAR) & RTC_AMR_BITMASK; - break; - } - } - else - { - switch (AlarmTimeType) - { - case RTC_TIMETYPE_SECOND: - RTCx->AMR |= (RTC_AMR_AMRSEC); - break; - case RTC_TIMETYPE_MINUTE: - RTCx->AMR |= (RTC_AMR_AMRMIN); - break; - case RTC_TIMETYPE_HOUR: - RTCx->AMR |= (RTC_AMR_AMRHOUR); - break; - case RTC_TIMETYPE_DAYOFWEEK: - RTCx->AMR |= (RTC_AMR_AMRDOW); - break; - case RTC_TIMETYPE_DAYOFMONTH: - RTCx->AMR |= (RTC_AMR_AMRDOM); - break; - case RTC_TIMETYPE_DAYOFYEAR: - RTCx->AMR |= (RTC_AMR_AMRDOY); - break; - case RTC_TIMETYPE_MONTH: - RTCx->AMR |= (RTC_AMR_AMRMON); - break; - case RTC_TIMETYPE_YEAR: - RTCx->AMR |= (RTC_AMR_AMRYEAR); - break; - } - } -} - - -/*********************************************************************//** - * @brief Set current time value for each time type in RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] Timetype: Time Type, should be: - * - RTC_TIMETYPE_SECOND - * - RTC_TIMETYPE_MINUTE - * - RTC_TIMETYPE_HOUR - * - RTC_TIMETYPE_DAYOFWEEK - * - RTC_TIMETYPE_DAYOFMONTH - * - RTC_TIMETYPE_DAYOFYEAR - * - RTC_TIMETYPE_MONTH - * - RTC_TIMETYPE_YEAR - * @param[in] TimeValue Time value to set - * @return None - **********************************************************************/ -void RTC_SetTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype, uint32_t TimeValue) -{ - switch ( Timetype) - { - case RTC_TIMETYPE_SECOND: - if(TimeValue <= RTC_SECOND_MAX) - RTCx->SEC = TimeValue & RTC_SEC_MASK; - break; - - case RTC_TIMETYPE_MINUTE: - if(TimeValue <= RTC_MINUTE_MAX) - RTCx->MIN = TimeValue & RTC_MIN_MASK; - break; - - case RTC_TIMETYPE_HOUR: - if(TimeValue <= RTC_HOUR_MAX) - RTCx->HOUR = TimeValue & RTC_HOUR_MASK; - break; - - case RTC_TIMETYPE_DAYOFWEEK: - if(TimeValue <= RTC_DAYOFWEEK_MAX) - RTCx->DOW = TimeValue & RTC_DOW_MASK; - break; - - case RTC_TIMETYPE_DAYOFMONTH: - if((TimeValue >= RTC_DAYOFMONTH_MIN)&&(TimeValue <= RTC_DAYOFMONTH_MAX)) - RTCx->DOM = TimeValue & RTC_DOM_MASK; - break; - - case RTC_TIMETYPE_DAYOFYEAR: - if((TimeValue >= RTC_DAYOFYEAR_MIN)&&(TimeValue <= RTC_DAYOFYEAR_MAX)) - RTCx->DOY = TimeValue & RTC_DOY_MASK; - break; - - case RTC_TIMETYPE_MONTH: - if((TimeValue >= RTC_MONTH_MIN)&&(TimeValue <= RTC_MONTH_MAX)) - RTCx->MONTH = TimeValue & RTC_MONTH_MASK; - break; - - case RTC_TIMETYPE_YEAR: - if(TimeValue <= RTC_YEAR_MAX) - RTCx->YEAR = TimeValue & RTC_YEAR_MASK; - break; - } -} - -/*********************************************************************//** - * @brief Get current time value for each type time type - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] Timetype: Time Type, should be: - * - RTC_TIMETYPE_SECOND - * - RTC_TIMETYPE_MINUTE - * - RTC_TIMETYPE_HOUR - * - RTC_TIMETYPE_DAYOFWEEK - * - RTC_TIMETYPE_DAYOFMONTH - * - RTC_TIMETYPE_DAYOFYEAR - * - RTC_TIMETYPE_MONTH - * - RTC_TIMETYPE_YEAR - * @return Value of time according to specified time type - **********************************************************************/ -uint32_t RTC_GetTime(LPC_RTC_TypeDef *RTCx, uint32_t Timetype) -{ - switch (Timetype) - { - case RTC_TIMETYPE_SECOND: - return (RTCx->SEC & RTC_SEC_MASK); - case RTC_TIMETYPE_MINUTE: - return (RTCx->MIN & RTC_MIN_MASK); - case RTC_TIMETYPE_HOUR: - return (RTCx->HOUR & RTC_HOUR_MASK); - case RTC_TIMETYPE_DAYOFWEEK: - return (RTCx->DOW & RTC_DOW_MASK); - case RTC_TIMETYPE_DAYOFMONTH: - return (RTCx->DOM & RTC_DOM_MASK); - case RTC_TIMETYPE_DAYOFYEAR: - return (RTCx->DOY & RTC_DOY_MASK); - case RTC_TIMETYPE_MONTH: - return (RTCx->MONTH & RTC_MONTH_MASK); - case RTC_TIMETYPE_YEAR: - return (RTCx->YEAR & RTC_YEAR_MASK); - default: - return (0); - } -} - - -/*********************************************************************//** - * @brief Set full of time in RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] pFullTime Pointer to a RTC_TIME_Type structure that - * contains time value in full. - * @return None - **********************************************************************/ -void RTC_SetFullTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime) -{ - RTCx->DOM = pFullTime->DOM & RTC_DOM_MASK; - RTCx->DOW = pFullTime->DOW & RTC_DOW_MASK; - RTCx->DOY = pFullTime->DOY & RTC_DOY_MASK; - RTCx->HOUR = pFullTime->HOUR & RTC_HOUR_MASK; - RTCx->MIN = pFullTime->MIN & RTC_MIN_MASK; - RTCx->SEC = pFullTime->SEC & RTC_SEC_MASK; - RTCx->MONTH = pFullTime->MONTH & RTC_MONTH_MASK; - RTCx->YEAR = pFullTime->YEAR & RTC_YEAR_MASK; -} - - -/*********************************************************************//** - * @brief Get full of time in RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] pFullTime Pointer to a RTC_TIME_Type structure that - * will be stored time in full. - * @return None - **********************************************************************/ -void RTC_GetFullTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime) -{ - pFullTime->DOM = RTCx->DOM & RTC_DOM_MASK; - pFullTime->DOW = RTCx->DOW & RTC_DOW_MASK; - pFullTime->DOY = RTCx->DOY & RTC_DOY_MASK; - pFullTime->HOUR = RTCx->HOUR & RTC_HOUR_MASK; - pFullTime->MIN = RTCx->MIN & RTC_MIN_MASK; - pFullTime->SEC = RTCx->SEC & RTC_SEC_MASK; - pFullTime->MONTH = RTCx->MONTH & RTC_MONTH_MASK; - pFullTime->YEAR = RTCx->YEAR & RTC_YEAR_MASK; -} - - -/*********************************************************************//** - * @brief Set alarm time value for each time type - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] Timetype: Time Type, should be: - * - RTC_TIMETYPE_SECOND - * - RTC_TIMETYPE_MINUTE - * - RTC_TIMETYPE_HOUR - * - RTC_TIMETYPE_DAYOFWEEK - * - RTC_TIMETYPE_DAYOFMONTH - * - RTC_TIMETYPE_DAYOFYEAR - * - RTC_TIMETYPE_MONTH - * - RTC_TIMETYPE_YEAR - * @param[in] ALValue Alarm time value to set - * @return None - **********************************************************************/ -void RTC_SetAlarmTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype, uint32_t ALValue) -{ - switch (Timetype) - { - case RTC_TIMETYPE_SECOND: - if(ALValue <= RTC_SECOND_MAX) - RTCx->ALSEC = ALValue & RTC_SEC_MASK; - break; - - case RTC_TIMETYPE_MINUTE: - if(ALValue <= RTC_MINUTE_MAX) - RTCx->ALMIN = ALValue & RTC_MIN_MASK; - break; - - case RTC_TIMETYPE_HOUR: - if(ALValue <= RTC_HOUR_MAX) - RTCx->ALHOUR = ALValue & RTC_HOUR_MASK; - break; - - case RTC_TIMETYPE_DAYOFWEEK: - if(ALValue <= RTC_DAYOFWEEK_MAX) - RTCx->ALDOW = ALValue & RTC_DOW_MASK; - break; - - case RTC_TIMETYPE_DAYOFMONTH: - if((ALValue >= RTC_DAYOFMONTH_MIN)&&(ALValue <= RTC_DAYOFMONTH_MAX)) - RTCx->ALDOM = ALValue & RTC_DOM_MASK; - break; - - case RTC_TIMETYPE_DAYOFYEAR: - if((ALValue >= RTC_DAYOFYEAR_MIN)&&(ALValue <= RTC_DAYOFYEAR_MAX)) - RTCx->ALDOY = ALValue & RTC_DOY_MASK; - break; - - case RTC_TIMETYPE_MONTH: - if((ALValue >= RTC_MONTH_MIN)&&(ALValue <= RTC_MONTH_MAX)) - RTCx->ALMON = ALValue & RTC_MONTH_MASK; - break; - - case RTC_TIMETYPE_YEAR: - if(ALValue <= RTC_YEAR_MAX) - RTCx->ALYEAR = ALValue & RTC_YEAR_MASK; - break; - } -} - - - -/*********************************************************************//** - * @brief Get alarm time value for each time type - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] Timetype: Time Type, should be: - * - RTC_TIMETYPE_SECOND - * - RTC_TIMETYPE_MINUTE - * - RTC_TIMETYPE_HOUR - * - RTC_TIMETYPE_DAYOFWEEK - * - RTC_TIMETYPE_DAYOFMONTH - * - RTC_TIMETYPE_DAYOFYEAR - * - RTC_TIMETYPE_MONTH - * - RTC_TIMETYPE_YEAR - * @return Value of Alarm time according to specified time type - **********************************************************************/ -uint32_t RTC_GetAlarmTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype) -{ - switch (Timetype) - { - case RTC_TIMETYPE_SECOND: - return (RTCx->ALSEC & RTC_SEC_MASK); - case RTC_TIMETYPE_MINUTE: - return (RTCx->ALMIN & RTC_MIN_MASK); - case RTC_TIMETYPE_HOUR: - return (RTCx->ALHOUR & RTC_HOUR_MASK); - case RTC_TIMETYPE_DAYOFWEEK: - return (RTCx->ALDOW & RTC_DOW_MASK); - case RTC_TIMETYPE_DAYOFMONTH: - return (RTCx->ALDOM & RTC_DOM_MASK); - case RTC_TIMETYPE_DAYOFYEAR: - return (RTCx->ALDOY & RTC_DOY_MASK); - case RTC_TIMETYPE_MONTH: - return (RTCx->ALMON & RTC_MONTH_MASK); - case RTC_TIMETYPE_YEAR: - return (RTCx->ALYEAR & RTC_YEAR_MASK); - default: - return (0); - } -} - - -/*********************************************************************//** - * @brief Set full of alarm time in RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] pFullTime Pointer to a RTC_TIME_Type structure that - * contains alarm time value in full. - * @return None - **********************************************************************/ -void RTC_SetFullAlarmTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime) -{ - RTCx->ALDOM = pFullTime->DOM & RTC_DOM_MASK; - RTCx->ALDOW = pFullTime->DOW & RTC_DOW_MASK; - RTCx->ALDOY = pFullTime->DOY & RTC_DOY_MASK; - RTCx->ALHOUR = pFullTime->HOUR & RTC_HOUR_MASK; - RTCx->ALMIN = pFullTime->MIN & RTC_MIN_MASK; - RTCx->ALSEC = pFullTime->SEC & RTC_SEC_MASK; - RTCx->ALMON = pFullTime->MONTH & RTC_MONTH_MASK; - RTCx->ALYEAR = pFullTime->YEAR & RTC_YEAR_MASK; -} - - -/*********************************************************************//** - * @brief Get full of alarm time in RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] pFullTime Pointer to a RTC_TIME_Type structure that - * will be stored alarm time in full. - * @return None - **********************************************************************/ -void RTC_GetFullAlarmTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime) -{ - pFullTime->DOM = RTCx->ALDOM & RTC_DOM_MASK; - pFullTime->DOW = RTCx->ALDOW & RTC_DOW_MASK; - pFullTime->DOY = RTCx->ALDOY & RTC_DOY_MASK; - pFullTime->HOUR = RTCx->ALHOUR & RTC_HOUR_MASK; - pFullTime->MIN = RTCx->ALMIN & RTC_MIN_MASK; - pFullTime->SEC = RTCx->ALSEC & RTC_SEC_MASK; - pFullTime->MONTH = RTCx->ALMON & RTC_MONTH_MASK; - pFullTime->YEAR = RTCx->ALYEAR & RTC_YEAR_MASK; -} - - -/*********************************************************************//** - * @brief Check whether if specified Location interrupt in - * RTC peripheral is set or not - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] IntType Interrupt location type, should be: - * - RTC_INT_COUNTER_INCREASE: Counter Increment Interrupt - * block generated an interrupt. - * - RTC_INT_ALARM: Alarm generated an - * interrupt. - * @return New state of specified Location interrupt in RTC peripheral - * (SET or RESET) - **********************************************************************/ -IntStatus RTC_GetIntPending (LPC_RTC_TypeDef *RTCx, uint32_t IntType) -{ - return ((RTCx->ILR & IntType) ? SET : RESET); -} - - -/*********************************************************************//** - * @brief Clear specified Location interrupt pending in - * RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] IntType Interrupt location type, should be: - * - RTC_INT_COUNTER_INCREASE: Clear Counter Increment - * Interrupt pending. - * - RTC_INT_ALARM: Clear alarm interrupt pending - * @return None - **********************************************************************/ -void RTC_ClearIntPending (LPC_RTC_TypeDef *RTCx, uint32_t IntType) -{ - RTCx->ILR |= IntType; -} - -/*********************************************************************//** - * @brief Enable/Disable calibration counter in RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] NewState New State of this function, should be: - * - ENABLE: The calibration counter is enabled and counting - * - DISABLE: The calibration counter is disabled and reset to zero - * @return None - **********************************************************************/ -void RTC_CalibCounterCmd(LPC_RTC_TypeDef *RTCx, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - RTCx->CCR &= (~RTC_CCR_CCALEN) & RTC_CCR_BITMASK; - } - else - { - RTCx->CCR |= RTC_CCR_CCALEN; - } -} - - -/*********************************************************************//** - * @brief Configures Calibration in RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] CalibValue Calibration value, should be in range from - * 0 to 131,072 - * @param[in] CalibDir Calibration Direction, should be: - * - RTC_CALIB_DIR_FORWARD: Forward calibration - * - RTC_CALIB_DIR_BACKWARD: Backward calibration - * @return None - **********************************************************************/ -void RTC_CalibConfig(LPC_RTC_TypeDef *RTCx, uint32_t CalibValue, uint8_t CalibDir) -{ - RTCx->CALIBRATION = ((CalibValue) & RTC_CALIBRATION_CALVAL_MASK) \ - | ((CalibDir == RTC_CALIB_DIR_BACKWARD) ? RTC_CALIBRATION_LIBDIR : 0); -} - - -/*********************************************************************//** - * @brief Write value to General purpose registers - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] Channel General purpose registers Channel number, - * should be in range from 0 to 4. - * @param[in] Value Value to write - * @return None - * Note: These General purpose registers can be used to store important - * information when the main power supply is off. The value in these - * registers is not affected by chip reset. - **********************************************************************/ -void RTC_WriteGPREG (LPC_RTC_TypeDef *RTCx, uint8_t Channel, uint32_t Value) -{ - uint32_t *preg; - - preg = (uint32_t *)&RTCx->GPREG0; - preg += Channel; - *preg = Value; -} - - -/*********************************************************************//** - * @brief Read value from General purpose registers - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] Channel General purpose registers Channel number, - * should be in range from 0 to 4. - * @return Read Value - * Note: These General purpose registers can be used to store important - * information when the main power supply is off. The value in these - * registers is not affected by chip reset. - **********************************************************************/ -uint32_t RTC_ReadGPREG (LPC_RTC_TypeDef *RTCx, uint8_t Channel) -{ - uint32_t *preg; - uint32_t value; - - preg = (uint32_t *)&RTCx->GPREG0; - preg += Channel; - value = *preg; - return (value); -} -/*********************************************************************//** - * @brief Initialize an variable of type RTC_ER_CONFIG_Type. - * @param[in] pConfig The address of input variable. - * @return None - **********************************************************************/ -void RTC_ER_InitConfigStruct(RTC_ER_CONFIG_Type* pConfig) -{ - uint32_t tmp; - if(pConfig == NULL) - return; - - for(tmp = 0; tmp < RTC_ER_INPUT_CHANNEL_NUM; tmp++) - { - pConfig->InputChannel[tmp].EventOnPosEdge = FALSE; - pConfig->InputChannel[tmp].GPClear= FALSE; - pConfig->InputChannel[tmp].IntWake= FALSE; - } - pConfig->Clk = 64; -} - -/*********************************************************************//** - * @brief Initialize Event Monitor/Recorder - * @param[in] pConfig Configuration - * @return SUCCESS/ERROR - * Note: The RTC Module must be intialized before initializing this module. - **********************************************************************/ -Status RTC_ER_Init(RTC_ER_CONFIG_Type* pConfig) -{ - if(pConfig == NULL) - return ERROR; - if((LPC_RTC->CCR & RTC_CCR_CLKEN) == 0) - return ERROR; - - /* EV0 */ - if(pConfig->InputChannel[0].EventOnPosEdge) - LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV0_POS_EDGE; - else - LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV0_POS_EDGE; - - if(pConfig->InputChannel[0].IntWake) - LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV0_INTWAKE_ENABLE; - else - LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV0_INTWAKE_ENABLE; - - if(pConfig->InputChannel[0].GPClear) - LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV0_GPCLEAR_ENABLE; - else - LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV0_GPCLEAR_ENABLE; - - /* EV1 */ - if(pConfig->InputChannel[1].EventOnPosEdge) - LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV1_POS_EDGE; - else - LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV1_POS_EDGE; - - if(pConfig->InputChannel[1].IntWake) - LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV1_INTWAKE_ENABLE; - else - LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV1_INTWAKE_ENABLE; - - if(pConfig->InputChannel[1].GPClear) - LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV1_GPCLEAR_ENABLE; - else - LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV1_GPCLEAR_ENABLE; - - /* EV2 */ - if(pConfig->InputChannel[2].EventOnPosEdge) - LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV2_POS_EDGE; - else - LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV2_POS_EDGE; - - if(pConfig->InputChannel[2].IntWake) - LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV2_INTWAKE_ENABLE; - else - LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV2_INTWAKE_ENABLE; - - if(pConfig->InputChannel[2].GPClear) - LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV2_GPCLEAR_ENABLE; - else - LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV2_GPCLEAR_ENABLE; - - /* Sample Clock */ - LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_MODE_MASK; - switch(pConfig->Clk) - { - case 0: - LPC_RTC->ERCONTROL |= RTC_ERCTRL_MODE_CLK_DISABLE; - break; - case 16: - LPC_RTC->ERCONTROL |= RTC_ERCTRL_MODE_16HZ; - break; - case 64: - LPC_RTC->ERCONTROL |= RTC_ERCTRL_MODE_64HZ; - break; - case 1000: - LPC_RTC->ERCONTROL |= RTC_ERCTRL_MODE_1KHZ; - break; - default: - return ERROR; - } - return SUCCESS; -} -/*********************************************************************//** - * @brief Enable/Disable a input channel for Event Monitor/Recorder - * @param[in] channel Channel Number. It should be 0~2 - * @param[in]state ENABLE/DISABLE - * @return SUCCESS/ERROR - **********************************************************************/ -Status RTC_ER_Cmd(uint8_t channel, FunctionalState state) -{ - switch(channel) - { - case 0: - if(state) - LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV0_INPUT_ENABLE; - else - LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV0_INPUT_ENABLE; - break; - case 1: - if(state) - LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV1_INPUT_ENABLE; - else - LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV1_INPUT_ENABLE; - break; - case 2: - if(state) - LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV2_INPUT_ENABLE; - else - LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV2_INPUT_ENABLE; - break; - default: - return ERROR; - } - return SUCCESS; -} -/*********************************************************************//** - * @brief Get event count on a given channel. - * @param[in] channel Channel Number. It should be 0~2 - * @return counter - **********************************************************************/ -uint8_t RTC_ER_GetEventCount(uint8_t channel) -{ - uint8_t count = 0; - switch(channel) - { - case 0: - count = RTC_ER_EV0_COUNTER(LPC_RTC->ERCOUNTERS); - break; - case 1: - count = RTC_ER_EV1_COUNTER(LPC_RTC->ERCOUNTERS); - break; - case 2: - count = RTC_ER_EV2_COUNTER(LPC_RTC->ERCOUNTERS); - break; - default: - break; - } - return count; -} -/*********************************************************************//** - * @brief Get Event Monirot/Recorder Status. - * @param[in] None - * @return Status. It can includes: - * RTC_ER_EVENTS_ON_EV0_FLG - * RTC_ER_EVENTS_ON_EV1_FLG - * RTC_ER_EVENTS_ON_EV2_FLG - * RTC_ER_STATUS_GP_CLEARED_FLG - * RTC_ER_STATUS_WAKEUP_REQ_PENDING - **********************************************************************/ -uint32_t RTC_ER_GetStatus(void) -{ - return LPC_RTC->ERSTATUS; -} -/*********************************************************************//** - * @brief Clear Event Monitor/recoder status register. - * @param[in] status Status Flag. It should be: - * RTC_ER_EVENTS_ON_EV0_FLG - * RTC_ER_EVENTS_ON_EV1_FLG - * RTC_ER_EVENTS_ON_EV2_FLG - * RTC_ER_STATUS_GP_CLEARED_FLG - * RTC_ER_STATUS_WAKEUP_REQ_PENDING - * @return None - **********************************************************************/ -void RTC_ER_ClearStatus(uint32_t status) -{ - LPC_RTC->ERSTATUS |= status; -} -/*********************************************************************//** - * @brief Check whether a Wakup request is pending or not. - * @param[in] None - * @return TRUE/FALSE - **********************************************************************/ -Bool RTC_ER_WakupReqPending(void) -{ - if(LPC_RTC->ERSTATUS & RTC_ER_STATUS_WAKEUP_REQ_PENDING) - return TRUE; - else - return FALSE; -} -/*********************************************************************//** - * @brief Check whether RTC General Purpose registed has been cleared or not. - * @param[in] None - * @return TRUE/FALSE - **********************************************************************/ -Bool RTC_ER_GPCleared(void) -{ - if(LPC_RTC->ERSTATUS & RTC_ER_STATUS_GP_CLEARED_FLG) - return TRUE; - else - return FALSE; -} -/*********************************************************************//** - * @brief Get the timestamp of the fist event on a given channel. - * @param[in] channel Channel number (It should be 0~2) - * @param[in] pTimeStamp point to the buffer - * @return SUCCESS/ERROR - **********************************************************************/ -Status RTC_ER_GetFirstTimeStamp(uint8_t channel, RTC_ER_TIMESTAMP_Type* pTimeStamp) -{ - if(pTimeStamp == NULL) - return ERROR; - - switch(channel) - { - case 0: - if((LPC_RTC->ERSTATUS & (1<SEC = RTC_ER_TIMESTAMP_SEC(LPC_RTC->ERFIRSTSTAMP0); - pTimeStamp->MIN= RTC_ER_TIMESTAMP_MIN(LPC_RTC->ERFIRSTSTAMP0); - pTimeStamp->HOUR= RTC_ER_TIMESTAMP_HOUR(LPC_RTC->ERFIRSTSTAMP0); - pTimeStamp->DOY = RTC_ER_TIMESTAMP_DOY(LPC_RTC->ERFIRSTSTAMP0); - break; - case 1: - if((LPC_RTC->ERSTATUS & (1<SEC = RTC_ER_TIMESTAMP_SEC(LPC_RTC->ERFIRSTSTAMP1); - pTimeStamp->MIN= RTC_ER_TIMESTAMP_MIN(LPC_RTC->ERFIRSTSTAMP1); - pTimeStamp->HOUR= RTC_ER_TIMESTAMP_HOUR(LPC_RTC->ERFIRSTSTAMP1); - pTimeStamp->DOY = RTC_ER_TIMESTAMP_DOY(LPC_RTC->ERFIRSTSTAMP1); - break; - case 2: - if((LPC_RTC->ERSTATUS & (1<SEC = RTC_ER_TIMESTAMP_SEC(LPC_RTC->ERFIRSTSTAMP2); - pTimeStamp->MIN= RTC_ER_TIMESTAMP_MIN(LPC_RTC->ERFIRSTSTAMP2); - pTimeStamp->HOUR= RTC_ER_TIMESTAMP_HOUR(LPC_RTC->ERFIRSTSTAMP2); - pTimeStamp->DOY = RTC_ER_TIMESTAMP_DOY(LPC_RTC->ERFIRSTSTAMP2); - break; - default: - break; - } - return SUCCESS; - -} -/*********************************************************************//** - * @brief Get the timestamp of the last event on a given channel. - * @param[in] channel Channel number (It should be 0~2) - * @param[in] pTimeStamp point to the buffer - * @return SUCCESS/ERROR - **********************************************************************/ -Status RTC_ER_GetLastTimeStamp(uint8_t channel, RTC_ER_TIMESTAMP_Type* pTimeStamp) -{ - if(pTimeStamp == NULL) - return ERROR; - - switch(channel) - { - case 0: - if((LPC_RTC->ERSTATUS & (1<SEC = RTC_ER_TIMESTAMP_SEC(LPC_RTC->ERLASTSTAMP0); - pTimeStamp->MIN= RTC_ER_TIMESTAMP_MIN(LPC_RTC->ERLASTSTAMP0); - pTimeStamp->HOUR= RTC_ER_TIMESTAMP_HOUR(LPC_RTC->ERLASTSTAMP0); - pTimeStamp->DOY = RTC_ER_TIMESTAMP_DOY(LPC_RTC->ERLASTSTAMP0); - break; - case 1: - if((LPC_RTC->ERSTATUS & (1<SEC = RTC_ER_TIMESTAMP_SEC(LPC_RTC->ERLASTSTAMP1); - pTimeStamp->MIN= RTC_ER_TIMESTAMP_MIN(LPC_RTC->ERLASTSTAMP1); - pTimeStamp->HOUR= RTC_ER_TIMESTAMP_HOUR(LPC_RTC->ERLASTSTAMP1); - pTimeStamp->DOY = RTC_ER_TIMESTAMP_DOY(LPC_RTC->ERLASTSTAMP1); - break; - case 2: - if((LPC_RTC->ERSTATUS & (1<SEC = RTC_ER_TIMESTAMP_SEC(LPC_RTC->ERLASTSTAMP2); - pTimeStamp->MIN= RTC_ER_TIMESTAMP_MIN(LPC_RTC->ERLASTSTAMP2); - pTimeStamp->HOUR= RTC_ER_TIMESTAMP_HOUR(LPC_RTC->ERLASTSTAMP2); - pTimeStamp->DOY = RTC_ER_TIMESTAMP_DOY(LPC_RTC->ERLASTSTAMP2); - break; - default: - break; - } - return SUCCESS; - -} - - -/** - * @} - */ - -#endif /*_RTC*/ -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_ssp.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_ssp.c deleted file mode 100644 index f197e5b4e41..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_ssp.c +++ /dev/null @@ -1,644 +0,0 @@ -/********************************************************************** -* $Id$ lpc_ssp.c 2011-06-02 -*//** -* @file lpc_ssp.c -* @brief Contains all functions support for SSP firmware library -* on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup SSP - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _SSP - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_ssp.h" -#include "lpc_clkpwr.h" - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup SSP_Public_Functions - * @{ - */ -static void setSSPclock (LPC_SSP_TypeDef *SSPx, uint32_t target_clock); - -/*********************************************************************//** - * @brief Setup clock rate for SSP device - * @param[in] SSPx SSP peripheral definition, should be: - * - LPC_SSP0: SSP0 peripheral - * - LPC_SSP1: SSP1 peripheral - * @param[in] target_clock : clock of SSP (Hz) - * @return None - ***********************************************************************/ -static void setSSPclock (LPC_SSP_TypeDef *SSPx, uint32_t target_clock) -{ - uint32_t prescale, cr0_div, cmp_clk, ssp_clk; - ssp_clk = CLKPWR_GetCLK (CLKPWR_CLKTYPE_PER); - - /* Find closest divider to get at or under the target frequency. - Use smallest prescale possible and rely on the divider to get - the closest target frequency */ - cr0_div = 0; - cmp_clk = 0xFFFFFFFF; - prescale = 2; - while (cmp_clk > target_clock) - { - cmp_clk = ssp_clk / ((cr0_div + 1) * prescale); - if (cmp_clk > target_clock) - { - cr0_div++; - if (cr0_div > 0xFF) - { - cr0_div = 0; - prescale += 2; - } - } - } - - /* Write computed prescaler and divider back to register */ - SSPx->CR0 &= (~SSP_CR0_SCR(0xFF)) & SSP_CR0_BITMASK; - SSPx->CR0 |= (SSP_CR0_SCR(cr0_div)) & SSP_CR0_BITMASK; - SSPx->CPSR = prescale & SSP_CPSR_BITMASK; -} - -/** - * @} - */ - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup SSP_Public_Functions - * @{ - */ - -/********************************************************************//** - * @brief Initializes the SSPx peripheral according to the specified -* parameters in the SSP_ConfigStruct. - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0: SSP0 peripheral - * - LPC_SSP1: SSP1 peripheral - * @param[in] SSP_ConfigStruct Pointer to a SSP_CFG_Type structure -* that contains the configuration information for the -* specified SSP peripheral. - * @return None - *********************************************************************/ -void SSP_Init(LPC_SSP_TypeDef *SSPx, SSP_CFG_Type *SSP_ConfigStruct) -{ - uint32_t tmp; - - if(SSPx == LPC_SSP0) { - /* Set up clock and power for SSP0 module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSSP0, ENABLE); - } else if(SSPx == LPC_SSP1) { - /* Set up clock and power for SSP1 module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSSP1, ENABLE); - } else if(SSPx == LPC_SSP2) { - /* Set up clock and power for SSP1 module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSSP2, ENABLE); - } else { - return; - } - - /* Configure SSP, interrupt is disable, LoopBack mode is disable, - * SSP is disable, Slave output is disable as default - */ - tmp = ((SSP_ConfigStruct->CPHA) | (SSP_ConfigStruct->CPOL) \ - | (SSP_ConfigStruct->FrameFormat) | (SSP_ConfigStruct->Databit)) - & SSP_CR0_BITMASK; - // write back to SSP control register - SSPx->CR0 = tmp; - - tmp = SSP_ConfigStruct->Mode & SSP_CR1_BITMASK; - // Write back to CR1 - SSPx->CR1 = tmp; - - // Set clock rate for SSP peripheral - setSSPclock(SSPx, SSP_ConfigStruct->ClockRate); -} - -/*********************************************************************//** - * @brief De-initializes the SSPx peripheral registers to their -* default reset values. - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0: SSP0 peripheral - * - LPC_SSP1: SSP1 peripheral - * @return None - **********************************************************************/ -void SSP_DeInit(LPC_SSP_TypeDef* SSPx) -{ - if (SSPx == LPC_SSP0){ - /* Set up clock and power for SSP0 module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSSP0, DISABLE); - } else if (SSPx == LPC_SSP1) { - /* Set up clock and power for SSP1 module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSSP1, DISABLE); - } else if (SSPx == LPC_SSP2) { - /* Set up clock and power for SSP1 module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSSP2, DISABLE); - } -} - -/*****************************************************************************//** -* @brief Get data size bit selected -* @param[in] SSPx pointer to LPC_SSP_TypeDef structure, should be: -* - LPC_SSP0: SSP0 peripheral -* - LPC_SSP1: SSP1 peripheral -* @return Data size, could be: -* - SSP_DATABIT_4: 4 bit transfer -* - SSP_DATABIT_5: 5 bit transfer -* ... -* - SSP_DATABIT_16: 16 bit transfer -*******************************************************************************/ -uint8_t SSP_GetDataSize(LPC_SSP_TypeDef* SSPx) -{ - return (SSPx->CR0 & (0xF)); -} - -/*****************************************************************************//** -* @brief Fills each SSP_InitStruct member with its default value: -* - CPHA = SSP_CPHA_FIRST -* - CPOL = SSP_CPOL_HI -* - ClockRate = 1000000 -* - Databit = SSP_DATABIT_8 -* - Mode = SSP_MASTER_MODE -* - FrameFormat = SSP_FRAME_SSP -* @param[in] SSP_InitStruct Pointer to a SSP_CFG_Type structure -* which will be initialized. -* @return None -*******************************************************************************/ -void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct) -{ - SSP_InitStruct->CPHA = SSP_CPHA_FIRST; - SSP_InitStruct->CPOL = SSP_CPOL_HI; - SSP_InitStruct->ClockRate = 1000000; - SSP_InitStruct->Databit = SSP_DATABIT_8; - SSP_InitStruct->Mode = SSP_MASTER_MODE; - SSP_InitStruct->FrameFormat = SSP_FRAME_SPI; -} - - -/*********************************************************************//** - * @brief Enable or disable SSP peripheral's operation - * @param[in] SSPx SSP peripheral, should be: - * - LPC_SSP0: SSP0 peripheral - * - LPC_SSP1: SSP1 peripheral - * @param[in] NewState New State of SSPx peripheral's operation - * @return none - **********************************************************************/ -void SSP_Cmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - SSPx->CR1 |= SSP_CR1_SSP_EN; - } - else - { - SSPx->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK; - } -} - -/*********************************************************************//** - * @brief Enable or disable Loop Back mode function in SSP peripheral - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0: SSP0 peripheral - * - LPC_SSP1: SSP1 peripheral - * @param[in] NewState New State of Loop Back mode, should be: - * - ENABLE: Enable this function - * - DISABLE: Disable this function - * @return None - **********************************************************************/ -void SSP_LoopBackCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - SSPx->CR1 |= SSP_CR1_LBM_EN; - } - else - { - SSPx->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK; - } -} - -/*********************************************************************//** - * @brief Enable or disable Slave Output function in SSP peripheral - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0: SSP0 peripheral - * - LPC_SSP1: SSP1 peripheral - * @param[in] NewState New State of Slave Output function, should be: - * - ENABLE: Slave Output in normal operation - * - DISABLE: Slave Output is disabled. This blocks - * SSP controller from driving the transmit data - * line (MISO) - * Note: This function is available when SSP peripheral in Slave mode - * @return None - **********************************************************************/ -void SSP_SlaveOutputCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - SSPx->CR1 &= (~SSP_CR1_SO_DISABLE) & SSP_CR1_BITMASK; - } - else - { - SSPx->CR1 |= SSP_CR1_SO_DISABLE; - } -} - - - -/*********************************************************************//** - * @brief Transmit a single data through SSPx peripheral - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0: SSP0 peripheral - * - LPC_SSP1: SSP1 peripheral - * @param[in] Data Data to transmit (must be 16 or 8-bit long, - * this depend on SSP data bit number configured) - * @return none - **********************************************************************/ -void SSP_SendData(LPC_SSP_TypeDef* SSPx, uint16_t Data) -{ - SSPx->DR = SSP_DR_BITMASK(Data); -} - - - -/*********************************************************************//** - * @brief Receive a single data from SSPx peripheral - * @param[in] SSPx SSP peripheral selected, should be - * - LPC_SSP0: SSP0 peripheral - * - LPC_SSP1: SSP1 peripheral - * @return Data received (16-bit long) - **********************************************************************/ -uint16_t SSP_ReceiveData(LPC_SSP_TypeDef* SSPx) -{ - return ((uint16_t) (SSP_DR_BITMASK(SSPx->DR))); -} - -/*********************************************************************//** - * @brief SSP Read write data function - * @param[in] SSPx Pointer to SSP peripheral, should be - * - LPC_SSP0: SSP0 peripheral - * - LPC_SSP1: SSP1 peripheral - * @param[in] dataCfg Pointer to a SSP_DATA_SETUP_Type structure that - * contains specified information about transmit - * data configuration. - * @param[in] xfType Transfer type, should be: - * - SSP_TRANSFER_POLLING: Polling mode - * - SSP_TRANSFER_INTERRUPT: Interrupt mode - * @return Actual Data length has been transferred in polling mode. - * In interrupt mode, always return (0) - * Return (-1) if error. - * Note: This function can be used in both master and slave mode. - ***********************************************************************/ -int32_t SSP_ReadWrite (LPC_SSP_TypeDef *SSPx, SSP_DATA_SETUP_Type *dataCfg, \ - SSP_TRANSFER_Type xfType) -{ - uint8_t *rdata8; - uint8_t *wdata8; - uint16_t *rdata16; - uint16_t *wdata16; - uint32_t stat; - uint32_t tmp; - int32_t dataword; - - dataCfg->rx_cnt = 0; - dataCfg->tx_cnt = 0; - dataCfg->status = 0; - - - /* Clear all remaining data in RX FIFO */ - while (SSPx->SR & SSP_SR_RNE){ - tmp = (uint32_t) SSP_ReceiveData(SSPx); - } - - // Clear status - SSPx->ICR = SSP_ICR_BITMASK; - if(SSP_GetDataSize(SSPx)>SSP_DATABIT_8) - dataword = 1; - else dataword = 0; - - // Polling mode ---------------------------------------------------------------------- - if (xfType == SSP_TRANSFER_POLLING){ - if (dataword == 0){ - rdata8 = (uint8_t *)dataCfg->rx_data; - wdata8 = (uint8_t *)dataCfg->tx_data; - } else { - rdata16 = (uint16_t *)dataCfg->rx_data; - wdata16 = (uint16_t *)dataCfg->tx_data; - } - while ((dataCfg->tx_cnt < dataCfg->length) || (dataCfg->rx_cnt < dataCfg->length)){ - if ((SSPx->SR & SSP_SR_TNF) && (dataCfg->tx_cnt < dataCfg->length)){ - // Write data to buffer - if(dataCfg->tx_data == NULL){ - if (dataword == 0){ - SSP_SendData(SSPx, 0xFF); - dataCfg->tx_cnt++; - } else { - SSP_SendData(SSPx, 0xFFFF); - dataCfg->tx_cnt += 2; - } - } else { - if (dataword == 0){ - SSP_SendData(SSPx, *wdata8); - wdata8++; - dataCfg->tx_cnt++; - } else { - SSP_SendData(SSPx, *wdata16); - wdata16++; - dataCfg->tx_cnt += 2; - } - } - } - - // Check overrun error - if ((stat = SSPx->RIS) & SSP_RIS_ROR){ - // save status and return - dataCfg->status = stat | SSP_STAT_ERROR; - return (-1); - } - - // Check for any data available in RX FIFO - while ((SSPx->SR & SSP_SR_RNE) && (dataCfg->rx_cnt < dataCfg->length)){ - // Read data from SSP data - tmp = SSP_ReceiveData(SSPx); - - // Store data to destination - if (dataCfg->rx_data != NULL) - { - if (dataword == 0){ - *(rdata8) = (uint8_t) tmp; - rdata8++; - } else { - *(rdata16) = (uint16_t) tmp; - rdata16++; - } - } - // Increase counter - if (dataword == 0){ - dataCfg->rx_cnt++; - } else { - dataCfg->rx_cnt += 2; - } - } - } - - // save status - dataCfg->status = SSP_STAT_DONE; - - if (dataCfg->tx_data != NULL){ - return dataCfg->tx_cnt; - } else if (dataCfg->rx_data != NULL){ - return dataCfg->rx_cnt; - } else { - return (0); - } - } - - // Interrupt mode ---------------------------------------------------------------------- - else if (xfType == SSP_TRANSFER_INTERRUPT){ - - while ((SSPx->SR & SSP_SR_TNF) && (dataCfg->tx_cnt < dataCfg->length)){ - // Write data to buffer - if(dataCfg->tx_data == NULL){ - if (dataword == 0){ - SSP_SendData(SSPx, 0xFF); - dataCfg->tx_cnt++; - } else { - SSP_SendData(SSPx, 0xFFFF); - dataCfg->tx_cnt += 2; - } - } else { - if (dataword == 0){ - SSP_SendData(SSPx, (*(uint8_t *)((uint32_t)dataCfg->tx_data + dataCfg->tx_cnt))); - dataCfg->tx_cnt++; - } else { - SSP_SendData(SSPx, (*(uint16_t *)((uint32_t)dataCfg->tx_data + dataCfg->tx_cnt))); - dataCfg->tx_cnt += 2; - } - } - - // Check error - if ((stat = SSPx->RIS) & SSP_RIS_ROR){ - // save status and return - dataCfg->status = stat | SSP_STAT_ERROR; - return (-1); - } - - // Check for any data available in RX FIFO - while ((SSPx->SR & SSP_SR_RNE) && (dataCfg->rx_cnt < dataCfg->length)){ - // Read data from SSP data - tmp = SSP_ReceiveData(SSPx); - - // Store data to destination - if (dataCfg->rx_data != NULL) - { - if (dataword == 0){ - *(uint8_t *)((uint32_t)dataCfg->rx_data + dataCfg->rx_cnt) = (uint8_t) tmp; - } else { - *(uint16_t *)((uint32_t)dataCfg->rx_data + dataCfg->rx_cnt) = (uint16_t) tmp; - } - } - // Increase counter - if (dataword == 0){ - dataCfg->rx_cnt++; - } else { - dataCfg->rx_cnt += 2; - } - } - } - - // If there more data to sent or receive - if ((dataCfg->rx_cnt < dataCfg->length) || (dataCfg->tx_cnt < dataCfg->length)){ - // Enable all interrupt - SSPx->IMSC = SSP_IMSC_BITMASK; - } else { - // Save status - dataCfg->status = SSP_STAT_DONE; - } - return (0); - } - - return (-1); -} - -/*********************************************************************//** - * @brief Checks whether the specified SSP status flag is set or not - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0: SSP0 peripheral - * - LPC_SSP1: SSP1 peripheral - * @param[in] FlagType Type of flag to check status, should be one - * of following: - * - SSP_STAT_TXFIFO_EMPTY: TX FIFO is empty - * - SSP_STAT_TXFIFO_NOTFULL: TX FIFO is not full - * - SSP_STAT_RXFIFO_NOTEMPTY: RX FIFO is not empty - * - SSP_STAT_RXFIFO_FULL: RX FIFO is full - * - SSP_STAT_BUSY: SSP peripheral is busy - * @return New State of specified SSP status flag - **********************************************************************/ -FlagStatus SSP_GetStatus(LPC_SSP_TypeDef* SSPx, uint32_t FlagType) -{ - return ((SSPx->SR & FlagType) ? SET : RESET); -} - -/*********************************************************************//** - * @brief Enable or disable specified interrupt type in SSP peripheral - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0: SSP0 peripheral - * - LPC_SSP1: SSP1 peripheral - * @param[in] IntType Interrupt type in SSP peripheral, should be: - * - SSP_INTCFG_ROR: Receive Overrun interrupt - * - SSP_INTCFG_RT: Receive Time out interrupt - * - SSP_INTCFG_RX: RX FIFO is at least half full interrupt - * - SSP_INTCFG_TX: TX FIFO is at least half empty interrupt - * @param[in] NewState New State of specified interrupt type, should be: - * - ENABLE: Enable this interrupt type - * - DISABLE: Disable this interrupt type - * @return None - * Note: We can enable/disable multi-interrupt type by OR multi value - **********************************************************************/ -void SSP_IntConfig(LPC_SSP_TypeDef *SSPx, uint32_t IntType, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - SSPx->IMSC |= IntType; - } - else - { - SSPx->IMSC &= (~IntType) & SSP_IMSC_BITMASK; - } -} - -/*********************************************************************//** - * @brief Check whether the specified Raw interrupt status flag is - * set or not - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0: SSP0 peripheral - * - LPC_SSP1: SSP1 peripheral - * @param[in] RawIntType Raw Interrupt Type, should be: - * - SSP_INTSTAT_RAW_ROR: Receive Overrun interrupt - * - SSP_INTSTAT_RAW_RT: Receive Time out interrupt - * - SSP_INTSTAT_RAW_RX: RX FIFO is at least half full interrupt - * - SSP_INTSTAT_RAW_TX: TX FIFO is at least half empty interrupt - * @return New State of specified Raw interrupt status flag in SSP peripheral - * Note: Enabling/Disabling specified interrupt in SSP peripheral does not - * effect to Raw Interrupt Status flag. - **********************************************************************/ -IntStatus SSP_GetRawIntStatus(LPC_SSP_TypeDef *SSPx, uint32_t RawIntType) -{ - return ((SSPx->RIS & RawIntType) ? SET : RESET); -} - -/*********************************************************************//** - * @brief Get Raw Interrupt Status register - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0: SSP0 peripheral - * - LPC_SSP1: SSP1 peripheral - * @return Raw Interrupt Status (RIS) register value - **********************************************************************/ -uint32_t SSP_GetRawIntStatusReg(LPC_SSP_TypeDef *SSPx) -{ - return (SSPx->RIS); -} - -/*********************************************************************//** - * @brief Check whether the specified interrupt status flag is - * set or not - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0: SSP0 peripheral - * - LPC_SSP1: SSP1 peripheral - * @param[in] IntType Raw Interrupt Type, should be: - * - SSP_INTSTAT_ROR: Receive Overrun interrupt - * - SSP_INTSTAT_RT: Receive Time out interrupt - * - SSP_INTSTAT_RX: RX FIFO is at least half full interrupt - * - SSP_INTSTAT_TX: TX FIFO is at least half empty interrupt - * @return New State of specified interrupt status flag in SSP peripheral - * Note: Enabling/Disabling specified interrupt in SSP peripheral effects - * to Interrupt Status flag. - **********************************************************************/ -IntStatus SSP_GetIntStatus (LPC_SSP_TypeDef *SSPx, uint32_t IntType) -{ - return ((SSPx->MIS & IntType) ? SET :RESET); -} - -/*********************************************************************//** - * @brief Clear specified interrupt pending in SSP peripheral - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0: SSP0 peripheral - * - LPC_SSP1: SSP1 peripheral - * @param[in] IntType Interrupt pending to clear, should be: - * - SSP_INTCLR_ROR: clears the "frame was received when - * RxFIFO was full" interrupt. - * - SSP_INTCLR_RT: clears the "Rx FIFO was not empty and - * has not been read for a timeout period" interrupt. - * @return None - **********************************************************************/ -void SSP_ClearIntPending(LPC_SSP_TypeDef *SSPx, uint32_t IntType) -{ - SSPx->ICR = IntType; -} - -/*********************************************************************//** - * @brief Enable/Disable DMA function for SSP peripheral - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0: SSP0 peripheral - * - LPC_SSP1: SSP1 peripheral - * @param[in] DMAMode Type of DMA, should be: - * - SSP_DMA_TX: DMA for the transmit FIFO - * - SSP_DMA_RX: DMA for the Receive FIFO - * @param[in] NewState New State of DMA function on SSP peripheral, - * should be: - * - ENALBE: Enable this function - * - DISABLE: Disable this function - * @return None - **********************************************************************/ -void SSP_DMACmd(LPC_SSP_TypeDef *SSPx, uint32_t DMAMode, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - SSPx->DMACR |= DMAMode; - } - else - { - SSPx->DMACR &= (~DMAMode) & SSP_DMA_BITMASK; - } -} - -/** - * @} - */ - -#endif /*_SSP*/ -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_systick.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_systick.c deleted file mode 100644 index 66ea6d870aa..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_systick.c +++ /dev/null @@ -1,192 +0,0 @@ -/********************************************************************** -* $Id$ lpc_systick.c 2011-06-02 -*//** -* @file lpc_systick.c -* @brief Contains all functions support for SysTick firmware library -* on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup SYSTICK - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _SYSTICK - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_systick.h" -#include "lpc_clkpwr.h" - - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup SYSTICK_Public_Functions - * @{ - */ -/*********************************************************************//** - * @brief Initial System Tick with using internal CPU clock source - * @param[in] time time interval(ms) - * @return None - * Note: time interval parameter should be less than: - * 1/cclk * (2^24) * 1000 (ms) - * In this case, with cclk = 96Mhz, time interval value < 174ms - **********************************************************************/ -void SYSTICK_InternalInit(uint32_t time) -{ - uint32_t cclk; - float maxtime; - - cclk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_CPU); - - /* With internal CPU clock frequency for LPC178X is 'SystemCoreClock' - * And limit 24 bit for RELOAD value - * So the maximum time can be set: - * 1/SystemCoreClock * (2^24) * 1000 (ms) - */ - //check time value is available or not - maxtime = (1<<24)/(cclk / 1000) ; - - if(time > maxtime) - { - //Error loop - while(1); - } - else - { - //Select CPU clock is System Tick clock source - SysTick->CTRL |= ST_CTRL_CLKSOURCE; - - /* Set RELOAD value - * RELOAD = (SystemCoreClock/1000) * time - 1 - * with time base is millisecond - */ - SysTick->LOAD = (cclk/1000)*time - 1; - } -} - -/*********************************************************************//** - * @brief Initial System Tick with using external clock source - * @param[in] freq external clock frequency(Hz) - * @param[in] time time interval(ms) - * @return None - **********************************************************************/ -void SYSTICK_ExternalInit(uint32_t freq, uint32_t time) -{ - float maxtime; - - /* With external clock frequency for LPC178X is 'freq' - * And limit 24 bit for RELOAD value - * So the maximum time can be set: - * 1/freq * (2^24) * 1000 (ms) - */ - //check time value is available or not - maxtime = (1<<24)/(freq / 1000) ; - if (time>maxtime) - { - //Error Loop - while(1); - } - else - { - //Select external clock is System Tick clock source - SysTick->CTRL &= ~ ST_CTRL_CLKSOURCE; - - /* Set RELOAD value - * RELOAD = (freq/1000) * time - 1 - * with time base is millisecond - */ - maxtime = (freq/1000)*time - 1; - SysTick->LOAD = (freq/1000)*time - 1; - } -} - -/*********************************************************************//** - * @brief Enable/disable System Tick counter - * @param[in] NewState System Tick counter status, should be: - * - ENABLE - * - DISABLE - * @return None - **********************************************************************/ -void SYSTICK_Cmd(FunctionalState NewState) -{ - if(NewState == ENABLE) - //Enable System Tick counter - SysTick->CTRL |= ST_CTRL_ENABLE; - else - //Disable System Tick counter - SysTick->CTRL &= ~ST_CTRL_ENABLE; -} - -/*********************************************************************//** - * @brief Enable/disable System Tick interrupt - * @param[in] NewState System Tick interrupt status, should be: - * - ENABLE - * - DISABLE - * @return None - **********************************************************************/ -void SYSTICK_IntCmd(FunctionalState NewState) -{ - if(NewState == ENABLE) - //Enable System Tick counter - SysTick->CTRL |= ST_CTRL_TICKINT; - else - //Disable System Tick counter - SysTick->CTRL &= ~ST_CTRL_TICKINT; -} - -/*********************************************************************//** - * @brief Get current value of System Tick counter - * @param[in] None - * @return current value of System Tick counter - **********************************************************************/ -uint32_t SYSTICK_GetCurrentValue(void) -{ - return (SysTick->VAL); -} - -/*********************************************************************//** - * @brief Clear Counter flag - * @param[in] None - * @return None - **********************************************************************/ -void SYSTICK_ClearCounterFlag(void) -{ - SysTick->CTRL &= ~ST_CTRL_COUNTFLAG; -} -/** - * @} - */ -#endif /*_SYSTICK*/ -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_timer.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_timer.c deleted file mode 100644 index dee26cc13ce..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_timer.c +++ /dev/null @@ -1,582 +0,0 @@ -/********************************************************************** -* $Id$ lpc_timer.c 2011-06-02 -*//** -* @file lpc_timer.c -* @brief Contains all functions support for Timer firmware library -* on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup TIMER - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _TIM - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_timer.h" -#include "lpc_clkpwr.h" -#include "lpc_pinsel.h" - -/* Private Functions ---------------------------------------------------------- */ - -static uint32_t getPClock (uint32_t timernum); -static uint32_t converUSecToVal (uint32_t timernum, uint32_t usec); -static int32_t converPtrToTimeNum (LPC_TIM_TypeDef *TIMx); - - -/*********************************************************************//** - * @brief Get peripheral clock of each timer controller - * @param[in] timernum Timer number - * @return Peripheral clock of timer - **********************************************************************/ -static uint32_t getPClock (uint32_t timernum) -{ - uint32_t clkdlycnt; - clkdlycnt = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER); - return clkdlycnt; -} - - -/*********************************************************************//** - * @brief Convert a time to a timer count value - * @param[in] timernum Timer number - * @param[in] usec Time in microseconds - * @return The number of required clock ticks to give the time delay - **********************************************************************/ -uint32_t converUSecToVal (uint32_t timernum, uint32_t usec) -{ - uint64_t clkdlycnt; - - // Get Pclock of timer - clkdlycnt = (uint64_t) getPClock(timernum); - - clkdlycnt = (clkdlycnt * usec) / 1000000; - return (uint32_t) clkdlycnt; -} - - -/*********************************************************************//** - * @brief Convert a timer register pointer to a timer number - * @param[in] TIMx Pointer to LPC_TIM_TypeDef, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @return The timer number (0 to 3) or -1 if register pointer is bad - **********************************************************************/ -int32_t converPtrToTimeNum (LPC_TIM_TypeDef *TIMx) -{ - int32_t tnum = -1; - - if (TIMx == LPC_TIM0) - { - tnum = 0; - } - else if (TIMx == LPC_TIM1) - { - tnum = 1; - } - else if (TIMx == LPC_TIM2) - { - tnum = 2; - } - else if (TIMx == LPC_TIM3) - { - tnum = 3; - } - - return tnum; -} - -/* End of Private Functions ---------------------------------------------------- */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup TIM_Public_Functions - * @{ - */ - -/*********************************************************************//** - * @brief Get Interrupt Status - * @param[in] TIMx Timer selection, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @param[in] IntFlag Interrupt type, should be: - * - TIM_MR0_INT: Interrupt for Match channel 0 - * - TIM_MR1_INT: Interrupt for Match channel 1 - * - TIM_MR2_INT: Interrupt for Match channel 2 - * - TIM_MR3_INT: Interrupt for Match channel 3 - * - TIM_CR0_INT: Interrupt for Capture channel 0 - * - TIM_CR1_INT: Interrupt for Capture channel 1 - * @return Flag Status for required interrupt - * - SET : interrupt - * - RESET : no interrupt - **********************************************************************/ -FlagStatus TIM_GetIntStatus(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag) -{ - uint8_t temp; - temp = (TIMx->IR)& TIM_IR_CLR(IntFlag); - if (temp) - return SET; - - return RESET; - -} -/*********************************************************************//** - * @brief Get Capture Interrupt Status - * @param[in] TIMx Timer selection, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @param[in] IntFlag: interrupt type, should be: - * - TIM_MR0_INT: Interrupt for Match channel 0 - * - TIM_MR1_INT: Interrupt for Match channel 1 - * - TIM_MR2_INT: Interrupt for Match channel 2 - * - TIM_MR3_INT: Interrupt for Match channel 3 - * - TIM_CR0_INT: Interrupt for Capture channel 0 - * - TIM_CR1_INT: Interrupt for Capture channel 1 - * @return FlagStatus - * - SET : interrupt - * - RESET : no interrupt - **********************************************************************/ -FlagStatus TIM_GetIntCaptureStatus(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag) -{ - uint8_t temp; - temp = (TIMx->IR) & (1<<(4+IntFlag)); - if(temp) - return SET; - return RESET; -} -/*********************************************************************//** - * @brief Clear Interrupt pending - * @param[in] TIMx Timer selection, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @param[in] IntFlag: interrupt type, should be: - * - TIM_MR0_INT: Interrupt for Match channel 0 - * - TIM_MR1_INT: Interrupt for Match channel 1 - * - TIM_MR2_INT: Interrupt for Match channel 2 - * - TIM_MR3_INT: Interrupt for Match channel 3 - * - TIM_CR0_INT: Interrupt for Capture channel 0 - * - TIM_CR1_INT: Interrupt for Capture channel 1 - * @return None - **********************************************************************/ -void TIM_ClearIntPending(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag) -{ - TIMx->IR = TIM_IR_CLR(IntFlag); -} - -/*********************************************************************//** - * @brief Clear Capture Interrupt pending - * @param[in] TIMx Timer selection, should be - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @param[in] IntFlag interrupt type, should be: - * - TIM_MR0_INT: Interrupt for Match channel 0 - * - TIM_MR1_INT: Interrupt for Match channel 1 - * - TIM_MR2_INT: Interrupt for Match channel 2 - * - TIM_MR3_INT: Interrupt for Match channel 3 - * - TIM_CR0_INT: Interrupt for Capture channel 0 - * - TIM_CR1_INT: Interrupt for Capture channel 1 - * @return None - **********************************************************************/ -void TIM_ClearIntCapturePending(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag) -{ - TIMx->IR = (1<<(4+IntFlag)); -} - -/*********************************************************************//** - * @brief Configuration for Timer at initial time - * @param[in] TimerCounterMode timer counter mode, should be: - * - TIM_TIMER_MODE: Timer mode - * - TIM_COUNTER_RISING_MODE: Counter rising mode - * - TIM_COUNTER_FALLING_MODE: Counter falling mode - * - TIM_COUNTER_ANY_MODE:Counter on both edges - * @param[in] TIM_ConfigStruct pointer to TIM_TIMERCFG_Type or - * TIM_COUNTERCFG_Type - * @return None - **********************************************************************/ -void TIM_ConfigStructInit(TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct) -{ - if (TimerCounterMode == TIM_TIMER_MODE ) - { - TIM_TIMERCFG_Type * pTimeCfg = (TIM_TIMERCFG_Type *)TIM_ConfigStruct; - pTimeCfg->PrescaleOption = TIM_PRESCALE_USVAL; - pTimeCfg->PrescaleValue = 1; - } - else - { - TIM_COUNTERCFG_Type * pCounterCfg = (TIM_COUNTERCFG_Type *)TIM_ConfigStruct; - pCounterCfg->CountInputSelect = TIM_COUNTER_INCAP0; - } -} - -/*********************************************************************//** - * @brief Initial Timer/Counter device - * Set Clock frequency for Timer - * Set initial configuration for Timer - * @param[in] TIMx Timer selection, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @param[in] TimerCounterMode Timer counter mode, should be: - * - TIM_TIMER_MODE: Timer mode - * - TIM_COUNTER_RISING_MODE: Counter rising mode - * - TIM_COUNTER_FALLING_MODE: Counter falling mode - * - TIM_COUNTER_ANY_MODE:Counter on both edges - * @param[in] TIM_ConfigStruct pointer to TIM_TIMERCFG_Type - * that contains the configuration information for the - * specified Timer peripheral. - * @return None - **********************************************************************/ -void TIM_Init(LPC_TIM_TypeDef *TIMx, TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct) -{ - TIM_TIMERCFG_Type *pTimeCfg; - TIM_COUNTERCFG_Type *pCounterCfg; - - //set power - if (TIMx== LPC_TIM0) - { - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM0, ENABLE); - } - else if (TIMx== LPC_TIM1) - { - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM1, ENABLE); - } - - else if (TIMx== LPC_TIM2) - { - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM2, ENABLE); - } - else if (TIMx== LPC_TIM3) - { - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM3, ENABLE); - } - - TIMx->CTCR &= ~TIM_CTCR_MODE_MASK; - TIMx->CTCR |= TIM_TIMER_MODE; - - TIMx->TC =0; - TIMx->PC =0; - TIMx->PR =0; - TIMx->TCR |= (1<<1); //Reset Counter - TIMx->TCR &= ~(1<<1); //release reset - if (TimerCounterMode == TIM_TIMER_MODE ) - { - pTimeCfg = (TIM_TIMERCFG_Type *)TIM_ConfigStruct; - if (pTimeCfg->PrescaleOption == TIM_PRESCALE_TICKVAL) - { - TIMx->PR = pTimeCfg->PrescaleValue -1 ; - } - else - { - TIMx->PR = converUSecToVal (converPtrToTimeNum(TIMx),pTimeCfg->PrescaleValue)-1; - } - } - else - { - - pCounterCfg = (TIM_COUNTERCFG_Type *)TIM_ConfigStruct; - TIMx->CTCR &= ~TIM_CTCR_INPUT_MASK; - if (pCounterCfg->CountInputSelect == TIM_COUNTER_INCAP1) - TIMx->CCR |= _BIT(2); - } - - // Clear interrupt pending - TIMx->IR = 0xFFFFFFFF; - -} - -/*********************************************************************//** - * @brief Close Timer/Counter device - * @param[in] TIMx Pointer to timer device, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @return None - **********************************************************************/ -void TIM_DeInit (LPC_TIM_TypeDef *TIMx) -{ - // Disable timer/counter - TIMx->TCR = 0x00; - - // Disable power - if (TIMx== LPC_TIM0) - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM0, DISABLE); - - else if (TIMx== LPC_TIM1) - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM1, DISABLE); - - else if (TIMx== LPC_TIM2) - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM2, DISABLE); - - else if (TIMx== LPC_TIM3) - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM2, DISABLE); - -} - -/*********************************************************************//** - * @brief Start/Stop Timer/Counter device - * @param[in] TIMx Pointer to timer device, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @param[in] NewState - * - ENABLE : set timer enable - * - DISABLE : disable timer - * @return None - **********************************************************************/ -void TIM_Cmd(LPC_TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - TIMx->TCR |= TIM_ENABLE; - } - else - { - TIMx->TCR &= ~TIM_ENABLE; - } -} - -/*********************************************************************//** - * @brief Reset Timer/Counter device, - * Make TC and PC are synchronously reset on the next - * positive edge of PCLK - * @param[in] TIMx Pointer to timer device, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @return None - **********************************************************************/ -void TIM_ResetCounter(LPC_TIM_TypeDef *TIMx) -{ - TIMx->TCR |= TIM_RESET; - TIMx->TCR &= ~TIM_RESET; -} - -/*********************************************************************//** - * @brief Configuration for Match register - * @param[in] TIMx Pointer to timer device, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @param[in] TIM_MatchConfigStruct Pointer to TIM_MATCHCFG_Type - * - MatchChannel : choose channel 0 or 1 - * - IntOnMatch : if SET, interrupt will be generated when MRxx match - * the value in TC - * - StopOnMatch : if SET, TC and PC will be stopped whenM Rxx match - * the value in TC - * - ResetOnMatch : if SET, Reset on MR0 when MRxx match - * the value in TC - * -ExtMatchOutputType: Select output for external match - * + 0: Do nothing for external output pin if match - * + 1: Force external output pin to low if match - * + 2: Force external output pin to high if match - * + 3: Toggle external output pin if match - * MatchValue: Set the value to be compared with TC value - * @return None - **********************************************************************/ -void TIM_ConfigMatch(LPC_TIM_TypeDef *TIMx, TIM_MATCHCFG_Type *TIM_MatchConfigStruct) -{ - switch(TIM_MatchConfigStruct->MatchChannel) - { - case 0: - TIMx->MR0 = TIM_MatchConfigStruct->MatchValue; - break; - case 1: - TIMx->MR1 = TIM_MatchConfigStruct->MatchValue; - break; - case 2: - TIMx->MR2 = TIM_MatchConfigStruct->MatchValue; - break; - case 3: - TIMx->MR3 = TIM_MatchConfigStruct->MatchValue; - break; - default: - //Error match value - //Error loop - while(1); - } - //interrupt on MRn - TIMx->MCR &= ~ TIM_MCR_CHANNEL_MASKBIT(TIM_MatchConfigStruct->MatchChannel); - - if (TIM_MatchConfigStruct->IntOnMatch) - TIMx->MCR |= TIM_INT_ON_MATCH(TIM_MatchConfigStruct->MatchChannel); - - //reset on MRn - if (TIM_MatchConfigStruct->ResetOnMatch) - TIMx->MCR |= TIM_RESET_ON_MATCH(TIM_MatchConfigStruct->MatchChannel); - - //stop on MRn - if (TIM_MatchConfigStruct->StopOnMatch) - TIMx->MCR |= TIM_STOP_ON_MATCH(TIM_MatchConfigStruct->MatchChannel); - - // match output type - - TIMx->EMR &= ~ TIM_EM_MASK(TIM_MatchConfigStruct->MatchChannel); - TIMx->EMR |= TIM_EM_SET(TIM_MatchConfigStruct->MatchChannel,TIM_MatchConfigStruct->ExtMatchOutputType); -} -/*********************************************************************//** - * @brief Update Match value - * @param[in] TIMx Pointer to timer device, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @param[in] MatchChannel Match channel, should be: 0..3 - * @param[in] MatchValue updated match value - * @return None - **********************************************************************/ -void TIM_UpdateMatchValue(LPC_TIM_TypeDef *TIMx,uint8_t MatchChannel, uint32_t MatchValue) -{ - switch(MatchChannel) - { - case 0: - TIMx->MR0 = MatchValue; - break; - case 1: - TIMx->MR1 = MatchValue; - break; - case 2: - TIMx->MR2 = MatchValue; - break; - case 3: - TIMx->MR3 = MatchValue; - break; - default: - //Error Loop - while(1); - } -} - -/*********************************************************************//** - * @brief Configuration for Capture register - * @param[in] TIMx Pointer to timer device, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @param[in] TIM_CaptureConfigStruct Pointer to TIM_CAPTURECFG_Type - * - CaptureChannel: set the channel to capture data - * - RisingEdge : if SET, Capture at rising edge - * - FallingEdge : if SET, Capture at falling edge - * - IntOnCaption : if SET, Capture generate interrupt - * @return None - **********************************************************************/ -void TIM_ConfigCapture(LPC_TIM_TypeDef *TIMx, TIM_CAPTURECFG_Type *TIM_CaptureConfigStruct) -{ - TIMx->CCR &= ~TIM_CCR_CHANNEL_MASKBIT(TIM_CaptureConfigStruct->CaptureChannel); - - if (TIM_CaptureConfigStruct->RisingEdge) - TIMx->CCR |= TIM_CAP_RISING(TIM_CaptureConfigStruct->CaptureChannel); - - if (TIM_CaptureConfigStruct->FallingEdge) - TIMx->CCR |= TIM_CAP_FALLING(TIM_CaptureConfigStruct->CaptureChannel); - - if (TIM_CaptureConfigStruct->IntOnCaption) - TIMx->CCR |= TIM_INT_ON_CAP(TIM_CaptureConfigStruct->CaptureChannel); -} - -/*********************************************************************//** - * @brief Read value of capture register in timer/counter device - * @param[in] TIMx Pointer to timer/counter device, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @param[in] CaptureChannel: capture channel number, should be: - * - TIM_COUNTER_INCAP0: CAPn.0 input pin for TIMERn - * - TIM_COUNTER_INCAP1: CAPn.1 input pin for TIMERn - * @return Value of capture register - **********************************************************************/ -uint32_t TIM_GetCaptureValue(LPC_TIM_TypeDef *TIMx, TIM_COUNTER_INPUT_OPT CaptureChannel) -{ - if(CaptureChannel==0) - return TIMx->CR0; - else - return TIMx->CR1; -} - -/*---------------Advanced TIMER functions -----------------------------------------*/ -/*********************************************************************//** - * @brief Timer wait (microseconds) - * @param[in] time number of microseconds waiting - * @return None - **********************************************************************/ -void TIM_Waitus(uint32_t time) -{ - TIM_MATCHCFG_Type MatchConfigStruct; - LPC_TIM0->IR = 0xFFFFFFFF; - - MatchConfigStruct.MatchChannel = 0; - MatchConfigStruct.IntOnMatch = ENABLE; - MatchConfigStruct.ResetOnMatch = ENABLE; - MatchConfigStruct.StopOnMatch = ENABLE; - MatchConfigStruct.ExtMatchOutputType = 0; - MatchConfigStruct.MatchValue = time; - - TIM_ConfigMatch(LPC_TIM0, &MatchConfigStruct); - TIM_Cmd(LPC_TIM0,ENABLE); - //wait until interrupt flag occur - while(!(LPC_TIM0->IR & 0x01)); - TIM_ResetCounter(LPC_TIM0); -} -/*********************************************************************//** - * @brief Timer wait (milliseconds) - * @param[in] time number of millisecond waiting - * @return None - **********************************************************************/ -void TIM_Waitms(uint32_t time) -{ - TIM_Waitus(time * 1000); -} -/** - * @} - */ -#endif /*_TIM*/ -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_uart.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_uart.c deleted file mode 100644 index bcd9ef51e08..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_uart.c +++ /dev/null @@ -1,1778 +0,0 @@ -/********************************************************************** -* $Id$ lpc_uart.c 2011-06-02 -*//** -* @file lpc_uart.c -* @brief Contains all functions support for UART firmware library -* on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup UART - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _UART - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_uart.h" -#include "lpc_clkpwr.h" - -/* Private Functions ---------------------------------------------------------- */ - -static Status uart_set_divisors(UART_ID_Type UartID, uint32_t baudrate); -static LPC_UART_TypeDef *uart_get_pointer(UART_ID_Type UartID); - - -/*********************************************************************//** - * @brief Determines best dividers to get a target clock rate - * @param[in] UARTx Pointer to selected UART peripheral, should be: - * - UART_0: UART0 peripheral - * - UART_1: UART1 peripheral - * - UART_2: UART2 peripheral - * - UART_3: UART3 peripheral - * - UART_4: UART4 peripheral - * @param[in] baudrate Desired UART baud rate. - * @return Error status, could be: - * - SUCCESS - * - ERROR - **********************************************************************/ -static Status uart_set_divisors(UART_ID_Type UartID, uint32_t baudrate) -{ - Status errorStatus = ERROR; - - uint32_t uClk; - uint32_t d, m, bestd, bestm, tmp; - uint64_t best_divisor, divisor; - uint32_t current_error, best_error; - uint32_t recalcbaud; - - /* get UART block clock */ - uClk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER); - - /* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers - * The formula is : - * BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL) - * It involves floating point calculations. That's the reason the formulae are adjusted with - * Multiply and divide method.*/ - - /* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions: - * 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */ - best_error = 0xFFFFFFFF; /* Worst case */ - bestd = 0; - bestm = 0; - best_divisor = 0; - - for (m = 1 ; m <= 15 ;m++) - { - for (d = 0 ; d < m ; d++) - { - divisor = ((uint64_t)uClk << 28)*m / (baudrate*(m+d)); - current_error = divisor & 0xFFFFFFFF; - - tmp = divisor>>32; - - /* Adjust error */ - if(current_error > ((uint32_t)1<<31)) - { - current_error = -current_error; - tmp++; - } - - /* Out of range */ - if(tmp < 1 || tmp > 65536) - continue; - - if( current_error < best_error) - { - best_error = current_error; - best_divisor = tmp; - bestd = d; - bestm = m; - - if(best_error == 0) - break; - } - } /* end of inner for loop */ - - if (best_error == 0) - break; - } /* end of outer for loop */ - - /* can not find best match */ - if(best_divisor == 0) - return ERROR; - - recalcbaud = (uClk >> 4) * bestm / (best_divisor * (bestm + bestd)); - - /* reuse best_error to evaluate baud error*/ - if(baudrate > recalcbaud) - best_error = baudrate - recalcbaud; - else - best_error = recalcbaud -baudrate; - - best_error = best_error * 100 / baudrate; - - if (best_error < UART_ACCEPTED_BAUDRATE_ERROR) - { - if (UartID == UART_1) - { - LPC_UART1->LCR |= UART_LCR_DLAB_EN; - - LPC_UART1->DLM = UART_LOAD_DLM(best_divisor); - - LPC_UART1->DLL = UART_LOAD_DLL(best_divisor); - - /* Then reset DLAB bit */ - LPC_UART1->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK; - - LPC_UART1->FDR = (UART_FDR_MULVAL(bestm) - | UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK; - } - else if (UartID == UART_4) - { - LPC_UART4->LCR |= UART_LCR_DLAB_EN; - - LPC_UART4->DLM = UART_LOAD_DLM(best_divisor); - - LPC_UART4->DLL = UART_LOAD_DLL(best_divisor); - - /* Then reset DLAB bit */ - LPC_UART4->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK; - - LPC_UART4->FDR = (UART_FDR_MULVAL(bestm) - | UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK; - } - - else - { - LPC_UART_TypeDef *UARTx = uart_get_pointer(UartID); - UARTx->LCR |= UART_LCR_DLAB_EN; - - UARTx->DLM = UART_LOAD_DLM(best_divisor); - - UARTx->DLL = UART_LOAD_DLL(best_divisor); - - /* Then reset DLAB bit */ - UARTx->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK; - - UARTx->FDR = (UART_FDR_MULVAL(bestm) \ - | UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK; - } - errorStatus = SUCCESS; - } - - return errorStatus; -} -/*********************************************************************//** - * @brief Get the pointer of a given Uart - * @param[in] UARTx Pointer to selected UART peripheral, should be: - * - UART_0: UART0 peripheral - * - UART_1: UART1 peripheral - * - UART_2: UART2 peripheral - * - UART_3: UART3 peripheral - * - UART_4: UART4 peripheral - * @return LPC_UART0~LPC_UART4 - **********************************************************************/ -LPC_UART_TypeDef *uart_get_pointer(UART_ID_Type UartID) -{ - LPC_UART_TypeDef *UARTx = NULL; - switch(UartID) - { - case UART_0: - UARTx = LPC_UART0; - break; - case UART_2: - UARTx = LPC_UART2; - break; - case UART_3: - UARTx = LPC_UART3; - break; - default: - break; - } - return UARTx; -} - -/* End of Private Functions ---------------------------------------------------- */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup UART_Public_Functions - * @{ - */ -/* UART Init/DeInit functions -------------------------------------------------*/ -/********************************************************************//** - * @brief Initializes the UARTx peripheral according to the specified - * parameters in the UART_ConfigStruct. - * @param[in] UARTx UART peripheral selected, should be: - * - UART_0: UART0 peripheral - * - UART_1: UART1 peripheral - * - UART_2: UART2 peripheral - * - UART_3: UART3 peripheral - * - UART_4: UART4 peripheral - * @param[in] UART_ConfigStruct Pointer to a UART_CFG_Type structure -* that contains the configuration information for the -* specified UART peripheral. - * @return None - *********************************************************************/ -void UART_Init(UART_ID_Type UartID, UART_CFG_Type *UART_ConfigStruct) -{ - uint32_t tmp; - switch (UartID) - { - case UART_0: - case UART_2: - case UART_3: - { - LPC_UART_TypeDef *UARTx = uart_get_pointer(UartID); - if(UartID == UART_0) - /* Set up clock and power for UART module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, ENABLE); - else if(UartID == UART_2) - /* Set up clock and power for UART module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, ENABLE); - else if(UartID == UART_3) - /* Set up clock and power for UART module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, ENABLE);; - /* FIFOs are empty */ - UARTx->FCR = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS); - - // Disable FIFO - UARTx->FCR = 0; - - // Dummy reading - while (UARTx->LSR & UART_LSR_RDR) - { - tmp = UARTx->RBR; - } - - UARTx->TER = UART_TER_TXEN; - - // Wait for current transmit complete - while (!(UARTx->LSR & UART_LSR_THRE)); - - // Disable Tx - UARTx->TER = 0; - - // Disable interrupt - UARTx->IER = 0; - - // Set LCR to default state - UARTx->LCR = 0; - - // Set ACR to default state - UARTx->ACR = 0; - - // Set RS485 control to default state - UARTx->RS485CTRL = 0; - - // Set RS485 delay timer to default state - UARTx->RS485DLY = 0; - - // Set RS485 addr match to default state - UARTx->ADRMATCH = 0; - - // Dummy reading - tmp = UARTx->LSR; - } - break; - case UART_1: - { - /* Set up clock and power for UART module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, ENABLE); - - /* FIFOs are empty */ - LPC_UART1->FCR = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS); - - // Disable FIFO - LPC_UART1->FCR = 0; - - // Dummy reading - while (LPC_UART1->LSR & UART_LSR_RDR) - { - tmp = LPC_UART1->RBR; - } - - LPC_UART1->TER = UART_TER_TXEN; - - // Wait for current transmit complete - while (!(LPC_UART1->LSR & UART_LSR_THRE)); - - // Disable Tx - LPC_UART1->TER = 0; - - // Disable interrupt - LPC_UART1->IER = 0; - - // Set LCR to default state - LPC_UART1->LCR = 0; - - // Set ACR to default state - LPC_UART1->ACR = 0; - - // Set RS485 control to default state - LPC_UART1->RS485CTRL = 0; - - // Set RS485 delay timer to default state - LPC_UART1->RS485DLY = 0; - - // Set RS485 addr match to default state - LPC_UART1->ADRMATCH = 0; - - // Dummy reading - tmp = LPC_UART1->LSR; - - // Set Modem Control to default state - LPC_UART1->MCR = 0; - - //Dummy Reading to Clear Status - tmp = LPC_UART1->MSR; - } - break; - case UART_4: - { - /* Set up clock and power for UART module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART4, ENABLE); - - /* FIFOs are empty */ - LPC_UART4->FCR = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS); - - // Disable FIFO - LPC_UART4->FCR = 0; - - // Dummy reading - while (LPC_UART4->LSR & UART_LSR_RDR) - { - tmp = LPC_UART4->RBR; - } - - LPC_UART4->TER = UART4_TER_TXEN; - - // Wait for current transmit complete - while (!(LPC_UART4->LSR & UART_LSR_THRE)); - - // Disable Tx - LPC_UART4->TER = 0; - - // Disable interrupt - LPC_UART4->IER = 0; - - // Set LCR to default state - LPC_UART4->LCR = 0; - - // Set ACR to default state - LPC_UART4->ACR = 0; - - // Set RS485 control to default state - LPC_UART4->RS485CTRL = 0; - - // Set RS485 delay timer to default state - LPC_UART4->RS485DLY = 0; - - // Set RS485 addr match to default state - LPC_UART4->ADRMATCH = 0; - - // Dummy reading - tmp = LPC_UART4->LSR; - - // Set IrDA Mode to default state - LPC_UART4->ICR = 0; - } - break; - } - - // Set Line Control register ---------------------------- - - uart_set_divisors(UartID, (UART_ConfigStruct->Baud_rate)); - - if (UartID == UART_1) - { - tmp = (LPC_UART1->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) \ - & UART_LCR_BITMASK; - } - else if (UartID == UART_4) - { - tmp = (LPC_UART4->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) \ - & UART_LCR_BITMASK; - } - else - { - LPC_UART_TypeDef *UARTx = uart_get_pointer(UartID); - tmp = (UARTx->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) & UART_LCR_BITMASK; - } - - switch (UART_ConfigStruct->Databits) - { - case UART_DATABIT_5: - tmp |= UART_LCR_WLEN5; - break; - - case UART_DATABIT_6: - tmp |= UART_LCR_WLEN6; - break; - - case UART_DATABIT_7: - tmp |= UART_LCR_WLEN7; - break; - - case UART_DATABIT_8: - - default: - tmp |= UART_LCR_WLEN8; - break; - } - - if (UART_ConfigStruct->Parity == UART_PARITY_NONE) - { - // Do nothing... - } - else - { - tmp |= UART_LCR_PARITY_EN; - switch (UART_ConfigStruct->Parity) - { - case UART_PARITY_ODD: - tmp |= UART_LCR_PARITY_ODD; - break; - - case UART_PARITY_EVEN: - tmp |= UART_LCR_PARITY_EVEN; - break; - - case UART_PARITY_SP_1: - tmp |= UART_LCR_PARITY_F_1; - break; - - case UART_PARITY_SP_0: - tmp |= UART_LCR_PARITY_F_0; - break; - - default: - break; - } - } - - switch (UART_ConfigStruct->Stopbits) - { - case UART_STOPBIT_2: - tmp |= UART_LCR_STOPBIT_SEL; - break; - - case UART_STOPBIT_1: - - default: - // Do no thing - break; - } - - - // Write back to LCR, configure FIFO and Disable Tx - if (UartID == UART_1) - { - LPC_UART1->LCR = (uint8_t)(tmp & UART_LCR_BITMASK); - } - else if (UartID == UART_4) - { - LPC_UART4->LCR = (uint8_t)(tmp & UART_LCR_BITMASK); - } - else - { - LPC_UART_TypeDef *UARTx = uart_get_pointer(UartID); - UARTx->LCR = (uint8_t)(tmp & UART_LCR_BITMASK); - } -} - -/*********************************************************************//** - * @brief De-initializes the UARTx peripheral registers to their - * default reset values. - * @param[in] UartID UART peripheral selected, should be: - * - UART_0: UART0 peripheral - * - UART_1: UART1 peripheral - * - UART_2: UART2 peripheral - * - UART_3: UART3 peripheral - * - UART_4: UART4 peripheral - * @return None - **********************************************************************/ -void UART_DeInit(UART_ID_Type UartID) -{ - UART_TxCmd(UartID, DISABLE); - if (UartID == UART_0) - { - /* Set up clock and power for UART module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, DISABLE); - } - - else if (UartID == UART_1) - { - /* Set up clock and power for UART module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, DISABLE); - } - - else if (UartID == UART_2) - { - /* Set up clock and power for UART module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, DISABLE); - } - - else if (UartID == UART_3) - { - /* Set up clock and power for UART module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, DISABLE); - } - else if (UartID == UART_4) - { - /* Set up clock and power for UART module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART4, DISABLE); - } -} - -/*****************************************************************************//** -* @brief Fills each UART_InitStruct member with its default value: -* - 115200 bps -* - 8-bit data -* - 1 Stopbit -* - None Parity -* @param[in] UART_InitStruct Pointer to a UART_CFG_Type structure -* which will be initialized. -* @return None -*******************************************************************************/ -void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct) -{ - UART_InitStruct->Baud_rate = 115200; - - UART_InitStruct->Databits = UART_DATABIT_8; - - UART_InitStruct->Parity = UART_PARITY_NONE; - - UART_InitStruct->Stopbits = UART_STOPBIT_1; -} - -/* UART Send/Recieve functions -------------------------------------------------*/ -/*********************************************************************//** - * @brief Transmit a single data through UART peripheral - * @param[in] UARTx UART peripheral selected, should be: - * - UART_0: UART0 peripheral - * - UART_1: UART1 peripheral - * - UART_2: UART2 peripheral - * - UART_3: UART3 peripheral - * - UART_4: UART4 peripheral - * @param[in] Data Data to transmit (must be 8-bit long) - * @return None - **********************************************************************/ -void UART_SendByte(UART_ID_Type UartID, uint8_t Data) -{ - switch (UartID) - { - case UART_0: - LPC_UART0->THR = Data & UART_THR_MASKBIT; - break; - case UART_1: - LPC_UART1->THR = Data & UART_THR_MASKBIT; - break; - case UART_2: - LPC_UART2->THR = Data & UART_THR_MASKBIT; - break; - case UART_3: - LPC_UART3->THR = Data & UART_THR_MASKBIT; - break; - case UART_4: - LPC_UART4->THR = Data & UART_THR_MASKBIT; - break; - } - -} - - -/*********************************************************************//** - * @brief Receive a single data from UART peripheral - * @param[in] UARTx UART peripheral selected, should be: - * - UART_0: UART0 peripheral - * - UART_1: UART1 peripheral - * - UART_2: UART2 peripheral - * - UART_3: UART3 peripheral - * - UART_4: UART4 peripheral - * @return Data received - **********************************************************************/ -uint8_t UART_ReceiveByte(UART_ID_Type UartID) -{ - switch (UartID) - { - case UART_0: - return (LPC_UART0->RBR & UART_RBR_MASKBIT); - case UART_1: - return (LPC_UART1->RBR & UART_RBR_MASKBIT); - case UART_2: - return (LPC_UART2->RBR & UART_RBR_MASKBIT); - case UART_3: - return (LPC_UART3->RBR & UART_RBR_MASKBIT); - case UART_4: - return (LPC_UART4->RBR & UART_RBR_MASKBIT); - } - return 0x00; -} - -/*********************************************************************//** - * @brief Send a block of data via UART peripheral - * @param[in] UARTx Selected UART peripheral used to send data, should be: - * - UART_0: UART0 peripheral - * - UART_1: UART1 peripheral - * - UART_2: UART2 peripheral - * - UART_3: UART3 peripheral - * - UART_4: UART4 peripheral - * @param[in] txbuf Pointer to Transmit buffer - * @param[in] buflen Length of Transmit buffer - * @param[in] flag Flag used in UART transfer, should be - * NONE_BLOCKING or BLOCKING - * @return Number of bytes sent. - * - * Note: when using UART in BLOCKING mode, a time-out condition is used - * via defined symbol UART_BLOCKING_TIMEOUT. - **********************************************************************/ -uint32_t UART_Send(UART_ID_Type UartID, uint8_t *txbuf, - uint32_t buflen, TRANSFER_BLOCK_Type flag) -{ - uint32_t bToSend, bSent, timeOut, fifo_cnt; - uint8_t *pChar = txbuf; - __IO uint32_t *LSR = NULL; - - switch (UartID) - { - case UART_0: - LSR = (__IO uint32_t *)&LPC_UART0->LSR; - break; - case UART_1: - LSR = (__IO uint32_t *)&LPC_UART1->LSR; - break; - case UART_2: - LSR = (__IO uint32_t *)&LPC_UART2->LSR; - break; - case UART_3: - LSR = (__IO uint32_t *)&LPC_UART3->LSR; - break; - case UART_4: - LSR = (__IO uint32_t *)&LPC_UART4->LSR; - break; - } - - bToSend = buflen; - - // blocking mode - if (flag == BLOCKING) - { - bSent = 0; - while (bToSend) - { - timeOut = UART_BLOCKING_TIMEOUT; - - // Wait for THR empty with timeout - while (!(*LSR & UART_LSR_THRE)) - { - if (timeOut == 0) - break; - - timeOut--; - } - - // Time out! - if(timeOut == 0) - break; - - fifo_cnt = UART_TX_FIFO_SIZE; - - while (fifo_cnt && bToSend) - { - UART_SendByte(UartID, (*pChar++)); - - fifo_cnt--; - - bToSend--; - - bSent++; - } - } - } - - // None blocking mode - else - { - bSent = 0; - while (bToSend) - { - if (bToSend == 0) - break; - - if (!(*LSR & UART_LSR_THRE)) - { - break; - } - - fifo_cnt = UART_TX_FIFO_SIZE; - - while (fifo_cnt && bToSend) - { - UART_SendByte(UartID, (*pChar++)); - - bToSend--; - - fifo_cnt--; - - bSent++; - } - } - } - - return bSent; -} - -/*********************************************************************//** - * @brief Receive a block of data via UART peripheral - * @param[in] UARTx Selected UART peripheral used to send data, - * should be: - * - UART_0: UART0 peripheral - * - UART_1: UART1 peripheral - * - UART_2: UART2 peripheral - * - UART_3: UART3 peripheral - * - UART_4: UART4 peripheral - * @param[out] rxbuf Pointer to Received buffer - * @param[in] buflen Length of Received buffer - * @param[in] flag Flag mode, should be NONE_BLOCKING or BLOCKING - - * @return Number of bytes received - * - * Note: when using UART in BLOCKING mode, a time-out condition is used - * via defined symbol UART_BLOCKING_TIMEOUT. - **********************************************************************/ -uint32_t UART_Receive(UART_ID_Type UartID, uint8_t *rxbuf, - uint32_t buflen, TRANSFER_BLOCK_Type flag) -{ - uint32_t bToRecv, bRecv, timeOut; - uint8_t *pChar = rxbuf; - __IO uint32_t *LSR = NULL; - - switch (UartID) - { - case UART_0: - LSR = (__IO uint32_t *)&LPC_UART0->LSR; - break; - case UART_1: - LSR = (__IO uint32_t *)&LPC_UART1->LSR; - break; - case UART_2: - LSR = (__IO uint32_t *)&LPC_UART2->LSR; - break; - case UART_3: - LSR = (__IO uint32_t *)&LPC_UART3->LSR; - break; - case UART_4: - LSR = (__IO uint32_t *)&LPC_UART4->LSR; - break; - } - - bToRecv = buflen; - - // Blocking mode - if (flag == BLOCKING) - { - bRecv = 0; - while (bToRecv) - { - timeOut = UART_BLOCKING_TIMEOUT; - while (!(*LSR & UART_LSR_RDR)) - { - if (timeOut == 0) - break; - - timeOut--; - } - - // Time out! - if(timeOut == 0) - break; - - // Get data from the buffer - (*pChar++) = UART_ReceiveByte(UartID); - - bToRecv--; - - bRecv++; - } - } - // None blocking mode - else - { - bRecv = 0; - while (bToRecv) - { - if (!(*LSR & UART_LSR_RDR)) - { - break; - } - else - { - (*pChar++) = UART_ReceiveByte(UartID); - - bRecv++; - - bToRecv--; - } - } - } - - return bRecv; -} - -/*********************************************************************//** - * @brief Force BREAK character on UART line, output pin UARTx TXD is - forced to logic 0. - * @param[in] UARTx UART peripheral selected, should be: - * - UART_0: UART0 peripheral - * - UART_1: UART1 peripheral - * - UART_2: UART2 peripheral - * - UART_3: UART3 peripheral - * - UART_4: UART4 peripheral - * @return None - **********************************************************************/ -void UART_ForceBreak(UART_ID_Type UartID) -{ - switch (UartID) - { - case UART_0: - LPC_UART0->LCR |= UART_LCR_BREAK_EN; - break; - case UART_1: - LPC_UART1->LCR |= UART_LCR_BREAK_EN; - break; - case UART_2: - LPC_UART2->LCR |= UART_LCR_BREAK_EN; - break; - case UART_3: - LPC_UART3->LCR |= UART_LCR_BREAK_EN; - break; - case UART_4: - LPC_UART4->LCR |= UART_LCR_BREAK_EN; - break; - } -} - - -/********************************************************************//** - * @brief Enable or disable specified UART interrupt. - * @param[in] UARTx UART peripheral selected, should be - * - UART_0: UART0 peripheral - * - UART_1: UART1 peripheral - * - UART_2: UART2 peripheral - * - UART_3: UART3 peripheral - * - UART_4: UART4 peripheral - * @param[in] UARTIntCfg Specifies the interrupt flag, - * should be one of the following: - - UART_INTCFG_RBR : RBR Interrupt enable - - UART_INTCFG_THRE : THR Interrupt enable - - UART_INTCFG_RLS : RX line status interrupt enable - - UART1_INTCFG_MS : Modem status interrupt enable (UART1 only) - - UART1_INTCFG_CTS : CTS1 signal transition interrupt enable (UART1 only) - - UART_INTCFG_ABEO : Enables the end of auto-baud interrupt - - UART_INTCFG_ABTO : Enables the auto-baud time-out interrupt - * @param[in] NewState New state of specified UART interrupt type, - * should be: - * - ENALBE: Enable this UART interrupt type. -* - DISALBE: Disable this UART interrupt type. - * @return None - *********************************************************************/ -void UART_IntConfig(UART_ID_Type UartID, UART_INT_Type UARTIntCfg, FunctionalState NewState) -{ - uint32_t tmp; - __IO uint32_t *IER = NULL; - uint32_t IERMask = 0; - - switch (UartID) - { - case UART_0: - IER = &LPC_UART0->IER; - IERMask = UART_IER_BITMASK; - break; - case UART_1: - IER = &LPC_UART1->IER; - IERMask = UART1_IER_BITMASK; - break; - case UART_2: - IER = &LPC_UART2->IER; - IERMask = UART_IER_BITMASK; - break; - case UART_3: - IER = &LPC_UART3->IER; - IERMask = UART_IER_BITMASK; - break; - case UART_4: - IER = &LPC_UART4->IER; - IERMask = UART_IER_BITMASK; - break; - } - - - switch(UARTIntCfg) - { - case UART_INTCFG_RBR: - tmp = UART_IER_RBRINT_EN; - break; - - case UART_INTCFG_THRE: - tmp = UART_IER_THREINT_EN; - break; - - case UART_INTCFG_RLS: - tmp = UART_IER_RLSINT_EN; - break; - - case UART_INTCFG_MS: - tmp = UART1_IER_MSINT_EN; - break; - - case UART_INTCFG_CTS: - tmp = UART1_IER_CTSINT_EN; - break; - - case UART_INTCFG_ABEO: - tmp = UART_IER_ABEOINT_EN; - break; - - case UART_INTCFG_ABTO: - tmp = UART_IER_ABTOINT_EN; - break; - } - - if (NewState == ENABLE) - { - *IER |= tmp& IERMask; - } - else - { - *IER &= (~tmp) & IERMask; - } -} - - -/********************************************************************//** - * @brief Get current value of Line Status register in UART peripheral. - * @param[in] UARTx UART peripheral selected, should be: - * - UART_0: UART0 peripheral - * - UART_1: UART1 peripheral - * - UART_2: UART2 peripheral - * - UART_3: UART3 peripheral - * - UART_4: UART4 peripheral - * @return Current value of Line Status register in UART peripheral. - * Note: The return value of this function must be ANDed with each member in - * UART_LS_Type enumeration to determine current flag status - * corresponding to each Line status type. Because some flags in - * Line Status register will be cleared after reading, the next reading - * Line Status register could not be correct. So this function used to - * read Line status register in one time only, then the return value - * used to check all flags. - *********************************************************************/ -uint8_t UART_GetLineStatus(UART_ID_Type UartID) -{ - switch (UartID) - { - case UART_0: - return ((LPC_UART0->LSR) & UART_LSR_BITMASK); - case UART_1: - return ((LPC_UART1->LSR) & UART_LSR_BITMASK); - case UART_2: - return ((LPC_UART2->LSR) & UART_LSR_BITMASK); - case UART_3: - return ((LPC_UART3->LSR) & UART_LSR_BITMASK); - case UART_4: - return ((LPC_UART4->LSR) & UART_LSR_BITMASK); - } - return 0; -} - -/********************************************************************//** - * @brief Get Interrupt Identification value - * @param[in] UARTx UART peripheral selected, should be: - * - UART_0: UART0 peripheral - * - UART_1: UART1 peripheral - * - UART_2: UART2 peripheral - * - UART_3: UART3 peripheral - * - UART_4: UART4 peripheral - * @return Current value of UART UIIR register in UART peripheral. - *********************************************************************/ -uint32_t UART_GetIntId(UART_ID_Type UartID) -{ - switch (UartID) - { - case UART_0: - return ((LPC_UART0->IIR) & UART_IIR_BITMASK); - case UART_1: - return ((LPC_UART1->IIR) & UART_IIR_BITMASK); - case UART_2: - return ((LPC_UART2->IIR) & UART_IIR_BITMASK); - case UART_3: - return ((LPC_UART3->IIR) & UART_IIR_BITMASK); - case UART_4: - return ((LPC_UART4->IIR) & UART_IIR_BITMASK); - } - return 0; -} - -/*********************************************************************//** - * @brief Check whether if UART is busy or not - * @param[in] UARTx UART peripheral selected, should be: - * - UART_0: UART0 peripheral - * - UART_1: UART1 peripheral - * - UART_2: UART2 peripheral - * - UART_3: UART3 peripheral - * - UART_4: UART4 peripheral - * @return RESET if UART is not busy, otherwise return SET. - **********************************************************************/ -FlagStatus UART_CheckBusy(UART_ID_Type UartID) -{ - uint32_t LSR = 0; - switch (UartID) - { - case UART_0: - LSR = (LPC_UART0)->LSR & UART_LSR_TEMT; - break; - case UART_1: - LSR = (LPC_UART1)->LSR & UART_LSR_TEMT; - break; - case UART_2: - LSR = (LPC_UART2)->LSR & UART_LSR_TEMT; - break; - case UART_3: - LSR = (LPC_UART3)->LSR & UART_LSR_TEMT; - break; - case UART_4: - LSR = (LPC_UART4)->LSR & UART_LSR_TEMT; - break; - } - - if (LSR & UART_LSR_TEMT) - { - return RESET; - } - return SET; -} - - -/*********************************************************************//** - * @brief Configure FIFO function on selected UART peripheral - * @param[in] UARTx UART peripheral selected, should be: - * - UART_0: UART0 peripheral - * - UART_1: UART1 peripheral - * - UART_2: UART2 peripheral - * - UART_3: UART3 peripheral - * - UART_4: UART4 peripheral - * @param[in] FIFOCfg Pointer to a UART_FIFO_CFG_Type Structure that - * contains specified information about FIFO configuration - * @return none - **********************************************************************/ -void UART_FIFOConfig(UART_ID_Type UartID, UART_FIFO_CFG_Type *FIFOCfg) -{ - uint8_t tmp = 0; - - tmp |= UART_FCR_FIFO_EN; - - switch (FIFOCfg->FIFO_Level) - { - case UART_FIFO_TRGLEV0: - tmp |= UART_FCR_TRG_LEV0; - break; - - case UART_FIFO_TRGLEV1: - tmp |= UART_FCR_TRG_LEV1; - break; - - case UART_FIFO_TRGLEV2: - tmp |= UART_FCR_TRG_LEV2; - break; - - case UART_FIFO_TRGLEV3: - - default: - tmp |= UART_FCR_TRG_LEV3; - break; - } - - if (FIFOCfg->FIFO_ResetTxBuf == ENABLE) - { - tmp |= UART_FCR_TX_RS; - } - - if (FIFOCfg->FIFO_ResetRxBuf == ENABLE) - { - tmp |= UART_FCR_RX_RS; - } - - if (FIFOCfg->FIFO_DMAMode == ENABLE) - { - tmp |= UART_FCR_DMAMODE_SEL; - } - - - //write to FIFO control register - switch (UartID) - { - case UART_0: - LPC_UART0->FCR = tmp & UART_FCR_BITMASK; - break; - case UART_1: - LPC_UART1->FCR = tmp & UART_FCR_BITMASK; - break; - case UART_2: - LPC_UART2->FCR = tmp & UART_FCR_BITMASK; - break; - case UART_3: - LPC_UART3->FCR = tmp & UART_FCR_BITMASK; - break; - case UART_4: - LPC_UART4->FCR = tmp & UART_FCR_BITMASK; - break; - } -} - -/*****************************************************************************//** -* @brief Fills each UART_FIFOInitStruct member with its default value: -* - FIFO_DMAMode = DISABLE -* - FIFO_Level = UART_FIFO_TRGLEV0 -* - FIFO_ResetRxBuf = ENABLE -* - FIFO_ResetTxBuf = ENABLE -* - FIFO_State = ENABLE -* @param[in] UART_FIFOInitStruct Pointer to a UART_FIFO_CFG_Type structure -* which will be initialized. -* @return None -*******************************************************************************/ -void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct) -{ - UART_FIFOInitStruct->FIFO_DMAMode = DISABLE; - - UART_FIFOInitStruct->FIFO_Level = UART_FIFO_TRGLEV0; - - UART_FIFOInitStruct->FIFO_ResetRxBuf = ENABLE; - - UART_FIFOInitStruct->FIFO_ResetTxBuf = ENABLE; -} - - -/*********************************************************************//** - * @brief Start/Stop Auto Baudrate activity - * @param[in] UARTx UART peripheral selected, should be - * - UART_0: UART0 peripheral - * - UART_1: UART1 peripheral - * - UART_2: UART2 peripheral - * - UART_3: UART3 peripheral - * - UART_4: UART4 peripheral - * @param[in] ABConfigStruct A pointer to UART_AB_CFG_Type structure that - * contains specified information about UART - * auto baudrate configuration - * @param[in] NewState New State of Auto baudrate activity, should be: - * - ENABLE: Start this activity - * - DISABLE: Stop this activity - * Note: Auto-baudrate mode enable bit will be cleared once this mode - * completed. - * @return none - **********************************************************************/ -void UART_ABCmd(UART_ID_Type UartID, UART_AB_CFG_Type *ABConfigStruct, - FunctionalState NewState) -{ - uint32_t tmp; - - tmp = 0; - if (NewState == ENABLE) - { - if (ABConfigStruct->ABMode == UART_AUTOBAUD_MODE1) - { - tmp |= UART_ACR_MODE; - } - if (ABConfigStruct->AutoRestart == ENABLE) - { - tmp |= UART_ACR_AUTO_RESTART; - } - } - - if (UartID == UART_1) - { - if (NewState == ENABLE) - { - // Clear DLL and DLM value - LPC_UART1->LCR |= UART_LCR_DLAB_EN; - - LPC_UART1->DLL = 0; - - LPC_UART1->DLM = 0; - - LPC_UART1->LCR &= ~UART_LCR_DLAB_EN; - - // FDR value must be reset to default value - LPC_UART1->FDR = 0x10; - - LPC_UART1->ACR = UART_ACR_START | tmp; - } - else - { - LPC_UART1->ACR = 0; - } - } - else if (UartID == UART_4) - { - if (NewState == ENABLE) - { - // Clear DLL and DLM value - LPC_UART4->LCR |= UART_LCR_DLAB_EN; - - LPC_UART4->DLL = 0; - - LPC_UART4->DLM = 0; - - LPC_UART4->LCR &= ~UART_LCR_DLAB_EN; - - // FDR value must be reset to default value - LPC_UART4->FDR = 0x10; - - LPC_UART4->ACR = UART_ACR_START | tmp; - } - else - { - LPC_UART4->ACR = 0; - } - } - else - { - LPC_UART_TypeDef *UARTx = uart_get_pointer(UartID); - if (NewState == ENABLE) - { - // Clear DLL and DLM value - UARTx->LCR |= UART_LCR_DLAB_EN; - - UARTx->DLL = 0; - - UARTx->DLM = 0; - - UARTx->LCR &= ~UART_LCR_DLAB_EN; - - // FDR value must be reset to default value - UARTx->FDR = 0x10; - - UARTx->ACR = UART_ACR_START | tmp; - } - else - { - UARTx->ACR = 0; - } - } -} - -/*********************************************************************//** - * @brief Clear Autobaud Interrupt Pending - * @param[in] UARTx UART peripheral selected, should be - * - UART_0: UART0 peripheral - * - UART_1: UART1 peripheral - * - UART_2: UART2 peripheral - * - UART_3: UART3 peripheral - * - UART_4: UART4 peripheral - * @param[in] ABIntType type of auto-baud interrupt, should be: - * - UART_AUTOBAUD_INTSTAT_ABEO: End of Auto-baud interrupt - * - UART_AUTOBAUD_INTSTAT_ABTO: Auto-baud time out interrupt - * @return none - **********************************************************************/ -void UART_ABClearIntPending(UART_ID_Type UartID, UART_ABEO_Type ABIntType) -{ - if (UartID == UART_1) - { - LPC_UART1->ACR |= ABIntType; - } - else if (UartID == UART_4) - { - LPC_UART4->ACR |= ABIntType; - } - else - { - LPC_UART_TypeDef *UARTx = uart_get_pointer(UartID); - UARTx->ACR |= ABIntType; - } -} - -/*********************************************************************//** - * @brief Enable/Disable transmission on UART TxD pin - * @param[in] UARTx UART peripheral selected, should be: - * - UART_0: UART0 peripheral - * - UART_1: UART1 peripheral - * - UART_2: UART2 peripheral - * - UART_3: UART3 peripheral - * - UART_4: UART4 peripheral - * @param[in] NewState New State of Tx transmission function, should be: - * - ENABLE: Enable this function - - DISABLE: Disable this function - * @return none - **********************************************************************/ -void UART_TxCmd(UART_ID_Type UartID, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - if (UartID == UART_1) - { - LPC_UART1->TER |= UART_TER_TXEN; - } - else if (UartID == UART_4) - { - LPC_UART4->TER |= UART4_TER_TXEN; - } - else - { - LPC_UART_TypeDef *UARTx = uart_get_pointer(UartID); - UARTx->TER |= UART_TER_TXEN; - } - } - else - { - if (UartID == UART_1) - { - LPC_UART1->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK; - } - else if (UartID == UART_4) - { - LPC_UART4->TER &= (~UART4_TER_TXEN) & UART4_TER_BITMASK; - } - else - { - LPC_UART_TypeDef *UARTx = uart_get_pointer(UartID); - UARTx->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK; - } - } -} - -/* UART IrDA functions ---------------------------------------------------*/ -/*********************************************************************//** - * @brief Enable or disable inverting serial input function of IrDA - * on UART peripheral. - * @param[in] UARTx UART peripheral selected, should be LPC_UART4 (only) - * @param[in] NewState New state of inverting serial input, should be: - * - ENABLE: Enable this function. - * - DISABLE: Disable this function. - * @return none - **********************************************************************/ -void UART_IrDAInvtInputCmd(UART_ID_Type UartID, FunctionalState NewState) -{ - if (UartID != UART_4) - return; - - if (NewState == ENABLE) - { - LPC_UART4->ICR |= UART_ICR_IRDAINV; - } - else if (NewState == DISABLE) - { - LPC_UART4->ICR &= (~UART_ICR_IRDAINV) & UART_ICR_BITMASK; - } - -} - - -/*********************************************************************//** - * @brief Enable or disable IrDA function on UART peripheral. - * @param[in] UARTx UART peripheral selected, should be LPC_UART4 (only) - * @param[in] NewState New state of IrDA function, should be: - * - ENABLE: Enable this function. - * - DISABLE: Disable this function. - * @return none - **********************************************************************/ -void UART_IrDACmd(UART_ID_Type UartID, FunctionalState NewState) -{ - if (UartID != UART_4) - return; - - if (NewState == ENABLE) - { - LPC_UART4->ICR |= UART_ICR_IRDAEN; - } - else - { - LPC_UART4->ICR &= (~UART_ICR_IRDAEN) & UART_ICR_BITMASK; - } -} - - -/*********************************************************************//** - * @brief Configure Pulse divider for IrDA function on UART peripheral. - * @param[in] UARTx UART peripheral selected, should be LPC_UART4 (only) - * @param[in] PulseDiv Pulse Divider value from Peripheral clock, - * should be one of the following: - - UART_IrDA_PULSEDIV2 : Pulse width = 2 * Tpclk - - UART_IrDA_PULSEDIV4 : Pulse width = 4 * Tpclk - - UART_IrDA_PULSEDIV8 : Pulse width = 8 * Tpclk - - UART_IrDA_PULSEDIV16 : Pulse width = 16 * Tpclk - - UART_IrDA_PULSEDIV32 : Pulse width = 32 * Tpclk - - UART_IrDA_PULSEDIV64 : Pulse width = 64 * Tpclk - - UART_IrDA_PULSEDIV128 : Pulse width = 128 * Tpclk - - UART_IrDA_PULSEDIV256 : Pulse width = 256 * Tpclk - - * @return none - **********************************************************************/ -void UART_IrDAPulseDivConfig(UART_ID_Type UartID, UART_IrDA_PULSE_Type PulseDiv) -{ - uint32_t tmp, tmp1; - - if (UartID != UART_4) - return; - - tmp1 = UART_ICR_PULSEDIV(PulseDiv); - - tmp = LPC_UART4->ICR & (~ UART_ICR_PULSEDIV(7)); - - tmp |= tmp1 | UART_ICR_FIXPULSE_EN; - - LPC_UART4->ICR = tmp & UART_ICR_BITMASK; -} - -/* UART1 FullModem function ---------------------------------------------*/ - -/*********************************************************************//** - * @brief Force pin DTR/RTS corresponding to given state (Full modem mode) - * @param[in] UARTx LPC_UART1 (only) - * @param[in] Pin Pin that NewState will be applied to, should be: - * - UART1_MODEM_PIN_DTR: DTR pin. - * - UART1_MODEM_PIN_RTS: RTS pin. - * @param[in] NewState New State of DTR/RTS pin, should be: - * - INACTIVE: Force the pin to inactive signal. - - ACTIVE: Force the pin to active signal. - * @return none - **********************************************************************/ -void UART_FullModemForcePinState(UART_ID_Type UartID, - UART_MODEM_PIN_Type Pin, - UART1_SignalState NewState) -{ - uint8_t tmp = 0; - if (UartID != UART_1) - return; - switch (Pin) - { - case UART1_MODEM_PIN_DTR: - tmp = UART1_MCR_DTR_CTRL; - break; - - case UART1_MODEM_PIN_RTS: - tmp = UART1_MCR_RTS_CTRL; - break; - - default: - break; - } - - if (NewState == ACTIVE) - { - LPC_UART1->MCR |= tmp; - } - else - { - LPC_UART1->MCR &= (~tmp) & UART1_MCR_BITMASK; - } -} - - -/*********************************************************************//** - * @brief Configure Full Modem mode for UART peripheral - * @param[in] UARTx LPC_UART1 (only) - * @param[in] Mode Full Modem mode, should be: - * - UART1_MODEM_MODE_LOOPBACK: Loop back mode. - * - UART1_MODEM_MODE_AUTO_RTS: Auto-RTS mode. - * - UART1_MODEM_MODE_AUTO_CTS: Auto-CTS mode. - * @param[in] NewState New State of this mode, should be: - * - ENABLE: Enable this mode. - - DISABLE: Disable this mode. - * @return none - **********************************************************************/ -void UART_FullModemConfigMode(UART_ID_Type UartID, UART_MODEM_MODE_Type Mode, - FunctionalState NewState) -{ - uint8_t tmp; - - if(UartID != UART_1) - return; - - switch(Mode) - { - case UART1_MODEM_MODE_LOOPBACK: - tmp = UART1_MCR_LOOPB_EN; - break; - - case UART1_MODEM_MODE_AUTO_RTS: - tmp = UART1_MCR_AUTO_RTS_EN; - break; - - case UART1_MODEM_MODE_AUTO_CTS: - tmp = UART1_MCR_AUTO_CTS_EN; - break; - - default: - break; - } - - if (NewState == ENABLE) - { - LPC_UART1->MCR |= tmp; - } - else - { - LPC_UART1->MCR &= (~tmp) & UART1_MCR_BITMASK; - } -} - - -/*********************************************************************//** - * @brief Get current status of modem status register - * @param[in] UARTx LPC_UART1 (only) - * @return Current value of modem status register - * Note: The return value of this function must be ANDed with each member - * UART_MODEM_STAT_type enumeration to determine current flag status - * corresponding to each modem flag status. Because some flags in - * modem status register will be cleared after reading, the next reading - * modem register could not be correct. So this function used to - * read modem status register in one time only, then the return value - * used to check all flags. - **********************************************************************/ -uint8_t UART_FullModemGetStatus(UART_ID_Type UartID) -{ - if(UartID != UART_1) - return 0; - - return ((LPC_UART1->MSR) & UART1_MSR_BITMASK); -} - - -/* UART RS485 functions --------------------------------------------------------------*/ -/*********************************************************************//** - * @brief Configure UART peripheral in RS485 mode according to the specified -* parameters in the RS485ConfigStruct. - * @param[in] UARTx LPC_UART0 ~LPC_UART4 - * @param[in] RS485ConfigStruct Pointer to a UART1_RS485_CTRLCFG_Type structure -* that contains the configuration information for specified UART -* in RS485 mode. - * @return None - **********************************************************************/ -void UART_RS485Config(UART_ID_Type UartID, UART1_RS485_CTRLCFG_Type *RS485ConfigStruct) -{ - uint32_t tmp; - __IO uint32_t *RS485DLY, *ADRMATCH, *RS485CTRL, *LCR; - - tmp = 0; - if (UartID == UART_1) - { - RS485DLY = (__IO uint32_t *)&LPC_UART1->RS485DLY; - ADRMATCH = (__IO uint32_t *)&LPC_UART1->ADRMATCH; - LCR = (__IO uint32_t *)&LPC_UART1->LCR; - RS485CTRL = (__IO uint32_t *)&LPC_UART1->RS485CTRL; - } - else if (UartID == UART_4) - { - RS485DLY = (__IO uint32_t *)&LPC_UART4->RS485DLY; - ADRMATCH = (__IO uint32_t *)&LPC_UART4->ADRMATCH; - LCR = (__IO uint32_t *)&LPC_UART4->LCR; - RS485CTRL = (__IO uint32_t *)&LPC_UART4->RS485CTRL; - } - else - { - LPC_UART_TypeDef *UARTx = uart_get_pointer(UartID); - RS485DLY = (__IO uint32_t *)&UARTx->RS485DLY; - ADRMATCH = (__IO uint32_t *)&UARTx->ADRMATCH; - LCR = (__IO uint32_t *)&UARTx->LCR; - RS485CTRL = (__IO uint32_t *)&UARTx->RS485CTRL; - } - // If Auto Direction Control is enabled - This function is used in Master mode - if (RS485ConfigStruct->AutoDirCtrl_State == ENABLE) - { - tmp |= UART_RS485CTRL_DCTRL_EN; - - // Set polar - if (RS485ConfigStruct->DirCtrlPol_Level == SET) - { - tmp |= UART_RS485CTRL_OINV_1; - } - - // Set pin according to. This condition is only with UART1. The others are used - // OE pin as default for control the direction of RS485 buffer IC - if ((RS485ConfigStruct->DirCtrlPin == UART_RS485_DIRCTRL_DTR) && - (UartID == UART_1)) - { - tmp |= UART_RS485CTRL_SEL_DTR; - } - - // Fill delay time - *RS485DLY = RS485ConfigStruct->DelayValue & UART_RS485DLY_BITMASK; - } - - // MultiDrop mode is enable - if (RS485ConfigStruct->NormalMultiDropMode_State == ENABLE) - { - tmp |= UART_RS485CTRL_NMM_EN; - } - - // Auto Address Detect function - if (RS485ConfigStruct->AutoAddrDetect_State == ENABLE) - { - tmp |= UART_RS485CTRL_AADEN; - - // Fill Match Address - *ADRMATCH = RS485ConfigStruct->MatchAddrValue & UART_RS485ADRMATCH_BITMASK; - } - - // Receiver is disable - if (RS485ConfigStruct->Rx_State == DISABLE) - { - tmp |= UART_RS485CTRL_RX_DIS; - } - - // write back to RS485 control register - *RS485CTRL = tmp & UART_RS485CTRL_BITMASK; - - // Enable Parity function and leave parity in stick '0' parity as default - *LCR |= (UART_LCR_PARITY_F_0 | UART_LCR_PARITY_EN); -} - -/*********************************************************************//** - * @brief Enable/Disable receiver in RS485 module in UART1 - * @param[in] UARTx LPC_UART1 (only) - * @param[in] NewState New State of command, should be: - * - ENABLE: Enable this function. - * - DISABLE: Disable this function. - * @return None - **********************************************************************/ -void UART_RS485ReceiverCmd(UART_ID_Type UartID, FunctionalState NewState) -{ - __IO uint32_t *RS485CTRL; - if (UartID == UART_1) - { - RS485CTRL = (__IO uint32_t *)&LPC_UART1->RS485DLY; - } - else if (UartID == UART_4) - { - RS485CTRL = (__IO uint32_t *)&LPC_UART4->RS485DLY; - } - else - { - LPC_UART_TypeDef *UARTx = uart_get_pointer(UartID); - RS485CTRL = (__IO uint32_t *)&UARTx->RS485DLY; - } - if (NewState == ENABLE) - { - *RS485CTRL &= ~UART_RS485CTRL_RX_DIS; - } - else - { - *RS485CTRL |= UART_RS485CTRL_RX_DIS; - } -} - -/*********************************************************************//** - * @brief Send data on RS485 bus with specified parity stick value (9-bit mode). - * @param[in] UARTx LPC_UART1 (only) - * @param[in] pDatFrm Pointer to data frame. - * @param[in] size Size of data. - * @param[in] ParityStick Parity Stick value, should be 0 or 1. - * @return None - **********************************************************************/ -uint32_t UART_RS485Send(UART_ID_Type UartID, uint8_t *pDatFrm, - uint32_t size, uint8_t ParityStick) -{ - uint8_t tmp, save; - uint32_t cnt; - __IO uint32_t *LCR, *LSR; - if (UartID == UART_1) - { - LCR = (__IO uint32_t *)&LPC_UART1->LCR; - LSR = (__IO uint32_t *)&LPC_UART1->LSR; - } - else if (UartID == UART_4) - { - LCR = (__IO uint32_t *)&LPC_UART4->LCR; - LSR = (__IO uint32_t *)&LPC_UART4->LSR; - } - else - { - LPC_UART_TypeDef *UARTx = uart_get_pointer(UartID); - LCR = (__IO uint32_t *)&UARTx->LCR; - LSR = (__IO uint32_t *)&UARTx->LSR; - } - - if (ParityStick) - { - save = tmp = *LCR & UART_LCR_BITMASK; - - tmp &= ~(UART_LCR_PARITY_EVEN); - - *LCR = tmp; - - cnt = UART_Send(UartID, pDatFrm, size, BLOCKING); - - while (!(*LSR & UART_LSR_TEMT)); - - *LCR = save; - } - else - { - cnt = UART_Send(UartID, pDatFrm, size, BLOCKING); - - while (!(*LSR & UART_LSR_TEMT)); - } - - return cnt; -} - -/*********************************************************************//** - * @brief Send Slave address frames on RS485 bus. - * @param[in] UARTx LPC_UART1 (only) - * @param[in] SlvAddr Slave Address. - * @return None - **********************************************************************/ -void UART_RS485SendSlvAddr(UART_ID_Type UartID, uint8_t SlvAddr) -{ - UART_RS485Send(UartID, &SlvAddr, 1, 1); -} - -/*********************************************************************//** - * @brief Send Data frames on RS485 bus. - * @param[in] UARTx LPC_UART1 (only) - * @param[in] pData Pointer to data to be sent. - * @param[in] size Size of data frame to be sent. - * @return None - **********************************************************************/ -uint32_t UART_RS485SendData(UART_ID_Type UartID, uint8_t *pData, uint32_t size) -{ - return (UART_RS485Send(UartID, pData, size, 0)); -} - -/** - * @} - */ -#endif /*_UART*/ -/** - * @} - */ -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_wwdt.c b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_wwdt.c deleted file mode 100644 index b4ca9465fca..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_wwdt.c +++ /dev/null @@ -1,484 +0,0 @@ -/********************************************************************** -* $Id$ lpc_wwdt.c 2011-06-02 -*//** -* @file lpc_wwdt.c -* @brief Contains all functions support for Wachtdog Timer -* firmware library on LPC -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup WWDT - * @{ - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc_libcfg.h" -#else -#include "lpc_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ -#ifdef _WDT - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_wwdt.h" -#include "lpc_clkpwr.h" -#include "lpc_pinsel.h" - - - /* Public Functions ----------------------------------------------------------- */ - /** @addtogroup WDT_Public_Functions - * @{ - */ - - /********************************************************************//** - * @brief Set timeout value to Timer Constant register - * (if enable) to generate a WatchDog event if match - * - * @param[in] timeoutVal The value (counter) will write directly to - * Register w/o pre-calc - * - * @return None - *********************************************************************/ -int8_t WWDT_SetTimeOutRaw(uint32_t timeoutVal) -{ - int8_t retval = 0; - - if(timeoutVal < WWDT_TIMEOUT_MIN) - { - timeoutVal = WWDT_TIMEOUT_MIN; - retval = WWDT_FUNC_BAD_PARAM; - } - else if (timeoutVal > WWDT_TIMEOUT_MAX) - { - timeoutVal = WWDT_TIMEOUT_MAX; - retval = WWDT_FUNC_BAD_PARAM; - } - - LPC_WDT->TC = timeoutVal; - - return retval; -} - - -/********************************************************************//** - * @brief Set WDT timeout (cal by usec) to TC register - * - * @param[in] timeout The time (usec) to generate watchdog event if - * the watchdog counter reach this value - * - * @return WWDT_FUNC_OK if success - *********************************************************************/ -int8_t WWDT_SetTimeOut(uint32_t timeout) -{ - return WWDT_SetTimeOutRaw(WDT_GET_FROM_USEC(timeout)); -} - - -/*********************************************************************//** -* @brief Initial for Watchdog function by setting timeout -* -* @param[in] TimeOut time out value, should be in range: -* 2048 .. 134217728 -* -* @return WWDT_FUNC_OK if success - **********************************************************************/ -int8_t WWDT_Init(uint32_t TimeOut) -{ - return WWDT_SetTimeOut(TimeOut); -} - -/*********************************************************************//** - * @brief Configure the WatchDog by initialization all the timing - * value for register (Warning value, Window value,...) - * - * @param wdtCfg a the st_Wdt_Config type value - * - * @return None - **********************************************************************/ -void WWDT_Configure(st_Wdt_Config wdtCfg) -{ - WWDT_SetTimeOut(wdtCfg.wdtTmrConst); - - if(wdtCfg.wdtEnable) - { - LPC_WDT->MOD |= WWDT_WDMOD_WDEN; - } - else - { - LPC_WDT->MOD &= ~WWDT_WDMOD_WDEN; - } - - if(wdtCfg.wdtReset) - { - LPC_WDT->MOD |= WWDT_WDMOD_WDRESET; - } - else - { - LPC_WDT->MOD &= ~WWDT_WDMOD_WDRESET; - } - - if(wdtCfg.wdtProtect) - { - LPC_WDT->MOD |= WWDT_WDMOD_WDPROTECT; - } - else - { - LPC_WDT->MOD &= ~WWDT_WDMOD_WDPROTECT; - } - - WWDT_SetWarning(wdtCfg.wdtWarningVal); - - WWDT_SetWindow(wdtCfg.wdtWindowVal); -} - -/*********************************************************************//** - * @brief Start WatchDog with specific Timeout - * - * @param TimeOut specific Timeout for WatchDog event - * - * @return WWDT_FUNC_OK if success - **********************************************************************/ -int8_t WWDT_Start(uint32_t TimeOut) -{ - int8_t retval = WWDT_FUNC_OK; - - retval = WWDT_SetTimeOut(TimeOut); - - WWDT_Cmd(ENABLE); - - return retval; -} - - -/********************************************************************//** - * @brief Update WDT timeout value and feed - * - * @param[in] WarnTime time to generate watchdog warning interrupt(us) - * should be in range: 2048 .. 134217728 - * - * @return None - *********************************************************************/ -void WWDT_SetTimerConstant(uint32_t constVal) -{ - LPC_WDT->TC = constVal; -} - - -/*********************************************************************//** - * @brief Enable/Disable WDT function - * - * @param[in] Mode WWDT mode that will be enabled/disabled, should be: - * - WWDT_PROTECT_MODE : protect mode - * - WWDT_RESET_MODE : reset mode - * - * @param[in] NewState new state of protection function, should be: - * - ENABLE: The watchdog reload value can be changed at any time - * - DISABLE: The watchdog reload value can be changed only after - * the counter is below the value of WDWARNINT and WDWINDOW - * - * @return None - **********************************************************************/ -void WWDT_SetMode(uint8_t mode, FunctionalState NewState) -{ - if (mode == WWDT_PROTECT_MODE ) - { - if(NewState == ENABLE) - LPC_WDT->MOD |= WWDT_WDMOD_WDPROTECT; - else - LPC_WDT->MOD &= ~WWDT_WDMOD_WDPROTECT; - } - else if(mode == WWDT_RESET_MODE) - { - if(NewState == ENABLE) - LPC_WDT->MOD |= WWDT_WDMOD_WDRESET; - else - LPC_WDT->MOD &= ~WWDT_WDMOD_WDRESET; - } -} - -/*********************************************************************//** - * @brief Enable/Disable WWDT activity - * - * @param[in] NewState To enable/disable the WatchDog - * - * @return None - **********************************************************************/ -void WWDT_Enable(FunctionalState NewState) -{ - if(NewState == ENABLE) - { - LPC_WDT->MOD |= WWDT_WDMOD_WDEN; - } - else - { - LPC_WDT->MOD &= ~WWDT_WDMOD_WDEN; - } -} - -/*********************************************************************//** - * @brief Enable/Disable WWDT activity. In case of Enable, it will - * do feeding WatchDog for its normal operation. - * - * @param[in] NewState To enable/disable the WatchDog - * - * @return None - **********************************************************************/ -void WWDT_Cmd(FunctionalState NewState) -{ - if(NewState == ENABLE) - { - LPC_WDT->MOD |= WWDT_WDMOD_WDEN; - - //Load the Feed register to start using WDT - WWDT_Feed(); - } - else - { - LPC_WDT->MOD &= ~WWDT_WDMOD_WDEN; - } -} - -/********************************************************************//** - * @brief Set the warning value to register to generate interrupt - * (if enable) if the watchdog timer matches this value. - * - * @param[in] warnVal The value (counter) will write directly to Warning - * Register w/o pre-calc - * - * @return WWDT_FUNC_OK if success - *********************************************************************/ -int8_t WWDT_SetWarningRaw(uint32_t warnVal) -{ - int8_t retval = WWDT_FUNC_OK; - - if(warnVal < WWDT_WARNINT_MIN) - { - warnVal = WWDT_WARNINT_MIN; - retval = WWDT_FUNC_BAD_PARAM; - } - else if (warnVal > WWDT_WARNINT_MAX) - { - warnVal = WWDT_WARNINT_MAX; - retval = WWDT_FUNC_BAD_PARAM; - } - - LPC_WDT->WARNINT = warnVal; - - return retval; -} - -/********************************************************************//** - * @brief Update WDT warning time (cal by usec) to warning register - * - * @param[in] WarnTime The time (usec) to generate watchdog warning - * interrupt should be in range: 2048 .. 8192 - * - * @return WWDT_FUNC_OK if success - *********************************************************************/ -int8_t WWDT_SetWarning(uint32_t WarnTime) -{ - return WWDT_SetWarningRaw(WDT_GET_FROM_USEC(WarnTime)); -} - - -/********************************************************************//** - * @brief Update WDT Windows value (by counter) to Window Register - * of WatchDog - * - * @param[in] wndVal The value (counter) will write directly to Window - * Register w/o pre-calc - * - * @return WWDT_FUNC_OK if success - *********************************************************************/ -int8_t WWDT_SetWindowRaw(uint32_t wndVal) -{ - int8_t retval = WWDT_FUNC_OK; - - if(wndVal < WWDT_WINDOW_MIN) - { - wndVal = WWDT_WINDOW_MIN; - retval = WWDT_FUNC_BAD_PARAM; - } - else if (wndVal > WWDT_WINDOW_MAX) - { - wndVal = WWDT_WINDOW_MAX; - retval = WWDT_FUNC_BAD_PARAM; - } - - LPC_WDT->WINDOW = wndVal; - - return retval; -} - - -/********************************************************************//** - * @brief Update WDT Windows value (by usec) to Window Register - * of WatchDog - * - * @param[in] WindowedTime Expected time (usec) to set watchdog window event - * - * @return WWDT_FUNC_OK if success - *********************************************************************/ -int8_t WWDT_SetWindow(uint32_t WindowedTime) -{ - return WWDT_SetWindowRaw(WDT_GET_FROM_USEC(WindowedTime)); -} - - -/********************************************************************//** - * @brief Update WDT timeout value for WatchDog event(s) - * - * @param[in] TimeOut Time Out value (usec) to be updated, should be - * in range: 2048 .. 134217728 - * - * @return None - *********************************************************************/ -void WDT_UpdateTimeOut(uint32_t TimeOut) -{ - /* check WDPROTECT, - * if it is enable, wait until the counter is below the value of - * WDWARNINT and WDWINDOW - */ - if(LPC_WDT->MOD & (1<<4)) - { - while((LPC_WDT->TV <(LPC_WDT->WARNINT & WWDT_WDWARNINT_MASK))\ - &&(LPC_WDT->TV <(LPC_WDT->WINDOW & WWDT_WDTC_MASK))); - } - - WWDT_SetTimeOut(TimeOut); -} - - -/********************************************************************//** - * @brief Read WWDT status flag - * - * @param[in] Status kind of status flag that you want to get, should be: - * - WWDT_WARNINT_FLAG: watchdog interrupt flag - * - WWDT_TIMEOUT_FLAG: watchdog time-out flag - * - * @return Time out flag status of WDT - *********************************************************************/ -FlagStatus WWDT_GetStatus (uint8_t Status) -{ - if(Status == WWDT_WARNINT_FLAG) - { - return ((FlagStatus)(LPC_WDT->MOD & (1<<3))); - } - else if (Status == WWDT_TIMEOUT_FLAG) - { - return ((FlagStatus)(LPC_WDT->MOD & (1<<2))); - } - return RESET; -} - -/********************************************************************//** - * @brief Clear WWDT status flag - * - * @param[in] Status kind of status flag that you want to get, should be: - * - WWDT_WARNINT_FLAG: watchdog interrupt flag - * - WWDT_TIMEOUT_FLAG: watchdog time-out flag - * - * @return None - *********************************************************************/ -void WWDT_ClearStatusFlag (uint8_t flag) -{ - if(flag == WWDT_WARNINT_FLAG) - { - // Write 1 to this bit to clear itself - LPC_WDT->MOD |= WWDT_WDMOD_WDINT; - } - else if(flag == WWDT_TIMEOUT_FLAG) - { - // Write 0 to this bit to clear itself - LPC_WDT->MOD &= ~ WWDT_WDMOD_WDTOF; - } -} - -/********************************************************************//** - * @brief Clear WDT Time out flag - * @param None - * @return None - *********************************************************************/ -void WWDT_ClrTimeOutFlag (void) -{ - LPC_WDT->MOD &= ~ WWDT_WDMOD_WDTOF; -} - - -/********************************************************************//** - * @brief Following the standard sequence to Feed the WatchDog Timer - * - * @param None - * - * @return None - *********************************************************************/ -void WWDT_FeedStdSeq (void) -{ - LPC_WDT->FEED = 0xAA; - - LPC_WDT->FEED = 0x55; -} - -/********************************************************************//** - * @brief After set WDTEN, call this function to start Watchdog - * or reload the Watchdog timer - * - * @param None - * - * @return None - *********************************************************************/ -void WWDT_Feed (void) -{ - // Disable irq interrupt - __disable_irq(); - - WWDT_FeedStdSeq(); - - // Then enable irq interrupt - __enable_irq(); -} - -/********************************************************************//** - * @brief Get the current value of WDT - * - * @param None - * - * @return Current value of WDT - *********************************************************************/ -uint32_t WWDT_GetCurrentCount(void) -{ - return LPC_WDT->TV; -} - -/** - * @} - */ - -#endif /*_WDT*/ -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/makefile b/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/makefile deleted file mode 100644 index 75cb107193e..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/makefile +++ /dev/null @@ -1,91 +0,0 @@ -######################################################################## -# $Id:: makefile 814 2008-06-19 19:57:32Z pdurgesh $ -# -# Project: Standard compile makefile -# -# Description: -# Makefile -# -######################################################################## -# Software that is described herein is for illustrative purposes only -# which provides customers with programming information regarding the -# products. This software is supplied "AS IS" without any warranties. -# NXP Semiconductors assumes no responsibility or liability for the -# use of the software, conveys no license or title under any patent, -# copyright, or mask work right to the product. NXP Semiconductors -# reserves the right to make changes in the software without -# notification. NXP Semiconductors also make no representation or -# warranty that such application will be suitable for the specified -# use without further testing or modification. -######################################################################## - -######################################################################## -# -# Get the project root -# -######################################################################## -PROJ_ROOT = $(CURDIR)/../.. - -######################################################################## -# -# Pick up the configuration file in make section -# -######################################################################## -include ../../makesection/makeconfig - -######################################################################## -# -# Pick up the default build rules -# -######################################################################## - -include $(PROJ_ROOT)/makesection/makerule/LPC/make.LPC.$(TOOL) - -######################################################################## -# -# Pick up the assembler and C source files in the directory -# -######################################################################## -include $(PROJ_ROOT)/makesection/makerule/common/make.rules.ftypes -AFLAGS +=-I../include -CFLAGS +=-I../include - - -######################################################################## -# -# Build the library -# -######################################################################## - -$(TARGET_FWLIB_LIB) : .vias $(OBJS) $(FWLIB_LIB_DIR) - $(ECHO) "creating" $(FWLIB) "Firmware support package library" - $(AR) $@ $(OBJS) - -$(FWLIB_LIB_DIR): - $(MKDIR) $(FWLIB_LIB_DIR) - -# delete all targets this Makefile can make -lib_clean: - -@$(RM) $(TARGET_FWLIB_LIB) - -# delete all targets this Makefile can make and all built libraries -# linked in -lib_realclean: - -@$(RM) $(FWLIB_LIB_DIR)/*.a - -@$(RMDIR) $(FWLIB_LIB_DIR) - -clean: lib_clean -realclean: lib_realclean - -######################################################################## -# -# Compile the code base -# -######################################################################## - -include $(PROJ_ROOT)/makesection/makerule/common/make.rules.build - -.PHONY: all lib_clean lib_realclean - - - diff --git a/bsp/nxp/lpc/lpc408x/Libraries/SConscript b/bsp/nxp/lpc/lpc408x/Libraries/SConscript deleted file mode 100644 index 4c815c49b83..00000000000 --- a/bsp/nxp/lpc/lpc408x/Libraries/SConscript +++ /dev/null @@ -1,15 +0,0 @@ -# RT-Thread building script for bridge - -import os -from building import * - -cwd = GetCurrentDir() -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/nxp/lpc/lpc408x/README.md b/bsp/nxp/lpc/lpc408x/README.md index 33ff5c80beb..02be59726cd 100644 --- a/bsp/nxp/lpc/lpc408x/README.md +++ b/bsp/nxp/lpc/lpc408x/README.md @@ -23,6 +23,14 @@ LPC408x æ¿çº§åŒ…æ”¯æŒ MDK4﹑MDK5 å¼€å‘环境和 GCC 编译器，以下是具 | MDK5 | MDK524a | | GCC | GCC 5.4.1 20160919 (release) | +**请注æ„ï¼ï¼ï¼** + +在执行编译工作å‰è¯·å…ˆæ‰“å¼€ENV执行以下指令（该指令用于拉å–å¿…è¦çš„库，å¦åˆ™æ— æ³•é€šè¿‡ç¼–译）： + +```bash +pkgs --update +``` + ## 烧写åŠæ‰§è¡Œ 供电方å¼ï¼šä½¿ç”¨æ–¹å£ USB 连接电脑和开å‘æ¿ã€‚ diff --git a/bsp/nxp/lpc/lpc408x/SConstruct b/bsp/nxp/lpc/lpc408x/SConstruct index d141bb42e9f..e019058ff7c 100644 --- a/bsp/nxp/lpc/lpc408x/SConstruct +++ b/bsp/nxp/lpc/lpc408x/SConstruct @@ -10,6 +10,23 @@ else: sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] from building import * +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "nxp-lpc-series-latest"), + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n==============================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("==============================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread.' + rtconfig.TARGET_EXT DefaultEnvironment(tools=[]) diff --git a/bsp/nxp/lpc/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c b/bsp/nxp/lpc/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c index 3309f50aaf5..77bf19e6322 100644 --- a/bsp/nxp/lpc/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c +++ b/bsp/nxp/lpc/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c @@ -105,7 +105,7 @@ /*---------------------------------------------------------------------------- - * Configure PLL1 + * Configure PLL1 *---------------------------------------------------------------------------- * Integer mode: * - PLL1_DIRECT = 0 (Post divider enabled) @@ -183,7 +183,7 @@ * * Normal operating mode without post-divider and with pre-divider * - PLL0USB_DIRECTI = 0 - * - PLL0USB_DIRECTO = 1 + * - PLL0USB_DIRECTO = 1 * - PLL0USB_BYPASS = 0 * - Output frequency: * FOUT = FIN * 2 * M / N @@ -367,7 +367,7 @@ void SetClock (void) { /*---------------------------------------------------------------------------- PLL0USB Setup *----------------------------------------------------------------------------*/ - + /* Power down PLL0USB */ LPC_CGU->PLL0USB_CTRL |= 1; @@ -385,10 +385,10 @@ void SetClock (void) { x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF); } } - + if (PLL0USB_M < 60) selp = (PLL0USB_M >> 1) + 1; else selp = 31; - + if (PLL0USB_M > 16384) seli = 1; else if (PLL0USB_M > 8192) seli = 2; else if (PLL0USB_M > 2048) seli = 4; @@ -408,13 +408,13 @@ void SetClock (void) { break; case 2: x = 0x00000202; break; - default: + default: for (i = PLL0USB_N; i <= 0x0100; i++) { x =(((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F); } } LPC_CGU->PLL0USB_NP_DIV = (x << 12); - + /* P divider */ x = 0x10; switch (PLL0USB_P) { @@ -428,10 +428,10 @@ void SetClock (void) { for (i = PLL0USB_P; i <= 0x200; i++) { x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) &0x0F); } - } + } LPC_CGU->PLL0USB_NP_DIV |= x; - - LPC_CGU->PLL0USB_CTRL = (PLL0USB_CLK_SEL << 24) | /* Clock source sel */ + + LPC_CGU->PLL0USB_CTRL = (PLL0USB_CLK_SEL << 24) | /* Clock source sel */ (1 << 11) | /* Autoblock En */ (1 << 4 ) | /* PLL0USB clock en */ (PLL0USB_DIRECTO << 3 ) | /* Direct output */ @@ -444,7 +444,7 @@ void SetClock (void) { /*---------------------------------------------------------------------------- Integer divider Setup *----------------------------------------------------------------------------*/ - + /* Configure integer dividers */ LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */ (IDIVA_IDIV << 2) | /* IDIV */ @@ -527,7 +527,7 @@ void SystemInit_ExtMemCtl (void) { LPC_CCU1->CLK_M4_EMC_CFG = (1 << 2) | (1 << 1) | 1; while (!(LPC_CCU1->CLK_M4_EMC_STAT & 1)); - /* Set EMC clock output delay */ + /* Set EMC clock output delay */ if (SystemCoreClock < 80000000UL) { LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_0; /* No EMC clock out delay */ } @@ -595,7 +595,7 @@ void SystemInit_ExtMemCtl (void) { LPC_SCU->SFSPD_4 = EMC_PIN_SET | 2; /* PD_4: D18 */ LPC_SCU->SFSPD_5 = EMC_PIN_SET | 2; /* PD_5: D19 */ LPC_SCU->SFSPD_6 = EMC_PIN_SET | 2; /* PD_6: D20 */ - LPC_SCU->SFSPD_7 = EMC_PIN_SET | 2; /* PD_7: D21 */ + LPC_SCU->SFSPD_7 = EMC_PIN_SET | 2; /* PD_7: D21 */ LPC_SCU->SFSPD_8 = EMC_PIN_SET | 2; /* PD_8: D22 */ LPC_SCU->SFSPD_9 = EMC_PIN_SET | 2; /* PD_9: D23 */ LPC_SCU->SFSPD_10 = EMC_PIN_SET | 2; /* PD_10: BLS3 */ @@ -652,7 +652,7 @@ void SystemInit_ExtMemCtl (void) { LPC_SCU->SFSCLK_1 = EMC_PIN_SET | 0; /* CLK1 */ LPC_SCU->SFSCLK_2 = EMC_PIN_SET | 0; /* CLK2 */ LPC_SCU->SFSCLK_3 = EMC_PIN_SET | 0; /* CLK3 */ - + /* Static memory configuration (chip select 0) */ #if (USE_EXT_STAT_MEM_CS0) LPC_EMC->STATICCONFIG0 = (1 << 7) | /* Byte lane state: use WE signal */ @@ -663,7 +663,7 @@ void SystemInit_ExtMemCtl (void) { LPC_EMC->STATICWAITRD0 = EMC_NANOSEC(90, SystemCoreClock, div); LPC_EMC->STATICCONFIG0 |= (1 << 19) ; /* Enable buffer */ #endif - + /* Dynamic memory configuration (chip select 0) */ #if (USE_EXT_DYN_MEM_CS0) @@ -738,6 +738,7 @@ uint32_t MeasureFreq (uint32_t clk_sel) { /*---------------------------------------------------------------------------- Get PLL1 (divider and multiplier) parameters *----------------------------------------------------------------------------*/ +uint32_t GetPLL1Param (void); __inline uint32_t GetPLL1Param (void) { uint32_t ctrl; uint32_t p; @@ -761,7 +762,7 @@ __inline uint32_t GetPLL1Param (void) { div *= (2*p); } } - return ((div << 8) | (mul)); + return ((div << 8) | (mul)); } @@ -783,7 +784,7 @@ int32_t GetClkSel (uint32_t clk_src) { return ((LPC_CREG->CREG0 & 0x0A) != 0x02) ? (-1) : (CLK_SRC_32KHZ); case CLK_SRC_XTAL: return (LPC_CGU->XTAL_OSC_CTRL & 1) ? (-1) : (CLK_SRC_XTAL); - + case CLK_SRC_PLL0U: reg = LPC_CGU->PLL0USB_CTRL; break; case CLK_SRC_PLL0A: reg = LPC_CGU->PLL0AUDIO_CTRL; break; case CLK_SRC_PLL1: reg = (LPC_CGU->PLL1_STAT & 1) ? (LPC_CGU->PLL1_CTRL) : (0); break; @@ -793,7 +794,7 @@ int32_t GetClkSel (uint32_t clk_src) { case CLK_SRC_IDIVC: reg = LPC_CGU->IDIVC_CTRL; break; case CLK_SRC_IDIVD: reg = LPC_CGU->IDIVD_CTRL; break; case CLK_SRC_IDIVE: reg = LPC_CGU->IDIVE_CTRL; break; - + default: return (clk_sel); } @@ -815,29 +816,29 @@ uint32_t GetClockFreq (uint32_t clk_src) { int32_t clk_sel = clk_src; do { - switch (clk_sel) { - case CLK_SRC_32KHZ: main_freq = CLK_32KHZ; break; + switch (clk_sel) { + case CLK_SRC_32KHZ: main_freq = CLK_32KHZ; break; case CLK_SRC_IRC: main_freq = CLK_IRC; break; - case CLK_SRC_ENET_RX: main_freq = CLK_ENET_RX; break; - case CLK_SRC_ENET_TX: main_freq = CLK_ENET_TX; break; - case CLK_SRC_GP_CLKIN: main_freq = CLK_GP_CLKIN; break; + case CLK_SRC_ENET_RX: main_freq = CLK_ENET_RX; break; + case CLK_SRC_ENET_TX: main_freq = CLK_ENET_TX; break; + case CLK_SRC_GP_CLKIN: main_freq = CLK_GP_CLKIN; break; case CLK_SRC_XTAL: main_freq = CLK_XTAL; break; - + case CLK_SRC_IDIVA: div *= ((LPC_CGU->IDIVA_CTRL >> 2) & 0x3) + 1; break; case CLK_SRC_IDIVB: div *= ((LPC_CGU->IDIVB_CTRL >> 2) & 0x3) + 1; break; case CLK_SRC_IDIVC: div *= ((LPC_CGU->IDIVC_CTRL >> 2) & 0x3) + 1; break; case CLK_SRC_IDIVD: div *= ((LPC_CGU->IDIVD_CTRL >> 2) & 0x3) + 1; break; case CLK_SRC_IDIVE: div *= ((LPC_CGU->IDIVE_CTRL >> 2) & 0x3) + 1; break; - + case CLK_SRC_PLL0U: /* Not implemented */ break; case CLK_SRC_PLL0A: /* Not implemented */ break; - + case CLK_SRC_PLL1: tmp = GetPLL1Param (); mul *= (tmp ) & 0xFF; /* PLL input clock multiplier */ div *= (tmp >> 8) & 0xFF; /* PLL input clock divider */ break; - + default: return (0); /* Clock not running or not supported */ } @@ -887,4 +888,4 @@ void SystemInit (void) { /* Update SystemCoreClock variable */ SystemCoreClockUpdate(); -} +} \ No newline at end of file diff --git a/bsp/nxp/lpc/lpc43xx/M0/rtconfig.h b/bsp/nxp/lpc/lpc43xx/M0/rtconfig.h index cccbbf29b28..f21e94fe95d 100644 --- a/bsp/nxp/lpc/lpc43xx/M0/rtconfig.h +++ b/bsp/nxp/lpc/lpc43xx/M0/rtconfig.h @@ -28,6 +28,8 @@ #define RT_USING_OVERFLOW_CHECK // +#define RT_CPUS_NR 1 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 // #define RT_USING_HOOK //
@@ -37,7 +39,6 @@ // #define RT_TIMER_THREAD_STACK_SIZE 512 // -#define RT_TICK_PER_SECOND 100 //
//
@@ -220,7 +221,8 @@ //
#define RT_USING_VBUS - +#define _RT_VBUS_RING_SZ 64 +#define RT_VBUS_GUEST_VIRQ 0 // diff --git a/bsp/nxp/lpc/lpc43xx/M4/SConstruct b/bsp/nxp/lpc/lpc43xx/M4/SConstruct index e8a4baa13cf..87dbbdc386a 100644 --- a/bsp/nxp/lpc/lpc43xx/M4/SConstruct +++ b/bsp/nxp/lpc/lpc43xx/M4/SConstruct @@ -25,11 +25,11 @@ Export('rtconfig') # prepare building environment objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) - +import glob if rtconfig.PLATFORM in ['gcc']: print('build M0 code first') if sys.platform.startswith('linux'): - import glob + ocwd = os.getcwd() os.chdir('../M0') res = os.system('scons') diff --git a/bsp/nxp/lpc/lpc43xx/M4/applications/application.c b/bsp/nxp/lpc/lpc43xx/M4/applications/application.c index 4dd4cfb49f6..eb5b3b19dd4 100644 --- a/bsp/nxp/lpc/lpc43xx/M4/applications/application.c +++ b/bsp/nxp/lpc/lpc43xx/M4/applications/application.c @@ -23,7 +23,7 @@ #endif static const unsigned char _M0_CODE[] rt_section("M0_CODE") = { -#include "M0_CODE.h" +// #include "M0_CODE.h" }; static void _boot_M0(void) diff --git a/bsp/nxp/lpc/lpc43xx/M4/rtconfig.h b/bsp/nxp/lpc/lpc43xx/M4/rtconfig.h index 1ee6b8f433d..632299104cd 100644 --- a/bsp/nxp/lpc/lpc43xx/M4/rtconfig.h +++ b/bsp/nxp/lpc/lpc43xx/M4/rtconfig.h @@ -223,7 +223,11 @@ // #define RT_USING_VBUS -// +#define RT_VBUS_GUEST_VIRQ 0 +#define _RT_VBUS_RING_SZ 64 +// +#define RT_CPUS_NR 1 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 #endif diff --git a/bsp/nxp/lpc/lpc5410x/Kconfig b/bsp/nxp/lpc/lpc5410x/Kconfig index 69e28527717..8d4f6b00460 100644 --- a/bsp/nxp/lpc/lpc5410x/Kconfig +++ b/bsp/nxp/lpc/lpc5410x/Kconfig @@ -12,4 +12,5 @@ osource "$PKGS_DIR/Kconfig" config SOC_LPC5410 bool select ARCH_ARM_CORTEX_M0 + select PKG_USING_NXP_LPC_DRIVER default y diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/arm_common_tables.h b/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/arm_common_tables.h deleted file mode 100644 index 7a59b5923e9..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/arm_common_tables.h +++ /dev/null @@ -1,93 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2013 ARM Limited. All rights reserved. -* -* $Date: 17. January 2013 -* $Revision: V1.4.1 -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -extern const q31_t realCoefAQ31[1024]; -extern const q31_t realCoefBQ31[1024]; -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoefQ31[6144]; -extern const q15_t twiddleCoefQ15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - - -#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) -#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) -#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) -#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/arm_math.h b/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/arm_math.h deleted file mode 100644 index 65304c127d6..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7306 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2013 ARM Limited. All rights reserved. -* -* $Date: 17. January 2013 -* $Revision: V1.4.1 -* -* Project: CMSIS DSP Library -* Title: arm_math.h -* -* Description: Public header file for CMSIS DSP Library -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * - * Examples - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * - * The library has been developed and tested with MDK-ARM version 4.60. - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * - * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM0b_math.uvproj - * - arm_cortexM0l_math.uvproj - * - arm_cortexM3b_math.uvproj - * - arm_cortexM3l_math.uvproj - * - arm_cortexM4b_math.uvproj - * - arm_cortexM4l_math.uvproj - * - arm_cortexM4bf_math.uvproj - * - arm_cortexM4lf_math.uvproj - * - * - * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - * Copyright Notice - * - * Copyright (C) 2010-2013 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined (ARM_MATH_CM4) -#include "core_cm4.h" -#elif defined (ARM_MATH_CM3) -#include "core_cm3.h" -#elif defined (ARM_MATH_CM0) -#include "core_cm0.h" -#define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) -#include "core_cm0plus.h" -#define ARM_MATH_CM0_FAMILY -#else -#include "ARMCM4.h" -#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x800000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined __CC_ARM -#define __SIMD32_TYPE int32_t __packed -#define CMSIS_UNUSED __attribute__((unused)) -#elif defined __ICCARM__ -#define CMSIS_UNUSED -#define __SIMD32_TYPE int32_t __packed -#elif defined __GNUC__ -#define __SIMD32_TYPE int32_t -#define CMSIS_UNUSED __attribute__((unused)) -#else -#error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) - -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) - -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - - -#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) -#define __CLZ __clz -#endif - -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) - - static __INLINE uint32_t __CLZ( - q31_t data); - - - static __INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - - } - -#endif - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - - uint32_t out, tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = __CLZ(in) - 1; - } - else - { - signBits = __CLZ(-in) - 1; - } - - /* Convert input sample to 1.31 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = (uint32_t) (in >> 24u); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (q31_t) (((q63_t) in * out) >> 31u); - tempVal = 0x7FFFFFFF - tempVal; - /* 1.31 with exp 1 */ - //out = (q31_t) (((q63_t) out * tempVal) >> 30u); - out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - - } - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - - uint32_t out = 0, tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = __CLZ(in) - 17; - } - else - { - signBits = __CLZ(-in) - 17; - } - - /* Convert input sample to 1.15 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = in >> 8; - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0; i < 2; i++) - { - tempVal = (q15_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFF - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - - - } - -#endif /* end of ARM_MATH_CM0_FAMILY */ - - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE q31_t __QADD8( - q31_t x, - q31_t y) - { - - q31_t sum; - q7_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((q31_t) (r + s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); - t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); - u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); - - sum = - (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | - (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); - - return sum; - - } - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB8( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((r - s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; - t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; - u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; - - sum = - (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & - 0x000000FF); - - return sum; - } - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE q31_t __QADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r + s, 16); - s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE q31_t __SHADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (s >> 1)); - s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r - s, 16); - s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __SHSUB16( - q31_t x, - q31_t y) - { - - q31_t diff; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (s >> 1)); - s = (((x >> 17) - (y >> 17)) << 16); - - diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return diff; - } - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE q31_t __QASX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE q31_t __SHASX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (y >> 17)); - s = (((x >> 17) + (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE q31_t __QSAX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE q31_t __SHSAX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (y >> 17)); - s = (((x >> 17) - (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMUSDX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((short) x * (short) (y >> 16)) - - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE q31_t __SMUADX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((short) x * (short) (y >> 16)) + - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE q31_t __QADD( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x + y); - } - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE q31_t __QSUB( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x - y); - } - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE q31_t __SMLAD( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE q31_t __SMLADX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMLSDX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum - ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE q63_t __SMLALD( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE q63_t __SMLALDX( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) y)) + - ((short) x * (short) (y >> 16)); - } - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE q31_t __SMUAD( - q31_t x, - q31_t y) - { - - return (((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE q31_t __SMUSD( - q31_t x, - q31_t y) - { - - return (-((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - static __INLINE q31_t __SXTB16( - q31_t x) - { - - return ((((x << 24) >> 24) & 0x0000FFFF) | - (((x << 8) >> 8) & 0xFFFF0000)); - } - - -#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] *S points to an instance of the Q7 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] *S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - * @return none - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] *S points to an instance of the Q15 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] *S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] *S points to an instance of the Q31 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] *S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] *S points to an instance of the floating-point FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] *S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q15; - - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - - - } arm_biquad_casd_df1_inst_f32; - - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q31; - - - - /** - * @brief Floating-point matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q31 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point matrix scaling. - * @param[in] *pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] *pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - /** - * @brief Q15 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#ifdef ARM_MATH_CM0_FAMILY - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] *S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @return none - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @return none - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the q15 PID Control structure - * @return none - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - - - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - - - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q31 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q15 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - /** - * @brief Floating-point vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Dot product of floating-point vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - /** - * @brief Dot product of Q7 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - /** - * @brief Dot product of Q15 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Dot product of Q31 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_f32; - - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the Q15 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - * @return none. - */ - - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - - } arm_lms_instance_q31; - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Correlation of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - /** - * @brief Correlation of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /* - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cos output. - * @return none. - */ - - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCcosVal); - - /* - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cosine output. - * @return none. - */ - - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - - - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#ifndef ARM_MATH_CM0_FAMILY - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD(S->A0, in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = __SMLALD(S->A1, (q31_t) *vstate, acc); - -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; - -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - - /** - * @ingroup groupController - */ - - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - */ - - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = - ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - - } - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - */ - - - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; - - } - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * The function implements the forward Park transform. - * - */ - - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - - } - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - - - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - */ - - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] *pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - - } - - } - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] *pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (y >> 20); - } - - - } - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] *pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - - - static __INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - - if(index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (y >> 20u); - - } - - } - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - - float32_t arm_sin_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q31_t arm_sin_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q15_t arm_sin_q15( - q15_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - - float32_t arm_cos_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q31_t arm_cos_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - - static __INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if(in > 0) - { - -// #if __FPU_USED -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - - - - - /** - * @brief floating-point Circular write function. - */ - - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - /** - * @brief Q15 Circular write function. - */ - - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - /** - * @brief Mean value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Mean value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Floating-point complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - /** - * @brief Q31 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - /** - * @brief Floating-point complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[in] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - * @return none. - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - - - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 - || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - - } - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20u); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20u); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return (acc << 2u); - - } - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return (acc >> 36); - - } - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return (acc >> 40); - - } - - /** - * @} end of BilinearInterpolate group - */ - - -#if defined ( __CC_ARM ) //Keil -//SMMLAR - #define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -//SMMLSR - #define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -//SMMULR - #define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -//Enter low optimization region - place directly above function definition - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - -//Exit low optimization region - place directly after end of function definition - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - -//Enter low optimization region - place directly above function definition - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ICCARM__) //IAR - //SMMLA - #define multAcc_32x32_keep32_R(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - - //SMMLS - #define multSub_32x32_keep32_R(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -//SMMUL - #define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - -//Enter low optimization region - place directly above function definition - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - -//Exit low optimization region - place directly after end of function definition - #define LOW_OPTIMIZATION_EXIT - -//Enter low optimization region - place directly above function definition - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__GNUC__) - //SMMLA - #define multAcc_32x32_keep32_R(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - - //SMMLS - #define multSub_32x32_keep32_R(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -//SMMUL - #define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) - - #define LOW_OPTIMIZATION_EXIT - - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - - - - -#ifdef __cplusplus -} -#endif - - -#endif /* _ARM_MATH_H */ - - -/** - * - * End of file. - */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_cm0.h b/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_cm0.h deleted file mode 100644 index ab31de0ee87..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_cm0.h +++ /dev/null @@ -1,682 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000 - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_cm0plus.h b/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_cm0plus.h deleted file mode 100644 index 5cea74e9af3..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_cm0plus.h +++ /dev/null @@ -1,793 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0P definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ - __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000 - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0 - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1) - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_cm3.h b/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_cm3.h deleted file mode 100644 index 122c9aa4a8f..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_cm3.h +++ /dev/null @@ -1,1627 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_cm4.h b/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_cm4.h deleted file mode 100644 index d65016c7149..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,1772 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_cm4_simd.h b/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_cm4_simd.h deleted file mode 100644 index 83db95b5f11..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_cm4_simd.h +++ /dev/null @@ -1,673 +0,0 @@ -/**************************************************************************//** - * @file core_cm4_simd.h - * @brief CMSIS Cortex-M4 SIMD Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_SIMD_H -#define __CORE_CM4_SIMD_H - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32) ) >> 32)) - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#include - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#include - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLALD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLALDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLSLD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLSLDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -/* not yet supported */ -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CORE_CM4_SIMD_H */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_cmFunc.h b/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_cmFunc.h deleted file mode 100644 index 0a18fafc301..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_cmFunc.h +++ /dev/null @@ -1,636 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_cmInstr.h b/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_cmInstr.h deleted file mode 100644 index d213f0eed7c..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_cmInstr.h +++ /dev/null @@ -1,688 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.20 - * @date 05. March 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - uint32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32 - op2)); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_sc000.h b/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_sc000.h deleted file mode 100644 index 1a2a0f2e300..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_sc000.h +++ /dev/null @@ -1,813 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup SC000 - @{ - */ - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (0) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000 - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1]; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154]; - __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/* SCB Security Features Register Definitions */ -#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ -#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ - -#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ -#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2]; - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of SC000 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_sc300.h b/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_sc300.h deleted file mode 100644 index cc34d6fc0ee..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/CMSIS/Include/core_sc300.h +++ /dev/null @@ -1,1598 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup SC3000 - @{ - */ - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (300) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000 - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/Device/SConscript b/bsp/nxp/lpc/lpc5410x/Libraries/Device/SConscript deleted file mode 100644 index 3b20d490387..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/Device/SConscript +++ /dev/null @@ -1,22 +0,0 @@ -# RT-Thread building script for component - -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -src = Split(''' -startup/sysinit.c -''') -CPPPATH = [cwd + '/../CMSIS/Include'] -CPPDEFINES = ['CORE_M4'] - - -# add for startup script -if rtconfig.PLATFORM in ['gcc']: - src += ['startup/gcc_startup_lpc5410x.c'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - src += ['startup/keil_startup_lpc5410x.s'] - -group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) - -Return('group') diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/cr_startup_lpc5410x-m0.c b/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/cr_startup_lpc5410x-m0.c deleted file mode 100644 index 0047e0a547d..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/cr_startup_lpc5410x-m0.c +++ /dev/null @@ -1,452 +0,0 @@ -//***************************************************************************** -// LPC5410x M0 Microcontroller Startup code for use with LPCXpresso IDE -// -// Version : 141022 -//***************************************************************************** -// -// Copyright(C) NXP Semiconductors, 2014 -// All rights reserved. -// -// Software that is described herein is for illustrative purposes only -// which provides customers with programming information regarding the -// LPC products. This software is supplied "AS IS" without any warranties of -// any kind, and NXP Semiconductors and its licensor disclaim any and -// all warranties, express or implied, including all implied warranties of -// merchantability, fitness for a particular purpose and non-infringement of -// intellectual property rights. NXP Semiconductors assumes no responsibility -// or liability for the use of the software, conveys no license or rights under any -// patent, copyright, mask work right, or any other intellectual property rights in -// or to any products. NXP Semiconductors reserves the right to make changes -// in the software without notification. NXP Semiconductors also makes no -// representation or warranty that such application will be suitable for the -// specified use without further testing or modification. -// -// Permission to use, copy, modify, and distribute this software and its -// documentation is hereby granted, under NXP Semiconductors' and its -// licensor's relevant copyrights in the software, without fee, provided that it -// is used in conjunction with NXP Semiconductors microcontrollers. This -// copyright, permission, and disclaimer notice must appear in all copies of -// this code. -//***************************************************************************** - -#if defined (__cplusplus) -#ifdef __REDLIB__ -#error Redlib does not support C++ -#else -//***************************************************************************** -// -// The entry point for the C++ library startup -// -//***************************************************************************** -extern "C" { - extern void __libc_init_array(void); -} -#endif -#endif - -#define WEAK __attribute__ ((weak)) -#define ALIAS(f) __attribute__ ((weak, alias (#f))) - -//***************************************************************************** -#if defined (__cplusplus) -extern "C" { -#endif - -//***************************************************************************** -#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN) -// Declaration of external SystemInit function -extern void SystemInit(void); -#endif - -//***************************************************************************** -// -// Forward declaration of the default handlers. These are aliased. -// When the application defines a handler (with the same name), this will -// automatically take precedence over these weak definitions -// -//***************************************************************************** -void ResetISR(void); -#if defined (__MULTICORE_MASTER) -void ResetISR2(void); -#endif -WEAK void NMI_Handler(void); -WEAK void HardFault_Handler(void); -//WEAK void MemManage_Handler(void); -//WEAK void BusFault_Handler(void); -//WEAK void UsageFault_Handler(void); -WEAK void SVC_Handler(void); -//WEAK void DebugMon_Handler(void); -WEAK void PendSV_Handler(void); -WEAK void SysTick_Handler(void); -WEAK void IntDefaultHandler(void); - -//***************************************************************************** -// -// Forward declaration of the specific IRQ handlers. These are aliased -// to the IntDefaultHandler, which is a 'forever' loop. When the application -// defines a handler (with the same name), this will automatically take -// precedence over these weak definitions -// -//***************************************************************************** -// External Interrupts - Available on M0/M4 -void WDT_IRQHandler(void) ALIAS(IntDefaultHandler); -void BOD_IRQHandler(void) ALIAS(IntDefaultHandler); -void Reserved_IRQHandler(void) ALIAS(IntDefaultHandler); -void DMA_IRQHandler(void) ALIAS(IntDefaultHandler); -void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT0_IRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT1_IRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT2_IRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT3_IRQHandler(void) ALIAS(IntDefaultHandler); -void UTICK_IRQHandler(void) ALIAS(IntDefaultHandler); -void MRT_IRQHandler(void) ALIAS(IntDefaultHandler); -void CT32B0_IRQHandler(void) ALIAS(IntDefaultHandler); -void CT32B1_IRQHandler(void) ALIAS(IntDefaultHandler); -void CT32B2_IRQHandler(void) ALIAS(IntDefaultHandler); -void CT32B3_IRQHandler(void) ALIAS(IntDefaultHandler); -void CT32B4_IRQHandler(void) ALIAS(IntDefaultHandler); -void SCT0_IRQHandler(void) ALIAS(IntDefaultHandler); -void UART0_IRQHandler(void) ALIAS(IntDefaultHandler); -void UART1_IRQHandler(void) ALIAS(IntDefaultHandler); -void UART2_IRQHandler(void) ALIAS(IntDefaultHandler); -void UART3_IRQHandler(void) ALIAS(IntDefaultHandler); -void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler); -void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler); -void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler); -void SPI0_IRQHandler(void) ALIAS(IntDefaultHandler); -void SPI1_IRQHandler(void) ALIAS(IntDefaultHandler); -void ADC_SEQA_IRQHandler(void) ALIAS(IntDefaultHandler); -void ADC_SEQB_IRQHandler(void) ALIAS(IntDefaultHandler); -void ADC_THCMP_IRQHandler(void) ALIAS(IntDefaultHandler); -void RTC_IRQHandler(void) ALIAS(IntDefaultHandler); -void MAILBOX_IRQHandler(void) ALIAS(IntDefaultHandler); -// External Interrupts - For M4 only -//void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler); -//void PIN_INT4_IRQHandler(void) ALIAS(IntDefaultHandler); -//void PIN_INT5_IRQHandler(void) ALIAS(IntDefaultHandler); -//void PIN_INT6_IRQHandler(void) ALIAS(IntDefaultHandler); -//void PIN_INT7_IRQHandler(void) ALIAS(IntDefaultHandler); -//void SPI2_IRQHandler(void) ALIAS(IntDefaultHandler); -//void SPI3_IRQHandler(void) ALIAS(IntDefaultHandler); -//void RIT_IRQHandler(void) ALIAS(IntDefaultHandler); -//void Reserved41_IRQHandler(void) ALIAS(IntDefaultHandler); -//void Reserved42_IRQHandler(void) ALIAS(IntDefaultHandler); -//void Reserved43_IRQHandler(void) ALIAS(IntDefaultHandler); -//void Reserved44_IRQHandler(void) ALIAS(IntDefaultHandler); -//***************************************************************************** -// -// The entry point for the application. -// __main() is the entry point for Redlib based applications -// main() is the entry point for Newlib based applications -// -//***************************************************************************** -#if defined (__REDLIB__) -extern void __main(void); -#endif -extern int main(void); -//***************************************************************************** -// -// External declaration for the pointer to the stack top from the Linker Script -// -//***************************************************************************** -extern void _vStackTop(void); - -//***************************************************************************** -#if defined (__cplusplus) -} // extern "C" -#endif -//***************************************************************************** -// -// The vector table. -// This relies on the linker script to place at correct location in memory. -// -//***************************************************************************** -extern void (* const g_pfnVectors[])(void); -__attribute__ ((section(".isr_vector"))) -void (* const g_pfnVectors[])(void) = { - // Core Level - CM0plus - &_vStackTop, // The initial stack pointer - ResetISR, // The reset handler - NMI_Handler, // The NMI handler - HardFault_Handler, // The hard fault handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - SVC_Handler, // SVCall handler - 0, // Reserved - 0, // Reserved - PendSV_Handler, // The PendSV handler - SysTick_Handler, // The SysTick handler - - // External Interrupts - Available on M0/M4 - WDT_IRQHandler, // Watchdog - BOD_IRQHandler, // Brown Out Detect - Reserved_IRQHandler, // Reserved - DMA_IRQHandler, // DMA Controller - GINT0_IRQHandler, // GPIO Group0 Interrupt - PIN_INT0_IRQHandler, // PIO INT0 - PIN_INT1_IRQHandler, // PIO INT1 - PIN_INT2_IRQHandler, // PIO INT2 - PIN_INT3_IRQHandler, // PIO INT3 - UTICK_IRQHandler, // UTICK timer - MRT_IRQHandler, // Multi-Rate Timer - CT32B0_IRQHandler, // Counter Timer 0 - CT32B1_IRQHandler, // Counter Timer 1 - CT32B2_IRQHandler, // Counter Timer 2 - CT32B3_IRQHandler, // Counter Timer 3 - CT32B4_IRQHandler, // Counter Timer 4 - SCT0_IRQHandler, // Smart Counter Timer - UART0_IRQHandler, // UART0 - UART1_IRQHandler, // UART1 - UART2_IRQHandler, // UART2 - UART3_IRQHandler, // UART3 - I2C0_IRQHandler, // I2C0 controller - I2C1_IRQHandler, // I2C1 controller - I2C2_IRQHandler, // I2C2 controller - SPI0_IRQHandler, // SPI0 controller - SPI1_IRQHandler, // SPI1 controller - ADC_SEQA_IRQHandler, // ADC SEQA - ADC_SEQB_IRQHandler, // ADC SEQB - ADC_THCMP_IRQHandler, // ADC THCMP and OVERRUN ORed - RTC_IRQHandler, // RTC Timer - Reserved_IRQHandler, // Reserved - MAILBOX_IRQHandler, // Mailbox - - // External Interrupts - For M4 only -// GINT1_IRQHandler, // GPIO Group1 Interrupt -// PIN_INT4_IRQHandler, // PIO INT4 -// PIN_INT5_IRQHandler, // PIO INT5 -// PIN_INT6_IRQHandler, // PIO INT6 -// PIN_INT7_IRQHandler, // PIO INT7 -// SPI2_IRQHandler, // SPI2 controller -// SPI3_IRQHandler, // SPI3 controller -// 0, // Reserved -// RIT_IRQHandler, // RIT Timer -// Reserved41_IRQHandler, // Reserved -// Reserved42_IRQHandler, // Reserved -// Reserved43_IRQHandler, // Reserved -// Reserved44_IRQHandler, // Reserved - -}; /* End of g_pfnVectors */ - -//***************************************************************************** -// Functions to carry out the initialization of RW and BSS data sections. These -// are written as separate functions rather than being inlined within the -// ResetISR() function in order to cope with MCUs with multiple banks of -// memory. -//***************************************************************************** -__attribute__ ((section(".after_vectors"))) -void data_init(unsigned int romstart, unsigned int start, unsigned int len) { - unsigned int *pulDest = (unsigned int*) start; - unsigned int *pulSrc = (unsigned int*) romstart; - unsigned int loop; - for (loop = 0; loop < len; loop = loop + 4) - *pulDest++ = *pulSrc++; -} - -__attribute__ ((section(".after_vectors"))) -void bss_init(unsigned int start, unsigned int len) { - unsigned int *pulDest = (unsigned int*) start; - unsigned int loop; - for (loop = 0; loop < len; loop = loop + 4) - *pulDest++ = 0; -} - -//***************************************************************************** -// The following symbols are constructs generated by the linker, indicating -// the location of various points in the "Global Section Table". This table is -// created by the linker via the Code Red managed linker script mechanism. It -// contains the load address, execution address and length of each RW data -// section and the execution and length of each BSS (zero initialized) section. -//***************************************************************************** -extern unsigned int __data_section_table; -extern unsigned int __data_section_table_end; -extern unsigned int __bss_section_table; -extern unsigned int __bss_section_table_end; - -//***************************************************************************** -// Reset entry point for your code. -// Sets up a simple runtime environment and initializes the C/C++ -// library. -//***************************************************************************** - -#if defined (__MULTICORE_MASTER) -//#define cpu_ctrl 0x40000300 -//#define coproc_boot 0x40000304 -//#define set coproc_stack 0x40000308 -__attribute__ ((naked, section(".after_vectors.reset"))) -void ResetISR(void) { - asm volatile( - ".syntax unified\t\n" - ".set cpu_ctrl, 0x40000300\t\n" - ".set coproc_boot, 0x40000304\t\n" - ".set coproc_stack, 0x40000308\t\n" - "MOVS R5, #1\t\n" - "LDR R0, =0xE000ED00\t\n" - "LDR R1, [R0]\t\n" // READ CPUID register - "LDR R2,=0x410CC601\t\n" // CM0 R0p1 identifier - "EORS R1,R1,R2\t\n" // XOR to see if we are C0 - "LDR R3, =cpu_ctrl\t\n" // get address of CPU_CTRL - "LDR R1,[R3]\t\n" // read cpu_ctrl reg into R1 - "BEQ.N cm0_boot\t\n" - "cm4_boot:\t\n" - "LDR R0,=coproc_boot\t\n" // coproc boot address - "LDR R0,[R0]\t\n" // get address to branch to - "MOVS R0,R0\t\n" // Check if 0 - "BEQ.N check_master_m4\t\n" // if zero in boot reg, we just branch to real reset - "BX R0\t\n" // otherwise, we branch to boot address - "commonboot:\t\n" - "LDR R0, =ResetISR2\t\n" // Jump to 'real' reset handler - "BX R0\t\n" - "cm0_boot:\t\n" - "LDR R0,=coproc_boot\t\n" // coproc boot address - "LDR R0,[R0]\t\n" // get address to branch to - "MOVS R0,R0\t\n" // Check if 0 - "BEQ.N check_master_m0\t\n" // if zero in boot reg, we just branch to real reset - "LDR R1,=coproc_stack\t\n" // pickup coprocesor stackpointer (from syscon CPSTACK) - "LDR R1,[R1]\t\n" - "MOV SP,R1\t\n" - "BX R0\t\n" // goto boot address - "check_master_m0:\t\n" - "ANDS R1,R1,R5\t\n" // bit test bit0 - "BEQ.N commonboot\t\n" // if we get 0, that means we are masters - "B.N goto_sleep_pending_reset\t\n" // Otherwise, there is no startup vector for slave, so we go to sleep - "check_master_m4:\t\n" - "ANDS R1,R1,R5\t\n" // bit test bit0 - "BNE.N commonboot\t\n" // if we get 1, that means we are masters - "goto_sleep_pending_reset:\t\n" - "MOV SP,R5\t\n" // load 0x1 into SP so that any stacking (eg on NMI) will not cause us to wakeup - // and write to uninitialised Stack area (instead it will LOCK us up before we cause damage) - // this code should only be reached if debugger bypassed ROM or we changed master without giving - // correct start address, the only way out of this is through a debugger change of SP and PC - "sleepo:\t\n" - "WFI\t\n" // go to sleep - "B.N sleepo\t\n" - ".syntax divided\t\n" - ); -} - - -__attribute__ ((section(".after_vectors.reset"))) -void ResetISR2(void) { - -#else -__attribute__ ((section(".after_vectors.reset"))) -void ResetISR(void) { -#endif - - // If this is not the CM0+ core... -#if !defined (CORE_M0PLUS) - // If this is not a slave project... -#if !defined (__MULTICORE_M0SLAVE) && \ - !defined (__MULTICORE_M4SLAVE) - // Optionally enable RAM banks that may be off by default at reset -#if !defined (DONT_ENABLE_DISABLED_RAMBANKS) - volatile unsigned int *SYSCON_SYSAHBCLKCTRL0 = (unsigned int *) 0x400000c0; - // Ensure that SRAM2(4) bit in SYSAHBCLKCTRL0 are set - *SYSCON_SYSAHBCLKCTRL0 |= (1 << 4); -#endif -#endif -#endif - - // - // Copy the data sections from flash to SRAM. - // - unsigned int LoadAddr, ExeAddr, SectionLen; - unsigned int *SectionTableAddr; - - // Load base address of Global Section Table - SectionTableAddr = &__data_section_table; - - // Copy the data sections from flash to SRAM. - while (SectionTableAddr < &__data_section_table_end) { - LoadAddr = *SectionTableAddr++; - ExeAddr = *SectionTableAddr++; - SectionLen = *SectionTableAddr++; - data_init(LoadAddr, ExeAddr, SectionLen); - } - // At this point, SectionTableAddr = &__bss_section_table; - // Zero fill the bss segment - while (SectionTableAddr < &__bss_section_table_end) { - ExeAddr = *SectionTableAddr++; - SectionLen = *SectionTableAddr++; - bss_init(ExeAddr, SectionLen); - } - -#if !defined (__USE_LPCOPEN) -// LPCOpen init code deals with VTOR initialisation - unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; - if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) { - // CMSIS : SCB->VTOR =
- *pSCB_VTOR = (unsigned int) g_pfnVectors; - } -#endif -#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN) - SystemInit(); -#endif - -#if defined (__cplusplus) - // - // Call C++ library initialisation - // - __libc_init_array(); -#endif - -#if defined (__REDLIB__) - // Call the Redlib library, which in turn calls main() - __main(); -#else - main(); -#endif - - // - // main() shouldn't return, but if it does, we'll just enter an infinite loop - // - while (1) { - ; - } -} - -//***************************************************************************** -// Default exception handlers. Override the ones here by defining your own -// handler routines in your application code. -//***************************************************************************** -__attribute__ ((section(".after_vectors"))) -void NMI_Handler(void) -{ while(1) {} -} - -__attribute__ ((section(".after_vectors"))) -void HardFault_Handler(void) -{ while(1) {} -} - -__attribute__ ((section(".after_vectors"))) -void SVC_Handler(void) -{ while(1) {} -} - -__attribute__ ((section(".after_vectors"))) -void PendSV_Handler(void) -{ while(1) {} -} - -__attribute__ ((section(".after_vectors"))) -void SysTick_Handler(void) -{ while(1) {} -} - -//***************************************************************************** -// -// Processor ends up here if an unexpected interrupt occurs or a specific -// handler is not present in the application code. -// -//***************************************************************************** -__attribute__ ((section(".after_vectors"))) -void IntDefaultHandler(void) -{ while(1) {} -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/cr_startup_lpc5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/cr_startup_lpc5410x.c deleted file mode 100644 index dfc9b16b392..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/cr_startup_lpc5410x.c +++ /dev/null @@ -1,482 +0,0 @@ -//***************************************************************************** -// LPC5410x Microcontroller Startup code for use with LPCXpresso IDE -// -// Version : 141022 -//***************************************************************************** -// -// Copyright(C) NXP Semiconductors, 2014 -// All rights reserved. -// -// Software that is described herein is for illustrative purposes only -// which provides customers with programming information regarding the -// LPC products. This software is supplied "AS IS" without any warranties of -// any kind, and NXP Semiconductors and its licensor disclaim any and -// all warranties, express or implied, including all implied warranties of -// merchantability, fitness for a particular purpose and non-infringement of -// intellectual property rights. NXP Semiconductors assumes no responsibility -// or liability for the use of the software, conveys no license or rights under any -// patent, copyright, mask work right, or any other intellectual property rights in -// or to any products. NXP Semiconductors reserves the right to make changes -// in the software without notification. NXP Semiconductors also makes no -// representation or warranty that such application will be suitable for the -// specified use without further testing or modification. -// -// Permission to use, copy, modify, and distribute this software and its -// documentation is hereby granted, under NXP Semiconductors' and its -// licensor's relevant copyrights in the software, without fee, provided that it -// is used in conjunction with NXP Semiconductors microcontrollers. This -// copyright, permission, and disclaimer notice must appear in all copies of -// this code. -//***************************************************************************** - -#if defined (__cplusplus) -#ifdef __REDLIB__ -#error Redlib does not support C++ -#else -//***************************************************************************** -// -// The entry point for the C++ library startup -// -//***************************************************************************** -extern "C" { - extern void __libc_init_array(void); -} -#endif -#endif - -#define WEAK __attribute__ ((weak)) -#define ALIAS(f) __attribute__ ((weak, alias (#f))) - -//***************************************************************************** -#if defined (__cplusplus) -extern "C" { -#endif - -//***************************************************************************** -#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN) -// Declaration of external SystemInit function -extern void SystemInit(void); -#endif - -//***************************************************************************** -// -// Forward declaration of the default handlers. These are aliased. -// When the application defines a handler (with the same name), this will -// automatically take precedence over these weak definitions -// -//***************************************************************************** -void ResetISR(void); -#if defined (__MULTICORE_MASTER) -void ResetISR2(void); -#endif -WEAK void NMI_Handler(void); -WEAK void HardFault_Handler(void); -WEAK void MemManage_Handler(void); -WEAK void BusFault_Handler(void); -WEAK void UsageFault_Handler(void); -WEAK void SVC_Handler(void); -WEAK void DebugMon_Handler(void); -WEAK void PendSV_Handler(void); -WEAK void SysTick_Handler(void); -WEAK void IntDefaultHandler(void); - -//***************************************************************************** -// -// Forward declaration of the specific IRQ handlers. These are aliased -// to the IntDefaultHandler, which is a 'forever' loop. When the application -// defines a handler (with the same name), this will automatically take -// precedence over these weak definitions -// -//***************************************************************************** -// External Interrupts - Available on M0/M4 -void WDT_IRQHandler(void) ALIAS(IntDefaultHandler); -void BOD_IRQHandler(void) ALIAS(IntDefaultHandler); -void Reserved_IRQHandler(void) ALIAS(IntDefaultHandler); -void DMA_IRQHandler(void) ALIAS(IntDefaultHandler); -void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT0_IRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT1_IRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT2_IRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT3_IRQHandler(void) ALIAS(IntDefaultHandler); -void UTICK_IRQHandler(void) ALIAS(IntDefaultHandler); -void MRT_IRQHandler(void) ALIAS(IntDefaultHandler); -void CT32B0_IRQHandler(void) ALIAS(IntDefaultHandler); -void CT32B1_IRQHandler(void) ALIAS(IntDefaultHandler); -void CT32B2_IRQHandler(void) ALIAS(IntDefaultHandler); -void CT32B3_IRQHandler(void) ALIAS(IntDefaultHandler); -void CT32B4_IRQHandler(void) ALIAS(IntDefaultHandler); -void SCT0_IRQHandler(void) ALIAS(IntDefaultHandler); -void UART0_IRQHandler(void) ALIAS(IntDefaultHandler); -void UART1_IRQHandler(void) ALIAS(IntDefaultHandler); -void UART2_IRQHandler(void) ALIAS(IntDefaultHandler); -void UART3_IRQHandler(void) ALIAS(IntDefaultHandler); -void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler); -void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler); -void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler); -void SPI0_IRQHandler(void) ALIAS(IntDefaultHandler); -void SPI1_IRQHandler(void) ALIAS(IntDefaultHandler); -void ADC_SEQA_IRQHandler(void) ALIAS(IntDefaultHandler); -void ADC_SEQB_IRQHandler(void) ALIAS(IntDefaultHandler); -void ADC_THCMP_IRQHandler(void) ALIAS(IntDefaultHandler); -void RTC_IRQHandler(void) ALIAS(IntDefaultHandler); -void MAILBOX_IRQHandler(void) ALIAS(IntDefaultHandler); -// External Interrupts - For M4 only -void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT4_IRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT5_IRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT6_IRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT7_IRQHandler(void) ALIAS(IntDefaultHandler); -void SPI2_IRQHandler(void) ALIAS(IntDefaultHandler); -void SPI3_IRQHandler(void) ALIAS(IntDefaultHandler); -void RIT_IRQHandler(void) ALIAS(IntDefaultHandler); -void Reserved41_IRQHandler(void) ALIAS(IntDefaultHandler); -void Reserved42_IRQHandler(void) ALIAS(IntDefaultHandler); -void Reserved43_IRQHandler(void) ALIAS(IntDefaultHandler); -void Reserved44_IRQHandler(void) ALIAS(IntDefaultHandler); - -//***************************************************************************** -// -// The entry point for the application. -// __main() is the entry point for Redlib based applications -// main() is the entry point for Newlib based applications -// -//***************************************************************************** -#if defined (__REDLIB__) -extern void __main(void); -#endif -extern int main(void); -//***************************************************************************** -// -// External declaration for the pointer to the stack top from the Linker Script -// -//***************************************************************************** -extern void _vStackTop(void); - -//***************************************************************************** -#if defined (__cplusplus) -} // extern "C" -#endif -//***************************************************************************** -// -// The vector table. -// This relies on the linker script to place at correct location in memory. -// -//***************************************************************************** -extern void (* const g_pfnVectors[])(void); -__attribute__ ((section(".isr_vector"))) -void (* const g_pfnVectors[])(void) = { - // Core Level - CM3 - &_vStackTop, // The initial stack pointer - ResetISR, // The reset handler - NMI_Handler, // The NMI handler - HardFault_Handler, // The hard fault handler - MemManage_Handler, // The MPU fault handler - BusFault_Handler, // The bus fault handler - UsageFault_Handler, // The usage fault handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - SVC_Handler, // SVCall handler - DebugMon_Handler, // Debug monitor handler - 0, // Reserved - PendSV_Handler, // The PendSV handler - SysTick_Handler, // The SysTick handler - - // External Interrupts - Available on M0/M4 - WDT_IRQHandler, // Watchdog - BOD_IRQHandler, // Brown Out Detect - Reserved_IRQHandler, // Reserved - DMA_IRQHandler, // DMA Controller - GINT0_IRQHandler, // GPIO Group0 Interrupt - PIN_INT0_IRQHandler, // PIO INT0 - PIN_INT1_IRQHandler, // PIO INT1 - PIN_INT2_IRQHandler, // PIO INT2 - PIN_INT3_IRQHandler, // PIO INT3 - UTICK_IRQHandler, // UTICK timer - MRT_IRQHandler, // Multi-Rate Timer - CT32B0_IRQHandler, // Counter Timer 0 - CT32B1_IRQHandler, // Counter Timer 1 - CT32B2_IRQHandler, // Counter Timer 2 - CT32B3_IRQHandler, // Counter Timer 3 - CT32B4_IRQHandler, // Counter Timer 4 - SCT0_IRQHandler, // Smart Counter Timer - UART0_IRQHandler, // UART0 - UART1_IRQHandler, // UART1 - UART2_IRQHandler, // UART2 - UART3_IRQHandler, // UART3 - I2C0_IRQHandler, // I2C0 controller - I2C1_IRQHandler, // I2C1 controller - I2C2_IRQHandler, // I2C2 controller - SPI0_IRQHandler, // SPI0 controller - SPI1_IRQHandler, // SPI1 controller - ADC_SEQA_IRQHandler, // ADC SEQA - ADC_SEQB_IRQHandler, // ADC SEQB - ADC_THCMP_IRQHandler, // ADC THCMP and OVERRUN ORed - RTC_IRQHandler, // RTC Timer - Reserved_IRQHandler, // Reserved - MAILBOX_IRQHandler, // Mailbox - - // External Interrupts - For M4 only - GINT1_IRQHandler, // GPIO Group1 Interrupt - PIN_INT4_IRQHandler, // PIO INT4 - PIN_INT5_IRQHandler, // PIO INT5 - PIN_INT6_IRQHandler, // PIO INT6 - PIN_INT7_IRQHandler, // PIO INT7 - SPI2_IRQHandler, // SPI2 controller - SPI3_IRQHandler, // SPI3 controller - 0, // Reserved - RIT_IRQHandler, // RIT Timer - Reserved41_IRQHandler, // Reserved - Reserved42_IRQHandler, // Reserved - Reserved43_IRQHandler, // Reserved - Reserved44_IRQHandler, // Reserved - -}; /* End of g_pfnVectors */ - -//***************************************************************************** -// Functions to carry out the initialization of RW and BSS data sections. These -// are written as separate functions rather than being inlined within the -// ResetISR() function in order to cope with MCUs with multiple banks of -// memory. -//***************************************************************************** -__attribute__ ((section(".after_vectors"))) -void data_init(unsigned int romstart, unsigned int start, unsigned int len) { - unsigned int *pulDest = (unsigned int*) start; - unsigned int *pulSrc = (unsigned int*) romstart; - unsigned int loop; - for (loop = 0; loop < len; loop = loop + 4) - *pulDest++ = *pulSrc++; -} - -__attribute__ ((section(".after_vectors"))) -void bss_init(unsigned int start, unsigned int len) { - unsigned int *pulDest = (unsigned int*) start; - unsigned int loop; - for (loop = 0; loop < len; loop = loop + 4) - *pulDest++ = 0; -} - -//***************************************************************************** -// The following symbols are constructs generated by the linker, indicating -// the location of various points in the "Global Section Table". This table is -// created by the linker via the Code Red managed linker script mechanism. It -// contains the load address, execution address and length of each RW data -// section and the execution and length of each BSS (zero initialized) section. -//***************************************************************************** -extern unsigned int __data_section_table; -extern unsigned int __data_section_table_end; -extern unsigned int __bss_section_table; -extern unsigned int __bss_section_table_end; - -//***************************************************************************** -// Reset entry point for your code. -// Sets up a simple runtime environment and initializes the C/C++ -// library. -//***************************************************************************** - -#if defined (__MULTICORE_MASTER) -//#define cpu_ctrl 0x40000300 -//#define coproc_boot 0x40000304 -//#define set coproc_stack 0x40000308 -__attribute__ ((naked, section(".after_vectors.reset"))) -void ResetISR(void) { - asm volatile( - ".set cpu_ctrl, 0x40000300\t\n" - ".set coproc_boot, 0x40000304\t\n" - ".set coproc_stack, 0x40000308\t\n" - "MOVS R5, #1\t\n" - "LDR R0, =0xE000ED00\t\n" - "LDR R1, [R0]\t\n" // READ CPUID register - "LDR R2,=0x410CC601\t\n" // CM0 R0p1 identifier - "EORS R1,R1,R2\t\n" // XOR to see if we are C0 - "LDR R3, =cpu_ctrl\t\n" // get address of CPU_CTRL - "LDR R1,[R3]\t\n" // read cpu_ctrl reg into R1 - "BEQ.N cm0_boot\t\n" - "cm4_boot:\t\n" - "LDR R0,=coproc_boot\t\n" // coproc boot address - "LDR R0,[R0]\t\n" // get address to branch to - "MOVS R0,R0\t\n" // Check if 0 - "BEQ.N check_master_m4\t\n" // if zero in boot reg, we just branch to real reset - "BX R0\t\n" // otherwise, we branch to boot address - "commonboot:\t\n" - "LDR R0, =ResetISR2\t\n" // Jump to 'real' reset handler - "BX R0\t\n" - "cm0_boot:\t\n" - "LDR R0,=coproc_boot\t\n" // coproc boot address - "LDR R0,[R0]\t\n" // get address to branch to - "MOVS R0,R0\t\n" // Check if 0 - "BEQ.N check_master_m0\t\n" // if zero in boot reg, we just branch to real reset - "LDR R1,=coproc_stack\t\n" // pickup coprocesor stackpointer (from syscon CPSTACK) - "LDR R1,[R1]\t\n" - "MOV SP,R1\t\n" - "BX R0\t\n" // goto boot address - "check_master_m0:\t\n" - "ANDS R1,R1,R5\t\n" // bit test bit0 - "BEQ.N commonboot\t\n" // if we get 0, that means we are masters - "B.N goto_sleep_pending_reset\t\n" // Otherwise, there is no startup vector for slave, so we go to sleep - "check_master_m4:\t\n" - "ANDS R1,R1,R5\t\n" // bit test bit0 - "BNE.N commonboot\t\n" // if we get 1, that means we are masters - "goto_sleep_pending_reset:\t\n" - "MOV SP,R5\t\n" // load 0x1 into SP so that any stacking (eg on NMI) will not cause us to wakeup - // and write to uninitialised Stack area (instead it will LOCK us up before we cause damage) - // this code should only be reached if debugger bypassed ROM or we changed master without giving - // correct start address, the only way out of this is through a debugger change of SP and PC - "sleepo:\t\n" - "WFI\t\n" // go to sleep - "B.N sleepo\t\n" - ); -} - - -__attribute__ ((section(".after_vectors.reset"))) -void ResetISR2(void) { - -#else -__attribute__ ((section(".after_vectors.reset"))) -void ResetISR(void) { -#endif - - // If this is not the CM0+ core... -#if !defined (CORE_M0PLUS) - // If this is not a slave project... -#if !defined (__MULTICORE_M0SLAVE) && \ - !defined (__MULTICORE_M4SLAVE) - // Optionally enable RAM banks that may be off by default at reset -#if !defined (DONT_ENABLE_DISABLED_RAMBANKS) - volatile unsigned int *SYSCON_SYSAHBCLKCTRL0 = (unsigned int *) 0x400000c0; - // Ensure that SRAM2(4) bit in SYSAHBCLKCTRL0 are set - *SYSCON_SYSAHBCLKCTRL0 |= (1 << 4); -#endif -#endif -#endif - - // - // Copy the data sections from flash to SRAM. - // - unsigned int LoadAddr, ExeAddr, SectionLen; - unsigned int *SectionTableAddr; - - // Load base address of Global Section Table - SectionTableAddr = &__data_section_table; - - // Copy the data sections from flash to SRAM. - while (SectionTableAddr < &__data_section_table_end) { - LoadAddr = *SectionTableAddr++; - ExeAddr = *SectionTableAddr++; - SectionLen = *SectionTableAddr++; - data_init(LoadAddr, ExeAddr, SectionLen); - } - // At this point, SectionTableAddr = &__bss_section_table; - // Zero fill the bss segment - while (SectionTableAddr < &__bss_section_table_end) { - ExeAddr = *SectionTableAddr++; - SectionLen = *SectionTableAddr++; - bss_init(ExeAddr, SectionLen); - } - -#if !defined (__USE_LPCOPEN) -// LPCOpen init code deals with FP and VTOR initialisation -#if defined (__VFP_FP__) && !defined (__SOFTFP__) - /* - * Code to enable the Cortex-M4 FPU only included - * if appropriate build options have been selected. - * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C) - */ - // CPACR is located at address 0xE000ED88 - asm("LDR.W R0, =0xE000ED88"); - // Read CPACR - asm("LDR R1, [R0]"); - // Set bits 20-23 to enable CP10 and CP11 coprocessors - asm(" ORR R1, R1, #(0xF << 20)"); - // Write back the modified value to the CPACR - asm("STR R1, [R0]"); -#endif // (__VFP_FP__) && !(__SOFTFP__) - // ****************************** - // Check to see if we are running the code from a non-zero - // address (eg RAM, external flash), in which case we need - // to modify the VTOR register to tell the CPU that the - // vector table is located at a non-0x0 address. - - // Note that we do not use the CMSIS register access mechanism, - // as there is no guarantee that the project has been configured - // to use CMSIS. - unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; - if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) { - // CMSIS : SCB->VTOR =
- *pSCB_VTOR = (unsigned int) g_pfnVectors; - } -#endif -#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN) - SystemInit(); -#endif - -#if defined (__cplusplus) - // - // Call C++ library initialisation - // - __libc_init_array(); -#endif - -#if defined (__REDLIB__) - // Call the Redlib library, which in turn calls main() - __main(); -#else - main(); -#endif - - // - // main() shouldn't return, but if it does, we'll just enter an infinite loop - // - while (1) { - ; - } -} - -//***************************************************************************** -// Default exception handlers. Override the ones here by defining your own -// handler routines in your application code. -//***************************************************************************** -__attribute__ ((section(".after_vectors"))) -void NMI_Handler(void) { - while (1) { - } -} - -__attribute__ ((section(".after_vectors"))) -void HardFault_Handler(void) { - while (1) { - } -} - -__attribute__ ((section(".after_vectors"))) -void SVC_Handler(void) { - while (1) { - } -} - -__attribute__ ((section(".after_vectors"))) -void PendSV_Handler(void) { - while (1) { - } -} - -__attribute__ ((section(".after_vectors"))) -void SysTick_Handler(void) { - while (1) { - } -} - -//***************************************************************************** -// -// Processor ends up here if an unexpected interrupt occurs or a specific -// handler is not present in the application code. -// -//***************************************************************************** -__attribute__ ((section(".after_vectors"))) -void IntDefaultHandler(void) { - while (1) { - } -} - diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/crp.c b/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/crp.c deleted file mode 100644 index 5abed58b938..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/crp.c +++ /dev/null @@ -1,38 +0,0 @@ -//***************************************************************************** -// crp.c -// -// Source file to create CRP word expected by LPCXpresso IDE linker -//***************************************************************************** -// -// Copyright(C) NXP Semiconductors, 2013 -// All rights reserved. -// -// Software that is described herein is for illustrative purposes only -// which provides customers with programming information regarding the -// LPC products. This software is supplied "AS IS" without any warranties of -// any kind, and NXP Semiconductors and its licensor disclaim any and -// all warranties, express or implied, including all implied warranties of -// merchantability, fitness for a particular purpose and non-infringement of -// intellectual property rights. NXP Semiconductors assumes no responsibility -// or liability for the use of the software, conveys no license or rights under any -// patent, copyright, mask work right, or any other intellectual property rights in -// or to any products. NXP Semiconductors reserves the right to make changes -// in the software without notification. NXP Semiconductors also makes no -// representation or warranty that such application will be suitable for the -// specified use without further testing or modification. -// -// Permission to use, copy, modify, and distribute this software and its -// documentation is hereby granted, under NXP Semiconductors' and its -// licensor's relevant copyrights in the software, without fee, provided that it -// is used in conjunction with NXP Semiconductors microcontrollers. This -// copyright, permission, and disclaimer notice must appear in all copies of -// this code. -//***************************************************************************** - -#if defined (__CODE_RED) -#include -// Variable to store CRP value in. Will be placed automatically -// by the linker when "Enable Code Read Protect" selected. -// See crp.h header for more information -__CRP const unsigned int CRP_WORD = CRP_NO_CRP ; -#endif diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/gcc_startup_lpc5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/gcc_startup_lpc5410x.c deleted file mode 100644 index fcc48208609..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/gcc_startup_lpc5410x.c +++ /dev/null @@ -1,230 +0,0 @@ -/* Startup code for use with GNU tools.*/ -/* Forward declaration of the default fault handlers.*/ -static void Reset_Handler(void); -static void Default_Handler(void); - -/* External declaration for the interrupt handler used by the application.*/ -void NMI_Handler(void) __attribute__((weak, alias("Default_Handler"))); -void HardFault_Handler(void) __attribute__((weak, alias("Default_Handler"))); -void MemManage_Handler(void) __attribute__((weak, alias("Default_Handler"))); -void BusFault_Handler(void) __attribute__((weak, alias("Default_Handler"))); -void UsageFault_Handler(void) __attribute__((weak, alias("Default_Handler"))); -void SVC_Handler(void) __attribute__((weak, alias("Default_Handler"))); -void DebugMon_Handler(void) __attribute__((weak, alias("Default_Handler"))); -void PendSV_Handler(void) __attribute__((weak, alias("Default_Handler"))); -void SysTick_Handler(void) __attribute__((weak, alias("Default_Handler"))); - -void WDT_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void BOD_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void DMA_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void GINT0_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); - -void PIN_INT0_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void PIN_INT1_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void PIN_INT2_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void PIN_INT3_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void UTICK_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void MRT_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void CT32B0_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void CT32B1_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void CT32B2_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void CT32B3_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void CT32B4_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void SCT0_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void UART0_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void UART1_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void UART2_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void UART3_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void I2C0_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void I2C1_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void I2C2_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void SPI0_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void SPI1_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void ADC_SEQA_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void ADC_SEQB_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void ADC_THCMP_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void RTC_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -/*void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));*/ -void MAILBOX_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void GINT1_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void PIN_INT4_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void PIN_INT5_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void PIN_INT6_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void PIN_INT7_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -/*void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));*/ -/*void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));*/ -/*void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));*/ -void RIT_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void Reserved41_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void Reserved42_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void Reserved43_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -void Reserved44_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); -/* The entry point for the application.*/ -extern int main(void); - -/* Reserve space for the system stack.*/ -static unsigned long pulStack[512]; - -/* The vector table. Note that the proper constructs must be placed on this to*/ -/* ensure that it ends up at physical address 0x0000.0000.*/ -__attribute__ ((section(".isr_vector"))) -void (* const g_pfnVectors[])(void) = -{ - (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)), - /* The initial stack pointer*/ - Reset_Handler, /* Reset Handler*/ - NMI_Handler, /* NMI Handler*/ - HardFault_Handler, /* Hard Fault Handler*/ - MemManage_Handler, /* MPU Fault Handler*/ - BusFault_Handler, /* Bus Fault Handler*/ - UsageFault_Handler, /* Usage Fault Handler*/ - 0, /* Reserved*/ - 0, /* Reserved*/ - 0, /* Reserved*/ - 0, /* Reserved*/ - SVC_Handler, /* SVCall Handler*/ - DebugMon_Handler, /* Debug Monitor Handler*/ - 0, /* Reserved*/ - PendSV_Handler, /* PendSV Handler*/ - SysTick_Handler, /* SysTick Handler*/ - - /* External Interrupts*/ - WDT_IRQHandler, - BOD_IRQHandler, - Reserved_IRQHandler, - DMA_IRQHandler, - GINT0_IRQHandler, - PIN_INT0_IRQHandler, - PIN_INT1_IRQHandler, - PIN_INT2_IRQHandler, - PIN_INT3_IRQHandler, - UTICK_IRQHandler, - MRT_IRQHandler, - CT32B0_IRQHandler, - CT32B1_IRQHandler, - CT32B2_IRQHandler, - CT32B3_IRQHandler, - CT32B4_IRQHandler, - SCT0_IRQHandler, - UART0_IRQHandler, - UART1_IRQHandler, - UART2_IRQHandler, - UART3_IRQHandler, - I2C0_IRQHandler, - I2C1_IRQHandler, - I2C2_IRQHandler, - SPI0_IRQHandler, - SPI1_IRQHandler, - ADC_SEQA_IRQHandler, - ADC_SEQB_IRQHandler, - ADC_THCMP_IRQHandler, - RTC_IRQHandler, - Reserved_IRQHandler, - MAILBOX_IRQHandler, - GINT1_IRQHandler, - PIN_INT4_IRQHandler, - PIN_INT5_IRQHandler, - PIN_INT6_IRQHandler, - PIN_INT7_IRQHandler, - Reserved_IRQHandler, - Reserved_IRQHandler, - Reserved_IRQHandler, - RIT_IRQHandler, - Reserved41_IRQHandler, - Reserved42_IRQHandler, - Reserved43_IRQHandler, - Reserved44_IRQHandler, -}; -/* RIT_IRQHandler */ -/* Reserved41_IRQHandler*/ -/* TReserved42_IRQHandler he following are constructs created by the linker, indicating where the*/ -/* tReserved43_IRQHandler he "data" and "bss" segments reside in memory. The initializers for the*/ -/* fReserved44_IRQHandler or the "data" segment resides immediately following the "text" segment.*/ -extern unsigned long _etext; -extern unsigned long _data; -extern unsigned long _edata; -extern unsigned long _bss; -extern unsigned long _ebss; - -/* This is the code that gets called when the processor first starts execution*/ -/* following a reset event. Only the absolutely necessary set is performed,*/ -/* after which the application supplied entry() routine is called. Any fancy*/ -/* actions (such as making decisions based on the reset cause register, and*/ -/* resetting the bits in that register) are left solely in the hands of the*/ -/* application.*/ -static void Reset_Handler(void) -{ - unsigned long *pulSrc, *pulDest; - - /* Copy the data segment initializers from flash to SRAM.*/ - pulSrc = &_etext; - /* cppcheck-suppress comparePointers */ - for(pulDest = &_data; pulDest < &_edata; ) - { - *pulDest++ = *pulSrc++; - } - - -#if !defined (__USE_LPCOPEN) -/* LPCOpen init code deals with FP and VTOR initialisation*/ -#if defined (__VFP_FP__) && !defined (__SOFTFP__) - /* - * Code to enable the Cortex-M4 FPU only included - * if appropriate build options have been selected. - * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C) - */ - /* CPACR is located at address 0xE000ED88*/ - asm("LDR.W R0, =0xE000ED88"); - /* Read CPACR*/ - asm("LDR R1, [R0]"); - /* Set bits 20-23 to enable CP10 and CP11 coprocessors*/ - asm(" ORR R1, R1, #(0xF << 20)"); - /* Write back the modified value to the CPACR*/ - asm("STR R1, [R0]"); -#endif /* (__VFP_FP__) && !(__SOFTFP__)*/ - /* Check to see if we are running the code from a non-zero*/ - /* address (eg RAM, external flash), in which case we need*/ - /* to modify the VTOR register to tell the CPU that the*/ - /* vector table is located at a non-0x0 address.*/ - - /* Note that we do not use the CMSIS register access mechanism,*/ - /* as there is no guarantee that the project has been configured*/ - /* to use CMSIS.*/ - unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; - if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) - { - /* CMSIS : SCB->VTOR =
*/ - *pSCB_VTOR = (unsigned int) g_pfnVectors; - } -#endif - - /* Zero fill the bss segment.*/ - __asm(" ldr r0, =_bss\n" - " ldr r1, =_ebss\n" - " mov r2, #0\n" - " .thumb_func\n" - "zero_loop:\n" - " cmp r0, r1\n" - " it lt\n" - " strlt r2, [r0], #4\n" - " blt zero_loop"); - - /* call system init.*/ - extern void SystemInit(void); - SystemInit(); - - /* Call the application's entry point.*/ - main(); -} - -/* This is the code that gets called when the processor receives an unexpected*/ -/* interrupt. This simply enters an infinite loop, preserving the system state*/ -/* for examination by a debugger.*/ -static void Default_Handler(void) -{ - /* Go into an infinite loop.*/ - while(1) - { - } -} \ No newline at end of file diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/iar_startup_lpc5410x-m0.s b/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/iar_startup_lpc5410x-m0.s deleted file mode 100644 index bc99ab5dc7d..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/iar_startup_lpc5410x-m0.s +++ /dev/null @@ -1,304 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC5410x-m0.s -; * @purpose: CMSIS Cortex-M4/M0+ Core Device Startup File -; * for the NXP LPC5410x Device Series (manually edited) -; * @version: V1.00 -; * @date: 19. October 2009 -; *---------------------------------------------------------------------------- -; * -; * Copyright (C) 2009 ARM Limited. All rights reserved. -; * -; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD 0 - DCD 0 - DCD 0 -__vector_table_0x1c - DCD 0 ; Checksum of the first 7 words - DCD 0 - DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot - DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot - DCD SVC_Handler - DCD 0 - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_IRQHandler ; Watchdog - DCD BOD_IRQHandler ; Brown Out Detect - DCD Reserved_IRQHandler ; Reserved - DCD DMA_IRQHandler ; DMA Controller - DCD GINT0_IRQHandler ; GPIO Group0 Interrupt - DCD PIN_INT0_IRQHandler ; PIO INT0 - DCD PIN_INT1_IRQHandler ; PIO INT1 - DCD PIN_INT2_IRQHandler ; PIO INT2 - DCD PIN_INT3_IRQHandler ; PIO INT3 - DCD UTICK_IRQHandler ; UTICK timer - DCD MRT_IRQHandler ; Multi-Rate Timer - DCD CT32B0_IRQHandler ; CT32B0 - DCD CT32B1_IRQHandler ; CT32B1 - DCD CT32B2_IRQHandler ; CT32B2 - DCD CT32B3_IRQHandler ; CT32B3 - DCD CT32B4_IRQHandler ; CT32B4 - DCD SCT0_IRQHandler ; Smart Counter Timer - DCD UART0_IRQHandler ; UART0 - DCD UART1_IRQHandler ; UART1 - DCD UART2_IRQHandler ; UART2 - DCD UART3_IRQHandler ; UART3 - DCD I2C0_IRQHandler ; I2C0 controller - DCD I2C1_IRQHandler ; I2C1 controller - DCD I2C2_IRQHandler ; I2C2 controller - DCD SPI0_IRQHandler ; SPI0 controller - DCD SPI1_IRQHandler ; SPI1 controller - DCD ADC_SEQA_IRQHandler ; ADC0 A sequence (A/D Converter) interrupt - DCD ADC_SEQB_IRQHandler ; ADC0 B sequence (A/D Converter) interrupt - DCD ADC_THCMP_IRQHandler ; ADC THCMP and OVERRUN ORed - DCD RTC_IRQHandler ; RTC Timer - DCD Reserved_IRQHandler ; Reserved - DCD MAILBOX_IRQHandler ; Mailbox - -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - -#if !defined(SLAVEBOOT) - DATA -cpu_id EQU 0xE000ED00 -cpu_ctrl EQU 0x40000300 -coproc_boot EQU 0x40000304 -coproc_stack EQU 0x40000308 -rel_vals - DC32 cpu_id, cpu_ctrl, coproc_boot, coproc_stack - DC16 0xFFF, 0xC24 -#endif - - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -; Reset Handler - shared for both cores -Reset_Handler - -#if !defined(SLAVEBOOT) -; Both the M0+ and M4 core come via this shared startup code, - ; but the M0+ and M4 core have different vector tables. - ; Determine if the core executing this code is the master or - ; the slave and handle each core state individually. -shared_boot_entry - LDR r6, =rel_vals - MOVS r4, #0 ; Flag for slave core (0) - MOVS r5, #1 - - ; Determine which core (M0+ or M4) this code is running on - ; r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) -get_current_core_id - LDR r0, [r6, #0] - LDR r1, [r0] ; r1 = CPU ID status - LSRS r1, r1, #4 ; Right justify 12 CPU ID bits - LDRH r2, [r6, #16] ; Mask for CPU ID bits - ANDS r2, r1, r2 ; r2 = ARM COrtex CPU ID - LDRH r3, [r6, #18] ; Mask for CPU ID bits - CMP r3, r2 ; Core ID matches M4 identifier - BNE get_master_status - MOV r4, r5 ; Set flag for master core (1) - - ; Determine if M4 core is the master or slave - ; r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) -get_master_status - LDR r0, [r6, #4] - LDR r3, [r0] ; r3 = SYSCON co-processor CPU control status - ANDS r3, r3, r5 ; r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) - - ; Select boot based on selected master core and core ID -select_boot - EORS r3, r3, r4 ; r4 = (Bit 0: 0 = master, 1 = slave) - BNE slave_boot - B normal_boot - - ; Slave boot -slave_boot - LDR r0, [r6, #8] - LDR r2, [r0] ; r1 = SYSCON co-processor boot address - CMP r2, #0 ; Slave boot address = 0 (not set up)? - BEQ cpu_sleep - LDR r0, [r6, #12] - LDR r1, [r0] ; r5 = SYSCON co-processor stack address - MOV sp, r1 ; Update slave CPU stack pointer - ; Be sure to update VTOR for the slave MCU to point to the - ; slave vector table in boot memory - BX r2 ; Jump to slave boot address - - ; Slave isn't yet setup for system boot from the master - ; so sleep until the master sets it up and then reboots it -cpu_sleep - MOV sp, r5 ; Will force exception if something happens -cpu_sleep_wfi - WFI ; Sleep forever until master reboots - B cpu_sleep_wfi -#endif ; defined(SLAVEBOOT) - - ; Normal boot for master/slave -normal_boot - LDR r0, =SystemInit - BLX r0 - LDR r0, =__iar_program_start - BX r0 - -; For cores with SystemInit() or __iar_program_start(), the code will sleep the MCU - PUBWEAK SystemInit - SECTION .text:CODE:REORDER:NOROOT(1) -SystemInit - BX LR - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK Reserved_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -Reserved_IRQHandler - B . - - PUBWEAK WDT_IRQHandler ; Watchdog - PUBWEAK BOD_IRQHandler ; Brown Out Detect - PUBWEAK DMA_IRQHandler ; DMA Controller - PUBWEAK GINT0_IRQHandler ; GPIO Group0 Interrupt - PUBWEAK PIN_INT0_IRQHandler ; PIO INT0 - PUBWEAK PIN_INT1_IRQHandler ; PIO INT1 - PUBWEAK PIN_INT2_IRQHandler ; PIO INT2 - PUBWEAK PIN_INT3_IRQHandler ; PIO INT3 - PUBWEAK UTICK_IRQHandler ; UTICK timer - PUBWEAK MRT_IRQHandler ; Multi-Rate Timer - PUBWEAK CT32B0_IRQHandler ; CT32B0 - PUBWEAK CT32B1_IRQHandler ; CT32B1 - PUBWEAK CT32B2_IRQHandler ; CT32B2 - PUBWEAK CT32B3_IRQHandler ; CT32B3 - PUBWEAK CT32B4_IRQHandler ; CT32B4 - PUBWEAK UART0_IRQHandler ; UART0 - PUBWEAK SCT0_IRQHandler ; Smart Counter Timer - PUBWEAK UART1_IRQHandler ; UART1 - PUBWEAK UART2_IRQHandler ; UART2 - PUBWEAK UART3_IRQHandler ; UART3 - PUBWEAK I2C0_IRQHandler ; I2C0 controller - PUBWEAK I2C1_IRQHandler ; I2C1 controller - PUBWEAK I2C2_IRQHandler ; I2C2 controller - PUBWEAK SPI0_IRQHandler ; SPI0 controller - PUBWEAK SPI1_IRQHandler ; SPI1 controller - PUBWEAK ADC_SEQA_IRQHandler ; ADC0 A sequence (A/D Converter) interrupt - PUBWEAK ADC_SEQB_IRQHandler ; ADC0 B sequence (A/D Converter) interrupt - PUBWEAK ADC_THCMP_IRQHandler ; ADC THCMP and OVERRUN ORed - PUBWEAK RTC_IRQHandler ; RTC Timer - PUBWEAK MAILBOX_IRQHandler ; Mailbox - -WDT_IRQHandler ; Watchdog -BOD_IRQHandler ; Brown Out Detect -DMA_IRQHandler ; DMA Controller -GINT0_IRQHandler ; GPIO Group0 Interrupt -PIN_INT0_IRQHandler ; PIO INT0 -PIN_INT1_IRQHandler ; PIO INT1 -PIN_INT2_IRQHandler ; PIO INT2 -PIN_INT3_IRQHandler ; PIO INT3 -UTICK_IRQHandler ; UTICK timer -MRT_IRQHandler ; Multi-Rate Timer -CT32B0_IRQHandler ; CT32B0 -CT32B1_IRQHandler ; CT32B1 -CT32B2_IRQHandler ; CT32B2 -CT32B3_IRQHandler ; CT32B3 -CT32B4_IRQHandler ; CT32B4 -UART0_IRQHandler ; UART0 -SCT0_IRQHandler ; Smart Counter Timer -UART1_IRQHandler ; UART1 -UART2_IRQHandler ; UART2 -UART3_IRQHandler ; UART3 -I2C0_IRQHandler ; I2C0 controller -I2C1_IRQHandler ; I2C1 controller -I2C2_IRQHandler ; I2C2 controller -SPI0_IRQHandler ; SPI0 controller -SPI1_IRQHandler ; SPI1 controller -ADC_SEQA_IRQHandler ; ADC0 A sequence (A/D Converter) interrupt -ADC_SEQB_IRQHandler ; ADC0 B sequence (A/D Converter) interrupt -ADC_THCMP_IRQHandler ; ADC THCMP and OVERRUN ORed -RTC_IRQHandler ; RTC Timer -MAILBOX_IRQHandler ; Mailbox - -Default_Handler: - B . - - END diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/iar_startup_lpc5410x.s b/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/iar_startup_lpc5410x.s deleted file mode 100644 index f78911b62a0..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/iar_startup_lpc5410x.s +++ /dev/null @@ -1,356 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC5410x.s -; * @purpose: CMSIS Cortex-M4/M0+ Core Device Startup File -; * for the NXP LPC5410x Device Series (manually edited) -; * @version: V1.00 -; * @date: 19. October 2009 -; *---------------------------------------------------------------------------- -; * -; * Copyright (C) 2009 ARM Limited. All rights reserved. -; * -; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 ; Checksum of the first 7 words - DCD 0 - DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot - DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_IRQHandler ; Watchdog - DCD BOD_IRQHandler ; Brown Out Detect - DCD Reserved_IRQHandler ; Reserved - DCD DMA_IRQHandler ; DMA Controller - DCD GINT0_IRQHandler ; GPIO Group0 Interrupt - DCD PIN_INT0_IRQHandler ; PIO INT0 - DCD PIN_INT1_IRQHandler ; PIO INT1 - DCD PIN_INT2_IRQHandler ; PIO INT2 - DCD PIN_INT3_IRQHandler ; PIO INT3 - DCD UTICK_IRQHandler ; UTICK timer - DCD MRT_IRQHandler ; Multi-Rate Timer - DCD CT32B0_IRQHandler ; CT32B0 - DCD CT32B1_IRQHandler ; CT32B1 - DCD CT32B2_IRQHandler ; CT32B2 - DCD CT32B3_IRQHandler ; CT32B3 - DCD CT32B4_IRQHandler ; CT32B4 - DCD SCT0_IRQHandler ; Smart Counter Timer - DCD UART0_IRQHandler ; UART0 - DCD UART1_IRQHandler ; UART1 - DCD UART2_IRQHandler ; UART2 - DCD UART3_IRQHandler ; UART3 - DCD I2C0_IRQHandler ; I2C0 controller - DCD I2C1_IRQHandler ; I2C1 controller - DCD I2C2_IRQHandler ; I2C2 controller - DCD SPI0_IRQHandler ; SPI0 controller - DCD SPI1_IRQHandler ; SPI1 controller - DCD ADC_SEQA_IRQHandler ; ADC0 A sequence (A/D Converter) interrupt - DCD ADC_SEQB_IRQHandler ; ADC0 B sequence (A/D Converter) interrupt - DCD ADC_THCMP_IRQHandler ; ADC THCMP and OVERRUN ORed - DCD RTC_IRQHandler ; RTC Timer - DCD Reserved_IRQHandler ; Reserved - DCD MAILBOX_IRQHandler ; Mailbox - DCD GINT1_IRQHandler ; GPIO Group1 Interrupt - DCD PIN_INT4_IRQHandler ; PIO INT4 - DCD PIN_INT5_IRQHandler ; PIO INT5 - DCD PIN_INT6_IRQHandler ; PIO INT6 - DCD PIN_INT7_IRQHandler ; PIO INT7 - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD RIT_IRQHandler ; RITimer - DCD Reserved41_IRQHandler ; Reserved - DCD Reserved42_IRQHandler ; Reserved - DCD Reserved43_IRQHandler ; Reserved - DCD Reserved44_IRQHandler ; Reserved -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - -#if !defined(SLAVEBOOT) - DATA -cpu_id EQU 0xE000ED00 -cpu_ctrl EQU 0x40000300 -coproc_boot EQU 0x40000304 -coproc_stack EQU 0x40000308 -rel_vals - DC32 cpu_id, cpu_ctrl, coproc_boot, coproc_stack - DC16 0xFFF, 0xC24 -#endif - - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -; Reset Handler - shared for both cores -Reset_Handler - -#if !defined(SLAVEBOOT) -; Both the M0+ and M4 core come via this shared startup code, - ; but the M0+ and M4 core have different vector tables. - ; Determine if the core executing this code is the master or - ; the slave and handle each core state individually. -shared_boot_entry - LDR r6, =rel_vals - MOVS r4, #0 ; Flag for slave core (0) - MOVS r5, #1 - - ; Determine which core (M0+ or M4) this code is running on - ; r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) -get_current_core_id - LDR r0, [r6, #0] - LDR r1, [r0] ; r1 = CPU ID status - LSRS r1, r1, #4 ; Right justify 12 CPU ID bits - LDRH r2, [r6, #16] ; Mask for CPU ID bits - ANDS r2, r1, r2 ; r2 = ARM COrtex CPU ID - LDRH r3, [r6, #18] ; Mask for CPU ID bits - CMP r3, r2 ; Core ID matches M4 identifier - BNE get_master_status - MOV r4, r5 ; Set flag for master core (1) - - ; Determine if M4 core is the master or slave - ; r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) -get_master_status - LDR r0, [r6, #4] - LDR r3, [r0] ; r3 = SYSCON co-processor CPU control status - ANDS r3, r3, r5 ; r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) - - ; Select boot based on selected master core and core ID -select_boot - EORS r3, r3, r4 ; r4 = (Bit 0: 0 = master, 1 = slave) - BNE slave_boot - B normal_boot - - ; Slave boot -slave_boot - LDR r0, [r6, #8] - LDR r2, [r0] ; r1 = SYSCON co-processor boot address - CMP r2, #0 ; Slave boot address = 0 (not set up)? - BEQ cpu_sleep - LDR r0, [r6, #12] - LDR r1, [r0] ; r5 = SYSCON co-processor stack address - MOV sp, r1 ; Update slave CPU stack pointer - ; Be sure to update VTOR for the slave MCU to point to the - ; slave vector table in boot memory - BX r2 ; Jump to slave boot address - - ; Slave isn't yet setup for system boot from the master - ; so sleep until the master sets it up and then reboots it -cpu_sleep - MOV sp, r5 ; Will force exception if something happens -cpu_sleep_wfi - WFI ; Sleep forever until master reboots - B cpu_sleep_wfi -#endif ; defined(SLAVEBOOT) - - ; Normal boot for master/slave -normal_boot - LDR r0, =SystemInit - BLX r0 - LDR r0, =__iar_program_start - BX r0 - -; For cores with SystemInit() or __iar_program_start(), the code will sleep the MCU - PUBWEAK SystemInit - SECTION .text:CODE:REORDER:NOROOT(1) -SystemInit - BX LR - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK Reserved_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -Reserved_IRQHandler - B . - - PUBWEAK WDT_IRQHandler ; Watchdog - PUBWEAK BOD_IRQHandler ; Brown Out Detect - PUBWEAK DMA_IRQHandler ; DMA Controller - PUBWEAK GINT0_IRQHandler ; GPIO Group0 Interrupt - PUBWEAK PIN_INT0_IRQHandler ; PIO INT0 - PUBWEAK PIN_INT1_IRQHandler ; PIO INT1 - PUBWEAK PIN_INT2_IRQHandler ; PIO INT2 - PUBWEAK PIN_INT3_IRQHandler ; PIO INT3 - PUBWEAK UTICK_IRQHandler ; UTICK timer - PUBWEAK MRT_IRQHandler ; Multi-Rate Timer - PUBWEAK CT32B0_IRQHandler ; CT32B0 - PUBWEAK CT32B1_IRQHandler ; CT32B1 - PUBWEAK CT32B2_IRQHandler ; CT32B2 - PUBWEAK CT32B3_IRQHandler ; CT32B3 - PUBWEAK CT32B4_IRQHandler ; CT32B4 - PUBWEAK UART0_IRQHandler ; UART0 - PUBWEAK SCT0_IRQHandler ; Smart Counter Timer - PUBWEAK UART1_IRQHandler ; UART1 - PUBWEAK UART2_IRQHandler ; UART2 - PUBWEAK UART3_IRQHandler ; UART3 - PUBWEAK I2C0_IRQHandler ; I2C0 controller - PUBWEAK I2C1_IRQHandler ; I2C1 controller - PUBWEAK I2C2_IRQHandler ; I2C2 controller - PUBWEAK SPI0_IRQHandler ; SPI0 controller - PUBWEAK SPI1_IRQHandler ; SPI1 controller - PUBWEAK ADC_SEQA_IRQHandler ; ADC0 A sequence (A/D Converter) interrupt - PUBWEAK ADC_SEQB_IRQHandler ; ADC0 B sequence (A/D Converter) interrupt - PUBWEAK ADC_THCMP_IRQHandler ; ADC THCMP and OVERRUN ORed - PUBWEAK RTC_IRQHandler ; RTC Timer - PUBWEAK MAILBOX_IRQHandler ; Mailbox - PUBWEAK GINT1_IRQHandler ; GPIO Group1 Interrupt - PUBWEAK PIN_INT4_IRQHandler ; PIO INT4 - PUBWEAK PIN_INT5_IRQHandler ; PIO INT5 - PUBWEAK PIN_INT6_IRQHandler ; PIO INT6 - PUBWEAK PIN_INT7_IRQHandler ; PIO INT7 - PUBWEAK RIT_IRQHandler ; RITimer - PUBWEAK Reserved41_IRQHandler ; Reserved - PUBWEAK Reserved42_IRQHandler ; Reserved - PUBWEAK Reserved43_IRQHandler ; Reserved - PUBWEAK Reserved44_IRQHandler ; Reserved - -WDT_IRQHandler ; Watchdog -BOD_IRQHandler ; Brown Out Detect -DMA_IRQHandler ; DMA Controller -GINT0_IRQHandler ; GPIO Group0 Interrupt -PIN_INT0_IRQHandler ; PIO INT0 -PIN_INT1_IRQHandler ; PIO INT1 -PIN_INT2_IRQHandler ; PIO INT2 -PIN_INT3_IRQHandler ; PIO INT3 -UTICK_IRQHandler ; UTICK timer -MRT_IRQHandler ; Multi-Rate Timer -CT32B0_IRQHandler ; CT32B0 -CT32B1_IRQHandler ; CT32B1 -CT32B2_IRQHandler ; CT32B2 -CT32B3_IRQHandler ; CT32B3 -CT32B4_IRQHandler ; CT32B4 -UART0_IRQHandler ; UART0 -SCT0_IRQHandler ; Smart Counter Timer -UART1_IRQHandler ; UART1 -UART2_IRQHandler ; UART2 -UART3_IRQHandler ; UART3 -I2C0_IRQHandler ; I2C0 controller -I2C1_IRQHandler ; I2C1 controller -I2C2_IRQHandler ; I2C2 controller -SPI0_IRQHandler ; SPI0 controller -SPI1_IRQHandler ; SPI1 controller -ADC_SEQA_IRQHandler ; ADC0 A sequence (A/D Converter) interrupt -ADC_SEQB_IRQHandler ; ADC0 B sequence (A/D Converter) interrupt -ADC_THCMP_IRQHandler ; ADC THCMP and OVERRUN ORed -RTC_IRQHandler ; RTC Timer -MAILBOX_IRQHandler ; Mailbox -GINT1_IRQHandler ; GPIO Group1 Interrupt -PIN_INT4_IRQHandler ; PIO INT4 -PIN_INT5_IRQHandler ; PIO INT5 -PIN_INT6_IRQHandler ; PIO INT6 -PIN_INT7_IRQHandler ; PIO INT7 -RIT_IRQHandler ; RITimer -Reserved41_IRQHandler ; Reserved -Reserved42_IRQHandler ; Reserved -Reserved43_IRQHandler ; Reserved -Reserved44_IRQHandler ; Reserved - -Default_Handler: - B . - - END diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/keil_startup_lpc5410x-m0.s b/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/keil_startup_lpc5410x-m0.s deleted file mode 100644 index 2b09d3340fb..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/keil_startup_lpc5410x-m0.s +++ /dev/null @@ -1,338 +0,0 @@ -;/* -; * @brief LPC5410x M0 core startup code for Keil -; * -; * @note -; * Copyright(C) NXP Semiconductors, 2014 -; * All rights reserved. -; * -; * @par -; * Software that is described herein is for illustrative purposes only -; * which provides customers with programming information regarding the -; * LPC products. This software is supplied "AS IS" without any warranties of -; * any kind, and NXP Semiconductors and its licensor disclaim any and -; * all warranties, express or implied, including all implied warranties of -; * merchantability, fitness for a particular purpose and non-infringement of -; * intellectual property rights. NXP Semiconductors assumes no responsibility -; * or liability for the use of the software, conveys no license or rights under any -; * patent, copyright, mask work right, or any other intellectual property rights in -; * or to any products. NXP Semiconductors reserves the right to make changes -; * in the software without notification. NXP Semiconductors also makes no -; * representation or warranty that such application will be suitable for the -; * specified use without further testing or modification. -; * -; * @par -; * Permission to use, copy, modify, and distribute this software and its -; * documentation is hereby granted, under NXP Semiconductors' and its -; * licensor's relevant copyrights in the software, without fee, provided that it -; * is used in conjunction with NXP Semiconductors microcontrollers. This -; * copyright, permission, and disclaimer notice must appear in all copies of -; * this code. -; */ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000200 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 - DCD 0 - DCD 0 -__vector_table_0x1c - DCD 0 ; Checksum of the first 7 words - DCD 0 - DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot - DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot - DCD SVC_Handler ; SVCall Handler - DCD 0 - DCD 0 - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WDT_IRQHandler ; Watchdog - DCD BOD_IRQHandler ; Brown Out Detect - DCD Reserved_IRQHandler ; Reserved - DCD DMA_IRQHandler ; DMA Controller - DCD GINT0_IRQHandler ; GPIO Group0 Interrupt - DCD PIN_INT0_IRQHandler ; PIO INT0 - DCD PIN_INT1_IRQHandler ; PIO INT1 - DCD PIN_INT2_IRQHandler ; PIO INT2 - DCD PIN_INT3_IRQHandler ; PIO INT3 - DCD UTICK_IRQHandler ; UTICK timer - DCD MRT_IRQHandler ; Multi-Rate Timer - DCD CT32B0_IRQHandler ; CT32B0 - DCD CT32B1_IRQHandler ; CT32B1 - DCD CT32B2_IRQHandler ; CT32B2 - DCD CT32B3_IRQHandler ; CT32B3 - DCD CT32B4_IRQHandler ; CT32B4 - DCD SCT0_IRQHandler ; Smart Counter Timer - DCD UART0_IRQHandler ; UART0 - DCD UART1_IRQHandler ; UART1 - DCD UART2_IRQHandler ; UART2 - DCD UART3_IRQHandler ; UART3 - DCD I2C0_IRQHandler ; I2C0 controller - DCD I2C1_IRQHandler ; I2C1 controller - DCD I2C2_IRQHandler ; I2C2 controller - DCD SPI0_IRQHandler ; SPI0 controller - DCD SPI1_IRQHandler ; SPI1 controller - DCD ADC_SEQA_IRQHandler ; ADC0 A sequence (A/D Converter) interrupt - DCD ADC_SEQB_IRQHandler ; ADC0 B sequence (A/D Converter) interrupt - DCD ADC_THCMP_IRQHandler ; ADC THCMP and OVERRUN ORed - DCD RTC_IRQHandler ; RTC Timer - DCD Reserved_IRQHandler ; Reserved - DCD MAILBOX_IRQHandler ; Mailbox - -;// Code Read Protection level (CRP) -;// CRP_Level: -;// <0xFFFFFFFF=> Disabled -;// <0x4E697370=> NO_ISP -;// <0x12345678=> CRP1 -;// <0x87654321=> CRP2 -;// <0x43218765=> CRP3 (Are you sure?) -;// -CRP_Level EQU 0xFFFFFFFF - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - AREA |.text|, CODE, READONLY - -cpu_id EQU 0xE000ED00 -cpu_ctrl EQU 0x40000300 -coproc_boot EQU 0x40000304 -coproc_stack EQU 0x40000308 - -rel_vals - DCD cpu_id, cpu_ctrl, coproc_boot, coproc_stack - DCW 0xFFF, 0xC24 - -; Reset Handler - shared for both cores -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - EXPORT SystemInit [WEAK] - IMPORT __main - - IF :LNOT::DEF:SLAVEBOOT - ; Both the M0+ and M4 core come via this shared startup code, - ; but the M0+ and M4 core have different vector tables. - ; Determine if the core executing this code is the master or - ; the slave and handle each core state individually. -shared_boot_entry - LDR r6, =rel_vals - MOVS r4, #0 ; Flag for slave core (0) - MOVS r5, #1 - - ; Determine which core (M0+ or M4) this code is running on - ; r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) -get_current_core_id - LDR r0, [r6, #0] - LDR r1, [r0] ; r1 = CPU ID status - LSRS r1, r1, #4 ; Right justify 12 CPU ID bits - LDRH r2, [r6, #16] ; Mask for CPU ID bits - ANDS r2, r1, r2 ; r2 = ARM COrtex CPU ID - LDRH r3, [r6, #18] ; Mask for CPU ID bits - CMP r3, r2 ; Core ID matches M4 identifier - BNE get_master_status - MOV r4, r5 ; Set flag for master core (1) - - ; Determine if M4 core is the master or slave - ; r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) -get_master_status - LDR r0, [r6, #4] - LDR r3, [r0] ; r3 = SYSCON co-processor CPU control status - ANDS r3, r3, r5 ; r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) - - ; Select boot based on selected master core and core ID -select_boot - EORS r3, r3, r4 ; r4 = (Bit 0: 0 = master, 1 = slave) - BNE slave_boot - B normal_boot - - ; Slave boot -slave_boot - LDR r0, [r6, #8] - LDR r2, [r0] ; r1 = SYSCON co-processor boot address - CMP r2, #0 ; Slave boot address = 0 (not set up)? - BEQ cpu_sleep - LDR r0, [r6, #12] - LDR r1, [r0] ; r5 = SYSCON co-processor stack address - MOV sp, r1 ; Update slave CPU stack pointer - ; Be sure to update VTOR for the slave MCU to point to the - ; slave vector table in boot memory - BX r2 ; Jump to slave boot address - - ; Slave isn't yet setup for system boot from the master - ; so sleep until the master sets it up and then reboots it -cpu_sleep - MOV sp, r5 ; Will force exception if something happens -cpu_sleep_wfi - WFI ; Sleep forever until master reboots - B cpu_sleep_wfi - ENDIF - - ; Normal boot for master/slave -normal_boot - LDR r0, =SystemInit - BLX r0 - LDR r0, =__main - BX r0 - ENDP - -; For cores with SystemInit() or __main(), the code will sleep the MCU -SystemInit PROC - EXPORT SystemInit [WEAK] - BX lr - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT WDT_IRQHandler [WEAK] ; Watchdog - EXPORT BOD_IRQHandler [WEAK] ; Brown Out Detect - EXPORT DMA_IRQHandler [WEAK] ; DMA Controller - EXPORT GINT0_IRQHandler [WEAK] ; GPIO Group0 Interrupt - EXPORT PIN_INT0_IRQHandler [WEAK] ; PIO INT0 - EXPORT PIN_INT1_IRQHandler [WEAK] ; PIO INT1 - EXPORT PIN_INT2_IRQHandler [WEAK] ; PIO INT2 - EXPORT PIN_INT3_IRQHandler [WEAK] ; PIO INT3 - EXPORT UTICK_IRQHandler [WEAK] ; UTICK timer - EXPORT MRT_IRQHandler [WEAK] ; Multi-Rate Timer - EXPORT CT32B0_IRQHandler [WEAK] ; CT32B0 - EXPORT CT32B1_IRQHandler [WEAK] ; CT32B1 - EXPORT CT32B2_IRQHandler [WEAK] ; CT32B2 - EXPORT CT32B3_IRQHandler [WEAK] ; CT32B3 - EXPORT CT32B4_IRQHandler [WEAK] ; CT32B4 - EXPORT UART0_IRQHandler [WEAK] ; UART0 - EXPORT SCT0_IRQHandler [WEAK] ; Smart Counter Timer - EXPORT UART1_IRQHandler [WEAK] ; UART1 - EXPORT UART2_IRQHandler [WEAK] ; UART2 - EXPORT UART3_IRQHandler [WEAK] ; UART3 - EXPORT I2C0_IRQHandler [WEAK] ; I2C0 controller - EXPORT I2C1_IRQHandler [WEAK] ; I2C1 controller - EXPORT I2C2_IRQHandler [WEAK] ; I2C2 controller - EXPORT SPI0_IRQHandler [WEAK] ; SPI0 controller - EXPORT SPI1_IRQHandler [WEAK] ; SPI1 controller - EXPORT ADC_SEQA_IRQHandler [WEAK] ; ADC0 A sequence (A/D Converter) interrupt - EXPORT ADC_SEQB_IRQHandler [WEAK] ; ADC0 B sequence (A/D Converter) interrupt - EXPORT ADC_THCMP_IRQHandler [WEAK] ; ADC THCMP and OVERRUN ORed - EXPORT RTC_IRQHandler [WEAK] ; RTC Timer - EXPORT MAILBOX_IRQHandler [WEAK] ; Mailbox - EXPORT Reserved_IRQHandler [WEAK] ; Reserved - -WDT_IRQHandler ; Watchdog -BOD_IRQHandler ; Brown Out Detect -DMA_IRQHandler ; DMA Controller -GINT0_IRQHandler ; GPIO Group0 Interrupt -PIN_INT0_IRQHandler ; PIO INT0 -PIN_INT1_IRQHandler ; PIO INT1 -PIN_INT2_IRQHandler ; PIO INT2 -PIN_INT3_IRQHandler ; PIO INT3 -UTICK_IRQHandler ; UTICK timer -MRT_IRQHandler ; Multi-Rate Timer -CT32B0_IRQHandler ; CT32B0 -CT32B1_IRQHandler ; CT32B1 -CT32B2_IRQHandler ; CT32B2 -CT32B3_IRQHandler ; CT32B3 -CT32B4_IRQHandler ; CT32B4 -UART0_IRQHandler ; UART0 -SCT0_IRQHandler ; Smart Counter Timer -UART1_IRQHandler ; UART1 -UART2_IRQHandler ; UART2 -UART3_IRQHandler ; UART3 -I2C0_IRQHandler ; I2C0 controller -I2C1_IRQHandler ; I2C1 controller -I2C2_IRQHandler ; I2C2 controller -SPI0_IRQHandler ; SPI0 controller -SPI1_IRQHandler ; SPI1 controller -ADC_SEQA_IRQHandler ; ADC0 A sequence (A/D Converter) interrupt -ADC_SEQB_IRQHandler ; ADC0 B sequence (A/D Converter) interrupt -ADC_THCMP_IRQHandler ; ADC THCMP and OVERRUN ORed -RTC_IRQHandler ; RTC Timer -MAILBOX_IRQHandler ; Mailbox -Reserved_IRQHandler ; Reserved - - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - - END diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/keil_startup_lpc5410x.s b/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/keil_startup_lpc5410x.s deleted file mode 100644 index d6a37ceb4a7..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/keil_startup_lpc5410x.s +++ /dev/null @@ -1,388 +0,0 @@ -;/* -; * @brief LPC5410x startup code for Keil -; * -; * @note -; * Copyright(C) NXP Semiconductors, 2014 -; * All rights reserved. -; * -; * @par -; * Software that is described herein is for illustrative purposes only -; * which provides customers with programming information regarding the -; * LPC products. This software is supplied "AS IS" without any warranties of -; * any kind, and NXP Semiconductors and its licensor disclaim any and -; * all warranties, express or implied, including all implied warranties of -; * merchantability, fitness for a particular purpose and non-infringement of -; * intellectual property rights. NXP Semiconductors assumes no responsibility -; * or liability for the use of the software, conveys no license or rights under any -; * patent, copyright, mask work right, or any other intellectual property rights in -; * or to any products. NXP Semiconductors reserves the right to make changes -; * in the software without notification. NXP Semiconductors also makes no -; * representation or warranty that such application will be suitable for the -; * specified use without further testing or modification. -; * -; * @par -; * Permission to use, copy, modify, and distribute this software and its -; * documentation is hereby granted, under NXP Semiconductors' and its -; * licensor's relevant copyrights in the software, without fee, provided that it -; * is used in conjunction with NXP Semiconductors microcontrollers. This -; * copyright, permission, and disclaimer notice must appear in all copies of -; * this code. -; */ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000200 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000100 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 ; Checksum of the first 7 words - DCD 0 - DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot - DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_IRQHandler ; Watchdog - DCD BOD_IRQHandler ; Brown Out Detect - DCD Reserved_IRQHandler ; Reserved - DCD DMA_IRQHandler ; DMA Controller - DCD GINT0_IRQHandler ; GPIO Group0 Interrupt - DCD PIN_INT0_IRQHandler ; PIO INT0 - DCD PIN_INT1_IRQHandler ; PIO INT1 - DCD PIN_INT2_IRQHandler ; PIO INT2 - DCD PIN_INT3_IRQHandler ; PIO INT3 - DCD UTICK_IRQHandler ; UTICK timer - DCD MRT_IRQHandler ; Multi-Rate Timer - DCD CT32B0_IRQHandler ; CT32B0 - DCD CT32B1_IRQHandler ; CT32B1 - DCD CT32B2_IRQHandler ; CT32B2 - DCD CT32B3_IRQHandler ; CT32B3 - DCD CT32B4_IRQHandler ; CT32B4 - DCD SCT0_IRQHandler ; Smart Counter Timer - DCD UART0_IRQHandler ; UART0 - DCD UART1_IRQHandler ; UART1 - DCD UART2_IRQHandler ; UART2 - DCD UART3_IRQHandler ; UART3 - DCD I2C0_IRQHandler ; I2C0 controller - DCD I2C1_IRQHandler ; I2C1 controller - DCD I2C2_IRQHandler ; I2C2 controller - DCD SPI0_IRQHandler ; SPI0 controller - DCD SPI1_IRQHandler ; SPI1 controller - DCD ADC_SEQA_IRQHandler ; ADC0 A sequence (A/D Converter) interrupt - DCD ADC_SEQB_IRQHandler ; ADC0 B sequence (A/D Converter) interrupt - DCD ADC_THCMP_IRQHandler ; ADC THCMP and OVERRUN ORed - DCD RTC_IRQHandler ; RTC Timer - DCD Reserved_IRQHandler ; Reserved - DCD MAILBOX_IRQHandler ; Mailbox - DCD GINT1_IRQHandler ; GPIO Group1 Interrupt - DCD PIN_INT4_IRQHandler ; PIO INT4 - DCD PIN_INT5_IRQHandler ; PIO INT5 - DCD PIN_INT6_IRQHandler ; PIO INT6 - DCD PIN_INT7_IRQHandler ; PIO INT7 - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD RIT_IRQHandler ; RITimer - DCD Reserved41_IRQHandler ; Reserved - DCD Reserved42_IRQHandler ; Reserved - DCD Reserved43_IRQHandler ; Reserved - DCD Reserved44_IRQHandler ; Reserved - -;// Code Read Protection level (CRP) -;// CRP_Level: -;// <0xFFFFFFFF=> Disabled -;// <0x4E697370=> NO_ISP -;// <0x12345678=> CRP1 -;// <0x87654321=> CRP2 -;// <0x43218765=> CRP3 (Are you sure?) -;// -;CRP_Level EQU 0xFFFFFFFF - - ;IF :LNOT::DEF:NO_CRP - ;AREA |.ARM.__at_0x02FC|, CODE, READONLY -;CRP_Key DCD 0xFFFFFFFF - ;ENDIF - - AREA |.text|, CODE, READONLY - -;cpu_id EQU 0xE000ED00 -;cpu_ctrl EQU 0x40000300 -;coproc_boot EQU 0x40000304 -;coproc_stack EQU 0x40000308 - -;rel_vals - ;DCD cpu_id, cpu_ctrl, coproc_boot, coproc_stack - ;DCW 0xFFF, 0xC24 - -; Reset Handler - shared for both cores -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - EXPORT SystemInit [WEAK] - IMPORT __main - - ;IF :LNOT::DEF:SLAVEBOOT - ;Both the M0+ and M4 core come via this shared startup code, - ;but the M0+ and M4 core have different vector tables. - ;Determine if the core executing this code is the master or - ;the slave and handle each core state individually. -;shared_boot_entry - ;LDR r6, =rel_vals - ;MOVS r4, #0 ; Flag for slave core (0) - ;MOVS r5, #1 - - ;; Determine which core (M0+ or M4) this code is running on - ;; r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) -;get_current_core_id - ;LDR r0, [r6, #0] - ;LDR r1, [r0] ; r1 = CPU ID status - ;LSRS r1, r1, #4 ; Right justify 12 CPU ID bits - ;LDRH r2, [r6, #16] ; Mask for CPU ID bits - ;ANDS r2, r1, r2 ; r2 = ARM COrtex CPU ID - ;LDRH r3, [r6, #18] ; Mask for CPU ID bits - ;CMP r3, r2 ; Core ID matches M4 identifier - ;BNE get_master_status - ;MOV r4, r5 ; Set flag for master core (1) - - ;; Determine if M4 core is the master or slave - ;; r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) -;get_master_status - ;LDR r0, [r6, #4] - ;LDR r3, [r0] ; r3 = SYSCON co-processor CPU control status - ;ANDS r3, r3, r5 ; r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) - - ;; Select boot based on selected master core and core ID -;select_boot - ;EORS r3, r3, r4 ; r4 = (Bit 0: 0 = master, 1 = slave) - ;BNE slave_boot - ;B normal_boot - - ;; Slave boot -;slave_boot - ;LDR r0, [r6, #8] - ;LDR r2, [r0] ; r1 = SYSCON co-processor boot address - ;CMP r2, #0 ; Slave boot address = 0 (not set up)? - ;BEQ cpu_sleep - ;LDR r0, [r6, #12] - ;LDR r1, [r0] ; r5 = SYSCON co-processor stack address - ;MOV sp, r1 ; Update slave CPU stack pointer - ;; Be sure to update VTOR for the slave MCU to point to the - ;; slave vector table in boot memory - ;BX r2 ; Jump to slave boot address - - ;; Slave isn't yet setup for system boot from the master - ;; so sleep until the master sets it up and then reboots it -;cpu_sleep - ;MOV sp, r5 ; Will force exception if something happens -;cpu_sleep_wfi - ;WFI ; Sleep forever until master reboots - ;B cpu_sleep_wfi - ;ENDIF - - ; Normal boot for master/slave -;normal_boot - LDR r0, =SystemInit - BLX r0 - LDR r0, =__main - BX r0 - ENDP - -; For cores with SystemInit() or __main(), the code will sleep the MCU -SystemInit PROC - EXPORT SystemInit [WEAK] - BX lr - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT WDT_IRQHandler [WEAK] ; Watchdog - EXPORT BOD_IRQHandler [WEAK] ; Brown Out Detect - EXPORT DMA_IRQHandler [WEAK] ; DMA Controller - EXPORT GINT0_IRQHandler [WEAK] ; GPIO Group0 Interrupt - EXPORT PIN_INT0_IRQHandler [WEAK] ; PIO INT0 - EXPORT PIN_INT1_IRQHandler [WEAK] ; PIO INT1 - EXPORT PIN_INT2_IRQHandler [WEAK] ; PIO INT2 - EXPORT PIN_INT3_IRQHandler [WEAK] ; PIO INT3 - EXPORT UTICK_IRQHandler [WEAK] ; UTICK timer - EXPORT MRT_IRQHandler [WEAK] ; Multi-Rate Timer - EXPORT CT32B0_IRQHandler [WEAK] ; CT32B0 - EXPORT CT32B1_IRQHandler [WEAK] ; CT32B1 - EXPORT CT32B2_IRQHandler [WEAK] ; CT32B2 - EXPORT CT32B3_IRQHandler [WEAK] ; CT32B3 - EXPORT CT32B4_IRQHandler [WEAK] ; CT32B4 - EXPORT UART0_IRQHandler [WEAK] ; UART0 - EXPORT SCT0_IRQHandler [WEAK] ; Smart Counter Timer - EXPORT UART1_IRQHandler [WEAK] ; UART1 - EXPORT UART2_IRQHandler [WEAK] ; UART2 - EXPORT UART3_IRQHandler [WEAK] ; UART3 - EXPORT I2C0_IRQHandler [WEAK] ; I2C0 controller - EXPORT I2C1_IRQHandler [WEAK] ; I2C1 controller - EXPORT I2C2_IRQHandler [WEAK] ; I2C2 controller - EXPORT SPI0_IRQHandler [WEAK] ; SPI0 controller - EXPORT SPI1_IRQHandler [WEAK] ; SPI1 controller - EXPORT ADC_SEQA_IRQHandler [WEAK] ; ADC0 A sequence (A/D Converter) interrupt - EXPORT ADC_SEQB_IRQHandler [WEAK] ; ADC0 B sequence (A/D Converter) interrupt - EXPORT ADC_THCMP_IRQHandler [WEAK] ; ADC THCMP and OVERRUN ORed - EXPORT RTC_IRQHandler [WEAK] ; RTC Timer - EXPORT MAILBOX_IRQHandler [WEAK] ; Mailbox - EXPORT GINT1_IRQHandler [WEAK] ; GPIO Group1 Interrupt - EXPORT PIN_INT4_IRQHandler [WEAK] ; PIO INT4 - EXPORT PIN_INT5_IRQHandler [WEAK] ; PIO INT5 - EXPORT PIN_INT6_IRQHandler [WEAK] ; PIO INT6 - EXPORT PIN_INT7_IRQHandler [WEAK] ; PIO INT7 - EXPORT RIT_IRQHandler [WEAK] ; RITimer - EXPORT Reserved41_IRQHandler [WEAK] ; Reserved - EXPORT Reserved42_IRQHandler [WEAK] ; Reserved - EXPORT Reserved43_IRQHandler [WEAK] ; Reserved - EXPORT Reserved44_IRQHandler [WEAK] ; Reserved - EXPORT Reserved_IRQHandler [WEAK] ; Reserved - -WDT_IRQHandler ; Watchdog -BOD_IRQHandler ; Brown Out Detect -DMA_IRQHandler ; DMA Controller -GINT0_IRQHandler ; GPIO Group0 Interrupt -PIN_INT0_IRQHandler ; PIO INT0 -PIN_INT1_IRQHandler ; PIO INT1 -PIN_INT2_IRQHandler ; PIO INT2 -PIN_INT3_IRQHandler ; PIO INT3 -UTICK_IRQHandler ; UTICK timer -MRT_IRQHandler ; Multi-Rate Timer -CT32B0_IRQHandler ; CT32B0 -CT32B1_IRQHandler ; CT32B1 -CT32B2_IRQHandler ; CT32B2 -CT32B3_IRQHandler ; CT32B3 -CT32B4_IRQHandler ; CT32B4 -UART0_IRQHandler ; UART0 -SCT0_IRQHandler ; Smart Counter Timer -UART1_IRQHandler ; UART1 -UART2_IRQHandler ; UART2 -UART3_IRQHandler ; UART3 -I2C0_IRQHandler ; I2C0 controller -I2C1_IRQHandler ; I2C1 controller -I2C2_IRQHandler ; I2C2 controller -SPI0_IRQHandler ; SPI0 controller -SPI1_IRQHandler ; SPI1 controller -ADC_SEQA_IRQHandler ; ADC0 A sequence (A/D Converter) interrupt -ADC_SEQB_IRQHandler ; ADC0 B sequence (A/D Converter) interrupt -ADC_THCMP_IRQHandler ; ADC THCMP and OVERRUN ORed -RTC_IRQHandler ; RTC Timer -MAILBOX_IRQHandler ; Mailbox -GINT1_IRQHandler ; GPIO Group1 Interrupt -PIN_INT4_IRQHandler ; PIO INT4 -PIN_INT5_IRQHandler ; PIO INT5 -PIN_INT6_IRQHandler ; PIO INT6 -PIN_INT7_IRQHandler ; PIO INT7 -RIT_IRQHandler ; RITimer -Reserved41_IRQHandler ; Reserved -Reserved42_IRQHandler ; Reserved -Reserved43_IRQHandler ; Reserved -Reserved44_IRQHandler ; Reserved -Reserved_IRQHandler ; Reserved - - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - - END diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/mtb.c b/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/mtb.c deleted file mode 100644 index 4a653898226..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/mtb.c +++ /dev/null @@ -1,86 +0,0 @@ -//***************************************************************************** -// +--+ -// | ++----+ -// +-++ | -// | | -// +-+--+ | -// | +--+--+ -// +----+ Copyright (c) 2013 Code Red Technologies Ltd. -// -// mtb.c -// -// Optionally defines an array to be used as a buffer for Micro Trace -// Buffer (MTB) instruction trace on Cortex-M0+ parts -// -// Version : 130502 -// -// Software License Agreement -// -// The software is owned by Code Red Technologies and/or its suppliers, and is -// protected under applicable copyright laws. All rights are reserved. Any -// use in violation of the foregoing restrictions may subject the user to criminal -// sanctions under applicable laws, as well as to civil liability for the breach -// of the terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT -// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH -// CODE RED TECHNOLOGIES LTD. -// -//***************************************************************************** - -/******************************************************************* - * Symbols controlling behavior of this code... - * - * __MTB_DISABLE - * If this symbol is defined, then the buffer array for the MTB - * will not be created. - * - * __MTB_BUFFER_SIZE - * Symbol specifying the sizer of the buffer array for the MTB. - * This must be a power of 2 in size, and fit into the available - * RAM. The MTB buffer will also be aligned to its 'size' - * boundary and be placed at the start of a RAM bank (which - * should ensure minimal or zero padding due to alignment). - * - * __MTB_RAM_BANK - * Allows MTB Buffer to be placed into specific RAM bank. When - * this is not defined, the "default" (first if there are - * several) RAM bank is used. - *******************************************************************/ - -// Ignore with none Code Red tools -#if defined (__CODE_RED) - -// Allow MTB to be removed by setting a define (via command line) -#if !defined (__MTB_DISABLE) - - // Allow for MTB buffer size being set by define set via command line - // Otherwise provide small default buffer - #if !defined (__MTB_BUFFER_SIZE) - #define __MTB_BUFFER_SIZE 128 - #endif - - // Check that buffer size requested is >0 bytes in size - #if (__MTB_BUFFER_SIZE > 0) - // Pull in MTB related macros - #include - - // Check if MYTB buffer is to be placed in specific RAM bank - #if defined(__MTB_RAM_BANK) - // Place MTB buffer into explicit bank of RAM - __CR_MTB_BUFFER_EXT(__MTB_BUFFER_SIZE,__MTB_RAM_BANK); - #else - // Place MTB buffer into 'default' bank of RAM - __CR_MTB_BUFFER(__MTB_BUFFER_SIZE); - - #endif // defined(__MTB_RAM_BANK) - - #endif // (__MTB_BUFFER_SIZE > 0) - -#endif // !defined (__MTB_DISABLE) - -#endif // defined (__CODE_RED) - diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/sysinit.c b/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/sysinit.c deleted file mode 100644 index 5a101cb5f8e..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/sysinit.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * @brief Common SystemInit function for LPC54xxx chips - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - - - - #include "chip.h" - - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ -/* Clock rate on the CLKIN pin */ -const uint32_t ExtClockIn = 0; - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - - -/* Set up and initialize hardware prior to call to main */ -void SystemInit(void) -{ -#if defined(__CODE_RED) - extern void(*const g_pfnVectors[]) (void); - SCB->VTOR = (uint32_t) &g_pfnVectors; -#else - //extern void *__Vectors; - //SCB->VTOR = (uint32_t) &isr_vector; - SCB->VTOR = 0x00000000 & 0x3FFFFF80; -#endif - -#if defined(CORE_M4) -#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1 - fpuInit(); -#endif -#endif - -#if !defined(__MULTICORE_M0SLAVE) && !defined(__MULTICORE_M4SLAVE) - /* Chip specific SystemInit */ - Chip_SystemInit(); -#endif -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/SConscript b/bsp/nxp/lpc/lpc5410x/Libraries/SConscript deleted file mode 100644 index 4c815c49b83..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/SConscript +++ /dev/null @@ -1,15 +0,0 @@ -# RT-Thread building script for bridge - -import os -from building import * - -cwd = GetCurrentDir() -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/SConscript b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/SConscript deleted file mode 100644 index 49280b645ee..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/SConscript +++ /dev/null @@ -1,75 +0,0 @@ -# RT-Thread building script for component - -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() - - - -src = Split(''' -chip_common/fpu_init.c -chip_common/iap.c -chip_common/ring_buffer.c -chip_common/rtc_ut.c - -chip_5410x/chip_5410x.c -chip_5410x/clock_5410x.c -chip_5410x/crc_5410x.c -chip_5410x/fifo_5410x.c -chip_5410x/gpiogroup_5410x.c -chip_5410x/gpio_5410x.c -chip_5410x/hw_adc.c -chip_5410x/hw_dmaaltd.c -chip_5410x/hw_dmaaltd_rom_api.c -chip_5410x/hw_i2cmd.c -chip_5410x/hw_i2cmd_rom_api.c -chip_5410x/hw_i2cmond.c -chip_5410x/hw_i2cmond_rom_api.c -chip_5410x/hw_i2csd.c -chip_5410x/hw_i2csd_rom_api.c -chip_5410x/hw_spimd.c -chip_5410x/hw_spimd_rom_api.c -chip_5410x/hw_spisd.c -chip_5410x/hw_spisd_rom_api.c -chip_5410x/hw_uart.c -chip_5410x/iocon_5410x.c -chip_5410x/pinint_5410x.c -chip_5410x/pll_5410x.c -chip_5410x/ritimer_5410x.c -chip_5410x/romapi_adc.c -chip_5410x/romapi_dma.c -chip_5410x/romapi_i2cm.c -chip_5410x/romapi_i2cmon.c -chip_5410x/romapi_i2cs.c -chip_5410x/romapi_spim.c -chip_5410x/romapi_spis.c -chip_5410x/romapi_uart.c -chip_5410x/rtc_5410x.c -chip_5410x/sct_5410x.c -chip_5410x/sct_pwm_5410x.c -chip_5410x/stopwatch_5410x.c -chip_5410x/syscon_5410x.c -chip_5410x/sysinit_5410x.c -chip_5410x/timer_5410x.c -chip_5410x/utick_5410x.c -chip_5410x/wwdt_5410x.c -''') - - -#LIBS = [cwd + '/chip_5410x/power_lib/keil/lib_power'] - -#lpc_chip\chip_5410x\power_lib\lpcxpresso -# add for startup script -if rtconfig.PLATFORM in ['gcc']: - LIBPATH = [cwd + '/chip_5410x/power_lib/lpcxpresso'] - LIBS = ['libpower'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - LIBPATH = [cwd + '/chip_5410x/power_lib/keil'] - LIBS = ['lib_power'] - -CPPPATH = [cwd + '/chip_common',cwd + '/chip_5410x',cwd + '/chip_5410x/config'] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH,LIBS = LIBS,LIBPATH=LIBPATH) - -Return('group') diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/chip.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/chip.h deleted file mode 100644 index 5be7e8618fc..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/chip.h +++ /dev/null @@ -1,240 +0,0 @@ -/* - * @brief LPC5410x basic chip inclusion file - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __CHIP_H_ -#define __CHIP_H_ - -#include "lpc_types.h" -#include "sys_config.h" -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef CORE_M4 -#ifndef CORE_M0PLUS -#error "CORE_M4 or CORE_M0PLUS is not defined for the LPC5410x architecture" -#error "CORE_M4 or CORE_M0PLUS should be defined as part of your compiler define list" -#endif -#endif - -#ifndef CHIP_LPC5410X -#error "The LPC5410X Chip include path is used for this build, but" -#error "CHIP_LPC5410X is not defined!" -#endif - -/** @defgroup PERIPH_5410X_BASE CHIP: LPC5410x Peripheral addresses and register set declarations - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/* Main memory addresses */ -#define LPC_FLASHMEM_BASE 0x00000000UL -#define LPC_SRAM0_BASE 0x02000000UL -#define LPC_SRAM1_BASE 0x02010000UL -#define LPC_ROM_BASE 0x03000000UL -#define LPC_SRAM2_BASE 0x03400000UL -#define LPC_GPIO_PORT_BASE 0x1C000000UL -#define LPC_DMA_BASE 0x1C004000UL -#define LPC_CRC_BASE 0x1C010000UL -#define LPC_SCT_BASE 0x1C018000UL -#define LPC_MBOX_BASE 0x1C02C000UL -#define LPC_ADC_BASE 0x1C034000UL -#define LPC_FIFO_BASE 0x1C038000UL - -/* APB0 peripheral group addresses */ -#define LPC_SYSCON_BASE 0x40000000UL -#define LPC_TIMER2_BASE 0x40004000UL -#define LPC_TIMER3_BASE 0x40008000UL -#define LPC_TIMER4_BASE 0x4000C000UL -#define LPC_GPIO_GROUPINT0_BASE 0x40010000UL -#define LPC_GPIO_GROUPINT1_BASE 0x40014000UL -#define LPC_PIN_INT_BASE 0x40018000UL -#define LPC_IOCON_BASE 0x4001C000UL -#define LPC_UTICK_BASE 0x40020000UL -#define LPC_FMC_BASE 0x40024000UL -#define LPC_PMU_BASE 0x4002C000UL -#define LPC_WWDT_BASE 0x40038000UL -#define LPC_RTC_BASE 0x4003C000UL - -/* APB1 peripheral group addresses */ -#define LPC_ASYNC_SYSCON_BASE 0x40080000UL -#define LPC_USART0_BASE 0x40084000UL -#define LPC_USART1_BASE 0x40088000UL -#define LPC_USART2_BASE 0x4008C000UL -#define LPC_USART3_BASE 0x40090000UL -#define LPC_I2C0_BASE 0x40094000UL -#define LPC_I2C1_BASE 0x40098000UL -#define LPC_I2C2_BASE 0x4009C000UL -#define LPC_SPI0_BASE 0x400A4000UL -#define LPC_SPI1_BASE 0x400A8000UL -#define LPC_TIMER0_BASE 0x400B4000UL -#define LPC_TIMER1_BASE 0x400B8000UL -#define LPC_INMUX_BASE 0x40050000UL -#define LPC_RITIMER_BASE 0x40070000UL -#define LPC_MRT_BASE 0x40074000UL - -/* Main memory register access */ -#define LPC_GPIO ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE) -#define LPC_DMA ((LPC_DMA_T *) LPC_DMA_BASE) -#define LPC_CRC ((LPC_CRC_T *) LPC_CRC_BASE) -#define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE) -#define LPC_MBOX ((LPC_MBOX_T *) LPC_MBOX_BASE) -#define LPC_ADC ((LPC_ADC_T *) LPC_ADC_BASE) -#define LPC_FIFO ((LPC_FIFO_T *) LPC_FIFO_BASE) - -/* APB0 peripheral group register access */ -#define LPC_SYSCON ((LPC_SYSCON_T *) LPC_SYSCON_BASE) -#define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE) -#define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE) -#define LPC_TIMER4 ((LPC_TIMER_T *) LPC_TIMER4_BASE) -#define LPC_GINT ((LPC_GPIOGROUPINT_T *) LPC_GPIO_GROUPINT0_BASE) -#define LPC_PININT ((LPC_PIN_INT_T *) LPC_PIN_INT_BASE) -#define LPC_IOCON ((LPC_IOCON_T *) LPC_IOCON_BASE) -#define LPC_UTICK ((LPC_UTICK_T *) LPC_UTICK_BASE) -#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE) -#define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE) - -/* APB1 peripheral group register access */ -#define LPC_ASYNC_SYSCON ((LPC_ASYNC_SYSCON_T *) LPC_ASYNC_SYSCON_BASE) -#define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE) -#define LPC_USART1 ((LPC_USART_T *) LPC_USART1_BASE) -#define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE) -#define LPC_USART3 ((LPC_USART_T *) LPC_USART3_BASE) -#define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE) -#define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE) -#define LPC_I2C2 ((LPC_I2C_T *) LPC_I2C2_BASE) -#define LPC_SCT0 LPC_SCT -#define LPC_SPI0 ((LPC_SPI_T *) LPC_SPI0_BASE) -#define LPC_SPI1 ((LPC_SPI_T *) LPC_SPI1_BASE) -#define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE) -#define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE) -#define LPC_INMUX ((LPC_INMUX_T *) LPC_INMUX_BASE) -#define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE) -#define LPC_MRT ((LPC_MRT_T *) LPC_MRT_BASE) -#define LPC_PMU ((LPC_PMU_T *) LPC_PMU_BASE) - -/** - * @} - */ - -/** @ingroup CHIP_5410X_DRIVER_OPTIONS - * @{ - */ - -/** - * @brief Clock rate on the CLKIN pin - * This value is defined externally to the chip layer and contains - * the value in Hz for the CLKIN pin for the board. If this pin isn't used, - * this rate can be 0. - */ -extern const uint32_t ExtClockIn; - -/** - * @} - */ - -/* Èç¹û²»ÓÃĪ¸öÎļþ£¬È¥µôÏàÓ¦µÄÎļþ£¬¿ÉÒÔ */ - -/* Include order is important! */ -#include "romapi_5410x.h" -#include "syscon_5410x.h" -#include "cpuctrl_5410x.h" -#include "clock_5410x.h" -#include "pmu_5410x.h" -#include "iocon_5410x.h" -#include "pinint_5410x.h" -#include "inmux_5410x.h" -#include "crc_5410x.h" -#include "gpio_5410x.h" -#include "fifo_5410x.h" -#include "mrt_5410x.h" -#include "wwdt_5410x.h" -#include "sct_5410x.h" -#include "sct_pwm_5410x.h" -#include "rtc_5410x.h" -#include "timer_5410x.h" -#include "ritimer_5410x.h" -#include "utick_5410x.h" -#include "gpiogroup_5410x.h" -#include "mailbox_5410x.h" -#include "fpu_init.h" -#include "power_lib_5410x.h" - -/** @defgroup SUPPORT_5410X_FUNC CHIP: LPC5410x support functions - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/** - * @brief Current system clock rate, mainly used for peripherals in SYSCON - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Update system core and ASYNC syscon clock rate, should be called if the - * system has a clock rate change - * @return None - */ -void SystemCoreClockUpdate(void); - -/** - * @brief Set up and initialize hardware prior to call to main() - * @return None - * @note Chip_SystemInit() is called prior to the application and sets up - * system clocking prior to the application starting. - */ -void Chip_SystemInit(void); - -/** - * @brief Clock and PLL initialization based on the internal oscillator - * @param iFreq : Rate (in Hz) to set the main system clock to - * @return None - */ -void Chip_SetupIrcClocking(uint32_t iFreq); - -/** - * @brief Clock and PLL initialization based on the external clock input - * @param iFreq : Rate (in Hz) to set the main system clock to - * @return None - */ -void Chip_SetupExtInClocking(uint32_t iFreq); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CHIP_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/chip_5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/chip_5410x.c deleted file mode 100644 index 38d5c63ce81..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/chip_5410x.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * @brief LPC5410X Miscellaneous chip specific functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/* System Clock Frequency (Core Clock) */ -uint32_t SystemCoreClock; - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Update system core clock rate, should be called if the system has - a clock rate change */ -void SystemCoreClockUpdate(void) -{ - /* CPU core speed (main clock speed adjusted by system clock divider) */ - SystemCoreClock = Chip_Clock_GetSystemClockRate(); -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/clock_5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/clock_5410x.c deleted file mode 100644 index 2512498fed0..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/clock_5410x.c +++ /dev/null @@ -1,393 +0,0 @@ -/* - * @brief LPC5410X clock driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/* Return asynchronous APB clock rate (no regard for divider) */ -static uint32_t Chip_Clock_GetAsyncSyscon_ClockRate_NoDiv(void) -{ - CHIP_ASYNC_SYSCON_SRC_T src; - uint32_t clkRate; - - src = Chip_Clock_GetAsyncSysconClockSource(); - switch (src) { - case SYSCON_ASYNC_IRC: - clkRate = Chip_Clock_GetIntOscRate(); - break; - - case SYSCON_ASYNC_WDTOSC: - clkRate = Chip_Clock_GetWDTOSCRate(); - break; - - case SYSCON_ASYNC_MAINCLK: - clkRate = Chip_Clock_GetMainClockRate(); - break; - - case SYSCON_ASYNC_CLKIN: - clkRate = Chip_Clock_GetSystemPLLInClockRate(); - break; - - case SYSCON_ASYNC_SYSPLLOUT: - clkRate = Chip_Clock_GetSystemPLLOutClockRate(false); - break; - - default: - clkRate = 0; - break; - } - - return clkRate; -} - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Return main A clock rate */ -uint32_t Chip_Clock_GetMain_A_ClockRate(void) -{ - uint32_t clkRate = 0; - - switch (Chip_Clock_GetMain_A_ClockSource()) { - case SYSCON_MAIN_A_CLKSRC_IRC: - clkRate = Chip_Clock_GetIntOscRate(); - break; - - case SYSCON_MAIN_A_CLKSRCA_CLKIN: - clkRate = Chip_Clock_GetExtClockInRate(); - break; - - case SYSCON_MAIN_A_CLKSRCA_WDTOSC: - clkRate = Chip_Clock_GetWDTOSCRate(); - break; - - default: - clkRate = 0; - break; - } - - return clkRate; -} - -/* Return main B clock rate */ -uint32_t Chip_Clock_GetMain_B_ClockRate(void) -{ - uint32_t clkRate = 0; - - switch (Chip_Clock_GetMain_B_ClockSource()) { - case SYSCON_MAIN_B_CLKSRC_MAINCLKSELA: - clkRate = Chip_Clock_GetMain_A_ClockRate(); - break; - - case SYSCON_MAIN_B_CLKSRC_SYSPLLIN: - clkRate = Chip_Clock_GetSystemPLLInClockRate(); - break; - - case SYSCON_MAIN_B_CLKSRC_SYSPLLOUT: - clkRate = Chip_Clock_GetSystemPLLOutClockRate(false); - break; - - case SYSCON_MAIN_B_CLKSRC_RTC: - clkRate = Chip_Clock_GetRTCOscRate(); - break; - } - - return clkRate; -} - -/* Set CLKOUT clock source and divider */ -void Chip_Clock_SetCLKOUTSource(CHIP_SYSCON_CLKOUTSRC_T src, uint32_t div) -{ - uint32_t srcClk = (uint32_t) src; - - /* Use a clock A source? */ - if (src >= SYSCON_CLKOUTSRCA_OUTPUT) { - /* Not using a CLKOUT A source */ - LPC_SYSCON->CLKOUTSELB = srcClk - SYSCON_CLKOUTSRCA_OUTPUT; - } - else { - /* Using a clock A source, select A and then switch B to A */ - LPC_SYSCON->CLKOUTSELA = srcClk; - LPC_SYSCON->CLKOUTSELB = 0; - } - - LPC_SYSCON->CLKOUTDIV = div; -} - -/* Enable a system or peripheral clock */ -void Chip_Clock_EnablePeriphClock(CHIP_SYSCON_CLOCK_T clk) -{ - uint32_t clkEnab = (uint32_t) clk; - - if (clkEnab >= 128) { - clkEnab = clkEnab - 128; - - LPC_ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1 << clkEnab); - } - else if (clkEnab >= 32) { - LPC_SYSCON->AHBCLKCTRLSET[1] = (1 << (clkEnab - 32)); - } - else { - LPC_SYSCON->AHBCLKCTRLSET[0] = (1 << clkEnab); - } -} - -/* Disable a system or peripheral clock */ -void Chip_Clock_DisablePeriphClock(CHIP_SYSCON_CLOCK_T clk) -{ - uint32_t clkEnab = (uint32_t) clk; - - if (clkEnab >= 128) { - clkEnab = clkEnab - 128; - - LPC_ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1 << clkEnab); - } - else if (clkEnab >= 32) { - LPC_SYSCON->AHBCLKCTRLCLR[1] = (1 << (clkEnab - 32)); - } - else { - LPC_SYSCON->AHBCLKCTRLCLR[0] = (1 << clkEnab); - } -} - -/* Returns the system tick rate as used with the system tick divider */ -uint32_t Chip_Clock_GetSysTickClockRate(void) -{ - uint32_t sysRate, div; - - div = LPC_SYSCON->SYSTICKCLKDIV; - - /* If divider is 0, the system tick clock is disabled */ - if (div == 0) { - sysRate = 0; - } - else { - sysRate = Chip_Clock_GetSystemClockRate() / LPC_SYSCON->SYSTICKCLKDIV; - } - - return sysRate; -} - -/* Return ADC clock rate */ -uint32_t Chip_Clock_GetADCClockRate(void) -{ - uint32_t div, clkRate = 0; - - div = Chip_Clock_GetADCClockDiv(); - - /* ADC clock only enabled if div>0 */ - if (div > 0) { - switch (Chip_Clock_GetADCClockSource()) { - case SYSCON_ADCCLKSELSRC_MAINCLK: - clkRate = Chip_Clock_GetMainClockRate(); - break; - - case SYSCON_ADCCLKSELSRC_SYSPLLOUT: - clkRate = Chip_Clock_GetSystemPLLOutClockRate(false); - break; - - case SYSCON_ADCCLKSELSRC_IRC: - clkRate = Chip_Clock_GetIntOscRate(); - break; - } - - clkRate = clkRate / div; - } - - return clkRate; -} - -/* Set asynchronous APB clock source */ -void Chip_Clock_SetAsyncSysconClockSource(CHIP_ASYNC_SYSCON_SRC_T src) -{ - uint32_t clkSrc = (uint32_t) src; - - if (src >= SYSCON_ASYNC_MAINCLK) { - LPC_ASYNC_SYSCON->ASYNCAPBCLKSELB = (clkSrc - 4); - } - else { - LPC_ASYNC_SYSCON->ASYNCAPBCLKSELA = clkSrc; - LPC_ASYNC_SYSCON->ASYNCAPBCLKSELB = 3; - } -} - -/* Get asynchronous APB clock source */ -CHIP_ASYNC_SYSCON_SRC_T Chip_Clock_GetAsyncSysconClockSource(void) -{ - uint32_t clkSrc; - - if (LPC_ASYNC_SYSCON->ASYNCAPBCLKSELB == 3) { - clkSrc = LPC_ASYNC_SYSCON->ASYNCAPBCLKSELA; - } - else { - clkSrc = 4 + LPC_ASYNC_SYSCON->ASYNCAPBCLKSELB; - } - - return (CHIP_ASYNC_SYSCON_SRC_T) clkSrc; -} - -/* Return asynchronous APB clock rate */ -uint32_t Chip_Clock_GetAsyncSyscon_ClockRate(void) -{ - uint32_t clkRate, div; - - clkRate = Chip_Clock_GetAsyncSyscon_ClockRate_NoDiv(); - div = LPC_ASYNC_SYSCON->ASYNCCLKDIV; - if (div == 0) { - /* Clock is disabled */ - return 0; - } - - return clkRate / div; -} - -/* Set main system clock source */ -void Chip_Clock_SetMainClockSource(CHIP_SYSCON_MAINCLKSRC_T src) -{ - uint32_t clkSrc = (uint32_t) src; - - if (clkSrc >= 4) { - /* Main B source only, not using main A */ - Chip_Clock_SetMain_B_ClockSource((CHIP_SYSCON_MAIN_B_CLKSRC_T) (clkSrc - 4)); - } - else { - /* Select main A clock source and set main B source to use main A */ - Chip_Clock_SetMain_A_ClockSource((CHIP_SYSCON_MAIN_A_CLKSRC_T) clkSrc); - Chip_Clock_SetMain_B_ClockSource(SYSCON_MAIN_B_CLKSRC_MAINCLKSELA); - } -} - -/* Returns the main clock source */ -CHIP_SYSCON_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void) -{ - CHIP_SYSCON_MAIN_B_CLKSRC_T srcB; - uint32_t clkSrc; - - /* Get main B clock source */ - srcB = Chip_Clock_GetMain_B_ClockSource(); - if (srcB == SYSCON_MAIN_B_CLKSRC_MAINCLKSELA) { - /* Using source A, so return source A */ - clkSrc = (uint32_t) Chip_Clock_GetMain_A_ClockSource(); - } - else { - /* Using source B */ - clkSrc = 4 + (uint32_t) srcB; - } - - return (CHIP_SYSCON_MAINCLKSRC_T) clkSrc; -} - -/* Return main clock rate */ -uint32_t Chip_Clock_GetMainClockRate(void) -{ - uint32_t clkRate; - - if (Chip_Clock_GetMain_B_ClockSource() == SYSCON_MAIN_B_CLKSRC_MAINCLKSELA) { - /* Return main A clock rate */ - clkRate = Chip_Clock_GetMain_A_ClockRate(); - } - else { - /* Return main B clock rate */ - clkRate = Chip_Clock_GetMain_B_ClockRate(); - } - - return clkRate; -} - -/* Return system clock rate */ -uint32_t Chip_Clock_GetSystemClockRate(void) -{ - /* No point in checking for divide by 0 */ - return Chip_Clock_GetMainClockRate() / LPC_SYSCON->AHBCLKDIV; -} - -/* Get UART base rate */ -uint32_t Chip_Clock_GetUARTBaseClockRate(void) -{ - uint64_t inclk; - - /* Get clock rate into FRG */ - inclk = (uint64_t) Chip_Clock_GetAsyncSyscon_ClockRate(); - - if (inclk != 0) { - uint32_t mult, divmult; - - divmult = LPC_ASYNC_SYSCON->FRGCTRL & 0xFF; - if ((divmult & 0xFF) == 0xFF) { - /* Fractional part is enabled, get multiplier */ - mult = (divmult >> 8) & 0xFF; - - /* Get fractional error */ - inclk = (inclk * 256) / (uint64_t) (256 + mult); - } - } - - return (uint32_t) inclk; -} - -/* Set UART base rate */ -uint32_t Chip_Clock_SetUARTBaseClockRate(uint32_t rate) -{ - uint32_t div, inclk, err; - uint64_t uart_fra_multiplier; - - /* Input clock into FRG block is the main system cloock */ - inclk = Chip_Clock_GetAsyncSyscon_ClockRate(); - - /* Get integer divider for coarse rate */ - div = inclk / rate; - if (div == 0) { - div = 1; - } - - /* Enable FRG clock */ - Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_FRG); - - err = inclk - (rate * div); - uart_fra_multiplier = (((uint64_t) err + (uint64_t) rate) * 256) / (uint64_t) (rate * div); - - /* Enable fractional divider and set multiplier */ - LPC_ASYNC_SYSCON->FRGCTRL = 0xFF | (uart_fra_multiplier << 8); - - return Chip_Clock_GetUARTBaseClockRate(); -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/clock_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/clock_5410x.h deleted file mode 100644 index 31b47539e91..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/clock_5410x.h +++ /dev/null @@ -1,473 +0,0 @@ -/* - * @brief LPC5410X clock driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __CLOCK_5410X_H_ -#define __CLOCK_5410X_H_ - -#include "pll_5410x.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup CLOCK_5410X CHIP: LPC5410X Clock Driver - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/* Internal oscillator frequency */ -#define SYSCON_IRC_FREQ (12000000) -#define SYSCON_WDTOSC_FREQ (500000) -#define SYSCON_RTC_FREQ (32768) - -/** - * @brief Returns the internal oscillator (IRC) clock rate - * @return internal oscillator (IRC) clock rate - */ -STATIC INLINE uint32_t Chip_Clock_GetIntOscRate(void) -{ - return SYSCON_IRC_FREQ; -} - -/** - * @brief Returns the external clock input rate - * @return External clock input rate - */ -STATIC INLINE uint32_t Chip_Clock_GetExtClockInRate(void) -{ - return ExtClockIn; -} - -/** - * @brief Returns the RTC clock rate - * @return RTC oscillator clock rate in Hz - */ -STATIC INLINE uint32_t Chip_Clock_GetRTCOscRate(void) -{ - return SYSCON_RTC_FREQ; -} - -/** - * @brief Return estimated watchdog oscillator rate - * @return Estimated watchdog oscillator rate - * @note This rate is accurate to plus or minus 40%. - */ -STATIC INLINE uint32_t Chip_Clock_GetWDTOSCRate(void) -{ - return SYSCON_WDTOSC_FREQ; -} - -/** - * Clock source selections for only the main A system clock. The main A system - * clock is used as an input into the main B system clock selector. Main clock A - * only needs to be setup if the main clock A input is used in the main clock - * system selector. - */ -typedef enum { - SYSCON_MAIN_A_CLKSRC_IRC = 0, /*!< Internal oscillator */ - SYSCON_MAIN_A_CLKSRCA_CLKIN, /*!< Crystal (main) oscillator in */ - SYSCON_MAIN_A_CLKSRCA_WDTOSC, /*!< Watchdog oscillator rate */ -} CHIP_SYSCON_MAIN_A_CLKSRC_T; - -/** - * @brief Set main A system clock source - * @param src : Clock source for main A - * @return Nothing - * @note This function only needs to be setup if main clock A will be - * selected in the Chip_Clock_GetMain_B_ClockRate() function. - */ -STATIC INLINE void Chip_Clock_SetMain_A_ClockSource(CHIP_SYSCON_MAIN_A_CLKSRC_T src) -{ - LPC_SYSCON->MAINCLKSELA = (uint32_t) src; -} - -/** - * @brief Returns the main A clock source - * @return Returns which clock is used for the main A - */ -STATIC INLINE CHIP_SYSCON_MAIN_A_CLKSRC_T Chip_Clock_GetMain_A_ClockSource(void) -{ - return (CHIP_SYSCON_MAIN_A_CLKSRC_T) (LPC_SYSCON->MAINCLKSELA); -} - -/** - * @brief Return main A clock rate - * @return main A clock rate in Hz - */ -uint32_t Chip_Clock_GetMain_A_ClockRate(void); - -/** - * Clock sources for only main B system clock - */ -typedef enum { - SYSCON_MAIN_B_CLKSRC_MAINCLKSELA = 0, /*!< main clock A */ - SYSCON_MAIN_B_CLKSRC_SYSPLLIN, /*!< System PLL input */ - SYSCON_MAIN_B_CLKSRC_SYSPLLOUT, /*!< System PLL output */ - SYSCON_MAIN_B_CLKSRC_RTC, /*!< RTC oscillator 32KHz output */ -} CHIP_SYSCON_MAIN_B_CLKSRC_T; - -/** - * @brief Set main B system clock source - * @param src : Clock source for main B - * @return Nothing - */ -STATIC INLINE void Chip_Clock_SetMain_B_ClockSource(CHIP_SYSCON_MAIN_B_CLKSRC_T src) -{ - LPC_SYSCON->MAINCLKSELB = (uint32_t) src; -} - -/** - * @brief Returns the main B clock source - * @return Returns which clock is used for the main B - */ -STATIC INLINE CHIP_SYSCON_MAIN_B_CLKSRC_T Chip_Clock_GetMain_B_ClockSource(void) -{ - return (CHIP_SYSCON_MAIN_B_CLKSRC_T) (LPC_SYSCON->MAINCLKSELB); -} - -/** - * @brief Return main B clock rate - * @return main B clock rate - */ -uint32_t Chip_Clock_GetMain_B_ClockRate(void); - -/** - * Clock sources for CLKOUT - */ -typedef enum { - SYSCON_CLKOUTSRC_MAINCLK = 0, /*!< Main system clock for CLKOUT */ - SYSCON_CLKOUTSRC_CLKIN, /*!< CLKIN for CLKOUT */ - SYSCON_CLKOUTSRC_WDTOSC, /*!< Watchdog oscillator for CLKOUT */ - SYSCON_CLKOUTSRC_IRC, /*!< Internal oscillator for CLKOUT */ - SYSCON_CLKOUTSRCA_OUTPUT, /*!< clkoutA output route to input of clkoutB */ - SYSCON_CLKOUTSRC_RTC = 7 /*!< RTC oscillator 32KHz for CLKOUT */ -} CHIP_SYSCON_CLKOUTSRC_T; - -/** - * @brief Set CLKOUT clock source and divider - * @param src : Clock source for CLKOUT - * @param div : divider for CLKOUT clock - * @return Nothing - * @note Use 0 to disable, or a divider value of 1 to 255. The CLKOUT clock - * rate is the clock source divided by the divider. This function will - * also toggle the clock source update register to update the clock - * source. - */ -void Chip_Clock_SetCLKOUTSource(CHIP_SYSCON_CLKOUTSRC_T src, uint32_t div); - -/** - * System and peripheral clocks enum - */ -typedef enum CHIP_SYSCON_CLOCK { - /* Peripheral clock enables for SYSAHBCLKCTRL0 */ - SYSCON_CLOCK_ROM = 1, /*!< ROM clock */ - SYSCON_CLOCK_SRAM1 = 3, /*!< SRAM1 clock */ - SYSCON_CLOCK_SRAM2, /*!< SRAM2 clock */ - SYSCON_CLOCK_FLASH = 7, /*!< FLASH controller clock */ - SYSCON_CLOCK_FMC, /*!< FMC clock */ - SYSCON_CLOCK_INPUTMUX = 11, /*!< Input mux clock */ - SYSCON_CLOCK_IOCON = 13, /*!< IOCON clock */ - SYSCON_CLOCK_GPIO0, /*!< GPIO0 clock */ - SYSCON_CLOCK_GPIO1, /*!< GPIO1 clock */ - SYSCON_CLOCK_PINT = 18, /*!< PININT clock */ - SYSCON_CLOCK_GINT, /*!< grouped pin interrupt block clock */ - SYSCON_CLOCK_DMA, /*!< DMA clock */ - SYSCON_CLOCK_CRC, /*!< CRC clock */ - SYSCON_CLOCK_WWDT, /*!< WDT clock */ - SYSCON_CLOCK_RTC, /*!< RTC clock */ - SYSCON_CLOCK_MAILBOX = 26, /*!< Mailbox clock */ - SYSCON_CLOCK_ADC0, /*!< ADC0 clock */ - - /* Peripheral clock enables for SYSAHBCLKCTRL1 */ - SYSCON_CLOCK_MRT = 32, /*!< multi-rate timer clock */ - SYSCON_CLOCK_RIT, /*!< Repetitive interval timer clock */ - SYSCON_CLOCK_SCT0, /*!< SCT0 clock */ - SYSCON_CLOCK_FIFO = 32 + 9, /*!< System FIFO clock */ - SYSCON_CLOCK_UTICK, /*!< UTICK clock */ - SYSCON_CLOCK_TIMER2 = 32 + 22, /*!< TIMER2 clock */ - SYSCON_CLOCK_TIMER3 = 32 + 26, /*!< TIMER3 clock */ - SYSCON_CLOCK_TIMER4, /*!< TIMER4 clock */ - - /* Peripheral clock enables for ASYNCAPBCLKCTRLCLR */ - SYSCON_CLOCK_USART0 = 128 + 1, /*!< USART0 clock */ - SYSCON_CLOCK_USART1, /*!< USART1 clock */ - SYSCON_CLOCK_USART2, /*!< USART2 clock */ - SYSCON_CLOCK_USART3, /*!< USART3 clock */ - SYSCON_CLOCK_I2C0, /*!< I2C0 clock */ - SYSCON_CLOCK_I2C1, /*!< I2C1 clock */ - SYSCON_CLOCK_I2C2, /*!< I2C2 clock */ - SYSCON_CLOCK_SPI0 = 128 + 9, /*!< SPI0 clock */ - SYSCON_CLOCK_SPI1, /*!< SPI1 clock */ - SYSCON_CLOCK_TIMER0 = 128 + 13, /*!< TIMER0 clock */ - SYSCON_CLOCK_TIMER1, /*!< TIMER1 clock */ - SYSCON_CLOCK_FRG /*!< FRG clock */ -} CHIP_SYSCON_CLOCK_T; - -/** - * @brief Enable a system or peripheral clock - * @param clk : Clock to enable - * @return Nothing - */ -void Chip_Clock_EnablePeriphClock(CHIP_SYSCON_CLOCK_T clk); - -/** - * @brief Disable a system or peripheral clock - * @param clk : Clock to disable - * @return Nothing - */ -void Chip_Clock_DisablePeriphClock(CHIP_SYSCON_CLOCK_T clk); - -/** - * @brief Set system tick clock divider (external CLKIN as SYSTICK reference only) - * @param div : divider for system clock - * @return Nothing - * @note Use 0 to disable, or a divider value of 1 to 255. The system tick - * rate is the external CLKIN rate divided by this value. The extern CLKIN pin - * signal, divided by the SYSTICKCLKDIV divider, is selected by clearing - * CLKSOURCE bit 2 in the System Tick CSR register. The core clock must be at least - * 2.5 times faster than the reference system tick clock otherwise the count - * values are unpredictable. - */ -STATIC INLINE void Chip_Clock_SetSysTickClockDiv(uint32_t div) -{ - LPC_SYSCON->SYSTICKCLKDIV = div; -} - -/** - * @brief Returns system tick clock divider - * @return system tick clock divider - */ -STATIC INLINE uint32_t Chip_Clock_GetSysTickClockDiv(void) -{ - return LPC_SYSCON->SYSTICKCLKDIV; -} - -/** - * @brief Returns the system tick rate as used with the system tick divider - * @return the system tick rate - */ -uint32_t Chip_Clock_GetSysTickClockRate(void); - -/** - * @brief Set system clock divider - * @param div : divider for system clock - * @return Nothing - * @note Use 0 to disable, or a divider value of 1 to 255. The system clock - * rate is the main system clock divided by this value. - */ -STATIC INLINE void Chip_Clock_SetSysClockDiv(uint32_t div) -{ - LPC_SYSCON->AHBCLKDIV = div; -} - -/** - * @brief Set system tick clock divider - * @param div : divider for system clock - * @return Nothing - * @note Use 0 to disable, or a divider value of 1 to 255. The system tick - * rate is the main system clock divided by this value. Use caution when using - * the CMSIS SysTick_Config() functions as they typically use SystemCoreClock - * for setup. - */ -STATIC INLINE void Chip_Clock_SetADCClockDiv(uint32_t div) -{ - LPC_SYSCON->ADCCLKDIV = div; -} - -/** - * @brief Returns ADC clock divider - * @return ADC clock divider, 0 = disabled - */ -STATIC INLINE uint32_t Chip_Clock_GetADCClockDiv(void) -{ - return LPC_SYSCON->ADCCLKDIV; -} - -/** - * Clock sources for ADC clock source select - */ -typedef enum { - SYSCON_ADCCLKSELSRC_MAINCLK = 0, /*!< Main clock */ - SYSCON_ADCCLKSELSRC_SYSPLLOUT, /*!< PLL output */ - SYSCON_ADCCLKSELSRC_IRC /*!< Internal oscillator */ -} CHIP_SYSCON_ADCCLKSELSRC_T; - -/** - * @brief Set the ADC clock source - * @param src : ADC clock source - * @return Nothing - */ -STATIC INLINE void Chip_Clock_SetADCClockSource(CHIP_SYSCON_ADCCLKSELSRC_T src) -{ - LPC_SYSCON->ADCCLKSEL = (uint32_t) src; -} - -/** - * @brief Returns the ADC clock source - * @return Returns which clock is used for the ADC clock source - */ -STATIC INLINE CHIP_SYSCON_ADCCLKSELSRC_T Chip_Clock_GetADCClockSource(void) -{ - return (CHIP_SYSCON_ADCCLKSELSRC_T) (LPC_SYSCON->ADCCLKSEL); -} - -/** - * @brief Return ADC clock rate - * @return ADC clock rate - */ -uint32_t Chip_Clock_GetADCClockRate(void); - -/** - * @brief Enable the RTC 32KHz output - * @return Nothing - * @note This clock can be used for the main clock directly, but - * do not use this clock with the system PLL. - */ -STATIC INLINE void Chip_Clock_EnableRTCOsc(void) -{ - LPC_SYSCON->RTCOSCCTRL = 1; -} - -/** - * @brief Disable the RTC 32KHz output - * @return Nothing - */ -STATIC INLINE void Chip_Clock_DisableRTCOsc(void) -{ - LPC_SYSCON->RTCOSCCTRL = 0; -} - -/** - * Clock source selections for the asynchronous APB clock - */ -typedef enum { - SYSCON_ASYNC_IRC = 0, /*!< IRC input */ - SYSCON_ASYNC_WDTOSC, /*!< Watchdog oscillator */ - SYSCON_ASYNC_MAINCLK = 4, /*!< Main clock */ - SYSCON_ASYNC_CLKIN, /*!< external CLK input */ - SYSCON_ASYNC_SYSPLLOUT /*!< System PLL output */ -} CHIP_ASYNC_SYSCON_SRC_T; - -/** - * @brief Set asynchronous APB clock source - * @param src : Clock source for asynchronous APB clock - * @return Nothing - */ -void Chip_Clock_SetAsyncSysconClockSource(CHIP_ASYNC_SYSCON_SRC_T src); - -/** - * @brief Get asynchronous APB clock source - * @return Clock source for asynchronous APB clock - */ -CHIP_ASYNC_SYSCON_SRC_T Chip_Clock_GetAsyncSysconClockSource(void); - -/** - * @brief Return asynchronous APB clock rate - * @return Asynchronous APB clock rate - * @note Includes adjustments by Async clock divider (ASYNCCLKDIV). - */ -uint32_t Chip_Clock_GetAsyncSyscon_ClockRate(void); - -/** - * @brief Set UART divider clock - * @param div : divider for UART clock - * @return Nothing - * @note Use 0 to disable, or a divider value of 1 to 255. The UART clock - * rate is the main system clock divided by this value. - */ -STATIC INLINE void Chip_Clock_SetAsyncSysconClockDiv(uint32_t div) -{ - LPC_ASYNC_SYSCON->ASYNCCLKDIV = div; -} - -/** - * Clock sources for main system clock. This is a mix of both main clock A - * and B selections. - */ -typedef enum { - SYSCON_MAINCLKSRC_IRC = 0, /*!< Internal oscillator */ - SYSCON_MAINCLKSRC_CLKIN, /*!< Crystal (main) oscillator in */ - SYSCON_MAINCLKSRC_WDTOSC, /*!< Watchdog oscillator rate */ - SYSCON_MAINCLKSRC_PLLIN = 5, /*!< System PLL input */ - SYSCON_MAINCLKSRC_PLLOUT, /*!< System PLL output */ - SYSCON_MAINCLKSRC_RTC /*!< RTC oscillator 32KHz output */ -} CHIP_SYSCON_MAINCLKSRC_T; - -/** - * @brief Set main system clock source - * @param src : Clock source for main system - * @return Nothing - */ -void Chip_Clock_SetMainClockSource(CHIP_SYSCON_MAINCLKSRC_T src); - -/** - * @brief Get main system clock source - * @return Clock source for main system - * @note - */ -CHIP_SYSCON_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void); - -/** - * @brief Return main clock rate - * @return main clock rate - */ -uint32_t Chip_Clock_GetMainClockRate(void); - -/** - * @brief Return system clock rate - * @return system clock rate - * @note This is the main clock rate divided by AHBCLKDIV. - */ -uint32_t Chip_Clock_GetSystemClockRate(void); - -/** - * @brief Get UART base clock rate - * @return UART base clock rate - */ -uint32_t Chip_Clock_GetUARTBaseClockRate(void); - -/** - * @brief Get UART base clock rate using FRG - * @return Actual UART base clock rate - * @note It's recommended to set a base rate at least 16x the - * expected maximum UART transfer bit rate. - */ -uint32_t Chip_Clock_SetUARTBaseClockRate(uint32_t rate); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CLOCK_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/cmd.bat b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/cmd.bat deleted file mode 100644 index 602c0a70246..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/cmd.bat +++ /dev/null @@ -1 +0,0 @@ -dir *.c >C:\Users\Administrator\Desktop\c.txt \ No newline at end of file diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/cmsis.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/cmsis.h deleted file mode 100644 index bd1047d3adb..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/cmsis.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * @brief LPC5410x selective CMSIS inclusion file - * - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __CMSIS_H_ -#define __CMSIS_H_ - -#include "lpc_types.h" -#include "sys_config.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* Select correct CMSIS include file based on CORE_* definition */ -#if defined(CORE_M4) -#include "cmsis_5410x.h" -typedef LPC5410X_IRQn_Type IRQn_Type; -#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ -#elif defined(CORE_M0PLUS) -#include "cmsis_5410x_m0.h" -typedef LPC5410X_M0_IRQn_Type IRQn_Type; -#include "core_cm0plus.h" /*!< Cortex-M0 Plus processor and core peripherals */ -#else -#error "No CORE_* definition is defined" -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* __CMSIS_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/config.xml b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/config.xml deleted file mode 100644 index 7e3976331d7..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/config.xml +++ /dev/null @@ -1,48 +0,0 @@ - - - - - - - - - - - - - - - - - diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/config/cmsis_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/config/cmsis_5410x.h deleted file mode 100644 index a32c7c51657..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/config/cmsis_5410x.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - * @brief Basic CMSIS include file for LPC5410x M4 core - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __CMSIS_5410X_H_ -#define __CMSIS_5410X_H_ - -#include "lpc_types.h" -#include "sys_config.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup CMSIS_5410X_M4 CHIP: LPC5410X M4 core CMSIS include file - * @ingroup CHIP_5410X_CMSIS_DRIVERS - * @{ - */ - -#if defined(__ARMCC_VERSION) -// Kill warning "#pragma push with no matching #pragma pop" - #pragma diag_suppress 2525 - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) -/* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) -// #pragma push // FIXME not usable for IAR - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ - -#if !defined(CORE_M4) -#error "CORE_M4 is not defined" -#endif - -/** @defgroup CMSIS_5410X_M4_IRQ CHIP_5410X: LPC5410X M4 core peripheral interrupt numbers - * @{ - */ - -typedef enum { - /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ - BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ - UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ - - /****** LPC5410X Specific Interrupt Numbers ********************************************************/ - WDT_IRQn = 0, /*!< WWDT */ - BOD_IRQn = 1, /*!< BOD */ - Reserved2_IRQn = 2, /*!< Reserved Interrupt */ - DMA_IRQn = 3, /*!< DMA */ - GINT0_IRQn = 4, /*!< GINT0 */ - PIN_INT0_IRQn = 5, /*!< PININT0 */ - PIN_INT1_IRQn = 6, /*!< PININT1 */ - PIN_INT2_IRQn = 7, /*!< PININT2 */ - PIN_INT3_IRQn = 8, /*!< PININT3 */ - UTICK_IRQn = 9, /*!< Micro-tick Timer interrupt */ - MRT_IRQn = 10, /*!< Multi-rate timer interrupt */ - CT32B0_IRQn = 11, /*!< CTMR0 */ - CT32B1_IRQn = 12, /*!< CTMR1 */ - CT32B2_IRQn = 13, /*!< CTMR2 */ - CT32B3_IRQn = 14, /*!< CTMR3 */ - CT32B4_IRQn = 15, /*!< CTMR4 */ - SCT0_IRQn = 16, /*!< SCT */ - UART0_IRQn = 17, /*!< UART0 */ - UART1_IRQn = 18, /*!< UART1 */ - UART2_IRQn = 19, /*!< UART2 */ - UART3_IRQn = 20, /*!< UART3 */ - I2C0_IRQn = 21, /*!< I2C0 */ - I2C1_IRQn = 22, /*!< I2C1 */ - I2C2_IRQn = 23, /*!< I2C2 */ - SPI0_IRQn = 24, /*!< SPI0 */ - SPI1_IRQn = 25, /*!< SPI1 */ - ADC_SEQA_IRQn = 26, /*!< ADC0 sequence A completion */ - ADC_SEQB_IRQn = 27, /*!< ADC0 sequence B completion */ - ADC_THCMP_IRQn = 28, /*!< ADC0 threshold compare and error */ - RTC_IRQn = 29, /*!< RTC alarm and wake-up interrupts */ - Reserved30_IRQn = 30, /*!< Reserved Interrupt */ - MAILBOX_IRQn = 31, /*!< Mailbox */ - GINT1_IRQn = 32, /*!< GINT1 */ - PIN_INT4_IRQn = 33, /*!< External Interrupt 4 */ - PIN_INT5_IRQn = 34, /*!< External Interrupt 5 */ - PIN_INT6_IRQn = 35, /*!< External Interrupt 6 */ - PIN_INT7_IRQn = 36, /*!< External Interrupt 7 */ - Reserved37_IRQn = 37, /*!< Reserved Interrupt */ - Reserved38_IRQn = 38, /*!< Reserved Interrupt */ - Reserved39_IRQn = 39, /*!< Reserved Interrupt */ - RIT_IRQn = 40, /*!< Repetitive Interrupt Timer */ - Reserved41_IRQn = 41, /*!< Reserved Interrupt */ - Reserved42_IRQn = 42, /*!< Reserved Interrupt */ - Reserved43_IRQn = 43, /*!< Reserved Interrupt */ - Reserved44_IRQn = 44, /*!< Reserved Interrupt */ -} LPC5410X_IRQn_Type; - -/** - * @} - */ - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/** @defgroup CMSIS_5410X_M4_COMMON CHIP: LPC5410X M4 core Cortex CMSIS definitions - * @{ - */ - -/* Configuration of the Cortex-M4 Processor and Core Peripherals */ -#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CMSIS_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/config/cmsis_5410x_m0.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/config/cmsis_5410x_m0.h deleted file mode 100644 index 4fa21b22d4e..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/config/cmsis_5410x_m0.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * @brief Basic CMSIS include file for LPC5410x M0+ core - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __CMSIS_5410X_M0_H_ -#define __CMSIS_5410X_M0_H_ - -#include "lpc_types.h" -#include "sys_config.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup CMSIS_5410X_M0 CHIP: LPC5410X M0 core CMSIS include file - * @ingroup CHIP_5410X_CMSIS_DRIVERS - * @{ - */ - -#if defined(__ARMCC_VERSION) -// Kill warning "#pragma push with no matching #pragma pop" - #pragma diag_suppress 2525 - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) -/* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) -// #pragma push // FIXME not usable for IAR - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ - -#if !defined(CORE_M0PLUS) -#error "CORE_M0PLUS is not defined" -#endif - -/** @defgroup CMSIS_5410X_M0_IRQ CHIP_5410X: LPC5410X M0 core peripheral interrupt numbers - * @{ - */ - -typedef enum { - /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ - - /****** LPC5410X Specific Interrupt Numbers ********************************************************/ - WDT_IRQn = 0, /*!< WWDT */ - BOD_IRQn = 1, /*!< BOD */ - Reserved2_IRQn = 2, /*!< Reserved Interrupt */ - DMA_IRQn = 3, /*!< DMA */ - GINT0_IRQn = 4, /*!< GINT0 */ - PIN_INT0_IRQn = 5, /*!< PININT0 */ - PIN_INT1_IRQn = 6, /*!< PININT1 */ - PIN_INT2_IRQn = 7, /*!< PININT2 */ - PIN_INT3_IRQn = 8, /*!< PININT3 */ - UTICK_IRQn = 9, /*!< Micro-tick Timer interrupt */ - MRT_IRQn = 10, /*!< Multi-rate timer interrupt */ - CT32B0_IRQn = 11, /*!< CTMR0 */ - CT32B1_IRQn = 12, /*!< CTMR1 */ - CT32B2_IRQn = 13, /*!< CTMR2 */ - CT32B3_IRQn = 14, /*!< CTMR3 */ - CT32B4_IRQn = 15, /*!< CTMR4 */ - SCT0_IRQn = 16, /*!< SCT */ - UART0_IRQn = 17, /*!< UART0 */ - UART1_IRQn = 18, /*!< UART1 */ - UART2_IRQn = 19, /*!< UART2 */ - UART3_IRQn = 20, /*!< UART3 */ - I2C0_IRQn = 21, /*!< I2C0 */ - I2C1_IRQn = 22, /*!< I2C1 */ - I2C2_IRQn = 23, /*!< I2C2 */ - SPI0_IRQn = 24, /*!< SPI0 */ - SPI1_IRQn = 25, /*!< SPI1 */ - ADC_SEQA_IRQn = 26, /*!< ADC0 sequence A completion */ - ADC_SEQB_IRQn = 27, /*!< ADC0 sequence B completion */ - ADC_THCMP_IRQn = 28, /*!< ADC0 threshold compare and error */ - RTC_IRQn = 29, /*!< RTC alarm and wake-up interrupts */ - Reserved30_IRQn = 30, /*!< Reserved Interrupt */ - MAILBOX_IRQn = 31, /*!< Mailbox */ -} LPC5410X_M0_IRQn_Type; - -/** - * @} - */ - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/** @defgroup CMSIS_5410X_M0_COMMON CHIP: LPC5410X M0 core Cortex CMSIS definitions - * @{ - */ - -/* Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define __CM0PLUS_REV 0x0001 /*!< Cortex-M0PLUS Core Revision */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __VTOR_PRESENT 1 - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CMSIS_5410X_M0_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/config/sys_config.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/config/sys_config.h deleted file mode 100644 index 0500ef091c3..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/config/sys_config.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __SYS_CONFIG_H_ -#define __SYS_CONFIG_H_ - -/* Build for LPC5410X chip family */ -#define CHIP_LPC5410X - -/* Define ROMDRIVERSV2_PRESENT to enable v2 driver support in ROM. For LPC54xxx - devices with boot ROM version 17.2 and later, this should be defined. - For earlier versions, this should not be defined. If the definitions is - not defined, the same v2 drivers will be used, but will use a version that - is located in FLASH instead. */ -// #define ROMDRIVERSV2_PRESENT - -#endif /* __SYS_CONFIG_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/cpuctrl_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/cpuctrl_5410x.h deleted file mode 100644 index 0e0dbd15c7c..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/cpuctrl_5410x.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * @brief LPC5410X CPU multi-core support driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __CPUCTRL_5410X_H_ -#define __CPUCTRL_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup CPUCTRL_5410X CHIP: LPC5410X CPU multi-core support driver - * @ingroup CHIP_5410X_DRIVERS - * This driver helps with determine which MCU core the software is running, - * whether the MCU core is in master or slave mode, and provides functions - * for master and slave core control.
- * - * The functions for the driver are provided as part of the - * @ref POWER_LIBRARY_5410X library. For more information on using the - * LPC5410x LPCopen package with multi-core, see @ref CHIP_5410X_MULTICORE
. - * @{ - */ - -/** - * @brief Determine which MCU this code is running on - * @return true if executing on the CM4, or false if executing on the CM0+ - */ -STATIC INLINE bool Chip_CPU_IsM4Core(void) { - /* M4 core is designated by values 0xC24 on bits 15..4 */ - if (((SCB->CPUID >> 4) & 0xFFF) == 0xC24) { - return true; - } - - return false; -} - -/** - * @brief Determine if this core is a slave or master - * @return true if this MCU is operating as the master, or false if operating as a slave - */ -bool Chip_CPU_IsMasterCore(void); - -/** - * @brief Setup M0+ boot and reset M0+ core - * @param coentry : Pointer to boot entry point for M0+ core - * @param costackptr : Pointer to where stack should be located for M0+ core - * @return Nothing - * @note Will setup boot stack and entry point, enable M0+ clock and then - * reset M0+ core. - */ -void Chip_CPU_CM0Boot(uint32_t *coentry, uint32_t *costackptr); - -/** - * @brief Setup M4 boot and reset M4 core - * @param coentry : Pointer to boot entry point for M4 core - * @param costackptr : Pointer to where stack should be located for M4 core - * @return Nothing - * @note Will setup boot stack and entry point, enable M4 clock and then - * reset M0+ core. - */ -void Chip_CPU_CM4Boot(uint32_t *coentry, uint32_t *costackptr); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CPUCTRL_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/crc_5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/crc_5410x.c deleted file mode 100644 index a4305a481a0..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/crc_5410x.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * @brief LPC5410X Cyclic Redundancy Check (CRC) Engine driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Initialize CRC engine */ -void Chip_CRC_Init(void) -{ - Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_CRC); - Chip_SYSCON_PeriphReset(RESET_CRC); -} - -/* De-initialize CRC engine */ -void Chip_CRC_Deinit(void) -{ - Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_CRC); -} - -/* Sets up the CRC engine with defaults based on the polynomial to be used */ -void Chip_CRC_UseDefaultConfig(CRC_POLY_T poly) -{ - switch (poly) { - case CRC_POLY_CRC16: - Chip_CRC_UseCRC16(); - break; - - case CRC_POLY_CRC32: - Chip_CRC_UseCRC32(); - break; - - case CRC_POLY_CCITT: - default: - Chip_CRC_UseCCITT(); - break; - } -} - -/* configure CRC engine and compute CCITT checksum from 8-bit data */ -uint32_t Chip_CRC_CRC8(const uint8_t *data, uint32_t bytes) -{ - Chip_CRC_UseCCITT(); - while (bytes > 0) { - Chip_CRC_Write8(*data); - data++; - bytes--; - } - - return Chip_CRC_Sum(); -} - -/* Convenience function for computing a standard CRC16 checksum from 16-bit data block */ -uint32_t Chip_CRC_CRC16(const uint16_t *data, uint32_t hwords) -{ - Chip_CRC_UseCRC16(); - while (hwords > 0) { - Chip_CRC_Write16(*data); - data++; - hwords--; - } - - return Chip_CRC_Sum(); -} - -/* Convenience function for computing a standard CRC32 checksum from 32-bit data block */ -uint32_t Chip_CRC_CRC32(const uint32_t *data, uint32_t words) -{ - Chip_CRC_UseCRC32(); - while (words > 0) { - Chip_CRC_Write32(*data); - data++; - words--; - } - - return Chip_CRC_Sum(); -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/crc_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/crc_5410x.h deleted file mode 100644 index cbf5ac93b55..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/crc_5410x.h +++ /dev/null @@ -1,262 +0,0 @@ -/* - * @brief LPC5410X Cyclic Redundancy Check (CRC) Engine driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __CRC_5410X_H_ -#define __CRC_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup CRC_5410X CHIP: LPC5410X Cyclic Redundancy Check Engine driver - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/** - * @brief CRC register block structure - */ -typedef struct { /*!< CRC Structure */ - __IO uint32_t MODE; /*!< CRC Mode Register */ - __IO uint32_t SEED; /*!< CRC SEED Register */ - union { - __I uint32_t SUM; /*!< CRC Checksum Register. */ - __O uint32_t WRDATA32; /*!< CRC Data Register: write size 32-bit*/ - __O uint16_t WRDATA16; /*!< CRC Data Register: write size 16-bit*/ - __O uint8_t WRDATA8; /*!< CRC Data Register: write size 8-bit*/ - }; - -} LPC_CRC_T; - -/* - * @brief CRC MODE register description - */ -#define CRC_MODE_POLY_BITMASK ((0x03)) /** CRC polynomial Bit mask */ -#define CRC_MODE_POLY_CCITT (0x00) /** Select CRC-CCITT polynomial */ -#define CRC_MODE_POLY_CRC16 (0x01) /** Select CRC-16 polynomial */ -#define CRC_MODE_POLY_CRC32 (0x02) /** Select CRC-32 polynomial */ -#define CRC_MODE_WRDATA_BITMASK (0x03 << 2) /** CRC WR_Data Config Bit mask */ -#define CRC_MODE_WRDATA_BIT_RVS (1 << 2) /** Select Bit order reverse for WR_DATA (per byte) */ -#define CRC_MODE_WRDATA_CMPL (1 << 3) /** Select One's complement for WR_DATA */ -#define CRC_MODE_SUM_BITMASK (0x03 << 4) /** CRC Sum Config Bit mask */ -#define CRC_MODE_SUM_BIT_RVS (1 << 4) /** Select Bit order reverse for CRC_SUM */ -#define CRC_MODE_SUM_CMPL (1 << 5) /** Select One's complement for CRC_SUM */ - -#define MODE_CFG_CCITT (0x00) /** Pre-defined mode word for default CCITT setup */ -#define MODE_CFG_CRC16 (0x15) /** Pre-defined mode word for default CRC16 setup */ -#define MODE_CFG_CRC32 (0x36) /** Pre-defined mode word for default CRC32 setup */ - -#define CRC_SEED_CCITT (0x0000FFFF)/** Initial seed value for CCITT mode */ -#define CRC_SEED_CRC16 (0x00000000)/** Initial seed value for CRC16 mode */ -#define CRC_SEED_CRC32 (0xFFFFFFFF)/** Initial seed value for CRC32 mode */ - -/** - * @brief CRC polynomial - */ -typedef enum IP_CRC_001_POLY { - CRC_POLY_CCITT = CRC_MODE_POLY_CCITT, /**< CRC-CCIT polynomial */ - CRC_POLY_CRC16 = CRC_MODE_POLY_CRC16, /**< CRC-16 polynomial */ - CRC_POLY_CRC32 = CRC_MODE_POLY_CRC32, /**< CRC-32 polynomial */ - CRC_POLY_LAST, -} CRC_POLY_T; - -/** - * @brief Initializes the CRC Engine - * @return Nothing - */ -void Chip_CRC_Init(void); - -/** - * @brief Deinitializes the CRC Engine - * @return Nothing - */ -void Chip_CRC_Deinit(void); - -/** - * @brief Set the polynomial used for the CRC calculation - * @param poly : The enumerated polynomial to be used - * @param flags : An Or'ed value of flags that setup the mode - * @return Nothing - * @note Flags for setting up the mode word include CRC_MODE_WRDATA_BIT_RVS, - * CRC_MODE_WRDATA_CMPL, CRC_MODE_SUM_BIT_RVS, and CRC_MODE_SUM_CMPL. - */ -STATIC INLINE void Chip_CRC_SetPoly(CRC_POLY_T poly, uint32_t flags) -{ - LPC_CRC->MODE = (uint32_t) poly | flags; -} - -/** - * @brief Sets up the CRC engine for CRC16 mode - * @return Nothing - */ -STATIC INLINE void Chip_CRC_UseCRC16(void) -{ - LPC_CRC->MODE = MODE_CFG_CRC16; - LPC_CRC->SEED = CRC_SEED_CRC16; -} - -/** - * @brief Sets up the CRC engine for CRC32 mode - * @return Nothing - */ -STATIC INLINE void Chip_CRC_UseCRC32(void) -{ - LPC_CRC->MODE = MODE_CFG_CRC32; - LPC_CRC->SEED = CRC_SEED_CRC32; -} - -/** - * @brief Sets up the CRC engine for CCITT mode - * @return Nothing - */ -STATIC INLINE void Chip_CRC_UseCCITT(void) -{ - LPC_CRC->MODE = MODE_CFG_CCITT; - LPC_CRC->SEED = CRC_SEED_CCITT; -} - -/** - * @brief Engage the CRC engine with defaults based on the polynomial to be used - * @param poly : The enumerated polynomial to be used - * @return Nothing - */ -void Chip_CRC_UseDefaultConfig(CRC_POLY_T poly); - -/** - * @brief Set the CRC Mode bits - * @param mode : Mode value - * @return Nothing - */ -STATIC INLINE void Chip_CRC_SetMode(uint32_t mode) -{ - LPC_CRC->MODE = mode; -} - -/** - * @brief Get the CRC Mode bits - * @return The current value of the CRC Mode bits - */ -STATIC INLINE uint32_t Chip_CRC_GetMode(void) -{ - return LPC_CRC->MODE; -} - -/** - * @brief Set the seed bits used by the CRC_SUM register - * @param seed : Seed value - * @return Nothing - */ -STATIC INLINE void Chip_CRC_SetSeed(uint32_t seed) -{ - LPC_CRC->SEED = seed; -} - -/** - * @brief Get the CRC seed value - * @return Seed value - */ -STATIC INLINE uint32_t Chip_CRC_GetSeed(void) -{ - return LPC_CRC->SEED; -} - -/** - * @brief Convenience function for writing 8-bit data to the CRC engine - * @param data : 8-bit data to write - * @return Nothing - */ -STATIC INLINE void Chip_CRC_Write8(uint8_t data) -{ - LPC_CRC->WRDATA8 = data; -} - -/** - * @brief Convenience function for writing 16-bit data to the CRC engine - * @param data : 16-bit data to write - * @return Nothing - */ -STATIC INLINE void Chip_CRC_Write16(uint16_t data) -{ - LPC_CRC->WRDATA16 = data; -} - -/** - * @brief Convenience function for writing 32-bit data to the CRC engine - * @param data : 32-bit data to write - * @return Nothing - */ -STATIC INLINE void Chip_CRC_Write32(uint32_t data) -{ - LPC_CRC->WRDATA32 = data; -} - -/** - * @brief Gets the CRC Sum based on the Mode and Seed as previously configured - * @return CRC Checksum value - */ -STATIC INLINE uint32_t Chip_CRC_Sum(void) -{ - return LPC_CRC->SUM; -} - -/** - * @brief Convenience function for computing a standard CCITT checksum from an 8-bit data block - * @param data : Pointer to the block of 8-bit data - * @param bytes : The number of bytes pointed to by data - * @return Check sum value - */ -uint32_t Chip_CRC_CRC8(const uint8_t *data, uint32_t bytes); - -/** - * @brief Convenience function for computing a standard CRC16 checksum from 16-bit data block - * @param data : Pointer to the block of 16-bit data - * @param hwords : The number of 16 byte entries pointed to by data - * @return Check sum value - */ -uint32_t Chip_CRC_CRC16(const uint16_t *data, uint32_t hwords); - -/** - * @brief Convenience function for computing a standard CRC32 checksum from 32-bit data block - * @param data : Pointer to the block of 32-bit data - * @param words : The number of 32-bit entries pointed to by data - * @return Check sum value - */ -uint32_t Chip_CRC_CRC32(const uint32_t *data, uint32_t words); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CRC_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/fifo_5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/fifo_5410x.c deleted file mode 100644 index fea37d9b5c4..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/fifo_5410x.c +++ /dev/null @@ -1,306 +0,0 @@ -/* - * @brief LPC5410X System FIFO chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/** SPI FIFO read FIFO statuses */ -#define LPC_SPIRXFIFO_STAT_SSEL0N (1 << 16) /*!< Slave select for receive on SSEL0 (active low) */ -#define LPC_SPIRXFIFO_STAT_SSEL1N (1 << 17) /*!< Slave select for receive on SSEL1 (active low) */ -#define LPC_SPIRXFIFO_STAT_SSEL2N (1 << 18) /*!< Slave select for receive on SSEL2 (active low) */ -#define LPC_SPIRXFIFO_STAT_SSEL3N (1 << 19) /*!< Slave select for receive on SSEL3 (active low) */ -#define LPC_SPIRXFIFO_STAT_SOT (1 << 20) /*!< This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted */ - -/** SPI FIFO write FIFO control */ -#define LPC_SPITXFIFO_CTRL_SSEL0N (1 << 16) /*!< Master assert for receive on SSEL0 (active low) */ -#define LPC_SPITXFIFO_CTRL_SSEL1N (1 << 17) /*!< Master assert for receive on SSEL1 (active low) */ -#define LPC_SPITXFIFO_CTRL_SSEL2N (1 << 18) /*!< Master assert for receive on SSEL2 (active low) */ -#define LPC_SPITXFIFO_CTRL_SSEL3N (1 << 19) /*!< Master assert for receive on SSEL3 (active low) */ -#define LPC_SPITXFIFO_CTRL_EOT (1 << 20) /*!< End of Transfer. The asserted SSEL will be deasserted at the end of a transfer */ -#define LPC_SPITXFIFO_CTRL_EOF (1 << 21) /*!< End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register */ -#define LPC_SPITXFIFO_CTRL_RXIGNORE (1 << 22) /*!< Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver */ -#define LPC_SPITXFIFO_CTRL_LEN(n) ((n) << 24) /*!< Data Length. Specifies the data length from 1 to 16 bits ((n-1) encoded) */ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Initializes the system FIFO */ -void Chip_FIFO_Init(LPC_FIFO_T *pFIFO) -{ - Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_FIFO); - Chip_SYSCON_PeriphReset(RESET_FIFO); -} - -/* Deinitializes the system FIFO */ -void Chip_FIFO_Deinit(LPC_FIFO_T *pFIFO) -{ - Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_FIFO); -} - -/* Get the FIFO space available for the USART/SPI direction */ -uint32_t Chip_FIFO_GetFifoSpace(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_DIR_T dir) -{ - uint32_t pcfg; - - if (periphId == FIFO_USART) { - pcfg = pFIFO->common.FIFOCTLUSART; - } - else { - pcfg = pFIFO->common.FIFOCTLSPI; - } - - if (dir == FIFO_RX) { - pcfg = pcfg >> 16; - } - else { - pcfg = pcfg >> 24; - } - - return pcfg & 0xFF; -} - -/* Pause a peripheral FIFO */ -void Chip_FIFO_PauseFifo(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_DIR_T dir) -{ - if (periphId == FIFO_USART) { - if (dir == FIFO_RX) { - pFIFO->common.FIFOCTLUSART |= (1 << 0); - } - else { - pFIFO->common.FIFOCTLUSART |= (1 << 8); - } - } - else { - if (dir == FIFO_RX) { - pFIFO->common.FIFOCTLSPI |= (1 << 0); - } - else { - pFIFO->common.FIFOCTLSPI |= (1 << 8); - } - } -} - -/* Unpause a peripheral FIFO */ -void Chip_FIFO_UnpauseFifo(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_DIR_T dir) -{ - if (periphId == FIFO_USART) { - if (dir == FIFO_RX) { - pFIFO->common.FIFOCTLUSART &= ~(1 << 0); - } - else { - pFIFO->common.FIFOCTLUSART &= ~(1 << 8); - } - } - else { - if (dir == FIFO_RX) { - pFIFO->common.FIFOCTLSPI &= ~(1 << 0); - } - else { - pFIFO->common.FIFOCTLSPI &= ~(1 << 8); - } - } -} - -/* Configure a peripheral's FIFO sizes */ -void Chip_FIFO_ConfigFifoSize(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_CFGSIZE_T *pSizes) -{ - int maxP, i; - uint32_t upDateMask; - volatile uint32_t *updateReg, *pFifoSizes, *pFifoPause; - - /* Pause FIFOs */ - Chip_FIFO_PauseFifo(LPC_FIFO, periphId, FIFO_RX); - Chip_FIFO_PauseFifo(LPC_FIFO, periphId, FIFO_TX); - - /* Maximum peripheral FIFOs supported */ - if (periphId == FIFO_USART) { - maxP = LPC_FIFO_USART_MAX; - updateReg = &pFIFO->common.FIFOUPDATEUSART; - upDateMask = 0xF | (0xF << 16); - pFifoSizes = &pFIFO->common.FIFOCFGUSART[0]; - pFifoPause = &pFIFO->common.FIFOCTLUSART; - } - else { - maxP = LPC_FIFO_SPI_MAX; - updateReg = &pFIFO->common.FIFOUPDATESPI; - upDateMask = 0x3 | (0x3 << 16); - pFifoSizes = &pFIFO->common.FIFOCFGSPI[0]; - pFifoPause = &pFIFO->common.FIFOCTLSPI; - } - - /* Wait for FIFO pause */ - while ((*pFifoPause & ((1 << 0) | (1 << 8))) != ((1 << 0) | (1 << 8))) {} - - /* Update FIFO sizes */ - for (i = 0; i < maxP; i++) { - pFifoSizes[i] = ((uint32_t) (pSizes->fifoRXSize[i]) << 0) | - ((uint32_t) (pSizes->fifoTXSize[i]) << 8); - } - - /* Update all peripheral FIFO sizes */ - *updateReg = upDateMask; -} - -/* Configure the USART system FIFO */ -void Chip_FIFOUSART_Configure(LPC_FIFO_T *pFIFO, int usartIndex, LPC_FIFO_CFG_T *pUSARTCfg) -{ - pFIFO->usart[usartIndex].CFG = - (pUSARTCfg->noTimeoutContWrite << 4) | - (pUSARTCfg->noTimeoutContEmpty << 5) | - (pUSARTCfg->timeoutBase << 8) | - (pUSARTCfg->timeoutValue << 12) | - (pUSARTCfg->rxThreshold << 16) | - (pUSARTCfg->txThreshold << 24); -} - -/* Write data to a system FIFO (non-blocking) */ -int Chip_FIFOUSART_WriteTX(LPC_FIFO_T *pFIFO, int usartIndex, bool sz8, void *buff, int numData) -{ - int datumWritten, sz16; - uint8_t *p8 = (uint8_t *) buff; - uint16_t *p16 = (uint16_t *) buff; - - /* Get configured FIFO size to determine write size, limit to buffer size */ - sz16 = (pFIFO->usart[usartIndex].STAT >> 24) & 0xFF; - if (sz16 > numData) { - sz16 = numData; - } - datumWritten = sz16; - - /* Write from buffer */ - while (sz16 > 0) { - if (sz8) { - pFIFO->usart[usartIndex].TXDAT = (uint32_t) *p8; - p8++; - } - else { - pFIFO->usart[usartIndex].TXDAT = (uint32_t) *p16; - p16++; - } - - sz16--; - } - - return datumWritten; -} - -/* Read data from a system FIFO (non-blocking) */ -int Chip_FIFOUSART_ReadRX(LPC_FIFO_T *pFIFO, int usartIndex, bool sz8, void *buff, int numData) -{ - int datumRead, sz16; - uint8_t *p8 = (uint8_t *) buff; - uint16_t *p16 = (uint16_t *) buff; - - /* Get configured FIFO size to determine read size, limit to buffer size */ - sz16 = (pFIFO->usart[usartIndex].STAT >> 16) & 0xFF; - if (sz16 > numData) { - sz16 = numData; - } - datumRead = sz16; - - /* Read into buffer */ - while (sz16 > 0) { - if (sz8) { - *p8 = (uint8_t) (pFIFO->usart[usartIndex].RXDAT & 0xFF); - p8++; - } - else { - *p16 = (uint16_t) (pFIFO->usart[usartIndex].RXDAT & 0x1FF); - p16++; - } - - sz16--; - } - - return datumRead; -} - -/* Read data from a system FIFO with status (non-blocking) */ -int Chip_FIFOUSART_ReadRXStatus(LPC_FIFO_T *pFIFO, int usartIndex, uint16_t *buff, int numData) -{ - int datumRead, sz16; - uint16_t *p16 = (uint16_t *) buff; - - /* Get configured FIFO size to determine read size, limit to buffer size */ - sz16 = (pFIFO->usart[usartIndex].STAT >> 16) & 0xFF; - if (sz16 > numData) { - sz16 = numData; - } - datumRead = sz16; - - /* Read into buffer */ - while (sz16 > 0) { - *p16 = (uint16_t) (pFIFO->usart[usartIndex].RXDATSTAT & 0xFFFF); - p16++; - sz16--; - } - - return datumRead; -} - -#if 0 /* Sorry, not yet support */ -/* Configure the USART system FIFO */ -void Chip_FIFOSPI_Configure(LPC_FIFO_T *pFIFO, int spiIndex, LPC_FIFO_CFG_T *pSPICfg) -{ - pFIFO->spi[spiIndex].CFG = - (pSPICfg->noTimeoutContWrite << 4) | - (pSPICfg->noTimeoutContEmpty << 5) | - (pSPICfg->timeoutBase << 6) | - (pSPICfg->timeoutValue << 12) | - (pSPICfg->rxThreshold << 16) | - (pSPICfg->txThreshold << 24); -} - -/* Start a data transfer (non-blocking) */ -void Chip_FIFOSPI_StartTransfer(LPC_FIFO_T *pFIFO, LPC_FIFO_SPICTL_T *pSetupData) -{ - pSetupData->start = 1; - Chip_FIFOSPI_Transfer(pFIFO, pSetupData); -} - - -/* Feed a SPI data transfer (non-blocking) */ -void Chip_FIFOSPI_Transfer(LPC_FIFO_T *pFIFO, LPC_FIFO_SPICTL_T *pSetupData) -{ - // FIXME - not yet ready -} -#endif diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/fifo_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/fifo_5410x.h deleted file mode 100644 index 2c8f48878cb..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/fifo_5410x.h +++ /dev/null @@ -1,558 +0,0 @@ -/* - * @brief LPC5410X System FIFO chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __FIFO_5410X_H_ -#define __FIFO_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup FIFO_5410X CHIP: LPC5410X System FIFO chip driver - * @ingroup CHIP_5410X_DRIVERS - * This driver provides basic functionality for the system FIFO - * and can be used to increase the amount of FIFO space available - * to the UART and SPI peripherals. If using the system FIFO with the - * UART or SPI drivers, the standard UART and SPI transfer handlers - * cannot be used and buffer/stream management and status checking - * must occur in the user application. - * @{ - */ - -/** Maximum USART peripherals */ -#define LPC_FIFO_USART_MAX (4) - -/** Maximum SPI peripherals */ -#define LPC_FIFO_SPI_MAX (2) - -/** - * @brief LPC5410X System FIFO USART register block structure - */ -typedef struct { - __IO uint32_t CFG; /*!< USART configuration Register */ - __IO uint32_t STAT; /*!< USART status Register */ - __IO uint32_t INTSTAT; /*!< USART interrupt status Register */ - __IO uint32_t CTLSET; /*!< USART control read and set Register */ - __IO uint32_t CTLCLR; /*!< USART control clear Register */ - __IO uint32_t RXDAT; /*!< USART received data Register */ - __IO uint32_t RXDATSTAT; /*!< USART received data with status Register */ - __IO uint32_t TXDAT; /*!< USART transmit data Register */ - __I uint32_t RESERVED[0x38]; -} LPC_FIFO_USART_T; - -/** - * @brief LPC5410X System FIFO SPI register block structure - */ -typedef struct { - __IO uint32_t CFG; /*!< SPI configuration Register */ - __IO uint32_t STAT; /*!< SPI status Register */ - __IO uint32_t INTSTAT; /*!< SPI interrupt status Register */ - __IO uint32_t CTLSET; /*!< SPI control read and set Register */ - __IO uint32_t CTLCLR; /*!< SPI control clear Register */ - __I uint32_t RXDAT; /*!< SPI received data Register */ - union { - __O uint32_t TXDATSPI; /*!< SPI transmit data and control Register */ - struct { - __O uint16_t TXDATSPI_DATA; /*!< SPI transmit data Register */ - __O uint16_t TXDATSPI_CTRL; /*!< SPI transmit control Register */ - }; - - }; - - __I uint32_t RESERVED[0x39]; -} LPC_FIFO_SPI_T; - -/** - * @brief LPC5410X System FIFO common register block structure - */ -typedef struct { - __I uint32_t reserved0[0x40]; - __IO uint32_t FIFOCTLUSART; /*!< USART FIFO global control Register */ - __O uint32_t FIFOUPDATEUSART; /*!< USART FIFO global update Register */ - __I uint32_t reserved1[0x2]; - __IO uint32_t FIFOCFGUSART[LPC_FIFO_USART_MAX]; /*!< USART FIFO configuration Registers */ - __I uint32_t reserved2[0x38]; - __IO uint32_t FIFOCTLSPI; /*!< SPI FIFO global control Register */ - __O uint32_t FIFOUPDATESPI; /*!< SPI FIFO global update Register */ - __I uint32_t reserved3[0x2]; - __IO uint32_t FIFOCFGSPI[LPC_FIFO_SPI_MAX]; /*!< SPI FIFO configuration Registers */ - __I uint32_t reserved4[0x3A]; - __I uint32_t reserved5[((0x1000 - 0x300) / sizeof(uint32_t))]; -} LPC_FIFO_CMN_T; - -/** - * @brief LPC5410X Complete system FIFO register block structure - */ -typedef struct { - LPC_FIFO_CMN_T common; - LPC_FIFO_USART_T usart[LPC_FIFO_USART_MAX]; - __I uint32_t reserved0[((0x2000 - 0x1400) / sizeof(uint32_t))]; - LPC_FIFO_SPI_T spi[LPC_FIFO_SPI_MAX]; -} LPC_FIFO_T; - -/** @defgroup FIFO_CMN_5410X CHIP: Common FIFO functions - * These functions are for both the USART and SPI configuration and - * status. - * @{ - */ - -/** - * @brief Initializes the system FIFO - * @brief pFIFO : Pointer to system FIFO registers - * @return Nothing - */ -void Chip_FIFO_Init(LPC_FIFO_T *pFIFO); - -/** - * @brief Deinitializes the system FIFO - * @brief pFIFO : Pointer to system FIFO registers - * @return Nothing - */ -void Chip_FIFO_Deinit(LPC_FIFO_T *pFIFO); - -/** USART/SPI peripheral identifier */ -typedef enum {FIFO_USART, FIFO_SPI} LPC_FIFO_PERIPHID_T; - -/** USART/SPI FIFO direction identifier */ -typedef enum {FIFO_RX, FIFO_TX} LPC_FIFO_DIR_T; - -/** - * @brief Get the FIFO space available for the USART/SPI direction - * @brief pFIFO : Pointer to system FIFO registers - * @brief periphId : Peripheral identifer - * @brief dir : FIFO direction - * @return Amount of FIFO space available for the peripheral - */ -uint32_t Chip_FIFO_GetFifoSpace(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_DIR_T dir); - -/** USART and SPI FIFO common statuses */ -#define LPC_FIFO_STAT_RXPAUSED (1 << 1) /*!< Receive FIFOs paused status */ -#define LPC_FIFO_STAT_RXEMPTY (1 << 2) /*!< Receive FIFOs empty status */ -#define LPC_FIFO_STAT_TXPAUSED (1 << 9) /*!< Transmit FIFOs paused status */ -#define LPC_FIFO_STAT_TXEMPTY (1 << 10) /*!< Transmit FIFOs empty status */ - -/** - * @brief Get periperhal FIFO status - * @brief pFIFO : Pointer to system FIFO registers - * @return A bitfield of status values, mask with LPC_FIFO_STAT_* values - * @note Mask with one or more LPC_FIFO_STAT_* definitions to get the - * status of the peripherals. - */ -STATIC INLINE uint32_t Chip_FIFO_GetFifoStatus(LPC_FIFO_T *pFIFO) -{ - return pFIFO->common.FIFOCTLUSART; -} - -/** - * @brief Pause a peripheral FIFO - * @brief pFIFO : Pointer to system FIFO registers - * @brief periphId : Peripheral identifer - * @brief dir : FIFO direction - * @return Nothing - */ -void Chip_FIFO_PauseFifo(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_DIR_T dir); - -/** - * @brief Unpause a peripheral FIFO - * @brief pFIFO : Pointer to system FIFO registers - * @brief periphId : Peripheral identifer - * @brief dir : FIFO direction - * @return Nothing - */ -void Chip_FIFO_UnpauseFifo(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_DIR_T dir); - -/** Stucture for setting USART or SPI FIFO sizes */ -typedef struct { - uint16_t fifoRXSize[4]; /*!< FIFO RX size, 0-3 for USARTS 0-3, or 0-1 for SPIS 0-1 */ - uint16_t fifoTXSize[4]; /*!< FIFO TX size, 0-3 for USARTS 0-3, or 0-1 for SPIS 0-1 */ -} LPC_FIFO_CFGSIZE_T; - -/** - * @brief Configure a peripheral's FIFO sizes - * @brief pFIFO : Pointer to system FIFO registers - * @brief periphId : Peripheral identifer - * @brief pSizes : Pointer to s structure filled out with the peripherla FIFO sizes - * @return Nothing - * @note This function configures all the FIFOs for a supported peripheral - * in a single call. Use 0 to disable the FIFO. This function will pause the FIFO - * and leave it paused after configuration, call Chip_FIFO_UnpauseFifo() after - * calling this function. - */ -void Chip_FIFO_ConfigFifoSize(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_CFGSIZE_T *pSizes); - -/** Stucture for setting USART and SPI FIFO configuration */ -typedef struct { - uint32_t noTimeoutContWrite : 1; /*!< Timeout Continue On Write, set to 0 to reset timeout on each TX FIFO data, or 1 for accumulated timeout */ - uint32_t noTimeoutContEmpty : 1; /*!< Timeout Continue On Empty., set to 0 to reset timeout on each RX FIFO data, or 1 for accumulated timeout */ - uint32_t timeoutBase : 4; /*!< Specifies the least significant timer bit to compare to TimeoutValue. See User Manual */ - uint32_t timeoutValue : 4; /*!< Specifies the maximum time value for timeout at the timer position identified by TimeoutBase. See User Manual */ - uint32_t rxThreshold : 8; /*!< Receive FIFO Threshold, number of data to receive prior to interrupt */ - uint32_t txThreshold : 8; /*!< Transmit FIFO Threshold, number of free TX data entries available prior to interrupt */ -} LPC_FIFO_CFG_T; - -/** USART and SPI FIFO statuses */ -#define LPC_PERIPFIFO_STAT_RXTH (1 << 0) /*!< When 1, the receive FIFO threshold has been reached */ -#define LPC_PERIPFIFO_STAT_TXTH (1 << 1) /*!< When 1, the transmit FIFO threshold has been reached */ -#define LPC_PERIPFIFO_STATCLR_RXTIMEOUT (1 << 4) /*!< When 1, the receive FIFO has timed out, based on the timeout configuration in the CFG register */ -#define LPC_PERIPFIFO_STATCLR_BUSERR (1 << 7) /*!< Bus Error. When 1, a bus error has occurred while processing data for the peripheral. The bus error flag can be cleared by writing a 1 to this bit. */ -#define LPC_PERIPFIFO_STAT_RXEMPTY (1 << 8) /*!< Receive FIFO Empty. When 1, the receive FIFO is currently empty. */ -#define LPC_PERIPFIFO_STAT_TXEMPTY (1 << 9) /*!< Transmit FIFO Empty. When 1, the transmit FIFO is currently empty. */ - -/** USART interrupt enable/disable bits */ -#define LPC_PERIPFIFO_INT_RXTH (1 << 0) /*!< Receive FIFO Threshold Interrupt Enable */ -#define LPC_PERIPFIFO_INT_TXTH (1 << 1) /*!< Transmit FIFO Threshold Interrupt Enable */ -#define LPC_PERIPFIFO_INT_RXTIMEOUT (1 << 4) /*!< Receive FIFO Timeout Interrupt Enable */ -#define LPC_PERIPFIFO_INT_RXFLUSH (1 << 8) /*!< Receive FIFO flush */ -#define LPC_PERIPFIFO_INT_TXFLUSH (1 << 9) /*!< Transmit FIFO flush */ - -/** - * @} - */ - -/** @defgroup FIFO_USART_5410X CHIP: USART FIFO functions - * These functions are for both the USART configuration, control, and status. - * @{ - */ - -/** - * @brief Configure the USART system FIFO - * @brief pFIFO : Pointer to system FIFO registers - * @brief usartIndex : USART system FIFO index, 0 - 3 - * @brief pUSARTCfg : Pointer to USART configuration - * @return Nothing - */ -void Chip_FIFOUSART_Configure(LPC_FIFO_T *pFIFO, int usartIndex, LPC_FIFO_CFG_T *pUSARTCfg); - -/** - * @brief Get USART FIFO statuses - * @brief pFIFO : Pointer to system FIFO registers - * @brief usartIndex : USART system FIFO index, 0 - 3 - * @return USART system FIFO statuses (mask with LPC_PERIPFIFO_STAT* values) - */ -STATIC INLINE uint32_t Chip_FIFOUSART_GetStatus(LPC_FIFO_T *pFIFO, int usartIndex) -{ - return pFIFO->usart[usartIndex].STAT; -} - -/** - * @brief Get USART RX FIFO count - * @brief pFIFO : Pointer to system FIFO registers - * @brief usartIndex : USART system FIFO index, 0 - 3 - * @return Returns how many entries may be read from the receive FIFO. 0 = FIFO empty. - */ -STATIC INLINE uint32_t Chip_FIFOUSART_GetRxCount(LPC_FIFO_T *pFIFO, int usartIndex) -{ - return (pFIFO->usart[usartIndex].STAT >> 16) & 0xFF; -} - -/** - * @brief Get USART TC FIFO count - * @brief pFIFO : Pointer to system FIFO registers - * @brief usartIndex : USART system FIFO index, 0 - 3 - * @return Returns how many entries may be written to the transmit FIFO. 0 = FIFO full. - */ -STATIC INLINE uint32_t Chip_FIFOUSART_GetTxCount(LPC_FIFO_T *pFIFO, int usartIndex) -{ - return (pFIFO->usart[usartIndex].STAT >> 24) & 0xFF; -} - -/** - * @brief Clear USART FIFO statuses - * @brief pFIFO : Pointer to system FIFO registers - * @brief usartIndex : USART system FIFO index, 0 - 3 - * @brief clearMask : Mask of latched bits to cleared, Or'ed values of LPC_PERIPFIFO_STATCLR* - * @return Nothing - */ -STATIC INLINE void Chip_FIFOUSART_ClearStatus(LPC_FIFO_T *pFIFO, int usartIndex, uint32_t clearMask) -{ - pFIFO->usart[usartIndex].STAT = clearMask; -} - -/** - * @brief Get USART FIFO pending interrupt statuses - * @brief pFIFO : Pointer to system FIFO registers - * @brief usartIndex : USART system FIFO index, 0 - 3 - * @return USART system FIFO pending interrupt statuses (mask with LPC_PERIPFIFO_STAT* values) - */ -STATIC INLINE uint32_t Chip_FIFOUSART_GetIntStatus(LPC_FIFO_T *pFIFO, int usartIndex) -{ - return pFIFO->usart[usartIndex].INTSTAT; -} - -/** - * @brief Enable USART system FIFO interrupts - * @brief pFIFO : Pointer to system FIFO registers - * @brief usartIndex : USART system FIFO index, 0 - 3 - * @brief intMask : Interrupts to enable (LPC_PERIPFIFO_INT_RXTH, LPC_PERIPFIFO_INT_TXTH, or LPC_PERIPFIFO_INT_RXTIMEOUT) - * @return Nothing - */ -STATIC INLINE void Chip_FIFOUSART_EnableInts(LPC_FIFO_T *pFIFO, int usartIndex, uint32_t intMask) -{ - pFIFO->usart[usartIndex].CTLSET = intMask; -} - -/** - * @brief Disable USART system FIFO interrupts - * @brief pFIFO : Pointer to system FIFO registers - * @brief usartIndex : USART system FIFO index, 0 - 3 - * @brief intMask : Interrupts to disable (LPC_PERIPFIFO_INT_RXTH, LPC_PERIPFIFO_INT_TXTH, or LPC_PERIPFIFO_INT_RXTIMEOUT) - * @return Nothing - */ -STATIC INLINE void Chip_FIFOUSART_DisableInts(LPC_FIFO_T *pFIFO, int usartIndex, uint32_t intMask) -{ - pFIFO->usart[usartIndex].CTLCLR = intMask; -} - -/** - * @brief Flush TX and/or RX USART system FIFOs - * @brief pFIFO : Pointer to system FIFO registers - * @brief usartIndex : USART system FIFO index, 0 - 3 - * @brief flushMask : FIFOS to flush (Or'ed LPC_PERIPFIFO_INT_RXFLUSH and/or LPC_PERIPFIFO_INT_TXFLUSH) - * @return Nothing - */ -STATIC INLINE void Chip_FIFOUSART_FlushFIFO(LPC_FIFO_T *pFIFO, int usartIndex, uint32_t flushMask) -{ - flushMask = flushMask & (LPC_PERIPFIFO_INT_RXFLUSH | LPC_PERIPFIFO_INT_TXFLUSH); - - pFIFO->usart[usartIndex].CTLSET = flushMask; - pFIFO->usart[usartIndex].CTLCLR = flushMask; -} - -/** - * @brief Write data to a USART system FIFO (non-blocking) - * @brief pFIFO : Pointer to system FIFO registers - * @brief usartIndex : USART system FIFO index, 0 - 3 - * @brief sz8 : Set to true for 8-bit or less data, or false for >8-bit - * @brief buff : Pointer to data in buffer to write - * @brief numData : Maximum number of data values to write - * @return The number of data values written to the USART system FIFO - */ -int Chip_FIFOUSART_WriteTX(LPC_FIFO_T *pFIFO, int usartIndex, bool sz8, void *buff, int numData); - -/** - * @brief Read data from a USART system FIFO (non-blocking) - * @brief pFIFO : Pointer to system FIFO registers - * @brief usartIndex : USART system FIFO index, 0 - 3 - * @brief sz8 : Set to true for 8-bit or less data, or false for >8-bit - * @brief buff : Pointer to data buffer to read into - * @brief numData : Maximum number of data values to read - * @return The number of data values read from the USART system FIFO - */ -int Chip_FIFOUSART_ReadRX(LPC_FIFO_T *pFIFO, int usartIndex, bool sz8, void *buff, int numData); - -/** USART FIFO read FIFO statuses */ -#define LPC_USARTRXFIFO_STAT_FRAMERR (1 << 13) /*!< Framing Error status flag */ -#define LPC_USARTRXFIFO_STAT_PARITYERR (1 << 14) /*!< Parity Error status flag */ -#define LPC_USARTRXFIFO_STAT_RXNOISE (1 << 15) /*!< Received Noise flag */ - -/** - * @brief Read data from a USART system FIFO with status (non-blocking) - * @brief pFIFO : Pointer to system FIFO registers - * @brief usartIndex : USART system FIFO index, 0 - 3 - * @brief buff : Pointer to data buffer to read into - * @brief numData : Maximum number of data values to read - * @return The number of data values with status read from the USART system FIFO. Mask - * the upper bits of each word in the buffer with the LPC_USARTRXFIFO_STAT_* flags to - * determine individual data status. - */ -int Chip_FIFOUSART_ReadRXStatus(LPC_FIFO_T *pFIFO, int usartIndex, uint16_t *buff, int numData); - -/** - * @} - */ - -/** @defgroup FIFO_SPI_5410X CHIP: SPI FIFO functions - * These functions are for both the SPI configuration, control, and status. - * @{ - */ - -/** - * @brief Configure the SPI system FIFO - * @brief pFIFO : Pointer to system FIFO registers - * @brief spiIndex : SPI system FIFO index, 0 - 1 - * @brief pUSARTCfg : Pointer to SPI configuration - * @return Nothing - */ -void Chip_FIFOSPI_Configure(LPC_FIFO_T *pFIFO, int spiIndex, LPC_FIFO_CFG_T *pSPICfg); - -/** - * @brief Get SPI FIFO statuses - * @brief pFIFO : Pointer to system FIFO registers - * @brief spiIndex : SPI system FIFO index, 0 - 1 - * @return SPI system FIFO statuses (mask with LPC_PERIPFIFO_STAT* values) - */ -STATIC INLINE uint32_t Chip_FIFOSPI_GetStatus(LPC_FIFO_T *pFIFO, int spiIndex) -{ - return pFIFO->spi[spiIndex].STAT; -} - -/** - * @brief Get SPI RX FIFO count - * @brief pFIFO : Pointer to system FIFO registers - * @brief spiIndex : SPI system FIFO index, 0 - 1 - * @return Returns how many entries may be read from the receive FIFO. 0 = FIFO empty. - */ -STATIC INLINE uint32_t Chip_FIFOSPI_GetRxCount(LPC_FIFO_T *pFIFO, int spiIndex) -{ - return (pFIFO->spi[spiIndex].STAT >> 16) & 0xFF; -} - -/** - * @brief Get SPI TX FIFO count - * @brief pFIFO : Pointer to system FIFO registers - * @brief spiIndex : SPI system FIFO index, 0 - 1 - * @return Returns how many entries may be written to the transmit FIFO. 0 = FIFO full. - */ -STATIC INLINE uint32_t Chip_FIFOSPI_GetTxCount(LPC_FIFO_T *pFIFO, int spiIndex) -{ - return (pFIFO->spi[spiIndex].STAT >> 24) & 0xFF; -} - -/** - * @brief Clear SPI FIFO statuses - * @brief pFIFO : Pointer to system FIFO registers - * @brief spiIndex : SPI system FIFO index, 0 - 1 - * @brief clearMask : Mask of latched bits to cleared, Or'ed values of LPC_PERIPFIFO_STATCLR* - * @return Nothing - */ -STATIC INLINE void Chip_FIFOSPI_ClearStatus(LPC_FIFO_T *pFIFO, int spiIndex, uint32_t clearMask) -{ - pFIFO->spi[spiIndex].STAT = clearMask; -} - -/** - * @brief Get SPI FIFO pending interrupt statuses - * @brief pFIFO : Pointer to system FIFO registers - * @brief spiIndex : SPI system FIFO index, 0 - 1 - * @return SPI system FIFO pending interrupt statuses (mask with LPC_PERIPFIFO_STAT* values) - */ -STATIC INLINE uint32_t Chip_FIFOSPI_GetIntStatus(LPC_FIFO_T *pFIFO, int spiIndex) -{ - return pFIFO->spi[spiIndex].INTSTAT; -} - -/** - * @brief Enable SPI system FIFO interrupts - * @brief pFIFO : Pointer to system FIFO registers - * @brief spiIndex : SPI system FIFO index, 0 - 1 - * @brief intMask : Interrupts to enable (LPC_PERIPFIFO_INT_RXTH, LPC_PERIPFIFO_INT_TXTH, or LPC_PERIPFIFO_INT_RXTIMEOUT) - * @return Nothing - */ -STATIC INLINE void Chip_FIFOSPI_EnableInts(LPC_FIFO_T *pFIFO, int spiIndex, uint32_t intMask) -{ - pFIFO->spi[spiIndex].CTLSET = intMask; -} - -/** - * @brief Disable SPI system FIFO interrupts - * @brief pFIFO : Pointer to system FIFO registers - * @brief spiIndex : SPI system FIFO index, 0 - 1 - * @brief intMask : Interrupts to disable (LPC_PERIPFIFO_INT_RXTH, LPC_PERIPFIFO_INT_TXTH, or LPC_PERIPFIFO_INT_RXTIMEOUT) - * @return Nothing - */ -STATIC INLINE void Chip_FIFOSPI_DisableInts(LPC_FIFO_T *pFIFO, int spiIndex, uint32_t intMask) -{ - pFIFO->spi[spiIndex].CTLCLR = intMask; -} - -/** - * @brief Flush TX and/or RX SPI system FIFOs - * @brief pFIFO : Pointer to system FIFO registers - * @brief spiIndex : SPI system FIFO index, 0 - 1 - * @brief flushMask : FIFOS to flush (Or'ed LPC_PERIPFIFO_INT_RXFLUSH and/or LPC_PERIPFIFO_INT_TXFLUSH) - * @return Nothing - */ -STATIC INLINE void Chip_FIFOSPI_FlushFIFO(LPC_FIFO_T *pFIFO, int spiIndex, uint32_t flushMask) -{ - flushMask = flushMask & (LPC_PERIPFIFO_INT_RXFLUSH | LPC_PERIPFIFO_INT_TXFLUSH); - - pFIFO->spi[spiIndex].CTLSET = flushMask; - pFIFO->spi[spiIndex].CTLCLR = flushMask; -} - -/** SPI transfer flags */ -#define LPC_SPIFIFO_FLAG_EOF (1 << 21) /*!< Add a delay between frames */ -#define LPC_SPIFIFO_FLAG_RXIGNORE (1 << 22) /*!< Ignore RX data */ - -/** SPI transfer error statuses */ -#define LPC_SPIFIFO_STAT_BUSY (0x0) /*!< SPI transfer busy/in progress */ -#define LPC_SPIFIFO_STAT_BADPARAM (0x1) /*!< SPI paramaters for transfer are invalid */ -#define LPC_SPIFIFO_STAT_TXUNDERRUN (0x2) /*!< Slave mode only, transmit FIFO underrun */ -#define LPC_SPIFIFO_STAT_RXOVERRUN (0x3) /*!< Slave mode only, receive FIFO overrun */ -#define LPC_SPIFIFO_STAT_COMPLETE (0xF) /*!< SPI transfer completed successfully */ - -#if 0 /* Sorry, not yet support */ -/** Stucture for SPI control */ -typedef struct { - uint32_t start : 1; /*!< Indicates transfer start, 0 = transfer resume, 1 = transfer start (automatically set by Chip_FIFOSPI_StartTransfer()) */ - uint32_t end : 1; /*!< Transfer wil end once buffers are empty */ - uint32_t sz8 : 1; /*!< Specifies the in and out buffer sizes, 0 = 16-bit, 1 = 8-bit */ - uint32_t sselNum : 2; /*!< SPI chip select number, 0 - 3 */ - void *inBuff; /*!< SPI transfer in data buffer pointer */ - uint32_t inIndex; /*!< SPI transfer in buffer index */ - void *outBuff; /*!< SPI transfer out data buffer pointer */ - uint32_t outIndex; /*!< SPI transfer out buffer index */ - uint32_t numData; /*!< Size of data both the receive and transfer buffers */ - int spiIndex; /*!< SPI system FIFO index, 0 - 1 */ -} LPC_FIFO_SPICTL_T; - -/** - * @brief Start a SPI data transfer (non-blocking) - * @brief pFIFO : Pointer to system FIFO registers - * @brief pSetupData : Pointer to SPI transfer setup structure - * @return Nothing - * @note Simply calls Chip_FIFOSPI_Transfer() with pSetupData->start = 1. - */ -void Chip_FIFOSPI_StartTransfer(LPC_FIFO_T *pFIFO, LPC_FIFO_SPICTL_T *pSetupData); - -/** - * @brief Feed a SPI data transfer (non-blocking) - * @brief pFIFO : Pointer to system FIFO registers - * @brief pSetupData : Pointer to SPI transfer setup structure - * @return Nothing - * @note Continues SPI transfer usng the system FIFO. - */ -void Chip_FIFOSPI_Transfer(LPC_FIFO_T *pFIFO, LPC_FIFO_SPICTL_T *pSetupData); -#endif - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __FIFO_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/gpio_5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/gpio_5410x.c deleted file mode 100644 index c97d365e045..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/gpio_5410x.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * @brief LPC5410X GPIO driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* GPIO initilisation function */ -void Chip_GPIO_Init(LPC_GPIO_T *pGPIO) -{ - Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_GPIO0); - Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_GPIO1); - Chip_SYSCON_PeriphReset(RESET_GPIO0); - Chip_SYSCON_PeriphReset(RESET_GPIO1); -} - -/* GPIO deinitialisation function */ -void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO) -{ - Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_GPIO0); - Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_GPIO1); -} - -/* Set GPIO direction for a single GPIO pin */ -void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin, bool setting) -{ - if (setting) { - pGPIO->DIR[port] |= 1UL << pin; - } - else { - pGPIO->DIR[port] &= ~(1UL << pin); - } -} - -/* Set GPIO direction for a single GPIO pin */ -void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output) -{ - if (output) { - Chip_GPIO_SetPinDIROutput(pGPIO, port, pin); - } - else { - Chip_GPIO_SetPinDIRInput(pGPIO, port, pin); - } -} - -/* Set Direction for a GPIO port */ -void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue, uint8_t out) -{ - if (out) { - pGPIO->DIR[portNum] |= bitValue; - } - else { - pGPIO->DIR[portNum] &= ~bitValue; - } -} - -/* Set GPIO direction for a all selected GPIO pins to an input or output */ -void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask, bool outSet) -{ - if (outSet) { - Chip_GPIO_SetPortDIROutput(pGPIO, port, pinMask); - } - else { - Chip_GPIO_SetPortDIRInput(pGPIO, port, pinMask); - } -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/gpio_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/gpio_5410x.h deleted file mode 100644 index 2522fe85aff..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/gpio_5410x.h +++ /dev/null @@ -1,471 +0,0 @@ -/* - * @brief LPC5410X GPIO driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __GPIO_5410X_H_ -#define __GPIO_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup GPIO_5410X CHIP: LPC5410X GPIO driver - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/** - * @brief GPIO port register block structure - */ -typedef struct { /*!< GPIO_PORT Structure */ - __IO uint8_t B[128][32]; /*!< Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */ - __IO uint32_t W[32][32]; /*!< Offset 0x1000: Word pin registers port 0 to n */ - __IO uint32_t DIR[32]; /*!< Offset 0x2000: Direction registers port n */ - __IO uint32_t MASK[32]; /*!< Offset 0x2080: Mask register port n */ - __IO uint32_t PIN[32]; /*!< Offset 0x2100: Portpin register port n */ - __IO uint32_t MPIN[32]; /*!< Offset 0x2180: Masked port register port n */ - __IO uint32_t SET[32]; /*!< Offset 0x2200: Write: Set register for port n Read: output bits for port n */ - __O uint32_t CLR[32]; /*!< Offset 0x2280: Clear port n */ - __O uint32_t NOT[32]; /*!< Offset 0x2300: Toggle port n */ -} LPC_GPIO_T; - -/** - * @brief Initialize GPIO block - * @param pGPIO : The base of GPIO peripheral on the chip - * @return Nothing - */ -void Chip_GPIO_Init(LPC_GPIO_T *pGPIO); - -/** - * @brief De-Initialize GPIO block - * @param pGPIO : The base of GPIO peripheral on the chip - * @return Nothing - */ -void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO); - -/** - * @brief Set a GPIO port/pin state - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : GPIO port to set - * @param pin : GPIO pin to set - * @param setting : true for high, false for low - * @return Nothing - * @note It is recommended to use the Chip_GPIO_SetPinState() function instead. - */ -STATIC INLINE void Chip_GPIO_WritePortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin, bool setting) -{ - pGPIO->B[port][pin] = setting; -} - -/** - * @brief Set a GPIO pin state via the GPIO byte register - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : GPIO port to set - * @param pin : GPIO pin to set - * @param setting : true for high, false for low - * @return Nothing - * @note This function replaces Chip_GPIO_WritePortBit() - */ -STATIC INLINE void Chip_GPIO_SetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool setting) -{ - pGPIO->B[port][pin] = setting; -} - -/** - * @brief Read a GPIO pin state via the GPIO byte register - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : GPIO port to read - * @param pin : GPIO pin to read - * @return true if the GPIO pin is high, false if low - * @note It is recommended to use the Chip_GPIO_GetPinState() function instead. - */ -STATIC INLINE bool Chip_GPIO_ReadPortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin) -{ - return (bool) pGPIO->B[port][pin]; -} - -/** - * @brief Get a GPIO pin state via the GPIO byte register - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : GPIO port to read - * @param pin : GPIO pin to get state for - * @return true if the GPIO is high, false if low - * @note This function replaces Chip_GPIO_ReadPortBit() - */ -STATIC INLINE bool Chip_GPIO_GetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) -{ - return (bool) pGPIO->B[port][pin]; -} - -/** - * @brief Set GPIO direction for a single GPIO pin - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : GPIO port to set - * @param pin : GPIO pin to set - * @param setting : true for output, false for input - * @return Nothing - * @note It is recommended to use the Chip_GPIO_SetPinDIROutput(), - * Chip_GPIO_SetPinDIRInput() or Chip_GPIO_SetPinDIR() functions instead - * of this function. - */ -void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin, bool setting); - -/** - * @brief Set GPIO direction for a single GPIO pin to an output - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : GPIO port to set - * @param pin : GPIO pin to set direction on as output - * @return Nothing - */ -STATIC INLINE void Chip_GPIO_SetPinDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) -{ - pGPIO->DIR[port] |= 1UL << pin; -} - -/** - * @brief Set GPIO direction for a single GPIO pin to an input - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : GPIO port to set - * @param pin : GPIO pin to set direction on as input - * @return Nothing - */ -STATIC INLINE void Chip_GPIO_SetPinDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) -{ - pGPIO->DIR[port] &= ~(1UL << pin); -} - -/** - * @brief Set GPIO direction for a single GPIO pin - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : GPIO port to set - * @param pin : GPIO pin to set direction for - * @param output : true for output, false for input - * @return Nothing - */ -void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output); - -/** - * @brief Read a GPIO direction (out or in) - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : GPIO port to read - * @param bit : GPIO bit direction to read - * @return true if the GPIO is an output, false if input - * @note It is recommended to use the Chip_GPIO_GetPinDIR() function instead. - */ -STATIC INLINE bool Chip_GPIO_ReadDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit) -{ - return (bool) (((pGPIO->DIR[port]) >> bit) & 1); -} - -/** - * @brief Get GPIO direction for a single GPIO pin - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : GPIO port to read (supports port 0 only) - * @param pin : GPIO pin to get direction for - * @return true if the GPIO is an output, false if input - */ -STATIC INLINE bool Chip_GPIO_GetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) -{ - return Chip_GPIO_ReadDirBit(pGPIO, port, pin); -} - -/** - * @brief Set Direction for a GPIO port - * @param pGPIO : The base of GPIO peripheral on the chip - * @param portNum : port Number - * @param bitValue : GPIO bit to set - * @param out : Direction value, 0 = input, !0 = output - * @return None - * @note Bits set to '0' are not altered. It is recommended to use the - * Chip_GPIO_SetPortDIR() function instead. - */ -void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue, uint8_t out); - -/** - * @brief Set GPIO direction for a all selected GPIO pins to an output - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number - * @param pinMask : GPIO pin mask to set direction on as output (bits 0..b for pins 0..n) - * @return Nothing - * @note Sets multiple GPIO pins to the output direction, each bit's position that is - * high sets the corresponding pin number for that bit to an output. - */ -STATIC INLINE void Chip_GPIO_SetPortDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask) -{ - pGPIO->DIR[port] |= pinMask; -} - -/** - * @brief Set GPIO direction for a all selected GPIO pins to an input - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number - * @param pinMask : GPIO pin mask to set direction on as input (bits 0..b for pins 0..n) - * @return Nothing - * @note Sets multiple GPIO pins to the input direction, each bit's position that is - * high sets the corresponding pin number for that bit to an input. - */ -STATIC INLINE void Chip_GPIO_SetPortDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask) -{ - pGPIO->DIR[port] &= ~pinMask; -} - -/** - * @brief Set GPIO direction for a all selected GPIO pins to an input or output - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number - * @param pinMask : GPIO pin mask to set direction on (bits 0..b for pins 0..n) - * @param outSet : Direction value, false = set as inputs, true = set as outputs - * @return Nothing - * @note Sets multiple GPIO pins to the input direction, each bit's position that is - * high sets the corresponding pin number for that bit to an input. - */ -void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask, bool outSet); - -/** - * @brief Get GPIO direction for a all GPIO pins - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number - * @return a bitfield containing the input and output states for each pin - * @note For pins 0..n, a high state in a bit corresponds to an output state for the - * same pin, while a low state corresponds to an input state. - */ -STATIC INLINE uint32_t Chip_GPIO_GetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port) -{ - return pGPIO->DIR[port]; -} - -/** - * @brief Set GPIO port mask value for GPIO masked read and write - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @param mask : Mask value for read and write - * @return Nothing - * @note Controls which bits corresponding to PIO0_n are active in the P0MPORT - * register (bit 0 = PIO0_0, bit 1 = PIO0_1, ..., bit 17 = PIO0_17). - */ -STATIC INLINE void Chip_GPIO_SetPortMask(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t mask) -{ - pGPIO->MASK[port] = mask; -} - -/** - * @brief Get GPIO port mask value used for GPIO masked read and write - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @return Returns value set with the Chip_GPIO_SetPortMask() function. - */ -STATIC INLINE uint32_t Chip_GPIO_GetPortMask(LPC_GPIO_T *pGPIO, uint8_t port) -{ - return pGPIO->MASK[port]; -} - -/** - * @brief Set all GPIO raw pin states (regardless of masking) - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @param value : Value to set all GPIO pin states (0..n) to - * @return Nothing - */ -STATIC INLINE void Chip_GPIO_SetPortValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value) -{ - pGPIO->PIN[port] = value; -} - -/** - * @brief Get all GPIO raw pin states (regardless of masking) - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @return Current (raw) state of all GPIO pins - */ -STATIC INLINE uint32_t Chip_GPIO_GetPortValue(LPC_GPIO_T *pGPIO, uint8_t port) -{ - return pGPIO->PIN[port]; -} - -/** - * @brief Set all GPIO pin states, but mask via the MASKP0 register - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @param value : Value to set all GPIO pin states (0..n) to - * @return Nothing - */ -STATIC INLINE void Chip_GPIO_SetMaskedPortValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value) -{ - pGPIO->MPIN[port] = value; -} - -/** - * @brief Get all GPIO pin statesm but mask via the MASKP0 register - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @return Current (masked) state of all GPIO pins - */ -STATIC INLINE uint32_t Chip_GPIO_GetMaskedPortValue(LPC_GPIO_T *pGPIO, uint8_t port) -{ - return pGPIO->MPIN[port]; -} - -/** - * @brief Set a GPIO port/bit to the high state - * @param pGPIO : The base of GPIO peripheral on the chip - * @param portNum : port number (supports port 0 only) - * @param bitValue : bit(s) in the port to set high - * @return None - * @note Any bit set as a '0' will not have it's state changed. This only - * applies to ports configured as an output. It is recommended to use the - * Chip_GPIO_SetPortOutHigh() function instead. - */ -STATIC INLINE void Chip_GPIO_SetValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue) -{ - pGPIO->SET[portNum] = bitValue; -} - -/** - * @brief Set selected GPIO output pins to the high state - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @param pins : pins (0..n) to set high - * @return None - * @note Any bit set as a '0' will not have it's state changed. This only - * applies to ports configured as an output. - */ -STATIC INLINE void Chip_GPIO_SetPortOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins) -{ - pGPIO->SET[port] = pins; -} - -/** - * @brief Set an individual GPIO output pin to the high state - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @param pin : pin number (0..n) to set high - * @return None - * @note Any bit set as a '0' will not have it's state changed. This only - * applies to ports configured as an output. - */ -STATIC INLINE void Chip_GPIO_SetPinOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) -{ - pGPIO->SET[port] = (1 << pin); -} - -/** - * @brief Set a GPIO port/bit to the low state - * @param pGPIO : The base of GPIO peripheral on the chip - * @param portNum : port number (support port 0 only) - * @param bitValue : bit(s) in the port to set low - * @return None - * @note Any bit set as a '0' will not have it's state changed. This only - * applies to ports configured as an output. It is recommended to use the - * Chip_GPIO_SetPortOutLow() function instead. - */ -STATIC INLINE void Chip_GPIO_ClearValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue) -{ - pGPIO->CLR[portNum] = bitValue; -} - -/** - * @brief Set selected GPIO output pins to the low state - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @param pins : pins (0..n) to set low - * @return None - * @note Any bit set as a '0' will not have it's state changed. This only - * applies to ports configured as an output. - */ -STATIC INLINE void Chip_GPIO_SetPortOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins) -{ - pGPIO->CLR[port] = pins; -} - -/** - * @brief Set an individual GPIO output pin to the low state - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @param pin : pin number (0..n) to set low - * @return None - * @note Any bit set as a '0' will not have it's state changed. This only - * applies to ports configured as an output. - */ -STATIC INLINE void Chip_GPIO_SetPinOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) -{ - pGPIO->CLR[port] = (1 << pin); -} - -/** - * @brief Toggle selected GPIO output pins to the opposite state - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @param pins : pins (0..n) to toggle - * @return None - * @note Any bit set as a '0' will not have it's state changed. This only - * applies to ports configured as an output. - */ -STATIC INLINE void Chip_GPIO_SetPortToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins) -{ - pGPIO->NOT[port] = pins; -} - -/** - * @brief Toggle an individual GPIO output pin to the opposite state - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @param pin : pin number (0..n) to toggle - * @return None - * @note Any bit set as a '0' will not have it's state changed. This only - * applies to ports configured as an output. - */ -STATIC INLINE void Chip_GPIO_SetPinToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) -{ - pGPIO->NOT[port] = (1 << pin); -} - -/** - * @brief Read current bit states for the selected port - * @param pGPIO : The base of GPIO peripheral on the chip - * @param portNum : port number to read (supports port 0 only) - * @return Current value of GPIO port - * @note The current states of the bits for the port are read, regardless of - * whether the GPIO port bits are input or output. It is recommended to use the - * Chip_GPIO_GetPortValue() function instead. - */ -STATIC INLINE uint32_t Chip_GPIO_ReadValue(LPC_GPIO_T *pGPIO, uint8_t portNum) -{ - return pGPIO->PIN[portNum]; -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __GPIO_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/gpiogroup_5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/gpiogroup_5410x.c deleted file mode 100644 index 8fa7bb45d6a..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/gpiogroup_5410x.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * @brief LPC5410x GPIO group driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/gpiogroup_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/gpiogroup_5410x.h deleted file mode 100644 index 11f781a7589..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/gpiogroup_5410x.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * @brief LPC5410x GPIO group driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __GPIOGROUP_5410X_H_ -#define __GPIOGROUP_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup GPIOGP_5410X CHIP: LPC5410x GPIO group driver - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/** - * @brief GPIO grouped interrupt register block structure - */ -typedef struct { /*!< GPIO_GROUP_INTn Structure */ - __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */ - __I uint32_t RESERVED0[7]; - __IO uint32_t PORT_POL[8]; /*!< GPIO grouped interrupt port polarity register */ - __IO uint32_t PORT_ENA[8]; /*!< GPIO grouped interrupt port m enable register */ - uint32_t RESERVED1[4072]; -} LPC_GPIOGROUPINT_T; - -/** - * LPC5410x GPIO group bit definitions - */ -#define GPIOGR_INT (1 << 0) /*!< GPIO interrupt pending/clear bit */ -#define GPIOGR_COMB (1 << 1) /*!< GPIO interrupt OR(0)/AND(1) mode bit */ -#define GPIOGR_TRIG (1 << 2) /*!< GPIO interrupt edge(0)/level(1) mode bit */ - -/** - * @brief Initialize GPIO group interrupt block - * @param pGPIOGPINT : The base of GPIO group peripheral on the chip - * @return Nothing - */ -STATIC INLINE void Chip_GPIOGP_Init(LPC_GPIOGROUPINT_T *pGPIOGPINT) -{ - Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_GINT); - Chip_SYSCON_PeriphReset(RESET_GINT); -} - -/** - * @brief De-Initialize GPIO group interrupt block - * @param pGPIOGPINT : The base of GPIO group peripheral on the chip - * @return Nothing - */ -STATIC INLINE void Chip_GPIOGP_DeInit(LPC_GPIOGROUPINT_T *pGPIOGPINT) -{ - Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_GINT); -} - -/** - * @brief Clear interrupt pending status for the selected group - * @param pGPIOGPINT : Pointer to GPIO group register block - * @param group : GPIO group number - * @return None - */ -STATIC INLINE void Chip_GPIOGP_ClearIntStatus(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group) -{ - pGPIOGPINT[group].CTRL |= GPIOGR_INT; -} - -/** - * @brief Returns current GPIO group inetrrupt pending status - * @param pGPIOGPINT : Pointer to GPIO group register block - * @param group : GPIO group number - * @return true if the group interrupt is pending, otherwise false. - */ -STATIC INLINE bool Chip_GPIOGP_GetIntStatus(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group) -{ - return (bool) ((pGPIOGPINT[group].CTRL & GPIOGR_INT) != 0); -} - -/** - * @brief Selected GPIO group functionality for trigger on any pin in group (OR mode) - * @param pGPIOGPINT : Pointer to GPIO group register block - * @param group : GPIO group number - * @return None - */ -STATIC INLINE void Chip_GPIOGP_SelectOrMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group) -{ - pGPIOGPINT[group].CTRL &= ~(GPIOGR_COMB | GPIOGR_INT); -} - -/** - * @brief Selected GPIO group functionality for trigger on all matching pins in group (AND mode) - * @param pGPIOGPINT : Pointer to GPIO group register block - * @param group : GPIO group number - * @return None - */ -STATIC INLINE void Chip_GPIOGP_SelectAndMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group) -{ - pGPIOGPINT[group].CTRL = (pGPIOGPINT[group].CTRL & ~GPIOGR_INT) | GPIOGR_COMB; -} - -/** - * @brief Selected GPIO group functionality edge trigger mode - * @param pGPIOGPINT : Pointer to GPIO group register block - * @param group : GPIO group number - * @return None - */ -STATIC INLINE void Chip_GPIOGP_SelectEdgeMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group) -{ - pGPIOGPINT[group].CTRL &= ~(GPIOGR_TRIG | GPIOGR_INT); -} - -/** - * @brief Selected GPIO group functionality level trigger mode - * @param pGPIOGPINT : Pointer to GPIO group register block - * @param group : GPIO group number - * @return None - */ -STATIC INLINE void Chip_GPIOGP_SelectLevelMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group) -{ - pGPIOGPINT[group].CTRL = (pGPIOGPINT[group].CTRL & ~GPIOGR_INT) | GPIOGR_TRIG; -} - -/** - * @brief Set selected pins for the group and port to low level trigger - * @param pGPIOGPINT : Pointer to GPIO group register block - * @param group : GPIO group number - * @param port : GPIO port number - * @param pinMask : Or'ed value of pins to select for low level (bit 0 = pin 0, 1 = pin1, etc.) - * @return None - */ -STATIC INLINE void Chip_GPIOGP_SelectLowLevel(LPC_GPIOGROUPINT_T *pGPIOGPINT, - uint8_t group, - uint8_t port, - uint32_t pinMask) -{ - pGPIOGPINT[group].PORT_POL[port] &= ~pinMask; -} - -/** - * @brief Set selected pins for the group and port to high level trigger - * @param pGPIOGPINT : Pointer to GPIO group register block - * @param group : GPIO group number - * @param port : GPIO port number - * @param pinMask : Or'ed value of pins to select for high level (bit 0 = pin 0, 1 = pin1, etc.) - * @return None - */ -STATIC INLINE void Chip_GPIOGP_SelectHighLevel(LPC_GPIOGROUPINT_T *pGPIOGPINT, - uint8_t group, - uint8_t port, - uint32_t pinMask) -{ - pGPIOGPINT[group].PORT_POL[port] |= pinMask; -} - -/** - * @brief Disabled selected pins for the group interrupt - * @param pGPIOGPINT : Pointer to GPIO group register block - * @param group : GPIO group number - * @param port : GPIO port number - * @param pinMask : Or'ed value of pins to disable interrupt for (bit 0 = pin 0, 1 = pin1, etc.) - * @return None - * @note Disabled pins do not contribute to the group interrupt. - */ -STATIC INLINE void Chip_GPIOGP_DisableGroupPins(LPC_GPIOGROUPINT_T *pGPIOGPINT, - uint8_t group, - uint8_t port, - uint32_t pinMask) -{ - pGPIOGPINT[group].PORT_ENA[port] &= ~pinMask; -} - -/** - * @brief Enable selected pins for the group interrupt - * @param pGPIOGPINT : Pointer to GPIO group register block - * @param group : GPIO group number - * @param port : GPIO port number - * @param pinMask : Or'ed value of pins to enable interrupt for (bit 0 = pin 0, 1 = pin1, etc.) - * @return None - * @note Enabled pins contribute to the group interrupt. - */ -STATIC INLINE void Chip_GPIOGP_EnableGroupPins(LPC_GPIOGROUPINT_T *pGPIOGPINT, - uint8_t group, - uint8_t port, - uint32_t pinMask) -{ - pGPIOGPINT[group].PORT_ENA[port] |= pinMask; -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __GPIOGROUP_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_adc.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_adc.c deleted file mode 100644 index 8cc8d4ef3e2..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_adc.c +++ /dev/null @@ -1,568 +0,0 @@ -/* - * @brief ADC ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include -#include "hw_adc_rom_api.h" - -/** @brief ADC ROM Driver Version */ -#define ADC_DRIVER_VERSION 0x0100 - -/* Internal defines */ -#define SEQ_A_MASK 0x7C0C5FFF -#define SEQ_B_MASK 0x5C0C5FFF -#define CTRL_MASK 0x00007F00 - -#define ADC_STATE_INACTIVE 0 -#define ADC_STATE_IDLE 1 -#define ADC_STATE_ACTIVE 2 - -/** @brief Channel flags offset */ -#define CB_THRES(ch) (1UL << (ch)) -#define CB_DATA(ch) (0x10000UL << (ch)) - -/* ADC Buffer management */ -typedef struct { - uint16_t *pCurr; /* ReceiveBuffer Pointer */ - size_t szCurr; /* Receive Count */ - uint16_t *pNext; /* Ring Buffer Pointer */ - size_t szNext; /* Receive Count */ - uint32_t idx; /* Current index */ - int32_t state; /* State of ADC */ -} ADC_BUFFER_T; - -/* ADC Driver internal data structure */ -typedef struct { - void *pUserData; /* Pointer to user data */ - ADC_REGS_T *pREGS; /* Pointer to Registers */ - uint32_t valSeq[2]; /* Stored SEQ A/B Values */ - ADC_BUFFER_T buffer[2]; /* Buffers to store converted data */ - uint32_t flags; /* flags */ - uint32_t regThrSel; /* Threshold flags */ - uint32_t regInt; /* Interrupt register */ - uint32_t flag1; /* Flags Extra */ - void(*cbTable[ADC_CBIDX_RESERVED]) (ADC_HANDLE_T, ADC_CBINDEX_T, void *); -} ADC_DRIVER_T; - -/* Prototype defines */ -static ErrorCode_t ADC_StopConversion(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex); - -/* PRIVATE: Invoke a call back function */ -static void _ADC_InvokeCallback(ADC_DRIVER_T *pADC, ADC_CBINDEX_T idx, void *param) -{ - if (pADC->cbTable[idx]) { - pADC->cbTable[idx]((ADC_HANDLE_T) pADC, idx, param); - } -} - -/* PRIVATE: Extract, format data and store into user buffer */ -static ErrorCode_t _ADC_GetData(ADC_DRIVER_T *pADC, ADC_SEQ_INDEX_T seqIndex, uint32_t data) -{ - uint8_t ch = ADC_DR_CHANNEL(data); - ADC_BUFFER_T *buf = &pADC->buffer[seqIndex]; - uint16_t *pDat = &buf->pCurr[buf->idx++]; - - /* Ignore extra data */ - if (!buf->szCurr) { - return LPC_OK; - } - - /* If data is not vaild something is wrong! */ - if (!(data & ADC_SEQ_GDAT_DATAVALID)) { - return ERR_FAILED; - } - - data >>= 4; - if (!(pADC->flag1 & (1UL << ch))) { - data &= 0xFFF; - } - - *pDat = data; - /* Invoke the call back for single data read if enabled */ - if (pADC->flags & CB_DATA(ch)) { - _ADC_InvokeCallback(pADC, ADC_CHDATA, (void *) ((ch << 16) | data)); - } - return LPC_OK; -} - -/* PRIVATE: Reads data from the GDAT or DAT register based on mode of operation */ -static ErrorCode_t _ADC_ReadData(ADC_DRIVER_T *pADC, ADC_SEQ_INDEX_T seqIndex) -{ - ADC_REGS_T *pREGS = pADC->pREGS; - int i; - - /* Check if this is End-of-Seq or End-of-SingleConversion */ - if (!(pADC->valSeq[seqIndex] & ADC_SEQ_CTRL_MODE_EOS)) { - return _ADC_GetData(pADC, seqIndex, pREGS->SEQ_GDAT[seqIndex]); - } - - /* Read channels having conversion data */ - for (i = 0; i < sizeof(pREGS->DAT) / sizeof(pREGS->DAT[0]); i++) { - if (pADC->valSeq[seqIndex] & ADC_SEQ_CTRL_CHANSEL(i)) { - if (_ADC_GetData(pADC, seqIndex, pREGS->DAT[i]) != LPC_OK) { - return ERR_FAILED; - } - } - } - return LPC_OK; -} - -/* PRIVATE: Overflow handler */ -static ErrorCode_t _ADC_Handle_Overflow(ADC_DRIVER_T *pADC, uint32_t flag) -{ - _ADC_InvokeCallback(pADC, ADC_OVERFLOW, (void *) ((flag >> 12) & 0x3FFF)); - return LPC_OK; -} - -/* PRIVATE: ADC Sequence event handler function */ -static ErrorCode_t _ADC_Handler_Seq(ADC_DRIVER_T *pADC, ADC_SEQ_INDEX_T seqIndex) -{ - ADC_REGS_T *pREGS = pADC->pREGS; - ADC_BUFFER_T *buf = &pADC->buffer[seqIndex]; - uint32_t flag = pREGS->FLAGS; - uint32_t tmp; - - /* Check if overrun is enabled and got an overrun */ - tmp = flag & ADC_FLAGS_SEQN_OVRRUN_MASK(seqIndex); - - if (!(flag & ADC_FLAGS_SEQN_INT_MASK(seqIndex))) { - return ERR_ADC_INVALID_SEQUENCE; - } - - if (_ADC_ReadData(pADC, seqIndex) != LPC_OK) { - return ERR_FAILED; - } - - /* Handle the overflow */ - if (tmp) { - _ADC_Handle_Overflow(pADC, flag); - } - - /* Clear the interrupt if it is for EOS and not EOC */ - if (pADC->valSeq[seqIndex] & ADC_SEQ_CTRL_MODE_EOS) { - pREGS->FLAGS = ADC_FLAGS_SEQN_INT_MASK(seqIndex); - } - - /* See if we are done with our buffer */ - if (buf->idx >= buf->szCurr) { - _ADC_InvokeCallback(pADC, (ADC_CBINDEX_T) (ADC_BUFFER_DONE + (ADC_CBINDEX_T)seqIndex), buf->pCurr); - if (!buf->pNext || !buf->szNext) { - buf->pCurr = 0; - buf->szCurr = 0; - - /* Nothing more to do stop the ADC */ - ADC_StopConversion(pADC, seqIndex); - return LPC_OK; - } - buf->pCurr = buf->pNext; - buf->szCurr = buf->szNext; - buf->pNext = 0; - buf->idx = buf->szNext = 0; - } - - /* If we are not in burst mode we must trigger next sample */ - if (!((pADC->valSeq[seqIndex] >> 12) & 0x1F) && !(pADC->valSeq[seqIndex] & ADC_SEQ_CTRL_BURST)) { - pREGS->SEQ_CTRL[seqIndex] = pADC->valSeq[seqIndex]; - } - - return LPC_OK; -} - -/* PRIVATE: ADC sequence handler polling mode */ -static ErrorCode_t _ADC_Handler_SeqPoll(ADC_DRIVER_T *pADC, ADC_SEQ_INDEX_T seqIndex) -{ - ADC_REGS_T *pREGS = pADC->pREGS; - ErrorCode_t ret = LPC_OK; - - /* Poll as long as the sequence is enabled */ - while (pREGS->SEQ_CTRL[seqIndex] & ADC_SEQ_CTRL_SEQ_ENA) { - if (!(pREGS->FLAGS & ADC_FLAGS_SEQN_INT_MASK(seqIndex))) { - continue; - } - ret = _ADC_Handler_Seq(pADC, seqIndex); - if (ret != LPC_OK) { - break; - } - } - return ret; -} - -/* PRIVATE: Handler for Overflow event */ -static ErrorCode_t _ADC_Handler_Ovr(ADC_DRIVER_T *pADC) -{ - uint32_t flags = pADC->pREGS->FLAGS; - - /* Invoke Sequence handler to clear-out the data */ - if (flags & ADC_FLAGS_SEQA_OVRRUN_MASK) { - return _ADC_Handler_Seq(pADC, ADC_SEQ_A); - } - else if (flags & ADC_FLAGS_SEQB_OVRRUN_MASK) { - return _ADC_Handler_Seq(pADC, ADC_SEQ_B); - } - else { - return ERR_FAILED; - } -} - -/* PRIVATE: Threshold event handler */ -static ErrorCode_t _ADC_Handler_Thres(ADC_DRIVER_T *pADC) -{ - uint32_t flags = pADC->pREGS->FLAGS; - - if (!(flags & ADC_FLAGS_THCMP_INT_MASK)) { - return ERR_FAILED; - } - - flags &= 0xFFF; - - /* Clear out the interrupts */ - pADC->pREGS->FLAGS = flags; - _ADC_InvokeCallback(pADC, ADC_THRESHOLD, (void *) flags); - - return LPC_OK; -} - -/* EXPORTED API: Register a call-back function */ -ErrorCode_t ADC_RegisterCallback(ADC_HANDLE_T hADC, ADC_CBINDEX_T idx, void (*cb_func)(ADC_HANDLE_T, - ADC_CBINDEX_T, - void *)) -{ - if (idx < ADC_CBIDX_RESERVED) { - ((ADC_DRIVER_T *) hADC)->cbTable[idx] = cb_func; - } - else { - return ERR_ADC_PARAM; - } - return LPC_OK; -} - -/* EXPORTED API: ADC Initialization function */ -ADC_HANDLE_T ADC_Init(void *mem, uint32_t base_addr, void *args) -{ - ADC_DRIVER_T *pADC; - - /* Check if the memory is word aligned */ - if ((uint32_t) mem & 0x3) { - return NULL; - } - - /* Assign memory provided by application */ - pADC = (ADC_DRIVER_T *) mem; - memset(pADC, 0, sizeof(ADC_DRIVER_T)); - - /* Assign the base address */ - pADC->pREGS = (ADC_REGS_T *) base_addr; - pADC->pUserData = args; - - /* To be safe stop the ADC in case it is not stopped */ - pADC->pREGS->SEQ_CTRL[0] = 0x00; - pADC->pREGS->SEQ_CTRL[1] = 0x00; - - return (ADC_HANDLE_T) pADC; -} - -/* EXPORTED API: Setup the ADC threshold registers */ -void ADC_SetThreshold(ADC_HANDLE_T hADC, uint32_t valThres0, uint32_t valThres1) -{ - ADC_REGS_T *pREGS = ((ADC_DRIVER_T *) hADC)->pREGS; - pREGS->THR0_LOW = (valThres0 << ADC_THR_VAL_POS) & ADC_THR_VAL_MASK; - pREGS->THR1_LOW = (valThres1 << ADC_THR_VAL_POS) & ADC_THR_VAL_MASK; - valThres0 >>= 16; - valThres1 >>= 16; - pREGS->THR0_HIGH = (valThres0 << ADC_THR_VAL_POS) & ADC_THR_VAL_MASK; - pREGS->THR1_HIGH = (valThres1 << ADC_THR_VAL_POS) & ADC_THR_VAL_MASK; -} - -/* EXPORTED API: Calibrate the ADC */ -ErrorCode_t ADC_Calibrate(ADC_HANDLE_T handle, uint32_t sysclk_freq) -{ - ADC_REGS_T *pREGS = ((ADC_DRIVER_T *) handle)->pREGS; - volatile uint32_t i; - - pREGS->STARTUP = ADC_STARTUP_ENABLE; - for ( i = 0; i < 0x10; i++ ) {} - if ( !(pREGS->STARTUP & ADC_STARTUP_ENABLE) ) { - return ERR_ADC_NO_POWER; - } - - /* If not in by-pass mode do the calibration */ - if ( (pREGS->CALIBR & ADC_CALREQD) && !(pREGS->CTRL & ADC_CR_BYPASS) ) { - uint32_t ctrl = pREGS->CTRL & (CTRL_MASK | 0xFF); - uint32_t tmp = ctrl; - - /* Set ADC to SYNC mode */ - tmp &= ~ADC_CR_ASYNC_MODE; - - /* To be safe run calibration at 1MHz UM permits upto 30MHz */ - if (sysclk_freq > 1000000UL) { - pREGS->CTRL = tmp | (((sysclk_freq / 1000000UL) - 1) & 0xFF); - } - - /* Calibration is needed, do it now. */ - pREGS->CALIBR = ADC_CALIB; - i = 0xF0000; - while ( (pREGS->CALIBR & ADC_CALIB) && --i ) {} - pREGS->CTRL = ctrl; - return i ? LPC_OK : ERR_TIME_OUT; - } - - /* A dummy conversion cycle will be performed. */ - pREGS->STARTUP = (pREGS->STARTUP | ADC_STARTUP_INIT) & 0x03; - i = 0x7FFFF; - while ( (pREGS->STARTUP & ADC_STARTUP_INIT) && --i ) {} - return i ? LPC_OK : ERR_TIME_OUT; -} - -/* EXPORTED API: Configure the ADC */ -ErrorCode_t ADC_Configure(ADC_HANDLE_T hADC, const ADC_CFG_T *pCfg) -{ - ADC_DRIVER_T *pADC = hADC; - ADC_REGS_T *pREGS = pADC->pREGS; - - pADC->valSeq[ADC_SEQ_A] = ADC_SEQ_CTRL_SEQ_ENA | ADC_SEQ_CTRL_START | (pCfg->flagSeqA & SEQ_A_MASK); - pADC->valSeq[ADC_SEQ_B] = ADC_SEQ_CTRL_SEQ_ENA | ADC_SEQ_CTRL_START | (pCfg->flagSeqB & SEQ_B_MASK); - - /* START is not required for BURST or H/W Trigger */ - if ((pCfg->flagSeqA & ADC_SEQ_CTRL_TRIGGER_MASK)) { - pADC->valSeq[ADC_SEQ_A] &= ~ADC_SEQ_CTRL_START; - } - - /* START is not required for BURST or H/W Trigger */ - if ((pCfg->flagSeqB & ADC_SEQ_CTRL_TRIGGER_MASK)) { - pADC->valSeq[ADC_SEQ_B] &= ~ADC_SEQ_CTRL_START; - } - - pREGS->CTRL = (pCfg->flagCfg & CTRL_MASK) | (pCfg->clkDiv & ADC_CR_CLKDIV_MASK); - - /* Enable/Disable overflow interrupt */ - if (pCfg->flagCfg & ENABLE_OVR) { - pADC->regInt |= ADC_INTEN_OVRRUN_ENABLE; - } - else { - pADC->regInt &= ~ADC_INTEN_OVRRUN_ENABLE; - } - - return LPC_OK; -} - -/* EXPORTED API: Configure channel specific options */ -ErrorCode_t ADC_ConfigureChannel(ADC_HANDLE_T hADC, uint32_t chanNum, uint32_t chanOpts) -{ - ADC_DRIVER_T *pADC = hADC; - - /* Sanity check */ - if (chanNum > ADC_MAX_CHANNEL_NUM) { - return ERR_ADC_PARAM; - } - - pADC->regInt &= ~(0x18 << (chanNum * 2)); - - if (chanOpts & ADC_CH_THRES_SEL1) { - pADC->regThrSel |= 1 << chanNum; - } - else { - pADC->regThrSel &= ~(1 << chanNum); - } - - if (chanOpts & ADC_CH_THRES_CROSSING) { - pADC->regInt |= 0x10 << (chanNum * 2); - } - else if (chanOpts & ADC_CH_THRES_OUTSIDE) { - pADC->regInt |= 0x08 << (chanNum * 2); - } - - if (chanOpts & ADC_CH_DATA_CALLBACK) { - pADC->flags |= CB_DATA(chanNum); - } - else { - pADC->flags &= ~CB_DATA(chanNum); - } - - if (chanOpts & ADC_CH_THRES_CALLBACK) { - pADC->flags |= CB_THRES(chanNum); - } - else { - pADC->flags &= ~CB_THRES(chanNum); - } - - if (chanOpts & ADC_CH_THRES_DATA) { - pADC->flag1 |= 1 << chanNum; - } - else { - pADC->flag1 &= ~(1 << chanNum); - } - - return LPC_OK; -} - -/* EXPORTED API: Start analog to digital conversion on selected sequence */ -ErrorCode_t ADC_StartConversion(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex, void *buff, size_t bufCount) -{ - ADC_DRIVER_T *pADC = hADC; - ADC_BUFFER_T *buf = &pADC->buffer[seqIndex]; - - /* Sanity check on parameters */ - if ((uint32_t) seqIndex > ADC_SEQ_B) { - return ERR_ADC_INVALID_SEQUENCE; - } - - /* If an active conversion is going on set the buffer ptr */ - if (buf->state == ADC_STATE_ACTIVE) { - if (buf->szNext) { - return ERR_BUSY; - } - buf->pNext = buff; - buf->szNext = bufCount; - return LPC_OK; - } - - /* Assign the buffers */ - buf->pCurr = buff; - buf->szCurr = bufCount; - buf->idx = 0; - - /* Invoke the call back before start */ - _ADC_InvokeCallback(pADC, (ADC_CBINDEX_T) (ADC_START_SEQ + (ADC_CBINDEX_T)seqIndex), (void *) &pADC->pREGS); - - buf->state = ADC_STATE_ACTIVE; - pADC->pREGS->SEQ_CTRL[seqIndex] = pADC->valSeq[seqIndex] & ~(ADC_SEQ_CTRL_SEQ_ENA | ADC_SEQ_CTRL_START); - pADC->regInt |= (1 << seqIndex); - pADC->pREGS->INTEN = pADC->regInt; - pADC->pREGS->CHAN_THRSEL = pADC->regThrSel; - pADC->pREGS->SEQ_CTRL[seqIndex] = pADC->valSeq[seqIndex]; - - return LPC_OK; -} - -ErrorCode_t ADC_SwTrigger(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex) -{ - ADC_DRIVER_T *pADC = hADC; - - /* Sanity check on parameters */ - if ((uint32_t) seqIndex > ADC_SEQ_B) { - return ERR_ADC_INVALID_SEQUENCE; - } - - pADC->pREGS->SEQ_CTRL[seqIndex] = pADC->valSeq[seqIndex] | ADC_SEQ_CTRL_SEQ_ENA | ADC_SEQ_CTRL_START; - return LPC_OK; -} - -/* EXPORTED API: Stop conversion on a given sequence */ -ErrorCode_t ADC_StopConversion(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex) -{ - ADC_DRIVER_T *pADC = hADC; - - /* Sanity check on parameters */ - if ((uint32_t) seqIndex > ADC_SEQ_B) { - return ERR_ADC_INVALID_SEQUENCE; - } - - pADC->regInt &= ~(1 << seqIndex); - pADC->pREGS->INTEN = pADC->regInt; /* Disable interrupts */ - pADC->buffer[seqIndex].state = ADC_STATE_IDLE; /* Set state to IDLE */ - - /* Stop and disable the sequence */ - pADC->pREGS->SEQ_CTRL[seqIndex] = pADC->valSeq[seqIndex] & - ~(ADC_SEQ_CTRL_SEQ_ENA | ADC_SEQ_CTRL_BURST | ADC_SEQ_CTRL_START); - _ADC_InvokeCallback(hADC, (ADC_CBINDEX_T)(ADC_STOP_SEQ + (ADC_CBINDEX_T)seqIndex), 0); - return LPC_OK; -} - -/* EXPORTED API: ADC Event handler */ -ErrorCode_t ADC_Handler(ADC_HANDLE_T hADC, ADC_HEVENT_T hEvent) -{ - ADC_DRIVER_T *pADC = hADC; - - switch (hEvent) { - case ADC_EV_SEQ_A_POLL: - return _ADC_Handler_SeqPoll(pADC, ADC_SEQ_A); - - case ADC_EV_SEQ_B_POLL: - return _ADC_Handler_SeqPoll(pADC, ADC_SEQ_B); - - case ADC_EV_SEQ_A_INT: - return _ADC_Handler_Seq(pADC, ADC_SEQ_A); - - case ADC_EV_SEQ_B_INT: - return _ADC_Handler_Seq(pADC, ADC_SEQ_B); - - case ADC_EV_SEQ_A_DMA: - if (!(pADC->valSeq[ADC_SEQ_A] & 0x3F000)) { - ADC_SwTrigger(hADC, ADC_SEQ_A); - } - return LPC_OK; - - case ADC_EV_SEQ_B_DMA: - if (!(pADC->valSeq[ADC_SEQ_B] & 0x3F000)) { - ADC_SwTrigger(hADC, ADC_SEQ_B); - } - return LPC_OK; - - case ADC_EV_OVR_INT: - return _ADC_Handler_Ovr(pADC); - - case ADC_EV_THRES_INT: - return _ADC_Handler_Thres(pADC); - - default: - return ERR_ADC_PARAM; - } -} - -/* EXPROTED API: Returns memory required for ADC driver */ -uint32_t ADC_GetMemSize(void) -{ - return sizeof(ADC_DRIVER_T); -} - -/* EXPORTED API: Function to Get the firmware Version */ -uint32_t ADC_GetDriverVersion(void) -{ - return ADC_DRIVER_VERSION; -} - -/** - * @brief Table of the addresses of all the 12-Bit ADC functions - * @note This table of function pointers is the API interface. - */ -const ROM_ADC_API_T adcrom_api = { - ADC_GetMemSize, - ADC_Init, - ADC_Configure, - ADC_ConfigureChannel, - ADC_SetThreshold, - ADC_RegisterCallback, - ADC_Calibrate, - ADC_Handler, - ADC_StartConversion, - ADC_StopConversion, - ADC_SwTrigger, - ADC_GetDriverVersion, -}; diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_adc.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_adc.h deleted file mode 100644 index a0337989a3d..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_adc.h +++ /dev/null @@ -1,243 +0,0 @@ -/* - * @brief ADC ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef _HW_ADC_H -#define _HW_ADC_H - -/******************* - * INCLUDE FILES * - ********************/ -#include - -#if defined( __CC_ARM ) - #pragma anon_unions -#endif - -/******************* - * EXPORTED MACROS * - ********************/ - -/********************* - * EXPORTED TYPEDEFS * - **********************/ -// ------------------------------------------------------------------------------------------------ -// ----- ADC ----- -// ------------------------------------------------------------------------------------------------ - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC) - */ - -typedef struct { /*!< (@ 0x40000000) ADC Structure */ - volatile uint32_t CTRL; /*!< (@ 0x40000000) A/D Control Register */ - volatile uint32_t INPUTSEL; /*!< (@ 0x40000004) A/D Input Control Register */ - union { - volatile uint32_t SEQ_CTRL[2]; - struct { - volatile uint32_t SEQA_CTRL; /*!< (@ 0x40000008) A/D SEQA Ctrl Register */ - volatile uint32_t SEQB_CTRL; /*!< (@ 0x4000000C) A/D SEQB Ctrl Register */ - }; - - }; - - union { - const volatile uint32_t SEQ_GDAT[2]; - struct { - const volatile uint32_t SEQA_GDAT; /*!< (@ 0x40000010) A/D SEQA Global Data Register */ - const volatile uint32_t SEQB_GDAT; /*!< (@ 0x40000014) A/D SEQB Global Data Register */ - }; - - }; - - uint32_t Reserved[2]; - union { - const volatile uint32_t DAT[12]; /*!< (@ 0x40000020) A/D Channel Data Register*/ - struct { - const volatile uint32_t DAT0; /*!< (@ 0x40000020) A/D Channel Data Register 0*/ - const volatile uint32_t DAT1; /*!< (@ 0x40000024) A/D Channel Data Register 1*/ - const volatile uint32_t DAT2; /*!< (@ 0x40000028) A/D Channel Data Register 2*/ - const volatile uint32_t DAT3; /*!< (@ 0x4000002C) A/D Channel Data Register 3*/ - const volatile uint32_t DAT4; /*!< (@ 0x40000030) A/D Channel Data Register 4*/ - const volatile uint32_t DAT5; /*!< (@ 0x40000034) A/D Channel Data Register 5*/ - const volatile uint32_t DAT6; /*!< (@ 0x40000038) A/D Channel Data Register 6*/ - const volatile uint32_t DAT7; /*!< (@ 0x4000003C) A/D Channel Data Register 7*/ - const volatile uint32_t DAT8; /*!< (@ 0x40000040) A/D Channel Data Register 8*/ - const volatile uint32_t DAT9; /*!< (@ 0x40000044) A/D Channel Data Register 9*/ - const volatile uint32_t DAT10; /*!< (@ 0x40000048) A/D Channel Data Register 10*/ - const volatile uint32_t DAT11; /*!< (@ 0x4000004C) A/D Channel Data Register 11*/ - }; - - }; - - union { - volatile uint32_t THR_LOW[2]; - struct { - volatile uint32_t THR0_LOW; /*!< (@ 0x40000050) A/D Low Threhold Register 0. */ - volatile uint32_t THR1_LOW; /*!< (@ 0x40000054) A/D Low Threhold Register 1. */ - }; - - }; - - union { - volatile uint32_t THR_HIGH[2]; - struct { - volatile uint32_t THR0_HIGH; /*!< (@ 0x40000058) A/D High Threhold Register 0. */ - volatile uint32_t THR1_HIGH; /*!< (@ 0x4000005C) A/D High Threhold Register 1. */ - }; - - }; - - volatile uint32_t CHAN_THRSEL; /*!< (@ 0x40000060) A/D Channel Threhold Select Register. */ - volatile uint32_t INTEN; /*!< (@ 0x40000064) A/D Interrupt Enable Register. */ - volatile uint32_t FLAGS; /*!< (@ 0x40000068) A/D Interrupt Request Flags Register. */ - volatile uint32_t STARTUP; /*!< (@ 0x4000006C) A/D Startup Register. */ - volatile uint32_t CALIBR; /*!< (@ 0x40000070) A/D Calibration Register. */ -} ADC_REGS_T; - -/** Maximum sample rate in Hz (12-bit conversions) */ -#define ADC_MAX_CHANNEL_NUM 12 - -/** - * @brief ADC register support bitfields and mask - */ -/** ADC Control register bit fields */ -#define ADC_CR_CLKDIV_MASK (0xFF << 0) /*!< Mask for Clock divider value */ -#define ADC_CR_CLKDIV_BITPOS (0) /*!< Bit position for Clock divider value */ -#define ADC_CR_ASYNC_MODE (1 << 8) -#define ADC_CR_RESOL_MASK (0x3 << 9) /*!< Two-bit mask for resolution */ -#define ADC_CR_RESOL(n) ((n) << 9) /*!< 2-bits, 6(0x0),8(0x1),10(0x2),12(0x3)-bit mode enable bit */ -#define ADC_CR_RESOL_BITPOS (9) -#define ADC_CR_BYPASS (1 << 11) /*!< Bypass mode */ -#define ADC_CR_TSAMP_MASK (0x7 << 12) /*!< Three-bit mask for Sample time */ - -/** - * @brief ADC resolution bits 9 and 10 - */ -typedef enum _ADC_RESOL_T { - ADC_RESOL_6BIT = 0, - ADC_RESOL_8BIT, - ADC_RESOL_10BIT, - ADC_RESOL_12BIT, -} ADC_RESOL_T; - -/* ADC input Select register */ -#define ADC_INPUTSEL_PIN (0x0 << 0) -#define ADC_INPUTSEL_CORE_VOL (0x1 << 0) -#define ADC_INPUTSEL_INTERNAL_VOL (0x2 << 0) -#define ADC_INPUTSEL_TEMP_VOL (0x3 << 0) - -/** ADC Sequence Control register bit fields */ -#define ADC_SEQ_CTRL_CHANSEL(n) (1 << (n)) /*!< Channel select macro */ -#define ADC_SEQ_CTRL_CHANSEL_BITPOS(n) ((n) << 0) /*!< Channel select macro */ -#define ADC_SEQ_CTRL_CHANSEL_MASK (0xFFF) /*!< Channel select mask */ - -/** SEQ_CTRL register bit fields */ -#define ADC_SEQ_CTRL_TRIGGER(n) ((n) << 12) -#define ADC_SEQ_CTRL_TRIGGER_MASK (0x1F << 12) -#define ADC_SEQ_CTRL_HWTRIG_POLPOS (1 << 18) /*!< HW trigger polarity - positive edge */ -#define ADC_SEQ_CTRL_HWTRIG_SYNCBYPASS (1 << 19) /*!< HW trigger bypass synchronisation */ -#define ADC_SEQ_CTRL_START (1 << 26) /*!< Start conversion enable bit */ -#define ADC_SEQ_CTRL_BURST (1 << 27) /*!< Repeated conversion enable bit */ -#define ADC_SEQ_CTRL_SINGLESTEP (1 << 28) /*!< Single step enable bit */ -#define ADC_SEQ_CTRL_LOWPRIO (1 << 29) /*!< High priority enable bit (regardless of name) */ -#define ADC_SEQ_CTRL_MODE_EOS (1 << 30) /*!< Mode End of sequence enable bit */ -#define ADC_SEQ_CTRL_SEQ_ENA (1UL << 31) /*!< Sequence enable bit */ - -/** ADC global data register bit fields */ -#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF << 4) /*!< Result value mask */ -#define ADC_SEQ_GDAT_RESULT_BITPOS (4) /*!< Result start bit position */ -#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x3 << 16) /*!< Comparion range mask */ -#define ADC_SEQ_GDAT_THCMPRANGE_BITPOS (16) /*!< Comparison range bit position */ -#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0x3 << 18) /*!< Comparion cross mask */ -#define ADC_SEQ_GDAT_THCMPCROSS_BITPOS (18) /*!< Comparison cross bit position */ -#define ADC_SEQ_GDAT_CHAN_MASK (0xF << 26) /*!< Channel number mask */ -#define ADC_SEQ_GDAT_CHAN_BITPOS (26) /*!< Channel number bit position */ -#define ADC_SEQ_GDAT_OVERRUN (1 << 30) /*!< Overrun bit */ -#define ADC_SEQ_GDAT_DATAVALID (1UL << 31) /*!< Data valid bit */ - -/** ADC Data register bit fields */ -#define ADC_DR_RESULT(n) ((((n) >> 4) & 0xFFF)) /*!< Macro for getting the ADC data value */ -#define ADC_DRTHR_RESULT(n) ((((n) >> 4) & 0xFFFF)) /*!< Macro for getting the ADC data value along with Threshold */ -#define ADC_DR_THCMPRANGE_MASK (0x3 << 16) /*!< Comparion range mask */ -#define ADC_DR_THCMPRANGE_BITPOS (16) /*!< Comparison range bit position */ -#define ADC_DR_THCMPRANGE(n) (((n) >> ADC_DR_THCMPRANGE_BITPOS) & 0x3) -#define ADC_DR_THCMPCROSS_MASK (0x3 << 18) /*!< Comparion cross mask */ -#define ADC_DR_THCMPCROSS_BITPOS (18) /*!< Comparison cross bit position */ -#define ADC_DR_THCMPCROSS(n) (((n) >> ADC_DR_THCMPCROSS_BITPOS) & 0x3) -#define ADC_DR_CHAN_MASK (0xF << 26) /*!< Channel number mask */ -#define ADC_DR_CHAN_BITPOS (26) /*!< Channel number bit position */ -#define ADC_DR_CHANNEL(n) (((n) >> ADC_DR_CHAN_BITPOS) & 0xF) /*!< Channel number bit position */ -#define ADC_DR_OVERRUN (1 << 30) /*!< Overrun bit */ -#define ADC_DR_DATAVALID (1UL << 31) /*!< Data valid bit */ -#define ADC_DR_DONE(n) (((n) >> 31)) - -/** ADC low/high Threshold register bit fields */ -#define ADC_THR_VAL_MASK (0xFFF << 4) /*!< Threshold value bit mask */ -#define ADC_THR_VAL_POS (4) /*!< Threshold value bit position */ - -/** ADC Threshold select register bit fields */ -#define ADC_THRSEL_CHAN_SEL_THR1(n) (1 << (n)) /*!< Select THR1 register for channel n */ - -/** ADC Interrupt Enable register bit fields */ -#define ADC_INTEN_SEQA_ENABLE (1 << 0) /*!< Sequence A Interrupt enable bit */ -#define ADC_INTEN_SEQB_ENABLE (1 << 1) /*!< Sequence B Interrupt enable bit */ -#define ADC_INTEN_SEQN_ENABLE(seq) (1 << (seq)) /*!< Sequence A/B Interrupt enable bit */ -#define ADC_INTEN_OVRRUN_ENABLE (1 << 2) /*!< Overrun Interrupt enable bit */ -#define ADC_INTEN_CMP_DISBALE (0) /*!< Disable comparison interrupt value */ -#define ADC_INTEN_CMP_OUTSIDETH (1) /*!< Outside threshold interrupt value */ -#define ADC_INTEN_CMP_CROSSTH (2) /*!< Crossing threshold interrupt value */ -#define ADC_INTEN_CMP_MASK (3) /*!< Comparison interrupt value mask */ -#define ADC_INTEN_CMP_ENABLE(isel, ch) (((isel) & ADC_INTEN_CMP_MASK) << ((2 * (ch)) + 3)) /*!< Interrupt selection for channel */ - -/** ADC Flags register bit fields */ -#define ADC_FLAGS_THCMP_MASK(ch) (1 << (ch)) /*!< Threshold comparison status for channel */ -#define ADC_FLAGS_OVRRUN_MASK(ch) (1 << (12 + (ch))) /*!< Overrun status for channel */ -#define ADC_FLAGS_SEQA_OVRRUN_MASK (1 << 24) /*!< Seq A Overrun status */ -#define ADC_FLAGS_SEQB_OVRRUN_MASK (1 << 25) /*!< Seq B Overrun status */ -#define ADC_FLAGS_SEQN_OVRRUN_MASK(seq) (1 << (24 + (seq))) /*!< Seq A/B Overrun status */ -#define ADC_FLAGS_SEQA_INT_MASK (1 << 28) /*!< Seq A Interrupt status */ -#define ADC_FLAGS_SEQB_INT_MASK (1 << 29) /*!< Seq B Interrupt status */ -#define ADC_FLAGS_SEQN_INT_MASK(seq) (1 << (28 + (seq)))/*!< Seq A/B Interrupt status */ -#define ADC_FLAGS_THCMP_INT_MASK (1 << 30) /*!< Threshold comparison Interrupt status */ -#define ADC_FLAGS_OVRRUN_INT_MASK (1UL << 31) /*!< Overrun Interrupt status */ - -/** ADC Startup register bit fields */ -#define ADC_STARTUP_ENABLE (0x1 << 0) -#define ADC_STARTUP_INIT (0x1 << 1) - -/* ADC Calibration register definition */ -#define ADC_CALIB (0x1 << 0) -#define ADC_CALREQD (0x1 << 1) - -/* Depending on the mode you are running: the slowest case is using interrupt and end of conversion while BURST mode is enabled. - For interrupt and end of sequence, the clock can be set faster. */ - -#endif /* _HW_ADCD_H Do not add any thing below this line */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_adc_rom_api.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_adc_rom_api.h deleted file mode 100644 index 7a48a663eb4..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_adc_rom_api.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * @brief ADC ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __HW_ADC_ROM_API_H -#define __HW_ADC_ROM_API_H - -#include -#include -#include "error.h" -#include "packing.h" -#include "hw_adc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup ROMAPI_ADC ADC (12-Bit) ROM driver functions and definitions - * @ingroup ROMAPI_ADC_WRAPPER - * @{ - */ - -/** @brief ADC Handler type */ -typedef void *ADC_HANDLE_T; - -/** @brief ADC SEQ Options */ -#define TRIG_SOFT (0UL << 12) /*!< Software Trigger */ -#define TRIG_PININT0 (0UL << 12) /*!< Hardware Trigger on PININT0 */ -#define TRIG_PININT1 (1UL << 12) /*!< Hardware Trigger on PININT1 */ -#define TRIG_ARMTXEV (5UL << 12) /*!< Hardware Trigger on ARM_TXEV */ -#define TRIG_POL_NEG 0 /*!< Trigger polarity is negative */ -#define TRIG_POL_POS (1UL << 18) /*!< Trigger polarity is positive */ -#define BYPASS_SYNC (1UL << 19) /*!< Bypass Synchronization Filp-Flop */ -#define MODE_BURST (1UL << 27) /*!< Enable Burst mode */ -#define MODE_SINGLE (1UL << 28) /*!< Enable Single mode */ -#define SEQA_PIRO_HIGH (1UL << 29) /*!< Set SEQA as HIGH Priority */ -#define MODE_EOC (0UL << 30) /*!< Event after end of Conversion */ -#define MODE_EOS (1UL << 30) /*!< Event after end of sequence */ -#define ENABLE_CH(ch) (1UL << (ch)) /*!< Enable the channel number */ - -/* Gets the ADC trigger from configuration */ -#define ADC_TRIGGER(cfg) (((cfg) & 0x3F000) >> 12) - -/** @brief ADC DMA source address offsets */ -#define ADC_DMA_SRC_SEQA 4 /*!< DMA Source offset for SEQ_A */ -#define ADC_DMA_SRC_SEQB 5 /*!< DMA Source offset for SEQ_B */ -#define ADC_DMA_SRC_CH0 8 /*!< DMA Source offset for CH0 */ -#define ADC_DMA_SRC_CH1 9 /*!< DMA Source offset for CH1 */ -#define ADC_DMA_SRC_CH2 10 /*!< DMA Source offset for CH2 */ -#define ADC_DMA_SRC_CH3 11 /*!< DMA Source offset for CH3 */ -#define ADC_DMA_SRC_CH4 12 /*!< DMA Source offset for CH4 */ -#define ADC_DMA_SRC_CH5 13 /*!< DMA Source offset for CH5 */ -#define ADC_DMA_SRC_CH6 14 /*!< DMA Source offset for CH6 */ -#define ADC_DMA_SRC_CH7 15 /*!< DMA Source offset for CH7 */ -#define ADC_DMA_SRC_CH8 16 /*!< DMA Source offset for CH8 */ -#define ADC_DMA_SRC_CH9 17 /*!< DMA Source offset for CH9 */ -#define ADC_DMA_SRC_CH10 18 /*!< DMA Source offset for CH10 */ -#define ADC_DMA_SRC_CH11 19 /*!< DMA Source offset for CH11 */ - -/** @brief ADC DMA Source address calculator */ -#define ADC_DMA_ADDR(ptr, src) ((*(uint32_t *) (ptr)) + ((src) << 2)) - -/** @brief ADC CTRL Options */ -#define MODE_SYNC (0UL << 8) /*!< Set ADC to synchoronous mode */ -#define MODE_ASYNC (1UL << 8) /*!< Set ADC to asynchoronous mode */ -#define RESOL_6BIT (0UL << 9) /*!< Set ADC Resolution to 6 bits */ -#define RESOL_8BIT (1UL << 9) /*!< Set ADC Resolution to 8 bits */ -#define RESOL_10BIT (2UL << 9) /*!< Set ADC Resolution to 10 bits */ -#define RESOL_12BIT (3UL << 9) /*!< Set ADC Resolution to 12 bits */ -#define BYPASS_CALIB (1UL << 11) /*!< Bypass calibration data */ -#define SAMPLE_TIME(x) (((x) & 7) << 12) /*!< Set the Sample Time to @a x */ -#define ENABLE_OVR (1UL << 24) /*!< Enable Overflow interrupt */ - -/** @brief User context conversion macro - * Macro used to extract the user defined data pointer from a ADC ROM - * driver handle.
- * To get a user context, simply use the macro on the driver's handle: - * void *pUserData = ROM_ADC_HANDLE_TOUDATA(hADC); - */ -#define ROM_ADC_HANDLE_TOUDATA(p) (void *) (*(uint32_t *) p) - -/** @brief ADC Threshold select */ -#define SEL_THRES1(ch) (1UL << (ch)) /*!< Select THRESHOLD-1 register */ -#define EN_THRES(ch) (1UL << (16 + (ch))) /*!< Enable Threshold compare */ - -/** @brief Convert DMA data to channel data */ -#define ADC_DATA_CH(data) (((data) >> 4) & 0xFFFF) - -/**@brief Threshold ranges */ -#define ADC_THRES_ABOVE 2 /*!< Threshold is above THRES_HI */ -#define ADC_THRES_BELOW 1 /*!< Threshold is below THRES_LO */ -#define ADC_THRES_INSIDE 0 /*!< Threshold is inside the range */ -#define ADC_THRES_RANGE(data) (((data) >> 12) & 0x3) /*!< Get Threshold range data */ - -/**@brief Threshold crossings */ -#define ADC_THRES_UP 3 /*!< Threshold crossing UP */ -#define ADC_THRES_DOWN 2 /*!< Threshold crossing DOWN */ -#define ADC_THRES_NONE 0 /*!< No threshold crossing */ -#define ADC_THRES_CORSS(data) (((data) >> 14) & 0x3) /*!< Get threshold crossing data */ - -/* @brief ADC Configuration data structure */ -typedef PRE_PACK struct POST_PACK { - uint32_t flagSeqA; /*!< Options for SEQ_A, like triggers, burst/single mode etc; */ - uint32_t flagSeqB; /*!< Options for SEQ_B, like triggers, burst/single mode etc; */ - uint32_t flagCfg; /*!< ADC Configuration flags, like SYNC/ASYNC mode select resolution select etc; see #MODE_SYNC, #RESOL_6BIT, #BYPASS_CALIB and #SAMPLE_TIME */ - uint32_t clkDiv; /*!< Clock divider value to be used in SYNC mode; not valid #MODE_ASYNC is present in #flagCfg */ -} ADC_CFG_T; - -/** @brief Event handler, event types */ -typedef enum { - ADC_EV_SEQ_A_POLL, /*!< SEQ_A Polling */ - ADC_EV_SEQ_B_POLL, /*!< SEQ_B Polling */ - ADC_EV_SEQ_A_INT, /*!< SEQ_A Interrupt */ - ADC_EV_SEQ_B_INT, /*!< SEQ_B Interrupt */ - ADC_EV_SEQ_A_DMA, /*!< SEQ_A DMA Event */ - ADC_EV_SEQ_B_DMA, /*!< SEQ_B DMA Event */ - ADC_EV_OVR_INT, /*!< Overflow interrupt */ - ADC_EV_THRES_INT, /*!< Threshold interrupt */ -} ADC_HEVENT_T; - -/** @brief Channel configuration options */ -#define ADC_CH_THRES_SEL1 0x01 /*!< Use THRES1 for threshold compare */ -#define ADC_CH_THRES_CALLBACK 0x02 /*!< Enable threshold callback event */ -#define ADC_CH_THRES_OUTSIDE 0x04 /*!< Enable threshold outside event */ -#define ADC_CH_THRES_CROSSING 0x08 /*!< Enable threshold crossing event */ -#define ADC_CH_DATA_CALLBACK 0x10 /*!< Enable callback for data available */ -#define ADC_CH_THRES_DATA 0x20 /*!< Add threshold value to DATA */ - -/** @brief Macros to extract information from call-back flags */ -#define ADC_OVR_SEQ_A(flag) (((flag) >> 12) & 1) /*!< Overflow in SEQ_A */ -#define ADC_OVR_SEQ_B(flag) (((flag) >> 13) & 1) /*!< Overflow in SEQ_B */ - -/** @brief Index to call-back functions */ -typedef enum { - ADC_START_SEQ, /*!< Start SEQ event */ - ADC_START_SEQ_A = ADC_START_SEQ, /*!< Start SEQ_A event */ - ADC_START_SEQ_B, /*!< Start SEQ_B event */ - ADC_STOP_SEQ, /*!< Stop SEQ event */ - ADC_STOP_SEQ_A = ADC_STOP_SEQ, /*!< Stop SEQ_A event */ - ADC_STOP_SEQ_B, /*!< Stop SEQ_B event */ - ADC_BUFFER_DONE, /*!< ADC Buffer full event */ - ADC_BUFFER_DONE_A = ADC_BUFFER_DONE, /*!< ADC Buffer full event for SEQ_A */ - ADC_BUFFER_DONE_B, /*!< ADC Buffer full event for SEQ_B */ - ADC_CHDATA, /*!< Data for Channel available */ - ADC_OVERFLOW, /*!< Over flow event */ - ADC_THRESHOLD, /*!< Threshold event */ - ADC_CBIDX_RESERVED, /*!< Reserved value (should not be used) */ -} ADC_CBINDEX_T; - -/** @brief ADC Sequence index */ -typedef enum { - ADC_SEQ_A, /*!< Index for Sequence A */ - ADC_SEQ_B, /*!< Index for Sequence B */ -} ADC_SEQ_INDEX_T; - -/** - * @brief Structure that has the API pointers in ROM Table - */ -typedef PRE_PACK struct POST_PACK { - /* Index of All the 12-Bit ADC driver APIs */ - uint32_t (*GetMemSize)(void); /*!< Returns needed memory size required for run-time context of ADC driver */ - ADC_HANDLE_T (*Init)(void *pMem, uint32_t baseAddr, void *pUserData); /*!< Initializes the ADC driver and peripheral */ - ErrorCode_t (*Configure)(ADC_HANDLE_T hADC, const ADC_CFG_T *pCfg); /*!< Configure the ADC to given parameters like resolution etc. */ - ErrorCode_t (*ConfigureCh)(ADC_HANDLE_T hADC, uint32_t chanNum, uint32_t chanOpts); /*!< Configure channel specific options */ - void (*SetThreshold)(ADC_HANDLE_T hADC, uint32_t valThr0, uint32_t valThr1);/*!< Set the threshold values for THRES0 (HIGH & LOW) and THRES1 (HIGH & LOW) */ - ErrorCode_t (*RegisterCB)(ADC_HANDLE_T hADC, ADC_CBINDEX_T cbIndex, - void (*pCbFunc)(ADC_HANDLE_T, ADC_CBINDEX_T, void *)); /*!< Registers an ADC callback function */ - ErrorCode_t (*Calibrate)(ADC_HANDLE_T hADC, uint32_t sysclk_freq); /*!< Calibrate the ADC peripheral */ - ErrorCode_t (*Handler)(ADC_HANDLE_T hADC, ADC_HEVENT_T event); /*!< ADC Event handler, should be called from the ISR */ - ErrorCode_t (*StartConversion)(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex, void *buffer, size_t bufCount); /*!< Start sampling of ADC inputs */ - ErrorCode_t (*StopConversion)(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex); /*!< Stop sampling of ADC inputs */ - ErrorCode_t (*SwTrigger)(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex); /*!< Generate a software trigger */ - uint32_t (*GetDriverVersion)(void); /*!< Get the version of the Driver Firmware in ROM */ -} ROM_ADC_API_T; - -/* Extern declaration so that application can access - * pointer to the function table - */ -extern const ROM_ADC_API_T adcrom_api; - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __HW_ADCD_ROM_API_H */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_dmaaltd.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_dmaaltd.c deleted file mode 100644 index 08ea3c5b372..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_dmaaltd.c +++ /dev/null @@ -1,624 +0,0 @@ -/* - * @brief DMA controller ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include -#include -#include "hw_dmaaltd.h" - -#define DRVVERSION 0x0100 - -typedef PRE_PACK struct POST_PACK { - uint32_t xfercfg; /*!< DMA Configuration register */ - uint32_t src; /*!< DMA source address */ - uint32_t dest; /*!< DMA destination address */ - ROM_DMA_DESC_T *pNextLink; /*!< Pointer to next descriptor link in a chain, NULL to end */ -} ROM_DMA_PRVXFERDESC_T; - -/* Private data structure used for the DMA controller driver, holds the driver and - peripheral context */ -typedef struct { - void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */ - LPC_DMA_T *base; /*!< Base address of DMA controller to use */ - ROM_DMA_PRVXFERDESC_T *sramBase; /*!< SRAM descriptor table (all channels) */ - ROM_DMA_QUEUE_T *pQueueHead; /*!< Pointer to linked list of queue descriptors */ -} DMA_DATACONTEXT_T; - -static const uint8_t mskAlign[3] = {0x0, 0x1, 0x3}; -static const uint8_t widthBytes[3] = {0x1, 0x2, 0x4}; - -#define _dma_ch_int_enable(p, ch) ((p)->DMACOMMON[0].INTENSET = (1 << (ch))) /* Enable interrupts for a channel */ -#define _dma_ch_int_disable(p, ch) ((p)->DMACOMMON[0].INTENCLR = (1 << (ch))) /* Disable interrupts for a channel */ -#define _dma_ch_enable(p, ch) ((p)->DMACOMMON[0].ENABLESET = (1 << (ch))) /* Enable a channel */ -#define _dma_ch_disable(p, ch) ((p)->DMACOMMON[0].ENABLECLR = (1 << (ch))) /* Disable a channel */ - -static void _dma_abort_ch(LPC_DMA_T *pDMA, uint8_t dmaCh) -{ - _dma_ch_disable(pDMA, dmaCh); - - /* Wait for channel to go unbusy */ - while ((pDMA->DMACOMMON[0].BUSY & (1 << dmaCh)) != 0) {} - - /* Abort */ - pDMA->DMACOMMON[0].ABORT = (1 << dmaCh); -} - -static void _dma_start_desc_chain(DMA_DATACONTEXT_T *pDrv, uint8_t dmaCh, ROM_DMA_DESC_T *pDesc) -{ - /* Switch to busy state */ - pDesc->status = ROM_DMA_DESC_STS_BUSY; - - /* Move transfer descriptor to DMA table */ - pDrv->sramBase[dmaCh].xfercfg = pDesc->xfercfg; - pDrv->sramBase[dmaCh].src = pDesc->src; - pDrv->sramBase[dmaCh].dest = pDesc->dest; - pDrv->sramBase[dmaCh].pNextLink = (ROM_DMA_DESC_T *) pDesc->pNextLink; - - /* Start transfer */ - pDrv->base->DMACH[dmaCh].XFERCFG = pDesc->xfercfg; -} - -// ********************************************************** -uint32_t dmaalt_get_mem_size(void) -{ - return sizeof(DMA_DATACONTEXT_T); -} - -ROM_DMA_HANDLE_T dmaalt_init(void *mem, const ROM_DMA_INIT_T *pInit) -{ - DMA_DATACONTEXT_T *pDrv; - - /* Verify alignment is at least 4 bytes */ - if (((uint32_t) mem & 0x3) != 0) { - return NULL; - } - - pDrv = (DMA_DATACONTEXT_T *) mem; - memset(pDrv, 0, sizeof(DMA_DATACONTEXT_T)); - - /* Save pointer to user data */ - pDrv->pUserData = pInit->pUserData; - pDrv->base = (LPC_DMA_T *) pInit->base; - pDrv->sramBase = (ROM_DMA_PRVXFERDESC_T *) pInit->sramBase; - - /* Enable DMA controller */ - pDrv->base->CTRL = 1; - pDrv->base->SRAMBASE = (uint32_t) pInit->sramBase; - - return (ROM_DMA_HANDLE_T) pDrv; -} - -ErrorCode_t dmaalt_setup_channel(ROM_DMA_HANDLE_T pHandle, ROM_DMA_CHAN_CFG_T *pCfg, uint8_t dmaCh) -{ - uint32_t cfg; - DMA_DATACONTEXT_T *pDrv = (DMA_DATACONTEXT_T *) pHandle; - - /* Parameter checks */ - if ((pCfg->burstSize > (uint32_t) ROM_DMA_BURSTPOWER_1024) || (pCfg->channelPrio > 7)) { - return ERR_DMA_PARAM; - } - - /* Enable DMA channel, clear any errors, enable interrupts */ - pDrv->base->DMACOMMON[0].ENABLECLR = (1 << dmaCh); - pDrv->base->DMACOMMON[0].ERRINT = (1 << dmaCh); - pDrv->base->DMACOMMON[0].INTA = (1 << dmaCh); - pDrv->base->DMACOMMON[0].INTB = (1 << dmaCh); - - /* Basic DMA configuration */ - if (pCfg->periphReq) { - cfg = DMA_CFG_PERIPHREQEN; - } - else { - /* Hardware triggering */ - cfg = DMA_CFG_HWTRIGEN; - cfg |= (pCfg->triggerPolHi << 4) | (pCfg->triggerLevel << 5) | (pCfg->triggerBurst << 6); - } - cfg |= (pCfg->burstSize << 8) | (pCfg->srcBurstWrap << 14) | (pCfg->dstBurstWrap << 15) | (pCfg->channelPrio << 16); - pDrv->base->DMACH[dmaCh].CFG = cfg; - - return LPC_OK; -} - -ErrorCode_t dmaalt_init_queue(ROM_DMA_HANDLE_T pHandle, uint8_t dmaCh, ROM_DMA_QUEUE_T *pQueue) -{ - DMA_DATACONTEXT_T *pDrv = (DMA_DATACONTEXT_T *) pHandle; - - /* Check queue structure alignment */ - if (((uint32_t) pQueue & 0x3) != 0) { - /* Not aligned at 4 bytes, error */ - return ERR_DMA_NOT_ALIGNMENT; - } - - memset(pQueue, 0, sizeof(ROM_DMA_QUEUE_T)); - - /* Save DMA channekl for this queue */ - pQueue->dmaCh = dmaCh; - - /* Append to existing queue */ - if (pDrv->pQueueHead) { - pQueue->pQueueHead = (struct ROM_DMA_QUEUE *) pDrv->pQueueHead; - } - pDrv->pQueueHead = pQueue; - pQueue->queueSt = (uint8_t) ROM_QUEUE_ST_IDLE; - - return LPC_OK; -} - -void dmaalt_register_queue_callback(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue, uint32_t cbIndex, void *pCB) -{ - switch (cbIndex) { - case ROM_DMA_XFERCOMPLETE_CB: - pQueue->dmaCompCB = (dmaTransferCompleteCB) pCB; - break; - - case ROM_DMA_XFERDESCCOMPLETE_CB: - pQueue->dmaDescCompCB = (dmaTransferDescCompleteCB) pCB; - break; - - case ROM_DMA_XFERERROR_CB: - pQueue->dmaErrorCB = (dmaTransferErrorCB) pCB; - break; - } -} - -ErrorCode_t dmaalt_build_descriptor_chain(ROM_DMA_HANDLE_T pHandle, - ROM_DMA_XFERDESC_CFG_T *pXferCfg, - ROM_DMA_DESC_T *pDesc, - ROM_DMA_DESC_T *pDescPrev) -{ - uint32_t cfg, xfercnt, burstSize; - uint8_t srcWrap, destWrap; - DMA_DATACONTEXT_T *pDrv = (DMA_DATACONTEXT_T *) pHandle; - - /* Parameter checks */ - if (pDesc == NULL) { - return ERR_DMA_PARAM; - } - - /* Passed descriptor must be correctly aligned */ - if (((uint32_t) pDesc & 0xF) != 0) { - return ERR_DMA_NOT_ALIGNMENT; - } - - /* Parameter checks */ - if (pXferCfg->width > (uint8_t) ROM_DMA_WIDTH_4) { - return ERR_DMA_PARAM; - } - if ((pXferCfg->srcInc > (uint8_t) ROM_DMA_ADDRINC_4X) || - (pXferCfg->dstInc > (uint8_t) ROM_DMA_ADDRINC_4X)) { - return ERR_DMA_PARAM; - } - if ((pXferCfg->xferCount < 1) || (pXferCfg->xferCount > 1024)) { - return ERR_DMA_PARAM; - } - xfercnt = pXferCfg->xferCount - 1; /* Adjust for use with DMA */ - - /* Check source and destination address alignment */ - if (((uint32_t) pXferCfg->src & mskAlign[pXferCfg->width]) != 0) { - return ERR_DMA_NOT_ALIGNMENT; - } - if (((uint32_t) pXferCfg->dest & mskAlign[pXferCfg->width]) != 0) { - return ERR_DMA_NOT_ALIGNMENT; - } - - /* Get source and destination wrap states for the channel */ - cfg = pDrv->base->DMACH[pXferCfg->dmaCh].CFG; - - /* Get burst size in datum count, used for wrap end address, offset by - (-1) for end address computation */ - burstSize = (1 << ((cfg >> 8) & 0xF)) - 1; - - /* Setup source transfer address */ - if (pXferCfg->srcInc == ROM_DMA_ADDRINC_0X) { - /* No address increment - even with burst - so source address doesn't need - to be adjusted */ - pDesc->src = (uint32_t) pXferCfg->src; - } - else { - srcWrap = (uint8_t) ((cfg & (1 << 14)) != 0); - if (srcWrap) { - /* Wrap enabled - compute end address based on burst size and datum width */ - pDesc->src = (uint32_t) pXferCfg->src + ((uint32_t) widthBytes[pXferCfg->width] * - burstSize * (1 << ((uint32_t) pXferCfg->srcInc - 1))); - } - else { - /* No wrap - compute end address based on transfer size and datum width */ - pDesc->src = (uint32_t) pXferCfg->src + ((uint32_t) widthBytes[pXferCfg->width] * - xfercnt * (1 << ((uint32_t) pXferCfg->srcInc - 1))); - } - } - - /* Setup destination transfer address */ - if (pXferCfg->dstInc == ROM_DMA_ADDRINC_0X) { - /* No address increment - even with burst - so destination address doesn't need - to be adjusted */ - pDesc->dest = (uint32_t) pXferCfg->dest; - } - else { - destWrap = (uint8_t) ((cfg & (1 << 15)) != 0); - if (destWrap) { - /* Wrap enabled - compute end address based on burst size and datum width */ - pDesc->dest = (uint32_t) pXferCfg->dest + ((uint32_t) widthBytes[pXferCfg->width] * - burstSize * (1 << ((uint32_t) pXferCfg->dstInc - 1))); - } - else { - /* No wrap - compute end address based on transfer size and datum width */ - pDesc->dest = (uint32_t) pXferCfg->dest + ((uint32_t) widthBytes[pXferCfg->width] * - xfercnt * (1 << ((uint32_t) pXferCfg->dstInc - 1))); - } - } - - /* Save pointer to user data context */ - pDesc->pUserData = pXferCfg->pUserData; - - /* Is the descriptor linked from a previous descriptor? */ - if (pDescPrev) { - pDescPrev->pNextLink = (struct ROM_DMA_DESC *) pDesc; - - if (pXferCfg->enabCirc == 0) { - pDescPrev->xfercfg &= ~(1 << 5);/* Disables INTB on previous descriptor link */ - pDescPrev->xfercfg |= (1 << 1); /* Reload on chained links */ - } - } - else { - pDesc->pNextLink = NULL; - } - - /* NULL out next chain descriptor pointers. The next chain descriptor is - managed by the queue function, while the next link descriptor indicates the end - of a chain. */ - pDesc->pNextChain = NULL; - - /* Current descriptor status is queueing. Status only applies to the first descriptor - in a chain. */ - pDesc->status = ROM_DMA_DESC_STS_QUEUEING; - pDesc->savedXferSize = pXferCfg->xferCount; - - /* Normalize parameters that are multibit to single bit */ - pXferCfg->swTrig = (pXferCfg->swTrig != 0); - pXferCfg->clrTrig = (pXferCfg->clrTrig != 0); - pXferCfg->fireDescCB = (pXferCfg->fireDescCB != 0); - - if (pXferCfg->enabCirc) { - cfg = (1 << 1); /* Reload on chained links */ - } - else { - cfg = (1 << 5); /* INTB support for completion and next descriptor */ - } - if (pXferCfg->stallDesc == 0) { - cfg |= 0x1; /* CFGVALID */ - } - - /* Setup transfer configuration */ - cfg |= (pXferCfg->swTrig << 2) | (pXferCfg->clrTrig << 3) | - (pXferCfg->fireDescCB << 4) | (pXferCfg->width << 8) | (pXferCfg->srcInc << 12) | - (pXferCfg->dstInc << 14); - cfg |= (xfercnt << 16); - pDesc->xfercfg = cfg; - - return LPC_OK; -} - -uint32_t dmaalt_get_transfer_count(ROM_DMA_HANDLE_T pHandle, ROM_DMA_DESC_T *pDesc) -{ - uint32_t dataCount = 0; - - /* Count is only valid if descriptor is used */ - while (pDesc != NULL) { - if (pDesc->status == ROM_DMA_DESC_STS_SPENT) { - dataCount += (uint32_t) pDesc->savedXferSize; - } - - pDesc = (ROM_DMA_DESC_T *) pDesc->pNextLink; - } - - return dataCount; -} - -void dmaalt_unstall_descriptor_chain(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue) -{ - DMA_DATACONTEXT_T *pDrv = (DMA_DATACONTEXT_T *) pHandle; - - pDrv->base->DMACOMMON[0].SETVALID = (1 << pQueue->dmaCh); -} - -void dmaalt_queue_descriptor(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue, ROM_DMA_DESC_T *pDescChainHead) -{ - /* Add the link to the passed descriptor to the end of the queue */ - if (pQueue->pDescEnd != NULL) { - pQueue->pDescEnd->pNextChain = (struct ROM_DMA_DESC *) pDescChainHead; - } - pQueue->pDescEnd = pDescChainHead; - - /* Next descriptor in queue */ - if (pQueue->pDescNext == NULL) { - pQueue->pDescNext = pDescChainHead; - } - - /* Descriptor is ready */ - pDescChainHead->status = ROM_DMA_DESC_STS_READY; -} - -ROM_DMA_DESC_STS_T dmaalt_get_queue_pop_descriptor_status(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue) -{ - if (pQueue->pDescPop) { - return (ROM_DMA_DESC_STS_T) pQueue->pDescPop->status; - } - - return ROM_DMA_DESC_STS_INVALID; -} - -ROM_DMA_DESC_T *dmaalt_unqueue_descriptor(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue) -{ - ROM_DMA_DESC_T *pDesc = NULL; - - /* Get current queue pop descriptor */ - if (pQueue->pDescPop) { - /* Only expired (spent, error, or aborted descriptors can be unqueued. Use StopQueue to halt all - descriptors queued. */ - if (pQueue->pDescPop->status >= ROM_DMA_DESC_STS_SPENT) { - pDesc = (ROM_DMA_DESC_T *) pQueue->pDescPop; - pQueue->pDescPop = (ROM_DMA_DESC_T *) pQueue->pDescPop->pNextChain; - } - } - - return pDesc; -} - -ErrorCode_t dmaalt_start_queue(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue) -{ - DMA_DATACONTEXT_T *pDrv = (DMA_DATACONTEXT_T *) pHandle; - - /* Is DMA already running? No need to restart */ - if ((pDrv->base->DMACOMMON[0].ACTIVE & (1 << pQueue->dmaCh)) != 0) { - return LPC_OK; - } - - /* Is queue empty? */ - if (pQueue->pDescNext == NULL) { - return ERR_DMA_QUEUE_EMPTY; - } - - /* Does the queue currently have a descriptor in it? */ - if (pQueue->pDescNext) { - /* Is current descriptor chain ready? */ - if (pQueue->pDescNext->status == ROM_DMA_DESC_STS_READY) { - /* Queue is now running */ - pQueue->queueSt = (uint8_t) ROM_QUEUE_ST_RUNNING; - - /* Enable this channel */ - _dma_ch_enable(pDrv->base, pQueue->dmaCh); - _dma_ch_int_enable(pDrv->base, pQueue->dmaCh); - - _dma_start_desc_chain(pDrv, pQueue->dmaCh, pQueue->pDescNext); - } - } - - return LPC_OK; -} - -ErrorCode_t dmaalt_stop_queue(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue) -{ - DMA_DATACONTEXT_T *pDrv = (DMA_DATACONTEXT_T *) pHandle; - ErrorCode_t error = LPC_OK; - - /* Disable interrupts for this channel */ - _dma_ch_int_disable(pDrv->base, pQueue->dmaCh); - - /* If queue is empty, no need to stop */ - if (pQueue->pDescNext == NULL) { - return LPC_OK; - } - - /* If current transfer is queued or ready, then switch it to aborted status - and call completion callback if needed. */ - if (pQueue->pDescNext->status == ROM_DMA_DESC_STS_BUSY) { - /* Abort transfer */ - _dma_abort_ch(pDrv->base, pQueue->dmaCh); - } - else if (!((pQueue->pDescNext->status == ROM_DMA_DESC_STS_QUEUEING) || - (pQueue->pDescNext->status == ROM_DMA_DESC_STS_READY))) { - /* Other statuses are not legal for a queued descriptor */ - error = ERR_DMA_GENERAL; - } - - /* Unlatch interrupts */ - pDrv->base->DMACOMMON[0].ERRINT = (1 << pQueue->dmaCh); - pDrv->base->DMACOMMON[0].INTA = (1 << pQueue->dmaCh); - pDrv->base->DMACOMMON[0].INTB = (1 << pQueue->dmaCh); - - /* Call completion callback to indicate abort state */ - pQueue->pDescNext->status = ROM_DMA_DESC_STS_ABORT; - if (pQueue->dmaCompCB) { - pQueue->dmaCompCB(pHandle, (struct ROM_DMA_QUEUE *) pQueue, pQueue->pDescNext); - } - - /* Increment to next available descriptor since this one was aborted */ - pQueue->pDescNext = (ROM_DMA_DESC_T *) pQueue->pDescNext->pNextChain; - - /* Queue is now idle */ - pQueue->queueSt = (uint8_t) ROM_QUEUE_ST_IDLE; - - return error; -} - -void dmaalt_flush_queue(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue) -{ - DMA_DATACONTEXT_T *pDrv = (DMA_DATACONTEXT_T *) pHandle; - - /* Disable interrupts for this channel */ - _dma_ch_int_disable(pDrv->base, pQueue->dmaCh); - - /* Abort transfer */ - _dma_abort_ch(pDrv->base, pQueue->dmaCh); - - /* Unlatch interrupts */ - pDrv->base->DMACOMMON[0].ERRINT = (1 << pQueue->dmaCh); - pDrv->base->DMACOMMON[0].INTA = (1 << pQueue->dmaCh); - pDrv->base->DMACOMMON[0].INTB = (1 << pQueue->dmaCh); - - /* No callbacks on abort, all descriptors flushed */ - pQueue->pDescEnd = pQueue->pDescNext = pQueue->pDescPop = NULL; - - /* Queue is now idle */ - pQueue->queueSt = (uint8_t) ROM_QUEUE_ST_IDLE; -} - -uint8_t dmaalt_get_queue_state(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue) -{ - return pQueue->queueSt; -} - -void dmaalt_force_trigger(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue) -{ - DMA_DATACONTEXT_T *pDrv = (DMA_DATACONTEXT_T *) pHandle; - - pDrv->base->DMACOMMON[0].SETTRIG = (1 << pQueue->dmaCh); -} - -// Otime = "optimize for speed of code execution" -// ...add this pragma 1 line above the interrupt service routine function. -void dmaalt_handler(ROM_DMA_HANDLE_T pHandle) -{ - uint32_t err, inta, intb, all, dmaChMask; - ROM_DMA_QUEUE_T *pQueue; - ROM_DMA_DESC_T *pDesc; - DMA_DATACONTEXT_T *pDrv = (DMA_DATACONTEXT_T *) pHandle; - uint8_t nextChain = 0; - - /* DMA interrupt fires on one of three possible events: - 1) ERROR : A DMA error has occured - Calls error callback and stops queue - 2) INTA on descriptor completion - Calls descriptor completed callback - 3) INTB on descriptor chain completion - Calls descriptor chain completion callback */ - - /* Loop through all enabled DMA channels */ - pQueue = pDrv->pQueueHead; - err = pDrv->base->DMACOMMON[0].ERRINT; - inta = pDrv->base->DMACOMMON[0].INTA; - intb = pDrv->base->DMACOMMON[0].INTB; - all = err | inta | intb; - while (pQueue) { - dmaChMask = (1 << pQueue->dmaCh); - if ((all & dmaChMask) != 0) { - /* DMA interrupt fire for this channel */ - if ((err & dmaChMask) != 0) { - /* Abort current descriptor */ - _dma_ch_int_disable(pDrv->base, pQueue->dmaCh); - _dma_abort_ch(pDrv->base, pQueue->dmaCh); - - /* Error interrupt, clear */ - pDrv->base->DMACOMMON[0].ERRINT = dmaChMask; - pDrv->base->DMACOMMON[0].INTA = dmaChMask; - pDrv->base->DMACOMMON[0].INTB = dmaChMask; - - /* Update status to error */ - pQueue->pDescNext->status = ROM_DMA_DESC_STS_ERROR; - pQueue->queueSt = (uint8_t) ROM_QUEUE_ST_ERROR; - - /* Call error callback for channel */ - if (pQueue->dmaErrorCB) { - pQueue->dmaErrorCB(pHandle, (struct ROM_DMA_QUEUE *) pQueue, pQueue->pDescNext); - } - - nextChain = 1; - } - - /* Interrupt A is used for user defined interrupt tied to a descriptor */ - if ((inta & dmaChMask) != 0) { - pDrv->base->DMACOMMON[0].INTA = dmaChMask; - - /* Call transfer descriptor completion for channel */ - if (pQueue->dmaDescCompCB) { - pQueue->dmaDescCompCB(pHandle, (struct ROM_DMA_QUEUE *) pQueue, pQueue->pDescNext); - } - } - - /* Interrupt B is used for user transfer descriptor chain completion */ - if ((intb & dmaChMask) != 0) { - pDrv->base->DMACOMMON[0].INTB = dmaChMask; - - /* Update status to spent/complete */ - pQueue->pDescNext->status = ROM_DMA_DESC_STS_SPENT; - - /* Start the next descriptor chain? */ - pDesc = (ROM_DMA_DESC_T *) pQueue->pDescNext->pNextChain; - if ((pDesc) && (pDesc->status == ROM_DMA_DESC_STS_READY)) { - /* A queued descriptor is available and ready, so start it */ - _dma_start_desc_chain(pDrv, pQueue->dmaCh, pDesc); - } - - /* Call transfer descriptor completion for channel */ - if (pQueue->dmaCompCB) { - pQueue->dmaCompCB(pHandle, (struct ROM_DMA_QUEUE *) pQueue, pQueue->pDescNext); - } - - nextChain = 1; - } - - if (nextChain) { - /* Need to save in pop queue? */ - if (pQueue->pDescPop == NULL) { - pQueue->pDescPop = pQueue->pDescNext; - } - - /* Advance to next queued descriptor */ - pQueue->pDescNext = (ROM_DMA_DESC_T *) pQueue->pDescNext->pNextChain; - if (pQueue->pDescNext == NULL) { - /* No more descriptors */ - pQueue->pDescEnd = NULL; - } - } - - all &= ~dmaChMask; - } - - /* Next queue */ - pQueue = (ROM_DMA_QUEUE_T *) pQueue->pQueueHead; - } - - if (all) { - /* Unexpected interrupts, clear and disable */ - pDrv->base->DMACOMMON[0].ENABLECLR = all; - pDrv->base->DMACOMMON[0].INTENCLR = all; - pDrv->base->DMACOMMON[0].ERRINT = all; - pDrv->base->DMACOMMON[0].INTA = all; - pDrv->base->DMACOMMON[0].INTB = all; - } -} - -uint32_t dmaalt_get_driver_version(void) -{ - return DRVVERSION; -} - -// ********************************************************* diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_dmaaltd.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_dmaaltd.h deleted file mode 100644 index 8436254fbeb..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_dmaaltd.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * @brief DMA master ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __HW_DMAALTD_H -#define __HW_DMAALTD_H - -#include "error.h" -#include "hw_dmaaltd_rom_api.h" - -// *** DMA controller functions called by Application Program *** -uint32_t dmaalt_get_mem_size(void); - -ROM_DMA_HANDLE_T dmaalt_init(void *mem, const ROM_DMA_INIT_T *pInit); - -ErrorCode_t dmaalt_setup_channel(ROM_DMA_HANDLE_T pHandle, ROM_DMA_CHAN_CFG_T *pCfg, uint8_t dmaCh); - -ErrorCode_t dmaalt_init_queue(ROM_DMA_HANDLE_T pHandle, uint8_t dmaCh, ROM_DMA_QUEUE_T *pQueue); - -void dmaalt_register_queue_callback(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue, uint32_t cbIndex, void *pCB); - -ErrorCode_t dmaalt_build_descriptor_chain(ROM_DMA_HANDLE_T pHandle, - ROM_DMA_XFERDESC_CFG_T *pXferCfg, - ROM_DMA_DESC_T *pDesc, - ROM_DMA_DESC_T *pDescPrev); - -uint32_t dmaalt_get_transfer_count(ROM_DMA_HANDLE_T pHandle, ROM_DMA_DESC_T *pDesc); - -void dmaalt_unstall_descriptor_chain(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); - -void dmaalt_queue_descriptor(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue, ROM_DMA_DESC_T *pDescChainHead); - -ROM_DMA_DESC_STS_T dmaalt_get_queue_pop_descriptor_status(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); - -ROM_DMA_DESC_T *dmaalt_unqueue_descriptor(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); - -ErrorCode_t dmaalt_start_queue(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); - -ErrorCode_t dmaalt_stop_queue(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); - -void dmaalt_flush_queue(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); - -uint8_t dmaalt_get_queue_state(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); - -void dmaalt_force_trigger(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); - -void dmaalt_handler(ROM_DMA_HANDLE_T pHandle); - -uint32_t dmaalt_get_driver_version(void); - -// *** - -#endif /* __HW_DMAALTD_H */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_dmaaltd_regs.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_dmaaltd_regs.h deleted file mode 100644 index a21602c597b..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_dmaaltd_regs.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * @brief DMA master ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __HW_DMA_REGS_H_ -#define __HW_DMA_REGS_H_ - -/** - * @brief DMA Controller shared registers structure - */ -typedef struct { /*!< DMA shared registers structure */ - volatile uint32_t ENABLESET; /*!< DMA Channel Enable read and Set for all DMA channels */ - volatile uint32_t RESERVED0; - volatile uint32_t ENABLECLR; /*!< DMA Channel Enable Clear for all DMA channels */ - volatile uint32_t RESERVED1; - volatile uint32_t ACTIVE; /*!< DMA Channel Active status for all DMA channels */ - volatile uint32_t RESERVED2; - volatile uint32_t BUSY; /*!< DMA Channel Busy status for all DMA channels */ - volatile uint32_t RESERVED3; - volatile uint32_t ERRINT; /*!< DMA Error Interrupt status for all DMA channels */ - volatile uint32_t RESERVED4; - volatile uint32_t INTENSET; /*!< DMA Interrupt Enable read and Set for all DMA channels */ - volatile uint32_t RESERVED5; - volatile uint32_t INTENCLR; /*!< DMA Interrupt Enable Clear for all DMA channels */ - volatile uint32_t RESERVED6; - volatile uint32_t INTA; /*!< DMA Interrupt A status for all DMA channels */ - volatile uint32_t RESERVED7; - volatile uint32_t INTB; /*!< DMA Interrupt B status for all DMA channels */ - volatile uint32_t RESERVED8; - volatile uint32_t SETVALID; /*!< DMA Set ValidPending control bits for all DMA channels */ - volatile uint32_t RESERVED9; - volatile uint32_t SETTRIG; /*!< DMA Set Trigger control bits for all DMA channels */ - volatile uint32_t RESERVED10; - volatile uint32_t ABORT; /*!< DMA Channel Abort control for all DMA channels */ -} LPC_DMA_COMMON_T; - -/** - * @brief DMA Controller shared registers structure - */ -typedef struct { /*!< DMA channel register structure */ - volatile uint32_t CFG; /*!< DMA Configuration register */ - volatile uint32_t CTLSTAT; /*!< DMA Control and status register */ - volatile uint32_t XFERCFG; /*!< DMA Transfer configuration register */ - volatile uint32_t RESERVED; -} LPC_DMA_CHANNEL_T; - -/* On LPC540XX, Max DMA channel is 22 */ -#define MAX_DMA_CHANNEL (22) - -/** - * @brief DMA Controller register block structure - */ -typedef struct { /*!< DMA Structure */ - volatile uint32_t CTRL; /*!< DMA control register */ - volatile uint32_t INTSTAT; /*!< DMA Interrupt status register */ - volatile uint32_t SRAMBASE; /*!< DMA SRAM address of the channel configuration table */ - volatile uint32_t RESERVED2[5]; - LPC_DMA_COMMON_T DMACOMMON[1]; /*!< DMA shared channel (common) registers */ - volatile uint32_t RESERVED0[225]; - LPC_DMA_CHANNEL_T DMACH[MAX_DMA_CHANNEL]; /*!< DMA channel registers */ -} LPC_DMA_T; - -/* DMA interrupt status bits (common) */ -#define DMA_INTSTAT_ACTIVEINT 0x2 /*!< Summarizes whether any enabled interrupts are pending */ -#define DMA_INTSTAT_ACTIVEERRINT 0x4 /*!< Summarizes whether any error interrupts are pending */ - -/* Support macro for DMA_CHDESC_T */ -#define DMA_ADDR(addr) ((uint32_t) (addr)) - -/* Support definitions for setting the configuration of a DMA channel. You - will need to get more information on these options from the User manual. */ -#define DMA_CFG_PERIPHREQEN (1 << 0) /*!< Enables Peripheral DMA requests */ -#define DMA_CFG_HWTRIGEN (1 << 1) /*!< Use hardware triggering via imput mux */ -#define DMA_CFG_TRIGPOL_LOW (0 << 4) /*!< Hardware trigger is active low or falling edge */ -#define DMA_CFG_TRIGPOL_HIGH (1 << 4) /*!< Hardware trigger is active high or rising edge */ -#define DMA_CFG_TRIGTYPE_EDGE (0 << 5) /*!< Hardware trigger is edge triggered */ -#define DMA_CFG_TRIGTYPE_LEVEL (1 << 5) /*!< Hardware trigger is level triggered */ -#define DMA_CFG_TRIGBURST_SNGL (0 << 6) /*!< Single transfer. Hardware trigger causes a single transfer */ -#define DMA_CFG_TRIGBURST_BURST (1 << 6) /*!< Burst transfer (see UM) */ -#define DMA_CFG_BURSTPOWER_1 (0 << 8) /*!< Set DMA burst size to 1 transfer */ -#define DMA_CFG_BURSTPOWER_2 (1 << 8) /*!< Set DMA burst size to 2 transfers */ -#define DMA_CFG_BURSTPOWER_4 (2 << 8) /*!< Set DMA burst size to 4 transfers */ -#define DMA_CFG_BURSTPOWER_8 (3 << 8) /*!< Set DMA burst size to 8 transfers */ -#define DMA_CFG_BURSTPOWER_16 (4 << 8) /*!< Set DMA burst size to 16 transfers */ -#define DMA_CFG_BURSTPOWER_32 (5 << 8) /*!< Set DMA burst size to 32 transfers */ -#define DMA_CFG_BURSTPOWER_64 (6 << 8) /*!< Set DMA burst size to 64 transfers */ -#define DMA_CFG_BURSTPOWER_128 (7 << 8) /*!< Set DMA burst size to 128 transfers */ -#define DMA_CFG_BURSTPOWER_256 (8 << 8) /*!< Set DMA burst size to 256 transfers */ -#define DMA_CFG_BURSTPOWER_512 (9 << 8) /*!< Set DMA burst size to 512 transfers */ -#define DMA_CFG_BURSTPOWER_1024 (10 << 8) /*!< Set DMA burst size to 1024 transfers */ -#define DMA_CFG_BURSTPOWER(n) ((n) << 8) /*!< Set DMA burst size to 2^n transfers, max n=10 */ -#define DMA_CFG_SRCBURSTWRAP (1 << 14) /*!< Source burst wrapping is enabled for this DMA channel */ -#define DMA_CFG_DSTBURSTWRAP (1 << 15) /*!< Destination burst wrapping is enabled for this DMA channel */ -#define DMA_CFG_CHPRIORITY(p) ((p) << 16) /*!< Sets DMA channel priority, min 0 (highest), max 3 (lowest) */ - -/* DMA channel control and status register definitions */ -#define DMA_CTLSTAT_VALIDPENDING (1 << 0) /*!< Valid pending flag for this channel */ -#define DMA_CTLSTAT_TRIG (1 << 2) /*!< Trigger flag. Indicates that the trigger for this channel is currently set */ - -/* DMA channel transfer configuration registers definitions */ -#define DMA_XFERCFG_CFGVALID (1 << 0) /*!< Configuration Valid flag */ -#define DMA_XFERCFG_RELOAD (1 << 1) /*!< Indicates whether the channels control structure will be reloaded when the current descriptor is exhausted */ -#define DMA_XFERCFG_SWTRIG (1 << 2) /*!< Software Trigger */ -#define DMA_XFERCFG_CLRTRIG (1 << 3) /*!< Clear Trigger */ -#define DMA_XFERCFG_SETINTA (1 << 4) /*!< Set Interrupt flag A for this channel to fire when descriptor is complete */ -#define DMA_XFERCFG_SETINTB (1 << 5) /*!< Set Interrupt flag B for this channel to fire when descriptor is complete */ -#define DMA_XFERCFG_WIDTH_8 (0 << 8) /*!< 8-bit transfers are performed */ -#define DMA_XFERCFG_WIDTH_16 (1 << 8) /*!< 16-bit transfers are performed */ -#define DMA_XFERCFG_WIDTH_32 (2 << 8) /*!< 32-bit transfers are performed */ -#define DMA_XFERCFG_SRCINC_0 (0 << 12) /*!< DMA source address is not incremented after a transfer */ -#define DMA_XFERCFG_SRCINC_1 (1 << 12) /*!< DMA source address is incremented by 1 (width) after a transfer */ -#define DMA_XFERCFG_SRCINC_2 (2 << 12) /*!< DMA source address is incremented by 2 (width) after a transfer */ -#define DMA_XFERCFG_SRCINC_4 (3 << 12) /*!< DMA source address is incremented by 4 (width) after a transfer */ -#define DMA_XFERCFG_DSTINC_0 (0 << 14) /*!< DMA destination address is not incremented after a transfer */ -#define DMA_XFERCFG_DSTINC_1 (1 << 14) /*!< DMA destination address is incremented by 1 (width) after a transfer */ -#define DMA_XFERCFG_DSTINC_2 (2 << 14) /*!< DMA destination address is incremented by 2 (width) after a transfer */ -#define DMA_XFERCFG_DSTINC_4 (3 << 14) /*!< DMA destination address is incremented by 4 (width) after a transfer */ -#define DMA_XFERCFG_XFERCOUNT(n) ((n - 1) << 16) /*!< DMA transfer count in 'transfers', between (0)1 and (1023)1024 */ - -#endif /* __HW_DMA_REGS_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_dmaaltd_rom_api.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_dmaaltd_rom_api.c deleted file mode 100644 index 03371ff6bad..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_dmaaltd_rom_api.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * @brief DMA controller ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "hw_dmaaltd.h" - -const ROM_DMAALTD_API_T dmaalt_api = { - &dmaalt_get_mem_size, - &dmaalt_init, - &dmaalt_setup_channel, - &dmaalt_init_queue, - &dmaalt_register_queue_callback, - &dmaalt_build_descriptor_chain, - &dmaalt_get_transfer_count, - &dmaalt_unstall_descriptor_chain, - &dmaalt_queue_descriptor, - &dmaalt_get_queue_pop_descriptor_status, - &dmaalt_unqueue_descriptor, - &dmaalt_start_queue, - &dmaalt_stop_queue, - &dmaalt_flush_queue, - &dmaalt_get_queue_state, - &dmaalt_force_trigger, - &dmaalt_handler, - &dmaalt_get_driver_version -}; // end of table ************************************ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_dmaaltd_rom_api.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_dmaaltd_rom_api.h deleted file mode 100644 index 5369eb503d1..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_dmaaltd_rom_api.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * @brief DMA master ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __HW_DMAALTD_ROM_API_H -#define __HW_DMAALTD_ROM_API_H - -#include "stdint.h" // added to define uint32_t, etc. -#include "error.h" -#include "packing.h" -#include "hw_dmaaltd_regs.h" - -/** @defgroup ROMAPI_DMAALT DMA controller ROM driver functions and definitions - * @ingroup ROMAPI_DMA_WRAPPER - * @{ - */ - -/** @brief DMA controller handle type */ -typedef void *ROM_DMA_HANDLE_T; - -/** @brief User context conversion macro - * Macro used to extract the user defined data pointer from a DMA controller - * handle context.
- * To get a user context, simple use the macro on the drivers handle: - * void *pUserData = (void *) ROM_DMA_HANDLE_TOUDATA(driverHandle); - */ -#define ROM_DMA_HANDLE_TOUDATA(p) (void *) (*(uint32_t *) p) - -/** @brief DMA channel mapping - * Each channel is mapped to an individual peripheral and direction or a DMA - * imput mux trigger. - */ -typedef enum { - ROM_DMAREQ_UART0_RX = 0, /*!< UART00 receive DMA channel */ - ROM_DMA_CH0 = ROM_DMAREQ_UART0_RX, - ROM_DMAREQ_UART0_TX, /*!< UART0 transmit DMA channel */ - ROM_DMA_CH1 = ROM_DMAREQ_UART0_TX, - ROM_DMAREQ_UART1_RX, /*!< UART1 receive DMA channel */ - ROM_DMA_CH2 = ROM_DMAREQ_UART1_RX, - ROM_DMAREQ_UART1_TX, /*!< UART1 transmit DMA channel */ - ROM_DMA_CH3 = ROM_DMAREQ_UART1_TX, - ROM_DMAREQ_UART2_RX, /*!< UART2 receive DMA channel */ - ROM_DMA_CH4 = ROM_DMAREQ_UART2_RX, - ROM_DMAREQ_UART2_TX, /*!< UART2 transmit DMA channel */ - ROM_DMA_CH5 = ROM_DMAREQ_UART2_TX, - ROM_DMAREQ_UART3_RX, /*!< UART3 receive DMA channel */ - ROM_DMA_CH6 = ROM_DMAREQ_UART3_RX, - ROM_DMAREQ_UART3_TX, /*!< UART3 transmit DMA channel */ - ROM_DMA_CH7 = ROM_DMAREQ_UART3_TX, - ROM_DMAREQ_SPI0_RX, /*!< SPI0 receive DMA channel */ - ROM_DMA_CH8 = ROM_DMAREQ_SPI0_RX, - ROM_DMAREQ_SPI0_TX, /*!< SPI0 transmit DMA channel */ - ROM_DMA_CH9 = ROM_DMAREQ_SPI0_TX, - ROM_DMAREQ_SPI1_RX, /*!< SPI1 receive DMA channel */ - ROM_DMA_CH10 = ROM_DMAREQ_SPI1_RX, - ROM_DMAREQ_SPI1_TX, /*!< SPI1 transmit DMA channel */ - ROM_DMA_CH11 = ROM_DMAREQ_SPI1_TX, - ROM_DMAREQ_I2C0_SLAVE, /*!< I2C0 Slave DMA channel */ - ROM_DMA_CH12 = ROM_DMAREQ_I2C0_SLAVE, - ROM_DMAREQ_I2C0_MASTER, /*!< I2C0 Master DMA channel */ - ROM_DMA_CH13 = ROM_DMAREQ_I2C0_MASTER, - ROM_DMAREQ_I2C1_SLAVE, /*!< I2C1 Slave DMA channel */ - ROM_DMA_CH14 = ROM_DMAREQ_I2C1_SLAVE, - ROM_DMAREQ_I2C1_MASTER, /*!< I2C1 Master DMA channel */ - ROM_DMA_CH15 = ROM_DMAREQ_I2C1_MASTER, - ROM_DMAREQ_I2C2_SLAVE, /*!< I2C2 Slave DMA channel */ - ROM_DMA_CH16 = ROM_DMAREQ_I2C2_SLAVE, - ROM_DMAREQ_I2C2_MASTER, /*!< I2C2 Master DMA channel */ - ROM_DMA_CH17 = ROM_DMAREQ_I2C2_MASTER, - ROM_DMAREQ_I2C0_MONITOR, /*!< I2C0 Monitor DMA channel */ - ROM_DMA_CH18 = ROM_DMAREQ_I2C0_MONITOR, - ROM_DMAREQ_I2C1_MONITOR, /*!< I2C1 Monitor DMA channel */ - ROM_DMA_CH19 = ROM_DMAREQ_I2C1_MONITOR, - ROM_DMAREQ_I2C2_MONITOR, /*!< I2C2 Monitor DMA channel */ - ROM_DMA_CH20 = ROM_DMAREQ_I2C2_MONITOR, - ROM_RESERVED_SPARE_DMA, - ROM_DMAREG_CH21 = ROM_RESERVED_SPARE_DMA, - ROM_DMALASTCHANNEL = ROM_RESERVED_SPARE_DMA, -} ROM_DMA_CHID_T; - -/** @brief Descriptor status tags */ -typedef enum { - ROM_DMA_DESC_STS_INVALID, /*!< DMA descriptor is invalid */ - ROM_DMA_DESC_STS_QUEUEING, /*!< DMA descriptor is being queued */ - ROM_DMA_DESC_STS_READY, /*!< DMA descriptor ready status */ - ROM_DMA_DESC_STS_BUSY, /*!< DMA descriptor busy status */ - ROM_DMA_DESC_STS_SPENT, /*!< DMA descriptor spent (complete) status */ - ROM_DMA_DESC_STS_ABORT, /*!< DMA descriptor aborted status */ - ROM_DMA_DESC_STS_ERROR, /*!< DMA descriptor error status */ -} ROM_DMA_DESC_STS_T; - -/** @brief DMA transfer descriptor - must be 16 byte aligned */ -struct ROM_DMA_DESC; - -typedef PRE_PACK struct POST_PACK { - uint32_t xfercfg; /*!< DMA Configuration register */ - uint32_t src; /*!< DMA source address */ - uint32_t dest; /*!< DMA destination address */ - struct ROM_DMA_DESC *pNextLink; /*!< Pointer to next descriptor link in a chain, NULL to end */ - - struct ROM_DMA_DESC *pNextChain; /*!< Pointer to next descriptor chain to process, NULL to end */ - - uint32_t status; /*!< Descriptor's current status (ROM_DMA_DESC_STS_T) */ - void *pUserData; /*!< Pointer to user data for the descriptor (chain) */ - uint16_t savedXferSize; /*!< Saved transfer size for this descriptor */ - uint16_t reserved1[1]; /*!< Needed to maintain alignment at 16 bytes */ -} ROM_DMA_DESC_T; - -/** @brief DMA controller callback IDs */ -typedef enum { - ROM_DMA_XFERCOMPLETE_CB = 0, /*!< Callback ID for DMA transfer descriptor chain complete */ - ROM_DMA_XFERDESCCOMPLETE_CB, /*!< Callback ID for DMA transfer descriptor complete */ - ROM_DMA_XFERERROR_CB, /*!< Callback ID for DMA transfer error occurance */ -} ROM_DMA_CALLBACK_T; - -struct ROM_DMA_QUEUE; - -/** @brief DMA controller transfer descriptor chain complete callback - * This callback is called from the DMA controller handler when the DMA controller - * has completed a complete transfer descriptor chain, the chain has stopped due to an error, - * or the chain has been aborted. The callback is only called if it has been registered. - */ -typedef void (*dmaTransferCompleteCB)(ROM_DMA_HANDLE_T spimHandle, struct ROM_DMA_QUEUE *pQueue, - ROM_DMA_DESC_T *pTranDesc); - -/** @brief DMA controller transfer descriptor complete callback - * This callback is called from the DMA controller handler when the DMA controller - * has completed a transfer descriptor. The callback is only called if it has been registered - * and the transfer descriptor has been enabled for interrupt operation with the fireDescCB option. - */ -typedef void (*dmaTransferDescCompleteCB)(ROM_DMA_HANDLE_T spimHandle, struct ROM_DMA_QUEUE *pQueue, - ROM_DMA_DESC_T *pTranDesc); - -/** @brief DMA controller transfer descriptor error callback - * This callback is called from the DMA controller handler when and error has occured in the - * DMA transfer. The callback is only called if it has been registered and the transfer descriptor has - * been enabled for interrupt operation. - */ -typedef void (*dmaTransferErrorCB)(ROM_DMA_HANDLE_T spimHandle, struct ROM_DMA_QUEUE *pQueue, ROM_DMA_DESC_T *pTranDesc); - -/** @brief DMA transfer queue - must be 16 byte aligned */ -typedef PRE_PACK struct POST_PACK { - dmaTransferCompleteCB dmaCompCB; /*!< Transfer descriptor chain completion callback */ - dmaTransferDescCompleteCB dmaDescCompCB; /*!< Transfer descriptor completion callback */ - dmaTransferErrorCB dmaErrorCB; /*!< Transfer error callback */ - ROM_DMA_DESC_T *pDescEnd; /*!< Pointer to last descriptor chain */ - ROM_DMA_DESC_T *pDescNext; /*!< Pointer to next descriptor chain to process */ - ROM_DMA_DESC_T *pDescPop; /*!< Pointer to first descriptor chain */ - struct ROM_DMA_QUEUE *pQueueHead; /*!< Pointer to next queue descriptor */ - - uint8_t dmaCh; /*!< DMA channel mapped to this queue (ROM_DMA_CHID_T) */ - uint8_t queueSt; /*!< Current state of this queue (ROM_DMA_QUEUE_STATES_T) */ - uint8_t reserved[2]; -} ROM_DMA_QUEUE_T; - -/** @brief DMA burst transfer sizing - */ -typedef enum { - ROM_DMA_BURSTPOWER_1 = 0, /*!< Set DMA burst size to 1 data transfer */ - ROM_DMA_BURSTPOWER_2, /*!< Set DMA burst size to 2 data transfer */ - ROM_DMA_BURSTPOWER_4, /*!< Set DMA burst size to 4 data transfer */ - ROM_DMA_BURSTPOWER_8, /*!< Set DMA burst size to 8 data transfer */ - ROM_DMA_BURSTPOWER_16, /*!< Set DMA burst size to 16 data transfer */ - ROM_DMA_BURSTPOWER_32, /*!< Set DMA burst size to 32 data transfer */ - ROM_DMA_BURSTPOWER_64, /*!< Set DMA burst size to 64 data transfer */ - ROM_DMA_BURSTPOWER_128, /*!< Set DMA burst size to 128 data transfer */ - ROM_DMA_BURSTPOWER_256, /*!< Set DMA burst size to 256 data transfer */ - ROM_DMA_BURSTPOWER_512, /*!< Set DMA burst size to 512 data transfer */ - ROM_DMA_BURSTPOWER_1024 /*!< Set DMA burst size to 1024 data transfer */ -} ROM_DMA_BURSTPOWER_T; - -/** @brief DMA transfer channel setup structure (use this structure as const if possible) */ -typedef PRE_PACK struct POST_PACK { - uint32_t periphReq : 1; /*!< 0 = hardware trigger request, !0 = peripheral request */ - uint32_t triggerPolHi : 1; /*!< 0 = low trigger polarity, !0 = high polarity, only valid if triggerReq == 0 */ - uint32_t triggerLevel : 1; /*!< 0 = edge triggered, !0 = level triggered, only valid if triggerReq == 0 */ - uint32_t triggerBurst : 1; /*!< 0 = single data transfer, !0 = burst data transfer, only valid if triggerReq == 0 */ - uint32_t burstSize : 4; /*!< Burst data transfer size, only valid if triggerReq == 0 (ROM_DMA_BURSTPOWER_T) */ - uint32_t srcBurstWrap : 1; /*!< 0 = disable source burst wrap, !0 = enable source burst wrap */ - uint32_t dstBurstWrap : 1; /*!< 0 = disable destination burst wrap, !0 = enable destination burst wrap */ - uint32_t channelPrio : 3; /*!< 0 = highest channel priority, 7 = lowest channel priority */ - uint32_t reserved : 3; -} ROM_DMA_CHAN_CFG_T; - -/** @brief DMA transfer width values - */ -typedef enum { - ROM_DMA_WIDTH_1 = 0, /*!< Transfer size of data is 8-bits (1 byte) */ - ROM_DMA_WIDTH_2, /*!< Transfer size of data is 16-bits (1 byte) */ - ROM_DMA_WIDTH_4, /*!< Transfer size of data is 32-bits (1 byte) */ -} ROM_DMA_WIDTH_T; - -/** @brief DMA source and destination address increment values - */ -typedef enum { - ROM_DMA_ADDRINC_0X = 0, /*!< No address increment, useful to reading and writing FIFOs */ - ROM_DMA_ADDRINC_1X, /*!< Address increment by width */ - ROM_DMA_ADDRINC_2X, /*!< Address increment by 2x width */ - ROM_DMA_ADDRINC_4X, /*!< Address increment by 4x width */ -} ROM_DMA_ADDRINC_T; - -/** @brief DMA transfer setup structure */ -typedef PRE_PACK struct POST_PACK { - void *src; /*!< DMA source address */ - void *dest; /*!< DMA destination address */ - void *pUserData; /*!< Pointer to user data for the descriptor (chain), this only matters for the head descriptor in a chain */ - uint16_t xferCount; /*!< DMA transfer size in size of data width (not bytes). 1 to 1024 */ - uint8_t swTrig; /*!< !0 = Software trigger of channel when descriptor is started (not recommended) */ - uint8_t clrTrig; /*!< !0 = Clear trigger when descriptor is completed */ - uint8_t fireDescCB; /*!< !0 = DMA interrupt fires after this descriptor is complete and calls descriptor complete callback */ - uint8_t enabCirc; /*!< !0 = Enable circular buffer support : Will disable completion callback */ - uint8_t width; /*!< Data transfer width (ROM_DMA_WIDTH_T) */ - uint8_t srcInc; /*!< Source address incremention (ROM_DMA_ADDRINC_T) */ - uint8_t dstInc; /*!< Destination address incremention (ROM_DMA_ADDRINC_T) */ - uint8_t dmaCh; /*!< Configured DMA channel mapped to this descriptor (ROM_DMA_CHID_T) */ - uint8_t stallDesc; /*!< Stalls this descriptor using CFGVALID before transfer, must use SETVALID to restart */ - uint8_t reserved; -} ROM_DMA_XFERDESC_CFG_T; - -/** @brief SPI master initialization structure */ -typedef PRE_PACK struct POST_PACK { - void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */ - uint32_t base; /*!< Pointer to where the DMA peripheral is located */ - uint32_t sramBase; /*!< Pointer to memory used for DMA descriptor storage, must be 512 byte aligned */ -} ROM_DMA_INIT_T; - -/** @brief Queue operating states - * These are the possible states of the DMA descriptor channel queue. - */ -typedef enum { - ROM_QUEUE_ST_IDLE = 0, /*!< DMA queue is idle. Use ROM_SET_QUEUE_START to start */ - ROM_QUEUE_ST_RUNNING, /*!< DMA queue is processing descriptor chains */ - ROM_QUEUE_ST_ERROR /*!< DMA queue is stoipped due to an error. Use ROM_SET_QUEUE_START to restart at next descriptor chain */ -} ROM_DMA_QUEUE_STATES_T; - -/** @brief SPI master ROM indirect function structure */ -typedef PRE_PACK struct POST_PACK { - /* DMA driver initialization */ - uint32_t (*GetMemSize)(void); /*!< Returns needed memory size required for run-time context of DMA controller driver */ - ROM_DMA_HANDLE_T (*Init)(void *mem, const ROM_DMA_INIT_T *pInit); /*!< Initializes the DMA controller driver and peripheral */ - - /* DMA channel setup, channel queue setup, and channel callback registration */ - ErrorCode_t (*SetupChannel)(ROM_DMA_HANDLE_T pHandle, ROM_DMA_CHAN_CFG_T *pCfg, uint8_t dmaCh); /*!< Configures a DMA channel */ - ErrorCode_t (*InitQueue)(ROM_DMA_HANDLE_T pHandle, uint8_t dmaCh, ROM_DMA_QUEUE_T *pQueue); /*!< Initializes a transfer descriptor queue for a channel */ - void (*RegisterQueueCallback)(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue, uint32_t cbIndex, void *pCB); /*!< Registers an DMA controller callback for a queue */ - - /* DMA descriptor chain build and status support */ - ErrorCode_t (*BuildDescriptorChain)(ROM_DMA_HANDLE_T pHandle, ROM_DMA_XFERDESC_CFG_T *pXferCfg, - ROM_DMA_DESC_T *pDesc, ROM_DMA_DESC_T *pDescPrev); /*!< Builds a transfer descriptor chain from the passed settings */ - uint32_t (*GetTransferCount)(ROM_DMA_HANDLE_T pHandle, ROM_DMA_DESC_T *pDesc); /*!< Returns the number of items transferred on the last descriptor chain (spent status only) */ - void (*UnstallDescriptorChain)(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); /*!< Unstalls a descriptor chain that has been setup using the stallDesc option */ - - /* DMA queue management */ - void (*QueueDescriptor)(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue, ROM_DMA_DESC_T *pDescChainHead); /*!< Queues a transfer descriptor chain */ - ROM_DMA_DESC_STS_T (*GetQueuePopDescriptorStatus)(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); /*!< Returns current status of next descriptro to be popped from the queue, ROM_DMA_DESC_STS_INVALID if no descriptors exist to be popped */ - ROM_DMA_DESC_T * (*UnQueueDescriptor)(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T * pQueue); /*!< Pops (unqueues) an expired transfer descriptor from the queue - expired descriptors are in spent, error, or abort states */ - ErrorCode_t (*StartQueue)(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); /*!< Starts or restarts a queue at the next descriptor chain */ - ErrorCode_t (*StopQueue)(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); /*!< Stops DMA and aborts current descriptor chain being processed in queue, call StartQueue to restart at the next descriptor chain */ - void (*FlushQueue)(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); /*!< Stops DMA and completely flushes a transfer queue, queue is completely reset */ - uint8_t (*GetQueueState)(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); /*!< Returns the current queue state (ROM_DMA_QUEUE_STATES_T) */ - - /* Misc */ - void (*ForceTrigger)(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); /*!< Forces a DMA transfer to trigger */ - - /* DMA queue and transfer handler - must be called from DMA interrupt or from background as fast as possible */ - void (*DMAHandler)(ROM_DMA_HANDLE_T pHandle); /*!< DMA transfer (interrupt) handler */ - - /* Driver version */ - uint32_t (*GetDriverVersion)(void); -} ROM_DMAALTD_API_T; - -/** - * @} - */ - -extern const ROM_DMAALTD_API_T dmaalt_api; // so application program can access pointer to -// function table - -#endif /* __HW_DMAALTD_ROM_API_H */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2c_common.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2c_common.h deleted file mode 100644 index 19cc07e1d1c..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2c_common.h +++ /dev/null @@ -1,201 +0,0 @@ -/* - * @brief I2C ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __HW_I2C_COMMON_H_ -#define __HW_I2C_COMMON_H_ - -/** - * @brief I2C register block structure - */ -typedef struct { /* I2C0 Structure */ - volatile uint32_t CFG; /*!< I2C Configuration Register common for Master, Slave and Monitor */ - volatile uint32_t STAT; /*!< I2C Status Register common for Master, Slave and Monitor */ - volatile uint32_t INTENSET; /*!< I2C Interrupt Enable Set Register common for Master, Slave and Monitor */ - volatile uint32_t INTENCLR; /*!< I2C Interrupt Enable Clear Register common for Master, Slave and Monitor */ - volatile uint32_t TIMEOUT; /*!< I2C Timeout value Register */ - volatile uint32_t CLKDIV; /*!< I2C Clock Divider Register */ - volatile uint32_t INTSTAT; /*!< I2C Interrupt Status Register */ - volatile uint32_t RESERVED0; - volatile uint32_t MSTCTL; /*!< I2C Master Control Register */ - volatile uint32_t MSTTIME; /*!< I2C Master Time Register for SCL */ - volatile uint32_t MSTDAT; /*!< I2C Master Data Register */ - volatile uint32_t RESERVED1[5]; - volatile uint32_t SLVCTL; /*!< I2C Slave Control Register */ - volatile uint32_t SLVDAT; /*!< I2C Slave Data Register */ - volatile uint32_t SLVADR[4]; /*!< I2C Slave Address Registers */ - volatile uint32_t SLVQUAL0; /*!< I2C Slave Address Qualifier 0 Register */ - volatile uint32_t RESERVED2[9]; - volatile uint32_t MONRXDAT; /*!< I2C Monitor Data Register */ -} LPC_I2C_T; - -/* - * @brief I2C Configuration register Bit definition - */ -#define I2C_CFG_MSTEN (1 << 0) /*!< Master Enable/Disable Bit */ -#define I2C_CFG_SLVEN (1 << 1) /*!< Slave Enable/Disable Bit */ -#define I2C_CFG_MONEN (1 << 2) /*!< Monitor Enable/Disable Bit */ -#define I2C_CFG_TIMEOUTEN (1 << 3) /*!< Timeout Enable/Disable Bit */ -#define I2C_CFG_MONCLKSTR (1 << 4) /*!< Monitor Clock Stretching Bit */ -#define I2C_CFG_MASK ((uint32_t) 0x1F) /*!< Configuration Register Mask */ - -/* - * @brief I2C Status register Bit definition - */ -#define I2C_STAT_MSTPENDING (1 << 0) /*!< Master Pending Status Bit */ -#define I2C_STAT_MSTSTATE (0x7 << 1) /*!< Master State Code */ -#define I2C_STAT_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Bit */ -#define I2C_STAT_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Bit */ -#define I2C_STAT_SLVPENDING (1 << 8) /*!< Slave Pending Status Bit */ -#define I2C_STAT_SLVSTATE (0x3 << 9) /*!< Slave State Code */ -#define I2C_STAT_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Bit */ -#define I2C_STAT_SLVIDX (0x3 << 12) /*!< Slave Address Index */ -#define I2C_STAT_SLVSEL (1 << 14) /*!< Slave Selected Bit */ -#define I2C_STAT_SLVDESEL (1 << 15) /*!< Slave Deselect Bit */ -#define I2C_STAT_MONRDY (1 << 16) /*!< Monitor Ready Bit */ -#define I2C_STAT_MONOV (1 << 17) /*!< Monitor Overflow Flag */ -#define I2C_STAT_MONACTIVE (1 << 18) /*!< Monitor Active Flag */ -#define I2C_STAT_MONIDLE (1 << 19) /*!< Monitor Idle Flag */ -#define I2C_STAT_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Flag */ -#define I2C_STAT_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Flag */ - -#define I2C_STAT_MSTCODE_IDLE (0) /*!< Master Idle State Code */ -#define I2C_STAT_MSTCODE_RXREADY (1) /*!< Master Receive Ready State Code */ -#define I2C_STAT_MSTCODE_TXREADY (2) /*!< Master Transmit Ready State Code */ -#define I2C_STAT_MSTCODE_NACKADR (3) /*!< Master NACK by slave on address State Code */ -#define I2C_STAT_MSTCODE_NACKDAT (4) /*!< Master NACK by slave on data State Code */ - -#define I2C_STAT_SLVCODE_ADDR (0) /*!< Master Idle State Code */ -#define I2C_STAT_SLVCODE_RX (1) /*!< Received data is available Code */ -#define I2C_STAT_SLVCODE_TX (2) /*!< Data can be transmitted Code */ - -/* - * @brief I2C Interrupt Enable Set register Bit definition - */ -#define I2C_INTENSET_MSTPENDING (1 << 0) /*!< Master Pending Interrupt Enable Bit */ -#define I2C_INTENSET_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Interrupt Enable Bit */ -#define I2C_INTENSET_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Interrupt Enable Bit */ -#define I2C_INTENSET_SLVPENDING (1 << 8) /*!< Slave Pending Interrupt Enable Bit */ -#define I2C_INTENSET_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Interrupt Enable Bit */ -#define I2C_INTENSET_SLVDESEL (1 << 15) /*!< Slave Deselect Interrupt Enable Bit */ -#define I2C_INTENSET_MONRDY (1 << 16) /*!< Monitor Ready Interrupt Enable Bit */ -#define I2C_INTENSET_MONOV (1 << 17) /*!< Monitor Overflow Interrupt Enable Bit */ -#define I2C_INTENSET_MONIDLE (1 << 19) /*!< Monitor Idle Interrupt Enable Bit */ -#define I2C_INTENSET_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Enable Bit */ -#define I2C_INTENSET_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Enable Bit */ - -/* - * @brief I2C Interrupt Enable Clear register Bit definition - */ -#define I2C_INTENCLR_MSTPENDING (1 << 0) /*!< Master Pending Interrupt Clear Bit */ -#define I2C_INTENCLR_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Interrupt Clear Bit */ -#define I2C_INTENCLR_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Interrupt Clear Bit */ -#define I2C_INTENCLR_SLVPENDING (1 << 8) /*!< Slave Pending Interrupt Clear Bit */ -#define I2C_INTENCLR_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Interrupt Clear Bit */ -#define I2C_INTENCLR_SLVDESEL (1 << 15) /*!< Slave Deselect Interrupt Clear Bit */ -#define I2C_INTENCLR_MONRDY (1 << 16) /*!< Monitor Ready Interrupt Clear Bit */ -#define I2C_INTENCLR_MONOV (1 << 17) /*!< Monitor Overflow Interrupt Clear Bit */ -#define I2C_INTENCLR_MONIDLE (1 << 19) /*!< Monitor Idle Interrupt Clear Bit */ -#define I2C_INTENCLR_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Clear Bit */ -#define I2C_INTENCLR_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Clear Bit */ - -/* - * @brief I2C TimeOut Value Macro - */ -#define I2C_TIMEOUT_VAL(n) (((uint32_t) ((n) - 1) & 0xFFF0) | 0x000F) /*!< Macro for Timeout value register */ - -/* - * @brief I2C Interrupt Status register Bit definition - */ -#define I2C_INTSTAT_MSTPENDING (1 << 0) /*!< Master Pending Interrupt Status Bit */ -#define I2C_INTSTAT_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Interrupt Status Bit */ -#define I2C_INTSTAT_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Interrupt Status Bit */ -#define I2C_INTSTAT_SLVPENDING (1 << 8) /*!< Slave Pending Interrupt Status Bit */ -#define I2C_INTSTAT_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Interrupt Status Bit */ -#define I2C_INTSTAT_SLVDESEL (1 << 15) /*!< Slave Deselect Interrupt Status Bit */ -#define I2C_INTSTAT_MONRDY (1 << 16) /*!< Monitor Ready Interrupt Status Bit */ -#define I2C_INTSTAT_MONOV (1 << 17) /*!< Monitor Overflow Interrupt Status Bit */ -#define I2C_INTSTAT_MONIDLE (1 << 19) /*!< Monitor Idle Interrupt Status Bit */ -#define I2C_INTSTAT_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Status Bit */ -#define I2C_INTSTAT_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Status Bit */ - -/* - * @brief I2C Master Control register Bit definition - */ -#define I2C_MSTCTL_MSTCONTINUE (1 << 0) /*!< Master Continue Bit */ -#define I2C_MSTCTL_MSTSTART (1 << 1) /*!< Master Start Control Bit */ -#define I2C_MSTCTL_MSTSTOP (1 << 2) /*!< Master Stop Control Bit */ -#define I2C_MSTCTL_MSTDMA (1 << 3) /*!< Master DMA Enable Bit */ - -/* - * @brief I2C Master Time Register Field definition - */ -#define I2C_MSTTIME_MSTSCLLOW (0x07 << 0) /*!< Master SCL Low Time field */ -#define I2C_MSTTIME_MSTSCLHIGH (0x07 << 4) /*!< Master SCL High Time field */ - -/* - * @brief I2C Master Data Mask - */ -#define I2C_MSTDAT_DATAMASK ((uint32_t) 0x00FF << 0) /*!< Master data mask */ - -/* - * @brief I2C Slave Control register Bit definition - */ -#define I2C_SLVCTL_SLVCONTINUE (1 << 0) /*!< Slave Continue Bit */ -#define I2C_SLVCTL_SLVNACK (1 << 1) /*!< Slave NACK Bit */ -#define I2C_SLVCTL_SLVDMA (1 << 3) /*!< Slave DMA Enable Bit */ - -/* - * @brief I2C Slave Data Mask - */ -#define I2C_SLVDAT_DATAMASK ((uint32_t) 0x00FF << 0) /*!< Slave data mask */ - -/* - * @brief I2C Slave Address register Bit definition - */ -#define I2C_SLVADR_SADISABLE (1 << 0) /*!< Slave Address n Disable Bit */ -#define I2C_SLVADR_SLVADR (0x7F << 1) /*!< Slave Address field */ -#define I2C_SLVADR_MASK ((uint32_t) 0x00FF) /*!< Slave Address Mask */ - -/* - * @brief I2C Slave Address Qualifier 0 Register Bit definition - */ -#define I2C_SLVQUAL_QUALMODE0 (1 << 0) /*!< Slave Qualifier Mode Enable Bit */ -#define I2C_SLVQUAL_SLVQUAL0 (0x7F << 1) /*!< Slave Qualifier Address for Address 0 */ - -/* - * @brief I2C Monitor Data Register Bit definition - */ -#define I2C_MONRXDAT_DATA (0xFF << 0) /*!< Monitor Function Receive Data Field */ -#define I2C_MONRXDAT_MONSTART (1 << 8) /*!< Monitor Received Start Bit */ -#define I2C_MONRXDAT_MONRESTART (1 << 9) /*!< Monitor Received Repeated Start Bit */ -#define I2C_MONRXDAT_MONNACK (1 << 10) /*!< Monitor Received Nack Bit */ - -#endif /* __HW_I2C_COMMON_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmd.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmd.c deleted file mode 100644 index e5578f04a49..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmd.c +++ /dev/null @@ -1,369 +0,0 @@ -/* - * @brief I2C master ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include -#include -#include "hw_i2cmd.h" - -#define DRVVERSION 0x0100 - -/* Private data structure used for the I2C master driver, holds the driver and - peripheral context */ -typedef struct { - void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */ - LPC_I2C_T *base; /*!< Base address of I2C peripheral to use */ - i2cMasterCompleteCB pXferCompCB; /*!< Transfer complete callback */ - i2cMasterTransmitStartCB pTranStartCb; /*!< Transmit data start callback */ - i2cMasterReceiveStartCB pTranRecvCb; /*!< Receive data start callback */ - ROM_I2CM_XFER_T *pXfer; /*!< Pointer to current transfer */ - ErrorCode_t pendingStatus; /*!< Pending master transfer status before clocking transfer */ - uint16_t sendIdx; - uint16_t recvIdx; -} I2CM_DATACONTEXT_T; - -#define _rom_i2cmEnable(pI2C) (pI2C->CFG |= I2C_CFG_MSTEN); -#define _rom_i2cmGetMasterState(pI2C) ((pI2C->STAT & I2C_STAT_MSTSTATE) >> 1) - -/* Sets I2C Clock Divider registers */ -static void _rom_i2cmSetClockDiv(LPC_I2C_T *pI2C, uint32_t clkdiv) -{ - if ((clkdiv >= 1) && (clkdiv <= 65536)) { - pI2C->CLKDIV = clkdiv - 1; - } - else { - pI2C->CLKDIV = 0; - } -} - -/* Sets HIGH and LOW duty cycle registers */ -static void _rom_i2cmSetDutyCycle(LPC_I2C_T *pI2C, uint16_t sclH, uint16_t sclL) -{ - /* Limit to usable range of timing values */ - if (sclH < 2) { - sclH = 2; - } - else if (sclH > 9) { - sclH = 9; - } - if (sclL < 2) { - sclL = 2; - } - else if (sclL > 9) { - sclL = 9; - } - - pI2C->MSTTIME = (((sclH - 2) & 0x07) << 4) | ((sclL - 2) & 0x07); -} - -// ********************************************************** -uint32_t i2cm_get_mem_size(void) -{ - return sizeof(I2CM_DATACONTEXT_T); -} - -ROM_I2CM_HANDLE_T i2cm_init(void *mem, const ROM_I2CM_INIT_T *pInit) -{ - I2CM_DATACONTEXT_T *pDrv; - - /* Verify alignment is at least 4 bytes */ - if (((uint32_t) mem & 0x3) != 0) { - return NULL; - } - - pDrv = (I2CM_DATACONTEXT_T *) mem; - memset(pDrv, 0, sizeof(I2CM_DATACONTEXT_T)); - - /* Save base of peripheral and pointer to user data */ - pDrv->pUserData = pInit->pUserData; - pDrv->base = (LPC_I2C_T *) pInit->base; - - /* Pick a safe clock divider until clock rate is setup */ - _rom_i2cmSetClockDiv(pDrv->base, 8); - - /* Clear pending master statuses */ - pDrv->base->STAT = (I2C_STAT_MSTRARBLOSS | I2C_STAT_MSTSTSTPERR); - - /* Enable I2C master interface */ - _rom_i2cmEnable(pDrv->base); - - return pDrv; -} - -uint32_t i2cm_set_clock_rate(ROM_I2CM_HANDLE_T pHandle, uint32_t inRate, uint32_t i2cRate) -{ - uint32_t scl, div; - I2CM_DATACONTEXT_T *pDrv = (I2CM_DATACONTEXT_T *) pHandle; - - /* Determine the best I2C clock dividers to generate the target I2C master clock */ - /* The maximum SCL and SCH dividers are 7, for a maximum divider set of 14 */ - /* The I2C master divider is between 1 and 65536. */ - - /* Pick a main I2C divider that allows centered SCL/SCH dividers */ - div = inRate / (i2cRate << 3); - if (div == 0) { - div = 1; - } - _rom_i2cmSetClockDiv(pDrv->base, div); - - /* Determine SCL/SCH dividers */ - scl = inRate / (div * i2cRate); - _rom_i2cmSetDutyCycle(pDrv->base, (scl >> 1), (scl - (scl >> 1))); - - return inRate / (div * scl); -} - -void i2cm_register_callback(ROM_I2CM_HANDLE_T pHandle, uint32_t cbIndex, void *pCB) -{ - I2CM_DATACONTEXT_T *pDrv = (I2CM_DATACONTEXT_T *) pHandle; - - if (cbIndex == ROM_I2CM_DATACOMPLETE_CB) { - pDrv->pXferCompCB = (i2cMasterCompleteCB) pCB; - } - else if (cbIndex == ROM_I2CM_DATATRANSMITSTART_CB) { - pDrv->pTranStartCb = (i2cMasterTransmitStartCB) pCB; - } - else if (cbIndex == ROM_I2CM_DATATRECEIVESTART_CB) { - pDrv->pTranRecvCb = (i2cMasterReceiveStartCB) pCB; - } -} - -ErrorCode_t i2cm_transfer(ROM_I2CM_HANDLE_T pHandle, ROM_I2CM_XFER_T *pXfer) -{ - I2CM_DATACONTEXT_T *pDrv = (I2CM_DATACONTEXT_T *) pHandle; - - /* Is transfer NULL? */ - if (pXfer == NULL) { - return ERR_I2C_PARAM; - } - - /* I2C master controller should be pending and idle */ - if ((pDrv->base->STAT & I2C_STAT_MSTPENDING) == 0) { - pXfer->status = ERR_I2C_GENERAL_FAILURE; - return ERR_I2C_GENERAL_FAILURE; - } - if (_rom_i2cmGetMasterState(pDrv->base) != I2C_STAT_MSTCODE_IDLE) { - pXfer->status = ERR_I2C_GENERAL_FAILURE; - return ERR_I2C_GENERAL_FAILURE; - } - - /* Save transfer descriptor */ - pDrv->pXfer = pXfer; - pXfer->status = ERR_I2C_BUSY; - pDrv->sendIdx = 0; - pDrv->recvIdx = 0; - - /* Pending status for completion of trasnfer */ - pDrv->pendingStatus = ERR_I2C_GENERAL_FAILURE; - - /* Clear controller state */ - pDrv->base->STAT = (I2C_STAT_MSTRARBLOSS | I2C_STAT_MSTSTSTPERR); - - /* Will always transisiton to idle at start or end of transfer */ - if (pXfer->txSz) { - /* Call transmit start callback to setup TX DMA if needed */ - if (pDrv->pTranStartCb) { - pDrv->pTranStartCb(pHandle, pXfer); - } - - /* Start transmit state */ - pDrv->base->MSTDAT = (uint32_t) (pXfer->slaveAddr << 1); - pDrv->base->MSTCTL = I2C_MSTCTL_MSTSTART; - } - else if (pXfer->rxSz) { - /* Start receive state with start ot repeat start */ - pDrv->base->MSTDAT = (uint32_t) (pXfer->slaveAddr << 1) | 0x1; - pDrv->base->MSTCTL = I2C_MSTCTL_MSTSTART; - - /* Call receive start callback to setup RX DMA if needed */ - if (pDrv->pTranRecvCb) { - pDrv->pTranRecvCb(pHandle, pXfer); - } - } - else { - /* No data - either via data callbacks or a slave query only */ - pDrv->base->MSTDAT = (uint32_t) (pXfer->slaveAddr << 1); - pDrv->base->MSTCTL = I2C_MSTCTL_MSTSTART; - } - - /* Enable supported master interrupts */ - pDrv->base->INTENSET = (I2C_INTENSET_MSTPENDING | I2C_INTENSET_MSTRARBLOSS | - I2C_INTENSET_MSTSTSTPERR); - - /* Does the driver need to block? */ - if ((pXfer->flags & ROM_I2CM_FLAG_BLOCKING) != 0) { - while (pXfer->status == ERR_I2C_BUSY) { - i2cm_transfer_handler(pHandle); - } - } - - return pXfer->status; -} - -// Otime = "optimize for speed of code execution" -// ...add this pragma 1 line above the interrupt service routine function. -void i2cm_transfer_handler(ROM_I2CM_HANDLE_T pHandle) -{ - I2CM_DATACONTEXT_T *pDrv = (I2CM_DATACONTEXT_T *) pHandle; - ROM_I2CM_XFER_T *pXfer = pDrv->pXfer; - - uint32_t status = pDrv->base->STAT; - - if (status & I2C_STAT_MSTRARBLOSS) { - /* Master Lost Arbitration */ - /* Set transfer status as Arbitration Lost */ - pDrv->pendingStatus = ERR_I2C_LOSS_OF_ARBRITRATION; - - /* Clear Status Flags */ - pDrv->base->STAT = I2C_STAT_MSTRARBLOSS; - - pDrv->base->INTENCLR = (I2C_INTENSET_MSTPENDING | I2C_INTENSET_MSTRARBLOSS | - I2C_INTENSET_MSTSTSTPERR); - pXfer->status = pDrv->pendingStatus; - if (pDrv->pXferCompCB != NULL) { - pDrv->pXferCompCB(pHandle, pXfer); - } - } - else if (status & I2C_STAT_MSTSTSTPERR) { - /* Master Start Stop Error */ - /* Set transfer status as Bus Error */ - pDrv->pendingStatus = ERR_I2C_GENERAL_FAILURE; - - /* Clear Status Flags */ - pDrv->base->STAT = I2C_STAT_MSTSTSTPERR; - - pDrv->base->INTENCLR = (I2C_INTENSET_MSTPENDING | I2C_INTENSET_MSTRARBLOSS | - I2C_INTENSET_MSTSTSTPERR); - pXfer->status = pDrv->pendingStatus; - if (pDrv->pXferCompCB != NULL) { - pDrv->pXferCompCB(pHandle, pXfer); - } - } - else if (status & I2C_STAT_MSTPENDING) { - /* Master is Pending */ - /* Branch based on Master State Code */ - switch (_rom_i2cmGetMasterState(pDrv->base)) { - case I2C_STAT_MSTCODE_IDLE: /* Master idle */ - /* Idle state is only called on completion of transfer */ - /* Disable interrupts */ - pDrv->base->INTENCLR = (I2C_INTENSET_MSTPENDING | I2C_INTENSET_MSTRARBLOSS | - I2C_INTENSET_MSTSTSTPERR); - - /* Update status and call transfer completion callback */ - pXfer->status = pDrv->pendingStatus; - if (pDrv->pXferCompCB != NULL) { - pDrv->pXferCompCB(pHandle, pXfer); - } - break; - - case I2C_STAT_MSTCODE_RXREADY: /* Receive data is available */ - if (((pXfer->flags & ROM_I2CM_FLAG_DMARX) != 0) && (pXfer->rxSz > 0)) { - /* Use DMA for receive */ - pDrv->base->MSTCTL = I2C_MSTCTL_MSTDMA; - pXfer->flags &= ~ROM_I2CM_FLAG_DMARX; - pXfer->rxSz = 0; - return; - } - else if (pXfer->rxSz) { - uint8_t *p8 = pXfer->rxBuff; - p8[pDrv->recvIdx] = (uint8_t) pDrv->base->MSTDAT & 0xFF; - pDrv->recvIdx++; - pXfer->rxSz--; - } - - if (pXfer->rxSz) { - pDrv->base->MSTCTL = I2C_MSTCTL_MSTCONTINUE; - } - else { - /* Last byte to receive, send stop after byte received */ - pDrv->base->MSTCTL = I2C_MSTCTL_MSTCONTINUE | I2C_MSTCTL_MSTSTOP; - pDrv->pendingStatus = LPC_OK; - } - break; - - case I2C_STAT_MSTCODE_TXREADY: /* Master Transmit available */ - if (((pXfer->flags & ROM_I2CM_FLAG_DMATX) != 0) && (pXfer->txSz > 0)) { - /* Use DMA for transmit */ - pDrv->base->MSTCTL = I2C_MSTCTL_MSTDMA; - pXfer->flags &= ~ROM_I2CM_FLAG_DMATX; - pXfer->txSz = 0; - return; - } - else if (pXfer->txSz) { - uint8_t *p8 = (uint8_t *) pXfer->txBuff; - /* If Tx data available transmit data and continue */ - pDrv->base->MSTDAT = (uint32_t) p8[pDrv->sendIdx]; - pDrv->base->MSTCTL = I2C_MSTCTL_MSTCONTINUE; - pDrv->sendIdx++; - pXfer->txSz--; - } - else if (pXfer->rxSz == 0) { - pDrv->base->MSTCTL = I2C_MSTCTL_MSTSTOP; - pDrv->pendingStatus = LPC_OK; - } - else { - /* Start receive state with repeat start */ - pDrv->base->MSTDAT = (uint32_t) (pXfer->slaveAddr << 1) | 0x1; - pDrv->base->MSTCTL = I2C_MSTCTL_MSTSTART; - - /* Call receive start callback to setup RX DMA if needed */ - if (pDrv->pTranRecvCb) { - pDrv->pTranRecvCb(pHandle, pXfer); - } - } - break; - - case I2C_STAT_MSTCODE_NACKADR: /* Slave address was NACK'ed */ - /* Set transfer status as NACK on address */ - pDrv->pendingStatus = ERR_I2C_SLAVE_NOT_ADDRESSED; - pDrv->base->MSTCTL = I2C_MSTCTL_MSTSTOP; - break; - - case I2C_STAT_MSTCODE_NACKDAT: /* Slave data was NACK'ed */ - /* Set transfer status as NACK on data */ - pDrv->pendingStatus = ERR_I2C_NAK; - pDrv->base->MSTCTL = I2C_MSTCTL_MSTSTOP; - break; - - default: - /* Illegal I2C master state machine case. This should never happen. - Disable and re-enable controller to clear state machine */ - pDrv->pendingStatus = ERR_I2C_GENERAL_FAILURE; - break; - } - } -} - -uint32_t i2cm_get_driver_version(void) -{ - return DRVVERSION; -} - -// ********************************************************* diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmd.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmd.h deleted file mode 100644 index f04a407c5f2..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmd.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * @brief I2C master ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __HW_I2CMD_H -#define __HW_I2CMD_H - -#include "error.h" -#include "hw_i2cmd_rom_api.h" - -// *** I2C functions called by Application Program *** -uint32_t i2cm_get_mem_size(void); - -ROM_I2CM_HANDLE_T i2cm_init(void *mem, const ROM_I2CM_INIT_T *pInit); - -uint32_t i2cm_set_clock_rate(ROM_I2CM_HANDLE_T pHandle, uint32_t inRate, uint32_t i2cRate); - -void i2cm_register_callback(ROM_I2CM_HANDLE_T pHandle, uint32_t cbIndex, void *pCB); - -ErrorCode_t i2cm_transfer(ROM_I2CM_HANDLE_T pHandle, ROM_I2CM_XFER_T *pXfer); - -void i2cm_transfer_handler(ROM_I2CM_HANDLE_T pHandle); - -uint32_t i2cm_get_driver_version(void); - -// *** - -#endif /* __HW_I2CMD_H */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmd_rom_api.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmd_rom_api.c deleted file mode 100644 index 07a3e152591..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmd_rom_api.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * @brief I2C master ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "hw_i2cmd.h" - -// This creates a table with the addresses of all the I2C functions -// This table of function pointers is the API interface. -const ROM_I2CMD_API_T i2cm_api = { - &i2cm_get_mem_size, - &i2cm_init, - &i2cm_set_clock_rate, - &i2cm_register_callback, - &i2cm_transfer, - &i2cm_transfer_handler, - &i2cm_get_driver_version, -}; // end of table ************************************ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmd_rom_api.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmd_rom_api.h deleted file mode 100644 index 0962f875fcd..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmd_rom_api.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * @brief I2C master ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __HW_I2CMD_ROM_API_H -#define __HW_I2CMD_ROM_API_H - -#include "stdint.h" // added to define uint32_t, etc. -#include "error.h" -#include "packing.h" -#include "hw_i2c_common.h" - -/** @defgroup ROMAPI_I2CM I2C master ROM driver functions and definitions - * @ingroup ROMAPI_I2CM_WRAPPER - * @{ - */ - -/** @brief I2C master handle type */ -typedef void *ROM_I2CM_HANDLE_T; - -/** @brief User context conversion macro - * Macro used to extract the user defined data pointer from a I2C master - * handle context.
- * To get a user context, simple use the macro on the drivers handle: - * void *pUserData = (void *) ROM_I2CM_HANDLE_TOUDATA(driverHandle); - */ -#define ROM_I2CM_HANDLE_TOUDATA(p) (void *) (*(uint32_t *) p) - -/** @brief I2C master optional transfer flags */ -#define ROM_I2CM_FLAG_BLOCKING (1UL << 31) /*!< Transfer function will block until complete */ -#define ROM_I2CM_FLAG_DMATX (1UL << 30) /*!< DMA will be used for TX, requires DMA setup outside of the driver */ -#define ROM_I2CM_FLAG_DMARX (1UL << 29) /*!< DMA will be used for RX, requires DMA setup outside of the driver */ -#define ROM_I2CM_FLAG_USERBITS (0xFFFF) /*!< Application can safely use the flag bits designated by this mask */ - -/** @brief Master transfer descriptor */ -typedef PRE_PACK struct POST_PACK { - const void *txBuff; /*!< Pointer to array of bytes to be transmitted */ - void *rxBuff; /*!< Pointer memory where bytes received from I2C be stored */ - volatile ErrorCode_t status; /*!< Packed status of the current I2C transfer (ErrorCode_t), must be 32-bits */ - uint32_t flags; /*!< Optional transfer flags */ - uint16_t txSz; /*!< Number of bytes in transmit array, if 0 only receive transfer will be performed */ - uint16_t rxSz; /*!< Number of bytes to receive, if 0 only transmission we be performed */ - uint16_t slaveAddr; /*!< 7-bit I2C Slave address */ - uint16_t reserved; /*!< Reserved for alignment */ -} ROM_I2CM_XFER_T; - -/** I2C master callback IDs */ -typedef enum { - ROM_I2CM_DATACOMPLETE_CB = 0, /*!< Callback ID for I2C master data transfer complete */ - ROM_I2CM_DATATRANSMITSTART_CB, /*!< Callback ID for I2C master transmit start */ - ROM_I2CM_DATATRECEIVESTART_CB /*!< Callback ID for I2C master receive start */ -} ROM_I2CM_CALLBACK_T; - -/** @brief I2C master transfer complete callback prototype - * The I2C master state machine will call this function when the transfer completes normally - * or due to an error (NAK, arbitration, etc.). - */ -typedef void (*i2cMasterCompleteCB)(ROM_I2CM_HANDLE_T i2cmHandle, ROM_I2CM_XFER_T *pXfer); - -/** @brief I2C master data receive start callback - * The I2C master state machine will call this optional function prior to data transfer. - * The callback can be used to setup DMA or alter the receive buffer size. The callback is - * only called if it has been registered and the receive size (rxSz) in the transfer descriptor - * is 0. - */ -typedef void (*i2cMasterReceiveStartCB)(ROM_I2CM_HANDLE_T i2cmHandle, ROM_I2CM_XFER_T *pXfer); - -/** @brief I2C master data transmit start callback - * The I2C master state machine will call this optional function prior to data transfer. - * The callback can be used to setup DMA or alter the transmit buffer size. The callback is - * only called if it has been registered and the transmit size (txSz) in the transfer descriptor - * is 0. - */ -typedef void (*i2cMasterTransmitStartCB)(ROM_I2CM_HANDLE_T i2cmHandle, ROM_I2CM_XFER_T *pXfer); - -/** @brief I2C master initialization structure */ -typedef PRE_PACK struct POST_PACK { - void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */ - uint32_t base; /*!< Base address of I2C peripheral to use */ -} ROM_I2CM_INIT_T; - -/** @brief I2C master ROM indirect function structure */ -typedef PRE_PACK struct POST_PACK { - uint32_t (*GetMemSize)(void); /*!< Returns needed memory size required for run-time context of I2C master driver */ - ROM_I2CM_HANDLE_T (*Init)(void *mem, const ROM_I2CM_INIT_T *pInit); /*!< Initializes the I2C master driver and peripheral */ - uint32_t (*SetClockRate)(ROM_I2CM_HANDLE_T pHandle, uint32_t inRate, uint32_t i2cRate); /*!< Sets the I2C master clock rate */ - void (*RegisterCallback)(ROM_I2CM_HANDLE_T pHandle, uint32_t cbIndex, void *pCB); /*!< Registers an I2C master callback */ - ErrorCode_t (*Transfer)(ROM_I2CM_HANDLE_T pHandle, ROM_I2CM_XFER_T *pXfer); /*!< Perform or start and I2C master transfer */ - void (*TransferHandler)(ROM_I2CM_HANDLE_T pHandle); /*!< I2C master transfer (interrupt) handler */ - uint32_t (*GetDriverVersion)(void); -} ROM_I2CMD_API_T; - -/** - * @} - */ - -extern const ROM_I2CMD_API_T i2cm_api; // so application program can access pointer to -// function table - -#endif /* __HW_I2CMD_ROM_API_H */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmond.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmond.c deleted file mode 100644 index 4f7aa8c5e9d..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmond.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * @brief I2C monitor ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include -#include -#include "hw_i2cmond.h" - -#define DRVVERSION 0x0100 - -/* Private data structure used for the I2C monitor driver, holds the driver and - peripheral context */ -typedef struct { - void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */ - LPC_I2C_T *base; /*!< Base address of I2C peripheral to use */ - i2cMonCapReadyCB pCapCompCB; /*!< Capture complete callback */ - i2cMonSetupDMACB pDmaSetupCB; /*!< DMA setup callback */ - ROM_I2CMON_CAP_T *pCap; /*!< Pointer to current capture descriptor */ - ErrorCode_t pendingStatus; /*!< Pending monitor transfer status before clocking transfer */ -} I2CMON_DATACONTEXT_T; - -void i2cmon_transfer_handler(ROM_I2CMON_HANDLE_T pHandle) -; - -/* ********************************************************** */ -uint32_t i2cmon_get_mem_size(void) -{ - return sizeof(I2CMON_DATACONTEXT_T); -} - -ROM_I2CMON_HANDLE_T i2cmon_init(void *mem, const ROM_I2CMON_INIT_T *pInit) -{ - I2CMON_DATACONTEXT_T *pDrv; - uint32_t reg; - - /* Verify alignment is at least 4 bytes */ - if (((uint32_t) mem & 0x3) != 0) - { - return NULL; - } - - pDrv = (I2CMON_DATACONTEXT_T *) mem; - memset(pDrv, 0, sizeof(I2CMON_DATACONTEXT_T)); - - /* Save base of peripheral and pointer to user data */ - pDrv->pUserData = pInit->pUserData; - pDrv->base = (LPC_I2C_T *) pInit->base; - - /* Clear pending monitor statuses */ - pDrv->base->STAT = (I2C_STAT_MONIDLE | I2C_STAT_MONOV); - while ((pDrv->base->STAT & I2C_STAT_MONRDY) != 0) - { - /* Toss input data */ - reg = pDrv->base->MONRXDAT; - } - - /* Enable I2C monitor interface */ - reg = pDrv->base->CFG | I2C_CFG_MONEN; - if (pInit->stretch != 0) - { - reg |= I2C_CFG_MONCLKSTR; - } - pDrv->base->CFG = reg; - - return pDrv; -} - -void i2cmom_register_callback(ROM_I2CMON_HANDLE_T pHandle, uint32_t cbIndex, void *pCB) -{ - I2CMON_DATACONTEXT_T *pDrv = (I2CMON_DATACONTEXT_T *) pHandle; - - if (cbIndex == ROM_I2CMON_CAPTUREREADY_CB) - { - pDrv->pCapCompCB = (i2cMonCapReadyCB) pCB; - } - else if (cbIndex == ROM_I2CMON_DMASETUP_CB) - { - pDrv->pDmaSetupCB = (i2cMonSetupDMACB) pCB; - } -} - -ErrorCode_t i2cmom_start_log(ROM_I2CMON_HANDLE_T pHandle, ROM_I2CMON_CAP_T *pCap) -{ - I2CMON_DATACONTEXT_T *pDrv = (I2CMON_DATACONTEXT_T *) pHandle; - - /* I2C master controller should be pending and idle */ - if (pCap == NULL) - { - return ERR_I2C_PARAM; - } - - /* Verify receive buffer alignment */ - if ((pCap->startBuff == NULL) || ((((uint32_t) pCap->startBuff) & 0x1) != 0) || (pCap->startBuffSz == 0)) - { - pCap->status = ERR_I2C_PARAM; - return ERR_I2C_PARAM; - } - - pDrv->pCap = pCap; - pCap->capStartBuffSz = 0; - pDrv->pendingStatus = LPC_OK; - pCap->status = ERR_I2C_BUSY; - - if ((pCap->flags & ROM_I2CMON_FLAG_FLUSH) != 0) - { - while ((pDrv->base->STAT & I2C_STAT_MONRDY) != 0) - { - /* Toss input data */ - volatile uint32_t reg = pDrv->base->MONRXDAT; - (void)reg; - } - } - - /* Clear controller state */ - pDrv->base->STAT = (I2C_STAT_MONIDLE | I2C_STAT_MONOV); - - if (((pCap->flags & ROM_I2CMON_FLAG_DMARX) != 0) && (pDrv->pDmaSetupCB)) - { - pDrv->pDmaSetupCB(pHandle, pCap); - - /* Enable supported monitor interrupts */ - pDrv->base->INTENSET = (I2C_INTENSET_MONOV | I2C_INTENSET_MONIDLE); - } - else { - pCap->flags &= ~ROM_I2CMON_FLAG_DMARX; - - /* Enable supported monitor interrupts */ - pDrv->base->INTENSET = (I2C_INTENSET_MONRDY | I2C_INTENSET_MONOV | I2C_INTENSET_MONIDLE); - } - - /* Is transfer blocking? */ - if ((pCap->flags & ROM_I2CMON_FLAG_BLOCKING) != 0) - { - while (pCap->status == ERR_I2C_BUSY) - { - i2cmon_transfer_handler(pHandle); - } - } - - return pCap->status; -} - -/* Otime = "optimize for speed of code execution"*/ -/* ...add this pragma 1 line above the interrupt service routine function.*/ -void i2cmon_transfer_handler(ROM_I2CMON_HANDLE_T pHandle) -{ - I2CMON_DATACONTEXT_T *pDrv = (I2CMON_DATACONTEXT_T *) pHandle; - ROM_I2CMON_CAP_T *pCap = pDrv->pCap; - uint16_t data = 0, *pData; - - uint32_t status = pDrv->base->STAT; - - if (status & I2C_STAT_MONOV) - { - /* Monitor data overflow */ - data = pDrv->base->MONRXDAT; - pDrv->pendingStatus = ERR_I2C_BUFFER_OVERFLOW; - - /* Clear Status Flags */ - pDrv->base->STAT = I2C_STAT_MONOV; - } - else if (status & I2C_STAT_MONRDY) - { - /* Monitor ready */ - data = pDrv->base->MONRXDAT; - - /* Enough room to place this data? */ - if (pCap->capStartBuffSz >= pCap->startBuffSz) - { - /* Data overflow */ - pDrv->pendingStatus = ERR_I2C_BUFFER_OVERFLOW; - } - else { - pData = (uint16_t *) pCap->startBuff; - - pData[pCap->capStartBuffSz] = data; - pCap->capStartBuffSz++; - } - } - - /* Capture complete? */ - if ((status & I2C_INTSTAT_MONIDLE) != 0) - { - pDrv->base->INTENCLR = (I2C_INTENCLR_MONRDY | I2C_INTENCLR_MONOV | - I2C_INTENCLR_MONIDLE); - pCap->status = pDrv->pendingStatus; - if (pDrv->pCapCompCB) - { - pDrv->pCapCompCB(pHandle, pCap); - } - } -} - -uint32_t i2cmon_get_driver_version(void) -{ - return DRVVERSION; -} - -/* ********************************************************** */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmond.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmond.h deleted file mode 100644 index d68e416b510..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmond.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * @brief I2C monitor ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __HW_I2CMOND_H -#define __HW_I2CMOND_H - -#include "error.h" -#include "hw_i2cmond_rom_api.h" - -// *** I2C functions called by Application Program *** -uint32_t i2cmon_get_mem_size(void); - -ROM_I2CMON_HANDLE_T i2cmon_init(void *mem, const ROM_I2CMON_INIT_T *pInit); - -void i2cmom_register_callback(ROM_I2CMON_HANDLE_T pHandle, uint32_t cbIndex, void *pCB); - -ErrorCode_t i2cmom_start_log(ROM_I2CMON_HANDLE_T pHandle, ROM_I2CMON_CAP_T *pCap); - -void i2cmon_transfer_handler(ROM_I2CMON_HANDLE_T pHandle); - -uint32_t i2cmon_get_driver_version(void); - -// *** - -#endif /* __HW_I2CMOND_H */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmond_rom_api.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmond_rom_api.c deleted file mode 100644 index 2b43e93d877..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmond_rom_api.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * @brief I2C monitor ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "hw_i2cmond.h" - -// This creates a table with the addresses of all the I2C functions -// This table of function pointers is the API interface. -const ROM_I2CMOND_API_T i2cmon_api = { - &i2cmon_get_mem_size, - &i2cmon_init, - &i2cmom_register_callback, - &i2cmom_start_log, - &i2cmon_transfer_handler, - &i2cmon_get_driver_version, -}; // end of table ************************************ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmond_rom_api.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmond_rom_api.h deleted file mode 100644 index a4e126a679a..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmond_rom_api.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * @brief I2C monitor ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __HW_I2CMOND_ROM_API_H -#define __HW_I2CMOND_ROM_API_H - -#include "stdint.h" // added to define uint32_t, etc. -#include "error.h" -#include "packing.h" -#include "hw_i2c_common.h" - -/** @defgroup ROMAPI_I2CMON I2C monitor ROM driver functions and definitions - * @ingroup ROMAPI_I2CMON_WRAPPER - * @{ - */ - -/** @brief I2C monitor handle type */ -typedef void *ROM_I2CMON_HANDLE_T; - -/** @brief User context conversion macro - * Macro used to extract the user defined data pointer from a I2C monitor - * handle context.
- * To get a user context, simple use the macro on the drivers handle: - * void *pUserData = (void *) ROM_I2CMON_HANDLE_TOUDATA(driverHandle); - */ -#define ROM_I2CMON_HANDLE_TOUDATA(p) (void *) (*(uint32_t *) p) - -/** @brief I2C monitor optional transfer flags */ -#define ROM_I2CMON_FLAG_BLOCKING (1UL << 31) /*!< Capture function will block until complete */ -#define ROM_I2CMON_FLAG_DMARX (1UL << 29) /*!< DMA will be used for RX, requires DMA setup outside of the driver */ -#define ROM_I2CMON_FLAG_FLUSH (1UL << 25) /*!< Force monitor FIFO flush */ -#define ROM_I2CMON_FLAG_USERBITS (0xFFFF) /*!< Application can safely use the flag bits designated by this mask */ - -/** @brief Monitor transfer descriptor */ -typedef PRE_PACK struct POST_PACK { - const void *startBuff; /*!< Pointer to a buffer for capturing data after start, msy be 16-bit aligned */ - uint16_t startBuffSz; /*!< Number of bytes in startBuff buffer, data will be tossed if not big enough */ - uint16_t capStartBuffSz; /*!< Number of bytes captured in startBuff buffer */ - uint32_t flags; /*!< Optional transfer flags of type ROM_I2CMON_FLAG_* */ - volatile ErrorCode_t status; /*!< LPC_OK, busy status, or error code */ -} ROM_I2CMON_CAP_T; - -/** I2C monitor callback IDs */ -typedef enum { - ROM_I2CMON_CAPTUREREADY_CB = 0, /*!< Callback ID for I2C monitor capture ready */ - ROM_I2CMON_DMASETUP_CB /*!< Callback for DMA setup */ -} ROM_I2CMON_CALLBACK_T; - -/** @brief I2C monitor capture complete callback prototype - * The I2C monitor state machine will call this function when it captures an I2C transfer. - */ -typedef void (*i2cMonCapReadyCB)(ROM_I2CMON_HANDLE_T i2cmonHandle, ROM_I2CMON_CAP_T *pCap); - -/** @brief I2C monitor capture DMA setup callback prototype - * The I2C monitor state machine will call this function when DMA needs to be setup for - * the capture oeprations. - */ -typedef void (*i2cMonSetupDMACB)(ROM_I2CMON_HANDLE_T i2cmonHandle, ROM_I2CMON_CAP_T *pCap); - -/** @brief I2C monitor initialization structure */ -typedef PRE_PACK struct POST_PACK { - void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */ - uint32_t base; /*!< Base address of I2C peripheral to use */ - uint8_t stretch; /*!< 0 = disable monitor clock stretching, !0 = enable */ -} ROM_I2CMON_INIT_T; - -/** @brief I2C monitor ROM indirect function structure */ -typedef PRE_PACK struct POST_PACK { - uint32_t (*GetMemSize)(void); /*!< Returns needed memory size required for run-time context of I2C monitor driver */ - ROM_I2CMON_HANDLE_T (*Init)(void *mem, const ROM_I2CMON_INIT_T *pInit); /*!< Initializes the I2C monitor driver and peripheral */ - void (*RegisterCallback)(ROM_I2CMON_HANDLE_T pHandle, uint32_t cbIndex, void *pCB); /*!< Registers an I2C monitor callback */ - ErrorCode_t (*StartLog)(ROM_I2CMON_HANDLE_T pHandle, ROM_I2CMON_CAP_T *pCap); /*!< Start/queue a log descriptor */ - void (*TransferHandler)(ROM_I2CMON_HANDLE_T pHandle); /*!< I2C monitor transfer (interrupt) handler */ - uint32_t (*GetDriverVersion)(void); -} ROM_I2CMOND_API_T; - -/** - * @} - */ - -extern const ROM_I2CMOND_API_T i2cmon_api; // so application program can access pointer to -// function table - -#endif /* __HW_I2CMOND_ROM_API_H */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2csd.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2csd.c deleted file mode 100644 index edab3a9cdfc..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2csd.c +++ /dev/null @@ -1,301 +0,0 @@ -/* - * @brief I2C slave ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include -#include -#include "hw_i2csd.h" - -#define DRVVERSION 0x0100 - -/* Private data structure used for the I2C slave driver, holds the driver and - peripheral context */ -typedef struct { - void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */ - LPC_I2C_T *base; /*!< Base address of I2C peripheral to use */ - i2cSlaveStartCB pXferStartCB; /*!< Transfer start callback */ - i2cSlaveTransmitCB pTranTranCb; /*!< Data transmit callback */ - i2cSlaveReceiveCB pTranRecvCb; /*!< Data Receive callback */ - i2cSlaveCompleteCB pXferCompCB; /*!< Transfer complete callback */ - ROM_I2CS_XFER_T *pXfer; /*!< Pointer to current transfer */ - ErrorCode_t pendingStatus; /*!< Pending transfer status */ -} I2CS_DATACONTEXT_T; - -#define _rom_i2csEnable(pI2C) (pI2C->CFG |= I2C_CFG_SLVEN); -#define _rom_i2csGetSlaveAddr(pI2C, slvNum) ((pI2C->SLVADR[slvNum] >> 1) & 0x7F) -#define _rom_i2csGetSlaveMatchIndex(pI2C) ((pI2C->STAT & I2C_STAT_SLVIDX) >> 12) -#define _rom_i2csGetSlaveState(pI2C) (((pI2C->STAT & I2C_STAT_SLVSTATE) >> 9) & 0x3) - -// ********************************************************** -uint32_t i2cs_get_mem_size(void) -{ - return sizeof(I2CS_DATACONTEXT_T); -} - -ROM_I2CS_HANDLE_T i2cs_init(void *mem, const ROM_I2CS_INIT_T *pInit) -{ - I2CS_DATACONTEXT_T *pDrv; - - /* Verify alignment is at least 4 bytes */ - if (((uint32_t) mem & 0x3) != 0) { - return NULL; - } - - pDrv = (I2CS_DATACONTEXT_T *) mem; - memset(pDrv, 0, sizeof(I2CS_DATACONTEXT_T)); - - /* Save base of peripheral and pointer to user data */ - pDrv->pUserData = pInit->pUserData; - pDrv->base = (LPC_I2C_T *) pInit->base; - - /* If this needs to be changed, it should be done in the app after - this call. */ - pDrv->base->CLKDIV = 2; - - /* Clear controller state */ - pDrv->base->STAT = (I2C_STAT_SLVSEL | I2C_STAT_SLVDESEL); - - /* Enable I2C slave interface */ - _rom_i2csEnable(pDrv->base); - - return pDrv; -} - -void i2cs_setup_slave(ROM_I2CS_HANDLE_T pHandle, ROM_I2CS_SLAVE_T *pSlaveSetup) -{ - uint32_t sa, idx; - I2CS_DATACONTEXT_T *pDrv = (I2CS_DATACONTEXT_T *) pHandle; - - /* Limit usable slave address indexes to the maximum the controller can support */ - if (pSlaveSetup->SlaveIndex <= 3) { - sa = (uint32_t) (pSlaveSetup->slaveAddr & 0x7F) << 1; - if (pSlaveSetup->EnableSlave == 0) { - sa |= I2C_SLVADR_SADISABLE; /* Disable slave address */ - } - - /* Setup slave address at index */ - pDrv->base->SLVADR[pSlaveSetup->SlaveIndex] = sa; - } - - /* Check all slave indexes. If any are enabled, then enable the slave interrupts, - else disable the slave interrupts. */ - sa = 0; - for (idx = 0; ((idx <= 3) && (sa == 0)); idx++) { - if ((pDrv->base->SLVADR[idx] & I2C_SLVADR_SADISABLE) == 0) { - /* Slave is enabled */ - sa = 1; - } - } - if (sa) { - pDrv->base->INTENSET = I2C_INTENSET_SLVPENDING; - - } - else { - pDrv->base->INTENCLR = (I2C_INTENSET_SLVPENDING | I2C_INTENSET_SLVDESEL); - } -} - -void i2cs_register_callback(ROM_I2CS_HANDLE_T pHandle, uint32_t cbIndex, void *pCB) -{ - I2CS_DATACONTEXT_T *pDrv = (I2CS_DATACONTEXT_T *) pHandle; - - if (cbIndex == ROM_I2CS_START_CB) { - pDrv->pXferStartCB = (i2cSlaveStartCB) pCB; - } - else if (cbIndex == ROM_I2CS_XFERSEND_CB) { - pDrv->pTranTranCb = (i2cSlaveTransmitCB) pCB; - } - else if (cbIndex == ROM_I2CS_XFERRECV_CB) { - pDrv->pTranRecvCb = (i2cSlaveReceiveCB) pCB; - } - else if (cbIndex == ROM_I2CS_DONE_CB) { - pDrv->pXferCompCB = (i2cSlaveCompleteCB) pCB; - } -} - -ErrorCode_t i2cs_transfer(ROM_I2CS_HANDLE_T pHandle, ROM_I2CS_XFER_T *pXfer) -{ - I2CS_DATACONTEXT_T *pDrv = (I2CS_DATACONTEXT_T *) pHandle; - - /* Is transfer NULL? */ - if (pXfer == NULL) { - return ERR_I2C_PARAM; - } - - /* Save transfer descriptor */ - pDrv->pXfer = pXfer; - pXfer->status = ERR_I2C_BUSY; - pDrv->pendingStatus = LPC_OK; - pXfer->bytesSent = 0; - pXfer->bytesRecv = 0; - - return pXfer->status; -} - -// Otime = "optimize for speed of code execution" -// ...add this pragma 1 line above the interrupt service routine function. -void i2cs_transfer_handler(ROM_I2CS_HANDLE_T pHandle) -{ - I2CS_DATACONTEXT_T *pDrv = (I2CS_DATACONTEXT_T *) pHandle; - ROM_I2CS_XFER_T *pXfer = pDrv->pXfer; - - uint32_t done = 0; - uint16_t data = 0; - - uint32_t status = pDrv->base->INTSTAT; - - /* Transfer complete? */ - if ((status & I2C_INTENSET_SLVDESEL) != 0) { - pDrv->base->INTENCLR = I2C_INTENSET_SLVDESEL; - pDrv->base->STAT = I2C_STAT_SLVDESEL; - if (pXfer) { - pXfer->status = pDrv->pendingStatus; - pDrv->pXfer = NULL; - } - if (pDrv->pXferCompCB) { - pDrv->pXferCompCB(pHandle, pXfer); - } - return; - } - else if ((status & I2C_INTENSET_SLVPENDING) != 0) { - /* Determine the current I2C slave state */ - switch (_rom_i2csGetSlaveState(pDrv->base)) { - case I2C_STAT_SLVCODE_ADDR: - /* Get slave address that needs servicing */ - data = _rom_i2csGetSlaveAddr(pDrv->base, _rom_i2csGetSlaveMatchIndex(pDrv->base)); - - /* Call address callback */ - if (pDrv->pXferStartCB) { - pDrv->pXferStartCB(pHandle, data); - - /* Update transfer descriptor */ - pXfer = pDrv->pXfer; - } - pDrv->base->INTENSET = I2C_INTENSET_SLVDESEL; - break; - - case I2C_STAT_SLVCODE_RX: - /* Receive from master */ - /* A byte has been received in thee receive FIFO */ - if ((pXfer == NULL) || (pXfer->bytesRecv >= pXfer->rxSz)) { - /* No more data, call receive data callback */ - if (pDrv->pTranRecvCb) { - done = pDrv->pTranRecvCb(pHandle, pXfer); - if (pDrv->pXfer) { - pXfer = pDrv->pXfer; - pXfer->bytesRecv = 0; - } - } - } - - /* Not using DMA */ - if (!(done == ROM_I2CS_DMA)) { - data = (uint8_t) pDrv->base->SLVDAT; - if (pXfer == NULL) { - /* Toss data and NAK, no buffer space */ - done = ROM_I2CS_NAK; - pDrv->pendingStatus = ERR_I2C_BUFFER_OVERFLOW; - } - else { - uint8_t *p8 = pXfer->rxBuff; - if ((p8 == NULL) || (pXfer->bytesRecv >= pXfer->rxSz)) { - /* Toss data and NAK, no buffer space */ - done = ROM_I2CS_NAK; - pDrv->pendingStatus = ERR_I2C_BUFFER_OVERFLOW; - } - else { - p8[pXfer->bytesRecv] = (uint8_t) data; - pDrv->pXfer->bytesRecv++; - } - } - } - break; - - case I2C_STAT_SLVCODE_TX: - /* Send to master */ - /* A byte needs to be placed into the transmit FIFO */ - if ((pXfer == NULL) || (pXfer->bytesSent >= pXfer->txSz)) { - /* Does callback exist? */ - if (pDrv->pTranTranCb) { - done = pDrv->pTranTranCb(pHandle, pXfer); - /* Can't really NAK on read, so switch to continue */ - if (pDrv->pXfer) { - pXfer = pDrv->pXfer; - pXfer->bytesSent = 0; - } - if (done == ROM_I2CS_NAK) { - pDrv->base->SLVDAT = 0; - } - } - } - - /* Continue if not DMA or NAK */ - if (!((done == ROM_I2CS_NAK) || (done == ROM_I2CS_DMA))) { - if (pXfer == NULL) { - pDrv->base->SLVDAT = 0; - pDrv->pendingStatus = ERR_I2C_BUFFER_UNDERFLOW; - done = 0; - } - else { - uint8_t *p8 = (uint8_t *) pXfer->txBuff; - /* Not using DMA, so this is a normal transfer */ - if ((p8 == NULL) || (pXfer->bytesSent >= pXfer->txSz)) { - /* Have to send something, so NAK with 0 */ - pDrv->base->SLVDAT = 0; - pDrv->pendingStatus = ERR_I2C_BUFFER_UNDERFLOW; - done = 0; - } - else { - pDrv->base->SLVDAT = (uint32_t) p8[pXfer->bytesSent]; - pDrv->pXfer->bytesSent++; - } - } - } - break; - } - - if (done == ROM_I2CS_NAK) { - pDrv->base->SLVCTL = I2C_SLVCTL_SLVNACK; - } - else if (done == ROM_I2CS_DMA) { - pDrv->base->SLVCTL = I2C_SLVCTL_SLVDMA; - } - else { - pDrv->base->SLVCTL = I2C_SLVCTL_SLVCONTINUE; - } - } -} - -uint32_t i2cs_get_driver_version(void) -{ - return DRVVERSION; -} - -// ********************************************************* diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2csd.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2csd.h deleted file mode 100644 index d599b8b06d7..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2csd.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * @brief I2C slave ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __HW_I2CSD_H -#define __HW_I2CSD_H - -#include "error.h" -#include "hw_i2csd_rom_api.h" - -// *** I2C functions called by Application Program *** -uint32_t i2cs_get_mem_size(void); - -ROM_I2CS_HANDLE_T i2cs_init(void *mem, const ROM_I2CS_INIT_T *pInit); - -void i2cs_setup_slave(ROM_I2CS_HANDLE_T pHandle, ROM_I2CS_SLAVE_T *pSlaveSetup); - -void i2cs_register_callback(ROM_I2CS_HANDLE_T pHandle, uint32_t cbIndex, void *pCB); - -ErrorCode_t i2cs_transfer(ROM_I2CS_HANDLE_T pHandle, ROM_I2CS_XFER_T *pXfer); - -void i2cs_transfer_handler(ROM_I2CS_HANDLE_T pHandle); - -uint32_t i2cs_get_driver_version(void); - -// *** - -#endif /* __HW_I2CSD_H */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2csd_rom_api.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2csd_rom_api.c deleted file mode 100644 index b2c9dbd0494..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2csd_rom_api.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * @brief I2C slave ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "hw_i2csd.h" - -// This creates a table with the addresses of all the I2C functions -// This table of function pointers is the API interface. -const ROM_I2CSD_API_T i2cs_api = { - &i2cs_get_mem_size, - &i2cs_init, - &i2cs_setup_slave, - &i2cs_register_callback, - &i2cs_transfer, - &i2cs_transfer_handler, - &i2cs_get_driver_version, -}; // end of table ************************************ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2csd_rom_api.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2csd_rom_api.h deleted file mode 100644 index e5eba2c9fd0..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2csd_rom_api.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * @brief I2C slave ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __HW_I2CSD_ROM_API_H -#define __HW_I2CSD_ROM_API_H - -#include "stdint.h" // added to define uint32_t, etc. -#include "error.h" -#include "packing.h" -#include "hw_i2c_common.h" - -/** @defgroup ROMAPI_I2CS I2C slave ROM driver functions and definitions - * @ingroup ROMAPI_I2CS_WRAPPER - * @{ - */ - -/** @brief I2C slave handle type */ -typedef void *ROM_I2CS_HANDLE_T; - -/** @brief Maximum number of slave addresses supported by this driver */ -#define ROM_I2CS_MAX_SLAVES 4 - -/** @brief User context conversion macro - * Macro used to extract the user defined data pointer from a I2C master - * handle context.
- * To get a user context, simple use the macro on the drivers handle: - * void *pUserData = (void *) ROM_I2CS_HANDLE_TOUDATA(driverHandle); - */ -#define ROM_I2CS_HANDLE_TOUDATA(p) (void *) (*(uint32_t *) p) - -/** @brief I2C master optional transfer flags */ -#define ROM_I2CS_FLAG_USERBITS (0xFFFF) /*!< Application can safely use the flag bits designated by this mask */ - -/** @brief slave transfer descriptor */ -typedef PRE_PACK struct POST_PACK { - const void *txBuff; /*!< Pointer to array of bytes to be transmitted */ - void *rxBuff; /*!< Pointer memory where bytes received from I2C be stored */ - volatile ErrorCode_t status; /*!< Packed status of the current I2C transfer (ErrorCode_t), must be 32-bits */ - uint32_t flags; /*!< Reserved, set to 0 */ - uint16_t txSz; /*!< Number of bytes in transmit array, if 0 only receive transfer will be performed */ - uint16_t rxSz; /*!< Number of bytes to receive, if 0 only transmission will be performed */ - uint16_t bytesSent; /*!< Number of bytes sent */ - uint16_t bytesRecv; /*!< Number of bytes recevied */ -} ROM_I2CS_XFER_T; - -/** I2C slave callback IDs */ -typedef enum { - ROM_I2CS_START_CB = 0, /*!< Callback ID for I2C slave service start callback */ - ROM_I2CS_XFERSEND_CB, /*!< Callback ID for I2C slave send data callback */ - ROM_I2CS_XFERRECV_CB, /*!< Callback ID for I2C slave receive data callback */ - ROM_I2CS_DONE_CB, /*!< Callback ID for I2C slave service done callback */ -} ROM_I2CS_CALLBACK_T; - -/** @brief I2C slave state machine transfer control */ -typedef enum { - ROM_I2CS_CONTINUE = 0, /*!< Continue transfer */ - ROM_I2CS_NAK, /*!< Will NAK master at next opportunity */ - ROM_I2CS_DMA /*!< Tell I2C handler DMA is handling the data */ -} ROM_I2CS_TRANCTRL_T; - -/** @brief I2C slave transfer start callback - * This callback is called from the I2C slave handler when an I2C slave address supported - * by the controller is addressed. - */ -typedef void (*i2cSlaveStartCB)(ROM_I2CS_HANDLE_T i2csHandle, uint16_t addr); - -/** @brief I2C slave send data callback - * This callback is called from the I2C slave handler when an I2C slave address needs - * data to send in the transfer descriptor. It is called on demand only when transmit - * data is needed for the transmit FIFO and the descriptor buffer is empty.
- * If you want to NAK the master, return ROM_I2CS_NAK to the caller. - * Return ROM_I2CS_CONTINUE or 0 to the caller for normal non-DMA data transfer. - * If you've setup a DMA descriptor for the transfer, return ROM_I2CS_DMA to the caller.
- */ -typedef ROM_I2CS_TRANCTRL_T (*i2cSlaveTransmitCB)(ROM_I2CS_HANDLE_T i2csHandle, ROM_I2CS_XFER_T *pXfer); - -/** @brief I2C slave receive data callback - * This callback is called from the I2C slave handler when an I2C slave address has - * receive data and the receive buffer is full.
- * If you want to NAK the master, return ROM_I2CS_NAK to the caller. - * Return ROM_I2CS_CONTINUE or 0 to the caller for normal non-DMA data transfer. - * If you've setup a DMA descriptor for the transfer, return ROM_I2CS_DMA to the caller.
- */ -typedef ROM_I2CS_TRANCTRL_T (*i2cSlaveReceiveCB)(ROM_I2CS_HANDLE_T i2csHandle, ROM_I2CS_XFER_T *pXfer); - -/** @brief I2C slave service done callback - * This callback is called from the I2C slave handler when an I2C slave transfer is - * completed. It's used to indicate the end of a slave transfer. - */ -typedef void (*i2cSlaveCompleteCB)(ROM_I2CS_HANDLE_T i2csHandle, ROM_I2CS_XFER_T *pXfer); - -/** @brief I2C slave initialization structure */ -typedef PRE_PACK struct POST_PACK { - void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */ - uint32_t base; /*!< Base address of I2C peripheral to use */ -} ROM_I2CS_INIT_T; - -/** @brief I2C slave address setup structure */ -typedef PRE_PACK struct POST_PACK { - uint16_t slaveAddr; /*!< Slave address used for this index in the controller */ - uint8_t SlaveIndex; /*!< Slave index to use, 0 is first index */ - uint8_t EnableSlave; /*!< Set to 0 to disable this slave index, or non-0 to enable */ -} ROM_I2CS_SLAVE_T; - -/** @brief I2C slave ROM indirect function structure */ -typedef PRE_PACK struct POST_PACK { - uint32_t (*GetMemSize)(void); /*!< Returns needed memory size required for run-time context of I2C slave driver */ - ROM_I2CS_HANDLE_T (*Init)(void *mem, const ROM_I2CS_INIT_T *pInit); /*!< Initializes the I2C slave driver and peripheral */ - void (*SetupSlave)(ROM_I2CS_HANDLE_T pHandle, ROM_I2CS_SLAVE_T *pSlaveSetup); /*!< Sets up a slave address to use with the I2C controller */ - void (*RegisterCallback)(ROM_I2CS_HANDLE_T pHandle, uint32_t cbIndex, void *pCB); /*!< Registers an I2C slave callback */ - ErrorCode_t (*Transfer)(ROM_I2CS_HANDLE_T pHandle, ROM_I2CS_XFER_T *pXfer); /*!< Queues an I2C slave transfer */ - void (*TransferHandler)(ROM_I2CS_HANDLE_T pHandle); /*!< I2C slave transfer (interrupt) handler */ - uint32_t (*GetDriverVersion)(void); -} ROM_I2CSD_API_T; - -/** - * @} - */ - -extern const ROM_I2CSD_API_T i2cs_api; // so application program can access pointer to -// function table - -#endif /* __HW_I2CSD_ROM_API_H */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spi_common.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spi_common.h deleted file mode 100644 index 6c0088786cd..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spi_common.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * @brief SPI ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __HW_SPI_COMMON_H_ -#define __HW_SPI_COMMON_H_ - -/** - * @brief SPI register block structure - */ -typedef struct { /*!< SPI Structure */ - volatile uint32_t CFG; /*!< SPI Configuration register */ - volatile uint32_t DLY; /*!< SPI Delay register */ - volatile uint32_t STAT; /*!< SPI Status register */ - volatile uint32_t INTENSET; /*!< SPI Interrupt Enable Set register */ - volatile uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear register */ - volatile uint32_t RXDAT; /*!< SPI Receive Data register */ - volatile uint32_t TXDATCTL; /*!< SPI Transmit Data with Control register */ - volatile uint32_t TXDAT; /*!< SPI Transmit Data register */ - volatile uint32_t TXCTRL; /*!< SPI Transmit Control register */ - volatile uint32_t DIV; /*!< SPI clock Divider register */ - volatile uint32_t INTSTAT; /*!< SPI Interrupt Status register */ -} LPC_SPI_T; - -/** - * Macro defines for SPI Configuration register - */ -#define SPI_CFG_BITMASK (0xFBD) /** SPI register bit mask */ -#define SPI_CFG_SPI_EN (1 << 0) /** SPI Slave Mode Select */ -#define SPI_CFG_SLAVE_EN (0 << 0) /** SPI Master Mode Select */ -#define SPI_CFG_MASTER_EN (1 << 2) /** SPI MSB First mode enable */ -#define SPI_CFG_MSB_FIRST_EN (0 << 3) /** SPI LSB First mode enable */ -#define SPI_CFG_LSB_FIRST_EN (1 << 3) /** SPI Clock Phase Select */ -#define SPI_CFG_CPHA_FIRST (0 << 4) /** Capture data on the first edge, Change data on the following edge */ -#define SPI_CFG_CPHA_SECOND (1 << 4) /** SPI Clock Polarity Select */ -#define SPI_CFG_CPOL_LO (0 << 5) /** The rest state of the clock (between frames) is low. */ -#define SPI_CFG_CPOL_HI (1 << 5) /** The rest state of the clock (between frames) is high. */ -#define SPI_CFG_LBM_EN (1 << 7) /** SPI control 1 loopback mode enable */ -#define SPI_CFG_SPOL_LO (0 << 8) /** SPI SSEL0 Polarity Select */ -#define SPI_CFG_SPOL_HI (1 << 8) /** SSEL0 is active High */ -#define SPI_CFG_SPOLNUM_HI(n) (1 << ((n) + 8)) /** SSELN is active High, selects 0 - 3 */ - -/** - * Macro defines for SPI Delay register - */ -#define SPI_DLY_BITMASK (0xFFFF) /** SPI DLY Register Mask */ -#define SPI_DLY_PRE_DELAY(n) (((n) & 0x0F) << 0) /** Time in SPI clocks between SSEL assertion and the beginning of a data frame */ -#define SPI_DLY_POST_DELAY(n) (((n) & 0x0F) << 4) /** Time in SPI clocks between the end of a data frame and SSEL deassertion. */ -#define SPI_DLY_FRAME_DELAY(n) (((n) & 0x0F) << 8) /** Minimum time in SPI clocks between adjacent data frames. */ -#define SPI_DLY_TRANSFER_DELAY(n) (((n) & 0x0F) << 12) /** Minimum time in SPI clocks that the SSEL is deasserted between transfers. */ - -/** - * Macro defines for SPI Status register - */ -#define SPI_STAT_BITMASK (0x1FF) /** SPI STAT Register BitMask */ -#define SPI_STAT_RXRDY (1 << 0) /** Receiver Ready Flag */ -#define SPI_STAT_TXRDY (1 << 1) /** Transmitter Ready Flag */ -#define SPI_STAT_RXOV (1 << 2) /** Receiver Overrun interrupt flag */ -#define SPI_STAT_TXUR (1 << 3) /** Transmitter Underrun interrupt flag (In Slave Mode only) */ -#define SPI_STAT_SSA (1 << 4) /** Slave Select Assert */ -#define SPI_STAT_SSD (1 << 5) /** Slave Select Deassert */ -#define SPI_STAT_STALLED (1 << 6) /** Stalled status flag */ -#define SPI_STAT_EOT (1 << 7) /** End Transfer flag */ -#define SPI_STAT_MSTIDLE (1 << 8) /** Idle status flag */ - -/** - * Macro defines for SPI Interrupt Enable read and Set register - */ -#define SPI_INTENSET_BITMASK (0x3F) /** SPI INTENSET Register BitMask */ -#define SPI_INTENSET_RXDYEN (1 << 0) /** Enable Interrupt when receiver data is available */ -#define SPI_INTENSET_TXDYEN (1 << 1) /** Enable Interrupt when the transmitter holding register is available. */ -#define SPI_INTENSET_RXOVEN (1 << 2) /** Enable Interrupt when a receiver overrun occurs */ -#define SPI_INTENSET_TXUREN (1 << 3) /** Enable Interrupt when a transmitter underrun occurs (In Slave Mode Only)*/ -#define SPI_INTENSET_SSAEN (1 << 4) /** Enable Interrupt when the Slave Select is asserted.*/ -#define SPI_INTENSET_SSDEN (1 << 5) /** Enable Interrupt when the Slave Select is deasserted..*/ - -/** - * Macro defines for SPI Interrupt Enable Clear register - */ -#define SPI_INTENCLR_BITMASK (0x3F) /** SPI INTENCLR Register BitMask */ -#define SPI_INTENCLR_RXDYEN (1 << 0) /** Disable Interrupt when receiver data is available */ -#define SPI_INTENCLR_TXDYEN (1 << 1) /** Disable Interrupt when the transmitter holding register is available. */ -#define SPI_INTENCLR_RXOVEN (1 << 2) /** Disable Interrupt when a receiver overrun occurs */ -#define SPI_INTENCLR_TXUREN (1 << 3) /** Disable Interrupt when a transmitter underrun occurs (In Slave Mode Only) */ -#define SPI_INTENCLR_SSAEN (1 << 4) /** Disable Interrupt when the Slave Select is asserted. */ -#define SPI_INTENCLR_SSDEN (1 << 5) /** Disable Interrupt when the Slave Select is deasserted.. */ - -/** - * Macro defines for SPI Receiver Data register - */ -#define SPI_RXDAT_BITMASK (0x1FFFFF) /** SPI RXDAT Register BitMask */ -#define SPI_RXDAT_DATA(n) ((n) & 0xFFFF) /** Receiver Data */ -#define SPI_RXDAT_RXSSELN_ACTIVE (0 << 16) /** The state of SSEL pin is active */ -#define SPI_RXDAT_RXSSELN_INACTIVE ((1 << 16) /** The state of SSEL pin is inactive */ -#define SPI_RXDAT_RXSSELNUM_INACTIVE(n) (1 << ((n) + 16)) /** The state of SSELN pin is inactive */ -#define SPI_RXDAT_SOT (1 << 20) /** Start of Transfer flag */ - -/** - * Macro defines for SPI Transmitter Data and Control register - */ -#define SPI_TXDATCTL_BITMASK (0xF7FFFFF) /** SPI TXDATCTL Register BitMask */ -#define SPI_TXDATCTL_DATA(n) ((n) & 0xFFFF) /** SPI Transmit Data */ -#define SPI_TXDATCTL_CTRLMASK (0xF7F0000) /** SPI TXDATCTL Register BitMask for control bits only */ -#define SPI_TXDATCTL_ASSERT_SSEL (0 << 16) /** Assert SSEL0 pin */ -#define SPI_TXDATCTL_DEASSERT_SSEL (1 << 16) /** Deassert SSEL0 pin */ -#define SPI_TXDATCTL_DEASSERTNUM_SSEL(n) (1 << ((n) + 16)) /** Deassert SSELN pin */ -#define SPI_TXDATCTL_DEASSERT_ALL (0xF << 16) /** Deassert all SSEL pins */ -#define SPI_TXDATCTL_EOT (1 << 20) /** End of Transfer flag (TRANSFER_DELAY is applied after sending the current frame) */ -#define SPI_TXDATCTL_EOF (1 << 21) /** End of Frame flag (FRAME_DELAY is applied after sending the current part) */ -#define SPI_TXDATCTL_RXIGNORE (1 << 22) /** Receive Ignore Flag */ -#define SPI_TXDATCTL_FLEN(n) (((n) & 0x0F) << 24) /** Frame length - 1 */ - -/** - * Macro defines for SPI Transmitter Data Register - */ -#define SPI_TXDAT_DATA(n) ((n) & 0xFFFF) /** SPI Transmit Data */ - -/** - * Macro defines for SPI Transmitter Control register - */ -#define SPI_TXCTL_BITMASK (0xF7F0000) /** SPI TXDATCTL Register BitMask */ -#define SPI_TXCTL_ASSERT_SSEL (0 << 16) /** Assert SSEL0 pin */ -#define SPI_TXCTL_DEASSERT_SSEL (1 << 16) /** Deassert SSEL0 pin */ -#define SPI_TXCTL_DEASSERTNUM_SSEL(n) (1 << ((n) + 16)) /** Deassert SSELN pin */ -#define SPI_TXDATCTL_DEASSERT_ALL (0xF << 16) /** Deassert all SSEL pins */ -#define SPI_TXCTL_EOT (1 << 20) /** End of Transfer flag (TRANSFER_DELAY is applied after sending the current frame) */ -#define SPI_TXCTL_EOF (1 << 21) /** End of Frame flag (FRAME_DELAY is applied after sending the current part) */ -#define SPI_TXCTL_RXIGNORE (1 << 22) /** Receive Ignore Flag */ -#define SPI_TXCTL_FLEN(n) ((((n) - 1) & 0x0F) << 24) /** Frame length, 0 - 16 */ -#define SPI_TXCTL_FLENMASK (0xF << 24) /** Frame length mask */ - -/** - * Macro defines for SPI Divider register - */ -#define SPI_DIV_VAL(n) ((n) & 0xFFFF) /** Rate divider value mask (In Master Mode only)*/ - -/** - * Macro defines for SPI Interrupt Status register - */ -#define SPI_INTSTAT_BITMASK (0x3F) /** SPI INTSTAT Register Bitmask */ -#define SPI_INTSTAT_RXRDY (1 << 0) /** Receiver Ready Flag */ -#define SPI_INTSTAT_TXRDY (1 << 1) /** Transmitter Ready Flag */ -#define SPI_INTSTAT_RXOV (1 << 2) /** Receiver Overrun interrupt flag */ -#define SPI_INTSTAT_TXUR (1 << 3) /** Transmitter Underrun interrupt flag (In Slave Mode only) */ -#define SPI_INTSTAT_SSA (1 << 4) /** Slave Select Assert */ -#define SPI_INTSTAT_SSD (1 << 5) /** Slave Select Deassert */ - -/** @brief SPI Clock Mode*/ -typedef enum { - ROM_SPI_CLOCK_CPHA0_CPOL0 = 0, /**< CPHA = 0, CPOL = 0 */ - ROM_SPI_CLOCK_MODE0 = ROM_SPI_CLOCK_CPHA0_CPOL0, /**< Alias for CPHA = 0, CPOL = 0 */ - ROM_SPI_CLOCK_CPHA1_CPOL0 = 1, /**< CPHA = 0, CPOL = 1 */ - ROM_SPI_CLOCK_MODE1 = ROM_SPI_CLOCK_CPHA1_CPOL0, /**< Alias for CPHA = 0, CPOL = 1 */ - ROM_SPI_CLOCK_CPHA0_CPOL1 = 2, /**< CPHA = 1, CPOL = 0 */ - ROM_SPI_CLOCK_MODE2 = ROM_SPI_CLOCK_CPHA0_CPOL1, /**< Alias for CPHA = 1, CPOL = 0 */ - ROM_SPI_CLOCK_CPHA1_CPOL1 = 3, /**< CPHA = 1, CPOL = 1 */ - ROM_SPI_CLOCK_MODE3 = ROM_SPI_CLOCK_CPHA1_CPOL1, /**< Alias for CPHA = 1, CPOL = 1 */ -} ROM_SPI_CLOCK_MODE_T; - -#endif /* __HW_SPI_COMMON_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spimd.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spimd.c deleted file mode 100644 index bd6ae6fd762..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spimd.c +++ /dev/null @@ -1,581 +0,0 @@ -/* - * @brief SPI master ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include -#include -#include "hw_spimd.h" - -#define DRVVERSION 0x0100 - -/* Private callback for FIFO push and pop functions. This privately maps - to the VFIFO for the SPI master, but can be overriden if needed. The driver will - automatically pick the right implementation at run-time based on the transfer - size in the transfer descriptor. */ -typedef uint16_t (*spiMasterFifoPushFN)(LPC_SPI_T *pSPI, void *data, uint32_t sendBytes, uint32_t curIndex); -typedef uint16_t (*spiMasterFifoPopFN)(LPC_SPI_T *pSPI, void *data, uint32_t bytes, uint32_t curIndex); - -/* Private data structure used for the SPI master driver, holds the driver and - peripheral context */ -typedef struct { - void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */ - LPC_SPI_T *base; /*!< Base address of SPI peripheral to use */ - uint32_t baseClockRate; /*!< SPI base clock rate in Hz, call Init() again if this rate changes */ - spiMasterXferCSAssertCB pAssertCb; /*!< SSEL assertion callback */ - spiMasterTransmitCB pTranCb; /*!< Transmit data start callback */ - spiMasterReceiveCB pRecvCb; /*!< Receive data start callback */ - spiMMasterXferCSDeAssertCB pDeassertCb; /*!< SSEL deassertion callback */ - spiMasterFifoPushFN pPushFN; /*!< Pointer to current FIFO push function */ - spiMasterFifoPopFN pPopFN; /*!< Pointer to current FIFO pop function */ - ROM_SPIM_XFER_T *pXfer; /*!< Pointer to current transfer descriptor */ - uint32_t sendIdx; /*!< Current transmit buffer index */ - uint32_t recvIdx; /*!< Current receive buffer index */ - ErrorCode_t pendingStatus; /*!< Pending transfer status */ - uint8_t xmitOn; /*!< Transfer in progress flag */ - uint8_t terminate; /*!< Terminate transfer flag */ - uint8_t reserved[2]; -} SPIM_DATACONTEXT_T; - -/* Maps config registers bits for SPI mode to the transfer descriptor */ -static const uint32_t spiModeBits[4] = { - (SPI_CFG_CPOL_LO | SPI_CFG_CPHA_FIRST), - (SPI_CFG_CPOL_LO | SPI_CFG_CPHA_SECOND), - (SPI_CFG_CPOL_HI | SPI_CFG_CPHA_FIRST), - (SPI_CFG_CPOL_HI | SPI_CFG_CPHA_SECOND) -}; - -void spim_close_pending_transfer(ROM_SPIM_HANDLE_T pHandle); - -/* FIFO push function using standard SPI FIFO for datum >8 bits */ -static uint16_t _rom_spimMasterFifoPush16(LPC_SPI_T *pSPI, void *data, uint32_t numData, uint32_t curIndex) -{ - uint16_t pushed = 0, *p16 = (uint16_t *) data; - - /* Push as 16-bit value */ - while ((numData > 0) && ((pSPI->STAT & SPI_STAT_TXRDY) != 0)) { - pSPI->TXDAT = (uint32_t) p16[curIndex]; - numData--; - curIndex++; - pushed++; - } - - return pushed; -} - -/* FIFO pop function using standard SPI FIFO for datum >8 bits */ -static uint16_t _rom_spimMasterFifoPop16(LPC_SPI_T *pSPI, void *data, uint32_t numData, uint32_t curIndex) -{ - uint16_t popped = 0, *p16 = (uint16_t *) data; - - /* Pop as 16-bit value */ - while ((numData > 0) && ((pSPI->STAT & SPI_STAT_RXRDY) != 0)) { - p16[curIndex] = (uint16_t) pSPI->RXDAT; - numData--; - curIndex++; - popped++; - } - - return popped; -} - -/* FIFO push function using standard SPI FIFO for datum <=8 bits */ -static uint16_t _rom_spimMasterFifoPush8(LPC_SPI_T *pSPI, void *data, uint32_t numData, uint32_t curIndex) -{ - uint16_t pushed = 0; - uint8_t *p8 = (uint8_t *) data; - - /* Push as 8-bit value */ - while ((numData > 0) && ((pSPI->STAT & SPI_STAT_TXRDY) != 0)) { - pSPI->TXDAT = (uint32_t) p8[curIndex]; - numData--; - curIndex++; - pushed++; - } - - return pushed; -} - -/* FIFO pop function using standard SPI FIFO for datum <=8 bits */ -static uint16_t _rom_spimMasterFifoPop8(LPC_SPI_T *pSPI, void *data, uint32_t numData, uint32_t curIndex) -{ - uint16_t popped = 0; - uint8_t *p8 = (uint8_t *) data; - - /* Pop as 16-bit value */ - while ((numData > 0) && ((pSPI->STAT & SPI_STAT_RXRDY) != 0)) { - p8[curIndex] = (uint8_t) pSPI->RXDAT; - numData--; - curIndex++; - popped++; - } - - return popped; -} - -/* Assert a SPI select */ -static void _rom_spimAssertSSEL(LPC_SPI_T *pSPI, uint8_t sselNum) -{ - /* Assert a SSEL line by driving it low */ - pSPI->TXCTRL &= ~SPI_TXDATCTL_DEASSERTNUM_SSEL(sselNum); -} - -static void _rom_spimCloseTransfer(SPIM_DATACONTEXT_T *pDrv) -{ - /* Transfer terminates after this byte */ - pDrv->xmitOn = 0; - pDrv->base->INTENCLR = SPI_INTENSET_TXDYEN; -} - -static void _rom_spimTransmitHandler(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_XFER_T *pXfer) -{ - SPIM_DATACONTEXT_T *pDrv = (SPIM_DATACONTEXT_T *) pHandle; - - /* Is DMA being used? */ - if ((pXfer->flags & ROM_SPIM_FLAG_DMATX) != 0) { - /* Call transmit callback, callback is pre-validated by setup */ - if (pDrv->pTranCb) { - pDrv->pTranCb(pHandle, pXfer); - - pDrv->base->INTENCLR = SPI_INTENSET_TXDYEN; - } - } - else { /* Transfer without using DMA */ - if ((pXfer->flags & ROM_SPIM_FLAG_TXIGNORE) != 0) { - /* ROM_SPIM_FLAG_TXIGNORE flag is set. Will send 0xFF and decrement txSz, - transfer terminates on last data */ - static const uint16_t sb = 0xFFFF; - if (pDrv->sendIdx >= pXfer->txSz) { - /* Transferring last datum, end transfer */ - spim_close_pending_transfer(pHandle); - } - else { - if (pDrv->sendIdx >= (pXfer->txSz - 1)) { - pDrv->base->TXCTRL |= SPI_TXCTL_EOT; - } - pDrv->sendIdx += pDrv->pPushFN(pDrv->base, (void *) &sb, 1, 0); - } - } - else { - /* Normal data transfer */ - if (pDrv->sendIdx >= pXfer->txSz) { - /* Ran out of data, so stop */ - spim_close_pending_transfer(pHandle); - } - else { - pDrv->sendIdx += pDrv->pPushFN(pDrv->base, (void *) pXfer->txBuff, 1, pDrv->sendIdx); - - /* Call callback for more data */ - if (pDrv->sendIdx >= pXfer->txSz) { - if (pDrv->pTranCb) { - pDrv->pTranCb(pHandle, pXfer); - pDrv->sendIdx = 0; - } - else { - /* No transmit callback, close transfer */ - spim_close_pending_transfer(pHandle); - } - } - } - } - } -} - -static void _rom_spimReceiveHandler(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_XFER_T *pXfer) -{ - SPIM_DATACONTEXT_T *pDrv = (SPIM_DATACONTEXT_T *) pHandle; - - /* Is DMA being used? */ - if ((pXfer->flags & ROM_SPIM_FLAG_DMARX) != 0) { - /* Call receive callback, callback is pre-validated by setup */ - if (pDrv->pRecvCb) { - pDrv->pRecvCb(pHandle, pXfer); - - pDrv->base->INTENCLR = SPI_INTENSET_RXDYEN; - } - } - else { /* Transfer without using DMA */ - /* Normal data transfer */ - if (pDrv->recvIdx >= pXfer->rxSz) { - uint16_t temp; - /* Ran out of data, overflowing */ - pDrv->pendingStatus = ERR_SPI_RXOVERRUN; - pDrv->recvIdx += pDrv->pPopFN(pDrv->base, (void *) &temp, 1, 0); /* Flush data */ - } - else { - pDrv->recvIdx += pDrv->pPopFN(pDrv->base, (void *) pXfer->rxBuff, 1, pDrv->recvIdx); - - /* Call callback for more data */ - if ((pDrv->recvIdx >= pXfer->rxSz) && (pDrv->pRecvCb)) { - pDrv->pRecvCb(pHandle, pXfer); - pDrv->recvIdx = 0; - } - } - } -} - -// ********************************************************** -uint32_t spim_get_mem_size(void) -{ - return sizeof(SPIM_DATACONTEXT_T); -} - -ROM_SPIM_HANDLE_T spim_init(void *mem, const ROM_SPIM_INIT_T *pInit) -{ - SPIM_DATACONTEXT_T *pDrv; - int i; - - /* Verify alignment is at least 4 bytes and clock rate is not 0 */ - if ((((uint32_t) mem & 0x3) != 0) || (pInit->baseClockRate == 0)) { - return NULL; - } - - pDrv = (SPIM_DATACONTEXT_T *) mem; - memset(pDrv, 0, sizeof(SPIM_DATACONTEXT_T)); - - /* Save base of peripheral and pointer to user data */ - pDrv->pUserData = pInit->pUserData; - pDrv->base = (LPC_SPI_T *) pInit->base; - pDrv->baseClockRate = pInit->baseClockRate; - - /* Enable SPI master interface, deassert all chip selects */ - pDrv->base->CFG = 0;/* Forces state machine reset */ - pDrv->base->CFG = SPI_CFG_SPI_EN | SPI_CFG_MASTER_EN; - - /* Set SPI slave select (SSEL) polarity for each slave signal */ - for (i = 0; i <= 3; i++) { - if (pInit->spiPol[i] == 0) { - /* Active low select, high during idle */ - pDrv->base->CFG &= ~(1 << (8 + i)); - } - else { - /* Active high, low during idle */ - pDrv->base->CFG |= (1 << (8 + i)); - } - } - - /* Deassert all chip selects */ - pDrv->base->TXCTRL = SPI_TXDATCTL_DEASSERT_ALL; - - /* Clear pending master statuses - RXOV, TXUR, SSA, SSD, EOT */ - pDrv->base->STAT = (SPI_STAT_RXOV | SPI_STAT_TXUR | SPI_STAT_SSA | - SPI_STAT_SSD | SPI_STAT_EOT); - - return (ROM_SPIM_HANDLE_T) pDrv; -} - -void spim_register_callback(ROM_SPIM_HANDLE_T pHandle, uint32_t cbIndex, void *pCB) -{ - SPIM_DATACONTEXT_T *pDrv = (SPIM_DATACONTEXT_T *) pHandle; - - switch (cbIndex) { - case ROM_SPIM_ASSERTSSEL_CB: - pDrv->pAssertCb = (spiMasterXferCSAssertCB) pCB; - break; - - case ROM_SPIM_DATATRANSMIT_CB: - pDrv->pTranCb = (spiMasterTransmitCB) pCB; - break; - - case ROM_SPIM_DATATRECEIVE_CB: - pDrv->pRecvCb = (spiMasterReceiveCB) pCB; - break; - - case ROM_SPIM_DEASSERTSSEL_CB: - pDrv->pDeassertCb = (spiMMasterXferCSDeAssertCB) pCB; - break; - } -} - -ErrorCode_t spim_setup_transfer(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_XFER_CONFIG_T *pCfg) -{ - SPIM_DATACONTEXT_T *pDrv = (SPIM_DATACONTEXT_T *) pHandle; - uint32_t reg; - - /* Verify config is valid */ - if (pCfg == NULL) { - return ERR_SPI_PARAM; - } - - /* Verify data parameters area valid */ - if ((pCfg->dataBits == 0) || (pCfg->dataBits > 16) || (pCfg->dXferBitRate == 0)) { - return ERR_SPI_PARAM; - } - - /* Verify mode */ - if (pCfg->mode > ROM_SPI_CLOCK_MODE3) { - return ERR_SPI_PARAM; - } - - /* Transfer timing is valid? */ - if ((pCfg->PreDelay > 15) || (pCfg->PostDelay > 15) || (pCfg->FrameDelay > 15) || - (pCfg->TransferDelay > 16)) { - return ERR_SPI_PARAM; - } - - /* Compute real clock rate from desired clock rate */ - reg = pDrv->baseClockRate / pCfg->dXferBitRate; - if ((pDrv->baseClockRate % pCfg->dXferBitRate) != 0) { - reg++; - } - if (reg > 0x10000) { - reg = 0x10000; - } - else if (reg == 0) { - reg = 1; - } - - /* Save pre-computed divider and set real SPI master bit rate for app */ - pDrv->base->DIV = (reg - 1); - pCfg->rXferBitRate = pDrv->baseClockRate / reg; - - /* Setup transfer timing */ - if (pCfg->TransferDelay == 0) { - pCfg->TransferDelay = 1; - } - pDrv->base->DLY = ( - SPI_DLY_PRE_DELAY(pCfg->PreDelay) | - SPI_DLY_POST_DELAY(pCfg->PostDelay) | - SPI_DLY_FRAME_DELAY(pCfg->FrameDelay) | - SPI_DLY_TRANSFER_DELAY(pCfg->TransferDelay - 1)); - - /* Setup transfer mode and LSB/MSB first */ - reg = pDrv->base->CFG; - reg &= ~(SPI_CFG_LSB_FIRST_EN | SPI_CFG_CPHA_SECOND | - SPI_CFG_CPOL_HI); - - /* Setup SPI transfer configuration (CFG register) */ - reg |= spiModeBits[(int) pCfg->mode]; - if (pCfg->lsbFirst) { - reg |= SPI_CFG_LSB_FIRST_EN; - } - pDrv->base->CFG = reg; - - /* Setup SPI transfer configuration (TXCTRL) for data size, don't alter SPI SSEL states */ - reg = pDrv->base->TXCTRL & ~SPI_TXCTL_FLEN(16); - if (pCfg->FrameDelay > 0) { - reg |= SPI_TXCTL_EOF; - } - pDrv->base->TXCTRL = reg | SPI_TXCTL_FLEN(pCfg->dataBits); - - /* Setup FIFO callbacks based on the data transfer width */ - if (pCfg->dataBits > 8) { - pDrv->pPushFN = &_rom_spimMasterFifoPush16; - pDrv->pPopFN = &_rom_spimMasterFifoPop16; - } - else { - pDrv->pPushFN = &_rom_spimMasterFifoPush8; - pDrv->pPopFN = &_rom_spimMasterFifoPop8; - } - - return LPC_OK; -} - -ErrorCode_t spim_transfer(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_XFER_T *pXfer) -{ - SPIM_DATACONTEXT_T *pDrv = (SPIM_DATACONTEXT_T *) pHandle; - uint32_t reg; - uint8_t flen; - - /* Get length of a receive value */ - flen = 1 + (uint8_t) ((pDrv->base->TXCTRL >> 24) & 0xF); - - /* Is transfer descriptor valid? */ - if (pXfer == NULL) { - return ERR_SPI_PARAM; - } - - /* Is slave select valid? */ - if (pXfer->sselNum >= ROM_SPIM_MAXSELECTS) { - pXfer->status = ERR_SPI_PARAM; - return ERR_SPI_PARAM; - } - - /* Verify transmit size, must have at least 1 byte */ - if (pXfer->txSz == 0) { - pXfer->status = ERR_SPI_INVALID_LENGTH; - return ERR_SPI_INVALID_LENGTH; - } - - /* No need to check RX buffer alignment if ROM_SPIM_FLAG_RXIGNORE flag is set */ - if ((pXfer->flags & ROM_SPIM_FLAG_RXIGNORE) == 0) { - if ((pXfer->rxSz == 0) || (pXfer->rxBuff == NULL)) { - pXfer->status = ERR_SPI_PARAM; - return ERR_SPI_PARAM; - } - if ((flen > 8) && ((((uint32_t) pXfer->rxBuff) & 0x1) != 0)) { - /* Receive buffer not 16-bit aligned or not present */ - pXfer->status = ERR_SPI_PARAM; - return ERR_SPI_PARAM; - } - /* Is DMA being used? */ - if ((pXfer->flags & ROM_SPIM_FLAG_DMARX) != 0) { - if (pDrv->pRecvCb == NULL) { - pXfer->status = ERR_SPI_PARAM; - return ERR_SPI_PARAM; - } - } - } - - /* Check transmit buffer alignment */ - if ((pXfer->flags & ROM_SPIM_FLAG_TXIGNORE) == 0) { - if ((pXfer->txSz == 0) || (pXfer->txBuff == NULL)) { - pXfer->status = ERR_SPI_PARAM; - return ERR_SPI_PARAM; - } - if ((flen > 8) && ((((uint32_t) pXfer->txBuff) & 0x1) != 0)) { - pXfer->status = ERR_SPI_PARAM; - return ERR_SPI_PARAM; - } - /* Is DMA being used? */ - if ((pXfer->flags & ROM_SPIM_FLAG_DMATX) != 0) { - if (pDrv->pTranCb == NULL) { - pXfer->status = ERR_SPI_PARAM; - return ERR_SPI_PARAM; - } - } - } - - /* If in loopback mode, set loopback enable */ - reg = pDrv->base->CFG; - if ((pXfer->flags & ROM_SPIM_FLAG_LOOPBACK) != 0) { - reg |= SPI_CFG_LBM_EN; - } - else { - reg &= ~SPI_CFG_LBM_EN; - } - pDrv->base->CFG = reg; - - /* ROM_SPIM_FLAG_RXIGNORE flag */ - reg = pDrv->base->TXCTRL & ~SPI_TXCTL_EOT; - if ((pXfer->flags & ROM_SPIM_FLAG_RXIGNORE) != 0) { - reg |= SPI_TXCTL_RXIGNORE; - } - else { - reg &= ~SPI_TXCTL_RXIGNORE; - } - pDrv->base->TXCTRL = reg; - - /* Save pointer to transfer descriptor and initial status */ - pDrv->pXfer = pXfer; - pXfer->status = ERR_SPI_BUSY; - pDrv->pendingStatus = LPC_OK; - pDrv->sendIdx = pDrv->recvIdx = 0; - - /* Transmit start, no terminate */ - pDrv->xmitOn = 1; - pDrv->terminate = 0; - - /* Start transfer by asserting selected slave */ - _rom_spimAssertSSEL(pDrv->base, pXfer->sselNum); - - /* Enable SPI interrupts for master */ - pDrv->base->INTENSET = SPI_INTENSET_RXDYEN | SPI_INTENSET_TXDYEN | - SPI_INTENSET_SSAEN | SPI_INTENSET_SSDEN; - - /* Is transfer blocking? */ - if ((pXfer->flags & ROM_SPIM_FLAG_BLOCKING) != 0) { - while (pXfer->status == ERR_SPI_BUSY) { - spim_transfer_handler(pHandle); - } - } - - return pXfer->status; -} - -// Otime = "optimize for speed of code execution" -// ...add this pragma 1 line above the interrupt service routine function. -void spim_transfer_handler(ROM_SPIM_HANDLE_T pHandle) -{ - SPIM_DATACONTEXT_T *pDrv = (SPIM_DATACONTEXT_T *) pHandle; - ROM_SPIM_XFER_T *pXfer = pDrv->pXfer; - uint32_t status = pDrv->base->STAT; - - /* Master asserts slave */ - if ((status & SPI_STAT_SSA) != 0) { - pDrv->base->STAT = SPI_STAT_SSA; - pDrv->base->INTENCLR = SPI_INTENSET_SSAEN; - - /* Master SSEL assertion callback */ - if (pDrv->pAssertCb != NULL) { - pDrv->pAssertCb(pHandle, pXfer); - } - } - - /* Transmit data handler */ - if (((status & SPI_STAT_TXRDY) != 0) && (pDrv->xmitOn == 1)) { - /* Handle transmit */ - _rom_spimTransmitHandler(pHandle, pXfer); - } - - /* Receive data handler */ - if ((status & SPI_STAT_RXRDY) != 0) { - /* Handle receive */ - _rom_spimReceiveHandler(pHandle, pXfer); - } - - /* If the controller is stalled and the transmit is finished, close the transfer - or be stuck in a stalled condition indefinitely. */ - if (((status & SPI_STAT_STALLED) != 0) && (pDrv->xmitOn == 0)) { - spim_close_pending_transfer(pHandle); - } - - /* Master SSEL de-assertion callback */ - if ((status & SPI_STAT_SSD) != 0) { - pDrv->base->STAT = SPI_STAT_SSD; - pDrv->base->INTENCLR = SPI_INTENSET_SSAEN | SPI_INTENSET_SSDEN | - SPI_INTENSET_RXDYEN | SPI_INTENSET_TXDYEN; - pXfer->status = pDrv->pendingStatus; - - /* De-assetion event */ - if (pDrv->pDeassertCb != NULL) { - pDrv->pDeassertCb(pHandle, pXfer); - } - } -} - -void spim_close_pending_transfer(ROM_SPIM_HANDLE_T pHandle) -{ - SPIM_DATACONTEXT_T *pDrv = (SPIM_DATACONTEXT_T *) pHandle; - - /* If stalled, force an EOT */ - if ((pDrv->base->STAT & SPI_STAT_STALLED) != 0) { - pDrv->base->STAT = SPI_STAT_EOT; - } - pDrv->base->TXCTRL |= SPI_TXCTL_EOT; - - _rom_spimCloseTransfer(pDrv); -} - -uint32_t spim_get_driver_version(void) -{ - return DRVVERSION; -} - -// ********************************************************* diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spimd.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spimd.h deleted file mode 100644 index bc16b59cb65..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spimd.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * @brief SPI master ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __HW_SPIMD_H -#define __HW_SPIMD_H - -#include "error.h" -#include "hw_spimd_rom_api.h" - -// *** SPI functions called by Application Program *** -uint32_t spim_get_mem_size(void); - -ROM_SPIM_HANDLE_T spim_init(void *mem, const ROM_SPIM_INIT_T *pInit); - -void spim_register_callback(ROM_SPIM_HANDLE_T pHandle, uint32_t cbIndex, void *pCB); - -ErrorCode_t spim_setup_transfer(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_XFER_CONFIG_T *pCfg); - -ErrorCode_t spim_transfer(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_XFER_T *pXfer); - -void spim_transfer_handler(ROM_SPIM_HANDLE_T pHandle); - -void spim_close_pending_transfer(ROM_SPIM_HANDLE_T pHandle); - -uint32_t spim_get_driver_version(void); - -// *** - -#endif /* __HW_SPIMD_H */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spimd_rom_api.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spimd_rom_api.c deleted file mode 100644 index 55dc07b4748..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spimd_rom_api.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * @brief SPI master ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "hw_spimd.h" - -// This creates a table with the addresses of all the SPI functions -// This table of function pointers is the API interface. -const ROM_SPIMD_API_T spim_api = { - &spim_get_mem_size, - &spim_init, - &spim_register_callback, - &spim_setup_transfer, - &spim_transfer, - &spim_transfer_handler, - &spim_close_pending_transfer, - &spim_get_driver_version, -}; // end of table ************************************ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spimd_rom_api.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spimd_rom_api.h deleted file mode 100644 index 78d1e417295..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spimd_rom_api.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * @brief SPI master ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __HW_SPIMD_ROM_API_H -#define __HW_SPIMD_ROM_API_H - -#include "stdint.h" // added to define uint32_t, etc. -#include "error.h" -#include "packing.h" -#include "hw_spi_common.h" - -/** @defgroup ROMAPI_SPIM SPI master ROM driver functions and definitions - * @ingroup ROMAPI_SPIM_WRAPPER - * @{ - */ - -/** @brief SPI master handle type */ -typedef void *ROM_SPIM_HANDLE_T; - -/* Number of selects the SPI driver supports */ -#define ROM_SPIM_MAXSELECTS (4) - -/** @brief User context conversion macro - * Macro used to extract the user defined data pointer from a SPI master - * handle context.
- * To get a user context, simple use the macro on the drivers handle: - * void *pUserData = (void *) ROM_SPIM_HANDLE_TOUDATA(driverHandle); - */ -#define ROM_SPIM_HANDLE_TOUDATA(p) (void *) (*(uint32_t *) p) - -/** @brief SPI master optional transfer flags */ -#define ROM_SPIM_FLAG_BLOCKING (1UL << 31) /*!< Transfer function will block until complete */ -#define ROM_SPIM_FLAG_DMATX (1UL << 30) /*!< DMA will be used for TX, requires DMA setup outside of the driver */ -#define ROM_SPIM_FLAG_DMARX (1UL << 29) /*!< DMA will be used for RX, requires DMA setup outside of the driver */ -#define ROM_SPIM_FLAG_LOOPBACK (1UL << 28) /*!< Enables loopback mode for the transfer, useful for testing only */ -#define ROM_SPIM_FLAG_TXIGNORE (1UL << 27) /*!< Ignores receive data regardless of txBuff, transmit data callback will not be called, stops when txSz = 0 */ -#define ROM_SPIM_FLAG_RXIGNORE (1UL << 26) /*!< Ignores receive data regardless of rxBuff/rxSz, receive data callback will not be called */ -#define ROM_SPIM_FLAG_USERBITS (0xFFFF) /*!< Application can safely use the flag bits designated by this mask */ - -/** @brief SPI transfer configuration structure - once of these needs to be setup for - * each SPI select (SSEL) used on the master. If only SSEL0 is used, it only needs to be setup - * for that one slave select. This structure must be statically allocated for use with the - * driver and should not be created on the program stack. If anything in this structure - * changes, SetupSSEL() must be called again with the structure reference. */ -typedef PRE_PACK struct POST_PACK { - uint32_t dXferBitRate; /*!< Desired bit transfer rate (SPI clock) in Hz */ - uint32_t rXferBitRate; /*!< Real bit transfer rate (SPI clock) in Hz, modified by driver to actual rate */ - uint8_t mode; /*!< Mode selection for this transfer (ROM_SPI_CLOCK_MODE_T) */ - uint8_t lsbFirst; /*!< 0 for msb sent/recv first, !0 = for lsb send/recv first */ - uint8_t dataBits; /*!< Data transfer size in bits, between 1 and 16, txBuff and rxBuff must be 16-bit aligned if >8 */ - /* The time delays are based in SPI clocks (rXferBitRate). These values are used to configure the - SPI delays when a transfer is started, so these values do not need to be populated for the - SetupSSEL() function. The actual (rXferBitRate) and desired (dXferBitRate) SPI clocks may differ, - and the actual clock won't be known until after SetupSSEL() is called, so it's best to setup - these values after the call to SetupSSEL(). */ - uint8_t PreDelay; /*!< Pre-delay value in (rXferBitRate) SPI clocks, 0 - 15 */ - uint8_t PostDelay; /*!< Post-delay value in (rXferBitRate) SPI clocks, 0 - 15 */ - uint8_t FrameDelay; /*!< Delay value between frames of a transfer in (rXferBitRate) SPI clocks, 0 - 15 */ - uint8_t TransferDelay; /*!< Delay value between transfers in (rXferBitRate) SPI clocks, 1 - 16 */ - uint8_t reserved; -} ROM_SPIM_XFER_CONFIG_T; - -/** @brief SPI Master transfer descriptor */ -typedef PRE_PACK struct POST_PACK { - const void *txBuff; /*!< Pointer to array of datum to be transmitted, use NULL for receive only, must be 16-bit aligned if datum bits >8 */ - uint32_t txSz; /*!< Size of the transmit buffer (txBuff) in items (not bytes) before transmit callback is called */ - void *rxBuff; /*!< Pointer memory where datum received from SPI be stored, use NULL for transmit only, must be 16-bit aligned if datum bits >8 */ - uint32_t rxSz; /*!< Size of the receive buffer (rxBuff) in items (not bytes) before receive callback is called */ - uint32_t flags; /*!< Optional transfer flags, may be modified by driver */ - volatile ErrorCode_t status; /*!< Status of the current SPI transfer (ErrorCode_t), must be 32-bits */ - uint8_t sselNum; /*!< SPI master SSEL number for this transfer, 0 - 3 */ - uint8_t reserved1[3]; -} ROM_SPIM_XFER_T; - -/** @brief SPI master callback IDs */ -typedef enum { - ROM_SPIM_ASSERTSSEL_CB = 0, /*!< Callback ID for SPI master SSEL assertion */ - ROM_SPIM_DATATRANSMIT_CB, /*!< Callback ID for SPI master transmit start */ - ROM_SPIM_DATATRECEIVE_CB, /*!< Callback ID for SPI master receive start */ - ROM_SPIM_DEASSERTSSEL_CB /*!< Callback ID for SPI master SSEL de-assertion */ -} ROM_SPIM_CALLBACK_T; - -/** @brief SPI master select assert callback - * This callback is called from the SPI master handler when the SPI master - * selects the slave (asserts SSEL). The callback is only called if it has been registered.
- */ -typedef void (*spiMasterXferCSAssertCB)(ROM_SPIM_HANDLE_T spimHandle, ROM_SPIM_XFER_T *pXfer); - -/** @brief SPI master data receive start callback - * The SPI master state machine will call this optional function when it needs a buffer to - * receive data. The callback can be used to setup DMA or alter the receive buffer size. The - * callback is only called if it has been registered, the buffer has been fully used, and - * data is needed to populate the transmit FIFO. When using DMA, this callback must be enabled - * and used for DMA setup. - */ -typedef void (*spiMasterReceiveCB)(ROM_SPIM_HANDLE_T spimHandle, ROM_SPIM_XFER_T *pXfer); - -/** @brief SPI master data transmit start callback - * The SPI master state machine will call this optional function for data transfer. - * The callback can be used to setup DMA or alter the receive buffer size. The callback is - * only called if it has been registered, the buffer has been fully used, and data is pending - * is the receive FIFO. When using DMA, this callback must be enabled and used for DMA setup. - */ -typedef void (*spiMasterTransmitCB)(ROM_SPIM_HANDLE_T spimHandle, ROM_SPIM_XFER_T *pXfer); - -/** @brief SPI master transfer select deassert data callback - * This callback is called from the SPI master handler when the SPI master - * deasserts the slave select. The callback is only called if it has been registered.
- */ -typedef void (*spiMMasterXferCSDeAssertCB)(ROM_SPIM_HANDLE_T spimHandle, ROM_SPIM_XFER_T *pXfer); - -/** @brief SPI master initialization structure */ -typedef PRE_PACK struct POST_PACK { - void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */ - uint32_t base; /*!< Base address of SPI peripheral to use */ - uint32_t baseClockRate; /*!< SPI base clock rate in Hz, call Init() again if this rate changes */ - uint8_t spiPol[4]; /*!< SPI SSEL pollarity for each slave select, 0 = active low, !0 = active high */ -} ROM_SPIM_INIT_T; - -/** @brief SPI master ROM indirect function structure */ -typedef PRE_PACK struct POST_PACK { - uint32_t (*GetMemSize)(void); /*!< Returns needed memory size required for run-time context of SPI master driver */ - ROM_SPIM_HANDLE_T (*Init)(void *mem, const ROM_SPIM_INIT_T *pInit); /*!< Initializes the SPI master driver and peripheral */ - void (*RegisterCallback)(ROM_SPIM_HANDLE_T pHandle, uint32_t cbIndex, void *pCB); /*!< Registers an SPI master callback */ - ErrorCode_t (*SetupTransfer)(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_XFER_CONFIG_T *pCfg); /*!< Sets up a master select's transfer configuration, should be called when the transfer configuration changes */ - ErrorCode_t (*Transfer)(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_XFER_T *pXfer); /*!< Perform or start and SPI master transfer */ - void (*TransferHandler)(ROM_SPIM_HANDLE_T pHandle); /*!< SPI master transfer (interrupt) handler */ - void (*ClosePendingTransfer)(ROM_SPIM_HANDLE_T pHandle); /*!< Immediately terminates the current transfer */ - uint32_t (*GetDriverVersion)(void); -} ROM_SPIMD_API_T; - -/** - * @} - */ - -extern const ROM_SPIMD_API_T spim_api; // so application program can access pointer to -// function table - -#endif /* __HW_SPIMD_ROM_API_H */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spisd.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spisd.c deleted file mode 100644 index 6994f992114..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spisd.c +++ /dev/null @@ -1,535 +0,0 @@ -/* - * @brief SPI slave ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include -#include -#include "hw_spisd.h" - -#define DRVVERSION 0x0100 - -/* Private callback for FIFO push and pop functions. This privately maps - to the VFIFO for the SPI slave, but can be overriden if needed. The driver will - automatically pick the right implementation at run-time based on the transfer - size in the transfer descriptor. */ -typedef uint16_t (*spisSlaveFifoPushFN)(LPC_SPI_T *pSPI, void *data, uint32_t sendBytes, uint32_t curIndex); -typedef uint16_t (*spisSlaveFifoPopFN)(LPC_SPI_T *pSPI, void *data, uint32_t bytes, uint32_t curIndex); - -/* Private data structure used for the SPI slave driver, holds the driver and - peripheral context */ -typedef struct { - void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */ - LPC_SPI_T *base; /*!< Base address of SPI peripheral to use */ - spisSlaveXferCSAssertCB pAssertCb; /*!< SSEL assertion callback */ - spisSlaveTransmitCB pTranCb; /*!< Transmit data start callback */ - spisSlaveReceiveCB pRecvCb; /*!< Receive data start callback */ - spisSlaveXferCSDeAssertCB pDeassertCb; /*!< SSEL deassertion callback */ - spisSlaveFifoPushFN pPushFN; /*!< Pointer to current FIFO push function */ - spisSlaveFifoPopFN pPopFN; /*!< Pointer to current FIFO pop function */ - ROM_SPIS_XFER_T *pXfer; /*!< Pointer to current transfer descriptor */ - uint32_t sendIdx; /*!< Current transmit buffer index */ - uint32_t recvIdx; /*!< Current receive buffer index */ - ErrorCode_t pendingStatus; /*!< Pending transfer status */ -} SPIS_DATACONTEXT_T; - -/* Maps config registers bits for SPI mode to the transfer descriptor */ -static const uint32_t spiModeBits[4] = { - (SPI_CFG_CPOL_LO | SPI_CFG_CPHA_FIRST), - (SPI_CFG_CPOL_LO | SPI_CFG_CPHA_SECOND), - (SPI_CFG_CPOL_HI | SPI_CFG_CPHA_FIRST), - (SPI_CFG_CPOL_HI | SPI_CFG_CPHA_SECOND) -}; - -/* FIFO push function using standard SPI FIFO for datum >8 bits */ -static uint16_t _rom_spisSlaveFifoPush16(LPC_SPI_T *pSPI, void *data, uint32_t numData, uint32_t curIndex) -{ - uint16_t pushed = 0, *p16 = (uint16_t *) data; - - /* Push as 16-bit value */ - while ((numData > 0) && ((pSPI->STAT & SPI_STAT_TXRDY) != 0)) { - pSPI->TXDAT = (uint32_t) p16[curIndex]; - numData--; - curIndex++; - pushed++; - } - - return pushed; -} - -/* FIFO pop function using standard SPI FIFO for datum >8 bits */ -static uint16_t _rom_spisSlaveFifoPop16(LPC_SPI_T *pSPI, void *data, uint32_t numData, uint32_t curIndex) -{ - uint16_t popped = 0, *p16 = (uint16_t *) data; - - /* Pop as 16-bit value */ - while ((numData > 0) && ((pSPI->STAT & SPI_STAT_RXRDY) != 0)) { - p16[curIndex] = (uint16_t) pSPI->RXDAT; - numData--; - curIndex++; - popped++; - } - - return popped; -} - -/* FIFO push function using standard SPI FIFO for datum <=8 bits */ -static uint16_t _rom_spisSlaveFifoPush8(LPC_SPI_T *pSPI, void *data, uint32_t numData, uint32_t curIndex) -{ - uint16_t pushed = 0; - uint8_t *p8 = (uint8_t *) data; - - /* Push as 8-bit value */ - while ((numData > 0) && ((pSPI->STAT & SPI_STAT_TXRDY) != 0)) { - pSPI->TXDAT = (uint32_t) p8[curIndex]; - numData--; - curIndex++; - pushed++; - } - - return pushed; -} - -/* FIFO pop function using standard SPI FIFO for datum <=8 bits */ -static uint16_t _rom_spisSlaveFifoPop8(LPC_SPI_T *pSPI, void *data, uint32_t numData, uint32_t curIndex) -{ - uint16_t popped = 0; - uint8_t *p8 = (uint8_t *) data; - - /* Pop as 16-bit value */ - while ((numData > 0) && ((pSPI->STAT & SPI_STAT_RXRDY) != 0)) { - p8[curIndex] = (uint8_t) pSPI->RXDAT; - numData--; - curIndex++; - popped++; - } - - return popped; -} - -static void _rom_spisTransmitHandler(ROM_SPIS_HANDLE_T pHandle, ROM_SPIS_XFER_T *pXfer) -{ - SPIS_DATACONTEXT_T *pDrv = (SPIS_DATACONTEXT_T *) pHandle; - - /* This shouldn't be called if there is no transfer descriptor */ - if (!pXfer) { - pDrv->base->INTENCLR = SPI_INTENSET_TXDYEN; - return; - } - - /* Is DMA being used? */ - if ((pXfer->flags & ROM_SPIS_FLAG_DMATX) != 0) { - /* Call transmit callback, callback is pre-validated by setup */ - if (pDrv->pTranCb) { - pDrv->pTranCb(pHandle, pXfer); - } - - pDrv->base->INTENCLR = SPI_INTENSET_TXDYEN; - } - else { /* Transfer without using DMA */ - if ((pXfer->flags & ROM_SPIS_FLAG_TXIGNORE) != 0) { - /* ROM_SPIS_FLAG_TXIGNORE flag is set. Will send 0xFF */ - static const uint16_t sb = 0xFFFF; - pDrv->sendIdx += pDrv->pPushFN(pDrv->base, (void *) &sb, 1, 0); - } - else { - uint32_t bs; - - /* Normal data transfer */ - if (pDrv->sendIdx >= pXfer->txSz) { - /* Ran out of data, get more data */ - if (pDrv->pTranCb) { - pDrv->pTranCb(pHandle, pXfer); - pDrv->sendIdx = 0; - } - } - - if (pDrv->sendIdx < pXfer->txSz) { - bs = pDrv->pPushFN(pDrv->base, (void *) pXfer->txBuff, 1, pDrv->sendIdx); - pDrv->sendIdx += bs; - pXfer->txSent += bs; - } - else { - /* Out of transmit data and no more is provided via the callback, - so disable the transmit interrupt and let the hardware underflow - and send 0. It will only underflow if the master requests data - beyond what is in the transmit FIFO now. The underflow error code - needs to be handled as part of the hardware since this may not be - an underflow condition is the master stops on this datum. */ - pDrv->base->INTENCLR = SPI_INTENSET_TXDYEN; - } - } - } -} - -static void _rom_spisReceiveHandler(ROM_SPIS_HANDLE_T pHandle, ROM_SPIS_XFER_T *pXfer) -{ - SPIS_DATACONTEXT_T *pDrv = (SPIS_DATACONTEXT_T *) pHandle; - - /* This shouldn't be called if there is no transfer descriptor */ - if (!pXfer) { - pDrv->base->INTENCLR = SPI_INTENSET_RXDYEN; - return; - } - - /* Is DMA being used? */ - if ((pXfer->flags & ROM_SPIS_FLAG_DMARX) != 0) { - /* Call receive callback, callback is pre-validated by setup */ - if (pDrv->pRecvCb) { - pDrv->pRecvCb(pHandle, pXfer); - } - - pDrv->base->INTENCLR = SPI_INTENSET_RXDYEN; - } - else { /* Transfer without using DMA */ - if ((pXfer->flags & ROM_SPIS_FLAG_RXIGNORE) != 0) { - /* ROM_SPIS_FLAG_RXIGNORE flag is set. Toss data */ - uint16_t temp; - pDrv->recvIdx += pDrv->pPopFN(pDrv->base, (void *) &temp, 1, 0); - } - else { - uint32_t br; - - /* Normal data transfer */ - if (pDrv->recvIdx >= pXfer->rxSz) { - uint16_t temp; - /* Ran out of data, overflowing */ - pDrv->pendingStatus = ERR_SPI_RXOVERRUN; - br = pDrv->pPopFN(pDrv->base, (void *) &temp, 1, 0);/* Flush data */ - } - else { - br = pDrv->pPopFN(pDrv->base, (void *) pXfer->rxBuff, 1, pDrv->recvIdx); - pXfer->rxRecv += br; - pDrv->recvIdx += br; - - /* Call callback for more data */ - if ((pDrv->recvIdx >= pXfer->rxSz) && (pDrv->pRecvCb)) { - pDrv->pRecvCb(pHandle, pXfer); - pDrv->recvIdx = 0; - } - } - } - } -} - -/* Determine SSEL associated with the current data value */ -static uint8_t Chip_SPIS_FindSSEL(LPC_SPI_T *pSPI, uint32_t data) -{ - int i; - - /* Return first active SSEL starting at SSEL0 */ - for (i = 0; i <= 3; i++) { - if ((data & SPI_RXDAT_RXSSELNUM_INACTIVE(i)) == 0) { - /* Signal is active on low */ - return (uint8_t) i; - } - } - - return 0; -} - -// ********************************************************** -uint32_t spis_get_mem_size(void) -{ - return sizeof(SPIS_DATACONTEXT_T); -} - -ROM_SPIS_HANDLE_T spis_init(void *mem, const ROM_SPIS_INIT_T *pInit) -{ - SPIS_DATACONTEXT_T *pDrv; - int i; - - /* Verify alignment is at least 4 bytes */ - if (((uint32_t) mem & 0x3) != 0) { - return NULL; - } - - pDrv = (SPIS_DATACONTEXT_T *) mem; - memset(pDrv, 0, sizeof(SPIS_DATACONTEXT_T)); - - /* Save base of peripheral and pointer to user data */ - pDrv->pUserData = pInit->pUserData; - pDrv->base = (LPC_SPI_T *) pInit->base; - - /* Enable SPI slave interface */ - pDrv->base->CFG = 0; - pDrv->base->CFG = SPI_CFG_SPI_EN; - - /* Set SPI slave select (SSEL) polarity for each slave signal */ - for (i = 0; i <= 3; i++) { - if (pInit->spiPol[i] == 0) { - /* Active low select, high during idle */ - pDrv->base->CFG &= ~(1 << (8 + i)); - } - else { - /* Active high, low during idle */ - pDrv->base->CFG |= (1 << (8 + i)); - } - } - - /* Enable SPI slave interface, deassert all chip selects (not needed for slave) */ - pDrv->base->TXCTRL = SPI_TXDATCTL_DEASSERT_ALL; - - /* Clear pending slave statuses - RXOV, TXUR, SSA, SSD, EOT */ - pDrv->base->STAT = (SPI_STAT_RXOV | SPI_STAT_TXUR | SPI_STAT_SSA | - SPI_STAT_SSD | SPI_STAT_EOT); - - return (ROM_SPIS_HANDLE_T) pDrv; -} - -void spis_register_callback(ROM_SPIS_HANDLE_T pHandle, uint32_t cbIndex, void *pCB) -{ - SPIS_DATACONTEXT_T *pDrv = (SPIS_DATACONTEXT_T *) pHandle; - - switch (cbIndex) { - case ROM_SPIS_ASSERTSSEL_CB: - pDrv->pAssertCb = (spisSlaveXferCSAssertCB) pCB; - break; - - case ROM_SPIS_DATATRANSMIT_CB: - pDrv->pTranCb = (spisSlaveTransmitCB) pCB; - break; - - case ROM_SPIS_DATATRECEIVE_CB: - pDrv->pRecvCb = (spisSlaveReceiveCB) pCB; - break; - - case ROM_SPIS_DEASSERTSSEL_CB: - pDrv->pDeassertCb = (spisSlaveXferCSDeAssertCB) pCB; - break; - } -} - -ErrorCode_t spis_setup_slave(ROM_SPIS_HANDLE_T pHandle, ROM_SPIS_SLAVE_T *pCfg) -{ - SPIS_DATACONTEXT_T *pDrv = (SPIS_DATACONTEXT_T *) pHandle; - uint32_t reg; - - /* Verify config is valid */ - if (pCfg == NULL) { - return ERR_SPI_PARAM; - } - - /* Verify data parameters area valid */ - if ((pCfg->dataBits == 0) || (pCfg->dataBits > 16)) { - return ERR_SPI_PARAM; - } - - /* Verify mode */ - if (pCfg->mode > ROM_SPI_CLOCK_MODE3) { - return ERR_SPI_PARAM; - } - - /* Setup transfer mode and LSB/MSB first */ - reg = pDrv->base->CFG; - reg &= ~(SPI_CFG_LSB_FIRST_EN | SPI_CFG_CPHA_SECOND | - SPI_CFG_CPOL_HI); - - /* Setup SPI transfer configuration (CFG register) */ - reg |= spiModeBits[(int) pCfg->mode]; - if (pCfg->lsbFirst) { - reg |= SPI_CFG_LSB_FIRST_EN; - } - pDrv->base->CFG = reg; - - /* Setup SPI transfer configuration (TXCTRL) for data size, don't alter SPI SSEL states */ - reg = pDrv->base->TXCTRL & ~SPI_TXCTL_FLEN(16); - pDrv->base->TXCTRL = reg | SPI_TXCTL_FLEN(pCfg->dataBits); - - /* Setup FIFO callbacks based on the data transfer width */ - if (pCfg->dataBits > 8) { - pDrv->pPushFN = &_rom_spisSlaveFifoPush16; - pDrv->pPopFN = &_rom_spisSlaveFifoPop16; - } - else { - pDrv->pPushFN = &_rom_spisSlaveFifoPush8; - pDrv->pPopFN = &_rom_spisSlaveFifoPop8; - } - - /* Enable SPI interrupts for slave */ - pDrv->base->INTENSET = SPI_INTENSET_SSAEN | SPI_INTENSET_SSDEN | - SPI_INTENSET_RXOVEN | SPI_INTENSET_TXUREN; - - return LPC_OK; -} - -void spis_transfer_handler(ROM_SPIS_HANDLE_T pHandle) -{ - SPIS_DATACONTEXT_T *pDrv = (SPIS_DATACONTEXT_T *) pHandle; - ROM_SPIS_XFER_T *pXfer = pDrv->pXfer; - - /* Master asserts slave */ - if ((pDrv->base->INTSTAT & SPI_INTSTAT_SSA) != 0) { - pDrv->base->STAT = SPI_STAT_SSA; - - /* Slave SSEL assertion callback */ - if (pDrv->pAssertCb != NULL) { - /* If if takes too long to handle this event, there may also be - recevied data with the asserted SSEL status. The best way to prevent - this is to have the master provide a SSEL setup delay between the - start of the SSEL assertion and the transfer of the first datum, or - disable the assertion callback and ignore this event. */ - /* Note that setting up transfer buffers based on the slave address is - the assertion callback may result in a transmit underflow. */ - uint32_t data = pDrv->base->RXDAT; - pDrv->pAssertCb(pHandle, Chip_SPIS_FindSSEL(pDrv->base, data)); - - /* Update transfer descriptor */ - pXfer = pDrv->pXfer; - } - - /* Disable assertion interrupt, enable deassertion interrupt */ - pDrv->base->INTENCLR = SPI_INTENSET_SSAEN; - pDrv->base->INTENSET = SPI_INTENSET_SSDEN | SPI_INTENSET_RXDYEN | SPI_INTENSET_TXDYEN; - } - - /* If overrun or underrun errors occured, latch the error */ - if ((pDrv->base->INTSTAT & SPI_INTSTAT_TXUR) != 0) { - pDrv->pendingStatus = ERR_SPI_TXUNDERRUN; - pDrv->base->STAT = SPI_STAT_TXUR; - } - - /* Receive overflow takes precedence over TX */ - if ((pDrv->base->INTSTAT & SPI_INTSTAT_RXOV) != 0) { - pDrv->pendingStatus = ERR_SPI_RXOVERRUN; - pDrv->base->STAT = SPI_STAT_RXOV; - } - - if ((pDrv->base->INTSTAT & SPI_INTSTAT_TXRDY) != 0) { - /* Handle transmit */ - _rom_spisTransmitHandler(pHandle, pXfer); - } - - /* Receive data handler */ - if ((pDrv->base->INTSTAT & SPI_INTSTAT_RXRDY) != 0) { - /* Handle receive */ - _rom_spisReceiveHandler(pHandle, pXfer); - } - - /* Slave SSEL de-assertion callback */ - if ((pDrv->base->INTSTAT & SPI_INTSTAT_SSD) != 0) { - pDrv->base->STAT = SPI_STAT_SSD | SPI_STAT_RXOV | SPI_STAT_TXUR; - pDrv->base->INTENSET = SPI_INTENSET_SSAEN; - pDrv->base->INTENCLR = SPI_INTENSET_SSDEN | SPI_INTENSET_RXDYEN | SPI_INTENSET_TXDYEN; - - if (pXfer) { - pXfer->status = pDrv->pendingStatus; - pDrv->pXfer = NULL; - } - - /* On de-assertion, flush any data left in the transmmit and receive FIFO. - This is needed when streaming data and the size of the transfer isn't - known, so data may be left to transmit when the master deasserts. */ - pDrv->base->CFG &= ~SPI_CFG_SPI_EN; - pDrv->base->CFG |= SPI_CFG_SPI_EN; - - /* De-assetion event */ - if (pDrv->pDeassertCb != NULL) { - pDrv->pDeassertCb(pHandle, pXfer); - } - } -} - -ErrorCode_t spis_transfer(ROM_SPIS_HANDLE_T pHandle, ROM_SPIS_XFER_T *pXfer) -{ - SPIS_DATACONTEXT_T *pDrv = (SPIS_DATACONTEXT_T *) pHandle; - uint8_t flen; - - /* Get length of a receive value */ - flen = 1 + (uint8_t) ((pDrv->base->TXCTRL >> 24) & 0xF); - - /* Is transfer descriptor valid? */ - if (pXfer == NULL) { - return ERR_SPI_PARAM; - } - - /* No need to check RX buffer alignment if ROM_SPIS_FLAG_RXIGNORE flag is set */ - if ((pXfer->flags & ROM_SPIS_FLAG_RXIGNORE) == 0) { - if ((pXfer->rxSz == 0) || (pXfer->rxBuff == NULL)) { - pXfer->status = ERR_SPI_PARAM; - return ERR_SPI_PARAM; - } - if ((flen > 8) && ((((uint32_t) pXfer->rxBuff) & 0x1) != 0)) { - /* Receive buffer not 16-bit aligned or not present */ - pXfer->status = ERR_SPI_PARAM; - return ERR_SPI_PARAM; - } - /* Is DMA being used? */ - if ((pXfer->flags & ROM_SPIS_FLAG_DMARX) != 0) { - if (pDrv->pRecvCb == NULL) { - pXfer->status = ERR_SPI_PARAM; - return ERR_SPI_PARAM; - } - } - } - - /* Check transmit buffer alignment */ - if ((pXfer->flags & ROM_SPIS_FLAG_TXIGNORE) == 0) { - if ((pXfer->txSz == 0) || (pXfer->txBuff == NULL)) { - pXfer->status = ERR_SPI_PARAM; - return ERR_SPI_PARAM; - } - if ((flen > 8) && ((((uint32_t) pXfer->txBuff) & 0x1) != 0)) { - pXfer->status = ERR_SPI_PARAM; - return ERR_SPI_PARAM; - } - /* Is DMA being used? */ - if ((pXfer->flags & ROM_SPIS_FLAG_DMATX) != 0) { - if (pDrv->pTranCb == NULL) { - pXfer->status = ERR_SPI_PARAM; - return ERR_SPI_PARAM; - } - } - } - - /* ROM_SPIS_FLAG_RXIGNORE flag */ - if ((pXfer->flags & ROM_SPIS_FLAG_RXIGNORE) != 0) { - pDrv->base->TXCTRL |= SPI_TXCTL_RXIGNORE; - } - else { - pDrv->base->TXCTRL &= ~SPI_TXCTL_RXIGNORE; - } - - /* Save pointer to transfer descriptor and initial status */ - pDrv->pXfer = pXfer; - pXfer->status = ERR_SPI_BUSY; - pDrv->pendingStatus = LPC_OK; - pDrv->sendIdx = pDrv->recvIdx = pXfer->txSent = pXfer->rxRecv = 0; - - pDrv->base->INTENSET = SPI_INTENSET_RXDYEN | SPI_INTENSET_TXDYEN; - - return pXfer->status; -} - -uint32_t spis_get_driver_version(void) -{ - return DRVVERSION; -} - -// ********************************************************* diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spisd.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spisd.h deleted file mode 100644 index 2c7b5082351..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spisd.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * @brief SPI slave ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __HW_SPISD_H -#define __HW_SPISD_H - -#include "error.h" -#include "hw_spisd_rom_api.h" - -// *** SPI functions called by Application Program *** -uint32_t spis_get_mem_size(void); - -ROM_SPIS_HANDLE_T spis_init(void *mem, const ROM_SPIS_INIT_T *pInit); - -void spis_register_callback(ROM_SPIS_HANDLE_T pHandle, uint32_t cbIndex, void *pCB); - -ErrorCode_t spis_setup_slave(ROM_SPIS_HANDLE_T pHandle, ROM_SPIS_SLAVE_T *pCfg); - -void spis_transfer_handler(ROM_SPIS_HANDLE_T pHandle); - -ErrorCode_t spis_transfer(ROM_SPIS_HANDLE_T pHandle, ROM_SPIS_XFER_T *pXfer); - -uint32_t spis_get_driver_version(void); - -// *** - -#endif /* __HW_SPISD_H */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spisd_rom_api.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spisd_rom_api.c deleted file mode 100644 index 7ae7676f237..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spisd_rom_api.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * @brief SPI slave ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "hw_spisd.h" - -// This creates a table with the addresses of all the SPI functions -// This table of function pointers is the API interface. -const ROM_SPISD_API_T spis_api = { - &spis_get_mem_size, - &spis_init, - &spis_register_callback, - &spis_setup_slave, - &spis_transfer, - &spis_transfer_handler, - &spis_get_driver_version, -}; // end of table ************************************ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spisd_rom_api.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spisd_rom_api.h deleted file mode 100644 index 0a73a556be6..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_spisd_rom_api.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * @brief SPI slave ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __HW_SPISD_ROM_API_H -#define __HW_SPISD_ROM_API_H - -#include "stdint.h" // added to define uint32_t, etc. -#include "error.h" -#include "packing.h" -#include "hw_spi_common.h" - -/** @defgroup ROMAPI_SPIS SPI slave ROM driver functions and definitions - * @ingroup ROMAPI_SPIS_WRAPPER - * @{ - */ - -/** @brief SPI slave handle type */ -typedef void *ROM_SPIS_HANDLE_T; - -/** @brief Number of selects the SPI driver supports */ -#define ROM_SPIS_MAXSELECTS (4) - -/** @brief User context conversion macro - * Macro used to extract the user defined data pointer from a SPI slave - * handle context.
- * To get a user context, simple use the macro on the drivers handle: - * void *pUserData = (void *) ROM_SPIS_HANDLE_TOUDATA(driverHandle); - */ -#define ROM_SPIS_HANDLE_TOUDATA(p) (void *) (*(uint32_t *) p) - -/** @brief SPI slave optional transfer flags */ -#define ROM_SPIS_FLAG_DMATX (1UL << 30) /*!< DMA will be used for TX, requires DMA setup outside of the driver */ -#define ROM_SPIS_FLAG_DMARX (1UL << 29) /*!< DMA will be used for RX, requires DMA setup outside of the driver */ -#define ROM_SPIS_FLAG_TXIGNORE (1UL << 27) /*!< Ignores transmit data regardless of txBuff, transmit data callback will not be called, stops when txSz = 0 */ -#define ROM_SPIS_FLAG_RXIGNORE (1UL << 26) /*!< Ignores receive data regardless of rxBuff/rxSz, receive data callback will not be called */ -#define ROM_SPIS_FLAG_USERBITS (0xFFFF) /*!< Application can safely use the flag bits designated by this mask */ - -/** @brief SPI transfer configuration structure - once of these needs to be setup for - * each SPI select (SSEL) used on the slave. If only SSEL0 is used, it only needs to be setup - * for that one slave select. */ -typedef PRE_PACK struct POST_PACK { - uint8_t mode; /*!< Mode selection for this transfer (ROM_SPI_CLOCK_MODE_T) */ - uint8_t lsbFirst; /*!< 0 for msb sent/recv first, !0 = for lsb send/recv first */ - uint8_t dataBits; /*!< Data transfer size in bits, between 1 and 16, txBuff and rxBuff must be 16-bit aligned if >8 */ - uint8_t reserved; -} ROM_SPIS_SLAVE_T; - -/** @brief SPI slave transfer descriptor */ -typedef PRE_PACK struct POST_PACK { - const void *txBuff; /*!< Pointer to array of datum to be transmitted, must be 16-bit aligned if datum bits >8 */ - uint32_t txSz; /*!< Size of the transmit buffer (txBuff) in items (not bytes) before transmit callback is called */ - uint32_t txSent; /*!< Number of items (not bytes) sent between SSEL assertion and deassertion */ - void *rxBuff; /*!< Pointer memory where datum received from SPI be stored, must be 16-bit aligned if datum bits >8 */ - uint32_t rxSz; /*!< Size of the receive buffer (rxBuff) in items (not bytes) before receive callback is called */ - uint32_t rxRecv; /*!< Number of items (not bytes) received between SSEL assertion and deassertion */ - uint32_t flags; /*!< Optional transfer flags, may be modified by driver */ - volatile ErrorCode_t status; /*!< Status of the current SPI transfer (ErrorCode_t), must be 32-bits */ -} ROM_SPIS_XFER_T; - -/** @brief SPI slave callback IDs */ -typedef enum { - ROM_SPIS_ASSERTSSEL_CB = 0, /*!< Callback ID for SPI slave select (SSEL) assertion */ - ROM_SPIS_DATATRANSMIT_CB, /*!< Callback ID for SPI slave transmit start */ - ROM_SPIS_DATATRECEIVE_CB, /*!< Callback ID for SPI slave receive start */ - ROM_SPIS_DEASSERTSSEL_CB /*!< Callback ID for SPI slave select (SSEL) de-assertion (completion callback) */ -} ROM_SPIS_CALLBACK_T; - -/** @brief SPI slave select assert callback - * This callback is called from the SPI slave handler when the SPI slave - * selects the slave (asserts SSEL). The callback is only called if it has been registered. - */ -typedef void (*spisSlaveXferCSAssertCB)(ROM_SPIS_HANDLE_T spisHandle, uint8_t slaveNum); - -/** @brief SPI slave data receive start callback - * The SPI slave state machine will call this optional function when it needs a buffer to - * receive data. The callback can be used to setup DMA or alter the receive buffer size. The - * callback is only called if it has been registered, the buffer has been fully used, and - * data is pending is the receive FIFO. When using DMA, this callback must be enabled and - * used for DMA setup. - */ -typedef void (*spisSlaveReceiveCB)(ROM_SPIS_HANDLE_T spisHandle, ROM_SPIS_XFER_T *pXfer); - -/** @brief SPI slave data transmit start callback - * The SPI slave state machine will call this optional function prior to data transfer. - * The callback can be used to setup DMA or alter the receive buffer size. The callback - * is only called if it has been registered, the buffer has been fully used, and data is - * needed to populate the transmit FIFO. When using DMA, this callback must be enabled and - * used for DMA setup. - */ -typedef void (*spisSlaveTransmitCB)(ROM_SPIS_HANDLE_T spisHandle, ROM_SPIS_XFER_T *pXfer); - -/** @brief SPI slave transfer select deassert data callback - * This callback is called from the SPI slave handler when the SPI slave - * deasserts the slave select. The callback is only called if it has been registered. - */ -typedef void (*spisSlaveXferCSDeAssertCB)(ROM_SPIS_HANDLE_T spisHandle, ROM_SPIS_XFER_T *pXfer); - -/** @brief SPI slave initialization structure */ -typedef PRE_PACK struct POST_PACK { - void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */ - uint32_t base; /*!< Base address of SPI peripheral to use */ - uint8_t spiPol[4]; /*!< SPI SSEL pollarity for each slave select, 0 = active low, !0 = active high */ -} ROM_SPIS_INIT_T; - -/** @brief SPI slave ROM indirect function structure */ -typedef PRE_PACK struct POST_PACK { - uint32_t (*GetMemSize)(void); /*!< Returns needed memory size required for run-time context of SPI slave driver */ - ROM_SPIS_HANDLE_T (*Init)(void *mem, const ROM_SPIS_INIT_T *pInit); /*!< Initializes the SPI slave driver and peripheral */ - void (*RegisterCallback)(ROM_SPIS_HANDLE_T pHandle, uint32_t cbIndex, void *pCB); /*!< Registers an SPI slave callback */ - ErrorCode_t (*SetupSlave)(ROM_SPIS_HANDLE_T pHandle, ROM_SPIS_SLAVE_T *pSlaveSetup); /*!< Setup SPI slave transfer configuration */ - ErrorCode_t (*Transfer)(ROM_SPIS_HANDLE_T pHandle, ROM_SPIS_XFER_T *pXfer); /*!< Prepare a SPI slave transfer */ - void (*TransferHandler)(ROM_SPIS_HANDLE_T pHandle); /*!< SPI slave transfer (interrupt) handler */ - uint32_t (*GetDriverVersion)(void); -} ROM_SPISD_API_T; - -/** - * @} - */ - -extern const ROM_SPISD_API_T spis_api; // so application program can access pointer to -// function table - -#endif /* __HW_SPISD_ROM_API_H */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_uart.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_uart.c deleted file mode 100644 index b9bf27c518f..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_uart.c +++ /dev/null @@ -1,669 +0,0 @@ -/* - * @brief UART ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "error.h" -#include "hw_uart_rom_api.h" - -#define UART_IDLE_FIX /* Remove once IDLE problem is fixed */ - -/* UART Driver internal data structure */ -typedef struct { - void *pUserData; /* Pointer to user data */ - UART_REGS_T *pREGS; /* Pointer to Registers */ - UART_DATA_T xfer[2]; /* TX/RX transfer data */ -#ifdef UART_IDLE_FIX - uint32_t dly; /* Delay to count 1 bit time; REMOVE: when H/W is fixed */ -#endif - void(*cbTable[UART_CB_RESERVED]) (UART_HANDLE_T, UART_EVENT_T, void *); /* Call-back index table */ -} UART_DRIVER_T; - -/* PRIVATE: Division logic to divide without integer overflow */ -static uint32_t _UART_DivClk(uint32_t pclk, uint32_t m) -{ - uint32_t q, r, u = pclk >> 24, l = pclk << 8; - m = m + 256; - q = (1 << 24) / m; - r = (1 << 24) - (q * m); - return ((q * u) << 8) + (((r * u) << 8) + l) / m; -} - -/* PRIVATE: Get highest Over sampling value */ -static uint32_t _UART_GetHighDiv(uint32_t val, uint8_t strict) -{ - int32_t i, max = strict ? 16 : 5; - for (i = 16; i >= max; i--) - { - if (!(val % i)) - { - return i; - } - } - return 0; -} - -/* PRIVATE: Queue a transfer in UART */ -static ErrorCode_t _UART_Xfer(UART_DRIVER_T *pUART, void *buff, uint16_t len, uint8_t op) -{ - UART_DATA_T *xfr = &pUART->xfer[op]; - - /* Xfer of 0 bytes in a UART should always be successful */ - if (!len) - { - return LPC_OK; - } - - /* Check if a Xfer is alredy in progress */ - if (xfr->count > xfr->offset) - { - return ERR_BUSY; - } - - xfr->buf = (void *) buff; - xfr->count = len; - xfr->offset = 0; - xfr->state = UART_ST_BUSY; - if (!op) - { - pUART->pREGS->INTENSET = UART_INT_TXRDY; - } - else { - pUART->pREGS->INTENSET = UART_INT_RXRDY | UART_INT_FRMERR | UART_INT_RXNOISE | UART_INT_START | UART_INT_OVR; - } - - return LPC_OK; -} - -/* Calculate error difference */ -static int32_t _CalcErr(uint32_t n, uint32_t d, uint32_t *prev) -{ - uint32_t err = n - (n / d) * d; - uint32_t herr = ((n / d) + 1) * d - n; - if (herr < err) - { - err = herr; - } - - if (*prev <= err) - { - return 0; - } - *prev = err; - return (herr == err) + 1; -} - -/* Calculate the base DIV value */ -static ErrorCode_t _UART_CalcDiv(UART_BAUD_T *ub) -{ - int32_t i = 0; - uint32_t perr = ~0UL; - - if (!ub->div) - { - i = ub->ovr ? ub->ovr : 16; - } - - for (; i > 4; i--) - { - int32_t tmp = _CalcErr(ub->clk, ub->baud * i, &perr); - - /* Continue when no improvement seen in err value */ - if (!tmp) - { - continue; - } - - ub->div = tmp - 1; - if (ub->ovr == i) - { - break; - } - ub->ovr = i; - } - - if (!ub->ovr) - { - return ERR_UART_BAUDRATE; - } - - ub->div += ub->clk / (ub->baud * ub->ovr); - if (!ub->div) - { - return ERR_UART_BAUDRATE; - } - - ub->baud = ub->clk / (ub->div * ub->ovr); - return LPC_OK; -} - -/* Calculate the best MUL value */ -static void _UART_CalcMul(UART_BAUD_T *ub) -{ - uint32_t m, perr = ~0UL, pclk = ub->clk, ovr = ub->ovr; - - /* If clock is UART's base clock calculate only the divider */ - for (m = 0; m < 256; m++) - { - uint32_t ov = ovr, x, v, tmp; - - /* Get clock and calculate error */ - x = _UART_DivClk(pclk, m); - tmp = _CalcErr(x, ub->baud, &perr); - v = (x / ub->baud) + tmp - 1; - - /* Update if new error is better than previous best */ - if (!tmp || (ovr && (v % ovr)) || - (!ovr && ((ov = _UART_GetHighDiv(v, ovr)) == 0))) - { - continue; - } - - ub->ovr = ov; - ub->mul = m; - ub->clk = x; - ub->div = tmp - 1; - } -} - -/* PRIVATE: Invoke UART Call back functions */ -static void _UART_InvokeCB(UART_DRIVER_T *pUART, UART_EVENT_T event, void *arg) -{ - void (*cbfn)(UART_HANDLE_T, UART_EVENT_T, void *); - cbfn = pUART->cbTable[(uint32_t) event >> 1]; - if (cbfn != NULL) - { - cbfn((UART_HANDLE_T) pUART, event, arg); - } -} - -/* PRIVATE: Handler for data transfers */ -static void _UART_HandleTxRx(UART_HANDLE_T hUART, UART_EVENT_T event, void *arg) -{ - UART_DATA_T *dat = (UART_DATA_T *) arg; - UART_DRIVER_T *pUART = (UART_DRIVER_T *) hUART; - uint16_t *buf16 = dat->buf; - uint8_t *buf8 = dat->buf; - - /* Transmit data */ - if (event == UART_TX_DATA) - { - while (dat->count && (pUART->pREGS->INTSTAT & UART_INT_TXRDY)) - { - if (dat->dwidth) - { - pUART->pREGS->TXDAT = *buf16++; - } - else { - pUART->pREGS->TXDAT = *buf8++; - } - dat->count--; - } - return; - } - - /* Receive data */ - while (dat->count && (pUART->pREGS->INTSTAT & UART_INT_RXRDY)) - { - if (dat->dwidth) - { - *buf16++ = pUART->pREGS->RXDAT & 0x1FF; - } - else { - *buf8++ = pUART->pREGS->RXDAT & 0xFF; - } - dat->count--; - } -} - -/* Handle UART Receive event */ -static int32_t _UART_HandleXfer(UART_DRIVER_T *pUART, uint8_t op) -{ - UART_DATA_T dat; - UART_DATA_T *xfr = &pUART->xfer[op]; - - /* See if the transfer is already complete */ - if (xfr->offset >= xfr->count) - { - return 2; - } - - /* Fill the buffer data structure */ - dat.count = xfr->count - xfr->offset; - dat.dwidth = ((pUART->pREGS->CFG >> 2) & 3) > 1; - if (dat.dwidth) - { - dat.buf = &((uint16_t *) xfr->buf)[xfr->offset]; - } - else { - dat.buf = &((uint8_t *) xfr->buf)[xfr->offset]; - } - - if (!xfr->offset && xfr->count) - { - _UART_InvokeCB(pUART, UART_TX_START, xfr); - } - - pUART->cbTable[UART_CB_DATA]((UART_HANDLE_T) pUART, (UART_EVENT_T) (UART_TX_DATA + op), &dat); - xfr->offset = (xfr->count - dat.count); - - if (xfr->offset >= xfr->count) - { - if (!op) - { - pUART->pREGS->INTENCLR = UART_INT_TXRDY; - } - else { - pUART->pREGS->INTENCLR = UART_INT_RXRDY; - } - - _UART_InvokeCB(pUART, (UART_EVENT_T) (UART_TX_DONE + op), xfr); - if (xfr->state == UART_ST_BUSY) - { - xfr->state = UART_ST_DONE; - } - return 1; - } - return 0; -} - -/* STOP Receive under progress */ -static void _UART_StopRx(UART_HANDLE_T hUART) -{ - UART_DRIVER_T *pUART = (UART_DRIVER_T *) hUART; - UART_DATA_T *rx = &pUART->xfer[1]; - volatile uint16_t *idx = (volatile uint16_t *) &rx->offset; - - if (*idx >= rx->count) - { - return; - } - - /* Disable further receive interrupts */ - pUART->pREGS->INTENCLR = UART_INT_RXRDY; - rx->count = *idx; - _UART_InvokeCB(pUART, UART_RX_DONE, rx); -} - -/* EXPROTED API: Returns memory required for UART ROM driver */ -uint32_t UART_GetMemSize(void) -{ - return sizeof(UART_DRIVER_T); -} - -/* EXPORTED API: Calculate UART Baudrate divisors */ -ErrorCode_t UART_CalculateBaud(UART_BAUD_T *ub) -{ - if (!ub->mul) - { - _UART_CalcMul(ub); - } - - return _UART_CalcDiv(ub); -} - -/* EXPORTED API: UART Initialization function */ -UART_HANDLE_T UART_Init(void *mem, uint32_t base_addr, void *args) -{ - UART_DRIVER_T *pUART; - - /* Check if the memory is word aligned */ - if ((uint32_t) mem & 0x3) - { - return NULL; - } - - /* Assign memory provided by application */ - pUART = (UART_DRIVER_T *) mem; - memset(pUART, 0, sizeof(UART_DRIVER_T)); - - /* Assign the base address */ - pUART->pREGS = (UART_REGS_T *) base_addr; - pUART->pUserData = args; - - /* Set default handler for TX and RX */ - pUART->cbTable[UART_CB_DATA] = _UART_HandleTxRx; - return (UART_HANDLE_T) pUART; -} - -/* EXPORTED API: Configure UART parameters */ -ErrorCode_t UART_Configure(UART_HANDLE_T hUART, const UART_CFG_T *cfg) -{ - UART_DRIVER_T *pUART = (UART_DRIVER_T *) hUART; - UART_REGS_T *pREGS = pUART->pREGS; - - if (((cfg->cfg & UART_PAR_MASK) == (1 << 4)) || - ( (cfg->cfg & UART_DATA_MASK) == (3 << 2)) ) - { - return ERR_UART_PARAM; - } - - /* Enable parity error when parity is enabled */ - if ((cfg->cfg & UART_PAR_MASK) >> 4) - { - pREGS->INTENSET = UART_INT_PARERR; - } - - if (((int32_t) cfg->div <= 0) || ((int32_t) cfg->ovr <= 0)) - { - return ERR_UART_PARAM; - } - - pREGS->OSR = (cfg->ovr - 1) & 0x0F; - pREGS->BRG = (cfg->div - 1) & 0xFFFF; - pREGS->CFG = UART_CFG_ENABLE | (cfg->cfg & ~UART_CFG_RES); - - /* Enabled RX of BREAK event */ - if (cfg->cfg & UART_CFG_BRKRX) - { - pREGS->INTENSET = UART_INT_BREAK; - } - - /* Enable CTS interrupt if requested */ - if (cfg->cfg & UART_CFG_CTSEV) - { - pREGS->INTENSET = UART_INT_CTS; - } - -#ifdef UART_IDLE_FIX - /* REMOVE: if/else block after H/W idle is fixed */ - if (cfg->res > 224) - { - pUART->dly = 3072 * (cfg->res - 224); - } - else { - pUART->dly = cfg->res << 2; - } -#endif - - return LPC_OK; -} - -/* EXPORTED API: UART setup special operation like BREAK etc. */ -void UART_SetControl(UART_HANDLE_T hUART, uint32_t cfg) -{ - uint32_t en, dis; - UART_REGS_T *pREGS = ((UART_DRIVER_T *) hUART)->pREGS; - - /* Get list of enabled and disabled options */ - en = ((cfg >> 16) & (cfg & 0xFFFF)) << 1; - dis = ((cfg >> 16) & ~(cfg & 0xFFFF)) << 1; - - /* See if it is RX Stop request */ - if (cfg & UART_RX_STOP) - { - _UART_StopRx(hUART); - } - - /* See if any IDLEs are enabled */ - if (cfg & (UART_IDLE_MASK << 16)) - { - pREGS->INTENSET = (en >> 1) & UART_IDLE_MASK; - pREGS->INTENCLR = (dis >> 1) & UART_IDLE_MASK; - } - - /* See if it is a request BREAK after TX */ - if (en & UART_CTL_TXDIS) - { - if (en & UART_CTL_TXBRKEN) - { - pREGS->CTL = (pREGS->CTL & ~UART_CTL_RES) | UART_CTL_TXDIS; - while (!(pREGS->STAT & UART_INT_TXDIS)) - {} -#ifdef UART_IDLE_FIX - if (1) - { - volatile uint32_t dly = ((UART_DRIVER_T *) hUART)->dly; - while (dly--) - {}/* Provide some idling time H/W does not do this */ - } -#endif - } - else { - pREGS->INTENSET = UART_INT_TXDIS; - } - } - - /* See if we are releasing break and resume TX operation */ - if ((dis & UART_CTL_TXDIS) && (dis & UART_CTL_TXBRKEN)) - { - pREGS->CTL = pREGS->CTL & ~(UART_CTL_RES | UART_CTL_TXBRKEN); -#ifdef UART_IDLE_FIX - if (1) - { - volatile uint32_t dly = ((UART_DRIVER_T *) hUART)->dly; - while (dly--) - {} /* Provide some idling time H/W does not do this */ - } -#endif - } - - /* Check for autobaud and enable autobaud err interrupt */ - if (en & UART_CTL_AUTOBAUD) - { - pREGS->INTENSET = UART_INT_ABAUDERR; - } - - pREGS->CTL = ((pREGS->CTL | en) & ~dis) & ~UART_CTL_RES; -} - -/* EXPORTED API: Register a call-back function */ -ErrorCode_t UART_RegisterCB(UART_HANDLE_T hUART, - UART_CBINDEX_T idx, - void (*cb_func)(UART_HANDLE_T, UART_EVENT_T, void *)) -{ - if (idx < UART_CB_RESERVED) - { - ((UART_DRIVER_T *) hUART)->cbTable[idx] = cb_func; - } - else { - return ERR_UART_PARAM; - } - - /* Restore internal data handlers when external ones are un-registered */ - if ((idx == UART_CB_DATA) && (cb_func == NULL)) - { - ((UART_DRIVER_T *) hUART)->cbTable[idx] = _UART_HandleTxRx; - } - - return LPC_OK; -} - -/* EXPORTED API: UART Event handler */ -void UART_Handler(UART_HANDLE_T hUART) -{ - UART_DRIVER_T *pUART = (UART_DRIVER_T *) hUART; - uint32_t flags = pUART->pREGS->INTENSET & pUART->pREGS->INTSTAT; - - if (flags & UART_INT_TXRDY) - { - _UART_HandleXfer(pUART, 0); - } - - if (flags & UART_INT_FRMERR) - { - pUART->pREGS->STAT = UART_INT_FRMERR; - if (pUART->xfer[1].state == UART_ST_BUSY) - { - pUART->xfer[1].state = UART_ST_ERRFRM; - } - _UART_InvokeCB(pUART, UART_EV_ERROR, (void *) UART_ERROR_FRAME); - } - - if (flags & UART_INT_PARERR) - { - pUART->pREGS->STAT = UART_INT_PARERR; - if (pUART->xfer[1].state == UART_ST_BUSY) - { - pUART->xfer[1].state = UART_ST_ERRPAR; - } - _UART_InvokeCB(pUART, UART_EV_ERROR, (void *) UART_ERROR_PARITY); - } - - if (flags & UART_INT_ABAUDERR) - { - pUART->pREGS->STAT = UART_INT_ABAUDERR; - if (pUART->xfer[1].state == UART_ST_BUSY) - { - pUART->xfer[1].state = UART_ST_ERR; - } - _UART_InvokeCB(pUART, UART_EV_ERROR, (void *) UART_ERROR_AUTOBAUD); - } - - if (flags & UART_INT_RXNOISE) - { - pUART->pREGS->STAT = UART_INT_RXNOISE; - if (pUART->xfer[1].state == UART_ST_BUSY) - { - pUART->xfer[1].state = UART_ST_ERRNOISE; - } - _UART_InvokeCB(pUART, UART_EV_ERROR, (void *) UART_ERROR_RXNOISE); - } - - if (flags & UART_INT_OVR) - { - pUART->pREGS->STAT = UART_INT_OVR; - if (pUART->xfer[1].state == UART_ST_BUSY) - { - pUART->xfer[1].state = UART_ST_ERROVR; - } - _UART_InvokeCB(pUART, UART_EV_ERROR, (void *) UART_ERROR_OVERRUN); - } - - if (flags & UART_INT_RXRDY) - { - _UART_HandleXfer(pUART, 1); -#ifdef UART_IDLE_FIX - if (1) - { - volatile uint32_t dly = ((UART_DRIVER_T *) hUART)->dly; - while ((pUART->pREGS->STAT & UART_STAT_RXIDLE) && dly--) - {} - } -#else - while (pUART->pREGS->STAT & UART_STAT_RXIDLE) - {} -#endif - _UART_InvokeCB(pUART, (UART_EVENT_T) (UART_RX_INPROG + ((pUART->pREGS->STAT >> 1) & 1)), &pUART->xfer[1]); - } - - if (flags & UART_INT_TXIDLE) - { - _UART_InvokeCB(pUART, UART_EV_EVENT, (void *) UART_EVENT_TXIDLE); - } - - if (flags & UART_INT_TXDIS) - { - pUART->pREGS->INTENCLR = UART_INT_TXDIS;/* Disable interrupt */ - _UART_InvokeCB(pUART, UART_EV_EVENT, (void *) UART_EVENT_TXPAUSED); - } - - if (flags & UART_INT_CTS) - { - pUART->pREGS->STAT = UART_INT_CTS; - _UART_InvokeCB(pUART, UART_EV_EVENT, - (void *) ((pUART->pREGS->STAT & UART_STAT_CTS) ? UART_EVENT_CTSHI : UART_EVENT_CTSLO)); - } - - if (flags & UART_INT_BREAK) - { - pUART->pREGS->STAT = UART_INT_BREAK | UART_INT_FRMERR; - _UART_InvokeCB(pUART, UART_EV_EVENT, - (void *) ((pUART->pREGS->STAT & UART_STAT_BREAK) ? UART_EVENT_BREAK : UART_EVENT_NOBREAK)); - } - - if (flags & UART_INT_START) - { - pUART->pREGS->STAT = UART_INT_START; - _UART_InvokeCB(pUART, UART_RX_START, &pUART->xfer[1]); - } - -} - -/* EXPORTED API: UART Transmit API */ -ErrorCode_t UART_Tx(UART_HANDLE_T hUART, const void *buff, uint16_t len) -{ - return _UART_Xfer((UART_DRIVER_T *) hUART, (void *) buff, len, 0); -} - -/* EXPORTED API: UART Receive API */ -ErrorCode_t UART_Rx(UART_HANDLE_T hUART, void *buff, uint16_t len) -{ - return _UART_Xfer((UART_DRIVER_T *) hUART, buff, len, 1); -} - -/* EXPORTED API: Flush the TX buffer */ -void UART_WaitTX(UART_HANDLE_T hUART) -{ - while (!_UART_HandleXfer(hUART, 0)) - {} -} - -/* EXPORTED API: Fetch the data from UART into RX buffer */ -void UART_WaitRX(UART_HANDLE_T hUART) -{ - UART_REGS_T *pREGS = ((UART_DRIVER_T *) hUART)->pREGS; - /* See if the data needs to be discarded */ - if (_UART_HandleXfer(hUART, 1) == 2) - { - volatile uint32_t dummy; - while ((pREGS->STAT & UART_INT_RXRDY) || !(pREGS->STAT & UART_STAT_RXIDLE)) - { - dummy = pREGS->RXDAT; - (void)dummy; - } - } - while (!_UART_HandleXfer(hUART, 1)) - {} -} - -/* EXPORTED API: Function to Get the firmware Version */ -uint32_t UART_GetDriverVersion(void) -{ - return UART_DRIVER_VERSION; -} - -/** - * @brief Table of the addresses of all the UART ROM APIs - * @note This table of function pointers is the API interface. - */ -const ROM_UART_API_T uartrom_api = { - UART_GetMemSize, - UART_CalculateBaud, - UART_Init, - UART_Configure, - UART_SetControl, - UART_RegisterCB, - UART_Handler, - UART_Tx, - UART_Rx, - UART_WaitTX, - UART_WaitRX, - UART_GetDriverVersion, -}; diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_uart.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_uart.h deleted file mode 100644 index 18befb6c851..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_uart.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * @brief UART ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef _HW_UART_H -#define _HW_UART_H - -#define UART_DRIVER_VERSION 0x0100 - -/******************* - * INCLUDE FILES * - ********************/ -#include - -/* UART Status Register bits */ -#define UART_RXRDY (1 << 0) /* Receive data ready */ -#define UART_RXIDLE (1 << 1) /* Receiver Idle */ -#define UART_TXRDY (1 << 2) /* Transmitter ready */ -#define UART_TXIDLE (1 << 3) /* Transmitter Idle */ -#define UART_RXDERR (0xF100) /* overrun err, frame err, parity err, RxNoise err */ -#define UART_TXDERR (0x0200) /* underrun err */ -#define UART_START (0x1000) - -/* UART Interrupt register bits */ -#define UART_INT_RXRDY (1 << 0) -#define UART_INT_TXRDY (1 << 2) -#define UART_INT_TXIDLE (1 << 3) -#define UART_INT_CTS (1 << 5) -#define UART_INT_TXDIS (1 << 6) -#define UART_INT_OVR (1 << 8) -#define UART_INT_BREAK (1 << 11) -#define UART_INT_START (1 << 12) -#define UART_INT_FRMERR (1 << 13) -#define UART_INT_PARERR (1 << 14) -#define UART_INT_RXNOISE (1 << 15) -#define UART_INT_ABAUDERR (1 << 16) - -/* Configuration register bits */ -#define UARTEN 1 - -#define UART_CTL_TXDIS (1UL << 6) -#define UART_CTL_TXBRKEN (1UL << 1) -#define UART_CTL_AUTOBAUD (1UL << 16) -#define UART_CFG_RES (2UL | (1UL << 10) | (1UL << 13) | (1UL << 17) | (0xFFUL << 24)) -#define UART_CFG_ENABLE 1 -#define UART_PAR_MASK (3 << 4) -#define UART_DATA_MASK (3 << 2) -#define UART_CTL_RES (1UL | (7UL << 3) | (1UL << 7) | (0x3FUL << 10) | (0x7FFFUL << 17)) -#define UART_IDLE_MASK (1 << 3) -#define UART_STAT_CTS (1 << 4) -#define UART_STAT_BREAK (1 << 10) -#define UART_STAT_RXIDLE (1 << 1) - -/******************* - * EXPORTED MACROS * - ********************/ -#define ECHO_EN 1 -#define ECHO_DIS 0 - -/********************* - * EXPORTED TYPEDEFS * - **********************/ - -typedef struct { /* UART registers Structure */ - volatile uint32_t CFG; /*!< Offset: 0x000 Configuration register */ - volatile uint32_t CTL; /*!< Offset: 0x004 Control register */ - volatile uint32_t STAT; /*!< Offset: 0x008 Status register */ - volatile uint32_t INTENSET; /*!< Offset: 0x00C Interrupt Enable Read and Set register */ - volatile uint32_t INTENCLR; /*!< Offset: 0x010 Interrupt Enable Clear register */ - const volatile uint32_t RXDAT; /*!< Offset: 0x014 Receiver Data register */ - const volatile uint32_t RXDATSTAT; /*!< Offset: 0x018 Rx Data with status */ - volatile uint32_t TXDAT; /*!< Offset: 0x01C Transmitter Data Register */ - volatile uint32_t BRG; /*!< Offset: 0x020 Baud Rate Generator register */ - const volatile uint32_t INTSTAT; /*!< Offset: 0x024 Interrupt Status register */ - volatile uint32_t OSR; /*!< Offset: 0x028 Oversampling register */ - volatile uint32_t ADR; /*!< Offset: 0x02C Address register (for automatic address matching) */ -} UART_REGS_T; -typedef UART_REGS_T LPC_USART_T; - -#endif /* _HW_UART_H */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_uart_rom_api.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_uart_rom_api.h deleted file mode 100644 index 06b1398d4e0..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_uart_rom_api.h +++ /dev/null @@ -1,284 +0,0 @@ -/* - * @brief UART ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __HW_UART_ROM_API_H -#define __HW_UART_ROM_API_H - -#include -#include -#include "error.h" -#include "packing.h" -#include "hw_uart.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup ROMAPI_UART UART/USART ROM driver functions and definitions - * @ingroup ROMAPI_UART_WRAPPER - * @{ - */ - -/** @brief UART Handler type */ -typedef void *UART_HANDLE_T; - -/** @brief UART Data transfer status */ -typedef enum { - UART_ST_DONE, /*!< Transfer completed */ - UART_ST_BUSY, /*!< Transfer is in progress */ - UART_ST_ERR, /*!< Generic error */ - UART_ST_ERRPAR, /*!< ERROR: PARITY */ - UART_ST_ERRFRM, /*!< ERROR: Frame */ - UART_ST_ERRNOISE, /*!< ERROR: Receiver noise */ - UART_ST_ERROVR, /*!< ERROR: Overflow */ -} UART_STATE_T; - -/** @brief UART Transfer structure */ -typedef PRE_PACK struct POST_PACK { - void *buf; /*!< Pointer to buffer */ - uint16_t count; /*!< Number of items to be sent/received [Not number of bytes] */ - uint8_t dwidth; /*!< Width of data items in @a buf; 0 - 8:Bits; 1 - 16:Bits */ -#ifdef UARTROMV2_PRESENT - uint8_t state; /*!< UART TX/RX eror status see #UART_STATE_T */ - uint16_t offset; /*!< Offset of the buffer at which data is being currently processed; usually not used by application */ -#else - volatile uint8_t state; /*!< UART TX/RX eror status see #UART_STATE_T */ - volatile uint16_t offset; /*!< Offset of the buffer at which data is being currently processed; usually not used by application */ -#endif - uint16_t reserved; /*!< Reserved for alignment */ -} UART_DATA_T; - -/** - * @brief UART Baud rate calculation structure - * @note - * Use oversampling (@a ovr) value other than 16, only if the difference - * between the actual baud and desired baud has an unacceptable error percentage. - * Smaller @a ovr values can cause the sampling position within the data-bit - * less accurate an may potentially cause more noise errors or incorrect data - * set ovr to < 10 only when there is no other higher values suitable. - */ -typedef PRE_PACK struct POST_PACK { - uint32_t clk; /*!< IN: Base clock to fractional divider; OUT: "Base clock rate for UART" */ - uint32_t baud; /*!< IN: Required baud rate; OUT: Actual baud rate */ - uint8_t ovr; /*!< IN: Number of desired over samples [0-auto detect or values 5 to 16]; OUT: Auto detected over samples [unchanged if IN is not 0] */ - uint8_t mul; /*!< IN: 0 - calculate MUL, 1 - do't calculate (@a clk) has UART base clock; OUT: MUL value to be set in FRG register */ - uint16_t div; /*!< OUT: Integer divider to divide the "Base clock rate for UART" */ -} UART_BAUD_T; - -/** @brief UART Callback function index - * - * These values must be passed by the application, when they register their - * callbacks with the ROM driver - */ -typedef enum { - UART_CB_START, /*!< UART Callback for TX/RX START event; will have @a event argument set to #UART_TX_START - for TX start event and #UART_RX_START for RX start event */ - UART_CB_DONE, /*!< UART Callback for TX/RX Complete event; will have @a event argument set to #UART_TX_DONE - for TX Done event and #UART_RX_DONE for RX done event*/ - UART_CB_DATA, /*!< UART Callback sending TX data or receiving RX Data; will have @a event argument set - to #UART_TX_DATA for TX data and #UART_RX_DATA for RX data*/ - UART_CB_RXPROG, /*!< UART Callback for every received character (progress); will have @a event argument set - to #UART_RX_INPROG if a character is received and more characters are arriving, - else it will be set to #UART_RX_NOPROG when character is received and no more characters - are found within one character time frame*/ - UART_CB_ERREVT, /*!< UART Callback for any Errors/Events; @a event argument will be #UART_EV_ERROR if the - callback is for error event, or it will be #UART_EV_EVENT if it is nor normal events like - BREAK, TXPAUSE etc., */ - UART_CB_RESERVED/*!< Reserved; Should not be used */ -} UART_CBINDEX_T; - -/** @brief UART Event enumerations - * - * These values are passed by the driver as the second argument - * of the callback functions that are invoked by the ROM driver - */ -typedef enum { - UART_TX_START, /*!< UART TX Start event; @a arg will be a pointer to #UART_DATA_T that has information related to TX buffer */ - UART_RX_START, /*!< UART RX Start event; @a arg will be a pointer to #UART_DATA_T that has information related to RX buffer - this event does not mean a start of RX into the given buffer, instead it means receiver has started receiving - new character after being idle for one character frame time */ - UART_TX_DONE, /*!< UART TX Complete event; @a arg will be a pointer to #UART_DATA_T that has information related to TX Buffer */ - UART_RX_DONE, /*!< UART RX Complete event; @a arg will be a pointer to #UART_DATA_T that has information related to RX Buffer */ - UART_TX_DATA, /*!< UART Push TX data; @a arg will be pointer to #UART_DATA_T; @a buf will contain the pointer to the data - to be sent, @a sz will have the number of items to be sent and @a b16 will be set to 1 if the data to be - transmitted is of 16-bits wide (else @a b16 will be 0); after pushing the data from buf the callback should - set the @a sz to number of bytes remaining to be sent */ - UART_RX_DATA, /*!< UART Pop RX data; @a arg will be pointer to #UART_DATA_T; @a buf will contain the pointer to memory where - receive data be stored, @a sz will have the number of items to be received and @a b16 will be set to 1 if the - data to be received is of 16-bits wide [Bits 9 to 15 must be 0] (else @a b16 will be 0); after reading the data - into buf the callback should set the @a sz to number of bytes yet to be received */ - UART_RX_INPROG, /*!< Received a UART character and more characters are being processed by shift register */ - UART_RX_NOPROG, /*!< Received a UART character and no more characters are received within one character time */ - UART_EV_ERROR, /*!< UART Error; @a arg parameter will be one of the UART_ERROR_XXX (Example #UART_ERROR_FRAME) */ - UART_EV_EVENT /*!< UART special events; @a arg parameter will be one of the UART_EVENT_XXX (Example #UART_EVENT_BREAK) */ -} UART_EVENT_T; - -/** @brief UART Configuration bits - * - * These bits can be OR'd to get the configuration value (second parameter) for aConfigure API - */ -#undef UART_CFG_MODE32K -#undef UART_CFG_LINMODE -#define UART_CFG_7BIT 0 /*!< UART uses 7-Bit data transfer; Buffer used by Send and Receive API must be of type uint8_t * */ -#define UART_CFG_8BIT (1 << 2) /*!< UART uses 8-Bit data transfer; Buffer used by Send and Receive API must be of type uint8_t * */ -#define UART_CFG_9BIT (1 << 3) /*!< UART uses 9-Bit data transfer; Buffer used by Send and Receive API must be of type uint16_t * */ -#define UART_CFG_NOPAR 0 /*!< UART Transfers do not use parity */ -#define UART_CFG_EVENPAR (2 << 5) /*!< Enable EVEN Parity */ -#define UART_CFG_ODDPAR (3 << 4) /*!< Enable ODD Parity */ -#define UART_CFG_1STOP 0 /*!< UART Tx/Rx will use 1-stop bit at the end of transfer */ -#define UART_CFG_2STOP (1 << 6) /*!< UART Tx/Rx will use 2-Stop bits towards end of transfers */ -#define UART_CFG_MODE32K (1 << 7) /*!< Use 32KHz RTC clock; Needs special clocking setup to be done by the application */ -#define UART_CFG_LINMODE (1 << 8) /*!< Break detect and generation will use LIN bus operation */ -#define UART_CFG_HWFLOW (1 << 9) /*!< Enable Hardware flow control */ -#define UART_CFG_CTSEV (1 << 10) /*!< Enable CTS events */ -#define UART_CFG_BRKRX (1 << 13) /*!< Enable BREAK receive events */ - -/* USART Synchorous mode configurations */ -#define UART_CFG_SYNMODE (1 << 11)/*!< Synchronous Mode: Enable Synchronous mode */ -#define UART_CFG_FALLING 0 /*!< Synchronous Mode: Sample data during falling edge of SCLK (Must be used with #UART_CFG_SYNMODE) */ -#define UART_CFG_RISING (1 << 12)/*!< Synchronous mode: Sample data during rising edge of SCLK (Must be used with #UART_CFG_SYNMODE) */ -#define UART_CFG_MASTER (1 << 14)/*!< Synchronous mode: USART will be the master (Must be used with #UART_CFG_SYNMODE) */ - -/* UART Modes */ -#define UART_CFG_LOOPBACK (1 << 15)/*!< UART will operate in diagnostic loopback mode */ -#define UART_CFG_IRDAMODE (1 << 16)/*!< UART will operate in IrDA mode */ - -/* RS-485 specific configurations */ -#define UART_CFG_OESEL (1 << 20)/*!< RS-485: RTS will be used to control output enable of an RS-485 transceiver */ -#define UART_CFG_OETA (1 << 18)/*!< RS-485: Deassertion of Output Enable signal will be delayed for 1 character time; should be used with #UART_CFG_OESEL */ -#define UART_CFG_AUTOADDR (1 << 19)/*!< RS-485: Enable Automatic address checking [If MSB of Rx data is 1, hadware compares it with address set with #UART_CFG_ADDR] */ -#define UART_CFG_OEPOLHIGH (1 << 21)/*!< RS-485: Output enable signal is active high */ -#define UART_CFG_ADDR(adr) ((adr) << 24)/*!< RS-485: Set RS-485 device address comparision */ - -#define UART_CFG_RXPOL (1 << 22)/*!< Invert the RX Pin polarity; 1 considered start and 0 considered stop, with inverted data */ -#define UART_CFG_TXPOL (1 << 23)/*!< Invert the TX Pin polarity; 1 sent as start and 0 sent as stop, with inverted data */ - -/** @brief UART configuration options used with UART_SetCtrl() */ -#define UART_BREAK_ON ((1UL << 0) | (1UL << 16)) /*!< Sends BREAK on the TX line till SetConfig() called with #UART_BREAK_OFF; - Sending BREAK when TX is in progress might make the receiver get a frame error - Use UART_TX_PAUSE before setting UART_BREAK_ON to safely send break */ -#define UART_BREAK_OFF (1UL << 16) /*!< Turns OFF break condition */ -#define UART_ADDRDET_ON ((1UL << 1) | (1UL << 17)) /*!< Enable Address detect mode in RS-485; When turned on receiver ignores all - incoming data that has MSB [Typically 9th Bit] as 0, when data with MSB as 1 - is received it will cause the UART TX EVENT, software can compare the address - and call SetConfig with #UART_ADDRDET_OFF to resume to normal mode */ -#define UART_ADDRDET_OFF (1UL << 17) /*!< Disable address detect mode in RS-485 */ -#define UART_TX_PAUSE ((1UL << 5) | (1UL << 21)) /*!< Pause Transmit; typically used for Software flow control implementation this, - will invoke callback registerd for #UART_CB_ERREVT with @a event as #UART_EV_EVENT - and the (void *) arg will be #UART_EVENT_TXPAUSED, the callback will be called after - the current data in shift register is completely transmitted */ -#define UART_TX_RESUME (1UL << 21) /*!< Resume Transmit; typically used for Software flow control */ -#define UART_CCLK_ON ((1UL << 7) | (1UL << 23)) /*!< In Sync mode; sends continuous clock so that RX can happen independent of TX */ -#define UART_CCLK_OFF (1UL << 23) /*!< In Sync mode; Disables continuous clock so that clock will be generated only when characters are being sent */ -#define UART_CCLK_AUTO ((1UL << 8) | (1UL << 24)) /*!< In Sync mode; Sends continuous clock until a complete character is received */ -#define UART_AUTOBAUD ((1UL << 15) | (1UL << 31)) /*!< Enables Autobaud mode; sets the DIV value based on received character */ -#define UART_TXIDLE_ON ((1UL << 3) | (1UL << 19)) /*!< Enable event generation on TX IDLE */ -#define UART_TXIDLE_OFF (1UL << 19) /*!< Disable event generation on TX IDLE */ -#define UART_RX_STOP (1UL << 18) - -/* @brief UART event codes for arg parameter of callback (see #UART_EV_EVENT) */ -#define UART_EVENT_BREAK 0x100 /*!< UART RX line is in BREAK state */ -#define UART_EVENT_NOBREAK 0x101 /*!< UART RX line restored from BREAK state */ -#define UART_EVENT_TXIDLE 0x102 /*!< UART TX is idle; nothing in shift register */ -#define UART_EVENT_TXPAUSED 0x103 /*!< TX is paused */ -#define UART_EVENT_CTSHI 0x104 /*!< CTS line went from low to high; typically used for flow-control */ -#define UART_EVENT_CTSLO 0x105 /*!< CTS line went from High to Low; typically used for flow-control */ - -/** @brief Error codes for arg parameter of callback (see #UART_EV_ERROR) */ -#define UART_ERROR_FRAME 0x200 /*!< UART Frame error */ -#define UART_ERROR_PARITY 0x201 /*!< UART Parity error */ -#define UART_ERROR_AUTOBAUD 0x202 /*!< UART Autobaud error */ -#define UART_ERROR_RXNOISE 0x203 /*!< UART RX NOISE error */ -#define UART_ERROR_OVERRUN 0x204 /*!< UART RX overrun error */ - -/** @brief User context conversion macro - * Macro used to extract the user defined data pointer from a UART ROM - * driver handle.
- * To get a user context, simply use the macro on the driver's handle: - * void *pUserData = ROM_UART_HANDLE_TOUDATA(hUART); - */ -#define ROM_UART_HANDLE_TOUDATA(p) (void *) (*(uint32_t *) p) - -/** @brief UART Configuration data structure */ -typedef PRE_PACK struct POST_PACK { - uint32_t cfg; /*!< UART Configuration value; OR'ed UART_CFG_XXXX values(example #UART_CFG_8BIT) */ - uint16_t div; /*!< UART baudrate divider value; usually calculated by using UART_CalBaud() API */ - uint8_t ovr; /*!< UART Over sampling value; usually calculated by using UART_CalBaud() API */ - uint8_t res; /*!< Reserved for alignment; must be 0 */ -} UART_CFG_T; - -/** - * @brief Structure that has the API pointers in ROM Table - */ -typedef PRE_PACK struct POST_PACK { - /* Index of All the UART/USART driver APIs */ - uint32_t (*GetMemSize)(void); /*!< Returns needed memory size required for run-time context of UART driver */ - ErrorCode_t (*CalBaud)(UART_BAUD_T *baud); /*!< Calculates the baudrate parameters for the given frequency, baud rate */ - UART_HANDLE_T (*Init)(void *pMem, uint32_t baseAddr, void *pUserData); /*!< Initializes the UART driver and peripheral */ - ErrorCode_t (*Configure)(UART_HANDLE_T hUART, const UART_CFG_T *cfg); /*!< Configure the UART to given parameters */ - void (*SetCtrl)(UART_HANDLE_T hUART, uint32_t cfgVal); /*!< Set/Clear special control operations like BREAK, IDLE, etc., */ - ErrorCode_t (*RegisterCB)(UART_HANDLE_T hUART, UART_CBINDEX_T cbIndex, - void (*pCbFunc)(UART_HANDLE_T, UART_EVENT_T, void *)); /*!< Registers an UART callback function */ - void (*Handler)(UART_HANDLE_T hUART); /*!< UART Event handler, should be called from the ISR */ - ErrorCode_t (*Send)(UART_HANDLE_T hUART, const void *buffer, uint16_t size);/*!< Send data to UART */ - ErrorCode_t (*Receive)(UART_HANDLE_T hUART, void *buffer, uint16_t size); /*!< Receive data from UART */ - void (*WaitTx)(UART_HANDLE_T hUART);/*!< Wait for UART TX to complete; Used for polling */ - void (*WaitRx)(UART_HANDLE_T hUART);/*!< Wait for UART data receive to complete; Used for polling */ - uint32_t (*GetDriverVersion)(void); /*!< Get the version of the Driver Firmware in ROM */ -} ROM_UART_API_T; - -/* UART Register offsets */ -#define UART_TX_OFFSET 0x1C -#define UART_RX_OFFSET 0x14 - -/** @brief Calculates UART TX register base address from UART handle */ -#define UART_DMA_TXADDR(han) (*(((uint32_t *) (han)) + 1) + UART_TX_OFFSET) - -/** @brief Calculates UART RX register base address from UART handle */ -#define UART_DMA_RXADDR(han) (*(((uint32_t *) (han)) + 1) + UART_RX_OFFSET) - -/* REMOVE: after H/W IDLE is fixed */ -#define UART_BIT_DLY(baud) ((baud) / 4800 ? 921600 / (baud) : 2400 / (baud) + 224) - -/* Extern declaration so that application can access - * pointer to the function table - */ -extern const ROM_UART_API_T uartrom_api; - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __HW_UART_ROM_API_H */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/inmux_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/inmux_5410x.h deleted file mode 100644 index 5347f055f0a..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/inmux_5410x.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * @brief LPC5410X Input Mux Registers and Driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __INMUX_5410X_H_ -#define __INMUX_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup INMUX_5410X CHIP: LPC5410X Input Mux Registers and Driver - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/** - * @brief LPC5410X Input Mux Register Block Structure - */ -typedef struct { /*!< INMUX Structure */ - __IO uint32_t RESERVED0[6]; - __I uint32_t RESERVED1[42]; - __IO uint32_t PINTSEL[8]; /*!< Pin interrupt select registers */ - __IO uint32_t DMA_ITRIG_INMUX[22]; /*!< Input mux register for DMA trigger inputs */ - __I uint32_t RESERVED2[2]; - __IO uint32_t DMA_OTRIG_INMUX[4]; /*!< Input mux register for DMA trigger inputs */ - __I uint32_t RESERVED3[4]; - __IO uint32_t FREQMEAS_REF; /*!< Clock selection for frequency measurement ref clock */ - __IO uint32_t FREQMEAS_TARGET; /*!< Clock selection for frequency measurement target clock */ -} LPC_INMUX_T; - -/** - * @brief GPIO Pin Interrupt Pin Select (sets PINTSEL register) - * @param pintSel : GPIO PINTSEL interrupt, should be: 0 to 7 - * @param portNum : GPIO port number interrupt, should be: 0 to 1 - * @param pinNum : GPIO pin number Interrupt, should be: 0 to 31 - * @return Nothing - */ -STATIC INLINE void Chip_INMUX_PinIntSel(uint8_t pintSel, uint8_t portNum, uint8_t pinNum) -{ - LPC_INMUX->PINTSEL[pintSel] = (portNum * 32) + pinNum; -} - -/* DMA triggers that can mapped to DMA channels */ -typedef enum { - DMATRIG_ADC0_SEQA_IRQ = 0, /*!< ADC0 sequencer A interrupt as trigger */ - DMATRIG_ADC0_SEQB_IRQ, /*!< ADC0 sequencer B interrupt as trigger */ - DMATRIG_SCT0_DMA0, /*!< SCT 0, DMA 0 as trigger */ - DMATRIG_SCT0_DMA1, /*!< SCT 1, DMA 1 as trigger */ - DMATRIG_TIMER0_MATCH0, /*!< Timer 0, match 0 trigger */ - DMATRIG_TIMER0_MATCH1, /*!< Timer 0, match 1 trigger */ - DMATRIG_TIMER1_MATCH0, /*!< Timer 1, match 0 trigger */ - DMATRIG_TIMER1_MATCH1, /*!< Timer 1, match 1 trigger */ - DMATRIG_TIMER2_MATCH0, /*!< Timer 2, match 0 trigger */ - DMATRIG_TIMER2_MATCH1, /*!< Timer 2, match 1 trigger */ - DMATRIG_TIMER3_MATCH0, /*!< Timer 3, match 0 trigger */ - DMATRIG_TIMER3_MATCH1, /*!< Timer 3, match 1 trigger */ - DMATRIG_TIMER4_MATCH0, /*!< Timer 4, match 0 trigger */ - DMATRIG_TIMER4_MATCH1, /*!< Timer 4, match 1 trigger */ - DMATRIG_PININT0, /*!< Pin interrupt 0 trigger */ - DMATRIG_PININT1, /*!< Pin interrupt 1 trigger */ - DMATRIG_PININT2, /*!< Pin interrupt 2 trigger */ - DMATRIG_PININT3, /*!< Pin interrupt 3 trigger */ - DMATRIG_OUTMUX0, /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */ - DMATRIG_OUTMUX1, /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */ - DMATRIG_OUTMUX2, /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */ - DMATRIG_OUTMUX3 /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */ -} DMA_TRIGSRC_T; - -/** - * @brief Select a trigger source for a DMA channel - * @param ch : DMA channel number - * @param trig : Trigger source for the DMA channel - * @return Nothing - */ -STATIC INLINE void Chip_INMUX_SetDMATrigger(uint8_t ch, DMA_TRIGSRC_T trig) -{ - LPC_INMUX->DMA_ITRIG_INMUX[ch] = (uint32_t) trig; -} - -/** - * @brief Selects a DMA trigger source for the DMATRIG_OUTMUXn IDs - * @param index : Select 0 to 3 to sets the source for DMATRIG_OUTMUX0 to DMATRIG_OUTMUX3 - * @param dmaCh : DMA channel to select for DMATRIG_OUTMUXn source - * @return Nothing - * @note This function sets the DMA trigger (out) source used with the DMATRIG_OUTMUXn - * trigger source. - */ -STATIC INLINE void Chip_INMUX_SetDMAOutMux(uint8_t index, uint8_t dmaCh) -{ - LPC_INMUX->DMA_OTRIG_INMUX[index] = (uint32_t) dmaCh; -} - -/* Freqeuency measure reference and target clock sources */ -typedef enum { - FREQMSR_CLKIN = 0, /*!< CLKIN pin */ - FREQMSR_IRC, /*!< Internal RC (IRC) oscillator */ - FREQMSR_WDOSC, /*!< Watchdog oscillator */ - FREQMSR_32KHZOSC, /*!< 32KHz (RTC) oscillator rate */ - FREQ_MEAS_MAIN_CLK, /*!< main system clock */ - FREQMSR_PIO0_4, /*!< External pin PIO0_4 as input rate */ - FREQMSR_PIO0_20, /*!< External pin PIO0_20 as input rate */ - FREQMSR_PIO0_24, /*!< External pin PIO0_24 as input rate */ - FREQMSR_PIO1_4 /*!< External pin PIO1_4 as input rate */ -} FREQMSR_SRC_T; - -/** - * @brief Selects a reference clock used with the frequency measure function - * @param ref : Frequency measure function reference clock - * @return Nothing - */ -STATIC INLINE void Chip_INMUX_SetFreqMeasRefClock(FREQMSR_SRC_T ref) -{ - LPC_INMUX->FREQMEAS_REF = (uint32_t) ref; -} - -/** - * @brief Selects a target clock used with the frequency measure function - * @param targ : Frequency measure function reference clock - * @return Nothing - */ -STATIC INLINE void Chip_INMUX_SetFreqMeasTargClock(FREQMSR_SRC_T targ) -{ - LPC_INMUX->FREQMEAS_TARGET = (uint32_t) targ; -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __INMUX_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/iocon_5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/iocon_5410x.c deleted file mode 100644 index 865279a7888..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/iocon_5410x.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * @brief LPC5410X IOCON driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Set all I/O Control pin muxing */ -void Chip_IOCON_SetPinMuxing(LPC_IOCON_T *pIOCON, const PINMUX_GRP_T *pinArray, uint32_t arrayLength) -{ - uint32_t ix; - - for (ix = 0; ix < arrayLength; ix++ ) { - Chip_IOCON_PinMuxSet(pIOCON, pinArray[ix].port, pinArray[ix].pin, pinArray[ix].modefunc); - } -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/iocon_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/iocon_5410x.h deleted file mode 100644 index 2ae340b5c9e..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/iocon_5410x.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * @brief LPC5410X IOCON register block and driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __IOCON_5410X_H_ -#define __IOCON_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup IOCON_5410X CHIP: LPC5410X IOCON register block and driver - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/** - * @brief LPC5410X IO Configuration Unit register block structure - */ -typedef struct { /*!< LPC5410X IOCON Structure */ - __IO uint32_t PIO[2][32]; -} LPC_IOCON_T; - -/** - * @brief Array of IOCON pin definitions passed to Chip_IOCON_SetPinMuxing() must be in this format - */ -typedef struct { - uint32_t port : 8; /* Pin port */ - uint32_t pin : 8; /* Pin number */ - uint32_t modefunc : 16; /* Function and mode */ -} PINMUX_GRP_T; - -/** - * IOCON function and mode selection definitions - * See the User Manual for specific modes and functions supported by the - * various LPC15XX pins. - */ -#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ -#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ -#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ -#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ -#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ -#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ -#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ -#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ -#define IOCON_MODE_INACT (0x0 << 3) /*!< No addition pin function */ -#define IOCON_MODE_PULLDOWN (0x1 << 3) /*!< Selects pull-down function */ -#define IOCON_MODE_PULLUP (0x2 << 3) /*!< Selects pull-up function */ -#define IOCON_MODE_REPEATER (0x3 << 3) /*!< Selects pin repeater function */ -#define IOCON_HYS_EN (0x1 << 5) /*!< Enables hysteresis */ -#define IOCON_GPIO_MODE (0x1 << 5) /*!< GPIO Mode */ -#define IOCON_I2C_SLEW (0x1 << 5) /*!< I2C Slew Rate Control */ -#define IOCON_INV_EN (0x1 << 6) /*!< Enables invert function on input */ -#define IOCON_ANALOG_EN (0x0 << 7) /*!< Enables analog function by setting 0 to bit 7 */ -#define IOCON_DIGITAL_EN (0x1 << 7) /*!< Enables digital function by setting 1 to bit 7(default) */ -#define IOCON_STDI2C_EN (0x1 << 8) /*!< I2C standard mode/fast-mode */ -#define IOCON_FASTI2C_EN (0x3 << 8) /*!< I2C Fast-mode Plus and high-speed slave */ -#define IOCON_INPFILT_OFF (0x1 << 8) /*!< Input filter Off for GPIO pins */ -#define IOCON_INPFILT_ON (0x0 << 8) /*!< Input filter On for GPIO pins */ -#define IOCON_OPENDRAIN_EN (0x1 << 10) /*!< Enables open-drain function */ -#define IOCON_S_MODE_0CLK (0x0 << 11) /*!< Bypass input filter */ -#define IOCON_S_MODE_1CLK (0x1 << 11) /*!< Input pulses shorter than 1 filter clock are rejected */ -#define IOCON_S_MODE_2CLK (0x2 << 11) /*!< Input pulses shorter than 2 filter clock2 are rejected */ -#define IOCON_S_MODE_3CLK (0x3 << 11) /*!< Input pulses shorter than 3 filter clock2 are rejected */ -#define IOCON_S_MODE(clks) ((clks) << 11) /*!< Select clocks for digital input filter mode */ -#define IOCON_CLKDIV(div) ((div) << 13) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ - -/** - * @brief Sets I/O Control pin mux - * @param pIOCON : The base of IOCON peripheral on the chip - * @param port : GPIO port to mux - * @param pin : GPIO pin to mux - * @param modefunc : OR'ed values or type IOCON_* - * @return Nothing - */ -STATIC INLINE void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t modefunc) -{ - pIOCON->PIO[port][pin] = modefunc; -} - -/** - * @brief I/O Control pin mux - * @param pIOCON : The base of IOCON peripheral on the chip - * @param port : GPIO port to mux - * @param pin : GPIO pin to mux - * @param mode : OR'ed values or type IOCON_* - * @param func : Pin function, value of type IOCON_FUNC? - * @return Nothing - */ -STATIC INLINE void Chip_IOCON_PinMux(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint16_t mode, uint8_t func) -{ - Chip_IOCON_PinMuxSet(pIOCON, port, pin, (uint32_t) (mode | func)); -} - -/** - * @brief Set all I/O Control pin muxing - * @param pIOCON : The base of IOCON peripheral on the chip - * @param pinArray : Pointer to array of pin mux selections - * @param arrayLength : Number of entries in pinArray - * @return Nothing - */ -void Chip_IOCON_SetPinMuxing(LPC_IOCON_T *pIOCON, const PINMUX_GRP_T *pinArray, uint32_t arrayLength); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __IOCON_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/keil_output/core_m4/ArInp.Scr b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/keil_output/core_m4/ArInp.Scr deleted file mode 100644 index 599fc03c973..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/keil_output/core_m4/ArInp.Scr +++ /dev/null @@ -1,47 +0,0 @@ ---create .\keil_output\core_m4\lib_chip_5410x.lib -.\keil_output\core_m4\ring_buffer.o -.\keil_output\core_m4\chip_5410x.o -.\keil_output\core_m4\clock_5410x.o -.\keil_output\core_m4\crc_5410x.o -.\keil_output\core_m4\gpio_5410x.o -.\keil_output\core_m4\iocon_5410x.o -.\keil_output\core_m4\pinint_5410x.o -.\keil_output\core_m4\sct_5410x.o -.\keil_output\core_m4\sct_pwm_5410x.o -.\keil_output\core_m4\syscon_5410x.o -.\keil_output\core_m4\sysinit_5410x.o -.\keil_output\core_m4\timer_5410x.o -.\keil_output\core_m4\utick_5410x.o -.\keil_output\core_m4\wwdt_5410x.o -.\keil_output\core_m4\rtc_5410x.o -.\keil_output\core_m4\fpu_init.o -.\keil_output\core_m4\iap.o -.\keil_output\core_m4\gpiogroup_5410x.o -.\keil_output\core_m4\stopwatch_5410x.o -.\keil_output\core_m4\ritimer_5410x.o -.\keil_output\core_m4\romapi_adc.o -.\keil_output\core_m4\romapi_dma.o -.\keil_output\core_m4\romapi_i2cm.o -.\keil_output\core_m4\romapi_i2cmon.o -.\keil_output\core_m4\romapi_i2cs.o -.\keil_output\core_m4\romapi_spim.o -.\keil_output\core_m4\romapi_spis.o -.\keil_output\core_m4\romapi_uart.o -.\keil_output\core_m4\rtc_ut.o -.\keil_output\core_m4\pll_5410x.o -.\keil_output\core_m4\hw_adc.o -.\keil_output\core_m4\hw_dmaaltd.o -.\keil_output\core_m4\hw_dmaaltd_rom_api.o -.\keil_output\core_m4\hw_i2cmd.o -.\keil_output\core_m4\hw_i2cmd_rom_api.o -.\keil_output\core_m4\hw_i2cmond.o -.\keil_output\core_m4\hw_i2cmond_rom_api.o -.\keil_output\core_m4\hw_i2csd.o -.\keil_output\core_m4\hw_i2csd_rom_api.o -.\keil_output\core_m4\hw_spimd_rom_api.o -.\keil_output\core_m4\hw_spisd.o -.\keil_output\core_m4\hw_spisd_rom_api.o -.\keil_output\core_m4\hw_spimd.o -.\keil_output\core_m4\hw_uart.o -.\keil_output\core_m4\fifo_5410x.o -.\power_lib\keil\lib_power.lib diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/lib_chip_5410x.ewp b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/lib_chip_5410x.ewp deleted file mode 100644 index 61b8390d91d..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/lib_chip_5410x.ewp +++ /dev/null @@ -1,1095 +0,0 @@ - - - - 2 - - chip_5410x_lib - - ARM - - 1 - - General - 3 - - 22 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - csp - - $PROJ_DIR$\chip_5410x.c - - - $PROJ_DIR$\clock_5410x.c - - - $PROJ_DIR$\crc_5410x.c - - - $PROJ_DIR$\fifo_5410x.c - - - $PROJ_DIR$\..\chip_common\fpu_init.c - - - $PROJ_DIR$\gpio_5410x.c - - - $PROJ_DIR$\gpiogroup_5410x.c - - - $PROJ_DIR$\hw_adc.c - - - $PROJ_DIR$\hw_dmaaltd.c - - - $PROJ_DIR$\hw_dmaaltd_rom_api.c - - - $PROJ_DIR$\hw_i2cmd.c - - - $PROJ_DIR$\hw_i2cmd_rom_api.c - - - $PROJ_DIR$\hw_i2cmond.c - - - $PROJ_DIR$\hw_i2cmond_rom_api.c - - - $PROJ_DIR$\hw_i2csd.c - - - $PROJ_DIR$\hw_i2csd_rom_api.c - - - $PROJ_DIR$\hw_spimd.c - - - $PROJ_DIR$\hw_spimd_rom_api.c - - - $PROJ_DIR$\hw_spisd.c - - - $PROJ_DIR$\hw_spisd_rom_api.c - - - $PROJ_DIR$\hw_uart.c - - - $PROJ_DIR$\..\chip_common\iap.c - - - $PROJ_DIR$\iocon_5410x.c - - - $PROJ_DIR$\pinint_5410x.c - - - $PROJ_DIR$\pll_5410x.c - - - $PROJ_DIR$\..\chip_common\ring_buffer.c - - - $PROJ_DIR$\ritimer_5410x.c - - - $PROJ_DIR$\romapi_adc.c - - - $PROJ_DIR$\romapi_dma.c - - - $PROJ_DIR$\romapi_i2cm.c - - - $PROJ_DIR$\romapi_i2cmon.c - - - $PROJ_DIR$\romapi_i2cs.c - - - $PROJ_DIR$\romapi_spim.c - - - $PROJ_DIR$\romapi_spis.c - - - $PROJ_DIR$\romapi_uart.c - - - $PROJ_DIR$\rtc_5410x.c - - - $PROJ_DIR$\..\chip_common\rtc_ut.c - - - $PROJ_DIR$\sct_5410x.c - - - $PROJ_DIR$\sct_pwm_5410x.c - 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### uVision Project, (C) Keil Software
- - - - lib_chip_5410x - 0x4 - ARM-ADS - - - LPC54102:M4 - NXP - Keil.LPC54000_DFP.1.0.0 - http://www.keil.com/pack/ - IROM(0x00000000,0x80000) IRAM(0x02000000,0x10000) IRAM2(0x02010000,0x08000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD02000000 -FC1000 -FN1 -FF0LPC54xxx_512 -FS00 -FL080000 -FP0($$Device:LPC54102$Flash\LPC54xxx_512.FLM)) - 0 - $$Device:LPC54102$Device\Include\LPC54xxx.h - - - - - - - - - - $$Device:LPC54102$SVD\LPC54xxx.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\keil_output\core_m4\ - lib_chip_5410x - 0 - 1 - 0 - 1 - 1 - .\keil_output\core_m4\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - 1 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -MPU - DCM.DLL - -pCM4 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 1 - 0 - 1 - - 0 - 1 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M4" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 2 - 1 - 0 - 8 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x2000000 - 0x10000 - - - 1 - 0x0 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x80000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x2000000 - 0x10000 - - - 0 - 0x2010000 - 0x8000 - - - - - - 1 - 4 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 0 - 0 - - - CORE_M4 - - .\config;..\chip_5410x;..\chip_common;..\..\..\CMSIS\CMSIS\Include - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x00000000 - - - - - - - - - - - - - csp - - - ring_buffer.c - 1 - ..\chip_common\ring_buffer.c - - - chip_5410x.c - 1 - .\chip_5410x.c - - - clock_5410x.c - 1 - .\clock_5410x.c - - - crc_5410x.c - 1 - .\crc_5410x.c - - - gpio_5410x.c - 1 - .\gpio_5410x.c - - - iocon_5410x.c - 1 - .\iocon_5410x.c - - - pinint_5410x.c - 1 - .\pinint_5410x.c - - - sct_5410x.c - 1 - .\sct_5410x.c - - - sct_pwm_5410x.c - 1 - .\sct_pwm_5410x.c - - - syscon_5410x.c - 1 - .\syscon_5410x.c - - - sysinit_5410x.c - 1 - .\sysinit_5410x.c - - - timer_5410x.c - 1 - .\timer_5410x.c - - - utick_5410x.c - 1 - .\utick_5410x.c - - - wwdt_5410x.c - 1 - .\wwdt_5410x.c - - - rtc_5410x.c - 1 - .\rtc_5410x.c - - - fpu_init.c - 1 - ..\chip_common\fpu_init.c - - - iap.c - 1 - ..\chip_common\iap.c - - - gpiogroup_5410x.c - 1 - .\gpiogroup_5410x.c - - - stopwatch_5410x.c - 1 - .\stopwatch_5410x.c - - - ritimer_5410x.c - 1 - .\ritimer_5410x.c - - - romapi_adc.c - 1 - .\romapi_adc.c - - - romapi_dma.c - 1 - .\romapi_dma.c - - - romapi_i2cm.c - 1 - .\romapi_i2cm.c - - - romapi_i2cmon.c - 1 - .\romapi_i2cmon.c - - - romapi_i2cs.c - 1 - .\romapi_i2cs.c - - - romapi_spim.c - 1 - .\romapi_spim.c - - - romapi_spis.c - 1 - .\romapi_spis.c - - - romapi_uart.c - 1 - .\romapi_uart.c - - - rtc_ut.c - 1 - ..\chip_common\rtc_ut.c - - - pll_5410x.c - 1 - .\pll_5410x.c - - - hw_adc.c - 1 - .\hw_adc.c - - - hw_dmaaltd.c - 1 - .\hw_dmaaltd.c - - - hw_dmaaltd_rom_api.c - 1 - .\hw_dmaaltd_rom_api.c - - - hw_i2cmd.c - 1 - .\hw_i2cmd.c - - - hw_i2cmd_rom_api.c - 1 - .\hw_i2cmd_rom_api.c - - - hw_i2cmond.c - 1 - .\hw_i2cmond.c - - - hw_i2cmond_rom_api.c - 1 - .\hw_i2cmond_rom_api.c - - - hw_i2csd.c - 1 - .\hw_i2csd.c - - - hw_i2csd_rom_api.c - 1 - .\hw_i2csd_rom_api.c - - - hw_spimd_rom_api.c - 1 - .\hw_spimd_rom_api.c - - - hw_spisd.c - 1 - .\hw_spisd.c - - - hw_spisd_rom_api.c - 1 - .\hw_spisd_rom_api.c - - - hw_spimd.c - 1 - .\hw_spimd.c - - - hw_uart.c - 1 - .\hw_uart.c - - - fifo_5410x.c - 1 - .\fifo_5410x.c - - - - - lib - - - lib_power.lib - 4 - .\power_lib\keil\lib_power.lib - - - - - - - - diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/lib_chip_5410x_m0.ewp b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/lib_chip_5410x_m0.ewp deleted file mode 100644 index c81958e00e1..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/lib_chip_5410x_m0.ewp +++ /dev/null @@ -1,1089 +0,0 @@ - - - - 2 - - chip_5410x_lib - - ARM - - 1 - - General - 3 - - 22 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - csp - - $PROJ_DIR$\chip_5410x.c - - - $PROJ_DIR$\clock_5410x.c - - - $PROJ_DIR$\crc_5410x.c - - - $PROJ_DIR$\gpio_5410x.c - - - $PROJ_DIR$\gpiogroup_5410x.c - - - $PROJ_DIR$\hw_adc.c - - - $PROJ_DIR$\hw_dmaaltd.c - - - $PROJ_DIR$\hw_dmaaltd_rom_api.c - - - $PROJ_DIR$\hw_i2cmd.c - - - $PROJ_DIR$\hw_i2cmd_rom_api.c - - - $PROJ_DIR$\hw_i2cmond.c - - - $PROJ_DIR$\hw_i2cmond_rom_api.c - - - $PROJ_DIR$\hw_i2csd.c - - - $PROJ_DIR$\hw_i2csd_rom_api.c - - - $PROJ_DIR$\hw_spimd.c - - - $PROJ_DIR$\hw_spimd_rom_api.c - - - $PROJ_DIR$\hw_spisd.c - - - $PROJ_DIR$\hw_spisd_rom_api.c - - - $PROJ_DIR$\hw_uart.c - - - $PROJ_DIR$\fifo_5410x.c - - - $PROJ_DIR$\iocon_5410x.c - - - $PROJ_DIR$\pinint_5410x.c - - - $PROJ_DIR$\pll_5410x.c - - - $PROJ_DIR$\..\chip_common\ring_buffer.c - - - $PROJ_DIR$\ritimer_5410x.c - - - $PROJ_DIR$\romapi_adc.c - - - $PROJ_DIR$\romapi_dma.c - - - $PROJ_DIR$\romapi_i2cm.c - - - $PROJ_DIR$\romapi_i2cmon.c - - - $PROJ_DIR$\romapi_i2cs.c - - - $PROJ_DIR$\romapi_spim.c - - - $PROJ_DIR$\romapi_spis.c - - - $PROJ_DIR$\romapi_uart.c - - - $PROJ_DIR$\rtc_5410x.c - - - $PROJ_DIR$\..\chip_common\rtc_ut.c - - - $PROJ_DIR$\sct_5410x.c - - - $PROJ_DIR$\sct_pwm_5410x.c - - - $PROJ_DIR$\stopwatch_5410x.c - - - $PROJ_DIR$\syscon_5410x.c - - - $PROJ_DIR$\sysinit_5410x.c - - - $PROJ_DIR$\timer_5410x.c - - - $PROJ_DIR$\utick_5410x.c - - - $PROJ_DIR$\wwdt_5410x.c - - - - libs - - $PROJ_DIR$\power_lib\iar\lib_power.a - - - - - diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/lib_chip_5410x_m0.uvprojx b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/lib_chip_5410x_m0.uvprojx deleted file mode 100644 index d58f5367bd5..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/lib_chip_5410x_m0.uvprojx +++ /dev/null @@ -1,652 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - lib_chip_5410x_m0 - 0x4 - ARM-ADS - - - LPC54102:M0plus - NXP - Keil.LPC54000_DFP.0.0.0 - http://www.keil.com/pack/ - IROM(0x00000000,0x80000) IRAM(0x02000000,0x10000) IRAM2(0x02010000,0x08000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD02000000 -FC1000 -FN1 -FF0LPC54xxx_512 -FS00 -FL080000 -FP0($$Device:LPC54102$Flash\LPC54xxx_512.FLM)) - 0 - $$Device:LPC54102$Device\Include\LPC54xxx.h - - - - - - - - - - $$Device:LPC54102$SVD\LPC54xxx.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\keil_output\core_m0\ - lib_chip_5410x_m0 - 0 - 1 - 0 - 1 - 1 - .\keil_output\core_m4\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - 1 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DARMCM1.DLL - -pCM0+ - SARMCM3.DLL - - TARMCM1.DLL - -pCM0+ - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 1 - 0 - 1 - - 0 - 1 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M0+" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 8 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x2000000 - 0x10000 - - - 1 - 0x0 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x80000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x2000000 - 0x10000 - - - 0 - 0x2010000 - 0x8000 - - - - - - 1 - 4 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 0 - 0 - - - CORE_M0PLUS - - .\config;..\chip_5410x;..\chip_common;..\..\..\CMSIS\CMSIS\Include - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x00000000 - - - - - - - - - - - - - csp - - - ring_buffer.c - 1 - ..\chip_common\ring_buffer.c - - - chip_5410x.c - 1 - .\chip_5410x.c - - - clock_5410x.c - 1 - .\clock_5410x.c - - - crc_5410x.c - 1 - .\crc_5410x.c - - - gpio_5410x.c - 1 - .\gpio_5410x.c - - - iocon_5410x.c - 1 - .\iocon_5410x.c - - - pinint_5410x.c - 1 - .\pinint_5410x.c - - - sct_5410x.c - 1 - .\sct_5410x.c - - - sct_pwm_5410x.c - 1 - .\sct_pwm_5410x.c - - - syscon_5410x.c - 1 - .\syscon_5410x.c - - - sysinit_5410x.c - 1 - .\sysinit_5410x.c - - - timer_5410x.c - 1 - .\timer_5410x.c - - - utick_5410x.c - 1 - .\utick_5410x.c - - - wwdt_5410x.c - 1 - .\wwdt_5410x.c - - - rtc_5410x.c - 1 - .\rtc_5410x.c - - - fpu_init.c - 1 - ..\chip_common\fpu_init.c - - - iap.c - 1 - ..\chip_common\iap.c - - - gpiogroup_5410x.c - 1 - .\gpiogroup_5410x.c - - - stopwatch_5410x.c - 1 - .\stopwatch_5410x.c - - - ritimer_5410x.c - 1 - .\ritimer_5410x.c - - - romapi_adc.c - 1 - .\romapi_adc.c - - - romapi_dma.c - 1 - .\romapi_dma.c - - - romapi_i2cm.c - 1 - .\romapi_i2cm.c - - - romapi_i2cmon.c - 1 - .\romapi_i2cmon.c - - - romapi_i2cs.c - 1 - .\romapi_i2cs.c - - - romapi_spim.c - 1 - .\romapi_spim.c - - - romapi_spis.c - 1 - .\romapi_spis.c - - - romapi_uart.c - 1 - .\romapi_uart.c - - - rtc_ut.c - 1 - ..\chip_common\rtc_ut.c - - - pll_5410x.c - 1 - .\pll_5410x.c - - - hw_adc.c - 1 - .\hw_adc.c - - - hw_dmaaltd.c - 1 - .\hw_dmaaltd.c - - - hw_dmaaltd_rom_api.c - 1 - .\hw_dmaaltd_rom_api.c - - - hw_i2cmd.c - 1 - .\hw_i2cmd.c - - - hw_i2cmd_rom_api.c - 1 - .\hw_i2cmd_rom_api.c - - - hw_i2cmond.c - 1 - .\hw_i2cmond.c - - - hw_i2cmond_rom_api.c - 1 - .\hw_i2cmond_rom_api.c - - - hw_i2csd.c - 1 - .\hw_i2csd.c - - - hw_i2csd_rom_api.c - 1 - .\hw_i2csd_rom_api.c - - - hw_spimd_rom_api.c - 1 - .\hw_spimd_rom_api.c - - - hw_spisd.c - 1 - .\hw_spisd.c - - - hw_spisd_rom_api.c - 1 - .\hw_spisd_rom_api.c - - - hw_spimd.c - 1 - .\hw_spimd.c - - - hw_uart.c - 1 - .\hw_uart.c - - - fifo_5410x.c - 1 - .\fifo_5410x.c - - - - - lib - - - lib_power_m0.lib - 4 - .\power_lib\keil\lib_power_m0.lib - - - - - - - - diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/mailbox_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/mailbox_5410x.h deleted file mode 100644 index b28ddeaa3a8..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/mailbox_5410x.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * @brief LPC5410X Mailbox M4/M0+ driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __MAILBOX_5410X_H_ -#define __MAILBOX_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup MAILBOX_5410X CHIP: LPC5410X Mailbox M4/M0+ driver - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/* Mailbox indexes */ -typedef enum { - MAILBOX_CM0PLUS = 0, - MAILBOX_CM4 -} MBOX_IDX_T; -#define MAILBOX_AVAIL (MAILBOX_CM4 + 1) /* Number of available mailboxes */ - -/** Individual mailbox IRQ structure */ -typedef struct { - __IO uint32_t IRQ; /*!< Mailbox data */ - __O uint32_t IRQSET; /*!< Mailbox data set bits only */ - __O uint32_t IRQCLR; /*!< Mailbox dataclearset bits only */ - __I uint32_t RESERVED; -} LPC_MBOXIRQ_T; - -/** Mailbox register structure */ -typedef struct { /*!< Mailbox register structure */ - LPC_MBOXIRQ_T BOX[MAILBOX_AVAIL]; /*!< Mailbox, offset 0 = M0+, offset 1 = M4 */ - LPC_MBOXIRQ_T RESERVED1[15 - MAILBOX_AVAIL]; - __I uint32_t RESERVED2[2]; - __IO uint32_t MUTEX; /*!< Mutex */ -} LPC_MBOX_T; - -/** - * @brief Initialize mailbox - * @param pMBOX : Pointer to the mailbox register structure - * @return Nothing - * @note Even if both cores use the amilbox, only 1 core should initialize it. - */ -STATIC INLINE void Chip_MBOX_Init(LPC_MBOX_T *pMBOX) -{ - Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_MAILBOX); - Chip_SYSCON_PeriphReset(RESET_MAILBOX); -} - -/** - * @brief Shutdown mailbox - * @param pMBOX : Pointer to the mailbox register structure - * @return Nothing - */ -STATIC INLINE void Chip_MBOX_DeInit(LPC_MBOX_T *pMBOX) -{ - Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_MAILBOX); -} - -/** - * @brief Set data value in the mailbox based on the CPU ID - * @param pMBOX : Pointer to the mailbox register structure - * @param cpu_id : MAILBOX_CM0PLUS is M0+ or MAILBOX_CM4 is M4 - * @param mboxData : data to send in the mailbox - * @return Nothing - * @note Sets a data value to send via the MBOX to the other core. - */ -STATIC INLINE void Chip_MBOX_SetValue(LPC_MBOX_T *pMBOX, uint32_t cpu_id, uint32_t mboxData) -{ - pMBOX->BOX[cpu_id].IRQ = mboxData; -} - -/** - * @brief Set data bits in the mailbox based on the CPU ID - * @param pMBOX : Pointer to the mailbox register structure - * @param cpu_id : MAILBOX_CM0PLUS is M0+ or MAILBOX_CM4 is M4 - * @param mboxSetBits : data bits to set in the mailbox - * @return Nothing - * @note Sets data bits to send via the MBOX to the other core, A value of 0 will - * do nothing. Only sets bits selected with a 1 in it's bit position. - */ -STATIC INLINE void Chip_MBOX_SetValueBits(LPC_MBOX_T *pMBOX, uint32_t cpu_id, uint32_t mboxSetBits) -{ - pMBOX->BOX[cpu_id].IRQSET = mboxSetBits; -} - -/** - * @brief Clear data bits in the mailbox based on the CPU ID - * @param pMBOX : Pointer to the mailbox register structure - * @param cpu_id : MAILBOX_CM0PLUS is M0+ or MAILBOX_CM4 is M4 - * @param mboxClrBits : data bits to clear in the mailbox - * @return Nothing - * @note Clear data bits to send via the MBOX to the other core. A value of 0 will - * do nothing. Only clears bits selected with a 1 in it's bit position. - */ -STATIC INLINE void Chip_MBOX_ClearValueBits(LPC_MBOX_T *pMBOX, uint32_t cpu_id, uint32_t mboxClrBits) -{ - pMBOX->BOX[cpu_id].IRQCLR = mboxClrBits; -} - -/** - * @brief Get data in the mailbox based on the cpu_id - * @param pMBOX : Pointer to the mailbox register structure - * @param cpu_id : MAILBOX_CM0PLUS is M0+ or MAILBOX_CM4 is M4 - * @return Current mailbox data - */ -STATIC INLINE uint32_t Chip_MBOX_GetValue(LPC_MBOX_T *pMBOX, uint32_t cpu_id) -{ - return pMBOX->BOX[cpu_id].IRQ; -} - -/** - * @brief Get MUTEX state and lock mutex - * @param pMBOX : Pointer to the mailbox register structure - * @return See note - * @note Returns '1' if the mutex was taken or '0' if another resources has the - * mutex locked. Once a mutex is taken, it can be returned with the Chip_MBOX_SetMutex() - * function. - */ -STATIC INLINE uint32_t Chip_MBOX_GetMutex(LPC_MBOX_T *pMBOX) -{ - return pMBOX->MUTEX; -} - -/** - * @brief Set MUTEX state - * @param pMBOX : Pointer to the mailbox register structure - * @return Nothing - * @note Sets mutex state to '1' and allows other resources to get the mutex - */ -STATIC INLINE void Chip_MBOX_SetMutex(LPC_MBOX_T *pMBOX) -{ - pMBOX->MUTEX = 1; -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __MAILBOX_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/mrt_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/mrt_5410x.h deleted file mode 100644 index c2b4639da33..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/mrt_5410x.h +++ /dev/null @@ -1,340 +0,0 @@ -/* - * @brief LPC5410X Multi-Rate Timer (MRT) registers and driver functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __MRT_5410X_H_ -#define __MRT_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup MRT_5410X CHIP: LPC5410X Multi-Rate Timer driver - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/** - * @brief LPC5410X MRT chip configuration - */ -#define MRT_CHANNELS_NUM (4) -#define MRT_NO_IDLE_CHANNEL (0x40) - -/** - * @brief MRT register block structure - */ -typedef struct { - __IO uint32_t INTVAL; /*!< Timer interval register */ - __O uint32_t TIMER; /*!< Timer register */ - __IO uint32_t CTRL; /*!< Timer control register */ - __IO uint32_t STAT; /*!< Timer status register */ -} LPC_MRT_CH_T; - -/** - * @brief MRT register block structure - */ -typedef struct { - LPC_MRT_CH_T CHANNEL[MRT_CHANNELS_NUM]; - uint32_t unused[44]; - __IO uint32_t MODCFG; - __O uint32_t IDLE_CH; - __IO uint32_t IRQ_FLAG; -} LPC_MRT_T; - -/** - * @brief MRT Interrupt Modes enum - */ -typedef enum MRT_MODE { - MRT_MODE_REPEAT = (0 << 1), /*!< MRT Repeat interrupt mode */ - MRT_MODE_ONESHOT = (1 << 1) /*!< MRT One-shot interrupt mode */ -} MRT_MODE_T; - -/** - * @brief MRT register bit fields & masks - */ -/* MRT Time interval register bit fields */ -#define MRT_INTVAL_IVALUE (0x7FFFFFFF) /* Maximum interval load value and mask */ -#define MRT_INTVAL_LOAD (0x80000000UL) /* Force immediate load of timer interval register bit */ - -/* MRT Control register bit fields & masks */ -#define MRT_CTRL_INTEN_MASK (0x01) -#define MRT_CTRL_MODE_MASK (0x06) - -/* MRT Status register bit fields & masks */ -#define MRT_STAT_INTFLAG (0x01) -#define MRT_STAT_RUNNING (0x02) - -/* Pointer to individual MR register blocks */ -#define LPC_MRT_CH0 ((LPC_MRT_CH_T *) &LPC_MRT->CHANNEL[0]) -#define LPC_MRT_CH1 ((LPC_MRT_CH_T *) &LPC_MRT->CHANNEL[1]) -#define LPC_MRT_CH2 ((LPC_MRT_CH_T *) &LPC_MRT->CHANNEL[2]) -#define LPC_MRT_CH3 ((LPC_MRT_CH_T *) &LPC_MRT->CHANNEL[3]) -#define LPC_MRT_CH(ch) ((LPC_MRT_CH_T *) &LPC_MRT->CHANNEL[(ch)]) - -/* Global interrupt flag register interrupt mask/clear values */ -#define MRT0_INTFLAG (1) -#define MRT1_INTFLAG (2) -#define MRT2_INTFLAG (4) -#define MRT3_INTFLAG (8) -#define MRTn_INTFLAG(ch) (1 << (ch)) - -/** - * @brief Initializes the MRT - * @return Nothing - */ -STATIC INLINE void Chip_MRT_Init(void) -{ - /* Enable the clock to the register interface */ - Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_MRT); - - /* Reset MRT */ - Chip_SYSCON_PeriphReset(RESET_MRT); -} - -/** - * @brief De-initializes the MRT Channel - * @return Nothing - */ -STATIC INLINE void Chip_MRT_DeInit(void) -{ - /* Disable the clock to the MRT */ - Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_MRT); -} - -/** - * @brief Returns a pointer to the register block for a MRT channel - * @param ch : MRT channel tog et register block for (0..3) - * @return Pointer to the MRT register block for the channel - */ -STATIC INLINE LPC_MRT_CH_T *Chip_MRT_GetRegPtr(uint8_t ch) -{ - return LPC_MRT_CH(ch); -} - -/** - * @brief Returns the timer time interval value - * @param pMRT : Pointer to selected MRT Channel - * @return Timer time interval value (IVALUE) - */ -STATIC INLINE uint32_t Chip_MRT_GetInterval(LPC_MRT_CH_T *pMRT) -{ - return pMRT->INTVAL; -} - -/** - * @brief Sets the timer time interval value - * @param pMRT : Pointer to selected MRT Channel - * @param interval : The interval timeout (31-bits) - * @return Nothing - * @note Setting bit 31 in timer time interval register causes the time interval value - * to load immediately, otherwise the time interval value will be loaded in - * next timer cycle.
- * Example: Chip_MRT_SetInterval(pMRT, 0x500 | MRT_INTVAL_LOAD); // Will load timer interval immediately
- * Example: Chip_MRT_SetInterval(pMRT, 0x500); // Will load timer interval after internal expires - */ -STATIC INLINE void Chip_MRT_SetInterval(LPC_MRT_CH_T *pMRT, uint32_t interval) -{ - pMRT->INTVAL = interval; -} - -/** - * @brief Returns the current timer value - * @param pMRT : Pointer to selected MRT Channel - * @return The current timer value - */ -STATIC INLINE uint32_t Chip_MRT_GetTimer(LPC_MRT_CH_T *pMRT) -{ - return pMRT->TIMER; -} - -/** - * @brief Returns true if the timer is enabled - * @param pMRT : Pointer to selected MRT Channel - * @return True if enabled, Flase if not enabled - */ -STATIC INLINE bool Chip_MRT_GetEnabled(LPC_MRT_CH_T *pMRT) -{ - return (bool) ((pMRT->CTRL & MRT_CTRL_INTEN_MASK) != 0); -} - -/** - * @brief Enables the timer - * @param pMRT : Pointer to selected MRT Channel - * @return Nothing - */ -STATIC INLINE void Chip_MRT_SetEnabled(LPC_MRT_CH_T *pMRT) -{ - pMRT->CTRL |= MRT_CTRL_INTEN_MASK; -} - -/** - * @brief Disables the timer - * @param pMRT : Pointer to selected MRT Channel - * @return Nothing - */ -STATIC INLINE void Chip_MRT_SetDisabled(LPC_MRT_CH_T *pMRT) -{ - pMRT->CTRL &= ~MRT_CTRL_INTEN_MASK; -} - -/** - * @brief Returns the timer mode (repeat or one-shot) - * @param pMRT : Pointer to selected MRT Channel - * @return The current timer mode - */ -STATIC INLINE MRT_MODE_T Chip_MRT_GetMode(LPC_MRT_CH_T *pMRT) -{ - return (MRT_MODE_T) (pMRT->CTRL & MRT_CTRL_MODE_MASK); -} - -/** - * @brief Sets the timer mode (repeat or one-shot) - * @param pMRT : Pointer to selected MRT Channel - * @param mode : Timer mode - * @return Nothing - */ -STATIC INLINE void Chip_MRT_SetMode(LPC_MRT_CH_T *pMRT, MRT_MODE_T mode) -{ - uint32_t reg; - - reg = pMRT->CTRL & ~MRT_CTRL_MODE_MASK; - pMRT->CTRL = reg | (uint32_t) mode; -} - -/** - * @brief Check if the timer is configured in repeat mode - * @param pMRT : Pointer to selected MRT Channel - * @return True if in repeat mode, False if in one-shot mode - */ -STATIC INLINE bool Chip_MRT_IsRepeatMode(LPC_MRT_CH_T *pMRT) -{ - return ((pMRT->CTRL & MRT_CTRL_MODE_MASK) != 0) ? false : true; -} - -/** - * @brief Check if the timer is configured in one-shot mode - * @param pMRT : Pointer to selected MRT Channel - * @return True if in one-shot mode, False if in repeat mode - */ -STATIC INLINE bool Chip_MRT_IsOneShotMode(LPC_MRT_CH_T *pMRT) -{ - return ((pMRT->CTRL & MRT_CTRL_MODE_MASK) != 0) ? true : false; -} - -/** - * @brief Check if the timer has an interrupt pending - * @param pMRT : Pointer to selected MRT Channel - * @return True if interrupt is pending, False if no interrupt is pending - */ -STATIC INLINE bool Chip_MRT_IntPending(LPC_MRT_CH_T *pMRT) -{ - return (bool) ((pMRT->STAT & MRT_STAT_INTFLAG) != 0); -} - -/** - * @brief Clears the pending interrupt (if any) - * @param pMRT : Pointer to selected MRT Channel - * @return Nothing - */ -STATIC INLINE void Chip_MRT_IntClear(LPC_MRT_CH_T *pMRT) -{ - pMRT->STAT |= MRT_STAT_INTFLAG; -} - -/** - * @brief Check if the timer is running - * @param pMRT : Pointer to selected MRT Channel - * @return True if running, False if stopped - */ -STATIC INLINE bool Chip_MRT_Running(LPC_MRT_CH_T *pMRT) -{ - return (bool) ((pMRT->STAT & MRT_STAT_RUNNING) != 0); -} - -/** - * @brief Returns the IDLE channel value - * @return IDLE channel value (unshifted in bits 7..4) - */ -STATIC INLINE uint8_t Chip_MRT_GetIdleChannel(void) -{ - return (uint8_t) (LPC_MRT->IDLE_CH); -} - -/** - * @brief Returns the IDLE channel value - * @return IDLE channel value (shifted in bits 3..0) - */ -STATIC INLINE uint8_t Chip_MRT_GetIdleChannelShifted(void) -{ - return (uint8_t) (Chip_MRT_GetIdleChannel() >> 4); -} - -/** - * @brief Returns the interrupt pending status for all MRT channels - * @return IRQ pending channel bitfield(bit 0 = MRT0, bit 1 = MRT1, etc.) - */ -STATIC INLINE uint32_t Chip_MRT_GetIntPending(void) -{ - return LPC_MRT->IRQ_FLAG; -} - -/** - * @brief Returns the interrupt pending status for a singel MRT channel - * @param ch : Channel to check pending interrupt status for - * @return IRQ pending channel number - */ -STATIC INLINE bool Chip_MRT_GetIntPendingByChannel(uint8_t ch) -{ - return (bool) (((LPC_MRT->IRQ_FLAG >> ch) & 1) != 0); -} - -/** - * @brief Clears the interrupt pending status for one or more MRT channels - * @param mask : Channels to clear (bit 0 = MRT0, bit 1 = MRT1, etc.) - * @return Nothing - * @note Use this function to clear multiple interrupt pending states in - * a single call via the IRQ_FLAG register. Performs the same function for - * all MRT channels in a single call as the Chip_MRT_IntClear() does for a - * single channel. - */ -STATIC INLINE void Chip_MRT_ClearIntPending(uint32_t mask) -{ - LPC_MRT->IRQ_FLAG = mask; -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __MRT_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pinint_5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pinint_5410x.c deleted file mode 100644 index 6b3d380c199..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pinint_5410x.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * @brief LPC5410X Pin Interrupt and Pattern Match Registers and driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Set source for pattern match engine */ -void Chip_PININT_SetPatternMatchSrc(LPC_PIN_INT_T *pPININT, - Chip_PININT_SELECT_T channelNum, - Chip_PININT_BITSLICE_T sliceNum) -{ - uint32_t pmsrc_reg; - - /* Source source for pattern matching */ - pmsrc_reg = pPININT->PMSRC & ~(PININT_SRC_BITSOURCE_MASK << (PININT_SRC_BITSOURCE_START + (sliceNum * 3))); - pPININT->PMSRC = pmsrc_reg | (channelNum << (PININT_SRC_BITSOURCE_START + (sliceNum * 3))); -} - -/* Configure Pattern match engine */ -void Chip_PININT_SetPatternMatchConfig(LPC_PIN_INT_T *pPININT, Chip_PININT_BITSLICE_T sliceNum, - Chip_PININT_BITSLICE_CFG_T slice_cfg, bool end_point) -{ - uint32_t pmcfg_reg; - - /* Configure bit slice configuration */ - pmcfg_reg = pPININT->PMCFG & ~(PININT_SRC_BITCFG_MASK << (PININT_SRC_BITCFG_START + (sliceNum * 3))); - pPININT->PMCFG = pmcfg_reg | (slice_cfg << (PININT_SRC_BITCFG_START + (sliceNum * 3))); - - /* If end point is true, enable the bits */ - if (end_point == true) { - /* By default slice 7 is final component */ - if (sliceNum != PININTBITSLICE7) { - pPININT->PMCFG |= (0x1 << sliceNum); - } - } -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pinint_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pinint_5410x.h deleted file mode 100644 index 668860a10ee..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pinint_5410x.h +++ /dev/null @@ -1,413 +0,0 @@ -/* - * @brief LPC5410X Pin Interrupt and Pattern Match Registers and driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __PININT_5410X_H_ -#define __PININT_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup PININT_5410X CHIP: LPC5410X Pin Interrupt and Pattern Match driver - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/** - * @brief LPC5410X Pin Interrupt and Pattern Match register block structure - */ -typedef struct { /*!< PIN_INT Structure */ - __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */ - __IO uint32_t IENR; /*!< Pin Interrupt Enable (Rising) register */ - __IO uint32_t SIENR; /*!< Set Pin Interrupt Enable (Rising) register */ - __IO uint32_t CIENR; /*!< Clear Pin Interrupt Enable (Rising) register */ - __IO uint32_t IENF; /*!< Pin Interrupt Enable Falling Edge / Active Level register */ - __IO uint32_t SIENF; /*!< Set Pin Interrupt Enable Falling Edge / Active Level register */ - __IO uint32_t CIENF; /*!< Clear Pin Interrupt Enable Falling Edge / Active Level address */ - __IO uint32_t RISE; /*!< Pin Interrupt Rising Edge register */ - __IO uint32_t FALL; /*!< Pin Interrupt Falling Edge register */ - __IO uint32_t IST; /*!< Pin Interrupt Status register */ - __IO uint32_t PMCTRL; /*!< GPIO pattern match interrupt control register */ - __IO uint32_t PMSRC; /*!< GPIO pattern match interrupt bit-slice source register */ - __IO uint32_t PMCFG; /*!< GPIO pattern match interrupt bit slice configuration register */ -} LPC_PIN_INT_T; - -/** - * LPC5410X Pin Interrupt and Pattern match engine register - * bit fields and macros - */ - -/* PININT Interrupt Mode Mask */ -#define PININT_ISEL_PMODE_MASK ((uint32_t) 0x00FF) - -/* PININT Pattern Match Control Register Mask */ -#define PININT_PMCTRL_MASK ((uint32_t) 0xFF000003) - -/* PININT interrupt control register */ -#define PININT_PMCTRL_PMATCH_SEL (1 << 0) -#define PININT_PMCTRL_RXEV_ENA (1 << 1) - -/* PININT Bit slice source register bits */ -#define PININT_SRC_BITSOURCE_START 8 -#define PININT_SRC_BITSOURCE_MASK 7 - -/* PININT Bit slice configuration register bits */ -#define PININT_SRC_BITCFG_START 8 -#define PININT_SRC_BITCFG_MASK 7 - -/** - * LPC5410X Pin Interrupt channel values - */ -#define PININTCH0 (1 << 0) -#define PININTCH1 (1 << 1) -#define PININTCH2 (1 << 2) -#define PININTCH3 (1 << 3) -#define PININTCH4 (1 << 4) -#define PININTCH5 (1 << 5) -#define PININTCH6 (1 << 6) -#define PININTCH7 (1 << 7) -#define PININTCH(ch) (1 << (ch)) - -/** - * LPC5410X Pin Interrupt select enum values - */ -typedef enum Chip_PININT_SELECT { - PININTSELECT0 = 0, - PININTSELECT1 = 1, - PININTSELECT2 = 2, - PININTSELECT3 = 3, - PININTSELECT4 = 4, - PININTSELECT5 = 5, - PININTSELECT6 = 6, - PININTSELECT7 = 7 -} Chip_PININT_SELECT_T; - -/** - * LPC5410X Pin Matching Interrupt bit slice enum values - */ -typedef enum Chip_PININT_BITSLICE { - PININTBITSLICE0 = 0, /*!< PININT Bit slice 0 */ - PININTBITSLICE1 = 1, /*!< PININT Bit slice 1 */ - PININTBITSLICE2 = 2, /*!< PININT Bit slice 2 */ - PININTBITSLICE3 = 3, /*!< PININT Bit slice 3 */ - PININTBITSLICE4 = 4, /*!< PININT Bit slice 4 */ - PININTBITSLICE5 = 5, /*!< PININT Bit slice 5 */ - PININTBITSLICE6 = 6, /*!< PININT Bit slice 6 */ - PININTBITSLICE7 = 7 /*!< PININT Bit slice 7 */ -} Chip_PININT_BITSLICE_T; - -/** - * LPC5410X Pin Matching Interrupt bit slice configuration enum values - */ -typedef enum Chip_PININT_BITSLICE_CFG { - PININT_PATTERNCONST1 = 0x0, /*!< Contributes to product term match */ - PININT_PATTERNRISING = 0x1, /*!< Rising edge */ - PININT_PATTERNFALLING = 0x2, /*!< Falling edge */ - PININT_PATTERNRISINGORFALLING = 0x3, /*!< Rising or Falling edge */ - PININT_PATTERNHIGH = 0x4, /*!< High level */ - PININT_PATTERNLOW = 0x5, /*!< Low level */ - PININT_PATTERNCONST0 = 0x6, /*!< Never contributes for match */ - PININT_PATTERNEVENT = 0x7 /*!< Match occurs on event */ -} Chip_PININT_BITSLICE_CFG_T; - -/** - * @brief Initialize Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @return Nothing - * @note This function should be used after the Chip_GPIO_Init() function. - */ -STATIC INLINE void Chip_PININT_Init(LPC_PIN_INT_T *pPININT) -{ - Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_PINT); - Chip_SYSCON_PeriphReset(RESET_PINT); -} - -/** - * @brief De-Initialize Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @return Nothing - */ -STATIC INLINE void Chip_PININT_DeInit(LPC_PIN_INT_T *pPININT) -{ - Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_PINT); -} - -/** - * @brief Configure the pins as edge sensitive in Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @param pins : Pins (ORed value of PININTCH*) - * @return Nothing - */ -STATIC INLINE void Chip_PININT_SetPinModeEdge(LPC_PIN_INT_T *pPININT, uint32_t pins) -{ - pPININT->ISEL = (pPININT->ISEL & PININT_ISEL_PMODE_MASK) & ~pins; -} - -/** - * @brief Configure the pins as level sensitive in Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @param pins : Pins (ORed value of PININTCH*) - * @return Nothing - */ -STATIC INLINE void Chip_PININT_SetPinModeLevel(LPC_PIN_INT_T *pPININT, uint32_t pins) -{ - pPININT->ISEL = (pPININT->ISEL & PININT_ISEL_PMODE_MASK) | pins; -} - -/** - * @brief Return current PININT edge or level sensitive interrupt selection state - * @param pPININT : The base address of Pin interrupt block - * @return A bifield containing the edge/level sensitive selection for each - * interrupt. Bit 0 = PININT0, 1 = PININT1, etc. - * For each bit, a 0 means the edge sensitive interrupt is selected, while a 1 - * means the level sensitive interrupt is selected. - */ -STATIC INLINE uint32_t Chip_PININT_GetPinMode(LPC_PIN_INT_T *pPININT) -{ - return pPININT->ISEL & PININT_ISEL_PMODE_MASK; -} - -/** - * @brief Return current PININT rising edge or level interrupt enable state - * @param pPININT : The base address of Pin interrupt block - * @return A bifield containing the rising edge/level enable for each - * interrupt. Bit 0 = PININT0, 1 = PININT1, etc. - * For each bit, a 0 means the rising edge/level interrupt is disabled, while a 1 - * means it's enabled. - */ -STATIC INLINE uint32_t Chip_PININT_GetHighEnabled(LPC_PIN_INT_T *pPININT) -{ - return pPININT->IENR; -} - -/** - * @brief Enable rising edge/level PININT interrupts for pins - * @param pPININT : The base address of Pin interrupt block - * @param pins : Pins to enable (ORed value of PININTCH*) - * @return Nothing - */ -STATIC INLINE void Chip_PININT_EnableIntHigh(LPC_PIN_INT_T *pPININT, uint32_t pins) -{ - pPININT->SIENR = pins; -} - -/** - * @brief Disable rising edge/level PININT interrupts for pins - * @param pPININT : The base address of Pin interrupt block - * @param pins : Pins to disable (ORed value of PININTCH*) - * @return Nothing - */ -STATIC INLINE void Chip_PININT_DisableIntHigh(LPC_PIN_INT_T *pPININT, uint32_t pins) -{ - pPININT->CIENR = pins; -} - -/** - * @brief Return current PININT falling edge or level interrupt active level enable state - * @param pPININT : The base address of Pin interrupt block - * @return A bifield containing the falling edge/level interrupt active level enable for each - * interrupt. Bit 0 = PININT0, 1 = PININT1, etc. - * For each bit, a 0 means the falling edge is disabled/level interrupt active low is enabled, while a 1 - * means the falling edge is enabled/level interrupt active high is enabled. - */ -STATIC INLINE uint32_t Chip_PININT_GetLowEnabled(LPC_PIN_INT_T *pPININT) -{ - return pPININT->IENF; -} - -/** - * @brief Enable falling edge/level active level PININT interrupts for pins - * @param pPININT : The base address of Pin interrupt block - * @param pins : Pins to enable (ORed value of PININTCH*) - * @return Nothing - */ -STATIC INLINE void Chip_PININT_EnableIntLow(LPC_PIN_INT_T *pPININT, uint32_t pins) -{ - pPININT->SIENF = pins; -} - -/** - * @brief Disable low edge/level active level PININT interrupts for pins - * @param pPININT : The base address of Pin interrupt block - * @param pins : Pins to disable (ORed value of PININTCH*) - * @return Nothing - */ -STATIC INLINE void Chip_PININT_DisableIntLow(LPC_PIN_INT_T *pPININT, uint32_t pins) -{ - pPININT->CIENF = pins; -} - -/** - * @brief Return pin states that have a detected latched rising edge (RISE) state - * @param pPININT : The base address of Pin interrupt block - * @return PININT states (bit n = high) with a latched rise state detected - */ -STATIC INLINE uint32_t Chip_PININT_GetRiseStates(LPC_PIN_INT_T *pPININT) -{ - return pPININT->RISE; -} - -/** - * @brief Clears pin states that had a latched rising edge (RISE) state - * @param pPININT : The base address of Pin interrupt block - * @param pins : Pins with latched states to clear - * @return Nothing - */ -STATIC INLINE void Chip_PININT_ClearRiseStates(LPC_PIN_INT_T *pPININT, uint32_t pins) -{ - pPININT->RISE = pins; -} - -/** - * @brief Return pin states that have a detected latched falling edge (FALL) state - * @param pPININT : The base address of Pin interrupt block - * @return PININT states (bit n = high) with a latched rise state detected - */ -STATIC INLINE uint32_t Chip_PININT_GetFallStates(LPC_PIN_INT_T *pPININT) -{ - return pPININT->FALL; -} - -/** - * @brief Clears pin states that had a latched falling edge (FALL) state - * @param pPININT : The base address of Pin interrupt block - * @param pins : Pins with latched states to clear - * @return Nothing - */ -STATIC INLINE void Chip_PININT_ClearFallStates(LPC_PIN_INT_T *pPININT, uint32_t pins) -{ - pPININT->FALL = pins; -} - -/** - * @brief Get interrupt status from Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @return Interrupt status (bit n for PININTn = high means interrupt ie pending) - */ -STATIC INLINE uint32_t Chip_PININT_GetIntStatus(LPC_PIN_INT_T *pPININT) -{ - return pPININT->IST; -} - -/** - * @brief Clear interrupt status in Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @param pins : Pin interrupts to clear (ORed value of PININTCH*) - * @return Nothing - */ -STATIC INLINE void Chip_PININT_ClearIntStatus(LPC_PIN_INT_T *pPININT, uint32_t pins) -{ - pPININT->IST = pins; -} - -/** - * @brief Set source for pattern match in Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @param channelNum : PININT channel number (From 0 to 7) - * @param sliceNum : PININT slice number - * @return Nothing - */ -void Chip_PININT_SetPatternMatchSrc(LPC_PIN_INT_T *pPININT, - Chip_PININT_SELECT_T channelNum, - Chip_PININT_BITSLICE_T sliceNum); - -/** - * @brief Configure the pattern matcch in Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @param sliceNum : PININT slice number - * @param slice_cfg : PININT slice configuration value (enum Chip_PININT_BITSLICE_CFG_T) - * @param end_point : If true, current slice is final component - * @return Nothing - */ -void Chip_PININT_SetPatternMatchConfig(LPC_PIN_INT_T *pPININT, Chip_PININT_BITSLICE_T sliceNum, - Chip_PININT_BITSLICE_CFG_T slice_cfg, bool end_point); - -/** - * @brief Enable pattern match interrupts in Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @return Nothing - */ -STATIC INLINE void Chip_PININT_EnablePatternMatch(LPC_PIN_INT_T *pPININT) -{ - pPININT->PMCTRL = (pPININT->PMCTRL & PININT_PMCTRL_MASK) | PININT_PMCTRL_PMATCH_SEL; -} - -/** - * @brief Disable pattern match interrupts in Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @return Nothing - */ -STATIC INLINE void Chip_PININT_DisablePatternMatch(LPC_PIN_INT_T *pPININT) -{ - pPININT->PMCTRL = (pPININT->PMCTRL & PININT_PMCTRL_MASK) & ~PININT_PMCTRL_PMATCH_SEL; -} - -/** - * @brief Enable RXEV output in Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @return Nothing - */ -STATIC INLINE void Chip_PININT_EnablePatternMatchRxEv(LPC_PIN_INT_T *pPININT) -{ - pPININT->PMCTRL = (pPININT->PMCTRL & PININT_PMCTRL_MASK) | PININT_PMCTRL_RXEV_ENA; -} - -/** - * @brief Disable RXEV output in Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @return Nothing - */ -STATIC INLINE void Chip_PININT_DisablePatternMatchRxEv(LPC_PIN_INT_T *pPININT) -{ - pPININT->PMCTRL = (pPININT->PMCTRL & PININT_PMCTRL_MASK) & ~PININT_PMCTRL_RXEV_ENA; -} - -/** - * @brief Return pattern match state - * @param pPININT : The base address of Pin interrupt block - * @return 8 bit pattern match state, where a 1 in any bit indicates that - * the corresponding product term has matched by the current state - * of its inputs. - */ -STATIC INLINE uint32_t Chip_PININT_GetPatternMatchState(LPC_PIN_INT_T *pPININT) -{ - return pPININT->PMCTRL >> 24; -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __PININT_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pintable_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pintable_5410x.h deleted file mode 100644 index ab7119485ca..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pintable_5410x.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * @brief LPC5410x enhanced boot block - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __PINTABLE_5410X_H_ -#define __PINTABLE_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup PINTAB_5410X CHIP: LPC5410X Enhanced boot block support - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/** - * @brief LPC5410X Pin table structure used for enhanced boot block support - */ -struct PINTABLE { - /* pin table marker: Should be 0xFEEDA5A5 */ - uint32_t marker; - /* img_type: - 0 = Normal image check IRQ line to halt boot - 1 = Wait for AP to send SH_CMD_BOOT command - 2 = Boot image with no AP checks - 3 = No CRC or AP checks needed. Used during development */ - uint8_t img_type; - /* ifSel: Interface selection for host - (0,=AUTODETECT, 1=I2C0, 2=I2C1, 3=I2C2, 4=SPI0, 5=SPI1) */ - uint8_t ifSel; - /* hostIrqPortPin: Host IRQ port (bits 7:5) and pins (bits 4:0) */ - uint8_t hostIrqPortPin; - /* hostMisoPortPin: SPI MISO port (bits 7:5) and pins (bits 4:0) */ - uint8_t hostMisoPortPin; - /* hostMosiPortPin: SPI MOSI port (bits 7:5) and pins (bits 4:0) */ - uint8_t hostMosiPortPin; - /* hostSselPortPin: SPI SEL port (bits 7:5) and pins (bits 4:0) */ - uint8_t hostSselPortPin; - /* hostSckPortPin: SPI SCK port (bits 7:5) and pins (bits 4:0) */ - uint8_t hostSckPortPin; - /* xorVal: XOR value of the 7 bytes above */ - uint8_t xorVal; - /* CRC32 length and value fields */ - uint32_t crc32_len; - uint32_t crc32_val; - /* Application image version number */ - uint32_t version; -}; - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __PINTAB_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pll_5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pll_5410x.c deleted file mode 100644 index 242bed455f9..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pll_5410x.c +++ /dev/null @@ -1,928 +0,0 @@ -/* - * @brief LPC5410X PLL driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -#define NVALMAX (0x100) -#define PVALMAX (0x20) -#define MVALMAX (0x8000) - -/* SYS PLL related bit fields */ -#define SYS_PLL_SELR(d) (((d) & 0xf) << 0) /*!< Bandwidth select R value */ -#define SYS_PLL_SELI(d) (((d) & 0x3f) << 4) /*!< Bandwidth select I value */ -#define SYS_PLL_SELP(d) (((d) & 0x1f) << 10) /*!< Bandwidth select P value */ -#define SYS_PLL_BYPASS (1 << 15) /*!< Enable PLL bypass */ -#define SYS_PLL_BYPASSCCODIV2 (1 << 16) /*!< Enable bypass of extra divider by 2 */ -#define SYS_PLL_UPLIMOFF (1 << 17) /*!< Enable spread spectrum/fractional mode */ -#define SYS_PLL_BANDSEL (1 << 18) /*!< Enable MDEC control */ -#define SYS_PLL_DIRECTI (1 << 19) /*!< PLL0 direct input enable */ -#define SYS_PLL_DIRECTO (1 << 20) /*!< PLL0 direct output enable */ - -/* #define FRAC_BITS_SELI (8) // For retaining fractions in divisions*/ -#define PLL_SSCG0_MDEC_VAL_P (0) /* MDEC is in bits 16 downto 0*/ -#define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) /* NDEC is in bits 9 downto 0*/ -#define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0*/ -#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P) -#define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0*/ -#define PLL_PDEC_VAL_M (0x3FFUL << PLL_PDEC_VAL_P) - -#define PLL_MIN_CCO_FREQ_MHZ (75000000) -#define PLL_MAX_CCO_FREQ_MHZ (150000000) -#define PLL_LOWER_IN_LIMIT (4000) /*!< Minimum PLL input rate */ -#define PLL_MIN_IN_SSMODE (2000000) -#define PLL_MAX_IN_SSMODE (4000000) - -/* Middle of the range values for spread-spectrum*/ -#define PLL_SSCG_MF_FREQ_VALUE 4 -#define PLL_SSCG_MC_COMP_VALUE 2 -#define PLL_SSCG_MR_DEPTH_VALUE 4 -#define PLL_SSCG_DITHER_VALUE 0 - -/* pll SYSPLLCTRL Bits*/ -#define SYSCON_SYSPLLCTRL_SELR_P 0 -#define SYSCON_SYSPLLCTRL_SELR_M (0xFUL << SYSCON_SYSPLLCTRL_SELR_P) -#define SYSCON_SYSPLLCTRL_SELI_P 4 -#define SYSCON_SYSPLLCTRL_SELI_M (0x3FUL << SYSCON_SYSPLLCTRL_SELI_P) -#define SYSCON_SYSPLLCTRL_SELP_P 10 -#define SYSCON_SYSPLLCTRL_SELP_M (0x1FUL << SYSCON_SYSPLLCTRL_SELP_P) -#define SYSCON_SYSPLLCTRL_BYPASS_P 15 /* sys_pll150_ctrl*/ -#define SYSCON_SYSPLLCTRL_BYPASS (1UL << SYSCON_SYSPLLCTRL_BYPASS_P) -#define SYSCON_SYSPLLCTRL_BYPASS_FBDIV2_P 16 -#define SYSCON_SYSPLLCTRL_BYPASS_FBDIV2 (1UL << SYSCON_SYSPLLCTRL_BYPASS_FBDIV2_P) -#define SYSCON_SYSPLLCTRL_UPLIMOFF_P 17 -#define SYSCON_SYSPLLCTRL_UPLIMOFF (1UL << SYSCON_SYSPLLCTRL_UPLIMOFF_P) -#define SYSCON_SYSPLLCTRL_BANDSEL_SSCGREG_N_P 18 -#define SYSCON_SYSPLLCTRL_BANDSEL_SSCGREG_N (1UL << SYSCON_SYSPLLCTRL_BANDSEL_SSCGREG_N_P) -#define SYSCON_SYSPLLCTRL_DIRECTI_P 19 -#define SYSCON_SYSPLLCTRL_DIRECTI (1UL << SYSCON_SYSPLLCTRL_DIRECTI_P) -#define SYSCON_SYSPLLCTRL_DIRECTO_P 20 -#define SYSCON_SYSPLLCTRL_DIRECTO (1UL << SYSCON_SYSPLLCTRL_DIRECTO_P) - -#define SYSCON_SYSPLLSTAT_LOCK_P 0 -#define SYSCON_SYSPLLSTAT_LOCK (1UL << SYSCON_SYSPLLSTAT_LOCK_P) - -#define PLL_CTRL_BYPASS_P 15 /* sys_pll150_ctrl*/ -#define PLL_CTRL_BYPASS_FBDIV2_P 16 -#define PLL_CTRL_UPLIMOFF_P 17 -#define PLL_CTRL_BANDSEL_SSCGREG_N_P 18 -#define PLL_CTRL_DIRECTI_P 19 -#define PLL_CTRL_DIRECTO_P 20 - -#define PLL_CTRL_BYPASS (1 << PLL_CTRL_BYPASS_P) -#define PLL_CTRL_DIRECTI (1 << PLL_CTRL_DIRECTI_P) -#define PLL_CTRL_DIRECTO (1 << PLL_CTRL_DIRECTO_P) -#define PLL_CTRL_UPLIMOFF (1 << PLL_CTRL_UPLIMOFF_P) -#define PLL_CTRL_BANDSEL_SSCGREG_N (1 << PLL_CTRL_BANDSEL_SSCGREG_N_P) -#define PLL_CTRL_BYPASS_FBDIV2 (1 << PLL_CTRL_BYPASS_FBDIV2_P) - -/* SSCG control[0]*/ -/* #define PLL_SSCG0_MDEC_VAL_P 0 // MDEC is in bits 16 downto 0*/ -#define PLL_SSCG0_MREQ_P 17 -#define PLL_SSCG0_SEL_EXT_SSCG_N_P 18 -#define PLL_SSCG0_SEL_EXT_SSCG_N (1 << PLL_SSCG0_SEL_EXT_SSCG_N_P) -#define PLL_SSCG0_MREQ (1 << PLL_SSCG0_MREQ_P) - -/* SSCG control[1]*/ -#define PLL_SSCG1_MD_REQ_P 19 -#define PLL_SSCG1_MOD_PD_SSCGCLK_N_P 28 -#define PLL_SSCG1_DITHER_P 29 -#define PLL_SSCG1_MOD_PD_SSCGCLK_N (1 << PLL_SSCG1_MOD_PD_SSCGCLK_N_P) -#define PLL_SSCG1_DITHER (1 << PLL_SSCG1_DITHER_P) -#define PLL_SSCG1_MD_REQ (1 << PLL_SSCG1_MD_REQ_P) - -/* PLL NDEC reg*/ -#define PLL_NDEC_VAL_SET(value) (((unsigned long) (value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) -#define PLL_NDEC_NREQ_P 10 -#define PLL_NDEC_NREQ (1 << PLL_NDEC_NREQ_P) - -/* PLL PDEC reg*/ -#define PLL_PDEC_VAL_SET(value) (((unsigned long) (value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M) -#define PLL_PDEC_PREQ_P 7 -#define PLL_PDEC_PREQ (1 << PLL_PDEC_PREQ_P) - -/* SSCG control[0]*/ -#define PLL_SSCG0_MDEC_VAL_SET(value) (((unsigned long) (value) << PLL_SSCG0_MDEC_VAL_P) & PLL_SSCG0_MDEC_VAL_M) -#define PLL_SSCG0_MREQ_P 17 -#define PLL_SSCG0_MREQ (1 << PLL_SSCG0_MREQ_P) -#define PLL_SSCG0_SEL_EXT_SSCG_N_P 18 -#define PLL_SSCG0_SEL_EXT_SSCG_N (1 << PLL_SSCG0_SEL_EXT_SSCG_N_P) - -/* SSCG control[1]*/ -#define PLL_SSCG1_MD_FRACT_P 0 -#define PLL_SSCG1_MD_INT_P 11 -#define PLL_SSCG1_MF_P 20 -#define PLL_SSCG1_MC_P 26 -#define PLL_SSCG1_MR_P 23 - -#define PLL_SSCG1_MD_FRACT_M (0x7FFUL << PLL_SSCG1_MD_FRACT_P) -#define PLL_SSCG1_MD_INT_M (0xFFUL << PLL_SSCG1_MD_INT_P) -#define PLL_SSCG1_MF_M (0x7UL << PLL_SSCG1_MF_P) -#define PLL_SSCG1_MC_M (0x3UL << PLL_SSCG1_MC_P) -#define PLL_SSCG1_MR_M (0x7UL << PLL_SSCG1_MR_P) - -#define PLL_SSCG1_MD_FRACT_SET(value) (((unsigned long) (value) << \ - PLL_SSCG1_MD_FRACT_P) & PLL_SSCG1_MD_FRACT_M) -#define PLL_SSCG1_MD_INT_SET(value) (((unsigned long) (value) << \ - PLL_SSCG1_MD_INT_P) & PLL_SSCG1_MD_INT_M) -/* -#define PLL_SSCG1_MF_SET(value) (((unsigned long) (value) << \ - PLL_SSCG1_MF_P) & PLL_SSCG1_MF_M) -#define PLL_SSCG1_MC_SET(value) (((unsigned long) (value) << \ - PLL_SSCG1_MC_P) & PLL_SSCG1_MC_M) -#define PLL_SSCG1_MR_SET(value) (((unsigned long) (value) << \ - PLL_SSCG1_MR_P) & PLL_SSCG1_MR_M) -*/ - -/* Middle of the range values for spread-spectrum*/ - -#define PLL0_SSCG_MF_FREQ_VALUE 4 -#define PLL0_SSCG_MC_COMP_VALUE 2 -#define PLL0_SSCG_MR_DEPTH_VALUE 4 -#define PLL0_SSCG_DITHER_VALUE 0 - -#define PLL_MAX_N_DIV 0x100 - -/* Saved value of PLL output rate, computed whenever needed to save run-time - computation on each call to retrive the PLL rate. */ -static uint32_t curPllRate; - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/* Find encoded NDEC value for raw N value, max N = NVALMAX */ -static uint32_t pllEncodeN(uint32_t N) -{ - uint32_t x, i; - - /* Find NDec */ - switch (N) - { - case 0: - x = 0xFFF; - break; - - case 1: - x = 0x302; - break; - - case 2: - x = 0x202; - break; - - default: - x = 0x080; - for (i = N; i <= NVALMAX; i++) - { - x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F); - } - break; - } - - return x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P); -} - -/* Find decoded N value for raw NDEC value */ -static uint32_t pllDecodeN(uint32_t NDEC) -{ - uint32_t n, x, i; - - /* Find NDec */ - switch (NDEC) - { - case 0xFFF: - n = 0; - break; - - case 0x302: - n = 1; - break; - - case 0x202: - n = 2; - break; - - default: - x = 0x080; - n = 0xFFFFFFFF; - for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFF)); i--) - { - x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F); - if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC) - { - /* Decoded value of NDEC */ - n = i; - } - } - break; - } - - return n; -} - -/* Find encoded PDEC value for raw P value, max P = PVALMAX */ -static uint32_t pllEncodeP(uint32_t P) -{ - uint32_t x, i; - - /* Find PDec */ - switch (P) - { - case 0: - x = 0xFF; - break; - - case 1: - x = 0x62; - break; - - case 2: - x = 0x42; - break; - - default: - x = 0x10; - for (i = P; i <= PVALMAX; i++) - { - x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xF); - } - break; - } - - return x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P); -} - -/* Find decoded P value for raw PDEC value */ -static uint32_t pllDecodeP(uint32_t PDEC) -{ - uint32_t p, x, i; - - /* Find PDec */ - switch (PDEC) - { - case 0xFF: - p = 0; - break; - - case 0x62: - p = 1; - break; - - case 0x42: - p = 2; - break; - - default: - x = 0x10; - p = 0xFFFFFFFF; - for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFF)); i--) - { - x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xF); - if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC) - { - /* Decoded value of PDEC */ - p = i; - } - } - break; - } - - return p; -} - -/* Find encoded MDEC value for raw M value, max M = MVALMAX */ -static uint32_t pllEncodeM(uint32_t M) -{ - uint32_t i, x; - - /* Find MDec */ - switch (M) - { - case 0: - x = 0xFFFFF; - break; - - case 1: - x = 0x18003; - break; - - case 2: - x = 0x10003; - break; - - default: - x = 0x04000; - for (i = M; i <= MVALMAX; i++) - { - x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF); - } - break; - } - - return x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P); -} - -/* Find decoded M value for raw MDEC value */ -static uint32_t pllDecodeM(uint32_t MDEC) -{ - uint32_t m, i, x; - - /* Find MDec */ - switch (MDEC) - { - case 0xFFFFF: - m = 0; - break; - - case 0x18003: - m = 1; - break; - - case 0x10003: - m = 2; - break; - - default: - x = 0x04000; - m = 0xFFFFFFFF; - for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFF)); i--) - { - x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF); - if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC) - { - /* Decoded value of MDEC */ - m = i; - } - } - break; - } - - return m; -} - -/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ -static void pllFindSel(uint32_t M, bool bypassFBDIV2, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) -{ - /* Bypass divider? */ - if (bypassFBDIV2) - { - M = M / 2; - } - - /* bandwidth: compute selP from Multiplier */ - if (M < 60) - { - *pSelP = (M >> 1) + 1; - } - else { - *pSelP = PVALMAX - 1; - } - - /* bandwidth: compute selI from Multiplier */ - if (M > 16384) - { - *pSelI = 1; - } - else if (M > 8192) - { - *pSelI = 2; - } - else if (M > 2048) - { - *pSelI = 4; - } - else if (M >= 501) - { - *pSelI = 8; - } - else if (M >= 60) - { - *pSelI = 4 * (1024 / (M + 9)); - } - else { - *pSelI = (M & 0x3C) + 4; - } - - if (*pSelI > (SYSCON_SYSPLLCTRL_SELI_M >> SYSCON_SYSPLLCTRL_SELI_P)) - { - *pSelI = (SYSCON_SYSPLLCTRL_SELI_M >> SYSCON_SYSPLLCTRL_SELI_P); - } - - *pSelR = 0; -} - -/* Get predivider (N) from PLL NDEC setting */ -uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg) -{ - uint32_t preDiv = 1; - - /* Direct input is not used? */ - if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI) == 0) - { - /* Decode NDEC value to get (N) pre divider */ - preDiv = pllDecodeN(nDecReg & 0x3FF); - if (preDiv == 0) - { - preDiv = 1; - } - } - - /* Adjusted by 1, directi is used to bypass */ - return preDiv; -} - -/* Get postdivider (P) from PLL PDEC setting */ -uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg) -{ - uint32_t postDiv = 1; - - /* Direct input is not used? */ - if ((ctrlReg & SYS_PLL_DIRECTO) == 0) - { - /* Decode PDEC value to get (P) post divider */ - postDiv = 2 * pllDecodeP(pDecReg & 0x7F); - if (postDiv == 0) - { - postDiv = 2; - } - } - - /* Adjusted by 1, directo is used to bypass */ - return postDiv; -} - -/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ -uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg) -{ - uint32_t mMult = 1; - - /* Decode MDEC value to get (M) multiplier */ - mMult = pllDecodeM(mDecReg & 0x1FFFF); - - /* Extra divided by 2 needed? */ - if ((ctrlReg & SYSCON_SYSPLLCTRL_BYPASS_FBDIV2) == 0) - { - mMult = mMult >> 1; - } - - if (mMult == 0) - { - mMult = 1; - } - - return mMult; -} - -static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) -{ - uint32_t tmp; - - while (n != 0) - { - tmp = n; - n = m % n; - m = tmp; - } - - return m; -} - -/* Set PLL output based on desired output rate */ -static PLL_ERROR_T Chip_Clock_GetPllConfig(uint32_t finHz, uint32_t foutHz, PLL_SETUP_T *pSetup, - bool useFeedbackDiv2, bool useSS) -{ - uint32_t nDivOutHz, fccoHz, multFccoDiv; - uint32_t pllPreDivider, pllMultiplier, pllBypassFBDIV2, pllPostDivider; - uint32_t pllDirectInput, pllDirectOutput; - uint32_t pllSelP, pllSelI, pllSelR, bandsel, uplimoff; - - /* Baseline parameters (no input or output dividers) */ - pllPreDivider = 1; /* 1 implies pre-divider will be disabled */ - pllPostDivider = 0; /* 0 implies post-divider will be disabled */ - pllDirectOutput = 1; - if (useFeedbackDiv2) - { - /* Using feedback divider for M, so disable bypass */ - pllBypassFBDIV2 = 0; - } - else { - pllBypassFBDIV2 = 1; - } - multFccoDiv = (2 - pllBypassFBDIV2); - - /* Verify output rate parameter */ - if (foutHz > PLL_MAX_CCO_FREQ_MHZ) - { - /* Maximum PLL output with post divider=1 cannot go above this frequency */ - return PLL_ERROR_OUTPUT_TOO_HIGH; - } - if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1))) - { - /* Minmum PLL output with maximum post divider cannot go below this frequency */ - return PLL_ERROR_OUTPUT_TOO_LOW; - } - - /* If using SS mode, input clock needs to be between 2MHz and 4MHz */ - if (useSS) - { - /* Verify input rate parameter */ - if (finHz < PLL_MIN_IN_SSMODE) - { - /* Input clock into the PLL cannot be lower than this */ - return PLL_ERROR_INPUT_TOO_LOW; - } - - /* PLL input in SS mode must be under 4MHz */ - pllPreDivider = finHz / ((PLL_MIN_IN_SSMODE + PLL_MAX_IN_SSMODE) / 2); - if (pllPreDivider > NVALMAX) - { - return PLL_ERROR_INPUT_TOO_HIGH; - } - } - else { - /* Verify input rate parameter */ - if (finHz < PLL_LOWER_IN_LIMIT) - { - /* Input clock into the PLL cannot be lower than this */ - return PLL_ERROR_INPUT_TOO_LOW; - } - } - - /* Find the optimal CCO frequency for the output and input that - will keep it inside the PLL CCO range. This may require - tweaking the post-divider for the PLL. */ - fccoHz = foutHz; - while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) - { - /* CCO output is less than minimum CCO range, so the CCO output - needs to be bumped up and the post-divider is used to bring - the PLL output back down. */ - pllPostDivider++; - if (pllPostDivider > PVALMAX) - { - return PLL_ERROR_OUTSIDE_INTLIMIT; - } - - /* Target CCO goes up, PLL output goes down */ - fccoHz = foutHz * (pllPostDivider * 2); - pllDirectOutput = 0; - } - - /* Determine if a pre-divider is needed to get the best frequency */ - if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) - { - uint32_t a = FindGreatestCommonDivisor(fccoHz, (multFccoDiv * finHz)); - - if (a > 20000) - { - a = (multFccoDiv * finHz) / a; - if ((a != 0) && (a < PLL_MAX_N_DIV)) - { - pllPreDivider = a; - } - } - } - - /* Bypass pre-divider hardware if pre-divider is 1 */ - if (pllPreDivider > 1) - { - pllDirectInput = 0; - } - else { - pllDirectInput = 1; - } - - /* Determine PLL multipler */ - nDivOutHz = (finHz / pllPreDivider); - pllMultiplier = (fccoHz / nDivOutHz) / multFccoDiv; - - /* Find optimal values for filter */ - if (useSS == false) - { - /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ - if ((nDivOutHz * ((multFccoDiv * pllMultiplier * 2) + 1)) < (fccoHz * 2)) - { - pllMultiplier++; - } - - /* Setup filtering */ - pllFindSel(pllMultiplier, pllBypassFBDIV2, &pllSelP, &pllSelI, &pllSelR); - bandsel = 1; - uplimoff = 0; - - /* Get encoded value for M (mult) and use manual filter, disable SS mode */ - pSetup->SYSPLLSSCTRL[0] = (PLL_SSCG0_MDEC_VAL_SET(pllEncodeM(pllMultiplier)) | - (1 << PLL_SSCG0_SEL_EXT_SSCG_N_P)); - - /* Power down SSC, not used */ - pSetup->SYSPLLSSCTRL[1] = PLL_SSCG1_MOD_PD_SSCGCLK_N; - } - else { - uint64_t fc; - - /* Filtering will be handled by SSC */ - pllSelR = pllSelI = pllSelP = 0; - bandsel = 0; - uplimoff = 1; - - /* The PLL multiplier will get very close and slightly under the - desired target frequency. A small fractional component can be - added to fine tune the frequency upwards to the target. */ - fc = ((uint64_t) (fccoHz % (multFccoDiv * nDivOutHz)) << 11) / (multFccoDiv * nDivOutHz); - - /* MDEC set by SSC */ - pSetup->SYSPLLSSCTRL[0] = 0; - - /* Set multiplier */ - pSetup->SYSPLLSSCTRL[1] = PLL_SSCG1_MD_INT_SET(pllMultiplier) | - PLL_SSCG1_MD_FRACT_SET((uint32_t) fc); - } - - /* Get encoded values for N (prediv) and P (postdiv) */ - pSetup->SYSPLLNDEC = PLL_NDEC_VAL_SET(pllEncodeN(pllPreDivider)); - pSetup->SYSPLLPDEC = PLL_PDEC_VAL_SET(pllEncodeP(pllPostDivider)); - - /* PLL control */ - pSetup->SYSPLLCTRL = - (pllSelR << SYSCON_SYSPLLCTRL_SELR_P) | /* Filter coefficient */ - (pllSelI << SYSCON_SYSPLLCTRL_SELI_P) | /* Filter coefficient */ - (pllSelP << SYSCON_SYSPLLCTRL_SELP_P) | /* Filter coefficient */ - (0 << SYSCON_SYSPLLCTRL_BYPASS_P) | /* PLL bypass mode disabled */ - (pllBypassFBDIV2 << SYSCON_SYSPLLCTRL_BYPASS_FBDIV2_P) | /* Extra M / 2 divider? */ - (uplimoff << SYSCON_SYSPLLCTRL_UPLIMOFF_P) | /* SS/fractional mode disabled */ - (bandsel << SYSCON_SYSPLLCTRL_BANDSEL_SSCGREG_N_P) | /* Manual bandwidth selection enabled */ - (pllDirectInput << SYSCON_SYSPLLCTRL_DIRECTI_P) | /* Bypass pre-divider? */ - (pllDirectOutput << SYSCON_SYSPLLCTRL_DIRECTO_P); /* Bypass post-divider? */ - - return PLL_ERROR_SUCCESS; -} - -/* Update local PLL rate variable */ -static void Chip_Clock_GetSystemPLLOutFromSetupUpdate(PLL_SETUP_T *pSetup) -{ - curPllRate = Chip_Clock_GetSystemPLLOutFromSetup(pSetup); -} - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Return System PLL input clock rate */ -uint32_t Chip_Clock_GetSystemPLLInClockRate(void) -{ - uint32_t clkRate = 0; - - switch ((CHIP_SYSCON_PLLCLKSRC_T) (LPC_SYSCON->SYSPLLCLKSEL & 0x3)) - { - case SYSCON_PLLCLKSRC_IRC: - clkRate = Chip_Clock_GetIntOscRate(); - break; - - case SYSCON_PLLCLKSRC_CLKIN: - clkRate = Chip_Clock_GetExtClockInRate(); - break; - - case SYSCON_PLLCLKSRC_WDTOSC: - clkRate = Chip_Clock_GetWDTOSCRate(); - break; - - case SYSCON_PLLCLKSRC_RTC: - clkRate = Chip_Clock_GetRTCOscRate(); - break; - } - - return clkRate; -} - -/* Return System PLL output clock rate from setup structure */ -uint32_t Chip_Clock_GetSystemPLLOutFromSetup(PLL_SETUP_T *pSetup) -{ - uint32_t prediv, postdiv, mMult, inPllRate; - uint64_t workRate; - - inPllRate = Chip_Clock_GetSystemPLLInClockRate(); - if ((pSetup->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_P) == 0) - { - /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ - prediv = findPllPreDiv(pSetup->SYSPLLCTRL, pSetup->SYSPLLNDEC); - postdiv = findPllPostDiv(pSetup->SYSPLLCTRL, pSetup->SYSPLLPDEC); - - /* Adjust input clock */ - inPllRate = inPllRate / prediv; - - /* If using the SS, use the multiplier */ - if (pSetup->SYSPLLSSCTRL[1] & PLL_SSCG1_MOD_PD_SSCGCLK_N) - { - /* MDEC used for rate */ - mMult = findPllMMult(pSetup->SYSPLLCTRL, pSetup->SYSPLLSSCTRL[0]); - workRate = (uint64_t) inPllRate * (uint64_t) mMult; - } - else { - uint64_t fract; - - /* SS multipler used for rate */ - mMult = (pSetup->SYSPLLSSCTRL[1] & PLL_SSCG1_MD_INT_M) >> PLL_SSCG1_MD_INT_P; - workRate = (uint64_t) inPllRate * (uint64_t) mMult; - - /* Adjust by fractional */ - fract = (uint64_t) (pSetup->SYSPLLSSCTRL[1] & PLL_SSCG1_MD_FRACT_M) >> PLL_SSCG1_MD_FRACT_P; - workRate = workRate + ((inPllRate * fract) / 0x7FF); - } - - workRate = workRate / ((uint64_t) postdiv); - } - else { - /* In bypass mode */ - workRate = (uint64_t) inPllRate; - } - - return (uint32_t) workRate; -} - -/* Return System PLL output clock rate */ -uint32_t Chip_Clock_GetSystemPLLOutClockRate(bool recompute) -{ - PLL_SETUP_T Setup; - uint32_t rate; - - if ((recompute) || (curPllRate == 0)) - { - Setup.SYSPLLCTRL = LPC_SYSCON->SYSPLLCTRL; - Setup.SYSPLLNDEC = LPC_SYSCON->SYSPLLNDEC; - Setup.SYSPLLPDEC = LPC_SYSCON->SYSPLLPDEC; - Setup.SYSPLLSSCTRL[0] = LPC_SYSCON->SYSPLLSSCTRL[0]; - Setup.SYSPLLSSCTRL[1] = LPC_SYSCON->SYSPLLSSCTRL[1]; - - Chip_Clock_GetSystemPLLOutFromSetupUpdate(&Setup); - } - - rate = curPllRate; - - return rate; -} - -/* Enables and disables PLL bypass mode */ -void Chip_Clock_SetBypassPLL(bool bypass) -{ - if (bypass) - { - LPC_SYSCON->SYSPLLCTRL |= SYSCON_SYSPLLCTRL_BYPASS_P; - } - else { - LPC_SYSCON->SYSPLLCTRL &= ~SYSCON_SYSPLLCTRL_BYPASS_P; - } -} - -/* Set PLL output based on the passed PLL setup data */ -PLL_ERROR_T Chip_Clock_SetupPLLData(PLL_CONFIG_T *pControl, PLL_SETUP_T *pSetup) -{ - uint32_t inRate; - bool useSS = (bool) ((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0); - PLL_ERROR_T pllError; - - /* Determine input rate for the PLL */ - if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0) - { - inRate = pControl->InputRate; - } - else { - inRate = Chip_Clock_GetSystemPLLInClockRate(); - } - - /* PLL flag options */ - pllError = Chip_Clock_GetPllConfig(inRate, pControl->desiredRate, pSetup, false, useSS); - if ((useSS) && (pllError == PLL_ERROR_SUCCESS)) - { - /* If using SS mode, then some tweaks are made to the generated setup */ - pSetup->SYSPLLSSCTRL[1] |= (uint32_t) pControl->ss_mf | (uint32_t) pControl->ss_mr | - (uint32_t) pControl->ss_mc; - if (pControl->mfDither) - { - pSetup->SYSPLLSSCTRL[1] |= PLL_SSCG1_DITHER; - } - } - - return pllError; -} - -/* Set PLL output from PLL setup structure */ -PLL_ERROR_T Chip_Clock_SetupSystemPLLPrec(PLL_SETUP_T *pSetup) -{ - /* Power off PLL during setup changes */ - Chip_SYSCON_PowerDown(SYSCON_PDRUNCFG_PD_SYS_PLL); - - /* Write PLL setup data */ - LPC_SYSCON->SYSPLLCTRL = pSetup->SYSPLLCTRL; - LPC_SYSCON->SYSPLLNDEC = pSetup->SYSPLLNDEC; - LPC_SYSCON->SYSPLLNDEC = pSetup->SYSPLLNDEC | PLL_NDEC_NREQ;/* latch */ - LPC_SYSCON->SYSPLLPDEC = pSetup->SYSPLLPDEC; - LPC_SYSCON->SYSPLLPDEC = pSetup->SYSPLLPDEC | PLL_PDEC_PREQ;/* latch */ - LPC_SYSCON->SYSPLLSSCTRL[0] = pSetup->SYSPLLSSCTRL[0]; - LPC_SYSCON->SYSPLLSSCTRL[0] = pSetup->SYSPLLSSCTRL[0] | PLL_SSCG0_MREQ; /* latch */ - LPC_SYSCON->SYSPLLSSCTRL[1] = pSetup->SYSPLLSSCTRL[1]; - LPC_SYSCON->SYSPLLSSCTRL[1] = pSetup->SYSPLLSSCTRL[1] | PLL_SSCG1_MD_REQ; /* latch */ - - /* Flags for lock or power on */ - if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0) - { - Chip_SYSCON_PowerUp(SYSCON_PDRUNCFG_PD_SYS_PLL); - } - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0) - { - while (Chip_Clock_IsSystemPLLLocked() == false) - {} - } - - /* Update current programmed PLL rate var */ - Chip_Clock_GetSystemPLLOutFromSetupUpdate(pSetup); - - /* System voltage adjustment, occurs prior to setting main system clock */ - if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0) - { - Chip_POWER_SetVoltage(POWER_LOW_POWER_MODE, curPllRate); - } - - return PLL_ERROR_SUCCESS; -} - -/* Set System PLL clock based on the input frequency and multiplier */ -void Chip_Clock_SetupSystemPLL(uint32_t multiply_by, uint32_t input_freq) -{ - uint32_t cco_freq = input_freq * multiply_by; - uint32_t pdec = 1; - uint32_t selr; - uint32_t seli; - uint32_t selp; - uint32_t mdec, ndec; - - uint32_t directo = SYS_PLL_DIRECTO; - - while (cco_freq < 75000000) - { - multiply_by <<= 1; /* double value in each iteration */ - pdec <<= 1; /* correspondingly double pdec to cancel effect of double msel */ - cco_freq = input_freq * multiply_by; - } - selr = 0; - seli = (multiply_by & 0x3c) + 4; - selp = (multiply_by >> 1) + 1; - - if (pdec > 1) - { - directo = 0; /* use post divider */ - pdec = pdec / 2; /* Account for minus 1 encoding */ - /* Translate P value */ - pdec = (pdec == 1) ? 0x62 : /* 1 * 2 */ - (pdec == 2) ? 0x42 : /* 2 * 2 */ - (pdec == 4) ? 0x02 : /* 4 * 2 */ - (pdec == 8) ? 0x0b : /* 8 * 2 */ - (pdec == 16) ? 0x11 : /* 16 * 2 */ - (pdec == 32) ? 0x08 : 0x08; /* 32 * 2 */ - } - - /* Only support values of 2 to 16 (to keep driver simple) */ - mdec = 0x7fff >> (16 - (multiply_by - 1)); - ndec = 0x202; /* pre divide by 2 (hardcoded) */ - - LPC_SYSCON->SYSPLLCTRL = SYS_PLL_BANDSEL | directo | (selr << SYSCON_SYSPLLCTRL_SELR_P) | - (seli << SYSCON_SYSPLLCTRL_SELI_P) | (selp << SYSCON_SYSPLLCTRL_SELP_P); - LPC_SYSCON->SYSPLLPDEC = pdec | (1 << 7); /* set Pdec value and assert preq */ - LPC_SYSCON->SYSPLLNDEC = ndec | (1 << 10); /* set Pdec value and assert preq */ - LPC_SYSCON->SYSPLLSSCTRL[0] = (1 << 18) | (1 << 17) | mdec; /* select non sscg MDEC value, assert mreq and select mdec value */ -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pll_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pll_5410x.h deleted file mode 100644 index e207af92ef0..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pll_5410x.h +++ /dev/null @@ -1,305 +0,0 @@ -/* - * @brief LPC5410X PLL driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __PLL_5410X_H_ -#define __PLL_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup PLL_5410X CHIP: LPC5410X PLL Driver - * @ingroup CHIP_5410X_DRIVERS - * The PLL in the LPC5410x is flexible, but can be complex to use. This driver - * provides functions to help setup and use the PLL in it's various supported - * modes.
- * - * This driver does not alter PLL clock source or system clocks outside the - * PLL (like the main clock source) that may be referenced from the PLL. It - * may optionally setup system voltages, wait for PLL lock, and power cycle - * the PLL during setup based on setup flags. - * - * The driver works by first generating a PLL setup structure from a desired - * PLL configuration structure. The PLL setup structure is then passed to the - * PLL setup function to setup the PLL. In a user spplication, the PLL setup - * structure can be pre-populated with PLL setup data to avoid using the PLL - * configuration structure (or multiple PLL setup structures can be used to - * more dynamically control PLL output rate). - * - * How to use this driver
- @verbatim - // Setup PLL configuration - PLL_CONFIG_T pllConfig = { - 75000000, // desiredRate = 75MHz - 0, // InputRate = 0Hz (not used) - 0 // No flags, function will determine best setup to get closest rate - }; - - // Get closest PLL setup to get the desired configuration - PLL_SETUP_T pllSetup; - uint32_t actualPllRate; - PLL_ERROR_T pllError; - pllError = Chip_Clock_SetupPLLData(&pllConfig, &pllSetup, &actualPllRate); - if (pllError != PLL_ERROR_SUCCESS) { - printf("PLL setup error #%x\r\n", (uint32_t) pllError); - while (1); - } - else { - printf("PLL config successful, actual config rate = %uHz\r\n", actualPllRate); - } - - // Make sure main system clock is not using PLL, as the PLL setup - // function will power off and optionally power on the PLL - Chip_Clock_SetMainClockSource(SYSCON_MAINCLKSRC_IRC); - - // Setup PLL source - Chip_Clock_SetSystemPLLSource(SYSCON_PLLCLKSRC_IRC); - - // Now to apply the configuration to the PLL - pllSetup.flags = PLL_SETUPFLAG_WAITLOCK; - Chip_Clock_SetupSystemPLLPrec(&pllSetup); - - // Switch main system clock to PLL - Chip_Clock_SetMainClockSource(SYSCON_MAINCLKSRC_PLLOUT); - @endverbatim - * - * @{ - */ - -/** - * Clock sources for system PLLs - */ -typedef enum CHIP_SYSCON_PLLCLKSRC { - SYSCON_PLLCLKSRC_IRC = 0, /*!< Internal oscillator */ - SYSCON_PLLCLKSRC_CLKIN, /*!< External clock input pin */ - SYSCON_PLLCLKSRC_WDTOSC, /*!< WDT oscillator */ - SYSCON_PLLCLKSRC_RTC, /*!< RTC 32KHz oscillator */ -} CHIP_SYSCON_PLLCLKSRC_T; - -/** - * @brief Set System PLL clock source - * @param src : Clock source for system PLL - * @return Nothing - * @note The PLL should be pwoered down prior to changing the source. - */ -STATIC INLINE void Chip_Clock_SetSystemPLLSource(CHIP_SYSCON_PLLCLKSRC_T src) -{ - LPC_SYSCON->SYSPLLCLKSEL = (uint32_t) src; -} - -/** - * @brief Return System PLL input clock rate - * @return System PLL input clock rate - */ -uint32_t Chip_Clock_GetSystemPLLInClockRate(void); - -/** - * @brief Return System PLL output clock rate - * @param recompute : Forces a PLL rate recomputation if true - * @return System PLL output clock rate - * @note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t Chip_Clock_GetSystemPLLOutClockRate(bool recompute); - -/** - * @brief Enables and disables PLL bypass mode - * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass - * @return System PLL output clock rate - */ -void Chip_Clock_SetBypassPLL(bool bypass); - -/** - * @brief Check if PLL is locked or not - * @return true if the PLL is locked, false if not locked - */ -STATIC INLINE bool Chip_Clock_IsSystemPLLLocked(void) -{ - return (bool) ((LPC_SYSCON->SYSPLLSTAT & 1) != 0); -} - -/** @brief PLL configuration structure flags for 'flags' field - * These flags control how the PLL configuration function sets up the PLL setup structure.
- * - * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the - * configuration structure must be assigned with the expected PLL frequency. If the - * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration - * function and the driver will determine the PLL rate from the currently selected - * PLL source. This flag might be used to configure the PLL input clock more accurately - * when using the WDT oscillator or a more dyanmic CLKIN source.
- * - * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the - * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider - * are not used.
- */ -#define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */ -#define PLL_CONFIGFLAG_FORCENOFRACT (1 << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */ - -/** @brief PLL Spread Spectrum (SS) Programmable modulation frequency - * See (MF) field in the SYSPLLSSCTRL1 register in the UM. - */ -typedef enum { - SS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ˜ 3.9 - 7.8 kHz) */ - SS_MF_384 = (1 << 20), /*!< Nss ˜= 384 (fm ˜ 5.2 - 10.4 kHz) */ - SS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ˜ 7.8 - 15.6 kHz) */ - SS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ˜ 15.6 - 31.3 kHz) */ - SS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ˜ 32.3 - 64.5 kHz) */ - SS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ˜ 62.5- 125 kHz) */ - SS_MF_24 = (6 << 20), /*!< Nss ˜= 24 (fm ˜ 83.3- 166.6 kHz) */ - SS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ˜ 125- 250 kHz) */ -} SS_PROGMODFM_T; - -/** @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth - * See (MR) field in the SYSPLLSSCTRL1 register in the UM. - */ -typedef enum { - SS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */ - SS_MR_K1 = (1 << 23), /*!< k = 1 */ - SS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */ - SS_MR_K2 = (3 << 23), /*!< k = 2 */ - SS_MR_K3 = (4 << 23), /*!< k = 3 */ - SS_MR_K4 = (5 << 23), /*!< k = 4 */ - SS_MR_K6 = (6 << 23), /*!< k = 6 */ - SS_MR_K8 = (7 << 23) /*!< k = 8 */ -} SS_PROGMODDP_T; - -/** @brief PLL Spread Spectrum (SS) Modulation waveform control - * See (MC) field in the SYSPLLSSCTRL1 register in the UM.
- * Compensation for low pass filtering of the PLL to get a triangular - * modulation at the output of the PLL, giving a flat frequency spectrum. - */ -typedef enum { - SS_MC_NOC = (0 << 26), /*!< no compensation */ - SS_MC_RECC = (2 << 26), /*!< recommended setting */ - SS_MC_MAXC = (3 << 26), /*!< max. compensation */ -} SS_MODWVCTRL_T; - -/** @brief PLL configuration structure - * This structure can be used to configure the settings for a PLL - * setup structure. Fill in the desired configuration for the PLL - * and call the PLL setup function to fill in a PLL setup structure. - */ -typedef struct { - uint32_t desiredRate; /*!< Desired PLL rate in Hz */ - uint32_t InputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */ - uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ - SS_PROGMODFM_T ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ - SS_PROGMODDP_T ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ - SS_MODWVCTRL_T ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ - bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ -} PLL_CONFIG_T; - -/** @brief PLL setup structure flags for 'flags' field - * These flags control how the PLL setup function sets up the PLL - */ -#define PLL_SETUPFLAG_POWERUP (1 << 0) /*!< Setup will power on the PLL after setup */ -#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ -#define PLL_SETUPFLAG_ADGVOLT (1 << 2) /*!< Optimize system voltage for the new PLL rate */ - -/** @brief PLL setup structure - * This structure can be used to pre-build a PLL setup configuration - * at run-time and quickly set the PLL to the configuration. It can be - * populated with the PLL setup function. If powering up or waiting - * for PLL lock, the PLL input clock source should be configured prior - * to PLL setup. - */ -typedef struct { - uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ - uint32_t SYSPLLCTRL; /*!< PLL control register */ - uint32_t SYSPLLNDEC; /*!< PLL NDEC register */ - uint32_t SYSPLLPDEC; /*!< PLL PDEC register */ - uint32_t SYSPLLSSCTRL[2]; /*!< PLL SSCTL registers */ -} PLL_SETUP_T; - -/** @brief PLL status definitions - */ -typedef enum { - PLL_ERROR_SUCCESS = 0, /*!< PLL operation was successful */ - PLL_ERROR_OUTPUT_TOO_LOW, /*!< PLL output rate request was too low */ - PLL_ERROR_OUTPUT_TOO_HIGH, /*!< PLL output rate request was too high */ - PLL_ERROR_INPUT_TOO_LOW, /*!< PLL input rate is too low */ - PLL_ERROR_INPUT_TOO_HIGH, /*!< PLL input rate is too high */ - PLL_ERROR_OUTSIDE_INTLIMIT /*!< Requested output rate isn't possible */ -} PLL_ERROR_T; - -/** - * @brief Return System PLL output clock rate from setup structure - * @param pSetup : Pointer to a PLL setup structure - * @return System PLL output clock rate the setup structure will generate - */ -uint32_t Chip_Clock_GetSystemPLLOutFromSetup(PLL_SETUP_T *pSetup); - -/** - * @brief Set PLL output based on the passed PLL setup data - * @param pControl : Pointer to populated PLL control structure to generate setup with - * @param pSetup : Pointer to PLL setup structure to be filled - * @return PLL_ERROR_SUCCESS on success, or PLL setup error code - * @note Actual frequency for setup may vary from the desired frequency based on the - * accuracy of input clocks, rounding, non-fractional PLL mode, etc. - */ -PLL_ERROR_T Chip_Clock_SetupPLLData(PLL_CONFIG_T *pControl, PLL_SETUP_T *pSetup); - -/** - * @brief Set PLL output from PLL setup structure (precise frequency) - * @param pSetup : Pointer to populated PLL setup structure - * @return PLL_ERROR_SUCCESS on success, or PLL setup error code - * @note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -PLL_ERROR_T Chip_Clock_SetupSystemPLLPrec(PLL_SETUP_T *pSetup); - -/** - * @brief Set PLL output based on the multiplier and input frequency - * @param multiply_by : multiplier - * @param input_freq : Clock input frequency of the PLL - * @return Nothing - * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this - * function does not disable or enable PLL power, wait for PLL lock, - * or adjust system voltages. These must be done in the application. - * The function will not alter any source clocks (ie, main systen clock) - * that may use the PLL, so these should be setup prior to and after - * exiting the function. - */ -void Chip_Clock_SetupSystemPLL(uint32_t multiply_by, uint32_t input_freq); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __PLL_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pmu_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pmu_5410x.h deleted file mode 100644 index 46eb9ffd324..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pmu_5410x.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * @brief LPC5410X Power Management declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __PMU_5410X_H_ -#define __PMU_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup PMU_5410X CHIP: LPC5410X Power Management declarations and functions - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/** - * @brief PMU register block structure - * @note Most of the PMU support is handled by the PMU library. - */ -typedef struct { - __I uint32_t RESERVED0[4]; - __I uint32_t RESERVED1[4]; - __I uint32_t RESERVED2[4]; - __I uint32_t RESERVED3[4]; - __I uint32_t RESERVED4; - __IO uint32_t BODCTRL; - __I uint32_t RESERVED5; - __I uint32_t RESERVED6; - __IO uint32_t DPDWAKESRC; -} LPC_PMU_T; - -/** - * Brown-out detector reset level - */ -typedef enum { - PMU_BODRSTLVL_0, /*!< Brown-out reset at ~1.5v */ - PMU_BODRSTLVL_1_50V = PMU_BODRSTLVL_0, - PMU_BODRSTLVL_1, /*!< Brown-out reset at ~1.85v */ - PMU_BODRSTLVL_1_85V = PMU_BODRSTLVL_1, - PMU_BODRSTLVL_2, /*!< Brown-out reset at ~2.0v */ - PMU_BODRSTLVL_2_00V = PMU_BODRSTLVL_2, - PMU_BODRSTLVL_3, /*!< Brown-out reset at ~2.3v */ - PMU_BODRSTLVL_2_30V = PMU_BODRSTLVL_3 -} CHIP_PMU_BODRSTLVL_T; - -/** - * Brown-out detector interrupt level - */ -typedef enum CHIP_PMU_BODRINTVAL { - PMU_BODINTVAL_LVL0, /*!< Brown-out interrupt at ~2.05v */ - PMU_BODINTVAL_2_05v = PMU_BODINTVAL_LVL0, - PMU_BODINTVAL_LVL1, /*!< Brown-out interrupt at ~2.45v */ - PMU_BODINTVAL_2_45v = PMU_BODINTVAL_LVL1, - PMU_BODINTVAL_LVL2, /*!< Brown-out interrupt at ~2.75v */ - PMU_BODINTVAL_2_75v = PMU_BODINTVAL_LVL2, - PMU_BODINTVAL_LVL3, /*!< Brown-out interrupt at ~3.05v */ - PMU_BODINTVAL_3_05v = PMU_BODINTVAL_LVL3 -} CHIP_PMU_BODRINTVAL_T; - -/** - * brown-out detection reset status (in BODCTRL register) - */ -#define PMU_BOD_RST (1 << 6) -/** - * brown-out detection interrupt status (in BODCTRL register) - */ -#define PMU_BOD_INT (1 << 7) - -/** - * @brief Set brown-out detection interrupt and reset levels - * @param rstlvl : Brown-out detector reset level - * @param intlvl : Brown-out interrupt level - * @return Nothing - * @note Brown-out detection reset will be disabled upon exiting this function. - * Use Chip_PMU_EnableBODReset() to re-enable. - */ -STATIC INLINE void Chip_PMU_SetBODLevels(CHIP_PMU_BODRSTLVL_T rstlvl, - CHIP_PMU_BODRINTVAL_T intlvl) -{ - LPC_PMU->BODCTRL = ((uint32_t) rstlvl) | (((uint32_t) intlvl) << 2); -} - -/** - * @brief Enable brown-out detection reset - * @return Nothing - */ -STATIC INLINE void Chip_PMU_EnableBODReset(void) -{ - LPC_PMU->BODCTRL |= (1 << 4); -} - -/** - * @brief Disable brown-out detection reset - * @return Nothing - */ -STATIC INLINE void Chip_PMU_DisableBODReset(void) -{ - LPC_PMU->BODCTRL &= ~(1 << 4); -} - -/** - * @brief Enable brown-out detection interrupt - * @return Nothing - */ -STATIC INLINE void Chip_PMU_EnableBODInt(void) -{ - LPC_PMU->BODCTRL |= (1 << 5); -} - -/** - * @brief Disable brown-out detection interrupt - * @return Nothing - */ -STATIC INLINE void Chip_PMU_DisableBODInt(void) -{ - LPC_PMU->BODCTRL &= ~(1 << 5); -} - -/** - * Deep power down reset sources - */ -#define PMU_DPDWU_RESET (1 << 0) /*!< Deep powerdown wakeup by reset pin */ -#define PMU_DPDWU_RTC (1 << 1) /*!< Deep powerdown wakeup by RTC */ -#define PMU_DPDWU_BODRESET (1 << 2) /*!< Deep powerdown wakeup by brown out reset*/ -#define PMU_DPDWU_BODINTR (1 << 3) /*!< Deep powerdown wakeup by brown out interrupt */ - -/** - * @brief Return wakeup sources from deep power down mode - * @return Deep power down mode wakeup sources - * @note Mask the return value with a PMU_DPDWU_* value to determine - * the wakeup source from deep power down. - */ -STATIC INLINE uint32_t Chip_PMU_GetDPDWUSource(void) -{ - return LPC_PMU->DPDWAKESRC; -} - -/** - * @brief Clear a deep power down mode wakeup source - * @param mask : Or'ed PMU_DPDWU_* values to clear - * @return Nothing - */ -STATIC INLINE void Chip_PMU_ClearDPDWUSource(uint32_t mask) -{ - LPC_PMU->DPDWAKESRC = mask; -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __PMU_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/iar/lib_power.a b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/iar/lib_power.a deleted file mode 100644 index 0ac3c53ece8..00000000000 Binary files a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/iar/lib_power.a and /dev/null differ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/iar/lib_power_m0.a b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/iar/lib_power_m0.a deleted file mode 100644 index c6bcba184cf..00000000000 Binary files a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/iar/lib_power_m0.a and /dev/null differ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/keil/lib_power.lib b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/keil/lib_power.lib deleted file mode 100644 index d6271384a44..00000000000 Binary files a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/keil/lib_power.lib and /dev/null differ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/keil/lib_power_m0.lib b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/keil/lib_power_m0.lib deleted file mode 100644 index 7295fbb2642..00000000000 Binary files a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/keil/lib_power_m0.lib and /dev/null differ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/lpcxpresso/lib_power.a b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/lpcxpresso/lib_power.a deleted file mode 100644 index f5064ec2ef3..00000000000 Binary files a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/lpcxpresso/lib_power.a and /dev/null differ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/lpcxpresso/libpower.a b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/lpcxpresso/libpower.a deleted file mode 100644 index f5064ec2ef3..00000000000 Binary files a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/lpcxpresso/libpower.a and /dev/null differ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/lpcxpresso/libpower_m0.a b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/lpcxpresso/libpower_m0.a deleted file mode 100644 index f1e2dbc5ca2..00000000000 Binary files a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/lpcxpresso/libpower_m0.a and /dev/null differ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib_5410x.h deleted file mode 100644 index 52e902c6edd..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib_5410x.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * @brief LPC5410x Power library functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __POWER_LIB_5410X_H_ -#define __POWER_LIB_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup POWER_LIBRARY_5410X CHIP: LPC5410X Power LIBRARY functions - * The power library provides functions to control system power usage and - * place the device into low power modes.
- * - * Clock shutdown in sleep and power down modes
- * When using the Chip_POWER_EnterPowerMode() function, system clocks are - * shutdown based on the selected sleep or power down mode and the device - * version being used. The following list details which clocks are shut down - * in which modes for which device versions. You can keep a clock enabled - * for a sleep or power down mode by enabling it in the 'peripheral_ctrl' - * field in the Chip_POWER_EnterPowerMode() function.
- * - * Mode: Sleep
- * No clocks are disabled for any chip version.
- * - * Mode: Deep sleep
- * SYSCON_PDRUNCFG_PD_IRC_OSC
- * SYSCON_PDRUNCFG_PD_IRC
- * SYSCON_PDRUNCFG_PD_FLASH (v17.1 and later only)
- * SYSCON_PDRUNCFG_PD_BOD_INTR
- * SYSCON_PDRUNCFG_PD_ADC0
- * SYSCON_PDRUNCFG_PD_ROM
- * SYSCON_PDRUNCFG_PD_VDDA_ENA
- * SYSCON_PDRUNCFG_PD_SYS_PLL
- * SYSCON_PDRUNCFG_PD_VREFP
- * - * Mode: Power down
- * SYSCON_PDRUNCFG_PD_IRC_OSC
- * SYSCON_PDRUNCFG_PD_IRC
- * SYSCON_PDRUNCFG_PD_FLASH (v17.1 and later only)
- * SYSCON_PDRUNCFG_PD_BOD_RST
- * SYSCON_PDRUNCFG_PD_BOD_INTR
- * SYSCON_PDRUNCFG_PD_ADC0
- * SYSCON_PDRUNCFG_PD_SRAM0B
- * SYSCON_PDRUNCFG_PD_SRAM1
- * SYSCON_PDRUNCFG_PD_SRAM2
- * SYSCON_PDRUNCFG_PD_ROM
- * SYSCON_PDRUNCFG_PD_VDDA_ENA
- * SYSCON_PDRUNCFG_PD_WDT_OSC
- * SYSCON_PDRUNCFG_PD_SYS_PLL
- * SYSCON_PDRUNCFG_PD_VREFP
- * SYSCON_PDRUNCFG_PD_32K_OSC
- * - * Mode: Deep power down
- * All clocks are disabled for all chip versions.
- * - * If you are using a peripheral was a wakeup source for a power down mode, - * it needs to be kept active with the call to Chip_POWER_EnterPowerMode(). For - * example, if you are using the RTC to wake the system up from power down mode, - * the 32KHz RTC oscillator needs to remain active, so the power down call would - * look like this:
- * Chip_POWER_EnterPowerMode(POWER_POWER_DOWN, SYSCON_PDRUNCFG_PD_32K_OSC);
- * If your application uses internal RAM beyond the first 8K, you will also need - * to prevent power down of the IRAM like this:
- * Chip_POWER_EnterPowerMode(POWER_POWER_DOWN, (SYSCON_PDRUNCFG_PD_32K_OSC | SYSCON_PDRUNCFG_PD_SRAM0A));
- * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/** - * @brief Sets up the System PLL given the PLL input frequency and feedback multiplier - * @param multiply_by : PLL multiplier, minimum of 1, maximum of 16 - * @param input_freq : Input frequency into the PLL - * @return LPC_OK on success, or an error code (see error.h) - */ -uint32_t Chip_POWER_SetPLL(uint32_t multiply_by, uint32_t input_freq); - -/** - * @brief Set optimal system voltage based on passed system frequency - * @param mode : Power mode - * @param desired_freq : System (CPU) frequency - * @return LPC_OK on success, or an error code (see error.h) - * @note This function will adjust the system voltages to the lowest - * levels that will support the passed mode and CPU frequency. - */ -uint32_t Chip_POWER_SetVoltage(PERF_MODE_T mode, uint32_t desired_freq); - -/** - * @brief Enters the selected power state - * @param mode : Power mode - * @param peripheral_ctrl : Peripherals that will remain powered up in the power state - * @return Nothing - * @note The 'peripheral_ctrl' field is a bitmask of bits from the - * PDRUNCFG register (SYSCON_PDRUNCFG_PD_*) that describe which - * peripherals can wake up the chip from the power state. These - * peripherals are not powered down during the power state.
- */ -void Chip_POWER_EnterPowerMode(POWER_MODE_T mode, uint32_t peripheral_ctrl); - -/* ROM versions */ -#define LPC5410X_ROMVER_0 (0x1100) -#define LPC5410X_ROMVER_1 (0x1101) -#define LPC5410X_ROMVER_2 (0x1102) - -/** - * @brief Fast powerdown for IRAM based applications - * @param peripheral_ctrl : Peripherals that will remain powered up in the power down state - * @return Nothing - * @note The 'peripheral_ctrl' field is a bitmask of bits from the - * PDRUNCFG register (SYSCON_PDRUNCFG_PD_*) that describe which - * peripherals can wake up the chip from the power state. These - * peripherals are not powered down during the power state.
- * This function should only be used when not executing code in FLASH. - * It will power down FLASH and leave it powered down on exit, so all - * code should be placed in IRAM prior to calling. It provides a quicker - * wakeup response than the default powerdown function - * (Chip_POWER_EnterPowerMode(POWER_POWER_DOWN, ...)). - */ -void Chip_POWER_EnterPowerModeIramOnly(uint32_t peripheral_ctrl); - -/** - * @brief Return ROM version - * @return ROM version - * @note Will return one of the following version numbers:
- * (0x1100) for v17.0 ROMs.
- * (0x1101) for v17.1 ROMs.
- * (0x1102) for v17.2 ROMs.
- */ -uint32_t Chip_POWER_GetROMVersion(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __POWER_LIB_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/ritimer_5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/ritimer_5410x.c deleted file mode 100644 index e9aab5924e2..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/ritimer_5410x.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * @brief LPC5410X RITimer chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Initialize the RIT */ -void Chip_RIT_Init(LPC_RITIMER_T *pRITimer) -{ - Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_RIT); - Chip_SYSCON_PeriphReset(RESET_RIT); - - /* Default is timer disabled */ - pRITimer->CTRL = 0x0; -} - -/* DeInitialize the RIT */ -void Chip_RIT_DeInit(LPC_RITIMER_T *pRITimer) -{ - pRITimer->CTRL = 0x0; - Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_RIT); -} - -/* Set timer interval value */ -void Chip_RIT_SetTimerInterval(LPC_RITIMER_T *pRITimer, uint32_t time_interval) -{ - uint32_t cmp_value; - - /* Determine aapproximate compare value based on clock rate and passed interval */ - cmp_value = (Chip_Clock_GetMainClockRate() / 1000) * time_interval; - - /* Set timer compare value */ - Chip_RIT_SetCOMPVAL(pRITimer, cmp_value); -} - -/* Set timer interval value (48-bit) */ -void Chip_RIT_SetTimerInterval64(LPC_RITIMER_T *pRITimer, uint64_t time_interval) -{ - uint64_t cmp_value; - - /* Determine aapproximate compare value based on clock rate and passed interval */ - cmp_value = (uint64_t) Chip_Clock_GetMainClockRate() / 1000; - cmp_value = cmp_value * time_interval; - - /* Set timer compare value */ - Chip_RIT_SetCOMPVAL64(pRITimer, cmp_value); -} - -/* Check whether interrupt is pending */ -IntStatus Chip_RIT_GetIntStatus(LPC_RITIMER_T *pRITimer) -{ - uint8_t result; - - if ((pRITimer->CTRL & RIT_CTRL_INT) == 1) { - result = SET; - } - else { - return RESET; - } - - return (IntStatus) result; -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/ritimer_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/ritimer_5410x.h deleted file mode 100644 index a5232ef1d8c..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/ritimer_5410x.h +++ /dev/null @@ -1,249 +0,0 @@ -/* - * @brief LPC5410x RITimer driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __RITIMER_5410X_H_ -#define __RITIMER_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup RITIMER_5410X CHIP: LPC5410x Repetitive Interrupt Timer driver - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/** - * @brief Repetitive Interrupt Timer register block structure - */ -typedef struct { /*!< RITIMER Structure */ - __IO uint32_t COMPVAL; /*!< Compare register */ - __IO uint32_t MASK; /*!< Mask register */ - __IO uint32_t CTRL; /*!< Control register */ - __IO uint32_t COUNTER; /*!< 32-bit counter */ - __IO uint32_t COMPVAL_H; /*!< Compare register, upper 16-bits */ - __IO uint32_t MASK_H; /*!< Compare register, upper 16-bits */ - __I uint32_t reserved; - __IO uint32_t COUNTER_H; /*!< Counter register, upper 16-bits */ -} LPC_RITIMER_T; - -/* - * @brief RITIMER register support bitfields and mask - */ - -/* - * RIT control register - */ -/** Set by H/W when the counter value equals the masked compare value */ -#define RIT_CTRL_INT ((uint32_t) (1)) -/** Set timer enable clear to 0 when the counter value equals the masked compare value */ -#define RIT_CTRL_ENCLR ((uint32_t) _BIT(1)) -/** Set timer enable on debug */ -#define RIT_CTRL_ENBR ((uint32_t) _BIT(2)) -/** Set timer enable */ -#define RIT_CTRL_TEN ((uint32_t) _BIT(3)) - -/** - * @brief Initialize the RIT - * @param pRITimer : RITimer peripheral selected - * @return None - */ -void Chip_RIT_Init(LPC_RITIMER_T *pRITimer); - -/** - * @brief Shutdown the RIT - * @param pRITimer : RITimer peripheral selected - * @return None - */ -void Chip_RIT_DeInit(LPC_RITIMER_T *pRITimer); - -/** - * @brief Enable Timer - * @param pRITimer : RITimer peripheral selected - * @return None - */ -STATIC INLINE void Chip_RIT_Enable(LPC_RITIMER_T *pRITimer) -{ - pRITimer->CTRL |= RIT_CTRL_TEN; -} - -/** - * @brief Disable Timer - * @param pRITimer : RITimer peripheral selected - * @return None - */ -STATIC INLINE void Chip_RIT_Disable(LPC_RITIMER_T *pRITimer) -{ - pRITimer->CTRL &= ~RIT_CTRL_TEN; -} - -/** - * @brief Enable timer debug - * @param pRITimer : RITimer peripheral selected - * @return None - */ -STATIC INLINE void Chip_RIT_DebugEnable(LPC_RITIMER_T *pRITimer) -{ - pRITimer->CTRL |= RIT_CTRL_ENBR; -} - -/** - * @brief Disable timer debug - * @param pRITimer : RITimer peripheral selected - * @return None - */ -STATIC INLINE void Chip_RIT_DebugDisable(LPC_RITIMER_T *pRITimer) -{ - pRITimer->CTRL &= ~RIT_CTRL_ENBR; -} - -/** - * @brief Enable clear on compare match - * @param pRITimer : RITimer peripheral selected - * @return None - */ -STATIC INLINE void Chip_RIT_CompClearEnable(LPC_RITIMER_T *pRITimer) -{ - pRITimer->CTRL |= RIT_CTRL_ENCLR; -} - -/** - * @brief Disable clear on compare match - * @param pRITimer : RITimer peripheral selected - * @return None - */ -STATIC INLINE void Chip_RIT_CompClearDisable(LPC_RITIMER_T *pRITimer) -{ - pRITimer->CTRL &= ~RIT_CTRL_ENCLR; -} - -/** - * @brief Check whether interrupt flag is set or not - * @param pRITimer : RITimer peripheral selected - * @return Current interrupt status, either ET or UNSET - */ -IntStatus Chip_RIT_GetIntStatus(LPC_RITIMER_T *pRITimer); - -/** - * @brief Set a tick value for the interrupt to time out - * @param pRITimer : RITimer peripheral selected - * @param val : value (in ticks) of the interrupt to be set - * @return None - */ -STATIC INLINE void Chip_RIT_SetCOMPVAL(LPC_RITIMER_T *pRITimer, uint32_t val) -{ - pRITimer->COMPVAL = val; - pRITimer->COMPVAL_H = 0; -} - -/** - * @brief Set a tick value for the interrupt to time out (48-bits) - * @param pRITimer : RITimer peripheral selected - * @param val : value (in ticks) of the interrupt to be set, 48-bits max - * @return None - */ -STATIC INLINE void Chip_RIT_SetCOMPVAL64(LPC_RITIMER_T *pRITimer, uint64_t val) -{ - pRITimer->COMPVAL = (uint32_t) (val & 0xFFFFFFFF); - pRITimer->COMPVAL_H = (uint32_t) ((val >> 32) & 0xFFFF); -} - -/** - * @brief Enables or clears the RIT or interrupt - * @param pRITimer : RITimer peripheral selected - * @param val : RIT to be set, one or more RIT_CTRL_* values - * @return None - */ -STATIC INLINE void Chip_RIT_EnableCTRL(LPC_RITIMER_T *pRITimer, uint32_t val) -{ - pRITimer->CTRL |= val; -} - -/** - * @brief Clears the RIT interrupt - * @param pRITimer : RITimer peripheral selected - * @return None - */ -STATIC INLINE void Chip_RIT_ClearInt(LPC_RITIMER_T *pRITimer) -{ - pRITimer->CTRL |= RIT_CTRL_INT; -} - -/** - * @brief Returns the current RIT Counter value - * @param pRITimer : RITimer peripheral selected - * @return the current timer counter value - */ -STATIC INLINE uint32_t Chip_RIT_GetCounter(LPC_RITIMER_T *pRITimer) -{ - return pRITimer->COUNTER; -} - -/** - * @brief Returns the current RIT Counter value (48-bit) - * @param pRITimer : RITimer peripheral selected - * @return the current timer counter value - */ -STATIC INLINE uint64_t Chip_RIT_GetCounter64(LPC_RITIMER_T *pRITimer) -{ - uint64_t retVal; - - retVal = (uint64_t) pRITimer->COUNTER; - retVal = retVal | (((uint64_t) pRITimer->COUNTER_H) << 32); - - return retVal; -} - -/** - * @brief Set timer interval value - * @param pRITimer : RITimer peripheral selected - * @param time_interval : timer interval value (ms) - * @return None - */ -void Chip_RIT_SetTimerInterval(LPC_RITIMER_T *pRITimer, uint32_t time_interval); - -/** - * @brief Set timer interval value (48-bit) - * @param pRITimer : RITimer peripheral selected - * @param time_interval : timer interval value (ms) - * @return None - */ -void Chip_RIT_SetTimerInterval64(LPC_RITIMER_T *pRITimer, uint64_t time_interval); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __RITIMER_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/rom_pwr_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/rom_pwr_5410x.h deleted file mode 100644 index c6169f81fab..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/rom_pwr_5410x.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * @brief LPC5410X Power ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __ROM_PWR_5410X_H_ -#define __ROM_PWR_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup PWRD_5410X CHIP: LPC5410X Power ROM API declarations and functions - * @ingroup ROMAPI_5410X - * @{ - */ - -/* 'mode' input values to set_voltage ROM function */ -typedef enum { - POWER_LOW_POWER_MODE = 0, - POWER_BALANCED_MODE, - POWER_HIGH_PERFORMANCE -} PERF_MODE_T; - -/* 'mode' input values to power_mode_configure ROM function */ -typedef enum { - POWER_SLEEP = 0, - POWER_DEEP_SLEEP, - POWER_POWER_DOWN, - POWER_DEEP_POWER_DOWN -} POWER_MODE_T; - -/** @brief Power ROM indirect function structure - * Do not use these functions as direct calls to ROM. Instead, use the - * wrapper functions provided by the Power library (power_lib_5410x.h) - */ -typedef struct { - uint32_t (*set_pll)(uint32_t multiply_by, uint32_t input_freq); - uint32_t (*set_voltage)(uint32_t mode, uint32_t desired_freq); - void (*power_mode_configure)(uint32_t mode, uint32_t peripheral_ctrl); -} PWRD_API_T; - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ROM_PWR_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_5410x.h deleted file mode 100644 index 68b7e2622ae..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_5410x.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * @brief LPC5410X ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __ROMAPI_5410X_H_ -#define __ROMAPI_5410X_H_ - -#include -#include "iap.h" -#include "error.h" -#include "cmsis.h" - -/* v1 ROM driver APIs */ -#include "rom_pwr_5410x.h" - -/* v2 ROM driver APIs */ -#include "romapi_adc.h" -#include "romapi_dma.h" -#include "romapi_i2cm.h" -#include "romapi_i2cmon.h" -#include "romapi_i2cs.h" -#include "romapi_spim.h" -#include "romapi_spis.h" -#include "romapi_uart.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup ROMAPI_5410X CHIP: LPC5410X ROM API declarations and functions - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/** - * @brief High level ROM API structure - */ -typedef struct { - const uint32_t reserved_usb; /*!< Reserved */ - const uint32_t reserved_clib; /*!< Reserved */ - const uint32_t reserved_can; /*!< Reserved */ - const PWRD_API_T *pPWRD; /*!< Power API function table base address */ - const uint32_t reserved_div; /*!< Reserved */ - const uint32_t reserved_i2cd; /*!< Reserved */ - const uint32_t reserved_dmad; /*!< Reserved */ - const uint32_t reserved_spid; /*!< Reserved */ - const uint32_t reserved_adcd; /*!< Reserved */ - const uint32_t reserved_uartd; /*!< Reserved */ - const uint32_t reserved_vfifo; /*!< Reserved */ - const uint32_t reserved_usart; /*!< Reserved */ - /* v2 drivers - only present in some LPC5410x devices */ - const ROM_I2CMD_API_T *pI2CMD; /*!< v2 I2C master only driver API function table base address */ - const ROM_I2CSD_API_T *pI2CSD; /*!< v2 I2C slave only driver API function table base address */ - const ROM_I2CMOND_API_T *pI2CMOND; /*!< v2 I2C bus monitor driver API function table base address */ - const ROM_SPIMD_API_T *pSPIMD; /*!< v2 SPI master only driver API function table base address */ - const ROM_SPISD_API_T *pSPISD; /*!< v2 SPI slave only driver API function table base address */ - const ROM_DMAALTD_API_T *pDMAALT; /*!< v2 abstract DMA driver API function table base address */ - const ROM_ADC_API_T *pADCALT; /*!< v2 ADC driver API function table base address */ - const ROM_UART_API_T *pUARTALT; /*!< v2 UART driver API function table base address */ -} LPC_ROM_API_T; - -/* Pointer to ROM API function address */ -#define LPC_ROM_API_BASE_LOC 0x03000200UL -#define LPC_ROM_API (*(LPC_ROM_API_T * *) LPC_ROM_API_BASE_LOC) - -/* Pointer to @ref PWRD_API_T functions in ROM */ -#define LPC_PWRD_API ((LPC_ROM_API)->pPWRD) - -/* Pointer to v2 I2C master peripheral driver functions in ROM */ -#define ROMAPI_I2CM_API ((LPC_ROM_API)->pI2CMD) - -/* Pointer to v2 I2C master peripheral driver functions in ROM */ -#define ROMAPI_I2CMON_API ((LPC_ROM_API)->pI2CMOND) - -/* Pointer to v2 I2C slave peripheral driver functions in ROM */ -#define ROMAPI_I2CS_API ((LPC_ROM_API)->pI2CSD) - -/* Pointer to v2 SPI master peripheral driver functions in ROM */ -#define ROMAPI_SPIM_API ((LPC_ROM_API)->pSPIMD) - -/* Pointer to v2 SPI slave peripheral driver functions in ROM */ -#define ROMAPI_SPIS_API ((LPC_ROM_API)->pSPISD) - -/* Pointer to v2 DMA controller driver functions in ROM */ -#define ROMAPI_DMAALT_API ((LPC_ROM_API)->pDMAALT) - -/* Pointer to v2 ADC driver functions in ROM */ -#define ROMAPI_ADC_API ((LPC_ROM_API)->pADCALT) - -/* Pointer to v2 UART controller driver functions in ROM */ -#define ROMAPI_UART_API ((LPC_ROM_API)->pUARTALT) - -/* Pointer to ROM IAP entry functions */ -#define IAP_ENTRY_LOCATION 0x03000205 - -/** - * @brief LPC5410x IAP_ENTRY API function type - */ -static INLINE void iap_entry(uint32_t cmd_param[5], uint32_t status_result[4]) -{ - ((IAP_ENTRY_T) IAP_ENTRY_LOCATION)(cmd_param, status_result); -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ROMAPI_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_adc.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_adc.c deleted file mode 100644 index c07ee4cbbc7..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_adc.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * @brief ADC ROM API declarations and functions - * These are the public ROM APIs and functions of the ADC ROM - * driver. - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "romapi_5410x.h" - -/* Get memory size in bytes needed for ADC driver context */ -uint32_t ROM_ADC_GetMemSize(void) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_ADC_API->GetMemSize(); -#else - return adcrom_api.GetMemSize(); -#endif -} - -/* Initialize the ADC ROM driver */ -ADC_HANDLE_T ROM_ADC_Init(void *pMem, uint32_t baseAddr, void *pUserData) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_ADC_API->Init(pMem, baseAddr, pUserData); -#else - return adcrom_api.Init(pMem, baseAddr, pUserData); -#endif -} - -/* Configure the ADC peripheral */ -ErrorCode_t ROM_ADC_Configure(ADC_HANDLE_T hADC, const ADC_CFG_T *pCfg) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_ADC_API->Configure(hADC, pCfg); -#else - return adcrom_api.Configure(hADC, pCfg); -#endif -} - -/* Calibrate the ADC */ -ErrorCode_t ROM_ADC_Calibrate(ADC_HANDLE_T hADC, uint32_t sysclk_freq) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_ADC_API->Calibrate(hADC, sysclk_freq); -#else - return adcrom_api.Calibrate(hADC, sysclk_freq); -#endif -} - -/* Start the conversion on given SEQ */ -ErrorCode_t ROM_ADC_StartConversion(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex, void *pBuf, size_t bufCount) -{ -#if defined(ROMDRIVERSV2_PRESENT) - /* Correct index adjust bug */ - uint32_t *ptr = &((uint32_t *)hADC)[9 + seqIndex * 6]; - if (*ptr != 2) *(ptr - 1) = 0; - - return ROMAPI_ADC_API->StartConversion(hADC, seqIndex, pBuf, bufCount); -#else - return adcrom_api.StartConversion(hADC, seqIndex, pBuf, bufCount); -#endif -} - -/* ADC Event handler */ -ErrorCode_t ROM_ADC_Handler(ADC_HANDLE_T hADC, ADC_HEVENT_T hEvent) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_ADC_API->Handler(hADC, hEvent); -#else - return adcrom_api.Handler(hADC, hEvent); -#endif -} - -/* ADC Callback register */ -ErrorCode_t ROM_ADC_RegisterCB(ADC_HANDLE_T hADC, ADC_CBINDEX_T cbIndex, void (*pCbFunc)(ADC_HANDLE_T, - ADC_CBINDEX_T, - void *)) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_ADC_API->RegisterCB(hADC, cbIndex, pCbFunc); -#else - return adcrom_api.RegisterCB(hADC, cbIndex, pCbFunc); -#endif -} - -/* Set Threshold register values */ -void ROM_ADC_SetThreshold(ADC_HANDLE_T hADC, uint32_t valThr0, uint32_t valThr1) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_ADC_API->SetThreshold(hADC, valThr0, valThr1); -#else - adcrom_api.SetThreshold(hADC, valThr0, valThr1); -#endif -} - -/* Configure ADC channel */ -ErrorCode_t ROM_ADC_ConfigureCh(ADC_HANDLE_T hADC, uint32_t chanNum, uint32_t chanOpts) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_ADC_API->ConfigureCh(hADC, chanNum, chanOpts); -#else - return adcrom_api.ConfigureCh(hADC, chanNum, chanOpts); -#endif -} - -/* Stop conversion of Analog samples */ -ErrorCode_t ROM_ADC_StopConversion(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_ADC_API->StopConversion(hADC, seqIndex); -#else - return adcrom_api.StopConversion(hADC, seqIndex); -#endif -} - -/* Generate a software trigger */ -ErrorCode_t ROM_ADC_SwTrigger(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_ADC_API->SwTrigger(hADC, seqIndex); -#else - return adcrom_api.SwTrigger(hADC, seqIndex); -#endif -} - -/* Get Current verion of the driver */ -uint16_t ROM_ADC_GetDriverVersion(void) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_ADC_API->GetDriverVersion(); -#else - return adcrom_api.GetDriverVersion(); -#endif -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_adc.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_adc.h deleted file mode 100644 index e648fb19747..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_adc.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * @brief ADC ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __ROMAPI_ADC_H_ -#define __ROMAPI_ADC_H_ - -#include "hw_adc_rom_api.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup ROMAPI_ADC_WRAPPER CHIP: ADC ROM Driver wrapper functions - * @ingroup ROMAPI_5410X - * @{ - */ - -/** - * @brief Get memory size in bytes needed for ADC driver context - * @return Size in bytes needed for the ROM driver - */ -uint32_t ROM_ADC_GetMemSize(void); - -/** - * @brief Initialize ADC ROM Driver - * @param pMem : Pointer to memory area for driver context - * @param baseAddr : Base address of the ADC peripheral - * @param pUserData : Pointer to User Data - * @return Pointer to the device context handle or NULL on alignment failure - * @note Parameter @a pMem must be a pointer to word aligned memory - * if the pointer is not word aligned (4-Byte) the function returns - * NULL. - */ -ADC_HANDLE_T ROM_ADC_Init(void *pMem, uint32_t baseAddr, void *pUserData); - -/** - * @brief Configure the ADC peripheral - * @param hADC : Handle to ADC obtained using ROM_ADC_Init() - * @param pCfg : Pointer to configuration structure #ADC_CFG_T - * @return Always returns LPC_OK - */ -ErrorCode_t ROM_ADC_Configure(ADC_HANDLE_T hADC, const ADC_CFG_T *pCfg); - -/** - * @brief Calibrate ADC upon startup or wakeup after powerdown - * @pre ADC must be Initialized and Configured - * @param hADC : Handle to ADC obtained using ROM_ADC_Init() - * @param sysclk_freq : Frequency of the system - * @return Result of calibrarion operation - * @retval LPC_OK Calibration is successful - * @retval ERR_ADC_NO_POWER Unable to powerup ADC - * @retval ERR_TIME_OUT Calibration operation timed-out - */ -ErrorCode_t ROM_ADC_Calibrate(ADC_HANDLE_T hADC, uint32_t sysclk_freq); - -/** - * @brief Start the ADC peripheral - * @pre ADC must be properly initialized, Configured and Calibrated - * @param hADC : Handle to ADC obtained using ROM_ADC_Init() - * @param seqIndex : Index of the sequence to start must be one of #ADC_SEQ_A or #ADC_SEQ_B - * @param pBuf : Pointer to buffer (see note below) - * @param szBuf : Size of buffer (see note below) - * @return Result of the start operation - * @retval LPC_OK Successfully started ADC sampling on given sequence or - * given buffer is queued successfully (when called from #ADC_BUFFER_DONE - * callback handler) - * @retval ERR_ADC_INVALID_SEQUENCE Parameter @a seqIndex is not one of #ADC_SEQ_A or #ADC_SEQ_B - * @retval ERR_BUSY Already a buffer is active and swap buffer is also configured - * @note The size of the buffer must be M x N where M is the number of channels enabled in - * sequence @a seqIndex, and N is the number of samples to be converted. - * The buffer provided by @a pBuf must be of size M x N x sizeof(uint16_t) bytes(for non-DMA). - * Assume that channels 1, 3, 4, 8 are enabled in sequence @a seqIndex and number of - * samples to be collected is N, the buffer will be filled with DATA_1[0], DATA_3[0], - * DATA_4[0], DATA_8[0], ... , DATA_1[N], DATA_3[N], DATA_4[N], DATA_8[N], note - * that the order in which the channels are enabled does not matter they will always be - * filled up in ascending order. - */ -ErrorCode_t ROM_ADC_StartConversion(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex, void *pBuf, size_t szBuf); - -/** - * @brief Handler to handle ADC events - * @param hADC : Handle to ADC obtained using ROM_ADC_Init() - * @param hEvent : Type of the event - * @return Event handling results - * @retval LPC_OK Event successfully handled - * @retval ERR_ADC_INVALID_SEQUENCE Event is not for the given sequence - * @retval ERR_FAILED Internal ADC error (Channel enabled but no data available) - * @retval ERR_ADC_PARAM Invaild event parameter for @a hEvent - */ -ErrorCode_t ROM_ADC_Handler(ADC_HANDLE_T hADC, ADC_HEVENT_T hEvent); - -/** - * @brief Registers a callback function associated with an event - * @param hADC : Handle to ADC obtained using ROM_ADC_Init() - * @param cbIndex : Index of the call-back function (Associated with an event) - * @param pCbFunc : Pointer to callback function - * @return Success or failure - * @retval LPC_OK Callback successfully registered - * @retval ERR_ADC_PARAM Invaild event parameter for @a cbIndex - */ -ErrorCode_t ROM_ADC_RegisterCB(ADC_HANDLE_T hADC, ADC_CBINDEX_T cbIndex, void (*pCbFunc)(ADC_HANDLE_T, - ADC_CBINDEX_T, - void *)); - -/** - * @brief Setup high and low threshold values for threshold 0, 1 - * @param hADC : Handle to ADC obtained using ROM_ADC_Init() - * @param valThr0 : Threshold 0 value (bits 31-16 has high value, bits 15-0 has low value) - * @param valThr1 : Threshold 1 value (bits 31-16 has high value, bits 15-0 has low value) - * @return Nothing - */ -void ROM_ADC_SetThreshold(ADC_HANDLE_T hADC, uint32_t valThr0, uint32_t valThr1); - -/** - * @brief Configure a single channel - * @param hADC : Handle to ADC obtained using ROM_ADC_Init() - * @param chanNum : Channel number - * @param chanOpts : Options for the channel - * @return LPC_OK on success, ERR_ADC_PARAM if @a chanNum is invalid - */ -ErrorCode_t ROM_ADC_ConfigureCh(ADC_HANDLE_T hADC, uint32_t chanNum, uint32_t chanOpts); - -/** - * @brief Stop the conversion in progress - * @param hADC : Handle to ADC obtained using ROM_ADC_Init() - * @param seqIndex : Sequence that needs to be stopped - * @return LPC_OK on success, ERR_ADC_INVALID_SEQUENCE if @a seqIndex is invalid - */ -ErrorCode_t ROM_ADC_StopConversion(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex); - -/** - * @brief Generate software trigger for given sequence - * @param hADC : Handle to ADC obtained using ROM_ADC_Init() - * @param seqIndex : Sequence that needs to be triggered - * @return LPC_OK on success, ERR_ADC_INVALID_SEQUENCE if @a seqIndex is invalid - */ -ErrorCode_t ROM_ADC_SwTrigger(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex); - -/** - * @brief Return the ADC ROM driver version - * @return Driver version number - * @note The returned driver version number consists of a major and minor - * number, with the minor number in the lower 8 bits and the major number in - * the upper 8 bits. - */ -uint16_t ROM_ADC_GetDriverVersion(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ROMAPI_ADC_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_dma.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_dma.c deleted file mode 100644 index 7c9450fdfd5..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_dma.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * @brief DMA master ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "romapi_5410x.h" - -/* Get memory size in bytes needed for DMA controller driver context */ -uint32_t ROM_DMA_GetMemSize(void) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_DMAALT_API->GetMemSize(); -#else - return dmaalt_api.GetMemSize(); -#endif -} - -/* Initialize DMA controller */ -ROM_DMA_HANDLE_T ROM_DMA_Init(void *mem, ROM_DMA_INIT_T *pInit) -{ - /* Verify SRAMBASE alginemnt is at least MINDMATABLEALIGN bytes */ - if (((uint32_t) pInit->sramBase & (MINDMATABLEALIGN - 1)) != 0) { - return NULL; - } - -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_DMAALT_API->Init(mem, pInit); -#else - return dmaalt_api.Init(mem, pInit); -#endif -} - -/* Configures a DMA channel */ -ErrorCode_t ROM_DMA_SetupChannel(ROM_DMA_HANDLE_T pHandle, ROM_DMA_CHAN_CFG_T *pCfg, uint8_t dmaCh) -{ - if (dmaCh >= NUMDMACHANNELS) { - return ERR_DMA_CHANNEL_NUMBER; - } - -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_DMAALT_API->SetupChannel(pHandle, pCfg, dmaCh); -#else - return dmaalt_api.SetupChannel(pHandle, pCfg, dmaCh); -#endif -} - -/* Initializes a transfer descriptor queue for a channel */ -ErrorCode_t ROM_DMA_InitQueue(ROM_DMA_HANDLE_T pHandle, uint8_t dmaCh, ROM_DMA_QUEUE_T *pQueue) -{ - if (dmaCh >= NUMDMACHANNELS) { - return ERR_DMA_CHANNEL_NUMBER; - } - -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_DMAALT_API->InitQueue(pHandle, dmaCh, pQueue); -#else - return dmaalt_api.InitQueue(pHandle, dmaCh, pQueue); -#endif -} - -/* Registers an DMA controller callback for a queue */ -void ROM_DMA_RegisterQueueCallback(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue, uint32_t cbIndex, void *pCB) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_DMAALT_API->RegisterQueueCallback(pHandle, pQueue, cbIndex, pCB); -#else - dmaalt_api.RegisterQueueCallback(pHandle, pQueue, cbIndex, pCB); -#endif -} - -/* Builds a transfer descriptor chain from the passed settings */ -ErrorCode_t ROM_DMA_BuildDescriptorChain(ROM_DMA_HANDLE_T pHandle, - ROM_DMA_XFERDESC_CFG_T *pXferCfg, - ROM_DMA_DESC_T *pDesc, - ROM_DMA_DESC_T *pDescPrev) -{ - if (pXferCfg->dmaCh >= NUMDMACHANNELS) { - return ERR_DMA_CHANNEL_NUMBER; - } - -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_DMAALT_API->BuildDescriptorChain(pHandle, pXferCfg, pDesc, pDescPrev); -#else - return dmaalt_api.BuildDescriptorChain(pHandle, pXferCfg, pDesc, pDescPrev); -#endif -} - -/* Returns the number of items transferred on the last descriptor chain (spent status only) */ -uint32_t ROM_DMA_GetTransferCount(ROM_DMA_HANDLE_T pHandle, ROM_DMA_DESC_T *pDesc) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_DMAALT_API->GetTransferCount(pHandle, pDesc); -#else - return dmaalt_api.GetTransferCount(pHandle, pDesc); -#endif -} - -/* Unstalls a descriptor chain that has been setup using the stallDesc option */ -void ROM_DMA_UnstallDescriptorChain(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_DMAALT_API->UnstallDescriptorChain(pHandle, pQueue); -#else - dmaalt_api.UnstallDescriptorChain(pHandle, pQueue); -#endif -} - -/* Queues a transfer descriptor chain */ -void ROM_DMA_QueueDescriptor(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue, ROM_DMA_DESC_T *pDescChainHead) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_DMAALT_API->QueueDescriptor(pHandle, pQueue, pDescChainHead); -#else - dmaalt_api.QueueDescriptor(pHandle, pQueue, pDescChainHead); -#endif -} - -/* Returns current status of next descriptor to be popped from the queue */ -ROM_DMA_DESC_STS_T ROM_DMA_GetQueuePopDescriptorStatus(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_DMAALT_API->GetQueuePopDescriptorStatus(pHandle, pQueue); -#else - return dmaalt_api.GetQueuePopDescriptorStatus(pHandle, pQueue); -#endif -} - -/* Pops (unqueues) an expired transfer descriptor from the queue - expired descriptors are in spent, error, or abort states */ -ROM_DMA_DESC_T *ROM_DMA_UnQueueDescriptor(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_DMAALT_API->UnQueueDescriptor(pHandle, pQueue); -#else - return dmaalt_api.UnQueueDescriptor(pHandle, pQueue); -#endif -} - -/* Starts or restarts a queue at the next descriptor chain */ -ErrorCode_t ROM_DMA_StartQueue(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_DMAALT_API->StartQueue(pHandle, pQueue); -#else - return dmaalt_api.StartQueue(pHandle, pQueue); -#endif -} - -/* Stops DMA and aborts current descriptor chain being processed in queue */ -ErrorCode_t ROM_DMA_StopQueue(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_DMAALT_API->StopQueue(pHandle, pQueue); -#else - return dmaalt_api.StopQueue(pHandle, pQueue); -#endif -} - -/* Stops DMA and completely flushes a transfer queue, queue is completely reset */ -void ROM_DMA_FlushQueue(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_DMAALT_API->FlushQueue(pHandle, pQueue); -#else - dmaalt_api.FlushQueue(pHandle, pQueue); -#endif -} - -/* Returns the current queue state (ROM_DMA_QUEUE_STATES_T) */ -uint8_t ROM_DMA_GetQueueState(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_DMAALT_API->GetQueueState(pHandle, pQueue); -#else - return dmaalt_api.GetQueueState(pHandle, pQueue); -#endif -} - -/* Forces a DMA transfer to trigger */ -void ROM_DMA_ForceTrigger(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_DMAALT_API->ForceTrigger(pHandle, pQueue); -#else - dmaalt_api.ForceTrigger(pHandle, pQueue); -#endif -} - -/* DMA controller (interrupt) handler */ -void ROM_DMA_DMAHandler(ROM_DMA_HANDLE_T pHandle) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_DMAALT_API->DMAHandler(pHandle); -#else - dmaalt_api.DMAHandler(pHandle); -#endif -} - -/* Return the DMA controller ROM driver version */ -uint16_t ROM_DMA_GetDriverVersion(void) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_DMAALT_API->GetDriverVersion(); -#else - return dmaalt_api.GetDriverVersion(); -#endif -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_dma.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_dma.h deleted file mode 100644 index a653f15c241..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_dma.h +++ /dev/null @@ -1,221 +0,0 @@ -/* - * @brief DMA controller ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __ROMAPI_DMA_H_ -#define __ROMAPI_DMA_H_ - -#include "hw_dmaaltd.h" - -/** @defgroup ROMAPI_DMA_WRAPPER CHIP: DMA controller ROM wrapper functions - * @ingroup ROMAPI_5410X - * @{ - */ - -/** @brief Minimum byte alignment value needed for the channel table. - * Use 4 for 4 byte alginment, 8 for 8 byte alignment, etc. */ -#define MINDMATABLEALIGN 512 - -/** @brief Number of DMA channels the DMA controller supports. */ -#define NUMDMACHANNELS 22 - -/** - * @brief Get memory size in bytes needed for DMA controller driver context - * @return Size in bytes needed for the ROM driver - */ -uint32_t ROM_DMA_GetMemSize(void); - -/** - * @brief Initialize DMA controller - * @param mem : Pointer to memory area used to driver context - * @param pInit : Pointer to DMA controller init data - * @return NULL on error, or a pointer to the device context handle - */ -ROM_DMA_HANDLE_T ROM_DMA_Init(void *mem, ROM_DMA_INIT_T *pInit); - -/** - * @brief Configures a DMA channel - * @param pHandle : Pointer to driver context handle - * @param pCfg : Pointer to DMA channel configuration structure - * @param dmaCh : DMA channel to configure - * @return LPC_OK if no errors occured, or an error code - */ -ErrorCode_t ROM_DMA_SetupChannel(ROM_DMA_HANDLE_T pHandle, ROM_DMA_CHAN_CFG_T *pCfg, uint8_t dmaCh); - -/** - * @brief Initialzies a transfer descriptor queue for a channel - * @param pHandle : Pointer to driver context handle - * @param dmaCh : DMA channel to configure - * @param pQueue : Pointer to a queue to initialize - * @return LPC_OK if no errors occured, or an error code - */ -ErrorCode_t ROM_DMA_InitQueue(ROM_DMA_HANDLE_T pHandle, uint8_t dmaCh, ROM_DMA_QUEUE_T *pQueue); - -/** - * @brief Registers an DMA controller callback for a queue - * @param pHandle : Pointer to driver context handle - * @param pQueue : Pointer to a queue - * @param cbIndex : Callback to register - * @param pCB : Pointer to callback function - * @return Nothing - */ -void ROM_DMA_RegisterQueueCallback(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue, uint32_t cbIndex, void *pCB); - -/** - * @brief Builds a transfer descriptor chain from the passed settings - * @param pHandle : Pointer to driver context handle - * @param pXferCfg : Pointer to the transfer configuration - * @param pDesc : Pointer to a descriptor to setup - * @param pDescPrev : Pointer to previous descriptor that will link to this one - * @return LPC_OK if no errors occured, or an error code - * @note When creating a DMA descriptor chain (more than 1 link), chain the descriptors - * together by passing the previous descriptor pointers for subsequenct calls to this function. - */ -ErrorCode_t ROM_DMA_BuildDescriptorChain(ROM_DMA_HANDLE_T pHandle, - ROM_DMA_XFERDESC_CFG_T *pXferCfg, - ROM_DMA_DESC_T *pDesc, - ROM_DMA_DESC_T *pDescPrev); - -/** - * @brief Returns the number of items transferred on the last descriptor chain (spent status only) - * @param pHandle : Pointer to driver context handle - * @param pDesc : Pointer to a descriptor chain to count - * @return LPC_OK if no errors occured, or an error code - */ -uint32_t ROM_DMA_GetTransferCount(ROM_DMA_HANDLE_T pHandle, ROM_DMA_DESC_T *pDesc); - -/** - * @brief Unstalls a descriptor chain that has been setup using the stallDesc option - * @param pHandle : Pointer to driver context handle - * @param pQueue : Pointer to a descriptor chain to unstall - * @return Nothing - * @note If a descriptor in a chain is setup with the stallDesc!=0 option in the - * @ref ROM_DMA_XFERDESC_CFG_T setup structure, the descriptor will stall when it - * is loaded. A stalled descriptor is ready to be processed, but won't start until a - * call to this fucntion is made. - */ -void ROM_DMA_UnstallDescriptorChain(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); - -/** - * @brief Queues a transfer descriptor chain - * @param pHandle : Pointer to driver context handle - * @param pQueue : Pointer to a queue - * @param pDescChainHead : Pointer to the start of a descriptor chain to queue - * @return Nothing - */ -void ROM_DMA_QueueDescriptor(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue, ROM_DMA_DESC_T *pDescChainHead); - -/** - * @brief Returns current status of next descriptor to be popped from the queue - * @param pHandle : Pointer to driver context handle - * @param pQueue : Pointer to a queue - * @return Pointer to next pop descriptor, or ROM_DMA_DESC_STS_INVALID if no descriptors exist to be popped - * @note Only descriptors that are spent, aborted, or have an error can be popped. Calling ROM_DMA_StopQueue() - * will abort the current descriptor in progress. This function returns the next descriptor that can be popped - * regardless of status without actually popping it. - */ -ROM_DMA_DESC_STS_T ROM_DMA_GetQueuePopDescriptorStatus(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); - -/** - * @brief Pops (unqueues) an expired transfer descriptor from the queue - expired descriptors are in spent, error, or abort states - * @param pHandle : Pointer to driver context handle - * @param pQueue : Pointer to a queue - * @return Pointer to popped descriptor, or NULL if no descriptors exist to be popped - * @note Only descriptors that are spent, aborted, or have an error can be popped. Calling ROM_DMA_StopQueue() - * will abort the current descriptor in progress. - */ -ROM_DMA_DESC_T *ROM_DMA_UnQueueDescriptor(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); - -/** - * @brief Starts or restarts a queue at the next descriptor chain - * @param pHandle : Pointer to driver context handle - * @param pQueue : Pointer to a queue - * @return LPC_OK if the queue is started or currently started, or an error code - */ -ErrorCode_t ROM_DMA_StartQueue(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); - -/** - * @brief Stops DMA and aborts current descriptor chain being processed in queue - * @param pHandle : Pointer to driver context handle - * @param pQueue : Pointer to a queue - * @return LPC_OK if the queue is stopped or already stopped, or an error code - * @note If multiple descriptor chains are queued up, this aborts the current one - * being processed in queueing, ready, or busy states. All descriptors after the aborted - * descriptor remain ready. - */ -ErrorCode_t ROM_DMA_StopQueue(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); - -/** - * @brief Stops DMA and completely flushes a transfer queue, queue is completely reset - * @param pHandle : Pointer to driver context handle - * @param pQueue : Pointer to a queue - * @return Nothing - * @note Flushes the entire queue of all descriptors and stops DMA. - */ -void ROM_DMA_FlushQueue(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); - -/** - * @brief Returns the current queue state (ROM_DMA_QUEUE_STATES_T) - * @param pHandle : Pointer to driver context handle - * @param pQueue : Pointer to a queue - * @return Current queue status (ROM_DMA_QUEUE_STATES_T) - */ -uint8_t ROM_DMA_GetQueueState(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); - -/** - * @brief Forces a DMA transfer to trigger - * @param pHandle : Pointer to driver context handle - * @param pQueue : Pointer to a queue - * @return Nothing - */ -void ROM_DMA_ForceTrigger(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue); - -/** - * @brief DMA controller (interrupt) handler - * @param pHandle : Pointer to driver context handle - * @return Nothing - * @note This function should be called from the DMA interrupt handler. - */ -void ROM_DMA_DMAHandler(ROM_DMA_HANDLE_T pHandle); - -/** - * @brief Return the DMA controller ROM driver version - * @return Driver version number - * @note The returned driver version number consists of a major and minor - * number, with the minor number in the lower 8 bits and the major number in - * the upper 8 bits. - */ -uint16_t ROM_DMA_GetDriverVersion(void); - -/** - * @} - */ - -#endif /* __ROMAPI_DMA_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_i2cm.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_i2cm.c deleted file mode 100644 index a68a27f74a0..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_i2cm.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * @brief I2C master ROM API declarations and functions - * These are the public ROM APIs and functions of the I2C master - * driver. - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "romapi_5410x.h" - -/* Get memory size in bytes needed for I2C master driver context */ -uint32_t ROM_I2CM_GetMemSize(void) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_I2CM_API->GetMemSize(); -#else - return i2cm_api.GetMemSize(); -#endif -} - -/* Initialize I2C master peripheral */ -ROM_I2CM_HANDLE_T ROM_I2CM_Init(void *mem, const ROM_I2CM_INIT_T *pInit) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_I2CM_API->Init(mem, pInit); -#else - return i2cm_api.Init(mem, pInit); -#endif -} - -/* Set I2C master clock rate */ -uint32_t ROM_I2CM_SetClockRate(ROM_I2CM_HANDLE_T pHandle, uint32_t inRate, uint32_t i2cRate) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_I2CM_API->SetClockRate(pHandle, inRate, i2cRate); -#else - return i2cm_api.SetClockRate(pHandle, inRate, i2cRate); -#endif -} - -/* Register a I2C master callback */ -void ROM_I2CM_RegisterCallback(ROM_I2CM_HANDLE_T pHandle, ROM_I2CM_CALLBACK_T cbIndex, void *pCB) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_I2CM_API->RegisterCallback(pHandle, cbIndex, pCB); -#else - i2cm_api.RegisterCallback(pHandle, cbIndex, pCB); -#endif -} - -/* Start a I2C master transfer */ -ErrorCode_t ROM_I2CM_Transfer(ROM_I2CM_HANDLE_T pHandle, ROM_I2CM_XFER_T *pXfer) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_I2CM_API->Transfer(pHandle, pXfer); -#else - return i2cm_api.Transfer(pHandle, pXfer); -#endif -} - -/* I2C master transfer (interrupt) handler */ -void ROM_I2CM_TransferHandler(ROM_I2CM_HANDLE_T pHandle) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_I2CM_API->TransferHandler(pHandle); -#else - i2cm_api.TransferHandler(pHandle); -#endif -} - -/* Return the I2C master ROM driver version */ -uint16_t ROM_I2CM_GetDriverVersion(void) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_I2CM_API->GetDriverVersion(); -#else - return i2cm_api.GetDriverVersion(); -#endif -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_i2cm.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_i2cm.h deleted file mode 100644 index 938ed00f215..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_i2cm.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * @brief I2C master ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __ROMAPI_I2CM_H_ -#define __ROMAPI_I2CM_H_ - -#include "hw_i2cmd.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup ROMAPI_I2CM_WRAPPER CHIP: I2C master ROM wrapper functions - * @ingroup ROMAPI_5410X - * @{ - */ - -/** - * @brief Get memory size in bytes needed for I2C master driver context - * @return Size in bytes needed for the ROM driver - */ -uint32_t ROM_I2CM_GetMemSize(void); - -/** - * @brief Initialize I2C master peripheral - * @param mem : Pointer to memory area used to driver context - * @param pInit : Pointer to I2C master init data - * @return NULL on error, or a pointer to the device context handle - */ -ROM_I2CM_HANDLE_T ROM_I2CM_Init(void *mem, const ROM_I2CM_INIT_T *pInit); - -/** - * @brief Set I2C master clock rate - * @param pHandle : Pointer to driver context handle - * @param inRate : Base clock rate for the I2C peripheral in Hz - * @param i2cRate : Desired I2C master clock rate - * @return Actual I2C master clock rate - */ -uint32_t ROM_I2CM_SetClockRate(ROM_I2CM_HANDLE_T pHandle, uint32_t inRate, uint32_t i2cRate); - -/** - * @brief Register a I2C master callback - * @param pHandle : Pointer to driver context handle - * @param cbIndex : Callback to register - * @param pCB : Pointer to callback function - * @return Nothing - */ -void ROM_I2CM_RegisterCallback(ROM_I2CM_HANDLE_T pHandle, ROM_I2CM_CALLBACK_T cbIndex, void *pCB); - -/** - * @brief Start a I2C master transfer - * @param pHandle : Pointer to driver context handle - * @param pXfer : Pointer to master transfer configuration - * @return Error code - * @note This function starts the transfer and returns immediately. - */ -ErrorCode_t ROM_I2CM_Transfer(ROM_I2CM_HANDLE_T pHandle, ROM_I2CM_XFER_T *pXfer); - -/** - * @brief I2C master transfer (interrupt) handler - * @param pHandle : Pointer to driver context handle - * @return Nothing - * @note This function should be called from the I2C interrupt handler and - * is used in interrupt and DMA modes. - */ -void ROM_I2CM_TransferHandler(ROM_I2CM_HANDLE_T pHandle); - -/** - * @brief Return the I2C master ROM driver version - * @return Driver version number - * @note The returned driver version number consists of a major and minor - * number, with the minor number in the lower 8 bits and the major number in - * the upper 8 bits. - */ -uint16_t ROM_I2CM_GetDriverVersion(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ROMAPI_I2CM_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_i2cmon.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_i2cmon.c deleted file mode 100644 index 5b76583a5c6..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_i2cmon.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * @brief I2C monitor ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "romapi_5410x.h" - -/* Get memory size in bytes needed for I2C monitor driver context */ -uint32_t ROM_I2CMON_GetMemSize(void) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_I2CMON_API->GetMemSize(); -#else - return i2cmon_api.GetMemSize(); -#endif -} - -/* Initialize I2C monitor peripheral */ -ROM_I2CMON_HANDLE_T ROM_I2CMON_Init(void *mem, ROM_I2CMON_INIT_T *pInit) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_I2CMON_API->Init(mem, pInit); -#else - return i2cmon_api.Init(mem, pInit); -#endif -} - -/* Register a I2C monitor callback */ -void ROM_I2CMON_RegisterCallback(ROM_I2CMON_HANDLE_T pHandle, ROM_I2CMON_CALLBACK_T cbIndex, void *pCB) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_I2CMON_API->RegisterCallback(pHandle, cbIndex, pCB); -#else - i2cmon_api.RegisterCallback(pHandle, cbIndex, pCB); -#endif -} - -/* Start I2C monitoring */ -ErrorCode_t ROM_I2CMON_StartLog(ROM_I2CMON_HANDLE_T pHandle, ROM_I2CMON_CAP_T *pCap) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_I2CMON_API->StartLog(pHandle, pCap); -#else - return i2cmon_api.StartLog(pHandle, pCap); -#endif -} - -/* I2C monitor transfer (interrupt) handler */ -void ROM_I2CMON_TransferHandler(ROM_I2CMON_HANDLE_T pHandle) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_I2CMON_API->TransferHandler(pHandle); -#else - i2cmon_api.TransferHandler(pHandle); -#endif -} - -/* Return the I2C monitor ROM driver version */ -uint16_t ROM_I2CMON_GetDriverVersion(void) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_I2CMON_API->GetDriverVersion(); -#else - return i2cmon_api.GetDriverVersion(); -#endif -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_i2cmon.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_i2cmon.h deleted file mode 100644 index 9dd3cafbfa2..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_i2cmon.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * @brief I2C monitor ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __ROMAPI_I2CMON_H_ -#define __ROMAPI_I2CMON_H_ - -#include "hw_i2cmond.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup ROMAPI_I2CMON_WRAPPER CHIP: I2C monitor ROM wrapper functions - * @ingroup ROMAPI_5410X - * @{ - */ - -/** - * @brief Get memory size in bytes needed for I2C monitor driver context - * @return Size in bytes needed for the ROM driver - */ -uint32_t ROM_I2CMON_GetMemSize(void); - -/** - * @brief Initialize I2C monitor peripheral - * @param mem : Pointer to memory area used to driver context - * @param pInit : Pointer to I2C monitor init data - * @return NULL on error, or a pointer to the device context handle - */ -ROM_I2CMON_HANDLE_T ROM_I2CMON_Init(void *mem, ROM_I2CMON_INIT_T *pInit); - -/** - * @brief Register a I2C monitor callback - * @param pHandle : Pointer to driver context handle - * @param cbIndex : Callback to register - * @param pCB : Pointer to callback function - * @return Nothing - */ -void ROM_I2CMON_RegisterCallback(ROM_I2CMON_HANDLE_T pHandle, ROM_I2CMON_CALLBACK_T cbIndex, void *pCB); - -/** - * @brief Start I2C monitoring - * @param pHandle : Pointer to driver context handle - * @param pCap : Pointer to capture monitor configuration - * @return Error code - * @note This function starts the transfer and returns immediately. - */ -ErrorCode_t ROM_I2CMON_StartLog(ROM_I2CMON_HANDLE_T pHandle, ROM_I2CMON_CAP_T *pCap); - -/** - * @brief I2C monitor transfer (interrupt) handler - * @param pHandle : Pointer to driver context handle - * @return Nothing - * @note This function should be called from the I2C interrupt handler and - * is used in interrupt and DMA modes. - */ -void ROM_I2CMON_TransferHandler(ROM_I2CMON_HANDLE_T pHandle); - -/** - * @brief Return the I2C monitor ROM driver version - * @return Driver version number - * @note The returned driver version number consists of a major and minor - * number, with the minor number in the lower 8 bits and the major number in - * the upper 8 bits. - */ -uint16_t ROM_I2CMON_GetDriverVersion(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ROMAPI_I2CMON_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_i2cs.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_i2cs.c deleted file mode 100644 index edc0721b6cb..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_i2cs.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * @brief I2C slave ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "romapi_5410x.h" - -/* Get memory size in bytes needed for I2C slave driver context */ -uint32_t ROM_I2CS_GetMemSize(void) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_I2CS_API->GetMemSize(); -#else - return i2cs_api.GetMemSize(); -#endif -} - -/* Initialize I2C slave peripheral */ -ROM_I2CS_HANDLE_T ROM_I2CS_Init(void *mem, ROM_I2CS_INIT_T *pInit) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_I2CS_API->Init(mem, pInit); -#else - return i2cs_api.Init(mem, pInit); -#endif -} - -/* Set I2C slave clock rate */ -void ROM_I2CS_SetupSlave(ROM_I2CS_HANDLE_T pHandle, ROM_I2CS_SLAVE_T *pSlaveSetup) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_I2CS_API->SetupSlave(pHandle, pSlaveSetup); -#else - i2cs_api.SetupSlave(pHandle, pSlaveSetup); -#endif -} - -/* Register a I2C slave callback */ -void ROM_I2CS_RegisterCallback(ROM_I2CS_HANDLE_T pHandle, ROM_I2CS_CALLBACK_T cbIndex, void *pCB) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_I2CS_API->RegisterCallback(pHandle, cbIndex, pCB); -#else - i2cs_api.RegisterCallback(pHandle, cbIndex, pCB); -#endif -} - -/* Start a I2C slave transfer */ -ErrorCode_t ROM_I2CS_Transfer(ROM_I2CS_HANDLE_T pHandle, ROM_I2CS_XFER_T *pXfer) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_I2CS_API->Transfer(pHandle, pXfer); -#else - return i2cs_api.Transfer(pHandle, pXfer); -#endif -} - -/* I2C slave transfer (interrupt) handler */ -void ROM_I2CS_TransferHandler(ROM_I2CS_HANDLE_T pHandle) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_I2CS_API->TransferHandler(pHandle); -#else - i2cs_api.TransferHandler(pHandle); -#endif -} - -/* Return the I2C slave ROM driver version */ -uint16_t ROM_I2CS_GetDriverVersion(void) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_I2CS_API->GetDriverVersion(); -#else - return i2cs_api.GetDriverVersion(); -#endif -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_i2cs.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_i2cs.h deleted file mode 100644 index 416e7e58179..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_i2cs.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * @brief I2C slave ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __ROMAPI_I2CS_H_ -#define __ROMAPI_I2CS_H_ - -#include "hw_i2csd.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup ROMAPI_I2CS_WRAPPER CHIP: I2C slave ROM wrapper functions - * @ingroup ROMAPI_5410X - * @{ - */ - -/** - * @brief Get memory size in bytes needed for I2C slave driver context - * @return Size in bytes needed for the ROM driver - */ -uint32_t ROM_I2CS_GetMemSize(void); - -/** - * @brief Initialize I2C slave peripheral - * @param mem : Pointer to memory area used to driver context - * @param pInit : Pointer to I2C slave init data - * @return NULL on error, or a pointer to the device context handle - */ -ROM_I2CS_HANDLE_T ROM_I2CS_Init(void *mem, ROM_I2CS_INIT_T *pInit); - -/** - * @brief Set I2C slave clock rate - * @param pHandle : Pointer to driver context handle - * @param pSlaveSetup : Slave setup data - * @return Nothing - * @note See the use model for more information on how to setup slave addresses. - */ -void ROM_I2CS_SetupSlave(ROM_I2CS_HANDLE_T pHandle, ROM_I2CS_SLAVE_T *pSlaveSetup); - -/** - * @brief Register a I2C slave callback - * @param pHandle : Pointer to driver context handle - * @param cbIndex : Callback to register - * @param pCB : Pointer to callback function - * @return Nothing - */ -void ROM_I2CS_RegisterCallback(ROM_I2CS_HANDLE_T pHandle, ROM_I2CS_CALLBACK_T cbIndex, void *pCB); - -/** - * @brief Queues an I2C slave transfer - * @param pHandle : Pointer to driver context handle - * @param pXfer : Pointer to slave transfer configuration - * @return Always returns LPC_OK - * @note This functions never blocks. - */ -ErrorCode_t ROM_I2CS_Transfer(ROM_I2CS_HANDLE_T pHandle, ROM_I2CS_XFER_T *pXfer); - -/** - * @brief I2C slave transfer (interrupt) handler - * @param pHandle : Pointer to driver context handle - * @return Nothing - * @note This function should be called from the I2C interrupt handler and - * is used in interrupt and DMA modes. - */ -void ROM_I2CS_TransferHandler(ROM_I2CS_HANDLE_T pHandle); - -/** - * @brief Return the I2C slave ROM driver version - * @return Driver version number - * @note The returned driver version number consists of a major and minor - * number, with the minor number in the lower 8 bits and the major number in - * the upper 8 bits. - */ -uint16_t ROM_I2CS_GetDriverVersion(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ROMAPI_I2CS_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_spim.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_spim.c deleted file mode 100644 index 83b6b12e97e..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_spim.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * @brief SPI master ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "romapi_5410x.h" - -/* Get memory size in bytes needed for SPI master driver context */ -uint32_t ROM_SPIM_GetMemSize(void) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_SPIM_API->GetMemSize(); -#else - return spim_api.GetMemSize(); -#endif -} - -/* Initialize SPI master peripheral */ -ROM_SPIM_HANDLE_T ROM_SPIM_Init(void *mem, ROM_SPIM_INIT_T *pInit) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_SPIM_API->Init(mem, pInit); -#else - return spim_api.Init(mem, pInit); -#endif -} - -void ROM_SPIM_RegisterCallback(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_CALLBACK_T cbIndex, void *pCB) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_SPIM_API->RegisterCallback(pHandle, cbIndex, pCB); -#else - spim_api.RegisterCallback(pHandle, cbIndex, pCB); -#endif -} - -ErrorCode_t ROM_SPIM_SetupTransfer(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_XFER_CONFIG_T *pCfg) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_SPIM_API->SetupTransfer(pHandle, pCfg); -#else - return spim_api.SetupTransfer(pHandle, pCfg); -#endif -} - -ErrorCode_t ROM_SPIM_Transfer(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_XFER_T *pXfer) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_SPIM_API->Transfer(pHandle, pXfer); -#else - return spim_api.Transfer(pHandle, pXfer); -#endif -} - -void ROM_SPIM_TransferHandler(ROM_SPIM_HANDLE_T pHandle) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_SPIM_API->TransferHandler(pHandle); -#else - spim_api.TransferHandler(pHandle); -#endif -} - -void ROM_SPIM_ClosePendingTransfer(ROM_SPIM_HANDLE_T pHandle) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_SPIM_API->ClosePendingTransfer(pHandle); -#else - spim_api.ClosePendingTransfer(pHandle); -#endif -} - -/* Return the SPI master ROM driver version */ -uint16_t ROM_SPIM_GetDriverVersion(void) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_SPIM_API->GetDriverVersion(); -#else - return spim_api.GetDriverVersion(); -#endif -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_spim.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_spim.h deleted file mode 100644 index faba2251bac..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_spim.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * @brief SPI master ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __ROMAPI_SPIM_H_ -#define __ROMAPI_SPIM_H_ - -#include "hw_spimd.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup ROMAPI_SPIM_WRAPPER CHIP: SPI master ROM wrapper functions - * @ingroup ROMAPI_5410X - * @{ - */ - -/** - * @brief Get memory size in bytes needed for SPI master driver context - * @return Size in bytes needed for the ROM driver - */ -uint32_t ROM_SPIM_GetMemSize(void); - -/** - * @brief Initialize SPI master peripheral - * @param mem : Pointer to memory area used to driver context - * @param pInit : Pointer to SPI master init data - * @return NULL on error, or a pointer to the device context handle - */ -ROM_SPIM_HANDLE_T ROM_SPIM_Init(void *mem, ROM_SPIM_INIT_T *pInit); - -/** - * @brief Register a SPI master callback - * @param pHandle : Pointer to driver context handle - * @param cbIndex : Callback to register - * @param pCB : Pointer to callback function - * @return Nothing - */ -void ROM_SPIM_RegisterCallback(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_CALLBACK_T cbIndex, void *pCB); - -ErrorCode_t ROM_SPIM_SetupTransfer(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_XFER_CONFIG_T *pCfg); - -/** - * @brief Start a SPI master transfer - * @param pHandle : Pointer to driver context handle - * @param pXfer : Pointer to master transfer configuration - * @return Error code - * @note This function starts the transfer and returns immediately. - */ -ErrorCode_t ROM_SPIM_Transfer(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_XFER_T *pXfer); - -/** - * @brief SPI master transfer (interrupt) handler - * @param pHandle : Pointer to driver context handle - * @return Nothing - * @note This function should be called from the SPI interrupt handler and - * is used in interrupt and DMA modes. - */ -void ROM_SPIM_TransferHandler(ROM_SPIM_HANDLE_T pHandle); - -/** - * @brief Safely stop a SPI master transfer - * @param pHandle : Pointer to driver context handle - * @return Nothing - * @note This function completes the SPI transfer at the next possible - * transfer completion state. This should be called when DMA is used and - * DMA transfer is complete, or whenever the transfer neesd to be aborted. - * It will safely transmit any data already inside the SPI transmit FIFOs - * before stopping. - */ -void ROM_SPIM_ClosePendingTransfer(ROM_SPIM_HANDLE_T pHandle); - -/** - * @brief Return the SPI master ROM driver version - * @return Driver version number - * @note The returned driver version number consists of a major and minor - * number, with the minor number in the lower 8 bits and the major number in - * the upper 8 bits. - */ -uint16_t ROM_SPIM_GetDriverVersion(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ROMAPI_SPIM_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_spis.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_spis.c deleted file mode 100644 index 934ce64e70d..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_spis.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * @brief SPI slave ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "romapi_5410x.h" - -/* Get memory size in bytes needed for SPI slave driver context */ -uint32_t ROM_SPIS_GetMemSize(void) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_SPIS_API->GetMemSize(); -#else - return spis_api.GetMemSize(); -#endif -} - -/* Initialize SPI slave peripheral */ -ROM_SPIS_HANDLE_T ROM_SPIS_Init(void *mem, ROM_SPIS_INIT_T *pInit) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_SPIS_API->Init(mem, pInit); -#else - return spis_api.Init(mem, pInit); -#endif -} - -void ROM_SPIS_RegisterCallback(ROM_SPIS_HANDLE_T pHandle, ROM_SPIS_CALLBACK_T cbIndex, void *pCB) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_SPIS_API->RegisterCallback(pHandle, cbIndex, pCB); -#else - spis_api.RegisterCallback(pHandle, cbIndex, pCB); -#endif -} - -ErrorCode_t ROM_SPIS_SetupSlave(ROM_SPIS_HANDLE_T pHandle, ROM_SPIS_SLAVE_T *pSlaveSetup) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_SPIS_API->SetupSlave(pHandle, pSlaveSetup); -#else - return spis_api.SetupSlave(pHandle, pSlaveSetup); -#endif -} - -ErrorCode_t ROM_SPIS_Transfer(ROM_SPIS_HANDLE_T pHandle, ROM_SPIS_XFER_T *pXfer) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_SPIS_API->Transfer(pHandle, pXfer); -#else - return spis_api.Transfer(pHandle, pXfer); -#endif -} - -void ROM_SPIS_TransferHandler(ROM_SPIS_HANDLE_T pHandle) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_SPIS_API->TransferHandler(pHandle); -#else - spis_api.TransferHandler(pHandle); -#endif -} - -/* Return the SPI slave ROM driver version */ -uint16_t ROM_SPIS_GetDriverVersion(void) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_SPIS_API->GetDriverVersion(); -#else - return spis_api.GetDriverVersion(); -#endif -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_spis.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_spis.h deleted file mode 100644 index 9418fab3acd..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_spis.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * @brief SPI slave ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __ROMAPI_SPIS_H_ -#define __ROMAPI_SPIS_H_ - -#include "hw_spisd.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup ROMAPI_SPIS_WRAPPER CHIP: SPI slave ROM wrapper functions - * @ingroup ROMAPI_5410X - * @{ - */ - -/** - * @brief Get memory size in bytes needed for SPI slave driver context - * @return Size in bytes needed for the ROM driver - */ -uint32_t ROM_SPIS_GetMemSize(void); - -/** - * @brief Initialize SPI slave peripheral - * @param mem : Pointer to memory area used to driver context - * @param pInit : Pointer to SPI slave init data - * @return NULL on error, or a pointer to the device context handle - */ -ROM_SPIS_HANDLE_T ROM_SPIS_Init(void *mem, ROM_SPIS_INIT_T *pInit); - -/** - * @brief Register a SPI slave callback - * @param pHandle : Pointer to driver context handle - * @param cbIndex : Callback to register - * @param pCB : Pointer to callback function - * @return Nothing - */ -void ROM_SPIS_RegisterCallback(ROM_SPIS_HANDLE_T pHandle, ROM_SPIS_CALLBACK_T cbIndex, void *pCB); - -/** - * @brief Setup SPI slave transfer configuration - * @param pHandle : Pointer to driver context handle - * @param pSlaveSetup : Slave setup data - * @return Error code - * @note Sets up the slave interface configuration for a transfer. - */ -ErrorCode_t ROM_SPIS_SetupSlave(ROM_SPIS_HANDLE_T pHandle, ROM_SPIS_SLAVE_T *pSlaveSetup); - -/** - * @brief Start a SPI slave transfer - * @param pHandle : Pointer to driver context handle - * @param pXfer : Pointer to slave transfer configuration - * @return Error code - * @note This function starts the transfer and returns immediately. - */ -ErrorCode_t ROM_SPIS_Transfer(ROM_SPIS_HANDLE_T pHandle, ROM_SPIS_XFER_T *pXfer); - -/** - * @brief SPI slave transfer (interrupt) handler - * @param pHandle : Pointer to driver context handle - * @return Nothing - * @note This function should be called from the SPI interrupt handler and - * is used in interrupt and DMA modes. - */ -void ROM_SPIS_TransferHandler(ROM_SPIS_HANDLE_T pHandle); - -/** - * @brief Return the SPI slave ROM driver version - * @return Driver version number - * @note The returned driver version number consists of a major and minor - * number, with the minor number in the lower 8 bits and the major number in - * the upper 8 bits. - */ -uint16_t ROM_SPIS_GetDriverVersion(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ROMAPI_SPIS_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_uart.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_uart.c deleted file mode 100644 index 8c6e2ac331a..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_uart.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * @brief UART ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "romapi_5410x.h" - -/* Get memory size in bytes needed for ADC driver context */ -uint32_t ROM_UART_GetMemSize(void) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_UART_API->GetMemSize(); -#else - return uartrom_api.GetMemSize(); -#endif -} - -/* Initialize the UART ROM driver */ -UART_HANDLE_T ROM_UART_Init(void *pMem, uint32_t baseAddr, void *pUserData) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_UART_API->Init(pMem, baseAddr, pUserData); -#else - return uartrom_api.Init(pMem, baseAddr, pUserData); -#endif -} - -/* Configure the UART peripheral */ -ErrorCode_t ROM_UART_Configure(UART_HANDLE_T hUART, const UART_CFG_T *pCfg) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_UART_API->Configure(hUART, pCfg); -#else - return uartrom_api.Configure(hUART, pCfg); -#endif -} - -/* Calculate baudrate dividers and oversampling values */ -ErrorCode_t ROM_UART_CalBaud(UART_BAUD_T *baud) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_UART_API->CalBaud(baud); -#else - return uartrom_api.CalBaud(baud); -#endif -} - -/* Set/Clear special control operations like BREAK, IDLE, etc., */ -void ROM_UART_SetCtrl(UART_HANDLE_T hUART, uint32_t cfgVal) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_UART_API->SetCtrl(hUART, cfgVal); -#else - uartrom_api.SetCtrl(hUART, cfgVal); -#endif -} - -/* Registers an UART callback function */ -ErrorCode_t ROM_UART_RegisterCB(UART_HANDLE_T hUART, UART_CBINDEX_T cbIndex, void (*pCbFunc)(UART_HANDLE_T, - UART_EVENT_T, - void *)) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_UART_API->RegisterCB(hUART, cbIndex, pCbFunc); -#else - return uartrom_api.RegisterCB(hUART, cbIndex, pCbFunc); -#endif -} - -/* UART Event handler, should be called from the ISR */ -void ROM_UART_Handler(UART_HANDLE_T hUART) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_UART_API->Handler(hUART); -#else - uartrom_api.Handler(hUART); -#endif -} - -/* Send data to UART */ -ErrorCode_t ROM_UART_Send(UART_HANDLE_T hUART, const void *buffer, uint16_t size) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_UART_API->Send(hUART, buffer, size); -#else - return uartrom_api.Send(hUART, buffer, size); -#endif -} - -/* Receive data from UART */ -ErrorCode_t ROM_UART_Receive(UART_HANDLE_T hUART, void *buffer, uint16_t size) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_UART_API->Receive(hUART, buffer, size); -#else - return uartrom_api.Receive(hUART, buffer, size); -#endif -} - -/* Wait for UART TX to complete; Used for polling */ -void ROM_UART_WaitTx(UART_HANDLE_T hUART) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_UART_API->WaitTx(hUART); -#else - uartrom_api.WaitTx(hUART); -#endif -} - -/* Wait for UART data receive to complete; Used for polling */ -void ROM_UART_WaitRx(UART_HANDLE_T hUART) -{ -#if defined(ROMDRIVERSV2_PRESENT) - ROMAPI_UART_API->WaitRx(hUART); -#else - uartrom_api.WaitRx(hUART); -#endif -} - -/* Get Current verion of the UART ROM driver */ -uint16_t ROM_UART_GetDriverVersion(void) -{ -#if defined(ROMDRIVERSV2_PRESENT) - return ROMAPI_UART_API->GetDriverVersion(); -#else - return uartrom_api.GetDriverVersion(); -#endif -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_uart.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_uart.h deleted file mode 100644 index 2a1da9c91bf..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_uart.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * @brief UART ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __ROMAPI_UART_H_ -#define __ROMAPI_UART_H_ - -#include "hw_uart_rom_api.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup ROMAPI_UART_WRAPPER CHIP: UART ROM wrapper functions - * @ingroup ROMAPI_5410X - * @{ - */ - -/** - * @brief Get memory size in bytes needed for SPI master driver context - * @return Size in bytes needed for the ROM driver - */ -uint32_t ROM_UART_GetMemSize(void); - -/** - * @brief Initialize UART ROM Driver - * @param pMem : Pointer to memory area for driver context - * @param baseAddr : Base address of the UART peripheral - * @param pUserData : Pointer to User Data - * @return Pointer to the device context handle or NULL on alignment failure - * @note Parameter @a pMem must be a pointer to word aligned memory - * if the pointer is not word aligned (4-Byte) the function returns - * NULL. - */ -UART_HANDLE_T ROM_UART_Init(void *pMem, uint32_t baseAddr, void *pUserData); - -/** - * @brief Configure the UART peripheral - * @param hUART : Handle to UART obtained using ROM_UART_Init() - * @param pCfg : Pointer to configuration structure #UART_CFG_T - * @return LPC_OK on Success, ERR_UART_PARAM if any of cfg values are invalid - */ -ErrorCode_t ROM_UART_Configure(UART_HANDLE_T hUART, const UART_CFG_T *pCfg); - -/** - * @brief Calculate UART Baud rate parameters - * @param baud : [IN/OUT] Pointer to baud rate structure - * @return LPC_OK on Success, ERR_UART_BAUDRATE baudrate for given frequency is not within limits - * @sa UART_BAUD_T - */ -ErrorCode_t ROM_UART_CalBaud(UART_BAUD_T *baud); - -/** - * @brief Set UART Control operations - * @param hUART : Handle to UART obtained using ROM_UART_Init() - * @param cfgVal : Configuration value (one or more (OR'ed) values of #UART_BREAK_ON, #UART_TX_PAUSE etc) - * @return Nothing - * @note - * To set TX in BREAK state, use ROM_UART_SetCtrl(hUART, UART_BREAK_ON), to bring TX out of BREAK state - * use ROM_UART_SetCtrl(hUART, UART_BREAK_OFF). Us the above method will set TX line to BREAK state even - * if there is a data is being sent, hence the receiver might get a UART FRAME error and the data in progress might - * get lost. To avoid this application can pause TX before the TX gets to BREAK state by calling, - * ROM_UART_SetCtrl(hUART, #UART_BREAK_ON | #UART_TX_PAUSE) and release the break by calling - * ROM_UART_SetCtrl(hUART, #UART_BREAK_OFF | #UART_TX_RESUME).
- * ROM_UART_SetCtrl(hUART, #UART_TX_PAUSE) will stop the TX until ROM_UART_SetCtrl(hUART, - * #UART_TX_RESUME) * this could be used to implement flow-control. - */ -void ROM_UART_SetCtrl(UART_HANDLE_T hUART, uint32_t cfgVal); - -/** - * @brief Registers a callback function associated with an event - * @param hUART : Handle to UART obtained using ROM_UART_Init() - * @param cbIndex : Index of the call-back function (Associated with an event) - * @param pCbFunc : Pointer to callback function - * @return Success or failure - * @retval LPC_OK Callback successfully registered - * @retval ERR_UART_PARAM Invaild event parameter for @a cbIndex - */ -ErrorCode_t ROM_UART_RegisterCB(UART_HANDLE_T hUART, UART_CBINDEX_T cbIndex, void (*pCbFunc)(UART_HANDLE_T, - UART_EVENT_T, - void *)); - -/** - * @brief UART Event handler function (Usually called from interrupt handler) - * @param hUART : Handle to UART obtained using ROM_UART_Init() - * @return Nothing - */ -void ROM_UART_Handler(UART_HANDLE_T hUART); - -/** - * @brief Send data to UART - * @param hUART : Handle to UART obtained using ROM_UART_Init() - * @param buffer : Buffer to send - * @param size : Number of items in buffer - * @return LPC_OK when buffer is queued successfully for sending - * @note If the UART Data size is 9, then buffer should be of type - * uint16_t *, size should be number of uint16_t (not size in bytes). - */ -ErrorCode_t ROM_UART_Send(UART_HANDLE_T hUART, const void *buffer, uint16_t size); - -/** - * @brief Receive data from UART - * @param hUART : Handle to UART obtained using ROM_UART_Init() - * @param buffer : Buffer to send - * @param size : Number of items in buffer - * @return LPC_OK when buffer is queued successfully for receiving data - * @note If the UART Data size is 9, then buffer should be of type - * uint16_t *, size should be number of uint16_t (not size in bytes). - */ -ErrorCode_t ROM_UART_Receive(UART_HANDLE_T hUART, void *buffer, uint16_t size); - -/** - * @brief Send data to UART [Blocking] - * @param hUART : Handle to UART obtained using ROM_UART_Init() - * @param buffer : Buffer to send - * @param size : Number of items in buffer - * @return LPC_OK when buffer is queued successfully for sending - * @note If the UART Data size is 9, then buffer should be of type - * uint16_t *, size should be number of uint16_t (not size in bytes). - * This API is not in the ROM this is a wrapper API, that uses - * @a ROM_UART_Send() and @a ROM_UART_FlushTx() - */ -ErrorCode_t ROM_UART_SendBlock(UART_HANDLE_T hUART, const void *buffer, uint16_t size); - -/** - * @brief Receive data from UART [Blocking] - * @param hUART : Handle to UART obtained using ROM_UART_Init() - * @param buffer : Buffer to send - * @param size : Number of items in buffer - * @return LPC_OK when buffer is queued successfully for receiving data - * @note If the UART Data size is 9, then buffer should be of type - * uint16_t *, size should be number of uint16_t (not size in bytes). - * This API is not in the ROM this is a wrapper API, that uses - * @a ROM_UART_Receive() and @a ROM_UART_FetchRx() - */ -ErrorCode_t ROM_UART_ReceiveBlock(UART_HANDLE_T hUART, void *buffer, uint16_t size); - -/** - * @brief Wait for the current TX buffer to be sent - * @param hUART : Handle to UART obtained using ROM_UART_Init() - * @return Nothing - * @note This call will bock the excution till all the data bytes are sent. - * @sa ROM_UART_Send() - */ -void ROM_UART_WaitTx(UART_HANDLE_T hUART); - -/** - * @brief Complete the current Receive transfer - * @param hUART : Handle to UART obtained using ROM_UART_Init() - * @return Nothing - * @note This call will bock the excution till all the data bytes are read, - * if there is no RX in progress this call will read and discard the current - * pending RX data and the incoming data until there is no data coming from uart - * atleast for one data time, mainly used for discarding UART frames that had - * started arriving and overflown before the ROM_UART_Receive was called. - * @sa ROM_UART_Receive() - */ -void ROM_UART_WaitRx(UART_HANDLE_T hUART); - -/** - * @brief Return the UART ROM driver version - * @return Driver version number - * @note The returned driver version number consists of a major and minor - * number, with the minor number in the lower 8 bits and the major number in - * the upper 8 bits. - */ -uint16_t ROM_UART_GetDriverVersion(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ROMAPI_UART_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/rtc_5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/rtc_5410x.c deleted file mode 100644 index 4426dfb231f..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/rtc_5410x.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * @brief LPC5410X RTC chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/rtc_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/rtc_5410x.h deleted file mode 100644 index 3c6743e4d55..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/rtc_5410x.h +++ /dev/null @@ -1,310 +0,0 @@ -/* - * @brief LPC5410X RTC chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __RTC_5410X_H_ -#define __RTC_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup RTC_5410X CHIP: LPC5410X Real Time clock - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/** - * @brief LPC5410X Real Time clock register block structure - */ -typedef struct { /*!< RTC */ - __IO uint32_t CTRL; /*!< RTC control register */ - __IO uint32_t MATCH; /*!< PRTC match (alarm) register */ - __IO uint32_t COUNT; /*!< RTC counter register */ - __IO uint32_t WAKE; /*!< RTC high-resolution/wake-up timer control register */ -} LPC_RTC_T; - -/* CTRL register defniitions */ -#define RTC_CTRL_SWRESET (1 << 0) /*!< Apply reset to RTC */ -#define RTC_CTRL_OFD (1 << 1) /*!< Oscillator fail detect status (failed bit) */ -#define RTC_CTRL_ALARM1HZ (1 << 2) /*!< RTC 1 Hz timer alarm flag status (match) bit */ -#define RTC_CTRL_WAKE1KHZ (1 << 3) /*!< RTC 1 kHz timer wake-up flag status (timeout) bit */ -#define RTC_CTRL_ALARMDPD_EN (1 << 4) /*!< RTC 1 Hz timer alarm for Deep power-down enable bit */ -#define RTC_CTRL_WAKEDPD_EN (1 << 5) /*!< RTC 1 kHz timer wake-up for Deep power-down enable bit */ -#define RTC_CTRL_RTC1KHZ_EN (1 << 6) /*!< RTC 1 kHz clock enable bit */ -#define RTC_CTRL_RTC_EN (1 << 7) /*!< RTC enable bit */ -#define RTC_CTRL_MASK ((uint32_t) 0xF1) /*!< RTC Control register Mask for reserved and status bits */ - -/** - * @brief Initialize the RTC peripheral - * @param pRTC : RTC peripheral selected - * @return None - */ -STATIC INLINE void Chip_RTC_Init(LPC_RTC_T *pRTC) -{ - Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_RTC); - Chip_SYSCON_PeriphReset(RESET_RTC); -} - -/** - * @brief De-initialize the RTC peripheral - * @param pRTC : RTC peripheral selected - * @return None - */ -STATIC INLINE void Chip_RTC_DeInit(LPC_RTC_T *pRTC) -{ - Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_RTC); -} - -/** - * @brief Enable RTC options - * @param pRTC : The base address of RTC block - * @param flags : And OR'ed value of RTC_CTRL_* definitions to enable - * @return Nothing - * @note You can enable multiple RTC options at once using this function - * by OR'ing them together. It is recommended to only use the - * RTC_CTRL_ALARMDPD_EN, RTC_CTRL_WAKEDPD_EN, RTC_CTRL_RTC1KHZ_EN, and - * RTC_CTRL_RTC_EN flags with this function. - */ -STATIC INLINE void Chip_RTC_EnableOptions(LPC_RTC_T *pRTC, uint32_t flags) -{ - pRTC->CTRL = (pRTC->CTRL & RTC_CTRL_MASK) | flags; -} - -/** - * @brief Disable RTC options - * @param pRTC : The base address of RTC block - * @param flags : And OR'ed value of RTC_CTRL_* definitions to disable - * @return Nothing - * @note You can enable multiple RTC options at once using this function - * by OR'ing them together. It is recommended to only use the - * RTC_CTRL_ALARMDPD_EN, RTC_CTRL_WAKEDPD_EN, RTC_CTRL_RTC1KHZ_EN, and - * RTC_CTRL_RTC_EN flags with this function. - */ -STATIC INLINE void Chip_RTC_DisableOptions(LPC_RTC_T *pRTC, uint32_t flags) -{ - pRTC->CTRL = (pRTC->CTRL & RTC_CTRL_MASK) & ~flags; -} - -/** - * @brief Reset RTC - * @param pRTC : The base address of RTC block - * @return Nothing - * @note The RTC state will be returned to it's default. - */ -STATIC INLINE void Chip_RTC_Reset(LPC_RTC_T *pRTC) -{ - Chip_RTC_EnableOptions(pRTC, RTC_CTRL_SWRESET); - Chip_RTC_DisableOptions(pRTC, RTC_CTRL_SWRESET); -} - -/** - * @brief Enables the RTC - * @param pRTC : The base address of RTC block - * @return Nothing - * @note You can also use Chip_RTC_EnableOptions() with the - * RTC_CTRL_RTC_EN flag to enable the RTC. - */ -STATIC INLINE void Chip_RTC_Enable(LPC_RTC_T *pRTC) -{ - Chip_RTC_EnableOptions(pRTC, RTC_CTRL_RTC_EN); -} - -/** - * @brief Disables the RTC - * @param pRTC : The base address of RTC block - * @return Nothing - * @note You can also use Chip_RTC_DisableOptions() with the - * RTC_CTRL_RTC_EN flag to enable the RTC. - */ -STATIC INLINE void Chip_RTC_Disable(LPC_RTC_T *pRTC) -{ - Chip_RTC_DisableOptions(pRTC, RTC_CTRL_RTC_EN); -} - -/** - * @brief Enables the RTC 1KHz high resolution timer - * @param pRTC : The base address of RTC block - * @return Nothing - * @note You can also use Chip_RTC_EnableOptions() with the - * RTC_CTRL_RTC1KHZ_EN flag to enable the high resolution - * timer. - */ -STATIC INLINE void Chip_RTC_Enable1KHZ(LPC_RTC_T *pRTC) -{ - Chip_RTC_EnableOptions(pRTC, RTC_CTRL_RTC1KHZ_EN); -} - -/** - * @brief Disables the RTC 1KHz high resolution timer - * @param pRTC : The base address of RTC block - * @return Nothing - * @note You can also use Chip_RTC_DisableOptions() with the - * RTC_CTRL_RTC1KHZ_EN flag to disable the high resolution - * timer. - */ -STATIC INLINE void Chip_RTC_Disable1KHZ(LPC_RTC_T *pRTC) -{ - Chip_RTC_DisableOptions(pRTC, RTC_CTRL_RTC1KHZ_EN); -} - -/** - * @brief Enables selected RTC wakeup events - * @param pRTC : The base address of RTC block - * @param ints : Wakeup events to enable - * @return Nothing - * @note Select either one or both (OR'ed) RTC_CTRL_ALARMDPD_EN - * and RTC_CTRL_WAKEDPD_EN values to enabled. You can also - * use Chip_RTC_EnableOptions() with the flags to enable - * the events. - */ -STATIC INLINE void Chip_RTC_EnableWakeup(LPC_RTC_T *pRTC, uint32_t ints) -{ - Chip_RTC_EnableOptions(pRTC, ints); -} - -/** - * @brief Disables selected RTC wakeup events - * @param pRTC : The base address of RTC block - * @param ints : Wakeup events to disable - * @return Nothing - * @note Select either one or both (OR'ed) RTC_CTRL_ALARMDPD_EN - * and RTC_CTRL_WAKEDPD_EN values to disabled. You can also - * use Chip_RTC_DisableOptions() with the flags to disable - * the events. - */ -STATIC INLINE void Chip_RTC_DisableWakeup(LPC_RTC_T *pRTC, uint32_t ints) -{ - Chip_RTC_DisableOptions(pRTC, ints); -} - -/** - * @brief Clears latched RTC statuses - * @param pRTC : The base address of RTC block - * @param stsMask : OR'ed status bits to clear - * @return Nothing - * @note Use and OR'ed stsMask value of RTC_CTRL_OFD, RTC_CTRL_ALARM1HZ, - * and RTC_CTRL_WAKE1KHZ to clear specific RTC states. - */ -STATIC INLINE void Chip_RTC_ClearStatus(LPC_RTC_T *pRTC, uint32_t stsMask) -{ - pRTC->CTRL = (pRTC->CTRL & RTC_CTRL_MASK) | stsMask; -} - -/** - * @brief Return RTC control/status register - * @param pRTC : The base address of RTC block - * @return The current RTC control/status register - * @note Mask the return value with a RTC_CTRL_* definitions to determine - * which bits are set. For example, mask the return value with - * RTC_CTRL_ALARM1HZ to determine if the alarm interrupt is pending. - */ -STATIC INLINE uint32_t Chip_RTC_GetStatus(LPC_RTC_T *pRTC) -{ - return pRTC->CTRL; -} - -/** - * @brief Set RTC match value for alarm status/interrupt - * @param pRTC : The base address of RTC block - * @param count : Alarm event time - * @return Nothing - */ -STATIC INLINE void Chip_RTC_SetAlarm(LPC_RTC_T *pRTC, uint32_t count) -{ - pRTC->MATCH = count; -} - -/** - * @brief Return the RTC match value used for alarm status/interrupt - * @param pRTC : The base address of RTC block - * @return Alarm event time - */ -STATIC INLINE uint32_t Chip_RTC_GetAlarm(LPC_RTC_T *pRTC) -{ - return pRTC->MATCH; -} - -/** - * @brief Set RTC match count for 1 second timer count - * @param pRTC : The base address of RTC block - * @param count : Initial count to set - * @return Nothing - * @note Only write to this register when the RTC_CTRL_RTC_EN bit in - * the CTRL Register is 0. The counter increments one second - * after the RTC_CTRL_RTC_EN bit is set. - */ -STATIC INLINE void Chip_RTC_SetCount(LPC_RTC_T *pRTC, uint32_t count) -{ - pRTC->COUNT = count; -} - -/** - * @brief Get current RTC 1 second timer count - * @param pRTC : The base address of RTC block - * @return current RTC 1 second timer count - */ -STATIC INLINE uint32_t Chip_RTC_GetCount(LPC_RTC_T *pRTC) -{ - return pRTC->COUNT; -} - -/** - * @brief Set RTC wake count countdown value (in mS ticks) - * @param pRTC : The base address of RTC block - * @param count : wakeup time in milliSeconds - * @return Nothing - * @note A write pre-loads a start count value into the wake-up - * timer and initializes a count-down sequence. - */ -STATIC INLINE void Chip_RTC_SetWake(LPC_RTC_T *pRTC, uint16_t count) -{ - pRTC->WAKE = count; -} - -/** - * @brief Get RTC wake count countdown value - * @param pRTC : The base address of RTC block - * @return current RTC wake count countdown value (in mS) - */ -STATIC INLINE uint16_t Chip_RTC_GetWake(LPC_RTC_T *pRTC) -{ - return pRTC->WAKE; -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __RTC_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/sct_5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/sct_5410x.c deleted file mode 100644 index aac69a27afe..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/sct_5410x.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * @brief LPC5410X State Configurable Timer driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Initialize SCT */ -void Chip_SCT_Init(LPC_SCT_T *pSCT) -{ - Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_SCT0); - Chip_SYSCON_PeriphReset(RESET_SCT0); -} - -/* Shutdown SCT */ -void Chip_SCT_DeInit(LPC_SCT_T *pSCT) -{ - Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_SCT0); -} - -/* Set/Clear SCT control register */ -void Chip_SCT_SetClrControl(LPC_SCT_T *pSCT, uint32_t value, FunctionalState ena) -{ - if (ena == ENABLE) { - Chip_SCT_SetControl(pSCT, value); - } - else { - Chip_SCT_ClearControl(pSCT, value); - } -} - -/* Set Conflict resolution */ -void Chip_SCT_SetConflictResolution(LPC_SCT_T *pSCT, uint8_t outnum, uint8_t value) -{ - uint32_t tem; - - tem = pSCT->RES & (~(0x03 << (2 * outnum))); - pSCT->RES = tem | (value << (2 * outnum)); -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/sct_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/sct_5410x.h deleted file mode 100644 index 1992df899e5..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/sct_5410x.h +++ /dev/null @@ -1,504 +0,0 @@ -/* - * @brief LPC5410X State Configurable Timer (SCT) Chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __SCT_5410X_H_ -#define __SCT_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup SCT_5410X CHIP: LPC5410X State Configurable Timer driver - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/* match/cap registers, events, states, inputs, outputs - * - * @brief SCT Module configuration - */ -#define CONFIG_SCT_nEV (13) /*!< Number of events */ -#define CONFIG_SCT_nRG (13) /*!< Number of match/compare registers */ -#define CONFIG_SCT_nOU (8) /*!< Number of outputs */ -#define CONFIG_SCT_nIN (8) /*!< Number of outputs */ - -/** - * @brief State Configurable Timer register block structure - */ -typedef struct { - __IO uint32_t CONFIG; /*!< Configuration Register */ - - union { - __IO uint32_t CTRL_U; /*!< Control Register */ - - struct { - __IO uint16_t CTRL_L; /*!< Low control register */ - __IO uint16_t CTRL_H; /*!< High control register */ - }; - - }; - - __IO uint16_t LIMIT_L; /*!< limit register for counter L */ - __IO uint16_t LIMIT_H; /*!< limit register for counter H */ - __IO uint16_t HALT_L; /*!< halt register for counter L */ - __IO uint16_t HALT_H; /*!< halt register for counter H */ - __IO uint16_t STOP_L; /*!< stop register for counter L */ - __IO uint16_t STOP_H; /*!< stop register for counter H */ - __IO uint16_t START_L; /*!< start register for counter L */ - __IO uint16_t START_H; /*!< start register for counter H */ - uint32_t RESERVED1[10]; /*!< 0x03C reserved */ - - union { - __IO uint32_t COUNT_U; /*!< counter register */ - - struct { - __IO uint16_t COUNT_L; /*!< counter register for counter L */ - __IO uint16_t COUNT_H; /*!< counter register for counter H */ - }; - - }; - - __IO uint16_t STATE_L; /*!< state register for counter L */ - __IO uint16_t STATE_H; /*!< state register for counter H */ - __I uint32_t INPUT; /*!< input register */ - __IO uint16_t REGMODE_L; /*!< match - capture registers mode register L */ - __IO uint16_t REGMODE_H; /*!< match - capture registers mode register H */ - __IO uint32_t OUTPUT; /*!< output register */ - __IO uint32_t OUTPUTDIRCTRL; /*!< output counter direction Control Register */ - __IO uint32_t RES; /*!< conflict resolution register */ - __IO uint32_t DMA0REQUEST; /*!< DMA0 Request Register */ - __IO uint32_t DMA1REQUEST; /*!< DMA1 Request Register */ - uint32_t RESERVED2[35]; - __IO uint32_t EVEN; /*!< event enable register */ - __IO uint32_t EVFLAG; /*!< event flag register */ - __IO uint32_t CONEN; /*!< conflict enable register */ - __IO uint32_t CONFLAG; /*!< conflict flag register */ - - union { - - __IO union { /*!< ... Match / Capture value */ - uint32_t U; /*!< SCTMATCH[i].U Unified 32-bit register */ - - struct { - uint16_t L; /*!< SCTMATCH[i].L Access to L value */ - uint16_t H; /*!< SCTMATCH[i].H Access to H value */ - }; - - } MATCH[CONFIG_SCT_nRG]; - - __I union { - uint32_t U; /*!< SCTCAP[i].U Unified 32-bit register */ - - struct { - uint16_t L; /*!< SCTCAP[i].L Access to L value */ - uint16_t H; /*!< SCTCAP[i].H Access to H value */ - }; - - } CAP[CONFIG_SCT_nRG]; - - }; - - uint32_t RESERVED3[48 + (16 - CONFIG_SCT_nRG)]; - - union { - - __IO union { /* 0x200-... Match Reload / Capture Control value */ - uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */ - - struct { - uint16_t L; /* SCTMATCHREL[i].L Access to L value */ - uint16_t H; /* SCTMATCHREL[i].H Access to H value */ - }; - - } MATCHREL[CONFIG_SCT_nRG]; - - __IO union { - uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */ - - struct { - uint16_t L; /* SCTCAPCTRL[i].L Access to H value */ - uint16_t H; /* SCTCAPCTRL[i].H Access to H value */ - }; - - } CAPCTRL[CONFIG_SCT_nRG]; - - }; - - uint32_t RESERVED6[48 + (16 - CONFIG_SCT_nRG)]; - - __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/ - uint32_t STATE; /* Event State Register */ - uint32_t CTRL; /* Event Control Register */ - } EVENT[CONFIG_SCT_nEV]; - - uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /*!< ...-0x4FC reserved */ - - __IO struct { /*!< 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */ - uint32_t SET; /*!< Output n Set Register */ - uint32_t CLR; /*!< Output n Clear Register */ - } OUT[CONFIG_SCT_nOU]; - - uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /*!< ...-0x7F8 reserved */ - __I uint32_t MODULECONTENT; /*!< 0x7FC Module Content */ -} LPC_SCT_T; - -/** - * @brief Macro defines for SCT configuration register - */ -#define SCT_CONFIG_16BIT_COUNTER 0x00000000 /*!< Operate as 2 16-bit counters */ -#define SCT_CONFIG_32BIT_COUNTER 0x00000001 /*!< Operate as 1 32-bit counter */ - -#define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /*!< Bus clock */ -#define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /*!< SCT clock */ -#define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /*!< Input clock selected in CLKSEL field */ -#define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /*!< Input clock edge selected in CLKSEL field */ - -#define SCT_CONFIG_CLKMODE_SYSCLK (0x0 << 1) /*!< System clock */ -#define SCT_CONFIG_CLKMODE_PRESCALED_SYSCLK (0x1 << 1) /*!< Prescaled system clock */ -#define SCT_CONFIG_CLKMODE_SCT_INPUT (0x2 << 1) /*!< Input clock/edge selected in CKSEL field */ -#define SCT_CONFIG_CLKMODE_PRESCALED_SCT_INPUT (0x3 << 1) /*!< Prescaled input clock/edge selected in CKSEL field */ - -#define SCT_CONFIG_CKSEL_RISING_IN_0 (0x0UL << 3) -#define SCT_CONFIG_CKSEL_FALLING_IN_0 (0x1UL << 3) -#define SCT_CONFIG_CKSEL_RISING_IN_1 (0x2UL << 3) -#define SCT_CONFIG_CKSEL_FALLING_IN_1 (0x3UL << 3) -#define SCT_CONFIG_CKSEL_RISING_IN_2 (0x4UL << 3) -#define SCT_CONFIG_CKSEL_FALLING_IN_2 (0x5UL << 3) -#define SCT_CONFIG_CKSEL_RISING_IN_3 (0x6UL << 3) -#define SCT_CONFIG_CKSEL_FALLING_IN_3 (0x7UL << 3) -#define SCT_CONFIG_CKSEL_RISING_IN_4 (0x8UL << 3) -#define SCT_CONFIG_CKSEL_FALLING_IN_4 (0x9UL << 3) -#define SCT_CONFIG_CKSEL_RISING_IN_5 (0xAUL << 3) -#define SCT_CONFIG_CKSEL_FALLING_IN_5 (0xBUL << 3) -#define SCT_CONFIG_CKSEL_RISING_IN_6 (0xCUL << 3) -#define SCT_CONFIG_CKSEL_FALLING_IN_6 (0xDUL << 3) -#define SCT_CONFIG_CKSEL_RISING_IN_7 (0xEUL << 3) -#define SCT_CONFIG_CKSEL_FALLING_IN_7 (0xFUL << 3) -#define SCT_CONFIG_NORELOADL_U (0x1 << 7) /*!< Operate as 1 32-bit counter */ -#define SCT_CONFIG_NORELOADH (0x1 << 8) /*!< Operate as 1 32-bit counter */ -#define SCT_CONFIG_AUTOLIMIT_U (0x1UL << 17) -#define SCT_CONFIG_AUTOLIMIT_L (0x1UL << 17) -#define SCT_CONFIG_AUTOLIMIT_H (0x1UL << 18) - -/** - * @brief Macro defines for SCT control register - */ -#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /*!< Direction for low or unified counter */ -#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1 - -#define SCT_CTRL_STOP_L (1 << 1) /*!< Stop low counter */ -#define SCT_CTRL_HALT_L (1 << 2) /*!< Halt low counter */ -#define SCT_CTRL_CLRCTR_L (1 << 3) /*!< Clear low or unified counter */ -#define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /*!< Bidirectional bit */ -#define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /*!< Prescale clock for low or unified counter */ - -#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /*!< Direction for high counter */ -#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1 -#define SCT_CTRL_STOP_H (1 << 17) /*!< Stop high counter */ -#define SCT_CTRL_HALT_H (1 << 18) /*!< Halt high counter */ -#define SCT_CTRL_CLRCTR_H (1 << 19) /*!< Clear high counter */ -#define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20) -#define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /*!< Prescale clock for high counter */ - -#define SCT_EV_CTRL_MATCHSEL(reg) (reg << 0) -#define SCT_EV_CTRL_HEVENT_L (0UL << 4) -#define SCT_EV_CTRL_HEVENT_H (1UL << 4) -#define SCT_EV_CTRL_OUTSEL_INPUT (0UL << 5) -#define SCT_EV_CTRL_OUTSEL_OUTPUT (0UL << 5) -#define SCT_EV_CTRL_IOSEL(signal) (signal << 6) - -#define SCT_EV_CTRL_IOCOND_LOW (0UL << 10) -#define SCT_EV_CTRL_IOCOND_RISE (0x1UL << 10) -#define SCT_EV_CTRL_IOCOND_FALL (0x2UL << 10) -#define SCT_EV_CTRL_IOCOND_HIGH (0x3UL << 10) -#define SCT_EV_CTRL_COMBMODE_OR (0x0UL << 12) -#define SCT_EV_CTRL_COMBMODE_MATCH (0x1UL << 12) -#define SCT_EV_CTRL_COMBMODE_IO (0x2UL << 12) -#define SCT_EV_CTRL_COMBMODE_AND (0x3UL << 12) -#define SCT_EV_CTRL_STATELD (0x1UL << 14) -#define SCT_EV_CTRL_STATEV(x) (x << 15) -#define SCT_EV_CTRL_MATCHMEM (0x1UL << 20) -#define SCT_EV_CTRL_DIRECTION_INDEPENDENT (0x0UL << 21) -#define SCT_EV_CTRL_DIRECTION_UP (0x1UL << 21) -#define SCT_EV_CTRL_DIRECTION_DOWN (0x2UL << 21) - -/** - * @brief Macro defines for SCT Conflict resolution register - */ -#define SCT_RES_NOCHANGE (0) -#define SCT_RES_SET_OUTPUT (1) -#define SCT_RES_CLEAR_OUTPUT (2) -#define SCT_RES_TOGGLE_OUTPUT (3) - -/** - * SCT Match register values enum - */ -typedef enum CHIP_SCT_MATCH_REG { - SCT_MATCH_0 = 0, /*!< SCT Match register 0 */ - SCT_MATCH_1, - SCT_MATCH_2, - SCT_MATCH_3, - SCT_MATCH_4, - SCT_MATCH_5, - SCT_MATCH_6, - SCT_MATCH_7, - SCT_MATCH_8, - SCT_MATCH_9, - SCT_MATCH_10, - SCT_MATCH_11, - SCT_MATCH_12, - SCT_MATCH_13, - SCT_MATCH_14, - SCT_MATCH_15 -} CHIP_SCT_MATCH_REG_T; - -/** - * SCT Event values enum - */ -typedef enum CHIP_SCT_EVENT { - SCT_EVT_0 = (1 << 0), /*!< Event 0 */ - SCT_EVT_1 = (1 << 1), /*!< Event 1 */ - SCT_EVT_2 = (1 << 2), /*!< Event 2 */ - SCT_EVT_3 = (1 << 3), /*!< Event 3 */ - SCT_EVT_4 = (1 << 4), /*!< Event 4 */ - SCT_EVT_5 = (1 << 5), /*!< Event 5 */ - SCT_EVT_6 = (1 << 6), /*!< Event 6 */ - SCT_EVT_7 = (1 << 7), /*!< Event 7 */ - SCT_EVT_8 = (1 << 8), /*!< Event 8 */ - SCT_EVT_9 = (1 << 9), /*!< Event 9 */ - SCT_EVT_10 = (1 << 10), /*!< Event 10 */ - SCT_EVT_11 = (1 << 11), /*!< Event 11 */ - SCT_EVT_12 = (1 << 12), /*!< Event 12 */ - SCT_EVT_13 = (1 << 13), /*!< Event 13 */ - SCT_EVT_14 = (1 << 14), /*!< Event 14 */ - SCT_EVT_15 = (1 << 15) /*!< Event 15 */ -} CHIP_SCT_EVENT_T; - -/** - * @brief Set event control register - * @param pSCT : The base of SCT peripheral on the chip - * @param event_number - * @param value : The 32-bit event control setting - * @return Nothing - */ -STATIC INLINE void Chip_SCT_EventControl(LPC_SCT_T *pSCT, uint32_t event_number, - uint32_t value) { - pSCT->EVENT[event_number].CTRL = value; -} - -/** - * @brief Set event state mask register - * @param pSCT : The base of SCT peripheral on the chip - * @param event_number - * @param event_state_mask : The 32-bit event state mask setting - * @return Nothing - */ -STATIC INLINE void Chip_SCT_EventStateMask(LPC_SCT_T *pSCT, uint32_t event_number, - uint32_t event_state_mask) { - pSCT->EVENT[event_number].STATE = event_state_mask; -} - -/** - * @brief Set configuration register - * @param pSCT : The base of SCT peripheral on the chip - * @param cfg : The 32-bit configuration setting - * @return Nothing - */ -STATIC INLINE void Chip_SCT_Config(LPC_SCT_T *pSCT, uint32_t cfg) { - pSCT->CONFIG = cfg; -} - -/** - * @brief Configures the Limit register - * @param pSCT : The base of SCT peripheral on the chip - * @param value : The 32-bit Limit register value - * @return Nothing - */ -STATIC INLINE void Chip_SCT_Limit(LPC_SCT_T *pSCT, uint32_t value) { - pSCT->LIMIT_L = value; -} - -/** - * @brief Set or Clear the Control register - * @param pSCT : Pointer to SCT register block - * @param value : SCT Control register value - * @param ena : ENABLE - To set the fields specified by value - * : DISABLE - To clear the field specified by value - * @return Nothing - * Set or clear the control register bits as specified by the \a value - * parameter. If \a ena is set to ENABLE, the mentioned register fields - * will be set. If \a ena is set to DISABLE, the mentioned register - * fields will be cleared - */ -void Chip_SCT_SetClrControl(LPC_SCT_T *pSCT, uint32_t value, FunctionalState ena); - -/** - * @brief Set the conflict resolution - * @param pSCT : Pointer to SCT register block - * @param outnum : Output number - * @param value : Output value - * - SCT_RES_NOCHANGE :No change - * - SCT_RES_SET_OUTPUT :Set output - * - SCT_RES_CLEAR_OUTPUT :Clear output - * - SCT_RES_TOGGLE_OUTPUT :Toggle output - * : SCT_RES_NOCHANGE - * : DISABLE - To clear the field specified by value - * @return Nothing - * Set conflict resolution for the output \a outnum - */ -void Chip_SCT_SetConflictResolution(LPC_SCT_T *pSCT, uint8_t outnum, uint8_t value); - -/** - * @brief Set unified count value in State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @param count : The 32-bit count value - * @return Nothing - */ -STATIC INLINE void Chip_SCT_SetCount(LPC_SCT_T *pSCT, uint32_t count) { - pSCT->COUNT_U = count; -} - -/** - * @brief Set lower count value in State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @param count : The 16-bit count value - * @return Nothing - */ -STATIC INLINE void Chip_SCT_SetCountL(LPC_SCT_T *pSCT, uint16_t count) { - pSCT->COUNT_L = count; -} - -/** - * @brief Set higher count value in State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @param count : The 16-bit count value - * @return Nothing - */ -STATIC INLINE void Chip_SCT_SetCountH(LPC_SCT_T *pSCT, uint16_t count) { - pSCT->COUNT_H = count; -} - -/** - * @brief Set unified match count value in State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @param n : Match register value - * @param value : The 32-bit match count value - * @return Nothing - */ -STATIC INLINE void Chip_SCT_SetMatchCount(LPC_SCT_T *pSCT, CHIP_SCT_MATCH_REG_T n, uint32_t value) { - pSCT->MATCH[n].U = value; -} - -/** - * @brief Set unified match reload count value in State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @param n : Match register value - * @param value : The 32-bit match count reload value - * @return Nothing - */ -STATIC INLINE void Chip_SCT_SetMatchReload(LPC_SCT_T *pSCT, CHIP_SCT_MATCH_REG_T n, uint32_t value) { - pSCT->MATCHREL[n].U = value; -} - -/** - * @brief Enable the interrupt for the specified event in State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @param evt : Event value - * @return Nothing - */ -STATIC INLINE void Chip_SCT_EnableEventInt(LPC_SCT_T *pSCT, CHIP_SCT_EVENT_T evt) { - pSCT->EVEN |= evt; -} - -/** - * @brief Disable the interrupt for the specified event in State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @param evt : Event value - * @return Nothing - */ -STATIC INLINE void Chip_SCT_DisableEventInt(LPC_SCT_T *pSCT, CHIP_SCT_EVENT_T evt) { - pSCT->EVEN &= ~(evt); -} - -/** - * @brief Clear the specified event flag in State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @param evt : Event value - * @return Nothing - */ -STATIC INLINE void Chip_SCT_ClearEventFlag(LPC_SCT_T *pSCT, CHIP_SCT_EVENT_T evt) { - pSCT->EVFLAG |= evt; -} - -/** - * @brief Set control register in State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @param value : Value (ORed value of SCT_CTRL_* bits) - * @return Nothing - */ -STATIC INLINE void Chip_SCT_SetControl(LPC_SCT_T *pSCT, uint32_t value) { - pSCT->CTRL_U |= value; -} - -/** - * @brief Clear control register in State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @param value : Value (ORed value of SCT_CTRL_* bits) - * @return Nothing - */ -STATIC INLINE void Chip_SCT_ClearControl(LPC_SCT_T *pSCT, uint32_t value) { - pSCT->CTRL_U &= ~(value); -} - -/** - * @brief Initializes the State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @return Nothing - */ -void Chip_SCT_Init(LPC_SCT_T *pSCT); - -/** - * @brief Deinitializes the State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @return Nothing - */ -void Chip_SCT_DeInit(LPC_SCT_T *pSCT); - -/** - * @} - */ - -#ifdef __cplusplus -} - -#endif - -#endif /* __SCT_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/sct_pwm_5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/sct_pwm_5410x.c deleted file mode 100644 index aca45650545..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/sct_pwm_5410x.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * @brief LPC5410x State Configurable Timer PWM driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Setup the OUTPUT pin corresponding to the PWM index */ -void Chip_SCTPWM_SetOutPin(LPC_SCT_T *pSCT, uint8_t index, uint8_t pin) -{ - int ix = (int) index; - pSCT->EVENT[ix].CTRL = index | (1 << 12); - pSCT->EVENT[ix].STATE = 1; - pSCT->OUT[pin].SET = 1; - pSCT->OUT[pin].CLR = 1 << ix; - - /* Clear the output in-case of conflict */ - pSCT->RES = (pSCT->RES & ~(3 << (pin << 1))) | (0x01 << (pin << 1)); - - /* Set and Clear do not depend on direction */ - pSCT->OUTPUTDIRCTRL = (pSCT->OUTPUTDIRCTRL & ~(3 << (pin << 1))); -} - -/* Set the PWM frequency */ -void Chip_SCTPWM_SetRate(LPC_SCT_T *pSCT, uint32_t freq) -{ - uint32_t rate; - - rate = Chip_Clock_GetSystemClockRate() / freq; - - /* Stop the SCT before configuration */ - Chip_SCTPWM_Stop(pSCT); - - /* Set MATCH0 for max limit */ - pSCT->REGMODE_L = 0; - pSCT->REGMODE_H = 0; - Chip_SCT_SetMatchCount(pSCT, SCT_MATCH_0, 0); - Chip_SCT_SetMatchReload(pSCT, SCT_MATCH_0, rate); - pSCT->EVENT[0].CTRL = 1 << 12; - pSCT->EVENT[0].STATE = 1; - - /* Set SCT Counter to count 32-bits and reset to 0 after reaching MATCH0 */ - Chip_SCT_Config(pSCT, SCT_CONFIG_32BIT_COUNTER | SCT_CONFIG_AUTOLIMIT_L); -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/sct_pwm_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/sct_pwm_5410x.h deleted file mode 100644 index b1b8c93663d..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/sct_pwm_5410x.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * @brief LPC5410x State Configurable Timer (SCT/PWM) Chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __SCT_PWM_5410X_H_ -#define __SCT_PWM_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup SCT_PWM_5410X CHIP: LPC5410X State Configurable Timer PWM driver - * - * For more information on how to use the driver please visit the FAQ page at - * - * www.lpcware.com - * - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/** - * @brief Get number of ticks per PWM cycle - * @param pSCT : The base of SCT peripheral on the chip - * @return Number ot ticks that will be counted per cycle - * @note Return value of this function will be vaild only - * after calling Chip_SCTPWM_SetRate() - */ -STATIC INLINE uint32_t Chip_SCTPWM_GetTicksPerCycle(LPC_SCT_T *pSCT) -{ - return pSCT->MATCHREL[0].U; -} - -/** - * @brief Converts a percentage to ticks - * @param pSCT : The base of SCT peripheral on the chip - * @param percent : Percentage to convert (0 - 100) - * @return Number ot ticks corresponding to given percentage - * @note Do not use this function when using very low - * pwm rate (like 100Hz or less), on a chip that has - * very high frequency as the calculation might - * cause integer overflow - */ -STATIC INLINE uint32_t Chip_SCTPWM_PercentageToTicks(LPC_SCT_T *pSCT, uint8_t percent) -{ - return (Chip_SCTPWM_GetTicksPerCycle(pSCT) * percent) / 100; -} - -/** - * @brief Get number of ticks on per PWM cycle - * @param pSCT : The base of SCT peripheral on the chip - * @param index : Index of the PWM 1 to N (see notes) - * @return Number ot ticks for which the output will be ON per cycle - * @note @a index will be 1 to N where N is the "Number of - * match registers available in the SCT - 1" or - * "Number of OUTPUT pins available in the SCT" whichever - * is minimum. - */ -STATIC INLINE uint32_t Chip_SCTPWM_GetDutyCycle(LPC_SCT_T *pSCT, uint8_t index) -{ - return pSCT->MATCHREL[index].U; -} - -/** - * @brief Get number of ticks on per PWM cycle - * @param pSCT : The base of SCT peripheral on the chip - * @param index : Index of the PWM 1 to N (see notes) - * @param ticks : Number of ticks the output should say ON - * @return None - * @note @a index will be 1 to N where N is the "Number of - * match registers available in the SCT - 1" or - * "Number of OUTPUT pins available in the SCT" whichever - * is minimum. The new duty cycle will be effective only - * after completion of current PWM cycle. - */ -STATIC INLINE void Chip_SCTPWM_SetDutyCycle(LPC_SCT_T *pSCT, uint8_t index, uint32_t ticks) -{ - Chip_SCT_SetMatchReload(pSCT, (CHIP_SCT_MATCH_REG_T) index, ticks); -} - -/** - * @brief Initialize the SCT/PWM clock and reset - * @param pSCT : The base of SCT peripheral on the chip - * @return None - */ -STATIC INLINE void Chip_SCTPWM_Init(LPC_SCT_T *pSCT) -{ - Chip_SCT_Init(pSCT); -} - -/** - * @brief Start the SCT PWM - * @param pSCT : The base of SCT peripheral on the chip - * @return None - * @note This function must be called after all the - * configuration is completed. Do not call Chip_SCTPWM_SetRate() - * or Chip_SCTPWM_SetOutPin() after the SCT/PWM is started. Use - * Chip_SCTPWM_Stop() to stop the SCT/PWM before reconfiguring, - * Chip_SCTPWM_SetDutyCycle() can be called when the SCT/PWM is - * running to change the DutyCycle. - */ -STATIC INLINE void Chip_SCTPWM_Start(LPC_SCT_T *pSCT) -{ - Chip_SCT_ClearControl(pSCT, SCT_CTRL_HALT_L | SCT_CTRL_HALT_H); -} - -/** - * @brief Stop the SCT PWM - * @param pSCT : The base of SCT peripheral on the chip - * @return None - */ -STATIC INLINE void Chip_SCTPWM_Stop(LPC_SCT_T *pSCT) -{ - /* Stop SCT */ - Chip_SCT_SetControl(pSCT, SCT_CTRL_HALT_L | SCT_CTRL_HALT_H); - - /* Clear the counter */ - Chip_SCT_SetControl(pSCT, SCT_CTRL_CLRCTR_L | SCT_CTRL_CLRCTR_H); -} - -/** - * @brief Sets the frequency of the generated PWM wave - * @param pSCT : The base of SCT peripheral on the chip - * @param freq : Frequency in Hz - * @return None - */ -void Chip_SCTPWM_SetRate(LPC_SCT_T *pSCT, uint32_t freq); - -/** - * @brief Setup the OUTPUT pin and associate it with an index - * @param pSCT : The base of the SCT peripheral on the chip - * @param index : Index of PWM 1 to N (see notes) - * @param pin : COUT pin to be associated with the index - * @return None - * @note @a index will be 1 to N where N is the "Number of - * match registers available in the SCT - 1" or - * "Number of OUTPUT pins available in the SCT" whichever - * is minimum. - */ -void Chip_SCTPWM_SetOutPin(LPC_SCT_T *pSCT, uint8_t index, uint8_t pin); - -/** - * @} - */ - -#ifdef __cplusplus -} - -#endif - -#endif /* __SCT_PWM_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/stopwatch_5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/stopwatch_5410x.c deleted file mode 100644 index 483df426920..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/stopwatch_5410x.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * @brief LPC5410x specific stopwatch implementation - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" -#include "stopwatch.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/* Precompute these to optimize runtime */ -static uint32_t ticksPerSecond; -static uint32_t ticksPerMs; -static uint32_t ticksPerUs; - -/* Use this timer for stopwatch */ -#define LPC_TIMER32_1 LPC_TIMER0 - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Initialize stopwatch */ -void StopWatch_Init(void) -{ - /* Set prescaler to divide by 8 */ - const uint32_t prescaleDivisor = 8; - Chip_TIMER_Init(LPC_TIMER32_1); - Chip_TIMER_PrescaleSet(LPC_TIMER32_1, prescaleDivisor - 1); - Chip_TIMER_Enable(LPC_TIMER32_1); - - /* Pre-compute tick rate. */ - ticksPerSecond = Chip_Clock_GetAsyncSyscon_ClockRate() / prescaleDivisor; - ticksPerMs = ticksPerSecond / 1000; - ticksPerUs = ticksPerSecond / 1000000; -} - -/* Start a stopwatch */ -uint32_t StopWatch_Start(void) -{ - /* Return the current timer count. */ - return Chip_TIMER_ReadCount(LPC_TIMER32_1); -} - -/* Returns number of ticks per second of the stopwatch timer */ -uint32_t StopWatch_TicksPerSecond(void) -{ - return ticksPerSecond; -} - -/* Converts from stopwatch ticks to mS. */ -uint32_t StopWatch_TicksToMs(uint32_t ticks) -{ - return ticks / ticksPerMs; -} - -/* Converts from stopwatch ticks to uS. */ -uint32_t StopWatch_TicksToUs(uint32_t ticks) -{ - return ticks / ticksPerUs; -} - -/* Converts from mS to stopwatch ticks. */ -uint32_t StopWatch_MsToTicks(uint32_t mS) -{ - return mS * ticksPerMs; -} - -/* Converts from uS to stopwatch ticks. */ -uint32_t StopWatch_UsToTicks(uint32_t uS) -{ - return uS * ticksPerUs; -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/syscon_5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/syscon_5410x.c deleted file mode 100644 index 860a8ae36f2..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/syscon_5410x.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * @brief LPC5410X System & Control driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Set source for non-maskable interrupt (NMI) */ -void Chip_SYSCON_SetNMISource(uint32_t intsrc) -{ - uint32_t reg; - - reg = LPC_SYSCON->NMISRC; -#if defined(CORE_M4) - reg &= ~SYSCON_NMISRC_M4_ENABLE; -#else - reg &= ~SYSCON_NMISRC_M0_ENABLE; - intsrc = (intsrc << 8); -#endif - - /* First write without NMI bit, and then write source */ - LPC_SYSCON->NMISRC = reg; - LPC_SYSCON->NMISRC = reg | intsrc; -} - -/* Enable interrupt used for NMI source */ -void Chip_SYSCON_EnableNMISource(void) -{ -#if defined(CORE_M4) - LPC_SYSCON->NMISRC |= SYSCON_NMISRC_M4_ENABLE; -#else - LPC_SYSCON->NMISRC |= SYSCON_NMISRC_M0_ENABLE; -#endif -} - -/* Disable interrupt used for NMI source */ -void Chip_SYSCON_DisableNMISource(void) -{ -#if defined(CORE_M4) - LPC_SYSCON->NMISRC &= ~SYSCON_NMISRC_M4_ENABLE; -#else - LPC_SYSCON->NMISRC &= ~SYSCON_NMISRC_M0_ENABLE; -#endif -} - -/* Enable or disable asynchronous APB bridge and subsystem */ -void Chip_SYSCON_Enable_ASYNC_Syscon(bool enable) -{ - if (enable) { - LPC_SYSCON->ASYNCAPBCTRL = 0x01; - } - else { - LPC_SYSCON->ASYNCAPBCTRL = 0x00; - } -} - -/* Resets a peripheral */ -void Chip_SYSCON_PeriphReset(CHIP_SYSCON_PERIPH_RESET_T periph) -{ - uint32_t pid = (uint32_t) periph; - - if (pid >= 128) { - /* Async resets mapped to 128 and above, offset for peripheral bit index */ - pid = 1 << (((uint32_t) periph) - 128); - LPC_ASYNC_SYSCON->ASYNCPRESETCTRLSET = pid; - LPC_ASYNC_SYSCON->ASYNCPRESETCTRLCLR = pid; - } - else if (periph >= 32) { - pid = 1 << (((uint32_t) periph) - 32); - LPC_SYSCON->PRESETCTRLSET[1] = pid; - LPC_SYSCON->PRESETCTRLCLR[1] = pid; - } - else { - pid = 1 << ((uint32_t) periph); - LPC_SYSCON->PRESETCTRLSET[0] = pid; - LPC_SYSCON->PRESETCTRLCLR[0] = pid; - } -} - -/* Returns the computed value for a frequency measurement cycle */ -uint32_t Chip_SYSCON_GetCompFreqMeas(uint32_t refClockRate) -{ - uint32_t capval; - uint64_t clkrate = 0; - - /* Get raw capture value */ - capval = Chip_SYSCON_GetRawFreqMeasCapval(); - - /* Limit CAPVAL check */ - if (capval > 2) { - clkrate = (((uint64_t) capval - 2) * (uint64_t) refClockRate) / 0x4000; - } - - return (uint32_t) clkrate; -} - -void Chip_SYSCON_PowerUp(uint32_t powerupmask) -{ - /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ - if (powerupmask & SYSCON_PDRUNCFG_PD_SYS_PLL) { - volatile uint32_t delayX; - uint32_t maxCCO = (1 << 18) | 0x3fff; - uint32_t curSSCTRL = LPC_SYSCON->SYSPLLSSCTRL[0]; - - /* If NOT using spread spectrum mode */ - if (curSSCTRL & (1 << 18)) { - - /* Turn on PLL */ - LPC_SYSCON->PDRUNCFGCLR = SYSCON_PDRUNCFG_PD_SYS_PLL; - - /* this sequence acclerates the PLL lock time */ - LPC_SYSCON->SYSPLLSSCTRL[0] = maxCCO | (1 << 17); /* Set mreq to activate */ - LPC_SYSCON->SYSPLLSSCTRL[0] = maxCCO; /* clear mreq to prepare for restoring mreq */ - - /* Delay for 20 uSec @ 12Mhz*/ - for (delayX = 0; delayX < 48; ++delayX) {} - - /* set original value back with mreq */ - LPC_SYSCON->SYSPLLSSCTRL[0] = curSSCTRL | (1 << 17); - } - } - - /* Enable peripheral states by setting low */ - LPC_SYSCON->PDRUNCFGCLR = powerupmask; -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/syscon_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/syscon_5410x.h deleted file mode 100644 index 3901eb5657f..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/syscon_5410x.h +++ /dev/null @@ -1,567 +0,0 @@ -/* - * @brief LPC5410X System & Control driver inclusion file - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __SYSCON_5410X_H_ -#define __SYSCON_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup SYSCON_5410X CHIP: LPC5410X System and Control Driver - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/** - * @brief LPC5410X Main system configuration register block structure - */ -typedef struct { - __IO uint32_t SYSMEMREMAP; /*!< System Remap register */ - __I uint32_t RESERVED0[4]; - __IO uint32_t SYSTCKCAL; /*!< System Tick Calibration register */ - __I uint32_t RESERVED1[1]; - __IO uint32_t NMISRC; /*!< NMI Source select register */ - __IO uint32_t ASYNCAPBCTRL; /*!< Asynch APB chiplet control register */ - __I uint32_t RESERVED2[7]; - __IO uint32_t SYSRSTSTAT; /*!< System Reset Stat register */ - __IO uint32_t PRESETCTRL[2]; /*!< Peripheral Reset Ctrl register */ - __IO uint32_t PRESETCTRLSET[2]; /*!< Peripheral Reset Ctrl Set register */ - __IO uint32_t PRESETCTRLCLR[2]; /*!< Peripheral Reset Ctrl Clr register */ - __IO uint32_t PIOPORCAP[2]; /*!< PIO Power-On Reset Capture register */ - __I uint32_t RESERVED3[1]; - __IO uint32_t PIORESCAP[2]; /*!< PIO Pad Reset Capture register */ - __I uint32_t RESERVED4[4]; - __IO uint32_t MAINCLKSELA; /*!< Main Clk sel Source Sel A register */ - __IO uint32_t MAINCLKSELB; /*!< Main Clk sel Source Sel B register */ - __I uint32_t RESERVED5; - __IO uint32_t ADCCLKSEL; /*!< ADC Async Clk Sel register */ - __I uint32_t RESERVED6; - __IO uint32_t CLKOUTSELA; /*!< Clk Out Sel Source A register */ - __IO uint32_t CLKOUTSELB; /*!< Clk Out Sel Source B register */ - __I uint32_t RESERVED7; - __IO uint32_t SYSPLLCLKSEL; /*!< System PLL Clk Selregister */ - __I uint32_t RESERVED8[7]; - __IO uint32_t AHBCLKCTRL[2]; /*!< AHB Peripheral Clk Enable register */ - __IO uint32_t AHBCLKCTRLSET[2]; /*!< AHB Peripheral Clk Enable Set register */ - __IO uint32_t AHBCLKCTRLCLR[2]; /*!< AHB Peripheral Clk Enable Clr register */ - __I uint32_t RESERVED9[2]; - __IO uint32_t SYSTICKCLKDIV; /*!< Systick Clock divider register */ - __I uint32_t RESERVED10[7]; - __IO uint32_t AHBCLKDIV; /*!< Main Clk Divider register */ - __IO uint32_t RESERVED11; - __IO uint32_t ADCCLKDIV; /*!< ADC Async Clk Divider register */ - __IO uint32_t CLKOUTDIV; /*!< Clk Out Divider register */ - __I uint32_t RESERVED12[4]; - __IO uint32_t FREQMECTRL; /*!< Frequency Measure Control register */ - __IO uint32_t FLASHCFG; /*!< Flash Config register */ - __I uint32_t RESERVED13[8]; - __IO uint32_t FIFOCTRL; /*!< VFIFO control register */ - __I uint32_t RESERVED14[14]; - __I uint32_t RESERVED15[1]; - __I uint32_t RESERVED16[2]; - __IO uint32_t RTCOSCCTRL; /*!< RTC Oscillator Control register */ - __I uint32_t RESERVED17[7]; - __IO uint32_t SYSPLLCTRL; /*!< System PLL control register */ - __IO uint32_t SYSPLLSTAT; /*!< PLL status register */ - __IO uint32_t SYSPLLNDEC; /*!< PLL N decoder register */ - __IO uint32_t SYSPLLPDEC; /*!< PLL P decoder register */ - __IO uint32_t SYSPLLSSCTRL[2]; /*!< Spread Spectrum control registers */ - __I uint32_t RESERVED18[18]; - __IO uint32_t PDRUNCFG; /*!< Power Down Run Config register */ - __IO uint32_t PDRUNCFGSET; /*!< Power Down Run Config Set register */ - __IO uint32_t PDRUNCFGCLR; /*!< Power Down Run Config Clr register */ - __I uint32_t RESERVED19[9]; - __IO uint32_t STARTERP[2]; /*!< Start Signal Enable Register */ - __IO uint32_t STARTERSET[2]; /*!< Start Signal Enable Set Register */ - __IO uint32_t STARTERCLR[2]; /*!< Start Signal Enable Clr Register */ - __I uint32_t RESERVED20[42]; - __I uint32_t RESERVED20A[4]; - __I uint32_t RESERVED21[57]; - __IO uint32_t JTAG_IDCODE; - __IO uint32_t DEVICE_ID0; /*!< Boot ROM and die revision register */ - __IO uint32_t DEVICE_ID1; /*!< Boot ROM and die revision register */ -} LPC_SYSCON_T; - -/** - * @brief LPC5410X Asynchronous system configuration register block structure - */ -typedef struct { - __IO uint32_t AYSNCPRESETCTRL; /*!< peripheral reset register */ - __IO uint32_t ASYNCPRESETCTRLSET; /*!< peripheral reset Set register */ - __IO uint32_t ASYNCPRESETCTRLCLR; /*!< peripheral reset Clr register */ - __I uint32_t RESERVED0; - __IO uint32_t ASYNCAPBCLKCTRL; /*!< clk enable register */ - __IO uint32_t ASYNCAPBCLKCTRLSET; /*!< clk enable Set register */ - __IO uint32_t ASYNCAPBCLKCTRLCLR; /*!< clk enable Clr register */ - __I uint32_t RESERVED1; - __IO uint32_t ASYNCAPBCLKSELA; /*!< clk source mux A register */ - __IO uint32_t ASYNCAPBCLKSELB; /*!< clk source mux B register */ - __IO uint32_t ASYNCCLKDIV; /*!< clk div register */ - __I uint32_t RESERVED2; - __IO uint32_t FRGCTRL; /*!< Fraction Rate Generator Ctrl register */ -} LPC_ASYNC_SYSCON_T; - -/** - * System memory remap modes used to remap interrupt vectors - */ -typedef enum CHIP_SYSCON_BOOT_MODE_REMAP { - REMAP_BOOT_LOADER_MODE, /*!< Interrupt vectors are re-mapped to Boot ROM */ - REMAP_USER_RAM_MODE, /*!< Interrupt vectors are re-mapped to user Static RAM */ - REMAP_USER_FLASH_MODE /*!< Interrupt vectors are not re-mapped and reside in Flash */ -} CHIP_SYSCON_BOOT_MODE_REMAP_T; - -/** - * @brief Re-map interrupt vectors - * @param remap : system memory map value - * @return Nothing - */ -STATIC INLINE void Chip_SYSCON_Map(CHIP_SYSCON_BOOT_MODE_REMAP_T remap) -{ - LPC_SYSCON->SYSMEMREMAP = (uint32_t) remap; -} - -/** - * @brief Get system remap setting - * @return System remap setting - */ -STATIC INLINE CHIP_SYSCON_BOOT_MODE_REMAP_T Chip_SYSCON_GetMemoryMap(void) -{ - return (CHIP_SYSCON_BOOT_MODE_REMAP_T) LPC_SYSCON->SYSMEMREMAP; -} - -/** - * @brief Set System tick timer calibration value - * @param sysCalVal : System tick timer calibration value - * @return Nothing - */ -STATIC INLINE void Chip_SYSCON_SetSYSTCKCAL(uint32_t sysCalVal) -{ - LPC_SYSCON->SYSTCKCAL = sysCalVal; -} - -/** - * Non-Maskable Interrupt Enable/Disable value - */ -#define SYSCON_NMISRC_M0_ENABLE ((uint32_t) 1 << 30) /*!< Enable the Non-Maskable Interrupt M0 (NMI) source */ -#define SYSCON_NMISRC_M4_ENABLE ((uint32_t) 1 << 31) /*!< Enable the Non-Maskable Interrupt M4 (NMI) source */ - -/** - * @brief Set source for non-maskable interrupt (NMI) - * @param intsrc : IRQ number to assign to the NMI - * @return Nothing - * @note The NMI source will be disabled upon exiting this function. Use the - * Chip_SYSCON_EnableNMISource() function to enable the NMI source. - */ -void Chip_SYSCON_SetNMISource(uint32_t intsrc); - -/** - * @brief Enable interrupt used for NMI source - * @return Nothing - */ -void Chip_SYSCON_EnableNMISource(void); - -/** - * @brief Disable interrupt used for NMI source - * @return Nothing - */ -void Chip_SYSCON_DisableNMISource(void); - -/** - * @brief Enable or disable asynchronous APB bridge and subsystem - * @param enable : true to enable, false to disable - * @return Nothing - * @note This bridge must be enabled to access peripherals on the - * associated bridge. - */ -void Chip_SYSCON_Enable_ASYNC_Syscon(bool enable); - -/** - * @brief Set UART Fractional divider value - * @param fmul : Fractional multiplier value - * @param fdiv : Fractional divider value (Must always be 0xFF) - * @return Nothing - */ -STATIC INLINE void Chip_SYSCON_SetUSARTFRGCtrl(uint8_t fmul, uint8_t fdiv) -{ - LPC_ASYNC_SYSCON->FRGCTRL = ((uint32_t) fmul << 8) | fdiv; -} - -/** - * System reset status values - */ -#define SYSCON_RST_POR (1 << 0) /*!< POR reset status */ -#define SYSCON_RST_EXTRST (1 << 1) /*!< External reset status */ -#define SYSCON_RST_WDT (1 << 2) /*!< Watchdog reset status */ -#define SYSCON_RST_BOD (1 << 3) /*!< Brown-out detect reset status */ -#define SYSCON_RST_SYSRST (1 << 4) /*!< software system reset status */ - -/** - * @brief Get system reset status - * @return An Or'ed value of SYSCON_RST_* - * @note This function returns the detected reset source(s). - */ -STATIC INLINE uint32_t Chip_SYSCON_GetSystemRSTStatus(void) -{ - return LPC_SYSCON->SYSRSTSTAT; -} - -/** - * @brief Clear system reset status - * @param reset : An Or'ed value of SYSCON_RST_* status to clear - * @return Nothing - * @note This function clears the specified reset source(s). - */ -STATIC INLINE void Chip_SYSCON_ClearSystemRSTStatus(uint32_t reset) -{ - LPC_SYSCON->SYSRSTSTAT = reset; -} - -/** - * Peripheral reset identifiers - */ -typedef enum { - /* Peripheral reset enables for PRESETCTRL0 */ - RESET_FLASH = 7, /*!< Flash controller */ - RESET_FMC, /*!< Flash accelerator */ - RESET_INMUX = 11, /*!< Input mux */ - RESET_IOCON = 13, /*!< IOCON */ - RESET_GPIO0, /*!< GPIO Port 0 */ - RESET_GPIO1, /*!< GPIO Port 1 */ - RESET_PINT = 18, /*!< Pin interrupt */ - RESET_GINT, /*!< Grouped interrupt (GINT) */ - RESET_DMA, /*!< DMA */ - RESET_CRC, /*!< CRC */ - RESET_WWDT, /*!< Watchdog timer */ - RESET_RTC, /*!< RTC */ - RESET_MAILBOX = 26, /*!< Mailbox */ - RESET_ADC0, /*!< ADC0 */ - - /* Peripheral reset enables for PRESETCTRL1 */ - RESET_MRT = 32 + 0, /*!< multi-rate timer */ - RESET_RIT, /*!< Repetitive interrupt timer */ - RESET_SCT0, /*!< SCT0 */ - RESET_FIFO = 32 + 9, /*!< System FIFO */ - RESET_UTICK, /*!< Micro-tick Timer */ - RESET_TIMER2 = 32 + 22, /*!< TIMER2 */ - RESET_TIMER3 = 32 + 26, /*!< TIMER3 */ - RESET_TIMER4, /*!< TIMER4 */ - - /* Async peripheral reset enables for ASYNCPRESETCTRL */ - RESET_USART0 = 128 + 1, /*!< UART0 */ - RESET_USART1, /*!< UART1 */ - RESET_USART2, /*!< UART2 */ - RESET_USART3, /*!< UART3 */ - RESET_I2C0, /*!< I2C0 */ - RESET_I2C1, /*!< I2C1 */ - RESET_I2C2, /*!< I2C2 */ - RESET_SPI0 = 128 + 9, /*!< SPI0 */ - RESET_SPI1, /*!< SPI1 */ - RESET_TIMER0 = 128 + 13, /*!< TIMER0 */ - RESET_TIMER1, /*!< TIMER1 */ - RESET_FRG0 /*!< FRG */ -} CHIP_SYSCON_PERIPH_RESET_T; - -/** - * @brief Resets a peripheral - * @param periph : Peripheral to reset - * @return Nothing - * Will assert and de-assert reset for a peripheral. - */ -void Chip_SYSCON_PeriphReset(CHIP_SYSCON_PERIPH_RESET_T periph); - -/** - * @brief Read POR captured PIO status - * @param port : 0 for port 0 pins, 1 for port 1 pins, 2 for port 2 pins, etc. - * @return captured Power-On-Reset (POR) PIO status - */ -STATIC INLINE uint32_t Chip_SYSCON_GetPORPIOStatus(uint8_t port) -{ - return LPC_SYSCON->PIOPORCAP[port]; -} - -/** - * @brief Read reset captured PIO status - * @param port : 0 for port 0 pins, 1 for port 1 pins, 2 for port 2 pins, etc. - * @return captured reset PIO status - * @note Used when reset other than a Power-On-Reset (POR) occurs. - */ -STATIC INLINE uint32_t Chip_SYSCON_GetResetPIOStatus(uint8_t port) -{ - return LPC_SYSCON->PIORESCAP[port]; -} - -/** - * @brief Starts a frequency measurement cycle - * @return Nothing - * @note This function is meant to be used with the Chip_INMUX_SetFreqMeasRefClock() - * and Chip_INMUX_SetFreqMeasTargClock() functions. - */ -STATIC INLINE void Chip_SYSCON_StartFreqMeas(void) -{ - LPC_SYSCON->FREQMECTRL = 0; - LPC_SYSCON->FREQMECTRL = (1UL << 31); -} - -/** - * @brief Indicates when a frequency measurement cycle is complete - * @return true if a measurement cycle is active, otherwise false - */ -STATIC INLINE bool Chip_SYSCON_IsFreqMeasComplete(void) -{ - return (bool) ((LPC_SYSCON->FREQMECTRL & (1UL << 31)) == 0); -} - -/** - * @brief Returns the raw capture value for a frequency measurement cycle - * @return raw cpature value (this is not a frequency) - */ -STATIC INLINE uint32_t Chip_SYSCON_GetRawFreqMeasCapval(void) -{ - return LPC_SYSCON->FREQMECTRL & 0x3FFF; -} - -/** - * @brief Returns the computed value for a frequency measurement cycle - * @param refClockRate : Reference clock rate used during the frequency measurement cycle - * @return Computed cpature value - */ -uint32_t Chip_SYSCON_GetCompFreqMeas(uint32_t refClockRate); - -/** - * @brief FLASH Access time definitions - */ -typedef enum { - SYSCON_FLASH_1CYCLE = 0, /*!< Flash accesses use 1 CPU clock */ - FLASHTIM_20MHZ_CPU = SYSCON_FLASH_1CYCLE, - SYSCON_FLASH_2CYCLE, /*!< Flash accesses use 2 CPU clocks */ - SYSCON_FLASH_3CYCLE, /*!< Flash accesses use 3 CPU clocks */ - SYSCON_FLASH_4CYCLE, /*!< Flash accesses use 4 CPU clocks */ - SYSCON_FLASH_5CYCLE, /*!< Flash accesses use 5 CPU clocks */ - SYSCON_FLASH_6CYCLE, /*!< Flash accesses use 6 CPU clocks */ - SYSCON_FLASH_7CYCLE, /*!< Flash accesses use 7 CPU clocks */ - SYSCON_FLASH_8CYCLE /*!< Flash accesses use 8 CPU clocks */ -} SYSCON_FLASHTIM_T; - -/** - * @brief Set FLASH memory access time in clocks - * @param clks : Clock cycles for FLASH access - * @return Nothing - */ -STATIC INLINE void Chip_SYSCON_SetFLASHAccess(SYSCON_FLASHTIM_T clks) -{ - uint32_t tmp; - - tmp = LPC_SYSCON->FLASHCFG & ~(0xF << 12); - - /* Don't alter lower bits */ - LPC_SYSCON->FLASHCFG = tmp | ((uint32_t) clks << 12); -} - -/** - * @brief System FIFO bit definitions - */ -#define SYSCON_FIFO_U0TXFIFOEN (1 << 0) /*!< USART0 transmitter FIFO enable bit */ -#define SYSCON_FIFO_U1TXFIFOEN (1 << 1) /*!< USART1 transmitter FIFO enable bit */ -#define SYSCON_FIFO_U2TXFIFOEN (1 << 2) /*!< USART2 transmitter FIFO enable bit */ -#define SYSCON_FIFO_U3TXFIFOEN (1 << 3) /*!< USART3 transmitter FIFO enable bit */ -#define SYSCON_FIFO_SPI0TXFIFOEN (1 << 4) /*!< SPI0 transmitter FIFO enable bit */ -#define SYSCON_FIFO_SPI1TXFIFOEN (1 << 5) /*!< SPI1 transmitter FIFO enable bit */ -#define SYSCON_FIFO_U0RXFIFOEN (1 << 8) /*!< USART0 receiver FIFO enable bit */ -#define SYSCON_FIFO_U1RXFIFOEN (1 << 9) /*!< USART1 receiver FIFO enable bit */ -#define SYSCON_FIFO_U2RXFIFOEN (1 << 10) /*!< USART2 receiver FIFO enable bit */ -#define SYSCON_FIFO_U3RXFIFOEN (1 << 11) /*!< USART3 receiver FIFO enable bit */ -#define SYSCON_FIFO_SPI0RXFIFOEN (1 << 12) /*!< SPI0 receiver FIFO enable bit */ -#define SYSCON_FIFO_SPI1RXFIFOEN (1 << 13) /*!< SPI1 receiver FIFO enable bit */ - -/** - * @brief Enable System FIFO(s) for a peripheral - * @param enMask : Or'ed bits or type SYSCON_FIFO_* for enabling system FIFOs - * @return Nothing - */ -STATIC INLINE void Chip_SYSCON_EnableSysFIFO(uint32_t enMask) -{ - LPC_SYSCON->FIFOCTRL |= enMask; -} - -/** - * @brief Disable System FIFO(s) for a peripheral - * @param disMask : Or'ed bits or type SYSCON_FIFO_* for disabling system FIFOs - * @return Nothing - */ -STATIC INLINE void Chip_SYSCON_DisableSysFIFO(uint32_t disMask) -{ - LPC_SYSCON->FIFOCTRL &= ~disMask; -} - -/** - * Power control definition bits (0 = powered, 1 = powered down) - */ -#define SYSCON_PDRUNCFG_PD_IRC_OSC (1 << 3) /*!< IRC oscillator output */ -#define SYSCON_PDRUNCFG_PD_IRC (1 << 4) /*!< IRC oscillator */ -#define SYSCON_PDRUNCFG_PD_FLASH (1 << 5) /*!< Flash memory */ -#define SYSCON_PDRUNCFG_PD_BOD_RST (1 << 7) /*!< Brown-out Detect reset */ -#define SYSCON_PDRUNCFG_PD_BOD_INTR (1 << 8) /*!< Brown-out Detect interrupt */ -#define SYSCON_PDRUNCFG_PD_ADC0 (1 << 10) /*!< ADC0 */ -#define SYSCON_PDRUNCFG_PD_SRAM0A (1 << 13) /*!< First 8 kB of SRAM0 */ -#define SYSCON_PDRUNCFG_PD_SRAM0B (1 << 14) /*!< Remaining portion of SRAM0 */ -#define SYSCON_PDRUNCFG_PD_SRAM1 (1 << 15) /*!< SRAM1 */ -#define SYSCON_PDRUNCFG_PD_SRAM2 (1 << 16) /*!< SRAM2 */ -#define SYSCON_PDRUNCFG_PD_ROM (1 << 17) /*!< ROM */ -#define SYSCON_PDRUNCFG_PD_VDDA_ENA (1 << 19) /*!< Vdda to the ADC, must be enabled for the ADC to work */ -#define SYSCON_PDRUNCFG_PD_WDT_OSC (1 << 20) /*!< Watchdog oscillator */ -#define SYSCON_PDRUNCFG_PD_SYS_PLL (1 << 22) /*!< PLL0 */ -#define SYSCON_PDRUNCFG_PD_VREFP (1 << 23) /*!< Vrefp to the ADC, must be enabled for the ADC to work */ -#define SYSCON_PDRUNCFG_PD_32K_OSC (1 << 24) /*!< 32 kHz RTC oscillator */ - -/** - * @brief Power up one or more blocks or peripherals - * @return OR'ed values of SYSCON_PDRUNCFG_* values - * @note A high state indicates the peripheral is powered down. - */ -STATIC INLINE uint32_t Chip_SYSCON_GetPowerStates(void) -{ - return LPC_SYSCON->PDRUNCFG; -} - -/** - * @brief Power down one or more blocks or peripherals - * @param powerdownmask : OR'ed values of SYSCON_PDRUNCFG_* values - * @return Nothing - */ -STATIC INLINE void Chip_SYSCON_PowerDown(uint32_t powerdownmask) -{ - /* Disable peripheral states by setting high */ - LPC_SYSCON->PDRUNCFGSET = powerdownmask; -} - -/** - * @brief Power up one or more blocks or peripherals - * @param powerupmask : OR'ed values of SYSCON_PDRUNCFG_* values - * @return Nothing - */ -void Chip_SYSCON_PowerUp(uint32_t powerupmask); - -/** - * Start enable enumerations - for enabling and disabling peripheral wakeup - */ -typedef enum { - SYSCON_STARTER_WWDT = 0, - SYSCON_STARTER_BOD, - SYSCON_STARTER_DMA = 3, - SYSCON_STARTER_GINT0, - SYSCON_STARTER_PINT0, - SYSCON_STARTER_PINT1, - SYSCON_STARTER_PINT2, - SYSCON_STARTER_PINT3, - SYSCON_STARTER_UTICK, - SYSCON_STARTER_MRT, - SYSCON_STARTER_TIMER0, - SYSCON_STARTER_TIMER1, - SYSCON_STARTER_TIMER2, - SYSCON_STARTER_TIMER3, - SYSCON_STARTER_TIMER4, - SYSCON_STARTER_SCT0, - SYSCON_STARTER_USART0, - SYSCON_STARTER_USART1, - SYSCON_STARTER_USART2, - SYSCON_STARTER_USART3, - SYSCON_STARTER_I2C0, - SYSCON_STARTER_I2C1, - SYSCON_STARTER_I2C2, - SYSCON_STARTER_SPI0, - SYSCON_STARTER_SPI1, - SYSCON_STARTER_ADC0_SEQA, - SYSCON_STARTER_ADC0_SEQB, - SYSCON_STARTER_ADC0_THCMP, - SYSCON_STARTER_RTC, - SYSCON_STARTER_MAILBOX = 31, - /* For M4 only */ - SYSCON_STARTER_GINT1 = 32 + 0, - SYSCON_STARTER_PINT4, - SYSCON_STARTER_PINT5, - SYSCON_STARTER_PINT6, - SYSCON_STARTER_PINT7, - SYSCON_STARTER_RIT = 32 + 8, -} CHIP_SYSCON_WAKEUP_T; - -/** - * @brief Enables a pin's (PINT) wakeup logic - * @param periphId : Peripheral identifier - * @return Nothing - */ -STATIC INLINE void Chip_SYSCON_EnableWakeup(CHIP_SYSCON_WAKEUP_T periphId) -{ - uint32_t pid = (uint32_t) periphId; - - if (pid < 32) { - LPC_SYSCON->STARTERSET[0] = (1 << pid); - } - else { - LPC_SYSCON->STARTERSET[1] = (1 << (pid - 32)); - } -} - -/** - * @brief Disables peripheral's wakeup logic - * @param periphId : Peripheral identifier - * @return Nothing - */ -STATIC INLINE void Chip_SYSCON_DisableWakeup(CHIP_SYSCON_WAKEUP_T periphId) -{ - uint32_t pid = (uint32_t) periphId; - - if (pid < 32) { - LPC_SYSCON->STARTERCLR[0] = (1 << pid); - } - else { - LPC_SYSCON->STARTERCLR[1] = (1 << (pid - 32)); - } -} - -/** - * @brief Return the device ID - * @return Device ID - */ -STATIC INLINE uint32_t Chip_SYSCON_GetDeviceID(void) -{ - return LPC_SYSCON->DEVICE_ID0; -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSCON_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/sysinit_5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/sysinit_5410x.c deleted file mode 100644 index 06b9170f9ec..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/sysinit_5410x.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * @brief LPC5410X Chip specific SystemInit - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/* Sets the best FLASH clock arte for the passed frequency */ -static void setupFlashClocks(uint32_t freq) -{ - /* v17.0 ROM support only - coarse FLASH clocking timing. - FLASH access is setup based on voltage for v17.1 and later ROMs - as part of the power library. */ - if (Chip_POWER_GetROMVersion() == LPC5410X_ROMVER_0) { - if (freq < 20000000) { - Chip_SYSCON_SetFLASHAccess(SYSCON_FLASH_1CYCLE); - } - else if (freq < 48000000) { - Chip_SYSCON_SetFLASHAccess(SYSCON_FLASH_2CYCLE); - } - else if (freq < 72000000) { - Chip_SYSCON_SetFLASHAccess(SYSCON_FLASH_3CYCLE); - } - else { - Chip_SYSCON_SetFLASHAccess(SYSCON_FLASH_4CYCLE); - } - } -} - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Clock and PLL initialization based on the internal oscillator */ -void Chip_SetupIrcClocking(uint32_t iFreq) -{ - PLL_CONFIG_T pllConfig; - PLL_SETUP_T pllSetup; - PLL_ERROR_T pllError; - - /* Turn on the IRC by clearing the power down bit */ - Chip_SYSCON_PowerUp(SYSCON_PDRUNCFG_PD_IRC_OSC | SYSCON_PDRUNCFG_PD_IRC); - - /* Select the PLL input to the IRC */ - Chip_Clock_SetSystemPLLSource(SYSCON_PLLCLKSRC_IRC); - - /* Setup FLASH access û½øÈ¥??*/ - setupFlashClocks(iFreq); - - /* Power down PLL to change the PLL divider ratio */ - Chip_SYSCON_PowerDown(SYSCON_PDRUNCFG_PD_SYS_PLL); - - /* Setup PLL configuration */ - pllConfig.desiredRate = iFreq; - pllConfig.InputRate = 0; - pllConfig.flags = PLL_CONFIGFLAG_FORCENOFRACT; - pllError = Chip_Clock_SetupPLLData(&pllConfig, &pllSetup); - if (pllError == PLL_ERROR_SUCCESS) { - pllSetup.flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_ADGVOLT; - pllError = Chip_Clock_SetupSystemPLLPrec(&pllSetup); - } - - /* Set system clock divider to 1 */ - Chip_Clock_SetSysClockDiv(1); - - /* Set main clock source to the system PLL. This will drive 24MHz - for the main clock and 24MHz for the system clock */ - Chip_Clock_SetMainClockSource(SYSCON_MAINCLKSRC_PLLOUT); - - /* ASYSNC SYSCON needs to be on or all serial peripheral won't work. - Be careful if PLL is used or not, ASYNC_SYSCON source needs to be - selected carefully. */ - Chip_SYSCON_Enable_ASYNC_Syscon(true); - Chip_Clock_SetAsyncSysconClockDiv(1); - Chip_Clock_SetAsyncSysconClockSource(SYSCON_ASYNC_IRC); -} - -/* Clock and PLL initialization based on the external clock input */ -void Chip_SetupExtInClocking(uint32_t iFreq) -{ - PLL_CONFIG_T pllConfig; - PLL_SETUP_T pllSetup; - PLL_ERROR_T pllError; - - /* IOCON clock left on, this is needed is CLKIN is used. */ - Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_IOCON); - - /* Select external clock input pin */ - Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 22, (IOCON_MODE_PULLUP | - IOCON_FUNC1 | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF)); - - /* Select the PLL input to the EXT clock input */ - Chip_Clock_SetSystemPLLSource(SYSCON_PLLCLKSRC_CLKIN); - - /* Setup FLASH access */ - setupFlashClocks(iFreq); - - /* Power down PLL to change the PLL divider ratio */ - Chip_SYSCON_PowerDown(SYSCON_PDRUNCFG_PD_SYS_PLL); - - /* Setup PLL configuration */ - pllConfig.desiredRate = iFreq; - pllConfig.InputRate = 0; - pllConfig.flags = PLL_CONFIGFLAG_FORCENOFRACT; - pllError = Chip_Clock_SetupPLLData(&pllConfig, &pllSetup); - if (pllError == PLL_ERROR_SUCCESS) { - pllSetup.flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_ADGVOLT; - pllError = Chip_Clock_SetupSystemPLLPrec(&pllSetup); - } - - /* Set system clock divider to 1 */ - Chip_Clock_SetSysClockDiv(1); - - /* Set main clock source to the system PLL. This will drive 24MHz - for the main clock and 24MHz for the system clock */ - Chip_Clock_SetMainClockSource(SYSCON_MAINCLKSRC_PLLOUT); - - /* ASYSNC SYSCON needs to be on or all serial peripheral won't work. - Be careful if PLL is used or not, ASYNC_SYSCON source needs to be - selected carefully. */ - Chip_SYSCON_Enable_ASYNC_Syscon(true); - Chip_Clock_SetAsyncSysconClockDiv(1); - Chip_Clock_SetAsyncSysconClockSource(SYSCON_ASYNC_IRC); -} - -/* Set up and initialize hardware prior to call to main */ -void Chip_SystemInit(void) -{ - /* Initial internal clocking @100MHz */ - Chip_SetupIrcClocking(100000000); -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/timer_5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/timer_5410x.c deleted file mode 100644 index 7938a1988aa..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/timer_5410x.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * @brief LPC5410X 32-bit Timer/PWM driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -struct TBASE_TO_TMRBITS { - uint32_t base; - uint8_t clockID; - uint8_t resetID; -}; - -#define LAST_TIMER (4) -static const struct TBASE_TO_TMRBITS tbaseToTimerIDs[LAST_TIMER + 1] = { - {LPC_TIMER0_BASE, (uint8_t) SYSCON_CLOCK_TIMER0, (uint8_t) RESET_TIMER0}, - {LPC_TIMER1_BASE, (uint8_t) SYSCON_CLOCK_TIMER1, (uint8_t) RESET_TIMER1}, - {LPC_TIMER2_BASE, (uint8_t) SYSCON_CLOCK_TIMER2, (uint8_t) RESET_TIMER2}, - {LPC_TIMER3_BASE, (uint8_t) SYSCON_CLOCK_TIMER3, (uint8_t) RESET_TIMER3}, - {LPC_TIMER4_BASE, (uint8_t) SYSCON_CLOCK_TIMER4, (uint8_t) RESET_TIMER4} -}; - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/* Return index into tbaseToTimerIDs for timers 0-4 */ -static int GetClockID(LPC_TIMER_T *pTMR) -{ - int timerId = LAST_TIMER; - - while (timerId >= 0) { - if (pTMR == (LPC_TIMER_T *) tbaseToTimerIDs[timerId].base) { - return timerId; - } - - timerId--; - } - - /* Waill return timer 0 if no timer match */ - return 0; -} - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Initialize a timer */ -void Chip_TIMER_Init(LPC_TIMER_T *pTMR) -{ - int clockId = GetClockID(pTMR); - - Chip_Clock_EnablePeriphClock((CHIP_SYSCON_CLOCK_T) tbaseToTimerIDs[clockId].clockID); - Chip_SYSCON_PeriphReset((CHIP_SYSCON_PERIPH_RESET_T) tbaseToTimerIDs[clockId].resetID); -} - -/* Shutdown a timer */ -void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR) -{ - int clockId = GetClockID(pTMR); - - Chip_Clock_DisablePeriphClock((CHIP_SYSCON_CLOCK_T) tbaseToTimerIDs[clockId].clockID); -} - -/* Resets the timer counter and prescale counts to 0 */ -void Chip_TIMER_Reset(LPC_TIMER_T *pTMR) -{ - uint32_t reg; - - /* Disable timer, set terminal count to non-0 */ - reg = pTMR->TCR; - pTMR->TCR = 0; - pTMR->TC = 1; - - /* Reset timer counter */ - pTMR->TCR = TIMER_RESET; - - /* Wait for terminal count to clear */ - while (pTMR->TC != 0) {} - - /* Restore timer state */ - pTMR->TCR = reg; -} - -/* Sets external match control (MATn.matchnum) pin control */ -void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state, - TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum) -{ - uint32_t mask, reg; - - /* Clear bits corresponding to selected match register */ - mask = (1 << matchnum) | (0x03 << (4 + (matchnum * 2))); - /* Also mask reserved bits */ - reg = (pTMR->EMR & TIMER_EMR_MASK) & ~mask; - - /* Set new configuration for selected match register */ - pTMR->EMR = reg | (((uint32_t) initial_state) << matchnum) | - (((uint32_t) matchState) << (4 + (matchnum * 2))); -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/timer_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/timer_5410x.h deleted file mode 100644 index 59bbee9083c..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/timer_5410x.h +++ /dev/null @@ -1,456 +0,0 @@ -/* - * @brief LPC5410X 32-bit Timer/PWM driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __TIMER_5410X_H_ -#define __TIMER_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup TIMER_5410X CHIP: LPC5410X 32-bit Timer driver - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/** - * @brief 32-bit Standard timer register block structure - */ -typedef struct { /*!< TIMERn Structure */ - __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ - __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ - __IO uint32_t TC; /*!< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */ - __IO uint32_t PR; /*!< Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */ - __IO uint32_t PC; /*!< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */ - __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */ - __IO uint32_t MR[4]; /*!< Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ - __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ - __IO uint32_t CR[4]; /*!< Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */ - __IO uint32_t EMR; /*!< External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */ - __I uint32_t RESERVED0[12]; - __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ - __IO uint32_t PWMC; -} LPC_TIMER_T; - -/** Macro to clear interrupt pending */ -#define TIMER_IR_CLR(n) _BIT(n) - -/** Macro for getting a timer match interrupt bit */ -#define TIMER_MATCH_INT(n) (_BIT((n) & 0x0F)) -/** Macro for getting a capture event interrupt bit */ -#define TIMER_CAP_INT(n) (_BIT((((n) & 0x0F) + 4))) - -/** Timer/counter enable bit */ -#define TIMER_ENABLE ((uint32_t) (1 << 0)) -/** Timer/counter reset bit */ -#define TIMER_RESET ((uint32_t) (1 << 1)) -/** Timer Control register Mask */ -#define TIMER_CTRL_MASK ((uint32_t) 0x03) - -/** Bit location for interrupt on MRx match, n = 0 to 3 */ -#define TIMER_INT_ON_MATCH(n) (_BIT(((n) * 3))) -/** Bit location for reset on MRx match, n = 0 to 3 */ -#define TIMER_RESET_ON_MATCH(n) (_BIT((((n) * 3) + 1))) -/** Bit location for stop on MRx match, n = 0 to 3 */ -#define TIMER_STOP_ON_MATCH(n) (_BIT((((n) * 3) + 2))) -/** Match Control register Mask */ -#define TIMER_MCR_MASK ((uint32_t) 0x0FFF) - -/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */ -#define TIMER_CAP_RISING(n) (_BIT(((n) * 3))) -/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */ -#define TIMER_CAP_FALLING(n) (_BIT((((n) * 3) + 1))) -/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */ -#define TIMER_INT_ON_CAP(n) (_BIT((((n) * 3) + 2))) -/** Capture Control register Mask */ -#define TIMER_CCR_MASK ((uint32_t) 0x0FFF) -/** External Match register Mask */ -#define TIMER_EMR_MASK ((uint32_t) 0x0FFF) -/** Counter Control register Mask */ -#define TIMER_CTCR_MASK ((uint32_t) 0x0F) - -/** - * @brief Initialize a timer - * @param pTMR : Pointer to timer IP register address - * @return Nothing - */ -void Chip_TIMER_Init(LPC_TIMER_T *pTMR); - -/** - * @brief Shutdown a timer - * @param pTMR : Pointer to timer IP register address - * @return Nothing - */ -void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR); - -/** - * @brief Determine if a match interrupt is pending - * @param pTMR : Pointer to timer IP register address - * @param matchnum : Match interrupt number to check - * @return false if the interrupt is not pending, otherwise true - * @note Determine if the match interrupt for the passed timer and match - * counter is pending. - */ -STATIC INLINE bool Chip_TIMER_MatchPending(LPC_TIMER_T *pTMR, int8_t matchnum) -{ - return (bool) ((pTMR->IR & TIMER_MATCH_INT(matchnum)) != 0); -} - -/** - * @brief Determine if a capture interrupt is pending - * @param pTMR : Pointer to timer IP register address - * @param capnum : Capture interrupt number to check - * @return false if the interrupt is not pending, otherwise true - * @note Determine if the capture interrupt for the passed capture pin is - * pending. - */ -STATIC INLINE bool Chip_TIMER_CapturePending(LPC_TIMER_T *pTMR, int8_t capnum) -{ - return (bool) ((pTMR->IR & TIMER_CAP_INT(capnum)) != 0); -} - -/** - * @brief Clears a (pending) match interrupt - * @param pTMR : Pointer to timer IP register address - * @param matchnum : Match interrupt number to clear - * @return Nothing - * @note Clears a pending timer match interrupt. - */ -STATIC INLINE void Chip_TIMER_ClearMatch(LPC_TIMER_T *pTMR, int8_t matchnum) -{ - pTMR->IR = TIMER_IR_CLR(matchnum); -} - -/** - * @brief Clears a (pending) capture interrupt - * @param pTMR : Pointer to timer IP register address - * @param capnum : Capture interrupt number to clear - * @return Nothing - * @note Clears a pending timer capture interrupt. - */ -STATIC INLINE void Chip_TIMER_ClearCapture(LPC_TIMER_T *pTMR, int8_t capnum) -{ - pTMR->IR = (0x10 << capnum); -} - -/** - * @brief Enables the timer (starts count) - * @param pTMR : Pointer to timer IP register address - * @return Nothing - * @note Enables the timer to start counting. - */ -STATIC INLINE void Chip_TIMER_Enable(LPC_TIMER_T *pTMR) -{ - pTMR->TCR = (pTMR->TCR & TIMER_CTRL_MASK) | TIMER_ENABLE; -} - -/** - * @brief Disables the timer (stops count) - * @param pTMR : Pointer to timer IP register address - * @return Nothing - * @note Disables the timer to stop counting. - */ -STATIC INLINE void Chip_TIMER_Disable(LPC_TIMER_T *pTMR) -{ - pTMR->TCR = (pTMR->TCR & TIMER_CTRL_MASK) & ~TIMER_ENABLE; -} - -/** - * @brief Returns the current timer count - * @param pTMR : Pointer to timer IP register address - * @return Current timer terminal count value - * @note Returns the current timer terminal count. - */ -STATIC INLINE uint32_t Chip_TIMER_ReadCount(LPC_TIMER_T *pTMR) -{ - return pTMR->TC; -} - -/** - * @brief Returns the current prescale count - * @param pTMR : Pointer to timer IP register address - * @return Current timer prescale count value - * @note Returns the current prescale count. - */ -STATIC INLINE uint32_t Chip_TIMER_ReadPrescale(LPC_TIMER_T *pTMR) -{ - return pTMR->PC; -} - -/** - * @brief Sets the prescaler value - * @param pTMR : Pointer to timer IP register address - * @param prescale : Prescale value to set the prescale register to - * @return Nothing - * @note Sets the prescale count value. - */ -STATIC INLINE void Chip_TIMER_PrescaleSet(LPC_TIMER_T *pTMR, uint32_t prescale) -{ - pTMR->PR = prescale; -} - -/** - * @brief Sets a timer match value - * @param pTMR : Pointer to timer IP register address - * @param matchnum : Match timer to set match count for - * @param matchval : Match value for the selected match count - * @return Nothing - * @note Sets one of the timer match values. - */ -STATIC INLINE void Chip_TIMER_SetMatch(LPC_TIMER_T *pTMR, int8_t matchnum, uint32_t matchval) -{ - pTMR->MR[matchnum] = matchval; -} - -/** - * @brief Reads a capture register - * @param pTMR : Pointer to timer IP register address - * @param capnum : Capture register to read - * @return The selected capture register value - * @note Returns the selected capture register value. - */ -STATIC INLINE uint32_t Chip_TIMER_ReadCapture(LPC_TIMER_T *pTMR, int8_t capnum) -{ - return pTMR->CR[capnum]; -} - -/** - * @brief Resets the timer terminal and prescale counts to 0 - * @param pTMR : Pointer to timer IP register address - * @return Nothing - */ -void Chip_TIMER_Reset(LPC_TIMER_T *pTMR); - -/** - * @brief Enables a match interrupt that fires when the terminal count - * matches the match counter value. - * @param pTMR : Pointer to timer IP register address - * @param matchnum : Match timer, 0 to 3 - * @return Nothing - */ -STATIC INLINE void Chip_TIMER_MatchEnableInt(LPC_TIMER_T *pTMR, int8_t matchnum) -{ - pTMR->MCR = (pTMR->MCR & TIMER_MCR_MASK) | TIMER_INT_ON_MATCH(matchnum); -} - -/** - * @brief Disables a match interrupt for a match counter. - * @param pTMR : Pointer to timer IP register address - * @param matchnum : Match timer, 0 to 3 - * @return Nothing - */ -STATIC INLINE void Chip_TIMER_MatchDisableInt(LPC_TIMER_T *pTMR, int8_t matchnum) -{ - pTMR->MCR = (pTMR->MCR & TIMER_MCR_MASK) & ~TIMER_INT_ON_MATCH(matchnum); -} - -/** - * @brief For the specific match counter, enables reset of the terminal count register when a match occurs - * @param pTMR : Pointer to timer IP register address - * @param matchnum : Match timer, 0 to 3 - * @return Nothing - */ -STATIC INLINE void Chip_TIMER_ResetOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum) -{ - pTMR->MCR = (pTMR->MCR & TIMER_MCR_MASK) | TIMER_RESET_ON_MATCH(matchnum); -} - -/** - * @brief For the specific match counter, disables reset of the terminal count register when a match occurs - * @param pTMR : Pointer to timer IP register address - * @param matchnum : Match timer, 0 to 3 - * @return Nothing - */ -STATIC INLINE void Chip_TIMER_ResetOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum) -{ - pTMR->MCR = (pTMR->MCR & TIMER_MCR_MASK) & ~TIMER_RESET_ON_MATCH(matchnum); -} - -/** - * @brief Enable a match timer to stop the terminal count when a - * match count equals the terminal count. - * @param pTMR : Pointer to timer IP register address - * @param matchnum : Match timer, 0 to 3 - * @return Nothing - */ -STATIC INLINE void Chip_TIMER_StopOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum) -{ - pTMR->MCR = (pTMR->MCR & TIMER_MCR_MASK) | TIMER_STOP_ON_MATCH(matchnum); -} - -/** - * @brief Disable stop on match for a match timer. Disables a match timer - * to stop the terminal count when a match count equals the terminal count. - * @param pTMR : Pointer to timer IP register address - * @param matchnum : Match timer, 0 to 3 - * @return Nothing - */ -STATIC INLINE void Chip_TIMER_StopOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum) -{ - pTMR->MCR = (pTMR->MCR & TIMER_MCR_MASK) & ~TIMER_STOP_ON_MATCH(matchnum); -} - -/** - * @brief Enables capture on on rising edge of selected CAP signal for the - * selected capture register, enables the selected CAPn.capnum signal to load - * the capture register with the terminal coount on a rising edge. - * @param pTMR : Pointer to timer IP register address - * @param capnum : Capture signal/register to use - * @return Nothing - */ -STATIC INLINE void Chip_TIMER_CaptureRisingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum) -{ - pTMR->CCR = (pTMR->CCR & TIMER_CCR_MASK) | TIMER_CAP_RISING(capnum); -} - -/** - * @brief Disables capture on on rising edge of selected CAP signal. For the - * selected capture register, disables the selected CAPn.capnum signal to load - * the capture register with the terminal coount on a rising edge. - * @param pTMR : Pointer to timer IP register address - * @param capnum : Capture signal/register to use - * @return Nothing - */ -STATIC INLINE void Chip_TIMER_CaptureRisingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum) -{ - pTMR->CCR = (pTMR->CCR & TIMER_CCR_MASK) & ~TIMER_CAP_RISING(capnum); -} - -/** - * @brief Enables capture on on falling edge of selected CAP signal. For the - * selected capture register, enables the selected CAPn.capnum signal to load - * the capture register with the terminal coount on a falling edge. - * @param pTMR : Pointer to timer IP register address - * @param capnum : Capture signal/register to use - * @return Nothing - */ -STATIC INLINE void Chip_TIMER_CaptureFallingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum) -{ - pTMR->CCR = (pTMR->CCR & TIMER_CCR_MASK) | TIMER_CAP_FALLING(capnum); -} - -/** - * @brief Disables capture on on falling edge of selected CAP signal. For the - * selected capture register, disables the selected CAPn.capnum signal to load - * the capture register with the terminal coount on a falling edge. - * @param pTMR : Pointer to timer IP register address - * @param capnum : Capture signal/register to use - * @return Nothing - */ -STATIC INLINE void Chip_TIMER_CaptureFallingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum) -{ - pTMR->CCR = (pTMR->CCR & TIMER_CCR_MASK) & ~TIMER_CAP_FALLING(capnum); -} - -/** - * @brief Enables interrupt on capture of selected CAP signal. For the - * selected capture register, an interrupt will be generated when the enabled - * rising or falling edge on CAPn.capnum is detected. - * @param pTMR : Pointer to timer IP register address - * @param capnum : Capture signal/register to use - * @return Nothing - */ -STATIC INLINE void Chip_TIMER_CaptureEnableInt(LPC_TIMER_T *pTMR, int8_t capnum) -{ - pTMR->CCR = (pTMR->CCR & TIMER_CCR_MASK) | TIMER_INT_ON_CAP(capnum); -} - -/** - * @brief Disables interrupt on capture of selected CAP signal - * @param pTMR : Pointer to timer IP register address - * @param capnum : Capture signal/register to use - * @return Nothing - */ -STATIC INLINE void Chip_TIMER_CaptureDisableInt(LPC_TIMER_T *pTMR, int8_t capnum) -{ - pTMR->CCR = (pTMR->CCR & TIMER_CCR_MASK) & ~TIMER_INT_ON_CAP(capnum); -} - -/** - * @brief Standard timer initial match pin state and change state - */ -typedef enum IP_TIMER_PIN_MATCH_STATE { - TIMER_EXTMATCH_DO_NOTHING = 0, /*!< Timer match state does nothing on match pin */ - TIMER_EXTMATCH_CLEAR = 1, /*!< Timer match state sets match pin low */ - TIMER_EXTMATCH_SET = 2, /*!< Timer match state sets match pin high */ - TIMER_EXTMATCH_TOGGLE = 3 /*!< Timer match state toggles match pin */ -} TIMER_PIN_MATCH_STATE_T; - -/** - * @brief Sets external match control (MATn.matchnum) pin control. For the pin - * selected with matchnum, sets the function of the pin that occurs on - * a terminal count match for the match count. - * @param pTMR : Pointer to timer IP register address - * @param initial_state : Initial state of the pin, high(1) or low(0) - * @param matchState : Selects the match state for the pin - * @param matchnum : MATn.matchnum signal to use - * @return Nothing - * @note For the pin selected with matchnum, sets the function of the pin that occurs on - * a terminal count match for the match count. - */ -void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state, - TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum); - -/** - * @brief Standard timer clock and edge for count source - */ -typedef enum IP_TIMER_CAP_SRC_STATE { - TIMER_CAPSRC_RISING_PCLK = 0, /*!< Timer ticks on PCLK rising edge */ - TIMER_CAPSRC_RISING_CAPN = 1, /*!< Timer ticks on CAPn.x rising edge */ - TIMER_CAPSRC_FALLING_CAPN = 2, /*!< Timer ticks on CAPn.x falling edge */ - TIMER_CAPSRC_BOTH_CAPN = 3 /*!< Timer ticks on CAPn.x both edges */ -} TIMER_CAP_SRC_STATE_T; - -/** - * @brief Sets timer count source and edge with the selected passed from CapSrc. - * If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value. - * @param pTMR : Pointer to timer IP register address - * @param capSrc : timer clock source and edge - * @param capnum : CAPn.capnum pin to use (0 - 2) - * @return Nothing - * @note If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value. - */ -STATIC INLINE void Chip_TIMER_TIMER_SetCountClockSrc(LPC_TIMER_T *pTMR, - TIMER_CAP_SRC_STATE_T capSrc, - int8_t capnum) -{ - pTMR->CTCR = (pTMR->CTCR & ~TIMER_CTCR_MASK) | ((uint32_t) capSrc | ((uint32_t) capnum) << 2); -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __TIMER_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/utick_5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/utick_5410x.c deleted file mode 100644 index a52fb3e4883..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/utick_5410x.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * @brief LPC5410X UTICK chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Setup UTICK */ -void Chip_UTICK_SetTick(LPC_UTICK_T *pUTICK, uint32_t tick_value, bool repeat) -{ - if (repeat) { - tick_value |= UTICK_CTRL_REPEAT; - } - - pUTICK->CTRL = tick_value; -} - -/* Setup UTICK for the passed delay */ -void Chip_UTICK_SetDelayMs(LPC_UTICK_T *pUTICK, uint32_t delayMs, bool repeat) -{ - uint32_t tick_value = (delayMs * Chip_Clock_GetWDTOSCRate()) / 1000; - - if (repeat) { - tick_value |= UTICK_CTRL_REPEAT; - } - else { - tick_value &= ~UTICK_CTRL_REPEAT; - } - - pUTICK->CTRL = tick_value; -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/utick_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/utick_5410x.h deleted file mode 100644 index 8053dea6c78..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/utick_5410x.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * @brief LPC5410X Micro Tick chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __UTICK_5410X_H_ -#define __UTICK_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup UTICK_5410X CHIP: LPC5410X Micro Tick driver - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/** - * @brief Micro Tick register block structure - */ -typedef struct { - __IO uint32_t CTRL; /*!< UTick Control register */ - __IO uint32_t STATUS; /*!< UTick Status register */ -} LPC_UTICK_T; - -/** - * @brief UTick register definitions - */ -/** UTick repeat delay bit */ -#define UTICK_CTRL_REPEAT ((uint32_t) 1UL << 31) -/** UTick Delay Value Mask */ -#define UTICK_CTRL_DELAY_MASK ((uint32_t) 0x7FFFFFFF) -/** UTick Interrupt Status bit */ -#define UTICK_STATUS_INTR ((uint32_t) 1 << 0) -/** UTick Active Status bit */ -#define UTICK_STATUS_ACTIVE ((uint32_t) 1 << 1) -/** UTick Status Register Mask */ -#define UTICK_STATUS_MASK ((uint32_t) 0x03) - -/** - * @brief Initialize the UTICK peripheral - * @param pUTICK : UTICK peripheral selected - * @return Nothing - */ -STATIC INLINE void Chip_UTICK_Init(LPC_UTICK_T *pUTICK) -{ - Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_UTICK); - Chip_SYSCON_PeriphReset(RESET_UTICK); -} - -/** - * @brief De-initialize the UTICK peripheral - * @param pUTICK : UTICK peripheral selected - * @return Nothing - */ -STATIC INLINE void Chip_UTICK_DeInit(LPC_UTICK_T *pUTICK) -{ - Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_UTICK); -} - -/** - * @brief Setup UTICK - * @param pUTICK : The base address of UTICK block - * @param tick_value : Tick value, should not exceed UTICK_CTRL_DELAY_MASK - * @param repeat : If true then delay repeats continuously else it is one time - * @return Nothing - */ -void Chip_UTICK_SetTick(LPC_UTICK_T *pUTICK, uint32_t tick_value, bool repeat); - -/** - * @brief Setup UTICK for the passed delay (in mS) - * @param pUTICK : The base address of UTICK block - * @param delayMs : Delay value in mS (Maximum is 1000mS) - * @param repeat : If true then delay repeats continuously else it is one time - * @return Nothing - * @note The WDT oscillator runs at about 500KHz, so delays in uS won't be - * too accurate. - */ -void Chip_UTICK_SetDelayMs(LPC_UTICK_T *pUTICK, uint32_t delayMs, bool repeat); - -/** - * @brief Read UTICK Value - * @param pUTICK : The base address of UTICK block - * @return Current tick value - */ -STATIC INLINE uint32_t Chip_UTICK_GetTick(LPC_UTICK_T *pUTICK) -{ - return pUTICK->CTRL & UTICK_CTRL_DELAY_MASK; -} - -/** - * @brief Halt UTICK timer - * @param pUTICK : The base address of UTICK block - * @return Nothing - */ -STATIC INLINE void Chip_UTICK_Halt(LPC_UTICK_T *pUTICK) -{ - pUTICK->CTRL = 0; -} - -/** - * @brief Returns the status of UTICK - * @param pUTICK : The base address of UTICK block - * @return Micro tick timer status register value - */ -STATIC INLINE uint32_t Chip_UTICK_GetStatus(LPC_UTICK_T *pUTICK) -{ - return pUTICK->STATUS; -} - -/** - * @brief Clears UTICK Interrupt flag - * @param pUTICK : The base address of UTICK block - * @return Nothing - */ -STATIC INLINE void Chip_UTICK_ClearInterrupt(LPC_UTICK_T *pUTICK) -{ - pUTICK->STATUS = UTICK_STATUS_INTR; -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __UTICK_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/wwdt_5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/wwdt_5410x.c deleted file mode 100644 index a1a6b862b53..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/wwdt_5410x.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * @brief LPC5410X WWDT chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Initialize the Watchdog timer */ -void Chip_WWDT_Init(LPC_WWDT_T *pWWDT) -{ - Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_WWDT); - Chip_SYSCON_PeriphReset(RESET_WWDT); - - /* Disable watchdog */ - pWWDT->MOD = 0; - pWWDT->TC = 0xFF; - pWWDT->WARNINT = 0x3FF; - pWWDT->WINDOW = 0xFFFFFF; -} - -/* Clear WWDT interrupt status flags */ -void Chip_WWDT_ClearStatusFlag(LPC_WWDT_T *pWWDT, uint32_t status) -{ - if (status & WWDT_WDMOD_WDTOF) { - pWWDT->MOD &= (~WWDT_WDMOD_WDTOF) & WWDT_WDMOD_BITMASK; - } - /* Interrupt flag is cleared by writing a 1 */ - if (status & WWDT_WDMOD_WDINT) { - pWWDT->MOD = (pWWDT->MOD & WWDT_WDMOD_BITMASK) | WWDT_WDMOD_WDINT; - } -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/wwdt_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/wwdt_5410x.h deleted file mode 100644 index 1416ee5c7ff..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/wwdt_5410x.h +++ /dev/null @@ -1,244 +0,0 @@ -/* - * @brief LPC5410X WWDT chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __WWDT_5410X_H_ -#define __WWDT_5410X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup LPC_WWDT CHIP: LPC5410X Windowed Watchdog driver - * @ingroup CHIP_5410X_DRIVERS - * @{ - */ - -/** - * @brief Windowed Watchdog register block structure - */ -typedef struct { /*!< WWDT Structure */ - __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ - __IO uint32_t TC; /*!< Watchdog timer constant register. This register determines the time-out value. */ - __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */ - __I uint32_t TV; /*!< Watchdog timer value register. This register reads out the current value of the Watchdog timer. */ - __I uint32_t RESERVED0; - __IO uint32_t WARNINT; /*!< Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */ - __IO uint32_t WINDOW; /*!< Watchdog timer window register. This register contains the Watchdog window value. */ -} LPC_WWDT_T; - -/** - * @brief Watchdog Mode register definitions - */ -/** Watchdog Mode Bitmask */ -#define WWDT_WDMOD_BITMASK ((uint32_t) 0x3F) -/** WWDT enable bit */ -#define WWDT_WDMOD_WDEN ((uint32_t) (1 << 0)) -/** WWDT reset enable bit */ -#define WWDT_WDMOD_WDRESET ((uint32_t) (1 << 1)) -/** WWDT time-out flag bit */ -#define WWDT_WDMOD_WDTOF ((uint32_t) (1 << 2)) -/** WWDT warning interrupt flag bit */ -#define WWDT_WDMOD_WDINT ((uint32_t) (1 << 3)) -/** WWDT Protect flag bit */ -#define WWDT_WDMOD_WDPROTECT ((uint32_t) (1 << 4)) -/** WWDT lock bit */ -#define WWDT_WDMOD_LOCK ((uint32_t) (1 << 5)) - -/** - * @brief Initialize the Watchdog timer - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @return None - */ -void Chip_WWDT_Init(LPC_WWDT_T *pWWDT); - -/** - * @brief Shutdown the Watchdog timer - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @return None - */ -STATIC INLINE void Chip_WWDT_DeInit(LPC_WWDT_T *pWWDT) -{ - Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_WWDT); -} - -/** - * @brief Set WDT timeout constant value used for feed - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @param timeout : WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX - * @return none - */ -STATIC INLINE void Chip_WWDT_SetTimeOut(LPC_WWDT_T *pWWDT, uint32_t timeout) -{ - pWWDT->TC = timeout; -} - -/** - * @brief Feed watchdog timer - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @return None - * @note If this function isn't called, a watchdog timer warning will occur. - * After the warning, a timeout will occur if a feed has happened. - * Note that if WWDT registers are modified in an interrupt then it is a good - * idea to prevent those interrupts when writing the feed sequence. - */ -STATIC INLINE void Chip_WWDT_Feed(LPC_WWDT_T *pWWDT) -{ - pWWDT->FEED = 0xAA; - pWWDT->FEED = 0x55; -} - -/** - * @brief Set WWDT warning interrupt - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @param timeout : WDT warning in ticks, between 0 and 1023 - * @return None - * @note This is the number of ticks after the watchdog interrupt that the - * warning interrupt will be generated. - */ -STATIC INLINE void Chip_WWDT_SetWarning(LPC_WWDT_T *pWWDT, uint32_t timeout) -{ - pWWDT->WARNINT = timeout; -} - -/** - * @brief Get WWDT warning interrupt - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @return WWDT warning interrupt - */ -STATIC INLINE uint32_t Chip_WWDT_GetWarning(LPC_WWDT_T *pWWDT) -{ - return pWWDT->WARNINT; -} - -/** - * @brief Set WWDT window time - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @param timeout : WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX - * @return None - * @note The watchdog timer must be fed between the timeout from the Chip_WWDT_SetTimeOut() - * function and this function, with this function defining the last tick before the - * watchdog window interrupt occurs. - */ -STATIC INLINE void Chip_WWDT_SetWindow(LPC_WWDT_T *pWWDT, uint32_t timeout) -{ - pWWDT->WINDOW = timeout; -} - -/** - * @brief Get WWDT window time - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @return WWDT window time - */ -STATIC INLINE uint32_t Chip_WWDT_GetWindow(LPC_WWDT_T *pWWDT) -{ - return pWWDT->WINDOW; -} - -/** - * @brief Enable watchdog timer options - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @param options : An or'ed set of options of values - * WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT - * @return None - * @note You can enable more than one option at once (ie, WWDT_WDMOD_WDRESET | - * WWDT_WDMOD_WDPROTECT), but use the WWDT_WDMOD_WDEN after all other options - * are set (or unset) with no other options. If WWDT_WDMOD_LOCK is used, it cannot - * be unset. - */ -STATIC INLINE void Chip_WWDT_SetOption(LPC_WWDT_T *pWWDT, uint32_t options) -{ - pWWDT->MOD = (pWWDT->MOD & WWDT_WDMOD_BITMASK) | options; -} - -/** - * @brief Disable/clear watchdog timer options - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @param options : An or'ed set of options of values - * WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT - * @return None - * @note You can disable more than one option at once (ie, WWDT_WDMOD_WDRESET | - * WWDT_WDMOD_WDTOF). - */ -STATIC INLINE void Chip_WWDT_UnsetOption(LPC_WWDT_T *pWWDT, uint32_t options) -{ - pWWDT->MOD &= (~options) & WWDT_WDMOD_BITMASK; -} - -/** - * @brief Enable WWDT activity - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @return None - */ -STATIC INLINE void Chip_WWDT_Start(LPC_WWDT_T *pWWDT) -{ - Chip_WWDT_SetOption(pWWDT, WWDT_WDMOD_WDEN); - Chip_WWDT_Feed(pWWDT); -} - -/** - * @brief Read WWDT status flag - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @return Watchdog status, an Or'ed value of WWDT_WDMOD_* - */ -STATIC INLINE uint32_t Chip_WWDT_GetStatus(LPC_WWDT_T *pWWDT) -{ - return pWWDT->MOD; -} - -/** - * @brief Clear WWDT interrupt status flags - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @param status : Or'ed value of status flag(s) that you want to clear, should be: - * - WWDT_WDMOD_WDTOF: Clear watchdog timeout flag - * - WWDT_WDMOD_WDINT: Clear watchdog warning flag - * @return None - */ -void Chip_WWDT_ClearStatusFlag(LPC_WWDT_T *pWWDT, uint32_t status); - -/** - * @brief Get the current value of WDT - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @return current value of WDT - */ -STATIC INLINE uint32_t Chip_WWDT_GetCurrentCount(LPC_WWDT_T *pWWDT) -{ - return pWWDT->TV; -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __WWDT_5410X_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/error.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/error.h deleted file mode 100644 index 517e7a4956f..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/error.h +++ /dev/null @@ -1,272 +0,0 @@ -/* - * @brief Error code returned by Boot ROM drivers/library functions - * - * This file contains unified error codes to be used across driver, - * middleware, applications, hal and demo software. - * - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __LPC_ERROR_H__ -#define __LPC_ERROR_H__ - -/** Error code returned by Boot ROM drivers/library functions - * - * Error codes are a 32-bit value with : - * - The 16 MSB contains the peripheral code number - * - The 16 LSB contains an error code number associated to that peripheral - * - */ -typedef enum -{ - /**\b 0x00000000*/ LPC_OK=0, /**< enum value returned on Success */ - /**\b 0xFFFFFFFF*/ ERR_FAILED = -1, /**< enum value returned on general failure */ - /**\b 0xFFFFFFFE*/ ERR_TIME_OUT = -2, /**< enum value returned on general timeout */ - /**\b 0xFFFFFFFD*/ ERR_BUSY = -3, /**< enum value returned when resource is busy */ - - /* ISP related errors */ - ERR_ISP_BASE = 0x00000000, - /*0x00000001*/ ERR_ISP_INVALID_COMMAND = ERR_ISP_BASE + 1, - /*0x00000002*/ ERR_ISP_SRC_ADDR_ERROR, /* Source address not on word boundary */ - /*0x00000003*/ ERR_ISP_DST_ADDR_ERROR, /* Destination address not on word or 256 byte boundary */ - /*0x00000004*/ ERR_ISP_SRC_ADDR_NOT_MAPPED, - /*0x00000005*/ ERR_ISP_DST_ADDR_NOT_MAPPED, - /*0x00000006*/ ERR_ISP_COUNT_ERROR, /* Byte count is not multiple of 4 or is not a permitted value */ - /*0x00000007*/ ERR_ISP_INVALID_SECTOR, - /*0x00000008*/ ERR_ISP_SECTOR_NOT_BLANK, - /*0x00000009*/ ERR_ISP_SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION, - /*0x0000000A*/ ERR_ISP_COMPARE_ERROR, - /*0x0000000B*/ ERR_ISP_BUSY, /* Flash programming hardware interface is busy */ - /*0x0000000C*/ ERR_ISP_PARAM_ERROR, /* Insufficient number of parameters */ - /*0x0000000D*/ ERR_ISP_ADDR_ERROR, /* Address not on word boundary */ - /*0x0000000E*/ ERR_ISP_ADDR_NOT_MAPPED, - /*0x0000000F*/ ERR_ISP_CMD_LOCKED, /* Command is locked */ - /*0x00000010*/ ERR_ISP_INVALID_CODE, /* Unlock code is invalid */ - /*0x00000011*/ ERR_ISP_INVALID_BAUD_RATE, - /*0x00000012*/ ERR_ISP_INVALID_STOP_BIT, - /*0x00000013*/ ERR_ISP_CODE_READ_PROTECTION_ENABLED, - /*0x00000014*/ ERR_ISP_INVALID_FLASH_UNIT, - /*0x00000015*/ ERR_ISP_USER_CODE_CHECKSUM, - /*0x00000016*/ ERR_ISP_SETTING_ACTIVE_PARTITION, - /*0x00000017*/ ERR_ISP_IRC_NO_POWER, - /*0x00000018*/ ERR_ISP_FLASH_NO_POWER, - /*0x00000019*/ ERR_ISP_EEPROM_NO_POWER, - /*0x0000001A*/ ERR_ISP_EEPROM_NO_CLOCK, - /*0x0000001B*/ ERR_ISP_FLASH_NO_CLOCK, - /*0x0000001C*/ ERR_ISP_REINVOKE_ISP_CONFIG, - - /* ROM API related errors */ - ERR_API_BASE = 0x00010000, - /**\b 0x00010001*/ ERR_API_INVALID_PARAMS = ERR_API_BASE + 1, /**< Invalid parameters*/ - /**\b 0x00010002*/ ERR_API_INVALID_PARAM1, /**< PARAM1 is invalid */ - /**\b 0x00010003*/ ERR_API_INVALID_PARAM2, /**< PARAM2 is invalid */ - /**\b 0x00010004*/ ERR_API_INVALID_PARAM3, /**< PARAM3 is invalid */ - /**\b 0x00010005*/ ERR_API_MOD_INIT, /**< API is called before module init */ - - /* SPIFI API related errors */ - ERR_SPIFI_BASE = 0x00020000, - /*0x00020001*/ ERR_SPIFI_DEVICE_ERROR =ERR_SPIFI_BASE+1, - /*0x00020002*/ ERR_SPIFI_INTERNAL_ERROR, - /*0x00020003*/ ERR_SPIFI_TIMEOUT, - /*0x00020004*/ ERR_SPIFI_OPERAND_ERROR, - /*0x00020005*/ ERR_SPIFI_STATUS_PROBLEM, - /*0x00020006*/ ERR_SPIFI_UNKNOWN_EXT, - /*0x00020007*/ ERR_SPIFI_UNKNOWN_ID, - /*0x00020008*/ ERR_SPIFI_UNKNOWN_TYPE, - /*0x00020009*/ ERR_SPIFI_UNKNOWN_MFG, - /*0x0002000A*/ ERR_SPIFI_NO_DEVICE, - /*0x0002000B*/ ERR_SPIFI_ERASE_NEEDED, - - SEC_AES_NO_ERROR=0, - /* Security API related errors */ - ERR_SEC_AES_BASE = 0x00030000, - /*0x00030001*/ ERR_SEC_AES_WRONG_CMD=ERR_SEC_AES_BASE+1, - /*0x00030002*/ ERR_SEC_AES_NOT_SUPPORTED, - /*0x00030003*/ ERR_SEC_AES_KEY_ALREADY_PROGRAMMED, - /*0x00030004*/ ERR_SEC_AES_DMA_CHANNEL_CFG, - /*0x00030005*/ ERR_SEC_AES_DMA_MUX_CFG, - /*0x00030006*/ SEC_AES_DMA_BUSY, - - /* USB device stack related errors */ - ERR_USBD_BASE = 0x00040000, - /**\b 0x00040001*/ ERR_USBD_INVALID_REQ = ERR_USBD_BASE + 1, /**< invalid request */ - /**\b 0x00040002*/ ERR_USBD_UNHANDLED, /**< Callback did not process the event */ - /**\b 0x00040003*/ ERR_USBD_STALL, /**< Stall the endpoint on which the call back is called */ - /**\b 0x00040004*/ ERR_USBD_SEND_ZLP, /**< Send ZLP packet on the endpoint on which the call back is called */ - /**\b 0x00040005*/ ERR_USBD_SEND_DATA, /**< Send data packet on the endpoint on which the call back is called */ - /**\b 0x00040006*/ ERR_USBD_BAD_DESC, /**< Bad descriptor*/ - /**\b 0x00040007*/ ERR_USBD_BAD_CFG_DESC,/**< Bad config descriptor*/ - /**\b 0x00040008*/ ERR_USBD_BAD_INTF_DESC,/**< Bad interface descriptor*/ - /**\b 0x00040009*/ ERR_USBD_BAD_EP_DESC,/**< Bad endpoint descriptor*/ - /**\b 0x0004000a*/ ERR_USBD_BAD_MEM_BUF, /**< Bad alignment of buffer passed. */ - /**\b 0x0004000b*/ ERR_USBD_TOO_MANY_CLASS_HDLR, /**< Too many class handlers. */ - - /* CGU related errors */ - ERR_CGU_BASE = 0x00050000, - /*0x00050001*/ ERR_CGU_NOT_IMPL=ERR_CGU_BASE+1, - /*0x00050002*/ ERR_CGU_INVALID_PARAM, - /*0x00050003*/ ERR_CGU_INVALID_SLICE, - /*0x00050004*/ ERR_CGU_OUTPUT_GEN, - /*0x00050005*/ ERR_CGU_DIV_SRC, - /*0x00050006*/ ERR_CGU_DIV_VAL, - /*0x00050007*/ ERR_CGU_SRC, - - /* I2C related errors */ - ERR_I2C_BASE = 0x00060000, - /*0x00060000*/ ERR_I2C_BUSY = ERR_I2C_BASE, - /*0x00060001*/ ERR_I2C_NAK, - /*0x00060002*/ ERR_I2C_BUFFER_OVERFLOW, - /*0x00060003*/ ERR_I2C_BYTE_COUNT_ERR, - /*0x00060004*/ ERR_I2C_LOSS_OF_ARBRITRATION, - /*0x00060005*/ ERR_I2C_SLAVE_NOT_ADDRESSED, - /*0x00060006*/ ERR_I2C_LOSS_OF_ARBRITRATION_NAK_BIT, - /*0x00060007*/ ERR_I2C_GENERAL_FAILURE, - /*0x00060008*/ ERR_I2C_REGS_SET_TO_DEFAULT, - /*0x00060009*/ ERR_I2C_TIMEOUT, - /*0x0006000A*/ ERR_I2C_BUFFER_UNDERFLOW, - /*0x0006000B*/ ERR_I2C_PARAM, - - /* OTP related errors */ - ERR_OTP_BASE = 0x00070000, - /*0x00070001*/ ERR_OTP_WR_ENABLE_INVALID = ERR_OTP_BASE+1, - /*0x00070002*/ ERR_OTP_SOME_BITS_ALREADY_PROGRAMMED, - /*0x00070003*/ ERR_OTP_ALL_DATA_OR_MASK_ZERO, - /*0x00070004*/ ERR_OTP_WRITE_ACCESS_LOCKED, - /*0x00070005*/ ERR_OTP_READ_DATA_MISMATCH, - /*0x00070006*/ ERR_OTP_USB_ID_ENABLED, - /*0x00070007*/ ERR_OTP_ETH_MAC_ENABLED, - /*0x00070008*/ ERR_OTP_AES_KEYS_ENABLED, - /*0x00070009*/ ERR_OTP_ILLEGAL_BANK, - - /* UART related errors */ - ERR_UART_BASE = 0x00080000, - /*0x00080001*/ ERR_UART_RXD_BUSY = ERR_UART_BASE+1, //UART rxd is busy - /*0x00080002*/ ERR_UART_TXD_BUSY, //UART txd is busy - /*0x00080003*/ ERR_UART_OVERRUN_FRAME_PARITY_NOISE, //overrun err, frame err, parity err, RxNoise err - /*0x00080004*/ ERR_UART_UNDERRUN, //underrun err - /*0x00080005*/ ERR_UART_PARAM, //parameter is error - /*0x00080006*/ ERR_UART_BAUDRATE, //baudrate setting is error - - /* CAN related errors */ - ERR_CAN_BASE = 0x00090000, - /*0x00090001*/ ERR_CAN_BAD_MEM_BUF = ERR_CAN_BASE+1, - /*0x00090002*/ ERR_CAN_INIT_FAIL, - /*0x00090003*/ ERR_CANOPEN_INIT_FAIL, - - /* SPIFI Lite API related errors */ - ERR_SPIFI_LITE_BASE = 0x000A0000, - /*0x000A0001*/ ERR_SPIFI_LITE_INVALID_ARGUMENTS = ERR_SPIFI_LITE_BASE+1, - /*0x000A0002*/ ERR_SPIFI_LITE_BUSY, - /*0x000A0003*/ ERR_SPIFI_LITE_MEMORY_MODE_ON, - /*0x000A0004*/ ERR_SPIFI_LITE_MEMORY_MODE_OFF, - /*0x000A0005*/ ERR_SPIFI_LITE_IN_DMA, - /*0x000A0006*/ ERR_SPIFI_LITE_NOT_IN_DMA, - /*0x000A0100*/ PENDING_SPIFI_LITE, - - /* CLK related errors */ - ERR_CLK_BASE = 0x000B0000, - /*0x000B0001*/ ERR_CLK_NOT_IMPL=ERR_CLK_BASE+1, - /*0x000B0002*/ ERR_CLK_INVALID_PARAM, - /*0x000B0003*/ ERR_CLK_INVALID_SLICE, - /*0x000B0004*/ ERR_CLK_OUTPUT_GEN, - /*0x000B0005*/ ERR_CLK_DIV_SRC, - /*0x000B0006*/ ERR_CLK_DIV_VAL, - /*0x000B0007*/ ERR_CLK_SRC, - /*0x000B0008*/ ERR_CLK_PLL_FIN_TOO_SMALL, - /*0x000B0009*/ ERR_CLK_PLL_FIN_TOO_LARGE, - /*0x000B000A*/ ERR_CLK_PLL_FOUT_TOO_SMALL, - /*0x000B000B*/ ERR_CLK_PLL_FOUT_TOO_LARGE, - /*0x000B000C*/ ERR_CLK_PLL_NO_SOLUTION, - /*0x000B000D*/ ERR_CLK_PLL_MIN_PCT, - /*0x000B000E*/ ERR_CLK_PLL_MAX_PCT, - /*0x000B000F*/ ERR_CLK_OSC_FREQ, - /*0x000B0010*/ ERR_CLK_CFG, - /*0x000B0011*/ ERR_CLK_TIMEOUT, - /*0x000B0012*/ ERR_CLK_BASE_OFF, - /*0x000B0013*/ ERR_CLK_OFF_DEADLOCK, - - /*Power API*/ - ERR_PWR_BASE = 0x000C0000, - /*0x000C0001*/ PWR_ERROR_ILLEGAL_MODE=ERR_PWR_BASE+1, - /*0x000C0002*/ PWR_ERROR_CLOCK_FREQ_TOO_HIGH, - /*0x000C0003*/ PWR_ERROR_INVALID_STATE, - /*0x000C0004*/ PWR_ERROR_INVALID_CFG, - /*0x000C0005*/ PWR_ERROR_PVT_DETECT, - - /* DMA related errors */ - ERR_DMA_BASE = 0x000D0000, - /*0x000D0001*/ ERR_DMA_ERROR_INT=ERR_DMA_BASE+1, - /*0x000D0002*/ ERR_DMA_CHANNEL_NUMBER, - /*0x000D0003*/ ERR_DMA_CHANNEL_DISABLED, - /*0x000D0004*/ ERR_DMA_BUSY, - /*0x000D0005*/ ERR_DMA_NOT_ALIGNMENT, - /*0x000D0006*/ ERR_DMA_PING_PONG_EN, - /*0x000D0007*/ ERR_DMA_CHANNEL_VALID_PENDING, - /*0x000D0008*/ ERR_DMA_PARAM, - /*0x000D0009*/ ERR_DMA_QUEUE_EMPTY, - /*0x000D000A*/ ERR_DMA_GENERAL, - - /* SPI related errors */ - ERR_SPI_BASE = 0x000E0000, - /*0x000E0000*/ ERR_SPI_BUSY=ERR_SPI_BASE, - /*0x000E0001*/ ERR_SPI_RXOVERRUN, - /*0x000E0002*/ ERR_SPI_TXUNDERRUN, - /*0x000E0003*/ ERR_SPI_SELNASSERT, - /*0x000E0004*/ ERR_SPI_SELNDEASSERT, - /*0x000E0005*/ ERR_SPI_CLKSTALL, - /*0x000E0006*/ ERR_SPI_PARAM, - /*0x000E0007*/ ERR_SPI_INVALID_LENGTH, - - /* ADC related errors */ - ERR_ADC_BASE = 0x000F0000, - /*0x000F0001*/ ERR_ADC_OVERRUN=ERR_ADC_BASE+1, - /*0x000F0002*/ ERR_ADC_INVALID_CHANNEL, - /*0x000F0003*/ ERR_ADC_INVALID_SEQUENCE, - /*0x000F0004*/ ERR_ADC_INVALID_SETUP, - /*0x000F0005*/ ERR_ADC_PARAM, - /*0x000F0006*/ ERR_ADC_INVALID_LENGTH, - /*0x000F0007*/ ERR_ADC_NO_POWER, - - /* Debugger Mailbox related errors */ - ERR_DM_BASE = 0x00100000, - /*0x00100001*/ ERR_DM_NOT_ENTERED=ERR_DM_BASE+1, - /*0x00100002*/ ERR_DM_UNKNOWN_CMD, - /*0x00100003*/ ERR_DM_COMM_FAIL - -} ErrorCode_t; - -#ifndef offsetof -#define offsetof(s, m) (int) &(((s *) 0)->m) -#endif - -#define COMPILE_TIME_ASSERT(pred) switch (0) { \ - case 0: \ - case pred:; } - -#endif /* __LPC_ERROR_H__ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/fpu_init.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/fpu_init.c deleted file mode 100644 index 88125dda5e5..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/fpu_init.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * @brief FPU init code - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#if defined(CORE_M4) - -#include "sys_config.h" -#include "cmsis.h" -#include "stdint.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -#define LPC_CPACR 0xE000ED88 - -#define SCB_MVFR0 0xE000EF40 -#define SCB_MVFR0_RESET 0x10110021 - -#define SCB_MVFR1 0xE000EF44 -#define SCB_MVFR1_RESET 0x11000011 - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Early initialization of the FPU */ -void fpuInit(void) -{ -#if __FPU_PRESENT != 0 - // from arm trm manual: - // ; CPACR is located at address 0xE000ED88 - // LDR.W R0, =0xE000ED88 - // ; Read CPACR - // LDR R1, [R0] - // ; Set bits 20-23 to enable CP10 and CP11 coprocessors - // ORR R1, R1, #(0xF << 20) - // ; Write back the modified value to the CPACR - // STR R1, [R0] - - volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR; - volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0; - volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1; - volatile uint32_t Cpacr; - volatile uint32_t Mvfr0; - volatile uint32_t Mvfr1; - char vfpPresent = 0; - - Mvfr0 = *regMvfr0; - Mvfr1 = *regMvfr1; - - vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1)); - - if (vfpPresent) { - Cpacr = *regCpacr; - Cpacr |= (0xF << 20); - *regCpacr = Cpacr; // enable CP10 and CP11 for full access - } -#endif /* __FPU_PRESENT != 0 */ -} - -#endif /* defined(CORE_M4 */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/fpu_init.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/fpu_init.h deleted file mode 100644 index 86e71c89875..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/fpu_init.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * @brief FPU init code - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __FPU_INIT_H_ -#define __FPU_INIT_H_ - -/** - * @defgroup CHIP_FPU_CMX CHIP: FPU initialization - * @ingroup CHIP_Common - * Cortex FPU initialization - * @{ - */ - -/** - * @brief Early initialization of the FPU - * @return Nothing - */ -void fpuInit(void); - -/** - * @} - */ - -#endif /* __FPU_INIT_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/iap.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/iap.c deleted file mode 100644 index 76f72a2f59b..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/iap.c +++ /dev/null @@ -1,175 +0,0 @@ -/* - * @brief Common FLASH support functions - * - * @note - * Copyright(C) NXP Semiconductors, 2013 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Prepare sector for write operation */ -uint8_t Chip_IAP_PreSectorForReadWrite(uint32_t strSector, uint32_t endSector) -{ - uint32_t command[5], result[4]; - - command[0] = IAP_PREWRRITE_CMD; - command[1] = strSector; - command[2] = endSector; - iap_entry(command, result); - - return result[0]; -} - -/* Copy RAM to flash */ -uint8_t Chip_IAP_CopyRamToFlash(uint32_t dstAdd, uint32_t *srcAdd, uint32_t byteswrt) -{ - uint32_t command[5], result[4]; - - command[0] = IAP_WRISECTOR_CMD; - command[1] = dstAdd; - command[2] = (uint32_t) srcAdd; - command[3] = byteswrt; - command[4] = SystemCoreClock / 1000; - iap_entry(command, result); - - return result[0]; -} - -/* Erase sector */ -uint8_t Chip_IAP_EraseSector(uint32_t strSector, uint32_t endSector) -{ - uint32_t command[5], result[4]; - - command[0] = IAP_ERSSECTOR_CMD; - command[1] = strSector; - command[2] = endSector; - command[3] = SystemCoreClock / 1000; - iap_entry(command, result); - - return result[0]; -} - -/* Blank check sector */ -uint8_t Chip_IAP_BlankCheckSector(uint32_t strSector, uint32_t endSector) -{ - uint32_t command[5], result[4]; - - command[0] = IAP_BLANK_CHECK_SECTOR_CMD; - command[1] = strSector; - command[2] = endSector; - iap_entry(command, result); - - return result[0]; -} - -/* Read part identification number */ -uint32_t Chip_IAP_ReadPID() -{ - uint32_t command[5], result[4]; - - command[0] = IAP_REPID_CMD; - iap_entry(command, result); - - return result[1]; -} - -/* Read boot code version number */ -uint8_t Chip_IAP_ReadBootCode() -{ - uint32_t command[5], result[4]; - - command[0] = IAP_READ_BOOT_CODE_CMD; - iap_entry(command, result); - - return result[0]; -} - -/* IAP compare */ -uint8_t Chip_IAP_Compare(uint32_t dstAdd, uint32_t srcAdd, uint32_t bytescmp) -{ - uint32_t command[5], result[4]; - - command[0] = IAP_COMPARE_CMD; - command[1] = dstAdd; - command[2] = srcAdd; - command[3] = bytescmp; - iap_entry(command, result); - - return result[0]; -} - -/* Reinvoke ISP */ -uint8_t Chip_IAP_ReinvokeISP() -{ - uint32_t command[5], result[4]; - - command[0] = IAP_REINVOKE_ISP_CMD; - iap_entry(command, result); - - return result[0]; -} - -/* Read the unique ID */ -uint32_t Chip_IAP_ReadUID() -{ - uint32_t command[5], result[4]; - - command[0] = IAP_READ_UID_CMD; - iap_entry(command, result); - - return result[1]; -} - -/* Erase page */ -uint8_t Chip_IAP_ErasePage(uint32_t strPage, uint32_t endPage) -{ - uint32_t command[5], result[4]; - - command[0] = IAP_ERASE_PAGE_CMD; - command[1] = strPage; - command[2] = endPage; - command[3] = SystemCoreClock / 1000; - iap_entry(command, result); - - return result[0]; -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/iap.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/iap.h deleted file mode 100644 index 78b167f1e8b..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/iap.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * @brief Common IAP support functions - * - * @note - * Copyright(C) NXP Semiconductors, 2013 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __IAP_H_ -#define __IAP_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup COMMON_IAP CHIP: Common Chip ISP/IAP commands and return codes - * @ingroup CHIP_Common - * @{ - */ - -/* IAP command definitions */ -#define IAP_PREWRRITE_CMD 50 /*!< Prepare sector for write operation command */ -#define IAP_WRISECTOR_CMD 51 /*!< Write Sector command */ -#define IAP_ERSSECTOR_CMD 52 /*!< Erase Sector command */ -#define IAP_BLANK_CHECK_SECTOR_CMD 53 /*!< Blank check sector */ -#define IAP_REPID_CMD 54 /*!< Read PartID command */ -#define IAP_READ_BOOT_CODE_CMD 55 /*!< Read Boot code version */ -#define IAP_COMPARE_CMD 56 /*!< Compare two RAM address locations */ -#define IAP_REINVOKE_ISP_CMD 57 /*!< Reinvoke ISP */ -#define IAP_READ_UID_CMD 58 /*!< Read UID */ -#define IAP_ERASE_PAGE_CMD 59 /*!< Erase page */ -#define IAP_EEPROM_WRITE 61 /*!< EEPROM Write command */ -#define IAP_EEPROM_READ 62 /*!< EEPROM READ command */ - -/* IAP response definitions */ -#define IAP_CMD_SUCCESS 0 /*!< Command is executed successfully */ -#define IAP_INVALID_COMMAND 1 /*!< Invalid command */ -#define IAP_SRC_ADDR_ERROR 2 /*!< Source address is not on word boundary */ -#define IAP_DST_ADDR_ERROR 3 /*!< Destination address is not on a correct boundary */ -#define IAP_SRC_ADDR_NOT_MAPPED 4 /*!< Source address is not mapped in the memory map */ -#define IAP_DST_ADDR_NOT_MAPPED 5 /*!< Destination address is not mapped in the memory map */ -#define IAP_COUNT_ERROR 6 /*!< Byte count is not multiple of 4 or is not a permitted value */ -#define IAP_INVALID_SECTOR 7 /*!< Sector number is invalid or end sector number is greater than start sector number */ -#define IAP_SECTOR_NOT_BLANK 8 /*!< Sector is not blank */ -#define IAP_SECTOR_NOT_PREPARED 9 /*!< Command to prepare sector for write operation was not executed */ -#define IAP_COMPARE_ERROR 10 /*!< Source and destination data not equal */ -#define IAP_BUSY 11 /*!< Flash programming hardware interface is busy */ -#define IAP_PARAM_ERROR 12 /*!< nsufficient number of parameters or invalid parameter */ -#define IAP_ADDR_ERROR 13 /*!< Address is not on word boundary */ -#define IAP_ADDR_NOT_MAPPED 14 /*!< Address is not mapped in the memory map */ -#define IAP_CMD_LOCKED 15 /*!< Command is locked */ -#define IAP_INVALID_CODE 16 /*!< Unlock code is invalid */ -#define IAP_INVALID_BAUD_RATE 17 /*!< Invalid baud rate setting */ -#define IAP_INVALID_STOP_BIT 18 /*!< Invalid stop bit setting */ -#define IAP_CRP_ENABLED 19 /*!< Code read protection enabled */ - -/* IAP_ENTRY API function type */ -typedef void (*IAP_ENTRY_T)(uint32_t[5], uint32_t[4]); - -/** - * @brief Prepare sector for write operation - * @param strSector : Start sector number - * @param endSector : End sector number - * @return Status code to indicate the command is executed successfully or not - * @note This command must be executed before executing "Copy RAM to flash" - * or "Erase Sector" command. - * The end sector must be greater than or equal to start sector number - */ -uint8_t Chip_IAP_PreSectorForReadWrite(uint32_t strSector, uint32_t endSector); - -/** - * @brief Copy RAM to flash - * @param dstAdd : Destination flash address where data bytes are to be written - * @param srcAdd : Source flash address where data bytes are to be read - * @param byteswrt : Number of bytes to be written - * @return Status code to indicate the command is executed successfully or not - * @note The addresses should be a 256 byte boundary and the number of bytes - * should be 256 | 512 | 1024 | 4096 - */ -uint8_t Chip_IAP_CopyRamToFlash(uint32_t dstAdd, uint32_t *srcAdd, uint32_t byteswrt); - -/** - * @brief Erase sector - * @param strSector : Start sector number - * @param endSector : End sector number - * @return Status code to indicate the command is executed successfully or not - * @note The end sector must be greater than or equal to start sector number - */ -uint8_t Chip_IAP_EraseSector(uint32_t strSector, uint32_t endSector); - -/** - * @brief Blank check a sector or multiples sector of on-chip flash memory - * @param strSector : Start sector number - * @param endSector : End sector number - * @return Offset of the first non blank word location if the status code is SECTOR_NOT_BLANK - * @note The end sector must be greater than or equal to start sector number - */ -// FIXME - There are two return value (result[0] & result[1] -// Result0:Offset of the first non blank word location if the Status Code is -// SECTOR_NOT_BLANK. -// Result1:Contents of non blank word location. -uint8_t Chip_IAP_BlankCheckSector(uint32_t strSector, uint32_t endSector); - -/** - * @brief Read part identification number - * @return Part identification number - */ -uint32_t Chip_IAP_ReadPID(void); - -/** - * @brief Read boot code version number - * @return Boot code version number - */ -uint8_t Chip_IAP_ReadBootCode(void); - -/** - * @brief Compare the memory contents at two locations - * @param dstAdd : Destination of the RAM address of data bytes to be compared - * @param srcAdd : Source of the RAM address of data bytes to be compared - * @param bytescmp : Number of bytes to be compared - * @return Offset of the first mismatch of the status code is COMPARE_ERROR - * @note The addresses should be a word boundary and number of bytes should be - * a multiply of 4 - */ -uint8_t Chip_IAP_Compare(uint32_t dstAdd, uint32_t srcAdd, uint32_t bytescmp); - -/** - * @brief IAP reinvoke ISP to invoke the bootloader in ISP mode - * @return none - */ -uint8_t Chip_IAP_ReinvokeISP(void); - -/** - * @brief Read the unique ID - * @return Status code to indicate the command is executed successfully or not - */ -uint32_t Chip_IAP_ReadUID(void); - -/** - * @brief Erase a page or multiple papers of on-chip flash memory - * @param strPage : Start page number - * @param endPage : End page number - * @return Status code to indicate the command is executed successfully or not - * @note The page number must be greater than or equal to start page number - */ -// FIXME - There are four return value -// Result0:The first 32-bit word (at the lowest address) -// Result1:The second 32-bit word. -// Result2:The third 32-bit word. -// Result3:The fourth 32-bit word. -uint8_t Chip_IAP_ErasePage(uint32_t strPage, uint32_t endPage); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __IAP_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/lpc_types.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/lpc_types.h deleted file mode 100644 index 14c7b605009..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/lpc_types.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * @brief Common types used in LPC functions - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __LPC_TYPES_H_ -#define __LPC_TYPES_H_ - -#include -#include - -/** @defgroup LPC_Types CHIP: LPC Common Types - * @ingroup CHIP_Common - * @{ - */ - -/** @defgroup LPC_Types_Public_Types LPC Public Types - * @{ - */ - -/** - * @brief Boolean Type definition - */ -typedef enum {FALSE = 0, TRUE = !FALSE} Bool; - -/** - * @brief Boolean Type definition - */ -#if !defined(__cplusplus) -// typedef enum {false = 0, true = !false} bool; -#endif - -/** - * @brief Flag Status and Interrupt Flag Status type definition - */ -typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState; -#define PARAM_SETSTATE(State) ((State == RESET) || (State == SET)) - -/** - * @brief Functional State Definition - */ -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define PARAM_FUNCTIONALSTATE(State) ((State == DISABLE) || (State == ENABLE)) - -/** - * @ Status type definition - */ -typedef enum {ERROR = 0, SUCCESS = !ERROR} Status; - -/** - * Read/Write transfer type mode (Block or non-block) - */ -typedef enum { - NONE_BLOCKING = 0, /**< None Blocking type */ - BLOCKING, /**< Blocking type */ -} TRANSFER_BLOCK_T; - -/** Pointer to Function returning Void (any number of parameters) */ -typedef void (*PFV)(); - -/** Pointer to Function returning int32_t (any number of parameters) */ -typedef int32_t (*PFI)(); - -/** - * @} - */ - -/** @defgroup LPC_Types_Public_Macros LPC Public Macros - * @{ - */ - -/* _BIT(n) sets the bit at position "n" - * _BIT(n) is intended to be used in "OR" and "AND" expressions: - * e.g., "(_BIT(3) | _BIT(7))". - */ -#undef _BIT -/* Set bit macro */ -#define _BIT(n) (1 << (n)) - -/* _SBF(f,v) sets the bit field starting at position "f" to value "v". - * _SBF(f,v) is intended to be used in "OR" and "AND" expressions: - * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)" - */ -#undef _SBF -/* Set bit field macro */ -#define _SBF(f, v) ((v) << (f)) - -/* _BITMASK constructs a symbol with 'field_width' least significant - * bits set. - * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF - * The symbol is intended to be used to limit the bit field width - * thusly: - * = (any_expression) & _BITMASK(x), where 0 < x <= 32. - * If "any_expression" results in a value that is larger than can be - * contained in 'x' bits, the bits above 'x - 1' are masked off. When - * used with the _SBF example above, the example would be written: - * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16)) - * This ensures that the value written to a_reg is no wider than - * 16 bits, and makes the code easier to read and understand. - */ -#undef _BITMASK -/* Bitmask creation macro */ -#define _BITMASK(field_width) ( _BIT(field_width) - 1) - -/* NULL pointer */ -#ifndef NULL -#define NULL ((void *) 0) -#endif - -/* Number of elements in an array */ -#define NELEMENTS(array) (sizeof(array) / sizeof(array[0])) - -/* Static data/function define */ -#define STATIC static -/* External data/function define */ -#define EXTERN extern - -#if !defined(MAX) -#define MAX(a, b) (((a) > (b)) ? (a) : (b)) -#endif -#if !defined(MIN) -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) -#endif - -/** - * @} - */ - -/* Old Type Definition compatibility */ -/** @addtogroup LPC_Types_Public_Types - * @{ - */ - -/** LPC type for character type */ -typedef char CHAR; - -/** LPC type for 8 bit unsigned value */ -typedef uint8_t UNS_8; - -/** LPC type for 8 bit signed value */ -typedef int8_t INT_8; - -/** LPC type for 16 bit unsigned value */ -typedef uint16_t UNS_16; - -/** LPC type for 16 bit signed value */ -typedef int16_t INT_16; - -/** LPC type for 32 bit unsigned value */ -typedef uint32_t UNS_32; - -/** LPC type for 32 bit signed value */ -typedef int32_t INT_32; - -/** LPC type for 64 bit signed value */ -typedef int64_t INT_64; - -/** LPC type for 64 bit unsigned value */ -typedef uint64_t UNS_64; - -#ifdef __CODE_RED -#define BOOL_32 bool -#define BOOL_16 bool -#define BOOL_8 bool -#else -/** 32 bit boolean type */ -typedef bool BOOL_32; - -/** 16 bit boolean type */ -typedef bool BOOL_16; - -/** 8 bit boolean type */ -typedef bool BOOL_8; -#endif - -#ifdef __CC_ARM -#define INLINE __inline -#else -#define INLINE inline -#endif - -/** - * @} - */ - -/** - * @} - */ - -#endif /* __LPC_TYPES_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/packing.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/packing.h deleted file mode 100644 index c2b9631bb32..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/packing.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * @brief Packing macros - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __PACKING_H_ -#define __PACKING_H_ - -#define PRE_PACK /* Nothing */ -#define POST_PACK /* Nothing */ -#define ALIGNED(n) /* Nothing */ - -#endif /* __PACKING_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/ring_buffer.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/ring_buffer.c deleted file mode 100644 index 47a0c34f95f..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/ring_buffer.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * @brief Common ring buffer support functions - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include -#include "ring_buffer.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -#define RB_INDH(rb) ((rb)->head & ((rb)->count - 1)) -#define RB_INDT(rb) ((rb)->tail & ((rb)->count - 1)) - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Initialize ring buffer */ -int RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count) -{ - RingBuff->data = buffer; - RingBuff->count = count; - RingBuff->itemSz = itemSize; - RingBuff->head = RingBuff->tail = 0; - - return 1; -} - -/* Insert a single item into Ring Buffer */ -int RingBuffer_Insert(RINGBUFF_T *RingBuff, const void *data) -{ - uint8_t *ptr = RingBuff->data; - - /* We cannot insert when queue is full */ - if (RingBuffer_IsFull(RingBuff)) - return 0; - - ptr += RB_INDH(RingBuff) * RingBuff->itemSz; - memcpy(ptr, data, RingBuff->itemSz); - RingBuff->head++; - - return 1; -} - -/* Insert multiple items into Ring Buffer */ -int RingBuffer_InsertMult(RINGBUFF_T *RingBuff, const void *data, int num) -{ - uint8_t *ptr = RingBuff->data; - int cnt1, cnt2; - - /* We cannot insert when queue is full */ - if (RingBuffer_IsFull(RingBuff)) - return 0; - - /* Calculate the segment lengths */ - cnt1 = cnt2 = RingBuffer_GetFree(RingBuff); - if (RB_INDH(RingBuff) + cnt1 >= RingBuff->count) - cnt1 = RingBuff->count - RB_INDH(RingBuff); - cnt2 -= cnt1; - - cnt1 = MIN(cnt1, num); - num -= cnt1; - - cnt2 = MIN(cnt2, num); - num -= cnt2; - - /* Write segment 1 */ - ptr += RB_INDH(RingBuff) * RingBuff->itemSz; - memcpy(ptr, data, cnt1 * RingBuff->itemSz); - RingBuff->head += cnt1; - - /* Write segment 2 */ - ptr = (uint8_t *) RingBuff->data + RB_INDH(RingBuff) * RingBuff->itemSz; - data = (const uint8_t *) data + cnt1 * RingBuff->itemSz; - memcpy(ptr, data, cnt2 * RingBuff->itemSz); - RingBuff->head += cnt2; - - return cnt1 + cnt2; -} - -/* Pop single item from Ring Buffer */ -int RingBuffer_Pop(RINGBUFF_T *RingBuff, void *data) -{ - uint8_t *ptr = RingBuff->data; - - /* We cannot pop when queue is empty */ - if (RingBuffer_IsEmpty(RingBuff)) - return 0; - - ptr += RB_INDT(RingBuff) * RingBuff->itemSz; - memcpy(data, ptr, RingBuff->itemSz); - RingBuff->tail++; - - return 1; -} - -/* Pop multiple items from Ring buffer */ -int RingBuffer_PopMult(RINGBUFF_T *RingBuff, void *data, int num) -{ - uint8_t *ptr = RingBuff->data; - int cnt1, cnt2; - - /* We cannot insert when queue is empty */ - if (RingBuffer_IsEmpty(RingBuff)) - return 0; - - /* Calculate the segment lengths */ - cnt1 = cnt2 = RingBuffer_GetCount(RingBuff); - if (RB_INDT(RingBuff) + cnt1 >= RingBuff->count) - cnt1 = RingBuff->count - RB_INDT(RingBuff); - cnt2 -= cnt1; - - cnt1 = MIN(cnt1, num); - num -= cnt1; - - cnt2 = MIN(cnt2, num); - num -= cnt2; - - /* Write segment 1 */ - ptr += RB_INDT(RingBuff) * RingBuff->itemSz; - memcpy(data, ptr, cnt1 * RingBuff->itemSz); - RingBuff->tail += cnt1; - - /* Write segment 2 */ - ptr = (uint8_t *) RingBuff->data + RB_INDT(RingBuff) * RingBuff->itemSz; - data = (uint8_t *) data + cnt1 * RingBuff->itemSz; - memcpy(data, ptr, cnt2 * RingBuff->itemSz); - RingBuff->tail += cnt2; - - return cnt1 + cnt2; -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/ring_buffer.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/ring_buffer.h deleted file mode 100644 index 8c205fd3a8a..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/ring_buffer.h +++ /dev/null @@ -1,188 +0,0 @@ -/* - * @brief Common ring buffer support functions - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __RING_BUFFER_H_ -#define __RING_BUFFER_H_ - -#include "lpc_types.h" - -/** @defgroup Ring_Buffer CHIP: Simple ring buffer implementation - * @ingroup CHIP_Common - * @{ - */ - -/** - * @brief Ring buffer structure - */ -typedef struct { - void *data; - int count; - int itemSz; - uint32_t head; - uint32_t tail; -} RINGBUFF_T; - -/** - * @def RB_VHEAD(rb) - * volatile typecasted head index - */ -#define RB_VHEAD(rb) (*(volatile uint32_t *) &(rb)->head) - -/** - * @def RB_VTAIL(rb) - * volatile typecasted tail index - */ -#define RB_VTAIL(rb) (*(volatile uint32_t *) &(rb)->tail) - -/** - * @brief Initialize ring buffer - * @param RingBuff : Pointer to ring buffer to initialize - * @param buffer : Pointer to buffer to associate with RingBuff - * @param itemSize : Size of each buffer item size - * @param count : Size of ring buffer - * @note Memory pointed by @a buffer must have correct alignment of - * @a itemSize, and @a count must be a power of 2 and must at - * least be 2 or greater. - * @return Nothing - */ -int RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count); - -/** - * @brief Resets the ring buffer to empty - * @param RingBuff : Pointer to ring buffer - * @return Nothing - */ -STATIC INLINE void RingBuffer_Flush(RINGBUFF_T *RingBuff) -{ - RingBuff->head = RingBuff->tail = 0; -} - -/** - * @brief Return size the ring buffer - * @param RingBuff : Pointer to ring buffer - * @return Size of the ring buffer in bytes - */ -STATIC INLINE int RingBuffer_GetSize(RINGBUFF_T *RingBuff) -{ - return RingBuff->count; -} - -/** - * @brief Return number of items in the ring buffer - * @param RingBuff : Pointer to ring buffer - * @return Number of items in the ring buffer - */ -STATIC INLINE int RingBuffer_GetCount(RINGBUFF_T *RingBuff) -{ - return RB_VHEAD(RingBuff) - RB_VTAIL(RingBuff); -} - -/** - * @brief Return number of free items in the ring buffer - * @param RingBuff : Pointer to ring buffer - * @return Number of free items in the ring buffer - */ -STATIC INLINE int RingBuffer_GetFree(RINGBUFF_T *RingBuff) -{ - return RingBuff->count - RingBuffer_GetCount(RingBuff); -} - -/** - * @brief Return number of items in the ring buffer - * @param RingBuff : Pointer to ring buffer - * @return 1 if the ring buffer is full, otherwise 0 - */ -STATIC INLINE int RingBuffer_IsFull(RINGBUFF_T *RingBuff) -{ - return (RingBuffer_GetCount(RingBuff) >= RingBuff->count); -} - -/** - * @brief Return empty status of ring buffer - * @param RingBuff : Pointer to ring buffer - * @return 1 if the ring buffer is empty, otherwise 0 - */ -STATIC INLINE int RingBuffer_IsEmpty(RINGBUFF_T *RingBuff) -{ - return RB_VHEAD(RingBuff) == RB_VTAIL(RingBuff); -} - -/** - * @brief Insert a single item into ring buffer - * @param RingBuff : Pointer to ring buffer - * @param data : pointer to item - * @return 1 when successfully inserted, - * 0 on error (Buffer not initialized using - * RingBuffer_Init() or attempted to insert - * when buffer is full) - */ -int RingBuffer_Insert(RINGBUFF_T *RingBuff, const void *data); - -/** - * @brief Insert an array of items into ring buffer - * @param RingBuff : Pointer to ring buffer - * @param data : Pointer to first element of the item array - * @param num : Number of items in the array - * @return number of items successfully inserted, - * 0 on error (Buffer not initialized using - * RingBuffer_Init() or attempted to insert - * when buffer is full) - */ -int RingBuffer_InsertMult(RINGBUFF_T *RingBuff, const void *data, int num); - -/** - * @brief Pop an item from the ring buffer - * @param RingBuff : Pointer to ring buffer - * @param data : Pointer to memory where popped item be stored - * @return 1 when item popped successfuly onto @a data, - * 0 When error (Buffer not initialized using - * RingBuffer_Init() or attempted to pop item when - * the buffer is empty) - */ -int RingBuffer_Pop(RINGBUFF_T *RingBuff, void *data); - -/** - * @brief Pop an array of items from the ring buffer - * @param RingBuff : Pointer to ring buffer - * @param data : Pointer to memory where popped items be stored - * @param num : Max number of items array @a data can hold - * @return Number of items popped onto @a data, - * 0 on error (Buffer not initialized using RingBuffer_Init() - * or attempted to pop when the buffer is empty) - */ -int RingBuffer_PopMult(RINGBUFF_T *RingBuff, void *data, int num); - - -/** - * @} - */ - -#endif /* __RING_BUFFER_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/rtc_ut.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/rtc_ut.c deleted file mode 100644 index c998261489b..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/rtc_ut.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * @brief RTC tick to (a more) Universal Time - * Adds conversion functions to use an RTC that only provides a - * seconds capability to provide "struct tm" support. - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "rtc_ut.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -#define SECSPERMIN (60) -#define MINSPERHOUR (60) -#define SECSPERHOUR (SECSPERMIN * MINSPERHOUR) -#define HOURSPERDAY (24) -#define SECSPERDAY (SECSPERMIN * MINSPERHOUR * HOURSPERDAY) -#define DAYSPERWEEK (7) -#define MONETHSPERYEAR (12) -#define DAYSPERYEAR (365) -#define DAYSPERLEAPYEAR (366) - -/* Days per month, LY is special */ -static uint8_t daysPerMonth[2][MONETHSPERYEAR] = { - {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}, /* Normal year */ - {31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}, /* Leap year */ -}; - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/* Converts the number of days offset from the start year to real year - data accounting for leap years */ -static void GetDMLY(int dayOff, struct tm *pTime) -{ - bool YearFound = false; - int daysYear = dayOff; - int leapYear, curLeapYear, year = TM_YEAR_BASE, monthYear = 0; - bool MonthFound = false; - - /* Leap year check for less than 1 year time */ - if ((year % 4) == 0) { - curLeapYear = 1; - } - else { - curLeapYear = 0; - } - - /* Determine offset of years from days offset */ - while (YearFound == false) { - if ((year % 4) == 0) { - /* Leap year, 366 days */ - daysYear = DAYSPERLEAPYEAR; - leapYear = 1; - } - else { - /* Leap year, 365 days */ - daysYear = DAYSPERYEAR; - leapYear = 0; - } - - if (dayOff > daysYear) { - dayOff -= daysYear; - year++; - } - else { - YearFound = true; - curLeapYear = leapYear; /* In a leap year */ - } - } - - /* Save relative year and day into year */ - pTime->tm_year = year - TM_YEAR_BASE; /* Base year relative */ - pTime->tm_yday = dayOff;/* 0 relative */ - - /* Determine offset of months from days offset */ - while (MonthFound == false) { - if ((dayOff + 1) > daysPerMonth[curLeapYear][monthYear]) { - /* Next month */ - dayOff -= daysPerMonth[curLeapYear][monthYear]; - monthYear++; - } - else { - /* Month found */ - MonthFound = true; - } - } - - pTime->tm_mday = dayOff + 1;/* 1 relative */ - pTime->tm_mon = monthYear; /* 0 relative */ -} - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Converts an RTC tick time to Universal time */ -void ConvertRtcTime(uint32_t rtcTick, struct tm *pTime) -{ - int daySeconds, dayNum; - - /* Get day offset and seconds since start */ - dayNum = (int) (rtcTick / SECSPERDAY); - daySeconds = (int) (rtcTick % SECSPERDAY); - - /* Fill in secs, min, hours */ - pTime->tm_sec = daySeconds % 60; - pTime->tm_hour = daySeconds / SECSPERHOUR; - pTime->tm_min = (daySeconds - (pTime->tm_hour * SECSPERHOUR)) / SECSPERMIN; - - /* Weekday, 0 = Sunday, 6 = Saturday */ - pTime->tm_wday = (dayNum + TM_DAYOFWEEK) % DAYSPERWEEK; - - /* Get year, month, day of month, and day of year */ - GetDMLY(dayNum, pTime); - - /* Not supported in this driver */ - pTime->tm_isdst = 0; -} - -/* Converts a Universal time to RTC tick time */ -void ConvertTimeRtc(struct tm *pTime, uint32_t *rtcTick) -{ - int leapYear, year = pTime->tm_year + TM_YEAR_BASE; - uint32_t dayOff, monthOff, monthCur, rtcTicks = 0; - - /* Leap year check for less than 1 year time */ - if ((year % 4) == 0) { - leapYear = 1; - } - else { - leapYear = 0; - } - - /* Add days for each year and leap year */ - while (year > TM_YEAR_BASE) { - if ((year % 4) == 0) { - /* Leap year, 366 days */ - rtcTicks += DAYSPERLEAPYEAR * SECSPERDAY; - leapYear = 1; - } - else { - /* Leap year, 365 days */ - rtcTicks += DAYSPERYEAR * SECSPERDAY; - leapYear = 0; - } - - year--; - } - - /* Day and month are 0 relative offsets since day and month - start at 1 */ - dayOff = (uint32_t) pTime->tm_mday - 1; - monthOff = (uint32_t) pTime->tm_mon; - - /* Add in seconds for passed months */ - for (monthCur = 0; monthCur < monthOff; monthCur++) { - rtcTicks += (uint32_t) (daysPerMonth[leapYear][monthCur] * SECSPERDAY); - } - - /* Add in seconds for day offset into the current month */ - rtcTicks += (dayOff * SECSPERDAY); - - /* Add in seconds for hours, minutes, and seconds */ - rtcTicks += (uint32_t) (pTime->tm_hour * SECSPERHOUR); - rtcTicks += (uint32_t) (pTime->tm_min * SECSPERMIN); - rtcTicks += (uint32_t) pTime->tm_sec; - - *rtcTick = rtcTicks; -} diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/rtc_ut.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/rtc_ut.h deleted file mode 100644 index 9caffc2dd66..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/rtc_ut.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * @brief RTC tick to (a more) Universal Time - * Adds conversion functions to use an RTC that only provides a - * seconds capability to provide "struct tm" support. - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __RTC_UT_H_ -#define __RTC_UT_H_ - -#include "chip.h" -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup RTC_UT CHIP: RTC tick to (a more) Universal Time conversion functions - * @ingroup CHIP_Common - * This driver converts between a RTC 1-second tick value and - * a Universal time format in a structure of type 'struct tm'. - * @{ - */ - -/* Starting year and starting day of week for the driver */ -#define TM_YEAR_BASE (1900) -#define TM_DAYOFWEEK (1) - -/** - * @brief Converts a RTC tick time to Universal time - * @param rtcTick : Current RTC time value - * @param pTime : Pointer to time structure to fill - * @return Nothing - * @note When setting time, the 'tm_wday', 'tm_yday', and 'tm_isdst' - * fields are not used. - */ -void ConvertRtcTime(uint32_t rtcTick, struct tm *pTime); - -/** - * @brief Converts a Universal time to RTC tick time - * @param pTime : Pointer to time structure to use - * @param rtcTick : Pointer to RTC time value to fill - * @return Nothing - * @note When converting time, the 'tm_isdst' field is not - * populated by the conversion function. - */ -void ConvertTimeRtc(struct tm *pTime, uint32_t *rtcTick); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __RTC_UT_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/stopwatch.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/stopwatch.h deleted file mode 100644 index c298735fa2a..00000000000 --- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/stopwatch.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * @brief Common stopwatch support - * - * @note - * Copyright(C) NXP Semiconductors, 2013 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __STOPWATCH_H_ -#define __STOPWATCH_H_ - -#include "cmsis.h" - -/** @defgroup Stop_Watch CHIP: Stopwatch primitives. - * @ingroup CHIP_Common - * @{ - */ - -/** - * @brief Initialize stopwatch - * @return Nothing - */ -void StopWatch_Init(void); - -/** - * @brief Start a stopwatch - * @return Current cycle count - */ -uint32_t StopWatch_Start(void); - -/** - * @brief Returns number of ticks elapsed since stopwatch was started - * @param startTime : Time returned by StopWatch_Start(). - * @return Number of ticks elapsed since stopwatch was started - */ -STATIC INLINE uint32_t StopWatch_Elapsed(uint32_t startTime) -{ - return StopWatch_Start() - startTime; -} - -/** - * @brief Returns number of ticks per second of the stopwatch timer - * @return Number of ticks per second of the stopwatch timer - */ -uint32_t StopWatch_TicksPerSecond(void); - -/** - * @brief Converts from stopwatch ticks to mS. - * @param ticks : Duration in ticks to convert to mS. - * @return Number of mS in given number of ticks - */ -uint32_t StopWatch_TicksToMs(uint32_t ticks); - -/** - * @brief Converts from stopwatch ticks to uS. - * @param ticks : Duration in ticks to convert to uS. - * @return Number of uS in given number of ticks - */ -uint32_t StopWatch_TicksToUs(uint32_t ticks); - -/** - * @brief Converts from mS to stopwatch ticks. - * @param mS : Duration in mS to convert to ticks. - * @return Number of ticks in given number of mS - */ -uint32_t StopWatch_MsToTicks(uint32_t mS); - -/** - * @brief Converts from uS to stopwatch ticks. - * @param uS : Duration in uS to convert to ticks. - * @return Number of ticks in given number of uS - */ -uint32_t StopWatch_UsToTicks(uint32_t uS); - -/** - * @brief Delays the given number of ticks using stopwatch primitives - * @param ticks : Number of ticks to delay - * @return Nothing - */ -STATIC INLINE void StopWatch_DelayTicks(uint32_t ticks) -{ - uint32_t startTime = StopWatch_Start(); - while (StopWatch_Elapsed(startTime) < ticks) {} -} - -/** - * @brief Delays the given number of mS using stopwatch primitives - * @param mS : Number of mS to delay - * @return Nothing - */ -STATIC INLINE void StopWatch_DelayMs(uint32_t mS) -{ - uint32_t ticks = StopWatch_MsToTicks(mS); - uint32_t startTime = StopWatch_Start(); - while (StopWatch_Elapsed(startTime) < ticks) {} -} - -/** - * @brief Delays the given number of uS using stopwatch primitives - * @param uS : Number of uS to delay - * @return Nothing - */ -STATIC INLINE void StopWatch_DelayUs(uint32_t uS) -{ - uint32_t ticks = StopWatch_UsToTicks(uS); - uint32_t startTime = StopWatch_Start(); - while (StopWatch_Elapsed(startTime) < ticks) {} -} - -/** - * @} - */ - -#endif /* __STOPWATCH_H_ */ diff --git a/bsp/nxp/lpc/lpc5410x/SConstruct b/bsp/nxp/lpc/lpc5410x/SConstruct index 16fdd619846..27627378f96 100644 --- a/bsp/nxp/lpc/lpc5410x/SConstruct +++ b/bsp/nxp/lpc/lpc5410x/SConstruct @@ -10,6 +10,23 @@ else: sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] from building import * +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "nxp-lpc-series-latest"), + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n==============================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("==============================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread-%s.%s' % (rtconfig.BOARD_NAME, rtconfig.TARGET_EXT) DefaultEnvironment(tools=[]) diff --git a/bsp/nxp/lpc/lpc54114-lite/Kconfig b/bsp/nxp/lpc/lpc54114-lite/Kconfig index f1ba90dba4d..c890ea4dd59 100644 --- a/bsp/nxp/lpc/lpc54114-lite/Kconfig +++ b/bsp/nxp/lpc/lpc54114-lite/Kconfig @@ -14,6 +14,7 @@ config SOC_LPC54114 select ARCH_ARM_CORTEX_M4 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select PKG_USING_NXP_LPC_DRIVER default y diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/SConscript b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/SConscript deleted file mode 100644 index 9524170709e..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/SConscript +++ /dev/null @@ -1,12 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -src = Glob('*.c') - -CPPPATH = [cwd] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/arm_common_tables.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/arm_common_tables.h deleted file mode 100644 index dfea7460e9a..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/arm_common_tables.h +++ /dev/null @@ -1,121 +0,0 @@ -/* ---------------------------------------------------------------------- - * Project: CMSIS DSP Library - * Title: arm_common_tables.h - * Description: Extern declaration for common tables - * - * $Date: 27. January 2017 - * $Revision: V.1.5.1 - * - * Target Processor: Cortex-M cores - * -------------------------------------------------------------------- */ -/* - * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - -/* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) -#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) -#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) -#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) -#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) -#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) -#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) -#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) -#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) -#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/arm_const_structs.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/arm_const_structs.h deleted file mode 100644 index 80a3e8bbe72..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/arm_const_structs.h +++ /dev/null @@ -1,66 +0,0 @@ -/* ---------------------------------------------------------------------- - * Project: CMSIS DSP Library - * Title: arm_const_structs.h - * Description: Constant structs that are initialized for user convenience. - * For example, some can be given as arguments to the arm_cfft_f32() function. - * - * $Date: 27. January 2017 - * $Revision: V.1.5.1 - * - * Target Processor: Cortex-M cores - * -------------------------------------------------------------------- */ -/* - * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; - -#endif diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/arm_math.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/arm_math.h deleted file mode 100644 index ea9dd26aa81..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7157 +0,0 @@ -/****************************************************************************** - * @file arm_math.h - * @brief Public header file for CMSIS DSP LibraryU - * @version V1.5.3 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) - * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) - * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) - * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) - * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) - * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) - * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) - * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) - * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) - * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) - * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) - * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) - * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) - * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) - * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) - * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) - * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) - * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) - * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. - * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. - * - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK version 5.14.0.0 - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvprojx - * - * - * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. - * - * Preprocessor Macros - * ------------ - * - * Each library project have different preprocessor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and - * ARM_MATH_CM7 for building the library on cortex-M7. - * - * - ARM_MATH_ARMV8MxL: - * - * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library - * on Armv8-M Mainline target. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. - * - * - __DSP_PRESENT: - * - * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions. - * - *
- * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
- * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2015 Arm Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -/* Compiler specific diagnostic adjustment */ -#if defined ( __CC_ARM ) - -#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - -#elif defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -#elif defined ( __ICCARM__ ) - -#elif defined ( __TI_ARM__ ) - -#elif defined ( __CSMC__ ) - -#elif defined ( __TASKING__ ) - -#else - #error Unknown compiler -#endif - - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) - #include "core_cm7.h" - #define ARM_MATH_DSP -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" - #define ARM_MATH_DSP -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) - #include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_ARMV8MBL) - #include "core_armv8mbl.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_ARMV8MML) - #include "core_armv8mml.h" - #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) - #define ARM_MATH_DSP - #endif -#else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI - #define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined ( __CC_ARM ) - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __GNUC__ ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __ICCARM__ ) - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED - #define CMSIS_INLINE - -#elif defined ( __TI_ARM__ ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE - -#elif defined ( __CSMC__ ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED - #define CMSIS_INLINE - -#elif defined ( __TASKING__ ) - #define __SIMD32_TYPE __unaligned int32_t - #define CMSIS_UNUSED - #define CMSIS_INLINE - -#else - #error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if !defined (ARM_MATH_DSP) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif /* !defined (ARM_MATH_DSP) */ - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - q31_t out; - uint32_t tempVal; - uint32_t index, i; - uint32_t signBits; - - if (in > 0) - { - signBits = ((uint32_t) (__CLZ( in) - 1)); - } - else - { - signBits = ((uint32_t) (__CLZ(-in) - 1)); - } - - /* Convert input sample to 1.31 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 24); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0U; i < 2U; i++) - { - tempVal = (uint32_t) (((q63_t) in * out) >> 31); - tempVal = 0x7FFFFFFFu - tempVal; - /* 1.31 with exp 1 */ - /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ - out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1U); - } - - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - q15_t out = 0; - uint32_t tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if (in > 0) - { - signBits = ((uint32_t)(__CLZ( in) - 17)); - } - else - { - signBits = ((uint32_t)(__CLZ(-in) - 17)); - } - - /* Convert input sample to 1.15 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 8); - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0U; i < 2U; i++) - { - tempVal = (uint32_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFFu - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - } - - -/* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if !defined (ARM_MATH_DSP) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( - uint32_t x, - uint32_t y) - { -/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ - q31_t r = 0, s = 0; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE int32_t __QADD( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); - } - - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); - } - - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( - uint32_t x) - { - return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | - ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); - } - - /* - * @brief C custom defined SMMLA for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( - int32_t x, - int32_t y, - int32_t sum) - { - return (sum + (int32_t) (((int64_t) x * y) >> 32)); - } - -#endif /* !defined (ARM_MATH_DSP) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] S points to an instance of the Q7 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] S points to an instance of the Q15 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] S points to an instance of the Q31 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] S points to an instance of the floating-point FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q15; - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_casd_df1_inst_f32; - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q31; - - - /** - * @brief Floating-point matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); - - - /** - * @brief Q31, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q31 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix scaling. - * @param[in] pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - - /** - * @brief Q15 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#if !defined (ARM_MATH_DSP) - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] S points to an instance of the q15 PID Control structure - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - -/* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] S points to an instance of the Q31 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] S points to an instance of the Q15 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - - /** - * @brief Floating-point vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Dot product of floating-point vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - - /** - * @brief Dot product of Q7 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - - /** - * @brief Dot product of Q15 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Dot product of Q31 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_f32; - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] S points to an instance of the floating-point FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the Q15 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - */ - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q31; - - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Correlation of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] S points to an instance of the floating-point sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] S points to an instance of the Q31 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] S points to an instance of the Q15 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] S points to an instance of the Q7 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cos output. - */ - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCosVal); - - - /** - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cosine output. - */ - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31U); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#if defined (ARM_MATH_DSP) - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - */ - CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - } - - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; - } - - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * The function implements the forward Park transform. - * - */ - CMSIS_INLINE __STATIC_INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - } - - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if (i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if ((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (q31_t)0xFFF00000) >> 20); - - if (index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if (index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1U); - } - } - - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (int32_t)0xFFF00000) >> 20); - - if (index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if (index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (q15_t) (y >> 20); - } - } - - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - if (index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (q7_t) (y >> 20); - } - } - - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - float32_t arm_sin_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q31_t arm_sin_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q15_t arm_sin_q15( - q15_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - float32_t arm_cos_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q31_t arm_cos_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if (in >= 0.0f) - { - -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined(__GNUC__) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) - __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - /** - * @brief floating-point Circular write function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0U; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0U) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0U; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0U) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q15 Circular write function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0U; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0U) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q15 Circular Read function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0U) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0U; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0U) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q7 Circular Read function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0U) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - - /** - * @brief Mean value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Mean value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Floating-point complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - - /** - * @brief Q31 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - - /** - * @brief Floating-point complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - */ - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[in] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - } - - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11U; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; - x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11U; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; - y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return ((q31_t)(acc << 2)); - } - - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return ((q15_t)(acc >> 36)); - } - - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return ((q7_t)(acc >> 40)); - } - - /** - * @} end of BilinearInterpolate group - */ - - -/* SMMLAR */ -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMLSR */ -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMULR */ -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -/* SMMLA */ -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -/* SMMLS */ -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -/* SMMUL */ -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - -#if defined ( __CC_ARM ) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif - - /* Enter low optimization region - place directly above function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __GNUC__ ) - #define LOW_OPTIMIZATION_ENTER \ - __attribute__(( optimize("-O1") )) - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __ICCARM__ ) - /* Enter low optimization region - place directly above function definition */ - #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define LOW_OPTIMIZATION_EXIT - - /* Enter low optimization region - place directly above function definition */ - #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __TI_ARM__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __CSMC__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __TASKING__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - -#ifdef __cplusplus -} -#endif - -/* Compiler specific diagnostic adjustment */ -#if defined ( __CC_ARM ) - -#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - -#elif defined ( __GNUC__ ) -#pragma GCC diagnostic pop - -#elif defined ( __ICCARM__ ) - -#elif defined ( __TI_ARM__ ) - -#elif defined ( __CSMC__ ) - -#elif defined ( __TASKING__ ) - -#else - #error Unknown compiler -#endif - -#endif /* _ARM_MATH_H */ - -/** - * - * End of file. - */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/cmsis_armcc.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/cmsis_armcc.h deleted file mode 100644 index 093d35b9e5c..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/cmsis_armcc.h +++ /dev/null @@ -1,870 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use Arm Compiler Toolchain V4.0.677 or later!" -#endif - -/* CMSIS compiler control architecture macros */ -#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ - (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) - #define __ARM_ARCH_6M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) - #define __ARM_ARCH_7M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) - #define __ARM_ARCH_7EM__ 1 -#endif - - /* __ARM_ARCH_8M_BASE__ not applicable */ - /* __ARM_ARCH_8M_MAIN__ not applicable */ - - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE static __forceinline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __declspec(noreturn) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed)) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT __packed struct -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION __packed union -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1U); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#else - (void)fpscr; -#endif -} - -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0U) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return result; -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/cmsis_armclang.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/cmsis_armclang.h deleted file mode 100644 index 5c4c20e8777..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/cmsis_armclang.h +++ /dev/null @@ -1,1877 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armclang.h - * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#pragma clang system_header /* treat file as system include file */ - -#ifndef __ARM_COMPAT_H -#include /* Compatibility header for Arm Compiler 5 intrinsics */ -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); see arm_compat.h */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); see arm_compat.h */ - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr -#else -#define __get_FPSCR() ((uint32_t)0U) -#endif - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __set_FPSCR __builtin_arm_set_fpscr -#else -#define __set_FPSCR(x) ((void)(x)) -#endif - -#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF); - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF); - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF); - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __builtin_bswap32(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __ROR(__REV(value), 16) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) (int16_t)__builtin_bswap16(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __builtin_arm_rbit - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ (uint8_t)__builtin_clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __builtin_arm_ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/cmsis_compiler.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/cmsis_compiler.h deleted file mode 100644 index 94212eb87a9..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/cmsis_compiler.h +++ /dev/null @@ -1,266 +0,0 @@ -/**************************************************************************//** - * @file cmsis_compiler.h - * @brief CMSIS compiler generic header file - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_COMPILER_H -#define __CMSIS_COMPILER_H - -#include - -/* - * Arm Compiler 4/5 - */ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - - -/* - * Arm Compiler 6 (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armclang.h" - - -/* - * GNU Compiler - */ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - - -/* - * IAR Compiler - */ -#elif defined ( __ICCARM__ ) - #include - - -/* - * TI Arm Compiler - */ -#elif defined ( __TI_ARM__ ) - #include - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __attribute__((packed)) - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed)) - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed)) - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - -/* - * TASKING Compiler - */ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __packed__ - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __packed__ - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __packed__ - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __packed__ T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __align(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - -/* - * COSMIC Compiler - */ -#elif defined ( __CSMC__ ) - #include - - #ifndef __ASM - #define __ASM _asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - // NO RETURN is automatically detected hence no warning here - #define __NO_RETURN - #endif - #ifndef __USED - #warning No compiler specific solution for __USED. __USED is ignored. - #define __USED - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __PACKED - #define __PACKED @packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT @packed struct - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION @packed union - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - @packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - -#else - #error Unknown compiler. -#endif - - -#endif /* __CMSIS_COMPILER_H */ - diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/cmsis_gcc.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/cmsis_gcc.h deleted file mode 100644 index 5d0f07e8acc..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/cmsis_gcc.h +++ /dev/null @@ -1,2088 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS compiler GCC header file - * @version V5.0.3 - * @date 16. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -/* Fallback for __has_builtin */ -#ifndef __has_builtin - #define __has_builtin(x) (0) -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - return __builtin_arm_get_fpscr(); -#else - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#endif -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - __builtin_arm_set_fpscr(fpscr); -#else - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); -#endif -#else - (void)fpscr; -#endif -} - -#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __ASM volatile ("nop") - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __ASM volatile ("wfi") - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __ASM volatile ("wfe") - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __ASM volatile ("sev") - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__STATIC_FORCEINLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__STATIC_FORCEINLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__STATIC_FORCEINLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (int16_t)__builtin_bswap16(value); -#else - int16_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return result; -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ (uint8_t)__builtin_clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__STATIC_FORCEINLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ - __extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#pragma GCC diagnostic pop - -#endif /* __CMSIS_GCC_H */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/cmsis_iccarm.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/cmsis_iccarm.h deleted file mode 100644 index edcaee3d4ab..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/cmsis_iccarm.h +++ /dev/null @@ -1,913 +0,0 @@ -/**************************************************************************//** - * @file cmsis_iccarm.h - * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.0.5 - * @date 10. January 2018 - ******************************************************************************/ - -//------------------------------------------------------------------------------ -// -// Copyright (c) 2017-2018 IAR Systems -// -// Licensed under the Apache License, Version 2.0 (the "License") -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -//------------------------------------------------------------------------------ - - -#ifndef __CMSIS_ICCARM_H__ -#define __CMSIS_ICCARM_H__ - -#ifndef __ICCARM__ - #error This file should only be compiled by ICCARM -#endif - -#pragma system_include - -#define __IAR_FT _Pragma("inline=forced") __intrinsic - -#if (__VER__ >= 8000000) - #define __ICCARM_V8 1 -#else - #define __ICCARM_V8 0 -#endif - -#ifndef __ALIGNED - #if __ICCARM_V8 - #define __ALIGNED(x) __attribute__((aligned(x))) - #elif (__VER__ >= 7080000) - /* Needs IAR language extensions */ - #define __ALIGNED(x) __attribute__((aligned(x))) - #else - #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. - #define __ALIGNED(x) - #endif -#endif - - -/* Define compiler macros for CPU architecture, used in CMSIS 5. - */ -#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ -/* Macros already defined */ -#else - #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' - #if __ARM_ARCH == 6 - #define __ARM_ARCH_6M__ 1 - #elif __ARM_ARCH == 7 - #if __ARM_FEATURE_DSP - #define __ARM_ARCH_7EM__ 1 - #else - #define __ARM_ARCH_7M__ 1 - #endif - #endif /* __ARM_ARCH */ - #endif /* __ARM_ARCH_PROFILE == 'M' */ -#endif - -/* Alternativ core deduction for older ICCARM's */ -#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ - !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) - #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) - #define __ARM_ARCH_6M__ 1 - #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) - #define __ARM_ARCH_7M__ 1 - #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) - #define __ARM_ARCH_7EM__ 1 - #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #else - #error "Unknown target." - #endif -#endif - - - -#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 - #define __IAR_M0_FAMILY 1 -#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 - #define __IAR_M0_FAMILY 1 -#else - #define __IAR_M0_FAMILY 0 -#endif - - -#ifndef __ASM - #define __ASM __asm -#endif - -#ifndef __INLINE - #define __INLINE inline -#endif - -#ifndef __NO_RETURN - #if __ICCARM_V8 - #define __NO_RETURN __attribute__((__noreturn__)) - #else - #define __NO_RETURN _Pragma("object_attribute=__noreturn") - #endif -#endif - -#ifndef __PACKED - #if __ICCARM_V8 - #define __PACKED __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED __packed - #endif -#endif - -#ifndef __PACKED_STRUCT - #if __ICCARM_V8 - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_STRUCT __packed struct - #endif -#endif - -#ifndef __PACKED_UNION - #if __ICCARM_V8 - #define __PACKED_UNION union __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_UNION __packed union - #endif -#endif - -#ifndef __RESTRICT - #define __RESTRICT restrict -#endif - -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif - -#ifndef __FORCEINLINE - #define __FORCEINLINE _Pragma("inline=forced") -#endif - -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE -#endif - -#ifndef __UNALIGNED_UINT16_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint16_t __iar_uint16_read(void const *ptr) -{ - return *(__packed uint16_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) -#endif - - -#ifndef __UNALIGNED_UINT16_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) -{ - *(__packed uint16_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint32_t __iar_uint32_read(void const *ptr) -{ - return *(__packed uint32_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) -#endif - -#ifndef __UNALIGNED_UINT32_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) -{ - *(__packed uint32_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32 /* deprecated */ -#pragma language=save -#pragma language=extended -__packed struct __iar_u32 { uint32_t v; }; -#pragma language=restore -#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) -#endif - -#ifndef __USED - #if __ICCARM_V8 - #define __USED __attribute__((used)) - #else - #define __USED _Pragma("__root") - #endif -#endif - -#ifndef __WEAK - #if __ICCARM_V8 - #define __WEAK __attribute__((weak)) - #else - #define __WEAK _Pragma("__weak") - #endif -#endif - - -#ifndef __ICCARM_INTRINSICS_VERSION__ - #define __ICCARM_INTRINSICS_VERSION__ 0 -#endif - -#if __ICCARM_INTRINSICS_VERSION__ == 2 - - #if defined(__CLZ) - #undef __CLZ - #endif - #if defined(__REVSH) - #undef __REVSH - #endif - #if defined(__RBIT) - #undef __RBIT - #endif - #if defined(__SSAT) - #undef __SSAT - #endif - #if defined(__USAT) - #undef __USAT - #endif - - #include "iccarm_builtin.h" - - #define __disable_fault_irq __iar_builtin_disable_fiq - #define __disable_irq __iar_builtin_disable_interrupt - #define __enable_fault_irq __iar_builtin_enable_fiq - #define __enable_irq __iar_builtin_enable_interrupt - #define __arm_rsr __iar_builtin_rsr - #define __arm_wsr __iar_builtin_wsr - - - #define __get_APSR() (__arm_rsr("APSR")) - #define __get_BASEPRI() (__arm_rsr("BASEPRI")) - #define __get_CONTROL() (__arm_rsr("CONTROL")) - #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) - - #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - #define __get_FPSCR() (__arm_rsr("FPSCR")) - #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) - #else - #define __get_FPSCR() ( 0 ) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #define __get_IPSR() (__arm_rsr("IPSR")) - #define __get_MSP() (__arm_rsr("MSP")) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __get_MSPLIM() (0U) - #else - #define __get_MSPLIM() (__arm_rsr("MSPLIM")) - #endif - #define __get_PRIMASK() (__arm_rsr("PRIMASK")) - #define __get_PSP() (__arm_rsr("PSP")) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __get_PSPLIM() (0U) - #else - #define __get_PSPLIM() (__arm_rsr("PSPLIM")) - #endif - - #define __get_xPSR() (__arm_rsr("xPSR")) - - #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) - #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) - #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) - #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) - #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __set_MSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) - #endif - #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) - #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __set_PSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) - #endif - - #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) - #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) - #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) - #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) - #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) - #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) - #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) - #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) - #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) - #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) - #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) - #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) - #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) - #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) - #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) - #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) - #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) - #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) - - #define __NOP __iar_builtin_no_operation - - #define __CLZ __iar_builtin_CLZ - #define __CLREX __iar_builtin_CLREX - - #define __DMB __iar_builtin_DMB - #define __DSB __iar_builtin_DSB - #define __ISB __iar_builtin_ISB - - #define __LDREXB __iar_builtin_LDREXB - #define __LDREXH __iar_builtin_LDREXH - #define __LDREXW __iar_builtin_LDREX - - #define __RBIT __iar_builtin_RBIT - #define __REV __iar_builtin_REV - #define __REV16 __iar_builtin_REV16 - - __IAR_FT int16_t __REVSH(int16_t val) - { - return (int16_t) __iar_builtin_REVSH(val); - } - - #define __ROR __iar_builtin_ROR - #define __RRX __iar_builtin_RRX - - #define __SEV __iar_builtin_SEV - - #if !__IAR_M0_FAMILY - #define __SSAT __iar_builtin_SSAT - #endif - - #define __STREXB __iar_builtin_STREXB - #define __STREXH __iar_builtin_STREXH - #define __STREXW __iar_builtin_STREX - - #if !__IAR_M0_FAMILY - #define __USAT __iar_builtin_USAT - #endif - - #define __WFE __iar_builtin_WFE - #define __WFI __iar_builtin_WFI - - #if __ARM_MEDIA__ - #define __SADD8 __iar_builtin_SADD8 - #define __QADD8 __iar_builtin_QADD8 - #define __SHADD8 __iar_builtin_SHADD8 - #define __UADD8 __iar_builtin_UADD8 - #define __UQADD8 __iar_builtin_UQADD8 - #define __UHADD8 __iar_builtin_UHADD8 - #define __SSUB8 __iar_builtin_SSUB8 - #define __QSUB8 __iar_builtin_QSUB8 - #define __SHSUB8 __iar_builtin_SHSUB8 - #define __USUB8 __iar_builtin_USUB8 - #define __UQSUB8 __iar_builtin_UQSUB8 - #define __UHSUB8 __iar_builtin_UHSUB8 - #define __SADD16 __iar_builtin_SADD16 - #define __QADD16 __iar_builtin_QADD16 - #define __SHADD16 __iar_builtin_SHADD16 - #define __UADD16 __iar_builtin_UADD16 - #define __UQADD16 __iar_builtin_UQADD16 - #define __UHADD16 __iar_builtin_UHADD16 - #define __SSUB16 __iar_builtin_SSUB16 - #define __QSUB16 __iar_builtin_QSUB16 - #define __SHSUB16 __iar_builtin_SHSUB16 - #define __USUB16 __iar_builtin_USUB16 - #define __UQSUB16 __iar_builtin_UQSUB16 - #define __UHSUB16 __iar_builtin_UHSUB16 - #define __SASX __iar_builtin_SASX - #define __QASX __iar_builtin_QASX - #define __SHASX __iar_builtin_SHASX - #define __UASX __iar_builtin_UASX - #define __UQASX __iar_builtin_UQASX - #define __UHASX __iar_builtin_UHASX - #define __SSAX __iar_builtin_SSAX - #define __QSAX __iar_builtin_QSAX - #define __SHSAX __iar_builtin_SHSAX - #define __USAX __iar_builtin_USAX - #define __UQSAX __iar_builtin_UQSAX - #define __UHSAX __iar_builtin_UHSAX - #define __USAD8 __iar_builtin_USAD8 - #define __USADA8 __iar_builtin_USADA8 - #define __SSAT16 __iar_builtin_SSAT16 - #define __USAT16 __iar_builtin_USAT16 - #define __UXTB16 __iar_builtin_UXTB16 - #define __UXTAB16 __iar_builtin_UXTAB16 - #define __SXTB16 __iar_builtin_SXTB16 - #define __SXTAB16 __iar_builtin_SXTAB16 - #define __SMUAD __iar_builtin_SMUAD - #define __SMUADX __iar_builtin_SMUADX - #define __SMMLA __iar_builtin_SMMLA - #define __SMLAD __iar_builtin_SMLAD - #define __SMLADX __iar_builtin_SMLADX - #define __SMLALD __iar_builtin_SMLALD - #define __SMLALDX __iar_builtin_SMLALDX - #define __SMUSD __iar_builtin_SMUSD - #define __SMUSDX __iar_builtin_SMUSDX - #define __SMLSD __iar_builtin_SMLSD - #define __SMLSDX __iar_builtin_SMLSDX - #define __SMLSLD __iar_builtin_SMLSLD - #define __SMLSLDX __iar_builtin_SMLSLDX - #define __SEL __iar_builtin_SEL - #define __QADD __iar_builtin_QADD - #define __QSUB __iar_builtin_QSUB - #define __PKHBT __iar_builtin_PKHBT - #define __PKHTB __iar_builtin_PKHTB - #endif - -#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #define __CLZ __cmsis_iar_clz_not_active - #define __SSAT __cmsis_iar_ssat_not_active - #define __USAT __cmsis_iar_usat_not_active - #define __RBIT __cmsis_iar_rbit_not_active - #define __get_APSR __cmsis_iar_get_APSR_not_active - #endif - - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #define __get_FPSCR __cmsis_iar_get_FPSR_not_active - #define __set_FPSCR __cmsis_iar_set_FPSR_not_active - #endif - - #ifdef __INTRINSICS_INCLUDED - #error intrinsics.h is already included previously! - #endif - - #include - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #undef __CLZ - #undef __SSAT - #undef __USAT - #undef __RBIT - #undef __get_APSR - - __STATIC_INLINE uint8_t __CLZ(uint32_t data) - { - if (data == 0U) { return 32U; } - - uint32_t count = 0U; - uint32_t mask = 0x80000000U; - - while ((data & mask) == 0U) - { - count += 1U; - mask = mask >> 1U; - } - return count; - } - - __STATIC_INLINE uint32_t __RBIT(uint32_t v) - { - uint8_t sc = 31U; - uint32_t r = v; - for (v >>= 1U; v; v >>= 1U) - { - r <<= 1U; - r |= v & 1U; - sc--; - } - return (r << sc); - } - - __STATIC_INLINE uint32_t __get_APSR(void) - { - uint32_t res; - __asm("MRS %0,APSR" : "=r" (res)); - return res; - } - - #endif - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #undef __get_FPSCR - #undef __set_FPSCR - #define __get_FPSCR() (0) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #pragma diag_suppress=Pe940 - #pragma diag_suppress=Pe177 - - #define __enable_irq __enable_interrupt - #define __disable_irq __disable_interrupt - #define __NOP __no_operation - - #define __get_xPSR __get_PSR - - #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) - - __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) - { - return __LDREX((unsigned long *)ptr); - } - - __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) - { - return __STREX(value, (unsigned long *)ptr); - } - #endif - - - /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - #if (__CORTEX_M >= 0x03) - - __IAR_FT uint32_t __RRX(uint32_t value) - { - uint32_t result; - __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); - return(result); - } - - __IAR_FT void __set_BASEPRI_MAX(uint32_t value) - { - __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); - } - - - #define __enable_fault_irq __enable_fiq - #define __disable_fault_irq __disable_fiq - - - #endif /* (__CORTEX_M >= 0x03) */ - - __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) - { - return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); - } - - #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - __IAR_FT uint32_t __get_MSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,MSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_MSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR MSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __get_PSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,PSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_PSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR PSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) - { - __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PSP_NS(uint32_t value) - { - __asm volatile("MSR PSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_MSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSP_NS(uint32_t value) - { - __asm volatile("MSR MSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_SP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,SP_NS" : "=r" (res)); - return res; - } - __IAR_FT void __TZ_set_SP_NS(uint32_t value) - { - __asm volatile("MSR SP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) - { - __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) - { - __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) - { - __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); - return res; - } - __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) - { - __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) - { - __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); - } - - #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - -#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) - -#if __IAR_M0_FAMILY - __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) - { - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; - } - - __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) - { - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; - } -#endif - -#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - - __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) - { - uint32_t res; - __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) - { - uint32_t res; - __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) - { - uint32_t res; - __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return res; - } - - __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) - { - __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) - { - __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) - { - __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); - } - -#endif /* (__CORTEX_M >= 0x03) */ - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - - __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); - return res; - } - - __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) - { - __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) - { - __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) - { - __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); - } - - __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); - return res; - } - -#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#undef __IAR_FT -#undef __IAR_M0_FAMILY -#undef __ICCARM_V8 - -#pragma diag_default=Pe940 -#pragma diag_default=Pe177 - -#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/cmsis_version.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/cmsis_version.h deleted file mode 100644 index 660f612aa31..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/cmsis_version.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************//** - * @file cmsis_version.h - * @brief CMSIS Core(M) Version definitions - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CMSIS_VERSION_H -#define __CMSIS_VERSION_H - -/* CMSIS Version definitions */ -#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ -#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ - __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ -#endif diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_armv8mbl.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_armv8mbl.h deleted file mode 100644 index 47a39893ace..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_armv8mbl.h +++ /dev/null @@ -1,1896 +0,0 @@ -/**************************************************************************//** - * @file core_armv8mbl.h - * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_ARMV8MBL_H_GENERIC -#define __CORE_ARMV8MBL_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MBL - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS definitions */ -#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MBL_H_DEPENDANT -#define __CORE_ARMV8MBL_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv8MBL_REV - #define __ARMv8MBL_REV 0x0000U - #warning "__ARMv8MBL_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif - - #ifndef __ETM_PRESENT - #define __ETM_PRESENT 0U - #warning "__ETM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MTB_PRESENT - #define __MTB_PRESENT 0U - #warning "__MTB_PRESENT not defined in device header file; using default!" - #endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MBL */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_armv8mml.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_armv8mml.h deleted file mode 100644 index 0951a1f7812..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_armv8mml.h +++ /dev/null @@ -1,2960 +0,0 @@ -/**************************************************************************//** - * @file core_armv8mml.h - * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_ARMV8MML_H_GENERIC -#define __CORE_ARMV8MML_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MML - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS Armv8MML definitions */ -#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (81U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MML_H_DEPENDANT -#define __CORE_ARMV8MML_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv8MML_REV - #define __ARMv8MML_REV 0x0000U - #warning "__ARMv8MML_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MML */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_cm0.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_cm0.h deleted file mode 100644 index a3f1b9ac330..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_cm0.h +++ /dev/null @@ -1,888 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V5.0.3 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M0 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000U - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - Address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)0x0U; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)0x0U; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_cm0plus.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_cm0plus.h deleted file mode 100644 index f8f30c3496a..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_cm0plus.h +++ /dev/null @@ -1,1023 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000U - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; - -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_cm23.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_cm23.h deleted file mode 100644 index 7d1d478af2a..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_cm23.h +++ /dev/null @@ -1,1899 +0,0 @@ -/**************************************************************************//** - * @file core_cm23.h - * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM23_H_GENERIC -#define __CORE_CM23_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M23 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS definitions */ -#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ - __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (23U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM23_H_DEPENDANT -#define __CORE_CM23_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM23_REV - #define __CM23_REV 0x0000U - #warning "__CM23_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif - - #ifndef __ETM_PRESENT - #define __ETM_PRESENT 0U - #warning "__ETM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MTB_PRESENT - #define __MTB_PRESENT 0U - #warning "__MTB_PRESENT not defined in device header file; using default!" - #endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M23 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ - -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_cm3.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_cm3.h deleted file mode 100644 index a2c0d080572..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_cm3.h +++ /dev/null @@ -1,1933 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V5.0.5 - * @date 08. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M3 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (3U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200U - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1U]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ - -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_cm33.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_cm33.h deleted file mode 100644 index b1efbcae7c7..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_cm33.h +++ /dev/null @@ -1,2963 +0,0 @@ -/**************************************************************************//** - * @file core_cm33.h - * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File - * @version V5.0.5 - * @date 08. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM33_H_GENERIC -#define __CORE_CM33_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M33 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM33 definitions */ -#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ - __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (33U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined (__TARGET_FPU_VFP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined (__ARM_PCS_VFP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined (__ARMVFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined (__TI_VFP_SUPPORT__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined (__FPU_VFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM33_H_DEPENDANT -#define __CORE_CM33_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM33_REV - #define __CM33_REV 0x0000U - #warning "__CM33_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M33 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ - -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_cm4.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_cm4.h deleted file mode 100644 index a11a3817a23..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,2118 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V5.0.5 - * @date 08. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M4 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (4U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000U - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ - -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_cm7.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_cm7.h deleted file mode 100644 index 1fe53bf012f..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_cm7.h +++ /dev/null @@ -1,2660 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V5.0.5 - * @date 08. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M7 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (7U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000U - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0U - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1U]; - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ - -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = SCB->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## Cache functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_INLINE void SCB_EnableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_INLINE void SCB_DisableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_INLINE void SCB_InvalidateICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_INLINE void SCB_EnableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_INLINE void SCB_DisableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - register uint32_t ccsidr; - register uint32_t sets; - register uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_INLINE void SCB_InvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_INLINE void SCB_CleanDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_INLINE void SCB_CleanInvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t)addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCIMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCIMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_sc000.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_sc000.h deleted file mode 100644 index 9aab5e5b3ea..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_sc000.h +++ /dev/null @@ -1,1016 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V5.0.3 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC000 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_SC (000U) /*!< Cortex secure core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000U - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the SC000 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_sc300.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_sc300.h deleted file mode 100644 index a569ef2acec..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/core_sc300.h +++ /dev/null @@ -1,1903 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V5.0.3 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC3000 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_SC (300U) /*!< Cortex secure core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000U - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED1[129U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1U]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/mpu_armv7.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/mpu_armv7.h deleted file mode 100644 index aa180c9e596..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/mpu_armv7.h +++ /dev/null @@ -1,197 +0,0 @@ -/****************************************************************************** - * @file mpu_armv7.h - * @brief CMSIS MPU API for Armv7-M MPU - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2017-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_MPU_ARMV7_H -#define ARM_MPU_ARMV7_H - -#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) -#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) -#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) -#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) -#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) -#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) -#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) -#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) -#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) -#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) -#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) -#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) -#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) -#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) -#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) -#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) -#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) -#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) -#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) -#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) -#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) -#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) -#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) -#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) -#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) -#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) -#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) -#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) - -#define ARM_MPU_AP_NONE 0U -#define ARM_MPU_AP_PRIV 1U -#define ARM_MPU_AP_URO 2U -#define ARM_MPU_AP_FULL 3U -#define ARM_MPU_AP_PRO 5U -#define ARM_MPU_AP_RO 6U - -/** MPU Region Base Address Register Value -* -* \param Region The region to be configured, number 0 to 15. -* \param BaseAddress The base address for the region. -*/ -#define ARM_MPU_RBAR(Region, BaseAddress) \ - (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ - ((Region) & MPU_RBAR_REGION_Msk) | \ - (MPU_RBAR_VALID_Msk)) - -/** -* MPU Region Attribute and Size Register Value -* -* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. -* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. -* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. -* \param IsShareable Region is shareable between multiple bus masters. -* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. -* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -* \param SubRegionDisable Sub-region disable field. -* \param Size Region size of the region to be configured, for example 4K, 8K. -*/ -#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ - ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ - (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ - (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ - (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ - (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ - (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \ - (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ - (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ - (MPU_RASR_ENABLE_Msk)) - - -/** -* Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; //!< The region base address register value (RBAR) - uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DSB(); - __ISB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DSB(); - __ISB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - MPU->RNR = rnr; - MPU->RASR = 0U; -} - -/** Configure an MPU region. -* \param rbar Value for RBAR register. -* \param rsar Value for RSAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) -{ - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rsar Value for RSAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) -{ - MPU->RNR = rnr; - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Memcopy with strictly ordered memory access, e.g. for register targets. -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - while (cnt > MPU_TYPE_RALIASES) { - orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); - table += MPU_TYPE_RALIASES; - cnt -= MPU_TYPE_RALIASES; - } - orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); -} - -#endif diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/mpu_armv8.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/mpu_armv8.h deleted file mode 100644 index 0ccfc74fe5b..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/mpu_armv8.h +++ /dev/null @@ -1,333 +0,0 @@ -/****************************************************************************** - * @file mpu_armv8.h - * @brief CMSIS MPU API for Armv8-M MPU - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2017-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_MPU_ARMV8_H -#define ARM_MPU_ARMV8_H - -/** \brief Attribute for device memory (outer only) */ -#define ARM_MPU_ATTR_DEVICE ( 0U ) - -/** \brief Attribute for non-cacheable, normal memory */ -#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) - -/** \brief Attribute for normal memory (outer and inner) -* \param NT Non-Transient: Set to 1 for non-transient data. -* \param WB Write-Back: Set to 1 to use write-back update policy. -* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. -* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. -*/ -#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ - (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) - -/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) - -/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) - -/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGRE (2U) - -/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_GRE (3U) - -/** \brief Memory Attribute -* \param O Outer memory attributes -* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes -*/ -#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) - -/** \brief Normal memory non-shareable */ -#define ARM_MPU_SH_NON (0U) - -/** \brief Normal memory outer shareable */ -#define ARM_MPU_SH_OUTER (2U) - -/** \brief Normal memory inner shareable */ -#define ARM_MPU_SH_INNER (3U) - -/** \brief Memory access permissions -* \param RO Read-Only: Set to 1 for read-only memory. -* \param NP Non-Privileged: Set to 1 for non-privileged memory. -*/ -#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) - -/** \brief Region Base Address Register value -* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. -* \param SH Defines the Shareability domain for this memory region. -* \param RO Read-Only: Set to 1 for a read-only memory region. -* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. -* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. -*/ -#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ - ((BASE & MPU_RBAR_BASE_Pos) | \ - ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ - ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ - ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) - -/** \brief Region Limit Address Register value -* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -* \param IDX The attribute index to be associated with this memory region. -*/ -#define ARM_MPU_RLAR(LIMIT, IDX) \ - ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ - ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ - (MPU_RLAR_EN_Msk)) - -/** -* Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; /*!< Region Base Address Register value */ - uint32_t RLAR; /*!< Region Limit Address Register value */ -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DSB(); - __ISB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DSB(); - __ISB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; -} - -#ifdef MPU_NS -/** Enable the Non-secure MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) -{ - __DSB(); - __ISB(); - MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif -} - -/** Disable the Non-secure MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable_NS(void) -{ - __DSB(); - __ISB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; -} -#endif - -/** Set the memory attribute encoding to the given MPU. -* \param mpu Pointer to the MPU to be configured. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) -{ - const uint8_t reg = idx / 4U; - const uint32_t pos = ((idx % 4U) * 8U); - const uint32_t mask = 0xFFU << pos; - - if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { - return; // invalid index - } - - mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); -} - -/** Set the memory attribute encoding. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU, idx, attr); -} - -#ifdef MPU_NS -/** Set the memory attribute encoding to the Non-secure MPU. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); -} -#endif - -/** Clear and disable the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) -{ - mpu->RNR = rnr; - mpu->RLAR = 0U; -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU, rnr); -} - -#ifdef MPU_NS -/** Clear and disable the given Non-secure MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU_NS, rnr); -} -#endif - -/** Configure the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - mpu->RNR = rnr; - mpu->RBAR = rbar; - mpu->RLAR = rlar; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); -} - -#ifdef MPU_NS -/** Configure the given Non-secure MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); -} -#endif - -/** Memcopy with strictly ordered memory access, e.g. for register targets. -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table to the given MPU. -* \param mpu Pointer to the MPU registers to be used. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - if (cnt == 1U) { - mpu->RNR = rnr; - orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); - } else { - uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); - uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; - - mpu->RNR = rnrBase; - while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { - uint32_t c = MPU_TYPE_RALIASES - rnrOffset; - orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); - table += c; - cnt -= c; - rnrOffset = 0U; - rnrBase += MPU_TYPE_RALIASES; - mpu->RNR = rnrBase; - } - - orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); - } -} - -/** Load the given number of MPU regions from a table. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU, rnr, table, cnt); -} - -#ifdef MPU_NS -/** Load the given number of MPU regions from a table to the Non-secure MPU. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); -} -#endif - -#endif - diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/tz_context.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/tz_context.h deleted file mode 100644 index 0d09749f3a5..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/Include/tz_context.h +++ /dev/null @@ -1,70 +0,0 @@ -/****************************************************************************** - * @file tz_context.h - * @brief Context Management for Armv8-M TrustZone - * @version V1.0.1 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2017-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef TZ_CONTEXT_H -#define TZ_CONTEXT_H - -#include - -#ifndef TZ_MODULEID_T -#define TZ_MODULEID_T -/// \details Data type that identifies secure software modules called by a process. -typedef uint32_t TZ_ModuleId_t; -#endif - -/// \details TZ Memory ID identifies an allocated memory slot. -typedef uint32_t TZ_MemoryId_t; - -/// Initialize secure context memory system -/// \return execution status (1: success, 0: error) -uint32_t TZ_InitContextSystem_S (void); - -/// Allocate context memory for calling secure software modules in TrustZone -/// \param[in] module identifies software modules called from non-secure mode -/// \return value != 0 id TrustZone memory slot identifier -/// \return value 0 no memory available or internal error -TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); - -/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); - -/// Load secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); - -/// Store secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); - -#endif // TZ_CONTEXT_H diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/SConscript b/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/SConscript deleted file mode 100644 index 4c815c49b83..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/CMSIS/SConscript +++ /dev/null @@ -1,15 +0,0 @@ -# RT-Thread building script for bridge - -import os -from building import * - -cwd = GetCurrentDir() -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/SConscript b/bsp/nxp/lpc/lpc54114-lite/Libraries/SConscript deleted file mode 100644 index 4c815c49b83..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/SConscript +++ /dev/null @@ -1,15 +0,0 @@ -# RT-Thread building script for bridge - -import os -from building import * - -cwd = GetCurrentDir() -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm0plus.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm0plus.h deleted file mode 100644 index 6dff1ea844f..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm0plus.h +++ /dev/null @@ -1,7103 +0,0 @@ -/* -** ################################################################### -** Processors: LPC54114J256BD64_cm0plus -** LPC54114J256UK49_cm0plus -** -** Compilers: Keil ARM C/C++ Compiler -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 -** Version: rev. 1.0, 2016-04-29 -** Build: b180227 -** -** Abstract: -** CMSIS Peripheral Access Layer for LPC54114_cm0plus -** -** The Clear BSD License -** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without -** modification, are permitted (subject to the limitations in the -** disclaimer below) provided that the following conditions are met: -** -** * Redistributions of source code must retain the above copyright -** notice, this list of conditions and the following disclaimer. -** -** * Redistributions in binary form must reproduce the above copyright -** notice, this list of conditions and the following disclaimer in the -** documentation and/or other materials provided with the distribution. -** -** * Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from -** this software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2016-04-29) -** Initial version. -** -** ################################################################### -*/ - -/*! - * @file LPC54114_cm0plus.h - * @version 1.0 - * @date 2016-04-29 - * @brief CMSIS Peripheral Access Layer for LPC54114_cm0plus - * - * CMSIS Peripheral Access Layer for LPC54114_cm0plus - */ - -#ifndef _LPC54114_CM0PLUS_H_ -#define _LPC54114_CM0PLUS_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0000U - - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Auxiliary constants */ - NotAvail_IRQn = -128, /**< Not available device specific interrupt */ - - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ - - /* Device specific interrupts */ - WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */ - DMA0_IRQn = 1, /**< DMA controller */ - GINT0_IRQn = 2, /**< GPIO group 0 */ - GINT1_IRQn = 3, /**< GPIO group 1 */ - PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ - PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ - PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ - PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ - UTICK0_IRQn = 8, /**< Micro-tick Timer */ - MRT0_IRQn = 9, /**< Multi-rate timer */ - CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ - CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ - SCT0_IRQn = 12, /**< SCTimer/PWM */ - CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ - FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C) */ - FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C) */ - FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C) */ - FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C) */ - FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C) */ - FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C) */ - FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S) */ - FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S) */ - ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */ - ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */ - ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */ - DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */ - HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */ - USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ - USB0_IRQn = 28, /**< USB device */ - RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ - IOH_IRQn = 30, /**< IOH */ - MAILBOX_IRQn = 31 /**< Mailbox interrupt (present on selected devices) */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M0 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration - * @{ - */ - -#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ -#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ -#define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ -#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ - -#include "core_cm0plus.h" /* Core Peripheral Access Layer */ -#include "system_LPC54114_cm0plus.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Mapping Information - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Mapping_Information Mapping Information - * @{ - */ - -/** Mapping Information */ -/*! - * @addtogroup dma_request - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief Structure for the DMA hardware request - * - * Defines the structure for the DMA hardware request collections. The user can configure the - * hardware request to trigger the DMA transfer accordingly. The index - * of the hardware request varies according to the to SoC. - */ -typedef enum _dma_request_source -{ - kDmaRequestFlexcomm0Rx = 0U, /**< Flexcomm Interface 0 RX/I2C Slave */ - kDmaRequestFlexcomm0Tx = 1U, /**< Flexcomm Interface 0 TX/I2C Master */ - kDmaRequestFlexcomm1Rx = 2U, /**< Flexcomm Interface 1 RX/I2C Slave */ - kDmaRequestFlexcomm1Tx = 3U, /**< Flexcomm Interface 1 TX/I2C Master */ - kDmaRequestFlexcomm2Rx = 4U, /**< Flexcomm Interface 2 RX/I2C Slave */ - kDmaRequestFlexcomm2Tx = 5U, /**< Flexcomm Interface 2 TX/I2C Master */ - kDmaRequestFlexcomm3Rx = 6U, /**< Flexcomm Interface 3 RX/I2C Slave */ - kDmaRequestFlexcomm3Tx = 7U, /**< Flexcomm Interface 3 TX/I2C Master */ - kDmaRequestFlexcomm4Rx = 8U, /**< Flexcomm Interface 4 RX/I2C Slave */ - kDmaRequestFlexcomm4Tx = 9U, /**< Flexcomm Interface 4 TX/I2C Master */ - kDmaRequestFlexcomm5Rx = 10U, /**< Flexcomm Interface 5 RX/I2C Slave */ - kDmaRequestFlexcomm5Tx = 11U, /**< Flexcomm Interface 5 TX/I2C Master */ - kDmaRequestFlexcomm6Rx = 12U, /**< Flexcomm Interface 6 RX/I2C Slave */ - kDmaRequestFlexcomm6Tx = 13U, /**< Flexcomm Interface 6 TX/I2C Master */ - kDmaRequestFlexcomm7Rx = 14U, /**< Flexcomm Interface 7 RX/I2C Slave */ - kDmaRequestFlexcomm7Tx = 15U, /**< Flexcomm Interface 7 TX/I2C Master */ - kDmaRequestDMIC0 = 16U, /**< Digital microphone interface 0 */ - kDmaRequestDMIC1 = 17U, /**< Digital microphone interface 1 */ - kDmaRequestNoDMARequest18 = 18U, /**< No DMA request 18 */ - kDmaRequestNoDMARequest19 = 19U, /**< No DMA request 19 */ -} dma_request_source_t; - -/* @} */ - - -/*! - * @} - */ /* end of group Mapping_Information */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #else - #pragma push - #pragma anon_unions - #endif -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */ - __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */ - __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */ - __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */ - uint8_t RESERVED_0[8]; - __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */ - __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */ - __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */ - __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */ - __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */ - __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */ - __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */ - __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */ - __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */ - __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */ -/*! @{ */ -#define ADC_CTRL_CLKDIV_MASK (0xFFU) -#define ADC_CTRL_CLKDIV_SHIFT (0U) -#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK) -#define ADC_CTRL_ASYNMODE_MASK (0x100U) -#define ADC_CTRL_ASYNMODE_SHIFT (8U) -#define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK) -#define ADC_CTRL_RESOL_MASK (0x600U) -#define ADC_CTRL_RESOL_SHIFT (9U) -#define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK) -#define ADC_CTRL_BYPASSCAL_MASK (0x800U) -#define ADC_CTRL_BYPASSCAL_SHIFT (11U) -#define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK) -#define ADC_CTRL_TSAMP_MASK (0x7000U) -#define ADC_CTRL_TSAMP_SHIFT (12U) -#define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK) -/*! @} */ - -/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */ -/*! @{ */ -#define ADC_INSEL_SEL_MASK (0x3U) -#define ADC_INSEL_SEL_SHIFT (0U) -#define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK) -/*! @} */ - -/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */ -/*! @{ */ -#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU) -#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U) -#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK) -#define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U) -#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U) -#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK) -#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U) -#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U) -#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK) -#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U) -#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U) -#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK) -#define ADC_SEQ_CTRL_START_MASK (0x4000000U) -#define ADC_SEQ_CTRL_START_SHIFT (26U) -#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK) -#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U) -#define ADC_SEQ_CTRL_BURST_SHIFT (27U) -#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK) -#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U) -#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U) -#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK) -#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U) -#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U) -#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK) -#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U) -#define ADC_SEQ_CTRL_MODE_SHIFT (30U) -#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK) -#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U) -#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U) -#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK) -/*! @} */ - -/* The count of ADC_SEQ_CTRL */ -#define ADC_SEQ_CTRL_COUNT (2U) - -/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */ -/*! @{ */ -#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U) -#define ADC_SEQ_GDAT_RESULT_SHIFT (4U) -#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK) -#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U) -#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U) -#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK) -#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U) -#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U) -#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK) -#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U) -#define ADC_SEQ_GDAT_CHN_SHIFT (26U) -#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK) -#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U) -#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U) -#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK) -#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U) -#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U) -#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK) -/*! @} */ - -/* The count of ADC_SEQ_GDAT */ -#define ADC_SEQ_GDAT_COUNT (2U) - -/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */ -/*! @{ */ -#define ADC_DAT_RESULT_MASK (0xFFF0U) -#define ADC_DAT_RESULT_SHIFT (4U) -#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK) -#define ADC_DAT_THCMPRANGE_MASK (0x30000U) -#define ADC_DAT_THCMPRANGE_SHIFT (16U) -#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK) -#define ADC_DAT_THCMPCROSS_MASK (0xC0000U) -#define ADC_DAT_THCMPCROSS_SHIFT (18U) -#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK) -#define ADC_DAT_CHANNEL_MASK (0x3C000000U) -#define ADC_DAT_CHANNEL_SHIFT (26U) -#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK) -#define ADC_DAT_OVERRUN_MASK (0x40000000U) -#define ADC_DAT_OVERRUN_SHIFT (30U) -#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK) -#define ADC_DAT_DATAVALID_MASK (0x80000000U) -#define ADC_DAT_DATAVALID_SHIFT (31U) -#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK) -/*! @} */ - -/* The count of ADC_DAT */ -#define ADC_DAT_COUNT (12U) - -/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ -/*! @{ */ -#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U) -#define ADC_THR0_LOW_THRLOW_SHIFT (4U) -#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK) -/*! @} */ - -/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ -/*! @{ */ -#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U) -#define ADC_THR1_LOW_THRLOW_SHIFT (4U) -#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK) -/*! @} */ - -/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ -/*! @{ */ -#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U) -#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U) -#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK) -/*! @} */ - -/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ -/*! @{ */ -#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U) -#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U) -#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK) -/*! @} */ - -/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */ -/*! @{ */ -#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U) -#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U) -#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U) -#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U) -#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U) -#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U) -#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U) -#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U) -#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U) -#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U) -#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U) -#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U) -#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U) -#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U) -#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U) -#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U) -#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U) -#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U) -#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U) -#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U) -#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U) -#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U) -#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U) -#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U) -#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK) -/*! @} */ - -/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */ -/*! @{ */ -#define ADC_INTEN_SEQA_INTEN_MASK (0x1U) -#define ADC_INTEN_SEQA_INTEN_SHIFT (0U) -#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK) -#define ADC_INTEN_SEQB_INTEN_MASK (0x2U) -#define ADC_INTEN_SEQB_INTEN_SHIFT (1U) -#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK) -#define ADC_INTEN_OVR_INTEN_MASK (0x4U) -#define ADC_INTEN_OVR_INTEN_SHIFT (2U) -#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK) -#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U) -#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U) -#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK) -#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U) -#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U) -#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK) -#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U) -#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U) -#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK) -#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U) -#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U) -#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK) -#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U) -#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U) -#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK) -#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U) -#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U) -#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK) -#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U) -#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U) -#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK) -#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U) -#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U) -#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK) -#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U) -#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U) -#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK) -#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U) -#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U) -#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK) -#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U) -#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U) -#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK) -#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U) -#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U) -#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK) -/*! @} */ - -/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */ -/*! @{ */ -#define ADC_FLAGS_THCMP0_MASK (0x1U) -#define ADC_FLAGS_THCMP0_SHIFT (0U) -#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK) -#define ADC_FLAGS_THCMP1_MASK (0x2U) -#define ADC_FLAGS_THCMP1_SHIFT (1U) -#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK) -#define ADC_FLAGS_THCMP2_MASK (0x4U) -#define ADC_FLAGS_THCMP2_SHIFT (2U) -#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK) -#define ADC_FLAGS_THCMP3_MASK (0x8U) -#define ADC_FLAGS_THCMP3_SHIFT (3U) -#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK) -#define ADC_FLAGS_THCMP4_MASK (0x10U) -#define ADC_FLAGS_THCMP4_SHIFT (4U) -#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK) -#define ADC_FLAGS_THCMP5_MASK (0x20U) -#define ADC_FLAGS_THCMP5_SHIFT (5U) -#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK) -#define ADC_FLAGS_THCMP6_MASK (0x40U) -#define ADC_FLAGS_THCMP6_SHIFT (6U) -#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK) -#define ADC_FLAGS_THCMP7_MASK (0x80U) -#define ADC_FLAGS_THCMP7_SHIFT (7U) -#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK) -#define ADC_FLAGS_THCMP8_MASK (0x100U) -#define ADC_FLAGS_THCMP8_SHIFT (8U) -#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK) -#define ADC_FLAGS_THCMP9_MASK (0x200U) -#define ADC_FLAGS_THCMP9_SHIFT (9U) -#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK) -#define ADC_FLAGS_THCMP10_MASK (0x400U) -#define ADC_FLAGS_THCMP10_SHIFT (10U) -#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK) -#define ADC_FLAGS_THCMP11_MASK (0x800U) -#define ADC_FLAGS_THCMP11_SHIFT (11U) -#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK) -#define ADC_FLAGS_OVERRUN0_MASK (0x1000U) -#define ADC_FLAGS_OVERRUN0_SHIFT (12U) -#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK) -#define ADC_FLAGS_OVERRUN1_MASK (0x2000U) -#define ADC_FLAGS_OVERRUN1_SHIFT (13U) -#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK) -#define ADC_FLAGS_OVERRUN2_MASK (0x4000U) -#define ADC_FLAGS_OVERRUN2_SHIFT (14U) -#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK) -#define ADC_FLAGS_OVERRUN3_MASK (0x8000U) -#define ADC_FLAGS_OVERRUN3_SHIFT (15U) -#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK) -#define ADC_FLAGS_OVERRUN4_MASK (0x10000U) -#define ADC_FLAGS_OVERRUN4_SHIFT (16U) -#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK) -#define ADC_FLAGS_OVERRUN5_MASK (0x20000U) -#define ADC_FLAGS_OVERRUN5_SHIFT (17U) -#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK) -#define ADC_FLAGS_OVERRUN6_MASK (0x40000U) -#define ADC_FLAGS_OVERRUN6_SHIFT (18U) -#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK) -#define ADC_FLAGS_OVERRUN7_MASK (0x80000U) -#define ADC_FLAGS_OVERRUN7_SHIFT (19U) -#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK) -#define ADC_FLAGS_OVERRUN8_MASK (0x100000U) -#define ADC_FLAGS_OVERRUN8_SHIFT (20U) -#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK) -#define ADC_FLAGS_OVERRUN9_MASK (0x200000U) -#define ADC_FLAGS_OVERRUN9_SHIFT (21U) -#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK) -#define ADC_FLAGS_OVERRUN10_MASK (0x400000U) -#define ADC_FLAGS_OVERRUN10_SHIFT (22U) -#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK) -#define ADC_FLAGS_OVERRUN11_MASK (0x800000U) -#define ADC_FLAGS_OVERRUN11_SHIFT (23U) -#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK) -#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U) -#define ADC_FLAGS_SEQA_OVR_SHIFT (24U) -#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK) -#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U) -#define ADC_FLAGS_SEQB_OVR_SHIFT (25U) -#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK) -#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U) -#define ADC_FLAGS_SEQA_INT_SHIFT (28U) -#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK) -#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U) -#define ADC_FLAGS_SEQB_INT_SHIFT (29U) -#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK) -#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U) -#define ADC_FLAGS_THCMP_INT_SHIFT (30U) -#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK) -#define ADC_FLAGS_OVR_INT_MASK (0x80000000U) -#define ADC_FLAGS_OVR_INT_SHIFT (31U) -#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK) -/*! @} */ - -/*! @name STARTUP - ADC Startup register. */ -/*! @{ */ -#define ADC_STARTUP_ADC_ENA_MASK (0x1U) -#define ADC_STARTUP_ADC_ENA_SHIFT (0U) -#define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK) -#define ADC_STARTUP_ADC_INIT_MASK (0x2U) -#define ADC_STARTUP_ADC_INIT_SHIFT (1U) -#define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK) -/*! @} */ - -/*! @name CALIB - ADC Calibration register. */ -/*! @{ */ -#define ADC_CALIB_CALIB_MASK (0x1U) -#define ADC_CALIB_CALIB_SHIFT (0U) -#define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK) -#define ADC_CALIB_CALREQD_MASK (0x2U) -#define ADC_CALIB_CALREQD_SHIFT (1U) -#define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK) -#define ADC_CALIB_CALVALUE_MASK (0x1FCU) -#define ADC_CALIB_CALVALUE_SHIFT (2U) -#define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ADC_Register_Masks */ - - -/* ADC - Peripheral instance base addresses */ -/** Peripheral ADC0 base address */ -#define ADC0_BASE (0x400A0000u) -/** Peripheral ADC0 base pointer */ -#define ADC0 ((ADC_Type *)ADC0_BASE) -/** Array initializer of ADC peripheral base addresses */ -#define ADC_BASE_ADDRS { ADC0_BASE } -/** Array initializer of ADC peripheral base pointers */ -#define ADC_BASE_PTRS { ADC0 } -/** Interrupt vectors for the ADC peripheral type */ -#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn } -#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn } - -/*! - * @} - */ /* end of group ADC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ASYNC_SYSCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer - * @{ - */ - -/** ASYNC_SYSCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */ - __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */ - __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */ - __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */ - __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */ - uint8_t RESERVED_1[4]; - __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */ -} ASYNC_SYSCON_Type; - -/* ---------------------------------------------------------------------------- - -- ASYNC_SYSCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks - * @{ - */ - -/*! @name ASYNCPRESETCTRL - Async peripheral reset control */ -/*! @{ */ -#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U) -#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U) -#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK) -#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U) -#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U) -#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK) -/*! @} */ - -/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */ -/*! @{ */ -#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU) -#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U) -#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK) -/*! @} */ - -/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */ -/*! @{ */ -#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU) -#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U) -#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK) -/*! @} */ - -/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */ -/*! @{ */ -#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK) -/*! @} */ - -/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */ -/*! @{ */ -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK) -/*! @} */ - -/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */ -/*! @{ */ -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK) -/*! @} */ - -/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */ -/*! @{ */ -#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U) -#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U) -#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ASYNC_SYSCON_Register_Masks */ - - -/* ASYNC_SYSCON - Peripheral instance base addresses */ -/** Peripheral ASYNC_SYSCON base address */ -#define ASYNC_SYSCON_BASE (0x40040000u) -/** Peripheral ASYNC_SYSCON base pointer */ -#define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE) -/** Array initializer of ASYNC_SYSCON peripheral base addresses */ -#define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE } -/** Array initializer of ASYNC_SYSCON peripheral base pointers */ -#define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON } - -/*! - * @} - */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CRC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer - * @{ - */ - -/** CRC - Register Layout Typedef */ -typedef struct { - __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ - __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ - union { /* offset: 0x8 */ - __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ - __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ - }; -} CRC_Type; - -/* ---------------------------------------------------------------------------- - -- CRC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Register_Masks CRC Register Masks - * @{ - */ - -/*! @name MODE - CRC mode register */ -/*! @{ */ -#define CRC_MODE_CRC_POLY_MASK (0x3U) -#define CRC_MODE_CRC_POLY_SHIFT (0U) -#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) -#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) -#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) -#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) -#define CRC_MODE_CMPL_WR_MASK (0x8U) -#define CRC_MODE_CMPL_WR_SHIFT (3U) -#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) -#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) -#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) -#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) -#define CRC_MODE_CMPL_SUM_MASK (0x20U) -#define CRC_MODE_CMPL_SUM_SHIFT (5U) -#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) -/*! @} */ - -/*! @name SEED - CRC seed register */ -/*! @{ */ -#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) -#define CRC_SEED_CRC_SEED_SHIFT (0U) -#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) -/*! @} */ - -/*! @name SUM - CRC checksum register */ -/*! @{ */ -#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) -#define CRC_SUM_CRC_SUM_SHIFT (0U) -#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) -/*! @} */ - -/*! @name WR_DATA - CRC data register */ -/*! @{ */ -#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) -#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) -#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CRC_Register_Masks */ - - -/* CRC - Peripheral instance base addresses */ -/** Peripheral CRC_ENGINE base address */ -#define CRC_ENGINE_BASE (0x40095000u) -/** Peripheral CRC_ENGINE base pointer */ -#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) -/** Array initializer of CRC peripheral base addresses */ -#define CRC_BASE_ADDRS { CRC_ENGINE_BASE } -/** Array initializer of CRC peripheral base pointers */ -#define CRC_BASE_PTRS { CRC_ENGINE } - -/*! - * @} - */ /* end of group CRC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CTIMER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer - * @{ - */ - -/** CTIMER - Register Layout Typedef */ -typedef struct { - __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ - __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ - __IO uint32_t TC; /**< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR., offset: 0x8 */ - __IO uint32_t PR; /**< Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC., offset: 0xC */ - __IO uint32_t PC; /**< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface., offset: 0x10 */ - __IO uint32_t MCR; /**< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs., offset: 0x14 */ - __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ - __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ - __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ - __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ - uint8_t RESERVED_0[48]; - __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ - __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */ -} CTIMER_Type; - -/* ---------------------------------------------------------------------------- - -- CTIMER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Register_Masks CTIMER Register Masks - * @{ - */ - -/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ -/*! @{ */ -#define CTIMER_IR_MR0INT_MASK (0x1U) -#define CTIMER_IR_MR0INT_SHIFT (0U) -#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) -#define CTIMER_IR_MR1INT_MASK (0x2U) -#define CTIMER_IR_MR1INT_SHIFT (1U) -#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) -#define CTIMER_IR_MR2INT_MASK (0x4U) -#define CTIMER_IR_MR2INT_SHIFT (2U) -#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) -#define CTIMER_IR_MR3INT_MASK (0x8U) -#define CTIMER_IR_MR3INT_SHIFT (3U) -#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) -#define CTIMER_IR_CR0INT_MASK (0x10U) -#define CTIMER_IR_CR0INT_SHIFT (4U) -#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) -#define CTIMER_IR_CR1INT_MASK (0x20U) -#define CTIMER_IR_CR1INT_SHIFT (5U) -#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) -#define CTIMER_IR_CR2INT_MASK (0x40U) -#define CTIMER_IR_CR2INT_SHIFT (6U) -#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) -#define CTIMER_IR_CR3INT_MASK (0x80U) -#define CTIMER_IR_CR3INT_SHIFT (7U) -#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) -/*! @} */ - -/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ -/*! @{ */ -#define CTIMER_TCR_CEN_MASK (0x1U) -#define CTIMER_TCR_CEN_SHIFT (0U) -#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) -#define CTIMER_TCR_CRST_MASK (0x2U) -#define CTIMER_TCR_CRST_SHIFT (1U) -#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) -/*! @} */ - -/*! @name TC - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR. */ -/*! @{ */ -#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_TC_TCVAL_SHIFT (0U) -#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) -/*! @} */ - -/*! @name PR - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. */ -/*! @{ */ -#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PR_PRVAL_SHIFT (0U) -#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) -/*! @} */ - -/*! @name PC - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */ -/*! @{ */ -#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PC_PCVAL_SHIFT (0U) -#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) -/*! @} */ - -/*! @name MCR - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */ -/*! @{ */ -#define CTIMER_MCR_MR0I_MASK (0x1U) -#define CTIMER_MCR_MR0I_SHIFT (0U) -#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) -#define CTIMER_MCR_MR0R_MASK (0x2U) -#define CTIMER_MCR_MR0R_SHIFT (1U) -#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) -#define CTIMER_MCR_MR0S_MASK (0x4U) -#define CTIMER_MCR_MR0S_SHIFT (2U) -#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) -#define CTIMER_MCR_MR1I_MASK (0x8U) -#define CTIMER_MCR_MR1I_SHIFT (3U) -#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) -#define CTIMER_MCR_MR1R_MASK (0x10U) -#define CTIMER_MCR_MR1R_SHIFT (4U) -#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) -#define CTIMER_MCR_MR1S_MASK (0x20U) -#define CTIMER_MCR_MR1S_SHIFT (5U) -#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) -#define CTIMER_MCR_MR2I_MASK (0x40U) -#define CTIMER_MCR_MR2I_SHIFT (6U) -#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) -#define CTIMER_MCR_MR2R_MASK (0x80U) -#define CTIMER_MCR_MR2R_SHIFT (7U) -#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) -#define CTIMER_MCR_MR2S_MASK (0x100U) -#define CTIMER_MCR_MR2S_SHIFT (8U) -#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) -#define CTIMER_MCR_MR3I_MASK (0x200U) -#define CTIMER_MCR_MR3I_SHIFT (9U) -#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) -#define CTIMER_MCR_MR3R_MASK (0x400U) -#define CTIMER_MCR_MR3R_SHIFT (10U) -#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) -#define CTIMER_MCR_MR3S_MASK (0x800U) -#define CTIMER_MCR_MR3S_SHIFT (11U) -#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) -/*! @} */ - -/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ -/*! @{ */ -#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) -#define CTIMER_MR_MATCH_SHIFT (0U) -#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) -/*! @} */ - -/* The count of CTIMER_MR */ -#define CTIMER_MR_COUNT (4U) - -/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ -/*! @{ */ -#define CTIMER_CCR_CAP0RE_MASK (0x1U) -#define CTIMER_CCR_CAP0RE_SHIFT (0U) -#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) -#define CTIMER_CCR_CAP0FE_MASK (0x2U) -#define CTIMER_CCR_CAP0FE_SHIFT (1U) -#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) -#define CTIMER_CCR_CAP0I_MASK (0x4U) -#define CTIMER_CCR_CAP0I_SHIFT (2U) -#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) -#define CTIMER_CCR_CAP1RE_MASK (0x8U) -#define CTIMER_CCR_CAP1RE_SHIFT (3U) -#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) -#define CTIMER_CCR_CAP1FE_MASK (0x10U) -#define CTIMER_CCR_CAP1FE_SHIFT (4U) -#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) -#define CTIMER_CCR_CAP1I_MASK (0x20U) -#define CTIMER_CCR_CAP1I_SHIFT (5U) -#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) -#define CTIMER_CCR_CAP2RE_MASK (0x40U) -#define CTIMER_CCR_CAP2RE_SHIFT (6U) -#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) -#define CTIMER_CCR_CAP2FE_MASK (0x80U) -#define CTIMER_CCR_CAP2FE_SHIFT (7U) -#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) -#define CTIMER_CCR_CAP2I_MASK (0x100U) -#define CTIMER_CCR_CAP2I_SHIFT (8U) -#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) -#define CTIMER_CCR_CAP3RE_MASK (0x200U) -#define CTIMER_CCR_CAP3RE_SHIFT (9U) -#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) -#define CTIMER_CCR_CAP3FE_MASK (0x400U) -#define CTIMER_CCR_CAP3FE_SHIFT (10U) -#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) -#define CTIMER_CCR_CAP3I_MASK (0x800U) -#define CTIMER_CCR_CAP3I_SHIFT (11U) -#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) -/*! @} */ - -/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ -/*! @{ */ -#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) -#define CTIMER_CR_CAP_SHIFT (0U) -#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) -/*! @} */ - -/* The count of CTIMER_CR */ -#define CTIMER_CR_COUNT (4U) - -/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ -/*! @{ */ -#define CTIMER_EMR_EM0_MASK (0x1U) -#define CTIMER_EMR_EM0_SHIFT (0U) -#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) -#define CTIMER_EMR_EM1_MASK (0x2U) -#define CTIMER_EMR_EM1_SHIFT (1U) -#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) -#define CTIMER_EMR_EM2_MASK (0x4U) -#define CTIMER_EMR_EM2_SHIFT (2U) -#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) -#define CTIMER_EMR_EM3_MASK (0x8U) -#define CTIMER_EMR_EM3_SHIFT (3U) -#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) -#define CTIMER_EMR_EMC0_MASK (0x30U) -#define CTIMER_EMR_EMC0_SHIFT (4U) -#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) -#define CTIMER_EMR_EMC1_MASK (0xC0U) -#define CTIMER_EMR_EMC1_SHIFT (6U) -#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) -#define CTIMER_EMR_EMC2_MASK (0x300U) -#define CTIMER_EMR_EMC2_SHIFT (8U) -#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) -#define CTIMER_EMR_EMC3_MASK (0xC00U) -#define CTIMER_EMR_EMC3_SHIFT (10U) -#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) -/*! @} */ - -/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ -/*! @{ */ -#define CTIMER_CTCR_CTMODE_MASK (0x3U) -#define CTIMER_CTCR_CTMODE_SHIFT (0U) -#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) -#define CTIMER_CTCR_CINSEL_MASK (0xCU) -#define CTIMER_CTCR_CINSEL_SHIFT (2U) -#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) -#define CTIMER_CTCR_ENCC_MASK (0x10U) -#define CTIMER_CTCR_ENCC_SHIFT (4U) -#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) -#define CTIMER_CTCR_SELCC_MASK (0xE0U) -#define CTIMER_CTCR_SELCC_SHIFT (5U) -#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) -/*! @} */ - -/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */ -/*! @{ */ -#define CTIMER_PWMC_PWMEN0_MASK (0x1U) -#define CTIMER_PWMC_PWMEN0_SHIFT (0U) -#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) -#define CTIMER_PWMC_PWMEN1_MASK (0x2U) -#define CTIMER_PWMC_PWMEN1_SHIFT (1U) -#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) -#define CTIMER_PWMC_PWMEN2_MASK (0x4U) -#define CTIMER_PWMC_PWMEN2_SHIFT (2U) -#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) -#define CTIMER_PWMC_PWMEN3_MASK (0x8U) -#define CTIMER_PWMC_PWMEN3_SHIFT (3U) -#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CTIMER_Register_Masks */ - - -/* CTIMER - Peripheral instance base addresses */ -/** Peripheral CTIMER0 base address */ -#define CTIMER0_BASE (0x40008000u) -/** Peripheral CTIMER0 base pointer */ -#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) -/** Peripheral CTIMER1 base address */ -#define CTIMER1_BASE (0x40009000u) -/** Peripheral CTIMER1 base pointer */ -#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) -/** Peripheral CTIMER2 base address */ -#define CTIMER2_BASE (0x40028000u) -/** Peripheral CTIMER2 base pointer */ -#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) -/** Peripheral CTIMER3 base address */ -#define CTIMER3_BASE (0x40048000u) -/** Peripheral CTIMER3 base pointer */ -#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) -/** Peripheral CTIMER4 base address */ -#define CTIMER4_BASE (0x40049000u) -/** Peripheral CTIMER4 base pointer */ -#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) -/** Array initializer of CTIMER peripheral base addresses */ -#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } -/** Array initializer of CTIMER peripheral base pointers */ -#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } -/** Interrupt vectors for the CTIMER peripheral type */ -#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, NotAvail_IRQn, CTIMER3_IRQn, NotAvail_IRQn } - -/*! - * @} - */ /* end of group CTIMER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer - * @{ - */ - -/** DMA - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ - __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ - __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ - uint8_t RESERVED_0[20]; - struct { /* offset: 0x20, array step: 0x5C */ - __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ - uint8_t RESERVED_0[4]; - __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ - uint8_t RESERVED_1[4]; - __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ - uint8_t RESERVED_2[4]; - __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ - uint8_t RESERVED_3[4]; - __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ - uint8_t RESERVED_4[4]; - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ - uint8_t RESERVED_5[4]; - __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ - uint8_t RESERVED_6[4]; - __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ - uint8_t RESERVED_7[4]; - __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ - uint8_t RESERVED_8[4]; - __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ - uint8_t RESERVED_9[4]; - __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ - uint8_t RESERVED_10[4]; - __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ - } COMMON[1]; - uint8_t RESERVED_1[900]; - struct { /* offset: 0x400, array step: 0x10 */ - __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ - __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ - __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } CHANNEL[20]; -} DMA_Type; - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/*! @name CTRL - DMA control. */ -/*! @{ */ -#define DMA_CTRL_ENABLE_MASK (0x1U) -#define DMA_CTRL_ENABLE_SHIFT (0U) -#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status. */ -/*! @{ */ -#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) -#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) -#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) -#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) -#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) -#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) -/*! @} */ - -/*! @name SRAMBASE - SRAM address of the channel configuration table. */ -/*! @{ */ -#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) -#define DMA_SRAMBASE_OFFSET_SHIFT (9U) -#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) -/*! @} */ - -/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) -#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLESET */ -#define DMA_COMMON_ENABLESET_COUNT (1U) - -/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) -#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLECLR */ -#define DMA_COMMON_ENABLECLR_COUNT (1U) - -/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) -#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ACTIVE */ -#define DMA_COMMON_ACTIVE_COUNT (1U) - -/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) -#define DMA_COMMON_BUSY_BSY_SHIFT (0U) -#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) -/*! @} */ - -/* The count of DMA_COMMON_BUSY */ -#define DMA_COMMON_BUSY_COUNT (1U) - -/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) -#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ERRINT */ -#define DMA_COMMON_ERRINT_COUNT (1U) - -/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) -#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENSET */ -#define DMA_COMMON_INTENSET_COUNT (1U) - -/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) -#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENCLR */ -#define DMA_COMMON_INTENCLR_COUNT (1U) - -/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTA_IA_SHIFT (0U) -#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTA */ -#define DMA_COMMON_INTA_COUNT (1U) - -/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTB_IB_SHIFT (0U) -#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTB */ -#define DMA_COMMON_INTB_COUNT (1U) - -/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETVALID_SV_SHIFT (0U) -#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETVALID */ -#define DMA_COMMON_SETVALID_COUNT (1U) - -/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) -#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETTRIG */ -#define DMA_COMMON_SETTRIG_COUNT (1U) - -/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) -#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ABORT */ -#define DMA_COMMON_ABORT_COUNT (1U) - -/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ -/*! @{ */ -#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) -#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) -#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) -#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) -#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) -#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) -#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) -#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) -#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) -#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) -#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) -#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) -#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) -#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) -#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) -#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) -#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) -#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) -#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) -#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) -#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) -#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) -#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CFG */ -#define DMA_CHANNEL_CFG_COUNT (20U) - -/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ -/*! @{ */ -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) -#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) -#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) -#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CTLSTAT */ -#define DMA_CHANNEL_CTLSTAT_COUNT (20U) - -/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ -/*! @{ */ -#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) -#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) -#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) -#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) -#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) -#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) -#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) -#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) -#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) -#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) -#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) -#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) -#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) -#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) -#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) -#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) -#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) -#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) -#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) -#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) -#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) -#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) -#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) -#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) -#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) -#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) -#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_XFERCFG */ -#define DMA_CHANNEL_XFERCFG_COUNT (20U) - - -/*! - * @} - */ /* end of group DMA_Register_Masks */ - - -/* DMA - Peripheral instance base addresses */ -/** Peripheral DMA0 base address */ -#define DMA0_BASE (0x40082000u) -/** Peripheral DMA0 base pointer */ -#define DMA0 ((DMA_Type *)DMA0_BASE) -/** Array initializer of DMA peripheral base addresses */ -#define DMA_BASE_ADDRS { DMA0_BASE } -/** Array initializer of DMA peripheral base pointers */ -#define DMA_BASE_PTRS { DMA0 } -/** Interrupt vectors for the DMA peripheral type */ -#define DMA_IRQS { DMA0_IRQn } - -/*! - * @} - */ /* end of group DMA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMIC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer - * @{ - */ - -/** DMIC - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x100 */ - __IO uint32_t OSR; /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */ - __IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */ - __IO uint32_t PREAC2FSCOEF; /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */ - __IO uint32_t PREAC4FSCOEF; /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */ - __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */ - uint8_t RESERVED_0[108]; - __IO uint32_t FIFO_CTRL; /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */ - __IO uint32_t FIFO_STATUS; /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */ - __IO uint32_t FIFO_DATA; /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */ - __IO uint32_t PHY_CTRL; /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */ - __IO uint32_t DC_CTRL; /**< DC Control register 0, array offset: 0x90, array step: 0x100 */ - uint8_t RESERVED_1[108]; - } CHANNEL[2]; - uint8_t RESERVED_0[3328]; - __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ - uint8_t RESERVED_1[8]; - __IO uint32_t IOCFG; /**< I/O Configuration register, offset: 0xF0C */ - __IO uint32_t USE2FS; /**< Use 2FS register, offset: 0xF10 */ - uint8_t RESERVED_2[108]; - __IO uint32_t HWVADGAIN; /**< HWVAD input gain register, offset: 0xF80 */ - __IO uint32_t HWVADHPFS; /**< HWVAD filter control register, offset: 0xF84 */ - __IO uint32_t HWVADST10; /**< HWVAD control register, offset: 0xF88 */ - __IO uint32_t HWVADRSTT; /**< HWVAD filter reset register, offset: 0xF8C */ - __IO uint32_t HWVADTHGN; /**< HWVAD noise estimator gain register, offset: 0xF90 */ - __IO uint32_t HWVADTHGS; /**< HWVAD signal estimator gain register, offset: 0xF94 */ - __I uint32_t HWVADLOWZ; /**< HWVAD noise envelope estimator register, offset: 0xF98 */ - uint8_t RESERVED_3[96]; - __I uint32_t ID; /**< Module Identification register, offset: 0xFFC */ -} DMIC_Type; - -/* ---------------------------------------------------------------------------- - -- DMIC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMIC_Register_Masks DMIC Register Masks - * @{ - */ - -/*! @name CHANNEL_OSR - Oversample Rate register 0 */ -/*! @{ */ -#define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU) -#define DMIC_CHANNEL_OSR_OSR_SHIFT (0U) -#define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_OSR */ -#define DMIC_CHANNEL_OSR_COUNT (2U) - -/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */ -/*! @{ */ -#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU) -#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U) -#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_DIVHFCLK */ -#define DMIC_CHANNEL_DIVHFCLK_COUNT (2U) - -/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */ -/*! @{ */ -#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U) -#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U) -#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_PREAC2FSCOEF */ -#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U) - -/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */ -/*! @{ */ -#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U) -#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U) -#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_PREAC4FSCOEF */ -#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U) - -/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */ -/*! @{ */ -#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU) -#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U) -#define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_GAINSHIFT */ -#define DMIC_CHANNEL_GAINSHIFT_COUNT (2U) - -/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */ -/*! @{ */ -#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U) -#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U) -#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK) -#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U) -#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U) -#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK) -#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U) -#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U) -#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK) -#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U) -#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U) -#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK) -#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U) -#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U) -#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_FIFO_CTRL */ -#define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U) - -/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */ -/*! @{ */ -#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U) -#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U) -#define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK) -#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U) -#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U) -#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK) -#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U) -#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U) -#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_FIFO_STATUS */ -#define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U) - -/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */ -/*! @{ */ -#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU) -#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U) -#define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_FIFO_DATA */ -#define DMIC_CHANNEL_FIFO_DATA_COUNT (2U) - -/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */ -/*! @{ */ -#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U) -#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U) -#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK) -#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U) -#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U) -#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_PHY_CTRL */ -#define DMIC_CHANNEL_PHY_CTRL_COUNT (2U) - -/*! @name CHANNEL_DC_CTRL - DC Control register 0 */ -/*! @{ */ -#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U) -#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U) -#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK) -#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U) -#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U) -#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK) -#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U) -#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U) -#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_DC_CTRL */ -#define DMIC_CHANNEL_DC_CTRL_COUNT (2U) - -/*! @name CHANEN - Channel Enable register */ -/*! @{ */ -#define DMIC_CHANEN_EN_CH0_MASK (0x1U) -#define DMIC_CHANEN_EN_CH0_SHIFT (0U) -#define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK) -#define DMIC_CHANEN_EN_CH1_MASK (0x2U) -#define DMIC_CHANEN_EN_CH1_SHIFT (1U) -#define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK) -/*! @} */ - -/*! @name IOCFG - I/O Configuration register */ -/*! @{ */ -#define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U) -#define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U) -#define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK) -#define DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U) -#define DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U) -#define DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK) -#define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U) -#define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U) -#define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK) -/*! @} */ - -/*! @name USE2FS - Use 2FS register */ -/*! @{ */ -#define DMIC_USE2FS_USE2FS_MASK (0x1U) -#define DMIC_USE2FS_USE2FS_SHIFT (0U) -#define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK) -/*! @} */ - -/*! @name HWVADGAIN - HWVAD input gain register */ -/*! @{ */ -#define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU) -#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U) -#define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK) -/*! @} */ - -/*! @name HWVADHPFS - HWVAD filter control register */ -/*! @{ */ -#define DMIC_HWVADHPFS_HPFS_MASK (0x3U) -#define DMIC_HWVADHPFS_HPFS_SHIFT (0U) -#define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK) -/*! @} */ - -/*! @name HWVADST10 - HWVAD control register */ -/*! @{ */ -#define DMIC_HWVADST10_ST10_MASK (0x1U) -#define DMIC_HWVADST10_ST10_SHIFT (0U) -#define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK) -/*! @} */ - -/*! @name HWVADRSTT - HWVAD filter reset register */ -/*! @{ */ -#define DMIC_HWVADRSTT_RSTT_MASK (0x1U) -#define DMIC_HWVADRSTT_RSTT_SHIFT (0U) -#define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK) -/*! @} */ - -/*! @name HWVADTHGN - HWVAD noise estimator gain register */ -/*! @{ */ -#define DMIC_HWVADTHGN_THGN_MASK (0xFU) -#define DMIC_HWVADTHGN_THGN_SHIFT (0U) -#define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK) -/*! @} */ - -/*! @name HWVADTHGS - HWVAD signal estimator gain register */ -/*! @{ */ -#define DMIC_HWVADTHGS_THGS_MASK (0xFU) -#define DMIC_HWVADTHGS_THGS_SHIFT (0U) -#define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK) -/*! @} */ - -/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */ -/*! @{ */ -#define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU) -#define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U) -#define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK) -/*! @} */ - -/*! @name ID - Module Identification register */ -/*! @{ */ -#define DMIC_ID_ID_MASK (0xFFFFFFFFU) -#define DMIC_ID_ID_SHIFT (0U) -#define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group DMIC_Register_Masks */ - - -/* DMIC - Peripheral instance base addresses */ -/** Peripheral DMIC0 base address */ -#define DMIC0_BASE (0x40090000u) -/** Peripheral DMIC0 base pointer */ -#define DMIC0 ((DMIC_Type *)DMIC0_BASE) -/** Array initializer of DMIC peripheral base addresses */ -#define DMIC_BASE_ADDRS { DMIC0_BASE } -/** Array initializer of DMIC peripheral base pointers */ -#define DMIC_BASE_PTRS { DMIC0 } -/** Interrupt vectors for the DMIC peripheral type */ -#define DMIC_IRQS { DMIC0_IRQn } -#define DMIC_HWVAD_IRQS { HWVAD0_IRQn } - -/*! - * @} - */ /* end of group DMIC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer - * @{ - */ - -/** FLEXCOMM - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4088]; - __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ - __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ -} FLEXCOMM_Type; - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks - * @{ - */ - -/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ -/*! @{ */ -#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) -#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) -#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) -#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) -#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) -#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) -#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) -#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) -#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) -#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) -#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) -#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) -#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) -#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) -#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) -#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) -#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) -#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) -#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) -#define FLEXCOMM_PSELID_ID_SHIFT (12U) -#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) -/*! @} */ - -/*! @name PID - Peripheral identification register. */ -/*! @{ */ -#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) -#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) -#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) -#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U) -#define FLEXCOMM_PID_Major_Rev_SHIFT (12U) -#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK) -#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) -#define FLEXCOMM_PID_ID_SHIFT (16U) -#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLEXCOMM_Register_Masks */ - - -/* FLEXCOMM - Peripheral instance base addresses */ -/** Peripheral FLEXCOMM0 base address */ -#define FLEXCOMM0_BASE (0x40086000u) -/** Peripheral FLEXCOMM0 base pointer */ -#define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) -/** Peripheral FLEXCOMM1 base address */ -#define FLEXCOMM1_BASE (0x40087000u) -/** Peripheral FLEXCOMM1 base pointer */ -#define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) -/** Peripheral FLEXCOMM2 base address */ -#define FLEXCOMM2_BASE (0x40088000u) -/** Peripheral FLEXCOMM2 base pointer */ -#define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) -/** Peripheral FLEXCOMM3 base address */ -#define FLEXCOMM3_BASE (0x40089000u) -/** Peripheral FLEXCOMM3 base pointer */ -#define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) -/** Peripheral FLEXCOMM4 base address */ -#define FLEXCOMM4_BASE (0x4008A000u) -/** Peripheral FLEXCOMM4 base pointer */ -#define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) -/** Peripheral FLEXCOMM5 base address */ -#define FLEXCOMM5_BASE (0x40096000u) -/** Peripheral FLEXCOMM5 base pointer */ -#define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) -/** Peripheral FLEXCOMM6 base address */ -#define FLEXCOMM6_BASE (0x40097000u) -/** Peripheral FLEXCOMM6 base pointer */ -#define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) -/** Peripheral FLEXCOMM7 base address */ -#define FLEXCOMM7_BASE (0x40098000u) -/** Peripheral FLEXCOMM7 base pointer */ -#define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) -/** Array initializer of FLEXCOMM peripheral base addresses */ -#define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE } -/** Array initializer of FLEXCOMM peripheral base pointers */ -#define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7 } -/** Interrupt vectors for the FLEXCOMM peripheral type */ -#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer - * @{ - */ - -/** GINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ - uint8_t RESERVED_0[28]; - __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[24]; - __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ -} GINT_Type; - -/* ---------------------------------------------------------------------------- - -- GINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Register_Masks GINT Register Masks - * @{ - */ - -/*! @name CTRL - GPIO grouped interrupt control register */ -/*! @{ */ -#define GINT_CTRL_INT_MASK (0x1U) -#define GINT_CTRL_INT_SHIFT (0U) -#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) -#define GINT_CTRL_COMB_MASK (0x2U) -#define GINT_CTRL_COMB_SHIFT (1U) -#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) -#define GINT_CTRL_TRIG_MASK (0x4U) -#define GINT_CTRL_TRIG_SHIFT (2U) -#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) -/*! @} */ - -/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ -/*! @{ */ -#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) -#define GINT_PORT_POL_POL_SHIFT (0U) -#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) -/*! @} */ - -/* The count of GINT_PORT_POL */ -#define GINT_PORT_POL_COUNT (2U) - -/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ -/*! @{ */ -#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) -#define GINT_PORT_ENA_ENA_SHIFT (0U) -#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) -/*! @} */ - -/* The count of GINT_PORT_ENA */ -#define GINT_PORT_ENA_COUNT (2U) - - -/*! - * @} - */ /* end of group GINT_Register_Masks */ - - -/* GINT - Peripheral instance base addresses */ -/** Peripheral GINT0 base address */ -#define GINT0_BASE (0x40002000u) -/** Peripheral GINT0 base pointer */ -#define GINT0 ((GINT_Type *)GINT0_BASE) -/** Peripheral GINT1 base address */ -#define GINT1_BASE (0x40003000u) -/** Peripheral GINT1 base pointer */ -#define GINT1 ((GINT_Type *)GINT1_BASE) -/** Array initializer of GINT peripheral base addresses */ -#define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } -/** Array initializer of GINT peripheral base pointers */ -#define GINT_BASE_PTRS { GINT0, GINT1 } -/** Interrupt vectors for the GINT peripheral type */ -#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } - -/*! - * @} - */ /* end of group GINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer - * @{ - */ - -/** GPIO - Register Layout Typedef */ -typedef struct { - __IO uint8_t B[2][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ - uint8_t RESERVED_0[4032]; - __IO uint32_t W[2][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ - uint8_t RESERVED_1[3840]; - __IO uint32_t DIR[2]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */ - uint8_t RESERVED_2[120]; - __IO uint32_t MASK[2]; /**< Mask register, array offset: 0x2080, array step: 0x4 */ - uint8_t RESERVED_3[120]; - __IO uint32_t PIN[2]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */ - uint8_t RESERVED_4[120]; - __IO uint32_t MPIN[2]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */ - uint8_t RESERVED_5[120]; - __IO uint32_t SET[2]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */ - uint8_t RESERVED_6[120]; - __O uint32_t CLR[2]; /**< Clear port, array offset: 0x2280, array step: 0x4 */ - uint8_t RESERVED_7[120]; - __O uint32_t NOT[2]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */ - uint8_t RESERVED_8[120]; - __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ - uint8_t RESERVED_9[120]; - __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ - uint8_t RESERVED_10[120]; - __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ -} GPIO_Type; - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */ -/*! @{ */ -#define GPIO_B_PBYTE_MASK (0x1U) -#define GPIO_B_PBYTE_SHIFT (0U) -#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) -/*! @} */ - -/* The count of GPIO_B */ -#define GPIO_B_COUNT (2U) - -/* The count of GPIO_B */ -#define GPIO_B_COUNT2 (32U) - -/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */ -/*! @{ */ -#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) -#define GPIO_W_PWORD_SHIFT (0U) -#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) -/*! @} */ - -/* The count of GPIO_W */ -#define GPIO_W_COUNT (2U) - -/* The count of GPIO_W */ -#define GPIO_W_COUNT2 (32U) - -/*! @name DIR - Direction registers */ -/*! @{ */ -#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) -#define GPIO_DIR_DIRP_SHIFT (0U) -#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) -/*! @} */ - -/* The count of GPIO_DIR */ -#define GPIO_DIR_COUNT (2U) - -/*! @name MASK - Mask register */ -/*! @{ */ -#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) -#define GPIO_MASK_MASKP_SHIFT (0U) -#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) -/*! @} */ - -/* The count of GPIO_MASK */ -#define GPIO_MASK_COUNT (2U) - -/*! @name PIN - Port pin register */ -/*! @{ */ -#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) -#define GPIO_PIN_PORT_SHIFT (0U) -#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) -/*! @} */ - -/* The count of GPIO_PIN */ -#define GPIO_PIN_COUNT (2U) - -/*! @name MPIN - Masked port register */ -/*! @{ */ -#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) -#define GPIO_MPIN_MPORTP_SHIFT (0U) -#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) -/*! @} */ - -/* The count of GPIO_MPIN */ -#define GPIO_MPIN_COUNT (2U) - -/*! @name SET - Write: Set register for port Read: output bits for port */ -/*! @{ */ -#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) -#define GPIO_SET_SETP_SHIFT (0U) -#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) -/*! @} */ - -/* The count of GPIO_SET */ -#define GPIO_SET_COUNT (2U) - -/*! @name CLR - Clear port */ -/*! @{ */ -#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) -#define GPIO_CLR_CLRP_SHIFT (0U) -#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) -/*! @} */ - -/* The count of GPIO_CLR */ -#define GPIO_CLR_COUNT (2U) - -/*! @name NOT - Toggle port */ -/*! @{ */ -#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) -#define GPIO_NOT_NOTP_SHIFT (0U) -#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) -/*! @} */ - -/* The count of GPIO_NOT */ -#define GPIO_NOT_COUNT (2U) - -/*! @name DIRSET - Set pin direction bits for port */ -/*! @{ */ -#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU) -#define GPIO_DIRSET_DIRSETP_SHIFT (0U) -#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) -/*! @} */ - -/* The count of GPIO_DIRSET */ -#define GPIO_DIRSET_COUNT (2U) - -/*! @name DIRCLR - Clear pin direction bits for port */ -/*! @{ */ -#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU) -#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) -#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) -/*! @} */ - -/* The count of GPIO_DIRCLR */ -#define GPIO_DIRCLR_COUNT (2U) - -/*! @name DIRNOT - Toggle pin direction bits for port */ -/*! @{ */ -#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU) -#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) -#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) -/*! @} */ - -/* The count of GPIO_DIRNOT */ -#define GPIO_DIRNOT_COUNT (2U) - - -/*! - * @} - */ /* end of group GPIO_Register_Masks */ - - -/* GPIO - Peripheral instance base addresses */ -/** Peripheral GPIO base address */ -#define GPIO_BASE (0x4008C000u) -/** Peripheral GPIO base pointer */ -#define GPIO ((GPIO_Type *)GPIO_BASE) -/** Array initializer of GPIO peripheral base addresses */ -#define GPIO_BASE_ADDRS { GPIO_BASE } -/** Array initializer of GPIO peripheral base pointers */ -#define GPIO_BASE_PTRS { GPIO } - -/*! - * @} - */ /* end of group GPIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2C Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer - * @{ - */ - -/** I2C - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[2048]; - __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ - __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ - __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ - __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ - __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ - __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ - uint8_t RESERVED_1[4]; - __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ - __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ - __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ - uint8_t RESERVED_2[20]; - __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ - __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ - __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ - __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ - uint8_t RESERVED_3[36]; - __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ -} I2C_Type; - -/* ---------------------------------------------------------------------------- - -- I2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Register_Masks I2C Register Masks - * @{ - */ - -/*! @name CFG - Configuration for shared functions. */ -/*! @{ */ -#define I2C_CFG_MSTEN_MASK (0x1U) -#define I2C_CFG_MSTEN_SHIFT (0U) -#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) -#define I2C_CFG_SLVEN_MASK (0x2U) -#define I2C_CFG_SLVEN_SHIFT (1U) -#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) -#define I2C_CFG_MONEN_MASK (0x4U) -#define I2C_CFG_MONEN_SHIFT (2U) -#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) -#define I2C_CFG_TIMEOUTEN_MASK (0x8U) -#define I2C_CFG_TIMEOUTEN_SHIFT (3U) -#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) -#define I2C_CFG_MONCLKSTR_MASK (0x10U) -#define I2C_CFG_MONCLKSTR_SHIFT (4U) -#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) -#define I2C_CFG_HSCAPABLE_MASK (0x20U) -#define I2C_CFG_HSCAPABLE_SHIFT (5U) -#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) -/*! @} */ - -/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ -/*! @{ */ -#define I2C_STAT_MSTPENDING_MASK (0x1U) -#define I2C_STAT_MSTPENDING_SHIFT (0U) -#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) -#define I2C_STAT_MSTSTATE_MASK (0xEU) -#define I2C_STAT_MSTSTATE_SHIFT (1U) -#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) -#define I2C_STAT_MSTARBLOSS_MASK (0x10U) -#define I2C_STAT_MSTARBLOSS_SHIFT (4U) -#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) -#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) -#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) -#define I2C_STAT_SLVPENDING_MASK (0x100U) -#define I2C_STAT_SLVPENDING_SHIFT (8U) -#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) -#define I2C_STAT_SLVSTATE_MASK (0x600U) -#define I2C_STAT_SLVSTATE_SHIFT (9U) -#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) -#define I2C_STAT_SLVNOTSTR_MASK (0x800U) -#define I2C_STAT_SLVNOTSTR_SHIFT (11U) -#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) -#define I2C_STAT_SLVIDX_MASK (0x3000U) -#define I2C_STAT_SLVIDX_SHIFT (12U) -#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) -#define I2C_STAT_SLVSEL_MASK (0x4000U) -#define I2C_STAT_SLVSEL_SHIFT (14U) -#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) -#define I2C_STAT_SLVDESEL_MASK (0x8000U) -#define I2C_STAT_SLVDESEL_SHIFT (15U) -#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) -#define I2C_STAT_MONRDY_MASK (0x10000U) -#define I2C_STAT_MONRDY_SHIFT (16U) -#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) -#define I2C_STAT_MONOV_MASK (0x20000U) -#define I2C_STAT_MONOV_SHIFT (17U) -#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) -#define I2C_STAT_MONACTIVE_MASK (0x40000U) -#define I2C_STAT_MONACTIVE_SHIFT (18U) -#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) -#define I2C_STAT_MONIDLE_MASK (0x80000U) -#define I2C_STAT_MONIDLE_SHIFT (19U) -#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) -#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) -#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) -#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) -#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable Set and read register. */ -/*! @{ */ -#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) -#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) -#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) -#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) -#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) -#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) -#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) -#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) -#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) -#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) -#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) -#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) -#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) -#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) -#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) -#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) -#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) -#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) -#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) -#define I2C_INTENSET_MONRDYEN_SHIFT (16U) -#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) -#define I2C_INTENSET_MONOVEN_MASK (0x20000U) -#define I2C_INTENSET_MONOVEN_SHIFT (17U) -#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) -#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) -#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) -#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) -#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) -#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) -#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) -#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) -#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) -#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear register. */ -/*! @{ */ -#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) -#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) -#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) -#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) -#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) -#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) -#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) -#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) -#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) -#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) -#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) -#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) -#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) -#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) -#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) -#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) -#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) -#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) -#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) -#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) -#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) -#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) -#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) -#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) -#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) -#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) -#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) -#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) -#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) -#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) -#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) -#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) -#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) -/*! @} */ - -/*! @name TIMEOUT - Time-out value register. */ -/*! @{ */ -#define I2C_TIMEOUT_TOMIN_MASK (0xFU) -#define I2C_TIMEOUT_TOMIN_SHIFT (0U) -#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) -#define I2C_TIMEOUT_TO_MASK (0xFFF0U) -#define I2C_TIMEOUT_TO_SHIFT (4U) -#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) -/*! @} */ - -/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ -/*! @{ */ -#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) -#define I2C_CLKDIV_DIVVAL_SHIFT (0U) -#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ -/*! @{ */ -#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) -#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) -#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) -#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) -#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) -#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) -#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) -#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) -#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) -#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) -#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) -#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) -#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) -#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) -#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) -#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) -#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) -#define I2C_INTSTAT_MONRDY_MASK (0x10000U) -#define I2C_INTSTAT_MONRDY_SHIFT (16U) -#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) -#define I2C_INTSTAT_MONOV_MASK (0x20000U) -#define I2C_INTSTAT_MONOV_SHIFT (17U) -#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) -#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) -#define I2C_INTSTAT_MONIDLE_SHIFT (19U) -#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) -#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) -#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) -#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) -#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name MSTCTL - Master control register. */ -/*! @{ */ -#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) -#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) -#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) -#define I2C_MSTCTL_MSTSTART_MASK (0x2U) -#define I2C_MSTCTL_MSTSTART_SHIFT (1U) -#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) -#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) -#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) -#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) -#define I2C_MSTCTL_MSTDMA_MASK (0x8U) -#define I2C_MSTCTL_MSTDMA_SHIFT (3U) -#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) -/*! @} */ - -/*! @name MSTTIME - Master timing configuration. */ -/*! @{ */ -#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) -#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) -#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) -#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) -#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) -#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) -/*! @} */ - -/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ -/*! @{ */ -#define I2C_MSTDAT_DATA_MASK (0xFFU) -#define I2C_MSTDAT_DATA_SHIFT (0U) -#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVCTL - Slave control register. */ -/*! @{ */ -#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) -#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) -#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) -#define I2C_SLVCTL_SLVNACK_MASK (0x2U) -#define I2C_SLVCTL_SLVNACK_SHIFT (1U) -#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) -#define I2C_SLVCTL_SLVDMA_MASK (0x8U) -#define I2C_SLVCTL_SLVDMA_SHIFT (3U) -#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) -#define I2C_SLVCTL_AUTOACK_MASK (0x100U) -#define I2C_SLVCTL_AUTOACK_SHIFT (8U) -#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) -#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) -#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) -#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) -/*! @} */ - -/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ -/*! @{ */ -#define I2C_SLVDAT_DATA_MASK (0xFFU) -#define I2C_SLVDAT_DATA_SHIFT (0U) -#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVADR - Slave address register. */ -/*! @{ */ -#define I2C_SLVADR_SADISABLE_MASK (0x1U) -#define I2C_SLVADR_SADISABLE_SHIFT (0U) -#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) -#define I2C_SLVADR_SLVADR_MASK (0xFEU) -#define I2C_SLVADR_SLVADR_SHIFT (1U) -#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) -#define I2C_SLVADR_AUTONACK_MASK (0x8000U) -#define I2C_SLVADR_AUTONACK_SHIFT (15U) -#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) -/*! @} */ - -/* The count of I2C_SLVADR */ -#define I2C_SLVADR_COUNT (4U) - -/*! @name SLVQUAL0 - Slave Qualification for address 0. */ -/*! @{ */ -#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) -#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) -#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) -#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) -#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) -#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) -/*! @} */ - -/*! @name MONRXDAT - Monitor receiver data register. */ -/*! @{ */ -#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) -#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) -#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) -#define I2C_MONRXDAT_MONSTART_MASK (0x100U) -#define I2C_MONRXDAT_MONSTART_SHIFT (8U) -#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) -#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) -#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) -#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) -#define I2C_MONRXDAT_MONNACK_MASK (0x400U) -#define I2C_MONRXDAT_MONNACK_SHIFT (10U) -#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2C_Register_Masks */ - - -/* I2C - Peripheral instance base addresses */ -/** Peripheral I2C0 base address */ -#define I2C0_BASE (0x40086000u) -/** Peripheral I2C0 base pointer */ -#define I2C0 ((I2C_Type *)I2C0_BASE) -/** Peripheral I2C1 base address */ -#define I2C1_BASE (0x40087000u) -/** Peripheral I2C1 base pointer */ -#define I2C1 ((I2C_Type *)I2C1_BASE) -/** Peripheral I2C2 base address */ -#define I2C2_BASE (0x40088000u) -/** Peripheral I2C2 base pointer */ -#define I2C2 ((I2C_Type *)I2C2_BASE) -/** Peripheral I2C3 base address */ -#define I2C3_BASE (0x40089000u) -/** Peripheral I2C3 base pointer */ -#define I2C3 ((I2C_Type *)I2C3_BASE) -/** Peripheral I2C4 base address */ -#define I2C4_BASE (0x4008A000u) -/** Peripheral I2C4 base pointer */ -#define I2C4 ((I2C_Type *)I2C4_BASE) -/** Peripheral I2C5 base address */ -#define I2C5_BASE (0x40096000u) -/** Peripheral I2C5 base pointer */ -#define I2C5 ((I2C_Type *)I2C5_BASE) -/** Peripheral I2C6 base address */ -#define I2C6_BASE (0x40097000u) -/** Peripheral I2C6 base pointer */ -#define I2C6 ((I2C_Type *)I2C6_BASE) -/** Peripheral I2C7 base address */ -#define I2C7_BASE (0x40098000u) -/** Peripheral I2C7 base pointer */ -#define I2C7 ((I2C_Type *)I2C7_BASE) -/** Array initializer of I2C peripheral base addresses */ -#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } -/** Array initializer of I2C peripheral base pointers */ -#define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } -/** Interrupt vectors for the I2C peripheral type */ -#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2C_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2S Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer - * @{ - */ - -/** I2S - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[3072]; - __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ - __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ - __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ - uint8_t RESERVED_2[480]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ - uint8_t RESERVED_5[8]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ - uint8_t RESERVED_6[8]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ -} I2S_Type; - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ -/*! @{ */ -#define I2S_CFG1_MAINENABLE_MASK (0x1U) -#define I2S_CFG1_MAINENABLE_SHIFT (0U) -#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) -#define I2S_CFG1_DATAPAUSE_MASK (0x2U) -#define I2S_CFG1_DATAPAUSE_SHIFT (1U) -#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) -#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) -#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) -#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) -#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) -#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) -#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) -#define I2S_CFG1_MODE_MASK (0xC0U) -#define I2S_CFG1_MODE_SHIFT (6U) -#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) -#define I2S_CFG1_RIGHTLOW_MASK (0x100U) -#define I2S_CFG1_RIGHTLOW_SHIFT (8U) -#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) -#define I2S_CFG1_LEFTJUST_MASK (0x200U) -#define I2S_CFG1_LEFTJUST_SHIFT (9U) -#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) -#define I2S_CFG1_ONECHANNEL_MASK (0x400U) -#define I2S_CFG1_ONECHANNEL_SHIFT (10U) -#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) -#define I2S_CFG1_PDMDATA_MASK (0x800U) -#define I2S_CFG1_PDMDATA_SHIFT (11U) -#define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK) -#define I2S_CFG1_SCK_POL_MASK (0x1000U) -#define I2S_CFG1_SCK_POL_SHIFT (12U) -#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) -#define I2S_CFG1_WS_POL_MASK (0x2000U) -#define I2S_CFG1_WS_POL_SHIFT (13U) -#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) -#define I2S_CFG1_DATALEN_MASK (0x1F0000U) -#define I2S_CFG1_DATALEN_SHIFT (16U) -#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) -/*! @} */ - -/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ -/*! @{ */ -#define I2S_CFG2_FRAMELEN_MASK (0x1FFU) -#define I2S_CFG2_FRAMELEN_SHIFT (0U) -#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) -#define I2S_CFG2_POSITION_MASK (0x1FF0000U) -#define I2S_CFG2_POSITION_SHIFT (16U) -#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) -/*! @} */ - -/*! @name STAT - Status register for the primary channel pair. */ -/*! @{ */ -#define I2S_STAT_BUSY_MASK (0x1U) -#define I2S_STAT_BUSY_SHIFT (0U) -#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) -#define I2S_STAT_SLVFRMERR_MASK (0x2U) -#define I2S_STAT_SLVFRMERR_SHIFT (1U) -#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) -#define I2S_STAT_LR_MASK (0x4U) -#define I2S_STAT_LR_SHIFT (2U) -#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) -#define I2S_STAT_DATAPAUSED_MASK (0x8U) -#define I2S_STAT_DATAPAUSED_SHIFT (3U) -#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) -/*! @} */ - -/*! @name DIV - Clock divider, used by all channel pairs. */ -/*! @{ */ -#define I2S_DIV_DIV_MASK (0xFFFU) -#define I2S_DIV_DIV_SHIFT (0U) -#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ -#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) -#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) -#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) -#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) -#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) -#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) -#define I2S_FIFOCFG_TXI2SSE0_MASK (0x4U) -#define I2S_FIFOCFG_TXI2SSE0_SHIFT (2U) -#define I2S_FIFOCFG_TXI2SSE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SSE0_SHIFT)) & I2S_FIFOCFG_TXI2SSE0_MASK) -#define I2S_FIFOCFG_PACK48_MASK (0x8U) -#define I2S_FIFOCFG_PACK48_SHIFT (3U) -#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) -#define I2S_FIFOCFG_SIZE_MASK (0x30U) -#define I2S_FIFOCFG_SIZE_SHIFT (4U) -#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) -#define I2S_FIFOCFG_DMATX_MASK (0x1000U) -#define I2S_FIFOCFG_DMATX_SHIFT (12U) -#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) -#define I2S_FIFOCFG_DMARX_MASK (0x2000U) -#define I2S_FIFOCFG_DMARX_SHIFT (13U) -#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) -#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) -#define I2S_FIFOCFG_WAKETX_SHIFT (14U) -#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) -#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) -#define I2S_FIFOCFG_WAKERX_SHIFT (15U) -#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) -#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) -#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) -#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) -#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) -#define I2S_FIFOCFG_POPDBG_MASK (0x40000U) -#define I2S_FIFOCFG_POPDBG_SHIFT (18U) -#define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ -#define I2S_FIFOSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOSTAT_TXERR_SHIFT (0U) -#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) -#define I2S_FIFOSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOSTAT_RXERR_SHIFT (1U) -#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) -#define I2S_FIFOSTAT_PERINT_MASK (0x8U) -#define I2S_FIFOSTAT_PERINT_SHIFT (3U) -#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) -#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) -#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) -#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) -#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) -#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) -#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) -#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) -#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) -#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) -#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) -#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) -#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ -#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) -#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) -#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) -#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) -#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) -#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) -#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) -#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) -#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ -#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) -#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) -#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) -#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) -#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) -#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) -#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) -#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) -#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) -#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ -#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) -#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) -#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) -#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) -#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) -#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) -#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) -#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) -#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) -#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ -#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) -#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) -#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) -#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) -#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) -#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) -#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) -#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) -#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) -#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) -#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ -#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFOWR_TXDATA_SHIFT (0U) -#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ -#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) -#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) -#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ -#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORD_RXDATA_SHIFT (0U) -#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ -#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48H_RXDATA_SHIFT (0U) -#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ -#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) -#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ -#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) -#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2S_Register_Masks */ - - -/* I2S - Peripheral instance base addresses */ -/** Peripheral I2S0 base address */ -#define I2S0_BASE (0x40097000u) -/** Peripheral I2S0 base pointer */ -#define I2S0 ((I2S_Type *)I2S0_BASE) -/** Peripheral I2S1 base address */ -#define I2S1_BASE (0x40098000u) -/** Peripheral I2S1 base pointer */ -#define I2S1 ((I2S_Type *)I2S1_BASE) -/** Array initializer of I2S peripheral base addresses */ -#define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE } -/** Array initializer of I2S peripheral base pointers */ -#define I2S_BASE_PTRS { I2S0, I2S1 } -/** Interrupt vectors for the I2S peripheral type */ -#define I2S_IRQS { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2S_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer - * @{ - */ - -/** INPUTMUX - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[192]; - __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ - __IO uint32_t DMA_ITRIG_INMUX[22]; /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */ - uint8_t RESERVED_1[40]; - __IO uint32_t DMA_OTRIG_INMUX[4]; /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */ - uint8_t RESERVED_2[16]; - __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ - __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ -} INPUTMUX_Type; - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks - * @{ - */ - -/*! @name PINTSEL - Pin interrupt select register */ -/*! @{ */ -#define INPUTMUX_PINTSEL_INTPIN_MASK (0xFFU) -#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) -#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PINTSEL */ -#define INPUTMUX_PINTSEL_COUNT (8U) - -/*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */ -/*! @{ */ -#define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U) -#define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA_ITRIG_INMUX */ -#define INPUTMUX_DMA_ITRIG_INMUX_COUNT (22U) - -/*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */ -/*! @{ */ -#define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT (0U) -#define INPUTMUX_DMA_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA_OTRIG_INMUX */ -#define INPUTMUX_DMA_OTRIG_INMUX_COUNT (4U) - -/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ -/*! @{ */ -#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) -#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) -/*! @} */ - -/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ -/*! @{ */ -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) -#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group INPUTMUX_Register_Masks */ - - -/* INPUTMUX - Peripheral instance base addresses */ -/** Peripheral INPUTMUX base address */ -#define INPUTMUX_BASE (0x40005000u) -/** Peripheral INPUTMUX base pointer */ -#define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) -/** Array initializer of INPUTMUX peripheral base addresses */ -#define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } -/** Array initializer of INPUTMUX peripheral base pointers */ -#define INPUTMUX_BASE_PTRS { INPUTMUX } - -/*! - * @} - */ /* end of group INPUTMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- IOCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer - * @{ - */ - -/** IOCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ -} IOCON_Type; - -/* ---------------------------------------------------------------------------- - -- IOCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Register_Masks IOCON Register Masks - * @{ - */ - -/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ -/*! @{ */ -#define IOCON_PIO_FUNC_MASK (0x7U) -#define IOCON_PIO_FUNC_SHIFT (0U) -#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) -#define IOCON_PIO_MODE_MASK (0x18U) -#define IOCON_PIO_MODE_SHIFT (3U) -#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) -#define IOCON_PIO_I2CSLEW_MASK (0x20U) -#define IOCON_PIO_I2CSLEW_SHIFT (5U) -#define IOCON_PIO_I2CSLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK) -#define IOCON_PIO_INVERT_MASK (0x40U) -#define IOCON_PIO_INVERT_SHIFT (6U) -#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) -#define IOCON_PIO_DIGIMODE_MASK (0x80U) -#define IOCON_PIO_DIGIMODE_SHIFT (7U) -#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) -#define IOCON_PIO_FILTEROFF_MASK (0x100U) -#define IOCON_PIO_FILTEROFF_SHIFT (8U) -#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) -#define IOCON_PIO_I2CDRIVE_MASK (0x200U) -#define IOCON_PIO_I2CDRIVE_SHIFT (9U) -#define IOCON_PIO_I2CDRIVE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK) -#define IOCON_PIO_SLEW_MASK (0x200U) -#define IOCON_PIO_SLEW_SHIFT (9U) -#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) -#define IOCON_PIO_I2CFILTER_MASK (0x400U) -#define IOCON_PIO_I2CFILTER_SHIFT (10U) -#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) -#define IOCON_PIO_OD_MASK (0x400U) -#define IOCON_PIO_OD_SHIFT (10U) -#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) -/*! @} */ - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT (2U) - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT2 (32U) - - -/*! - * @} - */ /* end of group IOCON_Register_Masks */ - - -/* IOCON - Peripheral instance base addresses */ -/** Peripheral IOCON base address */ -#define IOCON_BASE (0x40001000u) -/** Peripheral IOCON base pointer */ -#define IOCON ((IOCON_Type *)IOCON_BASE) -/** Array initializer of IOCON peripheral base addresses */ -#define IOCON_BASE_ADDRS { IOCON_BASE } -/** Array initializer of IOCON peripheral base pointers */ -#define IOCON_BASE_PTRS { IOCON } - -/*! - * @} - */ /* end of group IOCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MAILBOX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer - * @{ - */ - -/** MAILBOX - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x10 */ - __IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */ - __O uint32_t IRQSET; /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */ - __O uint32_t IRQCLR; /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } MBOXIRQ[2]; - uint8_t RESERVED_0[216]; - __IO uint32_t MUTEX; /**< Mutual exclusion register[1], offset: 0xF8 */ -} MAILBOX_Type; - -/* ---------------------------------------------------------------------------- - -- MAILBOX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks - * @{ - */ - -/*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */ -/*! @{ */ -#define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) -#define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U) -#define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK) -/*! @} */ - -/* The count of MAILBOX_MBOXIRQ_IRQ */ -#define MAILBOX_MBOXIRQ_IRQ_COUNT (2U) - -/*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */ -/*! @{ */ -#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) -#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U) -#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK) -/*! @} */ - -/* The count of MAILBOX_MBOXIRQ_IRQSET */ -#define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U) - -/*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */ -/*! @{ */ -#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) -#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U) -#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK) -/*! @} */ - -/* The count of MAILBOX_MBOXIRQ_IRQCLR */ -#define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U) - -/*! @name MUTEX - Mutual exclusion register[1] */ -/*! @{ */ -#define MAILBOX_MUTEX_EX_MASK (0x1U) -#define MAILBOX_MUTEX_EX_SHIFT (0U) -#define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MAILBOX_Register_Masks */ - - -/* MAILBOX - Peripheral instance base addresses */ -/** Peripheral MAILBOX base address */ -#define MAILBOX_BASE (0x4008B000u) -/** Peripheral MAILBOX base pointer */ -#define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) -/** Array initializer of MAILBOX peripheral base addresses */ -#define MAILBOX_BASE_ADDRS { MAILBOX_BASE } -/** Array initializer of MAILBOX peripheral base pointers */ -#define MAILBOX_BASE_PTRS { MAILBOX } -/** Interrupt vectors for the MAILBOX peripheral type */ -#define MAILBOX_IRQS { MAILBOX_IRQn } - -/*! - * @} - */ /* end of group MAILBOX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MRT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer - * @{ - */ - -/** MRT - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x10 */ - __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ - __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ - __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ - __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ - } CHANNEL[4]; - uint8_t RESERVED_0[176]; - __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ - __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ - __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ -} MRT_Type; - -/* ---------------------------------------------------------------------------- - -- MRT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Register_Masks MRT Register Masks - * @{ - */ - -/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ -/*! @{ */ -#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) -#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) -#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) -#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) -#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_INTVAL */ -#define MRT_CHANNEL_INTVAL_COUNT (4U) - -/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ -/*! @{ */ -#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) -#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_TIMER */ -#define MRT_CHANNEL_TIMER_COUNT (4U) - -/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ -/*! @{ */ -#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) -#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) -#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) -#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) -#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) -#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_CTRL */ -#define MRT_CHANNEL_CTRL_COUNT (4U) - -/*! @name CHANNEL_STAT - MRT Status register. */ -/*! @{ */ -#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) -#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) -#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) -#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) -#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) -#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) -#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) -#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) -#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_STAT */ -#define MRT_CHANNEL_STAT_COUNT (4U) - -/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ -/*! @{ */ -#define MRT_MODCFG_NOC_MASK (0xFU) -#define MRT_MODCFG_NOC_SHIFT (0U) -#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) -#define MRT_MODCFG_NOB_MASK (0x1F0U) -#define MRT_MODCFG_NOB_SHIFT (4U) -#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) -#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) -#define MRT_MODCFG_MULTITASK_SHIFT (31U) -#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) -/*! @} */ - -/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ -/*! @{ */ -#define MRT_IDLE_CH_CHAN_MASK (0xF0U) -#define MRT_IDLE_CH_CHAN_SHIFT (4U) -#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) -/*! @} */ - -/*! @name IRQ_FLAG - Global interrupt flag register */ -/*! @{ */ -#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) -#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) -#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) -#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) -#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) -#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) -#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) -#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) -#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) -#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) -#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) -#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MRT_Register_Masks */ - - -/* MRT - Peripheral instance base addresses */ -/** Peripheral MRT0 base address */ -#define MRT0_BASE (0x4000D000u) -/** Peripheral MRT0 base pointer */ -#define MRT0 ((MRT_Type *)MRT0_BASE) -/** Array initializer of MRT peripheral base addresses */ -#define MRT_BASE_ADDRS { MRT0_BASE } -/** Array initializer of MRT peripheral base pointers */ -#define MRT_BASE_PTRS { MRT0 } -/** Interrupt vectors for the MRT peripheral type */ -#define MRT_IRQS { MRT0_IRQn } - -/*! - * @} - */ /* end of group MRT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer - * @{ - */ - -/** PINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ - __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ - __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ - __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ - __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ - __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ - __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ - __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ - __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ - __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ - __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ - __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ - __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ -} PINT_Type; - -/* ---------------------------------------------------------------------------- - -- PINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Register_Masks PINT Register Masks - * @{ - */ - -/*! @name ISEL - Pin Interrupt Mode register */ -/*! @{ */ -#define PINT_ISEL_PMODE_MASK (0xFFU) -#define PINT_ISEL_PMODE_SHIFT (0U) -#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) -/*! @} */ - -/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ -/*! @{ */ -#define PINT_IENR_ENRL_MASK (0xFFU) -#define PINT_IENR_ENRL_SHIFT (0U) -#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) -/*! @} */ - -/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ -/*! @{ */ -#define PINT_SIENR_SETENRL_MASK (0xFFU) -#define PINT_SIENR_SETENRL_SHIFT (0U) -#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) -/*! @} */ - -/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ -/*! @{ */ -#define PINT_CIENR_CENRL_MASK (0xFFU) -#define PINT_CIENR_CENRL_SHIFT (0U) -#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) -/*! @} */ - -/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ -/*! @{ */ -#define PINT_IENF_ENAF_MASK (0xFFU) -#define PINT_IENF_ENAF_SHIFT (0U) -#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) -/*! @} */ - -/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ -/*! @{ */ -#define PINT_SIENF_SETENAF_MASK (0xFFU) -#define PINT_SIENF_SETENAF_SHIFT (0U) -#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) -/*! @} */ - -/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ -/*! @{ */ -#define PINT_CIENF_CENAF_MASK (0xFFU) -#define PINT_CIENF_CENAF_SHIFT (0U) -#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) -/*! @} */ - -/*! @name RISE - Pin interrupt rising edge register */ -/*! @{ */ -#define PINT_RISE_RDET_MASK (0xFFU) -#define PINT_RISE_RDET_SHIFT (0U) -#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) -/*! @} */ - -/*! @name FALL - Pin interrupt falling edge register */ -/*! @{ */ -#define PINT_FALL_FDET_MASK (0xFFU) -#define PINT_FALL_FDET_SHIFT (0U) -#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) -/*! @} */ - -/*! @name IST - Pin interrupt status register */ -/*! @{ */ -#define PINT_IST_PSTAT_MASK (0xFFU) -#define PINT_IST_PSTAT_SHIFT (0U) -#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) -/*! @} */ - -/*! @name PMCTRL - Pattern match interrupt control register */ -/*! @{ */ -#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) -#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) -#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) -#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) -#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) -#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) -#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) -#define PINT_PMCTRL_PMAT_SHIFT (24U) -#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) -/*! @} */ - -/*! @name PMSRC - Pattern match interrupt bit-slice source register */ -/*! @{ */ -#define PINT_PMSRC_SRC0_MASK (0x700U) -#define PINT_PMSRC_SRC0_SHIFT (8U) -#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) -#define PINT_PMSRC_SRC1_MASK (0x3800U) -#define PINT_PMSRC_SRC1_SHIFT (11U) -#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) -#define PINT_PMSRC_SRC2_MASK (0x1C000U) -#define PINT_PMSRC_SRC2_SHIFT (14U) -#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) -#define PINT_PMSRC_SRC3_MASK (0xE0000U) -#define PINT_PMSRC_SRC3_SHIFT (17U) -#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) -#define PINT_PMSRC_SRC4_MASK (0x700000U) -#define PINT_PMSRC_SRC4_SHIFT (20U) -#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) -#define PINT_PMSRC_SRC5_MASK (0x3800000U) -#define PINT_PMSRC_SRC5_SHIFT (23U) -#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) -#define PINT_PMSRC_SRC6_MASK (0x1C000000U) -#define PINT_PMSRC_SRC6_SHIFT (26U) -#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) -#define PINT_PMSRC_SRC7_MASK (0xE0000000U) -#define PINT_PMSRC_SRC7_SHIFT (29U) -#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) -/*! @} */ - -/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ -/*! @{ */ -#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) -#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) -#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) -#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) -#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) -#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) -#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) -#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) -#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) -#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) -#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) -#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) -#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) -#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) -#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) -#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) -#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) -#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) -#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) -#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) -#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) -#define PINT_PMCFG_CFG0_MASK (0x700U) -#define PINT_PMCFG_CFG0_SHIFT (8U) -#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) -#define PINT_PMCFG_CFG1_MASK (0x3800U) -#define PINT_PMCFG_CFG1_SHIFT (11U) -#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) -#define PINT_PMCFG_CFG2_MASK (0x1C000U) -#define PINT_PMCFG_CFG2_SHIFT (14U) -#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) -#define PINT_PMCFG_CFG3_MASK (0xE0000U) -#define PINT_PMCFG_CFG3_SHIFT (17U) -#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) -#define PINT_PMCFG_CFG4_MASK (0x700000U) -#define PINT_PMCFG_CFG4_SHIFT (20U) -#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) -#define PINT_PMCFG_CFG5_MASK (0x3800000U) -#define PINT_PMCFG_CFG5_SHIFT (23U) -#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) -#define PINT_PMCFG_CFG6_MASK (0x1C000000U) -#define PINT_PMCFG_CFG6_SHIFT (26U) -#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) -#define PINT_PMCFG_CFG7_MASK (0xE0000000U) -#define PINT_PMCFG_CFG7_SHIFT (29U) -#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PINT_Register_Masks */ - - -/* PINT - Peripheral instance base addresses */ -/** Peripheral PINT base address */ -#define PINT_BASE (0x40004000u) -/** Peripheral PINT base pointer */ -#define PINT ((PINT_Type *)PINT_BASE) -/** Array initializer of PINT peripheral base addresses */ -#define PINT_BASE_ADDRS { PINT_BASE } -/** Array initializer of PINT peripheral base pointers */ -#define PINT_BASE_PTRS { PINT } -/** Interrupt vectors for the PINT peripheral type */ -#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn } - -/*! - * @} - */ /* end of group PINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RTC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer - * @{ - */ - -/** RTC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ - __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ - __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ - __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ -} RTC_Type; - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/*! @name CTRL - RTC control register */ -/*! @{ */ -#define RTC_CTRL_SWRESET_MASK (0x1U) -#define RTC_CTRL_SWRESET_SHIFT (0U) -#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) -#define RTC_CTRL_ALARM1HZ_MASK (0x4U) -#define RTC_CTRL_ALARM1HZ_SHIFT (2U) -#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) -#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) -#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) -#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) -#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) -#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) -#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) -#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) -#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) -#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) -#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) -#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) -#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) -#define RTC_CTRL_RTC_EN_MASK (0x80U) -#define RTC_CTRL_RTC_EN_SHIFT (7U) -#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) -#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) -#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) -#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) -#define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) -#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) -#define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) -/*! @} */ - -/*! @name MATCH - RTC match register */ -/*! @{ */ -#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) -#define RTC_MATCH_MATVAL_SHIFT (0U) -#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) -/*! @} */ - -/*! @name COUNT - RTC counter register */ -/*! @{ */ -#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) -#define RTC_COUNT_VAL_SHIFT (0U) -#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) -/*! @} */ - -/*! @name WAKE - High-resolution/wake-up timer control register */ -/*! @{ */ -#define RTC_WAKE_VAL_MASK (0xFFFFU) -#define RTC_WAKE_VAL_SHIFT (0U) -#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group RTC_Register_Masks */ - - -/* RTC - Peripheral instance base addresses */ -/** Peripheral RTC base address */ -#define RTC_BASE (0x4002C000u) -/** Peripheral RTC base pointer */ -#define RTC ((RTC_Type *)RTC_BASE) -/** Array initializer of RTC peripheral base addresses */ -#define RTC_BASE_ADDRS { RTC_BASE } -/** Array initializer of RTC peripheral base pointers */ -#define RTC_BASE_PTRS { RTC } -/** Interrupt vectors for the RTC peripheral type */ -#define RTC_IRQS { RTC_IRQn } - -/*! - * @} - */ /* end of group RTC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SCT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer - * @{ - */ - -/** SCT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ - __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ - __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ - __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ - __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ - __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ - uint8_t RESERVED_0[40]; - __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ - __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ - __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ - __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ - __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ - __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ - __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ - __IO uint32_t DMA0REQUEST; /**< SCT DMA request 0 register, offset: 0x5C */ - __IO uint32_t DMA1REQUEST; /**< SCT DMA request 1 register, offset: 0x60 */ - uint8_t RESERVED_1[140]; - __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ - __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ - __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ - __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ - union { /* offset: 0x100 */ - __IO uint32_t SCTCAP[10]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ - __IO uint32_t SCTMATCH[10]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ - }; - uint8_t RESERVED_2[216]; - union { /* offset: 0x200 */ - __IO uint32_t SCTCAPCTRL[10]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ - __IO uint32_t SCTMATCHREL[10]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ - }; - uint8_t RESERVED_3[216]; - struct { /* offset: 0x300, array step: 0x8 */ - __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ - __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ - } EVENT[10]; - uint8_t RESERVED_4[432]; - struct { /* offset: 0x500, array step: 0x8 */ - __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ - __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ - } OUT[8]; - uint8_t RESERVED_5[700]; - uint32_t MODULECONTENT; /**< Reserved, offset: 0x7FC */ -} SCT_Type; - -/* ---------------------------------------------------------------------------- - -- SCT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Register_Masks SCT Register Masks - * @{ - */ - -/*! @name CONFIG - SCT configuration register */ -/*! @{ */ -#define SCT_CONFIG_UNIFY_MASK (0x1U) -#define SCT_CONFIG_UNIFY_SHIFT (0U) -#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) -#define SCT_CONFIG_CLKMODE_MASK (0x6U) -#define SCT_CONFIG_CLKMODE_SHIFT (1U) -#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) -#define SCT_CONFIG_CKSEL_MASK (0x78U) -#define SCT_CONFIG_CKSEL_SHIFT (3U) -#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) -#define SCT_CONFIG_NORELAOD_L_MASK (0x80U) -#define SCT_CONFIG_NORELAOD_L_SHIFT (7U) -#define SCT_CONFIG_NORELAOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK) -#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) -#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) -#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) -#define SCT_CONFIG_INSYNC_MASK (0x1E00U) -#define SCT_CONFIG_INSYNC_SHIFT (9U) -#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) -#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) -#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) -#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) -#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) -#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) -#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) -/*! @} */ - -/*! @name CTRL - SCT control register */ -/*! @{ */ -#define SCT_CTRL_DOWN_L_MASK (0x1U) -#define SCT_CTRL_DOWN_L_SHIFT (0U) -#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) -#define SCT_CTRL_STOP_L_MASK (0x2U) -#define SCT_CTRL_STOP_L_SHIFT (1U) -#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) -#define SCT_CTRL_HALT_L_MASK (0x4U) -#define SCT_CTRL_HALT_L_SHIFT (2U) -#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) -#define SCT_CTRL_CLRCTR_L_MASK (0x8U) -#define SCT_CTRL_CLRCTR_L_SHIFT (3U) -#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) -#define SCT_CTRL_BIDIR_L_MASK (0x10U) -#define SCT_CTRL_BIDIR_L_SHIFT (4U) -#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) -#define SCT_CTRL_PRE_L_MASK (0x1FE0U) -#define SCT_CTRL_PRE_L_SHIFT (5U) -#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) -#define SCT_CTRL_DOWN_H_MASK (0x10000U) -#define SCT_CTRL_DOWN_H_SHIFT (16U) -#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) -#define SCT_CTRL_STOP_H_MASK (0x20000U) -#define SCT_CTRL_STOP_H_SHIFT (17U) -#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) -#define SCT_CTRL_HALT_H_MASK (0x40000U) -#define SCT_CTRL_HALT_H_SHIFT (18U) -#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) -#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) -#define SCT_CTRL_CLRCTR_H_SHIFT (19U) -#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) -#define SCT_CTRL_BIDIR_H_MASK (0x100000U) -#define SCT_CTRL_BIDIR_H_SHIFT (20U) -#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) -#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) -#define SCT_CTRL_PRE_H_SHIFT (21U) -#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) -/*! @} */ - -/*! @name LIMIT - SCT limit event select register */ -/*! @{ */ -#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) -#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) -#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) -#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) -#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) -#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) -/*! @} */ - -/*! @name HALT - SCT halt event select register */ -/*! @{ */ -#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) -#define SCT_HALT_HALTMSK_L_SHIFT (0U) -#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) -#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) -#define SCT_HALT_HALTMSK_H_SHIFT (16U) -#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) -/*! @} */ - -/*! @name STOP - SCT stop event select register */ -/*! @{ */ -#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) -#define SCT_STOP_STOPMSK_L_SHIFT (0U) -#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) -#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) -#define SCT_STOP_STOPMSK_H_SHIFT (16U) -#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) -/*! @} */ - -/*! @name START - SCT start event select register */ -/*! @{ */ -#define SCT_START_STARTMSK_L_MASK (0xFFFFU) -#define SCT_START_STARTMSK_L_SHIFT (0U) -#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) -#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) -#define SCT_START_STARTMSK_H_SHIFT (16U) -#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) -/*! @} */ - -/*! @name COUNT - SCT counter register */ -/*! @{ */ -#define SCT_COUNT_CTR_L_MASK (0xFFFFU) -#define SCT_COUNT_CTR_L_SHIFT (0U) -#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) -#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) -#define SCT_COUNT_CTR_H_SHIFT (16U) -#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) -/*! @} */ - -/*! @name STATE - SCT state register */ -/*! @{ */ -#define SCT_STATE_STATE_L_MASK (0x1FU) -#define SCT_STATE_STATE_L_SHIFT (0U) -#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) -#define SCT_STATE_STATE_H_MASK (0x1F0000U) -#define SCT_STATE_STATE_H_SHIFT (16U) -#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) -/*! @} */ - -/*! @name INPUT - SCT input register */ -/*! @{ */ -#define SCT_INPUT_AIN0_MASK (0x1U) -#define SCT_INPUT_AIN0_SHIFT (0U) -#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) -#define SCT_INPUT_AIN1_MASK (0x2U) -#define SCT_INPUT_AIN1_SHIFT (1U) -#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) -#define SCT_INPUT_AIN2_MASK (0x4U) -#define SCT_INPUT_AIN2_SHIFT (2U) -#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) -#define SCT_INPUT_AIN3_MASK (0x8U) -#define SCT_INPUT_AIN3_SHIFT (3U) -#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) -#define SCT_INPUT_AIN4_MASK (0x10U) -#define SCT_INPUT_AIN4_SHIFT (4U) -#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) -#define SCT_INPUT_AIN5_MASK (0x20U) -#define SCT_INPUT_AIN5_SHIFT (5U) -#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) -#define SCT_INPUT_AIN6_MASK (0x40U) -#define SCT_INPUT_AIN6_SHIFT (6U) -#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) -#define SCT_INPUT_AIN7_MASK (0x80U) -#define SCT_INPUT_AIN7_SHIFT (7U) -#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) -#define SCT_INPUT_AIN8_MASK (0x100U) -#define SCT_INPUT_AIN8_SHIFT (8U) -#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) -#define SCT_INPUT_AIN9_MASK (0x200U) -#define SCT_INPUT_AIN9_SHIFT (9U) -#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) -#define SCT_INPUT_AIN10_MASK (0x400U) -#define SCT_INPUT_AIN10_SHIFT (10U) -#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) -#define SCT_INPUT_AIN11_MASK (0x800U) -#define SCT_INPUT_AIN11_SHIFT (11U) -#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) -#define SCT_INPUT_AIN12_MASK (0x1000U) -#define SCT_INPUT_AIN12_SHIFT (12U) -#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) -#define SCT_INPUT_AIN13_MASK (0x2000U) -#define SCT_INPUT_AIN13_SHIFT (13U) -#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) -#define SCT_INPUT_AIN14_MASK (0x4000U) -#define SCT_INPUT_AIN14_SHIFT (14U) -#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) -#define SCT_INPUT_AIN15_MASK (0x8000U) -#define SCT_INPUT_AIN15_SHIFT (15U) -#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) -#define SCT_INPUT_SIN0_MASK (0x10000U) -#define SCT_INPUT_SIN0_SHIFT (16U) -#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) -#define SCT_INPUT_SIN1_MASK (0x20000U) -#define SCT_INPUT_SIN1_SHIFT (17U) -#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) -#define SCT_INPUT_SIN2_MASK (0x40000U) -#define SCT_INPUT_SIN2_SHIFT (18U) -#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) -#define SCT_INPUT_SIN3_MASK (0x80000U) -#define SCT_INPUT_SIN3_SHIFT (19U) -#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) -#define SCT_INPUT_SIN4_MASK (0x100000U) -#define SCT_INPUT_SIN4_SHIFT (20U) -#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) -#define SCT_INPUT_SIN5_MASK (0x200000U) -#define SCT_INPUT_SIN5_SHIFT (21U) -#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) -#define SCT_INPUT_SIN6_MASK (0x400000U) -#define SCT_INPUT_SIN6_SHIFT (22U) -#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) -#define SCT_INPUT_SIN7_MASK (0x800000U) -#define SCT_INPUT_SIN7_SHIFT (23U) -#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) -#define SCT_INPUT_SIN8_MASK (0x1000000U) -#define SCT_INPUT_SIN8_SHIFT (24U) -#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) -#define SCT_INPUT_SIN9_MASK (0x2000000U) -#define SCT_INPUT_SIN9_SHIFT (25U) -#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) -#define SCT_INPUT_SIN10_MASK (0x4000000U) -#define SCT_INPUT_SIN10_SHIFT (26U) -#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) -#define SCT_INPUT_SIN11_MASK (0x8000000U) -#define SCT_INPUT_SIN11_SHIFT (27U) -#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) -#define SCT_INPUT_SIN12_MASK (0x10000000U) -#define SCT_INPUT_SIN12_SHIFT (28U) -#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) -#define SCT_INPUT_SIN13_MASK (0x20000000U) -#define SCT_INPUT_SIN13_SHIFT (29U) -#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) -#define SCT_INPUT_SIN14_MASK (0x40000000U) -#define SCT_INPUT_SIN14_SHIFT (30U) -#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) -#define SCT_INPUT_SIN15_MASK (0x80000000U) -#define SCT_INPUT_SIN15_SHIFT (31U) -#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) -/*! @} */ - -/*! @name REGMODE - SCT match/capture mode register */ -/*! @{ */ -#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) -#define SCT_REGMODE_REGMOD_L_SHIFT (0U) -#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) -#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) -#define SCT_REGMODE_REGMOD_H_SHIFT (16U) -#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) -/*! @} */ - -/*! @name OUTPUT - SCT output register */ -/*! @{ */ -#define SCT_OUTPUT_OUT_MASK (0xFFFFU) -#define SCT_OUTPUT_OUT_SHIFT (0U) -#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) -/*! @} */ - -/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ -/*! @{ */ -#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) -#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) -#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) -#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) -#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) -#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) -#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) -#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) -#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) -#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) -#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) -#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) -#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) -#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) -#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) -#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) -#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) -#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) -#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) -#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) -#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) -#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) -#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) -#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) -#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) -#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) -#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) -#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) -#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) -/*! @} */ - -/*! @name RES - SCT conflict resolution register */ -/*! @{ */ -#define SCT_RES_O0RES_MASK (0x3U) -#define SCT_RES_O0RES_SHIFT (0U) -#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) -#define SCT_RES_O1RES_MASK (0xCU) -#define SCT_RES_O1RES_SHIFT (2U) -#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) -#define SCT_RES_O2RES_MASK (0x30U) -#define SCT_RES_O2RES_SHIFT (4U) -#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) -#define SCT_RES_O3RES_MASK (0xC0U) -#define SCT_RES_O3RES_SHIFT (6U) -#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) -#define SCT_RES_O4RES_MASK (0x300U) -#define SCT_RES_O4RES_SHIFT (8U) -#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) -#define SCT_RES_O5RES_MASK (0xC00U) -#define SCT_RES_O5RES_SHIFT (10U) -#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) -#define SCT_RES_O6RES_MASK (0x3000U) -#define SCT_RES_O6RES_SHIFT (12U) -#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) -#define SCT_RES_O7RES_MASK (0xC000U) -#define SCT_RES_O7RES_SHIFT (14U) -#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) -#define SCT_RES_O8RES_MASK (0x30000U) -#define SCT_RES_O8RES_SHIFT (16U) -#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) -#define SCT_RES_O9RES_MASK (0xC0000U) -#define SCT_RES_O9RES_SHIFT (18U) -#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) -#define SCT_RES_O10RES_MASK (0x300000U) -#define SCT_RES_O10RES_SHIFT (20U) -#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) -#define SCT_RES_O11RES_MASK (0xC00000U) -#define SCT_RES_O11RES_SHIFT (22U) -#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) -#define SCT_RES_O12RES_MASK (0x3000000U) -#define SCT_RES_O12RES_SHIFT (24U) -#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) -#define SCT_RES_O13RES_MASK (0xC000000U) -#define SCT_RES_O13RES_SHIFT (26U) -#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) -#define SCT_RES_O14RES_MASK (0x30000000U) -#define SCT_RES_O14RES_SHIFT (28U) -#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) -#define SCT_RES_O15RES_MASK (0xC0000000U) -#define SCT_RES_O15RES_SHIFT (30U) -#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) -/*! @} */ - -/*! @name DMA0REQUEST - SCT DMA request 0 register */ -/*! @{ */ -#define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU) -#define SCT_DMA0REQUEST_DEV_0_SHIFT (0U) -#define SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK) -#define SCT_DMA0REQUEST_DRL0_MASK (0x40000000U) -#define SCT_DMA0REQUEST_DRL0_SHIFT (30U) -#define SCT_DMA0REQUEST_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK) -#define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U) -#define SCT_DMA0REQUEST_DRQ0_SHIFT (31U) -#define SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK) -/*! @} */ - -/*! @name DMA1REQUEST - SCT DMA request 1 register */ -/*! @{ */ -#define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU) -#define SCT_DMA1REQUEST_DEV_1_SHIFT (0U) -#define SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK) -#define SCT_DMA1REQUEST_DRL1_MASK (0x40000000U) -#define SCT_DMA1REQUEST_DRL1_SHIFT (30U) -#define SCT_DMA1REQUEST_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK) -#define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U) -#define SCT_DMA1REQUEST_DRQ1_SHIFT (31U) -#define SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK) -/*! @} */ - -/*! @name EVEN - SCT event interrupt enable register */ -/*! @{ */ -#define SCT_EVEN_IEN_MASK (0xFFFFU) -#define SCT_EVEN_IEN_SHIFT (0U) -#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) -/*! @} */ - -/*! @name EVFLAG - SCT event flag register */ -/*! @{ */ -#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) -#define SCT_EVFLAG_FLAG_SHIFT (0U) -#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) -/*! @} */ - -/*! @name CONEN - SCT conflict interrupt enable register */ -/*! @{ */ -#define SCT_CONEN_NCEN_MASK (0xFFFFU) -#define SCT_CONEN_NCEN_SHIFT (0U) -#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) -/*! @} */ - -/*! @name CONFLAG - SCT conflict flag register */ -/*! @{ */ -#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) -#define SCT_CONFLAG_NCFLAG_SHIFT (0U) -#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) -#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) -#define SCT_CONFLAG_BUSERRL_SHIFT (30U) -#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) -#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) -#define SCT_CONFLAG_BUSERRH_SHIFT (31U) -#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) -/*! @} */ - -/*! @name SCTCAP - SCT capture register of capture channel */ -/*! @{ */ -#define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU) -#define SCT_SCTCAP_CAPn_L_SHIFT (0U) -#define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK) -#define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U) -#define SCT_SCTCAP_CAPn_H_SHIFT (16U) -#define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK) -/*! @} */ - -/* The count of SCT_SCTCAP */ -#define SCT_SCTCAP_COUNT (10U) - -/*! @name SCTMATCH - SCT match value register of match channels */ -/*! @{ */ -#define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU) -#define SCT_SCTMATCH_MATCHn_L_SHIFT (0U) -#define SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK) -#define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U) -#define SCT_SCTMATCH_MATCHn_H_SHIFT (16U) -#define SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK) -/*! @} */ - -/* The count of SCT_SCTMATCH */ -#define SCT_SCTMATCH_COUNT (10U) - -/*! @name SCTCAPCTRL - SCT capture control register */ -/*! @{ */ -#define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU) -#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U) -#define SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK) -#define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) -#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U) -#define SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK) -/*! @} */ - -/* The count of SCT_SCTCAPCTRL */ -#define SCT_SCTCAPCTRL_COUNT (10U) - -/*! @name SCTMATCHREL - SCT match reload value register */ -/*! @{ */ -#define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU) -#define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U) -#define SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK) -#define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U) -#define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U) -#define SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK) -/*! @} */ - -/* The count of SCT_SCTMATCHREL */ -#define SCT_SCTMATCHREL_COUNT (10U) - -/*! @name EVENT_STATE - SCT event state register 0 */ -/*! @{ */ -#define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU) -#define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U) -#define SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK) -/*! @} */ - -/* The count of SCT_EVENT_STATE */ -#define SCT_EVENT_STATE_COUNT (10U) - -/*! @name EVENT_CTRL - SCT event control register 0 */ -/*! @{ */ -#define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU) -#define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U) -#define SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK) -#define SCT_EVENT_CTRL_HEVENT_MASK (0x10U) -#define SCT_EVENT_CTRL_HEVENT_SHIFT (4U) -#define SCT_EVENT_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK) -#define SCT_EVENT_CTRL_OUTSEL_MASK (0x20U) -#define SCT_EVENT_CTRL_OUTSEL_SHIFT (5U) -#define SCT_EVENT_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK) -#define SCT_EVENT_CTRL_IOSEL_MASK (0x3C0U) -#define SCT_EVENT_CTRL_IOSEL_SHIFT (6U) -#define SCT_EVENT_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK) -#define SCT_EVENT_CTRL_IOCOND_MASK (0xC00U) -#define SCT_EVENT_CTRL_IOCOND_SHIFT (10U) -#define SCT_EVENT_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK) -#define SCT_EVENT_CTRL_COMBMODE_MASK (0x3000U) -#define SCT_EVENT_CTRL_COMBMODE_SHIFT (12U) -#define SCT_EVENT_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK) -#define SCT_EVENT_CTRL_STATELD_MASK (0x4000U) -#define SCT_EVENT_CTRL_STATELD_SHIFT (14U) -#define SCT_EVENT_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK) -#define SCT_EVENT_CTRL_STATEV_MASK (0xF8000U) -#define SCT_EVENT_CTRL_STATEV_SHIFT (15U) -#define SCT_EVENT_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK) -#define SCT_EVENT_CTRL_MATCHMEM_MASK (0x100000U) -#define SCT_EVENT_CTRL_MATCHMEM_SHIFT (20U) -#define SCT_EVENT_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK) -#define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U) -#define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U) -#define SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK) -/*! @} */ - -/* The count of SCT_EVENT_CTRL */ -#define SCT_EVENT_CTRL_COUNT (10U) - -/*! @name OUT_SET - SCT output 0 set register */ -/*! @{ */ -#define SCT_OUT_SET_SET_MASK (0xFFFFU) -#define SCT_OUT_SET_SET_SHIFT (0U) -#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) -/*! @} */ - -/* The count of SCT_OUT_SET */ -#define SCT_OUT_SET_COUNT (8U) - -/*! @name OUT_CLR - SCT output 0 clear register */ -/*! @{ */ -#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) -#define SCT_OUT_CLR_CLR_SHIFT (0U) -#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) -/*! @} */ - -/* The count of SCT_OUT_CLR */ -#define SCT_OUT_CLR_COUNT (8U) - - -/*! - * @} - */ /* end of group SCT_Register_Masks */ - - -/* SCT - Peripheral instance base addresses */ -/** Peripheral SCT0 base address */ -#define SCT0_BASE (0x40085000u) -/** Peripheral SCT0 base pointer */ -#define SCT0 ((SCT_Type *)SCT0_BASE) -/** Array initializer of SCT peripheral base addresses */ -#define SCT_BASE_ADDRS { SCT0_BASE } -/** Array initializer of SCT peripheral base pointers */ -#define SCT_BASE_PTRS { SCT0 } -/** Interrupt vectors for the SCT peripheral type */ -#define SCT_IRQS { SCT0_IRQn } - -/*! - * @} - */ /* end of group SCT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer - * @{ - */ - -/** SPI - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[1024]; - __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ - __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ - __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ - __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ - __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ - __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ - uint8_t RESERVED_2[2516]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_6[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ -} SPI_Type; - -/* ---------------------------------------------------------------------------- - -- SPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Register_Masks SPI Register Masks - * @{ - */ - -/*! @name CFG - SPI Configuration register */ -/*! @{ */ -#define SPI_CFG_ENABLE_MASK (0x1U) -#define SPI_CFG_ENABLE_SHIFT (0U) -#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) -#define SPI_CFG_MASTER_MASK (0x4U) -#define SPI_CFG_MASTER_SHIFT (2U) -#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) -#define SPI_CFG_LSBF_MASK (0x8U) -#define SPI_CFG_LSBF_SHIFT (3U) -#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) -#define SPI_CFG_CPHA_MASK (0x10U) -#define SPI_CFG_CPHA_SHIFT (4U) -#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) -#define SPI_CFG_CPOL_MASK (0x20U) -#define SPI_CFG_CPOL_SHIFT (5U) -#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) -#define SPI_CFG_LOOP_MASK (0x80U) -#define SPI_CFG_LOOP_SHIFT (7U) -#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) -#define SPI_CFG_SPOL0_MASK (0x100U) -#define SPI_CFG_SPOL0_SHIFT (8U) -#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) -#define SPI_CFG_SPOL1_MASK (0x200U) -#define SPI_CFG_SPOL1_SHIFT (9U) -#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) -#define SPI_CFG_SPOL2_MASK (0x400U) -#define SPI_CFG_SPOL2_SHIFT (10U) -#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) -#define SPI_CFG_SPOL3_MASK (0x800U) -#define SPI_CFG_SPOL3_SHIFT (11U) -#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) -/*! @} */ - -/*! @name DLY - SPI Delay register */ -/*! @{ */ -#define SPI_DLY_PRE_DELAY_MASK (0xFU) -#define SPI_DLY_PRE_DELAY_SHIFT (0U) -#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) -#define SPI_DLY_POST_DELAY_MASK (0xF0U) -#define SPI_DLY_POST_DELAY_SHIFT (4U) -#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) -#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) -#define SPI_DLY_FRAME_DELAY_SHIFT (8U) -#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) -#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) -#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) -#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) -/*! @} */ - -/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ -/*! @{ */ -#define SPI_STAT_SSA_MASK (0x10U) -#define SPI_STAT_SSA_SHIFT (4U) -#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) -#define SPI_STAT_SSD_MASK (0x20U) -#define SPI_STAT_SSD_SHIFT (5U) -#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) -#define SPI_STAT_STALLED_MASK (0x40U) -#define SPI_STAT_STALLED_SHIFT (6U) -#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) -#define SPI_STAT_ENDTRANSFER_MASK (0x80U) -#define SPI_STAT_ENDTRANSFER_SHIFT (7U) -#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) -#define SPI_STAT_MSTIDLE_MASK (0x100U) -#define SPI_STAT_MSTIDLE_SHIFT (8U) -#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -/*! @{ */ -#define SPI_INTENSET_SSAEN_MASK (0x10U) -#define SPI_INTENSET_SSAEN_SHIFT (4U) -#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) -#define SPI_INTENSET_SSDEN_MASK (0x20U) -#define SPI_INTENSET_SSDEN_SHIFT (5U) -#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) -#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) -#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) -#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) -/*! @} */ - -/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ -/*! @{ */ -#define SPI_INTENCLR_SSAEN_MASK (0x10U) -#define SPI_INTENCLR_SSAEN_SHIFT (4U) -#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) -#define SPI_INTENCLR_SSDEN_MASK (0x20U) -#define SPI_INTENCLR_SSDEN_SHIFT (5U) -#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) -#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) -#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) -#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) -/*! @} */ - -/*! @name DIV - SPI clock Divider */ -/*! @{ */ -#define SPI_DIV_DIVVAL_MASK (0xFFFFU) -#define SPI_DIV_DIVVAL_SHIFT (0U) -#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - SPI Interrupt Status */ -/*! @{ */ -#define SPI_INTSTAT_SSA_MASK (0x10U) -#define SPI_INTSTAT_SSA_SHIFT (4U) -#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) -#define SPI_INTSTAT_SSD_MASK (0x20U) -#define SPI_INTSTAT_SSD_SHIFT (5U) -#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) -#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) -#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) -#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ -#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) -#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) -#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) -#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) -#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) -#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) -#define SPI_FIFOCFG_SIZE_MASK (0x30U) -#define SPI_FIFOCFG_SIZE_SHIFT (4U) -#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) -#define SPI_FIFOCFG_DMATX_MASK (0x1000U) -#define SPI_FIFOCFG_DMATX_SHIFT (12U) -#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) -#define SPI_FIFOCFG_DMARX_MASK (0x2000U) -#define SPI_FIFOCFG_DMARX_SHIFT (13U) -#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) -#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) -#define SPI_FIFOCFG_WAKETX_SHIFT (14U) -#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) -#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) -#define SPI_FIFOCFG_WAKERX_SHIFT (15U) -#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) -#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) -#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) -#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) -#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ -#define SPI_FIFOSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOSTAT_TXERR_SHIFT (0U) -#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) -#define SPI_FIFOSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOSTAT_RXERR_SHIFT (1U) -#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) -#define SPI_FIFOSTAT_PERINT_MASK (0x8U) -#define SPI_FIFOSTAT_PERINT_SHIFT (3U) -#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) -#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) -#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) -#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) -#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) -#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) -#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) -#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) -#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) -#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) -#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) -#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) -#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ -#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) -#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) -#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) -#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) -#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) -#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) -#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) -#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) -#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ -#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) -#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) -#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) -#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) -#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) -#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) -#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) -#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) -#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) -#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ -#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) -#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) -#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) -#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) -#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) -#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) -#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) -#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) -#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) -#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ -#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) -#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) -#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) -#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) -#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) -#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) -#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) -#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) -#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) -#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) -#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ -#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) -#define SPI_FIFOWR_TXDATA_SHIFT (0U) -#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) -#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) -#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) -#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) -#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) -#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) -#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) -#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) -#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) -#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) -#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) -#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) -#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) -#define SPI_FIFOWR_EOT_MASK (0x100000U) -#define SPI_FIFOWR_EOT_SHIFT (20U) -#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) -#define SPI_FIFOWR_EOF_MASK (0x200000U) -#define SPI_FIFOWR_EOF_SHIFT (21U) -#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) -#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) -#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) -#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) -#define SPI_FIFOWR_LEN_MASK (0xF000000U) -#define SPI_FIFOWR_LEN_SHIFT (24U) -#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ -#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORD_RXDATA_SHIFT (0U) -#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) -#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) -#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) -#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) -#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) -#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) -#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) -#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) -#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) -#define SPI_FIFORD_SOT_MASK (0x100000U) -#define SPI_FIFORD_SOT_SHIFT (20U) -#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ -#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) -#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) -#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) -#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) -#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) -#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) -#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) -#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) -#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) -#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) -#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) -#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) -#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SPI_Register_Masks */ - - -/* SPI - Peripheral instance base addresses */ -/** Peripheral SPI0 base address */ -#define SPI0_BASE (0x40086000u) -/** Peripheral SPI0 base pointer */ -#define SPI0 ((SPI_Type *)SPI0_BASE) -/** Peripheral SPI1 base address */ -#define SPI1_BASE (0x40087000u) -/** Peripheral SPI1 base pointer */ -#define SPI1 ((SPI_Type *)SPI1_BASE) -/** Peripheral SPI2 base address */ -#define SPI2_BASE (0x40088000u) -/** Peripheral SPI2 base pointer */ -#define SPI2 ((SPI_Type *)SPI2_BASE) -/** Peripheral SPI3 base address */ -#define SPI3_BASE (0x40089000u) -/** Peripheral SPI3 base pointer */ -#define SPI3 ((SPI_Type *)SPI3_BASE) -/** Peripheral SPI4 base address */ -#define SPI4_BASE (0x4008A000u) -/** Peripheral SPI4 base pointer */ -#define SPI4 ((SPI_Type *)SPI4_BASE) -/** Peripheral SPI5 base address */ -#define SPI5_BASE (0x40096000u) -/** Peripheral SPI5 base pointer */ -#define SPI5 ((SPI_Type *)SPI5_BASE) -/** Peripheral SPI6 base address */ -#define SPI6_BASE (0x40097000u) -/** Peripheral SPI6 base pointer */ -#define SPI6 ((SPI_Type *)SPI6_BASE) -/** Peripheral SPI7 base address */ -#define SPI7_BASE (0x40098000u) -/** Peripheral SPI7 base pointer */ -#define SPI7 ((SPI_Type *)SPI7_BASE) -/** Array initializer of SPI peripheral base addresses */ -#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE } -/** Array initializer of SPI peripheral base pointers */ -#define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7 } -/** Interrupt vectors for the SPI peripheral type */ -#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group SPI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPIFI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPIFI_Peripheral_Access_Layer SPIFI Peripheral Access Layer - * @{ - */ - -/** SPIFI - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< SPIFI control register, offset: 0x0 */ - __IO uint32_t CMD; /**< SPIFI command register, offset: 0x4 */ - __IO uint32_t ADDR; /**< SPIFI address register, offset: 0x8 */ - __IO uint32_t IDATA; /**< SPIFI intermediate data register, offset: 0xC */ - __IO uint32_t CLIMIT; /**< SPIFI limit register, offset: 0x10 */ - __IO uint32_t DATA; /**< SPIFI data register, offset: 0x14 */ - __IO uint32_t MCMD; /**< SPIFI memory command register, offset: 0x18 */ - __IO uint32_t STAT; /**< SPIFI status register, offset: 0x1C */ -} SPIFI_Type; - -/* ---------------------------------------------------------------------------- - -- SPIFI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPIFI_Register_Masks SPIFI Register Masks - * @{ - */ - -/*! @name CTRL - SPIFI control register */ -/*! @{ */ -#define SPIFI_CTRL_TIMEOUT_MASK (0xFFFFU) -#define SPIFI_CTRL_TIMEOUT_SHIFT (0U) -#define SPIFI_CTRL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK) -#define SPIFI_CTRL_CSHIGH_MASK (0xF0000U) -#define SPIFI_CTRL_CSHIGH_SHIFT (16U) -#define SPIFI_CTRL_CSHIGH(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK) -#define SPIFI_CTRL_D_PRFTCH_DIS_MASK (0x200000U) -#define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT (21U) -#define SPIFI_CTRL_D_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK) -#define SPIFI_CTRL_INTEN_MASK (0x400000U) -#define SPIFI_CTRL_INTEN_SHIFT (22U) -#define SPIFI_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK) -#define SPIFI_CTRL_MODE3_MASK (0x800000U) -#define SPIFI_CTRL_MODE3_SHIFT (23U) -#define SPIFI_CTRL_MODE3(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK) -#define SPIFI_CTRL_PRFTCH_DIS_MASK (0x8000000U) -#define SPIFI_CTRL_PRFTCH_DIS_SHIFT (27U) -#define SPIFI_CTRL_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK) -#define SPIFI_CTRL_DUAL_MASK (0x10000000U) -#define SPIFI_CTRL_DUAL_SHIFT (28U) -#define SPIFI_CTRL_DUAL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK) -#define SPIFI_CTRL_RFCLK_MASK (0x20000000U) -#define SPIFI_CTRL_RFCLK_SHIFT (29U) -#define SPIFI_CTRL_RFCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK) -#define SPIFI_CTRL_FBCLK_MASK (0x40000000U) -#define SPIFI_CTRL_FBCLK_SHIFT (30U) -#define SPIFI_CTRL_FBCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK) -#define SPIFI_CTRL_DMAEN_MASK (0x80000000U) -#define SPIFI_CTRL_DMAEN_SHIFT (31U) -#define SPIFI_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK) -/*! @} */ - -/*! @name CMD - SPIFI command register */ -/*! @{ */ -#define SPIFI_CMD_DATALEN_MASK (0x3FFFU) -#define SPIFI_CMD_DATALEN_SHIFT (0U) -#define SPIFI_CMD_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK) -#define SPIFI_CMD_POLL_MASK (0x4000U) -#define SPIFI_CMD_POLL_SHIFT (14U) -#define SPIFI_CMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK) -#define SPIFI_CMD_DOUT_MASK (0x8000U) -#define SPIFI_CMD_DOUT_SHIFT (15U) -#define SPIFI_CMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK) -#define SPIFI_CMD_INTLEN_MASK (0x70000U) -#define SPIFI_CMD_INTLEN_SHIFT (16U) -#define SPIFI_CMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK) -#define SPIFI_CMD_FIELDFORM_MASK (0x180000U) -#define SPIFI_CMD_FIELDFORM_SHIFT (19U) -#define SPIFI_CMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK) -#define SPIFI_CMD_FRAMEFORM_MASK (0xE00000U) -#define SPIFI_CMD_FRAMEFORM_SHIFT (21U) -#define SPIFI_CMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK) -#define SPIFI_CMD_OPCODE_MASK (0xFF000000U) -#define SPIFI_CMD_OPCODE_SHIFT (24U) -#define SPIFI_CMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK) -/*! @} */ - -/*! @name ADDR - SPIFI address register */ -/*! @{ */ -#define SPIFI_ADDR_ADDRESS_MASK (0xFFFFFFFFU) -#define SPIFI_ADDR_ADDRESS_SHIFT (0U) -#define SPIFI_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK) -/*! @} */ - -/*! @name IDATA - SPIFI intermediate data register */ -/*! @{ */ -#define SPIFI_IDATA_IDATA_MASK (0xFFFFFFFFU) -#define SPIFI_IDATA_IDATA_SHIFT (0U) -#define SPIFI_IDATA_IDATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK) -/*! @} */ - -/*! @name CLIMIT - SPIFI limit register */ -/*! @{ */ -#define SPIFI_CLIMIT_CLIMIT_MASK (0xFFFFFFFFU) -#define SPIFI_CLIMIT_CLIMIT_SHIFT (0U) -#define SPIFI_CLIMIT_CLIMIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK) -/*! @} */ - -/*! @name DATA - SPIFI data register */ -/*! @{ */ -#define SPIFI_DATA_DATA_MASK (0xFFFFFFFFU) -#define SPIFI_DATA_DATA_SHIFT (0U) -#define SPIFI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK) -/*! @} */ - -/*! @name MCMD - SPIFI memory command register */ -/*! @{ */ -#define SPIFI_MCMD_POLL_MASK (0x4000U) -#define SPIFI_MCMD_POLL_SHIFT (14U) -#define SPIFI_MCMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK) -#define SPIFI_MCMD_DOUT_MASK (0x8000U) -#define SPIFI_MCMD_DOUT_SHIFT (15U) -#define SPIFI_MCMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK) -#define SPIFI_MCMD_INTLEN_MASK (0x70000U) -#define SPIFI_MCMD_INTLEN_SHIFT (16U) -#define SPIFI_MCMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK) -#define SPIFI_MCMD_FIELDFORM_MASK (0x180000U) -#define SPIFI_MCMD_FIELDFORM_SHIFT (19U) -#define SPIFI_MCMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK) -#define SPIFI_MCMD_FRAMEFORM_MASK (0xE00000U) -#define SPIFI_MCMD_FRAMEFORM_SHIFT (21U) -#define SPIFI_MCMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK) -#define SPIFI_MCMD_OPCODE_MASK (0xFF000000U) -#define SPIFI_MCMD_OPCODE_SHIFT (24U) -#define SPIFI_MCMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK) -/*! @} */ - -/*! @name STAT - SPIFI status register */ -/*! @{ */ -#define SPIFI_STAT_MCINIT_MASK (0x1U) -#define SPIFI_STAT_MCINIT_SHIFT (0U) -#define SPIFI_STAT_MCINIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK) -#define SPIFI_STAT_CMD_MASK (0x2U) -#define SPIFI_STAT_CMD_SHIFT (1U) -#define SPIFI_STAT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK) -#define SPIFI_STAT_RESET_MASK (0x10U) -#define SPIFI_STAT_RESET_SHIFT (4U) -#define SPIFI_STAT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK) -#define SPIFI_STAT_INTRQ_MASK (0x20U) -#define SPIFI_STAT_INTRQ_SHIFT (5U) -#define SPIFI_STAT_INTRQ(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK) -#define SPIFI_STAT_VERSION_MASK (0xFF000000U) -#define SPIFI_STAT_VERSION_SHIFT (24U) -#define SPIFI_STAT_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_VERSION_SHIFT)) & SPIFI_STAT_VERSION_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SPIFI_Register_Masks */ - - -/* SPIFI - Peripheral instance base addresses */ -/** Peripheral SPIFI0 base address */ -#define SPIFI0_BASE (0x40080000u) -/** Peripheral SPIFI0 base pointer */ -#define SPIFI0 ((SPIFI_Type *)SPIFI0_BASE) -/** Array initializer of SPIFI peripheral base addresses */ -#define SPIFI_BASE_ADDRS { SPIFI0_BASE } -/** Array initializer of SPIFI peripheral base pointers */ -#define SPIFI_BASE_PTRS { SPIFI0 } - -/*! - * @} - */ /* end of group SPIFI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SYSCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer - * @{ - */ - -/** SYSCON - Register Layout Typedef */ -typedef struct { - uint32_t SYSMEMREMAP; /**< System Remap register, offset: 0x0 */ - uint8_t RESERVED_0[12]; - __IO uint32_t AHBMATPRIO; /**< AHB multilayer matrix priority control, offset: 0x10 */ - uint8_t RESERVED_1[44]; - __IO uint32_t SYSTCKCAL; /**< System tick counter calibration, offset: 0x40 */ - uint8_t RESERVED_2[4]; - __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ - __IO uint32_t ASYNCAPBCTRL; /**< Asynchronous APB Control, offset: 0x4C */ - uint8_t RESERVED_3[112]; - __I uint32_t PIOPORCAP[2]; /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */ - uint8_t RESERVED_4[8]; - __I uint32_t PIORESCAP[2]; /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */ - uint8_t RESERVED_5[40]; - __IO uint32_t PRESETCTRL[2]; /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */ - uint8_t RESERVED_6[24]; - __O uint32_t PRESETCTRLSET[2]; /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */ - uint8_t RESERVED_7[24]; - __O uint32_t PRESETCTRLCLR[2]; /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */ - uint8_t RESERVED_8[168]; - __IO uint32_t SYSRSTSTAT; /**< System reset status register, offset: 0x1F0 */ - uint8_t RESERVED_9[12]; - __IO uint32_t AHBCLKCTRL[2]; /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_10[24]; - __O uint32_t AHBCLKCTRLSET[2]; /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */ - uint8_t RESERVED_11[24]; - __O uint32_t AHBCLKCTRLCLR[2]; /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */ - uint8_t RESERVED_12[56]; - __IO uint32_t MAINCLKSELA; /**< Main clock source select A, offset: 0x280 */ - __IO uint32_t MAINCLKSELB; /**< Main clock source select B, offset: 0x284 */ - __IO uint32_t CLKOUTSELA; /**< CLKOUT clock source select A, offset: 0x288 */ - uint8_t RESERVED_13[4]; - __IO uint32_t SYSPLLCLKSEL; /**< PLL clock source select, offset: 0x290 */ - uint8_t RESERVED_14[12]; - __IO uint32_t SPIFICLKSEL; /**< SPIFI clock source select, offset: 0x2A0 */ - __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ - __IO uint32_t USBCLKSEL; /**< USB clock source select, offset: 0x2A8 */ - uint8_t RESERVED_15[4]; - __IO uint32_t FXCOMCLKSEL[8]; /**< Flexcomm 0 clock source select, array offset: 0x2B0, array step: 0x4 */ - uint8_t RESERVED_16[16]; - __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ - uint8_t RESERVED_17[4]; - __IO uint32_t FRGCLKSEL; /**< Fractional Rate Generator clock source select, offset: 0x2E8 */ - __IO uint32_t DMICCLKSEL; /**< Digital microphone (D-Mic) subsystem clock select, offset: 0x2EC */ - uint8_t RESERVED_18[16]; - __IO uint32_t SYSTICKCLKDIV; /**< SYSTICK clock divider, offset: 0x300 */ - __IO uint32_t TRACECLKDIV; /**< Trace clock divider, offset: 0x304 */ - uint8_t RESERVED_19[120]; - __IO uint32_t AHBCLKDIV; /**< AHB clock divider, offset: 0x380 */ - __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ - uint8_t RESERVED_20[8]; - __IO uint32_t SPIFICLKDIV; /**< SPIFI clock divider, offset: 0x390 */ - __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ - __IO uint32_t USBCLKDIV; /**< USB clock divider, offset: 0x398 */ - uint8_t RESERVED_21[4]; - __IO uint32_t FRGCTRL; /**< Fractional rate divider, offset: 0x3A0 */ - uint8_t RESERVED_22[4]; - __IO uint32_t DMICCLKDIV; /**< DMIC clock divider, offset: 0x3A8 */ - __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ - uint8_t RESERVED_23[80]; - __IO uint32_t FLASHCFG; /**< Flash wait states configuration, offset: 0x400 */ - uint8_t RESERVED_24[8]; - __IO uint32_t USBCLKCTRL; /**< USB clock control, offset: 0x40C */ - __IO uint32_t USBCLKSTAT; /**< USB clock status, offset: 0x410 */ - uint8_t RESERVED_25[4]; - __IO uint32_t FREQMECTRL; /**< Frequency measure register, offset: 0x418 */ - uint8_t RESERVED_26[4]; - __IO uint32_t MCLKIO; /**< MCLK input/output control, offset: 0x420 */ - uint8_t RESERVED_27[220]; - __IO uint32_t FROCTRL; /**< FRO oscillator control, offset: 0x500 */ - uint8_t RESERVED_28[4]; - __IO uint32_t WDTOSCCTRL; /**< Watchdog oscillator control, offset: 0x508 */ - __IO uint32_t RTCOSCCTRL; /**< RTC oscillator 32 kHz output control, offset: 0x50C */ - uint8_t RESERVED_29[112]; - __IO uint32_t SYSPLLCTRL; /**< PLL control, offset: 0x580 */ - __I uint32_t SYSPLLSTAT; /**< PLL status, offset: 0x584 */ - __IO uint32_t SYSPLLNDEC; /**< PLL N decoder, offset: 0x588 */ - __IO uint32_t SYSPLLPDEC; /**< PLL P decoder, offset: 0x58C */ - __IO uint32_t SYSPLLSSCTRL0; /**< PLL spread spectrum control 0, offset: 0x590 */ - __IO uint32_t SYSPLLSSCTRL1; /**< PLL spread spectrum control 1, offset: 0x594 */ - uint8_t RESERVED_30[104]; - __IO uint32_t PDSLEEPCFG[2]; /**< Sleep configuration register n, array offset: 0x600, array step: 0x4 */ - uint8_t RESERVED_31[8]; - __IO uint32_t PDRUNCFG[2]; /**< Power configuration register n, array offset: 0x610, array step: 0x4 */ - uint8_t RESERVED_32[8]; - __O uint32_t PDRUNCFGSET[2]; /**< Set bits in PDRUNCFGn, array offset: 0x620, array step: 0x4 */ - uint8_t RESERVED_33[8]; - __O uint32_t PDRUNCFGCLR[2]; /**< Clear bits in PDRUNCFGn, array offset: 0x630, array step: 0x4 */ - uint8_t RESERVED_34[72]; - __IO uint32_t STARTERP[2]; /**< Start logic n wake-up enable register, array offset: 0x680, array step: 0x4 */ - uint8_t RESERVED_35[24]; - __O uint32_t STARTERSET[2]; /**< Set bits in STARTERn, array offset: 0x6A0, array step: 0x4 */ - uint8_t RESERVED_36[24]; - __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTERn, array offset: 0x6C0, array step: 0x4 */ - uint8_t RESERVED_37[184]; - __IO uint32_t HWWAKE; /**< Configures special cases of hardware wake-up, offset: 0x780 */ - uint8_t RESERVED_38[124]; - __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ - __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ - __IO uint32_t CPSTACK; /**< Coprocessor Stack Address, offset: 0x808 */ - __I uint32_t CPSTAT; /**< Coprocessor Status, offset: 0x80C */ - uint8_t RESERVED_39[1524]; - __IO uint32_t AUTOCGOR; /**< Auto Clock-Gate Override Register, offset: 0xE04 */ - uint8_t RESERVED_40[492]; - __I uint32_t JTAGIDCODE; /**< JTAG ID code register, offset: 0xFF4 */ - __I uint32_t DEVICE_ID0; /**< Part ID register, offset: 0xFF8 */ - __I uint32_t DEVICE_ID1; /**< Boot ROM and die revision register, offset: 0xFFC */ - uint8_t RESERVED_41[127044]; - __IO uint32_t BODCTRL; /**< Brown-Out Detect control, offset: 0x20044 */ -} SYSCON_Type; - -/* ---------------------------------------------------------------------------- - -- SYSCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Register_Masks SYSCON Register Masks - * @{ - */ - -/*! @name AHBMATPRIO - AHB multilayer matrix priority control */ -/*! @{ */ -#define SYSCON_AHBMATPRIO_PRI_ICODE_MASK (0x3U) -#define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT (0U) -#define SYSCON_AHBMATPRIO_PRI_ICODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK) -#define SYSCON_AHBMATPRIO_PRI_DCODE_MASK (0xCU) -#define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT (2U) -#define SYSCON_AHBMATPRIO_PRI_DCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK) -#define SYSCON_AHBMATPRIO_PRI_SYS_MASK (0x30U) -#define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT (4U) -#define SYSCON_AHBMATPRIO_PRI_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK) -#define SYSCON_AHBMATPRIO_PRI_M0_MASK (0xC0U) -#define SYSCON_AHBMATPRIO_PRI_M0_SHIFT (6U) -#define SYSCON_AHBMATPRIO_PRI_M0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_M0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_M0_MASK) -#define SYSCON_AHBMATPRIO_PRI_USB_MASK (0x300U) -#define SYSCON_AHBMATPRIO_PRI_USB_SHIFT (8U) -#define SYSCON_AHBMATPRIO_PRI_USB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_MASK) -#define SYSCON_AHBMATPRIO_PRI_DMA_MASK (0xC00U) -#define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT (10U) -#define SYSCON_AHBMATPRIO_PRI_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK) -/*! @} */ - -/*! @name SYSTCKCAL - System tick counter calibration */ -/*! @{ */ -#define SYSCON_SYSTCKCAL_CAL_MASK (0xFFFFFFU) -#define SYSCON_SYSTCKCAL_CAL_SHIFT (0U) -#define SYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK) -#define SYSCON_SYSTCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_SYSTCKCAL_SKEW_SHIFT (24U) -#define SYSCON_SYSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK) -#define SYSCON_SYSTCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_SYSTCKCAL_NOREF_SHIFT (25U) -#define SYSCON_SYSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name NMISRC - NMI Source Select */ -/*! @{ */ -#define SYSCON_NMISRC_IRQM4_MASK (0x3FU) -#define SYSCON_NMISRC_IRQM4_SHIFT (0U) -#define SYSCON_NMISRC_IRQM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK) -#define SYSCON_NMISRC_IRQM0_MASK (0x3F00U) -#define SYSCON_NMISRC_IRQM0_SHIFT (8U) -#define SYSCON_NMISRC_IRQM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM0_SHIFT)) & SYSCON_NMISRC_IRQM0_MASK) -#define SYSCON_NMISRC_NMIENM0_MASK (0x40000000U) -#define SYSCON_NMISRC_NMIENM0_SHIFT (30U) -#define SYSCON_NMISRC_NMIENM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM0_SHIFT)) & SYSCON_NMISRC_NMIENM0_MASK) -#define SYSCON_NMISRC_NMIENM4_MASK (0x80000000U) -#define SYSCON_NMISRC_NMIENM4_SHIFT (31U) -#define SYSCON_NMISRC_NMIENM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK) -/*! @} */ - -/*! @name ASYNCAPBCTRL - Asynchronous APB Control */ -/*! @{ */ -#define SYSCON_ASYNCAPBCTRL_ENABLE_MASK (0x1U) -#define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT (0U) -#define SYSCON_ASYNCAPBCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK) -/*! @} */ - -/*! @name PIOPORCAP - POR captured value of port n */ -/*! @{ */ -#define SYSCON_PIOPORCAP_PIOPORCAP_MASK (0xFFFFFFFFU) -#define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT (0U) -#define SYSCON_PIOPORCAP_PIOPORCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK) -/*! @} */ - -/* The count of SYSCON_PIOPORCAP */ -#define SYSCON_PIOPORCAP_COUNT (2U) - -/*! @name PIORESCAP - Reset captured value of port n */ -/*! @{ */ -#define SYSCON_PIORESCAP_PIORESCAP_MASK (0xFFFFFFFFU) -#define SYSCON_PIORESCAP_PIORESCAP_SHIFT (0U) -#define SYSCON_PIORESCAP_PIORESCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK) -/*! @} */ - -/* The count of SYSCON_PIORESCAP */ -#define SYSCON_PIORESCAP_COUNT (2U) - -/*! @name PRESETCTRL - Peripheral reset control n */ -/*! @{ */ -#define SYSCON_PRESETCTRL_MRT0_RST_MASK (0x1U) -#define SYSCON_PRESETCTRL_MRT0_RST_SHIFT (0U) -#define SYSCON_PRESETCTRL_MRT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT0_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT0_RST_MASK) -#define SYSCON_PRESETCTRL_SCT0_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL_SCT0_RST_SHIFT (2U) -#define SYSCON_PRESETCTRL_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK) -#define SYSCON_PRESETCTRL_FLASH_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL_FLASH_RST_SHIFT (7U) -#define SYSCON_PRESETCTRL_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL_FLASH_RST_MASK) -#define SYSCON_PRESETCTRL_FMC_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL_FMC_RST_SHIFT (8U) -#define SYSCON_PRESETCTRL_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL_FMC_RST_MASK) -#define SYSCON_PRESETCTRL_UTICK0_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL_UTICK0_RST_SHIFT (10U) -#define SYSCON_PRESETCTRL_UTICK0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK0_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK0_RST_MASK) -#define SYSCON_PRESETCTRL_FC0_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL_FC0_RST_SHIFT (11U) -#define SYSCON_PRESETCTRL_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK) -#define SYSCON_PRESETCTRL_MUX_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL_MUX_RST_SHIFT (11U) -#define SYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK) -#define SYSCON_PRESETCTRL_FC1_RST_MASK (0x1000U) -#define SYSCON_PRESETCTRL_FC1_RST_SHIFT (12U) -#define SYSCON_PRESETCTRL_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK) -#define SYSCON_PRESETCTRL_FC2_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL_FC2_RST_SHIFT (13U) -#define SYSCON_PRESETCTRL_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK) -#define SYSCON_PRESETCTRL_IOCON_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL_IOCON_RST_SHIFT (13U) -#define SYSCON_PRESETCTRL_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK) -#define SYSCON_PRESETCTRL_FC3_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL_FC3_RST_SHIFT (14U) -#define SYSCON_PRESETCTRL_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK) -#define SYSCON_PRESETCTRL_GPIO0_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT (14U) -#define SYSCON_PRESETCTRL_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK) -#define SYSCON_PRESETCTRL_FC4_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL_FC4_RST_SHIFT (15U) -#define SYSCON_PRESETCTRL_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK) -#define SYSCON_PRESETCTRL_GPIO1_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT (15U) -#define SYSCON_PRESETCTRL_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK) -#define SYSCON_PRESETCTRL_FC5_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL_FC5_RST_SHIFT (16U) -#define SYSCON_PRESETCTRL_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK) -#define SYSCON_PRESETCTRL_FC6_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL_FC6_RST_SHIFT (17U) -#define SYSCON_PRESETCTRL_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK) -#define SYSCON_PRESETCTRL_FC7_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL_FC7_RST_SHIFT (18U) -#define SYSCON_PRESETCTRL_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK) -#define SYSCON_PRESETCTRL_PINT_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL_PINT_RST_SHIFT (18U) -#define SYSCON_PRESETCTRL_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK) -#define SYSCON_PRESETCTRL_DMIC0_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL_DMIC0_RST_SHIFT (19U) -#define SYSCON_PRESETCTRL_DMIC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC0_RST_MASK) -#define SYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL_GINT_RST_SHIFT (19U) -#define SYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK) -#define SYSCON_PRESETCTRL_DMA0_RST_MASK (0x100000U) -#define SYSCON_PRESETCTRL_DMA0_RST_SHIFT (20U) -#define SYSCON_PRESETCTRL_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA0_RST_MASK) -#define SYSCON_PRESETCTRL_CRC_RST_MASK (0x200000U) -#define SYSCON_PRESETCTRL_CRC_RST_SHIFT (21U) -#define SYSCON_PRESETCTRL_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK) -#define SYSCON_PRESETCTRL_CTIMER2_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT (22U) -#define SYSCON_PRESETCTRL_CTIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER2_RST_MASK) -#define SYSCON_PRESETCTRL_WWDT_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL_WWDT_RST_SHIFT (22U) -#define SYSCON_PRESETCTRL_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK) -#define SYSCON_PRESETCTRL_USB0_RST_MASK (0x2000000U) -#define SYSCON_PRESETCTRL_USB0_RST_SHIFT (25U) -#define SYSCON_PRESETCTRL_USB0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0_RST_MASK) -#define SYSCON_PRESETCTRL_CTIMER0_RST_MASK (0x4000000U) -#define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT (26U) -#define SYSCON_PRESETCTRL_CTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK) -#define SYSCON_PRESETCTRL_ADC0_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL_ADC0_RST_SHIFT (27U) -#define SYSCON_PRESETCTRL_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK) -#define SYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U) -#define SYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRL */ -#define SYSCON_PRESETCTRL_COUNT (2U) - -/*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */ -/*! @{ */ -#define SYSCON_PRESETCTRLSET_RST_SET_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLSET_RST_SET_SHIFT (0U) -#define SYSCON_PRESETCTRLSET_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLSET */ -#define SYSCON_PRESETCTRLSET_COUNT (2U) - -/*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */ -/*! @{ */ -#define SYSCON_PRESETCTRLCLR_RST_CLR_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT (0U) -#define SYSCON_PRESETCTRLCLR_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLCLR */ -#define SYSCON_PRESETCTRLCLR_COUNT (2U) - -/*! @name SYSRSTSTAT - System reset status register */ -/*! @{ */ -#define SYSCON_SYSRSTSTAT_POR_MASK (0x1U) -#define SYSCON_SYSRSTSTAT_POR_SHIFT (0U) -#define SYSCON_SYSRSTSTAT_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK) -#define SYSCON_SYSRSTSTAT_EXTRST_MASK (0x2U) -#define SYSCON_SYSRSTSTAT_EXTRST_SHIFT (1U) -#define SYSCON_SYSRSTSTAT_EXTRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK) -#define SYSCON_SYSRSTSTAT_WDT_MASK (0x4U) -#define SYSCON_SYSRSTSTAT_WDT_SHIFT (2U) -#define SYSCON_SYSRSTSTAT_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK) -#define SYSCON_SYSRSTSTAT_BOD_MASK (0x8U) -#define SYSCON_SYSRSTSTAT_BOD_SHIFT (3U) -#define SYSCON_SYSRSTSTAT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK) -#define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U) -#define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U) -#define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL - AHB Clock control n */ -/*! @{ */ -#define SYSCON_AHBCLKCTRL_MRT0_MASK (0x1U) -#define SYSCON_AHBCLKCTRL_MRT0_SHIFT (0U) -#define SYSCON_AHBCLKCTRL_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT0_SHIFT)) & SYSCON_AHBCLKCTRL_MRT0_MASK) -#define SYSCON_AHBCLKCTRL_ROM_MASK (0x2U) -#define SYSCON_AHBCLKCTRL_ROM_SHIFT (1U) -#define SYSCON_AHBCLKCTRL_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK) -#define SYSCON_AHBCLKCTRL_SCT0_MASK (0x4U) -#define SYSCON_AHBCLKCTRL_SCT0_SHIFT (2U) -#define SYSCON_AHBCLKCTRL_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK) -#define SYSCON_AHBCLKCTRL_SRAM1_MASK (0x8U) -#define SYSCON_AHBCLKCTRL_SRAM1_SHIFT (3U) -#define SYSCON_AHBCLKCTRL_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM1_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM1_MASK) -#define SYSCON_AHBCLKCTRL_SRAM2_MASK (0x10U) -#define SYSCON_AHBCLKCTRL_SRAM2_SHIFT (4U) -#define SYSCON_AHBCLKCTRL_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM2_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM2_MASK) -#define SYSCON_AHBCLKCTRL_FLASH_MASK (0x80U) -#define SYSCON_AHBCLKCTRL_FLASH_SHIFT (7U) -#define SYSCON_AHBCLKCTRL_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL_FLASH_MASK) -#define SYSCON_AHBCLKCTRL_FMC_MASK (0x100U) -#define SYSCON_AHBCLKCTRL_FMC_SHIFT (8U) -#define SYSCON_AHBCLKCTRL_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FMC_SHIFT)) & SYSCON_AHBCLKCTRL_FMC_MASK) -#define SYSCON_AHBCLKCTRL_UTICK0_MASK (0x400U) -#define SYSCON_AHBCLKCTRL_UTICK0_SHIFT (10U) -#define SYSCON_AHBCLKCTRL_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK0_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK0_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK (0x800U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT (11U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK) -#define SYSCON_AHBCLKCTRL_INPUTMUX_MASK (0x800U) -#define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT (11U) -#define SYSCON_AHBCLKCTRL_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK (0x1000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT (12U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT (13U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK) -#define SYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL_IOCON_SHIFT (13U) -#define SYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT (14U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK) -#define SYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U) -#define SYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT (15U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK) -#define SYSCON_AHBCLKCTRL_GPIO1_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL_GPIO1_SHIFT (15U) -#define SYSCON_AHBCLKCTRL_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT (16U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT (17U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT (18U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK) -#define SYSCON_AHBCLKCTRL_PINT_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL_PINT_SHIFT (18U) -#define SYSCON_AHBCLKCTRL_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK) -#define SYSCON_AHBCLKCTRL_DMIC0_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL_DMIC0_SHIFT (19U) -#define SYSCON_AHBCLKCTRL_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC0_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC0_MASK) -#define SYSCON_AHBCLKCTRL_GINT_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL_GINT_SHIFT (19U) -#define SYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK) -#define SYSCON_AHBCLKCTRL_DMA0_MASK (0x100000U) -#define SYSCON_AHBCLKCTRL_DMA0_SHIFT (20U) -#define SYSCON_AHBCLKCTRL_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL_DMA0_MASK) -#define SYSCON_AHBCLKCTRL_CRC_MASK (0x200000U) -#define SYSCON_AHBCLKCTRL_CRC_SHIFT (21U) -#define SYSCON_AHBCLKCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK) -#define SYSCON_AHBCLKCTRL_CTIMER2_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL_CTIMER2_SHIFT (22U) -#define SYSCON_AHBCLKCTRL_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER2_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER2_MASK) -#define SYSCON_AHBCLKCTRL_WWDT_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL_WWDT_SHIFT (22U) -#define SYSCON_AHBCLKCTRL_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK) -#define SYSCON_AHBCLKCTRL_RTC_MASK (0x800000U) -#define SYSCON_AHBCLKCTRL_RTC_SHIFT (23U) -#define SYSCON_AHBCLKCTRL_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK) -#define SYSCON_AHBCLKCTRL_USB0_MASK (0x2000000U) -#define SYSCON_AHBCLKCTRL_USB0_SHIFT (25U) -#define SYSCON_AHBCLKCTRL_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0_SHIFT)) & SYSCON_AHBCLKCTRL_USB0_MASK) -#define SYSCON_AHBCLKCTRL_CTIMER0_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT (26U) -#define SYSCON_AHBCLKCTRL_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK) -#define SYSCON_AHBCLKCTRL_MAILBOX_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL_MAILBOX_SHIFT (26U) -#define SYSCON_AHBCLKCTRL_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL_MAILBOX_MASK) -#define SYSCON_AHBCLKCTRL_ADC0_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL_ADC0_SHIFT (27U) -#define SYSCON_AHBCLKCTRL_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK) -#define SYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U) -#define SYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRL */ -#define SYSCON_AHBCLKCTRL_COUNT (2U) - -/*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */ -/*! @{ */ -#define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT (0U) -#define SYSCON_AHBCLKCTRLSET_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLSET */ -#define SYSCON_AHBCLKCTRLSET_COUNT (2U) - -/*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */ -/*! @{ */ -#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT (0U) -#define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLCLR */ -#define SYSCON_AHBCLKCTRLCLR_COUNT (2U) - -/*! @name MAINCLKSELA - Main clock source select A */ -/*! @{ */ -#define SYSCON_MAINCLKSELA_SEL_MASK (0x3U) -#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) -#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) -/*! @} */ - -/*! @name MAINCLKSELB - Main clock source select B */ -/*! @{ */ -#define SYSCON_MAINCLKSELB_SEL_MASK (0x3U) -#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) -#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) -/*! @} */ - -/*! @name CLKOUTSELA - CLKOUT clock source select A */ -/*! @{ */ -#define SYSCON_CLKOUTSELA_SEL_MASK (0x7U) -#define SYSCON_CLKOUTSELA_SEL_SHIFT (0U) -#define SYSCON_CLKOUTSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK) -/*! @} */ - -/*! @name SYSPLLCLKSEL - PLL clock source select */ -/*! @{ */ -#define SYSCON_SYSPLLCLKSEL_SEL_MASK (0x7U) -#define SYSCON_SYSPLLCLKSEL_SEL_SHIFT (0U) -#define SYSCON_SYSPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SPIFICLKSEL - SPIFI clock source select */ -/*! @{ */ -#define SYSCON_SPIFICLKSEL_SEL_MASK (0x7U) -#define SYSCON_SPIFICLKSEL_SEL_SHIFT (0U) -#define SYSCON_SPIFICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK) -/*! @} */ - -/*! @name ADCCLKSEL - ADC clock source select */ -/*! @{ */ -#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) -#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) -#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name USBCLKSEL - USB clock source select */ -/*! @{ */ -#define SYSCON_USBCLKSEL_SEL_MASK (0x7U) -#define SYSCON_USBCLKSEL_SEL_SHIFT (0U) -#define SYSCON_USBCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSEL_SEL_SHIFT)) & SYSCON_USBCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name FXCOMCLKSEL - Flexcomm 0 clock source select */ -/*! @{ */ -#define SYSCON_FXCOMCLKSEL_SEL_MASK (0x7U) -#define SYSCON_FXCOMCLKSEL_SEL_SHIFT (0U) -#define SYSCON_FXCOMCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FXCOMCLKSEL_SEL_SHIFT)) & SYSCON_FXCOMCLKSEL_SEL_MASK) -/*! @} */ - -/* The count of SYSCON_FXCOMCLKSEL */ -#define SYSCON_FXCOMCLKSEL_COUNT (8U) - -/*! @name MCLKCLKSEL - MCLK clock source select */ -/*! @{ */ -#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) -#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) -#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name FRGCLKSEL - Fractional Rate Generator clock source select */ -/*! @{ */ -#define SYSCON_FRGCLKSEL_SEL_MASK (0x7U) -#define SYSCON_FRGCLKSEL_SEL_SHIFT (0U) -#define SYSCON_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name DMICCLKSEL - Digital microphone (D-Mic) subsystem clock select */ -/*! @{ */ -#define SYSCON_DMICCLKSEL_SEL_MASK (0x7U) -#define SYSCON_DMICCLKSEL_SEL_SHIFT (0U) -#define SYSCON_DMICCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKDIV - SYSTICK clock divider */ -/*! @{ */ -#define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U) -#define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK) -#define SYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U) -#define SYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK) -#define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U) -#define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK) -/*! @} */ - -/*! @name TRACECLKDIV - Trace clock divider */ -/*! @{ */ -#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) -#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) -#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) -#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) -#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) -#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) -#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) -/*! @} */ - -/*! @name AHBCLKDIV - AHB clock divider */ -/*! @{ */ -#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) -#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) -#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) -#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) -#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) -#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) -/*! @} */ - -/*! @name CLKOUTDIV - CLKOUT clock divider */ -/*! @{ */ -#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) -#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) -#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) -#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) -#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) -#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) -#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) -#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) -#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) -/*! @} */ - -/*! @name SPIFICLKDIV - SPIFI clock divider */ -/*! @{ */ -#define SYSCON_SPIFICLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SPIFICLKDIV_DIV_SHIFT (0U) -#define SYSCON_SPIFICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK) -#define SYSCON_SPIFICLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SPIFICLKDIV_RESET_SHIFT (29U) -#define SYSCON_SPIFICLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_RESET_SHIFT)) & SYSCON_SPIFICLKDIV_RESET_MASK) -#define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SPIFICLKDIV_HALT_SHIFT (30U) -#define SYSCON_SPIFICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK) -/*! @} */ - -/*! @name ADCCLKDIV - ADC clock divider */ -/*! @{ */ -#define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) -#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) -#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) -#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) -#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) -#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) -/*! @} */ - -/*! @name USBCLKDIV - USB clock divider */ -/*! @{ */ -#define SYSCON_USBCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_USBCLKDIV_DIV_SHIFT (0U) -#define SYSCON_USBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_DIV_SHIFT)) & SYSCON_USBCLKDIV_DIV_MASK) -#define SYSCON_USBCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_USBCLKDIV_RESET_SHIFT (29U) -#define SYSCON_USBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_RESET_SHIFT)) & SYSCON_USBCLKDIV_RESET_MASK) -#define SYSCON_USBCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_USBCLKDIV_HALT_SHIFT (30U) -#define SYSCON_USBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_HALT_SHIFT)) & SYSCON_USBCLKDIV_HALT_MASK) -/*! @} */ - -/*! @name FRGCTRL - Fractional rate divider */ -/*! @{ */ -#define SYSCON_FRGCTRL_DIV_MASK (0xFFU) -#define SYSCON_FRGCTRL_DIV_SHIFT (0U) -#define SYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK) -#define SYSCON_FRGCTRL_MULT_MASK (0xFF00U) -#define SYSCON_FRGCTRL_MULT_SHIFT (8U) -#define SYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK) -/*! @} */ - -/*! @name DMICCLKDIV - DMIC clock divider */ -/*! @{ */ -#define SYSCON_DMICCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_DMICCLKDIV_DIV_SHIFT (0U) -#define SYSCON_DMICCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK) -#define SYSCON_DMICCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_DMICCLKDIV_RESET_SHIFT (29U) -#define SYSCON_DMICCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_RESET_SHIFT)) & SYSCON_DMICCLKDIV_RESET_MASK) -#define SYSCON_DMICCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_DMICCLKDIV_HALT_SHIFT (30U) -#define SYSCON_DMICCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK) -/*! @} */ - -/*! @name MCLKDIV - I2S MCLK clock divider */ -/*! @{ */ -#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_MCLKDIV_DIV_SHIFT (0U) -#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) -#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_MCLKDIV_RESET_SHIFT (29U) -#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) -#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_MCLKDIV_HALT_SHIFT (30U) -#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) -/*! @} */ - -/*! @name FLASHCFG - Flash wait states configuration */ -/*! @{ */ -#define SYSCON_FLASHCFG_FETCHCFG_MASK (0x3U) -#define SYSCON_FLASHCFG_FETCHCFG_SHIFT (0U) -#define SYSCON_FLASHCFG_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FETCHCFG_SHIFT)) & SYSCON_FLASHCFG_FETCHCFG_MASK) -#define SYSCON_FLASHCFG_DATACFG_MASK (0xCU) -#define SYSCON_FLASHCFG_DATACFG_SHIFT (2U) -#define SYSCON_FLASHCFG_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_DATACFG_SHIFT)) & SYSCON_FLASHCFG_DATACFG_MASK) -#define SYSCON_FLASHCFG_ACCEL_MASK (0x10U) -#define SYSCON_FLASHCFG_ACCEL_SHIFT (4U) -#define SYSCON_FLASHCFG_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_ACCEL_SHIFT)) & SYSCON_FLASHCFG_ACCEL_MASK) -#define SYSCON_FLASHCFG_PREFEN_MASK (0x20U) -#define SYSCON_FLASHCFG_PREFEN_SHIFT (5U) -#define SYSCON_FLASHCFG_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFEN_SHIFT)) & SYSCON_FLASHCFG_PREFEN_MASK) -#define SYSCON_FLASHCFG_PREFOVR_MASK (0x40U) -#define SYSCON_FLASHCFG_PREFOVR_SHIFT (6U) -#define SYSCON_FLASHCFG_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFOVR_SHIFT)) & SYSCON_FLASHCFG_PREFOVR_MASK) -#define SYSCON_FLASHCFG_FLASHTIM_MASK (0xF000U) -#define SYSCON_FLASHCFG_FLASHTIM_SHIFT (12U) -#define SYSCON_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FLASHTIM_SHIFT)) & SYSCON_FLASHCFG_FLASHTIM_MASK) -/*! @} */ - -/*! @name USBCLKCTRL - USB clock control */ -/*! @{ */ -#define SYSCON_USBCLKCTRL_POL_CLK_MASK (0x2U) -#define SYSCON_USBCLKCTRL_POL_CLK_SHIFT (1U) -#define SYSCON_USBCLKCTRL_POL_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKCTRL_POL_CLK_SHIFT)) & SYSCON_USBCLKCTRL_POL_CLK_MASK) -/*! @} */ - -/*! @name USBCLKSTAT - USB clock status */ -/*! @{ */ -#define SYSCON_USBCLKSTAT_NEED_CLKST_MASK (0x1U) -#define SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT (0U) -#define SYSCON_USBCLKSTAT_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT)) & SYSCON_USBCLKSTAT_NEED_CLKST_MASK) -/*! @} */ - -/*! @name FREQMECTRL - Frequency measure register */ -/*! @{ */ -#define SYSCON_FREQMECTRL_CAPVAL_MASK (0x3FFFU) -#define SYSCON_FREQMECTRL_CAPVAL_SHIFT (0U) -#define SYSCON_FREQMECTRL_CAPVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK) -#define SYSCON_FREQMECTRL_PROG_MASK (0x80000000U) -#define SYSCON_FREQMECTRL_PROG_SHIFT (31U) -#define SYSCON_FREQMECTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK) -/*! @} */ - -/*! @name MCLKIO - MCLK input/output control */ -/*! @{ */ -#define SYSCON_MCLKIO_DIR_MASK (0x1U) -#define SYSCON_MCLKIO_DIR_SHIFT (0U) -#define SYSCON_MCLKIO_DIR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK) -/*! @} */ - -/*! @name FROCTRL - FRO oscillator control */ -/*! @{ */ -#define SYSCON_FROCTRL_TRIM_MASK (0x3FFFU) -#define SYSCON_FROCTRL_TRIM_SHIFT (0U) -#define SYSCON_FROCTRL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_TRIM_SHIFT)) & SYSCON_FROCTRL_TRIM_MASK) -#define SYSCON_FROCTRL_SEL_MASK (0x4000U) -#define SYSCON_FROCTRL_SEL_SHIFT (14U) -#define SYSCON_FROCTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK) -#define SYSCON_FROCTRL_FREQTRIM_MASK (0xFF0000U) -#define SYSCON_FROCTRL_FREQTRIM_SHIFT (16U) -#define SYSCON_FROCTRL_FREQTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK) -#define SYSCON_FROCTRL_USBCLKADJ_MASK (0x1000000U) -#define SYSCON_FROCTRL_USBCLKADJ_SHIFT (24U) -#define SYSCON_FROCTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK) -#define SYSCON_FROCTRL_USBMODCHG_MASK (0x2000000U) -#define SYSCON_FROCTRL_USBMODCHG_SHIFT (25U) -#define SYSCON_FROCTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK) -#define SYSCON_FROCTRL_HSPDCLK_MASK (0x40000000U) -#define SYSCON_FROCTRL_HSPDCLK_SHIFT (30U) -#define SYSCON_FROCTRL_HSPDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK) -#define SYSCON_FROCTRL_WRTRIM_MASK (0x80000000U) -#define SYSCON_FROCTRL_WRTRIM_SHIFT (31U) -#define SYSCON_FROCTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_WRTRIM_SHIFT)) & SYSCON_FROCTRL_WRTRIM_MASK) -/*! @} */ - -/*! @name WDTOSCCTRL - Watchdog oscillator control */ -/*! @{ */ -#define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU) -#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U) -#define SYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK) -#define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x3E0U) -#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U) -#define SYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK) -/*! @} */ - -/*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */ -/*! @{ */ -#define SYSCON_RTCOSCCTRL_EN_MASK (0x1U) -#define SYSCON_RTCOSCCTRL_EN_SHIFT (0U) -#define SYSCON_RTCOSCCTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK) -/*! @} */ - -/*! @name SYSPLLCTRL - PLL control */ -/*! @{ */ -#define SYSCON_SYSPLLCTRL_SELR_MASK (0xFU) -#define SYSCON_SYSPLLCTRL_SELR_SHIFT (0U) -#define SYSCON_SYSPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK) -#define SYSCON_SYSPLLCTRL_SELI_MASK (0x3F0U) -#define SYSCON_SYSPLLCTRL_SELI_SHIFT (4U) -#define SYSCON_SYSPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK) -#define SYSCON_SYSPLLCTRL_SELP_MASK (0x7C00U) -#define SYSCON_SYSPLLCTRL_SELP_SHIFT (10U) -#define SYSCON_SYSPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK) -#define SYSCON_SYSPLLCTRL_BYPASS_MASK (0x8000U) -#define SYSCON_SYSPLLCTRL_BYPASS_SHIFT (15U) -#define SYSCON_SYSPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK) -#define SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK (0x10000U) -#define SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT (16U) -#define SYSCON_SYSPLLCTRL_BYPASSCCODIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK) -#define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK (0x20000U) -#define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT (17U) -#define SYSCON_SYSPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK) -#define SYSCON_SYSPLLCTRL_BANDSEL_MASK (0x40000U) -#define SYSCON_SYSPLLCTRL_BANDSEL_SHIFT (18U) -#define SYSCON_SYSPLLCTRL_BANDSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BANDSEL_SHIFT)) & SYSCON_SYSPLLCTRL_BANDSEL_MASK) -#define SYSCON_SYSPLLCTRL_DIRECTI_MASK (0x80000U) -#define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT (19U) -#define SYSCON_SYSPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK) -#define SYSCON_SYSPLLCTRL_DIRECTO_MASK (0x100000U) -#define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT (20U) -#define SYSCON_SYSPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK) -/*! @} */ - -/*! @name SYSPLLSTAT - PLL status */ -/*! @{ */ -#define SYSCON_SYSPLLSTAT_LOCK_MASK (0x1U) -#define SYSCON_SYSPLLSTAT_LOCK_SHIFT (0U) -#define SYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK) -/*! @} */ - -/*! @name SYSPLLNDEC - PLL N decoder */ -/*! @{ */ -#define SYSCON_SYSPLLNDEC_NDEC_MASK (0x3FFU) -#define SYSCON_SYSPLLNDEC_NDEC_SHIFT (0U) -#define SYSCON_SYSPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK) -#define SYSCON_SYSPLLNDEC_NREQ_MASK (0x400U) -#define SYSCON_SYSPLLNDEC_NREQ_SHIFT (10U) -#define SYSCON_SYSPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK) -/*! @} */ - -/*! @name SYSPLLPDEC - PLL P decoder */ -/*! @{ */ -#define SYSCON_SYSPLLPDEC_PDEC_MASK (0x7FU) -#define SYSCON_SYSPLLPDEC_PDEC_SHIFT (0U) -#define SYSCON_SYSPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK) -#define SYSCON_SYSPLLPDEC_PREQ_MASK (0x80U) -#define SYSCON_SYSPLLPDEC_PREQ_SHIFT (7U) -#define SYSCON_SYSPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK) -/*! @} */ - -/*! @name SYSPLLSSCTRL0 - PLL spread spectrum control 0 */ -/*! @{ */ -#define SYSCON_SYSPLLSSCTRL0_MDEC_MASK (0x1FFFFU) -#define SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT (0U) -#define SYSCON_SYSPLLSSCTRL0_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MDEC_MASK) -#define SYSCON_SYSPLLSSCTRL0_MREQ_MASK (0x20000U) -#define SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT (17U) -#define SYSCON_SYSPLLSSCTRL0_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MREQ_MASK) -#define SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK (0x40000U) -#define SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT (18U) -#define SYSCON_SYSPLLSSCTRL0_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT)) & SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK) -/*! @} */ - -/*! @name SYSPLLSSCTRL1 - PLL spread spectrum control 1 */ -/*! @{ */ -#define SYSCON_SYSPLLSSCTRL1_MD_MASK (0x7FFFFU) -#define SYSCON_SYSPLLSSCTRL1_MD_SHIFT (0U) -#define SYSCON_SYSPLLSSCTRL1_MD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MD_MASK) -#define SYSCON_SYSPLLSSCTRL1_MDREQ_MASK (0x80000U) -#define SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT (19U) -#define SYSCON_SYSPLLSSCTRL1_MDREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MDREQ_MASK) -#define SYSCON_SYSPLLSSCTRL1_MF_MASK (0x700000U) -#define SYSCON_SYSPLLSSCTRL1_MF_SHIFT (20U) -#define SYSCON_SYSPLLSSCTRL1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MF_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MF_MASK) -#define SYSCON_SYSPLLSSCTRL1_MR_MASK (0x3800000U) -#define SYSCON_SYSPLLSSCTRL1_MR_SHIFT (23U) -#define SYSCON_SYSPLLSSCTRL1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MR_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MR_MASK) -#define SYSCON_SYSPLLSSCTRL1_MC_MASK (0xC000000U) -#define SYSCON_SYSPLLSSCTRL1_MC_SHIFT (26U) -#define SYSCON_SYSPLLSSCTRL1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MC_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MC_MASK) -#define SYSCON_SYSPLLSSCTRL1_PD_MASK (0x10000000U) -#define SYSCON_SYSPLLSSCTRL1_PD_SHIFT (28U) -#define SYSCON_SYSPLLSSCTRL1_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_PD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_PD_MASK) -#define SYSCON_SYSPLLSSCTRL1_DITHER_MASK (0x20000000U) -#define SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT (29U) -#define SYSCON_SYSPLLSSCTRL1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT)) & SYSCON_SYSPLLSSCTRL1_DITHER_MASK) -/*! @} */ - -/*! @name PDSLEEPCFG - Sleep configuration register n */ -/*! @{ */ -#define SYSCON_PDSLEEPCFG_PD_SLEEP_MASK (0xFFFFFFFFU) -#define SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT (0U) -#define SYSCON_PDSLEEPCFG_PD_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT)) & SYSCON_PDSLEEPCFG_PD_SLEEP_MASK) -/*! @} */ - -/* The count of SYSCON_PDSLEEPCFG */ -#define SYSCON_PDSLEEPCFG_COUNT (2U) - -/*! @name PDRUNCFG - Power configuration register n */ -/*! @{ */ -#define SYSCON_PDRUNCFG_PDEN_FRO_MASK (0x10U) -#define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT (4U) -#define SYSCON_PDRUNCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK) -#define SYSCON_PDRUNCFG_PD_FLASH_MASK (0x20U) -#define SYSCON_PDRUNCFG_PD_FLASH_SHIFT (5U) -#define SYSCON_PDRUNCFG_PD_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_FLASH_SHIFT)) & SYSCON_PDRUNCFG_PD_FLASH_MASK) -#define SYSCON_PDRUNCFG_PDEN_TS_MASK (0x40U) -#define SYSCON_PDRUNCFG_PDEN_TS_SHIFT (6U) -#define SYSCON_PDRUNCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK) -#define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK (0x80U) -#define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT (7U) -#define SYSCON_PDRUNCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK) -#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK (0x100U) -#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT (8U) -#define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK) -#define SYSCON_PDRUNCFG_PDEN_ADC0_MASK (0x400U) -#define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT (10U) -#define SYSCON_PDRUNCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK) -#define SYSCON_PDRUNCFG_PD_VDDFLASH_MASK (0x800U) -#define SYSCON_PDRUNCFG_PD_VDDFLASH_SHIFT (11U) -#define SYSCON_PDRUNCFG_PD_VDDFLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_VDDFLASH_SHIFT)) & SYSCON_PDRUNCFG_PD_VDDFLASH_MASK) -#define SYSCON_PDRUNCFG_LP_VDDFLASH_MASK (0x1000U) -#define SYSCON_PDRUNCFG_LP_VDDFLASH_SHIFT (12U) -#define SYSCON_PDRUNCFG_LP_VDDFLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_LP_VDDFLASH_SHIFT)) & SYSCON_PDRUNCFG_LP_VDDFLASH_MASK) -#define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK (0x2000U) -#define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT (13U) -#define SYSCON_PDRUNCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK) -#define SYSCON_PDRUNCFG_PDEN_SRAM1_MASK (0x4000U) -#define SYSCON_PDRUNCFG_PDEN_SRAM1_SHIFT (14U) -#define SYSCON_PDRUNCFG_PDEN_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM1_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM1_MASK) -#define SYSCON_PDRUNCFG_PDEN_SRAM2_MASK (0x8000U) -#define SYSCON_PDRUNCFG_PDEN_SRAM2_SHIFT (15U) -#define SYSCON_PDRUNCFG_PDEN_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM2_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM2_MASK) -#define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK (0x10000U) -#define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT (16U) -#define SYSCON_PDRUNCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK) -#define SYSCON_PDRUNCFG_PDEN_ROM_MASK (0x20000U) -#define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT (17U) -#define SYSCON_PDRUNCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK) -#define SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK (0x40000U) -#define SYSCON_PDRUNCFG_PD_VDDHV_ENA_SHIFT (18U) -#define SYSCON_PDRUNCFG_PD_VDDHV_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_VDDHV_ENA_SHIFT)) & SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK) -#define SYSCON_PDRUNCFG_PDEN_VDDA_MASK (0x80000U) -#define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT (19U) -#define SYSCON_PDRUNCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK) -#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK (0x100000U) -#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT (20U) -#define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) -#define SYSCON_PDRUNCFG_PDEN_USB_PHY_MASK (0x200000U) -#define SYSCON_PDRUNCFG_PDEN_USB_PHY_SHIFT (21U) -#define SYSCON_PDRUNCFG_PDEN_USB_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_PHY_MASK) -#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK (0x400000U) -#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT (22U) -#define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK) -#define SYSCON_PDRUNCFG_PDEN_VREFP_MASK (0x800000U) -#define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT (23U) -#define SYSCON_PDRUNCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK) -#define SYSCON_PDRUNCFG_PD_FLASH_BG_MASK (0x2000000U) -#define SYSCON_PDRUNCFG_PD_FLASH_BG_SHIFT (25U) -#define SYSCON_PDRUNCFG_PD_FLASH_BG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_FLASH_BG_SHIFT)) & SYSCON_PDRUNCFG_PD_FLASH_BG_MASK) -#define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_MASK (0x10000000U) -#define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_SHIFT (28U) -#define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_SHIFT)) & SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_MASK) -#define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_MASK (0x20000000U) -#define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_SHIFT (29U) -#define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_SHIFT)) & SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_MASK) -/*! @} */ - -/* The count of SYSCON_PDRUNCFG */ -#define SYSCON_PDRUNCFG_COUNT (2U) - -/*! @name PDRUNCFGSET - Set bits in PDRUNCFGn */ -/*! @{ */ -#define SYSCON_PDRUNCFGSET_PD_SET_MASK (0xFFFFFFFFU) -#define SYSCON_PDRUNCFGSET_PD_SET_SHIFT (0U) -#define SYSCON_PDRUNCFGSET_PD_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PD_SET_SHIFT)) & SYSCON_PDRUNCFGSET_PD_SET_MASK) -/*! @} */ - -/* The count of SYSCON_PDRUNCFGSET */ -#define SYSCON_PDRUNCFGSET_COUNT (2U) - -/*! @name PDRUNCFGCLR - Clear bits in PDRUNCFGn */ -/*! @{ */ -#define SYSCON_PDRUNCFGCLR_PD_CLR_MASK (0xFFFFFFFFU) -#define SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT (0U) -#define SYSCON_PDRUNCFGCLR_PD_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT)) & SYSCON_PDRUNCFGCLR_PD_CLR_MASK) -/*! @} */ - -/* The count of SYSCON_PDRUNCFGCLR */ -#define SYSCON_PDRUNCFGCLR_COUNT (2U) - -/*! @name STARTERP - Start logic n wake-up enable register */ -/*! @{ */ -#define SYSCON_STARTERP_PINT4_MASK (0x1U) -#define SYSCON_STARTERP_PINT4_SHIFT (0U) -#define SYSCON_STARTERP_PINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT4_SHIFT)) & SYSCON_STARTERP_PINT4_MASK) -#define SYSCON_STARTERP_WDT_BOD_MASK (0x1U) -#define SYSCON_STARTERP_WDT_BOD_SHIFT (0U) -#define SYSCON_STARTERP_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_WDT_BOD_SHIFT)) & SYSCON_STARTERP_WDT_BOD_MASK) -#define SYSCON_STARTERP_DMA0_MASK (0x2U) -#define SYSCON_STARTERP_DMA0_SHIFT (1U) -#define SYSCON_STARTERP_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_DMA0_SHIFT)) & SYSCON_STARTERP_DMA0_MASK) -#define SYSCON_STARTERP_PINT5_MASK (0x2U) -#define SYSCON_STARTERP_PINT5_SHIFT (1U) -#define SYSCON_STARTERP_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT5_SHIFT)) & SYSCON_STARTERP_PINT5_MASK) -#define SYSCON_STARTERP_GINT0_MASK (0x4U) -#define SYSCON_STARTERP_GINT0_SHIFT (2U) -#define SYSCON_STARTERP_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_GINT0_SHIFT)) & SYSCON_STARTERP_GINT0_MASK) -#define SYSCON_STARTERP_PINT6_MASK (0x4U) -#define SYSCON_STARTERP_PINT6_SHIFT (2U) -#define SYSCON_STARTERP_PINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT6_SHIFT)) & SYSCON_STARTERP_PINT6_MASK) -#define SYSCON_STARTERP_GINT1_MASK (0x8U) -#define SYSCON_STARTERP_GINT1_SHIFT (3U) -#define SYSCON_STARTERP_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_GINT1_SHIFT)) & SYSCON_STARTERP_GINT1_MASK) -#define SYSCON_STARTERP_PINT7_MASK (0x8U) -#define SYSCON_STARTERP_PINT7_SHIFT (3U) -#define SYSCON_STARTERP_PINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT7_SHIFT)) & SYSCON_STARTERP_PINT7_MASK) -#define SYSCON_STARTERP_CTIMER2_MASK (0x10U) -#define SYSCON_STARTERP_CTIMER2_SHIFT (4U) -#define SYSCON_STARTERP_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER2_SHIFT)) & SYSCON_STARTERP_CTIMER2_MASK) -#define SYSCON_STARTERP_PIN_INT0_MASK (0x10U) -#define SYSCON_STARTERP_PIN_INT0_SHIFT (4U) -#define SYSCON_STARTERP_PIN_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT0_SHIFT)) & SYSCON_STARTERP_PIN_INT0_MASK) -#define SYSCON_STARTERP_CTIMER4_MASK (0x20U) -#define SYSCON_STARTERP_CTIMER4_SHIFT (5U) -#define SYSCON_STARTERP_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER4_SHIFT)) & SYSCON_STARTERP_CTIMER4_MASK) -#define SYSCON_STARTERP_PIN_INT1_MASK (0x20U) -#define SYSCON_STARTERP_PIN_INT1_SHIFT (5U) -#define SYSCON_STARTERP_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT1_SHIFT)) & SYSCON_STARTERP_PIN_INT1_MASK) -#define SYSCON_STARTERP_PIN_INT2_MASK (0x40U) -#define SYSCON_STARTERP_PIN_INT2_SHIFT (6U) -#define SYSCON_STARTERP_PIN_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT2_SHIFT)) & SYSCON_STARTERP_PIN_INT2_MASK) -#define SYSCON_STARTERP_PIN_INT3_MASK (0x80U) -#define SYSCON_STARTERP_PIN_INT3_SHIFT (7U) -#define SYSCON_STARTERP_PIN_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT3_SHIFT)) & SYSCON_STARTERP_PIN_INT3_MASK) -#define SYSCON_STARTERP_UTICK0_MASK (0x100U) -#define SYSCON_STARTERP_UTICK0_SHIFT (8U) -#define SYSCON_STARTERP_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_UTICK0_SHIFT)) & SYSCON_STARTERP_UTICK0_MASK) -#define SYSCON_STARTERP_MRT0_MASK (0x200U) -#define SYSCON_STARTERP_MRT0_SHIFT (9U) -#define SYSCON_STARTERP_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_MRT0_SHIFT)) & SYSCON_STARTERP_MRT0_MASK) -#define SYSCON_STARTERP_CTIMER0_MASK (0x400U) -#define SYSCON_STARTERP_CTIMER0_SHIFT (10U) -#define SYSCON_STARTERP_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER0_SHIFT)) & SYSCON_STARTERP_CTIMER0_MASK) -#define SYSCON_STARTERP_CTIMER1_MASK (0x800U) -#define SYSCON_STARTERP_CTIMER1_SHIFT (11U) -#define SYSCON_STARTERP_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER1_SHIFT)) & SYSCON_STARTERP_CTIMER1_MASK) -#define SYSCON_STARTERP_SCT0_MASK (0x1000U) -#define SYSCON_STARTERP_SCT0_SHIFT (12U) -#define SYSCON_STARTERP_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_SCT0_SHIFT)) & SYSCON_STARTERP_SCT0_MASK) -#define SYSCON_STARTERP_CTIMER3_MASK (0x2000U) -#define SYSCON_STARTERP_CTIMER3_SHIFT (13U) -#define SYSCON_STARTERP_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER3_SHIFT)) & SYSCON_STARTERP_CTIMER3_MASK) -#define SYSCON_STARTERP_FLEXCOMM0_MASK (0x4000U) -#define SYSCON_STARTERP_FLEXCOMM0_SHIFT (14U) -#define SYSCON_STARTERP_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM0_SHIFT)) & SYSCON_STARTERP_FLEXCOMM0_MASK) -#define SYSCON_STARTERP_FLEXCOMM1_MASK (0x8000U) -#define SYSCON_STARTERP_FLEXCOMM1_SHIFT (15U) -#define SYSCON_STARTERP_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM1_SHIFT)) & SYSCON_STARTERP_FLEXCOMM1_MASK) -#define SYSCON_STARTERP_FLEXCOMM2_MASK (0x10000U) -#define SYSCON_STARTERP_FLEXCOMM2_SHIFT (16U) -#define SYSCON_STARTERP_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM2_SHIFT)) & SYSCON_STARTERP_FLEXCOMM2_MASK) -#define SYSCON_STARTERP_FLEXCOMM3_MASK (0x20000U) -#define SYSCON_STARTERP_FLEXCOMM3_SHIFT (17U) -#define SYSCON_STARTERP_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM3_SHIFT)) & SYSCON_STARTERP_FLEXCOMM3_MASK) -#define SYSCON_STARTERP_FLEXCOMM4_MASK (0x40000U) -#define SYSCON_STARTERP_FLEXCOMM4_SHIFT (18U) -#define SYSCON_STARTERP_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM4_SHIFT)) & SYSCON_STARTERP_FLEXCOMM4_MASK) -#define SYSCON_STARTERP_FLEXCOMM5_MASK (0x80000U) -#define SYSCON_STARTERP_FLEXCOMM5_SHIFT (19U) -#define SYSCON_STARTERP_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM5_SHIFT)) & SYSCON_STARTERP_FLEXCOMM5_MASK) -#define SYSCON_STARTERP_FLEXCOMM6_MASK (0x100000U) -#define SYSCON_STARTERP_FLEXCOMM6_SHIFT (20U) -#define SYSCON_STARTERP_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM6_SHIFT)) & SYSCON_STARTERP_FLEXCOMM6_MASK) -#define SYSCON_STARTERP_FLEXCOMM7_MASK (0x200000U) -#define SYSCON_STARTERP_FLEXCOMM7_SHIFT (21U) -#define SYSCON_STARTERP_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM7_SHIFT)) & SYSCON_STARTERP_FLEXCOMM7_MASK) -#define SYSCON_STARTERP_ADC0_SEQA_MASK (0x400000U) -#define SYSCON_STARTERP_ADC0_SEQA_SHIFT (22U) -#define SYSCON_STARTERP_ADC0_SEQA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_SEQA_SHIFT)) & SYSCON_STARTERP_ADC0_SEQA_MASK) -#define SYSCON_STARTERP_ADC0_SEQB_MASK (0x800000U) -#define SYSCON_STARTERP_ADC0_SEQB_SHIFT (23U) -#define SYSCON_STARTERP_ADC0_SEQB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_SEQB_SHIFT)) & SYSCON_STARTERP_ADC0_SEQB_MASK) -#define SYSCON_STARTERP_ADC0_THCMP_MASK (0x1000000U) -#define SYSCON_STARTERP_ADC0_THCMP_SHIFT (24U) -#define SYSCON_STARTERP_ADC0_THCMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_THCMP_SHIFT)) & SYSCON_STARTERP_ADC0_THCMP_MASK) -#define SYSCON_STARTERP_DMIC0_MASK (0x2000000U) -#define SYSCON_STARTERP_DMIC0_SHIFT (25U) -#define SYSCON_STARTERP_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_DMIC0_SHIFT)) & SYSCON_STARTERP_DMIC0_MASK) -#define SYSCON_STARTERP_USB0_NEEDCLK_MASK (0x8000000U) -#define SYSCON_STARTERP_USB0_NEEDCLK_SHIFT (27U) -#define SYSCON_STARTERP_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTERP_USB0_NEEDCLK_MASK) -#define SYSCON_STARTERP_USB0_MASK (0x10000000U) -#define SYSCON_STARTERP_USB0_SHIFT (28U) -#define SYSCON_STARTERP_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_USB0_SHIFT)) & SYSCON_STARTERP_USB0_MASK) -#define SYSCON_STARTERP_RTC_MASK (0x20000000U) -#define SYSCON_STARTERP_RTC_SHIFT (29U) -#define SYSCON_STARTERP_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_RTC_SHIFT)) & SYSCON_STARTERP_RTC_MASK) -#define SYSCON_STARTERP_MAILBOX_MASK (0x80000000U) -#define SYSCON_STARTERP_MAILBOX_SHIFT (31U) -#define SYSCON_STARTERP_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_MAILBOX_SHIFT)) & SYSCON_STARTERP_MAILBOX_MASK) -/*! @} */ - -/* The count of SYSCON_STARTERP */ -#define SYSCON_STARTERP_COUNT (2U) - -/*! @name STARTERSET - Set bits in STARTERn */ -/*! @{ */ -#define SYSCON_STARTERSET_START_SET_MASK (0xFFFFFFFFU) -#define SYSCON_STARTERSET_START_SET_SHIFT (0U) -#define SYSCON_STARTERSET_START_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK) -/*! @} */ - -/* The count of SYSCON_STARTERSET */ -#define SYSCON_STARTERSET_COUNT (2U) - -/*! @name STARTERCLR - Clear bits in STARTERn */ -/*! @{ */ -#define SYSCON_STARTERCLR_START_CLR_MASK (0xFFFFFFFFU) -#define SYSCON_STARTERCLR_START_CLR_SHIFT (0U) -#define SYSCON_STARTERCLR_START_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK) -/*! @} */ - -/* The count of SYSCON_STARTERCLR */ -#define SYSCON_STARTERCLR_COUNT (2U) - -/*! @name HWWAKE - Configures special cases of hardware wake-up */ -/*! @{ */ -#define SYSCON_HWWAKE_FORCEWAKE_MASK (0x1U) -#define SYSCON_HWWAKE_FORCEWAKE_SHIFT (0U) -#define SYSCON_HWWAKE_FORCEWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK) -#define SYSCON_HWWAKE_FCWAKE_MASK (0x2U) -#define SYSCON_HWWAKE_FCWAKE_SHIFT (1U) -#define SYSCON_HWWAKE_FCWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK) -#define SYSCON_HWWAKE_WAKEDMIC_MASK (0x4U) -#define SYSCON_HWWAKE_WAKEDMIC_SHIFT (2U) -#define SYSCON_HWWAKE_WAKEDMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMIC_SHIFT)) & SYSCON_HWWAKE_WAKEDMIC_MASK) -#define SYSCON_HWWAKE_WAKEDMA_MASK (0x8U) -#define SYSCON_HWWAKE_WAKEDMA_SHIFT (3U) -#define SYSCON_HWWAKE_WAKEDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK) -/*! @} */ - -/*! @name CPUCTRL - CPU Control for multiple processors */ -/*! @{ */ -#define SYSCON_CPUCTRL_MASTERCPU_MASK (0x1U) -#define SYSCON_CPUCTRL_MASTERCPU_SHIFT (0U) -#define SYSCON_CPUCTRL_MASTERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_MASTERCPU_SHIFT)) & SYSCON_CPUCTRL_MASTERCPU_MASK) -#define SYSCON_CPUCTRL_CM4CLKEN_MASK (0x4U) -#define SYSCON_CPUCTRL_CM4CLKEN_SHIFT (2U) -#define SYSCON_CPUCTRL_CM4CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM4CLKEN_SHIFT)) & SYSCON_CPUCTRL_CM4CLKEN_MASK) -#define SYSCON_CPUCTRL_CM0CLKEN_MASK (0x8U) -#define SYSCON_CPUCTRL_CM0CLKEN_SHIFT (3U) -#define SYSCON_CPUCTRL_CM0CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM0CLKEN_SHIFT)) & SYSCON_CPUCTRL_CM0CLKEN_MASK) -#define SYSCON_CPUCTRL_CM4RSTEN_MASK (0x10U) -#define SYSCON_CPUCTRL_CM4RSTEN_SHIFT (4U) -#define SYSCON_CPUCTRL_CM4RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM4RSTEN_SHIFT)) & SYSCON_CPUCTRL_CM4RSTEN_MASK) -#define SYSCON_CPUCTRL_CM0RSTEN_MASK (0x20U) -#define SYSCON_CPUCTRL_CM0RSTEN_SHIFT (5U) -#define SYSCON_CPUCTRL_CM0RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM0RSTEN_SHIFT)) & SYSCON_CPUCTRL_CM0RSTEN_MASK) -#define SYSCON_CPUCTRL_POWERCPU_MASK (0x40U) -#define SYSCON_CPUCTRL_POWERCPU_SHIFT (6U) -#define SYSCON_CPUCTRL_POWERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_POWERCPU_SHIFT)) & SYSCON_CPUCTRL_POWERCPU_MASK) -/*! @} */ - -/*! @name CPBOOT - Coprocessor Boot Address */ -/*! @{ */ -#define SYSCON_CPBOOT_BOOTADDR_MASK (0xFFFFFFFFU) -#define SYSCON_CPBOOT_BOOTADDR_SHIFT (0U) -#define SYSCON_CPBOOT_BOOTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_BOOTADDR_SHIFT)) & SYSCON_CPBOOT_BOOTADDR_MASK) -/*! @} */ - -/*! @name CPSTACK - Coprocessor Stack Address */ -/*! @{ */ -#define SYSCON_CPSTACK_STACKADDR_MASK (0xFFFFFFFFU) -#define SYSCON_CPSTACK_STACKADDR_SHIFT (0U) -#define SYSCON_CPSTACK_STACKADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTACK_STACKADDR_SHIFT)) & SYSCON_CPSTACK_STACKADDR_MASK) -/*! @} */ - -/*! @name CPSTAT - Coprocessor Status */ -/*! @{ */ -#define SYSCON_CPSTAT_CM4SLEEPING_MASK (0x1U) -#define SYSCON_CPSTAT_CM4SLEEPING_SHIFT (0U) -#define SYSCON_CPSTAT_CM4SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM4SLEEPING_SHIFT)) & SYSCON_CPSTAT_CM4SLEEPING_MASK) -#define SYSCON_CPSTAT_CM0SLEEPING_MASK (0x2U) -#define SYSCON_CPSTAT_CM0SLEEPING_SHIFT (1U) -#define SYSCON_CPSTAT_CM0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CM0SLEEPING_MASK) -#define SYSCON_CPSTAT_CM4LOCKUP_MASK (0x4U) -#define SYSCON_CPSTAT_CM4LOCKUP_SHIFT (2U) -#define SYSCON_CPSTAT_CM4LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM4LOCKUP_SHIFT)) & SYSCON_CPSTAT_CM4LOCKUP_MASK) -#define SYSCON_CPSTAT_CM0LOCKUP_MASK (0x8U) -#define SYSCON_CPSTAT_CM0LOCKUP_SHIFT (3U) -#define SYSCON_CPSTAT_CM0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CM0LOCKUP_MASK) -/*! @} */ - -/*! @name AUTOCGOR - Auto Clock-Gate Override Register */ -/*! @{ */ -#define SYSCON_AUTOCGOR_RAM0X_MASK (0x2U) -#define SYSCON_AUTOCGOR_RAM0X_SHIFT (1U) -#define SYSCON_AUTOCGOR_RAM0X(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK) -#define SYSCON_AUTOCGOR_RAM1_MASK (0x4U) -#define SYSCON_AUTOCGOR_RAM1_SHIFT (2U) -#define SYSCON_AUTOCGOR_RAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM1_SHIFT)) & SYSCON_AUTOCGOR_RAM1_MASK) -#define SYSCON_AUTOCGOR_RAM2_MASK (0x8U) -#define SYSCON_AUTOCGOR_RAM2_SHIFT (3U) -#define SYSCON_AUTOCGOR_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK) -/*! @} */ - -/*! @name JTAGIDCODE - JTAG ID code register */ -/*! @{ */ -#define SYSCON_JTAGIDCODE_JTAGID_MASK (0xFFFFFFFFU) -#define SYSCON_JTAGIDCODE_JTAGID_SHIFT (0U) -#define SYSCON_JTAGIDCODE_JTAGID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK) -/*! @} */ - -/*! @name DEVICE_ID0 - Part ID register */ -/*! @{ */ -#define SYSCON_DEVICE_ID0_PARTID_MASK (0xFFFFFFFFU) -#define SYSCON_DEVICE_ID0_PARTID_SHIFT (0U) -#define SYSCON_DEVICE_ID0_PARTID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK) -/*! @} */ - -/*! @name DEVICE_ID1 - Boot ROM and die revision register */ -/*! @{ */ -#define SYSCON_DEVICE_ID1_REVID_MASK (0xFFFFFFFFU) -#define SYSCON_DEVICE_ID1_REVID_SHIFT (0U) -#define SYSCON_DEVICE_ID1_REVID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK) -/*! @} */ - -/*! @name BODCTRL - Brown-Out Detect control */ -/*! @{ */ -#define SYSCON_BODCTRL_BODRSTLEV_MASK (0x3U) -#define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0U) -#define SYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK) -#define SYSCON_BODCTRL_BODRSTENA_MASK (0x4U) -#define SYSCON_BODCTRL_BODRSTENA_SHIFT (2U) -#define SYSCON_BODCTRL_BODRSTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK) -#define SYSCON_BODCTRL_BODINTLEV_MASK (0x18U) -#define SYSCON_BODCTRL_BODINTLEV_SHIFT (3U) -#define SYSCON_BODCTRL_BODINTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK) -#define SYSCON_BODCTRL_BODINTENA_MASK (0x20U) -#define SYSCON_BODCTRL_BODINTENA_SHIFT (5U) -#define SYSCON_BODCTRL_BODINTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK) -#define SYSCON_BODCTRL_BODRSTSTAT_MASK (0x40U) -#define SYSCON_BODCTRL_BODRSTSTAT_SHIFT (6U) -#define SYSCON_BODCTRL_BODRSTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK) -#define SYSCON_BODCTRL_BODINTSTAT_MASK (0x80U) -#define SYSCON_BODCTRL_BODINTSTAT_SHIFT (7U) -#define SYSCON_BODCTRL_BODINTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SYSCON_Register_Masks */ - - -/* SYSCON - Peripheral instance base addresses */ -/** Peripheral SYSCON base address */ -#define SYSCON_BASE (0x40000000u) -/** Peripheral SYSCON base pointer */ -#define SYSCON ((SYSCON_Type *)SYSCON_BASE) -/** Array initializer of SYSCON peripheral base addresses */ -#define SYSCON_BASE_ADDRS { SYSCON_BASE } -/** Array initializer of SYSCON peripheral base pointers */ -#define SYSCON_BASE_PTRS { SYSCON } - -/*! - * @} - */ /* end of group SYSCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USART Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer - * @{ - */ - -/** USART - Register Layout Typedef */ -typedef struct { - __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ - __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ - __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ - uint8_t RESERVED_0[12]; - __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ - __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ - __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ - __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ - uint8_t RESERVED_1[3536]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_2[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_4[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ -} USART_Type; - -/* ---------------------------------------------------------------------------- - -- USART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Register_Masks USART Register Masks - * @{ - */ - -/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ -/*! @{ */ -#define USART_CFG_ENABLE_MASK (0x1U) -#define USART_CFG_ENABLE_SHIFT (0U) -#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) -#define USART_CFG_DATALEN_MASK (0xCU) -#define USART_CFG_DATALEN_SHIFT (2U) -#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) -#define USART_CFG_PARITYSEL_MASK (0x30U) -#define USART_CFG_PARITYSEL_SHIFT (4U) -#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) -#define USART_CFG_STOPLEN_MASK (0x40U) -#define USART_CFG_STOPLEN_SHIFT (6U) -#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) -#define USART_CFG_MODE32K_MASK (0x80U) -#define USART_CFG_MODE32K_SHIFT (7U) -#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) -#define USART_CFG_LINMODE_MASK (0x100U) -#define USART_CFG_LINMODE_SHIFT (8U) -#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) -#define USART_CFG_CTSEN_MASK (0x200U) -#define USART_CFG_CTSEN_SHIFT (9U) -#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) -#define USART_CFG_SYNCEN_MASK (0x800U) -#define USART_CFG_SYNCEN_SHIFT (11U) -#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) -#define USART_CFG_CLKPOL_MASK (0x1000U) -#define USART_CFG_CLKPOL_SHIFT (12U) -#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) -#define USART_CFG_SYNCMST_MASK (0x4000U) -#define USART_CFG_SYNCMST_SHIFT (14U) -#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) -#define USART_CFG_LOOP_MASK (0x8000U) -#define USART_CFG_LOOP_SHIFT (15U) -#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) -#define USART_CFG_IOMODE_MASK (0x10000U) -#define USART_CFG_IOMODE_SHIFT (16U) -#define USART_CFG_IOMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_IOMODE_SHIFT)) & USART_CFG_IOMODE_MASK) -#define USART_CFG_OETA_MASK (0x40000U) -#define USART_CFG_OETA_SHIFT (18U) -#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) -#define USART_CFG_AUTOADDR_MASK (0x80000U) -#define USART_CFG_AUTOADDR_SHIFT (19U) -#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) -#define USART_CFG_OESEL_MASK (0x100000U) -#define USART_CFG_OESEL_SHIFT (20U) -#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) -#define USART_CFG_OEPOL_MASK (0x200000U) -#define USART_CFG_OEPOL_SHIFT (21U) -#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) -#define USART_CFG_RXPOL_MASK (0x400000U) -#define USART_CFG_RXPOL_SHIFT (22U) -#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) -#define USART_CFG_TXPOL_MASK (0x800000U) -#define USART_CFG_TXPOL_SHIFT (23U) -#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) -/*! @} */ - -/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ -/*! @{ */ -#define USART_CTL_TXBRKEN_MASK (0x2U) -#define USART_CTL_TXBRKEN_SHIFT (1U) -#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) -#define USART_CTL_ADDRDET_MASK (0x4U) -#define USART_CTL_ADDRDET_SHIFT (2U) -#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) -#define USART_CTL_TXDIS_MASK (0x40U) -#define USART_CTL_TXDIS_SHIFT (6U) -#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) -#define USART_CTL_CC_MASK (0x100U) -#define USART_CTL_CC_SHIFT (8U) -#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) -#define USART_CTL_CLRCCONRX_MASK (0x200U) -#define USART_CTL_CLRCCONRX_SHIFT (9U) -#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) -#define USART_CTL_AUTOBAUD_MASK (0x10000U) -#define USART_CTL_AUTOBAUD_SHIFT (16U) -#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) -/*! @} */ - -/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ -/*! @{ */ -#define USART_STAT_RXIDLE_MASK (0x2U) -#define USART_STAT_RXIDLE_SHIFT (1U) -#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) -#define USART_STAT_TXIDLE_MASK (0x8U) -#define USART_STAT_TXIDLE_SHIFT (3U) -#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) -#define USART_STAT_CTS_MASK (0x10U) -#define USART_STAT_CTS_SHIFT (4U) -#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) -#define USART_STAT_DELTACTS_MASK (0x20U) -#define USART_STAT_DELTACTS_SHIFT (5U) -#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) -#define USART_STAT_TXDISSTAT_MASK (0x40U) -#define USART_STAT_TXDISSTAT_SHIFT (6U) -#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) -#define USART_STAT_RXBRK_MASK (0x400U) -#define USART_STAT_RXBRK_SHIFT (10U) -#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) -#define USART_STAT_DELTARXBRK_MASK (0x800U) -#define USART_STAT_DELTARXBRK_SHIFT (11U) -#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) -#define USART_STAT_START_MASK (0x1000U) -#define USART_STAT_START_SHIFT (12U) -#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) -#define USART_STAT_FRAMERRINT_MASK (0x2000U) -#define USART_STAT_FRAMERRINT_SHIFT (13U) -#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) -#define USART_STAT_PARITYERRINT_MASK (0x4000U) -#define USART_STAT_PARITYERRINT_SHIFT (14U) -#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) -#define USART_STAT_RXNOISEINT_MASK (0x8000U) -#define USART_STAT_RXNOISEINT_SHIFT (15U) -#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) -#define USART_STAT_ABERR_MASK (0x10000U) -#define USART_STAT_ABERR_SHIFT (16U) -#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -/*! @{ */ -#define USART_INTENSET_TXIDLEEN_MASK (0x8U) -#define USART_INTENSET_TXIDLEEN_SHIFT (3U) -#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) -#define USART_INTENSET_DELTACTSEN_MASK (0x20U) -#define USART_INTENSET_DELTACTSEN_SHIFT (5U) -#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) -#define USART_INTENSET_TXDISEN_MASK (0x40U) -#define USART_INTENSET_TXDISEN_SHIFT (6U) -#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) -#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) -#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) -#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) -#define USART_INTENSET_STARTEN_MASK (0x1000U) -#define USART_INTENSET_STARTEN_SHIFT (12U) -#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) -#define USART_INTENSET_FRAMERREN_MASK (0x2000U) -#define USART_INTENSET_FRAMERREN_SHIFT (13U) -#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) -#define USART_INTENSET_PARITYERREN_MASK (0x4000U) -#define USART_INTENSET_PARITYERREN_SHIFT (14U) -#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) -#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) -#define USART_INTENSET_RXNOISEEN_SHIFT (15U) -#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) -#define USART_INTENSET_ABERREN_MASK (0x10000U) -#define USART_INTENSET_ABERREN_SHIFT (16U) -#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ -/*! @{ */ -#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) -#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) -#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) -#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) -#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) -#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) -#define USART_INTENCLR_TXDISCLR_MASK (0x40U) -#define USART_INTENCLR_TXDISCLR_SHIFT (6U) -#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) -#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) -#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) -#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) -#define USART_INTENCLR_STARTCLR_MASK (0x1000U) -#define USART_INTENCLR_STARTCLR_SHIFT (12U) -#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) -#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) -#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) -#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) -#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) -#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) -#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) -#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) -#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) -#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) -#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) -#define USART_INTENCLR_ABERRCLR_SHIFT (16U) -#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) -/*! @} */ - -/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ -/*! @{ */ -#define USART_BRG_BRGVAL_MASK (0xFFFFU) -#define USART_BRG_BRGVAL_SHIFT (0U) -#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ -/*! @{ */ -#define USART_INTSTAT_TXIDLE_MASK (0x8U) -#define USART_INTSTAT_TXIDLE_SHIFT (3U) -#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) -#define USART_INTSTAT_DELTACTS_MASK (0x20U) -#define USART_INTSTAT_DELTACTS_SHIFT (5U) -#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) -#define USART_INTSTAT_TXDISINT_MASK (0x40U) -#define USART_INTSTAT_TXDISINT_SHIFT (6U) -#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) -#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) -#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) -#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) -#define USART_INTSTAT_START_MASK (0x1000U) -#define USART_INTSTAT_START_SHIFT (12U) -#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) -#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) -#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) -#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) -#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) -#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) -#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) -#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) -#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) -#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) -#define USART_INTSTAT_ABERRINT_MASK (0x10000U) -#define USART_INTSTAT_ABERRINT_SHIFT (16U) -#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) -/*! @} */ - -/*! @name OSR - Oversample selection register for asynchronous communication. */ -/*! @{ */ -#define USART_OSR_OSRVAL_MASK (0xFU) -#define USART_OSR_OSRVAL_SHIFT (0U) -#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) -/*! @} */ - -/*! @name ADDR - Address register for automatic address matching. */ -/*! @{ */ -#define USART_ADDR_ADDRESS_MASK (0xFFU) -#define USART_ADDR_ADDRESS_SHIFT (0U) -#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ -#define USART_FIFOCFG_ENABLETX_MASK (0x1U) -#define USART_FIFOCFG_ENABLETX_SHIFT (0U) -#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) -#define USART_FIFOCFG_ENABLERX_MASK (0x2U) -#define USART_FIFOCFG_ENABLERX_SHIFT (1U) -#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) -#define USART_FIFOCFG_SIZE_MASK (0x30U) -#define USART_FIFOCFG_SIZE_SHIFT (4U) -#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) -#define USART_FIFOCFG_DMATX_MASK (0x1000U) -#define USART_FIFOCFG_DMATX_SHIFT (12U) -#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) -#define USART_FIFOCFG_DMARX_MASK (0x2000U) -#define USART_FIFOCFG_DMARX_SHIFT (13U) -#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) -#define USART_FIFOCFG_WAKETX_MASK (0x4000U) -#define USART_FIFOCFG_WAKETX_SHIFT (14U) -#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) -#define USART_FIFOCFG_WAKERX_MASK (0x8000U) -#define USART_FIFOCFG_WAKERX_SHIFT (15U) -#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) -#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) -#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) -#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) -#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ -#define USART_FIFOSTAT_TXERR_MASK (0x1U) -#define USART_FIFOSTAT_TXERR_SHIFT (0U) -#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) -#define USART_FIFOSTAT_RXERR_MASK (0x2U) -#define USART_FIFOSTAT_RXERR_SHIFT (1U) -#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) -#define USART_FIFOSTAT_PERINT_MASK (0x8U) -#define USART_FIFOSTAT_PERINT_SHIFT (3U) -#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) -#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) -#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) -#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) -#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) -#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) -#define USART_FIFOSTAT_RXFULL_MASK (0x80U) -#define USART_FIFOSTAT_RXFULL_SHIFT (7U) -#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) -#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define USART_FIFOSTAT_TXLVL_SHIFT (8U) -#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) -#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define USART_FIFOSTAT_RXLVL_SHIFT (16U) -#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ -#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) -#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) -#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) -#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) -#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) -#define USART_FIFOTRIG_TXLVL_SHIFT (8U) -#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) -#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define USART_FIFOTRIG_RXLVL_SHIFT (16U) -#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ -#define USART_FIFOINTENSET_TXERR_MASK (0x1U) -#define USART_FIFOINTENSET_TXERR_SHIFT (0U) -#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) -#define USART_FIFOINTENSET_RXERR_MASK (0x2U) -#define USART_FIFOINTENSET_RXERR_SHIFT (1U) -#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) -#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) -#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) -#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) -#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) -#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) -#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ -#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) -#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) -#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) -#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) -#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) -#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) -#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) -#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) -#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) -#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ -#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) -#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) -#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) -#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) -#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) -#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) -#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) -#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) -#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) -#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) -#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) -#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) -#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ -#define USART_FIFOWR_TXDATA_MASK (0x1FFU) -#define USART_FIFOWR_TXDATA_SHIFT (0U) -#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ -#define USART_FIFORD_RXDATA_MASK (0x1FFU) -#define USART_FIFORD_RXDATA_SHIFT (0U) -#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) -#define USART_FIFORD_FRAMERR_MASK (0x2000U) -#define USART_FIFORD_FRAMERR_SHIFT (13U) -#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) -#define USART_FIFORD_PARITYERR_MASK (0x4000U) -#define USART_FIFORD_PARITYERR_SHIFT (14U) -#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) -#define USART_FIFORD_RXNOISE_MASK (0x8000U) -#define USART_FIFORD_RXNOISE_SHIFT (15U) -#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ -#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) -#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) -#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) -#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) -#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) -#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) -#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) -#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) -#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) -#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) -#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) -#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USART_Register_Masks */ - - -/* USART - Peripheral instance base addresses */ -/** Peripheral USART0 base address */ -#define USART0_BASE (0x40086000u) -/** Peripheral USART0 base pointer */ -#define USART0 ((USART_Type *)USART0_BASE) -/** Peripheral USART1 base address */ -#define USART1_BASE (0x40087000u) -/** Peripheral USART1 base pointer */ -#define USART1 ((USART_Type *)USART1_BASE) -/** Peripheral USART2 base address */ -#define USART2_BASE (0x40088000u) -/** Peripheral USART2 base pointer */ -#define USART2 ((USART_Type *)USART2_BASE) -/** Peripheral USART3 base address */ -#define USART3_BASE (0x40089000u) -/** Peripheral USART3 base pointer */ -#define USART3 ((USART_Type *)USART3_BASE) -/** Peripheral USART4 base address */ -#define USART4_BASE (0x4008A000u) -/** Peripheral USART4 base pointer */ -#define USART4 ((USART_Type *)USART4_BASE) -/** Peripheral USART5 base address */ -#define USART5_BASE (0x40096000u) -/** Peripheral USART5 base pointer */ -#define USART5 ((USART_Type *)USART5_BASE) -/** Peripheral USART6 base address */ -#define USART6_BASE (0x40097000u) -/** Peripheral USART6 base pointer */ -#define USART6 ((USART_Type *)USART6_BASE) -/** Peripheral USART7 base address */ -#define USART7_BASE (0x40098000u) -/** Peripheral USART7 base pointer */ -#define USART7 ((USART_Type *)USART7_BASE) -/** Array initializer of USART peripheral base addresses */ -#define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } -/** Array initializer of USART peripheral base pointers */ -#define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } -/** Interrupt vectors for the USART peripheral type */ -#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group USART_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer - * @{ - */ - -/** USB - Register Layout Typedef */ -typedef struct { - __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ - __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ - __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ - __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ - __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ - __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ - __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ - __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ - __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ - __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ - __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ - uint8_t RESERVED_0[8]; - __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ -} USB_Type; - -/* ---------------------------------------------------------------------------- - -- USB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Register_Masks USB Register Masks - * @{ - */ - -/*! @name DEVCMDSTAT - USB Device Command/Status register */ -/*! @{ */ -#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) -#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) -#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) -#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) -#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) -#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) -#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) -#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) -#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) -#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) -#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) -#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) -#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) -#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) -#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) -#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) -#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) -#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) -#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) -#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) -#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) -#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) -#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) -#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) -#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) -#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) -#define USB_DEVCMDSTAT_DCON_SHIFT (16U) -#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) -#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) -#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) -#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) -#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) -#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) -#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) -#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) -#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) -#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) -#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) -#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) -#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) -#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) -#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) -#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) -#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) -#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) -#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) -/*! @} */ - -/*! @name INFO - USB Info register */ -/*! @{ */ -#define USB_INFO_FRAME_NR_MASK (0x7FFU) -#define USB_INFO_FRAME_NR_SHIFT (0U) -#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) -#define USB_INFO_ERR_CODE_MASK (0x7800U) -#define USB_INFO_ERR_CODE_SHIFT (11U) -#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) -/*! @} */ - -/*! @name EPLISTSTART - USB EP Command/Status List start address */ -/*! @{ */ -#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) -#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) -#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) -/*! @} */ - -/*! @name DATABUFSTART - USB Data buffer start address */ -/*! @{ */ -#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) -#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) -#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) -/*! @} */ - -/*! @name LPM - USB Link Power Management register */ -/*! @{ */ -#define USB_LPM_HIRD_HW_MASK (0xFU) -#define USB_LPM_HIRD_HW_SHIFT (0U) -#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) -#define USB_LPM_HIRD_SW_MASK (0xF0U) -#define USB_LPM_HIRD_SW_SHIFT (4U) -#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) -#define USB_LPM_DATA_PENDING_MASK (0x100U) -#define USB_LPM_DATA_PENDING_SHIFT (8U) -#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) -/*! @} */ - -/*! @name EPSKIP - USB Endpoint skip */ -/*! @{ */ -#define USB_EPSKIP_SKIP_MASK (0x3FFFFFFFU) -#define USB_EPSKIP_SKIP_SHIFT (0U) -#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) -/*! @} */ - -/*! @name EPINUSE - USB Endpoint Buffer in use */ -/*! @{ */ -#define USB_EPINUSE_BUF_MASK (0x3FCU) -#define USB_EPINUSE_BUF_SHIFT (2U) -#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) -/*! @} */ - -/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ -/*! @{ */ -#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) -#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) -#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) -/*! @} */ - -/*! @name INTSTAT - USB interrupt status register */ -/*! @{ */ -#define USB_INTSTAT_EP0OUT_MASK (0x1U) -#define USB_INTSTAT_EP0OUT_SHIFT (0U) -#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) -#define USB_INTSTAT_EP0IN_MASK (0x2U) -#define USB_INTSTAT_EP0IN_SHIFT (1U) -#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) -#define USB_INTSTAT_EP1OUT_MASK (0x4U) -#define USB_INTSTAT_EP1OUT_SHIFT (2U) -#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) -#define USB_INTSTAT_EP1IN_MASK (0x8U) -#define USB_INTSTAT_EP1IN_SHIFT (3U) -#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) -#define USB_INTSTAT_EP2OUT_MASK (0x10U) -#define USB_INTSTAT_EP2OUT_SHIFT (4U) -#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) -#define USB_INTSTAT_EP2IN_MASK (0x20U) -#define USB_INTSTAT_EP2IN_SHIFT (5U) -#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) -#define USB_INTSTAT_EP3OUT_MASK (0x40U) -#define USB_INTSTAT_EP3OUT_SHIFT (6U) -#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) -#define USB_INTSTAT_EP3IN_MASK (0x80U) -#define USB_INTSTAT_EP3IN_SHIFT (7U) -#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) -#define USB_INTSTAT_EP4OUT_MASK (0x100U) -#define USB_INTSTAT_EP4OUT_SHIFT (8U) -#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) -#define USB_INTSTAT_EP4IN_MASK (0x200U) -#define USB_INTSTAT_EP4IN_SHIFT (9U) -#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) -#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) -#define USB_INTSTAT_FRAME_INT_SHIFT (30U) -#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) -#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) -#define USB_INTSTAT_DEV_INT_SHIFT (31U) -#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) -/*! @} */ - -/*! @name INTEN - USB interrupt enable register */ -/*! @{ */ -#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) -#define USB_INTEN_EP_INT_EN_SHIFT (0U) -#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) -#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) -#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) -#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) -#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) -#define USB_INTEN_DEV_INT_EN_SHIFT (31U) -#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) -/*! @} */ - -/*! @name INTSETSTAT - USB set interrupt status register */ -/*! @{ */ -#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) -#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) -#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) -#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) -#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) -#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) -#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) -#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) -#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) -/*! @} */ - -/*! @name EPTOGGLE - USB Endpoint toggle register */ -/*! @{ */ -#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) -#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) -#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USB_Register_Masks */ - - -/* USB - Peripheral instance base addresses */ -/** Peripheral USB0 base address */ -#define USB0_BASE (0x40084000u) -/** Peripheral USB0 base pointer */ -#define USB0 ((USB_Type *)USB0_BASE) -/** Array initializer of USB peripheral base addresses */ -#define USB_BASE_ADDRS { USB0_BASE } -/** Array initializer of USB peripheral base pointers */ -#define USB_BASE_PTRS { USB0 } -/** Interrupt vectors for the USB peripheral type */ -#define USB_IRQS { USB0_IRQn } -#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- UTICK Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer - * @{ - */ - -/** UTICK - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ - __IO uint32_t STAT; /**< Status register., offset: 0x4 */ - __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ - __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ - __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ -} UTICK_Type; - -/* ---------------------------------------------------------------------------- - -- UTICK Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Register_Masks UTICK Register Masks - * @{ - */ - -/*! @name CTRL - Control register. */ -/*! @{ */ -#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) -#define UTICK_CTRL_DELAYVAL_SHIFT (0U) -#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) -#define UTICK_CTRL_REPEAT_MASK (0x80000000U) -#define UTICK_CTRL_REPEAT_SHIFT (31U) -#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) -/*! @} */ - -/*! @name STAT - Status register. */ -/*! @{ */ -#define UTICK_STAT_INTR_MASK (0x1U) -#define UTICK_STAT_INTR_SHIFT (0U) -#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) -#define UTICK_STAT_ACTIVE_MASK (0x2U) -#define UTICK_STAT_ACTIVE_SHIFT (1U) -#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) -/*! @} */ - -/*! @name CFG - Capture configuration register. */ -/*! @{ */ -#define UTICK_CFG_CAPEN0_MASK (0x1U) -#define UTICK_CFG_CAPEN0_SHIFT (0U) -#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) -#define UTICK_CFG_CAPEN1_MASK (0x2U) -#define UTICK_CFG_CAPEN1_SHIFT (1U) -#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) -#define UTICK_CFG_CAPEN2_MASK (0x4U) -#define UTICK_CFG_CAPEN2_SHIFT (2U) -#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) -#define UTICK_CFG_CAPEN3_MASK (0x8U) -#define UTICK_CFG_CAPEN3_SHIFT (3U) -#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) -#define UTICK_CFG_CAPPOL0_MASK (0x100U) -#define UTICK_CFG_CAPPOL0_SHIFT (8U) -#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) -#define UTICK_CFG_CAPPOL1_MASK (0x200U) -#define UTICK_CFG_CAPPOL1_SHIFT (9U) -#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) -#define UTICK_CFG_CAPPOL2_MASK (0x400U) -#define UTICK_CFG_CAPPOL2_SHIFT (10U) -#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) -#define UTICK_CFG_CAPPOL3_MASK (0x800U) -#define UTICK_CFG_CAPPOL3_SHIFT (11U) -#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) -/*! @} */ - -/*! @name CAPCLR - Capture clear register. */ -/*! @{ */ -#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) -#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) -#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) -#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) -#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) -#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) -#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) -#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) -#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) -#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) -#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) -#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) -/*! @} */ - -/*! @name CAP - Capture register . */ -/*! @{ */ -#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) -#define UTICK_CAP_CAP_VALUE_SHIFT (0U) -#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) -#define UTICK_CAP_VALID_MASK (0x80000000U) -#define UTICK_CAP_VALID_SHIFT (31U) -#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) -/*! @} */ - -/* The count of UTICK_CAP */ -#define UTICK_CAP_COUNT (4U) - - -/*! - * @} - */ /* end of group UTICK_Register_Masks */ - - -/* UTICK - Peripheral instance base addresses */ -/** Peripheral UTICK0 base address */ -#define UTICK0_BASE (0x4000E000u) -/** Peripheral UTICK0 base pointer */ -#define UTICK0 ((UTICK_Type *)UTICK0_BASE) -/** Array initializer of UTICK peripheral base addresses */ -#define UTICK_BASE_ADDRS { UTICK0_BASE } -/** Array initializer of UTICK peripheral base pointers */ -#define UTICK_BASE_PTRS { UTICK0 } -/** Interrupt vectors for the UTICK peripheral type */ -#define UTICK_IRQS { UTICK0_IRQn } - -/*! - * @} - */ /* end of group UTICK_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- WWDT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer - * @{ - */ - -/** WWDT - Register Layout Typedef */ -typedef struct { - __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ - __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ - __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ - __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ - uint8_t RESERVED_0[4]; - __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ - __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ -} WWDT_Type; - -/* ---------------------------------------------------------------------------- - -- WWDT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Register_Masks WWDT Register Masks - * @{ - */ - -/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ -/*! @{ */ -#define WWDT_MOD_WDEN_MASK (0x1U) -#define WWDT_MOD_WDEN_SHIFT (0U) -#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) -#define WWDT_MOD_WDRESET_MASK (0x2U) -#define WWDT_MOD_WDRESET_SHIFT (1U) -#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) -#define WWDT_MOD_WDTOF_MASK (0x4U) -#define WWDT_MOD_WDTOF_SHIFT (2U) -#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) -#define WWDT_MOD_WDINT_MASK (0x8U) -#define WWDT_MOD_WDINT_SHIFT (3U) -#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) -#define WWDT_MOD_WDPROTECT_MASK (0x10U) -#define WWDT_MOD_WDPROTECT_SHIFT (4U) -#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) -#define WWDT_MOD_LOCK_MASK (0x20U) -#define WWDT_MOD_LOCK_SHIFT (5U) -#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) -/*! @} */ - -/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ -/*! @{ */ -#define WWDT_TC_COUNT_MASK (0xFFFFFFU) -#define WWDT_TC_COUNT_SHIFT (0U) -#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) -/*! @} */ - -/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ -/*! @{ */ -#define WWDT_FEED_FEED_MASK (0xFFU) -#define WWDT_FEED_FEED_SHIFT (0U) -#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) -/*! @} */ - -/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ -/*! @{ */ -#define WWDT_TV_COUNT_MASK (0xFFFFFFU) -#define WWDT_TV_COUNT_SHIFT (0U) -#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) -/*! @} */ - -/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ -/*! @{ */ -#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) -#define WWDT_WARNINT_WARNINT_SHIFT (0U) -#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) -/*! @} */ - -/*! @name WINDOW - Watchdog Window compare value. */ -/*! @{ */ -#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) -#define WWDT_WINDOW_WINDOW_SHIFT (0U) -#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group WWDT_Register_Masks */ - - -/* WWDT - Peripheral instance base addresses */ -/** Peripheral WWDT base address */ -#define WWDT_BASE (0x4000C000u) -/** Peripheral WWDT base pointer */ -#define WWDT ((WWDT_Type *)WWDT_BASE) -/** Array initializer of WWDT peripheral base addresses */ -#define WWDT_BASE_ADDRS { WWDT_BASE } -/** Array initializer of WWDT peripheral base pointers */ -#define WWDT_BASE_PTRS { WWDT } -/** Interrupt vectors for the WWDT peripheral type */ -#define WWDT_IRQS { WDT_BOD_IRQn } - -/*! - * @} - */ /* end of group WWDT_Peripheral_Access_Layer */ - - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop - #else - #pragma pop - #endif -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -/*! - * @} - */ /* end of group Peripheral_access_layer */ - - -/* ---------------------------------------------------------------------------- - -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - * @{ - */ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang system_header - #endif -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma system_include -#endif - -/** - * @brief Mask and left-shift a bit field value for use in a register bit range. - * @param field Name of the register bit field. - * @param value Value of the bit field. - * @return Masked and shifted value. - */ -#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) -/** - * @brief Mask and right-shift a register value to extract a bit field value. - * @param field Name of the register bit field. - * @param value Value of the register. - * @return Masked and shifted bit field value. - */ -#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) - -/*! - * @} - */ /* end of group Bit_Field_Generic_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SDK Compatibility - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDK_Compatibility_Symbols SDK Compatibility - * @{ - */ - -/* No SDK compatibility issues. */ - -/*! - * @} - */ /* end of group SDK_Compatibility_Symbols */ - - -#endif /* _LPC54114_CM0PLUS_H_ */ - diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm0plus_features.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm0plus_features.h deleted file mode 100644 index a13ad9a40b7..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm0plus_features.h +++ /dev/null @@ -1,249 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2016-05-09 -** Build: b180327 -** -** Abstract: -** Chip specific module features. -** -** The Clear BSD License -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without -** modification, are permitted (subject to the limitations in the -** disclaimer below) provided that the following conditions are met: -** -** * Redistributions of source code must retain the above copyright -** notice, this list of conditions and the following disclaimer. -** -** * Redistributions in binary form must reproduce the above copyright -** notice, this list of conditions and the following disclaimer in the -** documentation and/or other materials provided with the distribution. -** -** * Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from -** this software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2016-05-09) -** Initial version. -** -** ################################################################### -*/ - -#ifndef _LPC54114_cm0plus_FEATURES_H_ -#define _LPC54114_cm0plus_FEATURES_H_ - -/* SOC module features */ - -/* @brief ADC availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC_COUNT (1) -/* @brief ASYNC_SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1) -/* @brief CRC availability on the SoC. */ -#define FSL_FEATURE_SOC_CRC_COUNT (1) -/* @brief CTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_CTIMER_COUNT (5) -/* @brief DMA availability on the SoC. */ -#define FSL_FEATURE_SOC_DMA_COUNT (1) -/* @brief DMIC availability on the SoC. */ -#define FSL_FEATURE_SOC_DMIC_COUNT (1) -/* @brief FLEXCOMM availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (8) -/* @brief GINT availability on the SoC. */ -#define FSL_FEATURE_SOC_GINT_COUNT (2) -/* @brief GPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_GPIO_COUNT (1) -/* @brief I2C availability on the SoC. */ -#define FSL_FEATURE_SOC_I2C_COUNT (8) -/* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (2) -/* @brief INPUTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) -/* @brief IOCON availability on the SoC. */ -#define FSL_FEATURE_SOC_IOCON_COUNT (1) -/* @brief MAILBOX availability on the SoC. */ -#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) -/* @brief MRT availability on the SoC. */ -#define FSL_FEATURE_SOC_MRT_COUNT (1) -/* @brief PINT availability on the SoC. */ -#define FSL_FEATURE_SOC_PINT_COUNT (1) -/* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (1) -/* @brief SCT availability on the SoC. */ -#define FSL_FEATURE_SOC_SCT_COUNT (1) -/* @brief SPI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPI_COUNT (8) -/* @brief SPIFI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPIFI_COUNT (1) -/* @brief SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCON_COUNT (1) -/* @brief USART availability on the SoC. */ -#define FSL_FEATURE_SOC_USART_COUNT (8) -/* @brief USB availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_COUNT (1) -/* @brief UTICK availability on the SoC. */ -#define FSL_FEATURE_SOC_UTICK_COUNT (1) -/* @brief WWDT availability on the SoC. */ -#define FSL_FEATURE_SOC_WWDT_COUNT (1) - -/* ADC module features */ - -/* @brief Do not has input select (register INSEL). */ -#define FSL_FEATURE_ADC_HAS_NO_INSEL (0) -/* @brief Has ASYNMODE bitfile in CTRL reigster. */ -#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1) -/* @brief Has ASYNMODE bitfile in CTRL reigster. */ -#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1) -/* @brief Has ASYNMODE bitfile in CTRL reigster. */ -#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1) -/* @brief Has ASYNMODE bitfile in CTRL reigster. */ -#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1) -/* @brief Has ASYNMODE bitfile in CTRL reigster. */ -#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0) -/* @brief Has ASYNMODE bitfile in CTRL reigster. */ -#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0) -/* @brief Has startup register. */ -#define FSL_FEATURE_ADC_HAS_STARTUP_REG (1) -/* @brief Has ADTrim register */ -#define FSL_FEATURE_ADC_HAS_TRIM_REG (0) -/* @brief Has Calibration register. */ -#define FSL_FEATURE_ADC_HAS_CALIB_REG (1) - -/* DMA module features */ - -/* @brief Number of channels */ -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (20) - -/* FLEXCOMM module features */ - -/* @brief FLEXCOMM0 USART INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) -/* @brief FLEXCOMM0 SPI INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) -/* @brief FLEXCOMM0 I2C INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) -/* @brief FLEXCOMM1 USART INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) -/* @brief FLEXCOMM1 SPI INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) -/* @brief FLEXCOMM1 I2C INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) -/* @brief FLEXCOMM2 USART INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) -/* @brief FLEXCOMM2 SPI INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) -/* @brief FLEXCOMM2 I2C INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) -/* @brief FLEXCOMM3 USART INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) -/* @brief FLEXCOMM3 SPI INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) -/* @brief FLEXCOMM3 I2C INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) -/* @brief FLEXCOMM4 USART INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) -/* @brief FLEXCOMM4 SPI INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) -/* @brief FLEXCOMM4 I2C INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) -/* @brief FLEXCOMM5 USART INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) -/* @brief FLEXCOMM5 SPI INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) -/* @brief FLEXCOMM5 I2C INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) -/* @brief FLEXCOMM6 USART INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) -/* @brief FLEXCOMM6 SPI INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) -/* @brief FLEXCOMM6 I2C INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) -/* @brief FLEXCOMM7 I2S INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (0) -/* @brief FLEXCOMM7 USART INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) -/* @brief FLEXCOMM7 SPI INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) -/* @brief FLEXCOMM7 I2C INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) -/* @brief FLEXCOMM7 I2S INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (1) - -/* MAILBOX module features */ - -/* @brief Mailbox side for current core. */ -#define FSL_FEATURE_MAILBOX_SIDE_B (1) - -/* MRT module features */ - -/* @brief number of channels. */ -#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) - -/* interrupt module features */ - -/* @brief Lowest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) -/* @brief Highest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105) - -/* PINT module features */ - -/* @brief Number of connected outputs */ -#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (4) - -/* SCT module features */ - -/* @brief Number of events */ -#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (10) -/* @brief Number of states */ -#define FSL_FEATURE_SCT_NUMBER_OF_STATES (10) -/* @brief Number of match capture */ -#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) -/* @brief Number of outputs */ -#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (8) - -/* SYSCON module features */ - -/* @brief Pointer to ROM IAP entry functions */ -#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205) -/* @brief Flash page size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256) -/* @brief Flash sector size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) -/* @brief Flash size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (262144) - -/* SysTick module features */ - -/* @brief Systick has external reference clock. */ -#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) -/* @brief Systick external reference clock is core clock divided by this value. */ -#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) - -/* USB module features */ - -/* @brief Number of the endpoint in USB FS */ -#define FSL_FEATURE_USB_EP_NUM (5) - -#endif /* _LPC54114_cm0plus_FEATURES_H_ */ - diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm4.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm4.h deleted file mode 100644 index 8b46983446b..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm4.h +++ /dev/null @@ -1,7116 +0,0 @@ -/* -** ################################################################### -** Processors: LPC54114J256BD64_cm4 -** LPC54114J256UK49_cm4 -** -** Compilers: Keil ARM C/C++ Compiler -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 -** Version: rev. 1.0, 2016-04-29 -** Build: b180227 -** -** Abstract: -** CMSIS Peripheral Access Layer for LPC54114_cm4 -** -** The Clear BSD License -** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without -** modification, are permitted (subject to the limitations in the -** disclaimer below) provided that the following conditions are met: -** -** * Redistributions of source code must retain the above copyright -** notice, this list of conditions and the following disclaimer. -** -** * Redistributions in binary form must reproduce the above copyright -** notice, this list of conditions and the following disclaimer in the -** documentation and/or other materials provided with the distribution. -** -** * Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from -** this software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2016-04-29) -** Initial version. -** -** ################################################################### -*/ - -/*! - * @file LPC54114_cm4.h - * @version 1.0 - * @date 2016-04-29 - * @brief CMSIS Peripheral Access Layer for LPC54114_cm4 - * - * CMSIS Peripheral Access Layer for LPC54114_cm4 - */ - -#ifndef _LPC54114_CM4_H_ -#define _LPC54114_CM4_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0000U - - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 56 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Auxiliary constants */ - NotAvail_IRQn = -128, /**< Not available device specific interrupt */ - - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ - - /* Device specific interrupts */ - WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */ - DMA0_IRQn = 1, /**< DMA controller */ - GINT0_IRQn = 2, /**< GPIO group 0 */ - GINT1_IRQn = 3, /**< GPIO group 1 */ - PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ - PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ - PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ - PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ - UTICK0_IRQn = 8, /**< Micro-tick Timer */ - MRT0_IRQn = 9, /**< Multi-rate timer */ - CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ - CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ - SCT0_IRQn = 12, /**< SCTimer/PWM */ - CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ - FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C) */ - FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C) */ - FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C) */ - FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C) */ - FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C) */ - FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C) */ - FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S) */ - FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S) */ - ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */ - ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */ - ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */ - DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */ - HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */ - USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ - USB0_IRQn = 28, /**< USB device */ - RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ - IOH_IRQn = 30, /**< IOH */ - MAILBOX_IRQn = 31, /**< Mailbox interrupt (present on selected devices) */ - PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ - PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ - PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ - PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ - CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ - CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ - Reserved54_IRQn = 38, /**< Reserved interrupt */ - SPIFI0_IRQn = 39 /**< SPI flash interface */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M4 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration - * @{ - */ - -#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ -#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ - -#include "core_cm4.h" /* Core Peripheral Access Layer */ -#include "system_LPC54114_cm4.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Mapping Information - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Mapping_Information Mapping Information - * @{ - */ - -/** Mapping Information */ -/*! - * @addtogroup dma_request - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief Structure for the DMA hardware request - * - * Defines the structure for the DMA hardware request collections. The user can configure the - * hardware request to trigger the DMA transfer accordingly. The index - * of the hardware request varies according to the to SoC. - */ -typedef enum _dma_request_source -{ - kDmaRequestFlexcomm0Rx = 0U, /**< Flexcomm Interface 0 RX/I2C Slave */ - kDmaRequestFlexcomm0Tx = 1U, /**< Flexcomm Interface 0 TX/I2C Master */ - kDmaRequestFlexcomm1Rx = 2U, /**< Flexcomm Interface 1 RX/I2C Slave */ - kDmaRequestFlexcomm1Tx = 3U, /**< Flexcomm Interface 1 TX/I2C Master */ - kDmaRequestFlexcomm2Rx = 4U, /**< Flexcomm Interface 2 RX/I2C Slave */ - kDmaRequestFlexcomm2Tx = 5U, /**< Flexcomm Interface 2 TX/I2C Master */ - kDmaRequestFlexcomm3Rx = 6U, /**< Flexcomm Interface 3 RX/I2C Slave */ - kDmaRequestFlexcomm3Tx = 7U, /**< Flexcomm Interface 3 TX/I2C Master */ - kDmaRequestFlexcomm4Rx = 8U, /**< Flexcomm Interface 4 RX/I2C Slave */ - kDmaRequestFlexcomm4Tx = 9U, /**< Flexcomm Interface 4 TX/I2C Master */ - kDmaRequestFlexcomm5Rx = 10U, /**< Flexcomm Interface 5 RX/I2C Slave */ - kDmaRequestFlexcomm5Tx = 11U, /**< Flexcomm Interface 5 TX/I2C Master */ - kDmaRequestFlexcomm6Rx = 12U, /**< Flexcomm Interface 6 RX/I2C Slave */ - kDmaRequestFlexcomm6Tx = 13U, /**< Flexcomm Interface 6 TX/I2C Master */ - kDmaRequestFlexcomm7Rx = 14U, /**< Flexcomm Interface 7 RX/I2C Slave */ - kDmaRequestFlexcomm7Tx = 15U, /**< Flexcomm Interface 7 TX/I2C Master */ - kDmaRequestDMIC0 = 16U, /**< Digital microphone interface 0 */ - kDmaRequestDMIC1 = 17U, /**< Digital microphone interface 1 */ - kDmaRequestNoDMARequest18 = 18U, /**< No DMA request 18 */ - kDmaRequestNoDMARequest19 = 19U, /**< No DMA request 19 */ -} dma_request_source_t; - -/* @} */ - - -/*! - * @} - */ /* end of group Mapping_Information */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #else - #pragma push - #pragma anon_unions - #endif -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */ - __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */ - __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */ - __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */ - uint8_t RESERVED_0[8]; - __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */ - __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */ - __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */ - __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */ - __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */ - __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */ - __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */ - __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */ - __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */ - __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */ -/*! @{ */ -#define ADC_CTRL_CLKDIV_MASK (0xFFU) -#define ADC_CTRL_CLKDIV_SHIFT (0U) -#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK) -#define ADC_CTRL_ASYNMODE_MASK (0x100U) -#define ADC_CTRL_ASYNMODE_SHIFT (8U) -#define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK) -#define ADC_CTRL_RESOL_MASK (0x600U) -#define ADC_CTRL_RESOL_SHIFT (9U) -#define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK) -#define ADC_CTRL_BYPASSCAL_MASK (0x800U) -#define ADC_CTRL_BYPASSCAL_SHIFT (11U) -#define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK) -#define ADC_CTRL_TSAMP_MASK (0x7000U) -#define ADC_CTRL_TSAMP_SHIFT (12U) -#define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK) -/*! @} */ - -/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */ -/*! @{ */ -#define ADC_INSEL_SEL_MASK (0x3U) -#define ADC_INSEL_SEL_SHIFT (0U) -#define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK) -/*! @} */ - -/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */ -/*! @{ */ -#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU) -#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U) -#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK) -#define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U) -#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U) -#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK) -#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U) -#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U) -#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK) -#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U) -#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U) -#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK) -#define ADC_SEQ_CTRL_START_MASK (0x4000000U) -#define ADC_SEQ_CTRL_START_SHIFT (26U) -#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK) -#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U) -#define ADC_SEQ_CTRL_BURST_SHIFT (27U) -#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK) -#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U) -#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U) -#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK) -#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U) -#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U) -#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK) -#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U) -#define ADC_SEQ_CTRL_MODE_SHIFT (30U) -#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK) -#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U) -#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U) -#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK) -/*! @} */ - -/* The count of ADC_SEQ_CTRL */ -#define ADC_SEQ_CTRL_COUNT (2U) - -/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */ -/*! @{ */ -#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U) -#define ADC_SEQ_GDAT_RESULT_SHIFT (4U) -#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK) -#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U) -#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U) -#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK) -#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U) -#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U) -#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK) -#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U) -#define ADC_SEQ_GDAT_CHN_SHIFT (26U) -#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK) -#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U) -#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U) -#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK) -#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U) -#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U) -#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK) -/*! @} */ - -/* The count of ADC_SEQ_GDAT */ -#define ADC_SEQ_GDAT_COUNT (2U) - -/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */ -/*! @{ */ -#define ADC_DAT_RESULT_MASK (0xFFF0U) -#define ADC_DAT_RESULT_SHIFT (4U) -#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK) -#define ADC_DAT_THCMPRANGE_MASK (0x30000U) -#define ADC_DAT_THCMPRANGE_SHIFT (16U) -#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK) -#define ADC_DAT_THCMPCROSS_MASK (0xC0000U) -#define ADC_DAT_THCMPCROSS_SHIFT (18U) -#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK) -#define ADC_DAT_CHANNEL_MASK (0x3C000000U) -#define ADC_DAT_CHANNEL_SHIFT (26U) -#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK) -#define ADC_DAT_OVERRUN_MASK (0x40000000U) -#define ADC_DAT_OVERRUN_SHIFT (30U) -#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK) -#define ADC_DAT_DATAVALID_MASK (0x80000000U) -#define ADC_DAT_DATAVALID_SHIFT (31U) -#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK) -/*! @} */ - -/* The count of ADC_DAT */ -#define ADC_DAT_COUNT (12U) - -/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ -/*! @{ */ -#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U) -#define ADC_THR0_LOW_THRLOW_SHIFT (4U) -#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK) -/*! @} */ - -/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ -/*! @{ */ -#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U) -#define ADC_THR1_LOW_THRLOW_SHIFT (4U) -#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK) -/*! @} */ - -/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ -/*! @{ */ -#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U) -#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U) -#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK) -/*! @} */ - -/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ -/*! @{ */ -#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U) -#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U) -#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK) -/*! @} */ - -/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */ -/*! @{ */ -#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U) -#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U) -#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U) -#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U) -#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U) -#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U) -#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U) -#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U) -#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U) -#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U) -#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U) -#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U) -#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U) -#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U) -#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U) -#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U) -#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U) -#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U) -#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U) -#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U) -#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U) -#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U) -#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U) -#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U) -#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK) -/*! @} */ - -/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */ -/*! @{ */ -#define ADC_INTEN_SEQA_INTEN_MASK (0x1U) -#define ADC_INTEN_SEQA_INTEN_SHIFT (0U) -#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK) -#define ADC_INTEN_SEQB_INTEN_MASK (0x2U) -#define ADC_INTEN_SEQB_INTEN_SHIFT (1U) -#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK) -#define ADC_INTEN_OVR_INTEN_MASK (0x4U) -#define ADC_INTEN_OVR_INTEN_SHIFT (2U) -#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK) -#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U) -#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U) -#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK) -#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U) -#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U) -#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK) -#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U) -#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U) -#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK) -#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U) -#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U) -#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK) -#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U) -#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U) -#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK) -#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U) -#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U) -#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK) -#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U) -#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U) -#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK) -#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U) -#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U) -#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK) -#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U) -#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U) -#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK) -#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U) -#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U) -#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK) -#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U) -#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U) -#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK) -#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U) -#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U) -#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK) -/*! @} */ - -/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */ -/*! @{ */ -#define ADC_FLAGS_THCMP0_MASK (0x1U) -#define ADC_FLAGS_THCMP0_SHIFT (0U) -#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK) -#define ADC_FLAGS_THCMP1_MASK (0x2U) -#define ADC_FLAGS_THCMP1_SHIFT (1U) -#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK) -#define ADC_FLAGS_THCMP2_MASK (0x4U) -#define ADC_FLAGS_THCMP2_SHIFT (2U) -#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK) -#define ADC_FLAGS_THCMP3_MASK (0x8U) -#define ADC_FLAGS_THCMP3_SHIFT (3U) -#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK) -#define ADC_FLAGS_THCMP4_MASK (0x10U) -#define ADC_FLAGS_THCMP4_SHIFT (4U) -#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK) -#define ADC_FLAGS_THCMP5_MASK (0x20U) -#define ADC_FLAGS_THCMP5_SHIFT (5U) -#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK) -#define ADC_FLAGS_THCMP6_MASK (0x40U) -#define ADC_FLAGS_THCMP6_SHIFT (6U) -#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK) -#define ADC_FLAGS_THCMP7_MASK (0x80U) -#define ADC_FLAGS_THCMP7_SHIFT (7U) -#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK) -#define ADC_FLAGS_THCMP8_MASK (0x100U) -#define ADC_FLAGS_THCMP8_SHIFT (8U) -#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK) -#define ADC_FLAGS_THCMP9_MASK (0x200U) -#define ADC_FLAGS_THCMP9_SHIFT (9U) -#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK) -#define ADC_FLAGS_THCMP10_MASK (0x400U) -#define ADC_FLAGS_THCMP10_SHIFT (10U) -#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK) -#define ADC_FLAGS_THCMP11_MASK (0x800U) -#define ADC_FLAGS_THCMP11_SHIFT (11U) -#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK) -#define ADC_FLAGS_OVERRUN0_MASK (0x1000U) -#define ADC_FLAGS_OVERRUN0_SHIFT (12U) -#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK) -#define ADC_FLAGS_OVERRUN1_MASK (0x2000U) -#define ADC_FLAGS_OVERRUN1_SHIFT (13U) -#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK) -#define ADC_FLAGS_OVERRUN2_MASK (0x4000U) -#define ADC_FLAGS_OVERRUN2_SHIFT (14U) -#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK) -#define ADC_FLAGS_OVERRUN3_MASK (0x8000U) -#define ADC_FLAGS_OVERRUN3_SHIFT (15U) -#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK) -#define ADC_FLAGS_OVERRUN4_MASK (0x10000U) -#define ADC_FLAGS_OVERRUN4_SHIFT (16U) -#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK) -#define ADC_FLAGS_OVERRUN5_MASK (0x20000U) -#define ADC_FLAGS_OVERRUN5_SHIFT (17U) -#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK) -#define ADC_FLAGS_OVERRUN6_MASK (0x40000U) -#define ADC_FLAGS_OVERRUN6_SHIFT (18U) -#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK) -#define ADC_FLAGS_OVERRUN7_MASK (0x80000U) -#define ADC_FLAGS_OVERRUN7_SHIFT (19U) -#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK) -#define ADC_FLAGS_OVERRUN8_MASK (0x100000U) -#define ADC_FLAGS_OVERRUN8_SHIFT (20U) -#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK) -#define ADC_FLAGS_OVERRUN9_MASK (0x200000U) -#define ADC_FLAGS_OVERRUN9_SHIFT (21U) -#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK) -#define ADC_FLAGS_OVERRUN10_MASK (0x400000U) -#define ADC_FLAGS_OVERRUN10_SHIFT (22U) -#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK) -#define ADC_FLAGS_OVERRUN11_MASK (0x800000U) -#define ADC_FLAGS_OVERRUN11_SHIFT (23U) -#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK) -#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U) -#define ADC_FLAGS_SEQA_OVR_SHIFT (24U) -#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK) -#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U) -#define ADC_FLAGS_SEQB_OVR_SHIFT (25U) -#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK) -#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U) -#define ADC_FLAGS_SEQA_INT_SHIFT (28U) -#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK) -#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U) -#define ADC_FLAGS_SEQB_INT_SHIFT (29U) -#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK) -#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U) -#define ADC_FLAGS_THCMP_INT_SHIFT (30U) -#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK) -#define ADC_FLAGS_OVR_INT_MASK (0x80000000U) -#define ADC_FLAGS_OVR_INT_SHIFT (31U) -#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK) -/*! @} */ - -/*! @name STARTUP - ADC Startup register. */ -/*! @{ */ -#define ADC_STARTUP_ADC_ENA_MASK (0x1U) -#define ADC_STARTUP_ADC_ENA_SHIFT (0U) -#define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK) -#define ADC_STARTUP_ADC_INIT_MASK (0x2U) -#define ADC_STARTUP_ADC_INIT_SHIFT (1U) -#define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK) -/*! @} */ - -/*! @name CALIB - ADC Calibration register. */ -/*! @{ */ -#define ADC_CALIB_CALIB_MASK (0x1U) -#define ADC_CALIB_CALIB_SHIFT (0U) -#define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK) -#define ADC_CALIB_CALREQD_MASK (0x2U) -#define ADC_CALIB_CALREQD_SHIFT (1U) -#define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK) -#define ADC_CALIB_CALVALUE_MASK (0x1FCU) -#define ADC_CALIB_CALVALUE_SHIFT (2U) -#define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ADC_Register_Masks */ - - -/* ADC - Peripheral instance base addresses */ -/** Peripheral ADC0 base address */ -#define ADC0_BASE (0x400A0000u) -/** Peripheral ADC0 base pointer */ -#define ADC0 ((ADC_Type *)ADC0_BASE) -/** Array initializer of ADC peripheral base addresses */ -#define ADC_BASE_ADDRS { ADC0_BASE } -/** Array initializer of ADC peripheral base pointers */ -#define ADC_BASE_PTRS { ADC0 } -/** Interrupt vectors for the ADC peripheral type */ -#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn } -#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn } - -/*! - * @} - */ /* end of group ADC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ASYNC_SYSCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer - * @{ - */ - -/** ASYNC_SYSCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */ - __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */ - __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */ - __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */ - __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */ - uint8_t RESERVED_1[4]; - __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */ -} ASYNC_SYSCON_Type; - -/* ---------------------------------------------------------------------------- - -- ASYNC_SYSCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks - * @{ - */ - -/*! @name ASYNCPRESETCTRL - Async peripheral reset control */ -/*! @{ */ -#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U) -#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U) -#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK) -#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U) -#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U) -#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK) -/*! @} */ - -/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */ -/*! @{ */ -#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU) -#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U) -#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK) -/*! @} */ - -/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */ -/*! @{ */ -#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU) -#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U) -#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK) -/*! @} */ - -/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */ -/*! @{ */ -#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK) -/*! @} */ - -/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */ -/*! @{ */ -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK) -/*! @} */ - -/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */ -/*! @{ */ -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK) -/*! @} */ - -/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */ -/*! @{ */ -#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U) -#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U) -#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ASYNC_SYSCON_Register_Masks */ - - -/* ASYNC_SYSCON - Peripheral instance base addresses */ -/** Peripheral ASYNC_SYSCON base address */ -#define ASYNC_SYSCON_BASE (0x40040000u) -/** Peripheral ASYNC_SYSCON base pointer */ -#define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE) -/** Array initializer of ASYNC_SYSCON peripheral base addresses */ -#define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE } -/** Array initializer of ASYNC_SYSCON peripheral base pointers */ -#define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON } - -/*! - * @} - */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CRC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer - * @{ - */ - -/** CRC - Register Layout Typedef */ -typedef struct { - __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ - __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ - union { /* offset: 0x8 */ - __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ - __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ - }; -} CRC_Type; - -/* ---------------------------------------------------------------------------- - -- CRC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Register_Masks CRC Register Masks - * @{ - */ - -/*! @name MODE - CRC mode register */ -/*! @{ */ -#define CRC_MODE_CRC_POLY_MASK (0x3U) -#define CRC_MODE_CRC_POLY_SHIFT (0U) -#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) -#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) -#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) -#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) -#define CRC_MODE_CMPL_WR_MASK (0x8U) -#define CRC_MODE_CMPL_WR_SHIFT (3U) -#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) -#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) -#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) -#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) -#define CRC_MODE_CMPL_SUM_MASK (0x20U) -#define CRC_MODE_CMPL_SUM_SHIFT (5U) -#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) -/*! @} */ - -/*! @name SEED - CRC seed register */ -/*! @{ */ -#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) -#define CRC_SEED_CRC_SEED_SHIFT (0U) -#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) -/*! @} */ - -/*! @name SUM - CRC checksum register */ -/*! @{ */ -#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) -#define CRC_SUM_CRC_SUM_SHIFT (0U) -#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) -/*! @} */ - -/*! @name WR_DATA - CRC data register */ -/*! @{ */ -#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) -#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) -#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CRC_Register_Masks */ - - -/* CRC - Peripheral instance base addresses */ -/** Peripheral CRC_ENGINE base address */ -#define CRC_ENGINE_BASE (0x40095000u) -/** Peripheral CRC_ENGINE base pointer */ -#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) -/** Array initializer of CRC peripheral base addresses */ -#define CRC_BASE_ADDRS { CRC_ENGINE_BASE } -/** Array initializer of CRC peripheral base pointers */ -#define CRC_BASE_PTRS { CRC_ENGINE } - -/*! - * @} - */ /* end of group CRC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CTIMER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer - * @{ - */ - -/** CTIMER - Register Layout Typedef */ -typedef struct { - __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ - __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ - __IO uint32_t TC; /**< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR., offset: 0x8 */ - __IO uint32_t PR; /**< Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC., offset: 0xC */ - __IO uint32_t PC; /**< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface., offset: 0x10 */ - __IO uint32_t MCR; /**< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs., offset: 0x14 */ - __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ - __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ - __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ - __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ - uint8_t RESERVED_0[48]; - __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ - __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */ -} CTIMER_Type; - -/* ---------------------------------------------------------------------------- - -- CTIMER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Register_Masks CTIMER Register Masks - * @{ - */ - -/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ -/*! @{ */ -#define CTIMER_IR_MR0INT_MASK (0x1U) -#define CTIMER_IR_MR0INT_SHIFT (0U) -#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) -#define CTIMER_IR_MR1INT_MASK (0x2U) -#define CTIMER_IR_MR1INT_SHIFT (1U) -#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) -#define CTIMER_IR_MR2INT_MASK (0x4U) -#define CTIMER_IR_MR2INT_SHIFT (2U) -#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) -#define CTIMER_IR_MR3INT_MASK (0x8U) -#define CTIMER_IR_MR3INT_SHIFT (3U) -#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) -#define CTIMER_IR_CR0INT_MASK (0x10U) -#define CTIMER_IR_CR0INT_SHIFT (4U) -#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) -#define CTIMER_IR_CR1INT_MASK (0x20U) -#define CTIMER_IR_CR1INT_SHIFT (5U) -#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) -#define CTIMER_IR_CR2INT_MASK (0x40U) -#define CTIMER_IR_CR2INT_SHIFT (6U) -#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) -#define CTIMER_IR_CR3INT_MASK (0x80U) -#define CTIMER_IR_CR3INT_SHIFT (7U) -#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) -/*! @} */ - -/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ -/*! @{ */ -#define CTIMER_TCR_CEN_MASK (0x1U) -#define CTIMER_TCR_CEN_SHIFT (0U) -#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) -#define CTIMER_TCR_CRST_MASK (0x2U) -#define CTIMER_TCR_CRST_SHIFT (1U) -#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) -/*! @} */ - -/*! @name TC - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR. */ -/*! @{ */ -#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_TC_TCVAL_SHIFT (0U) -#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) -/*! @} */ - -/*! @name PR - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. */ -/*! @{ */ -#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PR_PRVAL_SHIFT (0U) -#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) -/*! @} */ - -/*! @name PC - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */ -/*! @{ */ -#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PC_PCVAL_SHIFT (0U) -#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) -/*! @} */ - -/*! @name MCR - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */ -/*! @{ */ -#define CTIMER_MCR_MR0I_MASK (0x1U) -#define CTIMER_MCR_MR0I_SHIFT (0U) -#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) -#define CTIMER_MCR_MR0R_MASK (0x2U) -#define CTIMER_MCR_MR0R_SHIFT (1U) -#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) -#define CTIMER_MCR_MR0S_MASK (0x4U) -#define CTIMER_MCR_MR0S_SHIFT (2U) -#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) -#define CTIMER_MCR_MR1I_MASK (0x8U) -#define CTIMER_MCR_MR1I_SHIFT (3U) -#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) -#define CTIMER_MCR_MR1R_MASK (0x10U) -#define CTIMER_MCR_MR1R_SHIFT (4U) -#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) -#define CTIMER_MCR_MR1S_MASK (0x20U) -#define CTIMER_MCR_MR1S_SHIFT (5U) -#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) -#define CTIMER_MCR_MR2I_MASK (0x40U) -#define CTIMER_MCR_MR2I_SHIFT (6U) -#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) -#define CTIMER_MCR_MR2R_MASK (0x80U) -#define CTIMER_MCR_MR2R_SHIFT (7U) -#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) -#define CTIMER_MCR_MR2S_MASK (0x100U) -#define CTIMER_MCR_MR2S_SHIFT (8U) -#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) -#define CTIMER_MCR_MR3I_MASK (0x200U) -#define CTIMER_MCR_MR3I_SHIFT (9U) -#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) -#define CTIMER_MCR_MR3R_MASK (0x400U) -#define CTIMER_MCR_MR3R_SHIFT (10U) -#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) -#define CTIMER_MCR_MR3S_MASK (0x800U) -#define CTIMER_MCR_MR3S_SHIFT (11U) -#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) -/*! @} */ - -/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ -/*! @{ */ -#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) -#define CTIMER_MR_MATCH_SHIFT (0U) -#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) -/*! @} */ - -/* The count of CTIMER_MR */ -#define CTIMER_MR_COUNT (4U) - -/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ -/*! @{ */ -#define CTIMER_CCR_CAP0RE_MASK (0x1U) -#define CTIMER_CCR_CAP0RE_SHIFT (0U) -#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) -#define CTIMER_CCR_CAP0FE_MASK (0x2U) -#define CTIMER_CCR_CAP0FE_SHIFT (1U) -#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) -#define CTIMER_CCR_CAP0I_MASK (0x4U) -#define CTIMER_CCR_CAP0I_SHIFT (2U) -#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) -#define CTIMER_CCR_CAP1RE_MASK (0x8U) -#define CTIMER_CCR_CAP1RE_SHIFT (3U) -#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) -#define CTIMER_CCR_CAP1FE_MASK (0x10U) -#define CTIMER_CCR_CAP1FE_SHIFT (4U) -#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) -#define CTIMER_CCR_CAP1I_MASK (0x20U) -#define CTIMER_CCR_CAP1I_SHIFT (5U) -#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) -#define CTIMER_CCR_CAP2RE_MASK (0x40U) -#define CTIMER_CCR_CAP2RE_SHIFT (6U) -#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) -#define CTIMER_CCR_CAP2FE_MASK (0x80U) -#define CTIMER_CCR_CAP2FE_SHIFT (7U) -#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) -#define CTIMER_CCR_CAP2I_MASK (0x100U) -#define CTIMER_CCR_CAP2I_SHIFT (8U) -#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) -#define CTIMER_CCR_CAP3RE_MASK (0x200U) -#define CTIMER_CCR_CAP3RE_SHIFT (9U) -#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) -#define CTIMER_CCR_CAP3FE_MASK (0x400U) -#define CTIMER_CCR_CAP3FE_SHIFT (10U) -#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) -#define CTIMER_CCR_CAP3I_MASK (0x800U) -#define CTIMER_CCR_CAP3I_SHIFT (11U) -#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) -/*! @} */ - -/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ -/*! @{ */ -#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) -#define CTIMER_CR_CAP_SHIFT (0U) -#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) -/*! @} */ - -/* The count of CTIMER_CR */ -#define CTIMER_CR_COUNT (4U) - -/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ -/*! @{ */ -#define CTIMER_EMR_EM0_MASK (0x1U) -#define CTIMER_EMR_EM0_SHIFT (0U) -#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) -#define CTIMER_EMR_EM1_MASK (0x2U) -#define CTIMER_EMR_EM1_SHIFT (1U) -#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) -#define CTIMER_EMR_EM2_MASK (0x4U) -#define CTIMER_EMR_EM2_SHIFT (2U) -#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) -#define CTIMER_EMR_EM3_MASK (0x8U) -#define CTIMER_EMR_EM3_SHIFT (3U) -#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) -#define CTIMER_EMR_EMC0_MASK (0x30U) -#define CTIMER_EMR_EMC0_SHIFT (4U) -#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) -#define CTIMER_EMR_EMC1_MASK (0xC0U) -#define CTIMER_EMR_EMC1_SHIFT (6U) -#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) -#define CTIMER_EMR_EMC2_MASK (0x300U) -#define CTIMER_EMR_EMC2_SHIFT (8U) -#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) -#define CTIMER_EMR_EMC3_MASK (0xC00U) -#define CTIMER_EMR_EMC3_SHIFT (10U) -#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) -/*! @} */ - -/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ -/*! @{ */ -#define CTIMER_CTCR_CTMODE_MASK (0x3U) -#define CTIMER_CTCR_CTMODE_SHIFT (0U) -#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) -#define CTIMER_CTCR_CINSEL_MASK (0xCU) -#define CTIMER_CTCR_CINSEL_SHIFT (2U) -#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) -#define CTIMER_CTCR_ENCC_MASK (0x10U) -#define CTIMER_CTCR_ENCC_SHIFT (4U) -#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) -#define CTIMER_CTCR_SELCC_MASK (0xE0U) -#define CTIMER_CTCR_SELCC_SHIFT (5U) -#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) -/*! @} */ - -/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */ -/*! @{ */ -#define CTIMER_PWMC_PWMEN0_MASK (0x1U) -#define CTIMER_PWMC_PWMEN0_SHIFT (0U) -#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) -#define CTIMER_PWMC_PWMEN1_MASK (0x2U) -#define CTIMER_PWMC_PWMEN1_SHIFT (1U) -#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) -#define CTIMER_PWMC_PWMEN2_MASK (0x4U) -#define CTIMER_PWMC_PWMEN2_SHIFT (2U) -#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) -#define CTIMER_PWMC_PWMEN3_MASK (0x8U) -#define CTIMER_PWMC_PWMEN3_SHIFT (3U) -#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CTIMER_Register_Masks */ - - -/* CTIMER - Peripheral instance base addresses */ -/** Peripheral CTIMER0 base address */ -#define CTIMER0_BASE (0x40008000u) -/** Peripheral CTIMER0 base pointer */ -#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) -/** Peripheral CTIMER1 base address */ -#define CTIMER1_BASE (0x40009000u) -/** Peripheral CTIMER1 base pointer */ -#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) -/** Peripheral CTIMER2 base address */ -#define CTIMER2_BASE (0x40028000u) -/** Peripheral CTIMER2 base pointer */ -#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) -/** Peripheral CTIMER3 base address */ -#define CTIMER3_BASE (0x40048000u) -/** Peripheral CTIMER3 base pointer */ -#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) -/** Peripheral CTIMER4 base address */ -#define CTIMER4_BASE (0x40049000u) -/** Peripheral CTIMER4 base pointer */ -#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) -/** Array initializer of CTIMER peripheral base addresses */ -#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } -/** Array initializer of CTIMER peripheral base pointers */ -#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } -/** Interrupt vectors for the CTIMER peripheral type */ -#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } - -/*! - * @} - */ /* end of group CTIMER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer - * @{ - */ - -/** DMA - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ - __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ - __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ - uint8_t RESERVED_0[20]; - struct { /* offset: 0x20, array step: 0x5C */ - __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ - uint8_t RESERVED_0[4]; - __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ - uint8_t RESERVED_1[4]; - __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ - uint8_t RESERVED_2[4]; - __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ - uint8_t RESERVED_3[4]; - __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ - uint8_t RESERVED_4[4]; - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ - uint8_t RESERVED_5[4]; - __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ - uint8_t RESERVED_6[4]; - __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ - uint8_t RESERVED_7[4]; - __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ - uint8_t RESERVED_8[4]; - __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ - uint8_t RESERVED_9[4]; - __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ - uint8_t RESERVED_10[4]; - __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ - } COMMON[1]; - uint8_t RESERVED_1[900]; - struct { /* offset: 0x400, array step: 0x10 */ - __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ - __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ - __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } CHANNEL[20]; -} DMA_Type; - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/*! @name CTRL - DMA control. */ -/*! @{ */ -#define DMA_CTRL_ENABLE_MASK (0x1U) -#define DMA_CTRL_ENABLE_SHIFT (0U) -#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status. */ -/*! @{ */ -#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) -#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) -#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) -#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) -#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) -#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) -/*! @} */ - -/*! @name SRAMBASE - SRAM address of the channel configuration table. */ -/*! @{ */ -#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) -#define DMA_SRAMBASE_OFFSET_SHIFT (9U) -#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) -/*! @} */ - -/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) -#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLESET */ -#define DMA_COMMON_ENABLESET_COUNT (1U) - -/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) -#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLECLR */ -#define DMA_COMMON_ENABLECLR_COUNT (1U) - -/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) -#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ACTIVE */ -#define DMA_COMMON_ACTIVE_COUNT (1U) - -/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) -#define DMA_COMMON_BUSY_BSY_SHIFT (0U) -#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) -/*! @} */ - -/* The count of DMA_COMMON_BUSY */ -#define DMA_COMMON_BUSY_COUNT (1U) - -/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) -#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ERRINT */ -#define DMA_COMMON_ERRINT_COUNT (1U) - -/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) -#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENSET */ -#define DMA_COMMON_INTENSET_COUNT (1U) - -/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) -#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENCLR */ -#define DMA_COMMON_INTENCLR_COUNT (1U) - -/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTA_IA_SHIFT (0U) -#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTA */ -#define DMA_COMMON_INTA_COUNT (1U) - -/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTB_IB_SHIFT (0U) -#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTB */ -#define DMA_COMMON_INTB_COUNT (1U) - -/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETVALID_SV_SHIFT (0U) -#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETVALID */ -#define DMA_COMMON_SETVALID_COUNT (1U) - -/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) -#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETTRIG */ -#define DMA_COMMON_SETTRIG_COUNT (1U) - -/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) -#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ABORT */ -#define DMA_COMMON_ABORT_COUNT (1U) - -/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ -/*! @{ */ -#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) -#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) -#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) -#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) -#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) -#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) -#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) -#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) -#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) -#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) -#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) -#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) -#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) -#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) -#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) -#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) -#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) -#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) -#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) -#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) -#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) -#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) -#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CFG */ -#define DMA_CHANNEL_CFG_COUNT (20U) - -/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ -/*! @{ */ -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) -#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) -#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) -#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CTLSTAT */ -#define DMA_CHANNEL_CTLSTAT_COUNT (20U) - -/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ -/*! @{ */ -#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) -#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) -#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) -#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) -#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) -#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) -#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) -#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) -#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) -#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) -#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) -#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) -#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) -#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) -#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) -#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) -#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) -#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) -#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) -#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) -#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) -#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) -#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) -#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) -#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) -#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) -#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_XFERCFG */ -#define DMA_CHANNEL_XFERCFG_COUNT (20U) - - -/*! - * @} - */ /* end of group DMA_Register_Masks */ - - -/* DMA - Peripheral instance base addresses */ -/** Peripheral DMA0 base address */ -#define DMA0_BASE (0x40082000u) -/** Peripheral DMA0 base pointer */ -#define DMA0 ((DMA_Type *)DMA0_BASE) -/** Array initializer of DMA peripheral base addresses */ -#define DMA_BASE_ADDRS { DMA0_BASE } -/** Array initializer of DMA peripheral base pointers */ -#define DMA_BASE_PTRS { DMA0 } -/** Interrupt vectors for the DMA peripheral type */ -#define DMA_IRQS { DMA0_IRQn } - -/*! - * @} - */ /* end of group DMA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMIC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer - * @{ - */ - -/** DMIC - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x100 */ - __IO uint32_t OSR; /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */ - __IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */ - __IO uint32_t PREAC2FSCOEF; /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */ - __IO uint32_t PREAC4FSCOEF; /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */ - __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */ - uint8_t RESERVED_0[108]; - __IO uint32_t FIFO_CTRL; /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */ - __IO uint32_t FIFO_STATUS; /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */ - __IO uint32_t FIFO_DATA; /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */ - __IO uint32_t PHY_CTRL; /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */ - __IO uint32_t DC_CTRL; /**< DC Control register 0, array offset: 0x90, array step: 0x100 */ - uint8_t RESERVED_1[108]; - } CHANNEL[2]; - uint8_t RESERVED_0[3328]; - __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ - uint8_t RESERVED_1[8]; - __IO uint32_t IOCFG; /**< I/O Configuration register, offset: 0xF0C */ - __IO uint32_t USE2FS; /**< Use 2FS register, offset: 0xF10 */ - uint8_t RESERVED_2[108]; - __IO uint32_t HWVADGAIN; /**< HWVAD input gain register, offset: 0xF80 */ - __IO uint32_t HWVADHPFS; /**< HWVAD filter control register, offset: 0xF84 */ - __IO uint32_t HWVADST10; /**< HWVAD control register, offset: 0xF88 */ - __IO uint32_t HWVADRSTT; /**< HWVAD filter reset register, offset: 0xF8C */ - __IO uint32_t HWVADTHGN; /**< HWVAD noise estimator gain register, offset: 0xF90 */ - __IO uint32_t HWVADTHGS; /**< HWVAD signal estimator gain register, offset: 0xF94 */ - __I uint32_t HWVADLOWZ; /**< HWVAD noise envelope estimator register, offset: 0xF98 */ - uint8_t RESERVED_3[96]; - __I uint32_t ID; /**< Module Identification register, offset: 0xFFC */ -} DMIC_Type; - -/* ---------------------------------------------------------------------------- - -- DMIC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMIC_Register_Masks DMIC Register Masks - * @{ - */ - -/*! @name CHANNEL_OSR - Oversample Rate register 0 */ -/*! @{ */ -#define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU) -#define DMIC_CHANNEL_OSR_OSR_SHIFT (0U) -#define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_OSR */ -#define DMIC_CHANNEL_OSR_COUNT (2U) - -/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */ -/*! @{ */ -#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU) -#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U) -#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_DIVHFCLK */ -#define DMIC_CHANNEL_DIVHFCLK_COUNT (2U) - -/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */ -/*! @{ */ -#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U) -#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U) -#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_PREAC2FSCOEF */ -#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U) - -/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */ -/*! @{ */ -#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U) -#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U) -#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_PREAC4FSCOEF */ -#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U) - -/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */ -/*! @{ */ -#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU) -#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U) -#define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_GAINSHIFT */ -#define DMIC_CHANNEL_GAINSHIFT_COUNT (2U) - -/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */ -/*! @{ */ -#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U) -#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U) -#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK) -#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U) -#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U) -#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK) -#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U) -#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U) -#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK) -#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U) -#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U) -#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK) -#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U) -#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U) -#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_FIFO_CTRL */ -#define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U) - -/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */ -/*! @{ */ -#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U) -#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U) -#define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK) -#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U) -#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U) -#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK) -#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U) -#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U) -#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_FIFO_STATUS */ -#define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U) - -/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */ -/*! @{ */ -#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU) -#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U) -#define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_FIFO_DATA */ -#define DMIC_CHANNEL_FIFO_DATA_COUNT (2U) - -/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */ -/*! @{ */ -#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U) -#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U) -#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK) -#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U) -#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U) -#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_PHY_CTRL */ -#define DMIC_CHANNEL_PHY_CTRL_COUNT (2U) - -/*! @name CHANNEL_DC_CTRL - DC Control register 0 */ -/*! @{ */ -#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U) -#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U) -#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK) -#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U) -#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U) -#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK) -#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U) -#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U) -#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_DC_CTRL */ -#define DMIC_CHANNEL_DC_CTRL_COUNT (2U) - -/*! @name CHANEN - Channel Enable register */ -/*! @{ */ -#define DMIC_CHANEN_EN_CH0_MASK (0x1U) -#define DMIC_CHANEN_EN_CH0_SHIFT (0U) -#define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK) -#define DMIC_CHANEN_EN_CH1_MASK (0x2U) -#define DMIC_CHANEN_EN_CH1_SHIFT (1U) -#define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK) -/*! @} */ - -/*! @name IOCFG - I/O Configuration register */ -/*! @{ */ -#define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U) -#define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U) -#define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK) -#define DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U) -#define DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U) -#define DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK) -#define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U) -#define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U) -#define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK) -/*! @} */ - -/*! @name USE2FS - Use 2FS register */ -/*! @{ */ -#define DMIC_USE2FS_USE2FS_MASK (0x1U) -#define DMIC_USE2FS_USE2FS_SHIFT (0U) -#define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK) -/*! @} */ - -/*! @name HWVADGAIN - HWVAD input gain register */ -/*! @{ */ -#define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU) -#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U) -#define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK) -/*! @} */ - -/*! @name HWVADHPFS - HWVAD filter control register */ -/*! @{ */ -#define DMIC_HWVADHPFS_HPFS_MASK (0x3U) -#define DMIC_HWVADHPFS_HPFS_SHIFT (0U) -#define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK) -/*! @} */ - -/*! @name HWVADST10 - HWVAD control register */ -/*! @{ */ -#define DMIC_HWVADST10_ST10_MASK (0x1U) -#define DMIC_HWVADST10_ST10_SHIFT (0U) -#define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK) -/*! @} */ - -/*! @name HWVADRSTT - HWVAD filter reset register */ -/*! @{ */ -#define DMIC_HWVADRSTT_RSTT_MASK (0x1U) -#define DMIC_HWVADRSTT_RSTT_SHIFT (0U) -#define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK) -/*! @} */ - -/*! @name HWVADTHGN - HWVAD noise estimator gain register */ -/*! @{ */ -#define DMIC_HWVADTHGN_THGN_MASK (0xFU) -#define DMIC_HWVADTHGN_THGN_SHIFT (0U) -#define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK) -/*! @} */ - -/*! @name HWVADTHGS - HWVAD signal estimator gain register */ -/*! @{ */ -#define DMIC_HWVADTHGS_THGS_MASK (0xFU) -#define DMIC_HWVADTHGS_THGS_SHIFT (0U) -#define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK) -/*! @} */ - -/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */ -/*! @{ */ -#define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU) -#define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U) -#define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK) -/*! @} */ - -/*! @name ID - Module Identification register */ -/*! @{ */ -#define DMIC_ID_ID_MASK (0xFFFFFFFFU) -#define DMIC_ID_ID_SHIFT (0U) -#define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group DMIC_Register_Masks */ - - -/* DMIC - Peripheral instance base addresses */ -/** Peripheral DMIC0 base address */ -#define DMIC0_BASE (0x40090000u) -/** Peripheral DMIC0 base pointer */ -#define DMIC0 ((DMIC_Type *)DMIC0_BASE) -/** Array initializer of DMIC peripheral base addresses */ -#define DMIC_BASE_ADDRS { DMIC0_BASE } -/** Array initializer of DMIC peripheral base pointers */ -#define DMIC_BASE_PTRS { DMIC0 } -/** Interrupt vectors for the DMIC peripheral type */ -#define DMIC_IRQS { DMIC0_IRQn } -#define DMIC_HWVAD_IRQS { HWVAD0_IRQn } - -/*! - * @} - */ /* end of group DMIC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer - * @{ - */ - -/** FLEXCOMM - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4088]; - __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ - __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ -} FLEXCOMM_Type; - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks - * @{ - */ - -/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ -/*! @{ */ -#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) -#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) -#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) -#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) -#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) -#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) -#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) -#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) -#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) -#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) -#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) -#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) -#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) -#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) -#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) -#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) -#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) -#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) -#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) -#define FLEXCOMM_PSELID_ID_SHIFT (12U) -#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) -/*! @} */ - -/*! @name PID - Peripheral identification register. */ -/*! @{ */ -#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) -#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) -#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) -#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U) -#define FLEXCOMM_PID_Major_Rev_SHIFT (12U) -#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK) -#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) -#define FLEXCOMM_PID_ID_SHIFT (16U) -#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLEXCOMM_Register_Masks */ - - -/* FLEXCOMM - Peripheral instance base addresses */ -/** Peripheral FLEXCOMM0 base address */ -#define FLEXCOMM0_BASE (0x40086000u) -/** Peripheral FLEXCOMM0 base pointer */ -#define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) -/** Peripheral FLEXCOMM1 base address */ -#define FLEXCOMM1_BASE (0x40087000u) -/** Peripheral FLEXCOMM1 base pointer */ -#define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) -/** Peripheral FLEXCOMM2 base address */ -#define FLEXCOMM2_BASE (0x40088000u) -/** Peripheral FLEXCOMM2 base pointer */ -#define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) -/** Peripheral FLEXCOMM3 base address */ -#define FLEXCOMM3_BASE (0x40089000u) -/** Peripheral FLEXCOMM3 base pointer */ -#define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) -/** Peripheral FLEXCOMM4 base address */ -#define FLEXCOMM4_BASE (0x4008A000u) -/** Peripheral FLEXCOMM4 base pointer */ -#define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) -/** Peripheral FLEXCOMM5 base address */ -#define FLEXCOMM5_BASE (0x40096000u) -/** Peripheral FLEXCOMM5 base pointer */ -#define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) -/** Peripheral FLEXCOMM6 base address */ -#define FLEXCOMM6_BASE (0x40097000u) -/** Peripheral FLEXCOMM6 base pointer */ -#define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) -/** Peripheral FLEXCOMM7 base address */ -#define FLEXCOMM7_BASE (0x40098000u) -/** Peripheral FLEXCOMM7 base pointer */ -#define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) -/** Array initializer of FLEXCOMM peripheral base addresses */ -#define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE } -/** Array initializer of FLEXCOMM peripheral base pointers */ -#define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7 } -/** Interrupt vectors for the FLEXCOMM peripheral type */ -#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer - * @{ - */ - -/** GINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ - uint8_t RESERVED_0[28]; - __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[24]; - __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ -} GINT_Type; - -/* ---------------------------------------------------------------------------- - -- GINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Register_Masks GINT Register Masks - * @{ - */ - -/*! @name CTRL - GPIO grouped interrupt control register */ -/*! @{ */ -#define GINT_CTRL_INT_MASK (0x1U) -#define GINT_CTRL_INT_SHIFT (0U) -#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) -#define GINT_CTRL_COMB_MASK (0x2U) -#define GINT_CTRL_COMB_SHIFT (1U) -#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) -#define GINT_CTRL_TRIG_MASK (0x4U) -#define GINT_CTRL_TRIG_SHIFT (2U) -#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) -/*! @} */ - -/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ -/*! @{ */ -#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) -#define GINT_PORT_POL_POL_SHIFT (0U) -#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) -/*! @} */ - -/* The count of GINT_PORT_POL */ -#define GINT_PORT_POL_COUNT (2U) - -/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ -/*! @{ */ -#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) -#define GINT_PORT_ENA_ENA_SHIFT (0U) -#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) -/*! @} */ - -/* The count of GINT_PORT_ENA */ -#define GINT_PORT_ENA_COUNT (2U) - - -/*! - * @} - */ /* end of group GINT_Register_Masks */ - - -/* GINT - Peripheral instance base addresses */ -/** Peripheral GINT0 base address */ -#define GINT0_BASE (0x40002000u) -/** Peripheral GINT0 base pointer */ -#define GINT0 ((GINT_Type *)GINT0_BASE) -/** Peripheral GINT1 base address */ -#define GINT1_BASE (0x40003000u) -/** Peripheral GINT1 base pointer */ -#define GINT1 ((GINT_Type *)GINT1_BASE) -/** Array initializer of GINT peripheral base addresses */ -#define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } -/** Array initializer of GINT peripheral base pointers */ -#define GINT_BASE_PTRS { GINT0, GINT1 } -/** Interrupt vectors for the GINT peripheral type */ -#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } - -/*! - * @} - */ /* end of group GINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer - * @{ - */ - -/** GPIO - Register Layout Typedef */ -typedef struct { - __IO uint8_t B[2][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ - uint8_t RESERVED_0[4032]; - __IO uint32_t W[2][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ - uint8_t RESERVED_1[3840]; - __IO uint32_t DIR[2]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */ - uint8_t RESERVED_2[120]; - __IO uint32_t MASK[2]; /**< Mask register, array offset: 0x2080, array step: 0x4 */ - uint8_t RESERVED_3[120]; - __IO uint32_t PIN[2]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */ - uint8_t RESERVED_4[120]; - __IO uint32_t MPIN[2]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */ - uint8_t RESERVED_5[120]; - __IO uint32_t SET[2]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */ - uint8_t RESERVED_6[120]; - __O uint32_t CLR[2]; /**< Clear port, array offset: 0x2280, array step: 0x4 */ - uint8_t RESERVED_7[120]; - __O uint32_t NOT[2]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */ - uint8_t RESERVED_8[120]; - __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ - uint8_t RESERVED_9[120]; - __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ - uint8_t RESERVED_10[120]; - __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ -} GPIO_Type; - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */ -/*! @{ */ -#define GPIO_B_PBYTE_MASK (0x1U) -#define GPIO_B_PBYTE_SHIFT (0U) -#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) -/*! @} */ - -/* The count of GPIO_B */ -#define GPIO_B_COUNT (2U) - -/* The count of GPIO_B */ -#define GPIO_B_COUNT2 (32U) - -/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */ -/*! @{ */ -#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) -#define GPIO_W_PWORD_SHIFT (0U) -#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) -/*! @} */ - -/* The count of GPIO_W */ -#define GPIO_W_COUNT (2U) - -/* The count of GPIO_W */ -#define GPIO_W_COUNT2 (32U) - -/*! @name DIR - Direction registers */ -/*! @{ */ -#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) -#define GPIO_DIR_DIRP_SHIFT (0U) -#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) -/*! @} */ - -/* The count of GPIO_DIR */ -#define GPIO_DIR_COUNT (2U) - -/*! @name MASK - Mask register */ -/*! @{ */ -#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) -#define GPIO_MASK_MASKP_SHIFT (0U) -#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) -/*! @} */ - -/* The count of GPIO_MASK */ -#define GPIO_MASK_COUNT (2U) - -/*! @name PIN - Port pin register */ -/*! @{ */ -#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) -#define GPIO_PIN_PORT_SHIFT (0U) -#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) -/*! @} */ - -/* The count of GPIO_PIN */ -#define GPIO_PIN_COUNT (2U) - -/*! @name MPIN - Masked port register */ -/*! @{ */ -#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) -#define GPIO_MPIN_MPORTP_SHIFT (0U) -#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) -/*! @} */ - -/* The count of GPIO_MPIN */ -#define GPIO_MPIN_COUNT (2U) - -/*! @name SET - Write: Set register for port Read: output bits for port */ -/*! @{ */ -#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) -#define GPIO_SET_SETP_SHIFT (0U) -#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) -/*! @} */ - -/* The count of GPIO_SET */ -#define GPIO_SET_COUNT (2U) - -/*! @name CLR - Clear port */ -/*! @{ */ -#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) -#define GPIO_CLR_CLRP_SHIFT (0U) -#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) -/*! @} */ - -/* The count of GPIO_CLR */ -#define GPIO_CLR_COUNT (2U) - -/*! @name NOT - Toggle port */ -/*! @{ */ -#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) -#define GPIO_NOT_NOTP_SHIFT (0U) -#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) -/*! @} */ - -/* The count of GPIO_NOT */ -#define GPIO_NOT_COUNT (2U) - -/*! @name DIRSET - Set pin direction bits for port */ -/*! @{ */ -#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU) -#define GPIO_DIRSET_DIRSETP_SHIFT (0U) -#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) -/*! @} */ - -/* The count of GPIO_DIRSET */ -#define GPIO_DIRSET_COUNT (2U) - -/*! @name DIRCLR - Clear pin direction bits for port */ -/*! @{ */ -#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU) -#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) -#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) -/*! @} */ - -/* The count of GPIO_DIRCLR */ -#define GPIO_DIRCLR_COUNT (2U) - -/*! @name DIRNOT - Toggle pin direction bits for port */ -/*! @{ */ -#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU) -#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) -#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) -/*! @} */ - -/* The count of GPIO_DIRNOT */ -#define GPIO_DIRNOT_COUNT (2U) - - -/*! - * @} - */ /* end of group GPIO_Register_Masks */ - - -/* GPIO - Peripheral instance base addresses */ -/** Peripheral GPIO base address */ -#define GPIO_BASE (0x4008C000u) -/** Peripheral GPIO base pointer */ -#define GPIO ((GPIO_Type *)GPIO_BASE) -/** Array initializer of GPIO peripheral base addresses */ -#define GPIO_BASE_ADDRS { GPIO_BASE } -/** Array initializer of GPIO peripheral base pointers */ -#define GPIO_BASE_PTRS { GPIO } - -/*! - * @} - */ /* end of group GPIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2C Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer - * @{ - */ - -/** I2C - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[2048]; - __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ - __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ - __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ - __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ - __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ - __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ - uint8_t RESERVED_1[4]; - __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ - __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ - __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ - uint8_t RESERVED_2[20]; - __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ - __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ - __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ - __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ - uint8_t RESERVED_3[36]; - __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ -} I2C_Type; - -/* ---------------------------------------------------------------------------- - -- I2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Register_Masks I2C Register Masks - * @{ - */ - -/*! @name CFG - Configuration for shared functions. */ -/*! @{ */ -#define I2C_CFG_MSTEN_MASK (0x1U) -#define I2C_CFG_MSTEN_SHIFT (0U) -#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) -#define I2C_CFG_SLVEN_MASK (0x2U) -#define I2C_CFG_SLVEN_SHIFT (1U) -#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) -#define I2C_CFG_MONEN_MASK (0x4U) -#define I2C_CFG_MONEN_SHIFT (2U) -#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) -#define I2C_CFG_TIMEOUTEN_MASK (0x8U) -#define I2C_CFG_TIMEOUTEN_SHIFT (3U) -#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) -#define I2C_CFG_MONCLKSTR_MASK (0x10U) -#define I2C_CFG_MONCLKSTR_SHIFT (4U) -#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) -#define I2C_CFG_HSCAPABLE_MASK (0x20U) -#define I2C_CFG_HSCAPABLE_SHIFT (5U) -#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) -/*! @} */ - -/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ -/*! @{ */ -#define I2C_STAT_MSTPENDING_MASK (0x1U) -#define I2C_STAT_MSTPENDING_SHIFT (0U) -#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) -#define I2C_STAT_MSTSTATE_MASK (0xEU) -#define I2C_STAT_MSTSTATE_SHIFT (1U) -#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) -#define I2C_STAT_MSTARBLOSS_MASK (0x10U) -#define I2C_STAT_MSTARBLOSS_SHIFT (4U) -#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) -#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) -#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) -#define I2C_STAT_SLVPENDING_MASK (0x100U) -#define I2C_STAT_SLVPENDING_SHIFT (8U) -#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) -#define I2C_STAT_SLVSTATE_MASK (0x600U) -#define I2C_STAT_SLVSTATE_SHIFT (9U) -#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) -#define I2C_STAT_SLVNOTSTR_MASK (0x800U) -#define I2C_STAT_SLVNOTSTR_SHIFT (11U) -#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) -#define I2C_STAT_SLVIDX_MASK (0x3000U) -#define I2C_STAT_SLVIDX_SHIFT (12U) -#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) -#define I2C_STAT_SLVSEL_MASK (0x4000U) -#define I2C_STAT_SLVSEL_SHIFT (14U) -#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) -#define I2C_STAT_SLVDESEL_MASK (0x8000U) -#define I2C_STAT_SLVDESEL_SHIFT (15U) -#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) -#define I2C_STAT_MONRDY_MASK (0x10000U) -#define I2C_STAT_MONRDY_SHIFT (16U) -#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) -#define I2C_STAT_MONOV_MASK (0x20000U) -#define I2C_STAT_MONOV_SHIFT (17U) -#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) -#define I2C_STAT_MONACTIVE_MASK (0x40000U) -#define I2C_STAT_MONACTIVE_SHIFT (18U) -#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) -#define I2C_STAT_MONIDLE_MASK (0x80000U) -#define I2C_STAT_MONIDLE_SHIFT (19U) -#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) -#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) -#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) -#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) -#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable Set and read register. */ -/*! @{ */ -#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) -#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) -#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) -#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) -#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) -#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) -#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) -#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) -#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) -#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) -#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) -#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) -#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) -#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) -#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) -#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) -#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) -#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) -#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) -#define I2C_INTENSET_MONRDYEN_SHIFT (16U) -#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) -#define I2C_INTENSET_MONOVEN_MASK (0x20000U) -#define I2C_INTENSET_MONOVEN_SHIFT (17U) -#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) -#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) -#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) -#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) -#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) -#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) -#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) -#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) -#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) -#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear register. */ -/*! @{ */ -#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) -#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) -#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) -#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) -#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) -#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) -#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) -#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) -#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) -#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) -#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) -#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) -#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) -#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) -#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) -#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) -#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) -#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) -#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) -#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) -#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) -#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) -#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) -#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) -#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) -#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) -#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) -#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) -#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) -#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) -#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) -#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) -#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) -/*! @} */ - -/*! @name TIMEOUT - Time-out value register. */ -/*! @{ */ -#define I2C_TIMEOUT_TOMIN_MASK (0xFU) -#define I2C_TIMEOUT_TOMIN_SHIFT (0U) -#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) -#define I2C_TIMEOUT_TO_MASK (0xFFF0U) -#define I2C_TIMEOUT_TO_SHIFT (4U) -#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) -/*! @} */ - -/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ -/*! @{ */ -#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) -#define I2C_CLKDIV_DIVVAL_SHIFT (0U) -#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ -/*! @{ */ -#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) -#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) -#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) -#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) -#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) -#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) -#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) -#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) -#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) -#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) -#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) -#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) -#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) -#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) -#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) -#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) -#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) -#define I2C_INTSTAT_MONRDY_MASK (0x10000U) -#define I2C_INTSTAT_MONRDY_SHIFT (16U) -#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) -#define I2C_INTSTAT_MONOV_MASK (0x20000U) -#define I2C_INTSTAT_MONOV_SHIFT (17U) -#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) -#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) -#define I2C_INTSTAT_MONIDLE_SHIFT (19U) -#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) -#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) -#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) -#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) -#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name MSTCTL - Master control register. */ -/*! @{ */ -#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) -#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) -#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) -#define I2C_MSTCTL_MSTSTART_MASK (0x2U) -#define I2C_MSTCTL_MSTSTART_SHIFT (1U) -#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) -#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) -#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) -#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) -#define I2C_MSTCTL_MSTDMA_MASK (0x8U) -#define I2C_MSTCTL_MSTDMA_SHIFT (3U) -#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) -/*! @} */ - -/*! @name MSTTIME - Master timing configuration. */ -/*! @{ */ -#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) -#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) -#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) -#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) -#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) -#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) -/*! @} */ - -/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ -/*! @{ */ -#define I2C_MSTDAT_DATA_MASK (0xFFU) -#define I2C_MSTDAT_DATA_SHIFT (0U) -#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVCTL - Slave control register. */ -/*! @{ */ -#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) -#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) -#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) -#define I2C_SLVCTL_SLVNACK_MASK (0x2U) -#define I2C_SLVCTL_SLVNACK_SHIFT (1U) -#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) -#define I2C_SLVCTL_SLVDMA_MASK (0x8U) -#define I2C_SLVCTL_SLVDMA_SHIFT (3U) -#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) -#define I2C_SLVCTL_AUTOACK_MASK (0x100U) -#define I2C_SLVCTL_AUTOACK_SHIFT (8U) -#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) -#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) -#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) -#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) -/*! @} */ - -/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ -/*! @{ */ -#define I2C_SLVDAT_DATA_MASK (0xFFU) -#define I2C_SLVDAT_DATA_SHIFT (0U) -#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVADR - Slave address register. */ -/*! @{ */ -#define I2C_SLVADR_SADISABLE_MASK (0x1U) -#define I2C_SLVADR_SADISABLE_SHIFT (0U) -#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) -#define I2C_SLVADR_SLVADR_MASK (0xFEU) -#define I2C_SLVADR_SLVADR_SHIFT (1U) -#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) -#define I2C_SLVADR_AUTONACK_MASK (0x8000U) -#define I2C_SLVADR_AUTONACK_SHIFT (15U) -#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) -/*! @} */ - -/* The count of I2C_SLVADR */ -#define I2C_SLVADR_COUNT (4U) - -/*! @name SLVQUAL0 - Slave Qualification for address 0. */ -/*! @{ */ -#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) -#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) -#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) -#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) -#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) -#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) -/*! @} */ - -/*! @name MONRXDAT - Monitor receiver data register. */ -/*! @{ */ -#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) -#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) -#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) -#define I2C_MONRXDAT_MONSTART_MASK (0x100U) -#define I2C_MONRXDAT_MONSTART_SHIFT (8U) -#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) -#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) -#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) -#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) -#define I2C_MONRXDAT_MONNACK_MASK (0x400U) -#define I2C_MONRXDAT_MONNACK_SHIFT (10U) -#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2C_Register_Masks */ - - -/* I2C - Peripheral instance base addresses */ -/** Peripheral I2C0 base address */ -#define I2C0_BASE (0x40086000u) -/** Peripheral I2C0 base pointer */ -#define I2C0 ((I2C_Type *)I2C0_BASE) -/** Peripheral I2C1 base address */ -#define I2C1_BASE (0x40087000u) -/** Peripheral I2C1 base pointer */ -#define I2C1 ((I2C_Type *)I2C1_BASE) -/** Peripheral I2C2 base address */ -#define I2C2_BASE (0x40088000u) -/** Peripheral I2C2 base pointer */ -#define I2C2 ((I2C_Type *)I2C2_BASE) -/** Peripheral I2C3 base address */ -#define I2C3_BASE (0x40089000u) -/** Peripheral I2C3 base pointer */ -#define I2C3 ((I2C_Type *)I2C3_BASE) -/** Peripheral I2C4 base address */ -#define I2C4_BASE (0x4008A000u) -/** Peripheral I2C4 base pointer */ -#define I2C4 ((I2C_Type *)I2C4_BASE) -/** Peripheral I2C5 base address */ -#define I2C5_BASE (0x40096000u) -/** Peripheral I2C5 base pointer */ -#define I2C5 ((I2C_Type *)I2C5_BASE) -/** Peripheral I2C6 base address */ -#define I2C6_BASE (0x40097000u) -/** Peripheral I2C6 base pointer */ -#define I2C6 ((I2C_Type *)I2C6_BASE) -/** Peripheral I2C7 base address */ -#define I2C7_BASE (0x40098000u) -/** Peripheral I2C7 base pointer */ -#define I2C7 ((I2C_Type *)I2C7_BASE) -/** Array initializer of I2C peripheral base addresses */ -#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } -/** Array initializer of I2C peripheral base pointers */ -#define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } -/** Interrupt vectors for the I2C peripheral type */ -#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2C_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2S Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer - * @{ - */ - -/** I2S - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[3072]; - __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ - __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ - __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ - uint8_t RESERVED_2[480]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ - uint8_t RESERVED_5[8]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ - uint8_t RESERVED_6[8]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ -} I2S_Type; - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ -/*! @{ */ -#define I2S_CFG1_MAINENABLE_MASK (0x1U) -#define I2S_CFG1_MAINENABLE_SHIFT (0U) -#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) -#define I2S_CFG1_DATAPAUSE_MASK (0x2U) -#define I2S_CFG1_DATAPAUSE_SHIFT (1U) -#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) -#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) -#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) -#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) -#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) -#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) -#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) -#define I2S_CFG1_MODE_MASK (0xC0U) -#define I2S_CFG1_MODE_SHIFT (6U) -#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) -#define I2S_CFG1_RIGHTLOW_MASK (0x100U) -#define I2S_CFG1_RIGHTLOW_SHIFT (8U) -#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) -#define I2S_CFG1_LEFTJUST_MASK (0x200U) -#define I2S_CFG1_LEFTJUST_SHIFT (9U) -#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) -#define I2S_CFG1_ONECHANNEL_MASK (0x400U) -#define I2S_CFG1_ONECHANNEL_SHIFT (10U) -#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) -#define I2S_CFG1_PDMDATA_MASK (0x800U) -#define I2S_CFG1_PDMDATA_SHIFT (11U) -#define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK) -#define I2S_CFG1_SCK_POL_MASK (0x1000U) -#define I2S_CFG1_SCK_POL_SHIFT (12U) -#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) -#define I2S_CFG1_WS_POL_MASK (0x2000U) -#define I2S_CFG1_WS_POL_SHIFT (13U) -#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) -#define I2S_CFG1_DATALEN_MASK (0x1F0000U) -#define I2S_CFG1_DATALEN_SHIFT (16U) -#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) -/*! @} */ - -/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ -/*! @{ */ -#define I2S_CFG2_FRAMELEN_MASK (0x1FFU) -#define I2S_CFG2_FRAMELEN_SHIFT (0U) -#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) -#define I2S_CFG2_POSITION_MASK (0x1FF0000U) -#define I2S_CFG2_POSITION_SHIFT (16U) -#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) -/*! @} */ - -/*! @name STAT - Status register for the primary channel pair. */ -/*! @{ */ -#define I2S_STAT_BUSY_MASK (0x1U) -#define I2S_STAT_BUSY_SHIFT (0U) -#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) -#define I2S_STAT_SLVFRMERR_MASK (0x2U) -#define I2S_STAT_SLVFRMERR_SHIFT (1U) -#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) -#define I2S_STAT_LR_MASK (0x4U) -#define I2S_STAT_LR_SHIFT (2U) -#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) -#define I2S_STAT_DATAPAUSED_MASK (0x8U) -#define I2S_STAT_DATAPAUSED_SHIFT (3U) -#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) -/*! @} */ - -/*! @name DIV - Clock divider, used by all channel pairs. */ -/*! @{ */ -#define I2S_DIV_DIV_MASK (0xFFFU) -#define I2S_DIV_DIV_SHIFT (0U) -#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ -#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) -#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) -#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) -#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) -#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) -#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) -#define I2S_FIFOCFG_TXI2SSE0_MASK (0x4U) -#define I2S_FIFOCFG_TXI2SSE0_SHIFT (2U) -#define I2S_FIFOCFG_TXI2SSE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SSE0_SHIFT)) & I2S_FIFOCFG_TXI2SSE0_MASK) -#define I2S_FIFOCFG_PACK48_MASK (0x8U) -#define I2S_FIFOCFG_PACK48_SHIFT (3U) -#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) -#define I2S_FIFOCFG_SIZE_MASK (0x30U) -#define I2S_FIFOCFG_SIZE_SHIFT (4U) -#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) -#define I2S_FIFOCFG_DMATX_MASK (0x1000U) -#define I2S_FIFOCFG_DMATX_SHIFT (12U) -#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) -#define I2S_FIFOCFG_DMARX_MASK (0x2000U) -#define I2S_FIFOCFG_DMARX_SHIFT (13U) -#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) -#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) -#define I2S_FIFOCFG_WAKETX_SHIFT (14U) -#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) -#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) -#define I2S_FIFOCFG_WAKERX_SHIFT (15U) -#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) -#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) -#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) -#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) -#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) -#define I2S_FIFOCFG_POPDBG_MASK (0x40000U) -#define I2S_FIFOCFG_POPDBG_SHIFT (18U) -#define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ -#define I2S_FIFOSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOSTAT_TXERR_SHIFT (0U) -#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) -#define I2S_FIFOSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOSTAT_RXERR_SHIFT (1U) -#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) -#define I2S_FIFOSTAT_PERINT_MASK (0x8U) -#define I2S_FIFOSTAT_PERINT_SHIFT (3U) -#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) -#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) -#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) -#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) -#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) -#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) -#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) -#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) -#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) -#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) -#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) -#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) -#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ -#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) -#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) -#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) -#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) -#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) -#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) -#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) -#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) -#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ -#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) -#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) -#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) -#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) -#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) -#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) -#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) -#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) -#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) -#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ -#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) -#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) -#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) -#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) -#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) -#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) -#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) -#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) -#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) -#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ -#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) -#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) -#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) -#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) -#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) -#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) -#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) -#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) -#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) -#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) -#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ -#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFOWR_TXDATA_SHIFT (0U) -#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ -#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) -#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) -#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ -#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORD_RXDATA_SHIFT (0U) -#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ -#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48H_RXDATA_SHIFT (0U) -#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ -#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) -#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ -#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) -#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2S_Register_Masks */ - - -/* I2S - Peripheral instance base addresses */ -/** Peripheral I2S0 base address */ -#define I2S0_BASE (0x40097000u) -/** Peripheral I2S0 base pointer */ -#define I2S0 ((I2S_Type *)I2S0_BASE) -/** Peripheral I2S1 base address */ -#define I2S1_BASE (0x40098000u) -/** Peripheral I2S1 base pointer */ -#define I2S1 ((I2S_Type *)I2S1_BASE) -/** Array initializer of I2S peripheral base addresses */ -#define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE } -/** Array initializer of I2S peripheral base pointers */ -#define I2S_BASE_PTRS { I2S0, I2S1 } -/** Interrupt vectors for the I2S peripheral type */ -#define I2S_IRQS { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2S_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer - * @{ - */ - -/** INPUTMUX - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[192]; - __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ - __IO uint32_t DMA_ITRIG_INMUX[22]; /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */ - uint8_t RESERVED_1[40]; - __IO uint32_t DMA_OTRIG_INMUX[4]; /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */ - uint8_t RESERVED_2[16]; - __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ - __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ -} INPUTMUX_Type; - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks - * @{ - */ - -/*! @name PINTSEL - Pin interrupt select register */ -/*! @{ */ -#define INPUTMUX_PINTSEL_INTPIN_MASK (0xFFU) -#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) -#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PINTSEL */ -#define INPUTMUX_PINTSEL_COUNT (8U) - -/*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */ -/*! @{ */ -#define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U) -#define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA_ITRIG_INMUX */ -#define INPUTMUX_DMA_ITRIG_INMUX_COUNT (22U) - -/*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */ -/*! @{ */ -#define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT (0U) -#define INPUTMUX_DMA_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA_OTRIG_INMUX */ -#define INPUTMUX_DMA_OTRIG_INMUX_COUNT (4U) - -/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ -/*! @{ */ -#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) -#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) -/*! @} */ - -/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ -/*! @{ */ -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) -#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group INPUTMUX_Register_Masks */ - - -/* INPUTMUX - Peripheral instance base addresses */ -/** Peripheral INPUTMUX base address */ -#define INPUTMUX_BASE (0x40005000u) -/** Peripheral INPUTMUX base pointer */ -#define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) -/** Array initializer of INPUTMUX peripheral base addresses */ -#define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } -/** Array initializer of INPUTMUX peripheral base pointers */ -#define INPUTMUX_BASE_PTRS { INPUTMUX } - -/*! - * @} - */ /* end of group INPUTMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- IOCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer - * @{ - */ - -/** IOCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ -} IOCON_Type; - -/* ---------------------------------------------------------------------------- - -- IOCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Register_Masks IOCON Register Masks - * @{ - */ - -/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ -/*! @{ */ -#define IOCON_PIO_FUNC_MASK (0x7U) -#define IOCON_PIO_FUNC_SHIFT (0U) -#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) -#define IOCON_PIO_MODE_MASK (0x18U) -#define IOCON_PIO_MODE_SHIFT (3U) -#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) -#define IOCON_PIO_I2CSLEW_MASK (0x20U) -#define IOCON_PIO_I2CSLEW_SHIFT (5U) -#define IOCON_PIO_I2CSLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK) -#define IOCON_PIO_INVERT_MASK (0x40U) -#define IOCON_PIO_INVERT_SHIFT (6U) -#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) -#define IOCON_PIO_DIGIMODE_MASK (0x80U) -#define IOCON_PIO_DIGIMODE_SHIFT (7U) -#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) -#define IOCON_PIO_FILTEROFF_MASK (0x100U) -#define IOCON_PIO_FILTEROFF_SHIFT (8U) -#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) -#define IOCON_PIO_I2CDRIVE_MASK (0x200U) -#define IOCON_PIO_I2CDRIVE_SHIFT (9U) -#define IOCON_PIO_I2CDRIVE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK) -#define IOCON_PIO_SLEW_MASK (0x200U) -#define IOCON_PIO_SLEW_SHIFT (9U) -#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) -#define IOCON_PIO_I2CFILTER_MASK (0x400U) -#define IOCON_PIO_I2CFILTER_SHIFT (10U) -#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) -#define IOCON_PIO_OD_MASK (0x400U) -#define IOCON_PIO_OD_SHIFT (10U) -#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) -/*! @} */ - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT (2U) - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT2 (32U) - - -/*! - * @} - */ /* end of group IOCON_Register_Masks */ - - -/* IOCON - Peripheral instance base addresses */ -/** Peripheral IOCON base address */ -#define IOCON_BASE (0x40001000u) -/** Peripheral IOCON base pointer */ -#define IOCON ((IOCON_Type *)IOCON_BASE) -/** Array initializer of IOCON peripheral base addresses */ -#define IOCON_BASE_ADDRS { IOCON_BASE } -/** Array initializer of IOCON peripheral base pointers */ -#define IOCON_BASE_PTRS { IOCON } - -/*! - * @} - */ /* end of group IOCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MAILBOX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer - * @{ - */ - -/** MAILBOX - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x10 */ - __IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */ - __O uint32_t IRQSET; /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */ - __O uint32_t IRQCLR; /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } MBOXIRQ[2]; - uint8_t RESERVED_0[216]; - __IO uint32_t MUTEX; /**< Mutual exclusion register[1], offset: 0xF8 */ -} MAILBOX_Type; - -/* ---------------------------------------------------------------------------- - -- MAILBOX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks - * @{ - */ - -/*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */ -/*! @{ */ -#define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) -#define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U) -#define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK) -/*! @} */ - -/* The count of MAILBOX_MBOXIRQ_IRQ */ -#define MAILBOX_MBOXIRQ_IRQ_COUNT (2U) - -/*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */ -/*! @{ */ -#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) -#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U) -#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK) -/*! @} */ - -/* The count of MAILBOX_MBOXIRQ_IRQSET */ -#define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U) - -/*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */ -/*! @{ */ -#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) -#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U) -#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK) -/*! @} */ - -/* The count of MAILBOX_MBOXIRQ_IRQCLR */ -#define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U) - -/*! @name MUTEX - Mutual exclusion register[1] */ -/*! @{ */ -#define MAILBOX_MUTEX_EX_MASK (0x1U) -#define MAILBOX_MUTEX_EX_SHIFT (0U) -#define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MAILBOX_Register_Masks */ - - -/* MAILBOX - Peripheral instance base addresses */ -/** Peripheral MAILBOX base address */ -#define MAILBOX_BASE (0x4008B000u) -/** Peripheral MAILBOX base pointer */ -#define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) -/** Array initializer of MAILBOX peripheral base addresses */ -#define MAILBOX_BASE_ADDRS { MAILBOX_BASE } -/** Array initializer of MAILBOX peripheral base pointers */ -#define MAILBOX_BASE_PTRS { MAILBOX } -/** Interrupt vectors for the MAILBOX peripheral type */ -#define MAILBOX_IRQS { MAILBOX_IRQn } - -/*! - * @} - */ /* end of group MAILBOX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MRT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer - * @{ - */ - -/** MRT - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x10 */ - __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ - __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ - __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ - __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ - } CHANNEL[4]; - uint8_t RESERVED_0[176]; - __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ - __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ - __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ -} MRT_Type; - -/* ---------------------------------------------------------------------------- - -- MRT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Register_Masks MRT Register Masks - * @{ - */ - -/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ -/*! @{ */ -#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) -#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) -#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) -#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) -#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_INTVAL */ -#define MRT_CHANNEL_INTVAL_COUNT (4U) - -/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ -/*! @{ */ -#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) -#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_TIMER */ -#define MRT_CHANNEL_TIMER_COUNT (4U) - -/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ -/*! @{ */ -#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) -#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) -#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) -#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) -#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) -#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_CTRL */ -#define MRT_CHANNEL_CTRL_COUNT (4U) - -/*! @name CHANNEL_STAT - MRT Status register. */ -/*! @{ */ -#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) -#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) -#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) -#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) -#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) -#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) -#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) -#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) -#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_STAT */ -#define MRT_CHANNEL_STAT_COUNT (4U) - -/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ -/*! @{ */ -#define MRT_MODCFG_NOC_MASK (0xFU) -#define MRT_MODCFG_NOC_SHIFT (0U) -#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) -#define MRT_MODCFG_NOB_MASK (0x1F0U) -#define MRT_MODCFG_NOB_SHIFT (4U) -#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) -#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) -#define MRT_MODCFG_MULTITASK_SHIFT (31U) -#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) -/*! @} */ - -/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ -/*! @{ */ -#define MRT_IDLE_CH_CHAN_MASK (0xF0U) -#define MRT_IDLE_CH_CHAN_SHIFT (4U) -#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) -/*! @} */ - -/*! @name IRQ_FLAG - Global interrupt flag register */ -/*! @{ */ -#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) -#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) -#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) -#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) -#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) -#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) -#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) -#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) -#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) -#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) -#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) -#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MRT_Register_Masks */ - - -/* MRT - Peripheral instance base addresses */ -/** Peripheral MRT0 base address */ -#define MRT0_BASE (0x4000D000u) -/** Peripheral MRT0 base pointer */ -#define MRT0 ((MRT_Type *)MRT0_BASE) -/** Array initializer of MRT peripheral base addresses */ -#define MRT_BASE_ADDRS { MRT0_BASE } -/** Array initializer of MRT peripheral base pointers */ -#define MRT_BASE_PTRS { MRT0 } -/** Interrupt vectors for the MRT peripheral type */ -#define MRT_IRQS { MRT0_IRQn } - -/*! - * @} - */ /* end of group MRT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer - * @{ - */ - -/** PINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ - __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ - __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ - __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ - __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ - __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ - __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ - __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ - __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ - __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ - __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ - __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ - __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ -} PINT_Type; - -/* ---------------------------------------------------------------------------- - -- PINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Register_Masks PINT Register Masks - * @{ - */ - -/*! @name ISEL - Pin Interrupt Mode register */ -/*! @{ */ -#define PINT_ISEL_PMODE_MASK (0xFFU) -#define PINT_ISEL_PMODE_SHIFT (0U) -#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) -/*! @} */ - -/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ -/*! @{ */ -#define PINT_IENR_ENRL_MASK (0xFFU) -#define PINT_IENR_ENRL_SHIFT (0U) -#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) -/*! @} */ - -/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ -/*! @{ */ -#define PINT_SIENR_SETENRL_MASK (0xFFU) -#define PINT_SIENR_SETENRL_SHIFT (0U) -#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) -/*! @} */ - -/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ -/*! @{ */ -#define PINT_CIENR_CENRL_MASK (0xFFU) -#define PINT_CIENR_CENRL_SHIFT (0U) -#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) -/*! @} */ - -/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ -/*! @{ */ -#define PINT_IENF_ENAF_MASK (0xFFU) -#define PINT_IENF_ENAF_SHIFT (0U) -#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) -/*! @} */ - -/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ -/*! @{ */ -#define PINT_SIENF_SETENAF_MASK (0xFFU) -#define PINT_SIENF_SETENAF_SHIFT (0U) -#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) -/*! @} */ - -/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ -/*! @{ */ -#define PINT_CIENF_CENAF_MASK (0xFFU) -#define PINT_CIENF_CENAF_SHIFT (0U) -#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) -/*! @} */ - -/*! @name RISE - Pin interrupt rising edge register */ -/*! @{ */ -#define PINT_RISE_RDET_MASK (0xFFU) -#define PINT_RISE_RDET_SHIFT (0U) -#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) -/*! @} */ - -/*! @name FALL - Pin interrupt falling edge register */ -/*! @{ */ -#define PINT_FALL_FDET_MASK (0xFFU) -#define PINT_FALL_FDET_SHIFT (0U) -#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) -/*! @} */ - -/*! @name IST - Pin interrupt status register */ -/*! @{ */ -#define PINT_IST_PSTAT_MASK (0xFFU) -#define PINT_IST_PSTAT_SHIFT (0U) -#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) -/*! @} */ - -/*! @name PMCTRL - Pattern match interrupt control register */ -/*! @{ */ -#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) -#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) -#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) -#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) -#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) -#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) -#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) -#define PINT_PMCTRL_PMAT_SHIFT (24U) -#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) -/*! @} */ - -/*! @name PMSRC - Pattern match interrupt bit-slice source register */ -/*! @{ */ -#define PINT_PMSRC_SRC0_MASK (0x700U) -#define PINT_PMSRC_SRC0_SHIFT (8U) -#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) -#define PINT_PMSRC_SRC1_MASK (0x3800U) -#define PINT_PMSRC_SRC1_SHIFT (11U) -#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) -#define PINT_PMSRC_SRC2_MASK (0x1C000U) -#define PINT_PMSRC_SRC2_SHIFT (14U) -#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) -#define PINT_PMSRC_SRC3_MASK (0xE0000U) -#define PINT_PMSRC_SRC3_SHIFT (17U) -#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) -#define PINT_PMSRC_SRC4_MASK (0x700000U) -#define PINT_PMSRC_SRC4_SHIFT (20U) -#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) -#define PINT_PMSRC_SRC5_MASK (0x3800000U) -#define PINT_PMSRC_SRC5_SHIFT (23U) -#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) -#define PINT_PMSRC_SRC6_MASK (0x1C000000U) -#define PINT_PMSRC_SRC6_SHIFT (26U) -#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) -#define PINT_PMSRC_SRC7_MASK (0xE0000000U) -#define PINT_PMSRC_SRC7_SHIFT (29U) -#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) -/*! @} */ - -/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ -/*! @{ */ -#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) -#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) -#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) -#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) -#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) -#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) -#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) -#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) -#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) -#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) -#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) -#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) -#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) -#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) -#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) -#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) -#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) -#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) -#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) -#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) -#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) -#define PINT_PMCFG_CFG0_MASK (0x700U) -#define PINT_PMCFG_CFG0_SHIFT (8U) -#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) -#define PINT_PMCFG_CFG1_MASK (0x3800U) -#define PINT_PMCFG_CFG1_SHIFT (11U) -#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) -#define PINT_PMCFG_CFG2_MASK (0x1C000U) -#define PINT_PMCFG_CFG2_SHIFT (14U) -#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) -#define PINT_PMCFG_CFG3_MASK (0xE0000U) -#define PINT_PMCFG_CFG3_SHIFT (17U) -#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) -#define PINT_PMCFG_CFG4_MASK (0x700000U) -#define PINT_PMCFG_CFG4_SHIFT (20U) -#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) -#define PINT_PMCFG_CFG5_MASK (0x3800000U) -#define PINT_PMCFG_CFG5_SHIFT (23U) -#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) -#define PINT_PMCFG_CFG6_MASK (0x1C000000U) -#define PINT_PMCFG_CFG6_SHIFT (26U) -#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) -#define PINT_PMCFG_CFG7_MASK (0xE0000000U) -#define PINT_PMCFG_CFG7_SHIFT (29U) -#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PINT_Register_Masks */ - - -/* PINT - Peripheral instance base addresses */ -/** Peripheral PINT base address */ -#define PINT_BASE (0x40004000u) -/** Peripheral PINT base pointer */ -#define PINT ((PINT_Type *)PINT_BASE) -/** Array initializer of PINT peripheral base addresses */ -#define PINT_BASE_ADDRS { PINT_BASE } -/** Array initializer of PINT peripheral base pointers */ -#define PINT_BASE_PTRS { PINT } -/** Interrupt vectors for the PINT peripheral type */ -#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn } - -/*! - * @} - */ /* end of group PINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RTC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer - * @{ - */ - -/** RTC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ - __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ - __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ - __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ -} RTC_Type; - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/*! @name CTRL - RTC control register */ -/*! @{ */ -#define RTC_CTRL_SWRESET_MASK (0x1U) -#define RTC_CTRL_SWRESET_SHIFT (0U) -#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) -#define RTC_CTRL_ALARM1HZ_MASK (0x4U) -#define RTC_CTRL_ALARM1HZ_SHIFT (2U) -#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) -#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) -#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) -#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) -#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) -#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) -#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) -#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) -#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) -#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) -#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) -#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) -#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) -#define RTC_CTRL_RTC_EN_MASK (0x80U) -#define RTC_CTRL_RTC_EN_SHIFT (7U) -#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) -#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) -#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) -#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) -#define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) -#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) -#define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) -/*! @} */ - -/*! @name MATCH - RTC match register */ -/*! @{ */ -#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) -#define RTC_MATCH_MATVAL_SHIFT (0U) -#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) -/*! @} */ - -/*! @name COUNT - RTC counter register */ -/*! @{ */ -#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) -#define RTC_COUNT_VAL_SHIFT (0U) -#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) -/*! @} */ - -/*! @name WAKE - High-resolution/wake-up timer control register */ -/*! @{ */ -#define RTC_WAKE_VAL_MASK (0xFFFFU) -#define RTC_WAKE_VAL_SHIFT (0U) -#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group RTC_Register_Masks */ - - -/* RTC - Peripheral instance base addresses */ -/** Peripheral RTC base address */ -#define RTC_BASE (0x4002C000u) -/** Peripheral RTC base pointer */ -#define RTC ((RTC_Type *)RTC_BASE) -/** Array initializer of RTC peripheral base addresses */ -#define RTC_BASE_ADDRS { RTC_BASE } -/** Array initializer of RTC peripheral base pointers */ -#define RTC_BASE_PTRS { RTC } -/** Interrupt vectors for the RTC peripheral type */ -#define RTC_IRQS { RTC_IRQn } - -/*! - * @} - */ /* end of group RTC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SCT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer - * @{ - */ - -/** SCT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ - __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ - __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ - __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ - __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ - __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ - uint8_t RESERVED_0[40]; - __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ - __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ - __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ - __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ - __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ - __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ - __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ - __IO uint32_t DMA0REQUEST; /**< SCT DMA request 0 register, offset: 0x5C */ - __IO uint32_t DMA1REQUEST; /**< SCT DMA request 1 register, offset: 0x60 */ - uint8_t RESERVED_1[140]; - __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ - __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ - __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ - __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ - union { /* offset: 0x100 */ - __IO uint32_t SCTCAP[10]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ - __IO uint32_t SCTMATCH[10]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ - }; - uint8_t RESERVED_2[216]; - union { /* offset: 0x200 */ - __IO uint32_t SCTCAPCTRL[10]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ - __IO uint32_t SCTMATCHREL[10]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ - }; - uint8_t RESERVED_3[216]; - struct { /* offset: 0x300, array step: 0x8 */ - __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ - __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ - } EVENT[10]; - uint8_t RESERVED_4[432]; - struct { /* offset: 0x500, array step: 0x8 */ - __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ - __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ - } OUT[8]; - uint8_t RESERVED_5[700]; - uint32_t MODULECONTENT; /**< Reserved, offset: 0x7FC */ -} SCT_Type; - -/* ---------------------------------------------------------------------------- - -- SCT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Register_Masks SCT Register Masks - * @{ - */ - -/*! @name CONFIG - SCT configuration register */ -/*! @{ */ -#define SCT_CONFIG_UNIFY_MASK (0x1U) -#define SCT_CONFIG_UNIFY_SHIFT (0U) -#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) -#define SCT_CONFIG_CLKMODE_MASK (0x6U) -#define SCT_CONFIG_CLKMODE_SHIFT (1U) -#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) -#define SCT_CONFIG_CKSEL_MASK (0x78U) -#define SCT_CONFIG_CKSEL_SHIFT (3U) -#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) -#define SCT_CONFIG_NORELAOD_L_MASK (0x80U) -#define SCT_CONFIG_NORELAOD_L_SHIFT (7U) -#define SCT_CONFIG_NORELAOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK) -#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) -#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) -#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) -#define SCT_CONFIG_INSYNC_MASK (0x1E00U) -#define SCT_CONFIG_INSYNC_SHIFT (9U) -#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) -#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) -#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) -#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) -#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) -#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) -#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) -/*! @} */ - -/*! @name CTRL - SCT control register */ -/*! @{ */ -#define SCT_CTRL_DOWN_L_MASK (0x1U) -#define SCT_CTRL_DOWN_L_SHIFT (0U) -#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) -#define SCT_CTRL_STOP_L_MASK (0x2U) -#define SCT_CTRL_STOP_L_SHIFT (1U) -#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) -#define SCT_CTRL_HALT_L_MASK (0x4U) -#define SCT_CTRL_HALT_L_SHIFT (2U) -#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) -#define SCT_CTRL_CLRCTR_L_MASK (0x8U) -#define SCT_CTRL_CLRCTR_L_SHIFT (3U) -#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) -#define SCT_CTRL_BIDIR_L_MASK (0x10U) -#define SCT_CTRL_BIDIR_L_SHIFT (4U) -#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) -#define SCT_CTRL_PRE_L_MASK (0x1FE0U) -#define SCT_CTRL_PRE_L_SHIFT (5U) -#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) -#define SCT_CTRL_DOWN_H_MASK (0x10000U) -#define SCT_CTRL_DOWN_H_SHIFT (16U) -#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) -#define SCT_CTRL_STOP_H_MASK (0x20000U) -#define SCT_CTRL_STOP_H_SHIFT (17U) -#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) -#define SCT_CTRL_HALT_H_MASK (0x40000U) -#define SCT_CTRL_HALT_H_SHIFT (18U) -#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) -#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) -#define SCT_CTRL_CLRCTR_H_SHIFT (19U) -#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) -#define SCT_CTRL_BIDIR_H_MASK (0x100000U) -#define SCT_CTRL_BIDIR_H_SHIFT (20U) -#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) -#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) -#define SCT_CTRL_PRE_H_SHIFT (21U) -#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) -/*! @} */ - -/*! @name LIMIT - SCT limit event select register */ -/*! @{ */ -#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) -#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) -#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) -#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) -#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) -#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) -/*! @} */ - -/*! @name HALT - SCT halt event select register */ -/*! @{ */ -#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) -#define SCT_HALT_HALTMSK_L_SHIFT (0U) -#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) -#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) -#define SCT_HALT_HALTMSK_H_SHIFT (16U) -#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) -/*! @} */ - -/*! @name STOP - SCT stop event select register */ -/*! @{ */ -#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) -#define SCT_STOP_STOPMSK_L_SHIFT (0U) -#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) -#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) -#define SCT_STOP_STOPMSK_H_SHIFT (16U) -#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) -/*! @} */ - -/*! @name START - SCT start event select register */ -/*! @{ */ -#define SCT_START_STARTMSK_L_MASK (0xFFFFU) -#define SCT_START_STARTMSK_L_SHIFT (0U) -#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) -#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) -#define SCT_START_STARTMSK_H_SHIFT (16U) -#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) -/*! @} */ - -/*! @name COUNT - SCT counter register */ -/*! @{ */ -#define SCT_COUNT_CTR_L_MASK (0xFFFFU) -#define SCT_COUNT_CTR_L_SHIFT (0U) -#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) -#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) -#define SCT_COUNT_CTR_H_SHIFT (16U) -#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) -/*! @} */ - -/*! @name STATE - SCT state register */ -/*! @{ */ -#define SCT_STATE_STATE_L_MASK (0x1FU) -#define SCT_STATE_STATE_L_SHIFT (0U) -#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) -#define SCT_STATE_STATE_H_MASK (0x1F0000U) -#define SCT_STATE_STATE_H_SHIFT (16U) -#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) -/*! @} */ - -/*! @name INPUT - SCT input register */ -/*! @{ */ -#define SCT_INPUT_AIN0_MASK (0x1U) -#define SCT_INPUT_AIN0_SHIFT (0U) -#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) -#define SCT_INPUT_AIN1_MASK (0x2U) -#define SCT_INPUT_AIN1_SHIFT (1U) -#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) -#define SCT_INPUT_AIN2_MASK (0x4U) -#define SCT_INPUT_AIN2_SHIFT (2U) -#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) -#define SCT_INPUT_AIN3_MASK (0x8U) -#define SCT_INPUT_AIN3_SHIFT (3U) -#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) -#define SCT_INPUT_AIN4_MASK (0x10U) -#define SCT_INPUT_AIN4_SHIFT (4U) -#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) -#define SCT_INPUT_AIN5_MASK (0x20U) -#define SCT_INPUT_AIN5_SHIFT (5U) -#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) -#define SCT_INPUT_AIN6_MASK (0x40U) -#define SCT_INPUT_AIN6_SHIFT (6U) -#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) -#define SCT_INPUT_AIN7_MASK (0x80U) -#define SCT_INPUT_AIN7_SHIFT (7U) -#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) -#define SCT_INPUT_AIN8_MASK (0x100U) -#define SCT_INPUT_AIN8_SHIFT (8U) -#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) -#define SCT_INPUT_AIN9_MASK (0x200U) -#define SCT_INPUT_AIN9_SHIFT (9U) -#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) -#define SCT_INPUT_AIN10_MASK (0x400U) -#define SCT_INPUT_AIN10_SHIFT (10U) -#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) -#define SCT_INPUT_AIN11_MASK (0x800U) -#define SCT_INPUT_AIN11_SHIFT (11U) -#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) -#define SCT_INPUT_AIN12_MASK (0x1000U) -#define SCT_INPUT_AIN12_SHIFT (12U) -#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) -#define SCT_INPUT_AIN13_MASK (0x2000U) -#define SCT_INPUT_AIN13_SHIFT (13U) -#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) -#define SCT_INPUT_AIN14_MASK (0x4000U) -#define SCT_INPUT_AIN14_SHIFT (14U) -#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) -#define SCT_INPUT_AIN15_MASK (0x8000U) -#define SCT_INPUT_AIN15_SHIFT (15U) -#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) -#define SCT_INPUT_SIN0_MASK (0x10000U) -#define SCT_INPUT_SIN0_SHIFT (16U) -#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) -#define SCT_INPUT_SIN1_MASK (0x20000U) -#define SCT_INPUT_SIN1_SHIFT (17U) -#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) -#define SCT_INPUT_SIN2_MASK (0x40000U) -#define SCT_INPUT_SIN2_SHIFT (18U) -#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) -#define SCT_INPUT_SIN3_MASK (0x80000U) -#define SCT_INPUT_SIN3_SHIFT (19U) -#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) -#define SCT_INPUT_SIN4_MASK (0x100000U) -#define SCT_INPUT_SIN4_SHIFT (20U) -#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) -#define SCT_INPUT_SIN5_MASK (0x200000U) -#define SCT_INPUT_SIN5_SHIFT (21U) -#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) -#define SCT_INPUT_SIN6_MASK (0x400000U) -#define SCT_INPUT_SIN6_SHIFT (22U) -#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) -#define SCT_INPUT_SIN7_MASK (0x800000U) -#define SCT_INPUT_SIN7_SHIFT (23U) -#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) -#define SCT_INPUT_SIN8_MASK (0x1000000U) -#define SCT_INPUT_SIN8_SHIFT (24U) -#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) -#define SCT_INPUT_SIN9_MASK (0x2000000U) -#define SCT_INPUT_SIN9_SHIFT (25U) -#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) -#define SCT_INPUT_SIN10_MASK (0x4000000U) -#define SCT_INPUT_SIN10_SHIFT (26U) -#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) -#define SCT_INPUT_SIN11_MASK (0x8000000U) -#define SCT_INPUT_SIN11_SHIFT (27U) -#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) -#define SCT_INPUT_SIN12_MASK (0x10000000U) -#define SCT_INPUT_SIN12_SHIFT (28U) -#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) -#define SCT_INPUT_SIN13_MASK (0x20000000U) -#define SCT_INPUT_SIN13_SHIFT (29U) -#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) -#define SCT_INPUT_SIN14_MASK (0x40000000U) -#define SCT_INPUT_SIN14_SHIFT (30U) -#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) -#define SCT_INPUT_SIN15_MASK (0x80000000U) -#define SCT_INPUT_SIN15_SHIFT (31U) -#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) -/*! @} */ - -/*! @name REGMODE - SCT match/capture mode register */ -/*! @{ */ -#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) -#define SCT_REGMODE_REGMOD_L_SHIFT (0U) -#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) -#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) -#define SCT_REGMODE_REGMOD_H_SHIFT (16U) -#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) -/*! @} */ - -/*! @name OUTPUT - SCT output register */ -/*! @{ */ -#define SCT_OUTPUT_OUT_MASK (0xFFFFU) -#define SCT_OUTPUT_OUT_SHIFT (0U) -#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) -/*! @} */ - -/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ -/*! @{ */ -#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) -#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) -#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) -#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) -#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) -#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) -#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) -#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) -#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) -#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) -#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) -#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) -#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) -#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) -#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) -#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) -#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) -#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) -#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) -#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) -#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) -#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) -#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) -#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) -#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) -#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) -#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) -#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) -#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) -/*! @} */ - -/*! @name RES - SCT conflict resolution register */ -/*! @{ */ -#define SCT_RES_O0RES_MASK (0x3U) -#define SCT_RES_O0RES_SHIFT (0U) -#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) -#define SCT_RES_O1RES_MASK (0xCU) -#define SCT_RES_O1RES_SHIFT (2U) -#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) -#define SCT_RES_O2RES_MASK (0x30U) -#define SCT_RES_O2RES_SHIFT (4U) -#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) -#define SCT_RES_O3RES_MASK (0xC0U) -#define SCT_RES_O3RES_SHIFT (6U) -#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) -#define SCT_RES_O4RES_MASK (0x300U) -#define SCT_RES_O4RES_SHIFT (8U) -#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) -#define SCT_RES_O5RES_MASK (0xC00U) -#define SCT_RES_O5RES_SHIFT (10U) -#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) -#define SCT_RES_O6RES_MASK (0x3000U) -#define SCT_RES_O6RES_SHIFT (12U) -#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) -#define SCT_RES_O7RES_MASK (0xC000U) -#define SCT_RES_O7RES_SHIFT (14U) -#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) -#define SCT_RES_O8RES_MASK (0x30000U) -#define SCT_RES_O8RES_SHIFT (16U) -#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) -#define SCT_RES_O9RES_MASK (0xC0000U) -#define SCT_RES_O9RES_SHIFT (18U) -#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) -#define SCT_RES_O10RES_MASK (0x300000U) -#define SCT_RES_O10RES_SHIFT (20U) -#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) -#define SCT_RES_O11RES_MASK (0xC00000U) -#define SCT_RES_O11RES_SHIFT (22U) -#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) -#define SCT_RES_O12RES_MASK (0x3000000U) -#define SCT_RES_O12RES_SHIFT (24U) -#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) -#define SCT_RES_O13RES_MASK (0xC000000U) -#define SCT_RES_O13RES_SHIFT (26U) -#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) -#define SCT_RES_O14RES_MASK (0x30000000U) -#define SCT_RES_O14RES_SHIFT (28U) -#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) -#define SCT_RES_O15RES_MASK (0xC0000000U) -#define SCT_RES_O15RES_SHIFT (30U) -#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) -/*! @} */ - -/*! @name DMA0REQUEST - SCT DMA request 0 register */ -/*! @{ */ -#define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU) -#define SCT_DMA0REQUEST_DEV_0_SHIFT (0U) -#define SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK) -#define SCT_DMA0REQUEST_DRL0_MASK (0x40000000U) -#define SCT_DMA0REQUEST_DRL0_SHIFT (30U) -#define SCT_DMA0REQUEST_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK) -#define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U) -#define SCT_DMA0REQUEST_DRQ0_SHIFT (31U) -#define SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK) -/*! @} */ - -/*! @name DMA1REQUEST - SCT DMA request 1 register */ -/*! @{ */ -#define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU) -#define SCT_DMA1REQUEST_DEV_1_SHIFT (0U) -#define SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK) -#define SCT_DMA1REQUEST_DRL1_MASK (0x40000000U) -#define SCT_DMA1REQUEST_DRL1_SHIFT (30U) -#define SCT_DMA1REQUEST_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK) -#define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U) -#define SCT_DMA1REQUEST_DRQ1_SHIFT (31U) -#define SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK) -/*! @} */ - -/*! @name EVEN - SCT event interrupt enable register */ -/*! @{ */ -#define SCT_EVEN_IEN_MASK (0xFFFFU) -#define SCT_EVEN_IEN_SHIFT (0U) -#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) -/*! @} */ - -/*! @name EVFLAG - SCT event flag register */ -/*! @{ */ -#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) -#define SCT_EVFLAG_FLAG_SHIFT (0U) -#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) -/*! @} */ - -/*! @name CONEN - SCT conflict interrupt enable register */ -/*! @{ */ -#define SCT_CONEN_NCEN_MASK (0xFFFFU) -#define SCT_CONEN_NCEN_SHIFT (0U) -#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) -/*! @} */ - -/*! @name CONFLAG - SCT conflict flag register */ -/*! @{ */ -#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) -#define SCT_CONFLAG_NCFLAG_SHIFT (0U) -#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) -#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) -#define SCT_CONFLAG_BUSERRL_SHIFT (30U) -#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) -#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) -#define SCT_CONFLAG_BUSERRH_SHIFT (31U) -#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) -/*! @} */ - -/*! @name SCTCAP - SCT capture register of capture channel */ -/*! @{ */ -#define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU) -#define SCT_SCTCAP_CAPn_L_SHIFT (0U) -#define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK) -#define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U) -#define SCT_SCTCAP_CAPn_H_SHIFT (16U) -#define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK) -/*! @} */ - -/* The count of SCT_SCTCAP */ -#define SCT_SCTCAP_COUNT (10U) - -/*! @name SCTMATCH - SCT match value register of match channels */ -/*! @{ */ -#define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU) -#define SCT_SCTMATCH_MATCHn_L_SHIFT (0U) -#define SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK) -#define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U) -#define SCT_SCTMATCH_MATCHn_H_SHIFT (16U) -#define SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK) -/*! @} */ - -/* The count of SCT_SCTMATCH */ -#define SCT_SCTMATCH_COUNT (10U) - -/*! @name SCTCAPCTRL - SCT capture control register */ -/*! @{ */ -#define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU) -#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U) -#define SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK) -#define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) -#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U) -#define SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK) -/*! @} */ - -/* The count of SCT_SCTCAPCTRL */ -#define SCT_SCTCAPCTRL_COUNT (10U) - -/*! @name SCTMATCHREL - SCT match reload value register */ -/*! @{ */ -#define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU) -#define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U) -#define SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK) -#define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U) -#define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U) -#define SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK) -/*! @} */ - -/* The count of SCT_SCTMATCHREL */ -#define SCT_SCTMATCHREL_COUNT (10U) - -/*! @name EVENT_STATE - SCT event state register 0 */ -/*! @{ */ -#define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU) -#define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U) -#define SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK) -/*! @} */ - -/* The count of SCT_EVENT_STATE */ -#define SCT_EVENT_STATE_COUNT (10U) - -/*! @name EVENT_CTRL - SCT event control register 0 */ -/*! @{ */ -#define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU) -#define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U) -#define SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK) -#define SCT_EVENT_CTRL_HEVENT_MASK (0x10U) -#define SCT_EVENT_CTRL_HEVENT_SHIFT (4U) -#define SCT_EVENT_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK) -#define SCT_EVENT_CTRL_OUTSEL_MASK (0x20U) -#define SCT_EVENT_CTRL_OUTSEL_SHIFT (5U) -#define SCT_EVENT_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK) -#define SCT_EVENT_CTRL_IOSEL_MASK (0x3C0U) -#define SCT_EVENT_CTRL_IOSEL_SHIFT (6U) -#define SCT_EVENT_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK) -#define SCT_EVENT_CTRL_IOCOND_MASK (0xC00U) -#define SCT_EVENT_CTRL_IOCOND_SHIFT (10U) -#define SCT_EVENT_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK) -#define SCT_EVENT_CTRL_COMBMODE_MASK (0x3000U) -#define SCT_EVENT_CTRL_COMBMODE_SHIFT (12U) -#define SCT_EVENT_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK) -#define SCT_EVENT_CTRL_STATELD_MASK (0x4000U) -#define SCT_EVENT_CTRL_STATELD_SHIFT (14U) -#define SCT_EVENT_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK) -#define SCT_EVENT_CTRL_STATEV_MASK (0xF8000U) -#define SCT_EVENT_CTRL_STATEV_SHIFT (15U) -#define SCT_EVENT_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK) -#define SCT_EVENT_CTRL_MATCHMEM_MASK (0x100000U) -#define SCT_EVENT_CTRL_MATCHMEM_SHIFT (20U) -#define SCT_EVENT_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK) -#define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U) -#define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U) -#define SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK) -/*! @} */ - -/* The count of SCT_EVENT_CTRL */ -#define SCT_EVENT_CTRL_COUNT (10U) - -/*! @name OUT_SET - SCT output 0 set register */ -/*! @{ */ -#define SCT_OUT_SET_SET_MASK (0xFFFFU) -#define SCT_OUT_SET_SET_SHIFT (0U) -#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) -/*! @} */ - -/* The count of SCT_OUT_SET */ -#define SCT_OUT_SET_COUNT (8U) - -/*! @name OUT_CLR - SCT output 0 clear register */ -/*! @{ */ -#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) -#define SCT_OUT_CLR_CLR_SHIFT (0U) -#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) -/*! @} */ - -/* The count of SCT_OUT_CLR */ -#define SCT_OUT_CLR_COUNT (8U) - - -/*! - * @} - */ /* end of group SCT_Register_Masks */ - - -/* SCT - Peripheral instance base addresses */ -/** Peripheral SCT0 base address */ -#define SCT0_BASE (0x40085000u) -/** Peripheral SCT0 base pointer */ -#define SCT0 ((SCT_Type *)SCT0_BASE) -/** Array initializer of SCT peripheral base addresses */ -#define SCT_BASE_ADDRS { SCT0_BASE } -/** Array initializer of SCT peripheral base pointers */ -#define SCT_BASE_PTRS { SCT0 } -/** Interrupt vectors for the SCT peripheral type */ -#define SCT_IRQS { SCT0_IRQn } - -/*! - * @} - */ /* end of group SCT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer - * @{ - */ - -/** SPI - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[1024]; - __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ - __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ - __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ - __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ - __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ - __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ - uint8_t RESERVED_2[2516]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_6[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ -} SPI_Type; - -/* ---------------------------------------------------------------------------- - -- SPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Register_Masks SPI Register Masks - * @{ - */ - -/*! @name CFG - SPI Configuration register */ -/*! @{ */ -#define SPI_CFG_ENABLE_MASK (0x1U) -#define SPI_CFG_ENABLE_SHIFT (0U) -#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) -#define SPI_CFG_MASTER_MASK (0x4U) -#define SPI_CFG_MASTER_SHIFT (2U) -#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) -#define SPI_CFG_LSBF_MASK (0x8U) -#define SPI_CFG_LSBF_SHIFT (3U) -#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) -#define SPI_CFG_CPHA_MASK (0x10U) -#define SPI_CFG_CPHA_SHIFT (4U) -#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) -#define SPI_CFG_CPOL_MASK (0x20U) -#define SPI_CFG_CPOL_SHIFT (5U) -#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) -#define SPI_CFG_LOOP_MASK (0x80U) -#define SPI_CFG_LOOP_SHIFT (7U) -#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) -#define SPI_CFG_SPOL0_MASK (0x100U) -#define SPI_CFG_SPOL0_SHIFT (8U) -#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) -#define SPI_CFG_SPOL1_MASK (0x200U) -#define SPI_CFG_SPOL1_SHIFT (9U) -#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) -#define SPI_CFG_SPOL2_MASK (0x400U) -#define SPI_CFG_SPOL2_SHIFT (10U) -#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) -#define SPI_CFG_SPOL3_MASK (0x800U) -#define SPI_CFG_SPOL3_SHIFT (11U) -#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) -/*! @} */ - -/*! @name DLY - SPI Delay register */ -/*! @{ */ -#define SPI_DLY_PRE_DELAY_MASK (0xFU) -#define SPI_DLY_PRE_DELAY_SHIFT (0U) -#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) -#define SPI_DLY_POST_DELAY_MASK (0xF0U) -#define SPI_DLY_POST_DELAY_SHIFT (4U) -#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) -#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) -#define SPI_DLY_FRAME_DELAY_SHIFT (8U) -#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) -#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) -#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) -#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) -/*! @} */ - -/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ -/*! @{ */ -#define SPI_STAT_SSA_MASK (0x10U) -#define SPI_STAT_SSA_SHIFT (4U) -#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) -#define SPI_STAT_SSD_MASK (0x20U) -#define SPI_STAT_SSD_SHIFT (5U) -#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) -#define SPI_STAT_STALLED_MASK (0x40U) -#define SPI_STAT_STALLED_SHIFT (6U) -#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) -#define SPI_STAT_ENDTRANSFER_MASK (0x80U) -#define SPI_STAT_ENDTRANSFER_SHIFT (7U) -#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) -#define SPI_STAT_MSTIDLE_MASK (0x100U) -#define SPI_STAT_MSTIDLE_SHIFT (8U) -#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -/*! @{ */ -#define SPI_INTENSET_SSAEN_MASK (0x10U) -#define SPI_INTENSET_SSAEN_SHIFT (4U) -#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) -#define SPI_INTENSET_SSDEN_MASK (0x20U) -#define SPI_INTENSET_SSDEN_SHIFT (5U) -#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) -#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) -#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) -#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) -/*! @} */ - -/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ -/*! @{ */ -#define SPI_INTENCLR_SSAEN_MASK (0x10U) -#define SPI_INTENCLR_SSAEN_SHIFT (4U) -#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) -#define SPI_INTENCLR_SSDEN_MASK (0x20U) -#define SPI_INTENCLR_SSDEN_SHIFT (5U) -#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) -#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) -#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) -#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) -/*! @} */ - -/*! @name DIV - SPI clock Divider */ -/*! @{ */ -#define SPI_DIV_DIVVAL_MASK (0xFFFFU) -#define SPI_DIV_DIVVAL_SHIFT (0U) -#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - SPI Interrupt Status */ -/*! @{ */ -#define SPI_INTSTAT_SSA_MASK (0x10U) -#define SPI_INTSTAT_SSA_SHIFT (4U) -#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) -#define SPI_INTSTAT_SSD_MASK (0x20U) -#define SPI_INTSTAT_SSD_SHIFT (5U) -#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) -#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) -#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) -#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ -#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) -#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) -#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) -#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) -#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) -#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) -#define SPI_FIFOCFG_SIZE_MASK (0x30U) -#define SPI_FIFOCFG_SIZE_SHIFT (4U) -#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) -#define SPI_FIFOCFG_DMATX_MASK (0x1000U) -#define SPI_FIFOCFG_DMATX_SHIFT (12U) -#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) -#define SPI_FIFOCFG_DMARX_MASK (0x2000U) -#define SPI_FIFOCFG_DMARX_SHIFT (13U) -#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) -#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) -#define SPI_FIFOCFG_WAKETX_SHIFT (14U) -#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) -#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) -#define SPI_FIFOCFG_WAKERX_SHIFT (15U) -#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) -#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) -#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) -#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) -#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ -#define SPI_FIFOSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOSTAT_TXERR_SHIFT (0U) -#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) -#define SPI_FIFOSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOSTAT_RXERR_SHIFT (1U) -#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) -#define SPI_FIFOSTAT_PERINT_MASK (0x8U) -#define SPI_FIFOSTAT_PERINT_SHIFT (3U) -#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) -#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) -#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) -#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) -#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) -#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) -#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) -#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) -#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) -#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) -#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) -#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) -#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ -#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) -#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) -#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) -#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) -#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) -#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) -#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) -#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) -#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ -#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) -#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) -#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) -#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) -#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) -#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) -#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) -#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) -#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) -#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ -#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) -#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) -#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) -#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) -#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) -#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) -#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) -#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) -#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) -#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ -#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) -#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) -#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) -#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) -#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) -#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) -#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) -#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) -#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) -#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) -#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ -#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) -#define SPI_FIFOWR_TXDATA_SHIFT (0U) -#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) -#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) -#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) -#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) -#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) -#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) -#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) -#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) -#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) -#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) -#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) -#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) -#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) -#define SPI_FIFOWR_EOT_MASK (0x100000U) -#define SPI_FIFOWR_EOT_SHIFT (20U) -#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) -#define SPI_FIFOWR_EOF_MASK (0x200000U) -#define SPI_FIFOWR_EOF_SHIFT (21U) -#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) -#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) -#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) -#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) -#define SPI_FIFOWR_LEN_MASK (0xF000000U) -#define SPI_FIFOWR_LEN_SHIFT (24U) -#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ -#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORD_RXDATA_SHIFT (0U) -#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) -#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) -#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) -#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) -#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) -#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) -#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) -#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) -#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) -#define SPI_FIFORD_SOT_MASK (0x100000U) -#define SPI_FIFORD_SOT_SHIFT (20U) -#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ -#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) -#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) -#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) -#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) -#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) -#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) -#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) -#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) -#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) -#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) -#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) -#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) -#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SPI_Register_Masks */ - - -/* SPI - Peripheral instance base addresses */ -/** Peripheral SPI0 base address */ -#define SPI0_BASE (0x40086000u) -/** Peripheral SPI0 base pointer */ -#define SPI0 ((SPI_Type *)SPI0_BASE) -/** Peripheral SPI1 base address */ -#define SPI1_BASE (0x40087000u) -/** Peripheral SPI1 base pointer */ -#define SPI1 ((SPI_Type *)SPI1_BASE) -/** Peripheral SPI2 base address */ -#define SPI2_BASE (0x40088000u) -/** Peripheral SPI2 base pointer */ -#define SPI2 ((SPI_Type *)SPI2_BASE) -/** Peripheral SPI3 base address */ -#define SPI3_BASE (0x40089000u) -/** Peripheral SPI3 base pointer */ -#define SPI3 ((SPI_Type *)SPI3_BASE) -/** Peripheral SPI4 base address */ -#define SPI4_BASE (0x4008A000u) -/** Peripheral SPI4 base pointer */ -#define SPI4 ((SPI_Type *)SPI4_BASE) -/** Peripheral SPI5 base address */ -#define SPI5_BASE (0x40096000u) -/** Peripheral SPI5 base pointer */ -#define SPI5 ((SPI_Type *)SPI5_BASE) -/** Peripheral SPI6 base address */ -#define SPI6_BASE (0x40097000u) -/** Peripheral SPI6 base pointer */ -#define SPI6 ((SPI_Type *)SPI6_BASE) -/** Peripheral SPI7 base address */ -#define SPI7_BASE (0x40098000u) -/** Peripheral SPI7 base pointer */ -#define SPI7 ((SPI_Type *)SPI7_BASE) -/** Array initializer of SPI peripheral base addresses */ -#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE } -/** Array initializer of SPI peripheral base pointers */ -#define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7 } -/** Interrupt vectors for the SPI peripheral type */ -#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group SPI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPIFI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPIFI_Peripheral_Access_Layer SPIFI Peripheral Access Layer - * @{ - */ - -/** SPIFI - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< SPIFI control register, offset: 0x0 */ - __IO uint32_t CMD; /**< SPIFI command register, offset: 0x4 */ - __IO uint32_t ADDR; /**< SPIFI address register, offset: 0x8 */ - __IO uint32_t IDATA; /**< SPIFI intermediate data register, offset: 0xC */ - __IO uint32_t CLIMIT; /**< SPIFI limit register, offset: 0x10 */ - __IO uint32_t DATA; /**< SPIFI data register, offset: 0x14 */ - __IO uint32_t MCMD; /**< SPIFI memory command register, offset: 0x18 */ - __IO uint32_t STAT; /**< SPIFI status register, offset: 0x1C */ -} SPIFI_Type; - -/* ---------------------------------------------------------------------------- - -- SPIFI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPIFI_Register_Masks SPIFI Register Masks - * @{ - */ - -/*! @name CTRL - SPIFI control register */ -/*! @{ */ -#define SPIFI_CTRL_TIMEOUT_MASK (0xFFFFU) -#define SPIFI_CTRL_TIMEOUT_SHIFT (0U) -#define SPIFI_CTRL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK) -#define SPIFI_CTRL_CSHIGH_MASK (0xF0000U) -#define SPIFI_CTRL_CSHIGH_SHIFT (16U) -#define SPIFI_CTRL_CSHIGH(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK) -#define SPIFI_CTRL_D_PRFTCH_DIS_MASK (0x200000U) -#define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT (21U) -#define SPIFI_CTRL_D_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK) -#define SPIFI_CTRL_INTEN_MASK (0x400000U) -#define SPIFI_CTRL_INTEN_SHIFT (22U) -#define SPIFI_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK) -#define SPIFI_CTRL_MODE3_MASK (0x800000U) -#define SPIFI_CTRL_MODE3_SHIFT (23U) -#define SPIFI_CTRL_MODE3(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK) -#define SPIFI_CTRL_PRFTCH_DIS_MASK (0x8000000U) -#define SPIFI_CTRL_PRFTCH_DIS_SHIFT (27U) -#define SPIFI_CTRL_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK) -#define SPIFI_CTRL_DUAL_MASK (0x10000000U) -#define SPIFI_CTRL_DUAL_SHIFT (28U) -#define SPIFI_CTRL_DUAL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK) -#define SPIFI_CTRL_RFCLK_MASK (0x20000000U) -#define SPIFI_CTRL_RFCLK_SHIFT (29U) -#define SPIFI_CTRL_RFCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK) -#define SPIFI_CTRL_FBCLK_MASK (0x40000000U) -#define SPIFI_CTRL_FBCLK_SHIFT (30U) -#define SPIFI_CTRL_FBCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK) -#define SPIFI_CTRL_DMAEN_MASK (0x80000000U) -#define SPIFI_CTRL_DMAEN_SHIFT (31U) -#define SPIFI_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK) -/*! @} */ - -/*! @name CMD - SPIFI command register */ -/*! @{ */ -#define SPIFI_CMD_DATALEN_MASK (0x3FFFU) -#define SPIFI_CMD_DATALEN_SHIFT (0U) -#define SPIFI_CMD_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK) -#define SPIFI_CMD_POLL_MASK (0x4000U) -#define SPIFI_CMD_POLL_SHIFT (14U) -#define SPIFI_CMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK) -#define SPIFI_CMD_DOUT_MASK (0x8000U) -#define SPIFI_CMD_DOUT_SHIFT (15U) -#define SPIFI_CMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK) -#define SPIFI_CMD_INTLEN_MASK (0x70000U) -#define SPIFI_CMD_INTLEN_SHIFT (16U) -#define SPIFI_CMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK) -#define SPIFI_CMD_FIELDFORM_MASK (0x180000U) -#define SPIFI_CMD_FIELDFORM_SHIFT (19U) -#define SPIFI_CMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK) -#define SPIFI_CMD_FRAMEFORM_MASK (0xE00000U) -#define SPIFI_CMD_FRAMEFORM_SHIFT (21U) -#define SPIFI_CMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK) -#define SPIFI_CMD_OPCODE_MASK (0xFF000000U) -#define SPIFI_CMD_OPCODE_SHIFT (24U) -#define SPIFI_CMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK) -/*! @} */ - -/*! @name ADDR - SPIFI address register */ -/*! @{ */ -#define SPIFI_ADDR_ADDRESS_MASK (0xFFFFFFFFU) -#define SPIFI_ADDR_ADDRESS_SHIFT (0U) -#define SPIFI_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK) -/*! @} */ - -/*! @name IDATA - SPIFI intermediate data register */ -/*! @{ */ -#define SPIFI_IDATA_IDATA_MASK (0xFFFFFFFFU) -#define SPIFI_IDATA_IDATA_SHIFT (0U) -#define SPIFI_IDATA_IDATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK) -/*! @} */ - -/*! @name CLIMIT - SPIFI limit register */ -/*! @{ */ -#define SPIFI_CLIMIT_CLIMIT_MASK (0xFFFFFFFFU) -#define SPIFI_CLIMIT_CLIMIT_SHIFT (0U) -#define SPIFI_CLIMIT_CLIMIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK) -/*! @} */ - -/*! @name DATA - SPIFI data register */ -/*! @{ */ -#define SPIFI_DATA_DATA_MASK (0xFFFFFFFFU) -#define SPIFI_DATA_DATA_SHIFT (0U) -#define SPIFI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK) -/*! @} */ - -/*! @name MCMD - SPIFI memory command register */ -/*! @{ */ -#define SPIFI_MCMD_POLL_MASK (0x4000U) -#define SPIFI_MCMD_POLL_SHIFT (14U) -#define SPIFI_MCMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK) -#define SPIFI_MCMD_DOUT_MASK (0x8000U) -#define SPIFI_MCMD_DOUT_SHIFT (15U) -#define SPIFI_MCMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK) -#define SPIFI_MCMD_INTLEN_MASK (0x70000U) -#define SPIFI_MCMD_INTLEN_SHIFT (16U) -#define SPIFI_MCMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK) -#define SPIFI_MCMD_FIELDFORM_MASK (0x180000U) -#define SPIFI_MCMD_FIELDFORM_SHIFT (19U) -#define SPIFI_MCMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK) -#define SPIFI_MCMD_FRAMEFORM_MASK (0xE00000U) -#define SPIFI_MCMD_FRAMEFORM_SHIFT (21U) -#define SPIFI_MCMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK) -#define SPIFI_MCMD_OPCODE_MASK (0xFF000000U) -#define SPIFI_MCMD_OPCODE_SHIFT (24U) -#define SPIFI_MCMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK) -/*! @} */ - -/*! @name STAT - SPIFI status register */ -/*! @{ */ -#define SPIFI_STAT_MCINIT_MASK (0x1U) -#define SPIFI_STAT_MCINIT_SHIFT (0U) -#define SPIFI_STAT_MCINIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK) -#define SPIFI_STAT_CMD_MASK (0x2U) -#define SPIFI_STAT_CMD_SHIFT (1U) -#define SPIFI_STAT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK) -#define SPIFI_STAT_RESET_MASK (0x10U) -#define SPIFI_STAT_RESET_SHIFT (4U) -#define SPIFI_STAT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK) -#define SPIFI_STAT_INTRQ_MASK (0x20U) -#define SPIFI_STAT_INTRQ_SHIFT (5U) -#define SPIFI_STAT_INTRQ(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK) -#define SPIFI_STAT_VERSION_MASK (0xFF000000U) -#define SPIFI_STAT_VERSION_SHIFT (24U) -#define SPIFI_STAT_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_VERSION_SHIFT)) & SPIFI_STAT_VERSION_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SPIFI_Register_Masks */ - - -/* SPIFI - Peripheral instance base addresses */ -/** Peripheral SPIFI0 base address */ -#define SPIFI0_BASE (0x40080000u) -/** Peripheral SPIFI0 base pointer */ -#define SPIFI0 ((SPIFI_Type *)SPIFI0_BASE) -/** Array initializer of SPIFI peripheral base addresses */ -#define SPIFI_BASE_ADDRS { SPIFI0_BASE } -/** Array initializer of SPIFI peripheral base pointers */ -#define SPIFI_BASE_PTRS { SPIFI0 } -/** Interrupt vectors for the SPIFI peripheral type */ -#define SPIFI_IRQS { SPIFI0_IRQn } - -/*! - * @} - */ /* end of group SPIFI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SYSCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer - * @{ - */ - -/** SYSCON - Register Layout Typedef */ -typedef struct { - uint32_t SYSMEMREMAP; /**< System Remap register, offset: 0x0 */ - uint8_t RESERVED_0[12]; - __IO uint32_t AHBMATPRIO; /**< AHB multilayer matrix priority control, offset: 0x10 */ - uint8_t RESERVED_1[44]; - __IO uint32_t SYSTCKCAL; /**< System tick counter calibration, offset: 0x40 */ - uint8_t RESERVED_2[4]; - __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ - __IO uint32_t ASYNCAPBCTRL; /**< Asynchronous APB Control, offset: 0x4C */ - uint8_t RESERVED_3[112]; - __I uint32_t PIOPORCAP[2]; /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */ - uint8_t RESERVED_4[8]; - __I uint32_t PIORESCAP[2]; /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */ - uint8_t RESERVED_5[40]; - __IO uint32_t PRESETCTRL[2]; /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */ - uint8_t RESERVED_6[24]; - __O uint32_t PRESETCTRLSET[2]; /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */ - uint8_t RESERVED_7[24]; - __O uint32_t PRESETCTRLCLR[2]; /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */ - uint8_t RESERVED_8[168]; - __IO uint32_t SYSRSTSTAT; /**< System reset status register, offset: 0x1F0 */ - uint8_t RESERVED_9[12]; - __IO uint32_t AHBCLKCTRL[2]; /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_10[24]; - __O uint32_t AHBCLKCTRLSET[2]; /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */ - uint8_t RESERVED_11[24]; - __O uint32_t AHBCLKCTRLCLR[2]; /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */ - uint8_t RESERVED_12[56]; - __IO uint32_t MAINCLKSELA; /**< Main clock source select A, offset: 0x280 */ - __IO uint32_t MAINCLKSELB; /**< Main clock source select B, offset: 0x284 */ - __IO uint32_t CLKOUTSELA; /**< CLKOUT clock source select A, offset: 0x288 */ - uint8_t RESERVED_13[4]; - __IO uint32_t SYSPLLCLKSEL; /**< PLL clock source select, offset: 0x290 */ - uint8_t RESERVED_14[12]; - __IO uint32_t SPIFICLKSEL; /**< SPIFI clock source select, offset: 0x2A0 */ - __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ - __IO uint32_t USBCLKSEL; /**< USB clock source select, offset: 0x2A8 */ - uint8_t RESERVED_15[4]; - __IO uint32_t FXCOMCLKSEL[8]; /**< Flexcomm 0 clock source select, array offset: 0x2B0, array step: 0x4 */ - uint8_t RESERVED_16[16]; - __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ - uint8_t RESERVED_17[4]; - __IO uint32_t FRGCLKSEL; /**< Fractional Rate Generator clock source select, offset: 0x2E8 */ - __IO uint32_t DMICCLKSEL; /**< Digital microphone (D-Mic) subsystem clock select, offset: 0x2EC */ - uint8_t RESERVED_18[16]; - __IO uint32_t SYSTICKCLKDIV; /**< SYSTICK clock divider, offset: 0x300 */ - __IO uint32_t TRACECLKDIV; /**< Trace clock divider, offset: 0x304 */ - uint8_t RESERVED_19[120]; - __IO uint32_t AHBCLKDIV; /**< AHB clock divider, offset: 0x380 */ - __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ - uint8_t RESERVED_20[8]; - __IO uint32_t SPIFICLKDIV; /**< SPIFI clock divider, offset: 0x390 */ - __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ - __IO uint32_t USBCLKDIV; /**< USB clock divider, offset: 0x398 */ - uint8_t RESERVED_21[4]; - __IO uint32_t FRGCTRL; /**< Fractional rate divider, offset: 0x3A0 */ - uint8_t RESERVED_22[4]; - __IO uint32_t DMICCLKDIV; /**< DMIC clock divider, offset: 0x3A8 */ - __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ - uint8_t RESERVED_23[80]; - __IO uint32_t FLASHCFG; /**< Flash wait states configuration, offset: 0x400 */ - uint8_t RESERVED_24[8]; - __IO uint32_t USBCLKCTRL; /**< USB clock control, offset: 0x40C */ - __IO uint32_t USBCLKSTAT; /**< USB clock status, offset: 0x410 */ - uint8_t RESERVED_25[4]; - __IO uint32_t FREQMECTRL; /**< Frequency measure register, offset: 0x418 */ - uint8_t RESERVED_26[4]; - __IO uint32_t MCLKIO; /**< MCLK input/output control, offset: 0x420 */ - uint8_t RESERVED_27[220]; - __IO uint32_t FROCTRL; /**< FRO oscillator control, offset: 0x500 */ - uint8_t RESERVED_28[4]; - __IO uint32_t WDTOSCCTRL; /**< Watchdog oscillator control, offset: 0x508 */ - __IO uint32_t RTCOSCCTRL; /**< RTC oscillator 32 kHz output control, offset: 0x50C */ - uint8_t RESERVED_29[112]; - __IO uint32_t SYSPLLCTRL; /**< PLL control, offset: 0x580 */ - __I uint32_t SYSPLLSTAT; /**< PLL status, offset: 0x584 */ - __IO uint32_t SYSPLLNDEC; /**< PLL N decoder, offset: 0x588 */ - __IO uint32_t SYSPLLPDEC; /**< PLL P decoder, offset: 0x58C */ - __IO uint32_t SYSPLLSSCTRL0; /**< PLL spread spectrum control 0, offset: 0x590 */ - __IO uint32_t SYSPLLSSCTRL1; /**< PLL spread spectrum control 1, offset: 0x594 */ - uint8_t RESERVED_30[104]; - __IO uint32_t PDSLEEPCFG[2]; /**< Sleep configuration register n, array offset: 0x600, array step: 0x4 */ - uint8_t RESERVED_31[8]; - __IO uint32_t PDRUNCFG[2]; /**< Power configuration register n, array offset: 0x610, array step: 0x4 */ - uint8_t RESERVED_32[8]; - __O uint32_t PDRUNCFGSET[2]; /**< Set bits in PDRUNCFGn, array offset: 0x620, array step: 0x4 */ - uint8_t RESERVED_33[8]; - __O uint32_t PDRUNCFGCLR[2]; /**< Clear bits in PDRUNCFGn, array offset: 0x630, array step: 0x4 */ - uint8_t RESERVED_34[72]; - __IO uint32_t STARTERP[2]; /**< Start logic n wake-up enable register, array offset: 0x680, array step: 0x4 */ - uint8_t RESERVED_35[24]; - __O uint32_t STARTERSET[2]; /**< Set bits in STARTERn, array offset: 0x6A0, array step: 0x4 */ - uint8_t RESERVED_36[24]; - __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTERn, array offset: 0x6C0, array step: 0x4 */ - uint8_t RESERVED_37[184]; - __IO uint32_t HWWAKE; /**< Configures special cases of hardware wake-up, offset: 0x780 */ - uint8_t RESERVED_38[124]; - __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ - __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ - __IO uint32_t CPSTACK; /**< Coprocessor Stack Address, offset: 0x808 */ - __I uint32_t CPSTAT; /**< Coprocessor Status, offset: 0x80C */ - uint8_t RESERVED_39[1524]; - __IO uint32_t AUTOCGOR; /**< Auto Clock-Gate Override Register, offset: 0xE04 */ - uint8_t RESERVED_40[492]; - __I uint32_t JTAGIDCODE; /**< JTAG ID code register, offset: 0xFF4 */ - __I uint32_t DEVICE_ID0; /**< Part ID register, offset: 0xFF8 */ - __I uint32_t DEVICE_ID1; /**< Boot ROM and die revision register, offset: 0xFFC */ - uint8_t RESERVED_41[127044]; - __IO uint32_t BODCTRL; /**< Brown-Out Detect control, offset: 0x20044 */ -} SYSCON_Type; - -/* ---------------------------------------------------------------------------- - -- SYSCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Register_Masks SYSCON Register Masks - * @{ - */ - -/*! @name AHBMATPRIO - AHB multilayer matrix priority control */ -/*! @{ */ -#define SYSCON_AHBMATPRIO_PRI_ICODE_MASK (0x3U) -#define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT (0U) -#define SYSCON_AHBMATPRIO_PRI_ICODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK) -#define SYSCON_AHBMATPRIO_PRI_DCODE_MASK (0xCU) -#define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT (2U) -#define SYSCON_AHBMATPRIO_PRI_DCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK) -#define SYSCON_AHBMATPRIO_PRI_SYS_MASK (0x30U) -#define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT (4U) -#define SYSCON_AHBMATPRIO_PRI_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK) -#define SYSCON_AHBMATPRIO_PRI_M0_MASK (0xC0U) -#define SYSCON_AHBMATPRIO_PRI_M0_SHIFT (6U) -#define SYSCON_AHBMATPRIO_PRI_M0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_M0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_M0_MASK) -#define SYSCON_AHBMATPRIO_PRI_USB_MASK (0x300U) -#define SYSCON_AHBMATPRIO_PRI_USB_SHIFT (8U) -#define SYSCON_AHBMATPRIO_PRI_USB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_MASK) -#define SYSCON_AHBMATPRIO_PRI_DMA_MASK (0xC00U) -#define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT (10U) -#define SYSCON_AHBMATPRIO_PRI_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK) -/*! @} */ - -/*! @name SYSTCKCAL - System tick counter calibration */ -/*! @{ */ -#define SYSCON_SYSTCKCAL_CAL_MASK (0xFFFFFFU) -#define SYSCON_SYSTCKCAL_CAL_SHIFT (0U) -#define SYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK) -#define SYSCON_SYSTCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_SYSTCKCAL_SKEW_SHIFT (24U) -#define SYSCON_SYSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK) -#define SYSCON_SYSTCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_SYSTCKCAL_NOREF_SHIFT (25U) -#define SYSCON_SYSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name NMISRC - NMI Source Select */ -/*! @{ */ -#define SYSCON_NMISRC_IRQM4_MASK (0x3FU) -#define SYSCON_NMISRC_IRQM4_SHIFT (0U) -#define SYSCON_NMISRC_IRQM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK) -#define SYSCON_NMISRC_IRQM0_MASK (0x3F00U) -#define SYSCON_NMISRC_IRQM0_SHIFT (8U) -#define SYSCON_NMISRC_IRQM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM0_SHIFT)) & SYSCON_NMISRC_IRQM0_MASK) -#define SYSCON_NMISRC_NMIENM0_MASK (0x40000000U) -#define SYSCON_NMISRC_NMIENM0_SHIFT (30U) -#define SYSCON_NMISRC_NMIENM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM0_SHIFT)) & SYSCON_NMISRC_NMIENM0_MASK) -#define SYSCON_NMISRC_NMIENM4_MASK (0x80000000U) -#define SYSCON_NMISRC_NMIENM4_SHIFT (31U) -#define SYSCON_NMISRC_NMIENM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK) -/*! @} */ - -/*! @name ASYNCAPBCTRL - Asynchronous APB Control */ -/*! @{ */ -#define SYSCON_ASYNCAPBCTRL_ENABLE_MASK (0x1U) -#define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT (0U) -#define SYSCON_ASYNCAPBCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK) -/*! @} */ - -/*! @name PIOPORCAP - POR captured value of port n */ -/*! @{ */ -#define SYSCON_PIOPORCAP_PIOPORCAP_MASK (0xFFFFFFFFU) -#define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT (0U) -#define SYSCON_PIOPORCAP_PIOPORCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK) -/*! @} */ - -/* The count of SYSCON_PIOPORCAP */ -#define SYSCON_PIOPORCAP_COUNT (2U) - -/*! @name PIORESCAP - Reset captured value of port n */ -/*! @{ */ -#define SYSCON_PIORESCAP_PIORESCAP_MASK (0xFFFFFFFFU) -#define SYSCON_PIORESCAP_PIORESCAP_SHIFT (0U) -#define SYSCON_PIORESCAP_PIORESCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK) -/*! @} */ - -/* The count of SYSCON_PIORESCAP */ -#define SYSCON_PIORESCAP_COUNT (2U) - -/*! @name PRESETCTRL - Peripheral reset control n */ -/*! @{ */ -#define SYSCON_PRESETCTRL_MRT0_RST_MASK (0x1U) -#define SYSCON_PRESETCTRL_MRT0_RST_SHIFT (0U) -#define SYSCON_PRESETCTRL_MRT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT0_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT0_RST_MASK) -#define SYSCON_PRESETCTRL_SCT0_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL_SCT0_RST_SHIFT (2U) -#define SYSCON_PRESETCTRL_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK) -#define SYSCON_PRESETCTRL_FLASH_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL_FLASH_RST_SHIFT (7U) -#define SYSCON_PRESETCTRL_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL_FLASH_RST_MASK) -#define SYSCON_PRESETCTRL_FMC_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL_FMC_RST_SHIFT (8U) -#define SYSCON_PRESETCTRL_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL_FMC_RST_MASK) -#define SYSCON_PRESETCTRL_UTICK0_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL_UTICK0_RST_SHIFT (10U) -#define SYSCON_PRESETCTRL_UTICK0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK0_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK0_RST_MASK) -#define SYSCON_PRESETCTRL_FC0_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL_FC0_RST_SHIFT (11U) -#define SYSCON_PRESETCTRL_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK) -#define SYSCON_PRESETCTRL_MUX_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL_MUX_RST_SHIFT (11U) -#define SYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK) -#define SYSCON_PRESETCTRL_FC1_RST_MASK (0x1000U) -#define SYSCON_PRESETCTRL_FC1_RST_SHIFT (12U) -#define SYSCON_PRESETCTRL_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK) -#define SYSCON_PRESETCTRL_FC2_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL_FC2_RST_SHIFT (13U) -#define SYSCON_PRESETCTRL_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK) -#define SYSCON_PRESETCTRL_IOCON_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL_IOCON_RST_SHIFT (13U) -#define SYSCON_PRESETCTRL_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK) -#define SYSCON_PRESETCTRL_FC3_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL_FC3_RST_SHIFT (14U) -#define SYSCON_PRESETCTRL_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK) -#define SYSCON_PRESETCTRL_GPIO0_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT (14U) -#define SYSCON_PRESETCTRL_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK) -#define SYSCON_PRESETCTRL_FC4_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL_FC4_RST_SHIFT (15U) -#define SYSCON_PRESETCTRL_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK) -#define SYSCON_PRESETCTRL_GPIO1_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT (15U) -#define SYSCON_PRESETCTRL_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK) -#define SYSCON_PRESETCTRL_FC5_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL_FC5_RST_SHIFT (16U) -#define SYSCON_PRESETCTRL_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK) -#define SYSCON_PRESETCTRL_FC6_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL_FC6_RST_SHIFT (17U) -#define SYSCON_PRESETCTRL_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK) -#define SYSCON_PRESETCTRL_FC7_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL_FC7_RST_SHIFT (18U) -#define SYSCON_PRESETCTRL_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK) -#define SYSCON_PRESETCTRL_PINT_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL_PINT_RST_SHIFT (18U) -#define SYSCON_PRESETCTRL_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK) -#define SYSCON_PRESETCTRL_DMIC0_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL_DMIC0_RST_SHIFT (19U) -#define SYSCON_PRESETCTRL_DMIC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC0_RST_MASK) -#define SYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL_GINT_RST_SHIFT (19U) -#define SYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK) -#define SYSCON_PRESETCTRL_DMA0_RST_MASK (0x100000U) -#define SYSCON_PRESETCTRL_DMA0_RST_SHIFT (20U) -#define SYSCON_PRESETCTRL_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA0_RST_MASK) -#define SYSCON_PRESETCTRL_CRC_RST_MASK (0x200000U) -#define SYSCON_PRESETCTRL_CRC_RST_SHIFT (21U) -#define SYSCON_PRESETCTRL_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK) -#define SYSCON_PRESETCTRL_CTIMER2_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT (22U) -#define SYSCON_PRESETCTRL_CTIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER2_RST_MASK) -#define SYSCON_PRESETCTRL_WWDT_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL_WWDT_RST_SHIFT (22U) -#define SYSCON_PRESETCTRL_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK) -#define SYSCON_PRESETCTRL_USB0_RST_MASK (0x2000000U) -#define SYSCON_PRESETCTRL_USB0_RST_SHIFT (25U) -#define SYSCON_PRESETCTRL_USB0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0_RST_MASK) -#define SYSCON_PRESETCTRL_CTIMER0_RST_MASK (0x4000000U) -#define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT (26U) -#define SYSCON_PRESETCTRL_CTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK) -#define SYSCON_PRESETCTRL_ADC0_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL_ADC0_RST_SHIFT (27U) -#define SYSCON_PRESETCTRL_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK) -#define SYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U) -#define SYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRL */ -#define SYSCON_PRESETCTRL_COUNT (2U) - -/*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */ -/*! @{ */ -#define SYSCON_PRESETCTRLSET_RST_SET_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLSET_RST_SET_SHIFT (0U) -#define SYSCON_PRESETCTRLSET_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLSET */ -#define SYSCON_PRESETCTRLSET_COUNT (2U) - -/*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */ -/*! @{ */ -#define SYSCON_PRESETCTRLCLR_RST_CLR_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT (0U) -#define SYSCON_PRESETCTRLCLR_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLCLR */ -#define SYSCON_PRESETCTRLCLR_COUNT (2U) - -/*! @name SYSRSTSTAT - System reset status register */ -/*! @{ */ -#define SYSCON_SYSRSTSTAT_POR_MASK (0x1U) -#define SYSCON_SYSRSTSTAT_POR_SHIFT (0U) -#define SYSCON_SYSRSTSTAT_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK) -#define SYSCON_SYSRSTSTAT_EXTRST_MASK (0x2U) -#define SYSCON_SYSRSTSTAT_EXTRST_SHIFT (1U) -#define SYSCON_SYSRSTSTAT_EXTRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK) -#define SYSCON_SYSRSTSTAT_WDT_MASK (0x4U) -#define SYSCON_SYSRSTSTAT_WDT_SHIFT (2U) -#define SYSCON_SYSRSTSTAT_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK) -#define SYSCON_SYSRSTSTAT_BOD_MASK (0x8U) -#define SYSCON_SYSRSTSTAT_BOD_SHIFT (3U) -#define SYSCON_SYSRSTSTAT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK) -#define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U) -#define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U) -#define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL - AHB Clock control n */ -/*! @{ */ -#define SYSCON_AHBCLKCTRL_MRT0_MASK (0x1U) -#define SYSCON_AHBCLKCTRL_MRT0_SHIFT (0U) -#define SYSCON_AHBCLKCTRL_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT0_SHIFT)) & SYSCON_AHBCLKCTRL_MRT0_MASK) -#define SYSCON_AHBCLKCTRL_ROM_MASK (0x2U) -#define SYSCON_AHBCLKCTRL_ROM_SHIFT (1U) -#define SYSCON_AHBCLKCTRL_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK) -#define SYSCON_AHBCLKCTRL_SCT0_MASK (0x4U) -#define SYSCON_AHBCLKCTRL_SCT0_SHIFT (2U) -#define SYSCON_AHBCLKCTRL_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK) -#define SYSCON_AHBCLKCTRL_SRAM1_MASK (0x8U) -#define SYSCON_AHBCLKCTRL_SRAM1_SHIFT (3U) -#define SYSCON_AHBCLKCTRL_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM1_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM1_MASK) -#define SYSCON_AHBCLKCTRL_SRAM2_MASK (0x10U) -#define SYSCON_AHBCLKCTRL_SRAM2_SHIFT (4U) -#define SYSCON_AHBCLKCTRL_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM2_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM2_MASK) -#define SYSCON_AHBCLKCTRL_FLASH_MASK (0x80U) -#define SYSCON_AHBCLKCTRL_FLASH_SHIFT (7U) -#define SYSCON_AHBCLKCTRL_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL_FLASH_MASK) -#define SYSCON_AHBCLKCTRL_FMC_MASK (0x100U) -#define SYSCON_AHBCLKCTRL_FMC_SHIFT (8U) -#define SYSCON_AHBCLKCTRL_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FMC_SHIFT)) & SYSCON_AHBCLKCTRL_FMC_MASK) -#define SYSCON_AHBCLKCTRL_UTICK0_MASK (0x400U) -#define SYSCON_AHBCLKCTRL_UTICK0_SHIFT (10U) -#define SYSCON_AHBCLKCTRL_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK0_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK0_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK (0x800U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT (11U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK) -#define SYSCON_AHBCLKCTRL_INPUTMUX_MASK (0x800U) -#define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT (11U) -#define SYSCON_AHBCLKCTRL_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK (0x1000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT (12U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT (13U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK) -#define SYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL_IOCON_SHIFT (13U) -#define SYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT (14U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK) -#define SYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U) -#define SYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT (15U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK) -#define SYSCON_AHBCLKCTRL_GPIO1_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL_GPIO1_SHIFT (15U) -#define SYSCON_AHBCLKCTRL_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT (16U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT (17U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT (18U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK) -#define SYSCON_AHBCLKCTRL_PINT_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL_PINT_SHIFT (18U) -#define SYSCON_AHBCLKCTRL_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK) -#define SYSCON_AHBCLKCTRL_DMIC0_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL_DMIC0_SHIFT (19U) -#define SYSCON_AHBCLKCTRL_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC0_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC0_MASK) -#define SYSCON_AHBCLKCTRL_GINT_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL_GINT_SHIFT (19U) -#define SYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK) -#define SYSCON_AHBCLKCTRL_DMA0_MASK (0x100000U) -#define SYSCON_AHBCLKCTRL_DMA0_SHIFT (20U) -#define SYSCON_AHBCLKCTRL_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL_DMA0_MASK) -#define SYSCON_AHBCLKCTRL_CRC_MASK (0x200000U) -#define SYSCON_AHBCLKCTRL_CRC_SHIFT (21U) -#define SYSCON_AHBCLKCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK) -#define SYSCON_AHBCLKCTRL_CTIMER2_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL_CTIMER2_SHIFT (22U) -#define SYSCON_AHBCLKCTRL_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER2_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER2_MASK) -#define SYSCON_AHBCLKCTRL_WWDT_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL_WWDT_SHIFT (22U) -#define SYSCON_AHBCLKCTRL_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK) -#define SYSCON_AHBCLKCTRL_RTC_MASK (0x800000U) -#define SYSCON_AHBCLKCTRL_RTC_SHIFT (23U) -#define SYSCON_AHBCLKCTRL_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK) -#define SYSCON_AHBCLKCTRL_USB0_MASK (0x2000000U) -#define SYSCON_AHBCLKCTRL_USB0_SHIFT (25U) -#define SYSCON_AHBCLKCTRL_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0_SHIFT)) & SYSCON_AHBCLKCTRL_USB0_MASK) -#define SYSCON_AHBCLKCTRL_CTIMER0_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT (26U) -#define SYSCON_AHBCLKCTRL_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK) -#define SYSCON_AHBCLKCTRL_MAILBOX_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL_MAILBOX_SHIFT (26U) -#define SYSCON_AHBCLKCTRL_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL_MAILBOX_MASK) -#define SYSCON_AHBCLKCTRL_ADC0_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL_ADC0_SHIFT (27U) -#define SYSCON_AHBCLKCTRL_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK) -#define SYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U) -#define SYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRL */ -#define SYSCON_AHBCLKCTRL_COUNT (2U) - -/*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */ -/*! @{ */ -#define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT (0U) -#define SYSCON_AHBCLKCTRLSET_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLSET */ -#define SYSCON_AHBCLKCTRLSET_COUNT (2U) - -/*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */ -/*! @{ */ -#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT (0U) -#define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLCLR */ -#define SYSCON_AHBCLKCTRLCLR_COUNT (2U) - -/*! @name MAINCLKSELA - Main clock source select A */ -/*! @{ */ -#define SYSCON_MAINCLKSELA_SEL_MASK (0x3U) -#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) -#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) -/*! @} */ - -/*! @name MAINCLKSELB - Main clock source select B */ -/*! @{ */ -#define SYSCON_MAINCLKSELB_SEL_MASK (0x3U) -#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) -#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) -/*! @} */ - -/*! @name CLKOUTSELA - CLKOUT clock source select A */ -/*! @{ */ -#define SYSCON_CLKOUTSELA_SEL_MASK (0x7U) -#define SYSCON_CLKOUTSELA_SEL_SHIFT (0U) -#define SYSCON_CLKOUTSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK) -/*! @} */ - -/*! @name SYSPLLCLKSEL - PLL clock source select */ -/*! @{ */ -#define SYSCON_SYSPLLCLKSEL_SEL_MASK (0x7U) -#define SYSCON_SYSPLLCLKSEL_SEL_SHIFT (0U) -#define SYSCON_SYSPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SPIFICLKSEL - SPIFI clock source select */ -/*! @{ */ -#define SYSCON_SPIFICLKSEL_SEL_MASK (0x7U) -#define SYSCON_SPIFICLKSEL_SEL_SHIFT (0U) -#define SYSCON_SPIFICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK) -/*! @} */ - -/*! @name ADCCLKSEL - ADC clock source select */ -/*! @{ */ -#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) -#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) -#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name USBCLKSEL - USB clock source select */ -/*! @{ */ -#define SYSCON_USBCLKSEL_SEL_MASK (0x7U) -#define SYSCON_USBCLKSEL_SEL_SHIFT (0U) -#define SYSCON_USBCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSEL_SEL_SHIFT)) & SYSCON_USBCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name FXCOMCLKSEL - Flexcomm 0 clock source select */ -/*! @{ */ -#define SYSCON_FXCOMCLKSEL_SEL_MASK (0x7U) -#define SYSCON_FXCOMCLKSEL_SEL_SHIFT (0U) -#define SYSCON_FXCOMCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FXCOMCLKSEL_SEL_SHIFT)) & SYSCON_FXCOMCLKSEL_SEL_MASK) -/*! @} */ - -/* The count of SYSCON_FXCOMCLKSEL */ -#define SYSCON_FXCOMCLKSEL_COUNT (8U) - -/*! @name MCLKCLKSEL - MCLK clock source select */ -/*! @{ */ -#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) -#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) -#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name FRGCLKSEL - Fractional Rate Generator clock source select */ -/*! @{ */ -#define SYSCON_FRGCLKSEL_SEL_MASK (0x7U) -#define SYSCON_FRGCLKSEL_SEL_SHIFT (0U) -#define SYSCON_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name DMICCLKSEL - Digital microphone (D-Mic) subsystem clock select */ -/*! @{ */ -#define SYSCON_DMICCLKSEL_SEL_MASK (0x7U) -#define SYSCON_DMICCLKSEL_SEL_SHIFT (0U) -#define SYSCON_DMICCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKDIV - SYSTICK clock divider */ -/*! @{ */ -#define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U) -#define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK) -#define SYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U) -#define SYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK) -#define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U) -#define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK) -/*! @} */ - -/*! @name TRACECLKDIV - Trace clock divider */ -/*! @{ */ -#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) -#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) -#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) -#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) -#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) -#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) -#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) -/*! @} */ - -/*! @name AHBCLKDIV - AHB clock divider */ -/*! @{ */ -#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) -#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) -#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) -#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) -#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) -#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) -/*! @} */ - -/*! @name CLKOUTDIV - CLKOUT clock divider */ -/*! @{ */ -#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) -#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) -#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) -#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) -#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) -#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) -#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) -#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) -#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) -/*! @} */ - -/*! @name SPIFICLKDIV - SPIFI clock divider */ -/*! @{ */ -#define SYSCON_SPIFICLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SPIFICLKDIV_DIV_SHIFT (0U) -#define SYSCON_SPIFICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK) -#define SYSCON_SPIFICLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SPIFICLKDIV_RESET_SHIFT (29U) -#define SYSCON_SPIFICLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_RESET_SHIFT)) & SYSCON_SPIFICLKDIV_RESET_MASK) -#define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SPIFICLKDIV_HALT_SHIFT (30U) -#define SYSCON_SPIFICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK) -/*! @} */ - -/*! @name ADCCLKDIV - ADC clock divider */ -/*! @{ */ -#define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) -#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) -#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) -#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) -#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) -#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) -/*! @} */ - -/*! @name USBCLKDIV - USB clock divider */ -/*! @{ */ -#define SYSCON_USBCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_USBCLKDIV_DIV_SHIFT (0U) -#define SYSCON_USBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_DIV_SHIFT)) & SYSCON_USBCLKDIV_DIV_MASK) -#define SYSCON_USBCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_USBCLKDIV_RESET_SHIFT (29U) -#define SYSCON_USBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_RESET_SHIFT)) & SYSCON_USBCLKDIV_RESET_MASK) -#define SYSCON_USBCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_USBCLKDIV_HALT_SHIFT (30U) -#define SYSCON_USBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_HALT_SHIFT)) & SYSCON_USBCLKDIV_HALT_MASK) -/*! @} */ - -/*! @name FRGCTRL - Fractional rate divider */ -/*! @{ */ -#define SYSCON_FRGCTRL_DIV_MASK (0xFFU) -#define SYSCON_FRGCTRL_DIV_SHIFT (0U) -#define SYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK) -#define SYSCON_FRGCTRL_MULT_MASK (0xFF00U) -#define SYSCON_FRGCTRL_MULT_SHIFT (8U) -#define SYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK) -/*! @} */ - -/*! @name DMICCLKDIV - DMIC clock divider */ -/*! @{ */ -#define SYSCON_DMICCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_DMICCLKDIV_DIV_SHIFT (0U) -#define SYSCON_DMICCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK) -#define SYSCON_DMICCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_DMICCLKDIV_RESET_SHIFT (29U) -#define SYSCON_DMICCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_RESET_SHIFT)) & SYSCON_DMICCLKDIV_RESET_MASK) -#define SYSCON_DMICCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_DMICCLKDIV_HALT_SHIFT (30U) -#define SYSCON_DMICCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK) -/*! @} */ - -/*! @name MCLKDIV - I2S MCLK clock divider */ -/*! @{ */ -#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_MCLKDIV_DIV_SHIFT (0U) -#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) -#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_MCLKDIV_RESET_SHIFT (29U) -#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) -#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_MCLKDIV_HALT_SHIFT (30U) -#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) -/*! @} */ - -/*! @name FLASHCFG - Flash wait states configuration */ -/*! @{ */ -#define SYSCON_FLASHCFG_FETCHCFG_MASK (0x3U) -#define SYSCON_FLASHCFG_FETCHCFG_SHIFT (0U) -#define SYSCON_FLASHCFG_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FETCHCFG_SHIFT)) & SYSCON_FLASHCFG_FETCHCFG_MASK) -#define SYSCON_FLASHCFG_DATACFG_MASK (0xCU) -#define SYSCON_FLASHCFG_DATACFG_SHIFT (2U) -#define SYSCON_FLASHCFG_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_DATACFG_SHIFT)) & SYSCON_FLASHCFG_DATACFG_MASK) -#define SYSCON_FLASHCFG_ACCEL_MASK (0x10U) -#define SYSCON_FLASHCFG_ACCEL_SHIFT (4U) -#define SYSCON_FLASHCFG_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_ACCEL_SHIFT)) & SYSCON_FLASHCFG_ACCEL_MASK) -#define SYSCON_FLASHCFG_PREFEN_MASK (0x20U) -#define SYSCON_FLASHCFG_PREFEN_SHIFT (5U) -#define SYSCON_FLASHCFG_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFEN_SHIFT)) & SYSCON_FLASHCFG_PREFEN_MASK) -#define SYSCON_FLASHCFG_PREFOVR_MASK (0x40U) -#define SYSCON_FLASHCFG_PREFOVR_SHIFT (6U) -#define SYSCON_FLASHCFG_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFOVR_SHIFT)) & SYSCON_FLASHCFG_PREFOVR_MASK) -#define SYSCON_FLASHCFG_FLASHTIM_MASK (0xF000U) -#define SYSCON_FLASHCFG_FLASHTIM_SHIFT (12U) -#define SYSCON_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FLASHTIM_SHIFT)) & SYSCON_FLASHCFG_FLASHTIM_MASK) -/*! @} */ - -/*! @name USBCLKCTRL - USB clock control */ -/*! @{ */ -#define SYSCON_USBCLKCTRL_POL_CLK_MASK (0x2U) -#define SYSCON_USBCLKCTRL_POL_CLK_SHIFT (1U) -#define SYSCON_USBCLKCTRL_POL_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKCTRL_POL_CLK_SHIFT)) & SYSCON_USBCLKCTRL_POL_CLK_MASK) -/*! @} */ - -/*! @name USBCLKSTAT - USB clock status */ -/*! @{ */ -#define SYSCON_USBCLKSTAT_NEED_CLKST_MASK (0x1U) -#define SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT (0U) -#define SYSCON_USBCLKSTAT_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT)) & SYSCON_USBCLKSTAT_NEED_CLKST_MASK) -/*! @} */ - -/*! @name FREQMECTRL - Frequency measure register */ -/*! @{ */ -#define SYSCON_FREQMECTRL_CAPVAL_MASK (0x3FFFU) -#define SYSCON_FREQMECTRL_CAPVAL_SHIFT (0U) -#define SYSCON_FREQMECTRL_CAPVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK) -#define SYSCON_FREQMECTRL_PROG_MASK (0x80000000U) -#define SYSCON_FREQMECTRL_PROG_SHIFT (31U) -#define SYSCON_FREQMECTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK) -/*! @} */ - -/*! @name MCLKIO - MCLK input/output control */ -/*! @{ */ -#define SYSCON_MCLKIO_DIR_MASK (0x1U) -#define SYSCON_MCLKIO_DIR_SHIFT (0U) -#define SYSCON_MCLKIO_DIR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK) -/*! @} */ - -/*! @name FROCTRL - FRO oscillator control */ -/*! @{ */ -#define SYSCON_FROCTRL_TRIM_MASK (0x3FFFU) -#define SYSCON_FROCTRL_TRIM_SHIFT (0U) -#define SYSCON_FROCTRL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_TRIM_SHIFT)) & SYSCON_FROCTRL_TRIM_MASK) -#define SYSCON_FROCTRL_SEL_MASK (0x4000U) -#define SYSCON_FROCTRL_SEL_SHIFT (14U) -#define SYSCON_FROCTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK) -#define SYSCON_FROCTRL_FREQTRIM_MASK (0xFF0000U) -#define SYSCON_FROCTRL_FREQTRIM_SHIFT (16U) -#define SYSCON_FROCTRL_FREQTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK) -#define SYSCON_FROCTRL_USBCLKADJ_MASK (0x1000000U) -#define SYSCON_FROCTRL_USBCLKADJ_SHIFT (24U) -#define SYSCON_FROCTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK) -#define SYSCON_FROCTRL_USBMODCHG_MASK (0x2000000U) -#define SYSCON_FROCTRL_USBMODCHG_SHIFT (25U) -#define SYSCON_FROCTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK) -#define SYSCON_FROCTRL_HSPDCLK_MASK (0x40000000U) -#define SYSCON_FROCTRL_HSPDCLK_SHIFT (30U) -#define SYSCON_FROCTRL_HSPDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK) -#define SYSCON_FROCTRL_WRTRIM_MASK (0x80000000U) -#define SYSCON_FROCTRL_WRTRIM_SHIFT (31U) -#define SYSCON_FROCTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_WRTRIM_SHIFT)) & SYSCON_FROCTRL_WRTRIM_MASK) -/*! @} */ - -/*! @name WDTOSCCTRL - Watchdog oscillator control */ -/*! @{ */ -#define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU) -#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U) -#define SYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK) -#define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x3E0U) -#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U) -#define SYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK) -/*! @} */ - -/*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */ -/*! @{ */ -#define SYSCON_RTCOSCCTRL_EN_MASK (0x1U) -#define SYSCON_RTCOSCCTRL_EN_SHIFT (0U) -#define SYSCON_RTCOSCCTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK) -/*! @} */ - -/*! @name SYSPLLCTRL - PLL control */ -/*! @{ */ -#define SYSCON_SYSPLLCTRL_SELR_MASK (0xFU) -#define SYSCON_SYSPLLCTRL_SELR_SHIFT (0U) -#define SYSCON_SYSPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK) -#define SYSCON_SYSPLLCTRL_SELI_MASK (0x3F0U) -#define SYSCON_SYSPLLCTRL_SELI_SHIFT (4U) -#define SYSCON_SYSPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK) -#define SYSCON_SYSPLLCTRL_SELP_MASK (0x7C00U) -#define SYSCON_SYSPLLCTRL_SELP_SHIFT (10U) -#define SYSCON_SYSPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK) -#define SYSCON_SYSPLLCTRL_BYPASS_MASK (0x8000U) -#define SYSCON_SYSPLLCTRL_BYPASS_SHIFT (15U) -#define SYSCON_SYSPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK) -#define SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK (0x10000U) -#define SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT (16U) -#define SYSCON_SYSPLLCTRL_BYPASSCCODIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK) -#define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK (0x20000U) -#define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT (17U) -#define SYSCON_SYSPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK) -#define SYSCON_SYSPLLCTRL_BANDSEL_MASK (0x40000U) -#define SYSCON_SYSPLLCTRL_BANDSEL_SHIFT (18U) -#define SYSCON_SYSPLLCTRL_BANDSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BANDSEL_SHIFT)) & SYSCON_SYSPLLCTRL_BANDSEL_MASK) -#define SYSCON_SYSPLLCTRL_DIRECTI_MASK (0x80000U) -#define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT (19U) -#define SYSCON_SYSPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK) -#define SYSCON_SYSPLLCTRL_DIRECTO_MASK (0x100000U) -#define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT (20U) -#define SYSCON_SYSPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK) -/*! @} */ - -/*! @name SYSPLLSTAT - PLL status */ -/*! @{ */ -#define SYSCON_SYSPLLSTAT_LOCK_MASK (0x1U) -#define SYSCON_SYSPLLSTAT_LOCK_SHIFT (0U) -#define SYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK) -/*! @} */ - -/*! @name SYSPLLNDEC - PLL N decoder */ -/*! @{ */ -#define SYSCON_SYSPLLNDEC_NDEC_MASK (0x3FFU) -#define SYSCON_SYSPLLNDEC_NDEC_SHIFT (0U) -#define SYSCON_SYSPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK) -#define SYSCON_SYSPLLNDEC_NREQ_MASK (0x400U) -#define SYSCON_SYSPLLNDEC_NREQ_SHIFT (10U) -#define SYSCON_SYSPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK) -/*! @} */ - -/*! @name SYSPLLPDEC - PLL P decoder */ -/*! @{ */ -#define SYSCON_SYSPLLPDEC_PDEC_MASK (0x7FU) -#define SYSCON_SYSPLLPDEC_PDEC_SHIFT (0U) -#define SYSCON_SYSPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK) -#define SYSCON_SYSPLLPDEC_PREQ_MASK (0x80U) -#define SYSCON_SYSPLLPDEC_PREQ_SHIFT (7U) -#define SYSCON_SYSPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK) -/*! @} */ - -/*! @name SYSPLLSSCTRL0 - PLL spread spectrum control 0 */ -/*! @{ */ -#define SYSCON_SYSPLLSSCTRL0_MDEC_MASK (0x1FFFFU) -#define SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT (0U) -#define SYSCON_SYSPLLSSCTRL0_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MDEC_MASK) -#define SYSCON_SYSPLLSSCTRL0_MREQ_MASK (0x20000U) -#define SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT (17U) -#define SYSCON_SYSPLLSSCTRL0_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MREQ_MASK) -#define SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK (0x40000U) -#define SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT (18U) -#define SYSCON_SYSPLLSSCTRL0_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT)) & SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK) -/*! @} */ - -/*! @name SYSPLLSSCTRL1 - PLL spread spectrum control 1 */ -/*! @{ */ -#define SYSCON_SYSPLLSSCTRL1_MD_MASK (0x7FFFFU) -#define SYSCON_SYSPLLSSCTRL1_MD_SHIFT (0U) -#define SYSCON_SYSPLLSSCTRL1_MD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MD_MASK) -#define SYSCON_SYSPLLSSCTRL1_MDREQ_MASK (0x80000U) -#define SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT (19U) -#define SYSCON_SYSPLLSSCTRL1_MDREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MDREQ_MASK) -#define SYSCON_SYSPLLSSCTRL1_MF_MASK (0x700000U) -#define SYSCON_SYSPLLSSCTRL1_MF_SHIFT (20U) -#define SYSCON_SYSPLLSSCTRL1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MF_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MF_MASK) -#define SYSCON_SYSPLLSSCTRL1_MR_MASK (0x3800000U) -#define SYSCON_SYSPLLSSCTRL1_MR_SHIFT (23U) -#define SYSCON_SYSPLLSSCTRL1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MR_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MR_MASK) -#define SYSCON_SYSPLLSSCTRL1_MC_MASK (0xC000000U) -#define SYSCON_SYSPLLSSCTRL1_MC_SHIFT (26U) -#define SYSCON_SYSPLLSSCTRL1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MC_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MC_MASK) -#define SYSCON_SYSPLLSSCTRL1_PD_MASK (0x10000000U) -#define SYSCON_SYSPLLSSCTRL1_PD_SHIFT (28U) -#define SYSCON_SYSPLLSSCTRL1_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_PD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_PD_MASK) -#define SYSCON_SYSPLLSSCTRL1_DITHER_MASK (0x20000000U) -#define SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT (29U) -#define SYSCON_SYSPLLSSCTRL1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT)) & SYSCON_SYSPLLSSCTRL1_DITHER_MASK) -/*! @} */ - -/*! @name PDSLEEPCFG - Sleep configuration register n */ -/*! @{ */ -#define SYSCON_PDSLEEPCFG_PD_SLEEP_MASK (0xFFFFFFFFU) -#define SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT (0U) -#define SYSCON_PDSLEEPCFG_PD_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT)) & SYSCON_PDSLEEPCFG_PD_SLEEP_MASK) -/*! @} */ - -/* The count of SYSCON_PDSLEEPCFG */ -#define SYSCON_PDSLEEPCFG_COUNT (2U) - -/*! @name PDRUNCFG - Power configuration register n */ -/*! @{ */ -#define SYSCON_PDRUNCFG_PDEN_FRO_MASK (0x10U) -#define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT (4U) -#define SYSCON_PDRUNCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK) -#define SYSCON_PDRUNCFG_PD_FLASH_MASK (0x20U) -#define SYSCON_PDRUNCFG_PD_FLASH_SHIFT (5U) -#define SYSCON_PDRUNCFG_PD_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_FLASH_SHIFT)) & SYSCON_PDRUNCFG_PD_FLASH_MASK) -#define SYSCON_PDRUNCFG_PDEN_TS_MASK (0x40U) -#define SYSCON_PDRUNCFG_PDEN_TS_SHIFT (6U) -#define SYSCON_PDRUNCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK) -#define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK (0x80U) -#define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT (7U) -#define SYSCON_PDRUNCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK) -#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK (0x100U) -#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT (8U) -#define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK) -#define SYSCON_PDRUNCFG_PDEN_ADC0_MASK (0x400U) -#define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT (10U) -#define SYSCON_PDRUNCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK) -#define SYSCON_PDRUNCFG_PD_VDDFLASH_MASK (0x800U) -#define SYSCON_PDRUNCFG_PD_VDDFLASH_SHIFT (11U) -#define SYSCON_PDRUNCFG_PD_VDDFLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_VDDFLASH_SHIFT)) & SYSCON_PDRUNCFG_PD_VDDFLASH_MASK) -#define SYSCON_PDRUNCFG_LP_VDDFLASH_MASK (0x1000U) -#define SYSCON_PDRUNCFG_LP_VDDFLASH_SHIFT (12U) -#define SYSCON_PDRUNCFG_LP_VDDFLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_LP_VDDFLASH_SHIFT)) & SYSCON_PDRUNCFG_LP_VDDFLASH_MASK) -#define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK (0x2000U) -#define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT (13U) -#define SYSCON_PDRUNCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK) -#define SYSCON_PDRUNCFG_PDEN_SRAM1_MASK (0x4000U) -#define SYSCON_PDRUNCFG_PDEN_SRAM1_SHIFT (14U) -#define SYSCON_PDRUNCFG_PDEN_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM1_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM1_MASK) -#define SYSCON_PDRUNCFG_PDEN_SRAM2_MASK (0x8000U) -#define SYSCON_PDRUNCFG_PDEN_SRAM2_SHIFT (15U) -#define SYSCON_PDRUNCFG_PDEN_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM2_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM2_MASK) -#define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK (0x10000U) -#define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT (16U) -#define SYSCON_PDRUNCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK) -#define SYSCON_PDRUNCFG_PDEN_ROM_MASK (0x20000U) -#define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT (17U) -#define SYSCON_PDRUNCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK) -#define SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK (0x40000U) -#define SYSCON_PDRUNCFG_PD_VDDHV_ENA_SHIFT (18U) -#define SYSCON_PDRUNCFG_PD_VDDHV_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_VDDHV_ENA_SHIFT)) & SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK) -#define SYSCON_PDRUNCFG_PDEN_VDDA_MASK (0x80000U) -#define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT (19U) -#define SYSCON_PDRUNCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK) -#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK (0x100000U) -#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT (20U) -#define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) -#define SYSCON_PDRUNCFG_PDEN_USB_PHY_MASK (0x200000U) -#define SYSCON_PDRUNCFG_PDEN_USB_PHY_SHIFT (21U) -#define SYSCON_PDRUNCFG_PDEN_USB_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_PHY_MASK) -#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK (0x400000U) -#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT (22U) -#define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK) -#define SYSCON_PDRUNCFG_PDEN_VREFP_MASK (0x800000U) -#define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT (23U) -#define SYSCON_PDRUNCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK) -#define SYSCON_PDRUNCFG_PD_FLASH_BG_MASK (0x2000000U) -#define SYSCON_PDRUNCFG_PD_FLASH_BG_SHIFT (25U) -#define SYSCON_PDRUNCFG_PD_FLASH_BG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_FLASH_BG_SHIFT)) & SYSCON_PDRUNCFG_PD_FLASH_BG_MASK) -#define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_MASK (0x10000000U) -#define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_SHIFT (28U) -#define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_SHIFT)) & SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_MASK) -#define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_MASK (0x20000000U) -#define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_SHIFT (29U) -#define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_SHIFT)) & SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_MASK) -/*! @} */ - -/* The count of SYSCON_PDRUNCFG */ -#define SYSCON_PDRUNCFG_COUNT (2U) - -/*! @name PDRUNCFGSET - Set bits in PDRUNCFGn */ -/*! @{ */ -#define SYSCON_PDRUNCFGSET_PD_SET_MASK (0xFFFFFFFFU) -#define SYSCON_PDRUNCFGSET_PD_SET_SHIFT (0U) -#define SYSCON_PDRUNCFGSET_PD_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PD_SET_SHIFT)) & SYSCON_PDRUNCFGSET_PD_SET_MASK) -/*! @} */ - -/* The count of SYSCON_PDRUNCFGSET */ -#define SYSCON_PDRUNCFGSET_COUNT (2U) - -/*! @name PDRUNCFGCLR - Clear bits in PDRUNCFGn */ -/*! @{ */ -#define SYSCON_PDRUNCFGCLR_PD_CLR_MASK (0xFFFFFFFFU) -#define SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT (0U) -#define SYSCON_PDRUNCFGCLR_PD_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT)) & SYSCON_PDRUNCFGCLR_PD_CLR_MASK) -/*! @} */ - -/* The count of SYSCON_PDRUNCFGCLR */ -#define SYSCON_PDRUNCFGCLR_COUNT (2U) - -/*! @name STARTERP - Start logic n wake-up enable register */ -/*! @{ */ -#define SYSCON_STARTERP_PINT4_MASK (0x1U) -#define SYSCON_STARTERP_PINT4_SHIFT (0U) -#define SYSCON_STARTERP_PINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT4_SHIFT)) & SYSCON_STARTERP_PINT4_MASK) -#define SYSCON_STARTERP_WDT_BOD_MASK (0x1U) -#define SYSCON_STARTERP_WDT_BOD_SHIFT (0U) -#define SYSCON_STARTERP_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_WDT_BOD_SHIFT)) & SYSCON_STARTERP_WDT_BOD_MASK) -#define SYSCON_STARTERP_DMA0_MASK (0x2U) -#define SYSCON_STARTERP_DMA0_SHIFT (1U) -#define SYSCON_STARTERP_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_DMA0_SHIFT)) & SYSCON_STARTERP_DMA0_MASK) -#define SYSCON_STARTERP_PINT5_MASK (0x2U) -#define SYSCON_STARTERP_PINT5_SHIFT (1U) -#define SYSCON_STARTERP_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT5_SHIFT)) & SYSCON_STARTERP_PINT5_MASK) -#define SYSCON_STARTERP_GINT0_MASK (0x4U) -#define SYSCON_STARTERP_GINT0_SHIFT (2U) -#define SYSCON_STARTERP_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_GINT0_SHIFT)) & SYSCON_STARTERP_GINT0_MASK) -#define SYSCON_STARTERP_PINT6_MASK (0x4U) -#define SYSCON_STARTERP_PINT6_SHIFT (2U) -#define SYSCON_STARTERP_PINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT6_SHIFT)) & SYSCON_STARTERP_PINT6_MASK) -#define SYSCON_STARTERP_GINT1_MASK (0x8U) -#define SYSCON_STARTERP_GINT1_SHIFT (3U) -#define SYSCON_STARTERP_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_GINT1_SHIFT)) & SYSCON_STARTERP_GINT1_MASK) -#define SYSCON_STARTERP_PINT7_MASK (0x8U) -#define SYSCON_STARTERP_PINT7_SHIFT (3U) -#define SYSCON_STARTERP_PINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT7_SHIFT)) & SYSCON_STARTERP_PINT7_MASK) -#define SYSCON_STARTERP_CTIMER2_MASK (0x10U) -#define SYSCON_STARTERP_CTIMER2_SHIFT (4U) -#define SYSCON_STARTERP_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER2_SHIFT)) & SYSCON_STARTERP_CTIMER2_MASK) -#define SYSCON_STARTERP_PIN_INT0_MASK (0x10U) -#define SYSCON_STARTERP_PIN_INT0_SHIFT (4U) -#define SYSCON_STARTERP_PIN_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT0_SHIFT)) & SYSCON_STARTERP_PIN_INT0_MASK) -#define SYSCON_STARTERP_CTIMER4_MASK (0x20U) -#define SYSCON_STARTERP_CTIMER4_SHIFT (5U) -#define SYSCON_STARTERP_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER4_SHIFT)) & SYSCON_STARTERP_CTIMER4_MASK) -#define SYSCON_STARTERP_PIN_INT1_MASK (0x20U) -#define SYSCON_STARTERP_PIN_INT1_SHIFT (5U) -#define SYSCON_STARTERP_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT1_SHIFT)) & SYSCON_STARTERP_PIN_INT1_MASK) -#define SYSCON_STARTERP_PIN_INT2_MASK (0x40U) -#define SYSCON_STARTERP_PIN_INT2_SHIFT (6U) -#define SYSCON_STARTERP_PIN_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT2_SHIFT)) & SYSCON_STARTERP_PIN_INT2_MASK) -#define SYSCON_STARTERP_PIN_INT3_MASK (0x80U) -#define SYSCON_STARTERP_PIN_INT3_SHIFT (7U) -#define SYSCON_STARTERP_PIN_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT3_SHIFT)) & SYSCON_STARTERP_PIN_INT3_MASK) -#define SYSCON_STARTERP_UTICK0_MASK (0x100U) -#define SYSCON_STARTERP_UTICK0_SHIFT (8U) -#define SYSCON_STARTERP_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_UTICK0_SHIFT)) & SYSCON_STARTERP_UTICK0_MASK) -#define SYSCON_STARTERP_MRT0_MASK (0x200U) -#define SYSCON_STARTERP_MRT0_SHIFT (9U) -#define SYSCON_STARTERP_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_MRT0_SHIFT)) & SYSCON_STARTERP_MRT0_MASK) -#define SYSCON_STARTERP_CTIMER0_MASK (0x400U) -#define SYSCON_STARTERP_CTIMER0_SHIFT (10U) -#define SYSCON_STARTERP_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER0_SHIFT)) & SYSCON_STARTERP_CTIMER0_MASK) -#define SYSCON_STARTERP_CTIMER1_MASK (0x800U) -#define SYSCON_STARTERP_CTIMER1_SHIFT (11U) -#define SYSCON_STARTERP_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER1_SHIFT)) & SYSCON_STARTERP_CTIMER1_MASK) -#define SYSCON_STARTERP_SCT0_MASK (0x1000U) -#define SYSCON_STARTERP_SCT0_SHIFT (12U) -#define SYSCON_STARTERP_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_SCT0_SHIFT)) & SYSCON_STARTERP_SCT0_MASK) -#define SYSCON_STARTERP_CTIMER3_MASK (0x2000U) -#define SYSCON_STARTERP_CTIMER3_SHIFT (13U) -#define SYSCON_STARTERP_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER3_SHIFT)) & SYSCON_STARTERP_CTIMER3_MASK) -#define SYSCON_STARTERP_FLEXCOMM0_MASK (0x4000U) -#define SYSCON_STARTERP_FLEXCOMM0_SHIFT (14U) -#define SYSCON_STARTERP_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM0_SHIFT)) & SYSCON_STARTERP_FLEXCOMM0_MASK) -#define SYSCON_STARTERP_FLEXCOMM1_MASK (0x8000U) -#define SYSCON_STARTERP_FLEXCOMM1_SHIFT (15U) -#define SYSCON_STARTERP_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM1_SHIFT)) & SYSCON_STARTERP_FLEXCOMM1_MASK) -#define SYSCON_STARTERP_FLEXCOMM2_MASK (0x10000U) -#define SYSCON_STARTERP_FLEXCOMM2_SHIFT (16U) -#define SYSCON_STARTERP_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM2_SHIFT)) & SYSCON_STARTERP_FLEXCOMM2_MASK) -#define SYSCON_STARTERP_FLEXCOMM3_MASK (0x20000U) -#define SYSCON_STARTERP_FLEXCOMM3_SHIFT (17U) -#define SYSCON_STARTERP_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM3_SHIFT)) & SYSCON_STARTERP_FLEXCOMM3_MASK) -#define SYSCON_STARTERP_FLEXCOMM4_MASK (0x40000U) -#define SYSCON_STARTERP_FLEXCOMM4_SHIFT (18U) -#define SYSCON_STARTERP_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM4_SHIFT)) & SYSCON_STARTERP_FLEXCOMM4_MASK) -#define SYSCON_STARTERP_FLEXCOMM5_MASK (0x80000U) -#define SYSCON_STARTERP_FLEXCOMM5_SHIFT (19U) -#define SYSCON_STARTERP_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM5_SHIFT)) & SYSCON_STARTERP_FLEXCOMM5_MASK) -#define SYSCON_STARTERP_FLEXCOMM6_MASK (0x100000U) -#define SYSCON_STARTERP_FLEXCOMM6_SHIFT (20U) -#define SYSCON_STARTERP_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM6_SHIFT)) & SYSCON_STARTERP_FLEXCOMM6_MASK) -#define SYSCON_STARTERP_FLEXCOMM7_MASK (0x200000U) -#define SYSCON_STARTERP_FLEXCOMM7_SHIFT (21U) -#define SYSCON_STARTERP_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM7_SHIFT)) & SYSCON_STARTERP_FLEXCOMM7_MASK) -#define SYSCON_STARTERP_ADC0_SEQA_MASK (0x400000U) -#define SYSCON_STARTERP_ADC0_SEQA_SHIFT (22U) -#define SYSCON_STARTERP_ADC0_SEQA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_SEQA_SHIFT)) & SYSCON_STARTERP_ADC0_SEQA_MASK) -#define SYSCON_STARTERP_ADC0_SEQB_MASK (0x800000U) -#define SYSCON_STARTERP_ADC0_SEQB_SHIFT (23U) -#define SYSCON_STARTERP_ADC0_SEQB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_SEQB_SHIFT)) & SYSCON_STARTERP_ADC0_SEQB_MASK) -#define SYSCON_STARTERP_ADC0_THCMP_MASK (0x1000000U) -#define SYSCON_STARTERP_ADC0_THCMP_SHIFT (24U) -#define SYSCON_STARTERP_ADC0_THCMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_THCMP_SHIFT)) & SYSCON_STARTERP_ADC0_THCMP_MASK) -#define SYSCON_STARTERP_DMIC0_MASK (0x2000000U) -#define SYSCON_STARTERP_DMIC0_SHIFT (25U) -#define SYSCON_STARTERP_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_DMIC0_SHIFT)) & SYSCON_STARTERP_DMIC0_MASK) -#define SYSCON_STARTERP_USB0_NEEDCLK_MASK (0x8000000U) -#define SYSCON_STARTERP_USB0_NEEDCLK_SHIFT (27U) -#define SYSCON_STARTERP_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTERP_USB0_NEEDCLK_MASK) -#define SYSCON_STARTERP_USB0_MASK (0x10000000U) -#define SYSCON_STARTERP_USB0_SHIFT (28U) -#define SYSCON_STARTERP_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_USB0_SHIFT)) & SYSCON_STARTERP_USB0_MASK) -#define SYSCON_STARTERP_RTC_MASK (0x20000000U) -#define SYSCON_STARTERP_RTC_SHIFT (29U) -#define SYSCON_STARTERP_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_RTC_SHIFT)) & SYSCON_STARTERP_RTC_MASK) -#define SYSCON_STARTERP_MAILBOX_MASK (0x80000000U) -#define SYSCON_STARTERP_MAILBOX_SHIFT (31U) -#define SYSCON_STARTERP_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_MAILBOX_SHIFT)) & SYSCON_STARTERP_MAILBOX_MASK) -/*! @} */ - -/* The count of SYSCON_STARTERP */ -#define SYSCON_STARTERP_COUNT (2U) - -/*! @name STARTERSET - Set bits in STARTERn */ -/*! @{ */ -#define SYSCON_STARTERSET_START_SET_MASK (0xFFFFFFFFU) -#define SYSCON_STARTERSET_START_SET_SHIFT (0U) -#define SYSCON_STARTERSET_START_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK) -/*! @} */ - -/* The count of SYSCON_STARTERSET */ -#define SYSCON_STARTERSET_COUNT (2U) - -/*! @name STARTERCLR - Clear bits in STARTERn */ -/*! @{ */ -#define SYSCON_STARTERCLR_START_CLR_MASK (0xFFFFFFFFU) -#define SYSCON_STARTERCLR_START_CLR_SHIFT (0U) -#define SYSCON_STARTERCLR_START_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK) -/*! @} */ - -/* The count of SYSCON_STARTERCLR */ -#define SYSCON_STARTERCLR_COUNT (2U) - -/*! @name HWWAKE - Configures special cases of hardware wake-up */ -/*! @{ */ -#define SYSCON_HWWAKE_FORCEWAKE_MASK (0x1U) -#define SYSCON_HWWAKE_FORCEWAKE_SHIFT (0U) -#define SYSCON_HWWAKE_FORCEWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK) -#define SYSCON_HWWAKE_FCWAKE_MASK (0x2U) -#define SYSCON_HWWAKE_FCWAKE_SHIFT (1U) -#define SYSCON_HWWAKE_FCWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK) -#define SYSCON_HWWAKE_WAKEDMIC_MASK (0x4U) -#define SYSCON_HWWAKE_WAKEDMIC_SHIFT (2U) -#define SYSCON_HWWAKE_WAKEDMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMIC_SHIFT)) & SYSCON_HWWAKE_WAKEDMIC_MASK) -#define SYSCON_HWWAKE_WAKEDMA_MASK (0x8U) -#define SYSCON_HWWAKE_WAKEDMA_SHIFT (3U) -#define SYSCON_HWWAKE_WAKEDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK) -/*! @} */ - -/*! @name CPUCTRL - CPU Control for multiple processors */ -/*! @{ */ -#define SYSCON_CPUCTRL_MASTERCPU_MASK (0x1U) -#define SYSCON_CPUCTRL_MASTERCPU_SHIFT (0U) -#define SYSCON_CPUCTRL_MASTERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_MASTERCPU_SHIFT)) & SYSCON_CPUCTRL_MASTERCPU_MASK) -#define SYSCON_CPUCTRL_CM4CLKEN_MASK (0x4U) -#define SYSCON_CPUCTRL_CM4CLKEN_SHIFT (2U) -#define SYSCON_CPUCTRL_CM4CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM4CLKEN_SHIFT)) & SYSCON_CPUCTRL_CM4CLKEN_MASK) -#define SYSCON_CPUCTRL_CM0CLKEN_MASK (0x8U) -#define SYSCON_CPUCTRL_CM0CLKEN_SHIFT (3U) -#define SYSCON_CPUCTRL_CM0CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM0CLKEN_SHIFT)) & SYSCON_CPUCTRL_CM0CLKEN_MASK) -#define SYSCON_CPUCTRL_CM4RSTEN_MASK (0x10U) -#define SYSCON_CPUCTRL_CM4RSTEN_SHIFT (4U) -#define SYSCON_CPUCTRL_CM4RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM4RSTEN_SHIFT)) & SYSCON_CPUCTRL_CM4RSTEN_MASK) -#define SYSCON_CPUCTRL_CM0RSTEN_MASK (0x20U) -#define SYSCON_CPUCTRL_CM0RSTEN_SHIFT (5U) -#define SYSCON_CPUCTRL_CM0RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM0RSTEN_SHIFT)) & SYSCON_CPUCTRL_CM0RSTEN_MASK) -#define SYSCON_CPUCTRL_POWERCPU_MASK (0x40U) -#define SYSCON_CPUCTRL_POWERCPU_SHIFT (6U) -#define SYSCON_CPUCTRL_POWERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_POWERCPU_SHIFT)) & SYSCON_CPUCTRL_POWERCPU_MASK) -/*! @} */ - -/*! @name CPBOOT - Coprocessor Boot Address */ -/*! @{ */ -#define SYSCON_CPBOOT_BOOTADDR_MASK (0xFFFFFFFFU) -#define SYSCON_CPBOOT_BOOTADDR_SHIFT (0U) -#define SYSCON_CPBOOT_BOOTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_BOOTADDR_SHIFT)) & SYSCON_CPBOOT_BOOTADDR_MASK) -/*! @} */ - -/*! @name CPSTACK - Coprocessor Stack Address */ -/*! @{ */ -#define SYSCON_CPSTACK_STACKADDR_MASK (0xFFFFFFFFU) -#define SYSCON_CPSTACK_STACKADDR_SHIFT (0U) -#define SYSCON_CPSTACK_STACKADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTACK_STACKADDR_SHIFT)) & SYSCON_CPSTACK_STACKADDR_MASK) -/*! @} */ - -/*! @name CPSTAT - Coprocessor Status */ -/*! @{ */ -#define SYSCON_CPSTAT_CM4SLEEPING_MASK (0x1U) -#define SYSCON_CPSTAT_CM4SLEEPING_SHIFT (0U) -#define SYSCON_CPSTAT_CM4SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM4SLEEPING_SHIFT)) & SYSCON_CPSTAT_CM4SLEEPING_MASK) -#define SYSCON_CPSTAT_CM0SLEEPING_MASK (0x2U) -#define SYSCON_CPSTAT_CM0SLEEPING_SHIFT (1U) -#define SYSCON_CPSTAT_CM0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CM0SLEEPING_MASK) -#define SYSCON_CPSTAT_CM4LOCKUP_MASK (0x4U) -#define SYSCON_CPSTAT_CM4LOCKUP_SHIFT (2U) -#define SYSCON_CPSTAT_CM4LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM4LOCKUP_SHIFT)) & SYSCON_CPSTAT_CM4LOCKUP_MASK) -#define SYSCON_CPSTAT_CM0LOCKUP_MASK (0x8U) -#define SYSCON_CPSTAT_CM0LOCKUP_SHIFT (3U) -#define SYSCON_CPSTAT_CM0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CM0LOCKUP_MASK) -/*! @} */ - -/*! @name AUTOCGOR - Auto Clock-Gate Override Register */ -/*! @{ */ -#define SYSCON_AUTOCGOR_RAM0X_MASK (0x2U) -#define SYSCON_AUTOCGOR_RAM0X_SHIFT (1U) -#define SYSCON_AUTOCGOR_RAM0X(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK) -#define SYSCON_AUTOCGOR_RAM1_MASK (0x4U) -#define SYSCON_AUTOCGOR_RAM1_SHIFT (2U) -#define SYSCON_AUTOCGOR_RAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM1_SHIFT)) & SYSCON_AUTOCGOR_RAM1_MASK) -#define SYSCON_AUTOCGOR_RAM2_MASK (0x8U) -#define SYSCON_AUTOCGOR_RAM2_SHIFT (3U) -#define SYSCON_AUTOCGOR_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK) -/*! @} */ - -/*! @name JTAGIDCODE - JTAG ID code register */ -/*! @{ */ -#define SYSCON_JTAGIDCODE_JTAGID_MASK (0xFFFFFFFFU) -#define SYSCON_JTAGIDCODE_JTAGID_SHIFT (0U) -#define SYSCON_JTAGIDCODE_JTAGID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK) -/*! @} */ - -/*! @name DEVICE_ID0 - Part ID register */ -/*! @{ */ -#define SYSCON_DEVICE_ID0_PARTID_MASK (0xFFFFFFFFU) -#define SYSCON_DEVICE_ID0_PARTID_SHIFT (0U) -#define SYSCON_DEVICE_ID0_PARTID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK) -/*! @} */ - -/*! @name DEVICE_ID1 - Boot ROM and die revision register */ -/*! @{ */ -#define SYSCON_DEVICE_ID1_REVID_MASK (0xFFFFFFFFU) -#define SYSCON_DEVICE_ID1_REVID_SHIFT (0U) -#define SYSCON_DEVICE_ID1_REVID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK) -/*! @} */ - -/*! @name BODCTRL - Brown-Out Detect control */ -/*! @{ */ -#define SYSCON_BODCTRL_BODRSTLEV_MASK (0x3U) -#define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0U) -#define SYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK) -#define SYSCON_BODCTRL_BODRSTENA_MASK (0x4U) -#define SYSCON_BODCTRL_BODRSTENA_SHIFT (2U) -#define SYSCON_BODCTRL_BODRSTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK) -#define SYSCON_BODCTRL_BODINTLEV_MASK (0x18U) -#define SYSCON_BODCTRL_BODINTLEV_SHIFT (3U) -#define SYSCON_BODCTRL_BODINTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK) -#define SYSCON_BODCTRL_BODINTENA_MASK (0x20U) -#define SYSCON_BODCTRL_BODINTENA_SHIFT (5U) -#define SYSCON_BODCTRL_BODINTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK) -#define SYSCON_BODCTRL_BODRSTSTAT_MASK (0x40U) -#define SYSCON_BODCTRL_BODRSTSTAT_SHIFT (6U) -#define SYSCON_BODCTRL_BODRSTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK) -#define SYSCON_BODCTRL_BODINTSTAT_MASK (0x80U) -#define SYSCON_BODCTRL_BODINTSTAT_SHIFT (7U) -#define SYSCON_BODCTRL_BODINTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SYSCON_Register_Masks */ - - -/* SYSCON - Peripheral instance base addresses */ -/** Peripheral SYSCON base address */ -#define SYSCON_BASE (0x40000000u) -/** Peripheral SYSCON base pointer */ -#define SYSCON ((SYSCON_Type *)SYSCON_BASE) -/** Array initializer of SYSCON peripheral base addresses */ -#define SYSCON_BASE_ADDRS { SYSCON_BASE } -/** Array initializer of SYSCON peripheral base pointers */ -#define SYSCON_BASE_PTRS { SYSCON } - -/*! - * @} - */ /* end of group SYSCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USART Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer - * @{ - */ - -/** USART - Register Layout Typedef */ -typedef struct { - __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ - __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ - __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ - uint8_t RESERVED_0[12]; - __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ - __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ - __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ - __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ - uint8_t RESERVED_1[3536]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_2[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_4[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ -} USART_Type; - -/* ---------------------------------------------------------------------------- - -- USART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Register_Masks USART Register Masks - * @{ - */ - -/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ -/*! @{ */ -#define USART_CFG_ENABLE_MASK (0x1U) -#define USART_CFG_ENABLE_SHIFT (0U) -#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) -#define USART_CFG_DATALEN_MASK (0xCU) -#define USART_CFG_DATALEN_SHIFT (2U) -#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) -#define USART_CFG_PARITYSEL_MASK (0x30U) -#define USART_CFG_PARITYSEL_SHIFT (4U) -#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) -#define USART_CFG_STOPLEN_MASK (0x40U) -#define USART_CFG_STOPLEN_SHIFT (6U) -#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) -#define USART_CFG_MODE32K_MASK (0x80U) -#define USART_CFG_MODE32K_SHIFT (7U) -#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) -#define USART_CFG_LINMODE_MASK (0x100U) -#define USART_CFG_LINMODE_SHIFT (8U) -#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) -#define USART_CFG_CTSEN_MASK (0x200U) -#define USART_CFG_CTSEN_SHIFT (9U) -#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) -#define USART_CFG_SYNCEN_MASK (0x800U) -#define USART_CFG_SYNCEN_SHIFT (11U) -#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) -#define USART_CFG_CLKPOL_MASK (0x1000U) -#define USART_CFG_CLKPOL_SHIFT (12U) -#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) -#define USART_CFG_SYNCMST_MASK (0x4000U) -#define USART_CFG_SYNCMST_SHIFT (14U) -#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) -#define USART_CFG_LOOP_MASK (0x8000U) -#define USART_CFG_LOOP_SHIFT (15U) -#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) -#define USART_CFG_IOMODE_MASK (0x10000U) -#define USART_CFG_IOMODE_SHIFT (16U) -#define USART_CFG_IOMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_IOMODE_SHIFT)) & USART_CFG_IOMODE_MASK) -#define USART_CFG_OETA_MASK (0x40000U) -#define USART_CFG_OETA_SHIFT (18U) -#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) -#define USART_CFG_AUTOADDR_MASK (0x80000U) -#define USART_CFG_AUTOADDR_SHIFT (19U) -#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) -#define USART_CFG_OESEL_MASK (0x100000U) -#define USART_CFG_OESEL_SHIFT (20U) -#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) -#define USART_CFG_OEPOL_MASK (0x200000U) -#define USART_CFG_OEPOL_SHIFT (21U) -#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) -#define USART_CFG_RXPOL_MASK (0x400000U) -#define USART_CFG_RXPOL_SHIFT (22U) -#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) -#define USART_CFG_TXPOL_MASK (0x800000U) -#define USART_CFG_TXPOL_SHIFT (23U) -#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) -/*! @} */ - -/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ -/*! @{ */ -#define USART_CTL_TXBRKEN_MASK (0x2U) -#define USART_CTL_TXBRKEN_SHIFT (1U) -#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) -#define USART_CTL_ADDRDET_MASK (0x4U) -#define USART_CTL_ADDRDET_SHIFT (2U) -#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) -#define USART_CTL_TXDIS_MASK (0x40U) -#define USART_CTL_TXDIS_SHIFT (6U) -#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) -#define USART_CTL_CC_MASK (0x100U) -#define USART_CTL_CC_SHIFT (8U) -#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) -#define USART_CTL_CLRCCONRX_MASK (0x200U) -#define USART_CTL_CLRCCONRX_SHIFT (9U) -#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) -#define USART_CTL_AUTOBAUD_MASK (0x10000U) -#define USART_CTL_AUTOBAUD_SHIFT (16U) -#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) -/*! @} */ - -/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ -/*! @{ */ -#define USART_STAT_RXIDLE_MASK (0x2U) -#define USART_STAT_RXIDLE_SHIFT (1U) -#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) -#define USART_STAT_TXIDLE_MASK (0x8U) -#define USART_STAT_TXIDLE_SHIFT (3U) -#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) -#define USART_STAT_CTS_MASK (0x10U) -#define USART_STAT_CTS_SHIFT (4U) -#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) -#define USART_STAT_DELTACTS_MASK (0x20U) -#define USART_STAT_DELTACTS_SHIFT (5U) -#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) -#define USART_STAT_TXDISSTAT_MASK (0x40U) -#define USART_STAT_TXDISSTAT_SHIFT (6U) -#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) -#define USART_STAT_RXBRK_MASK (0x400U) -#define USART_STAT_RXBRK_SHIFT (10U) -#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) -#define USART_STAT_DELTARXBRK_MASK (0x800U) -#define USART_STAT_DELTARXBRK_SHIFT (11U) -#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) -#define USART_STAT_START_MASK (0x1000U) -#define USART_STAT_START_SHIFT (12U) -#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) -#define USART_STAT_FRAMERRINT_MASK (0x2000U) -#define USART_STAT_FRAMERRINT_SHIFT (13U) -#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) -#define USART_STAT_PARITYERRINT_MASK (0x4000U) -#define USART_STAT_PARITYERRINT_SHIFT (14U) -#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) -#define USART_STAT_RXNOISEINT_MASK (0x8000U) -#define USART_STAT_RXNOISEINT_SHIFT (15U) -#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) -#define USART_STAT_ABERR_MASK (0x10000U) -#define USART_STAT_ABERR_SHIFT (16U) -#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -/*! @{ */ -#define USART_INTENSET_TXIDLEEN_MASK (0x8U) -#define USART_INTENSET_TXIDLEEN_SHIFT (3U) -#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) -#define USART_INTENSET_DELTACTSEN_MASK (0x20U) -#define USART_INTENSET_DELTACTSEN_SHIFT (5U) -#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) -#define USART_INTENSET_TXDISEN_MASK (0x40U) -#define USART_INTENSET_TXDISEN_SHIFT (6U) -#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) -#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) -#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) -#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) -#define USART_INTENSET_STARTEN_MASK (0x1000U) -#define USART_INTENSET_STARTEN_SHIFT (12U) -#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) -#define USART_INTENSET_FRAMERREN_MASK (0x2000U) -#define USART_INTENSET_FRAMERREN_SHIFT (13U) -#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) -#define USART_INTENSET_PARITYERREN_MASK (0x4000U) -#define USART_INTENSET_PARITYERREN_SHIFT (14U) -#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) -#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) -#define USART_INTENSET_RXNOISEEN_SHIFT (15U) -#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) -#define USART_INTENSET_ABERREN_MASK (0x10000U) -#define USART_INTENSET_ABERREN_SHIFT (16U) -#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ -/*! @{ */ -#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) -#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) -#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) -#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) -#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) -#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) -#define USART_INTENCLR_TXDISCLR_MASK (0x40U) -#define USART_INTENCLR_TXDISCLR_SHIFT (6U) -#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) -#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) -#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) -#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) -#define USART_INTENCLR_STARTCLR_MASK (0x1000U) -#define USART_INTENCLR_STARTCLR_SHIFT (12U) -#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) -#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) -#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) -#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) -#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) -#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) -#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) -#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) -#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) -#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) -#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) -#define USART_INTENCLR_ABERRCLR_SHIFT (16U) -#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) -/*! @} */ - -/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ -/*! @{ */ -#define USART_BRG_BRGVAL_MASK (0xFFFFU) -#define USART_BRG_BRGVAL_SHIFT (0U) -#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ -/*! @{ */ -#define USART_INTSTAT_TXIDLE_MASK (0x8U) -#define USART_INTSTAT_TXIDLE_SHIFT (3U) -#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) -#define USART_INTSTAT_DELTACTS_MASK (0x20U) -#define USART_INTSTAT_DELTACTS_SHIFT (5U) -#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) -#define USART_INTSTAT_TXDISINT_MASK (0x40U) -#define USART_INTSTAT_TXDISINT_SHIFT (6U) -#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) -#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) -#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) -#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) -#define USART_INTSTAT_START_MASK (0x1000U) -#define USART_INTSTAT_START_SHIFT (12U) -#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) -#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) -#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) -#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) -#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) -#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) -#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) -#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) -#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) -#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) -#define USART_INTSTAT_ABERRINT_MASK (0x10000U) -#define USART_INTSTAT_ABERRINT_SHIFT (16U) -#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) -/*! @} */ - -/*! @name OSR - Oversample selection register for asynchronous communication. */ -/*! @{ */ -#define USART_OSR_OSRVAL_MASK (0xFU) -#define USART_OSR_OSRVAL_SHIFT (0U) -#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) -/*! @} */ - -/*! @name ADDR - Address register for automatic address matching. */ -/*! @{ */ -#define USART_ADDR_ADDRESS_MASK (0xFFU) -#define USART_ADDR_ADDRESS_SHIFT (0U) -#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ -#define USART_FIFOCFG_ENABLETX_MASK (0x1U) -#define USART_FIFOCFG_ENABLETX_SHIFT (0U) -#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) -#define USART_FIFOCFG_ENABLERX_MASK (0x2U) -#define USART_FIFOCFG_ENABLERX_SHIFT (1U) -#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) -#define USART_FIFOCFG_SIZE_MASK (0x30U) -#define USART_FIFOCFG_SIZE_SHIFT (4U) -#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) -#define USART_FIFOCFG_DMATX_MASK (0x1000U) -#define USART_FIFOCFG_DMATX_SHIFT (12U) -#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) -#define USART_FIFOCFG_DMARX_MASK (0x2000U) -#define USART_FIFOCFG_DMARX_SHIFT (13U) -#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) -#define USART_FIFOCFG_WAKETX_MASK (0x4000U) -#define USART_FIFOCFG_WAKETX_SHIFT (14U) -#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) -#define USART_FIFOCFG_WAKERX_MASK (0x8000U) -#define USART_FIFOCFG_WAKERX_SHIFT (15U) -#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) -#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) -#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) -#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) -#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ -#define USART_FIFOSTAT_TXERR_MASK (0x1U) -#define USART_FIFOSTAT_TXERR_SHIFT (0U) -#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) -#define USART_FIFOSTAT_RXERR_MASK (0x2U) -#define USART_FIFOSTAT_RXERR_SHIFT (1U) -#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) -#define USART_FIFOSTAT_PERINT_MASK (0x8U) -#define USART_FIFOSTAT_PERINT_SHIFT (3U) -#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) -#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) -#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) -#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) -#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) -#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) -#define USART_FIFOSTAT_RXFULL_MASK (0x80U) -#define USART_FIFOSTAT_RXFULL_SHIFT (7U) -#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) -#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define USART_FIFOSTAT_TXLVL_SHIFT (8U) -#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) -#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define USART_FIFOSTAT_RXLVL_SHIFT (16U) -#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ -#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) -#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) -#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) -#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) -#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) -#define USART_FIFOTRIG_TXLVL_SHIFT (8U) -#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) -#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define USART_FIFOTRIG_RXLVL_SHIFT (16U) -#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ -#define USART_FIFOINTENSET_TXERR_MASK (0x1U) -#define USART_FIFOINTENSET_TXERR_SHIFT (0U) -#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) -#define USART_FIFOINTENSET_RXERR_MASK (0x2U) -#define USART_FIFOINTENSET_RXERR_SHIFT (1U) -#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) -#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) -#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) -#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) -#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) -#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) -#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ -#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) -#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) -#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) -#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) -#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) -#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) -#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) -#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) -#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) -#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ -#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) -#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) -#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) -#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) -#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) -#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) -#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) -#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) -#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) -#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) -#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) -#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) -#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ -#define USART_FIFOWR_TXDATA_MASK (0x1FFU) -#define USART_FIFOWR_TXDATA_SHIFT (0U) -#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ -#define USART_FIFORD_RXDATA_MASK (0x1FFU) -#define USART_FIFORD_RXDATA_SHIFT (0U) -#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) -#define USART_FIFORD_FRAMERR_MASK (0x2000U) -#define USART_FIFORD_FRAMERR_SHIFT (13U) -#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) -#define USART_FIFORD_PARITYERR_MASK (0x4000U) -#define USART_FIFORD_PARITYERR_SHIFT (14U) -#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) -#define USART_FIFORD_RXNOISE_MASK (0x8000U) -#define USART_FIFORD_RXNOISE_SHIFT (15U) -#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ -#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) -#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) -#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) -#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) -#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) -#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) -#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) -#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) -#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) -#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) -#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) -#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USART_Register_Masks */ - - -/* USART - Peripheral instance base addresses */ -/** Peripheral USART0 base address */ -#define USART0_BASE (0x40086000u) -/** Peripheral USART0 base pointer */ -#define USART0 ((USART_Type *)USART0_BASE) -/** Peripheral USART1 base address */ -#define USART1_BASE (0x40087000u) -/** Peripheral USART1 base pointer */ -#define USART1 ((USART_Type *)USART1_BASE) -/** Peripheral USART2 base address */ -#define USART2_BASE (0x40088000u) -/** Peripheral USART2 base pointer */ -#define USART2 ((USART_Type *)USART2_BASE) -/** Peripheral USART3 base address */ -#define USART3_BASE (0x40089000u) -/** Peripheral USART3 base pointer */ -#define USART3 ((USART_Type *)USART3_BASE) -/** Peripheral USART4 base address */ -#define USART4_BASE (0x4008A000u) -/** Peripheral USART4 base pointer */ -#define USART4 ((USART_Type *)USART4_BASE) -/** Peripheral USART5 base address */ -#define USART5_BASE (0x40096000u) -/** Peripheral USART5 base pointer */ -#define USART5 ((USART_Type *)USART5_BASE) -/** Peripheral USART6 base address */ -#define USART6_BASE (0x40097000u) -/** Peripheral USART6 base pointer */ -#define USART6 ((USART_Type *)USART6_BASE) -/** Peripheral USART7 base address */ -#define USART7_BASE (0x40098000u) -/** Peripheral USART7 base pointer */ -#define USART7 ((USART_Type *)USART7_BASE) -/** Array initializer of USART peripheral base addresses */ -#define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } -/** Array initializer of USART peripheral base pointers */ -#define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } -/** Interrupt vectors for the USART peripheral type */ -#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group USART_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer - * @{ - */ - -/** USB - Register Layout Typedef */ -typedef struct { - __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ - __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ - __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ - __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ - __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ - __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ - __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ - __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ - __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ - __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ - __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ - uint8_t RESERVED_0[8]; - __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ -} USB_Type; - -/* ---------------------------------------------------------------------------- - -- USB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Register_Masks USB Register Masks - * @{ - */ - -/*! @name DEVCMDSTAT - USB Device Command/Status register */ -/*! @{ */ -#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) -#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) -#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) -#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) -#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) -#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) -#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) -#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) -#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) -#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) -#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) -#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) -#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) -#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) -#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) -#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) -#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) -#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) -#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) -#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) -#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) -#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) -#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) -#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) -#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) -#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) -#define USB_DEVCMDSTAT_DCON_SHIFT (16U) -#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) -#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) -#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) -#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) -#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) -#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) -#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) -#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) -#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) -#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) -#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) -#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) -#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) -#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) -#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) -#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) -#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) -#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) -#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) -/*! @} */ - -/*! @name INFO - USB Info register */ -/*! @{ */ -#define USB_INFO_FRAME_NR_MASK (0x7FFU) -#define USB_INFO_FRAME_NR_SHIFT (0U) -#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) -#define USB_INFO_ERR_CODE_MASK (0x7800U) -#define USB_INFO_ERR_CODE_SHIFT (11U) -#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) -/*! @} */ - -/*! @name EPLISTSTART - USB EP Command/Status List start address */ -/*! @{ */ -#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) -#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) -#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) -/*! @} */ - -/*! @name DATABUFSTART - USB Data buffer start address */ -/*! @{ */ -#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) -#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) -#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) -/*! @} */ - -/*! @name LPM - USB Link Power Management register */ -/*! @{ */ -#define USB_LPM_HIRD_HW_MASK (0xFU) -#define USB_LPM_HIRD_HW_SHIFT (0U) -#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) -#define USB_LPM_HIRD_SW_MASK (0xF0U) -#define USB_LPM_HIRD_SW_SHIFT (4U) -#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) -#define USB_LPM_DATA_PENDING_MASK (0x100U) -#define USB_LPM_DATA_PENDING_SHIFT (8U) -#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) -/*! @} */ - -/*! @name EPSKIP - USB Endpoint skip */ -/*! @{ */ -#define USB_EPSKIP_SKIP_MASK (0x3FFFFFFFU) -#define USB_EPSKIP_SKIP_SHIFT (0U) -#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) -/*! @} */ - -/*! @name EPINUSE - USB Endpoint Buffer in use */ -/*! @{ */ -#define USB_EPINUSE_BUF_MASK (0x3FCU) -#define USB_EPINUSE_BUF_SHIFT (2U) -#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) -/*! @} */ - -/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ -/*! @{ */ -#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) -#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) -#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) -/*! @} */ - -/*! @name INTSTAT - USB interrupt status register */ -/*! @{ */ -#define USB_INTSTAT_EP0OUT_MASK (0x1U) -#define USB_INTSTAT_EP0OUT_SHIFT (0U) -#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) -#define USB_INTSTAT_EP0IN_MASK (0x2U) -#define USB_INTSTAT_EP0IN_SHIFT (1U) -#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) -#define USB_INTSTAT_EP1OUT_MASK (0x4U) -#define USB_INTSTAT_EP1OUT_SHIFT (2U) -#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) -#define USB_INTSTAT_EP1IN_MASK (0x8U) -#define USB_INTSTAT_EP1IN_SHIFT (3U) -#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) -#define USB_INTSTAT_EP2OUT_MASK (0x10U) -#define USB_INTSTAT_EP2OUT_SHIFT (4U) -#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) -#define USB_INTSTAT_EP2IN_MASK (0x20U) -#define USB_INTSTAT_EP2IN_SHIFT (5U) -#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) -#define USB_INTSTAT_EP3OUT_MASK (0x40U) -#define USB_INTSTAT_EP3OUT_SHIFT (6U) -#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) -#define USB_INTSTAT_EP3IN_MASK (0x80U) -#define USB_INTSTAT_EP3IN_SHIFT (7U) -#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) -#define USB_INTSTAT_EP4OUT_MASK (0x100U) -#define USB_INTSTAT_EP4OUT_SHIFT (8U) -#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) -#define USB_INTSTAT_EP4IN_MASK (0x200U) -#define USB_INTSTAT_EP4IN_SHIFT (9U) -#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) -#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) -#define USB_INTSTAT_FRAME_INT_SHIFT (30U) -#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) -#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) -#define USB_INTSTAT_DEV_INT_SHIFT (31U) -#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) -/*! @} */ - -/*! @name INTEN - USB interrupt enable register */ -/*! @{ */ -#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) -#define USB_INTEN_EP_INT_EN_SHIFT (0U) -#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) -#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) -#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) -#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) -#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) -#define USB_INTEN_DEV_INT_EN_SHIFT (31U) -#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) -/*! @} */ - -/*! @name INTSETSTAT - USB set interrupt status register */ -/*! @{ */ -#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) -#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) -#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) -#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) -#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) -#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) -#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) -#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) -#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) -/*! @} */ - -/*! @name EPTOGGLE - USB Endpoint toggle register */ -/*! @{ */ -#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) -#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) -#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USB_Register_Masks */ - - -/* USB - Peripheral instance base addresses */ -/** Peripheral USB0 base address */ -#define USB0_BASE (0x40084000u) -/** Peripheral USB0 base pointer */ -#define USB0 ((USB_Type *)USB0_BASE) -/** Array initializer of USB peripheral base addresses */ -#define USB_BASE_ADDRS { USB0_BASE } -/** Array initializer of USB peripheral base pointers */ -#define USB_BASE_PTRS { USB0 } -/** Interrupt vectors for the USB peripheral type */ -#define USB_IRQS { USB0_IRQn } -#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- UTICK Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer - * @{ - */ - -/** UTICK - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ - __IO uint32_t STAT; /**< Status register., offset: 0x4 */ - __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ - __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ - __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ -} UTICK_Type; - -/* ---------------------------------------------------------------------------- - -- UTICK Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Register_Masks UTICK Register Masks - * @{ - */ - -/*! @name CTRL - Control register. */ -/*! @{ */ -#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) -#define UTICK_CTRL_DELAYVAL_SHIFT (0U) -#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) -#define UTICK_CTRL_REPEAT_MASK (0x80000000U) -#define UTICK_CTRL_REPEAT_SHIFT (31U) -#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) -/*! @} */ - -/*! @name STAT - Status register. */ -/*! @{ */ -#define UTICK_STAT_INTR_MASK (0x1U) -#define UTICK_STAT_INTR_SHIFT (0U) -#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) -#define UTICK_STAT_ACTIVE_MASK (0x2U) -#define UTICK_STAT_ACTIVE_SHIFT (1U) -#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) -/*! @} */ - -/*! @name CFG - Capture configuration register. */ -/*! @{ */ -#define UTICK_CFG_CAPEN0_MASK (0x1U) -#define UTICK_CFG_CAPEN0_SHIFT (0U) -#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) -#define UTICK_CFG_CAPEN1_MASK (0x2U) -#define UTICK_CFG_CAPEN1_SHIFT (1U) -#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) -#define UTICK_CFG_CAPEN2_MASK (0x4U) -#define UTICK_CFG_CAPEN2_SHIFT (2U) -#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) -#define UTICK_CFG_CAPEN3_MASK (0x8U) -#define UTICK_CFG_CAPEN3_SHIFT (3U) -#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) -#define UTICK_CFG_CAPPOL0_MASK (0x100U) -#define UTICK_CFG_CAPPOL0_SHIFT (8U) -#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) -#define UTICK_CFG_CAPPOL1_MASK (0x200U) -#define UTICK_CFG_CAPPOL1_SHIFT (9U) -#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) -#define UTICK_CFG_CAPPOL2_MASK (0x400U) -#define UTICK_CFG_CAPPOL2_SHIFT (10U) -#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) -#define UTICK_CFG_CAPPOL3_MASK (0x800U) -#define UTICK_CFG_CAPPOL3_SHIFT (11U) -#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) -/*! @} */ - -/*! @name CAPCLR - Capture clear register. */ -/*! @{ */ -#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) -#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) -#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) -#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) -#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) -#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) -#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) -#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) -#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) -#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) -#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) -#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) -/*! @} */ - -/*! @name CAP - Capture register . */ -/*! @{ */ -#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) -#define UTICK_CAP_CAP_VALUE_SHIFT (0U) -#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) -#define UTICK_CAP_VALID_MASK (0x80000000U) -#define UTICK_CAP_VALID_SHIFT (31U) -#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) -/*! @} */ - -/* The count of UTICK_CAP */ -#define UTICK_CAP_COUNT (4U) - - -/*! - * @} - */ /* end of group UTICK_Register_Masks */ - - -/* UTICK - Peripheral instance base addresses */ -/** Peripheral UTICK0 base address */ -#define UTICK0_BASE (0x4000E000u) -/** Peripheral UTICK0 base pointer */ -#define UTICK0 ((UTICK_Type *)UTICK0_BASE) -/** Array initializer of UTICK peripheral base addresses */ -#define UTICK_BASE_ADDRS { UTICK0_BASE } -/** Array initializer of UTICK peripheral base pointers */ -#define UTICK_BASE_PTRS { UTICK0 } -/** Interrupt vectors for the UTICK peripheral type */ -#define UTICK_IRQS { UTICK0_IRQn } - -/*! - * @} - */ /* end of group UTICK_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- WWDT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer - * @{ - */ - -/** WWDT - Register Layout Typedef */ -typedef struct { - __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ - __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ - __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ - __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ - uint8_t RESERVED_0[4]; - __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ - __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ -} WWDT_Type; - -/* ---------------------------------------------------------------------------- - -- WWDT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Register_Masks WWDT Register Masks - * @{ - */ - -/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ -/*! @{ */ -#define WWDT_MOD_WDEN_MASK (0x1U) -#define WWDT_MOD_WDEN_SHIFT (0U) -#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) -#define WWDT_MOD_WDRESET_MASK (0x2U) -#define WWDT_MOD_WDRESET_SHIFT (1U) -#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) -#define WWDT_MOD_WDTOF_MASK (0x4U) -#define WWDT_MOD_WDTOF_SHIFT (2U) -#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) -#define WWDT_MOD_WDINT_MASK (0x8U) -#define WWDT_MOD_WDINT_SHIFT (3U) -#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) -#define WWDT_MOD_WDPROTECT_MASK (0x10U) -#define WWDT_MOD_WDPROTECT_SHIFT (4U) -#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) -#define WWDT_MOD_LOCK_MASK (0x20U) -#define WWDT_MOD_LOCK_SHIFT (5U) -#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) -/*! @} */ - -/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ -/*! @{ */ -#define WWDT_TC_COUNT_MASK (0xFFFFFFU) -#define WWDT_TC_COUNT_SHIFT (0U) -#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) -/*! @} */ - -/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ -/*! @{ */ -#define WWDT_FEED_FEED_MASK (0xFFU) -#define WWDT_FEED_FEED_SHIFT (0U) -#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) -/*! @} */ - -/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ -/*! @{ */ -#define WWDT_TV_COUNT_MASK (0xFFFFFFU) -#define WWDT_TV_COUNT_SHIFT (0U) -#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) -/*! @} */ - -/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ -/*! @{ */ -#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) -#define WWDT_WARNINT_WARNINT_SHIFT (0U) -#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) -/*! @} */ - -/*! @name WINDOW - Watchdog Window compare value. */ -/*! @{ */ -#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) -#define WWDT_WINDOW_WINDOW_SHIFT (0U) -#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group WWDT_Register_Masks */ - - -/* WWDT - Peripheral instance base addresses */ -/** Peripheral WWDT base address */ -#define WWDT_BASE (0x4000C000u) -/** Peripheral WWDT base pointer */ -#define WWDT ((WWDT_Type *)WWDT_BASE) -/** Array initializer of WWDT peripheral base addresses */ -#define WWDT_BASE_ADDRS { WWDT_BASE } -/** Array initializer of WWDT peripheral base pointers */ -#define WWDT_BASE_PTRS { WWDT } -/** Interrupt vectors for the WWDT peripheral type */ -#define WWDT_IRQS { WDT_BOD_IRQn } - -/*! - * @} - */ /* end of group WWDT_Peripheral_Access_Layer */ - - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop - #else - #pragma pop - #endif -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -/*! - * @} - */ /* end of group Peripheral_access_layer */ - - -/* ---------------------------------------------------------------------------- - -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - * @{ - */ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang system_header - #endif -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma system_include -#endif - -/** - * @brief Mask and left-shift a bit field value for use in a register bit range. - * @param field Name of the register bit field. - * @param value Value of the bit field. - * @return Masked and shifted value. - */ -#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) -/** - * @brief Mask and right-shift a register value to extract a bit field value. - * @param field Name of the register bit field. - * @param value Value of the register. - * @return Masked and shifted bit field value. - */ -#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) - -/*! - * @} - */ /* end of group Bit_Field_Generic_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SDK Compatibility - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDK_Compatibility_Symbols SDK Compatibility - * @{ - */ - -/* No SDK compatibility issues. */ - -/*! - * @} - */ /* end of group SDK_Compatibility_Symbols */ - - -#endif /* _LPC54114_CM4_H_ */ - diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm4_features.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm4_features.h deleted file mode 100644 index 0fe1ee1ab6b..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm4_features.h +++ /dev/null @@ -1,249 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2016-05-09 -** Build: b180327 -** -** Abstract: -** Chip specific module features. -** -** The Clear BSD License -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without -** modification, are permitted (subject to the limitations in the -** disclaimer below) provided that the following conditions are met: -** -** * Redistributions of source code must retain the above copyright -** notice, this list of conditions and the following disclaimer. -** -** * Redistributions in binary form must reproduce the above copyright -** notice, this list of conditions and the following disclaimer in the -** documentation and/or other materials provided with the distribution. -** -** * Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from -** this software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2016-05-09) -** Initial version. -** -** ################################################################### -*/ - -#ifndef _LPC54114_cm4_FEATURES_H_ -#define _LPC54114_cm4_FEATURES_H_ - -/* SOC module features */ - -/* @brief ADC availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC_COUNT (1) -/* @brief ASYNC_SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1) -/* @brief CRC availability on the SoC. */ -#define FSL_FEATURE_SOC_CRC_COUNT (1) -/* @brief CTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_CTIMER_COUNT (5) -/* @brief DMA availability on the SoC. */ -#define FSL_FEATURE_SOC_DMA_COUNT (1) -/* @brief DMIC availability on the SoC. */ -#define FSL_FEATURE_SOC_DMIC_COUNT (1) -/* @brief FLEXCOMM availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (8) -/* @brief GINT availability on the SoC. */ -#define FSL_FEATURE_SOC_GINT_COUNT (2) -/* @brief GPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_GPIO_COUNT (1) -/* @brief I2C availability on the SoC. */ -#define FSL_FEATURE_SOC_I2C_COUNT (8) -/* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (2) -/* @brief INPUTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) -/* @brief IOCON availability on the SoC. */ -#define FSL_FEATURE_SOC_IOCON_COUNT (1) -/* @brief MAILBOX availability on the SoC. */ -#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) -/* @brief MRT availability on the SoC. */ -#define FSL_FEATURE_SOC_MRT_COUNT (1) -/* @brief PINT availability on the SoC. */ -#define FSL_FEATURE_SOC_PINT_COUNT (1) -/* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (1) -/* @brief SCT availability on the SoC. */ -#define FSL_FEATURE_SOC_SCT_COUNT (1) -/* @brief SPI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPI_COUNT (8) -/* @brief SPIFI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPIFI_COUNT (1) -/* @brief SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCON_COUNT (1) -/* @brief USART availability on the SoC. */ -#define FSL_FEATURE_SOC_USART_COUNT (8) -/* @brief USB availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_COUNT (1) -/* @brief UTICK availability on the SoC. */ -#define FSL_FEATURE_SOC_UTICK_COUNT (1) -/* @brief WWDT availability on the SoC. */ -#define FSL_FEATURE_SOC_WWDT_COUNT (1) - -/* ADC module features */ - -/* @brief Do not has input select (register INSEL). */ -#define FSL_FEATURE_ADC_HAS_NO_INSEL (0) -/* @brief Has ASYNMODE bitfile in CTRL reigster. */ -#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1) -/* @brief Has ASYNMODE bitfile in CTRL reigster. */ -#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1) -/* @brief Has ASYNMODE bitfile in CTRL reigster. */ -#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1) -/* @brief Has ASYNMODE bitfile in CTRL reigster. */ -#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1) -/* @brief Has ASYNMODE bitfile in CTRL reigster. */ -#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0) -/* @brief Has ASYNMODE bitfile in CTRL reigster. */ -#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0) -/* @brief Has startup register. */ -#define FSL_FEATURE_ADC_HAS_STARTUP_REG (1) -/* @brief Has ADTrim register */ -#define FSL_FEATURE_ADC_HAS_TRIM_REG (0) -/* @brief Has Calibration register. */ -#define FSL_FEATURE_ADC_HAS_CALIB_REG (1) - -/* DMA module features */ - -/* @brief Number of channels */ -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (20) - -/* FLEXCOMM module features */ - -/* @brief FLEXCOMM0 USART INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) -/* @brief FLEXCOMM0 SPI INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) -/* @brief FLEXCOMM0 I2C INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) -/* @brief FLEXCOMM1 USART INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) -/* @brief FLEXCOMM1 SPI INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) -/* @brief FLEXCOMM1 I2C INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) -/* @brief FLEXCOMM2 USART INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) -/* @brief FLEXCOMM2 SPI INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) -/* @brief FLEXCOMM2 I2C INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) -/* @brief FLEXCOMM3 USART INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) -/* @brief FLEXCOMM3 SPI INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) -/* @brief FLEXCOMM3 I2C INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) -/* @brief FLEXCOMM4 USART INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) -/* @brief FLEXCOMM4 SPI INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) -/* @brief FLEXCOMM4 I2C INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) -/* @brief FLEXCOMM5 USART INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) -/* @brief FLEXCOMM5 SPI INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) -/* @brief FLEXCOMM5 I2C INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) -/* @brief FLEXCOMM6 USART INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) -/* @brief FLEXCOMM6 SPI INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) -/* @brief FLEXCOMM6 I2C INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) -/* @brief FLEXCOMM7 I2S INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (0) -/* @brief FLEXCOMM7 USART INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) -/* @brief FLEXCOMM7 SPI INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) -/* @brief FLEXCOMM7 I2C INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) -/* @brief FLEXCOMM7 I2S INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (1) - -/* MAILBOX module features */ - -/* @brief Mailbox side for current core. */ -#define FSL_FEATURE_MAILBOX_SIDE_A (1) - -/* MRT module features */ - -/* @brief number of channels. */ -#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) - -/* interrupt module features */ - -/* @brief Lowest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) -/* @brief Highest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105) - -/* PINT module features */ - -/* @brief Number of connected outputs */ -#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) - -/* SCT module features */ - -/* @brief Number of events */ -#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (10) -/* @brief Number of states */ -#define FSL_FEATURE_SCT_NUMBER_OF_STATES (10) -/* @brief Number of match capture */ -#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) -/* @brief Number of outputs */ -#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (8) - -/* SYSCON module features */ - -/* @brief Pointer to ROM IAP entry functions */ -#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205) -/* @brief Flash page size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256) -/* @brief Flash sector size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) -/* @brief Flash size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (262144) - -/* SysTick module features */ - -/* @brief Systick has external reference clock. */ -#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) -/* @brief Systick external reference clock is core clock divided by this value. */ -#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) - -/* USB module features */ - -/* @brief Number of the endpoint in USB FS */ -#define FSL_FEATURE_USB_EP_NUM (5) - -#endif /* _LPC54114_cm4_FEATURES_H_ */ - diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/SConscript b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/SConscript deleted file mode 100644 index b9e88373613..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/SConscript +++ /dev/null @@ -1,35 +0,0 @@ -# RT-Thread building script for bridge - -import os -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -objs = [] -list = os.listdir(cwd) -CPPDEFINES = [] - -objs = objs + SConscript(os.path.join('drivers', 'SConscript')) -objs = objs + SConscript(os.path.join('utilities', 'SConscript')) - -if rtconfig.PLATFORM in ['gcc']: - objs = objs + SConscript(os.path.join('gcc', 'SConscript')) - CPPDEFINES += ['__USE_CMSIS'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - objs = objs + SConscript(os.path.join('arm', 'SConscript')) -elif rtconfig.PLATFORM in ['iccarm']: - objs = objs + SConscript(os.path.join('iar', 'SConscript')) - -src = Split(""" -system_LPC54114_cm4.c -""") - -CPPPATH = [cwd] -CPPDEFINES += ['CORE_M4', 'CPU_LPC54114', 'CPU_LPC54114J256BD64_cm4=1'] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) - -objs = objs + group - -Return('objs') diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/LPC54114J256_cm0plus.scf b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/LPC54114J256_cm0plus.scf deleted file mode 100644 index b0d9176b43b..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/LPC54114J256_cm0plus.scf +++ /dev/null @@ -1,107 +0,0 @@ -#! armcc -E -/* -** ################################################################### -** Processors: LPC54114J256BD64_cm0plus -** LPC54114J256UK49_cm0plus -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC5411x User manual Rev. 1.0 16 February 2016 -** Version: rev. 1.0, 2016-04-29 -** Build: b160606 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** The Clear BSD License -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted (subject to the limitations in the disclaimer below) provided -** that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -#define m_interrupts_start 0x20010000 -#define m_interrupts_size 0x000000C0 - -#define m_text_start 0x200100C0 -#define m_text_size 0x0000FF40 - -#if (defined(__use_shmem__)) -#define m_rpmsg_sh_mem_start 0x20026800 -#define m_rpmsg_sh_mem_size 0x00001800 -#define m_data_start 0x20020000 -#define m_data_size 0x00006800 -#else -#define m_data_start 0x20020000 -#define m_data_size 0x00008000 -#endif - - -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (RESET,+FIRST) - } - ER_m_text m_text_start m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP ((ImageLimit(RW_m_data) == m_data_start) ? ImageLimit(RW_m_data) : +0) EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - -#if (defined(__use_shmem__)) - RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG - * (rpmsg_sh_mem_section) - } -#endif -} - diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/LPC54114J256_cm0plus_ram.scf b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/LPC54114J256_cm0plus_ram.scf deleted file mode 100644 index 99970a0bb32..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/LPC54114J256_cm0plus_ram.scf +++ /dev/null @@ -1,105 +0,0 @@ -#! armcc -E -/* -** ################################################################### -** Processors: LPC54114J256BD64_cm0plus -** LPC54114J256UK49_cm0plus -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC5411x User manual Rev. 1.0 16 February 2016 -** Version: rev. 1.0, 2016-04-29 -** Build: b160606 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** The Clear BSD License -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted (subject to the limitations in the disclaimer below) provided -** that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -#define m_interrupts_start 0x20010000 -#define m_interrupts_size 0x000000C0 - -#define m_text_start 0x200100C0 -#define m_text_size 0x0000FF40 - -#if (defined(__use_shmem__)) -#define m_rpmsg_sh_mem_start 0x20026800 -#define m_rpmsg_sh_mem_size 0x00001800 -#define m_data_start 0x20020000 -#define m_data_size 0x00006800 -#else -#define m_data_start 0x20020000 -#define m_data_size 0x00008000 -#endif - -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (RESET,+FIRST) - } - ER_m_text m_text_start m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP ((ImageLimit(RW_m_data) == m_data_start) ? ImageLimit(RW_m_data) : +0) EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } -#if (defined(__use_shmem__)) - RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG - * (rpmsg_sh_mem_section) - } -#endif -} - diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/LPC54114J256_cm4_ram.scf b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/LPC54114J256_cm4_ram.scf deleted file mode 100644 index d9a73cf6330..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/LPC54114J256_cm4_ram.scf +++ /dev/null @@ -1,106 +0,0 @@ -#! armcc -E -/* -** ################################################################### -** Processors: LPC54114J256BD64_cm4 -** LPC54114J256UK49_cm4 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC5411x User manual Rev. 1.0 16 February 2016 -** Version: rev. 1.0, 2016-04-29 -** Build: b160526 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** The Clear BSD License -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted (subject to the limitations in the disclaimer below) provided -** that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -#define m_interrupts_start 0x20000000 -#define m_interrupts_size 0x000000E0 - -#define m_text_start 0x200000E0 -#define m_text_size 0x0001FF20 - -#define m_data_start 0x20020000 -#define m_data_size 0x00008000 - -#define m_stack_start 0x04000000 -#define m_stack_size 0x00008000 - -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - - - -LR_m_text m_text_start m_text_size { ; load region size_region - ER_m_text m_text_start m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_stack_start+m_stack_size EMPTY -Stack_Size { ; Stack region growing down - } -} - -LR_m_interrupts m_interrupts_start m_interrupts_size { - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (RESET,+FIRST) - } -} - -LR_m_interrupts_ram m_interrupts_start m_interrupts_size { - VECTOR_RAM m_interrupts_start m_interrupts_size { ; load address = execution address - .ANY (.m_interrupts_ram) - } -} - diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/SConscript b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/SConscript deleted file mode 100644 index 578ff8d7c40..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/SConscript +++ /dev/null @@ -1,10 +0,0 @@ -from building import * - -cwd = GetCurrentDir() -src = Split(''' -startup_LPC54114_cm4.s -''') - -group = DefineGroup('Libraries', src, depend = [''], LIBS=['keil_lib_power'], LIBPATH=[cwd]) - -Return('group') diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/keil_lib_power.lib b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/keil_lib_power.lib deleted file mode 100644 index 304a63f82f2..00000000000 Binary files a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/keil_lib_power.lib and /dev/null differ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/keil_lib_power_m0.lib b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/keil_lib_power_m0.lib deleted file mode 100644 index 5cc5dd0727c..00000000000 Binary files a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/keil_lib_power_m0.lib and /dev/null differ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/startup_LPC54114_cm0plus.s b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/startup_LPC54114_cm0plus.s deleted file mode 100644 index dbaa73ffdd3..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/startup_LPC54114_cm0plus.s +++ /dev/null @@ -1,532 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC54114_cm0plus.s -; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the -; * LPC54114_cm0plus -; * @version: 1.0 -; * @date: 2016-4-29 -; * -; * The Clear BSD License -; * Copyright 1997 - 2016 Freescale Semiconductor, Inc. -; * Copyright 2016 - 2017 NXP -; * -; * All rights reserved. -; * -; * Redistribution and use in source and binary forms, with or without modification, -; * are permitted (subject to the limitations in the disclaimer below) provided -; * that the following conditions are met: -; * -; * o Redistributions of source code must retain the above copyright notice, this list -; * of conditions and the following disclaimer. -; * -; * o Redistributions in binary form must reproduce the above copyright notice, this -; * list of conditions and the following disclaimer in the documentation and/or -; * other materials provided with the distribution. -; * -; * o Neither the name of the copyright holder nor the names of its -; * contributors may be used to endorse or promote products derived from this -; * software without specific prior written permission. -; * -; * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S' PATENT RIGHTS ARE GRANTED BY THIS LICENSE. -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD 0 - DCD 0 - DCD 0 -__vector_table_0x1c - DCD 0 ; Checksum of the first 7 words - DCD 0 - DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot - DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot - DCD SVC_Handler - DCD 0 - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect - DCD DMA0_IRQHandler ; DMA controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S) - DCD ADC0_SEQA_IRQHandler ; ADC0 sequence A completion. - DCD ADC0_SEQB_IRQHandler ; ADC0 sequence B completion. - DCD ADC0_THCMP_IRQHandler ; ADC0 threshold compare and error. - DCD DMIC0_IRQHandler ; Digital microphone and DMIC subsystem - DCD HWVAD0_IRQHandler ; Hardware Voice Activity Detector - DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt - DCD USB0_IRQHandler ; USB device - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD IOH_IRQHandler ; IOH - DCD MAILBOX_IRQHandler ; Mailbox interrupt (present on selected devices) - -; Code Read Protection level (CRP) -; CRP_Level: -; <0xFFFFFFFF=> Disabled -; <0x4E697370=> NO_ISP -; <0x12345678=> CRP1 -; <0x87654321=> CRP2 -; <0x43218765=> CRP3 (Are you sure?) -; -CRP_Level EQU 0xFFFFFFFF - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - AREA |.text|, CODE, READONLY - -cpu_id EQU 0xE000ED00 -cpu_ctrl EQU 0x40000800 -coproc_boot EQU 0x40000804 -coproc_stack EQU 0x40000808 - -rel_vals - DCD cpu_id, cpu_ctrl, coproc_boot, coproc_stack - DCW 0xFFF, 0xC24 - -; Reset Handler - shared for both cores -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - IF :LNOT::DEF:SLAVEBOOT - ; Both the M0+ and M4 core come via this shared startup code, - ; but the M0+ and M4 core have different vector tables. - ; Determine if the core executing this code is the master or - ; the slave and handle each core state individually. -shared_boot_entry - LDR r6, =rel_vals - MOVS r4, #0 ; Flag for slave core (0) - MOVS r5, #1 - - ; Determine which core (M0+ or M4) this code is running on - ; r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) -get_current_core_id - LDR r0, [r6, #0] - LDR r1, [r0] ; r1 = CPU ID status - LSRS r1, r1, #4 ; Right justify 12 CPU ID bits - LDRH r2, [r6, #16] ; Mask for CPU ID bits - ANDS r2, r1, r2 ; r2 = ARM COrtex CPU ID - LDRH r3, [r6, #18] ; Mask for CPU ID bits - CMP r3, r2 ; Core ID matches M4 identifier - BNE get_master_status - MOV r4, r5 ; Set flag for master core (1) - - ; Determine if M4 core is the master or slave - ; r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) -get_master_status - LDR r0, [r6, #4] - LDR r3, [r0] ; r3 = SYSCON co-processor CPU control status - ANDS r3, r3, r5 ; r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) - - ; Select boot based on selected master core and core ID -select_boot - EORS r3, r3, r4 ; r4 = (Bit 0: 0 = master, 1 = slave) - BNE slave_boot - B normal_boot - - ; Slave boot -slave_boot - LDR r0, [r6, #8] - LDR r2, [r0] ; r1 = SYSCON co-processor boot address - CMP r2, #0 ; Slave boot address = 0 (not set up)? - BEQ cpu_sleep - LDR r0, [r6, #12] - LDR r1, [r0] ; r5 = SYSCON co-processor stack address - MOV sp, r1 ; Update slave CPU stack pointer - ; Be sure to update VTOR for the slave MCU to point to the - ; slave vector table in boot memory - BX r2 ; Jump to slave boot address - - ; Slave isn't yet setup for system boot from the master - ; so sleep until the master sets it up and then reboots it -cpu_sleep - MOV sp, r5 ; Will force exception if something happens -cpu_sleep_wfi - WFI ; Sleep forever until master reboots - B cpu_sleep_wfi - ENDIF - - ; Normal boot for master/slave -normal_boot - LDR r0, =SystemInit - BLX r0 - LDR r0, =__main - BX r0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -HardFault_Handler \ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP - -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -WDT_BOD_IRQHandler\ - PROC - EXPORT WDT_BOD_IRQHandler [WEAK] - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - ENDP - -DMA0_IRQHandler\ - PROC - EXPORT DMA0_IRQHandler [WEAK] - LDR R0, =DMA0_DriverIRQHandler - BX R0 - ENDP - -GINT0_IRQHandler\ - PROC - EXPORT GINT0_IRQHandler [WEAK] - LDR R0, =GINT0_DriverIRQHandler - BX R0 - ENDP - -GINT1_IRQHandler\ - PROC - EXPORT GINT1_IRQHandler [WEAK] - LDR R0, =GINT1_DriverIRQHandler - BX R0 - ENDP - -PIN_INT0_IRQHandler\ - PROC - EXPORT PIN_INT0_IRQHandler [WEAK] - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - ENDP - -PIN_INT1_IRQHandler\ - PROC - EXPORT PIN_INT1_IRQHandler [WEAK] - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - ENDP - -PIN_INT2_IRQHandler\ - PROC - EXPORT PIN_INT2_IRQHandler [WEAK] - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - ENDP - -PIN_INT3_IRQHandler\ - PROC - EXPORT PIN_INT3_IRQHandler [WEAK] - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - ENDP - -UTICK0_IRQHandler\ - PROC - EXPORT UTICK0_IRQHandler [WEAK] - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - ENDP - -MRT0_IRQHandler\ - PROC - EXPORT MRT0_IRQHandler [WEAK] - LDR R0, =MRT0_DriverIRQHandler - BX R0 - ENDP - -CTIMER0_IRQHandler\ - PROC - EXPORT CTIMER0_IRQHandler [WEAK] - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - ENDP - -CTIMER1_IRQHandler\ - PROC - EXPORT CTIMER1_IRQHandler [WEAK] - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - ENDP - -SCT0_IRQHandler\ - PROC - EXPORT SCT0_IRQHandler [WEAK] - LDR R0, =SCT0_DriverIRQHandler - BX R0 - ENDP - -CTIMER3_IRQHandler\ - PROC - EXPORT CTIMER3_IRQHandler [WEAK] - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM0_IRQHandler\ - PROC - EXPORT FLEXCOMM0_IRQHandler [WEAK] - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM1_IRQHandler\ - PROC - EXPORT FLEXCOMM1_IRQHandler [WEAK] - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM2_IRQHandler\ - PROC - EXPORT FLEXCOMM2_IRQHandler [WEAK] - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM3_IRQHandler\ - PROC - EXPORT FLEXCOMM3_IRQHandler [WEAK] - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM4_IRQHandler\ - PROC - EXPORT FLEXCOMM4_IRQHandler [WEAK] - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM5_IRQHandler\ - PROC - EXPORT FLEXCOMM5_IRQHandler [WEAK] - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM6_IRQHandler\ - PROC - EXPORT FLEXCOMM6_IRQHandler [WEAK] - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM7_IRQHandler\ - PROC - EXPORT FLEXCOMM7_IRQHandler [WEAK] - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - ENDP - -ADC0_SEQA_IRQHandler\ - PROC - EXPORT ADC0_SEQA_IRQHandler [WEAK] - LDR R0, =ADC0_SEQA_DriverIRQHandler - BX R0 - ENDP - -ADC0_SEQB_IRQHandler\ - PROC - EXPORT ADC0_SEQB_IRQHandler [WEAK] - LDR R0, =ADC0_SEQB_DriverIRQHandler - BX R0 - ENDP - -ADC0_THCMP_IRQHandler\ - PROC - EXPORT ADC0_THCMP_IRQHandler [WEAK] - LDR R0, =ADC0_THCMP_DriverIRQHandler - BX R0 - ENDP - -DMIC0_IRQHandler\ - PROC - EXPORT DMIC0_IRQHandler [WEAK] - LDR R0, =DMIC0_DriverIRQHandler - BX R0 - ENDP - -HWVAD0_IRQHandler\ - PROC - EXPORT HWVAD0_IRQHandler [WEAK] - LDR R0, =HWVAD0_DriverIRQHandler - BX R0 - ENDP - -USB0_NEEDCLK_IRQHandler\ - PROC - EXPORT USB0_NEEDCLK_IRQHandler [WEAK] - LDR R0, =USB0_NEEDCLK_DriverIRQHandler - BX R0 - ENDP - -USB0_IRQHandler\ - PROC - EXPORT USB0_IRQHandler [WEAK] - LDR R0, =USB0_DriverIRQHandler - BX R0 - ENDP - -RTC_IRQHandler\ - PROC - EXPORT RTC_IRQHandler [WEAK] - LDR R0, =RTC_DriverIRQHandler - BX R0 - ENDP - -IOH_IRQHandler\ - PROC - EXPORT IOH_IRQHandler [WEAK] - LDR R0, =IOH_DriverIRQHandler - BX R0 - ENDP - -MAILBOX_IRQHandler\ - PROC - EXPORT MAILBOX_IRQHandler [WEAK] - LDR R0, =MAILBOX_DriverIRQHandler - BX R0 - ENDP - -Default_Handler PROC - EXPORT WDT_BOD_DriverIRQHandler [WEAK] - EXPORT DMA0_DriverIRQHandler [WEAK] - EXPORT GINT0_DriverIRQHandler [WEAK] - EXPORT GINT1_DriverIRQHandler [WEAK] - EXPORT PIN_INT0_DriverIRQHandler [WEAK] - EXPORT PIN_INT1_DriverIRQHandler [WEAK] - EXPORT PIN_INT2_DriverIRQHandler [WEAK] - EXPORT PIN_INT3_DriverIRQHandler [WEAK] - EXPORT UTICK0_DriverIRQHandler [WEAK] - EXPORT MRT0_DriverIRQHandler [WEAK] - EXPORT CTIMER0_DriverIRQHandler [WEAK] - EXPORT CTIMER1_DriverIRQHandler [WEAK] - EXPORT SCT0_DriverIRQHandler [WEAK] - EXPORT CTIMER3_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM0_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM1_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM2_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM3_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM4_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM5_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM6_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM7_DriverIRQHandler [WEAK] - EXPORT ADC0_SEQA_DriverIRQHandler [WEAK] - EXPORT ADC0_SEQB_DriverIRQHandler [WEAK] - EXPORT ADC0_THCMP_DriverIRQHandler [WEAK] - EXPORT DMIC0_DriverIRQHandler [WEAK] - EXPORT HWVAD0_DriverIRQHandler [WEAK] - EXPORT USB0_NEEDCLK_DriverIRQHandler [WEAK] - EXPORT USB0_DriverIRQHandler [WEAK] - EXPORT RTC_DriverIRQHandler [WEAK] - EXPORT IOH_DriverIRQHandler [WEAK] - EXPORT MAILBOX_DriverIRQHandler [WEAK] - -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_SEQA_DriverIRQHandler -ADC0_SEQB_DriverIRQHandler -ADC0_THCMP_DriverIRQHandler -DMIC0_DriverIRQHandler -HWVAD0_DriverIRQHandler -USB0_NEEDCLK_DriverIRQHandler -USB0_DriverIRQHandler -RTC_DriverIRQHandler -IOH_DriverIRQHandler -MAILBOX_DriverIRQHandler - - B . - - ENDP - - - ALIGN - - - END - diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/startup_LPC54114_cm4.s b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/startup_LPC54114_cm4.s deleted file mode 100644 index dad9da5a92b..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/startup_LPC54114_cm4.s +++ /dev/null @@ -1,632 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC54114_cm4.s -; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the -; * LPC54114_cm4 -; * @version: 1.0 -; * @date: 2016-4-29 -; * -; * The Clear BSD License -; * Copyright 1997 - 2016 Freescale Semiconductor, Inc. -; * Copyright 2016 - 2017 NXP -; * -; * All rights reserved. -; * -; * Redistribution and use in source and binary forms, with or without modification, -; * are permitted (subject to the limitations in the disclaimer below) provided -; * that the following conditions are met: -; * -; * o Redistributions of source code must retain the above copyright notice, this list -; * of conditions and the following disclaimer. -; * -; * o Redistributions in binary form must reproduce the above copyright notice, this -; * list of conditions and the following disclaimer in the documentation and/or -; * other materials provided with the distribution. -; * -; * o Neither the name of the copyright holder nor the names of its -; * contributors may be used to endorse or promote products derived from this -; * software without specific prior written permission. -; * -; * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S' PATENT RIGHTS ARE GRANTED BY THIS LICENSE. -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 ; Checksum of the first 7 words - DCD 0 - DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot - DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect - DCD DMA0_IRQHandler ; DMA controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S) - DCD ADC0_SEQA_IRQHandler ; ADC0 sequence A completion. - DCD ADC0_SEQB_IRQHandler ; ADC0 sequence B completion. - DCD ADC0_THCMP_IRQHandler ; ADC0 threshold compare and error. - DCD DMIC0_IRQHandler ; Digital microphone and DMIC subsystem - DCD HWVAD0_IRQHandler ; Hardware Voice Activity Detector - DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt - DCD USB0_IRQHandler ; USB device - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD IOH_IRQHandler ; IOH - DCD MAILBOX_IRQHandler ; Mailbox interrupt (present on selected devices) - DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int - DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int - DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int - DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int - DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 - DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 - DCD Reserved54_IRQHandler ; Reserved interrupt - DCD SPIFI0_IRQHandler ; SPI flash interface - -; Code Read Protection level (CRP) -; CRP_Level: -; <0xFFFFFFFF=> Disabled -; <0x4E697370=> NO_ISP -; <0x12345678=> CRP1 -; <0x87654321=> CRP2 -; <0x43218765=> CRP3 (Are you sure?) -; -CRP_Level EQU 0xFFFFFFFF - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - AREA |.text|, CODE, READONLY - -cpu_id EQU 0xE000ED00 -cpu_ctrl EQU 0x40000800 -coproc_boot EQU 0x40000804 -coproc_stack EQU 0x40000808 - -rel_vals - DCD cpu_id, cpu_ctrl, coproc_boot, coproc_stack - DCW 0xFFF, 0xC24 - -; Reset Handler - shared for both cores -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - IF :LNOT::DEF:SLAVEBOOT - ; Both the M0+ and M4 core come via this shared startup code, - ; but the M0+ and M4 core have different vector tables. - ; Determine if the core executing this code is the master or - ; the slave and handle each core state individually. -shared_boot_entry - LDR r6, =rel_vals - MOVS r4, #0 ; Flag for slave core (0) - MOVS r5, #1 - - ; Determine which core (M0+ or M4) this code is running on - ; r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) -get_current_core_id - LDR r0, [r6, #0] - LDR r1, [r0] ; r1 = CPU ID status - LSRS r1, r1, #4 ; Right justify 12 CPU ID bits - LDRH r2, [r6, #16] ; Mask for CPU ID bits - ANDS r2, r1, r2 ; r2 = ARM COrtex CPU ID - LDRH r3, [r6, #18] ; Mask for CPU ID bits - CMP r3, r2 ; Core ID matches M4 identifier - BNE get_master_status - MOV r4, r5 ; Set flag for master core (1) - - ; Determine if M4 core is the master or slave - ; r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) -get_master_status - LDR r0, [r6, #4] - LDR r3, [r0] ; r3 = SYSCON co-processor CPU control status - ANDS r3, r3, r5 ; r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) - - ; Select boot based on selected master core and core ID -select_boot - EORS r3, r3, r4 ; r4 = (Bit 0: 0 = master, 1 = slave) - BNE slave_boot - B normal_boot - - ; Slave boot -slave_boot - LDR r0, [r6, #8] - LDR r2, [r0] ; r1 = SYSCON co-processor boot address - CMP r2, #0 ; Slave boot address = 0 (not set up)? - BEQ cpu_sleep - LDR r0, [r6, #12] - LDR r1, [r0] ; r5 = SYSCON co-processor stack address - MOV sp, r1 ; Update slave CPU stack pointer - ; Be sure to update VTOR for the slave MCU to point to the - ; slave vector table in boot memory - BX r2 ; Jump to slave boot address - - ; Slave isn't yet setup for system boot from the master - ; so sleep until the master sets it up and then reboots it -cpu_sleep - MOV sp, r5 ; Will force exception if something happens -cpu_sleep_wfi - WFI ; Sleep forever until master reboots - B cpu_sleep_wfi - ENDIF - - ; Normal boot for master/slave -normal_boot - LDR r0, =SystemInit - BLX r0 - LDR r0, =__main - BX r0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -HardFault_Handler \ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -MemManage_Handler PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP - -BusFault_Handler PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP - -UsageFault_Handler PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP - -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP - -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -WDT_BOD_IRQHandler\ - PROC - EXPORT WDT_BOD_IRQHandler [WEAK] - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - ENDP - -DMA0_IRQHandler\ - PROC - EXPORT DMA0_IRQHandler [WEAK] - LDR R0, =DMA0_DriverIRQHandler - BX R0 - ENDP - -GINT0_IRQHandler\ - PROC - EXPORT GINT0_IRQHandler [WEAK] - LDR R0, =GINT0_DriverIRQHandler - BX R0 - ENDP - -GINT1_IRQHandler\ - PROC - EXPORT GINT1_IRQHandler [WEAK] - LDR R0, =GINT1_DriverIRQHandler - BX R0 - ENDP - -PIN_INT0_IRQHandler\ - PROC - EXPORT PIN_INT0_IRQHandler [WEAK] - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - ENDP - -PIN_INT1_IRQHandler\ - PROC - EXPORT PIN_INT1_IRQHandler [WEAK] - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - ENDP - -PIN_INT2_IRQHandler\ - PROC - EXPORT PIN_INT2_IRQHandler [WEAK] - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - ENDP - -PIN_INT3_IRQHandler\ - PROC - EXPORT PIN_INT3_IRQHandler [WEAK] - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - ENDP - -UTICK0_IRQHandler\ - PROC - EXPORT UTICK0_IRQHandler [WEAK] - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - ENDP - -MRT0_IRQHandler\ - PROC - EXPORT MRT0_IRQHandler [WEAK] - LDR R0, =MRT0_DriverIRQHandler - BX R0 - ENDP - -CTIMER0_IRQHandler\ - PROC - EXPORT CTIMER0_IRQHandler [WEAK] - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - ENDP - -CTIMER1_IRQHandler\ - PROC - EXPORT CTIMER1_IRQHandler [WEAK] - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - ENDP - -SCT0_IRQHandler\ - PROC - EXPORT SCT0_IRQHandler [WEAK] - LDR R0, =SCT0_DriverIRQHandler - BX R0 - ENDP - -CTIMER3_IRQHandler\ - PROC - EXPORT CTIMER3_IRQHandler [WEAK] - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM0_IRQHandler\ - PROC - EXPORT FLEXCOMM0_IRQHandler [WEAK] - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM1_IRQHandler\ - PROC - EXPORT FLEXCOMM1_IRQHandler [WEAK] - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM2_IRQHandler\ - PROC - EXPORT FLEXCOMM2_IRQHandler [WEAK] - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM3_IRQHandler\ - PROC - EXPORT FLEXCOMM3_IRQHandler [WEAK] - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM4_IRQHandler\ - PROC - EXPORT FLEXCOMM4_IRQHandler [WEAK] - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM5_IRQHandler\ - PROC - EXPORT FLEXCOMM5_IRQHandler [WEAK] - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM6_IRQHandler\ - PROC - EXPORT FLEXCOMM6_IRQHandler [WEAK] - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM7_IRQHandler\ - PROC - EXPORT FLEXCOMM7_IRQHandler [WEAK] - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - ENDP - -ADC0_SEQA_IRQHandler\ - PROC - EXPORT ADC0_SEQA_IRQHandler [WEAK] - LDR R0, =ADC0_SEQA_DriverIRQHandler - BX R0 - ENDP - -ADC0_SEQB_IRQHandler\ - PROC - EXPORT ADC0_SEQB_IRQHandler [WEAK] - LDR R0, =ADC0_SEQB_DriverIRQHandler - BX R0 - ENDP - -ADC0_THCMP_IRQHandler\ - PROC - EXPORT ADC0_THCMP_IRQHandler [WEAK] - LDR R0, =ADC0_THCMP_DriverIRQHandler - BX R0 - ENDP - -DMIC0_IRQHandler\ - PROC - EXPORT DMIC0_IRQHandler [WEAK] - LDR R0, =DMIC0_DriverIRQHandler - BX R0 - ENDP - -HWVAD0_IRQHandler\ - PROC - EXPORT HWVAD0_IRQHandler [WEAK] - LDR R0, =HWVAD0_DriverIRQHandler - BX R0 - ENDP - -USB0_NEEDCLK_IRQHandler\ - PROC - EXPORT USB0_NEEDCLK_IRQHandler [WEAK] - LDR R0, =USB0_NEEDCLK_DriverIRQHandler - BX R0 - ENDP - -USB0_IRQHandler\ - PROC - EXPORT USB0_IRQHandler [WEAK] - LDR R0, =USB0_DriverIRQHandler - BX R0 - ENDP - -RTC_IRQHandler\ - PROC - EXPORT RTC_IRQHandler [WEAK] - LDR R0, =RTC_DriverIRQHandler - BX R0 - ENDP - -IOH_IRQHandler\ - PROC - EXPORT IOH_IRQHandler [WEAK] - LDR R0, =IOH_DriverIRQHandler - BX R0 - ENDP - -MAILBOX_IRQHandler\ - PROC - EXPORT MAILBOX_IRQHandler [WEAK] - LDR R0, =MAILBOX_DriverIRQHandler - BX R0 - ENDP - -PIN_INT4_IRQHandler\ - PROC - EXPORT PIN_INT4_IRQHandler [WEAK] - LDR R0, =PIN_INT4_DriverIRQHandler - BX R0 - ENDP - -PIN_INT5_IRQHandler\ - PROC - EXPORT PIN_INT5_IRQHandler [WEAK] - LDR R0, =PIN_INT5_DriverIRQHandler - BX R0 - ENDP - -PIN_INT6_IRQHandler\ - PROC - EXPORT PIN_INT6_IRQHandler [WEAK] - LDR R0, =PIN_INT6_DriverIRQHandler - BX R0 - ENDP - -PIN_INT7_IRQHandler\ - PROC - EXPORT PIN_INT7_IRQHandler [WEAK] - LDR R0, =PIN_INT7_DriverIRQHandler - BX R0 - ENDP - -CTIMER2_IRQHandler\ - PROC - EXPORT CTIMER2_IRQHandler [WEAK] - LDR R0, =CTIMER2_DriverIRQHandler - BX R0 - ENDP - -CTIMER4_IRQHandler\ - PROC - EXPORT CTIMER4_IRQHandler [WEAK] - LDR R0, =CTIMER4_DriverIRQHandler - BX R0 - ENDP - -Reserved54_IRQHandler\ - PROC - EXPORT Reserved54_IRQHandler [WEAK] - LDR R0, =Reserved54_DriverIRQHandler - BX R0 - ENDP - -SPIFI0_IRQHandler\ - PROC - EXPORT SPIFI0_IRQHandler [WEAK] - LDR R0, =SPIFI0_DriverIRQHandler - BX R0 - ENDP - -Default_Handler PROC - EXPORT WDT_BOD_DriverIRQHandler [WEAK] - EXPORT DMA0_DriverIRQHandler [WEAK] - EXPORT GINT0_DriverIRQHandler [WEAK] - EXPORT GINT1_DriverIRQHandler [WEAK] - EXPORT PIN_INT0_DriverIRQHandler [WEAK] - EXPORT PIN_INT1_DriverIRQHandler [WEAK] - EXPORT PIN_INT2_DriverIRQHandler [WEAK] - EXPORT PIN_INT3_DriverIRQHandler [WEAK] - EXPORT UTICK0_DriverIRQHandler [WEAK] - EXPORT MRT0_DriverIRQHandler [WEAK] - EXPORT CTIMER0_DriverIRQHandler [WEAK] - EXPORT CTIMER1_DriverIRQHandler [WEAK] - EXPORT SCT0_DriverIRQHandler [WEAK] - EXPORT CTIMER3_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM0_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM1_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM2_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM3_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM4_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM5_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM6_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM7_DriverIRQHandler [WEAK] - EXPORT ADC0_SEQA_DriverIRQHandler [WEAK] - EXPORT ADC0_SEQB_DriverIRQHandler [WEAK] - EXPORT ADC0_THCMP_DriverIRQHandler [WEAK] - EXPORT DMIC0_DriverIRQHandler [WEAK] - EXPORT HWVAD0_DriverIRQHandler [WEAK] - EXPORT USB0_NEEDCLK_DriverIRQHandler [WEAK] - EXPORT USB0_DriverIRQHandler [WEAK] - EXPORT RTC_DriverIRQHandler [WEAK] - EXPORT IOH_DriverIRQHandler [WEAK] - EXPORT MAILBOX_DriverIRQHandler [WEAK] - EXPORT PIN_INT4_DriverIRQHandler [WEAK] - EXPORT PIN_INT5_DriverIRQHandler [WEAK] - EXPORT PIN_INT6_DriverIRQHandler [WEAK] - EXPORT PIN_INT7_DriverIRQHandler [WEAK] - EXPORT CTIMER2_DriverIRQHandler [WEAK] - EXPORT CTIMER4_DriverIRQHandler [WEAK] - EXPORT Reserved54_DriverIRQHandler [WEAK] - EXPORT SPIFI0_DriverIRQHandler [WEAK] - -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_SEQA_DriverIRQHandler -ADC0_SEQB_DriverIRQHandler -ADC0_THCMP_DriverIRQHandler -DMIC0_DriverIRQHandler -HWVAD0_DriverIRQHandler -USB0_NEEDCLK_DriverIRQHandler -USB0_DriverIRQHandler -RTC_DriverIRQHandler -IOH_DriverIRQHandler -MAILBOX_DriverIRQHandler -PIN_INT4_DriverIRQHandler -PIN_INT5_DriverIRQHandler -PIN_INT6_DriverIRQHandler -PIN_INT7_DriverIRQHandler -CTIMER2_DriverIRQHandler -CTIMER4_DriverIRQHandler -Reserved54_DriverIRQHandler -SPIFI0_DriverIRQHandler - - B . - - ENDP - - - ALIGN - - - END - diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_i2c_cmsis.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_i2c_cmsis.c deleted file mode 100644 index 21bd2ca1262..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_i2c_cmsis.c +++ /dev/null @@ -1,2265 +0,0 @@ -/* - * Copyright (c) 2013-2016 ARM Limited. All rights reserved. - * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. - * Copyright 2016-2017 NXP. Not a Contribution. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#include "fsl_i2c_cmsis.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c_cmsis" -#endif - - -#if (RTE_I2C0 || RTE_I2C1 || RTE_I2C2 || RTE_I2C3 || RTE_I2C4 || RTE_I2C5 || RTE_I2C6 || RTE_I2C7 || RTE_I2C8 || \ - RTE_I2C9) - -#define ARM_I2C_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) - -/* - * ARMCC does not support split the data section automatically, so the driver - * needs to split the data to separate sections explicitly, to reduce codesize. - */ -#if defined(__CC_ARM) -#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) -#endif - -typedef const struct _cmsis_i2c_resource -{ - I2C_Type *base; /*!< I2C peripheral base address. */ - uint32_t (*GetFreq)(void); /*!< Function to get the clock frequency. */ - -} cmsis_i2c_resource_t; - -typedef union _cmsis_i2c_handle -{ - i2c_master_handle_t master_handle; /*!< master Interupt transfer handle. */ - i2c_slave_handle_t slave_handle; /*!< slave Interupt transfer handle. */ -} cmsis_i2c_handle_t; - -typedef struct _cmsis_i2c_interrupt_driver_state -{ - cmsis_i2c_resource_t *resource; /*!< Basic I2C resource. */ - cmsis_i2c_handle_t *handle; - ARM_I2C_SignalEvent_t cb_event; /*!< Callback function. */ - uint8_t flags; /*!< Control and state flags. */ -} cmsis_i2c_interrupt_driver_state_t; - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) -typedef const struct _cmsis_i2c_dma_resource -{ - DMA_Type *i2cDmaBase; /*!< DMA peripheral base address for i2c. */ - uint32_t i2cDmaChannel; /*!< DMA channel for i2c. */ -} cmsis_i2c_dma_resource_t; - -typedef struct _cmsis_i2c_dma_driver_state -{ - cmsis_i2c_resource_t *resource; /*!< i2c basic resource. */ - cmsis_i2c_dma_resource_t *dmaResource; /*!< i2c DMA resource. */ - i2c_master_dma_handle_t *master_dma_handle; /*!< i2c DMA transfer handle. */ - dma_handle_t *dmaHandle; /*!< DMA i2c handle. */ - uint8_t flags; /*!< Control and state flags. */ -} cmsis_i2c_dma_driver_state_t; -#endif - -static const ARM_DRIVER_VERSION s_i2cDriverVersion = {ARM_I2C_API_VERSION, ARM_I2C_DRV_VERSION}; - -static const ARM_I2C_CAPABILITIES s_i2cDriverCapabilities = { - 0, /*< supports 10-bit addressing*/ -}; - -extern uint32_t I2C_GetInstance(I2C_Type *base); - -static ARM_DRIVER_VERSION I2Cx_GetVersion(void) -{ - return s_i2cDriverVersion; -} - -static ARM_I2C_CAPABILITIES I2Cx_GetCapabilities(void) -{ - return s_i2cDriverCapabilities; -} - -#endif - -#if (RTE_I2C0_DMA_EN || RTE_I2C1_DMA_EN || RTE_I2C2_DMA_EN || RTE_I2C3_DMA_EN || RTE_I2C4_DMA_EN || RTE_I2C5_DMA_EN || \ - RTE_I2C6_DMA_EN || RTE_I2C7_DMA_EN || RTE_I2C8_DMA_EN || RTE_I2C9_DMA_EN) - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) -void KSDK_I2C_MASTER_DmaCallback(I2C_Type *base, i2c_master_dma_handle_t *handle, status_t status, void *userData) -{ - uint32_t event; - - if (status == kStatus_Success) /* Occurs after Master Transmit/Receive operation has finished. */ - { - event = ARM_I2C_EVENT_TRANSFER_DONE; - } - - if (userData) - { - ((ARM_I2C_SignalEvent_t)userData)(event); - } -} - -static int32_t I2C_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event, cmsis_i2c_dma_driver_state_t *i2c) -{ - if (!(i2c->flags & I2C_FLAG_INIT)) - { - DMA_EnableChannel(i2c->dmaResource->i2cDmaBase, i2c->dmaResource->i2cDmaChannel); - DMA_CreateHandle(i2c->dmaHandle, i2c->dmaResource->i2cDmaBase, i2c->dmaResource->i2cDmaChannel); - - I2C_MasterTransferCreateHandleDMA(i2c->resource->base, i2c->master_dma_handle, KSDK_I2C_MASTER_DmaCallback, - (void *)cb_event, i2c->dmaHandle); - i2c->flags = I2C_FLAG_INIT; - } - return ARM_DRIVER_OK; -} - -int32_t I2C_Master_DmaUninitialize(cmsis_i2c_dma_driver_state_t *i2c) -{ - i2c->flags = I2C_FLAG_UNINIT; - return ARM_DRIVER_OK; -} - -int32_t I2C_Master_DmaTransmit( - uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_dma_driver_state_t *i2c) -{ - int32_t status; - int32_t ret; - i2c_master_transfer_t masterXfer; - - /* Check if the I2C bus is idle - if not return busy status. */ - if (i2c->master_dma_handle->state != 0) - { - return ARM_DRIVER_ERROR_BUSY; - } - - masterXfer.slaveAddress = addr; /*7-bit slave address.*/ - masterXfer.direction = kI2C_Write; /*Transfer direction.*/ - masterXfer.subaddress = 0; /*Sub address*/ - masterXfer.subaddressSize = 0; /*Size of command buffer.*/ - masterXfer.data = (uint8_t *)data; /*Transfer buffer.*/ - masterXfer.dataSize = num; /*Transfer size.*/ - masterXfer.flags = kI2C_TransferDefaultFlag; /*Transfer flag which controls the transfer.*/ - - if (xfer_pending) - { - masterXfer.flags |= kI2C_TransferNoStopFlag; - } - - status = I2C_MasterTransferDMA(i2c->resource->base, i2c->master_dma_handle, &masterXfer); - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_I2C_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -int32_t I2C_Master_DmaReceive( - uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_dma_driver_state_t *i2c) -{ - int32_t status; - int32_t ret; - i2c_master_transfer_t masterXfer; - - /* Check if the I2C bus is idle - if not return busy status. */ - if (i2c->master_dma_handle->state != 0) - { - return ARM_DRIVER_ERROR_BUSY; - } - - masterXfer.slaveAddress = addr; /*7-bit slave address.*/ - masterXfer.direction = kI2C_Read; /*Transfer direction.*/ - masterXfer.subaddress = 0; /*Sub address*/ - masterXfer.subaddressSize = 0; /*Size of command buffer.*/ - masterXfer.data = data; /*Transfer buffer.*/ - masterXfer.dataSize = num; /*Transfer size.*/ - masterXfer.flags = kI2C_TransferDefaultFlag; /*Transfer flag which controls the transfer.*/ - - if (xfer_pending) - { - masterXfer.flags |= kI2C_TransferNoStopFlag; - } - - status = I2C_MasterTransferDMA(i2c->resource->base, i2c->master_dma_handle, &masterXfer); - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_I2C_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -int32_t I2C_Master_DmaGetDataCount(cmsis_i2c_dma_driver_state_t *i2c) -{ - size_t cnt; /*the number of currently transferred data bytes*/ - - I2C_MasterTransferGetCountDMA(i2c->resource->base, i2c->master_dma_handle, &cnt); - return cnt; -} - -int32_t I2C_Master_DmaControl(uint32_t control, uint32_t arg, cmsis_i2c_dma_driver_state_t *i2c) -{ - uint32_t baudRate_Bps; - - switch (control) - { - /* Not supported */ - case ARM_I2C_OWN_ADDRESS: - return ARM_DRIVER_ERROR_UNSUPPORTED; - /*Set Bus Speed; arg = bus speed*/ - case ARM_I2C_BUS_SPEED: - switch (arg) - { - case ARM_I2C_BUS_SPEED_STANDARD: - baudRate_Bps = 100000; - break; - case ARM_I2C_BUS_SPEED_FAST: - baudRate_Bps = 400000; - break; - case ARM_I2C_BUS_SPEED_FAST_PLUS: - baudRate_Bps = 1000000; - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - I2C_MasterSetBaudRate(i2c->resource->base, baudRate_Bps, i2c->resource->GetFreq()); - return ARM_DRIVER_OK; - /* Not supported */ - case ARM_I2C_BUS_CLEAR: - return ARM_DRIVER_ERROR_UNSUPPORTED; - /*Aborts the data transfer when Master for Transmit or Receive*/ - case ARM_I2C_ABORT_TRANSFER: - /*disable dma*/ - I2C_MasterTransferAbortDMA(i2c->resource->base, i2c->master_dma_handle); - - i2c->master_dma_handle->transferCount = 0; - i2c->master_dma_handle->transfer.data = NULL; - i2c->master_dma_handle->transfer.dataSize = 0; - return ARM_DRIVER_OK; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -int32_t I2C_Master_DmaPowerControl(ARM_POWER_STATE state, cmsis_i2c_dma_driver_state_t *i2c) -{ - switch (state) - { - /*terminates any pending data transfers, disable i2c moduole and i2c clock and related dma*/ - case ARM_POWER_OFF: - if (i2c->flags & I2C_FLAG_POWER) - { - I2C_Master_DmaControl(ARM_I2C_ABORT_TRANSFER, 0, i2c); - I2C_MasterDeinit(i2c->resource->base); - DMA_DisableChannel(i2c->dmaResource->i2cDmaBase, i2c->dmaResource->i2cDmaChannel); - i2c->flags = I2C_FLAG_INIT; - } - - return ARM_DRIVER_OK; - /* Not supported */ - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - /*enable i2c moduole and i2c clock*/ - case ARM_POWER_FULL: - if (i2c->flags == I2C_FLAG_UNINIT) - { - return ARM_DRIVER_ERROR; - } - - if (i2c->flags & I2C_FLAG_POWER) - { - /* Driver already powered */ - break; - } - FLEXCOMM_Init(i2c->resource->base, FLEXCOMM_PERIPH_I2C); - I2C_MasterEnable(i2c->resource->base, true); - i2c->flags |= I2C_FLAG_POWER; - - return ARM_DRIVER_OK; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - return ARM_DRIVER_OK; -} - -ARM_I2C_STATUS I2C_Master_DmaGetStatus(cmsis_i2c_dma_driver_state_t *i2c) -{ - ARM_I2C_STATUS stat; - uint32_t ksdk_i2c_status = I2C_GetStatusFlags(i2c->resource->base); - - stat.busy = !(ksdk_i2c_status & I2C_STAT_MSTPENDING_MASK); /*Busy flag.*/ - stat.direction = i2c->master_dma_handle->transfer.direction; /*Direction: 0=Transmitter, 1=Receiver.*/ - stat.mode = 1; /*Mode: 0=Slave, 1=Master.*/ - stat.arbitration_lost = !(!(ksdk_i2c_status & I2C_STAT_MSTARBLOSS_MASK)); - /*Master lost arbitration (cleared on start of next Master operation)*/ - - return stat; -} - -#endif - -#endif - -#if ((RTE_I2C0 && !RTE_I2C0_DMA_EN) || (RTE_I2C1 && !RTE_I2C1_DMA_EN) || (RTE_I2C2 && !RTE_I2C2_DMA_EN) || \ - (RTE_I2C3 && !RTE_I2C3_DMA_EN) || (RTE_I2C4 && !RTE_I2C4_DMA_EN) || (RTE_I2C5 && !RTE_I2C5_DMA_EN) || \ - (RTE_I2C6 && !RTE_I2C6_DMA_EN) || (RTE_I2C7 && !RTE_I2C7_DMA_EN) || (RTE_I2C8 && !RTE_I2C8_DMA_EN) || \ - (RTE_I2C9 && !RTE_I2C9_DMA_EN)) - -static void KSDK_I2C_SLAVE_InterruptCallback(I2C_Type *base, volatile i2c_slave_transfer_t *xfer, void *param) -{ - uint32_t event; - - switch (xfer->event) - { - case kI2C_SlaveCompletionEvent: /* Occurs after Slave Transmit/Receive operation has finished. */ - event = ARM_I2C_EVENT_TRANSFER_DONE; - break; - default: - event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE; - break; - } - - if (param) - { - ((ARM_I2C_SignalEvent_t)param)(event); - } -} - -static void KSDK_I2C_MASTER_InterruptCallback(I2C_Type *base, - i2c_master_handle_t *handle, - status_t status, - void *userData) -{ - uint32_t event; - - switch (status) - { - case kStatus_Success: /* Occurs after Master Transmit/Receive operation has finished. */ - event = ARM_I2C_EVENT_TRANSFER_DONE; - break; - case kStatus_I2C_ArbitrationLost: /*Occurs in master mode when arbitration is lost.*/ - event = ARM_I2C_EVENT_ARBITRATION_LOST; - break; - default: - event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE; - break; - } - - /* User data is actually CMSIS driver callback. */ - if (userData) - { - ((ARM_I2C_SignalEvent_t)userData)(event); - } -} - -static int32_t I2C_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event, cmsis_i2c_interrupt_driver_state_t *i2c) -{ - if (!(i2c->flags & I2C_FLAG_INIT)) - { - i2c->cb_event = cb_event; /* cb_event is CMSIS driver callback. */ - i2c->flags = I2C_FLAG_INIT; - } - - return ARM_DRIVER_OK; -} - -static int32_t I2C_InterruptUninitialize(cmsis_i2c_interrupt_driver_state_t *i2c) -{ - i2c->flags = I2C_FLAG_UNINIT; - return ARM_DRIVER_OK; -} - -int32_t I2C_Master_InterruptTransmit( - uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_interrupt_driver_state_t *i2c) -{ - int32_t status; - int32_t ret; - i2c_master_transfer_t masterXfer; - - /* Check if the I2C bus is idle - if not return busy status. */ - if (i2c->handle->master_handle.state != 0) - { - return ARM_DRIVER_ERROR_BUSY; - } - - I2C_MasterEnable(i2c->resource->base, true); - - /*create master_handle*/ - I2C_MasterTransferCreateHandle(i2c->resource->base, &(i2c->handle->master_handle), - KSDK_I2C_MASTER_InterruptCallback, (void *)i2c->cb_event); - - masterXfer.slaveAddress = addr; /*7-bit slave address.*/ - masterXfer.direction = kI2C_Write; /*Transfer direction.*/ - masterXfer.subaddress = (uint32_t)NULL; /*Sub address*/ - masterXfer.subaddressSize = 0; /*Size of command buffer.*/ - masterXfer.data = (uint8_t *)data; /*Transfer buffer.*/ - masterXfer.dataSize = num; /*Transfer size.*/ - masterXfer.flags = kI2C_TransferDefaultFlag; /*Transfer flag which controls the transfer.*/ - - if (xfer_pending) - { - masterXfer.flags |= kI2C_TransferNoStopFlag; - } - - status = I2C_MasterTransferNonBlocking(i2c->resource->base, &(i2c->handle->master_handle), &masterXfer); - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_I2C_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -int32_t I2C_Master_InterruptReceive( - uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_interrupt_driver_state_t *i2c) -{ - int32_t status; - int32_t ret; - i2c_master_transfer_t masterXfer; - - /* Check if the I2C bus is idle - if not return busy status. */ - if (i2c->handle->master_handle.state != 0) - { - return ARM_DRIVER_ERROR_BUSY; - } - - I2C_MasterEnable(i2c->resource->base, true); - - /*create master_handle*/ - I2C_MasterTransferCreateHandle(i2c->resource->base, &(i2c->handle->master_handle), - KSDK_I2C_MASTER_InterruptCallback, (void *)i2c->cb_event); - - masterXfer.slaveAddress = addr; /*7-bit slave address.*/ - masterXfer.direction = kI2C_Read; /*Transfer direction.*/ - masterXfer.subaddress = (uint32_t)NULL; /*Sub address*/ - masterXfer.subaddressSize = 0; /*Size of command buffer.*/ - masterXfer.data = data; /*Transfer buffer.*/ - masterXfer.dataSize = num; /*Transfer size.*/ - masterXfer.flags = kI2C_TransferDefaultFlag; /*Transfer flag which controls the transfer.*/ - - if (xfer_pending) - { - masterXfer.flags |= kI2C_TransferNoStopFlag; - } - - status = I2C_MasterTransferNonBlocking(i2c->resource->base, &(i2c->handle->master_handle), &masterXfer); - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_I2C_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -int32_t I2C_Slave_InterruptTransmit(const uint8_t *data, uint32_t num, cmsis_i2c_interrupt_driver_state_t *i2c) -{ - int32_t status; - int32_t ret; - - /* set Slave enable */ - I2C_SlaveEnable(i2c->resource->base, true); - - /*create slave_handle*/ - I2C_SlaveTransferCreateHandle(i2c->resource->base, &(i2c->handle->slave_handle), KSDK_I2C_SLAVE_InterruptCallback, - (void *)i2c->cb_event); - - status = I2C_SlaveTransferNonBlocking(i2c->resource->base, &(i2c->handle->slave_handle), kI2C_SlaveCompletionEvent); - - i2c->handle->slave_handle.transfer.txData = - (uint8_t *)data; /*Pointer to buffer with data to transmit to I2C Master*/ - i2c->handle->slave_handle.transfer.txSize = num; /*Number of data bytes to transmit*/ - i2c->handle->slave_handle.transfer.transferredCount = - 0; /*Number of bytes actually transferred since start or last repeated start. */ - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_I2C_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -int32_t I2C_Slave_InterruptReceive(uint8_t *data, uint32_t num, cmsis_i2c_interrupt_driver_state_t *i2c) -{ - int32_t status; - int32_t ret; - - /* set Slave enable */ - I2C_SlaveEnable(i2c->resource->base, true); - - /*create slave_handle*/ - I2C_SlaveTransferCreateHandle(i2c->resource->base, &(i2c->handle->slave_handle), KSDK_I2C_SLAVE_InterruptCallback, - (void *)i2c->cb_event); - - status = I2C_SlaveTransferNonBlocking(i2c->resource->base, &(i2c->handle->slave_handle), kI2C_SlaveCompletionEvent); - - i2c->handle->slave_handle.transfer.rxData = data; /*Pointer to buffer with data to transmit to I2C Master*/ - i2c->handle->slave_handle.transfer.rxSize = num; /*Number of data bytes to transmit*/ - i2c->handle->slave_handle.transfer.transferredCount = - 0; /*Number of bytes actually transferred since start or last repeated start. */ - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_I2C_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -int32_t I2C_InterruptGetDataCount(cmsis_i2c_interrupt_driver_state_t *i2c) -{ - uint32_t cnt = 0; /*the number of currently transferred data bytes*/ - - if (i2c->resource->base->CFG & I2C_CFG_MSTEN_MASK) - { - cnt = i2c->handle->master_handle.transferCount; - } - else - { - cnt = i2c->handle->slave_handle.transfer.transferredCount; - } - - return cnt; -} - -int32_t I2C_InterruptControl(uint32_t control, uint32_t arg, cmsis_i2c_interrupt_driver_state_t *i2c) -{ - uint32_t baudRate_Bps; - - switch (control) - { - /*Set Own Slave Address; arg = slave address*/ - case ARM_I2C_OWN_ADDRESS: - I2C_SlaveSetAddress(i2c->resource->base, kI2C_SlaveAddressRegister0, arg, false); - /* set Slave address 0 qual */ - i2c->resource->base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(0) | I2C_SLVQUAL0_SLVQUAL0(0); - return ARM_DRIVER_OK; - /*Set Bus Speed; arg = bus speed*/ - case ARM_I2C_BUS_SPEED: - switch (arg) - { - case ARM_I2C_BUS_SPEED_STANDARD: - baudRate_Bps = 100000; - break; - case ARM_I2C_BUS_SPEED_FAST: - baudRate_Bps = 400000; - break; - case ARM_I2C_BUS_SPEED_FAST_PLUS: - baudRate_Bps = 1000000; - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - I2C_MasterSetBaudRate(i2c->resource->base, baudRate_Bps, i2c->resource->GetFreq()); - return ARM_DRIVER_OK; - // Not supported - case ARM_I2C_BUS_CLEAR: - return ARM_DRIVER_ERROR_UNSUPPORTED; - /*Aborts the data transfer between Master and Slave for Transmit or Receive*/ - case ARM_I2C_ABORT_TRANSFER: - if (i2c->resource->base->CFG & I2C_CFG_MSTEN_MASK) - { - /*disable master interrupt and send STOP signal*/ - I2C_MasterTransferAbort(i2c->resource->base, &(i2c->handle->master_handle)); - - i2c->handle->master_handle.transferCount = 0; - i2c->handle->master_handle.transfer.data = NULL; - i2c->handle->master_handle.transfer.dataSize = 0; - } - /*if slave receive*/ - if ((i2c->resource->base->CFG & I2C_CFG_SLVEN_MASK) && - ((i2c->handle->slave_handle.slaveFsm) == kI2C_SlaveFsmReceive)) - { - /*disable slave interrupt*/ - I2C_SlaveTransferAbort(i2c->resource->base, &(i2c->handle->slave_handle)); - - i2c->handle->slave_handle.transfer.transferredCount = 0; - i2c->handle->slave_handle.transfer.txData = NULL; - i2c->handle->slave_handle.transfer.rxData = NULL; - } - return ARM_DRIVER_OK; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -static int32_t I2C_InterruptPowerControl(ARM_POWER_STATE state, cmsis_i2c_interrupt_driver_state_t *i2c) -{ - switch (state) - { - /*terminates any pending data transfers, disable i2c moduole and i2c clock*/ - case ARM_POWER_OFF: - if (i2c->flags & I2C_FLAG_POWER) - { - I2C_InterruptControl(ARM_I2C_ABORT_TRANSFER, 0, i2c); - I2C_MasterDeinit(i2c->resource->base); - I2C_SlaveDeinit(i2c->resource->base); - i2c->flags = I2C_FLAG_INIT; - } - - return ARM_DRIVER_OK; - /* Not supported */ - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - /*enable i2c moduole and i2c clock*/ - case ARM_POWER_FULL: - if (i2c->flags == I2C_FLAG_UNINIT) - { - return ARM_DRIVER_ERROR; - } - - if (i2c->flags & I2C_FLAG_POWER) - { - /* Driver already powered */ - break; - } - FLEXCOMM_Init(i2c->resource->base, FLEXCOMM_PERIPH_I2C); - i2c->flags |= I2C_FLAG_POWER; - - return ARM_DRIVER_OK; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - return ARM_DRIVER_OK; -} - -ARM_I2C_STATUS I2C_InterruptGetStatus(cmsis_i2c_interrupt_driver_state_t *i2c) -{ - ARM_I2C_STATUS stat; - uint32_t ksdk_i2c_status = I2C_GetStatusFlags(i2c->resource->base); - - if (i2c->resource->base->CFG & I2C_CFG_MSTEN_MASK) - { - stat.busy = !(ksdk_i2c_status & I2C_STAT_MSTPENDING_MASK); /*Busy flag.*/ - stat.direction = i2c->handle->master_handle.transfer.direction; /*Direction: 0=Transmitter, 1=Receiver.*/ - stat.mode = 1; /*Mode: 0=Slave, 1=Master.*/ - stat.arbitration_lost = !(!(ksdk_i2c_status & I2C_STAT_MSTARBLOSS_MASK)); - /*Master lost arbitration (cleared on start of next Master operation)*/ - } - - if (i2c->resource->base->CFG & I2C_CFG_SLVEN_MASK) - { - stat.busy = !(ksdk_i2c_status & I2C_STAT_SLVPENDING_MASK); /*Busy flag.*/ - if ((i2c->handle->slave_handle.slaveFsm) == kI2C_SlaveFsmReceive) - { - stat.direction = 1; /*Direction: 0=Transmitter, 1=Receiver.*/ - } - else - { - stat.direction = 0; /*Direction: 0=Transmitter, 1=Receiver.*/ - } - stat.mode = 0; /*Mode: 0=Slave, 1=Master.*/ - } - - return stat; -} - -#endif - -#if defined(I2C0) && RTE_I2C0 -/* User needs to provide the implementation for I2C0_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t I2C0_GetFreq(void); -extern void I2C0_InitPins(void); -extern void I2C0_DeinitPins(void); - -cmsis_i2c_resource_t I2C0_Resource = {I2C0, I2C0_GetFreq}; - -#if RTE_I2C0_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C0_DmaResource = {RTE_I2C0_Master_DMA_BASE, RTE_I2C0_Master_DMA_CH}; - -i2c_master_dma_handle_t I2C0_DmaHandle; -dma_handle_t I2C0_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c0_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C0_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C0_DmaDriverState = { -#endif - &I2C0_Resource, &I2C0_DmaResource, &I2C0_DmaHandle, &I2C0_DmaTxRxHandle, -}; - -static int32_t I2C0_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C0_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C0_DmaDriverState); -} - -int32_t I2C0_Master_DmaUninitialize(void) -{ - I2C0_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C0_DmaDriverState); -} - -int32_t I2C0_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C0_DmaDriverState); -} - -int32_t I2C0_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C0_DmaDriverState); -} - -int32_t I2C0_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C0_DmaDriverState); -} - -int32_t I2C0_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C0_DmaDriverState); -} - -int32_t I2C0_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C0_DmaDriverState); -} - -ARM_I2C_STATUS I2C0_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C0_DmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C0_handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c0_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C0_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C0_InterruptDriverState = { -#endif - &I2C0_Resource, &I2C0_handle, - -}; - -static int32_t I2C0_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C0_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C0_InterruptDriverState); -} - -static int32_t I2C0_InterruptUninitialize(void) -{ - I2C0_DeinitPins(); - return I2C_InterruptUninitialize(&I2C0_InterruptDriverState); -} - -static int32_t I2C0_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C0_InterruptDriverState); -} - -int32_t I2C0_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C0_InterruptDriverState); -} - -int32_t I2C0_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C0_InterruptDriverState); -} - -int32_t I2C0_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C0_InterruptDriverState); -} - -int32_t I2C0_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C0_InterruptDriverState); -} - -int32_t I2C0_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C0_InterruptDriverState); -} - -int32_t I2C0_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C0_InterruptDriverState); -} - -ARM_I2C_STATUS I2C0_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C0_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C0 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C0_DMA_EN - I2C0_Master_DmaInitialize, I2C0_Master_DmaUninitialize, I2C0_Master_DmaPowerControl, - I2C0_Master_DmaTransmit, I2C0_Master_DmaReceive, NULL, NULL, I2C0_Master_DmaGetDataCount, - I2C0_Master_DmaControl, I2C0_Master_DmaGetStatus -#else - I2C0_InterruptInitialize, I2C0_InterruptUninitialize, I2C0_InterruptPowerControl, - I2C0_Master_InterruptTransmit, I2C0_Master_InterruptReceive, I2C0_Slave_InterruptTransmit, - I2C0_Slave_InterruptReceive, I2C0_InterruptGetDataCount, I2C0_InterruptControl, - I2C0_InterruptGetStatus -#endif -}; - -#endif - -#if defined(I2C1) && RTE_I2C1 - -/* User needs to provide the implementation for I2C1_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t I2C1_GetFreq(void); -extern void I2C1_InitPins(void); -extern void I2C1_DeinitPins(void); - -cmsis_i2c_resource_t I2C1_Resource = {I2C1, I2C1_GetFreq}; - -#if RTE_I2C1_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C1_DmaResource = {RTE_I2C1_Master_DMA_BASE, RTE_I2C1_Master_DMA_CH}; - -i2c_master_dma_handle_t I2C1_DmaHandle; -dma_handle_t I2C1_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c1_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C1_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C1_DmaDriverState = { -#endif - &I2C1_Resource, &I2C1_DmaResource, &I2C1_DmaHandle, &I2C1_DmaTxRxHandle, -}; - -static int32_t I2C1_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C1_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C1_DmaDriverState); -} - -int32_t I2C1_Master_DmaUninitialize(void) -{ - I2C1_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C1_DmaDriverState); -} - -int32_t I2C1_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C1_DmaDriverState); -} - -int32_t I2C1_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C1_DmaDriverState); -} - -int32_t I2C1_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C1_DmaDriverState); -} - -int32_t I2C1_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C1_DmaDriverState); -} - -int32_t I2C1_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C1_DmaDriverState); -} - -ARM_I2C_STATUS I2C1_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C1_DmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C1_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c1_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C1_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C1_InterruptDriverState = { -#endif - &I2C1_Resource, &I2C1_Handle, -}; - -static int32_t I2C1_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C1_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C1_InterruptDriverState); -} - -static int32_t I2C1_InterruptUninitialize(void) -{ - I2C1_DeinitPins(); - return I2C_InterruptUninitialize(&I2C1_InterruptDriverState); -} - -static int32_t I2C1_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C1_InterruptDriverState); -} - -int32_t I2C1_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C1_InterruptDriverState); -} - -int32_t I2C1_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C1_InterruptDriverState); -} - -int32_t I2C1_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C1_InterruptDriverState); -} - -int32_t I2C1_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C1_InterruptDriverState); -} - -int32_t I2C1_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C1_InterruptDriverState); -} - -int32_t I2C1_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C1_InterruptDriverState); -} - -ARM_I2C_STATUS I2C1_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C1_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C1 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C1_DMA_EN - I2C1_Master_DmaInitialize, I2C1_Master_DmaUninitialize, I2C1_Master_DmaPowerControl, - I2C1_Master_DmaTransmit, I2C1_Master_DmaReceive, NULL, NULL, I2C1_Master_DmaGetDataCount, - I2C1_Master_DmaControl, I2C1_Master_DmaGetStatus -#else - I2C1_InterruptInitialize, I2C1_InterruptUninitialize, I2C1_InterruptPowerControl, - I2C1_Master_InterruptTransmit, I2C1_Master_InterruptReceive, I2C1_Slave_InterruptTransmit, - I2C1_Slave_InterruptReceive, I2C1_InterruptGetDataCount, I2C1_InterruptControl, - I2C1_InterruptGetStatus -#endif -}; - -#endif - -#if defined(I2C2) && RTE_I2C2 - -/* User needs to provide the implementation for I2C2_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t I2C2_GetFreq(void); -extern void I2C2_InitPins(void); -extern void I2C2_DeinitPins(void); - -cmsis_i2c_resource_t I2C2_Resource = {I2C2, I2C2_GetFreq}; - -#if RTE_I2C2_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C2_DmaResource = {RTE_I2C2_Master_DMA_BASE, RTE_I2C2_Master_DMA_CH}; - -i2c_master_dma_handle_t I2C2_DmaHandle; -dma_handle_t I2C2_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c2_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C2_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C2_DmaDriverState = { -#endif - &I2C2_Resource, &I2C2_DmaResource, &I2C2_DmaHandle, &I2C2_DmaTxRxHandle, -}; - -static int32_t I2C2_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C2_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C2_DmaDriverState); -} - -int32_t I2C2_Master_DmaUninitialize(void) -{ - I2C2_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C2_DmaDriverState); -} - -int32_t I2C2_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C2_DmaDriverState); -} - -int32_t I2C2_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C2_DmaDriverState); -} - -int32_t I2C2_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C2_DmaDriverState); -} - -int32_t I2C2_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C2_DmaDriverState); -} - -int32_t I2C2_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C2_DmaDriverState); -} - -ARM_I2C_STATUS I2C2_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C2_DmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C2_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c2_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C2_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C2_InterruptDriverState = { -#endif - &I2C2_Resource, &I2C2_Handle, - -}; - -static int32_t I2C2_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C2_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C2_InterruptDriverState); -} - -static int32_t I2C2_InterruptUninitialize(void) -{ - I2C2_DeinitPins(); - return I2C_InterruptUninitialize(&I2C2_InterruptDriverState); -} - -static int32_t I2C2_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C2_InterruptDriverState); -} - -int32_t I2C2_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C2_InterruptDriverState); -} - -int32_t I2C2_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C2_InterruptDriverState); -} - -int32_t I2C2_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C2_InterruptDriverState); -} - -int32_t I2C2_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C2_InterruptDriverState); -} - -int32_t I2C2_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C2_InterruptDriverState); -} - -int32_t I2C2_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C2_InterruptDriverState); -} - -ARM_I2C_STATUS I2C2_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C2_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C2 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C2_DMA_EN - I2C2_Master_DmaInitialize, I2C2_Master_DmaUninitialize, I2C2_Master_DmaPowerControl, - I2C2_Master_DmaTransmit, I2C2_Master_DmaReceive, NULL, NULL, I2C2_Master_DmaGetDataCount, - I2C2_Master_DmaControl, I2C2_Master_DmaGetStatus -#else - I2C2_InterruptInitialize, I2C2_InterruptUninitialize, I2C2_InterruptPowerControl, - I2C2_Master_InterruptTransmit, I2C2_Master_InterruptReceive, I2C2_Slave_InterruptTransmit, - I2C2_Slave_InterruptReceive, I2C2_InterruptGetDataCount, I2C2_InterruptControl, - I2C2_InterruptGetStatus -#endif -}; - -#endif - -#if defined(I2C3) && RTE_I2C3 - -/* User needs to provide the implementation for I2C3_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t I2C3_GetFreq(void); -extern void I2C3_InitPins(void); -extern void I2C3_DeinitPins(void); - -cmsis_i2c_resource_t I2C3_Resource = {I2C3, I2C3_GetFreq}; - -#if RTE_I2C3_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C3_DmaResource = {RTE_I2C3_Master_DMA_BASE, RTE_I2C3_Master_DMA_CH}; - -i2c_master_dma_handle_t I2C3_DmaHandle; -dma_handle_t I2C3_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c3_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C3_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C3_DmaDriverState = { -#endif - &I2C3_Resource, &I2C3_DmaResource, &I2C3_DmaHandle, &I2C3_DmaTxRxHandle, -}; - -static int32_t I2C3_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C3_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C3_DmaDriverState); -} - -int32_t I2C3_Master_DmaUninitialize(void) -{ - I2C3_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C3_DmaDriverState); -} - -int32_t I2C3_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C3_DmaDriverState); -} - -int32_t I2C3_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C3_DmaDriverState); -} - -int32_t I2C3_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C3_DmaDriverState); -} - -int32_t I2C3_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C3_DmaDriverState); -} - -int32_t I2C3_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C3_DmaDriverState); -} - -ARM_I2C_STATUS I2C3_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C3_DmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C3_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c3_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C3_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C3_InterruptDriverState = { -#endif - &I2C3_Resource, &I2C3_Handle, -}; - -static int32_t I2C3_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C3_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C3_InterruptDriverState); -} - -static int32_t I2C3_InterruptUninitialize(void) -{ - I2C3_DeinitPins(); - return I2C_InterruptUninitialize(&I2C3_InterruptDriverState); -} - -static int32_t I2C3_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C3_InterruptDriverState); -} - -int32_t I2C3_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C3_InterruptDriverState); -} - -int32_t I2C3_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C3_InterruptDriverState); -} - -int32_t I2C3_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C3_InterruptDriverState); -} - -int32_t I2C3_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C3_InterruptDriverState); -} - -int32_t I2C3_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C3_InterruptDriverState); -} - -int32_t I2C3_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C3_InterruptDriverState); -} - -ARM_I2C_STATUS I2C3_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C3_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C3 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C3_DMA_EN - I2C3_Master_DmaInitialize, I2C3_Master_DmaUninitialize, I2C3_Master_DmaPowerControl, - I2C3_Master_DmaTransmit, I2C3_Master_DmaReceive, NULL, NULL, I2C3_Master_DmaGetDataCount, - I2C3_Master_DmaControl, I2C3_Master_DmaGetStatus -#else - I2C3_InterruptInitialize, I2C3_InterruptUninitialize, I2C3_InterruptPowerControl, - I2C3_Master_InterruptTransmit, I2C3_Master_InterruptReceive, I2C3_Slave_InterruptTransmit, - I2C3_Slave_InterruptReceive, I2C3_InterruptGetDataCount, I2C3_InterruptControl, - I2C3_InterruptGetStatus -#endif -}; - -#endif - -#if defined(I2C4) && RTE_I2C4 -/* User needs to provide the implementation for I2C4_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t I2C4_GetFreq(void); -extern void I2C4_InitPins(void); -extern void I2C4_DeinitPins(void); - -cmsis_i2c_resource_t I2C4_Resource = {I2C4, I2C4_GetFreq}; - -#if RTE_I2C4_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C4_DmaResource = {RTE_I2C4_Master_DMA_BASE, RTE_I2C4_Master_DMA_CH}; - -i2c_master_dma_handle_t I2C4_DmaHandle; -dma_handle_t I2C4_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c4_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C4_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C4_DmaDriverState = { -#endif - &I2C4_Resource, &I2C4_DmaResource, &I2C4_DmaHandle, &I2C4_DmaTxRxHandle, -}; - -static int32_t I2C4_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C4_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C4_DmaDriverState); -} - -int32_t I2C4_Master_DmaUninitialize(void) -{ - I2C4_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C4_DmaDriverState); -} - -int32_t I2C4_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C4_DmaDriverState); -} - -int32_t I2C4_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C4_DmaDriverState); -} - -int32_t I2C4_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C4_DmaDriverState); -} - -int32_t I2C4_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C4_DmaDriverState); -} - -int32_t I2C4_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C4_DmaDriverState); -} - -ARM_I2C_STATUS I2C4_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C4_DmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C4_handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c4_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C4_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C4_InterruptDriverState = { -#endif - &I2C4_Resource, &I2C4_handle, - -}; - -static int32_t I2C4_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C4_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C4_InterruptDriverState); -} - -static int32_t I2C4_InterruptUninitialize(void) -{ - I2C4_DeinitPins(); - return I2C_InterruptUninitialize(&I2C4_InterruptDriverState); -} - -static int32_t I2C4_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C4_InterruptDriverState); -} - -int32_t I2C4_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C4_InterruptDriverState); -} - -int32_t I2C4_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C4_InterruptDriverState); -} - -int32_t I2C4_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C4_InterruptDriverState); -} - -int32_t I2C4_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C4_InterruptDriverState); -} - -int32_t I2C4_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C4_InterruptDriverState); -} - -int32_t I2C4_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C4_InterruptDriverState); -} - -ARM_I2C_STATUS I2C4_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C4_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C4 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C4_DMA_EN - I2C4_Master_DmaInitialize, I2C4_Master_DmaUninitialize, I2C4_Master_DmaPowerControl, - I2C4_Master_DmaTransmit, I2C4_Master_DmaReceive, NULL, NULL, I2C4_Master_DmaGetDataCount, - I2C4_Master_DmaControl, I2C4_Master_DmaGetStatus -#else - I2C4_InterruptInitialize, I2C4_InterruptUninitialize, I2C4_InterruptPowerControl, - I2C4_Master_InterruptTransmit, I2C4_Master_InterruptReceive, I2C4_Slave_InterruptTransmit, - I2C4_Slave_InterruptReceive, I2C4_InterruptGetDataCount, I2C4_InterruptControl, - I2C4_InterruptGetStatus -#endif -}; - -#endif - -#if defined(I2C5) && RTE_I2C5 -/* User needs to provide the implementation for I2C5_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t I2C5_GetFreq(void); -extern void I2C5_InitPins(void); -extern void I2C5_DeinitPins(void); - -cmsis_i2c_resource_t I2C5_Resource = {I2C5, I2C5_GetFreq}; - -#if RTE_I2C5_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C5_DmaResource = {RTE_I2C5_Master_DMA_BASE, RTE_I2C5_Master_DMA_CH}; - -i2c_master_dma_handle_t I2C5_DmaHandle; -dma_handle_t I2C5_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c5_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C5_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C5_DmaDriverState = { -#endif - &I2C5_Resource, &I2C5_DmaResource, &I2C5_DmaHandle, &I2C5_DmaTxRxHandle, -}; - -static int32_t I2C5_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C5_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C5_DmaDriverState); -} - -int32_t I2C5_Master_DmaUninitialize(void) -{ - I2C5_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C5_DmaDriverState); -} - -int32_t I2C5_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C5_DmaDriverState); -} - -int32_t I2C5_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C5_DmaDriverState); -} - -int32_t I2C5_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C5_DmaDriverState); -} - -int32_t I2C5_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C5_DmaDriverState); -} - -int32_t I2C5_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C5_DmaDriverState); -} - -ARM_I2C_STATUS I2C5_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C5_DmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C5_handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c5_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C5_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C5_InterruptDriverState = { -#endif - &I2C5_Resource, &I2C5_handle, - -}; - -static int32_t I2C5_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C5_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C5_InterruptDriverState); -} - -static int32_t I2C5_InterruptUninitialize(void) -{ - I2C5_DeinitPins(); - return I2C_InterruptUninitialize(&I2C5_InterruptDriverState); -} - -static int32_t I2C5_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C5_InterruptDriverState); -} - -int32_t I2C5_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C5_InterruptDriverState); -} - -int32_t I2C5_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C5_InterruptDriverState); -} - -int32_t I2C5_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C5_InterruptDriverState); -} - -int32_t I2C5_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C5_InterruptDriverState); -} - -int32_t I2C5_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C5_InterruptDriverState); -} - -int32_t I2C5_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C5_InterruptDriverState); -} - -ARM_I2C_STATUS I2C5_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C5_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C5 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C5_DMA_EN - I2C5_Master_DmaInitialize, I2C5_Master_DmaUninitialize, I2C5_Master_DmaPowerControl, - I2C5_Master_DmaTransmit, I2C5_Master_DmaReceive, NULL, NULL, I2C5_Master_DmaGetDataCount, - I2C5_Master_DmaControl, I2C5_Master_DmaGetStatus -#else - I2C5_InterruptInitialize, I2C5_InterruptUninitialize, I2C5_InterruptPowerControl, - I2C5_Master_InterruptTransmit, I2C5_Master_InterruptReceive, I2C5_Slave_InterruptTransmit, - I2C5_Slave_InterruptReceive, I2C5_InterruptGetDataCount, I2C5_InterruptControl, - I2C5_InterruptGetStatus -#endif -}; - -#endif - -#if defined(I2C6) && RTE_I2C6 -/* User needs to provide the implementation for I2C6_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t I2C6_GetFreq(void); -extern void I2C6_InitPins(void); -extern void I2C6_DeinitPins(void); - -cmsis_i2c_resource_t I2C6_Resource = {I2C6, I2C6_GetFreq}; - -#if RTE_I2C6_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C6_DmaResource = {RTE_I2C6_Master_DMA_BASE, RTE_I2C6_Master_DMA_CH}; - -i2c_master_dma_handle_t I2C6_DmaHandle; -dma_handle_t I2C6_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c6_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C6_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C6_DmaDriverState = { -#endif - &I2C6_Resource, &I2C6_DmaResource, &I2C6_DmaHandle, &I2C6_DmaTxRxHandle, -}; - -static int32_t I2C6_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C6_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C6_DmaDriverState); -} - -int32_t I2C6_Master_DmaUninitialize(void) -{ - I2C6_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C6_DmaDriverState); -} - -int32_t I2C6_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C6_DmaDriverState); -} - -int32_t I2C6_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C6_DmaDriverState); -} - -int32_t I2C6_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C6_DmaDriverState); -} - -int32_t I2C6_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C6_DmaDriverState); -} - -int32_t I2C6_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C6_DmaDriverState); -} - -ARM_I2C_STATUS I2C6_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C6_DmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C6_handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c6_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C6_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C6_InterruptDriverState = { -#endif - &I2C6_Resource, &I2C6_handle, - -}; - -static int32_t I2C6_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C6_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C6_InterruptDriverState); -} - -static int32_t I2C6_InterruptUninitialize(void) -{ - I2C6_DeinitPins(); - return I2C_InterruptUninitialize(&I2C6_InterruptDriverState); -} - -static int32_t I2C6_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C6_InterruptDriverState); -} - -int32_t I2C6_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C6_InterruptDriverState); -} - -int32_t I2C6_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C6_InterruptDriverState); -} - -int32_t I2C6_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C6_InterruptDriverState); -} - -int32_t I2C6_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C6_InterruptDriverState); -} - -int32_t I2C6_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C6_InterruptDriverState); -} - -int32_t I2C6_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C6_InterruptDriverState); -} - -ARM_I2C_STATUS I2C6_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C6_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C6 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C6_DMA_EN - I2C6_Master_DmaInitialize, I2C6_Master_DmaUninitialize, I2C6_Master_DmaPowerControl, - I2C6_Master_DmaTransmit, I2C6_Master_DmaReceive, NULL, NULL, I2C6_Master_DmaGetDataCount, - I2C6_Master_DmaControl, I2C6_Master_DmaGetStatus -#else - I2C6_InterruptInitialize, I2C6_InterruptUninitialize, I2C6_InterruptPowerControl, - I2C6_Master_InterruptTransmit, I2C6_Master_InterruptReceive, I2C6_Slave_InterruptTransmit, - I2C6_Slave_InterruptReceive, I2C6_InterruptGetDataCount, I2C6_InterruptControl, - I2C6_InterruptGetStatus -#endif -}; - -#endif - -#if defined(I2C7) && RTE_I2C7 -/* User needs to provide the implementation for I2C7_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t I2C7_GetFreq(void); -extern void I2C7_InitPins(void); -extern void I2C7_DeinitPins(void); - -cmsis_i2c_resource_t I2C7_Resource = {I2C7, I2C7_GetFreq}; - -#if RTE_I2C7_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C7_DmaResource = {RTE_I2C7_Master_DMA_BASE, RTE_I2C7_Master_DMA_CH}; - -i2c_master_dma_handle_t I2C7_DmaHandle; -dma_handle_t I2C7_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c7_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C7_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C7_DmaDriverState = { -#endif - &I2C7_Resource, &I2C7_DmaResource, &I2C7_DmaHandle, &I2C7_DmaTxRxHandle, -}; - -static int32_t I2C7_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C7_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C7_DmaDriverState); -} - -int32_t I2C7_Master_DmaUninitialize(void) -{ - I2C7_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C7_DmaDriverState); -} - -int32_t I2C7_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C7_DmaDriverState); -} - -int32_t I2C7_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C7_DmaDriverState); -} - -int32_t I2C7_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C7_DmaDriverState); -} - -int32_t I2C7_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C7_DmaDriverState); -} - -int32_t I2C7_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C7_DmaDriverState); -} - -ARM_I2C_STATUS I2C7_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C7_DmaDriverState); -} - -#endif - -#else -cmsis_i2c_handle_t I2C7_handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c7_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C7_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C7_InterruptDriverState = { -#endif - &I2C7_Resource, &I2C7_handle, - -}; - -static int32_t I2C7_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C7_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C7_InterruptDriverState); -} - -static int32_t I2C7_InterruptUninitialize(void) -{ - I2C7_DeinitPins(); - return I2C_InterruptUninitialize(&I2C7_InterruptDriverState); -} - -static int32_t I2C7_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C7_InterruptDriverState); -} - -int32_t I2C7_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C7_InterruptDriverState); -} - -int32_t I2C7_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C7_InterruptDriverState); -} - -int32_t I2C7_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C7_InterruptDriverState); -} - -int32_t I2C7_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C7_InterruptDriverState); -} - -int32_t I2C7_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C7_InterruptDriverState); -} - -int32_t I2C7_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C7_InterruptDriverState); -} - -ARM_I2C_STATUS I2C7_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C7_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C7 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C7_DMA_EN - I2C7_Master_DmaInitialize, I2C7_Master_DmaUninitialize, I2C7_Master_DmaPowerControl, - I2C7_Master_DmaTransmit, I2C7_Master_DmaReceive, NULL, NULL, I2C7_Master_DmaGetDataCount, - I2C7_Master_DmaControl, I2C7_Master_DmaGetStatus -#else - I2C7_InterruptInitialize, I2C7_InterruptUninitialize, I2C7_InterruptPowerControl, - I2C7_Master_InterruptTransmit, I2C7_Master_InterruptReceive, I2C7_Slave_InterruptTransmit, - I2C7_Slave_InterruptReceive, I2C7_InterruptGetDataCount, I2C7_InterruptControl, - I2C7_InterruptGetStatus -#endif -}; - -#endif - -#if defined(I2C8) && RTE_I2C8 -/* User needs to provide the implementation for I2C8_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t I2C8_GetFreq(void); -extern void I2C8_InitPins(void); -extern void I2C8_DeinitPins(void); - -cmsis_i2c_resource_t I2C8_Resource = {I2C8, I2C8_GetFreq}; - -#if RTE_I2C8_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C8_DmaResource = {RTE_I2C8_Master_DMA_BASE, RTE_I2C8_Master_DMA_CH}; - -i2c_master_dma_handle_t I2C8_DmaHandle; -dma_handle_t I2C8_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c8_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C8_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C8_DmaDriverState = { -#endif - &I2C8_Resource, &I2C8_DmaResource, &I2C8_DmaHandle, &I2C8_DmaTxRxHandle, -}; - -static int32_t I2C8_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C8_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C8_DmaDriverState); -} - -int32_t I2C8_Master_DmaUninitialize(void) -{ - I2C8_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C8_DmaDriverState); -} - -int32_t I2C8_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C8_DmaDriverState); -} - -int32_t I2C8_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C8_DmaDriverState); -} - -int32_t I2C8_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C8_DmaDriverState); -} - -int32_t I2C8_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C8_DmaDriverState); -} - -int32_t I2C8_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C8_DmaDriverState); -} - -ARM_I2C_STATUS I2C8_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C8_DmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C8_handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c8_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C8_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C8_InterruptDriverState = { -#endif - &I2C8_Resource, &I2C8_handle, - -}; - -static int32_t I2C8_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C8_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C8_InterruptDriverState); -} - -static int32_t I2C8_InterruptUninitialize(void) -{ - I2C8_DeinitPins(); - return I2C_InterruptUninitialize(&I2C8_InterruptDriverState); -} - -static int32_t I2C8_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C8_InterruptDriverState); -} - -int32_t I2C8_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C8_InterruptDriverState); -} - -int32_t I2C8_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C8_InterruptDriverState); -} - -int32_t I2C8_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C8_InterruptDriverState); -} - -int32_t I2C8_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C8_InterruptDriverState); -} - -int32_t I2C8_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C8_InterruptDriverState); -} - -int32_t I2C8_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C8_InterruptDriverState); -} - -ARM_I2C_STATUS I2C8_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C8_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C8 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C8_DMA_EN - I2C8_Master_DmaInitialize, I2C8_Master_DmaUninitialize, I2C8_Master_DmaPowerControl, - I2C8_Master_DmaTransmit, I2C8_Master_DmaReceive, NULL, NULL, I2C8_Master_DmaGetDataCount, - I2C8_Master_DmaControl, I2C8_Master_DmaGetStatus -#else - I2C8_InterruptInitialize, I2C8_InterruptUninitialize, I2C8_InterruptPowerControl, - I2C8_Master_InterruptTransmit, I2C8_Master_InterruptReceive, I2C8_Slave_InterruptTransmit, - I2C8_Slave_InterruptReceive, I2C8_InterruptGetDataCount, I2C8_InterruptControl, - I2C8_InterruptGetStatus -#endif -}; - -#endif - -#if defined(I2C9) && RTE_I2C9 -/* User needs to provide the implementation for I2C9_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t I2C9_GetFreq(void); -extern void I2C9_InitPins(void); -extern void I2C9_DeinitPins(void); - -cmsis_i2c_resource_t I2C9_Resource = {I2C9, I2C9_GetFreq}; - -#if RTE_I2C9_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C9_DmaResource = {RTE_I2C9_Master_DMA_BASE, RTE_I2C9_Master_DMA_CH}; - -i2c_master_dma_handle_t I2C9_DmaHandle; -dma_handle_t I2C9_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c9_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C9_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C9_DmaDriverState = { -#endif - &I2C9_Resource, &I2C9_DmaResource, &I2C9_DmaHandle, &I2C9_DmaTxRxHandle, -}; - -static int32_t I2C9_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C9_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C9_DmaDriverState); -} - -int32_t I2C9_Master_DmaUninitialize(void) -{ - I2C9_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C9_DmaDriverState); -} - -int32_t I2C9_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C9_DmaDriverState); -} - -int32_t I2C9_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C9_DmaDriverState); -} - -int32_t I2C9_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C9_DmaDriverState); -} - -int32_t I2C9_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C9_DmaDriverState); -} - -int32_t I2C9_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C9_DmaDriverState); -} - -ARM_I2C_STATUS I2C9_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C9_DmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C9_handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c9_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C9_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C9_InterruptDriverState = { -#endif - &I2C9_Resource, &I2C9_handle, - -}; - -static int32_t I2C9_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C9_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C9_InterruptDriverState); -} - -static int32_t I2C9_InterruptUninitialize(void) -{ - I2C9_DeinitPins(); - return I2C_InterruptUninitialize(&I2C9_InterruptDriverState); -} - -static int32_t I2C9_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C9_InterruptDriverState); -} - -int32_t I2C9_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C9_InterruptDriverState); -} - -int32_t I2C9_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C9_InterruptDriverState); -} - -int32_t I2C9_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C9_InterruptDriverState); -} - -int32_t I2C9_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C9_InterruptDriverState); -} - -int32_t I2C9_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C9_InterruptDriverState); -} - -int32_t I2C9_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C9_InterruptDriverState); -} - -ARM_I2C_STATUS I2C9_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C9_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C9 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C9_DMA_EN - I2C9_Master_DmaInitialize, I2C9_Master_DmaUninitialize, I2C9_Master_DmaPowerControl, - I2C9_Master_DmaTransmit, I2C9_Master_DmaReceive, NULL, NULL, I2C9_Master_DmaGetDataCount, - I2C9_Master_DmaControl, I2C9_Master_DmaGetStatus -#else - I2C9_InterruptInitialize, I2C9_InterruptUninitialize, I2C9_InterruptPowerControl, - I2C9_Master_InterruptTransmit, I2C9_Master_InterruptReceive, I2C9_Slave_InterruptTransmit, - I2C9_Slave_InterruptReceive, I2C9_InterruptGetDataCount, I2C9_InterruptControl, - I2C9_InterruptGetStatus -#endif -}; - -#endif diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_i2c_cmsis.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_i2c_cmsis.h deleted file mode 100644 index 0844a072837..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_i2c_cmsis.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2013-2016 ARM Limited. All rights reserved. - * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. - * Copyright 2016-2017 NXP. Not a Contribution. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#ifndef _FSL_I2C_CMSIS_H_ -#define _FSL_I2C_CMSIS_H_ -#include "fsl_common.h" -#include "Driver_I2C.h" -#include "RTE_Device.h" -#include "fsl_i2c.h" -#include "fsl_flexcomm.h" -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) -#include "fsl_i2c_dma.h" -#endif - -#if defined(I2C0) -extern ARM_DRIVER_I2C Driver_I2C0; -#endif - -#if defined(I2C1) -extern ARM_DRIVER_I2C Driver_I2C1; -#endif - -#if defined(I2C2) -extern ARM_DRIVER_I2C Driver_I2C2; -#endif - -#if defined(I2C3) -extern ARM_DRIVER_I2C Driver_I2C3; -#endif - -#if defined(I2C4) -extern ARM_DRIVER_I2C Driver_I2C4; -#endif - -#if defined(I2C5) -extern ARM_DRIVER_I2C Driver_I2C5; -#endif - -#if defined(I2C6) -extern ARM_DRIVER_I2C Driver_I2C6; -#endif - -#if defined(I2C7) -extern ARM_DRIVER_I2C Driver_I2C7; -#endif - -#if defined(I2C8) -extern ARM_DRIVER_I2C Driver_I2C8; -#endif - -#if defined(I2C9) -extern ARM_DRIVER_I2C Driver_I2C9; -#endif - -/* I2C Driver state flags */ -#define I2C_FLAG_UNINIT (0) -#define I2C_FLAG_INIT (1 << 0) -#define I2C_FLAG_POWER (1 << 1) - -#endif diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_spi_cmsis.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_spi_cmsis.c deleted file mode 100644 index 202e68d67b3..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_spi_cmsis.c +++ /dev/null @@ -1,2787 +0,0 @@ -/* - * Copyright (c) 2013-2016 ARM Limited. All rights reserved. - * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. - * Copyright 2016-2017 NXP. Not a Contribution. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "fsl_spi_cmsis.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi_cmsis" -#endif - - -#if (RTE_SPI0 || RTE_SPI1 || RTE_SPI2 || RTE_SPI3 || RTE_SPI4 || RTE_SPI5 || RTE_SPI6 || RTE_SPI7 || RTE_SPI8 || \ - RTE_SPI9) - -#define ARM_SPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */ - -/*! @brief IDs of clock for each FLEXCOMM module */ -static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; -/* Array of SPI reset number. */ -static const reset_ip_name_t s_spiResetInstance[] = FLEXCOMM_RSTS; -/* - * ARMCC does not support split the data section automatically, so the driver - * needs to split the data to separate sections explicitly, to reduce codesize. - */ -#if defined(__CC_ARM) -#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) -#endif - -typedef const struct _cmsis_spi_resource -{ - SPI_Type *base; - uint32_t instance; - uint32_t (*GetFreq)(void); -} cmsis_spi_resource_t; - -typedef union _cmsis_spi_handle -{ - spi_master_handle_t masterHandle; - spi_slave_handle_t slaveHandle; -} cmsis_spi_handle_t; - -typedef struct _cmsis_spi_interrupt_driver_state -{ - cmsis_spi_resource_t *resource; - cmsis_spi_handle_t *handle; - ARM_SPI_SignalEvent_t cb_event; - uint32_t baudRate_Bps; - uint8_t flags; /*!< Control and state flags. */ -} cmsis_spi_interrupt_driver_state_t; - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -typedef const struct _cmsis_spi_dma_resource -{ - DMA_Type *txdmaBase; - uint32_t txdmaChannel; - - DMA_Type *rxdmaBase; - uint32_t rxdmaChannel; -} cmsis_spi_dma_resource_t; - -typedef union _cmsis_spi_dma_handle -{ - spi_dma_handle_t masterHandle; - spi_dma_handle_t slaveHandle; -} cmsis_spi_dma_handle_t; - -typedef struct _cmsis_spi_dma_driver_state -{ - cmsis_spi_resource_t *resource; - cmsis_spi_dma_resource_t *dmaResource; - cmsis_spi_dma_handle_t *handle; - dma_handle_t *dmaRxDataHandle; - dma_handle_t *dmaTxDataHandle; - - uint32_t baudRate_Bps; - ARM_SPI_SignalEvent_t cb_event; - uint8_t flags; /*!< Control and state flags. */ -} cmsis_spi_dma_driver_state_t; -#endif - -/* Driver Version */ -static const ARM_DRIVER_VERSION s_SPIDriverVersion = {ARM_SPI_API_VERSION, ARM_SPI_DRV_VERSION}; - -/* Driver Capabilities */ -static const ARM_SPI_CAPABILITIES s_SPIDriverCapabilities = { - 1, /* Simplex Mode (Master and Slave) */ - 0, /* TI Synchronous Serial Interface */ - 0, /* Microwire Interface */ - 0 /* Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT */ -}; - -/******************************************************************************* - * Code - ******************************************************************************/ - -void SPI_MasterCommonControl(uint32_t control, - cmsis_spi_resource_t *resource, - uint8_t *status, - spi_master_config_t *masterConfig) -{ - switch (resource->instance) - { - case 0: -#if defined(RTE_SPI0_SSEL_NUM) - masterConfig->sselNum = RTE_SPI0_SSEL_NUM; -#endif -#if defined(RTE_SPI0_SSEL_POL) - masterConfig->sselPol = RTE_SPI0_SSEL_POL; -#endif - break; - - case 1: -#if defined(RTE_SPI1_SSEL_NUM) - masterConfig->sselNum = RTE_SPI1_SSEL_NUM; -#endif -#if defined(RTE_SPI1_SSEL_POL) - masterConfig->sselPol = RTE_SPI1_SSEL_POL; -#endif - break; - case 2: -#if defined(RTE_SPI2_SSEL_NUM) - masterConfig->sselNum = RTE_SPI2_SSEL_NUM; -#endif -#if defined(RTE_SPI2_SSEL_POL) - masterConfig->sselPol = RTE_SPI2_SSEL_POL; -#endif - break; - - case 3: -#if defined(RTE_SPI3_SSEL_NUM) - masterConfig->sselNum = RTE_SPI3_SSEL_NUM; -#endif -#if defined(RTE_SPI3_SSEL_POL) - masterConfig->sselPol = RTE_SPI3_SSEL_POL; -#endif - break; - - case 4: -#if defined(RTE_SPI4_SSEL_NUM) - masterConfig->sselNum = RTE_SPI4_SSEL_NUM; -#endif -#if defined(RTE_SPI4_SSEL_POL) - masterConfig->sselPol = RTE_SPI4_SSEL_POL; -#endif - break; - - case 5: -#if defined(RTE_SPI5_SSEL_NUM) - masterConfig->sselNum = RTE_SPI5_SSEL_NUM; -#endif -#if defined(RTE_SPI5_SSEL_POL) - masterConfig->sselPol = RTE_SPI5_SSEL_POL; -#endif - break; - - case 6: -#if defined(RTE_SPI6_SSEL_NUM) - masterConfig->sselNum = RTE_SPI6_SSEL_NUM; -#endif -#if defined(RTE_SPI6_SSEL_POL) - masterConfig->sselPol = RTE_SPI6_SSEL_POL; -#endif - break; - - case 7: -#if defined(RTE_SPI7_SSEL_NUM) - masterConfig->sselNum = RTE_SPI7_SSEL_NUM; -#endif -#if defined(RTE_SPI7_SSEL_POL) - masterConfig->sselPol = RTE_SPI7_SSEL_POL; -#endif - break; - - case 8: -#if defined(RTE_SPI8_SSEL_NUM) - masterConfig->sselNum = RTE_SPI8_SSEL_NUM; -#endif -#if defined(RTE_SPI8_SSEL_POL) - masterConfig->sselPol = RTE_SPI8_SSEL_POL; -#endif - break; - - case 9: -#if defined(RTE_SPI9_SSEL_NUM) - masterConfig->sselNum = RTE_SPI9_SSEL_NUM; -#endif -#if defined(RTE_SPI9_SSEL_POL) - masterConfig->sselPol = RTE_SPI9_SSEL_POL; -#endif - break; - - default: - break; - } - - switch (control & ARM_SPI_FRAME_FORMAT_Msk) - { - case ARM_SPI_CPOL0_CPHA0: - masterConfig->polarity = kSPI_ClockPolarityActiveHigh; - masterConfig->phase = kSPI_ClockPhaseFirstEdge; - break; - - case ARM_SPI_CPOL0_CPHA1: - masterConfig->polarity = kSPI_ClockPolarityActiveHigh; - masterConfig->phase = kSPI_ClockPhaseSecondEdge; - break; - - case ARM_SPI_CPOL1_CPHA0: - masterConfig->polarity = kSPI_ClockPolarityActiveLow; - masterConfig->phase = kSPI_ClockPhaseFirstEdge; - break; - - case ARM_SPI_CPOL1_CPHA1: - masterConfig->polarity = kSPI_ClockPolarityActiveLow; - masterConfig->phase = kSPI_ClockPhaseSecondEdge; - break; - - default: - break; - } - - if (control & ARM_SPI_DATA_BITS_Msk) /* setting Number of Data bits */ - { - if ((((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) >= 4) && - (((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) <= 16)) - { - masterConfig->dataWidth = - (spi_data_width_t)(((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) - 1); - } - } - - switch (control & ARM_SPI_BIT_ORDER_Msk) - { - case ARM_SPI_LSB_MSB: - masterConfig->direction = kSPI_LsbFirst; - break; - case ARM_SPI_MSB_LSB: - masterConfig->direction = kSPI_MsbFirst; - break; - - default: - break; - } -} - -void SPI_SlaveCommonControl(uint32_t control, - cmsis_spi_resource_t *resource, - uint8_t *status, - spi_slave_config_t *slaveConfig) -{ - switch (resource->instance) - { - case 0: -#if defined(RTE_SPI0_SSEL_POL) - slaveConfig->sselPol = RTE_SPI0_SSEL_POL; -#endif - break; - - case 1: -#if defined(RTE_SPI1_SSEL_POL) - slaveConfig->sselPol = RTE_SPI1_SSEL_POL; -#endif - break; - case 2: -#if defined(RTE_SPI2_SSEL_POL) - slaveConfig->sselPol = RTE_SPI2_SSEL_POL; -#endif - break; - - case 3: -#if defined(RTE_SPI3_SSEL_POL) - slaveConfig->sselPol = RTE_SPI3_SSEL_POL; -#endif - break; - - case 4: -#if defined(RTE_SPI4_SSEL_POL) - slaveConfig->sselPol = RTE_SPI4_SSEL_POL; -#endif - break; - - case 5: -#if defined(RTE_SPI5_SSEL_POL) - slaveConfig->sselPol = RTE_SPI5_SSEL_POL; -#endif - break; - - case 6: -#if defined(RTE_SPI6_SSEL_POL) - slaveConfig->sselPol = RTE_SPI6_SSEL_POL; -#endif - break; - - case 7: -#if defined(RTE_SPI7_SSEL_POL) - slaveConfig->sselPol = RTE_SPI7_SSEL_POL; -#endif - break; - - case 8: -#if defined(RTE_SPI8_SSEL_POL) - slaveConfig->sselPol = RTE_SPI8_SSEL_POL; -#endif - break; - - case 9: -#if defined(RTE_SPI9_SSEL_POL) - slaveConfig->sselPol = RTE_SPI9_SSEL_POL; -#endif - break; - - default: - break; - } - - switch (control & ARM_SPI_FRAME_FORMAT_Msk) - { - case ARM_SPI_CPOL0_CPHA0: - slaveConfig->polarity = kSPI_ClockPolarityActiveHigh; - slaveConfig->phase = kSPI_ClockPhaseFirstEdge; - break; - - case ARM_SPI_CPOL0_CPHA1: - slaveConfig->polarity = kSPI_ClockPolarityActiveHigh; - slaveConfig->phase = kSPI_ClockPhaseSecondEdge; - break; - - case ARM_SPI_CPOL1_CPHA0: - slaveConfig->polarity = kSPI_ClockPolarityActiveLow; - slaveConfig->phase = kSPI_ClockPhaseFirstEdge; - break; - - case ARM_SPI_CPOL1_CPHA1: - slaveConfig->polarity = kSPI_ClockPolarityActiveLow; - slaveConfig->phase = kSPI_ClockPhaseSecondEdge; - break; - - default: - break; - } - if (control & ARM_SPI_DATA_BITS_Msk) /* setting Number of Data bits */ - { - if ((((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) >= 4) && - (((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) <= 16)) - { - slaveConfig->dataWidth = - (spi_data_width_t)(((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) - 1); - } - } - switch (control & ARM_SPI_BIT_ORDER_Msk) - { - case ARM_SPI_LSB_MSB: - slaveConfig->direction = kSPI_LsbFirst; - break; - case ARM_SPI_MSB_LSB: - slaveConfig->direction = kSPI_MsbFirst; - break; - - default: - break; - } -} - -static ARM_DRIVER_VERSION SPIx_GetVersion(void) -{ - return s_SPIDriverVersion; -} - -static ARM_SPI_CAPABILITIES SPIx_GetCapabilities(void) -{ - return s_SPIDriverCapabilities; -} - -#endif - -#if (RTE_SPI0_DMA_EN || RTE_SPI1_DMA_EN || RTE_SPI2_DMA_EN || RTE_SPI3_DMA_EN || RTE_SPI4_DMA_EN || RTE_SPI5_DMA_EN || \ - RTE_SPI6_DMA_EN || RTE_SPI7_DMA_EN || RTE_SPI8_DMA_EN || RTE_SPI9_DMA_EN) - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -void KSDK_SPI_MasterDMACallback(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData) -{ - uint32_t event = 0; - - if (kStatus_Success == status) - { - event = ARM_SPI_EVENT_TRANSFER_COMPLETE; - } - - if (kStatus_SPI_Error == status) - { - event = ARM_SPI_EVENT_DATA_LOST; - } - - if (userData) - { - ((ARM_SPI_SignalEvent_t)userData)(event); - } -} -void KSDK_SPI_SlaveDMACallback(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData) -{ - uint32_t event = 0; - - if (kStatus_Success == status) - { - event = ARM_SPI_EVENT_TRANSFER_COMPLETE; - } - - if (kStatus_SPI_Error == status) - { - event = ARM_SPI_EVENT_DATA_LOST; - } - /* User data is actually CMSIS driver callback. */ - if (userData) - { - ((ARM_SPI_SignalEvent_t)userData)(event); - } -} - -static int32_t SPI_DMAInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_spi_dma_driver_state_t *spi) -{ - if (!(spi->flags & SPI_FLAG_INIT)) - { - spi->cb_event = cb_event; - spi->flags = SPI_FLAG_INIT; - } - return ARM_DRIVER_OK; -} - -static int32_t SPI_DMAUninitialize(cmsis_spi_dma_driver_state_t *spi) -{ - spi->flags = SPI_FLAG_UNINIT; - return ARM_DRIVER_OK; -} - -static int32_t SPI_DMAPowerControl(ARM_POWER_STATE state, cmsis_spi_dma_driver_state_t *spi) -{ - switch (state) - { - case ARM_POWER_OFF: - if (spi->flags & SPI_FLAG_POWER) - { - SPI_Deinit(spi->resource->base); - RESET_PeripheralReset(s_spiResetInstance[spi->resource->instance]); - - DMA_DisableChannel(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel); - DMA_DisableChannel(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); - DMA_Deinit(spi->dmaResource->txdmaBase); - DMA_Deinit(spi->dmaResource->rxdmaBase); - - spi->flags = SPI_FLAG_INIT; - } - break; - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - case ARM_POWER_FULL: - if (spi->flags == SPI_FLAG_UNINIT) - { - return ARM_DRIVER_ERROR; - } - - if (spi->flags & SPI_FLAG_POWER) - { - /* Driver already powered */ - break; - } - - /* Enable flexcomm clock gate */ - CLOCK_EnableClock(s_flexcommClocks[spi->resource->instance]); - /* Init DMA */ - DMA_Init(spi->dmaResource->rxdmaBase); - DMA_Init(spi->dmaResource->txdmaBase); - spi->flags |= SPI_FLAG_POWER; - - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - return ARM_DRIVER_OK; -} - -static int32_t SPI_DMASend(const void *data, uint32_t num, cmsis_spi_dma_driver_state_t *spi) -{ - int32_t ret; - status_t status; - spi_transfer_t xfer = {0}; - - xfer.rxData = NULL; - xfer.txData = (uint8_t *)data; - xfer.dataSize = num; - if (spi->flags & SPI_FLAG_MASTER) - { - xfer.configFlags |= kSPI_FrameAssert; - } - - if (spi->flags & SPI_FLAG_MASTER) - { - status = SPI_MasterTransferDMA(spi->resource->base, &spi->handle->masterHandle, &xfer); - } - else - { - status = SPI_SlaveTransferDMA(spi->resource->base, &spi->handle->slaveHandle, &xfer); - } - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_SPI_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t SPI_DMAReceive(void *data, uint32_t num, cmsis_spi_dma_driver_state_t *spi) -{ - int32_t ret; - status_t status; - spi_transfer_t xfer = {0}; - - xfer.txData = NULL; - xfer.rxData = (uint8_t *)data; - xfer.dataSize = num; - if (spi->flags & SPI_FLAG_MASTER) - { - xfer.configFlags |= kSPI_FrameAssert; - } - - if (spi->flags & SPI_FLAG_MASTER) - { - status = SPI_MasterTransferDMA(spi->resource->base, &spi->handle->masterHandle, &xfer); - } - else - { - status = SPI_SlaveTransferDMA(spi->resource->base, &spi->handle->slaveHandle, &xfer); - } - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_SPI_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t SPI_DMATransfer(const void *data_out, void *data_in, uint32_t num, cmsis_spi_dma_driver_state_t *spi) -{ - int32_t ret; - status_t status; - spi_transfer_t xfer = {0}; - - xfer.txData = (uint8_t *)data_out; - xfer.rxData = (uint8_t *)data_in; - xfer.dataSize = num; - if (spi->flags & SPI_FLAG_MASTER) - { - xfer.configFlags |= kSPI_FrameAssert; - } - - if (spi->flags & SPI_FLAG_MASTER) - { - status = SPI_MasterTransferDMA(spi->resource->base, &spi->handle->masterHandle, &xfer); - } - else - { - status = SPI_SlaveTransferDMA(spi->resource->base, &spi->handle->slaveHandle, &xfer); - } - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_SPI_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} -static uint32_t SPI_DMAGetCount(cmsis_spi_dma_driver_state_t *spi) -{ - uint32_t cnt; - size_t bytes; - - bytes = DMA_GetRemainingBytes(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); - - if (spi->flags & SPI_FLAG_MASTER) - { - cnt = spi->handle->masterHandle.transferSize - bytes; - } - else - { - cnt = spi->handle->slaveHandle.transferSize - bytes; - } - - return cnt; -} - -static int32_t SPI_DMAControl(uint32_t control, uint32_t arg, cmsis_spi_dma_driver_state_t *spi) -{ - if (!(spi->flags & SPI_FLAG_POWER)) - { - return ARM_DRIVER_ERROR; - } - - switch (control & ARM_SPI_CONTROL_Msk) - { - case ARM_SPI_MODE_INACTIVE: - SPI_Enable(spi->resource->base, false); - break; - case ARM_SPI_MODE_MASTER: - spi->baudRate_Bps = arg; - spi->flags |= SPI_FLAG_MASTER; - break; - - case ARM_SPI_MODE_SLAVE: - spi->flags &= ~SPI_FLAG_MASTER; - break; - - case ARM_SPI_SET_BUS_SPEED: - if (!(spi->flags & SPI_FLAG_MASTER)) - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - SPI_MasterSetBaud(spi->resource->base, arg, spi->resource->GetFreq()); - - spi->baudRate_Bps = arg; - return ARM_DRIVER_OK; - - case ARM_SPI_GET_BUS_SPEED: /* Set Bus Speed in bps; arg = value */ - if (!(spi->flags & SPI_FLAG_MASTER)) - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - return spi->baudRate_Bps; - - case ARM_SPI_CONTROL_SS: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - case ARM_SPI_ABORT_TRANSFER: - if (spi->flags & SPI_FLAG_MASTER) - { - SPI_MasterTransferAbortDMA(spi->resource->base, &spi->handle->masterHandle); - } - else - { - SPI_SlaveTransferAbortDMA(spi->resource->base, &spi->handle->slaveHandle); - } - return ARM_DRIVER_OK; - - case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */ - SPI_SetDummyData(spi->resource->base, (uint8_t)arg); - return ARM_DRIVER_OK; - - case ARM_SPI_MODE_MASTER_SIMPLEX: /* SPI Master (Output/Input on MOSI); arg = Bus Speed in bps */ - /* Mode is not supported by current driver. */ - return ARM_DRIVER_ERROR_UNSUPPORTED; - - case ARM_SPI_MODE_SLAVE_SIMPLEX: /* SPI Slave (Output/Input on MISO) */ - /* Mode is not supported by current driver. */ - return ARM_DRIVER_ERROR_UNSUPPORTED; - - default: - break; - } - - if (spi->flags & SPI_FLAG_MASTER) - { - switch (control & ARM_SPI_SS_MASTER_MODE_Msk) - { - /* - * Note: - * ARM_SPI_SS_MASTER_HW_OUTPUT is default configuration in driver, if ARM_SPI_SS_MASTER_UNUSED or - * ARM_SPI_SS_MASTER_SW is wanted, please disable pin function in SPIx_InitPins() which is configured - * by user in extern file. Besides, ARM_SPI_SS_MASTER_HW_INPUT is not supported in this driver. - */ - case ARM_SPI_SS_MASTER_UNUSED: /*!< SPI Slave Select when Master: Not used */ - break; - case ARM_SPI_SS_MASTER_SW: /*!< SPI Slave Select when Master: Software controlled. */ - break; - case ARM_SPI_SS_MASTER_HW_OUTPUT: /*!< SPI Slave Select when Master: Hardware controlled Output */ - break; - case ARM_SPI_SS_MASTER_HW_INPUT: /*!< SPI Slave Select when Master: Hardware monitored Input */ - break; - default: - break; - } - spi_master_config_t masterConfig; - SPI_MasterGetDefaultConfig(&masterConfig); - masterConfig.baudRate_Bps = spi->baudRate_Bps; - SPI_MasterCommonControl(control, spi->resource, &spi->flags, &masterConfig); - - if (spi->flags & SPI_FLAG_CONFIGURED) - { - SPI_Deinit(spi->resource->base); - RESET_PeripheralReset(s_spiResetInstance[spi->resource->instance]); - } - SPI_MasterInit(spi->resource->base, &masterConfig, spi->resource->GetFreq()); - - DMA_EnableChannel(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel); - DMA_EnableChannel(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); - DMA_SetChannelPriority(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel, kDMA_ChannelPriority3); - DMA_SetChannelPriority(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel, kDMA_ChannelPriority2); - DMA_CreateHandle(spi->dmaTxDataHandle, spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel); - DMA_CreateHandle(spi->dmaRxDataHandle, spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); - - SPI_MasterTransferCreateHandleDMA(spi->resource->base, &(spi->handle->masterHandle), KSDK_SPI_MasterDMACallback, - (void *)spi->cb_event, spi->dmaTxDataHandle, spi->dmaRxDataHandle); - spi->flags |= SPI_FLAG_CONFIGURED; - } - else - { - /* The SPI slave select is controlled by hardware, software mode is not supported by current driver. */ - switch (control & ARM_SPI_SS_SLAVE_MODE_Msk) - { - case ARM_SPI_SS_SLAVE_HW: - break; - case ARM_SPI_SS_SLAVE_SW: - break; - default: - break; - } - - spi_slave_config_t slaveConfig; - SPI_SlaveGetDefaultConfig(&slaveConfig); - SPI_SlaveCommonControl(control, spi->resource, &spi->flags, &slaveConfig); - - if (spi->flags & SPI_FLAG_CONFIGURED) - { - SPI_Deinit(spi->resource->base); - RESET_PeripheralReset(s_spiResetInstance[spi->resource->instance]); - } - SPI_SlaveInit(spi->resource->base, &slaveConfig); - - DMA_EnableChannel(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel); - DMA_EnableChannel(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); - DMA_SetChannelPriority(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel, kDMA_ChannelPriority0); - DMA_SetChannelPriority(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel, kDMA_ChannelPriority1); - DMA_CreateHandle(spi->dmaTxDataHandle, spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel); - DMA_CreateHandle(spi->dmaRxDataHandle, spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); - - SPI_SlaveTransferCreateHandleDMA(spi->resource->base, &(spi->handle->slaveHandle), KSDK_SPI_SlaveDMACallback, - (void *)spi->cb_event, spi->dmaTxDataHandle, spi->dmaRxDataHandle); - - spi->flags |= SPI_FLAG_CONFIGURED; - } - - return ARM_DRIVER_OK; -} - -ARM_SPI_STATUS SPI_DMAGetStatus(cmsis_spi_dma_driver_state_t *spi) -{ - ARM_SPI_STATUS stat; - - if (spi->flags & SPI_FLAG_MASTER) - { - stat.busy = - ((spi->handle->masterHandle.txInProgress == true) || (spi->handle->masterHandle.rxInProgress == true)) ? - (0U) : - (1U); - stat.data_lost = (kStatus_SPI_Error == spi->handle->masterHandle.state) ? (1U) : (0U); - } - else - { - stat.busy = - ((spi->handle->slaveHandle.txInProgress == true) || (spi->handle->slaveHandle.rxInProgress == true)) ? - (0U) : - (1U); - stat.data_lost = (kStatus_SPI_Error == spi->handle->slaveHandle.state) ? (1U) : (0U); - } - stat.mode_fault = 0U; - stat.reserved = 0U; - - return stat; -} -#endif /* defined(FSL_FEATURE_SOC_DMA_COUNT) */ - -#endif - -#if ((RTE_SPI0 && !RTE_SPI0_DMA_EN) || (RTE_SPI1 && !RTE_SPI1_DMA_EN) || (RTE_SPI2 && !RTE_SPI2_DMA_EN) || \ - (RTE_SPI3 && !RTE_SPI3_DMA_EN) || (RTE_SPI4 && !RTE_SPI4_DMA_EN) || (RTE_SPI5 && !RTE_SPI5_DMA_EN) || \ - (RTE_SPI6 && !RTE_SPI6_DMA_EN) || (RTE_SPI7 && !RTE_SPI7_DMA_EN) || (RTE_SPI8 && !RTE_SPI8_DMA_EN) || \ - (RTE_SPI9 && !RTE_SPI9_DMA_EN)) - -void KSDK_SPI_MasterInterruptCallback(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData) -{ - uint32_t event = 0; - - if ((kStatus_Success == status) || (kStatus_SPI_Idle == status)) - { - event = ARM_SPI_EVENT_TRANSFER_COMPLETE; - } - - if (kStatus_SPI_Error == status) - { - event = ARM_SPI_EVENT_DATA_LOST; - } - - /* User data is actually CMSIS driver callback. */ - if (userData) - { - ((ARM_SPI_SignalEvent_t)userData)(event); - } -} - -void KSDK_SPI_SlaveInterruptCallback(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData) -{ - uint32_t event = 0; - - if ((kStatus_Success == status) || (kStatus_SPI_Idle == status)) - { - event = ARM_SPI_EVENT_TRANSFER_COMPLETE; - } - - if (kStatus_SPI_Error == status) - { - event = ARM_SPI_EVENT_DATA_LOST; - } - - /* User data is actually CMSIS driver callback. */ - if (userData) - { - ((ARM_SPI_SignalEvent_t)userData)(event); - } -} - -static int32_t SPI_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_spi_interrupt_driver_state_t *spi) -{ - if (!(spi->flags & SPI_FLAG_INIT)) - { - spi->cb_event = cb_event; - spi->flags = SPI_FLAG_INIT; - } - - return ARM_DRIVER_OK; -} - -static int32_t SPI_InterruptUninitialize(cmsis_spi_interrupt_driver_state_t *spi) -{ - spi->flags = SPI_FLAG_UNINIT; - return ARM_DRIVER_OK; -} - -static int32_t SPI_InterruptPowerControl(ARM_POWER_STATE state, cmsis_spi_interrupt_driver_state_t *spi) -{ - switch (state) - { - case ARM_POWER_OFF: - if (spi->flags & SPI_FLAG_POWER) - { - SPI_Deinit(spi->resource->base); - /* Reset Periphera instance, and disable the clock gate */ - RESET_PeripheralReset(s_spiResetInstance[spi->resource->instance]); - spi->flags = SPI_FLAG_INIT; - } - break; - - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - case ARM_POWER_FULL: - if (spi->flags == SPI_FLAG_UNINIT) - { - return ARM_DRIVER_ERROR; - } - - if (spi->flags & SPI_FLAG_POWER) - { - /* Driver already powered */ - break; - } - - /* Enable flexcomm clock gate */ - CLOCK_EnableClock(s_flexcommClocks[spi->resource->instance]); - spi->flags |= SPI_FLAG_POWER; - - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - return ARM_DRIVER_OK; -} - -static int32_t SPI_InterruptSend(const void *data, uint32_t num, cmsis_spi_interrupt_driver_state_t *spi) -{ - int32_t ret; - status_t status; - spi_transfer_t xfer = {0}; - - xfer.rxData = NULL; - xfer.txData = (uint8_t *)data; - xfer.dataSize = num; - if (spi->flags & SPI_FLAG_MASTER) - { - xfer.configFlags |= kSPI_FrameAssert; - } - - if (spi->flags & SPI_FLAG_MASTER) - { - status = SPI_MasterTransferNonBlocking(spi->resource->base, &spi->handle->masterHandle, &xfer); - } - else - { - status = SPI_SlaveTransferNonBlocking(spi->resource->base, &spi->handle->slaveHandle, &xfer); - } - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_SPI_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t SPI_InterruptReceive(void *data, uint32_t num, cmsis_spi_interrupt_driver_state_t *spi) -{ - int32_t ret; - status_t status; - spi_transfer_t xfer = {0}; - - xfer.txData = NULL; - xfer.rxData = (uint8_t *)data; - xfer.dataSize = num; - if (spi->flags & SPI_FLAG_MASTER) - { - xfer.configFlags |= kSPI_FrameAssert; - } - - if (spi->flags & SPI_FLAG_MASTER) - { - status = SPI_MasterTransferNonBlocking(spi->resource->base, &spi->handle->masterHandle, &xfer); - } - else - { - status = SPI_SlaveTransferNonBlocking(spi->resource->base, &spi->handle->slaveHandle, &xfer); - } - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_SPI_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t SPI_InterruptTransfer(const void *data_out, - void *data_in, - uint32_t num, - cmsis_spi_interrupt_driver_state_t *spi) -{ - int32_t ret; - status_t status; - spi_transfer_t xfer = {0}; - - xfer.txData = (uint8_t *)data_out; - xfer.rxData = (uint8_t *)data_in; - xfer.dataSize = num; - if (spi->flags & SPI_FLAG_MASTER) - { - xfer.configFlags |= kSPI_FrameAssert; - } - - if (spi->flags & SPI_FLAG_MASTER) - { - status = SPI_MasterTransferNonBlocking(spi->resource->base, &spi->handle->masterHandle, &xfer); - } - else - { - status = SPI_SlaveTransferNonBlocking(spi->resource->base, &spi->handle->slaveHandle, &xfer); - } - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_SPI_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} -static uint32_t SPI_InterruptGetCount(cmsis_spi_interrupt_driver_state_t *spi) -{ - if (spi->flags & SPI_FLAG_MASTER) - { - return spi->handle->masterHandle.totalByteCount - spi->handle->masterHandle.rxRemainingBytes; - } - else - { - return spi->handle->slaveHandle.toReceiveCount - spi->handle->slaveHandle.rxRemainingBytes; - } -} - -static int32_t SPI_InterruptControl(uint32_t control, uint32_t arg, cmsis_spi_interrupt_driver_state_t *spi) -{ - if (!(spi->flags & SPI_FLAG_POWER)) - { - return ARM_DRIVER_ERROR; - } - - switch (control & ARM_SPI_CONTROL_Msk) - { - case ARM_SPI_MODE_INACTIVE: /* SPI mode Inactive */ - FLEXCOMM_Init(spi->resource->base, FLEXCOMM_PERIPH_NONE); - break; - - case ARM_SPI_MODE_MASTER: /* SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps */ - spi->baudRate_Bps = arg; - spi->flags |= SPI_FLAG_MASTER; - break; - - case ARM_SPI_MODE_SLAVE: /* SPI Slave (Output on MISO, Input on MOSI) */ - spi->flags &= ~SPI_FLAG_MASTER; - break; - - case ARM_SPI_GET_BUS_SPEED: /* Get Bus Speed in bps */ - if (!(spi->flags & SPI_FLAG_MASTER)) - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - return spi->baudRate_Bps; - - case ARM_SPI_SET_BUS_SPEED: /* Set Bus Speed in bps; */ - if (!(spi->flags & SPI_FLAG_MASTER)) - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - SPI_MasterSetBaud(spi->resource->base, arg, spi->resource->GetFreq()); - spi->baudRate_Bps = arg; - - return ARM_DRIVER_OK; - - case ARM_SPI_CONTROL_SS: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - case ARM_SPI_ABORT_TRANSFER: /* Abort current data transfer */ - if (spi->flags & SPI_FLAG_MASTER) - { - SPI_MasterTransferAbort(spi->resource->base, &spi->handle->masterHandle); - } - else - { - SPI_SlaveTransferAbort(spi->resource->base, &spi->handle->slaveHandle); - } - return ARM_DRIVER_OK; - - case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */ - SPI_SetDummyData(spi->resource->base, (uint8_t)arg); - return ARM_DRIVER_OK; - - case ARM_SPI_MODE_MASTER_SIMPLEX: /* SPI Master (Output/Input on MOSI); arg = Bus Speed in bps */ - /* Mode is not supported by current driver. */ - return ARM_DRIVER_ERROR_UNSUPPORTED; - - case ARM_SPI_MODE_SLAVE_SIMPLEX: /* SPI Slave (Output/Input on MISO) */ - /* Mode is not supported by current driver. */ - return ARM_DRIVER_ERROR_UNSUPPORTED; - - default: - break; - } - - if (spi->flags & SPI_FLAG_MASTER) - { - switch (control & ARM_SPI_SS_MASTER_MODE_Msk) - { - /* - * Note: - * ARM_SPI_SS_MASTER_HW_OUTPUT is default configuration in driver, if ARM_SPI_SS_MASTER_UNUSED or - * ARM_SPI_SS_MASTER_SW is wanted, please disable pin function in SPIx_InitPins() which is configured - * by user in extern file. Besides ARM_SPI_SS_MASTER_HW_INPUT is not supported in this driver. - */ - case ARM_SPI_SS_MASTER_UNUSED: /*!< SPI Slave Select when Master: Not used */ - break; - case ARM_SPI_SS_MASTER_SW: /*!< SPI Slave Select when Master: Software controlled. */ - break; - case ARM_SPI_SS_MASTER_HW_OUTPUT: /*!< SPI Slave Select when Master: Hardware controlled Output */ - break; - case ARM_SPI_SS_MASTER_HW_INPUT: /*!< SPI Slave Select when Master: Hardware monitored Input */ - break; - default: - break; - } - - spi_master_config_t masterConfig; - SPI_MasterGetDefaultConfig(&masterConfig); - masterConfig.baudRate_Bps = spi->baudRate_Bps; - - SPI_MasterCommonControl(control, spi->resource, &spi->flags, &masterConfig); - - if (spi->flags & SPI_FLAG_CONFIGURED) - { - SPI_Deinit(spi->resource->base); - RESET_PeripheralReset(s_spiResetInstance[spi->resource->instance]); - } - SPI_MasterInit(spi->resource->base, &masterConfig, spi->resource->GetFreq()); - SPI_MasterTransferCreateHandle(spi->resource->base, &spi->handle->masterHandle, - KSDK_SPI_MasterInterruptCallback, (void *)spi->cb_event); - spi->flags |= SPI_FLAG_CONFIGURED; - } - else - { - /* The SPI slave select is controlled by hardware, software mode is not supported by current driver. */ - switch (control & ARM_SPI_SS_SLAVE_MODE_Msk) - { - case ARM_SPI_SS_SLAVE_HW: - break; - case ARM_SPI_SS_SLAVE_SW: - break; - default: - break; - } - - spi_slave_config_t slaveConfig; - SPI_SlaveGetDefaultConfig(&slaveConfig); - - SPI_SlaveCommonControl(control, spi->resource, &spi->flags, &slaveConfig); - - if (spi->flags & SPI_FLAG_CONFIGURED) - { - SPI_Deinit(spi->resource->base); - RESET_PeripheralReset(s_spiResetInstance[spi->resource->instance]); - } - SPI_SlaveInit(spi->resource->base, &slaveConfig); - SPI_SlaveTransferCreateHandle(spi->resource->base, &spi->handle->slaveHandle, KSDK_SPI_SlaveInterruptCallback, - (void *)spi->cb_event); - spi->flags |= SPI_FLAG_CONFIGURED; - } - - return ARM_DRIVER_OK; -} - -ARM_SPI_STATUS SPI_InterruptGetStatus(cmsis_spi_interrupt_driver_state_t *spi) -{ - ARM_SPI_STATUS stat; - - if (spi->flags & SPI_FLAG_MASTER) - { - stat.busy = - ((spi->handle->masterHandle.txRemainingBytes > 0) || (spi->handle->masterHandle.rxRemainingBytes > 0)) ? - (0U) : - (1U); - stat.data_lost = (kStatus_SPI_Error == spi->handle->masterHandle.state) ? (1U) : (0U); - } - else - { - stat.busy = - ((spi->handle->slaveHandle.txRemainingBytes > 0) || (spi->handle->slaveHandle.rxRemainingBytes > 0)) ? - (0U) : - (1U); - stat.data_lost = (kStatus_SPI_Error == spi->handle->slaveHandle.state) ? (1U) : (0U); - } - stat.mode_fault = 0U; - stat.reserved = 0U; - - return stat; -} - -#endif - -#if defined(SPI0) && RTE_SPI0 - -/* User needs to provide the implementation for SPI0_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t SPI0_GetFreq(void); -extern void SPI0_InitPins(void); -extern void SPI0_DeinitPins(void); - -cmsis_spi_resource_t SPI0_Resource = {SPI0, 0, SPI0_GetFreq}; - -#if RTE_SPI0_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_spi_dma_resource_t SPI0_DMAResource = {RTE_SPI0_DMA_TX_DMA_BASE, RTE_SPI0_DMA_TX_CH, RTE_SPI0_DMA_RX_DMA_BASE, - RTE_SPI0_DMA_RX_CH}; - -static cmsis_spi_dma_handle_t SPI0_DmaHandle; -static dma_handle_t SPI0_DmaTxDataHandle; -static dma_handle_t SPI0_DmaRxDataHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi0_dma_driver_state") -static cmsis_spi_dma_driver_state_t SPI0_DMADriverState = { -#else -static cmsis_spi_dma_driver_state_t SPI0_DMADriverState = { -#endif - &SPI0_Resource, &SPI0_DMAResource, &SPI0_DmaHandle, &SPI0_DmaTxDataHandle, &SPI0_DmaRxDataHandle, - -}; - -static int32_t SPI0_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI0_InitPins(); - return SPI_DMAInitialize(cb_event, &SPI0_DMADriverState); -} - -static int32_t SPI0_DMAUninitialize(void) -{ - SPI0_DeinitPins(); - return SPI_DMAUninitialize(&SPI0_DMADriverState); -} - -static int32_t SPI0_DMAPowerControl(ARM_POWER_STATE state) -{ - return SPI_DMAPowerControl(state, &SPI0_DMADriverState); -} - -static int32_t SPI0_DMASend(const void *data, uint32_t num) -{ - return SPI_DMASend(data, num, &SPI0_DMADriverState); -} - -static int32_t SPI0_DMAReceive(void *data, uint32_t num) -{ - return SPI_DMAReceive(data, num, &SPI0_DMADriverState); -} - -static int32_t SPI0_DMATransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_DMATransfer(data_out, data_in, num, &SPI0_DMADriverState); -} - -static uint32_t SPI0_DMAGetCount(void) -{ - return SPI_DMAGetCount(&SPI0_DMADriverState); -} - -static int32_t SPI0_DMAControl(uint32_t control, uint32_t arg) -{ - return SPI_DMAControl(control, arg, &SPI0_DMADriverState); -} - -static ARM_SPI_STATUS SPI0_DMAGetStatus(void) -{ - return SPI_DMAGetStatus(&SPI0_DMADriverState); -} - -#endif - -#else - -static cmsis_spi_handle_t SPI0_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi0_interrupt_driver_state") -static cmsis_spi_interrupt_driver_state_t SPI0_InterruptDriverState = { -#else -static cmsis_spi_interrupt_driver_state_t SPI0_InterruptDriverState = { -#endif - &SPI0_Resource, &SPI0_Handle, -}; - -static int32_t SPI0_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI0_InitPins(); - return SPI_InterruptInitialize(cb_event, &SPI0_InterruptDriverState); -} - -static int32_t SPI0_InterruptUninitialize(void) -{ - SPI0_DeinitPins(); - return SPI_InterruptUninitialize(&SPI0_InterruptDriverState); -} - -static int32_t SPI0_InterruptPowerControl(ARM_POWER_STATE state) -{ - return SPI_InterruptPowerControl(state, &SPI0_InterruptDriverState); -} - -static int32_t SPI0_InterruptSend(const void *data, uint32_t num) -{ - return SPI_InterruptSend(data, num, &SPI0_InterruptDriverState); -} - -static int32_t SPI0_InterruptReceive(void *data, uint32_t num) -{ - return SPI_InterruptReceive(data, num, &SPI0_InterruptDriverState); -} - -static int32_t SPI0_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_InterruptTransfer(data_out, data_in, num, &SPI0_InterruptDriverState); -} - -static uint32_t SPI0_InterruptGetCount(void) -{ - return SPI_InterruptGetCount(&SPI0_InterruptDriverState); -} - -static int32_t SPI0_InterruptControl(uint32_t control, uint32_t arg) -{ - return SPI_InterruptControl(control, arg, &SPI0_InterruptDriverState); -} - -static ARM_SPI_STATUS SPI0_InterruptGetStatus(void) -{ - return SPI_InterruptGetStatus(&SPI0_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI0 = {SPIx_GetVersion, SPIx_GetCapabilities, -#if RTE_SPI0_DMA_EN - SPI0_DMAInitialize, SPI0_DMAUninitialize, SPI0_DMAPowerControl, SPI0_DMASend, - SPI0_DMAReceive, SPI0_DMATransfer, SPI0_DMAGetCount, SPI0_DMAControl, - SPI0_DMAGetStatus -#else - SPI0_InterruptInitialize, SPI0_InterruptUninitialize, SPI0_InterruptPowerControl, - SPI0_InterruptSend, SPI0_InterruptReceive, SPI0_InterruptTransfer, SPI0_InterruptGetCount, - SPI0_InterruptControl, SPI0_InterruptGetStatus -#endif -}; - -#endif /* SPI0 */ - -#if defined(SPI1) && RTE_SPI1 -/* User needs to provide the implementation for SPI1_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t SPI1_GetFreq(void); -extern void SPI1_InitPins(void); -extern void SPI1_DeinitPins(void); -cmsis_spi_resource_t SPI1_Resource = {SPI1, 1, SPI1_GetFreq}; - -#if RTE_SPI1_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_spi_dma_resource_t SPI1_DMAResource = {RTE_SPI1_DMA_TX_DMA_BASE, RTE_SPI1_DMA_TX_CH, RTE_SPI1_DMA_RX_DMA_BASE, - RTE_SPI1_DMA_RX_CH}; - -static cmsis_spi_dma_handle_t SPI1_DmaHandle; -static dma_handle_t SPI1_DmaTxDataHandle; -static dma_handle_t SPI1_DmaRxDataHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi1_dma_driver_state") -static cmsis_spi_dma_driver_state_t SPI1_DMADriverState = { -#else -static cmsis_spi_dma_driver_state_t SPI1_DMADriverState = { -#endif - &SPI1_Resource, &SPI1_DMAResource, &SPI1_DmaHandle, &SPI1_DmaRxDataHandle, &SPI1_DmaTxDataHandle, -}; - -static int32_t SPI1_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI1_InitPins(); - return SPI_DMAInitialize(cb_event, &SPI1_DMADriverState); -} - -static int32_t SPI1_DMAUninitialize(void) -{ - SPI1_DeinitPins(); - return SPI_DMAUninitialize(&SPI1_DMADriverState); -} - -static int32_t SPI1_DMAPowerControl(ARM_POWER_STATE state) -{ - return SPI_DMAPowerControl(state, &SPI1_DMADriverState); -} - -static int32_t SPI1_DMASend(const void *data, uint32_t num) -{ - return SPI_DMASend(data, num, &SPI1_DMADriverState); -} - -static int32_t SPI1_DMAReceive(void *data, uint32_t num) -{ - return SPI_DMAReceive(data, num, &SPI1_DMADriverState); -} - -static int32_t SPI1_DMATransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_DMATransfer(data_out, data_in, num, &SPI1_DMADriverState); -} - -static uint32_t SPI1_DMAGetCount(void) -{ - return SPI_DMAGetCount(&SPI1_DMADriverState); -} - -static int32_t SPI1_DMAControl(uint32_t control, uint32_t arg) -{ - return SPI_DMAControl(control, arg, &SPI1_DMADriverState); -} - -static ARM_SPI_STATUS SPI1_DMAGetStatus(void) -{ - return SPI_DMAGetStatus(&SPI1_DMADriverState); -} - -#endif - -#else - -static cmsis_spi_handle_t SPI1_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi1_interrupt_driver_state") -static cmsis_spi_interrupt_driver_state_t SPI1_InterruptDriverState = { -#else -static cmsis_spi_interrupt_driver_state_t SPI1_InterruptDriverState = { -#endif - &SPI1_Resource, &SPI1_Handle, -}; - -static int32_t SPI1_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI1_InitPins(); - return SPI_InterruptInitialize(cb_event, &SPI1_InterruptDriverState); -} - -static int32_t SPI1_InterruptUninitialize(void) -{ - SPI1_DeinitPins(); - return SPI_InterruptUninitialize(&SPI1_InterruptDriverState); -} - -static int32_t SPI1_InterruptPowerControl(ARM_POWER_STATE state) -{ - return SPI_InterruptPowerControl(state, &SPI1_InterruptDriverState); -} - -static int32_t SPI1_InterruptSend(const void *data, uint32_t num) -{ - return SPI_InterruptSend(data, num, &SPI1_InterruptDriverState); -} - -static int32_t SPI1_InterruptReceive(void *data, uint32_t num) -{ - return SPI_InterruptReceive(data, num, &SPI1_InterruptDriverState); -} - -static int32_t SPI1_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_InterruptTransfer(data_out, data_in, num, &SPI1_InterruptDriverState); -} - -static uint32_t SPI1_InterruptGetCount(void) -{ - return SPI_InterruptGetCount(&SPI1_InterruptDriverState); -} - -static int32_t SPI1_InterruptControl(uint32_t control, uint32_t arg) -{ - return SPI_InterruptControl(control, arg, &SPI1_InterruptDriverState); -} - -static ARM_SPI_STATUS SPI1_InterruptGetStatus(void) -{ - return SPI_InterruptGetStatus(&SPI1_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI1 = {SPIx_GetVersion, SPIx_GetCapabilities, -#if RTE_SPI1_DMA_EN - SPI1_DMAInitialize, SPI1_DMAUninitialize, SPI1_DMAPowerControl, SPI1_DMASend, - SPI1_DMAReceive, SPI1_DMATransfer, SPI1_DMAGetCount, SPI1_DMAControl, - SPI1_DMAGetStatus -#else - SPI1_InterruptInitialize, SPI1_InterruptUninitialize, SPI1_InterruptPowerControl, - SPI1_InterruptSend, SPI1_InterruptReceive, SPI1_InterruptTransfer, SPI1_InterruptGetCount, - SPI1_InterruptControl, SPI1_InterruptGetStatus -#endif -}; - -#endif /* SPI1 */ - -#if defined(SPI2) && RTE_SPI2 - -/* User needs to provide the implementation for SPI2_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t SPI2_GetFreq(void); -extern void SPI2_InitPins(void); -extern void SPI2_DeinitPins(void); - -cmsis_spi_resource_t SPI2_Resource = {SPI2, 2, SPI2_GetFreq}; - -#if RTE_SPI2_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_spi_dma_resource_t SPI2_DMAResource = {RTE_SPI2_DMA_TX_DMA_BASE, RTE_SPI2_DMA_TX_CH, RTE_SPI2_DMA_RX_DMA_BASE, - RTE_SPI2_DMA_RX_CH}; - -static cmsis_spi_dma_handle_t SPI2_DmaHandle; -static dma_handle_t SPI2_DmaTxDataHandle; -static dma_handle_t SPI2_DmaRxDataHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi2_dma_driver_state") -static cmsis_spi_dma_driver_state_t SPI2_DMADriverState = { -#else -static cmsis_spi_dma_driver_state_t SPI2_DMADriverState = { -#endif - &SPI2_Resource, &SPI2_DMAResource, &SPI2_DmaHandle, &SPI2_DmaRxDataHandle, &SPI2_DmaTxDataHandle, -}; - -static int32_t SPI2_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI2_InitPins(); - return SPI_DMAInitialize(cb_event, &SPI2_DMADriverState); -} - -static int32_t SPI2_DMAUninitialize(void) -{ - SPI2_DeinitPins(); - return SPI_DMAUninitialize(&SPI2_DMADriverState); -} - -static int32_t SPI2_DMAPowerControl(ARM_POWER_STATE state) -{ - return SPI_DMAPowerControl(state, &SPI2_DMADriverState); -} - -static int32_t SPI2_DMASend(const void *data, uint32_t num) -{ - return SPI_DMASend(data, num, &SPI2_DMADriverState); -} - -static int32_t SPI2_DMAReceive(void *data, uint32_t num) -{ - return SPI_DMAReceive(data, num, &SPI2_DMADriverState); -} - -static int32_t SPI2_DMATransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_DMATransfer(data_out, data_in, num, &SPI2_DMADriverState); -} - -static uint32_t SPI2_DMAGetCount(void) -{ - return SPI_DMAGetCount(&SPI2_DMADriverState); -} - -static int32_t SPI2_DMAControl(uint32_t control, uint32_t arg) -{ - return SPI_DMAControl(control, arg, &SPI2_DMADriverState); -} - -static ARM_SPI_STATUS SPI2_DMAGetStatus(void) -{ - return SPI_DMAGetStatus(&SPI2_DMADriverState); -} - -#endif - -#else - -static cmsis_spi_handle_t SPI2_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi2_interrupt_driver_state") -static cmsis_spi_interrupt_driver_state_t SPI2_InterruptDriverState = { -#else -static cmsis_spi_interrupt_driver_state_t SPI2_InterruptDriverState = { -#endif - &SPI2_Resource, &SPI2_Handle, -}; - -static int32_t SPI2_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI2_InitPins(); - return SPI_InterruptInitialize(cb_event, &SPI2_InterruptDriverState); -} - -static int32_t SPI2_InterruptUninitialize(void) -{ - SPI2_DeinitPins(); - return SPI_InterruptUninitialize(&SPI2_InterruptDriverState); -} - -static int32_t SPI2_InterruptPowerControl(ARM_POWER_STATE state) -{ - return SPI_InterruptPowerControl(state, &SPI2_InterruptDriverState); -} - -static int32_t SPI2_InterruptSend(const void *data, uint32_t num) -{ - return SPI_InterruptSend(data, num, &SPI2_InterruptDriverState); -} - -static int32_t SPI2_InterruptReceive(void *data, uint32_t num) -{ - return SPI_InterruptReceive(data, num, &SPI2_InterruptDriverState); -} - -static int32_t SPI2_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_InterruptTransfer(data_out, data_in, num, &SPI2_InterruptDriverState); -} - -static uint32_t SPI2_InterruptGetCount(void) -{ - return SPI_InterruptGetCount(&SPI2_InterruptDriverState); -} - -static int32_t SPI2_InterruptControl(uint32_t control, uint32_t arg) -{ - return SPI_InterruptControl(control, arg, &SPI2_InterruptDriverState); -} - -static ARM_SPI_STATUS SPI2_InterruptGetStatus(void) -{ - return SPI_InterruptGetStatus(&SPI2_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI2 = {SPIx_GetVersion, SPIx_GetCapabilities, -#if RTE_SPI2_DMA_EN - SPI2_DMAInitialize, SPI2_DMAUninitialize, SPI2_DMAPowerControl, SPI2_DMASend, - SPI2_DMAReceive, SPI2_DMATransfer, SPI2_DMAGetCount, SPI2_DMAControl, - SPI2_DMAGetStatus -#else - SPI2_InterruptInitialize, SPI2_InterruptUninitialize, SPI2_InterruptPowerControl, - SPI2_InterruptSend, SPI2_InterruptReceive, SPI2_InterruptTransfer, SPI2_InterruptGetCount, - SPI2_InterruptControl, SPI2_InterruptGetStatus -#endif -}; - -#endif /* SPI2 */ - -#if defined(SPI3) && RTE_SPI3 - -/* User needs to provide the implementation for SPI3_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t SPI3_GetFreq(void); -extern void SPI3_InitPins(void); -extern void SPI3_DeinitPins(void); - -cmsis_spi_resource_t SPI3_Resource = {SPI3, 3, SPI3_GetFreq}; - -#if RTE_SPI3_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_spi_dma_resource_t SPI3_DMAResource = {RTE_SPI3_DMA_TX_DMA_BASE, RTE_SPI3_DMA_TX_CH, RTE_SPI3_DMA_RX_DMA_BASE, - RTE_SPI3_DMA_RX_CH}; - -static cmsis_spi_dma_handle_t SPI3_DmaHandle; -static dma_handle_t SPI3_DmaTxDataHandle; -static dma_handle_t SPI3_DmaRxDataHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi3_dma_driver_state") -static cmsis_spi_dma_driver_state_t SPI3_DMADriverState = { -#else -static cmsis_spi_dma_driver_state_t SPI3_DMADriverState = { -#endif - &SPI3_Resource, &SPI3_DMAResource, &SPI3_DmaHandle, &SPI3_DmaRxDataHandle, &SPI3_DmaTxDataHandle, -}; - -static int32_t SPI3_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI3_InitPins(); - return SPI_DMAInitialize(cb_event, &SPI3_DMADriverState); -} - -static int32_t SPI3_DMAUninitialize(void) -{ - SPI3_DeinitPins(); - return SPI_DMAUninitialize(&SPI3_DMADriverState); -} - -static int32_t SPI3_DMAPowerControl(ARM_POWER_STATE state) -{ - return SPI_DMAPowerControl(state, &SPI3_DMADriverState); -} - -static int32_t SPI3_DMASend(const void *data, uint32_t num) -{ - return SPI_DMASend(data, num, &SPI3_DMADriverState); -} - -static int32_t SPI3_DMAReceive(void *data, uint32_t num) -{ - return SPI_DMAReceive(data, num, &SPI3_DMADriverState); -} - -static int32_t SPI3_DMATransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_DMATransfer(data_out, data_in, num, &SPI3_DMADriverState); -} - -static uint32_t SPI3_DMAGetCount(void) -{ - return SPI_DMAGetCount(&SPI3_DMADriverState); -} - -static int32_t SPI3_DMAControl(uint32_t control, uint32_t arg) -{ - return SPI_DMAControl(control, arg, &SPI3_DMADriverState); -} - -static ARM_SPI_STATUS SPI3_DMAGetStatus(void) -{ - return SPI_DMAGetStatus(&SPI3_DMADriverState); -} - -#endif - -#else - -static cmsis_spi_handle_t SPI3_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi3_interrupt_driver_state") -static cmsis_spi_interrupt_driver_state_t SPI3_InterruptDriverState = { -#else -static cmsis_spi_interrupt_driver_state_t SPI3_InterruptDriverState = { -#endif - &SPI3_Resource, &SPI3_Handle, -}; - -static int32_t SPI3_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI3_InitPins(); - return SPI_InterruptInitialize(cb_event, &SPI3_InterruptDriverState); -} - -static int32_t SPI3_InterruptUninitialize(void) -{ - SPI3_DeinitPins(); - return SPI_InterruptUninitialize(&SPI3_InterruptDriverState); -} - -static int32_t SPI3_InterruptPowerControl(ARM_POWER_STATE state) -{ - return SPI_InterruptPowerControl(state, &SPI3_InterruptDriverState); -} - -static int32_t SPI3_InterruptSend(const void *data, uint32_t num) -{ - return SPI_InterruptSend(data, num, &SPI3_InterruptDriverState); -} - -static int32_t SPI3_InterruptReceive(void *data, uint32_t num) -{ - return SPI_InterruptReceive(data, num, &SPI3_InterruptDriverState); -} - -static int32_t SPI3_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_InterruptTransfer(data_out, data_in, num, &SPI3_InterruptDriverState); -} - -static uint32_t SPI3_InterruptGetCount(void) -{ - return SPI_InterruptGetCount(&SPI3_InterruptDriverState); -} - -static int32_t SPI3_InterruptControl(uint32_t control, uint32_t arg) -{ - return SPI_InterruptControl(control, arg, &SPI3_InterruptDriverState); -} - -static ARM_SPI_STATUS SPI3_InterruptGetStatus(void) -{ - return SPI_InterruptGetStatus(&SPI3_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI3 = {SPIx_GetVersion, SPIx_GetCapabilities, -#if RTE_SPI3_DMA_EN - SPI3_DMAInitialize, SPI3_DMAUninitialize, SPI3_DMAPowerControl, SPI3_DMASend, - SPI3_DMAReceive, SPI3_DMATransfer, SPI3_DMAGetCount, SPI3_DMAControl, - SPI3_DMAGetStatus -#else - SPI3_InterruptInitialize, SPI3_InterruptUninitialize, SPI3_InterruptPowerControl, - SPI3_InterruptSend, SPI3_InterruptReceive, SPI3_InterruptTransfer, SPI3_InterruptGetCount, - SPI3_InterruptControl, SPI3_InterruptGetStatus -#endif -}; - -#endif /* SPI3 */ - -#if defined(SPI4) && RTE_SPI4 - -/* User needs to provide the implementation for SPI4_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t SPI4_GetFreq(void); -extern void SPI4_InitPins(void); -extern void SPI4_DeinitPins(void); - -cmsis_spi_resource_t SPI4_Resource = {SPI4, 4, SPI4_GetFreq}; - -#if RTE_SPI4_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_spi_dma_resource_t SPI4_DMAResource = {RTE_SPI4_DMA_TX_DMA_BASE, RTE_SPI4_DMA_TX_CH, RTE_SPI4_DMA_RX_DMA_BASE, - RTE_SPI4_DMA_RX_CH}; - -static cmsis_spi_dma_handle_t SPI4_DmaHandle; -static dma_handle_t SPI4_DmaTxDataHandle; -static dma_handle_t SPI4_DmaRxDataHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi4_dma_driver_state") -static cmsis_spi_dma_driver_state_t SPI4_DMADriverState = { -#else -static cmsis_spi_dma_driver_state_t SPI4_DMADriverState = { -#endif - &SPI4_Resource, &SPI4_DMAResource, &SPI4_DmaHandle, &SPI4_DmaRxDataHandle, &SPI4_DmaTxDataHandle, -}; - -static int32_t SPI4_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI4_InitPins(); - return SPI_DMAInitialize(cb_event, &SPI4_DMADriverState); -} - -static int32_t SPI4_DMAUninitialize(void) -{ - SPI4_DeinitPins(); - return SPI_DMAUninitialize(&SPI4_DMADriverState); -} - -static int32_t SPI4_DMAPowerControl(ARM_POWER_STATE state) -{ - return SPI_DMAPowerControl(state, &SPI4_DMADriverState); -} - -static int32_t SPI4_DMASend(const void *data, uint32_t num) -{ - return SPI_DMASend(data, num, &SPI4_DMADriverState); -} - -static int32_t SPI4_DMAReceive(void *data, uint32_t num) -{ - return SPI_DMAReceive(data, num, &SPI4_DMADriverState); -} - -static int32_t SPI4_DMATransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_DMATransfer(data_out, data_in, num, &SPI4_DMADriverState); -} - -static uint32_t SPI4_DMAGetCount(void) -{ - return SPI_DMAGetCount(&SPI4_DMADriverState); -} - -static int32_t SPI4_DMAControl(uint32_t control, uint32_t arg) -{ - return SPI_DMAControl(control, arg, &SPI4_DMADriverState); -} - -static ARM_SPI_STATUS SPI4_DMAGetStatus(void) -{ - return SPI_DMAGetStatus(&SPI4_DMADriverState); -} - -#endif - -#else - -static cmsis_spi_handle_t SPI4_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi4_interrupt_driver_state") -static cmsis_spi_interrupt_driver_state_t SPI4_InterruptDriverState = { -#else -static cmsis_spi_interrupt_driver_state_t SPI4_InterruptDriverState = { -#endif - &SPI4_Resource, &SPI4_Handle, -}; - -static int32_t SPI4_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI4_InitPins(); - return SPI_InterruptInitialize(cb_event, &SPI4_InterruptDriverState); -} - -static int32_t SPI4_InterruptUninitialize(void) -{ - SPI4_DeinitPins(); - return SPI_InterruptUninitialize(&SPI4_InterruptDriverState); -} - -static int32_t SPI4_InterruptPowerControl(ARM_POWER_STATE state) -{ - return SPI_InterruptPowerControl(state, &SPI4_InterruptDriverState); -} - -static int32_t SPI4_InterruptSend(const void *data, uint32_t num) -{ - return SPI_InterruptSend(data, num, &SPI4_InterruptDriverState); -} - -static int32_t SPI4_InterruptReceive(void *data, uint32_t num) -{ - return SPI_InterruptReceive(data, num, &SPI4_InterruptDriverState); -} - -static int32_t SPI4_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_InterruptTransfer(data_out, data_in, num, &SPI4_InterruptDriverState); -} - -static uint32_t SPI4_InterruptGetCount(void) -{ - return SPI_InterruptGetCount(&SPI4_InterruptDriverState); -} - -static int32_t SPI4_InterruptControl(uint32_t control, uint32_t arg) -{ - return SPI_InterruptControl(control, arg, &SPI4_InterruptDriverState); -} - -static ARM_SPI_STATUS SPI4_InterruptGetStatus(void) -{ - return SPI_InterruptGetStatus(&SPI4_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI4 = {SPIx_GetVersion, SPIx_GetCapabilities, -#if RTE_SPI4_DMA_EN - SPI4_DMAInitialize, SPI4_DMAUninitialize, SPI4_DMAPowerControl, SPI4_DMASend, - SPI4_DMAReceive, SPI4_DMATransfer, SPI4_DMAGetCount, SPI4_DMAControl, - SPI4_DMAGetStatus -#else - SPI4_InterruptInitialize, SPI4_InterruptUninitialize, SPI4_InterruptPowerControl, - SPI4_InterruptSend, SPI4_InterruptReceive, SPI4_InterruptTransfer, SPI4_InterruptGetCount, - SPI4_InterruptControl, SPI4_InterruptGetStatus -#endif -}; - -#endif /* SPI4 */ - -#if defined(SPI5) && RTE_SPI5 - -/* User needs to provide the implementation for SPI5_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t SPI5_GetFreq(void); -extern void SPI5_InitPins(void); -extern void SPI5_DeinitPins(void); - -cmsis_spi_resource_t SPI5_Resource = {SPI5, 5, SPI5_GetFreq}; - -#if RTE_SPI5_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_spi_dma_resource_t SPI5_DMAResource = {RTE_SPI5_DMA_TX_DMA_BASE, RTE_SPI5_DMA_TX_CH, RTE_SPI5_DMA_RX_DMA_BASE, - RTE_SPI5_DMA_RX_CH}; - -static cmsis_spi_dma_handle_t SPI5_DmaHandle; -static dma_handle_t SPI5_DmaTxDataHandle; -static dma_handle_t SPI5_DmaRxDataHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi5_dma_driver_state") -static cmsis_spi_dma_driver_state_t SPI5_DMADriverState = { -#else -static cmsis_spi_dma_driver_state_t SPI5_DMADriverState = { -#endif - &SPI5_Resource, &SPI5_DMAResource, &SPI5_DmaHandle, &SPI5_DmaRxDataHandle, &SPI5_DmaTxDataHandle, -}; - -static int32_t SPI5_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI5_InitPins(); - return SPI_DMAInitialize(cb_event, &SPI5_DMADriverState); -} - -static int32_t SPI5_DMAUninitialize(void) -{ - SPI5_DeinitPins(); - return SPI_DMAUninitialize(&SPI5_DMADriverState); -} - -static int32_t SPI5_DMAPowerControl(ARM_POWER_STATE state) -{ - return SPI_DMAPowerControl(state, &SPI5_DMADriverState); -} - -static int32_t SPI5_DMASend(const void *data, uint32_t num) -{ - return SPI_DMASend(data, num, &SPI5_DMADriverState); -} - -static int32_t SPI5_DMAReceive(void *data, uint32_t num) -{ - return SPI_DMAReceive(data, num, &SPI5_DMADriverState); -} - -static int32_t SPI5_DMATransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_DMATransfer(data_out, data_in, num, &SPI5_DMADriverState); -} - -static uint32_t SPI5_DMAGetCount(void) -{ - return SPI_DMAGetCount(&SPI5_DMADriverState); -} - -static int32_t SPI5_DMAControl(uint32_t control, uint32_t arg) -{ - return SPI_DMAControl(control, arg, &SPI5_DMADriverState); -} - -static ARM_SPI_STATUS SPI5_DMAGetStatus(void) -{ - return SPI_DMAGetStatus(&SPI5_DMADriverState); -} - -#endif - -#else - -static cmsis_spi_handle_t SPI5_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi5_interrupt_driver_state") -static cmsis_spi_interrupt_driver_state_t SPI5_InterruptDriverState = { -#else -static cmsis_spi_interrupt_driver_state_t SPI5_InterruptDriverState = { -#endif - &SPI5_Resource, &SPI5_Handle, -}; - -static int32_t SPI5_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI5_InitPins(); - return SPI_InterruptInitialize(cb_event, &SPI5_InterruptDriverState); -} - -static int32_t SPI5_InterruptUninitialize(void) -{ - SPI5_DeinitPins(); - return SPI_InterruptUninitialize(&SPI5_InterruptDriverState); -} - -static int32_t SPI5_InterruptPowerControl(ARM_POWER_STATE state) -{ - return SPI_InterruptPowerControl(state, &SPI5_InterruptDriverState); -} - -static int32_t SPI5_InterruptSend(const void *data, uint32_t num) -{ - return SPI_InterruptSend(data, num, &SPI5_InterruptDriverState); -} - -static int32_t SPI5_InterruptReceive(void *data, uint32_t num) -{ - return SPI_InterruptReceive(data, num, &SPI5_InterruptDriverState); -} - -static int32_t SPI5_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_InterruptTransfer(data_out, data_in, num, &SPI5_InterruptDriverState); -} - -static uint32_t SPI5_InterruptGetCount(void) -{ - return SPI_InterruptGetCount(&SPI5_InterruptDriverState); -} - -static int32_t SPI5_InterruptControl(uint32_t control, uint32_t arg) -{ - return SPI_InterruptControl(control, arg, &SPI5_InterruptDriverState); -} - -static ARM_SPI_STATUS SPI5_InterruptGetStatus(void) -{ - return SPI_InterruptGetStatus(&SPI5_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI5 = {SPIx_GetVersion, SPIx_GetCapabilities, -#if RTE_SPI5_DMA_EN - SPI5_DMAInitialize, SPI5_DMAUninitialize, SPI5_DMAPowerControl, SPI5_DMASend, - SPI5_DMAReceive, SPI5_DMATransfer, SPI5_DMAGetCount, SPI5_DMAControl, - SPI5_DMAGetStatus -#else - SPI5_InterruptInitialize, SPI5_InterruptUninitialize, SPI5_InterruptPowerControl, - SPI5_InterruptSend, SPI5_InterruptReceive, SPI5_InterruptTransfer, SPI5_InterruptGetCount, - SPI5_InterruptControl, SPI5_InterruptGetStatus -#endif -}; - -#endif /* SPI5 */ - -#if defined(SPI6) && RTE_SPI6 - -/* User needs to provide the implementation for SPI6_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t SPI6_GetFreq(void); -extern void SPI6_InitPins(void); -extern void SPI6_DeinitPins(void); - -cmsis_spi_resource_t SPI6_Resource = {SPI6, 6, SPI6_GetFreq}; - -#if RTE_SPI6_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_spi_dma_resource_t SPI6_DMAResource = {RTE_SPI6_DMA_TX_DMA_BASE, RTE_SPI6_DMA_TX_CH, RTE_SPI6_DMA_RX_DMA_BASE, - RTE_SPI6_DMA_RX_CH}; - -static cmsis_spi_dma_handle_t SPI6_DmaHandle; -static dma_handle_t SPI6_DmaTxDataHandle; -static dma_handle_t SPI6_DmaRxDataHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi6_dma_driver_state") -static cmsis_spi_dma_driver_state_t SPI6_DMADriverState = { -#else -static cmsis_spi_dma_driver_state_t SPI6_DMADriverState = { -#endif - &SPI6_Resource, &SPI6_DMAResource, &SPI6_DmaHandle, &SPI6_DmaRxDataHandle, &SPI6_DmaTxDataHandle, -}; - -static int32_t SPI6_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI6_InitPins(); - return SPI_DMAInitialize(cb_event, &SPI6_DMADriverState); -} - -static int32_t SPI6_DMAUninitialize(void) -{ - SPI6_DeinitPins(); - return SPI_DMAUninitialize(&SPI6_DMADriverState); -} - -static int32_t SPI6_DMAPowerControl(ARM_POWER_STATE state) -{ - return SPI_DMAPowerControl(state, &SPI6_DMADriverState); -} - -static int32_t SPI6_DMASend(const void *data, uint32_t num) -{ - return SPI_DMASend(data, num, &SPI6_DMADriverState); -} - -static int32_t SPI6_DMAReceive(void *data, uint32_t num) -{ - return SPI_DMAReceive(data, num, &SPI6_DMADriverState); -} - -static int32_t SPI6_DMATransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_DMATransfer(data_out, data_in, num, &SPI6_DMADriverState); -} - -static uint32_t SPI6_DMAGetCount(void) -{ - return SPI_DMAGetCount(&SPI6_DMADriverState); -} - -static int32_t SPI6_DMAControl(uint32_t control, uint32_t arg) -{ - return SPI_DMAControl(control, arg, &SPI6_DMADriverState); -} - -static ARM_SPI_STATUS SPI6_DMAGetStatus(void) -{ - return SPI_DMAGetStatus(&SPI6_DMADriverState); -} - -#endif - -#else - -static cmsis_spi_handle_t SPI6_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi6_interrupt_driver_state") -static cmsis_spi_interrupt_driver_state_t SPI6_InterruptDriverState = { -#else -static cmsis_spi_interrupt_driver_state_t SPI6_InterruptDriverState = { -#endif - &SPI6_Resource, &SPI6_Handle, -}; - -static int32_t SPI6_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI6_InitPins(); - return SPI_InterruptInitialize(cb_event, &SPI6_InterruptDriverState); -} - -static int32_t SPI6_InterruptUninitialize(void) -{ - SPI6_DeinitPins(); - return SPI_InterruptUninitialize(&SPI6_InterruptDriverState); -} - -static int32_t SPI6_InterruptPowerControl(ARM_POWER_STATE state) -{ - return SPI_InterruptPowerControl(state, &SPI6_InterruptDriverState); -} - -static int32_t SPI6_InterruptSend(const void *data, uint32_t num) -{ - return SPI_InterruptSend(data, num, &SPI6_InterruptDriverState); -} - -static int32_t SPI6_InterruptReceive(void *data, uint32_t num) -{ - return SPI_InterruptReceive(data, num, &SPI6_InterruptDriverState); -} - -static int32_t SPI6_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_InterruptTransfer(data_out, data_in, num, &SPI6_InterruptDriverState); -} - -static uint32_t SPI6_InterruptGetCount(void) -{ - return SPI_InterruptGetCount(&SPI6_InterruptDriverState); -} - -static int32_t SPI6_InterruptControl(uint32_t control, uint32_t arg) -{ - return SPI_InterruptControl(control, arg, &SPI6_InterruptDriverState); -} - -static ARM_SPI_STATUS SPI6_InterruptGetStatus(void) -{ - return SPI_InterruptGetStatus(&SPI6_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI6 = {SPIx_GetVersion, SPIx_GetCapabilities, -#if RTE_SPI6_DMA_EN - SPI6_DMAInitialize, SPI6_DMAUninitialize, SPI6_DMAPowerControl, SPI6_DMASend, - SPI6_DMAReceive, SPI6_DMATransfer, SPI6_DMAGetCount, SPI6_DMAControl, - SPI6_DMAGetStatus -#else - SPI6_InterruptInitialize, SPI6_InterruptUninitialize, SPI6_InterruptPowerControl, - SPI6_InterruptSend, SPI6_InterruptReceive, SPI6_InterruptTransfer, SPI6_InterruptGetCount, - SPI6_InterruptControl, SPI6_InterruptGetStatus -#endif -}; - -#endif /* SPI6 */ - -#if defined(SPI7) && RTE_SPI7 - -/* User needs to provide the implementation for SPI7_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t SPI7_GetFreq(void); -extern void SPI7_InitPins(void); -extern void SPI7_DeinitPins(void); - -cmsis_spi_resource_t SPI7_Resource = {SPI7, 7, SPI7_GetFreq}; - -#if RTE_SPI7_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_spi_dma_resource_t SPI7_DMAResource = {RTE_SPI7_DMA_TX_DMA_BASE, RTE_SPI7_DMA_TX_CH, RTE_SPI7_DMA_RX_DMA_BASE, - RTE_SPI7_DMA_RX_CH}; - -static cmsis_spi_dma_handle_t SPI7_DmaHandle; -static dma_handle_t SPI7_DmaTxDataHandle; -static dma_handle_t SPI7_DmaRxDataHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi7_dma_driver_state") -static cmsis_spi_dma_driver_state_t SPI7_DMADriverState = { -#else -static cmsis_spi_dma_driver_state_t SPI7_DMADriverState = { -#endif - &SPI7_Resource, &SPI7_DMAResource, &SPI7_DmaHandle, &SPI7_DmaRxDataHandle, &SPI7_DmaTxDataHandle, -}; - -static int32_t SPI7_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI7_InitPins(); - return SPI_DMAInitialize(cb_event, &SPI7_DMADriverState); -} - -static int32_t SPI7_DMAUninitialize(void) -{ - SPI7_DeinitPins(); - return SPI_DMAUninitialize(&SPI7_DMADriverState); -} - -static int32_t SPI7_DMAPowerControl(ARM_POWER_STATE state) -{ - return SPI_DMAPowerControl(state, &SPI7_DMADriverState); -} - -static int32_t SPI7_DMASend(const void *data, uint32_t num) -{ - return SPI_DMASend(data, num, &SPI7_DMADriverState); -} - -static int32_t SPI7_DMAReceive(void *data, uint32_t num) -{ - return SPI_DMAReceive(data, num, &SPI7_DMADriverState); -} - -static int32_t SPI7_DMATransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_DMATransfer(data_out, data_in, num, &SPI7_DMADriverState); -} - -static uint32_t SPI7_DMAGetCount(void) -{ - return SPI_DMAGetCount(&SPI7_DMADriverState); -} - -static int32_t SPI7_DMAControl(uint32_t control, uint32_t arg) -{ - return SPI_DMAControl(control, arg, &SPI7_DMADriverState); -} - -static ARM_SPI_STATUS SPI7_DMAGetStatus(void) -{ - return SPI_DMAGetStatus(&SPI7_DMADriverState); -} - -#endif - -#else - -static cmsis_spi_handle_t SPI7_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi7_interrupt_driver_state") -static cmsis_spi_interrupt_driver_state_t SPI7_InterruptDriverState = { -#else -static cmsis_spi_interrupt_driver_state_t SPI7_InterruptDriverState = { -#endif - &SPI7_Resource, &SPI7_Handle, -}; - -static int32_t SPI7_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI7_InitPins(); - return SPI_InterruptInitialize(cb_event, &SPI7_InterruptDriverState); -} - -static int32_t SPI7_InterruptUninitialize(void) -{ - SPI7_DeinitPins(); - return SPI_InterruptUninitialize(&SPI7_InterruptDriverState); -} - -static int32_t SPI7_InterruptPowerControl(ARM_POWER_STATE state) -{ - return SPI_InterruptPowerControl(state, &SPI7_InterruptDriverState); -} - -static int32_t SPI7_InterruptSend(const void *data, uint32_t num) -{ - return SPI_InterruptSend(data, num, &SPI7_InterruptDriverState); -} - -static int32_t SPI7_InterruptReceive(void *data, uint32_t num) -{ - return SPI_InterruptReceive(data, num, &SPI7_InterruptDriverState); -} - -static int32_t SPI7_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_InterruptTransfer(data_out, data_in, num, &SPI7_InterruptDriverState); -} - -static uint32_t SPI7_InterruptGetCount(void) -{ - return SPI_InterruptGetCount(&SPI7_InterruptDriverState); -} - -static int32_t SPI7_InterruptControl(uint32_t control, uint32_t arg) -{ - return SPI_InterruptControl(control, arg, &SPI7_InterruptDriverState); -} - -static ARM_SPI_STATUS SPI7_InterruptGetStatus(void) -{ - return SPI_InterruptGetStatus(&SPI7_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI7 = {SPIx_GetVersion, SPIx_GetCapabilities, -#if RTE_SPI7_DMA_EN - SPI7_DMAInitialize, SPI7_DMAUninitialize, SPI7_DMAPowerControl, SPI7_DMASend, - SPI7_DMAReceive, SPI7_DMATransfer, SPI7_DMAGetCount, SPI7_DMAControl, - SPI7_DMAGetStatus -#else - SPI7_InterruptInitialize, SPI7_InterruptUninitialize, SPI7_InterruptPowerControl, - SPI7_InterruptSend, SPI7_InterruptReceive, SPI7_InterruptTransfer, SPI7_InterruptGetCount, - SPI7_InterruptControl, SPI7_InterruptGetStatus -#endif -}; - -#endif /* SPI7 */ - -#if defined(SPI8) && RTE_SPI8 - -/* User needs to provide the implementation for SPI8_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t SPI8_GetFreq(void); -extern void SPI8_InitPins(void); -extern void SPI8_DeinitPins(void); - -cmsis_spi_resource_t SPI8_Resource = {SPI8, 8, SPI8_GetFreq}; - -#if RTE_SPI8_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_spi_dma_resource_t SPI8_DMAResource = {RTE_SPI8_DMA_TX_DMA_BASE, RTE_SPI8_DMA_TX_CH, RTE_SPI8_DMA_RX_DMA_BASE, - RTE_SPI8_DMA_RX_CH}; - -static cmsis_spi_dma_handle_t SPI8_DmaHandle; -static dma_handle_t SPI8_DmaTxDataHandle; -static dma_handle_t SPI8_DmaRxDataHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi8_dma_driver_state") -static cmsis_spi_dma_driver_state_t SPI8_DMADriverState = { -#else -static cmsis_spi_dma_driver_state_t SPI8_DMADriverState = { -#endif - &SPI8_Resource, &SPI8_DMAResource, &SPI8_DmaHandle, &SPI8_DmaRxDataHandle, &SPI8_DmaTxDataHandle, -}; - -static int32_t SPI8_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI8_InitPins(); - return SPI_DMAInitialize(cb_event, &SPI8_DMADriverState); -} - -static int32_t SPI8_DMAUninitialize(void) -{ - SPI8_DeinitPins(); - return SPI_DMAUninitialize(&SPI8_DMADriverState); -} - -static int32_t SPI8_DMAPowerControl(ARM_POWER_STATE state) -{ - return SPI_DMAPowerControl(state, &SPI8_DMADriverState); -} - -static int32_t SPI8_DMASend(const void *data, uint32_t num) -{ - return SPI_DMASend(data, num, &SPI8_DMADriverState); -} - -static int32_t SPI8_DMAReceive(void *data, uint32_t num) -{ - return SPI_DMAReceive(data, num, &SPI8_DMADriverState); -} - -static int32_t SPI8_DMATransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_DMATransfer(data_out, data_in, num, &SPI8_DMADriverState); -} - -static uint32_t SPI8_DMAGetCount(void) -{ - return SPI_DMAGetCount(&SPI8_DMADriverState); -} - -static int32_t SPI8_DMAControl(uint32_t control, uint32_t arg) -{ - return SPI_DMAControl(control, arg, &SPI8_DMADriverState); -} - -static ARM_SPI_STATUS SPI8_DMAGetStatus(void) -{ - return SPI_DMAGetStatus(&SPI8_DMADriverState); -} - -#endif - -#else - -static cmsis_spi_handle_t SPI8_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi8_interrupt_driver_state") -static cmsis_spi_interrupt_driver_state_t SPI8_InterruptDriverState = { -#else -static cmsis_spi_interrupt_driver_state_t SPI8_InterruptDriverState = { -#endif - &SPI8_Resource, &SPI8_Handle, -}; - -static int32_t SPI8_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI8_InitPins(); - return SPI_InterruptInitialize(cb_event, &SPI8_InterruptDriverState); -} - -static int32_t SPI8_InterruptUninitialize(void) -{ - SPI8_DeinitPins(); - return SPI_InterruptUninitialize(&SPI8_InterruptDriverState); -} - -static int32_t SPI8_InterruptPowerControl(ARM_POWER_STATE state) -{ - return SPI_InterruptPowerControl(state, &SPI8_InterruptDriverState); -} - -static int32_t SPI8_InterruptSend(const void *data, uint32_t num) -{ - return SPI_InterruptSend(data, num, &SPI8_InterruptDriverState); -} - -static int32_t SPI8_InterruptReceive(void *data, uint32_t num) -{ - return SPI_InterruptReceive(data, num, &SPI8_InterruptDriverState); -} - -static int32_t SPI8_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_InterruptTransfer(data_out, data_in, num, &SPI8_InterruptDriverState); -} - -static uint32_t SPI8_InterruptGetCount(void) -{ - return SPI_InterruptGetCount(&SPI8_InterruptDriverState); -} - -static int32_t SPI8_InterruptControl(uint32_t control, uint32_t arg) -{ - return SPI_InterruptControl(control, arg, &SPI8_InterruptDriverState); -} - -static ARM_SPI_STATUS SPI8_InterruptGetStatus(void) -{ - return SPI_InterruptGetStatus(&SPI8_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI8 = {SPIx_GetVersion, SPIx_GetCapabilities, -#if RTE_SPI8_DMA_EN - SPI8_DMAInitialize, SPI8_DMAUninitialize, SPI8_DMAPowerControl, SPI8_DMASend, - SPI8_DMAReceive, SPI8_DMATransfer, SPI8_DMAGetCount, SPI8_DMAControl, - SPI8_DMAGetStatus -#else - SPI8_InterruptInitialize, SPI8_InterruptUninitialize, SPI8_InterruptPowerControl, - SPI8_InterruptSend, SPI8_InterruptReceive, SPI8_InterruptTransfer, SPI8_InterruptGetCount, - SPI8_InterruptControl, SPI8_InterruptGetStatus -#endif -}; - -#endif /* SPI8 */ - -#if defined(SPI9) && RTE_SPI9 - -/* User needs to provide the implementation for SPI9_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t SPI9_GetFreq(void); -extern void SPI9_InitPins(void); -extern void SPI9_DeinitPins(void); - -cmsis_spi_resource_t SPI9_Resource = {SPI9, 9, SPI9_GetFreq}; - -#if RTE_SPI9_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_spi_dma_resource_t SPI9_DMAResource = {RTE_SPI9_DMA_TX_DMA_BASE, RTE_SPI9_DMA_TX_CH, RTE_SPI9_DMA_RX_DMA_BASE, - RTE_SPI9_DMA_RX_CH}; - -static cmsis_spi_dma_handle_t SPI9_DmaHandle; -static dma_handle_t SPI9_DmaTxDataHandle; -static dma_handle_t SPI9_DmaRxDataHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi9_dma_driver_state") -static cmsis_spi_dma_driver_state_t SPI9_DMADriverState = { -#else -static cmsis_spi_dma_driver_state_t SPI9_DMADriverState = { -#endif - &SPI9_Resource, &SPI9_DMAResource, &SPI9_DmaHandle, &SPI9_DmaRxDataHandle, &SPI9_DmaTxDataHandle, -}; - -static int32_t SPI9_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI9_InitPins(); - return SPI_DMAInitialize(cb_event, &SPI9_DMADriverState); -} - -static int32_t SPI9_DMAUninitialize(void) -{ - SPI9_DeinitPins(); - return SPI_DMAUninitialize(&SPI9_DMADriverState); -} - -static int32_t SPI9_DMAPowerControl(ARM_POWER_STATE state) -{ - return SPI_DMAPowerControl(state, &SPI9_DMADriverState); -} - -static int32_t SPI9_DMASend(const void *data, uint32_t num) -{ - return SPI_DMASend(data, num, &SPI9_DMADriverState); -} - -static int32_t SPI9_DMAReceive(void *data, uint32_t num) -{ - return SPI_DMAReceive(data, num, &SPI9_DMADriverState); -} - -static int32_t SPI9_DMATransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_DMATransfer(data_out, data_in, num, &SPI9_DMADriverState); -} - -static uint32_t SPI9_DMAGetCount(void) -{ - return SPI_DMAGetCount(&SPI9_DMADriverState); -} - -static int32_t SPI9_DMAControl(uint32_t control, uint32_t arg) -{ - return SPI_DMAControl(control, arg, &SPI9_DMADriverState); -} - -static ARM_SPI_STATUS SPI9_DMAGetStatus(void) -{ - return SPI_DMAGetStatus(&SPI9_DMADriverState); -} - -#endif - -#else - -static cmsis_spi_handle_t SPI9_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi9_interrupt_driver_state") -static cmsis_spi_interrupt_driver_state_t SPI9_InterruptDriverState = { -#else -static cmsis_spi_interrupt_driver_state_t SPI9_InterruptDriverState = { -#endif - &SPI9_Resource, &SPI9_Handle, -}; - -static int32_t SPI9_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI9_InitPins(); - return SPI_InterruptInitialize(cb_event, &SPI9_InterruptDriverState); -} - -static int32_t SPI9_InterruptUninitialize(void) -{ - SPI9_DeinitPins(); - return SPI_InterruptUninitialize(&SPI9_InterruptDriverState); -} - -static int32_t SPI9_InterruptPowerControl(ARM_POWER_STATE state) -{ - return SPI_InterruptPowerControl(state, &SPI9_InterruptDriverState); -} - -static int32_t SPI9_InterruptSend(const void *data, uint32_t num) -{ - return SPI_InterruptSend(data, num, &SPI9_InterruptDriverState); -} - -static int32_t SPI9_InterruptReceive(void *data, uint32_t num) -{ - return SPI_InterruptReceive(data, num, &SPI9_InterruptDriverState); -} - -static int32_t SPI9_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_InterruptTransfer(data_out, data_in, num, &SPI9_InterruptDriverState); -} - -static uint32_t SPI9_InterruptGetCount(void) -{ - return SPI_InterruptGetCount(&SPI9_InterruptDriverState); -} - -static int32_t SPI9_InterruptControl(uint32_t control, uint32_t arg) -{ - return SPI_InterruptControl(control, arg, &SPI9_InterruptDriverState); -} - -static ARM_SPI_STATUS SPI9_InterruptGetStatus(void) -{ - return SPI_InterruptGetStatus(&SPI9_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI9 = {SPIx_GetVersion, SPIx_GetCapabilities, -#if RTE_SPI9_DMA_EN - SPI9_DMAInitialize, SPI9_DMAUninitialize, SPI9_DMAPowerControl, SPI9_DMASend, - SPI9_DMAReceive, SPI9_DMATransfer, SPI9_DMAGetCount, SPI9_DMAControl, - SPI9_DMAGetStatus -#else - SPI9_InterruptInitialize, SPI9_InterruptUninitialize, SPI9_InterruptPowerControl, - SPI9_InterruptSend, SPI9_InterruptReceive, SPI9_InterruptTransfer, SPI9_InterruptGetCount, - SPI9_InterruptControl, SPI9_InterruptGetStatus -#endif -}; - -#endif /* SPI9 */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_spi_cmsis.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_spi_cmsis.h deleted file mode 100644 index f4f93e6a3c7..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_spi_cmsis.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2013-2016 ARM Limited. All rights reserved. - * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. - * Copyright 2016-2017 NXP. Not a Contribution. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _FSL_SPI_CMSIS_H_ -#define _FSL_SPI_CMSIS_H_ - -#include "fsl_spi.h" -#include "RTE_Device.h" -#include "Driver_SPI.h" -#if defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT) -#include "fsl_spi_dma.h" -#endif - -#if defined(SPI0) -extern ARM_DRIVER_SPI Driver_SPI0; -#endif /* SPI0 */ - -#if defined(SPI1) -extern ARM_DRIVER_SPI Driver_SPI1; -#endif /* SPI1 */ - -#if defined(SPI2) -extern ARM_DRIVER_SPI Driver_SPI2; -#endif /* SPI2 */ - -#if defined(SPI3) -extern ARM_DRIVER_SPI Driver_SPI3; -#endif /* SPI3 */ - -#if defined(SPI4) -extern ARM_DRIVER_SPI Driver_SPI4; -#endif /* SPI4 */ - -#if defined(SPI5) -extern ARM_DRIVER_SPI Driver_SPI5; -#endif /* SPI5 */ - -#if defined(SPI6) -extern ARM_DRIVER_SPI Driver_SPI6; -#endif /* SPI6 */ - -#if defined(SPI7) -extern ARM_DRIVER_SPI Driver_SPI7; -#endif /* SPI7 */ - -#if defined(SPI8) -extern ARM_DRIVER_SPI Driver_SPI8; -#endif /* SPI8 */ - -#if defined(SPI9) -extern ARM_DRIVER_SPI Driver_SPI9; -#endif /* SPI9 */ - -#define SPI_FLAG_UNINIT (0) -#define SPI_FLAG_INIT (1 << 0) -#define SPI_FLAG_POWER (1 << 1) -#define SPI_FLAG_CONFIGURED (1 << 2) -#define SPI_FLAG_MASTER (1 << 3) - -#endif diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_usart_cmsis.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_usart_cmsis.c deleted file mode 100644 index ce87f559246..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_usart_cmsis.c +++ /dev/null @@ -1,2713 +0,0 @@ -/* - * Copyright (c) 2013-2016 ARM Limited. All rights reserved. - * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. - * Copyright 2016-2017 NXP. Not a Contribution. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#include "fsl_usart_cmsis.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_cmsis" -#endif - - -#if (RTE_USART0 || RTE_USART1 || RTE_USART2 || RTE_USART3 || RTE_USART4 || RTE_USART5 || RTE_USART6 || RTE_USART7 || \ - RTE_USART8 || RTE_USART9) - -#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) - -/* - * ARMCC does not support split the data section automatically, so the driver - * needs to split the data to separate sections explicitly, to reduce codesize. - */ -#if defined(__CC_ARM) -#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) -#endif - -typedef const struct _cmsis_usart_resource -{ - USART_Type *base; /*!< usart peripheral base address. */ - uint32_t (*GetFreq)(void); /*!< Function to get the clock frequency. */ -} cmsis_usart_resource_t; - -typedef struct _cmsis_usart_non_blocking_driver_state -{ - cmsis_usart_resource_t *resource; /*!< Basic usart resource. */ - usart_handle_t *handle; /*!< Interupt transfer handle. */ - ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */ - uint8_t flags; /*!< Control and state flags. */ -} cmsis_usart_non_blocking_driver_state_t; - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) -typedef const struct _cmsis_usart_dma_resource -{ - DMA_Type *txDmaBase; /*!< DMA peripheral base address for TX. */ - uint32_t txDmaChannel; /*!< DMA channel for usart TX. */ - - DMA_Type *rxDmaBase; /*!< DMA peripheral base address for RX. */ - uint32_t rxDmaChannel; /*!< DMA channel for usart RX. */ -} cmsis_usart_dma_resource_t; - -typedef struct _cmsis_usart_dma_driver_state -{ - cmsis_usart_resource_t *resource; /*!< usart basic resource. */ - cmsis_usart_dma_resource_t *dmaResource; /*!< usart DMA resource. */ - usart_dma_handle_t *handle; /*!< usart DMA transfer handle. */ - dma_handle_t *rxHandle; /*!< DMA RX handle. */ - dma_handle_t *txHandle; /*!< DMA TX handle. */ - ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */ - uint8_t flags; /*!< Control and state flags. */ -} cmsis_usart_dma_driver_state_t; -#endif - -enum _usart_transfer_states -{ - kUSART_TxIdle, /*!< TX idle. */ - kUSART_TxBusy, /*!< TX busy. */ - kUSART_RxIdle, /*!< RX idle. */ - kUSART_RxBusy /*!< RX busy. */ -}; - -/* Driver Version */ -static const ARM_DRIVER_VERSION s_usartDriverVersion = {ARM_USART_API_VERSION, ARM_USART_DRV_VERSION}; - -static const ARM_USART_CAPABILITIES s_usartDriverCapabilities = { - 1, /* supports usart (Asynchronous) mode */ - 0, /* supports Synchronous Master mode */ - 0, /* supports Synchronous Slave mode */ - 0, /* supports usart Single-wire mode */ - 0, /* supports usart IrDA mode */ - 0, /* supports usart Smart Card mode */ - 0, /* Smart Card Clock generator */ - 0, /* RTS Flow Control available */ - 0, /* CTS Flow Control available */ - 0, /* Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE */ - 0, /* Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT */ - 0, /* RTS Line: 0=not available, 1=available */ - 0, /* CTS Line: 0=not available, 1=available */ - 0, /* DTR Line: 0=not available, 1=available */ - 0, /* DSR Line: 0=not available, 1=available */ - 0, /* DCD Line: 0=not available, 1=available */ - 0, /* RI Line: 0=not available, 1=available */ - 0, /* Signal CTS change event: \ref ARM_USART_EVENT_CTS */ - 0, /* Signal DSR change event: \ref ARM_USART_EVENT_DSR */ - 0, /* Signal DCD change event: \ref ARM_USART_EVENT_DCD */ - 0, /* Signal RI change event: \ref ARM_USART_EVENT_RI */ -}; - -/* - * Common control function used by usart_NonBlockingControl/usart_DmaControl/usart_EdmaControl - */ -static int32_t USART_CommonControl(uint32_t control, - uint32_t arg, - cmsis_usart_resource_t *resource, - uint8_t *isConfigured) -{ - usart_config_t config; - - USART_GetDefaultConfig(&config); - - switch (control & ARM_USART_CONTROL_Msk) - { - case ARM_USART_MODE_ASYNCHRONOUS: - /* USART Baudrate */ - config.baudRate_Bps = arg; - break; - - /* TX/RX IO is controlled in application layer. */ - case ARM_USART_CONTROL_TX: - if (arg) - { - config.enableTx = true; - } - else - { - config.enableTx = false; - } - return ARM_DRIVER_OK; - - case ARM_USART_CONTROL_RX: - if (arg) - { - config.enableRx = true; - } - else - { - config.enableRx = false; - } - - return ARM_DRIVER_OK; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - switch (control & ARM_USART_PARITY_Msk) - { - case ARM_USART_PARITY_NONE: - config.parityMode = kUSART_ParityDisabled; - break; - case ARM_USART_PARITY_EVEN: - config.parityMode = kUSART_ParityEven; - break; - case ARM_USART_PARITY_ODD: - config.parityMode = kUSART_ParityOdd; - break; - default: - return ARM_USART_ERROR_PARITY; - } - - switch (control & ARM_USART_STOP_BITS_Msk) - { - case ARM_USART_STOP_BITS_1: - /* The GetDefaultConfig has already set for this case. */ - break; - case ARM_USART_STOP_BITS_2: - config.stopBitCount = kUSART_TwoStopBit; - break; - default: - return ARM_USART_ERROR_STOP_BITS; - } - - /* If usart is already configured, deinit it first. */ - if ((*isConfigured) & USART_FLAG_CONFIGURED) - { - USART_Deinit(resource->base); - *isConfigured &= ~USART_FLAG_CONFIGURED; - } - - config.enableTx = true; - config.enableRx = true; - - if (kStatus_USART_BaudrateNotSupport == USART_Init(resource->base, &config, resource->GetFreq())) - { - return ARM_USART_ERROR_BAUDRATE; - } - - *isConfigured |= USART_FLAG_CONFIGURED; - - return ARM_DRIVER_OK; -} - -static ARM_DRIVER_VERSION USARTx_GetVersion(void) -{ - return s_usartDriverVersion; -} - -static ARM_USART_CAPABILITIES USARTx_GetCapabilities(void) -{ - return s_usartDriverCapabilities; -} - -static int32_t USARTx_SetModemControl(ARM_USART_MODEM_CONTROL control) -{ - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static ARM_USART_MODEM_STATUS USARTx_GetModemStatus(void) -{ - ARM_USART_MODEM_STATUS modem_status; - - modem_status.cts = 0U; - modem_status.dsr = 0U; - modem_status.ri = 0U; - modem_status.dcd = 0U; - modem_status.reserved = 0U; - - return modem_status; -} - -#endif - -#if (RTE_USART0_DMA_EN || RTE_USART1_DMA_EN || RTE_USART2_DMA_EN || RTE_USART3_DMA_EN || RTE_USART4_DMA_EN || \ - RTE_USART5_DMA_EN || RTE_USART6_DMA_EN || RTE_USART7_DMA_EN || RTE_USART8_DMA_EN || RTE_USART9_DMA_EN) - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) -void KSDK_USART_DmaCallback(USART_Type *base, usart_dma_handle_t *handle, status_t status, void *userData) -{ - uint32_t event = 0U; - - if (kStatus_USART_TxIdle == status) - { - event = ARM_USART_EVENT_SEND_COMPLETE; - } - - if (kStatus_USART_RxIdle == status) - { - event = ARM_USART_EVENT_RECEIVE_COMPLETE; - } - - /* User data is actually CMSIS driver callback. */ - if (userData) - { - ((ARM_USART_SignalEvent_t)userData)(event); - } -} - -static int32_t USART_DmaInitialize(ARM_USART_SignalEvent_t cb_event, cmsis_usart_dma_driver_state_t *usart) -{ - if (!(usart->flags & USART_FLAG_INIT)) - { - usart->cb_event = cb_event; - usart->flags = USART_FLAG_INIT; - } - - return ARM_DRIVER_OK; -} - -static int32_t USART_DmaUninitialize(cmsis_usart_dma_driver_state_t *usart) -{ - usart->flags = USART_FLAG_UNINIT; - return ARM_DRIVER_OK; -} - -static int32_t USART_DmaPowerControl(ARM_POWER_STATE state, cmsis_usart_dma_driver_state_t *usart) -{ - usart_config_t config; - - switch (state) - { - case ARM_POWER_OFF: - if (usart->flags & USART_FLAG_POWER) - { - USART_Deinit(usart->resource->base); - DMA_DisableChannel(usart->dmaResource->rxDmaBase, usart->dmaResource->rxDmaChannel); - DMA_DisableChannel(usart->dmaResource->txDmaBase, usart->dmaResource->txDmaChannel); - usart->flags = USART_FLAG_INIT; - } - break; - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - case ARM_POWER_FULL: - /* Must be initialized first. */ - if (usart->flags == USART_FLAG_UNINIT) - { - return ARM_DRIVER_ERROR; - } - - if (usart->flags & USART_FLAG_POWER) - { - /* Driver already powered */ - break; - } - - USART_GetDefaultConfig(&config); - config.enableTx = true; - config.enableRx = true; - - /* Set up DMA setting. */ - DMA_EnableChannel(usart->dmaResource->txDmaBase, usart->dmaResource->txDmaChannel); - DMA_EnableChannel(usart->dmaResource->rxDmaBase, usart->dmaResource->rxDmaChannel); - - DMA_CreateHandle(usart->rxHandle, usart->dmaResource->rxDmaBase, usart->dmaResource->rxDmaChannel); - DMA_CreateHandle(usart->txHandle, usart->dmaResource->txDmaBase, usart->dmaResource->txDmaChannel); - - /* Setup the usart. */ - USART_Init(usart->resource->base, &config, usart->resource->GetFreq()); - USART_TransferCreateHandleDMA(usart->resource->base, usart->handle, KSDK_USART_DmaCallback, - (void *)usart->cb_event, usart->txHandle, usart->rxHandle); - - usart->flags |= (USART_FLAG_POWER | USART_FLAG_CONFIGURED); - - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - return ARM_DRIVER_OK; -} - -static int32_t USART_DmaSend(const void *data, uint32_t num, cmsis_usart_dma_driver_state_t *usart) -{ - int32_t ret; - status_t status; - usart_transfer_t xfer; - - xfer.data = (uint8_t *)data; - xfer.dataSize = num; - - status = USART_TransferSendDMA(usart->resource->base, usart->handle, &xfer); - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_USART_TxBusy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t USART_DmaReceive(void *data, uint32_t num, cmsis_usart_dma_driver_state_t *usart) -{ - int32_t ret; - status_t status; - usart_transfer_t xfer; - - xfer.data = data; - xfer.dataSize = num; - - status = USART_TransferReceiveDMA(usart->resource->base, usart->handle, &xfer); - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_USART_RxBusy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t USART_DmaTransfer(const void *data_out, - void *data_in, - uint32_t num, - cmsis_usart_dma_driver_state_t *usart) -{ - /* Only in synchronous mode */ - return ARM_DRIVER_ERROR; -} - -static int32_t USART_DmaGetTxCount(cmsis_usart_dma_driver_state_t *usart) -{ - /* Does not support */ - return ARM_DRIVER_ERROR; -} - -static int32_t USART_DmaGetRxCount(cmsis_usart_dma_driver_state_t *usart) -{ - /* Does not support */ - return ARM_DRIVER_ERROR; -} - -static int32_t USART_DmaControl(uint32_t control, uint32_t arg, cmsis_usart_dma_driver_state_t *usart) -{ - /* Must be power on. */ - if (!(usart->flags & USART_FLAG_POWER)) - { - return ARM_DRIVER_ERROR; - } - - /* Does not support these features. */ - if (control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - switch (control & ARM_USART_CONTROL_Msk) - { - /* Abort Send */ - case ARM_USART_ABORT_SEND: - USART_EnableTxDMA(usart->resource->base, false); - DMA_AbortTransfer(usart->handle->txDmaHandle); - usart->handle->txState = kUSART_TxIdle; - return ARM_DRIVER_OK; - - /* Abort receive */ - case ARM_USART_ABORT_RECEIVE: - USART_EnableRxDMA(usart->resource->base, false); - DMA_AbortTransfer(usart->handle->rxDmaHandle); - usart->handle->rxState = kUSART_RxIdle; - return ARM_DRIVER_OK; - - default: - break; - } - - return USART_CommonControl(control, arg, usart->resource, &usart->flags); -} - -static ARM_USART_STATUS USART_DmaGetStatus(cmsis_usart_dma_driver_state_t *usart) -{ - ARM_USART_STATUS stat; - uint32_t ksdk_usart_status = usart->resource->base->STAT; - - stat.tx_busy = ((kUSART_TxBusy == usart->handle->txState) ? (1U) : (0U)); - stat.rx_busy = ((kUSART_RxBusy == usart->handle->rxState) ? (1U) : (0U)); - - stat.tx_underflow = 0U; - stat.rx_overflow = 0U; - - stat.rx_break = (!(!(ksdk_usart_status & USART_STAT_RXBRK_MASK))); - - stat.rx_framing_error = (!(!(ksdk_usart_status & USART_STAT_FRAMERRINT_MASK))); - stat.rx_parity_error = (!(!(ksdk_usart_status & USART_STAT_PARITYERRINT_MASK))); - stat.reserved = 0U; - - return stat; -} -#endif - -#endif - -#if ((RTE_USART0 && !RTE_USART0_DMA_EN) || (RTE_USART1 && !RTE_USART1_DMA_EN) || (RTE_USART2 && !RTE_USART2_DMA_EN) || \ - (RTE_USART3 && !RTE_USART3_DMA_EN) || (RTE_USART4 && !RTE_USART4_DMA_EN) || (RTE_USART5 && !RTE_USART5_DMA_EN) || \ - (RTE_USART6 && !RTE_USART6_DMA_EN) || (RTE_USART7 && !RTE_USART7_DMA_EN) || (RTE_USART8 && !RTE_USART8_DMA_EN) || \ - (RTE_USART9 && !RTE_USART9_DMA_EN)) - -void KSDK_USART_NonBlockingCallback(USART_Type *base, usart_handle_t *handle, status_t status, void *userData) -{ - uint32_t event = 0U; - - if (kStatus_USART_TxIdle == status) - { - event = ARM_USART_EVENT_SEND_COMPLETE; - } - if (kStatus_USART_RxIdle == status) - { - event = ARM_USART_EVENT_RECEIVE_COMPLETE; - } - - /* User data is actually CMSIS driver callback. */ - if (userData) - { - ((ARM_USART_SignalEvent_t)userData)(event); - } -} - -static int32_t USART_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event, - cmsis_usart_non_blocking_driver_state_t *usart) -{ - if (!(usart->flags & USART_FLAG_INIT)) - { - usart->cb_event = cb_event; - usart->flags = USART_FLAG_INIT; - } - - return ARM_DRIVER_OK; -} - -static int32_t USART_NonBlockingUninitialize(cmsis_usart_non_blocking_driver_state_t *usart) -{ - usart->flags = USART_FLAG_UNINIT; - return ARM_DRIVER_OK; -} - -static int32_t USART_NonBlockingPowerControl(ARM_POWER_STATE state, cmsis_usart_non_blocking_driver_state_t *usart) -{ - usart_config_t config; - - switch (state) - { - case ARM_POWER_OFF: - if (usart->flags & USART_FLAG_POWER) - { - USART_Deinit(usart->resource->base); - usart->flags = USART_FLAG_INIT; - } - break; - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - case ARM_POWER_FULL: - /* Must be initialized first. */ - if (usart->flags == USART_FLAG_UNINIT) - { - return ARM_DRIVER_ERROR; - } - - if (usart->flags & USART_FLAG_POWER) - { - /* Driver already powered */ - break; - } - - USART_GetDefaultConfig(&config); - config.enableTx = true; - config.enableRx = true; - - USART_Init(usart->resource->base, &config, usart->resource->GetFreq()); - USART_TransferCreateHandle(usart->resource->base, usart->handle, KSDK_USART_NonBlockingCallback, - (void *)usart->cb_event); - usart->flags |= (USART_FLAG_POWER | USART_FLAG_CONFIGURED); - - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - return ARM_DRIVER_OK; -} - -static int32_t USART_NonBlockingSend(const void *data, uint32_t num, cmsis_usart_non_blocking_driver_state_t *usart) -{ - int32_t ret; - status_t status; - usart_transfer_t xfer; - - xfer.data = (uint8_t *)data; - xfer.dataSize = num; - - status = USART_TransferSendNonBlocking(usart->resource->base, usart->handle, &xfer); - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_USART_TxBusy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t USART_NonBlockingReceive(void *data, uint32_t num, cmsis_usart_non_blocking_driver_state_t *usart) -{ - int32_t ret; - status_t status; - usart_transfer_t xfer; - - xfer.data = data; - xfer.dataSize = num; - - status = USART_TransferReceiveNonBlocking(usart->resource->base, usart->handle, &xfer, NULL); - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_USART_RxBusy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t USART_NonBlockingTransfer(const void *data_out, - void *data_in, - uint32_t num, - cmsis_usart_non_blocking_driver_state_t *usart) -{ - /* Only in synchronous mode */ - return ARM_DRIVER_ERROR; -} - -static uint32_t USART_NonBlockingGetTxCount(cmsis_usart_non_blocking_driver_state_t *usart) -{ - uint32_t cnt; - - /* If TX not in progress, then the TX count is txDataSizeAll saved in handle. */ - if (kUSART_TxIdle == usart->handle->txState) - { - cnt = usart->handle->txDataSizeAll; - } - else - { - cnt = usart->handle->txDataSizeAll - usart->handle->txDataSize; - } - - return cnt; -} - -static uint32_t USART_NonBlockingGetRxCount(cmsis_usart_non_blocking_driver_state_t *usart) -{ - uint32_t cnt; - - if (kUSART_RxIdle == usart->handle->rxState) - { - cnt = usart->handle->rxDataSizeAll; - } - else - { - cnt = usart->handle->rxDataSizeAll - usart->handle->rxDataSize; - } - - return cnt; -} - -static int32_t USART_NonBlockingControl(uint32_t control, uint32_t arg, cmsis_usart_non_blocking_driver_state_t *usart) -{ - /* Must be power on. */ - if (!(usart->flags & USART_FLAG_POWER)) - { - return ARM_DRIVER_ERROR; - } - - /* Does not support these features. */ - if (control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - switch (control & ARM_USART_CONTROL_Msk) - { - /* Abort Send */ - case ARM_USART_ABORT_SEND: - usart->resource->base->FIFOINTENSET &= ~USART_FIFOINTENSET_TXLVL_MASK; - usart->handle->txDataSize = 0; - usart->handle->txState = kUSART_TxIdle; - return ARM_DRIVER_OK; - - /* Abort receive */ - case ARM_USART_ABORT_RECEIVE: - usart->resource->base->FIFOINTENSET &= ~USART_FIFOINTENSET_RXLVL_MASK; - usart->handle->rxDataSize = 0U; - usart->handle->rxState = kUSART_RxIdle; - return ARM_DRIVER_OK; - - default: - break; - } - - return USART_CommonControl(control, arg, usart->resource, &usart->flags); -} - -static ARM_USART_STATUS USART_NonBlockingGetStatus(cmsis_usart_non_blocking_driver_state_t *usart) -{ - ARM_USART_STATUS stat; - uint32_t ksdk_usart_status = usart->resource->base->STAT; - - stat.tx_busy = ((kUSART_TxBusy == usart->handle->txState) ? (1U) : (0U)); - stat.rx_busy = ((kUSART_RxBusy == usart->handle->rxState) ? (1U) : (0U)); - - stat.tx_underflow = 0U; - stat.rx_overflow = 0U; - - stat.rx_break = (!(!(ksdk_usart_status & USART_STAT_RXBRK_MASK))); - - stat.rx_framing_error = (!(!(ksdk_usart_status & USART_STAT_FRAMERRINT_MASK))); - stat.rx_parity_error = (!(!(ksdk_usart_status & USART_STAT_PARITYERRINT_MASK))); - stat.reserved = 0U; - - return stat; -} - -#endif - -#if defined(USART0) && RTE_USART0 - -/* User needs to provide the implementation for USART0_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t USART0_GetFreq(void); -extern void USART0_InitPins(void); -extern void USART0_DeinitPins(void); - -cmsis_usart_resource_t usart0_Resource = {USART0, USART0_GetFreq}; - -/* usart0 Driver Control Block */ - -#if RTE_USART0_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_usart_dma_resource_t usart0_DmaResource = { - RTE_USART0_DMA_TX_DMA_BASE, RTE_USART0_DMA_TX_CH, RTE_USART0_DMA_RX_DMA_BASE, RTE_USART0_DMA_RX_CH, -}; - -usart_dma_handle_t USART0_DmaHandle; -dma_handle_t USART0_DmaRxHandle; -dma_handle_t USART0_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("usart0_dma_driver_state") -cmsis_usart_dma_driver_state_t usart0_DmaDriverState = { -#else -cmsis_usart_dma_driver_state_t usart0_DmaDriverState = { -#endif - &usart0_Resource, &usart0_DmaResource, &USART0_DmaHandle, &USART0_DmaRxHandle, &USART0_DmaTxHandle, -}; - -static int32_t USART0_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART0_InitPins(); - return USART_DmaInitialize(cb_event, &usart0_DmaDriverState); -} - -static int32_t USART0_DmaUninitialize(void) -{ - USART0_DeinitPins(); - return USART_DmaUninitialize(&usart0_DmaDriverState); -} - -static int32_t USART0_DmaPowerControl(ARM_POWER_STATE state) -{ - return USART_DmaPowerControl(state, &usart0_DmaDriverState); -} - -static int32_t USART0_DmaSend(const void *data, uint32_t num) -{ - return USART_DmaSend(data, num, &usart0_DmaDriverState); -} - -static int32_t USART0_DmaReceive(void *data, uint32_t num) -{ - return USART_DmaReceive(data, num, &usart0_DmaDriverState); -} - -static int32_t USART0_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_DmaTransfer(data_out, data_in, num, &usart0_DmaDriverState); -} - -static uint32_t USART0_DmaGetTxCount(void) -{ - return USART_DmaGetTxCount(&usart0_DmaDriverState); -} - -static uint32_t USART0_DmaGetRxCount(void) -{ - return USART_DmaGetRxCount(&usart0_DmaDriverState); -} - -static int32_t USART0_DmaControl(uint32_t control, uint32_t arg) -{ - return USART_DmaControl(control, arg, &usart0_DmaDriverState); -} - -static ARM_USART_STATUS USART0_DmaGetStatus(void) -{ - return USART_DmaGetStatus(&usart0_DmaDriverState); -} - -#endif - -#else - -usart_handle_t USART0_Handle; -#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1) -static uint8_t usart0_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("usart0_non_blocking_driver_state") -cmsis_usart_non_blocking_driver_state_t usart0_NonBlockingDriverState = { -#else -cmsis_usart_non_blocking_driver_state_t usart0_NonBlockingDriverState = { -#endif - &usart0_Resource, &USART0_Handle, -}; - -static int32_t USART0_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART0_InitPins(); - return USART_NonBlockingInitialize(cb_event, &usart0_NonBlockingDriverState); -} - -static int32_t USART0_NonBlockingUninitialize(void) -{ - USART0_DeinitPins(); - return USART_NonBlockingUninitialize(&usart0_NonBlockingDriverState); -} - -static int32_t USART0_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = USART_NonBlockingPowerControl(state, &usart0_NonBlockingDriverState); -#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (usart0_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - USART_TransferStartRingBuffer(usart0_NonBlockingDriverState.resource->base, - usart0_NonBlockingDriverState.handle, usart0_rxRingBuffer, USART_RX_BUFFER_LEN); - } -#endif - return result; -} - -static int32_t USART0_NonBlockingSend(const void *data, uint32_t num) -{ - return USART_NonBlockingSend(data, num, &usart0_NonBlockingDriverState); -} - -static int32_t USART0_NonBlockingReceive(void *data, uint32_t num) -{ - return USART_NonBlockingReceive(data, num, &usart0_NonBlockingDriverState); -} - -static int32_t USART0_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_NonBlockingTransfer(data_out, data_in, num, &usart0_NonBlockingDriverState); -} - -static uint32_t USART0_NonBlockingGetTxCount(void) -{ - return USART_NonBlockingGetTxCount(&usart0_NonBlockingDriverState); -} - -static uint32_t USART0_NonBlockingGetRxCount(void) -{ - return USART_NonBlockingGetRxCount(&usart0_NonBlockingDriverState); -} - -static int32_t USART0_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = USART_NonBlockingControl(control, arg, &usart0_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } -#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1) - /* Start receiving interrupts */ - usart0_NonBlockingDriverState.resource->base->FIFOINTENSET |= - USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -#endif - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS USART0_NonBlockingGetStatus(void) -{ - return USART_NonBlockingGetStatus(&usart0_NonBlockingDriverState); -} - -#endif - -ARM_DRIVER_USART Driver_USART0 = { - USARTx_GetVersion, USARTx_GetCapabilities, -#if RTE_USART0_DMA_EN - USART0_DmaInitialize, USART0_DmaUninitialize, USART0_DmaPowerControl, USART0_DmaSend, USART0_DmaReceive, - USART0_DmaTransfer, USART0_DmaGetTxCount, USART0_DmaGetRxCount, USART0_DmaControl, USART0_DmaGetStatus, -#else - USART0_NonBlockingInitialize, - USART0_NonBlockingUninitialize, - USART0_NonBlockingPowerControl, - USART0_NonBlockingSend, - USART0_NonBlockingReceive, - USART0_NonBlockingTransfer, - USART0_NonBlockingGetTxCount, - USART0_NonBlockingGetRxCount, - USART0_NonBlockingControl, - USART0_NonBlockingGetStatus, -#endif - USARTx_SetModemControl, USARTx_GetModemStatus}; - -#endif /* usart0 */ - -#if defined(USART1) && RTE_USART1 - -/* User needs to provide the implementation for USART1_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t USART1_GetFreq(void); -extern void USART1_InitPins(void); -extern void USART1_DeinitPins(void); - -cmsis_usart_resource_t usart1_Resource = {USART1, USART1_GetFreq}; - -#if RTE_USART1_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_usart_dma_resource_t usart1_DmaResource = { - RTE_USART1_DMA_TX_DMA_BASE, RTE_USART1_DMA_TX_CH, RTE_USART1_DMA_RX_DMA_BASE, RTE_USART1_DMA_RX_CH, -}; - -usart_dma_handle_t USART1_DmaHandle; -dma_handle_t USART1_DmaRxHandle; -dma_handle_t USART1_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("usart1_dma_driver_state") -cmsis_usart_dma_driver_state_t usart1_DmaDriverState = { -#else -cmsis_usart_dma_driver_state_t usart1_DmaDriverState = { -#endif - &usart1_Resource, &usart1_DmaResource, &USART1_DmaHandle, &USART1_DmaRxHandle, &USART1_DmaTxHandle, -}; - -static int32_t USART1_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART1_InitPins(); - return USART_DmaInitialize(cb_event, &usart1_DmaDriverState); -} - -static int32_t USART1_DmaUninitialize(void) -{ - USART1_DeinitPins(); - return USART_DmaUninitialize(&usart1_DmaDriverState); -} - -static int32_t USART1_DmaPowerControl(ARM_POWER_STATE state) -{ - return USART_DmaPowerControl(state, &usart1_DmaDriverState); -} - -static int32_t USART1_DmaSend(const void *data, uint32_t num) -{ - return USART_DmaSend(data, num, &usart1_DmaDriverState); -} - -static int32_t USART1_DmaReceive(void *data, uint32_t num) -{ - return USART_DmaReceive(data, num, &usart1_DmaDriverState); -} - -static int32_t USART1_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_DmaTransfer(data_out, data_in, num, &usart1_DmaDriverState); -} - -static uint32_t USART1_DmaGetTxCount(void) -{ - return USART_DmaGetTxCount(&usart1_DmaDriverState); -} - -static uint32_t USART1_DmaGetRxCount(void) -{ - return USART_DmaGetRxCount(&usart1_DmaDriverState); -} - -static int32_t USART1_DmaControl(uint32_t control, uint32_t arg) -{ - return USART_DmaControl(control, arg, &usart1_DmaDriverState); -} - -static ARM_USART_STATUS USART1_DmaGetStatus(void) -{ - return USART_DmaGetStatus(&usart1_DmaDriverState); -} - -#endif - -#else - -usart_handle_t USART1_Handle; -#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) -static uint8_t usart1_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("usart1_non_blocking_driver_state") -cmsis_usart_non_blocking_driver_state_t usart1_NonBlockingDriverState = { -#else -cmsis_usart_non_blocking_driver_state_t usart1_NonBlockingDriverState = { -#endif - &usart1_Resource, &USART1_Handle, -}; - -static int32_t USART1_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART1_InitPins(); - return USART_NonBlockingInitialize(cb_event, &usart1_NonBlockingDriverState); -} - -static int32_t USART1_NonBlockingUninitialize(void) -{ - USART1_DeinitPins(); - return USART_NonBlockingUninitialize(&usart1_NonBlockingDriverState); -} - -static int32_t USART1_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = USART_NonBlockingPowerControl(state, &usart1_NonBlockingDriverState); -#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (usart1_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - USART_TransferStartRingBuffer(usart1_NonBlockingDriverState.resource->base, - usart1_NonBlockingDriverState.handle, usart1_rxRingBuffer, USART_RX_BUFFER_LEN); - } -#endif - return result; -} - -static int32_t USART1_NonBlockingSend(const void *data, uint32_t num) -{ - return USART_NonBlockingSend(data, num, &usart1_NonBlockingDriverState); -} - -static int32_t USART1_NonBlockingReceive(void *data, uint32_t num) -{ - return USART_NonBlockingReceive(data, num, &usart1_NonBlockingDriverState); -} - -static int32_t USART1_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_NonBlockingTransfer(data_out, data_in, num, &usart1_NonBlockingDriverState); -} - -static uint32_t USART1_NonBlockingGetTxCount(void) -{ - return USART_NonBlockingGetTxCount(&usart1_NonBlockingDriverState); -} - -static uint32_t USART1_NonBlockingGetRxCount(void) -{ - return USART_NonBlockingGetRxCount(&usart1_NonBlockingDriverState); -} - -static int32_t USART1_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = USART_NonBlockingControl(control, arg, &usart1_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } -#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) - /* Start receiving interrupts */ - usart1_NonBlockingDriverState.resource->base->FIFOINTENSET |= - USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -#endif - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS USART1_NonBlockingGetStatus(void) -{ - return USART_NonBlockingGetStatus(&usart1_NonBlockingDriverState); -} - -#endif - -ARM_DRIVER_USART Driver_USART1 = { - USARTx_GetVersion, USARTx_GetCapabilities, -#if RTE_USART1_DMA_EN - USART1_DmaInitialize, USART1_DmaUninitialize, USART1_DmaPowerControl, USART1_DmaSend, USART1_DmaReceive, - USART1_DmaTransfer, USART1_DmaGetTxCount, USART1_DmaGetRxCount, USART1_DmaControl, USART1_DmaGetStatus, -#else - USART1_NonBlockingInitialize, - USART1_NonBlockingUninitialize, - USART1_NonBlockingPowerControl, - USART1_NonBlockingSend, - USART1_NonBlockingReceive, - USART1_NonBlockingTransfer, - USART1_NonBlockingGetTxCount, - USART1_NonBlockingGetRxCount, - USART1_NonBlockingControl, - USART1_NonBlockingGetStatus, -#endif - USARTx_SetModemControl, USARTx_GetModemStatus}; - -#endif /* usart1 */ - -#if defined(USART2) && RTE_USART2 - -/* User needs to provide the implementation for USART2_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t USART2_GetFreq(void); -extern void USART2_InitPins(void); -extern void USART2_DeinitPins(void); - -cmsis_usart_resource_t usart2_Resource = {USART2, USART2_GetFreq}; - -/* usart2 Driver Control Block */ - -#if RTE_USART2_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_usart_dma_resource_t usart2_DmaResource = { - RTE_USART2_DMA_TX_DMA_BASE, RTE_USART2_DMA_TX_CH, RTE_USART2_DMA_RX_DMA_BASE, RTE_USART2_DMA_RX_CH, -}; - -usart_dma_handle_t USART2_DmaHandle; -dma_handle_t USART2_DmaRxHandle; -dma_handle_t USART2_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("usart2_dma_driver_state") -cmsis_usart_dma_driver_state_t usart2_DmaDriverState = { -#else -cmsis_usart_dma_driver_state_t usart2_DmaDriverState = { -#endif - &usart2_Resource, &usart2_DmaResource, &USART2_DmaHandle, &USART2_DmaRxHandle, &USART2_DmaTxHandle, -}; - -static int32_t USART2_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART2_InitPins(); - return USART_DmaInitialize(cb_event, &usart2_DmaDriverState); -} - -static int32_t USART2_DmaUninitialize(void) -{ - USART2_DeinitPins(); - return USART_DmaUninitialize(&usart2_DmaDriverState); -} - -static int32_t USART2_DmaPowerControl(ARM_POWER_STATE state) -{ - return USART_DmaPowerControl(state, &usart2_DmaDriverState); -} - -static int32_t USART2_DmaSend(const void *data, uint32_t num) -{ - return USART_DmaSend(data, num, &usart2_DmaDriverState); -} - -static int32_t USART2_DmaReceive(void *data, uint32_t num) -{ - return USART_DmaReceive(data, num, &usart2_DmaDriverState); -} - -static int32_t USART2_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_DmaTransfer(data_out, data_in, num, &usart2_DmaDriverState); -} - -static uint32_t USART2_DmaGetTxCount(void) -{ - return USART_DmaGetTxCount(&usart2_DmaDriverState); -} - -static uint32_t USART2_DmaGetRxCount(void) -{ - return USART_DmaGetRxCount(&usart2_DmaDriverState); -} - -static int32_t USART2_DmaControl(uint32_t control, uint32_t arg) -{ - return USART_DmaControl(control, arg, &usart2_DmaDriverState); -} - -static ARM_USART_STATUS USART2_DmaGetStatus(void) -{ - return USART_DmaGetStatus(&usart2_DmaDriverState); -} - -#endif - -#else - -usart_handle_t USART2_Handle; -#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) -static uint8_t usart2_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("usart2_non_blocking_driver_state") -cmsis_usart_non_blocking_driver_state_t usart2_NonBlockingDriverState = { -#else -cmsis_usart_non_blocking_driver_state_t usart2_NonBlockingDriverState = { -#endif - &usart2_Resource, &USART2_Handle, -}; - -static int32_t USART2_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART2_InitPins(); - return USART_NonBlockingInitialize(cb_event, &usart2_NonBlockingDriverState); -} - -static int32_t USART2_NonBlockingUninitialize(void) -{ - USART2_DeinitPins(); - return USART_NonBlockingUninitialize(&usart2_NonBlockingDriverState); -} - -static int32_t USART2_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = USART_NonBlockingPowerControl(state, &usart2_NonBlockingDriverState); -#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (usart2_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - USART_TransferStartRingBuffer(usart2_NonBlockingDriverState.resource->base, - usart2_NonBlockingDriverState.handle, usart2_rxRingBuffer, USART_RX_BUFFER_LEN); - } -#endif - return result; -} - -static int32_t USART2_NonBlockingSend(const void *data, uint32_t num) -{ - return USART_NonBlockingSend(data, num, &usart2_NonBlockingDriverState); -} - -static int32_t USART2_NonBlockingReceive(void *data, uint32_t num) -{ - return USART_NonBlockingReceive(data, num, &usart2_NonBlockingDriverState); -} - -static int32_t USART2_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_NonBlockingTransfer(data_out, data_in, num, &usart2_NonBlockingDriverState); -} - -static uint32_t USART2_NonBlockingGetTxCount(void) -{ - return USART_NonBlockingGetTxCount(&usart2_NonBlockingDriverState); -} - -static uint32_t USART2_NonBlockingGetRxCount(void) -{ - return USART_NonBlockingGetRxCount(&usart2_NonBlockingDriverState); -} - -static int32_t USART2_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = USART_NonBlockingControl(control, arg, &usart2_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } -#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) - /* Start receiving interrupts */ - usart2_NonBlockingDriverState.resource->base->FIFOINTENSET |= - USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -#endif - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS USART2_NonBlockingGetStatus(void) -{ - return USART_NonBlockingGetStatus(&usart2_NonBlockingDriverState); -} - -#endif - -ARM_DRIVER_USART Driver_USART2 = { - USARTx_GetVersion, USARTx_GetCapabilities, -#if RTE_USART2_DMA_EN - USART2_DmaInitialize, USART2_DmaUninitialize, USART2_DmaPowerControl, USART2_DmaSend, USART2_DmaReceive, - USART2_DmaTransfer, USART2_DmaGetTxCount, USART2_DmaGetRxCount, USART2_DmaControl, USART2_DmaGetStatus, -#else - USART2_NonBlockingInitialize, - USART2_NonBlockingUninitialize, - USART2_NonBlockingPowerControl, - USART2_NonBlockingSend, - USART2_NonBlockingReceive, - USART2_NonBlockingTransfer, - USART2_NonBlockingGetTxCount, - USART2_NonBlockingGetRxCount, - USART2_NonBlockingControl, - USART2_NonBlockingGetStatus, -#endif - USARTx_SetModemControl, USARTx_GetModemStatus}; - -#endif /* usart2 */ - -#if defined(USART3) && RTE_USART3 - -/* User needs to provide the implementation for USART3_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t USART3_GetFreq(void); -extern void USART3_InitPins(void); -extern void USART3_DeinitPins(void); - -cmsis_usart_resource_t usart3_Resource = {USART3, USART3_GetFreq}; - -/* usart3 Driver Control Block */ -#if RTE_USART3_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_usart_dma_resource_t usart3_DmaResource = { - RTE_USART3_DMA_TX_DMA_BASE, RTE_USART3_DMA_TX_CH, RTE_USART3_DMA_RX_DMA_BASE, RTE_USART3_DMA_RX_CH, -}; - -usart_dma_handle_t USART3_DmaHandle; -dma_handle_t USART3_DmaRxHandle; -dma_handle_t USART3_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("usart3_dma_driver_state") -cmsis_usart_dma_driver_state_t usart3_DmaDriverState = { -#else -cmsis_usart_dma_driver_state_t usart3_DmaDriverState = { -#endif - &usart3_Resource, &usart3_DmaResource, &USART3_DmaHandle, &USART3_DmaRxHandle, &USART3_DmaTxHandle, -}; - -static int32_t USART3_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART3_InitPins(); - return USART_DmaInitialize(cb_event, &usart3_DmaDriverState); -} - -static int32_t USART3_DmaUninitialize(void) -{ - USART3_DeinitPins(); - return USART_DmaUninitialize(&usart3_DmaDriverState); -} - -static int32_t USART3_DmaPowerControl(ARM_POWER_STATE state) -{ - return USART_DmaPowerControl(state, &usart3_DmaDriverState); -} - -static int32_t USART3_DmaSend(const void *data, uint32_t num) -{ - return USART_DmaSend(data, num, &usart3_DmaDriverState); -} - -static int32_t USART3_DmaReceive(void *data, uint32_t num) -{ - return USART_DmaReceive(data, num, &usart3_DmaDriverState); -} - -static int32_t USART3_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_DmaTransfer(data_out, data_in, num, &usart3_DmaDriverState); -} - -static uint32_t USART3_DmaGetTxCount(void) -{ - return USART_DmaGetTxCount(&usart3_DmaDriverState); -} - -static uint32_t USART3_DmaGetRxCount(void) -{ - return USART_DmaGetRxCount(&usart3_DmaDriverState); -} - -static int32_t USART3_DmaControl(uint32_t control, uint32_t arg) -{ - return USART_DmaControl(control, arg, &usart3_DmaDriverState); -} - -static ARM_USART_STATUS USART3_DmaGetStatus(void) -{ - return USART_DmaGetStatus(&usart3_DmaDriverState); -} - -#endif - -#else - -usart_handle_t USART3_Handle; -#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) -static uint8_t usart3_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("usart3_non_blocking_driver_state") -cmsis_usart_non_blocking_driver_state_t usart3_NonBlockingDriverState = { -#else -cmsis_usart_non_blocking_driver_state_t usart3_NonBlockingDriverState = { -#endif - &usart3_Resource, &USART3_Handle, -}; - -static int32_t USART3_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART3_InitPins(); - return USART_NonBlockingInitialize(cb_event, &usart3_NonBlockingDriverState); -} - -static int32_t USART3_NonBlockingUninitialize(void) -{ - USART3_DeinitPins(); - return USART_NonBlockingUninitialize(&usart3_NonBlockingDriverState); -} - -static int32_t USART3_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = USART_NonBlockingPowerControl(state, &usart3_NonBlockingDriverState); -#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (usart3_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - USART_TransferStartRingBuffer(usart3_NonBlockingDriverState.resource->base, - usart3_NonBlockingDriverState.handle, usart3_rxRingBuffer, USART_RX_BUFFER_LEN); - } -#endif - return result; -} - -static int32_t USART3_NonBlockingSend(const void *data, uint32_t num) -{ - return USART_NonBlockingSend(data, num, &usart3_NonBlockingDriverState); -} - -static int32_t USART3_NonBlockingReceive(void *data, uint32_t num) -{ - return USART_NonBlockingReceive(data, num, &usart3_NonBlockingDriverState); -} - -static int32_t USART3_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_NonBlockingTransfer(data_out, data_in, num, &usart3_NonBlockingDriverState); -} - -static uint32_t USART3_NonBlockingGetTxCount(void) -{ - return USART_NonBlockingGetTxCount(&usart3_NonBlockingDriverState); -} - -static uint32_t USART3_NonBlockingGetRxCount(void) -{ - return USART_NonBlockingGetRxCount(&usart3_NonBlockingDriverState); -} - -static int32_t USART3_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = USART_NonBlockingControl(control, arg, &usart3_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } -#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) - /* Start receiving interrupts */ - usart3_NonBlockingDriverState.resource->base->FIFOINTENSET |= - USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -#endif - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS USART3_NonBlockingGetStatus(void) -{ - return USART_NonBlockingGetStatus(&usart3_NonBlockingDriverState); -} - -#endif - -ARM_DRIVER_USART Driver_USART3 = { - USARTx_GetVersion, USARTx_GetCapabilities, -#if RTE_USART3_DMA_EN - USART3_DmaInitialize, USART3_DmaUninitialize, USART3_DmaPowerControl, USART3_DmaSend, USART3_DmaReceive, - USART3_DmaTransfer, USART3_DmaGetTxCount, USART3_DmaGetRxCount, USART3_DmaControl, USART3_DmaGetStatus, -#else - USART3_NonBlockingInitialize, - USART3_NonBlockingUninitialize, - USART3_NonBlockingPowerControl, - USART3_NonBlockingSend, - USART3_NonBlockingReceive, - USART3_NonBlockingTransfer, - USART3_NonBlockingGetTxCount, - USART3_NonBlockingGetRxCount, - USART3_NonBlockingControl, - USART3_NonBlockingGetStatus, -#endif - USARTx_SetModemControl, USARTx_GetModemStatus}; - -#endif /* usart3 */ - -#if defined(USART4) && RTE_USART4 - -/* User needs to provide the implementation for USART4_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t USART4_GetFreq(void); -extern void USART4_InitPins(void); -extern void USART4_DeinitPins(void); - -cmsis_usart_resource_t usart4_Resource = {USART4, USART4_GetFreq}; - -#if RTE_USART4_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_usart_dma_resource_t usart4_DmaResource = { - RTE_USART4_DMA_TX_DMA_BASE, RTE_USART4_DMA_TX_CH, RTE_USART4_DMA_RX_DMA_BASE, RTE_USART4_DMA_RX_CH, -}; - -usart_dma_handle_t USART4_DmaHandle; -dma_handle_t USART4_DmaRxHandle; -dma_handle_t USART4_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("usart4_dma_driver_state") -cmsis_usart_dma_driver_state_t usart4_DmaDriverState = { -#else -cmsis_usart_dma_driver_state_t usart4_DmaDriverState = { -#endif - &usart4_Resource, &usart4_DmaResource, &USART4_DmaHandle, &USART4_DmaRxHandle, &USART4_DmaTxHandle, -}; - -static int32_t USART4_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART4_InitPins(); - return USART_DmaInitialize(cb_event, &usart4_DmaDriverState); -} - -static int32_t USART4_DmaUninitialize(void) -{ - USART4_DeinitPins(); - return USART_DmaUninitialize(&usart4_DmaDriverState); -} - -static int32_t USART4_DmaPowerControl(ARM_POWER_STATE state) -{ - return USART_DmaPowerControl(state, &usart4_DmaDriverState); -} - -static int32_t USART4_DmaSend(const void *data, uint32_t num) -{ - return USART_DmaSend(data, num, &usart4_DmaDriverState); -} - -static int32_t USART4_DmaReceive(void *data, uint32_t num) -{ - return USART_DmaReceive(data, num, &usart4_DmaDriverState); -} - -static int32_t USART4_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_DmaTransfer(data_out, data_in, num, &usart4_DmaDriverState); -} - -static uint32_t USART4_DmaGetTxCount(void) -{ - return USART_DmaGetTxCount(&usart4_DmaDriverState); -} - -static uint32_t USART4_DmaGetRxCount(void) -{ - return USART_DmaGetRxCount(&usart4_DmaDriverState); -} - -static int32_t USART4_DmaControl(uint32_t control, uint32_t arg) -{ - return USART_DmaControl(control, arg, &usart4_DmaDriverState); -} - -static ARM_USART_STATUS USART4_DmaGetStatus(void) -{ - return USART_DmaGetStatus(&usart4_DmaDriverState); -} - -#endif - -#else - -usart_handle_t USART4_Handle; -#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) -static uint8_t usart4_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("usart4_non_blocking_driver_state") -cmsis_usart_non_blocking_driver_state_t usart4_NonBlockingDriverState = { -#else -cmsis_usart_non_blocking_driver_state_t usart4_NonBlockingDriverState = { -#endif - &usart4_Resource, &USART4_Handle, -}; - -static int32_t USART4_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART4_InitPins(); - return USART_NonBlockingInitialize(cb_event, &usart4_NonBlockingDriverState); -} - -static int32_t USART4_NonBlockingUninitialize(void) -{ - USART4_DeinitPins(); - return USART_NonBlockingUninitialize(&usart4_NonBlockingDriverState); -} - -static int32_t USART4_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = USART_NonBlockingPowerControl(state, &usart4_NonBlockingDriverState); -#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (usart4_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - USART_TransferStartRingBuffer(usart4_NonBlockingDriverState.resource->base, - usart4_NonBlockingDriverState.handle, usart4_rxRingBuffer, USART_RX_BUFFER_LEN); - } -#endif - return result; -} - -static int32_t USART4_NonBlockingSend(const void *data, uint32_t num) -{ - return USART_NonBlockingSend(data, num, &usart4_NonBlockingDriverState); -} - -static int32_t USART4_NonBlockingReceive(void *data, uint32_t num) -{ - return USART_NonBlockingReceive(data, num, &usart4_NonBlockingDriverState); -} - -static int32_t USART4_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_NonBlockingTransfer(data_out, data_in, num, &usart4_NonBlockingDriverState); -} - -static uint32_t USART4_NonBlockingGetTxCount(void) -{ - return USART_NonBlockingGetTxCount(&usart4_NonBlockingDriverState); -} - -static uint32_t USART4_NonBlockingGetRxCount(void) -{ - return USART_NonBlockingGetRxCount(&usart4_NonBlockingDriverState); -} - -static int32_t USART4_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = USART_NonBlockingControl(control, arg, &usart4_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } -#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) - /* Start receiving interrupts */ - usart4_NonBlockingDriverState.resource->base->FIFOINTENSET |= - USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -#endif - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS USART4_NonBlockingGetStatus(void) -{ - return USART_NonBlockingGetStatus(&usart4_NonBlockingDriverState); -} - -#endif - -ARM_DRIVER_USART Driver_USART4 = { - USARTx_GetVersion, USARTx_GetCapabilities, -#if RTE_USART4_DMA_EN - USART4_DmaInitialize, USART4_DmaUninitialize, USART4_DmaPowerControl, USART4_DmaSend, USART4_DmaReceive, - USART4_DmaTransfer, USART4_DmaGetTxCount, USART4_DmaGetRxCount, USART4_DmaControl, USART4_DmaGetStatus, -#else - USART4_NonBlockingInitialize, - USART4_NonBlockingUninitialize, - USART4_NonBlockingPowerControl, - USART4_NonBlockingSend, - USART4_NonBlockingReceive, - USART4_NonBlockingTransfer, - USART4_NonBlockingGetTxCount, - USART4_NonBlockingGetRxCount, - USART4_NonBlockingControl, - USART4_NonBlockingGetStatus, -#endif - USARTx_SetModemControl, USARTx_GetModemStatus}; - -#endif /* usart4 */ - -#if defined(USART5) && RTE_USART5 - -/* User needs to provide the implementation for USART5_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t USART5_GetFreq(void); -extern void USART5_InitPins(void); -extern void USART5_DeinitPins(void); - -cmsis_usart_resource_t usart5_Resource = {USART5, USART5_GetFreq}; - -#if RTE_USART5_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_usart_dma_resource_t usart5_DmaResource = { - RTE_USART5_DMA_TX_DMA_BASE, RTE_USART5_DMA_TX_CH, RTE_USART5_DMA_RX_DMA_BASE, RTE_USART5_DMA_RX_CH, -}; - -usart_dma_handle_t USART5_DmaHandle; -dma_handle_t USART5_DmaRxHandle; -dma_handle_t USART5_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("usart5_dma_driver_state") -cmsis_usart_dma_driver_state_t usart5_DmaDriverState = { -#else -cmsis_usart_dma_driver_state_t usart5_DmaDriverState = { -#endif - &usart5_Resource, &usart5_DmaResource, &USART5_DmaHandle, &USART5_DmaRxHandle, &USART5_DmaTxHandle, -}; - -static int32_t USART5_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART5_InitPins(); - return USART_DmaInitialize(cb_event, &usart5_DmaDriverState); -} - -static int32_t USART5_DmaUninitialize(void) -{ - USART5_DeinitPins(); - return USART_DmaUninitialize(&usart5_DmaDriverState); -} - -static int32_t USART5_DmaPowerControl(ARM_POWER_STATE state) -{ - return USART_DmaPowerControl(state, &usart5_DmaDriverState); -} - -static int32_t USART5_DmaSend(const void *data, uint32_t num) -{ - return USART_DmaSend(data, num, &usart5_DmaDriverState); -} - -static int32_t USART5_DmaReceive(void *data, uint32_t num) -{ - return USART_DmaReceive(data, num, &usart5_DmaDriverState); -} - -static int32_t USART5_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_DmaTransfer(data_out, data_in, num, &usart5_DmaDriverState); -} - -static uint32_t USART5_DmaGetTxCount(void) -{ - return USART_DmaGetTxCount(&usart5_DmaDriverState); -} - -static uint32_t USART5_DmaGetRxCount(void) -{ - return USART_DmaGetRxCount(&usart5_DmaDriverState); -} - -static int32_t USART5_DmaControl(uint32_t control, uint32_t arg) -{ - return USART_DmaControl(control, arg, &usart5_DmaDriverState); -} - -static ARM_USART_STATUS USART5_DmaGetStatus(void) -{ - return USART_DmaGetStatus(&usart5_DmaDriverState); -} - -#endif - -#else - -usart_handle_t USART5_Handle; -#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1) -static uint8_t usart5_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("usart5_non_blocking_driver_state") -cmsis_usart_non_blocking_driver_state_t usart5_NonBlockingDriverState = { -#else -cmsis_usart_non_blocking_driver_state_t usart5_NonBlockingDriverState = { -#endif - &usart5_Resource, &USART5_Handle, -}; - -static int32_t USART5_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART5_InitPins(); - return USART_NonBlockingInitialize(cb_event, &usart5_NonBlockingDriverState); -} - -static int32_t USART5_NonBlockingUninitialize(void) -{ - USART5_DeinitPins(); - return USART_NonBlockingUninitialize(&usart5_NonBlockingDriverState); -} - -static int32_t USART5_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = USART_NonBlockingPowerControl(state, &usart5_NonBlockingDriverState); -#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (usart5_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - USART_TransferStartRingBuffer(usart5_NonBlockingDriverState.resource->base, - usart5_NonBlockingDriverState.handle, usart5_rxRingBuffer, USART_RX_BUFFER_LEN); - } -#endif - return result; -} - -static int32_t USART5_NonBlockingSend(const void *data, uint32_t num) -{ - return USART_NonBlockingSend(data, num, &usart5_NonBlockingDriverState); -} - -static int32_t USART5_NonBlockingReceive(void *data, uint32_t num) -{ - return USART_NonBlockingReceive(data, num, &usart5_NonBlockingDriverState); -} - -static int32_t USART5_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_NonBlockingTransfer(data_out, data_in, num, &usart5_NonBlockingDriverState); -} - -static uint32_t USART5_NonBlockingGetTxCount(void) -{ - return USART_NonBlockingGetTxCount(&usart5_NonBlockingDriverState); -} - -static uint32_t USART5_NonBlockingGetRxCount(void) -{ - return USART_NonBlockingGetRxCount(&usart5_NonBlockingDriverState); -} - -static int32_t USART5_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = USART_NonBlockingControl(control, arg, &usart5_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } -#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1) - /* Start receiving interrupts */ - usart5_NonBlockingDriverState.resource->base->FIFOINTENSET |= - USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -#endif - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS USART5_NonBlockingGetStatus(void) -{ - return USART_NonBlockingGetStatus(&usart5_NonBlockingDriverState); -} - -#endif - -ARM_DRIVER_USART Driver_USART5 = { - USARTx_GetVersion, USARTx_GetCapabilities, -#if RTE_USART5_DMA_EN - USART5_DmaInitialize, USART5_DmaUninitialize, USART5_DmaPowerControl, USART5_DmaSend, USART5_DmaReceive, - USART5_DmaTransfer, USART5_DmaGetTxCount, USART5_DmaGetRxCount, USART5_DmaControl, USART5_DmaGetStatus, -#else - USART5_NonBlockingInitialize, - USART5_NonBlockingUninitialize, - USART5_NonBlockingPowerControl, - USART5_NonBlockingSend, - USART5_NonBlockingReceive, - USART5_NonBlockingTransfer, - USART5_NonBlockingGetTxCount, - USART5_NonBlockingGetRxCount, - USART5_NonBlockingControl, - USART5_NonBlockingGetStatus, -#endif - USARTx_SetModemControl, USARTx_GetModemStatus}; - -#endif /* usart5 */ - -#if defined(USART6) && RTE_USART6 - -/* User needs to provide the implementation for USART6_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t USART6_GetFreq(void); -extern void USART6_InitPins(void); -extern void USART6_DeinitPins(void); - -cmsis_usart_resource_t usart6_Resource = {USART6, USART6_GetFreq}; - -#if RTE_USART6_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_usart_dma_resource_t usart6_DmaResource = { - RTE_USART6_DMA_TX_DMA_BASE, RTE_USART6_DMA_TX_CH, RTE_USART6_DMA_RX_DMA_BASE, RTE_USART6_DMA_RX_CH, -}; - -usart_dma_handle_t USART6_DmaHandle; -dma_handle_t USART6_DmaRxHandle; -dma_handle_t USART6_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("usart6_dma_driver_state") -cmsis_usart_dma_driver_state_t usart6_DmaDriverState = { -#else -cmsis_usart_dma_driver_state_t usart6_DmaDriverState = { -#endif - &usart6_Resource, &usart6_DmaResource, &USART6_DmaHandle, &USART6_DmaRxHandle, &USART6_DmaTxHandle, -}; - -static int32_t USART6_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART6_InitPins(); - return USART_DmaInitialize(cb_event, &usart6_DmaDriverState); -} - -static int32_t USART6_DmaUninitialize(void) -{ - USART6_DeinitPins(); - return USART_DmaUninitialize(&usart6_DmaDriverState); -} - -static int32_t USART6_DmaPowerControl(ARM_POWER_STATE state) -{ - return USART_DmaPowerControl(state, &usart6_DmaDriverState); -} - -static int32_t USART6_DmaSend(const void *data, uint32_t num) -{ - return USART_DmaSend(data, num, &usart6_DmaDriverState); -} - -static int32_t USART6_DmaReceive(void *data, uint32_t num) -{ - return USART_DmaReceive(data, num, &usart6_DmaDriverState); -} - -static int32_t USART6_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_DmaTransfer(data_out, data_in, num, &usart6_DmaDriverState); -} - -static uint32_t USART6_DmaGetTxCount(void) -{ - return USART_DmaGetTxCount(&usart6_DmaDriverState); -} - -static uint32_t USART6_DmaGetRxCount(void) -{ - return USART_DmaGetRxCount(&usart6_DmaDriverState); -} - -static int32_t USART6_DmaControl(uint32_t control, uint32_t arg) -{ - return USART_DmaControl(control, arg, &usart6_DmaDriverState); -} - -static ARM_USART_STATUS USART6_DmaGetStatus(void) -{ - return USART_DmaGetStatus(&usart6_DmaDriverState); -} - -#endif - -#else - -usart_handle_t USART6_Handle; -#if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1) -static uint8_t usart6_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("usart6_non_blocking_driver_state") -cmsis_usart_non_blocking_driver_state_t usart6_NonBlockingDriverState = { -#else -cmsis_usart_non_blocking_driver_state_t usart6_NonBlockingDriverState = { -#endif - &usart6_Resource, &USART6_Handle, -}; - -static int32_t USART6_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART6_InitPins(); - return USART_NonBlockingInitialize(cb_event, &usart6_NonBlockingDriverState); -} - -static int32_t USART6_NonBlockingUninitialize(void) -{ - USART6_DeinitPins(); - return USART_NonBlockingUninitialize(&usart6_NonBlockingDriverState); -} - -static int32_t USART6_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = USART_NonBlockingPowerControl(state, &usart6_NonBlockingDriverState); -#if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (usart6_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - USART_TransferStartRingBuffer(usart6_NonBlockingDriverState.resource->base, - usart6_NonBlockingDriverState.handle, usart6_rxRingBuffer, USART_RX_BUFFER_LEN); - } -#endif - return result; -} - -static int32_t USART6_NonBlockingSend(const void *data, uint32_t num) -{ - return USART_NonBlockingSend(data, num, &usart6_NonBlockingDriverState); -} - -static int32_t USART6_NonBlockingReceive(void *data, uint32_t num) -{ - return USART_NonBlockingReceive(data, num, &usart6_NonBlockingDriverState); -} - -static int32_t USART6_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_NonBlockingTransfer(data_out, data_in, num, &usart6_NonBlockingDriverState); -} - -static uint32_t USART6_NonBlockingGetTxCount(void) -{ - return USART_NonBlockingGetTxCount(&usart6_NonBlockingDriverState); -} - -static uint32_t USART6_NonBlockingGetRxCount(void) -{ - return USART_NonBlockingGetRxCount(&usart6_NonBlockingDriverState); -} - -static int32_t USART6_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = USART_NonBlockingControl(control, arg, &usart6_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } -#if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1) - /* Start receiving interrupts */ - usart6_NonBlockingDriverState.resource->base->FIFOINTENSET |= - USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -#endif - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS USART6_NonBlockingGetStatus(void) -{ - return USART_NonBlockingGetStatus(&usart6_NonBlockingDriverState); -} - -#endif - -ARM_DRIVER_USART Driver_USART6 = { - USARTx_GetVersion, USARTx_GetCapabilities, -#if RTE_USART6_DMA_EN - USART6_DmaInitialize, USART6_DmaUninitialize, USART6_DmaPowerControl, USART6_DmaSend, USART6_DmaReceive, - USART6_DmaTransfer, USART6_DmaGetTxCount, USART6_DmaGetRxCount, USART6_DmaControl, USART6_DmaGetStatus, -#else - USART6_NonBlockingInitialize, - USART6_NonBlockingUninitialize, - USART6_NonBlockingPowerControl, - USART6_NonBlockingSend, - USART6_NonBlockingReceive, - USART6_NonBlockingTransfer, - USART6_NonBlockingGetTxCount, - USART6_NonBlockingGetRxCount, - USART6_NonBlockingControl, - USART6_NonBlockingGetStatus, -#endif - USARTx_SetModemControl, USARTx_GetModemStatus}; - -#endif /* usart6 */ - -#if defined(USART7) && RTE_USART7 - -/* User needs to provide the implementation for USART7_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t USART7_GetFreq(void); -extern void USART7_InitPins(void); -extern void USART7_DeinitPins(void); - -cmsis_usart_resource_t usart7_Resource = {USART7, USART7_GetFreq}; - -#if RTE_USART7_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_usart_dma_resource_t usart7_DmaResource = { - RTE_USART7_DMA_TX_DMA_BASE, RTE_USART7_DMA_TX_CH, RTE_USART7_DMA_RX_DMA_BASE, RTE_USART7_DMA_RX_CH, -}; - -usart_dma_handle_t USART7_DmaHandle; -dma_handle_t USART7_DmaRxHandle; -dma_handle_t USART7_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("usart7_dma_driver_state") -cmsis_usart_dma_driver_state_t usart7_DmaDriverState = { -#else -cmsis_usart_dma_driver_state_t usart7_DmaDriverState = { -#endif - &usart7_Resource, &usart7_DmaResource, &USART7_DmaHandle, &USART7_DmaRxHandle, &USART7_DmaTxHandle, -}; - -static int32_t USART7_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART7_InitPins(); - return USART_DmaInitialize(cb_event, &usart7_DmaDriverState); -} - -static int32_t USART7_DmaUninitialize(void) -{ - USART7_DeinitPins(); - return USART_DmaUninitialize(&usart7_DmaDriverState); -} - -static int32_t USART7_DmaPowerControl(ARM_POWER_STATE state) -{ - return USART_DmaPowerControl(state, &usart7_DmaDriverState); -} - -static int32_t USART7_DmaSend(const void *data, uint32_t num) -{ - return USART_DmaSend(data, num, &usart7_DmaDriverState); -} - -static int32_t USART7_DmaReceive(void *data, uint32_t num) -{ - return USART_DmaReceive(data, num, &usart7_DmaDriverState); -} - -static int32_t USART7_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_DmaTransfer(data_out, data_in, num, &usart7_DmaDriverState); -} - -static uint32_t USART7_DmaGetTxCount(void) -{ - return USART_DmaGetTxCount(&usart7_DmaDriverState); -} - -static uint32_t USART7_DmaGetRxCount(void) -{ - return USART_DmaGetRxCount(&usart7_DmaDriverState); -} - -static int32_t USART7_DmaControl(uint32_t control, uint32_t arg) -{ - return USART_DmaControl(control, arg, &usart7_DmaDriverState); -} - -static ARM_USART_STATUS USART7_DmaGetStatus(void) -{ - return USART_DmaGetStatus(&usart7_DmaDriverState); -} - -#endif - -#else - -usart_handle_t USART7_Handle; -#if defined(USART7_RX_BUFFER_ENABLE) && (USART7_RX_BUFFER_ENABLE == 1) -static uint8_t usart7_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("usart7_non_blocking_driver_state") -cmsis_usart_non_blocking_driver_state_t usart7_NonBlockingDriverState = { -#else -cmsis_usart_non_blocking_driver_state_t usart7_NonBlockingDriverState = { -#endif - &usart7_Resource, &USART7_Handle, -}; - -static int32_t USART7_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART7_InitPins(); - return USART_NonBlockingInitialize(cb_event, &usart7_NonBlockingDriverState); -} - -static int32_t USART7_NonBlockingUninitialize(void) -{ - USART7_DeinitPins(); - return USART_NonBlockingUninitialize(&usart7_NonBlockingDriverState); -} - -static int32_t USART7_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = USART_NonBlockingPowerControl(state, &usart7_NonBlockingDriverState); -#if defined(USART7_RX_BUFFER_ENABLE) && (USART7_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (usart7_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - USART_TransferStartRingBuffer(usart7_NonBlockingDriverState.resource->base, - usart7_NonBlockingDriverState.handle, usart7_rxRingBuffer, USART_RX_BUFFER_LEN); - } -#endif - return result; -} - -static int32_t USART7_NonBlockingSend(const void *data, uint32_t num) -{ - return USART_NonBlockingSend(data, num, &usart7_NonBlockingDriverState); -} - -static int32_t USART7_NonBlockingReceive(void *data, uint32_t num) -{ - return USART_NonBlockingReceive(data, num, &usart7_NonBlockingDriverState); -} - -static int32_t USART7_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_NonBlockingTransfer(data_out, data_in, num, &usart7_NonBlockingDriverState); -} - -static uint32_t USART7_NonBlockingGetTxCount(void) -{ - return USART_NonBlockingGetTxCount(&usart7_NonBlockingDriverState); -} - -static uint32_t USART7_NonBlockingGetRxCount(void) -{ - return USART_NonBlockingGetRxCount(&usart7_NonBlockingDriverState); -} - -static int32_t USART7_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = USART_NonBlockingControl(control, arg, &usart7_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } -#if defined(USART7_RX_BUFFER_ENABLE) && (USART7_RX_BUFFER_ENABLE == 1) - /* Start receiving interrupts */ - usart7_NonBlockingDriverState.resource->base->FIFOINTENSET |= - USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -#endif - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS USART7_NonBlockingGetStatus(void) -{ - return USART_NonBlockingGetStatus(&usart7_NonBlockingDriverState); -} - -#endif - -ARM_DRIVER_USART Driver_USART7 = { - USARTx_GetVersion, USARTx_GetCapabilities, -#if RTE_USART7_DMA_EN - USART7_DmaInitialize, USART7_DmaUninitialize, USART7_DmaPowerControl, USART7_DmaSend, USART7_DmaReceive, - USART7_DmaTransfer, USART7_DmaGetTxCount, USART7_DmaGetRxCount, USART7_DmaControl, USART7_DmaGetStatus, -#else - USART7_NonBlockingInitialize, - USART7_NonBlockingUninitialize, - USART7_NonBlockingPowerControl, - USART7_NonBlockingSend, - USART7_NonBlockingReceive, - USART7_NonBlockingTransfer, - USART7_NonBlockingGetTxCount, - USART7_NonBlockingGetRxCount, - USART7_NonBlockingControl, - USART7_NonBlockingGetStatus, -#endif - USARTx_SetModemControl, USARTx_GetModemStatus}; - -#endif /* usart7 */ - -#if defined(USART8) && RTE_USART8 - -/* User needs to provide the implementation for USART8_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t USART8_GetFreq(void); -extern void USART8_InitPins(void); -extern void USART8_DeinitPins(void); - -cmsis_usart_resource_t usart8_Resource = {USART8, USART8_GetFreq}; - -#if RTE_USART8_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_usart_dma_resource_t usart8_DmaResource = { - RTE_USART8_DMA_TX_DMA_BASE, RTE_USART8_DMA_TX_CH, RTE_USART8_DMA_RX_DMA_BASE, RTE_USART8_DMA_RX_CH, -}; - -usart_dma_handle_t USART8_DmaHandle; -dma_handle_t USART8_DmaRxHandle; -dma_handle_t USART8_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("usart8_dma_driver_state") -cmsis_usart_dma_driver_state_t usart8_DmaDriverState = { -#else -cmsis_usart_dma_driver_state_t usart8_DmaDriverState = { -#endif - &usart8_Resource, &usart8_DmaResource, &USART8_DmaHandle, &USART8_DmaRxHandle, &USART8_DmaTxHandle, -}; - -static int32_t USART8_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART8_InitPins(); - return USART_DmaInitialize(cb_event, &usart8_DmaDriverState); -} - -static int32_t USART8_DmaUninitialize(void) -{ - USART8_DeinitPins(); - return USART_DmaUninitialize(&usart8_DmaDriverState); -} - -static int32_t USART8_DmaPowerControl(ARM_POWER_STATE state) -{ - return USART_DmaPowerControl(state, &usart8_DmaDriverState); -} - -static int32_t USART8_DmaSend(const void *data, uint32_t num) -{ - return USART_DmaSend(data, num, &usart8_DmaDriverState); -} - -static int32_t USART8_DmaReceive(void *data, uint32_t num) -{ - return USART_DmaReceive(data, num, &usart8_DmaDriverState); -} - -static int32_t USART8_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_DmaTransfer(data_out, data_in, num, &usart8_DmaDriverState); -} - -static uint32_t USART8_DmaGetTxCount(void) -{ - return USART_DmaGetTxCount(&usart8_DmaDriverState); -} - -static uint32_t USART8_DmaGetRxCount(void) -{ - return USART_DmaGetRxCount(&usart8_DmaDriverState); -} - -static int32_t USART8_DmaControl(uint32_t control, uint32_t arg) -{ - return USART_DmaControl(control, arg, &usart8_DmaDriverState); -} - -static ARM_USART_STATUS USART8_DmaGetStatus(void) -{ - return USART_DmaGetStatus(&usart8_DmaDriverState); -} - -#endif - -#else - -usart_handle_t USART8_Handle; -#if defined(USART8_RX_BUFFER_ENABLE) && (USART8_RX_BUFFER_ENABLE == 1) -static uint8_t usart8_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("usart8_non_blocking_driver_state") -cmsis_usart_non_blocking_driver_state_t usart8_NonBlockingDriverState = { -#else -cmsis_usart_non_blocking_driver_state_t usart8_NonBlockingDriverState = { -#endif - &usart8_Resource, &USART8_Handle, -}; - -static int32_t USART8_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART8_InitPins(); - return USART_NonBlockingInitialize(cb_event, &usart8_NonBlockingDriverState); -} - -static int32_t USART8_NonBlockingUninitialize(void) -{ - USART8_DeinitPins(); - return USART_NonBlockingUninitialize(&usart8_NonBlockingDriverState); -} - -static int32_t USART8_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = USART_NonBlockingPowerControl(state, &usart8_NonBlockingDriverState); -#if defined(USART8_RX_BUFFER_ENABLE) && (USART8_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (usart8_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - USART_TransferStartRingBuffer(usart8_NonBlockingDriverState.resource->base, - usart8_NonBlockingDriverState.handle, usart8_rxRingBuffer, USART_RX_BUFFER_LEN); - } -#endif - - return result; -} - -static int32_t USART8_NonBlockingSend(const void *data, uint32_t num) -{ - return USART_NonBlockingSend(data, num, &usart8_NonBlockingDriverState); -} - -static int32_t USART8_NonBlockingReceive(void *data, uint32_t num) -{ - return USART_NonBlockingReceive(data, num, &usart8_NonBlockingDriverState); -} - -static int32_t USART8_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_NonBlockingTransfer(data_out, data_in, num, &usart8_NonBlockingDriverState); -} - -static uint32_t USART8_NonBlockingGetTxCount(void) -{ - return USART_NonBlockingGetTxCount(&usart8_NonBlockingDriverState); -} - -static uint32_t USART8_NonBlockingGetRxCount(void) -{ - return USART_NonBlockingGetRxCount(&usart8_NonBlockingDriverState); -} - -static int32_t USART8_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = USART_NonBlockingControl(control, arg, &usart8_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } -#if defined(USART8_RX_BUFFER_ENABLE) && (USART8_RX_BUFFER_ENABLE == 1) - /* Start receiving interrupts */ - usart8_NonBlockingDriverState.resource->base->FIFOINTENSET |= - USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -#endif - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS USART8_NonBlockingGetStatus(void) -{ - return USART_NonBlockingGetStatus(&usart8_NonBlockingDriverState); -} - -#endif - -/* usart8 Driver Control Block */ -ARM_DRIVER_USART Driver_USART8 = { - USARTx_GetVersion, USARTx_GetCapabilities, -#if RTE_USART8_DMA_EN - USART8_DmaInitialize, USART8_DmaUninitialize, USART8_DmaPowerControl, USART8_DmaSend, USART8_DmaReceive, - USART8_DmaTransfer, USART8_DmaGetTxCount, USART8_DmaGetRxCount, USART8_DmaControl, USART8_DmaGetStatus, -#else - USART8_NonBlockingInitialize, - USART8_NonBlockingUninitialize, - USART8_NonBlockingPowerControl, - USART8_NonBlockingSend, - USART8_NonBlockingReceive, - USART8_NonBlockingTransfer, - USART8_NonBlockingGetTxCount, - USART8_NonBlockingGetRxCount, - USART8_NonBlockingControl, - USART8_NonBlockingGetStatus, -#endif - USARTx_SetModemControl, USARTx_GetModemStatus}; - -#endif /* usart8 */ - -#if defined(USART9) && RTE_USART9 - -/* User needs to provide the implementation for USART9_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t USART9_GetFreq(void); -extern void USART9_InitPins(void); -extern void USART9_DeinitPins(void); - -cmsis_usart_resource_t usart9_Resource = {USART9, USART9_GetFreq}; - -#if RTE_USART9_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_usart_dma_resource_t usart9_DmaResource = { - RTE_USART9_DMA_TX_DMA_BASE, RTE_USART9_DMA_TX_CH, RTE_USART9_DMA_RX_DMA_BASE, RTE_USART9_DMA_RX_CH, -}; - -usart_dma_handle_t USART9_DmaHandle; -dma_handle_t USART9_DmaRxHandle; -dma_handle_t USART9_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("usart9_dma_driver_state") -cmsis_usart_dma_driver_state_t usart9_DmaDriverState = { -#else -cmsis_usart_dma_driver_state_t usart9_DmaDriverState = { -#endif - &usart9_Resource, &usart9_DmaResource, &USART9_DmaHandle, &USART9_DmaRxHandle, &USART9_DmaTxHandle, -}; - -static int32_t USART9_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART9_InitPins(); - return USART_DmaInitialize(cb_event, &usart9_DmaDriverState); -} - -static int32_t USART9_DmaUninitialize(void) -{ - USART9_DeinitPins(); - return USART_DmaUninitialize(&usart9_DmaDriverState); -} - -static int32_t USART9_DmaPowerControl(ARM_POWER_STATE state) -{ - return USART_DmaPowerControl(state, &usart9_DmaDriverState); -} - -static int32_t USART9_DmaSend(const void *data, uint32_t num) -{ - return USART_DmaSend(data, num, &usart9_DmaDriverState); -} - -static int32_t USART9_DmaReceive(void *data, uint32_t num) -{ - return USART_DmaReceive(data, num, &usart9_DmaDriverState); -} - -static int32_t USART9_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_DmaTransfer(data_out, data_in, num, &usart9_DmaDriverState); -} - -static uint32_t USART9_DmaGetTxCount(void) -{ - return USART_DmaGetTxCount(&usart9_DmaDriverState); -} - -static uint32_t USART9_DmaGetRxCount(void) -{ - return USART_DmaGetRxCount(&usart9_DmaDriverState); -} - -static int32_t USART9_DmaControl(uint32_t control, uint32_t arg) -{ - return USART_DmaControl(control, arg, &usart9_DmaDriverState); -} - -static ARM_USART_STATUS USART9_DmaGetStatus(void) -{ - return USART_DmaGetStatus(&usart9_DmaDriverState); -} - -#endif - -#else - -usart_handle_t USART9_Handle; -#if defined(USART9_RX_BUFFER_ENABLE) && (USART9_RX_BUFFER_ENABLE == 1) -static uint8_t usart9_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("usart9_non_blocking_driver_state") -cmsis_usart_non_blocking_driver_state_t usart9_NonBlockingDriverState = { -#else -cmsis_usart_non_blocking_driver_state_t usart9_NonBlockingDriverState = { -#endif - &usart9_Resource, &USART9_Handle, -}; - -static int32_t USART9_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART9_InitPins(); - return USART_NonBlockingInitialize(cb_event, &usart9_NonBlockingDriverState); -} - -static int32_t USART9_NonBlockingUninitialize(void) -{ - USART9_DeinitPins(); - return USART_NonBlockingUninitialize(&usart9_NonBlockingDriverState); -} - -static int32_t USART9_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = USART_NonBlockingPowerControl(state, &usart9_NonBlockingDriverState); -#if defined(USART9_RX_BUFFER_ENABLE) && (USART9_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (usart9_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - USART_TransferStartRingBuffer(usart9_NonBlockingDriverState.resource->base, - usart9_NonBlockingDriverState.handle, usart9_rxRingBuffer, USART_RX_BUFFER_LEN); - } -#endif - - return result; -} - -static int32_t USART9_NonBlockingSend(const void *data, uint32_t num) -{ - return USART_NonBlockingSend(data, num, &usart9_NonBlockingDriverState); -} - -static int32_t USART9_NonBlockingReceive(void *data, uint32_t num) -{ - return USART_NonBlockingReceive(data, num, &usart9_NonBlockingDriverState); -} - -static int32_t USART9_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_NonBlockingTransfer(data_out, data_in, num, &usart9_NonBlockingDriverState); -} - -static uint32_t USART9_NonBlockingGetTxCount(void) -{ - return USART_NonBlockingGetTxCount(&usart9_NonBlockingDriverState); -} - -static uint32_t USART9_NonBlockingGetRxCount(void) -{ - return USART_NonBlockingGetRxCount(&usart9_NonBlockingDriverState); -} - -static int32_t USART9_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = USART_NonBlockingControl(control, arg, &usart9_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } -#if defined(USART9_RX_BUFFER_ENABLE) && (USART9_RX_BUFFER_ENABLE == 1) - /* Start receiving interrupts */ - usart9_NonBlockingDriverState.resource->base->FIFOINTENSET |= - USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -#endif - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS USART9_NonBlockingGetStatus(void) -{ - return USART_NonBlockingGetStatus(&usart9_NonBlockingDriverState); -} - -#endif - -/* usart9 Driver Control Block */ -ARM_DRIVER_USART Driver_USART9 = { - USARTx_GetVersion, USARTx_GetCapabilities, -#if RTE_USART9_DMA_EN - USART9_DmaInitialize, USART9_DmaUninitialize, USART9_DmaPowerControl, USART9_DmaSend, USART9_DmaReceive, - USART9_DmaTransfer, USART9_DmaGetTxCount, USART9_DmaGetRxCount, USART9_DmaControl, USART9_DmaGetStatus, -#else - USART9_NonBlockingInitialize, - USART9_NonBlockingUninitialize, - USART9_NonBlockingPowerControl, - USART9_NonBlockingSend, - USART9_NonBlockingReceive, - USART9_NonBlockingTransfer, - USART9_NonBlockingGetTxCount, - USART9_NonBlockingGetRxCount, - USART9_NonBlockingControl, - USART9_NonBlockingGetStatus, -#endif - USARTx_SetModemControl, USARTx_GetModemStatus}; - -#endif /* usart9 */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_usart_cmsis.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_usart_cmsis.h deleted file mode 100644 index ee6c0928dff..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_usart_cmsis.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2013-2016 ARM Limited. All rights reserved. - * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. - * Copyright 2016-2017 NXP. Not a Contribution. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#ifndef _FSL_USART_CMSIS_H_ -#define _FSL_USART_CMSIS_H_ - -#include "fsl_common.h" -#include "Driver_USART.h" -#include "RTE_Device.h" -#include "fsl_usart.h" -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) -#include "fsl_usart_dma.h" -#endif - -#if defined(USART0) -extern ARM_DRIVER_USART Driver_USART0; -#endif /* USART0 */ - -#if defined(USART1) -extern ARM_DRIVER_USART Driver_USART1; -#endif /* USART1 */ - -#if defined(USART2) -extern ARM_DRIVER_USART Driver_USART2; -#endif /* USART2 */ - -#if defined(USART3) -extern ARM_DRIVER_USART Driver_USART3; -#endif /* USART3 */ - -#if defined(USART4) -extern ARM_DRIVER_USART Driver_USART4; -#endif /* USART4 */ - -#if defined(USART5) -extern ARM_DRIVER_USART Driver_USART5; -#endif /* USART5 */ - -#if defined(USART6) -extern ARM_DRIVER_USART Driver_USART6; -#endif /* USART6 */ - -#if defined(USART7) -extern ARM_DRIVER_USART Driver_USART7; -#endif /* USART7 */ - -/* USART Driver state flags */ -#define USART_FLAG_UNINIT (0) -#define USART_FLAG_INIT (1 << 0) -#define USART_FLAG_POWER (1 << 1) -#define USART_FLAG_CONFIGURED (1 << 2) - -#endif /* _FSL_USART_CMSIS_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/SConscript b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/SConscript deleted file mode 100644 index 46044bf7bed..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/SConscript +++ /dev/null @@ -1,11 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -CPPPATH = [cwd] -src = Glob('*.c') - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_adc.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_adc.c deleted file mode 100644 index 2c44d9ff7d8..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_adc.c +++ /dev/null @@ -1,399 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_adc.h" -#include "fsl_clock.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_adc" -#endif - - -static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -static uint32_t ADC_GetInstance(ADC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_adcBases); instance++) - { - if (s_adcBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_adcBases)); - - return instance; -} - -void ADC_Init(ADC_Type *base, const adc_config_t *config) -{ - assert(config != NULL); - - uint32_t tmp32 = 0U; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable clock. */ - CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Disable the interrupts. */ - base->INTEN = 0U; /* Quickly disable all the interrupts. */ - - /* Configure the ADC block. */ - tmp32 = ADC_CTRL_CLKDIV(config->clockDividerNumber); - -#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE - /* Async or Sync clock mode. */ - switch (config->clockMode) - { - case kADC_ClockAsynchronousMode: - tmp32 |= ADC_CTRL_ASYNMODE_MASK; - break; - default: /* kADC_ClockSynchronousMode */ - break; - } -#endif /* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */ - -#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL - /* Resolution. */ - tmp32 |= ADC_CTRL_RESOL(config->resolution); -#endif/* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */ - -#if defined(FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL) & FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL - /* Bypass calibration. */ - if (config->enableBypassCalibration) - { - tmp32 |= ADC_CTRL_BYPASSCAL_MASK; - } -#endif/* FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL. */ - -#if defined(FSL_FEATURE_ADC_HAS_CTRL_TSAMP) & FSL_FEATURE_ADC_HAS_CTRL_TSAMP - /* Sample time clock count. */ - tmp32 |= ADC_CTRL_TSAMP(config->sampleTimeNumber); -#endif/* FSL_FEATURE_ADC_HAS_CTRL_TSAMP. */ - -#if defined(FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE) & FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE - if(config->enableLowPowerMode) - { - tmp32 |= ADC_CTRL_LPWRMODE_MASK; - } -#endif/* FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE. */ - - base->CTRL = tmp32; - -#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG - base->TRM &= ~ADC_TRM_VRANGE_MASK; - base->TRM |= ADC_TRM_VRANGE(config->voltageRange); -#endif/* FSL_FEATURE_ADC_HAS_TRIM_REG. */ -} - -void ADC_GetDefaultConfig(adc_config_t *config) -{ -#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE - config->clockMode = kADC_ClockSynchronousMode; -#endif/* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */ - - config->clockDividerNumber = 0U; -#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL - config->resolution = kADC_Resolution12bit; -#endif/* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */ -#if defined(FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL) & FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL - config->enableBypassCalibration = false; -#endif/* FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL. */ -#if defined(FSL_FEATURE_ADC_HAS_CTRL_TSAMP) & FSL_FEATURE_ADC_HAS_CTRL_TSAMP - config->sampleTimeNumber = 0U; -#endif/* FSL_FEATURE_ADC_HAS_CTRL_TSAMP. */ -#if defined(FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE) & FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE - config->enableLowPowerMode = false; -#endif/* FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE. */ -#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG - config->voltageRange = kADC_HighVoltageRange; -#endif/* FSL_FEATURE_ADC_HAS_TRIM_REG. */ -} - -void ADC_Deinit(ADC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -#if !(defined(FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) && FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) -#if defined(FSL_FEATURE_ADC_HAS_CALIB_REG) & FSL_FEATURE_ADC_HAS_CALIB_REG -bool ADC_DoSelfCalibration(ADC_Type *base) -{ - uint32_t i; - - /* Enable the converter. */ - /* This bit acn only be set 1 by software. It is cleared automatically whenever the ADC is powered down. - This bit should be set after at least 10 ms after the ADC is powered on. */ - base->STARTUP = ADC_STARTUP_ADC_ENA_MASK; - for (i = 0U; i < 0x10; i++) /* Wait a few clocks to startup up. */ - { - __ASM("NOP"); - } - if (!(base->STARTUP & ADC_STARTUP_ADC_ENA_MASK)) - { - return false; /* ADC is not powered up. */ - } - - /* If not in by-pass mode, do the calibration. */ - if ((ADC_CALIB_CALREQD_MASK == (base->CALIB & ADC_CALIB_CALREQD_MASK)) && - (0U == (base->CTRL & ADC_CTRL_BYPASSCAL_MASK))) - { - /* Calibration is needed, do it now. */ - base->CALIB = ADC_CALIB_CALIB_MASK; - i = 0xF0000; - while ((ADC_CALIB_CALIB_MASK == (base->CALIB & ADC_CALIB_CALIB_MASK)) && (--i)) - { - } - if (i == 0U) - { - return false; /* Calibration timeout. */ - } - } - - /* A dummy conversion cycle will be performed. */ - base->STARTUP |= ADC_STARTUP_ADC_INIT_MASK; - i = 0x7FFFF; - while ((ADC_STARTUP_ADC_INIT_MASK == (base->STARTUP & ADC_STARTUP_ADC_INIT_MASK)) && (--i)) - { - } - if (i == 0U) - { - return false; - } - - return true; -} -#else -bool ADC_DoSelfCalibration(ADC_Type *base, uint32_t frequency) -{ - uint32_t tmp32; - uint32_t i = 0xF0000; - - /* Store the current contents of the ADC CTRL register. */ - tmp32 = base->CTRL; - - /* Start ADC self-calibration. */ - base->CTRL |= ADC_CTRL_CALMODE_MASK; - - /* Divide the system clock to yield an ADC clock of about 500 kHz. */ - base->CTRL &= ~ADC_CTRL_CLKDIV_MASK; - base->CTRL |= ADC_CTRL_CLKDIV((frequency / 500000U) - 1U); - - /* Clear the LPWR bit. */ - base->CTRL &= ~ADC_CTRL_LPWRMODE_MASK; - - /* Wait for the completion of calibration. */ - while ((ADC_CTRL_CALMODE_MASK == (base->CTRL & ADC_CTRL_CALMODE_MASK)) && (--i)) - { - } - /* Restore the contents of the ADC CTRL register. */ - base->CTRL = tmp32; - - /* Judge whether the calibration is overtime. */ - if (i == 0U) - { - return false; /* Calibration timeout. */ - } - - return true; -} -#endif/* FSL_FEATURE_ADC_HAS_CALIB_REG */ -#endif/* FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC*/ - -void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config) -{ - assert(config != NULL); - - uint32_t tmp32; - - tmp32 = ADC_SEQ_CTRL_CHANNELS(config->channelMask) /* Channel mask. */ - | ADC_SEQ_CTRL_TRIGGER(config->triggerMask); /* Trigger mask. */ - - /* Polarity for tirgger signal. */ - switch (config->triggerPolarity) - { - case kADC_TriggerPolarityPositiveEdge: - tmp32 |= ADC_SEQ_CTRL_TRIGPOL_MASK; - break; - default: /* kADC_TriggerPolarityNegativeEdge */ - break; - } - - /* Bypass the clock Sync. */ - if (config->enableSyncBypass) - { - tmp32 |= ADC_SEQ_CTRL_SYNCBYPASS_MASK; - } - - /* Interrupt point. */ - switch (config->interruptMode) - { - case kADC_InterruptForEachSequence: - tmp32 |= ADC_SEQ_CTRL_MODE_MASK; - break; - default: /* kADC_InterruptForEachConversion */ - break; - } - - /* One trigger for a conversion, or for a sequence. */ - if (config->enableSingleStep) - { - tmp32 |= ADC_SEQ_CTRL_SINGLESTEP_MASK; - } - - base->SEQ_CTRL[0] = tmp32; -} - -void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config) -{ - assert(config != NULL); - - uint32_t tmp32; - - tmp32 = ADC_SEQ_CTRL_CHANNELS(config->channelMask) /* Channel mask. */ - | ADC_SEQ_CTRL_TRIGGER(config->triggerMask); /* Trigger mask. */ - - /* Polarity for tirgger signal. */ - switch (config->triggerPolarity) - { - case kADC_TriggerPolarityPositiveEdge: - tmp32 |= ADC_SEQ_CTRL_TRIGPOL_MASK; - break; - default: /* kADC_TriggerPolarityPositiveEdge */ - break; - } - - /* Bypass the clock Sync. */ - if (config->enableSyncBypass) - { - tmp32 |= ADC_SEQ_CTRL_SYNCBYPASS_MASK; - } - - /* Interrupt point. */ - switch (config->interruptMode) - { - case kADC_InterruptForEachSequence: - tmp32 |= ADC_SEQ_CTRL_MODE_MASK; - break; - default: /* kADC_InterruptForEachConversion */ - break; - } - - /* One trigger for a conversion, or for a sequence. */ - if (config->enableSingleStep) - { - tmp32 |= ADC_SEQ_CTRL_SINGLESTEP_MASK; - } - - base->SEQ_CTRL[1] = tmp32; -} - -bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info) -{ - assert(info != NULL); - - uint32_t tmp32 = base->SEQ_GDAT[0]; /* Read to clear the status. */ - - if (0U == (ADC_SEQ_GDAT_DATAVALID_MASK & tmp32)) - { - return false; - } - - info->result = (tmp32 & ADC_SEQ_GDAT_RESULT_MASK) >> ADC_SEQ_GDAT_RESULT_SHIFT; - info->thresholdCompareStatus = - (adc_threshold_compare_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPRANGE_MASK) >> ADC_SEQ_GDAT_THCMPRANGE_SHIFT); - info->thresholdCorssingStatus = - (adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT); - info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT; - info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK); - - return true; -} - -bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info) -{ - assert(info != NULL); - - uint32_t tmp32 = base->SEQ_GDAT[1]; /* Read to clear the status. */ - - if (0U == (ADC_SEQ_GDAT_DATAVALID_MASK & tmp32)) - { - return false; - } - - info->result = (tmp32 & ADC_SEQ_GDAT_RESULT_MASK) >> ADC_SEQ_GDAT_RESULT_SHIFT; - info->thresholdCompareStatus = - (adc_threshold_compare_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPRANGE_MASK) >> ADC_SEQ_GDAT_THCMPRANGE_SHIFT); - info->thresholdCorssingStatus = - (adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT); - info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT; - info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK); - - return true; -} - -bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info) -{ - assert(info != NULL); - assert(channel < ADC_DAT_COUNT); - - uint32_t tmp32 = base->DAT[channel]; /* Read to clear the status. */ - - if (0U == (ADC_DAT_DATAVALID_MASK & tmp32)) - { - return false; - } - - info->result = (tmp32 & ADC_DAT_RESULT_MASK) >> ADC_DAT_RESULT_SHIFT; - info->thresholdCompareStatus = - (adc_threshold_compare_status_t)((tmp32 & ADC_DAT_THCMPRANGE_MASK) >> ADC_DAT_THCMPRANGE_SHIFT); - info->thresholdCorssingStatus = - (adc_threshold_crossing_status_t)((tmp32 & ADC_DAT_THCMPCROSS_MASK) >> ADC_DAT_THCMPCROSS_SHIFT); - info->channelNumber = (tmp32 & ADC_DAT_CHANNEL_MASK) >> ADC_DAT_CHANNEL_SHIFT; - info->overrunFlag = ((tmp32 & ADC_DAT_OVERRUN_MASK) == ADC_DAT_OVERRUN_MASK); - - return true; -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_adc.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_adc.h deleted file mode 100644 index 06f29a26e82..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_adc.h +++ /dev/null @@ -1,729 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __FSL_ADC_H__ -#define __FSL_ADC_H__ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_adc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief ADC driver version 2.2.0. */ -#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) -/*@}*/ - -/*! - * @brief Flags - */ -enum _adc_status_flags -{ - kADC_ThresholdCompareFlagOnChn0 = 1U << 0U, /*!< Threshold comparison event on Channel 0. */ - kADC_ThresholdCompareFlagOnChn1 = 1U << 1U, /*!< Threshold comparison event on Channel 1. */ - kADC_ThresholdCompareFlagOnChn2 = 1U << 2U, /*!< Threshold comparison event on Channel 2. */ - kADC_ThresholdCompareFlagOnChn3 = 1U << 3U, /*!< Threshold comparison event on Channel 3. */ - kADC_ThresholdCompareFlagOnChn4 = 1U << 4U, /*!< Threshold comparison event on Channel 4. */ - kADC_ThresholdCompareFlagOnChn5 = 1U << 5U, /*!< Threshold comparison event on Channel 5. */ - kADC_ThresholdCompareFlagOnChn6 = 1U << 6U, /*!< Threshold comparison event on Channel 6. */ - kADC_ThresholdCompareFlagOnChn7 = 1U << 7U, /*!< Threshold comparison event on Channel 7. */ - kADC_ThresholdCompareFlagOnChn8 = 1U << 8U, /*!< Threshold comparison event on Channel 8. */ - kADC_ThresholdCompareFlagOnChn9 = 1U << 9U, /*!< Threshold comparison event on Channel 9. */ - kADC_ThresholdCompareFlagOnChn10 = 1U << 10U, /*!< Threshold comparison event on Channel 10. */ - kADC_ThresholdCompareFlagOnChn11 = 1U << 11U, /*!< Threshold comparison event on Channel 11. */ - kADC_OverrunFlagForChn0 = - 1U << 12U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 0. */ - kADC_OverrunFlagForChn1 = - 1U << 13U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 1. */ - kADC_OverrunFlagForChn2 = - 1U << 14U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 2. */ - kADC_OverrunFlagForChn3 = - 1U << 15U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 3. */ - kADC_OverrunFlagForChn4 = - 1U << 16U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 4. */ - kADC_OverrunFlagForChn5 = - 1U << 17U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 5. */ - kADC_OverrunFlagForChn6 = - 1U << 18U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 6. */ - kADC_OverrunFlagForChn7 = - 1U << 19U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 7. */ - kADC_OverrunFlagForChn8 = - 1U << 20U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 8. */ - kADC_OverrunFlagForChn9 = - 1U << 21U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 9. */ - kADC_OverrunFlagForChn10 = - 1U << 22U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 10. */ - kADC_OverrunFlagForChn11 = - 1U << 23U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 11. */ - kADC_GlobalOverrunFlagForSeqA = 1U << 24U, /*!< Mirror the glabal OVERRUN status flag for conversion sequence A. */ - kADC_GlobalOverrunFlagForSeqB = 1U << 25U, /*!< Mirror the global OVERRUN status flag for conversion sequence B. */ - kADC_ConvSeqAInterruptFlag = 1U << 28U, /*!< Sequence A interrupt/DMA trigger. */ - kADC_ConvSeqBInterruptFlag = 1U << 29U, /*!< Sequence B interrupt/DMA trigger. */ - kADC_ThresholdCompareInterruptFlag = 1U << 30U, /*!< Threshold comparision interrupt flag. */ - kADC_OverrunInterruptFlag = 1U << 31U, /*!< Overrun interrupt flag. */ -}; - -/*! - * @brief Interrupts - * @note Not all the interrupt options are listed here - */ -enum _adc_interrupt_enable -{ - kADC_ConvSeqAInterruptEnable = ADC_INTEN_SEQA_INTEN_MASK, /*!< Enable interrupt upon completion of each individual - conversion in sequence A, or entire sequence. */ - kADC_ConvSeqBInterruptEnable = ADC_INTEN_SEQB_INTEN_MASK, /*!< Enable interrupt upon completion of each individual - conversion in sequence B, or entire sequence. */ - kADC_OverrunInterruptEnable = ADC_INTEN_OVR_INTEN_MASK, /*!< Enable the detection of an overrun condition on any of - the channel data registers will cause an overrun - interrupt/DMA trigger. */ -}; - -#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE -/*! - * @brief Define selection of clock mode. - */ -typedef enum _adc_clock_mode -{ - kADC_ClockSynchronousMode = - 0U, /*!< The ADC clock would be derived from the system clock based on "clockDividerNumber". */ - kADC_ClockAsynchronousMode = 1U, /*!< The ADC clock would be based on the SYSCON block's divider. */ -} adc_clock_mode_t; -#endif/* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */ - - -#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL -/*! - * @brief Define selection of resolution. - */ -typedef enum _adc_resolution -{ - kADC_Resolution6bit = 0U, /*!< 6-bit resolution. */ - kADC_Resolution8bit = 1U, /*!< 8-bit resolution. */ - kADC_Resolution10bit = 2U, /*!< 10-bit resolution. */ - kADC_Resolution12bit = 3U, /*!< 12-bit resolution. */ -} adc_resolution_t; -#endif/* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */ - -#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG -/*! -* @brief Definfe range of the analog supply voltage VDDA. -*/ -typedef enum _adc_voltage_range -{ - kADC_HighVoltageRange = 0U, /* High voltage. VDD = 2.7 V to 3.6 V. */ - kADC_LowVoltageRange = 1U, /* Low voltage. VDD = 2.4 V to 2.7 V. */ -} adc_vdda_range_t; -#endif/* FSL_FEATURE_ADC_HAS_TRIM_REG. */ - -/*! - * @brief Define selection of polarity of selected input trigger for conversion sequence. - */ -typedef enum _adc_trigger_polarity -{ - kADC_TriggerPolarityNegativeEdge = 0U, /*!< A negative edge launches the conversion sequence on the trigger(s). */ - kADC_TriggerPolarityPositiveEdge = 1U, /*!< A positive edge launches the conversion sequence on the trigger(s). */ -} adc_trigger_polarity_t; - -/*! - * @brief Define selection of conversion sequence's priority. - */ -typedef enum _adc_priority -{ - kADC_PriorityLow = 0U, /*!< This sequence would be preempted when another sequence is started. */ - kADC_PriorityHigh = 1U, /*!< This sequence would preempt other sequence even when it is started. */ -} adc_priority_t; - -/*! - * @brief Define selection of conversion sequence's interrupt. - */ -typedef enum _adc_seq_interrupt_mode -{ - kADC_InterruptForEachConversion = 0U, /*!< The sequence interrupt/DMA trigger will be set at the end of each - individual ADC conversion inside this conversion sequence. */ - kADC_InterruptForEachSequence = 1U, /*!< The sequence interrupt/DMA trigger will be set when the entire set of - this sequence conversions completes. */ -} adc_seq_interrupt_mode_t; - -/*! - * @brief Define status of threshold compare result. - */ -typedef enum _adc_threshold_compare_status -{ - kADC_ThresholdCompareInRange = 0U, /*!< LOW threshold <= conversion value <= HIGH threshold. */ - kADC_ThresholdCompareBelowRange = 1U, /*!< conversion value < LOW threshold. */ - kADC_ThresholdCompareAboveRange = 2U, /*!< conversion value > HIGH threshold. */ -} adc_threshold_compare_status_t; - -/*! - * @brief Define status of threshold crossing detection result. - */ -typedef enum _adc_threshold_crossing_status -{ - /* The conversion on this channel had the same relationship (above or below) to the threshold value established by - * the designated LOW threshold value as did the previous conversion on this channel. */ - kADC_ThresholdCrossingNoDetected = 0U, /*!< No threshold Crossing detected. */ - - /* Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this - * channel was above the threshold value established by the designated LOW threshold value and the current sample is - * below that threshold. */ - kADC_ThresholdCrossingDownward = 2U, /*!< Downward Threshold Crossing detected. */ - - /* Indicates that a thre shold crossing in the upward direction has occurred - i.e. the previous sample on this - * channel was below the threshold value established by the designated LOW threshold value and the current sample is - * above that threshold. */ - kADC_ThresholdCrossingUpward = 3U, /*!< Upward Threshold Crossing Detected. */ -} adc_threshold_crossing_status_t; - -/*! - * @brief Define interrupt mode for threshold compare event. - */ -typedef enum _adc_threshold_interrupt_mode -{ - kADC_ThresholdInterruptDisabled = 0U, /*!< Threshold comparison interrupt is disabled. */ - kADC_ThresholdInterruptOnOutside = 1U, /*!< Threshold comparison interrupt is enabled on outside threshold. */ - kADC_ThresholdInterruptOnCrossing = 2U, /*!< Threshold comparison interrupt is enabled on crossing threshold. */ -} adc_threshold_interrupt_mode_t; - -/*! - * @brief Define structure for configuring the block. - */ -typedef struct _adc_config -{ -#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE - adc_clock_mode_t clockMode; /*!< Select the clock mode for ADC converter. */ -#endif/* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */ - uint32_t clockDividerNumber; /*!< This field is only available when using kADC_ClockSynchronousMode for "clockMode" - field. The divider would be plused by 1 based on the value in this field. The - available range is in 8 bits. */ -#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL - adc_resolution_t resolution; /*!< Select the conversion bits. */ -#endif/* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */ -#if defined(FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL) & FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL - bool enableBypassCalibration; /*!< By default, a calibration cycle must be performed each time the chip is - powered-up. Re-calibration may be warranted periodically - especially if - operating conditions have changed. To enable this option would avoid the need to - calibrate if offset error is not a concern in the application. */ -#endif/* FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL. */ -#if defined(FSL_FEATURE_ADC_HAS_CTRL_TSAMP) & FSL_FEATURE_ADC_HAS_CTRL_TSAMP - uint32_t sampleTimeNumber; /*!< By default, with value as "0U", the sample period would be 2.5 ADC clocks. Then, - to plus the "sampleTimeNumber" value here. The available value range is in 3 bits.*/ -#endif/* FSL_FEATURE_ADC_HAS_CTRL_TSAMP. */ -#if defined(FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE) & FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE - bool enableLowPowerMode; /*!< If disable low-power mode, ADC remains activated even when no conversions are requested. - If enable low-power mode, The ADC is automatically powered-down when no conversions are - taking place. */ -#endif/* FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE. */ -#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG -adc_vdda_range_t voltageRange; /*!< Configure the ADC for the appropriate operating range of the analog supply voltage VDDA. - Failure to set the area correctly causes the ADC to return incorrect conversion results. */ -#endif/* FSL_FEATURE_ADC_HAS_TRIM_REG. */ -} adc_config_t; - -/*! - * @brief Define structure for configuring conversion sequence. - */ -typedef struct _adc_conv_seq_config -{ - uint32_t channelMask; /*!< Selects which one or more of the ADC channels will be sampled and converted when this - sequence is launched. The masked channels would be involved in current conversion - sequence, beginning with the lowest-order. The available range is in 12-bit. */ - uint32_t triggerMask; /*!< Selects which one or more of the available hardware trigger sources will cause this - conversion sequence to be initiated. The available range is 6-bit.*/ - adc_trigger_polarity_t triggerPolarity; /*!< Select the trigger to lauch conversion sequence. */ - bool enableSyncBypass; /*!< To enable this feature allows the hardware trigger input to bypass synchronization - flip-flop stages and therefore shorten the time between the trigger input signal and the - start of a conversion. */ - bool enableSingleStep; /*!< When enabling this feature, a trigger will launch a single conversion on the next - channel in the sequence instead of the default response of launching an entire sequence - of conversions. */ - adc_seq_interrupt_mode_t interruptMode; /*!< Select the interrpt/DMA trigger mode. */ -} adc_conv_seq_config_t; - -/*! - * @brief Define structure of keeping conversion result information. - */ -typedef struct _adc_result_info -{ - uint32_t result; /*!< Keep the conversion data value. */ - adc_threshold_compare_status_t thresholdCompareStatus; /*!< Keep the threshold compare status. */ - adc_threshold_crossing_status_t thresholdCorssingStatus; /*!< Keep the threshold crossing status. */ - uint32_t channelNumber; /*!< Keep the channel number for this conversion. */ - bool overrunFlag; /*!< Keep the status whether the conversion is overrun or not. */ - /* The data available flag would be returned by the reading result API. */ -} adc_result_info_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @name Initialization and Deinitialization - * @{ - */ - -/*! - * @brief Initialize the ADC module. - * - * @param base ADC peripheral base address. - * @param config Pointer to configuration structure, see to #adc_config_t. - */ -void ADC_Init(ADC_Type *base, const adc_config_t *config); - -/*! - * @brief Deinitialize the ADC module. - * - * @param base ADC peripheral base address. - */ -void ADC_Deinit(ADC_Type *base); - -/*! - * @brief Gets an available pre-defined settings for initial configuration. - * - * This function initializes the initial configuration structure with an available settings. The default values are: - * @code - * config->clockMode = kADC_ClockSynchronousMode; - * config->clockDividerNumber = 0U; - * config->resolution = kADC_Resolution12bit; - * config->enableBypassCalibration = false; - * config->sampleTimeNumber = 0U; - * @endcode - * @param config Pointer to configuration structure. - */ -void ADC_GetDefaultConfig(adc_config_t *config); - -#if !(defined(FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) && FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) -#if defined(FSL_FEATURE_ADC_HAS_CALIB_REG) && FSL_FEATURE_ADC_HAS_CALIB_REG -/*! - * @brief Do the self hardware calibration. - * - * @param base ADC peripheral base address. - * @retval true Calibration succeed. - * @retval false Calibration failed. - */ -bool ADC_DoSelfCalibration(ADC_Type *base); -#else -/*! - * @brief Do the self calibration. To calibrate the ADC, set the ADC clock to 500 kHz. - * In order to achieve the specified ADC accuracy, the A/D converter must be recalibrated, at a minimum, - * following every chip reset before initiating normal ADC operation. - * - * @param base ADC peripheral base address. - * @param frequency The ststem clock frequency to ADC. - * @retval true Calibration succeed. - * @retval false Calibration failed. - */ -bool ADC_DoSelfCalibration(ADC_Type *base, uint32_t frequency); -#endif/* FSL_FEATURE_ADC_HAS_CALIB_REG */ -#endif/* FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC */ - -#if !(defined(FSL_FEATURE_ADC_HAS_NO_INSEL) && FSL_FEATURE_ADC_HAS_NO_INSEL) -/*! - * @brief Enable the internal temperature sensor measurement. - * - * When enabling the internal temperature sensor measurement, the channel 0 would be connected to internal sensor - * instead of external pin. - * - * @param base ADC peripheral base address. - * @param enable Switcher to enable the feature or not. - */ -static inline void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable) -{ - if (enable) - { - base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0x3); - } - else - { - base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0); - } -} -#endif /* FSL_FEATURE_ADC_HAS_NO_INSEL. */ -/* @} */ - -/*! - * @name Control conversion sequence A. - * @{ - */ - -/*! - * @brief Enable the conversion sequence A. - * - * In order to avoid spuriously triggering the sequence, the trigger to conversion sequence should be ready before the - * sequence is ready. when the sequence is disabled, the trigger would be ignored. Also, it is suggested to disable the - * sequence during changing the sequence's setting. - * - * @param base ADC peripheral base address. - * @param enable Switcher to enable the feature or not. - */ -static inline void ADC_EnableConvSeqA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_SEQ_ENA_MASK; - } - else - { - base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_SEQ_ENA_MASK; - } -} - -/*! - * @brief Configure the conversion sequence A. - * - * @param base ADC peripheral base address. - * @param config Pointer to configuration structure, see to #adc_conv_seq_config_t. - */ -void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config); - -/*! - * @brief Do trigger the sequence's conversion by software. - * - * @param base ADC peripheral base address. - */ -static inline void ADC_DoSoftwareTriggerConvSeqA(ADC_Type *base) -{ - base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_START_MASK; -} - -/*! - * @brief Enable the burst conversion of sequence A. - * - * Enable the burst mode would cause the conversion sequence to be cntinuously cycled through. Other triggers would be - * ignored while this mode is enabled. Repeated conversions could be halted by disabling this mode. And the sequence - * currently in process will be completed before cnversions are terminated. - * Note that a new sequence could begin just before the burst mode is disabled. - * - * @param base ADC peripheral base address. - * @param enable Switcher to enable this feature. - */ -static inline void ADC_EnableConvSeqABurstMode(ADC_Type *base, bool enable) -{ - if (enable) - { - base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_BURST_MASK; - } - else - { - base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_BURST_MASK; - } -} - -/*! - * @brief Set the high priority for conversion sequence A. - * - * @param base ADC peripheral bass address. - */ -static inline void ADC_SetConvSeqAHighPriority(ADC_Type *base) -{ - base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_LOWPRIO_MASK; -} - -/* @} */ - -/*! - * @name Control conversion sequence B. - * @{ - */ - -/*! - * @brief Enable the conversion sequence B. - * - * In order to avoid spuriously triggering the sequence, the trigger to conversion sequence should be ready before the - * sequence is ready. when the sequence is disabled, the trigger would be ignored. Also, it is suggested to disable the - * sequence during changing the sequence's setting. - * - * @param base ADC peripheral base address. - * @param enable Switcher to enable the feature or not. - */ -static inline void ADC_EnableConvSeqB(ADC_Type *base, bool enable) -{ - if (enable) - { - base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_SEQ_ENA_MASK; - } - else - { - base->SEQ_CTRL[1] &= ~ADC_SEQ_CTRL_SEQ_ENA_MASK; - } -} - -/*! - * @brief Configure the conversion sequence B. - * - * @param base ADC peripheral base address. - * @param config Pointer to configuration structure, see to #adc_conv_seq_config_t. - */ -void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config); - -/*! - * @brief Do trigger the sequence's conversion by software. - * - * @param base ADC peripheral base address. - */ -static inline void ADC_DoSoftwareTriggerConvSeqB(ADC_Type *base) -{ - base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_START_MASK; -} - -/*! - * @brief Enable the burst conversion of sequence B. - * - * Enable the burst mode would cause the conversion sequence to be continuously cycled through. Other triggers would be - * ignored while this mode is enabled. Repeated conversions could be halted by disabling this mode. And the sequence - * currently in process will be completed before cnversions are terminated. - * Note that a new sequence could begin just before the burst mode is disabled. - * - * @param base ADC peripheral base address. - * @param enable Switcher to enable this feature. - */ -static inline void ADC_EnableConvSeqBBurstMode(ADC_Type *base, bool enable) -{ - if (enable) - { - base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_BURST_MASK; - } - else - { - base->SEQ_CTRL[1] &= ~ADC_SEQ_CTRL_BURST_MASK; - } -} - -/*! - * @brief Set the high priority for conversion sequence B. - * - * @param base ADC peripheral bass address. - */ -static inline void ADC_SetConvSeqBHighPriority(ADC_Type *base) -{ - base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_LOWPRIO_MASK; -} - -/* @} */ - -/*! - * @name Data result. - * @{ - */ - -/*! - * @brief Get the global ADC conversion infomation of sequence A. - * - * @param base ADC peripheral base address. - * @param info Pointer to information structure, see to #adc_result_info_t; - * @retval true The conversion result is ready. - * @retval false The conversion result is not ready yet. - */ -bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info); - -/*! - * @brief Get the global ADC conversion infomation of sequence B. - * - * @param base ADC peripheral base address. - * @param info Pointer to information structure, see to #adc_result_info_t; - * @retval true The conversion result is ready. - * @retval false The conversion result is not ready yet. - */ -bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info); - -/*! - * @brief Get the channel's ADC conversion completed under each conversion sequence. - * - * @param base ADC peripheral base address. - * @param channel The indicated channel number. - * @param info Pointer to information structure, see to #adc_result_info_t; - * @retval true The conversion result is ready. - * @retval false The conversion result is not ready yet. - */ -bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info); - -/* @} */ - -/*! - * @name Threshold function. - * @{ - */ - -/*! - * @brief Set the threshhold pair 0 with low and high value. - * - * @param base ADC peripheral base address. - * @param lowValue LOW threshold value. - * @param highValue HIGH threshold value. - */ -static inline void ADC_SetThresholdPair0(ADC_Type *base, uint32_t lowValue, uint32_t highValue) -{ - base->THR0_LOW = ADC_THR0_LOW_THRLOW(lowValue); - base->THR0_HIGH = ADC_THR0_HIGH_THRHIGH(highValue); -} - -/*! - * @brief Set the threshhold pair 1 with low and high value. - * - * @param base ADC peripheral base address. - * @param lowValue LOW threshold value. The available value is with 12-bit. - * @param highValue HIGH threshold value. The available value is with 12-bit. - */ -static inline void ADC_SetThresholdPair1(ADC_Type *base, uint32_t lowValue, uint32_t highValue) -{ - base->THR1_LOW = ADC_THR1_LOW_THRLOW(lowValue); - base->THR1_HIGH = ADC_THR1_HIGH_THRHIGH(highValue); -} - -/*! - * @brief Set given channels to apply the threshold pare 0. - * - * @param base ADC peripheral base address. - * @param channelMask Indicated channels' mask. - */ -static inline void ADC_SetChannelWithThresholdPair0(ADC_Type *base, uint32_t channelMask) -{ - base->CHAN_THRSEL &= ~(channelMask); -} - -/*! - * @brief Set given channels to apply the threshold pare 1. - * - * @param base ADC peripheral base address. - * @param channelMask Indicated channels' mask. - */ -static inline void ADC_SetChannelWithThresholdPair1(ADC_Type *base, uint32_t channelMask) -{ - base->CHAN_THRSEL |= channelMask; -} - -/* @} */ - -/*! - * @name Interrupts. - * @{ - */ - -/*! - * @brief Enable interrupts for conversion sequences. - * - * @param base ADC peripheral base address. - * @param mask Mask of interrupt mask value for global block except each channal, see to #_adc_interrupt_enable. - */ -static inline void ADC_EnableInterrupts(ADC_Type *base, uint32_t mask) -{ - base->INTEN |= (0x7 & mask); -} - -/*! - * @brief Disable interrupts for conversion sequence. - * - * @param base ADC peripheral base address. - * @param mask Mask of interrupt mask value for global block except each channel, see to #_adc_interrupt_enable. - */ -static inline void ADC_DisableInterrupts(ADC_Type *base, uint32_t mask) -{ - base->INTEN &= ~(0x7 & mask); -} - -/*! - * @brief Enable the interrupt of threshold compare event for each channel. - * @deprecated Do not use this function. It has been superceded by @ADC_EnableThresholdCompareInterrupt - */ -static inline void ADC_EnableShresholdCompareInterrupt(ADC_Type *base, - uint32_t channel, - adc_threshold_interrupt_mode_t mode) -{ - base->INTEN = (base->INTEN & ~(0x3U << ((channel << 1U) + 3U))) | ((uint32_t)(mode) << ((channel << 1U) + 3U)); -} - -/*! - * @brief Enable the interrupt of threshold compare event for each channel. - * - * @param base ADC peripheral base address. - * @param channel Channel number. - * @param mode Interrupt mode for threshold compare event, see to #adc_threshold_interrupt_mode_t. - */ -static inline void ADC_EnableThresholdCompareInterrupt(ADC_Type *base, - uint32_t channel, - adc_threshold_interrupt_mode_t mode) -{ - base->INTEN = (base->INTEN & ~(0x3U << ((channel << 1U) + 3U))) | ((uint32_t)(mode) << ((channel << 1U) + 3U)); -} - -/* @} */ - -/*! - * @name Status. - * @{ - */ - -/*! - * @brief Get status flags of ADC module. - * - * @param base ADC peripheral base address. - * @return Mask of status flags of module, see to #_adc_status_flags. - */ -static inline uint32_t ADC_GetStatusFlags(ADC_Type *base) -{ - return base->FLAGS; -} - -/*! - * @brief Clear status flags of ADC module. - * - * @param base ADC peripheral base address. - * @param mask Mask of status flags of module, see to #_adc_status_flags. - */ -static inline void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) -{ - base->FLAGS = mask; /* Write 1 to clear. */ -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/* @} */ - -#endif /* __FSL_ADC_H__ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_clock.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_clock.c deleted file mode 100644 index 3d1231bcf3a..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_clock.c +++ /dev/null @@ -1,1605 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016 - 2017 , NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_common.h" -#include "fsl_clock.h" -#include "fsl_power.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.clock" -#endif -#define NVALMAX (0x100U) -#define PVALMAX (0x20U) -#define MVALMAX (0x8000U) - -#define PLL_MAX_N_DIV 0x100U - -#define INDEX_SECTOR_TRIM48 ((uint32_t *)0x01000444U) -#define INDEX_SECTOR_TRIM96 ((uint32_t *)0x01000430U) -/*-------------------------------------------------------------------------- -!!! If required these #defines can be moved to chip library file -----------------------------------------------------------------------------*/ - -#define PLL_SSCG0_MDEC_VAL_P (0U) /* MDEC is in bits 16 downto 0 */ -#define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) /* NDEC is in bits 9 downto 0 */ -#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */ -#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P) -#define PLL_PDEC_VAL_P (0U) /* PDEC is in bits 6:0 */ -#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P) - -#define PLL_MIN_CCO_FREQ_MHZ (75000000U) -#define PLL_MAX_CCO_FREQ_MHZ (150000000U) -#define PLL_LOWER_IN_LIMIT (4000U) /*!< Minimum PLL input rate */ -#define PLL_MIN_IN_SSMODE (2000000U) -#define PLL_MAX_IN_SSMODE (4000000U) - -/* Middle of the range values for spread-spectrum */ -#define PLL_SSCG_MF_FREQ_VALUE 4U -#define PLL_SSCG_MC_COMP_VALUE 2U -#define PLL_SSCG_MR_DEPTH_VALUE 4U -#define PLL_SSCG_DITHER_VALUE 0U - -/* PLL NDEC reg */ -#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) -/* PLL PDEC reg */ -#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M) -/* SSCG control0 */ -#define PLL_SSCG0_MDEC_VAL_SET(value) (((unsigned long)(value) << PLL_SSCG0_MDEC_VAL_P) & PLL_SSCG0_MDEC_VAL_M) - -/* SSCG control1 */ -#define PLL_SSCG1_MD_FRACT_P 0U -#define PLL_SSCG1_MD_INT_P 11U -#define PLL_SSCG1_MD_FRACT_M (0x7FFUL << PLL_SSCG1_MD_FRACT_P) -#define PLL_SSCG1_MD_INT_M (0xFFUL << PLL_SSCG1_MD_INT_P) - -#define PLL_SSCG1_MD_FRACT_SET(value) (((unsigned long)(value) << PLL_SSCG1_MD_FRACT_P) & PLL_SSCG1_MD_FRACT_M) -#define PLL_SSCG1_MD_INT_SET(value) (((unsigned long)(value) << PLL_SSCG1_MD_INT_P) & PLL_SSCG1_MD_INT_M) - -/* Saved value of PLL output rate, computed whenever needed to save run-time - computation on each call to retrive the PLL rate. */ -static uint32_t s_Pll_Freq; - -/* I2S mclk. */ -static uint32_t s_I2S_Mclk_Freq = 0U; - -/** External clock rate on the CLKIN pin in Hz. If not used, - set this to 0. Otherwise, set it to the exact rate in Hz this pin is - being driven at. */ -static const uint32_t s_Ext_Clk_Freq = 0U; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/* Find encoded NDEC value for raw N value, max N = NVALMAX */ -static uint32_t pllEncodeN(uint32_t N); -/* Find decoded N value for raw NDEC value */ -static uint32_t pllDecodeN(uint32_t NDEC); -/* Find encoded PDEC value for raw P value, max P = PVALMAX */ -static uint32_t pllEncodeP(uint32_t P); -/* Find decoded P value for raw PDEC value */ -static uint32_t pllDecodeP(uint32_t PDEC); -/* Find encoded MDEC value for raw M value, max M = MVALMAX */ -static uint32_t pllEncodeM(uint32_t M); -/* Find decoded M value for raw MDEC value */ -static uint32_t pllDecodeM(uint32_t MDEC); -/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ -static void pllFindSel(uint32_t M, bool bypassFBDIV2, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); -/* Get predivider (N) from PLL NDEC setting */ -static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg); -/* Get postdivider (P) from PLL PDEC setting */ -static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg); -/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ -static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg); -/* Get the greatest common divisor */ -static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); -/* Set PLL output based on desired output rate */ -static pll_error_t CLOCK_GetPllConfig( - uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useFeedbackDiv2, bool useSS); -/* Update local PLL rate variable */ -static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup); - -static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, - 42, 44, 45, 46, 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61}; -/******************************************************************************* - * Code - ******************************************************************************/ - -void CLOCK_AttachClk(clock_attach_id_t connection) -{ - bool final_descriptor = false; - uint8_t mux; - uint8_t pos; - uint32_t i; - volatile uint32_t *pClkSel; - - pClkSel = &(SYSCON->MAINCLKSELA); - - for (i = 0U; (i <= 2U) && (!final_descriptor); i++) - { - connection = (clock_attach_id_t)(connection >> (i * 12U)); /* pick up next descriptor */ - mux = (uint8_t)connection; - if (connection) - { - pos = ((connection & 0xf00U) >> 8U) - 1U; - if (mux == CM_ASYNCAPB) - { - ASYNC_SYSCON->ASYNCAPBCLKSELA = pos; - } - else - { - pClkSel[mux] = pos; - } - } - else - { - final_descriptor = true; - } - } -} - -void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) -{ - volatile uint32_t *pClkDiv; - - pClkDiv = &(SYSCON->SYSTICKCLKDIV); - if (reset) - { - pClkDiv[div_name] = 1U << 29U; - } - if (divided_by_value == 0U) /* halt */ - { - pClkDiv[div_name] = 1U << 30U; - } - else - { - pClkDiv[div_name] = (divided_by_value - 1U); - } -} - -/* Set FRO Clocking */ -status_t CLOCK_SetupFROClocking(uint32_t iFreq) -{ - uint32_t usb_adj; - if ((iFreq != 12000000U) && (iFreq != 48000000U) && (iFreq != 96000000U)) - { - return kStatus_Fail; - } - /* Power up the FRO and set this as the base clock */ - POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); - /* back up the value of whether USB adj is selected, in which case we will have a value of 1 else 0 */ - usb_adj = ((SYSCON->FROCTRL) & SYSCON_FROCTRL_USBCLKADJ_MASK) >> SYSCON_FROCTRL_USBCLKADJ_SHIFT; - if (iFreq > 12000000U) - { - if (iFreq == 96000000U) - { - SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM96) | - SYSCON_FROCTRL_SEL(1) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) | - SYSCON_FROCTRL_HSPDCLK(1); - } - else - { - SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM48) | - SYSCON_FROCTRL_SEL(0) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) | - SYSCON_FROCTRL_HSPDCLK(1); - } - } - else - { - SYSCON->FROCTRL &= ~SYSCON_FROCTRL_HSPDCLK(1); - } - - return 0U; -} - -uint32_t CLOCK_GetFro12MFreq(void) -{ - return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0U : 12000000U; -} - -uint32_t CLOCK_GetExtClkFreq(void) -{ - return (s_Ext_Clk_Freq); -} -uint32_t CLOCK_GetWdtOscFreq(void) -{ - uint8_t freq_sel, div_sel; - if (SYSCON->PDRUNCFG[kPDRUNCFG_PD_WDT_OSC >> 8UL] & (1UL << (kPDRUNCFG_PD_WDT_OSC & 0xffU))) - { - return 0U; - } - else - { - div_sel = ((SYSCON->WDTOSCCTRL & 0x1f) + 1) << 1; - freq_sel = - wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)]; - return ((uint32_t)freq_sel * 50000U) / ((uint32_t)div_sel); - } -} - -/* Get HF FRO Clk */ -uint32_t CLOCK_GetFroHfFreq(void) -{ - if ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) || !(SYSCON->FROCTRL & SYSCON_FROCTRL_HSPDCLK_MASK)) - { - return 0U; - } - - if(SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) - { - return 96000000U; - } - else - { - return 48000000U; - } -} - -uint32_t CLOCK_GetPllOutFreq(void) -{ - return s_Pll_Freq; -} - -uint32_t CLOCK_GetOsc32KFreq(void) -{ - return CLK_RTC_32K_CLK; /* Needs to be corrected to check that RTC Clock is enabled */ -} -uint32_t CLOCK_GetCoreSysClkFreq(void) -{ - uint32_t freq = 0U; - - switch(SYSCON->MAINCLKSELB) - { - case 0U: - if(SYSCON->MAINCLKSELA == 0U) - { - freq = CLOCK_GetFro12MFreq(); - } - else if(SYSCON->MAINCLKSELA == 1U) - { - freq = CLOCK_GetExtClkFreq(); - } - else if(SYSCON->MAINCLKSELA == 2U) - { - freq = CLOCK_GetWdtOscFreq(); - } - else if(SYSCON->MAINCLKSELA == 3U) - { - freq = CLOCK_GetFroHfFreq(); - } - else - {} - break; - case 2U: - freq = CLOCK_GetPllOutFreq(); - break; - - case 3U: - freq = CLOCK_GetOsc32KFreq(); - break; - - default: - break; - - } - - return freq; -} -uint32_t CLOCK_GetI2SMClkFreq(void) -{ - return s_I2S_Mclk_Freq; -} - -uint32_t CLOCK_GetAsyncApbClkFreq(void) -{ - async_clock_src_t clkSrc; - uint32_t clkRate; - - clkSrc = CLOCK_GetAsyncApbClkSrc(); - - switch (clkSrc) - { - case kCLOCK_AsyncMainClk: - clkRate = CLOCK_GetCoreSysClkFreq(); - break; - case kCLOCK_AsyncFro12Mhz: - clkRate = CLK_FRO_12MHZ; - break; - default: - clkRate = 0U; - break; - } - - return clkRate; -} - -/* Get FLEXCOMM Clk */ -uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) -{ - uint32_t freq = 0U; - - switch(SYSCON->FXCOMCLKSEL[id]) - { - case 0U: - freq = CLOCK_GetFro12MFreq(); - break; - case 1U: - freq = CLOCK_GetFroHfFreq(); - break; - case 2U: - freq = CLOCK_GetPllOutFreq(); - break; - case 3U: - freq = CLOCK_GetI2SMClkFreq(); - break; - case 4U: - freq = CLOCK_GetFrgClkFreq(); - break; - - default: - break; - } - - return freq; -} - -/* Get FRG Clk */ -uint32_t CLOCK_GetFRGInputClock(void) -{ - uint32_t freq = 0U; - - switch(SYSCON->FRGCLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPllOutFreq(); - break; - case 2U: - freq = CLOCK_GetFro12MFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - - default: - break; - } - - return freq; -} - -/* Get DMIC Clk */ -uint32_t CLOCK_GetDmicClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->DMICCLKSEL) - { - case 0U: - freq = CLOCK_GetFro12MFreq(); - break; - case 1U: - freq = CLOCK_GetFroHfFreq(); - break; - case 2U: - freq = CLOCK_GetPllOutFreq(); - break; - case 3U: - freq = CLOCK_GetI2SMClkFreq(); - break; - case 4U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 5U: - freq = CLOCK_GetWdtOscFreq(); - break; - default: - break; - } - - return freq / ((SYSCON->DMICCLKDIV & 0xffU) + 1U);; -} - -uint32_t CLOCK_SetFRGClock(uint32_t freq) -{ - uint32_t input = CLOCK_GetFRGInputClock(); - uint32_t mul; - - if ((freq > 48000000) || (freq > input) || (input / freq >= 2)) - { - /* FRG output frequency should be less than equal to 48MHz */ - return 0; - } - else - { - mul = ((uint64_t)(input - freq) * 256) / ((uint64_t)freq); - SYSCON->FRGCTRL = (mul << SYSCON_FRGCTRL_MULT_SHIFT) | SYSCON_FRGCTRL_DIV_MASK; - return 1; - } -} - -/* Get FRG Clk */ -uint32_t CLOCK_GetFrgClkFreq(void) -{ - uint32_t freq = 0U; - - if((SYSCON->FRGCTRL & SYSCON_FRGCTRL_DIV_MASK) == SYSCON_FRGCTRL_DIV_MASK) - { - freq = ((uint64_t)CLOCK_GetFRGInputClock() * (SYSCON_FRGCTRL_DIV_MASK + 1)) / - ((SYSCON_FRGCTRL_DIV_MASK + 1) + ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_MULT_MASK) >> SYSCON_FRGCTRL_MULT_SHIFT)); - } - else - { - freq = 0U; - } - - return freq; -} - -uint32_t CLOCK_GetUsbClkFreq(void) -{ - uint32_t freq = 0U; - - if(SYSCON->USBCLKSEL == 0U) - { - freq = CLOCK_GetFroHfFreq(); - } - else if (SYSCON->USBCLKSEL == 1) - { - freq = CLOCK_GetPllOutFreq(); - } - else - {} - - return freq / ((SYSCON->USBCLKDIV & 0xffU) + 1U); -} - -uint32_t CLOCK_GetFreq(clock_name_t clockName) -{ - uint32_t freq; - switch (clockName) - { - case kCLOCK_CoreSysClk: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case kCLOCK_BusClk: - freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); - break; - case kCLOCK_FroHf: - freq = CLOCK_GetFroHfFreq(); - break; - case kCLOCK_Fro12M: - freq = CLOCK_GetFro12MFreq(); - break; - case kCLOCK_PllOut: - freq = CLOCK_GetPllOutFreq(); - break; - case kCLOCK_UsbClk: - freq = CLOCK_GetUsbClkFreq(); - break; - case kCLOCK_WdtOsc: - freq = CLOCK_GetWdtOscFreq(); - break; - case kCLOCK_Frg: - freq = CLOCK_GetFrgClkFreq(); - break; - case kCLOCK_Dmic: - freq = CLOCK_GetDmicClkFreq(); - break; - - case kCLOCK_AsyncApbClk: - freq = CLOCK_GetAsyncApbClkFreq(); - break; - - case kCLOCK_FlexI2S: - freq = CLOCK_GetI2SMClkFreq(); - break; - - case kCLOCK_Flexcomm0: - freq = CLOCK_GetFlexCommClkFreq(0U); - break; - case kCLOCK_Flexcomm1: - freq = CLOCK_GetFlexCommClkFreq(1U); - break; - case kCLOCK_Flexcomm2: - freq = CLOCK_GetFlexCommClkFreq(2U); - break; - case kCLOCK_Flexcomm3: - freq = CLOCK_GetFlexCommClkFreq(3U); - break; - case kCLOCK_Flexcomm4: - freq = CLOCK_GetFlexCommClkFreq(4U); - break; - case kCLOCK_Flexcomm5: - freq = CLOCK_GetFlexCommClkFreq(5U); - break; - case kCLOCK_Flexcomm6: - freq = CLOCK_GetFlexCommClkFreq(6U); - break; - case kCLOCK_Flexcomm7: - freq = CLOCK_GetFlexCommClkFreq(7U); - break; - default: - freq = 0U; - break; - } - - return freq; -} - -/* Set the FLASH wait states for the passed frequency */ -void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq) -{ - if (iFreq <= 12000000U) - { - CLOCK_SetFLASHAccessCycles(kCLOCK_Flash1Cycle); - } - else if (iFreq <= 30000000U) - { - CLOCK_SetFLASHAccessCycles(kCLOCK_Flash2Cycle); - } - else if (iFreq <= 60000000U) - { - CLOCK_SetFLASHAccessCycles(kCLOCK_Flash3Cycle); - } - else if (iFreq <= 85000000U) - { - CLOCK_SetFLASHAccessCycles(kCLOCK_Flash4Cycle); - } - else - { - CLOCK_SetFLASHAccessCycles(kCLOCK_Flash5Cycle); - } -} - -/* Find encoded NDEC value for raw N value, max N = NVALMAX */ -static uint32_t pllEncodeN(uint32_t N) -{ - uint32_t x, i; - - /* Find NDec */ - switch (N) - { - case 0U: - x = 0x3FFU; - break; - - case 1U: - x = 0x302U; - break; - - case 2U: - x = 0x202U; - break; - - default: - x = 0x080U; - for (i = N; i <= NVALMAX; i++) - { - x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU); - } - break; - } - - return x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P); -} - -/* Find decoded N value for raw NDEC value */ -static uint32_t pllDecodeN(uint32_t NDEC) -{ - uint32_t n, x, i; - - /* Find NDec */ - switch (NDEC) - { - case 0x3FFU: - n = 0U; - break; - - case 0x302U: - n = 1U; - break; - - case 0x202U: - n = 2U; - break; - - default: - x = 0x080U; - n = 0xFFFFFFFFU; - for (i = NVALMAX; ((i >= 3U) && (n == 0xFFFFFFFFU)); i--) - { - x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU); - if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC) - { - /* Decoded value of NDEC */ - n = i; - } - } - break; - } - - return n; -} - -/* Find encoded PDEC value for raw P value, max P = PVALMAX */ -static uint32_t pllEncodeP(uint32_t P) -{ - uint32_t x, i; - - /* Find PDec */ - switch (P) - { - case 0U: - x = 0x7FU; - break; - - case 1U: - x = 0x62U; - break; - - case 2U: - x = 0x42U; - break; - - default: - x = 0x10U; - for (i = P; i <= PVALMAX; i++) - { - x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU); - } - break; - } - - return x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P); -} - -/* Find decoded P value for raw PDEC value */ -static uint32_t pllDecodeP(uint32_t PDEC) -{ - uint32_t p, x, i; - - /* Find PDec */ - switch (PDEC) - { - case 0x7FU: - p = 0U; - break; - - case 0x62U: - p = 1U; - break; - - case 0x42U: - p = 2U; - break; - - default: - x = 0x10U; - p = 0xFFFFFFFFU; - for (i = PVALMAX; ((i >= 3U) && (p == 0xFFFFFFFFU)); i--) - { - x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU); - if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC) - { - /* Decoded value of PDEC */ - p = i; - } - } - break; - } - - return p; -} - -/* Find encoded MDEC value for raw M value, max M = MVALMAX */ -static uint32_t pllEncodeM(uint32_t M) -{ - uint32_t i, x; - - /* Find MDec */ - switch (M) - { - case 0U: - x = 0x1FFFFU; - break; - - case 1U: - x = 0x18003U; - break; - - case 2U: - x = 0x10003U; - break; - - default: - x = 0x04000U; - for (i = M; i <= MVALMAX; i++) - { - x = (((x ^ (x >> 1U)) & 1U) << 14U) | ((x >> 1U) & 0x3FFFU); - } - break; - } - - return x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P); -} - -/* Find decoded M value for raw MDEC value */ -static uint32_t pllDecodeM(uint32_t MDEC) -{ - uint32_t m, i, x; - - /* Find MDec */ - switch (MDEC) - { - case 0x1FFFFU: - m = 0U; - break; - - case 0x18003U: - m = 1U; - break; - - case 0x10003U: - m = 2U; - break; - - default: - x = 0x04000U; - m = 0xFFFFFFFFU; - for (i = MVALMAX; ((i >= 3U) && (m == 0xFFFFFFFFU)); i--) - { - x = (((x ^ (x >> 1U)) & 1) << 14U) | ((x >> 1U) & 0x3FFFU); - if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC) - { - /* Decoded value of MDEC */ - m = i; - } - } - break; - } - - return m; -} - -/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ -static void pllFindSel(uint32_t M, bool bypassFBDIV2, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) -{ - /* bandwidth: compute selP from Multiplier */ - if (M < 60U) - { - *pSelP = (M >> 1U) + 1U; - } - else - { - *pSelP = PVALMAX - 1U; - } - - /* bandwidth: compute selI from Multiplier */ - if (M > 16384U) - { - *pSelI = 1U; - } - else if (M > 8192U) - { - *pSelI = 2U; - } - else if (M > 2048U) - { - *pSelI = 4U; - } - else if (M >= 501U) - { - *pSelI = 8U; - } - else if (M >= 60U) - { - *pSelI = 4U * (1024U / (M + 9U)); - } - else - { - *pSelI = (M & 0x3CU) + 4U; - } - - if (*pSelI > ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT)) - { - *pSelI = ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT); - } - - *pSelR = 0U; -} - -/* Get predivider (N) from PLL NDEC setting */ -static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg) -{ - uint32_t preDiv = 1; - - /* Direct input is not used? */ - if ((ctrlReg & (1UL << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) == 0U) - { - /* Decode NDEC value to get (N) pre divider */ - preDiv = pllDecodeN(nDecReg & 0x3FFU); - if (preDiv == 0U) - { - preDiv = 1U; - } - } - - /* Adjusted by 1, directi is used to bypass */ - return preDiv; -} - -/* Get postdivider (P) from PLL PDEC setting */ -static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg) -{ - uint32_t postDiv = 1U; - - /* Direct input is not used? */ - if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0U) - { - /* Decode PDEC value to get (P) post divider */ - postDiv = 2U * pllDecodeP(pDecReg & 0x7FU); - if (postDiv == 0U) - { - postDiv = 2U; - } - } - - /* Adjusted by 1, directo is used to bypass */ - return postDiv; -} - -/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ -static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg) -{ - uint32_t mMult = 1U; - - /* Decode MDEC value to get (M) multiplier */ - mMult = pllDecodeM(mDecReg & 0x1FFFFU); - - /* Extra multiply by 2 needed? */ - if ((ctrlReg & (SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK)) == 0U) - { - mMult = mMult << 1U; - } - - if (mMult == 0U) - { - mMult = 1U; - } - - return mMult; -} - -static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) -{ - uint32_t tmp; - - while (n != 0U) - { - tmp = n; - n = m % n; - m = tmp; - } - - return m; -} - -/* - * Set PLL output based on desired output rate. - * In this function, the it calculates the PLL setting for output frequency from input clock - * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. - * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. - */ -static pll_error_t CLOCK_GetPllConfigInternal( - uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useFeedbackDiv2, bool useSS) -{ - uint32_t nDivOutHz, fccoHz, multFccoDiv; - uint32_t pllPreDivider, pllMultiplier, pllBypassFBDIV2, pllPostDivider; - uint32_t pllDirectInput, pllDirectOutput; - uint32_t pllSelP, pllSelI, pllSelR, bandsel, uplimoff; - - /* Baseline parameters (no input or output dividers) */ - pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ - pllPostDivider = 0U; /* 0 implies post-divider will be disabled */ - pllDirectOutput = 1U; - if (useFeedbackDiv2) - { - /* Using feedback divider for M, so disable bypass */ - pllBypassFBDIV2 = 0U; - } - else - { - pllBypassFBDIV2 = 1U; - } - multFccoDiv = (2U - pllBypassFBDIV2); - - /* Verify output rate parameter */ - if (foutHz > PLL_MAX_CCO_FREQ_MHZ) - { - /* Maximum PLL output with post divider=1 cannot go above this frequency */ - return kStatus_PLL_OutputTooHigh; - } - if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) - { - /* Minmum PLL output with maximum post divider cannot go below this frequency */ - return kStatus_PLL_OutputTooLow; - } - - /* If using SS mode, input clock needs to be between 2MHz and 4MHz */ - if (useSS) - { - /* Verify input rate parameter */ - if (finHz < PLL_MIN_IN_SSMODE) - { - /* Input clock into the PLL cannot be lower than this */ - return kStatus_PLL_InputTooLow; - } - /* PLL input in SS mode must be under 4MHz */ - pllPreDivider = finHz / ((PLL_MIN_IN_SSMODE + PLL_MAX_IN_SSMODE) / 2); - if (pllPreDivider > NVALMAX) - { - return kStatus_PLL_InputTooHigh; - } - } - else - { - /* Verify input rate parameter */ - if (finHz < PLL_LOWER_IN_LIMIT) - { - /* Input clock into the PLL cannot be lower than this */ - return kStatus_PLL_InputTooLow; - } - } - - /* Find the optimal CCO frequency for the output and input that - will keep it inside the PLL CCO range. This may require - tweaking the post-divider for the PLL. */ - fccoHz = foutHz; - while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) - { - /* CCO output is less than minimum CCO range, so the CCO output - needs to be bumped up and the post-divider is used to bring - the PLL output back down. */ - pllPostDivider++; - if (pllPostDivider > PVALMAX) - { - return kStatus_PLL_OutsideIntLimit; - } - - /* Target CCO goes up, PLL output goes down */ - fccoHz = foutHz * (pllPostDivider * 2U); - pllDirectOutput = 0U; - } - - /* Determine if a pre-divider is needed to get the best frequency */ - if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) - { - uint32_t a = FindGreatestCommonDivisor(fccoHz, (multFccoDiv * finHz)); - - if (a > 20000U) - { - a = (multFccoDiv * finHz) / a; - if ((a != 0U) && (a < PLL_MAX_N_DIV)) - { - pllPreDivider = a; - } - } - } - - /* Bypass pre-divider hardware if pre-divider is 1 */ - if (pllPreDivider > 1U) - { - pllDirectInput = 0U; - } - else - { - pllDirectInput = 1U; - } - - /* Determine PLL multipler */ - nDivOutHz = (finHz / pllPreDivider); - pllMultiplier = (fccoHz / nDivOutHz) / multFccoDiv; - - /* Find optimal values for filter */ - if (useSS == false) - { - /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ - if ((nDivOutHz * ((multFccoDiv * pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) - { - pllMultiplier++; - } - - /* Setup filtering */ - pllFindSel(pllMultiplier, pllBypassFBDIV2, &pllSelP, &pllSelI, &pllSelR); - bandsel = 1U; - uplimoff = 0U; - - /* Get encoded value for M (mult) and use manual filter, disable SS mode */ - pSetup->syspllssctrl[0] = - (PLL_SSCG0_MDEC_VAL_SET(pllEncodeM(pllMultiplier)) | (1U << SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT)); - - /* Power down SSC, not used */ - pSetup->syspllssctrl[1] = (1U << SYSCON_SYSPLLSSCTRL1_PD_SHIFT); - } - else - { - uint64_t fc; - - /* Filtering will be handled by SSC */ - pllSelR = pllSelI = pllSelP = 0U; - bandsel = 0U; - uplimoff = 1U; - - /* The PLL multiplier will get very close and slightly under the - desired target frequency. A small fractional component can be - added to fine tune the frequency upwards to the target. */ - fc = ((uint64_t)(fccoHz % (multFccoDiv * nDivOutHz)) << 11U) / (multFccoDiv * nDivOutHz); - - /* MDEC set by SSC */ - pSetup->syspllssctrl[0U] = 0U; - - /* Set multiplier */ - pSetup->syspllssctrl[1] = PLL_SSCG1_MD_INT_SET(pllMultiplier) | PLL_SSCG1_MD_FRACT_SET((uint32_t)fc); - } - - /* Get encoded values for N (prediv) and P (postdiv) */ - pSetup->syspllndec = PLL_NDEC_VAL_SET(pllEncodeN(pllPreDivider)); - pSetup->syspllpdec = PLL_PDEC_VAL_SET(pllEncodeP(pllPostDivider)); - - /* PLL control */ - pSetup->syspllctrl = (pllSelR << SYSCON_SYSPLLCTRL_SELR_SHIFT) | /* Filter coefficient */ - (pllSelI << SYSCON_SYSPLLCTRL_SELI_SHIFT) | /* Filter coefficient */ - (pllSelP << SYSCON_SYSPLLCTRL_SELP_SHIFT) | /* Filter coefficient */ - (0 << SYSCON_SYSPLLCTRL_BYPASS_SHIFT) | /* PLL bypass mode disabled */ - (pllBypassFBDIV2 << SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT) | /* Extra M / 2 divider? */ - (uplimoff << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT) | /* SS/fractional mode disabled */ - (bandsel << SYSCON_SYSPLLCTRL_BANDSEL_SHIFT) | /* Manual bandwidth selection enabled */ - (pllDirectInput << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT) | /* Bypass pre-divider? */ - (pllDirectOutput << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT); /* Bypass post-divider? */ - - return kStatus_PLL_Success; -} - -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) -/* Alloct the static buffer for cache. */ -static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; -static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; -static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; -static bool s_UseFeedbackDiv2Cache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; -static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; -static uint32_t s_PllSetupCacheIdx = 0U; -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - -/* - * Calculate the PLL setting values from input clock freq to output freq. - */ -static pll_error_t CLOCK_GetPllConfig( - uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useFeedbackDiv2, bool useSS) -{ - pll_error_t retErr; -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - uint32_t i; - - for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) - { - if ( (finHz == s_FinHzCache[i]) - && (foutHz == s_FoutHzCache[i]) - && (useFeedbackDiv2 == s_UseFeedbackDiv2Cache[i]) - && (useSS == s_UseSSCache[i]) ) - { - /* Hit the target in cache buffer. */ - pSetup->syspllctrl = s_PllSetupCacheStruct[i].syspllctrl; - pSetup->syspllndec = s_PllSetupCacheStruct[i].syspllndec; - pSetup->syspllpdec = s_PllSetupCacheStruct[i].syspllpdec; - pSetup->syspllssctrl[0] = s_PllSetupCacheStruct[i].syspllssctrl[0]; - pSetup->syspllssctrl[1] = s_PllSetupCacheStruct[i].syspllssctrl[1]; - retErr = kStatus_PLL_Success; - break; - } - } - - if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - { - return retErr; - } -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - - retErr = CLOCK_GetPllConfigInternal( finHz, foutHz, pSetup, useFeedbackDiv2, useSS); - -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - /* Cache the most recent calulation result into buffer. */ - s_FinHzCache[s_PllSetupCacheIdx] = finHz; - s_FoutHzCache[s_PllSetupCacheIdx] = foutHz; - s_UseFeedbackDiv2Cache[s_PllSetupCacheIdx] = useFeedbackDiv2; - s_UseSSCache[s_PllSetupCacheIdx] = useSS; - - s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllctrl = pSetup->syspllctrl; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllndec = pSetup->syspllndec; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllpdec = pSetup->syspllpdec; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllssctrl[0] = pSetup->syspllssctrl[0]; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllssctrl[1] = pSetup->syspllssctrl[1]; - /* Update the index for next available buffer. */ - s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - - return retErr; -} - -/* Update local PLL rate variable */ -static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup) -{ - s_Pll_Freq = CLOCK_GetSystemPLLOutFromSetup(pSetup); -} - -/* Return System PLL input clock rate */ -uint32_t CLOCK_GetSystemPLLInClockRate(void) -{ - uint32_t clkRate = 0U; - - switch ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)) - { - case 0x00U: - clkRate = CLK_FRO_12MHZ; - break; - - case 0x01U: - clkRate = CLOCK_GetExtClkFreq(); - break; - - case 0x02U: - clkRate = CLOCK_GetWdtOscFreq(); - break; - - case 0x03U: - clkRate = CLOCK_GetOsc32KFreq(); - break; - - default: - clkRate = 0U; - break; - } - - return clkRate; -} - -/* Return System PLL output clock rate from setup structure */ -uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup) -{ - uint32_t prediv, postdiv, mMult, inPllRate; - uint64_t workRate; - - /* Get the input clock frequency of PLL. */ - inPllRate = CLOCK_GetSystemPLLInClockRate(); - - /* - * If the PLL is bypassed, PLL would not be used and the output of PLL module would just be the input clock. - */ - if ((pSetup->syspllctrl & (SYSCON_SYSPLLCTRL_BYPASS_MASK)) == 0U) - { - /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */ - /* - * 1. Pre-divider - * Pre-divider is only available when the DIRECTI is disabled. - */ - if (0U == (pSetup->syspllctrl & SYSCON_SYSPLLCTRL_DIRECTI_MASK)) - { - prediv = findPllPreDiv(pSetup->syspllctrl, pSetup->syspllndec); - } - else - { - prediv = 1U; /* The pre-divider is bypassed. */ - } - /* Adjust input clock */ - inPllRate = inPllRate / prediv; - - /* - * 2. M divider - * If using the SS, use the multiplier. - */ - if (pSetup->syspllssctrl[1] & (SYSCON_SYSPLLSSCTRL1_PD_MASK)) - { - /* MDEC used for rate */ - mMult = findPllMMult(pSetup->syspllctrl, pSetup->syspllssctrl[0]); - workRate = (uint64_t)inPllRate * (uint64_t)mMult; - } - else - { - uint64_t fract; - - /* SS multipler used for rate */ - mMult = (pSetup->syspllssctrl[1] & PLL_SSCG1_MD_INT_M) >> PLL_SSCG1_MD_INT_P; - workRate = (uint64_t)inPllRate * (uint64_t)mMult; - - /* Adjust by fractional */ - fract = (uint64_t)(pSetup->syspllssctrl[1] & PLL_SSCG1_MD_FRACT_M) >> PLL_SSCG1_MD_FRACT_P; - workRate = workRate + ((inPllRate * fract) / 0x800U); - } - - /* - * 3. Post-divider - * Post-divider is only available when the DIRECTO is disabled. - */ - if (0U == (pSetup->syspllctrl & SYSCON_SYSPLLCTRL_DIRECTO_MASK)) - { - postdiv = findPllPostDiv(pSetup->syspllctrl, pSetup->syspllpdec); - } - else - { - postdiv = 1U; /* The post-divider is bypassed. */ - } - workRate = workRate / ((uint64_t)postdiv); - } - else - { - /* In bypass mode */ - workRate = (uint64_t)inPllRate; - } - - return (uint32_t)workRate; -} - -/* Set the current PLL Rate */ -void CLOCK_SetStoredPLLClockRate(uint32_t rate) -{ - s_Pll_Freq = rate; -} - -/* Return System PLL output clock rate */ -uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute) -{ - pll_setup_t Setup; - uint32_t rate; - - if ((recompute) || (s_Pll_Freq == 0U)) - { - Setup.syspllctrl = SYSCON->SYSPLLCTRL; - Setup.syspllndec = SYSCON->SYSPLLNDEC; - Setup.syspllpdec = SYSCON->SYSPLLPDEC; - Setup.syspllssctrl[0] = SYSCON->SYSPLLSSCTRL0; - Setup.syspllssctrl[1] = SYSCON->SYSPLLSSCTRL1; - - CLOCK_GetSystemPLLOutFromSetupUpdate(&Setup); - } - - rate = s_Pll_Freq; - - return rate; -} - -/* Set PLL output based on the passed PLL setup data */ -pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup) -{ - uint32_t inRate; - bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0U); - bool useFbDiv2; - - pll_error_t pllError; - - /* Determine input rate for the PLL */ - if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U) - { - inRate = pControl->inputRate; - } - else - { - inRate = CLOCK_GetSystemPLLInClockRate(); - } - - if ((pSetup->flags & PLL_SETUPFLAG_USEFEEDBACKDIV2) != 0U) - { - useFbDiv2 = true; - } - else - { - useFbDiv2 = false; - } - - /* PLL flag options */ - pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup, useFbDiv2, useSS); - if ((useSS) && (pllError == kStatus_PLL_Success)) - { - /* If using SS mode, then some tweaks are made to the generated setup */ - pSetup->syspllssctrl[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc; - if (pControl->mfDither) - { - pSetup->syspllssctrl[1] |= (1U << SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT); - } - } - - return pllError; -} - -/* Set PLL output from PLL setup structure */ -pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg) -{ - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0); - - pSetup->flags = flagcfg; - - /* Write PLL setup data */ - SYSCON->SYSPLLCTRL = pSetup->syspllctrl; - SYSCON->SYSPLLNDEC = pSetup->syspllndec; - SYSCON->SYSPLLNDEC = pSetup->syspllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */ - SYSCON->SYSPLLPDEC = pSetup->syspllpdec; - SYSCON->SYSPLLPDEC = pSetup->syspllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */ - SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0]; - SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0] | (1U << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT); /* latch */ - SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1]; - SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1] | (1U << SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT); /* latch */ - - /* Flags for lock or power on */ - if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U) - { - /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ - volatile uint32_t delayX; - uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ - uint32_t curSSCTRL = SYSCON->SYSPLLSSCTRL0 & ~(1U << 17U); - - /* Initialize and power up PLL */ - SYSCON->SYSPLLSSCTRL0 = maxCCO; - POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); - - /* Set mreq to activate */ - SYSCON->SYSPLLSSCTRL0 = maxCCO | (1U << 17U); - - /* Delay for 72 uSec @ 12Mhz */ - for (delayX = 0U; delayX < 172U; ++delayX) - { - } - - /* clear mreq to prepare for restoring mreq */ - SYSCON->SYSPLLSSCTRL0 = curSSCTRL; - - /* set original value back and activate */ - SYSCON->SYSPLLSSCTRL0 = curSSCTRL | (1U << 17U); - - /* Enable peripheral states by setting low */ - POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); - } - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) - { - while (CLOCK_IsSystemPLLLocked() == false) - { - } - } - - /* Update current programmed PLL rate var */ - CLOCK_GetSystemPLLOutFromSetupUpdate(pSetup); - - /* System voltage adjustment, occurs prior to setting main system clock */ - if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U) - { - POWER_SetVoltageForFreq(s_Pll_Freq); - } - - return kStatus_PLL_Success; -} - -/* Setup PLL Frequency from pre-calculated value */ -pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup) -{ - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0); - - /* Write PLL setup data */ - SYSCON->SYSPLLCTRL = pSetup->syspllctrl; - SYSCON->SYSPLLNDEC = pSetup->syspllndec; - SYSCON->SYSPLLNDEC = pSetup->syspllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */ - SYSCON->SYSPLLPDEC = pSetup->syspllpdec; - SYSCON->SYSPLLPDEC = pSetup->syspllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */ - SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0]; - SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0] | (1U << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT); /* latch */ - SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1]; - SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1] | (1U << SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT); /* latch */ - - /* Flags for lock or power on */ - if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0) - { - /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ - volatile uint32_t delayX; - uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ - uint32_t curSSCTRL = SYSCON->SYSPLLSSCTRL0 & ~(1U << 17U); - - /* Initialize and power up PLL */ - SYSCON->SYSPLLSSCTRL0 = maxCCO; - POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); - - /* Set mreq to activate */ - SYSCON->SYSPLLSSCTRL0 = maxCCO | (1U << 17U); - - /* Delay for 72 uSec @ 12Mhz */ - for (delayX = 0U; delayX < 172U; ++delayX) - { - } - - /* clear mreq to prepare for restoring mreq */ - SYSCON->SYSPLLSSCTRL0 = curSSCTRL; - - /* set original value back and activate */ - SYSCON->SYSPLLSSCTRL0 = curSSCTRL | (1U << 17U); - - /* Enable peripheral states by setting low */ - POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); - } - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) - { - while (CLOCK_IsSystemPLLLocked() == false) - { - } - } - - /* Update current programmed PLL rate var */ - s_Pll_Freq = pSetup->pllRate; - - return kStatus_PLL_Success; -} - -/* Set System PLL clock based on the input frequency and multiplier */ -void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq) -{ - uint32_t cco_freq = input_freq * multiply_by; - uint32_t pdec = 1U; - uint32_t selr; - uint32_t seli; - uint32_t selp; - uint32_t mdec, ndec; - - uint32_t directo = SYSCON_SYSPLLCTRL_DIRECTO(1); - - while (cco_freq < 75000000U) - { - multiply_by <<= 1U; /* double value in each iteration */ - pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */ - cco_freq = input_freq * multiply_by; - } - selr = 0U; - if (multiply_by < 60U) - { - seli = (multiply_by & 0x3cU) + 4U; - selp = (multiply_by >> 1U) + 1U; - } - else - { - selp = 31U; - if (multiply_by > 16384U) - { - seli = 1U; - } - else if (multiply_by > 8192U) - { - seli = 2U; - } - else if (multiply_by > 2048U) - { - seli = 4U; - } - else if (multiply_by >= 501U) - { - seli = 8U; - } - else - { - seli = 4U * (1024U / (multiply_by + 9U)); - } - } - - if (pdec > 1U) - { - directo = 0U; /* use post divider */ - pdec = pdec / 2U; /* Account for minus 1 encoding */ - /* Translate P value */ - switch (pdec) - { - case 1U: - pdec = 0x62U; /* 1 * 2 */ - break; - case 2U: - pdec = 0x42U; /* 2 * 2 */ - break; - case 4U: - pdec = 0x02U; /* 4 * 2 */ - break; - case 8U: - pdec = 0x0bU; /* 8 * 2 */ - break; - case 16U: - pdec = 0x11U; /* 16 * 2 */ - break; - case 32U: - pdec = 0x08U; /* 32 * 2 */ - break; - default: - pdec = 0x08U; - break; - } - } - - mdec = PLL_SSCG0_MDEC_VAL_SET(pllEncodeM(multiply_by)); - ndec = 0x302U; /* pre divide by 1 (hardcoded) */ - - SYSCON->SYSPLLCTRL = SYSCON_SYSPLLCTRL_BANDSEL(1) | directo | SYSCON_SYSPLLCTRL_BYPASSCCODIV2(1) | - (selr << SYSCON_SYSPLLCTRL_SELR_SHIFT) | (seli << SYSCON_SYSPLLCTRL_SELI_SHIFT) | - (selp << SYSCON_SYSPLLCTRL_SELP_SHIFT); - SYSCON->SYSPLLPDEC = pdec | (1U << 7U); /* set Pdec value and assert preq */ - SYSCON->SYSPLLNDEC = ndec | (1U << 10U); /* set Pdec value and assert preq */ - SYSCON->SYSPLLSSCTRL0 = - (1U << 18U) | (1U << 17U) | mdec; /* select non sscg MDEC value, assert mreq and select mdec value */ -} -bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq) -{ - bool ret = true; - - CLOCK_DisableClock(kCLOCK_Usbd0); - - if (kCLOCK_UsbSrcFro == src) - { - switch (freq) - { - case 96000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsbClk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ - break; - case 48000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsbClk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ - break; - default: - ret = false; - break; - } - /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */ - SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK | - SYSCON_FROCTRL_USBCLKADJ_MASK; - /* select FRO 96 or 48 MHz */ - CLOCK_AttachClk(kFRO_HF_to_USB_CLK); - } - else - { - /*TODO , we only implement FRO as usb clock source*/ - ret = false; - } - - CLOCK_EnableClock(kCLOCK_Usbd0); - - return ret; -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_clock.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_clock.h deleted file mode 100644 index d63fd892e68..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_clock.h +++ /dev/null @@ -1,896 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016 - 2017 , NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name ofcopyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_CLOCK_H_ -#define _FSL_CLOCK_H_ - -#include "fsl_device_registers.h" -#include -#include -#include - -/*! @addtogroup clock */ -/*! @{ */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CLOCK driver version 2.0.2. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -/*! - * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. - * - * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function - * would cache the recent calulation and accelerate the execution to get the - * right settings. - */ -#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT -#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U -#endif - -/*! @brief Clock ip name array for FLEXCOMM. */ -#define FLEXCOMM_CLOCKS \ - { \ - kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \ - kCLOCK_FlexComm6, kCLOCK_FlexComm7 \ - } -/*! @brief Clock ip name array for LPUART. */ -#define LPUART_CLOCKS \ - { \ - kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \ - kCLOCK_MinUart6, kCLOCK_MinUart7 \ - } - -/*! @brief Clock ip name array for BI2C. */ -#define BI2C_CLOCKS \ - { \ - kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \ - } -/*! @brief Clock ip name array for LSPI. */ -#define LPSI_CLOCKS \ - { \ - kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \ - } -/*! @brief Clock ip name array for FLEXI2S. */ -#define FLEXI2S_CLOCKS \ - { \ - kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \ - kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \ - } -/*! @brief Clock ip name array for UTICK. */ -#define UTICK_CLOCKS \ - { \ - kCLOCK_Utick \ - } -/*! @brief Clock ip name array for DMIC. */ -#define DMIC_CLOCKS \ - { \ - kCLOCK_DMic \ - } -/*! @brief Clock ip name array for DMA. */ -#define DMA_CLOCKS \ - { \ - kCLOCK_Dma \ - } -/*! @brief Clock ip name array for CT32B. */ -#define CTIMER_CLOCKS \ - { \ - kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \ - } - -/*! @brief Clock ip name array for GPIO. */ -#define GPIO_CLOCKS \ - { \ - kCLOCK_Gpio0, kCLOCK_Gpio1 \ - } -/*! @brief Clock ip name array for ADC. */ -#define ADC_CLOCKS \ - { \ - kCLOCK_Adc0 \ - } -/*! @brief Clock ip name array for MRT. */ -#define MRT_CLOCKS \ - { \ - kCLOCK_Mrt \ - } -/*! @brief Clock ip name array for MRT. */ -#define SCT_CLOCKS \ - { \ - kCLOCK_Sct0 \ - } -/*! @brief Clock ip name array for RTC. */ -#define RTC_CLOCKS \ - { \ - kCLOCK_Rtc \ - } -/*! @brief Clock ip name array for WWDT. */ -#define WWDT_CLOCKS \ - { \ - kCLOCK_Wwdt \ - } -/*! @brief Clock ip name array for CRC. */ -#define CRC_CLOCKS \ - { \ - kCLOCK_Crc \ - } -/*! @brief Clock ip name array for USBD. */ -#define USBD_CLOCKS \ - { \ - kCLOCK_Usbd0 \ - } - -/*! @brief Clock ip name array for GINT. GINT0 & GINT1 share same slot */ -#define GINT_CLOCKS \ - { \ - kCLOCK_Gint, kCLOCK_Gint \ - } - -/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ -/*------------------------------------------------------------------------------ - clock_ip_name_t definition: -------------------------------------------------------------------------------*/ - -#define CLK_GATE_REG_OFFSET_SHIFT 8U -#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U -#define CLK_GATE_BIT_SHIFT_SHIFT 0U -#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU - -#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ - ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ - (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) - -#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) -#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) - -#define AHB_CLK_CTRL0 0 -#define AHB_CLK_CTRL1 1 -#define ASYNC_CLK_CTRL0 2 - -/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ -typedef enum _clock_ip_name -{ - kCLOCK_IpInvalid = 0U, - kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), - kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), - kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), - kCLOCK_Regfile = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), - kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), - kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), - kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), - kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), - kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), - kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), - kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), - kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), - kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), - kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /* GPIO_GLOBALINT0 and GPIO_GLOBALINT1 share the same slot */ - kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), - kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), - kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), - kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), - kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), - kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), - kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), - kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), - kCLOCK_SctIpu0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 6), - kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), - kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19), - kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), - kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), - kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), - kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), - kCLOCK_Pvtvf0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28), - kCLOCK_Pvtvf1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28), - kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29), - kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), - - kCLOCK_Ct32b3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13), - kCLOCK_Ct32b4 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14) -} clock_ip_name_t; - -/*! @brief Clock name used to get clock frequency. */ -typedef enum _clock_name -{ - kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ - kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ - kCLOCK_FroHf, /*!< FRO48/96 */ - kCLOCK_Fro12M, /*!< FRO12M */ - kCLOCK_ExtClk, /*!< External Clock */ - kCLOCK_PllOut, /*!< PLL Output */ - kCLOCK_UsbClk, /*!< USB input */ - kCLOCK_WdtOsc, /*!< Watchdog Oscillator */ - kCLOCK_Frg, /*!< Frg Clock */ - kCLOCK_Dmic, /*!< Digital Mic clock */ - kCLOCK_AsyncApbClk, /*!< Async APB clock */ - kCLOCK_FlexI2S, /*!< FlexI2S clock */ - kCLOCK_Flexcomm0, /*!< Flexcomm0Clock */ - kCLOCK_Flexcomm1, /*!< Flexcomm1Clock */ - kCLOCK_Flexcomm2, /*!< Flexcomm2Clock */ - kCLOCK_Flexcomm3, /*!< Flexcomm3Clock */ - kCLOCK_Flexcomm4, /*!< Flexcomm4Clock */ - kCLOCK_Flexcomm5, /*!< Flexcomm5Clock */ - kCLOCK_Flexcomm6, /*!< Flexcomm6Clock */ - kCLOCK_Flexcomm7, /*!< Flexcomm7Clock */ -} clock_name_t; - -/** - * Clock source selections for the asynchronous APB clock - */ -typedef enum _async_clock_src -{ - kCLOCK_AsyncMainClk = 0, /*!< Main System clock */ - kCLOCK_AsyncFro12Mhz, /*!< 12MHz FRO */ -} async_clock_src_t; - -/*! @brief Clock Mux Switches -* The encoding is as follows each connection identified is 64bits wide -* starting from LSB upwards -* -* [4 bits for choice, where 1 is A, 2 is B, 3 is C and 4 is D, 0 means end of descriptor] [8 bits mux ID]* -* -*/ - -#define MUX_A(m, choice) (((m) << 0) | (((choice) + 1) << 8)) -#define MUX_B(m, choice) (((m) << 12) | (((choice) + 1) << 20)) -#define MUX_C(m, choice) (((m) << 24) | (((choice) + 1) << 32)) -#define MUX_D(m, choice) (((m) << 36) | (((choice) + 1) << 44)) -#define MUX_E(m, choice) (((m) << 48) | (((choice) + 1) << 56)) - -#define CM_MAINCLKSELA 0 -#define CM_MAINCLKSELB 1 -#define CM_CLKOUTCLKSELA 2 -#define CM_CLKOUTCLKSELB 3 -#define CM_SYSPLLCLKSEL 4 -#define CM_USBPLLCLKSEL 5 -#define CM_AUDPLLCLKSEL 6 -#define CM_SCTPLLCLKSEL 7 -#define CM_SPIFICLKSEL 8 -#define CM_ADCASYNCCLKSEL 9 -#define CM_USBCLKSEL 10 -#define CM_USB1CLKSEL 11 -#define CM_FXCOMCLKSEL0 12 -#define CM_FXCOMCLKSEL1 13 -#define CM_FXCOMCLKSEL2 14 -#define CM_FXCOMCLKSEL3 15 -#define CM_FXCOMCLKSEL4 16 -#define CM_FXCOMCLKSEL5 17 -#define CM_FXCOMCLKSEL6 18 -#define CM_FXCOMCLKSEL7 19 -#define CM_FXCOMCLKSEL8 20 -#define CM_FXCOMCLKSEL9 21 -#define CM_FXCOMCLKSEL10 22 -#define CM_FXCOMCLKSEL11 23 -#define CM_FXI2S0MCLKCLKSEL 24 -#define CM_FXI2S1MCLKCLKSEL 25 -#define CM_FRGCLKSEL 26 -#define CM_DMICCLKSEL 27 - -#define CM_ASYNCAPB 28 - -typedef enum _clock_attach_id -{ - - kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0), - kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0), - kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0), - kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0), - kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 2), - kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 3), - - kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0), - kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1), - kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2), - kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3), - kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7), - - kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0), - kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1), - - kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), - kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), - kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), - kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), - - kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0), - kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1), - kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3), - kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7), - - kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), - kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), - kSYS_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), - kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), - kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), - kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), - - kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), - kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), - kSYS_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), - kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), - kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), - kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), - - kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), - kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), - kSYS_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), - kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), - kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), - kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), - - kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), - kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), - kSYS_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), - kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), - kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), - kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), - - kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), - kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), - kSYS_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), - kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), - kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), - kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), - - kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), - kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), - kSYS_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), - kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), - kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), - kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), - - kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), - kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), - kSYS_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), - kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), - kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), - kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), - - kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), - kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), - kSYS_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), - kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), - kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), - kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), - - kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0), - kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1), - kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2), - kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3), - kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7), - - kFRO_HF_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 0), - kSYS_PLL_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 1), - kNONE_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 7), - - kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0), - kFRO_HF_to_DMIC = MUX_A(CM_DMICCLKSEL, 1), - kSYS_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2), - kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3), - kMAIN_CLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 4), - kWDT_CLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 5), - kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7), - - kFRO_HF_to_USB_CLK = MUX_A(CM_USBCLKSEL, 0), - kSYS_PLL_to_USB_CLK = MUX_A(CM_USBCLKSEL, 1), - kMAIN_CLK_to_USB_CLK = MUX_A(CM_USBCLKSEL, 2), - kNONE_to_USB_CLK = MUX_A(CM_USBCLKSEL, 7), - - kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0), - kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1), - kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2), - kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3), - kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4), - kFRO12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5), - kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6), - kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7), - kNONE_to_NONE = 0x80000000U, -} clock_attach_id_t; - -/* Clock dividers */ -typedef enum _clock_div_name -{ - kCLOCK_DivSystickClk = 0, - kCLOCK_DivTraceClk = 1, - kCLOCK_DivAhbClk = 32, - kCLOCK_DivClkOut = 33, - kCLOCK_DivSpifiClk = 36, - kCLOCK_DivAdcAsyncClk = 37, - kCLOCK_DivUsbClk = 38, - kCLOCK_DivFrg = 40, - kCLOCK_DivDmicClk = 42, - kCLOCK_DivFxI2s0MClk = 43 -} clock_div_name_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -static inline void CLOCK_EnableClock(clock_ip_name_t clk) -{ - uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - if (index < 2) - { - SYSCON->AHBCLKCTRLSET[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); - } - else - { - ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); - } -} - -static inline void CLOCK_DisableClock(clock_ip_name_t clk) -{ - uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - if (index < 2) - { - SYSCON->AHBCLKCTRLCLR[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); - } - else - { - ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); - } -} -/** - * @brief FLASH Access time definitions - */ -typedef enum _clock_flashtim -{ - kCLOCK_Flash1Cycle = 0, /*!< Flash accesses use 1 CPU clock */ - kCLOCK_Flash2Cycle, /*!< Flash accesses use 2 CPU clocks */ - kCLOCK_Flash3Cycle, /*!< Flash accesses use 3 CPU clocks */ - kCLOCK_Flash4Cycle, /*!< Flash accesses use 4 CPU clocks */ - kCLOCK_Flash5Cycle, /*!< Flash accesses use 5 CPU clocks */ - kCLOCK_Flash6Cycle, /*!< Flash accesses use 6 CPU clocks */ - kCLOCK_Flash7Cycle, /*!< Flash accesses use 7 CPU clocks */ - kCLOCK_Flash8Cycle /*!< Flash accesses use 8 CPU clocks */ -} clock_flashtim_t; - -/** - * @brief Set FLASH memory access time in clocks - * @param clks : Clock cycles for FLASH access - * @return Nothing - */ -static inline void CLOCK_SetFLASHAccessCycles(clock_flashtim_t clks) -{ - uint32_t tmp; - - tmp = SYSCON->FLASHCFG & ~(SYSCON_FLASHCFG_FLASHTIM_MASK); - - /* Don't alter lower bits */ - SYSCON->FLASHCFG = tmp | ((uint32_t)clks << SYSCON_FLASHCFG_FLASHTIM_SHIFT); -} - -/** - * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). - * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is - * enabled. - * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ) - * @return returns success or fail status. - */ -status_t CLOCK_SetupFROClocking(uint32_t iFreq); -/** - * @brief Configure the clock selection muxes. - * @param connection : Clock to be configured. - * @return Nothing - */ -void CLOCK_AttachClk(clock_attach_id_t connection); -/** - * @brief Setup peripheral clock dividers. - * @param div_name : Clock divider name - * @param divided_by_value: Value to be divided - * @param reset : Whether to reset the divider counter. - * @return Nothing - */ -void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset); -/** - * @brief Set the flash wait states for the input freuqency. - * @param iFreq : Input frequency - * @return Nothing - */ -void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq); -/*! @brief Return Frequency of selected clock - * @return Frequency of selected clock - */ -uint32_t CLOCK_GetFreq(clock_name_t clockName); - -/*! @brief Return Input frequency for the Fractional baud rate generator - * @return Input Frequency for FRG - */ -uint32_t CLOCK_GetFRGInputClock(void); - -/*! @brief Return Input frequency for the DMIC - * @return Input Frequency for DMIC - */ -uint32_t CLOCK_GetDmicClkFreq(void); - -/*! @brief Return Input frequency for the FRG - * @return Input Frequency for FRG - */ -uint32_t CLOCK_GetFrgClkFreq(void); - -/*! @brief Set output of the Fractional baud rate generator - * @param freq : Desired output frequency - * @return Error Code 0 - fail 1 - success - */ -uint32_t CLOCK_SetFRGClock(uint32_t freq); - -/*! @brief Return Frequency of FRO 12MHz - * @return Frequency of FRO 12MHz - */ -uint32_t CLOCK_GetFro12MFreq(void); -/*! @brief Return Frequency of External Clock - * @return Frequency of External Clock. If no external clock is used returns 0. - */ -uint32_t CLOCK_GetExtClkFreq(void); -/*! @brief Return Frequency of Watchdog Oscillator - * @return Frequency of Watchdog Oscillator - */ -uint32_t CLOCK_GetWdtOscFreq(void); -/*! @brief Return Frequency of High-Freq output of FRO - * @return Frequency of High-Freq output of FRO - */ -uint32_t CLOCK_GetFroHfFreq(void); -/*! @brief Return Frequency of USB - * @return Frequency of USB - */ -uint32_t CLOCK_GetUsbClkFreq(void); -/*! @brief Return Frequency of PLL - * @return Frequency of PLL - */ -uint32_t CLOCK_GetPllOutFreq(void); -/*! @brief Return Frequency of 32kHz osc - * @return Frequency of 32kHz osc - */ -uint32_t CLOCK_GetOsc32KFreq(void); -/*! @brief Return Frequency of Core System - * @return Frequency of Core System - */ -uint32_t CLOCK_GetCoreSysClkFreq(void); -/*! @brief Return Frequency of I2S MCLK Clock - * @return Frequency of I2S MCLK Clock - */ -uint32_t CLOCK_GetI2SMClkFreq(void); -/*! @brief Return Frequency of Flexcomm functional Clock - * @return Frequency of Flexcomm functional Clock - */ -uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id); -/*! @brief Return Asynchronous APB Clock source - * @return Asynchronous APB CLock source - */ -__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void) -{ - return (async_clock_src_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3); -} -/*! @brief Return Frequency of Asynchronous APB Clock - * @return Frequency of Asynchronous APB Clock Clock - */ -uint32_t CLOCK_GetAsyncApbClkFreq(void); -/*! @brief Return System PLL input clock rate - * @return System PLL input clock rate - */ -uint32_t CLOCK_GetSystemPLLInClockRate(void); - -/*! @brief Return System PLL output clock rate - * @param recompute : Forces a PLL rate recomputation if true - * @return System PLL output clock rate - * @note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute); - -/*! @brief Enables and disables PLL bypass mode - * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass - * @return System PLL output clock rate - */ -__STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass) -{ - if (bypass) - { - SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT); - } - else - { - SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT); - } -} - -/*! @brief Check if PLL is locked or not - * @return true if the PLL is locked, false if not locked - */ -__STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void) -{ - return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0); -} - -/*! @brief Store the current PLL rate - * @param rate: Current rate of the PLL - * @return Nothing - **/ -void CLOCK_SetStoredPLLClockRate(uint32_t rate); - -/*! @brief PLL configuration structure flags for 'flags' field - * These flags control how the PLL configuration function sets up the PLL setup structure.
- * - * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the - * configuration structure must be assigned with the expected PLL frequency. If the - * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration - * function and the driver will determine the PLL rate from the currently selected - * PLL source. This flag might be used to configure the PLL input clock more accurately - * when using the WDT oscillator or a more dyanmic CLKIN source.
- * - * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the - * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider - * are not used.
- */ -#define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */ -#define PLL_CONFIGFLAG_FORCENOFRACT \ - (1 << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS \ - \ \ \ - \ \ \ \ \ - \ \ \ \ \ \ \ - \ \ \ \ \ \ \ \ \ - hardware */ - -/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency - * See (MF) field in the SYSPLLSSCTRL1 register in the UM. - */ -typedef enum _ss_progmodfm -{ - kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */ - kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */ - kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */ - kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */ - kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */ - kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */ - kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */ - kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */ -} ss_progmodfm_t; - -/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth - * See (MR) field in the SYSPLLSSCTRL1 register in the UM. - */ -typedef enum _ss_progmoddp -{ - kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */ - kSS_MR_K1 = (1 << 23), /*!< k = 1 */ - kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */ - kSS_MR_K2 = (3 << 23), /*!< k = 2 */ - kSS_MR_K3 = (4 << 23), /*!< k = 3 */ - kSS_MR_K4 = (5 << 23), /*!< k = 4 */ - kSS_MR_K6 = (6 << 23), /*!< k = 6 */ - kSS_MR_K8 = (7 << 23) /*!< k = 8 */ -} ss_progmoddp_t; - -/*! @brief PLL Spread Spectrum (SS) Modulation waveform control - * See (MC) field in the SYSPLLSSCTRL1 register in the UM.
- * Compensation for low pass filtering of the PLL to get a triangular - * modulation at the output of the PLL, giving a flat frequency spectrum. - */ -typedef enum _ss_modwvctrl -{ - kSS_MC_NOC = (0 << 26), /*!< no compensation */ - kSS_MC_RECC = (2 << 26), /*!< recommended setting */ - kSS_MC_MAXC = (3 << 26), /*!< max. compensation */ -} ss_modwvctrl_t; - -/*! @brief PLL configuration structure - * - * This structure can be used to configure the settings for a PLL - * setup structure. Fill in the desired configuration for the PLL - * and call the PLL setup function to fill in a PLL setup structure. - */ -typedef struct _pll_config -{ - uint32_t desiredRate; /*!< Desired PLL rate in Hz */ - uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */ - uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ - ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - ss_modwvctrl_t - ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ - bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - -} pll_config_t; - -/*! @brief PLL setup structure flags for 'flags' field -* These flags control how the PLL setup function sets up the PLL -*/ -#define PLL_SETUPFLAG_POWERUP (1 << 0) /*!< Setup will power on the PLL after setup */ -#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ -#define PLL_SETUPFLAG_ADGVOLT (1 << 2) /*!< Optimize system voltage for the new PLL rate */ -#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1 << 3) /*!< Use feedback divider by 2 in divider path */ - -/*! @brief PLL setup structure -* This structure can be used to pre-build a PLL setup configuration -* at run-time and quickly set the PLL to the configuration. It can be -* populated with the PLL setup function. If powering up or waiting -* for PLL lock, the PLL input clock source should be configured prior -* to PLL setup. -*/ -typedef struct _pll_setup -{ - uint32_t syspllctrl; /*!< PLL control register SYSPLLCTRL */ - uint32_t syspllndec; /*!< PLL NDEC register SYSPLLNDEC */ - uint32_t syspllpdec; /*!< PLL PDEC register SYSPLLPDEC */ - uint32_t syspllssctrl[2]; /*!< PLL SSCTL registers SYSPLLSSCTRL */ - uint32_t pllRate; /*!< Acutal PLL rate */ - uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ -} pll_setup_t; - -/*! @brief PLL status definitions - */ -typedef enum _pll_error -{ - kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ - kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ - kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ - kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ - kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ - kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5) /*!< Requested output rate isn't possible */ -} pll_error_t; - -/*! @brief USB clock source definition. */ -typedef enum _clock_usb_src -{ - kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */ - kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */ - kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */ - kCLOCK_UsbSrcNone = SYSCON_USBCLKSEL_SEL( - 7) /*!< Use None, this may be selected in order to reduce power when no output is needed. */ -} clock_usb_src_t; - -/*! @brief Return System PLL output clock rate from setup structure - * @param pSetup : Pointer to a PLL setup structure - * @return System PLL output clock rate calculated from the setup structure - */ -uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup); - -/*! @brief Set PLL output based on the passed PLL setup data - * @param pControl : Pointer to populated PLL control structure to generate setup with - * @param pSetup : Pointer to PLL setup structure to be filled - * @return PLL_ERROR_SUCCESS on success, or PLL setup error code - * @note Actual frequency for setup may vary from the desired frequency based on the - * accuracy of input clocks, rounding, non-fractional PLL mode, etc. - */ -pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup); - -/*! @brief Set PLL output from PLL setup structure (precise frequency) - * @param pSetup : Pointer to populated PLL setup structure -* @param flagcfg : Flag configuration for PLL config structure - * @return PLL_ERROR_SUCCESS on success, or PLL setup error code - * @note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg); - -/** - * @brief Set PLL output from PLL setup structure (precise frequency) - * @param pSetup : Pointer to populated PLL setup structure - * @return kStatus_PLL_Success on success, or PLL setup error code - * @note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup); - -/*! @brief Set PLL output based on the multiplier and input frequency - * @param multiply_by : multiplier - * @param input_freq : Clock input frequency of the PLL - * @return Nothing - * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this - * function does not disable or enable PLL power, wait for PLL lock, - * or adjust system voltages. These must be done in the application. - * The function will not alter any source clocks (ie, main systen clock) - * that may use the PLL, so these should be setup prior to and after - * exiting the function. - */ -void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq); - -/*! @brief Disable USB FS clock. - * - * Disable USB FS clock. - */ -static inline void CLOCK_DisableUsbfs0Clock(void) -{ - CLOCK_DisableClock(kCLOCK_Usbd0); -} -bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq); -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @} */ - -#endif /* _FSL_CLOCK_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_common.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_common.c deleted file mode 100644 index 903faf52b63..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_common.c +++ /dev/null @@ -1,192 +0,0 @@ -/* -* The Clear BSD License -* Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016 NXP -* All rights reserved. -* -* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted (subject to the limitations in the disclaimer below) provided -* that the following conditions are met: -* -* o Redistributions of source code must retain the above copyright notice, this list -* of conditions and the following disclaimer. -* -* o Redistributions in binary form must reproduce the above copyright notice, this -* list of conditions and the following disclaimer in the documentation and/or -* other materials provided with the distribution. -* -* o Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "fsl_common.h" -#define SDK_MEM_MAGIC_NUMBER 12345U - -typedef struct _mem_align_control_block -{ - uint16_t identifier; /*!< Identifier for the memory control block. */ - uint16_t offset; /*!< offset from aligned adress to real address */ -} mem_align_cb_t; - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.common" -#endif - - -#ifndef __GIC_PRIO_BITS -#if defined(ENABLE_RAM_VECTOR_TABLE) -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) -{ -/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ -#if defined(__CC_ARM) - extern uint32_t Image$$VECTOR_ROM$$Base[]; - extern uint32_t Image$$VECTOR_RAM$$Base[]; - extern uint32_t Image$$RW_m_data$$Base[]; - -#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base -#define __VECTOR_RAM Image$$VECTOR_RAM$$Base -#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) -#elif defined(__ICCARM__) - extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; -#elif defined(__GNUC__) - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; - extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; - uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); -#endif /* defined(__CC_ARM) */ - uint32_t n; - uint32_t ret; - uint32_t irqMaskValue; - - irqMaskValue = DisableGlobalIRQ(); - if (SCB->VTOR != (uint32_t)__VECTOR_RAM) - { - /* Copy the vector table from ROM to RAM */ - for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) - { - __VECTOR_RAM[n] = __VECTOR_TABLE[n]; - } - /* Point the VTOR to the position of vector table */ - SCB->VTOR = (uint32_t)__VECTOR_RAM; - } - - ret = __VECTOR_RAM[irq + 16]; - /* make sure the __VECTOR_RAM is noncachable */ - __VECTOR_RAM[irq + 16] = irqHandler; - - EnableGlobalIRQ(irqMaskValue); - -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif - - return ret; -} -#endif /* ENABLE_RAM_VECTOR_TABLE. */ -#endif /* __GIC_PRIO_BITS. */ - -#ifndef QN908XC_SERIES -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - -void EnableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t intNumber = (uint32_t)interrupt; - -#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1)) - { - SYSCON->STARTERP1 = 1u << intNumber; - } -#else - { - uint32_t index = 0; - - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERSET[index] = 1u << intNumber; - } -#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */ - EnableIRQ(interrupt); /* also enable interrupt at NVIC */ -} - -void DisableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t intNumber = (uint32_t)interrupt; - - DisableIRQ(interrupt); /* also disable interrupt at NVIC */ -#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1)) - { - SYSCON->STARTERP1 &= ~(1u << intNumber); - } -#else - { - uint32_t index = 0; - - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERCLR[index] = 1u << intNumber; - } -#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */ -} -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - -#endif /* QN908XC_SERIES */ - -void *SDK_Malloc(size_t size, size_t alignbytes) -{ - mem_align_cb_t *p_cb = NULL; - uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t); - void *p_align_addr, *p_addr = malloc(alignedsize); - - if (!p_addr) - { - return NULL; - } - - p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes); - - p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4); - p_cb->identifier = SDK_MEM_MAGIC_NUMBER; - p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr; - - return (void *)p_align_addr; -} - -void SDK_Free(void *ptr) -{ - mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4); - - if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) - { - return; - } - - free((void *)((uint32_t)ptr - p_cb->offset)); -} - diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_common.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_common.h deleted file mode 100644 index a53dbc2713d..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_common.h +++ /dev/null @@ -1,576 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_COMMON_H_ -#define _FSL_COMMON_H_ - -#include -#include -#include -#include -#include - -#if defined(__ICCARM__) -#include -#endif - -#include "fsl_device_registers.h" - -/*! - * @addtogroup ksdk_common - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Construct a status code value from a group and code number. */ -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) - -/*! @brief Construct the version number for drivers. */ -#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) - -/*! @name Driver version */ -/*@{*/ -/*! @brief common driver version 2.0.0. */ -#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/* Debug console type definition. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console base on LPC_USART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console base on SWO. */ - -/*! @brief Status group numbers. */ -enum _status_groups -{ - kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ - kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ - kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ - kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ - kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ - kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ - kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ - kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ - kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ - kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ - kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ - kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ - kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ - kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ - kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ - kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ - kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ - kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ - kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ - kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ - kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ - kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ - kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ - kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ - kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ - kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ - kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ - kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ - kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ - kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ - kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ - kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ - kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ - kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ - kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ - kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ - kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ - kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ - kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ - kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ - kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ - kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ - kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ - kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ - kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ - kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ - kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ - kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ - kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ - kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ - kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ - kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ - kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ - kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ - kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ - kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ - kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ - kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ - kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ - kStatusGroup_MICFIL = 72, /*!< Group number for MIC status codes. */ - kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ - kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ - kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ - kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ - kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ - kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ - kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ - kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ -}; - -/*! @brief Generic status return codes. */ -enum _generic_status -{ - kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), - kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), - kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), - kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), - kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), - kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), - kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), -}; - -/*! @brief Type used for all status and error return values. */ -typedef int32_t status_t; - -/* - * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t - * defined in previous of this file. - */ -#include "fsl_clock.h" - -/* - * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral - */ -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) -#include "fsl_reset.h" -#endif - -/* - * Macro guard for whether to use default weak IRQ implementation in drivers - */ -#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ -#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 -#endif - -/*! @name Min/max macros */ -/* @{ */ -#if !defined(MIN) -#define MIN(a, b) ((a) < (b) ? (a) : (b)) -#endif - -#if !defined(MAX) -#define MAX(a, b) ((a) > (b) ? (a) : (b)) -#endif -/* @} */ - -/*! @brief Computes the number of elements in an array. */ -#if !defined(ARRAY_SIZE) -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) -#endif - -/*! @name UINT16_MAX/UINT32_MAX value */ -/* @{ */ -#if !defined(UINT16_MAX) -#define UINT16_MAX ((uint16_t)-1) -#endif - -#if !defined(UINT32_MAX) -#define UINT32_MAX ((uint32_t)-1) -#endif -/* @} */ - -/*! @name Timer utilities */ -/* @{ */ -/*! Macro to convert a microsecond period to raw count value */ -#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) -/*! Macro to convert a raw count value to microsecond */ -#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) - -/*! Macro to convert a millisecond period to raw count value */ -#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) -/*! Macro to convert a raw count value to millisecond */ -#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) -/* @} */ - -/*! @name Alignment variable definition macros */ -/* @{ */ -#if (defined(__ICCARM__)) -/** - * Workaround to disable MISRA C message suppress warnings for IAR compiler. - * http://supp.iar.com/Support/?note=24725 - */ -_Pragma("diag_suppress=Pm120") -#define SDK_PRAGMA(x) _Pragma(#x) - _Pragma("diag_error=Pm120") -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var -#endif -#elif defined(__ARMCC_VERSION) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var -#endif -#elif defined(__GNUC__) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) -#endif -#else -#error Toolchain not supported -#define SDK_ALIGN(var, alignbytes) var -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) var -#endif -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) var -#endif -#endif - -/*! Macro to change a value to a given size aligned value */ -#define SDK_SIZEALIGN(var, alignbytes) \ - ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1))) -/* @} */ - -/*! @name Non-cacheable region definition macros */ -/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or - * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, - * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables - * will be initialized to zero in system startup. - */ -/* @{ */ -#if (defined(__ICCARM__)) -#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) -#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" -#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" -#else -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -#endif -#elif(defined(__ARMCC_VERSION)) -#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var -#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) __align(alignbytes) var -#else -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __align(alignbytes) var -#endif -#elif(defined(__GNUC__)) -/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" - * in your projects to make sure the non-cacheable section variables will be initialized in system startup. - */ -#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) -#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) -#else -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes))) -#endif -#else -#error Toolchain not supported. -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var -#endif -/* @} */ - -/*! @name Time sensitive region */ -/* @{ */ -#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE -#if (defined(__ICCARM__)) -#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" -#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" -#elif(defined(__ARMCC_VERSION)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func -#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func -#elif(defined(__GNUC__)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func -#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func -#else -#error Toolchain not supported. -#endif /* defined(__ICCARM__) */ -#else -#if (defined(__ICCARM__)) -#define AT_QUICKACCESS_SECTION_CODE(func) func -#define AT_QUICKACCESS_SECTION_DATA(func) func -#elif(defined(__ARMCC_VERSION)) -#define AT_QUICKACCESS_SECTION_CODE(func) func -#define AT_QUICKACCESS_SECTION_DATA(func) func -#elif(defined(__GNUC__)) -#define AT_QUICKACCESS_SECTION_CODE(func) func -#define AT_QUICKACCESS_SECTION_DATA(func) func -#else -#error Toolchain not supported. -#endif -#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ -/* @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) - extern "C" -{ -#endif - - /*! - * @brief Enable specific interrupt. - * - * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt enabled successfully - * @retval kStatus_Fail Failed to enable the interrupt - */ - static inline status_t EnableIRQ(IRQn_Type interrupt) - { - if (NotAvail_IRQn == interrupt) - { - return kStatus_Fail; - } - -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - return kStatus_Fail; - } -#endif - -#if defined(__GIC_PRIO_BITS) - GIC_EnableIRQ(interrupt); -#else - NVIC_EnableIRQ(interrupt); -#endif - return kStatus_Success; - } - - /*! - * @brief Disable specific interrupt. - * - * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt disabled successfully - * @retval kStatus_Fail Failed to disable the interrupt - */ - static inline status_t DisableIRQ(IRQn_Type interrupt) - { - if (NotAvail_IRQn == interrupt) - { - return kStatus_Fail; - } - -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - return kStatus_Fail; - } -#endif - -#if defined(__GIC_PRIO_BITS) - GIC_DisableIRQ(interrupt); -#else - NVIC_DisableIRQ(interrupt); -#endif - return kStatus_Success; - } - - /*! - * @brief Disable the global IRQ - * - * Disable the global interrupt and return the current primask register. User is required to provided the primask - * register for the EnableGlobalIRQ(). - * - * @return Current primask value. - */ - static inline uint32_t DisableGlobalIRQ(void) - { -#if defined(CPSR_I_Msk) - uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; - - __disable_irq(); - - return cpsr; -#else - uint32_t regPrimask = __get_PRIMASK(); - - __disable_irq(); - - return regPrimask; -#endif - } - - /*! - * @brief Enaable the global IRQ - * - * Set the primask register with the provided primask value but not just enable the primask. The idea is for the - * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to - * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. - * - * @param primask value of primask register to be restored. The primask value is supposed to be provided by the - * DisableGlobalIRQ(). - */ - static inline void EnableGlobalIRQ(uint32_t primask) - { -#if defined(CPSR_I_Msk) - __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); -#else - __set_PRIMASK(primask); -#endif - } - -#if defined(ENABLE_RAM_VECTOR_TABLE) - /*! - * @brief install IRQ handler - * - * @param irq IRQ number - * @param irqHandler IRQ handler address - * @return The old IRQ handler address - */ - uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); -#endif /* ENABLE_RAM_VECTOR_TABLE. */ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - /*! - * @brief Enable specific interrupt for wake-up from deep-sleep mode. - * - * Enable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally). - * - * @param interrupt The IRQ number. - */ - void EnableDeepSleepIRQ(IRQn_Type interrupt); - - /*! - * @brief Disable specific interrupt for wake-up from deep-sleep mode. - * - * Disable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally). - * - * @param interrupt The IRQ number. - */ - void DisableDeepSleepIRQ(IRQn_Type interrupt); -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - - /*! - * @brief Allocate memory with given alignment and aligned size. - * - * This is provided to support the dynamically allocated memory - * used in cache-able region. - * @param size The length required to malloc. - * @param alignbytes The alignment size. - * @retval The allocated memory. - */ - void *SDK_Malloc(size_t size, size_t alignbytes); - - /*! - * @brief Free memory. - * - * @param ptr The memory to be release. - */ - void SDK_Free(void *ptr); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_COMMON_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_crc.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_crc.c deleted file mode 100644 index 840817776a6..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_crc.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_crc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_crc" -#endif - - -#if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT -/* @brief Default user configuration structure for CRC-CCITT */ -#define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT -/*< CRC-CCIT polynomial x^16 + x^12 + x^5 + x^0 */ -#define CRC_DRIVER_DEFAULT_REVERSE_IN false -/*< Default is no bit reverse */ -#define CRC_DRIVER_DEFAULT_COMPLEMENT_IN false -/*< Default is without complement of written data */ -#define CRC_DRIVER_DEFAULT_REVERSE_OUT false -/*< Default is no bit reverse */ -#define CRC_DRIVER_DEFAULT_COMPLEMENT_OUT false -/*< Default is without complement of CRC data register read data */ -#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU -/*< Default initial checksum */ -#endif /* CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -void CRC_Init(CRC_Type *base, const crc_config_t *config) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* enable clock to CRC */ - CLOCK_EnableClock(kCLOCK_Crc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* configure CRC module and write the seed */ - base->MODE = 0 | CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) | - CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) | - CRC_MODE_CMPL_SUM(config->complementOut); - base->SEED = config->seed; -} - -void CRC_GetDefaultConfig(crc_config_t *config) -{ - static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_REVERSE_IN, - CRC_DRIVER_DEFAULT_COMPLEMENT_IN, CRC_DRIVER_DEFAULT_REVERSE_OUT, - CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED}; - - *config = default_config; -} - -void CRC_Reset(CRC_Type *base) -{ - crc_config_t config; - CRC_GetDefaultConfig(&config); - CRC_Init(base, &config); -} - -void CRC_GetConfig(CRC_Type *base, crc_config_t *config) -{ - /* extract CRC mode settings */ - uint32_t mode = base->MODE; - config->polynomial = (crc_polynomial_t)((mode & CRC_MODE_CRC_POLY_MASK) >> CRC_MODE_CRC_POLY_SHIFT); - config->reverseIn = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK); - config->complementIn = (bool)(mode & CRC_MODE_CMPL_WR_MASK); - config->reverseOut = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK); - config->complementOut = (bool)(mode & CRC_MODE_CMPL_SUM_MASK); - - /* reset CRC sum bit reverse and 1's complement setting, so its value can be used as a seed */ - base->MODE = mode & ~((1U << CRC_MODE_BIT_RVS_SUM_SHIFT) | (1U << CRC_MODE_CMPL_SUM_SHIFT)); - - /* now we can obtain intermediate raw CRC sum value */ - config->seed = base->SUM; - - /* restore original CRC sum bit reverse and 1's complement setting */ - base->MODE = mode; -} - -void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) -{ - const uint32_t *data32; - - /* 8-bit reads and writes till source address is aligned 4 bytes */ - while ((dataSize) && ((uint32_t)data & 3U)) - { - *((__O uint8_t *)&(base->WR_DATA)) = *data; - data++; - dataSize--; - } - - /* use 32-bit reads and writes as long as possible */ - data32 = (const uint32_t *)data; - while (dataSize >= sizeof(uint32_t)) - { - *((__O uint32_t *)&(base->WR_DATA)) = *data32; - data32++; - dataSize -= sizeof(uint32_t); - } - - data = (const uint8_t *)data32; - - /* 8-bit reads and writes till end of data buffer */ - while (dataSize) - { - *((__O uint8_t *)&(base->WR_DATA)) = *data; - data++; - dataSize--; - } -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_crc.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_crc.h deleted file mode 100644 index b2f8244b834..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_crc.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_CRC_H_ -#define _FSL_CRC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup crc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CRC driver version. Version 2.0.1. - * - * Current version: 2.0.1 - * - * Change log: - * - Version 2.0.0 - * - initial version - * - Version 2.0.1 - * - add explicit type cast when writing to WR_DATA - */ -#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -#ifndef CRC_DRIVER_CUSTOM_DEFAULTS -/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Uses CRC-16/CCITT-FALSE as default. */ -#define CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT 1 -#endif - -/*! @brief CRC polynomials to use. */ -typedef enum _crc_polynomial -{ - kCRC_Polynomial_CRC_CCITT = 0U, /*!< x^16+x^12+x^5+1 */ - kCRC_Polynomial_CRC_16 = 1U, /*!< x^16+x^15+x^2+1 */ - kCRC_Polynomial_CRC_32 = 2U /*!< x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */ -} crc_polynomial_t; - -/*! -* @brief CRC protocol configuration. -* -* This structure holds the configuration for the CRC protocol. -* -*/ -typedef struct _crc_config -{ - crc_polynomial_t polynomial; /*!< CRC polynomial. */ - bool reverseIn; /*!< Reverse bits on input. */ - bool complementIn; /*!< Perform 1's complement on input. */ - bool reverseOut; /*!< Reverse bits on output. */ - bool complementOut; /*!< Perform 1's complement on output. */ - uint32_t seed; /*!< Starting checksum value. */ -} crc_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Enables and configures the CRC peripheral module. - * - * This functions enables the CRC peripheral clock in the LPC SYSCON block. - * It also configures the CRC engine and starts checksum computation by writing the seed. - * - * @param base CRC peripheral address. - * @param config CRC module configuration structure. - */ -void CRC_Init(CRC_Type *base, const crc_config_t *config); - -/*! - * @brief Disables the CRC peripheral module. - * - * This functions disables the CRC peripheral clock in the LPC SYSCON block. - * - * @param base CRC peripheral address. - */ -static inline void CRC_Deinit(CRC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* disable clock to CRC */ - CLOCK_DisableClock(kCLOCK_Crc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief resets CRC peripheral module. - * - * @param base CRC peripheral address. - */ -void CRC_Reset(CRC_Type *base); - -/*! - * @brief Loads default values to CRC protocol configuration structure. - * - * Loads default values to CRC protocol configuration structure. The default values are: - * @code - * config->polynomial = kCRC_Polynomial_CRC_CCITT; - * config->reverseIn = false; - * config->complementIn = false; - * config->reverseOut = false; - * config->complementOut = false; - * config->seed = 0xFFFFU; - * @endcode - * - * @param config CRC protocol configuration structure - */ -void CRC_GetDefaultConfig(crc_config_t *config); - -/*! - * @brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure. - * - * The values, including seed, can be used to resume CRC calculation later. - - * @param base CRC peripheral address. - * @param config CRC protocol configuration structure - */ -void CRC_GetConfig(CRC_Type *base, crc_config_t *config); - -/*! - * @brief Writes data to the CRC module. - * - * Writes input data buffer bytes to CRC data register. - * - * @param base CRC peripheral address. - * @param data Input data stream, MSByte in data[0]. - * @param dataSize Size of the input data buffer in bytes. - */ -void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize); - -/*! - * @brief Reads 32-bit checksum from the CRC module. - * - * Reads CRC data register. - * - * @param base CRC peripheral address. - * @return final 32-bit checksum, after configured bit reverse and complement operations. - */ -static inline uint32_t CRC_Get32bitResult(CRC_Type *base) -{ - return base->SUM; -} - -/*! - * @brief Reads 16-bit checksum from the CRC module. - * - * Reads CRC data register. - * - * @param base CRC peripheral address. - * @return final 16-bit checksum, after configured bit reverse and complement operations. - */ -static inline uint16_t CRC_Get16bitResult(CRC_Type *base) -{ - return (uint16_t)base->SUM; -} - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_CRC_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_ctimer.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_ctimer.c deleted file mode 100644 index 87f1d2453b4..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_ctimer.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_ctimer.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.ctimer" -#endif - - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base Ctimer peripheral base address - * - * @return The Timer instance - */ -static uint32_t CTIMER_GetInstance(CTIMER_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to Timer bases for each instance. */ -static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to Timer clocks for each instance. */ -static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET -/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N; -#else -/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; -#endif - -/*! @brief Pointers real ISRs installed by drivers for each instance. */ -static ctimer_callback_t *s_ctimerCallback[FSL_FEATURE_SOC_CTIMER_COUNT] = {0}; - -/*! @brief Callback type installed by drivers for each instance. */ -static ctimer_callback_type_t ctimerCallbackType[FSL_FEATURE_SOC_CTIMER_COUNT] = {kCTIMER_SingleCallback}; - -/*! @brief Array to map timer instance to IRQ number. */ -static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t CTIMER_GetInstance(CTIMER_Type *base) -{ - uint32_t instance; - uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ctimerArrayCount; instance++) - { - if (s_ctimerBases[instance] == base) - { - break; - } - } - - assert(instance < ctimerArrayCount); - - return instance; -} - -void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) -{ - assert(config); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the timer clock*/ - CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the module */ - RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]); - - /* Setup the cimer mode and count select */ - base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input); - - /* Setup the timer prescale value */ - base->PR = CTIMER_PR_PRVAL(config->prescale); -} - -void CTIMER_Deinit(CTIMER_Type *base) -{ - uint32_t index = CTIMER_GetInstance(base); - /* Stop the timer */ - base->TCR &= ~CTIMER_TCR_CEN_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the timer clock*/ - CLOCK_DisableClock(s_ctimerClocks[index]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Disable IRQ at NVIC Level */ - DisableIRQ(s_ctimerIRQ[index]); -} - -void CTIMER_GetDefaultConfig(ctimer_config_t *config) -{ - assert(config); - - /* Run as a timer */ - config->mode = kCTIMER_TimerMode; - /* This field is ignored when mode is timer */ - config->input = kCTIMER_Capture_0; - /* Timer counter is incremented on every APB bus clock */ - config->prescale = 0; -} - -status_t CTIMER_SetupPwm(CTIMER_Type *base, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - bool enableInt) -{ - assert(pwmFreq_Hz > 0); - - uint32_t reg; - uint32_t period, pulsePeriod = 0; - uint32_t timerClock = srcClock_Hz / (base->PR + 1); - uint32_t index = CTIMER_GetInstance(base); - - if (matchChannel == kCTIMER_Match_3) - { - return kStatus_Fail; - } - - /* Enable PWM mode on the channel */ - base->PWMC |= (1U << matchChannel); - - /* Clear the stop, reset and interrupt bits for this channel */ - reg = base->MCR; - reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); - - /* If call back function is valid then enable match interrupt for the channel */ - if (enableInt) - { - reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); - } - - /* Reset the counter when match on channel 3 */ - reg |= CTIMER_MCR_MR3R_MASK; - - base->MCR = reg; - - /* Calculate PWM period match value */ - period = (timerClock / pwmFreq_Hz) - 1; - - /* Calculate pulse width match value */ - if (dutyCyclePercent == 0) - { - pulsePeriod = period + 1; - } - else - { - pulsePeriod = (period * (100 - dutyCyclePercent)) / 100; - } - - /* Match on channel 3 will define the PWM period */ - base->MR[kCTIMER_Match_3] = period; - - /* This will define the PWM pulse period */ - base->MR[matchChannel] = pulsePeriod; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); - /* If call back function is valid then enable interrupt and update the call back function */ - if (enableInt) - { - EnableIRQ(s_ctimerIRQ[index]); - } - - return kStatus_Success; -} - -status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, - ctimer_match_t matchChannel, - uint32_t pwmPeriod, - uint32_t pulsePeriod, - bool enableInt) -{ - uint32_t reg; - uint32_t index = CTIMER_GetInstance(base); - - if (matchChannel == kCTIMER_Match_3) - { - return kStatus_Fail; - } - - /* Enable PWM mode on the channel */ - base->PWMC |= (1U << matchChannel); - - /* Clear the stop, reset and interrupt bits for this channel */ - reg = base->MCR; - reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); - - /* If call back function is valid then enable match interrupt for the channel */ - if (enableInt) - { - reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); - } - - /* Reset the counter when match on channel 3 */ - reg |= CTIMER_MCR_MR3R_MASK; - - base->MCR = reg; - - /* Match on channel 3 will define the PWM period */ - base->MR[kCTIMER_Match_3] = pwmPeriod; - - /* This will define the PWM pulse period */ - base->MR[matchChannel] = pulsePeriod; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); - /* If call back function is valid then enable interrupt and update the call back function */ - if (enableInt) - { - EnableIRQ(s_ctimerIRQ[index]); - } - - return kStatus_Success; -} - -void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent) -{ - uint32_t pulsePeriod = 0, period; - - /* Match channel 3 defines the PWM period */ - period = base->MR[kCTIMER_Match_3]; - - /* Calculate pulse width match value */ - pulsePeriod = (period * dutyCyclePercent) / 100; - - /* For 0% dutycyle, make pulse period greater than period so the event will never occur */ - if (dutyCyclePercent == 0) - { - pulsePeriod = period + 1; - } - else - { - pulsePeriod = (period * (100 - dutyCyclePercent)) / 100; - } - - /* Update dutycycle */ - base->MR[matchChannel] = pulsePeriod; -} - -void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config) -{ - uint32_t reg; - uint32_t index = CTIMER_GetInstance(base); - - /* Set the counter operation when a match on this channel occurs */ - reg = base->MCR; - reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); - reg |= (uint32_t)((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + (matchChannel * 3))); - reg |= (uint32_t)((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + (matchChannel * 3))); - reg |= (uint32_t)((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); - base->MCR = reg; - - reg = base->EMR; - /* Set the match output operation when a match on this channel occurs */ - reg &= ~(CTIMER_EMR_EMC0_MASK << (matchChannel * 2)); - reg |= (uint32_t)config->outControl << (CTIMER_EMR_EMC0_SHIFT + (matchChannel * 2)); - - /* Set the initial state of the EM bit/output */ - reg &= ~(CTIMER_EMR_EM0_MASK << matchChannel); - reg |= (uint32_t)config->outPinInitState << matchChannel; - base->EMR = reg; - - /* Set the match value */ - base->MR[matchChannel] = config->matchValue; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); - /* If interrupt is enabled then enable interrupt and update the call back function */ - if (config->enableInterrupt) - { - EnableIRQ(s_ctimerIRQ[index]); - } -} - -void CTIMER_SetupCapture(CTIMER_Type *base, - ctimer_capture_channel_t capture, - ctimer_capture_edge_t edge, - bool enableInt) -{ - uint32_t reg = base->CCR; - uint32_t index = CTIMER_GetInstance(base); - - /* Set the capture edge */ - reg &= ~((CTIMER_CCR_CAP0RE_MASK | CTIMER_CCR_CAP0FE_MASK | CTIMER_CCR_CAP0I_MASK) << (capture * 3)); - reg |= (uint32_t)edge << (CTIMER_CCR_CAP0RE_SHIFT + (capture * 3)); - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, (kCTIMER_Capture0Flag << capture)); - /* If call back function is valid then enable capture interrupt for the channel and update the call back function */ - if (enableInt) - { - reg |= CTIMER_CCR_CAP0I_MASK << (capture * 3); - EnableIRQ(s_ctimerIRQ[index]); - } - base->CCR = reg; -} - -void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type) -{ - uint32_t index = CTIMER_GetInstance(base); - s_ctimerCallback[index] = cb_func; - ctimerCallbackType[index] = cb_type; -} - -void CTIMER_GenericIRQHandler(uint32_t index) -{ - uint32_t int_stat, i, mask; - /* Get Interrupt status flags */ - int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]); - /* Clear the status flags that were set */ - CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat); - if (ctimerCallbackType[index] == kCTIMER_SingleCallback) - { - if (s_ctimerCallback[index][0]) - { - s_ctimerCallback[index][0](int_stat); - } - } - else - { -#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT - for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) -#else - for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) -#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ - { - mask = 0x01 << i; - /* For each status flag bit that was set call the callback function if it is valid */ - if ((int_stat & mask) && (s_ctimerCallback[index][i])) - { - s_ctimerCallback[index][i](int_stat); - } - } - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(CTIMER0) -void CTIMER0_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(0); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(CTIMER1) -void CTIMER1_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(1); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(CTIMER2) -void CTIMER2_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(2); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(CTIMER3) -void CTIMER3_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(3); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(CTIMER4) -void CTIMER4_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(4); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -#endif diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_ctimer.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_ctimer.h deleted file mode 100644 index 6392451b3f7..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_ctimer.h +++ /dev/null @@ -1,496 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_CTIMER_H_ -#define _FSL_CTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup ctimer - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */ -/*@}*/ - -/*! @brief List of Timer capture channels */ -typedef enum _ctimer_capture_channel -{ - kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ - kCTIMER_Capture_1, /*!< Timer capture channel 1 */ - kCTIMER_Capture_2, /*!< Timer capture channel 2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - kCTIMER_Capture_3 /*!< Timer capture channel 3 */ -#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ -} ctimer_capture_channel_t; - -/*! @brief List of capture edge options */ -typedef enum _ctimer_capture_edge -{ - kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */ - kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */ - kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */ -} ctimer_capture_edge_t; - -/*! @brief List of Timer match registers */ -typedef enum _ctimer_match -{ - kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */ - kCTIMER_Match_1, /*!< Timer match register 1 */ - kCTIMER_Match_2, /*!< Timer match register 2 */ - kCTIMER_Match_3 /*!< Timer match register 3 */ -} ctimer_match_t; - -/*! @brief List of output control options */ -typedef enum _ctimer_match_output_control -{ - kCTIMER_Output_NoAction = 0U, /*!< No action is taken */ - kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */ - kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */ - kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */ -} ctimer_match_output_control_t; - -/*! @brief List of Timer modes */ -typedef enum _ctimer_timer_mode -{ - kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */ - kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */ - kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */ - kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */ -} ctimer_timer_mode_t; - -/*! @brief List of Timer interrupts */ -typedef enum _ctimer_interrupt_enable -{ - kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ - kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ - kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ - kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ - kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ - kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ - kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ -} ctimer_interrupt_enable_t; - -/*! @brief List of Timer flags */ -typedef enum _ctimer_status_flags -{ - kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ - kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ - kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ - kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ - kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ - kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ - kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ -#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT - kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ -#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ -} ctimer_status_flags_t; - -typedef void (*ctimer_callback_t)(uint32_t flags); - -/*! @brief Callback type when registering for a callback. When registering a callback - * an array of function pointers is passed the size could be 1 or 8, the callback - * type will tell that. - */ -typedef enum -{ - kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. - based on the status flags different channels needs to be handled differently */ - kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. - for both match/capture */ -} ctimer_callback_type_t; - -/*! - * @brief Match configuration - * - * This structure holds the configuration settings for each match register. - */ -typedef struct _ctimer_match_config -{ - uint32_t matchValue; /*!< This is stored in the match register */ - bool enableCounterReset; /*!< true: Match will reset the counter - false: Match will not reser the counter */ - bool enableCounterStop; /*!< true: Match will stop the counter - false: Match will not stop the counter */ - ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */ - bool outPinInitState; /*!< Initial value of the EM bit/output */ - bool enableInterrupt; /*!< true: Generate interrupt upon match - false: Do not generate interrupt on match */ - -} ctimer_match_config_t; - -/*! - * @brief Timer configuration structure - * - * This structure holds the configuration settings for the Timer peripheral. To initialize this - * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a - * pointer to the configuration structure instance. - * - * The configuration structure can be made constant so as to reside in flash. - */ -typedef struct _ctimer_config -{ - ctimer_timer_mode_t mode; /*!< Timer mode */ - ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer - modes that rely on this input signal to increment TC */ - uint32_t prescale; /*!< Prescale value */ -} ctimer_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application before using the driver. - * - * @param base Ctimer peripheral base address - * @param config Pointer to the user configuration structure. - */ -void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config); - -/*! - * @brief Gates the timer clock. - * - * @param base Ctimer peripheral base address - */ -void CTIMER_Deinit(CTIMER_Type *base); - -/*! - * @brief Fills in the timers configuration structure with the default settings. - * - * The default values are: - * @code - * config->mode = kCTIMER_TimerMode; - * config->input = kCTIMER_Capture_0; - * config->prescale = 0; - * @endcode - * @param config Pointer to the user configuration structure. - */ -void CTIMER_GetDefaultConfig(ctimer_config_t *config); - -/*! @}*/ - -/*! - * @name PWM setup operations - * @{ - */ - -/*! - * @brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function will assign match channel 3 to set the PWM cycle. - * - * @note When setting PWM output from multiple output pins, all should use the same PWM - * period - * - * @param base Ctimer peripheral base address - * @param matchChannel Match pin to be used to output the PWM signal - * @param pwmPeriod PWM period match value - * @param pulsePeriod Pulse width match value - * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt is generated - * - * @return kStatus_Success on success - * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period - */ -status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, - ctimer_match_t matchChannel, - uint32_t pwmPeriod, - uint32_t pulsePeriod, - bool enableInt); - -/*! - * @brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function will assign match channel 3 to set the PWM cycle. - * - * @note When setting PWM output from multiple output pins, all should use the same PWM - * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match pin to be used to output the PWM signal - * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz Timer counter clock in Hz - * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt is generated - * - * @return kStatus_Success on success - * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle - */ -status_t CTIMER_SetupPwm(CTIMER_Type *base, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - bool enableInt); - -/*! - * @brief Updates the pulse period of an active PWM signal. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match pin to be used to output the PWM signal - * @param pulsePeriod New PWM pulse width match value - */ -static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod) -{ - /* Update PWM pulse period match value */ - base->MR[matchChannel] = pulsePeriod; -} - -/*! - * @brief Updates the duty cycle of an active PWM signal. - * - * @note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match pin to be used to output the PWM signal - * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 - */ -void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent); - -/*! @}*/ - -/*! - * @brief Setup the match register. - * - * User configuration is used to setup the match value and action to be taken when a match occurs. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match register to configure - * @param config Pointer to the match configuration structure - */ -void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config); - -/*! - * @brief Setup the capture. - * - * @param base Ctimer peripheral base address - * @param capture Capture channel to configure - * @param edge Edge on the channel that will trigger a capture - * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back - * is called upon capture - */ -void CTIMER_SetupCapture(CTIMER_Type *base, - ctimer_capture_channel_t capture, - ctimer_capture_edge_t edge, - bool enableInt); - -/*! - * @brief Register callback. - * - * @param base Ctimer peripheral base address - * @param cb_func callback function - * @param cb_type callback function type, singular or multiple - */ -void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type); - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected Timer interrupts. - * - * @param base Ctimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) -{ - /* Enable match interrupts */ - base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); - - /* Enable capture interrupts */ - base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - ); -} - -/*! - * @brief Disables the selected Timer interrupts. - * - * @param base Ctimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) -{ - /* Disable match interrupts */ - base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK)); - - /* Disable capture interrupts */ - base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - )); -} - -/*! - * @brief Gets the enabled Timer interrupts. - * - * @param base Ctimer peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) -{ - uint32_t enabledIntrs = 0; - - /* Get all the match interrupts enabled */ - enabledIntrs = - base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); - - /* Get all the capture interrupts enabled */ - enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - ); - - return enabledIntrs; -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the Timer status flags. - * - * @param base Ctimer peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::ctimer_status_flags_t - */ -static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base) -{ - return base->IR; -} - -/*! - * @brief Clears the Timer status flags. - * - * @param base Ctimer peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::ctimer_status_flags_t - */ -static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask) -{ - base->IR = mask; -} - -/*! @}*/ - -/*! - * @name Counter Start and Stop - * @{ - */ - -/*! - * @brief Starts the Timer counter. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_StartTimer(CTIMER_Type *base) -{ - base->TCR |= CTIMER_TCR_CEN_MASK; -} - -/*! - * @brief Stops the Timer counter. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_StopTimer(CTIMER_Type *base) -{ - base->TCR &= ~CTIMER_TCR_CEN_MASK; -} - -/*! @}*/ - -/*! - * @brief Reset the counter. - * - * The timer counter and prescale counter are reset on the next positive edge of the APB clock. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_Reset(CTIMER_Type *base) -{ - base->TCR |= CTIMER_TCR_CRST_MASK; - base->TCR &= ~CTIMER_TCR_CRST_MASK; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_CTIMER_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dma.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dma.c deleted file mode 100644 index 5eaf1c5d648..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dma.c +++ /dev/null @@ -1,481 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_dma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_dma" -#endif - - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for DMA. - * - * @param base DMA peripheral base address. - */ -static uint32_t DMA_GetInstance(DMA_Type *base); - -/*! - * @brief Get virtual channel number. - * - * @param base DMA peripheral base address. - */ -static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map DMA instance number to base pointer. */ -static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map DMA instance number to clock name. */ -static const clock_ip_name_t s_dmaClockName[] = DMA_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Array to map DMA instance number to IRQ number. */ -static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS; - -/*! @brief Pointers to transfer handle for each DMA channel. */ -static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_ALL_CHANNELS]; - -/*! @brief Static table of descriptors */ -#if defined(__ICCARM__) -#pragma data_alignment = FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE -static dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_SOC_DMA_COUNT][FSL_FEATURE_DMA_MAX_CHANNELS] = {0}; -#elif defined(__CC_ARM) -__attribute__((aligned(FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE))) -static dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_SOC_DMA_COUNT][FSL_FEATURE_DMA_MAX_CHANNELS] = {0}; -#elif defined(__GNUC__) -__attribute__((aligned(FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE))) -static dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_SOC_DMA_COUNT][FSL_FEATURE_DMA_MAX_CHANNELS] = {0}; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t DMA_GetInstance(DMA_Type *base) -{ - int32_t instance; - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++) - { - if (s_dmaBases[instance] == base) - { - break; - } - } - assert(instance < ARRAY_SIZE(s_dmaBases)); - - return instance; -} - -static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base) -{ - uint32_t startChannel = 0, instance = 0; - uint32_t i = 0; - - instance = DMA_GetInstance(base); - - /* Compute start channel */ - for (i = 0; i < instance; i++) - { - startChannel += FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(s_dmaBases[i]); - } - - return startChannel; -} - -void DMA_Init(DMA_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* enable dma clock gate */ - CLOCK_EnableClock(s_dmaClockName[DMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* set descriptor table */ - base->SRAMBASE = (uint32_t)s_dma_descriptor_table; - /* enable dma peripheral */ - base->CTRL |= DMA_CTRL_ENABLE_MASK; -} - -void DMA_Deinit(DMA_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(s_dmaClockName[DMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Disable DMA peripheral */ - base->CTRL &= ~(DMA_CTRL_ENABLE_MASK); -} - -void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger) -{ - assert((channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)) && (NULL != trigger)); - - uint32_t tmp = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | - DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | - DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK); - tmp = base->CHANNEL[channel].CFG & (~tmp); - tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); - base->CHANNEL[channel].CFG = tmp; -} - -/*! - * @brief Gets the remaining bytes of the current DMA descriptor transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return The number of bytes which have not been transferred yet. - */ -uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - - /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes - * impossible to distinguish between: - * - transfer finishes (represented by value '0x3FF') - * - and remaining 1024 bytes to transfer (value 0x3FF) - * for all descriptor in chain, except the last one. - * If you decide to use this function, please use 1023 transfers as maximal value */ - - /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */ - if ((!DMA_ChannelIsActive(base, channel)) && - (0x3FF == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> - DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))) - { - return 0; - } - - return ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> - DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + - 1; -} - -static void DMA_SetupDescriptor( - dma_descriptor_t *desc, uint32_t xfercfg, void *srcEndAddr, void *dstEndAddr, void *nextDesc) -{ - desc->xfercfg = xfercfg; - desc->srcEndAddr = srcEndAddr; - desc->dstEndAddr = dstEndAddr; - desc->linkToNextDesc = nextDesc; -} - -/* Verify and convert dma_xfercfg_t to XFERCFG register */ -static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr) -{ - assert(xfercfg != NULL); - /* check source increment */ - assert((xfercfg->srcInc == 0) || (xfercfg->srcInc == 1) || (xfercfg->srcInc == 2) || (xfercfg->srcInc == 4)); - /* check destination increment */ - assert((xfercfg->dstInc == 0) || (xfercfg->dstInc == 1) || (xfercfg->dstInc == 2) || (xfercfg->dstInc == 4)); - /* check data width */ - assert((xfercfg->byteWidth == 1) || (xfercfg->byteWidth == 2) || (xfercfg->byteWidth == 4)); - /* check transfer count */ - assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT); - - uint32_t xfer = 0, tmp; - /* set valid flag - descriptor is ready now */ - xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid ? 1 : 0); - /* set reload - allow link to next descriptor */ - xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload ? 1 : 0); - /* set swtrig flag - start transfer */ - xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig ? 1 : 0); - /* set transfer count */ - xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig ? 1 : 0); - /* set INTA */ - xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA ? 1 : 0); - /* set INTB */ - xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB ? 1 : 0); - /* set data width */ - tmp = xfercfg->byteWidth == 4 ? 2 : xfercfg->byteWidth - 1; - xfer |= DMA_CHANNEL_XFERCFG_WIDTH(tmp); - /* set source increment value */ - tmp = xfercfg->srcInc == 4 ? 3 : xfercfg->srcInc; - xfer |= DMA_CHANNEL_XFERCFG_SRCINC(tmp); - /* set destination increment value */ - tmp = xfercfg->dstInc == 4 ? 3 : xfercfg->dstInc; - xfer |= DMA_CHANNEL_XFERCFG_DSTINC(tmp); - /* set transfer count */ - xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1); - - /* store xferCFG */ - *xfercfg_addr = xfer; -} - -void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc) -{ - uint32_t xfercfg_reg = 0; - - assert((NULL != desc) && (0 == (uint32_t)desc % 16) && (NULL != xfercfg)); - assert((NULL != srcAddr) && (0 == (uint32_t)srcAddr % xfercfg->byteWidth)); - assert((NULL != dstAddr) && (0 == (uint32_t)dstAddr % xfercfg->byteWidth)); - assert((NULL == nextDesc) || (0 == (uint32_t)nextDesc % 16)); - - /* Setup channel configuration */ - DMA_SetupXferCFG(xfercfg, &xfercfg_reg); - - /* Set descriptor structure */ - DMA_SetupDescriptor( - desc, xfercfg_reg, (uint8_t *)srcAddr + (xfercfg->srcInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)), - (uint8_t *)dstAddr + (xfercfg->dstInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)), nextDesc); -} - -void DMA_AbortTransfer(dma_handle_t *handle) -{ - assert(NULL != handle); - - DMA_DisableChannel(handle->base, handle->channel); - while (DMA_COMMON_CONST_REG_GET(handle->base, handle->channel, BUSY) & (1U << DMA_CHANNEL_INDEX(handle->channel))) - { - } - DMA_COMMON_REG_GET(handle->base, handle->channel, ABORT) |= 1U << DMA_CHANNEL_INDEX(handle->channel); - DMA_EnableChannel(handle->base, handle->channel); -} - -void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel) -{ - assert((NULL != handle) && (channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - - int32_t dmaInstance; - uint32_t startChannel = 0; - /* base address is invalid DMA instance */ - dmaInstance = DMA_GetInstance(base); - startChannel = DMA_GetVirtualStartChannel(base); - - memset(handle, 0, sizeof(*handle)); - handle->base = base; - handle->channel = channel; - s_DMAHandle[startChannel + channel] = handle; - /* Enable NVIC interrupt */ - EnableIRQ(s_dmaIRQNumber[dmaInstance]); -} - -void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData) -{ - assert(handle != NULL); - - handle->callback = callback; - handle->userData = userData; -} - -void DMA_PrepareTransfer(dma_transfer_config_t *config, - void *srcAddr, - void *dstAddr, - uint32_t byteWidth, - uint32_t transferBytes, - dma_transfer_type_t type, - void *nextDesc) -{ - uint32_t xfer_count; - assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr)); - assert((byteWidth == 1) || (byteWidth == 2) || (byteWidth == 4)); - - /* check max */ - xfer_count = transferBytes / byteWidth; - assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0 == transferBytes % byteWidth)); - - memset(config, 0, sizeof(*config)); - switch (type) - { - case kDMA_MemoryToMemory: - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 1; - config->isPeriph = false; - break; - case kDMA_PeripheralToMemory: - /* Peripheral register - source doesn't increment */ - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 1; - config->isPeriph = true; - break; - case kDMA_MemoryToPeripheral: - /* Peripheral register - destination doesn't increment */ - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - break; - case kDMA_StaticToStatic: - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - break; - default: - return; - } - - config->dstAddr = (uint8_t *)dstAddr; - config->srcAddr = (uint8_t *)srcAddr; - config->nextDesc = (uint8_t *)nextDesc; - config->xfercfg.transferCount = xfer_count; - config->xfercfg.byteWidth = byteWidth; - config->xfercfg.intA = true; - config->xfercfg.reload = nextDesc != NULL; - config->xfercfg.valid = true; -} - -status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) -{ - assert((NULL != handle) && (NULL != config)); - uint32_t instance = DMA_GetInstance(handle->base); - - /* Previous transfer has not finished */ - if (DMA_ChannelIsActive(handle->base, handle->channel)) - { - return kStatus_DMA_Busy; - } - - /* enable/disable peripheral request */ - if (config->isPeriph) - { - DMA_EnableChannelPeriphRq(handle->base, handle->channel); - } - else - { - DMA_DisableChannelPeriphRq(handle->base, handle->channel); - } - - DMA_CreateDescriptor(&(s_dma_descriptor_table[instance][handle->channel]), &config->xfercfg, config->srcAddr, - config->dstAddr, config->nextDesc); - - return kStatus_Success; -} - -void DMA_StartTransfer(dma_handle_t *handle) -{ - assert(NULL != handle); - - uint32_t instance = DMA_GetInstance(handle->base); - - /* Enable channel interrupt */ - DMA_EnableChannelInterrupts(handle->base, handle->channel); - - /* If HW trigger is enabled - disable SW trigger */ - if (handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK) - { - s_dma_descriptor_table[instance][handle->channel].xfercfg &= ~(DMA_CHANNEL_XFERCFG_SWTRIG_MASK); - } - /* Otherwise enable SW trigger */ - else - { - s_dma_descriptor_table[instance][handle->channel].xfercfg |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; - } - - /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = s_dma_descriptor_table[instance][handle->channel].xfercfg; - /* At this moment, the channel ACTIVE bit is set and application cannot modify - * or start another transfer using this channel. Channel ACTIVE bit is cleared by - * 'AbortTransfer' function or when the transfer finishes */ -} - -void DMA_IRQHandle(DMA_Type *base) -{ - dma_handle_t *handle; - int32_t channel_index; - uint32_t startChannel = DMA_GetVirtualStartChannel(base); - uint32_t i = 0; - - /* Find channels that have completed transfer */ - for (i = 0; i < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base); i++) - { - handle = s_DMAHandle[i + startChannel]; - /* Handle is not present */ - if (NULL == handle) - { - continue; - } - channel_index = DMA_CHANNEL_INDEX(handle->channel); - /* Channel uses INTA flag */ - if (DMA_COMMON_REG_GET(handle->base, handle->channel, INTA) & (1U << channel_index)) - { - /* Clear INTA flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, INTA, (1U << channel_index)); - if (handle->callback) - { - (handle->callback)(handle, handle->userData, true, kDMA_IntA); - } - } - /* Channel uses INTB flag */ - if (DMA_COMMON_REG_GET(handle->base, handle->channel, INTB) & (1U << channel_index)) - { - /* Clear INTB flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, INTB, (1U << channel_index)); - if (handle->callback) - { - (handle->callback)(handle, handle->userData, true, kDMA_IntB); - } - } - /* Error flag */ - if (DMA_COMMON_REG_GET(handle->base, handle->channel, ERRINT) & (1U << channel_index)) - { - /* Clear error flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, ERRINT, (1U << channel_index)); - if (handle->callback) - { - (handle->callback)(handle, handle->userData, false, kDMA_IntError); - } - } - } -} - -void DMA0_DriverIRQHandler(void) -{ - DMA_IRQHandle(DMA0); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -#if defined(DMA1) -void DMA1_DriverIRQHandler(void) -{ - DMA_IRQHandle(DMA1); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dma.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dma.h deleted file mode 100644 index ff2dee43881..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dma.h +++ /dev/null @@ -1,509 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_DMA_H_ -#define _FSL_DMA_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup dma - * @{ - */ - -/*! @file */ -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief DMA driver version */ -#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ -/*@}*/ - -#define DMA_MAX_TRANSFER_COUNT 0x400 - -#if defined FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_MAX_CHANNELS FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_ALL_CHANNELS (FSL_FEATURE_DMA_NUMBER_OF_CHANNELS * FSL_FEATURE_SOC_DMA_COUNT) -#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) -#endif - -/* Channel group consists of 32 channels. channel_group = (channel / 32) */ -#define DMA_CHANNEL_GROUP(channel) (((uint8_t)(channel)) >> 5U) -/* Channel index in channel group. channel_index = (channel % 32) */ -#define DMA_CHANNEL_INDEX(channel) (((uint8_t)(channel)) & 0x1F) - -#define DMA_COMMON_REG_GET(base, channel, reg) (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) -#define DMA_COMMON_CONST_REG_GET(base, channel, reg) (((volatile const uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) -#define DMA_COMMON_REG_SET(base, channel, reg, value) \ - (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)] = (value)) - -/*! @brief DMA descriptor structure */ -typedef struct _dma_descriptor -{ - uint32_t xfercfg; /*!< Transfer configuration */ - void *srcEndAddr; /*!< Last source address of DMA transfer */ - void *dstEndAddr; /*!< Last destination address of DMA transfer */ - void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */ -} dma_descriptor_t; - -/*! @brief DMA transfer configuration */ -typedef struct _dma_xfercfg -{ - bool valid; /*!< Descriptor is ready to transfer */ - bool reload; /*!< Reload channel configuration register after - current descriptor is exhausted */ - bool swtrig; /*!< Perform software trigger. Transfer if fired - when 'valid' is set */ - bool clrtrig; /*!< Clear trigger */ - bool intA; /*!< Raises IRQ when transfer is done and set IRQA status register flag */ - bool intB; /*!< Raises IRQ when transfer is done and set IRQB status register flag */ - uint8_t byteWidth; /*!< Byte width of data to transfer */ - uint8_t srcInc; /*!< Increment source address by 'srcInc' x 'byteWidth' */ - uint8_t dstInc; /*!< Increment destination address by 'dstInc' x 'byteWidth' */ - uint16_t transferCount; /*!< Number of transfers */ -} dma_xfercfg_t; - -/*! @brief DMA channel priority */ -typedef enum _dma_priority -{ - kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */ - kDMA_ChannelPriority1, /*!< Channel priority 1 */ - kDMA_ChannelPriority2, /*!< Channel priority 2 */ - kDMA_ChannelPriority3, /*!< Channel priority 3 */ - kDMA_ChannelPriority4, /*!< Channel priority 4 */ - kDMA_ChannelPriority5, /*!< Channel priority 5 */ - kDMA_ChannelPriority6, /*!< Channel priority 6 */ - kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */ -} dma_priority_t; - -/*! @brief DMA interrupt flags */ -typedef enum _dma_int -{ - kDMA_IntA, /*!< DMA interrupt flag A */ - kDMA_IntB, /*!< DMA interrupt flag B */ - kDMA_IntError, /*!< DMA interrupt flag error */ -} dma_irq_t; - -/*! @brief DMA trigger type*/ -typedef enum _dma_trigger_type -{ - kDMA_NoTrigger = 0, /*!< Trigger is disabled */ - kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */ - kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | - DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */ - kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */ - kDMA_RisingEdgeTrigger = - DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */ -} dma_trigger_type_t; - -/*! @brief DMA trigger burst */ -typedef enum _dma_trigger_burst -{ - kDMA_SingleTransfer = 0, /*!< Single transfer */ - kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */ - kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */ - kDMA_EdgeBurstTransfer2 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */ - kDMA_EdgeBurstTransfer4 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */ - kDMA_EdgeBurstTransfer8 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */ - kDMA_EdgeBurstTransfer16 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */ - kDMA_EdgeBurstTransfer32 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */ - kDMA_EdgeBurstTransfer64 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */ - kDMA_EdgeBurstTransfer128 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */ - kDMA_EdgeBurstTransfer256 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */ - kDMA_EdgeBurstTransfer512 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */ - kDMA_EdgeBurstTransfer1024 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */ -} dma_trigger_burst_t; - -/*! @brief DMA burst wrapping */ -typedef enum _dma_burst_wrap -{ - kDMA_NoWrap = 0, /*!< Wrapping is disabled */ - kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */ - kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */ - kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | - DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */ -} dma_burst_wrap_t; - -/*! @brief DMA transfer type */ -typedef enum _dma_transfer_type -{ - kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */ - kDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory (increment only destination) */ - kDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral (increment only source)*/ - kDMA_StaticToStatic, /*!< Peripheral to static memory (do not increment source or destination) */ -} dma_transfer_type_t; - -/*! @brief DMA channel trigger */ -typedef struct _dma_channel_trigger -{ - dma_trigger_type_t type; /*!< Select hardware trigger as edge triggered or level triggered. */ - dma_trigger_burst_t burst; /*!< Select whether hardware triggers cause a single or burst transfer. */ - dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */ -} dma_channel_trigger_t; - -/*! @brief DMA transfer status */ -enum _dma_transfer_status -{ - kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the - transfer request. */ -}; - -/*! @brief DMA transfer configuration */ -typedef struct _dma_transfer_config -{ - uint8_t *srcAddr; /*!< Source data address */ - uint8_t *dstAddr; /*!< Destination data address */ - uint8_t *nextDesc; /*!< Chain custom descriptor */ - dma_xfercfg_t xfercfg; /*!< Transfer options */ - bool isPeriph; /*!< DMA transfer is driven by peripheral */ -} dma_transfer_config_t; - -/*! @brief Callback for DMA */ -struct _dma_handle; - -/*! @brief Define Callback function for DMA. */ -typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode); - -/*! @brief DMA transfer handle structure */ -typedef struct _dma_handle -{ - dma_callback callback; /*!< Callback function. Invoked when transfer - of descriptor with interrupt flag finishes */ - void *userData; /*!< Callback function parameter */ - DMA_Type *base; /*!< DMA peripheral base address */ - uint8_t channel; /*!< DMA channel number */ -} dma_handle_t; - -/******************************************************************************* - * APIs - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name DMA initialization and De-initialization - * @{ - */ - -/*! - * @brief Initializes DMA peripheral. - * - * This function enable the DMA clock, set descriptor table and - * enable DMA peripheral. - * - * @param base DMA peripheral base address. - */ -void DMA_Init(DMA_Type *base); - -/*! - * @brief Deinitializes DMA peripheral. - * - * This function gates the DMA clock. - * - * @param base DMA peripheral base address. - */ -void DMA_Deinit(DMA_Type *base); - -/* @} */ -/*! - * @name DMA Channel Operation - * @{ - */ - -/*! -* @brief Return whether DMA channel is processing transfer -* -* @param base DMA peripheral base address. -* @param channel DMA channel number. -* @return True for active state, false otherwise. -*/ -static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - return (DMA_COMMON_CONST_REG_GET(base, channel, ACTIVE) & (1U << DMA_CHANNEL_INDEX(channel))) ? true : false; -} - -/*! - * @brief Enables the interrupt source for the DMA transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - DMA_COMMON_REG_GET(base, channel, INTENSET) |= 1U << DMA_CHANNEL_INDEX(channel); -} - -/*! - * @brief Disables the interrupt source for the DMA transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - DMA_COMMON_REG_GET(base, channel, INTENCLR) |= 1U << DMA_CHANNEL_INDEX(channel); -} - -/*! - * @brief Enable DMA channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - DMA_COMMON_REG_GET(base, channel, ENABLESET) |= 1U << DMA_CHANNEL_INDEX(channel); -} - -/*! - * @brief Disable DMA channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - DMA_COMMON_REG_GET(base, channel, ENABLECLR) |= 1U << DMA_CHANNEL_INDEX(channel); -} - -/*! - * @brief Set PERIPHREQEN of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK; -} - -/*! - * @brief Get PERIPHREQEN value of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return True for enabled PeriphRq, false for disabled. - */ -static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK; -} - -/*! - * @brief Set trigger settings of DMA channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param trigger trigger configuration. - */ -void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger); - -/*! - * @brief Gets the remaining bytes of the current DMA descriptor transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return The number of bytes which have not been transferred yet. - */ -uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel); - -/*! - * @brief Set priority of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param priority Channel priority value. - */ -static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - base->CHANNEL[channel].CFG = - (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority); -} - -/*! - * @brief Get priority of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return Channel priority value. - */ -static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> - DMA_CHANNEL_CFG_CHPRIORITY_SHIFT); -} - -/*! - * @brief Create application specific DMA descriptor - * to be used in a chain in transfer - * - * @param desc DMA descriptor address. - * @param xfercfg Transfer configuration for DMA descriptor. - * @param srcAddr Address of last item to transmit - * @param dstAddr Address of last item to receive. - * @param nextDesc Address of next descriptor in chain. - */ -void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc); - -/* @} */ - -/*! - * @name DMA Transactional Operation - * @{ - */ - -/*! - * @brief Abort running transfer by handle. - * - * This function aborts DMA transfer specified by handle. - * - * @param handle DMA handle pointer. - */ -void DMA_AbortTransfer(dma_handle_t *handle); - -/*! - * @brief Creates the DMA handle. - * - * This function is called if using transaction API for DMA. This function - * initializes the internal state of DMA handle. - * - * @param handle DMA handle pointer. The DMA handle stores callback function and - * parameters. - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel); - -/*! - * @brief Installs a callback function for the DMA transfer. - * - * This callback is called in DMA IRQ handler. Use the callback to do something after - * the current major loop transfer completes. - * - * @param handle DMA handle pointer. - * @param callback DMA callback function pointer. - * @param userData Parameter for callback function. - */ -void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData); - -/*! - * @brief Prepares the DMA transfer structure. - * - * This function prepares the transfer configuration structure according to the user input. - * - * @param config The user configuration structure of type dma_transfer_t. - * @param srcAddr DMA transfer source address. - * @param dstAddr DMA transfer destination address. - * @param byteWidth DMA transfer destination address width(bytes). - * @param transferBytes DMA transfer bytes to be transferred. - * @param type DMA transfer type. - * @param nextDesc Chain custom descriptor to transfer. - * @note The data address and the data width must be consistent. For example, if the SRC - * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in - * source address error(SAE). - */ -void DMA_PrepareTransfer(dma_transfer_config_t *config, - void *srcAddr, - void *dstAddr, - uint32_t byteWidth, - uint32_t transferBytes, - dma_transfer_type_t type, - void *nextDesc); - -/*! - * @brief Submits the DMA transfer request. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * - * @param handle DMA handle pointer. - * @param config Pointer to DMA transfer configuration structure. - * @retval kStatus_DMA_Success It means submit transfer request succeed. - * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config); - -/*! - * @brief DMA start transfer. - * - * This function enables the channel request. User can call this function after submitting the transfer request - * or before submitting the transfer request. - * - * @param handle DMA handle pointer. - */ -void DMA_StartTransfer(dma_handle_t *handle); - -/*! - * @brief DMA IRQ handler for descriptor transfer complete. - * - * This function clears the channel major interrupt flag and call - * the callback function if it is not NULL. - */ -void DMA_HandleIRQ(void); - -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/* @} */ - -#endif /*_FSL_DMA_H_*/ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic.c deleted file mode 100644 index d9cb1a4edca..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_dmic.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.dmic" -#endif - - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* Array of DMIC peripheral base address. */ -static DMIC_Type *const s_dmicBases[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_BASE_PTRS; - -/* Array of DMIC clock name. */ -static const clock_ip_name_t s_dmicClock[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_CLOCKS; - -/* Array of DMIC IRQ number. */ -static const IRQn_Type s_dmicIRQ[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_IRQS; - -/*! @brief Callback function array for DMIC(s). */ -static dmic_callback_t s_dmicCallback[FSL_FEATURE_SOC_DMIC_COUNT]; - -/* Array of HWVAD IRQ number. */ -static const IRQn_Type s_dmicHwvadIRQ[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_HWVAD_IRQS; - -/*! @brief Callback function array for HWVAD(s). */ -static dmic_hwvad_callback_t s_dmicHwvadCallback[FSL_FEATURE_SOC_DMIC_COUNT]; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get the DMIC instance from peripheral base address. - * - * @param base DMIC peripheral base address. - * @return DMIC instance. - */ -uint32_t DMIC_GetInstance(DMIC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_dmicBases); instance++) - { - if (s_dmicBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_dmicBases)); - - return instance; -} - -void DMIC_Init(DMIC_Type *base) -{ - assert(base); - - /* Enable the clock to the register interface */ - CLOCK_EnableClock(s_dmicClock[DMIC_GetInstance(base)]); - - /* Reset the peripheral */ - RESET_PeripheralReset(kDMIC_RST_SHIFT_RSTn); - - /* Disable DMA request*/ - base->CHANNEL[0].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_DMAEN(1); - base->CHANNEL[1].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_DMAEN(1); - - /* Disable DMIC interrupt. */ - base->CHANNEL[0].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN(1); - base->CHANNEL[1].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN(1); -} - -void DMIC_DeInit(DMIC_Type *base) -{ - assert(base); - /* Disable the clock to the register interface */ - CLOCK_DisableClock(s_dmicClock[DMIC_GetInstance(base)]); -} - -void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config) -{ - base->IOCFG = config; -} - -void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode) -{ - if (mode == kDMIC_OperationModeInterrupt) - { - /* Enable DMIC interrupt. */ - base->CHANNEL[0].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN(1); - base->CHANNEL[1].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN(1); - } - if (mode == kDMIC_OperationModeDma) - { - /* enable DMA request*/ - base->CHANNEL[0].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN(1); - base->CHANNEL[1].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN(1); - } -} - -void DMIC_ConfigChannel(DMIC_Type *base, - dmic_channel_t channel, - stereo_side_t side, - dmic_channel_config_t *channel_config) -{ - base->CHANNEL[channel].DIVHFCLK = channel_config->divhfclk; - base->CHANNEL[channel].OSR = channel_config->osr; - base->CHANNEL[channel].GAINSHIFT = channel_config->gainshft; - base->CHANNEL[channel].PREAC2FSCOEF = channel_config->preac2coef; - base->CHANNEL[channel].PREAC4FSCOEF = channel_config->preac4coef; - base->CHANNEL[channel].PHY_CTRL = - DMIC_CHANNEL_PHY_CTRL_PHY_FALL(side) | DMIC_CHANNEL_PHY_CTRL_PHY_HALF(channel_config->sample_rate); - base->CHANNEL[channel].DC_CTRL = DMIC_CHANNEL_DC_CTRL_DCPOLE(channel_config->dc_cut_level) | - DMIC_CHANNEL_DC_CTRL_DCGAIN(channel_config->post_dc_gain_reduce) | - DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(channel_config->saturate16bit); -} - -void DMIC_CfgChannelDc(DMIC_Type *base, - dmic_channel_t channel, - dc_removal_t dc_cut_level, - uint32_t post_dc_gain_reduce, - bool saturate16bit) -{ - base->CHANNEL[channel].DC_CTRL = DMIC_CHANNEL_DC_CTRL_DCPOLE(dc_cut_level) | - DMIC_CHANNEL_DC_CTRL_DCGAIN(post_dc_gain_reduce) | - DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(saturate16bit); -} - -void DMIC_Use2fs(DMIC_Type *base, bool use2fs) -{ - base->USE2FS = (use2fs) ? 0x1 : 0x0; -} - -void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask) -{ - base->CHANEN = channelmask; -} - -void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn) -{ - base->CHANNEL[channel].FIFO_CTRL |= - (base->CHANNEL[channel].FIFO_CTRL & (DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK | DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)) | - DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(trig_level) | DMIC_CHANNEL_FIFO_CTRL_ENABLE(enable) | - DMIC_CHANNEL_FIFO_CTRL_RESETN(resetn); -} - -void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb) -{ - uint32_t instance; - - instance = DMIC_GetInstance(base); - NVIC_ClearPendingIRQ(s_dmicIRQ[instance]); - /* Save callback pointer */ - s_dmicCallback[instance] = cb; - EnableIRQ(s_dmicIRQ[instance]); -} - -void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb) -{ - uint32_t instance; - - instance = DMIC_GetInstance(base); - DisableIRQ(s_dmicIRQ[instance]); - s_dmicCallback[instance] = NULL; - NVIC_ClearPendingIRQ(s_dmicIRQ[instance]); -} - -void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb) -{ - uint32_t instance; - - instance = DMIC_GetInstance(base); - NVIC_ClearPendingIRQ(s_dmicHwvadIRQ[instance]); - /* Save callback pointer */ - s_dmicHwvadCallback[instance] = vadcb; - EnableIRQ(s_dmicHwvadIRQ[instance]); -} - -void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb) -{ - uint32_t instance; - - instance = DMIC_GetInstance(base); - DisableIRQ(s_dmicHwvadIRQ[instance]); - s_dmicHwvadCallback[instance] = NULL; - NVIC_ClearPendingIRQ(s_dmicHwvadIRQ[instance]); -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(DMIC0) -/*DMIC0 IRQ handler */ -void DMIC0_DriverIRQHandler(void) -{ - if (s_dmicCallback[0] != NULL) - { - s_dmicCallback[0](); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -/*DMIC0 HWVAD IRQ handler */ -void HWVAD0_DriverIRQHandler(void) -{ - if (s_dmicHwvadCallback[0] != NULL) - { - s_dmicHwvadCallback[0](); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic.h deleted file mode 100644 index 575d17cfe6a..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic.h +++ /dev/null @@ -1,457 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_DMIC_H_ -#define _FSL_DMIC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup dmic_driver - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @name DMIC version - * @{ - */ - -/*! @brief DMIC driver version 2.0.0. */ -#define FSL_DMIC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @brief DMIC different operation modes. */ -typedef enum _operation_mode -{ - kDMIC_OperationModePoll = 0U, /*!< Polling mode */ - kDMIC_OperationModeInterrupt = 1U, /*!< Interrupt mode */ - kDMIC_OperationModeDma = 2U, /*!< DMA mode */ -} operation_mode_t; - -/*! @brief DMIC left/right values. */ -typedef enum _stereo_side -{ - kDMIC_Left = 0U, /*!< Left Stereo channel */ - kDMIC_Right = 1U, /*!< Right Stereo channel */ -} stereo_side_t; - -/*! @brief DMIC Clock pre-divider values. */ -typedef enum -{ - kDMIC_PdmDiv1 = 0U, /*!< DMIC pre-divider set in divide by 1 */ - kDMIC_PdmDiv2 = 1U, /*!< DMIC pre-divider set in divide by 2 */ - kDMIC_PdmDiv3 = 2U, /*!< DMIC pre-divider set in divide by 3 */ - kDMIC_PdmDiv4 = 3U, /*!< DMIC pre-divider set in divide by 4 */ - kDMIC_PdmDiv6 = 4U, /*!< DMIC pre-divider set in divide by 6 */ - kDMIC_PdmDiv8 = 5U, /*!< DMIC pre-divider set in divide by 8 */ - kDMIC_PdmDiv12 = 6U, /*!< DMIC pre-divider set in divide by 12 */ - kDMIC_PdmDiv16 = 7U, /*!< DMIC pre-divider set in divide by 16*/ - kDMIC_PdmDiv24 = 8U, /*!< DMIC pre-divider set in divide by 24*/ - kDMIC_PdmDiv32 = 9U, /*!< DMIC pre-divider set in divide by 32 */ - kDMIC_PdmDiv48 = 10U, /*!< DMIC pre-divider set in divide by 48 */ - kDMIC_PdmDiv64 = 11U, /*!< DMIC pre-divider set in divide by 64*/ - kDMIC_PdmDiv96 = 12U, /*!< DMIC pre-divider set in divide by 96*/ - kDMIC_PdmDiv128 = 13U, /*!< DMIC pre-divider set in divide by 128 */ -} pdm_div_t; - -/*! @brief Pre-emphasis Filter coefficient value for 2FS and 4FS modes. */ -typedef enum _compensation -{ - kDMIC_CompValueZero = 0U, /*!< Compensation 0 */ - kDMIC_CompValueNegativePoint16 = 1U, /*!< Compensation -0.16 */ - kDMIC_CompValueNegativePoint15 = 2U, /*!< Compensation -0.15 */ - kDMIC_CompValueNegativePoint13 = 3U, /*!< Compensation -0.13 */ -} compensation_t; - -/*! @brief DMIC DC filter control values. */ -typedef enum _dc_removal -{ - kDMIC_DcNoRemove = 0U, /*!< Flat response no filter */ - kDMIC_DcCut155 = 1U, /*!< Cut off Frequency is 155 Hz */ - kDMIC_DcCut78 = 2U, /*!< Cut off Frequency is 78 Hz */ - kDMIC_DcCut39 = 3U, /*!< Cut off Frequency is 39 Hz */ -} dc_removal_t; - -/*! @brief DMIC IO configiration. */ -typedef enum _dmic_io -{ - kDMIC_PdmDual = 0U, /*!< Two separate pairs of PDM wires */ - kDMIC_PdmStereo = 4U, /*!< Stereo Mic */ - kDMIC_PdmBypass = 3U, /*!< Clk Bypass clocks both channels */ - kDMIC_PdmBypassClk0 = 1U, /*!< Clk Bypass clocks only channel0 */ - kDMIC_PdmBypassClk1 = 2U, /*!< Clk Bypas clocks only channel1 */ -} dmic_io_t; - -/*! @brief DMIC Channel number. */ -typedef enum _dmic_channel -{ - kDMIC_Channel0 = 0U, /*!< DMIC channel 0 */ - kDMIC_Channel1 = 1U, /*!< DMIC channel 1 */ -} dmic_channel_t; - -/*! @brief DMIC and decimator sample rates. */ -typedef enum _dmic_phy_sample_rate -{ - kDMIC_PhyFullSpeed = 0U, /*!< Decimator gets one sample per each chosen clock edge of PDM interface */ - kDMIC_PhyHalfSpeed = 1U, /*!< PDM clock to Microphone is halved, decimator receives each sample twice */ -} dmic_phy_sample_rate_t; - -/*! @brief DMIC transfer status.*/ -enum _dmic_status -{ - kStatus_DMIC_Busy = MAKE_STATUS(kStatusGroup_DMIC, 0), /*!< DMIC is busy */ - kStatus_DMIC_Idle = MAKE_STATUS(kStatusGroup_DMIC, 1), /*!< DMIC is idle */ - kStatus_DMIC_OverRunError = MAKE_STATUS(kStatusGroup_DMIC, 2), /*!< DMIC over run Error */ - kStatus_DMIC_UnderRunError = MAKE_STATUS(kStatusGroup_DMIC, 3), /*!< DMIC under run Error */ -}; - -/*! @brief DMIC Channel configuration structure. */ -typedef struct _dmic_channel_config -{ - pdm_div_t divhfclk; /*!< DMIC Clock pre-divider values */ - uint32_t osr; /*!< oversampling rate(CIC decimation rate) for PCM */ - int32_t gainshft; /*!< 4FS PCM data gain control */ - compensation_t preac2coef; /*!< Pre-emphasis Filter coefficient value for 2FS */ - compensation_t preac4coef; /*!< Pre-emphasis Filter coefficient value for 4FS */ - dc_removal_t dc_cut_level; /*!< DMIC DC filter control values. */ - uint32_t post_dc_gain_reduce; /*!< Fine gain adjustment in the form of a number of bits to downshift */ - dmic_phy_sample_rate_t sample_rate; /*!< DMIC and decimator sample rates */ - bool saturate16bit; /*!< Selects 16-bit saturation. 0 means results roll over if out range and do not saturate. - 1 means if the result overflows, it saturates at 0xFFFF for positive overflow and - 0x8000 for negative overflow.*/ -} dmic_channel_config_t; - -/*! @brief DMIC Callback function. */ -typedef void (*dmic_callback_t)(void); - -/*! @brief HWVAD Callback function. */ -typedef void (*dmic_hwvad_callback_t)(void); - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * API - ******************************************************************************/ -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @brief Get the DMIC instance from peripheral base address. - * - * @param base DMIC peripheral base address. - * @return DMIC instance. - */ -uint32_t DMIC_GetInstance(DMIC_Type *base); - -/*! - * @brief Turns DMIC Clock on - * @param base : DMIC base - * @return Nothing - */ -void DMIC_Init(DMIC_Type *base); - -/*! - * @brief Turns DMIC Clock off - * @param base : DMIC base - * @return Nothing - */ -void DMIC_DeInit(DMIC_Type *base); - -/*! - * @brief Configure DMIC io - * @param base : The base address of DMIC interface - * @param config : DMIC io configuration - * @return Nothing - */ -void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config); - -/*! - * @brief Set DMIC operating mode - * @param base : The base address of DMIC interface - * @param mode : DMIC mode - * @return Nothing - */ -void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode); - -/*! - * @brief Configure DMIC channel - * @param base : The base address of DMIC interface - * @param channel : DMIC channel - * @param side : stereo_side_t, choice of left or right - * @param channel_config : Channel configuration - * @return Nothing - */ -void DMIC_ConfigChannel(DMIC_Type *base, - dmic_channel_t channel, - stereo_side_t side, - dmic_channel_config_t *channel_config); - -/*! - * @brief Configure DMIC channel - * @param base : The base address of DMIC interface - * @param channel : DMIC channel - * @param dc_cut_level : dc_removal_t, Cut off Frequency - * @param post_dc_gain_reduce : Fine gain adjustment in the form of a number of bits to downshift. - * @param saturate16bit : If selects 16-bit saturation. - */ -void DMIC_CfgChannelDc(DMIC_Type *base, - dmic_channel_t channel, - dc_removal_t dc_cut_level, - uint32_t post_dc_gain_reduce, - bool saturate16bit); - -/*! - * @brief Configure Clock scaling - * @param base : The base address of DMIC interface - * @param use2fs : clock scaling - * @return Nothing - */ -void DMIC_Use2fs(DMIC_Type *base, bool use2fs); - -/*! - * @brief Enable a particualr channel - * @param base : The base address of DMIC interface - * @param channelmask : Channel selection - * @return Nothing - */ -void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask); - -/*! - * @brief Configure fifo settings for DMIC channel - * @param base : The base address of DMIC interface - * @param channel : DMIC channel - * @param trig_level : FIFO trigger level - * @param enable : FIFO level - * @param resetn : FIFO reset - * @return Nothing - */ -void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn); - -/*! - * @brief Get FIFO status - * @param base : The base address of DMIC interface - * @param channel : DMIC channel - * @return FIFO status - */ -static inline uint32_t DMIC_FifoGetStatus(DMIC_Type *base, uint32_t channel) -{ - return base->CHANNEL[channel].FIFO_STATUS; -} - -/*! - * @brief Clear FIFO status - * @param base : The base address of DMIC interface - * @param channel : DMIC channel - * @param mask : Bits to be cleared - * @return FIFO status - */ -static inline void DMIC_FifoClearStatus(DMIC_Type *base, uint32_t channel, uint32_t mask) -{ - base->CHANNEL[channel].FIFO_STATUS = mask; -} - -/*! - * @brief Get FIFO data - * @param base : The base address of DMIC interface - * @param channel : DMIC channel - * @return FIFO data - */ -static inline uint32_t DMIC_FifoGetData(DMIC_Type *base, uint32_t channel) -{ - return base->CHANNEL[channel].FIFO_DATA; -} - -/*! - * @brief Enable callback. - - * This function enables the interrupt for the selected DMIC peripheral. - * The callback function is not enabled until this function is called. - * - * @param base Base address of the DMIC peripheral. - * @param cb callback Pointer to store callback function. - * @retval None. - */ -void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb); - -/*! - * @brief Disable callback. - - * This function disables the interrupt for the selected DMIC peripheral. - * - * @param base Base address of the DMIC peripheral. - * @param cb callback Pointer to store callback function.. - * @retval None. - */ -void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb); - -/** - * @} - */ - -/*! - * @name hwvad - * @{ - */ - -/*! - * @brief Sets the gain value for the noise estimator. - * - * @param base DMIC base pointer - * @param value gain value for the noise estimator. - * @retval None. - */ -static inline void DMIC_SetGainNoiseEstHwvad(DMIC_Type *base, uint32_t value) -{ - assert(NULL != base); - base->HWVADTHGN = value & 0xFu; -} - -/*! - * @brief Sets the gain value for the signal estimator. - * - * @param base DMIC base pointer - * @param value gain value for the signal estimator. - * @retval None. - */ -static inline void DMIC_SetGainSignalEstHwvad(DMIC_Type *base, uint32_t value) -{ - assert(NULL != base); - base->HWVADTHGS = value & 0xFu; -} - -/*! - * @brief Sets the hwvad filter cutoff frequency parameter. - * - * @param base DMIC base pointer - * @param value cut off frequency value. - * @retval None. - */ -static inline void DMIC_SetFilterCtrlHwvad(DMIC_Type *base, uint32_t value) -{ - assert(NULL != base); - base->HWVADHPFS = value & 0x3u; -} - -/*! - * @brief Sets the input gain of hwvad. - * - * @param base DMIC base pointer - * @param value input gain value for hwvad. - * @retval None. - */ -static inline void DMIC_SetInputGainHwvad(DMIC_Type *base, uint32_t value) -{ - assert(NULL != base); - base->HWVADGAIN = value & 0xFu; -} - -/*! - * @brief Clears hwvad internal interrupt flag. - * - * @param base DMIC base pointer - * @param st10 bit value. - * @retval None. - */ -static inline void DMIC_CtrlClrIntrHwvad(DMIC_Type *base, bool st10) -{ - assert(NULL != base); - base->HWVADST10 = (st10) ? 0x1 : 0x0; -} - -/*! - * @brief Resets hwvad filters. - * - * @param base DMIC base pointer - * @param rstt Reset bit value. - * @retval None. - */ -static inline void DMIC_FilterResetHwvad(DMIC_Type *base, bool rstt) -{ - assert(NULL != base); - base->HWVADRSTT = (rstt) ? 0x1 : 0x0; -} - -/*! - * @brief Gets the value from output of the filter z7. - * - * @param base DMIC base pointer - * @retval output of filter z7. - */ -static inline uint16_t DMIC_GetNoiseEnvlpEst(DMIC_Type *base) -{ - assert(NULL != base); - return (base->HWVADLOWZ & 0xFFFFu); -} - -/*! - * @brief Enable hwvad callback. - - * This function enables the hwvad interrupt for the selected DMIC peripheral. - * The callback function is not enabled until this function is called. - * - * @param base Base address of the DMIC peripheral. - * @param vadcb callback Pointer to store callback function. - * @retval None. - */ -void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb); - -/*! - * @brief Disable callback. - - * This function disables the hwvad interrupt for the selected DMIC peripheral. - * - * @param base Base address of the DMIC peripheral. - * @param vadcb callback Pointer to store callback function.. - * @retval None. - */ -void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb); - -/*! @} */ - -#ifdef __cplusplus -} -#endif - -/*! @}*/ - -#endif /* __FSL_DMIC_H */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic_dma.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic_dma.c deleted file mode 100644 index d1505dd9423..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic_dma.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_dmic_dma.h" -#include "fsl_dmic.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.dmic_dma" -#endif - -#define DMIC_HANDLE_ARRAY_SIZE 1 - -/*handle->state = kDMIC_Idle; - - if (dmicPrivateHandle->handle->callback) - { - dmicPrivateHandle->handle->callback(dmicPrivateHandle->base, dmicPrivateHandle->handle, kStatus_DMIC_Idle, - dmicPrivateHandle->handle->userData); - } -} - -status_t DMIC_TransferCreateHandleDMA(DMIC_Type *base, - dmic_dma_handle_t *handle, - dmic_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *rxDmaHandle) -{ - int32_t instance = 0; - - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } - /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - /* check DMIC instance by 'base'*/ - instance = DMIC_GetInstance(base); - assert(!(instance < 0)); - if (instance < 0) - { - return kStatus_InvalidArgument; - } - - memset(handle, 0, sizeof(*handle)); - /* assign 'base' and 'handle' */ - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - handle->callback = callback; - handle->userData = userData; - - handle->rxDmaHandle = rxDmaHandle; - - /* Set DMIC state to idle */ - handle->state = kDMIC_Idle; - /* Configure RX. */ - if (rxDmaHandle) - { - DMA_SetCallback(rxDmaHandle, DMIC_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]); - } - - return kStatus_Success; -} - -status_t DMIC_TransferReceiveDMA(DMIC_Type *base, - dmic_dma_handle_t *handle, - dmic_transfer_t *xfer, - uint32_t dmic_channel) -{ - assert(handle); - assert(handle->rxDmaHandle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - dma_transfer_config_t xferConfig; - status_t status; - uint32_t srcAddr = (uint32_t)(&base->CHANNEL[dmic_channel].FIFO_DATA); - - /* Check if the device is busy. If previous RX not finished.*/ - if (handle->state == kDMIC_Busy) - { - status = kStatus_DMIC_Busy; - } - else - { - handle->state = kDMIC_Busy; - handle->transferSize = xfer->dataSize; - - /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, (void *)srcAddr, xfer->data, sizeof(uint16_t), - xfer->dataSize, kDMA_PeripheralToMemory, NULL); - - /* Submit transfer. */ - DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); - - DMA_StartTransfer(handle->rxDmaHandle); - - status = kStatus_Success; - } - return status; -} - -void DMIC_TransferAbortReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle) -{ - assert(NULL != handle); - assert(NULL != handle->rxDmaHandle); - - /* Stop transfer. */ - DMA_AbortTransfer(handle->rxDmaHandle); - handle->state = kDMIC_Idle; -} - -status_t DMIC_TransferGetReceiveCountDMA(DMIC_Type *base, dmic_dma_handle_t *handle, uint32_t *count) -{ - assert(handle); - assert(handle->rxDmaHandle); - assert(count); - - if (kDMIC_Idle == handle->state) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->transferSize - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); - - return kStatus_Success; -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic_dma.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic_dma.h deleted file mode 100644 index 5ba15107fc4..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic_dma.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_DMIC_DMA_H_ -#define _FSL_DMIC_DMA_H_ - -#include "fsl_common.h" -#include "fsl_dma.h" - -/*! - * @addtogroup dmic_dma_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @name DMIC DMA version - * @{ - */ - -/*! @brief DMIC DMA driver version 2.0.0. */ -#define FSL_DMIC_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @brief DMIC transfer structure. */ -typedef struct _dmic_transfer -{ - uint16_t *data; /*!< The buffer of data to be transfer.*/ - size_t dataSize; /*!< The byte count to be transfer. */ -} dmic_transfer_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _dmic_dma_handle dmic_dma_handle_t; - -/*! @brief DMIC transfer callback function. */ -typedef void (*dmic_dma_transfer_callback_t)(DMIC_Type *base, - dmic_dma_handle_t *handle, - status_t status, - void *userData); - -/*! -* @brief DMIC DMA handle -*/ -struct _dmic_dma_handle -{ - DMIC_Type *base; /*!< DMIC peripheral base address. */ - dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ - dmic_dma_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< DMIC callback function parameter.*/ - size_t transferSize; /*!< Size of the data to receive. */ - volatile uint8_t state; /*!< Internal state of DMIC DMA transfer */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name DMA transactional - * @{ - */ - -/*! - * @brief Initializes the DMIC handle which is used in transactional functions. - * @param base DMIC peripheral base address. - * @param handle Pointer to dmic_dma_handle_t structure. - * @param callback Callback function. - * @param userData User data. - * @param rxDmaHandle User-requested DMA handle for RX DMA transfer. - */ -status_t DMIC_TransferCreateHandleDMA(DMIC_Type *base, - dmic_dma_handle_t *handle, - dmic_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *rxDmaHandle); - -/*! - * @brief Receives data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * @param base USART peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param xfer DMIC DMA transfer structure. See #dmic_transfer_t. - * @param dmic_channel DMIC channel - * @retval kStatus_Success - */ -status_t DMIC_TransferReceiveDMA(DMIC_Type *base, - dmic_dma_handle_t *handle, - dmic_transfer_t *xfer, - uint32_t dmic_channel); - -/*! - * @brief Aborts the received data using DMA. - * - * This function aborts the received data using DMA. - * - * @param base DMIC peripheral base address - * @param handle Pointer to dmic_dma_handle_t structure - */ -void DMIC_TransferAbortReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base DMIC peripheral base address. - * @param handle DMIC handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter count; - */ -status_t DMIC_TransferGetReceiveCountDMA(DMIC_Type *base, dmic_dma_handle_t *handle, uint32_t *count); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_DMIC_DMA_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flashiap.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flashiap.c deleted file mode 100644 index 62fbdd85ab4..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flashiap.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_flashiap.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flashiap" -#endif - - -#define HZ_TO_KHZ_DIV 1000 - -/******************************************************************************* - * Code - ******************************************************************************/ - -static status_t translate_iap_status(uint32_t status) -{ - /* Translate IAP return code to sdk status code */ - if (status == kStatus_Success) - { - return status; - } - else - { - return MAKE_STATUS(kStatusGroup_FLASHIAP, status); - } -} - -status_t FLASHIAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector) -{ - uint32_t command[5], result[4]; - - command[0] = kIapCmd_FLASHIAP_PrepareSectorforWrite; - command[1] = startSector; - command[2] = endSector; - iap_entry(command, result); - - return translate_iap_status(result[0]); -} - -status_t FLASHIAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock) -{ - uint32_t command[5], result[4]; - - command[0] = kIapCmd_FLASHIAP_CopyRamToFlash; - command[1] = dstAddr; - command[2] = (uint32_t)srcAddr; - command[3] = numOfBytes; - command[4] = systemCoreClock / HZ_TO_KHZ_DIV; - iap_entry(command, result); - - return translate_iap_status(result[0]); -} - -status_t FLASHIAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock) -{ - uint32_t command[5], result[4]; - - command[0] = kIapCmd_FLASHIAP_EraseSector; - command[1] = startSector; - command[2] = endSector; - command[3] = systemCoreClock / HZ_TO_KHZ_DIV; - iap_entry(command, result); - - return translate_iap_status(result[0]); -} - -status_t FLASHIAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t systemCoreClock) -{ - uint32_t command[5], result[4]; - - command[0] = kIapCmd_FLASHIAP_ErasePage; - command[1] = startPage; - command[2] = endPage; - command[3] = systemCoreClock / HZ_TO_KHZ_DIV; - iap_entry(command, result); - - return translate_iap_status(result[0]); -} - -status_t FLASHIAP_BlankCheckSector(uint32_t startSector, uint32_t endSector) -{ - uint32_t command[5], result[4]; - - command[0] = kIapCmd_FLASHIAP_BlankCheckSector; - command[1] = startSector; - command[2] = endSector; - iap_entry(command, result); - - return translate_iap_status(result[0]); -} - -status_t FLASHIAP_Compare(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes) -{ - uint32_t command[5], result[4]; - - command[0] = kIapCmd_FLASHIAP_Compare; - command[1] = dstAddr; - command[2] = (uint32_t)srcAddr; - command[3] = numOfBytes; - iap_entry(command, result); - - return translate_iap_status(result[0]); -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flashiap.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flashiap.h deleted file mode 100644 index 113db1f11f5..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flashiap.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_FLASHIAP_H_ -#define _FSL_FLASHIAP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup flashiap_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_FLASHIAP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ - /*@}*/ - -/*! - * @brief Flashiap status codes. - */ -enum _flashiap_status -{ - kStatus_FLASHIAP_Success = kStatus_Success, /*!< Api is executed successfully */ - kStatus_FLASHIAP_InvalidCommand = MAKE_STATUS(kStatusGroup_FLASHIAP, 1U), /*!< Invalid command */ - kStatus_FLASHIAP_SrcAddrError = - MAKE_STATUS(kStatusGroup_FLASHIAP, 2U), /*!< Source address is not on word boundary */ - kStatus_FLASHIAP_DstAddrError = - MAKE_STATUS(kStatusGroup_FLASHIAP, 3U), /*!< Destination address is not on a correct boundary */ - kStatus_FLASHIAP_SrcAddrNotMapped = - MAKE_STATUS(kStatusGroup_FLASHIAP, 4U), /*!< Source address is not mapped in the memory map */ - kStatus_FLASHIAP_DstAddrNotMapped = - MAKE_STATUS(kStatusGroup_FLASHIAP, 5U), /*!< Destination address is not mapped in the memory map */ - kStatus_FLASHIAP_CountError = - MAKE_STATUS(kStatusGroup_FLASHIAP, 6U), /*!< Byte count is not multiple of 4 or is not a permitted value */ - kStatus_FLASHIAP_InvalidSector = - MAKE_STATUS(kStatusGroup_FLASHIAP, - 7), /*!< Sector number is invalid or end sector number is greater than start sector number */ - kStatus_FLASHIAP_SectorNotblank = MAKE_STATUS(kStatusGroup_FLASHIAP, 8U), /*!< One or more sectors are not blank */ - kStatus_FLASHIAP_NotPrepared = - MAKE_STATUS(kStatusGroup_FLASHIAP, 9U), /*!< Command to prepare sector for write operation was not executed */ - kStatus_FLASHIAP_CompareError = - MAKE_STATUS(kStatusGroup_FLASHIAP, 10U), /*!< Destination and source memory contents do not match */ - kStatus_FLASHIAP_Busy = - MAKE_STATUS(kStatusGroup_FLASHIAP, 11U), /*!< Flash programming hardware interface is busy */ - kStatus_FLASHIAP_ParamError = - MAKE_STATUS(kStatusGroup_FLASHIAP, 12U), /*!< Insufficient number of parameters or invalid parameter */ - kStatus_FLASHIAP_AddrError = MAKE_STATUS(kStatusGroup_FLASHIAP, 13U), /*!< Address is not on word boundary */ - kStatus_FLASHIAP_AddrNotMapped = - MAKE_STATUS(kStatusGroup_FLASHIAP, 14U), /*!< Address is not mapped in the memory map */ - kStatus_FLASHIAP_NoPower = MAKE_STATUS(kStatusGroup_FLASHIAP, 24U), /*!< Flash memory block is powered down */ - kStatus_FLASHIAP_NoClock = - MAKE_STATUS(kStatusGroup_FLASHIAP, 27U), /*!< Flash memory block or controller is not clocked */ -}; - -/*! - * @brief Flashiap command codes. - */ -enum _flashiap_commands -{ - kIapCmd_FLASHIAP_PrepareSectorforWrite = 50U, /*!< Prepare Sector for write */ - kIapCmd_FLASHIAP_CopyRamToFlash = 51U, /*!< Copy RAM to flash */ - kIapCmd_FLASHIAP_EraseSector = 52U, /*!< Erase Sector */ - kIapCmd_FLASHIAP_BlankCheckSector = 53U, /*!< Blank check sector */ - kIapCmd_FLASHIAP_ReadPartId = 54U, /*!< Read part id */ - kIapCmd_FLASHIAP_Read_BootromVersion = 55U, /*!< Read bootrom version */ - kIapCmd_FLASHIAP_Compare = 56U, /*!< Compare */ - kIapCmd_FLASHIAP_ReinvokeISP = 57U, /*!< Reinvoke ISP */ - kIapCmd_FLASHIAP_ReadUid = 58U, /*!< Read Uid isp */ - kIapCmd_FLASHIAP_ErasePage = 59U, /*!< Erase Page */ - kIapCmd_FLASHIAP_ReadMisr = 70U, /*!< Read Misr */ - kIapCmd_FLASHIAP_ReinvokeI2cSpiISP = 71U /*!< Reinvoke I2C/SPI isp */ -}; - -/*! @brief IAP_ENTRY API function type */ -typedef void (*IAP_ENTRY_T)(uint32_t cmd[5], uint32_t stat[4]); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief IAP_ENTRY API function type - * - * Wrapper for rom iap call - * - * @param cmd_param IAP command and relevant parameter array. - * @param status_result IAP status result array. - * - * @retval None. Status/Result is returned via status_result array. - */ -static inline void iap_entry(uint32_t *cmd_param, uint32_t *status_result) -{ - ((IAP_ENTRY_T)FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION)(cmd_param, status_result); -} - -/*! - * @brief Prepare sector for write operation - - * This function prepares sector(s) for write/erase operation. This function must be - * called before calling the FLASHIAP_CopyRamToFlash() or FLASHIAP_EraseSector() or - * FLASHIAP_ErasePage() function. The end sector must be greater than or equal to - * start sector number. - * - * @param startSector Start sector number. - * @param endSector End sector number. - * - * @retval #kStatus_FLASHIAP_Success Api was executed successfully. - * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. - * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. - * @retval #kStatus_FLASHIAP_InvalidSector Sector number is invalid or end sector number - * is greater than start sector number. - * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy. - */ -status_t FLASHIAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector); - -/*! - * @brief Copy RAM to flash. - - * This function programs the flash memory. Corresponding sectors must be prepared - * via FLASHIAP_PrepareSectorForWrite before calling calling this function. The addresses - * should be a 256 byte boundary and the number of bytes should be 256 | 512 | 1024 | 4096. - * - * @param dstAddr Destination flash address where data bytes are to be written. - * @param srcAddr Source ram address from where data bytes are to be read. - * @param numOfBytes Number of bytes to be written. - * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the - * rom IAP function. - * - * @retval #kStatus_FLASHIAP_Success Api was executed successfully. - * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. - * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. - * @retval #kStatus_FLASHIAP_SrcAddrError Source address is not on word boundary. - * @retval #kStatus_FLASHIAP_DstAddrError Destination address is not on a correct boundary. - * @retval #kStatus_FLASHIAP_SrcAddrNotMapped Source address is not mapped in the memory map. - * @retval #kStatus_FLASHIAP_DstAddrNotMapped Destination address is not mapped in the memory map. - * @retval #kStatus_FLASHIAP_CountError Byte count is not multiple of 4 or is not a permitted value. - * @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed. - * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy. - */ -status_t FLASHIAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock); - -/*! - * @brief Erase sector - - * This function erases sector(s). The end sector must be greater than or equal to - * start sector number. FLASHIAP_PrepareSectorForWrite must be called before - * calling this function. - * - * @param startSector Start sector number. - * @param endSector End sector number. - * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the - * rom IAP function. - * - * @retval #kStatus_FLASHIAP_Success Api was executed successfully. - * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. - * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. - * @retval #kStatus_FLASHIAP_InvalidSector Sector number is invalid or end sector number - * is greater than start sector number. - * @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed. - * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy. - */ -status_t FLASHIAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock); - -/*! - - * This function erases page(s). The end page must be greater than or equal to - * start page number. Corresponding sectors must be prepared via FLASHIAP_PrepareSectorForWrite - * before calling calling this function. - * - * @param startPage Start page number - * @param endPage End page number - * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the - * rom IAP function. - * - * @retval #kStatus_FLASHIAP_Success Api was executed successfully. - * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. - * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. - * @retval #kStatus_FLASHIAP_InvalidSector Page number is invalid or end page number - * is greater than start page number - * @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed. - * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy. - */ -status_t FLASHIAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t systemCoreClock); - -/*! - * @brief Blank check sector(s) - * - * Blank check single or multiples sectors of flash memory. The end sector must be greater than or equal to - * start sector number. It can be used to verify the sector eraseure after FLASHIAP_EraseSector call. - * - * @param startSector : Start sector number. Must be greater than or equal to start sector number - * @param endSector : End sector number - * @retval #kStatus_FLASHIAP_Success One or more sectors are in erased state. - * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. - * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. - * @retval #kStatus_FLASHIAP_SectorNotblank One or more sectors are not blank. - */ -status_t FLASHIAP_BlankCheckSector(uint32_t startSector, uint32_t endSector); - -/*! - * @brief Compare memory contents of flash with ram. - - * This function compares the contents of flash and ram. It can be used to verify the flash - * memory contents after FLASHIAP_CopyRamToFlash call. - * - * @param dstAddr Destination flash address. - * @param srcAddr Source ram address. - * @param numOfBytes Number of bytes to be compared. - * - * @retval #kStatus_FLASHIAP_Success Contents of flash and ram match. - * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. - * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. - * @retval #kStatus_FLASHIAP_AddrError Address is not on word boundary. - * @retval #kStatus_FLASHIAP_AddrNotMapped Address is not mapped in the memory map. - * @retval #kStatus_FLASHIAP_CountError Byte count is not multiple of 4 or is not a permitted value. - * @retval #kStatus_FLASHIAP_CompareError Destination and source memory contents do not match. - */ -status_t FLASHIAP_Compare(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_FLASHIAP_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flexcomm.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flexcomm.c deleted file mode 100644 index f13a2f836b4..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flexcomm.c +++ /dev/null @@ -1,313 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! @brief Set the FLEXCOMM mode . */ -static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock); - -/*! @brief check whether flexcomm supports peripheral type */ -static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ -static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT]; - -/*! @brief Pointers to handles for each instance to provide context to interrupt routines */ -static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT]; - -/*! @brief Array to map FLEXCOMM instance number to IRQ number. */ -IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS; - -/*! @brief Array to map FLEXCOMM instance number to base address. */ -static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief IDs of clock for each FLEXCOMM module */ -static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* check whether flexcomm supports peripheral type */ -static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph) -{ - if (periph == FLEXCOMM_PERIPH_NONE) - { - return true; - } - else if (periph <= FLEXCOMM_PERIPH_I2S_TX) - { - return (base->PSELID & (uint32_t)(1 << ((uint32_t)periph + 3))) > (uint32_t)0 ? true : false; - } - else if (periph == FLEXCOMM_PERIPH_I2S_RX) - { - return (base->PSELID & (1 << 7)) > (uint32_t)0 ? true : false; - } - else - { - return false; - } -} - -/* Get the index corresponding to the FLEXCOMM */ -uint32_t FLEXCOMM_GetInstance(void *base) -{ - int i; - - for (i = 0; i < FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++) - { - if ((uint32_t)base == s_flexcommBaseAddrs[i]) - { - return i; - } - } - - assert(false); - return 0; -} - -/* Changes FLEXCOMM mode */ -static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock) -{ - /* Check whether peripheral type is present */ - if (!FLEXCOMM_PeripheralIsPresent(base, periph)) - { - return kStatus_OutOfRange; - } - - /* Flexcomm is locked to different peripheral type than expected */ - if ((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) && ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != periph)) - { - return kStatus_Fail; - } - - /* Check if we are asked to lock */ - if (lock) - { - base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK; - } - else - { - base->PSELID = (uint32_t)periph; - } - - return kStatus_Success; -} - -status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) -{ - int idx = FLEXCOMM_GetInstance(base); - - if (idx < 0) - { - return kStatus_InvalidArgument; - } - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the peripheral clock */ - CLOCK_EnableClock(s_flexcommClocks[idx]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Set the FLEXCOMM to given peripheral */ - return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0); -} - -void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(base); - - /* Clear handler first to avoid execution of the handler with wrong handle */ - s_flexcommIrqHandler[instance] = NULL; - s_flexcommHandle[instance] = handle; - s_flexcommIrqHandler[instance] = handler; -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(FLEXCOMM0) -void FLEXCOMM0_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[0]); - s_flexcommIrqHandler[0]((void *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM1) -void FLEXCOMM1_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[1]); - s_flexcommIrqHandler[1]((void *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM2) -void FLEXCOMM2_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[2]); - s_flexcommIrqHandler[2]((void *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM3) -void FLEXCOMM3_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[3]); - s_flexcommIrqHandler[3]((void *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM4) -void FLEXCOMM4_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[4]); - s_flexcommIrqHandler[4]((void *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -#endif - -#if defined(FLEXCOMM5) -void FLEXCOMM5_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[5]); - s_flexcommIrqHandler[5]((void *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM6) -void FLEXCOMM6_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[6]); - s_flexcommIrqHandler[6]((void *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM7) -void FLEXCOMM7_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[7]); - s_flexcommIrqHandler[7]((void *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM8) -void FLEXCOMM8_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[8]); - s_flexcommIrqHandler[8]((void *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM9) -void FLEXCOMM9_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[9]); - s_flexcommIrqHandler[9]((void *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flexcomm.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flexcomm.h deleted file mode 100644 index 74318e351cb..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flexcomm.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_FLEXCOMM_H_ -#define _FSL_FLEXCOMM_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup flexcomm_driver - * @{ - */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FlexCOMM driver version 2.0.0. */ -#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @brief FLEXCOMM peripheral modes. */ -typedef enum -{ - FLEXCOMM_PERIPH_NONE, /*!< No peripheral */ - FLEXCOMM_PERIPH_USART, /*!< USART peripheral */ - FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */ - FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */ - FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */ - FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */ -} FLEXCOMM_PERIPH_T; - -/*! @brief Typedef for interrupt handler. */ -typedef void (*flexcomm_irq_handler_t)(void *base, void *handle); - -/*! @brief Array with IRQ number for each FLEXCOMM module. */ -extern IRQn_Type const kFlexcommIrqs[]; - -/*! @brief Returns instance number for FLEXCOMM module with given base address. */ -uint32_t FLEXCOMM_GetInstance(void *base); - -/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ -status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph); - -/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM - * mode */ -void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle); - -/*@}*/ - -#endif /* _FSL_FLEXCOMM_H_*/ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_fmeas.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_fmeas.c deleted file mode 100644 index 5f087c7bc80..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_fmeas.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_fmeas.h" - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.fmeas" -#endif - - -/*! @brief Target clock counter value. - * According to user manual, 2 has to be subtracted from captured value (CAPVAL). */ -#define TARGET_CLOCK_COUNT(base) \ - ((uint32_t)( \ - ((((SYSCON_Type *)base)->FREQMECTRL & SYSCON_FREQMECTRL_CAPVAL_MASK) >> SYSCON_FREQMECTRL_CAPVAL_SHIFT) - 2)) - -/*! @brief Reference clock counter value. */ -#define REFERENCE_CLOCK_COUNT ((uint32_t)((SYSCON_FREQMECTRL_CAPVAL_MASK >> SYSCON_FREQMECTRL_CAPVAL_SHIFT) + 1)) - -/******************************************************************************* - * Code - ******************************************************************************/ - -uint32_t FMEAS_GetFrequency(SYSCON_Type *base, uint32_t refClockRate) -{ - uint32_t targetClockCount = TARGET_CLOCK_COUNT(base); - uint64_t clkrate = 0; - - if (targetClockCount > 0) - { - clkrate = (((uint64_t)targetClockCount) * (uint64_t)refClockRate) / REFERENCE_CLOCK_COUNT; - } - - return (uint32_t)clkrate; -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_fmeas.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_fmeas.h deleted file mode 100644 index 15921375f62..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_fmeas.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_FMEAS_H_ -#define _FSL_FMEAS_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup fmeas - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Defines LPC Frequency Measure driver version 2.0.0. - * - * Change log: - * - Version 2.0.0 - * - initial version - */ -#define FSL_FMEAS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name FMEAS Functional Operation - * @{ - */ - -/*! - * @brief Starts a frequency measurement cycle. - * - * @param base : SYSCON peripheral base address. - */ -static inline void FMEAS_StartMeasure(SYSCON_Type *base) -{ - base->FREQMECTRL = 0; - base->FREQMECTRL = (1UL << 31); -} - -/*! - * @brief Indicates when a frequency measurement cycle is complete. - * - * @param base : SYSCON peripheral base address. - * @return true if a measurement cycle is active, otherwise false. - */ -static inline bool FMEAS_IsMeasureComplete(SYSCON_Type *base) -{ - return (bool)((base->FREQMECTRL & (1UL << 31)) == 0); -} - -/*! - * @brief Returns the computed value for a frequency measurement cycle - * - * @param base : SYSCON peripheral base address. - * @param refClockRate : Reference clock rate used during the frequency measurement cycle. - * - * @return Frequency in Hz. - */ -uint32_t FMEAS_GetFrequency(SYSCON_Type *base, uint32_t refClockRate); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_FMEAS_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gint.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gint.c deleted file mode 100644 index e772da018b6..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gint.c +++ /dev/null @@ -1,321 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_gint.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.gint" -#endif - - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to GINT bases for each instance. */ -static GINT_Type *const s_gintBases[FSL_FEATURE_SOC_GINT_COUNT] = GINT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Clocks for each instance. */ -static const clock_ip_name_t s_gintClocks[FSL_FEATURE_SOC_GINT_COUNT] = GINT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Resets for each instance. */ -static const reset_ip_name_t s_gintResets[FSL_FEATURE_SOC_GINT_COUNT] = GINT_RSTS; - -/* @brief Irq number for each instance */ -static const IRQn_Type s_gintIRQ[FSL_FEATURE_SOC_GINT_COUNT] = GINT_IRQS; - -/*! @brief Callback function array for GINT(s). */ -static gint_cb_t s_gintCallback[FSL_FEATURE_SOC_GINT_COUNT]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t GINT_GetInstance(GINT_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_gintBases); instance++) - { - if (s_gintBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_gintBases)); - - return instance; -} - -void GINT_Init(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - s_gintCallback[instance] = NULL; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the peripheral clock */ - CLOCK_EnableClock(s_gintClocks[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the peripheral */ - RESET_PeripheralReset(s_gintResets[instance]); -} - -void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - base->CTRL = (GINT_CTRL_COMB(comb) | GINT_CTRL_TRIG(trig)); - - /* Save callback pointer */ - s_gintCallback[instance] = callback; -} - -void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - *comb = (gint_comb_t)((base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT); - *trig = (gint_trig_t)((base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT); - *callback = s_gintCallback[instance]; -} - -void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask) -{ - base->PORT_POL[port] = polarityMask; - base->PORT_ENA[port] = enableMask; -} - -void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask) -{ - *polarityMask = base->PORT_POL[port]; - *enableMask = base->PORT_ENA[port]; -} - -void GINT_EnableCallback(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - /* If GINT is configured in "AND" mode a spurious interrupt is generated. - Clear status and pending interrupt before enabling the irq in NVIC. */ - GINT_ClrStatus(base); - NVIC_ClearPendingIRQ(s_gintIRQ[instance]); - EnableIRQ(s_gintIRQ[instance]); -} - -void GINT_DisableCallback(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - DisableIRQ(s_gintIRQ[instance]); - GINT_ClrStatus(base); - NVIC_ClearPendingIRQ(s_gintIRQ[instance]); -} - -void GINT_Deinit(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - /* Cleanup */ - GINT_DisableCallback(base); - s_gintCallback[instance] = NULL; - - /* Reset the peripheral */ - RESET_PeripheralReset(s_gintResets[instance]); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the peripheral clock */ - CLOCK_DisableClock(s_gintClocks[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(GINT0) -void GINT0_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[0]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[0] != NULL) - { - s_gintCallback[0](); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(GINT1) -void GINT1_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[1]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[1] != NULL) - { - s_gintCallback[1](); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(GINT2) -void GINT2_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[2]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[2] != NULL) - { - s_gintCallback[2](); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(GINT3) -void GINT3_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[3]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[3] != NULL) - { - s_gintCallback[3](); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(GINT4) -void GINT4_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[4]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[4] != NULL) - { - s_gintCallback[4](); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(GINT5) -void GINT5_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[5]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[5] != NULL) - { - s_gintCallback[5](); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(GINT6) -void GINT6_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[6]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[6] != NULL) - { - s_gintCallback[6](); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(GINT7) -void GINT7_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[7]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[7] != NULL) - { - s_gintCallback[7](); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gint.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gint.h deleted file mode 100644 index f010600bed7..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gint.h +++ /dev/null @@ -1,248 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_GINT_H_ -#define _FSL_GINT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup gint_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ -/*@}*/ - -/*! @brief GINT combine inputs type */ -typedef enum _gint_comb -{ - kGINT_CombineOr = 0U, /*!< A grouped interrupt is generated when any one of the enabled inputs is active */ - kGINT_CombineAnd = 1U /*!< A grouped interrupt is generated when all enabled inputs are active */ -} gint_comb_t; - -/*! @brief GINT trigger type */ -typedef enum _gint_trig -{ - kGINT_TrigEdge = 0U, /*!< Edge triggered based on polarity */ - kGINT_TrigLevel = 1U /*!< Level triggered based on polarity */ -} gint_trig_t; - -/* @brief GINT port type */ -typedef enum _gint_port -{ - kGINT_Port0 = 0U, - kGINT_Port1 = 1U, -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 2U) - kGINT_Port2 = 2U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 3U) - kGINT_Port3 = 3U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 4U) - kGINT_Port4 = 4U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 5U) - kGINT_Port5 = 5U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 6U) - kGINT_Port6 = 6U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 7U) - kGINT_Port7 = 7U, -#endif -} gint_port_t; - -/*! @brief GINT Callback function. */ -typedef void (*gint_cb_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize GINT peripheral. - - * This function initializes the GINT peripheral and enables the clock. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_Init(GINT_Type *base); - -/*! - * @brief Setup GINT peripheral control parameters. - - * This function sets the control parameters of GINT peripheral. - * - * @param base Base address of the GINT peripheral. - * @param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. - * @param trig Controls if the enabled inputs are level or edge sensitive based on polarity. - * @param callback This function is called when configured group interrupt is generated. - * - * @retval None. - */ -void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback); - -/*! - * @brief Get GINT peripheral control parameters. - - * This function returns the control parameters of GINT peripheral. - * - * @param base Base address of the GINT peripheral. - * @param comb Pointer to store combine input value. - * @param trig Pointer to store trigger value. - * @param callback Pointer to store callback function. - * - * @retval None. - */ -void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback); - -/*! - * @brief Configure GINT peripheral pins. - - * This function enables and controls the polarity of enabled pin(s) of a given port. - * - * @param base Base address of the GINT peripheral. - * @param port Port number. - * @param polarityMask Each bit position selects the polarity of the corresponding enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * @param enableMask Each bit position selects if the corresponding pin is enabled or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * @retval None. - */ -void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask); - -/*! - * @brief Get GINT peripheral pin configuration. - - * This function returns the pin configuration of a given port. - * - * @param base Base address of the GINT peripheral. - * @param port Port number. - * @param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding - enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * @param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled - or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * @retval None. - */ -void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask); - -/*! - * @brief Enable callback. - - * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_EnableCallback(GINT_Type *base); - -/*! - * @brief Disable callback. - - * This function disables the interrupt for the selected GINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * @param base Base address of the peripheral. - * - * @retval None. - */ -void GINT_DisableCallback(GINT_Type *base); - -/*! - * @brief Clear GINT status. - - * This function clears the GINT status bit. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -static inline void GINT_ClrStatus(GINT_Type *base) -{ - base->CTRL |= GINT_CTRL_INT_MASK; -} - -/*! - * @brief Get GINT status. - - * This function returns the GINT status. - * - * @param base Base address of the GINT peripheral. - * - * @retval status = 0 No group interrupt request. = 1 Group interrupt request active. - */ -static inline uint32_t GINT_GetStatus(GINT_Type *base) -{ - return (base->CTRL & GINT_CTRL_INT_MASK); -} - -/*! - * @brief Deinitialize GINT peripheral. - - * This function disables the GINT clock. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_Deinit(GINT_Type *base); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_GINT_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gpio.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gpio.c deleted file mode 100644 index 12bf49db792..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gpio.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_gpio.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio" -#endif - - -/******************************************************************************* - * Variables - ******************************************************************************/ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map FGPIO instance number to clock name. */ -static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -/******************************************************************************* -* Prototypes -************ ******************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -void GPIO_PortInit(GPIO_Type *base, uint32_t port) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - assert(port < ARRAY_SIZE(s_gpioClockName)); - - /* Upgate the GPIO clock */ - CLOCK_EnableClock(s_gpioClockName[port]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) -{ - if (config->pinDirection == kGPIO_DigitalInput) - { - base->DIR[port] &= ~(1U << pin); - } - else - { - /* Set default output value */ - if (config->outputLogic == 0U) - { - base->CLR[port] = (1U << pin); - } - else - { - base->SET[port] = (1U << pin); - } - /* Set pin direction */ - base->DIR[port] |= 1U << pin; - } -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gpio.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gpio.h deleted file mode 100644 index 9ae8cce2652..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gpio.h +++ /dev/null @@ -1,355 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _LPC_GPIO_H_ -#define _LPC_GPIO_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_gpio - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPC GPIO driver version 2.1.1. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) -/*@}*/ - -/*! @brief LPC GPIO direction definition */ -typedef enum _gpio_pin_direction -{ - kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ - kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ -} gpio_pin_direction_t; - -/*! - * @brief The GPIO pin configuration structure. - * - * Every pin can only be configured as either output pin or input pin at a time. - * If configured as a input pin, then leave the outputConfig unused. - */ -typedef struct _gpio_pin_config -{ - gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ - /* Output configurations, please ignore if configured as a input one */ - uint8_t outputLogic; /*!< Set default output logic, no use in input */ -} gpio_pin_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @name GPIO Configuration */ -/*@{*/ - -/*! - * @brief Initializes the GPIO peripheral. - * - * This function ungates the GPIO clock. - * - * @param base GPIO peripheral base pointer. - * @param port GPIO port number. - */ -void GPIO_PortInit(GPIO_Type *base, uint32_t port); - -/*! - * @brief Initializes the GPIO peripheral. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortInit. - */ -static inline void GPIO_Init(GPIO_Type *base, uint32_t port) -{ - GPIO_PortInit(base, port); -} - -/*! - * @brief Initializes a GPIO pin used by the board. - * - * To initialize the GPIO, define a pin configuration, either input or output, in the user file. - * Then, call the GPIO_PinInit() function. - * - * This is an example to define an input pin or output pin configuration: - * @code - * // Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * //Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * @endcode - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @param config GPIO pin configuration pointer - */ -void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config); - -/*@}*/ - -/*! @name GPIO Output Operations */ -/*@{*/ - -/*! - * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @param output GPIO pin output logic level. - * - 0: corresponding pin output low-logic level. - * - 1: corresponding pin output high-logic level. - */ -static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) -{ - base->B[port][pin] = output; -} - -/*! - * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinWrite. - */ -static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) -{ - base->B[port][pin] = output; -} -/*@}*/ -/*! @name GPIO Input Operations */ -/*@{*/ - -/*! - * @brief Reads the current input value of the GPIO PIN. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @retval GPIO port input value - * - 0: corresponding pin input low-logic level. - * - 1: corresponding pin input high-logic level. - */ -static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) -{ - return (uint32_t)base->B[port][pin]; -} - -/*! - * @brief Reads the current input value of the GPIO PIN. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinRead. - */ -static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t port, uint32_t pin) -{ - return GPIO_PinRead(base, port, pin); -} -/*@}*/ - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 1. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->SET[port] = mask; -} - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 1. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortSet. - */ -static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - GPIO_PortSet(base, port, mask); -} - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 0. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->CLR[port] = mask; -} - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 0. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortClear. - */ -static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - GPIO_PortClear(base, port, mask); -} - -/*! - * @brief Reverses current output logic of the multiple GPIO pins. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->NOT[port] = mask; -} - -/*! - * @brief Reverses current output logic of the multiple GPIO pins. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortToggle. - */ -static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - GPIO_PortToggle(base, port, mask); -} -/*@}*/ - -/*! - * @brief Reads the current input value of the whole GPIO port. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - */ -static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port) -{ - return (uint32_t)base->PIN[port]; -} - -/*! - * @brief Reads the current input value of the whole GPIO port. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortRead - */ -static inline uint32_t GPIO_ReadPinsInput(GPIO_Type *base, uint32_t port) -{ - return GPIO_PortRead(base, port); -} - -/*@}*/ -/*! @name GPIO Mask Operations */ -/*@{*/ - -/*! - * @brief Sets port mask, 0 - enable pin, 1 - disable pin. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->MASK[port] = mask; -} - -/*! - * @brief Sets port mask, 0 - enable pin, 1 - disable pin. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortMaskedSet. - */ -static inline void GPIO_SetPortMask(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - GPIO_PortMaskedSet(base, port, mask); -} - -/*! - * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param output GPIO port output value. - */ -static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output) -{ - base->MPIN[port] = output; -} - -/*! - * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortMaskedWrite. - */ -static inline void GPIO_WriteMPort(GPIO_Type *base, uint32_t port, uint32_t output) -{ - GPIO_PortMaskedWrite(base, port, output); -} - -/*! - * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be - * affected. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @retval masked GPIO port value - */ -static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) -{ - return (uint32_t)base->MPIN[port]; -} - -/*! - * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be - * affected. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortMaskedRead. - */ -static inline uint32_t GPIO_ReadMPort(GPIO_Type *base, uint32_t port) -{ - return GPIO_PortMaskedRead(base, port); -} - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* _LPC_GPIO_H_*/ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c.c deleted file mode 100644 index b7ee6929fed..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c.c +++ /dev/null @@ -1,1514 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_i2c.h" -#include "fsl_flexcomm.h" -#include -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c" -#endif - - -/*! @brief Common sets of flags used by the driver. */ -enum _i2c_flag_constants -{ - kI2C_MasterIrqFlags = I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK, - kI2C_SlaveIrqFlags = I2C_INTSTAT_SLVPENDING_MASK | I2C_INTSTAT_SLVDESEL_MASK, -}; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); -static void I2C_SlaveInternalStateMachineReset(I2C_Type *base); -static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal); -static uint32_t I2C_SlavePollPending(I2C_Type *base); -static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event); -static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle); -static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, - i2c_slave_handle_t *handle, - const void *txData, - size_t txSize, - void *rxData, - size_t rxSize, - uint32_t eventMask); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map i2c instance number to base address. */ -static const uint32_t s_i2cBaseAddrs[FSL_FEATURE_SOC_I2C_COUNT] = I2C_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_i2cIRQ[] = I2C_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * @brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * @param base The I2C peripheral base address. - * @return I2C instance number starting from 0. - */ -uint32_t I2C_GetInstance(I2C_Type *base) -{ - int i; - for (i = 0; i < FSL_FEATURE_SOC_I2C_COUNT; i++) - { - if ((uint32_t)base == s_i2cBaseAddrs[i]) - { - return i; - } - } - assert(false); - return 0; -} - -void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) -{ - masterConfig->enableMaster = true; - masterConfig->baudRate_Bps = 100000U; - masterConfig->enableTimeout = false; -} - -void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) -{ - FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); - I2C_MasterEnable(base, masterConfig->enableMaster); - I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); -} - -void I2C_MasterDeinit(I2C_Type *base) -{ - I2C_MasterEnable(base, false); -} - -void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) -{ - uint32_t scl, divider; - uint32_t best_scl, best_div; - uint32_t err, best_err; - - best_err = 0; - - for (scl = 9; scl >= 2; scl--) - { - /* calculated ideal divider value for given scl */ - divider = srcClock_Hz / (baudRate_Bps * scl * 2u); - - /* adjust it if it is out of range */ - divider = (divider > 0x10000u) ? 0x10000 : divider; - - /* calculate error */ - err = srcClock_Hz - (baudRate_Bps * scl * 2u * divider); - if ((err < best_err) || (best_err == 0)) - { - best_div = divider; - best_scl = scl; - best_err = err; - } - - if ((err == 0) || (divider >= 0x10000u)) - { - /* either exact value was found - or divider is at its max (it would even greater in the next iteration for sure) */ - break; - } - } - - base->CLKDIV = I2C_CLKDIV_DIVVAL(best_div - 1); - base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl - 2u) | I2C_MSTTIME_MSTSCLHIGH(best_scl - 2u); -} - -static uint32_t I2C_PendingStatusWait(I2C_Type *base) -{ - uint32_t status; - -#if I2C_WAIT_TIMEOUT - uint32_t waitTimes = I2C_WAIT_TIMEOUT; -#endif - - do - { - status = I2C_GetStatusFlags(base); -#if I2C_WAIT_TIMEOUT - } while (((status & I2C_STAT_MSTPENDING_MASK) == 0) && (--waitTimes)); - - if (waitTimes == 0) - { - return kStatus_I2C_Timeout; - } -#else - } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); -#endif - - /* Clear controller state. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - return status; -} - -status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) -{ - status_t result; - result = I2C_PendingStatusWait(base); - if (result == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - - /* Write Address and RW bit to data register */ - base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1u); - /* Start the transfer */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - - return kStatus_Success; -} - -status_t I2C_MasterStop(I2C_Type *base) -{ - status_t result; - result = I2C_PendingStatusWait(base); - if (result == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - return kStatus_Success; -} - -status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags) -{ - uint32_t status; - uint32_t master_state; - status_t err; - - const uint8_t *buf = (const uint8_t *)(uintptr_t)txBuff; - - assert(txBuff); - - err = kStatus_Success; - while (txSize) - { - status = I2C_PendingStatusWait(base); - -#if I2C_WAIT_TIMEOUT - if (status == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } -#endif - - if (status & I2C_STAT_MSTARBLOSS_MASK) - { - return kStatus_I2C_ArbitrationLost; - } - - if (status & I2C_STAT_MSTSTSTPERR_MASK) - { - return kStatus_I2C_StartStopError; - } - - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - switch (master_state) - { - case I2C_STAT_MSTCODE_TXREADY: - /* ready to send next byte */ - base->MSTDAT = *buf++; - txSize--; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - break; - - case I2C_STAT_MSTCODE_NACKADR: - case I2C_STAT_MSTCODE_NACKDAT: - /* slave nacked the last byte */ - err = kStatus_I2C_Nak; - break; - - default: - /* unexpected state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - if (err != kStatus_Success) - { - return err; - } - } - - status = I2C_PendingStatusWait(base); - -#if I2C_WAIT_TIMEOUT - if (status == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } -#endif - - if ((status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK)) == 0) - { - if (!(flags & kI2C_TransferNoStopFlag)) - { - /* Initiate stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - status = I2C_PendingStatusWait(base); - if (status == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - } - - if (status & I2C_STAT_MSTARBLOSS_MASK) - { - return kStatus_I2C_ArbitrationLost; - } - - if (status & I2C_STAT_MSTSTSTPERR_MASK) - { - return kStatus_I2C_StartStopError; - } - - return kStatus_Success; -} - -status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags) -{ - uint32_t status = 0; - uint32_t master_state; - status_t err; - - uint8_t *buf = (uint8_t *)(rxBuff); - - assert(rxBuff); - - err = kStatus_Success; - while (rxSize) - { - status = I2C_PendingStatusWait(base); - -#if I2C_WAIT_TIMEOUT - if (status == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } -#endif - - if (status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK)) - { - break; - } - - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - switch (master_state) - { - case I2C_STAT_MSTCODE_RXREADY: - /* ready to send next byte */ - *(buf++) = base->MSTDAT; - if (--rxSize) - { - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - } - else - { - if ((flags & kI2C_TransferNoStopFlag) == 0) - { - /* initiate NAK and stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - status = I2C_PendingStatusWait(base); - -#if I2C_WAIT_TIMEOUT - if (status == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } -#endif - } - } - break; - - case I2C_STAT_MSTCODE_NACKADR: - case I2C_STAT_MSTCODE_NACKDAT: - /* slave nacked the last byte */ - err = kStatus_I2C_Nak; - break; - - default: - /* unexpected state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - if (err != kStatus_Success) - { - return err; - } - } - - if (status & I2C_STAT_MSTARBLOSS_MASK) - { - return kStatus_I2C_ArbitrationLost; - } - - if (status & I2C_STAT_MSTSTSTPERR_MASK) - { - return kStatus_I2C_StartStopError; - } - - return kStatus_Success; -} - -status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) -{ - status_t result = kStatus_Success; - uint32_t subaddress; - uint8_t subaddrBuf[4]; - int i; - - assert(xfer); - - /* If repeated start is requested, send repeated start. */ - if (!(xfer->flags & kI2C_TransferNoStartFlag)) - { - if (xfer->subaddressSize) - { - result = I2C_MasterStart(base, xfer->slaveAddress, kI2C_Write); - if (result == kStatus_Success) - { - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = xfer->subaddressSize - 1; i >= 0; i--) - { - subaddrBuf[i] = subaddress & 0xff; - subaddress >>= 8; - } - /* Send subaddress. */ - result = I2C_MasterWriteBlocking(base, subaddrBuf, xfer->subaddressSize, kI2C_TransferNoStopFlag); - if ((result == kStatus_Success) && (xfer->direction == kI2C_Read)) - { - result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction); - } - } - } - else if (xfer->flags & kI2C_TransferRepeatedStartFlag) - { - result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction); - } - else - { - result = I2C_MasterStart(base, xfer->slaveAddress, xfer->direction); - } - } - - if (result == kStatus_Success) - { - if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0)) - { - /* Transmit data. */ - result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); - } - else - { - if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0)) - { - /* Receive Data. */ - result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags); - } - } - } - - if (result == kStatus_I2C_Nak) - { - I2C_MasterStop(base); - } - - return result; -} - -void I2C_MasterTransferCreateHandle(I2C_Type *base, - i2c_master_handle_t *handle, - i2c_master_transfer_callback_t callback, - void *userData) -{ - uint32_t instance; - - assert(handle); - - /* Clear out the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Save base and instance. */ - handle->completionCallback = callback; - handle->userData = userData; - - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2C_MasterTransferHandleIRQ, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); - EnableIRQ(s_i2cIRQ[instance]); -} - -status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) -{ - status_t result; - - assert(handle); - assert(xfer); - assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); - - /* Return busy if another transaction is in progress. */ - if (handle->state != kIdleState) - { - return kStatus_I2C_Busy; - } - - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); - - /* Prepare transfer state machine. */ - result = I2C_InitTransferStateMachine(base, handle, xfer); - - /* Clear error flags. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Enable I2C internal IRQ sources. */ - I2C_EnableInterrupts(base, kI2C_MasterIrqFlags); - - return result; -} - -status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state == kIdleState) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* There is no necessity to disable interrupts as we read a single integer value */ - *count = handle->transferCount; - return kStatus_Success; -} - -status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) -{ - uint32_t status; - uint32_t master_state; - - if (handle->state != kIdleState) - { - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); - - /* Wait until module is ready */ - status = I2C_PendingStatusWait(base); - -#if I2C_WAIT_TIMEOUT - if (status == kStatus_I2C_Timeout) - { - /* Reset handle to idle state. */ - handle->state = kIdleState; - return kStatus_I2C_Timeout; - } -#endif - - /* Get the state of the I2C module */ - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if (master_state != I2C_STAT_MSTCODE_IDLE) - { - /* Send a stop command to finalize the transfer. */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - - /* Wait until the STOP is completed */ - status = I2C_PendingStatusWait(base); - if (status == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - - /* Reset handle. */ - handle->state = kIdleState; - } - return kStatus_Success; -} - -/*! - * @brief Prepares the transfer state machine and fills in the command buffer. - * @param handle Master nonblocking driver handle. - */ -static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) -{ - struct _i2c_master_transfer *transfer; - - handle->transfer = *xfer; - transfer = &(handle->transfer); - - handle->transferCount = 0; - handle->remainingBytes = transfer->dataSize; - handle->buf = (uint8_t *)transfer->data; - handle->remainingSubaddr = 0; - - if (transfer->flags & kI2C_TransferNoStartFlag) - { - /* Start condition shall be ommited, switch directly to next phase */ - if (transfer->dataSize == 0) - { - handle->state = kStopState; - } - else if (handle->transfer.direction == kI2C_Write) - { - handle->state = kTransmitDataState; - } - else if (handle->transfer.direction == kI2C_Read) - { - handle->state = kReceiveDataState; - } - else - { - return kStatus_I2C_InvalidParameter; - } - } - else - { - if (transfer->subaddressSize != 0) - { - int i; - uint32_t subaddress; - - if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) - { - return kStatus_I2C_InvalidParameter; - } - - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = xfer->subaddressSize - 1; i >= 0; i--) - { - handle->subaddrBuf[i] = subaddress & 0xff; - subaddress >>= 8; - } - handle->remainingSubaddr = transfer->subaddressSize; - } - handle->state = kStartState; - } - - return kStatus_Success; -} - -/*! - * @brief Execute states until FIFOs are exhausted. - * @param handle Master nonblocking driver handle. - * @param[out] isDone Set to true if the transfer has completed. - * @retval #kStatus_Success - * @retval #kStatus_I2C_ArbitrationLost - * @retval #kStatus_I2C_Nak - */ -static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) -{ - uint32_t status; - uint32_t master_state; - struct _i2c_master_transfer *transfer; - status_t err; - - transfer = &(handle->transfer); - - *isDone = false; - - status = I2C_GetStatusFlags(base); - - if (status & I2C_STAT_MSTARBLOSS_MASK) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); - return kStatus_I2C_ArbitrationLost; - } - - if (status & I2C_STAT_MSTSTSTPERR_MASK) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); - return kStatus_I2C_StartStopError; - } - - if ((status & I2C_STAT_MSTPENDING_MASK) == 0) - { - return kStatus_I2C_Busy; - } - - /* Get the state of the I2C module */ - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT)) - { - /* Slave NACKed last byte, issue stop and return error */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; - return kStatus_I2C_Nak; - } - - err = kStatus_Success; - switch (handle->state) - { - case kStartState: - if (handle->remainingSubaddr) - { - /* Subaddress takes precedence over the data transfer, direction is always "write" in this case */ - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = kTransmitSubaddrState; - } - else if (transfer->direction == kI2C_Write) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = handle->remainingBytes ? kTransmitDataState : kStopState; - } - else - { - base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; - handle->state = handle->remainingBytes ? kReceiveDataState : kStopState; - } - /* Send start condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - break; - - case kTransmitSubaddrState: - if (master_state != I2C_STAT_MSTCODE_TXREADY) - { - return kStatus_I2C_UnexpectedState; - } - - /* Most significant subaddress byte comes first */ - base->MSTDAT = handle->subaddrBuf[handle->transfer.subaddressSize - handle->remainingSubaddr]; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - if (--(handle->remainingSubaddr)) - { - /* There are still subaddress bytes to be transmitted */ - break; - } - if (handle->remainingBytes) - { - /* There is data to be transferred, if there is write to read turnaround it is necessary to perform - * repeated start */ - handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState; - } - else - { - /* No more data, schedule stop condition */ - handle->state = kStopState; - } - break; - - case kTransmitDataState: - if (master_state != I2C_STAT_MSTCODE_TXREADY) - { - return kStatus_I2C_UnexpectedState; - } - base->MSTDAT = *(handle->buf)++; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - if (--handle->remainingBytes == 0) - { - /* No more data, schedule stop condition */ - handle->state = kStopState; - } - handle->transferCount++; - break; - - case kReceiveDataState: - if (master_state != I2C_STAT_MSTCODE_RXREADY) - { - return kStatus_I2C_UnexpectedState; - } - *(handle->buf)++ = base->MSTDAT; - if (--handle->remainingBytes) - { - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - } - else - { - /* No more data expected, issue NACK and STOP right away */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; - } - handle->transferCount++; - break; - - case kStopState: - if (transfer->flags & kI2C_TransferNoStopFlag) - { - /* Stop condition is omitted, we are done */ - *isDone = true; - handle->state = kIdleState; - break; - } - /* Send stop condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; - break; - - case kWaitForCompletionState: - *isDone = true; - handle->state = kIdleState; - break; - - case kIdleState: - default: - /* State machine shall not be invoked again once it enters the idle state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - return err; -} - -void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle) -{ - bool isDone; - status_t result; - - /* Don't do anything if we don't have a valid handle. */ - if (!handle) - { - return; - } - - result = I2C_RunTransferStateMachine(base, handle, &isDone); - - if (isDone || (result != kStatus_Success)) - { - /* Restore handle to idle state. */ - handle->state = kIdleState; - - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); - - /* Invoke callback. */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } -} - -/*! - * @brief Sets the hardware slave state machine to reset - * - * Per documentation, the only the state machine is reset, the configuration settings remain. - * - * @param base The I2C peripheral base address. - */ -static void I2C_SlaveInternalStateMachineReset(I2C_Type *base) -{ - I2C_SlaveEnable(base, false); /* clear SLVEN Slave enable bit */ -} - -/*! - * @brief Compute CLKDIV - * - * This function computes CLKDIV value according to the given bus speed and Flexcomm source clock frequency. - * This setting is used by hardware during slave clock stretching. - * - * @param base The I2C peripheral base address. - * @return status of the operation - */ -static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal) -{ - uint32_t dataSetupTime_ns; - - switch (busSpeed) - { - case kI2C_SlaveStandardMode: - dataSetupTime_ns = 250u; - break; - - case kI2C_SlaveFastMode: - dataSetupTime_ns = 100u; - break; - - case kI2C_SlaveFastModePlus: - dataSetupTime_ns = 50u; - break; - - case kI2C_SlaveHsMode: - dataSetupTime_ns = 10u; - break; - - default: - dataSetupTime_ns = 0; - break; - } - - if (0 == dataSetupTime_ns) - { - return kStatus_InvalidArgument; - } - - /* divVal = (sourceClock_Hz / 1000000) * (dataSetupTime_ns / 1000) */ - *divVal = srcClock_Hz / 1000u; - *divVal = (*divVal) * dataSetupTime_ns; - *divVal = (*divVal) / 1000000u; - - if ((*divVal) > I2C_CLKDIV_DIVVAL_MASK) - { - *divVal = I2C_CLKDIV_DIVVAL_MASK; - } - - return kStatus_Success; -} - -/*! - * @brief Poll wait for the SLVPENDING flag. - * - * Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register. - * - * @param base The I2C peripheral base address. - * @return status register at time the SLVPENDING bit is read as set - */ -static uint32_t I2C_SlavePollPending(I2C_Type *base) -{ - uint32_t stat; - -#if I2C_WAIT_TIMEOUT - uint32_t waitTimes = I2C_WAIT_TIMEOUT; -#endif - do - { - stat = base->STAT; -#if I2C_WAIT_TIMEOUT - } while ((0u == (stat & I2C_STAT_SLVPENDING_MASK)) && (--waitTimes)); - - if (waitTimes == 0u) - { - return kStatus_I2C_Timeout; - } -#else - } while (0u == (stat & I2C_STAT_SLVPENDING_MASK)); -#endif - - return stat; -} - -/*! - * @brief Invoke event from I2C_SlaveTransferHandleIRQ(). - * - * Sets the event type to transfer structure and invokes the event callback, if it has been - * enabled by eventMask. - * - * @param base The I2C peripheral base address. - * @param handle The I2C slave handle for non-blocking APIs. - * @param event The I2C slave event to invoke. - */ -static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event) -{ - handle->transfer.event = event; - if ((handle->callback) && (handle->transfer.eventMask & event)) - { - handle->callback(base, &handle->transfer, handle->userData); - - /* if after event callback we have data buffer (callback func has added new data), keep transfer busy */ - if (false == handle->isBusy) - { - if (((handle->transfer.txData) && (handle->transfer.txSize)) || - ((handle->transfer.rxData) && (handle->transfer.rxSize))) - { - handle->isBusy = true; - } - } - - /* Clear the transferred count now that we have a new buffer. */ - if ((event == kI2C_SlaveReceiveEvent) || (event == kI2C_SlaveTransmitEvent)) - { - handle->transfer.transferredCount = 0; - } - } -} - -/*! - * @brief Handle slave address match event. - * - * Called by Slave interrupt routine to ACK or NACK the matched address. - * It also determines master direction (read or write). - * - * @param base The I2C peripheral base address. - * @return true if the matched address is ACK'ed - * @return false if the matched address is NACK'ed - */ -static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle) -{ - uint8_t addressByte0; - - addressByte0 = (uint8_t)base->SLVDAT; - - /* store the matched address */ - handle->transfer.receivedAddress = addressByte0; - - /* R/nW */ - if (addressByte0 & 1u) - { - /* if we have no data in this transfer, call callback to get new */ - if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); - } - - /* NACK if we have no data in this transfer. */ - if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0)) - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - return false; - } - - /* master wants to read, so slave transmit is next state */ - handle->slaveFsm = kI2C_SlaveFsmTransmit; - } - else - { - /* if we have no receive buffer in this transfer, call callback to get new */ - if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); - } - - /* NACK if we have no data in this transfer */ - if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0)) - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - return false; - } - - /* master wants write, so slave receive is next state */ - handle->slaveFsm = kI2C_SlaveFsmReceive; - } - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - return true; -} - -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. - * @param txData Data to be transmitted to master in response to master read from slave requests. NULL if slave RX only. - * @param txSize Size of txData buffer in bytes. - * @param rxData Data where received data from master will be stored in response to master write to slave requests. NULL - * if slave TX only. - * @param rxSize Size of rxData buffer in bytes. - * - * @retval #kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, - i2c_slave_handle_t *handle, - const void *txData, - size_t txSize, - void *rxData, - size_t rxSize, - uint32_t eventMask) -{ - status_t status; - - assert(handle); - - status = kStatus_Success; - - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags); - - /* Return busy if another transaction is in progress. */ - if (handle->isBusy) - { - status = kStatus_I2C_Busy; - } - - /* Save transfer into handle. */ - handle->transfer.txData = (const uint8_t *)(uintptr_t)txData; - handle->transfer.txSize = txSize; - handle->transfer.rxData = (uint8_t *)rxData; - handle->transfer.rxSize = rxSize; - handle->transfer.transferredCount = 0; - handle->transfer.eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent; - handle->isBusy = true; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* Clear w1c flags. */ - base->STAT |= 0u; - - /* Enable I2C internal IRQ sources. */ - I2C_EnableInterrupts(base, kI2C_SlaveIrqFlags); - - return status; -} - -status_t I2C_SlaveSetSendBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, txData, txSize, NULL, 0u, eventMask); -} - -status_t I2C_SlaveSetReceiveBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, NULL, 0u, rxData, rxSize, eventMask); -} - -void I2C_SlaveSetAddress(I2C_Type *base, - i2c_slave_address_register_t addressRegister, - uint8_t address, - bool addressDisable) -{ - base->SLVADR[addressRegister] = I2C_SLVADR_SLVADR(address) | I2C_SLVADR_SADISABLE(addressDisable); -} - -void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) -{ - assert(slaveConfig); - - i2c_slave_config_t mySlaveConfig = {0}; - - /* default config enables slave address 0 match to general I2C call address zero */ - mySlaveConfig.enableSlave = true; - mySlaveConfig.address1.addressDisable = true; - mySlaveConfig.address2.addressDisable = true; - mySlaveConfig.address3.addressDisable = true; - - *slaveConfig = mySlaveConfig; -} - -status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz) -{ - status_t status; - uint32_t divVal = 0; - - /* configure data setup time used when slave stretches clock */ - status = I2C_SlaveDivVal(srcClock_Hz, slaveConfig->busSpeed, &divVal); - if (kStatus_Success != status) - { - return status; - } - - FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); - - /* I2C Clock Divider register */ - base->CLKDIV = divVal; - - /* set Slave address */ - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister0, slaveConfig->address0.address, - slaveConfig->address0.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister1, slaveConfig->address1.address, - slaveConfig->address1.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister2, slaveConfig->address2.address, - slaveConfig->address2.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister3, slaveConfig->address3.address, - slaveConfig->address3.addressDisable); - - /* set Slave address 0 qual */ - base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(slaveConfig->qualMode) | I2C_SLVQUAL0_SLVQUAL0(slaveConfig->qualAddress); - - /* set Slave enable */ - base->CFG = I2C_CFG_SLVEN(slaveConfig->enableSlave); - - return status; -} - -void I2C_SlaveDeinit(I2C_Type *base) -{ - I2C_SlaveEnable(base, false); -} - -status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) -{ - const uint8_t *buf = txBuff; - uint32_t stat; - bool slaveAddress; - bool slaveTransmit; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - - /* Get slave machine state */ - slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); - slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX); - - /* in I2C_SlaveSend() it shall be either slaveAddress or slaveTransmit */ - if (!(slaveAddress || slaveTransmit)) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - if (slaveAddress) - { - /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - - /* send bytes up to txSize */ - while (txSize) - { - slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX); - - if (!slaveTransmit) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - /* Write 8 bits of data to the SLVDAT register */ - base->SLVDAT = I2C_SLVDAT_DATA(*buf); - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* advance counters and pointers for next data */ - buf++; - txSize--; - - if (txSize) - { - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - } - - return kStatus_Success; -} - -status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) -{ - uint8_t *buf = rxBuff; - uint32_t stat; - bool slaveAddress; - bool slaveReceive; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - - /* Get slave machine state */ - slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); - slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX); - - /* in I2C_SlaveReceive() it shall be either slaveAddress or slaveReceive */ - if (!(slaveAddress || slaveReceive)) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - if (slaveAddress) - { - /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - - /* receive bytes up to rxSize */ - while (rxSize) - { - slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX); - - if (!slaveReceive) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - /* Read 8 bits of data from the SLVDAT register */ - *buf = (uint8_t)base->SLVDAT; - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* advance counters and pointers for next data */ - buf++; - rxSize--; - - if (rxSize) - { - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - } - - return kStatus_Success; -} - -void I2C_SlaveTransferCreateHandle(I2C_Type *base, - i2c_slave_handle_t *handle, - i2c_slave_transfer_callback_t callback, - void *userData) -{ - uint32_t instance; - - assert(handle); - - /* Clear out the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Save base and instance. */ - handle->callback = callback; - handle->userData = userData; - - /* initialize fsm */ - handle->slaveFsm = kI2C_SlaveFsmAddressMatch; - - /* store pointer to handle into transfer struct */ - handle->transfer.handle = handle; - - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2C_SlaveTransferHandleIRQ, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags); - EnableIRQ(s_i2cIRQ[instance]); -} - -status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, handle, NULL, 0u, NULL, 0u, eventMask); -} - -status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (!handle->isBusy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* For an active transfer, just return the count from the handle. */ - *count = handle->transfer.transferredCount; - - return kStatus_Success; -} - -void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) -{ - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags); - - /* Set the SLVEN bit to 0 in the CFG register. */ - I2C_SlaveEnable(base, false); - - handle->isBusy = false; - handle->transfer.txSize = 0; - handle->transfer.rxSize = 0; -} - -void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle) -{ - uint32_t i2cStatus = base->STAT; - - if (i2cStatus & I2C_STAT_SLVDESEL_MASK) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveDeselectedEvent); - I2C_SlaveClearStatusFlags(base, I2C_STAT_SLVDESEL_MASK); - } - - /* SLVPENDING flag is cleared by writing I2C_SLVCTL_SLVCONTINUE_MASK to SLVCTL register */ - if (i2cStatus & I2C_STAT_SLVPENDING_MASK) - { - bool slaveAddress = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); - - if (slaveAddress) - { - I2C_SlaveAddressIRQ(base, handle); - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveAddressMatchEvent); - } - else - { - switch (handle->slaveFsm) - { - case kI2C_SlaveFsmReceive: - { - bool slaveReceive = - (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX); - - if (slaveReceive) - { - /* if we have no receive buffer in this transfer, call callback to get new */ - if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); - } - - /* receive a byte */ - if ((handle->transfer.rxData) && (handle->transfer.rxSize)) - { - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - *(handle->transfer.rxData) = (uint8_t)base->SLVDAT; - (handle->transfer.rxSize)--; - (handle->transfer.rxData)++; - (handle->transfer.transferredCount)++; - } - - /* is this last transaction for this transfer? allow next transaction */ - if ((0 == handle->transfer.rxSize) && (0 == handle->transfer.txSize)) - { - handle->isBusy = false; - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); - } - } - else - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - } - } - break; - - case kI2C_SlaveFsmTransmit: - { - bool slaveTransmit = - (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX); - - if (slaveTransmit) - { - /* if we have no data in this transfer, call callback to get new */ - if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); - } - - /* transmit a byte */ - if ((handle->transfer.txData) && (handle->transfer.txSize)) - { - base->SLVDAT = *(handle->transfer.txData); - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - (handle->transfer.txSize)--; - (handle->transfer.txData)++; - (handle->transfer.transferredCount)++; - } - - /* is this last transaction for this transfer? allow next transaction */ - if ((0 == handle->transfer.rxSize) && (0 == handle->transfer.txSize)) - { - handle->isBusy = false; - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); - } - } - else - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - } - } - break; - - default: - /* incorrect state, slv_abort()? */ - break; - } - } - } -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c.h deleted file mode 100644 index 8afb082c07e..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c.h +++ /dev/null @@ -1,1067 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_I2C_H_ -#define _FSL_I2C_H_ - -#include -#include "fsl_device_registers.h" -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define I2C_CFG_MASK 0x1f - -/*! - * @addtogroup i2c_driver - * @{ - */ - -/*! @file */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2C driver version 2.0.3. */ -#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ - -/*! @brief Timeout times for waiting flag. */ -#ifndef I2C_WAIT_TIMEOUT -#define I2C_WAIT_TIMEOUT 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ -#endif - -/* definitions for MSTCODE bits in I2C Status register STAT */ -#define I2C_STAT_MSTCODE_IDLE (0) /*!< Master Idle State Code */ -#define I2C_STAT_MSTCODE_RXREADY (1) /*!< Master Receive Ready State Code */ -#define I2C_STAT_MSTCODE_TXREADY (2) /*!< Master Transmit Ready State Code */ -#define I2C_STAT_MSTCODE_NACKADR (3) /*!< Master NACK by slave on address State Code */ -#define I2C_STAT_MSTCODE_NACKDAT (4) /*!< Master NACK by slave on data State Code */ - -/* definitions for SLVSTATE bits in I2C Status register STAT */ -#define I2C_STAT_SLVST_ADDR (0) -#define I2C_STAT_SLVST_RX (1) -#define I2C_STAT_SLVST_TX (2) - -/*! @brief I2C status return codes. */ -enum _i2c_status -{ - kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 0), /*!< The master is already performing a transfer. */ - kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 1), /*!< The slave driver is idle. */ - kStatus_I2C_Nak = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 2), /*!< The slave device sent a NAK in response to a byte. */ - kStatus_I2C_InvalidParameter = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 3), /*!< Unable to proceed due to invalid parameter. */ - kStatus_I2C_BitError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 4), /*!< Transferred bit was not seen on the bus. */ - kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 5), /*!< Arbitration lost error. */ - kStatus_I2C_NoTransferInProgress = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 6), /*!< Attempt to abort a transfer when one is not in progress. */ - kStatus_I2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */ - kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8), - kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9), - kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 10), /*!< Timeout poling status flags. */ -}; - -/*! @} */ - -/*! - * @addtogroup i2c_master_driver - * @{ - */ - -/*! - * @brief I2C master peripheral flags. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -enum _i2c_master_flags -{ - kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. */ - kI2C_MasterArbitrationLostFlag = - I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus */ - kI2C_MasterStartStopErrorFlag = - I2C_STAT_MSTSTSTPERR_MASK /*!< There was an error during start or stop phase of the transaction. */ -}; - -/*! @brief Direction of master and slave transfers. */ -typedef enum _i2c_direction -{ - kI2C_Write = 0U, /*!< Master transmit. */ - kI2C_Read = 1U /*!< Master receive. */ -} i2c_direction_t; - -/*! - * @brief Structure with settings to initialize the I2C master module. - * - * This structure holds configuration settings for the I2C peripheral. To initialize this - * structure to reasonable defaults, call the I2C_MasterGetDefaultConfig() function and - * pass a pointer to your configuration structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _i2c_master_config -{ - bool enableMaster; /*!< Whether to enable master mode. */ - uint32_t baudRate_Bps; /*!< Desired baud rate in bits per second. */ - bool enableTimeout; /*!< Enable internal timeout function. */ -} i2c_master_config_t; - -/* Forward declaration of the transfer descriptor and handle typedefs. */ -/*! @brief I2C master transfer typedef */ -typedef struct _i2c_master_transfer i2c_master_transfer_t; - -/*! @brief I2C master handle typedef */ -typedef struct _i2c_master_handle i2c_master_handle_t; - -/*! - * @brief Master completion callback function pointer type. - * - * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use - * in the call to I2C_MasterTransferCreateHandle(). - * - * @param base The I2C peripheral base address. - * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, - i2c_master_handle_t *handle, - status_t completionStatus, - void *userData); - -/*! - * @brief Transfer option flags. - * - * @note These enumerations are intended to be OR'd together to form a bit mask of options for - * the #_i2c_master_transfer::flags field. - */ -enum _i2c_master_transfer_flags -{ - kI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ - kI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ - kI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ - kI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ -}; - -/*! @brief States for the state machine used by transactional APIs. */ -enum _i2c_transfer_states -{ - kIdleState = 0, - kTransmitSubaddrState, - kTransmitDataState, - kReceiveDataState, - kReceiveLastDataState, - kStartState, - kStopState, - kWaitForCompletionState -}; - -/*! - * @brief Non-blocking transfer descriptor structure. - * - * This structure is used to pass transaction parameters to the I2C_MasterTransferNonBlocking() API. - */ -struct _i2c_master_transfer -{ - uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i2c_master_transfer_flags for available - options. Set to 0 or #kI2C_TransferDefaultFlag for normal transfers. */ - uint16_t slaveAddress; /*!< The 7-bit slave address. */ - i2c_direction_t direction; /*!< Either #kI2C_Read or #kI2C_Write. */ - uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ - size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ - void *data; /*!< Pointer to data to transfer. */ - size_t dataSize; /*!< Number of bytes to transfer. */ -}; - -/*! - * @brief Driver handle for master non-blocking APIs. - * @note The contents of this structure are private and subject to change. - */ -struct _i2c_master_handle -{ - uint8_t state; /*!< Transfer state machine current state. */ - uint32_t transferCount; /*!< Indicates progress of the transfer */ - uint32_t remainingBytes; /*!< Remaining byte count in current state. */ - uint8_t *buf; /*!< Buffer pointer for current state. */ - uint32_t remainingSubaddr; - uint8_t subaddrBuf[4]; - i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ - i2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ - void *userData; /*!< Application data passed to callback. */ -}; - -/*! @} */ - -/*! - * @addtogroup i2c_slave_driver - * @{ - */ - -/*! -* @brief I2C slave peripheral flags. -* -* @note These enums are meant to be OR'd together to form a bit mask. -*/ -enum _i2c_slave_flags -{ - kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. */ - kI2C_SlaveNotStretching = - I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 = yes, 1 = no). */ - kI2C_SlaveSelected = I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. */ - kI2C_SaveDeselected = - I2C_STAT_SLVDESEL_MASK /*!< Indicates that slave was previously deselected (deselect event took place, w1c). */ -}; - -/*! @brief I2C slave address register. */ -typedef enum _i2c_slave_address_register -{ - kI2C_SlaveAddressRegister0 = 0U, /*!< Slave Address 0 register. */ - kI2C_SlaveAddressRegister1 = 1U, /*!< Slave Address 1 register. */ - kI2C_SlaveAddressRegister2 = 2U, /*!< Slave Address 2 register. */ - kI2C_SlaveAddressRegister3 = 3U, /*!< Slave Address 3 register. */ -} i2c_slave_address_register_t; - -/*! @brief Data structure with 7-bit Slave address and Slave address disable. */ -typedef struct _i2c_slave_address -{ - uint8_t address; /*!< 7-bit Slave address SLVADR. */ - bool addressDisable; /*!< Slave address disable SADISABLE. */ -} i2c_slave_address_t; - -/*! @brief I2C slave address match options. */ -typedef enum _i2c_slave_address_qual_mode -{ - kI2C_QualModeMask = 0U, /*!< The SLVQUAL0 field (qualAddress) is used as a logical mask for matching address0. */ - kI2C_QualModeExtend = - 1U, /*!< The SLVQUAL0 (qualAddress) field is used to extend address 0 matching in a range of addresses. */ -} i2c_slave_address_qual_mode_t; - -/*! @brief I2C slave bus speed options. */ -typedef enum _i2c_slave_bus_speed -{ - kI2C_SlaveStandardMode = 0U, - kI2C_SlaveFastMode = 1U, - kI2C_SlaveFastModePlus = 2U, - kI2C_SlaveHsMode = 3U, -} i2c_slave_bus_speed_t; - -/*! - * @brief Structure with settings to initialize the I2C slave module. - * - * This structure holds configuration settings for the I2C slave peripheral. To initialize this - * structure to reasonable defaults, call the I2C_SlaveGetDefaultConfig() function and - * pass a pointer to your configuration structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _i2c_slave_config -{ - i2c_slave_address_t address0; /*!< Slave's 7-bit address and disable. */ - i2c_slave_address_t address1; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_t address2; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_t address3; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_qual_mode_t qualMode; /*!< Qualify mode for slave address 0. */ - uint8_t qualAddress; /*!< Slave address qualifier for address 0. */ - i2c_slave_bus_speed_t - busSpeed; /*!< Slave bus speed mode. If the slave function stretches SCL to allow for software response, it must - provide sufficient data setup time to the master before releasing the stretched clock. - This is accomplished by inserting one clock time of CLKDIV at that point. - The #busSpeed value is used to configure CLKDIV - such that one clock time is greater than the tSU;DAT value noted - in the I2C bus specification for the I2C mode that is being used. - If the #busSpeed mode is unknown at compile time, use the longest data setup time - kI2C_SlaveStandardMode (250 ns) */ - bool enableSlave; /*!< Enable slave mode. */ -} i2c_slave_config_t; - -/*! - * @brief Set of events sent to the callback for non blocking slave transfers. - * - * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together - * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable. - * Then, when the slave callback is invoked, it is passed the current event through its @a transfer - * parameter. - * - * @note These enumerations are meant to be OR'd together to form a bit mask of events. - */ -typedef enum _i2c_slave_transfer_event -{ - kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ - kI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit - (slave-transmitter role). */ - kI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received - data (slave-receiver role). */ - kI2C_SlaveCompletionEvent = 0x20U, /*!< All data in the active transfer have been consumed. */ - kI2C_SlaveDeselectedEvent = - 0x40U, /*!< The slave function has become deselected (SLVSEL flag changing from 1 to 0. */ - - /*! Bit mask of all available events. */ - kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | - kI2C_SlaveCompletionEvent | kI2C_SlaveDeselectedEvent, -} i2c_slave_transfer_event_t; - -/*! @brief I2C slave handle typedef. */ -typedef struct _i2c_slave_handle i2c_slave_handle_t; - -/*! @brief I2C slave transfer structure */ -typedef struct _i2c_slave_transfer -{ - i2c_slave_handle_t *handle; /*!< Pointer to handle that contains this transfer. */ - i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ - uint8_t receivedAddress; /*!< Matching address send by master. 7-bits plus R/nW bit0 */ - uint32_t eventMask; /*!< Mask of enabled events. */ - uint8_t *rxData; /*!< Transfer buffer for receive data */ - const uint8_t *txData; /*!< Transfer buffer for transmit data */ - size_t txSize; /*!< Transfer size */ - size_t rxSize; /*!< Transfer size */ - size_t transferredCount; /*!< Number of bytes transferred during this transfer. */ - status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for - #kI2C_SlaveCompletionEvent. */ -} i2c_slave_transfer_t; - -/*! - * @brief Slave event callback function pointer type. - * - * This callback is used only for the slave non-blocking transfer API. To install a callback, - * use the I2C_SlaveSetCallback() function after you have created a handle. - * - * @param base Base address for the I2C instance on which the event occurred. - * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *userData); - -/*! - * @brief I2C slave software finite state machine states. - */ -typedef enum _i2c_slave_fsm -{ - kI2C_SlaveFsmAddressMatch = 0u, - kI2C_SlaveFsmReceive = 2u, - kI2C_SlaveFsmTransmit = 3u, -} i2c_slave_fsm_t; - -/*! - * @brief I2C slave handle structure. - * @note The contents of this structure are private and subject to change. - */ -struct _i2c_slave_handle -{ - volatile i2c_slave_transfer_t transfer; /*!< I2C slave transfer. */ - volatile bool isBusy; /*!< Whether transfer is busy. */ - volatile i2c_slave_fsm_t slaveFsm; /*!< slave transfer state machine. */ - i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ - void *userData; /*!< Callback parameter passed to callback. */ -}; - -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup i2c_master_driver - * @{ - */ - -/*! @name Initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the I2C master peripheral. - * - * This function provides the following default configuration for the I2C master peripheral: - * @code - * masterConfig->enableMaster = true; - * masterConfig->baudRate_Bps = 100000U; - * masterConfig->enableTimeout = false; - * @endcode - * - * After calling this function, you can override any settings in order to customize the configuration, - * prior to initializing the master driver with I2C_MasterInit(). - * - * @param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. - */ -void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); - -/*! - * @brief Initializes the I2C master peripheral. - * - * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user - * provided configuration. A software reset is performed prior to configuration. - * - * @param base The I2C peripheral base address. - * @param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of - * defaults - * that you can override. - * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, - * filter widths, and timeout periods. - */ -void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); - -/*! -* @brief Deinitializes the I2C master peripheral. -* - * This function disables the I2C master peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -void I2C_MasterDeinit(I2C_Type *base); - -/*! - * @brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * @param base The I2C peripheral base address. - * @return I2C instance number starting from 0. - */ -uint32_t I2C_GetInstance(I2C_Type *base); - -/*! - * @brief Performs a software reset. - * - * Restores the I2C master peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -static inline void I2C_MasterReset(I2C_Type *base) -{ -} - -/*! - * @brief Enables or disables the I2C module as master. - * - * @param base The I2C peripheral base address. - * @param enable Pass true to enable or false to disable the specified I2C as master. - */ -static inline void I2C_MasterEnable(I2C_Type *base, bool enable) -{ - if (enable) - { - base->CFG = (base->CFG & I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK; - } - else - { - base->CFG = (base->CFG & I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK; - } -} - -/*@}*/ - -/*! @name Status */ -/*@{*/ - -/*! - * @brief Gets the I2C status flags. - * - * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit - * in the return value is set if the flag is asserted. - * - * @param base The I2C peripheral base address. - * @return State of the status flags: - * - 1: related status flag is set. - * - 0: related status flag is not set. - * @see _i2c_master_flags - */ -static inline uint32_t I2C_GetStatusFlags(I2C_Type *base) -{ - return base->STAT; -} - -/*! - * @brief Clears the I2C master status flag state. - * - * The following status register flags can be cleared: - * - #kI2C_MasterArbitrationLostFlag - * - #kI2C_MasterStartStopErrorFlag - * - * Attempts to clear other flags has no effect. - * - * @param base The I2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * #_i2c_master_flags enumerators OR'd together. You may pass the result of a previous call to - * I2C_GetStatusFlags(). - * @see _i2c_master_flags. - */ -static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - /* Allow clearing just master status flags */ - base->STAT = statusMask & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); -} - -/*@}*/ - -/*! @name Interrupts */ -/*@{*/ - -/*! - * @brief Enables the I2C master interrupt requests. - * - * @param base The I2C peripheral base address. - * @param interruptMask Bit mask of interrupts to enable. See #_i2c_master_flags for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2C_EnableInterrupts(I2C_Type *base, uint32_t interruptMask) -{ - base->INTENSET = interruptMask; -} - -/*! - * @brief Disables the I2C master interrupt requests. - * - * @param base The I2C peripheral base address. - * @param interruptMask Bit mask of interrupts to disable. See #_i2c_master_flags for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2C_DisableInterrupts(I2C_Type *base, uint32_t interruptMask) -{ - base->INTENCLR = interruptMask; -} - -/*! - * @brief Returns the set of currently enabled I2C master interrupt requests. - * - * @param base The I2C peripheral base address. - * @return A bitmask composed of #_i2c_master_flags enumerators OR'd together to indicate the - * set of enabled interrupts. - */ -static inline uint32_t I2C_GetEnabledInterrupts(I2C_Type *base) -{ - return base->INTSTAT; -} - -/*@}*/ - -/*! @name Bus operations */ -/*@{*/ - -/*! - * @brief Sets the I2C bus frequency for master transactions. - * - * The I2C master is automatically disabled and re-enabled as necessary to configure the baud - * rate. Do not call this function during a transfer, or the transfer is aborted. - * - * @param base The I2C peripheral base address. - * @param srcClock_Hz I2C functional clock frequency in Hertz. - * @param baudRate_Bps Requested bus frequency in bits per second. - */ -void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Returns whether the bus is idle. - * - * Requires the master mode to be enabled. - * - * @param base The I2C peripheral base address. - * @retval true Bus is busy. - * @retval false Bus is idle. - */ -static inline bool I2C_MasterGetBusIdleState(I2C_Type *base) -{ - /* True if MSTPENDING flag is set and MSTSTATE is zero == idle */ - return ((base->STAT & (I2C_STAT_MSTPENDING_MASK | I2C_STAT_MSTSTATE_MASK)) == I2C_STAT_MSTPENDING_MASK); -} - -/*! - * @brief Sends a START on the I2C bus. - * - * This function is used to initiate a new master mode transfer by sending the START signal. - * The slave address is sent following the I2C START signal. - * - * @param base I2C peripheral base pointer - * @param address 7-bit slave device address. - * @param direction Master transfer directions(transmit/receive). - * @retval kStatus_Success Successfully send the start signal. - * @retval kStatus_I2C_Busy Current bus is busy. - */ -status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); - -/*! - * @brief Sends a STOP signal on the I2C bus. - * - * @retval kStatus_Success Successfully send the stop signal. - * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. - */ -status_t I2C_MasterStop(I2C_Type *base); - -/*! - * @brief Sends a REPEATED START on the I2C bus. - * - * @param base I2C peripheral base pointer - * @param address 7-bit slave device address. - * @param direction Master transfer directions(transmit/receive). - * @retval kStatus_Success Successfully send the start signal. - * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. - */ -static inline status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) -{ - return I2C_MasterStart(base, address, direction); -} - -/*! - * @brief Performs a polling send transfer on the I2C bus. - * - * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may - * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this - * function returns #kStatus_I2C_Nak. - * - * @param base The I2C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * @retval kStatus_Success Data was sent successfully. - * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags); - -/*! - * @brief Performs a polling receive transfer on the I2C bus. - * - * @param base The I2C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * @retval kStatus_Success Data was received successfully. - * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags); - -/*! - * @brief Performs a master polling transfer on the I2C bus. - * - * @note The API does not return until the transfer succeeds or fails due - * to arbitration lost or receiving a NAK. - * - * @param base I2C peripheral base address. - * @param xfer Pointer to the transfer structure. - * @retval kStatus_Success Successfully complete the data transmission. - * @retval kStatus_I2C_Busy Previous transmission still not finished. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - */ -status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); - -/*@}*/ - -/*! @name Non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the I2C master non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. - * - * @param base The I2C peripheral base address. - * @param[out] handle Pointer to the I2C master driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void I2C_MasterTransferCreateHandle(I2C_Type *base, - i2c_master_handle_t *handle, - i2c_master_transfer_callback_t callback, - void *userData); - -/*! - * @brief Performs a non-blocking transaction on the I2C bus. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @param xfer The pointer to the transfer descriptor. - * @retval kStatus_Success The transaction was started successfully. - * @retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking - * transaction is already in progress. - */ -status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Returns number of bytes transferred so far. - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @param[out] count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_Success - * @retval #kStatus_I2C_Busy - */ -status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); - -/*! - * @brief Terminates a non-blocking I2C master transmission early. - * - * @note It is not safe to call this function from an IRQ handler that has a higher priority than the - * I2C peripheral's IRQ priority. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @retval kStatus_Success A transaction was successfully aborted. - * @retval #kStatus_I2C_Timeout Timeout during polling for flags. - */ -status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); - -/*@}*/ - -/*! @name IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle master interrupts. - * @note This function does not need to be called unless you are reimplementing the - * nonblocking API's interrupt handler routines to add special functionality. - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - */ -void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle); - -/*@}*/ - -/*! @} */ /* end of i2c_master_driver */ - -/*! - * @addtogroup i2c_slave_driver - * @{ - */ - -/*! @name Slave initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the I2C slave peripheral. - * - * This function provides the following default configuration for the I2C slave peripheral: - * @code - * slaveConfig->enableSlave = true; - * slaveConfig->address0.disable = false; - * slaveConfig->address0.address = 0u; - * slaveConfig->address1.disable = true; - * slaveConfig->address2.disable = true; - * slaveConfig->address3.disable = true; - * slaveConfig->busSpeed = kI2C_SlaveStandardMode; - * @endcode - * - * After calling this function, override any settings to customize the configuration, - * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the @a - * address0.address member of the configuration structure with the desired slave address. - * - * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to - * #i2c_slave_config_t. - */ -void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); - -/*! - * @brief Initializes the I2C slave peripheral. - * - * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user - * provided configuration. - * - * @param base The I2C peripheral base address. - * @param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults - * that you can override. - * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide - * enough - * data setup time for master when slave stretches the clock. - */ -status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz); - -/*! - * @brief Configures Slave Address n register. - * - * This function writes new value to Slave Address register. - * - * @param base The I2C peripheral base address. - * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be - * changed. - * @param address The slave address to be stored to the address register for matching. - * @param addressDisable Disable matching of the specified address register. - */ -void I2C_SlaveSetAddress(I2C_Type *base, - i2c_slave_address_register_t addressRegister, - uint8_t address, - bool addressDisable); - -/*! -* @brief Deinitializes the I2C slave peripheral. -* - * This function disables the I2C slave peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -void I2C_SlaveDeinit(I2C_Type *base); - -/*! - * @brief Enables or disables the I2C module as slave. - * - * @param base The I2C peripheral base address. - * @param enable True to enable or flase to disable. - */ -static inline void I2C_SlaveEnable(I2C_Type *base, bool enable) -{ - /* Set or clear the SLVEN bit in the CFG register. */ - base->CFG = I2C_CFG_SLVEN(enable); -} - -/*@}*/ /* end of Slave initialization and deinitialization */ - -/*! @name Slave status */ -/*@{*/ - -/*! - * @brief Clears the I2C status flag state. - * - * The following status register flags can be cleared: - * - slave deselected flag - * - * Attempts to clear other flags has no effect. - * - * @param base The I2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * #_i2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to - * I2C_SlaveGetStatusFlags(). - * @see _i2c_slave_flags. - */ -static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - /* Allow clearing just slave status flags */ - base->STAT = statusMask & I2C_STAT_SLVDESEL_MASK; -} - -/*@}*/ /* end of Slave status */ - -/*! @name Slave bus operations */ -/*@{*/ - -/*! - * @brief Performs a polling send transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * @param base The I2C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @return kStatus_Success Data has been sent. - * @return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). - */ -status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); - -/*! - * @brief Performs a polling receive transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * @param base The I2C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @return kStatus_Success Data has been received. - * @return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). - */ -status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); - -/*@}*/ /* end of Slave bus operations */ - -/*! @name Slave non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the I2C slave non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. - * - * @param base The I2C peripheral base address. - * @param[out] handle Pointer to the I2C slave driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void I2C_SlaveTransferCreateHandle(I2C_Type *base, - i2c_slave_handle_t *handle, - i2c_slave_transfer_callback_t callback, - void *userData); - -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. - * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); - -/*! - * @brief Starts accepting master read from slave requests. - * - * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param transfer Pointer to #i2c_slave_transfer_t structure. - * @param txData Pointer to data to send to master. - * @param txSize Size of txData in bytes. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetSendBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask); - -/*! - * @brief Starts accepting master write to slave requests. - * - * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param transfer Pointer to #i2c_slave_transfer_t structure. - * @param rxData Pointer to data to store data from master. - * @param rxSize Size of rxData in bytes. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetReceiveBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask); - -/*! - * @brief Returns the slave address sent by the I2C master. - * - * This function should only be called from the address match event callback #kI2C_SlaveAddressMatchEvent. - * - * @param base The I2C peripheral base address. - * @param transfer The I2C slave transfer. - * @return The 8-bit address matched by the I2C slave. Bit 0 contains the R/w direction bit, and - * the 7-bit slave address is in the upper 7 bits. - */ -static inline uint32_t I2C_SlaveGetReceivedAddress(I2C_Type *base, volatile i2c_slave_transfer_t *transfer) -{ - return transfer->receivedAddress; -} - -/*! - * @brief Aborts the slave non-blocking transfers. - * @note This API could be called at any time to stop slave for handling the bus events. - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * @retval kStatus_Success - * @retval #kStatus_I2C_Idle - */ -void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); - -/*! - * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_slave_handle_t structure. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_InvalidArgument count is Invalid. - * @retval kStatus_Success Successfully return the count. - */ -status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); - -/*@}*/ /* end of Slave non-blocking */ - -/*! @name Slave IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle slave interrupts. - * @note This function does not need to be called unless you are reimplementing the - * non blocking API's interrupt handler routines to add special functionality. - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - */ -void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle); - -/*@}*/ /* end of Slave IRQ handler */ - -/*! @} */ /* end of i2c_slave_driver */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2C_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c_dma.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c_dma.c deleted file mode 100644 index f8de0ab241d..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c_dma.c +++ /dev/null @@ -1,581 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_i2c_dma.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c_dma" -#endif - - -/*transfer = *xfer; - transfer = &(handle->transfer); - - handle->transferCount = 0; - handle->remainingBytesDMA = 0; - handle->buf = (uint8_t *)transfer->data; - handle->remainingSubaddr = 0; - - if (transfer->flags & kI2C_TransferNoStartFlag) - { - /* Start condition shall be ommited, switch directly to next phase */ - if (transfer->dataSize == 0) - { - handle->state = kStopState; - } - else if (handle->transfer.direction == kI2C_Write) - { - handle->state = xfer->dataSize = kTransmitDataState; - } - else if (handle->transfer.direction == kI2C_Read) - { - handle->state = (xfer->dataSize == 1) ? kReceiveLastDataState : kReceiveDataState; - } - else - { - return kStatus_I2C_InvalidParameter; - } - } - else - { - if (transfer->subaddressSize != 0) - { - int i; - uint32_t subaddress; - - if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) - { - return kStatus_I2C_InvalidParameter; - } - - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = xfer->subaddressSize - 1; i >= 0; i--) - { - handle->subaddrBuf[i] = subaddress & 0xff; - subaddress >>= 8; - } - handle->remainingSubaddr = transfer->subaddressSize; - } - - handle->state = kStartState; - } - - return kStatus_Success; -} - -static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - int transfer_size; - dma_transfer_config_t xferConfig; - - /* Update transfer count */ - handle->transferCount = handle->buf - (uint8_t *)handle->transfer.data; - - /* Check if there is anything to be transferred at all */ - if (handle->remainingBytesDMA == 0) - { - /* No data to be transferrred, disable DMA */ - base->MSTCTL = 0; - return; - } - - /* Calculate transfer size */ - transfer_size = handle->remainingBytesDMA; - if (transfer_size > I2C_MAX_DMA_TRANSFER_COUNT) - { - transfer_size = I2C_MAX_DMA_TRANSFER_COUNT; - } - - switch (handle->transfer.direction) - { - case kI2C_Write: - DMA_PrepareTransfer(&xferConfig, handle->buf, (void *)&base->MSTDAT, sizeof(uint8_t), transfer_size, - kDMA_MemoryToPeripheral, NULL); - break; - - case kI2C_Read: - DMA_PrepareTransfer(&xferConfig, (void *)&base->MSTDAT, handle->buf, sizeof(uint8_t), transfer_size, - kDMA_PeripheralToMemory, NULL); - break; - - default: - /* This should never happen */ - assert(0); - break; - } - - DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - DMA_StartTransfer(handle->dmaHandle); - - handle->remainingBytesDMA -= transfer_size; - handle->buf += transfer_size; -} - -/*! - * @brief Execute states until the transfer is done. - * @param handle Master nonblocking driver handle. - * @param[out] isDone Set to true if the transfer has completed. - * @retval #kStatus_Success - * @retval #kStatus_I2C_ArbitrationLost - * @retval #kStatus_I2C_Nak - */ -static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone) -{ - uint32_t status; - uint32_t master_state; - struct _i2c_master_transfer *transfer; - dma_transfer_config_t xferConfig; - status_t err; - uint32_t start_flag = 0; - - transfer = &(handle->transfer); - - *isDone = false; - - status = I2C_GetStatusFlags(base); - - if (status & I2C_STAT_MSTARBLOSS_MASK) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_ArbitrationLost; - } - - if (status & I2C_STAT_MSTSTSTPERR_MASK) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_StartStopError; - } - - if ((status & I2C_STAT_MSTPENDING_MASK) == 0) - { - return kStatus_I2C_Busy; - } - - /* Get the state of the I2C module */ - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT)) - { - /* Slave NACKed last byte, issue stop and return error */ - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; - return kStatus_I2C_Nak; - } - - err = kStatus_Success; - - if (handle->state == kStartState) - { - /* set start flag for later use */ - start_flag = I2C_MSTCTL_MSTSTART_MASK; - - if (handle->remainingSubaddr) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = kTransmitSubaddrState; - } - else if (transfer->direction == kI2C_Write) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - if (transfer->dataSize == 0) - { - /* No data to be transferred, initiate start and schedule stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - handle->state = kStopState; - return err; - } - handle->state = kTransmitDataState; - } - else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0)) - { - base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; - if (transfer->dataSize == 1) - { - /* The very last byte is always received by means of SW */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - handle->state = kReceiveLastDataState; - return err; - } - handle->state = kReceiveDataState; - } - else - { - handle->state = kIdleState; - err = kStatus_I2C_UnexpectedState; - return err; - } - } - - switch (handle->state) - { - case kTransmitSubaddrState: - if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag)) - { - return kStatus_I2C_UnexpectedState; - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - - /* Prepare and submit DMA transfer. */ - DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (void *)&base->MSTDAT, sizeof(uint8_t), - handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL); - DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - DMA_StartTransfer(handle->dmaHandle); - handle->remainingSubaddr = 0; - if (transfer->dataSize) - { - /* There is data to be transferred, if there is write to read turnaround it is necessary to perform - * repeated start */ - handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState; - } - else - { - /* No more data, schedule stop condition */ - handle->state = kStopState; - } - break; - - case kTransmitDataState: - if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag)) - { - return kStatus_I2C_UnexpectedState; - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - handle->remainingBytesDMA = handle->transfer.dataSize; - - I2C_RunDMATransfer(base, handle); - - /* Schedule stop condition */ - handle->state = kStopState; - break; - - case kReceiveDataState: - if ((master_state != I2C_STAT_MSTCODE_RXREADY) && (!start_flag)) - { - return kStatus_I2C_UnexpectedState; - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - handle->remainingBytesDMA = handle->transfer.dataSize - 1; - - I2C_RunDMATransfer(base, handle); - - /* Schedule reception of last data byte */ - handle->state = kReceiveLastDataState; - break; - - case kReceiveLastDataState: - if (master_state != I2C_STAT_MSTCODE_RXREADY) - { - return kStatus_I2C_UnexpectedState; - } - - ((uint8_t *)transfer->data)[transfer->dataSize - 1] = base->MSTDAT; - handle->transferCount++; - - /* No more data expected, issue NACK and STOP right away */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; - break; - - case kStopState: - if (transfer->flags & kI2C_TransferNoStopFlag) - { - /* Stop condition is omitted, we are done */ - *isDone = true; - handle->state = kIdleState; - break; - } - /* Send stop condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; - break; - - case kWaitForCompletionState: - *isDone = true; - handle->state = kIdleState; - break; - - case kStartState: - case kIdleState: - default: - /* State machine shall not be invoked again once it enters the idle state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - return err; -} - -void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - bool isDone; - status_t result; - - /* Don't do anything if we don't have a valid handle. */ - if (!handle) - { - return; - } - - result = I2C_RunTransferStateMachineDMA(base, handle, &isDone); - - if (isDone || (result != kStatus_Success)) - { - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, - I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK); - - /* Invoke callback. */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } -} - -static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData) -{ - i2c_master_dma_private_handle_t *dmaPrivateHandle; - - /* Don't do anything if we don't have a valid handle. */ - if (!handle) - { - return; - } - - dmaPrivateHandle = (i2c_master_dma_private_handle_t *)userData; - I2C_RunDMATransfer(dmaPrivateHandle->base, dmaPrivateHandle->handle); -} - -void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, - i2c_master_dma_handle_t *handle, - i2c_master_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *dmaHandle) -{ - uint32_t instance; - - assert(handle); - assert(dmaHandle); - - /* Zero handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Set the user callback and userData. */ - handle->completionCallback = callback; - handle->userData = userData; - - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2C_MasterTransferDMAHandleIRQ, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, - I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK); - EnableIRQ(s_i2cIRQ[instance]); - - /* Set the handle for DMA. */ - handle->dmaHandle = dmaHandle; - - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - DMA_SetCallback(dmaHandle, (dma_callback)I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]); -} - -status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer) -{ - status_t result; - - assert(handle); - assert(xfer); - assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); - - /* Return busy if another transaction is in progress. */ - if (handle->state != kIdleState) - { - return kStatus_I2C_Busy; - } - - /* Prepare transfer state machine. */ - result = I2C_InitTransferStateMachineDMA(base, handle, xfer); - - /* Clear error flags. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Enable I2C internal IRQ sources */ - I2C_EnableInterrupts(base, - I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_MSTPENDING_MASK); - - return result; -} - -status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state == kIdleState) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* There is no necessity to disable interrupts as we read a single integer value */ - *count = handle->transferCount; - return kStatus_Success; -} - -void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - uint32_t status; - uint32_t master_state; - - if (handle->state != kIdleState) - { - DMA_AbortTransfer(handle->dmaHandle); - - /* Disable DMA */ - base->MSTCTL = 0; - - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, - I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK); - - /* Wait until module is ready */ - do - { - status = I2C_GetStatusFlags(base); - } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); - - /* Clear controller state. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Get the state of the I2C module */ - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if (master_state != I2C_STAT_MSTCODE_IDLE) - { - /* Send a stop command to finalize the transfer. */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - - /* Wait until module is ready */ - do - { - status = I2C_GetStatusFlags(base); - } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); - - /* Clear controller state. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - } - - /* Reset the state to idle. */ - handle->state = kIdleState; - } -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c_dma.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c_dma.h deleted file mode 100644 index 536a8ef3870..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c_dma.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_I2C_DMA_H_ -#define _FSL_I2C_DMA_H_ - -#include "fsl_i2c.h" -#include "fsl_dma.h" - -/*! - * @addtogroup i2c_dma_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2C DMA driver version 2.0.3. */ -#define FSL_I2C_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ - -/*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */ -#define I2C_MAX_DMA_TRANSFER_COUNT 1024 - -/*! @brief I2C master dma handle typedef. */ -typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t; - -/*! @brief I2C master dma transfer callback typedef. */ -typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base, - i2c_master_dma_handle_t *handle, - status_t status, - void *userData); - -/*! @brief I2C master dma transfer structure. */ -struct _i2c_master_dma_handle -{ - uint8_t state; /*!< Transfer state machine current state. */ - uint32_t transferCount; /*!< Indicates progress of the transfer */ - uint32_t remainingBytesDMA; /*!< Remaining byte count to be transferred using DMA. */ - uint8_t *buf; /*!< Buffer pointer for current state. */ - uint32_t remainingSubaddr; - uint8_t subaddrBuf[4]; - dma_handle_t *dmaHandle; /*!< The DMA handler used. */ - i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ - i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */ - void *userData; /*!< Callback parameter passed to callback function. */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus. */ - -/*! - * @name I2C Block DMA Transfer Operation - * @{ - */ - -/*! - * @brief Init the I2C handle which is used in transcational functions - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param callback pointer to user callback function - * @param userData user param passed to the callback function - * @param dmaHandle DMA handle pointer - */ -void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, - i2c_master_dma_handle_t *handle, - i2c_master_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *dmaHandle); - -/*! - * @brief Performs a master dma non-blocking transfer on the I2C bus - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param xfer pointer to transfer structure of i2c_master_transfer_t - * @retval kStatus_Success Sucessully complete the data transmission. - * @retval kStatus_I2C_Busy Previous transmission still not finished. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. - */ -status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Get master transfer status during a dma non-blocking transfer - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param count Number of bytes transferred so far by the non-blocking transaction. - */ -status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count); - -/*! - * @brief Abort a master dma non-blocking transfer in a early time - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - */ -void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle); - -/* @} */ -#if defined(__cplusplus) -} -#endif /*_cplusplus. */ -/*@}*/ -#endif /*_FSL_I2C_DMA_H_*/ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s.c deleted file mode 100644 index 4f1f0c53496..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s.c +++ /dev/null @@ -1,836 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_i2s.h" -#include "fsl_flexcomm.h" -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s" -#endif - -/* TODO - absent in device header files, should be there */ -#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) -#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) -#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) -#define I2S_FIFOCFG_PACK48_MASK (0x8U) -#define I2S_FIFOCFG_PACK48_SHIFT (3U) -#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) - -/*! @brief I2S states. */ -enum _i2s_state -{ - kI2S_StateIdle = 0x0, /*!< Not performing transfer */ - kI2S_StateTx, /*!< Performing transmit */ - kI2S_StateTxWaitToWriteDummyData, /*!< Wait on FIFO in order to write final dummy data there */ - kI2S_StateTxWaitForEmptyFifo, /*!< Wait for FIFO to be flushed */ - kI2S_StateRx, /*!< Performing receive */ -}; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -static void I2S_Config(I2S_Type *base, const i2s_config_t *config); -static void I2S_TxEnable(I2S_Type *base, bool enable); -static void I2S_RxEnable(I2S_Type *base, bool enable); -static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer); - -/******************************************************************************* - * Code - ******************************************************************************/ - -void I2S_TxInit(I2S_Type *base, const i2s_config_t *config) -{ - uint32_t cfg = 0U; - uint32_t trig = 0U; - - FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_TX); - I2S_Config(base, config); - - /* Configure FIFO */ - - cfg |= I2S_FIFOCFG_ENABLETX(1U); /* enable TX FIFO */ - cfg |= I2S_FIFOCFG_EMPTYTX(1U); /* empty TX FIFO */ - cfg |= I2S_FIFOCFG_TXI2SE0(config->txEmptyZero); /* transmit zero when buffer becomes empty or last item */ - cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ - trig |= I2S_FIFOTRIG_TXLVLENA(1U); /* enable TX FIFO trigger */ - trig |= I2S_FIFOTRIG_TXLVL(config->watermark); /* set TX FIFO trigger level */ - - base->FIFOCFG = cfg; - base->FIFOTRIG = trig; -} - -void I2S_RxInit(I2S_Type *base, const i2s_config_t *config) -{ - uint32_t cfg = 0U; - uint32_t trig = 0U; - - FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_RX); - I2S_Config(base, config); - - /* Configure FIFO */ - - cfg |= I2S_FIFOCFG_ENABLERX(1U); /* enable RX FIFO */ - cfg |= I2S_FIFOCFG_EMPTYRX(1U); /* empty RX FIFO */ - cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ - trig |= I2S_FIFOTRIG_RXLVLENA(1U); /* enable RX FIFO trigger */ - trig |= I2S_FIFOTRIG_RXLVL(config->watermark); /* set RX FIFO trigger level */ - - base->FIFOCFG = cfg; - base->FIFOTRIG = trig; -} - -void I2S_TxGetDefaultConfig(i2s_config_t *config) -{ - config->masterSlave = kI2S_MasterSlaveNormalMaster; - config->mode = kI2S_ModeI2sClassic; - config->rightLow = false; - config->leftJust = false; - config->pdmData = false; - config->sckPol = false; - config->wsPol = false; - config->divider = 1U; - config->oneChannel = false; - config->dataLength = 16U; - config->frameLength = 32U; - config->position = 0U; - config->watermark = 4U; - config->txEmptyZero = true; - config->pack48 = false; -} - -void I2S_RxGetDefaultConfig(i2s_config_t *config) -{ - config->masterSlave = kI2S_MasterSlaveNormalSlave; - config->mode = kI2S_ModeI2sClassic; - config->rightLow = false; - config->leftJust = false; - config->pdmData = false; - config->sckPol = false; - config->wsPol = false; - config->divider = 1U; - config->oneChannel = false; - config->dataLength = 16U; - config->frameLength = 32U; - config->position = 0U; - config->watermark = 4U; - config->txEmptyZero = false; - config->pack48 = false; -} - -static void I2S_Config(I2S_Type *base, const i2s_config_t *config) -{ - assert(config); - - uint32_t cfg1 = 0U; - uint32_t cfg2 = 0U; - - /* set master/slave configuration */ - cfg1 |= I2S_CFG1_MSTSLVCFG(config->masterSlave); - - /* set I2S mode */ - cfg1 |= I2S_CFG1_MODE(config->mode); - - /* set right low (channel swap) */ - cfg1 |= I2S_CFG1_RIGHTLOW(config->rightLow); - - /* set data justification */ - cfg1 |= I2S_CFG1_LEFTJUST(config->leftJust); - - /* set source to PDM dmic */ - cfg1 |= I2S_CFG1_PDMDATA(config->pdmData); - - /* set SCLK polarity */ - cfg1 |= I2S_CFG1_SCK_POL(config->sckPol); - - /* set WS polarity */ - cfg1 |= I2S_CFG1_WS_POL(config->wsPol); - - /* set mono mode */ - cfg1 |= I2S_CFG1_ONECHANNEL(config->oneChannel); - - /* set data length */ - cfg1 |= I2S_CFG1_DATALEN(config->dataLength - 1U); - - /* set frame length */ - cfg2 |= I2S_CFG2_FRAMELEN(config->frameLength - 1U); - - /* set data position of this channel pair within the frame */ - cfg2 |= I2S_CFG2_POSITION(config->position); - - /* write to registers */ - base->CFG1 = cfg1; - base->CFG2 = cfg2; - - /* set the clock divider */ - base->DIV = I2S_DIV_DIV(config->divider - 1U); -} - -void I2S_Deinit(I2S_Type *base) -{ - /* TODO gate FLEXCOMM clock via FLEXCOMM driver */ -} - -static void I2S_TxEnable(I2S_Type *base, bool enable) -{ - if (enable) - { - I2S_EnableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag); - I2S_Enable(base); - } - else - { - I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag); - I2S_Disable(base); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - } -} - -static void I2S_RxEnable(I2S_Type *base, bool enable) -{ - if (enable) - { - I2S_EnableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag); - I2S_Enable(base); - } - else - { - I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag); - I2S_Disable(base); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - } -} - -static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer) -{ - assert(transfer->data); - if (!transfer->data) - { - return kStatus_InvalidArgument; - } - - assert(transfer->dataSize > 0U); - if (transfer->dataSize <= 0U) - { - return kStatus_InvalidArgument; - } - - if (handle->dataLength == 4U) - { - /* No alignment and data length requirements */ - } - else if ((handle->dataLength >= 5U) && (handle->dataLength <= 8U)) - { - assert((((uint32_t)transfer->data) % 2U) == 0U); - if ((((uint32_t)transfer->data) % 2U) != 0U) - { - /* Data not 2-bytes aligned */ - return kStatus_InvalidArgument; - } - - assert((transfer->dataSize % 2U) == 0U); - if ((transfer->dataSize % 2U) != 0U) - { - /* Data not in pairs of left/right channel bytes */ - return kStatus_InvalidArgument; - } - } - else if ((handle->dataLength >= 9U) && (handle->dataLength <= 16U)) - { - assert((((uint32_t)transfer->data) % 4U) == 0U); - if ((((uint32_t)transfer->data) % 4U) != 0U) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - - assert((transfer->dataSize % 4U) == 0U); - if ((transfer->dataSize % 4U) != 0U) - { - /* Data lenght not multiply of 4 */ - return kStatus_InvalidArgument; - } - } - else if ((handle->dataLength >= 17U) && (handle->dataLength <= 24U)) - { - assert((transfer->dataSize % 6U) == 0U); - if ((transfer->dataSize % 6U) != 0U) - { - /* Data lenght not multiply of 6 */ - return kStatus_InvalidArgument; - } - - assert(!((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U))); - if ((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U)) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - } - else /* if (handle->dataLength >= 25U) */ - { - assert((((uint32_t)transfer->data) % 4U) == 0U); - if ((((uint32_t)transfer->data) % 4U) != 0U) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - - if (handle->oneChannel) - { - assert((transfer->dataSize % 4U) == 0U); - if ((transfer->dataSize % 4U) != 0U) - { - /* Data lenght not multiply of 4 */ - return kStatus_InvalidArgument; - } - } - else - { - assert((transfer->dataSize % 8U) == 0U); - if ((transfer->dataSize % 8U) != 0U) - { - /* Data lenght not multiply of 8 */ - return kStatus_InvalidArgument; - } - } - } - - return kStatus_Success; -} - -void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) -{ - assert(handle); - - /* Clear out the handle */ - memset(handle, 0U, sizeof(*handle)); - - /* Save callback and user data */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Remember some items set previously by configuration */ - handle->watermark = ((base->FIFOTRIG & I2S_FIFOTRIG_TXLVL_MASK) >> I2S_FIFOTRIG_TXLVL_SHIFT); - handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT); - handle->dataLength = ((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; - handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT); - - handle->useFifo48H = false; - - /* Register IRQ handling */ - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_TxHandleIRQ, handle); -} - -status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) -{ - assert(handle); - if (!handle) - { - return kStatus_InvalidArgument; - } - - status_t result; - - result = I2S_ValidateBuffer(handle, &transfer); - if (result != kStatus_Success) - { - return result; - } - - if (handle->i2sQueue[handle->queueUser].dataSize) - { - /* Previously prepared buffers not processed yet */ - return kStatus_I2S_Busy; - } - - handle->state = kI2S_StateTx; - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_TXLVL_MASK)) | I2S_FIFOTRIG_TXLVL(handle->watermark); - I2S_TxEnable(base, true); - - return kStatus_Success; -} - -void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle) -{ - assert(handle); - - /* Disable I2S operation and interrupts */ - I2S_TxEnable(base, false); - - /* Reset state */ - handle->state = kI2S_StateIdle; - - /* Clear transfer queue */ - memset((void *)&handle->i2sQueue, 0U, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); - handle->queueDriver = 0U; - handle->queueUser = 0U; -} - -void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) -{ - assert(handle); - - /* Clear out the handle */ - memset(handle, 0U, sizeof(*handle)); - - /* Save callback and user data */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Remember some items set previously by configuration */ - handle->watermark = ((base->FIFOTRIG & I2S_FIFOTRIG_RXLVL_MASK) >> I2S_FIFOTRIG_RXLVL_SHIFT); - handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT); - handle->dataLength = ((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; - handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT); - - handle->useFifo48H = false; - - /* Register IRQ handling */ - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_RxHandleIRQ, handle); -} - -status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) -{ - assert(handle); - if (!handle) - { - return kStatus_InvalidArgument; - } - - status_t result; - - result = I2S_ValidateBuffer(handle, &transfer); - if (result != kStatus_Success) - { - return result; - } - - if (handle->i2sQueue[handle->queueUser].dataSize) - { - /* Previously prepared buffers not processed yet */ - return kStatus_I2S_Busy; - } - - handle->state = kI2S_StateRx; - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_RXLVL_MASK)) | I2S_FIFOTRIG_RXLVL(handle->watermark); - I2S_RxEnable(base, true); - - return kStatus_Success; -} - -void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle) -{ - assert(handle); - - /* Disable I2S operation and interrupts */ - I2S_RxEnable(base, false); - - /* Reset state */ - handle->state = kI2S_StateIdle; - - /* Clear transfer queue */ - memset((void *)&handle->i2sQueue, 0U, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); - handle->queueDriver = 0U; - handle->queueUser = 0U; -} - -status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) -{ - assert(handle); - if (!handle) - { - return kStatus_InvalidArgument; - } - - assert(count); - if (!count) - { - return kStatus_InvalidArgument; - } - - if (handle->state == kI2S_StateIdle) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->transferCount; - - return kStatus_Success; -} - -status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) -{ - assert(handle); - if (!handle) - { - return kStatus_InvalidArgument; - } - - assert(count); - if (!count) - { - return kStatus_InvalidArgument; - } - - if (handle->state == kI2S_StateIdle) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->errorCount; - - return kStatus_Success; -} - -void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) -{ - uint32_t intstat = base->FIFOINTSTAT; - uint32_t data; - - if (intstat & I2S_FIFOINTSTAT_TXERR_MASK) - { - handle->errorCount++; - - /* Clear TX error interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_TXERR(1U); - } - - if (intstat & I2S_FIFOINTSTAT_TXLVL_MASK) - { - if (handle->state == kI2S_StateTx) - { - /* Send data */ - - while ((base->FIFOSTAT & I2S_FIFOSTAT_TXNOTFULL_MASK) && - (handle->i2sQueue[handle->queueDriver].dataSize > 0U)) - { - /* Write output data */ - if (handle->dataLength == 4U) - { - data = *(handle->i2sQueue[handle->queueDriver].data); - base->FIFOWR = ((data & 0xF0U) << 12U) | (data & 0xFU); - handle->i2sQueue[handle->queueDriver].data++; - handle->transferCount++; - handle->i2sQueue[handle->queueDriver].dataSize--; - } - else if (handle->dataLength <= 8U) - { - data = *((volatile uint16_t *)handle->i2sQueue[handle->queueDriver].data); - base->FIFOWR = ((data & 0xFF00U) << 8U) | (data & 0xFFU); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); - } - else if (handle->dataLength <= 16U) - { - base->FIFOWR = *((volatile uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); - } - else if (handle->dataLength <= 24U) - { - if (handle->pack48) - { - if (handle->useFifo48H) - { - base->FIFOWR48H = *((volatile uint16_t *)(handle->i2sQueue[handle->queueDriver].data)); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); - handle->useFifo48H = false; - } - else - { - base->FIFOWR = *((volatile uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); - handle->useFifo48H = true; - } - } - else - { - data = (uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++)); - data |= ((uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++))) << 8U; - data |= ((uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++))) << 16U; - if (handle->useFifo48H) - { - base->FIFOWR48H = data; - handle->useFifo48H = false; - } - else - { - base->FIFOWR = data; - handle->useFifo48H = true; - } - handle->transferCount += 3U; - handle->i2sQueue[handle->queueDriver].dataSize -= 3U; - } - } - else /* if (handle->dataLength <= 32U) */ - { - base->FIFOWR = *((volatile uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); - } - - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* Actual data buffer sent out, switch to a next one */ - handle->queueDriver = (handle->queueDriver + 1U) % I2S_NUM_BUFFERS; - - /* Notify user */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); - } - - /* Check if the next buffer contains anything to send */ - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* Everything has been written to FIFO */ - handle->state = kI2S_StateTxWaitToWriteDummyData; - break; - } - } - } - } - else if (handle->state == kI2S_StateTxWaitToWriteDummyData) - { - /* Write dummy data */ - if ((handle->dataLength > 16U) && (handle->dataLength < 25U)) - { - if (handle->useFifo48H) - { - base->FIFOWR48H = 0U; - handle->useFifo48H = false; - } - else - { - base->FIFOWR = 0U; - base->FIFOWR48H = 0U; - } - } - else - { - base->FIFOWR = 0U; - } - - /* Next time invoke this handler when FIFO becomes empty (TX level 0) */ - base->FIFOTRIG &= ~I2S_FIFOTRIG_TXLVL_MASK; - handle->state = kI2S_StateTxWaitForEmptyFifo; - } - else if (handle->state == kI2S_StateTxWaitForEmptyFifo) - { - /* FIFO, including additional dummy data, has been emptied now, - * all relevant data should have been output from peripheral */ - - /* Stop transfer */ - I2S_Disable(base); - I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - - /* Reset state */ - handle->state = kI2S_StateIdle; - - /* Notify user */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); - } - } - else - { - /* Do nothing */ - } - - /* Clear TX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_TXLVL(1U); - } -} - -void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) -{ - uint32_t intstat = base->FIFOINTSTAT; - uint32_t data; - - if (intstat & I2S_FIFOINTSTAT_RXERR_MASK) - { - handle->errorCount++; - - /* Clear RX error interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXERR(1U); - } - - if (intstat & I2S_FIFOINTSTAT_RXLVL_MASK) - { - while ((base->FIFOSTAT & I2S_FIFOSTAT_RXNOTEMPTY_MASK) && (handle->i2sQueue[handle->queueDriver].dataSize > 0U)) - { - /* Read input data */ - if (handle->dataLength == 4U) - { - data = base->FIFORD; - *(handle->i2sQueue[handle->queueDriver].data) = ((data & 0x000F0000U) >> 12U) | (data & 0x0000000FU); - handle->i2sQueue[handle->queueDriver].data++; - handle->transferCount++; - handle->i2sQueue[handle->queueDriver].dataSize--; - } - else if (handle->dataLength <= 8U) - { - data = base->FIFORD; - *((volatile uint16_t *)handle->i2sQueue[handle->queueDriver].data) = ((data >> 8U) & 0xFF00U) | (data & 0xFFU); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); - } - else if (handle->dataLength <= 16U) - { - data = base->FIFORD; - *((volatile uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); - } - else if (handle->dataLength <= 24U) - { - if (handle->pack48) - { - if (handle->useFifo48H) - { - data = base->FIFORD48H; - handle->useFifo48H = false; - - *((volatile uint16_t *)handle->i2sQueue[handle->queueDriver].data) = data; - handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); - } - else - { - data = base->FIFORD; - handle->useFifo48H = true; - - *((volatile uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); - } - } - else - { - if (handle->useFifo48H) - { - data = base->FIFORD48H; - handle->useFifo48H = false; - } - else - { - data = base->FIFORD; - handle->useFifo48H = true; - } - - *(handle->i2sQueue[handle->queueDriver].data++) = data & 0xFFU; - *(handle->i2sQueue[handle->queueDriver].data++) = (data >> 8U) & 0xFFU; - *(handle->i2sQueue[handle->queueDriver].data++) = (data >> 16U) & 0xFFU; - handle->transferCount += 3U; - handle->i2sQueue[handle->queueDriver].dataSize -= 3U; - } - } - else /* if (handle->dataLength <= 32U) */ - { - data = base->FIFORD; - *((volatile uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); - } - - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* Actual data buffer filled with input data, switch to a next one */ - handle->queueDriver = (handle->queueDriver + 1U) % I2S_NUM_BUFFERS; - - /* Notify user */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); - } - - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* No other buffer prepared to receive data into */ - - /* Disable I2S operation and interrupts */ - I2S_Disable(base); - I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - - /* Reset state */ - handle->state = kI2S_StateIdle; - - /* Notify user */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); - } - - /* Clear RX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); - - return; - } - } - } - - /* Clear RX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); - } -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s.h deleted file mode 100644 index 67d6b1bb124..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s.h +++ /dev/null @@ -1,490 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_I2S_H_ -#define _FSL_I2S_H_ - -#include "fsl_device_registers.h" -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup i2s_driver - * @{ - */ - -/*! @file */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2S driver version 2.0.1. - * - * Current version: 2.0.1 - * - * Change log: - * - Version 2.0.1 - * - Unify component full name to FLEXCOMM I2S(DMA) Driver - * - Version 2.0.0 - * - initial version - */ -#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -#ifndef I2S_NUM_BUFFERS - -/*! @brief Number of buffers . */ -#define I2S_NUM_BUFFERS (4) - -#endif - -/*! @brief I2S status codes. */ -enum _i2s_status -{ - kStatus_I2S_BufferComplete = - MAKE_STATUS(kStatusGroup_I2S, 0), /*!< Transfer from/into a single buffer has completed */ - kStatus_I2S_Done = MAKE_STATUS(kStatusGroup_I2S, 1), /*!< All buffers transfers have completed */ - kStatus_I2S_Busy = - MAKE_STATUS(kStatusGroup_I2S, 2), /*!< Already performing a transfer and cannot queue another buffer */ -}; - -/*! - * @brief I2S flags. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -typedef enum _i2s_flags -{ - kI2S_TxErrorFlag = I2S_FIFOINTENSET_TXERR_MASK, /*!< TX error interrupt */ - kI2S_TxLevelFlag = I2S_FIFOINTENSET_TXLVL_MASK, /*!< TX level interrupt */ - kI2S_RxErrorFlag = I2S_FIFOINTENSET_RXERR_MASK, /*!< RX error interrupt */ - kI2S_RxLevelFlag = I2S_FIFOINTENSET_RXLVL_MASK /*!< RX level interrupt */ -} i2s_flags_t; - -/*! @brief Master / slave mode. */ -typedef enum _i2s_master_slave -{ - kI2S_MasterSlaveNormalSlave = 0x0, /*!< Normal slave */ - kI2S_MasterSlaveWsSyncMaster = 0x1, /*!< WS synchronized master */ - kI2S_MasterSlaveExtSckMaster = 0x2, /*!< Master using existing SCK */ - kI2S_MasterSlaveNormalMaster = 0x3 /*!< Normal master */ -} i2s_master_slave_t; - -/*! @brief I2S mode. */ -typedef enum _i2s_mode -{ - kI2S_ModeI2sClassic = 0x0, /*!< I2S classic mode */ - kI2S_ModeDspWs50 = 0x1, /*!< DSP mode, WS having 50% duty cycle */ - kI2S_ModeDspWsShort = 0x2, /*!< DSP mode, WS having one clock long pulse */ - kI2S_ModeDspWsLong = 0x3 /*!< DSP mode, WS having one data slot long pulse */ -} i2s_mode_t; - -/*! @brief I2S configuration structure. */ -typedef struct _i2s_config -{ - i2s_master_slave_t masterSlave; /*!< Master / slave configuration */ - i2s_mode_t mode; /*!< I2S mode */ - bool rightLow; /*!< Right channel data in low portion of FIFO */ - bool leftJust; /*!< Left justify data in FIFO */ - bool pdmData; /*!< Data source is the D-Mic subsystem */ - bool sckPol; /*!< SCK polarity */ - bool wsPol; /*!< WS polarity */ - uint16_t divider; /*!< Flexcomm function clock divider (1 - 4096) */ - bool oneChannel; /*!< true mono, false stereo */ - uint8_t dataLength; /*!< Data length (4 - 32) */ - uint16_t frameLength; /*!< Frame width (4 - 512) */ - uint16_t position; /*!< Data position in the frame */ - uint8_t watermark; /*!< FIFO trigger level */ - bool txEmptyZero; /*!< Transmit zero when buffer becomes empty or last item */ - bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit - values) */ -} i2s_config_t; - -/*! @brief Buffer to transfer from or receive audio data into. */ -typedef struct _i2s_transfer -{ - volatile uint8_t *data; /*!< Pointer to data buffer. */ - volatile size_t dataSize; /*!< Buffer size in bytes. */ -} i2s_transfer_t; - -/*! @brief Transactional state of the intialized transfer or receive I2S operation. */ -typedef struct _i2s_handle i2s_handle_t; - -/*! - * @brief Callback function invoked from transactional API - * on completion of a single buffer transfer. - * - * @param base I2S base pointer. - * @param handle pointer to I2S transaction. - * @param completionStatus status of the transaction. - * @param userData optional pointer to user arguments data. - */ -typedef void (*i2s_transfer_callback_t)(I2S_Type *base, - i2s_handle_t *handle, - status_t completionStatus, - void *userData); - -/*! @brief Members not to be accessed / modified outside of the driver. */ -struct _i2s_handle -{ - uint32_t state; /*!< State of transfer */ - i2s_transfer_callback_t completionCallback; /*!< Callback function pointer */ - void *userData; /*!< Application data passed to callback */ - bool oneChannel; /*!< true mono, false stereo */ - uint8_t dataLength; /*!< Data length (4 - 32) */ - bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit - values) */ - bool useFifo48H; /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */ - volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ - volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ - volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ - volatile uint32_t errorCount; /*!< Number of buffer underruns/overruns */ - volatile uint32_t transferCount; /*!< Number of bytes transferred */ - volatile uint8_t watermark; /*!< FIFO trigger level */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S transmission using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_TxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the I2S driver. - * - * @param base I2S base pointer. - * @param config pointer to I2S configuration structure. - */ -void I2S_TxInit(I2S_Type *base, const i2s_config_t *config); - -/*! - * @brief Initializes the FLEXCOMM peripheral for I2S receive functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S receive using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_RxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the I2S driver. - * - * @param base I2S base pointer. - * @param config pointer to I2S configuration structure. - */ -void I2S_RxInit(I2S_Type *base, const i2s_config_t *config); - -/*! - * @brief Sets the I2S Tx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_TxInit(). - * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified - * before calling I2S_TxInit(). - * Example: - @code - i2s_config_t config; - I2S_TxGetDefaultConfig(&config); - @endcode - * - * Default values: - * @code - * config->masterSlave = kI2S_MasterSlaveNormalMaster; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = true; - * config->pack48 = false; - * @endcode - * - * @param config pointer to I2S configuration structure. - */ -void I2S_TxGetDefaultConfig(i2s_config_t *config); - -/*! - * @brief Sets the I2S Rx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_RxInit(). - * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified - * before calling I2S_RxInit(). - * Example: - @code - i2s_config_t config; - I2S_RxGetDefaultConfig(&config); - @endcode - * - * Default values: - * @code - * config->masterSlave = kI2S_MasterSlaveNormalSlave; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = false; - * config->pack48 = false; - * @endcode - * - * @param config pointer to I2S configuration structure. - */ -void I2S_RxGetDefaultConfig(i2s_config_t *config); - -/*! - * @brief De-initializes the I2S peripheral. - * - * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit - * or I2S_RxInit is called to enable the clock. - * - * @param base I2S base pointer. - */ -void I2S_Deinit(I2S_Type *base); - -/*! @} */ - -/*! - * @name Non-blocking API - * @{ - */ - -/*! - * @brief Initializes handle for transfer of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); - -/*! - * @brief Begins or queue sending of the given data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts sending of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Initializes handle for reception of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); - -/*! - * @brief Begins or queue reception of data into given buffer. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. - */ -status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts receiving of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Returns number of bytes transferred so far. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param[out] count number of bytes transferred so far by the non-blocking transaction. - * - * @retval kStatus_Success - * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); - -/*! - * @brief Returns number of buffer underruns or overruns. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param[out] count number of transmit errors encountered so far by the non-blocking transaction. - * - * @retval kStatus_Success - * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); - -/*! @} */ - -/*! - * @name Enable / disable - * @{ - */ - -/*! - * @brief Enables I2S operation. - * - * @param base I2S base pointer. - */ -static inline void I2S_Enable(I2S_Type *base) -{ - base->CFG1 |= I2S_CFG1_MAINENABLE(1U); -} - -/*! - * @brief Disables I2S operation. - * - * @param base I2S base pointer. - */ -static inline void I2S_Disable(I2S_Type *base) -{ - base->CFG1 &= (~I2S_CFG1_MAINENABLE(1U)); -} - -/*! @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables I2S FIFO interrupts. - * - * @param base I2S base pointer. - * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2S_EnableInterrupts(I2S_Type *base, uint32_t interruptMask) -{ - base->FIFOINTENSET = interruptMask; -} - -/*! - * @brief Disables I2S FIFO interrupts. - * - * @param base I2S base pointer. - * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2S_DisableInterrupts(I2S_Type *base, uint32_t interruptMask) -{ - base->FIFOINTENCLR = interruptMask; -} - -/*! - * @brief Returns the set of currently enabled I2S FIFO interrupts. - * - * @param base I2S base pointer. - * - * @return A bitmask composed of #i2s_flags_t enumerators OR'd together - * to indicate the set of enabled interrupts. - */ -static inline uint32_t I2S_GetEnabledInterrupts(I2S_Type *base) -{ - return base->FIFOINTENSET; -} - -/*! - * @brief Invoked from interrupt handler when transmit FIFO level decreases. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Invoked from interrupt handler when receive FIFO level decreases. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); - -/*! @} */ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2S_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s_dma.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s_dma.c deleted file mode 100644 index 04bf7f0c516..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s_dma.c +++ /dev/null @@ -1,636 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_dma.h" -#include "fsl_i2s_dma.h" -#include "fsl_flexcomm.h" -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s_dma" -#endif - - -#define DMA_MAX_TRANSFER_BYTES (DMA_MAX_TRANSFER_COUNT * sizeof(uint32_t)) -#define DMA_DESCRIPTORS (2U) - -/*i2sQueue[handle->queueUser].dataSize) - { - /* Previously prepared buffers not processed yet, reject request */ - return kStatus_I2S_Busy; - } - - /* Enqueue data */ - privateHandle->descriptorQueue[handle->queueUser].data = transfer.data; - privateHandle->descriptorQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - return kStatus_Success; -} - -static uint32_t I2S_GetInstance(I2S_Type *base) -{ - uint32_t i; - - for (i = 0U; i < ARRAY_SIZE(s_I2sBaseAddrs); i++) - { - if ((uint32_t)base == s_I2sBaseAddrs[i]) - { - return i; - } - } - - assert(false); - return 0U; -} - -static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle) -{ - DMA_DisableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); -} - -static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle) -{ - if (handle->state != kI2S_DmaStateIdle) - { - DMA_EnableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); - } -} - -void I2S_TxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData) -{ - assert(handle); - assert(dmaHandle); - - uint32_t instance = I2S_GetInstance(base); - i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - - memset(handle, 0U, sizeof(*handle)); - handle->state = kI2S_DmaStateIdle; - handle->dmaHandle = dmaHandle; - handle->completionCallback = callback; - handle->userData = userData; - - memset(privateHandle, 0U, sizeof(*privateHandle)); - privateHandle->base = base; - privateHandle->handle = handle; - - DMA_SetCallback(dmaHandle, I2S_DMACallback, privateHandle); -} - -status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) -{ - status_t status; - - I2S_DisableDMAInterrupts(handle); - - /* Enqueue transfer buffer */ - status = I2S_EnqueueUserBuffer(base, handle, transfer); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - - /* Initialize DMA transfer */ - if (handle->state == kI2S_DmaStateIdle) - { - handle->state = kI2S_DmaStateTx; - status = I2S_StartTransferDMA(base, handle); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - } - - I2S_AddTransferDMA(base, handle); - I2S_EnableDMAInterrupts(handle); - - return kStatus_Success; -} - -void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - assert(handle); - assert(handle->dmaHandle); - - uint32_t instance = I2S_GetInstance(base); - i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - - I2S_DisableDMAInterrupts(handle); - - /* Abort operation */ - DMA_AbortTransfer(handle->dmaHandle); - - if (handle->state == kI2S_DmaStateTx) - { - /* Wait until all transmitted data get out of FIFO */ - while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) - { - } - /* The last piece of valid data can be still being transmitted from I2S at this moment */ - - /* Write additional data to FIFO */ - base->FIFOWR = 0U; - while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) - { - } - /* At this moment the additional data are out of FIFO, starting being transmitted. - * This means the preceding valid data has been just transmitted and we can stop I2S. */ - I2S_TxEnableDMA(base, false); - } - else - { - I2S_RxEnableDMA(base, false); - } - - I2S_Disable(base); - - /* Reset state */ - handle->state = kI2S_DmaStateIdle; - - /* Clear transfer queue */ - memset((void *)&(handle->i2sQueue), 0U, sizeof(handle->i2sQueue)); - handle->queueDriver = 0U; - handle->queueUser = 0U; - - /* Clear internal state */ - memset((void *)&(privateHandle->descriptorQueue), 0U, sizeof(privateHandle->descriptorQueue)); - memset((void *)&(privateHandle->enqueuedBytes), 0U, sizeof(privateHandle->enqueuedBytes)); - privateHandle->enqueuedBytesStart = 0U; - privateHandle->enqueuedBytesEnd = 0U; - privateHandle->dmaDescriptorsUsed = 0U; - privateHandle->descriptor = 0U; - privateHandle->queueDescriptor = 0U; - privateHandle->intA = false; -} - -void I2S_RxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData) -{ - I2S_TxTransferCreateHandleDMA(base, handle, dmaHandle, callback, userData); -} - -status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) -{ - status_t status; - - I2S_DisableDMAInterrupts(handle); - - /* Enqueue transfer buffer */ - status = I2S_EnqueueUserBuffer(base, handle, transfer); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - - /* Initialize DMA transfer */ - if (handle->state == kI2S_DmaStateIdle) - { - handle->state = kI2S_DmaStateRx; - status = I2S_StartTransferDMA(base, handle); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - } - - I2S_AddTransferDMA(base, handle); - I2S_EnableDMAInterrupts(handle); - - return kStatus_Success; -} - -static void I2S_TxEnableDMA(I2S_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= I2S_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= (~I2S_FIFOCFG_DMATX_MASK); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - } -} - -static void I2S_RxEnableDMA(I2S_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= I2S_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= (~I2S_FIFOCFG_DMARX_MASK); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - } -} - -static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer) -{ - assert(transfer); - - uint16_t transferBytes; - - if (transfer->dataSize >= (2 * DMA_MAX_TRANSFER_BYTES)) - { - transferBytes = DMA_MAX_TRANSFER_BYTES; - } - else if (transfer->dataSize > DMA_MAX_TRANSFER_BYTES) - { - transferBytes = transfer->dataSize / 2U; - if ((transferBytes % 4U) != 0U) - { - transferBytes -= (transferBytes % 4U); - } - } - else - { - transferBytes = transfer->dataSize; - } - - return transferBytes; -} - -static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - status_t status; - dma_transfer_config_t xferConfig = {0}; - i2s_dma_private_handle_t *privateHandle; - volatile i2s_transfer_t *transfer; - uint16_t transferBytes; - uint32_t instance; - int i; - dma_descriptor_t *descriptor; - dma_descriptor_t *nextDescriptor; - dma_xfercfg_t xfercfg; - - instance = I2S_GetInstance(base); - privateHandle = &(s_DmaPrivateHandle[instance]); - transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); - - transferBytes = I2S_GetTransferBytes(transfer); - - /* Prepare transfer of data via initial DMA transfer descriptor */ - DMA_PrepareTransfer( - &xferConfig, (void *)((handle->state == kI2S_DmaStateTx) ? (uint32_t)transfer->data : (uint32_t)(&(base->FIFORD))), - (void *)((handle->state == kI2S_DmaStateTx) ? (uint32_t)(&(base->FIFOWR)) : (uint32_t)transfer->data), sizeof(uint32_t), - transferBytes, (handle->state == kI2S_DmaStateTx) ? kDMA_MemoryToPeripheral : kDMA_PeripheralToMemory, - (void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U])); - - /* Initial descriptor is stored in another place in memory, but treat it as another descriptor for simplicity */ - privateHandle->dmaDescriptorsUsed = 1U; - privateHandle->intA = false; - - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; - privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; - - transfer->dataSize -= transferBytes; - transfer->data += transferBytes; - - if (transfer->dataSize == 0U) - { - transfer->data = NULL; - privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; - } - - /* Link the DMA descriptors for the case when no additional transfer is queued before the initial one finishes */ - for (i = 0; i < DMA_DESCRIPTORS; i++) - { - descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + i]); - nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + ((i + 1) % DMA_DESCRIPTORS)]); - - xfercfg.valid = true; - xfercfg.reload = true; - xfercfg.swtrig = false; - xfercfg.clrtrig = false; - xfercfg.intA = false; - xfercfg.intB = false; - xfercfg.byteWidth = sizeof(uint32_t); - xfercfg.srcInc = 0U; - xfercfg.dstInc = 0U; - xfercfg.transferCount = 8U; - - DMA_CreateDescriptor(descriptor, &xfercfg, - ((handle->state == kI2S_DmaStateTx) ? (void *)&s_DummyBufferTx : (void *)(uint32_t)(&(base->FIFORD))), - ((handle->state == kI2S_DmaStateTx) ? (void *)(uint32_t)(&(base->FIFOWR)) : (void *)&s_DummyBufferRx), - (void *)nextDescriptor); - } - - /* Submit and start initial DMA transfer */ - - if (handle->state == kI2S_DmaStateTx) - { - I2S_TxEnableDMA(base, true); - } - else - { - I2S_RxEnableDMA(base, true); - } - - status = DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - if (status != kStatus_Success) - { - return status; - } - - DMA_StartTransfer(handle->dmaHandle); - - I2S_Enable(base); - return kStatus_Success; -} - -static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - dma_xfercfg_t xfercfg; - volatile i2s_transfer_t *transfer; - uint16_t transferBytes; - uint32_t instance; - i2s_dma_private_handle_t *privateHandle; - dma_descriptor_t *descriptor; - dma_descriptor_t *nextDescriptor; - uint32_t srcAddr = 0, destAddr = 0; - - instance = I2S_GetInstance(base); - privateHandle = &(s_DmaPrivateHandle[instance]); - - while (privateHandle->dmaDescriptorsUsed < DMA_DESCRIPTORS) - { - transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); - - if (transfer->dataSize == 0U) - { - /* Nothing to be added */ - return; - } - - /* Determine currently configured descriptor and the other which it will link to */ - descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); - privateHandle->descriptor = (privateHandle->descriptor + 1U) % DMA_DESCRIPTORS; - nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); - - transferBytes = I2S_GetTransferBytes(transfer); - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; - privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; - - /* Configure descriptor */ - - xfercfg.valid = true; - xfercfg.reload = true; - xfercfg.swtrig = false; - xfercfg.clrtrig = false; - xfercfg.intA = privateHandle->intA; - xfercfg.intB = !privateHandle->intA; - xfercfg.byteWidth = sizeof(uint32_t); - xfercfg.srcInc = (handle->state == kI2S_DmaStateTx) ? 1U : 0U; - xfercfg.dstInc = (handle->state == kI2S_DmaStateTx) ? 0U : 1U; - xfercfg.transferCount = transferBytes / sizeof(uint32_t); - srcAddr = ((handle->state == kI2S_DmaStateTx) ? (uint32_t)transfer->data : (uint32_t)&(base->FIFORD)); - destAddr = ((handle->state == kI2S_DmaStateTx) ? (uint32_t)&(base->FIFOWR) : (uint32_t)transfer->data); - - DMA_CreateDescriptor(descriptor, &xfercfg, (void *)srcAddr, (void *)destAddr, (void *)nextDescriptor); - - /* Advance internal state */ - - privateHandle->dmaDescriptorsUsed++; - privateHandle->intA = !privateHandle->intA; - - transfer->dataSize -= transferBytes; - transfer->data += transferBytes; - if (transfer->dataSize == 0U) - { - transfer->data = NULL; - privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; - } - } -} - -void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds) -{ - i2s_dma_private_handle_t *privateHandle = (i2s_dma_private_handle_t *)userData; - i2s_dma_handle_t *i2sHandle = privateHandle->handle; - I2S_Type *base = privateHandle->base; - - if ((!transferDone) || (i2sHandle->state == kI2S_DmaStateIdle)) - { - return; - } - - if (privateHandle->dmaDescriptorsUsed > 0U) - { - /* Finished descriptor, decrease amount of data to be processed */ - - i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize -= - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart]; - i2sHandle->i2sQueue[i2sHandle->queueDriver].data += - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart]; - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] = 0U; - privateHandle->enqueuedBytesStart = (privateHandle->enqueuedBytesStart + 1U) % DMA_DESCRIPTORS; - - privateHandle->dmaDescriptorsUsed--; - - if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U) - { - /* Entire user buffer sent or received - advance to next one */ - i2sHandle->i2sQueue[i2sHandle->queueDriver].data = NULL; - i2sHandle->queueDriver = (i2sHandle->queueDriver + 1U) % I2S_NUM_BUFFERS; - - /* Notify user about buffer completion */ - if (i2sHandle->completionCallback) - { - (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_BufferComplete, i2sHandle->userData); - } - } - } - - if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U) - { - /* All user buffers processed */ - I2S_TransferAbortDMA(base, i2sHandle); - - /* Notify user about completion of the final buffer */ - if (i2sHandle->completionCallback) - { - (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_Done, i2sHandle->userData); - } - } - else - { - /* Enqueue another user buffer to DMA if it could not be done when in I2S_Rx/TxTransferSendDMA */ - I2S_AddTransferDMA(base, i2sHandle); - } -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s_dma.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s_dma.h deleted file mode 100644 index 05d69147290..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s_dma.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_I2S_DMA_H_ -#define _FSL_I2S_DMA_H_ - -#include "fsl_device_registers.h" -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -#include "fsl_dma.h" -#include "fsl_i2s.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup i2s_dma_driver - * @{ - */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2S DMA driver version 2.0.1. */ -#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! @brief Members not to be accessed / modified outside of the driver. */ -typedef struct _i2s_dma_handle i2s_dma_handle_t; - -/*! - * @brief Callback function invoked from DMA API on completion. - * - * @param base I2S base pointer. - * @param handle pointer to I2S transaction. - * @param completionStatus status of the transaction. - * @param userData optional pointer to user arguments data. - */ -typedef void (*i2s_dma_transfer_callback_t)(I2S_Type *base, - i2s_dma_handle_t *handle, - status_t completionStatus, - void *userData); - -struct _i2s_dma_handle -{ - uint32_t state; /*!< Internal state of I2S DMA transfer */ - i2s_dma_transfer_callback_t completionCallback; /*!< Callback function pointer */ - void *userData; /*!< Application data passed to callback */ - dma_handle_t *dmaHandle; /*!< DMA handle */ - volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ - volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ - volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! @} */ - -/*! - * @name DMA API - * @{ - */ - -/*! - * @brief Initializes handle for transfer of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param dmaHandle pointer to dma handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData); - -/*! - * @brief Begins or queue sending of the given data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts transfer of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle); - -/*! - * @brief Initializes handle for reception of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param dmaHandle pointer to dma handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData); - -/*! - * @brief Begins or queue reception of data into given buffer. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers - * which are not full. - */ -status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Invoked from DMA interrupt handler. - * - * @param handle pointer to DMA handle structure. - * @param userData argument for user callback. - * @param transferDone if transfer was done. - * @param tcds - */ -void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds); - -/*! @} */ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2S_DMA_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_inputmux.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_inputmux.c deleted file mode 100644 index d671da93fe8..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_inputmux.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_inputmux.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.inputmux" -#endif - - -/******************************************************************************* - * Code - ******************************************************************************/ - -void INPUTMUX_Init(INPUTMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE - CLOCK_EnableClock(kCLOCK_Sct); - CLOCK_EnableClock(kCLOCK_Dma); -#else - CLOCK_EnableClock(kCLOCK_InputMux); -#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection) -{ - uint32_t pmux_id; - uint32_t output_id; - - /* extract pmux to be used */ - pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT; - /* extract function number */ - output_id = ((uint32_t)(connection)) & 0xffffU; - /* programm signal */ - *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4)) = output_id; -} - -#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) -void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable) -{ - uint32_t ena_id; - uint32_t bit_offset; - - /* extract enable register to be used */ - ena_id = ((uint32_t)(signal)) >> ENA_SHIFT; - /* extract enable bit offset */ - bit_offset = ((uint32_t)(signal)) & 0xfU; - /* set signal */ - if (enable) - { - *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1U << bit_offset); - } - else - { - *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1U << bit_offset); - } -} -#endif - -void INPUTMUX_Deinit(INPUTMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE - CLOCK_DisableClock(kCLOCK_Sct); - CLOCK_DisableClock(kCLOCK_Dma); -#else - CLOCK_DisableClock(kCLOCK_InputMux); -#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_inputmux.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_inputmux.h deleted file mode 100644 index cdfda5bd6a0..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_inputmux.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_INPUTMUX_H_ -#define _FSL_INPUTMUX_H_ - -#include "fsl_inputmux_connections.h" -#include "fsl_common.h" - -/*! - * @addtogroup inputmux_driver - * @{ - */ - -/*! @file */ -/*! @file fsl_inputmux_connections.h */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Group interrupt driver version for SDK */ -#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ - /*@}*/ - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @brief Initialize INPUTMUX peripheral. - - * This function enables the INPUTMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * - * @retval None. - */ -void INPUTMUX_Init(INPUTMUX_Type *base); - -/*! - * @brief Attaches a signal - * - * This function gates the INPUTPMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * @param index Destination peripheral to attach the signal to. - * @param connection Selects connection. - * - * @retval None. -*/ -void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection); - -#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) -/*! - * @brief Enable/disable a signal - * - * This function gates the INPUTPMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * @param signal Enable signal register id and bit offset. - * @param enable Selects enable or disable. - * - * @retval None. -*/ -void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable); -#endif - -/*! - * @brief Deinitialize INPUTMUX peripheral. - - * This function disables the INPUTMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * - * @retval None. - */ -void INPUTMUX_Deinit(INPUTMUX_Type *base); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_INPUTMUX_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_inputmux_connections.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_inputmux_connections.h deleted file mode 100644 index 23e9cfe9dc2..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_inputmux_connections.h +++ /dev/null @@ -1,183 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016, NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_INPUTMUX_CONNECTIONS_ -#define _FSL_INPUTMUX_CONNECTIONS_ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" -#endif - -/*! - * @addtogroup inputmux_driver - * @{ - */ - -/*! @brief Periphinmux IDs */ -#define PINTSEL_PMUX_ID 0xC0U -#define DMA_TRIG0_PMUX_ID 0xE0U -#define DMA_OTRIG_PMUX_ID 0x160U -#define FREQMEAS_PMUX_ID 0x180U -#define PMUX_SHIFT 20U - -/*! @brief INPUTMUX connections type */ -typedef enum _inputmux_connection_t -{ - /*!< Frequency measure. */ - kINPUTMUX_MainOscToFreqmeas = 0U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Fro12MhzToFreqmeas = 1U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_WdtOscToFreqmeas = 2U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_32KhzOscToFreqmeas = 3U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_MainClkToFreqmeas = 4U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin4ToFreqmeas = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin20ToFreqmeas = 6U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin24ToFreqmeas = 7U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin4ToFreqmeas = 8U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), - /*!< Pin Interrupt. */ - kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - /*!< DMA ITRIG. */ - kINPUTMUX_Adc0SeqaIrqToDma = 0U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_ADC0SeqbIrqToDma = 1U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq0ToDma = 2U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq1ToDma = 3U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToDma = 4U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer0M1ToDma = 5U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToDma = 6U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToDma = 7U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer2M1ToDma = 8U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToDma = 9U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToDma = 10U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer4M1ToDma = 11U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_PinInt0ToDma = 12U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_PinInt1ToDma = 13U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_PinInt2ToDma = 14U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_PinInt3ToDma = 15U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Otrig0ToDma = 16U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Otrig1ToDma = 17U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Otrig2ToDma = 18U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Otrig3ToDma = 19U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - /*!< DMA OTRIG. */ - kINPUTMUX_DmaFlexcomm0RxTrigoutToTriginChannels = 0U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm0TxTrigoutToTriginChannels = 1U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm1RxTrigoutToTriginChannels = 2U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm1TxTrigoutToTriginChannels = 3U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm2RxTrigoutToTriginChannels = 4U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm2TxTrigoutToTriginChannels = 5U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm3RxTrigoutToTriginChannels = 6U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm3TxTrigoutToTriginChannels = 7U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm4RxTrigoutToTriginChannels = 8U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm4TxTrigoutToTriginChannels = 9U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm5RxTrigoutToTriginChannels = 10U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm5TxTrigoutToTriginChannels = 11U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm6RxTrigoutToTriginChannels = 12U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm6TxTrigoutToTriginChannels = 13U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm7RxTrigoutToTriginChannels = 14U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm7TxTrigoutToTriginChannels = 15U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaDmic0Ch0TrigoutToTriginChannels = 16U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Dmamic0Ch1TrigoutToTriginChannels = 17U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaSpifi0TrigoutToTriginChannels = 18U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaChannel19_TrigoutToTriginChannels = 19U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), -} inputmux_connection_t; - -/*@}*/ - -#endif /* _FSL_INPUTMUX_CONNECTIONS_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_iocon.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_iocon.h deleted file mode 100644 index a577a7eece8..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_iocon.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_IOCON_H_ -#define _FSL_IOCON_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_iocon - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon" -#endif - - -/*! @name Driver version */ -/*@{*/ -/*! @brief IOCON driver version 2.0.0. */ -#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/** - * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format - */ -typedef struct _iocon_group -{ - uint32_t port : 8; /* Pin port */ - uint32_t pin : 8; /* Pin number */ - uint32_t ionumber : 8; /* IO number */ - uint32_t modefunc : 16; /* Function and mode */ -} iocon_group_t; - -/** - * @brief IOCON function and mode selection definitions - * @note See the User Manual for specific modes and functions supported by the various pins. - */ -#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) -#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ -#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ -#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ -#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ -#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ -#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ -#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ -#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ -#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ -#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ -#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ -#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ -#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ -#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ -#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ -#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ -#define IOCON_MODE_INACT (0x0 << 4) /*!< No addition pin function */ -#define IOCON_MODE_PULLDOWN (0x1 << 4) /*!< Selects pull-down function */ -#define IOCON_MODE_PULLUP (0x2 << 4) /*!< Selects pull-up function */ -#define IOCON_MODE_REPEATER (0x3 << 4) /*!< Selects pin repeater function */ -#define IOCON_HYS_EN (0x1 << 6) /*!< Enables hysteresis */ -#define IOCON_GPIO_MODE (0x1 << 6) /*!< GPIO Mode */ -#define IOCON_I2C_SLEW (0x0 << 6) /*!< I2C Slew Rate Control */ -#define IOCON_INV_EN (0x1 << 7) /*!< Enables invert function on input */ -#define IOCON_ANALOG_EN (0x0 << 8) /*!< Enables analog function by setting 0 to bit 7 */ -#define IOCON_DIGITAL_EN (0x1 << 8) /*!< Enables digital function by setting 1 to bit 7(default) */ -#define IOCON_STDI2C_EN (0x1 << 9) /*!< I2C standard mode/fast-mode */ -#define IOCON_FASTI2C_EN (0x3 << 9) /*!< I2C Fast-mode Plus and high-speed slave */ -#define IOCON_INPFILT_OFF (0x1 << 9) /*!< Input filter Off for GPIO pins */ -#define IOCON_INPFILT_ON (0x0 << 9) /*!< Input filter On for GPIO pins */ -#define IOCON_OPENDRAIN_EN (0x1 << 11) /*!< Enables open-drain function */ -#define IOCON_S_MODE_0CLK (0x0 << 12) /*!< Bypass input filter */ -#define IOCON_S_MODE_1CLK (0x1 << 12) /*!< Input pulses shorter than 1 filter clock are rejected */ -#define IOCON_S_MODE_2CLK (0x2 << 12) /*!< Input pulses shorter than 2 filter clock2 are rejected */ -#define IOCON_S_MODE_3CLK (0x3 << 12) /*!< Input pulses shorter than 3 filter clock2 are rejected */ -#define IOCON_S_MODE(clks) ((clks) << 12) /*!< Select clocks for digital input filter mode */ -#define IOCON_CLKDIV(div) \ - ((div) << 14) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ -#else -#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ -#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ -#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ -#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ -#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ -#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ -#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ -#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ -#define IOCON_MODE_INACT (0x0 << 3) /*!< No addition pin function */ -#define IOCON_MODE_PULLDOWN (0x1 << 3) /*!< Selects pull-down function */ -#define IOCON_MODE_PULLUP (0x2 << 3) /*!< Selects pull-up function */ -#define IOCON_MODE_REPEATER (0x3 << 3) /*!< Selects pin repeater function */ -#define IOCON_HYS_EN (0x1 << 5) /*!< Enables hysteresis */ -#define IOCON_GPIO_MODE (0x1 << 5) /*!< GPIO Mode */ -#define IOCON_I2C_SLEW (0x0 << 5) /*!< I2C Slew Rate Control */ -#define IOCON_INV_EN (0x1 << 6) /*!< Enables invert function on input */ -#define IOCON_ANALOG_EN (0x0 << 7) /*!< Enables analog function by setting 0 to bit 7 */ -#define IOCON_DIGITAL_EN (0x1 << 7) /*!< Enables digital function by setting 1 to bit 7(default) */ -#define IOCON_STDI2C_EN (0x1 << 8) /*!< I2C standard mode/fast-mode */ -#define IOCON_FASTI2C_EN (0x3 << 8) /*!< I2C Fast-mode Plus and high-speed slave */ -#define IOCON_INPFILT_OFF (0x1 << 8) /*!< Input filter Off for GPIO pins */ -#define IOCON_INPFILT_ON (0x0 << 8) /*!< Input filter On for GPIO pins */ -#define IOCON_OPENDRAIN_EN (0x1 << 10) /*!< Enables open-drain function */ -#define IOCON_S_MODE_0CLK (0x0 << 11) /*!< Bypass input filter */ -#define IOCON_S_MODE_1CLK (0x1 << 11) /*!< Input pulses shorter than 1 filter clock are rejected */ -#define IOCON_S_MODE_2CLK (0x2 << 11) /*!< Input pulses shorter than 2 filter clock2 are rejected */ -#define IOCON_S_MODE_3CLK (0x3 << 11) /*!< Input pulses shorter than 3 filter clock2 are rejected */ -#define IOCON_S_MODE(clks) ((clks) << 11) /*!< Select clocks for digital input filter mode */ -#define IOCON_CLKDIV(div) \ - ((div) << 13) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ -#endif -#if defined(__cplusplus) -extern "C" { -#endif - -#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) -/** - * @brief Sets I/O Control pin mux - * @param base : The base of IOCON peripheral on the chip - * @param ionumber : GPIO number to mux - * @param modefunc : OR'ed values of type IOCON_* - * @return Nothing - */ -__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc) -{ - base->PIO[ionumber] = modefunc; -} -#else -/** - * @brief Sets I/O Control pin mux - * @param base : The base of IOCON peripheral on the chip - * @param port : GPIO port to mux - * @param pin : GPIO pin to mux - * @param modefunc : OR'ed values of type IOCON_* - * @return Nothing - */ -__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc) -{ - base->PIO[port][pin] = modefunc; -} -#endif - -/** - * @brief Set all I/O Control pin muxing - * @param base : The base of IOCON peripheral on the chip - * @param pinArray : Pointer to array of pin mux selections - * @param arrayLength : Number of entries in pinArray - * @return Nothing - */ -__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength) -{ - uint32_t i; - - for (i = 0; i < arrayLength; i++) - { -#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) - IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc); -#else - IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc); -#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */ - } -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_IOCON_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_mailbox.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_mailbox.h deleted file mode 100644 index df10337c5dc..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_mailbox.h +++ /dev/null @@ -1,210 +0,0 @@ -/* - * The Clear BSD License - * Copyright(C) NXP Semiconductors, 2014 - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_MAILBOX_H_ -#define _FSL_MAILBOX_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup mailbox - * @{ - */ - -/*! @file */ - -/****************************************************************************** - * Definitions - *****************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.mailbox" -#endif - - -/*! @name Driver version */ -/*@{*/ -/*! @brief MAILBOX driver version 2.0.0. */ -#define FSL_MAILBOX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! - * @brief CPU ID. - */ -typedef enum _mailbox_cpu_id -{ - kMAILBOX_CM0Plus = 0, - kMAILBOX_CM4 -} mailbox_cpu_id_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @name MAILBOX initialization - * @{ - */ - -/*! - * @brief Initializes the MAILBOX module. - * - * This function enables the MAILBOX clock only. - * - * @param base MAILBOX peripheral base address. - */ -static inline void MAILBOX_Init(MAILBOX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Mailbox); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief De-initializes the MAILBOX module. - * - * This function disables the MAILBOX clock only. - * - * @param base MAILBOX peripheral base address. - */ -static inline void MAILBOX_Deinit(MAILBOX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Mailbox); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/* @} */ - -/*! - * @brief Set data value in the mailbox based on the CPU ID. - * - * @param base MAILBOX peripheral base address. - * @param cpu_id CPU id, kMAILBOX_CM0Plus is M0+ or kMAILBOX_CM4 is M4. - * @param mboxData Data to send in the mailbox. - * - * @note Sets a data value to send via the MAILBOX to the other core. - */ -static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxData) -{ - assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); - base->MBOXIRQ[cpu_id].IRQ = mboxData; -} - -/*! - * @brief Get data in the mailbox based on the CPU ID. - * - * @param base MAILBOX peripheral base address. - * @param cpu_id CPU id, kMAILBOX_CM0Plus is M0+ or kMAILBOX_CM4 is M4. - * - * @return Current mailbox data. - */ -static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id) -{ - assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); - return base->MBOXIRQ[cpu_id].IRQ; -} - -/*! - * @brief Set data bits in the mailbox based on the CPU ID. - * - * @param base MAILBOX peripheral base address. - * @param cpu_id CPU id, kMAILBOX_CM0Plus is M0+ or kMAILBOX_CM4 is M4. - * @param mboxSetBits Data bits to set in the mailbox. - * - * @note Sets data bits to send via the MAILBOX to the other core. A value of 0 will - * do nothing. Only sets bits selected with a 1 in it's bit position. - */ -static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxSetBits) -{ - assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); - base->MBOXIRQ[cpu_id].IRQSET = mboxSetBits; -} - -/*! - * @brief Clear data bits in the mailbox based on the CPU ID. - * - * @param base MAILBOX peripheral base address. - * @param cpu_id CPU id, kMAILBOX_CM0Plus is M0+ or kMAILBOX_CM4 is M4. - * @param mboxClrBits Data bits to clear in the mailbox. - * - * @note Clear data bits to send via the MAILBOX to the other core. A value of 0 will - * do nothing. Only clears bits selected with a 1 in it's bit position. - */ -static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxClrBits) -{ - assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); - base->MBOXIRQ[cpu_id].IRQCLR = mboxClrBits; -} - -/*! - * @brief Get MUTEX state and lock mutex - * - * @param base MAILBOX peripheral base address. - * - * @return See note - * - * @note Returns '1' if the mutex was taken or '0' if another resources has the - * mutex locked. Once a mutex is taken, it can be returned with the MAILBOX_SetMutex() - * function. - */ -static inline uint32_t MAILBOX_GetMutex(MAILBOX_Type *base) -{ - return (base->MUTEX & MAILBOX_MUTEX_EX_MASK); -} - -/*! - * @brief Set MUTEX state - * - * @param base MAILBOX peripheral base address. - * - * @note Sets mutex state to '1' and allows other resources to get the mutex. - */ -static inline void MAILBOX_SetMutex(MAILBOX_Type *base) -{ - base->MUTEX = MAILBOX_MUTEX_EX_MASK; -} - -#if defined(__cplusplus) -} -#endif /*_cplusplus*/ -/*@}*/ - -#endif /* _FSL_MAILBOX_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_mrt.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_mrt.c deleted file mode 100644 index 1aa5f00cd0c..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_mrt.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_mrt.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.mrt" -#endif - - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base Multi-Rate timer peripheral base address - * - * @return The MRT instance - */ -static uint32_t MRT_GetInstance(MRT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to MRT bases for each instance. */ -static MRT_Type *const s_mrtBases[] = MRT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to MRT clocks for each instance. */ -static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if defined(FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET -/*! @brief Pointers to MRT resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_mrtResets[] = MRT_RSTS_N; -#else -/*! @brief Pointers to MRT resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_mrtResets[] = MRT_RSTS; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t MRT_GetInstance(MRT_Type *base) -{ - uint32_t instance; - uint32_t mrtArrayCount = (sizeof(s_mrtBases) / sizeof(s_mrtBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < mrtArrayCount; instance++) - { - if (s_mrtBases[instance] == base) - { - break; - } - } - - assert(instance < mrtArrayCount); - - return instance; -} - -void MRT_Init(MRT_Type *base, const mrt_config_t *config) -{ - assert(config); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate the MRT clock */ - CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the module */ - RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]); - -#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) - /* Set timer operating mode */ - base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask); -#endif -} - -void MRT_Deinit(MRT_Type *base) -{ - /* Stop all the timers */ - MRT_StopTimer(base, kMRT_Channel_0); - MRT_StopTimer(base, kMRT_Channel_1); -#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 2U) - MRT_StopTimer(base, kMRT_Channel_2); -#endif -#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 3U) - MRT_StopTimer(base, kMRT_Channel_3); -#endif - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the MRT clock*/ - CLOCK_DisableClock(s_mrtClocks[MRT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - - uint32_t newValue = count; - if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == kMRT_OneShotMode) || (immediateLoad)) - { - /* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */ - newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK; - } - - /* Update the timer interval value */ - base->CHANNEL[channel].INTVAL = newValue; -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_mrt.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_mrt.h deleted file mode 100644 index c435e97e1fa..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_mrt.h +++ /dev/null @@ -1,391 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_MRT_H_ -#define _FSL_MRT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup mrt - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! @brief List of MRT channels */ -typedef enum _mrt_chnl -{ - kMRT_Channel_0 = 0U, /*!< MRT channel number 0*/ - kMRT_Channel_1, /*!< MRT channel number 1 */ - kMRT_Channel_2, /*!< MRT channel number 2 */ - kMRT_Channel_3 /*!< MRT channel number 3 */ -} mrt_chnl_t; - -/*! @brief List of MRT timer modes */ -typedef enum _mrt_timer_mode -{ - kMRT_RepeatMode = (0 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< Repeat Interrupt mode */ - kMRT_OneShotMode = (1 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< One-shot Interrupt mode */ - kMRT_OneShotStallMode = (2 << MRT_CHANNEL_CTRL_MODE_SHIFT) /*!< One-shot stall mode */ -} mrt_timer_mode_t; - -/*! @brief List of MRT interrupts */ -typedef enum _mrt_interrupt_enable -{ - kMRT_TimerInterruptEnable = MRT_CHANNEL_CTRL_INTEN_MASK /*!< Timer interrupt enable*/ -} mrt_interrupt_enable_t; - -/*! @brief List of MRT status flags */ -typedef enum _mrt_status_flags -{ - kMRT_TimerInterruptFlag = MRT_CHANNEL_STAT_INTFLAG_MASK, /*!< Timer interrupt flag */ - kMRT_TimerRunFlag = MRT_CHANNEL_STAT_RUN_MASK, /*!< Indicates state of the timer */ -} mrt_status_flags_t; - -/*! - * @brief MRT configuration structure - * - * This structure holds the configuration settings for the MRT peripheral. To initialize this - * structure to reasonable defaults, call the MRT_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _mrt_config -{ - bool enableMultiTask; /*!< true: Timers run in multi-task mode; false: Timers run in hardware status mode */ -} mrt_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the MRT clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the MRT driver. - * - * @param base Multi-Rate timer peripheral base address - * @param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in - * MODCFG reigster, param config is useless. - */ -void MRT_Init(MRT_Type *base, const mrt_config_t *config); - -/*! - * @brief Gate the MRT clock - * - * @param base Multi-Rate timer peripheral base address - */ -void MRT_Deinit(MRT_Type *base); - -/*! - * @brief Fill in the MRT config struct with the default settings - * - * The default values are: - * @code - * config->enableMultiTask = false; - * @endcode - * @param config Pointer to user's MRT config structure. - */ -static inline void MRT_GetDefaultConfig(mrt_config_t *config) -{ - assert(config); -#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) - /* Use hardware status operating mode */ - config->enableMultiTask = false; -#endif -} - -/*! - * @brief Sets up an MRT channel mode. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Channel that is being configured. - * @param mode Timer mode to use for the channel. - */ -static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - - uint32_t reg = base->CHANNEL[channel].CTRL; - - /* Clear old value */ - reg &= ~MRT_CHANNEL_CTRL_MODE_MASK; - /* Add the new mode */ - reg |= mode; - - base->CHANNEL[channel].CTRL = reg; -} - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the MRT interrupt. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].CTRL |= mask; -} - -/*! - * @brief Disables the selected MRT interrupt. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to disable. This is a logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].CTRL &= ~mask; -} - -/*! - * @brief Gets the enabled MRT interrupts. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the MRT status flags - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::mrt_status_flags_t - */ -static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK)); -} - -/*! - * @brief Clears the MRT status flags. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::mrt_status_flags_t - */ -static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK); -} - -/*! @}*/ - -/*! - * @name Read and Write the timer period - * @{ - */ - -/*! - * @brief Used to update the timer period in units of count. - * - * The new value will be immediately loaded or will be loaded at the end of the current time - * interval. For one-shot interrupt mode the new value will be immediately loaded. - * - * @note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param count Timer period in units of ticks - * @param immediateLoad true: Load the new value immediately into the TIMER register; - * false: Load the new value at the end of current timer interval - */ -void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad); - -/*! - * @brief Reads the current timer counting value. - * - * This function returns the real-time timer counting value, in a range from 0 to a - * timer period. - * - * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return Current timer counting value in ticks - */ -static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - return base->CHANNEL[channel].TIMER; -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the timer counting. - * - * After calling this function, timers load period value, counts down to 0 and - * depending on the timer mode it will either load the respective start value again or stop. - * - * @note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - * @param count Timer period in units of ticks - */ -static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - /* Write the timer interval value */ - base->CHANNEL[channel].INTVAL = count; -} - -/*! - * @brief Stops the timer counting. - * - * This function stops the timer from counting. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - */ -static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - /* Stop the timer immediately */ - base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK; -} - -/*! @}*/ - -/*! - * @name Get & release channel - * @{ - */ - -/*! - * @brief Find the available channel. - * - * This function returns the lowest available channel number. - * - * @param base Multi-Rate timer peripheral base address - */ -static inline uint32_t MRT_GetIdleChannel(MRT_Type *base) -{ - return base->IDLE_CH; -} - -#if !(defined(FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) && FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) -/*! - * @brief Release the channel when the timer is using the multi-task mode. - * - * In multi-task mode, the INUSE flags allow more control over when MRT channels are released for - * further use. The user can hold on to a channel acquired by calling MRT_GetIdleChannel() for as - * long as it is needed and release it by calling this function. This removes the need to ask for - * an available channel for every use. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - */ -static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - - uint32_t reg = base->CHANNEL[channel].STAT; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg = ~MRT_CHANNEL_STAT_INTFLAG_MASK; - reg |= MRT_CHANNEL_STAT_INUSE_MASK; - - base->CHANNEL[channel].STAT = reg; -} -#endif - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_MRT_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_pint.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_pint.c deleted file mode 100644 index ad3a4aaaceb..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_pint.c +++ /dev/null @@ -1,541 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_pint.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.pint" -#endif - - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Irq number array */ -static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; - -/*! @brief Callback function array for PINT(s). */ -static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -void PINT_Init(PINT_Type *base) -{ - uint32_t i; - uint32_t pmcfg; - - assert(base); - - pmcfg = 0; - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_pintCallback[i] = NULL; - } - - /* Disable all bit slices */ - for (i = 0; i < PINT_PIN_INT_COUNT; i++) - { - pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U))); - } - -#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) - /* Enable the peripheral clock */ - CLOCK_EnableClock(kCLOCK_GpioInt); - - /* Reset the peripheral */ - RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); -#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) - /* Enable the peripheral clock */ - CLOCK_EnableClock(kCLOCK_Gpio0); - - /* Reset the peripheral */ - RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); -#else - /* Enable the peripheral clock */ - CLOCK_EnableClock(kCLOCK_Pint); - - /* Reset the peripheral */ - RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); -#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE && FSL_FEATURE_CLOCK_HAS_NO_GPIOINT_CLOCK_SOURCE*/ - - /* Disable all pattern match bit slices */ - base->PMCFG = pmcfg; -} - -void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback) -{ - assert(base); - - /* Clear Rise and Fall flags first */ - PINT_PinInterruptClrRiseFlag(base, intr); - PINT_PinInterruptClrFallFlag(base, intr); - - /* select level or edge sensitive */ - base->ISEL = (base->ISEL & ~(1U << intr)) | ((enable & PINT_PIN_INT_LEVEL) ? (1U << intr) : 0U); - - /* enable rising or level interrupt */ - if (enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE)) - { - base->SIENR = 1U << intr; - } - else - { - base->CIENR = 1U << intr; - } - - /* Enable falling or select high level */ - if (enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL) - { - base->SIENF = 1U << intr; - } - else - { - base->CIENF = 1U << intr; - } - - s_pintCallback[intr] = callback; -} - -void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback) -{ - uint32_t mask; - bool level; - - assert(base); - - *enable = kPINT_PinIntEnableNone; - level = false; - - mask = 1U << pintr; - if (base->ISEL & mask) - { - /* Pin interrupt is level sensitive */ - level = true; - } - - if (base->IENR & mask) - { - if (level) - { - /* Level interrupt is enabled */ - *enable = kPINT_PinIntEnableLowLevel; - } - else - { - /* Rising edge interrupt */ - *enable = kPINT_PinIntEnableRiseEdge; - } - } - - if (base->IENF & mask) - { - if (level) - { - /* Level interrupt is active high */ - *enable = kPINT_PinIntEnableHighLevel; - } - else - { - /* Either falling or both edge */ - if (*enable == kPINT_PinIntEnableRiseEdge) - { - /* Rising and faling edge */ - *enable = kPINT_PinIntEnableBothEdges; - } - else - { - /* Falling edge */ - *enable = kPINT_PinIntEnableFallEdge; - } - } - } - - *callback = s_pintCallback[pintr]; -} - -void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) -{ - uint32_t src_shift; - uint32_t cfg_shift; - uint32_t pmcfg; - - assert(base); - - src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U); - cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U); - - /* Input source selection for selected bit slice */ - base->PMSRC = (base->PMSRC & ~(PININT_BITSLICE_SRC_MASK << src_shift)) | (cfg->bs_src << src_shift); - - /* Bit slice configuration */ - pmcfg = base->PMCFG; - pmcfg = (pmcfg & ~(PININT_BITSLICE_CFG_MASK << cfg_shift)) | (cfg->bs_cfg << cfg_shift); - - /* If end point is true, enable the bits */ - if (bslice != 7U) - { - if (cfg->end_point) - { - pmcfg |= (0x1U << bslice); - } - else - { - pmcfg &= ~(0x1U << bslice); - } - } - - base->PMCFG = pmcfg; - - /* Save callback pointer */ - s_pintCallback[bslice] = cfg->callback; -} - -void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) -{ - uint32_t src_shift; - uint32_t cfg_shift; - - assert(base); - - src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U); - cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U); - - cfg->bs_src = (pint_pmatch_input_src_t)((base->PMSRC & (PININT_BITSLICE_SRC_MASK << src_shift)) >> src_shift); - cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)((base->PMCFG & (PININT_BITSLICE_CFG_MASK << cfg_shift)) >> cfg_shift); - - if (bslice == 7U) - { - cfg->end_point = true; - } - else - { - cfg->end_point = (base->PMCFG & (0x1U << bslice)) >> bslice; - } - cfg->callback = s_pintCallback[bslice]; -} - -uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base) -{ - uint32_t pmctrl; - uint32_t pmstatus; - uint32_t pmsrc; - - pmctrl = PINT->PMCTRL; - pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT; - if (pmstatus) - { - /* Reset Pattern match engine detection logic */ - pmsrc = base->PMSRC; - base->PMSRC = pmsrc; - } - return (pmstatus); -} - -void PINT_EnableCallback(PINT_Type *base) -{ - uint32_t i; - - assert(base); - - PINT_PinInterruptClrStatusAll(base); - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - NVIC_ClearPendingIRQ(s_pintIRQ[i]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - EnableIRQ(s_pintIRQ[i]); - } -} - -void PINT_DisableCallback(PINT_Type *base) -{ - uint32_t i; - - assert(base); - - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - DisableIRQ(s_pintIRQ[i]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i]); - } -} - -void PINT_Deinit(PINT_Type *base) -{ - uint32_t i; - - assert(base); - - /* Cleanup */ - PINT_DisableCallback(base); - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_pintCallback[i] = NULL; - } - -#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) - /* Reset the peripheral */ - RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); - - /* Disable the peripheral clock */ - CLOCK_DisableClock(kCLOCK_GpioInt); -#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) - /* Reset the peripheral */ - RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); - - /* Disable the peripheral clock */ - CLOCK_DisableClock(kCLOCK_Gpio0); -#else - /* Reset the peripheral */ - RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); - - /* Disable the peripheral clock */ - CLOCK_DisableClock(kCLOCK_Pint); -#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ -} - -/* IRQ handler functions overloading weak symbols in the startup */ -void PIN_INT0_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt0] != NULL) - { - s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus); - } - if((PINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) -void PIN_INT1_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt1] != NULL) - { - s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus); - } - if((PINT->ISEL & 0x2U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) -void PIN_INT2_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt2] != NULL) - { - s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus); - } - if((PINT->ISEL & 0x4U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) -void PIN_INT3_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt3] != NULL) - { - s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus); - } - if((PINT->ISEL & 0x8U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) -void PIN_INT4_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt4] != NULL) - { - s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus); - } - if((PINT->ISEL & 0x10U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT5_DAC1_IRQHandler(void) -#else -void PIN_INT5_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt5] != NULL) - { - s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus); - } - if((PINT->ISEL & 0x20U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT6_USART3_IRQHandler(void) -#else -void PIN_INT6_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt6] != NULL) - { - s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus); - } - if((PINT->ISEL & 0x40U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT7_USART4_IRQHandler(void) -#else -void PIN_INT7_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt7] != NULL) - { - s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus); - } - if((PINT->ISEL & 0x80U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_pint.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_pint.h deleted file mode 100644 index 9733f836b71..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_pint.h +++ /dev/null @@ -1,572 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_PINT_H_ -#define _FSL_PINT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup pint_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */ -/*@}*/ - -/* Number of interrupt line supported by PINT */ -#define PINT_PIN_INT_COUNT 8U - -/* Number of input sources supported by PINT */ -#define PINT_INPUT_COUNT 8U - -/* PININT Bit slice source register bits */ -#define PININT_BITSLICE_SRC_START 8U -#define PININT_BITSLICE_SRC_MASK 7U - -/* PININT Bit slice configuration register bits */ -#define PININT_BITSLICE_CFG_START 8U -#define PININT_BITSLICE_CFG_MASK 7U -#define PININT_BITSLICE_ENDP_MASK 7U - -#define PINT_PIN_INT_LEVEL 0x10U -#define PINT_PIN_INT_EDGE 0x00U -#define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U -#define PINT_PIN_INT_RISE 0x01U -#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE) -#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) -#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) -#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL) -#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) - -/*! @brief PINT Pin Interrupt enable type */ -typedef enum _pint_pin_enable -{ - kPINT_PinIntEnableNone = 0U, /*!< Do not generate Pin Interrupt */ - kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE, /*!< Generate Pin Interrupt on rising edge */ - kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE, /*!< Generate Pin Interrupt on falling edge */ - kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */ - kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL, /*!< Generate Pin Interrupt on low level */ - kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */ -} pint_pin_enable_t; - -/*! @brief PINT Pin Interrupt type */ -typedef enum _pint_int -{ - kPINT_PinInt0 = 0U, /*!< Pin Interrupt 0 */ -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_PinInt1 = 1U, /*!< Pin Interrupt 1 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) - kPINT_PinInt2 = 2U, /*!< Pin Interrupt 2 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) - kPINT_PinInt3 = 3U, /*!< Pin Interrupt 3 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) - kPINT_PinInt4 = 4U, /*!< Pin Interrupt 4 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) - kPINT_PinInt5 = 5U, /*!< Pin Interrupt 5 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) - kPINT_PinInt6 = 6U, /*!< Pin Interrupt 6 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) - kPINT_PinInt7 = 7U, /*!< Pin Interrupt 7 */ -#endif -} pint_pin_int_t; - -/*! @brief PINT Pattern Match bit slice input source type */ -typedef enum _pint_pmatch_input_src -{ - kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */ - kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */ - kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */ - kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */ - kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */ - kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */ - kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */ - kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */ -} pint_pmatch_input_src_t; - -/*! @brief PINT Pattern Match bit slice type */ -typedef enum _pint_pmatch_bslice -{ - kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) - kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) - kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) - kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) - kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) - kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) - kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */ -#endif -} pint_pmatch_bslice_t; - -/*! @brief PINT Pattern Match configuration type */ -typedef enum _pint_pmatch_bslice_cfg -{ - kPINT_PatternMatchAlways = 0U, /*!< Always Contributes to product term match */ - kPINT_PatternMatchStickyRise = 1U, /*!< Sticky Rising edge */ - kPINT_PatternMatchStickyFall = 2U, /*!< Sticky Falling edge */ - kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */ - kPINT_PatternMatchHigh = 4U, /*!< High level */ - kPINT_PatternMatchLow = 5U, /*!< Low level */ - kPINT_PatternMatchNever = 6U, /*!< Never contributes to product term match */ - kPINT_PatternMatchBothEdges = 7U, /*!< Either rising or falling edge */ -} pint_pmatch_bslice_cfg_t; - -/*! @brief PINT Callback function. */ -typedef void (*pint_cb_t)(pint_pin_int_t pintr, uint32_t pmatch_status); - -typedef struct _pint_pmatch_cfg -{ - pint_pmatch_input_src_t bs_src; - pint_pmatch_bslice_cfg_t bs_cfg; - bool end_point; - pint_cb_t callback; -} pint_pmatch_cfg_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize PINT peripheral. - - * This function initializes the PINT peripheral and enables the clock. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_Init(PINT_Type *base); - -/*! - * @brief Configure PINT peripheral pin interrupt. - - * This function configures a given pin interrupt. - * - * @param base Base address of the PINT peripheral. - * @param intr Pin interrupt. - * @param enable Selects detection logic. - * @param callback Callback. - * - * @retval None. - */ -void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback); - -/*! - * @brief Get PINT peripheral pin interrupt configuration. - - * This function returns the configuration of a given pin interrupt. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * @param enable Pointer to store the detection logic. - * @param callback Callback. - * - * @retval None. - */ -void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback); - -/*! - * @brief Clear Selected pin interrupt status. - - * This function clears the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr) -{ - base->IST = (1U << pintr); -} - -/*! - * @brief Get Selected pin interrupt status. - - * This function returns the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval status = 0 No pin interrupt request. = 1 Selected Pin interrupt request active. - */ -static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->IST & (1U << pintr)) ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupts status. - - * This function clears the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrStatusAll(PINT_Type *base) -{ - base->IST = PINT_IST_PSTAT_MASK; -} - -/*! - * @brief Get all pin interrupts status. - - * This function returns the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval status Each bit position indicates the status of corresponding pin interrupt. - * = 0 No pin interrupt request. = 1 Pin interrupt request active. - */ -static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base) -{ - return (base->IST); -} - -/*! - * @brief Clear Selected pin interrupt fall flag. - - * This function clears the selected pin interrupt fall flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - base->FALL = (1U << pintr); -} - -/*! - * @brief Get selected pin interrupt fall flag. - - * This function returns the selected pin interrupt fall flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval flag = 0 Falling edge has not been detected. = 1 Falling edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->FALL & (1U << pintr)) ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupt fall flags. - - * This function clears the fall flag for all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base) -{ - base->FALL = PINT_FALL_FDET_MASK; -} - -/*! - * @brief Get all pin interrupt fall flags. - - * This function returns the fall flag of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval flags Each bit position indicates the falling edge detection of the corresponding pin interrupt. - * 0 Falling edge has not been detected. = 1 Falling edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base) -{ - return (base->FALL); -} - -/*! - * @brief Clear Selected pin interrupt rise flag. - - * This function clears the selected pin interrupt rise flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - base->RISE = (1U << pintr); -} - -/*! - * @brief Get selected pin interrupt rise flag. - - * This function returns the selected pin interrupt rise flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval flag = 0 Rising edge has not been detected. = 1 Rising edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->RISE & (1U << pintr)) ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupt rise flags. - - * This function clears the rise flag for all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base) -{ - base->RISE = PINT_RISE_RDET_MASK; -} - -/*! - * @brief Get all pin interrupt rise flags. - - * This function returns the rise flag of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval flags Each bit position indicates the rising edge detection of the corresponding pin interrupt. - * 0 Rising edge has not been detected. = 1 Rising edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base) -{ - return (base->RISE); -} - -/*! - * @brief Configure PINT pattern match. - - * This function configures a given pattern match bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * @param cfg Pointer to bit slice configuration. - * - * @retval None. - */ -void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); - -/*! - * @brief Get PINT pattern match configuration. - - * This function returns the configuration of a given pattern match bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * @param cfg Pointer to bit slice configuration. - * - * @retval None. - */ -void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); - -/*! - * @brief Get pattern match bit slice status. - - * This function returns the status of selected bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * - * @retval status = 0 Match has not been detected. = 1 Match has been detected. - */ -static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_bslice_t bslice) -{ - return ((base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT) & (0x1U << bslice)) >> bslice; -} - -/*! - * @brief Get status of all pattern match bit slices. - - * This function returns the status of all bit slices. - * - * @param base Base address of the PINT peripheral. - * - * @retval status Each bit position indicates the match status of corresponding bit slice. - * = 0 Match has not been detected. = 1 Match has been detected. - */ -static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base) -{ - return base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT; -} - -/*! - * @brief Reset pattern match detection logic. - - * This function resets the pattern match detection logic if any of the product term is matching. - * - * @param base Base address of the PINT peripheral. - * - * @retval pmstatus Each bit position indicates the match status of corresponding bit slice. - * = 0 Match was detected. = 1 Match was not detected. - */ -uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base); - -/*! - * @brief Enable pattern match function. - - * This function enables the pattern match function. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchEnable(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) | PINT_PMCTRL_SEL_PMATCH_MASK; -} - -/*! - * @brief Disable pattern match function. - - * This function disables the pattern match function. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchDisable(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) & ~PINT_PMCTRL_SEL_PMATCH_MASK; -} - -/*! - * @brief Enable RXEV output. - - * This function enables the pattern match RXEV output. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) | PINT_PMCTRL_ENA_RXEV_MASK; -} - -/*! - * @brief Disable RXEV output. - - * This function disables the pattern match RXEV output. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) & ~PINT_PMCTRL_ENA_RXEV_MASK; -} - -/*! - * @brief Enable callback. - - * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_EnableCallback(PINT_Type *base); - -/*! - * @brief Disable callback. - - * This function disables the interrupt for the selected PINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * @param base Base address of the peripheral. - * - * @retval None. - */ -void PINT_DisableCallback(PINT_Type *base); - -/*! - * @brief Deinitialize PINT peripheral. - - * This function disables the PINT clock. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_Deinit(PINT_Type *base); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_PINT_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_power.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_power.c deleted file mode 100644 index 128de353cdf..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_power.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016, NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_common.h" -#include "fsl_power.h" -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.power" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Empty file since implementation is in header file and power library */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_power.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_power.h deleted file mode 100644 index 64ea4053713..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_power.h +++ /dev/null @@ -1,256 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016, NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_POWER_H_ -#define _FSL_POWER_H_ - -#include "fsl_common.h" - -/*! @addtogroup power */ -/*! @{ */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief power driver version 2.0.0. */ -#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -#define MAKE_PD_BITS(reg, slot) (((reg) << 8) | (slot)) -#define PDRCFG0 0x0U -#define PDRCFG1 0x1U - -typedef enum pd_bits -{ - kPDRUNCFG_PD_FRO_EN = MAKE_PD_BITS(PDRCFG0, 4U), - kPDRUNCFG_PD_FLASH = MAKE_PD_BITS(PDRCFG0, 5U), - kPDRUNCFG_PD_TEMPS = MAKE_PD_BITS(PDRCFG0, 6U), - kPDRUNCFG_PD_BOD_RESET = MAKE_PD_BITS(PDRCFG0, 7U), - kPDRUNCFG_PD_BOD_INTR = MAKE_PD_BITS(PDRCFG0, 8U), - kPDRUNCFG_PD_ADC0 = MAKE_PD_BITS(PDRCFG0, 10U), - kPDRUNCFG_PD_VDDFLASH = MAKE_PD_BITS(PDRCFG0, 11U), - kPDRUNCFG_LP_VDDFLASH = MAKE_PD_BITS(PDRCFG0, 12U), - kPDRUNCFG_PD_RAM0 = MAKE_PD_BITS(PDRCFG0, 13U), - kPDRUNCFG_PD_RAM1 = MAKE_PD_BITS(PDRCFG0, 14U), - kPDRUNCFG_PD_RAM2 = MAKE_PD_BITS(PDRCFG0, 15U), - kPDRUNCFG_PD_RAMX = MAKE_PD_BITS(PDRCFG0, 16U), - kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG0, 17U), - kPDRUNCFG_PD_VDDHV_ENA = MAKE_PD_BITS(PDRCFG0, 18U), - kPDRUNCFG_PD_VD7_ENA = MAKE_PD_BITS(PDRCFG0, 19U), - kPDRUNCFG_PD_WDT_OSC = MAKE_PD_BITS(PDRCFG0, 20U), - kPDRUNCFG_PD_USB0_PHY = MAKE_PD_BITS(PDRCFG0, 21U), - kPDRUNCFG_PD_SYS_PLL0 = MAKE_PD_BITS(PDRCFG0, 22U), - kPDRUNCFG_PD_VREFP_SW = MAKE_PD_BITS(PDRCFG0, 23U), - kPDRUNCFG_PD_FLASH_BG = MAKE_PD_BITS(PDRCFG0, 25U), - - kPDRUNCFG_PD_ALT_FLASH_IBG = MAKE_PD_BITS(PDRCFG1, 28U), - kPDRUNCFG_SEL_ALT_FLASH_IBG = MAKE_PD_BITS(PDRCFG1, 29U), - - /* - This enum member has no practical meaning,it is used to avoid MISRA issue, - user should not trying to use it. - */ - kPDRUNCFG_ForceUnsigned = 0x80000000U -} pd_bit_t; - -/* Power mode configuration API parameter */ -typedef enum _power_mode_config -{ - kPmu_Sleep = 0U, - kPmu_Deep_Sleep = 1U, - kPmu_Deep_PowerDown = 2U, -} power_mode_cfg_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! -* @name Power Configuration -* @{ -*/ - -/*! - * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral - * - * @param en peripheral for which to enable the PDRUNCFG bit - * @return none - */ -static inline void POWER_EnablePD(pd_bit_t en) -{ - /* PDRUNCFGSET */ - SYSCON->PDRUNCFGSET[(en >> 8UL)] = (1UL << (en & 0xffU)); -} - -/*! - * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral - * - * @param en peripheral for which to disable the PDRUNCFG bit - * @return none - */ -static inline void POWER_DisablePD(pd_bit_t en) -{ - /* PDRUNCFGCLR */ - SYSCON->PDRUNCFGCLR[(en >> 8UL)] = (1UL << (en & 0xffU)); -} - -/*! - * @brief API to enable deep sleep bit in the ARM Core. - * - * @return none - */ -static inline void POWER_EnableDeepSleep(void) -{ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; -} - -/*! - * @brief API to disable deep sleep bit in the ARM Core. - * - * @return none - */ -static inline void POWER_DisableDeepSleep(void) -{ - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; -} - -/*! - * @brief API to power down flash controller. - * - * @return none - */ -static inline void POWER_PowerDownFlash(void) -{ - /* note, we retain flash trim to make waking back up faster */ - SYSCON->PDRUNCFGSET[0] = - SYSCON_PDRUNCFG_LP_VDDFLASH_MASK | SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK | SYSCON_PDRUNCFG_PD_FLASH_BG_MASK; - - /* TURN OFF clock for Flash Controller (only needed for FLASH programming, will be turned on by ROM API) */ - CLOCK_DisableClock(kCLOCK_Flash); - - /* TURN OFF clock for Flash Accelerator */ - CLOCK_DisableClock(kCLOCK_Fmc); -} - -/*! - * @brief API to power up flash controller. - * - * @return none - */ -static inline void POWER_PowerUpFlash(void) -{ - SYSCON->PDRUNCFGCLR[0] = SYSCON_PDRUNCFG_LP_VDDFLASH_MASK | SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK; - - /* TURN ON clock for flash Accelerator */ - CLOCK_EnableClock(kCLOCK_Fmc); - - /* TURN ON clock for flash Controller */ - CLOCK_EnableClock(kCLOCK_Flash); -} - -/*! - * @brief Power Library API to enter different power mode. - * - * @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep sleep - * @return none - */ -void POWER_EnterPowerMode(power_mode_cfg_t mode, uint64_t exclude_from_pd); - -/*! - * @brief Power Library API to enter sleep mode. - * - * @return none - */ -void POWER_EnterSleep(void); - -/*! - * @brief Power Library API to enter deep sleep mode. - * - * @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep sleep - * @return none - */ -void POWER_EnterDeepSleep(uint64_t exclude_from_pd); - -/*! - * @brief Power Library API to enter deep power down mode. - * - * @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep power down mode, - * but this is has no effect as the voltages are cut off. - * @return none - */ -void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd); - -/*! - * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency. - * - * @param freq - The desired frequency at which the part would like to operate, - * note that the voltage and flash wait states should be set before changing frequency - * @return none - */ -void POWER_SetVoltageForFreq(uint32_t freq); - -/*! - * @brief Power Library API to choose low power regulation and set the voltage for the desired operating frequency. - * - * @param freq - The desired frequency at which the part would like to operate, - * note only 12MHz and 48Mhz are supported - * @return none - */ -void POWER_SetLowPowerVoltageForFreq(uint32_t freq); - -/*! - * @brief Power Library API to return the library version. - * - * @return version number of the power library - */ -uint32_t POWER_GetLibVersion(void); - -/* @} */ - -#ifdef __cplusplus -} -#endif - -/*! @} */ - -#endif /* _FSL_POWER_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_reset.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_reset.c deleted file mode 100644 index da1822e5e03..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_reset.c +++ /dev/null @@ -1,178 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016, NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_common.h" -#include "fsl_reset.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.reset" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) - -void RESET_SetPeripheralReset(reset_ip_name_t peripheral) -{ - const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; - const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); - const uint32_t bitMask = 1u << bitPos; - - assert(bitPos < 32u); - - /* ASYNC_SYSCON registers have offset 1024 */ - if (regIndex >= SYSCON_PRESETCTRL_COUNT) - { - /* reset register is in ASYNC_SYSCON */ - - /* set bit */ - ASYNC_SYSCON->ASYNCPRESETCTRLSET = bitMask; - /* wait until it reads 0b1 */ - while (0u == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask)) - { - } - } - else - { - /* reset register is in SYSCON */ - - /* set bit */ - SYSCON->PRESETCTRLSET[regIndex] = bitMask; - /* wait until it reads 0b1 */ - while (0u == (SYSCON->PRESETCTRL[regIndex] & bitMask)) - { - } - } -} - -void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) -{ - const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; - const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); - const uint32_t bitMask = 1u << bitPos; - - assert(bitPos < 32u); - - /* ASYNC_SYSCON registers have offset 1024 */ - if (regIndex >= SYSCON_PRESETCTRL_COUNT) - { - /* reset register is in ASYNC_SYSCON */ - - /* clear bit */ - ASYNC_SYSCON->ASYNCPRESETCTRLCLR = bitMask; - /* wait until it reads 0b0 */ - while (bitMask == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask)) - { - } - } - else - { - /* reset register is in SYSCON */ - - /* clear bit */ - SYSCON->PRESETCTRLCLR[regIndex] = bitMask; - /* wait until it reads 0b0 */ - while (bitMask == (SYSCON->PRESETCTRL[regIndex] & bitMask)) - { - } - } -} - -void RESET_PeripheralReset(reset_ip_name_t peripheral) -{ - RESET_SetPeripheralReset(peripheral); - RESET_ClearPeripheralReset(peripheral); -} - -void RESET_SetSlaveCoreReset(void) -{ - uint32_t cpuctrl = (SYSCON->CPUCTRL & ~0x7F80U) | 0xC0C48000U; - - /* CM4 is the master. */ - if (cpuctrl & SYSCON_CPUCTRL_MASTERCPU_MASK) - { - SYSCON->CPUCTRL = cpuctrl | SYSCON_CPUCTRL_CM0RSTEN_MASK; - } - /* CM0 is the master. */ - else - { - SYSCON->CPUCTRL = cpuctrl | SYSCON_CPUCTRL_CM4RSTEN_MASK; - } -} - -void RESET_ClearSlaveCoreReset(void) -{ - uint32_t cpuctrl = (SYSCON->CPUCTRL & ~0x7F80U) | 0xC0C48000U; - - /* CM4 is the master. */ - if (cpuctrl & SYSCON_CPUCTRL_MASTERCPU_MASK) - { - SYSCON->CPUCTRL = cpuctrl & ~SYSCON_CPUCTRL_CM0RSTEN_MASK; - } - /* CM0 is the master. */ - else - { - SYSCON->CPUCTRL = cpuctrl & ~SYSCON_CPUCTRL_CM4RSTEN_MASK; - } -} - -void RESET_SlaveCoreReset(uint32_t bootAddr, uint32_t bootStackPointer) -{ - volatile uint32_t i = 10U; - - SYSCON->CPSTACK = bootStackPointer; - SYSCON->CPBOOT = bootAddr; - - RESET_SetSlaveCoreReset(); - while(i--){} - RESET_ClearSlaveCoreReset(); -} - -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_reset.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_reset.h deleted file mode 100644 index 19142d12005..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_reset.h +++ /dev/null @@ -1,231 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016, NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_RESET_H_ -#define _FSL_RESET_H_ - -#include -#include -#include -#include -#include "fsl_device_registers.h" - -/*! - * @addtogroup ksdk_common - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief reset driver version 2.0.0. */ -#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! - * @brief Enumeration for peripheral reset control bits - * - * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers - */ -typedef enum _SYSCON_RSTn -{ - kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ - kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ - kMUX_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux reset control */ - kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ - kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ - kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ - kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ - kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ - kDMA_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ - kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ - kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ - kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ - kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ - kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ - kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ - kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ - kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ - kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ - kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ - kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ - kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ - kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ - kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ - kDMIC_RST_SHIFT_RSTn = 65536 | 19U, /**< Digital microphone interface reset control */ - kCT32B2_RST_SHIFT_RSTn = 65536 | 22U, /**< CT32B2 reset control */ - kUSB_RST_SHIFT_RSTn = 65536 | 25U, /**< USB reset control */ - kCT32B0_RST_SHIFT_RSTn = 65536 | 26U, /**< CT32B0 reset control */ - kCT32B1_RST_SHIFT_RSTn = 65536 | 27U, /**< CT32B1 reset control */ - kCT32B3_RST_SHIFT_RSTn = 67108864 | 13U, /**< CT32B3 reset control */ - kCT32B4_RST_SHIFT_RSTn = 67108864 | 14U, /**< CT32B4 reset control */ -} SYSCON_RSTn_t; - -/** Array initializers with peripheral reset bits **/ -#define ADC_RSTS \ - { \ - kADC0_RST_SHIFT_RSTn \ - } /* Reset bits for ADC peripheral */ -#define CRC_RSTS \ - { \ - kCRC_RST_SHIFT_RSTn \ - } /* Reset bits for CRC peripheral */ -#define DMA_RSTS \ - { \ - kDMA_RST_SHIFT_RSTn \ - } /* Reset bits for DMA peripheral */ -#define DMIC_RSTS \ - { \ - kDMIC_RST_SHIFT_RSTn \ - } /* Reset bits for ADC peripheral */ -#define FLEXCOMM_RSTS \ - { \ - kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ - kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn \ - } /* Reset bits for FLEXCOMM peripheral */ -#define GINT_RSTS \ - { \ - kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ - } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ -#define GPIO_RSTS \ - { \ - kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn \ - } /* Reset bits for GPIO peripheral */ -#define INPUTMUX_RSTS \ - { \ - kMUX_RST_SHIFT_RSTn \ - } /* Reset bits for INPUTMUX peripheral */ -#define IOCON_RSTS \ - { \ - kIOCON_RST_SHIFT_RSTn \ - } /* Reset bits for IOCON peripheral */ -#define FLASH_RSTS \ - { \ - kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ - } /* Reset bits for Flash peripheral */ -#define MRT_RSTS \ - { \ - kMRT_RST_SHIFT_RSTn \ - } /* Reset bits for MRT peripheral */ -#define PINT_RSTS \ - { \ - kPINT_RST_SHIFT_RSTn \ - } /* Reset bits for PINT peripheral */ -#define SCT_RSTS \ - { \ - kSCT0_RST_SHIFT_RSTn \ - } /* Reset bits for SCT peripheral */ -#define CTIMER_RSTS \ - { \ - kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \ - kCT32B4_RST_SHIFT_RSTn \ - } /* Reset bits for TIMER peripheral */ -#define USB_RSTS \ - { \ - kUSB_RST_SHIFT_RSTn \ - } /* Reset bits for USB peripheral */ -#define UTICK_RSTS \ - { \ - kUTICK_RST_SHIFT_RSTn \ - } /* Reset bits for UTICK peripheral */ -#define WWDT_RSTS \ - { \ - kWWDT_RST_SHIFT_RSTn \ - } /* Reset bits for WWDT peripheral */ - -typedef SYSCON_RSTn_t reset_ip_name_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Assert reset to peripheral. - * - * Asserts reset signal to specified peripheral module. - * - * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_SetPeripheralReset(reset_ip_name_t peripheral); - -/*! - * @brief Clear reset to peripheral. - * - * Clears reset signal to specified peripheral module, allows it to operate. - * - * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); - -/*! - * @brief Reset peripheral module. - * - * Reset peripheral module. - * - * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_PeripheralReset(reset_ip_name_t peripheral); - -/*! - * @brief Set slave core to reset state and hold. - */ -void RESET_SetSlaveCoreReset(void); - -/*! - * @brief Release slave core from reset state. - */ -void RESET_ClearSlaveCoreReset(void); - -/*! - * @brief Reset slave core with the boot entry. - */ -void RESET_SlaveCoreReset(uint32_t bootAddr, uint32_t bootStackPointer); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_RESET_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_rtc.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_rtc.c deleted file mode 100644 index 38b7aa595cb..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_rtc.c +++ /dev/null @@ -1,300 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_rtc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_rtc" -#endif - -#define SECONDS_IN_A_DAY (86400U) -#define SECONDS_IN_A_HOUR (3600U) -#define SECONDS_IN_A_MINUTE (60U) -#define DAYS_IN_A_YEAR (365U) -#define YEAR_RANGE_START (1970U) -#define YEAR_RANGE_END (2099U) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Checks whether the date and time passed in is valid - * - * @param datetime Pointer to structure where the date and time details are stored - * - * @return Returns false if the date & time details are out of range; true if in range - */ -static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime); - -/*! - * @brief Converts time data from datetime to seconds - * - * @param datetime Pointer to datetime structure where the date and time details are stored - * - * @return The result of the conversion in seconds - */ -static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime); - -/*! - * @brief Converts time data from seconds to a datetime structure - * - * @param seconds Seconds value that needs to be converted to datetime format - * @param datetime Pointer to the datetime structure where the result of the conversion is stored - */ -static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime); - -/******************************************************************************* - * Code - ******************************************************************************/ -static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Check year, month, hour, minute, seconds */ - if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || - (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) - { - /* If not correct then error*/ - return false; - } - - /* Adjust the days in February for a leap year */ - if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0)) - { - daysPerMonth[2] = 29U; - } - - /* Check the validity of the day */ - if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) - { - return false; - } - - return true; -} - -static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Number of days from begin of the non Leap-year*/ - /* Number of days from begin of the non Leap-year*/ - uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; - uint32_t seconds; - - /* Compute number of days from 1970 till given year*/ - seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; - /* Add leap year days */ - seconds += ((datetime->year / 4) - (1970U / 4)); - /* Add number of days till given month*/ - seconds += monthDays[datetime->month]; - /* Add days in given month. We subtract the current day as it is - * represented in the hours, minutes and seconds field*/ - seconds += (datetime->day - 1); - /* For leap year if month less than or equal to Febraury, decrement day counter*/ - if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) - { - seconds--; - } - - seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + - (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; - - return seconds; -} - -static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t x; - uint32_t secondsRemaining, days; - uint16_t daysInYear; - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Start with the seconds value that is passed in to be converted to date time format */ - secondsRemaining = seconds; - - /* Calcuate the number of days, we add 1 for the current day which is represented in the - * hours and seconds field - */ - days = secondsRemaining / SECONDS_IN_A_DAY + 1; - - /* Update seconds left*/ - secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; - - /* Calculate the datetime hour, minute and second fields */ - datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; - secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; - datetime->minute = secondsRemaining / 60U; - datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; - - /* Calculate year */ - daysInYear = DAYS_IN_A_YEAR; - datetime->year = YEAR_RANGE_START; - while (days > daysInYear) - { - /* Decrease day count by a year and increment year by 1 */ - days -= daysInYear; - datetime->year++; - - /* Adjust the number of days for a leap year */ - if (datetime->year & 3U) - { - daysInYear = DAYS_IN_A_YEAR; - } - else - { - daysInYear = DAYS_IN_A_YEAR + 1; - } - } - - /* Adjust the days in February for a leap year */ - if (!(datetime->year & 3U)) - { - daysPerMonth[2] = 29U; - } - - for (x = 1U; x <= 12U; x++) - { - if (days <= daysPerMonth[x]) - { - datetime->month = x; - break; - } - else - { - days -= daysPerMonth[x]; - } - } - - datetime->day = days; -} - -void RTC_Init(RTC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the RTC peripheral clock */ - CLOCK_EnableClock(kCLOCK_Rtc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Make sure the reset bit is cleared */ - base->CTRL &= ~RTC_CTRL_SWRESET_MASK; - -#if !(defined(FSL_FEATURE_RTC_HAS_NO_OSC_PD) && FSL_FEATURE_RTC_HAS_NO_OSC_PD) - /* Make sure the RTC OSC is powered up */ - base->CTRL &= ~RTC_CTRL_RTC_OSC_PD_MASK; -#endif -} - -status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Return error if the time provided is not valid */ - if (!(RTC_CheckDatetimeFormat(datetime))) - { - return kStatus_InvalidArgument; - } - - /* Set time in seconds */ - base->COUNT = RTC_ConvertDatetimeToSeconds(datetime); - - return kStatus_Success; -} - -void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t seconds = 0; - - seconds = base->COUNT; - RTC_ConvertSecondsToDatetime(seconds, datetime); -} - -status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) -{ - assert(alarmTime); - - uint32_t alarmSeconds = 0; - uint32_t currSeconds = 0; - - /* Return error if the alarm time provided is not valid */ - if (!(RTC_CheckDatetimeFormat(alarmTime))) - { - return kStatus_InvalidArgument; - } - - alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime); - - /* Get the current time */ - currSeconds = base->COUNT; - - /* Return error if the alarm time has passed */ - if (alarmSeconds < currSeconds) - { - return kStatus_Fail; - } - - /* Set alarm in seconds*/ - base->MATCH = alarmSeconds; - - return kStatus_Success; -} - -void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t alarmSeconds = 0; - - /* Get alarm in seconds */ - alarmSeconds = base->MATCH; - - RTC_ConvertSecondsToDatetime(alarmSeconds, datetime); -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_rtc.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_rtc.h deleted file mode 100644 index 7e885db6d83..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_rtc.h +++ /dev/null @@ -1,344 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_RTC_H_ -#define _FSL_RTC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup rtc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! @brief List of RTC interrupts */ -typedef enum _rtc_interrupt_enable -{ - kRTC_AlarmInterruptEnable = RTC_CTRL_ALARMDPD_EN_MASK, /*!< Alarm interrupt.*/ - kRTC_WakeupInterruptEnable = RTC_CTRL_WAKEDPD_EN_MASK /*!< Wake-up interrupt.*/ -} rtc_interrupt_enable_t; - -/*! @brief List of RTC flags */ -typedef enum _rtc_status_flags -{ - kRTC_AlarmFlag = RTC_CTRL_ALARM1HZ_MASK, /*!< Alarm flag*/ - kRTC_WakeupFlag = RTC_CTRL_WAKE1KHZ_MASK /*!< 1kHz wake-up timer flag*/ -} rtc_status_flags_t; - -/*! @brief Structure is used to hold the date and time */ -typedef struct _rtc_datetime -{ - uint16_t year; /*!< Range from 1970 to 2099.*/ - uint8_t month; /*!< Range from 1 to 12.*/ - uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ - uint8_t hour; /*!< Range from 0 to 23.*/ - uint8_t minute; /*!< Range from 0 to 59.*/ - uint8_t second; /*!< Range from 0 to 59.*/ -} rtc_datetime_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the RTC clock and enables the RTC oscillator. - * - * @note This API should be called at the beginning of the application using the RTC driver. - * - * @param base RTC peripheral base address - */ -void RTC_Init(RTC_Type *base); - -/*! - * @brief Stop the timer and gate the RTC clock - * - * @param base RTC peripheral base address - */ -static inline void RTC_Deinit(RTC_Type *base) -{ - /* Stop the RTC timer */ - base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the module clock */ - CLOCK_DisableClock(kCLOCK_Rtc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! @}*/ - -/*! - * @name Current Time & Alarm - * @{ - */ - -/*! - * @brief Sets the RTC date and time according to the given time structure. - * - * The RTC counter must be stopped prior to calling this function as writes to the RTC - * seconds register will fail if the RTC counter is running. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the date and time details to set are stored - * - * @return kStatus_Success: Success in setting the time and starting the RTC - * kStatus_InvalidArgument: Error because the datetime format is incorrect - */ -status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime); - -/*! - * @brief Gets the RTC time and stores it in the given time structure. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the date and time details are stored. - */ -void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime); - -/*! - * @brief Sets the RTC alarm time - * - * The function checks whether the specified alarm time is greater than the present - * time. If not, the function does not set the alarm and returns an error. - * - * @param base RTC peripheral base address - * @param alarmTime Pointer to structure where the alarm time is stored. - * - * @return kStatus_Success: success in setting the RTC alarm - * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect - * kStatus_Fail: Error because the alarm time has already passed - */ -status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime); - -/*! - * @brief Returns the RTC alarm time. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the alarm date and time details are stored. - */ -void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime); - -/*! @}*/ - -/*! - * @brief Enable the RTC high resolution timer and set the wake-up time. - * - * @param base RTC peripheral base address - * @param wakeupValue The value to be loaded into the RTC WAKE register - */ -static inline void RTC_SetWakeupCount(RTC_Type *base, uint16_t wakeupValue) -{ - /* Enable the 1kHz RTC timer */ - base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK; - - /* Set the start count value into the wake-up timer */ - base->WAKE = wakeupValue; -} - -/*! - * @brief Read actual RTC counter value. - * - * @param base RTC peripheral base address - */ -static inline uint16_t RTC_GetWakeupCount(RTC_Type *base) -{ - /* Read wake-up counter */ - return RTC_WAKE_VAL(base->WAKE); -} - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected RTC interrupts. - * - * @param base RTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) -{ - uint32_t reg = base->CTRL; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK); - reg |= mask; - - base->CTRL = reg; -} - -/*! - * @brief Disables the selected RTC interrupts. - * - * @param base RTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) -{ - uint32_t reg = base->CTRL; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK | mask); - - base->CTRL = reg; -} - -/*! - * @brief Gets the enabled RTC interrupts. - * - * @param base RTC peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) -{ - return (base->CTRL & (RTC_CTRL_ALARMDPD_EN_MASK | RTC_CTRL_WAKEDPD_EN_MASK)); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the RTC status flags - * - * @param base RTC peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::rtc_status_flags_t - */ -static inline uint32_t RTC_GetStatusFlags(RTC_Type *base) -{ - return (base->CTRL & (RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK)); -} - -/*! - * @brief Clears the RTC status flags. - * - * @param base RTC peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::rtc_status_flags_t - */ -static inline void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) -{ - uint32_t reg = base->CTRL; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK); - - /* Write 1 to the flags we wish to clear */ - reg |= mask; - - base->CTRL = reg; -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the RTC time counter. - * - * After calling this function, the timer counter increments once a second provided SR[TOF] or - * SR[TIF] are not set. - * - * @param base RTC peripheral base address - */ -static inline void RTC_StartTimer(RTC_Type *base) -{ - base->CTRL |= RTC_CTRL_RTC_EN_MASK; -} - -/*! - * @brief Stops the RTC time counter. - * - * RTC's seconds register can be written to only when the timer is stopped. - * - * @param base RTC peripheral base address - */ -static inline void RTC_StopTimer(RTC_Type *base) -{ - base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; -} - -/*! @}*/ - -/*! - * @brief Performs a software reset on the RTC module. - * - * This resets all RTC registers to their reset value. The bit is cleared by software explicitly clearing it. - * - * @param base RTC peripheral base address - */ -static inline void RTC_Reset(RTC_Type *base) -{ - base->CTRL |= RTC_CTRL_SWRESET_MASK; - base->CTRL &= ~RTC_CTRL_SWRESET_MASK; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_RTC_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_sctimer.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_sctimer.c deleted file mode 100644 index fb6b97ff615..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_sctimer.c +++ /dev/null @@ -1,559 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_sctimer.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.sctimer" -#endif - -/*! @brief Typedef for interrupt handler. */ -typedef void (*sctimer_isr_t)(SCT_Type *base); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base SCTimer peripheral base address - * - * @return The SCTimer instance - */ -static uint32_t SCTIMER_GetInstance(SCT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to SCT bases for each instance. */ -static SCT_Type *const s_sctBases[] = SCT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to SCT clocks for each instance. */ -static const clock_ip_name_t s_sctClocks[] = SCT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if defined(FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET -/*! @brief Pointers to SCT resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_sctResets[] = SCT_RSTS_N; -#else -/*! @brief Pointers to SCT resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_sctResets[] = SCT_RSTS; -#endif - -/*!< @brief SCTimer event Callback function. */ -static sctimer_event_callback_t s_eventCallback[FSL_FEATURE_SCT_NUMBER_OF_EVENTS]; - -/*!< @brief Keep track of SCTimer event number */ -static uint32_t s_currentEvent; - -/*!< @brief Keep track of SCTimer state number */ -static uint32_t s_currentState; - -/*!< @brief Keep track of SCTimer match/capture register number */ -static uint32_t s_currentMatch; - -/*! @brief Pointer to SCTimer IRQ handler */ -static sctimer_isr_t s_sctimerIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t SCTIMER_GetInstance(SCT_Type *base) -{ - uint32_t instance; - uint32_t sctArrayCount = (sizeof(s_sctBases) / sizeof(s_sctBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < sctArrayCount; instance++) - { - if (s_sctBases[instance] == base) - { - break; - } - } - - assert(instance < sctArrayCount); - - return instance; -} - -status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config) -{ - assert(config); - uint32_t i; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the SCTimer clock*/ - CLOCK_EnableClock(s_sctClocks[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the module */ - RESET_PeripheralReset(s_sctResets[SCTIMER_GetInstance(base)]); - - /* Setup the counter operation */ - base->CONFIG = SCT_CONFIG_CKSEL(config->clockSelect) | SCT_CONFIG_CLKMODE(config->clockMode) | - SCT_CONFIG_UNIFY(config->enableCounterUnify); - - /* Write to the control register, clear the counter and keep the counters halted */ - base->CTRL = SCT_CTRL_BIDIR_L(config->enableBidirection_l) | SCT_CTRL_PRE_L(config->prescale_l) | - SCT_CTRL_CLRCTR_L_MASK | SCT_CTRL_HALT_L_MASK; - - if (!(config->enableCounterUnify)) - { - base->CTRL |= SCT_CTRL_BIDIR_H(config->enableBidirection_h) | SCT_CTRL_PRE_H(config->prescale_h) | - SCT_CTRL_CLRCTR_H_MASK | SCT_CTRL_HALT_H_MASK; - } - - /* Initial state of channel output */ - base->OUTPUT = config->outInitState; - - /* Clear the global variables */ - s_currentEvent = 0; - s_currentState = 0; - s_currentMatch = 0; - - /* Clear the callback array */ - for (i = 0; i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) - { - s_eventCallback[i] = NULL; - } - - /* Save interrupt handler */ - s_sctimerIsr = SCTIMER_EventHandleIRQ; - - return kStatus_Success; -} - -void SCTIMER_Deinit(SCT_Type *base) -{ - /* Halt the counters */ - base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the SCTimer clock*/ - CLOCK_DisableClock(s_sctClocks[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void SCTIMER_GetDefaultConfig(sctimer_config_t *config) -{ - assert(config); - - /* SCT operates as a unified 32-bit counter */ - config->enableCounterUnify = true; - /* System clock clocks the entire SCT module */ - config->clockMode = kSCTIMER_System_ClockMode; - /* This is used only by certain clock modes */ - config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - /* Up count mode only for the unified counter */ - config->enableBidirection_l = false; - /* Up count mode only for Counte_H */ - config->enableBidirection_h = false; - /* Prescale factor of 1 */ - config->prescale_l = 0; - /* Prescale factor of 1 for Counter_H*/ - config->prescale_h = 0; - /* Clear outputs */ - config->outInitState = 0; -} - -status_t SCTIMER_SetupPwm(SCT_Type *base, - const sctimer_pwm_signal_param_t *pwmParams, - sctimer_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - uint32_t *event) -{ - assert(pwmParams); - assert(srcClock_Hz); - assert(pwmFreq_Hz); - assert(pwmParams->output < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - uint32_t period, pulsePeriod = 0; - uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1); - uint32_t periodEvent = 0, pulseEvent = 0; - uint32_t reg; - - /* This function will create 2 events, return an error if we do not have enough events available */ - if ((s_currentEvent + 2) > FSL_FEATURE_SCT_NUMBER_OF_EVENTS) - { - return kStatus_Fail; - } - - if (pwmParams->dutyCyclePercent == 0) - { - return kStatus_Fail; - } - - /* Set unify bit to operate in 32-bit counter mode */ - base->CONFIG |= SCT_CONFIG_UNIFY_MASK; - - /* Use bi-directional mode for center-aligned PWM */ - if (mode == kSCTIMER_CenterAlignedPwm) - { - base->CTRL |= SCT_CTRL_BIDIR_L_MASK; - } - - /* Calculate PWM period match value */ - if (mode == kSCTIMER_EdgeAlignedPwm) - { - period = (sctClock / pwmFreq_Hz) - 1; - } - else - { - period = sctClock / (pwmFreq_Hz * 2); - } - - /* Calculate pulse width match value */ - pulsePeriod = (period * pwmParams->dutyCyclePercent) / 100; - - /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ - if (pwmParams->dutyCyclePercent >= 100) - { - pulsePeriod = period + 2; - } - - /* Schedule an event when we reach the PWM period */ - SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, period, 0, kSCTIMER_Counter_L, &periodEvent); - - /* Schedule an event when we reach the pulse width */ - SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, pulsePeriod, 0, kSCTIMER_Counter_L, &pulseEvent); - - /* Reset the counter when we reach the PWM period */ - SCTIMER_SetupCounterLimitAction(base, kSCTIMER_Counter_L, periodEvent); - - /* Return the period event to the user */ - *event = periodEvent; - - /* For high-true level */ - if (pwmParams->level == kSCTIMER_HighTrue) - { - /* Set the initial output level to low which is the inactive state */ - base->OUTPUT &= ~(1U << pwmParams->output); - - if (mode == kSCTIMER_EdgeAlignedPwm) - { - /* Set the output when we reach the PWM period */ - SCTIMER_SetupOutputSetAction(base, pwmParams->output, periodEvent); - /* Clear the output when we reach the PWM pulse value */ - SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent); - } - else - { - /* Clear the output when we reach the PWM pulse event */ - SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent); - /* Reverse output when down counting */ - reg = base->OUTPUTDIRCTRL; - reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output)); - reg |= (1U << (2 * pwmParams->output)); - base->OUTPUTDIRCTRL = reg; - } - } - /* For low-true level */ - else - { - /* Set the initial output level to high which is the inactive state */ - base->OUTPUT |= (1U << pwmParams->output); - - if (mode == kSCTIMER_EdgeAlignedPwm) - { - /* Clear the output when we reach the PWM period */ - SCTIMER_SetupOutputClearAction(base, pwmParams->output, periodEvent); - /* Set the output when we reach the PWM pulse value */ - SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent); - } - else - { - /* Set the output when we reach the PWM pulse event */ - SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent); - /* Reverse output when down counting */ - reg = base->OUTPUTDIRCTRL; - reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output)); - reg |= (1U << (2 * pwmParams->output)); - base->OUTPUTDIRCTRL = reg; - } - } - - return kStatus_Success; -} - -void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event) - -{ - assert(dutyCyclePercent > 0); - assert(output < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - uint32_t periodMatchReg, pulseMatchReg; - uint32_t pulsePeriod = 0, period; - - /* Retrieve the match register number for the PWM period */ - periodMatchReg = base->EVENT[event].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK; - - /* Retrieve the match register number for the PWM pulse period */ - pulseMatchReg = base->EVENT[event + 1].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK; - - period = base->SCTMATCH[periodMatchReg]; - - /* Calculate pulse width match value */ - pulsePeriod = (period * dutyCyclePercent) / 100; - - /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ - if (dutyCyclePercent >= 100) - { - pulsePeriod = period + 2; - } - - /* Stop the counter before updating match register */ - SCTIMER_StopTimer(base, kSCTIMER_Counter_L); - - /* Update dutycycle */ - base->SCTMATCH[pulseMatchReg] = SCT_SCTMATCH_MATCHn_L(pulsePeriod); - base->SCTMATCHREL[pulseMatchReg] = SCT_SCTMATCHREL_RELOADn_L(pulsePeriod); - - /* Restart the counter */ - SCTIMER_StartTimer(base, kSCTIMER_Counter_L); -} - -status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, - sctimer_event_t howToMonitor, - uint32_t matchValue, - uint32_t whichIO, - sctimer_counter_t whichCounter, - uint32_t *event) -{ - uint32_t combMode = (((uint32_t)howToMonitor & SCT_EVENT_CTRL_COMBMODE_MASK) >> SCT_EVENT_CTRL_COMBMODE_SHIFT); - uint32_t currentCtrlVal = howToMonitor; - - /* Return an error if we have hit the limit in terms of number of events created */ - if (s_currentEvent >= FSL_FEATURE_SCT_NUMBER_OF_EVENTS) - { - return kStatus_Fail; - } - - /* IO only mode */ - if (combMode == 0x2U) - { - base->EVENT[s_currentEvent].CTRL = currentCtrlVal | SCT_EVENT_CTRL_IOSEL(whichIO); - } - /* Match mode only */ - else if (combMode == 0x1U) - { - /* Return an error if we have hit the limit in terms of number of number of match registers */ - if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - return kStatus_Fail; - } - - currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch); - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue); - base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue); - } - else - { - /* Select the counter, no need for this if operating in 32-bit mode */ - currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter); - base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue); - base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue); - } - base->EVENT[s_currentEvent].CTRL = currentCtrlVal; - /* Increment the match register number */ - s_currentMatch++; - } - /* Use both Match & IO */ - else - { - /* Return an error if we have hit the limit in terms of number of number of match registers */ - if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - return kStatus_Fail; - } - - currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch) | SCT_EVENT_CTRL_IOSEL(whichIO); - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue); - base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue); - } - else - { - /* Select the counter, no need for this if operating in 32-bit mode */ - currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter); - base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue); - base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue); - } - base->EVENT[s_currentEvent].CTRL = currentCtrlVal; - /* Increment the match register number */ - s_currentMatch++; - } - - /* Enable the event in the current state */ - base->EVENT[s_currentEvent].STATE = (1U << s_currentState); - - /* Return the event number */ - *event = s_currentEvent; - - /* Increment the event number */ - s_currentEvent++; - - return kStatus_Success; -} - -void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event) -{ - /* Enable event in the current state */ - base->EVENT[event].STATE |= (1U << s_currentState); -} - -status_t SCTIMER_IncreaseState(SCT_Type *base) -{ - /* Return an error if we have hit the limit in terms of states used */ - if (s_currentState >= FSL_FEATURE_SCT_NUMBER_OF_STATES) - { - return kStatus_Fail; - } - - s_currentState++; - - return kStatus_Success; -} - -uint32_t SCTIMER_GetCurrentState(SCT_Type *base) -{ - return s_currentState; -} - -void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - assert(whichIO < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - uint32_t reg; - - /* Set the same event to set and clear the output */ - base->OUT[whichIO].CLR |= (1U << event); - base->OUT[whichIO].SET |= (1U << event); - - /* Set the conflict resolution to toggle output */ - reg = base->RES; - reg &= ~(SCT_RES_O0RES_MASK << (2 * whichIO)); - reg |= (uint32_t)(kSCTIMER_ResolveToggle << (2 * whichIO)); - base->RES = reg; -} - -status_t SCTIMER_SetupCaptureAction(SCT_Type *base, - sctimer_counter_t whichCounter, - uint32_t *captureRegister, - uint32_t event) -{ - /* Return an error if we have hit the limit in terms of number of capture/match registers used */ - if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - return kStatus_Fail; - } - - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - /* Set the bit to enable event */ - base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_L(1 << event); - - /* Set this resource to be a capture rather than match */ - base->REGMODE |= SCT_REGMODE_REGMOD_L(1 << s_currentMatch); - } - else - { - /* Set bit to enable event */ - base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_H(1 << event); - - /* Set this resource to be a capture rather than match */ - base->REGMODE |= SCT_REGMODE_REGMOD_H(1 << s_currentMatch); - } - - /* Return the match register number */ - *captureRegister = s_currentMatch; - - /* Increase the match register number */ - s_currentMatch++; - - return kStatus_Success; -} - -void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event) -{ - s_eventCallback[event] = callback; -} - -void SCTIMER_EventHandleIRQ(SCT_Type *base) -{ - uint32_t eventFlag = SCT0->EVFLAG; - /* Only clear the flags whose interrupt field is enabled */ - uint32_t clearFlag = (eventFlag & SCT0->EVEN); - uint32_t mask = eventFlag; - int i = 0; - - /* Invoke the callback for certain events */ - for (i = 0; (i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS) && (mask != 0); i++) - { - if (mask & 0x1) - { - if (s_eventCallback[i] != NULL) - { - s_eventCallback[i](); - } - } - mask >>= 1; - } - - /* Clear event interrupt flag */ - SCT0->EVFLAG = clearFlag; -} - -void SCT0_IRQHandler(void) -{ - s_sctimerIsr(SCT0); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_sctimer.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_sctimer.h deleted file mode 100644 index 4274aa8068b..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_sctimer.h +++ /dev/null @@ -1,834 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_SCTIMER_H_ -#define _FSL_SCTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup sctimer - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! @brief SCTimer PWM operation modes */ -typedef enum _sctimer_pwm_mode -{ - kSCTIMER_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */ - kSCTIMER_CenterAlignedPwm /*!< Center-aligned PWM */ -} sctimer_pwm_mode_t; - -/*! @brief SCTimer counters when working as two independent 16-bit counters */ -typedef enum _sctimer_counter -{ - kSCTIMER_Counter_L = 0U, /*!< Counter L */ - kSCTIMER_Counter_H /*!< Counter H */ -} sctimer_counter_t; - -/*! @brief List of SCTimer input pins */ -typedef enum _sctimer_input -{ - kSCTIMER_Input_0 = 0U, /*!< SCTIMER input 0 */ - kSCTIMER_Input_1, /*!< SCTIMER input 1 */ - kSCTIMER_Input_2, /*!< SCTIMER input 2 */ - kSCTIMER_Input_3, /*!< SCTIMER input 3 */ - kSCTIMER_Input_4, /*!< SCTIMER input 4 */ - kSCTIMER_Input_5, /*!< SCTIMER input 5 */ - kSCTIMER_Input_6, /*!< SCTIMER input 6 */ - kSCTIMER_Input_7 /*!< SCTIMER input 7 */ -} sctimer_input_t; - -/*! @brief List of SCTimer output pins */ -typedef enum _sctimer_out -{ - kSCTIMER_Out_0 = 0U, /*!< SCTIMER output 0*/ - kSCTIMER_Out_1, /*!< SCTIMER output 1 */ - kSCTIMER_Out_2, /*!< SCTIMER output 2 */ - kSCTIMER_Out_3, /*!< SCTIMER output 3 */ - kSCTIMER_Out_4, /*!< SCTIMER output 4 */ - kSCTIMER_Out_5, /*!< SCTIMER output 5 */ - kSCTIMER_Out_6, /*!< SCTIMER output 6 */ - kSCTIMER_Out_7, /*!< SCTIMER output 7 */ - kSCTIMER_Out_8, /*!< SCTIMER output 8 */ - kSCTIMER_Out_9 /*!< SCTIMER output 9 */ -} sctimer_out_t; - -/*! @brief SCTimer PWM output pulse mode: high-true, low-true or no output */ -typedef enum _sctimer_pwm_level_select -{ - kSCTIMER_LowTrue = 0U, /*!< Low true pulses */ - kSCTIMER_HighTrue /*!< High true pulses */ -} sctimer_pwm_level_select_t; - -/*! @brief Options to configure a SCTimer PWM signal */ -typedef struct _sctimer_pwm_signal_param -{ - sctimer_out_t output; /*!< The output pin to use to generate the PWM signal */ - sctimer_pwm_level_select_t level; /*!< PWM output active level select. */ - uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 1 to 100 - 100 = always active signal (100% duty cycle).*/ -} sctimer_pwm_signal_param_t; - -/*! @brief SCTimer clock mode options */ -typedef enum _sctimer_clock_mode -{ - kSCTIMER_System_ClockMode = 0U, /*!< System Clock Mode */ - kSCTIMER_Sampled_ClockMode, /*!< Sampled System Clock Mode */ - kSCTIMER_Input_ClockMode, /*!< SCT Input Clock Mode */ - kSCTIMER_Asynchronous_ClockMode /*!< Asynchronous Mode */ -} sctimer_clock_mode_t; - -/*! @brief SCTimer clock select options */ -typedef enum _sctimer_clock_select -{ - kSCTIMER_Clock_On_Rise_Input_0 = 0U, /*!< Rising edges on input 0 */ - kSCTIMER_Clock_On_Fall_Input_0, /*!< Falling edges on input 0 */ - kSCTIMER_Clock_On_Rise_Input_1, /*!< Rising edges on input 1 */ - kSCTIMER_Clock_On_Fall_Input_1, /*!< Falling edges on input 1 */ - kSCTIMER_Clock_On_Rise_Input_2, /*!< Rising edges on input 2 */ - kSCTIMER_Clock_On_Fall_Input_2, /*!< Falling edges on input 2 */ - kSCTIMER_Clock_On_Rise_Input_3, /*!< Rising edges on input 3 */ - kSCTIMER_Clock_On_Fall_Input_3, /*!< Falling edges on input 3 */ - kSCTIMER_Clock_On_Rise_Input_4, /*!< Rising edges on input 4 */ - kSCTIMER_Clock_On_Fall_Input_4, /*!< Falling edges on input 4 */ - kSCTIMER_Clock_On_Rise_Input_5, /*!< Rising edges on input 5 */ - kSCTIMER_Clock_On_Fall_Input_5, /*!< Falling edges on input 5 */ - kSCTIMER_Clock_On_Rise_Input_6, /*!< Rising edges on input 6 */ - kSCTIMER_Clock_On_Fall_Input_6, /*!< Falling edges on input 6 */ - kSCTIMER_Clock_On_Rise_Input_7, /*!< Rising edges on input 7 */ - kSCTIMER_Clock_On_Fall_Input_7 /*!< Falling edges on input 7 */ -} sctimer_clock_select_t; - -/*! - * @brief SCTimer output conflict resolution options. - * - * Specifies what action should be taken if multiple events dictate that a given output should be - * both set and cleared at the same time - */ -typedef enum _sctimer_conflict_resolution -{ - kSCTIMER_ResolveNone = 0U, /*!< No change */ - kSCTIMER_ResolveSet, /*!< Set output */ - kSCTIMER_ResolveClear, /*!< Clear output */ - kSCTIMER_ResolveToggle /*!< Toggle output */ -} sctimer_conflict_resolution_t; - -/*! @brief List of SCTimer event types */ -typedef enum _sctimer_event -{ - kSCTIMER_InputLowOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - - kSCTIMER_MatchEventOnly = - (1 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - - kSCTIMER_InputLowEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - - kSCTIMER_InputLowAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT) -} sctimer_event_t; - -/*! @brief SCTimer callback typedef. */ -typedef void (*sctimer_event_callback_t)(void); - -/*! @brief List of SCTimer interrupts */ -typedef enum _sctimer_interrupt_enable -{ - kSCTIMER_Event0InterruptEnable = (1U << 0), /*!< Event 0 interrupt */ - kSCTIMER_Event1InterruptEnable = (1U << 1), /*!< Event 1 interrupt */ - kSCTIMER_Event2InterruptEnable = (1U << 2), /*!< Event 2 interrupt */ - kSCTIMER_Event3InterruptEnable = (1U << 3), /*!< Event 3 interrupt */ - kSCTIMER_Event4InterruptEnable = (1U << 4), /*!< Event 4 interrupt */ - kSCTIMER_Event5InterruptEnable = (1U << 5), /*!< Event 5 interrupt */ - kSCTIMER_Event6InterruptEnable = (1U << 6), /*!< Event 6 interrupt */ - kSCTIMER_Event7InterruptEnable = (1U << 7), /*!< Event 7 interrupt */ - kSCTIMER_Event8InterruptEnable = (1U << 8), /*!< Event 8 interrupt */ - kSCTIMER_Event9InterruptEnable = (1U << 9), /*!< Event 9 interrupt */ - kSCTIMER_Event10InterruptEnable = (1U << 10), /*!< Event 10 interrupt */ - kSCTIMER_Event11InterruptEnable = (1U << 11), /*!< Event 11 interrupt */ - kSCTIMER_Event12InterruptEnable = (1U << 12), /*!< Event 12 interrupt */ -} sctimer_interrupt_enable_t; - -/*! @brief List of SCTimer flags */ -typedef enum _sctimer_status_flags -{ - kSCTIMER_Event0Flag = (1U << 0), /*!< Event 0 Flag */ - kSCTIMER_Event1Flag = (1U << 1), /*!< Event 1 Flag */ - kSCTIMER_Event2Flag = (1U << 2), /*!< Event 2 Flag */ - kSCTIMER_Event3Flag = (1U << 3), /*!< Event 3 Flag */ - kSCTIMER_Event4Flag = (1U << 4), /*!< Event 4 Flag */ - kSCTIMER_Event5Flag = (1U << 5), /*!< Event 5 Flag */ - kSCTIMER_Event6Flag = (1U << 6), /*!< Event 6 Flag */ - kSCTIMER_Event7Flag = (1U << 7), /*!< Event 7 Flag */ - kSCTIMER_Event8Flag = (1U << 8), /*!< Event 8 Flag */ - kSCTIMER_Event9Flag = (1U << 9), /*!< Event 9 Flag */ - kSCTIMER_Event10Flag = (1U << 10), /*!< Event 10 Flag */ - kSCTIMER_Event11Flag = (1U << 11), /*!< Event 11 Flag */ - kSCTIMER_Event12Flag = (1U << 12), /*!< Event 12 Flag */ - kSCTIMER_BusErrorLFlag = - (1U << SCT_CONFLAG_BUSERRL_SHIFT), /*!< Bus error due to write when L counter was not halted */ - kSCTIMER_BusErrorHFlag = - (1U << SCT_CONFLAG_BUSERRH_SHIFT) /*!< Bus error due to write when H counter was not halted */ -} sctimer_status_flags_t; - -/*! - * @brief SCTimer configuration structure - * - * This structure holds the configuration settings for the SCTimer peripheral. To initialize this - * structure to reasonable defaults, call the SCTMR_GetDefaultConfig() function and pass a - * pointer to the configuration structure instance. - * - * The configuration structure can be made constant so as to reside in flash. - */ -typedef struct _sctimer_config -{ - bool enableCounterUnify; /*!< true: SCT operates as a unified 32-bit counter; - false: SCT operates as two 16-bit counters */ - sctimer_clock_mode_t clockMode; /*!< SCT clock mode value */ - sctimer_clock_select_t clockSelect; /*!< SCT clock select value */ - bool enableBidirection_l; /*!< true: Up-down count mode for the L or unified counter - false: Up count mode only for the L or unified counter */ - bool enableBidirection_h; /*!< true: Up-down count mode for the H or unified counter - false: Up count mode only for the H or unified counter. - This field is used only if the enableCounterUnify is set - to false */ - uint8_t prescale_l; /*!< Prescale value to produce the L or unified counter clock */ - uint8_t prescale_h; /*!< Prescale value to produce the H counter clock. - This field is used only if the enableCounterUnify is set - to false */ - uint8_t outInitState; /*!< Defines the initial output value */ -} sctimer_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the SCTimer clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the SCTimer driver. - * - * @param base SCTimer peripheral base address - * @param config Pointer to the user configuration structure. - * - * @return kStatus_Success indicates success; Else indicates failure. - */ -status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config); - -/*! - * @brief Gates the SCTimer clock. - * - * @param base SCTimer peripheral base address - */ -void SCTIMER_Deinit(SCT_Type *base); - -/*! - * @brief Fills in the SCTimer configuration structure with the default settings. - * - * The default values are: - * @code - * config->enableCounterUnify = true; - * config->clockMode = kSCTIMER_System_ClockMode; - * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - * config->enableBidirection_l = false; - * config->enableBidirection_h = false; - * config->prescale_l = 0; - * config->prescale_h = 0; - * config->outInitState = 0; - * @endcode - * @param config Pointer to the user configuration structure. - */ -void SCTIMER_GetDefaultConfig(sctimer_config_t *config); - -/*! @}*/ - -/*! - * @name PWM setup operations - * @{ - */ - -/*! - * @brief Configures the PWM signal parameters. - * - * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This - * function will create 2 events; one of the events will trigger on match with the pulse value - * and the other will trigger when the counter matches the PWM period. The PWM period event is - * also used as a limit event to reset the counter or change direction. Both events are enabled - * for the same state. The state number can be retrieved by calling the function - * SCTIMER_GetCurrentStateNumber(). - * The counter is set to operate as one 32-bit counter (unify bit is set to 1). - * The counter operates in bi-directional mode when generating a center-aligned PWM. - * - * @note When setting PWM output from multiple output pins, they all should use the same PWM mode - * i.e all PWM's should be either edge-aligned or center-aligned. - * When using this API, the PWM signal frequency of all the initialized channels must be the same. - * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the - * API's pwmFreq_Hz. - * - * @param base SCTimer peripheral base address - * @param pwmParams PWM parameters to configure the output - * @param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz SCTimer counter clock in Hz - * @param event Pointer to a variable where the PWM period event number is stored - * - * @return kStatus_Success on success - * kStatus_Fail If we have hit the limit in terms of number of events created or if - * an incorrect PWM dutycylce is passed in. - */ -status_t SCTIMER_SetupPwm(SCT_Type *base, - const sctimer_pwm_signal_param_t *pwmParams, - sctimer_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - uint32_t *event); - -/*! - * @brief Updates the duty cycle of an active PWM signal. - * - * @param base SCTimer peripheral base address - * @param output The output to configure - * @param dutyCyclePercent New PWM pulse width; the value should be between 1 to 100 - * @param event Event number associated with this PWM signal. This was returned to the user by the - * function SCTIMER_SetupPwm(). - */ -void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event); - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline void SCTIMER_EnableInterrupts(SCT_Type *base, uint32_t mask) -{ - base->EVEN |= mask; -} - -/*! - * @brief Disables the selected SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline void SCTIMER_DisableInterrupts(SCT_Type *base, uint32_t mask) -{ - base->EVEN &= ~mask; -} - -/*! - * @brief Gets the enabled SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline uint32_t SCTIMER_GetEnabledInterrupts(SCT_Type *base) -{ - return (base->EVEN & 0xFFFFU); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the SCTimer status flags. - * - * @param base SCTimer peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::sctimer_status_flags_t - */ -static inline uint32_t SCTIMER_GetStatusFlags(SCT_Type *base) -{ - uint32_t statusFlags = 0; - - /* Add the recorded events */ - statusFlags = (base->EVFLAG & 0xFFFFU); - - /* Add bus error flags */ - statusFlags |= (base->CONFLAG & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); - - return statusFlags; -} - -/*! - * @brief Clears the SCTimer status flags. - * - * @param base SCTimer peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::sctimer_status_flags_t - */ -static inline void SCTIMER_ClearStatusFlags(SCT_Type *base, uint32_t mask) -{ - /* Write to the flag registers */ - base->EVFLAG = (mask & 0xFFFFU); - base->CONFLAG = (mask & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); -} - -/*! @}*/ - -/*! - * @name Counter Start and Stop - * @{ - */ - -/*! - * @brief Starts the SCTimer counter. - * - * @param base SCTimer peripheral base address - * @param countertoStart SCTimer counter to start; if unify mode is set then function always - * writes to HALT_L bit - */ -static inline void SCTIMER_StartTimer(SCT_Type *base, sctimer_counter_t countertoStart) -{ - /* Clear HALT_L bit if counter is operating in 32-bit mode or user wants to start L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStart == kSCTIMER_Counter_L)) - { - base->CTRL &= ~(SCT_CTRL_HALT_L_MASK); - } - else - { - /* Start H counter */ - base->CTRL &= ~(SCT_CTRL_HALT_H_MASK); - } -} - -/*! - * @brief Halts the SCTimer counter. - * - * @param base SCTimer peripheral base address - * @param countertoStop SCTimer counter to stop; if unify mode is set then function always - * writes to HALT_L bit - */ -static inline void SCTIMER_StopTimer(SCT_Type *base, sctimer_counter_t countertoStop) -{ - /* Set HALT_L bit if counter is operating in 32-bit mode or user wants to stop L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStop == kSCTIMER_Counter_L)) - { - base->CTRL |= (SCT_CTRL_HALT_L_MASK); - } - else - { - /* Stop H counter */ - base->CTRL |= (SCT_CTRL_HALT_H_MASK); - } -} - -/*! @}*/ - -/*! - * @name Functions to create a new event and manage the state logic - * @{ - */ - -/*! - * @brief Create an event that is triggered on a match or IO and schedule in current state. - * - * This function will configure an event using the options provided by the user. If the event type uses - * the counter match, then the function will set the user provided match value into a match register - * and put this match register number into the event control register. - * The event is enabled for the current state and the event number is increased by one at the end. - * The function returns the event number; this event number can be used to configure actions to be - * done when this event is triggered. - * - * @param base SCTimer peripheral base address - * @param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t - * @param matchValue The match value that will be programmed to a match register - * @param whichIO The input or output that will be involved in event triggering. This field - * is ignored if the event type is "match only" - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as we have only 1 unified counter; hence ignored. - * @param event Pointer to a variable where the new event number is stored - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of events created or - if we have reached the limit in terms of number of match registers - */ -status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, - sctimer_event_t howToMonitor, - uint32_t matchValue, - uint32_t whichIO, - sctimer_counter_t whichCounter, - uint32_t *event); - -/*! - * @brief Enable an event in the current state. - * - * This function will allow the event passed in to trigger in the current state. The event must - * be created earlier by either calling the function SCTIMER_SetupPwm() or function - * SCTIMER_CreateAndScheduleEvent() . - * - * @param base SCTimer peripheral base address - * @param event Event number to enable in the current state - * - */ -void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event); - -/*! - * @brief Increase the state by 1 - * - * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new - * state. - * - * @param base SCTimer peripheral base address - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of states used - - */ -status_t SCTIMER_IncreaseState(SCT_Type *base); - -/*! - * @brief Provides the current state - * - * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). - * - * @param base SCTimer peripheral base address - * - * @return The current state - */ -uint32_t SCTIMER_GetCurrentState(SCT_Type *base); - -/*! @}*/ - -/*! - * @name Actions to take in response to an event - * @{ - */ - -/*! - * @brief Setup capture of the counter value on trigger of a selected event - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. - * @param captureRegister Pointer to a variable where the capture register number will be returned. User - * can read the captured value from this register when the specified event is triggered. - * @param event Event number that will trigger the capture - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of match/capture registers available - */ -status_t SCTIMER_SetupCaptureAction(SCT_Type *base, - sctimer_counter_t whichCounter, - uint32_t *captureRegister, - uint32_t event); - -/*! - * @brief Receive noticification when the event trigger an interrupt. - * - * If the interrupt for the event is enabled by the user, then a callback can be registered - * which will be invoked when the event is triggered - * - * @param base SCTimer peripheral base address - * @param event Event number that will trigger the interrupt - * @param callback Function to invoke when the event is triggered - */ - -void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event); - -/*! - * @brief Transition to the specified state. - * - * This transition will be triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param nextState The next state SCTimer will transition to - * @param event Event number that will trigger the state transition - */ -static inline void SCTIMER_SetupNextStateAction(SCT_Type *base, uint32_t nextState, uint32_t event) -{ - uint32_t reg = base->EVENT[event].CTRL; - - reg &= ~(SCT_EVENT_CTRL_STATEV_MASK); - /* Load the STATEV value when the event occurs to be the next state */ - reg |= SCT_EVENT_CTRL_STATEV(nextState) | SCT_EVENT_CTRL_STATELD_MASK; - - base->EVENT[event].CTRL = reg; -} - -/*! - * @brief Set the Output. - * - * This output will be set when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to set - * @param event Event number that will trigger the output change - */ -static inline void SCTIMER_SetupOutputSetAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - assert(whichIO < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - base->OUT[whichIO].SET |= (1U << event); -} - -/*! - * @brief Clear the Output. - * - * This output will be cleared when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to clear - * @param event Event number that will trigger the output change - */ -static inline void SCTIMER_SetupOutputClearAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - assert(whichIO < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - base->OUT[whichIO].CLR |= (1U << event); -} - -/*! - * @brief Toggle the output level. - * - * This change in the output level is triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to toggle - * @param event Event number that will trigger the output change - */ -void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event); - -/*! - * @brief Limit the running counter. - * - * The counter is limited when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. - * @param event Event number that will trigger the counter to be limited - */ -static inline void SCTIMER_SetupCounterLimitAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - base->LIMIT |= SCT_LIMIT_LIMMSK_L(1U << event); - } - else - { - base->LIMIT |= SCT_LIMIT_LIMMSK_H(1U << event); - } -} - -/*! - * @brief Stop the running counter. - * - * The counter is stopped when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. - * @param event Event number that will trigger the counter to be stopped - */ -static inline void SCTIMER_SetupCounterStopAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - base->STOP |= SCT_STOP_STOPMSK_L(1U << event); - } - else - { - base->STOP |= SCT_STOP_STOPMSK_H(1U << event); - } -} - -/*! - * @brief Re-start the stopped counter. - * - * The counter will re-start when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. - * @param event Event number that will trigger the counter to re-start - */ -static inline void SCTIMER_SetupCounterStartAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - base->START |= SCT_START_STARTMSK_L(1U << event); - } - else - { - base->START |= SCT_START_STARTMSK_H(1U << event); - } -} - -/*! - * @brief Halt the running counter. - * - * The counter is disabled (halted) when the event number that is passed in by the user is - * triggered. When the counter is halted, all further events are disabled. The HALT condition - * can only be removed by calling the SCTIMER_StartTimer() function. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. - * @param event Event number that will trigger the counter to be halted - */ -static inline void SCTIMER_SetupCounterHaltAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - base->HALT |= SCT_HALT_HALTMSK_L(1U << event); - } - else - { - base->HALT |= SCT_HALT_HALTMSK_H(1U << event); - } -} - -#if !(defined(FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) && FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) -/*! - * @brief Generate a DMA request. - * - * DMA request will be triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param dmaNumber The DMA request to generate - * @param event Event number that will trigger the DMA request - */ -static inline void SCTIMER_SetupDmaTriggerAction(SCT_Type *base, uint32_t dmaNumber, uint32_t event) -{ - if (dmaNumber == 0) - { - base->DMA0REQUEST |= (1U << event); - } - else - { - base->DMA1REQUEST |= (1U << event); - } -} -#endif /* FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST */ - -/*! - * @brief SCTimer interrupt handler. - * - * @param base SCTimer peripheral base address. - */ -void SCTIMER_EventHandleIRQ(SCT_Type *base); - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_SCTIMER_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi.c deleted file mode 100644 index 8c50edc7a03..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi.c +++ /dev/null @@ -1,864 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_spi.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi" -#endif - -/* Note: FIFOCFG[SIZE] has always value 1 = 8 items depth */ -#define SPI_FIFO_DEPTH(base) ((((base)->FIFOCFG & SPI_FIFOCFG_SIZE_MASK) >> SPI_FIFOCFG_SIZE_SHIFT) << 3) - -/* Convert transfer count to transfer bytes. dataWidth is a - * range <0,15>. Range <8,15> represents 2B transfer */ -#define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U)) -#define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U)) -#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK) | (SPI_CFG_SPOL3_MASK)) - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief internal SPI config array */ -static spi_config_t g_configs[FSL_FEATURE_SOC_SPI_COUNT] = {(spi_data_width_t)0}; - -/*! @brief Array to map SPI instance number to base address. */ -static const uint32_t s_spiBaseAddrs[FSL_FEATURE_SOC_SPI_COUNT] = SPI_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_spiIRQ[] = SPI_IRQS; - -/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ -volatile uint8_t s_dummyData[FSL_FEATURE_SOC_SPI_COUNT] = {0}; -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Get the index corresponding to the FLEXCOMM */ -uint32_t SPI_GetInstance(SPI_Type *base) -{ - int i; - - for (i = 0; i < FSL_FEATURE_SOC_SPI_COUNT; i++) - { - if ((uint32_t)base == s_spiBaseAddrs[i]) - { - return i; - } - } - - assert(false); - return 0; -} - -void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData) -{ - uint32_t instance = SPI_GetInstance(base); - s_dummyData[instance] = dummyData; -} - -void *SPI_GetConfig(SPI_Type *base) -{ - int32_t instance; - instance = SPI_GetInstance(base); - if (instance < 0) - { - return NULL; - } - return &g_configs[instance]; -} - -void SPI_MasterGetDefaultConfig(spi_master_config_t *config) -{ - assert(NULL != config); - - config->enableLoopback = false; - config->enableMaster = true; - config->polarity = kSPI_ClockPolarityActiveHigh; - config->phase = kSPI_ClockPhaseFirstEdge; - config->direction = kSPI_MsbFirst; - config->baudRate_Bps = 500000U; - config->dataWidth = kSPI_Data8Bits; - config->sselNum = kSPI_Ssel0; - config->txWatermark = kSPI_TxFifo0; - config->rxWatermark = kSPI_RxFifo1; - config->sselPol = kSPI_SpolActiveAllLow; - config->delayConfig.preDelay = 0U; - config->delayConfig.postDelay = 0U; - config->delayConfig.frameDelay = 0U; - config->delayConfig.transferDelay = 0U; -} - -status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz) -{ - int32_t result = 0, instance = 0; - uint32_t tmp; - - /* assert params */ - assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz))); - if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* initialize flexcomm to SPI mode */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); - assert(kStatus_Success == result); - if (kStatus_Success != result) - { - return result; - } - - /* set divider */ - result = SPI_MasterSetBaud(base, config->baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - /* get instance number */ - instance = SPI_GetInstance(base); - assert(instance >= 0); - - /* configure SPI mode */ - tmp = base->CFG; - tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | - SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); - /* phase */ - tmp |= SPI_CFG_CPHA(config->phase); - /* polarity */ - tmp |= SPI_CFG_CPOL(config->polarity); - /* direction */ - tmp |= SPI_CFG_LSBF(config->direction); - /* master mode */ - tmp |= SPI_CFG_MASTER(1); - /* loopback */ - tmp |= SPI_CFG_LOOP(config->enableLoopback); - /* configure active level for all CS */ - tmp |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); - base->CFG = tmp; - - /* store configuration */ - g_configs[instance].dataWidth = config->dataWidth; - g_configs[instance].sselNum = config->sselNum; - /* enable FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; - /* trigger level - empty txFIFO, one item in rxFIFO */ - tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); - tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable generating interrupts for FIFOTRIG levels */ - tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; - /* set FIFOTRIG */ - base->FIFOTRIG = tmp; - - /* Set the delay configuration. */ - SPI_SetTransferDelay(base, &config->delayConfig); - /* Set the dummy data. */ - SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); - - SPI_Enable(base, config->enableMaster); - return kStatus_Success; -} - -void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config) -{ - assert(NULL != config); - - config->enableSlave = true; - config->polarity = kSPI_ClockPolarityActiveHigh; - config->phase = kSPI_ClockPhaseFirstEdge; - config->direction = kSPI_MsbFirst; - config->dataWidth = kSPI_Data8Bits; - config->txWatermark = kSPI_TxFifo0; - config->rxWatermark = kSPI_RxFifo1; - config->sselPol = kSPI_SpolActiveAllLow; -} - -status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) -{ - int32_t result = 0, instance; - uint32_t tmp; - - /* assert params */ - assert(!((NULL == base) || (NULL == config))); - if ((NULL == base) || (NULL == config)) - { - return kStatus_InvalidArgument; - } - /* configure flexcomm to SPI, enable clock gate */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); - assert(kStatus_Success == result); - if (kStatus_Success != result) - { - return result; - } - - instance = SPI_GetInstance(base); - - /* configure SPI mode */ - tmp = base->CFG; - tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_ENABLE_MASK | - SPI_SSELPOL_MASK); - /* phase */ - tmp |= SPI_CFG_CPHA(config->phase); - /* polarity */ - tmp |= SPI_CFG_CPOL(config->polarity); - /* direction */ - tmp |= SPI_CFG_LSBF(config->direction); - /* configure active level for all CS */ - tmp |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); - base->CFG = tmp; - - /* store configuration */ - g_configs[instance].dataWidth = config->dataWidth; - /* empty and enable FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; - /* trigger level - empty txFIFO, one item in rxFIFO */ - tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); - tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable generating interrupts for FIFOTRIG levels */ - tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; - /* set FIFOTRIG */ - base->FIFOTRIG = tmp; - - SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); - - SPI_Enable(base, config->enableSlave); - return kStatus_Success; -} - -void SPI_Deinit(SPI_Type *base) -{ - /* Assert arguments */ - assert(NULL != base); - /* Disable interrupts, disable dma requests, disable peripheral */ - base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXERR_MASK | SPI_FIFOINTENCLR_RXERR_MASK | SPI_FIFOINTENCLR_TXLVL_MASK | - SPI_FIFOINTENCLR_RXLVL_MASK; - base->FIFOCFG &= ~(SPI_FIFOCFG_DMATX_MASK | SPI_FIFOCFG_DMARX_MASK); - base->CFG &= ~(SPI_CFG_ENABLE_MASK); -} - -void SPI_EnableTxDMA(SPI_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= SPI_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= ~SPI_FIFOCFG_DMATX_MASK; - } -} - -void SPI_EnableRxDMA(SPI_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= SPI_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= ~SPI_FIFOCFG_DMARX_MASK; - } -} - -status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) -{ - uint32_t tmp; - - /* assert params */ - assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))); - if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* calculate baudrate */ - tmp = (srcClock_Hz / baudrate_Bps) - 1; - if (tmp > 0xFFFF) - { - return kStatus_SPI_BaudrateNotSupport; - } - base->DIV &= ~SPI_DIV_DIVVAL_MASK; - base->DIV |= SPI_DIV_DIVVAL(tmp); - return kStatus_Success; -} - -void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags) -{ - uint32_t control = 0; - int32_t instance; - - /* check params */ - assert(NULL != base); - /* get and check instance */ - instance = SPI_GetInstance(base); - assert(!(instance < 0)); - if (instance < 0) - { - return; - } - - /* set data width */ - control |= SPI_FIFOWR_LEN(g_configs[instance].dataWidth); - /* set sssel */ - control |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum))); - /* mask configFlags */ - control |= (configFlags & SPI_FIFOWR_FLAGS_MASK); - /* control should not affect lower 16 bits */ - assert(!(control & 0xFFFF)); - base->FIFOWR = data | control; -} - -status_t SPI_MasterTransferCreateHandle(SPI_Type *base, - spi_master_handle_t *handle, - spi_master_callback_t callback, - void *userData) -{ - int32_t instance = 0; - - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } - /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - /* get flexcomm instance by 'base' param */ - instance = SPI_GetInstance(base); - assert(!(instance < 0)); - if (instance < 0) - { - return kStatus_InvalidArgument; - } - - memset(handle, 0, sizeof(*handle)); - /* Initialize the handle */ - if (base->CFG & SPI_CFG_MASTER_MASK) - { - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)SPI_MasterTransferHandleIRQ, handle); - } - else - { - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)SPI_SlaveTransferHandleIRQ, handle); - } - - handle->dataWidth = g_configs[instance].dataWidth; - /* in slave mode, the sselNum is not important */ - handle->sselNum = g_configs[instance].sselNum; - handle->txWatermark = (spi_txfifo_watermark_t)SPI_FIFOTRIG_TXLVL_GET(base); - handle->rxWatermark = (spi_rxfifo_watermark_t)SPI_FIFOTRIG_RXLVL_GET(base); - handle->callback = callback; - handle->userData = userData; - - /* Enable SPI NVIC */ - EnableIRQ(s_spiIRQ[instance]); - - return kStatus_Success; -} - -status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) -{ - int32_t instance; - uint32_t tx_ctrl = 0, last_ctrl = 0; - uint32_t tmp32, rxRemainingBytes, txRemainingBytes, dataWidth; - uint32_t toReceiveCount = 0; - uint8_t *txData, *rxData; - uint32_t fifoDepth; - - /* check params */ - // assert(!((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); - if ((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) - { - return kStatus_InvalidArgument; - } - - fifoDepth = SPI_FIFO_DEPTH(base); - txData = xfer->txData; - rxData = xfer->rxData; - txRemainingBytes = txData ? xfer->dataSize : 0; - rxRemainingBytes = rxData ? xfer->dataSize : 0; - - instance = SPI_GetInstance(base); - assert(instance >= 0); - dataWidth = g_configs[instance].dataWidth; - - /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ - assert(!((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))); - if ((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)) - { - return kStatus_InvalidArgument; - } - - /* clear tx/rx errors and empty FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - /* select slave to talk with */ - tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum))); - /* set width of data - range asserted at entry */ - tx_ctrl |= SPI_FIFOWR_LEN(dataWidth); - /* delay for frames */ - tx_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; - /* end of transfer */ - last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0; - /* last index of loop */ - while (txRemainingBytes || rxRemainingBytes || toReceiveCount) - { - /* if rxFIFO is not empty */ - if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) - { - tmp32 = base->FIFORD; - /* rxBuffer is not empty */ - if (rxRemainingBytes) - { - *(rxData++) = tmp32; - rxRemainingBytes--; - /* read 16 bits at once */ - if (dataWidth > 8) - { - *(rxData++) = tmp32 >> 8; - rxRemainingBytes--; - } - } - /* decrease number of data expected to receive */ - toReceiveCount -= 1; - } - /* transmit if txFIFO is not full and data to receive does not exceed FIFO depth */ - if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (toReceiveCount < fifoDepth) && - ((txRemainingBytes) || (rxRemainingBytes >= SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1)))) - { - /* txBuffer is not empty */ - if (txRemainingBytes) - { - tmp32 = *(txData++); - txRemainingBytes--; - /* write 16 bit at once */ - if (dataWidth > 8) - { - tmp32 |= ((uint32_t)(*(txData++))) << 8U; - txRemainingBytes--; - } - if (!txRemainingBytes) - { - tx_ctrl |= last_ctrl; - } - } - else - { - tmp32 = ((uint32_t)s_dummyData[instance] << 8U | (s_dummyData[instance])); - /* last transfer */ - if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1)) - { - tx_ctrl |= last_ctrl; - } - } - /* send data */ - tmp32 = tx_ctrl | tmp32; - base->FIFOWR = tmp32; - toReceiveCount += 1; - } - } - /* wait if TX FIFO of previous transfer is not empty */ - while (!(base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) - { - } - return kStatus_Success; -} - -status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer) -{ - /* check params */ - assert( - !((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) - { - return kStatus_InvalidArgument; - } - - /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ - assert(!((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))); - if ((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)) - { - return kStatus_InvalidArgument; - } - - /* Check if SPI is busy */ - if (handle->state == kStatus_SPI_Busy) - { - return kStatus_SPI_Busy; - } - - /* Set the handle information */ - handle->txData = xfer->txData; - handle->rxData = xfer->rxData; - /* set count */ - handle->txRemainingBytes = xfer->txData ? xfer->dataSize : 0; - handle->rxRemainingBytes = xfer->rxData ? xfer->dataSize : 0; - handle->totalByteCount = xfer->dataSize; - /* other options */ - handle->toReceiveCount = 0; - handle->configFlags = xfer->configFlags; - /* Set the SPI state to busy */ - handle->state = kStatus_SPI_Busy; - /* clear FIFOs when transfer starts */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - /* enable generating txIRQ and rxIRQ, first transfer is fired by empty txFIFO */ - base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK; - return kStatus_Success; -} - -status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer) -{ - assert(xfer); - - spi_transfer_t tempXfer = {0}; - status_t status; - - if (xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the pcs pin keep assert between transmit and receive. */ - if (xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); - } - else - { - tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; - } - - status = SPI_MasterTransferBlocking(base, &tempXfer); - - if (status != kStatus_Success) - { - return status; - } - - if (xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - /* SPI transfer blocking. */ - status = SPI_MasterTransferBlocking(base, &tempXfer); - - return status; -} - -status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, - spi_master_handle_t *handle, - spi_half_duplex_transfer_t *xfer) -{ - assert(xfer); - assert(handle); - spi_transfer_t tempXfer = {0}; - status_t status; - - if (xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the PCS pin keep assert between transmit and receive. */ - if (xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); - } - else - { - tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; - } - - status = SPI_MasterTransferBlocking(base, &tempXfer); - if (status != kStatus_Success) - { - return status; - } - - if (xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - status = SPI_MasterTransferNonBlocking(base, handle, &tempXfer); - - return status; -} - -status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count) -{ - assert(NULL != handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != kStatus_SPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - *count = handle->totalByteCount - handle->rxRemainingBytes; - return kStatus_Success; -} - -void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle) -{ - assert(NULL != handle); - - /* Disable interrupt requests*/ - base->FIFOINTENSET &= ~(SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK); - /* Empty FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - - handle->state = kStatus_SPI_Idle; - handle->txRemainingBytes = 0; - handle->rxRemainingBytes = 0; -} - -static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *handle) -{ - uint32_t tx_ctrl = 0, last_ctrl = 0, tmp32; - bool loopContinue; - uint32_t fifoDepth; - /* Get flexcomm instance by 'base' param */ - uint32_t instance = SPI_GetInstance(base); - - /* check params */ - assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData))); - - fifoDepth = SPI_FIFO_DEPTH(base); - /* select slave to talk with */ - tx_ctrl |= (SPI_DEASSERT_ALL & SPI_ASSERTNUM_SSEL(handle->sselNum)); - /* set width of data */ - tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth); - /* delay for frames */ - tx_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; - /* end of transfer */ - last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0; - do - { - loopContinue = false; - - /* rxFIFO is not empty */ - if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) - { - tmp32 = base->FIFORD; - /* rxBuffer is not empty */ - if (handle->rxRemainingBytes) - { - /* low byte must go first */ - *(handle->rxData++) = tmp32; - handle->rxRemainingBytes--; - /* read 16 bits at once */ - if (handle->dataWidth > kSPI_Data8Bits) - { - *(handle->rxData++) = tmp32 >> 8; - handle->rxRemainingBytes--; - } - } - /* decrease number of data expected to receive */ - handle->toReceiveCount -= 1; - loopContinue = true; - } - - /* - txFIFO is not full - * - we cannot cause rxFIFO overflow by sending more data than is the depth of FIFO - * - txBuffer is not empty or the next 'toReceiveCount' data can fit into rxBuffer - */ - if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (handle->toReceiveCount < fifoDepth) && - ((handle->txRemainingBytes) || - (handle->rxRemainingBytes >= SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1)))) - { - /* txBuffer is not empty */ - if (handle->txRemainingBytes) - { - /* low byte must go first */ - tmp32 = *(handle->txData++); - handle->txRemainingBytes--; - /* write 16 bit at once */ - if (handle->dataWidth > kSPI_Data8Bits) - { - tmp32 |= ((uint32_t)(*(handle->txData++))) << 8U; - handle->txRemainingBytes--; - } - /* last transfer */ - if (!handle->txRemainingBytes) - { - tx_ctrl |= last_ctrl; - } - } - else - { - tmp32 = ((uint32_t)s_dummyData[instance] << 8U | (s_dummyData[instance])); - /* last transfer */ - if (handle->rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1)) - { - tx_ctrl |= last_ctrl; - } - } - /* send data */ - tmp32 = tx_ctrl | tmp32; - base->FIFOWR = tmp32; - /* increase number of expected data to receive */ - handle->toReceiveCount += 1; - loopContinue = true; - } - } while (loopContinue); -} - -void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle) -{ - assert((NULL != base) && (NULL != handle)); - - /* IRQ behaviour: - * - first interrupt is triggered by empty txFIFO. The transfer function - * then tries empty rxFIFO and fill txFIFO interleaved that results to - * strategy to process as many items as possible. - * - the next IRQs can be: - * rxIRQ from nonempty rxFIFO which requires to empty rxFIFO. - * txIRQ from empty txFIFO which requires to refill txFIFO. - * - last interrupt is triggered by empty txFIFO. The last state is - * known by empty rxBuffer and txBuffer. If there is nothing to receive - * or send - both operations have been finished and interrupts can be - * disabled. - */ - - /* Data to send or read or expected to receive */ - if ((handle->txRemainingBytes) || (handle->rxRemainingBytes) || (handle->toReceiveCount)) - { - /* Transmit or receive data */ - SPI_TransferHandleIRQInternal(base, handle); - /* No data to send or read or receive. Transfer ends. Set txTrigger to 0 level and - * enable txIRQ to confirm when txFIFO becomes empty */ - if ((!handle->txRemainingBytes) && (!handle->rxRemainingBytes) && (!handle->toReceiveCount)) - { - base->FIFOTRIG = base->FIFOTRIG & (~SPI_FIFOTRIG_TXLVL_MASK); - base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK; - } - else - { - uint32_t rxRemainingCount = SPI_BYTES_TO_COUNT(handle->dataWidth, handle->rxRemainingBytes); - /* If, there are no data to send or rxFIFO is already filled with necessary number of dummy data, - * disable txIRQ. From this point only rxIRQ is used to receive data without any transmission */ - if ((!handle->txRemainingBytes) && (rxRemainingCount <= handle->toReceiveCount)) - { - base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXLVL_MASK; - } - /* Nothing to receive or transmit, but we still have pending data which are bellow rxLevel. - * Cannot clear rxFIFO, txFIFO might be still active */ - if (rxRemainingCount == 0) - { - if ((handle->txRemainingBytes == 0) && (handle->toReceiveCount != 0) && - (handle->toReceiveCount < SPI_FIFOTRIG_RXLVL_GET(base) + 1)) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(handle->toReceiveCount - 1); - } - } - /* Expected to receive less data than rxLevel value, we have to update rxLevel */ - else - { - if (rxRemainingCount < (SPI_FIFOTRIG_RXLVL_GET(base) + 1)) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(rxRemainingCount - 1); - } - } - } - } - else - { - /* Empty txFIFO is confirmed. Disable IRQs and restore triggers values */ - base->FIFOINTENCLR = SPI_FIFOINTENCLR_RXLVL_MASK | SPI_FIFOINTENCLR_TXLVL_MASK; - base->FIFOTRIG = (base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_RXLVL_MASK))) | - SPI_FIFOTRIG_RXLVL(handle->rxWatermark) | SPI_FIFOTRIG_TXLVL(handle->txWatermark); - /* set idle state and call user callback */ - handle->state = kStatus_SPI_Idle; - if (handle->callback) - { - (handle->callback)(base, handle, handle->state, handle->userData); - } - } -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi.h deleted file mode 100644 index 126792d486b..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi.h +++ /dev/null @@ -1,751 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_SPI_H_ -#define _FSL_SPI_H_ - -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/*! - * @addtogroup spi_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SPI driver version 2.0.2. */ -#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -/*! @brief Global variable for dummy data value setting. */ -extern volatile uint8_t s_dummyData[]; - -#ifndef SPI_DUMMYDATA -/*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */ -#define SPI_DUMMYDATA (0xFFU) -#endif - -#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFF) -#define SPI_CTRLMASK (0xFFFF0000) - -#define SPI_ASSERTNUM_SSEL(n) ((~(1U << ((n) + 16))) & 0xF0000) -#define SPI_DEASSERTNUM_SSEL(n) (1U << ((n) + 16)) -#define SPI_DEASSERT_ALL (0xF0000) - -#define SPI_FIFOWR_FLAGS_MASK (~(SPI_DEASSERT_ALL | SPI_FIFOWR_TXDATA_MASK | SPI_FIFOWR_LEN_MASK)) - -#define SPI_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_TXLVL_MASK) >> SPI_FIFOTRIG_TXLVL_SHIFT) -#define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT) - -/*! @brief SPI transfer option.*/ -typedef enum _spi_xfer_option -{ - kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), /*!< A delay may be inserted, defined in the DLY register.*/ - kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< SSEL will be deasserted at the end of a transfer */ -} spi_xfer_option_t; - -/*! @brief SPI data shifter direction options.*/ -typedef enum _spi_shift_direction -{ - kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */ - kSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. */ -} spi_shift_direction_t; - -/*! @brief SPI clock polarity configuration.*/ -typedef enum _spi_clock_polarity -{ - kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */ - kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */ -} spi_clock_polarity_t; - -/*! @brief SPI clock phase configuration.*/ -typedef enum _spi_clock_phase -{ - kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first - * cycle of a data transfer. */ - kSPI_ClockPhaseSecondEdge /*!< First edge on SCK occurs at the start of the - * first cycle of a data transfer. */ -} spi_clock_phase_t; - -/*! @brief txFIFO watermark values */ -typedef enum _spi_txfifo_watermark -{ - kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */ - kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */ - kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */ - kSPI_TxFifo3 = 3, /*!< SPI tx watermark at 3 items */ - kSPI_TxFifo4 = 4, /*!< SPI tx watermark at 4 items */ - kSPI_TxFifo5 = 5, /*!< SPI tx watermark at 5 items */ - kSPI_TxFifo6 = 6, /*!< SPI tx watermark at 6 items */ - kSPI_TxFifo7 = 7, /*!< SPI tx watermark at 7 items */ -} spi_txfifo_watermark_t; - -/*! @brief rxFIFO watermark values */ -typedef enum _spi_rxfifo_watermark -{ - kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */ - kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */ - kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */ - kSPI_RxFifo4 = 3, /*!< SPI rx watermark at 4 items */ - kSPI_RxFifo5 = 4, /*!< SPI rx watermark at 5 items */ - kSPI_RxFifo6 = 5, /*!< SPI rx watermark at 6 items */ - kSPI_RxFifo7 = 6, /*!< SPI rx watermark at 7 items */ - kSPI_RxFifo8 = 7, /*!< SPI rx watermark at 8 items */ -} spi_rxfifo_watermark_t; - -/*! @brief Transfer data width */ -typedef enum _spi_data_width -{ - kSPI_Data4Bits = 3, /*!< 4 bits data width */ - kSPI_Data5Bits = 4, /*!< 5 bits data width */ - kSPI_Data6Bits = 5, /*!< 6 bits data width */ - kSPI_Data7Bits = 6, /*!< 7 bits data width */ - kSPI_Data8Bits = 7, /*!< 8 bits data width */ - kSPI_Data9Bits = 8, /*!< 9 bits data width */ - kSPI_Data10Bits = 9, /*!< 10 bits data width */ - kSPI_Data11Bits = 10, /*!< 11 bits data width */ - kSPI_Data12Bits = 11, /*!< 12 bits data width */ - kSPI_Data13Bits = 12, /*!< 13 bits data width */ - kSPI_Data14Bits = 13, /*!< 14 bits data width */ - kSPI_Data15Bits = 14, /*!< 15 bits data width */ - kSPI_Data16Bits = 15, /*!< 16 bits data width */ -} spi_data_width_t; - -/*! @brief Slave select */ -typedef enum _spi_ssel -{ - kSPI_Ssel0 = 0, /*!< Slave select 0 */ - kSPI_Ssel1 = 1, /*!< Slave select 1 */ - kSPI_Ssel2 = 2, /*!< Slave select 2 */ - kSPI_Ssel3 = 3, /*!< Slave select 3 */ -} spi_ssel_t; - -/*! @brief ssel polarity */ -typedef enum _spi_spol -{ - kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0(1), - kSPI_Spol1ActiveHigh = SPI_CFG_SPOL1(1), - kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2(1), - kSPI_Spol3ActiveHigh = SPI_CFG_SPOL3(1), - kSPI_SpolActiveAllHigh = - (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh | kSPI_Spol3ActiveHigh), - kSPI_SpolActiveAllLow = 0, -} spi_spol_t; - -/*! - * @brief SPI delay time configure structure. - * Note: - * The DLY register controls several programmable delays related to SPI signalling, - * it stands for how many SPI clock time will be inserted. - * The maxinun value of these delay time is 15. - */ -typedef struct _spi_delay_config -{ - uint8_t preDelay; /*!< Delay between SSEL assertion and the beginning of transfer. */ - uint8_t postDelay; /*!< Delay between the end of transfer and SSEL deassertion. */ - uint8_t frameDelay; /*!< Delay between frame to frame. */ - uint8_t transferDelay; /*!< Delay between transfer to transfer. */ -} spi_delay_config_t; - -/*! @brief SPI master user configure structure.*/ -typedef struct _spi_master_config -{ - bool enableLoopback; /*!< Enable loopback for test purpose */ - bool enableMaster; /*!< Enable SPI at initialization time */ - spi_clock_polarity_t polarity; /*!< Clock polarity */ - spi_clock_phase_t phase; /*!< Clock phase */ - spi_shift_direction_t direction; /*!< MSB or LSB */ - uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */ - spi_data_width_t dataWidth; /*!< Width of the data */ - spi_ssel_t sselNum; /*!< Slave select number */ - spi_spol_t sselPol; /*!< Configure active CS polarity */ - spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ - spi_delay_config_t delayConfig; /*!< Delay configuration. */ -} spi_master_config_t; - -/*! @brief SPI slave user configure structure.*/ -typedef struct _spi_slave_config -{ - bool enableSlave; /*!< Enable SPI at initialization time */ - spi_clock_polarity_t polarity; /*!< Clock polarity */ - spi_clock_phase_t phase; /*!< Clock phase */ - spi_shift_direction_t direction; /*!< MSB or LSB */ - spi_data_width_t dataWidth; /*!< Width of the data */ - spi_spol_t sselPol; /*!< Configure active CS polarity */ - spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ -} spi_slave_config_t; - -/*! @brief SPI transfer status.*/ -enum _spi_status -{ - kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0), /*!< SPI bus is busy */ - kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1), /*!< SPI is idle */ - kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI error */ - kStatus_SPI_BaudrateNotSupport = - MAKE_STATUS(kStatusGroup_LPC_SPI, 3) /*!< Baudrate is not support in current clock source */ -}; - -/*! @brief SPI interrupt sources.*/ -enum _spi_interrupt_enable -{ - kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, /*!< Rx level interrupt */ - kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, /*!< Tx level interrupt */ -}; - -/*! @brief SPI status flags.*/ -enum _spi_statusflags -{ - kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK, /*!< txFifo is empty */ - kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK, /*!< txFifo is not full */ - kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, /*!< rxFIFO is not empty */ - kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK, /*!< rxFIFO is full */ -}; - -/*! @brief SPI transfer structure */ -typedef struct _spi_transfer -{ - uint8_t *txData; /*!< Send buffer */ - uint8_t *rxData; /*!< Receive buffer */ - uint32_t configFlags; /*!< Additional option to control transfer, @ref spi_xfer_option_t. */ - size_t dataSize; /*!< Transfer bytes */ -} spi_transfer_t; - -/*! @brief SPI half-duplex(master only) transfer structure */ -typedef struct _spi_half_duplex_transfer -{ - uint8_t *txData; /*!< Send buffer */ - uint8_t *rxData; /*!< Receive buffer */ - size_t txDataSize; /*!< Transfer bytes for transmit */ - size_t rxDataSize; /*!< Transfer bytes */ - uint32_t configFlags; /*!< Transfer configuration flags, @ref spi_xfer_option_t. */ - bool isPcsAssertInTransfer; /*!< If PCS pin keep assert between transmit and receive. true for assert and false for - deassert. */ - bool isTransmitFirst; /*!< True for transmit first and false for receive first. */ -} spi_half_duplex_transfer_t; - -/*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */ -typedef struct _spi_config -{ - spi_data_width_t dataWidth; - spi_ssel_t sselNum; -} spi_config_t; - -/*! @brief Master handle type */ -typedef struct _spi_master_handle spi_master_handle_t; - -/*! @brief Slave handle type */ -typedef spi_master_handle_t spi_slave_handle_t; - -/*! @brief SPI master callback for finished transmit */ -typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI slave callback for finished transmit */ -typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI transfer handle structure */ -struct _spi_master_handle -{ - uint8_t *volatile txData; /*!< Transfer buffer */ - uint8_t *volatile rxData; /*!< Receive buffer */ - volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */ - volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */ - volatile size_t toReceiveCount; /*!< Receive data remaining in bytes */ - size_t totalByteCount; /*!< A number of transfer bytes */ - volatile uint32_t state; /*!< SPI internal state */ - spi_master_callback_t callback; /*!< SPI callback */ - void *userData; /*!< Callback parameter */ - uint8_t dataWidth; /*!< Width of the data [Valid values: 1 to 16] */ - uint8_t sselNum; /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */ - uint32_t configFlags; /*!< Additional option to control transfer */ - spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ -}; - -#if defined(__cplusplus) -extern "C" { -#endif -/******************************************************************************* - * API - ******************************************************************************/ - -/*! @brief Returns instance number for SPI peripheral base address. */ -uint32_t SPI_GetInstance(SPI_Type *base); - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Sets the SPI master configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). - * User may use the initialized structure unchanged in SPI_MasterInit(), or modify - * some fields of the structure before calling SPI_MasterInit(). After calling this API, - * the master is ready to transfer. - * Example: - @code - spi_master_config_t config; - SPI_MasterGetDefaultConfig(&config); - @endcode - * - * @param config pointer to master config structure - */ -void SPI_MasterGetDefaultConfig(spi_master_config_t *config); - -/*! - * @brief Initializes the SPI with master configuration. - * - * The configuration structure can be filled by user from scratch, or be set with default - * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. - * Example - @code - spi_master_config_t config = { - .baudRate_Bps = 400000, - ... - }; - SPI_MasterInit(SPI0, &config); - @endcode - * - * @param base SPI base pointer - * @param config pointer to master configuration structure - * @param srcClock_Hz Source clock frequency. - */ -status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Sets the SPI slave configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). - * Modify some fields of the structure before calling SPI_SlaveInit(). - * Example: - @code - spi_slave_config_t config; - SPI_SlaveGetDefaultConfig(&config); - @endcode - * - * @param config pointer to slave configuration structure - */ -void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config); - -/*! - * @brief Initializes the SPI with slave configuration. - * - * The configuration structure can be filled by user from scratch or be set with - * default values by SPI_SlaveGetDefaultConfig(). - * After calling this API, the slave is ready to transfer. - * Example - @code - spi_slave_config_t config = { - .polarity = flexSPIClockPolarity_ActiveHigh; - .phase = flexSPIClockPhase_FirstEdge; - .direction = flexSPIMsbFirst; - ... - }; - SPI_SlaveInit(SPI0, &config); - @endcode - * - * @param base SPI base pointer - * @param config pointer to slave configuration structure - */ -status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config); - -/*! - * @brief De-initializes the SPI. - * - * Calling this API resets the SPI module, gates the SPI clock. - * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. - * - * @param base SPI base pointer - */ -void SPI_Deinit(SPI_Type *base); - -/*! - * @brief Enable or disable the SPI Master or Slave - * @param base SPI base pointer - * @param enable or disable ( true = enable, false = disable) - */ -static inline void SPI_Enable(SPI_Type *base, bool enable) -{ - if (enable) - { - base->CFG |= SPI_CFG_ENABLE_MASK; - } - else - { - base->CFG &= ~SPI_CFG_ENABLE_MASK; - } -} - -/*! @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the status flag. - * - * @param base SPI base pointer - * @return SPI Status, use status flag to AND @ref _spi_statusflags could get the related status. - */ -static inline uint32_t SPI_GetStatusFlags(SPI_Type *base) -{ - assert(NULL != base); - return base->FIFOSTAT; -} - -/*! @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the interrupt for the SPI. - * - * @param base SPI base pointer - * @param irqs SPI interrupt source. The parameter can be any combination of the following values: - * @arg kSPI_RxLvlIrq - * @arg kSPI_TxLvlIrq - */ -static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs) -{ - assert(NULL != base); - base->FIFOINTENSET = irqs; -} - -/*! - * @brief Disables the interrupt for the SPI. - * - * @param base SPI base pointer - * @param irqs SPI interrupt source. The parameter can be any combination of the following values: - * @arg kSPI_RxLvlIrq - * @arg kSPI_TxLvlIrq - */ -static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs) -{ - assert(NULL != base); - base->FIFOINTENCLR = irqs; -} - -/*! @} */ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Enables the DMA request from SPI txFIFO. - * - * @param base SPI base pointer - * @param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableTxDMA(SPI_Type *base, bool enable); - -/*! - * @brief Enables the DMA request from SPI rxFIFO. - * - * @param base SPI base pointer - * @param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableRxDMA(SPI_Type *base, bool enable); - -/*! @} */ - -/*! - * @name Bus Operations - * @{ - */ -/*! - * @brief Returns the configurations. - * - * @param base SPI peripheral address. - * @return return configurations which contain datawidth and SSEL numbers. - * return data type is a pointer of spi_config_t. - */ -void *SPI_GetConfig(SPI_Type *base); - -/*! - * @brief Sets the baud rate for SPI transfer. This is only used in master. - * - * @param base SPI base pointer - * @param baudrate_Bps baud rate needed in Hz. - * @param srcClock_Hz SPI source clock frequency in Hz. - */ -status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Writes a data into the SPI data register. - * - * @param base SPI base pointer - * @param data needs to be write. - * @param configFlags transfer configuration options @ref spi_xfer_option_t - */ -void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags); - -/*! - * @brief Gets a data from the SPI data register. - * - * @param base SPI base pointer - * @return Data in the register. - */ -static inline uint32_t SPI_ReadData(SPI_Type *base) -{ - assert(NULL != base); - return base->FIFORD; -} - -/*! - * @brief Set delay time for transfer. - * the delay uint is SPI clock time, maximum value is 0xF. - * @param base SPI base pointer - * @param config configuration for delay option @ref spi_delay_config_t. - */ -static inline void SPI_SetTransferDelay(SPI_Type *base, const spi_delay_config_t *config) -{ - assert(NULL != base); - assert(NULL != config); - base->DLY = (SPI_DLY_PRE_DELAY(config->preDelay) | SPI_DLY_POST_DELAY(config->postDelay) | - SPI_DLY_FRAME_DELAY(config->frameDelay) | SPI_DLY_TRANSFER_DELAY(config->transferDelay)); -} - -/*! - * @brief Set up the dummy data. - * - * @param base SPI peripheral address. - * @param dummyData Data to be transferred when tx buffer is NULL. - */ -void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData); - -/*! @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the SPI master handle. - * - * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback Callback function. - * @param userData User data. - */ -status_t SPI_MasterTransferCreateHandle(SPI_Type *base, - spi_master_handle_t *handle, - spi_master_callback_t callback, - void *userData); - -/*! - * @brief Transfers a block of data using a polling method. - * - * @param base SPI base pointer - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - */ -status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer); - -/*! - * @brief Performs a non-blocking SPI interrupt transfer. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer); - -/*! - * @brief Transfers a block of data using a polling method. - * - * This function will do a half-duplex transfer for SPI master, This is a blocking function, - * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, - * users can set transmit first or receive first. - * - * @param base SPI base pointer - * @param xfer pointer to spi_half_duplex_transfer_t structure - * @return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer); - -/*! - * @brief Performs a non-blocking SPI interrupt transfer. - * - * This function using polling way to do the first half transimission and using interrupts to - * do the second half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_half_duplex_transfer_t structure - * @return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, - spi_master_handle_t *handle, - spi_half_duplex_transfer_t *xfer); - -/*! - * @brief Gets the master transfer count. - * - * This function gets the master transfer count. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * @param count The number of bytes transferred by using the non-blocking transaction. - * @return status of status_t. - */ -status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count); - -/*! - * @brief SPI master aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle); - -/*! - * @brief Interrupts the handler for the SPI. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle); - -/*! - * @brief Initializes the SPI slave handle. - * - * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback Callback function. - * @param userData User data. - */ -static inline status_t SPI_SlaveTransferCreateHandle(SPI_Type *base, - spi_slave_handle_t *handle, - spi_slave_callback_t callback, - void *userData) -{ - return SPI_MasterTransferCreateHandle(base, handle, callback, userData); -} - -/*! - * @brief Performs a non-blocking SPI slave interrupt transfer. - * - * @note The API returns immediately after the transfer initialization is finished. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer) -{ - return SPI_MasterTransferNonBlocking(base, handle, xfer); -} - -/*! - * @brief Gets the slave transfer count. - * - * This function gets the slave transfer count. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * @param count The number of bytes transferred by using the non-blocking transaction. - * @return status of status_t. - */ -static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count) -{ - return SPI_MasterTransferGetCount(base, (spi_master_handle_t *)handle, count); -} - -/*! - * @brief SPI slave aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state. - */ -static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle) -{ - SPI_MasterTransferAbort(base, (spi_master_handle_t *)handle); -} - -/*! - * @brief Interrupts a handler for the SPI slave. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_slave_handle_t structure which stores the transfer state - */ -static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle) -{ - SPI_MasterTransferHandleIRQ(base, handle); -} - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_SPI_H_*/ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi_dma.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi_dma.c deleted file mode 100644 index f28c0b070fd..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi_dma.c +++ /dev/null @@ -1,526 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_spi_dma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi_dma" -#endif - -/*configFlags & (uint32_t)kSPI_FrameDelay ? (uint32_t)kSPI_FrameDelay : 0; - *fifowr |= xfer->configFlags & (uint32_t)kSPI_FrameAssert ? (uint32_t)kSPI_FrameAssert : 0; -} - -static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr) -{ - *fifowr |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(config->sselNum))); - /* set width of data - range asserted at entry */ - *fifowr |= SPI_FIFOWR_LEN(config->dataWidth); -} - -static void PrepareTxLastWord(spi_transfer_t *xfer, uint32_t *txLastWord, spi_config_t *config) -{ - if (config->dataWidth > kSPI_Data8Bits) - { - *txLastWord = (((uint32_t)xfer->txData[xfer->dataSize - 1] << 8U) | (xfer->txData[xfer->dataSize - 2])); - } - else - { - *txLastWord = xfer->txData[xfer->dataSize - 1]; - } - XferToFifoWR(xfer, txLastWord); - SpiConfigToFifoWR(config, txLastWord); -} - -static void SPI_SetupDummy(SPI_Type *base, spi_dma_txdummy_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p) -{ - uint32_t instance = SPI_GetInstance(base); - dummy->word = ((uint32_t)s_dummyData[instance] << 8U | s_dummyData[instance]); - dummy->lastWord = ((uint32_t)s_dummyData[instance] << 8U | s_dummyData[instance]); - XferToFifoWR(xfer, &dummy->word); - XferToFifoWR(xfer, &dummy->lastWord); - SpiConfigToFifoWR(spi_config_p, &dummy->word); - SpiConfigToFifoWR(spi_config_p, &dummy->lastWord); - /* Clear the end of transfer bit for continue word transfer. */ - dummy->word &= (uint32_t)(~kSPI_FrameAssert); -} - -status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle) -{ - int32_t instance = 0; - - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } - /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - instance = SPI_GetInstance(base); - - memset(handle, 0, sizeof(*handle)); - /* Set spi base to handle */ - handle->txHandle = txHandle; - handle->rxHandle = rxHandle; - handle->callback = callback; - handle->userData = userData; - - /* Set SPI state to idle */ - handle->state = kSPI_Idle; - - /* Set handle to global state */ - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - /* Install callback for Tx dma channel */ - DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]); - DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]); - - return kStatus_Success; -} - -status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) -{ - int32_t instance; - status_t result = kStatus_Success; - spi_config_t *spi_config_p; - - assert(!((NULL == handle) || (NULL == xfer))); - if ((NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - - /* Byte size is zero. */ - assert(!(xfer->dataSize == 0)); - if (xfer->dataSize == 0) - { - return kStatus_InvalidArgument; - } - /* cannot get instance from base address */ - instance = SPI_GetInstance(base); - assert(!(instance < 0)); - if (instance < 0) - { - return kStatus_InvalidArgument; - } - - /* Check if the device is busy */ - if (handle->state == kSPI_Busy) - { - return kStatus_SPI_Busy; - } - else - { - uint32_t tmp; - dma_transfer_config_t xferConfig = {0}; - spi_config_p = (spi_config_t *)SPI_GetConfig(base); - - handle->state = kStatus_SPI_Busy; - handle->transferSize = xfer->dataSize; - - /* receive */ - SPI_EnableRxDMA(base, true); - if (xfer->rxData) - { - DMA_PrepareTransfer(&xferConfig, ((void *)((uint32_t)&base->FIFORD)), xfer->rxData, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_PeripheralToMemory, NULL); - } - else - { - DMA_PrepareTransfer(&xferConfig, ((void *)((uint32_t)&base->FIFORD)), &s_rxDummy, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_StaticToStatic, NULL); - } - DMA_SubmitTransfer(handle->rxHandle, &xferConfig); - handle->rxInProgress = true; - DMA_StartTransfer(handle->rxHandle); - - /* transmit */ - SPI_EnableTxDMA(base, true); - - if (xfer->configFlags & kSPI_FrameAssert) - { - PrepareTxLastWord(xfer, &s_txLastWord[instance], spi_config_p); - } - - if (xfer->txData) - { - /* If end of tranfer function is enabled and data transfer frame is bigger then 1, use dma - * descriptor to send the last data. - */ - if ((xfer->configFlags & kSPI_FrameAssert) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2) : (xfer->dataSize > 1))) - { - dma_xfercfg_t tmp_xfercfg = {0}; - tmp_xfercfg.valid = true; - tmp_xfercfg.swtrig = true; - tmp_xfercfg.intA = true; - tmp_xfercfg.byteWidth = sizeof(uint32_t); - tmp_xfercfg.srcInc = 0; - tmp_xfercfg.dstInc = 0; - tmp_xfercfg.transferCount = 1; - /* Create chained descriptor to transmit last word */ - DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txLastWord[instance], - ((void *)((uint32_t)&base->FIFOWR)), NULL); - - DMA_PrepareTransfer( - &xferConfig, xfer->txData, ((void *)((uint32_t)&base->FIFOWR)), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)), - kDMA_MemoryToPeripheral, &s_spi_descriptor_table[instance]); - /* Disable interrupts for first descriptor to avoid calling callback twice. */ - xferConfig.xfercfg.intA = false; - xferConfig.xfercfg.intB = false; - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - else - { - DMA_PrepareTransfer( - &xferConfig, xfer->txData, ((void *)((uint32_t)&base->FIFOWR)), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_MemoryToPeripheral, NULL); - DMA_SubmitTransfer(handle->txHandle, &xferConfig); - } - } - else - { - /* Setup tx dummy data. */ - SPI_SetupDummy(base, &s_txDummy[instance], xfer, spi_config_p); - if ((xfer->configFlags & kSPI_FrameAssert) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2) : (xfer->dataSize > 1))) - { - dma_xfercfg_t tmp_xfercfg = {0}; - tmp_xfercfg.valid = true; - tmp_xfercfg.swtrig = true; - tmp_xfercfg.intA = true; - tmp_xfercfg.byteWidth = sizeof(uint32_t); - tmp_xfercfg.srcInc = 0; - tmp_xfercfg.dstInc = 0; - tmp_xfercfg.transferCount = 1; - /* Create chained descriptor to transmit last word */ - DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord, - (void *)((uint32_t)&base->FIFOWR), NULL); - /* Use common API to setup first descriptor */ - DMA_PrepareTransfer( - &xferConfig, &s_txDummy[instance].word, ((void *)((uint32_t)&base->FIFOWR)), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)), - kDMA_StaticToStatic, &s_spi_descriptor_table[instance]); - /* Disable interrupts for first descriptor to avoid calling callback twice */ - xferConfig.xfercfg.intA = false; - xferConfig.xfercfg.intB = false; - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - else - { - DMA_PrepareTransfer( - &xferConfig, &s_txDummy[instance].word, ((void *)((uint32_t)&base->FIFOWR)), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_StaticToStatic, NULL); - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - } - - handle->txInProgress = true; - tmp = 0; - XferToFifoWR(xfer, &tmp); - SpiConfigToFifoWR(spi_config_p, &tmp); - - /* Setup the control info. - * Halfword writes to just the control bits (offset 0xE22) doesn't push anything into the FIFO. - * And the data access type of control bits must be uint16_t, byte writes or halfword writes to FIFOWR - * will push the data and the current control bits into the FIFO. - */ - if ((xfer->configFlags & kSPI_FrameAssert) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize == 2U) : (xfer->dataSize == 1U))) - { - *(((uint16_t *)((uint32_t) & (base->FIFOWR))) + 1) = (uint16_t)(tmp >> 16U); - } - else - { - /* Clear the SPI_FIFOWR_EOT_MASK bit when data is not the last. */ - tmp &= (uint32_t)(~kSPI_FrameAssert); - *(((uint16_t *)((uint32_t) & (base->FIFOWR))) + 1) = (uint16_t)(tmp >> 16U); - } - - DMA_StartTransfer(handle->txHandle); - } - - return result; -} - -status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer) -{ - assert(xfer); - assert(handle); - spi_transfer_t tempXfer = {0}; - status_t status; - - if (xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the pcs pin keep assert between transmit and receive. */ - if (xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); - } - else - { - tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; - } - - status = SPI_MasterTransferBlocking(base, &tempXfer); - if (status != kStatus_Success) - { - return status; - } - - if (xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - status = SPI_MasterTransferDMA(base, handle, &tempXfer); - - return status; -} - -static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) -{ - spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; - spi_dma_handle_t *spiHandle = privHandle->handle; - SPI_Type *base = privHandle->base; - - /* change the state */ - spiHandle->rxInProgress = false; - - /* All finished, call the callback */ - if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) - { - spiHandle->state = kSPI_Idle; - if (spiHandle->callback) - { - (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); - } - } -} - -static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) -{ - spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; - spi_dma_handle_t *spiHandle = privHandle->handle; - SPI_Type *base = privHandle->base; - - /* change the state */ - spiHandle->txInProgress = false; - - /* All finished, call the callback */ - if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) - { - spiHandle->state = kSPI_Idle; - if (spiHandle->callback) - { - (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); - } - } -} - -void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) -{ - assert(NULL != handle); - - /* Stop tx transfer first */ - DMA_AbortTransfer(handle->txHandle); - /* Then rx transfer */ - DMA_AbortTransfer(handle->rxHandle); - - /* Set the handle state */ - handle->txInProgress = false; - handle->rxInProgress = false; - handle->state = kSPI_Idle; -} - -status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != kSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - size_t bytes; - - bytes = DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel); - - *count = handle->transferSize - bytes; - - return kStatus_Success; -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi_dma.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi_dma.h deleted file mode 100644 index 73f016d40ac..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi_dma.h +++ /dev/null @@ -1,234 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_SPI_DMA_H_ -#define _FSL_SPI_DMA_H_ - -#include "fsl_dma.h" -#include "fsl_spi.h" - -/*! - * @addtogroup spi_dma_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SPI DMA driver version 2.0.2. */ -#define FSL_SPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -typedef struct _spi_dma_handle spi_dma_handle_t; - -/*! @brief SPI DMA callback called at the end of transfer. */ -typedef void (*spi_dma_callback_t)(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI DMA transfer handle, users should not touch the content of the handle.*/ -struct _spi_dma_handle -{ - volatile bool txInProgress; /*!< Send transfer finished */ - volatile bool rxInProgress; /*!< Receive transfer finished */ - dma_handle_t *txHandle; /*!< DMA handler for SPI send */ - dma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ - uint8_t bytesPerFrame; /*!< Bytes in a frame for SPI tranfer */ - spi_dma_callback_t callback; /*!< Callback for SPI DMA transfer */ - void *userData; /*!< User Data for SPI DMA callback */ - uint32_t state; /*!< Internal state of SPI DMA transfer */ - size_t transferSize; /*!< Bytes need to be transfer */ -}; - -/******************************************************************************* - * APIs - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name DMA Transactional - * @{ - */ - -/*! - * @brief Initialize the SPI master DMA handle. - * - * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback User callback function called at the end of a transfer. - * @param userData User data for callback. - * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle); - -/*! - * @brief Perform a non-blocking SPI transfer using DMA. - * - * @note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - * @param xfer Pointer to dma transfer structure. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer); - -/*! - * @brief Transfers a block of data using a DMA method. - * - * This function using polling way to do the first half transimission and using DMA way to - * do the srcond half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * @param base SPI base pointer - * @param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. - * @param transfer A pointer to the spi_half_duplex_transfer_t structure. - * @return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer); - -/*! - * @brief Initialize the SPI slave DMA handle. - * - * This function initializes the SPI slave DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback User callback function called at the end of a transfer. - * @param userData User data for callback. - * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -static inline status_t SPI_SlaveTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle) -{ - return SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle); -} - -/*! - * @brief Perform a non-blocking SPI transfer using DMA. - * - * @note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - * @param xfer Pointer to dma transfer structure. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -static inline status_t SPI_SlaveTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) -{ - return SPI_MasterTransferDMA(base, handle, xfer); -} - -/*! - * @brief Abort a SPI transfer using DMA. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - */ -void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle); - -/*! - * @brief Gets the master DMA transfer remaining bytes. - * - * This function gets the master DMA transfer remaining bytes. - * - * @param base SPI peripheral base address. - * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * @param count A number of bytes transferred by the non-blocking transaction. - * @return status of status_t. - */ -status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count); - -/*! - * @brief Abort a SPI transfer using DMA. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - */ -static inline void SPI_SlaveTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) -{ - SPI_MasterTransferAbortDMA(base, handle); -} - -/*! - * @brief Gets the slave DMA transfer remaining bytes. - * - * This function gets the slave DMA transfer remaining bytes. - * - * @param base SPI peripheral base address. - * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * @param count A number of bytes transferred by the non-blocking transaction. - * @return status of status_t. - */ -static inline status_t SPI_SlaveTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) -{ - return SPI_MasterTransferGetCountDMA(base, handle, count); -} - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_SPI_DMA_H_*/ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart.c deleted file mode 100644 index 1117fac7786..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart.c +++ /dev/null @@ -1,718 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_usart.h" -#include "fsl_device_registers.h" -#include "fsl_flexcomm.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart" -#endif - - -enum _usart_transfer_states -{ - kUSART_TxIdle, /* TX idle. */ - kUSART_TxBusy, /* TX busy. */ - kUSART_RxIdle, /* RX idle. */ - kUSART_RxBusy /* RX busy. */ -}; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief IRQ name array */ -static const IRQn_Type s_usartIRQ[] = USART_IRQS; - -/*! @brief Array to map USART instance number to base address. */ -static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Get the index corresponding to the USART */ -uint32_t USART_GetInstance(USART_Type *base) -{ - int i; - - for (i = 0; i < FSL_FEATURE_SOC_USART_COUNT; i++) - { - if ((uint32_t)base == s_usartBaseAddrs[i]) - { - return i; - } - } - - assert(false); - return 0; -} - -size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) -{ - size_t size; - - /* Check arguments */ - assert(NULL != handle); - - if (handle->rxRingBufferTail > handle->rxRingBufferHead) - { - size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); - } - else - { - size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); - } - return size; -} - -static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle) -{ - bool full; - - /* Check arguments */ - assert(NULL != handle); - - if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) - { - full = true; - } - else - { - full = false; - } - return full; -} - -void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) -{ - /* Check arguments */ - assert(NULL != base); - assert(NULL != handle); - assert(NULL != ringBuffer); - - /* Setup the ringbuffer address */ - handle->rxRingBuffer = ringBuffer; - handle->rxRingBufferSize = ringBufferSize; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; - /* ring buffer is ready we can start receiving data */ - base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -} - -void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) -{ - /* Check arguments */ - assert(NULL != base); - assert(NULL != handle); - - if (handle->rxState == kUSART_RxIdle) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK; - } - handle->rxRingBuffer = NULL; - handle->rxRingBufferSize = 0U; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; -} - -status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz) -{ - int result; - - /* check arguments */ - assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz))); - if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* initialize flexcomm to USART mode */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART); - if (kStatus_Success != result) - { - return result; - } - - /* setup baudrate */ - result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - - if (config->enableTx) - { - /* empty and enable txFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK; - /* setup trigger level */ - base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK); - base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark); - /* enable trigger interrupt */ - base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK; - } - - /* empty and enable rxFIFO */ - if (config->enableRx) - { - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK; - /* setup trigger level */ - base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK); - base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable trigger interrupt */ - base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK; - } - /* setup configuration and enable USART */ - base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | - USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | USART_CFG_ENABLE_MASK; - return kStatus_Success; -} - -void USART_Deinit(USART_Type *base) -{ - /* Check arguments */ - assert(NULL != base); - while (!(base->STAT & USART_STAT_TXIDLE_MASK)) - { - } - /* Disable interrupts, disable dma requests, disable peripheral */ - base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK | - USART_FIFOINTENCLR_RXLVL_MASK; - base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK); - base->CFG &= ~(USART_CFG_ENABLE_MASK); -} - -void USART_GetDefaultConfig(usart_config_t *config) -{ - /* Check arguments */ - assert(NULL != config); - - /* Set always all members ! */ - config->baudRate_Bps = 115200U; - config->parityMode = kUSART_ParityDisabled; - config->stopBitCount = kUSART_OneStopBit; - config->bitCountPerChar = kUSART_8BitsPerChar; - config->loopback = false; - config->enableRx = false; - config->enableTx = false; - config->txWatermark = kUSART_TxFifo0; - config->rxWatermark = kUSART_RxFifo1; -} - -status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) -{ - uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1; - uint32_t osrval, brgval, diff, baudrate; - - /* check arguments */ - assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))); - if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* - * Smaller values of OSR can make the sampling position within a data bit less accurate and may - * potentially cause more noise errors or incorrect data. - */ - for (osrval = best_osrval; osrval >= 8; osrval--) - { - brgval = (srcClock_Hz / ((osrval + 1) * baudrate_Bps)) - 1; - if (brgval > 0xFFFF) - { - continue; - } - baudrate = srcClock_Hz / ((osrval + 1) * (brgval + 1)); - diff = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate; - if (diff < best_diff) - { - best_diff = diff; - best_osrval = osrval; - best_brgval = brgval; - } - } - - /* value over range */ - if (best_brgval > 0xFFFF) - { - return kStatus_USART_BaudrateNotSupport; - } - - base->OSR = best_osrval; - base->BRG = best_brgval; - return kStatus_Success; -} - -void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) -{ - /* Check arguments */ - assert(!((NULL == base) || (NULL == data))); - if ((NULL == base) || (NULL == data)) - { - return; - } - /* Check whether txFIFO is enabled */ - if (!(base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK)) - { - return; - } - for (; length > 0; length--) - { - /* Loop until txFIFO get some space for new data */ - while (!(base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) - { - } - base->FIFOWR = *data; - data++; - } - /* Wait to finish transfer */ - while (!(base->STAT & USART_STAT_TXIDLE_MASK)) - { - } -} - -status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) -{ - uint32_t status; - - /* check arguments */ - assert(!((NULL == base) || (NULL == data))); - if ((NULL == base) || (NULL == data)) - { - return kStatus_InvalidArgument; - } - - /* Check whether rxFIFO is enabled */ - if (!(base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK)) - { - return kStatus_Fail; - } - for (; length > 0; length--) - { - /* loop until rxFIFO have some data to read */ - while (!(base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) - { - } - /* check receive status */ - status = base->STAT; - if (status & USART_STAT_FRAMERRINT_MASK) - { - base->STAT |= USART_STAT_FRAMERRINT_MASK; - return kStatus_USART_FramingError; - } - if (status & USART_STAT_PARITYERRINT_MASK) - { - base->STAT |= USART_STAT_PARITYERRINT_MASK; - return kStatus_USART_ParityError; - } - if (status & USART_STAT_RXNOISEINT_MASK) - { - base->STAT |= USART_STAT_RXNOISEINT_MASK; - return kStatus_USART_NoiseError; - } - /* check rxFIFO status */ - if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) - { - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; - return kStatus_USART_RxError; - } - - *data = base->FIFORD; - data++; - } - return kStatus_Success; -} - -status_t USART_TransferCreateHandle(USART_Type *base, - usart_handle_t *handle, - usart_transfer_callback_t callback, - void *userData) -{ - int32_t instance = 0; - - /* Check 'base' */ - assert(!((NULL == base) || (NULL == handle))); - if ((NULL == base) || (NULL == handle)) - { - return kStatus_InvalidArgument; - } - - instance = USART_GetInstance(base); - - memset(handle, 0, sizeof(*handle)); - /* Set the TX/RX state. */ - handle->rxState = kUSART_RxIdle; - handle->txState = kUSART_TxIdle; - /* Set the callback and user data. */ - handle->callback = callback; - handle->userData = userData; - handle->rxWatermark = (usart_rxfifo_watermark_t)USART_FIFOTRIG_RXLVL_GET(base); - handle->txWatermark = (usart_txfifo_watermark_t)USART_FIFOTRIG_TXLVL_GET(base); - - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)USART_TransferHandleIRQ, handle); - - /* Enable interrupt in NVIC. */ - EnableIRQ(s_usartIRQ[instance]); - - return kStatus_Success; -} - -status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer) -{ - /* Check arguments */ - assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - /* Check xfer members */ - assert(!((0 == xfer->dataSize) || (NULL == xfer->data))); - if ((0 == xfer->dataSize) || (NULL == xfer->data)) - { - return kStatus_InvalidArgument; - } - - /* Return error if current TX busy. */ - if (kUSART_TxBusy == handle->txState) - { - return kStatus_USART_TxBusy; - } - else - { - handle->txData = xfer->data; - handle->txDataSize = xfer->dataSize; - handle->txDataSizeAll = xfer->dataSize; - handle->txState = kUSART_TxBusy; - /* Enable transmiter interrupt. */ - base->FIFOINTENSET |= USART_FIFOINTENSET_TXLVL_MASK; - } - return kStatus_Success; -} - -void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) -{ - assert(NULL != handle); - - /* Disable interrupts */ - base->FIFOINTENSET &= ~USART_FIFOINTENSET_TXLVL_MASK; - /* Empty txFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK; - - handle->txDataSize = 0; - handle->txState = kUSART_TxIdle; -} - -status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != count); - - if (kUSART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - handle->txDataSize; - - return kStatus_Success; -} - -status_t USART_TransferReceiveNonBlocking(USART_Type *base, - usart_handle_t *handle, - usart_transfer_t *xfer, - size_t *receivedBytes) -{ - uint32_t i; - /* How many bytes to copy from ring buffer to user memory. */ - size_t bytesToCopy = 0U; - /* How many bytes to receive. */ - size_t bytesToReceive; - /* How many bytes currently have received. */ - size_t bytesCurrentReceived; - uint32_t regPrimask = 0U; - - /* Check arguments */ - assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - /* Check xfer members */ - assert(!((0 == xfer->dataSize) || (NULL == xfer->data))); - if ((0 == xfer->dataSize) || (NULL == xfer->data)) - { - return kStatus_InvalidArgument; - } - - /* How to get data: - 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize - to uart handle, enable interrupt to store received data to xfer->data. When - all data received, trigger callback. - 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. - If there are enough data in ring buffer, copy them to xfer->data and return. - If there are not enough data in ring buffer, copy all of them to xfer->data, - save the xfer->data remained empty space to uart handle, receive data - to this empty space and trigger callback when finished. */ - if (kUSART_RxBusy == handle->rxState) - { - return kStatus_USART_RxBusy; - } - else - { - bytesToReceive = xfer->dataSize; - bytesCurrentReceived = 0U; - /* If RX ring buffer is used. */ - if (handle->rxRingBuffer) - { - /* Disable IRQ, protect ring buffer. */ - regPrimask = DisableGlobalIRQ(); - /* How many bytes in RX ring buffer currently. */ - bytesToCopy = USART_TransferGetRxRingBufferLength(handle); - if (bytesToCopy) - { - bytesToCopy = MIN(bytesToReceive, bytesToCopy); - bytesToReceive -= bytesToCopy; - /* Copy data from ring buffer to user memory. */ - for (i = 0U; i < bytesToCopy; i++) - { - xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; - /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - } - /* If ring buffer does not have enough data, still need to read more data. */ - if (bytesToReceive) - { - /* No data in ring buffer, save the request to UART handle. */ - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kUSART_RxBusy; - } - /* Enable IRQ if previously enabled. */ - EnableGlobalIRQ(regPrimask); - /* Call user callback since all data are received. */ - if (0 == bytesToReceive) - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); - } - } - } - /* Ring buffer not used. */ - else - { - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kUSART_RxBusy; - - /* Enable RX interrupt. */ - base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK; - } - /* Return the how many bytes have read. */ - if (receivedBytes) - { - *receivedBytes = bytesCurrentReceived; - } - } - return kStatus_Success; -} - -void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) -{ - assert(NULL != handle); - - /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ - if (!handle->rxRingBuffer) - { - /* Disable interrupts */ - base->FIFOINTENSET &= ~USART_FIFOINTENSET_RXLVL_MASK; - /* Empty rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - } - - handle->rxDataSize = 0U; - handle->rxState = kUSART_RxIdle; -} - -status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != count); - - if (kUSART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - handle->rxDataSize; - - return kStatus_Success; -} - -void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) -{ - /* Check arguments */ - assert((NULL != base) && (NULL != handle)); - - bool receiveEnabled = (handle->rxDataSize) || (handle->rxRingBuffer); - bool sendEnabled = handle->txDataSize; - - /* If RX overrun. */ - if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) - { - /* Clear rx error state. */ - base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback) - { - handle->callback(base, handle, kStatus_USART_RxError, handle->userData); - } - } - while ((receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) || - (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))) - { - /* Receive data */ - if (receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) - { - /* Receive to app bufffer if app buffer is present */ - if (handle->rxDataSize) - { - *handle->rxData = base->FIFORD; - handle->rxDataSize--; - handle->rxData++; - receiveEnabled = ((handle->rxDataSize != 0) || (handle->rxRingBuffer)); - if (!handle->rxDataSize) - { - if (!handle->rxRingBuffer) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; - } - handle->rxState = kUSART_RxIdle; - if (handle->callback) - { - handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); - } - } - } - /* Otherwise receive to ring buffer if ring buffer is present */ - else - { - if (handle->rxRingBuffer) - { - /* If RX ring buffer is full, trigger callback to notify over run. */ - if (USART_TransferIsRxRingBufferFull(handle)) - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData); - } - } - /* If ring buffer is still full after callback function, the oldest data is overrided. */ - if (USART_TransferIsRxRingBufferFull(handle)) - { - /* Increase handle->rxRingBufferTail to make room for new data. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - /* Read data. */ - handle->rxRingBuffer[handle->rxRingBufferHead] = base->FIFORD; - /* Increase handle->rxRingBufferHead. */ - if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferHead = 0U; - } - else - { - handle->rxRingBufferHead++; - } - } - } - } - /* Send data */ - if (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) - { - base->FIFOWR = *handle->txData; - handle->txDataSize--; - handle->txData++; - sendEnabled = handle->txDataSize != 0; - if (!sendEnabled) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK; - handle->txState = kUSART_TxIdle; - if (handle->callback) - { - handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); - } - } - } - } - - /* ring buffer is not used */ - if (NULL == handle->rxRingBuffer) - { - /* restore if rx transfer ends and rxLevel is different from default value */ - if ((handle->rxDataSize == 0) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark)) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark); - } - /* decrease level if rx transfer is bellow */ - if ((handle->rxDataSize != 0) && (handle->rxDataSize < (USART_FIFOTRIG_RXLVL_GET(base) + 1))) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(handle->rxDataSize - 1)); - } - } -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart.h deleted file mode 100644 index 9deb377f147..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart.h +++ /dev/null @@ -1,667 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_USART_H_ -#define _FSL_USART_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup usart_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief USART driver version 2.0.1. */ -#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT) -#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT) - -/*! @brief Error codes for the USART driver. */ -enum _usart_status -{ - kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */ - kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */ - kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */ - kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */ - kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */ - kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */ - kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */ - kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */ - kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */ - kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */ - kStatus_USART_BaudrateNotSupport = - MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */ -}; - -/*! @brief USART parity mode. */ -typedef enum _usart_parity_mode -{ - kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */ - kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ - kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ -} usart_parity_mode_t; - -/*! @brief USART stop bit count. */ -typedef enum _usart_stop_bit_count -{ - kUSART_OneStopBit = 0U, /*!< One stop bit */ - kUSART_TwoStopBit = 1U, /*!< Two stop bits */ -} usart_stop_bit_count_t; - -/*! @brief USART data size. */ -typedef enum _usart_data_len -{ - kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */ - kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */ -} usart_data_len_t; - -/*! @brief txFIFO watermark values */ -typedef enum _usart_txfifo_watermark -{ - kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */ - kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */ - kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */ - kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */ - kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */ - kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */ - kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */ - kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */ -} usart_txfifo_watermark_t; - -/*! @brief rxFIFO watermark values */ -typedef enum _usart_rxfifo_watermark -{ - kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */ - kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */ - kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */ - kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */ - kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */ - kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */ - kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */ - kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */ -} usart_rxfifo_watermark_t; - -/*! - * @brief USART interrupt configuration structure, default settings all disabled. - */ -enum _usart_interrupt_enable -{ - kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK), - kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK), - kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK), - kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK), -}; - -/*! - * @brief USART status flags. - * - * This provides constants for the USART status flags for use in the USART functions. - */ -enum _usart_flags -{ - kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */ - kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */ - kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */ - kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */ - kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */ - kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */ -}; - -/*! @brief USART configuration structure. */ -typedef struct _usart_config -{ - uint32_t baudRate_Bps; /*!< USART baud rate */ - usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ - usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ - usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */ - bool loopback; /*!< Enable peripheral loopback */ - bool enableRx; /*!< Enable RX */ - bool enableTx; /*!< Enable TX */ - usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ -} usart_config_t; - -/*! @brief USART transfer structure. */ -typedef struct _usart_transfer -{ - uint8_t *data; /*!< The buffer of data to be transfer.*/ - size_t dataSize; /*!< The byte count to be transfer. */ -} usart_transfer_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _usart_handle usart_handle_t; - -/*! @brief USART transfer callback function. */ -typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData); - -/*! @brief USART handle structure. */ -struct _usart_handle -{ - uint8_t *volatile txData; /*!< Address of remaining data to send. */ - volatile size_t txDataSize; /*!< Size of the remaining data to send. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ - volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - - uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ - size_t rxRingBufferSize; /*!< Size of the ring buffer. */ - volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ - volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ - - usart_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< USART callback function parameter.*/ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ - - usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! @brief Returns instance number for USART peripheral base address. */ -uint32_t USART_GetInstance(USART_Type *base); - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes a USART instance with user configuration structure and peripheral clock. - * - * This function configures the USART module with the user-defined settings. The user can configure the configuration - * structure and also get the default configuration by using the USART_GetDefaultConfig() function. - * Example below shows how to use this API to configure USART. - * @code - * usart_config_t usartConfig; - * usartConfig.baudRate_Bps = 115200U; - * usartConfig.parityMode = kUSART_ParityDisabled; - * usartConfig.stopBitCount = kUSART_OneStopBit; - * USART_Init(USART1, &usartConfig, 20000000U); - * @endcode - * - * @param base USART peripheral base address. - * @param config Pointer to user-defined configuration structure. - * @param srcClock_Hz USART clock source frequency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_InvalidArgument USART base address is not valid - * @retval kStatus_Success Status USART initialize succeed - */ -status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes a USART instance. - * - * This function waits for TX complete, disables TX and RX, and disables the USART clock. - * - * @param base USART peripheral base address. - */ -void USART_Deinit(USART_Type *base); - -/*! - * @brief Gets the default configuration structure. - * - * This function initializes the USART configuration structure to a default value. The default - * values are: - * usartConfig->baudRate_Bps = 115200U; - * usartConfig->parityMode = kUSART_ParityDisabled; - * usartConfig->stopBitCount = kUSART_OneStopBit; - * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; - * usartConfig->loopback = false; - * usartConfig->enableTx = false; - * usartConfig->enableRx = false; - * - * @param config Pointer to configuration structure. - */ -void USART_GetDefaultConfig(usart_config_t *config); - -/*! - * @brief Sets the USART instance baud rate. - * - * This function configures the USART module baud rate. This function is used to update - * the USART module baud rate after the USART module is initialized by the USART_Init. - * @code - * USART_SetBaudRate(USART1, 115200U, 20000000U); - * @endcode - * - * @param base USART peripheral base address. - * @param baudrate_Bps USART baudrate to be set. - * @param srcClock_Hz USART clock source freqency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_Success Set baudrate succeed. - * @retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Get USART status flags. - * - * This function get all USART status flags, the flags are returned as the logical - * OR value of the enumerators @ref _usart_flags. To check a specific status, - * compare the return value with enumerators in @ref _usart_flags. - * For example, to check whether the TX is empty: - * @code - * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1)) - * { - * ... - * } - * @endcode - * - * @param base USART peripheral base address. - * @return USART status flags which are ORed by the enumerators in the _usart_flags. - */ -static inline uint32_t USART_GetStatusFlags(USART_Type *base) -{ - return base->FIFOSTAT; -} - -/*! - * @brief Clear USART status flags. - * - * This function clear supported USART status flags - * Flags that can be cleared or set are: - * kUSART_TxError - * kUSART_RxError - * For example: - * @code - * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError) - * @endcode - * - * @param base USART peripheral base address. - * @param mask status flags to be cleared. - */ -static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask) -{ - /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */ - base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK); -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables USART interrupts according to the provided mask. - * - * This function enables the USART interrupts according to the provided mask. The mask - * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. - * For example, to enable TX empty interrupt and RX full interrupt: - * @code - * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); - * @endcode - * - * @param base USART peripheral base address. - * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable. - */ -static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) -{ - base->FIFOINTENSET = mask & 0xF; -} - -/*! - * @brief Disables USART interrupts according to a provided mask. - * - * This function disables the USART interrupts according to a provided mask. The mask - * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. - * This example shows how to disable the TX empty interrupt and RX full interrupt: - * @code - * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); - * @endcode - * - * @param base USART peripheral base address. - * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable. - */ -static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) -{ - base->FIFOINTENCLR = mask & 0xF; -} - -/*! - * @brief Returns enabled USART interrupts. - * - * This function returns the enabled USART interrupts. - * - * @param base USART peripheral base address. - */ -static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base) -{ - return base->FIFOINTENSET; -} - -/*! -* @brief Enable DMA for Tx -*/ -static inline void USART_EnableTxDMA(USART_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK); - } -} - -/*! -* @brief Enable DMA for Rx -*/ -static inline void USART_EnableRxDMA(USART_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK); - } -} - -/* @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Writes to the FIFOWR register. - * - * This function writes data to the txFIFO directly. The upper layer must ensure - * that txFIFO has space for data to write before calling this function. - * - * @param base USART peripheral base address. - * @param data The byte to write. - */ -static inline void USART_WriteByte(USART_Type *base, uint8_t data) -{ - base->FIFOWR = data; -} - -/*! - * @brief Reads the FIFORD register directly. - * - * This function reads data from the rxFIFO directly. The upper layer must - * ensure that the rxFIFO is not empty before calling this function. - * - * @param base USART peripheral base address. - * @return The byte read from USART data register. - */ -static inline uint8_t USART_ReadByte(USART_Type *base) -{ - return base->FIFORD; -} - -/*! - * @brief Writes to the TX register using a blocking method. - * - * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO - * to have room and writes data to the TX buffer. - * - * @param base USART peripheral base address. - * @param data Start address of the data to write. - * @param length Size of the data to write. - */ -void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length); - -/*! - * @brief Read RX data register using a blocking method. - * - * This function polls the RX register, waits for the RX register to be full or for RX FIFO to - * have data and read data from the TX register. - * - * @param base USART peripheral base address. - * @param data Start address of the buffer to store the received data. - * @param length Size of the buffer. - * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data. - * @retval kStatus_USART_ParityError Noise error happened while receiving data. - * @retval kStatus_USART_NoiseError Framing error happened while receiving data. - * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. - * @retval kStatus_Success Successfully received all data. - */ -status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the USART handle. - * - * This function initializes the USART handle which can be used for other USART - * transactional APIs. Usually, for a specified USART instance, - * call this API once to get the initialized handle. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param callback The callback function. - * @param userData The parameter of the callback function. - */ -status_t USART_TransferCreateHandle(USART_Type *base, - usart_handle_t *handle, - usart_transfer_callback_t callback, - void *userData); - -/*! - * @brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in the IRQ handler, the USART driver calls the callback - * function and passes the @ref kStatus_USART_TxIdle as status parameter. - * - * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written - * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, - * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART transfer structure. See #usart_transfer_t. - * @retval kStatus_Success Successfully start the data transmission. - * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific USART handle. - * - * When the RX ring buffer is used, data received are stored into the ring buffer even when the - * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * - * @note When using the RX ring buffer, one byte is reserved for internal use. In other - * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. - * @param ringBufferSize size of the ring buffer. - */ -void USART_TransferStartRingBuffer(USART_Type *base, - usart_handle_t *handle, - uint8_t *ringBuffer, - size_t ringBufferSize); - -/*! - * @brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the length of received data in RX ring buffer. - * - * @param handle USART handle pointer. - * @return Length of received data in RX ring buffer. - */ -size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle); - -/*! - * @brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out - * how many bytes are still not sent out. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been written to USART TX register. - * - * This function gets the number of bytes that have been written to USART TX - * register by interrupt method. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Send bytes count. - * @retval kStatus_NoTransferInProgress No send in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); - -/*! - * @brief Receives a buffer of data using an interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function, which - * returns without waiting for all data to be received. - * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and - * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in the ring buffer is not enough to read, the receive - * request is saved by the USART driver. When the new data arrives, the receive request - * is serviced first. When all data is received, the USART driver notifies the upper layer - * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle. - * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. - * The 5 bytes are copied to the xfer->data and this function returns with the - * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is - * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to the xfer->data. When all data is received, the upper layer is notified. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART transfer structure, see #usart_transfer_t. - * @param receivedBytes Bytes received from the ring buffer directly. - * @retval kStatus_Success Successfully queue the transfer into transmit queue. - * @retval kStatus_USART_RxBusy Previous receive request is not finished. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveNonBlocking(USART_Type *base, - usart_handle_t *handle, - usart_transfer_t *xfer, - size_t *receivedBytes); - -/*! - * @brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out - * how many bytes not received yet. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); - -/*! - * @brief USART IRQ handle function. - * - * This function handles the USART transmit and receive IRQ request. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_USART_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart_dma.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart_dma.c deleted file mode 100644 index 6f900e3aca4..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart_dma.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_usart.h" -#include "fsl_device_registers.h" -#include "fsl_dma.h" -#include "fsl_flexcomm.h" -#include "fsl_usart_dma.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_dma" -#endif - -/*base, false); - - usartPrivateHandle->handle->txState = kUSART_TxIdle; - - if (usartPrivateHandle->handle->callback) - { - usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_TxIdle, - usartPrivateHandle->handle->userData); - } -} - -static void USART_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode) -{ - assert(handle); - assert(param); - - usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param; - - /* Disable UART RX DMA. */ - USART_EnableRxDMA(usartPrivateHandle->base, false); - - usartPrivateHandle->handle->rxState = kUSART_RxIdle; - - if (usartPrivateHandle->handle->callback) - { - usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_RxIdle, - usartPrivateHandle->handle->userData); - } -} - -status_t USART_TransferCreateHandleDMA(USART_Type *base, - usart_dma_handle_t *handle, - usart_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *txDmaHandle, - dma_handle_t *rxDmaHandle) -{ - int32_t instance = 0; - - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } - /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - instance = USART_GetInstance(base); - - memset(handle, 0, sizeof(*handle)); - /* assign 'base' and 'handle' */ - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - /* set tx/rx 'idle' state */ - handle->rxState = kUSART_RxIdle; - handle->txState = kUSART_TxIdle; - - handle->callback = callback; - handle->userData = userData; - - handle->rxDmaHandle = rxDmaHandle; - handle->txDmaHandle = txDmaHandle; - - /* Configure TX. */ - if (txDmaHandle) - { - DMA_SetCallback(txDmaHandle, USART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]); - } - - /* Configure RX. */ - if (rxDmaHandle) - { - DMA_SetCallback(rxDmaHandle, USART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]); - } - - return kStatus_Success; -} - -status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) -{ - assert(handle); - assert(handle->txDmaHandle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - dma_transfer_config_t xferConfig; - status_t status; - - /* If previous TX not finished. */ - if (kUSART_TxBusy == handle->txState) - { - status = kStatus_USART_TxBusy; - } - else - { - handle->txState = kUSART_TxBusy; - handle->txDataSizeAll = xfer->dataSize; - - /* Enable DMA request from txFIFO */ - USART_EnableTxDMA(base, true); - - /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, xfer->data, ((void *)((uint32_t)&base->FIFOWR)), sizeof(uint8_t), - xfer->dataSize, kDMA_MemoryToPeripheral, NULL); - - /* Submit transfer. */ - DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); - DMA_StartTransfer(handle->txDmaHandle); - - status = kStatus_Success; - } - - return status; -} - -status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) -{ - assert(handle); - assert(handle->rxDmaHandle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - dma_transfer_config_t xferConfig; - status_t status; - - /* If previous RX not finished. */ - if (kUSART_RxBusy == handle->rxState) - { - status = kStatus_USART_RxBusy; - } - else - { - handle->rxState = kUSART_RxBusy; - handle->rxDataSizeAll = xfer->dataSize; - - /* Enable DMA request from rxFIFO */ - USART_EnableRxDMA(base, true); - - /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, ((void *)((uint32_t)&base->FIFORD)), xfer->data, sizeof(uint8_t), - xfer->dataSize, kDMA_PeripheralToMemory, NULL); - - /* Submit transfer. */ - DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); - DMA_StartTransfer(handle->rxDmaHandle); - - status = kStatus_Success; - } - - return status; -} - -void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle) -{ - assert(NULL != handle); - assert(NULL != handle->txDmaHandle); - - /* Stop transfer. */ - DMA_AbortTransfer(handle->txDmaHandle); - handle->txState = kUSART_TxIdle; -} - -void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle) -{ - assert(NULL != handle); - assert(NULL != handle->rxDmaHandle); - - /* Stop transfer. */ - DMA_AbortTransfer(handle->rxDmaHandle); - handle->rxState = kUSART_RxIdle; -} - -status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) -{ - assert(handle); - assert(handle->rxDmaHandle); - assert(count); - - if (kUSART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); - - return kStatus_Success; -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart_dma.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart_dma.h deleted file mode 100644 index 029f815dd48..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart_dma.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_USART_DMA_H_ -#define _FSL_USART_DMA_H_ - -#include "fsl_common.h" -#include "fsl_dma.h" -#include "fsl_usart.h" - -/*! - * @addtogroup usart_dma_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief USART dma driver version 2.0.1. */ -#define FSL_USART_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/* Forward declaration of the handle typedef. */ -typedef struct _usart_dma_handle usart_dma_handle_t; - -/*! @brief UART transfer callback function. */ -typedef void (*usart_dma_transfer_callback_t)(USART_Type *base, - usart_dma_handle_t *handle, - status_t status, - void *userData); - -/*! -* @brief UART DMA handle -*/ -struct _usart_dma_handle -{ - USART_Type *base; /*!< UART peripheral base address. */ - - usart_dma_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< UART callback function parameter.*/ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - - dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */ - dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name DMA transactional - * @{ - */ - -/*! - * @brief Initializes the USART handle which is used in transactional functions. - * @param base USART peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param callback Callback function. - * @param userData User data. - * @param txDmaHandle User-requested DMA handle for TX DMA transfer. - * @param rxDmaHandle User-requested DMA handle for RX DMA transfer. - */ -status_t USART_TransferCreateHandleDMA(USART_Type *base, - usart_dma_handle_t *handle, - usart_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *txDmaHandle, - dma_handle_t *rxDmaHandle); - -/*! - * @brief Sends data using DMA. - * - * This function sends data using DMA. This is a non-blocking function, which returns - * right away. When all data is sent, the send callback function is called. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART DMA transfer structure. See #usart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_USART_TxBusy Previous transfer on going. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Receives data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * @param base USART peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param xfer USART DMA transfer structure. See #usart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_USART_RxBusy Previous transfer on going. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Aborts the sent data using DMA. - * - * This function aborts send data using DMA. - * - * @param base USART peripheral base address - * @param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle); - -/*! - * @brief Aborts the received data using DMA. - * - * This function aborts the received data using DMA. - * - * @param base USART peripheral base address - * @param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_USART_DMA_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_utick.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_utick.c deleted file mode 100644 index 5c14d2ebf33..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_utick.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_utick.h" -#include "fsl_power.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.utick" -#endif - - -/* Typedef for interrupt handler. */ -typedef void (*utick_isr_t)(UTICK_Type *base, utick_callback_t cb); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base UTICK peripheral base address - * - * @return The UTICK instance - */ -static uint32_t UTICK_GetInstance(UTICK_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of UTICK handle. */ -static utick_callback_t s_utickHandle[FSL_FEATURE_SOC_UTICK_COUNT]; -/* Array of UTICK peripheral base address. */ -static UTICK_Type *const s_utickBases[] = UTICK_BASE_PTRS; -/* Array of UTICK IRQ number. */ -static const IRQn_Type s_utickIRQ[] = UTICK_IRQS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of UTICK clock name. */ -static const clock_ip_name_t s_utickClock[] = UTICK_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -/* UTICK ISR for transactional APIs. */ -static utick_isr_t s_utickIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t UTICK_GetInstance(UTICK_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_utickBases); instance++) - { - if (s_utickBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_utickBases)); - - return instance; -} - -void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb) -{ - uint32_t instance; - - /* Get instance from peripheral base address. */ - instance = UTICK_GetInstance(base); - - /* Save the handle in global variables to support the double weak mechanism. */ - s_utickHandle[instance] = cb; - EnableDeepSleepIRQ(s_utickIRQ[instance]); - base->CTRL = count | UTICK_CTRL_REPEAT(mode); -} - -void UTICK_Init(UTICK_Type *base) -{ - /* Enable utick clock */ - CLOCK_EnableClock(s_utickClock[UTICK_GetInstance(base)]); - /* Power up Watchdog oscillator*/ - POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC); - s_utickIsr = UTICK_HandleIRQ; -} - -void UTICK_Deinit(UTICK_Type *base) -{ - /* Turn off utick */ - base->CTRL = 0; - /* Disable utick clock */ - CLOCK_DisableClock(s_utickClock[UTICK_GetInstance(base)]); -} - -uint32_t UTICK_GetStatusFlags(UTICK_Type *base) -{ - return (base->STAT); -} - -void UTICK_ClearStatusFlags(UTICK_Type *base) -{ - base->STAT = UTICK_STAT_INTR_MASK; -} - -void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb) -{ - UTICK_ClearStatusFlags(base); - if (cb) - { - cb(); - } -} - -#if defined(UTICK0) -void UTICK0_DriverIRQHandler(void) -{ - s_utickIsr(UTICK0, s_utickHandle[0]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif -#if defined(UTICK1) -void UTICK1_DriverIRQHandler(void) -{ - s_utickIsr(UTICK1, s_utickHandle[1]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif -#if defined(UTICK2) -void UTICK2_DriverIRQHandler(void) -{ - s_utickIsr(UTICK2, s_utickHandle[2]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_utick.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_utick.h deleted file mode 100644 index 5cc3791b463..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_utick.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_UTICK_H_ -#define _FSL_UTICK_H_ - -#include "fsl_common.h" -/*! - * @addtogroup utick - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief UTICK driver version 2.0.0. */ -#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @brief UTICK timer operational mode. */ -typedef enum _utick_mode -{ - kUTICK_Onetime = 0x0U, /*!< Trigger once*/ - kUTICK_Repeat = 0x1U, /*!< Trigger repeatedly */ -} utick_mode_t; - -/*! @brief UTICK callback function. */ -typedef void (*utick_callback_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! -* @brief Initializes an UTICK by turning its bus clock on -* -*/ -void UTICK_Init(UTICK_Type *base); - -/*! - * @brief Deinitializes a UTICK instance. - * - * This function shuts down Utick bus clock - * - * @param base UTICK peripheral base address. - */ -void UTICK_Deinit(UTICK_Type *base); -/*! - * @brief Get Status Flags. - * - * This returns the status flag - * - * @param base UTICK peripheral base address. - * @return status register value - */ -uint32_t UTICK_GetStatusFlags(UTICK_Type *base); -/*! - * @brief Clear Status Interrupt Flags. - * - * This clears intr status flag - * - * @param base UTICK peripheral base address. - * @return none - */ -void UTICK_ClearStatusFlags(UTICK_Type *base); - -/*! - * @brief Starts UTICK. - * - * This function starts a repeat/onetime countdown with an optional callback - * - * @param base UTICK peripheral base address. - * @param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * @param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * @param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) - * @return none - */ -void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb); -/*! - * @brief UTICK Interrupt Service Handler. - * - * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request - * in UTICK_SetTick()). - * if no user callback is scheduled, the interrupt will simply be cleared. - * - * @param base UTICK peripheral base address. - * @param cb callback scheduled for this instance of UTICK - * @return none - */ -void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_UTICK_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_wwdt.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_wwdt.c deleted file mode 100644 index c793559492a..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_wwdt.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_wwdt.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.wwdt" -#endif - - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Gets the instance from the base address - * - * @param base WWDT peripheral base address - * - * @return The WWDT instance - */ -static uint32_t WWDT_GetInstance(WWDT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to WWDT bases for each instance. */ -static WWDT_Type *const s_wwdtBases[] = WWDT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to WWDT clocks for each instance. */ -static const clock_ip_name_t s_wwdtClocks[] = WWDT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) -/*! @brief Pointers to WWDT resets for each instance. */ -static const reset_ip_name_t s_wwdtResets[] = WWDT_RSTS; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t WWDT_GetInstance(WWDT_Type *base) -{ - uint32_t instance; - uint32_t wwdtArrayCount = (sizeof(s_wwdtBases) / sizeof(s_wwdtBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < wwdtArrayCount; instance++) - { - if (s_wwdtBases[instance] == base) - { - break; - } - } - - assert(instance < wwdtArrayCount); - - return instance; -} - -/******************************************************************************* - * Code - ******************************************************************************/ - -void WWDT_GetDefaultConfig(wwdt_config_t *config) -{ - assert(config); - - /* Enable the watch dog */ - config->enableWwdt = true; - /* Disable the watchdog timeout reset */ - config->enableWatchdogReset = false; - /* Disable the watchdog protection for updating the timeout value */ - config->enableWatchdogProtect = false; - /* Do not lock the watchdog oscillator */ - config->enableLockOscillator = false; - /* Windowing is not in effect */ - config->windowValue = 0xFFFFFFU; - /* Set the timeout value to the max */ - config->timeoutValue = 0xFFFFFFU; - /* No warning is provided */ - config->warningValue = 0; -} - -void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config) -{ - assert(config); - - uint32_t value = 0U; - uint32_t timeDelay = 0U; - uint32_t srcClock_Hz = 0U; - -#if defined(FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE) && FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE - srcClock_Hz = CLOCK_GetFreq(kCLOCK_LPOsc); -#else - srcClock_Hz = CLOCK_GetFreq(kCLOCK_WdtOsc); -#endif - - timeDelay = (SystemCoreClock / srcClock_Hz + 1) * 3; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the WWDT clock */ - CLOCK_EnableClock(s_wwdtClocks[WWDT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) - /* Reset the WWDT module */ - RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]); -#endif - - value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) | - WWDT_MOD_LOCK(config->enableLockOscillator); - /* Set configruation */ - base->TC = WWDT_TC_COUNT(config->timeoutValue); - base->MOD |= value; - base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue); - base->WARNINT = WWDT_WARNINT_WARNINT(config->warningValue); - WWDT_Refresh(base); - /* This WDPROTECT bit can be set once by software and is only cleared by a reset */ - if((base->MOD & WWDT_MOD_WDPROTECT_MASK) == 0U) - { - /* Set the WDPROTECT bit after the Feed Sequence (0xAA, 0x55) with 3 WDCLK delay */ - while (timeDelay--) - { - __NOP(); - } - base->MOD |= WWDT_MOD_WDPROTECT(config->enableWatchdogProtect); - } -} - -void WWDT_Deinit(WWDT_Type *base) -{ - WWDT_Disable(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the WWDT clock */ - CLOCK_DisableClock(s_wwdtClocks[WWDT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void WWDT_Refresh(WWDT_Type *base) -{ - uint32_t primaskValue = 0U; - - /* Disable the global interrupt to protect refresh sequence */ - primaskValue = DisableGlobalIRQ(); - base->FEED = WWDT_FIRST_WORD_OF_REFRESH; - base->FEED = WWDT_SECOND_WORD_OF_REFRESH; - EnableGlobalIRQ(primaskValue); -} - -void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask) -{ - /* Clear the WDINT bit so that we don't accidentally clear it */ - uint32_t reg = (base->MOD & (~WWDT_MOD_WDINT_MASK)); - - /* Clear timeout by writing a zero */ - if (mask & kWWDT_TimeoutFlag) - { - reg &= ~WWDT_MOD_WDTOF_MASK; - } - - /* Clear warning interrupt flag by writing a one */ - if (mask & kWWDT_WarningFlag) - { - reg |= WWDT_MOD_WDINT_MASK; - } - - base->MOD = reg; -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_wwdt.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_wwdt.h deleted file mode 100644 index 938be6a8604..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_wwdt.h +++ /dev/null @@ -1,287 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_WWDT_H_ -#define _FSL_WWDT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup wwdt - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Defines WWDT driver version 2.0.0. */ -#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @name Refresh sequence */ -/*@{*/ -#define WWDT_FIRST_WORD_OF_REFRESH (0xAAU) /*!< First word of refresh sequence */ -#define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */ -/*@}*/ - -/*! @brief Describes WWDT configuration structure. */ -typedef struct _wwdt_config -{ - bool enableWwdt; /*!< Enables or disables WWDT */ - bool enableWatchdogReset; /*!< true: Watchdog timeout will cause a chip reset - false: Watchdog timeout will not cause a chip reset */ - bool enableWatchdogProtect; /*!< true: Enable watchdog protect i.e timeout value can only be - changed after counter is below warning & window values - false: Disable watchdog protect; timeout value can be changed - at any time */ - bool enableLockOscillator; /*!< true: Disabling or powering down the watchdog oscillator is prevented - Once set, this bit can only be cleared by a reset - false: Do not lock oscillator */ - uint32_t windowValue; /*!< Window value, set this to 0xFFFFFF if windowing is not in effect */ - uint32_t timeoutValue; /*!< Timeout value */ - uint32_t warningValue; /*!< Watchdog time counter value that will generate a - warning interrupt. Set this to 0 for no warning */ - -} wwdt_config_t; - -/*! - * @brief WWDT status flags. - * - * This structure contains the WWDT status flags for use in the WWDT functions. - */ -enum _wwdt_status_flags_t -{ - kWWDT_TimeoutFlag = WWDT_MOD_WDTOF_MASK, /*!< Time-out flag, set when the timer times out */ - kWWDT_WarningFlag = WWDT_MOD_WDINT_MASK /*!< Warning interrupt flag, set when timer is below the value WDWARNINT */ -}; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name WWDT Initialization and De-initialization - * @{ - */ - -/*! - * @brief Initializes WWDT configure sturcture. - * - * This function initializes the WWDT configure structure to default value. The default - * value are: - * @code - * config->enableWwdt = true; - * config->enableWatchdogReset = false; - * config->enableWatchdogProtect = false; - * config->enableLockOscillator = false; - * config->windowValue = 0xFFFFFFU; - * config->timeoutValue = 0xFFFFFFU; - * config->warningValue = 0; - * @endcode - * - * @param config Pointer to WWDT config structure. - * @see wwdt_config_t - */ -void WWDT_GetDefaultConfig(wwdt_config_t *config); - -/*! - * @brief Initializes the WWDT. - * - * This function initializes the WWDT. When called, the WWDT runs according to the configuration. - * - * Example: - * @code - * wwdt_config_t config; - * WWDT_GetDefaultConfig(&config); - * config.timeoutValue = 0x7ffU; - * WWDT_Init(wwdt_base,&config); - * @endcode - * - * @param base WWDT peripheral base address - * @param config The configuration of WWDT - */ -void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config); - -/*! - * @brief Shuts down the WWDT. - * - * This function shuts down the WWDT. - * - * @param base WWDT peripheral base address - */ -void WWDT_Deinit(WWDT_Type *base); - -/* @} */ - -/*! - * @name WWDT Functional Operation - * @{ - */ - -/*! - * @brief Enables the WWDT module. - * - * This function write value into WWDT_MOD register to enable the WWDT, it is a write-once bit; - * once this bit is set to one and a watchdog feed is performed, the watchdog timer will run - * permanently. - * - * @param base WWDT peripheral base address - */ -static inline void WWDT_Enable(WWDT_Type *base) -{ - base->MOD |= WWDT_MOD_WDEN_MASK; -} - -/*! - * @brief Disables the WWDT module. - * - * This function write value into WWDT_MOD register to disable the WWDT. - * - * @param base WWDT peripheral base address - */ -static inline void WWDT_Disable(WWDT_Type *base) -{ - base->MOD &= ~WWDT_MOD_WDEN_MASK; -} - -/*! - * @brief Gets all WWDT status flags. - * - * This function gets all status flags. - * - * Example for getting Timeout Flag: - * @code - * uint32_t status; - * status = WWDT_GetStatusFlags(wwdt_base) & kWWDT_TimeoutFlag; - * @endcode - * @param base WWDT peripheral base address - * @return The status flags. This is the logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -static inline uint32_t WWDT_GetStatusFlags(WWDT_Type *base) -{ - return (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); -} - -/*! - * @brief Clear WWDT flag. - * - * This function clears WWDT status flag. - * - * Example for clearing warning flag: - * @code - * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); - * @endcode - * @param base WWDT peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask); - -/*! - * @brief Set the WWDT warning value. - * - * The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog - * interrupt. When the watchdog timer counter is no longer greater than the value defined by - * WARNINT, an interrupt will be generated after the subsequent WDCLK. - * - * @param base WWDT peripheral base address - * @param warningValue WWDT warning value. - */ -static inline void WWDT_SetWarningValue(WWDT_Type *base, uint32_t warningValue) -{ - base->WARNINT = WWDT_WARNINT_WARNINT(warningValue); -} - -/*! - * @brief Set the WWDT timeout value. - * - * This function sets the timeout value. Every time a feed sequence occurs the value in the TC - * register is loaded into the Watchdog timer. Writing a value below 0xFF will cause 0xFF to be - * loaded into the TC register. Thus the minimum time-out interval is TWDCLK*256*4. - * If enableWatchdogProtect flag is true in wwdt_config_t config structure, any attempt to change - * the timeout value before the watchdog counter is below the warning and window values - * will cause a watchdog reset and set the WDTOF flag. - * - * @param base WWDT peripheral base address - * @param timeoutCount WWDT timeout value, count of WWDT clock tick. - */ -static inline void WWDT_SetTimeoutValue(WWDT_Type *base, uint32_t timeoutCount) -{ - base->TC = WWDT_TC_COUNT(timeoutCount); -} - -/*! - * @brief Sets the WWDT window value. - * - * The WINDOW register determines the highest TV value allowed when a watchdog feed is performed. - * If a feed sequence occurs when timer value is greater than the value in WINDOW, a watchdog - * event will occur. To disable windowing, set windowValue to 0xFFFFFF (maximum possible timer - * value) so windowing is not in effect. - * - * @param base WWDT peripheral base address - * @param windowValue WWDT window value. - */ -static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue) -{ - base->WINDOW = WWDT_WINDOW_WINDOW(windowValue); -} - -/*! - * @brief Refreshes the WWDT timer. - * - * This function feeds the WWDT. - * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. - * - * @param base WWDT peripheral base address - */ -void WWDT_Refresh(WWDT_Type *base); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_WWDT_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/fsl_device_registers.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/fsl_device_registers.h deleted file mode 100644 index 18ee36a30c2..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/fsl_device_registers.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016 - 2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __FSL_DEVICE_REGISTERS_H__ -#define __FSL_DEVICE_REGISTERS_H__ - -/* - * Include the cpu specific register header files. - * - * The CPU macro should be declared in the project or makefile. - */ -#if (defined(CPU_LPC54114J256BD64_cm4) || defined(CPU_LPC54114J256UK49_cm4)) - -#define LPC54114_cm4_SERIES - -/* CMSIS-style register definitions */ -#include "LPC54114_cm4.h" -/* CPU specific feature definitions */ -#include "LPC54114_cm4_features.h" - -#elif (defined(CPU_LPC54114J256BD64_cm0plus) || defined(CPU_LPC54114J256UK49_cm0plus)) - -#define LPC54114_cm0plus_SERIES - -/* CMSIS-style register definitions */ -#include "LPC54114_cm0plus.h" -/* CPU specific feature definitions */ -#include "LPC54114_cm0plus_features.h" - -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_DEVICE_REGISTERS_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/LPC54114J256_cm0plus_flash.ld b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/LPC54114J256_cm0plus_flash.ld deleted file mode 100644 index d4139e668f9..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/LPC54114J256_cm0plus_flash.ld +++ /dev/null @@ -1,234 +0,0 @@ -/* -** ################################################################### -** Processors: LPC54114J256_cm0plus -** -** Compiler: GNU C Compiler -** Reference manual: LPC54114 Series Reference Manual, Rev. 0 , 11/2016 -** Version: rev. 1.0, 2016-11-02 -** Build: b161214 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** The Clear BSD License -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted (subject to the limitations in the disclaimer below) provided -** that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; -RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; - - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x20010000, LENGTH = 0x000000C0 - m_text (RX) : ORIGIN = 0x200100C0, LENGTH = 0x0000FF3F - m_data (RW) : ORIGIN = 0x20020000, LENGTH = 0x00007FFF - RPMSG_SHMEM_SIZE - rpmsg_sh_mem (RW) : ORIGIN = 0x20026800, LENGTH = RPMSG_SHMEM_SIZE -} - -/* Define output sections */ -SECTIONS -{ - /* NOINIT section for rpmsg_sh_mem */ - .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) - { - *(.noinit.$rpmsg_sh_mem*) - . = ALIGN(4) ; - } > rpmsg_sh_mem - - /* The startup code goes first into internal flash */ - .interrupts : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.ramfunc*) /* for functions in ram */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} - diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/LPC54114J256_cm0plus_ram.ld b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/LPC54114J256_cm0plus_ram.ld deleted file mode 100644 index ff6068634ba..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/LPC54114J256_cm0plus_ram.ld +++ /dev/null @@ -1,264 +0,0 @@ -/* -** ################################################################### -** Processors: LPC54114J256_cm0plus -** -** Compiler: GNU C Compiler -** Reference manual: LPC54114 Series Reference Manual, Rev. 0 , 11/2016 -** Version: rev. 1.0, 2016-11-02 -** Build: b161214 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** The Clear BSD License -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright (c) 2016 - 2017 , NXP -** All rights reserved. -** -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted (subject to the limitations in the disclaimer below) provided -** that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; -RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x20010000, LENGTH = 0x000000C0 - m_text (RX) : ORIGIN = 0x200100C0, LENGTH = 0x0000FF3F - m_data (RW) : ORIGIN = 0x20020000, LENGTH = 0x00007FFF - RPMSG_SHMEM_SIZE - rpmsg_sh_mem (RW) : ORIGIN = 0x20026800, LENGTH = RPMSG_SHMEM_SIZE -} - -/* Define output sections */ -SECTIONS -{ - /* NOINIT section for rpmsg_sh_mem */ - .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) - { - *(.noinit.$rpmsg_sh_mem*) - . = ALIGN(4) ; - } > rpmsg_sh_mem - - /* The startup code goes first into internal flash */ - .interrupts : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.ramfunc*) /* for functions in ram */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} - diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/LPC54114J256_cm4_ram.ld b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/LPC54114J256_cm4_ram.ld deleted file mode 100644 index 2c00abef81f..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/LPC54114J256_cm4_ram.ld +++ /dev/null @@ -1,257 +0,0 @@ -/* -** ################################################################### -** Processors: LPC54114J256_cm4 -** -** Compiler: GNU C Compiler -** Reference manual: LPC54114 Series Reference Manual, Rev. 0 , 11/2016 -** Version: rev. 1.0, 2016-11-02 -** Build: b161214 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** The Clear BSD License -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright (c) 2016 - 2017 , NXP -** All rights reserved. -** -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted (subject to the limitations in the disclaimer below) provided -** that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; -RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; - - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x20000000, LENGTH = 0x000000E0 - m_text (RX) : ORIGIN = 0x200000E0, LENGTH = 0x0001FF20 - m_data (RW) : ORIGIN = 0x20020000, LENGTH = 0x00008000 -} - -/* Define output sections */ -SECTIONS -{ - - /* The startup code goes first into internal flash */ - .interrupts : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.ramfunc*) /* for functions in ram */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} - diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/SConscript b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/SConscript deleted file mode 100644 index a39e208e857..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/SConscript +++ /dev/null @@ -1,10 +0,0 @@ -from building import * - -cwd = GetCurrentDir() -src = Split(''' -startup_LPC54114_cm4.S -''') - -group = DefineGroup('Libraries', src, depend = [''], LIBS=['libpower_cm4_hardabi'], LIBPATH=[cwd]) - -Return('group') diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/libpower_cm0.a b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/libpower_cm0.a deleted file mode 100644 index 98fab339a2a..00000000000 Binary files a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/libpower_cm0.a and /dev/null differ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/libpower_cm4_hardabi.a b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/libpower_cm4_hardabi.a deleted file mode 100644 index 1f40c8ccf66..00000000000 Binary files a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/libpower_cm4_hardabi.a and /dev/null differ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/libpower_cm4_softabi.a b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/libpower_cm4_softabi.a deleted file mode 100644 index 0cdaf13a35f..00000000000 Binary files a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/libpower_cm4_softabi.a and /dev/null differ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/startup_LPC54114_cm0plus.S b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/startup_LPC54114_cm0plus.S deleted file mode 100644 index d79fe51d77e..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/startup_LPC54114_cm0plus.S +++ /dev/null @@ -1,644 +0,0 @@ -/* ---------------------------------------------------------------------------------------*/ -/* @file: startup_LPC54114_cm0plus.S */ -/* @purpose: CMSIS Cortex-M0 Core Device Startup File */ -/* LPC54114_cm0plus */ -/* @version: 1.0 */ -/* @date: 2016-11-2 */ -/* @build: b161214 */ -/* ---------------------------------------------------------------------------------------*/ -/* */ -/* The Clear BSD License */ -/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2017 NXP */ -/* All rights reserved. */ -/* */ -/* Redistribution and use in source and binary forms, with or without modification, */ -/* are permitted (subject to the limitations in the disclaimer below) provided */ -/* that the following conditions are met: */ -/* */ -/* 1. Redistributions of source code must retain the above copyright notice, this list */ -/* of conditions and the following disclaimer. */ -/* */ -/* 2. Redistributions in binary form must reproduce the above copyright notice, this */ -/* list of conditions and the following disclaimer in the documentation and/or */ -/* other materials provided with the distribution. */ -/* */ -/* 3. Neither the name of the copyright holder nor the names of its */ -/* contributors may be used to endorse or promote products derived from this */ -/* software without specific prior written permission. */ -/* */ -/* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S' PATENT RIGHTS ARE GRANTED BY THIS LICENSE.*/ -/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ -/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ -/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ -/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ -/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ -/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ -/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ -/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ -/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ -/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - .syntax unified - .arch armv7-m - - .section .isr_vector, "a" - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts*/ - .long WDT_BOD_IRQHandler /* Watchdog Timer, Brownout detect */ - .long DMA0_IRQHandler /* DMA controller interrupt */ - .long GINT0_IRQHandler /* GPIO group 0 */ - .long GINT1_IRQHandler /* GPIO group 1 */ - .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - .long PIN_INT1_IRQHandler /* Pin interrupt 1 or pattern match engine slice 1 */ - .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - .long UTICK0_IRQHandler /* Micro-tick Timer */ - .long MRT0_IRQHandler /* Multi-rate timer */ - .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ - .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ - .long SCT0_IRQHandler /* SCTimer/PWM */ - .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ - .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */ - .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */ - .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */ - .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */ - .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */ - .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, FLEXCOMM) */ - .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, FLEXCOMM) */ - .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, FLEXCOMM) */ - .long ADC0_SEQA_IRQHandler /* ADC0 sequence A completion */ - .long ADC0_SEQB_IRQHandler /* ADC0 sequence B completion */ - .long ADC0_THCMP_IRQHandler /* ADC0 threshold compare and error. */ - .long DMIC0_IRQHandler /* RTC alarm and wake-up interrupts */ - .long HWVAD0_IRQHandler /* Hardware Voice Activity Detector */ - .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ - .long USB0_IRQHandler /* USB device */ - .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ - .long IOH_IRQHandler /* IOH interrupt */ - .long MAILBOX_IRQHandler /* Mailbox interrupt */ - .size __Vectors, . - __Vectors - - - - .text - .thumb -#ifndef SLAVEBOOT -rel_vals: - .long 0xE000ED00 /* cpu_id */ - .long 0x40000800 /* cpu_ctrl */ - .long 0x40000804 /* coproc_boot */ - .long 0x40000808 /* coproc_stack */ - .short 0x0FFF - .short 0x0C24 -#endif -/* Reset Handler */ - - .thumb_func - .align 2 - .globl Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function - -Reset_Handler: -#ifndef SLAVEBOOT -/* Both the M0+ and M4 core come via this shared startup code, - * but the M0+ and M4 core have different vector tables. - * Determine if the core executing this code is the master or - * the slave and handle each core state individually. */ - -shared_boot_entry: - ldr r6, =rel_vals - - /* Flag for slave core (0) */ - movs r4, 0 - movs r5, 1 - - /* Determine which core (M0+ or M4) this code is running on */ - /* r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) */ -get_current_core_id: - ldr r0, [r6, #0] - ldr r1, [r0] /* r1 = CPU ID status */ - lsrs r1, r1, #4 /* Right justify 12 CPU ID bits */ - ldrh r2, [r6, #16] /* Mask for CPU ID bits */ - ands r2, r1, r2 /* r2 = ARM COrtex CPU ID */ - ldrh r3, [r6, #18] /* Mask for CPU ID bits */ - cmp r3, r2 /* Core ID matches M4 identifier */ - bne get_master_status - mov r4, r5 /* Set flag for master core (1) */ - - /* Determine if M4 core is the master or slave */ - /* r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) */ -get_master_status: - ldr r0, [r6, #4] - ldr r3, [r0] /* r3 = SYSCON co-processor CPU control status */ - - ands r3, r3, r5 /* r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) */ - - /* Select boot based on selected master core and core ID */ - -select_boot: - eors r3, r3, r4 /* r4 = (Bit 0: 0 = master, 1 = slave) */ - - bne slave_boot - b normal_boot - - /* Slave boot */ -slave_boot: - ldr r0, [r6, #8] - ldr r2, [r0] /* r1 = SYSCON co-processor boot address */ - - cmp r2, #0 /* Slave boot address = 0 (not set up)? */ - - beq cpu_sleep - ldr r0, [r6, #12] - ldr r1, [r0] /* r5 = SYSCON co-processor stack address */ - - mov sp, r1 /* Update slave CPU stack pointer */ - - /* Be sure to update VTOR for the slave MCU to point to the */ - /* slave vector table in boot memory */ - bx r2 /* Jump to slave boot address */ - - /* Slave isn't yet setup for system boot from the master */ - /* so sleep until the master sets it up and then reboots it */ -cpu_sleep: - mov sp, r5 /* Will force exception if something happens */ -cpu_sleep_wfi: - wfi /* Sleep forever until master reboots */ - b cpu_sleep_wfi -#endif /* defined(SLAVEBOOT) */ - -#ifndef __START -#define __START _start -#endif -#ifndef __ATOLLIC__ -normal_boot: -#ifndef __NO_SYSTEM_INIT - ldr r0,=SystemInit - blx r0 -#endif -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .LC0 - -.LC1: - subs r3, 4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .LC1 -.LC0: - -#ifdef __STARTUP_CLEAR_BSS -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * Loop to zero out BSS section, which uses following symbols - * in linker script: - * __bss_start__: start of BSS section. Must align to 4 - * __bss_end__: end of BSS section. Must align to 4 - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - subs r2, r1 - ble .LC3 - - movs r0, 0 -.LC2: - str r0, [r1, r2] - subs r2, 4 - bge .LC2 -.LC3: -#endif /* __STARTUP_CLEAR_BSS */ - ldr r0,=__START - blx r0 -#else - ldr r0,=__libc_init_array - blx r0 - ldr r0,=main - bx r0 -#endif - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - - .align 1 - .thumb_func - .weak WDT_BOD_IRQHandler - .type WDT_BOD_IRQHandler, %function -WDT_BOD_IRQHandler: - ldr r0,=WDT_BOD_DriverIRQHandler - bx r0 - .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler - - - .align 1 - .thumb_func - .weak DMA0_IRQHandler - .type DMA0_IRQHandler, %function -DMA0_IRQHandler: - ldr r0,=DMA0_DriverIRQHandler - bx r0 - .size DMA0_IRQHandler, . - DMA0_IRQHandler - - .align 1 - .thumb_func - .weak GINT0_IRQHandler - .type GINT0_IRQHandler, %function -GINT0_IRQHandler: - ldr r0,=GINT0_DriverIRQHandler - bx r0 - .size GINT0_IRQHandler, . - GINT0_IRQHandler - - .align 1 - .thumb_func - .weak GINT1_IRQHandler - .type GINT1_IRQHandler, %function -GINT1_IRQHandler: - ldr r0,=GINT1_DriverIRQHandler - bx r0 - .size GINT1_IRQHandler, . - GINT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT0_IRQHandler - .type PIN_INT0_IRQHandler, %function -PIN_INT0_IRQHandler: - ldr r0,=PIN_INT0_DriverIRQHandler - bx r0 - .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT1_IRQHandler - .type PIN_INT1_IRQHandler, %function -PIN_INT1_IRQHandler: - ldr r0,=PIN_INT1_DriverIRQHandler - bx r0 - .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT2_IRQHandler - .type PIN_INT2_IRQHandler, %function -PIN_INT2_IRQHandler: - ldr r0,=PIN_INT2_DriverIRQHandler - bx r0 - .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT3_IRQHandler - .type PIN_INT3_IRQHandler, %function -PIN_INT3_IRQHandler: - ldr r0,=PIN_INT3_DriverIRQHandler - bx r0 - .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler - - .align 1 - .thumb_func - .weak UTICK0_IRQHandler - .type UTICK0_IRQHandler, %function -UTICK0_IRQHandler: - ldr r0,=UTICK0_DriverIRQHandler - bx r0 - .size UTICK0_IRQHandler, . - UTICK0_IRQHandler - - .align 1 - .thumb_func - .weak MRT0_IRQHandler - .type MRT0_IRQHandler, %function -MRT0_IRQHandler: - ldr r0,=MRT0_DriverIRQHandler - bx r0 - .size MRT0_IRQHandler, . - MRT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER0_IRQHandler - .type CTIMER0_IRQHandler, %function -CTIMER0_IRQHandler: - ldr r0,=CTIMER0_DriverIRQHandler - bx r0 - .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER1_IRQHandler - .type CTIMER1_IRQHandler, %function -CTIMER1_IRQHandler: - ldr r0,=CTIMER1_DriverIRQHandler - bx r0 - .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler - - - .align 1 - .thumb_func - .weak SCT0_IRQHandler - .type SCT0_IRQHandler, %function -SCT0_IRQHandler: - ldr r0,=SCT0_DriverIRQHandler - bx r0 - .size SCT0_IRQHandler, . - SCT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER3_IRQHandler - .type CTIMER3_IRQHandler, %function -CTIMER3_IRQHandler: - ldr r0,=CTIMER3_DriverIRQHandler - bx r0 - .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM0_IRQHandler - .type FLEXCOMM0_IRQHandler, %function -FLEXCOMM0_IRQHandler: - ldr r0,=FLEXCOMM0_DriverIRQHandler - bx r0 - .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM1_IRQHandler - .type FLEXCOMM1_IRQHandler, %function -FLEXCOMM1_IRQHandler: - ldr r0,=FLEXCOMM1_DriverIRQHandler - bx r0 - .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM2_IRQHandler - .type FLEXCOMM2_IRQHandler, %function -FLEXCOMM2_IRQHandler: - ldr r0,=FLEXCOMM2_DriverIRQHandler - bx r0 - .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM3_IRQHandler - .type FLEXCOMM3_IRQHandler, %function -FLEXCOMM3_IRQHandler: - ldr r0,=FLEXCOMM3_DriverIRQHandler - bx r0 - .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM4_IRQHandler - .type FLEXCOMM4_IRQHandler, %function -FLEXCOMM4_IRQHandler: - ldr r0,=FLEXCOMM4_DriverIRQHandler - bx r0 - .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM5_IRQHandler - .type FLEXCOMM5_IRQHandler, %function -FLEXCOMM5_IRQHandler: - ldr r0,=FLEXCOMM5_DriverIRQHandler - bx r0 - .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM6_IRQHandler - .type FLEXCOMM6_IRQHandler, %function -FLEXCOMM6_IRQHandler: - ldr r0,=FLEXCOMM6_DriverIRQHandler - bx r0 - .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM7_IRQHandler - .type FLEXCOMM7_IRQHandler, %function -FLEXCOMM7_IRQHandler: - ldr r0,=FLEXCOMM7_DriverIRQHandler - bx r0 - .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler - - - .align 1 - .thumb_func - .weak ADC0_SEQA_IRQHandler - .type ADC0_SEQA_IRQHandler, %function -ADC0_SEQA_IRQHandler: - ldr r0,=ADC0_SEQA_DriverIRQHandler - bx r0 - .size ADC0_SEQA_IRQHandler, . - ADC0_SEQA_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_SEQB_IRQHandler - .type ADC0_SEQB_IRQHandler, %function -ADC0_SEQB_IRQHandler: - ldr r0,=ADC0_SEQB_DriverIRQHandler - bx r0 - .size ADC0_SEQB_IRQHandler, . - ADC0_SEQB_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_THCMP_IRQHandler - .type ADC0_THCMP_IRQHandler, %function -ADC0_THCMP_IRQHandler: - ldr r0,=ADC0_THCMP_DriverIRQHandler - bx r0 - .size ADC0_THCMP_IRQHandler, . - ADC0_THCMP_IRQHandler - - .align 1 - .thumb_func - .weak DMIC0_IRQHandler - .type DMIC0_IRQHandler, %function -DMIC0_IRQHandler: - ldr r0,=DMIC0_DriverIRQHandler - bx r0 - .size DMIC0_IRQHandler, . - DMIC0_IRQHandler - - .align 1 - .thumb_func - .weak HWVAD0_IRQHandler - .type HWVAD0_IRQHandler, %function -HWVAD0_IRQHandler: - ldr r0,=HWVAD0_DriverIRQHandler - bx r0 - .size HWVAD0_IRQHandler, . - HWVAD0_IRQHandler - - .align 1 - .thumb_func - .weak USB0_NEEDCLK_IRQHandler - .type USB0_NEEDCLK_IRQHandler, %function -USB0_NEEDCLK_IRQHandler: - ldr r0,=USB0_NEEDCLK_DriverIRQHandler - bx r0 - .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak USB0_IRQHandler - .type USB0_IRQHandler, %function -USB0_IRQHandler: - ldr r0,=USB0_DriverIRQHandler - bx r0 - .size USB0_IRQHandler, . - USB0_IRQHandler - - .align 1 - .thumb_func - .weak RTC_IRQHandler - .type RTC_IRQHandler, %function -RTC_IRQHandler: - ldr r0,=RTC_DriverIRQHandler - bx r0 - .size RTC_IRQHandler, . - RTC_IRQHandler - - .align 1 - .thumb_func - .weak IOH_IRQHandler - .type IOH_IRQHandler, %function -IOH_IRQHandler: - ldr r0,=IOH_DriverIRQHandler - bx r0 - .size IOH_IRQHandler, . - IOH_IRQHandler - - .align 1 - .thumb_func - .weak MAILBOX_IRQHandler - .type MAILBOX_IRQHandler, %function -MAILBOX_IRQHandler: - ldr r0,=MAILBOX_DriverIRQHandler - bx r0 - .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler - - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm - -/* Exception Handlers */ - def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect */ - def_irq_handler DMA0_DriverIRQHandler /* DMA controller */ - def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */ - def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */ - def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */ - def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */ - def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */ - def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */ - def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */ - def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */ - def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C) */ - def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C) */ - def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C) */ - def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C) */ - def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C) */ - def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C) */ - def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S) */ - def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S) */ - def_irq_handler ADC0_SEQA_DriverIRQHandler /* ADC0 sequence A completion. */ - def_irq_handler ADC0_SEQB_DriverIRQHandler /* ADC0 sequence B completion. */ - def_irq_handler ADC0_THCMP_DriverIRQHandler /* ADC0 threshold compare and error. */ - def_irq_handler DMIC0_DriverIRQHandler /* Digital microphone and DMIC subsystem */ - def_irq_handler HWVAD0_DriverIRQHandler /* Hardware Voice sActivity Detector */ - def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */ - def_irq_handler USB0_DriverIRQHandler /* USB device */ - def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */ - def_irq_handler IOH_DriverIRQHandler /* IOH */ - def_irq_handler MAILBOX_DriverIRQHandler /* Mailbox interrupt (present on selected devices) */ - - .end diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/startup_LPC54114_cm4.S b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/startup_LPC54114_cm4.S deleted file mode 100644 index 886df39fa8c..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/startup_LPC54114_cm4.S +++ /dev/null @@ -1,767 +0,0 @@ -/* ---------------------------------------------------------------------------------------*/ -/* @file: startup_LPC54114_cm4.S */ -/* @purpose: CMSIS Cortex-M4 Core Device Startup File */ -/* LPC54114_cm4 */ -/* @version: 1.0 */ -/* @date: 2016-11-2 */ -/* @build: b161214 */ -/* ---------------------------------------------------------------------------------------*/ -/* */ -/* The Clear BSD License */ -/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2017 NXP */ -/* All rights reserved. */ -/* */ -/* Redistribution and use in source and binary forms, with or without modification, */ -/* are permitted (subject to the limitations in the disclaimer below) provided */ -/* that the following conditions are met: */ -/* */ -/* 1. Redistributions of source code must retain the above copyright notice, this list */ -/* of conditions and the following disclaimer. */ -/* */ -/* 2. Redistributions in binary form must reproduce the above copyright notice, this */ -/* list of conditions and the following disclaimer in the documentation and/or */ -/* other materials provided with the distribution. */ -/* */ -/* 3. Neither the name of the copyright holder nor the names of its */ -/* contributors may be used to endorse or promote products derived from this */ -/* software without specific prior written permission. */ -/* */ -/* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S' PATENT RIGHTS ARE GRANTED BY THIS LICENSE.*/ -/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ -/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ -/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ -/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ -/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ -/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ -/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ -/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ -/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ -/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - .syntax unified - .arch armv7-m - - .section .isr_vector, "a" - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long MemManage_Handler /* MPU Fault Handler*/ - .long BusFault_Handler /* Bus Fault Handler*/ - .long UsageFault_Handler /* Usage Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long DebugMon_Handler /* Debug Monitor Handler*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts*/ - .long WDT_BOD_IRQHandler /* Watchdog Timer, Brownout detect */ - .long DMA0_IRQHandler /* DMA controller interrupt */ - .long GINT0_IRQHandler /* GPIO group 0 */ - .long GINT1_IRQHandler /* GPIO group 1 */ - .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - .long PIN_INT1_IRQHandler /* Pin interrupt 1 or pattern match engine slice 1 */ - .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - .long UTICK0_IRQHandler /* Micro-tick Timer */ - .long MRT0_IRQHandler /* Multi-rate timer */ - .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ - .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ - .long SCT0_IRQHandler /* SCTimer/PWM */ - .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ - .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */ - .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */ - .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */ - .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */ - .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */ - .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, FLEXCOMM) */ - .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, FLEXCOMM) */ - .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, FLEXCOMM) */ - .long ADC0_SEQA_IRQHandler /* ADC0 sequence A completion */ - .long ADC0_SEQB_IRQHandler /* ADC0 sequence B completion */ - .long ADC0_THCMP_IRQHandler /* ADC0 threshold compare and error. */ - .long DMIC0_IRQHandler /* RTC alarm and wake-up interrupts */ - .long HWVAD0_IRQHandler /* Hardware Voice Activity Detector */ - .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ - .long USB0_IRQHandler /* USB device */ - .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ - .long IOH_IRQHandler /* IOH interrupt */ - .long MAILBOX_IRQHandler /* Mailbox interrupt */ - .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ - .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ - .long 0 /* Reserved interrupt */ - .long SPIFI0_IRQHandler /* SPI flash interface */ - .size __Vectors, . - __Vectors - - - - .text - .thumb -#ifndef SLAVEBOOT -rel_vals: - .long 0xE000ED00 /* cpu_id */ - .long 0x40000800 /* cpu_ctrl */ - .long 0x40000804 /* coproc_boot */ - .long 0x40000808 /* coproc_stack */ - .short 0x0FFF - .short 0x0C24 -#endif -/* Reset Handler */ - - .thumb_func - .align 2 - .globl Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function - -Reset_Handler: -#ifndef SLAVEBOOT -/* Both the M0+ and M4 core come via this shared startup code, - * but the M0+ and M4 core have different vector tables. - * Determine if the core executing this code is the master or - * the slave and handle each core state individually. */ - -shared_boot_entry: - ldr r6, =rel_vals - - /* Flag for slave core (0) */ - movs r4, 0 - movs r5, 1 - - /* Determine which core (M0+ or M4) this code is running on */ - /* r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) */ -get_current_core_id: - ldr r0, [r6, #0] - ldr r1, [r0] /* r1 = CPU ID status */ - lsrs r1, r1, #4 /* Right justify 12 CPU ID bits */ - ldrh r2, [r6, #16] /* Mask for CPU ID bits */ - ands r2, r1, r2 /* r2 = ARM COrtex CPU ID */ - ldrh r3, [r6, #18] /* Mask for CPU ID bits */ - cmp r3, r2 /* Core ID matches M4 identifier */ - bne get_master_status - mov r4, r5 /* Set flag for master core (1) */ - - /* Determine if M4 core is the master or slave */ - /* r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) */ -get_master_status: - ldr r0, [r6, #4] - ldr r3, [r0] /* r3 = SYSCON co-processor CPU control status */ - - ands r3, r3, r5 /* r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) */ - - /* Select boot based on selected master core and core ID */ - -select_boot: - eors r3, r3, r4 /* r4 = (Bit 0: 0 = master, 1 = slave) */ - - bne slave_boot - b normal_boot - - /* Slave boot */ -slave_boot: - ldr r0, [r6, #8] - ldr r2, [r0] /* r1 = SYSCON co-processor boot address */ - - cmp r2, #0 /* Slave boot address = 0 (not set up)? */ - - beq cpu_sleep - ldr r0, [r6, #12] - ldr r1, [r0] /* r5 = SYSCON co-processor stack address */ - - mov sp, r1 /* Update slave CPU stack pointer */ - - /* Be sure to update VTOR for the slave MCU to point to the */ - /* slave vector table in boot memory */ - bx r2 /* Jump to slave boot address */ - - /* Slave isn't yet setup for system boot from the master */ - /* so sleep until the master sets it up and then reboots it */ -cpu_sleep: - mov sp, r5 /* Will force exception if something happens */ -cpu_sleep_wfi: - wfi /* Sleep forever until master reboots */ - b cpu_sleep_wfi -#endif /* defined(SLAVEBOOT) */ - -#ifndef __START -#define __START _start -#endif -#ifndef __ATOLLIC__ -normal_boot: -#ifndef __NO_SYSTEM_INIT - ldr r0,=SystemInit - blx r0 -#endif - /* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -#if 1 -/* Here are two copies of loop implemenations. First one favors code size - * and the second one favors performance. Default uses the first one. - * Change to "#if 0" to use the second one */ -.LC0: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .LC0 -#else - subs r3, r2 - ble .LC1 -.LC0: - subs r3, #4 - ldr r0, [r1, r3] - str r0, [r2, r3] - bgt .LC0 -.LC1: -#endif - -#ifdef __STARTUP_CLEAR_BSS -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * Loop to zero out BSS section, which uses following symbols - * in linker script: - * __bss_start__: start of BSS section. Must align to 4 - * __bss_end__: end of BSS section. Must align to 4 - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.LC2: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC2 -#endif /* __STARTUP_CLEAR_BSS */ - ldr r0,=entry - blx r0 -#else - ldr r0,=__libc_init_array - blx r0 - ldr r0,=main - bx r0 -#endif - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak MemManage_Handler - .type MemManage_Handler, %function -MemManage_Handler: - ldr r0,=MemManage_Handler - bx r0 - .size MemManage_Handler, . - MemManage_Handler - - .align 1 - .thumb_func - .weak BusFault_Handler - .type BusFault_Handler, %function -BusFault_Handler: - ldr r0,=BusFault_Handler - bx r0 - .size BusFault_Handler, . - BusFault_Handler - - .align 1 - .thumb_func - .weak UsageFault_Handler - .type UsageFault_Handler, %function -UsageFault_Handler: - ldr r0,=UsageFault_Handler - bx r0 - .size UsageFault_Handler, . - UsageFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak DebugMon_Handler - .type DebugMon_Handler, %function -DebugMon_Handler: - ldr r0,=DebugMon_Handler - bx r0 - .size DebugMon_Handler, . - DebugMon_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - - .align 1 - .thumb_func - .weak WDT_BOD_IRQHandler - .type WDT_BOD_IRQHandler, %function -WDT_BOD_IRQHandler: - ldr r0,=WDT_BOD_DriverIRQHandler - bx r0 - .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler - - - .align 1 - .thumb_func - .weak DMA0_IRQHandler - .type DMA0_IRQHandler, %function -DMA0_IRQHandler: - ldr r0,=DMA0_DriverIRQHandler - bx r0 - .size DMA0_IRQHandler, . - DMA0_IRQHandler - - .align 1 - .thumb_func - .weak GINT0_IRQHandler - .type GINT0_IRQHandler, %function -GINT0_IRQHandler: - ldr r0,=GINT0_DriverIRQHandler - bx r0 - .size GINT0_IRQHandler, . - GINT0_IRQHandler - - .align 1 - .thumb_func - .weak GINT1_IRQHandler - .type GINT1_IRQHandler, %function -GINT1_IRQHandler: - ldr r0,=GINT1_DriverIRQHandler - bx r0 - .size GINT1_IRQHandler, . - GINT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT0_IRQHandler - .type PIN_INT0_IRQHandler, %function -PIN_INT0_IRQHandler: - ldr r0,=PIN_INT0_DriverIRQHandler - bx r0 - .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT1_IRQHandler - .type PIN_INT1_IRQHandler, %function -PIN_INT1_IRQHandler: - ldr r0,=PIN_INT1_DriverIRQHandler - bx r0 - .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT2_IRQHandler - .type PIN_INT2_IRQHandler, %function -PIN_INT2_IRQHandler: - ldr r0,=PIN_INT2_DriverIRQHandler - bx r0 - .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT3_IRQHandler - .type PIN_INT3_IRQHandler, %function -PIN_INT3_IRQHandler: - ldr r0,=PIN_INT3_DriverIRQHandler - bx r0 - .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler - - .align 1 - .thumb_func - .weak UTICK0_IRQHandler - .type UTICK0_IRQHandler, %function -UTICK0_IRQHandler: - ldr r0,=UTICK0_DriverIRQHandler - bx r0 - .size UTICK0_IRQHandler, . - UTICK0_IRQHandler - - .align 1 - .thumb_func - .weak MRT0_IRQHandler - .type MRT0_IRQHandler, %function -MRT0_IRQHandler: - ldr r0,=MRT0_DriverIRQHandler - bx r0 - .size MRT0_IRQHandler, . - MRT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER0_IRQHandler - .type CTIMER0_IRQHandler, %function -CTIMER0_IRQHandler: - ldr r0,=CTIMER0_DriverIRQHandler - bx r0 - .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER1_IRQHandler - .type CTIMER1_IRQHandler, %function -CTIMER1_IRQHandler: - ldr r0,=CTIMER1_DriverIRQHandler - bx r0 - .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler - - - .align 1 - .thumb_func - .weak SCT0_IRQHandler - .type SCT0_IRQHandler, %function -SCT0_IRQHandler: - ldr r0,=SCT0_DriverIRQHandler - bx r0 - .size SCT0_IRQHandler, . - SCT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER3_IRQHandler - .type CTIMER3_IRQHandler, %function -CTIMER3_IRQHandler: - ldr r0,=CTIMER3_DriverIRQHandler - bx r0 - .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM0_IRQHandler - .type FLEXCOMM0_IRQHandler, %function -FLEXCOMM0_IRQHandler: - ldr r0,=FLEXCOMM0_DriverIRQHandler - bx r0 - .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM1_IRQHandler - .type FLEXCOMM1_IRQHandler, %function -FLEXCOMM1_IRQHandler: - ldr r0,=FLEXCOMM1_DriverIRQHandler - bx r0 - .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM2_IRQHandler - .type FLEXCOMM2_IRQHandler, %function -FLEXCOMM2_IRQHandler: - ldr r0,=FLEXCOMM2_DriverIRQHandler - bx r0 - .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM3_IRQHandler - .type FLEXCOMM3_IRQHandler, %function -FLEXCOMM3_IRQHandler: - ldr r0,=FLEXCOMM3_DriverIRQHandler - bx r0 - .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM4_IRQHandler - .type FLEXCOMM4_IRQHandler, %function -FLEXCOMM4_IRQHandler: - ldr r0,=FLEXCOMM4_DriverIRQHandler - bx r0 - .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM5_IRQHandler - .type FLEXCOMM5_IRQHandler, %function -FLEXCOMM5_IRQHandler: - ldr r0,=FLEXCOMM5_DriverIRQHandler - bx r0 - .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM6_IRQHandler - .type FLEXCOMM6_IRQHandler, %function -FLEXCOMM6_IRQHandler: - ldr r0,=FLEXCOMM6_DriverIRQHandler - bx r0 - .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM7_IRQHandler - .type FLEXCOMM7_IRQHandler, %function -FLEXCOMM7_IRQHandler: - ldr r0,=FLEXCOMM7_DriverIRQHandler - bx r0 - .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler - - - .align 1 - .thumb_func - .weak ADC0_SEQA_IRQHandler - .type ADC0_SEQA_IRQHandler, %function -ADC0_SEQA_IRQHandler: - ldr r0,=ADC0_SEQA_DriverIRQHandler - bx r0 - .size ADC0_SEQA_IRQHandler, . - ADC0_SEQA_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_SEQB_IRQHandler - .type ADC0_SEQB_IRQHandler, %function -ADC0_SEQB_IRQHandler: - ldr r0,=ADC0_SEQB_DriverIRQHandler - bx r0 - .size ADC0_SEQB_IRQHandler, . - ADC0_SEQB_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_THCMP_IRQHandler - .type ADC0_THCMP_IRQHandler, %function -ADC0_THCMP_IRQHandler: - ldr r0,=ADC0_THCMP_DriverIRQHandler - bx r0 - .size ADC0_THCMP_IRQHandler, . - ADC0_THCMP_IRQHandler - - .align 1 - .thumb_func - .weak DMIC0_IRQHandler - .type DMIC0_IRQHandler, %function -DMIC0_IRQHandler: - ldr r0,=DMIC0_DriverIRQHandler - bx r0 - .size DMIC0_IRQHandler, . - DMIC0_IRQHandler - - .align 1 - .thumb_func - .weak HWVAD0_IRQHandler - .type HWVAD0_IRQHandler, %function -HWVAD0_IRQHandler: - ldr r0,=HWVAD0_DriverIRQHandler - bx r0 - .size HWVAD0_IRQHandler, . - HWVAD0_IRQHandler - - .align 1 - .thumb_func - .weak USB0_NEEDCLK_IRQHandler - .type USB0_NEEDCLK_IRQHandler, %function -USB0_NEEDCLK_IRQHandler: - ldr r0,=USB0_NEEDCLK_DriverIRQHandler - bx r0 - .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak USB0_IRQHandler - .type USB0_IRQHandler, %function -USB0_IRQHandler: - ldr r0,=USB0_DriverIRQHandler - bx r0 - .size USB0_IRQHandler, . - USB0_IRQHandler - - .align 1 - .thumb_func - .weak RTC_IRQHandler - .type RTC_IRQHandler, %function -RTC_IRQHandler: - ldr r0,=RTC_DriverIRQHandler - bx r0 - .size RTC_IRQHandler, . - RTC_IRQHandler - - .align 1 - .thumb_func - .weak IOH_IRQHandler - .type IOH_IRQHandler, %function -IOH_IRQHandler: - ldr r0,=IOH_DriverIRQHandler - bx r0 - .size IOH_IRQHandler, . - IOH_IRQHandler - - .align 1 - .thumb_func - .weak MAILBOX_IRQHandler - .type MAILBOX_IRQHandler, %function -MAILBOX_IRQHandler: - ldr r0,=MAILBOX_DriverIRQHandler - bx r0 - .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler - - - .align 1 - .thumb_func - .weak PIN_INT4_IRQHandler - .type PIN_INT4_IRQHandler, %function -PIN_INT4_IRQHandler: - ldr r0,=PIN_INT4_DriverIRQHandler - bx r0 - .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT5_IRQHandler - .type PIN_INT5_IRQHandler, %function -PIN_INT5_IRQHandler: - ldr r0,=PIN_INT5_DriverIRQHandler - bx r0 - .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT6_IRQHandler - .type PIN_INT6_IRQHandler, %function -PIN_INT6_IRQHandler: - ldr r0,=PIN_INT6_DriverIRQHandler - bx r0 - .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT7_IRQHandler - .type PIN_INT7_IRQHandler, %function -PIN_INT7_IRQHandler: - ldr r0,=PIN_INT7_DriverIRQHandler - bx r0 - .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler - - - .align 1 - .thumb_func - .weak CTIMER2_IRQHandler - .type CTIMER2_IRQHandler, %function -CTIMER2_IRQHandler: - ldr r0,=CTIMER2_DriverIRQHandler - bx r0 - .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER4_IRQHandler - .type CTIMER4_IRQHandler, %function -CTIMER4_IRQHandler: - ldr r0,=CTIMER4_DriverIRQHandler - bx r0 - .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler - - - .align 1 - .thumb_func - .weak SPIFI0_IRQHandler - .type SPIFI0_IRQHandler, %function -SPIFI0_IRQHandler: - ldr r0,=SPIFI0_DriverIRQHandler - bx r0 - .size SPIFI0_IRQHandler, . - SPIFI0_IRQHandler -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm - -/* Exception Handlers */ - def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect */ - def_irq_handler DMA0_DriverIRQHandler /* DMA controller */ - def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */ - def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */ - def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */ - def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */ - def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */ - def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */ - def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */ - def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */ - def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C) */ - def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C) */ - def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C) */ - def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C) */ - def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C) */ - def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C) */ - def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S) */ - def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S) */ - def_irq_handler ADC0_SEQA_DriverIRQHandler /* ADC0 sequence A completion. */ - def_irq_handler ADC0_SEQB_DriverIRQHandler /* ADC0 sequence B completion. */ - def_irq_handler ADC0_THCMP_DriverIRQHandler /* ADC0 threshold compare and error. */ - def_irq_handler DMIC0_DriverIRQHandler /* Digital microphone and DMIC subsystem */ - def_irq_handler HWVAD0_DriverIRQHandler /* Hardware Voice Activity Detector */ - def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */ - def_irq_handler USB0_DriverIRQHandler /* USB device */ - def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */ - def_irq_handler IOH_DriverIRQHandler /* IOH */ - def_irq_handler MAILBOX_DriverIRQHandler /* Mailbox interrupt (present on selected devices) */ - def_irq_handler PIN_INT4_DriverIRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - def_irq_handler PIN_INT5_DriverIRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - def_irq_handler PIN_INT6_DriverIRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - def_irq_handler PIN_INT7_DriverIRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - def_irq_handler CTIMER2_DriverIRQHandler /* Standard counter/timer CTIMER2 */ - def_irq_handler CTIMER4_DriverIRQHandler /* Standard counter/timer CTIMER4 */ - def_irq_handler SPIFI0_DriverIRQHandler /* SPI flash interface */ - - .end diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus.icf b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus.icf deleted file mode 100644 index 5ba71403bc3..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus.icf +++ /dev/null @@ -1,124 +0,0 @@ -/* -** ################################################################### -** Processors: LPC54114J256BD64_M0P -** LPC54114J256UK49_M0P -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 -** Version: rev. 1.0, 2016-04-29 -** Build: b161227 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** The Clear BSD License -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted (subject to the limitations in the disclaimer below) provided -** that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -define symbol m_interrupts_start = 0x20010000; -define symbol m_interrupts_end = 0x200100BF; - -define symbol m_text_start = 0x200100C0; -define symbol m_text_end = 0x2001FFFF; - -if (isdefinedsymbol(__use_shmem__)) { -define symbol m_data_start = 0x20020000; -define symbol m_data_end = 0x200267FF; - -define exported symbol rpmsg_sh_mem_start = 0x20026800; -define exported symbol rpmsg_sh_mem_end = 0x20027FFF; -} else { -define symbol m_data_start = 0x20020000; -define symbol m_data_end = 0x20027FFF; -} - -define symbol m_sramx_start = 0x04000000; -define symbol m_sramx_end = 0x04007FFF; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0800; -} - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region SRAMX_region = mem:[from m_sramx_start to m_sramx_end]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; - -if (isdefinedsymbol(__use_shmem__)) { -define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; -} - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - -initialize by copy { readwrite }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - // Required in a multi-threaded application - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -do not initialize { section .noinit }; -if (isdefinedsymbol(__use_shmem__)) { -do not initialize { section rpmsg_sh_mem_section }; -} - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in SRAMX_region { section sramx }; -place in CSTACK_region { block CSTACK }; -if (isdefinedsymbol(__use_shmem__)) { -place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus_ram.icf b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus_ram.icf deleted file mode 100644 index 59cc28d9dee..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus_ram.icf +++ /dev/null @@ -1,120 +0,0 @@ -/* -** ################################################################### -** Processors: LPC54114J256BD64_M0P -** LPC54114J256UK49_M0P -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 -** Version: rev. 1.0, 2016-04-29 -** Build: b161227 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** The Clear BSD License -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted (subject to the limitations in the disclaimer below) provided -** that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -define symbol m_interrupts_start = 0x20010000; -define symbol m_interrupts_end = 0x200100BF; - -define symbol m_text_start = 0x200100C0; -define symbol m_text_end = 0x2001FFFF; - -if (isdefinedsymbol(__use_shmem__)) { -define exported symbol rpmsg_sh_mem_start = 0x20026800; -define exported symbol rpmsg_sh_mem_end = 0x20027FFF; -define symbol m_data_start = 0x20020000; -define symbol m_data_end = 0x200267FF; -} else { -define symbol m_data_start = 0x20020000; -define symbol m_data_end = 0x20027FFF; -} - -define symbol m_sramx_start = 0x04000000; -define symbol m_sramx_end = 0x04007FFF; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0800; -} - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region SRAMX_region = mem:[from m_sramx_start to m_sramx_end]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -if (isdefinedsymbol(__use_shmem__)) { -define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; -} - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - -initialize by copy { readwrite }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - // Required in a multi-threaded application - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -do not initialize { section .noinit }; -do not initialize { section rpmsg_sh_mem_section }; - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in SRAMX_region { section sramx }; -place in CSTACK_region { block CSTACK }; -if (isdefinedsymbol(__use_shmem__)) { -place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm4_ram.icf b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm4_ram.icf deleted file mode 100644 index b3385275000..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm4_ram.icf +++ /dev/null @@ -1,99 +0,0 @@ -/* -** ################################################################### -** Processors: LPC54114J256BD64_M4 -** LPC54114J256UK49_M4 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 -** Version: rev. 1.0, 2016-04-29 -** Build: b161227 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** The Clear BSD License -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted (subject to the limitations in the disclaimer below) provided -** that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol m_interrupts_start = 0x20000000; -define symbol m_interrupts_end = 0x200000DF; - -define symbol m_text_start = 0x200000E0; -define symbol m_text_end = 0x20020000; - - -define symbol m_data_start = 0x20020000; -define symbol m_data_end = 0x20008000; - - -define symbol m_stack_start = 0x04000000; -define symbol m_stack_end = 0x04007FFF; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0800; -} - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end]; -define region CSTACK_region = mem:[from m_stack_start to m_stack_end]; - - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/SConscript b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/SConscript deleted file mode 100644 index d89e9d26996..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/SConscript +++ /dev/null @@ -1,10 +0,0 @@ -from building import * - -cwd = GetCurrentDir() -src = Split(''' -startup_LPC54114_cm4.s -''') - -group = DefineGroup('Libraries', src, depend = [''], LIBS=['iar_lib_power'], LIBPATH=[cwd]) - -Return('group') diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/iar_lib_power.a b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/iar_lib_power.a deleted file mode 100644 index c0a587fb0e2..00000000000 Binary files a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/iar_lib_power.a and /dev/null differ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/iar_lib_power_m0.a b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/iar_lib_power_m0.a deleted file mode 100644 index 481efdbc1bf..00000000000 Binary files a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/iar_lib_power_m0.a and /dev/null differ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/startup_LPC54114_cm0plus.s b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/startup_LPC54114_cm0plus.s deleted file mode 100644 index 594b30c6794..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/startup_LPC54114_cm0plus.s +++ /dev/null @@ -1,473 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC54114_cm0plus.s -; * @purpose: CMSIS Cortex-M0 Core Device Startup File -; * LPC54114_cm0plus -; * @version: 1.0 -; * @date: 2016-4-29 -; *---------------------------------------------------------------------------- -; * -; * The Clear BSD License -; * Copyright 1997 - 2016 Freescale Semiconductor. -; * Copyright 2016 - 2017 NXP -; * -; * All rights reserved. -; * -; Redistribution and use in source and binary forms, with or without modification, -; are permitted (subject to the limitations in the disclaimer below) provided -; that the following conditions are met: -; -; o Redistributions of source code must retain the above copyright notice, this list -; of conditions and the following disclaimer. -; -; o Redistributions in binary form must reproduce the above copyright notice, this -; list of conditions and the following disclaimer in the documentation and/or -; other materials provided with the distribution. -; -; o Neither the name of the copyright holder nor the names of its -; contributors may be used to endorse or promote products derived from this -; software without specific prior written permission. -; -; NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S' PATENT RIGHTS ARE GRANTED BY THIS LICENSE. -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD 0 - DCD 0 - DCD 0 -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD 0 - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect - DCD DMA0_IRQHandler ; DMA controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S) - DCD ADC0_SEQA_IRQHandler ; ADC0 sequence A completion. - DCD ADC0_SEQB_IRQHandler ; ADC0 sequence B completion. - DCD ADC0_THCMP_IRQHandler ; ADC0 threshold compare and error. - DCD DMIC0_IRQHandler ; Digital microphone and DMIC subsystem - DCD HWVAD0_IRQHandler ; Hardware Voice Activity Detector - DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt - DCD USB0_IRQHandler ; USB device - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD IOH_IRQHandler ; IOH - DCD MAILBOX_IRQHandler ; Mailbox interrupt (present on selected devices) -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - -#if !defined(SLAVEBOOT) - DATA -cpu_id EQU 0xE000ED00 ; CPUID Base Register (System control block register) -cpu_ctrl EQU 0x40000800 -coproc_boot EQU 0x40000804 -coproc_stack EQU 0x40000808 -rel_vals - DC32 cpu_id, cpu_ctrl, coproc_boot, coproc_stack - DC16 0xFFF, 0xC24 -#endif - - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -; Reset Handler - shared for both cores -Reset_Handler - -#if !defined(SLAVEBOOT) -; Both the M0+ and M4 core come via this shared startup code, - ; but the M0+ and M4 core have different vector tables. - ; Determine if the core executing this code is the master or - ; the slave and handle each core state individually. -shared_boot_entry - LDR r6, =rel_vals - MOVS r4, #0 ; Flag for slave core (0) - MOVS r5, #1 - - ; Determine which core (M0+ or M4) this code is running on - ; r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) -get_current_core_id - LDR r0, [r6, #0] - LDR r1, [r0] ; r1 = CPU ID status - LSRS r1, r1, #4 ; Right justify 12 CPU ID bits - LDRH r2, [r6, #16] ; Mask for CPU ID bits - ANDS r2, r1, r2 ; r2 = ARM COrtex CPU ID - LDRH r3, [r6, #18] ; Mask for CPU ID bits - CMP r3, r2 ; Core ID matches M4 identifier - BNE get_master_status - MOV r4, r5 ; Set flag for master core (1) - - ; Determine if M4 core is the master or slave - ; r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) -get_master_status - LDR r0, [r6, #4] - LDR r3, [r0] ; r3 = SYSCON co-processor CPU control status - ANDS r3, r3, r5 ; r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) - - ; Select boot based on selected master core and core ID -select_boot - EORS r3, r3, r4 ; r4 = (Bit 0: 0 = master, 1 = slave) - BNE slave_boot - B normal_boot - - ; Slave boot -slave_boot - LDR r0, [r6, #8] - LDR r2, [r0] ; r1 = SYSCON co-processor boot address - CMP r2, #0 ; Slave boot address = 0 (not set up)? - BEQ cpu_sleep - LDR r0, [r6, #12] - LDR r1, [r0] ; r5 = SYSCON co-processor stack address - MOV sp, r1 ; Update slave CPU stack pointer - ; Be sure to update VTOR for the slave MCU to point to the - ; slave vector table in boot memory - BX r2 ; Jump to slave boot address - - ; Slave isn't yet setup for system boot from the master - ; so sleep until the master sets it up and then reboots it -cpu_sleep - MOV sp, r5 ; Will force exception if something happens -cpu_sleep_wfi - WFI ; Sleep forever until master reboots - B cpu_sleep_wfi -#endif ; defined(SLAVEBOOT) - - ; Normal boot for master/slave -normal_boot - LDR r0, =SystemInit - BLX r0 - LDR r0, =__iar_program_start - BX r0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK WDT_BOD_IRQHandler - PUBWEAK WDT_BOD_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -WDT_BOD_IRQHandler - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler - LDR R0, =DMA0_DriverIRQHandler - BX R0 - PUBWEAK GINT0_IRQHandler - PUBWEAK GINT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT0_IRQHandler - LDR R0, =GINT0_DriverIRQHandler - BX R0 - PUBWEAK GINT1_IRQHandler - PUBWEAK GINT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT1_IRQHandler - LDR R0, =GINT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT0_IRQHandler - PUBWEAK PIN_INT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT0_IRQHandler - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT1_IRQHandler - PUBWEAK PIN_INT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT1_IRQHandler - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT2_IRQHandler - PUBWEAK PIN_INT2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT2_IRQHandler - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT3_IRQHandler - PUBWEAK PIN_INT3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT3_IRQHandler - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - PUBWEAK UTICK0_IRQHandler - PUBWEAK UTICK0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UTICK0_IRQHandler - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - PUBWEAK MRT0_IRQHandler - PUBWEAK MRT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -MRT0_IRQHandler - LDR R0, =MRT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER0_IRQHandler - PUBWEAK CTIMER0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER0_IRQHandler - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER1_IRQHandler - PUBWEAK CTIMER1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER1_IRQHandler - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - PUBWEAK SCT0_IRQHandler - PUBWEAK SCT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SCT0_IRQHandler - LDR R0, =SCT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER3_IRQHandler - PUBWEAK CTIMER3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER3_IRQHandler - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM0_IRQHandler - PUBWEAK FLEXCOMM0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM0_IRQHandler - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM1_IRQHandler - PUBWEAK FLEXCOMM1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM1_IRQHandler - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM2_IRQHandler - PUBWEAK FLEXCOMM2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM2_IRQHandler - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM3_IRQHandler - PUBWEAK FLEXCOMM3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM3_IRQHandler - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM4_IRQHandler - PUBWEAK FLEXCOMM4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM4_IRQHandler - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM5_IRQHandler - PUBWEAK FLEXCOMM5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM5_IRQHandler - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM6_IRQHandler - PUBWEAK FLEXCOMM6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM6_IRQHandler - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM7_IRQHandler - PUBWEAK FLEXCOMM7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM7_IRQHandler - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - PUBWEAK ADC0_SEQA_IRQHandler - PUBWEAK ADC0_SEQA_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_SEQA_IRQHandler - LDR R0, =ADC0_SEQA_DriverIRQHandler - BX R0 - PUBWEAK ADC0_SEQB_IRQHandler - PUBWEAK ADC0_SEQB_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_SEQB_IRQHandler - LDR R0, =ADC0_SEQB_DriverIRQHandler - BX R0 - PUBWEAK ADC0_THCMP_IRQHandler - PUBWEAK ADC0_THCMP_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_THCMP_IRQHandler - LDR R0, =ADC0_THCMP_DriverIRQHandler - BX R0 - PUBWEAK DMIC0_IRQHandler - PUBWEAK DMIC0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMIC0_IRQHandler - LDR R0, =DMIC0_DriverIRQHandler - BX R0 - PUBWEAK HWVAD0_IRQHandler - PUBWEAK HWVAD0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -HWVAD0_IRQHandler - LDR R0, =HWVAD0_DriverIRQHandler - BX R0 - PUBWEAK USB0_NEEDCLK_IRQHandler - PUBWEAK USB0_NEEDCLK_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_NEEDCLK_IRQHandler - LDR R0, =USB0_NEEDCLK_DriverIRQHandler - BX R0 - PUBWEAK USB0_IRQHandler - PUBWEAK USB0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_IRQHandler - LDR R0, =USB0_DriverIRQHandler - BX R0 - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -RTC_IRQHandler - LDR R0, =RTC_DriverIRQHandler - BX R0 - PUBWEAK IOH_IRQHandler - PUBWEAK IOH_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -IOH_IRQHandler - LDR R0, =IOH_DriverIRQHandler - BX R0 - PUBWEAK MAILBOX_IRQHandler - PUBWEAK MAILBOX_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -MAILBOX_IRQHandler - LDR R0, =MAILBOX_DriverIRQHandler - BX R0 -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_SEQA_DriverIRQHandler -ADC0_SEQB_DriverIRQHandler -ADC0_THCMP_DriverIRQHandler -DMIC0_DriverIRQHandler -HWVAD0_DriverIRQHandler -USB0_NEEDCLK_DriverIRQHandler -USB0_DriverIRQHandler -RTC_DriverIRQHandler -IOH_DriverIRQHandler -MAILBOX_DriverIRQHandler -DefaultISR - B . - - END diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/startup_LPC54114_cm4.s b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/startup_LPC54114_cm4.s deleted file mode 100644 index 9ef5d34e866..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/startup_LPC54114_cm4.s +++ /dev/null @@ -1,571 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC54114_cm4.s -; * @purpose: CMSIS Cortex-M4 Core Device Startup File -; * LPC54114_cm4 -; * @version: 1.0 -; * @date: 2016-4-29 -; *---------------------------------------------------------------------------- -; * -; * The Clear BSD License -; * Copyright 1997 - 2016 Freescale Semiconductor. -; * Copyright 2016 - 2017 NXP -; * -; * All rights reserved. -; * -; Redistribution and use in source and binary forms, with or without modification, -; are permitted (subject to the limitations in the disclaimer below) provided -; that the following conditions are met: -; -; o Redistributions of source code must retain the above copyright notice, this list -; of conditions and the following disclaimer. -; -; o Redistributions in binary form must reproduce the above copyright notice, this -; list of conditions and the following disclaimer in the documentation and/or -; other materials provided with the distribution. -; -; o Neither the name of the copyright holder nor the names of its -; contributors may be used to endorse or promote products derived from this -; software without specific prior written permission. -; -; NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S' PATENT RIGHTS ARE GRANTED BY THIS LICENSE. -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect - DCD DMA0_IRQHandler ; DMA controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S) - DCD ADC0_SEQA_IRQHandler ; ADC0 sequence A completion. - DCD ADC0_SEQB_IRQHandler ; ADC0 sequence B completion. - DCD ADC0_THCMP_IRQHandler ; ADC0 threshold compare and error. - DCD DMIC0_IRQHandler ; Digital microphone and DMIC subsystem - DCD HWVAD0_IRQHandler ; Hardware Voice Activity Detector - DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt - DCD USB0_IRQHandler ; USB device - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD IOH_IRQHandler ; IOH - DCD MAILBOX_IRQHandler ; Mailbox interrupt (present on selected devices) - DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int - DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int - DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int - DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int - DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 - DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 - DCD Reserved54_IRQHandler ; Reserved interrupt - DCD SPIFI0_IRQHandler ; SPI flash interface -__Vectors_End - -; Code Read Protection Level (CRP) -; <0xFFFFFFFF=> Disabled -; <0x4E697370=> NO_ISP -; <0x12345678=> CRP1 -; <0x87654321=> CRP2 -; <0x43218765=> CRP3 - -#if !defined NO_CRP - SECTION .crp:CODE -__CRP - DCD 0xFFFFFFFF -__CRP_End -#endif - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - SECTION .intvec:CODE:NOROOT(2) -#if !defined(SLAVEBOOT) - DATA -cpu_id EQU 0xE000ED00 ; CPUID Base Register (System control block register) -cpu_ctrl EQU 0x40000800 -coproc_boot EQU 0x40000804 -coproc_stack EQU 0x40000808 -rel_vals - DC32 cpu_id, cpu_ctrl, coproc_boot, coproc_stack - DC16 0xFFF, 0xC24 -#endif - - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -; Reset Handler - shared for both cores -Reset_Handler - -#if !defined(SLAVEBOOT) -; Both the M0+ and M4 core come via this shared startup code, - ; but the M0+ and M4 core have different vector tables. - ; Determine if the core executing this code is the master or - ; the slave and handle each core state individually. -shared_boot_entry - LDR r6, =rel_vals - MOVS r4, #0 ; Flag for slave core (0) - MOVS r5, #1 - - ; Determine which core (M0+ or M4) this code is running on - ; r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) -get_current_core_id - LDR r0, [r6, #0] - LDR r1, [r0] ; r1 = CPU ID status - LSRS r1, r1, #4 ; Right justify 12 CPU ID bits - LDRH r2, [r6, #16] ; Mask for CPU ID bits - ANDS r2, r1, r2 ; r2 = ARM COrtex CPU ID - LDRH r3, [r6, #18] ; Mask for CPU ID bits - CMP r3, r2 ; Core ID matches M4 identifier - BNE get_master_status - MOV r4, r5 ; Set flag for master core (1) - - ; Determine if M4 core is the master or slave - ; r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) -get_master_status - LDR r0, [r6, #4] - LDR r3, [r0] ; r3 = SYSCON co-processor CPU control status - ANDS r3, r3, r5 ; r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) - - ; Select boot based on selected master core and core ID -select_boot - EORS r3, r3, r4 ; r4 = (Bit 0: 0 = master, 1 = slave) - BNE slave_boot - B normal_boot - - ; Slave boot -slave_boot - LDR r0, [r6, #8] - LDR r2, [r0] ; r1 = SYSCON co-processor boot address - CMP r2, #0 ; Slave boot address = 0 (not set up)? - BEQ cpu_sleep - LDR r0, [r6, #12] - LDR r1, [r0] ; r5 = SYSCON co-processor stack address - MOV sp, r1 ; Update slave CPU stack pointer - ; Be sure to update VTOR for the slave MCU to point to the - ; slave vector table in boot memory - BX r2 ; Jump to slave boot address - - ; Slave isn't yet setup for system boot from the master - ; so sleep until the master sets it up and then reboots it -cpu_sleep - MOV sp, r5 ; Will force exception if something happens -cpu_sleep_wfi - WFI ; Sleep forever until master reboots - B cpu_sleep_wfi -#endif ; defined(SLAVEBOOT) - - ; Normal boot for master/slave -normal_boot - LDR r0, =SystemInit - BLX r0 - LDR r0, =__iar_program_start - BX r0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK WDT_BOD_IRQHandler - PUBWEAK WDT_BOD_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -WDT_BOD_IRQHandler - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler - LDR R0, =DMA0_DriverIRQHandler - BX R0 - PUBWEAK GINT0_IRQHandler - PUBWEAK GINT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT0_IRQHandler - LDR R0, =GINT0_DriverIRQHandler - BX R0 - PUBWEAK GINT1_IRQHandler - PUBWEAK GINT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT1_IRQHandler - LDR R0, =GINT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT0_IRQHandler - PUBWEAK PIN_INT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT0_IRQHandler - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT1_IRQHandler - PUBWEAK PIN_INT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT1_IRQHandler - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT2_IRQHandler - PUBWEAK PIN_INT2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT2_IRQHandler - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT3_IRQHandler - PUBWEAK PIN_INT3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT3_IRQHandler - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - PUBWEAK UTICK0_IRQHandler - PUBWEAK UTICK0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UTICK0_IRQHandler - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - PUBWEAK MRT0_IRQHandler - PUBWEAK MRT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -MRT0_IRQHandler - LDR R0, =MRT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER0_IRQHandler - PUBWEAK CTIMER0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER0_IRQHandler - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER1_IRQHandler - PUBWEAK CTIMER1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER1_IRQHandler - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - PUBWEAK SCT0_IRQHandler - PUBWEAK SCT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SCT0_IRQHandler - LDR R0, =SCT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER3_IRQHandler - PUBWEAK CTIMER3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER3_IRQHandler - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM0_IRQHandler - PUBWEAK FLEXCOMM0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM0_IRQHandler - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM1_IRQHandler - PUBWEAK FLEXCOMM1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM1_IRQHandler - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM2_IRQHandler - PUBWEAK FLEXCOMM2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM2_IRQHandler - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM3_IRQHandler - PUBWEAK FLEXCOMM3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM3_IRQHandler - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM4_IRQHandler - PUBWEAK FLEXCOMM4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM4_IRQHandler - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM5_IRQHandler - PUBWEAK FLEXCOMM5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM5_IRQHandler - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM6_IRQHandler - PUBWEAK FLEXCOMM6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM6_IRQHandler - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM7_IRQHandler - PUBWEAK FLEXCOMM7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM7_IRQHandler - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - PUBWEAK ADC0_SEQA_IRQHandler - PUBWEAK ADC0_SEQA_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_SEQA_IRQHandler - LDR R0, =ADC0_SEQA_DriverIRQHandler - BX R0 - PUBWEAK ADC0_SEQB_IRQHandler - PUBWEAK ADC0_SEQB_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_SEQB_IRQHandler - LDR R0, =ADC0_SEQB_DriverIRQHandler - BX R0 - PUBWEAK ADC0_THCMP_IRQHandler - PUBWEAK ADC0_THCMP_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_THCMP_IRQHandler - LDR R0, =ADC0_THCMP_DriverIRQHandler - BX R0 - PUBWEAK DMIC0_IRQHandler - PUBWEAK DMIC0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMIC0_IRQHandler - LDR R0, =DMIC0_DriverIRQHandler - BX R0 - PUBWEAK HWVAD0_IRQHandler - PUBWEAK HWVAD0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -HWVAD0_IRQHandler - LDR R0, =HWVAD0_DriverIRQHandler - BX R0 - PUBWEAK USB0_NEEDCLK_IRQHandler - PUBWEAK USB0_NEEDCLK_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_NEEDCLK_IRQHandler - LDR R0, =USB0_NEEDCLK_DriverIRQHandler - BX R0 - PUBWEAK USB0_IRQHandler - PUBWEAK USB0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_IRQHandler - LDR R0, =USB0_DriverIRQHandler - BX R0 - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -RTC_IRQHandler - LDR R0, =RTC_DriverIRQHandler - BX R0 - PUBWEAK IOH_IRQHandler - PUBWEAK IOH_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -IOH_IRQHandler - LDR R0, =IOH_DriverIRQHandler - BX R0 - PUBWEAK MAILBOX_IRQHandler - PUBWEAK MAILBOX_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -MAILBOX_IRQHandler - LDR R0, =MAILBOX_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT4_IRQHandler - PUBWEAK PIN_INT4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT4_IRQHandler - LDR R0, =PIN_INT4_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT5_IRQHandler - PUBWEAK PIN_INT5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT5_IRQHandler - LDR R0, =PIN_INT5_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT6_IRQHandler - PUBWEAK PIN_INT6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT6_IRQHandler - LDR R0, =PIN_INT6_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT7_IRQHandler - PUBWEAK PIN_INT7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT7_IRQHandler - LDR R0, =PIN_INT7_DriverIRQHandler - BX R0 - PUBWEAK CTIMER2_IRQHandler - PUBWEAK CTIMER2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER2_IRQHandler - LDR R0, =CTIMER2_DriverIRQHandler - BX R0 - PUBWEAK CTIMER4_IRQHandler - PUBWEAK CTIMER4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER4_IRQHandler - LDR R0, =CTIMER4_DriverIRQHandler - BX R0 - PUBWEAK Reserved54_IRQHandler - PUBWEAK Reserved54_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved54_IRQHandler - LDR R0, =Reserved54_DriverIRQHandler - BX R0 - PUBWEAK SPIFI0_IRQHandler - PUBWEAK SPIFI0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPIFI0_IRQHandler - LDR R0, =SPIFI0_DriverIRQHandler - BX R0 -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_SEQA_DriverIRQHandler -ADC0_SEQB_DriverIRQHandler -ADC0_THCMP_DriverIRQHandler -DMIC0_DriverIRQHandler -HWVAD0_DriverIRQHandler -USB0_NEEDCLK_DriverIRQHandler -USB0_DriverIRQHandler -RTC_DriverIRQHandler -IOH_DriverIRQHandler -MAILBOX_DriverIRQHandler -PIN_INT4_DriverIRQHandler -PIN_INT5_DriverIRQHandler -PIN_INT6_DriverIRQHandler -PIN_INT7_DriverIRQHandler -CTIMER2_DriverIRQHandler -CTIMER4_DriverIRQHandler -Reserved54_DriverIRQHandler -SPIFI0_DriverIRQHandler -DefaultISR - B . - - END diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/board.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/board.c deleted file mode 100644 index 25777b8729c..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/board.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include "fsl_common.h" -#include "clock_config.h" -#include "board.h" -#include "fsl_debug_console.h" - -#ifdef SDK_PRIMARY_CORE -/* Address of RAM, where the image for core1 should be copied */ -#define CORE1_BOOT_ADDRESS (void *)0x20010000 - -#if defined(__CC_ARM) -extern uint32_t Image$$CORE1_REGION$$Base; -extern uint32_t Image$$CORE1_REGION$$Length; -#define CORE1_IMAGE_START &Image$$CORE1_REGION$$Base -#elif defined(__ICCARM__) -extern unsigned char core1_image_start[]; -#define CORE1_IMAGE_START core1_image_start -#endif -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* Clock rate on the CLKIN pin */ -const uint32_t ExtClockIn = BOARD_EXTCLKINRATE; - -/******************************************************************************* - * Code - ******************************************************************************/ -/* Initialize debug console. */ -status_t BOARD_InitDebugConsole(void) -{ - status_t result; - - /* attach 12 MHz clock to FLEXCOMM0 (debug console) */ - CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0); - - RESET_PeripheralReset(BOARD_DEBUG_UART_RST); - result = DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM, - BOARD_DEBUG_UART_CLK_FREQ); - assert(kStatus_Success == result); - return result; -} - -#ifdef SDK_PRIMARY_CORE -/* Start the secondary core. */ -void BOARD_StartSecondaryCore(void) -{ -/* Calculate size of the secondary core image - not required on MCUXpresso. MCUXpresso copies the image to RAM during - * startup - * automatically */ -#if (defined(__CC_ARM) || defined(__ICCARM__)) -#if defined(__CC_ARM) - uint32_t core1_image_size = (uint32_t)&Image$$CORE1_REGION$$Length; -#elif defined(__ICCARM__) -#pragma section = "__sec_core" - uint32_t core1_image_size = (uint32_t)__section_end("__sec_core") - (uint32_t)&core1_image_start; -#endif - - /* Copy core1 application from FLASH to RAM. Primary core code is executed from FLASH, Secondary from RAM - * for maximal effectivity.*/ - memcpy(CORE1_BOOT_ADDRESS, (void *)CORE1_IMAGE_START, core1_image_size); -#endif - /* Boot source for Core 1 from RAM */ - SYSCON->CPBOOT = SYSCON_CPBOOT_BOOTADDR(*(uint32_t *)((uint8_t *)CORE1_BOOT_ADDRESS + 0x4)); - SYSCON->CPSTACK = SYSCON_CPSTACK_STACKADDR(*(uint32_t *)CORE1_BOOT_ADDRESS); - - uint32_t temp = SYSCON->CPUCTRL; - temp |= 0xc0c48000U; - SYSCON->CPUCTRL = temp | SYSCON_CPUCTRL_CM0RSTEN_MASK | SYSCON_CPUCTRL_CM0CLKEN_MASK; - SYSCON->CPUCTRL = (temp | SYSCON_CPUCTRL_CM0CLKEN_MASK) & (~SYSCON_CPUCTRL_CM0RSTEN_MASK); -} -#endif diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/board.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/board.h deleted file mode 100644 index 69c03d0a4c8..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/board.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#include "clock_config.h" -#include "fsl_common.h" -#include "fsl_gpio.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief The board name */ -#define BOARD_NAME "LPCXPRESSO54114" - -#define BOARD_EXTCLKINRATE (0) - -/*! @brief The UART to use for debug messages. */ -#define BOARD_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM -#define BOARD_DEBUG_UART_BASEADDR (uint32_t) USART0 -#define BOARD_DEBUG_UART_INSTANCE 0U -#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetFreq(kCLOCK_Flexcomm0) -#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0 -#define BOARD_DEBUG_UART_RST kFC0_RST_SHIFT_RSTn - -#define BOARD_DEBUG_SPI_CLK_FREQ 12000000 - -#ifndef BOARD_DEBUG_UART_BAUDRATE -#define BOARD_DEBUG_UART_BAUDRATE 115200 -#endif /* BOARD_DEBUG_UART_BAUDRATE */ - -#ifndef BOARD_LED_RED_GPIO -#define BOARD_LED_RED_GPIO GPIO -#endif -#define BOARD_LED_RED_GPIO_PORT 0U -#ifndef BOARD_LED_RED_GPIO_PIN -#define BOARD_LED_RED_GPIO_PIN 29U -#endif -#ifndef BOARD_LED_GREEN_GPIO -#define BOARD_LED_GREEN_GPIO GPIO -#endif -#define BOARD_LED_GREEN_GPIO_PORT 1U -#ifndef BOARD_LED_GREEN_GPIO_PIN -#define BOARD_LED_GREEN_GPIO_PIN 10U -#endif -#ifndef BOARD_LED_BLUE_GPIO -#define BOARD_LED_BLUE_GPIO GPIO -#endif -#define BOARD_LED_BLUE_GPIO_PORT 1U -#ifndef BOARD_LED_BLUE_GPIO_PIN -#define BOARD_LED_BLUE_GPIO_PIN 9U -#endif - -/* Board led color mapping */ -#define LOGIC_LED_ON 0U -#define LOGIC_LED_OFF 1U - -#define LED_RED_INIT(output) \ - GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, \ - &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_RED */ -#define LED_RED_ON() \ - GPIO_PortClear(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \ - 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED_RED */ -#define LED_RED_OFF() \ - GPIO_PortSet(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \ - 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED_RED */ -#define LED_RED_TOGGLE() \ - GPIO_PortToggle(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \ - 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED */ - -#define LED_GREEN_INIT(output) \ - GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \ - &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_GREEN */ -#define LED_GREEN_ON() \ - GPIO_PortClear(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \ - 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED_GREEN */ -#define LED_GREEN_OFF() \ - GPIO_PortSet(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \ - 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED_GREEN */ -#define LED_GREEN_TOGGLE() \ - GPIO_PortToggle(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \ - 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */ - -#define LED_BLUE_INIT(output) \ - GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, \ - &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_BLUE */ -#define LED_BLUE_ON() \ - GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \ - 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED_BLUE */ -#define LED_BLUE_OFF() \ - GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \ - 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED_BLUE */ -#define LED_BLUE_TOGGLE() \ - GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \ - 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/******************************************************************************* - * API - ******************************************************************************/ - -status_t BOARD_InitDebugConsole(void); - -#ifdef SDK_PRIMARY_CORE -void BOARD_StartSecondaryCore(void); -#endif - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -#endif /* _BOARD_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/clock_config.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/clock_config.c deleted file mode 100644 index 8a0b6bce73b..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/clock_config.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * How to set up clock using clock driver functions: - * - * 1. Setup clock sources. - * - * 2. Setup voltage for the fastest of the clock outputs - * - * 3. Set up wait states of the flash. - * - * 4. Set up all dividers. - * - * 5. Set up all selectors to provide selected clocks. - */ - -/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** -!!ClocksProfile -product: Clocks v1.0 -processor: LPC54114J256 -mcu_data: ksdk2_0 -processor_version: 1.1.0 -board: LPCXpresso54114 - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ - -#include "fsl_power.h" -#include "fsl_clock.h" -#include "clock_config.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ -void BOARD_InitBootClocks(void) -{ - BOARD_BootClockFROHF48M(); -} - -/******************************************************************************* - ********************* Configuration BOARD_BootClockFRO12M *********************** - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** -!!Configuration -name: BOARD_BootClockFRO12M -outputs: -- {id: System_clock.outFreq, value: 12 MHz} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ - -/******************************************************************************* - * Variables for BOARD_BootClockFRO12M configuration - ******************************************************************************/ -/******************************************************************************* - * Code for BOARD_BootClockFRO12M configuration - ******************************************************************************/ -void BOARD_BootClockFRO12M(void) -{ - /*!< Set up the clock sources */ - /*!< Set up FRO */ - POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally - being below the voltage for current speed */ - CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ - POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ - CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ - - /*!< Set up dividers */ - CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ - - /*!< Set up clock selectors - Attach clocks to the peripheries */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ - /*!< Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; -} - -/******************************************************************************* - ********************** Configuration BOARD_BootClockFROHF48M *********************** - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** -!!Configuration -name: BOARD_BootClockFROHF48M -outputs: -- {id: System_clock.outFreq, value: 48 MHz} -settings: -- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ - -/******************************************************************************* - * Variables for BOARD_BootClockFROHF48M configuration - ******************************************************************************/ -/******************************************************************************* - * Code for BOARD_BootClockFROHF48M configuration - ******************************************************************************/ -void BOARD_BootClockFROHF48M(void) -{ - /*!< Set up the clock sources */ - /*!< Set up FRO */ - POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally - being below the voltage for current speed */ - POWER_SetVoltageForFreq(48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ - CLOCK_SetFLASHAccessCyclesForFreq(48000000U); /*!< Set FLASH wait states for core */ - - CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */ - - /*!< Set up dividers */ - CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ - - /*!< Set up clock selectors - Attach clocks to the peripheries */ - CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ - /*!< Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK; -} - -/******************************************************************************* - ********************* Configuration BOARD_BootClockFROHF96M ********************** - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** -!!Configuration -name: BOARD_BootClockFROHF96M -outputs: -- {id: System_clock.outFreq, value: 96 MHz} -settings: -- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf} -sources: -- {id: SYSCON.fro_hf.outFreq, value: 96 MHz} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ - -/******************************************************************************* - * Variables for BOARD_BootClockFROHF96M configuration - ******************************************************************************/ -/******************************************************************************* - * Code for BOARD_BootClockFROHF96M configuration - ******************************************************************************/ -void BOARD_BootClockFROHF96M(void) -{ - /*!< Set up the clock sources */ - /*!< Set up FRO */ - POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally - being below the voltage for current speed */ - POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ - CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ - - CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */ - - /*!< Set up dividers */ - CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ - - /*!< Set up clock selectors - Attach clocks to the peripheries */ - CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ - /*!< Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; -} - diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/clock_config.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/clock_config.h deleted file mode 100644 index 57f92cb504c..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/clock_config.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions -******************************************************************************/ - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#define BOARD_XTAL0_CLK_HZ 12000000U /*!< Board xtal0 frequency in Hz */ -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ -#define BOARD_BootClockRUN BOARD_BootClockFROHF48M - -/******************************************************************************* - ********************* Configuration BOARD_BootClockFRO12M *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockFRO12M configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ - -/******************************************************************************* - * API for BOARD_BootClockFRO12M configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockFRO12M(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockFROHF48M *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockFROHF48M configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */ - -/******************************************************************************* - * API for BOARD_BootClockFROHF48M configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockFROHF48M(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************* Configuration BOARD_BootClockFROHF96M ********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockFROHF96M configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ - -/******************************************************************************* - * API for BOARD_BootClockFROHF96M configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockFROHF96M(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ - diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/peripherals.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/peripherals.c deleted file mode 100644 index 06f66846262..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/peripherals.c +++ /dev/null @@ -1,16 +0,0 @@ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Peripherals v1.0 - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Included files - ******************************************************************************/ -#include "peripherals.h" - -/******************************************************************************* - * BOARD_InitBootPeripherals function - ******************************************************************************/ -void BOARD_InitBootPeripherals(void) -{ -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/peripherals.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/peripherals.h deleted file mode 100644 index ca5e934dac6..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/peripherals.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _PERIPHERALS_H_ -#define _PERIPHERALS_H_ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus. */ -/******************************************************************************* - * BOARD_InitBootPeripherals function - ******************************************************************************/ -void BOARD_InitBootPeripherals(void); - -#if defined(__cplusplus) -} -#endif /*_cplusplus. */ - -#endif /* _PERIPHERALS_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/pin_mux.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/pin_mux.c deleted file mode 100644 index fe309216aea..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/pin_mux.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* clang-format off */ -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Pins v3.0 -processor: LPC54114J256 -mcu_data: ksdk2_0 -processor_version: 0.0.13 - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ -/* clang-format on */ - -#include "fsl_common.h" -#include "fsl_iocon.h" -#include "pin_mux.h" - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitBootPins - * Description : Calls initialization functions. - * - * END ****************************************************************************************************************/ -void BOARD_InitBootPins(void) -{ - BOARD_InitPins(); -} - -/* clang-format off */ -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitPins: -- options: {callFromInitBoot: 'true', coreID: cm4, enableClock: 'true'} -- pin_list: - - {pin_num: '31', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI, pin_signal: PIO0_0/FC0_RXD_SDA_MOSI/FC3_CTS_SDA_SSEL0/CTIMER0_CAP0/SCT0_OUT3, mode: inactive, invert: disabled, - glitch_filter: disabled, slew_rate: standard, open_drain: disabled} - - {pin_num: '32', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO, pin_signal: PIO0_1/FC0_TXD_SCL_MISO/FC3_RTS_SCL_SSEL1/CTIMER0_CAP1/SCT0_OUT1, mode: inactive, invert: disabled, - glitch_filter: disabled, slew_rate: standard, open_drain: disabled} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ -/* clang-format on */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitPins - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -/* Function assigned for the undefined */ -void BOARD_InitPins(void) -{ - /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ - CLOCK_EnableClock(kCLOCK_Iocon); - - const uint32_t port0_pin0_config = (/* Pin is configured as FC0_RXD_SDA_MOSI */ - IOCON_PIO_FUNC1 | - /* No addition pin function */ - IOCON_PIO_MODE_INACT | - /* Input function is not inverted */ - IOCON_PIO_INV_DI | - /* Enables digital function */ - IOCON_PIO_DIGITAL_EN | - /* Input filter disabled */ - IOCON_PIO_INPFILT_OFF | - /* Standard mode, output slew rate control is enabled */ - IOCON_PIO_SLEW_STANDARD | - /* Open drain is disabled */ - IOCON_PIO_OPENDRAIN_DI); - /* PORT0 PIN0 (coords: 31) is configured as FC0_RXD_SDA_MOSI */ - IOCON_PinMuxSet(IOCON, 0U, 0U, port0_pin0_config); - - const uint32_t port0_pin1_config = (/* Pin is configured as FC0_TXD_SCL_MISO */ - IOCON_PIO_FUNC1 | - /* No addition pin function */ - IOCON_PIO_MODE_INACT | - /* Input function is not inverted */ - IOCON_PIO_INV_DI | - /* Enables digital function */ - IOCON_PIO_DIGITAL_EN | - /* Input filter disabled */ - IOCON_PIO_INPFILT_OFF | - /* Standard mode, output slew rate control is enabled */ - IOCON_PIO_SLEW_STANDARD | - /* Open drain is disabled */ - IOCON_PIO_OPENDRAIN_DI); - /* PORT0 PIN1 (coords: 32) is configured as FC0_TXD_SCL_MISO */ - IOCON_PinMuxSet(IOCON, 0U, 1U, port0_pin1_config); -} -/*********************************************************************************************************************** - * EOF - **********************************************************************************************************************/ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/pin_mux.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/pin_mux.h deleted file mode 100644 index 339c1d672a1..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/project_template/pin_mux.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _PIN_MUX_H_ -#define _PIN_MUX_H_ - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ - -/*! @brief Direction type */ -typedef enum _pin_mux_direction -{ - kPIN_MUX_DirectionInput = 0U, /* Input direction */ - kPIN_MUX_DirectionOutput = 1U, /* Output direction */ - kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ -} pin_mux_direction_t; - -/*! - * @addtogroup pin_mux - * @{ - */ - -/*********************************************************************************************************************** - * API - **********************************************************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Calls initialization functions. - * - */ -void BOARD_InitBootPins(void); - -#define IOCON_PIO_DIGITAL_EN 0x80u /*!<@brief Enables digital function */ -#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ -#define IOCON_PIO_INPFILT_OFF 0x0100u /*!<@brief Input filter disabled */ -#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ -#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ -#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ -#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitPins(void); /* Function assigned for the Cortex-M0P */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ -#endif /* _PIN_MUX_H_ */ - -/*********************************************************************************************************************** - * EOF - **********************************************************************************************************************/ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm0plus.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm0plus.c deleted file mode 100644 index 5b2b15244fb..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm0plus.c +++ /dev/null @@ -1,366 +0,0 @@ -/* -** ################################################################### -** Processors: LPC54114J256BD64_cm0plus -** LPC54114J256UK49_cm0plus -** -** Compilers: Keil ARM C/C++ Compiler -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 -** Version: rev. 1.0, 2016-04-29 -** Build: b161227 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** The Clear BSD License -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted (subject to the limitations in the disclaimer below) provided -** that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2016-04-29) -** Initial version. -** -** ################################################################### -*/ - -/*! - * @file LPC54114_cm0plus - * @version 1.0 - * @date 2016-04-29 - * @brief Device specific configuration file for LPC54114_cm0plus - * (implementation file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include -#include "fsl_device_registers.h" - -#define NVALMAX (0x100) -#define PVALMAX (0x20) -#define MVALMAX (0x8000) -#define PLL_SSCG0_MDEC_VAL_P (0) /* MDEC is in bits 16 downto 0 */ -#define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) /* NDEC is in bits 9 downto 0 */ -#define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0 */ -#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P) -#define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0 */ -#define PLL_PDEC_VAL_M (0x3FFUL << PLL_PDEC_VAL_P) - -extern void *__Vectors; - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46, - 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61}; - -static uint32_t GetWdtOscFreq(void) -{ - uint8_t freq_sel, div_sel; - div_sel = ((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1) << 1; - freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)]; - return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel); -} - -/* Find decoded N value for raw NDEC value */ -static uint32_t pllDecodeN(uint32_t NDEC) -{ - uint32_t n, x, i; - - /* Find NDec */ - switch (NDEC) - { - case 0xFFF: - n = 0; - break; - case 0x302: - n = 1; - break; - case 0x202: - n = 2; - break; - default: - x = 0x080; - n = 0xFFFFFFFF; - for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFF)); i--) - { - x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F); - if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC) - { - /* Decoded value of NDEC */ - n = i; - } - } - break; - } - return n; -} - -/* Find decoded P value for raw PDEC value */ -static uint32_t pllDecodeP(uint32_t PDEC) -{ - uint32_t p, x, i; - /* Find PDec */ - switch (PDEC) - { - case 0xFF: - p = 0; - break; - case 0x62: - p = 1; - break; - case 0x42: - p = 2; - break; - default: - x = 0x10; - p = 0xFFFFFFFF; - for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFF)); i--) - { - x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xF); - if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC) - { - /* Decoded value of PDEC */ - p = i; - } - } - break; - } - return p; -} - -/* Find decoded M value for raw MDEC value */ -static uint32_t pllDecodeM(uint32_t MDEC) -{ - uint32_t m, i, x; - - /* Find MDec */ - switch (MDEC) - { - case 0xFFFFF: - m = 0; - break; - case 0x18003: - m = 1; - break; - case 0x10003: - m = 2; - break; - default: - x = 0x04000; - m = 0xFFFFFFFF; - for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFF)); i--) - { - x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF); - if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC) - { - /* Decoded value of MDEC */ - m = i; - } - } - break; - } - return m; -} - -/* Get predivider (N) from PLL NDEC setting */ -static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg) -{ - uint32_t preDiv = 1; - - /* Direct input is not used? */ - if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0) - { - /* Decode NDEC value to get (N) pre divider */ - preDiv = pllDecodeN(nDecReg & 0x3FF); - if (preDiv == 0) - { - preDiv = 1; - } - } - /* Adjusted by 1, directi is used to bypass */ - return preDiv; -} - -/* Get postdivider (P) from PLL PDEC setting */ -static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg) -{ - uint32_t postDiv = 1; - - /* Direct input is not used? */ - if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0) - { - /* Decode PDEC value to get (P) post divider */ - postDiv = 2 * pllDecodeP(pDecReg & 0x7F); - if (postDiv == 0) - { - postDiv = 2; - } - } - /* Adjusted by 1, directo is used to bypass */ - return postDiv; -} - -/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ -static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg) -{ - uint32_t mMult = 1; - - /* Decode MDEC value to get (M) multiplier */ - mMult = pllDecodeM(mDecReg & 0x1FFFF); - /* Extra multiply by 2 needed? */ - if ((ctrlReg & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK) == 0) - { - mMult = mMult << 1; - } - if (mMult == 0) - { - mMult = 1; - } - return mMult; -} - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ - -void SystemInit(void) -{ - SCB->VTOR = (uint32_t)&__Vectors; - SystemInitHook(); -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate(void) -{ - uint32_t clkRate = 0; - uint32_t prediv, postdiv; - uint64_t workRate; - - switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) - { - case 0x00: /* MAINCLKSELA clock (main_clk_a)*/ - switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = CLK_FRO_12MHZ; - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = CLK_CLK_IN; - break; - case 0x02: /* Watchdog oscillator (wdt_clk) */ - clkRate = GetWdtOscFreq(); - break; - default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */ - if (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) - { - clkRate = CLK_FRO_96MHZ; - } - else - { - clkRate = CLK_FRO_48MHZ; - } - break; - } - break; - case 0x02: /* System PLL clock (pll_clk)*/ - switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = CLK_FRO_12MHZ; - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = CLK_CLK_IN; - break; - case 0x02: /* Watchdog oscillator (wdt_clk) */ - clkRate = GetWdtOscFreq(); - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = CLK_RTC_32K_CLK; - break; - default: - break; - } - if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0) - { - /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ - prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC); - postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC); - /* Adjust input clock */ - clkRate = clkRate / prediv; - /* If using the SS, use the multiplier */ - if (SYSCON->SYSPLLSSCTRL1 & SYSCON_SYSPLLSSCTRL1_PD_MASK) - { - /* MDEC used for rate */ - workRate = (uint64_t)clkRate * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLSSCTRL0); - } - else - { - /* SS multipler used for rate */ - workRate = 0; - /* Adjust by fractional */ - workRate = workRate + ((clkRate * (uint64_t)((SYSCON->SYSPLLSSCTRL1 & 0x7FF) >> 0)) / 0x800); - } - clkRate = workRate / ((uint64_t)postdiv); - } - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = CLK_RTC_32K_CLK; - break; - default: - break; - } - SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1); -} - -/* ---------------------------------------------------------------------------- - -- SystemInitHook() - ---------------------------------------------------------------------------- */ - -__attribute__ ((weak)) void SystemInitHook (void) { - /* Void implementation of the weak function. */ -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm0plus.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm0plus.h deleted file mode 100644 index fa2b8c10124..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm0plus.h +++ /dev/null @@ -1,136 +0,0 @@ -/* -** ################################################################### -** Processors: LPC54114J256BD64_cm0plus -** LPC54114J256UK49_cm0plus -** -** Compilers: Keil ARM C/C++ Compiler -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 -** Version: rev. 1.0, 2016-04-29 -** Build: b161227 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** The Clear BSD License -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted (subject to the limitations in the disclaimer below) provided -** that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2016-04-29) -** Initial version. -** -** ################################################################### -*/ - -/*! - * @file LPC54114_cm0plus - * @version 1.0 - * @date 2016-04-29 - * @brief Device specific configuration file for LPC54114_cm0plus (header file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef _SYSTEM_LPC54114_cm0plus_H_ -#define _SYSTEM_LPC54114_cm0plus_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - - -#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ -#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ -#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ -#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ -#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ -#define CLK_CLK_IN 0u /* Default CLK_IN pin clock */ - - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -/** - * @brief SystemInit function hook. - * - * This weak function allows to call specific initialization code during the - * SystemInit() execution.This can be used when an application specific code needs - * to be called as close to the reset entry as possible (for example the Multicore - * Manager MCMGR_EarlyInit() function call). - * NOTE: No global r/w variables can be used in this hook function because the - * initialization of these variables happens after this function. - */ -void SystemInitHook (void); - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_LPC54114_cm0plus_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm4.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm4.c deleted file mode 100644 index b9b519540d7..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm4.c +++ /dev/null @@ -1,374 +0,0 @@ -/* -** ################################################################### -** Processors: LPC54114J256BD64_cm4 -** LPC54114J256UK49_cm4 -** -** Compilers: Keil ARM C/C++ Compiler -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 -** Version: rev. 1.0, 2016-04-29 -** Build: b161227 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** The Clear BSD License -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted (subject to the limitations in the disclaimer below) provided -** that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2016-04-29) -** Initial version. -** -** ################################################################### -*/ - -/*! - * @file LPC54114_cm4 - * @version 1.0 - * @date 2016-04-29 - * @brief Device specific configuration file for LPC54114_cm4 (implementation - * file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include -#include "fsl_device_registers.h" - -#define NVALMAX (0x100) -#define PVALMAX (0x20) -#define MVALMAX (0x8000) -#define PLL_SSCG0_MDEC_VAL_P (0) /* MDEC is in bits 16 downto 0 */ -#define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) /* NDEC is in bits 9 downto 0 */ -#define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0 */ -#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P) -#define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0 */ -#define PLL_PDEC_VAL_M (0x3FFUL << PLL_PDEC_VAL_P) - -extern void *__Vectors; - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46, - 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61}; - -static uint32_t GetWdtOscFreq(void) -{ - uint8_t freq_sel, div_sel; - div_sel = ((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1) << 1; - freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)]; - return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel); -} - -/* Find decoded N value for raw NDEC value */ -static uint32_t pllDecodeN(uint32_t NDEC) -{ - uint32_t n, x, i; - - /* Find NDec */ - switch (NDEC) - { - case 0xFFF: - n = 0; - break; - case 0x302: - n = 1; - break; - case 0x202: - n = 2; - break; - default: - x = 0x080; - n = 0xFFFFFFFF; - for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFF)); i--) - { - x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F); - if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC) - { - /* Decoded value of NDEC */ - n = i; - } - } - break; - } - return n; -} - -/* Find decoded P value for raw PDEC value */ -static uint32_t pllDecodeP(uint32_t PDEC) -{ - uint32_t p, x, i; - /* Find PDec */ - switch (PDEC) - { - case 0xFF: - p = 0; - break; - case 0x62: - p = 1; - break; - case 0x42: - p = 2; - break; - default: - x = 0x10; - p = 0xFFFFFFFF; - for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFF)); i--) - { - x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xF); - if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC) - { - /* Decoded value of PDEC */ - p = i; - } - } - break; - } - return p; -} - -/* Find decoded M value for raw MDEC value */ -static uint32_t pllDecodeM(uint32_t MDEC) -{ - uint32_t m, i, x; - - /* Find MDec */ - switch (MDEC) - { - case 0xFFFFF: - m = 0; - break; - case 0x18003: - m = 1; - break; - case 0x10003: - m = 2; - break; - default: - x = 0x04000; - m = 0xFFFFFFFF; - for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFF)); i--) - { - x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF); - if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC) - { - /* Decoded value of MDEC */ - m = i; - } - } - break; - } - return m; -} - -/* Get predivider (N) from PLL NDEC setting */ -static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg) -{ - uint32_t preDiv = 1; - - /* Direct input is not used? */ - if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0) - { - /* Decode NDEC value to get (N) pre divider */ - preDiv = pllDecodeN(nDecReg & 0x3FF); - if (preDiv == 0) - { - preDiv = 1; - } - } - /* Adjusted by 1, directi is used to bypass */ - return preDiv; -} - -/* Get postdivider (P) from PLL PDEC setting */ -static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg) -{ - uint32_t postDiv = 1; - - /* Direct input is not used? */ - if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0) - { - /* Decode PDEC value to get (P) post divider */ - postDiv = 2 * pllDecodeP(pDecReg & 0x7F); - if (postDiv == 0) - { - postDiv = 2; - } - } - /* Adjusted by 1, directo is used to bypass */ - return postDiv; -} - -/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ -static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg) -{ - uint32_t mMult = 1; - - /* Decode MDEC value to get (M) multiplier */ - mMult = pllDecodeM(mDecReg & 0x1FFFF); - /* Extra multiply by 2 needed? */ - if ((ctrlReg & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK) == 0) - { - mMult = mMult << 1; - } - if (mMult == 0) - { - mMult = 1; - } - return mMult; -} - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ - -void SystemInit(void) -{ -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) || (defined(__VFP_FP__) && !defined(__SOFTFP__)) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ - SCB->VTOR = (uint32_t)&__Vectors; -/* Optionally enable RAM banks that may be off by default at reset */ -#if !defined(DONT_ENABLE_DISABLED_RAMBANKS) - SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM2_MASK; -#endif - - SystemInitHook(); -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate(void) -{ - uint32_t clkRate = 0; - uint32_t prediv, postdiv; - uint64_t workRate; - - switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) - { - case 0x00: /* MAINCLKSELA clock (main_clk_a)*/ - switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = CLK_FRO_12MHZ; - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = CLK_CLK_IN; - break; - case 0x02: /* Watchdog oscillator (wdt_clk) */ - clkRate = GetWdtOscFreq(); - break; - default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */ - if (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) - { - clkRate = CLK_FRO_96MHZ; - } - else - { - clkRate = CLK_FRO_48MHZ; - } - break; - } - break; - case 0x02: /* System PLL clock (pll_clk)*/ - switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = CLK_FRO_12MHZ; - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = CLK_CLK_IN; - break; - case 0x02: /* Watchdog oscillator (wdt_clk) */ - clkRate = GetWdtOscFreq(); - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = CLK_RTC_32K_CLK; - break; - default: - break; - } - if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0) - { - /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ - prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC); - postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC); - /* Adjust input clock */ - clkRate = clkRate / prediv; - /* If using the SS, use the multiplier */ - if (SYSCON->SYSPLLSSCTRL1 & SYSCON_SYSPLLSSCTRL1_PD_MASK) - { - /* MDEC used for rate */ - workRate = (uint64_t)clkRate * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLSSCTRL0); - } - else - { - /* SS multipler used for rate */ - workRate = 0; - /* Adjust by fractional */ - workRate = workRate + ((clkRate * (uint64_t)((SYSCON->SYSPLLSSCTRL1 & 0x7FF) >> 0)) / 0x800); - } - clkRate = workRate / ((uint64_t)postdiv); - } - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = CLK_RTC_32K_CLK; - break; - default: - break; - } - SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1); -} - -/* ---------------------------------------------------------------------------- - -- SystemInitHook() - ---------------------------------------------------------------------------- */ - -__attribute__ ((weak)) void SystemInitHook (void) { - /* Void implementation of the weak function. */ -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm4.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm4.h deleted file mode 100644 index 33000bd751b..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm4.h +++ /dev/null @@ -1,136 +0,0 @@ -/* -** ################################################################### -** Processors: LPC54114J256BD64_cm4 -** LPC54114J256UK49_cm4 -** -** Compilers: Keil ARM C/C++ Compiler -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 -** Version: rev. 1.0, 2016-04-29 -** Build: b161227 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** The Clear BSD License -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted (subject to the limitations in the disclaimer below) provided -** that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2016-04-29) -** Initial version. -** -** ################################################################### -*/ - -/*! - * @file LPC54114_cm4 - * @version 1.0 - * @date 2016-04-29 - * @brief Device specific configuration file for LPC54114_cm4 (header file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef _SYSTEM_LPC54114_cm4_H_ -#define _SYSTEM_LPC54114_cm4_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - - -#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ -#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ -#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ -#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ -#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ -#define CLK_CLK_IN 0u /* Default CLK_IN pin clock */ - - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -/** - * @brief SystemInit function hook. - * - * This weak function allows to call specific initialization code during the - * SystemInit() execution.This can be used when an application specific code needs - * to be called as close to the reset entry as possible (for example the Multicore - * Manager MCMGR_EarlyInit() function call). - * NOTE: No global r/w variables can be used in this hook function because the - * initialization of these variables happens after this function. - */ -void SystemInitHook (void); - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_LPC54114_cm4_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/template/RTE_Device.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/template/RTE_Device.h deleted file mode 100644 index f065c275ce1..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/template/RTE_Device.h +++ /dev/null @@ -1,224 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -/* UART Select, UART0-UART7. */ -/* User needs to provide the implementation for XXX_GetFreq/XXX_InitPins/XXX_DeinitPins -in the application for enabling according instance. */ -#define RTE_USART0 0 -#define RTE_USART0_DMA_EN 0 -#define RTE_USART1 0 -#define RTE_USART1_DMA_EN 0 -#define RTE_USART2 0 -#define RTE_USART2_DMA_EN 0 -#define RTE_USART3 0 -#define RTE_USART3_DMA_EN 0 -#define RTE_USART4 0 -#define RTE_USART4_DMA_EN 0 -#define RTE_USART5 0 -#define RTE_USART5_DMA_EN 0 -#define RTE_USART6 0 -#define RTE_USART6_DMA_EN 0 -#define RTE_USART7 0 -#define RTE_USART7_DMA_EN 0 - -/* USART configuration. */ -#define USART_RX_BUFFER_LEN 64 -#define USART0_RX_BUFFER_ENABLE 0 -#define USART1_RX_BUFFER_ENABLE 0 -#define USART2_RX_BUFFER_ENABLE 0 -#define USART3_RX_BUFFER_ENABLE 0 -#define USART4_RX_BUFFER_ENABLE 0 -#define USART5_RX_BUFFER_ENABLE 0 -#define USART6_RX_BUFFER_ENABLE 0 -#define USART7_RX_BUFFER_ENABLE 0 - -#define RTE_USART0_DMA_TX_CH 1 -#define RTE_USART0_DMA_TX_DMA_BASE DMA0 -#define RTE_USART0_DMA_RX_CH 0 -#define RTE_USART0_DMA_RX_DMA_BASE DMA0 - -#define RTE_USART1_DMA_TX_CH 3 -#define RTE_USART1_DMA_TX_DMA_BASE DMA0 -#define RTE_USART1_DMA_RX_CH 2 -#define RTE_USART1_DMA_RX_DMA_BASE DMA0 - -#define RTE_USART2_DMA_TX_CH 5 -#define RTE_USART2_DMA_TX_DMA_BASE DMA0 -#define RTE_USART2_DMA_RX_CH 4 -#define RTE_USART2_DMA_RX_DMA_BASE DMA0 - -#define RTE_USART3_DMA_TX_CH 7 -#define RTE_USART3_DMA_TX_DMA_BASE DMA0 -#define RTE_USART3_DMA_RX_CH 6 -#define RTE_USART3_DMA_RX_DMA_BASE DMA0 - -#define RTE_USART4_DMA_TX_CH 9 -#define RTE_USART4_DMA_TX_DMA_BASE DMA0 -#define RTE_USART4_DMA_RX_CH 8 -#define RTE_USART4_DMA_RX_DMA_BASE DMA0 - -#define RTE_USART5_DMA_TX_CH 11 -#define RTE_USART5_DMA_TX_DMA_BASE DMA0 -#define RTE_USART5_DMA_RX_CH 10 -#define RTE_USART5_DMA_RX_DMA_BASE DMA0 - -#define RTE_USART6_DMA_TX_CH 13 -#define RTE_USART6_DMA_TX_DMA_BASE DMA0 -#define RTE_USART6_DMA_RX_CH 12 -#define RTE_USART6_DMA_RX_DMA_BASE DMA0 - -#define RTE_USART7_DMA_TX_CH 15 -#define RTE_USART7_DMA_TX_DMA_BASE DMA0 -#define RTE_USART7_DMA_RX_CH 14 -#define RTE_USART7_DMA_RX_DMA_BASE DMA0 - -/* I2C Select, I2C0 -I2C7*/ -/* User needs to provide the implementation for XXX_GetFreq/XXX_InitPins/XXX_DeinitPins -in the application for enabling according instance. */ -#define RTE_I2C0 0 -#define RTE_I2C0_DMA_EN 0 -#define RTE_I2C1 0 -#define RTE_I2C1_DMA_EN 0 -#define RTE_I2C2 0 -#define RTE_I2C2_DMA_EN 0 -#define RTE_I2C3 0 -#define RTE_I2C3_DMA_EN 0 -#define RTE_I2C4 0 -#define RTE_I2C4_DMA_EN 0 -#define RTE_I2C5 0 -#define RTE_I2C5_DMA_EN 0 -#define RTE_I2C6 0 -#define RTE_I2C6_DMA_EN 0 -#define RTE_I2C7 0 -#define RTE_I2C7_DMA_EN 0 - -/*I2C configuration*/ -#define RTE_I2C0_Master_DMA_BASE DMA0 -#define RTE_I2C0_Master_DMA_CH 1 - -#define RTE_I2C1_Master_DMA_BASE DMA0 -#define RTE_I2C1_Master_DMA_CH 3 - -#define RTE_I2C2_Master_DMA_BASE DMA0 -#define RTE_I2C2_Master_DMA_CH 5 - -#define RTE_I2C3_Master_DMA_BASE DMA0 -#define RTE_I2C3_Master_DMA_CH 7 - -#define RTE_I2C4_Master_DMA_BASE DMA0 -#define RTE_I2C4_Master_DMA_CH 9 - -#define RTE_I2C5_Master_DMA_BASE DMA0 -#define RTE_I2C5_Master_DMA_CH 11 - -#define RTE_I2C6_Master_DMA_BASE DMA0 -#define RTE_I2C6_Master_DMA_CH 13 - -#define RTE_I2C7_Master_DMA_BASE DMA0 -#define RTE_I2C7_Master_DMA_CH 15 - -/* SPI select, SPI0 - SPI7.*/ -/* User needs to provide the implementation for XXX_GetFreq/XXX_InitPins/XXX_DeinitPins -in the application for enabling according instance. */ -#define RTE_SPI0 0 -#define RTE_SPI0_DMA_EN 0 -#define RTE_SPI1 0 -#define RTE_SPI1_DMA_EN 0 -#define RTE_SPI2 0 -#define RTE_SPI2_DMA_EN 0 -#define RTE_SPI3 0 -#define RTE_SPI3_DMA_EN 0 -#define RTE_SPI4 0 -#define RTE_SPI4_DMA_EN 0 -#define RTE_SPI5 0 -#define RTE_SPI5_DMA_EN 0 -#define RTE_SPI6 0 -#define RTE_SPI6_DMA_EN 0 -#define RTE_SPI7 0 -#define RTE_SPI7_DMA_EN 0 - - -/* SPI configuration. */ -#define RTE_SPI0_SSEL_NUM kSPI_Ssel0 -#define RTE_SPI0_DMA_TX_CH 1 -#define RTE_SPI0_DMA_TX_DMA_BASE DMA0 -#define RTE_SPI0_DMA_RX_CH 0 -#define RTE_SPI0_DMA_RX_DMA_BASE DMA0 - -#define RTE_SPI1_SSEL_NUM kSPI_Ssel0 -#define RTE_SPI1_DMA_TX_CH 3 -#define RTE_SPI1_DMA_TX_DMA_BASE DMA0 -#define RTE_SPI1_DMA_RX_CH 2 -#define RTE_SPI1_DMA_RX_DMA_BASE DMA0 - -#define RTE_SPI2_SSEL_NUM kSPI_Ssel0 -#define RTE_SPI2_DMA_TX_CH 5 -#define RTE_SPI2_DMA_TX_DMA_BASE DMA0 -#define RTE_SPI2_DMA_RX_CH 4 -#define RTE_SPI2_DMA_RX_DMA_BASE DMA0 - -#define RTE_SPI3_SSEL_NUM kSPI_Ssel0 -#define RTE_SPI3_DMA_TX_CH 7 -#define RTE_SPI3_DMA_TX_DMA_BASE DMA0 -#define RTE_SPI3_DMA_RX_CH 6 -#define RTE_SPI3_DMA_RX_DMA_BASE DMA0 - -#define RTE_SPI4_SSEL_NUM kSPI_Ssel0 -#define RTE_SPI4_DMA_TX_CH 9 -#define RTE_SPI4_DMA_TX_DMA_BASE DMA0 -#define RTE_SPI4_DMA_RX_CH 8 -#define RTE_SPI4_DMA_RX_DMA_BASE DMA0 - -#define RTE_SPI5_SSEL_NUM kSPI_Ssel0 -#define RTE_SPI5_DMA_TX_CH 11 -#define RTE_SPI5_DMA_TX_DMA_BASE DMA0 -#define RTE_SPI5_DMA_RX_CH 10 -#define RTE_SPI5_DMA_RX_DMA_BASE DMA0 - -#define RTE_SPI6_SSEL_NUM kSPI_Ssel0 -#define RTE_SPI6_DMA_TX_CH 13 -#define RTE_SPI6_DMA_TX_DMA_BASE DMA0 -#define RTE_SPI6_DMA_RX_CH 12 -#define RTE_SPI6_DMA_RX_DMA_BASE DMA0 - -#define RTE_SPI7_SSEL_NUM kSPI_Ssel0 -#define RTE_SPI7_DMA_TX_CH 15 -#define RTE_SPI7_DMA_TX_DMA_BASE DMA0 -#define RTE_SPI7_DMA_RX_CH 14 -#define RTE_SPI7_DMA_RX_DMA_BASE DMA0 - -#endif /* __RTE_DEVICE_H */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/SConscript b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/SConscript deleted file mode 100644 index 6897da05ef0..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/SConscript +++ /dev/null @@ -1,13 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -CPPPATH = [cwd] -src = [] - -CPPDEFINES = ['SDK_DEBUGCONSOLE=0'] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) - -Return('group') diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_assert.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_assert.c deleted file mode 100644 index a249b645613..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_assert.c +++ /dev/null @@ -1,59 +0,0 @@ -/* -* The Clear BSD License -* Copyright (c) 2015-2016, Freescale Semiconductor, Inc. -* Copyright 2016-2017 NXP -* All rights reserved. -* -* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted (subject to the limitations in the disclaimer below) provided -* that the following conditions are met: -* -* o Redistributions of source code must retain the above copyright notice, this list -* of conditions and the following disclaimer. -* -* o Redistributions in binary form must reproduce the above copyright notice, this -* list of conditions and the following disclaimer in the documentation and/or -* other materials provided with the distribution. -* -* o Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "fsl_common.h" -#include "fsl_debug_console.h" - -#ifndef NDEBUG -#if (defined(__CC_ARM)) || (defined(__ICCARM__)) -void __aeabi_assert(const char *failedExpr, const char *file, int line) -{ - PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); - for (;;) - { - __BKPT(0); - } -} -#elif(defined(__GNUC__)) -void __assert_func(const char *file, int line, const char *func, const char *failedExpr) -{ - PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func); - for (;;) - { - __BKPT(0); - } -} -#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */ -#endif /* NDEBUG */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_debug_console.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_debug_console.c deleted file mode 100644 index 30c762f5e71..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_debug_console.c +++ /dev/null @@ -1,366 +0,0 @@ -/* - * This is a modified version of the file printf.c, which was distributed - * by Motorola as part of the M5407C3BOOT.zip package used to initialize - * the M5407C3 evaluation board. - * - * Copyright: - * 1999-2000 MOTOROLA, INC. All Rights Reserved. - * You are hereby granted a copyright license to use, modify, and - * distribute the SOFTWARE so long as this entire notice is - * retained without alteration in any modified and/or redistributed - * versions, and that such modified versions are clearly identified - * as such. No licenses are granted by implication, estoppel or - * otherwise under any patents or trademarks of Motorola, Inc. This - * software is provided on an "AS IS" basis and without warranty. - * - * To the maximum extent permitted by applicable law, MOTOROLA - * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING - * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR - * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE - * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY - * ACCOMPANYING WRITTEN MATERIALS. - * - * To the maximum extent permitted by applicable law, IN NO EVENT - * SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING - * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS - * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY - * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. - * - * Motorola assumes no responsibility for the maintenance and support - * of this software - - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#if defined(__CC_ARM) -#include -#endif - -#include "fsl_debug_console.h" -#include "fsl_debug_console_conf.h" -#include "fsl_log.h" -#include "fsl_str.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief This is a printf call back function which is used to relocate the log to buffer - * or print the log immediately when the local buffer is full. - * - * @param[in] buf Buffer to store log. - * @param[in] indicator Buffer index. - * @param[in] val Target character to store. - * @param[in] len length of the character - * - */ -#if SDK_DEBUGCONSOLE -static void DbgConsole_RelocateLog(char *buf, int32_t *indicator, char val, int len); -#endif -/******************************************************************************* - * Code - ******************************************************************************/ - -/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/ - -/* See fsl_debug_console.h for documentation of this function. */ -status_t DbgConsole_Init(uint32_t baseAddr, uint32_t baudRate, uint8_t device, uint32_t clkSrcFreq) -{ - assert(device != DEBUG_CONSOLE_DEVICE_TYPE_NONE); - - return LOG_Init(baseAddr, device, baudRate, clkSrcFreq); -} - -/* See fsl_debug_console.h for documentation of this function. */ -status_t DbgConsole_Deinit(void) -{ - /* LOG deinit */ - LOG_Deinit(); - - return kStatus_Success; -} - -status_t DbgConsole_Flush(void) -{ - /* wait log and io idle */ - return LOG_WaitIdle(); -} - -#if SDK_DEBUGCONSOLE -/* See fsl_debug_console.h for documentation of this function. */ -int DbgConsole_Printf(const char *fmt_s, ...) -{ - va_list ap; - int logLength = 0U, result = 0U; - char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {0U}; - - va_start(ap, fmt_s); - /* format print log first */ - logLength = StrFormatPrintf(fmt_s, ap, printBuf, DbgConsole_RelocateLog); - /* print log */ - result = LOG_Push((uint8_t *)printBuf, logLength); - - va_end(ap); - - return result; -} - -/* See fsl_debug_console.h for documentation of this function. */ -int DbgConsole_Putchar(int ch) -{ - /* print char */ - return LOG_Push((uint8_t *)&ch, 1U); -} - -/* See fsl_debug_console.h for documentation of this function. */ -int DbgConsole_Scanf(char *fmt_ptr, ...) -{ - va_list ap; - int result; - char scanfBuf[DEBUG_CONSOLE_SCANF_MAX_LOG_LEN + 1U] = {0U}; - - /* scanf log */ - LOG_ReadLine((uint8_t *)scanfBuf, DEBUG_CONSOLE_SCANF_MAX_LOG_LEN); - /* get va_list */ - va_start(ap, fmt_ptr); - /* format scanf log */ - result = StrFormatScanf(scanfBuf, fmt_ptr, ap); - - va_end(ap); - - return result; -} - -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -status_t DbgConsole_TryGetchar(char *ch) -{ - if (NULL != ch) - { - return LOG_TryReadCharacter((uint8_t *)ch); - } - - return kStatus_Fail; -} -#endif - -/* See fsl_debug_console.h for documentation of this function. */ -int DbgConsole_Getchar(void) -{ - uint8_t ch; - - /* Get char */ - LOG_ReadCharacter(&ch); - - return ch; -} - -static void DbgConsole_RelocateLog(char *buf, int32_t *indicator, char val, int len) -{ - int i = 0; - - for (i = 0; i < len; i++) - { - if ((*indicator + 1) >= DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN) - { - LOG_Push((uint8_t *)buf, *indicator); - *indicator = 0U; - } - - buf[*indicator] = val; - (*indicator)++; - } -} - -#endif /* SDK_DEBUGCONSOLE */ - -/*************Code to support toolchain's printf, scanf *******************************/ -/* These function __write and __read is used to support IAR toolchain to printf and scanf*/ -#if (defined(__ICCARM__)) -#if defined(SDK_DEBUGCONSOLE_UART) -#pragma weak __write -size_t __write(int handle, const unsigned char *buffer, size_t size) -{ - if (buffer == 0) - { - /* - * This means that we should flush internal buffers. Since we don't we just return. - * (Remember, "handle" == -1 means that all handles should be flushed.) - */ - return 0; - } - - /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ - if ((handle != 1) && (handle != 2)) - { - return ((size_t)-1); - } - - /* Send data. */ - LOG_Push((uint8_t *)buffer, 1U); - - return size; -} - -#pragma weak __read -size_t __read(int handle, unsigned char *buffer, size_t size) -{ - /* This function only reads from "standard in", for all other file handles it returns failure. */ - if (handle != 0) - { - return ((size_t)-1); - } - - /* Receive data.*/ - LOG_ReadLine(buffer, size); - - return size; -} -#endif /* SDK_DEBUGCONSOLE_UART */ - -/* support LPC Xpresso with RedLib */ -#elif(defined(__REDLIB__)) - -#if (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART)) -int __attribute__((weak)) __sys_write(int handle, char *buffer, int size) -{ - if (buffer == 0) - { - /* return -1 if error. */ - return -1; - } - - /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ - if ((handle != 1) && (handle != 2)) - { - return -1; - } - - /* Send data. */ - LOG_Push((uint8_t *)buffer, size); - - return 0; -} - -int __attribute__((weak)) __sys_readc(void) -{ - char tmp; - - /* Receive data. */ - LOG_ReadCharacter((uint8_t *)&tmp); - - return tmp; -} -#endif - -/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/ -#elif(defined(__GNUC__)) - -#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO)) && (defined(SDK_DEBUGCONSOLE_UART))) || \ - (defined(__MCUXPRESSO) && (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART)))) - -int __attribute__((weak)) _write(int handle, char *buffer, int size) -{ - if (buffer == 0) - { - /* return -1 if error. */ - return -1; - } - - /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ - if ((handle != 1) && (handle != 2)) - { - return -1; - } - - /* Send data. */ - LOG_Push((uint8_t *)buffer, size); - - return size; -} - -int __attribute__((weak)) _read(int handle, char *buffer, int size) -{ - /* This function only reads from "standard in", for all other file handles it returns failure. */ - if (handle != 0) - { - return -1; - } - - /* Receive data. */ - return LOG_ReadLine((uint8_t *)buffer, size); -} -#endif - -/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/ -#elif defined(__CC_ARM) -#if defined(SDK_DEBUGCONSOLE_UART) -struct __FILE -{ - int handle; - /* - * Whatever you require here. If the only file you are using is standard output using printf() for debugging, - * no file handling is required. - */ -}; - -/* FILE is typedef in stdio.h. */ -#pragma weak __stdout -#pragma weak __stdin -FILE __stdout; -FILE __stdin; - -#pragma weak fputc -int fputc(int ch, FILE *f) -{ - /* Send data. */ - return LOG_Push((uint8_t *)(&ch), 1); -} - -#pragma weak fgetc -int fgetc(FILE *f) -{ - char ch; - - /* Receive data. */ - LOG_ReadCharacter((uint8_t *)&ch); - - return ch; -} -#endif /* SDK_DEBUGCONSOLE_UART */ -#endif /* __ICCARM__ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_debug_console.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_debug_console.h deleted file mode 100644 index 14dd3a0c2d8..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_debug_console.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Debug console shall provide input and output functions to scan and print formatted data. - * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier" - * - [flags] :'-', '+', '#', ' ', '0' - * - [width]: number (0,1...) - * - [.precision]: number (0,1...) - * - [length]: do not support - * - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n' - * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier" - * - [*]: is supported. - * - [width]: number (0,1...) - * - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t') - * - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's' - */ - -#ifndef _FSL_DEBUGCONSOLE_H_ -#define _FSL_DEBUGCONSOLE_H_ - -#include "fsl_common.h" -/*! - * @addtogroup debugconsole - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Definition to select sdk or toolchain printf, scanf. */ -#ifndef SDK_DEBUGCONSOLE -#define SDK_DEBUGCONSOLE 1U -#endif - -/*! @brief Definition to select redirect toolchain printf, scanf to uart or not. */ -#ifndef SDK_DEBUGCONSOLE_UART -/* mcux will handle this macro, not define it here */ -#if (!defined(__MCUXPRESSO)) -#define SDK_DEBUGCONSOLE_UART -#endif -#endif - -#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE) -#include -#endif - -#if SDK_DEBUGCONSOLE /* Select printf, scanf, putchar, getchar of SDK version. */ -#define PRINTF DbgConsole_Printf -#define SCANF DbgConsole_Scanf -#define PUTCHAR DbgConsole_Putchar -#define GETCHAR DbgConsole_Getchar -#else /* Select printf, scanf, putchar, getchar of toolchain. */ -#define PRINTF printf -#define SCANF scanf -#define PUTCHAR putchar -#define GETCHAR getchar -#endif /* SDK_DEBUGCONSOLE */ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! @name Initialization*/ -/* @{ */ - -/*! - * @brief Initializes the peripheral used for debug messages. - * - * Call this function to enable debug log messages to be output via the specified peripheral, - * frequency of peripheral source clock, and base address at the specified baud rate. - * After this function has returned, stdout and stdin are connected to the selected peripheral. - * - * @param baseAddr Indicates the address of the peripheral used to send debug messages. - * @param baudRate The desired baud rate in bits per second. - * @param device Low level device type for the debug console, can be one of the following. - * @arg DEBUG_CONSOLE_DEVICE_TYPE_UART, - * @arg DEBUG_CONSOLE_DEVICE_TYPE_LPUART, - * @arg DEBUG_CONSOLE_DEVICE_TYPE_LPSCI, - * @arg DEBUG_CONSOLE_DEVICE_TYPE_USBCDC. - * @param clkSrcFreq Frequency of peripheral source clock. - * - * @return Indicates whether initialization was successful or not. - * @retval kStatus_Success Execution successfully - * @retval kStatus_Fail Execution failure - * @retval kStatus_InvalidArgument Invalid argument existed - */ -status_t DbgConsole_Init(uint32_t baseAddr, uint32_t baudRate, uint8_t device, uint32_t clkSrcFreq); - -/*! - * @brief De-initializes the peripheral used for debug messages. - * - * Call this function to disable debug log messages to be output via the specified peripheral - * base address and at the specified baud rate. - * - * @return Indicates whether de-initialization was successful or not. - */ -status_t DbgConsole_Deinit(void); - -#if SDK_DEBUGCONSOLE -/*! - * @brief Writes formatted output to the standard output stream. - * - * Call this function to write a formatted output to the standard output stream. - * - * @param fmt_s Format control string. - * @return Returns the number of characters printed or a negative value if an error occurs. - */ -int DbgConsole_Printf(const char *fmt_s, ...); - -/*! - * @brief Writes a character to stdout. - * - * Call this function to write a character to stdout. - * - * @param ch Character to be written. - * @return Returns the character written. - */ -int DbgConsole_Putchar(int ch); - -/*! - * @brief Reads formatted data from the standard input stream. - * - * Call this function to read formatted data from the standard input stream. - * - * @param fmt_ptr Format control string. - * @return Returns the number of fields successfully converted and assigned. - */ -int DbgConsole_Scanf(char *fmt_ptr, ...); - -/*! - * @brief Reads a character from standard input. - * - * Call this function to read a character from standard input. - * - * @return Returns the character read. - */ -int DbgConsole_Getchar(void); - -/*! - * @brief Debug console flush log. - * - * Call this function to wait the buffer empty and io idle before. - * If interrupt transfer is using, make sure the global IRQ is enable before call this function - * This function should be called when - * 1, before enter power down mode - * 2, log is required to print to terminal immediately - * @return Indicates whether wait idle was successful or not. - */ -status_t DbgConsole_Flush(void); - -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -/*! - * @brief Debug console try to get char - * This function provide a api which will not block current task, if character is - * avaliable return it , otherwise return fail. - * @param ch the address of char to receive - * @return Indicates get char was successful or not. - */ -status_t DbgConsole_TryGetchar(char *ch); -#endif - -#endif /* SDK_DEBUGCONSOLE */ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @} */ - -#endif /* _FSL_DEBUGCONSOLE_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_debug_console_conf.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_debug_console_conf.h deleted file mode 100644 index 7dfad4207d4..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_debug_console_conf.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_DEBUG_CONSOLE_CONF_H_ -#define _FSL_DEBUG_CONSOLE_CONF_H_ - -/****************Debug console configuration********************/ - -/*! @brief If Non-blocking mode is needed, please define it at project setting, -* otherwise blocking mode is the default transfer mode. -* Warning: If you want to use non-blocking transfer,please make sure the corresponding -* IO interrupt is enable, otherwise there is no output. -* And non-blocking is combine with buffer, no matter bare-metal or rtos. -*/ -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically -* when -* non-blocking transfer is using, -* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. -* If it is configured too small, log maybe missed , because the log will not be -* buffered if the buffer is full, and the print will return immediately with -1. -* And this value should be multiple of 4 to meet memory alignment. -* -*/ -#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN -#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U) -#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */ - -/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when -* non-blocking transfer is using, -* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. -* If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small. -* And this value should be multiple of 4 to meet memory alignment. -* -*/ -#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN -#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (512U) -#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */ - -#else -#define DEBUG_CONSOLE_TRANSFER_BLOCKING -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ - -/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log -* length can not bigger than this value. -* This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if -* the buffer is too big and current task stack size not big enough. -*/ -#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN -#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U) -#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */ - -/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log -* length can not bigger than this value. -* As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN. -*/ -#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN -#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U) -#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */ - -/*! @brief Debug console synchronization -* User should not change these macro for synchronization mode, but add the -* corresponding synchronization mechanism per different software environment. -* Such as, if another RTOS is used, -* add: -* #define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3 -* in this configuration file and implement the synchronization in fsl.log.c. -*/ -/*! @brief synchronization for baremetal software */ -#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0 -/*! @brief synchronization for freertos software */ -#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1 - -/*! @brief RTOS synchronization mechanism disable -* If not defined, default is enable, to avoid multitask log print mess. -* If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c -* If synchronization is disabled, log maybe messed on terminal. -*/ -#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -#ifdef FSL_RTOS_FREE_RTOS -#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS -#else -#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM -#endif /* FSL_RTOS_FREE_RTOS */ -#else -#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ -#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */ - -/*! @brief echo function support -* If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO -* at your project setting. -*/ -#ifndef DEBUG_CONSOLE_ENABLE_ECHO -#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0 -#else -#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1 -#endif /* DEBUG_CONSOLE_ENABLE_ECHO */ - -/*********************************************************************/ - -/***************Debug console other configuration*********************/ -/*! @brief Definition to printf the float number. */ -#ifndef PRINTF_FLOAT_ENABLE -#define PRINTF_FLOAT_ENABLE 0U -#endif /* PRINTF_FLOAT_ENABLE */ - -/*! @brief Definition to scanf the float number. */ -#ifndef SCANF_FLOAT_ENABLE -#define SCANF_FLOAT_ENABLE 0U -#endif /* SCANF_FLOAT_ENABLE */ - -/*! @brief Definition to support advanced format specifier for printf. */ -#ifndef PRINTF_ADVANCED_ENABLE -#define PRINTF_ADVANCED_ENABLE 0U -#endif /* PRINTF_ADVANCED_ENABLE */ - -/*! @brief Definition to support advanced format specifier for scanf. */ -#ifndef SCANF_ADVANCED_ENABLE -#define SCANF_ADVANCED_ENABLE 0U -#endif /* SCANF_ADVANCED_ENABLE */ - -/*! @brief Definition to select virtual com(USB CDC) as the debug console. */ -#ifndef BOARD_USE_VIRTUALCOM -#define BOARD_USE_VIRTUALCOM 0U -#endif -/*******************************************************************/ - -#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_notifier.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_notifier.c deleted file mode 100644 index 10cb9bece7a..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_notifier.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_notifier.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -status_t NOTIFIER_CreateHandle(notifier_handle_t *notifierHandle, - notifier_user_config_t **configs, - uint8_t configsNumber, - notifier_callback_config_t *callbacks, - uint8_t callbacksNumber, - notifier_user_function_t userFunction, - void *userData) -{ - /* Check input parameter - at least one configuration is required and userFunction must exist */ - if ((configs == NULL) || (configsNumber == 0U) || (userFunction == NULL)) - { - return kStatus_Fail; - } - /* Initialize handle structure */ - memset(notifierHandle, 0, sizeof(notifier_handle_t)); - /* Store references to user-defined configurations */ - notifierHandle->configsTable = configs; - notifierHandle->configsNumber = configsNumber; - /* Store references to user-defined callback configurations */ - if (callbacks != NULL) - { - notifierHandle->callbacksTable = callbacks; - notifierHandle->callbacksNumber = callbacksNumber; - /* If all callbacks return success, then the errorCallbackIndex is callbacksNumber */ - notifierHandle->errorCallbackIndex = callbacksNumber; - } - notifierHandle->userFunction = userFunction; - notifierHandle->userData = userData; - - return kStatus_Success; -} - -status_t NOTIFIER_SwitchConfig(notifier_handle_t *notifierHandle, uint8_t configIndex, notifier_policy_t policy) -{ - uint8_t currentStaticCallback = 0U; /* Index to array of statically registered call-backs */ - status_t returnCode = kStatus_Success; /* Function return */ - - notifier_notification_block_t notifyBlock; /* Callback notification block */ - notifier_callback_config_t *callbackConfig; /* Pointer to callback configuration */ - - /* Set errorcallbackindex as callbacksNumber, which means no callback error now */ - notifierHandle->errorCallbackIndex = notifierHandle->callbacksNumber; - - /* Requested configuration availability check */ - if (configIndex >= notifierHandle->configsNumber) - { - return kStatus_OutOfRange; - } - - /* Initialization of local variables from the Notifier handle structure */ - - notifyBlock.policy = policy; - notifyBlock.targetConfig = notifierHandle->configsTable[configIndex]; - notifyBlock.notifyType = kNOTIFIER_NotifyBefore; - - /* From all statically registered call-backs... */ - for (currentStaticCallback = 0U; currentStaticCallback < notifierHandle->callbacksNumber; currentStaticCallback++) - { - callbackConfig = &(notifierHandle->callbacksTable[currentStaticCallback]); - /* ...notify only those which asked to be called before the configuration switch */ - if (((uint32_t)callbackConfig->callbackType) & kNOTIFIER_CallbackBefore) - { - /* In case that call-back returned error code mark it, store the call-back handle and eventually cancel - * the configuration switch */ - if (callbackConfig->callback(¬ifyBlock, callbackConfig->callbackData) != kStatus_Success) - { - returnCode = kStatus_NOTIFIER_ErrorNotificationBefore; - notifierHandle->errorCallbackIndex = currentStaticCallback; - /* If not forcing configuration switch, call all already notified call-backs to revert their state - * as the switch is canceled */ - if (policy != kNOTIFIER_PolicyForcible) - { - break; - } - } - } - } - - /* Set configuration */ - - /* In case that any call-back returned error code and policy doesn't force the configuration set, go to after - * switch call-backs */ - if ((policy == kNOTIFIER_PolicyForcible) || (returnCode == kStatus_Success)) - { - returnCode = notifierHandle->userFunction(notifierHandle->configsTable[configIndex], notifierHandle->userData); - if (returnCode != kStatus_Success) - { - return returnCode; - } - /* Update current configuration index */ - notifierHandle->currentConfigIndex = configIndex; - notifyBlock.notifyType = kNOTIFIER_NotifyAfter; - /* From all statically registered call-backs... */ - for (currentStaticCallback = 0U; currentStaticCallback < notifierHandle->callbacksNumber; - currentStaticCallback++) - { - callbackConfig = &(notifierHandle->callbacksTable[currentStaticCallback]); - /* ...notify only those which asked to be called after the configruation switch */ - if (((uint32_t)callbackConfig->callbackType) & kNOTIFIER_CallbackAfter) - { - /* In case that call-back returned error code mark it and store the call-back handle */ - if (callbackConfig->callback(¬ifyBlock, callbackConfig->callbackData) != kStatus_Success) - { - returnCode = kStatus_NOTIFIER_ErrorNotificationAfter; - notifierHandle->errorCallbackIndex = currentStaticCallback; - if (policy != kNOTIFIER_PolicyForcible) - { - break; - } - } - } - } - } - else - { - /* End of unsuccessful switch */ - notifyBlock.notifyType = kNOTIFIER_NotifyRecover; - while (currentStaticCallback--) - { - callbackConfig = &(notifierHandle->callbacksTable[currentStaticCallback]); - if (((uint32_t)callbackConfig->callbackType) & kNOTIFIER_CallbackBefore) - { - callbackConfig->callback(¬ifyBlock, callbackConfig->callbackData); - } - } - } - - return returnCode; -} - -uint8_t NOTIFIER_GetErrorCallbackIndex(notifier_handle_t *notifierHandle) -{ - return notifierHandle->errorCallbackIndex; -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_notifier.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_notifier.h deleted file mode 100644 index 5c930d98127..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_notifier.h +++ /dev/null @@ -1,263 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_NOTIFIER_H_ -#define _FSL_NOTIFIER_H_ - -#include "fsl_common.h" -/*! - * @addtogroup notifier - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief Notifier error codes. - * - * Used as return value of Notifier functions. - */ -enum _notifier_status -{ - kStatus_NOTIFIER_ErrorNotificationBefore = - MAKE_STATUS(kStatusGroup_NOTIFIER, 0), /*!< An error occurs during send "BEFORE" notification. */ - kStatus_NOTIFIER_ErrorNotificationAfter = - MAKE_STATUS(kStatusGroup_NOTIFIER, 1), /*!< An error occurs during send "AFTER" notification. */ -}; - -/*! - * @brief Notifier policies. - * - * Defines whether the user function execution is forced or not. - * For kNOTIFIER_PolicyForcible, the user function is executed regardless of the callback results, - * while kNOTIFIER_PolicyAgreement policy is used to exit NOTIFIER_SwitchConfig() - * when any of the callbacks returns error code. - * See also NOTIFIER_SwitchConfig() description. - */ -typedef enum _notifier_policy -{ - kNOTIFIER_PolicyAgreement, /*!< NOTIFIER_SwitchConfig() method is exited when any of the callbacks returns error - code. */ - kNOTIFIER_PolicyForcible, /*!< The user function is executed regardless of the results. */ -} notifier_policy_t; - -/*! @brief Notification type. Used to notify registered callbacks */ -typedef enum _notifier_notification_type -{ - kNOTIFIER_NotifyRecover = 0x00U, /*!< Notify IP to recover to previous work state. */ - kNOTIFIER_NotifyBefore = 0x01U, /*!< Notify IP that configuration setting is going to change. */ - kNOTIFIER_NotifyAfter = 0x02U, /*!< Notify IP that configuration setting has been changed. */ -} notifier_notification_type_t; - -/*! - * @brief The callback type, which indicates kinds of notification the callback handles. - * - * Used in the callback configuration structure (notifier_callback_config_t) - * to specify when the registered callback is called during configuration switch initiated by the - * NOTIFIER_SwitchConfig(). - * Callback can be invoked in following situations. - * - Before the configuration switch (Callback return value can affect NOTIFIER_SwitchConfig() - * execution. See the NOTIFIER_SwitchConfig() and notifier_policy_t documentation). - * - After an unsuccessful attempt to switch configuration - * - After a successful configuration switch - */ -typedef enum _notifier_callback_type -{ - kNOTIFIER_CallbackBefore = 0x01U, /*!< Callback handles BEFORE notification. */ - kNOTIFIER_CallbackAfter = 0x02U, /*!< Callback handles AFTER notification. */ - kNOTIFIER_CallbackBeforeAfter = 0x03U, /*!< Callback handles BEFORE and AFTER notification. */ -} notifier_callback_type_t; - -/*! @brief Notifier user configuration type. - * - * Reference of the user defined configuration is stored in an array; the notifier switches between these configurations - * based on this array. - */ -typedef void notifier_user_config_t; - -/*! @brief Notifier user function prototype - * Use this function to execute specific operations in configuration switch. - * Before and after this function execution, different notification is sent to registered callbacks. - * If this function returns any error code, NOTIFIER_SwitchConfig() exits. - * - * @param targetConfig target Configuration. - * @param userData Refers to other specific data passed to user function. - * @return An error code or kStatus_Success. - */ -typedef status_t (*notifier_user_function_t)(notifier_user_config_t *targetConfig, void *userData); - -/*! @brief notification block passed to the registered callback function. */ -typedef struct _notifier_notification_block -{ - notifier_user_config_t *targetConfig; /*!< Pointer to target configuration. */ - notifier_policy_t policy; /*!< Configure transition policy. */ - notifier_notification_type_t notifyType; /*!< Configure notification type. */ -} notifier_notification_block_t; - -/*! - * @brief Callback prototype. - * - * Declaration of a callback. It is common for registered callbacks. - * Reference to function of this type is part of the notifier_callback_config_t callback configuration structure. - * Depending on callback type, function of this prototype is called (see NOTIFIER_SwitchConfig()) - * before configuration switch, after it or in both use cases to notify about - * the switch progress (see notifier_callback_type_t). When called, the type of the notification - * is passed as a parameter along with the reference to the target configuration structure (see notifier_notification_block_t) - * and any data passed during the callback registration. - * When notified before the configuration switch, depending on the configuration switch policy (see - * notifier_policy_t), the callback may deny the execution of the user function by returning an error code different - * than kStatus_Success (see NOTIFIER_SwitchConfig()). - * - * @param notify Notification block. - * @param data Callback data. Refers to the data passed during callback registration. Intended to - * pass any driver or application data such as internal state information. - * @return An error code or kStatus_Success. - */ -typedef status_t (*notifier_callback_t)(notifier_notification_block_t *notify, void *data); - -/*! - * @brief Callback configuration structure. - * - * This structure holds the configuration of callbacks. - * Callbacks of this type are expected to be statically allocated. - * This structure contains the following application-defined data. - * callback - pointer to the callback function - * callbackType - specifies when the callback is called - * callbackData - pointer to the data passed to the callback. - */ -typedef struct _notifier_callback_config -{ - notifier_callback_t callback; /*!< Pointer to the callback function. */ - notifier_callback_type_t callbackType; /*!< Callback type. */ - void *callbackData; /*!< Pointer to the data passed to the callback. */ -} notifier_callback_config_t; - -/*! - * @brief Notifier handle structure. - * - * Notifier handle structure. Contains data necessary for the Notifier proper function. - * Stores references to registered configurations, callbacks, information about their numbers, - * user function, user data, and other internal data. - * NOTIFIER_CreateHandle() must be called to initialize this handle. - */ -typedef struct _notifier_handle -{ - notifier_user_config_t **configsTable; /*!< Pointer to configure table. */ - uint8_t configsNumber; /*!< Number of configurations. */ - notifier_callback_config_t *callbacksTable; /*!< Pointer to callback table. */ - uint8_t callbacksNumber; /*!< Maximum number of callback configurations. */ - uint8_t errorCallbackIndex; /*!< Index of callback returns error. */ - uint8_t currentConfigIndex; /*!< Index of current configuration. */ - notifier_user_function_t userFunction; /*!< User function. */ - void *userData; /*!< User data passed to user function. */ -} notifier_handle_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Creates a Notifier handle. - * - * @param notifierHandle A pointer to the notifier handle. - * @param configs A pointer to an array with references to all configurations which is handled by the Notifier. - * @param configsNumber Number of configurations. Size of the configuration array. - * @param callbacks A pointer to an array of callback configurations. - * If there are no callbacks to register during Notifier initialization, use NULL value. - * @param callbacksNumber Number of registered callbacks. Size of the callbacks array. - * @param userFunction User function. - * @param userData User data passed to user function. - * @return An error Code or kStatus_Success. - */ -status_t NOTIFIER_CreateHandle(notifier_handle_t *notifierHandle, - notifier_user_config_t **configs, - uint8_t configsNumber, - notifier_callback_config_t *callbacks, - uint8_t callbacksNumber, - notifier_user_function_t userFunction, - void *userData); - -/*! - * @brief Switches the configuration according to a pre-defined structure. - * - * This function sets the system to the target configuration. Before transition, - * the Notifier sends notifications to all callbacks registered to the callback table. - * Callbacks are invoked in the following order: All registered callbacks are notified - * ordered by index in the callbacks array. The same order is used for before and after switch notifications. - * The notifications before the configuration switch can be used to obtain confirmation about - * the change from registered callbacks. If any registered callback denies the - * configuration change, further execution of this function depends on the notifier policy: the - * configuration change is either forced (kNOTIFIER_PolicyForcible) or exited (kNOTIFIER_PolicyAgreement). - * When configuration change is forced, the result of the before switch notifications are ignored. If an - * agreement is required, if any callback returns an error code, further notifications - * before switch notifications are cancelled and all already notified callbacks are re-invoked. - * The index of the callback which returned error code during pre-switch notifications is stored - * (any error codes during callbacks re-invocation are ignored) and NOTIFIER_GetErrorCallback() can be used to get it. - * Regardless of the policies, if any callback returns an error code, an error code indicating in which phase - * the error occurred is returned when NOTIFIER_SwitchConfig() exits. - * @param notifierHandle pointer to notifier handle - * @param configIndex Index of the target configuration. - * @param policy Transaction policy, kNOTIFIER_PolicyAgreement or kNOTIFIER_PolicyForcible. - * - * @return An error code or kStatus_Success. - * - */ -status_t NOTIFIER_SwitchConfig(notifier_handle_t *notifierHandle, uint8_t configIndex, notifier_policy_t policy); - -/*! - * @brief This function returns the last failed notification callback. - * - * This function returns an index of the last callback that failed during the configuration switch while - * the last NOTIFIER_SwitchConfig() was called. If the last NOTIFIER_SwitchConfig() call ended successfully - * value equal to callbacks number is returned. The returned value represents an index in the array of - * static call-backs. - * - * @param notifierHandle Pointer to the notifier handle - * @return Callback Index of the last failed callback or value equal to callbacks count. - */ -uint8_t NOTIFIER_GetErrorCallbackIndex(notifier_handle_t *notifierHandle); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_NOTIFIER_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_shell.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_shell.c deleted file mode 100644 index e8030ea68b7..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_shell.c +++ /dev/null @@ -1,651 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * POSIX getopt for Windows - * Code given out at the 1985 UNIFORUM conference in Dallas. - * - * From std-unix@ut-sally.UUCP (Moderator, John Quarterman) Sun Nov 3 14:34:15 1985 - * Relay-Version: version B 2.10.3 4.3bsd-beta 6/6/85; site gatech.CSNET - * Posting-Version: version B 2.10.2 9/18/84; site ut-sally.UUCP - * Path: gatech!akgua!mhuxv!mhuxt!mhuxr!ulysses!allegra!mit-eddie!genrad!panda!talcott!harvard!seismo!ut-sally!std-unix - * From: std-unix@ut-sally.UUCP (Moderator, John Quarterman) - * Newsgroups: mod.std.unix - * Subject: public domain AT&T getopt source - * Message-ID: <3352@ut-sally.UUCP> - * Date: 3 Nov 85 19:34:15 GMT - * Date-Received: 4 Nov 85 12:25:09 GMT - * Organization: IEEE/P1003 Portable Operating System Environment Committee - * Lines: 91 - * Approved: jsq@ut-sally.UUC - * Here's something you've all been waiting for: the AT&T public domain - * source for getopt(3). It is the code which was given out at the 1985 - * UNIFORUM conference in Dallas. I obtained it by electronic mail - * directly from AT&T. The people there assure me that it is indeed - * in the public domain - * There is no manual page. That is because the one they gave out at - * UNIFORUM was slightly different from the current System V Release 2 - * manual page. The difference apparently involved a note about the - * famous rules 5 and 6, recommending using white space between an option - * and its first argument, and not grouping options that have arguments. - * Getopt itself is currently lenient about both of these things White - * space is allowed, but not mandatory, and the last option in a group can - * have an argument. That particular version of the man page evidently - * has no official existence, and my source at AT&T did not send a copy. - * The current SVR2 man page reflects the actual behavor of this getopt. - * However, I am not about to post a copy of anything licensed by AT&T. - */ - -#include -#include "fsl_shell.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define KEY_ESC (0x1BU) -#define KET_DEL (0x7FU) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -static int32_t HelpCommand(p_shell_context_t context, int32_t argc, char **argv); /*!< help command */ - -static int32_t ExitCommand(p_shell_context_t context, int32_t argc, char **argv); /*!< exit command */ - -static int32_t ParseLine(const char *cmd, uint32_t len, char *argv[SHELL_MAX_ARGS]); /*!< parse line command */ - -static int32_t StrCompare(const char *str1, const char *str2, int32_t count); /*!< compare string command */ - -static void ProcessCommand(p_shell_context_t context, const char *cmd); /*!< process a command */ - -static void GetHistoryCommand(p_shell_context_t context, uint8_t hist_pos); /*!< get commands history */ - -static void AutoComplete(p_shell_context_t context); /*!< auto complete command */ - -static uint8_t GetChar(p_shell_context_t context); /*!< get a char from communication interface */ - -static int32_t StrLen(const char *str); /*!< get string length */ - -static char *StrCopy(char *dest, const char *src, int32_t count); /*!< string copy */ - -/******************************************************************************* - * Variables - ******************************************************************************/ -static const shell_command_context_t xHelpCommand = {"help", "\r\n\"help\": Lists all the registered commands\r\n", - HelpCommand, 0}; - -static const shell_command_context_t xExitCommand = {"exit", "\r\n\"exit\": Exit program\r\n", ExitCommand, 0}; - -static shell_command_context_list_t g_RegisteredCommands; - -static char g_paramBuffer[SHELL_BUFFER_SIZE]; - -/******************************************************************************* - * Code - ******************************************************************************/ -void SHELL_Init( - p_shell_context_t context, send_data_cb_t send_cb, recv_data_cb_t recv_cb, printf_data_t shell_printf, char *prompt) -{ - assert(send_cb != NULL); - assert(recv_cb != NULL); - assert(prompt != NULL); - assert(shell_printf != NULL); - - /* Memset for context */ - memset(context, 0, sizeof(shell_context_struct)); - context->send_data_func = send_cb; - context->recv_data_func = recv_cb; - context->printf_data_func = shell_printf; - context->prompt = prompt; - - SHELL_RegisterCommand(&xHelpCommand); - SHELL_RegisterCommand(&xExitCommand); -} - -int32_t SHELL_Main(p_shell_context_t context) -{ - uint8_t ch; - int32_t i; - - if (!context) - { - return -1; - } - - context->exit = false; - context->printf_data_func("\r\nSHELL (build: %s)\r\n", __DATE__); - context->printf_data_func("Copyright (c) 2017 NXP Semiconductor\r\n"); - context->printf_data_func(context->prompt); - - while (1) - { - if (context->exit) - { - break; - } - ch = GetChar(context); - /* If error occured when getting a char, continue to receive a new char. */ - if ((uint8_t)(-1) == ch) - { - continue; - } - /* Special key */ - if (ch == KEY_ESC) - { - context->stat = kSHELL_Special; - continue; - } - else if (context->stat == kSHELL_Special) - { - /* Function key */ - if (ch == '[') - { - context->stat = kSHELL_Function; - continue; - } - context->stat = kSHELL_Normal; - } - else if (context->stat == kSHELL_Function) - { - context->stat = kSHELL_Normal; - - switch ((uint8_t)ch) - { - /* History operation here */ - case 'A': /* Up key */ - GetHistoryCommand(context, context->hist_current); - if (context->hist_current < (context->hist_count - 1)) - { - context->hist_current++; - } - break; - case 'B': /* Down key */ - GetHistoryCommand(context, context->hist_current); - if (context->hist_current > 0) - { - context->hist_current--; - } - break; - case 'D': /* Left key */ - if (context->c_pos) - { - context->printf_data_func("\b"); - context->c_pos--; - } - break; - case 'C': /* Right key */ - if (context->c_pos < context->l_pos) - { - context->printf_data_func("%c", context->line[context->c_pos]); - context->c_pos++; - } - break; - default: - break; - } - continue; - } - /* Handle tab key */ - else if (ch == '\t') - { -#if SHELL_AUTO_COMPLETE - /* Move the cursor to the beginning of line */ - for (i = 0; i < context->c_pos; i++) - { - context->printf_data_func("\b"); - } - /* Do auto complete */ - AutoComplete(context); - /* Move position to end */ - context->c_pos = context->l_pos = StrLen(context->line); -#endif - continue; - } -#if SHELL_SEARCH_IN_HIST - /* Search command in history */ - else if ((ch == '`') && (context->l_pos == 0) && (context->line[0] == 0x00)) - { - } -#endif - /* Handle backspace key */ - else if ((ch == KET_DEL) || (ch == '\b')) - { - /* There must be at last one char */ - if (context->c_pos == 0) - { - continue; - } - - context->l_pos--; - context->c_pos--; - - if (context->l_pos > context->c_pos) - { - memmove(&context->line[context->c_pos], &context->line[context->c_pos + 1], - context->l_pos - context->c_pos); - context->line[context->l_pos] = 0; - context->printf_data_func("\b%s \b", &context->line[context->c_pos]); - - /* Reset position */ - for (i = context->c_pos; i <= context->l_pos; i++) - { - context->printf_data_func("\b"); - } - } - else /* Normal backspace operation */ - { - context->printf_data_func("\b \b"); - context->line[context->l_pos] = 0; - } - continue; - } - else - { - } - - /* Input too long */ - if (context->l_pos >= (SHELL_BUFFER_SIZE - 1)) - { - context->l_pos = 0; - } - - /* Handle end of line, break */ - if ((ch == '\r') || (ch == '\n')) - { - static char endoflinechar = 0U; - - if ((endoflinechar != 0U) && (endoflinechar != ch)) - { - continue; - } - else - { - endoflinechar = ch; - context->printf_data_func("\r\n"); - /* If command line is NULL, will start a new transfer */ - if (0U == StrLen(context->line)) - { - context->printf_data_func(context->prompt); - continue; - } - ProcessCommand(context, context->line); - /* Reset all params */ - context->c_pos = context->l_pos = 0; - context->hist_current = 0; - context->printf_data_func(context->prompt); - memset(context->line, 0, sizeof(context->line)); - continue; - } - } - - /* Normal character */ - if (context->c_pos < context->l_pos) - { - memmove(&context->line[context->c_pos + 1], &context->line[context->c_pos], - context->l_pos - context->c_pos); - context->line[context->c_pos] = ch; - context->printf_data_func("%s", &context->line[context->c_pos]); - /* Move the cursor to new position */ - for (i = context->c_pos; i < context->l_pos; i++) - { - context->printf_data_func("\b"); - } - } - else - { - context->line[context->l_pos] = ch; - context->printf_data_func("%c", ch); - } - - ch = 0; - context->l_pos++; - context->c_pos++; - } - return 0; -} - -static int32_t HelpCommand(p_shell_context_t context, int32_t argc, char **argv) -{ - uint8_t i = 0; - - for (i = 0; i < g_RegisteredCommands.numberOfCommandInList; i++) - { - context->printf_data_func(g_RegisteredCommands.CommandList[i]->pcHelpString); - } - return 0; -} - -static int32_t ExitCommand(p_shell_context_t context, int32_t argc, char **argv) -{ - /* Skip warning */ - context->printf_data_func("\r\nSHELL exited\r\n"); - context->exit = true; - return 0; -} - -static void ProcessCommand(p_shell_context_t context, const char *cmd) -{ - static const shell_command_context_t *tmpCommand = NULL; - static const char *tmpCommandString; - int32_t argc; - char *argv[SHELL_BUFFER_SIZE]; - uint8_t flag = 1; - uint8_t tmpCommandLen; - uint8_t tmpLen; - uint8_t i = 0; - - tmpLen = StrLen(cmd); - argc = ParseLine(cmd, tmpLen, argv); - - if ((tmpCommand == NULL) && (argc > 0)) - { - for (i = 0; i < g_RegisteredCommands.numberOfCommandInList; i++) - { - tmpCommand = g_RegisteredCommands.CommandList[i]; - tmpCommandString = tmpCommand->pcCommand; - tmpCommandLen = StrLen(tmpCommandString); - /* Compare with space or end of string */ - if ((cmd[tmpCommandLen] == ' ') || (cmd[tmpCommandLen] == 0x00)) - { - if (StrCompare(tmpCommandString, argv[0], tmpCommandLen) == 0) - { - /* support commands with optional number of parameters */ - if (tmpCommand->cExpectedNumberOfParameters == SHELL_OPTIONAL_PARAMS) - { - flag = 0; - } - else if ((tmpCommand->cExpectedNumberOfParameters == 0) && (argc == 1)) - { - flag = 0; - } - else if (tmpCommand->cExpectedNumberOfParameters > 0) - { - if ((argc - 1) == tmpCommand->cExpectedNumberOfParameters) - { - flag = 0; - } - } - else - { - flag = 1; - } - break; - } - } - } - } - - if ((tmpCommand != NULL) && (flag == 1U)) - { - context->printf_data_func( - "\r\nIncorrect command parameter(s). Enter \"help\" to view a list of available commands.\r\n\r\n"); - tmpCommand = NULL; - } - else if (tmpCommand != NULL) - { - tmpLen = StrLen(cmd); - /* Compare with last command. Push back to history buffer if different */ - if (tmpLen != StrCompare(cmd, context->hist_buf[0], StrLen(cmd))) - { - for (i = SHELL_HIST_MAX - 1; i > 0; i--) - { - memset(context->hist_buf[i], '\0', SHELL_BUFFER_SIZE); - tmpLen = StrLen(context->hist_buf[i - 1]); - StrCopy(context->hist_buf[i], context->hist_buf[i - 1], tmpLen); - } - memset(context->hist_buf[0], '\0', SHELL_BUFFER_SIZE); - tmpLen = StrLen(cmd); - StrCopy(context->hist_buf[0], cmd, tmpLen); - if (context->hist_count < SHELL_HIST_MAX) - { - context->hist_count++; - } - } - tmpCommand->pFuncCallBack(context, argc, argv); - tmpCommand = NULL; - } - else - { - context->printf_data_func( - "\r\nCommand not recognised. Enter 'help' to view a list of available commands.\r\n\r\n"); - tmpCommand = NULL; - } -} - -static void GetHistoryCommand(p_shell_context_t context, uint8_t hist_pos) -{ - uint8_t i; - uint32_t tmp; - - if (context->hist_buf[0][0] == '\0') - { - context->hist_current = 0; - return; - } - if (hist_pos >= SHELL_HIST_MAX) - { - hist_pos = SHELL_HIST_MAX - 1; - } - tmp = StrLen(context->line); - /* Clear current if have */ - if (tmp > 0) - { - memset(context->line, '\0', tmp); - for (i = 0; i < tmp; i++) - { - context->printf_data_func("\b \b"); - } - } - - context->l_pos = StrLen(context->hist_buf[hist_pos]); - context->c_pos = context->l_pos; - StrCopy(context->line, context->hist_buf[hist_pos], context->l_pos); - context->printf_data_func(context->hist_buf[hist_pos]); -} - -static void AutoComplete(p_shell_context_t context) -{ - int32_t len; - int32_t minLen; - uint8_t i = 0; - const shell_command_context_t *tmpCommand = NULL; - const char *namePtr; - const char *cmdName; - - minLen = 0; - namePtr = NULL; - - if (!StrLen(context->line)) - { - return; - } - context->printf_data_func("\r\n"); - /* Empty tab, list all commands */ - if (context->line[0] == '\0') - { - HelpCommand(context, 0, NULL); - return; - } - /* Do auto complete */ - for (i = 0; i < g_RegisteredCommands.numberOfCommandInList; i++) - { - tmpCommand = g_RegisteredCommands.CommandList[i]; - cmdName = tmpCommand->pcCommand; - if (StrCompare(context->line, cmdName, StrLen(context->line)) == 0) - { - if (minLen == 0) - { - namePtr = cmdName; - minLen = StrLen(namePtr); - /* Show possible matches */ - context->printf_data_func("%s\r\n", cmdName); - continue; - } - len = StrCompare(namePtr, cmdName, StrLen(namePtr)); - if (len < 0) - { - len = len * (-1); - } - if (len < minLen) - { - minLen = len; - } - } - } - /* Auto complete string */ - if (namePtr) - { - StrCopy(context->line, namePtr, minLen); - } - context->printf_data_func("%s%s", context->prompt, context->line); - return; -} - -static char *StrCopy(char *dest, const char *src, int32_t count) -{ - char *ret = dest; - int32_t i = 0; - - for (i = 0; i < count; i++) - { - dest[i] = src[i]; - } - - return ret; -} - -static int32_t StrLen(const char *str) -{ - int32_t i = 0; - - while (*str) - { - str++; - i++; - } - return i; -} - -static int32_t StrCompare(const char *str1, const char *str2, int32_t count) -{ - while (count--) - { - if (*str1++ != *str2++) - { - return *(unsigned char *)(str1 - 1) - *(unsigned char *)(str2 - 1); - } - } - return 0; -} - -static int32_t ParseLine(const char *cmd, uint32_t len, char *argv[SHELL_MAX_ARGS]) -{ - uint32_t argc; - char *p; - uint32_t position; - - /* Init params */ - memset(g_paramBuffer, '\0', len + 1); - StrCopy(g_paramBuffer, cmd, len); - - p = g_paramBuffer; - position = 0; - argc = 0; - - while (position < len) - { - /* Skip all blanks */ - while (((char)(*p) == ' ') && (position < len)) - { - *p = '\0'; - p++; - position++; - } - /* Process begin of a string */ - if (*p == '"') - { - p++; - position++; - argv[argc] = p; - argc++; - /* Skip this string */ - while ((*p != '"') && (position < len)) - { - p++; - position++; - } - /* Skip '"' */ - *p = '\0'; - p++; - position++; - } - else /* Normal char */ - { - argv[argc] = p; - argc++; - while (((char)*p != ' ') && ((char)*p != '\t') && (position < len)) - { - p++; - position++; - } - } - } - return argc; -} - -int32_t SHELL_RegisterCommand(const shell_command_context_t *command_context) -{ - int32_t result = 0; - - /* If have room in command list */ - if (g_RegisteredCommands.numberOfCommandInList < SHELL_MAX_CMD) - { - g_RegisteredCommands.CommandList[g_RegisteredCommands.numberOfCommandInList++] = command_context; - } - else - { - result = -1; - } - return result; -} - -static uint8_t GetChar(p_shell_context_t context) -{ - uint8_t ch; - -#if SHELL_USE_FILE_STREAM - ch = fgetc(context->STDIN); -#else - context->recv_data_func(&ch, 1U); -#endif - return ch; -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_shell.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_shell.h deleted file mode 100644 index c1cc6225b65..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_shell.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_SHELL_H_ -#define _FSL_SHELL_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup SHELL - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief Macro to set on/off history feature. */ -#ifndef SHELL_USE_HISTORY -#define SHELL_USE_HISTORY (0U) -#endif - -/*! @brief Macro to set on/off history feature. */ -#ifndef SHELL_SEARCH_IN_HIST -#define SHELL_SEARCH_IN_HIST (1U) -#endif - -/*! @brief Macro to select method stream. */ -#ifndef SHELL_USE_FILE_STREAM -#define SHELL_USE_FILE_STREAM (0U) -#endif - -/*! @brief Macro to set on/off auto-complete feature. */ -#ifndef SHELL_AUTO_COMPLETE -#define SHELL_AUTO_COMPLETE (1U) -#endif - -/*! @brief Macro to set console buffer size. */ -#ifndef SHELL_BUFFER_SIZE -#define SHELL_BUFFER_SIZE (64U) -#endif - -/*! @brief Macro to set maximum arguments in command. */ -#ifndef SHELL_MAX_ARGS -#define SHELL_MAX_ARGS (8U) -#endif - -/*! @brief Macro to set maximum count of history commands. */ -#ifndef SHELL_HIST_MAX -#define SHELL_HIST_MAX (3U) -#endif - -/*! @brief Macro to set maximum count of commands. */ -#ifndef SHELL_MAX_CMD -#define SHELL_MAX_CMD (20U) -#endif - -/*! @brief Macro to bypass arguments check */ -#define SHELL_OPTIONAL_PARAMS (0xFF) - -/*! @brief Shell user send data callback prototype.*/ -typedef void (*send_data_cb_t)(uint8_t *buf, uint32_t len); - -/*! @brief Shell user receiver data callback prototype.*/ -typedef void (*recv_data_cb_t)(uint8_t *buf, uint32_t len); - -/*! @brief Shell user printf data prototype.*/ -typedef int (*printf_data_t)(const char *format, ...); - -/*! @brief A type for the handle special key. */ -typedef enum _fun_key_status -{ - kSHELL_Normal = 0U, /*!< Normal key */ - kSHELL_Special = 1U, /*!< Special key */ - kSHELL_Function = 2U, /*!< Function key */ -} fun_key_status_t; - -/*! @brief Data structure for Shell environment. */ -typedef struct _shell_context_struct -{ - char *prompt; /*!< Prompt string */ - enum _fun_key_status stat; /*!< Special key status */ - char line[SHELL_BUFFER_SIZE]; /*!< Consult buffer */ - uint8_t cmd_num; /*!< Number of user commands */ - uint8_t l_pos; /*!< Total line position */ - uint8_t c_pos; /*!< Current line position */ -#if SHELL_USE_FILE_STREAM - FILE *STDOUT, *STDIN, *STDERR; -#else - send_data_cb_t send_data_func; /*!< Send data interface operation */ - recv_data_cb_t recv_data_func; /*!< Receive data interface operation */ - printf_data_t printf_data_func; -#endif - uint16_t hist_current; /*!< Current history command in hist buff*/ - uint16_t hist_count; /*!< Total history command in hist buff*/ - char hist_buf[SHELL_HIST_MAX][SHELL_BUFFER_SIZE]; /*!< History buffer*/ - bool exit; /*!< Exit Flag*/ -} shell_context_struct, *p_shell_context_t; - -/*! @brief User command function prototype. */ -typedef int32_t (*cmd_function_t)(p_shell_context_t context, int32_t argc, char **argv); - -/*! @brief User command data structure. */ -typedef struct _shell_command_context -{ - const char *pcCommand; /*!< The command that is executed. For example "help". It must be all lower case. */ - char *pcHelpString; /*!< String that describes how to use the command. It should start with the command itself, - and end with "\r\n". For example "help: Returns a list of all the commands\r\n". */ - const cmd_function_t - pFuncCallBack; /*!< A pointer to the callback function that returns the output generated by the command. */ - uint8_t cExpectedNumberOfParameters; /*!< Commands expect a fixed number of parameters, which may be zero. */ -} shell_command_context_t; - -/*! @brief Structure list command. */ -typedef struct _shell_command_context_list -{ - const shell_command_context_t *CommandList[SHELL_MAX_CMD]; /*!< The command table list */ - uint8_t numberOfCommandInList; /*!< The total command in list */ -} shell_command_context_list_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name Shell functional operation - * @{ - */ - -/*! -* @brief Enables the clock gate and configures the Shell module according to the configuration structure. -* -* This function must be called before calling all other Shell functions. -* Call operation the Shell commands with user-defined settings. -* The example below shows how to set up the middleware Shell and -* how to call the SHELL_Init function by passing in these parameters. -* This is an example. -* @code -* shell_context_struct user_context; -* SHELL_Init(&user_context, SendDataFunc, ReceiveDataFunc, "SHELL>> "); -* @endcode -* @param context The pointer to the Shell environment and runtime states. -* @param send_cb The pointer to call back send data function. -* @param recv_cb The pointer to call back receive data function. -* @param prompt The string prompt of Shell -*/ -void SHELL_Init(p_shell_context_t context, - send_data_cb_t send_cb, - recv_data_cb_t recv_cb, - printf_data_t shell_printf, - char *prompt); - -/*! - * @brief Shell register command. - * @param command_context The pointer to the command data structure. - * @return -1 if error or 0 if success - */ -int32_t SHELL_RegisterCommand(const shell_command_context_t *command_context); - -/*! - * @brief Main loop for Shell. - * Main loop for Shell; After this function is called, Shell begins to initialize the basic variables and starts to - * work. - * @param context The pointer to the Shell environment and runtime states. - * @return This function does not return until Shell command exit was called. - */ -int32_t SHELL_Main(p_shell_context_t context); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_SHELL_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_ucwxp.inf b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_ucwxp.inf deleted file mode 100644 index e9e9e4f02fd..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_ucwxp.inf +++ /dev/null @@ -1,104 +0,0 @@ -[Version] -Signature="$Windows NT$" -Class=Ports -ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318} -Provider=%MFGNAME% -LayoutFile=layout.inf -CatalogFile=%MFGFILENAME%.cat -DriverVer=02/16/2011,1.0 - -[Manufacturer] -%MFGNAME%=DeviceList, NTamd64 - -[DestinationDirs] -DefaultDestDir=12 - - -;------------------------------------------------------------------------------ -; Windows 2000/XP/Vista-32bit Sections -;------------------------------------------------------------------------------ - -[DriverInstall.nt] -include=mdmcpq.inf -CopyFiles=DriverCopyFiles.nt -AddReg=DriverInstall.nt.AddReg - -[DriverCopyFiles.nt] -usbser.sys,,,0x20 - -[DriverInstall.nt.AddReg] -HKR,,DevLoader,,*ntkern -HKR,,NTMPDriver,,%DRIVERFILENAME%.sys -HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" - -[DriverInstall.nt.Services] -AddService=usbser, 0x00000002, DriverService.nt - -[DriverService.nt] -DisplayName=%SERVICE% -ServiceType=1 -StartType=3 -ErrorControl=1 -ServiceBinary=%12%\%DRIVERFILENAME%.sys - -;------------------------------------------------------------------------------ -; Vista-64bit Sections -;------------------------------------------------------------------------------ - -[DriverInstall.NTamd64] -include=mdmcpq.inf -CopyFiles=DriverCopyFiles.NTamd64 -AddReg=DriverInstall.NTamd64.AddReg - -[DriverCopyFiles.NTamd64] -%DRIVERFILENAME%.sys,,,0x20 - -[DriverInstall.NTamd64.AddReg] -HKR,,DevLoader,,*ntkern -HKR,,NTMPDriver,,%DRIVERFILENAME%.sys -HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" - -[DriverInstall.NTamd64.Services] -AddService=usbser, 0x00000002, DriverService.NTamd64 - -[DriverService.NTamd64] -DisplayName=%SERVICE% -ServiceType=1 -StartType=3 -ErrorControl=1 -ServiceBinary=%12%\%DRIVERFILENAME%.sys - - -;------------------------------------------------------------------------------ -; Vendor and Product ID Definitions -;------------------------------------------------------------------------------ -; When developing your USB device, the VID and PID used in the PC side -; application program and the firmware on the microcontroller must match. -; Modify the below line to use your VID and PID. Use the format as shown below. -; Note: One INF file can be used for multiple devices with different VID and PIDs. -; For each supported device, append ",USB\VID_xxxx&PID_yyyy" to the end of the line. -;------------------------------------------------------------------------------ -[SourceDisksFiles] -[SourceDisksNames] -[DeviceList] -%DESCRIPTION%=DriverInstall, USB\VID_1FC9&PID_0300 -%DESCRIPTION%=DriverInstall, USB\VID_1FC9&PID_0800&MI_00 - -[DeviceList.NTamd64] -%DESCRIPTION% = DriverInstall, USB\VID_1FC9&PID_0300 -%DESCRIPTION% = DriverInstall, USB\VID_1FC9&PID_0800&MI_00 - - -;------------------------------------------------------------------------------ -; String Definitions -;------------------------------------------------------------------------------ -;Modify these strings to customize your device -;------------------------------------------------------------------------------ -[Strings] -MFGFILENAME="CDC" -DRIVERFILENAME ="usbser" -MFGNAME="NXP" -INSTDISK="NXP CDC Driver Installer" -DESCRIPTION="Virtual Com Port" -SERVICE="NXP Virtual COM Driver" - diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/fsl_io.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/fsl_io.c deleted file mode 100644 index 434564150d8..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/fsl_io.c +++ /dev/null @@ -1,815 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "fsl_io.h" -#include "fsl_debug_console_conf.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* check avaliable device */ -#if (defined(FSL_FEATURE_SOC_UART_COUNT) && (FSL_FEATURE_SOC_UART_COUNT != 0)) -#define DEBUG_CONSOLE_IO_UART -#endif - -#if (defined(FSL_FEATURE_SOC_IUART_COUNT) && (FSL_FEATURE_SOC_IUART_COUNT != 0)) -#define DEBUG_CONSOLE_IO_IUART -#endif - -#if (defined(FSL_FEATURE_SOC_LPUART_COUNT) && (FSL_FEATURE_SOC_LPUART_COUNT != 0)) -#define DEBUG_CONSOLE_IO_LPUART -#endif - -#if (defined(FSL_FEATURE_SOC_LPSCI_COUNT) && (FSL_FEATURE_SOC_LPSCI_COUNT != 0)) -#define DEBUG_CONSOLE_IO_LPSCI -#endif - -#if ((defined(FSL_FEATURE_SOC_USB_COUNT) && (FSL_FEATURE_SOC_USB_COUNT != 0)) && \ - (defined(BOARD_USE_VIRTUALCOM) && (BOARD_USE_VIRTUALCOM != 0))) -#define DEBUG_CONSOLE_IO_USBCDC -#endif - -#if (defined(FSL_FEATURE_SOC_FLEXCOMM_COUNT) && (FSL_FEATURE_SOC_FLEXCOMM_COUNT != 0)) -#define DEBUG_CONSOLE_IO_FLEXCOMM -#endif - -#if (defined(FSL_FEATURE_SOC_VFIFO_COUNT) && (FSL_FEATURE_SOC_VFIFO_COUNT != 0)) -#define DEBUG_CONSOLE_IO_VUSART -#endif - -/* If none of above io is supported, enable the swo for debug console, or swo can be enabled by define - * DEBUG_CONSOLE_IO_SWO directly */ -#if (!defined(DEBUG_CONSOLE_IO_SWO) && !defined(DEBUG_CONSOLE_IO_UART) && !defined(DEBUG_CONSOLE_IO_IUART) && \ -!defined(DEBUG_CONSOLE_IO_LPUART) && \ - !defined(DEBUG_CONSOLE_IO_LPSCI) && !defined(DEBUG_CONSOLE_IO_USBCDC) && \ -!defined(DEBUG_CONSOLE_IO_FLEXCOMM) && \ - !defined(DEBUG_CONSOLE_IO_VUSART)) -#define DEBUG_CONSOLE_IO_SWO -#endif - -/* configuration for debug console device */ -/* If new device is required as the low level device for debug console, - * Add the #elif branch and add the preprocessor macro to judge whether - * this kind of device exist in this SOC. */ -#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART) -#include "fsl_uart.h" -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -static uart_handle_t s_ioUartHandler; -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ -#endif /* defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART */ - -#if defined DEBUG_CONSOLE_IO_LPUART -#include "fsl_lpuart.h" -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -static lpuart_handle_t s_ioLpuartHandler; -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ -#endif /* DEBUG_CONSOLE_IO_LPUART */ - -#if defined DEBUG_CONSOLE_IO_LPSCI -#include "fsl_lpsci.h" -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -static lpsci_handle_t s_ioLpsciHandler; -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ -#endif /* DEBUG_CONSOLE_IO_LPSCI */ - -#if defined DEBUG_CONSOLE_IO_USBCDC -#include "usb_device_config.h" -#include "usb.h" -#include "usb_device_cdc_acm.h" -#include "usb_device_ch9.h" -#include "virtual_com.h" -#endif /* DEBUG_CONSOLE_IO_USBCDC */ - -#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART) -#include "fsl_usart.h" -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -static usart_handle_t s_ioUsartHandler; -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ -#endif /* defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART */ - -#if defined DEBUG_CONSOLE_IO_SWO -#include "fsl_swo.h" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Debug console IO state information. */ -static io_state_t s_debugConsoleIO = { - .ioBase = NULL, - .ioType = DEBUG_CONSOLE_DEVICE_TYPE_NONE, -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING - .callBack = NULL, -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ -}; - -/******************************************************************************* - * Code - ******************************************************************************/ - -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING - -#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART) -static void UART_Callback(UART_Type *base, uart_handle_t *handle, status_t status, void *userData) -{ - bool tx = false, rx = false; - size_t size = 0U; - - if (status == kStatus_UART_RxIdle) - { - rx = true; - size = handle->txDataSizeAll; - } - - if (status == kStatus_UART_TxIdle) - { - tx = true; - size = handle->txDataSizeAll; - } - - /* inform the buffer layer that transfer is complete */ - if (s_debugConsoleIO.callBack != NULL) - { - /* call buffer callback function */ - s_debugConsoleIO.callBack(&size, rx, tx); - } -} -#endif /* defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART */ - -#if defined DEBUG_CONSOLE_IO_LPSCI -static void LPSCI_Callback(UART0_Type *base, lpsci_handle_t *handle, status_t status, void *userData) -{ - bool tx = false, rx = false; - size_t size = 0U; - - if (status == kStatus_LPSCI_RxIdle) - { - rx = true; - size = handle->txDataSizeAll; - } - - if (status == kStatus_LPSCI_TxIdle) - { - tx = true; - size = handle->txDataSizeAll; - } - - /* inform the buffer layer that transfer is complete */ - if (s_debugConsoleIO.callBack != NULL) - { - /* call buffer callback function */ - s_debugConsoleIO.callBack(&size, rx, tx); - } -} -#endif /* DEBUG_CONSOLE_IO_LPSCI */ - -#if defined DEBUG_CONSOLE_IO_LPUART -static void LPUART_Callback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData) -{ - bool tx = false, rx = false; - size_t size = 0U; - - if (status == kStatus_LPUART_RxIdle) - { - rx = true; - size = handle->txDataSizeAll; - } - - if (status == kStatus_LPUART_TxIdle) - { - tx = true; - size = handle->txDataSizeAll; - } - - /* inform the buffer layer that transfer is complete */ - if (s_debugConsoleIO.callBack != NULL) - { - /* call buffer callback function */ - s_debugConsoleIO.callBack(&size, rx, tx); - } -} -#endif /* DEBUG_CONSOLE_IO_LPUART */ - -#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART) -static void USART_Callback(USART_Type *base, usart_handle_t *handle, status_t status, void *userData) -{ - bool tx = false, rx = false; - size_t size = 0U; - - if (status == kStatus_USART_RxIdle) - { - rx = true; - size = handle->txDataSizeAll; - } - - if (status == kStatus_USART_TxIdle) - { - tx = true; - size = handle->txDataSizeAll; - } - - /* inform the buffer layer that transfer is complete */ - if (s_debugConsoleIO.callBack != NULL) - { - /* call buffer callback function */ - s_debugConsoleIO.callBack(&size, rx, tx); - } -} -#endif /* defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART */ -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ - -void IO_Init(io_state_t *io, uint32_t baudRate, uint32_t clkSrcFreq, uint8_t *ringBuffer) -{ - assert(NULL != io); - - /* record device type/base */ - s_debugConsoleIO.ioType = io->ioType; - s_debugConsoleIO.ioBase = (void *)(io->ioBase); - - switch (s_debugConsoleIO.ioType) - { -#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART) - case DEBUG_CONSOLE_DEVICE_TYPE_UART: - case DEBUG_CONSOLE_DEVICE_TYPE_IUART: - { - uart_config_t uart_config; - UART_GetDefaultConfig(&uart_config); - uart_config.baudRate_Bps = baudRate; - /* Enable clock and initial UART module follow user configure structure. */ - UART_Init((UART_Type *)s_debugConsoleIO.ioBase, &uart_config, clkSrcFreq); - UART_EnableTx(s_debugConsoleIO.ioBase, true); - UART_EnableRx(s_debugConsoleIO.ioBase, true); -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING - s_debugConsoleIO.callBack = io->callBack; - /* create handler for interrupt transfer */ - UART_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioUartHandler, UART_Callback, NULL); - /* start ring buffer */ - UART_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioUartHandler, ringBuffer, - DEBUG_CONSOLE_RECEIVE_BUFFER_LEN); -#endif - } - break; -#endif - -#if defined DEBUG_CONSOLE_IO_LPUART - case DEBUG_CONSOLE_DEVICE_TYPE_LPUART: - { - lpuart_config_t lpuart_config; - LPUART_GetDefaultConfig(&lpuart_config); - lpuart_config.baudRate_Bps = baudRate; - /* Enable clock and initial UART module follow user configure structure. */ - LPUART_Init((LPUART_Type *)s_debugConsoleIO.ioBase, &lpuart_config, clkSrcFreq); - LPUART_EnableTx(s_debugConsoleIO.ioBase, true); - LPUART_EnableRx(s_debugConsoleIO.ioBase, true); -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING - s_debugConsoleIO.callBack = io->callBack; - /* create handler for interrupt transfer */ - LPUART_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, LPUART_Callback, NULL); - /* start ring buffer */ - LPUART_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, ringBuffer, - DEBUG_CONSOLE_RECEIVE_BUFFER_LEN); -#endif - } - break; -#endif -#if defined DEBUG_CONSOLE_IO_LPSCI - case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI: - { - lpsci_config_t lpsci_config; - LPSCI_GetDefaultConfig(&lpsci_config); - lpsci_config.baudRate_Bps = baudRate; - /* Enable clock and initial UART module follow user configure structure. */ - LPSCI_Init((UART0_Type *)s_debugConsoleIO.ioBase, &lpsci_config, clkSrcFreq); - LPSCI_EnableTx(s_debugConsoleIO.ioBase, true); - LPSCI_EnableRx(s_debugConsoleIO.ioBase, true); -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING - s_debugConsoleIO.callBack = io->callBack; - /* create handler for interrupt transfer */ - LPSCI_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, LPSCI_Callback, NULL); - /* start ring buffer */ - LPSCI_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, ringBuffer, - DEBUG_CONSOLE_RECEIVE_BUFFER_LEN); -#endif - } - break; -#endif -#if defined DEBUG_CONSOLE_IO_USBCDC - case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC: - { - s_debugConsoleIO.ioBase = USB_VcomInit(); - } - break; -#endif -#if defined DEBUG_CONSOLE_IO_FLEXCOMM - case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM: - { - usart_config_t usart_config; - USART_GetDefaultConfig(&usart_config); - usart_config.baudRate_Bps = baudRate; - /* Enable clock and initial UART module follow user configure structure. */ - USART_Init((USART_Type *)s_debugConsoleIO.ioBase, &usart_config, clkSrcFreq); -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING - s_debugConsoleIO.callBack = io->callBack; - /* create handler for interrupt transfer */ - USART_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioUsartHandler, USART_Callback, NULL); - /* start ring buffer */ - USART_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioUsartHandler, ringBuffer, - DEBUG_CONSOLE_RECEIVE_BUFFER_LEN); -#endif - } - break; -#endif -#if defined DEBUG_CONSOLE_IO_VUSART - case DEBUG_CONSOLE_DEVICE_TYPE_VUSART: - { - usart_config_t usart_config; - USART_GetDefaultConfig(&usart_config); - usart_config.baudRate_Bps = baudRate; - usart_config.enableRx = true; - usart_config.enableTx = true; - /* Enable rx fifo for user's continously input */ - usart_config.fifoConfig.enableRxFifo = true; - usart_config.fifoConfig.rxFifoSize = 8; - /* Enable clock and initial UART module follow user configure structure. */ - USART_Init((USART_Type *)s_debugConsoleIO.ioBase, &usart_config, clkSrcFreq); -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING - s_debugConsoleIO.callBack = io->callBack; - /* create handler for interrupt transfer */ - USART_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioUsartHandler, USART_Callback, NULL); - /* start ring buffer */ - USART_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioUsartHandler, ringBuffer, - DEBUG_CONSOLE_RECEIVE_BUFFER_LEN); -#endif - } - break; -#endif - -#if defined DEBUG_CONSOLE_IO_SWO - case DEBUG_CONSOLE_DEVICE_TYPE_SWO: - SWO_Init((uint32_t)s_debugConsoleIO.ioBase, baudRate, clkSrcFreq); - break; -#endif - default: - break; - } -} - -status_t IO_Deinit(void) -{ - if (s_debugConsoleIO.ioType == DEBUG_CONSOLE_DEVICE_TYPE_NONE) - { - return kStatus_Success; - } - - switch (s_debugConsoleIO.ioType) - { -#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART) - case DEBUG_CONSOLE_DEVICE_TYPE_UART: - case DEBUG_CONSOLE_DEVICE_TYPE_IUART: -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING - /* stop ring buffer */ - UART_TransferStopRingBuffer(s_debugConsoleIO.ioBase, &s_ioUartHandler); -#endif - /* Disable UART module. */ - UART_Deinit((UART_Type *)s_debugConsoleIO.ioBase); - - break; -#endif -#if defined DEBUG_CONSOLE_IO_LPSCI - case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI: -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING - /* stop ring buffer */ - LPSCI_TransferStopRingBuffer(s_debugConsoleIO.ioBase, &s_ioLpsciHandler); -#endif - /* Disable LPSCI module. */ - LPSCI_Deinit((UART0_Type *)s_debugConsoleIO.ioBase); - - break; -#endif -#if defined DEBUG_CONSOLE_IO_LPUART - case DEBUG_CONSOLE_DEVICE_TYPE_LPUART: -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING - /* stop ring buffer */ - LPUART_TransferStopRingBuffer(s_debugConsoleIO.ioBase, &s_ioLpuartHandler); -#endif - /* Disable LPUART module. */ - LPUART_Deinit((LPUART_Type *)s_debugConsoleIO.ioBase); - - break; -#endif -#if defined DEBUG_CONSOLE_IO_USBCDC - case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC: - /* Disable USBCDC module. */ - USB_VcomDeinit(s_debugConsoleIO.ioBase); - break; -#endif -#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART) - case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM: - case DEBUG_CONSOLE_DEVICE_TYPE_VUSART: -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING - /* stop ring buffer */ - USART_TransferStopRingBuffer(s_debugConsoleIO.ioBase, &s_ioUsartHandler); -#endif - /* deinit IO */ - USART_Deinit((USART_Type *)s_debugConsoleIO.ioBase); - - break; -#endif - -#if defined DEBUG_CONSOLE_IO_SWO - - case DEBUG_CONSOLE_DEVICE_TYPE_SWO: - SWO_Deinit((uint32_t)s_debugConsoleIO.ioBase); - break; -#endif - default: - s_debugConsoleIO.ioType = DEBUG_CONSOLE_DEVICE_TYPE_NONE; - break; - } - - s_debugConsoleIO.ioType = DEBUG_CONSOLE_DEVICE_TYPE_NONE; - - return kStatus_Success; -} - -status_t IO_WaitIdle(void) -{ - switch (s_debugConsoleIO.ioType) - { -#if (defined DEBUG_CONSOLE_IO_UART) - case DEBUG_CONSOLE_DEVICE_TYPE_UART: - /* wait transfer complete flag */ - while (!(UART_GetStatusFlags(s_debugConsoleIO.ioBase) & kUART_TransmissionCompleteFlag)) - { - } - - break; -#endif - -#if (defined DEBUG_CONSOLE_IO_IUART) - case DEBUG_CONSOLE_DEVICE_TYPE_IUART: - /* wait transfer complete flag */ - while (!(UART_GetStatusFlag(s_debugConsoleIO.ioBase, kUART_TxCompleteFlag))) - { - } - - break; -#endif - -#if defined DEBUG_CONSOLE_IO_LPSCI - case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI: - /* wait transfer complete flag */ - while (!(LPSCI_GetStatusFlags(s_debugConsoleIO.ioBase) & kLPSCI_TransmissionCompleteFlag)) - { - } - - break; -#endif - -#if defined DEBUG_CONSOLE_IO_LPUART - case DEBUG_CONSOLE_DEVICE_TYPE_LPUART: - /* wait transfer complete flag */ - while (!(LPUART_GetStatusFlags(s_debugConsoleIO.ioBase) & kLPUART_TransmissionCompleteFlag)) - { - } - break; -#endif - -#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART) - case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM: - case DEBUG_CONSOLE_DEVICE_TYPE_VUSART: - /* wait transfer complete flag */ - while (!(USART_GetStatusFlags(s_debugConsoleIO.ioBase) & kUSART_TxFifoEmptyFlag)) - { - } - break; -#endif - default: - break; - } - - return kStatus_Success; -} - -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING - -status_t IO_Transfer(uint8_t *ch, size_t size, bool tx) -{ - status_t status = kStatus_Fail; - - switch (s_debugConsoleIO.ioType) - { -#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART) - case DEBUG_CONSOLE_DEVICE_TYPE_UART: - case DEBUG_CONSOLE_DEVICE_TYPE_IUART: - { - uart_transfer_t transfer = {0U}; - transfer.data = ch; - transfer.dataSize = size; - /* transfer data */ - if (tx) - { - status = UART_TransferSendNonBlocking(s_debugConsoleIO.ioBase, &s_ioUartHandler, &transfer); - } - else - { - status = UART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioUartHandler, &transfer, NULL); - } - } - break; -#endif -#if defined DEBUG_CONSOLE_IO_LPSCI - case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI: - { - lpsci_transfer_t transfer = {0U}; - transfer.data = ch; - transfer.dataSize = size; - /* transfer data */ - if (tx) - { - status = LPSCI_TransferSendNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, &transfer); - } - else - { - status = LPSCI_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, &transfer, NULL); - } - } - break; -#endif - -#if defined DEBUG_CONSOLE_IO_LPUART - case DEBUG_CONSOLE_DEVICE_TYPE_LPUART: - { - lpuart_transfer_t transfer = {0U}; - transfer.data = ch; - transfer.dataSize = size; - /* transfer data */ - if (tx) - { - status = LPUART_TransferSendNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, &transfer); - } - else - { - status = - LPUART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, &transfer, NULL); - } - } - break; -#endif - -#if defined DEBUG_CONSOLE_IO_USBCDC - case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC: - { - if (tx) - { - USB_VcomWriteBlocking(s_debugConsoleIO.ioBase, ch, size); - } - else - { - USB_VcomReadBlocking(s_debugConsoleIO.ioBase, ch, size); - } - } - break; -#endif - -#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART) - case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM: - case DEBUG_CONSOLE_DEVICE_TYPE_VUSART: - { - usart_transfer_t transfer = {0U}; - transfer.data = ch; - transfer.dataSize = size; - /* transfer data */ - if (tx) - { - status = USART_TransferSendNonBlocking(s_debugConsoleIO.ioBase, &s_ioUsartHandler, &transfer); - } - else - { - status = USART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioUsartHandler, &transfer, NULL); - } - } - break; -#endif - -#if defined DEBUG_CONSOLE_IO_SWO - case DEBUG_CONSOLE_DEVICE_TYPE_SWO: - status = SWO_SendBlocking((uint32_t)s_debugConsoleIO.ioBase, ch, size); - break; -#endif - default: - break; - } - - return status; -} - -status_t IO_TryReceiveCharacter(uint8_t *ch) -{ - status_t status = kStatus_Fail; - uint32_t size = 1U; - - switch (s_debugConsoleIO.ioType) - { -#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART) - case DEBUG_CONSOLE_DEVICE_TYPE_UART: - case DEBUG_CONSOLE_DEVICE_TYPE_IUART: - { - uart_transfer_t transfer = {0U}; - transfer.data = ch; - transfer.dataSize = size; - if (UART_TransferGetRxRingBufferLength(&s_ioUartHandler) >= size) - { - /* transfer data */ - status = UART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioUartHandler, &transfer, NULL); - } - } - break; -#endif -#if defined DEBUG_CONSOLE_IO_LPSCI - case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI: - { - lpsci_transfer_t transfer = {0U}; - transfer.data = ch; - transfer.dataSize = size; - if (LPSCI_TransferGetRxRingBufferLength(&s_ioLpsciHandler) >= size) - { - /* transfer data */ - status = LPSCI_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, &transfer, NULL); - } - } - break; -#endif - -#if defined DEBUG_CONSOLE_IO_LPUART - case DEBUG_CONSOLE_DEVICE_TYPE_LPUART: - { - lpuart_transfer_t transfer = {0U}; - transfer.data = ch; - transfer.dataSize = size; - if (LPUART_TransferGetRxRingBufferLength(s_debugConsoleIO.ioBase, &s_ioLpuartHandler) >= size) - { - /* transfer data */ - status = - LPUART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, &transfer, NULL); - } - } - break; -#endif - -#if defined DEBUG_CONSOLE_IO_USBCDC - case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC: - break; -#endif - -#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART) - case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM: - case DEBUG_CONSOLE_DEVICE_TYPE_VUSART: - { - usart_transfer_t transfer = {0U}; - transfer.data = ch; - transfer.dataSize = size; - if (USART_TransferGetRxRingBufferLength(&s_ioUsartHandler) >= size) - { - /* transfer data */ - status = USART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioUsartHandler, &transfer, NULL); - } - } - break; -#endif - default: - break; - } - - return status; -} - -#else - -status_t IO_Transfer(uint8_t *ch, size_t size, bool tx) -{ - status_t status = kStatus_Success; - switch (s_debugConsoleIO.ioType) - { -#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART) - case DEBUG_CONSOLE_DEVICE_TYPE_UART: - case DEBUG_CONSOLE_DEVICE_TYPE_IUART: - { - if (tx) - { - UART_WriteBlocking(s_debugConsoleIO.ioBase, ch, size); - } - else - { - status = UART_ReadBlocking(s_debugConsoleIO.ioBase, ch, size); - } - } - break; -#endif -#if defined DEBUG_CONSOLE_IO_LPSCI - case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI: - { - if (tx) - { - LPSCI_WriteBlocking(s_debugConsoleIO.ioBase, ch, size); - } - else - { - status = LPSCI_ReadBlocking(s_debugConsoleIO.ioBase, ch, size); - } - } - break; -#endif - -#if defined DEBUG_CONSOLE_IO_LPUART - case DEBUG_CONSOLE_DEVICE_TYPE_LPUART: - { - if (tx) - { - LPUART_WriteBlocking(s_debugConsoleIO.ioBase, ch, size); - } - else - { - status = LPUART_ReadBlocking(s_debugConsoleIO.ioBase, ch, size); - } - } - break; -#endif - -#if defined DEBUG_CONSOLE_IO_USBCDC - case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC: - { - if (tx) - { - USB_VcomWriteBlocking(s_debugConsoleIO.ioBase, ch, size); - } - else - { - status = USB_VcomReadBlocking(s_debugConsoleIO.ioBase, ch, size); - } - } - break; -#endif - -#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART) - case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM: - case DEBUG_CONSOLE_DEVICE_TYPE_VUSART: - { - if (tx) - { - USART_WriteBlocking(s_debugConsoleIO.ioBase, ch, size); - } - else - { - status = USART_ReadBlocking(s_debugConsoleIO.ioBase, ch, size); - } - } - break; -#endif - -#if defined DEBUG_CONSOLE_IO_SWO - case DEBUG_CONSOLE_DEVICE_TYPE_SWO: - status = SWO_SendBlocking((uint32_t)s_debugConsoleIO.ioBase, ch, size); - break; -#endif - default: - status = kStatus_Fail; - break; - } - - return status; -} - -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/fsl_io.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/fsl_io.h deleted file mode 100644 index 396f66c70f3..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/fsl_io.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _FSL_IO_H -#define _FSL_IO_H - -#include "fsl_common.h" - -/*! - * @addtogroup debugconsole - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief define a notify callback for IO -* @param size , transfer data size. -* @param rx, indicate a rx transfer is success. -* @param tx, indicate a tx transfer is success. -*/ -typedef void (*notify)(size_t *size, bool rx, bool tx); - -/*! @brief State structure storing io. */ -typedef struct io_State -{ - void *ioBase; /*!< Base of the IP register. */ - uint8_t ioType; /*!< device type */ -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING - notify callBack; /*!< define the callback function for buffer */ -#endif - -} io_state_t; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @brief io init function. - * - * Call this function to init IO. - * - * @param io configuration pointer - * @param baudRate baud rate - * @param clkSrcFreq clock freq - * @param ringbuffer used to receive character - */ -void IO_Init(io_state_t *io, uint32_t baudRate, uint32_t clkSrcFreq, uint8_t *ringBuffer); - -/*! - * @brief Deinit IO. - * - * Call this function to Deinit IO. - * - * @return deinit status - */ -status_t IO_Deinit(void); - -/*! - * @brief io transfer function. - * - * Call this function to transfer log. - * Print log: - * @code - * IO_Transfer(ch, size, true); - * @endcode - * Scanf log: - * @code - * IO_Transfer(ch, size, false); - * @endcode - * - * @param ch transfer buffer pointer - * @param size transfer size - * @param tx indicate the transfer is TX or RX - */ -status_t IO_Transfer(uint8_t *ch, size_t size, bool tx); - -/*! - * @brief io wait idle. - * - * Call this function to wait the io idle - * - * @return Indicates whether wait idle was successful or not. - */ -status_t IO_WaitIdle(void); - -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -/*! - * @brief io try to receive one character. - * - * Call this function try to receive character - * @param ch the address of char to receive - * @return Indicates try getchar was successful or not. - */ -status_t IO_TryReceiveCharacter(uint8_t *ch); -#endif - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @} */ - -#endif /* _FSL_IO_H */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/swo/fsl_swo.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/swo/fsl_swo.c deleted file mode 100644 index c1360a2c9f2..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/swo/fsl_swo.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2018 NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "fsl_swo.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* SWO encoding protocol definition */ -#ifndef FSL_DEBUG_CONSOLE_SWO_PROTOCOL -#define FSL_DEBUG_CONSOLE_SWO_PROTOCOL kSWO_ProtocolNrz -#endif -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -status_t SWO_Init(uint32_t port, uint32_t baudRate, uint32_t clkSrcFreq) -{ - assert(baudRate <= clkSrcFreq); - assert((clkSrcFreq / baudRate) <= TPI_ACPR_PRESCALER_Msk); - assert((TPI->DEVID & (kSWO_ProtocolNrz | kSWO_ProtocolManchester)) != 0U); - - uint32_t prescaler = clkSrcFreq / baudRate - 1U; - - /* enable the ITM and DWT units */ - CoreDebug->DEMCR = CoreDebug_DEMCR_TRCENA_Msk; - - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) == 0U) - { - return kStatus_Fail; - } - /* Lock access */ - ITM->LAR = 0xC5ACCE55U; - /* Disable ITM */ - ITM->TER &= ~(1U << port); - ITM->TCR = 0U; - /* select SWO encoding protocol */ - TPI->SPPR = FSL_DEBUG_CONSOLE_SWO_PROTOCOL; - /* select asynchronous clock prescaler */ - TPI->ACPR = prescaler & 0xFFFFU; - /* allow unprivilege access */ - ITM->TPR = 0U; - /* enable ITM */ - ITM->TCR = - ITM_TCR_ITMENA_Msk | ITM_TCR_SYNCENA_Msk | ITM_TCR_TraceBusID_Msk | ITM_TCR_SWOENA_Msk | ITM_TCR_DWTENA_Msk; - /* enable the port bits */ - ITM->TER = 1U << port; - - return kStatus_Success; -} - -void SWO_Deinit(uint32_t port) -{ - /* disable ITM */ - ITM->TER &= ~(1U << port); -} - -status_t SWO_SendBlocking(uint32_t port, uint8_t *ch, size_t size) -{ - assert(ch != NULL); - assert((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0U); - assert((ITM->TER & (1U << port)) != 0U); - - uint16_t *strAddr = (uint16_t *)ch; - - while (size) - { - /* wait FIFO ready */ - while (ITM->PORT[port].u32 == 0U) - { - } - - if (size >= 2U) - { - size -= 2U; - ITM->PORT[port].u16 = *strAddr; - } - else - { - size -= 1U; - ITM->PORT[port].u8 = *((uint8_t *)strAddr); - } - strAddr++; - } - - return kStatus_Success; -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/swo/fsl_swo.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/swo/fsl_swo.h deleted file mode 100644 index 94cd6516828..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/swo/fsl_swo.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2018 NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _FSL_SWO_H_ -#define _FSL_SWO_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup debugconsole - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* swo protocol */ -enum _swo_protocol -{ - kSWO_ProtocolManchester = 1U, /*!< SWO manchester protocol */ - kSWO_ProtocolNrz = 2U, /*!< SWO UART/NRZ protocol */ -}; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @brief io init function. - * - * Call this function to init SWO. - * - * @param port port used to transfer data - * @param baudRate SWO clock - * @param clkSrcFreq core clock frequency - */ -status_t SWO_Init(uint32_t port, uint32_t baudRate, uint32_t clkSrcFreq); - -/*! - * @brief Deinit IO. - * - * Call this function to Deinit SWO. - * - * @param port port to deinit. - * @return deinit status - */ -void SWO_Deinit(uint32_t port); - -/*! - * @brief io transfer function. - * - * Call this function to print log. - * - * @param port port used to transfer data - * @param ch transfer buffer pointer - * @param size transfer size - */ -status_t SWO_SendBlocking(uint32_t port, uint8_t *ch, size_t size); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @} */ - -#endif /* _FSL_SWO_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/log/fsl_log.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/log/fsl_log.c deleted file mode 100644 index e36832d36d1..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/log/fsl_log.c +++ /dev/null @@ -1,587 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "fsl_log.h" -#include "fsl_debug_console_conf.h" -#include "fsl_io.h" -#ifdef FSL_RTOS_FREE_RTOS -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" -#endif -/******************************************************************************* - * Definitions - ******************************************************************************/ -#ifndef BACKSPACE -/*! @brief character backspace ASCII value */ -#define BACKSPACE 127 -#endif - -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -/*! @brief increase pop member */ -#define LOG_CHECK_BUFFER_INDEX_OVERFLOW(index) \ - { \ - if (index >= DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN) \ - { \ - index -= DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN; \ - } \ - \ -\ -} - -/*! @brief get current runing environment is ISR or not */ -#ifdef __CA7_REV -#define IS_RUNNING_IN_ISR() SystemGetIRQNestingLevel() -#else -#define IS_RUNNING_IN_ISR() __get_IPSR() -#endif /* __CA7_REV */ - -#else -#define IS_RUNNING_IN_ISR() (0U) -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ - -/* define for rtos */ -#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) -/* metex semaphore */ -#define LOG_CREATE_MUTEX_SEMAPHORE(mutex) (mutex = xSemaphoreCreateMutex()) - -#define LOG_GIVE_MUTEX_SEMAPHORE(mutex) \ - \ -{ \ - if (IS_RUNNING_IN_ISR() == 0U) \ - { \ - xSemaphoreGive(mutex); \ - } \ - \ -} - -#define LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) \ - \ -{ \ - if (IS_RUNNING_IN_ISR() == 0U) \ - { \ - xSemaphoreTake(mutex, portMAX_DELAY); \ - } \ - \ -} - -#define LOG_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) \ - \ -{ \ - if (IS_RUNNING_IN_ISR() == 0U) \ - { \ - result = xSemaphoreTake(mutex, 0U); \ - } \ - else \ - { \ - result = 1U; \ - } \ - \ -} - -/* Binary semaphore */ -#define LOG_CREATE_BINARY_SEMAPHORE(binary) (binary = xSemaphoreCreateBinary()) -#define LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) (xSemaphoreTake(binary, portMAX_DELAY)) -#define LOG_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (xSemaphoreGiveFromISR(binary, NULL)) - -#elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) - -#define LOG_CREATE_MUTEX_SEMAPHORE(mutex) -#define LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) -#define LOG_GIVE_MUTEX_SEMAPHORE(mutex) -#define LOG_CREATE_BINARY_SEMAPHORE(binary) -#define LOG_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U) -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -#define LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) \ - \ -{ \ - while (!binary) \ - ; \ - binary = false; \ - \ -\ -} -#define LOG_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (binary = true) -#else -#define LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) -#define LOG_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ - -/* add other implementation here -*such as : -* #elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_xxx) -*/ - -#else - -#define LOG_CREATE_MUTEX_SEMAPHORE(mutex) -#define LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) -#define LOG_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U) -#define LOG_GIVE_MUTEX_SEMAPHORE(mutex) -#define LOG_CREATE_BINARY_SEMAPHORE(binary) -#define LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) -#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */ - -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -/*! @brief Define the buffer -* The total buffer size should be calucate as (BUFFER_SUPPORT_LOG_LENGTH + 1) * BUFFER_SUPPORT_LOG_NUM * 4 -*/ -typedef struct _log_buffer -{ - volatile uint16_t totalIndex; /*!< indicate the total usage of the buffer */ - volatile uint16_t pushIndex; /*!< indicate the next push index */ - volatile uint16_t popIndex; /*!< indicate the pop index */ - uint8_t txBuf[DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN]; /*!< buffer to store printf log */ - - uint8_t rxBuf[DEBUG_CONSOLE_RECEIVE_BUFFER_LEN]; /*!< buffer to store scanf log */ -} log_buffer_t; -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ - -/******************************************************************************* - * Variables - ******************************************************************************/ -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -/* A global log buffer */ -static log_buffer_t s_log_buffer; -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ - -/* lock definition */ -#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -static SemaphoreHandle_t s_logPushSemaphore = NULL; -static SemaphoreHandle_t s_logReadSemaphore = NULL; -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ -static SemaphoreHandle_t s_logPopSemaphore = NULL; -static SemaphoreHandle_t s_logReadWaitSemaphore = NULL; - -#elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) - -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING - -static volatile bool s_logReadWaitSemaphore = false; /* transferred event from ISR for bare-metal + interrupt */ - -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ - -#else -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ - -/******************************************************************************* -* Prototypes -******************************************************************************/ -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -/*! - * @brief callback function for IO layer to notify LOG - * - * @param size last transfer data size - * @param receive indicate a RX transfer - * @param transmit indicate a TX transfer - * - */ -static void LOG_Transferred(size_t *size, bool receive, bool transmit); - -/*! - * @brief log push function - * - * @param buf target buffer - * @param size log size - * - */ -static int LOG_BufPush(uint8_t *buf, size_t size); - -/*! - * @brief Get next avaliable log - * - * @param next avaliable size - * @return next avaliable address - */ -static uint8_t *LOG_BufGetNextAvaliableLog(size_t *size); - -/*! - * @brief buf pop - * - * @param size log size popped and next available log size - * @return next avaliable address - */ -static uint8_t *LOG_BufPop(size_t *size); - -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ - -/*! - * @brief read one character - * - * @param ch character address - * @return indicate the read status - * - */ -static status_t LOG_ReadOneCharacter(uint8_t *ch); - -#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION -/*! - * @brief echo one character - * - * @param ch character address - * @param isGetchar flag to distinguish getchar from scanf - * @param index special for scanf to support backspace - * @return indicate the read status - * - */ -static status_t LOG_EchoCharacter(uint8_t *ch, bool isGetChar, int *index); -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -status_t LOG_Init(uint32_t baseAddr, uint8_t device, uint32_t baudRate, uint32_t clkSrcFreq) -{ - io_state_t io; - /* init io */ - io.ioBase = (void *)baseAddr; - io.ioType = device; - -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING - /* memset the global queue */ - memset(&s_log_buffer, 0U, sizeof(s_log_buffer)); - /* init callback for NON-BLOCKING */ - io.callBack = LOG_Transferred; - /* io init function */ - IO_Init(&io, baudRate, clkSrcFreq, s_log_buffer.rxBuf); - /* Debug console buffer push lock create */ - LOG_CREATE_MUTEX_SEMAPHORE(s_logPushSemaphore); - /* Debug console get/scanf mutex lock create */ - LOG_CREATE_MUTEX_SEMAPHORE(s_logReadSemaphore); -#else - IO_Init(&io, baudRate, clkSrcFreq, NULL); -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ - - /* Debug console lock create */ - LOG_CREATE_MUTEX_SEMAPHORE(s_logPopSemaphore); - LOG_CREATE_BINARY_SEMAPHORE(s_logReadWaitSemaphore); - - return kStatus_Success; -} - -void LOG_Deinit(void) -{ -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING - /* memset the global queue */ - memset(&s_log_buffer, 0U, sizeof(s_log_buffer)); -#endif /*DEBUG_CONSOLE_TRANSFER_NON_BLOCKING*/ - /* Deinit IO */ - IO_Deinit(); -} - -status_t LOG_WaitIdle(void) -{ -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING - /* wait buffer empty */ - while (!(s_log_buffer.totalIndex == 0U)) - ; -#endif /*DEBUG_CONSOLE_TRANSFER_NON_BLOCKING*/ - /* wait IO idle */ - IO_WaitIdle(); - - return kStatus_Success; -} - -int LOG_Push(uint8_t *buf, size_t size) -{ - assert(buf != NULL); - -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING - /* push to buffer */ - LOG_BufPush(buf, size); - buf = LOG_BufGetNextAvaliableLog(&size); -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ - /* pop log */ - return LOG_Pop(buf, size); -} - -int LOG_Pop(uint8_t *buf, size_t size) -{ - uint8_t getLock = 0U; - - if ((0 != size) && (NULL != buf)) - { - /* take POP lock, should be non-blocking */ - LOG_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(s_logPopSemaphore, getLock); - - if (getLock) - { - /* call IO transfer function */ - if (IO_Transfer(buf, size, true) != kStatus_Success) - { - size = 0U; - } - /* release POP lock */ - LOG_GIVE_MUTEX_SEMAPHORE(s_logPopSemaphore); - } - } - - return size; -} - -int LOG_ReadLine(uint8_t *buf, size_t size) -{ - assert(buf != NULL); - - int i = 0; - - /* take mutex lock function */ - LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_logReadSemaphore); - - for (i = 0; i < size; i++) - { - /* recieve one char every time */ - if (LOG_ReadOneCharacter(&buf[i]) != kStatus_Success) - { - return -1; - } -#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION - LOG_EchoCharacter(&buf[i], false, &i); -#endif - /* analysis data */ - if ((buf[i] == '\r') || (buf[i] == '\n')) - { - /* End of Line. */ - if (i == 0) - { - buf[i] = '\0'; - i = -1; - } - else - { - break; - } - } - } - /* get char should not add '\0'*/ - if (i == size) - { - buf[i] = '\0'; - } - else - { - buf[i + 1] = '\0'; - } - - /* release mutex lock function */ - LOG_GIVE_MUTEX_SEMAPHORE(s_logReadSemaphore); - - return i; -} - -int LOG_ReadCharacter(uint8_t *ch) -{ - assert(ch != NULL); - int ret = 0; - - /* take mutex lock function */ - LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_logReadSemaphore); - /* read one character */ - if (LOG_ReadOneCharacter(ch) == kStatus_Success) - { - ret = 1; -#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION - LOG_EchoCharacter(ch, true, NULL); -#endif - } - else - { - ret = -1; - } - - /* release mutex lock function */ - LOG_GIVE_MUTEX_SEMAPHORE(s_logReadSemaphore); - - return ret; -} - -static status_t LOG_ReadOneCharacter(uint8_t *ch) -{ - /* recieve one char every time */ - if (IO_Transfer(ch, 1U, false) != kStatus_Success) - { - return kStatus_Fail; - } - - /* wait release from ISR */ - LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(s_logReadWaitSemaphore); - - return kStatus_Success; -} - -#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION -static status_t LOG_EchoCharacter(uint8_t *ch, bool isGetChar, int *index) -{ - /* Due to scanf take \n and \r as end of string,should not echo */ - if (((*ch != '\r') && (*ch != '\n')) || (isGetChar)) - { - /* recieve one char every time */ - if (IO_Transfer(ch, 1U, true) != kStatus_Success) - { - return kStatus_Fail; - } - } - - if (!isGetChar) - { - if ((*index > 0) && (*ch == BACKSPACE)) - { - *index -= 2; - } - } - - return kStatus_Success; -} -#endif - -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -static int LOG_BufPush(uint8_t *buf, size_t size) -{ - uint32_t pushIndex = 0U, i = 0U; - bool pushAvaliable = false; - - /* take mutex lock function */ - LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_logPushSemaphore); - if (size <= (DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN - s_log_buffer.totalIndex)) - { - /* get push index */ - pushIndex = s_log_buffer.pushIndex; - s_log_buffer.pushIndex += size; - /* check index overflow */ - LOG_CHECK_BUFFER_INDEX_OVERFLOW(s_log_buffer.pushIndex); - /* update push/total index value */ - s_log_buffer.totalIndex += size; - pushAvaliable = true; - } - /* release mutex lock function */ - LOG_GIVE_MUTEX_SEMAPHORE(s_logPushSemaphore); - - /* check the buffer if have enough space to store the log */ - if (pushAvaliable) - { - for (i = size; i > 0; i--) - { - /* copy log to buffer, the buffer only support a fixed length argument, if the log argument - is longer than the fixed length, the left argument will be losed */ - s_log_buffer.txBuf[pushIndex] = *buf++; - /* increase index */ - pushIndex++; - /* check index overflow */ - LOG_CHECK_BUFFER_INDEX_OVERFLOW(pushIndex); - } - } - else - { - size = 0U; - } - - return size; -} - -static uint8_t *LOG_BufGetNextAvaliableLog(size_t *size) -{ - uint16_t popIndex = s_log_buffer.popIndex; - - /* get avaliable size */ - if (s_log_buffer.totalIndex > (DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN - popIndex)) - { - *size = (DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN - popIndex); - } - else - { - *size = s_log_buffer.totalIndex; - } - - /* return address */ - return (&(s_log_buffer.txBuf[popIndex])); -} - -static uint8_t *LOG_BufPop(size_t *size) -{ - if (s_log_buffer.totalIndex >= *size) - { - /* decrease the log total member */ - s_log_buffer.totalIndex -= *size; - /* there is more log in the queue to be pushed */ - if (s_log_buffer.totalIndex > 0U) - { - /* update the pop index */ - s_log_buffer.popIndex += *size; - /* check index overflow */ - LOG_CHECK_BUFFER_INDEX_OVERFLOW(s_log_buffer.popIndex); - - return LOG_BufGetNextAvaliableLog(size); - } - else - { - /* reset push and pop */ - s_log_buffer.popIndex = 0U; - s_log_buffer.pushIndex = 0U; - *size = 0U; - } - } - - return NULL; -} - -static void LOG_Transferred(size_t *size, bool receive, bool transmit) -{ - uint8_t *addr = NULL; - - if (transmit) - { - addr = LOG_BufPop(size); - /* continue pop log from buffer */ - LOG_Pop(addr, *size); - } - - if (receive) - { - /* release from ISR */ - LOG_GIVE_BINARY_SEMAPHORE_FROM_ISR(s_logReadWaitSemaphore); - } -} -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ - -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -status_t LOG_TryReadCharacter(uint8_t *ch) -{ - if (NULL != ch) - { - return IO_TryReceiveCharacter(ch); - } - return kStatus_Fail; -} -#endif diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/log/fsl_log.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/log/fsl_log.h deleted file mode 100644 index 87f4c8a7b81..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/log/fsl_log.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _FSL_LOG_H -#define _FSL_LOG_H - -#include "fsl_common.h" - -/*! - * @addtogroup debugconsole - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/************************************************************************************************* - * Prototypes - ************************************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @brief Initializes - * - * Call this function to init the buffer - * @param baseAddr, device base address - * @param device, device type - * @param baudRate, device communicate baudrate - * @param clkSrcFreq, device source clock freq - * - * @return Indicates whether initialization was successful or not. - * @retval kStatus_Success Execution successfully - * @retval kStatus_Fail Execution failure - */ -status_t LOG_Init(uint32_t baseAddr, uint8_t device, uint32_t baudRate, uint32_t clkSrcFreq); - -/*! - * @brief De-Initializes - * - * Call this function to deinit the buffer - * - * @return Indicates whether Deinit was successful or not. - */ -void LOG_Deinit(void); - -/*! - * @brief log push interface - * - * Call this function to print log - * @param fmt, buffer pointer - * @param size, avaliable size - * @return indicate the push size - * @retval-1 indicate buffer is full or transfer fail. - * @retval size return the push log size. - */ -int LOG_Push(uint8_t *buf, size_t size); - -/*! - * @brief log read one line function - * - * Call this function to print log - * @param fmt, buffer pointer - * @param size, avaliable size - * @reutrn the number of the recieved character - */ -int LOG_ReadLine(uint8_t *buf, size_t size); - -/*! - * @brief log read one character function - * - * Call this function to GETCHAR - * @param ch receive address - * @reutrn the number of the recieved character - */ -int LOG_ReadCharacter(uint8_t *ch); - -/*! - * @brief wait log and io idle - * - * Call this function to wait log buffer empty and io idle before enter low power mode. - * @return Indicates whether wait idle was successful or not. - */ -status_t LOG_WaitIdle(void); - -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -/*! - * @brief log try read one character - * Call this function to check character avaliable or not, if not return fail, otherwise return it. - * @param ch the address of char to receive - * @return Indicates try getchar was successful or not. - */ -status_t LOG_TryReadCharacter(uint8_t *ch); -#endif - -/*! - * @brief log pop function - * - * Call this function to pop log from buffer. - * @param buf buffer address to pop - * @param size log size to pop - * @return pop log size. - */ -int LOG_Pop(uint8_t *buf, size_t size); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @} */ - -#endif diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/str/fsl_str.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/str/fsl_str.c deleted file mode 100644 index d34e41a3ad0..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/str/fsl_str.c +++ /dev/null @@ -1,1327 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include -#include -#include -#include "fsl_str.h" -#include "fsl_debug_console_conf.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief The overflow value.*/ -#ifndef HUGE_VAL -#define HUGE_VAL (99.e99) -#endif /* HUGE_VAL */ - -#if SCANF_FLOAT_ENABLE -static double fnum = 0.0; -#endif /* SCANF_FLOAT_ENABLE */ - -#if PRINTF_ADVANCED_ENABLE -/*! @brief Specification modifier flags for printf. */ -enum _debugconsole_printf_flag -{ - kPRINTF_Minus = 0x01U, /*!< Minus FLag. */ - kPRINTF_Plus = 0x02U, /*!< Plus Flag. */ - kPRINTF_Space = 0x04U, /*!< Space Flag. */ - kPRINTF_Zero = 0x08U, /*!< Zero Flag. */ - kPRINTF_Pound = 0x10U, /*!< Pound Flag. */ - kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */ - kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */ - kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */ - kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */ -}; -#endif /* PRINTF_ADVANCED_ENABLE */ - -/*! @brief Specification modifier flags for scanf. */ -enum _debugconsole_scanf_flag -{ - kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */ - kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */ - kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */ - kSCANF_DestString = 0x8U, /*!< Destination String FLag. */ - kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */ - kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */ - kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */ - kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */ -#if SCANF_ADVANCED_ENABLE - kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */ - kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */ - kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */ - kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */ -#endif /* SCANF_ADVANCED_ENABLE */ -#if PRINTF_FLOAT_ENABLE - kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */ -#endif /*PRINTF_FLOAT_ENABLE */ - kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */ -}; - -/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */ -#if defined(__CC_ARM) -#pragma diag_suppress 1256 -#endif /* __CC_ARM */ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Scanline function which ignores white spaces. - * - * @param[in] s The address of the string pointer to update. - * @return String without white spaces. - */ -static uint32_t ScanIgnoreWhiteSpace(const char **s); - -/*! - * @brief Converts a radix number to a string and return its length. - * - * @param[in] numstr Converted string of the number. - * @param[in] nump Pointer to the number. - * @param[in] neg Polarity of the number. - * @param[in] radix The radix to be converted to. - * @param[in] use_caps Used to identify %x/X output format. - - * @return Length of the converted string. - */ -static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps); - -#if PRINTF_FLOAT_ENABLE -/*! - * @brief Converts a floating radix number to a string and return its length. - * - * @param[in] numstr Converted string of the number. - * @param[in] nump Pointer to the number. - * @param[in] radix The radix to be converted to. - * @param[in] precision_width Specify the precision width. - - * @return Length of the converted string. - */ -static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width); -#endif /* PRINTF_FLOAT_ENABLE */ - -/*! -* - */ -double modf(double input_dbl, double *intpart_ptr); - -/*************Code for process formatted data*******************************/ - -static uint32_t ScanIgnoreWhiteSpace(const char **s) -{ - uint8_t count = 0; - uint8_t c; - - c = **s; - while ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f')) - { - count++; - (*s)++; - c = **s; - } - return count; -} - -static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps) -{ -#if PRINTF_ADVANCED_ENABLE - int64_t a; - int64_t b; - int64_t c; - - uint64_t ua; - uint64_t ub; - uint64_t uc; -#else - int32_t a; - int32_t b; - int32_t c; - - uint32_t ua; - uint32_t ub; - uint32_t uc; -#endif /* PRINTF_ADVANCED_ENABLE */ - - int32_t nlen; - char *nstrp; - - nlen = 0; - nstrp = numstr; - *nstrp++ = '\0'; - - if (neg) - { -#if PRINTF_ADVANCED_ENABLE - a = *(int64_t *)nump; -#else - a = *(int32_t *)nump; -#endif /* PRINTF_ADVANCED_ENABLE */ - if (a == 0) - { - *nstrp = '0'; - ++nlen; - return nlen; - } - while (a != 0) - { -#if PRINTF_ADVANCED_ENABLE - b = (int64_t)a / (int64_t)radix; - c = (int64_t)a - ((int64_t)b * (int64_t)radix); - if (c < 0) - { - uc = (uint64_t)c; - c = (int64_t)(~uc) + 1 + '0'; - } -#else - b = a / radix; - c = a - (b * radix); - if (c < 0) - { - uc = (uint32_t)c; - c = (uint32_t)(~uc) + 1 + '0'; - } -#endif /* PRINTF_ADVANCED_ENABLE */ - else - { - c = c + '0'; - } - a = b; - *nstrp++ = (char)c; - ++nlen; - } - } - else - { -#if PRINTF_ADVANCED_ENABLE - ua = *(uint64_t *)nump; -#else - ua = *(uint32_t *)nump; -#endif /* PRINTF_ADVANCED_ENABLE */ - if (ua == 0) - { - *nstrp = '0'; - ++nlen; - return nlen; - } - while (ua != 0) - { -#if PRINTF_ADVANCED_ENABLE - ub = (uint64_t)ua / (uint64_t)radix; - uc = (uint64_t)ua - ((uint64_t)ub * (uint64_t)radix); -#else - ub = ua / (uint32_t)radix; - uc = ua - (ub * (uint32_t)radix); -#endif /* PRINTF_ADVANCED_ENABLE */ - - if (uc < 10) - { - uc = uc + '0'; - } - else - { - uc = uc - 10 + (use_caps ? 'A' : 'a'); - } - ua = ub; - *nstrp++ = (char)uc; - ++nlen; - } - } - return nlen; -} - -#if PRINTF_FLOAT_ENABLE -static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width) -{ - int32_t a; - int32_t b; - int32_t c; - int32_t i; - uint32_t uc; - double fa; - double dc; - double fb; - double r; - double fractpart; - double intpart; - - int32_t nlen; - char *nstrp; - nlen = 0; - nstrp = numstr; - *nstrp++ = '\0'; - r = *(double *)nump; - if (!r) - { - *nstrp = '0'; - ++nlen; - return nlen; - } - fractpart = modf((double)r, (double *)&intpart); - /* Process fractional part. */ - for (i = 0; i < precision_width; i++) - { - fractpart *= radix; - } - if (r >= 0) - { - fa = fractpart + (double)0.5; - if (fa >= pow(10, precision_width)) - { - intpart++; - } - } - else - { - fa = fractpart - (double)0.5; - if (fa <= -pow(10, precision_width)) - { - intpart--; - } - } - for (i = 0; i < precision_width; i++) - { - fb = fa / (int32_t)radix; - dc = (fa - (int64_t)fb * (int32_t)radix); - c = (int32_t)dc; - if (c < 0) - { - uc = (uint32_t)c; - c = (int32_t)(~uc) + 1 + '0'; - } - else - { - c = c + '0'; - } - fa = fb; - *nstrp++ = (char)c; - ++nlen; - } - *nstrp++ = (char)'.'; - ++nlen; - a = (int32_t)intpart; - if (a == 0) - { - *nstrp++ = '0'; - ++nlen; - } - else - { - while (a != 0) - { - b = (int32_t)a / (int32_t)radix; - c = (int32_t)a - ((int32_t)b * (int32_t)radix); - if (c < 0) - { - uc = (uint32_t)c; - c = (int32_t)(~uc) + 1 + '0'; - } - else - { - c = c + '0'; - } - a = b; - *nstrp++ = (char)c; - ++nlen; - } - } - return nlen; -} -#endif /* PRINTF_FLOAT_ENABLE */ - -int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb) -{ - /* va_list ap; */ - char *p; - int32_t c; - - char vstr[33]; - char *vstrp = NULL; - int32_t vlen = 0; - - int32_t done; - int32_t count = 0; - - uint32_t field_width; - uint32_t precision_width; - char *sval; - int32_t cval; - bool use_caps; - uint8_t radix = 0; - -#if PRINTF_ADVANCED_ENABLE - uint32_t flags_used; - int32_t schar, dschar; - int64_t ival; - uint64_t uval = 0; - bool valid_precision_width; -#else - int32_t ival; - uint32_t uval = 0; -#endif /* PRINTF_ADVANCED_ENABLE */ - -#if PRINTF_FLOAT_ENABLE - double fval; -#endif /* PRINTF_FLOAT_ENABLE */ - - /* Start parsing apart the format string and display appropriate formats and data. */ - for (p = (char *)fmt; (c = *p) != 0; p++) - { - /* - * All formats begin with a '%' marker. Special chars like - * '\n' or '\t' are normally converted to the appropriate - * character by the __compiler__. Thus, no need for this - * routine to account for the '\' character. - */ - if (c != '%') - { - cb(buf, &count, c, 1); - /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */ - continue; - } - - use_caps = true; - -#if PRINTF_ADVANCED_ENABLE - /* First check for specification modifier flags. */ - flags_used = 0; - done = false; - while (!done) - { - switch (*++p) - { - case '-': - flags_used |= kPRINTF_Minus; - break; - case '+': - flags_used |= kPRINTF_Plus; - break; - case ' ': - flags_used |= kPRINTF_Space; - break; - case '0': - flags_used |= kPRINTF_Zero; - break; - case '#': - flags_used |= kPRINTF_Pound; - break; - default: - /* We've gone one char too far. */ - --p; - done = true; - break; - } - } -#endif /* PRINTF_ADVANCED_ENABLE */ - - /* Next check for minimum field width. */ - field_width = 0; - done = false; - while (!done) - { - c = *++p; - if ((c >= '0') && (c <= '9')) - { - field_width = (field_width * 10) + (c - '0'); - } -#if PRINTF_ADVANCED_ENABLE - else if (c == '*') - { - field_width = (uint32_t)va_arg(ap, uint32_t); - } -#endif /* PRINTF_ADVANCED_ENABLE */ - else - { - /* We've gone one char too far. */ - --p; - done = true; - } - } - /* Next check for the width and precision field separator. */ - precision_width = 6; -#if PRINTF_ADVANCED_ENABLE - valid_precision_width = false; -#endif /* PRINTF_ADVANCED_ENABLE */ - if (*++p == '.') - { - /* Must get precision field width, if present. */ - precision_width = 0; - done = false; - while (!done) - { - c = *++p; - if ((c >= '0') && (c <= '9')) - { - precision_width = (precision_width * 10) + (c - '0'); -#if PRINTF_ADVANCED_ENABLE - valid_precision_width = true; -#endif /* PRINTF_ADVANCED_ENABLE */ - } -#if PRINTF_ADVANCED_ENABLE - else if (c == '*') - { - precision_width = (uint32_t)va_arg(ap, uint32_t); - valid_precision_width = true; - } -#endif /* PRINTF_ADVANCED_ENABLE */ - else - { - /* We've gone one char too far. */ - --p; - done = true; - } - } - } - else - { - /* We've gone one char too far. */ - --p; - } -#if PRINTF_ADVANCED_ENABLE - /* - * Check for the length modifier. - */ - switch (/* c = */ *++p) - { - case 'h': - if (*++p != 'h') - { - flags_used |= kPRINTF_LengthShortInt; - --p; - } - else - { - flags_used |= kPRINTF_LengthChar; - } - break; - case 'l': - if (*++p != 'l') - { - flags_used |= kPRINTF_LengthLongInt; - --p; - } - else - { - flags_used |= kPRINTF_LengthLongLongInt; - } - break; - default: - /* we've gone one char too far */ - --p; - break; - } -#endif /* PRINTF_ADVANCED_ENABLE */ - /* Now we're ready to examine the format. */ - c = *++p; - { - if ((c == 'd') || (c == 'i') || (c == 'f') || (c == 'F') || (c == 'x') || (c == 'X') || (c == 'o') || - (c == 'b') || (c == 'p') || (c == 'u')) - { - if ((c == 'd') || (c == 'i')) - { -#if PRINTF_ADVANCED_ENABLE - if (flags_used & kPRINTF_LengthLongLongInt) - { - ival = (int64_t)va_arg(ap, int64_t); - } - else -#endif /* PRINTF_ADVANCED_ENABLE */ - { - ival = (int32_t)va_arg(ap, int32_t); - } - vlen = ConvertRadixNumToString(vstr, &ival, true, 10, use_caps); - vstrp = &vstr[vlen]; -#if PRINTF_ADVANCED_ENABLE - if (ival < 0) - { - schar = '-'; - ++vlen; - } - else - { - if (flags_used & kPRINTF_Plus) - { - schar = '+'; - ++vlen; - } - else - { - if (flags_used & kPRINTF_Space) - { - schar = ' '; - ++vlen; - } - else - { - schar = 0; - } - } - } - dschar = false; - /* Do the ZERO pad. */ - if (flags_used & kPRINTF_Zero) - { - if (schar) - { - cb(buf, &count, schar, 1); - } - dschar = true; - - cb(buf, &count, '0', field_width - vlen); - vlen = field_width; - } - else - { - if (!(flags_used & kPRINTF_Minus)) - { - cb(buf, &count, ' ', field_width - vlen); - if (schar) - { - cb(buf, &count, schar, 1); - } - dschar = true; - } - } - /* The string was built in reverse order, now display in correct order. */ - if ((!dschar) && schar) - { - cb(buf, &count, schar, 1); - } -#endif /* PRINTF_ADVANCED_ENABLE */ - } - -#if PRINTF_FLOAT_ENABLE - if ((c == 'f') || (c == 'F')) - { - fval = (double)va_arg(ap, double); - vlen = ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width); - vstrp = &vstr[vlen]; - -#if PRINTF_ADVANCED_ENABLE - if (fval < 0) - { - schar = '-'; - ++vlen; - } - else - { - if (flags_used & kPRINTF_Plus) - { - schar = '+'; - ++vlen; - } - else - { - if (flags_used & kPRINTF_Space) - { - schar = ' '; - ++vlen; - } - else - { - schar = 0; - } - } - } - dschar = false; - if (flags_used & kPRINTF_Zero) - { - if (schar) - { - cb(buf, &count, schar, 1); - } - dschar = true; - cb(buf, &count, '0', field_width - vlen); - vlen = field_width; - } - else - { - if (!(flags_used & kPRINTF_Minus)) - { - cb(buf, &count, ' ', field_width - vlen); - if (schar) - { - cb(buf, &count, schar, 1); - } - dschar = true; - } - } - if ((!dschar) && schar) - { - cb(buf, &count, schar, 1); - } -#endif /* PRINTF_ADVANCED_ENABLE */ - } -#endif /* PRINTF_FLOAT_ENABLE */ - if ((c == 'X') || (c == 'x')) - { - if (c == 'x') - { - use_caps = false; - } -#if PRINTF_ADVANCED_ENABLE - if (flags_used & kPRINTF_LengthLongLongInt) - { - uval = (uint64_t)va_arg(ap, uint64_t); - } - else -#endif /* PRINTF_ADVANCED_ENABLE */ - { - uval = (uint32_t)va_arg(ap, uint32_t); - } - vlen = ConvertRadixNumToString(vstr, &uval, false, 16, use_caps); - vstrp = &vstr[vlen]; - -#if PRINTF_ADVANCED_ENABLE - dschar = false; - if (flags_used & kPRINTF_Zero) - { - if (flags_used & kPRINTF_Pound) - { - cb(buf, &count, '0', 1); - cb(buf, &count, (use_caps ? 'X' : 'x'), 1); - dschar = true; - } - cb(buf, &count, '0', field_width - vlen); - vlen = field_width; - } - else - { - if (!(flags_used & kPRINTF_Minus)) - { - if (flags_used & kPRINTF_Pound) - { - vlen += 2; - } - cb(buf, &count, ' ', field_width - vlen); - if (flags_used & kPRINTF_Pound) - { - cb(buf, &count, '0', 1); - cb(buf, &count, (use_caps ? 'X' : 'x'), 1); - dschar = true; - } - } - } - - if ((flags_used & kPRINTF_Pound) && (!dschar)) - { - cb(buf, &count, '0', 1); - cb(buf, &count, (use_caps ? 'X' : 'x'), 1); - vlen += 2; - } -#endif /* PRINTF_ADVANCED_ENABLE */ - } - if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u')) - { -#if PRINTF_ADVANCED_ENABLE - if (flags_used & kPRINTF_LengthLongLongInt) - { - uval = (uint64_t)va_arg(ap, uint64_t); - } - else -#endif /* PRINTF_ADVANCED_ENABLE */ - { - uval = (uint32_t)va_arg(ap, uint32_t); - } - - if (c == 'o') - { - radix = 8; - } - else if (c == 'b') - { - radix = 2; - } - else if (c == 'p') - { - radix = 16; - } - else - { - radix = 10; - } - - vlen = ConvertRadixNumToString(vstr, &uval, false, radix, use_caps); - vstrp = &vstr[vlen]; -#if PRINTF_ADVANCED_ENABLE - if (flags_used & kPRINTF_Zero) - { - cb(buf, &count, '0', field_width - vlen); - vlen = field_width; - } - else - { - if (!(flags_used & kPRINTF_Minus)) - { - cb(buf, &count, ' ', field_width - vlen); - } - } -#endif /* PRINTF_ADVANCED_ENABLE */ - } -#if !PRINTF_ADVANCED_ENABLE - cb(buf, &count, ' ', field_width - vlen); -#endif /* !PRINTF_ADVANCED_ENABLE */ - if (vstrp != NULL) - { - while (*vstrp) - { - cb(buf, &count, *vstrp--, 1); - } - } -#if PRINTF_ADVANCED_ENABLE - if (flags_used & kPRINTF_Minus) - { - cb(buf, &count, ' ', field_width - vlen); - } -#endif /* PRINTF_ADVANCED_ENABLE */ - } - else if (c == 'c') - { - cval = (char)va_arg(ap, uint32_t); - cb(buf, &count, cval, 1); - } - else if (c == 's') - { - sval = (char *)va_arg(ap, char *); - if (sval) - { -#if PRINTF_ADVANCED_ENABLE - if (valid_precision_width) - { - vlen = precision_width; - } - else - { - vlen = strlen(sval); - } -#else - vlen = strlen(sval); -#endif /* PRINTF_ADVANCED_ENABLE */ -#if PRINTF_ADVANCED_ENABLE - if (!(flags_used & kPRINTF_Minus)) -#endif /* PRINTF_ADVANCED_ENABLE */ - { - cb(buf, &count, ' ', field_width - vlen); - } - -#if PRINTF_ADVANCED_ENABLE - if (valid_precision_width) - { - while ((*sval) && (vlen > 0)) - { - cb(buf, &count, *sval++, 1); - vlen--; - } - /* In case that vlen sval is shorter than vlen */ - vlen = precision_width - vlen; - } - else - { -#endif /* PRINTF_ADVANCED_ENABLE */ - while (*sval) - { - cb(buf, &count, *sval++, 1); - } -#if PRINTF_ADVANCED_ENABLE - } -#endif /* PRINTF_ADVANCED_ENABLE */ - -#if PRINTF_ADVANCED_ENABLE - if (flags_used & kPRINTF_Minus) - { - cb(buf, &count, ' ', field_width - vlen); - } -#endif /* PRINTF_ADVANCED_ENABLE */ - } - } - else - { - cb(buf, &count, c, 1); - } - } - } - - return count; -} - -int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr) -{ - uint8_t base; - int8_t neg; - /* Identifier for the format string. */ - char *c = format; - char temp; - char *buf; - /* Flag telling the conversion specification. */ - uint32_t flag = 0; - /* Filed width for the matching input streams. */ - uint32_t field_width; - /* How many arguments are assigned except the suppress. */ - uint32_t nassigned = 0; - /* How many characters are read from the input streams. */ - uint32_t n_decode = 0; - - int32_t val; - - const char *s; - /* Identifier for the input string. */ - const char *p = line_ptr; - - /* Return EOF error before any conversion. */ - if (*p == '\0') - { - return -1; - } - - /* Decode directives. */ - while ((*c) && (*p)) - { - /* Ignore all white-spaces in the format strings. */ - if (ScanIgnoreWhiteSpace((const char **)&c)) - { - n_decode += ScanIgnoreWhiteSpace(&p); - } - else if ((*c != '%') || ((*c == '%') && (*(c + 1) == '%'))) - { - /* Ordinary characters. */ - c++; - if (*p == *c) - { - n_decode++; - p++; - c++; - } - else - { - /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream. - * However, it is deserted now. */ - break; - } - } - else - { - /* convernsion specification */ - c++; - /* Reset. */ - flag = 0; - field_width = 0; - base = 0; - - /* Loop to get full conversion specification. */ - while ((*c) && (!(flag & kSCANF_DestMask))) - { - switch (*c) - { -#if SCANF_ADVANCED_ENABLE - case '*': - if (flag & kSCANF_Suppress) - { - /* Match failure. */ - return nassigned; - } - flag |= kSCANF_Suppress; - c++; - break; - case 'h': - if (flag & kSCANF_LengthMask) - { - /* Match failure. */ - return nassigned; - } - - if (c[1] == 'h') - { - flag |= kSCANF_LengthChar; - c++; - } - else - { - flag |= kSCANF_LengthShortInt; - } - c++; - break; - case 'l': - if (flag & kSCANF_LengthMask) - { - /* Match failure. */ - return nassigned; - } - - if (c[1] == 'l') - { - flag |= kSCANF_LengthLongLongInt; - c++; - } - else - { - flag |= kSCANF_LengthLongInt; - } - c++; - break; -#endif /* SCANF_ADVANCED_ENABLE */ -#if SCANF_FLOAT_ENABLE - case 'L': - if (flag & kSCANF_LengthMask) - { - /* Match failure. */ - return nassigned; - } - flag |= kSCANF_LengthLongLongDouble; - c++; - break; -#endif /* SCANF_FLOAT_ENABLE */ - case '0': - case '1': - case '2': - case '3': - case '4': - case '5': - case '6': - case '7': - case '8': - case '9': - if (field_width) - { - /* Match failure. */ - return nassigned; - } - do - { - field_width = field_width * 10 + *c - '0'; - c++; - } while ((*c >= '0') && (*c <= '9')); - break; - case 'd': - base = 10; - flag |= kSCANF_TypeSinged; - flag |= kSCANF_DestInt; - c++; - break; - case 'u': - base = 10; - flag |= kSCANF_DestInt; - c++; - break; - case 'o': - base = 8; - flag |= kSCANF_DestInt; - c++; - break; - case 'x': - case 'X': - base = 16; - flag |= kSCANF_DestInt; - c++; - break; - case 'i': - base = 0; - flag |= kSCANF_DestInt; - c++; - break; -#if SCANF_FLOAT_ENABLE - case 'a': - case 'A': - case 'e': - case 'E': - case 'f': - case 'F': - case 'g': - case 'G': - flag |= kSCANF_DestFloat; - c++; - break; -#endif /* SCANF_FLOAT_ENABLE */ - case 'c': - flag |= kSCANF_DestChar; - if (!field_width) - { - field_width = 1; - } - c++; - break; - case 's': - flag |= kSCANF_DestString; - c++; - break; - default: - return nassigned; - } - } - - if (!(flag & kSCANF_DestMask)) - { - /* Format strings are exhausted. */ - return nassigned; - } - - if (!field_width) - { - /* Large than length of a line. */ - field_width = 99; - } - - /* Matching strings in input streams and assign to argument. */ - switch (flag & kSCANF_DestMask) - { - case kSCANF_DestChar: - s = (const char *)p; - buf = va_arg(args_ptr, char *); - while ((field_width--) && (*p)) - { - if (!(flag & kSCANF_Suppress)) - { - *buf++ = *p++; - } - else - { - p++; - } - n_decode++; - } - - if ((!(flag & kSCANF_Suppress)) && (s != p)) - { - nassigned++; - } - break; - case kSCANF_DestString: - n_decode += ScanIgnoreWhiteSpace(&p); - s = p; - buf = va_arg(args_ptr, char *); - while ((field_width--) && (*p != '\0') && (*p != ' ') && (*p != '\t') && (*p != '\n') && - (*p != '\r') && (*p != '\v') && (*p != '\f')) - { - if (flag & kSCANF_Suppress) - { - p++; - } - else - { - *buf++ = *p++; - } - n_decode++; - } - - if ((!(flag & kSCANF_Suppress)) && (s != p)) - { - /* Add NULL to end of string. */ - *buf = '\0'; - nassigned++; - } - break; - case kSCANF_DestInt: - n_decode += ScanIgnoreWhiteSpace(&p); - s = p; - val = 0; - if ((base == 0) || (base == 16)) - { - if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) - { - base = 16; - if (field_width >= 1) - { - p += 2; - n_decode += 2; - field_width -= 2; - } - } - } - - if (base == 0) - { - if (s[0] == '0') - { - base = 8; - } - else - { - base = 10; - } - } - - neg = 1; - switch (*p) - { - case '-': - neg = -1; - n_decode++; - p++; - field_width--; - break; - case '+': - neg = 1; - n_decode++; - p++; - field_width--; - break; - default: - break; - } - - while ((*p) && (field_width--)) - { - if ((*p <= '9') && (*p >= '0')) - { - temp = *p - '0'; - } - else if ((*p <= 'f') && (*p >= 'a')) - { - temp = *p - 'a' + 10; - } - else if ((*p <= 'F') && (*p >= 'A')) - { - temp = *p - 'A' + 10; - } - else - { - temp = base; - } - - if (temp >= base) - { - break; - } - else - { - val = base * val + temp; - } - p++; - n_decode++; - } - val *= neg; - if (!(flag & kSCANF_Suppress)) - { -#if SCANF_ADVANCED_ENABLE - switch (flag & kSCANF_LengthMask) - { - case kSCANF_LengthChar: - if (flag & kSCANF_TypeSinged) - { - *va_arg(args_ptr, signed char *) = (signed char)val; - } - else - { - *va_arg(args_ptr, unsigned char *) = (unsigned char)val; - } - break; - case kSCANF_LengthShortInt: - if (flag & kSCANF_TypeSinged) - { - *va_arg(args_ptr, signed short *) = (signed short)val; - } - else - { - *va_arg(args_ptr, unsigned short *) = (unsigned short)val; - } - break; - case kSCANF_LengthLongInt: - if (flag & kSCANF_TypeSinged) - { - *va_arg(args_ptr, signed long int *) = (signed long int)val; - } - else - { - *va_arg(args_ptr, unsigned long int *) = (unsigned long int)val; - } - break; - case kSCANF_LengthLongLongInt: - if (flag & kSCANF_TypeSinged) - { - *va_arg(args_ptr, signed long long int *) = (signed long long int)val; - } - else - { - *va_arg(args_ptr, unsigned long long int *) = (unsigned long long int)val; - } - break; - default: - /* The default type is the type int. */ - if (flag & kSCANF_TypeSinged) - { - *va_arg(args_ptr, signed int *) = (signed int)val; - } - else - { - *va_arg(args_ptr, unsigned int *) = (unsigned int)val; - } - break; - } -#else - /* The default type is the type int. */ - if (flag & kSCANF_TypeSinged) - { - *va_arg(args_ptr, signed int *) = (signed int)val; - } - else - { - *va_arg(args_ptr, unsigned int *) = (unsigned int)val; - } -#endif /* SCANF_ADVANCED_ENABLE */ - nassigned++; - } - break; -#if SCANF_FLOAT_ENABLE - case kSCANF_DestFloat: - n_decode += ScanIgnoreWhiteSpace(&p); - fnum = strtod(p, (char **)&s); - - if ((fnum >= HUGE_VAL) || (fnum <= -HUGE_VAL)) - { - break; - } - - n_decode += (int)(s) - (int)(p); - p = s; - if (!(flag & kSCANF_Suppress)) - { - if (flag & kSCANF_LengthLongLongDouble) - { - *va_arg(args_ptr, double *) = fnum; - } - else - { - *va_arg(args_ptr, float *) = (float)fnum; - } - nassigned++; - } - break; -#endif /* SCANF_FLOAT_ENABLE */ - default: - return nassigned; - } - } - } - return nassigned; -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/str/fsl_str.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/str/fsl_str.h deleted file mode 100644 index 47d835edf9a..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/str/fsl_str.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _FSL_STR_H -#define _FSL_STR_H - -#include "fsl_common.h" - -/*! - * @addtogroup debugconsole - * @{ - */ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @brief A function pointer which is used when format printf log. - */ -typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len); - -/*! - * @brief This function outputs its parameters according to a formatted string. - * - * @note I/O is performed by calling given function pointer using following - * (*func_ptr)(c); - * - * @param[in] fmt_ptr Format string for printf. - * @param[in] args_ptr Arguments to printf. - * @param[in] buf pointer to the buffer - * @param cb print callbck function pointer - * - * @return Number of characters to be print - */ -int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb); - -/*! - * @brief Converts an input line of ASCII characters based upon a provided - * string format. - * - * @param[in] line_ptr The input line of ASCII data. - * @param[in] format Format first points to the format string. - * @param[in] args_ptr The list of parameters. - * - * @return Number of input items converted and assigned. - * @retval IO_EOF When line_ptr is empty string "". - */ -int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @} */ - -#endif /* _FSL_STR_H */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_cdc_acm.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_cdc_acm.c deleted file mode 100644 index f6692488484..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_cdc_acm.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "usb_device_config.h" -#include "usb.h" -#include "usb_device.h" - -#if USB_DEVICE_CONFIG_CDC_ACM -#include "usb_device_cdc_acm.h" - -#endif diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_cdc_acm.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_cdc_acm.h deleted file mode 100644 index 20f1faff861..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_cdc_acm.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _USB_DEVICE_CDC_ACM_H_ -#define _USB_DEVICE_CDC_ACM_H_ 1 -/******************************************************************************* -* Definitions -******************************************************************************/ - -#define USB_DEVICE_CONFIG_CDC_ACM_MAX_INSTANCE (1) - -#define USB_DEVICE_CONFIG_CDC_COMM_CLASS_CODE (0x02) -#define USB_DEVICE_CONFIG_CDC_DATA_CLASS_CODE (0x0A) - -/* Class specific request Codes */ -#define USB_DEVICE_CDC_REQUEST_SEND_ENCAPSULATED_COMMAND (0x00) -#define USB_DEVICE_CDC_REQUEST_GET_ENCAPSULATED_RESPONSE (0x01) -#define USB_DEVICE_CDC_REQUEST_SET_COMM_FEATURE (0x02) -#define USB_DEVICE_CDC_REQUEST_GET_COMM_FEATURE (0x03) -#define USB_DEVICE_CDC_REQUEST_CLEAR_COMM_FEATURE (0x04) -#define USB_DEVICE_CDC_REQUEST_SET_AUX_LINE_STATE (0x10) -#define USB_DEVICE_CDC_REQUEST_SET_HOOK_STATE (0x11) -#define USB_DEVICE_CDC_REQUEST_PULSE_SETUP (0x12) -#define USB_DEVICE_CDC_REQUEST_SEND_PULSE (0x13) -#define USB_DEVICE_CDC_REQUEST_SET_PULSE_TIME (0x14) -#define USB_DEVICE_CDC_REQUEST_RING_AUX_JACK (0x15) -#define USB_DEVICE_CDC_REQUEST_SET_LINE_CODING (0x20) -#define USB_DEVICE_CDC_REQUEST_GET_LINE_CODING (0x21) -#define USB_DEVICE_CDC_REQUEST_SET_CONTROL_LINE_STATE (0x22) -#define USB_DEVICE_CDC_REQUEST_SEND_BREAK (0x23) -#define USB_DEVICE_CDC_REQUEST_SET_RINGER_PARAMS (0x30) -#define USB_DEVICE_CDC_REQUEST_GET_RINGER_PARAMS (0x31) -#define USB_DEVICE_CDC_REQUEST_SET_OPERATION_PARAM (0x32) -#define USB_DEVICE_CDC_REQUEST_GET_OPERATION_PARAM (0x33) -#define USB_DEVICE_CDC_REQUEST_SET_LINE_PARAMS (0x34) -#define USB_DEVICE_CDC_REQUEST_GET_LINE_PARAMS (0x35) -#define USB_DEVICE_CDC_REQUEST_DIAL_DIGITS (0x36) -#define USB_DEVICE_CDC_REQUEST_SET_UNIT_PARAMETER (0x37) -#define USB_DEVICE_CDC_REQUEST_GET_UNIT_PARAMETER (0x38) -#define USB_DEVICE_CDC_REQUEST_CLEAR_UNIT_PARAMETER (0x39) -#define USB_DEVICE_CDC_REQUEST_GET_PROFILE (0x3A) -#define USB_DEVICE_CDC_REQUEST_SET_ETHERNET_MULTICAST_FILTERS (0x40) -#define USB_DEVICE_CDC_REQUEST_SET_ETHERNET_POW_PATTER_FILTER (0x41) -#define USB_DEVICE_CDC_REQUEST_GET_ETHERNET_POW_PATTER_FILTER (0x42) -#define USB_DEVICE_CDC_REQUEST_SET_ETHERNET_PACKET_FILTER (0x43) -#define USB_DEVICE_CDC_REQUEST_GET_ETHERNET_STATISTIC (0x44) -#define USB_DEVICE_CDC_REQUEST_SET_ATM_DATA_FORMAT (0x50) -#define USB_DEVICE_CDC_REQUEST_GET_ATM_DEVICE_STATISTICS (0x51) -#define USB_DEVICE_CDC_REQUEST_SET_ATM_DEFAULT_VC (0x52) -#define USB_DEVICE_CDC_REQUEST_GET_ATM_VC_STATISTICS (0x53) -#define USB_DEVICE_CDC_REQUEST_MDLM_SPECIFIC_REQUESTS_MASK (0x7F) - -#define USB_DEVICE_CDC_REQUEST_GET_ABSTRACT_STATE (0x23) -#define USB_DEVICE_CDC_REQUEST_GET_COUNTRY_SETTING (0x24) -#define USB_DEVICE_CDC_REQUEST_SET_ABSTRACT_STATE (0x25) -#define USB_DEVICE_CDC_REQUEST_SET_COUNTRY_SETTING (0x26) -/* Class Specific Notification Codes */ -#define USB_DEVICE_CDC_REQUEST_NETWORK_CONNECTION_NOTIF (0x00) -#define USB_DEVICE_CDC_REQUEST_RESPONSE_AVAIL_NOTIF (0x01) -#define USB_DEVICE_CDC_REQUEST_AUX_JACK_HOOK_STATE_NOTIF (0x08) -#define USB_DEVICE_CDC_REQUEST_RING_DETECT_NOTIF (0x09) -#define USB_DEVICE_CDC_REQUEST_SERIAL_STATE_NOTIF (0x20) -#define USB_DEVICE_CDC_REQUEST_CALL_STATE_CHANGE_NOTIF (0x28) -#define USB_DEVICE_CDC_REQUEST_LINE_STATE_CHANGE_NOTIF (0x29) -#define USB_DEVICE_CDC_REQUEST_CONNECTION_SPEED_CHANGE_NOTIF (0x2A) -/* Communications Feature Selector Codes */ -#define USB_DEVICE_CDC_FEATURE_ABSTRACT_STATE (0x01) -#define USB_DEVICE_CDC_FEATURE_COUNTRY_SETTING (0x02) -/* Control Signal Bitmap Values */ -#define USB_DEVICE_CDC_CONTROL_SIG_BITMAP_CARRIER_ACTIVATION (0x02) -#define USB_DEVICE_CDC_CONTROL_SIG_BITMAP_DTE_PRESENCE (0x01) -/* UART State Bitmap Values */ -#define USB_DEVICE_CDC_UART_STATE_RX_CARRIER (0x01) -#define USB_DEVICE_CDC_UART_STATE_TX_CARRIER (0x02) -#define USB_DEVICE_CDC_UART_STATE_BREAK (0x04) -#define USB_DEVICE_CDC_UART_STATE_RING_SIGNAL (0x08) -#define USB_DEVICE_CDC_UART_STATE_FRAMING (0x10) -#define USB_DEVICE_CDC_UART_STATE_PARITY (0x20) -#define USB_DEVICE_CDC_UART_STATE_OVERRUN (0x40) - -#endif /* _USB_DEVICE_CDC_ACM_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_ch9.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_ch9.c deleted file mode 100644 index b8ee92b9e80..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_ch9.c +++ /dev/null @@ -1,947 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "usb_device_config.h" -#include "usb.h" - -#include "usb_device.h" -#include "usb_device_dci.h" -#include "usb_device_ch9.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief Standard request callback function typedef. - * - * This function is used to handle the standard request. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param setup The pointer of the setup packet. - * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. - * @param length It is an out parameter, the data length. - * - * @return A USB error code or kStatus_USB_Success. - */ -typedef usb_status_t (*usb_standard_request_callback_t)(usb_device_handle handle, - usb_setup_struct_t *setup, - uint8_t **buffer, - uint32_t *length); - -/******************************************************************************* -* Prototypes -******************************************************************************/ -/*! - * @brief Get the setup packet buffer. - * - * The function is used to get the setup packet buffer to save the setup packet data. - * - * @param handle The device handle. - * @param setupBuffer It is an OUT parameter, return the setup buffer address to the caller. - * - * @return A USB error code or kStatus_USB_Success. - */ -extern usb_status_t USB_DeviceGetSetupBuffer(usb_device_handle handle, usb_setup_struct_t **setupBuffer); - -/*! - * @brief Handle the class request. - * - * The function is used to handle the class request. - * - * @param handle The device handle. - * @param setup The setup packet buffer address. - * @param length It is an OUT parameter, return the data length need to be sent to host. - * @param buffer It is an OUT parameter, return the data buffer address. - * - * @return A USB error code or kStatus_USB_Success. - */ -extern usb_status_t USB_DeviceProcessClassRequest(usb_device_handle handle, - usb_setup_struct_t *setup, - uint32_t *length, - uint8_t **buffer); - -/*! - * @brief Get the buffer to save the class specific data sent from host. - * - * The function is used to get the buffer to save the class specific data sent from host. - * The function will be called when the device receives a setup pakcet, and the host needs to send data to the device in - * the data stage. - * - * @param handle The device handle. - * @param setup The setup packet buffer address. - * @param length Pass the length the host needs to sent. - * @param buffer It is an OUT parameter, return the data buffer address to save the host's data. - * - * @return A USB error code or kStatus_USB_Success. - */ -extern usb_status_t USB_DeviceGetClassReceiveBuffer(usb_device_handle handle, - usb_setup_struct_t *setup, - uint32_t *length, - uint8_t **buffer); - -/* standard request */ -/*! - * @brief Get the descritpor. - * - * The function is used to get the descritpor, including the device descritpor, configuration descriptor, and string - * descriptor, etc. - * - * @param handle The device handle. - * @param setup The setup packet buffer address. - * @param length It is an OUT parameter, return the data length need to be sent to host. - * @param buffer It is an OUT parameter, return the data buffer address. - * - * @return A USB error code or kStatus_USB_Success. - */ -extern usb_status_t USB_DeviceGetDescriptor(usb_device_handle handle, - usb_setup_struct_t *setup, - uint32_t *length, - uint8_t **buffer); - -/*! - * @brief Set the device configuration. - * - * The function is used to set the device configuration. - * - * @param handle The device handle. - * @param configure The configuration value. - * - * @return A USB error code or kStatus_USB_Success. - */ -extern usb_status_t USB_DeviceSetConfigure(usb_device_handle handle, uint8_t configure); - -/*! - * @brief Get the device configuration. - * - * The function is used to get the device configuration. - * - * @param handle The device handle. - * @param configure It is an OUT parameter, save the current configuration value. - * - * @return A USB error code or kStatus_USB_Success. - */ -extern usb_status_t USB_DeviceGetConfigure(usb_device_handle handle, uint8_t *configure); - -/*! - * @brief Set an interface alternate setting. - * - * The function is used to set an interface alternate setting. - * - * @param handle The device handle. - * @param interface The interface index. - * @param alternateSetting The new alternate setting value. - * - * @return A USB error code or kStatus_USB_Success. - */ -extern usb_status_t USB_DeviceSetInterface(usb_device_handle handle, uint8_t interface, uint8_t alternateSetting); - -/*! - * @brief Get an interface alternate setting. - * - * The function is used to get an interface alternate setting. - * - * @param handle The device handle. - * @param interface The interface index. - * @param alternateSetting It is an OUT parameter, save the new alternate setting value of the interface. - * - * @return A USB error code or kStatus_USB_Success. - */ -extern usb_status_t USB_DeviceGetInterface(usb_device_handle handle, uint8_t interface, uint8_t *alternateSetting); - -/*! - * @brief Configure a specified endpoint status. - * - * The function is used to configure a specified endpoint status, idle or halt. - * - * @param handle The device handle. - * @param endpointAddress The endpoint address, the BIT7 is the direction, 0 - USB_OUT, 1 - USB_IN. - * @param status The new status of the endpoint, 0 - idle, 1 - halt. - * - * @return A USB error code or kStatus_USB_Success. - */ -extern usb_status_t USB_DeviceConfigureEndpointStatus(usb_device_handle handle, - uint8_t endpointAddress, - uint8_t status); - -/*! - * @brief Configure the device remote wakeup feature. - * - * The function is used to configure the device remote wakeup feature, enable or disbale the remote wakeup feature. - * - * @param handle The device handle. - * @param enable The new feature value of the device remote wakeup, 0 - disable, 1 - enable. - * - * @return A USB error code or kStatus_USB_Success. - */ -extern usb_status_t USB_DeviceConfigureRemoteWakeup(usb_device_handle handle, uint8_t enable); - -static usb_status_t USB_DeviceCh9GetStatus(usb_device_handle handle, - usb_setup_struct_t *setup, - uint8_t **buffer, - uint32_t *length); -static usb_status_t USB_DeviceCh9SetClearFeature(usb_device_handle handle, - usb_setup_struct_t *setup, - uint8_t **buffer, - uint32_t *length); -static usb_status_t USB_DeviceCh9SetAddress(usb_device_handle handle, - usb_setup_struct_t *setup, - uint8_t **buffer, - uint32_t *length); -static usb_status_t USB_DeviceCh9GetDescriptor(usb_device_handle handle, - usb_setup_struct_t *setup, - uint8_t **buffer, - uint32_t *length); -static usb_status_t USB_DeviceCh9GetConfiguration(usb_device_handle handle, - usb_setup_struct_t *setup, - uint8_t **buffer, - uint32_t *length); -static usb_status_t USB_DeviceCh9SetConfiguration(usb_device_handle handle, - usb_setup_struct_t *setup, - uint8_t **buffer, - uint32_t *length); -static usb_status_t USB_DeviceCh9GetInterface(usb_device_handle handle, - usb_setup_struct_t *setup, - uint8_t **buffer, - uint32_t *length); -static usb_status_t USB_DeviceCh9SetInterface(usb_device_handle handle, - usb_setup_struct_t *setup, - uint8_t **buffer, - uint32_t *length); -static usb_status_t USB_DeviceCh9SynchFrame(usb_device_handle handle, - usb_setup_struct_t *setup, - uint8_t **buffer, - uint32_t *length); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* The function list to handle the standard request. */ -static const usb_standard_request_callback_t s_UsbDeviceStandardRequest[] = { - USB_DeviceCh9GetStatus, - USB_DeviceCh9SetClearFeature, - (usb_standard_request_callback_t)NULL, - USB_DeviceCh9SetClearFeature, - (usb_standard_request_callback_t)NULL, - USB_DeviceCh9SetAddress, - USB_DeviceCh9GetDescriptor, - (usb_standard_request_callback_t)NULL, /* USB_DeviceCh9SetDescriptor */ - USB_DeviceCh9GetConfiguration, - USB_DeviceCh9SetConfiguration, - USB_DeviceCh9GetInterface, - USB_DeviceCh9SetInterface, - USB_DeviceCh9SynchFrame, -}; - -/* - * The internal global variable. - * This variable is used in: - * get status request - * get configuration request - * get interface request - * set interface request - * get sync frame request - */ -static uint16_t s_UsbDeviceStandardRx; - -/******************************************************************************* -* Code -******************************************************************************/ -/*! - * @brief Handle get status request. - * - * This function is used to handle get status request. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param setup The pointer of the setup packet. - * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. - * @param length It is an out parameter, the data length. - * - * @retval kStatus_USB_Success The requst is handled successfully. - * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, - * or, the request is unsupported. - */ -static usb_status_t USB_DeviceCh9GetStatus(usb_device_handle handle, - usb_setup_struct_t *setup, - uint8_t **buffer, - uint32_t *length) -{ - usb_status_t error = kStatus_USB_InvalidRequest; - uint8_t state; - - USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); - - if ((kUSB_DeviceStateAddress != state) && (kUSB_DeviceStateConfigured != state)) - { - return error; - } - - if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_DEVICE) - { - /* Get the device status */ - error = USB_DeviceGetStatus(handle, kUSB_DeviceStatusDevice, &s_UsbDeviceStandardRx); - s_UsbDeviceStandardRx = s_UsbDeviceStandardRx & USB_GET_STATUS_DEVICE_MASK; - s_UsbDeviceStandardRx = USB_SHORT_TO_LITTLE_ENDIAN(s_UsbDeviceStandardRx); - /* The device status length must be USB_DEVICE_STATUS_SIZE. */ - *length = USB_DEVICE_STATUS_SIZE; - } - else if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_INTERFACE) - { - /* Get the interface status */ - error = kStatus_USB_Success; - s_UsbDeviceStandardRx = 0U; - /* The interface status length must be USB_INTERFACE_STATUS_SIZE. */ - *length = USB_INTERFACE_STATUS_SIZE; - } - else if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_ENDPOINT) - { - /* Get the endpoint status */ - usb_device_endpoint_status_struct_t endpointStatus; - endpointStatus.endpointAddress = (uint8_t)setup->wIndex; - endpointStatus.endpointStatus = kUSB_DeviceEndpointStateIdle; - error = USB_DeviceGetStatus(handle, kUSB_DeviceStatusEndpoint, &endpointStatus); - s_UsbDeviceStandardRx = endpointStatus.endpointStatus & USB_GET_STATUS_ENDPOINT_MASK; - s_UsbDeviceStandardRx = USB_SHORT_TO_LITTLE_ENDIAN(s_UsbDeviceStandardRx); - /* The endpoint status length must be USB_INTERFACE_STATUS_SIZE. */ - *length = USB_ENDPOINT_STATUS_SIZE; - } - else - { - } - *buffer = (uint8_t *)&s_UsbDeviceStandardRx; - - return error; -} - -/*! - * @brief Handle set or clear device feature request. - * - * This function is used to handle set or clear device feature request. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param setup The pointer of the setup packet. - * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. - * @param length It is an out parameter, the data length. - * - * @retval kStatus_USB_Success The requst is handled successfully. - * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, - * or, the request is unsupported. - */ -static usb_status_t USB_DeviceCh9SetClearFeature(usb_device_handle handle, - usb_setup_struct_t *setup, - uint8_t **buffer, - uint32_t *length) -{ - usb_status_t error = kStatus_USB_InvalidRequest; - uint8_t state; - uint8_t isSet = 0U; - - USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); - - if ((kUSB_DeviceStateAddress != state) && (kUSB_DeviceStateConfigured != state)) - { - return error; - } - - /* Identify the request is set or clear the feature. */ - if (USB_REQUEST_STANDARD_SET_FEATURE == setup->bRequest) - { - isSet = 1U; - } - - if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_DEVICE) - { - /* Set or Clear the device featrue. */ - if (USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_REMOTE_WAKEUP == setup->wValue) - { - /* Set or Clear the device remote wakeup featrue. */ - error = USB_DeviceConfigureRemoteWakeup(handle, isSet); - } -#if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U)) && \ - (defined(USB_DEVICE_CONFIG_EHCI_TEST_MODE) && (USB_DEVICE_CONFIG_EHCI_TEST_MODE > 0U)) - else if (USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_TEST_MODE == setup->wValue) - { - state = kUSB_DeviceStateTestMode; - error = USB_DeviceSetStatus(classHandle->handle, kUSB_DeviceStatusDeviceState, &state); - } -#endif - else - { - } - } - else if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_ENDPOINT) - { - /* Set or Clear the endpoint featrue. */ - if (USB_REQUEST_STANDARD_FEATURE_SELECTOR_ENDPOINT_HALT == setup->wValue) - { - if (USB_CONTROL_ENDPOINT == (setup->wIndex & USB_ENDPOINT_NUMBER_MASK)) - { - /* Set or Clear the control endpoint status(halt or not). */ - if (isSet) - { - USB_DeviceStallEndpoint(handle, (uint8_t)setup->wIndex); - } - else - { - USB_DeviceUnstallEndpoint(handle, (uint8_t)setup->wIndex); - } - } - - /* Set or Clear the endpoint status featrue. */ - error = USB_DeviceConfigureEndpointStatus(handle, setup->wIndex, isSet); - } - else - { - } - } - else - { - } - - return error; -} - -/*! - * @brief Handle set address request. - * - * This function is used to handle set address request. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param setup The pointer of the setup packet. - * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. - * @param length It is an out parameter, the data length. - * - * @retval kStatus_USB_Success The requst is handled successfully. - * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state. - */ -static usb_status_t USB_DeviceCh9SetAddress(usb_device_handle handle, - usb_setup_struct_t *setup, - uint8_t **buffer, - uint32_t *length) -{ - usb_status_t error = kStatus_USB_InvalidRequest; - uint8_t state; - - USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); - - if ((kUSB_DeviceStateAddressing != state) && (kUSB_DeviceStateAddress != state) && - (kUSB_DeviceStateDefault != state)) - { - return error; - } - - if (kUSB_DeviceStateAddressing != state) - { - /* If the device address is not setting, pass the address and the device state will change to - * kUSB_DeviceStateAddressing internally. */ - state = setup->wValue & 0xFFU; - error = USB_DeviceSetStatus(handle, kUSB_DeviceStatusAddress, &state); - } - else - { - /* If the device address is setting, set device address and the address will be write into the controller - * internally. */ - error = USB_DeviceSetStatus(handle, kUSB_DeviceStatusAddress, NULL); - /* And then change the device state to kUSB_DeviceStateAddress. */ - if (kStatus_USB_Success == error) - { - state = kUSB_DeviceStateAddress; - error = USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state); - } - } - - return error; -} - -/*! - * @brief Handle get descriptor request. - * - * This function is used to handle get descriptor request. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param setup The pointer of the setup packet. - * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. - * @param length It is an out parameter, the data length. - * - * @retval kStatus_USB_Success The requst is handled successfully. - * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, - * or, the request is unsupported. - */ -static usb_status_t USB_DeviceCh9GetDescriptor(usb_device_handle handle, - usb_setup_struct_t *setup, - uint8_t **buffer, - uint32_t *length) -{ - uint8_t state; - - USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); - - if ((kUSB_DeviceStateAddress != state) && (kUSB_DeviceStateConfigured != state) && - (kUSB_DeviceStateDefault != state)) - { - return kStatus_USB_InvalidRequest; - } - - return USB_DeviceGetDescriptor(handle, setup, length, buffer); -} - -/*! - * @brief Handle get current configuration request. - * - * This function is used to handle get current configuration request. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param setup The pointer of the setup packet. - * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. - * @param length It is an out parameter, the data length. - * - * @retval kStatus_USB_Success The requst is handled successfully. - * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, - * or, the request is unsupported. - */ -static usb_status_t USB_DeviceCh9GetConfiguration(usb_device_handle handle, - usb_setup_struct_t *setup, - uint8_t **buffer, - uint32_t *length) -{ - uint8_t state; - - USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); - - if ((kUSB_DeviceStateAddress != state) && ((kUSB_DeviceStateConfigured != state))) - { - return kStatus_USB_InvalidRequest; - } - - *length = USB_CONFIGURE_SIZE; - *buffer = (uint8_t *)&s_UsbDeviceStandardRx; - return USB_DeviceGetConfigure(handle, (uint8_t *)&s_UsbDeviceStandardRx); -} - -/*! - * @brief Handle set current configuration request. - * - * This function is used to handle set current configuration request. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param setup The pointer of the setup packet. - * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. - * @param length It is an out parameter, the data length. - * - * @retval kStatus_USB_Success The requst is handled successfully. - * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, - * or, the request is unsupported. - */ -static usb_status_t USB_DeviceCh9SetConfiguration(usb_device_handle handle, - usb_setup_struct_t *setup, - uint8_t **buffer, - uint32_t *length) -{ - uint8_t state; - - USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); - - if ((kUSB_DeviceStateAddress != state) && (kUSB_DeviceStateConfigured != state)) - { - return kStatus_USB_InvalidRequest; - } - - /* The device state is changed to kUSB_DeviceStateConfigured */ - state = kUSB_DeviceStateConfigured; - USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state); - if (!setup->wValue) - { - /* If the new configuration is zero, the device state is changed to kUSB_DeviceStateAddress */ - state = kUSB_DeviceStateAddress; - USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state); - } - - return USB_DeviceSetConfigure(handle, setup->wValue); -} - -/*! - * @brief Handle get the alternate setting of a interface request. - * - * This function is used to handle get the alternate setting of a interface request. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param setup The pointer of the setup packet. - * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. - * @param length It is an out parameter, the data length. - * - * @retval kStatus_USB_Success The requst is handled successfully. - * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, - * or, the request is unsupported. - */ -static usb_status_t USB_DeviceCh9GetInterface(usb_device_handle handle, - usb_setup_struct_t *setup, - uint8_t **buffer, - uint32_t *length) -{ - usb_status_t error = kStatus_USB_InvalidRequest; - uint8_t state; - - USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); - - if (state != kUSB_DeviceStateConfigured) - { - return error; - } - *length = USB_INTERFACE_SIZE; - *buffer = (uint8_t *)&s_UsbDeviceStandardRx; - - return USB_DeviceGetInterface(handle, setup->wIndex & 0xFFU, (uint8_t *)&s_UsbDeviceStandardRx); -} - -/*! - * @brief Handle set the alternate setting of a interface request. - * - * This function is used to handle set the alternate setting of a interface request. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param setup The pointer of the setup packet. - * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. - * @param length It is an out parameter, the data length. - * - * @retval kStatus_USB_Success The requst is handled successfully. - * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, - * or, the request is unsupported. - */ -static usb_status_t USB_DeviceCh9SetInterface(usb_device_handle handle, - usb_setup_struct_t *setup, - uint8_t **buffer, - uint32_t *length) -{ - uint8_t state; - - USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); - - if (state != kUSB_DeviceStateConfigured) - { - return kStatus_USB_InvalidRequest; - } - - return USB_DeviceSetInterface(handle, (setup->wIndex & 0xFFU), (setup->wValue & 0xFFU)); -} - -/*! - * @brief Handle get sync frame request. - * - * This function is used to handle get sync frame request. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param setup The pointer of the setup packet. - * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. - * @param length It is an out parameter, the data length. - * - * @retval kStatus_USB_Success The requst is handled successfully. - * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, - * or, the request is unsupported. - */ -static usb_status_t USB_DeviceCh9SynchFrame(usb_device_handle handle, - usb_setup_struct_t *setup, - uint8_t **buffer, - uint32_t *length) -{ - usb_status_t error = kStatus_USB_InvalidRequest; - uint8_t state; - - USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); - - if (state != kUSB_DeviceStateConfigured) - { - return error; - } - - s_UsbDeviceStandardRx = setup->wIndex; - /* Get the sync frame value */ - error = USB_DeviceGetStatus(handle, kUSB_DeviceStatusSynchFrame, &s_UsbDeviceStandardRx); - *buffer = (uint8_t *)&s_UsbDeviceStandardRx; - *length = sizeof(s_UsbDeviceStandardRx); - - return error; -} - -/*! - * @brief Send the reponse to the host. - * - * This function is used to send the reponse to the host. - * - * There are two cases this function will be called. - * Case one when a setup packet is received in control endpoint callback function: - * 1. If there is not data phase in the setup transfer, the function will prime an IN transfer with the data - * length is zero for status phase. - * 2. If there is an IN data phase, the function will prime an OUT transfer with the actual length to need to - * send for data phase. And then prime an IN transfer with the data length is zero for status phase. - * 3. If there is an OUT data phase, the function will prime an IN transfer with the actual length to want to - * receive for data phase. - * - * Case two when is not a setup packet received in control endpoint callback function: - * 1. The function will prime an IN transfer with data length is zero for status phase. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param setup The pointer of the setup packet. - * @param error The error code returned from the standard request fucntion. - * @param stage The stage of the control transfer. - * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. - * @param length It is an out parameter, the data length. - * - * @return A USB error code or kStatus_USB_Success. - */ -static usb_status_t USB_DeviceControlCallbackFeedback(usb_device_handle handle, - usb_setup_struct_t *setup, - usb_status_t error, - usb_device_control_read_write_sequence_t stage, - uint8_t **buffer, - uint32_t *length) -{ - usb_status_t errorCode = kStatus_USB_Error; - uint8_t direction = USB_IN; - - if (kStatus_USB_InvalidRequest == error) - { - /* Stall the control pipe when the request is unsupported. */ - if ((!((setup->bmRequestType & USB_REQUEST_TYPE_TYPE_MASK) == USB_REQUEST_TYPE_TYPE_STANDARD)) && - ((setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) == USB_REQUEST_TYPE_DIR_OUT) && (setup->wLength) && - (kUSB_DeviceControlPipeSetupStage == stage)) - { - direction = USB_OUT; - } - errorCode = USB_DeviceStallEndpoint( - handle, - (USB_CONTROL_ENDPOINT) | (uint8_t)((uint32_t)direction << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)); - } - else - { - if (*length > setup->wLength) - { - *length = setup->wLength; - } - errorCode = USB_DeviceSendRequest(handle, (USB_CONTROL_ENDPOINT), *buffer, *length); - - if ((kStatus_USB_Success == errorCode) && - (USB_REQUEST_TYPE_DIR_IN == (setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK))) - { - errorCode = USB_DeviceRecvRequest(handle, (USB_CONTROL_ENDPOINT), (uint8_t *)NULL, 0U); - } - } - return errorCode; -} - -/*! - * @brief Control endpoint callback function. - * - * This callback function is used to notify uplayer the tranfser result of a transfer. - * This callback pointer is passed when a sepcified endpoint initialied by calling API USB_DeviceInitEndpoint. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param message The result of a transfer, includes transfer buffer, transfer length and whether is in setup - * phase for control pipe. - * @param callbackParam The paramter for this callback. It is same with - * usb_device_endpoint_callback_struct_t::callbackParam. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceControlCallback(usb_device_handle handle, - usb_device_endpoint_callback_message_struct_t *message, - void *callbackParam) -{ - usb_setup_struct_t *deviceSetup; - uint8_t *setupOutBuffer; - uint8_t *buffer = (uint8_t *)NULL; - uint32_t length = 0U; - usb_status_t error = kStatus_USB_InvalidRequest; - uint8_t state; - - if (USB_UNINITIALIZED_VAL_32 == message->length) - { - return error; - } - - USB_DeviceGetSetupBuffer(handle, &deviceSetup); - USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); - - if (message->isSetup) - { - if ((USB_SETUP_PACKET_SIZE != message->length) || (NULL == message->buffer)) - { - /* If a invalid setup is received, the control pipes should be de-init and init again. - * Due to the IP can not meet this require, it is revesed for feature. - */ - /* - USB_DeviceDeinitEndpoint(handle, - USB_CONTROL_ENDPOINT | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)); - USB_DeviceDeinitEndpoint(handle, - USB_CONTROL_ENDPOINT | (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)); - USB_DeviceControlPipeInit(handle); - */ - return error; - } - /* Receive a setup request */ - usb_setup_struct_t *setup = (usb_setup_struct_t *)(message->buffer); - /* Copy the setup packet to the application buffer */ - deviceSetup->wValue = USB_SHORT_FROM_LITTLE_ENDIAN(setup->wValue); - deviceSetup->wIndex = USB_SHORT_FROM_LITTLE_ENDIAN(setup->wIndex); - deviceSetup->wLength = USB_SHORT_FROM_LITTLE_ENDIAN(setup->wLength); - deviceSetup->bRequest = setup->bRequest; - deviceSetup->bmRequestType = setup->bmRequestType; - - if ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_MASK) == USB_REQUEST_TYPE_TYPE_STANDARD) - { - /* Handle the standard request */ - if (s_UsbDeviceStandardRequest[deviceSetup->bRequest] != (usb_standard_request_callback_t)NULL) - { - error = s_UsbDeviceStandardRequest[deviceSetup->bRequest](handle, deviceSetup, &buffer, &length); - } - } - else - { - if ((deviceSetup->wLength) && - ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) == USB_REQUEST_TYPE_DIR_OUT)) - { - /* Class or vendor request with the OUT data phase. */ - if ((deviceSetup->wLength) && - ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_CLASS) == USB_REQUEST_TYPE_TYPE_CLASS)) - { - /* Get data buffer to receive the data from the host. */ - length = deviceSetup->wLength; - error = USB_DeviceGetClassReceiveBuffer(handle, deviceSetup, &length, &setupOutBuffer); - length = 0U; - } - else - { - } - if (kStatus_USB_Success == error) - { - /* Prime an OUT transfer */ - error = USB_DeviceRecvRequest(handle, USB_CONTROL_ENDPOINT, setupOutBuffer, deviceSetup->wLength); - return error; - } - } - else - { - /* Class or vendor request with the IN data phase. */ - if (((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_CLASS) == USB_REQUEST_TYPE_TYPE_CLASS)) - { - /* Get data buffer to response the host. */ - error = USB_DeviceProcessClassRequest(handle, deviceSetup, &length, &buffer); - } - else - { - } - } - } - /* Send the reponse to the host. */ - error = USB_DeviceControlCallbackFeedback(handle, deviceSetup, error, kUSB_DeviceControlPipeSetupStage, &buffer, - &length); - } - else if (kUSB_DeviceStateAddressing == state) - { - /* Set the device address to controller. */ - error = s_UsbDeviceStandardRequest[deviceSetup->bRequest](handle, deviceSetup, &buffer, &length); - } -#if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U)) && \ - (defined(USB_DEVICE_CONFIG_EHCI_TEST_MODE) && (USB_DEVICE_CONFIG_EHCI_TEST_MODE > 0U)) - else if (kUSB_DeviceStateTestMode == state) - { - uint8_t portTestControl = (uint8_t)(deviceSetup->wIndex >> 8); - /* Set the controller.into test mode. */ - error = USB_DeviceSetStatus(handle, kUSB_DeviceStatusTestMode, &portTestControl); - } -#endif - else if ((message->length) && (deviceSetup->wLength) && - ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) == USB_REQUEST_TYPE_DIR_OUT)) - { - if (((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_CLASS) == USB_REQUEST_TYPE_TYPE_CLASS)) - { - /* Data received in OUT phase, and notify the class driver. */ - error = USB_DeviceProcessClassRequest(handle, deviceSetup, &message->length, &message->buffer); - } - else - { - } - /* Send the reponse to the host. */ - error = USB_DeviceControlCallbackFeedback(handle, deviceSetup, error, kUSB_DeviceControlPipeDataStage, &buffer, - &length); - } - else - { - } - return error; -} - -/*! - * @brief Control endpoint initialization function. - * - * This callback function is used to initialize the control pipes. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param param The up layer handle. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceControlPipeInit(usb_device_handle handle) -{ - usb_device_endpoint_init_struct_t epInitStruct; - usb_device_endpoint_callback_struct_t endpointCallback; - usb_status_t error; - - endpointCallback.callbackFn = USB_DeviceControlCallback; - endpointCallback.callbackParam = handle; - - epInitStruct.zlt = 1U; - epInitStruct.transferType = USB_ENDPOINT_CONTROL; - epInitStruct.endpointAddress = USB_CONTROL_ENDPOINT | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT); - epInitStruct.maxPacketSize = USB_CONTROL_MAX_PACKET_SIZE; - /* Initialize the control IN pipe */ - error = USB_DeviceInitEndpoint(handle, &epInitStruct, &endpointCallback); - - if (kStatus_USB_Success != error) - { - return error; - } - epInitStruct.endpointAddress = USB_CONTROL_ENDPOINT | (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT); - /* Initialize the control OUT pipe */ - error = USB_DeviceInitEndpoint(handle, &epInitStruct, &endpointCallback); - - if (kStatus_USB_Success != error) - { - USB_DeviceDeinitEndpoint(handle, - USB_CONTROL_ENDPOINT | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)); - return error; - } - - return kStatus_USB_Success; -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_ch9.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_ch9.h deleted file mode 100644 index 0d964c800f4..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_ch9.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __USB_DEVICE_CH9_H__ -#define __USB_DEVICE_CH9_H__ - -/******************************************************************************* -* Definitions -******************************************************************************/ -/*! - * @addtogroup usb_device_ch9 - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Defines USB device status size when the host request to get device status */ -#define USB_DEVICE_STATUS_SIZE (0x02U) - -/*! @brief Defines USB device interface status size when the host request to get interface status */ -#define USB_INTERFACE_STATUS_SIZE (0x02U) - -/*! @brief Defines USB device endpoint status size when the host request to get endpoint status */ -#define USB_ENDPOINT_STATUS_SIZE (0x02U) - -/*! @brief Defines USB device configuration size when the host request to get current configuration */ -#define USB_CONFIGURE_SIZE (0X01U) - -/*! @brief Defines USB device interface alternate setting size when the host request to get interface alternate setting - */ -#define USB_INTERFACE_SIZE (0X01U) - -/*! @brief Defines USB device status mask */ -#define USB_GET_STATUS_DEVICE_MASK (0x03U) - -/*! @brief Defines USB device interface status mask */ -#define USB_GET_STATUS_INTERFACE_MASK (0x03U) - -/*! @brief Defines USB device endpoint status mask */ -#define USB_GET_STATUS_ENDPOINT_MASK (0x03U) - -/*! @brief Control read and write sequence */ -typedef enum _usb_device_control_read_write_sequence -{ - kUSB_DeviceControlPipeSetupStage = 0U, /*!< Setup stage */ - kUSB_DeviceControlPipeDataStage, /*!< Data stage */ - kUSB_DeviceControlPipeStatusStage, /*!< status stage */ -} usb_device_control_read_write_sequence_t; - -/******************************************************************************* -* API -******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @brief Initialize the control pipes. - * - * The function is used to initialize the control pipes. This function should be called when event - * kUSB_DeviceEventBusReset is received. - * - * @param handle The device handle. - * - * @return A USB error code or kStatus_USB_Success. - */ -extern usb_status_t USB_DeviceControlPipeInit(usb_device_handle handle); - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* __USB_DEVICE_CH9_H__ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_config.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_config.h deleted file mode 100644 index b9a5620e9bd..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_config.h +++ /dev/null @@ -1,183 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016 - 2018 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _USB_DEVICE_CONFIG_H_ -#define _USB_DEVICE_CONFIG_H_ - -/******************************************************************************* -* Definitions -******************************************************************************/ -/*! - * @name Hardware instance define - * @{ - */ - -/*! @brief KHCI instance count */ -#define USB_DEVICE_CONFIG_KHCI (0U) - -/*! @brief EHCI instance count */ -#define USB_DEVICE_CONFIG_EHCI (0U) - -/*! @brief LPC USB IP3511 FS instance count */ -#define USB_DEVICE_CONFIG_LPCIP3511FS (1U) - -/*! @brief LPC USB IP3511 HS instance count */ -#define USB_DEVICE_CONFIG_LPCIP3511HS (0U) - -/*! @brief Device instance count, the sum of KHCI and EHCI instance counts*/ -#define USB_DEVICE_CONFIG_NUM \ - (USB_DEVICE_CONFIG_KHCI + USB_DEVICE_CONFIG_EHCI + USB_DEVICE_CONFIG_LPCIP3511FS + USB_DEVICE_CONFIG_LPCIP3511HS) - -/* @} */ - -/*! - * @addtogroup usb_device_configuration - * @{ - */ - -/*! - * @name class instance define - * @{ - */ - -/*! @brief HID instance count */ -#define USB_DEVICE_CONFIG_HID (0U) - -/*! @brief CDC ACM instance count */ -#define USB_DEVICE_CONFIG_CDC_ACM (1U) - -/*! @brief MSC instance count */ -#define USB_DEVICE_CONFIG_MSC (0U) - -/*! @brief Audio instance count */ -#define USB_DEVICE_CONFIG_AUDIO (0U) - -/*! @brief PHDC instance count */ -#define USB_DEVICE_CONFIG_PHDC (0U) - -/*! @brief Video instance count */ -#define USB_DEVICE_CONFIG_VIDEO (0U) - -/*! @brief CCID instance count */ -#define USB_DEVICE_CONFIG_CCID (0U) - -/*! @brief Printer instance count */ -#define USB_DEVICE_CONFIG_PRINTER (0U) - -/*! @brief DFU instance count */ -#define USB_DEVICE_CONFIG_DFU (0U) - -/* @} */ - -/*! @brief Whether device is self power. 1U supported, 0U not supported */ -#define USB_DEVICE_CONFIG_SELF_POWER (1U) - -/*! @brief How many endpoints are supported in the stack. */ -#define USB_DEVICE_CONFIG_ENDPOINTS (4U) - -/*! @brief Whether the device task is enabled. */ -#define USB_DEVICE_CONFIG_USE_TASK (0U) - -/*! @brief How many the notification message are supported when the device task is enabled. */ -#define USB_DEVICE_CONFIG_MAX_MESSAGES (8U) - -/*! @brief Whether test mode enabled. */ -#define USB_DEVICE_CONFIG_USB20_TEST_MODE (0U) - -/*! @brief Whether device CV test is enabled. */ -#define USB_DEVICE_CONFIG_CV_TEST (0U) - -/*! @brief Whether device compliance test is enabled. If the macro is enabled, - the test mode and CV test macroes will be set.*/ -#define USB_DEVICE_CONFIG_COMPLIANCE_TEST (0U) - -#if ((defined(USB_DEVICE_CONFIG_COMPLIANCE_TEST)) && (USB_DEVICE_CONFIG_COMPLIANCE_TEST > 0U)) - -/*! @brief Undefine the marco USB_DEVICE_CONFIG_USB20_TEST_MODE. */ -#undef USB_DEVICE_CONFIG_USB20_TEST_MODE -/*! @brief Undefine the marco USB_DEVICE_CONFIG_CV_TEST. */ -#undef USB_DEVICE_CONFIG_CV_TEST - -/*! @brief enable the test mode. */ -#define USB_DEVICE_CONFIG_USB20_TEST_MODE (1U) - -/*! @brief enable the CV test */ -#define USB_DEVICE_CONFIG_CV_TEST (1U) - -#endif - -#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) - -/*! @brief The MAX buffer length for the KHCI DMA workaround.*/ -#define USB_DEVICE_CONFIG_KHCI_DMA_ALIGN_BUFFER_LENGTH (64U) -#endif - -#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) -/*! @brief How many the DTD are supported. */ -#define USB_DEVICE_CONFIG_EHCI_MAX_DTD (16U) - -/*! @brief Whether the EHCI ID pin detect feature enabled. */ -#define USB_DEVICE_CONFIG_EHCI_ID_PIN_DETECT (0U) -#endif - -/*! @brief Whether the keep alive feature enabled. */ -#define USB_DEVICE_CONFIG_KEEP_ALIVE_MODE (0U) - -/*! @brief Whether the transfer buffer is cache-enabled or not. */ -#ifndef USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE -#define USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE (0U) -#endif -/*! @brief Whether the low power mode is enabled or not. */ -#define USB_DEVICE_CONFIG_LOW_POWER_MODE (0U) - -#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) -/*! @brief Whether device remote wakeup supported. 1U supported, 0U not supported */ -#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U) - -/*! @brief Whether LPM is supported. 1U supported, 0U not supported */ -#define USB_DEVICE_CONFIG_LPM_L1 (0U) -#else -/*! @brief The device remote wakeup is unsupported. */ -#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U) -#endif - -/*! @brief Whether the device detached feature is enabled or not. */ -#define USB_DEVICE_CONFIG_DETACH_ENABLE (0U) - -/*! @brief Whether handle the USB bus error. */ -#define USB_DEVICE_CONFIG_ERROR_HANDLING (0U) - -/* @} */ - -#endif /* _USB_DEVICE_CONFIG_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_descriptor.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_descriptor.c deleted file mode 100644 index 8271e58a8ba..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_descriptor.c +++ /dev/null @@ -1,482 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "usb_device_config.h" -#include "usb.h" -#include "usb_device.h" - -#include "usb_device_cdc_acm.h" - -#include "usb_device_descriptor.h" - -/******************************************************************************* -* Variables -******************************************************************************/ -uint8_t g_currentConfigure = 0; -uint8_t g_interface[USB_CDC_VCOM_INTERFACE_COUNT]; - -/* Define device descriptor */ -uint8_t g_UsbDeviceDescriptor[USB_DESCRIPTOR_LENGTH_DEVICE] = { - /* Size of this descriptor in bytes */ - USB_DESCRIPTOR_LENGTH_DEVICE, - /* DEVICE Descriptor Type */ - USB_DESCRIPTOR_TYPE_DEVICE, - /* USB Specification Release Number in Binary-Coded Decimal (i.e., 2.10 is 210H). */ - USB_SHORT_GET_LOW(USB_DEVICE_SPECIFIC_BCD_VERSION), USB_SHORT_GET_HIGH(USB_DEVICE_SPECIFIC_BCD_VERSION), - /* Class code (assigned by the USB-IF). */ - USB_DEVICE_CLASS, - /* Subclass code (assigned by the USB-IF). */ - USB_DEVICE_SUBCLASS, - /* Protocol code (assigned by the USB-IF). */ - USB_DEVICE_PROTOCOL, - /* Maximum packet size for endpoint zero (only 8, 16, 32, or 64 are valid) */ - USB_CONTROL_MAX_PACKET_SIZE, - /* Vendor ID (assigned by the USB-IF) */ - 0xC9U, 0x1FU, - /* Product ID (assigned by the manufacturer) */ - 0x94, 0x00, - /* Device release number in binary-coded decimal */ - USB_SHORT_GET_LOW(USB_DEVICE_DEMO_BCD_VERSION), USB_SHORT_GET_HIGH(USB_DEVICE_DEMO_BCD_VERSION), - /* Index of string descriptor describing manufacturer */ - 0x01, - /* Index of string descriptor describing product */ - 0x02, - /* Index of string descriptor describing the device's serial number */ - 0x00, - /* Number of possible configurations */ - USB_DEVICE_CONFIGURATION_COUNT, -}; - -/* Define configuration descriptor */ -uint8_t g_UsbDeviceConfigurationDescriptor[USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL] = { - /* Size of this descriptor in bytes */ - USB_DESCRIPTOR_LENGTH_CONFIGURE, - /* CONFIGURATION Descriptor Type */ - USB_DESCRIPTOR_TYPE_CONFIGURE, - /* Total length of data returned for this configuration. */ - USB_SHORT_GET_LOW(USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL), - USB_SHORT_GET_HIGH(USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL), - /* Number of interfaces supported by this configuration */ - USB_CDC_VCOM_INTERFACE_COUNT, - /* Value to use as an argument to the SetConfiguration() request to select this configuration */ - USB_CDC_VCOM_CONFIGURE_INDEX, - /* Index of string descriptor describing this configuration */ - 0, - /* Configuration characteristics D7: Reserved (set to one) D6: Self-powered D5: Remote Wakeup D4...0: Reserved - (reset to zero) */ - (USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_MASK) | - (USB_DEVICE_CONFIG_SELF_POWER << USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_SHIFT) | - (USB_DEVICE_CONFIG_REMOTE_WAKEUP << USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_SHIFT), - /* Maximum power consumption of the USB * device from the bus in this specific * configuration when the device is - fully * operational. Expressed in 2 mA units * (i.e., 50 = 100 mA). */ - USB_DEVICE_MAX_POWER, - - /* Communication Interface Descriptor */ - USB_DESCRIPTOR_LENGTH_INTERFACE, USB_DESCRIPTOR_TYPE_INTERFACE, USB_CDC_VCOM_COMM_INTERFACE_INDEX, 0x00, - USB_CDC_VCOM_ENDPOINT_CIC_COUNT, USB_CDC_VCOM_CIC_CLASS, USB_CDC_VCOM_CIC_SUBCLASS, USB_CDC_VCOM_CIC_PROTOCOL, - 0x00, /* Interface Description String Index*/ - - /* CDC Class-Specific descriptor */ - USB_DESCRIPTOR_LENGTH_CDC_HEADER_FUNC, /* Size of this descriptor in bytes */ - USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */ - USB_CDC_HEADER_FUNC_DESC, 0x10, - 0x01, /* USB Class Definitions for Communications the Communication specification version 1.10 */ - - USB_DESCRIPTOR_LENGTH_CDC_CALL_MANAG, /* Size of this descriptor in bytes */ - USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */ - USB_CDC_CALL_MANAGEMENT_FUNC_DESC, - 0x01, /*Bit 0: Whether device handle call management itself 1, Bit 1: Whether device can send/receive call - management information over a Data Class Interface 0 */ - 0x01, /* Indicates multiplexed commands are handled via data interface */ - - USB_DESCRIPTOR_LENGTH_CDC_ABSTRACT, /* Size of this descriptor in bytes */ - USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */ - USB_CDC_ABSTRACT_CONTROL_FUNC_DESC, - 0x06, /* Bit 0: Whether device supports the request combination of Set_Comm_Feature, Clear_Comm_Feature, and - Get_Comm_Feature 0, Bit 1: Whether device supports the request combination of Set_Line_Coding, - Set_Control_Line_State, Get_Line_Coding, and the notification Serial_State 1, Bit ... */ - - USB_DESCRIPTOR_LENGTH_CDC_UNION_FUNC, /* Size of this descriptor in bytes */ - USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */ - USB_CDC_UNION_FUNC_DESC, 0x00, /* The interface number of the Communications or Data Class interface */ - 0x01, /* Interface number of subordinate interface in the Union */ - - /*Notification Endpoint descriptor */ - USB_DESCRIPTOR_LENGTH_ENDPOINT, USB_DESCRIPTOR_TYPE_ENDPOINT, USB_CDC_VCOM_INTERRUPT_IN_ENDPOINT | (USB_IN << 7U), - USB_ENDPOINT_INTERRUPT, USB_SHORT_GET_LOW(FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE), - USB_SHORT_GET_HIGH(FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE), FS_CDC_VCOM_INTERRUPT_IN_INTERVAL, - - /* Data Interface Descriptor */ - USB_DESCRIPTOR_LENGTH_INTERFACE, USB_DESCRIPTOR_TYPE_INTERFACE, USB_CDC_VCOM_DATA_INTERFACE_INDEX, 0x00, - USB_CDC_VCOM_ENDPOINT_DIC_COUNT, USB_CDC_VCOM_DIC_CLASS, USB_CDC_VCOM_DIC_SUBCLASS, USB_CDC_VCOM_DIC_PROTOCOL, - 0x00, /* Interface Description String Index*/ - - /*Bulk IN Endpoint descriptor */ - USB_DESCRIPTOR_LENGTH_ENDPOINT, USB_DESCRIPTOR_TYPE_ENDPOINT, USB_CDC_VCOM_BULK_IN_ENDPOINT | (USB_IN << 7U), - USB_ENDPOINT_BULK, USB_SHORT_GET_LOW(FS_CDC_VCOM_BULK_IN_PACKET_SIZE), - USB_SHORT_GET_HIGH(FS_CDC_VCOM_BULK_IN_PACKET_SIZE), 0x00, /* The polling interval value is every 0 Frames */ - - /*Bulk OUT Endpoint descriptor */ - USB_DESCRIPTOR_LENGTH_ENDPOINT, USB_DESCRIPTOR_TYPE_ENDPOINT, USB_CDC_VCOM_BULK_OUT_ENDPOINT | (USB_OUT << 7U), - USB_ENDPOINT_BULK, USB_SHORT_GET_LOW(FS_CDC_VCOM_BULK_OUT_PACKET_SIZE), - USB_SHORT_GET_HIGH(FS_CDC_VCOM_BULK_OUT_PACKET_SIZE), 0x00, /* The polling interval value is every 0 Frames */ -}; - -/* Define string descriptor */ -uint8_t g_UsbDeviceString0[USB_DESCRIPTOR_LENGTH_STRING0] = {sizeof(g_UsbDeviceString0), USB_DESCRIPTOR_TYPE_STRING, - 0x09, 0x04}; - -uint8_t g_UsbDeviceString1[USB_DESCRIPTOR_LENGTH_STRING1] = { - sizeof(g_UsbDeviceString1), - USB_DESCRIPTOR_TYPE_STRING, - 'N', - 0x00U, - 'X', - 0x00U, - 'P', - 0x00U, - ' ', - 0x00U, - 'S', - 0x00U, - 'E', - 0x00U, - 'M', - 0x00U, - 'I', - 0x00U, - 'C', - 0x00U, - 'O', - 0x00U, - 'N', - 0x00U, - 'D', - 0x00U, - 'U', - 0x00U, - 'C', - 0x00U, - 'T', - 0x00U, - 'O', - 0x00U, - 'R', - 0x00U, - 'S', - 0x00U, -}; - -uint8_t g_UsbDeviceString2[USB_DESCRIPTOR_LENGTH_STRING2] = {sizeof(g_UsbDeviceString2), - USB_DESCRIPTOR_TYPE_STRING, - 'M', - 0, - 'C', - 0, - 'U', - 0, - ' ', - 0, - 'V', - 0, - 'I', - 0, - 'R', - 0, - 'T', - 0, - 'U', - 0, - 'A', - 0, - 'L', - 0, - ' ', - 0, - 'C', - 0, - 'O', - 0, - 'M', - 0, - ' ', - 0, - 'D', - 0, - 'E', - 0, - 'M', - 0, - 'O', - 0}; - -uint8_t *g_UsbDeviceStringDescriptorArray[USB_DEVICE_STRING_COUNT] = {g_UsbDeviceString0, g_UsbDeviceString1, - g_UsbDeviceString2}; - -/* Define string descriptor size */ -uint32_t g_UsbDeviceStringDescriptorLength[USB_DEVICE_STRING_COUNT] = { - sizeof(g_UsbDeviceString0), sizeof(g_UsbDeviceString1), sizeof(g_UsbDeviceString2)}; -usb_language_t g_UsbDeviceLanguage[USB_DEVICE_LANGUAGE_COUNT] = {{ - g_UsbDeviceStringDescriptorArray, g_UsbDeviceStringDescriptorLength, (uint16_t)0x0409, -}}; - -usb_language_list_t g_UsbDeviceLanguageList = { - g_UsbDeviceString0, sizeof(g_UsbDeviceString0), g_UsbDeviceLanguage, USB_DEVICE_LANGUAGE_COUNT, -}; - -/******************************************************************************* -* Code -******************************************************************************/ -/*! - * @brief Get the descritpor. - * - * The function is used to get the descritpor, including the device descritpor, configuration descriptor, and string - * descriptor, etc. - * - * @param handle The device handle. - * @param setup The setup packet buffer address. - * @param length It is an OUT parameter, return the data length need to be sent to host. - * @param buffer It is an OUT parameter, return the data buffer address. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceGetDescriptor(usb_device_handle handle, - usb_setup_struct_t *setup, - uint32_t *length, - uint8_t **buffer) -{ - uint8_t descriptorType = (uint8_t)((setup->wValue & 0xFF00U) >> 8U); - uint8_t descriptorIndex = (uint8_t)((setup->wValue & 0x00FFU)); - usb_status_t ret = kStatus_USB_Success; - if (USB_REQUEST_STANDARD_GET_DESCRIPTOR != setup->bRequest) - { - return kStatus_USB_InvalidRequest; - } - switch (descriptorType) - { - case USB_DESCRIPTOR_TYPE_STRING: - { - if (descriptorIndex == 0) - { - *buffer = (uint8_t *)g_UsbDeviceLanguageList.languageString; - *length = g_UsbDeviceLanguageList.stringLength; - } - else - { - uint8_t langId = 0; - uint8_t langIndex = USB_DEVICE_STRING_COUNT; - - for (; langId < USB_DEVICE_LANGUAGE_COUNT; langId++) - { - if (setup->wIndex == g_UsbDeviceLanguageList.languageList[langId].languageId) - { - if (descriptorIndex < USB_DEVICE_STRING_COUNT) - { - langIndex = descriptorIndex; - } - break; - } - } - - if (USB_DEVICE_STRING_COUNT == langIndex) - { - langId = 0; - } - *buffer = (uint8_t *)g_UsbDeviceLanguageList.languageList[langId].string[langIndex]; - *length = g_UsbDeviceLanguageList.languageList[langId].length[langIndex]; - } - } - break; - case USB_DESCRIPTOR_TYPE_DEVICE: - { - *buffer = g_UsbDeviceDescriptor; - *length = USB_DESCRIPTOR_LENGTH_DEVICE; - } - break; - case USB_DESCRIPTOR_TYPE_CONFIGURE: - { - *buffer = g_UsbDeviceConfigurationDescriptor; - *length = USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL; - } - break; - default: - ret = kStatus_USB_InvalidRequest; - break; - } /* End Switch */ - return ret; -} - -/*! - * @brief Set the device configuration. - * - * The function is used to set the device configuration. - * - * @param handle The device handle. - * @param configure The configuration value. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceSetConfigure(usb_device_handle handle, uint8_t configure) -{ - if (!configure) - { - return kStatus_USB_Error; - } - g_currentConfigure = configure; - return USB_DeviceCallback(handle, kUSB_DeviceEventSetConfiguration, &configure); -} - -/*! - * @brief Get the device configuration. - * - * The function is used to get the device configuration. - * - * @param handle The device handle. - * @param configure It is an OUT parameter, save the current configuration value. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceGetConfigure(usb_device_handle handle, uint8_t *configure) -{ - *configure = g_currentConfigure; - return kStatus_USB_Success; -} - -/*! - * @brief Set an interface alternate setting. - * - * The function is used to set an interface alternate setting. - * - * @param handle The device handle. - * @param interface The interface index. - * @param alternateSetting The new alternate setting value. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceSetInterface(usb_device_handle handle, uint8_t interface, uint8_t alternateSetting) -{ - g_interface[interface] = alternateSetting; - return USB_DeviceCallback(handle, kUSB_DeviceEventSetInterface, &interface); -} - -/*! - * @brief Get an interface alternate setting. - * - * The function is used to get an interface alternate setting. - * - * @param handle The device handle. - * @param interface The interface index. - * @param alternateSetting It is an OUT parameter, save the new alternate setting value of the interface. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceGetInterface(usb_device_handle handle, uint8_t interface, uint8_t *alternateSetting) -{ - *alternateSetting = g_interface[interface]; - return kStatus_USB_Success; -} - -/*! - * @brief USB device set speed function. - * - * This function sets the speed of the USB device. - * - * Due to the difference of HS and FS descriptors, the device descriptors and configurations need to be updated to match - * current speed. - * As the default, the device descriptors and configurations are configured by using FS parameters for both EHCI and - * KHCI. - * When the EHCI is enabled, the application needs to call this fucntion to update device by using current speed. - * The updated information includes endpoint max packet size, endpoint interval, etc. - * - * @param handle The USB device handle. - * @param speed Speed type. USB_SPEED_HIGH/USB_SPEED_FULL/USB_SPEED_LOW. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceSetSpeed(usb_device_handle handle, uint8_t speed) -{ - usb_descriptor_union_t *ptr1; - usb_descriptor_union_t *ptr2; - - ptr1 = (usb_descriptor_union_t *)(&g_UsbDeviceConfigurationDescriptor[0]); - ptr2 = (usb_descriptor_union_t *)(&g_UsbDeviceConfigurationDescriptor[USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL - 1]); - - while (ptr1 < ptr2) - { - if (ptr1->common.bDescriptorType == USB_DESCRIPTOR_TYPE_ENDPOINT) - { - if (USB_CDC_VCOM_INTERRUPT_IN_ENDPOINT == (ptr1->endpoint.bEndpointAddress & 0x0FU)) - { - if (USB_SPEED_HIGH == speed) - { - ptr1->endpoint.bInterval = HS_CDC_VCOM_INTERRUPT_IN_INTERVAL; - USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(HS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE, - ptr1->endpoint.wMaxPacketSize); - } - else - { - ptr1->endpoint.bInterval = FS_CDC_VCOM_INTERRUPT_IN_INTERVAL; - USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE, - ptr1->endpoint.wMaxPacketSize); - } - } - else if (USB_CDC_VCOM_BULK_IN_ENDPOINT == (ptr1->endpoint.bEndpointAddress & 0x0FU)) - { - if (USB_SPEED_HIGH == speed) - { - USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(HS_CDC_VCOM_BULK_IN_PACKET_SIZE, ptr1->endpoint.wMaxPacketSize); - } - else - { - USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(FS_CDC_VCOM_BULK_IN_PACKET_SIZE, ptr1->endpoint.wMaxPacketSize); - } - } - else if (USB_CDC_VCOM_BULK_OUT_ENDPOINT == (ptr1->endpoint.bEndpointAddress & 0x0FU)) - { - if (USB_SPEED_HIGH == speed) - { - USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(HS_CDC_VCOM_BULK_OUT_PACKET_SIZE, ptr1->endpoint.wMaxPacketSize); - } - else - { - USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(FS_CDC_VCOM_BULK_OUT_PACKET_SIZE, ptr1->endpoint.wMaxPacketSize); - } - } - else - { - } - } - ptr1 = (usb_descriptor_union_t *)((uint8_t *)ptr1 + ptr1->common.bLength); - } - return kStatus_USB_Success; -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_descriptor.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_descriptor.h deleted file mode 100644 index 5b8c8084a26..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_descriptor.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _USB_DEVICE_DESCRIPTOR_H_ -#define _USB_DEVICE_DESCRIPTOR_H_ 1 - -/******************************************************************************* -* Definitions -******************************************************************************/ -#define USB_DEVICE_SPECIFIC_BCD_VERSION (0x0200) -#define USB_DEVICE_DEMO_BCD_VERSION (0x0101U) - -/* Communication Class Codes */ -#define CDC_COMM_CLASS (0x02) -/* Data Class Codes */ -#define CDC_DATA_CLASS (0x0A) - -/* Communication Class SubClass Codes */ -#define USB_CDC_DIRECT_LINE_CONTROL_MODEL (0x01) -#define USB_CDC_ABSTRACT_CONTROL_MODEL (0x02) -#define USB_CDC_TELEPHONE_CONTROL_MODEL (0x03) -#define USB_CDC_MULTI_CHANNEL_CONTROL_MODEL (0x04) -#define USB_CDC_CAPI_CONTROL_MOPDEL (0x05) -#define USB_CDC_ETHERNET_NETWORKING_CONTROL_MODEL (0x06) -#define USB_CDC_ATM_NETWORKING_CONTROL_MODEL (0x07) -#define USB_CDC_WIRELESS_HANDSET_CONTROL_MODEL (0x08) -#define USB_CDC_DEVICE_MANAGEMENT (0x09) -#define USB_CDC_MOBILE_DIRECT_LINE_MODEL (0x0A) -#define USB_CDC_OBEX (0x0B) -#define USB_CDC_ETHERNET_EMULATION_MODEL (0x0C) - -/* Communication Class Protocol Codes */ -#define USB_CDC_NO_CLASS_SPECIFIC_PROTOCOL (0x00) /*also for Data Class Protocol Code */ -#define USB_CDC_AT_250_PROTOCOL (0x01) -#define USB_CDC_AT_PCCA_101_PROTOCOL (0x02) -#define USB_CDC_AT_PCCA_101_ANNEX_O (0x03) -#define USB_CDC_AT_GSM_7_07 (0x04) -#define USB_CDC_AT_3GPP_27_007 (0x05) -#define USB_CDC_AT_TIA_CDMA (0x06) -#define USB_CDC_ETHERNET_EMULATION_PROTOCOL (0x07) -#define USB_CDC_EXTERNAL_PROTOCOL (0xFE) -#define USB_CDC_VENDOR_SPECIFIC (0xFF) /*also for Data Class Protocol Code */ - -/* Data Class Protocol Codes */ -#define USB_CDC_PYHSICAL_INTERFACE_PROTOCOL (0x30) -#define USB_CDC_HDLC_PROTOCOL (0x31) -#define USB_CDC_TRANSPARENT_PROTOCOL (0x32) -#define USB_CDC_MANAGEMENT_PROTOCOL (0x50) -#define USB_CDC_DATA_LINK_Q931_PROTOCOL (0x51) -#define USB_CDC_DATA_LINK_Q921_PROTOCOL (0x52) -#define USB_CDC_DATA_COMPRESSION_V42BIS (0x90) -#define USB_CDC_EURO_ISDN_PROTOCOL (0x91) -#define USB_CDC_RATE_ADAPTION_ISDN_V24 (0x92) -#define USB_CDC_CAPI_COMMANDS (0x93) -#define USB_CDC_HOST_BASED_DRIVER (0xFD) -#define USB_CDC_UNIT_FUNCTIONAL (0xFE) - -/* Descriptor SubType in Communications Class Functional Descriptors */ -#define USB_CDC_HEADER_FUNC_DESC (0x00) -#define USB_CDC_CALL_MANAGEMENT_FUNC_DESC (0x01) -#define USB_CDC_ABSTRACT_CONTROL_FUNC_DESC (0x02) -#define USB_CDC_DIRECT_LINE_FUNC_DESC (0x03) -#define USB_CDC_TELEPHONE_RINGER_FUNC_DESC (0x04) -#define USB_CDC_TELEPHONE_REPORT_FUNC_DESC (0x05) -#define USB_CDC_UNION_FUNC_DESC (0x06) -#define USB_CDC_COUNTRY_SELECT_FUNC_DESC (0x07) -#define USB_CDC_TELEPHONE_MODES_FUNC_DESC (0x08) -#define USB_CDC_TERMINAL_FUNC_DESC (0x09) -#define USB_CDC_NETWORK_CHANNEL_FUNC_DESC (0x0A) -#define USB_CDC_PROTOCOL_UNIT_FUNC_DESC (0x0B) -#define USB_CDC_EXTENSION_UNIT_FUNC_DESC (0x0C) -#define USB_CDC_MULTI_CHANNEL_FUNC_DESC (0x0D) -#define USB_CDC_CAPI_CONTROL_FUNC_DESC (0x0E) -#define USB_CDC_ETHERNET_NETWORKING_FUNC_DESC (0x0F) -#define USB_CDC_ATM_NETWORKING_FUNC_DESC (0x10) -#define USB_CDC_WIRELESS_CONTROL_FUNC_DESC (0x11) -#define USB_CDC_MOBILE_DIRECT_LINE_FUNC_DESC (0x12) -#define USB_CDC_MDLM_DETAIL_FUNC_DESC (0x13) -#define USB_CDC_DEVICE_MANAGEMENT_FUNC_DESC (0x14) -#define USB_CDC_OBEX_FUNC_DESC (0x15) -#define USB_CDC_COMMAND_SET_FUNC_DESC (0x16) -#define USB_CDC_COMMAND_SET_DETAIL_FUNC_DESC (0x17) -#define USB_CDC_TELEPHONE_CONTROL_FUNC_DESC (0x18) -#define USB_CDC_OBEX_SERVICE_ID_FUNC_DESC (0x19) - -/* usb descritpor length */ -#define USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL (67) -#define USB_DESCRIPTOR_LENGTH_CDC_HEADER_FUNC (5) -#define USB_DESCRIPTOR_LENGTH_CDC_CALL_MANAG (5) -#define USB_DESCRIPTOR_LENGTH_CDC_ABSTRACT (4) -#define USB_DESCRIPTOR_LENGTH_CDC_UNION_FUNC (5) - -#define USB_DEVICE_CONFIGURATION_COUNT (1) -#define USB_DEVICE_STRING_COUNT (3) -#define USB_DEVICE_LANGUAGE_COUNT (1) - -#define USB_CDC_VCOM_CONFIGURE_INDEX (1) - -#define USB_CDC_VCOM_ENDPOINT_CIC_COUNT (1) -#define USB_CDC_VCOM_ENDPOINT_DIC_COUNT (2) -#define USB_CDC_VCOM_INTERRUPT_IN_ENDPOINT (1) -#define USB_CDC_VCOM_BULK_IN_ENDPOINT (2) -#define USB_CDC_VCOM_BULK_OUT_ENDPOINT (3) -#define USB_CDC_VCOM_INTERFACE_COUNT (2) -#define USB_CDC_VCOM_COMM_INTERFACE_INDEX (0) -#define USB_CDC_VCOM_DATA_INTERFACE_INDEX (1) - -#define HS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE (16) -#define FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE (16) -#define HS_CDC_VCOM_INTERRUPT_IN_INTERVAL (0x07) /* 2^(7-1) = 8ms */ -#define FS_CDC_VCOM_INTERRUPT_IN_INTERVAL (0x08) -#define HS_CDC_VCOM_BULK_IN_PACKET_SIZE (512) -#define FS_CDC_VCOM_BULK_IN_PACKET_SIZE (64) -#define HS_CDC_VCOM_BULK_OUT_PACKET_SIZE (512) -#define FS_CDC_VCOM_BULK_OUT_PACKET_SIZE (64) - -#define USB_DESCRIPTOR_LENGTH_STRING0 (4) -#define USB_DESCRIPTOR_LENGTH_STRING1 (38) -#define USB_DESCRIPTOR_LENGTH_STRING2 (42) - -#define USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE (0x24) -#define USB_DESCRIPTOR_TYPE_CDC_CS_ENDPOINT (0x25) - -#define USB_DEVICE_CLASS (0x02) -#define USB_DEVICE_SUBCLASS (0x00) -#define USB_DEVICE_PROTOCOL (0x00) - -#define USB_DEVICE_MAX_POWER (0x32) - -#define USB_CDC_VCOM_CIC_CLASS (CDC_COMM_CLASS) -#define USB_CDC_VCOM_CIC_SUBCLASS (USB_CDC_ABSTRACT_CONTROL_MODEL) -#define USB_CDC_VCOM_CIC_PROTOCOL (USB_CDC_NO_CLASS_SPECIFIC_PROTOCOL) - -#define USB_CDC_VCOM_DIC_CLASS (CDC_DATA_CLASS) -#define USB_CDC_VCOM_DIC_SUBCLASS (0x00) -#define USB_CDC_VCOM_DIC_PROTOCOL (USB_CDC_NO_CLASS_SPECIFIC_PROTOCOL) - -/******************************************************************************* -* API -******************************************************************************/ -/*! - * @brief USB device callback function. - * - * This function handles the usb device specific requests. - * - * @param handle The USB device handle. - * @param event The USB device event type. - * @param param The parameter of the device specific request. - * - * @return A USB error code or kStatus_USB_Success. - */ -extern usb_status_t USB_DeviceCallback(usb_device_handle handle, uint32_t event, void *param); - -/*! - * @brief USB device set speed function. - * - * This function sets the speed of the USB device. - * - * Due to the difference of HS and FS descriptors, the device descriptors and configurations need to be updated to match - * current speed. - * As the default, the device descriptors and configurations are configured by using FS parameters for both EHCI and - * KHCI. - * When the EHCI is enabled, the application needs to call this fucntion to update device by using current speed. - * The updated information includes endpoint max packet size, endpoint interval, etc. - * - * @param handle The USB device handle. - * @param speed Speed type. USB_SPEED_HIGH/USB_SPEED_FULL/USB_SPEED_LOW. - * - * @return A USB error code or kStatus_USB_Success. - */ -extern usb_status_t USB_DeviceSetSpeed(usb_device_handle handle, uint8_t speed); - -#endif /* _USB_DEVICE_DESCRIPTOR_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/virtual_com.c b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/virtual_com.c deleted file mode 100644 index d9e507fbc61..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/virtual_com.c +++ /dev/null @@ -1,693 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_device_registers.h" -#include "clock_config.h" -#include "board.h" - -#include -#include - -#include "usb_device_config.h" -#include "usb.h" -#include "usb_device.h" - -#include "usb_device_cdc_acm.h" -#include "usb_device_ch9.h" - -#include "usb_device_descriptor.h" -#include "virtual_com.h" -#if (defined(FSL_FEATURE_SOC_SYSMPU_COUNT) && (FSL_FEATURE_SOC_SYSMPU_COUNT > 0U)) -#include "fsl_sysmpu.h" -#endif /* FSL_FEATURE_SOC_SYSMPU_COUNT */ -#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0) -#include "usb_phy.h" -#endif - -/* Provided by users. */ -extern void USB_DeviceClockInit(void); -extern void USB_DeviceIsrEnable(void); -/******************************************************************************* -* Definitions -******************************************************************************/ - -/******************************************************************************* -* Variables -******************************************************************************/ -/* Data structure of virtual com device */ -usb_cdc_vcom_struct_t s_cdcVcom; - -/* Line codinig of cdc device */ -static uint8_t s_lineCoding[LINE_CODING_SIZE] = { - /* E.g. 0x00,0xC2,0x01,0x00 : 0x0001C200 is 115200 bits per second */ - (LINE_CODING_DTERATE >> 0U) & 0x000000FFU, - (LINE_CODING_DTERATE >> 8U) & 0x000000FFU, - (LINE_CODING_DTERATE >> 16U) & 0x000000FFU, - (LINE_CODING_DTERATE >> 24U) & 0x000000FFU, - LINE_CODING_CHARFORMAT, - LINE_CODING_PARITYTYPE, - LINE_CODING_DATABITS}; - -/* Abstract state of cdc device */ -static uint8_t s_abstractState[COMM_FEATURE_DATA_SIZE] = {(STATUS_ABSTRACT_STATE >> 0U) & 0x00FFU, - (STATUS_ABSTRACT_STATE >> 8U) & 0x00FFU}; - -/* Country code of cdc device */ -static uint8_t s_countryCode[COMM_FEATURE_DATA_SIZE] = {(COUNTRY_SETTING >> 0U) & 0x00FFU, - (COUNTRY_SETTING >> 8U) & 0x00FFU}; - -/* CDC ACM information */ -static usb_cdc_acm_info_t s_usbCdcAcmInfo = {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0, 0, 0, 0, 0}; - -/* Data buffer for receiving and sending*/ -static uint8_t s_currRecvBuf[DATA_BUFF_SIZE]; -volatile static uint32_t s_recvSize = 0; -volatile static uint32_t s_sendSize = 0; -volatile static uint8_t s_sendComplete = 0; -volatile static uint8_t s_currRecvIndex = 0; -static uint32_t s_usbBulkMaxPacketSize = FS_CDC_VCOM_BULK_OUT_PACKET_SIZE; -/******************************************************************************* -* Prototypes -******************************************************************************/ - -/******************************************************************************* -* Code -******************************************************************************/ -/*! - * @brief Interrupt in pipe callback function. - * - * This function serves as the callback function for interrupt in pipe. - * - * @param handle The USB device handle. - * @param message The endpoint callback message - * @param callbackParam The parameter of the callback. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceCdcAcmInterruptIn(usb_device_handle handle, - usb_device_endpoint_callback_message_struct_t *message, - void *callbackParam) -{ - usb_status_t error = kStatus_USB_Error; - - return error; -} - -/*! - * @brief Bulk in pipe callback function. - * - * This function serves as the callback function for bulk in pipe. - * - * @param handle The USB device handle. - * @param message The endpoint callback message - * @param callbackParam The parameter of the callback. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceCdcAcmBulkIn(usb_device_handle handle, - usb_device_endpoint_callback_message_struct_t *message, - void *callbackParam) -{ - usb_status_t error = kStatus_USB_Error; - - if ((message->length != 0) && (!(message->length % s_usbBulkMaxPacketSize))) - { - /* If the last packet is the size of endpoint, then send also zero-ended packet, - ** meaning that we want to inform the host that we do not have any additional - ** data, so it can flush the output. - */ - USB_DeviceSendRequest(handle, USB_CDC_VCOM_BULK_IN_ENDPOINT, NULL, 0); - } - else if ((1 == s_cdcVcom.attach) && (1 == s_cdcVcom.startTransactions)) - { - if ((message->buffer != NULL) || ((message->buffer == NULL) && (message->length == 0))) - { - /* User: add your own code for send complete event */ - s_sendComplete = 1; -#if defined(FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED) && (FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED > 0U) && \ - defined(USB_DEVICE_CONFIG_KEEP_ALIVE_MODE) && (USB_DEVICE_CONFIG_KEEP_ALIVE_MODE > 0U) && \ - defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U) - USB0->INTEN &= ~USB_INTEN_SOFTOKEN_MASK; -#endif - } - } - else if ((0 == s_sendComplete) && (1 == s_cdcVcom.attach) && (0 == s_cdcVcom.startTransactions)) - { - s_sendComplete = 1; - } - else - { - } - return error; -} - -/*! - * @brief Bulk out pipe callback function. - * - * This function serves as the callback function for bulk out pipe. - * - * @param handle The USB device handle. - * @param message The endpoint callback message - * @param callbackParam The parameter of the callback. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceCdcAcmBulkOut(usb_device_handle handle, - usb_device_endpoint_callback_message_struct_t *message, - void *callbackParam) -{ - usb_status_t error = kStatus_USB_Error; - if (USB_UNINITIALIZED_VAL_32 == message->length) - { - s_recvSize = 0xFFFFFFFFU; - } - else if ((1 == s_cdcVcom.attach) && (1 == s_cdcVcom.startTransactions)) - { - s_recvSize = message->length; -#if defined(FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED) && (FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED > 0U) && \ - defined(USB_DEVICE_CONFIG_KEEP_ALIVE_MODE) && (USB_DEVICE_CONFIG_KEEP_ALIVE_MODE > 0U) && \ - defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U) - USB0->INTEN |= USB_INTEN_SOFTOKEN_MASK; -#endif - if (!s_recvSize) - { -#if defined(FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED) && (FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED > 0U) && \ - defined(USB_DEVICE_CONFIG_KEEP_ALIVE_MODE) && (USB_DEVICE_CONFIG_KEEP_ALIVE_MODE > 0U) && \ - defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U) - USB0->INTEN &= ~USB_INTEN_SOFTOKEN_MASK; -#endif - } - } - else - { - } - return error; -} - -/*! - * @brief Get the setup packet buffer. - * - * This function provides the buffer for setup packet. - * - * @param handle The USB device handle. - * @param setupBuffer The pointer to the address of setup packet buffer. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceGetSetupBuffer(usb_device_handle handle, usb_setup_struct_t **setupBuffer) -{ - static uint32_t cdcVcomSetup[2]; - if (NULL == setupBuffer) - { - return kStatus_USB_InvalidParameter; - } - *setupBuffer = (usb_setup_struct_t *)&cdcVcomSetup; - return kStatus_USB_Success; -} - -/*! - * @brief Get the setup packet data buffer. - * - * This function gets the data buffer for setup packet. - * - * @param handle The USB device handle. - * @param setup The pointer to the setup packet. - * @param length The pointer to the length of the data buffer. - * @param buffer The pointer to the address of setup packet data buffer. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceGetClassReceiveBuffer(usb_device_handle handle, - usb_setup_struct_t *setup, - uint32_t *length, - uint8_t **buffer) -{ - static uint8_t setupOut[8]; - if ((NULL == buffer) || ((*length) > sizeof(setupOut))) - { - return kStatus_USB_InvalidRequest; - } - *buffer = setupOut; - return kStatus_USB_Success; -} - -/*! - * @brief Configure remote wakeup feature. - * - * This function configures the remote wakeup feature. - * - * @param handle The USB device handle. - * @param enable 1: enable, 0: disable. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceConfigureRemoteWakeup(usb_device_handle handle, uint8_t enable) -{ - return kStatus_USB_InvalidRequest; -} - -/*! - * @brief CDC class specific callback function. - * - * This function handles the CDC class specific requests. - * - * @param handle The USB device handle. - * @param setup The pointer to the setup packet. - * @param length The pointer to the length of the data buffer. - * @param buffer The pointer to the address of setup packet data buffer. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceProcessClassRequest(usb_device_handle handle, - usb_setup_struct_t *setup, - uint32_t *length, - uint8_t **buffer) -{ - usb_status_t error = kStatus_USB_InvalidRequest; - - usb_cdc_acm_info_t *acmInfo = &s_usbCdcAcmInfo; - uint32_t len; - uint16_t *uartBitmap; - if (setup->wIndex != USB_CDC_VCOM_COMM_INTERFACE_INDEX) - { - return error; - } - - switch (setup->bRequest) - { - case USB_DEVICE_CDC_REQUEST_SEND_ENCAPSULATED_COMMAND: - break; - case USB_DEVICE_CDC_REQUEST_GET_ENCAPSULATED_RESPONSE: - break; - case USB_DEVICE_CDC_REQUEST_SET_COMM_FEATURE: - if (USB_DEVICE_CDC_FEATURE_ABSTRACT_STATE == setup->wValue) - { - *buffer = s_abstractState; - } - else if (USB_DEVICE_CDC_FEATURE_COUNTRY_SETTING == setup->wValue) - { - *buffer = s_countryCode; - } - else - { - } - error = kStatus_USB_Success; - break; - case USB_DEVICE_CDC_REQUEST_GET_COMM_FEATURE: - if (USB_DEVICE_CDC_FEATURE_ABSTRACT_STATE == setup->wValue) - { - *buffer = s_abstractState; - *length = COMM_FEATURE_DATA_SIZE; - } - else if (USB_DEVICE_CDC_FEATURE_COUNTRY_SETTING == setup->wValue) - { - *buffer = s_countryCode; - *length = COMM_FEATURE_DATA_SIZE; - } - else - { - } - error = kStatus_USB_Success; - break; - case USB_DEVICE_CDC_REQUEST_CLEAR_COMM_FEATURE: - break; - case USB_DEVICE_CDC_REQUEST_GET_LINE_CODING: - *buffer = s_lineCoding; - *length = LINE_CODING_SIZE; - error = kStatus_USB_Success; - break; - case USB_DEVICE_CDC_REQUEST_SET_LINE_CODING: - *buffer = s_lineCoding; - error = kStatus_USB_Success; - break; - case USB_DEVICE_CDC_REQUEST_SET_CONTROL_LINE_STATE: - { - acmInfo->dteStatus = setup->wValue; - /* activate/deactivate Tx carrier */ - if (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_CARRIER_ACTIVATION) - { - acmInfo->uartState |= USB_DEVICE_CDC_UART_STATE_TX_CARRIER; - } - else - { - acmInfo->uartState &= (uint16_t)~USB_DEVICE_CDC_UART_STATE_TX_CARRIER; - } - - /* activate carrier and DTE */ - if (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_DTE_PRESENCE) - { - acmInfo->uartState |= USB_DEVICE_CDC_UART_STATE_RX_CARRIER; - } - else - { - acmInfo->uartState &= (uint16_t)~USB_DEVICE_CDC_UART_STATE_RX_CARRIER; - } - - /* Indicates to DCE if DTE is present or not */ - acmInfo->dtePresent = (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_DTE_PRESENCE) ? true : false; - - /* Initialize the serial state buffer */ - acmInfo->serialStateBuf[0] = NOTIF_REQUEST_TYPE; /* bmRequestType */ - acmInfo->serialStateBuf[1] = USB_DEVICE_CDC_REQUEST_SERIAL_STATE_NOTIF; /* bNotification */ - acmInfo->serialStateBuf[2] = 0x00; /* wValue */ - acmInfo->serialStateBuf[3] = 0x00; - acmInfo->serialStateBuf[4] = 0x00; /* wIndex */ - acmInfo->serialStateBuf[5] = 0x00; - acmInfo->serialStateBuf[6] = UART_BITMAP_SIZE; /* wLength */ - acmInfo->serialStateBuf[7] = 0x00; - /* Notifiy to host the line state */ - acmInfo->serialStateBuf[4] = setup->wIndex; - /* Lower byte of UART BITMAP */ - uartBitmap = (uint16_t *)&acmInfo->serialStateBuf[NOTIF_PACKET_SIZE + UART_BITMAP_SIZE - 2]; - *uartBitmap = acmInfo->uartState; - len = (uint32_t)(NOTIF_PACKET_SIZE + UART_BITMAP_SIZE); - error = USB_DeviceSendRequest(handle, USB_CDC_VCOM_INTERRUPT_IN_ENDPOINT, acmInfo->serialStateBuf, len); - - /* Update status */ - if (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_CARRIER_ACTIVATION) - { - /* To do: CARRIER_ACTIVATED */ - } - else - { - /* To do: CARRIER_DEACTIVATED */ - } - if (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_DTE_PRESENCE) - { - /* DTE_ACTIVATED */ - if (1 == s_cdcVcom.attach) - { - s_cdcVcom.startTransactions = 1; -#if defined(FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED) && (FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED > 0U) && \ - defined(USB_DEVICE_CONFIG_KEEP_ALIVE_MODE) && (USB_DEVICE_CONFIG_KEEP_ALIVE_MODE > 0U) && \ - defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U) - USB0->INTEN &= ~USB_INTEN_SOFTOKEN_MASK; -#endif - } - } - else - { - /* DTE_DEACTIVATED */ - if (1 == s_cdcVcom.attach) - { - s_cdcVcom.startTransactions = 0; - } - } - } - break; - case USB_DEVICE_CDC_REQUEST_SEND_BREAK: - break; - default: - break; - } - - return error; -} - -/*! - * @brief USB device callback function. - * - * This function handles the usb device specific requests. - * - * @param handle The USB device handle. - * @param event The USB device event type. - * @param param The parameter of the device specific request. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceCallback(usb_device_handle handle, uint32_t event, void *param) -{ - usb_status_t error = kStatus_USB_Error; - uint8_t *temp8 = (uint8_t *)param; - - switch (event) - { - case kUSB_DeviceEventBusReset: - { - USB_DeviceControlPipeInit(s_cdcVcom.deviceHandle); - s_cdcVcom.attach = 0; -#if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0)) || \ - (defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) - if (kStatus_USB_Success == - USB_DeviceGetStatus(s_cdcVcom.deviceHandle, kUSB_DeviceStatusSpeed, &s_cdcVcom.speed)) - { - USB_DeviceSetSpeed(handle, s_cdcVcom.speed); - } -#endif - } - break; - case kUSB_DeviceEventSetConfiguration: - if (param) - { - s_cdcVcom.attach = 1; - s_cdcVcom.currentConfiguration = *temp8; - if (USB_CDC_VCOM_CONFIGURE_INDEX == (*temp8)) - { - usb_device_endpoint_init_struct_t epInitStruct; - usb_device_endpoint_callback_struct_t endpointCallback; - - /* Initiailize endpoint for interrupt pipe */ - endpointCallback.callbackFn = USB_DeviceCdcAcmInterruptIn; - endpointCallback.callbackParam = handle; - - epInitStruct.zlt = 0; - epInitStruct.transferType = USB_ENDPOINT_INTERRUPT; - epInitStruct.endpointAddress = USB_CDC_VCOM_INTERRUPT_IN_ENDPOINT | - (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT); - if (USB_SPEED_HIGH == s_cdcVcom.speed) - { - epInitStruct.maxPacketSize = HS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE; - } - else - { - epInitStruct.maxPacketSize = FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE; - } - - USB_DeviceInitEndpoint(s_cdcVcom.deviceHandle, &epInitStruct, &endpointCallback); - - /* Initiailize endpoints for bulk pipe */ - endpointCallback.callbackFn = USB_DeviceCdcAcmBulkIn; - endpointCallback.callbackParam = handle; - - epInitStruct.zlt = 0; - epInitStruct.transferType = USB_ENDPOINT_BULK; - epInitStruct.endpointAddress = - USB_CDC_VCOM_BULK_IN_ENDPOINT | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT); - if (USB_SPEED_HIGH == s_cdcVcom.speed) - { - epInitStruct.maxPacketSize = HS_CDC_VCOM_BULK_IN_PACKET_SIZE; - } - else - { - epInitStruct.maxPacketSize = FS_CDC_VCOM_BULK_IN_PACKET_SIZE; - } - - USB_DeviceInitEndpoint(s_cdcVcom.deviceHandle, &epInitStruct, &endpointCallback); - - endpointCallback.callbackFn = USB_DeviceCdcAcmBulkOut; - endpointCallback.callbackParam = handle; - - epInitStruct.zlt = 0; - epInitStruct.transferType = USB_ENDPOINT_BULK; - epInitStruct.endpointAddress = - USB_CDC_VCOM_BULK_OUT_ENDPOINT | (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT); - if (USB_SPEED_HIGH == s_cdcVcom.speed) - { - epInitStruct.maxPacketSize = HS_CDC_VCOM_BULK_OUT_PACKET_SIZE; - } - else - { - epInitStruct.maxPacketSize = FS_CDC_VCOM_BULK_OUT_PACKET_SIZE; - } - - USB_DeviceInitEndpoint(s_cdcVcom.deviceHandle, &epInitStruct, &endpointCallback); - - if (USB_SPEED_HIGH == s_cdcVcom.speed) - { - s_usbBulkMaxPacketSize = HS_CDC_VCOM_BULK_OUT_PACKET_SIZE; - } - else - { - s_usbBulkMaxPacketSize = FS_CDC_VCOM_BULK_OUT_PACKET_SIZE; - } - } - } - break; - default: - break; - } - - return error; -} - -/*! - * @brief USB configure endpoint function. - * - * This function configure endpoint status. - * - * @param handle The USB device handle. - * @param ep Endpoint address. - * @param status A flag to indicate whether to stall the endpoint. 1: stall, 0: unstall. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceConfigureEndpointStatus(usb_device_handle handle, uint8_t ep, uint8_t status) -{ - if (status) - { - return USB_DeviceStallEndpoint(handle, ep); - } - else - { - return USB_DeviceUnstallEndpoint(handle, ep); - } -} - -/* See virtual_com.h for documentation of this function. */ -void USB_VcomWriteBlocking(usb_device_handle baseAddr, const uint8_t *buf, size_t count) -{ - while ((s_cdcVcom.attach != 1) || (s_cdcVcom.startTransactions != 1)) - { - __NOP(); - }; - USB_DeviceSendRequest((usb_device_handle)baseAddr, USB_CDC_VCOM_BULK_IN_ENDPOINT, (uint8_t *)buf, count); - while (!s_sendComplete) - { - __NOP(); - }; - s_sendComplete = 0; -} - -/* See virtual_com.h for documentation of this function. */ -status_t USB_VcomReadBlocking(usb_device_handle baseAddr, uint8_t *buf, size_t count) -{ - status_t error = kStatus_Success; - size_t bufIndex = 0U, bytesToReceive = 0U; - assert(count != 0U); - - /* Waiting for the USB ready. */ - while ((s_cdcVcom.attach != 1) || (s_cdcVcom.startTransactions != 1)) - { - __NOP(); - }; - - do - { - /* If no receive request. */ - if (s_recvSize <= 0) - { - if (kStatus_USB_Success != - USB_DeviceRecvRequest(baseAddr, USB_CDC_VCOM_BULK_OUT_ENDPOINT, s_currRecvBuf, s_usbBulkMaxPacketSize)) - { - return kStatus_Fail; - } - s_currRecvIndex = 0; - } - /* Waiting for data received by virtual com. */ - while (s_recvSize <= 0) - { - __NOP(); - }; - - /* When receive request is error. */ - if (0xFFFFFFFFU == s_recvSize) - { - /* Waiting for the USB ready and transfer started. */ - while ((s_cdcVcom.attach != 1) || (s_cdcVcom.startTransactions != 1)) - { - __NOP(); - }; - s_recvSize = 0; - } - else - { - bytesToReceive = MIN(count, s_recvSize); - memcpy((void *)&buf[bufIndex], s_currRecvBuf + s_currRecvIndex, bytesToReceive); - count -= bytesToReceive; - s_recvSize -= bytesToReceive; - bufIndex += bytesToReceive; - s_currRecvIndex += bytesToReceive; - } - } while (0U != count); - return error; -} - -/* See virtual_com.h for documentation of this function. */ -usb_device_handle USB_VcomInit(void) -{ - usb_device_handle deviceHandle = NULL; - - USB_DeviceClockInit(); - -#if (defined(FSL_FEATURE_SOC_SYSMPU_COUNT) && (FSL_FEATURE_SOC_SYSMPU_COUNT > 0U)) - SYSMPU_Enable(SYSMPU, 0); -#endif /* FSL_FEATURE_SOC_SYSMPU_COUNT */ - - s_cdcVcom.speed = USB_SPEED_FULL; - s_cdcVcom.attach = 0; - s_cdcVcom.deviceHandle = NULL; - - if (kStatus_USB_Success != USB_DeviceInit(CONTROLLER_ID, USB_DeviceCallback, &s_cdcVcom.deviceHandle)) - { - deviceHandle = NULL; - } - else - { - deviceHandle = s_cdcVcom.deviceHandle; - USB_DeviceIsrEnable(); - USB_DeviceRun(s_cdcVcom.deviceHandle); - } - return deviceHandle; -} - -/* See virtual_com.h for documentation of this function. */ -void USB_VcomDeinit(usb_device_handle deviceHandle) -{ - USB_DeviceStop(deviceHandle); - USB_DeviceDeinit(deviceHandle); - s_cdcVcom.deviceHandle = NULL; -#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0) - USB_EhciPhyDeinit(CONTROLLER_ID); -#endif -#if defined(USB_DEVICE_CONFIG_KHCI) && (USB_DEVICE_CONFIG_KHCI > 0) - CLOCK_DisableUsbfs0Clock(); -#endif -#if defined(USB_DEVICE_CONFIG_LPCIP3511FS) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U) - /* enable USB IP clock, user code. */ - CLOCK_DisableClock(kCLOCK_Usbd0); -#endif /* USB_DEVICE_CONFIG_LPCIP3511FS */ - -#if defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U) -/* enable USB IP clock,user code. */ -#endif /* USB_DEVICE_CONFIG_LPCIP3511HS */ -} diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/virtual_com.h b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/virtual_com.h deleted file mode 100644 index 37ea3051f8b..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/utilities/virtual_com.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _USB_CDC_VCOM_H_ -#define _USB_CDC_VCOM_H_ 1 - -#include "usb_device_descriptor.h" -#include "fsl_common.h" - -/******************************************************************************* -* Definitions -******************************************************************************/ -#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0) -#define CONTROLLER_ID kUSB_ControllerEhci0 -#define DATA_BUFF_SIZE HS_CDC_VCOM_BULK_OUT_PACKET_SIZE -#endif /* USB_DEVICE_CONFIG_EHCI */ - -#if defined(USB_DEVICE_CONFIG_KHCI) && (USB_DEVICE_CONFIG_KHCI > 0) -#define CONTROLLER_ID kUSB_ControllerKhci0 -#define DATA_BUFF_SIZE FS_CDC_VCOM_BULK_OUT_PACKET_SIZE -#endif /* USB_DEVICE_CONFIG_KHCI */ - -#if defined(USB_DEVICE_CONFIG_LPCIP3511FS) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U) -#define CONTROLLER_ID kUSB_ControllerLpcIp3511Fs0 -#define DATA_BUFF_SIZE FS_CDC_VCOM_BULK_OUT_PACKET_SIZE -#endif /* USB_DEVICE_CONFIG_LPCIP3511FS */ - -#if defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U) -#define CONTROLLER_ID kUSB_ControllerLpcIp3511Hs0 -#define DATA_BUFF_SIZE HS_CDC_VCOM_BULK_OUT_PACKET_SIZE -#endif /* USB_DEVICE_CONFIG_LPCIP3511HS */ - -#if defined(USB_DEVICE_CONFIG_LPCIP3511FS) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U) -#define CONTROLLER_ID kUSB_ControllerLpcIp3511Fs0 -#define DATA_BUFF_SIZE FS_CDC_VCOM_BULK_OUT_PACKET_SIZE - -#endif - -#if defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U) -#define CONTROLLER_ID kUSB_ControllerLpcIp3511Hs0 -#define DATA_BUFF_SIZE HS_CDC_VCOM_BULK_OUT_PACKET_SIZE -#endif - -#define USB_DEVICE_INTERRUPT_PRIORITY (3U) - -/* Currently configured line coding */ -#define LINE_CODING_SIZE (0x07) -#define LINE_CODING_DTERATE (115200) -#define LINE_CODING_CHARFORMAT (0x00) -#define LINE_CODING_PARITYTYPE (0x00) -#define LINE_CODING_DATABITS (0x08) - -/* Communications feature */ -#define COMM_FEATURE_DATA_SIZE (0x02) -#define STATUS_ABSTRACT_STATE (0x0000) -#define COUNTRY_SETTING (0x0000) - -/* Notification of serial state */ -#define NOTIF_PACKET_SIZE (0x08) -#define UART_BITMAP_SIZE (0x02) -#define NOTIF_REQUEST_TYPE (0xA1) - -/* Define the types for application */ -typedef struct _usb_cdc_vcom_struct -{ - usb_device_handle deviceHandle; /* USB device handle. */ - volatile uint8_t attach; /* A flag to indicate whether a usb device is attached. 1: attached, 0: not attached */ - uint8_t speed; /* Speed of USB device. USB_SPEED_FULL/USB_SPEED_LOW/USB_SPEED_HIGH. */ - volatile uint8_t - startTransactions; /* A flag to indicate whether a CDC device is ready to transmit and receive data. */ - uint8_t currentConfiguration; /* Current configuration value. */ - uint8_t currentInterfaceAlternateSetting - [USB_CDC_VCOM_INTERFACE_COUNT]; /* Current alternate setting value for each interface. */ -} usb_cdc_vcom_struct_t; - -/* Define the infomation relates to abstract control model */ -typedef struct _usb_cdc_acm_info -{ - uint8_t serialStateBuf[NOTIF_PACKET_SIZE + UART_BITMAP_SIZE]; /* Serial state buffer of the CDC device to notify the - serial state to host. */ - bool dtePresent; /* A flag to indicate whether DTE is present. */ - uint16_t breakDuration; /* Length of time in milliseconds of the break signal */ - uint8_t dteStatus; /* Status of data terminal equipment */ - uint8_t currentInterface; /* Current interface index. */ - uint16_t uartState; /* UART state of the CDC device. */ -} usb_cdc_acm_info_t; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Application initialization function. - * - * This function initializes the application. - * - * @return pointer to USB device handle. - */ -usb_device_handle USB_VcomInit(void); - -/*! - * @brief Application initialization function. - * - * This function initializes the application. - * - * @return pointer to USB device handle. - */ -void USB_VcomDeinit(usb_device_handle deviceHandle); - -/*! - * @brief USB recive data from host using a blocking method. - * - * This function recives data from host by usb cdc protocol - * @param baseAddr pointer to USB device handle. - * @param buf pointer to the data. - * @param count size of the transfer. - * - * @return A USB error code or kStatus_USB_Success. - */ -status_t USB_VcomReadBlocking(usb_device_handle baseAddr, uint8_t *buf, size_t count); - -/*! - * @brief USB recive 'count' number of data from host using a blocking method. - * - * This function recives data from host by usb cdc protocol - * @param baseAddr pointer to USB device handle. - * @param buf pointer to the data. - * @param count size of the transfer. - * - * @return A USB error code or kStatus_USB_Success. - */ -status_t USB_VcomReadPolling(usb_device_handle baseAddr, uint8_t *buf, size_t count); - -/*! - * @brief USB send data to host using a blocking method. - * - * This function sends data to host by usb cdc protocol - * @param baseAddr pointer to USB device handle. - * @param buf pointer to the data. - * @param count size of the transfer. - * - * @return None. - */ -void USB_VcomWriteBlocking(usb_device_handle baseAddr, const uint8_t *buf, size_t count); - -#endif /* _USB_CDC_VCOM_H_ */ diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/SConscript b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/SConscript deleted file mode 100644 index 4c815c49b83..00000000000 --- a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/SConscript +++ /dev/null @@ -1,15 +0,0 @@ -# RT-Thread building script for bridge - -import os -from building import * - -cwd = GetCurrentDir() -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/nxp/lpc/lpc54114-lite/README.md b/bsp/nxp/lpc/lpc54114-lite/README.md index 1b0652401bf..4b4e90e5e41 100644 --- a/bsp/nxp/lpc/lpc54114-lite/README.md +++ b/bsp/nxp/lpc/lpc54114-lite/README.md @@ -78,6 +78,14 @@ LPC54114-Lite å¼€å‘æ¿çš„更多详细信æ¯è¯·å‚è€ƒä¸‡åˆ©ç”µå­ [å¼€å‘æ¿ç”¨ #### 编译下载 +**请注æ„ï¼ï¼ï¼** + +在执行编译工作å‰è¯·å…ˆæ‰“å¼€ENV执行以下指令（该指令用于拉å–å¿…è¦çš„库，å¦åˆ™æ— æ³•é€šè¿‡ç¼–译）： + +```bash +pkgs --update +``` + åŒå‡» project.uvprojx 文件，打开 MDK5 工程，编译并下载程åºåˆ°å¼€å‘æ¿ã€‚ > 工程默认é…置使用 CMSIS-DAP 仿真器下载程åºï¼Œåœ¨é€šè¿‡ Micro USB 连接开å‘æ¿çš„基础上，点击下载按钮å³å¯ä¸‹è½½ç¨‹åºåˆ°å¼€å‘æ¿ diff --git a/bsp/nxp/lpc/lpc54114-lite/SConstruct b/bsp/nxp/lpc/lpc54114-lite/SConstruct index f3d28ea6832..3de873bd859 100644 --- a/bsp/nxp/lpc/lpc54114-lite/SConstruct +++ b/bsp/nxp/lpc/lpc54114-lite/SConstruct @@ -10,6 +10,23 @@ else: sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] from building import * +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "nxp-lpc-series-latest"), + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n==============================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("==============================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread-%s.%s' % (rtconfig.BOARD_NAME, rtconfig.TARGET_EXT) DefaultEnvironment(tools=[]) diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/Kconfig b/bsp/nxp/lpc/lpc54608-LPCXpresso/Kconfig index e8907a51dac..4bbd2ee026a 100644 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/Kconfig +++ b/bsp/nxp/lpc/lpc54608-LPCXpresso/Kconfig @@ -14,6 +14,7 @@ config SOC_LPC54608 select ARCH_ARM_CORTEX_M4 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select PKG_USING_NXP_LPC_DRIVER default y source "$(BSP_DIR)/drivers/Kconfig" diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/README.md b/bsp/nxp/lpc/lpc54608-LPCXpresso/README.md index f0428c94c8a..4910ebb9a45 100644 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/README.md +++ b/bsp/nxp/lpc/lpc54608-LPCXpresso/README.md @@ -24,6 +24,14 @@ LPCXpresso54608æ¿çº§åŒ…支æŒMDK4﹑MDK5﹑IARå¼€å‘环境和GCC编译器，以 | IAR | IAR 7.60~IAR8.20 | | GCC | GCC 5.4.1 20160919 (release) | +**请注æ„ï¼ï¼ï¼** + +在执行编译工作å‰è¯·å…ˆæ‰“å¼€ENV执行以下指令（该指令用于拉å–å¿…è¦çš„库，å¦åˆ™æ— æ³•é€šè¿‡ç¼–译）： + +```bash +pkgs --update +``` + ## 烧写åŠæ‰§è¡Œ 供电方å¼ï¼šä½¿ç”¨ Micro USB 连接电脑和æ¿å­ä¸Šçš„J8(Debug Link)。 diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SConstruct b/bsp/nxp/lpc/lpc54608-LPCXpresso/SConstruct index 6677545fbb2..11928e9483f 100644 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SConstruct +++ b/bsp/nxp/lpc/lpc54608-LPCXpresso/SConstruct @@ -10,6 +10,23 @@ else: sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] from building import * +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "nxp-lpc-series-latest"), + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n==============================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("==============================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread-%s.%s' % (rtconfig.BOARD_NAME, rtconfig.TARGET_EXT) DefaultEnvironment(tools=[]) if rtconfig.PLATFORM == 'armcc': diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_ETH_MAC.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_ETH_MAC.c deleted file mode 100644 index 4fdb494379a..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_ETH_MAC.c +++ /dev/null @@ -1,210 +0,0 @@ -#include "Driver_ETH_MAC.h" - -#define ARM_ETH_MAC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */ - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_ETH_MAC_API_VERSION, - ARM_ETH_MAC_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_ETH_MAC_CAPABILITIES DriverCapabilities = { - 0, /* 1 = IPv4 header checksum verified on receive */ - 0, /* 1 = IPv6 checksum verification supported on receive */ - 0, /* 1 = UDP payload checksum verified on receive */ - 0, /* 1 = TCP payload checksum verified on receive */ - 0, /* 1 = ICMP payload checksum verified on receive */ - 0, /* 1 = IPv4 header checksum generated on transmit */ - 0, /* 1 = IPv6 checksum generation supported on transmit */ - 0, /* 1 = UDP payload checksum generated on transmit */ - 0, /* 1 = TCP payload checksum generated on transmit */ - 0, /* 1 = ICMP payload checksum generated on transmit */ - 0, /* Ethernet Media Interface type */ - 0, /* 1 = driver provides initial valid MAC address */ - 0, /* 1 = callback event \ref ARM_ETH_MAC_EVENT_RX_FRAME generated */ - 0, /* 1 = callback event \ref ARM_ETH_MAC_EVENT_TX_FRAME generated */ - 0, /* 1 = wakeup event \ref ARM_ETH_MAC_EVENT_WAKEUP generated */ - 0 /* 1 = Precision Timer supported */ -}; - -// -// Functions -// - -ARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion(void) -{ -} - -ARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities(void) -{ -} - -int32_t ARM_ETH_MAC_Initialize(ARM_ETH_MAC_SignalEvent_t cb_event) -{ -} - -int32_t ARM_ETH_MAC_Uninitialize(void) -{ -} - -int32_t ARM_ETH_MAC_PowerControl(ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -int32_t ARM_ETH_MAC_GetMacAddress(ARM_ETH_MAC_ADDR *ptr_addr) -{ -} - -int32_t ARM_ETH_MAC_SetMacAddress(const ARM_ETH_MAC_ADDR *ptr_addr) -{ -} - -int32_t ARM_ETH_MAC_SetAddressFilter(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr) -{ -} - -int32_t ARM_ETH_MAC_SendFrame(const uint8_t *frame, uint32_t len, uint32_t flags) -{ -} - -int32_t ARM_ETH_MAC_ReadFrame(uint8_t *frame, uint32_t len) -{ -} - -uint32_t ARM_ETH_MAC_GetRxFrameSize(void) -{ -} - -int32_t ARM_ETH_MAC_GetRxFrameTime(ARM_ETH_MAC_TIME *time) -{ -} - -int32_t ARM_ETH_MAC_GetTxFrameTime(ARM_ETH_MAC_TIME *time) -{ -} - -int32_t ARM_ETH_MAC_Control(uint32_t control, uint32_t arg) -{ - switch (control) - { - case ARM_ETH_MAC_CONFIGURE: - - switch (arg & ARM_ETH_MAC_SPEED_Msk) - { - case ARM_ETH_MAC_SPEED_10M: - break; - case ARM_ETH_SPEED_100M: - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - switch (arg & ARM_ETH_MAC_DUPLEX_Msk) - { - case ARM_ETH_MAC_DUPLEX_FULL: - break; - } - - if (arg & ARM_ETH_MAC_LOOPBACK) - { - } - - if ((arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX) || - (arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX)) - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - if (!(arg & ARM_ETH_MAC_ADDRESS_BROADCAST)) - { - } - - if (arg & ARM_ETH_MAC_ADDRESS_MULTICAST) - { - } - - if (arg & ARM_ETH_MAC_ADDRESS_ALL) - { - } - - break; - - case ARM_ETH_MAC_CONTROL_TX: - break; - - case ARM_ETH_MAC_CONTROL_RX: - break; - - case ARM_ETH_MAC_FLUSH: - if (arg & ARM_ETH_MAC_FLUSH_RX) - { - } - if (arg & ARM_ETH_MAC_FLUSH_TX) - { - } - break; - - case ARM_ETH_MAC_SLEEP: - break; - - case ARM_ETH_MAC_VLAN_FILTER: - break; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -int32_t ARM_ETH_MAC_ControlTimer(uint32_t control, ARM_ETH_MAC_TIME *time) -{ -} - -int32_t ARM_ETH_MAC_PHY_Read(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) -{ -} - -int32_t ARM_ETH_MAC_PHY_Write(uint8_t phy_addr, uint8_t reg_addr, uint16_t data) -{ -} - -void ARM_ETH_MAC_SignalEvent(uint32_t event) -{ -} - -// End ETH MAC Interface - -ARM_DRIVER_ETH_MAC Driver_ETH_MAC = -{ - ARM_ETH_MAC_GetVersion, - ARM_ETH_MAC_GetCapabilities, - ARM_ETH_MAC_Initialize, - ARM_ETH_MAC_Uninitialize, - ARM_ETH_MAC_PowerControl, - ARM_ETH_MAC_GetMacAddress, - ARM_ETH_MAC_SetMacAddress, - ARM_ETH_MAC_SetAddressFilter, - ARM_ETH_MAC_SendFrame, - ARM_ETH_MAC_ReadFrame, - ARM_ETH_MAC_GetRxFrameSize, - ARM_ETH_MAC_GetRxFrameTime, - ARM_ETH_MAC_GetTxFrameTime, - ARM_ETH_MAC_ControlTimer, - ARM_ETH_MAC_Control, - ARM_ETH_MAC_PHY_Read, - ARM_ETH_MAC_PHY_Write -}; diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_ETH_PHY.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_ETH_PHY.c deleted file mode 100644 index 01a633f170a..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_ETH_PHY.c +++ /dev/null @@ -1,109 +0,0 @@ -#include "Driver_ETH_PHY.h" - -#define ARM_ETH_PHY_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */ - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_ETH_PHY_API_VERSION, - ARM_ETH_PHY_DRV_VERSION -}; - -// -// Functions -// - -ARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion(void) -{ -} - -int32_t ARM_ETH_PHY_Initialize(ARM_ETH_PHY_Read_t fn_read, ARM_ETH_PHY_Write_t fn_write) -{ -} - -int32_t ARM_ETH_PHY_Uninitialize(void) -{ -} - -int32_t ARM_ETH_PHY_PowerControl(ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -int32_t ARM_ETH_PHY_SetInterface(uint32_t interface) -{ - switch (interface) - { - case ARM_ETH_INTERFACE_MII: - break; - case ARM_ETH_INTERFACE_RMII: - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -int32_t ARM_ETH_PHY_SetMode(uint32_t mode) -{ - switch (mode & ARM_ETH_PHY_SPEED_Msk) - { - case ARM_ETH_PHY_SPEED_10M: - break; - case ARM_ETH_PHY_SPEED_100M: - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - switch (mode & ARM_ETH_PHY_DUPLEX_Msk) - { - case ARM_ETH_PHY_DUPLEX_HALF: - break; - case ARM_ETH_PHY_DUPLEX_FULL: - break; - } - - if (mode & ARM_ETH_PHY_AUTO_NEGOTIATE) - { - } - - if (mode & ARM_ETH_PHY_LOOPBACK) - { - } - - if (mode & ARM_ETH_PHY_ISOLATE) - { - } -} - -ARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState(void) -{ -} - -ARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo(void) -{ -} - -ARM_DRIVER_ETH_PHY ARM_Driver_ETH_PHY_(ETH_PHY_NUM) = -{ - ARM_ETH_PHY_GetVersion, - ARM_ETH_PHY_Initialize, - ARM_ETH_PHY_Uninitialize, - ARM_ETH_PHY_PowerControl, - ARM_ETH_PHY_SetInterface, - ARM_ETH_PHY_SetMode, - ARM_ETH_PHY_GetLinkState, - ARM_ETH_PHY_GetLinkInfo, -}; diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_Flash.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_Flash.c deleted file mode 100644 index e1483543e32..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_Flash.c +++ /dev/null @@ -1,104 +0,0 @@ -#include "Driver_Flash.h" - -#define ARM_FLASH_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */ - -/* Sector Information */ -#ifdef FLASH_SECTORS -static ARM_FLASH_SECTOR FLASH_SECTOR_INFO[FLASH_SECTOR_COUNT] = { - FLASH_SECTORS -}; -#else -#define FLASH_SECTOR_INFO NULL -#endif - -/* Flash Information */ -static ARM_FLASH_INFO FlashInfo = { - 0, /* FLASH_SECTOR_INFO */ - 0, /* FLASH_SECTOR_COUNT */ - 0, /* FLASH_SECTOR_SIZE */ - 0, /* FLASH_PAGE_SIZE */ - 0, /* FLASH_PROGRAM_UNIT */ - 0 /* FLASH_ERASED_VALUE */ -}; - -/* Flash Status */ -static ARM_FLASH_STATUS FlashStatus; - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_FLASH_API_VERSION, - ARM_FLASH_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_FLASH_CAPABILITIES DriverCapabilities = { - 0, /* event_ready */ - 0, /* data_width = 0:8-bit, 1:16-bit, 2:32-bit */ - 0 /* erase_chip */ -}; - -// -// Functions -// - -ARM_DRIVER_VERSION ARM_Flash_GetVersion(void) -{ -} - -ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities(void) -{ -} - -int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event) -{ -} - -int32_t ARM_Flash_Uninitialize(void) -{ -} - -int32_t ARM_Flash_PowerControl(ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -int32_t ARM_Flash_ReadData(uint32_t addr, void *data, uint32_t cnt) -{ -} - -int32_t ARM_Flash_ProgramData(uint32_t addr, const void *data, uint32_t cnt) -{ -} - -int32_t ARM_Flash_EraseSector(uint32_t addr) -{ -} - -int32_t ARM_Flash_EraseChip(void) -{ -} - -ARM_FLASH_STATUS ARM_Flash_GetStatus(void) -{ -} - -ARM_FLASH_INFO * ARM_Flash_GetInfo(void) -{ -} - -void ARM_Flash_SignalEvent(uint32_t event) -{ -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_I2C.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_I2C.c deleted file mode 100644 index 3fb830f86fa..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_I2C.c +++ /dev/null @@ -1,130 +0,0 @@ -#include "Driver_I2C.h" - -#define ARM_I2C_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */ - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_I2C_API_VERSION, - ARM_I2C_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_I2C_CAPABILITIES DriverCapabilities = { - 0 /* supports 10-bit addressing */ -}; - -// -// Functions -// - -ARM_DRIVER_VERSION ARM_I2C_GetVersion(void) -{ -} - -ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities(void) -{ -} - -int32_t ARM_I2C_Initialize(ARM_I2C_SignalEvent_t cb_event) -{ -} - -int32_t ARM_I2C_Uninitialize(void) -{ -} - -int32_t ARM_I2C_PowerControl(ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -int32_t ARM_I2C_MasterTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ -} - -int32_t ARM_I2C_MasterReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ -} - -int32_t ARM_I2C_SlaveTransmit(const uint8_t *data, uint32_t num) -{ -} - -int32_t ARM_I2C_SlaveReceive(uint8_t *data, uint32_t num) -{ -} - -int32_t ARM_I2C_GetDataCount(void) -{ -} - -int32_t ARM_I2C_Control(uint32_t control, uint32_t arg) -{ - switch (control) - { - case ARM_I2C_OWN_ADDRESS: - break; - - case ARM_I2C_BUS_SPEED: - switch (arg) - { - case ARM_I2C_BUS_SPEED_STANDARD: - break; - case ARM_I2C_BUS_SPEED_FAST: - break; - case ARM_I2C_BUS_SPEED_FAST_PLUS: - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - break; - - case ARM_I2C_BUS_CLEAR: - break; - - case ARM_I2C_ABORT_TRANSFER: - break; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -ARM_I2C_STATUS ARM_I2C_GetStatus(void) -{ -} - -void ARM_I2C_SignalEvent(uint32_t event) -{ - // function body -} - -// End I2C Interface - -ARM_DRIVER_I2C Driver_I2C = { - ARM_I2C_GetVersion, - ARM_I2C_GetCapabilities, - ARM_I2C_Initialize, - ARM_I2C_Uninitialize, - ARM_I2C_PowerControl, - ARM_I2C_MasterTransmit, - ARM_I2C_MasterReceive, - ARM_I2C_SlaveTransmit, - ARM_I2C_SlaveReceive, - ARM_I2C_GetDataCount, - ARM_I2C_Control, - ARM_I2C_GetStatus -}; diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_MCI.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_MCI.c deleted file mode 100644 index edd6d9eb9ac..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_MCI.c +++ /dev/null @@ -1,201 +0,0 @@ -#include "Driver_MCI.h" - -#define ARM_MCI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */ - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_MCI_API_VERSION, - ARM_MCI_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_MCI_CAPABILITIES DriverCapabilities = { - 0, /* cd_state */ - 0, /* cd_event */ - 0, /* vdd */ - 0, /* vdd_1v8 */ - 0, /* vccq */ - 0, /* vccq_1v8 */ - 0, /* vccq_1v2 */ - 1, /* data_width_4 */ - 1, /* data_width_8 */ - 0, /* data_width_4_ddr */ - 0, /* data_width_8_ddr */ - 0, /* high_speed */ - 0, /* uhs_signaling */ - 0, /* uhs_tuning */ - 0, /* uhs_sdr50 */ - 0, /* uhs_sdr104 */ - 0, /* uhs_ddr50 */ - 0, /* uhs_driver_type_a */ - 0, /* uhs_driver_type_c */ - 0, /* uhs_driver_type_d */ - 1, /* sdio_interrupt */ - 1, /* read_wait */ - 0, /* suspend_resume */ - 0, /* mmc_interrupt */ - 0, /* mmc_boot */ - 0, /* ccs */ - 0 /* ccs_timeout */ -}; - -// -// Functions -// - -ARM_DRIVER_VERSION ARM_MCI_GetVersion(void) -{ -} - -ARM_MCI_CAPABILITIES ARM_MCI_GetCapabilities(void) -{ -} - -int32_t ARM_MCI_Initialize(ARM_MCI_SignalEvent_t cb_event) -{ -} - -int32_t ARM_MCI_Uninitialize(void) -{ -} - -int32_t ARM_MCI_PowerControl(ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -int32_t ARM_MCI_CardPower(uint32_t voltage) -{ - switch (voltage & ARM_MCI_POWER_VDD_Msk) - { - case ARM_MCI_POWER_VDD_OFF: - return ARM_DRIVER_OK; - - case ARM_MCI_POWER_VDD_3V3: - return ARM_DRIVER_OK; - - default: - break; - } -} - -int32_t ARM_MCI_ReadCD(void) -{ -} - -int32_t ARM_MCI_ReadWP(void) -{ -} - -int32_t ARM_MCI_SendCommand(uint32_t cmd, uint32_t arg, uint32_t flags, uint32_t *response) -{ -} - -int32_t ARM_MCI_SetupTransfer(uint8_t *data, uint32_t block_count, uint32_t block_size, uint32_t mode) -{ -} - -int32_t ARM_MCI_AbortTransfer(void) -{ -} - -int32_t ARM_MCI_Control(uint32_t control, uint32_t arg) -{ - switch (control) - { - case ARM_MCI_BUS_SPEED: - break; - - case ARM_MCI_BUS_SPEED_MODE: - break; - - case ARM_MCI_BUS_CMD_MODE: - /* Implement external pull-up control to support MMC cards in open-drain mode */ - /* Default mode is push-pull and is configured in Driver_MCI0.Initialize() */ - if (arg == ARM_MCI_BUS_CMD_PUSH_PULL) - { - /* Configure external circuit to work in push-pull mode */ - } - else if (arg == ARM_MCI_BUS_CMD_OPEN_DRAIN) - { - /* Configure external circuit to work in open-drain mode */ - } - else - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - break; - - case ARM_MCI_BUS_DATA_WIDTH: - switch (arg) - { - case ARM_MCI_BUS_DATA_WIDTH_1: - break; - case ARM_MCI_BUS_DATA_WIDTH_4: - break; - case ARM_MCI_BUS_DATA_WIDTH_8: - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - break; - - case ARM_MCI_CONTROL_RESET: - break; - - case ARM_MCI_CONTROL_CLOCK_IDLE: - break; - - case ARM_MCI_DATA_TIMEOUT: - break; - - case ARM_MCI_MONITOR_SDIO_INTERRUPT: - break; - - case ARM_MCI_CONTROL_READ_WAIT: - break; - - case ARM_MCI_DRIVER_STRENGTH: - default: return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -ARM_MCI_STATUS ARM_MCI_GetStatus(void) -{ -} - -void ARM_MCI_SignalEvent(uint32_t event) -{ - // function body -} - -// End MCI Interface - -ARM_DRIVER_MCI Driver_MCI = { - ARM_MCI_GetVersion, - ARM_MCI_GetCapabilities, - ARM_MCI_Initialize, - ARM_MCI_Uninitialize, - ARM_MCI_PowerControl, - ARM_MCI_CardPower, - ARM_MCI_ReadCD, - ARM_MCI_ReadWP, - ARM_MCI_SendCommand, - ARM_MCI_SetupTransfer, - ARM_MCI_AbortTransfer, - ARM_MCI_Control, - ARM_MCI_GetStatus -}; diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_SAI.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_SAI.c deleted file mode 100644 index f36c2c7d115..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_SAI.c +++ /dev/null @@ -1,107 +0,0 @@ -#include "Driver_SAI.h" - -#define ARM_SAI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */ - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_SAI_API_VERSION, - ARM_SAI_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_SAI_CAPABILITIES DriverCapabilities = { - 1, /* supports asynchronous Transmit/Receive */ - 0, /* supports synchronous Transmit/Receive */ - 0, /* supports user defined Protocol */ - 1, /* supports I2S Protocol */ - 0, /* supports MSB/LSB justified Protocol */ - 0, /* supports PCM short/long frame Protocol */ - 0, /* supports AC'97 Protocol */ - 0, /* supports Mono mode */ - 0, /* supports Companding */ - 0, /* supports MCLK (Master Clock) pin */ - 0 /* supports Frame error event: \ref ARM_SAI_EVENT_FRAME_ERROR */ -}; - -// -// Functions -// - -ARM_DRIVER_VERSION ARM_SAI_GetVersion (void) -{ -} - -ARM_SAI_CAPABILITIES ARM_SAI_GetCapabilities (void) -{ -} - -int32_t ARM_SAI_Initialize (ARM_SAI_SignalEvent_t cb_event) -{ -} - -int32_t ARM_SAI_Uninitialize (void) -{ -} - -int32_t ARM_SAI_PowerControl (ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -int32_t ARM_SAI_Send (const void *data, uint32_t num) -{ -} - -int32_t ARM_SAI_Receive (void *data, uint32_t num) -{ -} - -uint32_t ARM_SAI_GetTxCount (void) -{ -} - -uint32_t ARM_SAI_GetRxCount (void) -{ -} - -int32_t ARM_SAI_Control (uint32_t control, uint32_t arg1, uint32_t arg2) -{ -} - -ARM_SAI_STATUS ARM_SAI_GetStatus (void) -{ -} - -void ARM_SAI_SignalEvent(uint32_t event) -{ - // function body -} - -// End SAI Interface - -ARM_DRIVER_SAI Driver_SAI = { - ARM_SAI_GetVersion, - ARM_SAI_GetCapabilities, - ARM_SAI_Initialize, - ARM_SAI_Uninitialize, - ARM_SAI_PowerControl, - ARM_SAI_Send, - ARM_SAI_Receive, - ARM_SAI_GetTxCount, - ARM_SAI_GetRxCount, - ARM_SAI_Control, - ARM_SAI_GetStatus -}; diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_SPI.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_SPI.c deleted file mode 100644 index 108b5566661..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_SPI.c +++ /dev/null @@ -1,133 +0,0 @@ -#include "Driver_SPI.h" - -#define ARM_SPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */ - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_SPI_API_VERSION, - ARM_SPI_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_SPI_CAPABILITIES DriverCapabilities = { - 1, /* Simplex Mode (Master and Slave) */ - 1, /* TI Synchronous Serial Interface */ - 1, /* Microwire Interface */ - 0 /* Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT */ -}; - -// -// Functions -// - -ARM_DRIVER_VERSION ARM_SPI_GetVersion(void) -{ -} - -ARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities(void) -{ -} - -int32_t ARM_SPI_Initialize(ARM_SPI_SignalEvent_t cb_event) -{ -} - -int32_t ARM_SPI_Uninitialize(void) -{ -} - -int32_t ARM_SPI_PowerControl(ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -int32_t ARM_SPI_Send(const void *data, uint32_t num) -{ -} - -int32_t ARM_SPI_Receive(void *data, uint32_t num) -{ -} - -int32_t ARM_SPI_Transfer(const void *data_out, void *data_in, uint32_t num) -{ -} - -uint32_t ARM_SPI_GetDataCount(void) -{ -} - -int32_t ARM_SPI_Control(uint32_t control, uint32_t arg) -{ - switch (control & ARM_SPI_CONTROL_Msk) - { - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - case ARM_SPI_MODE_INACTIVE: // SPI Inactive - return ARM_DRIVER_OK; - - case ARM_SPI_MODE_MASTER: // SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps - break; - - case ARM_SPI_MODE_SLAVE: // SPI Slave (Output on MISO, Input on MOSI) - break; - - case ARM_SPI_MODE_MASTER_SIMPLEX: // SPI Master (Output/Input on MOSI); arg = Bus Speed in bps - case ARM_SPI_MODE_SLAVE_SIMPLEX: // SPI Slave (Output/Input on MISO) - return ARM_SPI_ERROR_MODE; - - case ARM_SPI_SET_BUS_SPEED: // Set Bus Speed in bps; arg = value - break; - - case ARM_SPI_GET_BUS_SPEED: // Get Bus Speed in bps - break; - - case ARM_SPI_SET_DEFAULT_TX_VALUE: // Set default Transmit value; arg = value - break; - - case ARM_SPI_CONTROL_SS: // Control Slave Select; arg = 0:inactive, 1:active - break; - - case ARM_SPI_ABORT_TRANSFER: // Abort current data transfer - break; - } -} - -ARM_SPI_STATUS ARM_SPI_GetStatus(void) -{ -} - -void ARM_SPI_SignalEvent(uint32_t event) -{ - // function body -} - -// End SPI Interface - -ARM_DRIVER_SPI Driver_SPI = { - ARM_SPI_GetVersion, - ARM_SPI_GetCapabilities, - ARM_SPI_Initialize, - ARM_SPI_Uninitialize, - ARM_SPI_PowerControl, - ARM_SPI_Send, - ARM_SPI_Receive, - ARM_SPI_Transfer, - ARM_SPI_GetDataCount, - ARM_SPI_Control, - ARM_SPI_GetStatus -}; diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_USART.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_USART.c deleted file mode 100644 index c81a904566b..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_USART.c +++ /dev/null @@ -1,132 +0,0 @@ -#include "Driver_USART.h" - -#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */ - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_USART_API_VERSION, - ARM_USART_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_USART_CAPABILITIES DriverCapabilities = { - 1, /* supports UART (Asynchronous) mode */ - 0, /* supports Synchronous Master mode */ - 0, /* supports Synchronous Slave mode */ - 0, /* supports UART Single-wire mode */ - 0, /* supports UART IrDA mode */ - 0, /* supports UART Smart Card mode */ - 0, /* Smart Card Clock generator available */ - 0, /* RTS Flow Control available */ - 0, /* CTS Flow Control available */ - 0, /* Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE */ - 0, /* Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT */ - 0, /* RTS Line: 0=not available, 1=available */ - 0, /* CTS Line: 0=not available, 1=available */ - 0, /* DTR Line: 0=not available, 1=available */ - 0, /* DSR Line: 0=not available, 1=available */ - 0, /* DCD Line: 0=not available, 1=available */ - 0, /* RI Line: 0=not available, 1=available */ - 0, /* Signal CTS change event: \ref ARM_USART_EVENT_CTS */ - 0, /* Signal DSR change event: \ref ARM_USART_EVENT_DSR */ - 0, /* Signal DCD change event: \ref ARM_USART_EVENT_DCD */ - 0 /* Signal RI change event: \ref ARM_USART_EVENT_RI */ -}; - -// -// Functions -// - -ARM_DRIVER_VERSION ARM_USART_GetVersion(void) -{ -} - -ARM_USART_CAPABILITIES ARM_USART_GetCapabilities(void) -{ -} - -int32_t ARM_USART_Initialize(ARM_USART_SignalEvent_t cb_event) -{ -} - -int32_t ARM_USART_Uninitialize(void) -{ -} - -int32_t ARM_USART_PowerControl(ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -int32_t ARM_USART_Send(const void *data, uint32_t num) -{ -} - -int32_t ARM_USART_Receive(void *data, uint32_t num) -{ -} - -int32_t ARM_USART_Transfer(const void *data_out, void *data_in, uint32_t num) -{ -} - -uint32_t ARM_USART_GetTxCount(void) -{ -} - -uint32_t ARM_USART_GetRxCount(void) -{ -} - -int32_t ARM_USART_Control(uint32_t control, uint32_t arg) -{ -} - -ARM_USART_STATUS ARM_USART_GetStatus(void) -{ -} - -int32_t ARM_USART_SetModemControl(ARM_USART_MODEM_CONTROL control) -{ -} - -ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus(void) -{ -} - -void ARM_USART_SignalEvent(uint32_t event) -{ - // function body -} - -// End USART Interface - -ARM_DRIVER_USART Driver_USART = { - ARM_USART_GetVersion, - ARM_USART_GetCapabilities, - ARM_USART_Initialize, - ARM_USART_Uninitialize, - ARM_USART_PowerControl, - ARM_USART_Send, - ARM_USART_Receive, - ARM_USART_Transfer, - ARM_USART_GetTxCount, - ARM_USART_GetRxCount, - ARM_USART_Control, - ARM_USART_GetStatus, - ARM_USART_SetModemControl, - ARM_USART_GetModemStatus -}; diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_USBD.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_USBD.c deleted file mode 100644 index bcb0062c663..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_USBD.c +++ /dev/null @@ -1,142 +0,0 @@ -#include "Driver_USBD.h" - -#define ARM_USBD_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */ - -/* Driver Version */ -static const ARM_DRIVER_VERSION usbd_driver_version = { - ARM_USBD_API_VERSION, - ARM_USBD_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_USBD_CAPABILITIES usbd_driver_capabilities = { - 0, /* vbus_detection */ - 0, /* event_vbus_on */ - 0 /* event_vbus_off */ -}; - -// -// Functions -// - -ARM_DRIVER_VERSION ARM_USBD_GetVersion(void) -{ -} - -ARM_USBD_CAPABILITIES ARM_USBD_GetCapabilities(void) -{ -} - -int32_t ARM_USBD_Initialize(ARM_USBD_SignalDeviceEvent_t cb_device_event, - ARM_USBD_SignalEndpointEvent_t cb_endpoint_event) -{ -} - -int32_t ARM_USBD_Uninitialize(void) -{ -} - -int32_t ARM_USBD_PowerControl(ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -int32_t ARM_USBD_DeviceConnect(void) -{ -} - -int32_t ARM_USBD_DeviceDisconnect(void) -{ -} - -ARM_USBD_STATE ARM_USBD_DeviceGetState(void) -{ -} - -int32_t ARM_USBD_DeviceRemoteWakeup(void) -{ -} - -int32_t ARM_USBD_DeviceSetAddress(uint8_t dev_addr) -{ -} - -int32_t ARM_USBD_ReadSetupPacket(uint8_t *setup) -{ -} - -int32_t ARM_USBD_EndpointConfigure(uint8_t ep_addr, - uint8_t ep_type, - uint16_t ep_max_packet_size) -{ -} - -int32_t ARM_USBD_EndpointUnconfigure(uint8_t ep_addr) -{ -} - -int32_t ARM_USBD_EndpointStall(uint8_t ep_addr, bool stall) -{ -} - -int32_t ARM_USBD_EndpointTransfer(uint8_t ep_addr, uint8_t *data, uint32_t num) -{ -} - -uint32_t ARM_USBD_EndpointTransferGetResult(uint8_t ep_addr) -{ -} - -int32_t ARM_USBD_EndpointTransferAbort(uint8_t ep_addr) -{ -} - -uint16_t ARM_USBD_GetFrameNumber(void) -{ -} - -void ARM_USBD_SignalDeviceEvent(uint32_t event) -{ - // function body -} - -void ARM_USBD_SignalEndpointEvent(uint8_t ep_addr, uint32_t ep_event) -{ - // function body -} - -// End USBD Interface - -ARM_DRIVER_USBD Driver_USBD = -{ - ARM_USBD_GetVersion, - ARM_USBD_GetCapabilities, - ARM_USBD_Initialize, - ARM_USBD_Uninitialize, - ARM_USBD_PowerControl, - ARM_USBD_DeviceConnect, - ARM_USBD_DeviceDisconnect, - ARM_USBD_DeviceGetState, - ARM_USBD_DeviceRemoteWakeup, - ARM_USBD_DeviceSetAddress, - ARM_USBD_EndpointConfigure, - ARM_USBD_EndpointUnconfigure, - ARM_USBD_EndpointStall, - ARM_USBD_EndpointTransfer, - ARM_USBD_EndpointTransferGetResult, - ARM_USBD_EndpointTransferAbort, - ARM_USBD_GetFrameNumber -}; diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_USBH.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_USBH.c deleted file mode 100644 index 36e6fd035d6..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/DriverTemplates/Driver_USBH.c +++ /dev/null @@ -1,209 +0,0 @@ -#include "Driver_USBH.h" - -/* USB Host Driver */ - -#define ARM_USBH_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */ - -/* Driver Version */ -static const ARM_DRIVER_VERSION usbh_driver_version = { - ARM_USBH_API_VERSION, - ARM_USBH_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_USBD_CAPABILITIES usbd_driver_capabilities = { - 0x0001, /* Root HUB available Ports Mask */ - 0, /* Automatic SPLIT packet handling */ - 0, /* Signal Connect event */ - 0, /* Signal Disconnect event */ - 0 /* Signal Overcurrent event */ -}; - -// -// Functions -// - -ARM_DRIVER_VERSION ARM_USBH_GetVersion(void) -{ -} - -ARM_USBH_CAPABILITIES ARM_USBH_GetCapabilities(void) -{ -} - -int32_t ARM_USBH_Initialize(ARM_USBH_SignalPortEvent_t cb_port_event, - ARM_USBH_SignalEndpointEvent_t cb_endpoint_event) -{ -} - -int32_t ARM_USBH_Uninitialize(void) -{ -} - -int32_t ARM_USBH_PowerControl(ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -int32_t ARM_USBH_PortVbusOnOff(uint8_t port, bool vbus) -{ -} - -int32_t ARM_USBH_PortReset(uint8_t port) -{ -} - -int32_t ARM_USBH_PortSuspend(uint8_t port) -{ -} - -int32_t ARM_USBH_PortResume(uint8_t port) -{ -} - -ARM_USBH_PORT_STATE ARM_USBH_PortGetState(uint8_t port) -{ -} - -ARM_USBH_EP_HANDLE ARM_USBH_EndpointCreate(uint8_t dev_addr, - uint8_t dev_speed, - uint8_t hub_addr, - uint8_t hub_port, - uint8_t ep_addr, - uint8_t ep_type, - uint16_t ep_max_packet_size, - uint8_t ep_interval) -{ -} - -int32_t ARM_USBH_EndpointModify(ARM_USBH_EP_HANDLE ep_hndl, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t hub_addr, - uint8_t hub_port, - uint16_t ep_max_packet_size) -{ -} - -int32_t ARM_USBH_EndpointDelete(ARM_USBH_EP_HANDLE ep_hndl) -{ -} - -int32_t ARM_USBH_EndpointReset(ARM_USBH_EP_HANDLE ep_hndl) -{ -} - -int32_t ARM_USBH_EndpointTransfer(ARM_USBH_EP_HANDLE ep_hndl, - uint32_t packet, - uint8_t *data, - uint32_t num) -{ -} - -uint32_t ARM_USBH_EndpointTransferGetResult(ARM_USBH_EP_HANDLE ep_hndl) -{ -} - -int32_t ARM_USBH_EndpointTransferAbort(ARM_USBH_EP_HANDLE ep_hndl) -{ -} - -uint16_t ARM_USBH_GetFrameNumber(void) -{ -} - -void ARM_USBH_SignalPortEvent(uint8_t port, uint32_t event) -{ - // function body -} - -void ARM_USBH_SignalEndpointEvent(ARM_USBH_EP_HANDLE ep_hndl, uint32_t event) -{ - // function body -} - -/* USB Host HCI (OHCI/EHCI) Driver */ - -#define ARM_USBH_HCI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */ - -/* Driver Version */ -static const ARM_DRIVER_VERSION usbh_hci_driver_version = { - ARM_USBH_HCI_API_VERSION, - ARM_USBH_HCI_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_USBD_CAPABILITIES usbh_hci_driver_capabilities = { - 0x0001 /* Root HUB available Ports Mask */ -}; - -// -// Functions -// - -ARM_DRIVER_VERSION ARM_USBH_HCI_GetVersion(void) -{ -} - -ARM_USBH_HCI_CAPABILITIES ARM_USBH_HCI_GetCapabilities(void) -{ -} - -int32_t ARM_USBH_HCI_Initialize(ARM_USBH_HCI_Interrupt_t *cb_interrupt) -{ -} - -int32_t ARM_USBH_HCI_Uninitialize(void) -{ -} - -int32_t ARM_USBH_HCI_PowerControl(ARM_POWER_STATE state) -{ - switch (state) - { - case ARM_POWER_OFF: - break; - - case ARM_POWER_LOW: - break; - - case ARM_POWER_FULL: - break; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -int32_t ARM_USBH_HCI_PortVbusOnOff(uint8_t port, bool vbus) -{ -} - -void ARM_USBH_HCI_Interrupt(void) -{ - // function body -} - -// End USBH Interface - -ARM_DRIVER_USBH_HCI Driver_USBH_HCI = { - ARM_USBH_HCI_GetVersion, - ARM_USBH_HCI_GetCapabilities, - ARM_USBH_HCI_Initialize, - ARM_USBH_HCI_Uninitialize, - ARM_USBH_HCI_PowerControl, - ARM_USBH_HCI_PortVbusOnOff -}; diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_CAN.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_CAN.h deleted file mode 100644 index 2c22219adce..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_CAN.h +++ /dev/null @@ -1,361 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2015 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * - * $Date: 9. September 2015 - * $Revision: V1.00 - * - * Project: CAN (Controller Area Network) Driver definitions - * -------------------------------------------------------------------------- */ - -/* History: - * Version 1.00 - * Initial release - */ - -#ifndef __DRIVER_CAN_H -#define __DRIVER_CAN_H - -#include "Driver_Common.h" - -#define ARM_CAN_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0)/* API version */ - - -/****** CAN Bitrate selection codes *****/ -typedef enum _ARM_CAN_BITRATE_SELECT { - ARM_CAN_BITRATE_NOMINAL, ///< Select nominal (flexible data-rate arbitration) bitrate - ARM_CAN_BITRATE_FD_DATA ///< Select flexible data-rate data bitrate -} ARM_CAN_BITRATE_SELECT; - -/****** CAN Bit Propagation Segment codes (PROP_SEG) *****/ -#define ARM_CAN_BIT_PROP_SEG_Pos 0UL ///< bits 7..0 -#define ARM_CAN_BIT_PROP_SEG_Msk (0xFFUL << ARM_CAN_BIT_PROP_SEG_Pos) -#define ARM_CAN_BIT_PROP_SEG(x) (((x) << ARM_CAN_BIT_PROP_SEG_Pos) & ARM_CAN_BIT_PROP_SEG_Msk) - -/****** CAN Bit Phase Buffer Segment 1 (PHASE_SEG1) codes *****/ -#define ARM_CAN_BIT_PHASE_SEG1_Pos 8UL ///< bits 15..8 -#define ARM_CAN_BIT_PHASE_SEG1_Msk (0xFFUL << ARM_CAN_BIT_PHASE_SEG1_Pos) -#define ARM_CAN_BIT_PHASE_SEG1(x) (((x) << ARM_CAN_BIT_PHASE_SEG1_Pos) & ARM_CAN_BIT_PHASE_SEG1_Msk) - -/****** CAN Bit Phase Buffer Segment 2 (PHASE_SEG2) codes *****/ -#define ARM_CAN_BIT_PHASE_SEG2_Pos 16UL ///< bits 23..16 -#define ARM_CAN_BIT_PHASE_SEG2_Msk (0xFFUL << ARM_CAN_BIT_PHASE_SEG2_Pos) -#define ARM_CAN_BIT_PHASE_SEG2(x) (((x) << ARM_CAN_BIT_PHASE_SEG2_Pos) & ARM_CAN_BIT_PHASE_SEG2_Msk) - -/****** CAN Bit (Re)Synchronization Jump Width Segment (SJW) *****/ -#define ARM_CAN_BIT_SJW_Pos 24UL ///< bits 28..24 -#define ARM_CAN_BIT_SJW_Msk (0x1FUL << ARM_CAN_BIT_SJW_Pos) -#define ARM_CAN_BIT_SJW(x) (((x) << ARM_CAN_BIT_SJW_Pos) & ARM_CAN_BIT_SJW_Msk) - -/****** CAN Mode codes *****/ -typedef enum _ARM_CAN_MODE { - ARM_CAN_MODE_INITIALIZATION, ///< Initialization mode - ARM_CAN_MODE_NORMAL, ///< Normal operation mode - ARM_CAN_MODE_RESTRICTED, ///< Restricted operation mode - ARM_CAN_MODE_MONITOR, ///< Bus monitoring mode - ARM_CAN_MODE_LOOPBACK_INTERNAL, ///< Loopback internal mode - ARM_CAN_MODE_LOOPBACK_EXTERNAL ///< Loopback external mode -} ARM_CAN_MODE; - -/****** CAN Filter Operation codes *****/ -typedef enum _ARM_CAN_FILTER_OPERATION { - ARM_CAN_FILTER_ID_EXACT_ADD, ///< Add exact id filter - ARM_CAN_FILTER_ID_EXACT_REMOVE, ///< Remove exact id filter - ARM_CAN_FILTER_ID_RANGE_ADD, ///< Add range id filter - ARM_CAN_FILTER_ID_RANGE_REMOVE, ///< Remove range id filter - ARM_CAN_FILTER_ID_MASKABLE_ADD, ///< Add maskable id filter - ARM_CAN_FILTER_ID_MASKABLE_REMOVE ///< Remove maskable id filter -} ARM_CAN_FILTER_OPERATION; - -/****** CAN Object Configuration codes *****/ -typedef enum _ARM_CAN_OBJ_CONFIG { - ARM_CAN_OBJ_INACTIVE, ///< CAN object inactive - ARM_CAN_OBJ_TX, ///< CAN transmit object - ARM_CAN_OBJ_RX, ///< CAN receive object - ARM_CAN_OBJ_RX_RTR_TX_DATA, ///< CAN object that on RTR reception automatically transmits Data Frame - ARM_CAN_OBJ_TX_RTR_RX_DATA ///< CAN object that transmits RTR and automatically receives Data Frame -} ARM_CAN_OBJ_CONFIG; - -/** -\brief CAN Object Capabilities -*/ -typedef struct _ARM_CAN_OBJ_CAPABILITIES { - uint32_t tx : 1; ///< Object supports transmission - uint32_t rx : 1; ///< Object supports reception - uint32_t rx_rtr_tx_data : 1; ///< Object supports RTR reception and automatic Data Frame transmission - uint32_t tx_rtr_rx_data : 1; ///< Object supports RTR transmission and automatic Data Frame reception - uint32_t multiple_filters : 1; ///< Object allows assignment of multiple filters to it - uint32_t exact_filtering : 1; ///< Object supports exact identifier filtering - uint32_t range_filtering : 1; ///< Object supports range identifier filtering - uint32_t mask_filtering : 1; ///< Object supports mask identifier filtering - uint32_t message_depth : 8; ///< Number of messages buffers (FIFO) for that object -} ARM_CAN_OBJ_CAPABILITIES; - -/****** CAN Control Function Operation codes *****/ -#define ARM_CAN_CONTROL_Pos 0UL -#define ARM_CAN_CONTROL_Msk (0xFFUL << ARM_CAN_CONTROL_Pos) -#define ARM_CAN_SET_FD_MODE (1UL << ARM_CAN_CONTROL_Pos) ///< Set FD operation mode; arg: 0 = disable, 1 = enable -#define ARM_CAN_ABORT_MESSAGE_SEND (2UL << ARM_CAN_CONTROL_Pos) ///< Abort sending of CAN message; arg = object -#define ARM_CAN_CONTROL_RETRANSMISSION (3UL << ARM_CAN_CONTROL_Pos) ///< Enable/disable automatic retransmission; arg: 0 = disable, 1 = enable (default state) -#define ARM_CAN_SET_TRANSCEIVER_DELAY (4UL << ARM_CAN_CONTROL_Pos) ///< Set transceiver delay; arg = delay in time quanta - -/****** CAN ID Frame Format codes *****/ -#define ARM_CAN_ID_IDE_Pos 31UL -#define ARM_CAN_ID_IDE_Msk (1UL << ARM_CAN_ID_IDE_Pos) - -/****** CAN Identifier encoding *****/ -#define ARM_CAN_STANDARD_ID(id) (id & 0x000007FFUL) ///< CAN identifier in standard format (11-bits) -#define ARM_CAN_EXTENDED_ID(id) ((id & 0x1FFFFFFFUL) | ARM_CAN_ID_IDE_Msk)///< CAN identifier in extended format (29-bits) - -/** -\brief CAN Message Information -*/ -typedef struct _ARM_CAN_MSG_INFO { - uint32_t id; ///< CAN identifier with frame format specifier (bit 31) - uint32_t rtr : 1; ///< Remote transmission request frame - uint32_t edl : 1; ///< Flexible data-rate format extended data length - uint32_t brs : 1; ///< Flexible data-rate format with bitrate switch - uint32_t esi : 1; ///< Flexible data-rate format error state indicator - uint32_t dlc : 4; ///< Data length code -} ARM_CAN_MSG_INFO; - -/****** CAN specific error code *****/ -#define ARM_CAN_INVALID_BITRATE_SELECT (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Bitrate selection not supported -#define ARM_CAN_INVALID_BITRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Requested bitrate not supported -#define ARM_CAN_INVALID_BIT_PROP_SEG (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Propagation segment value not supported -#define ARM_CAN_INVALID_BIT_PHASE_SEG1 (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Phase segment 1 value not supported -#define ARM_CAN_INVALID_BIT_PHASE_SEG2 (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Phase segment 2 value not supported -#define ARM_CAN_INVALID_BIT_SJW (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< SJW value not supported -#define ARM_CAN_NO_MESSAGE_AVAILABLE (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Message is not available - -/****** CAN Status codes *****/ -#define ARM_CAN_UNIT_STATE_INACTIVE (0U) ///< Unit state: Not active on bus (initialize or error bus off) -#define ARM_CAN_UNIT_STATE_ACTIVE (1U) ///< Unit state: Active on bus (can generate active error frame) -#define ARM_CAN_UNIT_STATE_PASSIVE (2U) ///< Unit state: Error passive (can not generate active error frame) -#define ARM_CAN_LEC_NO_ERROR (0U) ///< Last error code: No error -#define ARM_CAN_LEC_BIT_ERROR (1U) ///< Last error code: Bit error -#define ARM_CAN_LEC_STUFF_ERROR (2U) ///< Last error code: Bit stuffing error -#define ARM_CAN_LEC_CRC_ERROR (3U) ///< Last error code: CRC error -#define ARM_CAN_LEC_FORM_ERROR (4U) ///< Last error code: Illegal fixed-form bit -#define ARM_CAN_LEC_ACK_ERROR (5U) ///< Last error code: Acknowledgement error - -/** -\brief CAN Status -*/ -typedef struct _ARM_CAN_STATUS { - uint32_t unit_state : 4; ///< Unit bus state - uint32_t last_error_code : 4; ///< Last error code - uint32_t tx_error_count : 8; ///< Transmitter error count - uint32_t rx_error_count : 8; ///< Receiver error count -} ARM_CAN_STATUS; - - -/****** CAN Unit Event *****/ -#define ARM_CAN_EVENT_UNIT_ACTIVE (1U) ///< Unit entered Error Active state -#define ARM_CAN_EVENT_UNIT_WARNING (2U) ///< Unit entered Error Warning state (one or both error counters >= 96) -#define ARM_CAN_EVENT_UNIT_PASSIVE (3U) ///< Unit entered Error Passive state -#define ARM_CAN_EVENT_UNIT_BUS_OFF (4U) ///< Unit entered bus off state - -/****** CAN Send/Receive Event *****/ -#define ARM_CAN_EVENT_SEND_COMPLETE (1UL << 0) ///< Send complete -#define ARM_CAN_EVENT_RECEIVE (1UL << 1) ///< Message received -#define ARM_CAN_EVENT_RECEIVE_OVERRUN (1UL << 2) ///< Received message overrun - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_CAN_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION - - \fn ARM_CAN_CAPABILITIES ARM_CAN_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_CAN_CAPABILITIES - - \fn int32_t ARM_CAN_Initialize (ARM_CAN_SignalUnitEvent_t cb_unit_event, - ARM_CAN_SignalObjectEvent_t cb_object_event) - \brief Initialize CAN interface and register signal (callback) functions. - \param[in] cb_unit_event Pointer to \ref ARM_CAN_SignalUnitEvent callback function - \param[in] cb_object_event Pointer to \ref ARM_CAN_SignalObjectEvent callback function - \return \ref execution_status - - \fn int32_t ARM_CAN_Uninitialize (void) - \brief De-initialize CAN interface. - \return \ref execution_status - - \fn int32_t ARM_CAN_PowerControl (ARM_POWER_STATE state) - \brief Control CAN interface power. - \param[in] state Power state - - \ref ARM_POWER_OFF : power off: no operation possible - - \ref ARM_POWER_LOW : low power mode: retain state, detect and signal wake-up events - - \ref ARM_POWER_FULL : power on: full operation at maximum performance - \return \ref execution_status - - \fn uint32_t ARM_CAN_GetClock (void) - \brief Retrieve CAN base clock frequency. - \return base clock frequency - - \fn int32_t ARM_CAN_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments) - \brief Set bitrate for CAN interface. - \param[in] select Bitrate selection - - \ref ARM_CAN_BITRATE_NOMINAL : nominal (flexible data-rate arbitration) bitrate - - \ref ARM_CAN_BITRATE_FD_DATA : flexible data-rate data bitrate - \param[in] bitrate Bitrate - \param[in] bit_segments Segment time quanta for signal sampling - \return \ref execution_status - - \fn int32_t ARM_CAN_SetMode (ARM_CAN_MODE mode) - \brief Set operating mode for CAN interface. - \param[in] mode Operating mode - - \ref ARM_CAN_MODE_INITIALIZATION : initialization mode - - \ref ARM_CAN_MODE_NORMAL : normal operation mode - - \ref ARM_CAN_MODE_RESTRICTED : restricted operation mode - - \ref ARM_CAN_MODE_MONITOR : bus monitoring mode - - \ref ARM_CAN_MODE_LOOPBACK_INTERNAL : loopback internal mode - - \ref ARM_CAN_MODE_LOOPBACK_EXTERNAL : loopback external mode - \return \ref execution_status - - \fn ARM_CAN_OBJ_CAPABILITIES ARM_CAN_ObjectGetCapabilities (uint32_t obj_idx) - \brief Retrieve capabilities of an object. - \param[in] obj_idx Object index - \return \ref ARM_CAN_OBJ_CAPABILITIES - - \fn int32_t ARM_CAN_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg) - \brief Add or remove filter for message reception. - \param[in] obj_idx Object index of object that filter should be or is assigned to - \param[in] operation Operation on filter - - \ref ARM_CAN_FILTER_ID_EXACT_ADD : add exact id filter - - \ref ARM_CAN_FILTER_ID_EXACT_REMOVE : remove exact id filter - - \ref ARM_CAN_FILTER_ID_RANGE_ADD : add range id filter - - \ref ARM_CAN_FILTER_ID_RANGE_REMOVE : remove range id filter - - \ref ARM_CAN_FILTER_ID_MASKABLE_ADD : add maskable id filter - - \ref ARM_CAN_FILTER_ID_MASKABLE_REMOVE : remove maskable id filter - \param[in] id ID or start of ID range (depending on filter type) - \param[in] arg Mask or end of ID range (depending on filter type) - \return \ref execution_status - - \fn int32_t ARM_CAN_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg) - \brief Configure object. - \param[in] obj_idx Object index - \param[in] obj_cfg Object configuration state - - \ref ARM_CAN_OBJ_INACTIVE : deactivate object - - \ref ARM_CAN_OBJ_RX : configure object for reception - - \ref ARM_CAN_OBJ_TX : configure object for transmission - - \ref ARM_CAN_OBJ_RX_RTR_TX_DATA : configure object that on RTR reception automatically transmits Data Frame - - \ref ARM_CAN_OBJ_TX_RTR_RX_DATA : configure object that transmits RTR and automatically receives Data Frame - \return \ref execution_status - - \fn int32_t ARM_CAN_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size) - \brief Send message on CAN bus. - \param[in] obj_idx Object index - \param[in] msg_info Pointer to CAN message information - \param[in] data Pointer to data buffer - \param[in] size Number of data bytes to send - \return value >= 0 number of data bytes accepted to send - \return value < 0 \ref execution_status - - \fn int32_t ARM_CAN_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size) - \brief Read message received on CAN bus. - \param[in] obj_idx Object index - \param[out] msg_info Pointer to read CAN message information - \param[out] data Pointer to data buffer for read data - \param[in] size Maximum number of data bytes to read - \return value >= 0 number of data bytes read - \return value < 0 \ref execution_status - - \fn int32_t ARM_CAN_Control (uint32_t control, uint32_t arg) - \brief Control CAN interface. - \param[in] control Operation - - \ref ARM_CAN_SET_FD_MODE : set FD operation mode - - \ref ARM_CAN_ABORT_MESSAGE_SEND : abort sending of CAN message - - \ref ARM_CAN_CONTROL_RETRANSMISSION : enable/disable automatic retransmission - - \ref ARM_CAN_SET_TRANSCEIVER_DELAY : set transceiver delay - \param[in] arg Argument of operation - \return \ref execution_status - - \fn ARM_CAN_STATUS ARM_CAN_GetStatus (void) - \brief Get CAN status. - \return CAN status \ref ARM_CAN_STATUS - - \fn void ARM_CAN_SignalUnitEvent (uint32_t event) - \brief Signal CAN unit event. - \param[in] event \ref CAN_unit_events - \return none - - \fn void ARM_CAN_SignalObjectEvent (uint32_t obj_idx, uint32_t event) - \brief Signal CAN object event. - \param[in] obj_idx Object index - \param[in] event \ref CAN_events - \return none -*/ - -typedef void (*ARM_CAN_SignalUnitEvent_t) (uint32_t event); ///< Pointer to \ref ARM_CAN_SignalUnitEvent : Signal CAN Unit Event. -typedef void (*ARM_CAN_SignalObjectEvent_t) (uint32_t obj_idx, uint32_t event); ///< Pointer to \ref ARM_CAN_SignalObjectEvent : Signal CAN Object Event. - - -/** -\brief CAN Device Driver Capabilities. -*/ -typedef struct _ARM_CAN_CAPABILITIES { - uint32_t num_objects : 8; ///< Number of \ref can_objects available - uint32_t reentrant_operation : 1; ///< Support for reentrant calls to \ref ARM_CAN_MessageSend, \ref ARM_CAN_MessageRead, \ref ARM_CAN_ObjectConfigure and abort message sending used by \ref ARM_CAN_Control - uint32_t fd_mode : 1; ///< Support for CAN with flexible data-rate mode (CAN_FD) (set by \ref ARM_CAN_Control) - uint32_t restricted_mode : 1; ///< Support for restricted operation mode (set by \ref ARM_CAN_SetMode) - uint32_t monitor_mode : 1; ///< Support for bus monitoring mode (set by \ref ARM_CAN_SetMode) - uint32_t internal_loopback : 1; ///< Support for internal loopback mode (set by \ref ARM_CAN_SetMode) - uint32_t external_loopback : 1; ///< Support for external loopback mode (set by \ref ARM_CAN_SetMode) -} ARM_CAN_CAPABILITIES; - - -/** -\brief Access structure of the CAN Driver. -*/ -typedef struct _ARM_DRIVER_CAN { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_CAN_GetVersion : Get driver version. - ARM_CAN_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_CAN_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_CAN_SignalUnitEvent_t cb_unit_event, - ARM_CAN_SignalObjectEvent_t cb_object_event); ///< Pointer to \ref ARM_CAN_Initialize : Initialize CAN interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_CAN_Uninitialize : De-initialize CAN interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_CAN_PowerControl : Control CAN interface power. - uint32_t (*GetClock) (void); ///< Pointer to \ref ARM_CAN_GetClock : Retrieve CAN base clock frequency. - int32_t (*SetBitrate) (ARM_CAN_BITRATE_SELECT select, - uint32_t bitrate, - uint32_t bit_segments); ///< Pointer to \ref ARM_CAN_SetBitrate : Set bitrate for CAN interface. - int32_t (*SetMode) (ARM_CAN_MODE mode); ///< Pointer to \ref ARM_CAN_SetMode : Set operating mode for CAN interface. - ARM_CAN_OBJ_CAPABILITIES (*ObjectGetCapabilities) (uint32_t obj_idx); ///< Pointer to \ref ARM_CAN_ObjectGetCapabilities : Retrieve capabilities of an object. - int32_t (*ObjectSetFilter) (uint32_t obj_idx, - ARM_CAN_FILTER_OPERATION operation, - uint32_t id, - uint32_t arg); ///< Pointer to \ref ARM_CAN_ObjectSetFilter : Add or remove filter for message reception. - int32_t (*ObjectConfigure) (uint32_t obj_idx, - ARM_CAN_OBJ_CONFIG obj_cfg); ///< Pointer to \ref ARM_CAN_ObjectConfigure : Configure object. - int32_t (*MessageSend) (uint32_t obj_idx, - ARM_CAN_MSG_INFO *msg_info, - const uint8_t *data, - uint8_t size); ///< Pointer to \ref ARM_CAN_MessageSend : Send message on CAN bus. - int32_t (*MessageRead) (uint32_t obj_idx, - ARM_CAN_MSG_INFO *msg_info, - uint8_t *data, - uint8_t size); ///< Pointer to \ref ARM_CAN_MessageRead : Read message received on CAN bus. - int32_t (*Control) (uint32_t control, - uint32_t arg); ///< Pointer to \ref ARM_CAN_Control : Control CAN interface. - ARM_CAN_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_CAN_GetStatus : Get CAN status. -} const ARM_DRIVER_CAN; - -#endif /* __DRIVER_CAN_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_Common.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_Common.h deleted file mode 100644 index b11a115c467..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_Common.h +++ /dev/null @@ -1,72 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2014 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * - * $Date: 2. Jan 2014 - * $Revision: V2.00 - * - * Project: Common Driver definitions - * -------------------------------------------------------------------------- */ - -/* History: - * Version 2.00 - * Changed prefix ARM_DRV -> ARM_DRIVER - * Added General return codes definitions - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.00 - * Initial release - */ - -#ifndef __DRIVER_COMMON_H -#define __DRIVER_COMMON_H - -#include -#include -#include - -#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor)) - -/** -\brief Driver Version -*/ -typedef struct _ARM_DRIVER_VERSION { - uint16_t api; ///< API version - uint16_t drv; ///< Driver version -} ARM_DRIVER_VERSION; - -/* General return codes */ -#define ARM_DRIVER_OK 0 ///< Operation succeeded -#define ARM_DRIVER_ERROR -1 ///< Unspecified error -#define ARM_DRIVER_ERROR_BUSY -2 ///< Driver is busy -#define ARM_DRIVER_ERROR_TIMEOUT -3 ///< Timeout occurred -#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported -#define ARM_DRIVER_ERROR_PARAMETER -5 ///< Parameter error -#define ARM_DRIVER_ERROR_SPECIFIC -6 ///< Start of driver specific errors - -/** -\brief General power states -*/ -typedef enum _ARM_POWER_STATE { - ARM_POWER_OFF, ///< Power off: no operation possible - ARM_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events - ARM_POWER_FULL ///< Power on: full operation at maximum performance -} ARM_POWER_STATE; - -#endif /* __DRIVER_COMMON_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_ETH.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_ETH.h deleted file mode 100644 index ca087b6f173..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_ETH.h +++ /dev/null @@ -1,85 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2014 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * - * $Date: 7. Mar 2014 - * $Revision: V2.00 - * - * Project: Ethernet PHY and MAC Driver common definitions - * -------------------------------------------------------------------------- */ - -/* History: - * Version 2.00 - * Removed ARM_ETH_STATUS enumerator - * Removed ARM_ETH_MODE enumerator - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.00 - * Initial release - */ - -#ifndef __DRIVER_ETH_H -#define __DRIVER_ETH_H - -#include "Driver_Common.h" - -/** -\brief Ethernet Media Interface type -*/ -#define ARM_ETH_INTERFACE_MII 0 ///< Media Independent Interface (MII) -#define ARM_ETH_INTERFACE_RMII 1 ///< Reduced Media Independent Interface (RMII) -#define ARM_ETH_INTERFACE_SMII 2 ///< Serial Media Independent Interface (SMII) - -/** -\brief Ethernet link speed -*/ -#define ARM_ETH_SPEED_10M 0 ///< 10 Mbps link speed -#define ARM_ETH_SPEED_100M 1 ///< 100 Mbps link speed -#define ARM_ETH_SPEED_1G 2 ///< 1 Gpbs link speed - -/** -\brief Ethernet duplex mode -*/ -#define ARM_ETH_DUPLEX_HALF 0 ///< Half duplex link -#define ARM_ETH_DUPLEX_FULL 1 ///< Full duplex link - -/** -\brief Ethernet link state -*/ -typedef enum _ARM_ETH_LINK_STATE { - ARM_ETH_LINK_DOWN, ///< Link is down - ARM_ETH_LINK_UP ///< Link is up -} ARM_ETH_LINK_STATE; - -/** -\brief Ethernet link information -*/ -typedef struct _ARM_ETH_LINK_INFO { - uint32_t speed : 2; ///< Link speed: 0= 10 MBit, 1= 100 MBit, 2= 1 GBit - uint32_t duplex : 1; ///< Duplex mode: 0= Half, 1= Full -} ARM_ETH_LINK_INFO; - -/** -\brief Ethernet MAC Address -*/ -typedef struct _ARM_ETH_MAC_ADDR { - uint8_t b[6]; ///< MAC Address (6 bytes), MSB first -} ARM_ETH_MAC_ADDR; - -#endif /* __DRIVER_ETH_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_ETH_MAC.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_ETH_MAC.h deleted file mode 100644 index e215f09571e..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_ETH_MAC.h +++ /dev/null @@ -1,301 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2014 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * - * $Date: 30. May 2014 - * $Revision: V2.01 - * - * Project: Ethernet MAC (Media Access Control) Driver definitions - * -------------------------------------------------------------------------- */ - -/* History: - * Version 2.01 - * Added ARM_ETH_MAC_SLEEP Control - * Version 2.00 - * Changed MAC Address handling: - * moved from ARM_ETH_MAC_Initialize - * to new functions ARM_ETH_MAC_GetMacAddress and ARM_ETH_MAC_SetMacAddress - * Replaced ARM_ETH_MAC_SetMulticastAddr function with ARM_ETH_MAC_SetAddressFilter - * Extended ARM_ETH_MAC_SendFrame function with flags - * Added ARM_ETH_MAC_Control function: - * more control options (Broadcast, Multicast, Checksum offload, VLAN, ...) - * replaces ARM_ETH_MAC_SetMode - * replaces ARM_ETH_MAC_EnableTx, ARM_ETH_MAC_EnableRx - * Added optional event on transmitted frame - * Added support for PTP (Precision Time Protocol) through new functions: - * ARM_ETH_MAC_ControlTimer - * ARM_ETH_MAC_GetRxFrameTime - * ARM_ETH_MAC_GetTxFrameTime - * Changed prefix ARM_DRV -> ARM_DRIVER - * Changed return values of some functions to int32_t - * Version 1.10 - * Name space prefix ARM_ added - * Version 1.01 - * Renamed capabilities items for checksum offload - * Version 1.00 - * Initial release - */ - -#ifndef __DRIVER_ETH_MAC_H -#define __DRIVER_ETH_MAC_H - -#include "Driver_ETH.h" - -#define ARM_ETH_MAC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,01) /* API version */ - - -#define _ARM_Driver_ETH_MAC_(n) Driver_ETH_MAC##n -#define ARM_Driver_ETH_MAC_(n) _ARM_Driver_ETH_MAC_(n) - - -/****** Ethernet MAC Control Codes *****/ - -#define ARM_ETH_MAC_CONFIGURE (0x01) ///< Configure MAC; arg = configuration -#define ARM_ETH_MAC_CONTROL_TX (0x02) ///< Transmitter; arg: 0=disabled (default), 1=enabled -#define ARM_ETH_MAC_CONTROL_RX (0x03) ///< Receiver; arg: 0=disabled (default), 1=enabled -#define ARM_ETH_MAC_FLUSH (0x04) ///< Flush buffer; arg = ARM_ETH_MAC_FLUSH_... -#define ARM_ETH_MAC_SLEEP (0x05) ///< Sleep mode; arg: 1=enter and wait for Magic packet, 0=exit -#define ARM_ETH_MAC_VLAN_FILTER (0x06) ///< VLAN Filter for received frames; arg15..0: VLAN Tag; arg16: optional ARM_ETH_MAC_VLAN_FILTER_ID_ONLY; 0=disabled (default) - -/*----- Ethernet MAC Configuration -----*/ -#define ARM_ETH_MAC_SPEED_Pos 0 -#define ARM_ETH_MAC_SPEED_Msk (3UL << ARM_ETH_MAC_SPEED_Pos) -#define ARM_ETH_MAC_SPEED_10M (ARM_ETH_SPEED_10M << ARM_ETH_MAC_SPEED_Pos) ///< 10 Mbps link speed -#define ARM_ETH_MAC_SPEED_100M (ARM_ETH_SPEED_100M << ARM_ETH_MAC_SPEED_Pos) ///< 100 Mbps link speed -#define ARM_ETH_MAC_SPEED_1G (ARM_ETH_SPEED_1G << ARM_ETH_MAC_SPEED_Pos) ///< 1 Gpbs link speed -#define ARM_ETH_MAC_DUPLEX_Pos 2 -#define ARM_ETH_MAC_DUPLEX_Msk (1UL << ARM_ETH_MAC_DUPLEX_Pos) -#define ARM_ETH_MAC_DUPLEX_HALF (ARM_ETH_DUPLEX_HALF << ARM_ETH_MAC_DUPLEX_Pos) ///< Half duplex link -#define ARM_ETH_MAC_DUPLEX_FULL (ARM_ETH_DUPLEX_FULL << ARM_ETH_MAC_DUPLEX_Pos) ///< Full duplex link -#define ARM_ETH_MAC_LOOPBACK (1UL << 4) ///< Loop-back test mode -#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX (1UL << 5) ///< Receiver Checksum offload -#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX (1UL << 6) ///< Transmitter Checksum offload -#define ARM_ETH_MAC_ADDRESS_BROADCAST (1UL << 7) ///< Accept frames with Broadcast address -#define ARM_ETH_MAC_ADDRESS_MULTICAST (1UL << 8) ///< Accept frames with any Multicast address -#define ARM_ETH_MAC_ADDRESS_ALL (1UL << 9) ///< Accept frames with any address (Promiscuous Mode) - -/*----- Ethernet MAC Flush Flags -----*/ -#define ARM_ETH_MAC_FLUSH_RX (1UL << 0) ///< Flush Receive buffer -#define ARM_ETH_MAC_FLUSH_TX (1UL << 1) ///< Flush Transmit buffer - -/*----- Ethernet MAC VLAN Filter Flag -----*/ -#define ARM_ETH_MAC_VLAN_FILTER_ID_ONLY (1UL << 16) ///< Compare only the VLAN Identifier (12-bit) - - -/****** Ethernet MAC Frame Transmit Flags *****/ -#define ARM_ETH_MAC_TX_FRAME_FRAGMENT (1UL << 0) ///< Indicate frame fragment -#define ARM_ETH_MAC_TX_FRAME_EVENT (1UL << 1) ///< Generate event when frame is transmitted -#define ARM_ETH_MAC_TX_FRAME_TIMESTAMP (1UL << 2) ///< Capture frame time stamp - - -/****** Ethernet MAC Timer Control Codes *****/ -#define ARM_ETH_MAC_TIMER_GET_TIME (0x01) ///< Get current time -#define ARM_ETH_MAC_TIMER_SET_TIME (0x02) ///< Set new time -#define ARM_ETH_MAC_TIMER_INC_TIME (0x03) ///< Increment current time -#define ARM_ETH_MAC_TIMER_DEC_TIME (0x04) ///< Decrement current time -#define ARM_ETH_MAC_TIMER_SET_ALARM (0x05) ///< Set alarm time -#define ARM_ETH_MAC_TIMER_ADJUST_CLOCK (0x06) ///< Adjust clock frequency; time->ns: correction factor * 2^31 - - -/** -\brief Ethernet MAC Time -*/ -typedef struct _ARM_ETH_MAC_TIME { - uint32_t ns; ///< Nano seconds - uint32_t sec; ///< Seconds -} ARM_ETH_MAC_TIME; - - -/****** Ethernet MAC Event *****/ -#define ARM_ETH_MAC_EVENT_RX_FRAME (1UL << 0) ///< Frame Received -#define ARM_ETH_MAC_EVENT_TX_FRAME (1UL << 1) ///< Frame Transmitted -#define ARM_ETH_MAC_EVENT_WAKEUP (1UL << 2) ///< Wake-up (on Magic Packet) -#define ARM_ETH_MAC_EVENT_TIMER_ALARM (1UL << 3) ///< Timer Alarm - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION -*/ -/** - \fn ARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_ETH_MAC_CAPABILITIES -*/ -/** - \fn int32_t ARM_ETH_MAC_Initialize (ARM_ETH_MAC_SignalEvent_t cb_event) - \brief Initialize Ethernet MAC Device. - \param[in] cb_event Pointer to \ref ARM_ETH_MAC_SignalEvent - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_Uninitialize (void) - \brief De-initialize Ethernet MAC Device. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_PowerControl (ARM_POWER_STATE state) - \brief Control Ethernet MAC Device Power. - \param[in] state Power state - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_GetMacAddress (ARM_ETH_MAC_ADDR *ptr_addr) - \brief Get Ethernet MAC Address. - \param[in] ptr_addr Pointer to address - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_SetMacAddress (const ARM_ETH_MAC_ADDR *ptr_addr) - \brief Set Ethernet MAC Address. - \param[in] ptr_addr Pointer to address - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_SetAddressFilter (const ARM_ETH_MAC_ADDR *ptr_addr, - uint32_t num_addr) - \brief Configure Address Filter. - \param[in] ptr_addr Pointer to addresses - \param[in] num_addr Number of addresses to configure - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_SendFrame (const uint8_t *frame, uint32_t len, uint32_t flags) - \brief Send Ethernet frame. - \param[in] frame Pointer to frame buffer with data to send - \param[in] len Frame buffer length in bytes - \param[in] flags Frame transmit flags (see ARM_ETH_MAC_TX_FRAME_...) - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_ReadFrame (uint8_t *frame, uint32_t len) - \brief Read data of received Ethernet frame. - \param[in] frame Pointer to frame buffer for data to read into - \param[in] len Frame buffer length in bytes - \return number of data bytes read or execution status - - value >= 0: number of data bytes read - - value < 0: error occurred, value is execution status as defined with \ref execution_status -*/ -/** - \fn uint32_t ARM_ETH_MAC_GetRxFrameSize (void) - \brief Get size of received Ethernet frame. - \return number of bytes in received frame -*/ -/** - \fn int32_t ARM_ETH_MAC_GetRxFrameTime (ARM_ETH_MAC_TIME *time) - \brief Get time of received Ethernet frame. - \param[in] time Pointer to time structure for data to read into - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_GetTxFrameTime (ARM_ETH_MAC_TIME *time) - \brief Get time of transmitted Ethernet frame. - \param[in] time Pointer to time structure for data to read into - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_Control (uint32_t control, uint32_t arg) - \brief Control Ethernet Interface. - \param[in] control Operation - \param[in] arg Argument of operation (optional) - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_ControlTimer (uint32_t control, ARM_ETH_MAC_TIME *time) - \brief Control Precision Timer. - \param[in] control Operation - \param[in] time Pointer to time structure - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_PHY_Read (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) - \brief Read Ethernet PHY Register through Management Interface. - \param[in] phy_addr 5-bit device address - \param[in] reg_addr 5-bit register address - \param[out] data Pointer where the result is written to - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_MAC_PHY_Write (uint8_t phy_addr, uint8_t reg_addr, uint16_t data) - \brief Write Ethernet PHY Register through Management Interface. - \param[in] phy_addr 5-bit device address - \param[in] reg_addr 5-bit register address - \param[in] data 16-bit data to write - \return \ref execution_status -*/ - -/** - \fn void ARM_ETH_MAC_SignalEvent (uint32_t event) - \brief Callback function that signals a Ethernet Event. - \param[in] event event notification mask - \return none -*/ - -typedef void (*ARM_ETH_MAC_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_ETH_MAC_SignalEvent : Signal Ethernet Event. - - -/** -\brief Ethernet MAC Capabilities -*/ -typedef struct _ARM_ETH_MAC_CAPABILITIES { - uint32_t checksum_offload_rx_ip4 : 1; ///< 1 = IPv4 header checksum verified on receive - uint32_t checksum_offload_rx_ip6 : 1; ///< 1 = IPv6 checksum verification supported on receive - uint32_t checksum_offload_rx_udp : 1; ///< 1 = UDP payload checksum verified on receive - uint32_t checksum_offload_rx_tcp : 1; ///< 1 = TCP payload checksum verified on receive - uint32_t checksum_offload_rx_icmp : 1; ///< 1 = ICMP payload checksum verified on receive - uint32_t checksum_offload_tx_ip4 : 1; ///< 1 = IPv4 header checksum generated on transmit - uint32_t checksum_offload_tx_ip6 : 1; ///< 1 = IPv6 checksum generation supported on transmit - uint32_t checksum_offload_tx_udp : 1; ///< 1 = UDP payload checksum generated on transmit - uint32_t checksum_offload_tx_tcp : 1; ///< 1 = TCP payload checksum generated on transmit - uint32_t checksum_offload_tx_icmp : 1; ///< 1 = ICMP payload checksum generated on transmit - uint32_t media_interface : 2; ///< Ethernet Media Interface type - uint32_t mac_address : 1; ///< 1 = driver provides initial valid MAC address - uint32_t event_rx_frame : 1; ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_RX_FRAME generated - uint32_t event_tx_frame : 1; ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_TX_FRAME generated - uint32_t event_wakeup : 1; ///< 1 = wakeup event \ref ARM_ETH_MAC_EVENT_WAKEUP generated - uint32_t precision_timer : 1; ///< 1 = Precision Timer supported -} ARM_ETH_MAC_CAPABILITIES; - - -/** -\brief Access structure of the Ethernet MAC Driver -*/ -typedef struct _ARM_DRIVER_ETH_MAC { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_ETH_MAC_GetVersion : Get driver version. - ARM_ETH_MAC_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_ETH_MAC_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_ETH_MAC_SignalEvent_t cb_event); ///< Pointer to \ref ARM_ETH_MAC_Initialize : Initialize Ethernet MAC Device. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_ETH_MAC_Uninitialize : De-initialize Ethernet MAC Device. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_ETH_MAC_PowerControl : Control Ethernet MAC Device Power. - int32_t (*GetMacAddress) ( ARM_ETH_MAC_ADDR *ptr_addr); ///< Pointer to \ref ARM_ETH_MAC_GetMacAddress : Get Ethernet MAC Address. - int32_t (*SetMacAddress) (const ARM_ETH_MAC_ADDR *ptr_addr); ///< Pointer to \ref ARM_ETH_MAC_SetMacAddress : Set Ethernet MAC Address. - int32_t (*SetAddressFilter)(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr); ///< Pointer to \ref ARM_ETH_MAC_SetAddressFilter : Configure Address Filter. - int32_t (*SendFrame) (const uint8_t *frame, uint32_t len, uint32_t flags); ///< Pointer to \ref ARM_ETH_MAC_SendFrame : Send Ethernet frame. - int32_t (*ReadFrame) ( uint8_t *frame, uint32_t len); ///< Pointer to \ref ARM_ETH_MAC_ReadFrame : Read data of received Ethernet frame. - uint32_t (*GetRxFrameSize) (void); ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameSize : Get size of received Ethernet frame. - int32_t (*GetRxFrameTime) (ARM_ETH_MAC_TIME *time); ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameTime : Get time of received Ethernet frame. - int32_t (*GetTxFrameTime) (ARM_ETH_MAC_TIME *time); ///< Pointer to \ref ARM_ETH_MAC_GetTxFrameTime : Get time of transmitted Ethernet frame. - int32_t (*ControlTimer) (uint32_t control, ARM_ETH_MAC_TIME *time); ///< Pointer to \ref ARM_ETH_MAC_ControlTimer : Control Precision Timer. - int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_ETH_MAC_Control : Control Ethernet Interface. - int32_t (*PHY_Read) (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register through Management Interface. - int32_t (*PHY_Write) (uint8_t phy_addr, uint8_t reg_addr, uint16_t data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register through Management Interface. -} const ARM_DRIVER_ETH_MAC; - -#endif /* __DRIVER_ETH_MAC_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_ETH_PHY.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_ETH_PHY.h deleted file mode 100644 index 4066e1c8ac7..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_ETH_PHY.h +++ /dev/null @@ -1,133 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2014 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * - * $Date: 7. Mar 2014 - * $Revision: V2.00 - * - * Project: Ethernet PHY (Physical Transceiver) Driver definitions - * -------------------------------------------------------------------------- */ - -/* History: - * Version 2.00 - * changed parameter "mode" in function ARM_ETH_PHY_SetMode - * Changed prefix ARM_DRV -> ARM_DRIVER - * Changed return values of some functions to int32_t - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.00 - * Initial release - */ - -#ifndef __DRIVER_ETH_PHY_H -#define __DRIVER_ETH_PHY_H - -#include "Driver_ETH.h" - -#define ARM_ETH_PHY_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,00) /* API version */ - - -#define _ARM_Driver_ETH_PHY_(n) Driver_ETH_PHY##n -#define ARM_Driver_ETH_PHY_(n) _ARM_Driver_ETH_PHY_(n) - - -/****** Ethernet PHY Mode *****/ -#define ARM_ETH_PHY_SPEED_Pos 0 -#define ARM_ETH_PHY_SPEED_Msk (3UL << ARM_ETH_PHY_SPEED_Pos) -#define ARM_ETH_PHY_SPEED_10M (ARM_ETH_SPEED_10M << ARM_ETH_PHY_SPEED_Pos) ///< 10 Mbps link speed -#define ARM_ETH_PHY_SPEED_100M (ARM_ETH_SPEED_100M << ARM_ETH_PHY_SPEED_Pos) ///< 100 Mbps link speed -#define ARM_ETH_PHY_SPEED_1G (ARM_ETH_SPEED_1G << ARM_ETH_PHY_SPEED_Pos) ///< 1 Gpbs link speed -#define ARM_ETH_PHY_DUPLEX_Pos 2 -#define ARM_ETH_PHY_DUPLEX_Msk (1UL << ARM_ETH_PHY_DUPLEX_Pos) -#define ARM_ETH_PHY_DUPLEX_HALF (ARM_ETH_DUPLEX_HALF << ARM_ETH_PHY_DUPLEX_Pos) ///< Half duplex link -#define ARM_ETH_PHY_DUPLEX_FULL (ARM_ETH_DUPLEX_FULL << ARM_ETH_PHY_DUPLEX_Pos) ///< Full duplex link -#define ARM_ETH_PHY_AUTO_NEGOTIATE (1UL << 3) ///< Auto Negotiation mode -#define ARM_ETH_PHY_LOOPBACK (1UL << 4) ///< Loop-back test mode -#define ARM_ETH_PHY_ISOLATE (1UL << 5) ///< Isolate PHY from MII/RMII interface - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION -*/ -/** - \fn int32_t ARM_ETH_PHY_Initialize (ARM_ETH_PHY_Read_t fn_read, - ARM_ETH_PHY_Write_t fn_write) - \brief Initialize Ethernet PHY Device. - \param[in] fn_read Pointer to \ref ARM_ETH_MAC_PHY_Read - \param[in] fn_write Pointer to \ref ARM_ETH_MAC_PHY_Write - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_PHY_Uninitialize (void) - \brief De-initialize Ethernet PHY Device. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_PHY_PowerControl (ARM_POWER_STATE state) - \brief Control Ethernet PHY Device Power. - \param[in] state Power state - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_PHY_SetInterface (uint32_t interface) - \brief Set Ethernet Media Interface. - \param[in] interface Media Interface type - \return \ref execution_status -*/ -/** - \fn int32_t ARM_ETH_PHY_SetMode (uint32_t mode) - \brief Set Ethernet PHY Device Operation mode. - \param[in] mode Operation Mode - \return \ref execution_status -*/ -/** - \fn ARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState (void) - \brief Get Ethernet PHY Device Link state. - \return current link status \ref ARM_ETH_LINK_STATE -*/ -/** - \fn ARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo (void) - \brief Get Ethernet PHY Device Link information. - \return current link parameters \ref ARM_ETH_LINK_INFO -*/ - - -typedef int32_t (*ARM_ETH_PHY_Read_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register. -typedef int32_t (*ARM_ETH_PHY_Write_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register. - - -/** -\brief Access structure of the Ethernet PHY Driver -*/ -typedef struct _ARM_DRIVER_ETH_PHY { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_ETH_PHY_GetVersion : Get driver version. - int32_t (*Initialize) (ARM_ETH_PHY_Read_t fn_read, - ARM_ETH_PHY_Write_t fn_write); ///< Pointer to \ref ARM_ETH_PHY_Initialize : Initialize PHY Device. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_ETH_PHY_Uninitialize : De-initialize PHY Device. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_ETH_PHY_PowerControl : Control PHY Device Power. - int32_t (*SetInterface) (uint32_t interface); ///< Pointer to \ref ARM_ETH_PHY_SetInterface : Set Ethernet Media Interface. - int32_t (*SetMode) (uint32_t mode); ///< Pointer to \ref ARM_ETH_PHY_SetMode : Set Ethernet PHY Device Operation mode. - ARM_ETH_LINK_STATE (*GetLinkState) (void); ///< Pointer to \ref ARM_ETH_PHY_GetLinkState : Get Ethernet PHY Device Link state. - ARM_ETH_LINK_INFO (*GetLinkInfo) (void); ///< Pointer to \ref ARM_ETH_PHY_GetLinkInfo : Get Ethernet PHY Device Link information. -} const ARM_DRIVER_ETH_PHY; - -#endif /* __DRIVER_ETH_PHY_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_Flash.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_Flash.h deleted file mode 100644 index 0223299bd48..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_Flash.h +++ /dev/null @@ -1,194 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2014 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * - * $Date: 31. Mar 2014 - * $Revision: V2.00 - * - * Project: Flash Driver definitions - * -------------------------------------------------------------------------- */ - -/* History: - * Version 2.00 - * Renamed driver NOR -> Flash (more generic) - * Non-blocking operation - * Added Events, Status and Capabilities - * Linked Flash information (GetInfo) - * Version 1.11 - * Changed prefix ARM_DRV -> ARM_DRIVER - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.00 - * Initial release - */ - -#ifndef __DRIVER_FLASH_H -#define __DRIVER_FLASH_H - -#include "Driver_Common.h" - -#define ARM_FLASH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,00) /* API version */ - - -#define _ARM_Driver_Flash_(n) Driver_Flash##n -#define ARM_Driver_Flash_(n) _ARM_Driver_Flash_(n) - - -#define ARM_FLASH_SECTOR_INFO(addr,size) { (addr), (addr)+(size)-1 } - -/** -\brief Flash Sector information -*/ -typedef struct _ARM_FLASH_SECTOR { - uint32_t start; ///< Sector Start address - uint32_t end; ///< Sector End address (start+size-1) -} const ARM_FLASH_SECTOR; - -/** -\brief Flash information -*/ -typedef struct _ARM_FLASH_INFO { - ARM_FLASH_SECTOR *sector_info; ///< Sector layout information (NULL=Uniform sectors) - uint32_t sector_count; ///< Number of sectors - uint32_t sector_size; ///< Uniform sector size in bytes (0=sector_info used) - uint32_t page_size; ///< Optimal programming page size in bytes - uint32_t program_unit; ///< Smallest programmable unit in bytes - uint8_t erased_value; ///< Contents of erased memory (usually 0xFF) -} const ARM_FLASH_INFO; - - -/** -\brief Flash Status -*/ -typedef struct _ARM_FLASH_STATUS { - uint32_t busy : 1; ///< Flash busy flag - uint32_t error : 1; ///< Read/Program/Erase error flag (cleared on start of next operation) -} ARM_FLASH_STATUS; - - -/****** Flash Event *****/ -#define ARM_FLASH_EVENT_READY (1UL << 0) ///< Flash Ready -#define ARM_FLASH_EVENT_ERROR (1UL << 1) ///< Read/Program/Erase Error - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_Flash_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION -*/ -/** - \fn ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_FLASH_CAPABILITIES -*/ -/** - \fn int32_t ARM_Flash_Initialize (ARM_Flash_SignalEvent_t cb_event) - \brief Initialize the Flash Interface. - \param[in] cb_event Pointer to \ref ARM_Flash_SignalEvent - \return \ref execution_status -*/ -/** - \fn int32_t ARM_Flash_Uninitialize (void) - \brief De-initialize the Flash Interface. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_Flash_PowerControl (ARM_POWER_STATE state) - \brief Control the Flash interface power. - \param[in] state Power state - \return \ref execution_status -*/ -/** - \fn int32_t ARM_Flash_ReadData (uint32_t addr, void *data, uint32_t cnt) - \brief Read data from Flash. - \param[in] addr Data address. - \param[out] data Pointer to a buffer storing the data read from Flash. - \param[in] cnt Number of data items to read. - \return number of data items read or \ref execution_status -*/ -/** - \fn int32_t ARM_Flash_ProgramData (uint32_t addr, const void *data, uint32_t cnt) - \brief Program data to Flash. - \param[in] addr Data address. - \param[in] data Pointer to a buffer containing the data to be programmed to Flash. - \param[in] cnt Number of data items to program. - \return number of data items programmed or \ref execution_status -*/ -/** - \fn int32_t ARM_Flash_EraseSector (uint32_t addr) - \brief Erase Flash Sector. - \param[in] addr Sector address - \return \ref execution_status -*/ -/** - \fn int32_t ARM_Flash_EraseChip (void) - \brief Erase complete Flash. - Optional function for faster full chip erase. - \return \ref execution_status -*/ -/** - \fn ARM_FLASH_STATUS ARM_Flash_GetStatus (void) - \brief Get Flash status. - \return Flash status \ref ARM_FLASH_STATUS -*/ -/** - \fn ARM_FLASH_INFO * ARM_Flash_GetInfo (void) - \brief Get Flash information. - \return Pointer to Flash information \ref ARM_FLASH_INFO -*/ - -/** - \fn void ARM_Flash_SignalEvent (uint32_t event) - \brief Signal Flash event. - \param[in] event Event notification mask - \return none -*/ - -typedef void (*ARM_Flash_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_Flash_SignalEvent : Signal Flash Event. - - -/** -\brief Flash Driver Capabilities. -*/ -typedef struct _ARM_FLASH_CAPABILITIES { - uint32_t event_ready : 1; ///< Signal Flash Ready event - uint32_t data_width : 2; ///< Data width: 0=8-bit, 1=16-bit, 2=32-bit - uint32_t erase_chip : 1; ///< Supports EraseChip operation -} ARM_FLASH_CAPABILITIES; - - -/** -\brief Access structure of the Flash Driver -*/ -typedef struct _ARM_DRIVER_FLASH { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_Flash_GetVersion : Get driver version. - ARM_FLASH_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_Flash_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_Flash_SignalEvent_t cb_event); ///< Pointer to \ref ARM_Flash_Initialize : Initialize Flash Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_Flash_Uninitialize : De-initialize Flash Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_Flash_PowerControl : Control Flash Interface Power. - int32_t (*ReadData) (uint32_t addr, void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ReadData : Read data from Flash. - int32_t (*ProgramData) (uint32_t addr, const void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ProgramData : Program data to Flash. - int32_t (*EraseSector) (uint32_t addr); ///< Pointer to \ref ARM_Flash_EraseSector : Erase Flash Sector. - int32_t (*EraseChip) (void); ///< Pointer to \ref ARM_Flash_EraseChip : Erase complete Flash. - ARM_FLASH_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_Flash_GetStatus : Get Flash status. - ARM_FLASH_INFO * (*GetInfo) (void); ///< Pointer to \ref ARM_Flash_GetInfo : Get Flash information. -} const ARM_DRIVER_FLASH; - -#endif /* __DRIVER_FLASH_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_I2C.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_I2C.h deleted file mode 100644 index da05f982ad4..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_I2C.h +++ /dev/null @@ -1,207 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2014 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * - * $Date: 9. May 2014 - * $Revision: V2.02 - * - * Project: I2C (Inter-Integrated Circuit) Driver definitions - * -------------------------------------------------------------------------- */ - -/* History: - * Version 2.02 - * Removed function ARM_I2C_MasterTransfer in order to simplify drivers - * and added back parameter "xfer_pending" to functions - * ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive - * Version 2.01 - * Added function ARM_I2C_MasterTransfer and removed parameter "xfer_pending" - * from functions ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive - * Added function ARM_I2C_GetDataCount - * Removed flag "address_nack" from ARM_I2C_STATUS - * Replaced events ARM_I2C_EVENT_MASTER_DONE and ARM_I2C_EVENT_SLAVE_DONE - * with event ARM_I2C_EVENT_TRANSFER_DONE - * Added event ARM_I2C_EVENT_TRANSFER_INCOMPLETE - * Removed parameter "arg" from function ARM_I2C_SignalEvent - * Version 2.00 - * New simplified driver: - * complexity moved to upper layer (especially data handling) - * more unified API for different communication interfaces - * Added: - * Slave Mode - * Changed prefix ARM_DRV -> ARM_DRIVER - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.00 - * Initial release - */ - -#ifndef __DRIVER_I2C_H -#define __DRIVER_I2C_H - -#include "Driver_Common.h" - -#define ARM_I2C_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,02) /* API version */ - - -/****** I2C Control Codes *****/ - -#define ARM_I2C_OWN_ADDRESS (0x01) ///< Set Own Slave Address; arg = address -#define ARM_I2C_BUS_SPEED (0x02) ///< Set Bus Speed; arg = speed -#define ARM_I2C_BUS_CLEAR (0x03) ///< Execute Bus clear: send nine clock pulses -#define ARM_I2C_ABORT_TRANSFER (0x04) ///< Abort Master/Slave Transmit/Receive - -/*----- I2C Bus Speed -----*/ -#define ARM_I2C_BUS_SPEED_STANDARD (0x01) ///< Standard Speed (100kHz) -#define ARM_I2C_BUS_SPEED_FAST (0x02) ///< Fast Speed (400kHz) -#define ARM_I2C_BUS_SPEED_FAST_PLUS (0x03) ///< Fast+ Speed ( 1MHz) -#define ARM_I2C_BUS_SPEED_HIGH (0x04) ///< High Speed (3.4MHz) - - -/****** I2C Address Flags *****/ - -#define ARM_I2C_ADDRESS_10BIT 0x0400 ///< 10-bit address flag -#define ARM_I2C_ADDRESS_GC 0x8000 ///< General Call flag - - -/** -\brief I2C Status -*/ -typedef struct _ARM_I2C_STATUS { - uint32_t busy : 1; ///< Busy flag - uint32_t mode : 1; ///< Mode: 0=Slave, 1=Master - uint32_t direction : 1; ///< Direction: 0=Transmitter, 1=Receiver - uint32_t general_call : 1; ///< General Call indication (cleared on start of next Slave operation) - uint32_t arbitration_lost : 1; ///< Master lost arbitration (cleared on start of next Master operation) - uint32_t bus_error : 1; ///< Bus error detected (cleared on start of next Master/Slave operation) -} ARM_I2C_STATUS; - - -/****** I2C Event *****/ -#define ARM_I2C_EVENT_TRANSFER_DONE (1UL << 0) ///< Master/Slave Transmit/Receive finished -#define ARM_I2C_EVENT_TRANSFER_INCOMPLETE (1UL << 1) ///< Master/Slave Transmit/Receive incomplete transfer -#define ARM_I2C_EVENT_SLAVE_TRANSMIT (1UL << 2) ///< Slave Transmit operation requested -#define ARM_I2C_EVENT_SLAVE_RECEIVE (1UL << 3) ///< Slave Receive operation requested -#define ARM_I2C_EVENT_ADDRESS_NACK (1UL << 4) ///< Address not acknowledged from Slave -#define ARM_I2C_EVENT_GENERAL_CALL (1UL << 5) ///< General Call indication -#define ARM_I2C_EVENT_ARBITRATION_LOST (1UL << 6) ///< Master lost arbitration -#define ARM_I2C_EVENT_BUS_ERROR (1UL << 7) ///< Bus error detected (START/STOP at illegal position) -#define ARM_I2C_EVENT_BUS_CLEAR (1UL << 8) ///< Bus clear finished - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_I2C_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION - - \fn ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_I2C_CAPABILITIES - - \fn int32_t ARM_I2C_Initialize (ARM_I2C_SignalEvent_t cb_event) - \brief Initialize I2C Interface. - \param[in] cb_event Pointer to \ref ARM_I2C_SignalEvent - \return \ref execution_status - - \fn int32_t ARM_I2C_Uninitialize (void) - \brief De-initialize I2C Interface. - \return \ref execution_status - - \fn int32_t ARM_I2C_PowerControl (ARM_POWER_STATE state) - \brief Control I2C Interface Power. - \param[in] state Power state - \return \ref execution_status - - \fn int32_t ARM_I2C_MasterTransmit (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) - \brief Start transmitting data as I2C Master. - \param[in] addr Slave address (7-bit or 10-bit) - \param[in] data Pointer to buffer with data to transmit to I2C Slave - \param[in] num Number of data bytes to transmit - \param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated - \return \ref execution_status - - \fn int32_t ARM_I2C_MasterReceive (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) - \brief Start receiving data as I2C Master. - \param[in] addr Slave address (7-bit or 10-bit) - \param[out] data Pointer to buffer for data to receive from I2C Slave - \param[in] num Number of data bytes to receive - \param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated - \return \ref execution_status - - \fn int32_t ARM_I2C_SlaveTransmit (const uint8_t *data, uint32_t num) - \brief Start transmitting data as I2C Slave. - \param[in] data Pointer to buffer with data to transmit to I2C Master - \param[in] num Number of data bytes to transmit - \return \ref execution_status - - \fn int32_t ARM_I2C_SlaveReceive (uint8_t *data, uint32_t num) - \brief Start receiving data as I2C Slave. - \param[out] data Pointer to buffer for data to receive from I2C Master - \param[in] num Number of data bytes to receive - \return \ref execution_status - - \fn int32_t ARM_I2C_GetDataCount (void) - \brief Get transferred data count. - \return number of data bytes transferred; -1 when Slave is not addressed by Master - - \fn int32_t ARM_I2C_Control (uint32_t control, uint32_t arg) - \brief Control I2C Interface. - \param[in] control Operation - \param[in] arg Argument of operation (optional) - \return \ref execution_status - - \fn ARM_I2C_STATUS ARM_I2C_GetStatus (void) - \brief Get I2C status. - \return I2C status \ref ARM_I2C_STATUS - - \fn void ARM_I2C_SignalEvent (uint32_t event) - \brief Signal I2C Events. - \param[in] event \ref I2C_events notification mask -*/ - -typedef void (*ARM_I2C_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_I2C_SignalEvent : Signal I2C Event. - - -/** -\brief I2C Driver Capabilities. -*/ -typedef struct _ARM_I2C_CAPABILITIES { - uint32_t address_10_bit : 1; ///< supports 10-bit addressing -} ARM_I2C_CAPABILITIES; - - -/** -\brief Access structure of the I2C Driver. -*/ -typedef struct _ARM_DRIVER_I2C { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_I2C_GetVersion : Get driver version. - ARM_I2C_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_I2C_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_I2C_SignalEvent_t cb_event); ///< Pointer to \ref ARM_I2C_Initialize : Initialize I2C Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_I2C_Uninitialize : De-initialize I2C Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_I2C_PowerControl : Control I2C Interface Power. - int32_t (*MasterTransmit) (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterTransmit : Start transmitting data as I2C Master. - int32_t (*MasterReceive) (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterReceive : Start receiving data as I2C Master. - int32_t (*SlaveTransmit) ( const uint8_t *data, uint32_t num); ///< Pointer to \ref ARM_I2C_SlaveTransmit : Start transmitting data as I2C Slave. - int32_t (*SlaveReceive) ( uint8_t *data, uint32_t num); ///< Pointer to \ref ARM_I2C_SlaveReceive : Start receiving data as I2C Slave. - int32_t (*GetDataCount) (void); ///< Pointer to \ref ARM_I2C_GetDataCount : Get transferred data count. - int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_I2C_Control : Control I2C Interface. - ARM_I2C_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_I2C_GetStatus : Get I2C status. -} const ARM_DRIVER_I2C; - -#endif /* __DRIVER_I2C_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_MCI.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_MCI.h deleted file mode 100644 index 93375d07eb3..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_MCI.h +++ /dev/null @@ -1,350 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2014 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * - * $Date: 16. May 2014 - * $Revision: V2.02 - * - * Project: MCI (Memory Card Interface) Driver definitions - * -------------------------------------------------------------------------- */ - -/* History: - * Version 2.02 - * Added timeout and error flags to ARM_MCI_STATUS - * Added support for controlling optional RST_n pin (eMMC) - * Removed explicit Clock Control (ARM_MCI_CONTROL_CLOCK) - * Removed event ARM_MCI_EVENT_BOOT_ACK_TIMEOUT - * Version 2.01 - * Decoupled SPI mode from MCI driver - * Replaced function ARM_MCI_CardSwitchRead with ARM_MCI_ReadCD and ARM_MCI_ReadWP - * Version 2.00 - * Added support for: - * SD UHS-I (Ultra High Speed) - * SD I/O Interrupt - * Read Wait (SD I/O) - * Suspend/Resume (SD I/O) - * MMC Interrupt - * MMC Boot - * Stream Data transfer (MMC) - * VCCQ Power Supply Control (eMMC) - * Command Completion Signal (CCS) for CE-ATA - * Added ARM_MCI_Control function - * Added ARM_MCI_GetStatus function - * Removed ARM_MCI_BusMode, ARM_MCI_BusDataWidth, ARM_MCI_BusSingaling functions - * (replaced by ARM_MCI_Control) - * Changed ARM_MCI_CardPower function (voltage parameter) - * Changed ARM_MCI_SendCommnad function (flags parameter) - * Changed ARM_MCI_SetupTransfer function (mode parameter) - * Removed ARM_MCI_ReadTransfer and ARM_MCI_WriteTransfer functions - * Changed prefix ARM_DRV -> ARM_DRIVER - * Changed return values of some functions to int32_t - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.00 - * Initial release - */ - -#ifndef __DRIVER_MCI_H -#define __DRIVER_MCI_H - -#include "Driver_Common.h" - -#define ARM_MCI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,02) /* API version */ - - -/****** MCI Send Command Flags *****/ -#define ARM_MCI_RESPONSE_Pos 0 -#define ARM_MCI_RESPONSE_Msk (3UL << ARM_MCI_RESPONSE_Pos) -#define ARM_MCI_RESPONSE_NONE (0UL << ARM_MCI_RESPONSE_Pos) ///< No response expected (default) -#define ARM_MCI_RESPONSE_SHORT (1UL << ARM_MCI_RESPONSE_Pos) ///< Short response (48-bit) -#define ARM_MCI_RESPONSE_SHORT_BUSY (2UL << ARM_MCI_RESPONSE_Pos) ///< Short response with busy signal (48-bit) -#define ARM_MCI_RESPONSE_LONG (3UL << ARM_MCI_RESPONSE_Pos) ///< Long response (136-bit) - -#define ARM_MCI_RESPONSE_INDEX (1UL << 2) ///< Check command index in response -#define ARM_MCI_RESPONSE_CRC (1UL << 3) ///< Check CRC in response - -#define ARM_MCI_WAIT_BUSY (1UL << 4) ///< Wait until busy before sending the command - -#define ARM_MCI_TRANSFER_DATA (1UL << 5) ///< Activate Data transfer - -#define ARM_MCI_CARD_INITIALIZE (1UL << 6) ///< Execute Memory Card initialization sequence - -#define ARM_MCI_INTERRUPT_COMMAND (1UL << 7) ///< Send Interrupt command (CMD40 - MMC only) -#define ARM_MCI_INTERRUPT_RESPONSE (1UL << 8) ///< Send Interrupt response (CMD40 - MMC only) - -#define ARM_MCI_BOOT_OPERATION (1UL << 9) ///< Execute Boot operation (MMC only) -#define ARM_MCI_BOOT_ALTERNATIVE (1UL << 10) ///< Execute Alternative Boot operation (MMC only) -#define ARM_MCI_BOOT_ACK (1UL << 11) ///< Expect Boot Acknowledge (MMC only) - -#define ARM_MCI_CCSD (1UL << 12) ///< Send Command Completion Signal Disable (CCSD) for CE-ATA device -#define ARM_MCI_CCS (1UL << 13) ///< Expect Command Completion Signal (CCS) for CE-ATA device - - -/****** MCI Setup Transfer Mode *****/ -#define ARM_MCI_TRANSFER_READ (0UL << 0) ///< Data Read Transfer (from MCI) -#define ARM_MCI_TRANSFER_WRITE (1UL << 0) ///< Data Write Transfer (to MCI) -#define ARM_MCI_TRANSFER_BLOCK (0UL << 1) ///< Block Data transfer (default) -#define ARM_MCI_TRANSFER_STREAM (1UL << 1) ///< Stream Data transfer (MMC only) - - -/****** MCI Control Codes *****/ -#define ARM_MCI_BUS_SPEED (0x01) ///< Set Bus Speed; arg = requested speed in bits/s; returns configured speed in bits/s -#define ARM_MCI_BUS_SPEED_MODE (0x02) ///< Set Bus Speed Mode as specified with arg -#define ARM_MCI_BUS_CMD_MODE (0x03) ///< Set CMD Line Mode as specified with arg -#define ARM_MCI_BUS_DATA_WIDTH (0x04) ///< Set Bus Data Width as specified with arg -#define ARM_MCI_DRIVER_STRENGTH (0x05) ///< Set SD UHS-I Driver Strength as specified with arg -#define ARM_MCI_CONTROL_RESET (0x06) ///< Control optional RST_n Pin (eMMC); arg: 0=inactive, 1=active -#define ARM_MCI_CONTROL_CLOCK_IDLE (0x07) ///< Control Clock generation on CLK Pin when idle; arg: 0=disabled, 1=enabled -#define ARM_MCI_UHS_TUNING_OPERATION (0x08) ///< Sampling clock Tuning operation (SD UHS-I); arg: 0=reset, 1=execute -#define ARM_MCI_UHS_TUNING_RESULT (0x09) ///< Sampling clock Tuning result (SD UHS-I); returns: 0=done, 1=in progress, -1=error -#define ARM_MCI_DATA_TIMEOUT (0x0A) ///< Set Data timeout; arg = timeout in bus cycles -#define ARM_MCI_CSS_TIMEOUT (0x0B) ///< Set Command Completion Signal (CCS) timeout; arg = timeout in bus cycles -#define ARM_MCI_MONITOR_SDIO_INTERRUPT (0x0C) ///< Monitor SD I/O interrupt: arg: 0=disabled, 1=enabled -#define ARM_MCI_CONTROL_READ_WAIT (0x0D) ///< Control Read/Wait for SD I/O; arg: 0=disabled, 1=enabled -#define ARM_MCI_SUSPEND_TRANSFER (0x0E) ///< Suspend Data transfer (SD I/O); returns number of remaining bytes to transfer -#define ARM_MCI_RESUME_TRANSFER (0x0F) ///< Resume Data transfer (SD I/O) - -/*----- MCI Bus Speed Mode -----*/ -#define ARM_MCI_BUS_DEFAULT_SPEED (0x00) ///< SD/MMC: Default Speed mode up to 25/26MHz -#define ARM_MCI_BUS_HIGH_SPEED (0x01) ///< SD/MMC: High Speed mode up to 50/52MHz -#define ARM_MCI_BUS_UHS_SDR12 (0x02) ///< SD: SDR12 (Single Data Rate) up to 25MHz, 12.5MB/s: UHS-I (Ultra High Speed) 1.8V signaling -#define ARM_MCI_BUS_UHS_SDR25 (0x03) ///< SD: SDR25 (Single Data Rate) up to 50MHz, 25 MB/s: UHS-I (Ultra High Speed) 1.8V signaling -#define ARM_MCI_BUS_UHS_SDR50 (0x04) ///< SD: SDR50 (Single Data Rate) up to 100MHz, 50 MB/s: UHS-I (Ultra High Speed) 1.8V signaling -#define ARM_MCI_BUS_UHS_SDR104 (0x05) ///< SD: SDR104 (Single Data Rate) up to 208MHz, 104 MB/s: UHS-I (Ultra High Speed) 1.8V signaling -#define ARM_MCI_BUS_UHS_DDR50 (0x06) ///< SD: DDR50 (Dual Data Rate) up to 50MHz, 50 MB/s: UHS-I (Ultra High Speed) 1.8V signaling - -/*----- MCI CMD Line Mode -----*/ -#define ARM_MCI_BUS_CMD_PUSH_PULL (0x00) ///< Push-Pull CMD line (default) -#define ARM_MCI_BUS_CMD_OPEN_DRAIN (0x01) ///< Open Drain CMD line (MMC only) - -/*----- MCI Bus Data Width -----*/ -#define ARM_MCI_BUS_DATA_WIDTH_1 (0x00) ///< Bus data width: 1 bit (default) -#define ARM_MCI_BUS_DATA_WIDTH_4 (0x01) ///< Bus data width: 4 bits -#define ARM_MCI_BUS_DATA_WIDTH_8 (0x02) ///< Bus data width: 8 bits -#define ARM_MCI_BUS_DATA_WIDTH_4_DDR (0x03) ///< Bus data width: 4 bits, DDR (Dual Data Rate) - MMC only -#define ARM_MCI_BUS_DATA_WIDTH_8_DDR (0x04) ///< Bus data width: 8 bits, DDR (Dual Data Rate) - MMC only - -/*----- MCI Driver Strength -----*/ -#define ARM_MCI_DRIVER_TYPE_A (0x01) ///< SD UHS-I Driver Type A -#define ARM_MCI_DRIVER_TYPE_B (0x00) ///< SD UHS-I Driver Type B (default) -#define ARM_MCI_DRIVER_TYPE_C (0x02) ///< SD UHS-I Driver Type C -#define ARM_MCI_DRIVER_TYPE_D (0x03) ///< SD UHS-I Driver Type D - - -/****** MCI Card Power *****/ -#define ARM_MCI_POWER_VDD_Pos 0 -#define ARM_MCI_POWER_VDD_Msk (0x0FUL << ARM_MCI_POWER_VDD_Pos) -#define ARM_MCI_POWER_VDD_OFF (0x01UL << ARM_MCI_POWER_VDD_Pos) ///< VDD (VCC) turned off -#define ARM_MCI_POWER_VDD_3V3 (0x02UL << ARM_MCI_POWER_VDD_Pos) ///< VDD (VCC) = 3.3V -#define ARM_MCI_POWER_VDD_1V8 (0x03UL << ARM_MCI_POWER_VDD_Pos) ///< VDD (VCC) = 1.8V -#define ARM_MCI_POWER_VCCQ_Pos 4 -#define ARM_MCI_POWER_VCCQ_Msk (0x0FUL << ARM_MCI_POWER_VCCQ_Pos) -#define ARM_MCI_POWER_VCCQ_OFF (0x01UL << ARM_MCI_POWER_VCCQ_Pos) ///< eMMC VCCQ turned off -#define ARM_MCI_POWER_VCCQ_3V3 (0x02UL << ARM_MCI_POWER_VCCQ_Pos) ///< eMMC VCCQ = 3.3V -#define ARM_MCI_POWER_VCCQ_1V8 (0x03UL << ARM_MCI_POWER_VCCQ_Pos) ///< eMMC VCCQ = 1.8V -#define ARM_MCI_POWER_VCCQ_1V2 (0x04UL << ARM_MCI_POWER_VCCQ_Pos) ///< eMMC VCCQ = 1.2V - - -/** -\brief MCI Status -*/ -typedef struct _ARM_MCI_STATUS { - uint32_t command_active : 1; ///< Command active flag - uint32_t command_timeout : 1; ///< Command timeout flag (cleared on start of next command) - uint32_t command_error : 1; ///< Command error flag (cleared on start of next command) - uint32_t transfer_active : 1; ///< Transfer active flag - uint32_t transfer_timeout : 1; ///< Transfer timeout flag (cleared on start of next command) - uint32_t transfer_error : 1; ///< Transfer error flag (cleared on start of next command) - uint32_t sdio_interrupt : 1; ///< SD I/O Interrupt flag (cleared on start of monitoring) - uint32_t ccs : 1; ///< CCS flag (cleared on start of next command) -} ARM_MCI_STATUS; - - -/****** MCI Card Event *****/ -#define ARM_MCI_EVENT_CARD_INSERTED (1UL << 0) ///< Memory Card inserted -#define ARM_MCI_EVENT_CARD_REMOVED (1UL << 1) ///< Memory Card removed -#define ARM_MCI_EVENT_COMMAND_COMPLETE (1UL << 2) ///< Command completed -#define ARM_MCI_EVENT_COMMAND_TIMEOUT (1UL << 3) ///< Command timeout -#define ARM_MCI_EVENT_COMMAND_ERROR (1UL << 4) ///< Command response error (CRC error or invalid response) -#define ARM_MCI_EVENT_TRANSFER_COMPLETE (1UL << 5) ///< Data transfer completed -#define ARM_MCI_EVENT_TRANSFER_TIMEOUT (1UL << 6) ///< Data transfer timeout -#define ARM_MCI_EVENT_TRANSFER_ERROR (1UL << 7) ///< Data transfer CRC failed -#define ARM_MCI_EVENT_SDIO_INTERRUPT (1UL << 8) ///< SD I/O Interrupt -#define ARM_MCI_EVENT_CCS (1UL << 9) ///< Command Completion Signal (CCS) -#define ARM_MCI_EVENT_CCS_TIMEOUT (1UL << 10) ///< Command Completion Signal (CCS) Timeout - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_MCI_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION -*/ -/** - \fn ARM_MCI_CAPABILITIES ARM_MCI_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_MCI_CAPABILITIES -*/ -/** - \fn int32_t ARM_MCI_Initialize (ARM_MCI_SignalEvent_t cb_event) - \brief Initialize the Memory Card Interface - \param[in] cb_event Pointer to \ref ARM_MCI_SignalEvent - \return \ref execution_status -*/ -/** - \fn int32_t ARM_MCI_Uninitialize (void) - \brief De-initialize Memory Card Interface. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_MCI_PowerControl (ARM_POWER_STATE state) - \brief Control Memory Card Interface Power. - \param[in] state Power state \ref ARM_POWER_STATE - \return \ref execution_status -*/ -/** - \fn int32_t ARM_MCI_CardPower (uint32_t voltage) - \brief Set Memory Card Power supply voltage. - \param[in] voltage Memory Card Power supply voltage - \return \ref execution_status -*/ -/** - \fn int32_t ARM_MCI_ReadCD (void) - \brief Read Card Detect (CD) state. - \return 1:card detected, 0:card not detected, or error -*/ -/** - \fn int32_t ARM_MCI_ReadWP (void) - \brief Read Write Protect (WP) state. - \return 1:write protected, 0:not write protected, or error -*/ -/** - \fn int32_t ARM_MCI_SendCommand (uint32_t cmd, - uint32_t arg, - uint32_t flags, - uint32_t *response) - \brief Send Command to card and get the response. - \param[in] cmd Memory Card command - \param[in] arg Command argument - \param[in] flags Command flags - \param[out] response Pointer to buffer for response - \return \ref execution_status -*/ -/** - \fn int32_t ARM_MCI_SetupTransfer (uint8_t *data, - uint32_t block_count, - uint32_t block_size, - uint32_t mode) - \brief Setup read or write transfer operation. - \param[in,out] data Pointer to data block(s) to be written or read - \param[in] block_count Number of blocks - \param[in] block_size Size of a block in bytes - \param[in] mode Transfer mode - \return \ref execution_status -*/ -/** - \fn int32_t ARM_MCI_AbortTransfer (void) - \brief Abort current read/write data transfer. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_MCI_Control (uint32_t control, uint32_t arg) - \brief Control MCI Interface. - \param[in] control Operation - \param[in] arg Argument of operation (optional) - \return \ref execution_status -*/ -/** - \fn ARM_MCI_STATUS ARM_MCI_GetStatus (void) - \brief Get MCI status. - \return MCI status \ref ARM_MCI_STATUS -*/ - -/** - \fn void ARM_MCI_SignalEvent (uint32_t event) - \brief Callback function that signals a MCI Card Event. - \param[in] event \ref mci_event_gr - \return none -*/ - -typedef void (*ARM_MCI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_MCI_SignalEvent : Signal MCI Card Event. - - -/** -\brief MCI Driver Capabilities. -*/ -typedef struct _ARM_MCI_CAPABILITIES { - uint32_t cd_state : 1; ///< Card Detect State available - uint32_t cd_event : 1; ///< Signal Card Detect change event - uint32_t wp_state : 1; ///< Write Protect State available - uint32_t vdd : 1; ///< Supports VDD Card Power Supply Control - uint32_t vdd_1v8 : 1; ///< Supports 1.8 VDD Card Power Supply - uint32_t vccq : 1; ///< Supports VCCQ Card Power Supply Control (eMMC) - uint32_t vccq_1v8 : 1; ///< Supports 1.8 VCCQ Card Power Supply (eMMC) - uint32_t vccq_1v2 : 1; ///< Supports 1.2 VCCQ Card Power Supply (eMMC) - uint32_t data_width_4 : 1; ///< Supports 4-bit data - uint32_t data_width_8 : 1; ///< Supports 8-bit data - uint32_t data_width_4_ddr : 1; ///< Supports 4-bit data, DDR (Dual Data Rate) - MMC only - uint32_t data_width_8_ddr : 1; ///< Supports 8-bit data, DDR (Dual Data Rate) - MMC only - uint32_t high_speed : 1; ///< Supports SD/MMC High Speed Mode - uint32_t uhs_signaling : 1; ///< Supports SD UHS-I (Ultra High Speed) 1.8V signaling - uint32_t uhs_tuning : 1; ///< Supports SD UHS-I tuning - uint32_t uhs_sdr50 : 1; ///< Supports SD UHS-I SDR50 (Single Data Rate) up to 50MB/s - uint32_t uhs_sdr104 : 1; ///< Supports SD UHS-I SDR104 (Single Data Rate) up to 104MB/s - uint32_t uhs_ddr50 : 1; ///< Supports SD UHS-I DDR50 (Dual Data Rate) up to 50MB/s - uint32_t uhs_driver_type_a : 1; ///< Supports SD UHS-I Driver Type A - uint32_t uhs_driver_type_c : 1; ///< Supports SD UHS-I Driver Type C - uint32_t uhs_driver_type_d : 1; ///< Supports SD UHS-I Driver Type D - uint32_t sdio_interrupt : 1; ///< Supports SD I/O Interrupt - uint32_t read_wait : 1; ///< Supports Read Wait (SD I/O) - uint32_t suspend_resume : 1; ///< Supports Suspend/Resume (SD I/O) - uint32_t mmc_interrupt : 1; ///< Supports MMC Interrupt - uint32_t mmc_boot : 1; ///< Supports MMC Boot - uint32_t rst_n : 1; ///< Supports RST_n Pin Control (eMMC) - uint32_t ccs : 1; ///< Supports Command Completion Signal (CCS) for CE-ATA - uint32_t ccs_timeout : 1; ///< Supports Command Completion Signal (CCS) timeout for CE-ATA -} ARM_MCI_CAPABILITIES; - - -/** -\brief Access structure of the MCI Driver. -*/ -typedef struct _ARM_DRIVER_MCI { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_MCI_GetVersion : Get driver version. - ARM_MCI_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_MCI_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_MCI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_MCI_Initialize : Initialize MCI Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_MCI_Uninitialize : De-initialize MCI Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_MCI_PowerControl : Control MCI Interface Power. - int32_t (*CardPower) (uint32_t voltage); ///< Pointer to \ref ARM_MCI_CardPower : Set card power supply voltage. - int32_t (*ReadCD) (void); ///< Pointer to \ref ARM_MCI_ReadCD : Read Card Detect (CD) state. - int32_t (*ReadWP) (void); ///< Pointer to \ref ARM_MCI_ReadWP : Read Write Protect (WP) state. - int32_t (*SendCommand) (uint32_t cmd, - uint32_t arg, - uint32_t flags, - uint32_t *response); ///< Pointer to \ref ARM_MCI_SendCommand : Send Command to card and get the response. - int32_t (*SetupTransfer) (uint8_t *data, - uint32_t block_count, - uint32_t block_size, - uint32_t mode); ///< Pointer to \ref ARM_MCI_SetupTransfer : Setup data transfer operation. - int32_t (*AbortTransfer) (void); ///< Pointer to \ref ARM_MCI_AbortTransfer : Abort current data transfer. - int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_MCI_Control : Control MCI Interface. - ARM_MCI_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_MCI_GetStatus : Get MCI status. -} const ARM_DRIVER_MCI; - -#endif /* __DRIVER_MCI_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_NAND.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_NAND.h deleted file mode 100644 index a11a1ed6656..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_NAND.h +++ /dev/null @@ -1,403 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2014 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * - * $Date: 30. May 2014 - * $Revision: V2.01 - * - * Project: NAND Flash Driver definitions - * -------------------------------------------------------------------------- */ - -/* History: - * Version 2.01 - * Updated ARM_NAND_ECC_INFO structure and ARM_NAND_ECC_xxx definitions - * Version 2.00 - * New simplified driver: - * complexity moved to upper layer (command agnostic) - * Added support for: - * NV-DDR & NV-DDR2 Interface (ONFI specification) - * VCC, VCCQ and VPP Power Supply Control - * WP (Write Protect) Control - * Version 1.11 - * Changed prefix ARM_DRV -> ARM_DRIVER - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.00 - * Initial release - */ - -#ifndef __DRIVER_NAND_H -#define __DRIVER_NAND_H - -#include "Driver_Common.h" - -#define ARM_NAND_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,01) /* API version */ - - -/****** NAND Device Power *****/ -#define ARM_NAND_POWER_VCC_Pos 0 -#define ARM_NAND_POWER_VCC_Msk (0x07UL << ARM_NAND_POWER_VCC_Pos) -#define ARM_NAND_POWER_VCC_OFF (0x01UL << ARM_NAND_POWER_VCC_Pos) ///< VCC Power off -#define ARM_NAND_POWER_VCC_3V3 (0x02UL << ARM_NAND_POWER_VCC_Pos) ///< VCC = 3.3V -#define ARM_NAND_POWER_VCC_1V8 (0x03UL << ARM_NAND_POWER_VCC_Pos) ///< VCC = 1.8V -#define ARM_NAND_POWER_VCCQ_Pos 3 -#define ARM_NAND_POWER_VCCQ_Msk (0x07UL << ARM_NAND_POWER_VCCQ_Pos) -#define ARM_NAND_POWER_VCCQ_OFF (0x01UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ I/O Power off -#define ARM_NAND_POWER_VCCQ_3V3 (0x02UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 3.3V -#define ARM_NAND_POWER_VCCQ_1V8 (0x03UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 1.8V -#define ARM_NAND_POWER_VPP_OFF (1UL << 6) ///< VPP off -#define ARM_NAND_POWER_VPP_ON (1Ul << 7) ///< VPP on - - -/****** NAND Control Codes *****/ -#define ARM_NAND_BUS_MODE (0x01) ///< Set Bus Mode as specified with arg -#define ARM_NAND_BUS_DATA_WIDTH (0x02) ///< Set Bus Data Width as specified with arg -#define ARM_NAND_DRIVER_STRENGTH (0x03) ///< Set Driver Strength as specified with arg -#define ARM_NAND_DEVICE_READY_EVENT (0x04) ///< Generate \ref ARM_NAND_EVENT_DEVICE_READY; arg: 0=disabled (default), 1=enabled -#define ARM_NAND_DRIVER_READY_EVENT (0x05) ///< Generate \ref ARM_NAND_EVENT_DRIVER_READY; arg: 0=disabled (default), 1=enabled - -/*----- NAND Bus Mode (ONFI - Open NAND Flash Interface) -----*/ -#define ARM_NAND_BUS_INTERFACE_Pos 4 -#define ARM_NAND_BUS_INTERFACE_Msk (0x03UL << ARM_NAND_BUS_INTERFACE_Pos) -#define ARM_NAND_BUS_SDR (0x00UL << ARM_NAND_BUS_INTERFACE_Pos) ///< Data Interface: SDR (Single Data Rate) - Traditional interface (default) -#define ARM_NAND_BUS_DDR (0x01UL << ARM_NAND_BUS_INTERFACE_Pos) ///< Data Interface: NV-DDR (Double Data Rate) -#define ARM_NAND_BUS_DDR2 (0x02UL << ARM_NAND_BUS_INTERFACE_Pos) ///< Data Interface: NV-DDR2 (Double Data Rate) -#define ARM_NAND_BUS_TIMING_MODE_Pos 0 -#define ARM_NAND_BUS_TIMING_MODE_Msk (0x0FUL << ARM_NAND_BUS_TIMING_MODE_Pos) -#define ARM_NAND_BUS_TIMING_MODE_0 (0x00UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 0 (default) -#define ARM_NAND_BUS_TIMING_MODE_1 (0x01UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 1 -#define ARM_NAND_BUS_TIMING_MODE_2 (0x02UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 2 -#define ARM_NAND_BUS_TIMING_MODE_3 (0x03UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 3 -#define ARM_NAND_BUS_TIMING_MODE_4 (0x04UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 4 (SDR EDO capable) -#define ARM_NAND_BUS_TIMING_MODE_5 (0x05UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 5 (SDR EDO capable) -#define ARM_NAND_BUS_TIMING_MODE_6 (0x06UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 6 (NV-DDR2 only) -#define ARM_NAND_BUS_TIMING_MODE_7 (0x07UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 7 (NV-DDR2 only) -#define ARM_NAND_BUS_DDR2_DO_WCYC_Pos 8 -#define ARM_NAND_BUS_DDR2_DO_WCYC_Msk (0x0FUL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) -#define ARM_NAND_BUS_DDR2_DO_WCYC_0 (0x00UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 0 (default) -#define ARM_NAND_BUS_DDR2_DO_WCYC_1 (0x01UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 1 -#define ARM_NAND_BUS_DDR2_DO_WCYC_2 (0x02UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 2 -#define ARM_NAND_BUS_DDR2_DO_WCYC_4 (0x03UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 4 -#define ARM_NAND_BUS_DDR2_DI_WCYC_Pos 12 -#define ARM_NAND_BUS_DDR2_DI_WCYC_Msk (0x0FUL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) -#define ARM_NAND_BUS_DDR2_DI_WCYC_0 (0x00UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 0 (default) -#define ARM_NAND_BUS_DDR2_DI_WCYC_1 (0x01UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 1 -#define ARM_NAND_BUS_DDR2_DI_WCYC_2 (0x02UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 2 -#define ARM_NAND_BUS_DDR2_DI_WCYC_4 (0x03UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 4 -#define ARM_NAND_BUS_DDR2_VEN (1UL << 16) ///< DDR2 Enable external VREFQ as reference -#define ARM_NAND_BUS_DDR2_CMPD (1UL << 17) ///< DDR2 Enable complementary DQS (DQS_c) signal -#define ARM_NAND_BUS_DDR2_CMPR (1UL << 18) ///< DDR2 Enable complementary RE_n (RE_c) signal - -/*----- NAND Data Bus Width -----*/ -#define ARM_NAND_BUS_DATA_WIDTH_8 (0x00) ///< Bus Data Width: 8 bit (default) -#define ARM_NAND_BUS_DATA_WIDTH_16 (0x01) ///< Bus Data Width: 16 bit - -/*----- NAND Driver Strength (ONFI - Open NAND Flash Interface) -----*/ -#define ARM_NAND_DRIVER_STRENGTH_18 (0x00) ///< Driver Strength 2.0x = 18 Ohms -#define ARM_NAND_DRIVER_STRENGTH_25 (0x01) ///< Driver Strength 1.4x = 25 Ohms -#define ARM_NAND_DRIVER_STRENGTH_35 (0x02) ///< Driver Strength 1.0x = 35 Ohms (default) -#define ARM_NAND_DRIVER_STRENGTH_50 (0x03) ///< Driver Strength 0.7x = 50 Ohms - - -/****** NAND ECC for Read/Write Data Mode and Sequence Execution Code *****/ -#define ARM_NAND_ECC_INDEX_Pos 0 -#define ARM_NAND_ECC_INDEX_Msk (0xFFUL << ARM_NAND_ECC_INDEX_Pos) -#define ARM_NAND_ECC(n) ((n) & ARM_NAND_ECC_INDEX_Msk) ///< Select ECC -#define ARM_NAND_ECC0 (1UL << 8) ///< Use ECC0 of selected ECC -#define ARM_NAND_ECC1 (1UL << 9) ///< Use ECC1 of selected ECC - -/****** NAND Flag for Read/Write Data Mode and Sequence Execution Code *****/ -#define ARM_NAND_DRIVER_DONE_EVENT (1UL << 16) ///< Generate \ref ARM_NAND_EVENT_DRIVER_DONE - -/****** NAND Sequence Execution Code *****/ -#define ARM_NAND_CODE_SEND_CMD1 (1UL << 17) ///< Send Command 1 -#define ARM_NAND_CODE_SEND_ADDR_COL1 (1UL << 18) ///< Send Column Address 1 -#define ARM_NAND_CODE_SEND_ADDR_COL2 (1UL << 19) ///< Send Column Address 2 -#define ARM_NAND_CODE_SEND_ADDR_ROW1 (1UL << 20) ///< Send Row Address 1 -#define ARM_NAND_CODE_SEND_ADDR_ROW2 (1UL << 21) ///< Send Row Address 2 -#define ARM_NAND_CODE_SEND_ADDR_ROW3 (1UL << 22) ///< Send Row Address 3 -#define ARM_NAND_CODE_INC_ADDR_ROW (1UL << 23) ///< Auto-increment Row Address -#define ARM_NAND_CODE_WRITE_DATA (1UL << 24) ///< Write Data -#define ARM_NAND_CODE_SEND_CMD2 (1UL << 25) ///< Send Command 2 -#define ARM_NAND_CODE_WAIT_BUSY (1UL << 26) ///< Wait while R/Bn busy -#define ARM_NAND_CODE_READ_DATA (1UL << 27) ///< Read Data -#define ARM_NAND_CODE_SEND_CMD3 (1UL << 28) ///< Send Command 3 -#define ARM_NAND_CODE_READ_STATUS (1UL << 29) ///< Read Status byte and check FAIL bit (bit 0) - -/*----- NAND Sequence Execution Code: Command -----*/ -#define ARM_NAND_CODE_CMD1_Pos 0 -#define ARM_NAND_CODE_CMD1_Msk (0xFFUL << ARM_NAND_CODE_CMD1_Pos) -#define ARM_NAND_CODE_CMD2_Pos 8 -#define ARM_NAND_CODE_CMD2_Msk (0xFFUL << ARM_NAND_CODE_CMD2_Pos) -#define ARM_NAND_CODE_CMD3_Pos 16 -#define ARM_NAND_CODE_CMD3_Msk (0xFFUL << ARM_NAND_CODE_CMD3_Pos) - -/*----- NAND Sequence Execution Code: Column Address -----*/ -#define ARM_NAND_CODE_ADDR_COL1_Pos 0 -#define ARM_NAND_CODE_ADDR_COL1_Msk (0xFFUL << ARM_NAND_CODE_ADDR_COL1_Pos) -#define ARM_NAND_CODE_ADDR_COL2_Pos 8 -#define ARM_NAND_CODE_ADDR_COL2_Msk (0xFFUL << ARM_NAND_CODE_ADDR_COL2_Pos) - -/*----- NAND Sequence Execution Code: Row Address -----*/ -#define ARM_NAND_CODE_ADDR_ROW1_Pos 0 -#define ARM_NAND_CODE_ADDR_ROW1_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW1_Pos) -#define ARM_NAND_CODE_ADDR_ROW2_Pos 8 -#define ARM_NAND_CODE_ADDR_ROW2_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW2_Pos) -#define ARM_NAND_CODE_ADDR_ROW3_Pos 16 -#define ARM_NAND_CODE_ADDR_ROW3_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW3_Pos) - - -/****** NAND specific error codes *****/ -#define ARM_NAND_ERROR_ECC (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< ECC generation/correction failed - - -/** -\brief NAND ECC (Error Correction Code) Information -*/ -typedef struct _ARM_NAND_ECC_INFO { - uint32_t type : 2; ///< Type: 1=ECC0 over Data, 2=ECC0 over Data+Spare, 3=ECC0 over Data and ECC1 over Spare - uint32_t page_layout : 1; ///< Page layout: 0=|Data0|Spare0|...|DataN-1|SpareN-1|, 1=|Data0|...|DataN-1|Spare0|...|SpareN-1| - uint32_t page_count : 3; ///< Number of virtual pages: N = 2 ^ page_count - uint32_t page_size : 4; ///< Virtual Page size (Data+Spare): 0=512+16, 1=1k+32, 2=2k+64, 3=4k+128, 4=8k+256, 8=512+28, 9=1k+56, 10=2k+112, 11=4k+224, 12=8k+448 - uint32_t reserved : 14; ///< Reserved (must be zero) - uint32_t correctable_bits : 8; ///< Number of correctable bits (based on 512 byte codeword size) - uint16_t codeword_size [2]; ///< Number of bytes over which ECC is calculated - uint16_t ecc_size [2]; ///< ECC size in bytes (rounded up) - uint16_t ecc_offset [2]; ///< ECC offset in bytes (where ECC starts in Spare area) -} ARM_NAND_ECC_INFO; - - -/** -\brief NAND Status -*/ -typedef struct _ARM_NAND_STATUS { - uint32_t busy : 1; ///< Driver busy flag - uint32_t ecc_error : 1; ///< ECC error detected (cleared on next Read/WriteData or ExecuteSequence) -} ARM_NAND_STATUS; - - -/****** NAND Event *****/ -#define ARM_NAND_EVENT_DEVICE_READY (1UL << 0) ///< Device Ready: R/Bn rising edge -#define ARM_NAND_EVENT_DRIVER_READY (1UL << 1) ///< Driver Ready -#define ARM_NAND_EVENT_DRIVER_DONE (1UL << 2) ///< Driver operation done -#define ARM_NAND_EVENT_ECC_ERROR (1UL << 3) ///< ECC could not correct data - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_NAND_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION -*/ -/** - \fn ARM_NAND_CAPABILITIES ARM_NAND_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_NAND_CAPABILITIES -*/ -/** - \fn int32_t ARM_NAND_Initialize (ARM_NAND_SignalEvent_t cb_event) - \brief Initialize the NAND Interface. - \param[in] cb_event Pointer to \ref ARM_NAND_SignalEvent - \return \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_Uninitialize (void) - \brief De-initialize the NAND Interface. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_PowerControl (ARM_POWER_STATE state) - \brief Control the NAND interface power. - \param[in] state Power state - \return \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_DevicePower (uint32_t voltage) - \brief Set device power supply voltage. - \param[in] voltage NAND Device supply voltage - \return \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_WriteProtect (uint32_t dev_num, bool enable) - \brief Control WPn (Write Protect). - \param[in] dev_num Device number - \param[in] enable - - \b false Write Protect off - - \b true Write Protect on - \return \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_ChipEnable (uint32_t dev_num, bool enable) - \brief Control CEn (Chip Enable). - \param[in] dev_num Device number - \param[in] enable - - \b false Chip Enable off - - \b true Chip Enable on - \return \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_GetDeviceBusy (uint32_t dev_num) - \brief Get Device Busy pin state. - \param[in] dev_num Device number - \return 1=busy, 0=not busy, or error -*/ -/** - \fn int32_t ARM_NAND_SendCommand (uint32_t dev_num, uint8_t cmd) - \brief Send command to NAND device. - \param[in] dev_num Device number - \param[in] cmd Command - \return \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_SendAddress (uint32_t dev_num, uint8_t addr) - \brief Send address to NAND device. - \param[in] dev_num Device number - \param[in] addr Address - \return \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_ReadData (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode) - \brief Read data from NAND device. - \param[in] dev_num Device number - \param[out] data Pointer to buffer for data to read from NAND device - \param[in] cnt Number of data items to read - \param[in] mode Operation mode - \return number of data items read or \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_WriteData (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode) - \brief Write data to NAND device. - \param[in] dev_num Device number - \param[out] data Pointer to buffer with data to write to NAND device - \param[in] cnt Number of data items to write - \param[in] mode Operation mode - \return number of data items written or \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_ExecuteSequence (uint32_t dev_num, uint32_t code, uint32_t cmd, - uint32_t addr_col, uint32_t addr_row, - void *data, uint32_t data_cnt, - uint8_t *status, uint32_t *count) - \brief Execute sequence of operations. - \param[in] dev_num Device number - \param[in] code Sequence code - \param[in] cmd Command(s) - \param[in] addr_col Column address - \param[in] addr_row Row address - \param[in,out] data Pointer to data to be written or read - \param[in] data_cnt Number of data items in one iteration - \param[out] status Pointer to status read - \param[in,out] count Number of iterations - \return \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_AbortSequence (uint32_t dev_num) - \brief Abort sequence execution. - \param[in] dev_num Device number - \return \ref execution_status -*/ -/** - \fn int32_t ARM_NAND_Control (uint32_t dev_num, uint32_t control, uint32_t arg) - \brief Control NAND Interface. - \param[in] dev_num Device number - \param[in] control Operation - \param[in] arg Argument of operation - \return \ref execution_status -*/ -/** - \fn ARM_NAND_STATUS ARM_NAND_GetStatus (uint32_t dev_num) - \brief Get NAND status. - \param[in] dev_num Device number - \return NAND status \ref ARM_NAND_STATUS -*/ -/** - \fn int32_t ARM_NAND_InquireECC (int32_t index, ARM_NAND_ECC_INFO *info) - \brief Inquire about available ECC. - \param[in] index Device number - \param[out] info Pointer to ECC information \ref ARM_NAND_ECC_INFO retrieved - \return \ref execution_status -*/ - -/** - \fn void ARM_NAND_SignalEvent (uint32_t dev_num, uint32_t event) - \brief Signal NAND event. - \param[in] dev_num Device number - \param[in] event Event notification mask - \return none -*/ - -typedef void (*ARM_NAND_SignalEvent_t) (uint32_t dev_num, uint32_t event); ///< Pointer to \ref ARM_NAND_SignalEvent : Signal NAND Event. - - -/** -\brief NAND Driver Capabilities. -*/ -typedef struct _ARM_NAND_CAPABILITIES { - uint32_t event_device_ready : 1; ///< Signal Device Ready event (R/Bn rising edge) - uint32_t reentrant_operation : 1; ///< Supports re-entrant operation (SendCommand/Address, Read/WriteData) - uint32_t sequence_operation : 1; ///< Supports Sequence operation (ExecuteSequence, AbortSequence) - uint32_t vcc : 1; ///< Supports VCC Power Supply Control - uint32_t vcc_1v8 : 1; ///< Supports 1.8 VCC Power Supply - uint32_t vccq : 1; ///< Supports VCCQ I/O Power Supply Control - uint32_t vccq_1v8 : 1; ///< Supports 1.8 VCCQ I/O Power Supply - uint32_t vpp : 1; ///< Supports VPP High Voltage Power Supply Control - uint32_t wp : 1; ///< Supports WPn (Write Protect) Control - uint32_t ce_lines : 4; ///< Number of CEn (Chip Enable) lines: ce_lines + 1 - uint32_t ce_manual : 1; ///< Supports manual CEn (Chip Enable) Control - uint32_t rb_monitor : 1; ///< Supports R/Bn (Ready/Busy) Monitoring - uint32_t data_width_16 : 1; ///< Supports 16-bit data - uint32_t ddr : 1; ///< Supports NV-DDR Data Interface (ONFI) - uint32_t ddr2 : 1; ///< Supports NV-DDR2 Data Interface (ONFI) - uint32_t sdr_timing_mode : 3; ///< Fastest (highest) SDR Timing Mode supported (ONFI) - uint32_t ddr_timing_mode : 3; ///< Fastest (highest) NV_DDR Timing Mode supported (ONFI) - uint32_t ddr2_timing_mode : 3; ///< Fastest (highest) NV_DDR2 Timing Mode supported (ONFI) - uint32_t driver_strength_18 : 1; ///< Supports Driver Strength 2.0x = 18 Ohms - uint32_t driver_strength_25 : 1; ///< Supports Driver Strength 1.4x = 25 Ohms - uint32_t driver_strength_50 : 1; ///< Supports Driver Strength 0.7x = 50 Ohms -} ARM_NAND_CAPABILITIES; - - -/** -\brief Access structure of the NAND Driver. -*/ -typedef struct _ARM_DRIVER_NAND { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_NAND_GetVersion : Get driver version. - ARM_NAND_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_NAND_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_NAND_SignalEvent_t cb_event); ///< Pointer to \ref ARM_NAND_Initialize : Initialize NAND Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_NAND_Uninitialize : De-initialize NAND Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_NAND_PowerControl : Control NAND Interface Power. - int32_t (*DevicePower) (uint32_t voltage); ///< Pointer to \ref ARM_NAND_DevicePower : Set device power supply voltage. - int32_t (*WriteProtect) (uint32_t dev_num, bool enable); ///< Pointer to \ref ARM_NAND_WriteProtect : Control WPn (Write Protect). - int32_t (*ChipEnable) (uint32_t dev_num, bool enable); ///< Pointer to \ref ARM_NAND_ChipEnable : Control CEn (Chip Enable). - int32_t (*GetDeviceBusy) (uint32_t dev_num); ///< Pointer to \ref ARM_NAND_GetDeviceBusy : Get Device Busy pin state. - int32_t (*SendCommand) (uint32_t dev_num, uint8_t cmd); ///< Pointer to \ref ARM_NAND_SendCommand : Send command to NAND device. - int32_t (*SendAddress) (uint32_t dev_num, uint8_t addr); ///< Pointer to \ref ARM_NAND_SendAddress : Send address to NAND device. - int32_t (*ReadData) (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode); ///< Pointer to \ref ARM_NAND_ReadData : Read data from NAND device. - int32_t (*WriteData) (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode); ///< Pointer to \ref ARM_NAND_WriteData : Write data to NAND device. - int32_t (*ExecuteSequence)(uint32_t dev_num, uint32_t code, uint32_t cmd, - uint32_t addr_col, uint32_t addr_row, - void *data, uint32_t data_cnt, - uint8_t *status, uint32_t *count); ///< Pointer to \ref ARM_NAND_ExecuteSequence : Execute sequence of operations. - int32_t (*AbortSequence) (uint32_t dev_num); ///< Pointer to \ref ARM_NAND_AbortSequence : Abort sequence execution. - int32_t (*Control) (uint32_t dev_num, uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_NAND_Control : Control NAND Interface. - ARM_NAND_STATUS (*GetStatus) (uint32_t dev_num); ///< Pointer to \ref ARM_NAND_GetStatus : Get NAND status. - int32_t (*InquireECC) ( int32_t index, ARM_NAND_ECC_INFO *info); ///< Pointer to \ref ARM_NAND_InquireECC : Inquire about available ECC. -} const ARM_DRIVER_NAND; - -#endif /* __DRIVER_NAND_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_SAI.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_SAI.h deleted file mode 100644 index 52c54d5c747..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_SAI.h +++ /dev/null @@ -1,298 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2014 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * - * $Date: 9. Dec 2014 - * $Revision: V1.00 - * - * Project: SAI (Serial Audio Interface) Driver definitions - * -------------------------------------------------------------------------- */ - -/* History: - * Version 1.00 - * Initial release - */ - -#ifndef __DRIVER_SAI_H -#define __DRIVER_SAI_H - -#include "Driver_Common.h" - -#define ARM_SAI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,00) /* API version */ - - -/****** SAI Control Codes *****/ - -#define ARM_SAI_CONTROL_Msk (0xFFU) -#define ARM_SAI_CONFIGURE_TX (0x01U) ///< Configure Transmitter; arg1 and arg2 provide additional configuration -#define ARM_SAI_CONFIGURE_RX (0x02U) ///< Configure Receiver; arg1 and arg2 provide additional configuration -#define ARM_SAI_CONTROL_TX (0x03U) ///< Control Transmitter; arg1.0: 0=disable (default), 1=enable; arg1.1: mute -#define ARM_SAI_CONTROL_RX (0x04U) ///< Control Receiver; arg1.0: 0=disable (default), 1=enable -#define ARM_SAI_MASK_SLOTS_TX (0x05U) ///< Mask Transmitter slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default -#define ARM_SAI_MASK_SLOTS_RX (0x06U) ///< Mask Receiver slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default -#define ARM_SAI_ABORT_SEND (0x07U) ///< Abort \ref ARM_SAI_Send -#define ARM_SAI_ABORT_RECEIVE (0x08U) ///< Abort \ref ARM_SAI_Receive - -/*----- SAI Control Codes: Configuration Parameters: Mode -----*/ -#define ARM_SAI_MODE_Pos 8 -#define ARM_SAI_MODE_Msk (1U << ARM_SAI_MODE_Pos) -#define ARM_SAI_MODE_MASTER (1U << ARM_SAI_MODE_Pos) ///< Master Mode -#define ARM_SAI_MODE_SLAVE (0U << ARM_SAI_MODE_Pos) ///< Slave Mode (default) - -/*----- SAI Control Codes: Configuration Parameters: Synchronization -----*/ -#define ARM_SAI_SYNCHRONIZATION_Pos 9 -#define ARM_SAI_SYNCHRONIZATION_Msk (1U << ARM_SAI_SYNCHRONIZATION_Pos) -#define ARM_SAI_ASYNCHRONOUS (0U << ARM_SAI_SYNCHRONIZATION_Pos) ///< Asynchronous (default) -#define ARM_SAI_SYNCHRONOUS (1U << ARM_SAI_SYNCHRONIZATION_Pos) ///< Synchronous - -/*----- SAI Control Codes: Configuration Parameters: Protocol -----*/ -#define ARM_SAI_PROTOCOL_Pos 10 -#define ARM_SAI_PROTOCOL_Msk (7U << ARM_SAI_PROTOCOL_Pos) -#define ARM_SAI_PROTOCOL_USER (0U << ARM_SAI_PROTOCOL_Pos) ///< User defined (default) -#define ARM_SAI_PROTOCOL_I2S (1U << ARM_SAI_PROTOCOL_Pos) ///< I2S -#define ARM_SAI_PROTOCOL_MSB_JUSTIFIED (2U << ARM_SAI_PROTOCOL_Pos) ///< MSB (left) justified -#define ARM_SAI_PROTOCOL_LSB_JUSTIFIED (3U << ARM_SAI_PROTOCOL_Pos) ///< LSB (right) justified -#define ARM_SAI_PROTOCOL_PCM_SHORT (4U << ARM_SAI_PROTOCOL_Pos) ///< PCM with short frame -#define ARM_SAI_PROTOCOL_PCM_LONG (5U << ARM_SAI_PROTOCOL_Pos) ///< PCM with long frame -#define ARM_SAI_PROTOCOL_AC97 (6U << ARM_SAI_PROTOCOL_Pos) ///< AC'97 - -/*----- SAI Control Codes: Configuration Parameters: Data Size -----*/ -#define ARM_SAI_DATA_SIZE_Pos 13 -#define ARM_SAI_DATA_SIZE_Msk (0x1FU << ARM_SAI_DATA_SIZE_Pos) -#define ARM_SAI_DATA_SIZE(n) ((((n)-1)&0x1FU) << ARM_SAI_DATA_SIZE_Pos) ///< Data size in bits (8..32) - -/*----- SAI Control Codes: Configuration Parameters: Bit Order -----*/ -#define ARM_SAI_BIT_ORDER_Pos 18 -#define ARM_SAI_BIT_ORDER_Msk (1U << ARM_SAI_BIT_ORDER_Pos) -#define ARM_SAI_MSB_FIRST (0U << ARM_SAI_BIT_ORDER_Pos) ///< Data is transferred with MSB first (default) -#define ARM_SAI_LSB_FIRST (1U << ARM_SAI_BIT_ORDER_Pos) ///< Data is transferred with LSB first; User Protocol only (ignored otherwise) - -/*----- SAI Control Codes: Configuration Parameters: Mono Mode -----*/ -#define ARM_SAI_MONO_MODE (1U << 19) ///< Mono Mode (only for I2S, MSB/LSB justified) - -/*----- SAI Control Codes:Configuration Parameters: Companding -----*/ -#define ARM_SAI_COMPANDING_Pos 20 -#define ARM_SAI_COMPANDING_Msk (3U << ARM_SAI_COMPANDING_Pos) -#define ARM_SAI_COMPANDING_NONE (0U << ARM_SAI_COMPANDING_Pos) ///< No compading (default) -#define ARM_SAI_COMPANDING_A_LAW (2U << ARM_SAI_COMPANDING_Pos) ///< A-Law companding -#define ARM_SAI_COMPANDING_U_LAW (3U << ARM_SAI_COMPANDING_Pos) ///< u-Law companding - -/*----- SAI Control Codes: Configuration Parameters: Clock Polarity -----*/ -#define ARM_SAI_CLOCK_POLARITY_Pos 23 -#define ARM_SAI_CLOCK_POLARITY_Msk (1U << ARM_SAI_CLOCK_POLARITY_Pos) -#define ARM_SAI_CLOCK_POLARITY_0 (0U << ARM_SAI_CLOCK_POLARITY_Pos) ///< Drive on falling edge, Capture on rising edge (default) -#define ARM_SAI_CLOCK_POLARITY_1 (1U << ARM_SAI_CLOCK_POLARITY_Pos) ///< Drive on rising edge, Capture on falling edge - -/*----- SAI Control Codes: Configuration Parameters: Master Clock Pin -----*/ -#define ARM_SAI_MCLK_PIN_Pos 24 -#define ARM_SAI_MCLK_PIN_Msk (3U << ARM_SAI_MCLK_PIN_Pos) -#define ARM_SAI_MCLK_PIN_INACTIVE (0U << ARM_SAI_MCLK_PIN_Pos) ///< MCLK not used (default) -#define ARM_SAI_MCLK_PIN_OUTPUT (1U << ARM_SAI_MCLK_PIN_Pos) ///< MCLK is output (Master only) -#define ARM_SAI_MCLK_PIN_INPUT (2U << ARM_SAI_MCLK_PIN_Pos) ///< MCLK is input (Master only) - - -/****** SAI Configuration (arg1) *****/ - -/*----- SAI Configuration (arg1): Frame Length -----*/ -#define ARM_SAI_FRAME_LENGTH_Pos 0 -#define ARM_SAI_FRAME_LENGTH_Msk (0x3FFU << ARM_SAI_FRAME_LENGTH_Pos) -#define ARM_SAI_FRAME_LENGTH(n) ((((n)-1)&0x3FFU) << ARM_SAI_FRAME_LENGTH_Pos) ///< Frame length in bits (8..1024); default depends on protocol and data - -/*----- SAI Configuration (arg1): Frame Sync Width -----*/ -#define ARM_SAI_FRAME_SYNC_WIDTH_Pos 10 -#define ARM_SAI_FRAME_SYNC_WIDTH_Msk (0xFFU << ARM_SAI_FRAME_SYNC_WIDTH_Pos) -#define ARM_SAI_FRAME_SYNC_WIDTH(n) ((((n)-1)&0xFFU) << ARM_SAI_FRAME_SYNC_WIDTH_Pos) ///< Frame Sync width in bits (1..256); default=1; User Protocol only (ignored otherwise) - -/*----- SAI Configuration (arg1): Frame Sync Polarity -----*/ -#define ARM_SAI_FRAME_SYNC_POLARITY_Pos 18 -#define ARM_SAI_FRAME_SYNC_POLARITY_Msk (1U << ARM_SAI_FRAME_SYNC_POLARITY_Pos) -#define ARM_SAI_FRAME_SYNC_POLARITY_HIGH (0U << ARM_SAI_FRAME_SYNC_POLARITY_Pos) ///< Frame Sync is active high (default); User Protocol only (ignored otherwise) -#define ARM_SAI_FRAME_SYNC_POLARITY_LOW (1U << ARM_SAI_FRAME_SYNC_POLARITY_Pos) ///< Frame Sync is active low; User Protocol only (ignored otherwise) - -/*----- SAI Configuration (arg1): Frame Sync Early -----*/ -#define ARM_SAI_FRAME_SYNC_EARLY (1U << 19) ///< Frame Sync one bit before the first bit of the frame; User Protocol only (ignored otherwise) - -/*----- SAI Configuration (arg1): Slot Count -----*/ -#define ARM_SAI_SLOT_COUNT_Pos 20 -#define ARM_SAI_SLOT_COUNT_Msk (0x1FU << ARM_SAI_SLOT_COUNT_Pos) -#define ARM_SAI_SLOT_COUNT(n) ((((n)-1)&0x1FU) << ARM_SAI_SLOT_COUNT_Pos) ///< Number of slots in frame (1..32); default=1; User Protocol only (ignored otherwise) - -/*----- SAI Configuration (arg1): Slot Size -----*/ -#define ARM_SAI_SLOT_SIZE_Pos 25 -#define ARM_SAI_SLOT_SIZE_Msk (3U << ARM_SAI_SLOT_SIZE_Pos) -#define ARM_SAI_SLOT_SIZE_DEFAULT (0U << ARM_SAI_SLOT_SIZE_Pos) ///< Slot size is equal to data size (default) -#define ARM_SAI_SLOT_SIZE_16 (1U << ARM_SAI_SLOT_SIZE_Pos) ///< Slot size = 16 bits; User Protocol only (ignored otherwise) -#define ARM_SAI_SLOT_SIZE_32 (3U << ARM_SAI_SLOT_SIZE_Pos) ///< Slot size = 32 bits; User Protocol only (ignored otherwise) - -/*----- SAI Configuration (arg1): Slot Offset -----*/ -#define ARM_SAI_SLOT_OFFSET_Pos 27 -#define ARM_SAI_SLOT_OFFSET_Msk (0x1FU << ARM_SAI_SLOT_OFFSET_Pos) -#define ARM_SAI_SLOT_OFFSET(n) (((n)&0x1FU) << ARM_SAI_SLOT_OFFSET_Pos) ///< Offset of first data bit in slot (0..31); default=0; User Protocol only (ignored otherwise) - -/****** SAI Configuration (arg2) *****/ - -/*----- SAI Control Codes: Configuration Parameters: Audio Frequency (Master only) -----*/ -#define ARM_SAI_AUDIO_FREQ_Msk (0x0FFFFFU) ///< Audio frequency mask - -/*----- SAI Control Codes: Configuration Parameters: Master Clock Prescaler (Master only and MCLK Pin) -----*/ -#define ARM_SAI_MCLK_PRESCALER_Pos 20 -#define ARM_SAI_MCLK_PRESCALER_Msk (0xFFFU << ARM_SAI_MCLK_PRESCALER_Pos) -#define ARM_SAI_MCLK_PRESCALER(n) ((((n)-1)&0xFFFU) << ARM_SAI_MCLK_PRESCALER_Pos) ///< MCLK prescaler; Audio_frequency = MCLK/n; n = 1..4096 (default=1) - - -/****** SAI specific error codes *****/ -#define ARM_SAI_ERROR_SYNCHRONIZATION (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Synchronization not supported -#define ARM_SAI_ERROR_PROTOCOL (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified Protocol not supported -#define ARM_SAI_ERROR_DATA_SIZE (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified Data size not supported -#define ARM_SAI_ERROR_BIT_ORDER (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Bit order not supported -#define ARM_SAI_ERROR_MONO_MODE (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified Mono mode not supported -#define ARM_SAI_ERROR_COMPANDING (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Companding not supported -#define ARM_SAI_ERROR_CLOCK_POLARITY (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock polarity not supported -#define ARM_SAI_ERROR_AUDIO_FREQ (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Audio frequency not supported -#define ARM_SAI_ERROR_MCLK_PIN (ARM_DRIVER_ERROR_SPECIFIC - 9) ///< Specified MCLK Pin setting not supported -#define ARM_SAI_ERROR_MCLK_PRESCALER (ARM_DRIVER_ERROR_SPECIFIC - 10) ///< Specified MCLK Prescaler not supported -#define ARM_SAI_ERROR_FRAME_LENGHT (ARM_DRIVER_ERROR_SPECIFIC - 11) ///< Specified Frame length not supported -#define ARM_SAI_ERROR_FRAME_SYNC_WIDTH (ARM_DRIVER_ERROR_SPECIFIC - 12) ///< Specified Frame Sync width not supported -#define ARM_SAI_ERROR_FRAME_SYNC_POLARITY (ARM_DRIVER_ERROR_SPECIFIC - 13) ///< Specified Frame Sync polarity not supported -#define ARM_SAI_ERROR_FRAME_SYNC_EARLY (ARM_DRIVER_ERROR_SPECIFIC - 14) ///< Specified Frame Sync early not supported -#define ARM_SAI_ERROR_SLOT_COUNT (ARM_DRIVER_ERROR_SPECIFIC - 15) ///< Specified Slot count not supported -#define ARM_SAI_ERROR_SLOT_SIZE (ARM_DRIVER_ERROR_SPECIFIC - 16) ///< Specified Slot size not supported -#define ARM_SAI_ERROR_SLOT_OFFESET (ARM_DRIVER_ERROR_SPECIFIC - 17) ///< Specified Slot offset not supported - - -/** -\brief SAI Status -*/ -typedef struct _ARM_SAI_STATUS { - uint32_t tx_busy : 1; ///< Transmitter busy flag - uint32_t rx_busy : 1; ///< Receiver busy flag - uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation) - uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation) - uint32_t frame_error : 1; ///< Sync Frame error detected (cleared on start of next send/receive operation) -} ARM_SAI_STATUS; - - -/****** SAI Event *****/ -#define ARM_SAI_EVENT_SEND_COMPLETE (1U << 0) ///< Send completed -#define ARM_SAI_EVENT_RECEIVE_COMPLETE (1U << 1) ///< Receive completed -#define ARM_SAI_EVENT_TX_UNDERFLOW (1U << 2) ///< Transmit data not available -#define ARM_SAI_EVENT_RX_OVERFLOW (1U << 3) ///< Receive data overflow -#define ARM_SAI_EVENT_FRAME_ERROR (1U << 4) ///< Sync Frame error in Slave mode (optional) - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_SAI_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION - - \fn ARM_SAI_CAPABILITIES ARM_SAI_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_SAI_CAPABILITIES - - \fn int32_t ARM_SAI_Initialize (ARM_SAI_SignalEvent_t cb_event) - \brief Initialize SAI Interface. - \param[in] cb_event Pointer to \ref ARM_SAI_SignalEvent - \return \ref execution_status - - \fn int32_t ARM_SAI_Uninitialize (void) - \brief De-initialize SAI Interface. - \return \ref execution_status - - \fn int32_t ARM_SAI_PowerControl (ARM_POWER_STATE state) - \brief Control SAI Interface Power. - \param[in] state Power state - \return \ref execution_status - - \fn int32_t ARM_SAI_Send (const void *data, uint32_t num) - \brief Start sending data to SAI transmitter. - \param[in] data Pointer to buffer with data to send to SAI transmitter - \param[in] num Number of data items to send - \return \ref execution_status - - \fn int32_t ARM_SAI_Receive (void *data, uint32_t num) - \brief Start receiving data from SAI receiver. - \param[out] data Pointer to buffer for data to receive from SAI receiver - \param[in] num Number of data items to receive - \return \ref execution_status - - \fn uint32_t ARM_SAI_GetTxCount (void) - \brief Get transmitted data count. - \return number of data items transmitted - - \fn uint32_t ARM_SAI_GetRxCount (void) - \brief Get received data count. - \return number of data items received - - \fn int32_t ARM_SAI_Control (uint32_t control, uint32_t arg1, uint32_t arg2) - \brief Control SAI Interface. - \param[in] control Operation - \param[in] arg1 Argument 1 of operation (optional) - \param[in] arg2 Argument 2 of operation (optional) - \return common \ref execution_status and driver specific \ref sai_execution_status - - \fn ARM_SAI_STATUS ARM_SAI_GetStatus (void) - \brief Get SAI status. - \return SAI status \ref ARM_SAI_STATUS - - \fn void ARM_SAI_SignalEvent (uint32_t event) - \brief Signal SAI Events. - \param[in] event \ref SAI_events notification mask - \return none -*/ - -typedef void (*ARM_SAI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_SAI_SignalEvent : Signal SAI Event. - - -/** -\brief SAI Driver Capabilities. -*/ -typedef struct _ARM_SAI_CAPABILITIES { - uint32_t asynchronous : 1; ///< supports asynchronous Transmit/Receive - uint32_t synchronous : 1; ///< supports synchronous Transmit/Receive - uint32_t protocol_user : 1; ///< supports user defined Protocol - uint32_t protocol_i2s : 1; ///< supports I2S Protocol - uint32_t protocol_justified : 1; ///< supports MSB/LSB justified Protocol - uint32_t protocol_pcm : 1; ///< supports PCM short/long frame Protocol - uint32_t protocol_ac97 : 1; ///< supports AC'97 Protocol - uint32_t mono_mode : 1; ///< supports Mono mode - uint32_t companding : 1; ///< supports Companding - uint32_t mclk_pin : 1; ///< supports MCLK (Master Clock) pin - uint32_t event_frame_error : 1; ///< supports Frame error event: \ref ARM_SAI_EVENT_FRAME_ERROR -} ARM_SAI_CAPABILITIES; - - -/** -\brief Access structure of the SAI Driver. -*/ -typedef struct _ARM_DRIVER_SAI { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_SAI_GetVersion : Get driver version. - ARM_SAI_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_SAI_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_SAI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_SAI_Initialize : Initialize SAI Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_SAI_Uninitialize : De-initialize SAI Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_SAI_PowerControl : Control SAI Interface Power. - int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_SAI_Send : Start sending data to SAI Interface. - int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_SAI_Receive : Start receiving data from SAI Interface. - uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_SAI_GetTxCount : Get transmitted data count. - uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_SAI_GetRxCount : Get received data count. - int32_t (*Control) (uint32_t control, uint32_t arg1, uint32_t arg2); ///< Pointer to \ref ARM_SAI_Control : Control SAI Interface. - ARM_SAI_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_SAI_GetStatus : Get SAI status. -} const ARM_DRIVER_SAI; - -#endif /* __DRIVER_SAI_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_SPI.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_SPI.h deleted file mode 100644 index 28bd10af170..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_SPI.h +++ /dev/null @@ -1,237 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2014 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * - * $Date: 17. Apr 2014 - * $Revision: V2.01 - * - * Project: SPI (Serial Peripheral Interface) Driver definitions - * -------------------------------------------------------------------------- */ - -/* History: - * Version 2.01 - * Renamed status flag "tx_rx_busy" to "busy" - * Version 2.00 - * New simplified driver: - * complexity moved to upper layer (especially data handling) - * more unified API for different communication interfaces - * Added: - * Slave Mode - * Half-duplex Modes - * Configurable number of data bits - * Support for TI Mode and Microwire - * Changed prefix ARM_DRV -> ARM_DRIVER - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.01 - * Added "send_done_event" to Capabilities - * Version 1.00 - * Initial release - */ - -#ifndef __DRIVER_SPI_H -#define __DRIVER_SPI_H - -#include "Driver_Common.h" - -#define ARM_SPI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,00) /* API version */ - - -/****** SPI Control Codes *****/ - -#define ARM_SPI_CONTROL_Pos 0 -#define ARM_SPI_CONTROL_Msk (0xFFUL << ARM_SPI_CONTROL_Pos) - -/*----- SPI Control Codes: Mode -----*/ -#define ARM_SPI_MODE_INACTIVE (0x00UL << ARM_SPI_CONTROL_Pos) ///< SPI Inactive -#define ARM_SPI_MODE_MASTER (0x01UL << ARM_SPI_CONTROL_Pos) ///< SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps -#define ARM_SPI_MODE_SLAVE (0x02UL << ARM_SPI_CONTROL_Pos) ///< SPI Slave (Output on MISO, Input on MOSI) -#define ARM_SPI_MODE_MASTER_SIMPLEX (0x03UL << ARM_SPI_CONTROL_Pos) ///< SPI Master (Output/Input on MOSI); arg = Bus Speed in bps -#define ARM_SPI_MODE_SLAVE_SIMPLEX (0x04UL << ARM_SPI_CONTROL_Pos) ///< SPI Slave (Output/Input on MISO) - -/*----- SPI Control Codes: Mode Parameters: Frame Format -----*/ -#define ARM_SPI_FRAME_FORMAT_Pos 8 -#define ARM_SPI_FRAME_FORMAT_Msk (7UL << ARM_SPI_FRAME_FORMAT_Pos) -#define ARM_SPI_CPOL0_CPHA0 (0UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 0, Clock Phase 0 (default) -#define ARM_SPI_CPOL0_CPHA1 (1UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 0, Clock Phase 1 -#define ARM_SPI_CPOL1_CPHA0 (2UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 1, Clock Phase 0 -#define ARM_SPI_CPOL1_CPHA1 (3UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 1, Clock Phase 1 -#define ARM_SPI_TI_SSI (4UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Texas Instruments Frame Format -#define ARM_SPI_MICROWIRE (5UL << ARM_SPI_FRAME_FORMAT_Pos) ///< National Microwire Frame Format - -/*----- SPI Control Codes: Mode Parameters: Data Bits -----*/ -#define ARM_SPI_DATA_BITS_Pos 12 -#define ARM_SPI_DATA_BITS_Msk (0x3FUL << ARM_SPI_DATA_BITS_Pos) -#define ARM_SPI_DATA_BITS(n) (((n) & 0x3F) << ARM_SPI_DATA_BITS_Pos) ///< Number of Data bits - -/*----- SPI Control Codes: Mode Parameters: Bit Order -----*/ -#define ARM_SPI_BIT_ORDER_Pos 18 -#define ARM_SPI_BIT_ORDER_Msk (1UL << ARM_SPI_BIT_ORDER_Pos) -#define ARM_SPI_MSB_LSB (0UL << ARM_SPI_BIT_ORDER_Pos) ///< SPI Bit order from MSB to LSB (default) -#define ARM_SPI_LSB_MSB (1UL << ARM_SPI_BIT_ORDER_Pos) ///< SPI Bit order from LSB to MSB - -/*----- SPI Control Codes: Mode Parameters: Slave Select Mode -----*/ -#define ARM_SPI_SS_MASTER_MODE_Pos 19 -#define ARM_SPI_SS_MASTER_MODE_Msk (3UL << ARM_SPI_SS_MASTER_MODE_Pos) -#define ARM_SPI_SS_MASTER_UNUSED (0UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Not used (default) -#define ARM_SPI_SS_MASTER_SW (1UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Software controlled -#define ARM_SPI_SS_MASTER_HW_OUTPUT (2UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware controlled Output -#define ARM_SPI_SS_MASTER_HW_INPUT (3UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware monitored Input -#define ARM_SPI_SS_SLAVE_MODE_Pos 21 -#define ARM_SPI_SS_SLAVE_MODE_Msk (1UL << ARM_SPI_SS_SLAVE_MODE_Pos) -#define ARM_SPI_SS_SLAVE_HW (0UL << ARM_SPI_SS_SLAVE_MODE_Pos) ///< SPI Slave Select when Slave: Hardware monitored (default) -#define ARM_SPI_SS_SLAVE_SW (1UL << ARM_SPI_SS_SLAVE_MODE_Pos) ///< SPI Slave Select when Slave: Software controlled - - -/*----- SPI Control Codes: Miscellaneous Controls -----*/ -#define ARM_SPI_SET_BUS_SPEED (0x10UL << ARM_SPI_CONTROL_Pos) ///< Set Bus Speed in bps; arg = value -#define ARM_SPI_GET_BUS_SPEED (0x11UL << ARM_SPI_CONTROL_Pos) ///< Get Bus Speed in bps -#define ARM_SPI_SET_DEFAULT_TX_VALUE (0x12UL << ARM_SPI_CONTROL_Pos) ///< Set default Transmit value; arg = value -#define ARM_SPI_CONTROL_SS (0x13UL << ARM_SPI_CONTROL_Pos) ///< Control Slave Select; arg: 0=inactive, 1=active -#define ARM_SPI_ABORT_TRANSFER (0x14UL << ARM_SPI_CONTROL_Pos) ///< Abort current data transfer - - -/****** SPI Slave Select Signal definitions *****/ -#define ARM_SPI_SS_INACTIVE 0 ///< SPI Slave Select Signal Inactive -#define ARM_SPI_SS_ACTIVE 1 ///< SPI Slave Select Signal Active - - -/****** SPI specific error codes *****/ -#define ARM_SPI_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported -#define ARM_SPI_ERROR_FRAME_FORMAT (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified Frame Format not supported -#define ARM_SPI_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported -#define ARM_SPI_ERROR_BIT_ORDER (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Bit order not supported -#define ARM_SPI_ERROR_SS_MODE (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified Slave Select Mode not supported - - -/** -\brief SPI Status -*/ -typedef struct _ARM_SPI_STATUS { - uint32_t busy : 1; ///< Transmitter/Receiver busy flag - uint32_t data_lost : 1; ///< Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation) - uint32_t mode_fault : 1; ///< Mode fault detected; optional (cleared on start of transfer operation) -} ARM_SPI_STATUS; - - -/****** SPI Event *****/ -#define ARM_SPI_EVENT_TRANSFER_COMPLETE (1UL << 0) ///< Data Transfer completed -#define ARM_SPI_EVENT_DATA_LOST (1UL << 1) ///< Data lost: Receive overflow / Transmit underflow -#define ARM_SPI_EVENT_MODE_FAULT (1UL << 2) ///< Master Mode Fault (SS deactivated when Master) - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_SPI_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION - - \fn ARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_SPI_CAPABILITIES - - \fn int32_t ARM_SPI_Initialize (ARM_SPI_SignalEvent_t cb_event) - \brief Initialize SPI Interface. - \param[in] cb_event Pointer to \ref ARM_SPI_SignalEvent - \return \ref execution_status - - \fn int32_t ARM_SPI_Uninitialize (void) - \brief De-initialize SPI Interface. - \return \ref execution_status - - \fn int32_t ARM_SPI_PowerControl (ARM_POWER_STATE state) - \brief Control SPI Interface Power. - \param[in] state Power state - \return \ref execution_status - - \fn int32_t ARM_SPI_Send (const void *data, uint32_t num) - \brief Start sending data to SPI transmitter. - \param[in] data Pointer to buffer with data to send to SPI transmitter - \param[in] num Number of data items to send - \return \ref execution_status - - \fn int32_t ARM_SPI_Receive (void *data, uint32_t num) - \brief Start receiving data from SPI receiver. - \param[out] data Pointer to buffer for data to receive from SPI receiver - \param[in] num Number of data items to receive - \return \ref execution_status - - \fn int32_t ARM_SPI_Transfer (const void *data_out, - void *data_in, - uint32_t num) - \brief Start sending/receiving data to/from SPI transmitter/receiver. - \param[in] data_out Pointer to buffer with data to send to SPI transmitter - \param[out] data_in Pointer to buffer for data to receive from SPI receiver - \param[in] num Number of data items to transfer - \return \ref execution_status - - \fn uint32_t ARM_SPI_GetDataCount (void) - \brief Get transferred data count. - \return number of data items transferred - - \fn int32_t ARM_SPI_Control (uint32_t control, uint32_t arg) - \brief Control SPI Interface. - \param[in] control Operation - \param[in] arg Argument of operation (optional) - \return common \ref execution_status and driver specific \ref spi_execution_status - - \fn ARM_SPI_STATUS ARM_SPI_GetStatus (void) - \brief Get SPI status. - \return SPI status \ref ARM_SPI_STATUS - - \fn void ARM_SPI_SignalEvent (uint32_t event) - \brief Signal SPI Events. - \param[in] event \ref SPI_events notification mask - \return none -*/ - -typedef void (*ARM_SPI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_SPI_SignalEvent : Signal SPI Event. - - -/** -\brief SPI Driver Capabilities. -*/ -typedef struct _ARM_SPI_CAPABILITIES { - uint32_t simplex : 1; ///< supports Simplex Mode (Master and Slave) - uint32_t ti_ssi : 1; ///< supports TI Synchronous Serial Interface - uint32_t microwire : 1; ///< supports Microwire Interface - uint32_t event_mode_fault : 1; ///< Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT -} ARM_SPI_CAPABILITIES; - - -/** -\brief Access structure of the SPI Driver. -*/ -typedef struct _ARM_DRIVER_SPI { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_SPI_GetVersion : Get driver version. - ARM_SPI_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_SPI_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_SPI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_SPI_Initialize : Initialize SPI Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_SPI_Uninitialize : De-initialize SPI Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_SPI_PowerControl : Control SPI Interface Power. - int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_SPI_Send : Start sending data to SPI Interface. - int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_SPI_Receive : Start receiving data from SPI Interface. - int32_t (*Transfer) (const void *data_out, - void *data_in, - uint32_t num); ///< Pointer to \ref ARM_SPI_Transfer : Start sending/receiving data to/from SPI. - uint32_t (*GetDataCount) (void); ///< Pointer to \ref ARM_SPI_GetDataCount : Get transferred data count. - int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_SPI_Control : Control SPI Interface. - ARM_SPI_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_SPI_GetStatus : Get SPI status. -} const ARM_DRIVER_SPI; - -#endif /* __DRIVER_SPI_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_USART.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_USART.h deleted file mode 100644 index 63e88e2b991..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_USART.h +++ /dev/null @@ -1,330 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2014 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * - * $Date: 24. Nov 2014 - * $Revision: V2.02 - * - * Project: USART (Universal Synchronous Asynchronous Receiver Transmitter) - * Driver definitions - * -------------------------------------------------------------------------- */ - -/* History: - * Version 2.02 - * Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions - * Version 2.01 - * Removed optional argument parameter from Signal Event - * Version 2.00 - * New simplified driver: - * complexity moved to upper layer (especially data handling) - * more unified API for different communication interfaces - * renamed driver UART -> USART (Asynchronous & Synchronous) - * Added modes: - * Synchronous - * Single-wire - * IrDA - * Smart Card - * Changed prefix ARM_DRV -> ARM_DRIVER - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.01 - * Added events: - * ARM_UART_EVENT_TX_EMPTY, ARM_UART_EVENT_RX_TIMEOUT - * ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD - * Added functions: SetTxThreshold, SetRxThreshold - * Added "rx_timeout_event" to capabilities - * Version 1.00 - * Initial release - */ - -#ifndef __DRIVER_USART_H -#define __DRIVER_USART_H - -#include "Driver_Common.h" - -#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,02) /* API version */ - - -/****** USART Control Codes *****/ - -#define ARM_USART_CONTROL_Pos 0 -#define ARM_USART_CONTROL_Msk (0xFFUL << ARM_USART_CONTROL_Pos) - -/*----- USART Control Codes: Mode -----*/ -#define ARM_USART_MODE_ASYNCHRONOUS (0x01UL << ARM_USART_CONTROL_Pos) ///< UART (Asynchronous); arg = Baudrate -#define ARM_USART_MODE_SYNCHRONOUS_MASTER (0x02UL << ARM_USART_CONTROL_Pos) ///< Synchronous Master (generates clock signal); arg = Baudrate -#define ARM_USART_MODE_SYNCHRONOUS_SLAVE (0x03UL << ARM_USART_CONTROL_Pos) ///< Synchronous Slave (external clock signal) -#define ARM_USART_MODE_SINGLE_WIRE (0x04UL << ARM_USART_CONTROL_Pos) ///< UART Single-wire (half-duplex); arg = Baudrate -#define ARM_USART_MODE_IRDA (0x05UL << ARM_USART_CONTROL_Pos) ///< UART IrDA; arg = Baudrate -#define ARM_USART_MODE_SMART_CARD (0x06UL << ARM_USART_CONTROL_Pos) ///< UART Smart Card; arg = Baudrate - -/*----- USART Control Codes: Mode Parameters: Data Bits -----*/ -#define ARM_USART_DATA_BITS_Pos 8 -#define ARM_USART_DATA_BITS_Msk (7UL << ARM_USART_DATA_BITS_Pos) -#define ARM_USART_DATA_BITS_5 (5UL << ARM_USART_DATA_BITS_Pos) ///< 5 Data bits -#define ARM_USART_DATA_BITS_6 (6UL << ARM_USART_DATA_BITS_Pos) ///< 6 Data bit -#define ARM_USART_DATA_BITS_7 (7UL << ARM_USART_DATA_BITS_Pos) ///< 7 Data bits -#define ARM_USART_DATA_BITS_8 (0UL << ARM_USART_DATA_BITS_Pos) ///< 8 Data bits (default) -#define ARM_USART_DATA_BITS_9 (1UL << ARM_USART_DATA_BITS_Pos) ///< 9 Data bits - -/*----- USART Control Codes: Mode Parameters: Parity -----*/ -#define ARM_USART_PARITY_Pos 12 -#define ARM_USART_PARITY_Msk (3UL << ARM_USART_PARITY_Pos) -#define ARM_USART_PARITY_NONE (0UL << ARM_USART_PARITY_Pos) ///< No Parity (default) -#define ARM_USART_PARITY_EVEN (1UL << ARM_USART_PARITY_Pos) ///< Even Parity -#define ARM_USART_PARITY_ODD (2UL << ARM_USART_PARITY_Pos) ///< Odd Parity - -/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/ -#define ARM_USART_STOP_BITS_Pos 14 -#define ARM_USART_STOP_BITS_Msk (3UL << ARM_USART_STOP_BITS_Pos) -#define ARM_USART_STOP_BITS_1 (0UL << ARM_USART_STOP_BITS_Pos) ///< 1 Stop bit (default) -#define ARM_USART_STOP_BITS_2 (1UL << ARM_USART_STOP_BITS_Pos) ///< 2 Stop bits -#define ARM_USART_STOP_BITS_1_5 (2UL << ARM_USART_STOP_BITS_Pos) ///< 1.5 Stop bits -#define ARM_USART_STOP_BITS_0_5 (3UL << ARM_USART_STOP_BITS_Pos) ///< 0.5 Stop bits - -/*----- USART Control Codes: Mode Parameters: Flow Control -----*/ -#define ARM_USART_FLOW_CONTROL_Pos 16 -#define ARM_USART_FLOW_CONTROL_Msk (3UL << ARM_USART_FLOW_CONTROL_Pos) -#define ARM_USART_FLOW_CONTROL_NONE (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default) -#define ARM_USART_FLOW_CONTROL_RTS (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control -#define ARM_USART_FLOW_CONTROL_CTS (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control -#define ARM_USART_FLOW_CONTROL_RTS_CTS (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control - -/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/ -#define ARM_USART_CPOL_Pos 18 -#define ARM_USART_CPOL_Msk (1UL << ARM_USART_CPOL_Pos) -#define ARM_USART_CPOL0 (0UL << ARM_USART_CPOL_Pos) ///< CPOL = 0 (default) -#define ARM_USART_CPOL1 (1UL << ARM_USART_CPOL_Pos) ///< CPOL = 1 - -/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/ -#define ARM_USART_CPHA_Pos 19 -#define ARM_USART_CPHA_Msk (1UL << ARM_USART_CPHA_Pos) -#define ARM_USART_CPHA0 (0UL << ARM_USART_CPHA_Pos) ///< CPHA = 0 (default) -#define ARM_USART_CPHA1 (1UL << ARM_USART_CPHA_Pos) ///< CPHA = 1 - - -/*----- USART Control Codes: Miscellaneous Controls -----*/ -#define ARM_USART_SET_DEFAULT_TX_VALUE (0x10UL << ARM_USART_CONTROL_Pos) ///< Set default Transmit value (Synchronous Receive only); arg = value -#define ARM_USART_SET_IRDA_PULSE (0x11UL << ARM_USART_CONTROL_Pos) ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period -#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Guard Time; arg = number of bit periods -#define ARM_USART_SET_SMART_CARD_CLOCK (0x13UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated -#define ARM_USART_CONTROL_SMART_CARD_NACK (0x14UL << ARM_USART_CONTROL_Pos) ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled -#define ARM_USART_CONTROL_TX (0x15UL << ARM_USART_CONTROL_Pos) ///< Transmitter; arg: 0=disabled, 1=enabled -#define ARM_USART_CONTROL_RX (0x16UL << ARM_USART_CONTROL_Pos) ///< Receiver; arg: 0=disabled, 1=enabled -#define ARM_USART_CONTROL_BREAK (0x17UL << ARM_USART_CONTROL_Pos) ///< Continuous Break transmission; arg: 0=disabled, 1=enabled -#define ARM_USART_ABORT_SEND (0x18UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Send -#define ARM_USART_ABORT_RECEIVE (0x19UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Receive -#define ARM_USART_ABORT_TRANSFER (0x1AUL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Transfer - - - -/****** USART specific error codes *****/ -#define ARM_USART_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported -#define ARM_USART_ERROR_BAUDRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified baudrate not supported -#define ARM_USART_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported -#define ARM_USART_ERROR_PARITY (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Parity not supported -#define ARM_USART_ERROR_STOP_BITS (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified number of Stop bits not supported -#define ARM_USART_ERROR_FLOW_CONTROL (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Flow Control not supported -#define ARM_USART_ERROR_CPOL (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock Polarity not supported -#define ARM_USART_ERROR_CPHA (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Clock Phase not supported - - -/** -\brief USART Status -*/ -typedef struct _ARM_USART_STATUS { - uint32_t tx_busy : 1; ///< Transmitter busy flag - uint32_t rx_busy : 1; ///< Receiver busy flag - uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation) - uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation) - uint32_t rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation) - uint32_t rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation) - uint32_t rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation) -} ARM_USART_STATUS; - -/** -\brief USART Modem Control -*/ -typedef enum _ARM_USART_MODEM_CONTROL { - ARM_USART_RTS_CLEAR, ///< Deactivate RTS - ARM_USART_RTS_SET, ///< Activate RTS - ARM_USART_DTR_CLEAR, ///< Deactivate DTR - ARM_USART_DTR_SET ///< Activate DTR -} ARM_USART_MODEM_CONTROL; - -/** -\brief USART Modem Status -*/ -typedef struct _ARM_USART_MODEM_STATUS { - uint32_t cts : 1; ///< CTS state: 1=Active, 0=Inactive - uint32_t dsr : 1; ///< DSR state: 1=Active, 0=Inactive - uint32_t dcd : 1; ///< DCD state: 1=Active, 0=Inactive - uint32_t ri : 1; ///< RI state: 1=Active, 0=Inactive -} ARM_USART_MODEM_STATUS; - - -/****** USART Event *****/ -#define ARM_USART_EVENT_SEND_COMPLETE (1UL << 0) ///< Send completed; however USART may still transmit data -#define ARM_USART_EVENT_RECEIVE_COMPLETE (1UL << 1) ///< Receive completed -#define ARM_USART_EVENT_TRANSFER_COMPLETE (1UL << 2) ///< Transfer completed -#define ARM_USART_EVENT_TX_COMPLETE (1UL << 3) ///< Transmit completed (optional) -#define ARM_USART_EVENT_TX_UNDERFLOW (1UL << 4) ///< Transmit data not available (Synchronous Slave) -#define ARM_USART_EVENT_RX_OVERFLOW (1UL << 5) ///< Receive data overflow -#define ARM_USART_EVENT_RX_TIMEOUT (1UL << 6) ///< Receive character timeout (optional) -#define ARM_USART_EVENT_RX_BREAK (1UL << 7) ///< Break detected on receive -#define ARM_USART_EVENT_RX_FRAMING_ERROR (1UL << 8) ///< Framing error detected on receive -#define ARM_USART_EVENT_RX_PARITY_ERROR (1UL << 9) ///< Parity error detected on receive -#define ARM_USART_EVENT_CTS (1UL << 10) ///< CTS state changed (optional) -#define ARM_USART_EVENT_DSR (1UL << 11) ///< DSR state changed (optional) -#define ARM_USART_EVENT_DCD (1UL << 12) ///< DCD state changed (optional) -#define ARM_USART_EVENT_RI (1UL << 13) ///< RI state changed (optional) - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_USART_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION - - \fn ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void) - \brief Get driver capabilities - \return \ref ARM_USART_CAPABILITIES - - \fn int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event) - \brief Initialize USART Interface. - \param[in] cb_event Pointer to \ref ARM_USART_SignalEvent - \return \ref execution_status - - \fn int32_t ARM_USART_Uninitialize (void) - \brief De-initialize USART Interface. - \return \ref execution_status - - \fn int32_t ARM_USART_PowerControl (ARM_POWER_STATE state) - \brief Control USART Interface Power. - \param[in] state Power state - \return \ref execution_status - - \fn int32_t ARM_USART_Send (const void *data, uint32_t num) - \brief Start sending data to USART transmitter. - \param[in] data Pointer to buffer with data to send to USART transmitter - \param[in] num Number of data items to send - \return \ref execution_status - - \fn int32_t ARM_USART_Receive (void *data, uint32_t num) - \brief Start receiving data from USART receiver. - \param[out] data Pointer to buffer for data to receive from USART receiver - \param[in] num Number of data items to receive - \return \ref execution_status - - \fn int32_t ARM_USART_Transfer (const void *data_out, - void *data_in, - uint32_t num) - \brief Start sending/receiving data to/from USART transmitter/receiver. - \param[in] data_out Pointer to buffer with data to send to USART transmitter - \param[out] data_in Pointer to buffer for data to receive from USART receiver - \param[in] num Number of data items to transfer - \return \ref execution_status - - \fn uint32_t ARM_USART_GetTxCount (void) - \brief Get transmitted data count. - \return number of data items transmitted - - \fn uint32_t ARM_USART_GetRxCount (void) - \brief Get received data count. - \return number of data items received - - \fn int32_t ARM_USART_Control (uint32_t control, uint32_t arg) - \brief Control USART Interface. - \param[in] control Operation - \param[in] arg Argument of operation (optional) - \return common \ref execution_status and driver specific \ref usart_execution_status - - \fn ARM_USART_STATUS ARM_USART_GetStatus (void) - \brief Get USART status. - \return USART status \ref ARM_USART_STATUS - - \fn int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control) - \brief Set USART Modem Control line state. - \param[in] control \ref ARM_USART_MODEM_CONTROL - \return \ref execution_status - - \fn ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void) - \brief Get USART Modem Status lines state. - \return modem status \ref ARM_USART_MODEM_STATUS - - \fn void ARM_USART_SignalEvent (uint32_t event) - \brief Signal USART Events. - \param[in] event \ref USART_events notification mask - \return none -*/ - -typedef void (*ARM_USART_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event. - - -/** -\brief USART Device Driver Capabilities. -*/ -typedef struct _ARM_USART_CAPABILITIES { - uint32_t asynchronous : 1; ///< supports UART (Asynchronous) mode - uint32_t synchronous_master : 1; ///< supports Synchronous Master mode - uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode - uint32_t single_wire : 1; ///< supports UART Single-wire mode - uint32_t irda : 1; ///< supports UART IrDA mode - uint32_t smart_card : 1; ///< supports UART Smart Card mode - uint32_t smart_card_clock : 1; ///< Smart Card Clock generator available - uint32_t flow_control_rts : 1; ///< RTS Flow Control available - uint32_t flow_control_cts : 1; ///< CTS Flow Control available - uint32_t event_tx_complete : 1; ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE - uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT - uint32_t rts : 1; ///< RTS Line: 0=not available, 1=available - uint32_t cts : 1; ///< CTS Line: 0=not available, 1=available - uint32_t dtr : 1; ///< DTR Line: 0=not available, 1=available - uint32_t dsr : 1; ///< DSR Line: 0=not available, 1=available - uint32_t dcd : 1; ///< DCD Line: 0=not available, 1=available - uint32_t ri : 1; ///< RI Line: 0=not available, 1=available - uint32_t event_cts : 1; ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS - uint32_t event_dsr : 1; ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR - uint32_t event_dcd : 1; ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD - uint32_t event_ri : 1; ///< Signal RI change event: \ref ARM_USART_EVENT_RI -} ARM_USART_CAPABILITIES; - - -/** -\brief Access structure of the USART Driver. -*/ -typedef struct _ARM_DRIVER_USART { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USART_GetVersion : Get driver version. - ARM_USART_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_USART_SignalEvent_t cb_event); ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power. - int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter. - int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver. - int32_t (*Transfer) (const void *data_out, - void *data_in, - uint32_t num); ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART. - uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count. - uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count. - int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_USART_Control : Control USART Interface. - ARM_USART_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_USART_GetStatus : Get USART status. - int32_t (*SetModemControl) (ARM_USART_MODEM_CONTROL control); ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state. - ARM_USART_MODEM_STATUS (*GetModemStatus) (void); ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state. -} const ARM_DRIVER_USART; - -#endif /* __DRIVER_USART_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_USB.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_USB.h deleted file mode 100644 index 4f3a1b87add..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_USB.h +++ /dev/null @@ -1,95 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2014 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * - * $Date: 20. May 2014 - * $Revision: V2.00 - * - * Project: USB Driver common definitions - * -------------------------------------------------------------------------- */ - -/* History: - * Version 2.00 - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.01 - * Added PID Types - * Version 1.00 - * Initial release - */ - -#ifndef __DRIVER_USB_H -#define __DRIVER_USB_H - -#include "Driver_Common.h" - -/* USB Role */ -#define ARM_USB_ROLE_NONE 0 -#define ARM_USB_ROLE_HOST 1 -#define ARM_USB_ROLE_DEVICE 2 - -/* USB Pins */ -#define ARM_USB_PIN_DP (1 << 0) ///< USB D+ pin -#define ARM_USB_PIN_DM (1 << 1) ///< USB D- pin -#define ARM_USB_PIN_VBUS (1 << 2) ///< USB VBUS pin -#define ARM_USB_PIN_OC (1 << 3) ///< USB OverCurrent pin -#define ARM_USB_PIN_ID (1 << 4) ///< USB ID pin - -/* USB Speed */ -#define ARM_USB_SPEED_LOW 0 ///< Low-speed USB -#define ARM_USB_SPEED_FULL 1 ///< Full-speed USB -#define ARM_USB_SPEED_HIGH 2 ///< High-speed USB - -/* USB PID Types */ -#define ARM_USB_PID_OUT 1 -#define ARM_USB_PID_IN 9 -#define ARM_USB_PID_SOF 5 -#define ARM_USB_PID_SETUP 13 -#define ARM_USB_PID_DATA0 3 -#define ARM_USB_PID_DATA1 11 -#define ARM_USB_PID_DATA2 7 -#define ARM_USB_PID_MDATA 15 -#define ARM_USB_PID_ACK 2 -#define ARM_USB_PID_NAK 10 -#define ARM_USB_PID_STALL 14 -#define ARM_USB_PID_NYET 6 -#define ARM_USB_PID_PRE 12 -#define ARM_USB_PID_ERR 12 -#define ARM_USB_PID_SPLIT 8 -#define ARM_USB_PID_PING 4 -#define ARM_USB_PID_RESERVED 0 - -/* USB Endpoint Address (bEndpointAddress) */ -#define ARM_USB_ENDPOINT_NUMBER_MASK 0x0F -#define ARM_USB_ENDPOINT_DIRECTION_MASK 0x80 - -/* USB Endpoint Type */ -#define ARM_USB_ENDPOINT_CONTROL 0 ///< Control Endpoint -#define ARM_USB_ENDPOINT_ISOCHRONOUS 1 ///< Isochronous Endpoint -#define ARM_USB_ENDPOINT_BULK 2 ///< Bulk Endpoint -#define ARM_USB_ENDPOINT_INTERRUPT 3 ///< Interrupt Endpoint - -/* USB Endpoint Maximum Packet Size (wMaxPacketSize) */ -#define ARM_USB_ENDPOINT_MAX_PACKET_SIZE_MASK 0x07FF -#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_MASK 0x1800 -#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_1 0x0000 -#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_2 0x0800 -#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_3 0x1000 - -#endif /* __DRIVER_USB_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_USBD.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_USBD.h deleted file mode 100644 index 286e109b629..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_USBD.h +++ /dev/null @@ -1,263 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2014 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * - * $Date: 3. Jun 2014 - * $Revision: V2.01 - * - * Project: USB Device Driver definitions - * -------------------------------------------------------------------------- */ - -/* History: - * Version 2.01 - * Added ARM_USBD_ReadSetupPacket function - * Version 2.00 - * Removed ARM_USBD_DeviceConfigure function - * Removed ARM_USBD_SET_ADDRESS_STAGE parameter from ARM_USBD_DeviceSetAddress function - * Removed ARM_USBD_EndpointReadStart function - * Replaced ARM_USBD_EndpointRead and ARM_USBD_EndpointWrite functions with ARM_USBD_EndpointTransfer - * Added ARM_USBD_EndpointTransferGetResult function - * Renamed ARM_USBD_EndpointAbort function to ARM_USBD_EndpointTransferAbort - * Changed prefix ARM_DRV -> ARM_DRIVER - * Changed return values of some functions to int32_t - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.00 - * Initial release - */ - -#ifndef __DRIVER_USBD_H -#define __DRIVER_USBD_H - -#include "Driver_USB.h" - -#define ARM_USBD_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,01) /* API version */ - - -/** -\brief USB Device State -*/ -typedef struct _ARM_USBD_STATE { - uint32_t vbus : 1; ///< USB Device VBUS flag - uint32_t speed : 2; ///< USB Device speed setting (ARM_USB_SPEED_xxx) - uint32_t active : 1; ///< USB Device active flag -} ARM_USBD_STATE; - - -/****** USB Device Event *****/ -#define ARM_USBD_EVENT_VBUS_ON (1UL << 0) ///< USB Device VBUS On -#define ARM_USBD_EVENT_VBUS_OFF (1UL << 1) ///< USB Device VBUS Off -#define ARM_USBD_EVENT_RESET (1UL << 2) ///< USB Reset occurred -#define ARM_USBD_EVENT_HIGH_SPEED (1UL << 3) ///< USB switch to High Speed occurred -#define ARM_USBD_EVENT_SUSPEND (1UL << 4) ///< USB Suspend occurred -#define ARM_USBD_EVENT_RESUME (1UL << 5) ///< USB Resume occurred - -/****** USB Endpoint Event *****/ -#define ARM_USBD_EVENT_SETUP (1UL << 0) ///< SETUP Packet -#define ARM_USBD_EVENT_OUT (1UL << 1) ///< OUT Packet(s) -#define ARM_USBD_EVENT_IN (1UL << 2) ///< IN Packet(s) - - -#ifndef __DOXYGEN_MW__ // exclude from middleware documentation - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_USBD_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION -*/ -/** - \fn ARM_USBD_CAPABILITIES ARM_USBD_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_USBD_CAPABILITIES -*/ -/** - \fn int32_t ARM_USBD_Initialize (ARM_USBD_SignalDeviceEvent_t cb_device_event, - ARM_USBD_SignalEndpointEvent_t cb_endpoint_event) - \brief Initialize USB Device Interface. - \param[in] cb_device_event Pointer to \ref ARM_USBD_SignalDeviceEvent - \param[in] cb_endpoint_event Pointer to \ref ARM_USBD_SignalEndpointEvent - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBD_Uninitialize (void) - \brief De-initialize USB Device Interface. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBD_PowerControl (ARM_POWER_STATE state) - \brief Control USB Device Interface Power. - \param[in] state Power state - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBD_DeviceConnect (void) - \brief Connect USB Device. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBD_DeviceDisconnect (void) - \brief Disconnect USB Device. - \return \ref execution_status -*/ -/** - \fn ARM_USBD_STATE ARM_USBD_DeviceGetState (void) - \brief Get current USB Device State. - \return Device State \ref ARM_USBD_STATE -*/ -/** - \fn int32_t ARM_USBD_DeviceRemoteWakeup (void) - \brief Trigger USB Remote Wakeup. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBD_DeviceSetAddress (uint8_t dev_addr) - \brief Set USB Device Address. - \param[in] dev_addr Device Address - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBD_ReadSetupPacket (uint8_t *setup) - \brief Read setup packet received over Control Endpoint. - \param[out] setup Pointer to buffer for setup packet - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBD_EndpointConfigure (uint8_t ep_addr, - uint8_t ep_type, - uint16_t ep_max_packet_size) - \brief Configure USB Endpoint. - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \param[in] ep_type Endpoint Type (ARM_USB_ENDPOINT_xxx) - \param[in] ep_max_packet_size Endpoint Maximum Packet Size - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBD_EndpointUnconfigure (uint8_t ep_addr) - \brief Unconfigure USB Endpoint. - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBD_EndpointStall (uint8_t ep_addr, bool stall) - \brief Set/Clear Stall for USB Endpoint. - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \param[in] stall Operation - - \b false Clear - - \b true Set - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num) - \brief Read data from or Write data to USB Endpoint. - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \param[out] data Pointer to buffer for data to read or with data to write - \param[in] num Number of data bytes to transfer - \return \ref execution_status -*/ -/** - \fn uint32_t ARM_USBD_EndpointTransferGetResult (uint8_t ep_addr) - \brief Get result of USB Endpoint transfer. - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \return number of successfully transferred data bytes -*/ -/** - \fn int32_t ARM_USBD_EndpointTransferAbort (uint8_t ep_addr) - \brief Abort current USB Endpoint transfer. - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \return \ref execution_status -*/ -/** - \fn uint16_t ARM_USBD_GetFrameNumber (void) - \brief Get current USB Frame Number. - \return Frame Number -*/ - -/** - \fn void ARM_USBD_SignalDeviceEvent (uint32_t event) - \brief Signal USB Device Event. - \param[in] event \ref USBD_dev_events - \return none -*/ -/** - \fn void ARM_USBD_SignalEndpointEvent (uint8_t ep_addr, uint32_t event) - \brief Signal USB Endpoint Event. - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \param[in] event \ref USBD_ep_events - \return none -*/ - -typedef void (*ARM_USBD_SignalDeviceEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USBD_SignalDeviceEvent : Signal USB Device Event. -typedef void (*ARM_USBD_SignalEndpointEvent_t) (uint8_t ep_addr, uint32_t event); ///< Pointer to \ref ARM_USBD_SignalEndpointEvent : Signal USB Endpoint Event. - - -/** -\brief USB Device Driver Capabilities. -*/ -typedef struct _ARM_USBD_CAPABILITIES { - uint32_t vbus_detection : 1; ///< VBUS detection - uint32_t event_vbus_on : 1; ///< Signal VBUS On event - uint32_t event_vbus_off : 1; ///< Signal VBUS Off event -} ARM_USBD_CAPABILITIES; - - -/** -\brief Access structure of the USB Device Driver. -*/ -typedef struct _ARM_DRIVER_USBD { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USBD_GetVersion : Get driver version. - ARM_USBD_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USBD_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_USBD_SignalDeviceEvent_t cb_device_event, - ARM_USBD_SignalEndpointEvent_t cb_endpoint_event); ///< Pointer to \ref ARM_USBD_Initialize : Initialize USB Device Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USBD_Uninitialize : De-initialize USB Device Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USBD_PowerControl : Control USB Device Interface Power. - int32_t (*DeviceConnect) (void); ///< Pointer to \ref ARM_USBD_DeviceConnect : Connect USB Device. - int32_t (*DeviceDisconnect) (void); ///< Pointer to \ref ARM_USBD_DeviceDisconnect : Disconnect USB Device. - ARM_USBD_STATE (*DeviceGetState) (void); ///< Pointer to \ref ARM_USBD_DeviceGetState : Get current USB Device State. - int32_t (*DeviceRemoteWakeup) (void); ///< Pointer to \ref ARM_USBD_DeviceRemoteWakeup : Trigger USB Remote Wakeup. - int32_t (*DeviceSetAddress) (uint8_t dev_addr); ///< Pointer to \ref ARM_USBD_DeviceSetAddress : Set USB Device Address. - int32_t (*ReadSetupPacket) (uint8_t *setup); ///< Pointer to \ref ARM_USBD_ReadSetupPacket : Read setup packet received over Control Endpoint. - int32_t (*EndpointConfigure) (uint8_t ep_addr, - uint8_t ep_type, - uint16_t ep_max_packet_size); ///< Pointer to \ref ARM_USBD_EndpointConfigure : Configure USB Endpoint. - int32_t (*EndpointUnconfigure) (uint8_t ep_addr); ///< Pointer to \ref ARM_USBD_EndpointUnconfigure : Unconfigure USB Endpoint. - int32_t (*EndpointStall) (uint8_t ep_addr, bool stall); ///< Pointer to \ref ARM_USBD_EndpointStall : Set/Clear Stall for USB Endpoint. - int32_t (*EndpointTransfer) (uint8_t ep_addr, uint8_t *data, uint32_t num); ///< Pointer to \ref ARM_USBD_EndpointTransfer : Read data from or Write data to USB Endpoint. - uint32_t (*EndpointTransferGetResult) (uint8_t ep_addr); ///< Pointer to \ref ARM_USBD_EndpointTransferGetResult : Get result of USB Endpoint transfer. - int32_t (*EndpointTransferAbort) (uint8_t ep_addr); ///< Pointer to \ref ARM_USBD_EndpointTransferAbort : Abort current USB Endpoint transfer. - uint16_t (*GetFrameNumber) (void); ///< Pointer to \ref ARM_USBD_GetFrameNumber : Get current USB Frame Number. -} const ARM_DRIVER_USBD; - -#endif /* __DOXYGEN_MW__ */ - -#endif /* __DRIVER_USBD_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_USBH.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_USBH.h deleted file mode 100644 index 9973e7c2ecb..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Driver/Include/Driver_USBH.h +++ /dev/null @@ -1,406 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2014 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * - * $Date: 3. September 2014 - * $Revision: V2.01 - * - * Project: USB Host Driver definitions - * -------------------------------------------------------------------------- */ - -/* History: - * Version 2.01 - * Renamed structure ARM_USBH_EP_HANDLE to ARM_USBH_PIPE_HANDLE - * Renamed functions ARM_USBH_Endpoint... to ARM_USBH_Pipe... - * Renamed function ARM_USBH_SignalEndpointEvent to ARM_USBH_SignalPipeEvent - * Version 2.00 - * Replaced function ARM_USBH_PortPowerOnOff with ARM_USBH_PortVbusOnOff - * Changed function ARM_USBH_EndpointCreate parameters - * Replaced function ARM_USBH_EndpointConfigure with ARM_USBH_EndpointModify - * Replaced function ARM_USBH_EndpointClearHalt with ARM_USBH_EndpointReset - * Replaced function ARM_USBH_URB_Submit with ARM_USBH_EndpointTransfer - * Replaced function ARM_USBH_URB_Abort with ARM_USBH_EndpointTransferAbort - * Added function ARM_USBH_EndpointTransferGetResult - * Added function ARM_USBH_GetFrameNumber - * Changed prefix ARM_DRV -> ARM_DRIVER - * Version 1.20 - * Added API for OHCI/EHCI Host Controller Interface (HCI) - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.00 - * Initial release - */ - -#ifndef __DRIVER_USBH_H -#define __DRIVER_USBH_H - -#include "Driver_USB.h" - -#define ARM_USBH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,01) /* API version */ - - -/** -\brief USB Host Port State -*/ -typedef struct _ARM_USBH_PORT_STATE { - uint32_t connected : 1; ///< USB Host Port connected flag - uint32_t overcurrent : 1; ///< USB Host Port overcurrent flag - uint32_t speed : 2; ///< USB Host Port speed setting (ARM_USB_SPEED_xxx) -} ARM_USBH_PORT_STATE; - -/** -\brief USB Host Pipe Handle -*/ -typedef uint32_t ARM_USBH_PIPE_HANDLE; -#define ARM_USBH_EP_HANDLE ARM_USBH_PIPE_HANDLE /* Legacy name */ - - -/****** USB Host Packet Information *****/ -#define ARM_USBH_PACKET_TOKEN_Pos 0 -#define ARM_USBH_PACKET_TOKEN_Msk (0x0FUL << ARM_USBH_PACKET_TOKEN_Pos) -#define ARM_USBH_PACKET_SETUP (0x01UL << ARM_USBH_PACKET_TOKEN_Pos) ///< SETUP Packet -#define ARM_USBH_PACKET_OUT (0x02UL << ARM_USBH_PACKET_TOKEN_Pos) ///< OUT Packet -#define ARM_USBH_PACKET_IN (0x03UL << ARM_USBH_PACKET_TOKEN_Pos) ///< IN Packet -#define ARM_USBH_PACKET_PING (0x04UL << ARM_USBH_PACKET_TOKEN_Pos) ///< PING Packet - -#define ARM_USBH_PACKET_DATA_Pos 4 -#define ARM_USBH_PACKET_DATA_Msk (0x0FUL << ARM_USBH_PACKET_DATA_Pos) -#define ARM_USBH_PACKET_DATA0 (0x01UL << ARM_USBH_PACKET_DATA_Pos) ///< DATA0 PID -#define ARM_USBH_PACKET_DATA1 (0x02UL << ARM_USBH_PACKET_DATA_Pos) ///< DATA1 PID - -#define ARM_USBH_PACKET_SPLIT_Pos 8 -#define ARM_USBH_PACKET_SPLIT_Msk (0x0FUL << ARM_USBH_PACKET_SPLIT_Pos) -#define ARM_USBH_PACKET_SSPLIT (0x08UL << ARM_USBH_PACKET_SPLIT_Pos) ///< SSPLIT Packet -#define ARM_USBH_PACKET_SSPLIT_S (0x09UL << ARM_USBH_PACKET_SPLIT_Pos) ///< SSPLIT Packet: Data Start -#define ARM_USBH_PACKET_SSPLIT_E (0x0AUL << ARM_USBH_PACKET_SPLIT_Pos) ///< SSPLIT Packet: Data End -#define ARM_USBH_PACKET_SSPLIT_S_E (0x0BUL << ARM_USBH_PACKET_SPLIT_Pos) ///< SSPLIT Packet: Data All -#define ARM_USBH_PACKET_CSPLIT (0x0CUL << ARM_USBH_PACKET_SPLIT_Pos) ///< CSPLIT Packet - -#define ARM_USBH_PACKET_PRE (1UL << 12) ///< PRE Token - - -/****** USB Host Port Event *****/ -#define ARM_USBH_EVENT_CONNECT (1UL << 0) ///< USB Device Connected to Port -#define ARM_USBH_EVENT_DISCONNECT (1UL << 1) ///< USB Device Disconnected from Port -#define ARM_USBH_EVENT_OVERCURRENT (1UL << 2) ///< USB Device caused Overcurrent -#define ARM_USBH_EVENT_RESET (1UL << 3) ///< USB Reset completed -#define ARM_USBH_EVENT_SUSPEND (1UL << 4) ///< USB Suspend occurred -#define ARM_USBH_EVENT_RESUME (1UL << 5) ///< USB Resume occurred -#define ARM_USBH_EVENT_REMOTE_WAKEUP (1UL << 6) ///< USB Device activated Remote Wakeup - -/****** USB Host Pipe Event *****/ -#define ARM_USBH_EVENT_TRANSFER_COMPLETE (1UL << 0) ///< Transfer completed -#define ARM_USBH_EVENT_HANDSHAKE_NAK (1UL << 1) ///< NAK Handshake received -#define ARM_USBH_EVENT_HANDSHAKE_NYET (1UL << 2) ///< NYET Handshake received -#define ARM_USBH_EVENT_HANDSHAKE_MDATA (1UL << 3) ///< MDATA Handshake received -#define ARM_USBH_EVENT_HANDSHAKE_STALL (1UL << 4) ///< STALL Handshake received -#define ARM_USBH_EVENT_HANDSHAKE_ERR (1UL << 5) ///< ERR Handshake received -#define ARM_USBH_EVENT_BUS_ERROR (1UL << 6) ///< Bus Error detected - - -#ifndef __DOXYGEN_MW__ // exclude from middleware documentation - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_USBH_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION -*/ -/** - \fn ARM_USBH_CAPABILITIES ARM_USBH_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_USBH_CAPABILITIES -*/ -/** - \fn int32_t ARM_USBH_Initialize (ARM_USBH_SignalPortEvent_t cb_port_event, - ARM_USBH_SignalPipeEvent_t cb_pipe_event) - \brief Initialize USB Host Interface. - \param[in] cb_port_event Pointer to \ref ARM_USBH_SignalPortEvent - \param[in] cb_pipe_event Pointer to \ref ARM_USBH_SignalPipeEvent - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_Uninitialize (void) - \brief De-initialize USB Host Interface. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_PowerControl (ARM_POWER_STATE state) - \brief Control USB Host Interface Power. - \param[in] state Power state - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_PortVbusOnOff (uint8_t port, bool vbus) - \brief Root HUB Port VBUS on/off. - \param[in] port Root HUB Port Number - \param[in] vbus - - \b false VBUS off - - \b true VBUS on - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_PortReset (uint8_t port) - \brief Do Root HUB Port Reset. - \param[in] port Root HUB Port Number - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_PortSuspend (uint8_t port) - \brief Suspend Root HUB Port (stop generating SOFs). - \param[in] port Root HUB Port Number - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_PortResume (uint8_t port) - \brief Resume Root HUB Port (start generating SOFs). - \param[in] port Root HUB Port Number - \return \ref execution_status -*/ -/** - \fn ARM_USBH_PORT_STATE ARM_USBH_PortGetState (uint8_t port) - \brief Get current Root HUB Port State. - \param[in] port Root HUB Port Number - \return Port State \ref ARM_USBH_PORT_STATE -*/ -/** - \fn ARM_USBH_PIPE_HANDLE ARM_USBH_PipeCreate (uint8_t dev_addr, - uint8_t dev_speed, - uint8_t hub_addr, - uint8_t hub_port, - uint8_t ep_addr, - uint8_t ep_type, - uint16_t ep_max_packet_size, - uint8_t ep_interval) - \brief Create Pipe in System. - \param[in] dev_addr Device Address - \param[in] dev_speed Device Speed - \param[in] hub_addr Hub Address - \param[in] hub_port Hub Port - \param[in] ep_addr Endpoint Address - - ep_addr.0..3: Address - - ep_addr.7: Direction - \param[in] ep_type Endpoint Type (ARM_USB_ENDPOINT_xxx) - \param[in] ep_max_packet_size Endpoint Maximum Packet Size - \param[in] ep_interval Endpoint Polling Interval - \return Pipe Handle \ref ARM_USBH_PIPE_HANDLE -*/ -/** - \fn int32_t ARM_USBH_PipeModify (ARM_USBH_PIPE_HANDLE pipe_hndl, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t hub_addr, - uint8_t hub_port, - uint16_t ep_max_packet_size) - \brief Modify Pipe in System. - \param[in] pipe_hndl Pipe Handle - \param[in] dev_addr Device Address - \param[in] dev_speed Device Speed - \param[in] hub_addr Hub Address - \param[in] hub_port Hub Port - \param[in] ep_max_packet_size Endpoint Maximum Packet Size - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_PipeDelete (ARM_USBH_PIPE_HANDLE pipe_hndl) - \brief Delete Pipe from System. - \param[in] pipe_hndl Pipe Handle - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_PipeReset (ARM_USBH_PIPE_HANDLE pipe_hndl) - \brief Reset Pipe. - \param[in] pipe_hndl Pipe Handle - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_PipeTransfer (ARM_USBH_PIPE_HANDLE pipe_hndl, - uint32_t packet, - uint8_t *data, - uint32_t num) - \brief Transfer packets through USB Pipe. - \param[in] pipe_hndl Pipe Handle - \param[in] packet Packet information - \param[in] data Pointer to buffer with data to send or for data to receive - \param[in] num Number of data bytes to transfer - \return \ref execution_status -*/ -/** - \fn uint32_t ARM_USBH_PipeTransferGetResult (ARM_USBH_PIPE_HANDLE pipe_hndl) - \brief Get result of USB Pipe transfer. - \param[in] pipe_hndl Pipe Handle - \return number of successfully transferred data bytes -*/ -/** - \fn int32_t ARM_USBH_PipeTransferAbort (ARM_USBH_PIPE_HANDLE pipe_hndl) - \brief Abort current USB Pipe transfer. - \param[in] pipe_hndl Pipe Handle - \return \ref execution_status -*/ -/** - \fn uint16_t ARM_USBH_GetFrameNumber (void) - \brief Get current USB Frame Number. - \return Frame Number -*/ - -/** - \fn void ARM_USBH_SignalPortEvent (uint8_t port, uint32_t event) - \brief Signal Root HUB Port Event. - \param[in] port Root HUB Port Number - \param[in] event \ref USBH_port_events - \return none -*/ -/** - \fn void ARM_USBH_SignalPipeEvent (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event) - \brief Signal Pipe Event. - \param[in] pipe_hndl Pipe Handle - \param[in] event \ref USBH_pipe_events - \return none -*/ - -typedef void (*ARM_USBH_SignalPortEvent_t) (uint8_t port, uint32_t event); ///< Pointer to \ref ARM_USBH_SignalPortEvent : Signal Root HUB Port Event. -typedef void (*ARM_USBH_SignalPipeEvent_t) (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event); ///< Pointer to \ref ARM_USBH_SignalPipeEvent : Signal Pipe Event. -#define ARM_USBH_SignalEndpointEvent_t ARM_USBH_SignalPipeEvent_t /* Legacy name */ - - -/** -\brief USB Host Driver Capabilities. -*/ -typedef struct _ARM_USBH_CAPABILITIES { - uint32_t port_mask : 15; ///< Root HUB available Ports Mask - uint32_t auto_split : 1; ///< Automatic SPLIT packet handling - uint32_t event_connect : 1; ///< Signal Connect event - uint32_t event_disconnect : 1; ///< Signal Disconnect event - uint32_t event_overcurrent : 1; ///< Signal Overcurrent event -} ARM_USBH_CAPABILITIES; - - -/** -\brief Access structure of USB Host Driver. -*/ -typedef struct _ARM_DRIVER_USBH { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USBH_GetVersion : Get driver version. - ARM_USBH_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USBH_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_USBH_SignalPortEvent_t cb_port_event, - ARM_USBH_SignalPipeEvent_t cb_pipe_event); ///< Pointer to \ref ARM_USBH_Initialize : Initialize USB Host Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USBH_Uninitialize : De-initialize USB Host Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USBH_PowerControl : Control USB Host Interface Power. - int32_t (*PortVbusOnOff) (uint8_t port, bool vbus); ///< Pointer to \ref ARM_USBH_PortVbusOnOff : Root HUB Port VBUS on/off. - int32_t (*PortReset) (uint8_t port); ///< Pointer to \ref ARM_USBH_PortReset : Do Root HUB Port Reset. - int32_t (*PortSuspend) (uint8_t port); ///< Pointer to \ref ARM_USBH_PortSuspend : Suspend Root HUB Port (stop generating SOFs). - int32_t (*PortResume) (uint8_t port); ///< Pointer to \ref ARM_USBH_PortResume : Resume Root HUB Port (start generating SOFs). - ARM_USBH_PORT_STATE (*PortGetState) (uint8_t port); ///< Pointer to \ref ARM_USBH_PortGetState : Get current Root HUB Port State. - ARM_USBH_PIPE_HANDLE (*PipeCreate) (uint8_t dev_addr, - uint8_t dev_speed, - uint8_t hub_addr, - uint8_t hub_port, - uint8_t ep_addr, - uint8_t ep_type, - uint16_t ep_max_packet_size, - uint8_t ep_interval); ///< Pointer to \ref ARM_USBH_PipeCreate : Create Pipe in System. - int32_t (*PipeModify) (ARM_USBH_PIPE_HANDLE pipe_hndl, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t hub_addr, - uint8_t hub_port, - uint16_t ep_max_packet_size); ///< Pointer to \ref ARM_USBH_PipeModify : Modify Pipe in System. - int32_t (*PipeDelete) (ARM_USBH_PIPE_HANDLE pipe_hndl); ///< Pointer to \ref ARM_USBH_PipeDelete : Delete Pipe from System. - int32_t (*PipeReset) (ARM_USBH_PIPE_HANDLE pipe_hndl); ///< Pointer to \ref ARM_USBH_PipeReset : Reset Pipe. - int32_t (*PipeTransfer) (ARM_USBH_PIPE_HANDLE pipe_hndl, - uint32_t packet, - uint8_t *data, - uint32_t num); ///< Pointer to \ref ARM_USBH_PipeTransfer : Transfer packets through USB Pipe. - uint32_t (*PipeTransferGetResult) (ARM_USBH_PIPE_HANDLE pipe_hndl); ///< Pointer to \ref ARM_USBH_PipeTransferGetResult : Get result of USB Pipe transfer. - int32_t (*PipeTransferAbort) (ARM_USBH_PIPE_HANDLE pipe_hndl); ///< Pointer to \ref ARM_USBH_PipeTransferAbort : Abort current USB Pipe transfer. - uint16_t (*GetFrameNumber) (void); ///< Pointer to \ref ARM_USBH_GetFrameNumber : Get current USB Frame Number. -} const ARM_DRIVER_USBH; - - -// HCI (OHCI/EHCI) - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_USBH_HCI_GetVersion (void) - \brief Get USB Host HCI (OHCI/EHCI) driver version. - \return \ref ARM_DRIVER_VERSION -*/ -/** - \fn ARM_USBH_HCI_CAPABILITIES ARM_USBH_HCI_GetCapabilities (void) - \brief Get driver capabilities. - \return \ref ARM_USBH_HCI_CAPABILITIES -*/ -/** - \fn int32_t ARM_USBH_HCI_Initialize (ARM_USBH_HCI_Interrupt_t *cb_interrupt) - \brief Initialize USB Host HCI (OHCI/EHCI) Interface. - \param[in] cb_interrupt Pointer to Interrupt Handler Routine - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_HCI_Uninitialize (void) - \brief De-initialize USB Host HCI (OHCI/EHCI) Interface. - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_HCI_PowerControl (ARM_POWER_STATE state) - \brief Control USB Host HCI (OHCI/EHCI) Interface Power. - \param[in] state Power state - \return \ref execution_status -*/ -/** - \fn int32_t ARM_USBH_HCI_PortVbusOnOff (uint8_t port, bool vbus) - \brief USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off. - \param[in] port Root HUB Port Number - \param[in] vbus - - \b false VBUS off - - \b true VBUS on - \return \ref execution_status -*/ - -/** - \fn void ARM_USBH_HCI_Interrupt (void) - \brief USB Host HCI Interrupt Handler. - \return none -*/ - -typedef void (*ARM_USBH_HCI_Interrupt_t) (void); ///< Pointer to Interrupt Handler Routine. - - -/** -\brief USB Host HCI (OHCI/EHCI) Driver Capabilities. -*/ -typedef struct _ARM_USBH_HCI_CAPABILITIES { - uint32_t port_mask : 15; ///< Root HUB available Ports Mask -} ARM_USBH_HCI_CAPABILITIES; - - -/** - \brief Access structure of USB Host HCI (OHCI/EHCI) Driver. -*/ -typedef struct _ARM_DRIVER_USBH_HCI { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USBH_HCI_GetVersion : Get USB Host HCI (OHCI/EHCI) driver version. - ARM_USBH_HCI_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USBH_HCI_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_USBH_HCI_Interrupt_t cb_interrupt); ///< Pointer to \ref ARM_USBH_HCI_Initialize : Initialize USB Host HCI (OHCI/EHCI) Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USBH_HCI_Uninitialize : De-initialize USB Host HCI (OHCI/EHCI) Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USBH_HCI_PowerControl : Control USB Host HCI (OHCI/EHCI) Interface Power. - int32_t (*PortVbusOnOff) (uint8_t port, bool vbus); ///< Pointer to \ref ARM_USBH_HCI_PortVbusOnOff : USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off. -} const ARM_DRIVER_USBH_HCI; - -#endif /* __DOXYGEN_MW__ */ - -#endif /* __DRIVER_USBH_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/SConscript b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/SConscript deleted file mode 100644 index 8e16aeac362..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/SConscript +++ /dev/null @@ -1,12 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -src = Glob('*.c') - -CPPPATH = [cwd] - -group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/arm_common_tables.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/arm_common_tables.h deleted file mode 100644 index dfea7460e9a..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/arm_common_tables.h +++ /dev/null @@ -1,121 +0,0 @@ -/* ---------------------------------------------------------------------- - * Project: CMSIS DSP Library - * Title: arm_common_tables.h - * Description: Extern declaration for common tables - * - * $Date: 27. January 2017 - * $Revision: V.1.5.1 - * - * Target Processor: Cortex-M cores - * -------------------------------------------------------------------- */ -/* - * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - -/* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) -#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) -#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) -#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) -#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) -#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) -#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) -#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) -#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) -#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/arm_const_structs.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/arm_const_structs.h deleted file mode 100644 index 80a3e8bbe72..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/arm_const_structs.h +++ /dev/null @@ -1,66 +0,0 @@ -/* ---------------------------------------------------------------------- - * Project: CMSIS DSP Library - * Title: arm_const_structs.h - * Description: Constant structs that are initialized for user convenience. - * For example, some can be given as arguments to the arm_cfft_f32() function. - * - * $Date: 27. January 2017 - * $Revision: V.1.5.1 - * - * Target Processor: Cortex-M cores - * -------------------------------------------------------------------- */ -/* - * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; - -#endif diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/arm_math.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/arm_math.h deleted file mode 100644 index 6d754018966..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7257 +0,0 @@ -/* ---------------------------------------------------------------------- - * Project: CMSIS DSP Library - * Title: arm_math.h - * Description: Public header file for CMSIS DSP Library - * - * $Date: 27. January 2017 - * $Revision: V.1.5.1 - * - * Target Processor: Cortex-M cores - * -------------------------------------------------------------------- */ -/* - * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) - * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) - * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) - * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) - * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) - * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) - * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) - * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) - * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) - * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) - * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) - * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) - * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) - * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) - * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian) - * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian) - * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit) - * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions) - * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. - * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions. - * - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK-ARM version 5.14.0.0 - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvprojx - * - * - * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * ------------ - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and - * ARM_MATH_CM7 for building the library on cortex-M7. - * - * - ARM_MATH_ARMV8MxL: - * - * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library - * on ARMv8M Mainline target. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. - * - * - __DSP_PRESENT: - * - * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions. - * - *
- * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
- * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2015 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -/* Compiler specific diagnostic adjustment */ -#if defined ( __CC_ARM ) - -#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - -#elif defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -#elif defined ( __ICCARM__ ) - -#elif defined ( __TI_ARM__ ) - -#elif defined ( __CSMC__ ) - -#elif defined ( __TASKING__ ) - -#else - #error Unknown compiler -#endif - - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) - #include "core_cm7.h" - #define ARM_MATH_DSP -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" - #define ARM_MATH_DSP -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) - #include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_ARMV8MBL) - #include "core_armv8mbl.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_ARMV8MML) - #include "core_armv8mml.h" - #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) - #define ARM_MATH_DSP - #endif -#else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI - #define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined ( __CC_ARM ) - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __GNUC__ ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __ICCARM__ ) - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED - #define CMSIS_INLINE - -#elif defined ( __TI_ARM__ ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE - -#elif defined ( __CSMC__ ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED - #define CMSIS_INLINE - -#elif defined ( __TASKING__ ) - #define __SIMD32_TYPE __unaligned int32_t - #define CMSIS_UNUSED - #define CMSIS_INLINE - -#else - #error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ -#if !defined (ARM_MATH_DSP) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ -#endif /* !defined (ARM_MATH_DSP) */ - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - -/* - #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) - #define __CLZ __clz - #endif - */ -/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) - CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ( - q31_t data); - - CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while ((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - } -#endif - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - q31_t out; - uint32_t tempVal; - uint32_t index, i; - uint32_t signBits; - - if (in > 0) - { - signBits = ((uint32_t) (__CLZ( in) - 1)); - } - else - { - signBits = ((uint32_t) (__CLZ(-in) - 1)); - } - - /* Convert input sample to 1.31 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 24); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q63_t) in * out) >> 31); - tempVal = 0x7FFFFFFFu - tempVal; - /* 1.31 with exp 1 */ - /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ - out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - } - - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - q15_t out = 0; - uint32_t tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if (in > 0) - { - signBits = ((uint32_t)(__CLZ( in) - 17)); - } - else - { - signBits = ((uint32_t)(__CLZ(-in) - 17)); - } - - /* Convert input sample to 1.15 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 8); - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFFu - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - CMSIS_INLINE __STATIC_INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if (x > 0) - { - posMax = (posMax - 1); - - if (x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if (x < negMin) - { - x = negMin; - } - } - return (x); - } -#endif /* end of ARM_MATH_CM0_FAMILY */ - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ -#if !defined (ARM_MATH_DSP) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( - uint32_t x, - uint32_t y) - { -/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ - q31_t r = 0, s = 0; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE int32_t __QADD( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); - } - - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); - } - - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( - uint32_t x) - { - return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | - ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); - } - - /* - * @brief C custom defined SMMLA for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( - int32_t x, - int32_t y, - int32_t sum) - { - return (sum + (int32_t) (((int64_t) x * y) >> 32)); - } - -#if 0 - /* - * @brief C custom defined PKHBT for unavailable DSP extension - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT( - uint32_t x, - uint32_t y, - uint32_t leftshift) - { - return ( ((x ) & 0x0000FFFFUL) | - ((y << leftshift) & 0xFFFF0000UL) ); - } - - /* - * @brief C custom defined PKHTB for unavailable DSP extension - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB( - uint32_t x, - uint32_t y, - uint32_t rightshift) - { - return ( ((x ) & 0xFFFF0000UL) | - ((y >> rightshift) & 0x0000FFFFUL) ); - } -#endif - -/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ -#endif /* !defined (ARM_MATH_DSP) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] S points to an instance of the Q7 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] S points to an instance of the Q15 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] S points to an instance of the Q31 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] S points to an instance of the floating-point FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q15; - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_casd_df1_inst_f32; - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q31; - - - /** - * @brief Floating-point matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); - - - /** - * @brief Q31, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q31 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix scaling. - * @param[in] pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - - /** - * @brief Q15 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#if !defined (ARM_MATH_DSP) - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] S points to an instance of the q15 PID Control structure - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - -/* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] S points to an instance of the Q31 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] S points to an instance of the Q15 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - - /** - * @brief Floating-point vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Dot product of floating-point vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - - /** - * @brief Dot product of Q7 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - - /** - * @brief Dot product of Q15 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Dot product of Q31 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_f32; - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] S points to an instance of the floating-point FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the Q15 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - */ - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q31; - - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Correlation of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] S points to an instance of the floating-point sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] S points to an instance of the Q31 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] S points to an instance of the Q15 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] S points to an instance of the Q7 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cos output. - */ - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCosVal); - - - /** - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cosine output. - */ - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#if defined (ARM_MATH_DSP) - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - */ - CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - } - - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; - } - - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * The function implements the forward Park transform. - * - */ - CMSIS_INLINE __STATIC_INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - } - - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if (i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if ((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (q31_t)0xFFF00000) >> 20); - - if (index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if (index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - } - } - - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (int32_t)0xFFF00000) >> 20); - - if (index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if (index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (q15_t) (y >> 20); - } - } - - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - if (index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (q7_t) (y >> 20); - } - } - - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - float32_t arm_sin_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q31_t arm_sin_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q15_t arm_sin_q15( - q15_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - float32_t arm_cos_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q31_t arm_cos_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if (in >= 0.0f) - { - -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined(__GNUC__) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) - __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - /** - * @brief floating-point Circular write function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q15 Circular write function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q15 Circular Read function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q7 Circular Read function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - - /** - * @brief Mean value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Mean value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Floating-point complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - - /** - * @brief Q31 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - - /** - * @brief Floating-point complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - */ - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[in] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - } - - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; - x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; - y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return ((q31_t)(acc << 2)); - } - - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return ((q15_t)(acc >> 36)); - } - - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return ((q7_t)(acc >> 40)); - } - - /** - * @} end of BilinearInterpolate group - */ - - -/* SMMLAR */ -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMLSR */ -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMULR */ -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -/* SMMLA */ -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -/* SMMLS */ -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -/* SMMUL */ -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - -#if defined ( __CC_ARM ) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif - - /* Enter low optimization region - place directly above function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __GNUC__ ) - #define LOW_OPTIMIZATION_ENTER \ - __attribute__(( optimize("-O1") )) - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __ICCARM__ ) - /* Enter low optimization region - place directly above function definition */ - #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define LOW_OPTIMIZATION_EXIT - - /* Enter low optimization region - place directly above function definition */ - #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __TI_ARM__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __CSMC__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __TASKING__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - -#ifdef __cplusplus -} -#endif - -/* Compiler specific diagnostic adjustment */ -#if defined ( __CC_ARM ) - -#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - -#elif defined ( __GNUC__ ) -#pragma GCC diagnostic pop - -#elif defined ( __ICCARM__ ) - -#elif defined ( __TI_ARM__ ) - -#elif defined ( __CSMC__ ) - -#elif defined ( __TASKING__ ) - -#else - #error Unknown compiler -#endif - -#endif /* _ARM_MATH_H */ - -/** - * - * End of file. - */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_armcc.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_armcc.h deleted file mode 100644 index 1d6a5fbd5c5..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_armcc.h +++ /dev/null @@ -1,814 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS compiler ARMCC (ARM compiler V5) header file - * @version V5.0.2 - * @date 13. February 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* CMSIS compiler control architecture macros */ -#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ - (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) - #define __ARM_ARCH_6M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) - #define __ARM_ARCH_7M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) - #define __ARM_ARCH_7EM__ 1 -#endif - - /* __ARM_ARCH_8M_BASE__ not applicable */ - /* __ARM_ARCH_8M_MAIN__ not applicable */ - - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __declspec(noreturn) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed)) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT __packed struct -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION __packed union -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1U); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#else - (void)fpscr; -#endif -} - -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return(result); -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_armcc_V6.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_armcc_V6.h deleted file mode 100644 index cd13240ce36..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_armcc_V6.h +++ /dev/null @@ -1,1800 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc_V6.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_ARMCC_V6_H -#define __CMSIS_ARMCC_V6_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get IPSR Register (non-secure) - \details Returns the content of the non-secure IPSR Register when in secure state. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get APSR Register (non-secure) - \details Returns the content of the non-secure APSR Register when in secure state. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get xPSR Register (non-secure) - \details Returns the content of the non-secure xPSR Register when in secure state. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Base Priority with condition (non_secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) -{ - __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); -} -#endif - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - - -#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - -#if (__ARM_ARCH_8M__ == 1U) - -/** - \brief Get Process Stack Pointer Limit - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Get Process Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Get Main Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Set Main Stack Pointer Limit (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -} -#endif - -#endif /* (__ARM_ARCH_8M__ == 1U) */ - - -#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ - -/** - \brief Get FPSCR - \details eturns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#define __get_FPSCR __builtin_arm_get_fpscr -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} -#endif - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get FPSCR (non-secure) - \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. - \return Floating Point Status/Control register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} -#endif - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#define __set_FPSCR __builtin_arm_set_fpscr -#if 0 -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} -#endif - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set FPSCR (non-secure) - \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} -#endif - -#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF); - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF); - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF); - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __builtin_bswap32 - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} -#endif - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -/*#define __SSAT __builtin_arm_ssat*/ -#define __SSAT(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat -#if 0 -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) -#endif - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - -#if (__ARM_ARCH_8M__ == 1U) - -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* (__ARM_ARCH_8M__ == 1U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1U) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_V6_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_armclang.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_armclang.h deleted file mode 100644 index 2148297082b..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_armclang.h +++ /dev/null @@ -1,1802 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armclang.h - * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file - * @version V5.0.3 - * @date 27. March 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#ifndef __ARM_COMPAT_H -#include /* Compatibility header for ARM Compiler 5 intrinsics */ -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); see arm_compat.h */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); see arm_compat.h */ - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return(result); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Get Process Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - - return(result); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Get Main Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Set Main Stack Pointer Limit (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -/* #define __get_FPSCR __builtin_arm_get_fpscr */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -/* #define __set_FPSCR __builtin_arm_set_fpscr */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory"); -#else - (void)fpscr; -#endif -} - -#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF); - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF); - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF); - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __builtin_bswap32 - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */ -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} -#endif - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __builtin_arm_ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_compiler.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_compiler.h deleted file mode 100644 index 0f703ff9f20..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_compiler.h +++ /dev/null @@ -1,353 +0,0 @@ -/**************************************************************************//** - * @file cmsis_compiler.h - * @brief CMSIS compiler generic header file - * @version V5.0.2 - * @date 13. February 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_COMPILER_H -#define __CMSIS_COMPILER_H - -#include - -/* - * ARM Compiler 4/5 - */ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - - -/* - * ARM Compiler 6 (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armclang.h" - - -/* - * GNU Compiler - */ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - - -/* - * IAR Compiler - */ -#elif defined ( __ICCARM__ ) - - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - - #include - - /* CMSIS compiler control architecture macros */ - #if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__) - #ifndef __ARM_ARCH_6M__ - #define __ARM_ARCH_6M__ 1 - #endif - #elif (__CORE__ == __ARM7M__) - #ifndef __ARM_ARCH_7M__ - #define __ARM_ARCH_7M__ 1 - #endif - #elif (__CORE__ == __ARM7EM__) - #ifndef __ARM_ARCH_7EM__ - #define __ARM_ARCH_7EM__ 1 - #endif - #endif - - #ifndef __NO_RETURN - #define __NO_RETURN __noreturn - #endif - #ifndef __USED - #define __USED __root - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __PACKED - #define __PACKED __packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT __packed struct - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION __packed union - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - __packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - // Workaround for missing __CLZ intrinsic in - // various versions of the IAR compilers. - // __IAR_FEATURE_CLZ__ should be defined by - // the compiler that supports __CLZ internally. - #if (defined (__ARM_ARCH_6M__)) && (__ARM_ARCH_6M__ == 1) && (!defined (__IAR_FEATURE_CLZ__)) - __STATIC_INLINE uint32_t __CLZ(uint32_t data) - { - if (data == 0u) { return 32u; } - - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while ((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - } - #endif - - -/* - * TI ARM Compiler - */ -#elif defined ( __TI_ARM__ ) - #include - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __attribute__((packed)) - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed)) - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed)) - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - -/* - * TASKING Compiler - */ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __packed__ - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __packed__ - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __packed__ - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __packed__ T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __align(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - -/* - * COSMIC Compiler - */ -#elif defined ( __CSMC__ ) - #include - - #ifndef __ASM - #define __ASM _asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __NO_RETURN - // NO RETURN is automatically detected hence no warning here - #define __NO_RETURN - #endif - #ifndef __USED - #warning No compiler specific solution for __USED. __USED is ignored. - #define __USED - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __PACKED - #define __PACKED @packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT @packed struct - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION @packed union - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - @packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - -#else - #error Unknown compiler. -#endif - - -#endif /* __CMSIS_COMPILER_H */ - diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_gcc.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_gcc.h deleted file mode 100644 index 05f75703940..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_gcc.h +++ /dev/null @@ -1,1979 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS compiler GCC header file - * @version V5.0.2 - * @date 13. February 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -/* Fallback for __has_builtin */ -#ifndef __has_builtin - #define __has_builtin(x) (0) -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return(result); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Get Process Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - - return(result); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Get Main Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Set Main Stack Pointer Limit (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - return __builtin_arm_get_fpscr(); -#else - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#endif -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - __builtin_arm_set_fpscr(fpscr); -#else - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); -#endif -#else - (void)fpscr; -#endif -} - -#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -//{ -// __ASM volatile ("nop"); -//} -#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */ - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -//{ -// __ASM volatile ("wfi"); -//} -#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */ - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -//{ -// __ASM volatile ("wfe"); -//} -#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */ - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -//{ -// __ASM volatile ("sev"); -//} -#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */ - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */ - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#pragma GCC diagnostic pop - -#endif /* __CMSIS_GCC_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_version.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_version.h deleted file mode 100644 index d458a6c8599..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_version.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************//** - * @file cmsis_version.h - * @brief CMSIS Core(M) Version definitions - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CMSIS_VERSION_H -#define __CMSIS_VERSION_H - -/* CMSIS Version definitions */ -#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS Core(M) sub version */ -#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ - __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ -#endif diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_armv8mbl.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_armv8mbl.h deleted file mode 100644 index 13003e1cd62..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_armv8mbl.h +++ /dev/null @@ -1,1878 +0,0 @@ -/**************************************************************************//** - * @file core_armv8mbl.h - * @brief CMSIS ARMv8MBL Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_ARMV8MBL_H_GENERIC -#define __CORE_ARMV8MBL_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MBL - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS definitions */ -#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MBL_H_DEPENDANT -#define __CORE_ARMV8MBL_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv8MBL_REV - #define __ARMv8MBL_REV 0x0000U - #warning "__ARMv8MBL_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif - - #ifndef __ETM_PRESENT - #define __ETM_PRESENT 0U - #warning "__ETM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MTB_PRESENT - #define __MTB_PRESENT 0U - #warning "__MTB_PRESENT not defined in device header file; using default!" - #endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MBL */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for ARMv8-M Baseline */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for ARMv8-M Baseline */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_armv8mml.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_armv8mml.h deleted file mode 100644 index 5c4d6f6ee17..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_armv8mml.h +++ /dev/null @@ -1,2902 +0,0 @@ -/**************************************************************************//** - * @file core_armv8mml.h - * @brief CMSIS ARMv8MML Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_ARMV8MML_H_GENERIC -#define __CORE_ARMV8MML_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MML - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS ARMv8MML definitions */ -#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (81U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MML_H_DEPENDANT -#define __CORE_ARMV8MML_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv8MML_REV - #define __ARMv8MML_REV 0x0000U - #warning "__ARMv8MML_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MML */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm0.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm0.h deleted file mode 100644 index 2f63b68610b..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm0.h +++ /dev/null @@ -1,888 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M0 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000U - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - Address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)0x0U; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)0x0U; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm0plus.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm0plus.h deleted file mode 100644 index 5c6135802bb..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm0plus.h +++ /dev/null @@ -1,1021 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000U - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; - -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm23.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm23.h deleted file mode 100644 index b97fa9dd3f0..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm23.h +++ /dev/null @@ -1,1878 +0,0 @@ -/**************************************************************************//** - * @file core_cm23.h - * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM23_H_GENERIC -#define __CORE_CM23_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M23 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS definitions */ -#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ - __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (23U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM23_H_DEPENDANT -#define __CORE_CM23_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM23_REV - #define __CM23_REV 0x0000U - #warning "__CM23_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif - - #ifndef __ETM_PRESENT - #define __ETM_PRESENT 0U - #warning "__ETM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MTB_PRESENT - #define __MTB_PRESENT 0U - #warning "__MTB_PRESENT not defined in device header file; using default!" - #endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M23 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm3.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm3.h deleted file mode 100644 index 3c1f01f497b..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm3.h +++ /dev/null @@ -1,1928 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M3 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (3U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200U - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1U]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm33.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm33.h deleted file mode 100644 index fab2f9a1184..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm33.h +++ /dev/null @@ -1,2898 +0,0 @@ -/**************************************************************************//** - * @file core_cm33.h - * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM33_H_GENERIC -#define __CORE_CM33_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M33 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM33 definitions */ -#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ - __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (33U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM33_H_DEPENDANT -#define __CORE_CM33_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM33_REV - #define __CM33_REV 0x0000U - #warning "__CM33_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M33 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm4.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm4.h deleted file mode 100644 index ad3bc27d587..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,2113 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M4 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (4U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000U - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm7.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm7.h deleted file mode 100644 index bf701fe8ef4..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm7.h +++ /dev/null @@ -1,2655 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M7 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (7U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000U - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0U - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1U]; - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = SCB->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## Cache functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_INLINE void SCB_EnableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_INLINE void SCB_DisableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_INLINE void SCB_InvalidateICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_INLINE void SCB_EnableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_INLINE void SCB_DisableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - register uint32_t ccsidr; - register uint32_t sets; - register uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_INLINE void SCB_InvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_INLINE void SCB_CleanDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_INLINE void SCB_CleanInvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t)addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCIMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCIMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cmFunc.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cmFunc.h deleted file mode 100644 index 652a48af07a..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cmFunc.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cmInstr.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cmInstr.h deleted file mode 100644 index f474b0e6f36..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cmInstr.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cmSimd.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cmSimd.h deleted file mode 100644 index 66bf5c2a725..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cmSimd.h +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************//** - * @file core_cmSimd.h - * @brief CMSIS Cortex-M SIMD Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMSIMD_H -#define __CORE_CMSIMD_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CMSIMD_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_sc000.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_sc000.h deleted file mode 100644 index bd26eaa0db9..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_sc000.h +++ /dev/null @@ -1,1016 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC000 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_SC (000U) /*!< Cortex secure core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000U - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the SC000 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_sc300.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_sc300.h deleted file mode 100644 index 780372a350c..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_sc300.h +++ /dev/null @@ -1,1903 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC3000 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_SC (300U) /*!< Cortex secure core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000U - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED1[129U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1U]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/mpu_armv7.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/mpu_armv7.h deleted file mode 100644 index fb1a339bec1..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/mpu_armv7.h +++ /dev/null @@ -1,182 +0,0 @@ -/****************************************************************************** - * @file mpu_armv7.h - * @brief CMSIS MPU API for ARMv7 MPU - * @version V5.0.2 - * @date 09. June 2017 - ******************************************************************************/ -/* - * Copyright (c) 2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARM_MPU_ARMV7_H -#define ARM_MPU_ARMV7_H - -#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) -#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) -#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) -#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) -#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) -#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) -#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) -#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) -#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) -#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) -#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) -#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) -#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) -#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) -#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) -#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) -#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) -#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) -#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) -#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) -#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) -#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) -#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) -#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) -#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) -#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) -#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) -#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) - -#define ARM_MPU_AP_NONE 0u -#define ARM_MPU_AP_PRIV 1u -#define ARM_MPU_AP_URO 2u -#define ARM_MPU_AP_FULL 3u -#define ARM_MPU_AP_PRO 5u -#define ARM_MPU_AP_RO 6u - -/** MPU Region Base Address Register Value -* -* \param Region The region to be configured, number 0 to 15. -* \param BaseAddress The base address for the region. -*/ -#define ARM_MPU_RBAR(Region, BaseAddress) ((BaseAddress & MPU_RBAR_ADDR_Msk) | (Region & MPU_RBAR_REGION_Msk) | (1UL << MPU_RBAR_VALID_Pos)) - -/** -* MPU Region Attribut and Size Register Value -* -* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. -* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. -* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. -* \param IsShareable Region is shareable between multiple bus masters. -* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. -* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -* \param SubRegionDisable Sub-region disable field. -* \param Size Region size of the region to be configured, for example 4K, 8K. -*/ -#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ - ((DisableExec << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ - ((AccessPermission << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ - ((TypeExtField << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ - ((IsShareable << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ - ((IsCacheable << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ - ((IsBufferable << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \ - ((SubRegionDisable << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ - ((Size << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ - ((1UL << MPU_RASR_ENABLE_Pos) & MPU_RASR_ENABLE_Msk) - - -/** -* Struct for a single MPU Region -*/ -typedef struct _ARM_MPU_Region_t { - uint32_t RBAR; //!< The region base address register value (RBAR) - uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DSB(); - __ISB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable() -{ - __DSB(); - __ISB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - MPU->RNR = rnr; - MPU->RASR = 0u; -} - -/** Configure an MPU region. -* \param rbar Value for RBAR register. -* \param rsar Value for RSAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) -{ - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rsar Value for RSAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) -{ - MPU->RNR = rnr; - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Memcopy with strictly ordered memory access, e.g. for register targets. -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0u; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) -{ - orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*sizeof(ARM_MPU_Region_t)/4u); -} - -#endif diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/tz_context.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/tz_context.h deleted file mode 100644 index 0784d26cac9..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/tz_context.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2015-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------------- - * - * $Date: 21. September 2016 - * $Revision: V1.0 - * - * Project: TrustZone for ARMv8-M - * Title: Context Management for ARMv8-M TrustZone - * - * Version 1.0 - * Initial Release - *---------------------------------------------------------------------------*/ - -#ifndef TZ_CONTEXT_H -#define TZ_CONTEXT_H - -#include - -#ifndef TZ_MODULEID_T -#define TZ_MODULEID_T -/// \details Data type that identifies secure software modules called by a process. -typedef uint32_t TZ_ModuleId_t; -#endif - -/// \details TZ Memory ID identifies an allocated memory slot. -typedef uint32_t TZ_MemoryId_t; - -/// Initialize secure context memory system -/// \return execution status (1: success, 0: error) -uint32_t TZ_InitContextSystem_S (void); - -/// Allocate context memory for calling secure software modules in TrustZone -/// \param[in] module identifies software modules called from non-secure mode -/// \return value != 0 id TrustZone memory slot identifier -/// \return value 0 no memory available or internal error -TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); - -/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); - -/// Load secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); - -/// Store secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); - -#endif // TZ_CONTEXT_H diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/SConscript b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/SConscript deleted file mode 100644 index 4c815c49b83..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/SConscript +++ /dev/null @@ -1,15 +0,0 @@ -# RT-Thread building script for bridge - -import os -from building import * - -cwd = GetCurrentDir() -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/SConscript b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/SConscript deleted file mode 100644 index 4c815c49b83..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/SConscript +++ /dev/null @@ -1,15 +0,0 @@ -# RT-Thread building script for bridge - -import os -from building import * - -cwd = GetCurrentDir() -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/LPC54608.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/LPC54608.h deleted file mode 100644 index b0d51d03b8b..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/LPC54608.h +++ /dev/null @@ -1,12371 +0,0 @@ -/* -** ################################################################### -** Processors: LPC54608J512BD208 -** LPC54608J512ET180 -** -** Compilers: Keil ARM C/C++ Compiler -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: LPC54S60x/LPC5460x User manual Rev.0.9 7 Nov 2016 -** Version: rev. 1.1, 2016-11-25 -** Build: b170214 -** -** Abstract: -** CMSIS Peripheral Access Layer for LPC54608 -** -** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2016-08-12) -** Initial version. -** - rev. 1.1 (2016-11-25) -** Update CANFD and Classic CAN register. -** Add MAC TIMERSTAMP registers. -** -** ################################################################### -*/ - -/*! - * @file LPC54608.h - * @version 1.1 - * @date 2016-11-25 - * @brief CMSIS Peripheral Access Layer for LPC54608 - * - * CMSIS Peripheral Access Layer for LPC54608 - */ - -#ifndef _LPC54608_H_ -#define _LPC54608_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0001U - - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 73 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Auxiliary constants */ - NotAvail_IRQn = -128, /**< Not available device specific interrupt */ - - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ - - /* Device specific interrupts */ - WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */ - DMA0_IRQn = 1, /**< DMA controller */ - GINT0_IRQn = 2, /**< GPIO group 0 */ - GINT1_IRQn = 3, /**< GPIO group 1 */ - PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ - PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ - PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ - PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ - UTICK0_IRQn = 8, /**< Micro-tick Timer */ - MRT0_IRQn = 9, /**< Multi-rate timer */ - CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ - CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ - SCT0_IRQn = 12, /**< SCTimer/PWM */ - CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ - FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */ - FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */ - FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */ - FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */ - FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */ - FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */ - FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */ - FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */ - ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */ - ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */ - ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */ - DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */ - HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */ - USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ - USB0_IRQn = 28, /**< USB device */ - RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ - Reserved46_IRQn = 30, /**< Reserved interrupt */ - Reserved47_IRQn = 31, /**< Reserved interrupt */ - PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ - PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ - PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ - PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ - CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ - CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ - RIT_IRQn = 38, /**< Repetitive Interrupt Timer */ - SPIFI0_IRQn = 39, /**< SPI flash interface */ - FLEXCOMM8_IRQn = 40, /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */ - FLEXCOMM9_IRQn = 41, /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */ - SDIO_IRQn = 42, /**< SD/MMC */ - CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */ - CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */ - CAN1_IRQ0_IRQn = 45, /**< CAN1 interrupt0 */ - CAN1_IRQ1_IRQn = 46, /**< CAN1 interrupt1 */ - USB1_IRQn = 47, /**< USB1 interrupt */ - USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ - ETHERNET_IRQn = 49, /**< Ethernet */ - ETHERNET_PMT_IRQn = 50, /**< Ethernet power management interrupt */ - ETHERNET_MACLP_IRQn = 51, /**< Ethernet MAC interrupt */ - EEPROM_IRQn = 52, /**< EEPROM interrupt */ - LCD_IRQn = 53, /**< LCD interrupt */ - SHA_IRQn = 54, /**< SHA interrupt */ - SMARTCARD0_IRQn = 55, /**< Smart card 0 interrupt */ - SMARTCARD1_IRQn = 56 /**< Smart card 1 interrupt */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M4 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration - * @{ - */ - -#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ -#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ - -#include "core_cm4.h" /* Core Peripheral Access Layer */ -#include "system_LPC54608.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Mapping Information - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Mapping_Information Mapping Information - * @{ - */ - -/** Mapping Information */ - -/*! - * @} - */ /* end of group Mapping_Information */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */ - __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */ - __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */ - __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */ - uint8_t RESERVED_0[8]; - __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */ - __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */ - __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */ - __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */ - __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */ - __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */ - __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */ - __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */ - __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */ - __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */ -#define ADC_CTRL_CLKDIV_MASK (0xFFU) -#define ADC_CTRL_CLKDIV_SHIFT (0U) -#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK) -#define ADC_CTRL_ASYNMODE_MASK (0x100U) -#define ADC_CTRL_ASYNMODE_SHIFT (8U) -#define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK) -#define ADC_CTRL_RESOL_MASK (0x600U) -#define ADC_CTRL_RESOL_SHIFT (9U) -#define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK) -#define ADC_CTRL_BYPASSCAL_MASK (0x800U) -#define ADC_CTRL_BYPASSCAL_SHIFT (11U) -#define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK) -#define ADC_CTRL_TSAMP_MASK (0x7000U) -#define ADC_CTRL_TSAMP_SHIFT (12U) -#define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK) - -/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */ -#define ADC_INSEL_SEL_MASK (0x3U) -#define ADC_INSEL_SEL_SHIFT (0U) -#define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK) - -/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */ -#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU) -#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U) -#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK) -#define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U) -#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U) -#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK) -#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U) -#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U) -#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK) -#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U) -#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U) -#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK) -#define ADC_SEQ_CTRL_START_MASK (0x4000000U) -#define ADC_SEQ_CTRL_START_SHIFT (26U) -#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK) -#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U) -#define ADC_SEQ_CTRL_BURST_SHIFT (27U) -#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK) -#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U) -#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U) -#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK) -#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U) -#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U) -#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK) -#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U) -#define ADC_SEQ_CTRL_MODE_SHIFT (30U) -#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK) -#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U) -#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U) -#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK) - -/* The count of ADC_SEQ_CTRL */ -#define ADC_SEQ_CTRL_COUNT (2U) - -/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */ -#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U) -#define ADC_SEQ_GDAT_RESULT_SHIFT (4U) -#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK) -#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U) -#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U) -#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK) -#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U) -#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U) -#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK) -#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U) -#define ADC_SEQ_GDAT_CHN_SHIFT (26U) -#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK) -#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U) -#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U) -#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK) -#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U) -#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U) -#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK) - -/* The count of ADC_SEQ_GDAT */ -#define ADC_SEQ_GDAT_COUNT (2U) - -/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */ -#define ADC_DAT_RESULT_MASK (0xFFF0U) -#define ADC_DAT_RESULT_SHIFT (4U) -#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK) -#define ADC_DAT_THCMPRANGE_MASK (0x30000U) -#define ADC_DAT_THCMPRANGE_SHIFT (16U) -#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK) -#define ADC_DAT_THCMPCROSS_MASK (0xC0000U) -#define ADC_DAT_THCMPCROSS_SHIFT (18U) -#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK) -#define ADC_DAT_CHANNEL_MASK (0x3C000000U) -#define ADC_DAT_CHANNEL_SHIFT (26U) -#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK) -#define ADC_DAT_OVERRUN_MASK (0x40000000U) -#define ADC_DAT_OVERRUN_SHIFT (30U) -#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK) -#define ADC_DAT_DATAVALID_MASK (0x80000000U) -#define ADC_DAT_DATAVALID_SHIFT (31U) -#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK) - -/* The count of ADC_DAT */ -#define ADC_DAT_COUNT (12U) - -/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ -#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U) -#define ADC_THR0_LOW_THRLOW_SHIFT (4U) -#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK) - -/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ -#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U) -#define ADC_THR1_LOW_THRLOW_SHIFT (4U) -#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK) - -/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ -#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U) -#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U) -#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK) - -/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ -#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U) -#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U) -#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK) - -/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */ -#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U) -#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U) -#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U) -#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U) -#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U) -#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U) -#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U) -#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U) -#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U) -#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U) -#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U) -#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U) -#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U) -#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U) -#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U) -#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U) -#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U) -#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U) -#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U) -#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U) -#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U) -#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U) -#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U) -#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U) -#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK) - -/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */ -#define ADC_INTEN_SEQA_INTEN_MASK (0x1U) -#define ADC_INTEN_SEQA_INTEN_SHIFT (0U) -#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK) -#define ADC_INTEN_SEQB_INTEN_MASK (0x2U) -#define ADC_INTEN_SEQB_INTEN_SHIFT (1U) -#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK) -#define ADC_INTEN_OVR_INTEN_MASK (0x4U) -#define ADC_INTEN_OVR_INTEN_SHIFT (2U) -#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK) -#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U) -#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U) -#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK) -#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U) -#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U) -#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK) -#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U) -#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U) -#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK) -#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U) -#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U) -#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK) -#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U) -#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U) -#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK) -#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U) -#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U) -#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK) -#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U) -#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U) -#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK) -#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U) -#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U) -#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK) -#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U) -#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U) -#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK) -#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U) -#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U) -#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK) -#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U) -#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U) -#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK) -#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U) -#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U) -#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK) - -/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */ -#define ADC_FLAGS_THCMP0_MASK (0x1U) -#define ADC_FLAGS_THCMP0_SHIFT (0U) -#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK) -#define ADC_FLAGS_THCMP1_MASK (0x2U) -#define ADC_FLAGS_THCMP1_SHIFT (1U) -#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK) -#define ADC_FLAGS_THCMP2_MASK (0x4U) -#define ADC_FLAGS_THCMP2_SHIFT (2U) -#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK) -#define ADC_FLAGS_THCMP3_MASK (0x8U) -#define ADC_FLAGS_THCMP3_SHIFT (3U) -#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK) -#define ADC_FLAGS_THCMP4_MASK (0x10U) -#define ADC_FLAGS_THCMP4_SHIFT (4U) -#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK) -#define ADC_FLAGS_THCMP5_MASK (0x20U) -#define ADC_FLAGS_THCMP5_SHIFT (5U) -#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK) -#define ADC_FLAGS_THCMP6_MASK (0x40U) -#define ADC_FLAGS_THCMP6_SHIFT (6U) -#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK) -#define ADC_FLAGS_THCMP7_MASK (0x80U) -#define ADC_FLAGS_THCMP7_SHIFT (7U) -#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK) -#define ADC_FLAGS_THCMP8_MASK (0x100U) -#define ADC_FLAGS_THCMP8_SHIFT (8U) -#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK) -#define ADC_FLAGS_THCMP9_MASK (0x200U) -#define ADC_FLAGS_THCMP9_SHIFT (9U) -#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK) -#define ADC_FLAGS_THCMP10_MASK (0x400U) -#define ADC_FLAGS_THCMP10_SHIFT (10U) -#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK) -#define ADC_FLAGS_THCMP11_MASK (0x800U) -#define ADC_FLAGS_THCMP11_SHIFT (11U) -#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK) -#define ADC_FLAGS_OVERRUN0_MASK (0x1000U) -#define ADC_FLAGS_OVERRUN0_SHIFT (12U) -#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK) -#define ADC_FLAGS_OVERRUN1_MASK (0x2000U) -#define ADC_FLAGS_OVERRUN1_SHIFT (13U) -#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK) -#define ADC_FLAGS_OVERRUN2_MASK (0x4000U) -#define ADC_FLAGS_OVERRUN2_SHIFT (14U) -#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK) -#define ADC_FLAGS_OVERRUN3_MASK (0x8000U) -#define ADC_FLAGS_OVERRUN3_SHIFT (15U) -#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK) -#define ADC_FLAGS_OVERRUN4_MASK (0x10000U) -#define ADC_FLAGS_OVERRUN4_SHIFT (16U) -#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK) -#define ADC_FLAGS_OVERRUN5_MASK (0x20000U) -#define ADC_FLAGS_OVERRUN5_SHIFT (17U) -#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK) -#define ADC_FLAGS_OVERRUN6_MASK (0x40000U) -#define ADC_FLAGS_OVERRUN6_SHIFT (18U) -#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK) -#define ADC_FLAGS_OVERRUN7_MASK (0x80000U) -#define ADC_FLAGS_OVERRUN7_SHIFT (19U) -#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK) -#define ADC_FLAGS_OVERRUN8_MASK (0x100000U) -#define ADC_FLAGS_OVERRUN8_SHIFT (20U) -#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK) -#define ADC_FLAGS_OVERRUN9_MASK (0x200000U) -#define ADC_FLAGS_OVERRUN9_SHIFT (21U) -#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK) -#define ADC_FLAGS_OVERRUN10_MASK (0x400000U) -#define ADC_FLAGS_OVERRUN10_SHIFT (22U) -#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK) -#define ADC_FLAGS_OVERRUN11_MASK (0x800000U) -#define ADC_FLAGS_OVERRUN11_SHIFT (23U) -#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK) -#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U) -#define ADC_FLAGS_SEQA_OVR_SHIFT (24U) -#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK) -#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U) -#define ADC_FLAGS_SEQB_OVR_SHIFT (25U) -#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK) -#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U) -#define ADC_FLAGS_SEQA_INT_SHIFT (28U) -#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK) -#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U) -#define ADC_FLAGS_SEQB_INT_SHIFT (29U) -#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK) -#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U) -#define ADC_FLAGS_THCMP_INT_SHIFT (30U) -#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK) -#define ADC_FLAGS_OVR_INT_MASK (0x80000000U) -#define ADC_FLAGS_OVR_INT_SHIFT (31U) -#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK) - -/*! @name STARTUP - ADC Startup register. */ -#define ADC_STARTUP_ADC_ENA_MASK (0x1U) -#define ADC_STARTUP_ADC_ENA_SHIFT (0U) -#define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK) -#define ADC_STARTUP_ADC_INIT_MASK (0x2U) -#define ADC_STARTUP_ADC_INIT_SHIFT (1U) -#define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK) - -/*! @name CALIB - ADC Calibration register. */ -#define ADC_CALIB_CALIB_MASK (0x1U) -#define ADC_CALIB_CALIB_SHIFT (0U) -#define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK) -#define ADC_CALIB_CALREQD_MASK (0x2U) -#define ADC_CALIB_CALREQD_SHIFT (1U) -#define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK) -#define ADC_CALIB_CALVALUE_MASK (0x1FCU) -#define ADC_CALIB_CALVALUE_SHIFT (2U) -#define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK) - - -/*! - * @} - */ /* end of group ADC_Register_Masks */ - - -/* ADC - Peripheral instance base addresses */ -/** Peripheral ADC0 base address */ -#define ADC0_BASE (0x400A0000u) -/** Peripheral ADC0 base pointer */ -#define ADC0 ((ADC_Type *)ADC0_BASE) -/** Array initializer of ADC peripheral base addresses */ -#define ADC_BASE_ADDRS { ADC0_BASE } -/** Array initializer of ADC peripheral base pointers */ -#define ADC_BASE_PTRS { ADC0 } -/** Interrupt vectors for the ADC peripheral type */ -#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn } -#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn } - -/*! - * @} - */ /* end of group ADC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ASYNC_SYSCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer - * @{ - */ - -/** ASYNC_SYSCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */ - __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */ - __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */ - __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */ - __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */ - uint8_t RESERVED_1[4]; - __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */ -} ASYNC_SYSCON_Type; - -/* ---------------------------------------------------------------------------- - -- ASYNC_SYSCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks - * @{ - */ - -/*! @name ASYNCPRESETCTRL - Async peripheral reset control */ -#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U) -#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U) -#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK) -#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U) -#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U) -#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK) - -/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */ -#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU) -#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U) -#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK) - -/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */ -#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU) -#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U) -#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK) - -/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */ -#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK) - -/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */ -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK) - -/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */ -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK) - -/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */ -#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U) -#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U) -#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK) - - -/*! - * @} - */ /* end of group ASYNC_SYSCON_Register_Masks */ - - -/* ASYNC_SYSCON - Peripheral instance base addresses */ -/** Peripheral ASYNC_SYSCON base address */ -#define ASYNC_SYSCON_BASE (0x40040000u) -/** Peripheral ASYNC_SYSCON base pointer */ -#define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE) -/** Array initializer of ASYNC_SYSCON peripheral base addresses */ -#define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE } -/** Array initializer of ASYNC_SYSCON peripheral base pointers */ -#define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON } - -/*! - * @} - */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CAN Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer - * @{ - */ - -/** CAN - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[16]; - __IO uint32_t TEST; /**< Test Register, offset: 0x10 */ - uint8_t RESERVED_1[4]; - __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */ - __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */ - __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */ - __IO uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */ - __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */ - __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */ - uint8_t RESERVED_2[16]; - __I uint32_t ECR; /**< Error Counter Register, offset: 0x40 */ - __I uint32_t PSR; /**< Protocol Status Register, offset: 0x44 */ - __IO uint32_t TDCR; /**< Transmitter Delay Compensator Register, offset: 0x48 */ - uint8_t RESERVED_3[4]; - __IO uint32_t IR; /**< Interrupt Register, offset: 0x50 */ - __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */ - __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */ - __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */ - uint8_t RESERVED_4[32]; - __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */ - __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */ - __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */ - uint8_t RESERVED_5[4]; - __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */ - __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */ - __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */ - __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */ - __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */ - __IO uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */ - __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */ - __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */ - __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */ - __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */ - __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */ - __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */ - __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */ - __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */ - __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */ - __IO uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */ - __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */ - __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */ - __IO uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */ - __IO uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */ - __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */ - __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */ - uint8_t RESERVED_6[8]; - __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */ - __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */ - __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */ - uint8_t RESERVED_7[260]; - __IO uint32_t MRBA; /**< CAN Message RAM Base Address, offset: 0x200 */ - uint8_t RESERVED_8[508]; - __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */ - uint8_t RESERVED_9[508]; - __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */ -} CAN_Type; - -/* ---------------------------------------------------------------------------- - -- CAN Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CAN_Register_Masks CAN Register Masks - * @{ - */ - -/*! @name TEST - Test Register */ -#define CAN_TEST_LBCK_MASK (0x10U) -#define CAN_TEST_LBCK_SHIFT (4U) -#define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK) -#define CAN_TEST_TX_MASK (0x60U) -#define CAN_TEST_TX_SHIFT (5U) -#define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK) -#define CAN_TEST_RX_MASK (0x80U) -#define CAN_TEST_RX_SHIFT (7U) -#define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK) - -/*! @name CCCR - CC Control Register */ -#define CAN_CCCR_INIT_MASK (0x1U) -#define CAN_CCCR_INIT_SHIFT (0U) -#define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK) -#define CAN_CCCR_CCE_MASK (0x2U) -#define CAN_CCCR_CCE_SHIFT (1U) -#define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK) -#define CAN_CCCR_ASM_MASK (0x4U) -#define CAN_CCCR_ASM_SHIFT (2U) -#define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK) -#define CAN_CCCR_CSA_MASK (0x8U) -#define CAN_CCCR_CSA_SHIFT (3U) -#define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK) -#define CAN_CCCR_CSR_MASK (0x10U) -#define CAN_CCCR_CSR_SHIFT (4U) -#define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK) -#define CAN_CCCR_MON_MASK (0x20U) -#define CAN_CCCR_MON_SHIFT (5U) -#define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK) -#define CAN_CCCR_DAR_MASK (0x40U) -#define CAN_CCCR_DAR_SHIFT (6U) -#define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK) -#define CAN_CCCR_TEST_MASK (0x80U) -#define CAN_CCCR_TEST_SHIFT (7U) -#define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK) -#define CAN_CCCR_PXHD_MASK (0x1000U) -#define CAN_CCCR_PXHD_SHIFT (12U) -#define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK) -#define CAN_CCCR_EFBI_MASK (0x2000U) -#define CAN_CCCR_EFBI_SHIFT (13U) -#define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK) -#define CAN_CCCR_TXP_MASK (0x4000U) -#define CAN_CCCR_TXP_SHIFT (14U) -#define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK) - -/*! @name NBTP - Nominal Bit Timing and Prescaler Register */ -#define CAN_NBTP_NTSEG2_MASK (0x7FU) -#define CAN_NBTP_NTSEG2_SHIFT (0U) -#define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK) -#define CAN_NBTP_NTSEG1_MASK (0xFF00U) -#define CAN_NBTP_NTSEG1_SHIFT (8U) -#define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK) -#define CAN_NBTP_NBRP_MASK (0x1FF0000U) -#define CAN_NBTP_NBRP_SHIFT (16U) -#define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK) -#define CAN_NBTP_NSJW_MASK (0xFE000000U) -#define CAN_NBTP_NSJW_SHIFT (25U) -#define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK) - -/*! @name TSCC - Timestamp Counter Configuration */ -#define CAN_TSCC_TSS_MASK (0x3U) -#define CAN_TSCC_TSS_SHIFT (0U) -#define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK) -#define CAN_TSCC_TCP_MASK (0xF0000U) -#define CAN_TSCC_TCP_SHIFT (16U) -#define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK) - -/*! @name TSCV - Timestamp Counter Value */ -#define CAN_TSCV_TSC_MASK (0xFFFFU) -#define CAN_TSCV_TSC_SHIFT (0U) -#define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK) - -/*! @name TOCC - Timeout Counter Configuration */ -#define CAN_TOCC_ETOC_MASK (0x1U) -#define CAN_TOCC_ETOC_SHIFT (0U) -#define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK) -#define CAN_TOCC_TOS_MASK (0x6U) -#define CAN_TOCC_TOS_SHIFT (1U) -#define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK) -#define CAN_TOCC_TOP_MASK (0xFFFF0000U) -#define CAN_TOCC_TOP_SHIFT (16U) -#define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK) - -/*! @name TOCV - Timeout Counter Value */ -#define CAN_TOCV_TOC_MASK (0xFFFFU) -#define CAN_TOCV_TOC_SHIFT (0U) -#define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK) - -/*! @name ECR - Error Counter Register */ -#define CAN_ECR_TEC_MASK (0xFFU) -#define CAN_ECR_TEC_SHIFT (0U) -#define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK) -#define CAN_ECR_REC_MASK (0x7F00U) -#define CAN_ECR_REC_SHIFT (8U) -#define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK) -#define CAN_ECR_RP_MASK (0x8000U) -#define CAN_ECR_RP_SHIFT (15U) -#define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK) -#define CAN_ECR_CEL_MASK (0xFF0000U) -#define CAN_ECR_CEL_SHIFT (16U) -#define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK) - -/*! @name PSR - Protocol Status Register */ -#define CAN_PSR_LEC_MASK (0x7U) -#define CAN_PSR_LEC_SHIFT (0U) -#define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK) -#define CAN_PSR_ACT_MASK (0x18U) -#define CAN_PSR_ACT_SHIFT (3U) -#define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK) -#define CAN_PSR_EP_MASK (0x20U) -#define CAN_PSR_EP_SHIFT (5U) -#define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK) -#define CAN_PSR_EW_MASK (0x40U) -#define CAN_PSR_EW_SHIFT (6U) -#define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK) -#define CAN_PSR_BO_MASK (0x80U) -#define CAN_PSR_BO_SHIFT (7U) -#define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK) -#define CAN_PSR_PXE_MASK (0x4000U) -#define CAN_PSR_PXE_SHIFT (14U) -#define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK) -#define CAN_PSR_TDCV_MASK (0x7F0000U) -#define CAN_PSR_TDCV_SHIFT (16U) -#define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK) - -/*! @name TDCR - Transmitter Delay Compensator Register */ -#define CAN_TDCR_TDCF_MASK (0x7FU) -#define CAN_TDCR_TDCF_SHIFT (0U) -#define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK) -#define CAN_TDCR_TDCO_MASK (0x7F00U) -#define CAN_TDCR_TDCO_SHIFT (8U) -#define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK) - -/*! @name IR - Interrupt Register */ -#define CAN_IR_RF0N_MASK (0x1U) -#define CAN_IR_RF0N_SHIFT (0U) -#define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK) -#define CAN_IR_RF0W_MASK (0x2U) -#define CAN_IR_RF0W_SHIFT (1U) -#define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK) -#define CAN_IR_RF0F_MASK (0x4U) -#define CAN_IR_RF0F_SHIFT (2U) -#define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK) -#define CAN_IR_RF0L_MASK (0x8U) -#define CAN_IR_RF0L_SHIFT (3U) -#define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK) -#define CAN_IR_RF1N_MASK (0x10U) -#define CAN_IR_RF1N_SHIFT (4U) -#define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK) -#define CAN_IR_RF1W_MASK (0x20U) -#define CAN_IR_RF1W_SHIFT (5U) -#define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK) -#define CAN_IR_RF1F_MASK (0x40U) -#define CAN_IR_RF1F_SHIFT (6U) -#define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK) -#define CAN_IR_RF1L_MASK (0x80U) -#define CAN_IR_RF1L_SHIFT (7U) -#define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK) -#define CAN_IR_HPM_MASK (0x100U) -#define CAN_IR_HPM_SHIFT (8U) -#define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK) -#define CAN_IR_TC_MASK (0x200U) -#define CAN_IR_TC_SHIFT (9U) -#define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK) -#define CAN_IR_TCF_MASK (0x400U) -#define CAN_IR_TCF_SHIFT (10U) -#define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK) -#define CAN_IR_TFE_MASK (0x800U) -#define CAN_IR_TFE_SHIFT (11U) -#define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK) -#define CAN_IR_TEFN_MASK (0x1000U) -#define CAN_IR_TEFN_SHIFT (12U) -#define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK) -#define CAN_IR_TEFW_MASK (0x2000U) -#define CAN_IR_TEFW_SHIFT (13U) -#define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK) -#define CAN_IR_TEFF_MASK (0x4000U) -#define CAN_IR_TEFF_SHIFT (14U) -#define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK) -#define CAN_IR_TEFL_MASK (0x8000U) -#define CAN_IR_TEFL_SHIFT (15U) -#define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK) -#define CAN_IR_TSW_MASK (0x10000U) -#define CAN_IR_TSW_SHIFT (16U) -#define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK) -#define CAN_IR_MRAF_MASK (0x20000U) -#define CAN_IR_MRAF_SHIFT (17U) -#define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK) -#define CAN_IR_TOO_MASK (0x40000U) -#define CAN_IR_TOO_SHIFT (18U) -#define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK) -#define CAN_IR_DRX_MASK (0x80000U) -#define CAN_IR_DRX_SHIFT (19U) -#define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK) -#define CAN_IR_BEC_MASK (0x100000U) -#define CAN_IR_BEC_SHIFT (20U) -#define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK) -#define CAN_IR_BEU_MASK (0x200000U) -#define CAN_IR_BEU_SHIFT (21U) -#define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK) -#define CAN_IR_ELO_MASK (0x400000U) -#define CAN_IR_ELO_SHIFT (22U) -#define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK) -#define CAN_IR_EP_MASK (0x800000U) -#define CAN_IR_EP_SHIFT (23U) -#define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK) -#define CAN_IR_EW_MASK (0x1000000U) -#define CAN_IR_EW_SHIFT (24U) -#define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK) -#define CAN_IR_BO_MASK (0x2000000U) -#define CAN_IR_BO_SHIFT (25U) -#define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK) -#define CAN_IR_WDI_MASK (0x4000000U) -#define CAN_IR_WDI_SHIFT (26U) -#define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK) -#define CAN_IR_PEA_MASK (0x8000000U) -#define CAN_IR_PEA_SHIFT (27U) -#define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK) -#define CAN_IR_PED_MASK (0x10000000U) -#define CAN_IR_PED_SHIFT (28U) -#define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK) -#define CAN_IR_ARA_MASK (0x20000000U) -#define CAN_IR_ARA_SHIFT (29U) -#define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK) - -/*! @name IE - Interrupt Enable */ -#define CAN_IE_RF0NE_MASK (0x1U) -#define CAN_IE_RF0NE_SHIFT (0U) -#define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK) -#define CAN_IE_RF0WE_MASK (0x2U) -#define CAN_IE_RF0WE_SHIFT (1U) -#define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK) -#define CAN_IE_RF0FE_MASK (0x4U) -#define CAN_IE_RF0FE_SHIFT (2U) -#define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK) -#define CAN_IE_RF0LE_MASK (0x8U) -#define CAN_IE_RF0LE_SHIFT (3U) -#define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK) -#define CAN_IE_RF1NE_MASK (0x10U) -#define CAN_IE_RF1NE_SHIFT (4U) -#define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK) -#define CAN_IE_RF1WE_MASK (0x20U) -#define CAN_IE_RF1WE_SHIFT (5U) -#define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK) -#define CAN_IE_RF1FE_MASK (0x40U) -#define CAN_IE_RF1FE_SHIFT (6U) -#define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK) -#define CAN_IE_RF1LE_MASK (0x80U) -#define CAN_IE_RF1LE_SHIFT (7U) -#define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK) -#define CAN_IE_HPME_MASK (0x100U) -#define CAN_IE_HPME_SHIFT (8U) -#define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK) -#define CAN_IE_TCE_MASK (0x200U) -#define CAN_IE_TCE_SHIFT (9U) -#define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK) -#define CAN_IE_TCFE_MASK (0x400U) -#define CAN_IE_TCFE_SHIFT (10U) -#define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK) -#define CAN_IE_TFEE_MASK (0x800U) -#define CAN_IE_TFEE_SHIFT (11U) -#define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK) -#define CAN_IE_TEFNE_MASK (0x1000U) -#define CAN_IE_TEFNE_SHIFT (12U) -#define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK) -#define CAN_IE_TEFWE_MASK (0x2000U) -#define CAN_IE_TEFWE_SHIFT (13U) -#define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK) -#define CAN_IE_TEFFE_MASK (0x4000U) -#define CAN_IE_TEFFE_SHIFT (14U) -#define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK) -#define CAN_IE_TEFLE_MASK (0x8000U) -#define CAN_IE_TEFLE_SHIFT (15U) -#define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK) -#define CAN_IE_TSWE_MASK (0x10000U) -#define CAN_IE_TSWE_SHIFT (16U) -#define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK) -#define CAN_IE_MRAFE_MASK (0x20000U) -#define CAN_IE_MRAFE_SHIFT (17U) -#define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK) -#define CAN_IE_TOOE_MASK (0x40000U) -#define CAN_IE_TOOE_SHIFT (18U) -#define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK) -#define CAN_IE_DRXE_MASK (0x80000U) -#define CAN_IE_DRXE_SHIFT (19U) -#define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK) -#define CAN_IE_BECE_MASK (0x100000U) -#define CAN_IE_BECE_SHIFT (20U) -#define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK) -#define CAN_IE_BEUE_MASK (0x200000U) -#define CAN_IE_BEUE_SHIFT (21U) -#define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK) -#define CAN_IE_ELOE_MASK (0x400000U) -#define CAN_IE_ELOE_SHIFT (22U) -#define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK) -#define CAN_IE_EPE_MASK (0x800000U) -#define CAN_IE_EPE_SHIFT (23U) -#define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK) -#define CAN_IE_EWE_MASK (0x1000000U) -#define CAN_IE_EWE_SHIFT (24U) -#define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK) -#define CAN_IE_BOE_MASK (0x2000000U) -#define CAN_IE_BOE_SHIFT (25U) -#define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK) -#define CAN_IE_WDIE_MASK (0x4000000U) -#define CAN_IE_WDIE_SHIFT (26U) -#define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK) -#define CAN_IE_PEAE_MASK (0x8000000U) -#define CAN_IE_PEAE_SHIFT (27U) -#define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK) -#define CAN_IE_PEDE_MASK (0x10000000U) -#define CAN_IE_PEDE_SHIFT (28U) -#define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK) -#define CAN_IE_ARAE_MASK (0x20000000U) -#define CAN_IE_ARAE_SHIFT (29U) -#define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK) - -/*! @name ILS - Interrupt Line Select */ -#define CAN_ILS_RF0NL_MASK (0x1U) -#define CAN_ILS_RF0NL_SHIFT (0U) -#define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK) -#define CAN_ILS_RF0WL_MASK (0x2U) -#define CAN_ILS_RF0WL_SHIFT (1U) -#define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK) -#define CAN_ILS_RF0FL_MASK (0x4U) -#define CAN_ILS_RF0FL_SHIFT (2U) -#define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK) -#define CAN_ILS_RF0LL_MASK (0x8U) -#define CAN_ILS_RF0LL_SHIFT (3U) -#define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK) -#define CAN_ILS_RF1NL_MASK (0x10U) -#define CAN_ILS_RF1NL_SHIFT (4U) -#define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK) -#define CAN_ILS_RF1WL_MASK (0x20U) -#define CAN_ILS_RF1WL_SHIFT (5U) -#define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK) -#define CAN_ILS_RF1FL_MASK (0x40U) -#define CAN_ILS_RF1FL_SHIFT (6U) -#define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK) -#define CAN_ILS_RF1LL_MASK (0x80U) -#define CAN_ILS_RF1LL_SHIFT (7U) -#define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK) -#define CAN_ILS_HPML_MASK (0x100U) -#define CAN_ILS_HPML_SHIFT (8U) -#define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK) -#define CAN_ILS_TCL_MASK (0x200U) -#define CAN_ILS_TCL_SHIFT (9U) -#define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK) -#define CAN_ILS_TCFL_MASK (0x400U) -#define CAN_ILS_TCFL_SHIFT (10U) -#define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK) -#define CAN_ILS_TFEL_MASK (0x800U) -#define CAN_ILS_TFEL_SHIFT (11U) -#define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK) -#define CAN_ILS_TEFNL_MASK (0x1000U) -#define CAN_ILS_TEFNL_SHIFT (12U) -#define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK) -#define CAN_ILS_TEFWL_MASK (0x2000U) -#define CAN_ILS_TEFWL_SHIFT (13U) -#define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK) -#define CAN_ILS_TEFFL_MASK (0x4000U) -#define CAN_ILS_TEFFL_SHIFT (14U) -#define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK) -#define CAN_ILS_TEFLL_MASK (0x8000U) -#define CAN_ILS_TEFLL_SHIFT (15U) -#define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK) -#define CAN_ILS_TSWL_MASK (0x10000U) -#define CAN_ILS_TSWL_SHIFT (16U) -#define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK) -#define CAN_ILS_MRAFL_MASK (0x20000U) -#define CAN_ILS_MRAFL_SHIFT (17U) -#define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK) -#define CAN_ILS_TOOL_MASK (0x40000U) -#define CAN_ILS_TOOL_SHIFT (18U) -#define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK) -#define CAN_ILS_DRXL_MASK (0x80000U) -#define CAN_ILS_DRXL_SHIFT (19U) -#define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK) -#define CAN_ILS_BECL_MASK (0x100000U) -#define CAN_ILS_BECL_SHIFT (20U) -#define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK) -#define CAN_ILS_BEUL_MASK (0x200000U) -#define CAN_ILS_BEUL_SHIFT (21U) -#define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK) -#define CAN_ILS_ELOL_MASK (0x400000U) -#define CAN_ILS_ELOL_SHIFT (22U) -#define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK) -#define CAN_ILS_EPL_MASK (0x800000U) -#define CAN_ILS_EPL_SHIFT (23U) -#define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK) -#define CAN_ILS_EWL_MASK (0x1000000U) -#define CAN_ILS_EWL_SHIFT (24U) -#define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK) -#define CAN_ILS_BOL_MASK (0x2000000U) -#define CAN_ILS_BOL_SHIFT (25U) -#define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK) -#define CAN_ILS_WDIL_MASK (0x4000000U) -#define CAN_ILS_WDIL_SHIFT (26U) -#define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK) -#define CAN_ILS_PEAL_MASK (0x8000000U) -#define CAN_ILS_PEAL_SHIFT (27U) -#define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK) -#define CAN_ILS_PEDL_MASK (0x10000000U) -#define CAN_ILS_PEDL_SHIFT (28U) -#define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK) -#define CAN_ILS_ARAL_MASK (0x20000000U) -#define CAN_ILS_ARAL_SHIFT (29U) -#define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK) - -/*! @name ILE - Interrupt Line Enable */ -#define CAN_ILE_EINT0_MASK (0x1U) -#define CAN_ILE_EINT0_SHIFT (0U) -#define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK) -#define CAN_ILE_EINT1_MASK (0x2U) -#define CAN_ILE_EINT1_SHIFT (1U) -#define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK) - -/*! @name GFC - Global Filter Configuration */ -#define CAN_GFC_RRFE_MASK (0x1U) -#define CAN_GFC_RRFE_SHIFT (0U) -#define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK) -#define CAN_GFC_RRFS_MASK (0x2U) -#define CAN_GFC_RRFS_SHIFT (1U) -#define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK) -#define CAN_GFC_ANFE_MASK (0xCU) -#define CAN_GFC_ANFE_SHIFT (2U) -#define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK) -#define CAN_GFC_ANFS_MASK (0x30U) -#define CAN_GFC_ANFS_SHIFT (4U) -#define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK) - -/*! @name SIDFC - Standard ID Filter Configuration */ -#define CAN_SIDFC_FLSSA_MASK (0xFFFCU) -#define CAN_SIDFC_FLSSA_SHIFT (2U) -#define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK) -#define CAN_SIDFC_LSS_MASK (0xFF0000U) -#define CAN_SIDFC_LSS_SHIFT (16U) -#define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK) - -/*! @name XIDFC - Extended ID Filter Configuration */ -#define CAN_XIDFC_FLESA_MASK (0xFFFCU) -#define CAN_XIDFC_FLESA_SHIFT (2U) -#define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK) -#define CAN_XIDFC_LSE_MASK (0xFF0000U) -#define CAN_XIDFC_LSE_SHIFT (16U) -#define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK) - -/*! @name XIDAM - Extended ID AND Mask */ -#define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU) -#define CAN_XIDAM_EIDM_SHIFT (0U) -#define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK) - -/*! @name HPMS - High Priority Message Status */ -#define CAN_HPMS_BIDX_MASK (0x3FU) -#define CAN_HPMS_BIDX_SHIFT (0U) -#define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK) -#define CAN_HPMS_MSI_MASK (0xC0U) -#define CAN_HPMS_MSI_SHIFT (6U) -#define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK) -#define CAN_HPMS_FIDX_MASK (0x7F00U) -#define CAN_HPMS_FIDX_SHIFT (8U) -#define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK) -#define CAN_HPMS_FLST_MASK (0x8000U) -#define CAN_HPMS_FLST_SHIFT (15U) -#define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK) - -/*! @name NDAT1 - New Data 1 */ -#define CAN_NDAT1_ND_MASK (0xFFFFFFFFU) -#define CAN_NDAT1_ND_SHIFT (0U) -#define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK) - -/*! @name NDAT2 - New Data 2 */ -#define CAN_NDAT2_ND_MASK (0xFFFFFFFFU) -#define CAN_NDAT2_ND_SHIFT (0U) -#define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK) - -/*! @name RXF0C - Rx FIFO 0 Configuration */ -#define CAN_RXF0C_F0SA_MASK (0xFFFCU) -#define CAN_RXF0C_F0SA_SHIFT (2U) -#define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK) -#define CAN_RXF0C_F0S_MASK (0x7F0000U) -#define CAN_RXF0C_F0S_SHIFT (16U) -#define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK) -#define CAN_RXF0C_F0WM_MASK (0x7F000000U) -#define CAN_RXF0C_F0WM_SHIFT (24U) -#define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK) -#define CAN_RXF0C_F0OM_MASK (0x80000000U) -#define CAN_RXF0C_F0OM_SHIFT (31U) -#define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK) - -/*! @name RXF0S - Rx FIFO 0 Status */ -#define CAN_RXF0S_F0FL_MASK (0x7FU) -#define CAN_RXF0S_F0FL_SHIFT (0U) -#define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK) -#define CAN_RXF0S_F0GI_MASK (0x3F00U) -#define CAN_RXF0S_F0GI_SHIFT (8U) -#define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK) -#define CAN_RXF0S_F0PI_MASK (0x3F0000U) -#define CAN_RXF0S_F0PI_SHIFT (16U) -#define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK) -#define CAN_RXF0S_F0F_MASK (0x1000000U) -#define CAN_RXF0S_F0F_SHIFT (24U) -#define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK) -#define CAN_RXF0S_RF0L_MASK (0x2000000U) -#define CAN_RXF0S_RF0L_SHIFT (25U) -#define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK) - -/*! @name RXF0A - Rx FIFO 0 Acknowledge */ -#define CAN_RXF0A_F0AI_MASK (0x3FU) -#define CAN_RXF0A_F0AI_SHIFT (0U) -#define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK) - -/*! @name RXBC - Rx Buffer Configuration */ -#define CAN_RXBC_RBSA_MASK (0xFFFCU) -#define CAN_RXBC_RBSA_SHIFT (2U) -#define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK) - -/*! @name RXF1C - Rx FIFO 1 Configuration */ -#define CAN_RXF1C_F1SA_MASK (0xFFFCU) -#define CAN_RXF1C_F1SA_SHIFT (2U) -#define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK) -#define CAN_RXF1C_F1S_MASK (0x7F0000U) -#define CAN_RXF1C_F1S_SHIFT (16U) -#define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK) -#define CAN_RXF1C_F1WM_MASK (0x7F000000U) -#define CAN_RXF1C_F1WM_SHIFT (24U) -#define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK) -#define CAN_RXF1C_F1OM_MASK (0x80000000U) -#define CAN_RXF1C_F1OM_SHIFT (31U) -#define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK) - -/*! @name RXF1S - Rx FIFO 1 Status */ -#define CAN_RXF1S_F1FL_MASK (0x7FU) -#define CAN_RXF1S_F1FL_SHIFT (0U) -#define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK) -#define CAN_RXF1S_F1GI_MASK (0x3F00U) -#define CAN_RXF1S_F1GI_SHIFT (8U) -#define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK) -#define CAN_RXF1S_F1PI_MASK (0x3F0000U) -#define CAN_RXF1S_F1PI_SHIFT (16U) -#define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK) -#define CAN_RXF1S_F1F_MASK (0x1000000U) -#define CAN_RXF1S_F1F_SHIFT (24U) -#define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK) -#define CAN_RXF1S_RF1L_MASK (0x2000000U) -#define CAN_RXF1S_RF1L_SHIFT (25U) -#define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK) - -/*! @name RXF1A - Rx FIFO 1 Acknowledge */ -#define CAN_RXF1A_F1AI_MASK (0x3FU) -#define CAN_RXF1A_F1AI_SHIFT (0U) -#define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK) - -/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */ -#define CAN_RXESC_F0DS_MASK (0x7U) -#define CAN_RXESC_F0DS_SHIFT (0U) -#define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK) -#define CAN_RXESC_F1DS_MASK (0x70U) -#define CAN_RXESC_F1DS_SHIFT (4U) -#define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK) -#define CAN_RXESC_RBDS_MASK (0x700U) -#define CAN_RXESC_RBDS_SHIFT (8U) -#define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK) - -/*! @name TXBC - Tx Buffer Configuration */ -#define CAN_TXBC_TBSA_MASK (0xFFFCU) -#define CAN_TXBC_TBSA_SHIFT (2U) -#define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK) -#define CAN_TXBC_NDTB_MASK (0x3F0000U) -#define CAN_TXBC_NDTB_SHIFT (16U) -#define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK) -#define CAN_TXBC_TFQS_MASK (0x3F000000U) -#define CAN_TXBC_TFQS_SHIFT (24U) -#define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK) -#define CAN_TXBC_TFQM_MASK (0x40000000U) -#define CAN_TXBC_TFQM_SHIFT (30U) -#define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK) - -/*! @name TXFQS - Tx FIFO/Queue Status */ -#define CAN_TXFQS_TFGI_MASK (0x1F00U) -#define CAN_TXFQS_TFGI_SHIFT (8U) -#define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK) -#define CAN_TXFQS_TFQPI_MASK (0x1F0000U) -#define CAN_TXFQS_TFQPI_SHIFT (16U) -#define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK) -#define CAN_TXFQS_TFQF_MASK (0x200000U) -#define CAN_TXFQS_TFQF_SHIFT (21U) -#define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK) - -/*! @name TXESC - Tx Buffer Element Size Configuration */ -#define CAN_TXESC_TBDS_MASK (0x7U) -#define CAN_TXESC_TBDS_SHIFT (0U) -#define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK) - -/*! @name TXBRP - Tx Buffer Request Pending */ -#define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU) -#define CAN_TXBRP_TRP_SHIFT (0U) -#define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK) - -/*! @name TXBAR - Tx Buffer Add Request */ -#define CAN_TXBAR_AR_MASK (0xFFFFFFFFU) -#define CAN_TXBAR_AR_SHIFT (0U) -#define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK) - -/*! @name TXBCR - Tx Buffer Cancellation Request */ -#define CAN_TXBCR_CR_MASK (0xFFFFFFFFU) -#define CAN_TXBCR_CR_SHIFT (0U) -#define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK) - -/*! @name TXBTO - Tx Buffer Transmission Occurred */ -#define CAN_TXBTO_TO_MASK (0xFFFFFFFFU) -#define CAN_TXBTO_TO_SHIFT (0U) -#define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK) - -/*! @name TXBCF - Tx Buffer Cancellation Finished */ -#define CAN_TXBCF_TO_MASK (0xFFFFFFFFU) -#define CAN_TXBCF_TO_SHIFT (0U) -#define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK) - -/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */ -#define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU) -#define CAN_TXBTIE_TIE_SHIFT (0U) -#define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK) - -/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */ -#define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU) -#define CAN_TXBCIE_CFIE_SHIFT (0U) -#define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK) - -/*! @name TXEFC - Tx Event FIFO Configuration */ -#define CAN_TXEFC_EFSA_MASK (0xFFFCU) -#define CAN_TXEFC_EFSA_SHIFT (2U) -#define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK) -#define CAN_TXEFC_EFS_MASK (0x3F0000U) -#define CAN_TXEFC_EFS_SHIFT (16U) -#define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK) -#define CAN_TXEFC_EFWM_MASK (0x3F000000U) -#define CAN_TXEFC_EFWM_SHIFT (24U) -#define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK) - -/*! @name TXEFS - Tx Event FIFO Status */ -#define CAN_TXEFS_EFFL_MASK (0x3FU) -#define CAN_TXEFS_EFFL_SHIFT (0U) -#define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK) -#define CAN_TXEFS_EFGI_MASK (0x1F00U) -#define CAN_TXEFS_EFGI_SHIFT (8U) -#define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK) -#define CAN_TXEFS_EFPI_MASK (0x3F0000U) -#define CAN_TXEFS_EFPI_SHIFT (16U) -#define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK) -#define CAN_TXEFS_EFF_MASK (0x1000000U) -#define CAN_TXEFS_EFF_SHIFT (24U) -#define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK) -#define CAN_TXEFS_TEFL_MASK (0x2000000U) -#define CAN_TXEFS_TEFL_SHIFT (25U) -#define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK) - -/*! @name TXEFA - Tx Event FIFO Acknowledge */ -#define CAN_TXEFA_EFAI_MASK (0x1FU) -#define CAN_TXEFA_EFAI_SHIFT (0U) -#define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK) - -/*! @name MRBA - CAN Message RAM Base Address */ -#define CAN_MRBA_BA_MASK (0xFFFFFFFFU) -#define CAN_MRBA_BA_SHIFT (0U) -#define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK) - -/*! @name ETSCC - External Timestamp Counter Configuration */ -#define CAN_ETSCC_ETCP_MASK (0x7FFU) -#define CAN_ETSCC_ETCP_SHIFT (0U) -#define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK) -#define CAN_ETSCC_ETCE_MASK (0x80000000U) -#define CAN_ETSCC_ETCE_SHIFT (31U) -#define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK) - -/*! @name ETSCV - External Timestamp Counter Value */ -#define CAN_ETSCV_ETSC_MASK (0xFFFFU) -#define CAN_ETSCV_ETSC_SHIFT (0U) -#define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK) - - -/*! - * @} - */ /* end of group CAN_Register_Masks */ - - -/* CAN - Peripheral instance base addresses */ -/** Peripheral CAN0 base address */ -#define CAN0_BASE (0x4009D000u) -/** Peripheral CAN0 base pointer */ -#define CAN0 ((CAN_Type *)CAN0_BASE) -/** Peripheral CAN1 base address */ -#define CAN1_BASE (0x4009E000u) -/** Peripheral CAN1 base pointer */ -#define CAN1 ((CAN_Type *)CAN1_BASE) -/** Array initializer of CAN peripheral base addresses */ -#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE } -/** Array initializer of CAN peripheral base pointers */ -#define CAN_BASE_PTRS { CAN0, CAN1 } -/** Interrupt vectors for the CAN peripheral type */ -#define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn }, { CAN1_IRQ0_IRQn, CAN1_IRQ1_IRQn } } - -/*! - * @} - */ /* end of group CAN_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CRC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer - * @{ - */ - -/** CRC - Register Layout Typedef */ -typedef struct { - __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ - __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ - union { /* offset: 0x8 */ - __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ - __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ - }; -} CRC_Type; - -/* ---------------------------------------------------------------------------- - -- CRC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Register_Masks CRC Register Masks - * @{ - */ - -/*! @name MODE - CRC mode register */ -#define CRC_MODE_CRC_POLY_MASK (0x3U) -#define CRC_MODE_CRC_POLY_SHIFT (0U) -#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) -#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) -#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) -#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) -#define CRC_MODE_CMPL_WR_MASK (0x8U) -#define CRC_MODE_CMPL_WR_SHIFT (3U) -#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) -#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) -#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) -#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) -#define CRC_MODE_CMPL_SUM_MASK (0x20U) -#define CRC_MODE_CMPL_SUM_SHIFT (5U) -#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) - -/*! @name SEED - CRC seed register */ -#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) -#define CRC_SEED_CRC_SEED_SHIFT (0U) -#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) - -/*! @name SUM - CRC checksum register */ -#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) -#define CRC_SUM_CRC_SUM_SHIFT (0U) -#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) - -/*! @name WR_DATA - CRC data register */ -#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) -#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) -#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) - - -/*! - * @} - */ /* end of group CRC_Register_Masks */ - - -/* CRC - Peripheral instance base addresses */ -/** Peripheral CRC_ENGINE base address */ -#define CRC_ENGINE_BASE (0x40095000u) -/** Peripheral CRC_ENGINE base pointer */ -#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) -/** Array initializer of CRC peripheral base addresses */ -#define CRC_BASE_ADDRS { CRC_ENGINE_BASE } -/** Array initializer of CRC peripheral base pointers */ -#define CRC_BASE_PTRS { CRC_ENGINE } - -/*! - * @} - */ /* end of group CRC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CTIMER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer - * @{ - */ - -/** CTIMER - Register Layout Typedef */ -typedef struct { - __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ - __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ - __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ - __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ - __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ - __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ - __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ - __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ - __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ - __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ - uint8_t RESERVED_0[48]; - __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ - __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */ - __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ -} CTIMER_Type; - -/* ---------------------------------------------------------------------------- - -- CTIMER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Register_Masks CTIMER Register Masks - * @{ - */ - -/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ -#define CTIMER_IR_MR0INT_MASK (0x1U) -#define CTIMER_IR_MR0INT_SHIFT (0U) -#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) -#define CTIMER_IR_MR1INT_MASK (0x2U) -#define CTIMER_IR_MR1INT_SHIFT (1U) -#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) -#define CTIMER_IR_MR2INT_MASK (0x4U) -#define CTIMER_IR_MR2INT_SHIFT (2U) -#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) -#define CTIMER_IR_MR3INT_MASK (0x8U) -#define CTIMER_IR_MR3INT_SHIFT (3U) -#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) -#define CTIMER_IR_CR0INT_MASK (0x10U) -#define CTIMER_IR_CR0INT_SHIFT (4U) -#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) -#define CTIMER_IR_CR1INT_MASK (0x20U) -#define CTIMER_IR_CR1INT_SHIFT (5U) -#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) -#define CTIMER_IR_CR2INT_MASK (0x40U) -#define CTIMER_IR_CR2INT_SHIFT (6U) -#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) -#define CTIMER_IR_CR3INT_MASK (0x80U) -#define CTIMER_IR_CR3INT_SHIFT (7U) -#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) - -/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ -#define CTIMER_TCR_CEN_MASK (0x1U) -#define CTIMER_TCR_CEN_SHIFT (0U) -#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) -#define CTIMER_TCR_CRST_MASK (0x2U) -#define CTIMER_TCR_CRST_SHIFT (1U) -#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) - -/*! @name TC - Timer Counter */ -#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_TC_TCVAL_SHIFT (0U) -#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) - -/*! @name PR - Prescale Register */ -#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PR_PRVAL_SHIFT (0U) -#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) - -/*! @name PC - Prescale Counter */ -#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PC_PCVAL_SHIFT (0U) -#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) - -/*! @name MCR - Match Control Register */ -#define CTIMER_MCR_MR0I_MASK (0x1U) -#define CTIMER_MCR_MR0I_SHIFT (0U) -#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) -#define CTIMER_MCR_MR0R_MASK (0x2U) -#define CTIMER_MCR_MR0R_SHIFT (1U) -#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) -#define CTIMER_MCR_MR0S_MASK (0x4U) -#define CTIMER_MCR_MR0S_SHIFT (2U) -#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) -#define CTIMER_MCR_MR1I_MASK (0x8U) -#define CTIMER_MCR_MR1I_SHIFT (3U) -#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) -#define CTIMER_MCR_MR1R_MASK (0x10U) -#define CTIMER_MCR_MR1R_SHIFT (4U) -#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) -#define CTIMER_MCR_MR1S_MASK (0x20U) -#define CTIMER_MCR_MR1S_SHIFT (5U) -#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) -#define CTIMER_MCR_MR2I_MASK (0x40U) -#define CTIMER_MCR_MR2I_SHIFT (6U) -#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) -#define CTIMER_MCR_MR2R_MASK (0x80U) -#define CTIMER_MCR_MR2R_SHIFT (7U) -#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) -#define CTIMER_MCR_MR2S_MASK (0x100U) -#define CTIMER_MCR_MR2S_SHIFT (8U) -#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) -#define CTIMER_MCR_MR3I_MASK (0x200U) -#define CTIMER_MCR_MR3I_SHIFT (9U) -#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) -#define CTIMER_MCR_MR3R_MASK (0x400U) -#define CTIMER_MCR_MR3R_SHIFT (10U) -#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) -#define CTIMER_MCR_MR3S_MASK (0x800U) -#define CTIMER_MCR_MR3S_SHIFT (11U) -#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) -#define CTIMER_MCR_MR0RL_MASK (0x1000000U) -#define CTIMER_MCR_MR0RL_SHIFT (24U) -#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) -#define CTIMER_MCR_MR1RL_MASK (0x2000000U) -#define CTIMER_MCR_MR1RL_SHIFT (25U) -#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) -#define CTIMER_MCR_MR2RL_MASK (0x4000000U) -#define CTIMER_MCR_MR2RL_SHIFT (26U) -#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) -#define CTIMER_MCR_MR3RL_MASK (0x8000000U) -#define CTIMER_MCR_MR3RL_SHIFT (27U) -#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) - -/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ -#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) -#define CTIMER_MR_MATCH_SHIFT (0U) -#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) - -/* The count of CTIMER_MR */ -#define CTIMER_MR_COUNT (4U) - -/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ -#define CTIMER_CCR_CAP0RE_MASK (0x1U) -#define CTIMER_CCR_CAP0RE_SHIFT (0U) -#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) -#define CTIMER_CCR_CAP0FE_MASK (0x2U) -#define CTIMER_CCR_CAP0FE_SHIFT (1U) -#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) -#define CTIMER_CCR_CAP0I_MASK (0x4U) -#define CTIMER_CCR_CAP0I_SHIFT (2U) -#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) -#define CTIMER_CCR_CAP1RE_MASK (0x8U) -#define CTIMER_CCR_CAP1RE_SHIFT (3U) -#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) -#define CTIMER_CCR_CAP1FE_MASK (0x10U) -#define CTIMER_CCR_CAP1FE_SHIFT (4U) -#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) -#define CTIMER_CCR_CAP1I_MASK (0x20U) -#define CTIMER_CCR_CAP1I_SHIFT (5U) -#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) -#define CTIMER_CCR_CAP2RE_MASK (0x40U) -#define CTIMER_CCR_CAP2RE_SHIFT (6U) -#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) -#define CTIMER_CCR_CAP2FE_MASK (0x80U) -#define CTIMER_CCR_CAP2FE_SHIFT (7U) -#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) -#define CTIMER_CCR_CAP2I_MASK (0x100U) -#define CTIMER_CCR_CAP2I_SHIFT (8U) -#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) -#define CTIMER_CCR_CAP3RE_MASK (0x200U) -#define CTIMER_CCR_CAP3RE_SHIFT (9U) -#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) -#define CTIMER_CCR_CAP3FE_MASK (0x400U) -#define CTIMER_CCR_CAP3FE_SHIFT (10U) -#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) -#define CTIMER_CCR_CAP3I_MASK (0x800U) -#define CTIMER_CCR_CAP3I_SHIFT (11U) -#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) - -/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ -#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) -#define CTIMER_CR_CAP_SHIFT (0U) -#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) - -/* The count of CTIMER_CR */ -#define CTIMER_CR_COUNT (4U) - -/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ -#define CTIMER_EMR_EM0_MASK (0x1U) -#define CTIMER_EMR_EM0_SHIFT (0U) -#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) -#define CTIMER_EMR_EM1_MASK (0x2U) -#define CTIMER_EMR_EM1_SHIFT (1U) -#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) -#define CTIMER_EMR_EM2_MASK (0x4U) -#define CTIMER_EMR_EM2_SHIFT (2U) -#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) -#define CTIMER_EMR_EM3_MASK (0x8U) -#define CTIMER_EMR_EM3_SHIFT (3U) -#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) -#define CTIMER_EMR_EMC0_MASK (0x30U) -#define CTIMER_EMR_EMC0_SHIFT (4U) -#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) -#define CTIMER_EMR_EMC1_MASK (0xC0U) -#define CTIMER_EMR_EMC1_SHIFT (6U) -#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) -#define CTIMER_EMR_EMC2_MASK (0x300U) -#define CTIMER_EMR_EMC2_SHIFT (8U) -#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) -#define CTIMER_EMR_EMC3_MASK (0xC00U) -#define CTIMER_EMR_EMC3_SHIFT (10U) -#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) - -/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ -#define CTIMER_CTCR_CTMODE_MASK (0x3U) -#define CTIMER_CTCR_CTMODE_SHIFT (0U) -#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) -#define CTIMER_CTCR_CINSEL_MASK (0xCU) -#define CTIMER_CTCR_CINSEL_SHIFT (2U) -#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) -#define CTIMER_CTCR_ENCC_MASK (0x10U) -#define CTIMER_CTCR_ENCC_SHIFT (4U) -#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) -#define CTIMER_CTCR_SELCC_MASK (0xE0U) -#define CTIMER_CTCR_SELCC_SHIFT (5U) -#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) - -/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */ -#define CTIMER_PWMC_PWMEN0_MASK (0x1U) -#define CTIMER_PWMC_PWMEN0_SHIFT (0U) -#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) -#define CTIMER_PWMC_PWMEN1_MASK (0x2U) -#define CTIMER_PWMC_PWMEN1_SHIFT (1U) -#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) -#define CTIMER_PWMC_PWMEN2_MASK (0x4U) -#define CTIMER_PWMC_PWMEN2_SHIFT (2U) -#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) -#define CTIMER_PWMC_PWMEN3_MASK (0x8U) -#define CTIMER_PWMC_PWMEN3_SHIFT (3U) -#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) - -/*! @name MSR - Match Shadow Register */ -#define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU) -#define CTIMER_MSR_SHADOWW_SHIFT (0U) -#define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK) - -/* The count of CTIMER_MSR */ -#define CTIMER_MSR_COUNT (4U) - - -/*! - * @} - */ /* end of group CTIMER_Register_Masks */ - - -/* CTIMER - Peripheral instance base addresses */ -/** Peripheral CTIMER0 base address */ -#define CTIMER0_BASE (0x40008000u) -/** Peripheral CTIMER0 base pointer */ -#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) -/** Peripheral CTIMER1 base address */ -#define CTIMER1_BASE (0x40009000u) -/** Peripheral CTIMER1 base pointer */ -#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) -/** Peripheral CTIMER2 base address */ -#define CTIMER2_BASE (0x40028000u) -/** Peripheral CTIMER2 base pointer */ -#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) -/** Peripheral CTIMER3 base address */ -#define CTIMER3_BASE (0x40048000u) -/** Peripheral CTIMER3 base pointer */ -#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) -/** Peripheral CTIMER4 base address */ -#define CTIMER4_BASE (0x40049000u) -/** Peripheral CTIMER4 base pointer */ -#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) -/** Array initializer of CTIMER peripheral base addresses */ -#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } -/** Array initializer of CTIMER peripheral base pointers */ -#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } -/** Interrupt vectors for the CTIMER peripheral type */ -#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } - -/*! - * @} - */ /* end of group CTIMER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer - * @{ - */ - -/** DMA - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ - __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ - __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ - uint8_t RESERVED_0[20]; - struct { /* offset: 0x20, array step: 0x5C */ - __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ - uint8_t RESERVED_0[4]; - __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ - uint8_t RESERVED_1[4]; - __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ - uint8_t RESERVED_2[4]; - __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ - uint8_t RESERVED_3[4]; - __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ - uint8_t RESERVED_4[4]; - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ - uint8_t RESERVED_5[4]; - __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ - uint8_t RESERVED_6[4]; - __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ - uint8_t RESERVED_7[4]; - __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ - uint8_t RESERVED_8[4]; - __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ - uint8_t RESERVED_9[4]; - __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ - uint8_t RESERVED_10[4]; - __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ - } COMMON[1]; - uint8_t RESERVED_1[900]; - struct { /* offset: 0x400, array step: 0x10 */ - __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ - __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ - __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } CHANNEL[30]; -} DMA_Type; - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/*! @name CTRL - DMA control. */ -#define DMA_CTRL_ENABLE_MASK (0x1U) -#define DMA_CTRL_ENABLE_SHIFT (0U) -#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) - -/*! @name INTSTAT - Interrupt status. */ -#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) -#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) -#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) -#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) -#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) -#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) - -/*! @name SRAMBASE - SRAM address of the channel configuration table. */ -#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) -#define DMA_SRAMBASE_OFFSET_SHIFT (9U) -#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) - -/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ -#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) -#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) - -/* The count of DMA_COMMON_ENABLESET */ -#define DMA_COMMON_ENABLESET_COUNT (1U) - -/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ -#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) -#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) - -/* The count of DMA_COMMON_ENABLECLR */ -#define DMA_COMMON_ENABLECLR_COUNT (1U) - -/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ -#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) -#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) - -/* The count of DMA_COMMON_ACTIVE */ -#define DMA_COMMON_ACTIVE_COUNT (1U) - -/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ -#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) -#define DMA_COMMON_BUSY_BSY_SHIFT (0U) -#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) - -/* The count of DMA_COMMON_BUSY */ -#define DMA_COMMON_BUSY_COUNT (1U) - -/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ -#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) -#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) - -/* The count of DMA_COMMON_ERRINT */ -#define DMA_COMMON_ERRINT_COUNT (1U) - -/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ -#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) -#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) - -/* The count of DMA_COMMON_INTENSET */ -#define DMA_COMMON_INTENSET_COUNT (1U) - -/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ -#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) -#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) - -/* The count of DMA_COMMON_INTENCLR */ -#define DMA_COMMON_INTENCLR_COUNT (1U) - -/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ -#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTA_IA_SHIFT (0U) -#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) - -/* The count of DMA_COMMON_INTA */ -#define DMA_COMMON_INTA_COUNT (1U) - -/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ -#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTB_IB_SHIFT (0U) -#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) - -/* The count of DMA_COMMON_INTB */ -#define DMA_COMMON_INTB_COUNT (1U) - -/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ -#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETVALID_SV_SHIFT (0U) -#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) - -/* The count of DMA_COMMON_SETVALID */ -#define DMA_COMMON_SETVALID_COUNT (1U) - -/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ -#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) -#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) - -/* The count of DMA_COMMON_SETTRIG */ -#define DMA_COMMON_SETTRIG_COUNT (1U) - -/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ -#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) -#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) - -/* The count of DMA_COMMON_ABORT */ -#define DMA_COMMON_ABORT_COUNT (1U) - -/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ -#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) -#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) -#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) -#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) -#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) -#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) -#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) -#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) -#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) -#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) -#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) -#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) -#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) -#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) -#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) -#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) -#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) -#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) -#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) -#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) -#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) -#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) -#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) - -/* The count of DMA_CHANNEL_CFG */ -#define DMA_CHANNEL_CFG_COUNT (30U) - -/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) -#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) -#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) -#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) - -/* The count of DMA_CHANNEL_CTLSTAT */ -#define DMA_CHANNEL_CTLSTAT_COUNT (30U) - -/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ -#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) -#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) -#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) -#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) -#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) -#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) -#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) -#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) -#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) -#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) -#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) -#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) -#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) -#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) -#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) -#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) -#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) -#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) -#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) -#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) -#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) -#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) -#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) -#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) -#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) -#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) -#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) - -/* The count of DMA_CHANNEL_XFERCFG */ -#define DMA_CHANNEL_XFERCFG_COUNT (30U) - - -/*! - * @} - */ /* end of group DMA_Register_Masks */ - - -/* DMA - Peripheral instance base addresses */ -/** Peripheral DMA0 base address */ -#define DMA0_BASE (0x40082000u) -/** Peripheral DMA0 base pointer */ -#define DMA0 ((DMA_Type *)DMA0_BASE) -/** Array initializer of DMA peripheral base addresses */ -#define DMA_BASE_ADDRS { DMA0_BASE } -/** Array initializer of DMA peripheral base pointers */ -#define DMA_BASE_PTRS { DMA0 } -/** Interrupt vectors for the DMA peripheral type */ -#define DMA_IRQS { DMA0_IRQn } - -/*! - * @} - */ /* end of group DMA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMIC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer - * @{ - */ - -/** DMIC - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x100 */ - __IO uint32_t OSR; /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */ - __IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */ - __IO uint32_t PREAC2FSCOEF; /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */ - __IO uint32_t PREAC4FSCOEF; /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */ - __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */ - uint8_t RESERVED_0[108]; - __IO uint32_t FIFO_CTRL; /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */ - __IO uint32_t FIFO_STATUS; /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */ - __IO uint32_t FIFO_DATA; /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */ - __IO uint32_t PHY_CTRL; /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */ - __IO uint32_t DC_CTRL; /**< DC Control register 0, array offset: 0x90, array step: 0x100 */ - uint8_t RESERVED_1[108]; - } CHANNEL[2]; - uint8_t RESERVED_0[3328]; - __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ - uint8_t RESERVED_1[8]; - __IO uint32_t IOCFG; /**< I/O Configuration register, offset: 0xF0C */ - __IO uint32_t USE2FS; /**< Use 2FS register, offset: 0xF10 */ - uint8_t RESERVED_2[108]; - __IO uint32_t HWVADGAIN; /**< HWVAD input gain register, offset: 0xF80 */ - __IO uint32_t HWVADHPFS; /**< HWVAD filter control register, offset: 0xF84 */ - __IO uint32_t HWVADST10; /**< HWVAD control register, offset: 0xF88 */ - __IO uint32_t HWVADRSTT; /**< HWVAD filter reset register, offset: 0xF8C */ - __IO uint32_t HWVADTHGN; /**< HWVAD noise estimator gain register, offset: 0xF90 */ - __IO uint32_t HWVADTHGS; /**< HWVAD signal estimator gain register, offset: 0xF94 */ - __I uint32_t HWVADLOWZ; /**< HWVAD noise envelope estimator register, offset: 0xF98 */ - uint8_t RESERVED_3[96]; - __I uint32_t ID; /**< Module Identification register, offset: 0xFFC */ -} DMIC_Type; - -/* ---------------------------------------------------------------------------- - -- DMIC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMIC_Register_Masks DMIC Register Masks - * @{ - */ - -/*! @name CHANNEL_OSR - Oversample Rate register 0 */ -#define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU) -#define DMIC_CHANNEL_OSR_OSR_SHIFT (0U) -#define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK) - -/* The count of DMIC_CHANNEL_OSR */ -#define DMIC_CHANNEL_OSR_COUNT (2U) - -/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */ -#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU) -#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U) -#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK) - -/* The count of DMIC_CHANNEL_DIVHFCLK */ -#define DMIC_CHANNEL_DIVHFCLK_COUNT (2U) - -/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */ -#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U) -#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U) -#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK) - -/* The count of DMIC_CHANNEL_PREAC2FSCOEF */ -#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U) - -/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */ -#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U) -#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U) -#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK) - -/* The count of DMIC_CHANNEL_PREAC4FSCOEF */ -#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U) - -/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */ -#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU) -#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U) -#define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK) - -/* The count of DMIC_CHANNEL_GAINSHIFT */ -#define DMIC_CHANNEL_GAINSHIFT_COUNT (2U) - -/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */ -#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U) -#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U) -#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK) -#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U) -#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U) -#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK) -#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U) -#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U) -#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK) -#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U) -#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U) -#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK) -#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U) -#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U) -#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK) - -/* The count of DMIC_CHANNEL_FIFO_CTRL */ -#define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U) - -/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */ -#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U) -#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U) -#define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK) -#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U) -#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U) -#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK) -#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U) -#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U) -#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK) - -/* The count of DMIC_CHANNEL_FIFO_STATUS */ -#define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U) - -/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */ -#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU) -#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U) -#define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK) - -/* The count of DMIC_CHANNEL_FIFO_DATA */ -#define DMIC_CHANNEL_FIFO_DATA_COUNT (2U) - -/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */ -#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U) -#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U) -#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK) -#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U) -#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U) -#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK) - -/* The count of DMIC_CHANNEL_PHY_CTRL */ -#define DMIC_CHANNEL_PHY_CTRL_COUNT (2U) - -/*! @name CHANNEL_DC_CTRL - DC Control register 0 */ -#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U) -#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U) -#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK) -#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U) -#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U) -#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK) -#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U) -#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U) -#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK) - -/* The count of DMIC_CHANNEL_DC_CTRL */ -#define DMIC_CHANNEL_DC_CTRL_COUNT (2U) - -/*! @name CHANEN - Channel Enable register */ -#define DMIC_CHANEN_EN_CH0_MASK (0x1U) -#define DMIC_CHANEN_EN_CH0_SHIFT (0U) -#define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK) -#define DMIC_CHANEN_EN_CH1_MASK (0x2U) -#define DMIC_CHANEN_EN_CH1_SHIFT (1U) -#define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK) - -/*! @name IOCFG - I/O Configuration register */ -#define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U) -#define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U) -#define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK) -#define DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U) -#define DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U) -#define DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK) -#define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U) -#define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U) -#define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK) - -/*! @name USE2FS - Use 2FS register */ -#define DMIC_USE2FS_USE2FS_MASK (0x1U) -#define DMIC_USE2FS_USE2FS_SHIFT (0U) -#define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK) - -/*! @name HWVADGAIN - HWVAD input gain register */ -#define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU) -#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U) -#define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK) - -/*! @name HWVADHPFS - HWVAD filter control register */ -#define DMIC_HWVADHPFS_HPFS_MASK (0x3U) -#define DMIC_HWVADHPFS_HPFS_SHIFT (0U) -#define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK) - -/*! @name HWVADST10 - HWVAD control register */ -#define DMIC_HWVADST10_ST10_MASK (0x1U) -#define DMIC_HWVADST10_ST10_SHIFT (0U) -#define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK) - -/*! @name HWVADRSTT - HWVAD filter reset register */ -#define DMIC_HWVADRSTT_RSTT_MASK (0x1U) -#define DMIC_HWVADRSTT_RSTT_SHIFT (0U) -#define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK) - -/*! @name HWVADTHGN - HWVAD noise estimator gain register */ -#define DMIC_HWVADTHGN_THGN_MASK (0xFU) -#define DMIC_HWVADTHGN_THGN_SHIFT (0U) -#define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK) - -/*! @name HWVADTHGS - HWVAD signal estimator gain register */ -#define DMIC_HWVADTHGS_THGS_MASK (0xFU) -#define DMIC_HWVADTHGS_THGS_SHIFT (0U) -#define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK) - -/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */ -#define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU) -#define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U) -#define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK) - -/*! @name ID - Module Identification register */ -#define DMIC_ID_ID_MASK (0xFFFFFFFFU) -#define DMIC_ID_ID_SHIFT (0U) -#define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK) - - -/*! - * @} - */ /* end of group DMIC_Register_Masks */ - - -/* DMIC - Peripheral instance base addresses */ -/** Peripheral DMIC0 base address */ -#define DMIC0_BASE (0x40090000u) -/** Peripheral DMIC0 base pointer */ -#define DMIC0 ((DMIC_Type *)DMIC0_BASE) -/** Array initializer of DMIC peripheral base addresses */ -#define DMIC_BASE_ADDRS { DMIC0_BASE } -/** Array initializer of DMIC peripheral base pointers */ -#define DMIC_BASE_PTRS { DMIC0 } -/** Interrupt vectors for the DMIC peripheral type */ -#define DMIC_IRQS { DMIC0_IRQn } -#define DMIC_HWVAD_IRQS { HWVAD0_IRQn } - -/*! - * @} - */ /* end of group DMIC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- EEPROM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EEPROM_Peripheral_Access_Layer EEPROM Peripheral Access Layer - * @{ - */ - -/** EEPROM - Register Layout Typedef */ -typedef struct { - __IO uint32_t CMD; /**< EEPROM command register, offset: 0x0 */ - uint8_t RESERVED_0[4]; - __IO uint32_t RWSTATE; /**< EEPROM read wait state register, offset: 0x8 */ - __IO uint32_t AUTOPROG; /**< EEPROM auto programming register, offset: 0xC */ - __IO uint32_t WSTATE; /**< EEPROM wait state register, offset: 0x10 */ - __IO uint32_t CLKDIV; /**< EEPROM clock divider register, offset: 0x14 */ - __IO uint32_t PWRDWN; /**< EEPROM power-down register, offset: 0x18 */ - uint8_t RESERVED_1[4028]; - __O uint32_t INTENCLR; /**< EEPROM interrupt enable clear, offset: 0xFD8 */ - __O uint32_t INTENSET; /**< EEPROM interrupt enable set, offset: 0xFDC */ - __I uint32_t INTSTAT; /**< EEPROM interrupt status, offset: 0xFE0 */ - __I uint32_t INTEN; /**< EEPROM interrupt enable, offset: 0xFE4 */ - __O uint32_t INTSTATCLR; /**< EEPROM interrupt status clear, offset: 0xFE8 */ - __O uint32_t INTSTATSET; /**< EEPROM interrupt status set, offset: 0xFEC */ -} EEPROM_Type; - -/* ---------------------------------------------------------------------------- - -- EEPROM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EEPROM_Register_Masks EEPROM Register Masks - * @{ - */ - -/*! @name CMD - EEPROM command register */ -#define EEPROM_CMD_CMD_MASK (0x7U) -#define EEPROM_CMD_CMD_SHIFT (0U) -#define EEPROM_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_CMD_CMD_SHIFT)) & EEPROM_CMD_CMD_MASK) - -/*! @name RWSTATE - EEPROM read wait state register */ -#define EEPROM_RWSTATE_RPHASE2_MASK (0xFFU) -#define EEPROM_RWSTATE_RPHASE2_SHIFT (0U) -#define EEPROM_RWSTATE_RPHASE2(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE2_SHIFT)) & EEPROM_RWSTATE_RPHASE2_MASK) -#define EEPROM_RWSTATE_RPHASE1_MASK (0xFF00U) -#define EEPROM_RWSTATE_RPHASE1_SHIFT (8U) -#define EEPROM_RWSTATE_RPHASE1(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE1_SHIFT)) & EEPROM_RWSTATE_RPHASE1_MASK) - -/*! @name AUTOPROG - EEPROM auto programming register */ -#define EEPROM_AUTOPROG_AUTOPROG_MASK (0x3U) -#define EEPROM_AUTOPROG_AUTOPROG_SHIFT (0U) -#define EEPROM_AUTOPROG_AUTOPROG(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_AUTOPROG_AUTOPROG_SHIFT)) & EEPROM_AUTOPROG_AUTOPROG_MASK) - -/*! @name WSTATE - EEPROM wait state register */ -#define EEPROM_WSTATE_PHASE3_MASK (0xFFU) -#define EEPROM_WSTATE_PHASE3_SHIFT (0U) -#define EEPROM_WSTATE_PHASE3(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE3_SHIFT)) & EEPROM_WSTATE_PHASE3_MASK) -#define EEPROM_WSTATE_PHASE2_MASK (0xFF00U) -#define EEPROM_WSTATE_PHASE2_SHIFT (8U) -#define EEPROM_WSTATE_PHASE2(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE2_SHIFT)) & EEPROM_WSTATE_PHASE2_MASK) -#define EEPROM_WSTATE_PHASE1_MASK (0xFF0000U) -#define EEPROM_WSTATE_PHASE1_SHIFT (16U) -#define EEPROM_WSTATE_PHASE1(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE1_SHIFT)) & EEPROM_WSTATE_PHASE1_MASK) -#define EEPROM_WSTATE_LCK_PARWEP_MASK (0x80000000U) -#define EEPROM_WSTATE_LCK_PARWEP_SHIFT (31U) -#define EEPROM_WSTATE_LCK_PARWEP(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_LCK_PARWEP_SHIFT)) & EEPROM_WSTATE_LCK_PARWEP_MASK) - -/*! @name CLKDIV - EEPROM clock divider register */ -#define EEPROM_CLKDIV_CLKDIV_MASK (0xFFFFU) -#define EEPROM_CLKDIV_CLKDIV_SHIFT (0U) -#define EEPROM_CLKDIV_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_CLKDIV_CLKDIV_SHIFT)) & EEPROM_CLKDIV_CLKDIV_MASK) - -/*! @name PWRDWN - EEPROM power-down register */ -#define EEPROM_PWRDWN_PWRDWN_MASK (0x1U) -#define EEPROM_PWRDWN_PWRDWN_SHIFT (0U) -#define EEPROM_PWRDWN_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_PWRDWN_PWRDWN_SHIFT)) & EEPROM_PWRDWN_PWRDWN_MASK) - -/*! @name INTENCLR - EEPROM interrupt enable clear */ -#define EEPROM_INTENCLR_PROG_CLR_EN_MASK (0x4U) -#define EEPROM_INTENCLR_PROG_CLR_EN_SHIFT (2U) -#define EEPROM_INTENCLR_PROG_CLR_EN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENCLR_PROG_CLR_EN_SHIFT)) & EEPROM_INTENCLR_PROG_CLR_EN_MASK) - -/*! @name INTENSET - EEPROM interrupt enable set */ -#define EEPROM_INTENSET_PROG_SET_EN_MASK (0x4U) -#define EEPROM_INTENSET_PROG_SET_EN_SHIFT (2U) -#define EEPROM_INTENSET_PROG_SET_EN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENSET_PROG_SET_EN_SHIFT)) & EEPROM_INTENSET_PROG_SET_EN_MASK) - -/*! @name INTSTAT - EEPROM interrupt status */ -#define EEPROM_INTSTAT_END_OF_PROG_MASK (0x4U) -#define EEPROM_INTSTAT_END_OF_PROG_SHIFT (2U) -#define EEPROM_INTSTAT_END_OF_PROG(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTAT_END_OF_PROG_SHIFT)) & EEPROM_INTSTAT_END_OF_PROG_MASK) - -/*! @name INTEN - EEPROM interrupt enable */ -#define EEPROM_INTEN_EE_PROG_DONE_MASK (0x4U) -#define EEPROM_INTEN_EE_PROG_DONE_SHIFT (2U) -#define EEPROM_INTEN_EE_PROG_DONE(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTEN_EE_PROG_DONE_SHIFT)) & EEPROM_INTEN_EE_PROG_DONE_MASK) - -/*! @name INTSTATCLR - EEPROM interrupt status clear */ -#define EEPROM_INTSTATCLR_PROG_CLR_ST_MASK (0x4U) -#define EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT (2U) -#define EEPROM_INTSTATCLR_PROG_CLR_ST(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT)) & EEPROM_INTSTATCLR_PROG_CLR_ST_MASK) - -/*! @name INTSTATSET - EEPROM interrupt status set */ -#define EEPROM_INTSTATSET_PROG_SET_ST_MASK (0x4U) -#define EEPROM_INTSTATSET_PROG_SET_ST_SHIFT (2U) -#define EEPROM_INTSTATSET_PROG_SET_ST(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATSET_PROG_SET_ST_SHIFT)) & EEPROM_INTSTATSET_PROG_SET_ST_MASK) - - -/*! - * @} - */ /* end of group EEPROM_Register_Masks */ - - -/* EEPROM - Peripheral instance base addresses */ -/** Peripheral EEPROM base address */ -#define EEPROM_BASE (0x40014000u) -/** Peripheral EEPROM base pointer */ -#define EEPROM ((EEPROM_Type *)EEPROM_BASE) -/** Array initializer of EEPROM peripheral base addresses */ -#define EEPROM_BASE_ADDRS { EEPROM_BASE } -/** Array initializer of EEPROM peripheral base pointers */ -#define EEPROM_BASE_PTRS { EEPROM } -/** Interrupt vectors for the EEPROM peripheral type */ -#define EEPROM_IRQS { EEPROM_IRQn } - -/*! - * @} - */ /* end of group EEPROM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- EMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EMC_Peripheral_Access_Layer EMC Peripheral Access Layer - * @{ - */ - -/** EMC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CONTROL; /**< Controls operation of the memory controller, offset: 0x0 */ - __I uint32_t STATUS; /**< Provides EMC status information, offset: 0x4 */ - __IO uint32_t CONFIG; /**< Configures operation of the memory controller, offset: 0x8 */ - uint8_t RESERVED_0[20]; - __IO uint32_t DYNAMICCONTROL; /**< Controls dynamic memory operation, offset: 0x20 */ - __IO uint32_t DYNAMICREFRESH; /**< Configures dynamic memory refresh, offset: 0x24 */ - __IO uint32_t DYNAMICREADCONFIG; /**< Configures dynamic memory read strategy, offset: 0x28 */ - uint8_t RESERVED_1[4]; - __IO uint32_t DYNAMICRP; /**< Precharge command period, offset: 0x30 */ - __IO uint32_t DYNAMICRAS; /**< Active to precharge command period, offset: 0x34 */ - __IO uint32_t DYNAMICSREX; /**< Self-refresh exit time, offset: 0x38 */ - __IO uint32_t DYNAMICAPR; /**< Last-data-out to active command time, offset: 0x3C */ - __IO uint32_t DYNAMICDAL; /**< Data-in to active command time, offset: 0x40 */ - __IO uint32_t DYNAMICWR; /**< Write recovery time, offset: 0x44 */ - __IO uint32_t DYNAMICRC; /**< Selects the active to active command period, offset: 0x48 */ - __IO uint32_t DYNAMICRFC; /**< Selects the auto-refresh period, offset: 0x4C */ - __IO uint32_t DYNAMICXSR; /**< Time for exit self-refresh to active command, offset: 0x50 */ - __IO uint32_t DYNAMICRRD; /**< Latency for active bank A to active bank B, offset: 0x54 */ - __IO uint32_t DYNAMICMRD; /**< Time for load mode register to active command, offset: 0x58 */ - uint8_t RESERVED_2[36]; - __IO uint32_t STATICEXTENDEDWAIT; /**< Time for long static memory read and write transfers, offset: 0x80 */ - uint8_t RESERVED_3[124]; - struct { /* offset: 0x100, array step: 0x20 */ - __IO uint32_t DYNAMICCONFIG; /**< Configuration information for EMC_DYCSx, array offset: 0x100, array step: 0x20 */ - __IO uint32_t DYNAMICRASCAS; /**< RAS and CAS latencies for EMC_DYCSx, array offset: 0x104, array step: 0x20 */ - uint8_t RESERVED_0[24]; - } DYNAMIC[4]; - uint8_t RESERVED_4[128]; - struct { /* offset: 0x200, array step: 0x20 */ - __IO uint32_t STATICCONFIG; /**< Configuration for EMC_CSx, array offset: 0x200, array step: 0x20 */ - __IO uint32_t STATICWAITWEN; /**< Delay from EMC_CSx to write enable, array offset: 0x204, array step: 0x20 */ - __IO uint32_t STATICWAITOEN; /**< Delay from EMC_CSx or address change, whichever is later, to output enable, array offset: 0x208, array step: 0x20 */ - __IO uint32_t STATICWAITRD; /**< Delay from EMC_CSx to a read access, array offset: 0x20C, array step: 0x20 */ - __IO uint32_t STATICWAITPAGE; /**< Delay for asynchronous page mode sequential accesses for EMC_CSx, array offset: 0x210, array step: 0x20 */ - __IO uint32_t STATICWAITWR; /**< Delay from EMC_CSx to a write access, array offset: 0x214, array step: 0x20 */ - __IO uint32_t STATICWAITTURN; /**< Number of bus turnaround cycles EMC_CSx, array offset: 0x218, array step: 0x20 */ - uint8_t RESERVED_0[4]; - } STATIC[4]; -} EMC_Type; - -/* ---------------------------------------------------------------------------- - -- EMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EMC_Register_Masks EMC Register Masks - * @{ - */ - -/*! @name CONTROL - Controls operation of the memory controller */ -#define EMC_CONTROL_E_MASK (0x1U) -#define EMC_CONTROL_E_SHIFT (0U) -#define EMC_CONTROL_E(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_E_SHIFT)) & EMC_CONTROL_E_MASK) -#define EMC_CONTROL_M_MASK (0x2U) -#define EMC_CONTROL_M_SHIFT (1U) -#define EMC_CONTROL_M(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_M_SHIFT)) & EMC_CONTROL_M_MASK) -#define EMC_CONTROL_L_MASK (0x4U) -#define EMC_CONTROL_L_SHIFT (2U) -#define EMC_CONTROL_L(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_L_SHIFT)) & EMC_CONTROL_L_MASK) - -/*! @name STATUS - Provides EMC status information */ -#define EMC_STATUS_B_MASK (0x1U) -#define EMC_STATUS_B_SHIFT (0U) -#define EMC_STATUS_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_B_SHIFT)) & EMC_STATUS_B_MASK) -#define EMC_STATUS_S_MASK (0x2U) -#define EMC_STATUS_S_SHIFT (1U) -#define EMC_STATUS_S(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_S_SHIFT)) & EMC_STATUS_S_MASK) -#define EMC_STATUS_SA_MASK (0x4U) -#define EMC_STATUS_SA_SHIFT (2U) -#define EMC_STATUS_SA(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_SA_SHIFT)) & EMC_STATUS_SA_MASK) - -/*! @name CONFIG - Configures operation of the memory controller */ -#define EMC_CONFIG_EM_MASK (0x1U) -#define EMC_CONFIG_EM_SHIFT (0U) -#define EMC_CONFIG_EM(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_EM_SHIFT)) & EMC_CONFIG_EM_MASK) -#define EMC_CONFIG_CLKR_MASK (0x100U) -#define EMC_CONFIG_CLKR_SHIFT (8U) -#define EMC_CONFIG_CLKR(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_CLKR_SHIFT)) & EMC_CONFIG_CLKR_MASK) - -/*! @name DYNAMICCONTROL - Controls dynamic memory operation */ -#define EMC_DYNAMICCONTROL_CE_MASK (0x1U) -#define EMC_DYNAMICCONTROL_CE_SHIFT (0U) -#define EMC_DYNAMICCONTROL_CE(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CE_SHIFT)) & EMC_DYNAMICCONTROL_CE_MASK) -#define EMC_DYNAMICCONTROL_CS_MASK (0x2U) -#define EMC_DYNAMICCONTROL_CS_SHIFT (1U) -#define EMC_DYNAMICCONTROL_CS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CS_SHIFT)) & EMC_DYNAMICCONTROL_CS_MASK) -#define EMC_DYNAMICCONTROL_SR_MASK (0x4U) -#define EMC_DYNAMICCONTROL_SR_SHIFT (2U) -#define EMC_DYNAMICCONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_SR_SHIFT)) & EMC_DYNAMICCONTROL_SR_MASK) -#define EMC_DYNAMICCONTROL_MMC_MASK (0x20U) -#define EMC_DYNAMICCONTROL_MMC_SHIFT (5U) -#define EMC_DYNAMICCONTROL_MMC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_MMC_SHIFT)) & EMC_DYNAMICCONTROL_MMC_MASK) -#define EMC_DYNAMICCONTROL_I_MASK (0x180U) -#define EMC_DYNAMICCONTROL_I_SHIFT (7U) -#define EMC_DYNAMICCONTROL_I(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_I_SHIFT)) & EMC_DYNAMICCONTROL_I_MASK) - -/*! @name DYNAMICREFRESH - Configures dynamic memory refresh */ -#define EMC_DYNAMICREFRESH_REFRESH_MASK (0x7FFU) -#define EMC_DYNAMICREFRESH_REFRESH_SHIFT (0U) -#define EMC_DYNAMICREFRESH_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREFRESH_REFRESH_SHIFT)) & EMC_DYNAMICREFRESH_REFRESH_MASK) - -/*! @name DYNAMICREADCONFIG - Configures dynamic memory read strategy */ -#define EMC_DYNAMICREADCONFIG_RD_MASK (0x3U) -#define EMC_DYNAMICREADCONFIG_RD_SHIFT (0U) -#define EMC_DYNAMICREADCONFIG_RD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREADCONFIG_RD_SHIFT)) & EMC_DYNAMICREADCONFIG_RD_MASK) - -/*! @name DYNAMICRP - Precharge command period */ -#define EMC_DYNAMICRP_TRP_MASK (0xFU) -#define EMC_DYNAMICRP_TRP_SHIFT (0U) -#define EMC_DYNAMICRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRP_TRP_SHIFT)) & EMC_DYNAMICRP_TRP_MASK) - -/*! @name DYNAMICRAS - Active to precharge command period */ -#define EMC_DYNAMICRAS_TRAS_MASK (0xFU) -#define EMC_DYNAMICRAS_TRAS_SHIFT (0U) -#define EMC_DYNAMICRAS_TRAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRAS_TRAS_SHIFT)) & EMC_DYNAMICRAS_TRAS_MASK) - -/*! @name DYNAMICSREX - Self-refresh exit time */ -#define EMC_DYNAMICSREX_TSREX_MASK (0xFU) -#define EMC_DYNAMICSREX_TSREX_SHIFT (0U) -#define EMC_DYNAMICSREX_TSREX(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICSREX_TSREX_SHIFT)) & EMC_DYNAMICSREX_TSREX_MASK) - -/*! @name DYNAMICAPR - Last-data-out to active command time */ -#define EMC_DYNAMICAPR_TAPR_MASK (0xFU) -#define EMC_DYNAMICAPR_TAPR_SHIFT (0U) -#define EMC_DYNAMICAPR_TAPR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICAPR_TAPR_SHIFT)) & EMC_DYNAMICAPR_TAPR_MASK) - -/*! @name DYNAMICDAL - Data-in to active command time */ -#define EMC_DYNAMICDAL_TDAL_MASK (0xFU) -#define EMC_DYNAMICDAL_TDAL_SHIFT (0U) -#define EMC_DYNAMICDAL_TDAL(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICDAL_TDAL_SHIFT)) & EMC_DYNAMICDAL_TDAL_MASK) - -/*! @name DYNAMICWR - Write recovery time */ -#define EMC_DYNAMICWR_TWR_MASK (0xFU) -#define EMC_DYNAMICWR_TWR_SHIFT (0U) -#define EMC_DYNAMICWR_TWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICWR_TWR_SHIFT)) & EMC_DYNAMICWR_TWR_MASK) - -/*! @name DYNAMICRC - Selects the active to active command period */ -#define EMC_DYNAMICRC_TRC_MASK (0x1FU) -#define EMC_DYNAMICRC_TRC_SHIFT (0U) -#define EMC_DYNAMICRC_TRC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRC_TRC_SHIFT)) & EMC_DYNAMICRC_TRC_MASK) - -/*! @name DYNAMICRFC - Selects the auto-refresh period */ -#define EMC_DYNAMICRFC_TRFC_MASK (0x1FU) -#define EMC_DYNAMICRFC_TRFC_SHIFT (0U) -#define EMC_DYNAMICRFC_TRFC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRFC_TRFC_SHIFT)) & EMC_DYNAMICRFC_TRFC_MASK) - -/*! @name DYNAMICXSR - Time for exit self-refresh to active command */ -#define EMC_DYNAMICXSR_TXSR_MASK (0x1FU) -#define EMC_DYNAMICXSR_TXSR_SHIFT (0U) -#define EMC_DYNAMICXSR_TXSR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICXSR_TXSR_SHIFT)) & EMC_DYNAMICXSR_TXSR_MASK) - -/*! @name DYNAMICRRD - Latency for active bank A to active bank B */ -#define EMC_DYNAMICRRD_TRRD_MASK (0xFU) -#define EMC_DYNAMICRRD_TRRD_SHIFT (0U) -#define EMC_DYNAMICRRD_TRRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRRD_TRRD_SHIFT)) & EMC_DYNAMICRRD_TRRD_MASK) - -/*! @name DYNAMICMRD - Time for load mode register to active command */ -#define EMC_DYNAMICMRD_TMRD_MASK (0xFU) -#define EMC_DYNAMICMRD_TMRD_SHIFT (0U) -#define EMC_DYNAMICMRD_TMRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICMRD_TMRD_SHIFT)) & EMC_DYNAMICMRD_TMRD_MASK) - -/*! @name STATICEXTENDEDWAIT - Time for long static memory read and write transfers */ -#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK (0x3FFU) -#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT (0U) -#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT)) & EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK) - -/*! @name DYNAMIC_DYNAMICCONFIG - Configuration information for EMC_DYCSx */ -#define EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK (0x18U) -#define EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT (3U) -#define EMC_DYNAMIC_DYNAMICCONFIG_MD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK) -#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK (0x1F80U) -#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT (7U) -#define EMC_DYNAMIC_DYNAMICCONFIG_AM0(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK) -#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK (0x4000U) -#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT (14U) -#define EMC_DYNAMIC_DYNAMICCONFIG_AM1(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK) -#define EMC_DYNAMIC_DYNAMICCONFIG_B_MASK (0x80000U) -#define EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT (19U) -#define EMC_DYNAMIC_DYNAMICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_B_MASK) -#define EMC_DYNAMIC_DYNAMICCONFIG_P_MASK (0x100000U) -#define EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT (20U) -#define EMC_DYNAMIC_DYNAMICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_P_MASK) - -/* The count of EMC_DYNAMIC_DYNAMICCONFIG */ -#define EMC_DYNAMIC_DYNAMICCONFIG_COUNT (4U) - -/*! @name DYNAMIC_DYNAMICRASCAS - RAS and CAS latencies for EMC_DYCSx */ -#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK (0x3U) -#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT (0U) -#define EMC_DYNAMIC_DYNAMICRASCAS_RAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK) -#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK (0x300U) -#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT (8U) -#define EMC_DYNAMIC_DYNAMICRASCAS_CAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK) - -/* The count of EMC_DYNAMIC_DYNAMICRASCAS */ -#define EMC_DYNAMIC_DYNAMICRASCAS_COUNT (4U) - -/*! @name STATIC_STATICCONFIG - Configuration for EMC_CSx */ -#define EMC_STATIC_STATICCONFIG_MW_MASK (0x3U) -#define EMC_STATIC_STATICCONFIG_MW_SHIFT (0U) -#define EMC_STATIC_STATICCONFIG_MW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_MW_SHIFT)) & EMC_STATIC_STATICCONFIG_MW_MASK) -#define EMC_STATIC_STATICCONFIG_PM_MASK (0x8U) -#define EMC_STATIC_STATICCONFIG_PM_SHIFT (3U) -#define EMC_STATIC_STATICCONFIG_PM(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PM_SHIFT)) & EMC_STATIC_STATICCONFIG_PM_MASK) -#define EMC_STATIC_STATICCONFIG_PC_MASK (0x40U) -#define EMC_STATIC_STATICCONFIG_PC_SHIFT (6U) -#define EMC_STATIC_STATICCONFIG_PC(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PC_SHIFT)) & EMC_STATIC_STATICCONFIG_PC_MASK) -#define EMC_STATIC_STATICCONFIG_PB_MASK (0x80U) -#define EMC_STATIC_STATICCONFIG_PB_SHIFT (7U) -#define EMC_STATIC_STATICCONFIG_PB(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PB_SHIFT)) & EMC_STATIC_STATICCONFIG_PB_MASK) -#define EMC_STATIC_STATICCONFIG_EW_MASK (0x100U) -#define EMC_STATIC_STATICCONFIG_EW_SHIFT (8U) -#define EMC_STATIC_STATICCONFIG_EW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_EW_SHIFT)) & EMC_STATIC_STATICCONFIG_EW_MASK) -#define EMC_STATIC_STATICCONFIG_B_MASK (0x80000U) -#define EMC_STATIC_STATICCONFIG_B_SHIFT (19U) -#define EMC_STATIC_STATICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_B_SHIFT)) & EMC_STATIC_STATICCONFIG_B_MASK) -#define EMC_STATIC_STATICCONFIG_P_MASK (0x100000U) -#define EMC_STATIC_STATICCONFIG_P_SHIFT (20U) -#define EMC_STATIC_STATICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_P_SHIFT)) & EMC_STATIC_STATICCONFIG_P_MASK) - -/* The count of EMC_STATIC_STATICCONFIG */ -#define EMC_STATIC_STATICCONFIG_COUNT (4U) - -/*! @name STATIC_STATICWAITWEN - Delay from EMC_CSx to write enable */ -#define EMC_STATIC_STATICWAITWEN_WAITWEN_MASK (0xFU) -#define EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT (0U) -#define EMC_STATIC_STATICWAITWEN_WAITWEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT)) & EMC_STATIC_STATICWAITWEN_WAITWEN_MASK) - -/* The count of EMC_STATIC_STATICWAITWEN */ -#define EMC_STATIC_STATICWAITWEN_COUNT (4U) - -/*! @name STATIC_STATICWAITOEN - Delay from EMC_CSx or address change, whichever is later, to output enable */ -#define EMC_STATIC_STATICWAITOEN_WAITOEN_MASK (0xFU) -#define EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT (0U) -#define EMC_STATIC_STATICWAITOEN_WAITOEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT)) & EMC_STATIC_STATICWAITOEN_WAITOEN_MASK) - -/* The count of EMC_STATIC_STATICWAITOEN */ -#define EMC_STATIC_STATICWAITOEN_COUNT (4U) - -/*! @name STATIC_STATICWAITRD - Delay from EMC_CSx to a read access */ -#define EMC_STATIC_STATICWAITRD_WAITRD_MASK (0x1FU) -#define EMC_STATIC_STATICWAITRD_WAITRD_SHIFT (0U) -#define EMC_STATIC_STATICWAITRD_WAITRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITRD_WAITRD_SHIFT)) & EMC_STATIC_STATICWAITRD_WAITRD_MASK) - -/* The count of EMC_STATIC_STATICWAITRD */ -#define EMC_STATIC_STATICWAITRD_COUNT (4U) - -/*! @name STATIC_STATICWAITPAGE - Delay for asynchronous page mode sequential accesses for EMC_CSx */ -#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK (0x1FU) -#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT (0U) -#define EMC_STATIC_STATICWAITPAGE_WAITPAGE(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT)) & EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK) - -/* The count of EMC_STATIC_STATICWAITPAGE */ -#define EMC_STATIC_STATICWAITPAGE_COUNT (4U) - -/*! @name STATIC_STATICWAITWR - Delay from EMC_CSx to a write access */ -#define EMC_STATIC_STATICWAITWR_WAITWR_MASK (0x1FU) -#define EMC_STATIC_STATICWAITWR_WAITWR_SHIFT (0U) -#define EMC_STATIC_STATICWAITWR_WAITWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWR_WAITWR_SHIFT)) & EMC_STATIC_STATICWAITWR_WAITWR_MASK) - -/* The count of EMC_STATIC_STATICWAITWR */ -#define EMC_STATIC_STATICWAITWR_COUNT (4U) - -/*! @name STATIC_STATICWAITTURN - Number of bus turnaround cycles EMC_CSx */ -#define EMC_STATIC_STATICWAITTURN_WAITTURN_MASK (0xFU) -#define EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT (0U) -#define EMC_STATIC_STATICWAITTURN_WAITTURN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT)) & EMC_STATIC_STATICWAITTURN_WAITTURN_MASK) - -/* The count of EMC_STATIC_STATICWAITTURN */ -#define EMC_STATIC_STATICWAITTURN_COUNT (4U) - - -/*! - * @} - */ /* end of group EMC_Register_Masks */ - - -/* EMC - Peripheral instance base addresses */ -/** Peripheral EMC base address */ -#define EMC_BASE (0x40081000u) -/** Peripheral EMC base pointer */ -#define EMC ((EMC_Type *)EMC_BASE) -/** Array initializer of EMC peripheral base addresses */ -#define EMC_BASE_ADDRS { EMC_BASE } -/** Array initializer of EMC peripheral base pointers */ -#define EMC_BASE_PTRS { EMC } - -/*! - * @} - */ /* end of group EMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ENET Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer - * @{ - */ - -/** ENET - Register Layout Typedef */ -typedef struct { - __IO uint32_t MAC_CONFIG; /**< MAC configuration register, offset: 0x0 */ - __IO uint32_t MAC_EXT_CONFIG; /**< , offset: 0x4 */ - __IO uint32_t MAC_FRAME_FILTER; /**< MAC frame filter register, offset: 0x8 */ - __IO uint32_t MAC_WD_TIMEROUT; /**< MAC watchdog Timeout register, offset: 0xC */ - uint8_t RESERVED_0[64]; - __IO uint32_t MAC_VLAN_TAG; /**< MAC vlan tag register, offset: 0x50 */ - uint8_t RESERVED_1[28]; - __IO uint32_t MAC_TX_FLOW_CTRL_Q[2]; /**< Transmit flow control register, array offset: 0x70, array step: 0x4 */ - uint8_t RESERVED_2[24]; - __IO uint32_t MAC_RX_FLOW_CTRL; /**< Receive flow control register, offset: 0x90 */ - uint8_t RESERVED_3[4]; - __IO uint32_t MAC_TXQ_PRIO_MAP; /**< , offset: 0x98 */ - uint8_t RESERVED_4[4]; - __IO uint32_t MAC_RXQ_CTRL[3]; /**< Receive Queue Control 0 register 0x0000, array offset: 0xA0, array step: 0x4 */ - uint8_t RESERVED_5[4]; - __I uint32_t MAC_INTR_STAT; /**< Interrupt status register 0x0000, offset: 0xB0 */ - __IO uint32_t MAC_INTR_EN; /**< Interrupt enable register 0x0000, offset: 0xB4 */ - __I uint32_t MAC_RXTX_STAT; /**< Receive Transmit Status register, offset: 0xB8 */ - uint8_t RESERVED_6[4]; - __IO uint32_t MAC_PMT_CRTL_STAT; /**< , offset: 0xC0 */ - __IO uint32_t MAC_RWAKE_FRFLT; /**< Remote wake-up frame filter, offset: 0xC4 */ - uint8_t RESERVED_7[8]; - __IO uint32_t MAC_LPI_CTRL_STAT; /**< LPI Control and Status Register, offset: 0xD0 */ - __IO uint32_t MAC_LPI_TIMER_CTRL; /**< LPI Timers Control register, offset: 0xD4 */ - __IO uint32_t MAC_LPI_ENTR_TIMR; /**< LPI entry Timer register, offset: 0xD8 */ - __IO uint32_t MAC_1US_TIC_COUNTR; /**< , offset: 0xDC */ - uint8_t RESERVED_8[48]; - __IO uint32_t MAC_VERSION; /**< MAC version register, offset: 0x110 */ - __I uint32_t MAC_DBG; /**< MAC debug register, offset: 0x114 */ - uint8_t RESERVED_9[4]; - __IO uint32_t MAC_HW_FEAT[3]; /**< MAC hardware feature register 0x0201, array offset: 0x11C, array step: 0x4 */ - uint8_t RESERVED_10[216]; - __IO uint32_t MAC_MDIO_ADDR; /**< MIDO address Register, offset: 0x200 */ - __IO uint32_t MAC_MDIO_DATA; /**< MDIO Data register, offset: 0x204 */ - uint8_t RESERVED_11[248]; - __IO uint32_t MAC_ADDR_HIGH; /**< MAC address0 high register, offset: 0x300 */ - __IO uint32_t MAC_ADDR_LOW; /**< MAC address0 low register, offset: 0x304 */ - uint8_t RESERVED_12[2040]; - __IO uint32_t MAC_TIMESTAMP_CTRL; /**< Time stamp control register, offset: 0xB00 */ - __IO uint32_t MAC_SUB_SCND_INCR; /**< Sub-second increment register, offset: 0xB04 */ - __I uint32_t MAC_SYS_TIME_SCND; /**< System time seconds register, offset: 0xB08 */ - __I uint32_t MAC_SYS_TIME_NSCND; /**< System time nanoseconds register, offset: 0xB0C */ - __IO uint32_t MAC_SYS_TIME_SCND_UPD; /**< , offset: 0xB10 */ - __IO uint32_t MAC_SYS_TIME_NSCND_UPD; /**< , offset: 0xB14 */ - __IO uint32_t MAC_SYS_TIMESTMP_ADDEND; /**< Time stamp addend register, offset: 0xB18 */ - __IO uint32_t MAC_SYS_TIME_HWORD_SCND; /**< , offset: 0xB1C */ - __I uint32_t MAC_SYS_TIMESTMP_STAT; /**< Time stamp status register, offset: 0xB20 */ - uint8_t RESERVED_13[12]; - __I uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Tx timestamp status nanoseconds, offset: 0xB30 */ - __I uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS; /**< Tx timestamp status seconds, offset: 0xB34 */ - uint8_t RESERVED_14[32]; - __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp ingress correction, offset: 0xB58 */ - __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp egress correction, offset: 0xB5C */ - uint8_t RESERVED_15[160]; - __IO uint32_t MTL_OP_MODE; /**< MTL Operation Mode Register, offset: 0xC00 */ - uint8_t RESERVED_16[28]; - __I uint32_t MTL_INTR_STAT; /**< MTL Interrupt Status register, offset: 0xC20 */ - uint8_t RESERVED_17[12]; - __IO uint32_t MTL_RXQ_DMA_MAP; /**< MTL Receive Queue and DMA Channel Mapping register, offset: 0xC30 */ - uint8_t RESERVED_18[204]; - struct { /* offset: 0xD00, array step: 0x40 */ - __IO uint32_t MTL_TXQX_OP_MODE; /**< MTL TxQx Operation Mode register, array offset: 0xD00, array step: 0x40 */ - __I uint32_t MTL_TXQX_UNDRFLW; /**< MTL TxQx Underflow register, array offset: 0xD04, array step: 0x40 */ - __I uint32_t MTL_TXQX_DBG; /**< MTL TxQx Debug register, array offset: 0xD08, array step: 0x40 */ - uint8_t RESERVED_0[4]; - __IO uint32_t MTL_TXQX_ETS_CTRL; /**< MTL TxQx ETS control register, only TxQ1 support, array offset: 0xD10, array step: 0x40 */ - __IO uint32_t MTL_TXQX_ETS_STAT; /**< MTL TxQx ETS Status register, array offset: 0xD14, array step: 0x40 */ - __IO uint32_t MTL_TXQX_QNTM_WGHT; /**< , array offset: 0xD18, array step: 0x40 */ - __IO uint32_t MTL_TXQX_SNDSLP_CRDT; /**< MTL TxQx SendSlopCredit register, only TxQ1 support, array offset: 0xD1C, array step: 0x40 */ - __IO uint32_t MTL_TXQX_HI_CRDT; /**< MTL TxQx hiCredit register, only TxQ1 support, array offset: 0xD20, array step: 0x40 */ - __IO uint32_t MTL_TXQX_LO_CRDT; /**< MTL TxQx loCredit register, only TxQ1 support, array offset: 0xD24, array step: 0x40 */ - uint8_t RESERVED_1[4]; - __IO uint32_t MTL_TXQX_INTCTRL_STAT; /**< , array offset: 0xD2C, array step: 0x40 */ - __IO uint32_t MTL_RXQX_OP_MODE; /**< MTL RxQx Operation Mode register, array offset: 0xD30, array step: 0x40 */ - __IO uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT; /**< MTL RxQx Missed Packet Overflow Counter register, array offset: 0xD34, array step: 0x40 */ - __IO uint32_t MTL_RXQX_DBG; /**< MTL RxQx Debug register, array offset: 0xD38, array step: 0x40 */ - __IO uint32_t MTL_RXQX_CTRL; /**< MTL RxQx Control register, array offset: 0xD3C, array step: 0x40 */ - } MTL_QUEUE[2]; - uint8_t RESERVED_19[640]; - __IO uint32_t DMA_MODE; /**< DMA mode register, offset: 0x1000 */ - __IO uint32_t DMA_SYSBUS_MODE; /**< DMA System Bus mode, offset: 0x1004 */ - __IO uint32_t DMA_INTR_STAT; /**< DMA Interrupt status, offset: 0x1008 */ - __IO uint32_t DMA_DBG_STAT; /**< DMA Debug Status, offset: 0x100C */ - uint8_t RESERVED_20[240]; - struct { /* offset: 0x1100, array step: 0x80 */ - __IO uint32_t DMA_CHX_CTRL; /**< DMA Channelx Control, array offset: 0x1100, array step: 0x80 */ - __IO uint32_t DMA_CHX_TX_CTRL; /**< DMA Channelx Transmit Control, array offset: 0x1104, array step: 0x80 */ - __IO uint32_t DMA_CHX_RX_CTRL; /**< DMA Channelx Receive Control, array offset: 0x1108, array step: 0x80 */ - uint8_t RESERVED_0[8]; - __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR; /**< , array offset: 0x1114, array step: 0x80 */ - uint8_t RESERVED_1[4]; - __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR; /**< , array offset: 0x111C, array step: 0x80 */ - __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR; /**< , array offset: 0x1120, array step: 0x80 */ - uint8_t RESERVED_2[4]; - __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR; /**< , array offset: 0x1128, array step: 0x80 */ - __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH; /**< , array offset: 0x112C, array step: 0x80 */ - __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH; /**< Channelx Rx descriptor Ring Length, array offset: 0x1130, array step: 0x80 */ - __IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1134, array step: 0x80 */ - __IO uint32_t DMA_CHX_RX_INT_WDTIMER; /**< Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */ - __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT; /**< Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */ - uint8_t RESERVED_3[4]; - __I uint32_t DMA_CHX_CUR_HST_TXDESC; /**< Channelx Current Host Transmit descriptor, array offset: 0x1144, array step: 0x80 */ - uint8_t RESERVED_4[4]; - __I uint32_t DMA_CHX_CUR_HST_RXDESC; /**< , array offset: 0x114C, array step: 0x80 */ - uint8_t RESERVED_5[4]; - __I uint32_t DMA_CHX_CUR_HST_TXBUF; /**< , array offset: 0x1154, array step: 0x80 */ - uint8_t RESERVED_6[4]; - __I uint32_t DMA_CHX_CUR_HST_RXBUF; /**< Channelx Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */ - __IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: 0x1160, array step: 0x80 */ - uint8_t RESERVED_7[28]; - } DMA_CH[2]; -} ENET_Type; - -/* ---------------------------------------------------------------------------- - -- ENET Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ENET_Register_Masks ENET Register Masks - * @{ - */ - -/*! @name MAC_CONFIG - MAC configuration register */ -#define ENET_MAC_CONFIG_RE_MASK (0x1U) -#define ENET_MAC_CONFIG_RE_SHIFT (0U) -#define ENET_MAC_CONFIG_RE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_RE_SHIFT)) & ENET_MAC_CONFIG_RE_MASK) -#define ENET_MAC_CONFIG_TE_MASK (0x2U) -#define ENET_MAC_CONFIG_TE_SHIFT (1U) -#define ENET_MAC_CONFIG_TE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_TE_SHIFT)) & ENET_MAC_CONFIG_TE_MASK) -#define ENET_MAC_CONFIG_PRELEN_MASK (0xCU) -#define ENET_MAC_CONFIG_PRELEN_SHIFT (2U) -#define ENET_MAC_CONFIG_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PRELEN_SHIFT)) & ENET_MAC_CONFIG_PRELEN_MASK) -#define ENET_MAC_CONFIG_DC_MASK (0x10U) -#define ENET_MAC_CONFIG_DC_SHIFT (4U) -#define ENET_MAC_CONFIG_DC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DC_SHIFT)) & ENET_MAC_CONFIG_DC_MASK) -#define ENET_MAC_CONFIG_BL_MASK (0x60U) -#define ENET_MAC_CONFIG_BL_SHIFT (5U) -#define ENET_MAC_CONFIG_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BL_SHIFT)) & ENET_MAC_CONFIG_BL_MASK) -#define ENET_MAC_CONFIG_DR_MASK (0x100U) -#define ENET_MAC_CONFIG_DR_SHIFT (8U) -#define ENET_MAC_CONFIG_DR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DR_SHIFT)) & ENET_MAC_CONFIG_DR_MASK) -#define ENET_MAC_CONFIG_DCRS_MASK (0x200U) -#define ENET_MAC_CONFIG_DCRS_SHIFT (9U) -#define ENET_MAC_CONFIG_DCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DCRS_SHIFT)) & ENET_MAC_CONFIG_DCRS_MASK) -#define ENET_MAC_CONFIG_DO_MASK (0x400U) -#define ENET_MAC_CONFIG_DO_SHIFT (10U) -#define ENET_MAC_CONFIG_DO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DO_SHIFT)) & ENET_MAC_CONFIG_DO_MASK) -#define ENET_MAC_CONFIG_ECRSFD_MASK (0x800U) -#define ENET_MAC_CONFIG_ECRSFD_SHIFT (11U) -#define ENET_MAC_CONFIG_ECRSFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ECRSFD_SHIFT)) & ENET_MAC_CONFIG_ECRSFD_MASK) -#define ENET_MAC_CONFIG_LM_MASK (0x1000U) -#define ENET_MAC_CONFIG_LM_SHIFT (12U) -#define ENET_MAC_CONFIG_LM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_LM_SHIFT)) & ENET_MAC_CONFIG_LM_MASK) -#define ENET_MAC_CONFIG_DM_MASK (0x2000U) -#define ENET_MAC_CONFIG_DM_SHIFT (13U) -#define ENET_MAC_CONFIG_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DM_SHIFT)) & ENET_MAC_CONFIG_DM_MASK) -#define ENET_MAC_CONFIG_FES_MASK (0x4000U) -#define ENET_MAC_CONFIG_FES_SHIFT (14U) -#define ENET_MAC_CONFIG_FES(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_FES_SHIFT)) & ENET_MAC_CONFIG_FES_MASK) -#define ENET_MAC_CONFIG_PS_MASK (0x8000U) -#define ENET_MAC_CONFIG_PS_SHIFT (15U) -#define ENET_MAC_CONFIG_PS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PS_SHIFT)) & ENET_MAC_CONFIG_PS_MASK) -#define ENET_MAC_CONFIG_JE_MASK (0x10000U) -#define ENET_MAC_CONFIG_JE_SHIFT (16U) -#define ENET_MAC_CONFIG_JE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JE_SHIFT)) & ENET_MAC_CONFIG_JE_MASK) -#define ENET_MAC_CONFIG_JD_MASK (0x20000U) -#define ENET_MAC_CONFIG_JD_SHIFT (17U) -#define ENET_MAC_CONFIG_JD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JD_SHIFT)) & ENET_MAC_CONFIG_JD_MASK) -#define ENET_MAC_CONFIG_BE_MASK (0x40000U) -#define ENET_MAC_CONFIG_BE_SHIFT (18U) -#define ENET_MAC_CONFIG_BE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BE_SHIFT)) & ENET_MAC_CONFIG_BE_MASK) -#define ENET_MAC_CONFIG_WD_MASK (0x80000U) -#define ENET_MAC_CONFIG_WD_SHIFT (19U) -#define ENET_MAC_CONFIG_WD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_WD_SHIFT)) & ENET_MAC_CONFIG_WD_MASK) -#define ENET_MAC_CONFIG_ACS_MASK (0x100000U) -#define ENET_MAC_CONFIG_ACS_SHIFT (20U) -#define ENET_MAC_CONFIG_ACS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ACS_SHIFT)) & ENET_MAC_CONFIG_ACS_MASK) -#define ENET_MAC_CONFIG_CST_MASK (0x200000U) -#define ENET_MAC_CONFIG_CST_SHIFT (21U) -#define ENET_MAC_CONFIG_CST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_CST_SHIFT)) & ENET_MAC_CONFIG_CST_MASK) -#define ENET_MAC_CONFIG_S2KP_MASK (0x400000U) -#define ENET_MAC_CONFIG_S2KP_SHIFT (22U) -#define ENET_MAC_CONFIG_S2KP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_S2KP_SHIFT)) & ENET_MAC_CONFIG_S2KP_MASK) -#define ENET_MAC_CONFIG_GPSLCE_MASK (0x800000U) -#define ENET_MAC_CONFIG_GPSLCE_SHIFT (23U) -#define ENET_MAC_CONFIG_GPSLCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_GPSLCE_SHIFT)) & ENET_MAC_CONFIG_GPSLCE_MASK) -#define ENET_MAC_CONFIG_IPG_MASK (0x7000000U) -#define ENET_MAC_CONFIG_IPG_SHIFT (24U) -#define ENET_MAC_CONFIG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPG_SHIFT)) & ENET_MAC_CONFIG_IPG_MASK) -#define ENET_MAC_CONFIG_IPC_MASK (0x8000000U) -#define ENET_MAC_CONFIG_IPC_SHIFT (27U) -#define ENET_MAC_CONFIG_IPC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPC_SHIFT)) & ENET_MAC_CONFIG_IPC_MASK) - -/*! @name MAC_EXT_CONFIG - */ -#define ENET_MAC_EXT_CONFIG_GPSL_MASK (0x3FFFU) -#define ENET_MAC_EXT_CONFIG_GPSL_SHIFT (0U) -#define ENET_MAC_EXT_CONFIG_GPSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_GPSL_SHIFT)) & ENET_MAC_EXT_CONFIG_GPSL_MASK) -#define ENET_MAC_EXT_CONFIG_DCRCC_MASK (0x10000U) -#define ENET_MAC_EXT_CONFIG_DCRCC_SHIFT (16U) -#define ENET_MAC_EXT_CONFIG_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_DCRCC_SHIFT)) & ENET_MAC_EXT_CONFIG_DCRCC_MASK) -#define ENET_MAC_EXT_CONFIG_SPEN_MASK (0x20000U) -#define ENET_MAC_EXT_CONFIG_SPEN_SHIFT (17U) -#define ENET_MAC_EXT_CONFIG_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_SPEN_SHIFT)) & ENET_MAC_EXT_CONFIG_SPEN_MASK) -#define ENET_MAC_EXT_CONFIG_USP_MASK (0x40000U) -#define ENET_MAC_EXT_CONFIG_USP_SHIFT (18U) -#define ENET_MAC_EXT_CONFIG_USP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_USP_SHIFT)) & ENET_MAC_EXT_CONFIG_USP_MASK) - -/*! @name MAC_FRAME_FILTER - MAC frame filter register */ -#define ENET_MAC_FRAME_FILTER_PR_MASK (0x1U) -#define ENET_MAC_FRAME_FILTER_PR_SHIFT (0U) -#define ENET_MAC_FRAME_FILTER_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PR_SHIFT)) & ENET_MAC_FRAME_FILTER_PR_MASK) -#define ENET_MAC_FRAME_FILTER_DAIF_MASK (0x8U) -#define ENET_MAC_FRAME_FILTER_DAIF_SHIFT (3U) -#define ENET_MAC_FRAME_FILTER_DAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_DAIF_MASK) -#define ENET_MAC_FRAME_FILTER_PM_MASK (0x10U) -#define ENET_MAC_FRAME_FILTER_PM_SHIFT (4U) -#define ENET_MAC_FRAME_FILTER_PM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PM_SHIFT)) & ENET_MAC_FRAME_FILTER_PM_MASK) -#define ENET_MAC_FRAME_FILTER_DBF_MASK (0x20U) -#define ENET_MAC_FRAME_FILTER_DBF_SHIFT (5U) -#define ENET_MAC_FRAME_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DBF_SHIFT)) & ENET_MAC_FRAME_FILTER_DBF_MASK) -#define ENET_MAC_FRAME_FILTER_PCF_MASK (0xC0U) -#define ENET_MAC_FRAME_FILTER_PCF_SHIFT (6U) -#define ENET_MAC_FRAME_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PCF_SHIFT)) & ENET_MAC_FRAME_FILTER_PCF_MASK) -#define ENET_MAC_FRAME_FILTER_SAIF_MASK (0x100U) -#define ENET_MAC_FRAME_FILTER_SAIF_SHIFT (8U) -#define ENET_MAC_FRAME_FILTER_SAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAIF_MASK) -#define ENET_MAC_FRAME_FILTER_SAF_MASK (0x200U) -#define ENET_MAC_FRAME_FILTER_SAF_SHIFT (9U) -#define ENET_MAC_FRAME_FILTER_SAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAF_MASK) -#define ENET_MAC_FRAME_FILTER_RA_MASK (0x80000000U) -#define ENET_MAC_FRAME_FILTER_RA_SHIFT (31U) -#define ENET_MAC_FRAME_FILTER_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_RA_SHIFT)) & ENET_MAC_FRAME_FILTER_RA_MASK) - -/*! @name MAC_WD_TIMEROUT - MAC watchdog Timeout register */ -#define ENET_MAC_WD_TIMEROUT_WTO_MASK (0xFU) -#define ENET_MAC_WD_TIMEROUT_WTO_SHIFT (0U) -#define ENET_MAC_WD_TIMEROUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_WTO_SHIFT)) & ENET_MAC_WD_TIMEROUT_WTO_MASK) -#define ENET_MAC_WD_TIMEROUT_PWE_MASK (0x100U) -#define ENET_MAC_WD_TIMEROUT_PWE_SHIFT (8U) -#define ENET_MAC_WD_TIMEROUT_PWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_PWE_SHIFT)) & ENET_MAC_WD_TIMEROUT_PWE_MASK) - -/*! @name MAC_VLAN_TAG - MAC vlan tag register */ -#define ENET_MAC_VLAN_TAG_VL_MASK (0xFFFFU) -#define ENET_MAC_VLAN_TAG_VL_SHIFT (0U) -#define ENET_MAC_VLAN_TAG_VL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VL_SHIFT)) & ENET_MAC_VLAN_TAG_VL_MASK) -#define ENET_MAC_VLAN_TAG_ETV_MASK (0x10000U) -#define ENET_MAC_VLAN_TAG_ETV_SHIFT (16U) -#define ENET_MAC_VLAN_TAG_ETV(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ETV_SHIFT)) & ENET_MAC_VLAN_TAG_ETV_MASK) -#define ENET_MAC_VLAN_TAG_VTIM_MASK (0x20000U) -#define ENET_MAC_VLAN_TAG_VTIM_SHIFT (17U) -#define ENET_MAC_VLAN_TAG_VTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTIM_SHIFT)) & ENET_MAC_VLAN_TAG_VTIM_MASK) -#define ENET_MAC_VLAN_TAG_ESVL_MASK (0x40000U) -#define ENET_MAC_VLAN_TAG_ESVL_SHIFT (18U) -#define ENET_MAC_VLAN_TAG_ESVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ESVL_SHIFT)) & ENET_MAC_VLAN_TAG_ESVL_MASK) -#define ENET_MAC_VLAN_TAG_ERSVLM_MASK (0x80000U) -#define ENET_MAC_VLAN_TAG_ERSVLM_SHIFT (19U) -#define ENET_MAC_VLAN_TAG_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERSVLM_SHIFT)) & ENET_MAC_VLAN_TAG_ERSVLM_MASK) -#define ENET_MAC_VLAN_TAG_DOVLTC_MASK (0x100000U) -#define ENET_MAC_VLAN_TAG_DOVLTC_SHIFT (20U) -#define ENET_MAC_VLAN_TAG_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_DOVLTC_SHIFT)) & ENET_MAC_VLAN_TAG_DOVLTC_MASK) -#define ENET_MAC_VLAN_TAG_EVLS_MASK (0x600000U) -#define ENET_MAC_VLAN_TAG_EVLS_SHIFT (21U) -#define ENET_MAC_VLAN_TAG_EVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLS_MASK) -#define ENET_MAC_VLAN_TAG_EVLRXS_MASK (0x1000000U) -#define ENET_MAC_VLAN_TAG_EVLRXS_SHIFT (24U) -#define ENET_MAC_VLAN_TAG_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLRXS_MASK) -#define ENET_MAC_VLAN_TAG_VTHM_MASK (0x2000000U) -#define ENET_MAC_VLAN_TAG_VTHM_SHIFT (25U) -#define ENET_MAC_VLAN_TAG_VTHM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTHM_SHIFT)) & ENET_MAC_VLAN_TAG_VTHM_MASK) -#define ENET_MAC_VLAN_TAG_EDVLP_MASK (0x4000000U) -#define ENET_MAC_VLAN_TAG_EDVLP_SHIFT (26U) -#define ENET_MAC_VLAN_TAG_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EDVLP_SHIFT)) & ENET_MAC_VLAN_TAG_EDVLP_MASK) -#define ENET_MAC_VLAN_TAG_ERIVLT_MASK (0x8000000U) -#define ENET_MAC_VLAN_TAG_ERIVLT_SHIFT (27U) -#define ENET_MAC_VLAN_TAG_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERIVLT_SHIFT)) & ENET_MAC_VLAN_TAG_ERIVLT_MASK) -#define ENET_MAC_VLAN_TAG_EIVLS_MASK (0x30000000U) -#define ENET_MAC_VLAN_TAG_EIVLS_SHIFT (28U) -#define ENET_MAC_VLAN_TAG_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLS_MASK) -#define ENET_MAC_VLAN_TAG_EIVLRXS_MASK (0x80000000U) -#define ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT (31U) -#define ENET_MAC_VLAN_TAG_EIVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLRXS_MASK) - -/*! @name MAC_TX_FLOW_CTRL_Q - Transmit flow control register */ -#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK (0x1U) -#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT (0U) -#define ENET_MAC_TX_FLOW_CTRL_Q_FCB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK) -#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK (0x2U) -#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT (1U) -#define ENET_MAC_TX_FLOW_CTRL_Q_TFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK) -#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U) -#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U) -#define ENET_MAC_TX_FLOW_CTRL_Q_PLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK) -#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U) -#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U) -#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK) -#define ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xFFFF0000U) -#define ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16U) -#define ENET_MAC_TX_FLOW_CTRL_Q_PT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK) - -/* The count of ENET_MAC_TX_FLOW_CTRL_Q */ -#define ENET_MAC_TX_FLOW_CTRL_Q_COUNT (2U) - -/*! @name MAC_RX_FLOW_CTRL - Receive flow control register */ -#define ENET_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U) -#define ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U) -#define ENET_MAC_RX_FLOW_CTRL_RFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_RFE_MASK) -#define ENET_MAC_RX_FLOW_CTRL_UP_MASK (0x2U) -#define ENET_MAC_RX_FLOW_CTRL_UP_SHIFT (1U) -#define ENET_MAC_RX_FLOW_CTRL_UP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_UP_MASK) - -/*! @name MAC_TXQ_PRIO_MAP - */ -#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK (0xFFU) -#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT (0U) -#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK) -#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK (0xFF00U) -#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT (8U) -#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK) - -/*! @name MAC_RXQ_CTRL - Receive Queue Control 0 register 0x0000 */ -#define ENET_MAC_RXQ_CTRL_RXQ0EN_MASK (0x3U) -#define ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT (0U) -#define ENET_MAC_RXQ_CTRL_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ0EN_MASK) -#define ENET_MAC_RXQ_CTRL_PSRQ0_MASK (0xFFU) -#define ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT (0U) -#define ENET_MAC_RXQ_CTRL_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ0_MASK) -#define ENET_MAC_RXQ_CTRL_AVCPQ_MASK (0x7U) -#define ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT (0U) -#define ENET_MAC_RXQ_CTRL_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVCPQ_MASK) -#define ENET_MAC_RXQ_CTRL_RXQ1EN_MASK (0xCU) -#define ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT (2U) -#define ENET_MAC_RXQ_CTRL_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ1EN_MASK) -#define ENET_MAC_RXQ_CTRL_AVPTPQ_MASK (0x70U) -#define ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT (4U) -#define ENET_MAC_RXQ_CTRL_AVPTPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVPTPQ_MASK) -#define ENET_MAC_RXQ_CTRL_PSRQ1_MASK (0xFF00U) -#define ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT (8U) -#define ENET_MAC_RXQ_CTRL_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ1_MASK) -#define ENET_MAC_RXQ_CTRL_UPQ_MASK (0x7000U) -#define ENET_MAC_RXQ_CTRL_UPQ_SHIFT (12U) -#define ENET_MAC_RXQ_CTRL_UPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_UPQ_MASK) -#define ENET_MAC_RXQ_CTRL_PSRQ2_MASK (0xFF0000U) -#define ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT (16U) -#define ENET_MAC_RXQ_CTRL_PSRQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ2_MASK) -#define ENET_MAC_RXQ_CTRL_MCBCQ_MASK (0x70000U) -#define ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT (16U) -#define ENET_MAC_RXQ_CTRL_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQ_MASK) -#define ENET_MAC_RXQ_CTRL_MCBCQEN_MASK (0x100000U) -#define ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT (20U) -#define ENET_MAC_RXQ_CTRL_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQEN_MASK) -#define ENET_MAC_RXQ_CTRL_PSRQ3_MASK (0xFF000000U) -#define ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT (24U) -#define ENET_MAC_RXQ_CTRL_PSRQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ3_MASK) - -/* The count of ENET_MAC_RXQ_CTRL */ -#define ENET_MAC_RXQ_CTRL_COUNT (3U) - -/*! @name MAC_INTR_STAT - Interrupt status register 0x0000 */ -#define ENET_MAC_INTR_STAT_PHYIS_MASK (0x8U) -#define ENET_MAC_INTR_STAT_PHYIS_SHIFT (3U) -#define ENET_MAC_INTR_STAT_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PHYIS_SHIFT)) & ENET_MAC_INTR_STAT_PHYIS_MASK) -#define ENET_MAC_INTR_STAT_PMTIS_MASK (0x10U) -#define ENET_MAC_INTR_STAT_PMTIS_SHIFT (4U) -#define ENET_MAC_INTR_STAT_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PMTIS_SHIFT)) & ENET_MAC_INTR_STAT_PMTIS_MASK) -#define ENET_MAC_INTR_STAT_LPIIS_MASK (0x20U) -#define ENET_MAC_INTR_STAT_LPIIS_SHIFT (5U) -#define ENET_MAC_INTR_STAT_LPIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_LPIIS_SHIFT)) & ENET_MAC_INTR_STAT_LPIIS_MASK) -#define ENET_MAC_INTR_STAT_TSIS_MASK (0x1000U) -#define ENET_MAC_INTR_STAT_TSIS_SHIFT (12U) -#define ENET_MAC_INTR_STAT_TSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TSIS_SHIFT)) & ENET_MAC_INTR_STAT_TSIS_MASK) -#define ENET_MAC_INTR_STAT_TXSTSIS_MASK (0x2000U) -#define ENET_MAC_INTR_STAT_TXSTSIS_SHIFT (13U) -#define ENET_MAC_INTR_STAT_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_TXSTSIS_MASK) -#define ENET_MAC_INTR_STAT_RXSTSIS_MASK (0x4000U) -#define ENET_MAC_INTR_STAT_RXSTSIS_SHIFT (14U) -#define ENET_MAC_INTR_STAT_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_RXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_RXSTSIS_MASK) - -/*! @name MAC_INTR_EN - Interrupt enable register 0x0000 */ -#define ENET_MAC_INTR_EN_PHYIE_MASK (0x8U) -#define ENET_MAC_INTR_EN_PHYIE_SHIFT (3U) -#define ENET_MAC_INTR_EN_PHYIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PHYIE_SHIFT)) & ENET_MAC_INTR_EN_PHYIE_MASK) -#define ENET_MAC_INTR_EN_PMTIE_MASK (0x10U) -#define ENET_MAC_INTR_EN_PMTIE_SHIFT (4U) -#define ENET_MAC_INTR_EN_PMTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PMTIE_SHIFT)) & ENET_MAC_INTR_EN_PMTIE_MASK) -#define ENET_MAC_INTR_EN_LPIIE_MASK (0x20U) -#define ENET_MAC_INTR_EN_LPIIE_SHIFT (5U) -#define ENET_MAC_INTR_EN_LPIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_LPIIE_SHIFT)) & ENET_MAC_INTR_EN_LPIIE_MASK) -#define ENET_MAC_INTR_EN_TSIE_MASK (0x1000U) -#define ENET_MAC_INTR_EN_TSIE_SHIFT (12U) -#define ENET_MAC_INTR_EN_TSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TSIE_SHIFT)) & ENET_MAC_INTR_EN_TSIE_MASK) -#define ENET_MAC_INTR_EN_TXSTSIE_MASK (0x2000U) -#define ENET_MAC_INTR_EN_TXSTSIE_SHIFT (13U) -#define ENET_MAC_INTR_EN_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TXSTSIE_SHIFT)) & ENET_MAC_INTR_EN_TXSTSIE_MASK) -#define ENET_MAC_INTR_EN_RXSTSIS_MASK (0x4000U) -#define ENET_MAC_INTR_EN_RXSTSIS_SHIFT (14U) -#define ENET_MAC_INTR_EN_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_RXSTSIS_SHIFT)) & ENET_MAC_INTR_EN_RXSTSIS_MASK) - -/*! @name MAC_RXTX_STAT - Receive Transmit Status register */ -#define ENET_MAC_RXTX_STAT_TJT_MASK (0x1U) -#define ENET_MAC_RXTX_STAT_TJT_SHIFT (0U) -#define ENET_MAC_RXTX_STAT_TJT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_TJT_SHIFT)) & ENET_MAC_RXTX_STAT_TJT_MASK) -#define ENET_MAC_RXTX_STAT_NCARR_MASK (0x2U) -#define ENET_MAC_RXTX_STAT_NCARR_SHIFT (1U) -#define ENET_MAC_RXTX_STAT_NCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_NCARR_SHIFT)) & ENET_MAC_RXTX_STAT_NCARR_MASK) -#define ENET_MAC_RXTX_STAT_LCARR_MASK (0x4U) -#define ENET_MAC_RXTX_STAT_LCARR_SHIFT (2U) -#define ENET_MAC_RXTX_STAT_LCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCARR_SHIFT)) & ENET_MAC_RXTX_STAT_LCARR_MASK) -#define ENET_MAC_RXTX_STAT_EXDEF_MASK (0x8U) -#define ENET_MAC_RXTX_STAT_EXDEF_SHIFT (3U) -#define ENET_MAC_RXTX_STAT_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXDEF_SHIFT)) & ENET_MAC_RXTX_STAT_EXDEF_MASK) -#define ENET_MAC_RXTX_STAT_LCOL_MASK (0x10U) -#define ENET_MAC_RXTX_STAT_LCOL_SHIFT (4U) -#define ENET_MAC_RXTX_STAT_LCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCOL_SHIFT)) & ENET_MAC_RXTX_STAT_LCOL_MASK) -#define ENET_MAC_RXTX_STAT_EXCOL_MASK (0x20U) -#define ENET_MAC_RXTX_STAT_EXCOL_SHIFT (5U) -#define ENET_MAC_RXTX_STAT_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXCOL_SHIFT)) & ENET_MAC_RXTX_STAT_EXCOL_MASK) -#define ENET_MAC_RXTX_STAT_RWT_MASK (0x100U) -#define ENET_MAC_RXTX_STAT_RWT_SHIFT (8U) -#define ENET_MAC_RXTX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_RWT_SHIFT)) & ENET_MAC_RXTX_STAT_RWT_MASK) - -/*! @name MAC_PMT_CRTL_STAT - */ -#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK (0x1U) -#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT (0U) -#define ENET_MAC_PMT_CRTL_STAT_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK) -#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK (0x2U) -#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT (1U) -#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK) -#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK (0x4U) -#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT (2U) -#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK) -#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK (0x20U) -#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT (5U) -#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK) -#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK (0x40U) -#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT (6U) -#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK) -#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK (0x200U) -#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT (9U) -#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK) -#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK (0x400U) -#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT (10U) -#define ENET_MAC_PMT_CRTL_STAT_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK) -#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK (0x1F000000U) -#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT (24U) -#define ENET_MAC_PMT_CRTL_STAT_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK) -#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK (0x80000000U) -#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT (31U) -#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK) - -/*! @name MAC_RWAKE_FRFLT - Remote wake-up frame filter */ -#define ENET_MAC_RWAKE_FRFLT_ADDR_MASK (0xFFFFFFFFU) -#define ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT (0U) -#define ENET_MAC_RWAKE_FRFLT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT)) & ENET_MAC_RWAKE_FRFLT_ADDR_MASK) - -/*! @name MAC_LPI_CTRL_STAT - LPI Control and Status Register */ -#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK (0x1U) -#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT (0U) -#define ENET_MAC_LPI_CTRL_STAT_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK) -#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK (0x2U) -#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT (1U) -#define ENET_MAC_LPI_CTRL_STAT_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK) -#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK (0x4U) -#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT (2U) -#define ENET_MAC_LPI_CTRL_STAT_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK) -#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK (0x8U) -#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT (3U) -#define ENET_MAC_LPI_CTRL_STAT_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK) -#define ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK (0x100U) -#define ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT (8U) -#define ENET_MAC_LPI_CTRL_STAT_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK) -#define ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK (0x200U) -#define ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT (9U) -#define ENET_MAC_LPI_CTRL_STAT_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK) -#define ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK (0x10000U) -#define ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT (16U) -#define ENET_MAC_LPI_CTRL_STAT_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK) -#define ENET_MAC_LPI_CTRL_STAT_PLS_MASK (0x20000U) -#define ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT (17U) -#define ENET_MAC_LPI_CTRL_STAT_PLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_PLS_MASK) -#define ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK (0x80000U) -#define ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT (19U) -#define ENET_MAC_LPI_CTRL_STAT_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK) -#define ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK (0x100000U) -#define ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT (20U) -#define ENET_MAC_LPI_CTRL_STAT_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK) -#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK (0x200000U) -#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT (21U) -#define ENET_MAC_LPI_CTRL_STAT_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK) - -/*! @name MAC_LPI_TIMER_CTRL - LPI Timers Control register */ -#define ENET_MAC_LPI_TIMER_CTRL_TWT_MASK (0xFFFFU) -#define ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT (0U) -#define ENET_MAC_LPI_TIMER_CTRL_TWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_TWT_MASK) -#define ENET_MAC_LPI_TIMER_CTRL_LST_MASK (0x3FF0000U) -#define ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT (16U) -#define ENET_MAC_LPI_TIMER_CTRL_LST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_LST_MASK) - -/*! @name MAC_LPI_ENTR_TIMR - LPI entry Timer register */ -#define ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK (0xFFFF8U) -#define ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT (3U) -#define ENET_MAC_LPI_ENTR_TIMR_LPIET(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT)) & ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK) - -/*! @name MAC_1US_TIC_COUNTR - */ -#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK (0xFFFU) -#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT (0U) -#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT)) & ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK) - -/*! @name MAC_VERSION - MAC version register */ -#define ENET_MAC_VERSION_SNPVER_MASK (0xFFU) -#define ENET_MAC_VERSION_SNPVER_SHIFT (0U) -#define ENET_MAC_VERSION_SNPVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_SNPVER_SHIFT)) & ENET_MAC_VERSION_SNPVER_MASK) -#define ENET_MAC_VERSION_USERVER_MASK (0xFF00U) -#define ENET_MAC_VERSION_USERVER_SHIFT (8U) -#define ENET_MAC_VERSION_USERVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_USERVER_SHIFT)) & ENET_MAC_VERSION_USERVER_MASK) - -/*! @name MAC_DBG - MAC debug register */ -#define ENET_MAC_DBG_REPESTS_MASK (0x1U) -#define ENET_MAC_DBG_REPESTS_SHIFT (0U) -#define ENET_MAC_DBG_REPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_REPESTS_SHIFT)) & ENET_MAC_DBG_REPESTS_MASK) -#define ENET_MAC_DBG_RFCFCSTS_MASK (0x6U) -#define ENET_MAC_DBG_RFCFCSTS_SHIFT (1U) -#define ENET_MAC_DBG_RFCFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_RFCFCSTS_SHIFT)) & ENET_MAC_DBG_RFCFCSTS_MASK) -#define ENET_MAC_DBG_TPESTS_MASK (0x10000U) -#define ENET_MAC_DBG_TPESTS_SHIFT (16U) -#define ENET_MAC_DBG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TPESTS_SHIFT)) & ENET_MAC_DBG_TPESTS_MASK) -#define ENET_MAC_DBG_TFCSTS_MASK (0x60000U) -#define ENET_MAC_DBG_TFCSTS_SHIFT (17U) -#define ENET_MAC_DBG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TFCSTS_SHIFT)) & ENET_MAC_DBG_TFCSTS_MASK) - -/*! @name MAC_HW_FEAT - MAC hardware feature register 0x0201 */ -#define ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK (0x1FU) -#define ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U) -#define ENET_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK) -#define ENET_MAC_HW_FEAT_RXQCNT_MASK (0xFU) -#define ENET_MAC_HW_FEAT_RXQCNT_SHIFT (0U) -#define ENET_MAC_HW_FEAT_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXQCNT_MASK) -#define ENET_MAC_HW_FEAT_MIISEL_MASK (0x1U) -#define ENET_MAC_HW_FEAT_MIISEL_SHIFT (0U) -#define ENET_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_MAC_HW_FEAT_MIISEL_MASK) -#define ENET_MAC_HW_FEAT_HDSEL_MASK (0x4U) -#define ENET_MAC_HW_FEAT_HDSEL_SHIFT (2U) -#define ENET_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_MAC_HW_FEAT_HDSEL_MASK) -#define ENET_MAC_HW_FEAT_VLHASH_MASK (0x10U) -#define ENET_MAC_HW_FEAT_VLHASH_SHIFT (4U) -#define ENET_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_MAC_HW_FEAT_VLHASH_MASK) -#define ENET_MAC_HW_FEAT_SMASEL_MASK (0x20U) -#define ENET_MAC_HW_FEAT_SMASEL_SHIFT (5U) -#define ENET_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_MAC_HW_FEAT_SMASEL_MASK) -#define ENET_MAC_HW_FEAT_TXQCNT_MASK (0x3C0U) -#define ENET_MAC_HW_FEAT_TXQCNT_SHIFT (6U) -#define ENET_MAC_HW_FEAT_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXQCNT_MASK) -#define ENET_MAC_HW_FEAT_RWKSEL_MASK (0x40U) -#define ENET_MAC_HW_FEAT_RWKSEL_SHIFT (6U) -#define ENET_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_MAC_HW_FEAT_RWKSEL_MASK) -#define ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK (0x7C0U) -#define ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U) -#define ENET_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK) -#define ENET_MAC_HW_FEAT_MGKSEL_MASK (0x80U) -#define ENET_MAC_HW_FEAT_MGKSEL_SHIFT (7U) -#define ENET_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_MAC_HW_FEAT_MGKSEL_MASK) -#define ENET_MAC_HW_FEAT_MMCSEL_MASK (0x100U) -#define ENET_MAC_HW_FEAT_MMCSEL_SHIFT (8U) -#define ENET_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_MAC_HW_FEAT_MMCSEL_MASK) -#define ENET_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U) -#define ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U) -#define ENET_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_MAC_HW_FEAT_ARPOFFSEL_MASK) -#define ENET_MAC_HW_FEAT_OSTEN_MASK (0x800U) -#define ENET_MAC_HW_FEAT_OSTEN_SHIFT (11U) -#define ENET_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_MAC_HW_FEAT_OSTEN_MASK) -#define ENET_MAC_HW_FEAT_RXCHCNT_MASK (0xF000U) -#define ENET_MAC_HW_FEAT_RXCHCNT_SHIFT (12U) -#define ENET_MAC_HW_FEAT_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXCHCNT_MASK) -#define ENET_MAC_HW_FEAT_TSSEL_MASK (0x1000U) -#define ENET_MAC_HW_FEAT_TSSEL_SHIFT (12U) -#define ENET_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSEL_MASK) -#define ENET_MAC_HW_FEAT_PTOEN_MASK (0x1000U) -#define ENET_MAC_HW_FEAT_PTOEN_SHIFT (12U) -#define ENET_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_MAC_HW_FEAT_PTOEN_MASK) -#define ENET_MAC_HW_FEAT_EEESEL_MASK (0x2000U) -#define ENET_MAC_HW_FEAT_EEESEL_SHIFT (13U) -#define ENET_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_MAC_HW_FEAT_EEESEL_MASK) -#define ENET_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U) -#define ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U) -#define ENET_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_MAC_HW_FEAT_ADVTHWORD_MASK) -#define ENET_MAC_HW_FEAT_ADDR64_MASK (0xC000U) -#define ENET_MAC_HW_FEAT_ADDR64_SHIFT (14U) -#define ENET_MAC_HW_FEAT_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_MAC_HW_FEAT_ADDR64_MASK) -#define ENET_MAC_HW_FEAT_TXCOESEL_MASK (0x4000U) -#define ENET_MAC_HW_FEAT_TXCOESEL_SHIFT (14U) -#define ENET_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_TXCOESEL_MASK) -#define ENET_MAC_HW_FEAT_DCBEN_MASK (0x10000U) -#define ENET_MAC_HW_FEAT_DCBEN_SHIFT (16U) -#define ENET_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_MAC_HW_FEAT_DCBEN_MASK) -#define ENET_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U) -#define ENET_MAC_HW_FEAT_RXCOESEL_SHIFT (16U) -#define ENET_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_RXCOESEL_MASK) -#define ENET_MAC_HW_FEAT_SPEN_MASK (0x20000U) -#define ENET_MAC_HW_FEAT_SPEN_SHIFT (17U) -#define ENET_MAC_HW_FEAT_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPEN_SHIFT)) & ENET_MAC_HW_FEAT_SPEN_MASK) -#define ENET_MAC_HW_FEAT_TXCHCNT_MASK (0x3C0000U) -#define ENET_MAC_HW_FEAT_TXCHCNT_SHIFT (18U) -#define ENET_MAC_HW_FEAT_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXCHCNT_MASK) -#define ENET_MAC_HW_FEAT_TSOEN_MASK (0x40000U) -#define ENET_MAC_HW_FEAT_TSOEN_SHIFT (18U) -#define ENET_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_MAC_HW_FEAT_TSOEN_MASK) -#define ENET_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U) -#define ENET_MAC_HW_FEAT_DBGMEMA_SHIFT (19U) -#define ENET_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_MAC_HW_FEAT_DBGMEMA_MASK) -#define ENET_MAC_HW_FEAT_AVSEL_MASK (0x100000U) -#define ENET_MAC_HW_FEAT_AVSEL_SHIFT (20U) -#define ENET_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_MAC_HW_FEAT_AVSEL_MASK) -#define ENET_MAC_HW_FEAT_LPMODEEN_MASK (0x800000U) -#define ENET_MAC_HW_FEAT_LPMODEEN_SHIFT (23U) -#define ENET_MAC_HW_FEAT_LPMODEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_LPMODEEN_SHIFT)) & ENET_MAC_HW_FEAT_LPMODEEN_MASK) -#define ENET_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U) -#define ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U) -#define ENET_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_MAC_HW_FEAT_PPSOUTNUM_MASK) -#define ENET_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U) -#define ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U) -#define ENET_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_MAC_HW_FEAT_HASHTBLSZ_MASK) -#define ENET_MAC_HW_FEAT_TSSTSSEL_MASK (0x6000000U) -#define ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U) -#define ENET_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSTSSEL_MASK) -#define ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK (0x78000000U) -#define ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT (27U) -#define ENET_MAC_HW_FEAT_L3_L4_FILTER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT)) & ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK) -#define ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U) -#define ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U) -#define ENET_MAC_HW_FEAT_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK) -#define ENET_MAC_HW_FEAT_ACTPHYSEL_MASK (0x70000000U) -#define ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT (28U) -#define ENET_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_MAC_HW_FEAT_ACTPHYSEL_MASK) - -/* The count of ENET_MAC_HW_FEAT */ -#define ENET_MAC_HW_FEAT_COUNT (3U) - -/*! @name MAC_MDIO_ADDR - MIDO address Register */ -#define ENET_MAC_MDIO_ADDR_MB_MASK (0x1U) -#define ENET_MAC_MDIO_ADDR_MB_SHIFT (0U) -#define ENET_MAC_MDIO_ADDR_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MB_SHIFT)) & ENET_MAC_MDIO_ADDR_MB_MASK) -#define ENET_MAC_MDIO_ADDR_MOC_MASK (0xCU) -#define ENET_MAC_MDIO_ADDR_MOC_SHIFT (2U) -#define ENET_MAC_MDIO_ADDR_MOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MOC_SHIFT)) & ENET_MAC_MDIO_ADDR_MOC_MASK) -#define ENET_MAC_MDIO_ADDR_CR_MASK (0xF00U) -#define ENET_MAC_MDIO_ADDR_CR_SHIFT (8U) -#define ENET_MAC_MDIO_ADDR_CR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_CR_SHIFT)) & ENET_MAC_MDIO_ADDR_CR_MASK) -#define ENET_MAC_MDIO_ADDR_NTC_MASK (0x7000U) -#define ENET_MAC_MDIO_ADDR_NTC_SHIFT (12U) -#define ENET_MAC_MDIO_ADDR_NTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_NTC_SHIFT)) & ENET_MAC_MDIO_ADDR_NTC_MASK) -#define ENET_MAC_MDIO_ADDR_RDA_MASK (0x1F0000U) -#define ENET_MAC_MDIO_ADDR_RDA_SHIFT (16U) -#define ENET_MAC_MDIO_ADDR_RDA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_RDA_SHIFT)) & ENET_MAC_MDIO_ADDR_RDA_MASK) -#define ENET_MAC_MDIO_ADDR_PA_MASK (0x3E00000U) -#define ENET_MAC_MDIO_ADDR_PA_SHIFT (21U) -#define ENET_MAC_MDIO_ADDR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PA_SHIFT)) & ENET_MAC_MDIO_ADDR_PA_MASK) -#define ENET_MAC_MDIO_ADDR_BTB_MASK (0x4000000U) -#define ENET_MAC_MDIO_ADDR_BTB_SHIFT (26U) -#define ENET_MAC_MDIO_ADDR_BTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_BTB_SHIFT)) & ENET_MAC_MDIO_ADDR_BTB_MASK) -#define ENET_MAC_MDIO_ADDR_PSE_MASK (0x8000000U) -#define ENET_MAC_MDIO_ADDR_PSE_SHIFT (27U) -#define ENET_MAC_MDIO_ADDR_PSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PSE_SHIFT)) & ENET_MAC_MDIO_ADDR_PSE_MASK) - -/*! @name MAC_MDIO_DATA - MDIO Data register */ -#define ENET_MAC_MDIO_DATA_MD_MASK (0xFFFFU) -#define ENET_MAC_MDIO_DATA_MD_SHIFT (0U) -#define ENET_MAC_MDIO_DATA_MD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_MD_SHIFT)) & ENET_MAC_MDIO_DATA_MD_MASK) - -/*! @name MAC_ADDR_HIGH - MAC address0 high register */ -#define ENET_MAC_ADDR_HIGH_A47_32_MASK (0xFFFFU) -#define ENET_MAC_ADDR_HIGH_A47_32_SHIFT (0U) -#define ENET_MAC_ADDR_HIGH_A47_32(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_A47_32_SHIFT)) & ENET_MAC_ADDR_HIGH_A47_32_MASK) -#define ENET_MAC_ADDR_HIGH_DCS_MASK (0x10000U) -#define ENET_MAC_ADDR_HIGH_DCS_SHIFT (16U) -#define ENET_MAC_ADDR_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_DCS_SHIFT)) & ENET_MAC_ADDR_HIGH_DCS_MASK) -#define ENET_MAC_ADDR_HIGH_AE_MASK (0x80000000U) -#define ENET_MAC_ADDR_HIGH_AE_SHIFT (31U) -#define ENET_MAC_ADDR_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_AE_SHIFT)) & ENET_MAC_ADDR_HIGH_AE_MASK) - -/*! @name MAC_ADDR_LOW - MAC address0 low register */ -#define ENET_MAC_ADDR_LOW_A31_0_MASK (0xFFFFFFFFU) -#define ENET_MAC_ADDR_LOW_A31_0_SHIFT (0U) -#define ENET_MAC_ADDR_LOW_A31_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_LOW_A31_0_SHIFT)) & ENET_MAC_ADDR_LOW_A31_0_MASK) - -/*! @name MAC_TIMESTAMP_CTRL - Time stamp control register */ -#define ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK (0x1U) -#define ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT (0U) -#define ENET_MAC_TIMESTAMP_CTRL_TSENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK) -#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK (0x2U) -#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT (1U) -#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK) -#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK (0x4U) -#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT (2U) -#define ENET_MAC_TIMESTAMP_CTRL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK) -#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK (0x8U) -#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT (3U) -#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK) -#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK (0x10U) -#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT (4U) -#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK) -#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK (0x20U) -#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT (5U) -#define ENET_MAC_TIMESTAMP_CTRL_TADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK) -#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK (0x100U) -#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT (8U) -#define ENET_MAC_TIMESTAMP_CTRL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK) -#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK (0x200U) -#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT (9U) -#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK) -#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK (0x400U) -#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT (10U) -#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK) -#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK (0x800U) -#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT (11U) -#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK) -#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK (0x1000U) -#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT (12U) -#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK) -#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK (0x2000U) -#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT (13U) -#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK) -#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK (0x4000U) -#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT (14U) -#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK) -#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK (0x8000U) -#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT (15U) -#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK) -#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK (0x30000U) -#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT (16U) -#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK) -#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK (0x40000U) -#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT (18U) -#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK) -#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK (0x1000000U) -#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT (24U) -#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK) -#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK (0x10000000U) -#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT (28U) -#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK) - -/*! @name MAC_SUB_SCND_INCR - Sub-second increment register */ -#define ENET_MAC_SUB_SCND_INCR_SSINC_MASK (0xFF0000U) -#define ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT (16U) -#define ENET_MAC_SUB_SCND_INCR_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT)) & ENET_MAC_SUB_SCND_INCR_SSINC_MASK) - -/*! @name MAC_SYS_TIME_SCND - System time seconds register */ -#define ENET_MAC_SYS_TIME_SCND_TSS_MASK (0xFFFFFFFFU) -#define ENET_MAC_SYS_TIME_SCND_TSS_SHIFT (0U) -#define ENET_MAC_SYS_TIME_SCND_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_TSS_MASK) - -/*! @name MAC_SYS_TIME_NSCND - System time nanoseconds register */ -#define ENET_MAC_SYS_TIME_NSCND_TSSS_MASK (0x7FFFFFFFU) -#define ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT (0U) -#define ENET_MAC_SYS_TIME_NSCND_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK) - -/*! @name MAC_SYS_TIME_SCND_UPD - */ -#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK (0xFFFFFFFFU) -#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT (0U) -#define ENET_MAC_SYS_TIME_SCND_UPD_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK) - -/*! @name MAC_SYS_TIME_NSCND_UPD - */ -#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK (0x7FFFFFFFU) -#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT (0U) -#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK) -#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK (0x80000000U) -#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT (31U) -#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK) - -/*! @name MAC_SYS_TIMESTMP_ADDEND - Time stamp addend register */ -#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK (0xFFFFFFFFU) -#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT (0U) -#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT)) & ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK) - -/*! @name MAC_SYS_TIME_HWORD_SCND - */ -#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK (0xFFFFU) -#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT (0U) -#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT)) & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK) - -/*! @name MAC_SYS_TIMESTMP_STAT - Time stamp status register */ -#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK (0x1U) -#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT (0U) -#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT)) & ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK) - -/*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Tx timestamp status nanoseconds */ -#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK (0x7FFFFFFFU) -#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT (0U) -#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK) -#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK (0x80000000U) -#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT (31U) -#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK) - -/*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Tx timestamp status seconds */ -#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK (0xFFFFFFFFU) -#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT (0U) -#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK) - -/*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp ingress correction */ -#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU) -#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U) -#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK) - -/*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp egress correction */ -#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU) -#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U) -#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK) - -/*! @name MTL_OP_MODE - MTL Operation Mode Register */ -#define ENET_MTL_OP_MODE_DTXSTS_MASK (0x2U) -#define ENET_MTL_OP_MODE_DTXSTS_SHIFT (1U) -#define ENET_MTL_OP_MODE_DTXSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_DTXSTS_SHIFT)) & ENET_MTL_OP_MODE_DTXSTS_MASK) -#define ENET_MTL_OP_MODE_RAA_MASK (0x4U) -#define ENET_MTL_OP_MODE_RAA_SHIFT (2U) -#define ENET_MTL_OP_MODE_RAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_RAA_SHIFT)) & ENET_MTL_OP_MODE_RAA_MASK) -#define ENET_MTL_OP_MODE_SCHALG_MASK (0x60U) -#define ENET_MTL_OP_MODE_SCHALG_SHIFT (5U) -#define ENET_MTL_OP_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_SCHALG_SHIFT)) & ENET_MTL_OP_MODE_SCHALG_MASK) -#define ENET_MTL_OP_MODE_CNTPRST_MASK (0x100U) -#define ENET_MTL_OP_MODE_CNTPRST_SHIFT (8U) -#define ENET_MTL_OP_MODE_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTPRST_SHIFT)) & ENET_MTL_OP_MODE_CNTPRST_MASK) -#define ENET_MTL_OP_MODE_CNTCLR_MASK (0x200U) -#define ENET_MTL_OP_MODE_CNTCLR_SHIFT (9U) -#define ENET_MTL_OP_MODE_CNTCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTCLR_SHIFT)) & ENET_MTL_OP_MODE_CNTCLR_MASK) - -/*! @name MTL_INTR_STAT - MTL Interrupt Status register */ -#define ENET_MTL_INTR_STAT_Q0IS_MASK (0x1U) -#define ENET_MTL_INTR_STAT_Q0IS_SHIFT (0U) -#define ENET_MTL_INTR_STAT_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q0IS_SHIFT)) & ENET_MTL_INTR_STAT_Q0IS_MASK) -#define ENET_MTL_INTR_STAT_Q1IS_MASK (0x2U) -#define ENET_MTL_INTR_STAT_Q1IS_SHIFT (1U) -#define ENET_MTL_INTR_STAT_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q1IS_SHIFT)) & ENET_MTL_INTR_STAT_Q1IS_MASK) - -/*! @name MTL_RXQ_DMA_MAP - MTL Receive Queue and DMA Channel Mapping register */ -#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK (0x1U) -#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT (0U) -#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK) -#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK (0x10U) -#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT (4U) -#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK) -#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK (0x100U) -#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT (8U) -#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK) -#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK (0x1000U) -#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT (12U) -#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK) - -/*! @name MTL_QUEUE_MTL_TXQX_OP_MODE - MTL TxQx Operation Mode register */ -#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U) -#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U) -#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK) -#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK (0x2U) -#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT (1U) -#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK) -#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU) -#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U) -#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK) -#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK (0x70U) -#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT (4U) -#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK) -#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK (0x70000U) -#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT (16U) -#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK) - -/* The count of ENET_MTL_QUEUE_MTL_TXQX_OP_MODE */ -#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_COUNT (2U) - -/*! @name MTL_QUEUE_MTL_TXQX_UNDRFLW - MTL TxQx Underflow register */ -#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU) -#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U) -#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK) -#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U) -#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U) -#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK) - -/* The count of ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW */ -#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_COUNT (2U) - -/*! @name MTL_QUEUE_MTL_TXQX_DBG - MTL TxQx Debug register */ -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U) -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U) -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK) -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK (0x6U) -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT (1U) -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK) -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK (0x8U) -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT (3U) -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK) -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK (0x10U) -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT (4U) -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK) -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U) -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U) -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK) -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK (0x70000U) -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT (16U) -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK) -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK (0x700000U) -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT (20U) -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK) - -/* The count of ENET_MTL_QUEUE_MTL_TXQX_DBG */ -#define ENET_MTL_QUEUE_MTL_TXQX_DBG_COUNT (2U) - -/*! @name MTL_QUEUE_MTL_TXQX_ETS_CTRL - MTL TxQx ETS control register, only TxQ1 support */ -#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U) -#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U) -#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK) -#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U) -#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U) -#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK) -#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U) -#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U) -#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK) - -/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL */ -#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_COUNT (2U) - -/*! @name MTL_QUEUE_MTL_TXQX_ETS_STAT - MTL TxQx ETS Status register */ -#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU) -#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U) -#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK) - -/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT */ -#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_COUNT (2U) - -/*! @name MTL_QUEUE_MTL_TXQX_QNTM_WGHT - */ -#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU) -#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U) -#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK) - -/* The count of ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT */ -#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_COUNT (2U) - -/*! @name MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT - MTL TxQx SendSlopCredit register, only TxQ1 support */ -#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU) -#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U) -#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK) - -/* The count of ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT */ -#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_COUNT (2U) - -/*! @name MTL_QUEUE_MTL_TXQX_HI_CRDT - MTL TxQx hiCredit register, only TxQ1 support */ -#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK (0x1FFFFFFFU) -#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT (0U) -#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK) - -/* The count of ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT */ -#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_COUNT (2U) - -/*! @name MTL_QUEUE_MTL_TXQX_LO_CRDT - MTL TxQx loCredit register, only TxQ1 support */ -#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK (0x1FFFFFFFU) -#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT (0U) -#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK) - -/* The count of ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT */ -#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_COUNT (2U) - -/*! @name MTL_QUEUE_MTL_TXQX_INTCTRL_STAT - */ -#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U) -#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U) -#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK) -#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U) -#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U) -#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK) -#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U) -#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U) -#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK) -#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U) -#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U) -#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK) -#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U) -#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U) -#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK) -#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U) -#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U) -#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK) - -/* The count of ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT */ -#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_COUNT (2U) - -/*! @name MTL_QUEUE_MTL_RXQX_OP_MODE - MTL RxQx Operation Mode register */ -#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK (0x3U) -#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT (0U) -#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK) -#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK (0x8U) -#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT (3U) -#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK) -#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK (0x10U) -#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT (4U) -#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK) -#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK (0x20U) -#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT (5U) -#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK) -#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U) -#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U) -#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK) -#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK (0x700000U) -#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT (20U) -#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK) - -/* The count of ENET_MTL_QUEUE_MTL_RXQX_OP_MODE */ -#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_COUNT (2U) - -/*! @name MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT - MTL RxQx Missed Packet Overflow Counter register */ -#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU) -#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U) -#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK) -#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U) -#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U) -#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK) - -/* The count of ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT */ -#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (2U) - -/*! @name MTL_QUEUE_MTL_RXQX_DBG - MTL RxQx Debug register */ -#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK (0x1U) -#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT (0U) -#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK) -#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK (0x6U) -#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT (1U) -#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK) -#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK (0x30U) -#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT (4U) -#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK) -#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK (0x3FFF0000U) -#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT (16U) -#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK) - -/* The count of ENET_MTL_QUEUE_MTL_RXQX_DBG */ -#define ENET_MTL_QUEUE_MTL_RXQX_DBG_COUNT (2U) - -/*! @name MTL_QUEUE_MTL_RXQX_CTRL - MTL RxQx Control register */ -#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U) -#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U) -#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK) -#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U) -#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U) -#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK) - -/* The count of ENET_MTL_QUEUE_MTL_RXQX_CTRL */ -#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_COUNT (2U) - -/*! @name DMA_MODE - DMA mode register */ -#define ENET_DMA_MODE_SWR_MASK (0x1U) -#define ENET_DMA_MODE_SWR_SHIFT (0U) -#define ENET_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_SWR_SHIFT)) & ENET_DMA_MODE_SWR_MASK) -#define ENET_DMA_MODE_DA_MASK (0x2U) -#define ENET_DMA_MODE_DA_SHIFT (1U) -#define ENET_DMA_MODE_DA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_DA_SHIFT)) & ENET_DMA_MODE_DA_MASK) -#define ENET_DMA_MODE_TAA_MASK (0x1CU) -#define ENET_DMA_MODE_TAA_SHIFT (2U) -#define ENET_DMA_MODE_TAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TAA_SHIFT)) & ENET_DMA_MODE_TAA_MASK) -#define ENET_DMA_MODE_TXPR_MASK (0x800U) -#define ENET_DMA_MODE_TXPR_SHIFT (11U) -#define ENET_DMA_MODE_TXPR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TXPR_SHIFT)) & ENET_DMA_MODE_TXPR_MASK) -#define ENET_DMA_MODE_PR_MASK (0x7000U) -#define ENET_DMA_MODE_PR_SHIFT (12U) -#define ENET_DMA_MODE_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_PR_SHIFT)) & ENET_DMA_MODE_PR_MASK) - -/*! @name DMA_SYSBUS_MODE - DMA System Bus mode */ -#define ENET_DMA_SYSBUS_MODE_FB_MASK (0x1U) -#define ENET_DMA_SYSBUS_MODE_FB_SHIFT (0U) -#define ENET_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_DMA_SYSBUS_MODE_FB_MASK) -#define ENET_DMA_SYSBUS_MODE_AAL_MASK (0x1000U) -#define ENET_DMA_SYSBUS_MODE_AAL_SHIFT (12U) -#define ENET_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_DMA_SYSBUS_MODE_AAL_MASK) -#define ENET_DMA_SYSBUS_MODE_MB_MASK (0x4000U) -#define ENET_DMA_SYSBUS_MODE_MB_SHIFT (14U) -#define ENET_DMA_SYSBUS_MODE_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_MB_SHIFT)) & ENET_DMA_SYSBUS_MODE_MB_MASK) -#define ENET_DMA_SYSBUS_MODE_RB_MASK (0x8000U) -#define ENET_DMA_SYSBUS_MODE_RB_SHIFT (15U) -#define ENET_DMA_SYSBUS_MODE_RB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_RB_SHIFT)) & ENET_DMA_SYSBUS_MODE_RB_MASK) - -/*! @name DMA_INTR_STAT - DMA Interrupt status */ -#define ENET_DMA_INTR_STAT_DC0IS_MASK (0x1U) -#define ENET_DMA_INTR_STAT_DC0IS_SHIFT (0U) -#define ENET_DMA_INTR_STAT_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC0IS_SHIFT)) & ENET_DMA_INTR_STAT_DC0IS_MASK) -#define ENET_DMA_INTR_STAT_DC1IS_MASK (0x2U) -#define ENET_DMA_INTR_STAT_DC1IS_SHIFT (1U) -#define ENET_DMA_INTR_STAT_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC1IS_SHIFT)) & ENET_DMA_INTR_STAT_DC1IS_MASK) -#define ENET_DMA_INTR_STAT_MTLIS_MASK (0x10000U) -#define ENET_DMA_INTR_STAT_MTLIS_SHIFT (16U) -#define ENET_DMA_INTR_STAT_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MTLIS_SHIFT)) & ENET_DMA_INTR_STAT_MTLIS_MASK) -#define ENET_DMA_INTR_STAT_MACIS_MASK (0x20000U) -#define ENET_DMA_INTR_STAT_MACIS_SHIFT (17U) -#define ENET_DMA_INTR_STAT_MACIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MACIS_SHIFT)) & ENET_DMA_INTR_STAT_MACIS_MASK) - -/*! @name DMA_DBG_STAT - DMA Debug Status */ -#define ENET_DMA_DBG_STAT_AHSTS_MASK (0x1U) -#define ENET_DMA_DBG_STAT_AHSTS_SHIFT (0U) -#define ENET_DMA_DBG_STAT_AHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_AHSTS_SHIFT)) & ENET_DMA_DBG_STAT_AHSTS_MASK) -#define ENET_DMA_DBG_STAT_RPS0_MASK (0xF00U) -#define ENET_DMA_DBG_STAT_RPS0_SHIFT (8U) -#define ENET_DMA_DBG_STAT_RPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS0_SHIFT)) & ENET_DMA_DBG_STAT_RPS0_MASK) -#define ENET_DMA_DBG_STAT_TPS0_MASK (0xF000U) -#define ENET_DMA_DBG_STAT_TPS0_SHIFT (12U) -#define ENET_DMA_DBG_STAT_TPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS0_SHIFT)) & ENET_DMA_DBG_STAT_TPS0_MASK) -#define ENET_DMA_DBG_STAT_RPS1_MASK (0xF0000U) -#define ENET_DMA_DBG_STAT_RPS1_SHIFT (16U) -#define ENET_DMA_DBG_STAT_RPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS1_SHIFT)) & ENET_DMA_DBG_STAT_RPS1_MASK) -#define ENET_DMA_DBG_STAT_TPS1_MASK (0xF00000U) -#define ENET_DMA_DBG_STAT_TPS1_SHIFT (20U) -#define ENET_DMA_DBG_STAT_TPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS1_SHIFT)) & ENET_DMA_DBG_STAT_TPS1_MASK) - -/*! @name DMA_CH_DMA_CHX_CTRL - DMA Channelx Control */ -#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK (0x10000U) -#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT (16U) -#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK) -#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK (0x1C0000U) -#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT (18U) -#define ENET_DMA_CH_DMA_CHX_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK) - -/* The count of ENET_DMA_CH_DMA_CHX_CTRL */ -#define ENET_DMA_CH_DMA_CHX_CTRL_COUNT (2U) - -/*! @name DMA_CH_DMA_CHX_TX_CTRL - DMA Channelx Transmit Control */ -#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK (0x1U) -#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT (0U) -#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK) -#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK (0xEU) -#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT (1U) -#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK) -#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK (0x10U) -#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT (4U) -#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK) -#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK (0x3F0000U) -#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT (16U) -#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK) - -/* The count of ENET_DMA_CH_DMA_CHX_TX_CTRL */ -#define ENET_DMA_CH_DMA_CHX_TX_CTRL_COUNT (2U) - -/*! @name DMA_CH_DMA_CHX_RX_CTRL - DMA Channelx Receive Control */ -#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK (0x1U) -#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT (0U) -#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK) -#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK (0x7FF8U) -#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT (3U) -#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK) -#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK (0x3F0000U) -#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT (16U) -#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK) -#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK (0x80000000U) -#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT (31U) -#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK) - -/* The count of ENET_DMA_CH_DMA_CHX_RX_CTRL */ -#define ENET_DMA_CH_DMA_CHX_RX_CTRL_COUNT (2U) - -/*! @name DMA_CH_DMA_CHX_TXDESC_LIST_ADDR - */ -#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK (0xFFFFFFFCU) -#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT (2U) -#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK) - -/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR */ -#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_COUNT (2U) - -/*! @name DMA_CH_DMA_CHX_RXDESC_LIST_ADDR - */ -#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK (0xFFFFFFFCU) -#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT (2U) -#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK) - -/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR */ -#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_COUNT (2U) - -/*! @name DMA_CH_DMA_CHX_TXDESC_TAIL_PTR - */ -#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFFCU) -#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (2U) -#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK) - -/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR */ -#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_COUNT (2U) - -/*! @name DMA_CH_DMA_CHX_RXDESC_TAIL_PTR - */ -#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFFCU) -#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (2U) -#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK) - -/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR */ -#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_COUNT (2U) - -/*! @name DMA_CH_DMA_CHX_TXDESC_RING_LENGTH - */ -#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU) -#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U) -#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK) - -/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH */ -#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_COUNT (2U) - -/*! @name DMA_CH_DMA_CHX_RXDESC_RING_LENGTH - Channelx Rx descriptor Ring Length */ -#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU) -#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U) -#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK) - -/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH */ -#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_COUNT (2U) - -/*! @name DMA_CH_DMA_CHX_INT_EN - Channelx Interrupt Enable */ -#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK (0x1U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT (0U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK) -#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK (0x2U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT (1U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK) -#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK (0x4U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT (2U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK) -#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK (0x40U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT (6U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK) -#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK (0x80U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT (7U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK) -#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK (0x100U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT (8U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK) -#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK (0x200U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT (9U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK) -#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK (0x400U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT (10U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK) -#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK (0x800U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT (11U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK) -#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK (0x1000U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT (12U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK) -#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK (0x4000U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT (14U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK) -#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK (0x8000U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT (15U) -#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK) - -/* The count of ENET_DMA_CH_DMA_CHX_INT_EN */ -#define ENET_DMA_CH_DMA_CHX_INT_EN_COUNT (2U) - -/*! @name DMA_CH_DMA_CHX_RX_INT_WDTIMER - Receive Interrupt Watchdog Timer */ -#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK (0xFFU) -#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT (0U) -#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK) - -/* The count of ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER */ -#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_COUNT (2U) - -/*! @name DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT - Slot Function Control and Status */ -#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U) -#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U) -#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK) -#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U) -#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U) -#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK) -#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U) -#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U) -#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK) - -/* The count of ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT */ -#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (2U) - -/*! @name DMA_CH_DMA_CHX_CUR_HST_TXDESC - Channelx Current Host Transmit descriptor */ -#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK (0xFFFFFFFFU) -#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT (0U) -#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK) - -/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC */ -#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_COUNT (2U) - -/*! @name DMA_CH_DMA_CHX_CUR_HST_RXDESC - */ -#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK (0xFFFFFFFFU) -#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT (0U) -#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK) - -/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC */ -#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_COUNT (2U) - -/*! @name DMA_CH_DMA_CHX_CUR_HST_TXBUF - */ -#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK (0xFFFFFFFFU) -#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT (0U) -#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK) - -/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF */ -#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_COUNT (2U) - -/*! @name DMA_CH_DMA_CHX_CUR_HST_RXBUF - Channelx Current Application Receive Buffer Address */ -#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK (0xFFFFFFFFU) -#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT (0U) -#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK) - -/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF */ -#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_COUNT (2U) - -/*! @name DMA_CH_DMA_CHX_STAT - Channelx DMA status register */ -#define ENET_DMA_CH_DMA_CHX_STAT_TI_MASK (0x1U) -#define ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT (0U) -#define ENET_DMA_CH_DMA_CHX_STAT_TI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK) -#define ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK (0x2U) -#define ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT (1U) -#define ENET_DMA_CH_DMA_CHX_STAT_TPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK) -#define ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK (0x4U) -#define ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT (2U) -#define ENET_DMA_CH_DMA_CHX_STAT_TBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK) -#define ENET_DMA_CH_DMA_CHX_STAT_RI_MASK (0x40U) -#define ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT (6U) -#define ENET_DMA_CH_DMA_CHX_STAT_RI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK) -#define ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK (0x80U) -#define ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT (7U) -#define ENET_DMA_CH_DMA_CHX_STAT_RBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK) -#define ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK (0x100U) -#define ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT (8U) -#define ENET_DMA_CH_DMA_CHX_STAT_RPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK) -#define ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK (0x200U) -#define ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT (9U) -#define ENET_DMA_CH_DMA_CHX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK) -#define ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK (0x400U) -#define ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT (10U) -#define ENET_DMA_CH_DMA_CHX_STAT_ETI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK) -#define ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK (0x800U) -#define ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT (11U) -#define ENET_DMA_CH_DMA_CHX_STAT_ERI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK) -#define ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK (0x1000U) -#define ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT (12U) -#define ENET_DMA_CH_DMA_CHX_STAT_FBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK) -#define ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK (0x4000U) -#define ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT (14U) -#define ENET_DMA_CH_DMA_CHX_STAT_AIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK) -#define ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK (0x8000U) -#define ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT (15U) -#define ENET_DMA_CH_DMA_CHX_STAT_NIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK) -#define ENET_DMA_CH_DMA_CHX_STAT_EB_MASK (0x70000U) -#define ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT (16U) -#define ENET_DMA_CH_DMA_CHX_STAT_EB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_EB_MASK) - -/* The count of ENET_DMA_CH_DMA_CHX_STAT */ -#define ENET_DMA_CH_DMA_CHX_STAT_COUNT (2U) - - -/*! - * @} - */ /* end of group ENET_Register_Masks */ - - -/* ENET - Peripheral instance base addresses */ -/** Peripheral ENET base address */ -#define ENET_BASE (0x40092000u) -/** Peripheral ENET base pointer */ -#define ENET ((ENET_Type *)ENET_BASE) -/** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET_BASE } -/** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET } -/** Interrupt vectors for the ENET peripheral type */ -#define ENET_IRQS { ETHERNET_IRQn } -#define ENET_PMT_IRQS { ETHERNET_PMT_IRQn } -#define ENET_MACLP_IRQS { ETHERNET_MACLP_IRQn } - -/*! - * @} - */ /* end of group ENET_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer - * @{ - */ - -/** FLEXCOMM - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4088]; - __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ - __IO uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ -} FLEXCOMM_Type; - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks - * @{ - */ - -/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ -#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) -#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) -#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) -#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) -#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) -#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) -#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) -#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) -#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) -#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) -#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) -#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) -#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) -#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) -#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) -#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) -#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) -#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) -#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) -#define FLEXCOMM_PSELID_ID_SHIFT (12U) -#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) - -/*! @name PID - Peripheral identification register. */ -#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) -#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) -#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) -#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U) -#define FLEXCOMM_PID_Major_Rev_SHIFT (12U) -#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK) -#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) -#define FLEXCOMM_PID_ID_SHIFT (16U) -#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) - - -/*! - * @} - */ /* end of group FLEXCOMM_Register_Masks */ - - -/* FLEXCOMM - Peripheral instance base addresses */ -/** Peripheral FLEXCOMM0 base address */ -#define FLEXCOMM0_BASE (0x40086000u) -/** Peripheral FLEXCOMM0 base pointer */ -#define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) -/** Peripheral FLEXCOMM1 base address */ -#define FLEXCOMM1_BASE (0x40087000u) -/** Peripheral FLEXCOMM1 base pointer */ -#define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) -/** Peripheral FLEXCOMM2 base address */ -#define FLEXCOMM2_BASE (0x40088000u) -/** Peripheral FLEXCOMM2 base pointer */ -#define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) -/** Peripheral FLEXCOMM3 base address */ -#define FLEXCOMM3_BASE (0x40089000u) -/** Peripheral FLEXCOMM3 base pointer */ -#define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) -/** Peripheral FLEXCOMM4 base address */ -#define FLEXCOMM4_BASE (0x4008A000u) -/** Peripheral FLEXCOMM4 base pointer */ -#define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) -/** Peripheral FLEXCOMM5 base address */ -#define FLEXCOMM5_BASE (0x40096000u) -/** Peripheral FLEXCOMM5 base pointer */ -#define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) -/** Peripheral FLEXCOMM6 base address */ -#define FLEXCOMM6_BASE (0x40097000u) -/** Peripheral FLEXCOMM6 base pointer */ -#define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) -/** Peripheral FLEXCOMM7 base address */ -#define FLEXCOMM7_BASE (0x40098000u) -/** Peripheral FLEXCOMM7 base pointer */ -#define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) -/** Peripheral FLEXCOMM8 base address */ -#define FLEXCOMM8_BASE (0x40099000u) -/** Peripheral FLEXCOMM8 base pointer */ -#define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) -/** Peripheral FLEXCOMM9 base address */ -#define FLEXCOMM9_BASE (0x4009A000u) -/** Peripheral FLEXCOMM9 base pointer */ -#define FLEXCOMM9 ((FLEXCOMM_Type *)FLEXCOMM9_BASE) -/** Array initializer of FLEXCOMM peripheral base addresses */ -#define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE, FLEXCOMM9_BASE } -/** Array initializer of FLEXCOMM peripheral base pointers */ -#define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9 } -/** Interrupt vectors for the FLEXCOMM peripheral type */ -#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn } - -/*! - * @} - */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer - * @{ - */ - -/** FMC - Register Layout Typedef */ -typedef struct { - __IO uint32_t FCTR; /**< Control register, offset: 0x0 */ - uint8_t RESERVED_0[12]; - __IO uint32_t FBWST; /**< Wait state register, offset: 0x10 */ - uint8_t RESERVED_1[12]; - __IO uint32_t FMSSTART; /**< Signature start address register, offset: 0x20 */ - __IO uint32_t FMSSTOP; /**< Signature stop-address register, offset: 0x24 */ - uint8_t RESERVED_2[4]; - __I uint32_t FMSW[4]; /**< Words of 128-bit signature word, array offset: 0x2C, array step: 0x4 */ - uint8_t RESERVED_3[4004]; - __I uint32_t FMSTAT; /**< Signature generation status register, offset: 0xFE0 */ - uint8_t RESERVED_4[4]; - __O uint32_t FMSTATCLR; /**< Signature generation status clear register, offset: 0xFE8 */ -} FMC_Type; - -/* ---------------------------------------------------------------------------- - -- FMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FMC_Register_Masks FMC Register Masks - * @{ - */ - -/*! @name FCTR - Control register */ -#define FMC_FCTR_FS_RD0_MASK (0x8U) -#define FMC_FCTR_FS_RD0_SHIFT (3U) -#define FMC_FCTR_FS_RD0(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD0_SHIFT)) & FMC_FCTR_FS_RD0_MASK) -#define FMC_FCTR_FS_RD1_MASK (0x10U) -#define FMC_FCTR_FS_RD1_SHIFT (4U) -#define FMC_FCTR_FS_RD1(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD1_SHIFT)) & FMC_FCTR_FS_RD1_MASK) - -/*! @name FBWST - Wait state register */ -#define FMC_FBWST_WAITSTATES_MASK (0xFFU) -#define FMC_FBWST_WAITSTATES_SHIFT (0U) -#define FMC_FBWST_WAITSTATES(x) (((uint32_t)(((uint32_t)(x)) << FMC_FBWST_WAITSTATES_SHIFT)) & FMC_FBWST_WAITSTATES_MASK) - -/*! @name FMSSTART - Signature start address register */ -#define FMC_FMSSTART_START_MASK (0x1FFFFU) -#define FMC_FMSSTART_START_SHIFT (0U) -#define FMC_FMSSTART_START(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTART_START_SHIFT)) & FMC_FMSSTART_START_MASK) - -/*! @name FMSSTOP - Signature stop-address register */ -#define FMC_FMSSTOP_STOP_MASK (0x1FFFFU) -#define FMC_FMSSTOP_STOP_SHIFT (0U) -#define FMC_FMSSTOP_STOP(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_STOP_SHIFT)) & FMC_FMSSTOP_STOP_MASK) -#define FMC_FMSSTOP_SIG_START_MASK (0x20000U) -#define FMC_FMSSTOP_SIG_START_SHIFT (17U) -#define FMC_FMSSTOP_SIG_START(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_SIG_START_SHIFT)) & FMC_FMSSTOP_SIG_START_MASK) - -/*! @name FMSW - Words of 128-bit signature word */ -#define FMC_FMSW_SW_MASK (0xFFFFFFFFU) -#define FMC_FMSW_SW_SHIFT (0U) -#define FMC_FMSW_SW(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSW_SW_SHIFT)) & FMC_FMSW_SW_MASK) - -/* The count of FMC_FMSW */ -#define FMC_FMSW_COUNT (4U) - -/*! @name FMSTAT - Signature generation status register */ -#define FMC_FMSTAT_SIG_DONE_MASK (0x4U) -#define FMC_FMSTAT_SIG_DONE_SHIFT (2U) -#define FMC_FMSTAT_SIG_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSTAT_SIG_DONE_SHIFT)) & FMC_FMSTAT_SIG_DONE_MASK) - -/*! @name FMSTATCLR - Signature generation status clear register */ -#define FMC_FMSTATCLR_SIG_DONE_CLR_MASK (0x4U) -#define FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT (2U) -#define FMC_FMSTATCLR_SIG_DONE_CLR(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT)) & FMC_FMSTATCLR_SIG_DONE_CLR_MASK) - - -/*! - * @} - */ /* end of group FMC_Register_Masks */ - - -/* FMC - Peripheral instance base addresses */ -/** Peripheral FMC base address */ -#define FMC_BASE (0x40034000u) -/** Peripheral FMC base pointer */ -#define FMC ((FMC_Type *)FMC_BASE) -/** Array initializer of FMC peripheral base addresses */ -#define FMC_BASE_ADDRS { FMC_BASE } -/** Array initializer of FMC peripheral base pointers */ -#define FMC_BASE_PTRS { FMC } - -/*! - * @} - */ /* end of group FMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer - * @{ - */ - -/** GINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ - uint8_t RESERVED_0[28]; - __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[24]; - __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ -} GINT_Type; - -/* ---------------------------------------------------------------------------- - -- GINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Register_Masks GINT Register Masks - * @{ - */ - -/*! @name CTRL - GPIO grouped interrupt control register */ -#define GINT_CTRL_INT_MASK (0x1U) -#define GINT_CTRL_INT_SHIFT (0U) -#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) -#define GINT_CTRL_COMB_MASK (0x2U) -#define GINT_CTRL_COMB_SHIFT (1U) -#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) -#define GINT_CTRL_TRIG_MASK (0x4U) -#define GINT_CTRL_TRIG_SHIFT (2U) -#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) - -/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ -#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) -#define GINT_PORT_POL_POL_SHIFT (0U) -#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) - -/* The count of GINT_PORT_POL */ -#define GINT_PORT_POL_COUNT (2U) - -/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ -#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) -#define GINT_PORT_ENA_ENA_SHIFT (0U) -#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) - -/* The count of GINT_PORT_ENA */ -#define GINT_PORT_ENA_COUNT (2U) - - -/*! - * @} - */ /* end of group GINT_Register_Masks */ - - -/* GINT - Peripheral instance base addresses */ -/** Peripheral GINT0 base address */ -#define GINT0_BASE (0x40002000u) -/** Peripheral GINT0 base pointer */ -#define GINT0 ((GINT_Type *)GINT0_BASE) -/** Peripheral GINT1 base address */ -#define GINT1_BASE (0x40003000u) -/** Peripheral GINT1 base pointer */ -#define GINT1 ((GINT_Type *)GINT1_BASE) -/** Array initializer of GINT peripheral base addresses */ -#define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } -/** Array initializer of GINT peripheral base pointers */ -#define GINT_BASE_PTRS { GINT0, GINT1 } -/** Interrupt vectors for the GINT peripheral type */ -#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } - -/*! - * @} - */ /* end of group GINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer - * @{ - */ - -/** GPIO - Register Layout Typedef */ -typedef struct { - __IO uint8_t B[6][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ - uint8_t RESERVED_0[3904]; - __IO uint32_t W[6][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ - uint8_t RESERVED_1[3328]; - __IO uint32_t DIR[6]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */ - uint8_t RESERVED_2[104]; - __IO uint32_t MASK[6]; /**< Mask register, array offset: 0x2080, array step: 0x4 */ - uint8_t RESERVED_3[104]; - __IO uint32_t PIN[6]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */ - uint8_t RESERVED_4[104]; - __IO uint32_t MPIN[6]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */ - uint8_t RESERVED_5[104]; - __IO uint32_t SET[6]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */ - uint8_t RESERVED_6[104]; - __O uint32_t CLR[6]; /**< Clear port, array offset: 0x2280, array step: 0x4 */ - uint8_t RESERVED_7[104]; - __O uint32_t NOT[6]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */ - uint8_t RESERVED_8[104]; - __O uint32_t DIRSET[6]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ - uint8_t RESERVED_9[104]; - __O uint32_t DIRCLR[6]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ - uint8_t RESERVED_10[104]; - __O uint32_t DIRNOT[6]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ -} GPIO_Type; - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */ -#define GPIO_B_PBYTE_MASK (0x1U) -#define GPIO_B_PBYTE_SHIFT (0U) -#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) - -/* The count of GPIO_B */ -#define GPIO_B_COUNT (6U) - -/* The count of GPIO_B */ -#define GPIO_B_COUNT2 (32U) - -/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */ -#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) -#define GPIO_W_PWORD_SHIFT (0U) -#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) - -/* The count of GPIO_W */ -#define GPIO_W_COUNT (6U) - -/* The count of GPIO_W */ -#define GPIO_W_COUNT2 (32U) - -/*! @name DIR - Direction registers */ -#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) -#define GPIO_DIR_DIRP_SHIFT (0U) -#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) - -/* The count of GPIO_DIR */ -#define GPIO_DIR_COUNT (6U) - -/*! @name MASK - Mask register */ -#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) -#define GPIO_MASK_MASKP_SHIFT (0U) -#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) - -/* The count of GPIO_MASK */ -#define GPIO_MASK_COUNT (6U) - -/*! @name PIN - Port pin register */ -#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) -#define GPIO_PIN_PORT_SHIFT (0U) -#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) - -/* The count of GPIO_PIN */ -#define GPIO_PIN_COUNT (6U) - -/*! @name MPIN - Masked port register */ -#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) -#define GPIO_MPIN_MPORTP_SHIFT (0U) -#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) - -/* The count of GPIO_MPIN */ -#define GPIO_MPIN_COUNT (6U) - -/*! @name SET - Write: Set register for port Read: output bits for port */ -#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) -#define GPIO_SET_SETP_SHIFT (0U) -#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) - -/* The count of GPIO_SET */ -#define GPIO_SET_COUNT (6U) - -/*! @name CLR - Clear port */ -#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) -#define GPIO_CLR_CLRP_SHIFT (0U) -#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) - -/* The count of GPIO_CLR */ -#define GPIO_CLR_COUNT (6U) - -/*! @name NOT - Toggle port */ -#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) -#define GPIO_NOT_NOTP_SHIFT (0U) -#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) - -/* The count of GPIO_NOT */ -#define GPIO_NOT_COUNT (6U) - -/*! @name DIRSET - Set pin direction bits for port */ -#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU) -#define GPIO_DIRSET_DIRSETP_SHIFT (0U) -#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) - -/* The count of GPIO_DIRSET */ -#define GPIO_DIRSET_COUNT (6U) - -/*! @name DIRCLR - Clear pin direction bits for port */ -#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU) -#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) -#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) - -/* The count of GPIO_DIRCLR */ -#define GPIO_DIRCLR_COUNT (6U) - -/*! @name DIRNOT - Toggle pin direction bits for port */ -#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU) -#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) -#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) - -/* The count of GPIO_DIRNOT */ -#define GPIO_DIRNOT_COUNT (6U) - - -/*! - * @} - */ /* end of group GPIO_Register_Masks */ - - -/* GPIO - Peripheral instance base addresses */ -/** Peripheral GPIO base address */ -#define GPIO_BASE (0x4008C000u) -/** Peripheral GPIO base pointer */ -#define GPIO ((GPIO_Type *)GPIO_BASE) -/** Array initializer of GPIO peripheral base addresses */ -#define GPIO_BASE_ADDRS { GPIO_BASE } -/** Array initializer of GPIO peripheral base pointers */ -#define GPIO_BASE_PTRS { GPIO } - -/*! - * @} - */ /* end of group GPIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2C Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer - * @{ - */ - -/** I2C - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[2048]; - __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ - __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ - __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ - __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ - __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ - __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ - uint8_t RESERVED_1[4]; - __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ - __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ - __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ - uint8_t RESERVED_2[20]; - __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ - __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ - __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ - __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ - uint8_t RESERVED_3[36]; - __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ - uint8_t RESERVED_4[1912]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} I2C_Type; - -/* ---------------------------------------------------------------------------- - -- I2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Register_Masks I2C Register Masks - * @{ - */ - -/*! @name CFG - Configuration for shared functions. */ -#define I2C_CFG_MSTEN_MASK (0x1U) -#define I2C_CFG_MSTEN_SHIFT (0U) -#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) -#define I2C_CFG_SLVEN_MASK (0x2U) -#define I2C_CFG_SLVEN_SHIFT (1U) -#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) -#define I2C_CFG_MONEN_MASK (0x4U) -#define I2C_CFG_MONEN_SHIFT (2U) -#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) -#define I2C_CFG_TIMEOUTEN_MASK (0x8U) -#define I2C_CFG_TIMEOUTEN_SHIFT (3U) -#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) -#define I2C_CFG_MONCLKSTR_MASK (0x10U) -#define I2C_CFG_MONCLKSTR_SHIFT (4U) -#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) -#define I2C_CFG_HSCAPABLE_MASK (0x20U) -#define I2C_CFG_HSCAPABLE_SHIFT (5U) -#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) - -/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ -#define I2C_STAT_MSTPENDING_MASK (0x1U) -#define I2C_STAT_MSTPENDING_SHIFT (0U) -#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) -#define I2C_STAT_MSTSTATE_MASK (0xEU) -#define I2C_STAT_MSTSTATE_SHIFT (1U) -#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) -#define I2C_STAT_MSTARBLOSS_MASK (0x10U) -#define I2C_STAT_MSTARBLOSS_SHIFT (4U) -#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) -#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) -#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) -#define I2C_STAT_SLVPENDING_MASK (0x100U) -#define I2C_STAT_SLVPENDING_SHIFT (8U) -#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) -#define I2C_STAT_SLVSTATE_MASK (0x600U) -#define I2C_STAT_SLVSTATE_SHIFT (9U) -#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) -#define I2C_STAT_SLVNOTSTR_MASK (0x800U) -#define I2C_STAT_SLVNOTSTR_SHIFT (11U) -#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) -#define I2C_STAT_SLVIDX_MASK (0x3000U) -#define I2C_STAT_SLVIDX_SHIFT (12U) -#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) -#define I2C_STAT_SLVSEL_MASK (0x4000U) -#define I2C_STAT_SLVSEL_SHIFT (14U) -#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) -#define I2C_STAT_SLVDESEL_MASK (0x8000U) -#define I2C_STAT_SLVDESEL_SHIFT (15U) -#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) -#define I2C_STAT_MONRDY_MASK (0x10000U) -#define I2C_STAT_MONRDY_SHIFT (16U) -#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) -#define I2C_STAT_MONOV_MASK (0x20000U) -#define I2C_STAT_MONOV_SHIFT (17U) -#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) -#define I2C_STAT_MONACTIVE_MASK (0x40000U) -#define I2C_STAT_MONACTIVE_SHIFT (18U) -#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) -#define I2C_STAT_MONIDLE_MASK (0x80000U) -#define I2C_STAT_MONIDLE_SHIFT (19U) -#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) -#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) -#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) -#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) -#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) - -/*! @name INTENSET - Interrupt Enable Set and read register. */ -#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) -#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) -#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) -#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) -#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) -#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) -#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) -#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) -#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) -#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) -#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) -#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) -#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) -#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) -#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) -#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) -#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) -#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) -#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) -#define I2C_INTENSET_MONRDYEN_SHIFT (16U) -#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) -#define I2C_INTENSET_MONOVEN_MASK (0x20000U) -#define I2C_INTENSET_MONOVEN_SHIFT (17U) -#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) -#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) -#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) -#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) -#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) -#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) -#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) -#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) -#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) -#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) - -/*! @name INTENCLR - Interrupt Enable Clear register. */ -#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) -#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) -#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) -#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) -#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) -#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) -#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) -#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) -#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) -#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) -#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) -#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) -#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) -#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) -#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) -#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) -#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) -#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) -#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) -#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) -#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) -#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) -#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) -#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) -#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) -#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) -#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) -#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) -#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) -#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) -#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) -#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) -#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) - -/*! @name TIMEOUT - Time-out value register. */ -#define I2C_TIMEOUT_TOMIN_MASK (0xFU) -#define I2C_TIMEOUT_TOMIN_SHIFT (0U) -#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) -#define I2C_TIMEOUT_TO_MASK (0xFFF0U) -#define I2C_TIMEOUT_TO_SHIFT (4U) -#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) - -/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ -#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) -#define I2C_CLKDIV_DIVVAL_SHIFT (0U) -#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) - -/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ -#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) -#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) -#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) -#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) -#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) -#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) -#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) -#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) -#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) -#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) -#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) -#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) -#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) -#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) -#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) -#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) -#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) -#define I2C_INTSTAT_MONRDY_MASK (0x10000U) -#define I2C_INTSTAT_MONRDY_SHIFT (16U) -#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) -#define I2C_INTSTAT_MONOV_MASK (0x20000U) -#define I2C_INTSTAT_MONOV_SHIFT (17U) -#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) -#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) -#define I2C_INTSTAT_MONIDLE_SHIFT (19U) -#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) -#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) -#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) -#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) -#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) - -/*! @name MSTCTL - Master control register. */ -#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) -#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) -#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) -#define I2C_MSTCTL_MSTSTART_MASK (0x2U) -#define I2C_MSTCTL_MSTSTART_SHIFT (1U) -#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) -#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) -#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) -#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) -#define I2C_MSTCTL_MSTDMA_MASK (0x8U) -#define I2C_MSTCTL_MSTDMA_SHIFT (3U) -#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) - -/*! @name MSTTIME - Master timing configuration. */ -#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) -#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) -#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) -#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) -#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) -#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) - -/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ -#define I2C_MSTDAT_DATA_MASK (0xFFU) -#define I2C_MSTDAT_DATA_SHIFT (0U) -#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) - -/*! @name SLVCTL - Slave control register. */ -#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) -#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) -#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) -#define I2C_SLVCTL_SLVNACK_MASK (0x2U) -#define I2C_SLVCTL_SLVNACK_SHIFT (1U) -#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) -#define I2C_SLVCTL_SLVDMA_MASK (0x8U) -#define I2C_SLVCTL_SLVDMA_SHIFT (3U) -#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) -#define I2C_SLVCTL_AUTOACK_MASK (0x100U) -#define I2C_SLVCTL_AUTOACK_SHIFT (8U) -#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) -#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) -#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) -#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) - -/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ -#define I2C_SLVDAT_DATA_MASK (0xFFU) -#define I2C_SLVDAT_DATA_SHIFT (0U) -#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) - -/*! @name SLVADR - Slave address register. */ -#define I2C_SLVADR_SADISABLE_MASK (0x1U) -#define I2C_SLVADR_SADISABLE_SHIFT (0U) -#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) -#define I2C_SLVADR_SLVADR_MASK (0xFEU) -#define I2C_SLVADR_SLVADR_SHIFT (1U) -#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) -#define I2C_SLVADR_AUTONACK_MASK (0x8000U) -#define I2C_SLVADR_AUTONACK_SHIFT (15U) -#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) - -/* The count of I2C_SLVADR */ -#define I2C_SLVADR_COUNT (4U) - -/*! @name SLVQUAL0 - Slave Qualification for address 0. */ -#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) -#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) -#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) -#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) -#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) -#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) - -/*! @name MONRXDAT - Monitor receiver data register. */ -#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) -#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) -#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) -#define I2C_MONRXDAT_MONSTART_MASK (0x100U) -#define I2C_MONRXDAT_MONSTART_SHIFT (8U) -#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) -#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) -#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) -#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) -#define I2C_MONRXDAT_MONNACK_MASK (0x400U) -#define I2C_MONRXDAT_MONNACK_SHIFT (10U) -#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) - -/*! @name ID - Peripheral identification register. */ -#define I2C_ID_APERTURE_MASK (0xFFU) -#define I2C_ID_APERTURE_SHIFT (0U) -#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) -#define I2C_ID_MINOR_REV_MASK (0xF00U) -#define I2C_ID_MINOR_REV_SHIFT (8U) -#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) -#define I2C_ID_MAJOR_REV_MASK (0xF000U) -#define I2C_ID_MAJOR_REV_SHIFT (12U) -#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) -#define I2C_ID_ID_MASK (0xFFFF0000U) -#define I2C_ID_ID_SHIFT (16U) -#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) - - -/*! - * @} - */ /* end of group I2C_Register_Masks */ - - -/* I2C - Peripheral instance base addresses */ -/** Peripheral I2C0 base address */ -#define I2C0_BASE (0x40086000u) -/** Peripheral I2C0 base pointer */ -#define I2C0 ((I2C_Type *)I2C0_BASE) -/** Peripheral I2C1 base address */ -#define I2C1_BASE (0x40087000u) -/** Peripheral I2C1 base pointer */ -#define I2C1 ((I2C_Type *)I2C1_BASE) -/** Peripheral I2C2 base address */ -#define I2C2_BASE (0x40088000u) -/** Peripheral I2C2 base pointer */ -#define I2C2 ((I2C_Type *)I2C2_BASE) -/** Peripheral I2C3 base address */ -#define I2C3_BASE (0x40089000u) -/** Peripheral I2C3 base pointer */ -#define I2C3 ((I2C_Type *)I2C3_BASE) -/** Peripheral I2C4 base address */ -#define I2C4_BASE (0x4008A000u) -/** Peripheral I2C4 base pointer */ -#define I2C4 ((I2C_Type *)I2C4_BASE) -/** Peripheral I2C5 base address */ -#define I2C5_BASE (0x40096000u) -/** Peripheral I2C5 base pointer */ -#define I2C5 ((I2C_Type *)I2C5_BASE) -/** Peripheral I2C6 base address */ -#define I2C6_BASE (0x40097000u) -/** Peripheral I2C6 base pointer */ -#define I2C6 ((I2C_Type *)I2C6_BASE) -/** Peripheral I2C7 base address */ -#define I2C7_BASE (0x40098000u) -/** Peripheral I2C7 base pointer */ -#define I2C7 ((I2C_Type *)I2C7_BASE) -/** Peripheral I2C8 base address */ -#define I2C8_BASE (0x40099000u) -/** Peripheral I2C8 base pointer */ -#define I2C8 ((I2C_Type *)I2C8_BASE) -/** Peripheral I2C9 base address */ -#define I2C9_BASE (0x4009A000u) -/** Peripheral I2C9 base pointer */ -#define I2C9 ((I2C_Type *)I2C9_BASE) -/** Array initializer of I2C peripheral base addresses */ -#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE, I2C9_BASE } -/** Array initializer of I2C peripheral base pointers */ -#define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9 } -/** Interrupt vectors for the I2C peripheral type */ -#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn } - -/*! - * @} - */ /* end of group I2C_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2S Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer - * @{ - */ - -/** I2S - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[32]; - struct { /* offset: 0x20, array step: 0x20 */ - __IO uint32_t PCFG1; /**< Configuration register 1 for channel pair, array offset: 0x20, array step: 0x20 */ - __IO uint32_t PCFG2; /**< Configuration register 2 for channel pair, array offset: 0x24, array step: 0x20 */ - __IO uint32_t PSTAT; /**< Status register for channel pair, array offset: 0x28, array step: 0x20 */ - uint8_t RESERVED_0[20]; - } SECCHANNEL[3]; - uint8_t RESERVED_1[2944]; - __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ - __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ - __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ - uint8_t RESERVED_2[16]; - __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ - uint8_t RESERVED_3[480]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_4[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_5[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ - uint8_t RESERVED_6[8]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ - uint8_t RESERVED_7[8]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ - uint8_t RESERVED_8[4020]; - __I uint32_t ID; /**< I2S Module identification, offset: 0x1DFC */ -} I2S_Type; - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */ -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U) -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U) -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK) -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U) -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U) -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK) - -/* The count of I2S_SECCHANNEL_PCFG1 */ -#define I2S_SECCHANNEL_PCFG1_COUNT (3U) - -/*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */ -#define I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U) -#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U) -#define I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK) - -/* The count of I2S_SECCHANNEL_PCFG2 */ -#define I2S_SECCHANNEL_PCFG2_COUNT (3U) - -/*! @name SECCHANNEL_PSTAT - Status register for channel pair */ -#define I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U) -#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U) -#define I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK) -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U) -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U) -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK) -#define I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U) -#define I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U) -#define I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK) -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U) -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U) -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK) - -/* The count of I2S_SECCHANNEL_PSTAT */ -#define I2S_SECCHANNEL_PSTAT_COUNT (3U) - -/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ -#define I2S_CFG1_MAINENABLE_MASK (0x1U) -#define I2S_CFG1_MAINENABLE_SHIFT (0U) -#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) -#define I2S_CFG1_DATAPAUSE_MASK (0x2U) -#define I2S_CFG1_DATAPAUSE_SHIFT (1U) -#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) -#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) -#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) -#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) -#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) -#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) -#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) -#define I2S_CFG1_MODE_MASK (0xC0U) -#define I2S_CFG1_MODE_SHIFT (6U) -#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) -#define I2S_CFG1_RIGHTLOW_MASK (0x100U) -#define I2S_CFG1_RIGHTLOW_SHIFT (8U) -#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) -#define I2S_CFG1_LEFTJUST_MASK (0x200U) -#define I2S_CFG1_LEFTJUST_SHIFT (9U) -#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) -#define I2S_CFG1_ONECHANNEL_MASK (0x400U) -#define I2S_CFG1_ONECHANNEL_SHIFT (10U) -#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) -#define I2S_CFG1_PDMDATA_MASK (0x800U) -#define I2S_CFG1_PDMDATA_SHIFT (11U) -#define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK) -#define I2S_CFG1_SCK_POL_MASK (0x1000U) -#define I2S_CFG1_SCK_POL_SHIFT (12U) -#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) -#define I2S_CFG1_WS_POL_MASK (0x2000U) -#define I2S_CFG1_WS_POL_SHIFT (13U) -#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) -#define I2S_CFG1_DATALEN_MASK (0x1F0000U) -#define I2S_CFG1_DATALEN_SHIFT (16U) -#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) - -/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ -#define I2S_CFG2_FRAMELEN_MASK (0x1FFU) -#define I2S_CFG2_FRAMELEN_SHIFT (0U) -#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) -#define I2S_CFG2_POSITION_MASK (0x1FF0000U) -#define I2S_CFG2_POSITION_SHIFT (16U) -#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) - -/*! @name STAT - Status register for the primary channel pair. */ -#define I2S_STAT_BUSY_MASK (0x1U) -#define I2S_STAT_BUSY_SHIFT (0U) -#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) -#define I2S_STAT_SLVFRMERR_MASK (0x2U) -#define I2S_STAT_SLVFRMERR_SHIFT (1U) -#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) -#define I2S_STAT_LR_MASK (0x4U) -#define I2S_STAT_LR_SHIFT (2U) -#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) -#define I2S_STAT_DATAPAUSED_MASK (0x8U) -#define I2S_STAT_DATAPAUSED_SHIFT (3U) -#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) - -/*! @name DIV - Clock divider, used by all channel pairs. */ -#define I2S_DIV_DIV_MASK (0xFFFU) -#define I2S_DIV_DIV_SHIFT (0U) -#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) -#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) -#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) -#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) -#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) -#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) -#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) -#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) -#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) -#define I2S_FIFOCFG_PACK48_MASK (0x8U) -#define I2S_FIFOCFG_PACK48_SHIFT (3U) -#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) -#define I2S_FIFOCFG_SIZE_MASK (0x30U) -#define I2S_FIFOCFG_SIZE_SHIFT (4U) -#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) -#define I2S_FIFOCFG_DMATX_MASK (0x1000U) -#define I2S_FIFOCFG_DMATX_SHIFT (12U) -#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) -#define I2S_FIFOCFG_DMARX_MASK (0x2000U) -#define I2S_FIFOCFG_DMARX_SHIFT (13U) -#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) -#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) -#define I2S_FIFOCFG_WAKETX_SHIFT (14U) -#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) -#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) -#define I2S_FIFOCFG_WAKERX_SHIFT (15U) -#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) -#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) -#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) -#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) -#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) -#define I2S_FIFOCFG_POPDBG_MASK (0x40000U) -#define I2S_FIFOCFG_POPDBG_SHIFT (18U) -#define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK) - -/*! @name FIFOSTAT - FIFO status register. */ -#define I2S_FIFOSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOSTAT_TXERR_SHIFT (0U) -#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) -#define I2S_FIFOSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOSTAT_RXERR_SHIFT (1U) -#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) -#define I2S_FIFOSTAT_PERINT_MASK (0x8U) -#define I2S_FIFOSTAT_PERINT_SHIFT (3U) -#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) -#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) -#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) -#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) -#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) -#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) -#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) -#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) -#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) -#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) -#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) -#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) -#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) -#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) -#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) -#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) -#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) -#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) -#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) -#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) -#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) -#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) -#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) -#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) -#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) -#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) -#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) -#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) -#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) -#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) -#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) -#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) -#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) -#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) -#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) -#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) -#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) -#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) -#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) -#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) -#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) -#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) -#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) -#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) -#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) -#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) -#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) -#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) -#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) - -/*! @name FIFOWR - FIFO write data. */ -#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFOWR_TXDATA_SHIFT (0U) -#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) - -/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) -#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) -#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) - -/*! @name FIFORD - FIFO read data. */ -#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORD_RXDATA_SHIFT (0U) -#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) - -/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48H_RXDATA_SHIFT (0U) -#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) -#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) - -/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) -#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) - -/*! @name ID - I2S Module identification */ -#define I2S_ID_Aperture_MASK (0xFFU) -#define I2S_ID_Aperture_SHIFT (0U) -#define I2S_ID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK) -#define I2S_ID_Minor_Rev_MASK (0xF00U) -#define I2S_ID_Minor_Rev_SHIFT (8U) -#define I2S_ID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK) -#define I2S_ID_Major_Rev_MASK (0xF000U) -#define I2S_ID_Major_Rev_SHIFT (12U) -#define I2S_ID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK) -#define I2S_ID_ID_MASK (0xFFFF0000U) -#define I2S_ID_ID_SHIFT (16U) -#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) - - -/*! - * @} - */ /* end of group I2S_Register_Masks */ - - -/* I2S - Peripheral instance base addresses */ -/** Peripheral I2S0 base address */ -#define I2S0_BASE (0x40097000u) -/** Peripheral I2S0 base pointer */ -#define I2S0 ((I2S_Type *)I2S0_BASE) -/** Peripheral I2S1 base address */ -#define I2S1_BASE (0x40098000u) -/** Peripheral I2S1 base pointer */ -#define I2S1 ((I2S_Type *)I2S1_BASE) -/** Array initializer of I2S peripheral base addresses */ -#define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE } -/** Array initializer of I2S peripheral base pointers */ -#define I2S_BASE_PTRS { I2S0, I2S1 } -/** Interrupt vectors for the I2S peripheral type */ -#define I2S_IRQS { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2S_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer - * @{ - */ - -/** INPUTMUX - Register Layout Typedef */ -typedef struct { - __IO uint32_t SCT0_INMUX[7]; /**< Trigger select register for DMA channel, array offset: 0x0, array step: 0x4 */ - uint8_t RESERVED_0[164]; - __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ - __IO uint32_t DMA_ITRIG_INMUX[30]; /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */ - uint8_t RESERVED_1[8]; - __IO uint32_t DMA_OTRIG_INMUX[4]; /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */ - uint8_t RESERVED_2[16]; - __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ - __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ -} INPUTMUX_Type; - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks - * @{ - */ - -/*! @name SCT0_INMUX - Trigger select register for DMA channel */ -#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU) -#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) -#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK) - -/* The count of INPUTMUX_SCT0_INMUX */ -#define INPUTMUX_SCT0_INMUX_COUNT (7U) - -/*! @name PINTSEL - Pin interrupt select register */ -#define INPUTMUX_PINTSEL_INTPIN_MASK (0xFFU) -#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) -#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) - -/* The count of INPUTMUX_PINTSEL */ -#define INPUTMUX_PINTSEL_COUNT (8U) - -/*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */ -#define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U) -#define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK) - -/* The count of INPUTMUX_DMA_ITRIG_INMUX */ -#define INPUTMUX_DMA_ITRIG_INMUX_COUNT (30U) - -/*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */ -#define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT (0U) -#define INPUTMUX_DMA_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK) - -/* The count of INPUTMUX_DMA_OTRIG_INMUX */ -#define INPUTMUX_DMA_OTRIG_INMUX_COUNT (4U) - -/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ -#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) -#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) - -/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) -#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) - - -/*! - * @} - */ /* end of group INPUTMUX_Register_Masks */ - - -/* INPUTMUX - Peripheral instance base addresses */ -/** Peripheral INPUTMUX base address */ -#define INPUTMUX_BASE (0x40005000u) -/** Peripheral INPUTMUX base pointer */ -#define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) -/** Array initializer of INPUTMUX peripheral base addresses */ -#define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } -/** Array initializer of INPUTMUX peripheral base pointers */ -#define INPUTMUX_BASE_PTRS { INPUTMUX } - -/*! - * @} - */ /* end of group INPUTMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- IOCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer - * @{ - */ - -/** IOCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t PIO[6][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ -} IOCON_Type; - -/* ---------------------------------------------------------------------------- - -- IOCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Register_Masks IOCON Register Masks - * @{ - */ - -/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31 */ -#define IOCON_PIO_FUNC_MASK (0xFU) -#define IOCON_PIO_FUNC_SHIFT (0U) -#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) -#define IOCON_PIO_MODE_MASK (0x30U) -#define IOCON_PIO_MODE_SHIFT (4U) -#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) -#define IOCON_PIO_I2CSLEW_MASK (0x40U) -#define IOCON_PIO_I2CSLEW_SHIFT (6U) -#define IOCON_PIO_I2CSLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK) -#define IOCON_PIO_INVERT_MASK (0x80U) -#define IOCON_PIO_INVERT_SHIFT (7U) -#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) -#define IOCON_PIO_DIGIMODE_MASK (0x100U) -#define IOCON_PIO_DIGIMODE_SHIFT (8U) -#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) -#define IOCON_PIO_FILTEROFF_MASK (0x200U) -#define IOCON_PIO_FILTEROFF_SHIFT (9U) -#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) -#define IOCON_PIO_I2CDRIVE_MASK (0x400U) -#define IOCON_PIO_I2CDRIVE_SHIFT (10U) -#define IOCON_PIO_I2CDRIVE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK) -#define IOCON_PIO_SLEW_MASK (0x400U) -#define IOCON_PIO_SLEW_SHIFT (10U) -#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) -#define IOCON_PIO_OD_MASK (0x800U) -#define IOCON_PIO_OD_SHIFT (11U) -#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) -#define IOCON_PIO_I2CFILTER_MASK (0x800U) -#define IOCON_PIO_I2CFILTER_SHIFT (11U) -#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT (6U) - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT2 (32U) - - -/*! - * @} - */ /* end of group IOCON_Register_Masks */ - - -/* IOCON - Peripheral instance base addresses */ -/** Peripheral IOCON base address */ -#define IOCON_BASE (0x40001000u) -/** Peripheral IOCON base pointer */ -#define IOCON ((IOCON_Type *)IOCON_BASE) -/** Array initializer of IOCON peripheral base addresses */ -#define IOCON_BASE_ADDRS { IOCON_BASE } -/** Array initializer of IOCON peripheral base pointers */ -#define IOCON_BASE_PTRS { IOCON } - -/*! - * @} - */ /* end of group IOCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LCD Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer - * @{ - */ - -/** LCD - Register Layout Typedef */ -typedef struct { - __IO uint32_t TIMH; /**< Horizontal Timing Control register, offset: 0x0 */ - __IO uint32_t TIMV; /**< Vertical Timing Control register, offset: 0x4 */ - __IO uint32_t POL; /**< Clock and Signal Polarity Control register, offset: 0x8 */ - __IO uint32_t LE; /**< Line End Control register, offset: 0xC */ - __IO uint32_t UPBASE; /**< Upper Panel Frame Base Address register, offset: 0x10 */ - __IO uint32_t LPBASE; /**< Lower Panel Frame Base Address register, offset: 0x14 */ - __IO uint32_t CTRL; /**< LCD Control register, offset: 0x18 */ - __IO uint32_t INTMSK; /**< Interrupt Mask register, offset: 0x1C */ - __I uint32_t INTRAW; /**< Raw Interrupt Status register, offset: 0x20 */ - __I uint32_t INTSTAT; /**< Masked Interrupt Status register, offset: 0x24 */ - __IO uint32_t INTCLR; /**< Interrupt Clear register, offset: 0x28 */ - __I uint32_t UPCURR; /**< Upper Panel Current Address Value register, offset: 0x2C */ - __I uint32_t LPCURR; /**< Lower Panel Current Address Value register, offset: 0x30 */ - uint8_t RESERVED_0[460]; - __IO uint32_t PAL[128]; /**< 256x16-bit Color Palette registers, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_1[1024]; - __IO uint32_t CRSR_IMG[256]; /**< Cursor Image registers, array offset: 0x800, array step: 0x4 */ - __IO uint32_t CRSR_CTRL; /**< Cursor Control register, offset: 0xC00 */ - __IO uint32_t CRSR_CFG; /**< Cursor Configuration register, offset: 0xC04 */ - __IO uint32_t CRSR_PAL0; /**< Cursor Palette register 0, offset: 0xC08 */ - __IO uint32_t CRSR_PAL1; /**< Cursor Palette register 1, offset: 0xC0C */ - __IO uint32_t CRSR_XY; /**< Cursor XY Position register, offset: 0xC10 */ - __IO uint32_t CRSR_CLIP; /**< Cursor Clip Position register, offset: 0xC14 */ - uint8_t RESERVED_2[8]; - __IO uint32_t CRSR_INTMSK; /**< Cursor Interrupt Mask register, offset: 0xC20 */ - __O uint32_t CRSR_INTCLR; /**< Cursor Interrupt Clear register, offset: 0xC24 */ - __I uint32_t CRSR_INTRAW; /**< Cursor Raw Interrupt Status register, offset: 0xC28 */ - __I uint32_t CRSR_INTSTAT; /**< Cursor Masked Interrupt Status register, offset: 0xC2C */ -} LCD_Type; - -/* ---------------------------------------------------------------------------- - -- LCD Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LCD_Register_Masks LCD Register Masks - * @{ - */ - -/*! @name TIMH - Horizontal Timing Control register */ -#define LCD_TIMH_PPL_MASK (0xFCU) -#define LCD_TIMH_PPL_SHIFT (2U) -#define LCD_TIMH_PPL(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_PPL_SHIFT)) & LCD_TIMH_PPL_MASK) -#define LCD_TIMH_HSW_MASK (0xFF00U) -#define LCD_TIMH_HSW_SHIFT (8U) -#define LCD_TIMH_HSW(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HSW_SHIFT)) & LCD_TIMH_HSW_MASK) -#define LCD_TIMH_HFP_MASK (0xFF0000U) -#define LCD_TIMH_HFP_SHIFT (16U) -#define LCD_TIMH_HFP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HFP_SHIFT)) & LCD_TIMH_HFP_MASK) -#define LCD_TIMH_HBP_MASK (0xFF000000U) -#define LCD_TIMH_HBP_SHIFT (24U) -#define LCD_TIMH_HBP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HBP_SHIFT)) & LCD_TIMH_HBP_MASK) - -/*! @name TIMV - Vertical Timing Control register */ -#define LCD_TIMV_LPP_MASK (0x3FFU) -#define LCD_TIMV_LPP_SHIFT (0U) -#define LCD_TIMV_LPP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_LPP_SHIFT)) & LCD_TIMV_LPP_MASK) -#define LCD_TIMV_VSW_MASK (0xFC00U) -#define LCD_TIMV_VSW_SHIFT (10U) -#define LCD_TIMV_VSW(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VSW_SHIFT)) & LCD_TIMV_VSW_MASK) -#define LCD_TIMV_VFP_MASK (0xFF0000U) -#define LCD_TIMV_VFP_SHIFT (16U) -#define LCD_TIMV_VFP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VFP_SHIFT)) & LCD_TIMV_VFP_MASK) -#define LCD_TIMV_VBP_MASK (0xFF000000U) -#define LCD_TIMV_VBP_SHIFT (24U) -#define LCD_TIMV_VBP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VBP_SHIFT)) & LCD_TIMV_VBP_MASK) - -/*! @name POL - Clock and Signal Polarity Control register */ -#define LCD_POL_PCD_LO_MASK (0x1FU) -#define LCD_POL_PCD_LO_SHIFT (0U) -#define LCD_POL_PCD_LO(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_LO_SHIFT)) & LCD_POL_PCD_LO_MASK) -#define LCD_POL_ACB_MASK (0x7C0U) -#define LCD_POL_ACB_SHIFT (6U) -#define LCD_POL_ACB(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_ACB_SHIFT)) & LCD_POL_ACB_MASK) -#define LCD_POL_IVS_MASK (0x800U) -#define LCD_POL_IVS_SHIFT (11U) -#define LCD_POL_IVS(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IVS_SHIFT)) & LCD_POL_IVS_MASK) -#define LCD_POL_IHS_MASK (0x1000U) -#define LCD_POL_IHS_SHIFT (12U) -#define LCD_POL_IHS(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IHS_SHIFT)) & LCD_POL_IHS_MASK) -#define LCD_POL_IPC_MASK (0x2000U) -#define LCD_POL_IPC_SHIFT (13U) -#define LCD_POL_IPC(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IPC_SHIFT)) & LCD_POL_IPC_MASK) -#define LCD_POL_IOE_MASK (0x4000U) -#define LCD_POL_IOE_SHIFT (14U) -#define LCD_POL_IOE(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IOE_SHIFT)) & LCD_POL_IOE_MASK) -#define LCD_POL_CPL_MASK (0x3FF0000U) -#define LCD_POL_CPL_SHIFT (16U) -#define LCD_POL_CPL(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_CPL_SHIFT)) & LCD_POL_CPL_MASK) -#define LCD_POL_BCD_MASK (0x4000000U) -#define LCD_POL_BCD_SHIFT (26U) -#define LCD_POL_BCD(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_BCD_SHIFT)) & LCD_POL_BCD_MASK) -#define LCD_POL_PCD_HI_MASK (0xF8000000U) -#define LCD_POL_PCD_HI_SHIFT (27U) -#define LCD_POL_PCD_HI(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_HI_SHIFT)) & LCD_POL_PCD_HI_MASK) - -/*! @name LE - Line End Control register */ -#define LCD_LE_LED_MASK (0x7FU) -#define LCD_LE_LED_SHIFT (0U) -#define LCD_LE_LED(x) (((uint32_t)(((uint32_t)(x)) << LCD_LE_LED_SHIFT)) & LCD_LE_LED_MASK) -#define LCD_LE_LEE_MASK (0x10000U) -#define LCD_LE_LEE_SHIFT (16U) -#define LCD_LE_LEE(x) (((uint32_t)(((uint32_t)(x)) << LCD_LE_LEE_SHIFT)) & LCD_LE_LEE_MASK) - -/*! @name UPBASE - Upper Panel Frame Base Address register */ -#define LCD_UPBASE_LCDUPBASE_MASK (0xFFFFFFF8U) -#define LCD_UPBASE_LCDUPBASE_SHIFT (3U) -#define LCD_UPBASE_LCDUPBASE(x) (((uint32_t)(((uint32_t)(x)) << LCD_UPBASE_LCDUPBASE_SHIFT)) & LCD_UPBASE_LCDUPBASE_MASK) - -/*! @name LPBASE - Lower Panel Frame Base Address register */ -#define LCD_LPBASE_LCDLPBASE_MASK (0xFFFFFFF8U) -#define LCD_LPBASE_LCDLPBASE_SHIFT (3U) -#define LCD_LPBASE_LCDLPBASE(x) (((uint32_t)(((uint32_t)(x)) << LCD_LPBASE_LCDLPBASE_SHIFT)) & LCD_LPBASE_LCDLPBASE_MASK) - -/*! @name CTRL - LCD Control register */ -#define LCD_CTRL_LCDEN_MASK (0x1U) -#define LCD_CTRL_LCDEN_SHIFT (0U) -#define LCD_CTRL_LCDEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDEN_SHIFT)) & LCD_CTRL_LCDEN_MASK) -#define LCD_CTRL_LCDBPP_MASK (0xEU) -#define LCD_CTRL_LCDBPP_SHIFT (1U) -#define LCD_CTRL_LCDBPP(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBPP_SHIFT)) & LCD_CTRL_LCDBPP_MASK) -#define LCD_CTRL_LCDBW_MASK (0x10U) -#define LCD_CTRL_LCDBW_SHIFT (4U) -#define LCD_CTRL_LCDBW(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBW_SHIFT)) & LCD_CTRL_LCDBW_MASK) -#define LCD_CTRL_LCDTFT_MASK (0x20U) -#define LCD_CTRL_LCDTFT_SHIFT (5U) -#define LCD_CTRL_LCDTFT(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDTFT_SHIFT)) & LCD_CTRL_LCDTFT_MASK) -#define LCD_CTRL_LCDMONO8_MASK (0x40U) -#define LCD_CTRL_LCDMONO8_SHIFT (6U) -#define LCD_CTRL_LCDMONO8(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDMONO8_SHIFT)) & LCD_CTRL_LCDMONO8_MASK) -#define LCD_CTRL_LCDDUAL_MASK (0x80U) -#define LCD_CTRL_LCDDUAL_SHIFT (7U) -#define LCD_CTRL_LCDDUAL(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDDUAL_SHIFT)) & LCD_CTRL_LCDDUAL_MASK) -#define LCD_CTRL_BGR_MASK (0x100U) -#define LCD_CTRL_BGR_SHIFT (8U) -#define LCD_CTRL_BGR(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BGR_SHIFT)) & LCD_CTRL_BGR_MASK) -#define LCD_CTRL_BEBO_MASK (0x200U) -#define LCD_CTRL_BEBO_SHIFT (9U) -#define LCD_CTRL_BEBO(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEBO_SHIFT)) & LCD_CTRL_BEBO_MASK) -#define LCD_CTRL_BEPO_MASK (0x400U) -#define LCD_CTRL_BEPO_SHIFT (10U) -#define LCD_CTRL_BEPO(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEPO_SHIFT)) & LCD_CTRL_BEPO_MASK) -#define LCD_CTRL_LCDPWR_MASK (0x800U) -#define LCD_CTRL_LCDPWR_SHIFT (11U) -#define LCD_CTRL_LCDPWR(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDPWR_SHIFT)) & LCD_CTRL_LCDPWR_MASK) -#define LCD_CTRL_LCDVCOMP_MASK (0x3000U) -#define LCD_CTRL_LCDVCOMP_SHIFT (12U) -#define LCD_CTRL_LCDVCOMP(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDVCOMP_SHIFT)) & LCD_CTRL_LCDVCOMP_MASK) -#define LCD_CTRL_WATERMARK_MASK (0x10000U) -#define LCD_CTRL_WATERMARK_SHIFT (16U) -#define LCD_CTRL_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_WATERMARK_SHIFT)) & LCD_CTRL_WATERMARK_MASK) - -/*! @name INTMSK - Interrupt Mask register */ -#define LCD_INTMSK_FUFIM_MASK (0x2U) -#define LCD_INTMSK_FUFIM_SHIFT (1U) -#define LCD_INTMSK_FUFIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_FUFIM_SHIFT)) & LCD_INTMSK_FUFIM_MASK) -#define LCD_INTMSK_LNBUIM_MASK (0x4U) -#define LCD_INTMSK_LNBUIM_SHIFT (2U) -#define LCD_INTMSK_LNBUIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_LNBUIM_SHIFT)) & LCD_INTMSK_LNBUIM_MASK) -#define LCD_INTMSK_VCOMPIM_MASK (0x8U) -#define LCD_INTMSK_VCOMPIM_SHIFT (3U) -#define LCD_INTMSK_VCOMPIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_VCOMPIM_SHIFT)) & LCD_INTMSK_VCOMPIM_MASK) -#define LCD_INTMSK_BERIM_MASK (0x10U) -#define LCD_INTMSK_BERIM_SHIFT (4U) -#define LCD_INTMSK_BERIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_BERIM_SHIFT)) & LCD_INTMSK_BERIM_MASK) - -/*! @name INTRAW - Raw Interrupt Status register */ -#define LCD_INTRAW_FUFRIS_MASK (0x2U) -#define LCD_INTRAW_FUFRIS_SHIFT (1U) -#define LCD_INTRAW_FUFRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_FUFRIS_SHIFT)) & LCD_INTRAW_FUFRIS_MASK) -#define LCD_INTRAW_LNBURIS_MASK (0x4U) -#define LCD_INTRAW_LNBURIS_SHIFT (2U) -#define LCD_INTRAW_LNBURIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_LNBURIS_SHIFT)) & LCD_INTRAW_LNBURIS_MASK) -#define LCD_INTRAW_VCOMPRIS_MASK (0x8U) -#define LCD_INTRAW_VCOMPRIS_SHIFT (3U) -#define LCD_INTRAW_VCOMPRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_VCOMPRIS_SHIFT)) & LCD_INTRAW_VCOMPRIS_MASK) -#define LCD_INTRAW_BERRAW_MASK (0x10U) -#define LCD_INTRAW_BERRAW_SHIFT (4U) -#define LCD_INTRAW_BERRAW(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_BERRAW_SHIFT)) & LCD_INTRAW_BERRAW_MASK) - -/*! @name INTSTAT - Masked Interrupt Status register */ -#define LCD_INTSTAT_FUFMIS_MASK (0x2U) -#define LCD_INTSTAT_FUFMIS_SHIFT (1U) -#define LCD_INTSTAT_FUFMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_FUFMIS_SHIFT)) & LCD_INTSTAT_FUFMIS_MASK) -#define LCD_INTSTAT_LNBUMIS_MASK (0x4U) -#define LCD_INTSTAT_LNBUMIS_SHIFT (2U) -#define LCD_INTSTAT_LNBUMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_LNBUMIS_SHIFT)) & LCD_INTSTAT_LNBUMIS_MASK) -#define LCD_INTSTAT_VCOMPMIS_MASK (0x8U) -#define LCD_INTSTAT_VCOMPMIS_SHIFT (3U) -#define LCD_INTSTAT_VCOMPMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_VCOMPMIS_SHIFT)) & LCD_INTSTAT_VCOMPMIS_MASK) -#define LCD_INTSTAT_BERMIS_MASK (0x10U) -#define LCD_INTSTAT_BERMIS_SHIFT (4U) -#define LCD_INTSTAT_BERMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_BERMIS_SHIFT)) & LCD_INTSTAT_BERMIS_MASK) - -/*! @name INTCLR - Interrupt Clear register */ -#define LCD_INTCLR_FUFIC_MASK (0x2U) -#define LCD_INTCLR_FUFIC_SHIFT (1U) -#define LCD_INTCLR_FUFIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_FUFIC_SHIFT)) & LCD_INTCLR_FUFIC_MASK) -#define LCD_INTCLR_LNBUIC_MASK (0x4U) -#define LCD_INTCLR_LNBUIC_SHIFT (2U) -#define LCD_INTCLR_LNBUIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_LNBUIC_SHIFT)) & LCD_INTCLR_LNBUIC_MASK) -#define LCD_INTCLR_VCOMPIC_MASK (0x8U) -#define LCD_INTCLR_VCOMPIC_SHIFT (3U) -#define LCD_INTCLR_VCOMPIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_VCOMPIC_SHIFT)) & LCD_INTCLR_VCOMPIC_MASK) -#define LCD_INTCLR_BERIC_MASK (0x10U) -#define LCD_INTCLR_BERIC_SHIFT (4U) -#define LCD_INTCLR_BERIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_BERIC_SHIFT)) & LCD_INTCLR_BERIC_MASK) - -/*! @name UPCURR - Upper Panel Current Address Value register */ -#define LCD_UPCURR_LCDUPCURR_MASK (0xFFFFFFFFU) -#define LCD_UPCURR_LCDUPCURR_SHIFT (0U) -#define LCD_UPCURR_LCDUPCURR(x) (((uint32_t)(((uint32_t)(x)) << LCD_UPCURR_LCDUPCURR_SHIFT)) & LCD_UPCURR_LCDUPCURR_MASK) - -/*! @name LPCURR - Lower Panel Current Address Value register */ -#define LCD_LPCURR_LCDLPCURR_MASK (0xFFFFFFFFU) -#define LCD_LPCURR_LCDLPCURR_SHIFT (0U) -#define LCD_LPCURR_LCDLPCURR(x) (((uint32_t)(((uint32_t)(x)) << LCD_LPCURR_LCDLPCURR_SHIFT)) & LCD_LPCURR_LCDLPCURR_MASK) - -/*! @name PAL - 256x16-bit Color Palette registers */ -#define LCD_PAL_R04_0_MASK (0x1FU) -#define LCD_PAL_R04_0_SHIFT (0U) -#define LCD_PAL_R04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R04_0_SHIFT)) & LCD_PAL_R04_0_MASK) -#define LCD_PAL_G04_0_MASK (0x3E0U) -#define LCD_PAL_G04_0_SHIFT (5U) -#define LCD_PAL_G04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G04_0_SHIFT)) & LCD_PAL_G04_0_MASK) -#define LCD_PAL_B04_0_MASK (0x7C00U) -#define LCD_PAL_B04_0_SHIFT (10U) -#define LCD_PAL_B04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B04_0_SHIFT)) & LCD_PAL_B04_0_MASK) -#define LCD_PAL_I0_MASK (0x8000U) -#define LCD_PAL_I0_SHIFT (15U) -#define LCD_PAL_I0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I0_SHIFT)) & LCD_PAL_I0_MASK) -#define LCD_PAL_R14_0_MASK (0x1F0000U) -#define LCD_PAL_R14_0_SHIFT (16U) -#define LCD_PAL_R14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R14_0_SHIFT)) & LCD_PAL_R14_0_MASK) -#define LCD_PAL_G14_0_MASK (0x3E00000U) -#define LCD_PAL_G14_0_SHIFT (21U) -#define LCD_PAL_G14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G14_0_SHIFT)) & LCD_PAL_G14_0_MASK) -#define LCD_PAL_B14_0_MASK (0x7C000000U) -#define LCD_PAL_B14_0_SHIFT (26U) -#define LCD_PAL_B14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B14_0_SHIFT)) & LCD_PAL_B14_0_MASK) -#define LCD_PAL_I1_MASK (0x80000000U) -#define LCD_PAL_I1_SHIFT (31U) -#define LCD_PAL_I1(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I1_SHIFT)) & LCD_PAL_I1_MASK) - -/* The count of LCD_PAL */ -#define LCD_PAL_COUNT (128U) - -/*! @name CRSR_IMG - Cursor Image registers */ -#define LCD_CRSR_IMG_CRSR_IMG_MASK (0xFFFFFFFFU) -#define LCD_CRSR_IMG_CRSR_IMG_SHIFT (0U) -#define LCD_CRSR_IMG_CRSR_IMG(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_IMG_CRSR_IMG_SHIFT)) & LCD_CRSR_IMG_CRSR_IMG_MASK) - -/* The count of LCD_CRSR_IMG */ -#define LCD_CRSR_IMG_COUNT (256U) - -/*! @name CRSR_CTRL - Cursor Control register */ -#define LCD_CRSR_CTRL_CRSRON_MASK (0x1U) -#define LCD_CRSR_CTRL_CRSRON_SHIFT (0U) -#define LCD_CRSR_CTRL_CRSRON(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRON_SHIFT)) & LCD_CRSR_CTRL_CRSRON_MASK) -#define LCD_CRSR_CTRL_CRSRNUM1_0_MASK (0x30U) -#define LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT (4U) -#define LCD_CRSR_CTRL_CRSRNUM1_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT)) & LCD_CRSR_CTRL_CRSRNUM1_0_MASK) - -/*! @name CRSR_CFG - Cursor Configuration register */ -#define LCD_CRSR_CFG_CRSRSIZE_MASK (0x1U) -#define LCD_CRSR_CFG_CRSRSIZE_SHIFT (0U) -#define LCD_CRSR_CFG_CRSRSIZE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_CRSRSIZE_SHIFT)) & LCD_CRSR_CFG_CRSRSIZE_MASK) -#define LCD_CRSR_CFG_FRAMESYNC_MASK (0x2U) -#define LCD_CRSR_CFG_FRAMESYNC_SHIFT (1U) -#define LCD_CRSR_CFG_FRAMESYNC(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_FRAMESYNC_SHIFT)) & LCD_CRSR_CFG_FRAMESYNC_MASK) - -/*! @name CRSR_PAL0 - Cursor Palette register 0 */ -#define LCD_CRSR_PAL0_RED_MASK (0xFFU) -#define LCD_CRSR_PAL0_RED_SHIFT (0U) -#define LCD_CRSR_PAL0_RED(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_RED_SHIFT)) & LCD_CRSR_PAL0_RED_MASK) -#define LCD_CRSR_PAL0_GREEN_MASK (0xFF00U) -#define LCD_CRSR_PAL0_GREEN_SHIFT (8U) -#define LCD_CRSR_PAL0_GREEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_GREEN_SHIFT)) & LCD_CRSR_PAL0_GREEN_MASK) -#define LCD_CRSR_PAL0_BLUE_MASK (0xFF0000U) -#define LCD_CRSR_PAL0_BLUE_SHIFT (16U) -#define LCD_CRSR_PAL0_BLUE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_BLUE_SHIFT)) & LCD_CRSR_PAL0_BLUE_MASK) - -/*! @name CRSR_PAL1 - Cursor Palette register 1 */ -#define LCD_CRSR_PAL1_RED_MASK (0xFFU) -#define LCD_CRSR_PAL1_RED_SHIFT (0U) -#define LCD_CRSR_PAL1_RED(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_RED_SHIFT)) & LCD_CRSR_PAL1_RED_MASK) -#define LCD_CRSR_PAL1_GREEN_MASK (0xFF00U) -#define LCD_CRSR_PAL1_GREEN_SHIFT (8U) -#define LCD_CRSR_PAL1_GREEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_GREEN_SHIFT)) & LCD_CRSR_PAL1_GREEN_MASK) -#define LCD_CRSR_PAL1_BLUE_MASK (0xFF0000U) -#define LCD_CRSR_PAL1_BLUE_SHIFT (16U) -#define LCD_CRSR_PAL1_BLUE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_BLUE_SHIFT)) & LCD_CRSR_PAL1_BLUE_MASK) - -/*! @name CRSR_XY - Cursor XY Position register */ -#define LCD_CRSR_XY_CRSRX_MASK (0x3FFU) -#define LCD_CRSR_XY_CRSRX_SHIFT (0U) -#define LCD_CRSR_XY_CRSRX(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRX_SHIFT)) & LCD_CRSR_XY_CRSRX_MASK) -#define LCD_CRSR_XY_CRSRY_MASK (0x3FF0000U) -#define LCD_CRSR_XY_CRSRY_SHIFT (16U) -#define LCD_CRSR_XY_CRSRY(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRY_SHIFT)) & LCD_CRSR_XY_CRSRY_MASK) - -/*! @name CRSR_CLIP - Cursor Clip Position register */ -#define LCD_CRSR_CLIP_CRSRCLIPX_MASK (0x3FU) -#define LCD_CRSR_CLIP_CRSRCLIPX_SHIFT (0U) -#define LCD_CRSR_CLIP_CRSRCLIPX(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPX_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPX_MASK) -#define LCD_CRSR_CLIP_CRSRCLIPY_MASK (0x3F00U) -#define LCD_CRSR_CLIP_CRSRCLIPY_SHIFT (8U) -#define LCD_CRSR_CLIP_CRSRCLIPY(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPY_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPY_MASK) - -/*! @name CRSR_INTMSK - Cursor Interrupt Mask register */ -#define LCD_CRSR_INTMSK_CRSRIM_MASK (0x1U) -#define LCD_CRSR_INTMSK_CRSRIM_SHIFT (0U) -#define LCD_CRSR_INTMSK_CRSRIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTMSK_CRSRIM_SHIFT)) & LCD_CRSR_INTMSK_CRSRIM_MASK) - -/*! @name CRSR_INTCLR - Cursor Interrupt Clear register */ -#define LCD_CRSR_INTCLR_CRSRIC_MASK (0x1U) -#define LCD_CRSR_INTCLR_CRSRIC_SHIFT (0U) -#define LCD_CRSR_INTCLR_CRSRIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTCLR_CRSRIC_SHIFT)) & LCD_CRSR_INTCLR_CRSRIC_MASK) - -/*! @name CRSR_INTRAW - Cursor Raw Interrupt Status register */ -#define LCD_CRSR_INTRAW_CRSRRIS_MASK (0x1U) -#define LCD_CRSR_INTRAW_CRSRRIS_SHIFT (0U) -#define LCD_CRSR_INTRAW_CRSRRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTRAW_CRSRRIS_SHIFT)) & LCD_CRSR_INTRAW_CRSRRIS_MASK) - -/*! @name CRSR_INTSTAT - Cursor Masked Interrupt Status register */ -#define LCD_CRSR_INTSTAT_CRSRMIS_MASK (0x1U) -#define LCD_CRSR_INTSTAT_CRSRMIS_SHIFT (0U) -#define LCD_CRSR_INTSTAT_CRSRMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTSTAT_CRSRMIS_SHIFT)) & LCD_CRSR_INTSTAT_CRSRMIS_MASK) - - -/*! - * @} - */ /* end of group LCD_Register_Masks */ - - -/* LCD - Peripheral instance base addresses */ -/** Peripheral LCD base address */ -#define LCD_BASE (0x40083000u) -/** Peripheral LCD base pointer */ -#define LCD ((LCD_Type *)LCD_BASE) -/** Array initializer of LCD peripheral base addresses */ -#define LCD_BASE_ADDRS { LCD_BASE } -/** Array initializer of LCD peripheral base pointers */ -#define LCD_BASE_PTRS { LCD } -/** Interrupt vectors for the LCD peripheral type */ -#define LCD_IRQS { LCD_IRQn } - -/*! - * @} - */ /* end of group LCD_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MRT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer - * @{ - */ - -/** MRT - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x10 */ - __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ - __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ - __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ - __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ - } CHANNEL[4]; - uint8_t RESERVED_0[176]; - __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ - __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ - __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ -} MRT_Type; - -/* ---------------------------------------------------------------------------- - -- MRT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Register_Masks MRT Register Masks - * @{ - */ - -/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ -#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) -#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) -#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) -#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) -#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) - -/* The count of MRT_CHANNEL_INTVAL */ -#define MRT_CHANNEL_INTVAL_COUNT (4U) - -/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ -#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) -#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) - -/* The count of MRT_CHANNEL_TIMER */ -#define MRT_CHANNEL_TIMER_COUNT (4U) - -/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ -#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) -#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) -#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) -#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) -#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) -#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) - -/* The count of MRT_CHANNEL_CTRL */ -#define MRT_CHANNEL_CTRL_COUNT (4U) - -/*! @name CHANNEL_STAT - MRT Status register. */ -#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) -#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) -#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) -#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) -#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) -#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) -#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) -#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) -#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) - -/* The count of MRT_CHANNEL_STAT */ -#define MRT_CHANNEL_STAT_COUNT (4U) - -/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ -#define MRT_MODCFG_NOC_MASK (0xFU) -#define MRT_MODCFG_NOC_SHIFT (0U) -#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) -#define MRT_MODCFG_NOB_MASK (0x1F0U) -#define MRT_MODCFG_NOB_SHIFT (4U) -#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) -#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) -#define MRT_MODCFG_MULTITASK_SHIFT (31U) -#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) - -/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ -#define MRT_IDLE_CH_CHAN_MASK (0xF0U) -#define MRT_IDLE_CH_CHAN_SHIFT (4U) -#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) - -/*! @name IRQ_FLAG - Global interrupt flag register */ -#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) -#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) -#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) -#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) -#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) -#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) -#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) -#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) -#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) -#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) -#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) -#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) - - -/*! - * @} - */ /* end of group MRT_Register_Masks */ - - -/* MRT - Peripheral instance base addresses */ -/** Peripheral MRT0 base address */ -#define MRT0_BASE (0x4000D000u) -/** Peripheral MRT0 base pointer */ -#define MRT0 ((MRT_Type *)MRT0_BASE) -/** Array initializer of MRT peripheral base addresses */ -#define MRT_BASE_ADDRS { MRT0_BASE } -/** Array initializer of MRT peripheral base pointers */ -#define MRT_BASE_PTRS { MRT0 } -/** Interrupt vectors for the MRT peripheral type */ -#define MRT_IRQS { MRT0_IRQn } - -/*! - * @} - */ /* end of group MRT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- OTPC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OTPC_Peripheral_Access_Layer OTPC Peripheral Access Layer - * @{ - */ - -/** OTPC - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[16]; - __I uint32_t AESKEY[8]; /**< Register for reading the AES key., array offset: 0x10, array step: 0x4 */ - __I uint32_t ECRP; /**< ECRP options., offset: 0x30 */ - uint8_t RESERVED_1[4]; - __I uint32_t USER0; /**< User application specific options., offset: 0x38 */ - __I uint32_t USER1; /**< User application specific options., offset: 0x3C */ -} OTPC_Type; - -/* ---------------------------------------------------------------------------- - -- OTPC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OTPC_Register_Masks OTPC Register Masks - * @{ - */ - -/*! @name AESKEY - Register for reading the AES key. */ -#define OTPC_AESKEY_KEY_MASK (0xFFFFFFFFU) -#define OTPC_AESKEY_KEY_SHIFT (0U) -#define OTPC_AESKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << OTPC_AESKEY_KEY_SHIFT)) & OTPC_AESKEY_KEY_MASK) - -/* The count of OTPC_AESKEY */ -#define OTPC_AESKEY_COUNT (8U) - -/*! @name ECRP - ECRP options. */ -#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK (0x10U) -#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT (4U) -#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT)) & OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK) -#define OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK (0x20U) -#define OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT (5U) -#define OTPC_ECRP_IAP_PROTECTION_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT)) & OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK) -#define OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK (0x40U) -#define OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT (6U) -#define OTPC_ECRP_CRP_ISP_DISABLE_PIN(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK) -#define OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK (0x80U) -#define OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT (7U) -#define OTPC_ECRP_CRP_ISP_DISABLE_IAP(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK) -#define OTPC_ECRP_CRP_ALLOW_ZERO_MASK (0x200U) -#define OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT (9U) -#define OTPC_ECRP_CRP_ALLOW_ZERO(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT)) & OTPC_ECRP_CRP_ALLOW_ZERO_MASK) -#define OTPC_ECRP_JTAG_DISABLE_MASK (0x80000000U) -#define OTPC_ECRP_JTAG_DISABLE_SHIFT (31U) -#define OTPC_ECRP_JTAG_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_JTAG_DISABLE_SHIFT)) & OTPC_ECRP_JTAG_DISABLE_MASK) - -/*! @name USER0 - User application specific options. */ -#define OTPC_USER0_USER0_MASK (0xFFFFFFFFU) -#define OTPC_USER0_USER0_SHIFT (0U) -#define OTPC_USER0_USER0(x) (((uint32_t)(((uint32_t)(x)) << OTPC_USER0_USER0_SHIFT)) & OTPC_USER0_USER0_MASK) - -/*! @name USER1 - User application specific options. */ -#define OTPC_USER1_USER1_MASK (0xFFFFFFFFU) -#define OTPC_USER1_USER1_SHIFT (0U) -#define OTPC_USER1_USER1(x) (((uint32_t)(((uint32_t)(x)) << OTPC_USER1_USER1_SHIFT)) & OTPC_USER1_USER1_MASK) - - -/*! - * @} - */ /* end of group OTPC_Register_Masks */ - - -/* OTPC - Peripheral instance base addresses */ -/** Peripheral OTPC base address */ -#define OTPC_BASE (0x40015000u) -/** Peripheral OTPC base pointer */ -#define OTPC ((OTPC_Type *)OTPC_BASE) -/** Array initializer of OTPC peripheral base addresses */ -#define OTPC_BASE_ADDRS { OTPC_BASE } -/** Array initializer of OTPC peripheral base pointers */ -#define OTPC_BASE_PTRS { OTPC } - -/*! - * @} - */ /* end of group OTPC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer - * @{ - */ - -/** PINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ - __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ - __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ - __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ - __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ - __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ - __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ - __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ - __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ - __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ - __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ - __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ - __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ -} PINT_Type; - -/* ---------------------------------------------------------------------------- - -- PINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Register_Masks PINT Register Masks - * @{ - */ - -/*! @name ISEL - Pin Interrupt Mode register */ -#define PINT_ISEL_PMODE_MASK (0xFFU) -#define PINT_ISEL_PMODE_SHIFT (0U) -#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) - -/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ -#define PINT_IENR_ENRL_MASK (0xFFU) -#define PINT_IENR_ENRL_SHIFT (0U) -#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) - -/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ -#define PINT_SIENR_SETENRL_MASK (0xFFU) -#define PINT_SIENR_SETENRL_SHIFT (0U) -#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) - -/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ -#define PINT_CIENR_CENRL_MASK (0xFFU) -#define PINT_CIENR_CENRL_SHIFT (0U) -#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) - -/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ -#define PINT_IENF_ENAF_MASK (0xFFU) -#define PINT_IENF_ENAF_SHIFT (0U) -#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) - -/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ -#define PINT_SIENF_SETENAF_MASK (0xFFU) -#define PINT_SIENF_SETENAF_SHIFT (0U) -#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) - -/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ -#define PINT_CIENF_CENAF_MASK (0xFFU) -#define PINT_CIENF_CENAF_SHIFT (0U) -#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) - -/*! @name RISE - Pin interrupt rising edge register */ -#define PINT_RISE_RDET_MASK (0xFFU) -#define PINT_RISE_RDET_SHIFT (0U) -#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) - -/*! @name FALL - Pin interrupt falling edge register */ -#define PINT_FALL_FDET_MASK (0xFFU) -#define PINT_FALL_FDET_SHIFT (0U) -#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) - -/*! @name IST - Pin interrupt status register */ -#define PINT_IST_PSTAT_MASK (0xFFU) -#define PINT_IST_PSTAT_SHIFT (0U) -#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) - -/*! @name PMCTRL - Pattern match interrupt control register */ -#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) -#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) -#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) -#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) -#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) -#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) -#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) -#define PINT_PMCTRL_PMAT_SHIFT (24U) -#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) - -/*! @name PMSRC - Pattern match interrupt bit-slice source register */ -#define PINT_PMSRC_SRC0_MASK (0x700U) -#define PINT_PMSRC_SRC0_SHIFT (8U) -#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) -#define PINT_PMSRC_SRC1_MASK (0x3800U) -#define PINT_PMSRC_SRC1_SHIFT (11U) -#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) -#define PINT_PMSRC_SRC2_MASK (0x1C000U) -#define PINT_PMSRC_SRC2_SHIFT (14U) -#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) -#define PINT_PMSRC_SRC3_MASK (0xE0000U) -#define PINT_PMSRC_SRC3_SHIFT (17U) -#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) -#define PINT_PMSRC_SRC4_MASK (0x700000U) -#define PINT_PMSRC_SRC4_SHIFT (20U) -#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) -#define PINT_PMSRC_SRC5_MASK (0x3800000U) -#define PINT_PMSRC_SRC5_SHIFT (23U) -#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) -#define PINT_PMSRC_SRC6_MASK (0x1C000000U) -#define PINT_PMSRC_SRC6_SHIFT (26U) -#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) -#define PINT_PMSRC_SRC7_MASK (0xE0000000U) -#define PINT_PMSRC_SRC7_SHIFT (29U) -#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) - -/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ -#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) -#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) -#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) -#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) -#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) -#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) -#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) -#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) -#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) -#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) -#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) -#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) -#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) -#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) -#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) -#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) -#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) -#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) -#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) -#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) -#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) -#define PINT_PMCFG_CFG0_MASK (0x700U) -#define PINT_PMCFG_CFG0_SHIFT (8U) -#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) -#define PINT_PMCFG_CFG1_MASK (0x3800U) -#define PINT_PMCFG_CFG1_SHIFT (11U) -#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) -#define PINT_PMCFG_CFG2_MASK (0x1C000U) -#define PINT_PMCFG_CFG2_SHIFT (14U) -#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) -#define PINT_PMCFG_CFG3_MASK (0xE0000U) -#define PINT_PMCFG_CFG3_SHIFT (17U) -#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) -#define PINT_PMCFG_CFG4_MASK (0x700000U) -#define PINT_PMCFG_CFG4_SHIFT (20U) -#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) -#define PINT_PMCFG_CFG5_MASK (0x3800000U) -#define PINT_PMCFG_CFG5_SHIFT (23U) -#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) -#define PINT_PMCFG_CFG6_MASK (0x1C000000U) -#define PINT_PMCFG_CFG6_SHIFT (26U) -#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) -#define PINT_PMCFG_CFG7_MASK (0xE0000000U) -#define PINT_PMCFG_CFG7_SHIFT (29U) -#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) - - -/*! - * @} - */ /* end of group PINT_Register_Masks */ - - -/* PINT - Peripheral instance base addresses */ -/** Peripheral PINT base address */ -#define PINT_BASE (0x40004000u) -/** Peripheral PINT base pointer */ -#define PINT ((PINT_Type *)PINT_BASE) -/** Array initializer of PINT peripheral base addresses */ -#define PINT_BASE_ADDRS { PINT_BASE } -/** Array initializer of PINT peripheral base pointers */ -#define PINT_BASE_PTRS { PINT } -/** Interrupt vectors for the PINT peripheral type */ -#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn } - -/*! - * @} - */ /* end of group PINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RIT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RIT_Peripheral_Access_Layer RIT Peripheral Access Layer - * @{ - */ - -/** RIT - Register Layout Typedef */ -typedef struct { - __IO uint32_t COMPVAL; /**< Compare value LSB register, offset: 0x0 */ - __IO uint32_t MASK; /**< Mask LSB register, offset: 0x4 */ - __IO uint32_t CTRL; /**< Control register, offset: 0x8 */ - __IO uint32_t COUNTER; /**< Counter LSB register, offset: 0xC */ - __IO uint32_t COMPVAL_H; /**< Compare value MSB register, offset: 0x10 */ - __IO uint32_t MASK_H; /**< Mask MSB register, offset: 0x14 */ - uint8_t RESERVED_0[4]; - __IO uint32_t COUNTER_H; /**< Counter MSB register, offset: 0x1C */ -} RIT_Type; - -/* ---------------------------------------------------------------------------- - -- RIT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RIT_Register_Masks RIT Register Masks - * @{ - */ - -/*! @name COMPVAL - Compare value LSB register */ -#define RIT_COMPVAL_RICOMP_MASK (0xFFFFFFFFU) -#define RIT_COMPVAL_RICOMP_SHIFT (0U) -#define RIT_COMPVAL_RICOMP(x) (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_RICOMP_SHIFT)) & RIT_COMPVAL_RICOMP_MASK) - -/*! @name MASK - Mask LSB register */ -#define RIT_MASK_RIMASK_MASK (0xFFFFFFFFU) -#define RIT_MASK_RIMASK_SHIFT (0U) -#define RIT_MASK_RIMASK(x) (((uint32_t)(((uint32_t)(x)) << RIT_MASK_RIMASK_SHIFT)) & RIT_MASK_RIMASK_MASK) - -/*! @name CTRL - Control register */ -#define RIT_CTRL_RITINT_MASK (0x1U) -#define RIT_CTRL_RITINT_SHIFT (0U) -#define RIT_CTRL_RITINT(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITINT_SHIFT)) & RIT_CTRL_RITINT_MASK) -#define RIT_CTRL_RITENCLR_MASK (0x2U) -#define RIT_CTRL_RITENCLR_SHIFT (1U) -#define RIT_CTRL_RITENCLR(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENCLR_SHIFT)) & RIT_CTRL_RITENCLR_MASK) -#define RIT_CTRL_RITENBR_MASK (0x4U) -#define RIT_CTRL_RITENBR_SHIFT (2U) -#define RIT_CTRL_RITENBR(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENBR_SHIFT)) & RIT_CTRL_RITENBR_MASK) -#define RIT_CTRL_RITEN_MASK (0x8U) -#define RIT_CTRL_RITEN_SHIFT (3U) -#define RIT_CTRL_RITEN(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITEN_SHIFT)) & RIT_CTRL_RITEN_MASK) - -/*! @name COUNTER - Counter LSB register */ -#define RIT_COUNTER_RICOUNTER_MASK (0xFFFFFFFFU) -#define RIT_COUNTER_RICOUNTER_SHIFT (0U) -#define RIT_COUNTER_RICOUNTER(x) (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_RICOUNTER_SHIFT)) & RIT_COUNTER_RICOUNTER_MASK) - -/*! @name COMPVAL_H - Compare value MSB register */ -#define RIT_COMPVAL_H_RICOMP_MASK (0xFFFFU) -#define RIT_COMPVAL_H_RICOMP_SHIFT (0U) -#define RIT_COMPVAL_H_RICOMP(x) (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_H_RICOMP_SHIFT)) & RIT_COMPVAL_H_RICOMP_MASK) - -/*! @name MASK_H - Mask MSB register */ -#define RIT_MASK_H_RIMASK_MASK (0xFFFFU) -#define RIT_MASK_H_RIMASK_SHIFT (0U) -#define RIT_MASK_H_RIMASK(x) (((uint32_t)(((uint32_t)(x)) << RIT_MASK_H_RIMASK_SHIFT)) & RIT_MASK_H_RIMASK_MASK) - -/*! @name COUNTER_H - Counter MSB register */ -#define RIT_COUNTER_H_RICOUNTER_MASK (0xFFFFU) -#define RIT_COUNTER_H_RICOUNTER_SHIFT (0U) -#define RIT_COUNTER_H_RICOUNTER(x) (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_H_RICOUNTER_SHIFT)) & RIT_COUNTER_H_RICOUNTER_MASK) - - -/*! - * @} - */ /* end of group RIT_Register_Masks */ - - -/* RIT - Peripheral instance base addresses */ -/** Peripheral RIT base address */ -#define RIT_BASE (0x4002D000u) -/** Peripheral RIT base pointer */ -#define RIT ((RIT_Type *)RIT_BASE) -/** Array initializer of RIT peripheral base addresses */ -#define RIT_BASE_ADDRS { RIT_BASE } -/** Array initializer of RIT peripheral base pointers */ -#define RIT_BASE_PTRS { RIT } -/** Interrupt vectors for the RIT peripheral type */ -#define RIT_IRQS { RIT_IRQn } - -/*! - * @} - */ /* end of group RIT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RTC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer - * @{ - */ - -/** RTC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ - __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ - __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ - __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ - uint8_t RESERVED_0[48]; - __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */ -} RTC_Type; - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/*! @name CTRL - RTC control register */ -#define RTC_CTRL_SWRESET_MASK (0x1U) -#define RTC_CTRL_SWRESET_SHIFT (0U) -#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) -#define RTC_CTRL_ALARM1HZ_MASK (0x4U) -#define RTC_CTRL_ALARM1HZ_SHIFT (2U) -#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) -#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) -#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) -#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) -#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) -#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) -#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) -#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) -#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) -#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) -#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) -#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) -#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) -#define RTC_CTRL_RTC_EN_MASK (0x80U) -#define RTC_CTRL_RTC_EN_SHIFT (7U) -#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) -#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) -#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) -#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) - -/*! @name MATCH - RTC match register */ -#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) -#define RTC_MATCH_MATVAL_SHIFT (0U) -#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) - -/*! @name COUNT - RTC counter register */ -#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) -#define RTC_COUNT_VAL_SHIFT (0U) -#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) - -/*! @name WAKE - High-resolution/wake-up timer control register */ -#define RTC_WAKE_VAL_MASK (0xFFFFU) -#define RTC_WAKE_VAL_SHIFT (0U) -#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) - -/*! @name GPREG - General Purpose register */ -#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU) -#define RTC_GPREG_GPDATA_SHIFT (0U) -#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK) - -/* The count of RTC_GPREG */ -#define RTC_GPREG_COUNT (8U) - - -/*! - * @} - */ /* end of group RTC_Register_Masks */ - - -/* RTC - Peripheral instance base addresses */ -/** Peripheral RTC base address */ -#define RTC_BASE (0x4002C000u) -/** Peripheral RTC base pointer */ -#define RTC ((RTC_Type *)RTC_BASE) -/** Array initializer of RTC peripheral base addresses */ -#define RTC_BASE_ADDRS { RTC_BASE } -/** Array initializer of RTC peripheral base pointers */ -#define RTC_BASE_PTRS { RTC } -/** Interrupt vectors for the RTC peripheral type */ -#define RTC_IRQS { RTC_IRQn } - -/*! - * @} - */ /* end of group RTC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SCT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer - * @{ - */ - -/** SCT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ - __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ - __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ - __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ - __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ - __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ - uint8_t RESERVED_0[40]; - __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ - __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ - __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ - __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ - __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ - __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ - __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ - __IO uint32_t DMA0REQUEST; /**< SCT DMA request 0 register, offset: 0x5C */ - __IO uint32_t DMA1REQUEST; /**< SCT DMA request 1 register, offset: 0x60 */ - uint8_t RESERVED_1[140]; - __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ - __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ - __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ - __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ - union { /* offset: 0x100 */ - __IO uint32_t SCTCAP[10]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ - __IO uint32_t SCTMATCH[10]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ - }; - uint8_t RESERVED_2[216]; - union { /* offset: 0x200 */ - __IO uint32_t SCTCAPCTRL[10]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ - __IO uint32_t SCTMATCHREL[10]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ - }; - uint8_t RESERVED_3[216]; - struct { /* offset: 0x300, array step: 0x8 */ - __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ - __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ - } EVENT[10]; - uint8_t RESERVED_4[432]; - struct { /* offset: 0x500, array step: 0x8 */ - __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ - __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ - } OUT[10]; -} SCT_Type; - -/* ---------------------------------------------------------------------------- - -- SCT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Register_Masks SCT Register Masks - * @{ - */ - -/*! @name CONFIG - SCT configuration register */ -#define SCT_CONFIG_UNIFY_MASK (0x1U) -#define SCT_CONFIG_UNIFY_SHIFT (0U) -#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) -#define SCT_CONFIG_CLKMODE_MASK (0x6U) -#define SCT_CONFIG_CLKMODE_SHIFT (1U) -#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) -#define SCT_CONFIG_CKSEL_MASK (0x78U) -#define SCT_CONFIG_CKSEL_SHIFT (3U) -#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) -#define SCT_CONFIG_NORELAOD_L_MASK (0x80U) -#define SCT_CONFIG_NORELAOD_L_SHIFT (7U) -#define SCT_CONFIG_NORELAOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK) -#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) -#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) -#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) -#define SCT_CONFIG_INSYNC_MASK (0x1E00U) -#define SCT_CONFIG_INSYNC_SHIFT (9U) -#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) -#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) -#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) -#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) -#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) -#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) -#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) - -/*! @name CTRL - SCT control register */ -#define SCT_CTRL_DOWN_L_MASK (0x1U) -#define SCT_CTRL_DOWN_L_SHIFT (0U) -#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) -#define SCT_CTRL_STOP_L_MASK (0x2U) -#define SCT_CTRL_STOP_L_SHIFT (1U) -#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) -#define SCT_CTRL_HALT_L_MASK (0x4U) -#define SCT_CTRL_HALT_L_SHIFT (2U) -#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) -#define SCT_CTRL_CLRCTR_L_MASK (0x8U) -#define SCT_CTRL_CLRCTR_L_SHIFT (3U) -#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) -#define SCT_CTRL_BIDIR_L_MASK (0x10U) -#define SCT_CTRL_BIDIR_L_SHIFT (4U) -#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) -#define SCT_CTRL_PRE_L_MASK (0x1FE0U) -#define SCT_CTRL_PRE_L_SHIFT (5U) -#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) -#define SCT_CTRL_DOWN_H_MASK (0x10000U) -#define SCT_CTRL_DOWN_H_SHIFT (16U) -#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) -#define SCT_CTRL_STOP_H_MASK (0x20000U) -#define SCT_CTRL_STOP_H_SHIFT (17U) -#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) -#define SCT_CTRL_HALT_H_MASK (0x40000U) -#define SCT_CTRL_HALT_H_SHIFT (18U) -#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) -#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) -#define SCT_CTRL_CLRCTR_H_SHIFT (19U) -#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) -#define SCT_CTRL_BIDIR_H_MASK (0x100000U) -#define SCT_CTRL_BIDIR_H_SHIFT (20U) -#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) -#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) -#define SCT_CTRL_PRE_H_SHIFT (21U) -#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) - -/*! @name LIMIT - SCT limit event select register */ -#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) -#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) -#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) -#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) -#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) -#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) - -/*! @name HALT - SCT halt event select register */ -#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) -#define SCT_HALT_HALTMSK_L_SHIFT (0U) -#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) -#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) -#define SCT_HALT_HALTMSK_H_SHIFT (16U) -#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) - -/*! @name STOP - SCT stop event select register */ -#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) -#define SCT_STOP_STOPMSK_L_SHIFT (0U) -#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) -#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) -#define SCT_STOP_STOPMSK_H_SHIFT (16U) -#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) - -/*! @name START - SCT start event select register */ -#define SCT_START_STARTMSK_L_MASK (0xFFFFU) -#define SCT_START_STARTMSK_L_SHIFT (0U) -#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) -#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) -#define SCT_START_STARTMSK_H_SHIFT (16U) -#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) - -/*! @name COUNT - SCT counter register */ -#define SCT_COUNT_CTR_L_MASK (0xFFFFU) -#define SCT_COUNT_CTR_L_SHIFT (0U) -#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) -#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) -#define SCT_COUNT_CTR_H_SHIFT (16U) -#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) - -/*! @name STATE - SCT state register */ -#define SCT_STATE_STATE_L_MASK (0x1FU) -#define SCT_STATE_STATE_L_SHIFT (0U) -#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) -#define SCT_STATE_STATE_H_MASK (0x1F0000U) -#define SCT_STATE_STATE_H_SHIFT (16U) -#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) - -/*! @name INPUT - SCT input register */ -#define SCT_INPUT_AIN0_MASK (0x1U) -#define SCT_INPUT_AIN0_SHIFT (0U) -#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) -#define SCT_INPUT_AIN1_MASK (0x2U) -#define SCT_INPUT_AIN1_SHIFT (1U) -#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) -#define SCT_INPUT_AIN2_MASK (0x4U) -#define SCT_INPUT_AIN2_SHIFT (2U) -#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) -#define SCT_INPUT_AIN3_MASK (0x8U) -#define SCT_INPUT_AIN3_SHIFT (3U) -#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) -#define SCT_INPUT_AIN4_MASK (0x10U) -#define SCT_INPUT_AIN4_SHIFT (4U) -#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) -#define SCT_INPUT_AIN5_MASK (0x20U) -#define SCT_INPUT_AIN5_SHIFT (5U) -#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) -#define SCT_INPUT_AIN6_MASK (0x40U) -#define SCT_INPUT_AIN6_SHIFT (6U) -#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) -#define SCT_INPUT_AIN7_MASK (0x80U) -#define SCT_INPUT_AIN7_SHIFT (7U) -#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) -#define SCT_INPUT_AIN8_MASK (0x100U) -#define SCT_INPUT_AIN8_SHIFT (8U) -#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) -#define SCT_INPUT_AIN9_MASK (0x200U) -#define SCT_INPUT_AIN9_SHIFT (9U) -#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) -#define SCT_INPUT_AIN10_MASK (0x400U) -#define SCT_INPUT_AIN10_SHIFT (10U) -#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) -#define SCT_INPUT_AIN11_MASK (0x800U) -#define SCT_INPUT_AIN11_SHIFT (11U) -#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) -#define SCT_INPUT_AIN12_MASK (0x1000U) -#define SCT_INPUT_AIN12_SHIFT (12U) -#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) -#define SCT_INPUT_AIN13_MASK (0x2000U) -#define SCT_INPUT_AIN13_SHIFT (13U) -#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) -#define SCT_INPUT_AIN14_MASK (0x4000U) -#define SCT_INPUT_AIN14_SHIFT (14U) -#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) -#define SCT_INPUT_AIN15_MASK (0x8000U) -#define SCT_INPUT_AIN15_SHIFT (15U) -#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) -#define SCT_INPUT_SIN0_MASK (0x10000U) -#define SCT_INPUT_SIN0_SHIFT (16U) -#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) -#define SCT_INPUT_SIN1_MASK (0x20000U) -#define SCT_INPUT_SIN1_SHIFT (17U) -#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) -#define SCT_INPUT_SIN2_MASK (0x40000U) -#define SCT_INPUT_SIN2_SHIFT (18U) -#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) -#define SCT_INPUT_SIN3_MASK (0x80000U) -#define SCT_INPUT_SIN3_SHIFT (19U) -#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) -#define SCT_INPUT_SIN4_MASK (0x100000U) -#define SCT_INPUT_SIN4_SHIFT (20U) -#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) -#define SCT_INPUT_SIN5_MASK (0x200000U) -#define SCT_INPUT_SIN5_SHIFT (21U) -#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) -#define SCT_INPUT_SIN6_MASK (0x400000U) -#define SCT_INPUT_SIN6_SHIFT (22U) -#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) -#define SCT_INPUT_SIN7_MASK (0x800000U) -#define SCT_INPUT_SIN7_SHIFT (23U) -#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) -#define SCT_INPUT_SIN8_MASK (0x1000000U) -#define SCT_INPUT_SIN8_SHIFT (24U) -#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) -#define SCT_INPUT_SIN9_MASK (0x2000000U) -#define SCT_INPUT_SIN9_SHIFT (25U) -#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) -#define SCT_INPUT_SIN10_MASK (0x4000000U) -#define SCT_INPUT_SIN10_SHIFT (26U) -#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) -#define SCT_INPUT_SIN11_MASK (0x8000000U) -#define SCT_INPUT_SIN11_SHIFT (27U) -#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) -#define SCT_INPUT_SIN12_MASK (0x10000000U) -#define SCT_INPUT_SIN12_SHIFT (28U) -#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) -#define SCT_INPUT_SIN13_MASK (0x20000000U) -#define SCT_INPUT_SIN13_SHIFT (29U) -#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) -#define SCT_INPUT_SIN14_MASK (0x40000000U) -#define SCT_INPUT_SIN14_SHIFT (30U) -#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) -#define SCT_INPUT_SIN15_MASK (0x80000000U) -#define SCT_INPUT_SIN15_SHIFT (31U) -#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) - -/*! @name REGMODE - SCT match/capture mode register */ -#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) -#define SCT_REGMODE_REGMOD_L_SHIFT (0U) -#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) -#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) -#define SCT_REGMODE_REGMOD_H_SHIFT (16U) -#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) - -/*! @name OUTPUT - SCT output register */ -#define SCT_OUTPUT_OUT_MASK (0xFFFFU) -#define SCT_OUTPUT_OUT_SHIFT (0U) -#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) - -/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ -#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) -#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) -#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) -#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) -#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) -#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) -#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) -#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) -#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) -#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) -#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) -#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) -#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) -#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) -#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) -#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) -#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) -#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) -#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) -#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) -#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) -#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) -#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) -#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) -#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) -#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) -#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) -#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) -#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) - -/*! @name RES - SCT conflict resolution register */ -#define SCT_RES_O0RES_MASK (0x3U) -#define SCT_RES_O0RES_SHIFT (0U) -#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) -#define SCT_RES_O1RES_MASK (0xCU) -#define SCT_RES_O1RES_SHIFT (2U) -#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) -#define SCT_RES_O2RES_MASK (0x30U) -#define SCT_RES_O2RES_SHIFT (4U) -#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) -#define SCT_RES_O3RES_MASK (0xC0U) -#define SCT_RES_O3RES_SHIFT (6U) -#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) -#define SCT_RES_O4RES_MASK (0x300U) -#define SCT_RES_O4RES_SHIFT (8U) -#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) -#define SCT_RES_O5RES_MASK (0xC00U) -#define SCT_RES_O5RES_SHIFT (10U) -#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) -#define SCT_RES_O6RES_MASK (0x3000U) -#define SCT_RES_O6RES_SHIFT (12U) -#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) -#define SCT_RES_O7RES_MASK (0xC000U) -#define SCT_RES_O7RES_SHIFT (14U) -#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) -#define SCT_RES_O8RES_MASK (0x30000U) -#define SCT_RES_O8RES_SHIFT (16U) -#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) -#define SCT_RES_O9RES_MASK (0xC0000U) -#define SCT_RES_O9RES_SHIFT (18U) -#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) -#define SCT_RES_O10RES_MASK (0x300000U) -#define SCT_RES_O10RES_SHIFT (20U) -#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) -#define SCT_RES_O11RES_MASK (0xC00000U) -#define SCT_RES_O11RES_SHIFT (22U) -#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) -#define SCT_RES_O12RES_MASK (0x3000000U) -#define SCT_RES_O12RES_SHIFT (24U) -#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) -#define SCT_RES_O13RES_MASK (0xC000000U) -#define SCT_RES_O13RES_SHIFT (26U) -#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) -#define SCT_RES_O14RES_MASK (0x30000000U) -#define SCT_RES_O14RES_SHIFT (28U) -#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) -#define SCT_RES_O15RES_MASK (0xC0000000U) -#define SCT_RES_O15RES_SHIFT (30U) -#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) - -/*! @name DMA0REQUEST - SCT DMA request 0 register */ -#define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU) -#define SCT_DMA0REQUEST_DEV_0_SHIFT (0U) -#define SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK) -#define SCT_DMA0REQUEST_DRL0_MASK (0x40000000U) -#define SCT_DMA0REQUEST_DRL0_SHIFT (30U) -#define SCT_DMA0REQUEST_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK) -#define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U) -#define SCT_DMA0REQUEST_DRQ0_SHIFT (31U) -#define SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK) - -/*! @name DMA1REQUEST - SCT DMA request 1 register */ -#define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU) -#define SCT_DMA1REQUEST_DEV_1_SHIFT (0U) -#define SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK) -#define SCT_DMA1REQUEST_DRL1_MASK (0x40000000U) -#define SCT_DMA1REQUEST_DRL1_SHIFT (30U) -#define SCT_DMA1REQUEST_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK) -#define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U) -#define SCT_DMA1REQUEST_DRQ1_SHIFT (31U) -#define SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK) - -/*! @name EVEN - SCT event interrupt enable register */ -#define SCT_EVEN_IEN_MASK (0xFFFFU) -#define SCT_EVEN_IEN_SHIFT (0U) -#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) - -/*! @name EVFLAG - SCT event flag register */ -#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) -#define SCT_EVFLAG_FLAG_SHIFT (0U) -#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) - -/*! @name CONEN - SCT conflict interrupt enable register */ -#define SCT_CONEN_NCEN_MASK (0xFFFFU) -#define SCT_CONEN_NCEN_SHIFT (0U) -#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) - -/*! @name CONFLAG - SCT conflict flag register */ -#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) -#define SCT_CONFLAG_NCFLAG_SHIFT (0U) -#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) -#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) -#define SCT_CONFLAG_BUSERRL_SHIFT (30U) -#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) -#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) -#define SCT_CONFLAG_BUSERRH_SHIFT (31U) -#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) - -/*! @name SCTCAP - SCT capture register of capture channel */ -#define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU) -#define SCT_SCTCAP_CAPn_L_SHIFT (0U) -#define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK) -#define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U) -#define SCT_SCTCAP_CAPn_H_SHIFT (16U) -#define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK) - -/* The count of SCT_SCTCAP */ -#define SCT_SCTCAP_COUNT (10U) - -/*! @name SCTMATCH - SCT match value register of match channels */ -#define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU) -#define SCT_SCTMATCH_MATCHn_L_SHIFT (0U) -#define SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK) -#define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U) -#define SCT_SCTMATCH_MATCHn_H_SHIFT (16U) -#define SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK) - -/* The count of SCT_SCTMATCH */ -#define SCT_SCTMATCH_COUNT (10U) - -/*! @name SCTCAPCTRL - SCT capture control register */ -#define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU) -#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U) -#define SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK) -#define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) -#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U) -#define SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK) - -/* The count of SCT_SCTCAPCTRL */ -#define SCT_SCTCAPCTRL_COUNT (10U) - -/*! @name SCTMATCHREL - SCT match reload value register */ -#define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU) -#define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U) -#define SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK) -#define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U) -#define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U) -#define SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK) - -/* The count of SCT_SCTMATCHREL */ -#define SCT_SCTMATCHREL_COUNT (10U) - -/*! @name EVENT_STATE - SCT event state register 0 */ -#define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU) -#define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U) -#define SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK) - -/* The count of SCT_EVENT_STATE */ -#define SCT_EVENT_STATE_COUNT (10U) - -/*! @name EVENT_CTRL - SCT event control register 0 */ -#define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU) -#define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U) -#define SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK) -#define SCT_EVENT_CTRL_HEVENT_MASK (0x10U) -#define SCT_EVENT_CTRL_HEVENT_SHIFT (4U) -#define SCT_EVENT_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK) -#define SCT_EVENT_CTRL_OUTSEL_MASK (0x20U) -#define SCT_EVENT_CTRL_OUTSEL_SHIFT (5U) -#define SCT_EVENT_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK) -#define SCT_EVENT_CTRL_IOSEL_MASK (0x3C0U) -#define SCT_EVENT_CTRL_IOSEL_SHIFT (6U) -#define SCT_EVENT_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK) -#define SCT_EVENT_CTRL_IOCOND_MASK (0xC00U) -#define SCT_EVENT_CTRL_IOCOND_SHIFT (10U) -#define SCT_EVENT_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK) -#define SCT_EVENT_CTRL_COMBMODE_MASK (0x3000U) -#define SCT_EVENT_CTRL_COMBMODE_SHIFT (12U) -#define SCT_EVENT_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK) -#define SCT_EVENT_CTRL_STATELD_MASK (0x4000U) -#define SCT_EVENT_CTRL_STATELD_SHIFT (14U) -#define SCT_EVENT_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK) -#define SCT_EVENT_CTRL_STATEV_MASK (0xF8000U) -#define SCT_EVENT_CTRL_STATEV_SHIFT (15U) -#define SCT_EVENT_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK) -#define SCT_EVENT_CTRL_MATCHMEM_MASK (0x100000U) -#define SCT_EVENT_CTRL_MATCHMEM_SHIFT (20U) -#define SCT_EVENT_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK) -#define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U) -#define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U) -#define SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK) - -/* The count of SCT_EVENT_CTRL */ -#define SCT_EVENT_CTRL_COUNT (10U) - -/*! @name OUT_SET - SCT output 0 set register */ -#define SCT_OUT_SET_SET_MASK (0xFFFFU) -#define SCT_OUT_SET_SET_SHIFT (0U) -#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) - -/* The count of SCT_OUT_SET */ -#define SCT_OUT_SET_COUNT (10U) - -/*! @name OUT_CLR - SCT output 0 clear register */ -#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) -#define SCT_OUT_CLR_CLR_SHIFT (0U) -#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) - -/* The count of SCT_OUT_CLR */ -#define SCT_OUT_CLR_COUNT (10U) - - -/*! - * @} - */ /* end of group SCT_Register_Masks */ - - -/* SCT - Peripheral instance base addresses */ -/** Peripheral SCT0 base address */ -#define SCT0_BASE (0x40085000u) -/** Peripheral SCT0 base pointer */ -#define SCT0 ((SCT_Type *)SCT0_BASE) -/** Array initializer of SCT peripheral base addresses */ -#define SCT_BASE_ADDRS { SCT0_BASE } -/** Array initializer of SCT peripheral base pointers */ -#define SCT_BASE_PTRS { SCT0 } -/** Interrupt vectors for the SCT peripheral type */ -#define SCT_IRQS { SCT0_IRQn } - -/*! - * @} - */ /* end of group SCT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SDIF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer - * @{ - */ - -/** SDIF - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register, offset: 0x0 */ - __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */ - __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */ - __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */ - __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */ - __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */ - __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */ - __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */ - __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */ - __IO uint32_t CMD; /**< Command register, offset: 0x2C */ - __IO uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */ - __IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */ - __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */ - __IO uint32_t STATUS; /**< Status register, offset: 0x48 */ - __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */ - __IO uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */ - __IO uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */ - uint8_t RESERVED_1[4]; - __IO uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */ - __IO uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */ - __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */ - uint8_t RESERVED_2[16]; - __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */ - uint8_t RESERVED_3[4]; - __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */ - __IO uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */ - __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */ - __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */ - __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */ - __IO uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */ - __IO uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */ - uint8_t RESERVED_4[100]; - __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */ - __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */ - uint8_t RESERVED_5[248]; - __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */ -} SDIF_Type; - -/* ---------------------------------------------------------------------------- - -- SDIF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDIF_Register_Masks SDIF Register Masks - * @{ - */ - -/*! @name CTRL - Control register */ -#define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U) -#define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U) -#define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK) -#define SDIF_CTRL_FIFO_RESET_MASK (0x2U) -#define SDIF_CTRL_FIFO_RESET_SHIFT (1U) -#define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK) -#define SDIF_CTRL_DMA_RESET_MASK (0x4U) -#define SDIF_CTRL_DMA_RESET_SHIFT (2U) -#define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK) -#define SDIF_CTRL_INT_ENABLE_MASK (0x10U) -#define SDIF_CTRL_INT_ENABLE_SHIFT (4U) -#define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK) -#define SDIF_CTRL_READ_WAIT_MASK (0x40U) -#define SDIF_CTRL_READ_WAIT_SHIFT (6U) -#define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK) -#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U) -#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U) -#define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK) -#define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U) -#define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U) -#define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK) -#define SDIF_CTRL_SEND_CCSD_MASK (0x200U) -#define SDIF_CTRL_SEND_CCSD_SHIFT (9U) -#define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK) -#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U) -#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U) -#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK) -#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U) -#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U) -#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK) -#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U) -#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U) -#define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK) -#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U) -#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U) -#define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK) -#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U) -#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U) -#define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK) -#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U) -#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U) -#define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) - -/*! @name PWREN - Power Enable register */ -#define SDIF_PWREN_POWER_ENABLE_MASK (0x1U) -#define SDIF_PWREN_POWER_ENABLE_SHIFT (0U) -#define SDIF_PWREN_POWER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE_SHIFT)) & SDIF_PWREN_POWER_ENABLE_MASK) - -/*! @name CLKDIV - Clock Divider register */ -#define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU) -#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U) -#define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK) - -/*! @name CLKENA - Clock Enable register */ -#define SDIF_CLKENA_CCLK_ENABLE_MASK (0x1U) -#define SDIF_CLKENA_CCLK_ENABLE_SHIFT (0U) -#define SDIF_CLKENA_CCLK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK_ENABLE_MASK) -#define SDIF_CLKENA_CCLK_LOW_POWER_MASK (0x10000U) -#define SDIF_CLKENA_CCLK_LOW_POWER_SHIFT (16U) -#define SDIF_CLKENA_CCLK_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK_LOW_POWER_MASK) - -/*! @name TMOUT - Time-out register */ -#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU) -#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U) -#define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK) -#define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U) -#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U) -#define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK) - -/*! @name CTYPE - Card Type register */ -#define SDIF_CTYPE_CARD_WIDTH0_MASK (0x1U) -#define SDIF_CTYPE_CARD_WIDTH0_SHIFT (0U) -#define SDIF_CTYPE_CARD_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD_WIDTH0_MASK) -#define SDIF_CTYPE_CARD_WIDTH1_MASK (0x10000U) -#define SDIF_CTYPE_CARD_WIDTH1_SHIFT (16U) -#define SDIF_CTYPE_CARD_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD_WIDTH1_MASK) - -/*! @name BLKSIZ - Block Size register */ -#define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU) -#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U) -#define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK) - -/*! @name BYTCNT - Byte Count register */ -#define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU) -#define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U) -#define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK) - -/*! @name INTMASK - Interrupt Mask register */ -#define SDIF_INTMASK_CDET_MASK (0x1U) -#define SDIF_INTMASK_CDET_SHIFT (0U) -#define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK) -#define SDIF_INTMASK_RE_MASK (0x2U) -#define SDIF_INTMASK_RE_SHIFT (1U) -#define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK) -#define SDIF_INTMASK_CDONE_MASK (0x4U) -#define SDIF_INTMASK_CDONE_SHIFT (2U) -#define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK) -#define SDIF_INTMASK_DTO_MASK (0x8U) -#define SDIF_INTMASK_DTO_SHIFT (3U) -#define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK) -#define SDIF_INTMASK_TXDR_MASK (0x10U) -#define SDIF_INTMASK_TXDR_SHIFT (4U) -#define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK) -#define SDIF_INTMASK_RXDR_MASK (0x20U) -#define SDIF_INTMASK_RXDR_SHIFT (5U) -#define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK) -#define SDIF_INTMASK_RCRC_MASK (0x40U) -#define SDIF_INTMASK_RCRC_SHIFT (6U) -#define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK) -#define SDIF_INTMASK_DCRC_MASK (0x80U) -#define SDIF_INTMASK_DCRC_SHIFT (7U) -#define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK) -#define SDIF_INTMASK_RTO_MASK (0x100U) -#define SDIF_INTMASK_RTO_SHIFT (8U) -#define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK) -#define SDIF_INTMASK_DRTO_MASK (0x200U) -#define SDIF_INTMASK_DRTO_SHIFT (9U) -#define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK) -#define SDIF_INTMASK_HTO_MASK (0x400U) -#define SDIF_INTMASK_HTO_SHIFT (10U) -#define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK) -#define SDIF_INTMASK_FRUN_MASK (0x800U) -#define SDIF_INTMASK_FRUN_SHIFT (11U) -#define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK) -#define SDIF_INTMASK_HLE_MASK (0x1000U) -#define SDIF_INTMASK_HLE_SHIFT (12U) -#define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK) -#define SDIF_INTMASK_SBE_MASK (0x2000U) -#define SDIF_INTMASK_SBE_SHIFT (13U) -#define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK) -#define SDIF_INTMASK_ACD_MASK (0x4000U) -#define SDIF_INTMASK_ACD_SHIFT (14U) -#define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK) -#define SDIF_INTMASK_EBE_MASK (0x8000U) -#define SDIF_INTMASK_EBE_SHIFT (15U) -#define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK) -#define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U) -#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U) -#define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK) - -/*! @name CMDARG - Command Argument register */ -#define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU) -#define SDIF_CMDARG_CMD_ARG_SHIFT (0U) -#define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK) - -/*! @name CMD - Command register */ -#define SDIF_CMD_CMD_INDEX_MASK (0x3FU) -#define SDIF_CMD_CMD_INDEX_SHIFT (0U) -#define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK) -#define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U) -#define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U) -#define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK) -#define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U) -#define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U) -#define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK) -#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U) -#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U) -#define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK) -#define SDIF_CMD_DATA_EXPECTED_MASK (0x200U) -#define SDIF_CMD_DATA_EXPECTED_SHIFT (9U) -#define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK) -#define SDIF_CMD_READ_WRITE_MASK (0x400U) -#define SDIF_CMD_READ_WRITE_SHIFT (10U) -#define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK) -#define SDIF_CMD_TRANSFER_MODE_MASK (0x800U) -#define SDIF_CMD_TRANSFER_MODE_SHIFT (11U) -#define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK) -#define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U) -#define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U) -#define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK) -#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U) -#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U) -#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK) -#define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U) -#define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U) -#define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK) -#define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U) -#define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U) -#define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK) -#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U) -#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U) -#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK) -#define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U) -#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U) -#define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK) -#define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U) -#define SDIF_CMD_CCS_EXPECTED_SHIFT (23U) -#define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK) -#define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U) -#define SDIF_CMD_ENABLE_BOOT_SHIFT (24U) -#define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK) -#define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U) -#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U) -#define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK) -#define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U) -#define SDIF_CMD_DISABLE_BOOT_SHIFT (26U) -#define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK) -#define SDIF_CMD_BOOT_MODE_MASK (0x8000000U) -#define SDIF_CMD_BOOT_MODE_SHIFT (27U) -#define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK) -#define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U) -#define SDIF_CMD_VOLT_SWITCH_SHIFT (28U) -#define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK) -#define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U) -#define SDIF_CMD_USE_HOLD_REG_SHIFT (29U) -#define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK) -#define SDIF_CMD_START_CMD_MASK (0x80000000U) -#define SDIF_CMD_START_CMD_SHIFT (31U) -#define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK) - -/*! @name RESP - Response register */ -#define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU) -#define SDIF_RESP_RESPONSE_SHIFT (0U) -#define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK) - -/* The count of SDIF_RESP */ -#define SDIF_RESP_COUNT (4U) - -/*! @name MINTSTS - Masked Interrupt Status register */ -#define SDIF_MINTSTS_CDET_MASK (0x1U) -#define SDIF_MINTSTS_CDET_SHIFT (0U) -#define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK) -#define SDIF_MINTSTS_RE_MASK (0x2U) -#define SDIF_MINTSTS_RE_SHIFT (1U) -#define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK) -#define SDIF_MINTSTS_CDONE_MASK (0x4U) -#define SDIF_MINTSTS_CDONE_SHIFT (2U) -#define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK) -#define SDIF_MINTSTS_DTO_MASK (0x8U) -#define SDIF_MINTSTS_DTO_SHIFT (3U) -#define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK) -#define SDIF_MINTSTS_TXDR_MASK (0x10U) -#define SDIF_MINTSTS_TXDR_SHIFT (4U) -#define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK) -#define SDIF_MINTSTS_RXDR_MASK (0x20U) -#define SDIF_MINTSTS_RXDR_SHIFT (5U) -#define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK) -#define SDIF_MINTSTS_RCRC_MASK (0x40U) -#define SDIF_MINTSTS_RCRC_SHIFT (6U) -#define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK) -#define SDIF_MINTSTS_DCRC_MASK (0x80U) -#define SDIF_MINTSTS_DCRC_SHIFT (7U) -#define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK) -#define SDIF_MINTSTS_RTO_MASK (0x100U) -#define SDIF_MINTSTS_RTO_SHIFT (8U) -#define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK) -#define SDIF_MINTSTS_DRTO_MASK (0x200U) -#define SDIF_MINTSTS_DRTO_SHIFT (9U) -#define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK) -#define SDIF_MINTSTS_HTO_MASK (0x400U) -#define SDIF_MINTSTS_HTO_SHIFT (10U) -#define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK) -#define SDIF_MINTSTS_FRUN_MASK (0x800U) -#define SDIF_MINTSTS_FRUN_SHIFT (11U) -#define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK) -#define SDIF_MINTSTS_HLE_MASK (0x1000U) -#define SDIF_MINTSTS_HLE_SHIFT (12U) -#define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK) -#define SDIF_MINTSTS_SBE_MASK (0x2000U) -#define SDIF_MINTSTS_SBE_SHIFT (13U) -#define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK) -#define SDIF_MINTSTS_ACD_MASK (0x4000U) -#define SDIF_MINTSTS_ACD_SHIFT (14U) -#define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK) -#define SDIF_MINTSTS_EBE_MASK (0x8000U) -#define SDIF_MINTSTS_EBE_SHIFT (15U) -#define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK) -#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U) -#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U) -#define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK) - -/*! @name RINTSTS - Raw Interrupt Status register */ -#define SDIF_RINTSTS_CDET_MASK (0x1U) -#define SDIF_RINTSTS_CDET_SHIFT (0U) -#define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK) -#define SDIF_RINTSTS_RE_MASK (0x2U) -#define SDIF_RINTSTS_RE_SHIFT (1U) -#define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK) -#define SDIF_RINTSTS_CDONE_MASK (0x4U) -#define SDIF_RINTSTS_CDONE_SHIFT (2U) -#define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK) -#define SDIF_RINTSTS_DTO_MASK (0x8U) -#define SDIF_RINTSTS_DTO_SHIFT (3U) -#define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK) -#define SDIF_RINTSTS_TXDR_MASK (0x10U) -#define SDIF_RINTSTS_TXDR_SHIFT (4U) -#define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK) -#define SDIF_RINTSTS_RXDR_MASK (0x20U) -#define SDIF_RINTSTS_RXDR_SHIFT (5U) -#define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK) -#define SDIF_RINTSTS_RCRC_MASK (0x40U) -#define SDIF_RINTSTS_RCRC_SHIFT (6U) -#define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK) -#define SDIF_RINTSTS_DCRC_MASK (0x80U) -#define SDIF_RINTSTS_DCRC_SHIFT (7U) -#define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK) -#define SDIF_RINTSTS_RTO_BAR_MASK (0x100U) -#define SDIF_RINTSTS_RTO_BAR_SHIFT (8U) -#define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK) -#define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U) -#define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U) -#define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK) -#define SDIF_RINTSTS_HTO_MASK (0x400U) -#define SDIF_RINTSTS_HTO_SHIFT (10U) -#define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK) -#define SDIF_RINTSTS_FRUN_MASK (0x800U) -#define SDIF_RINTSTS_FRUN_SHIFT (11U) -#define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK) -#define SDIF_RINTSTS_HLE_MASK (0x1000U) -#define SDIF_RINTSTS_HLE_SHIFT (12U) -#define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK) -#define SDIF_RINTSTS_SBE_MASK (0x2000U) -#define SDIF_RINTSTS_SBE_SHIFT (13U) -#define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK) -#define SDIF_RINTSTS_ACD_MASK (0x4000U) -#define SDIF_RINTSTS_ACD_SHIFT (14U) -#define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK) -#define SDIF_RINTSTS_EBE_MASK (0x8000U) -#define SDIF_RINTSTS_EBE_SHIFT (15U) -#define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK) -#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U) -#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U) -#define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK) - -/*! @name STATUS - Status register */ -#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U) -#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U) -#define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK) -#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U) -#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U) -#define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK) -#define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U) -#define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U) -#define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK) -#define SDIF_STATUS_FIFO_FULL_MASK (0x8U) -#define SDIF_STATUS_FIFO_FULL_SHIFT (3U) -#define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK) -#define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U) -#define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U) -#define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK) -#define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U) -#define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U) -#define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK) -#define SDIF_STATUS_DATA_BUSY_MASK (0x200U) -#define SDIF_STATUS_DATA_BUSY_SHIFT (9U) -#define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK) -#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U) -#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U) -#define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK) -#define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) -#define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U) -#define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK) -#define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U) -#define SDIF_STATUS_FIFO_COUNT_SHIFT (17U) -#define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK) -#define SDIF_STATUS_DMA_ACK_MASK (0x40000000U) -#define SDIF_STATUS_DMA_ACK_SHIFT (30U) -#define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK) -#define SDIF_STATUS_DMA_REQ_MASK (0x80000000U) -#define SDIF_STATUS_DMA_REQ_SHIFT (31U) -#define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK) - -/*! @name FIFOTH - FIFO Threshold Watermark register */ -#define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU) -#define SDIF_FIFOTH_TX_WMARK_SHIFT (0U) -#define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK) -#define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U) -#define SDIF_FIFOTH_RX_WMARK_SHIFT (16U) -#define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK) -#define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U) -#define SDIF_FIFOTH_DMA_MTS_SHIFT (28U) -#define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK) - -/*! @name CDETECT - Card Detect register */ -#define SDIF_CDETECT_CARD_DETECT_MASK (0x1U) -#define SDIF_CDETECT_CARD_DETECT_SHIFT (0U) -#define SDIF_CDETECT_CARD_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD_DETECT_SHIFT)) & SDIF_CDETECT_CARD_DETECT_MASK) - -/*! @name WRTPRT - Write Protect register */ -#define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U) -#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U) -#define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK) - -/*! @name TCBCNT - Transferred CIU Card Byte Count register */ -#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU) -#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U) -#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK) - -/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */ -#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU) -#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U) -#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK) - -/*! @name DEBNCE - Debounce Count register */ -#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU) -#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U) -#define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK) - -/*! @name RST_N - Hardware Reset */ -#define SDIF_RST_N_CARD_RESET_MASK (0x1U) -#define SDIF_RST_N_CARD_RESET_SHIFT (0U) -#define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK) - -/*! @name BMOD - Bus Mode register */ -#define SDIF_BMOD_SWR_MASK (0x1U) -#define SDIF_BMOD_SWR_SHIFT (0U) -#define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK) -#define SDIF_BMOD_FB_MASK (0x2U) -#define SDIF_BMOD_FB_SHIFT (1U) -#define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK) -#define SDIF_BMOD_DSL_MASK (0x7CU) -#define SDIF_BMOD_DSL_SHIFT (2U) -#define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK) -#define SDIF_BMOD_DE_MASK (0x80U) -#define SDIF_BMOD_DE_SHIFT (7U) -#define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK) -#define SDIF_BMOD_PBL_MASK (0x700U) -#define SDIF_BMOD_PBL_SHIFT (8U) -#define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK) - -/*! @name PLDMND - Poll Demand register */ -#define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU) -#define SDIF_PLDMND_PD_SHIFT (0U) -#define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK) - -/*! @name DBADDR - Descriptor List Base Address register */ -#define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU) -#define SDIF_DBADDR_SDL_SHIFT (0U) -#define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK) - -/*! @name IDSTS - Internal DMAC Status register */ -#define SDIF_IDSTS_TI_MASK (0x1U) -#define SDIF_IDSTS_TI_SHIFT (0U) -#define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK) -#define SDIF_IDSTS_RI_MASK (0x2U) -#define SDIF_IDSTS_RI_SHIFT (1U) -#define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK) -#define SDIF_IDSTS_FBE_MASK (0x4U) -#define SDIF_IDSTS_FBE_SHIFT (2U) -#define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK) -#define SDIF_IDSTS_DU_MASK (0x10U) -#define SDIF_IDSTS_DU_SHIFT (4U) -#define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK) -#define SDIF_IDSTS_CES_MASK (0x20U) -#define SDIF_IDSTS_CES_SHIFT (5U) -#define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK) -#define SDIF_IDSTS_NIS_MASK (0x100U) -#define SDIF_IDSTS_NIS_SHIFT (8U) -#define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK) -#define SDIF_IDSTS_AIS_MASK (0x200U) -#define SDIF_IDSTS_AIS_SHIFT (9U) -#define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK) -#define SDIF_IDSTS_EB_MASK (0x1C00U) -#define SDIF_IDSTS_EB_SHIFT (10U) -#define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK) -#define SDIF_IDSTS_FSM_MASK (0x1E000U) -#define SDIF_IDSTS_FSM_SHIFT (13U) -#define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK) - -/*! @name IDINTEN - Internal DMAC Interrupt Enable register */ -#define SDIF_IDINTEN_TI_MASK (0x1U) -#define SDIF_IDINTEN_TI_SHIFT (0U) -#define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK) -#define SDIF_IDINTEN_RI_MASK (0x2U) -#define SDIF_IDINTEN_RI_SHIFT (1U) -#define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK) -#define SDIF_IDINTEN_FBE_MASK (0x4U) -#define SDIF_IDINTEN_FBE_SHIFT (2U) -#define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK) -#define SDIF_IDINTEN_DU_MASK (0x10U) -#define SDIF_IDINTEN_DU_SHIFT (4U) -#define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK) -#define SDIF_IDINTEN_CES_MASK (0x20U) -#define SDIF_IDINTEN_CES_SHIFT (5U) -#define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK) -#define SDIF_IDINTEN_NIS_MASK (0x100U) -#define SDIF_IDINTEN_NIS_SHIFT (8U) -#define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK) -#define SDIF_IDINTEN_AIS_MASK (0x200U) -#define SDIF_IDINTEN_AIS_SHIFT (9U) -#define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK) - -/*! @name DSCADDR - Current Host Descriptor Address register */ -#define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU) -#define SDIF_DSCADDR_HDA_SHIFT (0U) -#define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK) - -/*! @name BUFADDR - Current Buffer Descriptor Address register */ -#define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU) -#define SDIF_BUFADDR_HBA_SHIFT (0U) -#define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK) - -/*! @name CARDTHRCTL - Card Threshold Control */ -#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U) -#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U) -#define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK) -#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U) -#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U) -#define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK) -#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U) -#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U) -#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK) - -/*! @name BACKENDPWR - Power control */ -#define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U) -#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U) -#define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK) - -/*! @name FIFO - SDIF FIFO */ -#define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU) -#define SDIF_FIFO_DATA_SHIFT (0U) -#define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK) - -/* The count of SDIF_FIFO */ -#define SDIF_FIFO_COUNT (64U) - - -/*! - * @} - */ /* end of group SDIF_Register_Masks */ - - -/* SDIF - Peripheral instance base addresses */ -/** Peripheral SDIF base address */ -#define SDIF_BASE (0x4009B000u) -/** Peripheral SDIF base pointer */ -#define SDIF ((SDIF_Type *)SDIF_BASE) -/** Array initializer of SDIF peripheral base addresses */ -#define SDIF_BASE_ADDRS { SDIF_BASE } -/** Array initializer of SDIF peripheral base pointers */ -#define SDIF_BASE_PTRS { SDIF } -/** Interrupt vectors for the SDIF peripheral type */ -#define SDIF_IRQS { SDIO_IRQn } - -/*! - * @} - */ /* end of group SDIF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SMARTCARD Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SMARTCARD_Peripheral_Access_Layer SMARTCARD Peripheral Access Layer - * @{ - */ - -/** SMARTCARD - Register Layout Typedef */ -typedef struct { - union { /* offset: 0x0 */ - __IO uint32_t DLL; /**< Divisor Latch LSB, offset: 0x0 */ - __I uint32_t RBR; /**< Receiver Buffer Register, offset: 0x0 */ - __O uint32_t THR; /**< Transmit Holding Register, offset: 0x0 */ - }; - union { /* offset: 0x4 */ - __IO uint32_t DLM; /**< Divisor Latch MSB, offset: 0x4 */ - __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x4 */ - }; - union { /* offset: 0x8 */ - __O uint32_t FCR; /**< FIFO Control Register, offset: 0x8 */ - __I uint32_t IIR; /**< Interrupt ID Register, offset: 0x8 */ - }; - __IO uint32_t LCR; /**< Line Control Register, offset: 0xC */ - uint8_t RESERVED_0[4]; - __I uint32_t LSR; /**< Line Status Register, offset: 0x14 */ - uint8_t RESERVED_1[4]; - __IO uint32_t SCR; /**< Scratch Pad Register, offset: 0x1C */ - uint8_t RESERVED_2[12]; - __IO uint32_t OSR; /**< Oversampling register, offset: 0x2C */ - uint8_t RESERVED_3[24]; - __IO uint32_t SCICTRL; /**< Smart Card Interface control register, offset: 0x48 */ -} SMARTCARD_Type; - -/* ---------------------------------------------------------------------------- - -- SMARTCARD Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SMARTCARD_Register_Masks SMARTCARD Register Masks - * @{ - */ - -/*! @name DLL - Divisor Latch LSB */ -#define SMARTCARD_DLL_DLLSB_MASK (0xFFU) -#define SMARTCARD_DLL_DLLSB_SHIFT (0U) -#define SMARTCARD_DLL_DLLSB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLL_DLLSB_SHIFT)) & SMARTCARD_DLL_DLLSB_MASK) - -/*! @name RBR - Receiver Buffer Register */ -#define SMARTCARD_RBR_RBR_MASK (0xFFU) -#define SMARTCARD_RBR_RBR_SHIFT (0U) -#define SMARTCARD_RBR_RBR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_RBR_RBR_SHIFT)) & SMARTCARD_RBR_RBR_MASK) - -/*! @name THR - Transmit Holding Register */ -#define SMARTCARD_THR_THR_MASK (0xFFU) -#define SMARTCARD_THR_THR_SHIFT (0U) -#define SMARTCARD_THR_THR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_THR_THR_SHIFT)) & SMARTCARD_THR_THR_MASK) - -/*! @name DLM - Divisor Latch MSB */ -#define SMARTCARD_DLM_DLMSB_MASK (0xFFU) -#define SMARTCARD_DLM_DLMSB_SHIFT (0U) -#define SMARTCARD_DLM_DLMSB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLM_DLMSB_SHIFT)) & SMARTCARD_DLM_DLMSB_MASK) - -/*! @name IER - Interrupt Enable Register */ -#define SMARTCARD_IER_RBRIE_MASK (0x1U) -#define SMARTCARD_IER_RBRIE_SHIFT (0U) -#define SMARTCARD_IER_RBRIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RBRIE_SHIFT)) & SMARTCARD_IER_RBRIE_MASK) -#define SMARTCARD_IER_THREIE_MASK (0x2U) -#define SMARTCARD_IER_THREIE_SHIFT (1U) -#define SMARTCARD_IER_THREIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_THREIE_SHIFT)) & SMARTCARD_IER_THREIE_MASK) -#define SMARTCARD_IER_RXIE_MASK (0x4U) -#define SMARTCARD_IER_RXIE_SHIFT (2U) -#define SMARTCARD_IER_RXIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RXIE_SHIFT)) & SMARTCARD_IER_RXIE_MASK) - -/*! @name FCR - FIFO Control Register */ -#define SMARTCARD_FCR_FIFOEN_MASK (0x1U) -#define SMARTCARD_FCR_FIFOEN_SHIFT (0U) -#define SMARTCARD_FCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_FIFOEN_SHIFT)) & SMARTCARD_FCR_FIFOEN_MASK) -#define SMARTCARD_FCR_RXFIFORES_MASK (0x2U) -#define SMARTCARD_FCR_RXFIFORES_SHIFT (1U) -#define SMARTCARD_FCR_RXFIFORES(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXFIFORES_SHIFT)) & SMARTCARD_FCR_RXFIFORES_MASK) -#define SMARTCARD_FCR_TXFIFORES_MASK (0x4U) -#define SMARTCARD_FCR_TXFIFORES_SHIFT (2U) -#define SMARTCARD_FCR_TXFIFORES(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_TXFIFORES_SHIFT)) & SMARTCARD_FCR_TXFIFORES_MASK) -#define SMARTCARD_FCR_DMAMODE_MASK (0x8U) -#define SMARTCARD_FCR_DMAMODE_SHIFT (3U) -#define SMARTCARD_FCR_DMAMODE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_DMAMODE_SHIFT)) & SMARTCARD_FCR_DMAMODE_MASK) -#define SMARTCARD_FCR_RXTRIGLVL_MASK (0xC0U) -#define SMARTCARD_FCR_RXTRIGLVL_SHIFT (6U) -#define SMARTCARD_FCR_RXTRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXTRIGLVL_SHIFT)) & SMARTCARD_FCR_RXTRIGLVL_MASK) - -/*! @name IIR - Interrupt ID Register */ -#define SMARTCARD_IIR_INTSTATUS_MASK (0x1U) -#define SMARTCARD_IIR_INTSTATUS_SHIFT (0U) -#define SMARTCARD_IIR_INTSTATUS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTSTATUS_SHIFT)) & SMARTCARD_IIR_INTSTATUS_MASK) -#define SMARTCARD_IIR_INTID_MASK (0xEU) -#define SMARTCARD_IIR_INTID_SHIFT (1U) -#define SMARTCARD_IIR_INTID(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTID_SHIFT)) & SMARTCARD_IIR_INTID_MASK) -#define SMARTCARD_IIR_FIFOENABLE_MASK (0xC0U) -#define SMARTCARD_IIR_FIFOENABLE_SHIFT (6U) -#define SMARTCARD_IIR_FIFOENABLE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_FIFOENABLE_SHIFT)) & SMARTCARD_IIR_FIFOENABLE_MASK) - -/*! @name LCR - Line Control Register */ -#define SMARTCARD_LCR_WLS_MASK (0x3U) -#define SMARTCARD_LCR_WLS_SHIFT (0U) -#define SMARTCARD_LCR_WLS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_WLS_SHIFT)) & SMARTCARD_LCR_WLS_MASK) -#define SMARTCARD_LCR_SBS_MASK (0x4U) -#define SMARTCARD_LCR_SBS_SHIFT (2U) -#define SMARTCARD_LCR_SBS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_SBS_SHIFT)) & SMARTCARD_LCR_SBS_MASK) -#define SMARTCARD_LCR_PE_MASK (0x8U) -#define SMARTCARD_LCR_PE_SHIFT (3U) -#define SMARTCARD_LCR_PE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PE_SHIFT)) & SMARTCARD_LCR_PE_MASK) -#define SMARTCARD_LCR_PS_MASK (0x30U) -#define SMARTCARD_LCR_PS_SHIFT (4U) -#define SMARTCARD_LCR_PS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PS_SHIFT)) & SMARTCARD_LCR_PS_MASK) -#define SMARTCARD_LCR_DLAB_MASK (0x80U) -#define SMARTCARD_LCR_DLAB_SHIFT (7U) -#define SMARTCARD_LCR_DLAB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_DLAB_SHIFT)) & SMARTCARD_LCR_DLAB_MASK) - -/*! @name LSR - Line Status Register */ -#define SMARTCARD_LSR_RDR_MASK (0x1U) -#define SMARTCARD_LSR_RDR_SHIFT (0U) -#define SMARTCARD_LSR_RDR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RDR_SHIFT)) & SMARTCARD_LSR_RDR_MASK) -#define SMARTCARD_LSR_OE_MASK (0x2U) -#define SMARTCARD_LSR_OE_SHIFT (1U) -#define SMARTCARD_LSR_OE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_OE_SHIFT)) & SMARTCARD_LSR_OE_MASK) -#define SMARTCARD_LSR_PE_MASK (0x4U) -#define SMARTCARD_LSR_PE_SHIFT (2U) -#define SMARTCARD_LSR_PE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_PE_SHIFT)) & SMARTCARD_LSR_PE_MASK) -#define SMARTCARD_LSR_FE_MASK (0x8U) -#define SMARTCARD_LSR_FE_SHIFT (3U) -#define SMARTCARD_LSR_FE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_FE_SHIFT)) & SMARTCARD_LSR_FE_MASK) -#define SMARTCARD_LSR_THRE_MASK (0x20U) -#define SMARTCARD_LSR_THRE_SHIFT (5U) -#define SMARTCARD_LSR_THRE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_THRE_SHIFT)) & SMARTCARD_LSR_THRE_MASK) -#define SMARTCARD_LSR_TEMT_MASK (0x40U) -#define SMARTCARD_LSR_TEMT_SHIFT (6U) -#define SMARTCARD_LSR_TEMT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_TEMT_SHIFT)) & SMARTCARD_LSR_TEMT_MASK) -#define SMARTCARD_LSR_RXFE_MASK (0x80U) -#define SMARTCARD_LSR_RXFE_SHIFT (7U) -#define SMARTCARD_LSR_RXFE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RXFE_SHIFT)) & SMARTCARD_LSR_RXFE_MASK) - -/*! @name SCR - Scratch Pad Register */ -#define SMARTCARD_SCR_PAD_MASK (0xFFU) -#define SMARTCARD_SCR_PAD_SHIFT (0U) -#define SMARTCARD_SCR_PAD(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCR_PAD_SHIFT)) & SMARTCARD_SCR_PAD_MASK) - -/*! @name OSR - Oversampling register */ -#define SMARTCARD_OSR_OSFRAC_MASK (0xEU) -#define SMARTCARD_OSR_OSFRAC_SHIFT (1U) -#define SMARTCARD_OSR_OSFRAC(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSFRAC_SHIFT)) & SMARTCARD_OSR_OSFRAC_MASK) -#define SMARTCARD_OSR_OSINT_MASK (0xF0U) -#define SMARTCARD_OSR_OSINT_SHIFT (4U) -#define SMARTCARD_OSR_OSINT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSINT_SHIFT)) & SMARTCARD_OSR_OSINT_MASK) -#define SMARTCARD_OSR_FDINT_MASK (0x7F00U) -#define SMARTCARD_OSR_FDINT_SHIFT (8U) -#define SMARTCARD_OSR_FDINT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_FDINT_SHIFT)) & SMARTCARD_OSR_FDINT_MASK) - -/*! @name SCICTRL - Smart Card Interface control register */ -#define SMARTCARD_SCICTRL_SCIEN_MASK (0x1U) -#define SMARTCARD_SCICTRL_SCIEN_SHIFT (0U) -#define SMARTCARD_SCICTRL_SCIEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_SCIEN_SHIFT)) & SMARTCARD_SCICTRL_SCIEN_MASK) -#define SMARTCARD_SCICTRL_NACKDIS_MASK (0x2U) -#define SMARTCARD_SCICTRL_NACKDIS_SHIFT (1U) -#define SMARTCARD_SCICTRL_NACKDIS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_NACKDIS_SHIFT)) & SMARTCARD_SCICTRL_NACKDIS_MASK) -#define SMARTCARD_SCICTRL_PROTSEL_MASK (0x4U) -#define SMARTCARD_SCICTRL_PROTSEL_SHIFT (2U) -#define SMARTCARD_SCICTRL_PROTSEL(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_PROTSEL_SHIFT)) & SMARTCARD_SCICTRL_PROTSEL_MASK) -#define SMARTCARD_SCICTRL_TXRETRY_MASK (0xE0U) -#define SMARTCARD_SCICTRL_TXRETRY_SHIFT (5U) -#define SMARTCARD_SCICTRL_TXRETRY(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_TXRETRY_SHIFT)) & SMARTCARD_SCICTRL_TXRETRY_MASK) -#define SMARTCARD_SCICTRL_GUARDTIME_MASK (0xFF00U) -#define SMARTCARD_SCICTRL_GUARDTIME_SHIFT (8U) -#define SMARTCARD_SCICTRL_GUARDTIME(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_GUARDTIME_SHIFT)) & SMARTCARD_SCICTRL_GUARDTIME_MASK) - - -/*! - * @} - */ /* end of group SMARTCARD_Register_Masks */ - - -/* SMARTCARD - Peripheral instance base addresses */ -/** Peripheral SMARTCARD0 base address */ -#define SMARTCARD0_BASE (0x40036000u) -/** Peripheral SMARTCARD0 base pointer */ -#define SMARTCARD0 ((SMARTCARD_Type *)SMARTCARD0_BASE) -/** Peripheral SMARTCARD1 base address */ -#define SMARTCARD1_BASE (0x40037000u) -/** Peripheral SMARTCARD1 base pointer */ -#define SMARTCARD1 ((SMARTCARD_Type *)SMARTCARD1_BASE) -/** Array initializer of SMARTCARD peripheral base addresses */ -#define SMARTCARD_BASE_ADDRS { SMARTCARD0_BASE, SMARTCARD1_BASE } -/** Array initializer of SMARTCARD peripheral base pointers */ -#define SMARTCARD_BASE_PTRS { SMARTCARD0, SMARTCARD1 } -/** Interrupt vectors for the SMARTCARD peripheral type */ -#define SMARTCARD_IRQS { SMARTCARD0_IRQn, SMARTCARD1_IRQn } - -/*! - * @} - */ /* end of group SMARTCARD_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer - * @{ - */ - -/** SPI - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[1024]; - __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ - __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ - __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ - __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ - __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ - __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ - uint8_t RESERVED_2[2516]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_6[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_7[440]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} SPI_Type; - -/* ---------------------------------------------------------------------------- - -- SPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Register_Masks SPI Register Masks - * @{ - */ - -/*! @name CFG - SPI Configuration register */ -#define SPI_CFG_ENABLE_MASK (0x1U) -#define SPI_CFG_ENABLE_SHIFT (0U) -#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) -#define SPI_CFG_MASTER_MASK (0x4U) -#define SPI_CFG_MASTER_SHIFT (2U) -#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) -#define SPI_CFG_LSBF_MASK (0x8U) -#define SPI_CFG_LSBF_SHIFT (3U) -#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) -#define SPI_CFG_CPHA_MASK (0x10U) -#define SPI_CFG_CPHA_SHIFT (4U) -#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) -#define SPI_CFG_CPOL_MASK (0x20U) -#define SPI_CFG_CPOL_SHIFT (5U) -#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) -#define SPI_CFG_LOOP_MASK (0x80U) -#define SPI_CFG_LOOP_SHIFT (7U) -#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) -#define SPI_CFG_SPOL0_MASK (0x100U) -#define SPI_CFG_SPOL0_SHIFT (8U) -#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) -#define SPI_CFG_SPOL1_MASK (0x200U) -#define SPI_CFG_SPOL1_SHIFT (9U) -#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) -#define SPI_CFG_SPOL2_MASK (0x400U) -#define SPI_CFG_SPOL2_SHIFT (10U) -#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) -#define SPI_CFG_SPOL3_MASK (0x800U) -#define SPI_CFG_SPOL3_SHIFT (11U) -#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) - -/*! @name DLY - SPI Delay register */ -#define SPI_DLY_PRE_DELAY_MASK (0xFU) -#define SPI_DLY_PRE_DELAY_SHIFT (0U) -#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) -#define SPI_DLY_POST_DELAY_MASK (0xF0U) -#define SPI_DLY_POST_DELAY_SHIFT (4U) -#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) -#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) -#define SPI_DLY_FRAME_DELAY_SHIFT (8U) -#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) -#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) -#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) -#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) - -/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ -#define SPI_STAT_SSA_MASK (0x10U) -#define SPI_STAT_SSA_SHIFT (4U) -#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) -#define SPI_STAT_SSD_MASK (0x20U) -#define SPI_STAT_SSD_SHIFT (5U) -#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) -#define SPI_STAT_STALLED_MASK (0x40U) -#define SPI_STAT_STALLED_SHIFT (6U) -#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) -#define SPI_STAT_ENDTRANSFER_MASK (0x80U) -#define SPI_STAT_ENDTRANSFER_SHIFT (7U) -#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) -#define SPI_STAT_MSTIDLE_MASK (0x100U) -#define SPI_STAT_MSTIDLE_SHIFT (8U) -#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) - -/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -#define SPI_INTENSET_SSAEN_MASK (0x10U) -#define SPI_INTENSET_SSAEN_SHIFT (4U) -#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) -#define SPI_INTENSET_SSDEN_MASK (0x20U) -#define SPI_INTENSET_SSDEN_SHIFT (5U) -#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) -#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) -#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) -#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) - -/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ -#define SPI_INTENCLR_SSAEN_MASK (0x10U) -#define SPI_INTENCLR_SSAEN_SHIFT (4U) -#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) -#define SPI_INTENCLR_SSDEN_MASK (0x20U) -#define SPI_INTENCLR_SSDEN_SHIFT (5U) -#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) -#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) -#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) -#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) - -/*! @name DIV - SPI clock Divider */ -#define SPI_DIV_DIVVAL_MASK (0xFFFFU) -#define SPI_DIV_DIVVAL_SHIFT (0U) -#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) - -/*! @name INTSTAT - SPI Interrupt Status */ -#define SPI_INTSTAT_SSA_MASK (0x10U) -#define SPI_INTSTAT_SSA_SHIFT (4U) -#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) -#define SPI_INTSTAT_SSD_MASK (0x20U) -#define SPI_INTSTAT_SSD_SHIFT (5U) -#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) -#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) -#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) -#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) -#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) -#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) -#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) -#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) -#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) -#define SPI_FIFOCFG_SIZE_MASK (0x30U) -#define SPI_FIFOCFG_SIZE_SHIFT (4U) -#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) -#define SPI_FIFOCFG_DMATX_MASK (0x1000U) -#define SPI_FIFOCFG_DMATX_SHIFT (12U) -#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) -#define SPI_FIFOCFG_DMARX_MASK (0x2000U) -#define SPI_FIFOCFG_DMARX_SHIFT (13U) -#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) -#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) -#define SPI_FIFOCFG_WAKETX_SHIFT (14U) -#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) -#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) -#define SPI_FIFOCFG_WAKERX_SHIFT (15U) -#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) -#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) -#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) -#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) -#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) -#define SPI_FIFOCFG_POPDBG_MASK (0x40000U) -#define SPI_FIFOCFG_POPDBG_SHIFT (18U) -#define SPI_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK) - -/*! @name FIFOSTAT - FIFO status register. */ -#define SPI_FIFOSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOSTAT_TXERR_SHIFT (0U) -#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) -#define SPI_FIFOSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOSTAT_RXERR_SHIFT (1U) -#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) -#define SPI_FIFOSTAT_PERINT_MASK (0x8U) -#define SPI_FIFOSTAT_PERINT_SHIFT (3U) -#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) -#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) -#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) -#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) -#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) -#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) -#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) -#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) -#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) -#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) -#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) -#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) -#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) -#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) -#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) -#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) -#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) -#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) -#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) -#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) -#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) -#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) -#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) -#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) -#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) -#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) -#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) -#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) -#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) -#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) -#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) -#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) -#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) -#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) -#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) -#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) -#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) -#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) -#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) -#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) -#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) -#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) -#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) -#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) -#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) -#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) -#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) -#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) -#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) - -/*! @name FIFOWR - FIFO write data. */ -#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) -#define SPI_FIFOWR_TXDATA_SHIFT (0U) -#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) -#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) -#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) -#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) -#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) -#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) -#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) -#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) -#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) -#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) -#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) -#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) -#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) -#define SPI_FIFOWR_EOT_MASK (0x100000U) -#define SPI_FIFOWR_EOT_SHIFT (20U) -#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) -#define SPI_FIFOWR_EOF_MASK (0x200000U) -#define SPI_FIFOWR_EOF_SHIFT (21U) -#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) -#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) -#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) -#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) -#define SPI_FIFOWR_LEN_MASK (0xF000000U) -#define SPI_FIFOWR_LEN_SHIFT (24U) -#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) - -/*! @name FIFORD - FIFO read data. */ -#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORD_RXDATA_SHIFT (0U) -#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) -#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) -#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) -#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) -#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) -#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) -#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) -#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) -#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) -#define SPI_FIFORD_SOT_MASK (0x100000U) -#define SPI_FIFORD_SOT_SHIFT (20U) -#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) -#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) -#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) -#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) -#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) -#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) -#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) -#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) -#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) -#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) -#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) -#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) -#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) - -/*! @name ID - Peripheral identification register. */ -#define SPI_ID_APERTURE_MASK (0xFFU) -#define SPI_ID_APERTURE_SHIFT (0U) -#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) -#define SPI_ID_MINOR_REV_MASK (0xF00U) -#define SPI_ID_MINOR_REV_SHIFT (8U) -#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) -#define SPI_ID_MAJOR_REV_MASK (0xF000U) -#define SPI_ID_MAJOR_REV_SHIFT (12U) -#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) -#define SPI_ID_ID_MASK (0xFFFF0000U) -#define SPI_ID_ID_SHIFT (16U) -#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) - - -/*! - * @} - */ /* end of group SPI_Register_Masks */ - - -/* SPI - Peripheral instance base addresses */ -/** Peripheral SPI0 base address */ -#define SPI0_BASE (0x40086000u) -/** Peripheral SPI0 base pointer */ -#define SPI0 ((SPI_Type *)SPI0_BASE) -/** Peripheral SPI1 base address */ -#define SPI1_BASE (0x40087000u) -/** Peripheral SPI1 base pointer */ -#define SPI1 ((SPI_Type *)SPI1_BASE) -/** Peripheral SPI2 base address */ -#define SPI2_BASE (0x40088000u) -/** Peripheral SPI2 base pointer */ -#define SPI2 ((SPI_Type *)SPI2_BASE) -/** Peripheral SPI3 base address */ -#define SPI3_BASE (0x40089000u) -/** Peripheral SPI3 base pointer */ -#define SPI3 ((SPI_Type *)SPI3_BASE) -/** Peripheral SPI4 base address */ -#define SPI4_BASE (0x4008A000u) -/** Peripheral SPI4 base pointer */ -#define SPI4 ((SPI_Type *)SPI4_BASE) -/** Peripheral SPI5 base address */ -#define SPI5_BASE (0x40096000u) -/** Peripheral SPI5 base pointer */ -#define SPI5 ((SPI_Type *)SPI5_BASE) -/** Peripheral SPI6 base address */ -#define SPI6_BASE (0x40097000u) -/** Peripheral SPI6 base pointer */ -#define SPI6 ((SPI_Type *)SPI6_BASE) -/** Peripheral SPI7 base address */ -#define SPI7_BASE (0x40098000u) -/** Peripheral SPI7 base pointer */ -#define SPI7 ((SPI_Type *)SPI7_BASE) -/** Peripheral SPI8 base address */ -#define SPI8_BASE (0x40099000u) -/** Peripheral SPI8 base pointer */ -#define SPI8 ((SPI_Type *)SPI8_BASE) -/** Peripheral SPI9 base address */ -#define SPI9_BASE (0x4009A000u) -/** Peripheral SPI9 base pointer */ -#define SPI9 ((SPI_Type *)SPI9_BASE) -/** Array initializer of SPI peripheral base addresses */ -#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE, SPI9_BASE } -/** Array initializer of SPI peripheral base pointers */ -#define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8, SPI9 } -/** Interrupt vectors for the SPI peripheral type */ -#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn } - -/*! - * @} - */ /* end of group SPI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPIFI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPIFI_Peripheral_Access_Layer SPIFI Peripheral Access Layer - * @{ - */ - -/** SPIFI - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< SPIFI control register, offset: 0x0 */ - __IO uint32_t CMD; /**< SPIFI command register, offset: 0x4 */ - __IO uint32_t ADDR; /**< SPIFI address register, offset: 0x8 */ - __IO uint32_t IDATA; /**< SPIFI intermediate data register, offset: 0xC */ - __IO uint32_t CLIMIT; /**< SPIFI limit register, offset: 0x10 */ - __IO uint32_t DATA; /**< SPIFI data register, offset: 0x14 */ - __IO uint32_t MCMD; /**< SPIFI memory command register, offset: 0x18 */ - __IO uint32_t STAT; /**< SPIFI status register, offset: 0x1C */ -} SPIFI_Type; - -/* ---------------------------------------------------------------------------- - -- SPIFI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPIFI_Register_Masks SPIFI Register Masks - * @{ - */ - -/*! @name CTRL - SPIFI control register */ -#define SPIFI_CTRL_TIMEOUT_MASK (0xFFFFU) -#define SPIFI_CTRL_TIMEOUT_SHIFT (0U) -#define SPIFI_CTRL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK) -#define SPIFI_CTRL_CSHIGH_MASK (0xF0000U) -#define SPIFI_CTRL_CSHIGH_SHIFT (16U) -#define SPIFI_CTRL_CSHIGH(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK) -#define SPIFI_CTRL_D_PRFTCH_DIS_MASK (0x200000U) -#define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT (21U) -#define SPIFI_CTRL_D_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK) -#define SPIFI_CTRL_INTEN_MASK (0x400000U) -#define SPIFI_CTRL_INTEN_SHIFT (22U) -#define SPIFI_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK) -#define SPIFI_CTRL_MODE3_MASK (0x800000U) -#define SPIFI_CTRL_MODE3_SHIFT (23U) -#define SPIFI_CTRL_MODE3(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK) -#define SPIFI_CTRL_PRFTCH_DIS_MASK (0x8000000U) -#define SPIFI_CTRL_PRFTCH_DIS_SHIFT (27U) -#define SPIFI_CTRL_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK) -#define SPIFI_CTRL_DUAL_MASK (0x10000000U) -#define SPIFI_CTRL_DUAL_SHIFT (28U) -#define SPIFI_CTRL_DUAL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK) -#define SPIFI_CTRL_RFCLK_MASK (0x20000000U) -#define SPIFI_CTRL_RFCLK_SHIFT (29U) -#define SPIFI_CTRL_RFCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK) -#define SPIFI_CTRL_FBCLK_MASK (0x40000000U) -#define SPIFI_CTRL_FBCLK_SHIFT (30U) -#define SPIFI_CTRL_FBCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK) -#define SPIFI_CTRL_DMAEN_MASK (0x80000000U) -#define SPIFI_CTRL_DMAEN_SHIFT (31U) -#define SPIFI_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK) - -/*! @name CMD - SPIFI command register */ -#define SPIFI_CMD_DATALEN_MASK (0x3FFFU) -#define SPIFI_CMD_DATALEN_SHIFT (0U) -#define SPIFI_CMD_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK) -#define SPIFI_CMD_POLL_MASK (0x4000U) -#define SPIFI_CMD_POLL_SHIFT (14U) -#define SPIFI_CMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK) -#define SPIFI_CMD_DOUT_MASK (0x8000U) -#define SPIFI_CMD_DOUT_SHIFT (15U) -#define SPIFI_CMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK) -#define SPIFI_CMD_INTLEN_MASK (0x70000U) -#define SPIFI_CMD_INTLEN_SHIFT (16U) -#define SPIFI_CMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK) -#define SPIFI_CMD_FIELDFORM_MASK (0x180000U) -#define SPIFI_CMD_FIELDFORM_SHIFT (19U) -#define SPIFI_CMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK) -#define SPIFI_CMD_FRAMEFORM_MASK (0xE00000U) -#define SPIFI_CMD_FRAMEFORM_SHIFT (21U) -#define SPIFI_CMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK) -#define SPIFI_CMD_OPCODE_MASK (0xFF000000U) -#define SPIFI_CMD_OPCODE_SHIFT (24U) -#define SPIFI_CMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK) - -/*! @name ADDR - SPIFI address register */ -#define SPIFI_ADDR_ADDRESS_MASK (0xFFFFFFFFU) -#define SPIFI_ADDR_ADDRESS_SHIFT (0U) -#define SPIFI_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK) - -/*! @name IDATA - SPIFI intermediate data register */ -#define SPIFI_IDATA_IDATA_MASK (0xFFFFFFFFU) -#define SPIFI_IDATA_IDATA_SHIFT (0U) -#define SPIFI_IDATA_IDATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK) - -/*! @name CLIMIT - SPIFI limit register */ -#define SPIFI_CLIMIT_CLIMIT_MASK (0xFFFFFFFFU) -#define SPIFI_CLIMIT_CLIMIT_SHIFT (0U) -#define SPIFI_CLIMIT_CLIMIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK) - -/*! @name DATA - SPIFI data register */ -#define SPIFI_DATA_DATA_MASK (0xFFFFFFFFU) -#define SPIFI_DATA_DATA_SHIFT (0U) -#define SPIFI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK) - -/*! @name MCMD - SPIFI memory command register */ -#define SPIFI_MCMD_POLL_MASK (0x4000U) -#define SPIFI_MCMD_POLL_SHIFT (14U) -#define SPIFI_MCMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK) -#define SPIFI_MCMD_DOUT_MASK (0x8000U) -#define SPIFI_MCMD_DOUT_SHIFT (15U) -#define SPIFI_MCMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK) -#define SPIFI_MCMD_INTLEN_MASK (0x70000U) -#define SPIFI_MCMD_INTLEN_SHIFT (16U) -#define SPIFI_MCMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK) -#define SPIFI_MCMD_FIELDFORM_MASK (0x180000U) -#define SPIFI_MCMD_FIELDFORM_SHIFT (19U) -#define SPIFI_MCMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK) -#define SPIFI_MCMD_FRAMEFORM_MASK (0xE00000U) -#define SPIFI_MCMD_FRAMEFORM_SHIFT (21U) -#define SPIFI_MCMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK) -#define SPIFI_MCMD_OPCODE_MASK (0xFF000000U) -#define SPIFI_MCMD_OPCODE_SHIFT (24U) -#define SPIFI_MCMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK) - -/*! @name STAT - SPIFI status register */ -#define SPIFI_STAT_MCINIT_MASK (0x1U) -#define SPIFI_STAT_MCINIT_SHIFT (0U) -#define SPIFI_STAT_MCINIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK) -#define SPIFI_STAT_CMD_MASK (0x2U) -#define SPIFI_STAT_CMD_SHIFT (1U) -#define SPIFI_STAT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK) -#define SPIFI_STAT_RESET_MASK (0x10U) -#define SPIFI_STAT_RESET_SHIFT (4U) -#define SPIFI_STAT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK) -#define SPIFI_STAT_INTRQ_MASK (0x20U) -#define SPIFI_STAT_INTRQ_SHIFT (5U) -#define SPIFI_STAT_INTRQ(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK) - - -/*! - * @} - */ /* end of group SPIFI_Register_Masks */ - - -/* SPIFI - Peripheral instance base addresses */ -/** Peripheral SPIFI0 base address */ -#define SPIFI0_BASE (0x40080000u) -/** Peripheral SPIFI0 base pointer */ -#define SPIFI0 ((SPIFI_Type *)SPIFI0_BASE) -/** Array initializer of SPIFI peripheral base addresses */ -#define SPIFI_BASE_ADDRS { SPIFI0_BASE } -/** Array initializer of SPIFI peripheral base pointers */ -#define SPIFI_BASE_PTRS { SPIFI0 } -/** Interrupt vectors for the SPIFI peripheral type */ -#define SPIFI_IRQS { SPIFI0_IRQn } - -/*! - * @} - */ /* end of group SPIFI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SYSCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer - * @{ - */ - -/** SYSCON - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[16]; - __IO uint32_t AHBMATPRIO; /**< AHB multilayer matrix priority control, offset: 0x10 */ - uint8_t RESERVED_1[44]; - __IO uint32_t SYSTCKCAL; /**< System tick counter calibration, offset: 0x40 */ - uint8_t RESERVED_2[4]; - __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ - __IO uint32_t ASYNCAPBCTRL; /**< Asynchronous APB Control, offset: 0x4C */ - uint8_t RESERVED_3[112]; - __I uint32_t PIOPORCAP[2]; /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */ - uint8_t RESERVED_4[8]; - __I uint32_t PIORESCAP[2]; /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */ - uint8_t RESERVED_5[40]; - __IO uint32_t PRESETCTRL[3]; /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */ - uint8_t RESERVED_6[20]; - __O uint32_t PRESETCTRLSET[3]; /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */ - uint8_t RESERVED_7[20]; - __O uint32_t PRESETCTRLCLR[3]; /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */ - uint8_t RESERVED_8[164]; - __IO uint32_t SYSRSTSTAT; /**< System reset status register, offset: 0x1F0 */ - uint8_t RESERVED_9[12]; - __IO uint32_t AHBCLKCTRL[3]; /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_10[20]; - __O uint32_t AHBCLKCTRLSET[3]; /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */ - uint8_t RESERVED_11[20]; - __O uint32_t AHBCLKCTRLCLR[3]; /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */ - uint8_t RESERVED_12[52]; - __IO uint32_t MAINCLKSELA; /**< Main clock source select A, offset: 0x280 */ - __IO uint32_t MAINCLKSELB; /**< Main clock source select B, offset: 0x284 */ - __IO uint32_t CLKOUTSELA; /**< CLKOUT clock source select A, offset: 0x288 */ - uint8_t RESERVED_13[4]; - __IO uint32_t SYSPLLCLKSEL; /**< PLL clock source select, offset: 0x290 */ - uint8_t RESERVED_14[4]; - __IO uint32_t AUDPLLCLKSEL; /**< Audio PLL clock source select, offset: 0x298 */ - uint8_t RESERVED_15[4]; - __IO uint32_t SPIFICLKSEL; /**< SPIFI clock source select, offset: 0x2A0 */ - __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ - __IO uint32_t USB0CLKSEL; /**< USB0 clock source select, offset: 0x2A8 */ - __IO uint32_t USB1CLKSEL; /**< USB1 clock source select, offset: 0x2AC */ - __IO uint32_t FCLKSEL[10]; /**< Flexcomm 0 clock source select, array offset: 0x2B0, array step: 0x4 */ - uint8_t RESERVED_16[8]; - __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ - uint8_t RESERVED_17[4]; - __IO uint32_t FRGCLKSEL; /**< Fractional Rate Generator clock source select, offset: 0x2E8 */ - __IO uint32_t DMICCLKSEL; /**< Digital microphone (DMIC) subsystem clock select, offset: 0x2EC */ - __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ - __IO uint32_t LCDCLKSEL; /**< LCD clock source select, offset: 0x2F4 */ - __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */ - uint8_t RESERVED_18[4]; - __IO uint32_t SYSTICKCLKDIV; /**< SYSTICK clock divider, offset: 0x300 */ - __IO uint32_t ARMTRACECLKDIV; /**< ARM Trace clock divider, offset: 0x304 */ - __IO uint32_t CAN0CLKDIV; /**< MCAN0 clock divider, offset: 0x308 */ - __IO uint32_t CAN1CLKDIV; /**< MCAN1 clock divider, offset: 0x30C */ - __IO uint32_t SC0CLKDIV; /**< Smartcard0 clock divider, offset: 0x310 */ - __IO uint32_t SC1CLKDIV; /**< Smartcard1 clock divider, offset: 0x314 */ - uint8_t RESERVED_19[104]; - __IO uint32_t AHBCLKDIV; /**< AHB clock divider, offset: 0x380 */ - __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ - __IO uint32_t FROHFCLKDIV; /**< FROHF clock divider, offset: 0x388 */ - uint8_t RESERVED_20[4]; - __IO uint32_t SPIFICLKDIV; /**< SPIFI clock divider, offset: 0x390 */ - __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ - __IO uint32_t USB0CLKDIV; /**< USB0 clock divider, offset: 0x398 */ - __IO uint32_t USB1CLKDIV; /**< USB1 clock divider, offset: 0x39C */ - __IO uint32_t FRGCTRL; /**< Fractional rate divider, offset: 0x3A0 */ - uint8_t RESERVED_21[4]; - __IO uint32_t DMICCLKDIV; /**< DMIC clock divider, offset: 0x3A8 */ - __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ - __IO uint32_t LCDCLKDIV; /**< LCD clock divider, offset: 0x3B0 */ - __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ - __IO uint32_t EMCCLKDIV; /**< EMC clock divider, offset: 0x3B8 */ - __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */ - uint8_t RESERVED_22[64]; - __IO uint32_t FLASHCFG; /**< Flash wait states configuration, offset: 0x400 */ - uint8_t RESERVED_23[8]; - __IO uint32_t USB0CLKCTRL; /**< USB0 clock control, offset: 0x40C */ - __IO uint32_t USB0CLKSTAT; /**< USB0 clock status, offset: 0x410 */ - uint8_t RESERVED_24[4]; - __IO uint32_t FREQMECTRL; /**< Frequency measure register, offset: 0x418 */ - uint8_t RESERVED_25[4]; - __IO uint32_t MCLKIO; /**< MCLK input/output control, offset: 0x420 */ - __IO uint32_t USB1CLKCTRL; /**< USB1 clock control, offset: 0x424 */ - __IO uint32_t USB1CLKSTAT; /**< USB1 clock status, offset: 0x428 */ - uint8_t RESERVED_26[24]; - __IO uint32_t EMCSYSCTRL; /**< EMC system control, offset: 0x444 */ - __IO uint32_t EMCDLYCTRL; /**< EMC clock delay control, offset: 0x448 */ - __IO uint32_t EMCDLYCAL; /**< EMC delay chain calibration control, offset: 0x44C */ - __IO uint32_t ETHPHYSEL; /**< Ethernet PHY Selection, offset: 0x450 */ - __IO uint32_t ETHSBDCTRL; /**< Ethernet SBD flow control, offset: 0x454 */ - uint8_t RESERVED_27[8]; - __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */ - uint8_t RESERVED_28[156]; - __IO uint32_t FROCTRL; /**< FRO oscillator control, offset: 0x500 */ - __IO uint32_t SYSOSCCTRL; /**< System oscillator control, offset: 0x504 */ - __IO uint32_t WDTOSCCTRL; /**< Watchdog oscillator control, offset: 0x508 */ - __IO uint32_t RTCOSCCTRL; /**< RTC oscillator 32 kHz output control, offset: 0x50C */ - uint8_t RESERVED_29[12]; - __IO uint32_t USBPLLCTRL; /**< USB PLL control, offset: 0x51C */ - __IO uint32_t USBPLLSTAT; /**< USB PLL status, offset: 0x520 */ - uint8_t RESERVED_30[92]; - __IO uint32_t SYSPLLCTRL; /**< System PLL control, offset: 0x580 */ - __IO uint32_t SYSPLLSTAT; /**< PLL status, offset: 0x584 */ - __IO uint32_t SYSPLLNDEC; /**< PLL N divider, offset: 0x588 */ - __IO uint32_t SYSPLLPDEC; /**< PLL P divider, offset: 0x58C */ - __IO uint32_t SYSPLLMDEC; /**< System PLL M divider, offset: 0x590 */ - uint8_t RESERVED_31[12]; - __IO uint32_t AUDPLLCTRL; /**< Audio PLL control, offset: 0x5A0 */ - __IO uint32_t AUDPLLSTAT; /**< Audio PLL status, offset: 0x5A4 */ - __IO uint32_t AUDPLLNDEC; /**< Audio PLL N divider, offset: 0x5A8 */ - __IO uint32_t AUDPLLPDEC; /**< Audio PLL P divider, offset: 0x5AC */ - __IO uint32_t AUDPLLMDEC; /**< Audio PLL M divider, offset: 0x5B0 */ - __IO uint32_t AUDPLLFRAC; /**< Audio PLL fractional divider control, offset: 0x5B4 */ - uint8_t RESERVED_32[72]; - __IO uint32_t PDSLEEPCFG[2]; /**< Power configuration register 0, array offset: 0x600, array step: 0x4 */ - uint8_t RESERVED_33[8]; - __IO uint32_t PDRUNCFG[2]; /**< Power configuration register 0, array offset: 0x610, array step: 0x4 */ - uint8_t RESERVED_34[8]; - __IO uint32_t PDRUNCFGSET[2]; /**< Set bits in PDRUNCFG0, array offset: 0x620, array step: 0x4 */ - uint8_t RESERVED_35[8]; - __IO uint32_t PDRUNCFGCLR[2]; /**< Clear bits in PDRUNCFG0, array offset: 0x630, array step: 0x4 */ - uint8_t RESERVED_36[72]; - __IO uint32_t STARTER[2]; /**< Start logic 0 wake-up enable register, array offset: 0x680, array step: 0x4 */ - uint8_t RESERVED_37[24]; - __O uint32_t STARTERSET[2]; /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */ - uint8_t RESERVED_38[24]; - __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTER0, array offset: 0x6C0, array step: 0x4 */ - uint8_t RESERVED_39[184]; - __IO uint32_t HWWAKE; /**< Configures special cases of hardware wake-up, offset: 0x780 */ - uint8_t RESERVED_40[1664]; - __IO uint32_t AUTOCGOR; /**< Auto Clock-Gate Override Register, offset: 0xE04 */ - uint8_t RESERVED_41[492]; - __I uint32_t JTAGIDCODE; /**< JTAG ID code register, offset: 0xFF4 */ - __I uint32_t DEVICE_ID0; /**< Part ID register, offset: 0xFF8 */ - __I uint32_t DEVICE_ID1; /**< Boot ROM and die revision register, offset: 0xFFC */ - uint8_t RESERVED_42[127044]; - __IO uint32_t BODCTRL; /**< Brown-Out Detect control, offset: 0x20044 */ -} SYSCON_Type; - -/* ---------------------------------------------------------------------------- - -- SYSCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Register_Masks SYSCON Register Masks - * @{ - */ - -/*! @name AHBMATPRIO - AHB multilayer matrix priority control */ -#define SYSCON_AHBMATPRIO_PRI_ICODE_MASK (0x3U) -#define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT (0U) -#define SYSCON_AHBMATPRIO_PRI_ICODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK) -#define SYSCON_AHBMATPRIO_PRI_DCODE_MASK (0xCU) -#define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT (2U) -#define SYSCON_AHBMATPRIO_PRI_DCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK) -#define SYSCON_AHBMATPRIO_PRI_SYS_MASK (0x30U) -#define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT (4U) -#define SYSCON_AHBMATPRIO_PRI_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK) -#define SYSCON_AHBMATPRIO_PRI_DMA_MASK (0x3C0U) -#define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT (6U) -#define SYSCON_AHBMATPRIO_PRI_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK) -#define SYSCON_AHBMATPRIO_PRI_ETH_MASK (0xC00U) -#define SYSCON_AHBMATPRIO_PRI_ETH_SHIFT (10U) -#define SYSCON_AHBMATPRIO_PRI_ETH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ETH_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ETH_MASK) -#define SYSCON_AHBMATPRIO_PRI_LCD_MASK (0x3000U) -#define SYSCON_AHBMATPRIO_PRI_LCD_SHIFT (12U) -#define SYSCON_AHBMATPRIO_PRI_LCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_LCD_SHIFT)) & SYSCON_AHBMATPRIO_PRI_LCD_MASK) -#define SYSCON_AHBMATPRIO_PRI_USB0_MASK (0xC000U) -#define SYSCON_AHBMATPRIO_PRI_USB0_SHIFT (14U) -#define SYSCON_AHBMATPRIO_PRI_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB0_MASK) -#define SYSCON_AHBMATPRIO_PRI_USB1_MASK (0x30000U) -#define SYSCON_AHBMATPRIO_PRI_USB1_SHIFT (16U) -#define SYSCON_AHBMATPRIO_PRI_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB1_MASK) -#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0xC0000U) -#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (18U) -#define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK) -#define SYSCON_AHBMATPRIO_PRI_MCAN1_MASK (0x300000U) -#define SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT (20U) -#define SYSCON_AHBMATPRIO_PRI_MCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN1_MASK) -#define SYSCON_AHBMATPRIO_PRI_MCAN2_MASK (0xC00000U) -#define SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT (22U) -#define SYSCON_AHBMATPRIO_PRI_MCAN2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN2_MASK) -#define SYSCON_AHBMATPRIO_PRI_SHA_MASK (0x3000000U) -#define SYSCON_AHBMATPRIO_PRI_SHA_SHIFT (24U) -#define SYSCON_AHBMATPRIO_PRI_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SHA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SHA_MASK) - -/*! @name SYSTCKCAL - System tick counter calibration */ -#define SYSCON_SYSTCKCAL_CAL_MASK (0xFFFFFFU) -#define SYSCON_SYSTCKCAL_CAL_SHIFT (0U) -#define SYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK) -#define SYSCON_SYSTCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_SYSTCKCAL_SKEW_SHIFT (24U) -#define SYSCON_SYSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK) -#define SYSCON_SYSTCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_SYSTCKCAL_NOREF_SHIFT (25U) -#define SYSCON_SYSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK) - -/*! @name NMISRC - NMI Source Select */ -#define SYSCON_NMISRC_IRQM4_MASK (0x3FU) -#define SYSCON_NMISRC_IRQM4_SHIFT (0U) -#define SYSCON_NMISRC_IRQM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK) -#define SYSCON_NMISRC_NMIENM4_MASK (0x80000000U) -#define SYSCON_NMISRC_NMIENM4_SHIFT (31U) -#define SYSCON_NMISRC_NMIENM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK) - -/*! @name ASYNCAPBCTRL - Asynchronous APB Control */ -#define SYSCON_ASYNCAPBCTRL_ENABLE_MASK (0x1U) -#define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT (0U) -#define SYSCON_ASYNCAPBCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK) - -/*! @name PIOPORCAP - POR captured value of port n */ -#define SYSCON_PIOPORCAP_PIOPORCAP_MASK (0xFFFFFFFFU) -#define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT (0U) -#define SYSCON_PIOPORCAP_PIOPORCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK) - -/* The count of SYSCON_PIOPORCAP */ -#define SYSCON_PIOPORCAP_COUNT (2U) - -/*! @name PIORESCAP - Reset captured value of port n */ -#define SYSCON_PIORESCAP_PIORESCAP_MASK (0xFFFFFFFFU) -#define SYSCON_PIORESCAP_PIORESCAP_SHIFT (0U) -#define SYSCON_PIORESCAP_PIORESCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK) - -/* The count of SYSCON_PIORESCAP */ -#define SYSCON_PIORESCAP_COUNT (2U) - -/*! @name PRESETCTRL - Peripheral reset control n */ -#define SYSCON_PRESETCTRL_MRT_RST_MASK (0x1U) -#define SYSCON_PRESETCTRL_MRT_RST_SHIFT (0U) -#define SYSCON_PRESETCTRL_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT_RST_MASK) -#define SYSCON_PRESETCTRL_SCT0_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL_SCT0_RST_SHIFT (2U) -#define SYSCON_PRESETCTRL_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK) -#define SYSCON_PRESETCTRL_LCD_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL_LCD_RST_SHIFT (2U) -#define SYSCON_PRESETCTRL_LCD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_LCD_RST_SHIFT)) & SYSCON_PRESETCTRL_LCD_RST_MASK) -#define SYSCON_PRESETCTRL_SDIO_RST_MASK (0x8U) -#define SYSCON_PRESETCTRL_SDIO_RST_SHIFT (3U) -#define SYSCON_PRESETCTRL_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL_SDIO_RST_MASK) -#define SYSCON_PRESETCTRL_USB1H_RST_MASK (0x10U) -#define SYSCON_PRESETCTRL_USB1H_RST_SHIFT (4U) -#define SYSCON_PRESETCTRL_USB1H_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1H_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1H_RST_MASK) -#define SYSCON_PRESETCTRL_USB1D_RST_MASK (0x20U) -#define SYSCON_PRESETCTRL_USB1D_RST_SHIFT (5U) -#define SYSCON_PRESETCTRL_USB1D_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1D_RST_MASK) -#define SYSCON_PRESETCTRL_USB1RAM_RST_MASK (0x40U) -#define SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT (6U) -#define SYSCON_PRESETCTRL_USB1RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1RAM_RST_MASK) -#define SYSCON_PRESETCTRL_EMC_RESET_MASK (0x80U) -#define SYSCON_PRESETCTRL_EMC_RESET_SHIFT (7U) -#define SYSCON_PRESETCTRL_EMC_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EMC_RESET_SHIFT)) & SYSCON_PRESETCTRL_EMC_RESET_MASK) -#define SYSCON_PRESETCTRL_FLASH_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL_FLASH_RST_SHIFT (7U) -#define SYSCON_PRESETCTRL_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL_FLASH_RST_MASK) -#define SYSCON_PRESETCTRL_MCAN0_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL_MCAN0_RST_SHIFT (7U) -#define SYSCON_PRESETCTRL_MCAN0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN0_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN0_RST_MASK) -#define SYSCON_PRESETCTRL_FMC_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL_FMC_RST_SHIFT (8U) -#define SYSCON_PRESETCTRL_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL_FMC_RST_MASK) -#define SYSCON_PRESETCTRL_ETH_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL_ETH_RST_SHIFT (8U) -#define SYSCON_PRESETCTRL_ETH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ETH_RST_SHIFT)) & SYSCON_PRESETCTRL_ETH_RST_MASK) -#define SYSCON_PRESETCTRL_MCAN1_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL_MCAN1_RST_SHIFT (8U) -#define SYSCON_PRESETCTRL_MCAN1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN1_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN1_RST_MASK) -#define SYSCON_PRESETCTRL_GPIO4_RST_MASK (0x200U) -#define SYSCON_PRESETCTRL_GPIO4_RST_SHIFT (9U) -#define SYSCON_PRESETCTRL_GPIO4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO4_RST_MASK) -#define SYSCON_PRESETCTRL_EEPROM_RST_MASK (0x200U) -#define SYSCON_PRESETCTRL_EEPROM_RST_SHIFT (9U) -#define SYSCON_PRESETCTRL_EEPROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EEPROM_RST_SHIFT)) & SYSCON_PRESETCTRL_EEPROM_RST_MASK) -#define SYSCON_PRESETCTRL_GPIO5_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL_GPIO5_RST_SHIFT (10U) -#define SYSCON_PRESETCTRL_GPIO5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO5_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO5_RST_MASK) -#define SYSCON_PRESETCTRL_UTICK_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL_UTICK_RST_SHIFT (10U) -#define SYSCON_PRESETCTRL_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK_RST_MASK) -#define SYSCON_PRESETCTRL_SPIFI_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL_SPIFI_RST_SHIFT (10U) -#define SYSCON_PRESETCTRL_SPIFI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SPIFI_RST_SHIFT)) & SYSCON_PRESETCTRL_SPIFI_RST_MASK) -#define SYSCON_PRESETCTRL_AES_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL_AES_RST_SHIFT (11U) -#define SYSCON_PRESETCTRL_AES_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_AES_RST_SHIFT)) & SYSCON_PRESETCTRL_AES_RST_MASK) -#define SYSCON_PRESETCTRL_MUX_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL_MUX_RST_SHIFT (11U) -#define SYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK) -#define SYSCON_PRESETCTRL_FC0_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL_FC0_RST_SHIFT (11U) -#define SYSCON_PRESETCTRL_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK) -#define SYSCON_PRESETCTRL_OTP_RST_MASK (0x1000U) -#define SYSCON_PRESETCTRL_OTP_RST_SHIFT (12U) -#define SYSCON_PRESETCTRL_OTP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_OTP_RST_SHIFT)) & SYSCON_PRESETCTRL_OTP_RST_MASK) -#define SYSCON_PRESETCTRL_FC1_RST_MASK (0x1000U) -#define SYSCON_PRESETCTRL_FC1_RST_SHIFT (12U) -#define SYSCON_PRESETCTRL_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK) -#define SYSCON_PRESETCTRL_IOCON_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL_IOCON_RST_SHIFT (13U) -#define SYSCON_PRESETCTRL_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK) -#define SYSCON_PRESETCTRL_RNG_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL_RNG_RST_SHIFT (13U) -#define SYSCON_PRESETCTRL_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL_RNG_RST_MASK) -#define SYSCON_PRESETCTRL_FC2_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL_FC2_RST_SHIFT (13U) -#define SYSCON_PRESETCTRL_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK) -#define SYSCON_PRESETCTRL_FC8_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL_FC8_RST_SHIFT (14U) -#define SYSCON_PRESETCTRL_FC8_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC8_RST_SHIFT)) & SYSCON_PRESETCTRL_FC8_RST_MASK) -#define SYSCON_PRESETCTRL_FC3_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL_FC3_RST_SHIFT (14U) -#define SYSCON_PRESETCTRL_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK) -#define SYSCON_PRESETCTRL_GPIO0_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT (14U) -#define SYSCON_PRESETCTRL_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK) -#define SYSCON_PRESETCTRL_GPIO1_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT (15U) -#define SYSCON_PRESETCTRL_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK) -#define SYSCON_PRESETCTRL_FC9_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL_FC9_RST_SHIFT (15U) -#define SYSCON_PRESETCTRL_FC9_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC9_RST_SHIFT)) & SYSCON_PRESETCTRL_FC9_RST_MASK) -#define SYSCON_PRESETCTRL_FC4_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL_FC4_RST_SHIFT (15U) -#define SYSCON_PRESETCTRL_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK) -#define SYSCON_PRESETCTRL_USB0HMR_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT (16U) -#define SYSCON_PRESETCTRL_USB0HMR_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HMR_RST_MASK) -#define SYSCON_PRESETCTRL_GPIO2_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL_GPIO2_RST_SHIFT (16U) -#define SYSCON_PRESETCTRL_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO2_RST_MASK) -#define SYSCON_PRESETCTRL_FC5_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL_FC5_RST_SHIFT (16U) -#define SYSCON_PRESETCTRL_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK) -#define SYSCON_PRESETCTRL_GPIO3_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL_GPIO3_RST_SHIFT (17U) -#define SYSCON_PRESETCTRL_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO3_RST_MASK) -#define SYSCON_PRESETCTRL_FC6_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL_FC6_RST_SHIFT (17U) -#define SYSCON_PRESETCTRL_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK) -#define SYSCON_PRESETCTRL_USB0HSL_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT (17U) -#define SYSCON_PRESETCTRL_USB0HSL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HSL_RST_MASK) -#define SYSCON_PRESETCTRL_FC7_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL_FC7_RST_SHIFT (18U) -#define SYSCON_PRESETCTRL_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK) -#define SYSCON_PRESETCTRL_SHA_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL_SHA_RST_SHIFT (18U) -#define SYSCON_PRESETCTRL_SHA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SHA_RST_SHIFT)) & SYSCON_PRESETCTRL_SHA_RST_MASK) -#define SYSCON_PRESETCTRL_PINT_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL_PINT_RST_SHIFT (18U) -#define SYSCON_PRESETCTRL_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK) -#define SYSCON_PRESETCTRL_DMIC_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL_DMIC_RST_SHIFT (19U) -#define SYSCON_PRESETCTRL_DMIC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC_RST_MASK) -#define SYSCON_PRESETCTRL_SC0_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL_SC0_RST_SHIFT (19U) -#define SYSCON_PRESETCTRL_SC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC0_RST_SHIFT)) & SYSCON_PRESETCTRL_SC0_RST_MASK) -#define SYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL_GINT_RST_SHIFT (19U) -#define SYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK) -#define SYSCON_PRESETCTRL_SC1_RST_MASK (0x100000U) -#define SYSCON_PRESETCTRL_SC1_RST_SHIFT (20U) -#define SYSCON_PRESETCTRL_SC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC1_RST_SHIFT)) & SYSCON_PRESETCTRL_SC1_RST_MASK) -#define SYSCON_PRESETCTRL_DMA0_RST_MASK (0x100000U) -#define SYSCON_PRESETCTRL_DMA0_RST_SHIFT (20U) -#define SYSCON_PRESETCTRL_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA0_RST_MASK) -#define SYSCON_PRESETCTRL_CRC_RST_MASK (0x200000U) -#define SYSCON_PRESETCTRL_CRC_RST_SHIFT (21U) -#define SYSCON_PRESETCTRL_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK) -#define SYSCON_PRESETCTRL_CTIMER2_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT (22U) -#define SYSCON_PRESETCTRL_CTIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER2_RST_MASK) -#define SYSCON_PRESETCTRL_WWDT_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL_WWDT_RST_SHIFT (22U) -#define SYSCON_PRESETCTRL_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK) -#define SYSCON_PRESETCTRL_USB0D_RST_MASK (0x2000000U) -#define SYSCON_PRESETCTRL_USB0D_RST_SHIFT (25U) -#define SYSCON_PRESETCTRL_USB0D_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0D_RST_MASK) -#define SYSCON_PRESETCTRL_CTIMER0_RST_MASK (0x4000000U) -#define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT (26U) -#define SYSCON_PRESETCTRL_CTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK) -#define SYSCON_PRESETCTRL_ADC0_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL_ADC0_RST_SHIFT (27U) -#define SYSCON_PRESETCTRL_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK) -#define SYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U) -#define SYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK) - -/* The count of SYSCON_PRESETCTRL */ -#define SYSCON_PRESETCTRL_COUNT (3U) - -/*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */ -#define SYSCON_PRESETCTRLSET_RST_SET_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLSET_RST_SET_SHIFT (0U) -#define SYSCON_PRESETCTRLSET_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK) - -/* The count of SYSCON_PRESETCTRLSET */ -#define SYSCON_PRESETCTRLSET_COUNT (3U) - -/*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */ -#define SYSCON_PRESETCTRLCLR_RST_CLR_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT (0U) -#define SYSCON_PRESETCTRLCLR_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK) - -/* The count of SYSCON_PRESETCTRLCLR */ -#define SYSCON_PRESETCTRLCLR_COUNT (3U) - -/*! @name SYSRSTSTAT - System reset status register */ -#define SYSCON_SYSRSTSTAT_POR_MASK (0x1U) -#define SYSCON_SYSRSTSTAT_POR_SHIFT (0U) -#define SYSCON_SYSRSTSTAT_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK) -#define SYSCON_SYSRSTSTAT_EXTRST_MASK (0x2U) -#define SYSCON_SYSRSTSTAT_EXTRST_SHIFT (1U) -#define SYSCON_SYSRSTSTAT_EXTRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK) -#define SYSCON_SYSRSTSTAT_WDT_MASK (0x4U) -#define SYSCON_SYSRSTSTAT_WDT_SHIFT (2U) -#define SYSCON_SYSRSTSTAT_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK) -#define SYSCON_SYSRSTSTAT_BOD_MASK (0x8U) -#define SYSCON_SYSRSTSTAT_BOD_SHIFT (3U) -#define SYSCON_SYSRSTSTAT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK) -#define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U) -#define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U) -#define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK) - -/*! @name AHBCLKCTRL - AHB Clock control n */ -#define SYSCON_AHBCLKCTRL_MRT_MASK (0x1U) -#define SYSCON_AHBCLKCTRL_MRT_SHIFT (0U) -#define SYSCON_AHBCLKCTRL_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT_SHIFT)) & SYSCON_AHBCLKCTRL_MRT_MASK) -#define SYSCON_AHBCLKCTRL_RIT_MASK (0x2U) -#define SYSCON_AHBCLKCTRL_RIT_SHIFT (1U) -#define SYSCON_AHBCLKCTRL_RIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RIT_SHIFT)) & SYSCON_AHBCLKCTRL_RIT_MASK) -#define SYSCON_AHBCLKCTRL_ROM_MASK (0x2U) -#define SYSCON_AHBCLKCTRL_ROM_SHIFT (1U) -#define SYSCON_AHBCLKCTRL_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK) -#define SYSCON_AHBCLKCTRL_SCT0_MASK (0x4U) -#define SYSCON_AHBCLKCTRL_SCT0_SHIFT (2U) -#define SYSCON_AHBCLKCTRL_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK) -#define SYSCON_AHBCLKCTRL_LCD_MASK (0x4U) -#define SYSCON_AHBCLKCTRL_LCD_SHIFT (2U) -#define SYSCON_AHBCLKCTRL_LCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_LCD_SHIFT)) & SYSCON_AHBCLKCTRL_LCD_MASK) -#define SYSCON_AHBCLKCTRL_SRAM1_MASK (0x8U) -#define SYSCON_AHBCLKCTRL_SRAM1_SHIFT (3U) -#define SYSCON_AHBCLKCTRL_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM1_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM1_MASK) -#define SYSCON_AHBCLKCTRL_SDIO_MASK (0x8U) -#define SYSCON_AHBCLKCTRL_SDIO_SHIFT (3U) -#define SYSCON_AHBCLKCTRL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL_SDIO_MASK) -#define SYSCON_AHBCLKCTRL_SRAM2_MASK (0x10U) -#define SYSCON_AHBCLKCTRL_SRAM2_SHIFT (4U) -#define SYSCON_AHBCLKCTRL_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM2_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM2_MASK) -#define SYSCON_AHBCLKCTRL_USB1H_MASK (0x10U) -#define SYSCON_AHBCLKCTRL_USB1H_SHIFT (4U) -#define SYSCON_AHBCLKCTRL_USB1H(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1H_SHIFT)) & SYSCON_AHBCLKCTRL_USB1H_MASK) -#define SYSCON_AHBCLKCTRL_SRAM3_MASK (0x20U) -#define SYSCON_AHBCLKCTRL_SRAM3_SHIFT (5U) -#define SYSCON_AHBCLKCTRL_SRAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM3_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM3_MASK) -#define SYSCON_AHBCLKCTRL_USB1D_MASK (0x20U) -#define SYSCON_AHBCLKCTRL_USB1D_SHIFT (5U) -#define SYSCON_AHBCLKCTRL_USB1D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1D_SHIFT)) & SYSCON_AHBCLKCTRL_USB1D_MASK) -#define SYSCON_AHBCLKCTRL_USB1RAM_MASK (0x40U) -#define SYSCON_AHBCLKCTRL_USB1RAM_SHIFT (6U) -#define SYSCON_AHBCLKCTRL_USB1RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1RAM_SHIFT)) & SYSCON_AHBCLKCTRL_USB1RAM_MASK) -#define SYSCON_AHBCLKCTRL_FLASH_MASK (0x80U) -#define SYSCON_AHBCLKCTRL_FLASH_SHIFT (7U) -#define SYSCON_AHBCLKCTRL_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL_FLASH_MASK) -#define SYSCON_AHBCLKCTRL_EMC_MASK (0x80U) -#define SYSCON_AHBCLKCTRL_EMC_SHIFT (7U) -#define SYSCON_AHBCLKCTRL_EMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EMC_SHIFT)) & SYSCON_AHBCLKCTRL_EMC_MASK) -#define SYSCON_AHBCLKCTRL_MCAN0_MASK (0x80U) -#define SYSCON_AHBCLKCTRL_MCAN0_SHIFT (7U) -#define SYSCON_AHBCLKCTRL_MCAN0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN0_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN0_MASK) -#define SYSCON_AHBCLKCTRL_FMC_MASK (0x100U) -#define SYSCON_AHBCLKCTRL_FMC_SHIFT (8U) -#define SYSCON_AHBCLKCTRL_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FMC_SHIFT)) & SYSCON_AHBCLKCTRL_FMC_MASK) -#define SYSCON_AHBCLKCTRL_ETH_MASK (0x100U) -#define SYSCON_AHBCLKCTRL_ETH_SHIFT (8U) -#define SYSCON_AHBCLKCTRL_ETH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ETH_SHIFT)) & SYSCON_AHBCLKCTRL_ETH_MASK) -#define SYSCON_AHBCLKCTRL_MCAN1_MASK (0x100U) -#define SYSCON_AHBCLKCTRL_MCAN1_SHIFT (8U) -#define SYSCON_AHBCLKCTRL_MCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN1_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN1_MASK) -#define SYSCON_AHBCLKCTRL_EEPROM_MASK (0x200U) -#define SYSCON_AHBCLKCTRL_EEPROM_SHIFT (9U) -#define SYSCON_AHBCLKCTRL_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EEPROM_SHIFT)) & SYSCON_AHBCLKCTRL_EEPROM_MASK) -#define SYSCON_AHBCLKCTRL_GPIO4_MASK (0x200U) -#define SYSCON_AHBCLKCTRL_GPIO4_SHIFT (9U) -#define SYSCON_AHBCLKCTRL_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO4_MASK) -#define SYSCON_AHBCLKCTRL_GPIO5_MASK (0x400U) -#define SYSCON_AHBCLKCTRL_GPIO5_SHIFT (10U) -#define SYSCON_AHBCLKCTRL_GPIO5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO5_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO5_MASK) -#define SYSCON_AHBCLKCTRL_UTICK_MASK (0x400U) -#define SYSCON_AHBCLKCTRL_UTICK_SHIFT (10U) -#define SYSCON_AHBCLKCTRL_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK_MASK) -#define SYSCON_AHBCLKCTRL_SPIFI_MASK (0x400U) -#define SYSCON_AHBCLKCTRL_SPIFI_SHIFT (10U) -#define SYSCON_AHBCLKCTRL_SPIFI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SPIFI_SHIFT)) & SYSCON_AHBCLKCTRL_SPIFI_MASK) -#define SYSCON_AHBCLKCTRL_INPUTMUX_MASK (0x800U) -#define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT (11U) -#define SYSCON_AHBCLKCTRL_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK) -#define SYSCON_AHBCLKCTRL_AES_MASK (0x800U) -#define SYSCON_AHBCLKCTRL_AES_SHIFT (11U) -#define SYSCON_AHBCLKCTRL_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_AES_SHIFT)) & SYSCON_AHBCLKCTRL_AES_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK (0x800U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT (11U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK) -#define SYSCON_AHBCLKCTRL_OTP_MASK (0x1000U) -#define SYSCON_AHBCLKCTRL_OTP_SHIFT (12U) -#define SYSCON_AHBCLKCTRL_OTP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_OTP_SHIFT)) & SYSCON_AHBCLKCTRL_OTP_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK (0x1000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT (12U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK) -#define SYSCON_AHBCLKCTRL_RNG_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL_RNG_SHIFT (13U) -#define SYSCON_AHBCLKCTRL_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RNG_SHIFT)) & SYSCON_AHBCLKCTRL_RNG_MASK) -#define SYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL_IOCON_SHIFT (13U) -#define SYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT (13U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK) -#define SYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U) -#define SYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT (14U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT (14U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT (15U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT (15U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK) -#define SYSCON_AHBCLKCTRL_GPIO1_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL_GPIO1_SHIFT (15U) -#define SYSCON_AHBCLKCTRL_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK) -#define SYSCON_AHBCLKCTRL_GPIO2_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL_GPIO2_SHIFT (16U) -#define SYSCON_AHBCLKCTRL_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO2_MASK) -#define SYSCON_AHBCLKCTRL_USB0HMR_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL_USB0HMR_SHIFT (16U) -#define SYSCON_AHBCLKCTRL_USB0HMR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HMR_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HMR_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT (16U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT (17U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK) -#define SYSCON_AHBCLKCTRL_GPIO3_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL_GPIO3_SHIFT (17U) -#define SYSCON_AHBCLKCTRL_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO3_MASK) -#define SYSCON_AHBCLKCTRL_USB0HSL_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL_USB0HSL_SHIFT (17U) -#define SYSCON_AHBCLKCTRL_USB0HSL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HSL_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HSL_MASK) -#define SYSCON_AHBCLKCTRL_PINT_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL_PINT_SHIFT (18U) -#define SYSCON_AHBCLKCTRL_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK) -#define SYSCON_AHBCLKCTRL_SHA0_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL_SHA0_SHIFT (18U) -#define SYSCON_AHBCLKCTRL_SHA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SHA0_SHIFT)) & SYSCON_AHBCLKCTRL_SHA0_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT (18U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK) -#define SYSCON_AHBCLKCTRL_DMIC_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL_DMIC_SHIFT (19U) -#define SYSCON_AHBCLKCTRL_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC_MASK) -#define SYSCON_AHBCLKCTRL_GINT_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL_GINT_SHIFT (19U) -#define SYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK) -#define SYSCON_AHBCLKCTRL_SC0_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL_SC0_SHIFT (19U) -#define SYSCON_AHBCLKCTRL_SC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC0_SHIFT)) & SYSCON_AHBCLKCTRL_SC0_MASK) -#define SYSCON_AHBCLKCTRL_SC1_MASK (0x100000U) -#define SYSCON_AHBCLKCTRL_SC1_SHIFT (20U) -#define SYSCON_AHBCLKCTRL_SC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC1_SHIFT)) & SYSCON_AHBCLKCTRL_SC1_MASK) -#define SYSCON_AHBCLKCTRL_DMA_MASK (0x100000U) -#define SYSCON_AHBCLKCTRL_DMA_SHIFT (20U) -#define SYSCON_AHBCLKCTRL_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA_SHIFT)) & SYSCON_AHBCLKCTRL_DMA_MASK) -#define SYSCON_AHBCLKCTRL_CRC_MASK (0x200000U) -#define SYSCON_AHBCLKCTRL_CRC_SHIFT (21U) -#define SYSCON_AHBCLKCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK) -#define SYSCON_AHBCLKCTRL_WWDT_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL_WWDT_SHIFT (22U) -#define SYSCON_AHBCLKCTRL_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK) -#define SYSCON_AHBCLKCTRL_CTIMER2_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL_CTIMER2_SHIFT (22U) -#define SYSCON_AHBCLKCTRL_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER2_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER2_MASK) -#define SYSCON_AHBCLKCTRL_RTC_MASK (0x800000U) -#define SYSCON_AHBCLKCTRL_RTC_SHIFT (23U) -#define SYSCON_AHBCLKCTRL_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK) -#define SYSCON_AHBCLKCTRL_USB0D_MASK (0x2000000U) -#define SYSCON_AHBCLKCTRL_USB0D_SHIFT (25U) -#define SYSCON_AHBCLKCTRL_USB0D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0D_SHIFT)) & SYSCON_AHBCLKCTRL_USB0D_MASK) -#define SYSCON_AHBCLKCTRL_CTIMER0_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT (26U) -#define SYSCON_AHBCLKCTRL_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK) -#define SYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U) -#define SYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK) -#define SYSCON_AHBCLKCTRL_ADC0_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL_ADC0_SHIFT (27U) -#define SYSCON_AHBCLKCTRL_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK) - -/* The count of SYSCON_AHBCLKCTRL */ -#define SYSCON_AHBCLKCTRL_COUNT (3U) - -/*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */ -#define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT (0U) -#define SYSCON_AHBCLKCTRLSET_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK) - -/* The count of SYSCON_AHBCLKCTRLSET */ -#define SYSCON_AHBCLKCTRLSET_COUNT (3U) - -/*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */ -#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT (0U) -#define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK) - -/* The count of SYSCON_AHBCLKCTRLCLR */ -#define SYSCON_AHBCLKCTRLCLR_COUNT (3U) - -/*! @name MAINCLKSELA - Main clock source select A */ -#define SYSCON_MAINCLKSELA_SEL_MASK (0x3U) -#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) -#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) - -/*! @name MAINCLKSELB - Main clock source select B */ -#define SYSCON_MAINCLKSELB_SEL_MASK (0x3U) -#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) -#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) - -/*! @name CLKOUTSELA - CLKOUT clock source select A */ -#define SYSCON_CLKOUTSELA_SEL_MASK (0x7U) -#define SYSCON_CLKOUTSELA_SEL_SHIFT (0U) -#define SYSCON_CLKOUTSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK) - -/*! @name SYSPLLCLKSEL - PLL clock source select */ -#define SYSCON_SYSPLLCLKSEL_SEL_MASK (0x7U) -#define SYSCON_SYSPLLCLKSEL_SEL_SHIFT (0U) -#define SYSCON_SYSPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK) - -/*! @name AUDPLLCLKSEL - Audio PLL clock source select */ -#define SYSCON_AUDPLLCLKSEL_SEL_MASK (0x7U) -#define SYSCON_AUDPLLCLKSEL_SEL_SHIFT (0U) -#define SYSCON_AUDPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCLKSEL_SEL_SHIFT)) & SYSCON_AUDPLLCLKSEL_SEL_MASK) - -/*! @name SPIFICLKSEL - SPIFI clock source select */ -#define SYSCON_SPIFICLKSEL_SEL_MASK (0x7U) -#define SYSCON_SPIFICLKSEL_SEL_SHIFT (0U) -#define SYSCON_SPIFICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK) - -/*! @name ADCCLKSEL - ADC clock source select */ -#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) -#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) -#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) - -/*! @name USB0CLKSEL - USB0 clock source select */ -#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) -#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) -#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) - -/*! @name USB1CLKSEL - USB1 clock source select */ -#define SYSCON_USB1CLKSEL_SEL_MASK (0x7U) -#define SYSCON_USB1CLKSEL_SEL_SHIFT (0U) -#define SYSCON_USB1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSEL_SEL_SHIFT)) & SYSCON_USB1CLKSEL_SEL_MASK) - -/*! @name FCLKSEL - Flexcomm 0 clock source select */ -#define SYSCON_FCLKSEL_SEL_MASK (0x7U) -#define SYSCON_FCLKSEL_SEL_SHIFT (0U) -#define SYSCON_FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCLKSEL_SEL_SHIFT)) & SYSCON_FCLKSEL_SEL_MASK) - -/* The count of SYSCON_FCLKSEL */ -#define SYSCON_FCLKSEL_COUNT (10U) - -/*! @name MCLKCLKSEL - MCLK clock source select */ -#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) -#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) -#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) - -/*! @name FRGCLKSEL - Fractional Rate Generator clock source select */ -#define SYSCON_FRGCLKSEL_SEL_MASK (0x7U) -#define SYSCON_FRGCLKSEL_SEL_SHIFT (0U) -#define SYSCON_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK) - -/*! @name DMICCLKSEL - Digital microphone (DMIC) subsystem clock select */ -#define SYSCON_DMICCLKSEL_SEL_MASK (0x7U) -#define SYSCON_DMICCLKSEL_SEL_SHIFT (0U) -#define SYSCON_DMICCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK) - -/*! @name SCTCLKSEL - SCTimer/PWM clock source select */ -#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) -#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) -#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) - -/*! @name LCDCLKSEL - LCD clock source select */ -#define SYSCON_LCDCLKSEL_SEL_MASK (0x3U) -#define SYSCON_LCDCLKSEL_SEL_SHIFT (0U) -#define SYSCON_LCDCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKSEL_SEL_SHIFT)) & SYSCON_LCDCLKSEL_SEL_MASK) - -/*! @name SDIOCLKSEL - SDIO clock source select */ -#define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U) -#define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U) -#define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK) - -/*! @name SYSTICKCLKDIV - SYSTICK clock divider */ -#define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U) -#define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK) -#define SYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U) -#define SYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK) -#define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U) -#define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK) -#define SYSCON_SYSTICKCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT (31U) -#define SYSCON_SYSTICKCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV_REQFLAG_MASK) - -/*! @name ARMTRACECLKDIV - ARM Trace clock divider */ -#define SYSCON_ARMTRACECLKDIV_DIV_MASK (0xFFU) -#define SYSCON_ARMTRACECLKDIV_DIV_SHIFT (0U) -#define SYSCON_ARMTRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_DIV_SHIFT)) & SYSCON_ARMTRACECLKDIV_DIV_MASK) -#define SYSCON_ARMTRACECLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_ARMTRACECLKDIV_RESET_SHIFT (29U) -#define SYSCON_ARMTRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_RESET_SHIFT)) & SYSCON_ARMTRACECLKDIV_RESET_MASK) -#define SYSCON_ARMTRACECLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_ARMTRACECLKDIV_HALT_SHIFT (30U) -#define SYSCON_ARMTRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_HALT_SHIFT)) & SYSCON_ARMTRACECLKDIV_HALT_MASK) -#define SYSCON_ARMTRACECLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT (31U) -#define SYSCON_ARMTRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_ARMTRACECLKDIV_REQFLAG_MASK) - -/*! @name CAN0CLKDIV - MCAN0 clock divider */ -#define SYSCON_CAN0CLKDIV_DIV_MASK (0xFFU) -#define SYSCON_CAN0CLKDIV_DIV_SHIFT (0U) -#define SYSCON_CAN0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_DIV_SHIFT)) & SYSCON_CAN0CLKDIV_DIV_MASK) -#define SYSCON_CAN0CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_CAN0CLKDIV_RESET_SHIFT (29U) -#define SYSCON_CAN0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_RESET_SHIFT)) & SYSCON_CAN0CLKDIV_RESET_MASK) -#define SYSCON_CAN0CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_CAN0CLKDIV_HALT_SHIFT (30U) -#define SYSCON_CAN0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_HALT_SHIFT)) & SYSCON_CAN0CLKDIV_HALT_MASK) -#define SYSCON_CAN0CLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_CAN0CLKDIV_REQFLAG_SHIFT (31U) -#define SYSCON_CAN0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN0CLKDIV_REQFLAG_MASK) - -/*! @name CAN1CLKDIV - MCAN1 clock divider */ -#define SYSCON_CAN1CLKDIV_DIV_MASK (0xFFU) -#define SYSCON_CAN1CLKDIV_DIV_SHIFT (0U) -#define SYSCON_CAN1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_DIV_SHIFT)) & SYSCON_CAN1CLKDIV_DIV_MASK) -#define SYSCON_CAN1CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_CAN1CLKDIV_RESET_SHIFT (29U) -#define SYSCON_CAN1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_RESET_SHIFT)) & SYSCON_CAN1CLKDIV_RESET_MASK) -#define SYSCON_CAN1CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_CAN1CLKDIV_HALT_SHIFT (30U) -#define SYSCON_CAN1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_HALT_SHIFT)) & SYSCON_CAN1CLKDIV_HALT_MASK) -#define SYSCON_CAN1CLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_CAN1CLKDIV_REQFLAG_SHIFT (31U) -#define SYSCON_CAN1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN1CLKDIV_REQFLAG_MASK) - -/*! @name SC0CLKDIV - Smartcard0 clock divider */ -#define SYSCON_SC0CLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SC0CLKDIV_DIV_SHIFT (0U) -#define SYSCON_SC0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_DIV_SHIFT)) & SYSCON_SC0CLKDIV_DIV_MASK) -#define SYSCON_SC0CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SC0CLKDIV_RESET_SHIFT (29U) -#define SYSCON_SC0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_RESET_SHIFT)) & SYSCON_SC0CLKDIV_RESET_MASK) -#define SYSCON_SC0CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SC0CLKDIV_HALT_SHIFT (30U) -#define SYSCON_SC0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_HALT_SHIFT)) & SYSCON_SC0CLKDIV_HALT_MASK) -#define SYSCON_SC0CLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_SC0CLKDIV_REQFLAG_SHIFT (31U) -#define SYSCON_SC0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC0CLKDIV_REQFLAG_MASK) - -/*! @name SC1CLKDIV - Smartcard1 clock divider */ -#define SYSCON_SC1CLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SC1CLKDIV_DIV_SHIFT (0U) -#define SYSCON_SC1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_DIV_SHIFT)) & SYSCON_SC1CLKDIV_DIV_MASK) -#define SYSCON_SC1CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SC1CLKDIV_RESET_SHIFT (29U) -#define SYSCON_SC1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_RESET_SHIFT)) & SYSCON_SC1CLKDIV_RESET_MASK) -#define SYSCON_SC1CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SC1CLKDIV_HALT_SHIFT (30U) -#define SYSCON_SC1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_HALT_SHIFT)) & SYSCON_SC1CLKDIV_HALT_MASK) -#define SYSCON_SC1CLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_SC1CLKDIV_REQFLAG_SHIFT (31U) -#define SYSCON_SC1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC1CLKDIV_REQFLAG_MASK) - -/*! @name AHBCLKDIV - AHB clock divider */ -#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) -#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) -#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U) -#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK) - -/*! @name CLKOUTDIV - CLKOUT clock divider */ -#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) -#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) -#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) -#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) -#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) -#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) -#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) -#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) -#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) -#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U) -#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK) - -/*! @name FROHFCLKDIV - FROHF clock divider */ -#define SYSCON_FROHFCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_FROHFCLKDIV_DIV_SHIFT (0U) -#define SYSCON_FROHFCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_DIV_SHIFT)) & SYSCON_FROHFCLKDIV_DIV_MASK) -#define SYSCON_FROHFCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_FROHFCLKDIV_RESET_SHIFT (29U) -#define SYSCON_FROHFCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_RESET_SHIFT)) & SYSCON_FROHFCLKDIV_RESET_MASK) -#define SYSCON_FROHFCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_FROHFCLKDIV_HALT_SHIFT (30U) -#define SYSCON_FROHFCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_HALT_SHIFT)) & SYSCON_FROHFCLKDIV_HALT_MASK) -#define SYSCON_FROHFCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_FROHFCLKDIV_REQFLAG_SHIFT (31U) -#define SYSCON_FROHFCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_REQFLAG_SHIFT)) & SYSCON_FROHFCLKDIV_REQFLAG_MASK) - -/*! @name SPIFICLKDIV - SPIFI clock divider */ -#define SYSCON_SPIFICLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SPIFICLKDIV_DIV_SHIFT (0U) -#define SYSCON_SPIFICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK) -#define SYSCON_SPIFICLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SPIFICLKDIV_RESET_SHIFT (29U) -#define SYSCON_SPIFICLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_RESET_SHIFT)) & SYSCON_SPIFICLKDIV_RESET_MASK) -#define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SPIFICLKDIV_HALT_SHIFT (30U) -#define SYSCON_SPIFICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK) -#define SYSCON_SPIFICLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_SPIFICLKDIV_REQFLAG_SHIFT (31U) -#define SYSCON_SPIFICLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_REQFLAG_SHIFT)) & SYSCON_SPIFICLKDIV_REQFLAG_MASK) - -/*! @name ADCCLKDIV - ADC clock divider */ -#define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) -#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) -#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) -#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) -#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) -#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) -#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U) -#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK) - -/*! @name USB0CLKDIV - USB0 clock divider */ -#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) -#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) -#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) -#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) -#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) -#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) -#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) -#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U) -#define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK) - -/*! @name USB1CLKDIV - USB1 clock divider */ -#define SYSCON_USB1CLKDIV_DIV_MASK (0xFFU) -#define SYSCON_USB1CLKDIV_DIV_SHIFT (0U) -#define SYSCON_USB1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_DIV_SHIFT)) & SYSCON_USB1CLKDIV_DIV_MASK) -#define SYSCON_USB1CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_USB1CLKDIV_RESET_SHIFT (29U) -#define SYSCON_USB1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_RESET_SHIFT)) & SYSCON_USB1CLKDIV_RESET_MASK) -#define SYSCON_USB1CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_USB1CLKDIV_HALT_SHIFT (30U) -#define SYSCON_USB1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_HALT_SHIFT)) & SYSCON_USB1CLKDIV_HALT_MASK) -#define SYSCON_USB1CLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_USB1CLKDIV_REQFLAG_SHIFT (31U) -#define SYSCON_USB1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB1CLKDIV_REQFLAG_MASK) - -/*! @name FRGCTRL - Fractional rate divider */ -#define SYSCON_FRGCTRL_DIV_MASK (0xFFU) -#define SYSCON_FRGCTRL_DIV_SHIFT (0U) -#define SYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK) -#define SYSCON_FRGCTRL_MULT_MASK (0xFF00U) -#define SYSCON_FRGCTRL_MULT_SHIFT (8U) -#define SYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK) - -/*! @name DMICCLKDIV - DMIC clock divider */ -#define SYSCON_DMICCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_DMICCLKDIV_DIV_SHIFT (0U) -#define SYSCON_DMICCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK) -#define SYSCON_DMICCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_DMICCLKDIV_RESET_SHIFT (29U) -#define SYSCON_DMICCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_RESET_SHIFT)) & SYSCON_DMICCLKDIV_RESET_MASK) -#define SYSCON_DMICCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_DMICCLKDIV_HALT_SHIFT (30U) -#define SYSCON_DMICCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK) -#define SYSCON_DMICCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_DMICCLKDIV_REQFLAG_SHIFT (31U) -#define SYSCON_DMICCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_REQFLAG_SHIFT)) & SYSCON_DMICCLKDIV_REQFLAG_MASK) - -/*! @name MCLKDIV - I2S MCLK clock divider */ -#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_MCLKDIV_DIV_SHIFT (0U) -#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) -#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_MCLKDIV_RESET_SHIFT (29U) -#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) -#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_MCLKDIV_HALT_SHIFT (30U) -#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) -#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U) -#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK) - -/*! @name LCDCLKDIV - LCD clock divider */ -#define SYSCON_LCDCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_LCDCLKDIV_DIV_SHIFT (0U) -#define SYSCON_LCDCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_DIV_SHIFT)) & SYSCON_LCDCLKDIV_DIV_MASK) -#define SYSCON_LCDCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_LCDCLKDIV_RESET_SHIFT (29U) -#define SYSCON_LCDCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_RESET_SHIFT)) & SYSCON_LCDCLKDIV_RESET_MASK) -#define SYSCON_LCDCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_LCDCLKDIV_HALT_SHIFT (30U) -#define SYSCON_LCDCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_HALT_SHIFT)) & SYSCON_LCDCLKDIV_HALT_MASK) -#define SYSCON_LCDCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_LCDCLKDIV_REQFLAG_SHIFT (31U) -#define SYSCON_LCDCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_REQFLAG_SHIFT)) & SYSCON_LCDCLKDIV_REQFLAG_MASK) - -/*! @name SCTCLKDIV - SCT/PWM clock divider */ -#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) -#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) -#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) -#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) -#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) -#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) -#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U) -#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK) - -/*! @name EMCCLKDIV - EMC clock divider */ -#define SYSCON_EMCCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_EMCCLKDIV_DIV_SHIFT (0U) -#define SYSCON_EMCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_DIV_SHIFT)) & SYSCON_EMCCLKDIV_DIV_MASK) -#define SYSCON_EMCCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_EMCCLKDIV_RESET_SHIFT (29U) -#define SYSCON_EMCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_RESET_SHIFT)) & SYSCON_EMCCLKDIV_RESET_MASK) -#define SYSCON_EMCCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_EMCCLKDIV_HALT_SHIFT (30U) -#define SYSCON_EMCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_HALT_SHIFT)) & SYSCON_EMCCLKDIV_HALT_MASK) -#define SYSCON_EMCCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_EMCCLKDIV_REQFLAG_SHIFT (31U) -#define SYSCON_EMCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_REQFLAG_SHIFT)) & SYSCON_EMCCLKDIV_REQFLAG_MASK) - -/*! @name SDIOCLKDIV - SDIO clock divider */ -#define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U) -#define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK) -#define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U) -#define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK) -#define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U) -#define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK) -#define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U) -#define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK) - -/*! @name FLASHCFG - Flash wait states configuration */ -#define SYSCON_FLASHCFG_FETCHCFG_MASK (0x3U) -#define SYSCON_FLASHCFG_FETCHCFG_SHIFT (0U) -#define SYSCON_FLASHCFG_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FETCHCFG_SHIFT)) & SYSCON_FLASHCFG_FETCHCFG_MASK) -#define SYSCON_FLASHCFG_DATACFG_MASK (0xCU) -#define SYSCON_FLASHCFG_DATACFG_SHIFT (2U) -#define SYSCON_FLASHCFG_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_DATACFG_SHIFT)) & SYSCON_FLASHCFG_DATACFG_MASK) -#define SYSCON_FLASHCFG_ACCEL_MASK (0x10U) -#define SYSCON_FLASHCFG_ACCEL_SHIFT (4U) -#define SYSCON_FLASHCFG_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_ACCEL_SHIFT)) & SYSCON_FLASHCFG_ACCEL_MASK) -#define SYSCON_FLASHCFG_PREFEN_MASK (0x20U) -#define SYSCON_FLASHCFG_PREFEN_SHIFT (5U) -#define SYSCON_FLASHCFG_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFEN_SHIFT)) & SYSCON_FLASHCFG_PREFEN_MASK) -#define SYSCON_FLASHCFG_PREFOVR_MASK (0x40U) -#define SYSCON_FLASHCFG_PREFOVR_SHIFT (6U) -#define SYSCON_FLASHCFG_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFOVR_SHIFT)) & SYSCON_FLASHCFG_PREFOVR_MASK) -#define SYSCON_FLASHCFG_FLASHTIM_MASK (0xF000U) -#define SYSCON_FLASHCFG_FLASHTIM_SHIFT (12U) -#define SYSCON_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FLASHTIM_SHIFT)) & SYSCON_FLASHCFG_FLASHTIM_MASK) - -/*! @name USB0CLKCTRL - USB0 clock control */ -#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U) -#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U) -#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK) -#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U) -#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U) -#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK) -#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U) -#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U) -#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK) -#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U) -#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U) -#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK) -#define SYSCON_USB0CLKCTRL_PU_DISABLE_MASK (0x10U) -#define SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT (4U) -#define SYSCON_USB0CLKCTRL_PU_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT)) & SYSCON_USB0CLKCTRL_PU_DISABLE_MASK) - -/*! @name USB0CLKSTAT - USB0 clock status */ -#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK (0x1U) -#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT (0U) -#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK) -#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK (0x2U) -#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U) -#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK) - -/*! @name FREQMECTRL - Frequency measure register */ -#define SYSCON_FREQMECTRL_CAPVAL_MASK (0x3FFFU) -#define SYSCON_FREQMECTRL_CAPVAL_SHIFT (0U) -#define SYSCON_FREQMECTRL_CAPVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK) -#define SYSCON_FREQMECTRL_PROG_MASK (0x80000000U) -#define SYSCON_FREQMECTRL_PROG_SHIFT (31U) -#define SYSCON_FREQMECTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK) - -/*! @name MCLKIO - MCLK input/output control */ -#define SYSCON_MCLKIO_DIR_MASK (0x1U) -#define SYSCON_MCLKIO_DIR_SHIFT (0U) -#define SYSCON_MCLKIO_DIR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK) - -/*! @name USB1CLKCTRL - USB1 clock control */ -#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U) -#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U) -#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK) -#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U) -#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U) -#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK) -#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U) -#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U) -#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK) -#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U) -#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U) -#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK) -#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U) -#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U) -#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK) - -/*! @name USB1CLKSTAT - USB1 clock status */ -#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK (0x1U) -#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT (0U) -#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK) -#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK (0x2U) -#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT (1U) -#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK) - -/*! @name EMCSYSCTRL - EMC system control */ -#define SYSCON_EMCSYSCTRL_EMCSC_MASK (0x1U) -#define SYSCON_EMCSYSCTRL_EMCSC_SHIFT (0U) -#define SYSCON_EMCSYSCTRL_EMCSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCSC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCSC_MASK) -#define SYSCON_EMCSYSCTRL_EMCRD_MASK (0x2U) -#define SYSCON_EMCSYSCTRL_EMCRD_SHIFT (1U) -#define SYSCON_EMCSYSCTRL_EMCRD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCRD_SHIFT)) & SYSCON_EMCSYSCTRL_EMCRD_MASK) -#define SYSCON_EMCSYSCTRL_EMCBC_MASK (0x4U) -#define SYSCON_EMCSYSCTRL_EMCBC_SHIFT (2U) -#define SYSCON_EMCSYSCTRL_EMCBC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCBC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCBC_MASK) -#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK (0x8U) -#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT (3U) -#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT)) & SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK) - -/*! @name EMCDLYCTRL - EMC clock delay control */ -#define SYSCON_EMCDLYCTRL_CMD_DELAY_MASK (0x1FU) -#define SYSCON_EMCDLYCTRL_CMD_DELAY_SHIFT (0U) -#define SYSCON_EMCDLYCTRL_CMD_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCTRL_CMD_DELAY_SHIFT)) & SYSCON_EMCDLYCTRL_CMD_DELAY_MASK) -#define SYSCON_EMCDLYCTRL_FBCLK_DELAY_MASK (0x1F00U) -#define SYSCON_EMCDLYCTRL_FBCLK_DELAY_SHIFT (8U) -#define SYSCON_EMCDLYCTRL_FBCLK_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCTRL_FBCLK_DELAY_SHIFT)) & SYSCON_EMCDLYCTRL_FBCLK_DELAY_MASK) - -/*! @name EMCDLYCAL - EMC delay chain calibration control */ -#define SYSCON_EMCDLYCAL_CALVALUE_MASK (0xFFU) -#define SYSCON_EMCDLYCAL_CALVALUE_SHIFT (0U) -#define SYSCON_EMCDLYCAL_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_CALVALUE_SHIFT)) & SYSCON_EMCDLYCAL_CALVALUE_MASK) -#define SYSCON_EMCDLYCAL_START_MASK (0x4000U) -#define SYSCON_EMCDLYCAL_START_SHIFT (14U) -#define SYSCON_EMCDLYCAL_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_START_SHIFT)) & SYSCON_EMCDLYCAL_START_MASK) -#define SYSCON_EMCDLYCAL_DONE_MASK (0x8000U) -#define SYSCON_EMCDLYCAL_DONE_SHIFT (15U) -#define SYSCON_EMCDLYCAL_DONE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_DONE_SHIFT)) & SYSCON_EMCDLYCAL_DONE_MASK) - -/*! @name ETHPHYSEL - Ethernet PHY Selection */ -#define SYSCON_ETHPHYSEL_PHY_SEL_MASK (0x4U) -#define SYSCON_ETHPHYSEL_PHY_SEL_SHIFT (2U) -#define SYSCON_ETHPHYSEL_PHY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHPHYSEL_PHY_SEL_SHIFT)) & SYSCON_ETHPHYSEL_PHY_SEL_MASK) - -/*! @name ETHSBDCTRL - Ethernet SBD flow control */ -#define SYSCON_ETHSBDCTRL_SBD_CTRL_MASK (0x3U) -#define SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT (0U) -#define SYSCON_ETHSBDCTRL_SBD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT)) & SYSCON_ETHSBDCTRL_SBD_CTRL_MASK) - -/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */ -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK) -#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) -#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U) -#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK) - -/*! @name FROCTRL - FRO oscillator control */ -#define SYSCON_FROCTRL_TRIM_MASK (0x3FFFU) -#define SYSCON_FROCTRL_TRIM_SHIFT (0U) -#define SYSCON_FROCTRL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_TRIM_SHIFT)) & SYSCON_FROCTRL_TRIM_MASK) -#define SYSCON_FROCTRL_SEL_MASK (0x4000U) -#define SYSCON_FROCTRL_SEL_SHIFT (14U) -#define SYSCON_FROCTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK) -#define SYSCON_FROCTRL_FREQTRIM_MASK (0xFF0000U) -#define SYSCON_FROCTRL_FREQTRIM_SHIFT (16U) -#define SYSCON_FROCTRL_FREQTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK) -#define SYSCON_FROCTRL_USBCLKADJ_MASK (0x1000000U) -#define SYSCON_FROCTRL_USBCLKADJ_SHIFT (24U) -#define SYSCON_FROCTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK) -#define SYSCON_FROCTRL_USBMODCHG_MASK (0x2000000U) -#define SYSCON_FROCTRL_USBMODCHG_SHIFT (25U) -#define SYSCON_FROCTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK) -#define SYSCON_FROCTRL_HSPDCLK_MASK (0x40000000U) -#define SYSCON_FROCTRL_HSPDCLK_SHIFT (30U) -#define SYSCON_FROCTRL_HSPDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK) -#define SYSCON_FROCTRL_WRTRIM_MASK (0x80000000U) -#define SYSCON_FROCTRL_WRTRIM_SHIFT (31U) -#define SYSCON_FROCTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_WRTRIM_SHIFT)) & SYSCON_FROCTRL_WRTRIM_MASK) - -/*! @name SYSOSCCTRL - System oscillator control */ -#define SYSCON_SYSOSCCTRL_BYPASS_MASK (0x1U) -#define SYSCON_SYSOSCCTRL_BYPASS_SHIFT (0U) -#define SYSCON_SYSOSCCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_BYPASS_SHIFT)) & SYSCON_SYSOSCCTRL_BYPASS_MASK) -#define SYSCON_SYSOSCCTRL_FREQRANGE_MASK (0x2U) -#define SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT (1U) -#define SYSCON_SYSOSCCTRL_FREQRANGE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT)) & SYSCON_SYSOSCCTRL_FREQRANGE_MASK) - -/*! @name WDTOSCCTRL - Watchdog oscillator control */ -#define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU) -#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U) -#define SYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK) -#define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x3E0U) -#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U) -#define SYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK) - -/*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */ -#define SYSCON_RTCOSCCTRL_EN_MASK (0x1U) -#define SYSCON_RTCOSCCTRL_EN_SHIFT (0U) -#define SYSCON_RTCOSCCTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK) - -/*! @name USBPLLCTRL - USB PLL control */ -#define SYSCON_USBPLLCTRL_MSEL_MASK (0xFFU) -#define SYSCON_USBPLLCTRL_MSEL_SHIFT (0U) -#define SYSCON_USBPLLCTRL_MSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_MSEL_SHIFT)) & SYSCON_USBPLLCTRL_MSEL_MASK) -#define SYSCON_USBPLLCTRL_PSEL_MASK (0x300U) -#define SYSCON_USBPLLCTRL_PSEL_SHIFT (8U) -#define SYSCON_USBPLLCTRL_PSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_PSEL_SHIFT)) & SYSCON_USBPLLCTRL_PSEL_MASK) -#define SYSCON_USBPLLCTRL_NSEL_MASK (0xC00U) -#define SYSCON_USBPLLCTRL_NSEL_SHIFT (10U) -#define SYSCON_USBPLLCTRL_NSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_NSEL_SHIFT)) & SYSCON_USBPLLCTRL_NSEL_MASK) -#define SYSCON_USBPLLCTRL_DIRECT_MASK (0x1000U) -#define SYSCON_USBPLLCTRL_DIRECT_SHIFT (12U) -#define SYSCON_USBPLLCTRL_DIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_DIRECT_SHIFT)) & SYSCON_USBPLLCTRL_DIRECT_MASK) -#define SYSCON_USBPLLCTRL_BYPASS_MASK (0x2000U) -#define SYSCON_USBPLLCTRL_BYPASS_SHIFT (13U) -#define SYSCON_USBPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_BYPASS_SHIFT)) & SYSCON_USBPLLCTRL_BYPASS_MASK) -#define SYSCON_USBPLLCTRL_FBSEL_MASK (0x4000U) -#define SYSCON_USBPLLCTRL_FBSEL_SHIFT (14U) -#define SYSCON_USBPLLCTRL_FBSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_FBSEL_SHIFT)) & SYSCON_USBPLLCTRL_FBSEL_MASK) - -/*! @name USBPLLSTAT - USB PLL status */ -#define SYSCON_USBPLLSTAT_LOCK_MASK (0x1U) -#define SYSCON_USBPLLSTAT_LOCK_SHIFT (0U) -#define SYSCON_USBPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLSTAT_LOCK_SHIFT)) & SYSCON_USBPLLSTAT_LOCK_MASK) - -/*! @name SYSPLLCTRL - System PLL control */ -#define SYSCON_SYSPLLCTRL_SELR_MASK (0xFU) -#define SYSCON_SYSPLLCTRL_SELR_SHIFT (0U) -#define SYSCON_SYSPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK) -#define SYSCON_SYSPLLCTRL_SELI_MASK (0x3F0U) -#define SYSCON_SYSPLLCTRL_SELI_SHIFT (4U) -#define SYSCON_SYSPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK) -#define SYSCON_SYSPLLCTRL_SELP_MASK (0x7C00U) -#define SYSCON_SYSPLLCTRL_SELP_SHIFT (10U) -#define SYSCON_SYSPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK) -#define SYSCON_SYSPLLCTRL_BYPASS_MASK (0x8000U) -#define SYSCON_SYSPLLCTRL_BYPASS_SHIFT (15U) -#define SYSCON_SYSPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK) -#define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK (0x20000U) -#define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT (17U) -#define SYSCON_SYSPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK) -#define SYSCON_SYSPLLCTRL_DIRECTI_MASK (0x80000U) -#define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT (19U) -#define SYSCON_SYSPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK) -#define SYSCON_SYSPLLCTRL_DIRECTO_MASK (0x100000U) -#define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT (20U) -#define SYSCON_SYSPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK) - -/*! @name SYSPLLSTAT - PLL status */ -#define SYSCON_SYSPLLSTAT_LOCK_MASK (0x1U) -#define SYSCON_SYSPLLSTAT_LOCK_SHIFT (0U) -#define SYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK) - -/*! @name SYSPLLNDEC - PLL N divider */ -#define SYSCON_SYSPLLNDEC_NDEC_MASK (0x3FFU) -#define SYSCON_SYSPLLNDEC_NDEC_SHIFT (0U) -#define SYSCON_SYSPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK) -#define SYSCON_SYSPLLNDEC_NREQ_MASK (0x400U) -#define SYSCON_SYSPLLNDEC_NREQ_SHIFT (10U) -#define SYSCON_SYSPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK) - -/*! @name SYSPLLPDEC - PLL P divider */ -#define SYSCON_SYSPLLPDEC_PDEC_MASK (0x7FU) -#define SYSCON_SYSPLLPDEC_PDEC_SHIFT (0U) -#define SYSCON_SYSPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK) -#define SYSCON_SYSPLLPDEC_PREQ_MASK (0x80U) -#define SYSCON_SYSPLLPDEC_PREQ_SHIFT (7U) -#define SYSCON_SYSPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK) - -/*! @name SYSPLLMDEC - System PLL M divider */ -#define SYSCON_SYSPLLMDEC_MDEC_MASK (0x1FFFFU) -#define SYSCON_SYSPLLMDEC_MDEC_SHIFT (0U) -#define SYSCON_SYSPLLMDEC_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MDEC_SHIFT)) & SYSCON_SYSPLLMDEC_MDEC_MASK) -#define SYSCON_SYSPLLMDEC_MREQ_MASK (0x20000U) -#define SYSCON_SYSPLLMDEC_MREQ_SHIFT (17U) -#define SYSCON_SYSPLLMDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MREQ_SHIFT)) & SYSCON_SYSPLLMDEC_MREQ_MASK) - -/*! @name AUDPLLCTRL - Audio PLL control */ -#define SYSCON_AUDPLLCTRL_SELR_MASK (0xFU) -#define SYSCON_AUDPLLCTRL_SELR_SHIFT (0U) -#define SYSCON_AUDPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELR_SHIFT)) & SYSCON_AUDPLLCTRL_SELR_MASK) -#define SYSCON_AUDPLLCTRL_SELI_MASK (0x3F0U) -#define SYSCON_AUDPLLCTRL_SELI_SHIFT (4U) -#define SYSCON_AUDPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELI_SHIFT)) & SYSCON_AUDPLLCTRL_SELI_MASK) -#define SYSCON_AUDPLLCTRL_SELP_MASK (0x7C00U) -#define SYSCON_AUDPLLCTRL_SELP_SHIFT (10U) -#define SYSCON_AUDPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELP_SHIFT)) & SYSCON_AUDPLLCTRL_SELP_MASK) -#define SYSCON_AUDPLLCTRL_BYPASS_MASK (0x8000U) -#define SYSCON_AUDPLLCTRL_BYPASS_SHIFT (15U) -#define SYSCON_AUDPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_BYPASS_SHIFT)) & SYSCON_AUDPLLCTRL_BYPASS_MASK) -#define SYSCON_AUDPLLCTRL_UPLIMOFF_MASK (0x20000U) -#define SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT (17U) -#define SYSCON_AUDPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_AUDPLLCTRL_UPLIMOFF_MASK) -#define SYSCON_AUDPLLCTRL_DIRECTI_MASK (0x80000U) -#define SYSCON_AUDPLLCTRL_DIRECTI_SHIFT (19U) -#define SYSCON_AUDPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTI_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTI_MASK) -#define SYSCON_AUDPLLCTRL_DIRECTO_MASK (0x100000U) -#define SYSCON_AUDPLLCTRL_DIRECTO_SHIFT (20U) -#define SYSCON_AUDPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTO_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTO_MASK) - -/*! @name AUDPLLSTAT - Audio PLL status */ -#define SYSCON_AUDPLLSTAT_LOCK_MASK (0x1U) -#define SYSCON_AUDPLLSTAT_LOCK_SHIFT (0U) -#define SYSCON_AUDPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLSTAT_LOCK_SHIFT)) & SYSCON_AUDPLLSTAT_LOCK_MASK) - -/*! @name AUDPLLNDEC - Audio PLL N divider */ -#define SYSCON_AUDPLLNDEC_NDEC_MASK (0x3FFU) -#define SYSCON_AUDPLLNDEC_NDEC_SHIFT (0U) -#define SYSCON_AUDPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NDEC_SHIFT)) & SYSCON_AUDPLLNDEC_NDEC_MASK) -#define SYSCON_AUDPLLNDEC_NREQ_MASK (0x400U) -#define SYSCON_AUDPLLNDEC_NREQ_SHIFT (10U) -#define SYSCON_AUDPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NREQ_SHIFT)) & SYSCON_AUDPLLNDEC_NREQ_MASK) - -/*! @name AUDPLLPDEC - Audio PLL P divider */ -#define SYSCON_AUDPLLPDEC_PDEC_MASK (0x7FU) -#define SYSCON_AUDPLLPDEC_PDEC_SHIFT (0U) -#define SYSCON_AUDPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PDEC_SHIFT)) & SYSCON_AUDPLLPDEC_PDEC_MASK) -#define SYSCON_AUDPLLPDEC_PREQ_MASK (0x80U) -#define SYSCON_AUDPLLPDEC_PREQ_SHIFT (7U) -#define SYSCON_AUDPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PREQ_SHIFT)) & SYSCON_AUDPLLPDEC_PREQ_MASK) - -/*! @name AUDPLLMDEC - Audio PLL M divider */ -#define SYSCON_AUDPLLMDEC_MDEC_MASK (0x1FFFFU) -#define SYSCON_AUDPLLMDEC_MDEC_SHIFT (0U) -#define SYSCON_AUDPLLMDEC_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MDEC_SHIFT)) & SYSCON_AUDPLLMDEC_MDEC_MASK) -#define SYSCON_AUDPLLMDEC_MREQ_MASK (0x20000U) -#define SYSCON_AUDPLLMDEC_MREQ_SHIFT (17U) -#define SYSCON_AUDPLLMDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MREQ_SHIFT)) & SYSCON_AUDPLLMDEC_MREQ_MASK) - -/*! @name AUDPLLFRAC - Audio PLL fractional divider control */ -#define SYSCON_AUDPLLFRAC_CTRL_MASK (0x3FFFFFU) -#define SYSCON_AUDPLLFRAC_CTRL_SHIFT (0U) -#define SYSCON_AUDPLLFRAC_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_CTRL_SHIFT)) & SYSCON_AUDPLLFRAC_CTRL_MASK) -#define SYSCON_AUDPLLFRAC_REQ_MASK (0x400000U) -#define SYSCON_AUDPLLFRAC_REQ_SHIFT (22U) -#define SYSCON_AUDPLLFRAC_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_REQ_SHIFT)) & SYSCON_AUDPLLFRAC_REQ_MASK) -#define SYSCON_AUDPLLFRAC_SEL_EXT_MASK (0x800000U) -#define SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT (23U) -#define SYSCON_AUDPLLFRAC_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT)) & SYSCON_AUDPLLFRAC_SEL_EXT_MASK) - -/*! @name PDSLEEPCFG - Power configuration register 0 */ -#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK (0x1U) -#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT (0U) -#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK (0x2U) -#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT (1U) -#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK (0x4U) -#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT (2U) -#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK (0x8U) -#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT (3U) -#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_FRO_MASK (0x10U) -#define SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT (4U) -#define SYSCON_PDSLEEPCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_FRO_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_EEPROM_MASK (0x20U) -#define SYSCON_PDSLEEPCFG_PDEN_EEPROM_SHIFT (5U) -#define SYSCON_PDSLEEPCFG_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_EEPROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_EEPROM_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_TS_MASK (0x40U) -#define SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT (6U) -#define SYSCON_PDSLEEPCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_TS_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK (0x80U) -#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT (7U) -#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_RNG_MASK (0x80U) -#define SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT (7U) -#define SYSCON_PDSLEEPCFG_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_RNG_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK (0x100U) -#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT (8U) -#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK (0x200U) -#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT (9U) -#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK (0x400U) -#define SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT (10U) -#define SYSCON_PDSLEEPCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK (0x2000U) -#define SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT (13U) -#define SYSCON_PDSLEEPCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK (0x4000U) -#define SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT (14U) -#define SYSCON_PDSLEEPCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK (0x8000U) -#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT (15U) -#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK (0x10000U) -#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT (16U) -#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_ROM_MASK (0x20000U) -#define SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT (17U) -#define SYSCON_PDSLEEPCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ROM_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK (0x80000U) -#define SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT (19U) -#define SYSCON_PDSLEEPCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK (0x100000U) -#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT (20U) -#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK (0x200000U) -#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT (21U) -#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK (0x400000U) -#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT (22U) -#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK (0x800000U) -#define SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT (23U) -#define SYSCON_PDSLEEPCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_VD3_MASK (0x4000000U) -#define SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT (26U) -#define SYSCON_PDSLEEPCFG_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD3_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_VD4_MASK (0x8000000U) -#define SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT (27U) -#define SYSCON_PDSLEEPCFG_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD4_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_VD5_MASK (0x10000000U) -#define SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT (28U) -#define SYSCON_PDSLEEPCFG_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD5_MASK) -#define SYSCON_PDSLEEPCFG_PDEN_VD6_MASK (0x20000000U) -#define SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT (29U) -#define SYSCON_PDSLEEPCFG_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD6_MASK) - -/* The count of SYSCON_PDSLEEPCFG */ -#define SYSCON_PDSLEEPCFG_COUNT (2U) - -/*! @name PDRUNCFG - Power configuration register 0 */ -#define SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK (0x1U) -#define SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT (0U) -#define SYSCON_PDRUNCFG_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK) -#define SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK (0x2U) -#define SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT (1U) -#define SYSCON_PDRUNCFG_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK) -#define SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK (0x4U) -#define SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT (2U) -#define SYSCON_PDRUNCFG_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK) -#define SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK (0x8U) -#define SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT (3U) -#define SYSCON_PDRUNCFG_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK) -#define SYSCON_PDRUNCFG_PDEN_FRO_MASK (0x10U) -#define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT (4U) -#define SYSCON_PDRUNCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK) -#define SYSCON_PDRUNCFG_PDEN_EEPROM_MASK (0x20U) -#define SYSCON_PDRUNCFG_PDEN_EEPROM_SHIFT (5U) -#define SYSCON_PDRUNCFG_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_EEPROM_MASK) -#define SYSCON_PDRUNCFG_PDEN_TS_MASK (0x40U) -#define SYSCON_PDRUNCFG_PDEN_TS_SHIFT (6U) -#define SYSCON_PDRUNCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK) -#define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK (0x80U) -#define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT (7U) -#define SYSCON_PDRUNCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK) -#define SYSCON_PDRUNCFG_PDEN_RNG_MASK (0x80U) -#define SYSCON_PDRUNCFG_PDEN_RNG_SHIFT (7U) -#define SYSCON_PDRUNCFG_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFG_PDEN_RNG_MASK) -#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK (0x100U) -#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT (8U) -#define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK) -#define SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK (0x200U) -#define SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT (9U) -#define SYSCON_PDRUNCFG_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK) -#define SYSCON_PDRUNCFG_PDEN_ADC0_MASK (0x400U) -#define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT (10U) -#define SYSCON_PDRUNCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK) -#define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK (0x2000U) -#define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT (13U) -#define SYSCON_PDRUNCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK) -#define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK (0x4000U) -#define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT (14U) -#define SYSCON_PDRUNCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK) -#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK (0x8000U) -#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT (15U) -#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK) -#define SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK (0x10000U) -#define SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT (16U) -#define SYSCON_PDRUNCFG_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK) -#define SYSCON_PDRUNCFG_PDEN_ROM_MASK (0x20000U) -#define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT (17U) -#define SYSCON_PDRUNCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK) -#define SYSCON_PDRUNCFG_PDEN_VDDA_MASK (0x80000U) -#define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT (19U) -#define SYSCON_PDRUNCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK) -#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK (0x100000U) -#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT (20U) -#define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) -#define SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK (0x200000U) -#define SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT (21U) -#define SYSCON_PDRUNCFG_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK) -#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK (0x400000U) -#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT (22U) -#define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK) -#define SYSCON_PDRUNCFG_PDEN_VREFP_MASK (0x800000U) -#define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT (23U) -#define SYSCON_PDRUNCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK) -#define SYSCON_PDRUNCFG_PDEN_VD3_MASK (0x4000000U) -#define SYSCON_PDRUNCFG_PDEN_VD3_SHIFT (26U) -#define SYSCON_PDRUNCFG_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD3_MASK) -#define SYSCON_PDRUNCFG_PDEN_VD4_MASK (0x8000000U) -#define SYSCON_PDRUNCFG_PDEN_VD4_SHIFT (27U) -#define SYSCON_PDRUNCFG_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD4_MASK) -#define SYSCON_PDRUNCFG_PDEN_VD5_MASK (0x10000000U) -#define SYSCON_PDRUNCFG_PDEN_VD5_SHIFT (28U) -#define SYSCON_PDRUNCFG_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD5_MASK) -#define SYSCON_PDRUNCFG_PDEN_VD6_MASK (0x20000000U) -#define SYSCON_PDRUNCFG_PDEN_VD6_SHIFT (29U) -#define SYSCON_PDRUNCFG_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD6_MASK) - -/* The count of SYSCON_PDRUNCFG */ -#define SYSCON_PDRUNCFG_COUNT (2U) - -/*! @name PDRUNCFGSET - Set bits in PDRUNCFG0 */ -#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK (0x1U) -#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT (0U) -#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK (0x2U) -#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT (1U) -#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK (0x4U) -#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT (2U) -#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK (0x8U) -#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT (3U) -#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_FRO_MASK (0x10U) -#define SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT (4U) -#define SYSCON_PDRUNCFGSET_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_FRO_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_EEPROM_MASK (0x20U) -#define SYSCON_PDRUNCFGSET_PDEN_EEPROM_SHIFT (5U) -#define SYSCON_PDRUNCFGSET_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_EEPROM_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_TS_MASK (0x40U) -#define SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT (6U) -#define SYSCON_PDRUNCFGSET_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_TS_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK (0x80U) -#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT (7U) -#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_RNG_MASK (0x80U) -#define SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT (7U) -#define SYSCON_PDRUNCFGSET_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_RNG_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK (0x100U) -#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT (8U) -#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK (0x200U) -#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT (9U) -#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK (0x400U) -#define SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT (10U) -#define SYSCON_PDRUNCFGSET_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK (0x2000U) -#define SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT (13U) -#define SYSCON_PDRUNCFGSET_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK (0x4000U) -#define SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT (14U) -#define SYSCON_PDRUNCFGSET_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK (0x8000U) -#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT (15U) -#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK (0x10000U) -#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT (16U) -#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_ROM_MASK (0x20000U) -#define SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT (17U) -#define SYSCON_PDRUNCFGSET_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ROM_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK (0x80000U) -#define SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT (19U) -#define SYSCON_PDRUNCFGSET_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK (0x100000U) -#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT (20U) -#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK (0x200000U) -#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT (21U) -#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK (0x400000U) -#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT (22U) -#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK (0x800000U) -#define SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT (23U) -#define SYSCON_PDRUNCFGSET_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_VD3_MASK (0x4000000U) -#define SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT (26U) -#define SYSCON_PDRUNCFGSET_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD3_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_VD4_MASK (0x8000000U) -#define SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT (27U) -#define SYSCON_PDRUNCFGSET_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD4_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_VD5_MASK (0x10000000U) -#define SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT (28U) -#define SYSCON_PDRUNCFGSET_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD5_MASK) -#define SYSCON_PDRUNCFGSET_PDEN_VD6_MASK (0x20000000U) -#define SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT (29U) -#define SYSCON_PDRUNCFGSET_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD6_MASK) - -/* The count of SYSCON_PDRUNCFGSET */ -#define SYSCON_PDRUNCFGSET_COUNT (2U) - -/*! @name PDRUNCFGCLR - Clear bits in PDRUNCFG0 */ -#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK (0x1U) -#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT (0U) -#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK (0x2U) -#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT (1U) -#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK (0x4U) -#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT (2U) -#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK (0x8U) -#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT (3U) -#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK (0x10U) -#define SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT (4U) -#define SYSCON_PDRUNCFGCLR_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_EEPROM_MASK (0x20U) -#define SYSCON_PDRUNCFGCLR_PDEN_EEPROM_SHIFT (5U) -#define SYSCON_PDRUNCFGCLR_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_EEPROM_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_TS_MASK (0x40U) -#define SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT (6U) -#define SYSCON_PDRUNCFGCLR_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_TS_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK (0x80U) -#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT (7U) -#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK (0x80U) -#define SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT (7U) -#define SYSCON_PDRUNCFGCLR_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK (0x100U) -#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT (8U) -#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK (0x200U) -#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT (9U) -#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK (0x400U) -#define SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT (10U) -#define SYSCON_PDRUNCFGCLR_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK (0x2000U) -#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT (13U) -#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK (0x4000U) -#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT (14U) -#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK (0x8000U) -#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT (15U) -#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK (0x10000U) -#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT (16U) -#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK (0x20000U) -#define SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT (17U) -#define SYSCON_PDRUNCFGCLR_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK (0x80000U) -#define SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT (19U) -#define SYSCON_PDRUNCFGCLR_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK (0x100000U) -#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT (20U) -#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK (0x200000U) -#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT (21U) -#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK (0x400000U) -#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT (22U) -#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK (0x800000U) -#define SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT (23U) -#define SYSCON_PDRUNCFGCLR_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK (0x4000000U) -#define SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT (26U) -#define SYSCON_PDRUNCFGCLR_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK (0x8000000U) -#define SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT (27U) -#define SYSCON_PDRUNCFGCLR_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK (0x10000000U) -#define SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT (28U) -#define SYSCON_PDRUNCFGCLR_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK) -#define SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK (0x20000000U) -#define SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT (29U) -#define SYSCON_PDRUNCFGCLR_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK) - -/* The count of SYSCON_PDRUNCFGCLR */ -#define SYSCON_PDRUNCFGCLR_COUNT (2U) - -/*! @name STARTER - Start logic 0 wake-up enable register */ -#define SYSCON_STARTER_WDT_BOD_MASK (0x1U) -#define SYSCON_STARTER_WDT_BOD_SHIFT (0U) -#define SYSCON_STARTER_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WDT_BOD_SHIFT)) & SYSCON_STARTER_WDT_BOD_MASK) -#define SYSCON_STARTER_PINT4_MASK (0x1U) -#define SYSCON_STARTER_PINT4_SHIFT (0U) -#define SYSCON_STARTER_PINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT4_SHIFT)) & SYSCON_STARTER_PINT4_MASK) -#define SYSCON_STARTER_PINT5_MASK (0x2U) -#define SYSCON_STARTER_PINT5_SHIFT (1U) -#define SYSCON_STARTER_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT5_SHIFT)) & SYSCON_STARTER_PINT5_MASK) -#define SYSCON_STARTER_DMA_MASK (0x2U) -#define SYSCON_STARTER_DMA_SHIFT (1U) -#define SYSCON_STARTER_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMA_SHIFT)) & SYSCON_STARTER_DMA_MASK) -#define SYSCON_STARTER_GINT0_MASK (0x4U) -#define SYSCON_STARTER_GINT0_SHIFT (2U) -#define SYSCON_STARTER_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK) -#define SYSCON_STARTER_PINT6_MASK (0x4U) -#define SYSCON_STARTER_PINT6_SHIFT (2U) -#define SYSCON_STARTER_PINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT6_SHIFT)) & SYSCON_STARTER_PINT6_MASK) -#define SYSCON_STARTER_GINT1_MASK (0x8U) -#define SYSCON_STARTER_GINT1_SHIFT (3U) -#define SYSCON_STARTER_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK) -#define SYSCON_STARTER_PINT7_MASK (0x8U) -#define SYSCON_STARTER_PINT7_SHIFT (3U) -#define SYSCON_STARTER_PINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT7_SHIFT)) & SYSCON_STARTER_PINT7_MASK) -#define SYSCON_STARTER_CTIMER2_MASK (0x10U) -#define SYSCON_STARTER_CTIMER2_SHIFT (4U) -#define SYSCON_STARTER_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER2_SHIFT)) & SYSCON_STARTER_CTIMER2_MASK) -#define SYSCON_STARTER_PIN_INT0_MASK (0x10U) -#define SYSCON_STARTER_PIN_INT0_SHIFT (4U) -#define SYSCON_STARTER_PIN_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT0_SHIFT)) & SYSCON_STARTER_PIN_INT0_MASK) -#define SYSCON_STARTER_CTIMER4_MASK (0x20U) -#define SYSCON_STARTER_CTIMER4_SHIFT (5U) -#define SYSCON_STARTER_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER4_SHIFT)) & SYSCON_STARTER_CTIMER4_MASK) -#define SYSCON_STARTER_PIN_INT1_MASK (0x20U) -#define SYSCON_STARTER_PIN_INT1_SHIFT (5U) -#define SYSCON_STARTER_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT1_SHIFT)) & SYSCON_STARTER_PIN_INT1_MASK) -#define SYSCON_STARTER_PIN_INT2_MASK (0x40U) -#define SYSCON_STARTER_PIN_INT2_SHIFT (6U) -#define SYSCON_STARTER_PIN_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT2_SHIFT)) & SYSCON_STARTER_PIN_INT2_MASK) -#define SYSCON_STARTER_PIN_INT3_MASK (0x80U) -#define SYSCON_STARTER_PIN_INT3_SHIFT (7U) -#define SYSCON_STARTER_PIN_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT3_SHIFT)) & SYSCON_STARTER_PIN_INT3_MASK) -#define SYSCON_STARTER_SPIFI_MASK (0x80U) -#define SYSCON_STARTER_SPIFI_SHIFT (7U) -#define SYSCON_STARTER_SPIFI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SPIFI_SHIFT)) & SYSCON_STARTER_SPIFI_MASK) -#define SYSCON_STARTER_FLEXCOMM8_MASK (0x100U) -#define SYSCON_STARTER_FLEXCOMM8_SHIFT (8U) -#define SYSCON_STARTER_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM8_SHIFT)) & SYSCON_STARTER_FLEXCOMM8_MASK) -#define SYSCON_STARTER_UTICK_MASK (0x100U) -#define SYSCON_STARTER_UTICK_SHIFT (8U) -#define SYSCON_STARTER_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK_SHIFT)) & SYSCON_STARTER_UTICK_MASK) -#define SYSCON_STARTER_MRT_MASK (0x200U) -#define SYSCON_STARTER_MRT_SHIFT (9U) -#define SYSCON_STARTER_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT_SHIFT)) & SYSCON_STARTER_MRT_MASK) -#define SYSCON_STARTER_FLEXCOMM9_MASK (0x200U) -#define SYSCON_STARTER_FLEXCOMM9_SHIFT (9U) -#define SYSCON_STARTER_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM9_SHIFT)) & SYSCON_STARTER_FLEXCOMM9_MASK) -#define SYSCON_STARTER_CTIMER0_MASK (0x400U) -#define SYSCON_STARTER_CTIMER0_SHIFT (10U) -#define SYSCON_STARTER_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK) -#define SYSCON_STARTER_CTIMER1_MASK (0x800U) -#define SYSCON_STARTER_CTIMER1_SHIFT (11U) -#define SYSCON_STARTER_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK) -#define SYSCON_STARTER_SCT0_MASK (0x1000U) -#define SYSCON_STARTER_SCT0_SHIFT (12U) -#define SYSCON_STARTER_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK) -#define SYSCON_STARTER_CTIMER3_MASK (0x2000U) -#define SYSCON_STARTER_CTIMER3_SHIFT (13U) -#define SYSCON_STARTER_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK) -#define SYSCON_STARTER_FLEXCOMM0_MASK (0x4000U) -#define SYSCON_STARTER_FLEXCOMM0_SHIFT (14U) -#define SYSCON_STARTER_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM0_SHIFT)) & SYSCON_STARTER_FLEXCOMM0_MASK) -#define SYSCON_STARTER_FLEXCOMM1_MASK (0x8000U) -#define SYSCON_STARTER_FLEXCOMM1_SHIFT (15U) -#define SYSCON_STARTER_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM1_SHIFT)) & SYSCON_STARTER_FLEXCOMM1_MASK) -#define SYSCON_STARTER_USB1_MASK (0x8000U) -#define SYSCON_STARTER_USB1_SHIFT (15U) -#define SYSCON_STARTER_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_SHIFT)) & SYSCON_STARTER_USB1_MASK) -#define SYSCON_STARTER_FLEXCOMM2_MASK (0x10000U) -#define SYSCON_STARTER_FLEXCOMM2_SHIFT (16U) -#define SYSCON_STARTER_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM2_SHIFT)) & SYSCON_STARTER_FLEXCOMM2_MASK) -#define SYSCON_STARTER_USB1_ACT_MASK (0x10000U) -#define SYSCON_STARTER_USB1_ACT_SHIFT (16U) -#define SYSCON_STARTER_USB1_ACT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_ACT_SHIFT)) & SYSCON_STARTER_USB1_ACT_MASK) -#define SYSCON_STARTER_ENET_INT1_MASK (0x20000U) -#define SYSCON_STARTER_ENET_INT1_SHIFT (17U) -#define SYSCON_STARTER_ENET_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT1_SHIFT)) & SYSCON_STARTER_ENET_INT1_MASK) -#define SYSCON_STARTER_FLEXCOMM3_MASK (0x20000U) -#define SYSCON_STARTER_FLEXCOMM3_SHIFT (17U) -#define SYSCON_STARTER_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM3_SHIFT)) & SYSCON_STARTER_FLEXCOMM3_MASK) -#define SYSCON_STARTER_ENET_INT2_MASK (0x40000U) -#define SYSCON_STARTER_ENET_INT2_SHIFT (18U) -#define SYSCON_STARTER_ENET_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT2_SHIFT)) & SYSCON_STARTER_ENET_INT2_MASK) -#define SYSCON_STARTER_FLEXCOMM4_MASK (0x40000U) -#define SYSCON_STARTER_FLEXCOMM4_SHIFT (18U) -#define SYSCON_STARTER_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM4_SHIFT)) & SYSCON_STARTER_FLEXCOMM4_MASK) -#define SYSCON_STARTER_ENET_INT0_MASK (0x80000U) -#define SYSCON_STARTER_ENET_INT0_SHIFT (19U) -#define SYSCON_STARTER_ENET_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT0_SHIFT)) & SYSCON_STARTER_ENET_INT0_MASK) -#define SYSCON_STARTER_FLEXCOMM5_MASK (0x80000U) -#define SYSCON_STARTER_FLEXCOMM5_SHIFT (19U) -#define SYSCON_STARTER_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM5_SHIFT)) & SYSCON_STARTER_FLEXCOMM5_MASK) -#define SYSCON_STARTER_FLEXCOMM6_MASK (0x100000U) -#define SYSCON_STARTER_FLEXCOMM6_SHIFT (20U) -#define SYSCON_STARTER_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM6_SHIFT)) & SYSCON_STARTER_FLEXCOMM6_MASK) -#define SYSCON_STARTER_FLEXCOMM7_MASK (0x200000U) -#define SYSCON_STARTER_FLEXCOMM7_SHIFT (21U) -#define SYSCON_STARTER_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM7_SHIFT)) & SYSCON_STARTER_FLEXCOMM7_MASK) -#define SYSCON_STARTER_ADC0_SEQA_MASK (0x400000U) -#define SYSCON_STARTER_ADC0_SEQA_SHIFT (22U) -#define SYSCON_STARTER_ADC0_SEQA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SEQA_SHIFT)) & SYSCON_STARTER_ADC0_SEQA_MASK) -#define SYSCON_STARTER_SMARTCARD0_MASK (0x800000U) -#define SYSCON_STARTER_SMARTCARD0_SHIFT (23U) -#define SYSCON_STARTER_SMARTCARD0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SMARTCARD0_SHIFT)) & SYSCON_STARTER_SMARTCARD0_MASK) -#define SYSCON_STARTER_ADC0_SEQB_MASK (0x800000U) -#define SYSCON_STARTER_ADC0_SEQB_SHIFT (23U) -#define SYSCON_STARTER_ADC0_SEQB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SEQB_SHIFT)) & SYSCON_STARTER_ADC0_SEQB_MASK) -#define SYSCON_STARTER_ADC0_THCMP_MASK (0x1000000U) -#define SYSCON_STARTER_ADC0_THCMP_SHIFT (24U) -#define SYSCON_STARTER_ADC0_THCMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_THCMP_SHIFT)) & SYSCON_STARTER_ADC0_THCMP_MASK) -#define SYSCON_STARTER_SMARTCARD1_MASK (0x1000000U) -#define SYSCON_STARTER_SMARTCARD1_SHIFT (24U) -#define SYSCON_STARTER_SMARTCARD1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SMARTCARD1_SHIFT)) & SYSCON_STARTER_SMARTCARD1_MASK) -#define SYSCON_STARTER_DMIC_MASK (0x2000000U) -#define SYSCON_STARTER_DMIC_SHIFT (25U) -#define SYSCON_STARTER_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMIC_SHIFT)) & SYSCON_STARTER_DMIC_MASK) -#define SYSCON_STARTER_HWVAD_MASK (0x4000000U) -#define SYSCON_STARTER_HWVAD_SHIFT (26U) -#define SYSCON_STARTER_HWVAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HWVAD_SHIFT)) & SYSCON_STARTER_HWVAD_MASK) -#define SYSCON_STARTER_USB0_NEEDCLK_MASK (0x8000000U) -#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT (27U) -#define SYSCON_STARTER_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK) -#define SYSCON_STARTER_USB0_MASK (0x10000000U) -#define SYSCON_STARTER_USB0_SHIFT (28U) -#define SYSCON_STARTER_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK) -#define SYSCON_STARTER_RTC_MASK (0x20000000U) -#define SYSCON_STARTER_RTC_SHIFT (29U) -#define SYSCON_STARTER_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_SHIFT)) & SYSCON_STARTER_RTC_MASK) - -/* The count of SYSCON_STARTER */ -#define SYSCON_STARTER_COUNT (2U) - -/*! @name STARTERSET - Set bits in STARTER */ -#define SYSCON_STARTERSET_START_SET_MASK (0xFFFFFFFFU) -#define SYSCON_STARTERSET_START_SET_SHIFT (0U) -#define SYSCON_STARTERSET_START_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK) - -/* The count of SYSCON_STARTERSET */ -#define SYSCON_STARTERSET_COUNT (2U) - -/*! @name STARTERCLR - Clear bits in STARTER0 */ -#define SYSCON_STARTERCLR_START_CLR_MASK (0xFFFFFFFFU) -#define SYSCON_STARTERCLR_START_CLR_SHIFT (0U) -#define SYSCON_STARTERCLR_START_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK) - -/* The count of SYSCON_STARTERCLR */ -#define SYSCON_STARTERCLR_COUNT (2U) - -/*! @name HWWAKE - Configures special cases of hardware wake-up */ -#define SYSCON_HWWAKE_FORCEWAKE_MASK (0x1U) -#define SYSCON_HWWAKE_FORCEWAKE_SHIFT (0U) -#define SYSCON_HWWAKE_FORCEWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK) -#define SYSCON_HWWAKE_FCWAKE_MASK (0x2U) -#define SYSCON_HWWAKE_FCWAKE_SHIFT (1U) -#define SYSCON_HWWAKE_FCWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK) -#define SYSCON_HWWAKE_WAKEDMIC_MASK (0x4U) -#define SYSCON_HWWAKE_WAKEDMIC_SHIFT (2U) -#define SYSCON_HWWAKE_WAKEDMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMIC_SHIFT)) & SYSCON_HWWAKE_WAKEDMIC_MASK) -#define SYSCON_HWWAKE_WAKEDMA_MASK (0x8U) -#define SYSCON_HWWAKE_WAKEDMA_SHIFT (3U) -#define SYSCON_HWWAKE_WAKEDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK) - -/*! @name AUTOCGOR - Auto Clock-Gate Override Register */ -#define SYSCON_AUTOCGOR_RAM0X_MASK (0x2U) -#define SYSCON_AUTOCGOR_RAM0X_SHIFT (1U) -#define SYSCON_AUTOCGOR_RAM0X(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK) -#define SYSCON_AUTOCGOR_RAM1_MASK (0x4U) -#define SYSCON_AUTOCGOR_RAM1_SHIFT (2U) -#define SYSCON_AUTOCGOR_RAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM1_SHIFT)) & SYSCON_AUTOCGOR_RAM1_MASK) -#define SYSCON_AUTOCGOR_RAM2_MASK (0x8U) -#define SYSCON_AUTOCGOR_RAM2_SHIFT (3U) -#define SYSCON_AUTOCGOR_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK) -#define SYSCON_AUTOCGOR_RAM3_MASK (0x10U) -#define SYSCON_AUTOCGOR_RAM3_SHIFT (4U) -#define SYSCON_AUTOCGOR_RAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM3_SHIFT)) & SYSCON_AUTOCGOR_RAM3_MASK) - -/*! @name JTAGIDCODE - JTAG ID code register */ -#define SYSCON_JTAGIDCODE_JTAGID_MASK (0xFFFFFFFFU) -#define SYSCON_JTAGIDCODE_JTAGID_SHIFT (0U) -#define SYSCON_JTAGIDCODE_JTAGID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK) - -/*! @name DEVICE_ID0 - Part ID register */ -#define SYSCON_DEVICE_ID0_PARTID_MASK (0xFFFFFFFFU) -#define SYSCON_DEVICE_ID0_PARTID_SHIFT (0U) -#define SYSCON_DEVICE_ID0_PARTID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK) - -/*! @name DEVICE_ID1 - Boot ROM and die revision register */ -#define SYSCON_DEVICE_ID1_REVID_MASK (0xFFFFFFFFU) -#define SYSCON_DEVICE_ID1_REVID_SHIFT (0U) -#define SYSCON_DEVICE_ID1_REVID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK) - -/*! @name BODCTRL - Brown-Out Detect control */ -#define SYSCON_BODCTRL_BODRSTLEV_MASK (0x3U) -#define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0U) -#define SYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK) -#define SYSCON_BODCTRL_BODRSTENA_MASK (0x4U) -#define SYSCON_BODCTRL_BODRSTENA_SHIFT (2U) -#define SYSCON_BODCTRL_BODRSTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK) -#define SYSCON_BODCTRL_BODINTLEV_MASK (0x18U) -#define SYSCON_BODCTRL_BODINTLEV_SHIFT (3U) -#define SYSCON_BODCTRL_BODINTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK) -#define SYSCON_BODCTRL_BODINTENA_MASK (0x20U) -#define SYSCON_BODCTRL_BODINTENA_SHIFT (5U) -#define SYSCON_BODCTRL_BODINTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK) -#define SYSCON_BODCTRL_BODRSTSTAT_MASK (0x40U) -#define SYSCON_BODCTRL_BODRSTSTAT_SHIFT (6U) -#define SYSCON_BODCTRL_BODRSTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK) -#define SYSCON_BODCTRL_BODINTSTAT_MASK (0x80U) -#define SYSCON_BODCTRL_BODINTSTAT_SHIFT (7U) -#define SYSCON_BODCTRL_BODINTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK) - - -/*! - * @} - */ /* end of group SYSCON_Register_Masks */ - - -/* SYSCON - Peripheral instance base addresses */ -/** Peripheral SYSCON base address */ -#define SYSCON_BASE (0x40000000u) -/** Peripheral SYSCON base pointer */ -#define SYSCON ((SYSCON_Type *)SYSCON_BASE) -/** Array initializer of SYSCON peripheral base addresses */ -#define SYSCON_BASE_ADDRS { SYSCON_BASE } -/** Array initializer of SYSCON peripheral base pointers */ -#define SYSCON_BASE_PTRS { SYSCON } - -/*! - * @} - */ /* end of group SYSCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USART Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer - * @{ - */ - -/** USART - Register Layout Typedef */ -typedef struct { - __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ - __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ - __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ - uint8_t RESERVED_0[12]; - __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ - __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ - __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ - __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ - uint8_t RESERVED_1[3536]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_2[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_4[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_6[440]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} USART_Type; - -/* ---------------------------------------------------------------------------- - -- USART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Register_Masks USART Register Masks - * @{ - */ - -/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ -#define USART_CFG_ENABLE_MASK (0x1U) -#define USART_CFG_ENABLE_SHIFT (0U) -#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) -#define USART_CFG_DATALEN_MASK (0xCU) -#define USART_CFG_DATALEN_SHIFT (2U) -#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) -#define USART_CFG_PARITYSEL_MASK (0x30U) -#define USART_CFG_PARITYSEL_SHIFT (4U) -#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) -#define USART_CFG_STOPLEN_MASK (0x40U) -#define USART_CFG_STOPLEN_SHIFT (6U) -#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) -#define USART_CFG_MODE32K_MASK (0x80U) -#define USART_CFG_MODE32K_SHIFT (7U) -#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) -#define USART_CFG_LINMODE_MASK (0x100U) -#define USART_CFG_LINMODE_SHIFT (8U) -#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) -#define USART_CFG_CTSEN_MASK (0x200U) -#define USART_CFG_CTSEN_SHIFT (9U) -#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) -#define USART_CFG_SYNCEN_MASK (0x800U) -#define USART_CFG_SYNCEN_SHIFT (11U) -#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) -#define USART_CFG_CLKPOL_MASK (0x1000U) -#define USART_CFG_CLKPOL_SHIFT (12U) -#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) -#define USART_CFG_SYNCMST_MASK (0x4000U) -#define USART_CFG_SYNCMST_SHIFT (14U) -#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) -#define USART_CFG_LOOP_MASK (0x8000U) -#define USART_CFG_LOOP_SHIFT (15U) -#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) -#define USART_CFG_OETA_MASK (0x40000U) -#define USART_CFG_OETA_SHIFT (18U) -#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) -#define USART_CFG_AUTOADDR_MASK (0x80000U) -#define USART_CFG_AUTOADDR_SHIFT (19U) -#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) -#define USART_CFG_OESEL_MASK (0x100000U) -#define USART_CFG_OESEL_SHIFT (20U) -#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) -#define USART_CFG_OEPOL_MASK (0x200000U) -#define USART_CFG_OEPOL_SHIFT (21U) -#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) -#define USART_CFG_RXPOL_MASK (0x400000U) -#define USART_CFG_RXPOL_SHIFT (22U) -#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) -#define USART_CFG_TXPOL_MASK (0x800000U) -#define USART_CFG_TXPOL_SHIFT (23U) -#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) - -/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ -#define USART_CTL_TXBRKEN_MASK (0x2U) -#define USART_CTL_TXBRKEN_SHIFT (1U) -#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) -#define USART_CTL_ADDRDET_MASK (0x4U) -#define USART_CTL_ADDRDET_SHIFT (2U) -#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) -#define USART_CTL_TXDIS_MASK (0x40U) -#define USART_CTL_TXDIS_SHIFT (6U) -#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) -#define USART_CTL_CC_MASK (0x100U) -#define USART_CTL_CC_SHIFT (8U) -#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) -#define USART_CTL_CLRCCONRX_MASK (0x200U) -#define USART_CTL_CLRCCONRX_SHIFT (9U) -#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) -#define USART_CTL_AUTOBAUD_MASK (0x10000U) -#define USART_CTL_AUTOBAUD_SHIFT (16U) -#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) - -/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ -#define USART_STAT_RXIDLE_MASK (0x2U) -#define USART_STAT_RXIDLE_SHIFT (1U) -#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) -#define USART_STAT_TXIDLE_MASK (0x8U) -#define USART_STAT_TXIDLE_SHIFT (3U) -#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) -#define USART_STAT_CTS_MASK (0x10U) -#define USART_STAT_CTS_SHIFT (4U) -#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) -#define USART_STAT_DELTACTS_MASK (0x20U) -#define USART_STAT_DELTACTS_SHIFT (5U) -#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) -#define USART_STAT_TXDISSTAT_MASK (0x40U) -#define USART_STAT_TXDISSTAT_SHIFT (6U) -#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) -#define USART_STAT_RXBRK_MASK (0x400U) -#define USART_STAT_RXBRK_SHIFT (10U) -#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) -#define USART_STAT_DELTARXBRK_MASK (0x800U) -#define USART_STAT_DELTARXBRK_SHIFT (11U) -#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) -#define USART_STAT_START_MASK (0x1000U) -#define USART_STAT_START_SHIFT (12U) -#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) -#define USART_STAT_FRAMERRINT_MASK (0x2000U) -#define USART_STAT_FRAMERRINT_SHIFT (13U) -#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) -#define USART_STAT_PARITYERRINT_MASK (0x4000U) -#define USART_STAT_PARITYERRINT_SHIFT (14U) -#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) -#define USART_STAT_RXNOISEINT_MASK (0x8000U) -#define USART_STAT_RXNOISEINT_SHIFT (15U) -#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) -#define USART_STAT_ABERR_MASK (0x10000U) -#define USART_STAT_ABERR_SHIFT (16U) -#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) - -/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -#define USART_INTENSET_TXIDLEEN_MASK (0x8U) -#define USART_INTENSET_TXIDLEEN_SHIFT (3U) -#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) -#define USART_INTENSET_DELTACTSEN_MASK (0x20U) -#define USART_INTENSET_DELTACTSEN_SHIFT (5U) -#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) -#define USART_INTENSET_TXDISEN_MASK (0x40U) -#define USART_INTENSET_TXDISEN_SHIFT (6U) -#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) -#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) -#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) -#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) -#define USART_INTENSET_STARTEN_MASK (0x1000U) -#define USART_INTENSET_STARTEN_SHIFT (12U) -#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) -#define USART_INTENSET_FRAMERREN_MASK (0x2000U) -#define USART_INTENSET_FRAMERREN_SHIFT (13U) -#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) -#define USART_INTENSET_PARITYERREN_MASK (0x4000U) -#define USART_INTENSET_PARITYERREN_SHIFT (14U) -#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) -#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) -#define USART_INTENSET_RXNOISEEN_SHIFT (15U) -#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) -#define USART_INTENSET_ABERREN_MASK (0x10000U) -#define USART_INTENSET_ABERREN_SHIFT (16U) -#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) - -/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ -#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) -#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) -#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) -#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) -#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) -#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) -#define USART_INTENCLR_TXDISCLR_MASK (0x40U) -#define USART_INTENCLR_TXDISCLR_SHIFT (6U) -#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) -#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) -#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) -#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) -#define USART_INTENCLR_STARTCLR_MASK (0x1000U) -#define USART_INTENCLR_STARTCLR_SHIFT (12U) -#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) -#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) -#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) -#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) -#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) -#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) -#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) -#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) -#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) -#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) -#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) -#define USART_INTENCLR_ABERRCLR_SHIFT (16U) -#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) - -/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ -#define USART_BRG_BRGVAL_MASK (0xFFFFU) -#define USART_BRG_BRGVAL_SHIFT (0U) -#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) - -/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ -#define USART_INTSTAT_TXIDLE_MASK (0x8U) -#define USART_INTSTAT_TXIDLE_SHIFT (3U) -#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) -#define USART_INTSTAT_DELTACTS_MASK (0x20U) -#define USART_INTSTAT_DELTACTS_SHIFT (5U) -#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) -#define USART_INTSTAT_TXDISINT_MASK (0x40U) -#define USART_INTSTAT_TXDISINT_SHIFT (6U) -#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) -#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) -#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) -#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) -#define USART_INTSTAT_START_MASK (0x1000U) -#define USART_INTSTAT_START_SHIFT (12U) -#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) -#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) -#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) -#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) -#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) -#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) -#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) -#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) -#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) -#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) -#define USART_INTSTAT_ABERRINT_MASK (0x10000U) -#define USART_INTSTAT_ABERRINT_SHIFT (16U) -#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) - -/*! @name OSR - Oversample selection register for asynchronous communication. */ -#define USART_OSR_OSRVAL_MASK (0xFU) -#define USART_OSR_OSRVAL_SHIFT (0U) -#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) - -/*! @name ADDR - Address register for automatic address matching. */ -#define USART_ADDR_ADDRESS_MASK (0xFFU) -#define USART_ADDR_ADDRESS_SHIFT (0U) -#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -#define USART_FIFOCFG_ENABLETX_MASK (0x1U) -#define USART_FIFOCFG_ENABLETX_SHIFT (0U) -#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) -#define USART_FIFOCFG_ENABLERX_MASK (0x2U) -#define USART_FIFOCFG_ENABLERX_SHIFT (1U) -#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) -#define USART_FIFOCFG_SIZE_MASK (0x30U) -#define USART_FIFOCFG_SIZE_SHIFT (4U) -#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) -#define USART_FIFOCFG_DMATX_MASK (0x1000U) -#define USART_FIFOCFG_DMATX_SHIFT (12U) -#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) -#define USART_FIFOCFG_DMARX_MASK (0x2000U) -#define USART_FIFOCFG_DMARX_SHIFT (13U) -#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) -#define USART_FIFOCFG_WAKETX_MASK (0x4000U) -#define USART_FIFOCFG_WAKETX_SHIFT (14U) -#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) -#define USART_FIFOCFG_WAKERX_MASK (0x8000U) -#define USART_FIFOCFG_WAKERX_SHIFT (15U) -#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) -#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) -#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) -#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) -#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) -#define USART_FIFOCFG_POPDBG_MASK (0x40000U) -#define USART_FIFOCFG_POPDBG_SHIFT (18U) -#define USART_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK) - -/*! @name FIFOSTAT - FIFO status register. */ -#define USART_FIFOSTAT_TXERR_MASK (0x1U) -#define USART_FIFOSTAT_TXERR_SHIFT (0U) -#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) -#define USART_FIFOSTAT_RXERR_MASK (0x2U) -#define USART_FIFOSTAT_RXERR_SHIFT (1U) -#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) -#define USART_FIFOSTAT_PERINT_MASK (0x8U) -#define USART_FIFOSTAT_PERINT_SHIFT (3U) -#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) -#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) -#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) -#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) -#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) -#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) -#define USART_FIFOSTAT_RXFULL_MASK (0x80U) -#define USART_FIFOSTAT_RXFULL_SHIFT (7U) -#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) -#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define USART_FIFOSTAT_TXLVL_SHIFT (8U) -#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) -#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define USART_FIFOSTAT_RXLVL_SHIFT (16U) -#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) -#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) -#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) -#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) -#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) -#define USART_FIFOTRIG_TXLVL_SHIFT (8U) -#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) -#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define USART_FIFOTRIG_RXLVL_SHIFT (16U) -#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -#define USART_FIFOINTENSET_TXERR_MASK (0x1U) -#define USART_FIFOINTENSET_TXERR_SHIFT (0U) -#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) -#define USART_FIFOINTENSET_RXERR_MASK (0x2U) -#define USART_FIFOINTENSET_RXERR_SHIFT (1U) -#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) -#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) -#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) -#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) -#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) -#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) -#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) -#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) -#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) -#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) -#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) -#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) -#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) -#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) -#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) -#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) -#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) -#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) -#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) -#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) -#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) -#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) -#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) -#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) -#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) -#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) -#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) -#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) - -/*! @name FIFOWR - FIFO write data. */ -#define USART_FIFOWR_TXDATA_MASK (0x1FFU) -#define USART_FIFOWR_TXDATA_SHIFT (0U) -#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) - -/*! @name FIFORD - FIFO read data. */ -#define USART_FIFORD_RXDATA_MASK (0x1FFU) -#define USART_FIFORD_RXDATA_SHIFT (0U) -#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) -#define USART_FIFORD_FRAMERR_MASK (0x2000U) -#define USART_FIFORD_FRAMERR_SHIFT (13U) -#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) -#define USART_FIFORD_PARITYERR_MASK (0x4000U) -#define USART_FIFORD_PARITYERR_SHIFT (14U) -#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) -#define USART_FIFORD_RXNOISE_MASK (0x8000U) -#define USART_FIFORD_RXNOISE_SHIFT (15U) -#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) -#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) -#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) -#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) -#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) -#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) -#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) -#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) -#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) -#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) -#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) -#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) - -/*! @name ID - Peripheral identification register. */ -#define USART_ID_APERTURE_MASK (0xFFU) -#define USART_ID_APERTURE_SHIFT (0U) -#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) -#define USART_ID_MINOR_REV_MASK (0xF00U) -#define USART_ID_MINOR_REV_SHIFT (8U) -#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) -#define USART_ID_MAJOR_REV_MASK (0xF000U) -#define USART_ID_MAJOR_REV_SHIFT (12U) -#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) -#define USART_ID_ID_MASK (0xFFFF0000U) -#define USART_ID_ID_SHIFT (16U) -#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) - - -/*! - * @} - */ /* end of group USART_Register_Masks */ - - -/* USART - Peripheral instance base addresses */ -/** Peripheral USART0 base address */ -#define USART0_BASE (0x40086000u) -/** Peripheral USART0 base pointer */ -#define USART0 ((USART_Type *)USART0_BASE) -/** Peripheral USART1 base address */ -#define USART1_BASE (0x40087000u) -/** Peripheral USART1 base pointer */ -#define USART1 ((USART_Type *)USART1_BASE) -/** Peripheral USART2 base address */ -#define USART2_BASE (0x40088000u) -/** Peripheral USART2 base pointer */ -#define USART2 ((USART_Type *)USART2_BASE) -/** Peripheral USART3 base address */ -#define USART3_BASE (0x40089000u) -/** Peripheral USART3 base pointer */ -#define USART3 ((USART_Type *)USART3_BASE) -/** Peripheral USART4 base address */ -#define USART4_BASE (0x4008A000u) -/** Peripheral USART4 base pointer */ -#define USART4 ((USART_Type *)USART4_BASE) -/** Peripheral USART5 base address */ -#define USART5_BASE (0x40096000u) -/** Peripheral USART5 base pointer */ -#define USART5 ((USART_Type *)USART5_BASE) -/** Peripheral USART6 base address */ -#define USART6_BASE (0x40097000u) -/** Peripheral USART6 base pointer */ -#define USART6 ((USART_Type *)USART6_BASE) -/** Peripheral USART7 base address */ -#define USART7_BASE (0x40098000u) -/** Peripheral USART7 base pointer */ -#define USART7 ((USART_Type *)USART7_BASE) -/** Peripheral USART8 base address */ -#define USART8_BASE (0x40099000u) -/** Peripheral USART8 base pointer */ -#define USART8 ((USART_Type *)USART8_BASE) -/** Peripheral USART9 base address */ -#define USART9_BASE (0x4009A000u) -/** Peripheral USART9 base pointer */ -#define USART9 ((USART_Type *)USART9_BASE) -/** Array initializer of USART peripheral base addresses */ -#define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE, USART8_BASE, USART9_BASE } -/** Array initializer of USART peripheral base pointers */ -#define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7, USART8, USART9 } -/** Interrupt vectors for the USART peripheral type */ -#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn } - -/*! - * @} - */ /* end of group USART_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer - * @{ - */ - -/** USB - Register Layout Typedef */ -typedef struct { - __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ - __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ - __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ - __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ - __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ - __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ - __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ - __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ - __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ - __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ - __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ - uint8_t RESERVED_0[8]; - __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ -} USB_Type; - -/* ---------------------------------------------------------------------------- - -- USB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Register_Masks USB Register Masks - * @{ - */ - -/*! @name DEVCMDSTAT - USB Device Command/Status register */ -#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) -#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) -#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) -#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) -#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) -#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) -#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) -#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) -#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) -#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) -#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) -#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) -#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) -#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) -#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) -#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) -#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) -#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) -#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) -#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) -#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) -#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) -#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) -#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) -#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) -#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) -#define USB_DEVCMDSTAT_DCON_SHIFT (16U) -#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) -#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) -#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) -#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) -#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) -#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) -#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) -#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) -#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) -#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) -#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) -#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) -#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) -#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) -#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) -#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) -#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) -#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) -#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) - -/*! @name INFO - USB Info register */ -#define USB_INFO_FRAME_NR_MASK (0x7FFU) -#define USB_INFO_FRAME_NR_SHIFT (0U) -#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) -#define USB_INFO_ERR_CODE_MASK (0x7800U) -#define USB_INFO_ERR_CODE_SHIFT (11U) -#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) -#define USB_INFO_MINREV_MASK (0xFF0000U) -#define USB_INFO_MINREV_SHIFT (16U) -#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK) -#define USB_INFO_MAJREV_MASK (0xFF000000U) -#define USB_INFO_MAJREV_SHIFT (24U) -#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK) - -/*! @name EPLISTSTART - USB EP Command/Status List start address */ -#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) -#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) -#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) - -/*! @name DATABUFSTART - USB Data buffer start address */ -#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) -#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) -#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) - -/*! @name LPM - USB Link Power Management register */ -#define USB_LPM_HIRD_HW_MASK (0xFU) -#define USB_LPM_HIRD_HW_SHIFT (0U) -#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) -#define USB_LPM_HIRD_SW_MASK (0xF0U) -#define USB_LPM_HIRD_SW_SHIFT (4U) -#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) -#define USB_LPM_DATA_PENDING_MASK (0x100U) -#define USB_LPM_DATA_PENDING_SHIFT (8U) -#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) - -/*! @name EPSKIP - USB Endpoint skip */ -#define USB_EPSKIP_SKIP_MASK (0x3FFU) -#define USB_EPSKIP_SKIP_SHIFT (0U) -#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) - -/*! @name EPINUSE - USB Endpoint Buffer in use */ -#define USB_EPINUSE_BUF_MASK (0x3FCU) -#define USB_EPINUSE_BUF_SHIFT (2U) -#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) - -/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ -#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) -#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) -#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) - -/*! @name INTSTAT - USB interrupt status register */ -#define USB_INTSTAT_EP0OUT_MASK (0x1U) -#define USB_INTSTAT_EP0OUT_SHIFT (0U) -#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) -#define USB_INTSTAT_EP0IN_MASK (0x2U) -#define USB_INTSTAT_EP0IN_SHIFT (1U) -#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) -#define USB_INTSTAT_EP1OUT_MASK (0x4U) -#define USB_INTSTAT_EP1OUT_SHIFT (2U) -#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) -#define USB_INTSTAT_EP1IN_MASK (0x8U) -#define USB_INTSTAT_EP1IN_SHIFT (3U) -#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) -#define USB_INTSTAT_EP2OUT_MASK (0x10U) -#define USB_INTSTAT_EP2OUT_SHIFT (4U) -#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) -#define USB_INTSTAT_EP2IN_MASK (0x20U) -#define USB_INTSTAT_EP2IN_SHIFT (5U) -#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) -#define USB_INTSTAT_EP3OUT_MASK (0x40U) -#define USB_INTSTAT_EP3OUT_SHIFT (6U) -#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) -#define USB_INTSTAT_EP3IN_MASK (0x80U) -#define USB_INTSTAT_EP3IN_SHIFT (7U) -#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) -#define USB_INTSTAT_EP4OUT_MASK (0x100U) -#define USB_INTSTAT_EP4OUT_SHIFT (8U) -#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) -#define USB_INTSTAT_EP4IN_MASK (0x200U) -#define USB_INTSTAT_EP4IN_SHIFT (9U) -#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) -#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) -#define USB_INTSTAT_FRAME_INT_SHIFT (30U) -#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) -#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) -#define USB_INTSTAT_DEV_INT_SHIFT (31U) -#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) - -/*! @name INTEN - USB interrupt enable register */ -#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) -#define USB_INTEN_EP_INT_EN_SHIFT (0U) -#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) -#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) -#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) -#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) -#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) -#define USB_INTEN_DEV_INT_EN_SHIFT (31U) -#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) - -/*! @name INTSETSTAT - USB set interrupt status register */ -#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) -#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) -#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) -#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) -#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) -#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) -#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) -#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) -#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) - -/*! @name EPTOGGLE - USB Endpoint toggle register */ -#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) -#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) -#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) - - -/*! - * @} - */ /* end of group USB_Register_Masks */ - - -/* USB - Peripheral instance base addresses */ -/** Peripheral USB0 base address */ -#define USB0_BASE (0x40084000u) -/** Peripheral USB0 base pointer */ -#define USB0 ((USB_Type *)USB0_BASE) -/** Array initializer of USB peripheral base addresses */ -#define USB_BASE_ADDRS { USB0_BASE } -/** Array initializer of USB peripheral base pointers */ -#define USB_BASE_PTRS { USB0 } -/** Interrupt vectors for the USB peripheral type */ -#define USB_IRQS { USB0_IRQn } -#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBFSH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer - * @{ - */ - -/** USBFSH - Register Layout Typedef */ -typedef struct { - __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */ - __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */ - __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */ - __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */ - __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */ - __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */ - __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */ - __IO uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */ - __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */ - __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */ - __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */ - __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */ - __IO uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */ - __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */ - __IO uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */ - __IO uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */ - __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */ - __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */ - __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */ - __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */ - __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */ - __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */ - uint8_t RESERVED_0[4]; - __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */ -} USBFSH_Type; - -/* ---------------------------------------------------------------------------- - -- USBFSH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBFSH_Register_Masks USBFSH Register Masks - * @{ - */ - -/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */ -#define USBFSH_HCREVISION_REV_MASK (0xFFU) -#define USBFSH_HCREVISION_REV_SHIFT (0U) -#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK) - -/*! @name HCCONTROL - Defines the operating modes of the HC */ -#define USBFSH_HCCONTROL_CBSR_MASK (0x3U) -#define USBFSH_HCCONTROL_CBSR_SHIFT (0U) -#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK) -#define USBFSH_HCCONTROL_PLE_MASK (0x4U) -#define USBFSH_HCCONTROL_PLE_SHIFT (2U) -#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK) -#define USBFSH_HCCONTROL_IE_MASK (0x8U) -#define USBFSH_HCCONTROL_IE_SHIFT (3U) -#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK) -#define USBFSH_HCCONTROL_CLE_MASK (0x10U) -#define USBFSH_HCCONTROL_CLE_SHIFT (4U) -#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK) -#define USBFSH_HCCONTROL_BLE_MASK (0x20U) -#define USBFSH_HCCONTROL_BLE_SHIFT (5U) -#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK) -#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U) -#define USBFSH_HCCONTROL_HCFS_SHIFT (6U) -#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK) -#define USBFSH_HCCONTROL_IR_MASK (0x100U) -#define USBFSH_HCCONTROL_IR_SHIFT (8U) -#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK) -#define USBFSH_HCCONTROL_RWC_MASK (0x200U) -#define USBFSH_HCCONTROL_RWC_SHIFT (9U) -#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK) -#define USBFSH_HCCONTROL_RWE_MASK (0x400U) -#define USBFSH_HCCONTROL_RWE_SHIFT (10U) -#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK) - -/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */ -#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U) -#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U) -#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK) -#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U) -#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U) -#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK) -#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U) -#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U) -#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK) -#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U) -#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U) -#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK) -#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U) -#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U) -#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK) - -/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */ -#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U) -#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK) -#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U) -#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK) -#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U) -#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK) -#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U) -#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK) -#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U) -#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK) -#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U) -#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK) -#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U) -#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK) -#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U) -#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U) -#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK) - -/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */ -#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U) -#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK) -#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U) -#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK) -#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U) -#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK) -#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U) -#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK) -#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U) -#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK) -#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U) -#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK) -#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U) -#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK) -#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U) -#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U) -#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK) -#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U) -#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U) -#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK) - -/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */ -#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U) -#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK) -#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U) -#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK) -#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U) -#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK) -#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U) -#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK) -#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U) -#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK) -#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U) -#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK) -#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U) -#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK) -#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U) -#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U) -#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK) -#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U) -#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U) -#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK) - -/*! @name HCHCCA - Contains the physical address of the host controller communication area */ -#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U) -#define USBFSH_HCHCCA_HCCA_SHIFT (8U) -#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK) - -/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */ -#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U) -#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK) - -/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */ -#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U) -#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U) -#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK) - -/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */ -#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U) -#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK) - -/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */ -#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U) -#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U) -#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK) - -/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */ -#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U) -#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK) - -/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */ -#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U) -#define USBFSH_HCDONEHEAD_DH_SHIFT (4U) -#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK) - -/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */ -#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU) -#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U) -#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK) -#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U) -#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U) -#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK) -#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U) -#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U) -#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK) - -/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */ -#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU) -#define USBFSH_HCFMREMAINING_FR_SHIFT (0U) -#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK) -#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U) -#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U) -#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK) - -/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */ -#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU) -#define USBFSH_HCFMNUMBER_FN_SHIFT (0U) -#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK) - -/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */ -#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU) -#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U) -#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK) - -/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */ -#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU) -#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U) -#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK) - -/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */ -#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU) -#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U) -#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK) -#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U) -#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U) -#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK) -#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U) -#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U) -#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK) -#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U) -#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U) -#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK) -#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U) -#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U) -#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK) -#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U) -#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U) -#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK) -#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U) -#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U) -#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK) - -/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */ -#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU) -#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U) -#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK) -#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U) -#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U) -#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK) - -/*! @name HCRHSTATUS - This register is divided into two parts */ -#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U) -#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U) -#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK) -#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U) -#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U) -#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK) -#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U) -#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U) -#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK) -#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U) -#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U) -#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK) -#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U) -#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U) -#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK) -#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U) -#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U) -#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK) - -/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */ -#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U) -#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U) -#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK) -#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U) -#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U) -#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK) -#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U) -#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U) -#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK) -#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U) -#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U) -#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK) -#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U) -#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U) -#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK) -#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U) -#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U) -#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK) -#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U) -#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U) -#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK) -#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U) -#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U) -#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK) -#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U) -#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U) -#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK) -#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U) -#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U) -#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK) -#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U) -#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U) -#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK) -#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U) -#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U) -#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK) - -/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ -#define USBFSH_PORTMODE_ID_MASK (0x1U) -#define USBFSH_PORTMODE_ID_SHIFT (0U) -#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK) -#define USBFSH_PORTMODE_ID_EN_MASK (0x100U) -#define USBFSH_PORTMODE_ID_EN_SHIFT (8U) -#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK) -#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) -#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U) -#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK) - - -/*! - * @} - */ /* end of group USBFSH_Register_Masks */ - - -/* USBFSH - Peripheral instance base addresses */ -/** Peripheral USBFSH base address */ -#define USBFSH_BASE (0x400A2000u) -/** Peripheral USBFSH base pointer */ -#define USBFSH ((USBFSH_Type *)USBFSH_BASE) -/** Array initializer of USBFSH peripheral base addresses */ -#define USBFSH_BASE_ADDRS { USBFSH_BASE } -/** Array initializer of USBFSH peripheral base pointers */ -#define USBFSH_BASE_PTRS { USBFSH } -/** Interrupt vectors for the USBFSH peripheral type */ -#define USBFSH_IRQS { USB0_IRQn } -#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBFSH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBHSD Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer - * @{ - */ - -/** USBHSD - Register Layout Typedef */ -typedef struct { - __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ - __I uint32_t INFO; /**< USB Info register, offset: 0x4 */ - __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ - __I uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ - __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ - __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ - __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ - __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ - __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ - __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ - __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ - uint8_t RESERVED_0[8]; - __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ - uint8_t RESERVED_1[4]; - __IO uint32_t ULPIDEBUG; /**< UTMI/ULPI debug register, offset: 0x3C */ -} USBHSD_Type; - -/* ---------------------------------------------------------------------------- - -- USBHSD Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSD_Register_Masks USBHSD Register Masks - * @{ - */ - -/*! @name DEVCMDSTAT - USB Device Command/Status register */ -#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) -#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) -#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK) -#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U) -#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U) -#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK) -#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U) -#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U) -#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK) -#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) -#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) -#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK) -#define USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK (0x400U) -#define USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT (10U) -#define USBHSD_DEVCMDSTAT_FORCE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK) -#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U) -#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U) -#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK) -#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) -#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK) -#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) -#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK) -#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) -#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK) -#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) -#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK) -#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U) -#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U) -#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK) -#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U) -#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U) -#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK) -#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) -#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U) -#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK) -#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) -#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U) -#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK) -#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U) -#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U) -#define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK) -#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U) -#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U) -#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK) -#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) -#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U) -#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK) -#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U) -#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U) -#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK) -#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U) -#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U) -#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK) -#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U) -#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U) -#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK) - -/*! @name INFO - USB Info register */ -#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU) -#define USBHSD_INFO_FRAME_NR_SHIFT (0U) -#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK) -#define USBHSD_INFO_ERR_CODE_MASK (0x7800U) -#define USBHSD_INFO_ERR_CODE_SHIFT (11U) -#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK) -#define USBHSD_INFO_Minrev_MASK (0xFF0000U) -#define USBHSD_INFO_Minrev_SHIFT (16U) -#define USBHSD_INFO_Minrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Minrev_SHIFT)) & USBHSD_INFO_Minrev_MASK) -#define USBHSD_INFO_Majrev_MASK (0xFF000000U) -#define USBHSD_INFO_Majrev_SHIFT (24U) -#define USBHSD_INFO_Majrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Majrev_SHIFT)) & USBHSD_INFO_Majrev_MASK) - -/*! @name EPLISTSTART - USB EP Command/Status List start address */ -#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U) -#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U) -#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK) -#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U) -#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U) -#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK) - -/*! @name DATABUFSTART - USB Data buffer start address */ -#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU) -#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U) -#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK) - -/*! @name LPM - USB Link Power Management register */ -#define USBHSD_LPM_HIRD_HW_MASK (0xFU) -#define USBHSD_LPM_HIRD_HW_SHIFT (0U) -#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK) -#define USBHSD_LPM_HIRD_SW_MASK (0xF0U) -#define USBHSD_LPM_HIRD_SW_SHIFT (4U) -#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK) -#define USBHSD_LPM_DATA_PENDING_MASK (0x100U) -#define USBHSD_LPM_DATA_PENDING_SHIFT (8U) -#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK) - -/*! @name EPSKIP - USB Endpoint skip */ -#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU) -#define USBHSD_EPSKIP_SKIP_SHIFT (0U) -#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK) - -/*! @name EPINUSE - USB Endpoint Buffer in use */ -#define USBHSD_EPINUSE_BUF_MASK (0xFFCU) -#define USBHSD_EPINUSE_BUF_SHIFT (2U) -#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK) - -/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ -#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU) -#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U) -#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK) - -/*! @name INTSTAT - USB interrupt status register */ -#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U) -#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U) -#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK) -#define USBHSD_INTSTAT_EP0IN_MASK (0x2U) -#define USBHSD_INTSTAT_EP0IN_SHIFT (1U) -#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK) -#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U) -#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U) -#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK) -#define USBHSD_INTSTAT_EP1IN_MASK (0x8U) -#define USBHSD_INTSTAT_EP1IN_SHIFT (3U) -#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK) -#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U) -#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U) -#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK) -#define USBHSD_INTSTAT_EP2IN_MASK (0x20U) -#define USBHSD_INTSTAT_EP2IN_SHIFT (5U) -#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK) -#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U) -#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U) -#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK) -#define USBHSD_INTSTAT_EP3IN_MASK (0x80U) -#define USBHSD_INTSTAT_EP3IN_SHIFT (7U) -#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK) -#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U) -#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U) -#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK) -#define USBHSD_INTSTAT_EP4IN_MASK (0x200U) -#define USBHSD_INTSTAT_EP4IN_SHIFT (9U) -#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK) -#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U) -#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U) -#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK) -#define USBHSD_INTSTAT_EP5IN_MASK (0x800U) -#define USBHSD_INTSTAT_EP5IN_SHIFT (11U) -#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK) -#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U) -#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U) -#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK) -#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U) -#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U) -#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK) - -/*! @name INTEN - USB interrupt enable register */ -#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU) -#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U) -#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK) -#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U) -#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U) -#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK) -#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U) -#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U) -#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK) - -/*! @name INTSETSTAT - USB set interrupt status register */ -#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU) -#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U) -#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK) -#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) -#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) -#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK) -#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) -#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U) -#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK) - -/*! @name EPTOGGLE - USB Endpoint toggle register */ -#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU) -#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U) -#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK) - -/*! @name ULPIDEBUG - UTMI/ULPI debug register */ -#define USBHSD_ULPIDEBUG_PHY_ADDR_MASK (0xFFU) -#define USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT (0U) -#define USBHSD_ULPIDEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ADDR_MASK) -#define USBHSD_ULPIDEBUG_PHY_WDATA_MASK (0xFF00U) -#define USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT (8U) -#define USBHSD_ULPIDEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_WDATA_MASK) -#define USBHSD_ULPIDEBUG_PHY_RDATA_MASK (0xFF0000U) -#define USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT (16U) -#define USBHSD_ULPIDEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RDATA_MASK) -#define USBHSD_ULPIDEBUG_PHY_RW_MASK (0x1000000U) -#define USBHSD_ULPIDEBUG_PHY_RW_SHIFT (24U) -#define USBHSD_ULPIDEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RW_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RW_MASK) -#define USBHSD_ULPIDEBUG_PHY_ACCESS_MASK (0x2000000U) -#define USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT (25U) -#define USBHSD_ULPIDEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ACCESS_MASK) -#define USBHSD_ULPIDEBUG_PHY_MODE_MASK (0x80000000U) -#define USBHSD_ULPIDEBUG_PHY_MODE_SHIFT (31U) -#define USBHSD_ULPIDEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_MODE_SHIFT)) & USBHSD_ULPIDEBUG_PHY_MODE_MASK) - - -/*! - * @} - */ /* end of group USBHSD_Register_Masks */ - - -/* USBHSD - Peripheral instance base addresses */ -/** Peripheral USBHSD base address */ -#define USBHSD_BASE (0x40094000u) -/** Peripheral USBHSD base pointer */ -#define USBHSD ((USBHSD_Type *)USBHSD_BASE) -/** Array initializer of USBHSD peripheral base addresses */ -#define USBHSD_BASE_ADDRS { USBHSD_BASE } -/** Array initializer of USBHSD peripheral base pointers */ -#define USBHSD_BASE_PTRS { USBHSD } -/** Interrupt vectors for the USBHSD peripheral type */ -#define USBHSD_IRQS { USB1_IRQn } -#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBHSD_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBHSH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer - * @{ - */ - -/** USBHSH - Register Layout Typedef */ -typedef struct { - __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */ - __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */ - __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x8 */ - __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */ - __IO uint32_t ATL_PTD_BASE_ADDR; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */ - __IO uint32_t ISO_PTD_BASE_ADDR; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */ - __IO uint32_t INT_PTD_BASE_ADDR; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */ - __IO uint32_t DATA_PAYLOAD_BASE_ADDR; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */ - __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */ - __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */ - __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */ - __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */ - __IO uint32_t ATL_PTD_DONE_MAP; /**< Done map for each ATL PTD, offset: 0x30 */ - __IO uint32_t ATL_PTD_SKIP_MAP; /**< Skip map for each ATL PTD, offset: 0x34 */ - __IO uint32_t ISO_PTD_DONE_MAP; /**< Done map for each ISO PTD, offset: 0x38 */ - __IO uint32_t ISO_PTD_SKIP_MAP; /**< Skip map for each ISO PTD, offset: 0x3C */ - __IO uint32_t INT_PTD_DONE_MAP; /**< Done map for each INT PTD, offset: 0x40 */ - __IO uint32_t INT_PTD_SKIP_MAP; /**< Skip map for each INT PTD, offset: 0x44 */ - __IO uint32_t LAST_PTD_INUSE; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */ - __IO uint32_t UTMIPLUS_ULPI_DEBUG; /**< Register to read/write registers in the attached USB PHY, offset: 0x4C */ - __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */ -} USBHSH_Type; - -/* ---------------------------------------------------------------------------- - -- USBHSH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSH_Register_Masks USBHSH Register Masks - * @{ - */ - -/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */ -#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU) -#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U) -#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK) -#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U) -#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U) -#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK) - -/*! @name HCSPARAMS - Host Controller Structural Parameters */ -#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU) -#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U) -#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK) -#define USBHSH_HCSPARAMS_PPC_MASK (0x10U) -#define USBHSH_HCSPARAMS_PPC_SHIFT (4U) -#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK) -#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U) -#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U) -#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK) - -/*! @name HCCPARAMS - Host Controller Capability Parameters */ -#define USBHSH_HCCPARAMS_LPMC_MASK (0x20000U) -#define USBHSH_HCCPARAMS_LPMC_SHIFT (17U) -#define USBHSH_HCCPARAMS_LPMC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK) - -/*! @name FLADJ_FRINDEX - Frame Length Adjustment */ -#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU) -#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U) -#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK) -#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U) -#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U) -#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) - -/*! @name ATL_PTD_BASE_ADDR - Memory base address where ATL PTD0 is stored */ -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK (0x1F0U) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT (4U) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK (0xFFFFFE00U) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT (9U) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK) - -/*! @name ISO_PTD_BASE_ADDR - Memory base address where ISO PTD0 is stored */ -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK (0x3E0U) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT (5U) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK (0xFFFFFC00U) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT (10U) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK) - -/*! @name INT_PTD_BASE_ADDR - Memory base address where INT PTD0 is stored */ -#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK (0x3E0U) -#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT (5U) -#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK) -#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK (0xFFFFFC00U) -#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT (10U) -#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK) - -/*! @name DATA_PAYLOAD_BASE_ADDR - Memory base address that indicates the start of the data payload buffers */ -#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK (0xFFFF0000U) -#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT (16U) -#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT)) & USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK) - -/*! @name USBCMD - USB Command register */ -#define USBHSH_USBCMD_RS_MASK (0x1U) -#define USBHSH_USBCMD_RS_SHIFT (0U) -#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK) -#define USBHSH_USBCMD_HCRESET_MASK (0x2U) -#define USBHSH_USBCMD_HCRESET_SHIFT (1U) -#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK) -#define USBHSH_USBCMD_FLS_MASK (0xCU) -#define USBHSH_USBCMD_FLS_SHIFT (2U) -#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK) -#define USBHSH_USBCMD_LHCR_MASK (0x80U) -#define USBHSH_USBCMD_LHCR_SHIFT (7U) -#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK) -#define USBHSH_USBCMD_ATL_EN_MASK (0x100U) -#define USBHSH_USBCMD_ATL_EN_SHIFT (8U) -#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK) -#define USBHSH_USBCMD_ISO_EN_MASK (0x200U) -#define USBHSH_USBCMD_ISO_EN_SHIFT (9U) -#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK) -#define USBHSH_USBCMD_INT_EN_MASK (0x400U) -#define USBHSH_USBCMD_INT_EN_SHIFT (10U) -#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK) -#define USBHSH_USBCMD_HIRD_MASK (0xF000000U) -#define USBHSH_USBCMD_HIRD_SHIFT (24U) -#define USBHSH_USBCMD_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK) -#define USBHSH_USBCMD_LPM_RWU_MASK (0x10000000U) -#define USBHSH_USBCMD_LPM_RWU_SHIFT (28U) -#define USBHSH_USBCMD_LPM_RWU(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LPM_RWU_SHIFT)) & USBHSH_USBCMD_LPM_RWU_MASK) - -/*! @name USBSTS - USB Interrupt Status register */ -#define USBHSH_USBSTS_PCD_MASK (0x4U) -#define USBHSH_USBSTS_PCD_SHIFT (2U) -#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK) -#define USBHSH_USBSTS_FLR_MASK (0x8U) -#define USBHSH_USBSTS_FLR_SHIFT (3U) -#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK) -#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U) -#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U) -#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK) -#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U) -#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U) -#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK) -#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U) -#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U) -#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK) -#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U) -#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U) -#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK) - -/*! @name USBINTR - USB Interrupt Enable register */ -#define USBHSH_USBINTR_PCDE_MASK (0x4U) -#define USBHSH_USBINTR_PCDE_SHIFT (2U) -#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK) -#define USBHSH_USBINTR_FLRE_MASK (0x8U) -#define USBHSH_USBINTR_FLRE_SHIFT (3U) -#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK) -#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U) -#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U) -#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK) -#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U) -#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U) -#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK) -#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U) -#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U) -#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK) -#define USBHSH_USBINTR_SOF_E_MASK (0x80000U) -#define USBHSH_USBINTR_SOF_E_SHIFT (19U) -#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK) - -/*! @name PORTSC1 - Port Status and Control register */ -#define USBHSH_PORTSC1_CCS_MASK (0x1U) -#define USBHSH_PORTSC1_CCS_SHIFT (0U) -#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK) -#define USBHSH_PORTSC1_CSC_MASK (0x2U) -#define USBHSH_PORTSC1_CSC_SHIFT (1U) -#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK) -#define USBHSH_PORTSC1_PED_MASK (0x4U) -#define USBHSH_PORTSC1_PED_SHIFT (2U) -#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK) -#define USBHSH_PORTSC1_PEDC_MASK (0x8U) -#define USBHSH_PORTSC1_PEDC_SHIFT (3U) -#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK) -#define USBHSH_PORTSC1_OCA_MASK (0x10U) -#define USBHSH_PORTSC1_OCA_SHIFT (4U) -#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK) -#define USBHSH_PORTSC1_OCC_MASK (0x20U) -#define USBHSH_PORTSC1_OCC_SHIFT (5U) -#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK) -#define USBHSH_PORTSC1_FPR_MASK (0x40U) -#define USBHSH_PORTSC1_FPR_SHIFT (6U) -#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK) -#define USBHSH_PORTSC1_SUSP_MASK (0x80U) -#define USBHSH_PORTSC1_SUSP_SHIFT (7U) -#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK) -#define USBHSH_PORTSC1_PR_MASK (0x100U) -#define USBHSH_PORTSC1_PR_SHIFT (8U) -#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK) -#define USBHSH_PORTSC1_SUS_L1_MASK (0x200U) -#define USBHSH_PORTSC1_SUS_L1_SHIFT (9U) -#define USBHSH_PORTSC1_SUS_L1(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK) -#define USBHSH_PORTSC1_LS_MASK (0xC00U) -#define USBHSH_PORTSC1_LS_SHIFT (10U) -#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK) -#define USBHSH_PORTSC1_PP_MASK (0x1000U) -#define USBHSH_PORTSC1_PP_SHIFT (12U) -#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK) -#define USBHSH_PORTSC1_PIC_MASK (0xC000U) -#define USBHSH_PORTSC1_PIC_SHIFT (14U) -#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK) -#define USBHSH_PORTSC1_PTC_MASK (0xF0000U) -#define USBHSH_PORTSC1_PTC_SHIFT (16U) -#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK) -#define USBHSH_PORTSC1_PSPD_MASK (0x300000U) -#define USBHSH_PORTSC1_PSPD_SHIFT (20U) -#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK) -#define USBHSH_PORTSC1_WOO_MASK (0x400000U) -#define USBHSH_PORTSC1_WOO_SHIFT (22U) -#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK) -#define USBHSH_PORTSC1_SUS_STAT_MASK (0x1800000U) -#define USBHSH_PORTSC1_SUS_STAT_SHIFT (23U) -#define USBHSH_PORTSC1_SUS_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK) -#define USBHSH_PORTSC1_DEV_ADD_MASK (0xFE000000U) -#define USBHSH_PORTSC1_DEV_ADD_SHIFT (25U) -#define USBHSH_PORTSC1_DEV_ADD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK) - -/*! @name ATL_PTD_DONE_MAP - Done map for each ATL PTD */ -#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT (0U) -#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT)) & USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK) - -/*! @name ATL_PTD_SKIP_MAP - Skip map for each ATL PTD */ -#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT (0U) -#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT)) & USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK) - -/*! @name ISO_PTD_DONE_MAP - Done map for each ISO PTD */ -#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT (0U) -#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT)) & USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK) - -/*! @name ISO_PTD_SKIP_MAP - Skip map for each ISO PTD */ -#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT (0U) -#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT)) & USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK) - -/*! @name INT_PTD_DONE_MAP - Done map for each INT PTD */ -#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT (0U) -#define USBHSH_INT_PTD_DONE_MAP_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT)) & USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK) - -/*! @name INT_PTD_SKIP_MAP - Skip map for each INT PTD */ -#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT (0U) -#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT)) & USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK) - -/*! @name LAST_PTD_INUSE - Marks the last PTD in the list for ISO, INT and ATL */ -#define USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK (0x1FU) -#define USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT (0U) -#define USBHSH_LAST_PTD_INUSE_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK) -#define USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK (0x1F00U) -#define USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT (8U) -#define USBHSH_LAST_PTD_INUSE_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK) -#define USBHSH_LAST_PTD_INUSE_INT_LAST_MASK (0x1F0000U) -#define USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT (16U) -#define USBHSH_LAST_PTD_INUSE_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_INT_LAST_MASK) - -/*! @name UTMIPLUS_ULPI_DEBUG - Register to read/write registers in the attached USB PHY */ -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK (0xFFU) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT (0U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK (0xFF00U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT (8U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK (0xFF0000U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT (16U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK (0x1000000U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT (24U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK (0x2000000U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT (25U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK (0x80000000U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT (31U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK) - -/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ -#define USBHSH_PORTMODE_ID0_MASK (0x1U) -#define USBHSH_PORTMODE_ID0_SHIFT (0U) -#define USBHSH_PORTMODE_ID0(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_SHIFT)) & USBHSH_PORTMODE_ID0_MASK) -#define USBHSH_PORTMODE_ID0_EN_MASK (0x100U) -#define USBHSH_PORTMODE_ID0_EN_SHIFT (8U) -#define USBHSH_PORTMODE_ID0_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_EN_SHIFT)) & USBHSH_PORTMODE_ID0_EN_MASK) -#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) -#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U) -#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK) -#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U) -#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U) -#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK) -#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U) -#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U) -#define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK) - - -/*! - * @} - */ /* end of group USBHSH_Register_Masks */ - - -/* USBHSH - Peripheral instance base addresses */ -/** Peripheral USBHSH base address */ -#define USBHSH_BASE (0x400A3000u) -/** Peripheral USBHSH base pointer */ -#define USBHSH ((USBHSH_Type *)USBHSH_BASE) -/** Array initializer of USBHSH peripheral base addresses */ -#define USBHSH_BASE_ADDRS { USBHSH_BASE } -/** Array initializer of USBHSH peripheral base pointers */ -#define USBHSH_BASE_PTRS { USBHSH } -/** Interrupt vectors for the USBHSH peripheral type */ -#define USBHSH_IRQS { USB1_IRQn } -#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBHSH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- UTICK Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer - * @{ - */ - -/** UTICK - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ - __IO uint32_t STAT; /**< Status register., offset: 0x4 */ - __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ - __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ - __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ -} UTICK_Type; - -/* ---------------------------------------------------------------------------- - -- UTICK Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Register_Masks UTICK Register Masks - * @{ - */ - -/*! @name CTRL - Control register. */ -#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) -#define UTICK_CTRL_DELAYVAL_SHIFT (0U) -#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) -#define UTICK_CTRL_REPEAT_MASK (0x80000000U) -#define UTICK_CTRL_REPEAT_SHIFT (31U) -#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) - -/*! @name STAT - Status register. */ -#define UTICK_STAT_INTR_MASK (0x1U) -#define UTICK_STAT_INTR_SHIFT (0U) -#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) -#define UTICK_STAT_ACTIVE_MASK (0x2U) -#define UTICK_STAT_ACTIVE_SHIFT (1U) -#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) - -/*! @name CFG - Capture configuration register. */ -#define UTICK_CFG_CAPEN0_MASK (0x1U) -#define UTICK_CFG_CAPEN0_SHIFT (0U) -#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) -#define UTICK_CFG_CAPEN1_MASK (0x2U) -#define UTICK_CFG_CAPEN1_SHIFT (1U) -#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) -#define UTICK_CFG_CAPEN2_MASK (0x4U) -#define UTICK_CFG_CAPEN2_SHIFT (2U) -#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) -#define UTICK_CFG_CAPEN3_MASK (0x8U) -#define UTICK_CFG_CAPEN3_SHIFT (3U) -#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) -#define UTICK_CFG_CAPPOL0_MASK (0x100U) -#define UTICK_CFG_CAPPOL0_SHIFT (8U) -#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) -#define UTICK_CFG_CAPPOL1_MASK (0x200U) -#define UTICK_CFG_CAPPOL1_SHIFT (9U) -#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) -#define UTICK_CFG_CAPPOL2_MASK (0x400U) -#define UTICK_CFG_CAPPOL2_SHIFT (10U) -#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) -#define UTICK_CFG_CAPPOL3_MASK (0x800U) -#define UTICK_CFG_CAPPOL3_SHIFT (11U) -#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) - -/*! @name CAPCLR - Capture clear register. */ -#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) -#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) -#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) -#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) -#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) -#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) -#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) -#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) -#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) -#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) -#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) -#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) - -/*! @name CAP - Capture register . */ -#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) -#define UTICK_CAP_CAP_VALUE_SHIFT (0U) -#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) -#define UTICK_CAP_VALID_MASK (0x80000000U) -#define UTICK_CAP_VALID_SHIFT (31U) -#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) - -/* The count of UTICK_CAP */ -#define UTICK_CAP_COUNT (4U) - - -/*! - * @} - */ /* end of group UTICK_Register_Masks */ - - -/* UTICK - Peripheral instance base addresses */ -/** Peripheral UTICK0 base address */ -#define UTICK0_BASE (0x4000E000u) -/** Peripheral UTICK0 base pointer */ -#define UTICK0 ((UTICK_Type *)UTICK0_BASE) -/** Array initializer of UTICK peripheral base addresses */ -#define UTICK_BASE_ADDRS { UTICK0_BASE } -/** Array initializer of UTICK peripheral base pointers */ -#define UTICK_BASE_PTRS { UTICK0 } -/** Interrupt vectors for the UTICK peripheral type */ -#define UTICK_IRQS { UTICK0_IRQn } - -/*! - * @} - */ /* end of group UTICK_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- WWDT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer - * @{ - */ - -/** WWDT - Register Layout Typedef */ -typedef struct { - __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ - __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ - __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ - __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ - uint8_t RESERVED_0[4]; - __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ - __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ -} WWDT_Type; - -/* ---------------------------------------------------------------------------- - -- WWDT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Register_Masks WWDT Register Masks - * @{ - */ - -/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ -#define WWDT_MOD_WDEN_MASK (0x1U) -#define WWDT_MOD_WDEN_SHIFT (0U) -#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) -#define WWDT_MOD_WDRESET_MASK (0x2U) -#define WWDT_MOD_WDRESET_SHIFT (1U) -#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) -#define WWDT_MOD_WDTOF_MASK (0x4U) -#define WWDT_MOD_WDTOF_SHIFT (2U) -#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) -#define WWDT_MOD_WDINT_MASK (0x8U) -#define WWDT_MOD_WDINT_SHIFT (3U) -#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) -#define WWDT_MOD_WDPROTECT_MASK (0x10U) -#define WWDT_MOD_WDPROTECT_SHIFT (4U) -#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) -#define WWDT_MOD_LOCK_MASK (0x20U) -#define WWDT_MOD_LOCK_SHIFT (5U) -#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) - -/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ -#define WWDT_TC_COUNT_MASK (0xFFFFFFU) -#define WWDT_TC_COUNT_SHIFT (0U) -#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) - -/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ -#define WWDT_FEED_FEED_MASK (0xFFU) -#define WWDT_FEED_FEED_SHIFT (0U) -#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) - -/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ -#define WWDT_TV_COUNT_MASK (0xFFFFFFU) -#define WWDT_TV_COUNT_SHIFT (0U) -#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) - -/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ -#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) -#define WWDT_WARNINT_WARNINT_SHIFT (0U) -#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) - -/*! @name WINDOW - Watchdog Window compare value. */ -#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) -#define WWDT_WINDOW_WINDOW_SHIFT (0U) -#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) - - -/*! - * @} - */ /* end of group WWDT_Register_Masks */ - - -/* WWDT - Peripheral instance base addresses */ -/** Peripheral WWDT base address */ -#define WWDT_BASE (0x4000C000u) -/** Peripheral WWDT base pointer */ -#define WWDT ((WWDT_Type *)WWDT_BASE) -/** Array initializer of WWDT peripheral base addresses */ -#define WWDT_BASE_ADDRS { WWDT_BASE } -/** Array initializer of WWDT peripheral base pointers */ -#define WWDT_BASE_PTRS { WWDT } -/** Interrupt vectors for the WWDT peripheral type */ -#define WWDT_IRQS { WDT_BOD_IRQn } - -/*! - * @} - */ /* end of group WWDT_Peripheral_Access_Layer */ - - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma pop -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -/*! - * @} - */ /* end of group Peripheral_access_layer */ - - -/* ---------------------------------------------------------------------------- - -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - * @{ - */ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang system_header - #endif -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma system_include -#endif - -/** - * @brief Mask and left-shift a bit field value for use in a register bit range. - * @param field Name of the register bit field. - * @param value Value of the bit field. - * @return Masked and shifted value. - */ -#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) -/** - * @brief Mask and right-shift a register value to extract a bit field value. - * @param field Name of the register bit field. - * @param value Value of the register. - * @return Masked and shifted bit field value. - */ -#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) - -/*! - * @} - */ /* end of group Bit_Field_Generic_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SDK Compatibility - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDK_Compatibility_Symbols SDK Compatibility - * @{ - */ - -/** EMC CS base address */ -#define EMC_CS0_BASE (0x80000000u) -#define EMC_CS1_BASE (0x90000000u) -#define EMC_CS2_BASE (0x98000000u) -#define EMC_CS3_BASE (0x9C000000u) -#define EMC_DYCS0_BASE (0xA0000000u) -#define EMC_DYCS1_BASE (0xB0000000u) -#define EMC_DYCS2_BASE (0xC0000000u) -#define EMC_DYCS3_BASE (0xD0000000u) -#define EMC_CS_ADDRESS {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE} -#define EMC_DYCS_ADDRESS {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE} - -/** OTP API */ -typedef struct { - uint32_t (*otpInit)(void); /** Initializes OTP controller */ - uint32_t (*otpEnableBankWriteMask)(uint32_t bankMask); /** Unlock one or more OTP banks for write access */ - uint32_t (*otpDisableBankWriteMask)(uint32_t bankMask); /** Lock one or more OTP banks for write access */ - uint32_t (*otpEnableBankWriteLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask, - uint32_t lockWrite); /** Locks or unlocks write access to a register of an OTP bank and the write lock */ - uint32_t (*otpEnableBankReadLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask, - uint32_t lockWrite); /** Locks or unlocks read access to a register of an OTP bank and the write lock */ - uint32_t (*otpProgramReg)(uint32_t bankIndex, uint32_t regIndex, uint32_t value); /** Program a single register in an OTP bank */ - uint32_t RESERVED_0[5]; - uint32_t (*rngRead)(void); /** Returns 32-bit number from hardware random number generator */ - uint32_t (*otpGetDriverVersion)(void); /** Returns the version of the OTP driver in ROM */ -} OTP_API_Type; - -/** ROM API */ -typedef struct { - __I uint32_t usbdApiBase; /** USB API Base */ - uint32_t RESERVED_0[13]; - __I OTP_API_Type *otpApiBase; /** OTP API Base */ - __I uint32_t aesApiBase; /** AES API Base */ - __I uint32_t secureApiBase; /** Secure API Base */ -} ROM_API_Type; - -/** ROM API base address */ -#define ROM_API_BASE (0x03000200u) -/** ROM API base pointer */ -#define ROM_API (*(ROM_API_Type**) ROM_API_BASE) -/** OTP API base pointer */ -#define OTP_API (ROM_API->otpApiBase) - -/*! - * @} - */ /* end of group SDK_Compatibility_Symbols */ - - -#endif /* _LPC54608_H_ */ - diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/LPC54608_features.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/LPC54608_features.h deleted file mode 100644 index 1bdb5d04e33..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/LPC54608_features.h +++ /dev/null @@ -1,231 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.1, 2016-11-25 -** Build: b170112 -** -** Abstract: -** Chip specific module features. -** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2016-08-12) -** Initial version. -** - rev. 1.1 (2016-11-25) -** Update CANFD and Classic CAN register. -** Add MAC TIMERSTAMP registers. -** -** ################################################################### -*/ - -#ifndef _LPC54608_FEATURES_H_ -#define _LPC54608_FEATURES_H_ - -/* SOC module features */ - -/* @brief ADC availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC_COUNT (1) -/* @brief ASYNC_SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1) -/* @brief CRC availability on the SoC. */ -#define FSL_FEATURE_SOC_CRC_COUNT (1) -/* @brief DMA availability on the SoC. */ -#define FSL_FEATURE_SOC_DMA_COUNT (1) -/* @brief DMIC availability on the SoC. */ -#define FSL_FEATURE_SOC_DMIC_COUNT (1) -/* @brief FLEXCOMM availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (10) -/* @brief GINT availability on the SoC. */ -#define FSL_FEATURE_SOC_GINT_COUNT (2) -/* @brief GPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_GPIO_COUNT (1) -/* @brief I2C availability on the SoC. */ -#define FSL_FEATURE_SOC_I2C_COUNT (10) -/* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (2) -/* @brief INPUTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) -/* @brief IOCON availability on the SoC. */ -#define FSL_FEATURE_SOC_IOCON_COUNT (1) -/* @brief MRT availability on the SoC. */ -#define FSL_FEATURE_SOC_MRT_COUNT (1) -/* @brief PINT availability on the SoC. */ -#define FSL_FEATURE_SOC_PINT_COUNT (1) -/* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (1) -/* @brief SCT availability on the SoC. */ -#define FSL_FEATURE_SOC_SCT_COUNT (1) -/* @brief SPI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPI_COUNT (10) -/* @brief SPIFI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPIFI_COUNT (1) -/* @brief SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCON_COUNT (1) -/* @brief CTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_CTIMER_COUNT (5) -/* @brief USART availability on the SoC. */ -#define FSL_FEATURE_SOC_USART_COUNT (10) -/* @brief USB availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_COUNT (1) -/* @brief UTICK availability on the SoC. */ -#define FSL_FEATURE_SOC_UTICK_COUNT (1) -/* @brief WWDT availability on the SoC. */ -#define FSL_FEATURE_SOC_WWDT_COUNT (1) -/* @brief USBFSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBFSH_COUNT (1) -/* @brief USBHSD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSD_COUNT (1) -/* @brief USBHSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSH_COUNT (1) -/* @brief EEPROM availability on the SoC. */ -#define FSL_FEATURE_SOC_EEPROM_COUNT (1) -/* @brief EMC availability on the SoC. */ -#define FSL_FEATURE_SOC_EMC_COUNT (1) -/* @brief ENET availability on the SoC. */ -#define FSL_FEATURE_SOC_LPC_ENET_COUNT (1) -/* @brief SDIF availability on the SoC. */ -#define FSL_FEATURE_SOC_SDIF_COUNT (1) -/* @brief SMARTCARD availability on the SoC. */ -#define FSL_FEATURE_SOC_SMARTCARD_COUNT (2) -/* @brief LCD availability on the SoC. */ -#define FSL_FEATURE_SOC_LCD_COUNT (1) -/* @brief CAN availability on the SoC. */ -#define FSL_FEATURE_SOC_LPC_CAN_COUNT (2) -/* @brief SHA availability on the SoC. */ -#define FSL_FEATURE_SOC_SHA_COUNT (0) -/* @brief AES availability on the SoC. */ -#define FSL_FEATURE_SOC_AES_COUNT (0) -/* @brief RIT availability on the SoC. */ -#define FSL_FEATURE_SOC_RIT_COUNT (1) -/* @brief FMC availability on the SoC. */ -#define FSL_FEATURE_SOC_FMC_COUNT (1) -/* @brief RNG availability on the SoC. */ -#define FSL_FEATURE_SOC_LPC_RNG_COUNT (1) - -/* CAN module features */ - -/* @brief Support CANFD or not */ -#define FSL_FEATURE_CAN_SUPPORT_CANFD (0) - -/* DMA module features */ - -/* @brief Number of channels */ -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30) - -/* EEPROM module features */ - -/* @brief Size of the EEPROM */ -#define FSL_FEATURE_EEPROM_SIZE (0x00004000) -/* @brief Base address of the EEPROM */ -#define FSL_FEATURE_EEPROM_BASE_ADDRESS (0x40108000) -/* @brief Page count of the EEPROM */ -#define FSL_FEATURE_EEPROM_PAGE_COUNT (128) -/* @brief Command number for eeprom program */ -#define FSL_FEATURE_EEPROM_PROGRAM_CMD (6) -/* @brief EEPROM internal clock freqency */ -#define FSL_FEATURE_EEPROM_INTERNAL_FREQ (1500000) - -/* IOCON module features */ - -/* @brief Func bit field width */ -#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) - -/* PINT module features */ - -/* @brief Number of connected outputs */ -#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) - -/* SCT module features */ - -/* @brief Number of events */ -#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (10) -/* @brief Number of states */ -#define FSL_FEATURE_SCT_NUMBER_OF_STATES (10) -/* @brief Number of match capture */ -#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) - -/* SDIF module features */ - -/* @brief FIFO depth, every location is a WORD */ -#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) -/* @brief Max DMA buffer size */ -#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) -/* @brief Max source clock in HZ */ -#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) - -/* SPIFI module features */ - -/* @brief SPIFI start address */ -#define FSL_FEATURE_SPIFI_START_ADDR (0x10000000) -/* @brief SPIFI end address */ -#define FSL_FEATURE_SPIFI_END_ADDR (0x17FFFFFF) - -/* SYSCON module features */ - -/* @brief Pointer to ROM IAP entry functions */ -#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205) -/* @brief Flash page size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256) -/* @brief Flash sector size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) -/* @brief Flash size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288) - -/* USB module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USB_USB_RAM (0x00002000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) - -/* USBFSH module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBFSH_USB_RAM (0x00002000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) - -/* USBHSD module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSD_USB_RAM (0x00002000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) - -/* USBHSH module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSH_USB_RAM (0x00002000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) - -#endif /* _LPC54608_FEATURES_H_ */ - diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/SConscript b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/SConscript deleted file mode 100644 index a825e384326..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/SConscript +++ /dev/null @@ -1,32 +0,0 @@ -# RT-Thread building script for bridge - -import os -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -objs = [] -list = os.listdir(cwd) -CPPDEFINES = [] - -objs = objs + SConscript(os.path.join('drivers', 'SConscript')) -objs = objs + SConscript(os.path.join('utilities', 'SConscript')) - -if rtconfig.PLATFORM in ['gcc']: - objs = objs + SConscript(os.path.join('mcuxpresso', 'SConscript')) - CPPDEFINES += ['__USE_CMSIS'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - objs = objs + SConscript(os.path.join('arm', 'SConscript')) -elif rtconfig.PLATFORM in ['iccarm']: - objs = objs + SConscript(os.path.join('iar', 'SConscript')) - -src = Glob('*.c') -CPPPATH = [cwd] -CPPDEFINES += ['CORE_M4', 'CPU_LPC54608', 'CPU_LPC54608J512ET180=1'] - -group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) - -objs = objs + group - -Return('objs') diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/arm/LPC54608J512_flash.scf b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/arm/LPC54608J512_flash.scf deleted file mode 100644 index 0e5d8933316..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/arm/LPC54608J512_flash.scf +++ /dev/null @@ -1,120 +0,0 @@ -#! armcc -E -/* -** ################################################################### -** Processors: LPC54608J512BD208 -** LPC54608J512ET180 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC54S60x/LPC5460x User manual Rev.0.9 7 Nov 2016 -** Version: rev. 1.1, 2016-11-25 -** Build: b161227 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -#if (defined(__ram_vector_table__)) - #define __ram_vector_table_size__ 0x00000400 -#else - #define __ram_vector_table_size__ 0x00000000 -#endif - -#define m_interrupts_start 0x00000000 -#define m_interrupts_size 0x00000400 - -#define m_text_start 0x00000400 -#define m_text_size 0x0007FC00 - -#define m_interrupts_ram_start 0x20000000 -#define m_interrupts_ram_size __ram_vector_table_size__ - -#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size) -#define m_data_size (0x00028000 - m_interrupts_ram_size) - -#define m_usb_sram_start 0x40100000 -#define m_usb_sram_size 0x00002000 - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (RESET,+FIRST) - } - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - -#if (defined(__ram_vector_table__)) - VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size { - } -#else - VECTOR_RAM m_interrupts_start EMPTY 0 { - } -#endif - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } -} - -LR_m_usb_bdt m_usb_sram_start usb_bdt_size { - ER_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (m_usb_bdt) - } -} - -LR_m_usb_ram (m_usb_sram_start + usb_bdt_size) (m_usb_sram_size - usb_bdt_size) { - ER_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (m_usb_global) - } -} - diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/arm/LPC54608J512_ram.scf b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/arm/LPC54608J512_ram.scf deleted file mode 100644 index 61ffe44d0ff..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/arm/LPC54608J512_ram.scf +++ /dev/null @@ -1,113 +0,0 @@ -#! armcc -E -/* -** ################################################################### -** Processors: LPC54608J512BD208 -** LPC54608J512ET180 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC54S60x/LPC5460x User manual Rev.0.9 7 Nov 2016 -** Version: rev. 1.1, 2016-11-25 -** Build: b161227 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -#define m_interrupts_start 0x20000000 -#define m_interrupts_size 0x00000400 - -#define m_text_start 0x20000400 -#define m_text_size 0x00013E00 - -#define m_data_start 0x20014200 -#define m_data_size 0x00013E00 - -#define m_usb_sram_start 0x40100000 -#define m_usb_sram_size 0x00002000 - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -LR_m_text m_text_start m_text_size { ; load region size_region - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } -} - -LR_m_interrupts m_interrupts_start m_interrupts_size { - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (RESET,+FIRST) - } -} - -LR_m_interrupts_ram m_interrupts_start m_interrupts_size { - VECTOR_RAM m_interrupts_start m_interrupts_size { ; load address = execution address - .ANY (.m_interrupts_ram) - } -} - -LR_m_usb_bdt m_usb_sram_start usb_bdt_size { - ER_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (m_usb_bdt) - } -} - -LR_m_usb_ram (m_usb_sram_start + usb_bdt_size) (m_usb_sram_size - usb_bdt_size) { - ER_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (m_usb_global) - } -} - diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/arm/SConscript b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/arm/SConscript deleted file mode 100644 index 0ff9f8cb3e7..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/arm/SConscript +++ /dev/null @@ -1,10 +0,0 @@ -from building import * - -cwd = GetCurrentDir() -src = Split(''' -startup_LPC54608.s -''') - -group = DefineGroup('CMSIS', src, depend = [''], LIBS=['keil_lib_power'], LIBPATH=[cwd]) - -Return('group') diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/arm/keil_lib_power.lib b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/arm/keil_lib_power.lib deleted file mode 100644 index 2cab4e5e686..00000000000 Binary files a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/arm/keil_lib_power.lib and /dev/null differ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/arm/startup_LPC54608.s b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/arm/startup_LPC54608.s deleted file mode 100644 index 7416e0e5449..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/arm/startup_LPC54608.s +++ /dev/null @@ -1,713 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC54608.s -; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the -; * LPC54608 -; * @version: 1.1 -; * @date: 2016-11-25 -; * -; * Copyright 1997 - 2016 Freescale Semiconductor, Inc. -; * Copyright 2016 - 2017 NXP -; * -; * Redistribution and use in source and binary forms, with or without modification, -; * are permitted provided that the following conditions are met: -; * -; * o Redistributions of source code must retain the above copyright notice, this list -; * of conditions and the following disclaimer. -; * -; * o Redistributions in binary form must reproduce the above copyright notice, this -; * list of conditions and the following disclaimer in the documentation and/or -; * other materials provided with the distribution. -; * -; * o Neither the name of the copyright holder nor the names of its -; * contributors may be used to endorse or promote products derived from this -; * software without specific prior written permission. -; * -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 ; Checksum of the first 7 words - DCD 0xFFFFFFFF ; ECRP - DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot - DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect - DCD DMA0_IRQHandler ; DMA controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) - DCD ADC0_SEQA_IRQHandler ; ADC0 sequence A completion. - DCD ADC0_SEQB_IRQHandler ; ADC0 sequence B completion. - DCD ADC0_THCMP_IRQHandler ; ADC0 threshold compare and error. - DCD DMIC0_IRQHandler ; Digital microphone and DMIC subsystem - DCD HWVAD0_IRQHandler ; Hardware Voice Activity Detector - DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt - DCD USB0_IRQHandler ; USB device - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD Reserved46_IRQHandler ; Reserved interrupt - DCD Reserved47_IRQHandler ; Reserved interrupt - DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int - DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int - DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int - DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int - DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 - DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 - DCD RIT_IRQHandler ; Repetitive Interrupt Timer - DCD SPIFI0_IRQHandler ; SPI flash interface - DCD FLEXCOMM8_IRQHandler ; Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM9_IRQHandler ; Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) - DCD SDIO_IRQHandler ; SD/MMC - DCD CAN0_IRQ0_IRQHandler ; CAN0 interrupt0 - DCD CAN0_IRQ1_IRQHandler ; CAN0 interrupt1 - DCD CAN1_IRQ0_IRQHandler ; CAN1 interrupt0 - DCD CAN1_IRQ1_IRQHandler ; CAN1 interrupt1 - DCD USB1_IRQHandler ; USB1 interrupt - DCD USB1_NEEDCLK_IRQHandler ; USB1 activity - DCD ETHERNET_IRQHandler ; Ethernet - DCD ETHERNET_PMT_IRQHandler ; Ethernet power management interrupt - DCD ETHERNET_MACLP_IRQHandler ; Ethernet MAC interrupt - DCD EEPROM_IRQHandler ; EEPROM interrupt - DCD LCD_IRQHandler ; LCD interrupt - DCD SHA_IRQHandler ; SHA interrupt - DCD SMARTCARD0_IRQHandler ; Smart card 0 interrupt - DCD SMARTCARD1_IRQHandler ; Smart card 1 interrupt - - AREA |.text|, CODE, READONLY - -; Reset Handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR r0, =SystemInit - BLX r0 - LDR r0, =__main - BX r0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -HardFault_Handler \ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -MemManage_Handler PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP - -BusFault_Handler PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP - -UsageFault_Handler PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP - -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP - -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -WDT_BOD_IRQHandler\ - PROC - EXPORT WDT_BOD_IRQHandler [WEAK] - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - ENDP - -DMA0_IRQHandler\ - PROC - EXPORT DMA0_IRQHandler [WEAK] - LDR R0, =DMA0_DriverIRQHandler - BX R0 - ENDP - -GINT0_IRQHandler\ - PROC - EXPORT GINT0_IRQHandler [WEAK] - LDR R0, =GINT0_DriverIRQHandler - BX R0 - ENDP - -GINT1_IRQHandler\ - PROC - EXPORT GINT1_IRQHandler [WEAK] - LDR R0, =GINT1_DriverIRQHandler - BX R0 - ENDP - -PIN_INT0_IRQHandler\ - PROC - EXPORT PIN_INT0_IRQHandler [WEAK] - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - ENDP - -PIN_INT1_IRQHandler\ - PROC - EXPORT PIN_INT1_IRQHandler [WEAK] - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - ENDP - -PIN_INT2_IRQHandler\ - PROC - EXPORT PIN_INT2_IRQHandler [WEAK] - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - ENDP - -PIN_INT3_IRQHandler\ - PROC - EXPORT PIN_INT3_IRQHandler [WEAK] - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - ENDP - -UTICK0_IRQHandler\ - PROC - EXPORT UTICK0_IRQHandler [WEAK] - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - ENDP - -MRT0_IRQHandler\ - PROC - EXPORT MRT0_IRQHandler [WEAK] - LDR R0, =MRT0_DriverIRQHandler - BX R0 - ENDP - -CTIMER0_IRQHandler\ - PROC - EXPORT CTIMER0_IRQHandler [WEAK] - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - ENDP - -CTIMER1_IRQHandler\ - PROC - EXPORT CTIMER1_IRQHandler [WEAK] - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - ENDP - -SCT0_IRQHandler\ - PROC - EXPORT SCT0_IRQHandler [WEAK] - LDR R0, =SCT0_DriverIRQHandler - BX R0 - ENDP - -CTIMER3_IRQHandler\ - PROC - EXPORT CTIMER3_IRQHandler [WEAK] - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM0_IRQHandler\ - PROC - EXPORT FLEXCOMM0_IRQHandler [WEAK] - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM1_IRQHandler\ - PROC - EXPORT FLEXCOMM1_IRQHandler [WEAK] - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM2_IRQHandler\ - PROC - EXPORT FLEXCOMM2_IRQHandler [WEAK] - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM3_IRQHandler\ - PROC - EXPORT FLEXCOMM3_IRQHandler [WEAK] - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM4_IRQHandler\ - PROC - EXPORT FLEXCOMM4_IRQHandler [WEAK] - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM5_IRQHandler\ - PROC - EXPORT FLEXCOMM5_IRQHandler [WEAK] - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM6_IRQHandler\ - PROC - EXPORT FLEXCOMM6_IRQHandler [WEAK] - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM7_IRQHandler\ - PROC - EXPORT FLEXCOMM7_IRQHandler [WEAK] - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - ENDP - -ADC0_SEQA_IRQHandler\ - PROC - EXPORT ADC0_SEQA_IRQHandler [WEAK] - LDR R0, =ADC0_SEQA_DriverIRQHandler - BX R0 - ENDP - -ADC0_SEQB_IRQHandler\ - PROC - EXPORT ADC0_SEQB_IRQHandler [WEAK] - LDR R0, =ADC0_SEQB_DriverIRQHandler - BX R0 - ENDP - -ADC0_THCMP_IRQHandler\ - PROC - EXPORT ADC0_THCMP_IRQHandler [WEAK] - LDR R0, =ADC0_THCMP_DriverIRQHandler - BX R0 - ENDP - -DMIC0_IRQHandler\ - PROC - EXPORT DMIC0_IRQHandler [WEAK] - LDR R0, =DMIC0_DriverIRQHandler - BX R0 - ENDP - -HWVAD0_IRQHandler\ - PROC - EXPORT HWVAD0_IRQHandler [WEAK] - LDR R0, =HWVAD0_DriverIRQHandler - BX R0 - ENDP - -USB0_NEEDCLK_IRQHandler\ - PROC - EXPORT USB0_NEEDCLK_IRQHandler [WEAK] - LDR R0, =USB0_NEEDCLK_DriverIRQHandler - BX R0 - ENDP - -USB0_IRQHandler\ - PROC - EXPORT USB0_IRQHandler [WEAK] - LDR R0, =USB0_DriverIRQHandler - BX R0 - ENDP - -RTC_IRQHandler\ - PROC - EXPORT RTC_IRQHandler [WEAK] - LDR R0, =RTC_DriverIRQHandler - BX R0 - ENDP - -Reserved46_IRQHandler\ - PROC - EXPORT Reserved46_IRQHandler [WEAK] - LDR R0, =Reserved46_DriverIRQHandler - BX R0 - ENDP - -Reserved47_IRQHandler\ - PROC - EXPORT Reserved47_IRQHandler [WEAK] - LDR R0, =Reserved47_DriverIRQHandler - BX R0 - ENDP - -PIN_INT4_IRQHandler\ - PROC - EXPORT PIN_INT4_IRQHandler [WEAK] - LDR R0, =PIN_INT4_DriverIRQHandler - BX R0 - ENDP - -PIN_INT5_IRQHandler\ - PROC - EXPORT PIN_INT5_IRQHandler [WEAK] - LDR R0, =PIN_INT5_DriverIRQHandler - BX R0 - ENDP - -PIN_INT6_IRQHandler\ - PROC - EXPORT PIN_INT6_IRQHandler [WEAK] - LDR R0, =PIN_INT6_DriverIRQHandler - BX R0 - ENDP - -PIN_INT7_IRQHandler\ - PROC - EXPORT PIN_INT7_IRQHandler [WEAK] - LDR R0, =PIN_INT7_DriverIRQHandler - BX R0 - ENDP - -CTIMER2_IRQHandler\ - PROC - EXPORT CTIMER2_IRQHandler [WEAK] - LDR R0, =CTIMER2_DriverIRQHandler - BX R0 - ENDP - -CTIMER4_IRQHandler\ - PROC - EXPORT CTIMER4_IRQHandler [WEAK] - LDR R0, =CTIMER4_DriverIRQHandler - BX R0 - ENDP - -RIT_IRQHandler\ - PROC - EXPORT RIT_IRQHandler [WEAK] - LDR R0, =RIT_DriverIRQHandler - BX R0 - ENDP - -SPIFI0_IRQHandler\ - PROC - EXPORT SPIFI0_IRQHandler [WEAK] - LDR R0, =SPIFI0_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM8_IRQHandler\ - PROC - EXPORT FLEXCOMM8_IRQHandler [WEAK] - LDR R0, =FLEXCOMM8_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM9_IRQHandler\ - PROC - EXPORT FLEXCOMM9_IRQHandler [WEAK] - LDR R0, =FLEXCOMM9_DriverIRQHandler - BX R0 - ENDP - -SDIO_IRQHandler\ - PROC - EXPORT SDIO_IRQHandler [WEAK] - LDR R0, =SDIO_DriverIRQHandler - BX R0 - ENDP - -CAN0_IRQ0_IRQHandler\ - PROC - EXPORT CAN0_IRQ0_IRQHandler [WEAK] - LDR R0, =CAN0_IRQ0_DriverIRQHandler - BX R0 - ENDP - -CAN0_IRQ1_IRQHandler\ - PROC - EXPORT CAN0_IRQ1_IRQHandler [WEAK] - LDR R0, =CAN0_IRQ1_DriverIRQHandler - BX R0 - ENDP - -CAN1_IRQ0_IRQHandler\ - PROC - EXPORT CAN1_IRQ0_IRQHandler [WEAK] - LDR R0, =CAN1_IRQ0_DriverIRQHandler - BX R0 - ENDP - -CAN1_IRQ1_IRQHandler\ - PROC - EXPORT CAN1_IRQ1_IRQHandler [WEAK] - LDR R0, =CAN1_IRQ1_DriverIRQHandler - BX R0 - ENDP - -USB1_IRQHandler\ - PROC - EXPORT USB1_IRQHandler [WEAK] - LDR R0, =USB1_DriverIRQHandler - BX R0 - ENDP - -USB1_NEEDCLK_IRQHandler\ - PROC - EXPORT USB1_NEEDCLK_IRQHandler [WEAK] - LDR R0, =USB1_NEEDCLK_DriverIRQHandler - BX R0 - ENDP - -ETHERNET_IRQHandler\ - PROC - EXPORT ETHERNET_IRQHandler [WEAK] - LDR R0, =ETHERNET_DriverIRQHandler - BX R0 - ENDP - -ETHERNET_PMT_IRQHandler\ - PROC - EXPORT ETHERNET_PMT_IRQHandler [WEAK] - LDR R0, =ETHERNET_PMT_DriverIRQHandler - BX R0 - ENDP - -ETHERNET_MACLP_IRQHandler\ - PROC - EXPORT ETHERNET_MACLP_IRQHandler [WEAK] - LDR R0, =ETHERNET_MACLP_DriverIRQHandler - BX R0 - ENDP - -EEPROM_IRQHandler\ - PROC - EXPORT EEPROM_IRQHandler [WEAK] - LDR R0, =EEPROM_DriverIRQHandler - BX R0 - ENDP - -LCD_IRQHandler\ - PROC - EXPORT LCD_IRQHandler [WEAK] - LDR R0, =LCD_DriverIRQHandler - BX R0 - ENDP - -SHA_IRQHandler\ - PROC - EXPORT SHA_IRQHandler [WEAK] - LDR R0, =SHA_DriverIRQHandler - BX R0 - ENDP - -SMARTCARD0_IRQHandler\ - PROC - EXPORT SMARTCARD0_IRQHandler [WEAK] - LDR R0, =SMARTCARD0_DriverIRQHandler - BX R0 - ENDP - -SMARTCARD1_IRQHandler\ - PROC - EXPORT SMARTCARD1_IRQHandler [WEAK] - LDR R0, =SMARTCARD1_DriverIRQHandler - BX R0 - ENDP - -Default_Handler PROC - EXPORT WDT_BOD_DriverIRQHandler [WEAK] - EXPORT DMA0_DriverIRQHandler [WEAK] - EXPORT GINT0_DriverIRQHandler [WEAK] - EXPORT GINT1_DriverIRQHandler [WEAK] - EXPORT PIN_INT0_DriverIRQHandler [WEAK] - EXPORT PIN_INT1_DriverIRQHandler [WEAK] - EXPORT PIN_INT2_DriverIRQHandler [WEAK] - EXPORT PIN_INT3_DriverIRQHandler [WEAK] - EXPORT UTICK0_DriverIRQHandler [WEAK] - EXPORT MRT0_DriverIRQHandler [WEAK] - EXPORT CTIMER0_DriverIRQHandler [WEAK] - EXPORT CTIMER1_DriverIRQHandler [WEAK] - EXPORT SCT0_DriverIRQHandler [WEAK] - EXPORT CTIMER3_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM0_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM1_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM2_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM3_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM4_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM5_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM6_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM7_DriverIRQHandler [WEAK] - EXPORT ADC0_SEQA_DriverIRQHandler [WEAK] - EXPORT ADC0_SEQB_DriverIRQHandler [WEAK] - EXPORT ADC0_THCMP_DriverIRQHandler [WEAK] - EXPORT DMIC0_DriverIRQHandler [WEAK] - EXPORT HWVAD0_DriverIRQHandler [WEAK] - EXPORT USB0_NEEDCLK_DriverIRQHandler [WEAK] - EXPORT USB0_DriverIRQHandler [WEAK] - EXPORT RTC_DriverIRQHandler [WEAK] - EXPORT Reserved46_DriverIRQHandler [WEAK] - EXPORT Reserved47_DriverIRQHandler [WEAK] - EXPORT PIN_INT4_DriverIRQHandler [WEAK] - EXPORT PIN_INT5_DriverIRQHandler [WEAK] - EXPORT PIN_INT6_DriverIRQHandler [WEAK] - EXPORT PIN_INT7_DriverIRQHandler [WEAK] - EXPORT CTIMER2_DriverIRQHandler [WEAK] - EXPORT CTIMER4_DriverIRQHandler [WEAK] - EXPORT RIT_DriverIRQHandler [WEAK] - EXPORT SPIFI0_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM8_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM9_DriverIRQHandler [WEAK] - EXPORT SDIO_DriverIRQHandler [WEAK] - EXPORT CAN0_IRQ0_DriverIRQHandler [WEAK] - EXPORT CAN0_IRQ1_DriverIRQHandler [WEAK] - EXPORT CAN1_IRQ0_DriverIRQHandler [WEAK] - EXPORT CAN1_IRQ1_DriverIRQHandler [WEAK] - EXPORT USB1_DriverIRQHandler [WEAK] - EXPORT USB1_NEEDCLK_DriverIRQHandler [WEAK] - EXPORT ETHERNET_DriverIRQHandler [WEAK] - EXPORT ETHERNET_PMT_DriverIRQHandler [WEAK] - EXPORT ETHERNET_MACLP_DriverIRQHandler [WEAK] - EXPORT EEPROM_DriverIRQHandler [WEAK] - EXPORT LCD_DriverIRQHandler [WEAK] - EXPORT SHA_DriverIRQHandler [WEAK] - EXPORT SMARTCARD0_DriverIRQHandler [WEAK] - EXPORT SMARTCARD1_DriverIRQHandler [WEAK] - -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_SEQA_DriverIRQHandler -ADC0_SEQB_DriverIRQHandler -ADC0_THCMP_DriverIRQHandler -DMIC0_DriverIRQHandler -HWVAD0_DriverIRQHandler -USB0_NEEDCLK_DriverIRQHandler -USB0_DriverIRQHandler -RTC_DriverIRQHandler -Reserved46_DriverIRQHandler -Reserved47_DriverIRQHandler -PIN_INT4_DriverIRQHandler -PIN_INT5_DriverIRQHandler -PIN_INT6_DriverIRQHandler -PIN_INT7_DriverIRQHandler -CTIMER2_DriverIRQHandler -CTIMER4_DriverIRQHandler -RIT_DriverIRQHandler -SPIFI0_DriverIRQHandler -FLEXCOMM8_DriverIRQHandler -FLEXCOMM9_DriverIRQHandler -SDIO_DriverIRQHandler -CAN0_IRQ0_DriverIRQHandler -CAN0_IRQ1_DriverIRQHandler -CAN1_IRQ0_DriverIRQHandler -CAN1_IRQ1_DriverIRQHandler -USB1_DriverIRQHandler -USB1_NEEDCLK_DriverIRQHandler -ETHERNET_DriverIRQHandler -ETHERNET_PMT_DriverIRQHandler -ETHERNET_MACLP_DriverIRQHandler -EEPROM_DriverIRQHandler -LCD_DriverIRQHandler -SHA_DriverIRQHandler -SMARTCARD0_DriverIRQHandler -SMARTCARD1_DriverIRQHandler - - B . - - ENDP - - - ALIGN - - - END - diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/cmsis_drivers/fsl_i2c_cmsis.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/cmsis_drivers/fsl_i2c_cmsis.c deleted file mode 100644 index d727c2a22d8..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/cmsis_drivers/fsl_i2c_cmsis.c +++ /dev/null @@ -1,2091 +0,0 @@ -/* - * Copyright (c) 2013-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_i2c_cmsis.h" - -#if (RTE_I2C0 || RTE_I2C1 || RTE_I2C2 || RTE_I2C3 || RTE_I2C4 || RTE_I2C5 || RTE_I2C6 || RTE_I2C7 || RTE_I2C8 || \ - RTE_I2C9) - -#define ARM_I2C_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) - -/* - * ARMCC does not support split the data section automatically, so the driver - * needs to split the data to separate sections explicitly, to reduce codesize. - */ -#if defined(__CC_ARM) -#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) -#endif - -typedef const struct _cmsis_i2c_resource -{ - I2C_Type *base; /*!< I2C peripheral base address. */ - uint32_t (*GetFreq)(void); /*!< Function to get the clock frequency. */ - -} cmsis_i2c_resource_t; - -typedef union _cmsis_i2c_handle -{ - i2c_master_handle_t master_handle; /*!< master Interupt transfer handle. */ - i2c_slave_handle_t slave_handle; /*!< slave Interupt transfer handle. */ -} cmsis_i2c_handle_t; - -typedef struct _cmsis_i2c_interrupt_driver_state -{ - cmsis_i2c_resource_t *resource; /*!< Basic I2C resource. */ - cmsis_i2c_handle_t *handle; - ARM_I2C_SignalEvent_t cb_event; /*!< Callback function. */ - bool isInitialized; /*!< Is initialized or not. */ -} cmsis_i2c_interrupt_driver_state_t; -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) -typedef const struct _cmsis_i2c_dma_resource -{ - DMA_Type *i2cDmaBase; /*!< DMA peripheral base address for i2c. */ - uint32_t i2cDmaChannel; /*!< DMA channel for i2c. */ -} cmsis_i2c_dma_resource_t; - -typedef struct _cmsis_i2c_dma_driver_state -{ - cmsis_i2c_resource_t *resource; /*!< i2c basic resource. */ - cmsis_i2c_dma_resource_t *dmaResource; /*!< i2c DMA resource. */ - i2c_master_dma_handle_t *master_dma_handle; /*!< i2c DMA transfer handle. */ - dma_handle_t *dmaHandle; /*!< DMA i2c handle. */ - bool isInitialized; /*!< Is initialized or not. */ -} cmsis_i2c_dma_driver_state_t; -#endif - -static const ARM_DRIVER_VERSION s_i2cDriverVersion = {ARM_I2C_API_VERSION, ARM_I2C_DRV_VERSION}; - -static const ARM_I2C_CAPABILITIES s_i2cDriverCapabilities = { - 0, /*< supports 10-bit addressing*/ -}; - -extern uint32_t I2C_GetInstance(I2C_Type *base); - -static ARM_DRIVER_VERSION I2Cx_GetVersion(void) -{ - return s_i2cDriverVersion; -} - -static ARM_I2C_CAPABILITIES I2Cx_GetCapabilities(void) -{ - return s_i2cDriverCapabilities; -} - -#endif - -#if (RTE_I2C0_DMA_EN || RTE_I2C1_DMA_EN || RTE_I2C2_DMA_EN || RTE_I2C3_DMA_EN || RTE_I2C4_DMA_EN || RTE_I2C5_DMA_EN || \ - RTE_I2C6_DMA_EN || RTE_I2C7_DMA_EN || RTE_I2C8_DMA_EN || RTE_I2C9_DMA_EN) - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) -void KSDK_I2C_MASTER_DmaCallback(I2C_Type *base, i2c_master_dma_handle_t *handle, status_t status, void *userData) -{ - uint32_t event; - - if (status == kStatus_Success) /* Occurs after Master Transmit/Receive operation has finished. */ - { - event = ARM_I2C_EVENT_TRANSFER_DONE; - } - - if (userData) - { - ((ARM_I2C_SignalEvent_t)userData)(event); - } -} -static int32_t I2C_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event, cmsis_i2c_dma_driver_state_t *i2c) -{ - if (!(i2c->isInitialized)) - { - DMA_EnableChannel(i2c->dmaResource->i2cDmaBase, i2c->dmaResource->i2cDmaChannel); - DMA_CreateHandle(i2c->dmaHandle, i2c->dmaResource->i2cDmaBase, i2c->dmaResource->i2cDmaChannel); - - I2C_MasterTransferCreateHandleDMA(i2c->resource->base, i2c->master_dma_handle, KSDK_I2C_MASTER_DmaCallback, - (void *)cb_event, i2c->dmaHandle); - i2c->isInitialized = true; - } - return ARM_DRIVER_OK; -} -int32_t I2C_Master_DmaUninitialize(cmsis_i2c_dma_driver_state_t *i2c) -{ - return ARM_DRIVER_OK; -} -int32_t I2C_Master_DmaTransmit( - uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_dma_driver_state_t *i2c) -{ - int32_t status; - int32_t ret; - i2c_master_transfer_t masterXfer; - - /* Check if the I2C bus is idle - if not return busy status. */ - if (i2c->master_dma_handle->state != 0) - { - return ARM_DRIVER_ERROR_BUSY; - } - - masterXfer.slaveAddress = addr; /*7-bit slave address.*/ - masterXfer.direction = kI2C_Write; /*Transfer direction.*/ - masterXfer.subaddress = 0; /*Sub address*/ - masterXfer.subaddressSize = 0; /*Size of command buffer.*/ - masterXfer.data = (uint8_t *)data; /*Transfer buffer.*/ - masterXfer.dataSize = num; /*Transfer size.*/ - masterXfer.flags = kI2C_TransferDefaultFlag; /*Transfer flag which controls the transfer.*/ - - if (xfer_pending) - { - masterXfer.flags |= kI2C_TransferNoStopFlag; - } - - status = I2C_MasterTransferDMA(i2c->resource->base, i2c->master_dma_handle, &masterXfer); - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_I2C_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} -int32_t I2C_Master_DmaReceive( - uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_dma_driver_state_t *i2c) -{ - int32_t status; - int32_t ret; - i2c_master_transfer_t masterXfer; - - /* Check if the I2C bus is idle - if not return busy status. */ - if (i2c->master_dma_handle->state != 0) - { - return ARM_DRIVER_ERROR_BUSY; - } - - masterXfer.slaveAddress = addr; /*7-bit slave address.*/ - masterXfer.direction = kI2C_Read; /*Transfer direction.*/ - masterXfer.subaddress = 0; /*Sub address*/ - masterXfer.subaddressSize = 0; /*Size of command buffer.*/ - masterXfer.data = data; /*Transfer buffer.*/ - masterXfer.dataSize = num; /*Transfer size.*/ - masterXfer.flags = kI2C_TransferDefaultFlag; /*Transfer flag which controls the transfer.*/ - - if (xfer_pending) - { - masterXfer.flags |= kI2C_TransferNoStopFlag; - } - - status = I2C_MasterTransferDMA(i2c->resource->base, i2c->master_dma_handle, &masterXfer); - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_I2C_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} -int32_t I2C_Master_DmaGetDataCount(cmsis_i2c_dma_driver_state_t *i2c) -{ - size_t cnt; /*the number of currently transferred data bytes*/ - - I2C_MasterTransferGetCountDMA(i2c->resource->base, i2c->master_dma_handle, &cnt); - return cnt; -} -int32_t I2C_Master_DmaControl(uint32_t control, uint32_t arg, cmsis_i2c_dma_driver_state_t *i2c) -{ - uint32_t baudRate_Bps; - - switch (control) - { - /* Not supported */ - case ARM_I2C_OWN_ADDRESS: - return ARM_DRIVER_ERROR_UNSUPPORTED; - /*Set Bus Speed; arg = bus speed*/ - case ARM_I2C_BUS_SPEED: - switch (arg) - { - case ARM_I2C_BUS_SPEED_STANDARD: - baudRate_Bps = 100000; - break; - case ARM_I2C_BUS_SPEED_FAST: - baudRate_Bps = 400000; - break; - case ARM_I2C_BUS_SPEED_FAST_PLUS: - baudRate_Bps = 1000000; - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - I2C_MasterSetBaudRate(i2c->resource->base, baudRate_Bps, i2c->resource->GetFreq()); - return ARM_DRIVER_OK; - /* Not supported */ - case ARM_I2C_BUS_CLEAR: - return ARM_DRIVER_ERROR_UNSUPPORTED; - /*Aborts the data transfer when Master for Transmit or Receive*/ - case ARM_I2C_ABORT_TRANSFER: - /*disable dma*/ - I2C_MasterTransferAbortDMA(i2c->resource->base, i2c->master_dma_handle); - - i2c->master_dma_handle->transferCount = 0; - i2c->master_dma_handle->transfer.data = NULL; - i2c->master_dma_handle->transfer.dataSize = 0; - return ARM_DRIVER_OK; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} -int32_t I2C_Master_DmaPowerControl(ARM_POWER_STATE state, cmsis_i2c_dma_driver_state_t *i2c) -{ - switch (state) - { - /*terminates any pending data transfers, disable i2c moduole and i2c clock and related dma*/ - case ARM_POWER_OFF: - I2C_Master_DmaControl(ARM_I2C_ABORT_TRANSFER, 0, i2c); - I2C_MasterDeinit(i2c->resource->base); - DMA_DisableChannel(i2c->dmaResource->i2cDmaBase, i2c->dmaResource->i2cDmaChannel); - - return ARM_DRIVER_OK; - /* Not supported */ - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - /*enable i2c moduole and i2c clock*/ - case ARM_POWER_FULL: - FLEXCOMM_Init(i2c->resource->base, FLEXCOMM_PERIPH_I2C); - I2C_MasterEnable(i2c->resource->base, true); - - return ARM_DRIVER_OK; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} -ARM_I2C_STATUS I2C_Master_DmaGetStatus(cmsis_i2c_dma_driver_state_t *i2c) -{ - ARM_I2C_STATUS stat; - uint32_t ksdk_i2c_status = I2C_GetStatusFlags(i2c->resource->base); - - stat.busy = !(ksdk_i2c_status & I2C_STAT_MSTPENDING_MASK); /*Busy flag.*/ - stat.direction = i2c->master_dma_handle->transfer.direction; /*Direction: 0=Transmitter, 1=Receiver.*/ - stat.mode = 1; /*Mode: 0=Slave, 1=Master.*/ - stat.arbitration_lost = !(!(ksdk_i2c_status & I2C_STAT_MSTARBLOSS_MASK)); - /*Master lost arbitration (cleared on start of next Master operation)*/ - - return stat; -} -#endif - -#endif - -#if ((RTE_I2C0 && !RTE_I2C0_DMA_EN) || (RTE_I2C1 && !RTE_I2C1_DMA_EN) || (RTE_I2C2 && !RTE_I2C2_DMA_EN) || \ - (RTE_I2C3 && !RTE_I2C3_DMA_EN) || (RTE_I2C4 && !RTE_I2C4_DMA_EN) || (RTE_I2C5 && !RTE_I2C5_DMA_EN) || \ - (RTE_I2C6 && !RTE_I2C6_DMA_EN) || (RTE_I2C7 && !RTE_I2C7_DMA_EN) || (RTE_I2C8 && !RTE_I2C8_DMA_EN) || \ - (RTE_I2C9 && !RTE_I2C9_DMA_EN)) - -static void KSDK_I2C_SLAVE_InterruptCallback(I2C_Type *base, volatile i2c_slave_transfer_t *xfer, void *param) -{ - uint32_t event; - - switch (xfer->event) - { - case kI2C_SlaveCompletionEvent: /* Occurs after Slave Transmit/Receive operation has finished. */ - event = ARM_I2C_EVENT_TRANSFER_DONE; - break; - default: - event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE; - break; - } - - if (param) - { - ((ARM_I2C_SignalEvent_t)param)(event); - } -} - -static void KSDK_I2C_MASTER_InterruptCallback(I2C_Type *base, - i2c_master_handle_t *handle, - status_t status, - void *userData) -{ - uint32_t event; - - switch (status) - { - case kStatus_Success: /* Occurs after Master Transmit/Receive operation has finished. */ - event = ARM_I2C_EVENT_TRANSFER_DONE; - break; - case kStatus_I2C_ArbitrationLost: /*Occurs in master mode when arbitration is lost.*/ - event = ARM_I2C_EVENT_ARBITRATION_LOST; - break; - default: - event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE; - break; - } - - /* User data is actually CMSIS driver callback. */ - if (userData) - { - ((ARM_I2C_SignalEvent_t)userData)(event); - } -} - -static int32_t I2C_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event, cmsis_i2c_interrupt_driver_state_t *i2c) -{ - i2c->cb_event = cb_event; /* cb_event is CMSIS driver callback. */ - return ARM_DRIVER_OK; -} - -static int32_t I2C_InterruptUninitialize(cmsis_i2c_interrupt_driver_state_t *i2c) -{ - return ARM_DRIVER_OK; -} - -int32_t I2C_Master_InterruptTransmit( - uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_interrupt_driver_state_t *i2c) -{ - int32_t status; - int32_t ret; - i2c_master_transfer_t masterXfer; - - /* Check if the I2C bus is idle - if not return busy status. */ - if (i2c->handle->master_handle.state != 0) - { - return ARM_DRIVER_ERROR_BUSY; - } - - I2C_MasterEnable(i2c->resource->base, true); - - /*create master_handle*/ - I2C_MasterTransferCreateHandle(i2c->resource->base, &(i2c->handle->master_handle), - KSDK_I2C_MASTER_InterruptCallback, (void *)i2c->cb_event); - - masterXfer.slaveAddress = addr; /*7-bit slave address.*/ - masterXfer.direction = kI2C_Write; /*Transfer direction.*/ - masterXfer.subaddress = (uint32_t)NULL; /*Sub address*/ - masterXfer.subaddressSize = 0; /*Size of command buffer.*/ - masterXfer.data = (uint8_t *)data; /*Transfer buffer.*/ - masterXfer.dataSize = num; /*Transfer size.*/ - masterXfer.flags = kI2C_TransferDefaultFlag; /*Transfer flag which controls the transfer.*/ - - if (xfer_pending) - { - masterXfer.flags |= kI2C_TransferNoStopFlag; - } - - status = I2C_MasterTransferNonBlocking(i2c->resource->base, &(i2c->handle->master_handle), &masterXfer); - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_I2C_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -int32_t I2C_Master_InterruptReceive( - uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_interrupt_driver_state_t *i2c) -{ - int32_t status; - int32_t ret; - i2c_master_transfer_t masterXfer; - - /* Check if the I2C bus is idle - if not return busy status. */ - if (i2c->handle->master_handle.state != 0) - { - return ARM_DRIVER_ERROR_BUSY; - } - - I2C_MasterEnable(i2c->resource->base, true); - - /*create master_handle*/ - I2C_MasterTransferCreateHandle(i2c->resource->base, &(i2c->handle->master_handle), - KSDK_I2C_MASTER_InterruptCallback, (void *)i2c->cb_event); - - masterXfer.slaveAddress = addr; /*7-bit slave address.*/ - masterXfer.direction = kI2C_Read; /*Transfer direction.*/ - masterXfer.subaddress = (uint32_t)NULL; /*Sub address*/ - masterXfer.subaddressSize = 0; /*Size of command buffer.*/ - masterXfer.data = data; /*Transfer buffer.*/ - masterXfer.dataSize = num; /*Transfer size.*/ - masterXfer.flags = kI2C_TransferDefaultFlag; /*Transfer flag which controls the transfer.*/ - - if (xfer_pending) - { - masterXfer.flags |= kI2C_TransferNoStopFlag; - } - - status = I2C_MasterTransferNonBlocking(i2c->resource->base, &(i2c->handle->master_handle), &masterXfer); - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_I2C_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -int32_t I2C_Slave_InterruptTransmit(const uint8_t *data, uint32_t num, cmsis_i2c_interrupt_driver_state_t *i2c) -{ - int32_t status; - int32_t ret; - - /* set Slave enable */ - I2C_SlaveEnable(i2c->resource->base, true); - - /*create slave_handle*/ - I2C_SlaveTransferCreateHandle(i2c->resource->base, &(i2c->handle->slave_handle), KSDK_I2C_SLAVE_InterruptCallback, - (void *)i2c->cb_event); - - status = I2C_SlaveTransferNonBlocking(i2c->resource->base, &(i2c->handle->slave_handle), kI2C_SlaveCompletionEvent); - - i2c->handle->slave_handle.transfer.txData = - (uint8_t *)data; /*Pointer to buffer with data to transmit to I2C Master*/ - i2c->handle->slave_handle.transfer.txSize = num; /*Number of data bytes to transmit*/ - i2c->handle->slave_handle.transfer.transferredCount = - 0; /*Number of bytes actually transferred since start or last repeated start. */ - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_I2C_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} -int32_t I2C_Slave_InterruptReceive(uint8_t *data, uint32_t num, cmsis_i2c_interrupt_driver_state_t *i2c) -{ - int32_t status; - int32_t ret; - - /* set Slave enable */ - I2C_SlaveEnable(i2c->resource->base, true); - - /*create slave_handle*/ - I2C_SlaveTransferCreateHandle(i2c->resource->base, &(i2c->handle->slave_handle), KSDK_I2C_SLAVE_InterruptCallback, - (void *)i2c->cb_event); - - status = I2C_SlaveTransferNonBlocking(i2c->resource->base, &(i2c->handle->slave_handle), kI2C_SlaveCompletionEvent); - - i2c->handle->slave_handle.transfer.rxData = data; /*Pointer to buffer with data to transmit to I2C Master*/ - i2c->handle->slave_handle.transfer.rxSize = num; /*Number of data bytes to transmit*/ - i2c->handle->slave_handle.transfer.transferredCount = - 0; /*Number of bytes actually transferred since start or last repeated start. */ - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_I2C_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} -int32_t I2C_InterruptGetDataCount(cmsis_i2c_interrupt_driver_state_t *i2c) -{ - uint32_t cnt = 0; /*the number of currently transferred data bytes*/ - - if (i2c->resource->base->CFG & I2C_CFG_MSTEN_MASK) - { - cnt = i2c->handle->master_handle.transferCount; - } - else - { - cnt = i2c->handle->slave_handle.transfer.transferredCount; - } - - return cnt; -} - -int32_t I2C_InterruptControl(uint32_t control, uint32_t arg, cmsis_i2c_interrupt_driver_state_t *i2c) -{ - uint32_t baudRate_Bps; - - switch (control) - { - /*Set Own Slave Address; arg = slave address*/ - case ARM_I2C_OWN_ADDRESS: - I2C_SlaveSetAddress(i2c->resource->base, kI2C_SlaveAddressRegister0, arg, false); - /* set Slave address 0 qual */ - i2c->resource->base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(0) | I2C_SLVQUAL0_SLVQUAL0(0); - return ARM_DRIVER_OK; - /*Set Bus Speed; arg = bus speed*/ - case ARM_I2C_BUS_SPEED: - switch (arg) - { - case ARM_I2C_BUS_SPEED_STANDARD: - baudRate_Bps = 100000; - break; - case ARM_I2C_BUS_SPEED_FAST: - baudRate_Bps = 400000; - break; - case ARM_I2C_BUS_SPEED_FAST_PLUS: - baudRate_Bps = 1000000; - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - I2C_MasterSetBaudRate(i2c->resource->base, baudRate_Bps, i2c->resource->GetFreq()); - return ARM_DRIVER_OK; - // Not supported - case ARM_I2C_BUS_CLEAR: - return ARM_DRIVER_ERROR_UNSUPPORTED; - /*Aborts the data transfer between Master and Slave for Transmit or Receive*/ - case ARM_I2C_ABORT_TRANSFER: - if (i2c->resource->base->CFG & I2C_CFG_MSTEN_MASK) - { - /*disable master interrupt and send STOP signal*/ - I2C_MasterTransferAbort(i2c->resource->base, &(i2c->handle->master_handle)); - - i2c->handle->master_handle.transferCount = 0; - i2c->handle->master_handle.transfer.data = NULL; - i2c->handle->master_handle.transfer.dataSize = 0; - } - /*if slave receive*/ - if ((i2c->resource->base->CFG & I2C_CFG_SLVEN_MASK) && - ((i2c->handle->slave_handle.slaveFsm) == kI2C_SlaveFsmReceive)) - { - /*disable slave interrupt*/ - I2C_SlaveTransferAbort(i2c->resource->base, &(i2c->handle->slave_handle)); - - i2c->handle->slave_handle.transfer.transferredCount = 0; - i2c->handle->slave_handle.transfer.txData = NULL; - i2c->handle->slave_handle.transfer.rxData = NULL; - } - return ARM_DRIVER_OK; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} -static int32_t I2C_InterruptPowerControl(ARM_POWER_STATE state, cmsis_i2c_interrupt_driver_state_t *i2c) -{ - switch (state) - { - /*terminates any pending data transfers, disable i2c moduole and i2c clock*/ - case ARM_POWER_OFF: - - I2C_InterruptControl(ARM_I2C_ABORT_TRANSFER, 0, i2c); - - I2C_MasterDeinit(i2c->resource->base); - I2C_SlaveDeinit(i2c->resource->base); - - return ARM_DRIVER_OK; - /* Not supported */ - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - /*enable i2c moduole and i2c clock*/ - case ARM_POWER_FULL: - - FLEXCOMM_Init(i2c->resource->base, FLEXCOMM_PERIPH_I2C); - - return ARM_DRIVER_OK; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} -ARM_I2C_STATUS I2C_InterruptGetStatus(cmsis_i2c_interrupt_driver_state_t *i2c) -{ - ARM_I2C_STATUS stat; - uint32_t ksdk_i2c_status = I2C_GetStatusFlags(i2c->resource->base); - - if (i2c->resource->base->CFG & I2C_CFG_MSTEN_MASK) - { - stat.busy = !(ksdk_i2c_status & I2C_STAT_MSTPENDING_MASK); /*Busy flag.*/ - stat.direction = i2c->handle->master_handle.transfer.direction; /*Direction: 0=Transmitter, 1=Receiver.*/ - stat.mode = 1; /*Mode: 0=Slave, 1=Master.*/ - stat.arbitration_lost = !(!(ksdk_i2c_status & I2C_STAT_MSTARBLOSS_MASK)); - /*Master lost arbitration (cleared on start of next Master operation)*/ - } - - if (i2c->resource->base->CFG & I2C_CFG_SLVEN_MASK) - { - stat.busy = !(ksdk_i2c_status & I2C_STAT_SLVPENDING_MASK); /*Busy flag.*/ - if ((i2c->handle->slave_handle.slaveFsm) == kI2C_SlaveFsmReceive) - { - stat.direction = 1; /*Direction: 0=Transmitter, 1=Receiver.*/ - } - else - { - stat.direction = 0; /*Direction: 0=Transmitter, 1=Receiver.*/ - } - stat.mode = 0; /*Mode: 0=Slave, 1=Master.*/ - } - - return stat; -} - -#endif - -#if defined(I2C0) && RTE_I2C0 -/* User needs to provide the implementation for I2C0_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t I2C0_GetFreq(void); -extern void I2C0_InitPins(void); -extern void I2C0_DeinitPins(void); - -cmsis_i2c_resource_t I2C0_Resource = {I2C0, I2C0_GetFreq}; - -#if RTE_I2C0_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C0_DmaResource = {RTE_I2C0_Master_DMA_BASE, RTE_I2C0_Master_DMA_CH}; - -i2c_master_dma_handle_t I2C0_DmaHandle; -dma_handle_t I2C0_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c0_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C0_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C0_DmaDriverState = { -#endif - &I2C0_Resource, &I2C0_DmaResource, &I2C0_DmaHandle, &I2C0_DmaTxRxHandle, -}; - -static int32_t I2C0_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C0_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C0_DmaDriverState); -} -int32_t I2C0_Master_DmaUninitialize(void) -{ - I2C0_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C0_DmaDriverState); -} -int32_t I2C0_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C0_DmaDriverState); -} -int32_t I2C0_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C0_DmaDriverState); -} -int32_t I2C0_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C0_DmaDriverState); -} -int32_t I2C0_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C0_DmaDriverState); -} -int32_t I2C0_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C0_DmaDriverState); -} -ARM_I2C_STATUS I2C0_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C0_DmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C0_handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c0_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C0_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C0_InterruptDriverState = { -#endif - &I2C0_Resource, &I2C0_handle, - -}; - -static int32_t I2C0_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C0_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C0_InterruptDriverState); -} -static int32_t I2C0_InterruptUninitialize(void) -{ - I2C0_DeinitPins(); - return I2C_InterruptUninitialize(&I2C0_InterruptDriverState); -} -static int32_t I2C0_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C0_InterruptDriverState); -} -int32_t I2C0_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C0_InterruptDriverState); -} - -int32_t I2C0_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C0_InterruptDriverState); -} - -int32_t I2C0_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C0_InterruptDriverState); -} -int32_t I2C0_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C0_InterruptDriverState); -} -int32_t I2C0_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C0_InterruptDriverState); -} -int32_t I2C0_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C0_InterruptDriverState); -} -ARM_I2C_STATUS I2C0_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C0_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C0 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C0_DMA_EN - I2C0_Master_DmaInitialize, I2C0_Master_DmaUninitialize, I2C0_Master_DmaPowerControl, - I2C0_Master_DmaTransmit, I2C0_Master_DmaReceive, NULL, NULL, I2C0_Master_DmaGetDataCount, - I2C0_Master_DmaControl, I2C0_Master_DmaGetStatus -#else - I2C0_InterruptInitialize, I2C0_InterruptUninitialize, I2C0_InterruptPowerControl, - I2C0_Master_InterruptTransmit, I2C0_Master_InterruptReceive, I2C0_Slave_InterruptTransmit, - I2C0_Slave_InterruptReceive, I2C0_InterruptGetDataCount, I2C0_InterruptControl, - I2C0_InterruptGetStatus -#endif -}; - -#endif - -#if defined(I2C1) && RTE_I2C1 - -/* User needs to provide the implementation for I2C1_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t I2C1_GetFreq(void); -extern void I2C1_InitPins(void); -extern void I2C1_DeinitPins(void); - -cmsis_i2c_resource_t I2C1_Resource = {I2C1, I2C1_GetFreq}; - -#if RTE_I2C1_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C1_DmaResource = {RTE_I2C1_Master_DMA_BASE, RTE_I2C1_Master_DMA_CH}; - -i2c_master_dma_handle_t I2C1_DmaHandle; -dma_handle_t I2C1_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c1_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C1_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C1_DmaDriverState = { -#endif - &I2C1_Resource, &I2C1_DmaResource, &I2C1_DmaHandle, &I2C1_DmaTxRxHandle, -}; - -static int32_t I2C1_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C1_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C1_DmaDriverState); -} -int32_t I2C1_Master_DmaUninitialize(void) -{ - I2C1_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C1_DmaDriverState); -} -int32_t I2C1_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C1_DmaDriverState); -} -int32_t I2C1_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C1_DmaDriverState); -} -int32_t I2C1_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C1_DmaDriverState); -} -int32_t I2C1_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C1_DmaDriverState); -} -int32_t I2C1_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C1_DmaDriverState); -} -ARM_I2C_STATUS I2C1_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C1_DmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C1_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c1_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C1_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C1_InterruptDriverState = { -#endif - &I2C1_Resource, &I2C1_Handle, -}; - -static int32_t I2C1_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C1_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C1_InterruptDriverState); -} -static int32_t I2C1_InterruptUninitialize(void) -{ - I2C1_DeinitPins(); - return I2C_InterruptUninitialize(&I2C1_InterruptDriverState); -} -static int32_t I2C1_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C1_InterruptDriverState); -} -int32_t I2C1_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C1_InterruptDriverState); -} - -int32_t I2C1_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C1_InterruptDriverState); -} - -int32_t I2C1_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C1_InterruptDriverState); -} -int32_t I2C1_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C1_InterruptDriverState); -} -int32_t I2C1_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C1_InterruptDriverState); -} -int32_t I2C1_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C1_InterruptDriverState); -} -ARM_I2C_STATUS I2C1_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C1_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C1 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C1_DMA_EN - I2C1_Master_DmaInitialize, I2C1_Master_DmaUninitialize, I2C1_Master_DmaPowerControl, - I2C1_Master_DmaTransmit, I2C1_Master_DmaReceive, NULL, NULL, I2C1_Master_DmaGetDataCount, - I2C1_Master_DmaControl, I2C1_Master_DmaGetStatus -#else - I2C1_InterruptInitialize, I2C1_InterruptUninitialize, I2C1_InterruptPowerControl, - I2C1_Master_InterruptTransmit, I2C1_Master_InterruptReceive, I2C1_Slave_InterruptTransmit, - I2C1_Slave_InterruptReceive, I2C1_InterruptGetDataCount, I2C1_InterruptControl, - I2C1_InterruptGetStatus -#endif -}; - -#endif - -#if defined(I2C2) && RTE_I2C2 - -/* User needs to provide the implementation for I2C2_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t I2C2_GetFreq(void); -extern void I2C2_InitPins(void); -extern void I2C2_DeinitPins(void); - -cmsis_i2c_resource_t I2C2_Resource = {I2C2, I2C2_GetFreq}; - -#if RTE_I2C2_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C2_DmaResource = {RTE_I2C2_Master_DMA_BASE, RTE_I2C2_Master_DMA_CH}; - -i2c_master_dma_handle_t I2C2_DmaHandle; -dma_handle_t I2C2_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c2_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C2_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C2_DmaDriverState = { -#endif - &I2C2_Resource, &I2C2_DmaResource, &I2C2_DmaHandle, &I2C2_DmaTxRxHandle, -}; - -static int32_t I2C2_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C2_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C2_DmaDriverState); -} -int32_t I2C2_Master_DmaUninitialize(void) -{ - I2C2_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C2_DmaDriverState); -} -int32_t I2C2_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C2_DmaDriverState); -} -int32_t I2C2_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C2_DmaDriverState); -} -int32_t I2C2_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C2_DmaDriverState); -} -int32_t I2C2_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C2_DmaDriverState); -} -int32_t I2C2_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C2_DmaDriverState); -} -ARM_I2C_STATUS I2C2_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C2_DmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C2_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c2_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C2_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C2_InterruptDriverState = { -#endif - &I2C2_Resource, &I2C2_Handle, - -}; - -static int32_t I2C2_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C2_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C2_InterruptDriverState); -} -static int32_t I2C2_InterruptUninitialize(void) -{ - I2C2_DeinitPins(); - return I2C_InterruptUninitialize(&I2C2_InterruptDriverState); -} -static int32_t I2C2_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C2_InterruptDriverState); -} -int32_t I2C2_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C2_InterruptDriverState); -} - -int32_t I2C2_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C2_InterruptDriverState); -} - -int32_t I2C2_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C2_InterruptDriverState); -} -int32_t I2C2_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C2_InterruptDriverState); -} -int32_t I2C2_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C2_InterruptDriverState); -} -int32_t I2C2_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C2_InterruptDriverState); -} -ARM_I2C_STATUS I2C2_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C2_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C2 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C2_DMA_EN - I2C2_Master_DmaInitialize, I2C2_Master_DmaUninitialize, I2C2_Master_DmaPowerControl, - I2C2_Master_DmaTransmit, I2C2_Master_DmaReceive, NULL, NULL, I2C2_Master_DmaGetDataCount, - I2C2_Master_DmaControl, I2C2_Master_DmaGetStatus -#else - I2C2_InterruptInitialize, I2C2_InterruptUninitialize, I2C2_InterruptPowerControl, - I2C2_Master_InterruptTransmit, I2C2_Master_InterruptReceive, I2C2_Slave_InterruptTransmit, - I2C2_Slave_InterruptReceive, I2C2_InterruptGetDataCount, I2C2_InterruptControl, - I2C2_InterruptGetStatus -#endif -}; - -#endif - -#if defined(I2C3) && RTE_I2C3 - -/* User needs to provide the implementation for I2C3_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t I2C3_GetFreq(void); -extern void I2C3_InitPins(void); -extern void I2C3_DeinitPins(void); - -cmsis_i2c_resource_t I2C3_Resource = {I2C3, I2C3_GetFreq}; - -#if RTE_I2C3_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C3_DmaResource = {RTE_I2C3_Master_DMA_BASE, RTE_I2C3_Master_DMA_CH}; - -i2c_master_dma_handle_t I2C3_DmaHandle; -dma_handle_t I2C3_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c3_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C3_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C3_DmaDriverState = { -#endif - &I2C3_Resource, &I2C3_DmaResource, &I2C3_DmaHandle, &I2C3_DmaTxRxHandle, -}; - -static int32_t I2C3_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C3_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C3_DmaDriverState); -} -int32_t I2C3_Master_DmaUninitialize(void) -{ - I2C3_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C3_DmaDriverState); -} -int32_t I2C3_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C3_DmaDriverState); -} -int32_t I2C3_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C3_DmaDriverState); -} -int32_t I2C3_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C3_DmaDriverState); -} -int32_t I2C3_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C3_DmaDriverState); -} -int32_t I2C3_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C3_DmaDriverState); -} -ARM_I2C_STATUS I2C3_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C3_DmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C3_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c3_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C3_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C3_InterruptDriverState = { -#endif - &I2C3_Resource, &I2C3_Handle, -}; - -static int32_t I2C3_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C3_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C3_InterruptDriverState); -} -static int32_t I2C3_InterruptUninitialize(void) -{ - I2C3_DeinitPins(); - return I2C_InterruptUninitialize(&I2C3_InterruptDriverState); -} -static int32_t I2C3_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C3_InterruptDriverState); -} -int32_t I2C3_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C3_InterruptDriverState); -} - -int32_t I2C3_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C3_InterruptDriverState); -} - -int32_t I2C3_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C3_InterruptDriverState); -} -int32_t I2C3_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C3_InterruptDriverState); -} -int32_t I2C3_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C3_InterruptDriverState); -} - -int32_t I2C3_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C3_InterruptDriverState); -} -ARM_I2C_STATUS I2C3_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C3_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C3 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C3_DMA_EN - I2C3_Master_DmaInitialize, I2C3_Master_DmaUninitialize, I2C3_Master_DmaPowerControl, - I2C3_Master_DmaTransmit, I2C3_Master_DmaReceive, NULL, NULL, I2C3_Master_DmaGetDataCount, - I2C3_Master_DmaControl, I2C3_Master_DmaGetStatus -#else - I2C3_InterruptInitialize, I2C3_InterruptUninitialize, I2C3_InterruptPowerControl, - I2C3_Master_InterruptTransmit, I2C3_Master_InterruptReceive, I2C3_Slave_InterruptTransmit, - I2C3_Slave_InterruptReceive, I2C3_InterruptGetDataCount, I2C3_InterruptControl, - I2C3_InterruptGetStatus -#endif -}; - -#endif - -#if defined(I2C4) && RTE_I2C4 -/* User needs to provide the implementation for I2C4_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t I2C4_GetFreq(void); -extern void I2C4_InitPins(void); -extern void I2C4_DeinitPins(void); - -cmsis_i2c_resource_t I2C4_Resource = {I2C4, I2C4_GetFreq}; - -#if RTE_I2C4_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C4_DmaResource = {RTE_I2C4_Master_DMA_BASE, RTE_I2C4_Master_DMA_CH}; - -i2c_master_dma_handle_t I2C4_DmaHandle; -dma_handle_t I2C4_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c4_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C4_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C4_DmaDriverState = { -#endif - &I2C4_Resource, &I2C4_DmaResource, &I2C4_DmaHandle, &I2C4_DmaTxRxHandle, -}; - -static int32_t I2C4_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C4_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C4_DmaDriverState); -} -int32_t I2C4_Master_DmaUninitialize(void) -{ - I2C4_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C4_DmaDriverState); -} -int32_t I2C4_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C4_DmaDriverState); -} -int32_t I2C4_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C4_DmaDriverState); -} -int32_t I2C4_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C4_DmaDriverState); -} -int32_t I2C4_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C4_DmaDriverState); -} -int32_t I2C4_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C4_DmaDriverState); -} -ARM_I2C_STATUS I2C4_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C4_DmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C4_handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c4_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C4_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C4_InterruptDriverState = { -#endif - &I2C4_Resource, &I2C4_handle, - -}; - -static int32_t I2C4_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C4_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C4_InterruptDriverState); -} -static int32_t I2C4_InterruptUninitialize(void) -{ - I2C4_DeinitPins(); - return I2C_InterruptUninitialize(&I2C4_InterruptDriverState); -} -static int32_t I2C4_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C4_InterruptDriverState); -} -int32_t I2C4_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C4_InterruptDriverState); -} - -int32_t I2C4_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C4_InterruptDriverState); -} - -int32_t I2C4_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C4_InterruptDriverState); -} -int32_t I2C4_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C4_InterruptDriverState); -} -int32_t I2C4_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C4_InterruptDriverState); -} -int32_t I2C4_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C4_InterruptDriverState); -} -ARM_I2C_STATUS I2C4_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C4_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C4 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C4_DMA_EN - I2C4_Master_DmaInitialize, I2C4_Master_DmaUninitialize, I2C4_Master_DmaPowerControl, - I2C4_Master_DmaTransmit, I2C4_Master_DmaReceive, NULL, NULL, I2C4_Master_DmaGetDataCount, - I2C4_Master_DmaControl, I2C4_Master_DmaGetStatus -#else - I2C4_InterruptInitialize, I2C4_InterruptUninitialize, I2C4_InterruptPowerControl, - I2C4_Master_InterruptTransmit, I2C4_Master_InterruptReceive, I2C4_Slave_InterruptTransmit, - I2C4_Slave_InterruptReceive, I2C4_InterruptGetDataCount, I2C4_InterruptControl, - I2C4_InterruptGetStatus -#endif -}; - -#endif - -#if defined(I2C5) && RTE_I2C5 -/* User needs to provide the implementation for I2C5_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t I2C5_GetFreq(void); -extern void I2C5_InitPins(void); -extern void I2C5_DeinitPins(void); - -cmsis_i2c_resource_t I2C5_Resource = {I2C5, I2C5_GetFreq}; - -#if RTE_I2C5_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C5_DmaResource = {RTE_I2C5_Master_DMA_BASE, RTE_I2C5_Master_DMA_CH}; - -i2c_master_dma_handle_t I2C5_DmaHandle; -dma_handle_t I2C5_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c5_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C5_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C5_DmaDriverState = { -#endif - &I2C5_Resource, &I2C5_DmaResource, &I2C5_DmaHandle, &I2C5_DmaTxRxHandle, -}; - -static int32_t I2C5_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C5_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C5_DmaDriverState); -} -int32_t I2C5_Master_DmaUninitialize(void) -{ - I2C5_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C5_DmaDriverState); -} -int32_t I2C5_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C5_DmaDriverState); -} -int32_t I2C5_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C5_DmaDriverState); -} -int32_t I2C5_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C5_DmaDriverState); -} -int32_t I2C5_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C5_DmaDriverState); -} -int32_t I2C5_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C5_DmaDriverState); -} -ARM_I2C_STATUS I2C5_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C5_DmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C5_handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c5_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C5_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C5_InterruptDriverState = { -#endif - &I2C5_Resource, &I2C5_handle, - -}; - -static int32_t I2C5_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C5_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C5_InterruptDriverState); -} -static int32_t I2C5_InterruptUninitialize(void) -{ - I2C5_DeinitPins(); - return I2C_InterruptUninitialize(&I2C5_InterruptDriverState); -} -static int32_t I2C5_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C5_InterruptDriverState); -} -int32_t I2C5_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C5_InterruptDriverState); -} - -int32_t I2C5_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C5_InterruptDriverState); -} - -int32_t I2C5_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C5_InterruptDriverState); -} -int32_t I2C5_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C5_InterruptDriverState); -} -int32_t I2C5_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C5_InterruptDriverState); -} -int32_t I2C5_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C5_InterruptDriverState); -} -ARM_I2C_STATUS I2C5_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C5_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C5 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C5_DMA_EN - I2C5_Master_DmaInitialize, I2C5_Master_DmaUninitialize, I2C5_Master_DmaPowerControl, - I2C5_Master_DmaTransmit, I2C5_Master_DmaReceive, NULL, NULL, I2C5_Master_DmaGetDataCount, - I2C5_Master_DmaControl, I2C5_Master_DmaGetStatus -#else - I2C5_InterruptInitialize, I2C5_InterruptUninitialize, I2C5_InterruptPowerControl, - I2C5_Master_InterruptTransmit, I2C5_Master_InterruptReceive, I2C5_Slave_InterruptTransmit, - I2C5_Slave_InterruptReceive, I2C5_InterruptGetDataCount, I2C5_InterruptControl, - I2C5_InterruptGetStatus -#endif -}; - -#endif - -#if defined(I2C6) && RTE_I2C6 -/* User needs to provide the implementation for I2C6_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t I2C6_GetFreq(void); -extern void I2C6_InitPins(void); -extern void I2C6_DeinitPins(void); - -cmsis_i2c_resource_t I2C6_Resource = {I2C6, I2C6_GetFreq}; - -#if RTE_I2C6_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C6_DmaResource = {RTE_I2C6_Master_DMA_BASE, RTE_I2C6_Master_DMA_CH}; - -i2c_master_dma_handle_t I2C6_DmaHandle; -dma_handle_t I2C6_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c6_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C6_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C6_DmaDriverState = { -#endif - &I2C6_Resource, &I2C6_DmaResource, &I2C6_DmaHandle, &I2C6_DmaTxRxHandle, -}; - -static int32_t I2C6_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C6_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C6_DmaDriverState); -} -int32_t I2C6_Master_DmaUninitialize(void) -{ - I2C6_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C6_DmaDriverState); -} -int32_t I2C6_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C6_DmaDriverState); -} -int32_t I2C6_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C6_DmaDriverState); -} -int32_t I2C6_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C6_DmaDriverState); -} -int32_t I2C6_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C6_DmaDriverState); -} -int32_t I2C6_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C6_DmaDriverState); -} -ARM_I2C_STATUS I2C6_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C6_DmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C6_handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c6_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C6_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C6_InterruptDriverState = { -#endif - &I2C6_Resource, &I2C6_handle, - -}; - -static int32_t I2C6_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C6_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C6_InterruptDriverState); -} -static int32_t I2C6_InterruptUninitialize(void) -{ - I2C6_DeinitPins(); - return I2C_InterruptUninitialize(&I2C6_InterruptDriverState); -} -static int32_t I2C6_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C6_InterruptDriverState); -} -int32_t I2C6_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C6_InterruptDriverState); -} - -int32_t I2C6_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C6_InterruptDriverState); -} - -int32_t I2C6_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C6_InterruptDriverState); -} -int32_t I2C6_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C6_InterruptDriverState); -} -int32_t I2C6_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C6_InterruptDriverState); -} -int32_t I2C6_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C6_InterruptDriverState); -} -ARM_I2C_STATUS I2C6_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C6_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C6 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C6_DMA_EN - I2C6_Master_DmaInitialize, I2C6_Master_DmaUninitialize, I2C6_Master_DmaPowerControl, - I2C6_Master_DmaTransmit, I2C6_Master_DmaReceive, NULL, NULL, I2C6_Master_DmaGetDataCount, - I2C6_Master_DmaControl, I2C6_Master_DmaGetStatus -#else - I2C6_InterruptInitialize, I2C6_InterruptUninitialize, I2C6_InterruptPowerControl, - I2C6_Master_InterruptTransmit, I2C6_Master_InterruptReceive, I2C6_Slave_InterruptTransmit, - I2C6_Slave_InterruptReceive, I2C6_InterruptGetDataCount, I2C6_InterruptControl, - I2C6_InterruptGetStatus -#endif -}; - -#endif - -#if defined(I2C7) && RTE_I2C7 -/* User needs to provide the implementation for I2C7_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t I2C7_GetFreq(void); -extern void I2C7_InitPins(void); -extern void I2C7_DeinitPins(void); - -cmsis_i2c_resource_t I2C7_Resource = {I2C7, I2C7_GetFreq}; - -#if RTE_I2C7_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C7_DmaResource = {RTE_I2C7_Master_DMA_BASE, RTE_I2C7_Master_DMA_CH}; - -i2c_master_dma_handle_t I2C7_DmaHandle; -dma_handle_t I2C7_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c7_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C7_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C7_DmaDriverState = { -#endif - &I2C7_Resource, &I2C7_DmaResource, &I2C7_DmaHandle, &I2C7_DmaTxRxHandle, -}; - -static int32_t I2C7_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C7_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C7_DmaDriverState); -} -int32_t I2C7_Master_DmaUninitialize(void) -{ - I2C7_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C7_DmaDriverState); -} -int32_t I2C7_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C7_DmaDriverState); -} -int32_t I2C7_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C7_DmaDriverState); -} -int32_t I2C7_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C7_DmaDriverState); -} -int32_t I2C7_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C7_DmaDriverState); -} -int32_t I2C7_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C7_DmaDriverState); -} -ARM_I2C_STATUS I2C7_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C7_DmaDriverState); -} - -#endif - -#else -cmsis_i2c_handle_t I2C7_handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c7_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C7_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C7_InterruptDriverState = { -#endif - &I2C7_Resource, &I2C7_handle, - -}; - -static int32_t I2C7_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C7_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C7_InterruptDriverState); -} -static int32_t I2C7_InterruptUninitialize(void) -{ - I2C7_DeinitPins(); - return I2C_InterruptUninitialize(&I2C7_InterruptDriverState); -} -static int32_t I2C7_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C7_InterruptDriverState); -} -int32_t I2C7_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C7_InterruptDriverState); -} - -int32_t I2C7_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C7_InterruptDriverState); -} - -int32_t I2C7_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C7_InterruptDriverState); -} -int32_t I2C7_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C7_InterruptDriverState); -} -int32_t I2C7_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C7_InterruptDriverState); -} -int32_t I2C7_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C7_InterruptDriverState); -} -ARM_I2C_STATUS I2C7_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C7_InterruptDriverState); -} -#endif - -ARM_DRIVER_I2C Driver_I2C7 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C7_DMA_EN - I2C7_Master_DmaInitialize, I2C7_Master_DmaUninitialize, I2C7_Master_DmaPowerControl, - I2C7_Master_DmaTransmit, I2C7_Master_DmaReceive, NULL, NULL, I2C7_Master_DmaGetDataCount, - I2C7_Master_DmaControl, I2C7_Master_DmaGetStatus -#else - I2C7_InterruptInitialize, I2C7_InterruptUninitialize, I2C7_InterruptPowerControl, - I2C7_Master_InterruptTransmit, I2C7_Master_InterruptReceive, I2C7_Slave_InterruptTransmit, - I2C7_Slave_InterruptReceive, I2C7_InterruptGetDataCount, I2C7_InterruptControl, - I2C7_InterruptGetStatus -#endif -}; - -#endif - -#if defined(I2C8) && RTE_I2C8 -/* User needs to provide the implementation for I2C8_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t I2C8_GetFreq(void); -extern void I2C8_InitPins(void); -extern void I2C8_DeinitPins(void); - -cmsis_i2c_resource_t I2C8_Resource = {I2C8, I2C8_GetFreq}; - -#if RTE_I2C8_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C8_DmaResource = {RTE_I2C8_Master_DMA_BASE, RTE_I2C8_Master_DMA_CH}; - -i2c_master_dma_handle_t I2C8_DmaHandle; -dma_handle_t I2C8_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c8_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C8_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C8_DmaDriverState = { -#endif - &I2C8_Resource, &I2C8_DmaResource, &I2C8_DmaHandle, &I2C8_DmaTxRxHandle, -}; - -static int32_t I2C8_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C8_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C8_DmaDriverState); -} -int32_t I2C8_Master_DmaUninitialize(void) -{ - I2C8_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C8_DmaDriverState); -} -int32_t I2C8_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C8_DmaDriverState); -} -int32_t I2C8_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C8_DmaDriverState); -} -int32_t I2C8_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C8_DmaDriverState); -} -int32_t I2C8_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C8_DmaDriverState); -} -int32_t I2C8_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C8_DmaDriverState); -} -ARM_I2C_STATUS I2C8_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C8_DmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C8_handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c8_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C8_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C8_InterruptDriverState = { -#endif - &I2C8_Resource, &I2C8_handle, - -}; - -static int32_t I2C8_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C8_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C8_InterruptDriverState); -} -static int32_t I2C8_InterruptUninitialize(void) -{ - I2C8_DeinitPins(); - return I2C_InterruptUninitialize(&I2C8_InterruptDriverState); -} -static int32_t I2C8_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C8_InterruptDriverState); -} -int32_t I2C8_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C8_InterruptDriverState); -} - -int32_t I2C8_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C8_InterruptDriverState); -} - -int32_t I2C8_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C8_InterruptDriverState); -} -int32_t I2C8_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C8_InterruptDriverState); -} -int32_t I2C8_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C8_InterruptDriverState); -} -int32_t I2C8_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C8_InterruptDriverState); -} -ARM_I2C_STATUS I2C8_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C8_InterruptDriverState); -} -#endif - -ARM_DRIVER_I2C Driver_I2C8 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C8_DMA_EN - I2C8_Master_DmaInitialize, I2C8_Master_DmaUninitialize, I2C8_Master_DmaPowerControl, - I2C8_Master_DmaTransmit, I2C8_Master_DmaReceive, NULL, NULL, I2C8_Master_DmaGetDataCount, - I2C8_Master_DmaControl, I2C8_Master_DmaGetStatus -#else - I2C8_InterruptInitialize, I2C8_InterruptUninitialize, I2C8_InterruptPowerControl, - I2C8_Master_InterruptTransmit, I2C8_Master_InterruptReceive, I2C8_Slave_InterruptTransmit, - I2C8_Slave_InterruptReceive, I2C8_InterruptGetDataCount, I2C8_InterruptControl, - I2C8_InterruptGetStatus -#endif -}; - -#endif - -#if defined(I2C9) && RTE_I2C9 -/* User needs to provide the implementation for I2C9_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t I2C9_GetFreq(void); -extern void I2C9_InitPins(void); -extern void I2C9_DeinitPins(void); - -cmsis_i2c_resource_t I2C9_Resource = {I2C9, I2C9_GetFreq}; - -#if RTE_I2C9_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C9_DmaResource = {RTE_I2C9_Master_DMA_BASE, RTE_I2C9_Master_DMA_CH}; - -i2c_master_dma_handle_t I2C9_DmaHandle; -dma_handle_t I2C9_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c9_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C9_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C9_DmaDriverState = { -#endif - &I2C9_Resource, &I2C9_DmaResource, &I2C9_DmaHandle, &I2C9_DmaTxRxHandle, -}; - -static int32_t I2C9_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C9_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C9_DmaDriverState); -} -int32_t I2C9_Master_DmaUninitialize(void) -{ - I2C9_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C9_DmaDriverState); -} -int32_t I2C9_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C9_DmaDriverState); -} -int32_t I2C9_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C9_DmaDriverState); -} -int32_t I2C9_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C9_DmaDriverState); -} -int32_t I2C9_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C9_DmaDriverState); -} -int32_t I2C9_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C9_DmaDriverState); -} -ARM_I2C_STATUS I2C9_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C9_DmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C9_handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c9_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C9_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C9_InterruptDriverState = { -#endif - &I2C9_Resource, &I2C9_handle, - -}; - -static int32_t I2C9_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C9_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C9_InterruptDriverState); -} -static int32_t I2C9_InterruptUninitialize(void) -{ - I2C9_DeinitPins(); - return I2C_InterruptUninitialize(&I2C9_InterruptDriverState); -} -static int32_t I2C9_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C9_InterruptDriverState); -} -int32_t I2C9_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C9_InterruptDriverState); -} - -int32_t I2C9_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C9_InterruptDriverState); -} - -int32_t I2C9_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C9_InterruptDriverState); -} -int32_t I2C9_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C9_InterruptDriverState); -} -int32_t I2C9_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C9_InterruptDriverState); -} -int32_t I2C9_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C9_InterruptDriverState); -} -ARM_I2C_STATUS I2C9_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C9_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C9 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C9_DMA_EN - I2C9_Master_DmaInitialize, I2C9_Master_DmaUninitialize, I2C9_Master_DmaPowerControl, - I2C9_Master_DmaTransmit, I2C9_Master_DmaReceive, NULL, NULL, I2C9_Master_DmaGetDataCount, - I2C9_Master_DmaControl, I2C9_Master_DmaGetStatus -#else - I2C9_InterruptInitialize, I2C9_InterruptUninitialize, I2C9_InterruptPowerControl, - I2C9_Master_InterruptTransmit, I2C9_Master_InterruptReceive, I2C9_Slave_InterruptTransmit, - I2C9_Slave_InterruptReceive, I2C9_InterruptGetDataCount, I2C9_InterruptControl, - I2C9_InterruptGetStatus -#endif -}; - -#endif diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/cmsis_drivers/fsl_i2c_cmsis.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/cmsis_drivers/fsl_i2c_cmsis.h deleted file mode 100644 index e517179f232..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/cmsis_drivers/fsl_i2c_cmsis.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2013-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_I2C_CMSIS_H_ -#define _FSL_I2C_CMSIS_H_ -#include "fsl_common.h" -#include "Driver_I2C.h" -#include "RTE_Device.h" -#include "fsl_i2c.h" -#include "fsl_flexcomm.h" -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) -#include "fsl_i2c_dma.h" -#endif - -#if defined(I2C0) -extern ARM_DRIVER_I2C Driver_I2C0; -#endif - -#if defined(I2C1) -extern ARM_DRIVER_I2C Driver_I2C1; -#endif - -#if defined(I2C2) -extern ARM_DRIVER_I2C Driver_I2C2; -#endif - -#if defined(I2C3) -extern ARM_DRIVER_I2C Driver_I2C3; -#endif - -#if defined(I2C4) -extern ARM_DRIVER_I2C Driver_I2C4; -#endif - -#if defined(I2C5) -extern ARM_DRIVER_I2C Driver_I2C5; -#endif - -#if defined(I2C6) -extern ARM_DRIVER_I2C Driver_I2C6; -#endif - -#if defined(I2C7) -extern ARM_DRIVER_I2C Driver_I2C7; -#endif - -#if defined(I2C8) -extern ARM_DRIVER_I2C Driver_I2C8; -#endif - -#if defined(I2C9) -extern ARM_DRIVER_I2C Driver_I2C9; -#endif - -#endif diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/cmsis_drivers/fsl_spi_cmsis.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/cmsis_drivers/fsl_spi_cmsis.c deleted file mode 100644 index 99d912a78be..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/cmsis_drivers/fsl_spi_cmsis.c +++ /dev/null @@ -1,2654 +0,0 @@ -/* - * Copyright (c) 2013-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_spi_cmsis.h" - -#if (RTE_SPI0 || RTE_SPI1 || RTE_SPI2 || RTE_SPI3 || RTE_SPI4 || RTE_SPI5 || RTE_SPI6 || RTE_SPI7 || RTE_SPI8 || \ - RTE_SPI9) - -#define ARM_SPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */ - -/*! @brief IDs of clock for each FLEXCOMM module */ -static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; -/* Array of SPI reset number. */ -static const reset_ip_name_t s_spiResetInstance[] = FLEXCOMM_RSTS; -/* - * ARMCC does not support split the data section automatically, so the driver - * needs to split the data to separate sections explicitly, to reduce codesize. - */ -#if defined(__CC_ARM) -#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) -#endif - -typedef struct _cmsis_spi_status -{ - bool isInitialized; - bool isPowerOn; - bool isConfigured; - bool isMasterMode; -} cmsis_spi_status_t; - -typedef const struct _cmsis_spi_resource -{ - SPI_Type *base; - uint32_t instance; - uint32_t (*GetFreq)(void); -} cmsis_spi_resource_t; - -typedef union _cmsis_spi_handle -{ - spi_master_handle_t masterHandle; - spi_slave_handle_t slaveHandle; -} cmsis_spi_handle_t; - -typedef struct _cmsis_spi_interrupt_driver_state -{ - cmsis_spi_resource_t *resource; - cmsis_spi_handle_t *handle; - ARM_SPI_SignalEvent_t cb_event; - uint32_t baudRate_Bps; - cmsis_spi_status_t status; -} cmsis_spi_interrupt_driver_state_t; - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -typedef const struct _cmsis_spi_dma_resource -{ - DMA_Type *txdmaBase; - uint32_t txdmaChannel; - - DMA_Type *rxdmaBase; - uint32_t rxdmaChannel; -} cmsis_spi_dma_resource_t; - -typedef union _cmsis_spi_dma_handle -{ - spi_dma_handle_t masterHandle; - spi_dma_handle_t slaveHandle; -} cmsis_spi_dma_handle_t; - -typedef struct _cmsis_spi_dma_driver_state -{ - cmsis_spi_resource_t *resource; - cmsis_spi_dma_resource_t *dmaResource; - cmsis_spi_dma_handle_t *handle; - dma_handle_t *dmaRxDataHandle; - dma_handle_t *dmaTxDataHandle; - - uint32_t baudRate_Bps; - ARM_SPI_SignalEvent_t cb_event; - cmsis_spi_status_t status; -} cmsis_spi_dma_driver_state_t; -#endif - -/* Driver Version */ -static const ARM_DRIVER_VERSION s_SPIDriverVersion = {ARM_SPI_API_VERSION, ARM_SPI_DRV_VERSION}; - -/* Driver Capabilities */ -static const ARM_SPI_CAPABILITIES s_SPIDriverCapabilities = { - 1, /* Simplex Mode (Master and Slave) */ - 0, /* TI Synchronous Serial Interface */ - 0, /* Microwire Interface */ - 0 /* Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT */ -}; - -/******************************************************************************* - * Code - ******************************************************************************/ - -void SPI_MasterCommonControl(uint32_t control, - cmsis_spi_resource_t *resource, - cmsis_spi_status_t *status, - spi_master_config_t *masterConfig) -{ - switch (resource->instance) - { - case 0: - masterConfig->sselNum = RTE_SPI0_SSEL_NUM; - break; - - case 1: - masterConfig->sselNum = RTE_SPI1_SSEL_NUM; - break; - - case 2: - masterConfig->sselNum = RTE_SPI2_SSEL_NUM; - break; - - case 3: - masterConfig->sselNum = RTE_SPI3_SSEL_NUM; - break; - - case 4: - masterConfig->sselNum = RTE_SPI4_SSEL_NUM; - break; - - case 5: - masterConfig->sselNum = RTE_SPI5_SSEL_NUM; - break; - - case 6: - masterConfig->sselNum = RTE_SPI6_SSEL_NUM; - break; - - case 7: - masterConfig->sselNum = RTE_SPI7_SSEL_NUM; - break; - - case 8: -#if defined(RTE_SPI8_SSEL_NUM) - masterConfig->sselNum = RTE_SPI8_SSEL_NUM; -#endif - break; - - case 9: -#if defined(RTE_SPI9_SSEL_NUM) - masterConfig->sselNum = RTE_SPI9_SSEL_NUM; -#endif - break; - - default: - break; - } - - switch (control & ARM_SPI_FRAME_FORMAT_Msk) - { - case ARM_SPI_CPOL0_CPHA1: - masterConfig->polarity = kSPI_ClockPolarityActiveLow; - masterConfig->phase = kSPI_ClockPhaseSecondEdge; - break; - - case ARM_SPI_CPOL1_CPHA0: - masterConfig->polarity = kSPI_ClockPolarityActiveHigh; - masterConfig->phase = kSPI_ClockPhaseFirstEdge; - break; - - case ARM_SPI_CPOL1_CPHA1: - masterConfig->polarity = kSPI_ClockPolarityActiveHigh; - masterConfig->phase = kSPI_ClockPhaseSecondEdge; - break; - case ARM_SPI_CPOL0_CPHA0: - masterConfig->polarity = kSPI_ClockPolarityActiveLow; - masterConfig->phase = kSPI_ClockPhaseFirstEdge; - break; - - default: - break; - } - - if (control & ARM_SPI_DATA_BITS_Msk) /* setting Number of Data bits */ - { - if ((((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) >= 4) && - (((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) <= 16)) - { - masterConfig->dataWidth = - (spi_data_width_t)(((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) - 1); - } - } - - switch (control & ARM_SPI_BIT_ORDER_Msk) - { - case ARM_SPI_LSB_MSB: - masterConfig->direction = kSPI_LsbFirst; - break; - case ARM_SPI_MSB_LSB: - masterConfig->direction = kSPI_MsbFirst; - break; - - default: - break; - } -} - -void SPI_SlaveCommonControl(uint32_t control, - cmsis_spi_resource_t *resource, - cmsis_spi_status_t *status, - spi_slave_config_t *slaveConfig) -{ - switch (control & ARM_SPI_FRAME_FORMAT_Msk) - { - case ARM_SPI_CPOL0_CPHA1: - slaveConfig->polarity = kSPI_ClockPolarityActiveLow; - slaveConfig->phase = kSPI_ClockPhaseSecondEdge; - break; - - case ARM_SPI_CPOL1_CPHA0: - slaveConfig->polarity = kSPI_ClockPolarityActiveHigh; - slaveConfig->phase = kSPI_ClockPhaseFirstEdge; - break; - - case ARM_SPI_CPOL1_CPHA1: - slaveConfig->polarity = kSPI_ClockPolarityActiveHigh; - slaveConfig->phase = kSPI_ClockPhaseSecondEdge; - break; - case ARM_SPI_CPOL0_CPHA0: - slaveConfig->polarity = kSPI_ClockPolarityActiveLow; - slaveConfig->phase = kSPI_ClockPhaseFirstEdge; - break; - - default: - break; - } - if (control & ARM_SPI_DATA_BITS_Msk) /* setting Number of Data bits */ - { - if ((((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) >= 4) && - (((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) <= 16)) - { - slaveConfig->dataWidth = - (spi_data_width_t)(((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) - 1); - } - } - switch (control & ARM_SPI_BIT_ORDER_Msk) - { - case ARM_SPI_LSB_MSB: - slaveConfig->direction = kSPI_LsbFirst; - break; - case ARM_SPI_MSB_LSB: - slaveConfig->direction = kSPI_MsbFirst; - break; - - default: - break; - } -} - -static ARM_DRIVER_VERSION SPIx_GetVersion(void) -{ - return s_SPIDriverVersion; -} - -static ARM_SPI_CAPABILITIES SPIx_GetCapabilities(void) -{ - return s_SPIDriverCapabilities; -} - -#endif - -#if (RTE_SPI0_DMA_EN || RTE_SPI1_DMA_EN || RTE_SPI2_DMA_EN || RTE_SPI3_DMA_EN || RTE_SPI4_DMA_EN || RTE_SPI5_DMA_EN || \ - RTE_SPI6_DMA_EN || RTE_SPI7_DMA_EN || RTE_SPI8_DMA_EN || RTE_SPI9_DMA_EN) - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -void KSDK_SPI_MasterDMACallback(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData) -{ - uint32_t event = 0; - - if (kStatus_Success == status) - { - event = ARM_SPI_EVENT_TRANSFER_COMPLETE; - } - - if (kStatus_SPI_Error == status) - { - event = ARM_SPI_EVENT_DATA_LOST; - } - - if (userData) - { - ((ARM_SPI_SignalEvent_t)userData)(event); - } -} -void KSDK_SPI_SlaveDMACallback(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData) -{ - uint32_t event = 0; - - if (kStatus_Success == status) - { - event = ARM_SPI_EVENT_TRANSFER_COMPLETE; - } - - if (kStatus_SPI_Error == status) - { - event = ARM_SPI_EVENT_DATA_LOST; - } - /* User data is actually CMSIS driver callback. */ - if (userData) - { - ((ARM_SPI_SignalEvent_t)userData)(event); - } -} - -static int32_t SPI_DMAInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_spi_dma_driver_state_t *spi) -{ - if (spi->status.isInitialized) - { - return ARM_DRIVER_OK; - } - - spi->status.isInitialized = true; - spi->cb_event = cb_event; - return ARM_DRIVER_OK; -} - -static int32_t SPI_DMAUninitialize(cmsis_spi_dma_driver_state_t *spi) -{ - spi->status.isInitialized = false; - return ARM_DRIVER_OK; -} - -static int32_t SPI_DMAPowerControl(ARM_POWER_STATE state, cmsis_spi_dma_driver_state_t *spi) -{ - switch (state) - { - case ARM_POWER_OFF: - if (spi->status.isPowerOn) - { - SPI_Deinit(spi->resource->base); - RESET_PeripheralReset(s_spiResetInstance[spi->resource->instance]); - - DMA_DisableChannel(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel); - DMA_DisableChannel(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); - DMA_Deinit(spi->dmaResource->txdmaBase); - DMA_Deinit(spi->dmaResource->rxdmaBase); - - spi->status.isPowerOn = false; - spi->status.isConfigured = false; - spi->status.isMasterMode = false; - } - break; - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - case ARM_POWER_FULL: - if (!spi->status.isInitialized) - { - return ARM_DRIVER_ERROR; - } - - if (!spi->status.isPowerOn) - { - /* Enable flexcomm clock gate */ - CLOCK_EnableClock(s_flexcommClocks[spi->resource->instance]); - /* Init DMA */ - DMA_Init(spi->dmaResource->rxdmaBase); - DMA_Init(spi->dmaResource->txdmaBase); - spi->status.isPowerOn = true; - } - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - return ARM_DRIVER_OK; -} - -static int32_t SPI_DMASend(const void *data, uint32_t num, cmsis_spi_dma_driver_state_t *spi) -{ - int32_t ret; - status_t status; - spi_transfer_t xfer; - - xfer.rxData = NULL; - xfer.txData = (uint8_t *)data; - xfer.dataSize = num; - if (spi->status.isMasterMode) - { - xfer.configFlags |= kSPI_FrameAssert; - } - - if (spi->status.isMasterMode) - { - status = SPI_MasterTransferDMA(spi->resource->base, &spi->handle->masterHandle, &xfer); - } - else - { - status = SPI_SlaveTransferDMA(spi->resource->base, &spi->handle->slaveHandle, &xfer); - } - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_SPI_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t SPI_DMAReceive(void *data, uint32_t num, cmsis_spi_dma_driver_state_t *spi) -{ - int32_t ret; - status_t status; - spi_transfer_t xfer; - - xfer.txData = NULL; - xfer.rxData = (uint8_t *)data; - xfer.dataSize = num; - if (spi->status.isMasterMode) - { - xfer.configFlags |= kSPI_FrameAssert; - } - - if (spi->status.isMasterMode) - { - status = SPI_MasterTransferDMA(spi->resource->base, &spi->handle->masterHandle, &xfer); - } - else - { - status = SPI_SlaveTransferDMA(spi->resource->base, &spi->handle->slaveHandle, &xfer); - } - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_SPI_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t SPI_DMATransfer(const void *data_out, void *data_in, uint32_t num, cmsis_spi_dma_driver_state_t *spi) -{ - int32_t ret; - status_t status; - spi_transfer_t xfer; - - xfer.txData = (uint8_t *)data_out; - xfer.rxData = (uint8_t *)data_in; - xfer.dataSize = num; - if (spi->status.isMasterMode) - { - xfer.configFlags |= kSPI_FrameAssert; - } - - if (spi->status.isMasterMode) - { - status = SPI_MasterTransferDMA(spi->resource->base, &spi->handle->masterHandle, &xfer); - } - else - { - status = SPI_SlaveTransferDMA(spi->resource->base, &spi->handle->slaveHandle, &xfer); - } - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_SPI_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} -static uint32_t SPI_DMAGetCount(cmsis_spi_dma_driver_state_t *spi) -{ - uint32_t cnt; - size_t bytes; - - bytes = DMA_GetRemainingBytes(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); - - if (spi->status.isMasterMode) - { - cnt = spi->handle->masterHandle.transferSize - bytes; - } - else - { - cnt = spi->handle->slaveHandle.transferSize - bytes; - } - - return cnt; -} - -static int32_t SPI_DMAControl(uint32_t control, uint32_t arg, cmsis_spi_dma_driver_state_t *spi) -{ - if (!spi->status.isPowerOn) - { - return ARM_DRIVER_ERROR; - } - - switch (control & ARM_SPI_CONTROL_Msk) - { - case ARM_SPI_MODE_INACTIVE: - SPI_Enable(spi->resource->base, false); - break; - case ARM_SPI_MODE_MASTER: - spi->baudRate_Bps = arg; - spi->status.isMasterMode = true; - break; - - case ARM_SPI_MODE_SLAVE: - { - spi->status.isMasterMode = false; - } - break; - - case ARM_SPI_SET_BUS_SPEED: - if (!spi->status.isMasterMode) - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - SPI_MasterSetBaud(spi->resource->base, arg, spi->resource->GetFreq()); - - spi->baudRate_Bps = arg; - return ARM_DRIVER_OK; - - case ARM_SPI_GET_BUS_SPEED: /* Set Bus Speed in bps; arg = value */ - if (!spi->status.isMasterMode) - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - return spi->baudRate_Bps; - - case ARM_SPI_CONTROL_SS: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - case ARM_SPI_ABORT_TRANSFER: - if (spi->status.isMasterMode) - { - SPI_MasterTransferAbortDMA(spi->resource->base, &spi->handle->masterHandle); - } - else - { - SPI_SlaveTransferAbortDMA(spi->resource->base, &spi->handle->slaveHandle); - } - return ARM_DRIVER_OK; - - default: - break; - } - - if (spi->status.isMasterMode) - { - switch (control & ARM_SPI_SS_MASTER_MODE_Msk) - { - /* - * Note: - * ARM_SPI_SS_MASTER_HW_OUTPUT is default configuration in driver, if ARM_SPI_SS_MASTER_UNUSED or - * ARM_SPI_SS_MASTER_SW is wanted, please disable pin function in SPIx_InitPins() which is configured - * by user in extern file. Besides ARM_SPI_SS_MASTER_HW_INPUT is not supported in this driver. - */ - case ARM_SPI_SS_MASTER_UNUSED: /*!< SPI Slave Select when Master: Not used */ - break; - case ARM_SPI_SS_MASTER_SW: /*!< SPI Slave Select when Master: Software controlled. */ - break; - case ARM_SPI_SS_MASTER_HW_OUTPUT: /*!< SPI Slave Select when Master: Hardware controlled Output */ - break; - case ARM_SPI_SS_MASTER_HW_INPUT: /*!< SPI Slave Select when Master: Hardware monitored Input */ - return ARM_SPI_ERROR_SS_MODE; - default: - break; - } - spi_master_config_t masterConfig; - SPI_MasterGetDefaultConfig(&masterConfig); - masterConfig.baudRate_Bps = spi->baudRate_Bps; - SPI_MasterCommonControl(control, spi->resource, &spi->status, &masterConfig); - - if (spi->status.isConfigured) - { - SPI_Deinit(spi->resource->base); - RESET_PeripheralReset(s_spiResetInstance[spi->resource->instance]); - } - SPI_MasterInit(spi->resource->base, &masterConfig, spi->resource->GetFreq()); - - DMA_EnableChannel(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel); - DMA_EnableChannel(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); - DMA_SetChannelPriority(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel, kDMA_ChannelPriority3); - DMA_SetChannelPriority(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel, kDMA_ChannelPriority2); - DMA_CreateHandle(spi->dmaTxDataHandle, spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel); - DMA_CreateHandle(spi->dmaRxDataHandle, spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); - - SPI_MasterTransferCreateHandleDMA(spi->resource->base, &(spi->handle->masterHandle), KSDK_SPI_MasterDMACallback, - (void *)spi->cb_event, spi->dmaTxDataHandle, spi->dmaRxDataHandle); - spi->status.isConfigured = true; - } - else - { - spi_slave_config_t slaveConfig; - SPI_SlaveGetDefaultConfig(&slaveConfig); - SPI_SlaveCommonControl(control, spi->resource, &spi->status, &slaveConfig); - - if (spi->status.isConfigured) - { - SPI_Deinit(spi->resource->base); - RESET_PeripheralReset(s_spiResetInstance[spi->resource->instance]); - } - SPI_SlaveInit(spi->resource->base, &slaveConfig); - - DMA_EnableChannel(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel); - DMA_EnableChannel(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); - DMA_SetChannelPriority(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel, kDMA_ChannelPriority0); - DMA_SetChannelPriority(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel, kDMA_ChannelPriority1); - DMA_CreateHandle(spi->dmaTxDataHandle, spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel); - DMA_CreateHandle(spi->dmaRxDataHandle, spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); - - SPI_SlaveTransferCreateHandleDMA(spi->resource->base, &(spi->handle->slaveHandle), KSDK_SPI_SlaveDMACallback, - (void *)spi->cb_event, spi->dmaTxDataHandle, spi->dmaRxDataHandle); - - spi->status.isConfigured = true; - } - - return ARM_DRIVER_OK; -} - -ARM_SPI_STATUS SPI_DMAGetStatus(cmsis_spi_dma_driver_state_t *spi) -{ - ARM_SPI_STATUS stat; - - if (spi->status.isMasterMode) - { - stat.busy = - ((spi->handle->masterHandle.txInProgress == true) || (spi->handle->masterHandle.rxInProgress == true)) ? - (0U) : - (1U); - stat.data_lost = (kStatus_SPI_Error == spi->handle->masterHandle.state) ? (1U) : (0U); - } - else - { - stat.busy = - ((spi->handle->slaveHandle.txInProgress == true) || (spi->handle->slaveHandle.rxInProgress == true)) ? - (0U) : - (1U); - stat.data_lost = (kStatus_SPI_Error == spi->handle->slaveHandle.state) ? (1U) : (0U); - } - - stat.mode_fault = 0U; - return stat; -} -#endif /* defined(FSL_FEATURE_SOC_DMA_COUNT) */ - -#endif - -#if ((RTE_SPI0 && !RTE_SPI0_DMA_EN) || (RTE_SPI1 && !RTE_SPI1_DMA_EN) || (RTE_SPI2 && !RTE_SPI2_DMA_EN) || \ - (RTE_SPI3 && !RTE_SPI3_DMA_EN) || (RTE_SPI4 && !RTE_SPI4_DMA_EN) || (RTE_SPI5 && !RTE_SPI5_DMA_EN) || \ - (RTE_SPI6 && !RTE_SPI6_DMA_EN) || (RTE_SPI7 && !RTE_SPI7_DMA_EN) || (RTE_SPI8 && !RTE_SPI8_DMA_EN) || \ - (RTE_SPI9 && !RTE_SPI9_DMA_EN)) - -void KSDK_SPI_MasterInterruptCallback(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData) -{ - uint32_t event = 0; - - if ((kStatus_Success == status) || (kStatus_SPI_Idle == status)) - { - event = ARM_SPI_EVENT_TRANSFER_COMPLETE; - } - - if (kStatus_SPI_Error == status) - { - event = ARM_SPI_EVENT_DATA_LOST; - } - - /* User data is actually CMSIS driver callback. */ - if (userData) - { - ((ARM_SPI_SignalEvent_t)userData)(event); - } -} - -void KSDK_SPI_SlaveInterruptCallback(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData) -{ - uint32_t event = 0; - - if ((kStatus_Success == status) || (kStatus_SPI_Idle == status)) - { - event = ARM_SPI_EVENT_TRANSFER_COMPLETE; - } - - if (kStatus_SPI_Error == status) - { - event = ARM_SPI_EVENT_DATA_LOST; - } - - /* User data is actually CMSIS driver callback. */ - if (userData) - { - ((ARM_SPI_SignalEvent_t)userData)(event); - } -} - -static int32_t SPI_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_spi_interrupt_driver_state_t *spi) -{ - if (spi->status.isInitialized) - { - return ARM_DRIVER_OK; - } - spi->cb_event = cb_event; - spi->status.isInitialized = true; - return ARM_DRIVER_OK; -} - -static int32_t SPI_InterruptUninitialize(cmsis_spi_interrupt_driver_state_t *spi) -{ - spi->status.isInitialized = false; - return ARM_DRIVER_OK; -} - -static int32_t SPI_InterruptPowerControl(ARM_POWER_STATE state, cmsis_spi_interrupt_driver_state_t *spi) -{ - switch (state) - { - case ARM_POWER_OFF: - if (spi->status.isPowerOn) - { - SPI_Deinit(spi->resource->base); - /* Reset Periphera instance, and disable the clock gate */ - RESET_PeripheralReset(s_spiResetInstance[spi->resource->instance]); - spi->status.isPowerOn = false; - spi->status.isConfigured = false; - spi->status.isMasterMode = false; - } - break; - - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - case ARM_POWER_FULL: - if (!spi->status.isInitialized) - { - return ARM_DRIVER_ERROR; - } - - if (!spi->status.isPowerOn) - { - /* Enable flexcomm clock gate */ - CLOCK_EnableClock(s_flexcommClocks[spi->resource->instance]); - spi->status.isPowerOn = true; - } - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - return ARM_DRIVER_OK; -} - -static int32_t SPI_InterruptSend(const void *data, uint32_t num, cmsis_spi_interrupt_driver_state_t *spi) -{ - int32_t ret; - status_t status; - spi_transfer_t xfer; - - xfer.rxData = NULL; - xfer.txData = (uint8_t *)data; - xfer.dataSize = num; - if (spi->status.isMasterMode) - { - xfer.configFlags |= kSPI_FrameAssert; - } - - if (spi->status.isMasterMode) - { - status = SPI_MasterTransferNonBlocking(spi->resource->base, &spi->handle->masterHandle, &xfer); - } - else - { - status = SPI_SlaveTransferNonBlocking(spi->resource->base, &spi->handle->slaveHandle, &xfer); - } - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_SPI_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t SPI_InterruptReceive(void *data, uint32_t num, cmsis_spi_interrupt_driver_state_t *spi) -{ - int32_t ret; - status_t status; - spi_transfer_t xfer; - - xfer.txData = NULL; - xfer.rxData = (uint8_t *)data; - xfer.dataSize = num; - if (spi->status.isMasterMode) - { - xfer.configFlags |= kSPI_FrameAssert; - } - - if (spi->status.isMasterMode) - { - status = SPI_MasterTransferNonBlocking(spi->resource->base, &spi->handle->masterHandle, &xfer); - } - else - { - status = SPI_SlaveTransferNonBlocking(spi->resource->base, &spi->handle->slaveHandle, &xfer); - } - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_SPI_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t SPI_InterruptTransfer(const void *data_out, - void *data_in, - uint32_t num, - cmsis_spi_interrupt_driver_state_t *spi) -{ - int32_t ret; - status_t status; - spi_transfer_t xfer; - - xfer.txData = (uint8_t *)data_out; - xfer.rxData = (uint8_t *)data_in; - xfer.dataSize = num; - if (spi->status.isMasterMode) - { - xfer.configFlags |= kSPI_FrameAssert; - } - - if (spi->status.isMasterMode) - { - status = SPI_MasterTransferNonBlocking(spi->resource->base, &spi->handle->masterHandle, &xfer); - } - else - { - status = SPI_SlaveTransferNonBlocking(spi->resource->base, &spi->handle->slaveHandle, &xfer); - } - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_SPI_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} -static uint32_t SPI_InterruptGetCount(cmsis_spi_interrupt_driver_state_t *spi) -{ - if (spi->status.isMasterMode) - { - return spi->handle->masterHandle.totalByteCount - spi->handle->masterHandle.rxRemainingBytes; - } - else - { - return spi->handle->slaveHandle.toReceiveCount - spi->handle->slaveHandle.rxRemainingBytes; - } -} - -static int32_t SPI_InterruptControl(uint32_t control, uint32_t arg, cmsis_spi_interrupt_driver_state_t *spi) -{ - if (!spi->status.isPowerOn) - { - return ARM_DRIVER_ERROR; - } - - switch (control & ARM_SPI_CONTROL_Msk) - { - case ARM_SPI_MODE_INACTIVE: /* SPI mode Inactive */ - FLEXCOMM_Init(spi->resource->base, FLEXCOMM_PERIPH_NONE); - break; - - case ARM_SPI_MODE_MASTER: /* SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps */ - spi->baudRate_Bps = arg; - spi->status.isMasterMode = true; - break; - - case ARM_SPI_MODE_SLAVE: /* SPI Slave (Output on MISO, Input on MOSI) */ - spi->status.isMasterMode = false; - break; - - case ARM_SPI_GET_BUS_SPEED: /* Get Bus Speed in bps */ - if (!spi->status.isMasterMode) - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - return spi->baudRate_Bps; - - case ARM_SPI_SET_BUS_SPEED: /* Set Bus Speed in bps; */ - if (!spi->status.isMasterMode) - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - SPI_MasterSetBaud(spi->resource->base, arg, spi->resource->GetFreq()); - spi->baudRate_Bps = arg; - - return ARM_DRIVER_OK; - - case ARM_SPI_CONTROL_SS: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - case ARM_SPI_ABORT_TRANSFER: /* Abort current data transfer */ - if (spi->status.isMasterMode) - { - SPI_MasterTransferAbort(spi->resource->base, &spi->handle->masterHandle); - } - else - { - SPI_SlaveTransferAbort(spi->resource->base, &spi->handle->slaveHandle); - } - return ARM_DRIVER_OK; - - default: - break; - } - - if (spi->status.isMasterMode) - { - switch (control & ARM_SPI_SS_MASTER_MODE_Msk) - { - /* - * Note: - * ARM_SPI_SS_MASTER_HW_OUTPUT is default configuration in driver, if ARM_SPI_SS_MASTER_UNUSED or - * ARM_SPI_SS_MASTER_SW is wanted, please disable pin function in SPIx_InitPins() which is configured - * by user in extern file. Besides ARM_SPI_SS_MASTER_HW_INPUT is not supported in this driver. - */ - case ARM_SPI_SS_MASTER_UNUSED: /*!< SPI Slave Select when Master: Not used */ - break; - case ARM_SPI_SS_MASTER_SW: /*!< SPI Slave Select when Master: Software controlled. */ - break; - case ARM_SPI_SS_MASTER_HW_OUTPUT: /*!< SPI Slave Select when Master: Hardware controlled Output */ - break; - case ARM_SPI_SS_MASTER_HW_INPUT: /*!< SPI Slave Select when Master: Hardware monitored Input */ - return ARM_SPI_ERROR_SS_MODE; - default: - break; - } - - spi_master_config_t masterConfig; - SPI_MasterGetDefaultConfig(&masterConfig); - masterConfig.baudRate_Bps = spi->baudRate_Bps; - - SPI_MasterCommonControl(control, spi->resource, &spi->status, &masterConfig); - - if (spi->status.isConfigured) - { - SPI_Deinit(spi->resource->base); - RESET_PeripheralReset(s_spiResetInstance[spi->resource->instance]); - } - SPI_MasterInit(spi->resource->base, &masterConfig, spi->resource->GetFreq()); - SPI_MasterTransferCreateHandle(spi->resource->base, &spi->handle->masterHandle, - KSDK_SPI_MasterInterruptCallback, (void *)spi->cb_event); - spi->status.isConfigured = true; - } - else - { - spi_slave_config_t slaveConfig; - SPI_SlaveGetDefaultConfig(&slaveConfig); - - SPI_SlaveCommonControl(control, spi->resource, &spi->status, &slaveConfig); - - if (spi->status.isConfigured) - { - SPI_Deinit(spi->resource->base); - RESET_PeripheralReset(s_spiResetInstance[spi->resource->instance]); - } - SPI_SlaveInit(spi->resource->base, &slaveConfig); - SPI_SlaveTransferCreateHandle(spi->resource->base, &spi->handle->slaveHandle, KSDK_SPI_SlaveInterruptCallback, - (void *)spi->cb_event); - spi->status.isConfigured = true; - } - - return ARM_DRIVER_OK; -} - -ARM_SPI_STATUS SPI_InterruptGetStatus(cmsis_spi_interrupt_driver_state_t *spi) -{ - ARM_SPI_STATUS stat; - - if (spi->status.isMasterMode) - { - stat.busy = - ((spi->handle->masterHandle.txRemainingBytes > 0) || (spi->handle->masterHandle.rxRemainingBytes > 0)) ? - (0U) : - (1U); - stat.data_lost = (kStatus_SPI_Error == spi->handle->masterHandle.state) ? (1U) : (0U); - } - else - { - stat.busy = - ((spi->handle->slaveHandle.txRemainingBytes > 0) || (spi->handle->slaveHandle.rxRemainingBytes > 0)) ? - (0U) : - (1U); - stat.data_lost = (kStatus_SPI_Error == spi->handle->slaveHandle.state) ? (1U) : (0U); - } - - stat.mode_fault = 0U; - return stat; -} - -#endif - -#if defined(SPI0) && RTE_SPI0 - -/* User needs to provide the implementation for SPI0_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t SPI0_GetFreq(void); -extern void SPI0_InitPins(void); -extern void SPI0_DeinitPins(void); - -cmsis_spi_resource_t SPI0_Resource = {SPI0, 0, SPI0_GetFreq}; - -#if RTE_SPI0_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_spi_dma_resource_t SPI0_DMAResource = {RTE_SPI0_DMA_TX_DMA_BASE, RTE_SPI0_DMA_TX_CH, RTE_SPI0_DMA_RX_DMA_BASE, - RTE_SPI0_DMA_RX_CH}; - -static cmsis_spi_dma_handle_t SPI0_DmaHandle; -static dma_handle_t SPI0_DmaTxDataHandle; -static dma_handle_t SPI0_DmaRxDataHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi0_dma_driver_state") -static cmsis_spi_dma_driver_state_t SPI0_DMADriverState = { -#else -static cmsis_spi_dma_driver_state_t SPI0_DMADriverState = { -#endif - &SPI0_Resource, &SPI0_DMAResource, &SPI0_DmaHandle, &SPI0_DmaTxDataHandle, &SPI0_DmaRxDataHandle, - -}; - -static int32_t SPI0_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI0_InitPins(); - return SPI_DMAInitialize(cb_event, &SPI0_DMADriverState); -} - -static int32_t SPI0_DMAUninitialize(void) -{ - SPI0_DeinitPins(); - return SPI_DMAUninitialize(&SPI0_DMADriverState); -} - -static int32_t SPI0_DMAPowerControl(ARM_POWER_STATE state) -{ - return SPI_DMAPowerControl(state, &SPI0_DMADriverState); -} - -static int32_t SPI0_DMASend(const void *data, uint32_t num) -{ - return SPI_DMASend(data, num, &SPI0_DMADriverState); -} - -static int32_t SPI0_DMAReceive(void *data, uint32_t num) -{ - return SPI_DMAReceive(data, num, &SPI0_DMADriverState); -} - -static int32_t SPI0_DMATransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_DMATransfer(data_out, data_in, num, &SPI0_DMADriverState); -} - -static uint32_t SPI0_DMAGetCount(void) -{ - return SPI_DMAGetCount(&SPI0_DMADriverState); -} - -static int32_t SPI0_DMAControl(uint32_t control, uint32_t arg) -{ - return SPI_DMAControl(control, arg, &SPI0_DMADriverState); -} - -static ARM_SPI_STATUS SPI0_DMAGetStatus(void) -{ - return SPI_DMAGetStatus(&SPI0_DMADriverState); -} - -#endif - -#else - -static cmsis_spi_handle_t SPI0_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi0_interrupt_driver_state") -static cmsis_spi_interrupt_driver_state_t SPI0_InterruptDriverState = { -#else -static cmsis_spi_interrupt_driver_state_t SPI0_InterruptDriverState = { -#endif - &SPI0_Resource, &SPI0_Handle, -}; - -static int32_t SPI0_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI0_InitPins(); - return SPI_InterruptInitialize(cb_event, &SPI0_InterruptDriverState); -} - -static int32_t SPI0_InterruptUninitialize(void) -{ - SPI0_DeinitPins(); - return SPI_InterruptUninitialize(&SPI0_InterruptDriverState); -} - -static int32_t SPI0_InterruptPowerControl(ARM_POWER_STATE state) -{ - return SPI_InterruptPowerControl(state, &SPI0_InterruptDriverState); -} - -static int32_t SPI0_InterruptSend(const void *data, uint32_t num) -{ - return SPI_InterruptSend(data, num, &SPI0_InterruptDriverState); -} - -static int32_t SPI0_InterruptReceive(void *data, uint32_t num) -{ - return SPI_InterruptReceive(data, num, &SPI0_InterruptDriverState); -} - -static int32_t SPI0_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_InterruptTransfer(data_out, data_in, num, &SPI0_InterruptDriverState); -} - -static uint32_t SPI0_InterruptGetCount(void) -{ - return SPI_InterruptGetCount(&SPI0_InterruptDriverState); -} - -static int32_t SPI0_InterruptControl(uint32_t control, uint32_t arg) -{ - return SPI_InterruptControl(control, arg, &SPI0_InterruptDriverState); -} - -static ARM_SPI_STATUS SPI0_InterruptGetStatus(void) -{ - return SPI_InterruptGetStatus(&SPI0_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI0 = {SPIx_GetVersion, SPIx_GetCapabilities, -#if RTE_SPI0_DMA_EN - SPI0_DMAInitialize, SPI0_DMAUninitialize, SPI0_DMAPowerControl, SPI0_DMASend, - SPI0_DMAReceive, SPI0_DMATransfer, SPI0_DMAGetCount, SPI0_DMAControl, - SPI0_DMAGetStatus -#else - SPI0_InterruptInitialize, SPI0_InterruptUninitialize, SPI0_InterruptPowerControl, - SPI0_InterruptSend, SPI0_InterruptReceive, SPI0_InterruptTransfer, SPI0_InterruptGetCount, - SPI0_InterruptControl, SPI0_InterruptGetStatus -#endif -}; - -#endif /* SPI0 */ - -#if defined(SPI1) && RTE_SPI1 -/* User needs to provide the implementation for SPI1_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t SPI1_GetFreq(void); -extern void SPI1_InitPins(void); -extern void SPI1_DeinitPins(void); -cmsis_spi_resource_t SPI1_Resource = {SPI1, 1, SPI1_GetFreq}; - -#if RTE_SPI1_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_spi_dma_resource_t SPI1_DMAResource = {RTE_SPI1_DMA_TX_DMA_BASE, RTE_SPI1_DMA_TX_CH, RTE_SPI1_DMA_RX_DMA_BASE, - RTE_SPI1_DMA_RX_CH}; - -static cmsis_spi_dma_handle_t SPI1_DmaHandle; -static dma_handle_t SPI1_DmaTxDataHandle; -static dma_handle_t SPI1_DmaRxDataHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi1_dma_driver_state") -static cmsis_spi_dma_driver_state_t SPI1_DMADriverState = { -#else -static cmsis_spi_dma_driver_state_t SPI1_DMADriverState = { -#endif - &SPI1_Resource, &SPI1_DMAResource, &SPI1_DmaHandle, &SPI1_DmaRxDataHandle, &SPI1_DmaTxDataHandle, -}; - -static int32_t SPI1_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI1_InitPins(); - return SPI_DMAInitialize(cb_event, &SPI1_DMADriverState); -} - -static int32_t SPI1_DMAUninitialize(void) -{ - SPI1_DeinitPins(); - return SPI_DMAUninitialize(&SPI1_DMADriverState); -} - -static int32_t SPI1_DMAPowerControl(ARM_POWER_STATE state) -{ - return SPI_DMAPowerControl(state, &SPI1_DMADriverState); -} - -static int32_t SPI1_DMASend(const void *data, uint32_t num) -{ - return SPI_DMASend(data, num, &SPI1_DMADriverState); -} - -static int32_t SPI1_DMAReceive(void *data, uint32_t num) -{ - return SPI_DMAReceive(data, num, &SPI1_DMADriverState); -} - -static int32_t SPI1_DMATransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_DMATransfer(data_out, data_in, num, &SPI1_DMADriverState); -} - -static uint32_t SPI1_DMAGetCount(void) -{ - return SPI_DMAGetCount(&SPI1_DMADriverState); -} - -static int32_t SPI1_DMAControl(uint32_t control, uint32_t arg) -{ - return SPI_DMAControl(control, arg, &SPI1_DMADriverState); -} - -static ARM_SPI_STATUS SPI1_DMAGetStatus(void) -{ - return SPI_DMAGetStatus(&SPI1_DMADriverState); -} - -#endif - -#else - -static cmsis_spi_handle_t SPI1_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi1_interrupt_driver_state") -static cmsis_spi_interrupt_driver_state_t SPI1_InterruptDriverState = { -#else -static cmsis_spi_interrupt_driver_state_t SPI1_InterruptDriverState = { -#endif - &SPI1_Resource, &SPI1_Handle, -}; - -static int32_t SPI1_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI1_InitPins(); - return SPI_InterruptInitialize(cb_event, &SPI1_InterruptDriverState); -} - -static int32_t SPI1_InterruptUninitialize(void) -{ - SPI1_DeinitPins(); - return SPI_InterruptUninitialize(&SPI1_InterruptDriverState); -} - -static int32_t SPI1_InterruptPowerControl(ARM_POWER_STATE state) -{ - return SPI_InterruptPowerControl(state, &SPI1_InterruptDriverState); -} - -static int32_t SPI1_InterruptSend(const void *data, uint32_t num) -{ - return SPI_InterruptSend(data, num, &SPI1_InterruptDriverState); -} - -static int32_t SPI1_InterruptReceive(void *data, uint32_t num) -{ - return SPI_InterruptReceive(data, num, &SPI1_InterruptDriverState); -} - -static int32_t SPI1_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_InterruptTransfer(data_out, data_in, num, &SPI1_InterruptDriverState); -} - -static uint32_t SPI1_InterruptGetCount(void) -{ - return SPI_InterruptGetCount(&SPI1_InterruptDriverState); -} - -static int32_t SPI1_InterruptControl(uint32_t control, uint32_t arg) -{ - return SPI_InterruptControl(control, arg, &SPI1_InterruptDriverState); -} - -static ARM_SPI_STATUS SPI1_InterruptGetStatus(void) -{ - return SPI_InterruptGetStatus(&SPI1_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI1 = {SPIx_GetVersion, SPIx_GetCapabilities, -#if RTE_SPI1_DMA_EN - SPI1_DMAInitialize, SPI1_DMAUninitialize, SPI1_DMAPowerControl, SPI1_DMASend, - SPI1_DMAReceive, SPI1_DMATransfer, SPI1_DMAGetCount, SPI1_DMAControl, - SPI1_DMAGetStatus -#else - SPI1_InterruptInitialize, SPI1_InterruptUninitialize, SPI1_InterruptPowerControl, - SPI1_InterruptSend, SPI1_InterruptReceive, SPI1_InterruptTransfer, SPI1_InterruptGetCount, - SPI1_InterruptControl, SPI1_InterruptGetStatus -#endif -}; - -#endif /* SPI1 */ - -#if defined(SPI2) && RTE_SPI2 - -/* User needs to provide the implementation for SPI2_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t SPI2_GetFreq(void); -extern void SPI2_InitPins(void); -extern void SPI2_DeinitPins(void); - -cmsis_spi_resource_t SPI2_Resource = {SPI2, 2, SPI2_GetFreq}; - -#if RTE_SPI2_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_spi_dma_resource_t SPI2_DMAResource = {RTE_SPI2_DMA_TX_DMA_BASE, RTE_SPI2_DMA_TX_CH, RTE_SPI2_DMA_RX_DMA_BASE, - RTE_SPI2_DMA_RX_CH}; - -static cmsis_spi_dma_handle_t SPI2_DmaHandle; -static dma_handle_t SPI2_DmaTxDataHandle; -static dma_handle_t SPI2_DmaRxDataHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi2_dma_driver_state") -static cmsis_spi_dma_driver_state_t SPI2_DMADriverState = { -#else -static cmsis_spi_dma_driver_state_t SPI2_DMADriverState = { -#endif - &SPI2_Resource, &SPI2_DMAResource, &SPI2_DmaHandle, &SPI2_DmaRxDataHandle, &SPI2_DmaTxDataHandle, -}; - -static int32_t SPI2_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI2_InitPins(); - return SPI_DMAInitialize(cb_event, &SPI2_DMADriverState); -} - -static int32_t SPI2_DMAUninitialize(void) -{ - SPI2_DeinitPins(); - return SPI_DMAUninitialize(&SPI2_DMADriverState); -} - -static int32_t SPI2_DMAPowerControl(ARM_POWER_STATE state) -{ - return SPI_DMAPowerControl(state, &SPI2_DMADriverState); -} - -static int32_t SPI2_DMASend(const void *data, uint32_t num) -{ - return SPI_DMASend(data, num, &SPI2_DMADriverState); -} - -static int32_t SPI2_DMAReceive(void *data, uint32_t num) -{ - return SPI_DMAReceive(data, num, &SPI2_DMADriverState); -} - -static int32_t SPI2_DMATransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_DMATransfer(data_out, data_in, num, &SPI2_DMADriverState); -} - -static uint32_t SPI2_DMAGetCount(void) -{ - return SPI_DMAGetCount(&SPI2_DMADriverState); -} - -static int32_t SPI2_DMAControl(uint32_t control, uint32_t arg) -{ - return SPI_DMAControl(control, arg, &SPI2_DMADriverState); -} - -static ARM_SPI_STATUS SPI2_DMAGetStatus(void) -{ - return SPI_DMAGetStatus(&SPI2_DMADriverState); -} - -#endif - -#else - -static cmsis_spi_handle_t SPI2_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi2_interrupt_driver_state") -static cmsis_spi_interrupt_driver_state_t SPI2_InterruptDriverState = { -#else -static cmsis_spi_interrupt_driver_state_t SPI2_InterruptDriverState = { -#endif - &SPI2_Resource, &SPI2_Handle, -}; - -static int32_t SPI2_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI2_InitPins(); - return SPI_InterruptInitialize(cb_event, &SPI2_InterruptDriverState); -} - -static int32_t SPI2_InterruptUninitialize(void) -{ - SPI2_DeinitPins(); - return SPI_InterruptUninitialize(&SPI2_InterruptDriverState); -} - -static int32_t SPI2_InterruptPowerControl(ARM_POWER_STATE state) -{ - return SPI_InterruptPowerControl(state, &SPI2_InterruptDriverState); -} - -static int32_t SPI2_InterruptSend(const void *data, uint32_t num) -{ - return SPI_InterruptSend(data, num, &SPI2_InterruptDriverState); -} - -static int32_t SPI2_InterruptReceive(void *data, uint32_t num) -{ - return SPI_InterruptReceive(data, num, &SPI2_InterruptDriverState); -} - -static int32_t SPI2_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_InterruptTransfer(data_out, data_in, num, &SPI2_InterruptDriverState); -} - -static uint32_t SPI2_InterruptGetCount(void) -{ - return SPI_InterruptGetCount(&SPI2_InterruptDriverState); -} - -static int32_t SPI2_InterruptControl(uint32_t control, uint32_t arg) -{ - return SPI_InterruptControl(control, arg, &SPI2_InterruptDriverState); -} - -static ARM_SPI_STATUS SPI2_InterruptGetStatus(void) -{ - return SPI_InterruptGetStatus(&SPI2_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI2 = {SPIx_GetVersion, SPIx_GetCapabilities, -#if RTE_SPI2_DMA_EN - SPI2_DMAInitialize, SPI2_DMAUninitialize, SPI2_DMAPowerControl, SPI2_DMASend, - SPI2_DMAReceive, SPI2_DMATransfer, SPI2_DMAGetCount, SPI2_DMAControl, - SPI2_DMAGetStatus -#else - SPI2_InterruptInitialize, SPI2_InterruptUninitialize, SPI2_InterruptPowerControl, - SPI2_InterruptSend, SPI2_InterruptReceive, SPI2_InterruptTransfer, SPI2_InterruptGetCount, - SPI2_InterruptControl, SPI2_InterruptGetStatus -#endif -}; - -#endif /* SPI2 */ - -#if defined(SPI3) && RTE_SPI3 - -/* User needs to provide the implementation for SPI3_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t SPI3_GetFreq(void); -extern void SPI3_InitPins(void); -extern void SPI3_DeinitPins(void); - -cmsis_spi_resource_t SPI3_Resource = {SPI3, 3, SPI3_GetFreq}; - -#if RTE_SPI3_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_spi_dma_resource_t SPI3_DMAResource = {RTE_SPI3_DMA_TX_DMA_BASE, RTE_SPI3_DMA_TX_CH, RTE_SPI3_DMA_RX_DMA_BASE, - RTE_SPI3_DMA_RX_CH}; - -static cmsis_spi_dma_handle_t SPI3_DmaHandle; -static dma_handle_t SPI3_DmaTxDataHandle; -static dma_handle_t SPI3_DmaRxDataHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi3_dma_driver_state") -static cmsis_spi_dma_driver_state_t SPI3_DMADriverState = { -#else -static cmsis_spi_dma_driver_state_t SPI3_DMADriverState = { -#endif - &SPI3_Resource, &SPI3_DMAResource, &SPI3_DmaHandle, &SPI3_DmaRxDataHandle, &SPI3_DmaTxDataHandle, -}; - -static int32_t SPI3_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI3_InitPins(); - return SPI_DMAInitialize(cb_event, &SPI3_DMADriverState); -} - -static int32_t SPI3_DMAUninitialize(void) -{ - SPI3_DeinitPins(); - return SPI_DMAUninitialize(&SPI3_DMADriverState); -} - -static int32_t SPI3_DMAPowerControl(ARM_POWER_STATE state) -{ - return SPI_DMAPowerControl(state, &SPI3_DMADriverState); -} - -static int32_t SPI3_DMASend(const void *data, uint32_t num) -{ - return SPI_DMASend(data, num, &SPI3_DMADriverState); -} - -static int32_t SPI3_DMAReceive(void *data, uint32_t num) -{ - return SPI_DMAReceive(data, num, &SPI3_DMADriverState); -} - -static int32_t SPI3_DMATransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_DMATransfer(data_out, data_in, num, &SPI3_DMADriverState); -} - -static uint32_t SPI3_DMAGetCount(void) -{ - return SPI_DMAGetCount(&SPI3_DMADriverState); -} - -static int32_t SPI3_DMAControl(uint32_t control, uint32_t arg) -{ - return SPI_DMAControl(control, arg, &SPI3_DMADriverState); -} - -static ARM_SPI_STATUS SPI3_DMAGetStatus(void) -{ - return SPI_DMAGetStatus(&SPI3_DMADriverState); -} - -#endif - -#else - -static cmsis_spi_handle_t SPI3_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi3_interrupt_driver_state") -static cmsis_spi_interrupt_driver_state_t SPI3_InterruptDriverState = { -#else -static cmsis_spi_interrupt_driver_state_t SPI3_InterruptDriverState = { -#endif - &SPI3_Resource, &SPI3_Handle, -}; - -static int32_t SPI3_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI3_InitPins(); - return SPI_InterruptInitialize(cb_event, &SPI3_InterruptDriverState); -} - -static int32_t SPI3_InterruptUninitialize(void) -{ - SPI3_DeinitPins(); - return SPI_InterruptUninitialize(&SPI3_InterruptDriverState); -} - -static int32_t SPI3_InterruptPowerControl(ARM_POWER_STATE state) -{ - return SPI_InterruptPowerControl(state, &SPI3_InterruptDriverState); -} - -static int32_t SPI3_InterruptSend(const void *data, uint32_t num) -{ - return SPI_InterruptSend(data, num, &SPI3_InterruptDriverState); -} - -static int32_t SPI3_InterruptReceive(void *data, uint32_t num) -{ - return SPI_InterruptReceive(data, num, &SPI3_InterruptDriverState); -} - -static int32_t SPI3_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_InterruptTransfer(data_out, data_in, num, &SPI3_InterruptDriverState); -} - -static uint32_t SPI3_InterruptGetCount(void) -{ - return SPI_InterruptGetCount(&SPI3_InterruptDriverState); -} - -static int32_t SPI3_InterruptControl(uint32_t control, uint32_t arg) -{ - return SPI_InterruptControl(control, arg, &SPI3_InterruptDriverState); -} - -static ARM_SPI_STATUS SPI3_InterruptGetStatus(void) -{ - return SPI_InterruptGetStatus(&SPI3_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI3 = {SPIx_GetVersion, SPIx_GetCapabilities, -#if RTE_SPI3_DMA_EN - SPI3_DMAInitialize, SPI3_DMAUninitialize, SPI3_DMAPowerControl, SPI3_DMASend, - SPI3_DMAReceive, SPI3_DMATransfer, SPI3_DMAGetCount, SPI3_DMAControl, - SPI3_DMAGetStatus -#else - SPI3_InterruptInitialize, SPI3_InterruptUninitialize, SPI3_InterruptPowerControl, - SPI3_InterruptSend, SPI3_InterruptReceive, SPI3_InterruptTransfer, SPI3_InterruptGetCount, - SPI3_InterruptControl, SPI3_InterruptGetStatus -#endif -}; - -#endif /* SPI3 */ - -#if defined(SPI4) && RTE_SPI4 - -/* User needs to provide the implementation for SPI4_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t SPI4_GetFreq(void); -extern void SPI4_InitPins(void); -extern void SPI4_DeinitPins(void); - -cmsis_spi_resource_t SPI4_Resource = {SPI4, 4, SPI4_GetFreq}; - -#if RTE_SPI4_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_spi_dma_resource_t SPI4_DMAResource = {RTE_SPI4_DMA_TX_DMA_BASE, RTE_SPI4_DMA_TX_CH, RTE_SPI4_DMA_RX_DMA_BASE, - RTE_SPI4_DMA_RX_CH}; - -static cmsis_spi_dma_handle_t SPI4_DmaHandle; -static dma_handle_t SPI4_DmaTxDataHandle; -static dma_handle_t SPI4_DmaRxDataHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi4_dma_driver_state") -static cmsis_spi_dma_driver_state_t SPI4_DMADriverState = { -#else -static cmsis_spi_dma_driver_state_t SPI4_DMADriverState = { -#endif - &SPI4_Resource, &SPI4_DMAResource, &SPI4_DmaHandle, &SPI4_DmaRxDataHandle, &SPI4_DmaTxDataHandle, -}; - -static int32_t SPI4_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI4_InitPins(); - return SPI_DMAInitialize(cb_event, &SPI4_DMADriverState); -} - -static int32_t SPI4_DMAUninitialize(void) -{ - SPI4_DeinitPins(); - return SPI_DMAUninitialize(&SPI4_DMADriverState); -} - -static int32_t SPI4_DMAPowerControl(ARM_POWER_STATE state) -{ - return SPI_DMAPowerControl(state, &SPI4_DMADriverState); -} - -static int32_t SPI4_DMASend(const void *data, uint32_t num) -{ - return SPI_DMASend(data, num, &SPI4_DMADriverState); -} - -static int32_t SPI4_DMAReceive(void *data, uint32_t num) -{ - return SPI_DMAReceive(data, num, &SPI4_DMADriverState); -} - -static int32_t SPI4_DMATransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_DMATransfer(data_out, data_in, num, &SPI4_DMADriverState); -} - -static uint32_t SPI4_DMAGetCount(void) -{ - return SPI_DMAGetCount(&SPI4_DMADriverState); -} - -static int32_t SPI4_DMAControl(uint32_t control, uint32_t arg) -{ - return SPI_DMAControl(control, arg, &SPI4_DMADriverState); -} - -static ARM_SPI_STATUS SPI4_DMAGetStatus(void) -{ - return SPI_DMAGetStatus(&SPI4_DMADriverState); -} - -#endif - -#else - -static cmsis_spi_handle_t SPI4_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi4_interrupt_driver_state") -static cmsis_spi_interrupt_driver_state_t SPI4_InterruptDriverState = { -#else -static cmsis_spi_interrupt_driver_state_t SPI4_InterruptDriverState = { -#endif - &SPI4_Resource, &SPI4_Handle, -}; - -static int32_t SPI4_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI4_InitPins(); - return SPI_InterruptInitialize(cb_event, &SPI4_InterruptDriverState); -} - -static int32_t SPI4_InterruptUninitialize(void) -{ - SPI4_DeinitPins(); - return SPI_InterruptUninitialize(&SPI4_InterruptDriverState); -} - -static int32_t SPI4_InterruptPowerControl(ARM_POWER_STATE state) -{ - return SPI_InterruptPowerControl(state, &SPI4_InterruptDriverState); -} - -static int32_t SPI4_InterruptSend(const void *data, uint32_t num) -{ - return SPI_InterruptSend(data, num, &SPI4_InterruptDriverState); -} - -static int32_t SPI4_InterruptReceive(void *data, uint32_t num) -{ - return SPI_InterruptReceive(data, num, &SPI4_InterruptDriverState); -} - -static int32_t SPI4_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_InterruptTransfer(data_out, data_in, num, &SPI4_InterruptDriverState); -} - -static uint32_t SPI4_InterruptGetCount(void) -{ - return SPI_InterruptGetCount(&SPI4_InterruptDriverState); -} - -static int32_t SPI4_InterruptControl(uint32_t control, uint32_t arg) -{ - return SPI_InterruptControl(control, arg, &SPI4_InterruptDriverState); -} - -static ARM_SPI_STATUS SPI4_InterruptGetStatus(void) -{ - return SPI_InterruptGetStatus(&SPI4_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI4 = {SPIx_GetVersion, SPIx_GetCapabilities, -#if RTE_SPI4_DMA_EN - SPI4_DMAInitialize, SPI4_DMAUninitialize, SPI4_DMAPowerControl, SPI4_DMASend, - SPI4_DMAReceive, SPI4_DMATransfer, SPI4_DMAGetCount, SPI4_DMAControl, - SPI4_DMAGetStatus -#else - SPI4_InterruptInitialize, SPI4_InterruptUninitialize, SPI4_InterruptPowerControl, - SPI4_InterruptSend, SPI4_InterruptReceive, SPI4_InterruptTransfer, SPI4_InterruptGetCount, - SPI4_InterruptControl, SPI4_InterruptGetStatus -#endif -}; - -#endif /* SPI4 */ - -#if defined(SPI5) && RTE_SPI5 - -/* User needs to provide the implementation for SPI5_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t SPI5_GetFreq(void); -extern void SPI5_InitPins(void); -extern void SPI5_DeinitPins(void); - -cmsis_spi_resource_t SPI5_Resource = {SPI5, 5, SPI5_GetFreq}; - -#if RTE_SPI5_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_spi_dma_resource_t SPI5_DMAResource = {RTE_SPI5_DMA_TX_DMA_BASE, RTE_SPI5_DMA_TX_CH, RTE_SPI5_DMA_RX_DMA_BASE, - RTE_SPI5_DMA_RX_CH}; - -static cmsis_spi_dma_handle_t SPI5_DmaHandle; -static dma_handle_t SPI5_DmaTxDataHandle; -static dma_handle_t SPI5_DmaRxDataHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi5_dma_driver_state") -static cmsis_spi_dma_driver_state_t SPI5_DMADriverState = { -#else -static cmsis_spi_dma_driver_state_t SPI5_DMADriverState = { -#endif - &SPI5_Resource, &SPI5_DMAResource, &SPI5_DmaHandle, &SPI5_DmaRxDataHandle, &SPI5_DmaTxDataHandle, -}; - -static int32_t SPI5_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI5_InitPins(); - return SPI_DMAInitialize(cb_event, &SPI5_DMADriverState); -} - -static int32_t SPI5_DMAUninitialize(void) -{ - SPI5_DeinitPins(); - return SPI_DMAUninitialize(&SPI5_DMADriverState); -} - -static int32_t SPI5_DMAPowerControl(ARM_POWER_STATE state) -{ - return SPI_DMAPowerControl(state, &SPI5_DMADriverState); -} - -static int32_t SPI5_DMASend(const void *data, uint32_t num) -{ - return SPI_DMASend(data, num, &SPI5_DMADriverState); -} - -static int32_t SPI5_DMAReceive(void *data, uint32_t num) -{ - return SPI_DMAReceive(data, num, &SPI5_DMADriverState); -} - -static int32_t SPI5_DMATransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_DMATransfer(data_out, data_in, num, &SPI5_DMADriverState); -} - -static uint32_t SPI5_DMAGetCount(void) -{ - return SPI_DMAGetCount(&SPI5_DMADriverState); -} - -static int32_t SPI5_DMAControl(uint32_t control, uint32_t arg) -{ - return SPI_DMAControl(control, arg, &SPI5_DMADriverState); -} - -static ARM_SPI_STATUS SPI5_DMAGetStatus(void) -{ - return SPI_DMAGetStatus(&SPI5_DMADriverState); -} - -#endif - -#else - -static cmsis_spi_handle_t SPI5_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi5_interrupt_driver_state") -static cmsis_spi_interrupt_driver_state_t SPI5_InterruptDriverState = { -#else -static cmsis_spi_interrupt_driver_state_t SPI5_InterruptDriverState = { -#endif - &SPI5_Resource, &SPI5_Handle, -}; - -static int32_t SPI5_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI5_InitPins(); - return SPI_InterruptInitialize(cb_event, &SPI5_InterruptDriverState); -} - -static int32_t SPI5_InterruptUninitialize(void) -{ - SPI5_DeinitPins(); - return SPI_InterruptUninitialize(&SPI5_InterruptDriverState); -} - -static int32_t SPI5_InterruptPowerControl(ARM_POWER_STATE state) -{ - return SPI_InterruptPowerControl(state, &SPI5_InterruptDriverState); -} - -static int32_t SPI5_InterruptSend(const void *data, uint32_t num) -{ - return SPI_InterruptSend(data, num, &SPI5_InterruptDriverState); -} - -static int32_t SPI5_InterruptReceive(void *data, uint32_t num) -{ - return SPI_InterruptReceive(data, num, &SPI5_InterruptDriverState); -} - -static int32_t SPI5_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_InterruptTransfer(data_out, data_in, num, &SPI5_InterruptDriverState); -} - -static uint32_t SPI5_InterruptGetCount(void) -{ - return SPI_InterruptGetCount(&SPI5_InterruptDriverState); -} - -static int32_t SPI5_InterruptControl(uint32_t control, uint32_t arg) -{ - return SPI_InterruptControl(control, arg, &SPI5_InterruptDriverState); -} - -static ARM_SPI_STATUS SPI5_InterruptGetStatus(void) -{ - return SPI_InterruptGetStatus(&SPI5_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI5 = {SPIx_GetVersion, SPIx_GetCapabilities, -#if RTE_SPI5_DMA_EN - SPI5_DMAInitialize, SPI5_DMAUninitialize, SPI5_DMAPowerControl, SPI5_DMASend, - SPI5_DMAReceive, SPI5_DMATransfer, SPI5_DMAGetCount, SPI5_DMAControl, - SPI5_DMAGetStatus -#else - SPI5_InterruptInitialize, SPI5_InterruptUninitialize, SPI5_InterruptPowerControl, - SPI5_InterruptSend, SPI5_InterruptReceive, SPI5_InterruptTransfer, SPI5_InterruptGetCount, - SPI5_InterruptControl, SPI5_InterruptGetStatus -#endif -}; - -#endif /* SPI5 */ - -#if defined(SPI6) && RTE_SPI6 - -/* User needs to provide the implementation for SPI6_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t SPI6_GetFreq(void); -extern void SPI6_InitPins(void); -extern void SPI6_DeinitPins(void); - -cmsis_spi_resource_t SPI6_Resource = {SPI6, 6, SPI6_GetFreq}; - -#if RTE_SPI6_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_spi_dma_resource_t SPI6_DMAResource = {RTE_SPI6_DMA_TX_DMA_BASE, RTE_SPI6_DMA_TX_CH, RTE_SPI6_DMA_RX_DMA_BASE, - RTE_SPI6_DMA_RX_CH}; - -static cmsis_spi_dma_handle_t SPI6_DmaHandle; -static dma_handle_t SPI6_DmaTxDataHandle; -static dma_handle_t SPI6_DmaRxDataHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi6_dma_driver_state") -static cmsis_spi_dma_driver_state_t SPI6_DMADriverState = { -#else -static cmsis_spi_dma_driver_state_t SPI6_DMADriverState = { -#endif - &SPI6_Resource, &SPI6_DMAResource, &SPI6_DmaHandle, &SPI6_DmaRxDataHandle, &SPI6_DmaTxDataHandle, -}; - -static int32_t SPI6_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI6_InitPins(); - return SPI_DMAInitialize(cb_event, &SPI6_DMADriverState); -} - -static int32_t SPI6_DMAUninitialize(void) -{ - SPI6_DeinitPins(); - return SPI_DMAUninitialize(&SPI6_DMADriverState); -} - -static int32_t SPI6_DMAPowerControl(ARM_POWER_STATE state) -{ - return SPI_DMAPowerControl(state, &SPI6_DMADriverState); -} - -static int32_t SPI6_DMASend(const void *data, uint32_t num) -{ - return SPI_DMASend(data, num, &SPI6_DMADriverState); -} - -static int32_t SPI6_DMAReceive(void *data, uint32_t num) -{ - return SPI_DMAReceive(data, num, &SPI6_DMADriverState); -} - -static int32_t SPI6_DMATransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_DMATransfer(data_out, data_in, num, &SPI6_DMADriverState); -} - -static uint32_t SPI6_DMAGetCount(void) -{ - return SPI_DMAGetCount(&SPI6_DMADriverState); -} - -static int32_t SPI6_DMAControl(uint32_t control, uint32_t arg) -{ - return SPI_DMAControl(control, arg, &SPI6_DMADriverState); -} - -static ARM_SPI_STATUS SPI6_DMAGetStatus(void) -{ - return SPI_DMAGetStatus(&SPI6_DMADriverState); -} - -#endif - -#else - -static cmsis_spi_handle_t SPI6_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi6_interrupt_driver_state") -static cmsis_spi_interrupt_driver_state_t SPI6_InterruptDriverState = { -#else -static cmsis_spi_interrupt_driver_state_t SPI6_InterruptDriverState = { -#endif - &SPI6_Resource, &SPI6_Handle, -}; - -static int32_t SPI6_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI6_InitPins(); - return SPI_InterruptInitialize(cb_event, &SPI6_InterruptDriverState); -} - -static int32_t SPI6_InterruptUninitialize(void) -{ - SPI6_DeinitPins(); - return SPI_InterruptUninitialize(&SPI6_InterruptDriverState); -} - -static int32_t SPI6_InterruptPowerControl(ARM_POWER_STATE state) -{ - return SPI_InterruptPowerControl(state, &SPI6_InterruptDriverState); -} - -static int32_t SPI6_InterruptSend(const void *data, uint32_t num) -{ - return SPI_InterruptSend(data, num, &SPI6_InterruptDriverState); -} - -static int32_t SPI6_InterruptReceive(void *data, uint32_t num) -{ - return SPI_InterruptReceive(data, num, &SPI6_InterruptDriverState); -} - -static int32_t SPI6_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_InterruptTransfer(data_out, data_in, num, &SPI6_InterruptDriverState); -} - -static uint32_t SPI6_InterruptGetCount(void) -{ - return SPI_InterruptGetCount(&SPI6_InterruptDriverState); -} - -static int32_t SPI6_InterruptControl(uint32_t control, uint32_t arg) -{ - return SPI_InterruptControl(control, arg, &SPI6_InterruptDriverState); -} - -static ARM_SPI_STATUS SPI6_InterruptGetStatus(void) -{ - return SPI_InterruptGetStatus(&SPI6_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI6 = {SPIx_GetVersion, SPIx_GetCapabilities, -#if RTE_SPI6_DMA_EN - SPI6_DMAInitialize, SPI6_DMAUninitialize, SPI6_DMAPowerControl, SPI6_DMASend, - SPI6_DMAReceive, SPI6_DMATransfer, SPI6_DMAGetCount, SPI6_DMAControl, - SPI6_DMAGetStatus -#else - SPI6_InterruptInitialize, SPI6_InterruptUninitialize, SPI6_InterruptPowerControl, - SPI6_InterruptSend, SPI6_InterruptReceive, SPI6_InterruptTransfer, SPI6_InterruptGetCount, - SPI6_InterruptControl, SPI6_InterruptGetStatus -#endif -}; - -#endif /* SPI6 */ - -#if defined(SPI7) && RTE_SPI7 - -/* User needs to provide the implementation for SPI7_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t SPI7_GetFreq(void); -extern void SPI7_InitPins(void); -extern void SPI7_DeinitPins(void); - -cmsis_spi_resource_t SPI7_Resource = {SPI7, 7, SPI7_GetFreq}; - -#if RTE_SPI7_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_spi_dma_resource_t SPI7_DMAResource = {RTE_SPI7_DMA_TX_DMA_BASE, RTE_SPI7_DMA_TX_CH, RTE_SPI7_DMA_RX_DMA_BASE, - RTE_SPI7_DMA_RX_CH}; - -static cmsis_spi_dma_handle_t SPI7_DmaHandle; -static dma_handle_t SPI7_DmaTxDataHandle; -static dma_handle_t SPI7_DmaRxDataHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi7_dma_driver_state") -static cmsis_spi_dma_driver_state_t SPI7_DMADriverState = { -#else -static cmsis_spi_dma_driver_state_t SPI7_DMADriverState = { -#endif - &SPI7_Resource, &SPI7_DMAResource, &SPI7_DmaHandle, &SPI7_DmaRxDataHandle, &SPI7_DmaTxDataHandle, -}; - -static int32_t SPI7_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI7_InitPins(); - return SPI_DMAInitialize(cb_event, &SPI7_DMADriverState); -} - -static int32_t SPI7_DMAUninitialize(void) -{ - SPI7_DeinitPins(); - return SPI_DMAUninitialize(&SPI7_DMADriverState); -} - -static int32_t SPI7_DMAPowerControl(ARM_POWER_STATE state) -{ - return SPI_DMAPowerControl(state, &SPI7_DMADriverState); -} - -static int32_t SPI7_DMASend(const void *data, uint32_t num) -{ - return SPI_DMASend(data, num, &SPI7_DMADriverState); -} - -static int32_t SPI7_DMAReceive(void *data, uint32_t num) -{ - return SPI_DMAReceive(data, num, &SPI7_DMADriverState); -} - -static int32_t SPI7_DMATransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_DMATransfer(data_out, data_in, num, &SPI7_DMADriverState); -} - -static uint32_t SPI7_DMAGetCount(void) -{ - return SPI_DMAGetCount(&SPI7_DMADriverState); -} - -static int32_t SPI7_DMAControl(uint32_t control, uint32_t arg) -{ - return SPI_DMAControl(control, arg, &SPI7_DMADriverState); -} - -static ARM_SPI_STATUS SPI7_DMAGetStatus(void) -{ - return SPI_DMAGetStatus(&SPI7_DMADriverState); -} - -#endif - -#else - -static cmsis_spi_handle_t SPI7_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi7_interrupt_driver_state") -static cmsis_spi_interrupt_driver_state_t SPI7_InterruptDriverState = { -#else -static cmsis_spi_interrupt_driver_state_t SPI7_InterruptDriverState = { -#endif - &SPI7_Resource, &SPI7_Handle, -}; - -static int32_t SPI7_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI7_InitPins(); - return SPI_InterruptInitialize(cb_event, &SPI7_InterruptDriverState); -} - -static int32_t SPI7_InterruptUninitialize(void) -{ - SPI7_DeinitPins(); - return SPI_InterruptUninitialize(&SPI7_InterruptDriverState); -} - -static int32_t SPI7_InterruptPowerControl(ARM_POWER_STATE state) -{ - return SPI_InterruptPowerControl(state, &SPI7_InterruptDriverState); -} - -static int32_t SPI7_InterruptSend(const void *data, uint32_t num) -{ - return SPI_InterruptSend(data, num, &SPI7_InterruptDriverState); -} - -static int32_t SPI7_InterruptReceive(void *data, uint32_t num) -{ - return SPI_InterruptReceive(data, num, &SPI7_InterruptDriverState); -} - -static int32_t SPI7_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_InterruptTransfer(data_out, data_in, num, &SPI7_InterruptDriverState); -} - -static uint32_t SPI7_InterruptGetCount(void) -{ - return SPI_InterruptGetCount(&SPI7_InterruptDriverState); -} - -static int32_t SPI7_InterruptControl(uint32_t control, uint32_t arg) -{ - return SPI_InterruptControl(control, arg, &SPI7_InterruptDriverState); -} - -static ARM_SPI_STATUS SPI7_InterruptGetStatus(void) -{ - return SPI_InterruptGetStatus(&SPI7_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI7 = {SPIx_GetVersion, SPIx_GetCapabilities, -#if RTE_SPI7_DMA_EN - SPI7_DMAInitialize, SPI7_DMAUninitialize, SPI7_DMAPowerControl, SPI7_DMASend, - SPI7_DMAReceive, SPI7_DMATransfer, SPI7_DMAGetCount, SPI7_DMAControl, - SPI7_DMAGetStatus -#else - SPI7_InterruptInitialize, SPI7_InterruptUninitialize, SPI7_InterruptPowerControl, - SPI7_InterruptSend, SPI7_InterruptReceive, SPI7_InterruptTransfer, SPI7_InterruptGetCount, - SPI7_InterruptControl, SPI7_InterruptGetStatus -#endif -}; - -#endif /* SPI7 */ - -#if defined(SPI8) && RTE_SPI8 - -/* User needs to provide the implementation for SPI8_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t SPI8_GetFreq(void); -extern void SPI8_InitPins(void); -extern void SPI8_DeinitPins(void); - -cmsis_spi_resource_t SPI8_Resource = {SPI8, 8, SPI8_GetFreq}; - -#if RTE_SPI8_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_spi_dma_resource_t SPI8_DMAResource = {RTE_SPI8_DMA_TX_DMA_BASE, RTE_SPI8_DMA_TX_CH, RTE_SPI8_DMA_RX_DMA_BASE, - RTE_SPI8_DMA_RX_CH}; - -static cmsis_spi_dma_handle_t SPI8_DmaHandle; -static dma_handle_t SPI8_DmaTxDataHandle; -static dma_handle_t SPI8_DmaRxDataHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi8_dma_driver_state") -static cmsis_spi_dma_driver_state_t SPI8_DMADriverState = { -#else -static cmsis_spi_dma_driver_state_t SPI8_DMADriverState = { -#endif - &SPI8_Resource, &SPI8_DMAResource, &SPI8_DmaHandle, &SPI8_DmaRxDataHandle, &SPI8_DmaTxDataHandle, -}; - -static int32_t SPI8_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI8_InitPins(); - return SPI_DMAInitialize(cb_event, &SPI8_DMADriverState); -} - -static int32_t SPI8_DMAUninitialize(void) -{ - SPI8_DeinitPins(); - return SPI_DMAUninitialize(&SPI8_DMADriverState); -} - -static int32_t SPI8_DMAPowerControl(ARM_POWER_STATE state) -{ - return SPI_DMAPowerControl(state, &SPI8_DMADriverState); -} - -static int32_t SPI8_DMASend(const void *data, uint32_t num) -{ - return SPI_DMASend(data, num, &SPI8_DMADriverState); -} - -static int32_t SPI8_DMAReceive(void *data, uint32_t num) -{ - return SPI_DMAReceive(data, num, &SPI8_DMADriverState); -} - -static int32_t SPI8_DMATransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_DMATransfer(data_out, data_in, num, &SPI8_DMADriverState); -} - -static uint32_t SPI8_DMAGetCount(void) -{ - return SPI_DMAGetCount(&SPI8_DMADriverState); -} - -static int32_t SPI8_DMAControl(uint32_t control, uint32_t arg) -{ - return SPI_DMAControl(control, arg, &SPI8_DMADriverState); -} - -static ARM_SPI_STATUS SPI8_DMAGetStatus(void) -{ - return SPI_DMAGetStatus(&SPI8_DMADriverState); -} - -#endif - -#else - -static cmsis_spi_handle_t SPI8_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi8_interrupt_driver_state") -static cmsis_spi_interrupt_driver_state_t SPI8_InterruptDriverState = { -#else -static cmsis_spi_interrupt_driver_state_t SPI8_InterruptDriverState = { -#endif - &SPI8_Resource, &SPI8_Handle, -}; - -static int32_t SPI8_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI8_InitPins(); - return SPI_InterruptInitialize(cb_event, &SPI8_InterruptDriverState); -} - -static int32_t SPI8_InterruptUninitialize(void) -{ - SPI8_DeinitPins(); - return SPI_InterruptUninitialize(&SPI8_InterruptDriverState); -} - -static int32_t SPI8_InterruptPowerControl(ARM_POWER_STATE state) -{ - return SPI_InterruptPowerControl(state, &SPI8_InterruptDriverState); -} - -static int32_t SPI8_InterruptSend(const void *data, uint32_t num) -{ - return SPI_InterruptSend(data, num, &SPI8_InterruptDriverState); -} - -static int32_t SPI8_InterruptReceive(void *data, uint32_t num) -{ - return SPI_InterruptReceive(data, num, &SPI8_InterruptDriverState); -} - -static int32_t SPI8_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_InterruptTransfer(data_out, data_in, num, &SPI8_InterruptDriverState); -} - -static uint32_t SPI8_InterruptGetCount(void) -{ - return SPI_InterruptGetCount(&SPI8_InterruptDriverState); -} - -static int32_t SPI8_InterruptControl(uint32_t control, uint32_t arg) -{ - return SPI_InterruptControl(control, arg, &SPI8_InterruptDriverState); -} - -static ARM_SPI_STATUS SPI8_InterruptGetStatus(void) -{ - return SPI_InterruptGetStatus(&SPI8_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI8 = {SPIx_GetVersion, SPIx_GetCapabilities, -#if RTE_SPI8_DMA_EN - SPI8_DMAInitialize, SPI8_DMAUninitialize, SPI8_DMAPowerControl, SPI8_DMASend, - SPI8_DMAReceive, SPI8_DMATransfer, SPI8_DMAGetCount, SPI8_DMAControl, - SPI8_DMAGetStatus -#else - SPI8_InterruptInitialize, SPI8_InterruptUninitialize, SPI8_InterruptPowerControl, - SPI8_InterruptSend, SPI8_InterruptReceive, SPI8_InterruptTransfer, SPI8_InterruptGetCount, - SPI8_InterruptControl, SPI8_InterruptGetStatus -#endif -}; - -#endif /* SPI8 */ - -#if defined(SPI9) && RTE_SPI9 - -/* User needs to provide the implementation for SPI9_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t SPI9_GetFreq(void); -extern void SPI9_InitPins(void); -extern void SPI9_DeinitPins(void); - -cmsis_spi_resource_t SPI9_Resource = {SPI9, 9, SPI9_GetFreq}; - -#if RTE_SPI9_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_spi_dma_resource_t SPI9_DMAResource = {RTE_SPI9_DMA_TX_DMA_BASE, RTE_SPI9_DMA_TX_CH, RTE_SPI9_DMA_RX_DMA_BASE, - RTE_SPI9_DMA_RX_CH}; - -static cmsis_spi_dma_handle_t SPI9_DmaHandle; -static dma_handle_t SPI9_DmaTxDataHandle; -static dma_handle_t SPI9_DmaRxDataHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi9_dma_driver_state") -static cmsis_spi_dma_driver_state_t SPI9_DMADriverState = { -#else -static cmsis_spi_dma_driver_state_t SPI9_DMADriverState = { -#endif - &SPI9_Resource, &SPI9_DMAResource, &SPI9_DmaHandle, &SPI9_DmaRxDataHandle, &SPI9_DmaTxDataHandle, -}; - -static int32_t SPI9_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI9_InitPins(); - return SPI_DMAInitialize(cb_event, &SPI9_DMADriverState); -} - -static int32_t SPI9_DMAUninitialize(void) -{ - SPI9_DeinitPins(); - return SPI_DMAUninitialize(&SPI9_DMADriverState); -} - -static int32_t SPI9_DMAPowerControl(ARM_POWER_STATE state) -{ - return SPI_DMAPowerControl(state, &SPI9_DMADriverState); -} - -static int32_t SPI9_DMASend(const void *data, uint32_t num) -{ - return SPI_DMASend(data, num, &SPI9_DMADriverState); -} - -static int32_t SPI9_DMAReceive(void *data, uint32_t num) -{ - return SPI_DMAReceive(data, num, &SPI9_DMADriverState); -} - -static int32_t SPI9_DMATransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_DMATransfer(data_out, data_in, num, &SPI9_DMADriverState); -} - -static uint32_t SPI9_DMAGetCount(void) -{ - return SPI_DMAGetCount(&SPI9_DMADriverState); -} - -static int32_t SPI9_DMAControl(uint32_t control, uint32_t arg) -{ - return SPI_DMAControl(control, arg, &SPI9_DMADriverState); -} - -static ARM_SPI_STATUS SPI9_DMAGetStatus(void) -{ - return SPI_DMAGetStatus(&SPI9_DMADriverState); -} - -#endif - -#else - -static cmsis_spi_handle_t SPI9_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("spi9_interrupt_driver_state") -static cmsis_spi_interrupt_driver_state_t SPI9_InterruptDriverState = { -#else -static cmsis_spi_interrupt_driver_state_t SPI9_InterruptDriverState = { -#endif - &SPI9_Resource, &SPI9_Handle, -}; - -static int32_t SPI9_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - SPI9_InitPins(); - return SPI_InterruptInitialize(cb_event, &SPI9_InterruptDriverState); -} - -static int32_t SPI9_InterruptUninitialize(void) -{ - SPI9_DeinitPins(); - return SPI_InterruptUninitialize(&SPI9_InterruptDriverState); -} - -static int32_t SPI9_InterruptPowerControl(ARM_POWER_STATE state) -{ - return SPI_InterruptPowerControl(state, &SPI9_InterruptDriverState); -} - -static int32_t SPI9_InterruptSend(const void *data, uint32_t num) -{ - return SPI_InterruptSend(data, num, &SPI9_InterruptDriverState); -} - -static int32_t SPI9_InterruptReceive(void *data, uint32_t num) -{ - return SPI_InterruptReceive(data, num, &SPI9_InterruptDriverState); -} - -static int32_t SPI9_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return SPI_InterruptTransfer(data_out, data_in, num, &SPI9_InterruptDriverState); -} - -static uint32_t SPI9_InterruptGetCount(void) -{ - return SPI_InterruptGetCount(&SPI9_InterruptDriverState); -} - -static int32_t SPI9_InterruptControl(uint32_t control, uint32_t arg) -{ - return SPI_InterruptControl(control, arg, &SPI9_InterruptDriverState); -} - -static ARM_SPI_STATUS SPI9_InterruptGetStatus(void) -{ - return SPI_InterruptGetStatus(&SPI9_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI9 = {SPIx_GetVersion, SPIx_GetCapabilities, -#if RTE_SPI9_DMA_EN - SPI9_DMAInitialize, SPI9_DMAUninitialize, SPI9_DMAPowerControl, SPI9_DMASend, - SPI9_DMAReceive, SPI9_DMATransfer, SPI9_DMAGetCount, SPI9_DMAControl, - SPI9_DMAGetStatus -#else - SPI9_InterruptInitialize, SPI9_InterruptUninitialize, SPI9_InterruptPowerControl, - SPI9_InterruptSend, SPI9_InterruptReceive, SPI9_InterruptTransfer, SPI9_InterruptGetCount, - SPI9_InterruptControl, SPI9_InterruptGetStatus -#endif -}; - -#endif /* SPI9 */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/cmsis_drivers/fsl_spi_cmsis.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/cmsis_drivers/fsl_spi_cmsis.h deleted file mode 100644 index 8f2c40ea254..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/cmsis_drivers/fsl_spi_cmsis.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2013-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_SPI_CMSIS_H_ -#define _FSL_SPI_CMSIS_H_ - -#include "fsl_spi.h" -#include "RTE_Device.h" -#include "Driver_SPI.h" -#if defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT) -#include "fsl_spi_dma.h" -#endif - -#if defined(SPI0) -extern ARM_DRIVER_SPI Driver_SPI0; -#endif /* SPI0 */ - -#if defined(SPI1) -extern ARM_DRIVER_SPI Driver_SPI1; -#endif /* SPI1 */ - -#if defined(SPI2) -extern ARM_DRIVER_SPI Driver_SPI2; -#endif /* SPI2 */ - -#if defined(SPI3) -extern ARM_DRIVER_SPI Driver_SPI3; -#endif /* SPI3 */ - -#if defined(SPI4) -extern ARM_DRIVER_SPI Driver_SPI4; -#endif /* SPI4 */ - -#if defined(SPI5) -extern ARM_DRIVER_SPI Driver_SPI5; -#endif /* SPI5 */ - -#if defined(SPI6) -extern ARM_DRIVER_SPI Driver_SPI6; -#endif /* SPI6 */ - -#if defined(SPI7) -extern ARM_DRIVER_SPI Driver_SPI7; -#endif /* SPI7 */ - -#if defined(SPI8) -extern ARM_DRIVER_SPI Driver_SPI8; -#endif /* SPI8 */ - -#if defined(SPI9) -extern ARM_DRIVER_SPI Driver_SPI9; -#endif /* SPI9 */ - -#endif diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/cmsis_drivers/fsl_usart_cmsis.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/cmsis_drivers/fsl_usart_cmsis.c deleted file mode 100644 index 1688ed56301..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/cmsis_drivers/fsl_usart_cmsis.c +++ /dev/null @@ -1,2732 +0,0 @@ -/* - * Copyright (c) 2013-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_usart_cmsis.h" - -#if (RTE_USART0 || RTE_USART1 || RTE_USART2 || RTE_USART3 || RTE_USART4 || RTE_USART5 || RTE_USART6 || RTE_USART7 || \ - RTE_USART8 || RTE_USART9) - -#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) - -/* - * ARMCC does not support split the data section automatically, so the driver - * needs to split the data to separate sections explicitly, to reduce codesize. - */ -#if defined(__CC_ARM) -#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) -#endif - -typedef const struct _cmsis_usart_resource -{ - USART_Type *base; /*!< usart peripheral base address. */ - uint32_t (*GetFreq)(void); /*!< Function to get the clock frequency. */ -} cmsis_usart_resource_t; - -typedef struct _cmsis_usart_non_blocking_driver_state -{ - cmsis_usart_resource_t *resource; /*!< Basic usart resource. */ - usart_handle_t *handle; /*!< Interupt transfer handle. */ - ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */ - bool isInitialized; /*!< Is initialized or not. */ - bool isPowerOn; /*!< Is power on or not. */ - bool isConfigured; /*!< Configured to work or not. */ -} cmsis_usart_non_blocking_driver_state_t; - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) -typedef const struct _cmsis_usart_dma_resource -{ - DMA_Type *txDmaBase; /*!< DMA peripheral base address for TX. */ - uint32_t txDmaChannel; /*!< DMA channel for usart TX. */ - - DMA_Type *rxDmaBase; /*!< DMA peripheral base address for RX. */ - uint32_t rxDmaChannel; /*!< DMA channel for usart RX. */ -} cmsis_usart_dma_resource_t; - -typedef struct _cmsis_usart_dma_driver_state -{ - cmsis_usart_resource_t *resource; /*!< usart basic resource. */ - cmsis_usart_dma_resource_t *dmaResource; /*!< usart DMA resource. */ - usart_dma_handle_t *handle; /*!< usart DMA transfer handle. */ - dma_handle_t *rxHandle; /*!< DMA RX handle. */ - dma_handle_t *txHandle; /*!< DMA TX handle. */ - ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */ - bool isInitialized; /*!< Is initialized or not. */ - bool isPowerOn; /*!< Is power on or not. */ - bool isConfigured; /*!< Configured to work or not. */ -} cmsis_usart_dma_driver_state_t; -#endif - -enum _usart_transfer_states -{ - kUSART_TxIdle, /*!< TX idle. */ - kUSART_TxBusy, /*!< TX busy. */ - kUSART_RxIdle, /*!< RX idle. */ - kUSART_RxBusy /*!< RX busy. */ -}; - -/* Driver Version */ -static const ARM_DRIVER_VERSION s_usartDriverVersion = {ARM_USART_API_VERSION, ARM_USART_DRV_VERSION}; - -static const ARM_USART_CAPABILITIES s_usartDriverCapabilities = { - 1, /* supports usart (Asynchronous) mode */ - 0, /* supports Synchronous Master mode */ - 0, /* supports Synchronous Slave mode */ - 0, /* supports usart Single-wire mode */ - 0, /* supports usart IrDA mode */ - 0, /* supports usart Smart Card mode */ - 0, /* Smart Card Clock generator */ - 0, /* RTS Flow Control available */ - 0, /* CTS Flow Control available */ - 0, /* Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE */ - 0, /* Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT */ - 0, /* RTS Line: 0=not available, 1=available */ - 0, /* CTS Line: 0=not available, 1=available */ - 0, /* DTR Line: 0=not available, 1=available */ - 0, /* DSR Line: 0=not available, 1=available */ - 0, /* DCD Line: 0=not available, 1=available */ - 0, /* RI Line: 0=not available, 1=available */ - 0, /* Signal CTS change event: \ref ARM_USART_EVENT_CTS */ - 0, /* Signal DSR change event: \ref ARM_USART_EVENT_DSR */ - 0, /* Signal DCD change event: \ref ARM_USART_EVENT_DCD */ - 0, /* Signal RI change event: \ref ARM_USART_EVENT_RI */ -}; - -/* - * Common control function used by usart_NonBlockingControl/usart_DmaControl/usart_EdmaControl - */ -static int32_t USART_CommonControl(uint32_t control, uint32_t arg, cmsis_usart_resource_t *resource, bool *isConfigured) -{ - usart_config_t config; - - USART_GetDefaultConfig(&config); - - switch (control & ARM_USART_CONTROL_Msk) - { - case ARM_USART_MODE_ASYNCHRONOUS: - /* USART Baudrate */ - config.baudRate_Bps = arg; - break; - - /* TX/RX IO is controlled in application layer. */ - case ARM_USART_CONTROL_TX: - if (arg) - { - config.enableTx = true; - } - else - { - config.enableTx = false; - } - return ARM_DRIVER_OK; - - case ARM_USART_CONTROL_RX: - if (arg) - { - config.enableRx = true; - } - else - { - config.enableRx = false; - } - - return ARM_DRIVER_OK; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - switch (control & ARM_USART_PARITY_Msk) - { - case ARM_USART_PARITY_NONE: - config.parityMode = kUSART_ParityDisabled; - break; - case ARM_USART_PARITY_EVEN: - config.parityMode = kUSART_ParityEven; - break; - case ARM_USART_PARITY_ODD: - config.parityMode = kUSART_ParityOdd; - break; - default: - return ARM_USART_ERROR_PARITY; - } - - switch (control & ARM_USART_STOP_BITS_Msk) - { - case ARM_USART_STOP_BITS_1: - /* The GetDefaultConfig has already set for this case. */ - break; - case ARM_USART_STOP_BITS_2: - config.stopBitCount = kUSART_TwoStopBit; - break; - default: - return ARM_USART_ERROR_STOP_BITS; - } - - /* If usart is already configured, deinit it first. */ - if (*isConfigured) - { - USART_Deinit(resource->base); - *isConfigured = false; - } - - config.enableTx = true; - config.enableRx = true; - - if (kStatus_USART_BaudrateNotSupport == USART_Init(resource->base, &config, resource->GetFreq())) - { - return ARM_USART_ERROR_BAUDRATE; - } - - *isConfigured = true; - - return ARM_DRIVER_OK; -} - -static ARM_DRIVER_VERSION USARTx_GetVersion(void) -{ - return s_usartDriverVersion; -} - -static ARM_USART_CAPABILITIES USARTx_GetCapabilities(void) -{ - return s_usartDriverCapabilities; -} - -static int32_t USARTx_SetModemControl(ARM_USART_MODEM_CONTROL control) -{ - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static ARM_USART_MODEM_STATUS USARTx_GetModemStatus(void) -{ - ARM_USART_MODEM_STATUS modem_status; - - modem_status.cts = 0U; - modem_status.dsr = 0U; - modem_status.ri = 0U; - modem_status.dcd = 0U; - - return modem_status; -} - -#endif - -#if (RTE_USART0_DMA_EN || RTE_USART1_DMA_EN || RTE_USART2_DMA_EN || RTE_USART3_DMA_EN || RTE_USART4_DMA_EN || \ - RTE_USART5_DMA_EN || RTE_USART6_DMA_EN || RTE_USART7_DMA_EN || RTE_USART8_DMA_EN || RTE_USART9_DMA_EN) - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) -void KSDK_USART_DmaCallback(USART_Type *base, usart_dma_handle_t *handle, status_t status, void *userData) -{ - uint32_t event; - - if (kStatus_USART_TxIdle == status) - { - event = ARM_USART_EVENT_SEND_COMPLETE; - } - - if (kStatus_USART_RxIdle == status) - { - event = ARM_USART_EVENT_RECEIVE_COMPLETE; - } - - /* User data is actually CMSIS driver callback. */ - if (userData) - { - ((ARM_USART_SignalEvent_t)userData)(event); - } -} - -static int32_t USART_DmaInitialize(ARM_USART_SignalEvent_t cb_event, cmsis_usart_dma_driver_state_t *usart) -{ - if (usart->isInitialized) - { - /* Driver is already initialized */ - return ARM_DRIVER_OK; - } - - usart->cb_event = cb_event; - usart->isInitialized = true; - - return ARM_DRIVER_OK; -} - -static int32_t USART_DmaUninitialize(cmsis_usart_dma_driver_state_t *usart) -{ - usart->isInitialized = false; - return ARM_DRIVER_OK; -} - -static int32_t USART_DmaPowerControl(ARM_POWER_STATE state, cmsis_usart_dma_driver_state_t *usart) -{ - usart_config_t config; - - switch (state) - { - case ARM_POWER_OFF: - if (usart->isPowerOn) - { - USART_Deinit(usart->resource->base); - DMA_DisableChannel(usart->dmaResource->rxDmaBase, usart->dmaResource->rxDmaChannel); - DMA_DisableChannel(usart->dmaResource->txDmaBase, usart->dmaResource->txDmaChannel); - usart->isPowerOn = false; - usart->isConfigured = false; - } - break; - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - case ARM_POWER_FULL: - /* Must be initialized first. */ - if (!usart->isInitialized) - { - return ARM_DRIVER_ERROR; - } - - if (!usart->isPowerOn) - { - USART_GetDefaultConfig(&config); - config.enableTx = true; - config.enableRx = true; - - /* Set up DMA setting. */ - DMA_EnableChannel(usart->dmaResource->txDmaBase, usart->dmaResource->txDmaChannel); - DMA_EnableChannel(usart->dmaResource->rxDmaBase, usart->dmaResource->rxDmaChannel); - - DMA_CreateHandle(usart->rxHandle, usart->dmaResource->rxDmaBase, usart->dmaResource->rxDmaChannel); - DMA_CreateHandle(usart->txHandle, usart->dmaResource->txDmaBase, usart->dmaResource->txDmaChannel); - - /* Setup the usart. */ - USART_Init(usart->resource->base, &config, usart->resource->GetFreq()); - USART_TransferCreateHandleDMA(usart->resource->base, usart->handle, KSDK_USART_DmaCallback, - (void *)usart->cb_event, usart->txHandle, usart->rxHandle); - - usart->isPowerOn = true; - usart->isConfigured = true; - } - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - return ARM_DRIVER_OK; -} - -static int32_t USART_DmaSend(const void *data, uint32_t num, cmsis_usart_dma_driver_state_t *usart) -{ - int32_t ret; - status_t status; - usart_transfer_t xfer; - - xfer.data = (uint8_t *)data; - xfer.dataSize = num; - - status = USART_TransferSendDMA(usart->resource->base, usart->handle, &xfer); - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_USART_TxBusy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t USART_DmaReceive(void *data, uint32_t num, cmsis_usart_dma_driver_state_t *usart) -{ - int32_t ret; - status_t status; - usart_transfer_t xfer; - - xfer.data = data; - xfer.dataSize = num; - - status = USART_TransferReceiveDMA(usart->resource->base, usart->handle, &xfer); - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_USART_RxBusy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t USART_DmaTransfer(const void *data_out, - void *data_in, - uint32_t num, - cmsis_usart_dma_driver_state_t *usart) -{ - /* Only in synchronous mode */ - return ARM_DRIVER_ERROR; -} - -static int32_t USART_DmaGetTxCount(cmsis_usart_dma_driver_state_t *usart) -{ - /* Does not support */ - return ARM_DRIVER_ERROR; -} - -static int32_t USART_DmaGetRxCount(cmsis_usart_dma_driver_state_t *usart) -{ - /* Does not support */ - return ARM_DRIVER_ERROR; -} - -static int32_t USART_DmaControl(uint32_t control, uint32_t arg, cmsis_usart_dma_driver_state_t *usart) -{ - /* Must be power on. */ - if (!usart->isPowerOn) - { - return ARM_DRIVER_ERROR; - } - - /* Does not support these features. */ - if (control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - switch (control & ARM_USART_CONTROL_Msk) - { - /* Abort Send */ - case ARM_USART_ABORT_SEND: - USART_EnableTxDMA(usart->resource->base, false); - DMA_AbortTransfer(usart->handle->txDmaHandle); - usart->handle->txState = kUSART_TxIdle; - return ARM_DRIVER_OK; - - /* Abort receive */ - case ARM_USART_ABORT_RECEIVE: - USART_EnableRxDMA(usart->resource->base, false); - DMA_AbortTransfer(usart->handle->rxDmaHandle); - usart->handle->rxState = kUSART_RxIdle; - return ARM_DRIVER_OK; - - default: - break; - } - - return USART_CommonControl(control, arg, usart->resource, &usart->isConfigured); -} - -static ARM_USART_STATUS USART_DmaGetStatus(cmsis_usart_dma_driver_state_t *usart) -{ - ARM_USART_STATUS stat; - uint32_t ksdk_usart_status = usart->resource->base->STAT; - - stat.tx_busy = ((kUSART_TxBusy == usart->handle->txState) ? (1U) : (0U)); - stat.rx_busy = ((kUSART_RxBusy == usart->handle->rxState) ? (1U) : (0U)); - - stat.tx_underflow = 0U; - stat.rx_overflow = 0U; - - stat.rx_break = (!(!(ksdk_usart_status & USART_STAT_RXBRK_MASK))); - - stat.rx_framing_error = (!(!(ksdk_usart_status & USART_STAT_FRAMERRINT_MASK))); - stat.rx_parity_error = (!(!(ksdk_usart_status & USART_STAT_PARITYERRINT_MASK))); - - return stat; -} -#endif - -#endif - -#if ((RTE_USART0 && !RTE_USART0_DMA_EN) || (RTE_USART1 && !RTE_USART1_DMA_EN) || (RTE_USART2 && !RTE_USART2_DMA_EN) || \ - (RTE_USART3 && !RTE_USART3_DMA_EN) || (RTE_USART4 && !RTE_USART4_DMA_EN) || (RTE_USART5 && !RTE_USART5_DMA_EN) || \ - (RTE_USART6 && !RTE_USART6_DMA_EN) || (RTE_USART7 && !RTE_USART7_DMA_EN) || (RTE_USART8 && !RTE_USART8_DMA_EN) || \ - (RTE_USART9 && !RTE_USART9_DMA_EN)) - -void KSDK_USART_NonBlockingCallback(USART_Type *base, usart_handle_t *handle, status_t status, void *userData) -{ - uint32_t event; - - if (kStatus_USART_TxIdle == status) - { - event = ARM_USART_EVENT_SEND_COMPLETE; - } - if (kStatus_USART_RxIdle == status) - { - event = ARM_USART_EVENT_RECEIVE_COMPLETE; - } - - /* User data is actually CMSIS driver callback. */ - if (userData) - { - ((ARM_USART_SignalEvent_t)userData)(event); - } -} - -static int32_t USART_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event, - cmsis_usart_non_blocking_driver_state_t *usart) -{ - if (usart->isInitialized) - { - /* Driver is already initialized */ - return ARM_DRIVER_OK; - } - - usart->cb_event = cb_event; - usart->isInitialized = true; - - return ARM_DRIVER_OK; -} - -static int32_t USART_NonBlockingUninitialize(cmsis_usart_non_blocking_driver_state_t *usart) -{ - usart->isInitialized = false; - return ARM_DRIVER_OK; -} - -static int32_t USART_NonBlockingPowerControl(ARM_POWER_STATE state, cmsis_usart_non_blocking_driver_state_t *usart) -{ - usart_config_t config; - - switch (state) - { - case ARM_POWER_OFF: - if (usart->isPowerOn) - { - USART_Deinit(usart->resource->base); - usart->isPowerOn = false; - usart->isConfigured = false; - } - break; - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - case ARM_POWER_FULL: - /* Must be initialized first. */ - if (!usart->isInitialized) - { - return ARM_DRIVER_ERROR; - } - - if (!usart->isPowerOn) - { - USART_GetDefaultConfig(&config); - config.enableTx = true; - config.enableRx = true; - - USART_Init(usart->resource->base, &config, usart->resource->GetFreq()); - USART_TransferCreateHandle(usart->resource->base, usart->handle, KSDK_USART_NonBlockingCallback, - (void *)usart->cb_event); - usart->isPowerOn = true; - usart->isConfigured = true; - } - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - return ARM_DRIVER_OK; -} - -static int32_t USART_NonBlockingSend(const void *data, uint32_t num, cmsis_usart_non_blocking_driver_state_t *usart) -{ - int32_t ret; - status_t status; - usart_transfer_t xfer; - - xfer.data = (uint8_t *)data; - xfer.dataSize = num; - - status = USART_TransferSendNonBlocking(usart->resource->base, usart->handle, &xfer); - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_USART_TxBusy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t USART_NonBlockingReceive(void *data, uint32_t num, cmsis_usart_non_blocking_driver_state_t *usart) -{ - int32_t ret; - status_t status; - usart_transfer_t xfer; - - xfer.data = data; - xfer.dataSize = num; - - status = USART_TransferReceiveNonBlocking(usart->resource->base, usart->handle, &xfer, NULL); - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_USART_RxBusy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t USART_NonBlockingTransfer(const void *data_out, - void *data_in, - uint32_t num, - cmsis_usart_non_blocking_driver_state_t *usart) -{ - /* Only in synchronous mode */ - return ARM_DRIVER_ERROR; -} - -static uint32_t USART_NonBlockingGetTxCount(cmsis_usart_non_blocking_driver_state_t *usart) -{ - uint32_t cnt; - - /* If TX not in progress, then the TX count is txDataSizeAll saved in handle. */ - if (kUSART_TxIdle == usart->handle->txState) - { - cnt = usart->handle->txDataSizeAll; - } - else - { - cnt = usart->handle->txDataSizeAll - usart->handle->txDataSize; - } - - return cnt; -} - -static uint32_t USART_NonBlockingGetRxCount(cmsis_usart_non_blocking_driver_state_t *usart) -{ - uint32_t cnt; - - if (kUSART_RxIdle == usart->handle->rxState) - { - cnt = usart->handle->rxDataSizeAll; - } - else - { - cnt = usart->handle->rxDataSizeAll - usart->handle->rxDataSize; - } - - return cnt; -} - -static int32_t USART_NonBlockingControl(uint32_t control, uint32_t arg, cmsis_usart_non_blocking_driver_state_t *usart) -{ - /* Must be power on. */ - if (!usart->isPowerOn) - { - return ARM_DRIVER_ERROR; - } - - /* Does not support these features. */ - if (control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - switch (control & ARM_USART_CONTROL_Msk) - { - /* Abort Send */ - case ARM_USART_ABORT_SEND: - usart->resource->base->FIFOINTENSET &= ~USART_FIFOINTENSET_TXLVL_MASK; - usart->handle->txDataSize = 0; - usart->handle->txState = kUSART_TxIdle; - return ARM_DRIVER_OK; - - /* Abort receive */ - case ARM_USART_ABORT_RECEIVE: - usart->resource->base->FIFOINTENSET &= ~USART_FIFOINTENSET_RXLVL_MASK; - usart->handle->rxDataSize = 0U; - usart->handle->rxState = kUSART_RxIdle; - return ARM_DRIVER_OK; - - default: - break; - } - - return USART_CommonControl(control, arg, usart->resource, &usart->isConfigured); -} - -static ARM_USART_STATUS USART_NonBlockingGetStatus(cmsis_usart_non_blocking_driver_state_t *usart) -{ - ARM_USART_STATUS stat; - uint32_t ksdk_usart_status = usart->resource->base->STAT; - - stat.tx_busy = ((kUSART_TxBusy == usart->handle->txState) ? (1U) : (0U)); - stat.rx_busy = ((kUSART_RxBusy == usart->handle->rxState) ? (1U) : (0U)); - - stat.tx_underflow = 0U; - stat.rx_overflow = 0U; - - stat.rx_break = (!(!(ksdk_usart_status & USART_STAT_RXBRK_MASK))); - - stat.rx_framing_error = (!(!(ksdk_usart_status & USART_STAT_FRAMERRINT_MASK))); - stat.rx_parity_error = (!(!(ksdk_usart_status & USART_STAT_PARITYERRINT_MASK))); - - return stat; -} - -#endif - -#if defined(USART0) && RTE_USART0 - -/* User needs to provide the implementation for USART0_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t USART0_GetFreq(void); -extern void USART0_InitPins(void); -extern void USART0_DeinitPins(void); - -cmsis_usart_resource_t usart0_Resource = {USART0, USART0_GetFreq}; - -/* usart0 Driver Control Block */ - -#if RTE_USART0_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_usart_dma_resource_t usart0_DmaResource = { - RTE_USART0_DMA_TX_DMA_BASE, RTE_USART0_DMA_TX_CH, RTE_USART0_DMA_RX_DMA_BASE, RTE_USART0_DMA_RX_CH, -}; - -usart_dma_handle_t USART0_DmaHandle; -dma_handle_t USART0_DmaRxHandle; -dma_handle_t USART0_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("usart0_dma_driver_state") -cmsis_usart_dma_driver_state_t usart0_DmaDriverState = { -#else -cmsis_usart_dma_driver_state_t usart0_DmaDriverState = { -#endif - &usart0_Resource, &usart0_DmaResource, &USART0_DmaHandle, &USART0_DmaRxHandle, &USART0_DmaTxHandle, -}; - -static int32_t USART0_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART0_InitPins(); - return USART_DmaInitialize(cb_event, &usart0_DmaDriverState); -} - -static int32_t USART0_DmaUninitialize(void) -{ - USART0_DeinitPins(); - return USART_DmaUninitialize(&usart0_DmaDriverState); -} - -static int32_t USART0_DmaPowerControl(ARM_POWER_STATE state) -{ - return USART_DmaPowerControl(state, &usart0_DmaDriverState); -} - -static int32_t USART0_DmaSend(const void *data, uint32_t num) -{ - return USART_DmaSend(data, num, &usart0_DmaDriverState); -} - -static int32_t USART0_DmaReceive(void *data, uint32_t num) -{ - return USART_DmaReceive(data, num, &usart0_DmaDriverState); -} - -static int32_t USART0_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_DmaTransfer(data_out, data_in, num, &usart0_DmaDriverState); -} - -static uint32_t USART0_DmaGetTxCount(void) -{ - return USART_DmaGetTxCount(&usart0_DmaDriverState); -} - -static uint32_t USART0_DmaGetRxCount(void) -{ - return USART_DmaGetRxCount(&usart0_DmaDriverState); -} - -static int32_t USART0_DmaControl(uint32_t control, uint32_t arg) -{ - return USART_DmaControl(control, arg, &usart0_DmaDriverState); -} - -static ARM_USART_STATUS USART0_DmaGetStatus(void) -{ - return USART_DmaGetStatus(&usart0_DmaDriverState); -} - -#endif - -#else - -usart_handle_t USART0_Handle; -#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1) -static uint8_t usart0_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("usart0_non_blocking_driver_state") -cmsis_usart_non_blocking_driver_state_t usart0_NonBlockingDriverState = { -#else -cmsis_usart_non_blocking_driver_state_t usart0_NonBlockingDriverState = { -#endif - &usart0_Resource, &USART0_Handle, -}; - -static int32_t USART0_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART0_InitPins(); - return USART_NonBlockingInitialize(cb_event, &usart0_NonBlockingDriverState); -} - -static int32_t USART0_NonBlockingUninitialize(void) -{ - USART0_DeinitPins(); - return USART_NonBlockingUninitialize(&usart0_NonBlockingDriverState); -} - -static int32_t USART0_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = USART_NonBlockingPowerControl(state, &usart0_NonBlockingDriverState); -#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (usart0_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - USART_TransferStartRingBuffer(usart0_NonBlockingDriverState.resource->base, - usart0_NonBlockingDriverState.handle, usart0_rxRingBuffer, USART_RX_BUFFER_LEN); - } -#endif - return result; -} - -static int32_t USART0_NonBlockingSend(const void *data, uint32_t num) -{ - return USART_NonBlockingSend(data, num, &usart0_NonBlockingDriverState); -} - -static int32_t USART0_NonBlockingReceive(void *data, uint32_t num) -{ - return USART_NonBlockingReceive(data, num, &usart0_NonBlockingDriverState); -} - -static int32_t USART0_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_NonBlockingTransfer(data_out, data_in, num, &usart0_NonBlockingDriverState); -} - -static uint32_t USART0_NonBlockingGetTxCount(void) -{ - return USART_NonBlockingGetTxCount(&usart0_NonBlockingDriverState); -} - -static uint32_t USART0_NonBlockingGetRxCount(void) -{ - return USART_NonBlockingGetRxCount(&usart0_NonBlockingDriverState); -} - -static int32_t USART0_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = USART_NonBlockingControl(control, arg, &usart0_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } -#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1) - /* Start receiving interrupts */ - usart0_NonBlockingDriverState.resource->base->FIFOINTENSET |= - USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -#endif - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS USART0_NonBlockingGetStatus(void) -{ - return USART_NonBlockingGetStatus(&usart0_NonBlockingDriverState); -} - -#endif - -ARM_DRIVER_USART Driver_USART0 = { - USARTx_GetVersion, USARTx_GetCapabilities, -#if RTE_USART0_DMA_EN - USART0_DmaInitialize, USART0_DmaUninitialize, USART0_DmaPowerControl, USART0_DmaSend, USART0_DmaReceive, - USART0_DmaTransfer, USART0_DmaGetTxCount, USART0_DmaGetRxCount, USART0_DmaControl, USART0_DmaGetStatus, -#else - USART0_NonBlockingInitialize, - USART0_NonBlockingUninitialize, - USART0_NonBlockingPowerControl, - USART0_NonBlockingSend, - USART0_NonBlockingReceive, - USART0_NonBlockingTransfer, - USART0_NonBlockingGetTxCount, - USART0_NonBlockingGetRxCount, - USART0_NonBlockingControl, - USART0_NonBlockingGetStatus, -#endif - USARTx_SetModemControl, USARTx_GetModemStatus}; - -#endif /* usart0 */ - -#if defined(USART1) && RTE_USART1 - -/* User needs to provide the implementation for USART1_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t USART1_GetFreq(void); -extern void USART1_InitPins(void); -extern void USART1_DeinitPins(void); - -cmsis_usart_resource_t usart1_Resource = {USART1, USART1_GetFreq}; - -#if RTE_USART1_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_usart_dma_resource_t usart1_DmaResource = { - RTE_USART1_DMA_TX_DMA_BASE, RTE_USART1_DMA_TX_CH, RTE_USART1_DMA_RX_DMA_BASE, RTE_USART1_DMA_RX_CH, -}; - -usart_dma_handle_t USART1_DmaHandle; -dma_handle_t USART1_DmaRxHandle; -dma_handle_t USART1_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("usart1_dma_driver_state") -cmsis_usart_dma_driver_state_t usart1_DmaDriverState = { -#else -cmsis_usart_dma_driver_state_t usart1_DmaDriverState = { -#endif - &usart1_Resource, &usart1_DmaResource, &USART1_DmaHandle, &USART1_DmaRxHandle, &USART1_DmaTxHandle, -}; - -static int32_t USART1_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART1_InitPins(); - return USART_DmaInitialize(cb_event, &usart1_DmaDriverState); -} - -static int32_t USART1_DmaUninitialize(void) -{ - USART1_DeinitPins(); - return USART_DmaUninitialize(&usart1_DmaDriverState); -} - -static int32_t USART1_DmaPowerControl(ARM_POWER_STATE state) -{ - return USART_DmaPowerControl(state, &usart1_DmaDriverState); -} - -static int32_t USART1_DmaSend(const void *data, uint32_t num) -{ - return USART_DmaSend(data, num, &usart1_DmaDriverState); -} - -static int32_t USART1_DmaReceive(void *data, uint32_t num) -{ - return USART_DmaReceive(data, num, &usart1_DmaDriverState); -} - -static int32_t USART1_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_DmaTransfer(data_out, data_in, num, &usart1_DmaDriverState); -} - -static uint32_t USART1_DmaGetTxCount(void) -{ - return USART_DmaGetTxCount(&usart1_DmaDriverState); -} - -static uint32_t USART1_DmaGetRxCount(void) -{ - return USART_DmaGetRxCount(&usart1_DmaDriverState); -} - -static int32_t USART1_DmaControl(uint32_t control, uint32_t arg) -{ - return USART_DmaControl(control, arg, &usart1_DmaDriverState); -} - -static ARM_USART_STATUS USART1_DmaGetStatus(void) -{ - return USART_DmaGetStatus(&usart1_DmaDriverState); -} - -#endif - -#else - -usart_handle_t USART1_Handle; -#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) -static uint8_t usart1_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("usart1_non_blocking_driver_state") -cmsis_usart_non_blocking_driver_state_t usart1_NonBlockingDriverState = { -#else -cmsis_usart_non_blocking_driver_state_t usart1_NonBlockingDriverState = { -#endif - &usart1_Resource, &USART1_Handle, -}; - -static int32_t USART1_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART1_InitPins(); - return USART_NonBlockingInitialize(cb_event, &usart1_NonBlockingDriverState); -} - -static int32_t USART1_NonBlockingUninitialize(void) -{ - USART1_DeinitPins(); - return USART_NonBlockingUninitialize(&usart1_NonBlockingDriverState); -} - -static int32_t USART1_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = USART_NonBlockingPowerControl(state, &usart1_NonBlockingDriverState); -#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (usart1_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - USART_TransferStartRingBuffer(usart1_NonBlockingDriverState.resource->base, - usart1_NonBlockingDriverState.handle, usart1_rxRingBuffer, USART_RX_BUFFER_LEN); - } -#endif - return result; -} - -static int32_t USART1_NonBlockingSend(const void *data, uint32_t num) -{ - return USART_NonBlockingSend(data, num, &usart1_NonBlockingDriverState); -} - -static int32_t USART1_NonBlockingReceive(void *data, uint32_t num) -{ - return USART_NonBlockingReceive(data, num, &usart1_NonBlockingDriverState); -} - -static int32_t USART1_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_NonBlockingTransfer(data_out, data_in, num, &usart1_NonBlockingDriverState); -} - -static uint32_t USART1_NonBlockingGetTxCount(void) -{ - return USART_NonBlockingGetTxCount(&usart1_NonBlockingDriverState); -} - -static uint32_t USART1_NonBlockingGetRxCount(void) -{ - return USART_NonBlockingGetRxCount(&usart1_NonBlockingDriverState); -} - -static int32_t USART1_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = USART_NonBlockingControl(control, arg, &usart1_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } -#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) - /* Start receiving interrupts */ - usart1_NonBlockingDriverState.resource->base->FIFOINTENSET |= - USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -#endif - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS USART1_NonBlockingGetStatus(void) -{ - return USART_NonBlockingGetStatus(&usart1_NonBlockingDriverState); -} - -#endif - -ARM_DRIVER_USART Driver_USART1 = { - USARTx_GetVersion, USARTx_GetCapabilities, -#if RTE_USART1_DMA_EN - USART1_DmaInitialize, USART1_DmaUninitialize, USART1_DmaPowerControl, USART1_DmaSend, USART1_DmaReceive, - USART1_DmaTransfer, USART1_DmaGetTxCount, USART1_DmaGetRxCount, USART1_DmaControl, USART1_DmaGetStatus, -#else - USART1_NonBlockingInitialize, - USART1_NonBlockingUninitialize, - USART1_NonBlockingPowerControl, - USART1_NonBlockingSend, - USART1_NonBlockingReceive, - USART1_NonBlockingTransfer, - USART1_NonBlockingGetTxCount, - USART1_NonBlockingGetRxCount, - USART1_NonBlockingControl, - USART1_NonBlockingGetStatus, -#endif - USARTx_SetModemControl, USARTx_GetModemStatus}; - -#endif /* usart1 */ - -#if defined(USART2) && RTE_USART2 - -/* User needs to provide the implementation for USART2_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t USART2_GetFreq(void); -extern void USART2_InitPins(void); -extern void USART2_DeinitPins(void); - -cmsis_usart_resource_t usart2_Resource = {USART2, USART2_GetFreq}; - -/* usart2 Driver Control Block */ - -#if RTE_USART2_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_usart_dma_resource_t usart2_DmaResource = { - RTE_USART2_DMA_TX_DMA_BASE, RTE_USART2_DMA_TX_CH, RTE_USART2_DMA_RX_DMA_BASE, RTE_USART2_DMA_RX_CH, -}; - -usart_dma_handle_t USART2_DmaHandle; -dma_handle_t USART2_DmaRxHandle; -dma_handle_t USART2_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("usart2_dma_driver_state") -cmsis_usart_dma_driver_state_t usart2_DmaDriverState = { -#else -cmsis_usart_dma_driver_state_t usart2_DmaDriverState = { -#endif - &usart2_Resource, &usart2_DmaResource, &USART2_DmaHandle, &USART2_DmaRxHandle, &USART2_DmaTxHandle, -}; - -static int32_t USART2_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART2_InitPins(); - return USART_DmaInitialize(cb_event, &usart2_DmaDriverState); -} - -static int32_t USART2_DmaUninitialize(void) -{ - USART2_DeinitPins(); - return USART_DmaUninitialize(&usart2_DmaDriverState); -} - -static int32_t USART2_DmaPowerControl(ARM_POWER_STATE state) -{ - return USART_DmaPowerControl(state, &usart2_DmaDriverState); -} - -static int32_t USART2_DmaSend(const void *data, uint32_t num) -{ - return USART_DmaSend(data, num, &usart2_DmaDriverState); -} - -static int32_t USART2_DmaReceive(void *data, uint32_t num) -{ - return USART_DmaReceive(data, num, &usart2_DmaDriverState); -} - -static int32_t USART2_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_DmaTransfer(data_out, data_in, num, &usart2_DmaDriverState); -} - -static uint32_t USART2_DmaGetTxCount(void) -{ - return USART_DmaGetTxCount(&usart2_DmaDriverState); -} - -static uint32_t USART2_DmaGetRxCount(void) -{ - return USART_DmaGetRxCount(&usart2_DmaDriverState); -} - -static int32_t USART2_DmaControl(uint32_t control, uint32_t arg) -{ - return USART_DmaControl(control, arg, &usart2_DmaDriverState); -} - -static ARM_USART_STATUS USART2_DmaGetStatus(void) -{ - return USART_DmaGetStatus(&usart2_DmaDriverState); -} - -#endif - -#else - -usart_handle_t USART2_Handle; -#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) -static uint8_t usart2_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("usart2_non_blocking_driver_state") -cmsis_usart_non_blocking_driver_state_t usart2_NonBlockingDriverState = { -#else -cmsis_usart_non_blocking_driver_state_t usart2_NonBlockingDriverState = { -#endif - &usart2_Resource, &USART2_Handle, -}; - -static int32_t USART2_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART2_InitPins(); - return USART_NonBlockingInitialize(cb_event, &usart2_NonBlockingDriverState); -} - -static int32_t USART2_NonBlockingUninitialize(void) -{ - USART2_DeinitPins(); - return USART_NonBlockingUninitialize(&usart2_NonBlockingDriverState); -} - -static int32_t USART2_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = USART_NonBlockingPowerControl(state, &usart2_NonBlockingDriverState); -#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (usart2_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - USART_TransferStartRingBuffer(usart2_NonBlockingDriverState.resource->base, - usart2_NonBlockingDriverState.handle, usart2_rxRingBuffer, USART_RX_BUFFER_LEN); - } -#endif - return result; -} - -static int32_t USART2_NonBlockingSend(const void *data, uint32_t num) -{ - return USART_NonBlockingSend(data, num, &usart2_NonBlockingDriverState); -} - -static int32_t USART2_NonBlockingReceive(void *data, uint32_t num) -{ - return USART_NonBlockingReceive(data, num, &usart2_NonBlockingDriverState); -} - -static int32_t USART2_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_NonBlockingTransfer(data_out, data_in, num, &usart2_NonBlockingDriverState); -} - -static uint32_t USART2_NonBlockingGetTxCount(void) -{ - return USART_NonBlockingGetTxCount(&usart2_NonBlockingDriverState); -} - -static uint32_t USART2_NonBlockingGetRxCount(void) -{ - return USART_NonBlockingGetRxCount(&usart2_NonBlockingDriverState); -} - -static int32_t USART2_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = USART_NonBlockingControl(control, arg, &usart2_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } -#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) - /* Start receiving interrupts */ - usart2_NonBlockingDriverState.resource->base->FIFOINTENSET |= - USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -#endif - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS USART2_NonBlockingGetStatus(void) -{ - return USART_NonBlockingGetStatus(&usart2_NonBlockingDriverState); -} - -#endif - -ARM_DRIVER_USART Driver_USART2 = { - USARTx_GetVersion, USARTx_GetCapabilities, -#if RTE_USART2_DMA_EN - USART2_DmaInitialize, USART2_DmaUninitialize, USART2_DmaPowerControl, USART2_DmaSend, USART2_DmaReceive, - USART2_DmaTransfer, USART2_DmaGetTxCount, USART2_DmaGetRxCount, USART2_DmaControl, USART2_DmaGetStatus, -#else - USART2_NonBlockingInitialize, - USART2_NonBlockingUninitialize, - USART2_NonBlockingPowerControl, - USART2_NonBlockingSend, - USART2_NonBlockingReceive, - USART2_NonBlockingTransfer, - USART2_NonBlockingGetTxCount, - USART2_NonBlockingGetRxCount, - USART2_NonBlockingControl, - USART2_NonBlockingGetStatus, -#endif - USARTx_SetModemControl, USARTx_GetModemStatus}; - -#endif /* usart2 */ - -#if defined(USART3) && RTE_USART3 - -/* User needs to provide the implementation for USART3_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t USART3_GetFreq(void); -extern void USART3_InitPins(void); -extern void USART3_DeinitPins(void); - -cmsis_usart_resource_t usart3_Resource = {USART3, USART3_GetFreq}; - -/* usart3 Driver Control Block */ -#if RTE_USART3_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_usart_dma_resource_t usart3_DmaResource = { - RTE_USART3_DMA_TX_DMA_BASE, RTE_USART3_DMA_TX_CH, RTE_USART3_DMA_RX_DMA_BASE, RTE_USART3_DMA_RX_CH, -}; - -usart_dma_handle_t USART3_DmaHandle; -dma_handle_t USART3_DmaRxHandle; -dma_handle_t USART3_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("usart3_dma_driver_state") -cmsis_usart_dma_driver_state_t usart3_DmaDriverState = { -#else -cmsis_usart_dma_driver_state_t usart3_DmaDriverState = { -#endif - &usart3_Resource, &usart3_DmaResource, &USART3_DmaHandle, &USART3_DmaRxHandle, &USART3_DmaTxHandle, -}; - -static int32_t USART3_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART3_InitPins(); - return USART_DmaInitialize(cb_event, &usart3_DmaDriverState); -} - -static int32_t USART3_DmaUninitialize(void) -{ - USART3_DeinitPins(); - return USART_DmaUninitialize(&usart3_DmaDriverState); -} - -static int32_t USART3_DmaPowerControl(ARM_POWER_STATE state) -{ - return USART_DmaPowerControl(state, &usart3_DmaDriverState); -} - -static int32_t USART3_DmaSend(const void *data, uint32_t num) -{ - return USART_DmaSend(data, num, &usart3_DmaDriverState); -} - -static int32_t USART3_DmaReceive(void *data, uint32_t num) -{ - return USART_DmaReceive(data, num, &usart3_DmaDriverState); -} - -static int32_t USART3_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_DmaTransfer(data_out, data_in, num, &usart3_DmaDriverState); -} - -static uint32_t USART3_DmaGetTxCount(void) -{ - return USART_DmaGetTxCount(&usart3_DmaDriverState); -} - -static uint32_t USART3_DmaGetRxCount(void) -{ - return USART_DmaGetRxCount(&usart3_DmaDriverState); -} - -static int32_t USART3_DmaControl(uint32_t control, uint32_t arg) -{ - return USART_DmaControl(control, arg, &usart3_DmaDriverState); -} - -static ARM_USART_STATUS USART3_DmaGetStatus(void) -{ - return USART_DmaGetStatus(&usart3_DmaDriverState); -} - -#endif - -#else - -usart_handle_t USART3_Handle; -#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) -static uint8_t usart3_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("usart3_non_blocking_driver_state") -cmsis_usart_non_blocking_driver_state_t usart3_NonBlockingDriverState = { -#else -cmsis_usart_non_blocking_driver_state_t usart3_NonBlockingDriverState = { -#endif - &usart3_Resource, &USART3_Handle, -}; - -static int32_t USART3_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART3_InitPins(); - return USART_NonBlockingInitialize(cb_event, &usart3_NonBlockingDriverState); -} - -static int32_t USART3_NonBlockingUninitialize(void) -{ - USART3_DeinitPins(); - return USART_NonBlockingUninitialize(&usart3_NonBlockingDriverState); -} - -static int32_t USART3_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = USART_NonBlockingPowerControl(state, &usart3_NonBlockingDriverState); -#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (usart3_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - USART_TransferStartRingBuffer(usart3_NonBlockingDriverState.resource->base, - usart3_NonBlockingDriverState.handle, usart3_rxRingBuffer, USART_RX_BUFFER_LEN); - } -#endif - return result; -} - -static int32_t USART3_NonBlockingSend(const void *data, uint32_t num) -{ - return USART_NonBlockingSend(data, num, &usart3_NonBlockingDriverState); -} - -static int32_t USART3_NonBlockingReceive(void *data, uint32_t num) -{ - return USART_NonBlockingReceive(data, num, &usart3_NonBlockingDriverState); -} - -static int32_t USART3_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_NonBlockingTransfer(data_out, data_in, num, &usart3_NonBlockingDriverState); -} - -static uint32_t USART3_NonBlockingGetTxCount(void) -{ - return USART_NonBlockingGetTxCount(&usart3_NonBlockingDriverState); -} - -static uint32_t USART3_NonBlockingGetRxCount(void) -{ - return USART_NonBlockingGetRxCount(&usart3_NonBlockingDriverState); -} - -static int32_t USART3_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = USART_NonBlockingControl(control, arg, &usart3_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } -#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) - /* Start receiving interrupts */ - usart3_NonBlockingDriverState.resource->base->FIFOINTENSET |= - USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -#endif - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS USART3_NonBlockingGetStatus(void) -{ - return USART_NonBlockingGetStatus(&usart3_NonBlockingDriverState); -} - -#endif - -ARM_DRIVER_USART Driver_USART3 = { - USARTx_GetVersion, USARTx_GetCapabilities, -#if RTE_USART3_DMA_EN - USART3_DmaInitialize, USART3_DmaUninitialize, USART3_DmaPowerControl, USART3_DmaSend, USART3_DmaReceive, - USART3_DmaTransfer, USART3_DmaGetTxCount, USART3_DmaGetRxCount, USART3_DmaControl, USART3_DmaGetStatus, -#else - USART3_NonBlockingInitialize, - USART3_NonBlockingUninitialize, - USART3_NonBlockingPowerControl, - USART3_NonBlockingSend, - USART3_NonBlockingReceive, - USART3_NonBlockingTransfer, - USART3_NonBlockingGetTxCount, - USART3_NonBlockingGetRxCount, - USART3_NonBlockingControl, - USART3_NonBlockingGetStatus, -#endif - USARTx_SetModemControl, USARTx_GetModemStatus}; - -#endif /* usart3 */ - -#if defined(USART4) && RTE_USART4 - -/* User needs to provide the implementation for USART4_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t USART4_GetFreq(void); -extern void USART4_InitPins(void); -extern void USART4_DeinitPins(void); - -cmsis_usart_resource_t usart4_Resource = {USART4, USART4_GetFreq}; - -#if RTE_USART4_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_usart_dma_resource_t usart4_DmaResource = { - RTE_USART4_DMA_TX_DMA_BASE, RTE_USART4_DMA_TX_CH, RTE_USART4_DMA_RX_DMA_BASE, RTE_USART4_DMA_RX_CH, -}; - -usart_dma_handle_t USART4_DmaHandle; -dma_handle_t USART4_DmaRxHandle; -dma_handle_t USART4_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("usart4_dma_driver_state") -cmsis_usart_dma_driver_state_t usart4_DmaDriverState = { -#else -cmsis_usart_dma_driver_state_t usart4_DmaDriverState = { -#endif - &usart4_Resource, &usart4_DmaResource, &USART4_DmaHandle, &USART4_DmaRxHandle, &USART4_DmaTxHandle, -}; - -static int32_t USART4_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART4_InitPins(); - return USART_DmaInitialize(cb_event, &usart4_DmaDriverState); -} - -static int32_t USART4_DmaUninitialize(void) -{ - USART4_DeinitPins(); - return USART_DmaUninitialize(&usart4_DmaDriverState); -} - -static int32_t USART4_DmaPowerControl(ARM_POWER_STATE state) -{ - return USART_DmaPowerControl(state, &usart4_DmaDriverState); -} - -static int32_t USART4_DmaSend(const void *data, uint32_t num) -{ - return USART_DmaSend(data, num, &usart4_DmaDriverState); -} - -static int32_t USART4_DmaReceive(void *data, uint32_t num) -{ - return USART_DmaReceive(data, num, &usart4_DmaDriverState); -} - -static int32_t USART4_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_DmaTransfer(data_out, data_in, num, &usart4_DmaDriverState); -} - -static uint32_t USART4_DmaGetTxCount(void) -{ - return USART_DmaGetTxCount(&usart4_DmaDriverState); -} - -static uint32_t USART4_DmaGetRxCount(void) -{ - return USART_DmaGetRxCount(&usart4_DmaDriverState); -} - -static int32_t USART4_DmaControl(uint32_t control, uint32_t arg) -{ - return USART_DmaControl(control, arg, &usart4_DmaDriverState); -} - -static ARM_USART_STATUS USART4_DmaGetStatus(void) -{ - return USART_DmaGetStatus(&usart4_DmaDriverState); -} - -#endif - -#else - -usart_handle_t USART4_Handle; -#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) -static uint8_t usart4_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("usart4_non_blocking_driver_state") -cmsis_usart_non_blocking_driver_state_t usart4_NonBlockingDriverState = { -#else -cmsis_usart_non_blocking_driver_state_t usart4_NonBlockingDriverState = { -#endif - &usart4_Resource, &USART4_Handle, -}; - -static int32_t USART4_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART4_InitPins(); - return USART_NonBlockingInitialize(cb_event, &usart4_NonBlockingDriverState); -} - -static int32_t USART4_NonBlockingUninitialize(void) -{ - USART4_DeinitPins(); - return USART_NonBlockingUninitialize(&usart4_NonBlockingDriverState); -} - -static int32_t USART4_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = USART_NonBlockingPowerControl(state, &usart4_NonBlockingDriverState); -#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (usart4_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - USART_TransferStartRingBuffer(usart4_NonBlockingDriverState.resource->base, - usart4_NonBlockingDriverState.handle, usart4_rxRingBuffer, USART_RX_BUFFER_LEN); - } -#endif - return result; -} - -static int32_t USART4_NonBlockingSend(const void *data, uint32_t num) -{ - return USART_NonBlockingSend(data, num, &usart4_NonBlockingDriverState); -} - -static int32_t USART4_NonBlockingReceive(void *data, uint32_t num) -{ - return USART_NonBlockingReceive(data, num, &usart4_NonBlockingDriverState); -} - -static int32_t USART4_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_NonBlockingTransfer(data_out, data_in, num, &usart4_NonBlockingDriverState); -} - -static uint32_t USART4_NonBlockingGetTxCount(void) -{ - return USART_NonBlockingGetTxCount(&usart4_NonBlockingDriverState); -} - -static uint32_t USART4_NonBlockingGetRxCount(void) -{ - return USART_NonBlockingGetRxCount(&usart4_NonBlockingDriverState); -} - -static int32_t USART4_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = USART_NonBlockingControl(control, arg, &usart4_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } -#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) - /* Start receiving interrupts */ - usart4_NonBlockingDriverState.resource->base->FIFOINTENSET |= - USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -#endif - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS USART4_NonBlockingGetStatus(void) -{ - return USART_NonBlockingGetStatus(&usart4_NonBlockingDriverState); -} - -#endif - -ARM_DRIVER_USART Driver_USART4 = { - USARTx_GetVersion, USARTx_GetCapabilities, -#if RTE_USART4_DMA_EN - USART4_DmaInitialize, USART4_DmaUninitialize, USART4_DmaPowerControl, USART4_DmaSend, USART4_DmaReceive, - USART4_DmaTransfer, USART4_DmaGetTxCount, USART4_DmaGetRxCount, USART4_DmaControl, USART4_DmaGetStatus, -#else - USART4_NonBlockingInitialize, - USART4_NonBlockingUninitialize, - USART4_NonBlockingPowerControl, - USART4_NonBlockingSend, - USART4_NonBlockingReceive, - USART4_NonBlockingTransfer, - USART4_NonBlockingGetTxCount, - USART4_NonBlockingGetRxCount, - USART4_NonBlockingControl, - USART4_NonBlockingGetStatus, -#endif - USARTx_SetModemControl, USARTx_GetModemStatus}; - -#endif /* usart4 */ - -#if defined(USART5) && RTE_USART5 - -/* User needs to provide the implementation for USART5_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t USART5_GetFreq(void); -extern void USART5_InitPins(void); -extern void USART5_DeinitPins(void); - -cmsis_usart_resource_t usart5_Resource = {USART5, USART5_GetFreq}; - -#if RTE_USART5_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_usart_dma_resource_t usart5_DmaResource = { - RTE_USART5_DMA_TX_DMA_BASE, RTE_USART5_DMA_TX_CH, RTE_USART5_DMA_RX_DMA_BASE, RTE_USART5_DMA_RX_CH, -}; - -usart_dma_handle_t USART5_DmaHandle; -dma_handle_t USART5_DmaRxHandle; -dma_handle_t USART5_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("usart5_dma_driver_state") -cmsis_usart_dma_driver_state_t usart5_DmaDriverState = { -#else -cmsis_usart_dma_driver_state_t usart5_DmaDriverState = { -#endif - &usart5_Resource, &usart5_DmaResource, &USART5_DmaHandle, &USART5_DmaRxHandle, &USART5_DmaTxHandle, -}; - -static int32_t USART5_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART5_InitPins(); - return USART_DmaInitialize(cb_event, &usart5_DmaDriverState); -} - -static int32_t USART5_DmaUninitialize(void) -{ - USART5_DeinitPins(); - return USART_DmaUninitialize(&usart5_DmaDriverState); -} - -static int32_t USART5_DmaPowerControl(ARM_POWER_STATE state) -{ - return USART_DmaPowerControl(state, &usart5_DmaDriverState); -} - -static int32_t USART5_DmaSend(const void *data, uint32_t num) -{ - return USART_DmaSend(data, num, &usart5_DmaDriverState); -} - -static int32_t USART5_DmaReceive(void *data, uint32_t num) -{ - return USART_DmaReceive(data, num, &usart5_DmaDriverState); -} - -static int32_t USART5_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_DmaTransfer(data_out, data_in, num, &usart5_DmaDriverState); -} - -static uint32_t USART5_DmaGetTxCount(void) -{ - return USART_DmaGetTxCount(&usart5_DmaDriverState); -} - -static uint32_t USART5_DmaGetRxCount(void) -{ - return USART_DmaGetRxCount(&usart5_DmaDriverState); -} - -static int32_t USART5_DmaControl(uint32_t control, uint32_t arg) -{ - return USART_DmaControl(control, arg, &usart5_DmaDriverState); -} - -static ARM_USART_STATUS USART5_DmaGetStatus(void) -{ - return USART_DmaGetStatus(&usart5_DmaDriverState); -} - -#endif - -#else - -usart_handle_t USART5_Handle; -#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1) -static uint8_t usart5_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("usart5_non_blocking_driver_state") -cmsis_usart_non_blocking_driver_state_t usart5_NonBlockingDriverState = { -#else -cmsis_usart_non_blocking_driver_state_t usart5_NonBlockingDriverState = { -#endif - &usart5_Resource, &USART5_Handle, -}; - -static int32_t USART5_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART5_InitPins(); - return USART_NonBlockingInitialize(cb_event, &usart5_NonBlockingDriverState); -} - -static int32_t USART5_NonBlockingUninitialize(void) -{ - USART5_DeinitPins(); - return USART_NonBlockingUninitialize(&usart5_NonBlockingDriverState); -} - -static int32_t USART5_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = USART_NonBlockingPowerControl(state, &usart5_NonBlockingDriverState); -#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (usart5_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - USART_TransferStartRingBuffer(usart5_NonBlockingDriverState.resource->base, - usart5_NonBlockingDriverState.handle, usart5_rxRingBuffer, USART_RX_BUFFER_LEN); - } -#endif - return result; -} - -static int32_t USART5_NonBlockingSend(const void *data, uint32_t num) -{ - return USART_NonBlockingSend(data, num, &usart5_NonBlockingDriverState); -} - -static int32_t USART5_NonBlockingReceive(void *data, uint32_t num) -{ - return USART_NonBlockingReceive(data, num, &usart5_NonBlockingDriverState); -} - -static int32_t USART5_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_NonBlockingTransfer(data_out, data_in, num, &usart5_NonBlockingDriverState); -} - -static uint32_t USART5_NonBlockingGetTxCount(void) -{ - return USART_NonBlockingGetTxCount(&usart5_NonBlockingDriverState); -} - -static uint32_t USART5_NonBlockingGetRxCount(void) -{ - return USART_NonBlockingGetRxCount(&usart5_NonBlockingDriverState); -} - -static int32_t USART5_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = USART_NonBlockingControl(control, arg, &usart5_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } -#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1) - /* Start receiving interrupts */ - usart5_NonBlockingDriverState.resource->base->FIFOINTENSET |= - USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -#endif - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS USART5_NonBlockingGetStatus(void) -{ - return USART_NonBlockingGetStatus(&usart5_NonBlockingDriverState); -} - -#endif - -ARM_DRIVER_USART Driver_USART5 = { - USARTx_GetVersion, USARTx_GetCapabilities, -#if RTE_USART5_DMA_EN - USART5_DmaInitialize, USART5_DmaUninitialize, USART5_DmaPowerControl, USART5_DmaSend, USART5_DmaReceive, - USART5_DmaTransfer, USART5_DmaGetTxCount, USART5_DmaGetRxCount, USART5_DmaControl, USART5_DmaGetStatus, -#else - USART5_NonBlockingInitialize, - USART5_NonBlockingUninitialize, - USART5_NonBlockingPowerControl, - USART5_NonBlockingSend, - USART5_NonBlockingReceive, - USART5_NonBlockingTransfer, - USART5_NonBlockingGetTxCount, - USART5_NonBlockingGetRxCount, - USART5_NonBlockingControl, - USART5_NonBlockingGetStatus, -#endif - USARTx_SetModemControl, USARTx_GetModemStatus}; - -#endif /* usart5 */ - -#if defined(USART6) && RTE_USART6 - -/* User needs to provide the implementation for USART6_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t USART6_GetFreq(void); -extern void USART6_InitPins(void); -extern void USART6_DeinitPins(void); - -cmsis_usart_resource_t usart6_Resource = {USART6, USART6_GetFreq}; - -#if RTE_USART6_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_usart_dma_resource_t usart6_DmaResource = { - RTE_USART6_DMA_TX_DMA_BASE, RTE_USART6_DMA_TX_CH, RTE_USART6_DMA_RX_DMA_BASE, RTE_USART6_DMA_RX_CH, -}; - -usart_dma_handle_t USART6_DmaHandle; -dma_handle_t USART6_DmaRxHandle; -dma_handle_t USART6_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("usart6_dma_driver_state") -cmsis_usart_dma_driver_state_t usart6_DmaDriverState = { -#else -cmsis_usart_dma_driver_state_t usart6_DmaDriverState = { -#endif - &usart6_Resource, &usart6_DmaResource, &USART6_DmaHandle, &USART6_DmaRxHandle, &USART6_DmaTxHandle, -}; - -static int32_t USART6_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART6_InitPins(); - return USART_DmaInitialize(cb_event, &usart6_DmaDriverState); -} - -static int32_t USART6_DmaUninitialize(void) -{ - USART6_DeinitPins(); - return USART_DmaUninitialize(&usart6_DmaDriverState); -} - -static int32_t USART6_DmaPowerControl(ARM_POWER_STATE state) -{ - return USART_DmaPowerControl(state, &usart6_DmaDriverState); -} - -static int32_t USART6_DmaSend(const void *data, uint32_t num) -{ - return USART_DmaSend(data, num, &usart6_DmaDriverState); -} - -static int32_t USART6_DmaReceive(void *data, uint32_t num) -{ - return USART_DmaReceive(data, num, &usart6_DmaDriverState); -} - -static int32_t USART6_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_DmaTransfer(data_out, data_in, num, &usart6_DmaDriverState); -} - -static uint32_t USART6_DmaGetTxCount(void) -{ - return USART_DmaGetTxCount(&usart6_DmaDriverState); -} - -static uint32_t USART6_DmaGetRxCount(void) -{ - return USART_DmaGetRxCount(&usart6_DmaDriverState); -} - -static int32_t USART6_DmaControl(uint32_t control, uint32_t arg) -{ - return USART_DmaControl(control, arg, &usart6_DmaDriverState); -} - -static ARM_USART_STATUS USART6_DmaGetStatus(void) -{ - return USART_DmaGetStatus(&usart6_DmaDriverState); -} - -#endif - -#else - -usart_handle_t USART6_Handle; -#if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1) -static uint8_t usart6_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("usart6_non_blocking_driver_state") -cmsis_usart_non_blocking_driver_state_t usart6_NonBlockingDriverState = { -#else -cmsis_usart_non_blocking_driver_state_t usart6_NonBlockingDriverState = { -#endif - &usart6_Resource, &USART6_Handle, -}; - -static int32_t USART6_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART6_InitPins(); - return USART_NonBlockingInitialize(cb_event, &usart6_NonBlockingDriverState); -} - -static int32_t USART6_NonBlockingUninitialize(void) -{ - USART6_DeinitPins(); - return USART_NonBlockingUninitialize(&usart6_NonBlockingDriverState); -} - -static int32_t USART6_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = USART_NonBlockingPowerControl(state, &usart6_NonBlockingDriverState); -#if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (usart6_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - USART_TransferStartRingBuffer(usart6_NonBlockingDriverState.resource->base, - usart6_NonBlockingDriverState.handle, usart6_rxRingBuffer, USART_RX_BUFFER_LEN); - } -#endif - return result; -} - -static int32_t USART6_NonBlockingSend(const void *data, uint32_t num) -{ - return USART_NonBlockingSend(data, num, &usart6_NonBlockingDriverState); -} - -static int32_t USART6_NonBlockingReceive(void *data, uint32_t num) -{ - return USART_NonBlockingReceive(data, num, &usart6_NonBlockingDriverState); -} - -static int32_t USART6_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_NonBlockingTransfer(data_out, data_in, num, &usart6_NonBlockingDriverState); -} - -static uint32_t USART6_NonBlockingGetTxCount(void) -{ - return USART_NonBlockingGetTxCount(&usart6_NonBlockingDriverState); -} - -static uint32_t USART6_NonBlockingGetRxCount(void) -{ - return USART_NonBlockingGetRxCount(&usart6_NonBlockingDriverState); -} - -static int32_t USART6_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = USART_NonBlockingControl(control, arg, &usart6_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } -#if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1) - /* Start receiving interrupts */ - usart6_NonBlockingDriverState.resource->base->FIFOINTENSET |= - USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -#endif - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS USART6_NonBlockingGetStatus(void) -{ - return USART_NonBlockingGetStatus(&usart6_NonBlockingDriverState); -} - -#endif - -ARM_DRIVER_USART Driver_USART6 = { - USARTx_GetVersion, USARTx_GetCapabilities, -#if RTE_USART6_DMA_EN - USART6_DmaInitialize, USART6_DmaUninitialize, USART6_DmaPowerControl, USART6_DmaSend, USART6_DmaReceive, - USART6_DmaTransfer, USART6_DmaGetTxCount, USART6_DmaGetRxCount, USART6_DmaControl, USART6_DmaGetStatus, -#else - USART6_NonBlockingInitialize, - USART6_NonBlockingUninitialize, - USART6_NonBlockingPowerControl, - USART6_NonBlockingSend, - USART6_NonBlockingReceive, - USART6_NonBlockingTransfer, - USART6_NonBlockingGetTxCount, - USART6_NonBlockingGetRxCount, - USART6_NonBlockingControl, - USART6_NonBlockingGetStatus, -#endif - USARTx_SetModemControl, USARTx_GetModemStatus}; - -#endif /* usart6 */ - -#if defined(USART7) && RTE_USART7 - -/* User needs to provide the implementation for USART7_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t USART7_GetFreq(void); -extern void USART7_InitPins(void); -extern void USART7_DeinitPins(void); - -cmsis_usart_resource_t usart7_Resource = {USART7, USART7_GetFreq}; - -#if RTE_USART7_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_usart_dma_resource_t usart7_DmaResource = { - RTE_USART7_DMA_TX_DMA_BASE, RTE_USART7_DMA_TX_CH, RTE_USART7_DMA_RX_DMA_BASE, RTE_USART7_DMA_RX_CH, -}; - -usart_dma_handle_t USART7_DmaHandle; -dma_handle_t USART7_DmaRxHandle; -dma_handle_t USART7_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("usart7_dma_driver_state") -cmsis_usart_dma_driver_state_t usart7_DmaDriverState = { -#else -cmsis_usart_dma_driver_state_t usart7_DmaDriverState = { -#endif - &usart7_Resource, &usart7_DmaResource, &USART7_DmaHandle, &USART7_DmaRxHandle, &USART7_DmaTxHandle, -}; - -static int32_t USART7_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART7_InitPins(); - return USART_DmaInitialize(cb_event, &usart7_DmaDriverState); -} - -static int32_t USART7_DmaUninitialize(void) -{ - USART7_DeinitPins(); - return USART_DmaUninitialize(&usart7_DmaDriverState); -} - -static int32_t USART7_DmaPowerControl(ARM_POWER_STATE state) -{ - return USART_DmaPowerControl(state, &usart7_DmaDriverState); -} - -static int32_t USART7_DmaSend(const void *data, uint32_t num) -{ - return USART_DmaSend(data, num, &usart7_DmaDriverState); -} - -static int32_t USART7_DmaReceive(void *data, uint32_t num) -{ - return USART_DmaReceive(data, num, &usart7_DmaDriverState); -} - -static int32_t USART7_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_DmaTransfer(data_out, data_in, num, &usart7_DmaDriverState); -} - -static uint32_t USART7_DmaGetTxCount(void) -{ - return USART_DmaGetTxCount(&usart7_DmaDriverState); -} - -static uint32_t USART7_DmaGetRxCount(void) -{ - return USART_DmaGetRxCount(&usart7_DmaDriverState); -} - -static int32_t USART7_DmaControl(uint32_t control, uint32_t arg) -{ - return USART_DmaControl(control, arg, &usart7_DmaDriverState); -} - -static ARM_USART_STATUS USART7_DmaGetStatus(void) -{ - return USART_DmaGetStatus(&usart7_DmaDriverState); -} - -#endif - -#else - -usart_handle_t USART7_Handle; -#if defined(USART7_RX_BUFFER_ENABLE) && (USART7_RX_BUFFER_ENABLE == 1) -static uint8_t usart7_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("usart7_non_blocking_driver_state") -cmsis_usart_non_blocking_driver_state_t usart7_NonBlockingDriverState = { -#else -cmsis_usart_non_blocking_driver_state_t usart7_NonBlockingDriverState = { -#endif - &usart7_Resource, &USART7_Handle, -}; - -static int32_t USART7_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART7_InitPins(); - return USART_NonBlockingInitialize(cb_event, &usart7_NonBlockingDriverState); -} - -static int32_t USART7_NonBlockingUninitialize(void) -{ - USART7_DeinitPins(); - return USART_NonBlockingUninitialize(&usart7_NonBlockingDriverState); -} - -static int32_t USART7_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = USART_NonBlockingPowerControl(state, &usart7_NonBlockingDriverState); -#if defined(USART7_RX_BUFFER_ENABLE) && (USART7_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (usart7_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - USART_TransferStartRingBuffer(usart7_NonBlockingDriverState.resource->base, - usart7_NonBlockingDriverState.handle, usart7_rxRingBuffer, USART_RX_BUFFER_LEN); - } -#endif - return result; -} - -static int32_t USART7_NonBlockingSend(const void *data, uint32_t num) -{ - return USART_NonBlockingSend(data, num, &usart7_NonBlockingDriverState); -} - -static int32_t USART7_NonBlockingReceive(void *data, uint32_t num) -{ - return USART_NonBlockingReceive(data, num, &usart7_NonBlockingDriverState); -} - -static int32_t USART7_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_NonBlockingTransfer(data_out, data_in, num, &usart7_NonBlockingDriverState); -} - -static uint32_t USART7_NonBlockingGetTxCount(void) -{ - return USART_NonBlockingGetTxCount(&usart7_NonBlockingDriverState); -} - -static uint32_t USART7_NonBlockingGetRxCount(void) -{ - return USART_NonBlockingGetRxCount(&usart7_NonBlockingDriverState); -} - -static int32_t USART7_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = USART_NonBlockingControl(control, arg, &usart7_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } -#if defined(USART7_RX_BUFFER_ENABLE) && (USART7_RX_BUFFER_ENABLE == 1) - /* Start receiving interrupts */ - usart7_NonBlockingDriverState.resource->base->FIFOINTENSET |= - USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -#endif - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS USART7_NonBlockingGetStatus(void) -{ - return USART_NonBlockingGetStatus(&usart7_NonBlockingDriverState); -} - -#endif - -ARM_DRIVER_USART Driver_USART7 = { - USARTx_GetVersion, USARTx_GetCapabilities, -#if RTE_USART7_DMA_EN - USART7_DmaInitialize, USART7_DmaUninitialize, USART7_DmaPowerControl, USART7_DmaSend, USART7_DmaReceive, - USART7_DmaTransfer, USART7_DmaGetTxCount, USART7_DmaGetRxCount, USART7_DmaControl, USART7_DmaGetStatus, -#else - USART7_NonBlockingInitialize, - USART7_NonBlockingUninitialize, - USART7_NonBlockingPowerControl, - USART7_NonBlockingSend, - USART7_NonBlockingReceive, - USART7_NonBlockingTransfer, - USART7_NonBlockingGetTxCount, - USART7_NonBlockingGetRxCount, - USART7_NonBlockingControl, - USART7_NonBlockingGetStatus, -#endif - USARTx_SetModemControl, USARTx_GetModemStatus}; - -#endif /* usart7 */ - -#if defined(USART8) && RTE_USART8 - -/* User needs to provide the implementation for USART8_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t USART8_GetFreq(void); -extern void USART8_InitPins(void); -extern void USART8_DeinitPins(void); - -cmsis_usart_resource_t usart8_Resource = {USART8, USART8_GetFreq}; - -#if RTE_USART8_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_usart_dma_resource_t usart8_DmaResource = { - RTE_USART8_DMA_TX_DMA_BASE, RTE_USART8_DMA_TX_CH, RTE_USART8_DMA_RX_DMA_BASE, RTE_USART8_DMA_RX_CH, -}; - -usart_dma_handle_t USART8_DmaHandle; -dma_handle_t USART8_DmaRxHandle; -dma_handle_t USART8_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("usart8_dma_driver_state") -cmsis_usart_dma_driver_state_t usart8_DmaDriverState = { -#else -cmsis_usart_dma_driver_state_t usart8_DmaDriverState = { -#endif - &usart8_Resource, &usart8_DmaResource, &USART8_DmaHandle, &USART8_DmaRxHandle, &USART8_DmaTxHandle, -}; - -static int32_t USART8_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART8_InitPins(); - return USART_DmaInitialize(cb_event, &usart8_DmaDriverState); -} - -static int32_t USART8_DmaUninitialize(void) -{ - USART8_DeinitPins(); - return USART_DmaUninitialize(&usart8_DmaDriverState); -} - -static int32_t USART8_DmaPowerControl(ARM_POWER_STATE state) -{ - return USART_DmaPowerControl(state, &usart8_DmaDriverState); -} - -static int32_t USART8_DmaSend(const void *data, uint32_t num) -{ - return USART_DmaSend(data, num, &usart8_DmaDriverState); -} - -static int32_t USART8_DmaReceive(void *data, uint32_t num) -{ - return USART_DmaReceive(data, num, &usart8_DmaDriverState); -} - -static int32_t USART8_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_DmaTransfer(data_out, data_in, num, &usart8_DmaDriverState); -} - -static uint32_t USART8_DmaGetTxCount(void) -{ - return USART_DmaGetTxCount(&usart8_DmaDriverState); -} - -static uint32_t USART8_DmaGetRxCount(void) -{ - return USART_DmaGetRxCount(&usart8_DmaDriverState); -} - -static int32_t USART8_DmaControl(uint32_t control, uint32_t arg) -{ - return USART_DmaControl(control, arg, &usart8_DmaDriverState); -} - -static ARM_USART_STATUS USART8_DmaGetStatus(void) -{ - return USART_DmaGetStatus(&usart8_DmaDriverState); -} - -#endif - -#else - -usart_handle_t USART8_Handle; -#if defined(USART8_RX_BUFFER_ENABLE) && (USART8_RX_BUFFER_ENABLE == 1) -static uint8_t usart8_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("usart8_non_blocking_driver_state") -cmsis_usart_non_blocking_driver_state_t usart8_NonBlockingDriverState = { -#else -cmsis_usart_non_blocking_driver_state_t usart8_NonBlockingDriverState = { -#endif - &usart8_Resource, &USART8_Handle, -}; - -static int32_t USART8_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART8_InitPins(); - return USART_NonBlockingInitialize(cb_event, &usart8_NonBlockingDriverState); -} - -static int32_t USART8_NonBlockingUninitialize(void) -{ - USART8_DeinitPins(); - return USART_NonBlockingUninitialize(&usart8_NonBlockingDriverState); -} - -static int32_t USART8_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = USART_NonBlockingPowerControl(state, &usart8_NonBlockingDriverState); -#if defined(USART8_RX_BUFFER_ENABLE) && (USART8_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (usart8_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - USART_TransferStartRingBuffer(usart8_NonBlockingDriverState.resource->base, - usart8_NonBlockingDriverState.handle, usart8_rxRingBuffer, USART_RX_BUFFER_LEN); - } -#endif - - return result; -} - -static int32_t USART8_NonBlockingSend(const void *data, uint32_t num) -{ - return USART_NonBlockingSend(data, num, &usart8_NonBlockingDriverState); -} - -static int32_t USART8_NonBlockingReceive(void *data, uint32_t num) -{ - return USART_NonBlockingReceive(data, num, &usart8_NonBlockingDriverState); -} - -static int32_t USART8_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_NonBlockingTransfer(data_out, data_in, num, &usart8_NonBlockingDriverState); -} - -static uint32_t USART8_NonBlockingGetTxCount(void) -{ - return USART_NonBlockingGetTxCount(&usart8_NonBlockingDriverState); -} - -static uint32_t USART8_NonBlockingGetRxCount(void) -{ - return USART_NonBlockingGetRxCount(&usart8_NonBlockingDriverState); -} - -static int32_t USART8_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = USART_NonBlockingControl(control, arg, &usart8_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } -#if defined(USART8_RX_BUFFER_ENABLE) && (USART8_RX_BUFFER_ENABLE == 1) - /* Start receiving interrupts */ - usart8_NonBlockingDriverState.resource->base->FIFOINTENSET |= - USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -#endif - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS USART8_NonBlockingGetStatus(void) -{ - return USART_NonBlockingGetStatus(&usart8_NonBlockingDriverState); -} - -#endif - -/* usart8 Driver Control Block */ -ARM_DRIVER_USART Driver_USART8 = { - USARTx_GetVersion, USARTx_GetCapabilities, -#if RTE_USART8_DMA_EN - USART8_DmaInitialize, USART8_DmaUninitialize, USART8_DmaPowerControl, USART8_DmaSend, USART8_DmaReceive, - USART8_DmaTransfer, USART8_DmaGetTxCount, USART8_DmaGetRxCount, USART8_DmaControl, USART8_DmaGetStatus, -#else - USART8_NonBlockingInitialize, - USART8_NonBlockingUninitialize, - USART8_NonBlockingPowerControl, - USART8_NonBlockingSend, - USART8_NonBlockingReceive, - USART8_NonBlockingTransfer, - USART8_NonBlockingGetTxCount, - USART8_NonBlockingGetRxCount, - USART8_NonBlockingControl, - USART8_NonBlockingGetStatus, -#endif - USARTx_SetModemControl, USARTx_GetModemStatus}; - -#endif /* usart8 */ - -#if defined(USART9) && RTE_USART9 - -/* User needs to provide the implementation for USART9_GetFreq/InitPins/DeinitPins -in the application for enabling according instance. */ -extern uint32_t USART9_GetFreq(void); -extern void USART9_InitPins(void); -extern void USART9_DeinitPins(void); - -cmsis_usart_resource_t usart9_Resource = {USART9, USART9_GetFreq}; - -#if RTE_USART9_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_usart_dma_resource_t usart9_DmaResource = { - RTE_USART9_DMA_TX_DMA_BASE, RTE_USART9_DMA_TX_CH, RTE_USART9_DMA_RX_DMA_BASE, RTE_USART9_DMA_RX_CH, -}; - -usart_dma_handle_t USART9_DmaHandle; -dma_handle_t USART9_DmaRxHandle; -dma_handle_t USART9_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("usart9_dma_driver_state") -cmsis_usart_dma_driver_state_t usart9_DmaDriverState = { -#else -cmsis_usart_dma_driver_state_t usart9_DmaDriverState = { -#endif - &usart9_Resource, &usart9_DmaResource, &USART9_DmaHandle, &USART9_DmaRxHandle, &USART9_DmaTxHandle, -}; - -static int32_t USART9_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART9_InitPins(); - return USART_DmaInitialize(cb_event, &usart9_DmaDriverState); -} - -static int32_t USART9_DmaUninitialize(void) -{ - USART9_DeinitPins(); - return USART_DmaUninitialize(&usart9_DmaDriverState); -} - -static int32_t USART9_DmaPowerControl(ARM_POWER_STATE state) -{ - return USART_DmaPowerControl(state, &usart9_DmaDriverState); -} - -static int32_t USART9_DmaSend(const void *data, uint32_t num) -{ - return USART_DmaSend(data, num, &usart9_DmaDriverState); -} - -static int32_t USART9_DmaReceive(void *data, uint32_t num) -{ - return USART_DmaReceive(data, num, &usart9_DmaDriverState); -} - -static int32_t USART9_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_DmaTransfer(data_out, data_in, num, &usart9_DmaDriverState); -} - -static uint32_t USART9_DmaGetTxCount(void) -{ - return USART_DmaGetTxCount(&usart9_DmaDriverState); -} - -static uint32_t USART9_DmaGetRxCount(void) -{ - return USART_DmaGetRxCount(&usart9_DmaDriverState); -} - -static int32_t USART9_DmaControl(uint32_t control, uint32_t arg) -{ - return USART_DmaControl(control, arg, &usart9_DmaDriverState); -} - -static ARM_USART_STATUS USART9_DmaGetStatus(void) -{ - return USART_DmaGetStatus(&usart9_DmaDriverState); -} - -#endif - -#else - -usart_handle_t USART9_Handle; -#if defined(USART9_RX_BUFFER_ENABLE) && (USART9_RX_BUFFER_ENABLE == 1) -static uint8_t usart9_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("usart9_non_blocking_driver_state") -cmsis_usart_non_blocking_driver_state_t usart9_NonBlockingDriverState = { -#else -cmsis_usart_non_blocking_driver_state_t usart9_NonBlockingDriverState = { -#endif - &usart9_Resource, &USART9_Handle, -}; - -static int32_t USART9_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - USART9_InitPins(); - return USART_NonBlockingInitialize(cb_event, &usart9_NonBlockingDriverState); -} - -static int32_t USART9_NonBlockingUninitialize(void) -{ - USART9_DeinitPins(); - return USART_NonBlockingUninitialize(&usart9_NonBlockingDriverState); -} - -static int32_t USART9_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = USART_NonBlockingPowerControl(state, &usart9_NonBlockingDriverState); -#if defined(USART9_RX_BUFFER_ENABLE) && (USART9_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (usart9_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - USART_TransferStartRingBuffer(usart9_NonBlockingDriverState.resource->base, - usart9_NonBlockingDriverState.handle, usart9_rxRingBuffer, USART_RX_BUFFER_LEN); - } -#endif - - return result; -} - -static int32_t USART9_NonBlockingSend(const void *data, uint32_t num) -{ - return USART_NonBlockingSend(data, num, &usart9_NonBlockingDriverState); -} - -static int32_t USART9_NonBlockingReceive(void *data, uint32_t num) -{ - return USART_NonBlockingReceive(data, num, &usart9_NonBlockingDriverState); -} - -static int32_t USART9_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return USART_NonBlockingTransfer(data_out, data_in, num, &usart9_NonBlockingDriverState); -} - -static uint32_t USART9_NonBlockingGetTxCount(void) -{ - return USART_NonBlockingGetTxCount(&usart9_NonBlockingDriverState); -} - -static uint32_t USART9_NonBlockingGetRxCount(void) -{ - return USART_NonBlockingGetRxCount(&usart9_NonBlockingDriverState); -} - -static int32_t USART9_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = USART_NonBlockingControl(control, arg, &usart9_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } -#if defined(USART9_RX_BUFFER_ENABLE) && (USART9_RX_BUFFER_ENABLE == 1) - /* Start receiving interrupts */ - usart9_NonBlockingDriverState.resource->base->FIFOINTENSET |= - USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -#endif - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS USART9_NonBlockingGetStatus(void) -{ - return USART_NonBlockingGetStatus(&usart9_NonBlockingDriverState); -} - -#endif - -/* usart9 Driver Control Block */ -ARM_DRIVER_USART Driver_USART9 = { - USARTx_GetVersion, USARTx_GetCapabilities, -#if RTE_USART9_DMA_EN - USART9_DmaInitialize, USART9_DmaUninitialize, USART9_DmaPowerControl, USART9_DmaSend, USART9_DmaReceive, - USART9_DmaTransfer, USART9_DmaGetTxCount, USART9_DmaGetRxCount, USART9_DmaControl, USART9_DmaGetStatus, -#else - USART9_NonBlockingInitialize, - USART9_NonBlockingUninitialize, - USART9_NonBlockingPowerControl, - USART9_NonBlockingSend, - USART9_NonBlockingReceive, - USART9_NonBlockingTransfer, - USART9_NonBlockingGetTxCount, - USART9_NonBlockingGetRxCount, - USART9_NonBlockingControl, - USART9_NonBlockingGetStatus, -#endif - USARTx_SetModemControl, USARTx_GetModemStatus}; - -#endif /* usart9 */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/cmsis_drivers/fsl_usart_cmsis.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/cmsis_drivers/fsl_usart_cmsis.h deleted file mode 100644 index 3e13dc33b67..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/cmsis_drivers/fsl_usart_cmsis.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_USART_CMSIS_H_ -#define _FSL_USART_CMSIS_H_ - -#include "fsl_common.h" -#include "Driver_USART.h" -#include "RTE_Device.h" -#include "fsl_usart.h" -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) -#include "fsl_usart_dma.h" -#endif - -#if defined(USART0) -extern ARM_DRIVER_USART Driver_USART0; -#endif /* USART0 */ - -#if defined(USART1) -extern ARM_DRIVER_USART Driver_USART1; -#endif /* USART1 */ - -#if defined(USART2) -extern ARM_DRIVER_USART Driver_USART2; -#endif /* USART2 */ - -#if defined(USART3) -extern ARM_DRIVER_USART Driver_USART3; -#endif /* USART3 */ - -#if defined(USART4) -extern ARM_DRIVER_USART Driver_USART4; -#endif /* USART4 */ - -#if defined(USART5) -extern ARM_DRIVER_USART Driver_USART5; -#endif /* USART5 */ - -#if defined(USART6) -extern ARM_DRIVER_USART Driver_USART6; -#endif /* USART6 */ - -#if defined(USART7) -extern ARM_DRIVER_USART Driver_USART7; -#endif /* USART7 */ - -#endif /* _FSL_USART_CMSIS_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/SConscript b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/SConscript deleted file mode 100644 index 46044bf7bed..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/SConscript +++ /dev/null @@ -1,11 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -CPPPATH = [cwd] -src = Glob('*.c') - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_adc.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_adc.c deleted file mode 100644 index 2c8b2cb1110..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_adc.c +++ /dev/null @@ -1,316 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_adc.h" -#include "fsl_clock.h" - -static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -static uint32_t ADC_GetInstance(ADC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_adcBases); instance++) - { - if (s_adcBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_adcBases)); - - return instance; -} - -void ADC_Init(ADC_Type *base, const adc_config_t *config) -{ - assert(config != NULL); - - uint32_t tmp32 = 0U; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable clock. */ - CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Disable the interrupts. */ - base->INTEN = 0U; /* Quickly disable all the interrupts. */ - - /* Configure the ADC block. */ - tmp32 = ADC_CTRL_CLKDIV(config->clockDividerNumber); - - /* Async or Sync clock mode. */ - switch (config->clockMode) - { - case kADC_ClockAsynchronousMode: - tmp32 |= ADC_CTRL_ASYNMODE_MASK; - break; - default: /* kADC_ClockSynchronousMode */ - break; - } - - /* Resolution. */ - tmp32 |= ADC_CTRL_RESOL(config->resolution); - - /* Bypass calibration. */ - if (config->enableBypassCalibration) - { - tmp32 |= ADC_CTRL_BYPASSCAL_MASK; - } - - /* Sample time clock count. */ - tmp32 |= ADC_CTRL_TSAMP(config->sampleTimeNumber); - - base->CTRL = tmp32; -} - -void ADC_GetDefaultConfig(adc_config_t *config) -{ - config->clockMode = kADC_ClockSynchronousMode; - config->clockDividerNumber = 0U; - config->resolution = kADC_Resolution12bit; - config->enableBypassCalibration = false; - config->sampleTimeNumber = 0U; -} - -void ADC_Deinit(ADC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -bool ADC_DoSelfCalibration(ADC_Type *base) -{ - uint32_t i; - - /* Enable the converter. */ - /* This bit acn only be set 1 by software. It is cleared automatically whenever the ADC is powered down. - This bit should be set after at least 10 ms after the ADC is powered on. */ - base->STARTUP = ADC_STARTUP_ADC_ENA_MASK; - for (i = 0U; i < 0x10; i++) /* Wait a few clocks to startup up. */ - { - __ASM("NOP"); - } - if (!(base->STARTUP & ADC_STARTUP_ADC_ENA_MASK)) - { - return false; /* ADC is not powered up. */ - } - - /* If not in by-pass mode, do the calibration. */ - if ((ADC_CALIB_CALREQD_MASK == (base->CALIB & ADC_CALIB_CALREQD_MASK)) && - (0U == (base->CTRL & ADC_CTRL_BYPASSCAL_MASK))) - { - /* Calibration is needed, do it now. */ - base->CALIB = ADC_CALIB_CALIB_MASK; - i = 0xF0000; - while ((ADC_CALIB_CALIB_MASK == (base->CALIB & ADC_CALIB_CALIB_MASK)) && (--i)) - { - } - if (i == 0U) - { - return false; /* Calibration timeout. */ - } - } - - /* A dummy conversion cycle will be performed. */ - base->STARTUP |= ADC_STARTUP_ADC_INIT_MASK; - i = 0x7FFFF; - while ((ADC_STARTUP_ADC_INIT_MASK == (base->STARTUP & ADC_STARTUP_ADC_INIT_MASK)) && (--i)) - { - } - if (i == 0U) - { - return false; - } - - return true; -} - -void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config) -{ - assert(config != NULL); - - uint32_t tmp32; - - tmp32 = ADC_SEQ_CTRL_CHANNELS(config->channelMask) /* Channel mask. */ - | ADC_SEQ_CTRL_TRIGGER(config->triggerMask); /* Trigger mask. */ - - /* Polarity for tirgger signal. */ - switch (config->triggerPolarity) - { - case kADC_TriggerPolarityPositiveEdge: - tmp32 |= ADC_SEQ_CTRL_TRIGPOL_MASK; - break; - default: /* kADC_TriggerPolarityNegativeEdge */ - break; - } - - /* Bypass the clock Sync. */ - if (config->enableSyncBypass) - { - tmp32 |= ADC_SEQ_CTRL_SYNCBYPASS_MASK; - } - - /* Interrupt point. */ - switch (config->interruptMode) - { - case kADC_InterruptForEachSequence: - tmp32 |= ADC_SEQ_CTRL_MODE_MASK; - break; - default: /* kADC_InterruptForEachConversion */ - break; - } - - /* One trigger for a conversion, or for a sequence. */ - if (config->enableSingleStep) - { - tmp32 |= ADC_SEQ_CTRL_SINGLESTEP_MASK; - } - - base->SEQ_CTRL[0] = tmp32; -} - -void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config) -{ - assert(config != NULL); - - uint32_t tmp32; - - tmp32 = ADC_SEQ_CTRL_CHANNELS(config->channelMask) /* Channel mask. */ - | ADC_SEQ_CTRL_TRIGGER(config->triggerMask); /* Trigger mask. */ - - /* Polarity for tirgger signal. */ - switch (config->triggerPolarity) - { - case kADC_TriggerPolarityPositiveEdge: - tmp32 |= ADC_SEQ_CTRL_TRIGPOL_MASK; - break; - default: /* kADC_TriggerPolarityPositiveEdge */ - break; - } - - /* Bypass the clock Sync. */ - if (config->enableSyncBypass) - { - tmp32 |= ADC_SEQ_CTRL_SYNCBYPASS_MASK; - } - - /* Interrupt point. */ - switch (config->interruptMode) - { - case kADC_InterruptForEachSequence: - tmp32 |= ADC_SEQ_CTRL_MODE_MASK; - break; - default: /* kADC_InterruptForEachConversion */ - break; - } - - /* One trigger for a conversion, or for a sequence. */ - if (config->enableSingleStep) - { - tmp32 |= ADC_SEQ_CTRL_SINGLESTEP_MASK; - } - - base->SEQ_CTRL[1] = tmp32; -} - -bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info) -{ - assert(info != NULL); - - uint32_t tmp32 = base->SEQ_GDAT[0]; /* Read to clear the status. */ - - if (0U == (ADC_SEQ_GDAT_DATAVALID_MASK & tmp32)) - { - return false; - } - - info->result = (tmp32 & ADC_SEQ_GDAT_RESULT_MASK) >> ADC_SEQ_GDAT_RESULT_SHIFT; - info->thresholdCompareStatus = - (adc_threshold_compare_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPRANGE_MASK) >> ADC_SEQ_GDAT_THCMPRANGE_SHIFT); - info->thresholdCorssingStatus = - (adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT); - info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT; - info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK); - - return true; -} - -bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info) -{ - assert(info != NULL); - - uint32_t tmp32 = base->SEQ_GDAT[1]; /* Read to clear the status. */ - - if (0U == (ADC_SEQ_GDAT_DATAVALID_MASK & tmp32)) - { - return false; - } - - info->result = (tmp32 & ADC_SEQ_GDAT_RESULT_MASK) >> ADC_SEQ_GDAT_RESULT_SHIFT; - info->thresholdCompareStatus = - (adc_threshold_compare_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPRANGE_MASK) >> ADC_SEQ_GDAT_THCMPRANGE_SHIFT); - info->thresholdCorssingStatus = - (adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT); - info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT; - info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK); - - return true; -} - -bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info) -{ - assert(info != NULL); - assert(channel < ADC_DAT_COUNT); - - uint32_t tmp32 = base->DAT[channel]; /* Read to clear the status. */ - - if (0U == (ADC_DAT_DATAVALID_MASK & tmp32)) - { - return false; - } - - info->result = (tmp32 & ADC_DAT_RESULT_MASK) >> ADC_DAT_RESULT_SHIFT; - info->thresholdCompareStatus = - (adc_threshold_compare_status_t)((tmp32 & ADC_DAT_THCMPRANGE_MASK) >> ADC_DAT_THCMPRANGE_SHIFT); - info->thresholdCorssingStatus = - (adc_threshold_crossing_status_t)((tmp32 & ADC_DAT_THCMPCROSS_MASK) >> ADC_DAT_THCMPCROSS_SHIFT); - info->channelNumber = (tmp32 & ADC_DAT_CHANNEL_MASK) >> ADC_DAT_CHANNEL_SHIFT; - info->overrunFlag = ((tmp32 & ADC_DAT_OVERRUN_MASK) == ADC_DAT_OVERRUN_MASK); - - return true; -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_adc.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_adc.h deleted file mode 100644 index 6db5030cd8c..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_adc.h +++ /dev/null @@ -1,664 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __FSL_ADC_H__ -#define __FSL_ADC_H__ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_adc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief ADC driver version 2.0.0. */ -#define LPC_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! - * @brief Flags - */ -enum _adc_status_flags -{ - kADC_ThresholdCompareFlagOnChn0 = 1U << 0U, /*!< Threshold comparison event on Channel 0. */ - kADC_ThresholdCompareFlagOnChn1 = 1U << 1U, /*!< Threshold comparison event on Channel 1. */ - kADC_ThresholdCompareFlagOnChn2 = 1U << 2U, /*!< Threshold comparison event on Channel 2. */ - kADC_ThresholdCompareFlagOnChn3 = 1U << 3U, /*!< Threshold comparison event on Channel 3. */ - kADC_ThresholdCompareFlagOnChn4 = 1U << 4U, /*!< Threshold comparison event on Channel 4. */ - kADC_ThresholdCompareFlagOnChn5 = 1U << 5U, /*!< Threshold comparison event on Channel 5. */ - kADC_ThresholdCompareFlagOnChn6 = 1U << 6U, /*!< Threshold comparison event on Channel 6. */ - kADC_ThresholdCompareFlagOnChn7 = 1U << 7U, /*!< Threshold comparison event on Channel 7. */ - kADC_ThresholdCompareFlagOnChn8 = 1U << 8U, /*!< Threshold comparison event on Channel 8. */ - kADC_ThresholdCompareFlagOnChn9 = 1U << 9U, /*!< Threshold comparison event on Channel 9. */ - kADC_ThresholdCompareFlagOnChn10 = 1U << 10U, /*!< Threshold comparison event on Channel 10. */ - kADC_ThresholdCompareFlagOnChn11 = 1U << 11U, /*!< Threshold comparison event on Channel 11. */ - kADC_OverrunFlagForChn0 = - 1U << 12U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 0. */ - kADC_OverrunFlagForChn1 = - 1U << 13U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 1. */ - kADC_OverrunFlagForChn2 = - 1U << 14U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 2. */ - kADC_OverrunFlagForChn3 = - 1U << 15U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 3. */ - kADC_OverrunFlagForChn4 = - 1U << 16U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 4. */ - kADC_OverrunFlagForChn5 = - 1U << 17U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 5. */ - kADC_OverrunFlagForChn6 = - 1U << 18U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 6. */ - kADC_OverrunFlagForChn7 = - 1U << 19U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 7. */ - kADC_OverrunFlagForChn8 = - 1U << 20U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 8. */ - kADC_OverrunFlagForChn9 = - 1U << 21U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 9. */ - kADC_OverrunFlagForChn10 = - 1U << 22U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 10. */ - kADC_OverrunFlagForChn11 = - 1U << 23U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 11. */ - kADC_GlobalOverrunFlagForSeqA = 1U << 24U, /*!< Mirror the glabal OVERRUN status flag for conversion sequence A. */ - kADC_GlobalOverrunFlagForSeqB = 1U << 25U, /*!< Mirror the global OVERRUN status flag for conversion sequence B. */ - kADC_ConvSeqAInterruptFlag = 1U << 28U, /*!< Sequence A interrupt/DMA trigger. */ - kADC_ConvSeqBInterruptFlag = 1U << 29U, /*!< Sequence B interrupt/DMA trigger. */ - kADC_ThresholdCompareInterruptFlag = 1U << 30U, /*!< Threshold comparision interrupt flag. */ - kADC_OverrunInterruptFlag = 1U << 31U, /*!< Overrun interrupt flag. */ -}; - -/*! - * @brief Interrupts - * @note Not all the interrupt options are listed here - */ -enum _adc_interrupt_enable -{ - kADC_ConvSeqAInterruptEnable = ADC_INTEN_SEQA_INTEN_MASK, /*!< Enable interrupt upon completion of each individual - conversion in sequence A, or entire sequence. */ - kADC_ConvSeqBInterruptEnable = ADC_INTEN_SEQB_INTEN_MASK, /*!< Enable interrupt upon completion of each individual - conversion in sequence B, or entire sequence. */ - kADC_OverrunInterruptEnable = ADC_INTEN_OVR_INTEN_MASK, /*!< Enable the detection of an overrun condition on any of - the channel data registers will cause an overrun - interrupt/DMA trigger. */ -}; - -/*! - * @brief Define selection of clock mode. - */ -typedef enum _adc_clock_mode -{ - kADC_ClockSynchronousMode = - 0U, /*!< The ADC clock would be derived from the system clock based on "clockDividerNumber". */ - kADC_ClockAsynchronousMode = 1U, /*!< The ADC clock would be based on the SYSCON block's divider. */ -} adc_clock_mode_t; - -/*! - * @brief Define selection of resolution. - */ -typedef enum _adc_resolution -{ - kADC_Resolution6bit = 0U, /*!< 6-bit resolution. */ - kADC_Resolution8bit = 1U, /*!< 8-bit resolution. */ - kADC_Resolution10bit = 2U, /*!< 10-bit resolution. */ - kADC_Resolution12bit = 3U, /*!< 12-bit resolution. */ -} adc_resolution_t; - -/*! - * @brief Define selection of polarity of selected input trigger for conversion sequence. - */ -typedef enum _adc_trigger_polarity -{ - kADC_TriggerPolarityNegativeEdge = 0U, /*!< A negative edge launches the conversion sequence on the trigger(s). */ - kADC_TriggerPolarityPositiveEdge = 1U, /*!< A positive edge launches the conversion sequence on the trigger(s). */ -} adc_trigger_polarity_t; - -/*! - * @brief Define selection of conversion sequence's priority. - */ -typedef enum _adc_priority -{ - kADC_PriorityLow = 0U, /*!< This sequence would be preempted when another sequence is started. */ - kADC_PriorityHigh = 1U, /*!< This sequence would preempt other sequence even when is is started. */ -} adc_priority_t; - -/*! - * @brief Define selection of conversion sequence's interrupt. - */ -typedef enum _adc_seq_interrupt_mode -{ - kADC_InterruptForEachConversion = 0U, /*!< The sequence interrupt/DMA trigger will be set at the end of each - individual ADC conversion inside this conversion sequence. */ - kADC_InterruptForEachSequence = 1U, /*!< The sequence interrupt/DMA trigger will be set when the entire set of - this sequence conversions completes. */ -} adc_seq_interrupt_mode_t; - -/*! - * @brief Define status of threshold compare result. - */ -typedef enum _adc_threshold_compare_status -{ - kADC_ThresholdCompareInRange = 0U, /*!< LOW threshold <= conversion value <= HIGH threshold. */ - kADC_ThresholdCompareBelowRange = 1U, /*!< conversion value < LOW threshold. */ - kADC_ThresholdCompareAboveRange = 2U, /*!< conversion value > HIGH threshold. */ -} adc_threshold_compare_status_t; - -/*! - * @brief Define status of threshold crossing detection result. - */ -typedef enum _adc_threshold_crossing_status -{ - /* The conversion on this channel had the same relationship (above or below) to the threshold value established by - * the designated LOW threshold value as did the previous conversion on this channel. */ - kADC_ThresholdCrossingNoDetected = 0U, /*!< No threshold Crossing detected. */ - - /* Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this - * channel was above the threshold value established by the designated LOW threshold value and the current sample is - * below that threshold. */ - kADC_ThresholdCrossingDownward = 2U, /*!< Downward Threshold Crossing detected. */ - - /* Indicates that a thre shold crossing in the upward direction has occurred - i.e. the previous sample on this - * channel was below the threshold value established by the designated LOW threshold value and the current sample is - * above that threshold. */ - kADC_ThresholdCrossingUpward = 3U, /*!< Upward Threshold Crossing Detected. */ -} adc_threshold_crossing_status_t; - -/*! - * @brief Define interrupt mode for threshold compare event. - */ -typedef enum _adc_threshold_interrupt_mode -{ - kADC_ThresholdInterruptDisabled = 0U, /*!< Threshold comparison interrupt is disabled. */ - kADC_ThresholdInterruptOnOutside = 1U, /*!< Threshold comparison interrupt is enabled on outside threshold. */ - kADC_ThresholdInterruptOnCrossing = 2U, /*!< Threshold comparison interrupt is enabled on crossing threshold. */ -} adc_threshold_interrupt_mode_t; - -/*! - * @brief Define structure for configuring the block. - */ -typedef struct _adc_config -{ - adc_clock_mode_t clockMode; /*!< Select the clock mode for ADC converter. */ - uint32_t clockDividerNumber; /*!< This field is only available when using kADC_ClockSynchronousMode for "clockMode" - field. The divider would be plused by 1 based on the value in this field. The - available range is in 8 bits. */ - adc_resolution_t resolution; /*!< Select the conversion bits. */ - bool enableBypassCalibration; /*!< By default, a calibration cycle must be performed each time the chip is - powered-up. Re-calibration may be warranted periodically - especially if - operating conditions have changed. To enable this option would avoid the need to - calibrate if offset error is not a concern in the application. */ - uint32_t sampleTimeNumber; /*!< By default, with value as "0U", the sample period would be 2.5 ADC clocks. Then, - to plus the "sampleTimeNumber" value here. The available value range is in 3 bits.*/ -} adc_config_t; - -/*! - * @brief Define structure for configuring conversion sequence. - */ -typedef struct _adc_conv_seq_config -{ - uint32_t channelMask; /*!< Selects which one or more of the ADC channels will be sampled and converted when this - sequence is launched. The masked channels would be involved in current conversion - sequence, beginning with the lowest-order. The available range is in 12-bit. */ - uint32_t triggerMask; /*!< Selects which one or more of the available hardware trigger sources will cause this - conversion sequence to be initiated. The available range is 6-bit.*/ - adc_trigger_polarity_t triggerPolarity; /*!< Select the trigger to lauch conversion sequence. */ - bool enableSyncBypass; /*!< To enable this feature allows the hardware trigger input to bypass synchronization - flip-flop stages and therefore shorten the time between the trigger input signal and the - start of a conversion. */ - bool enableSingleStep; /*!< When enabling this feature, a trigger will launch a single conversion on the next - channel in the sequence instead of the default response of launching an entire sequence - of conversions. */ - adc_seq_interrupt_mode_t interruptMode; /*!< Select the interrpt/DMA trigger mode. */ -} adc_conv_seq_config_t; - -/*! - * @brief Define structure of keeping conversion result information. - */ -typedef struct _adc_result_info -{ - uint32_t result; /*!< Keey the conversion data value. */ - adc_threshold_compare_status_t thresholdCompareStatus; /*!< Keep the threshold compare status. */ - adc_threshold_crossing_status_t thresholdCorssingStatus; /*!< Keep the threshold crossing status. */ - uint32_t channelNumber; /*!< Keep the channel number for this conversion. */ - bool overrunFlag; /*!< Keep the status whether the conversion is overrun or not. */ - /* The data available flag would be returned by the reading result API. */ -} adc_result_info_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @name Initialization and Deinitialization - * @{ - */ - -/*! - * @brief Initialize the ADC module. - * - * @param base ADC peripheral base address. - * @param config Pointer to configuration structure, see to #adc_config_t. - */ -void ADC_Init(ADC_Type *base, const adc_config_t *config); - -/*! - * @brief Deinitialize the ADC module. - * - * @param base ADC peripheral base address. - */ -void ADC_Deinit(ADC_Type *base); - -/*! - * @brief Gets an available pre-defined settings for initial configuration. - * - * This function initializes the initial configuration structure with an available settings. The default values are: - * @code - * config->clockMode = kADC_ClockSynchronousMode; - * config->clockDividerNumber = 0U; - * config->resolution = kADC_Resolution12bit; - * config->enableBypassCalibration = false; - * config->sampleTimeNumber = 0U; - * @endcode - * @param config Pointer to configuration structure. - */ -void ADC_GetDefaultConfig(adc_config_t *config); - -/*! - * @brief Do the self hardware calibration. - * - * @param base ADC peripheral base address. - * @retval true Calibration succeed. - * @retval false Calibration failed. - */ -bool ADC_DoSelfCalibration(ADC_Type *base); - -/*! - * @brief Enable the internal temperature sensor measurement. - * - * When enabling the internal temperature sensor measurement, the channel 0 would be connected to internal sensor - * instead of external pin. - * - * @param base ADC peripheral base address. - * @param enable Switcher to enable the feature or not. - */ -static inline void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable) -{ - if (enable) - { - base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0x3); - } - else - { - base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0); - } -} - -/* @} */ - -/*! - * @name Control conversion sequence A. - * @{ - */ - -/*! - * @brief Enable the conversion sequence A. - * - * In order to avoid spuriously triggering the sequence, the trigger to conversion sequence should be ready before the - * sequence is ready. when the sequence is disabled, the trigger would be ignored. Also, it is suggested to disable the - * sequence during changing the sequence's setting. - * - * @param base ADC peripheral base address. - * @param enable Switcher to enable the feature or not. - */ -static inline void ADC_EnableConvSeqA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_SEQ_ENA_MASK; - } - else - { - base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_SEQ_ENA_MASK; - } -} - -/*! - * @brief Configure the conversion sequence A. - * - * @param base ADC peripheral base address. - * @param config Pointer to configuration structure, see to #adc_conv_seq_config_t. - */ -void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config); - -/*! - * @brief Do trigger the sequence's conversion by software. - * - * @param base ADC peripheral base address. - */ -static inline void ADC_DoSoftwareTriggerConvSeqA(ADC_Type *base) -{ - base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_START_MASK; -} - -/*! - * @brief Enable the burst conversion of sequence A. - * - * Enable the burst mode would cause the conversion sequence to be cntinuously cycled through. Other triggers would be - * ignored while this mode is enabled. Repeated conversions could be halted by disabling this mode. And the sequence - * currently in process will be completed before cnversions are terminated. - * Note that a new sequence could begin just before the burst mode is disabled. - * - * @param base ADC peripheral base address. - * @param enable Switcher to enable this feature. - */ -static inline void ADC_EnableConvSeqABurstMode(ADC_Type *base, bool enable) -{ - if (enable) - { - base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_BURST_MASK; - } - else - { - base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_BURST_MASK; - } -} - -/*! - * @brief Set the high priority for conversion sequence A. - * - * @param base ADC peripheral bass address. - */ -static inline void ADC_SetConvSeqAHighPriority(ADC_Type *base) -{ - base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_LOWPRIO_MASK; -} - -/* @} */ - -/*! - * @name Control conversion sequence B. - * @{ - */ - -/*! - * @brief Enable the conversion sequence B. - * - * In order to avoid spuriously triggering the sequence, the trigger to conversion sequence should be ready before the - * sequence is ready. when the sequence is disabled, the trigger would be ignored. Also, it is suggested to disable the - * sequence during changing the sequence's setting. - * - * @param base ADC peripheral base address. - * @param enable Switcher to enable the feature or not. - */ -static inline void ADC_EnableConvSeqB(ADC_Type *base, bool enable) -{ - if (enable) - { - base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_SEQ_ENA_MASK; - } - else - { - base->SEQ_CTRL[1] &= ~ADC_SEQ_CTRL_SEQ_ENA_MASK; - } -} - -/*! - * @brief Configure the conversion sequence B. - * - * @param base ADC peripheral base address. - * @param config Pointer to configuration structure, see to #adc_conv_seq_config_t. - */ -void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config); - -/*! - * @brief Do trigger the sequence's conversion by software. - * - * @param base ADC peripheral base address. - */ -static inline void ADC_DoSoftwareTriggerConvSeqB(ADC_Type *base) -{ - base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_START_MASK; -} - -/*! - * @brief Enable the burst conversion of sequence B. - * - * Enable the burst mode would cause the conversion sequence to be continuously cycled through. Other triggers would be - * ignored while this mode is enabled. Repeated conversions could be halted by disabling this mode. And the sequence - * currently in process will be completed before cnversions are terminated. - * Note that a new sequence could begin just before the burst mode is disabled. - * - * @param base ADC peripheral base address. - * @param enable Switcher to enable this feature. - */ -static inline void ADC_EnableConvSeqBBurstMode(ADC_Type *base, bool enable) -{ - if (enable) - { - base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_BURST_MASK; - } - else - { - base->SEQ_CTRL[1] &= ~ADC_SEQ_CTRL_BURST_MASK; - } -} - -/*! - * @brief Set the high priority for conversion sequence B. - * - * @param base ADC peripheral bass address. - */ -static inline void ADC_SetConvSeqBHighPriority(ADC_Type *base) -{ - base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_LOWPRIO_MASK; -} - -/* @} */ - -/*! - * @name Data result. - * @{ - */ - -/*! - * @brief Get the global ADC conversion infomation of sequence A. - * - * @param base ADC peripheral base address. - * @param info Pointer to information structure, see to #adc_result_info_t; - * @retval true The conversion result is ready. - * @retval false The conversion result is not ready yet. - */ -bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info); - -/*! - * @brief Get the global ADC conversion infomation of sequence B. - * - * @param base ADC peripheral base address. - * @param info Pointer to information structure, see to #adc_result_info_t; - * @retval true The conversion result is ready. - * @retval false The conversion result is not ready yet. - */ -bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info); - -/*! - * @brief Get the channel's ADC conversion completed under each conversion sequence. - * - * @param base ADC peripheral base address. - * @param channel The indicated channel number. - * @param info Pointer to information structure, see to #adc_result_info_t; - * @retval true The conversion result is ready. - * @retval false The conversion result is not ready yet. - */ -bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info); - -/* @} */ - -/*! - * @name Threshold function. - * @{ - */ - -/*! - * @brief Set the threshhold pair 0 with low and high value. - * - * @param base ADC peripheral base address. - * @param lowValue LOW threshold value. - * @param highValue HIGH threshold value. - */ -static inline void ADC_SetThresholdPair0(ADC_Type *base, uint32_t lowValue, uint32_t highValue) -{ - base->THR0_LOW = ADC_THR0_LOW_THRLOW(lowValue); - base->THR0_HIGH = ADC_THR0_HIGH_THRHIGH(highValue); -} - -/*! - * @brief Set the threshhold pair 1 with low and high value. - * - * @param base ADC peripheral base address. - * @param lowValue LOW threshold value. The available value is with 12-bit. - * @param highValue HIGH threshold value. The available value is with 12-bit. - */ -static inline void ADC_SetThresholdPair1(ADC_Type *base, uint32_t lowValue, uint32_t highValue) -{ - base->THR1_LOW = ADC_THR1_LOW_THRLOW(lowValue); - base->THR1_HIGH = ADC_THR1_HIGH_THRHIGH(highValue); -} - -/*! - * @brief Set given channels to apply the threshold pare 0. - * - * @param base ADC peripheral base address. - * @param channelMask Indicated channels' mask. - */ -static inline void ADC_SetChannelWithThresholdPair0(ADC_Type *base, uint32_t channelMask) -{ - base->CHAN_THRSEL &= ~(channelMask); -} - -/*! - * @brief Set given channels to apply the threshold pare 1. - * - * @param base ADC peripheral base address. - * @param channelMask Indicated channels' mask. - */ -static inline void ADC_SetChannelWithThresholdPair1(ADC_Type *base, uint32_t channelMask) -{ - base->CHAN_THRSEL |= channelMask; -} - -/* @} */ - -/*! - * @name Interrupts. - * @{ - */ - -/*! - * @brief Enable interrupts for conversion sequences. - * - * @param base ADC peripheral base address. - * @param mask Mask of interrupt mask value for global block except each channal, see to #_adc_interrupt_enable. - */ -static inline void ADC_EnableInterrupts(ADC_Type *base, uint32_t mask) -{ - base->INTEN |= (0x7 & mask); -} - -/*! - * @brief Disable interrupts for conversion sequence. - * - * @param base ADC peripheral base address. - * @param mask Mask of interrupt mask value for global block except each channel, see to #_adc_interrupt_enable. - */ -static inline void ADC_DisableInterrupts(ADC_Type *base, uint32_t mask) -{ - base->INTEN &= ~(0x7 & mask); -} - -/*! - * @brief Enable the interrupt of shreshold compare event for each channel. - * - * @param base ADC peripheral base address. - * @param channel Channel number. - * @param mode Interrupt mode for threshold compare event, see to #adc_threshold_interrupt_mode_t. - */ -static inline void ADC_EnableShresholdCompareInterrupt(ADC_Type *base, - uint32_t channel, - adc_threshold_interrupt_mode_t mode) -{ - base->INTEN = (base->INTEN & ~(0x3U << ((channel << 1U) + 3U))) | ((uint32_t)(mode) << ((channel << 1U) + 3U)); -} - -/* @} */ - -/*! - * @name Status. - * @{ - */ - -/*! - * @brief Get status flags of ADC module. - * - * @param base ADC peripheral base address. - * @return Mask of status flags of module, see to #_adc_status_flags. - */ -static inline uint32_t ADC_GetStatusFlags(ADC_Type *base) -{ - return base->FLAGS; -} - -/*! - * @brief Clear status flags of ADC module. - * - * @param base ADC peripheral base address. - * @param mask Mask of status flags of module, see to #_adc_status_flags. - */ -static inline void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) -{ - base->FLAGS = mask; /* Write 1 to clear. */ -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/* @} */ - -#endif /* __FSL_ADC_H__ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_clock.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_clock.c deleted file mode 100644 index 90a32de9d36..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_clock.c +++ /dev/null @@ -1,2169 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016 - 2017 , NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_common.h" -#include "fsl_clock.h" -#include "fsl_power.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define NVALMAX (0x100U) -#define PVALMAX (0x20U) -#define MVALMAX (0x8000U) - -#define USB_NVALMAX (0x4U) -#define USB_PVALMAX (0x8U) -#define USB_MVALMAX (0x100U) - -#define PLL_MAX_N_DIV 0x100U -#define USB_PLL_MAX_N_DIV 0x100U - -#define INDEX_SECTOR_TRIM48 ((uint32_t *)0x01000448U) -#define INDEX_SECTOR_TRIM96 ((uint32_t *)0x0100044CU) -/*-------------------------------------------------------------------------- -!!! If required these #defines can be moved to chip library file -----------------------------------------------------------------------------*/ - -#define PLL_MDEC_VAL_P (0U) /*!< MDEC is in bits 16 downto 0 */ -#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P) /*!< NDEC is in bits 9 downto 0 */ -#define PLL_NDEC_VAL_P (0U) /*!< NDEC is in bits 9:0 */ -#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P) -#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */ -#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P) - -#define PLL_MIN_CCO_FREQ_MHZ (275000000U) -#define PLL_MAX_CCO_FREQ_MHZ (550000000U) -#define PLL_LOWER_IN_LIMIT (4000U) /*!< Minimum PLL input rate */ -#define PLL_MIN_IN_SSMODE (2000000U) -#define PLL_MAX_IN_SSMODE (4000000U) - -/*!< Middle of the range values for spread-spectrum */ -#define PLL_SSCG_MF_FREQ_VALUE 4U -#define PLL_SSCG_MC_COMP_VALUE 2U -#define PLL_SSCG_MR_DEPTH_VALUE 4U -#define PLL_SSCG_DITHER_VALUE 0U - -/*!< USB PLL CCO MAX AND MIN FREQ */ -#define USB_PLL_MIN_CCO_FREQ_MHZ (156000000U) -#define USB_PLL_MAX_CCO_FREQ_MHZ (320000000U) -#define USB_PLL_LOWER_IN_LIMIT (1000000U) /*!< Minimum PLL input rate */ - -#define USB_PLL_MSEL_VAL_P (0U) /*!< MSEL is in bits 7 downto 0 */ -#define USB_PLL_MSEL_VAL_M (0xFFU) -#define USB_PLL_PSEL_VAL_P (8U) /*!< PDEC is in bits 9:8 */ -#define USB_PLL_PSEL_VAL_M (0x3U) -#define USB_PLL_NSEL_VAL_P (10U) /*!< NDEC is in bits 11:10 */ -#define USB_PLL_NSEL_VAL_M (0x3U) - -/*!< SWITCH USB POSTDIVIDER FOR REGITSER WRITING */ -#define SWITCH_USB_PSEL(x) ((x==0x0U) ? 0x1U : (x==0x1U) ? 0x02U : (x==0x2U) ? 0x4U : (x==3U) ? 0x8U : 0U) - -/*!< SYS PLL NDEC reg */ -#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) -/*!< SYS PLL PDEC reg */ -#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M) -/*!< SYS PLL MDEC reg */ -#define PLL_MDEC_VAL_SET(value) (((unsigned long)(value) << PLL_MDEC_VAL_P) & PLL_MDEC_VAL_M) - -/*!< SYS PLL NSEL reg */ -#define USB_PLL_NSEL_VAL_SET(value) (((unsigned long)(value) & USB_PLL_NSEL_VAL_M) << USB_PLL_NSEL_VAL_P) -/*!< SYS PLL PSEL reg */ -#define USB_PLL_PSEL_VAL_SET(value) (((unsigned long)(value) & USB_PLL_PSEL_VAL_M) << USB_PLL_PSEL_VAL_P) -/*!< SYS PLL MSEL reg */ -#define USB_PLL_MSEL_VAL_SET(value) (((unsigned long)(value) & USB_PLL_MSEL_VAL_M) << USB_PLL_MSEL_VAL_P) - -/*!< FRAC control */ -#define AUDIO_PLL_FRACT_MD_P (0U) -#define AUDIO_PLL_FRACT_MD_INT_P (15U) -#define AUDIO_PLL_FRACT_MD_M (0x7FFFUL << AUDIO_PLL_FRACT_MD_P) -#define AUDIO_PLL_FRACT_MD_INT_M (0x7FUL << AUDIO_PLL_FRACT_MD_INT_P) - -#define AUDIO_PLL_MD_FRACT_SET(value) (((unsigned long)(value) << AUDIO_PLL_FRACT_MD_P) & PLL_FRAC_MD_FRACT_M) -#define AUDIO_PLL_MD_INT_SET(value) (((unsigned long)(value) << AUDIO_PLL_FRACT_MD_INT_P) & AUDIO_PLL_FRACT_MD_INT_M) - -/* Saved value of PLL output rate, computed whenever needed to save run-time - computation on each call to retrive the PLL rate. */ -static uint32_t s_Pll_Freq; -static uint32_t s_Usb_Pll_Freq; -static uint32_t s_Audio_Pll_Freq; - - -/** External clock rate on the CLKIN pin in Hz. If not used, - set this to 0. Otherwise, set it to the exact rate in Hz this pin is - being driven at. */ -const uint32_t g_I2S_Mclk_Freq = 0U; -const uint32_t g_Ext_Clk_Freq = 12000000U; -const uint32_t g_Lcd_Clk_In_Freq = 0U; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/* Find encoded NDEC value for raw N value, max N = NVALMAX */ -static uint32_t pllEncodeN(uint32_t N); -/* Find decoded N value for raw NDEC value */ -static uint32_t pllDecodeN(uint32_t NDEC); -/* Find encoded PDEC value for raw P value, max P = PVALMAX */ -static uint32_t pllEncodeP(uint32_t P); -/* Find decoded P value for raw PDEC value */ -static uint32_t pllDecodeP(uint32_t PDEC); -/* Find encoded MDEC value for raw M value, max M = MVALMAX */ -static uint32_t pllEncodeM(uint32_t M); -/* Find decoded M value for raw MDEC value */ -static uint32_t pllDecodeM(uint32_t MDEC); -/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ -static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); -/* Get predivider (N) from PLL NDEC setting */ -static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg); -/* Get postdivider (P) from PLL PDEC setting */ -static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg); -/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ -static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg); -/* Get the greatest common divisor */ -static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); -/* Set PLL output based on desired output rate */ -static pll_error_t CLOCK_GetPllConfig( - uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup); - -/* Update local PLL rate variable */ -static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup); -static void CLOCK_GetAudioPLLOutFromSetupUpdate(pll_setup_t *pSetup); - -static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46, - 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61}; -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Clock Selection for IP */ -void CLOCK_AttachClk(clock_attach_id_t connection) -{ - bool final_descriptor = false; - uint8_t mux; - uint8_t pos; - uint32_t i; - volatile uint32_t *pClkSel; - - pClkSel = &(SYSCON->MAINCLKSELA); - - for (i = 0U; (i <= 2U) && (!final_descriptor); i++) - { - connection = (clock_attach_id_t)(connection >> (i * 12U)); /*!< pick up next descriptor */ - mux = (uint8_t)connection; - if (connection) - { - pos = ((connection & 0xf00U) >> 8U) - 1U; - if (mux == CM_ASYNCAPB) - { - SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1); - ASYNC_SYSCON->ASYNCAPBCLKSELA = pos; - } - else - { - pClkSel[mux] = pos; - } - } - else - { - final_descriptor = true; - } - } -} - -/* Set IP Clock Divider */ -void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) -{ - volatile uint32_t *pClkDiv; - - pClkDiv = &(SYSCON->SYSTICKCLKDIV); - if (reset) - { - pClkDiv[div_name] = 1U << 29U; - } - if (divided_by_value == 0U) /*!< halt */ - { - pClkDiv[div_name] = 1U << 30U; - } - else - { - pClkDiv[div_name] = (divided_by_value - 1U); - } -} - -/* Set FRO Clocking */ -status_t CLOCK_SetupFROClocking(uint32_t iFreq) -{ - uint32_t usb_adj; - if ((iFreq != 12000000U) && (iFreq != 48000000U) && (iFreq != 96000000U)) - { - return kStatus_Fail; - } - /* Power up the FRO and set this as the base clock */ - POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); - /* back up the value of whether USB adj is selected, in which case we will have a value of 1 else 0 */ - usb_adj = ((SYSCON->FROCTRL) & SYSCON_FROCTRL_USBCLKADJ_MASK) >> SYSCON_FROCTRL_USBCLKADJ_SHIFT; - if (iFreq > 12000000U) - { - if (iFreq == 96000000U) - { - SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM96) | - SYSCON_FROCTRL_SEL(1) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) | - SYSCON_FROCTRL_HSPDCLK(1); - } - else - { - SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM48) | - SYSCON_FROCTRL_SEL(0) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) | - SYSCON_FROCTRL_HSPDCLK(1); - } - } - else - { - SYSCON->FROCTRL &= ~SYSCON_FROCTRL_HSPDCLK(1); - } - - return 0U; -} - -/* Get CLOCK OUT Clk */ -uint32_t CLOCK_GetClockOutClkFreq(void) -{ - return (SYSCON->CLKOUTSELA == 0U) ? CLOCK_GetCoreSysClkFreq(): - (SYSCON->CLKOUTSELA == 1U) ? CLOCK_GetExtClkFreq(): - (SYSCON->CLKOUTSELA == 2U) ? CLOCK_GetWdtOscFreq(): - (SYSCON->CLKOUTSELA == 3U) ? CLOCK_GetFroHfFreq(): - (SYSCON->CLKOUTSELA == 4U) ? CLOCK_GetPllOutFreq(): - (SYSCON->CLKOUTSELA == 5U) ? CLOCK_GetUsbPllOutFreq(): - (SYSCON->CLKOUTSELA == 6U) ? CLOCK_GetAudioPllOutFreq(): - (SYSCON->CLKOUTSELA == 7U) ? CLOCK_GetOsc32KFreq():0U; -} - -/* Get SPIFI Clk */ -uint32_t CLOCK_GetSpifiClkFreq(void) -{ - return (SYSCON->SPIFICLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq(): - (SYSCON->SPIFICLKSEL == 1U) ? CLOCK_GetPllOutFreq(): - (SYSCON->SPIFICLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq(): - (SYSCON->SPIFICLKSEL == 3U) ? CLOCK_GetFroHfFreq(): - (SYSCON->SPIFICLKSEL == 4U) ? CLOCK_GetAudioPllOutFreq(): - (SYSCON->SPIFICLKSEL == 7U) ? 0U:0U; -} - -/* Get ADC Clk */ -uint32_t CLOCK_GetAdcClkFreq(void) -{ - return (SYSCON->ADCCLKSEL == 0U) ? CLOCK_GetFroHfFreq(): - (SYSCON->ADCCLKSEL == 1U) ? CLOCK_GetPllOutFreq(): - (SYSCON->ADCCLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq(): - (SYSCON->ADCCLKSEL == 3U) ? CLOCK_GetAudioPllOutFreq(): - (SYSCON->ADCCLKSEL == 7U) ? 0U:0U; -} - -/* Get USB0 Clk */ -uint32_t CLOCK_GetUsb0ClkFreq(void) -{ - return (SYSCON->USB0CLKSEL == 0U) ? CLOCK_GetFroHfFreq(): - (SYSCON->USB0CLKSEL == 1U) ? CLOCK_GetPllOutFreq(): - (SYSCON->USB0CLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq(): - (SYSCON->USB0CLKSEL == 7U) ? 0U:0U; -} - -/* Get USB1 Clk */ -uint32_t CLOCK_GetUsb1ClkFreq(void) -{ - - return (SYSCON->USB1CLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq(): - (SYSCON->USB1CLKSEL == 1U) ? CLOCK_GetPllOutFreq(): - (SYSCON->USB1CLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq(): - (SYSCON->USB1CLKSEL == 7U) ? 0U:0U; -} - -/* Get MCLK Clk */ -uint32_t CLOCK_GetMclkClkFreq(void) -{ - return (SYSCON->MCLKCLKSEL == 0U) ? CLOCK_GetFroHfFreq() / ((SYSCON->FROHFCLKDIV & 0xffu) + 1U): - (SYSCON->MCLKCLKSEL == 1U) ? CLOCK_GetAudioPllOutFreq(): - (SYSCON->MCLKCLKSEL == 7U) ? 0U:0U; -} - -/* Get SCTIMER Clk */ -uint32_t CLOCK_GetSctClkFreq(void) -{ - return (SYSCON->SCTCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq(): - (SYSCON->SCTCLKSEL == 1U) ? CLOCK_GetPllOutFreq(): - (SYSCON->SCTCLKSEL == 2U) ? CLOCK_GetFroHfFreq(): - (SYSCON->SCTCLKSEL == 3U) ? CLOCK_GetAudioPllOutFreq(): - (SYSCON->SCTCLKSEL == 7U) ? 0U:0U; -} - -/* Get SDIO Clk */ -uint32_t CLOCK_GetSdioClkFreq(void) -{ - return (SYSCON->SDIOCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq(): - (SYSCON->SDIOCLKSEL == 1U) ? CLOCK_GetPllOutFreq(): - (SYSCON->SDIOCLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq(): - (SYSCON->SDIOCLKSEL == 3U) ? CLOCK_GetFroHfFreq(): - (SYSCON->SDIOCLKSEL == 4U) ? CLOCK_GetAudioPllOutFreq(): - (SYSCON->SDIOCLKSEL == 7U) ? 0U:0U; -} - -/* Get LCD Clk */ -uint32_t CLOCK_GetLcdClkFreq(void) -{ - return (SYSCON->LCDCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq(): - (SYSCON->LCDCLKSEL == 1U) ? CLOCK_GetLcdClkIn(): - (SYSCON->LCDCLKSEL == 2U) ? CLOCK_GetFroHfFreq(): - (SYSCON->LCDCLKSEL == 3U) ? 0U:0U; -} - -/* Get LCD CLK IN Clk */ -uint32_t CLOCK_GetLcdClkIn(void) -{ - return g_Lcd_Clk_In_Freq; -} - -/* Get FRO 12M Clk */ -uint32_t CLOCK_GetFro12MFreq(void) -{ - return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0U : 12000000U; -} - -/* Get EXT OSC Clk */ -uint32_t CLOCK_GetExtClkFreq(void) -{ - return g_Ext_Clk_Freq; -} - -/* Get WATCH DOG Clk */ -uint32_t CLOCK_GetWdtOscFreq(void) -{ - uint8_t freq_sel, div_sel; - if (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) - { - return 0U; - } - else - { - div_sel = ((SYSCON->WDTOSCCTRL & 0x1f) + 1) << 1; - freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)]; - return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel); - } -} - -/* Get HF FRO Clk */ -uint32_t CLOCK_GetFroHfFreq(void) -{ - return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0 : - !(SYSCON->FROCTRL & SYSCON_FROCTRL_HSPDCLK_MASK) ? 0 : - (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) ? 96000000U : 48000000U; -} - -/* Get SYSTEM PLL Clk */ -uint32_t CLOCK_GetPllOutFreq(void) -{ - return s_Pll_Freq; -} - -/* Get AUDIO PLL Clk */ -uint32_t CLOCK_GetAudioPllOutFreq(void) -{ - return s_Audio_Pll_Freq; -} - -/* Get USB PLL Clk */ -uint32_t CLOCK_GetUsbPllOutFreq(void) -{ - return s_Usb_Pll_Freq; -} - -/* Get RTC OSC Clk */ -uint32_t CLOCK_GetOsc32KFreq(void) -{ - return CLK_RTC_32K_CLK; /* Needs to be corrected to check that RTC Clock is enabled */ -} - -/* Get MAIN Clk */ -uint32_t CLOCK_GetCoreSysClkFreq(void) -{ - return ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 0U)) ? CLOCK_GetFro12MFreq() : - ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 1U)) ? CLOCK_GetExtClkFreq() : - ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 2U)) ? CLOCK_GetWdtOscFreq() : - ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 3U)) ? CLOCK_GetFroHfFreq() : - (SYSCON->MAINCLKSELB == 2U) ? CLOCK_GetPllOutFreq() : - (SYSCON->MAINCLKSELB == 3U) ? CLOCK_GetOsc32KFreq() : 0U; -} - -/* Get I2S MCLK Clk */ -uint32_t CLOCK_GetI2SMClkFreq(void) -{ - return g_I2S_Mclk_Freq; -} - -/* Get ASYNC APB Clk */ -uint32_t CLOCK_GetAsyncApbClkFreq(void) -{ - async_clock_src_t clkSrc; - uint32_t clkRate; - - clkSrc = CLOCK_GetAsyncApbClkSrc(); - - switch (clkSrc) - { - case kCLOCK_AsyncMainClk: - clkRate = CLOCK_GetCoreSysClkFreq(); - break; - case kCLOCK_AsyncFro12Mhz: - clkRate = CLK_FRO_12MHZ; - break; - default: - clkRate = 0U; - break; - } - - return clkRate; -} - -/* Get FLEXCOMM Clk */ -uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) -{ - return (SYSCON->FCLKSEL[id] == 0U) ? CLOCK_GetFro12MFreq() : - (SYSCON->FCLKSEL[id] == 1U) ? CLOCK_GetFroHfFreq() : - (SYSCON->FCLKSEL[id] == 2U) ? CLOCK_GetPllOutFreq() : - (SYSCON->FCLKSEL[id] == 3U) ? CLOCK_GetI2SMClkFreq() : - (SYSCON->FCLKSEL[id] == 4U) ? CLOCK_GetFreq(kCLOCK_Frg) : 0U; -} - -/* Get FRG Clk */ -uint32_t CLOCK_GetFRGInputClock(void) -{ - return (SYSCON->FRGCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq() : - (SYSCON->FRGCLKSEL == 1U) ? CLOCK_GetPllOutFreq() : - (SYSCON->FRGCLKSEL == 2U) ? CLOCK_GetFro12MFreq() : - (SYSCON->FRGCLKSEL == 3U) ? CLOCK_GetFroHfFreq() : 0U; -} - -/* Set FRG Clk */ -uint32_t CLOCK_SetFRGClock(uint32_t freq) -{ - uint32_t input = CLOCK_GetFRGInputClock(); - uint32_t mul; - - if ((freq > 48000000) || (freq > input) || (input / freq >= 2)) - { - /* FRG output frequency should be less than equal to 48MHz */ - return 0; - } - else - { - mul = ((uint64_t)(input - freq) * 256) / ((uint64_t)freq); - SYSCON->FRGCTRL = (mul << SYSCON_FRGCTRL_MULT_SHIFT) | SYSCON_FRGCTRL_DIV_MASK; - return 1; - } -} - -/* Set IP Clk */ -uint32_t CLOCK_GetFreq(clock_name_t clockName) -{ - uint32_t freq; - switch (clockName) - { - case kCLOCK_CoreSysClk: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case kCLOCK_BusClk: - freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); - break; - case kCLOCK_ClockOut: - freq = CLOCK_GetClockOutClkFreq() / ((SYSCON->CLKOUTDIV & 0xffU) + 1U); - break; - case kCLOCK_SpiFi: - freq = CLOCK_GetSpifiClkFreq() / ((SYSCON->SPIFICLKDIV & 0xffU) + 1U ); - break; - case kCLOCK_Adc: - freq = CLOCK_GetAdcClkFreq() / ((SYSCON->ADCCLKDIV & 0xffU) + 1U ); - break; - case kCLOCK_Usb0: - freq = CLOCK_GetUsb0ClkFreq() / ((SYSCON->USB0CLKDIV & 0xffU) + 1U ); - break; - case kCLOCK_Usb1: - freq = CLOCK_GetUsb1ClkFreq() / ((SYSCON->USB1CLKDIV & 0xffU) + 1U ); - break; - case kCLOCK_Mclk: - freq = CLOCK_GetMclkClkFreq() / ((SYSCON->MCLKDIV & 0xffU) + 1U ); - break; - case kCLOCK_FroHf: - freq = CLOCK_GetFroHfFreq(); - break; - case kCLOCK_Fro12M: - freq = CLOCK_GetFro12MFreq(); - break; - case kCLOCK_ExtClk: - freq = CLOCK_GetExtClkFreq(); - break; - case kCLOCK_PllOut: - freq = CLOCK_GetPllOutFreq(); - break; - case kClock_WdtOsc: - freq = CLOCK_GetWdtOscFreq(); - break; - case kCLOCK_Frg: - freq = (SYSCON->FRGCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq() : - (SYSCON->FRGCLKSEL == 1U) ? CLOCK_GetPllOutFreq() : - (SYSCON->FRGCLKSEL == 2U) ? CLOCK_GetFro12MFreq() : - (SYSCON->FRGCLKSEL == 3U) ? CLOCK_GetFroHfFreq() : 0U; - break; - case kCLOCK_Dmic: - freq = (SYSCON->DMICCLKSEL == 0U) ? CLOCK_GetFro12MFreq() : - (SYSCON->DMICCLKSEL == 1U) ? CLOCK_GetFroHfFreq() : - (SYSCON->DMICCLKSEL == 2U) ? CLOCK_GetPllOutFreq() : - (SYSCON->DMICCLKSEL == 3U) ? CLOCK_GetI2SMClkFreq() : - (SYSCON->DMICCLKSEL == 4U) ? CLOCK_GetCoreSysClkFreq() : - (SYSCON->DMICCLKSEL == 5U) ? CLOCK_GetWdtOscFreq() : 0U; - freq = freq / ((SYSCON->DMICCLKDIV & 0xffU) + 1U); - break; - - case kCLOCK_AsyncApbClk: - freq = CLOCK_GetAsyncApbClkFreq(); - break; - case kCLOCK_Sct: - freq = CLOCK_GetSctClkFreq() / ((SYSCON->SCTCLKDIV & 0xffU) + 1U); - break; - case kCLOCK_SDio: - freq = CLOCK_GetSdioClkFreq() / ((SYSCON->SDIOCLKDIV & 0xffU) + 1U); - break; - case kCLOCK_EMC: - freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U) / ((SYSCON->EMCCLKDIV & 0xffU) + 1U); - break; - case kCLOCK_LCD: - freq = CLOCK_GetLcdClkFreq() / ((SYSCON->LCDCLKDIV & 0xffU) + 1U); - break; - case kCLOCK_MCAN0: - freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CAN0CLKDIV & 0xffU) + 1U); - break; - case kCLOCK_MCAN1: - freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CAN1CLKDIV & 0xffU) + 1U); - break; - case kCLOCK_FlexI2S: - freq = CLOCK_GetI2SMClkFreq(); - break; - case kCLOCK_Flexcomm0: - freq = CLOCK_GetFlexCommClkFreq(0U); - break; - case kCLOCK_Flexcomm1: - freq = CLOCK_GetFlexCommClkFreq(1U); - break; - case kCLOCK_Flexcomm2: - freq = CLOCK_GetFlexCommClkFreq(2U); - break; - case kCLOCK_Flexcomm3: - freq = CLOCK_GetFlexCommClkFreq(3U); - break; - case kCLOCK_Flexcomm4: - freq = CLOCK_GetFlexCommClkFreq(4U); - break; - case kCLOCK_Flexcomm5: - freq = CLOCK_GetFlexCommClkFreq(5U); - break; - case kCLOCK_Flexcomm6: - freq = CLOCK_GetFlexCommClkFreq(6U); - break; - case kCLOCK_Flexcomm7: - freq = CLOCK_GetFlexCommClkFreq(7U); - break; - case kCLOCK_Flexcomm8: - freq = CLOCK_GetFlexCommClkFreq(8U); - break; - case kCLOCK_Flexcomm9: - freq = CLOCK_GetFlexCommClkFreq(9U); - break; - default: - freq = 0U; - break; - } - - return freq; -} - -/* Set the FLASH wait states for the passed frequency */ -void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq) -{ - if (iFreq <= 12000000U) - { - CLOCK_SetFLASHAccessCycles(kCLOCK_Flash1Cycle); - } - else if (iFreq <= 24000000U) - { - CLOCK_SetFLASHAccessCycles(kCLOCK_Flash2Cycle); - } - else if (iFreq <= 36000000U) - { - CLOCK_SetFLASHAccessCycles(kCLOCK_Flash3Cycle); - } - else if (iFreq <= 60000000U) - { - CLOCK_SetFLASHAccessCycles(kCLOCK_Flash4Cycle); - } - else if (iFreq <= 96000000U) - { - CLOCK_SetFLASHAccessCycles(kCLOCK_Flash5Cycle); - } - else if (iFreq <= 120000000U) - { - CLOCK_SetFLASHAccessCycles(kCLOCK_Flash6Cycle); - } - else if (iFreq <= 144000000U) - { - CLOCK_SetFLASHAccessCycles(kCLOCK_Flash7Cycle); - } - else if (iFreq <= 168000000U) - { - CLOCK_SetFLASHAccessCycles(kCLOCK_Flash8Cycle); - } - else - { - CLOCK_SetFLASHAccessCycles(kCLOCK_Flash9Cycle); - } -} - -/* Find encoded NDEC value for raw N value, max N = NVALMAX */ -static uint32_t pllEncodeN(uint32_t N) -{ - uint32_t x, i; - - /* Find NDec */ - switch (N) - { - case 0U: - x = 0x3FFU; - break; - - case 1U: - x = 0x302U; - break; - - case 2U: - x = 0x202U; - break; - - default: - x = 0x080U; - for (i = N; i <= NVALMAX; i++) - { - x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU); - } - break; - } - - return x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P); -} - -/* Find decoded N value for raw NDEC value */ -static uint32_t pllDecodeN(uint32_t NDEC) -{ - uint32_t n, x, i; - - /* Find NDec */ - switch (NDEC) - { - case 0x3FFU: - n = 0U; - break; - - case 0x302U: - n = 1U; - break; - - case 0x202U: - n = 2U; - break; - - default: - x = 0x080U; - n = 0xFFFFFFFFU; - for (i = NVALMAX; ((i >= 3U) && (n == 0xFFFFFFFFU)); i--) - { - x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU); - if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC) - { - /* Decoded value of NDEC */ - n = i; - } - } - break; - } - - return n; -} - -/* Find encoded PDEC value for raw P value, max P = PVALMAX */ -static uint32_t pllEncodeP(uint32_t P) -{ - uint32_t x, i; - - /* Find PDec */ - switch (P) - { - case 0U: - x = 0x7FU; - break; - - case 1U: - x = 0x62U; - break; - - case 2U: - x = 0x42U; - break; - - default: - x = 0x10U; - for (i = P; i <= PVALMAX; i++) - { - x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU); - } - break; - } - - return x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P); -} - -/* Find decoded P value for raw PDEC value */ -static uint32_t pllDecodeP(uint32_t PDEC) -{ - uint32_t p, x, i; - - /* Find PDec */ - switch (PDEC) - { - case 0x7FU: - p = 0U; - break; - - case 0x62U: - p = 1U; - break; - - case 0x42U: - p = 2U; - break; - - default: - x = 0x10U; - p = 0xFFFFFFFFU; - for (i = PVALMAX; ((i >= 3U) && (p == 0xFFFFFFFFU)); i--) - { - x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU); - if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC) - { - /* Decoded value of PDEC */ - p = i; - } - } - break; - } - - return p; -} - -/* Find encoded MDEC value for raw M value, max M = MVALMAX */ -static uint32_t pllEncodeM(uint32_t M) -{ - uint32_t i, x; - - /* Find MDec */ - switch (M) - { - case 0U: - x = 0x1FFFFU; - break; - - case 1U: - x = 0x18003U; - break; - - case 2U: - x = 0x10003U; - break; - - default: - x = 0x04000U; - for (i = M; i <= MVALMAX; i++) - { - x = (((x ^ (x >> 1U)) & 1U) << 14U) | ((x >> 1U) & 0x3FFFU); - } - break; - } - - return x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P); -} - -/* Find decoded M value for raw MDEC value */ -static uint32_t pllDecodeM(uint32_t MDEC) -{ - uint32_t m, i, x; - - /* Find MDec */ - switch (MDEC) - { - case 0x1FFFFU: - m = 0U; - break; - - case 0x18003U: - m = 1U; - break; - - case 0x10003U: - m = 2U; - break; - - default: - x = 0x04000U; - m = 0xFFFFFFFFU; - for (i = MVALMAX; ((i >= 3U) && (m == 0xFFFFFFFFU)); i--) - { - x = (((x ^ (x >> 1U)) & 1) << 14U) | ((x >> 1U) & 0x3FFFU); - if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC) - { - /* Decoded value of MDEC */ - m = i; - } - } - break; - } - - return m; -} - -/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ -static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) -{ - /* bandwidth: compute selP from Multiplier */ - if (M < 60U) - { - *pSelP = (M >> 1U) + 1U; - } - else - { - *pSelP = PVALMAX - 1U; - } - - /* bandwidth: compute selI from Multiplier */ - if (M > 16384U) - { - *pSelI = 1U; - } - else if (M > 8192U) - { - *pSelI = 2U; - } - else if (M > 2048U) - { - *pSelI = 4U; - } - else if (M >= 501U) - { - *pSelI = 8U; - } - else if (M >= 60U) - { - *pSelI = 4U * (1024U / (M + 9U)); - } - else - { - *pSelI = (M & 0x3CU) + 4U; - } - - if (*pSelI > ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT)) - { - *pSelI = ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT); - } - - *pSelR = 0U; -} - -/* Get predivider (N) from PLL NDEC setting */ -static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg) -{ - uint32_t preDiv = 1; - - /* Direct input is not used? */ - if ((ctrlReg & (1UL << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) == 0U) - { - /* Decode NDEC value to get (N) pre divider */ - preDiv = pllDecodeN(nDecReg & 0x3FFU); - if (preDiv == 0U) - { - preDiv = 1U; - } - } - - /* Adjusted by 1, directi is used to bypass */ - return preDiv; -} - -/* Get postdivider (P) from PLL PDEC setting */ -static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg) -{ - uint32_t postDiv = 1U; - - /* Direct input is not used? */ - if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0U) - { - /* Decode PDEC value to get (P) post divider */ - postDiv = 2U * pllDecodeP(pDecReg & 0x7FU); - if (postDiv == 0U) - { - postDiv = 2U; - } - } - - /* Adjusted by 1, directo is used to bypass */ - return postDiv; -} - -/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ -static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg) -{ - uint32_t mMult = 1U; - - /* Decode MDEC value to get (M) multiplier */ - mMult = pllDecodeM(mDecReg & 0x1FFFFU); - - if (mMult == 0U) - { - mMult = 1U; - } - - return mMult; -} - -/* Find greatest common divisor between m and n */ -static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) -{ - uint32_t tmp; - - while (n != 0U) - { - tmp = n; - n = m % n; - m = tmp; - } - - return m; -} - -/* - * Set PLL output based on desired output rate. - * In this function, the it calculates the PLL setting for output frequency from input clock - * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. - * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. - */ -static pll_error_t CLOCK_GetPllConfigInternal( - uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup) -{ - uint32_t nDivOutHz, fccoHz, multFccoDiv; - uint32_t pllPreDivider, pllMultiplier, pllPostDivider; - uint32_t pllDirectInput, pllDirectOutput; - uint32_t pllSelP, pllSelI, pllSelR, uplimoff; - - /* Baseline parameters (no input or output dividers) */ - pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ - pllPostDivider = 0U; /* 0 implies post-divider will be disabled */ - pllDirectOutput = 1U; - multFccoDiv = 2U; - - /* Verify output rate parameter */ - if (foutHz > PLL_MAX_CCO_FREQ_MHZ) - { - /* Maximum PLL output with post divider=1 cannot go above this frequency */ - return kStatus_PLL_OutputTooHigh; - } - if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) - { - /* Minmum PLL output with maximum post divider cannot go below this frequency */ - return kStatus_PLL_OutputTooLow; - } - - /* Verify input rate parameter */ - if (finHz < PLL_LOWER_IN_LIMIT) - { - /* Input clock into the PLL cannot be lower than this */ - return kStatus_PLL_InputTooLow; - } - - /* Find the optimal CCO frequency for the output and input that - will keep it inside the PLL CCO range. This may require - tweaking the post-divider for the PLL. */ - fccoHz = foutHz; - while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) - { - /* CCO output is less than minimum CCO range, so the CCO output - needs to be bumped up and the post-divider is used to bring - the PLL output back down. */ - pllPostDivider++; - if (pllPostDivider > PVALMAX) - { - return kStatus_PLL_OutsideIntLimit; - } - - /* Target CCO goes up, PLL output goes down */ - fccoHz = foutHz * (pllPostDivider * 2U); - pllDirectOutput = 0U; - } - - /* Determine if a pre-divider is needed to get the best frequency */ - if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz)) - { - uint32_t a = FindGreatestCommonDivisor(fccoHz, (multFccoDiv * finHz)); - - if (a > 20000U) - { - a = (multFccoDiv * finHz) / a; - if ((a != 0U) && (a < PLL_MAX_N_DIV)) - { - pllPreDivider = a; - } - } - } - - /* Bypass pre-divider hardware if pre-divider is 1 */ - if (pllPreDivider > 1U) - { - pllDirectInput = 0U; - } - else - { - pllDirectInput = 1U; - } - - /* Determine PLL multipler */ - nDivOutHz = (finHz / pllPreDivider); - pllMultiplier = (fccoHz / nDivOutHz) / multFccoDiv; - - /* Find optimal values for filter */ - /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ - if ((nDivOutHz * ((multFccoDiv * pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) - { - pllMultiplier++; - } - - /* Setup filtering */ - pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR); - uplimoff = 0U; - - /* Get encoded value for M (mult) and use manual filter, disable SS mode */ - pSetup->pllmdec = - PLL_MDEC_VAL_SET(pllEncodeM(pllMultiplier)) ; - - /* Get encoded values for N (prediv) and P (postdiv) */ - pSetup->pllndec = PLL_NDEC_VAL_SET(pllEncodeN(pllPreDivider)); - pSetup->pllpdec = PLL_PDEC_VAL_SET(pllEncodeP(pllPostDivider)); - - /* PLL control */ - pSetup->pllctrl = (pllSelR << SYSCON_SYSPLLCTRL_SELR_SHIFT) | /* Filter coefficient */ - (pllSelI << SYSCON_SYSPLLCTRL_SELI_SHIFT) | /* Filter coefficient */ - (pllSelP << SYSCON_SYSPLLCTRL_SELP_SHIFT) | /* Filter coefficient */ - (0 << SYSCON_SYSPLLCTRL_BYPASS_SHIFT) | /* PLL bypass mode disabled */ - (uplimoff << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT) | /* SS/fractional mode disabled */ - (pllDirectInput << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT) | /* Bypass pre-divider? */ - (pllDirectOutput << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT); /* Bypass post-divider? */ - - return kStatus_PLL_Success; -} - -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) -/* Alloct the static buffer for cache. */ -pll_setup_t gPllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; -uint32_t gFinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; -uint32_t gFoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; -uint32_t gPllSetupCacheIdx = 0U; -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - -/* - * Calculate the PLL setting values from input clock freq to output freq. - */ -static pll_error_t CLOCK_GetPllConfig( - uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup) -{ - pll_error_t retErr; -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - uint32_t i; - - for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) - { - if ( (finHz == gFinHzCache[i]) && (foutHz == gFoutHzCache[i]) ) - { - /* Hit the target in cache buffer. */ - pSetup->pllctrl = gPllSetupCacheStruct[i].pllctrl; - pSetup->pllndec = gPllSetupCacheStruct[i].pllndec; - pSetup->pllpdec = gPllSetupCacheStruct[i].pllpdec; - pSetup->pllmdec = gPllSetupCacheStruct[i].pllmdec; - retErr = kStatus_PLL_Success; - } - } - - if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - { - return retErr; - } -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - - /* No cache or did not hit the cache. */ - retErr = CLOCK_GetPllConfigInternal(finHz, foutHz, pSetup); - -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - if (kStatus_PLL_Success == retErr) - { - /* Cache the most recent calulation result into buffer. */ - gFinHzCache[gPllSetupCacheIdx] = finHz; - gFoutHzCache[gPllSetupCacheIdx] = foutHz; - - gPllSetupCacheStruct[gPllSetupCacheIdx].pllctrl = pSetup->pllctrl; - gPllSetupCacheStruct[gPllSetupCacheIdx].pllndec = pSetup->pllndec; - gPllSetupCacheStruct[gPllSetupCacheIdx].pllpdec = pSetup->pllpdec; - gPllSetupCacheStruct[gPllSetupCacheIdx].pllmdec = pSetup->pllmdec; - /* Update the index for next available buffer. */ - gPllSetupCacheIdx = (gPllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; - } -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - - return retErr; -} - -/* Update SYSTEM PLL rate variable */ -static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup) -{ - s_Pll_Freq = CLOCK_GetSystemPLLOutFromSetup(pSetup); -} - -/* Update AUDIO PLL rate variable */ -static void CLOCK_GetAudioPLLOutFromSetupUpdate(pll_setup_t *pSetup) -{ - s_Audio_Pll_Freq = CLOCK_GetAudioPLLOutFromSetup(pSetup); -} - -/* Update USB PLL rate variable */ -static void CLOCK_GetUsbPLLOutFromSetupUpdate(const usb_pll_setup_t *pSetup) -{ - s_Usb_Pll_Freq = CLOCK_GetUsbPLLOutFromSetup(pSetup); -} - -/* Return System PLL input clock rate */ -uint32_t CLOCK_GetSystemPLLInClockRate(void) -{ - uint32_t clkRate = 0U; - - switch ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)) - { - case 0x00U: - clkRate = CLK_FRO_12MHZ; - break; - - case 0x01U: - clkRate = CLOCK_GetExtClkFreq(); - break; - - case 0x02U: - clkRate = CLOCK_GetWdtOscFreq(); - break; - - case 0x03U: - clkRate = CLOCK_GetOsc32KFreq(); - break; - - default: - clkRate = 0U; - break; - } - - return clkRate; -} - -/* Return Audio PLL input clock rate */ -uint32_t CLOCK_GetAudioPLLInClockRate(void) -{ - uint32_t clkRate = 0U; - - switch ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK)) - { - case 0x00U: - clkRate = CLK_FRO_12MHZ; - break; - - case 0x01U: - clkRate = CLOCK_GetExtClkFreq(); - break; - - default: - clkRate = 0U; - break; - } - - return clkRate; -} - -/* Return System PLL output clock rate from setup structure */ -uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup) -{ - uint32_t prediv, postdiv, mMult, inPllRate; - uint64_t workRate; - - inPllRate = CLOCK_GetSystemPLLInClockRate(); - /* If the PLL is bypassed, PLL would not be used and the output of PLL module would just be the input clock*/ - if ((pSetup->pllctrl & (SYSCON_SYSPLLCTRL_BYPASS_MASK)) == 0U) - { - /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */ - /* - * 1. Pre-divider - * Pre-divider is only available when the DIRECTI is disabled. - */ - if (0U == (pSetup->pllctrl & SYSCON_SYSPLLCTRL_DIRECTI_MASK)) - { - prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec); - } - else - { - prediv = 1U; /* The pre-divider is bypassed. */ - } - /* - * 2. Post-divider - * Post-divider is only available when the DIRECTO is disabled. - */ - if (0U == (pSetup->pllctrl & SYSCON_SYSPLLCTRL_DIRECTO_MASK)) - { - postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec); - } - else - { - postdiv = 1U; /* The post-divider is bypassed. */ - } - /* Adjust input clock */ - inPllRate = inPllRate / prediv; - - /* MDEC used for rate */ - mMult = findPllMMult(pSetup->pllctrl, pSetup->pllmdec); - workRate = (uint64_t)inPllRate * (uint64_t)mMult; - - workRate = workRate / ((uint64_t)postdiv); - workRate = workRate * 2U; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/ - - } - else - { - /* In bypass mode */ - workRate = (uint64_t)inPllRate; - } - - return (uint32_t)workRate; -} - -/* Return Usb PLL output clock rate from setup structure */ -uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup) -{ - uint32_t nsel, psel, msel, inPllRate; - uint64_t workRate; - inPllRate = CLOCK_GetExtClkFreq(); - msel = pSetup->msel; - psel = pSetup->psel; - nsel = pSetup->nsel; - - if (pSetup->fbsel == 1U) - { - /*integer_mode: Fout = M*(Fin/N), Fcco = 2*P*M*(Fin/N) */ - workRate = (inPllRate) * (msel + 1U) / (nsel + 1U); - } - else - { - /* non integer_mode: Fout = M*(Fin/N)/(2*P), Fcco = M * (Fin/N) */ - workRate = (inPllRate / (nsel + 1U)) * (msel + 1U) / (2U * SWITCH_USB_PSEL(psel)); - } - - return (uint32_t)workRate; -} - -/* Return Audio PLL output clock rate from setup structure */ -uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup) -{ - uint32_t prediv, postdiv, mMult, inPllRate; - uint64_t workRate; - - inPllRate = CLOCK_GetAudioPLLInClockRate(); - if ((pSetup->pllctrl & (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) == 0U) - { - /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */ - /* - * 1. Pre-divider - * Pre-divider is only available when the DIRECTI is disabled. - */ - if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTI_MASK)) - { - prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec); - } - else - { - prediv = 1U; /* The pre-divider is bypassed. */ - } - /* - * 2. Post-divider - * Post-divider is only available when the DIRECTO is disabled. - */ - if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTO_MASK)) - { - postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec); - } - else - { - postdiv = 1U; /* The post-divider is bypassed. */ - } - /* Adjust input clock */ - inPllRate = inPllRate / prediv; - - /* MDEC used for rate */ - mMult = findPllMMult(pSetup->pllctrl, pSetup->pllmdec); - workRate = (uint64_t)inPllRate * (uint64_t)mMult; - - workRate = workRate / ((uint64_t)postdiv); - workRate = workRate * 2U; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/ - } - else - { - /* In bypass mode */ - workRate = (uint64_t)inPllRate; - } - - return (uint32_t)workRate; -} - -/* Set the current PLL Rate */ -void CLOCK_SetStoredPLLClockRate(uint32_t rate) -{ - s_Pll_Freq = rate; -} - -/* Set the current Audio PLL Rate */ -void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate) -{ - s_Audio_Pll_Freq = rate; -} - -/* Set the current Usb PLL Rate */ -void CLOCK_SetStoredUsbPLLClockRate(uint32_t rate) -{ - s_Usb_Pll_Freq = rate; -} - -/* Return System PLL output clock rate */ -uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute) -{ - pll_setup_t Setup; - uint32_t rate; - - if ((recompute) || (s_Pll_Freq == 0U)) - { - Setup.pllctrl = SYSCON->SYSPLLCTRL; - Setup.pllndec = SYSCON->SYSPLLNDEC; - Setup.pllpdec = SYSCON->SYSPLLPDEC; - Setup.pllmdec = SYSCON->SYSPLLMDEC; - - CLOCK_GetSystemPLLOutFromSetupUpdate(&Setup); - } - - rate = s_Pll_Freq; - - return rate; -} - -/* Return AUDIO PLL output clock rate */ -uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute) -{ - pll_setup_t Setup; - uint32_t rate; - - if ((recompute) || (s_Audio_Pll_Freq == 0U)) - { - Setup.pllctrl = SYSCON->AUDPLLCTRL; - Setup.pllndec = SYSCON->AUDPLLNDEC; - Setup.pllpdec = SYSCON->AUDPLLPDEC; - Setup.pllmdec = SYSCON->AUDPLLMDEC; - - CLOCK_GetAudioPLLOutFromSetupUpdate(&Setup); - } - - rate = s_Audio_Pll_Freq; - return rate; -} - -/* Return USB PLL output clock rate */ -uint32_t CLOCK_GetUsbPLLOutClockRate(bool recompute) -{ - usb_pll_setup_t Setup; - uint32_t rate; - - if ((recompute) || (s_Usb_Pll_Freq == 0U)) - { - Setup.msel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_MSEL_SHIFT) & SYSCON_USBPLLCTRL_MSEL_MASK; - Setup.psel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_PSEL_SHIFT) & SYSCON_USBPLLCTRL_PSEL_MASK; - Setup.nsel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_NSEL_SHIFT) & SYSCON_USBPLLCTRL_NSEL_MASK; - Setup.fbsel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_FBSEL_SHIFT) & SYSCON_USBPLLCTRL_FBSEL_MASK; - Setup.bypass = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_BYPASS_SHIFT) & SYSCON_USBPLLCTRL_BYPASS_MASK; - Setup.direct = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_DIRECT_SHIFT) & SYSCON_USBPLLCTRL_DIRECT_MASK; - CLOCK_GetUsbPLLOutFromSetupUpdate(&Setup); - } - - rate = s_Usb_Pll_Freq; - return rate; -} - -/* Set PLL output based on the passed PLL setup data */ -pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup) -{ - uint32_t inRate; - pll_error_t pllError; - - /* Determine input rate for the PLL */ - if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U) - { - inRate = pControl->inputRate; - } - else - { - inRate = CLOCK_GetSystemPLLInClockRate(); - } - - /* PLL flag options */ - pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup); - pSetup->pllRate = pControl->desiredRate; - return pllError; -} - -/* Set PLL output from PLL setup structure */ -pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg) -{ - if ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) == 0x01U) - { - /* Turn on the ext clock if system pll input select clk_in */ - CLOCK_Enable_SysOsc(true); - } - /* Enable power for PLLs */ - POWER_SetPLL(); - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0); - /*!< Set FLASH waitstates for core */ - CLOCK_SetFLASHAccessCyclesForFreq(pSetup->pllRate); - pSetup->flags = flagcfg; - - /* Write PLL setup data */ - SYSCON->SYSPLLCTRL = pSetup->pllctrl; - SYSCON->SYSPLLNDEC = pSetup->pllndec; - SYSCON->SYSPLLNDEC = pSetup->pllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */ - SYSCON->SYSPLLPDEC = pSetup->pllpdec; - SYSCON->SYSPLLPDEC = pSetup->pllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */ - SYSCON->SYSPLLMDEC = pSetup->pllmdec; - SYSCON->SYSPLLMDEC = pSetup->pllmdec | (1U << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */ - - /* Flags for lock or power on */ - if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U) - { - /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ - volatile uint32_t delayX; - uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ - uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1U << 17U); - - /* Initialize and power up PLL */ - SYSCON->SYSPLLMDEC = maxCCO; - POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); - - /* Set mreq to activate */ - SYSCON->SYSPLLMDEC = maxCCO | (1U << 17U); - - /* Delay for 72 uSec @ 12Mhz */ - for (delayX = 0U; delayX < 172U; ++delayX) - { - } - - /* clear mreq to prepare for restoring mreq */ - SYSCON->SYSPLLMDEC = curSSCTRL; - - /* set original value back and activate */ - SYSCON->SYSPLLMDEC = curSSCTRL | (1U << 17U); - - /* Enable peripheral states by setting low */ - POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); - } - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) - { - while (CLOCK_IsSystemPLLLocked() == false) - { - } - } - - /* Update current programmed PLL rate var */ - CLOCK_GetSystemPLLOutFromSetupUpdate(pSetup); - - /* System voltage adjustment, occurs prior to setting main system clock */ - if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U) - { - POWER_SetVoltageForFreq(s_Pll_Freq); - } - - return kStatus_PLL_Success; -} - - -/* Set AUDIO PLL output from AUDIO PLL setup structure */ -pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg) -{ - if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U) - { - /* Turn on the ext clock if system pll input select clk_in */ - CLOCK_Enable_SysOsc(true); - } - /* Enable power VD3 for PLLs */ - POWER_SetPLL(); - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL); - - pSetup->flags = flagcfg; - - /* Write PLL setup data */ - SYSCON->AUDPLLCTRL = pSetup->pllctrl; - SYSCON->AUDPLLNDEC = pSetup->pllndec; - SYSCON->AUDPLLNDEC = pSetup->pllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */ - SYSCON->AUDPLLPDEC = pSetup->pllpdec; - SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */ - SYSCON->AUDPLLMDEC = pSetup->pllmdec; - SYSCON->AUDPLLMDEC = pSetup->pllmdec | (1U << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */ - SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(1); /* disable fractional function */ - - /* Flags for lock or power on */ - if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U) - { - /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ - volatile uint32_t delayX; - uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ - uint32_t curSSCTRL = SYSCON->AUDPLLMDEC & ~(1U << 17U); - - /* Initialize and power up PLL */ - SYSCON->AUDPLLMDEC = maxCCO; - POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL); - - /* Set mreq to activate */ - SYSCON->AUDPLLMDEC = maxCCO | (1U << 17U); - - /* Delay for 72 uSec @ 12Mhz */ - for (delayX = 0U; delayX < 172U; ++delayX) - { - } - - /* clear mreq to prepare for restoring mreq */ - SYSCON->AUDPLLMDEC = curSSCTRL; - - /* set original value back and activate */ - SYSCON->AUDPLLMDEC = curSSCTRL | (1U << 17U); - - /* Enable peripheral states by setting low */ - POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL); - } - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) - { - while (CLOCK_IsAudioPLLLocked() == false) - { - } - } - - /* Update current programmed PLL rate var */ - CLOCK_GetAudioPLLOutFromSetupUpdate(pSetup); - - return kStatus_PLL_Success; -} - -/* Set Audio PLL output based on the passed Audio PLL setup data */ -pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup) -{ - uint32_t inRate; - pll_error_t pllError; - - /* Determine input rate for the PLL */ - if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U) - { - inRate = pControl->inputRate; - } - else - { - inRate = CLOCK_GetAudioPLLInClockRate(); - } - - /* PLL flag options */ - pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup); - pSetup->pllRate = pControl->desiredRate; - return pllError; -} - - - -/* Setup PLL Frequency from pre-calculated value */ -pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup) -{ - if ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) == 0x01U) - { - /* Turn on the ext clock if system pll input select clk_in */ - CLOCK_Enable_SysOsc(true); - } - /* Enable power VD3 for PLLs */ - POWER_SetPLL(); - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0); - - /* Write PLL setup data */ - SYSCON->SYSPLLCTRL = pSetup->pllctrl; - SYSCON->SYSPLLNDEC = pSetup->pllndec; - SYSCON->SYSPLLNDEC = pSetup->pllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */ - SYSCON->SYSPLLPDEC = pSetup->pllpdec; - SYSCON->SYSPLLPDEC = pSetup->pllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */ - SYSCON->SYSPLLMDEC = pSetup->pllmdec; - SYSCON->SYSPLLMDEC = pSetup->pllmdec | (1U << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */ - - /* Flags for lock or power on */ - if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0) - { - /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ - volatile uint32_t delayX; - uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ - uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1U << 17U); - - /* Initialize and power up PLL */ - SYSCON->SYSPLLMDEC = maxCCO; - POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); - - /* Set mreq to activate */ - SYSCON->SYSPLLMDEC = maxCCO | (1U << 17U); - - /* Delay for 72 uSec @ 12Mhz */ - for (delayX = 0U; delayX < 172U; ++delayX) - { - } - - /* clear mreq to prepare for restoring mreq */ - SYSCON->SYSPLLMDEC = curSSCTRL; - - /* set original value back and activate */ - SYSCON->SYSPLLMDEC = curSSCTRL | (1U << 17U); - - /* Enable peripheral states by setting low */ - POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); - } - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) - { - while (CLOCK_IsSystemPLLLocked() == false) - { - } - } - - /* Update current programmed PLL rate var */ - s_Pll_Freq = pSetup->pllRate; - - return kStatus_PLL_Success; -} - -/* Setup Audio PLL Frequency from pre-calculated value */ -pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup) -{ - if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U) - { - /* Turn on the ext clock if system pll input select clk_in */ - CLOCK_Enable_SysOsc(true); - } - /* Enable power VD3 for PLLs */ - POWER_SetPLL(); - /* Power off Audio PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL); - - /* Write Audio PLL setup data */ - SYSCON->AUDPLLCTRL = pSetup->pllctrl; - SYSCON->AUDPLLFRAC = pSetup->audpllfrac; - SYSCON->AUDPLLFRAC = pSetup->audpllfrac | (1U << SYSCON_AUDPLLFRAC_REQ_SHIFT); /* latch */ - SYSCON->AUDPLLNDEC = pSetup->pllndec; - SYSCON->AUDPLLNDEC = pSetup->pllndec | (1U << SYSCON_AUDPLLNDEC_NREQ_SHIFT); /* latch */ - SYSCON->AUDPLLPDEC = pSetup->pllpdec; - SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1U << SYSCON_AUDPLLPDEC_PREQ_SHIFT); /* latch */ - SYSCON->AUDPLLMDEC = pSetup->pllmdec; - SYSCON->AUDPLLMDEC = pSetup->pllmdec | (1U << SYSCON_AUDPLLMDEC_MREQ_SHIFT); /* latch */ - SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(1); /* disable fractional function */ - - /* Flags for lock or power on */ - if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0) - { - /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ - volatile uint32_t delayX; - uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ - uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1U << 17U); - - /* Initialize and power up PLL */ - SYSCON->SYSPLLMDEC = maxCCO; - POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL); - - /* Set mreq to activate */ - SYSCON->SYSPLLMDEC = maxCCO | (1U << 17U); - - /* Delay for 72 uSec @ 12Mhz */ - for (delayX = 0U; delayX < 172U; ++delayX) - { - } - - /* clear mreq to prepare for restoring mreq */ - SYSCON->SYSPLLMDEC = curSSCTRL; - - /* set original value back and activate */ - SYSCON->SYSPLLMDEC = curSSCTRL | (1U << 17U); - - /* Enable peripheral states by setting low */ - POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL); - } - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) - { - while (CLOCK_IsAudioPLLLocked() == false) - { - } - } - - /* Update current programmed PLL rate var */ - s_Audio_Pll_Freq = pSetup->pllRate; - - return kStatus_PLL_Success; -} - -/* Setup USB PLL Frequency from pre-calculated value */ -pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup) -{ - uint32_t usbpllctrl, fccoHz; - uint8_t msel, psel, nsel; - bool pllDirectInput, pllDirectOutput, pllfbsel; - volatile uint32_t delayX; - - msel = pSetup->msel; - psel = pSetup->psel; - nsel = pSetup->nsel; - pllDirectInput = pSetup->direct; - pllDirectOutput = pSetup->bypass; - pllfbsel = pSetup->fbsel; - - /* Input clock into the PLL cannot be lower than this */ - if (pSetup->inputRate < USB_PLL_LOWER_IN_LIMIT ) - { - return kStatus_PLL_InputTooLow; - } - - if (pllfbsel == 1U) - { - /*integer_mode: Fout = M*(Fin/N), Fcco = 2*P*M*(Fin/N) */ - fccoHz = (pSetup->inputRate / (nsel + 1U)) * 2 * (msel + 1U) * SWITCH_USB_PSEL(psel) ; - - /* USB PLL CCO out rate cannot be lower than this */ - if (fccoHz < USB_PLL_MIN_CCO_FREQ_MHZ) - { - return kStatus_PLL_CCOTooLow; - } - /* USB PLL CCO out rate cannot be Higher than this */ - if (fccoHz > USB_PLL_MAX_CCO_FREQ_MHZ) - { - return kStatus_PLL_CCOTooHigh; - } - } - else - { - /* non integer_mode: Fout = M*(Fin/N)/(2*P), Fcco = M * (Fin/N) */ - fccoHz = pSetup->inputRate / (nsel + 1U) * (msel + 1U); - - /* USB PLL CCO out rate cannot be lower than this */ - if (fccoHz < USB_PLL_MIN_CCO_FREQ_MHZ) - { - return kStatus_PLL_CCOTooLow; - } - /* USB PLL CCO out rate cannot be Higher than this */ - if (fccoHz > USB_PLL_MAX_CCO_FREQ_MHZ) - { - return kStatus_PLL_CCOTooHigh; - } - } - - /* If configure the USB HOST clock, VD5 power for USB PHY should be enable - before the the PLL is working */ - /* Turn on the ext clock for usb pll input */ - CLOCK_Enable_SysOsc(true); - - /* Enable power VD3 for PLLs */ - POWER_SetPLL(); - - /* Power on the VD5 for USB PHY */ - POWER_SetUsbPhy(); - - /* Power off USB PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_USB_PLL); - - /* Write USB PLL setup data */ - usbpllctrl = USB_PLL_NSEL_VAL_SET(nsel) | /* NSEL VALUE */ - USB_PLL_PSEL_VAL_SET(psel) | /* PSEL VALUE */ - USB_PLL_MSEL_VAL_SET(msel) | /* MSEL VALUE */ - (uint32_t)pllDirectInput << SYSCON_USBPLLCTRL_BYPASS_SHIFT | /* BYPASS DISABLE */ - (uint32_t)pllDirectOutput << SYSCON_USBPLLCTRL_DIRECT_SHIFT | /* DIRECTO DISABLE */ - (uint32_t)pllfbsel << SYSCON_USBPLLCTRL_FBSEL_SHIFT; /* FBSEL SELECT */ - - SYSCON->USBPLLCTRL = usbpllctrl; - - POWER_DisablePD(kPDRUNCFG_PD_USB_PLL); - - /* Delay for 72 uSec @ 12Mhz for the usb pll to lock */ - for (delayX = 0U; delayX < 172U; ++delayX) - { - } - - while (CLOCK_IsUsbPLLLocked() == false) - { - } - CLOCK_GetUsbPLLOutFromSetupUpdate(pSetup); - return kStatus_PLL_Success; -} - -/* Set System PLL clock based on the input frequency and multiplier */ -void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq) -{ - uint32_t cco_freq = input_freq * multiply_by; - uint32_t pdec = 1U; - uint32_t selr; - uint32_t seli; - uint32_t selp; - uint32_t mdec, ndec; - - uint32_t directo = SYSCON_SYSPLLCTRL_DIRECTO(1); - - while (cco_freq < 275000000U) - { - multiply_by <<= 1U; /* double value in each iteration */ - pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */ - cco_freq = input_freq * multiply_by; - } - selr = 0U; - if (multiply_by < 60U) - { - seli = (multiply_by & 0x3cU) + 4U; - selp = (multiply_by >> 1U) + 1U; - } - else - { - selp = 31U; - if (multiply_by > 16384U) - { - seli = 1U; - } - else if (multiply_by > 8192U) - { - seli = 2U; - } - else if (multiply_by > 2048U) - { - seli = 4U; - } - else if (multiply_by >= 501U) - { - seli = 8U; - } - else - { - seli = 4U * (1024U / (multiply_by + 9U)); - } - } - - if (pdec > 1U) - { - directo = 0U; /* use post divider */ - pdec = pdec / 2U; /* Account for minus 1 encoding */ - /* Translate P value */ - switch (pdec) - { - case 1U: - pdec = 0x62U; /* 1 * 2 */ - break; - case 2U: - pdec = 0x42U; /* 2 * 2 */ - break; - case 4U: - pdec = 0x02U; /* 4 * 2 */ - break; - case 8U: - pdec = 0x0bU; /* 8 * 2 */ - break; - case 16U: - pdec = 0x11U; /* 16 * 2 */ - break; - case 32U: - pdec = 0x08U; /* 32 * 2 */ - break; - default: - pdec = 0x08U; - break; - } - } - - mdec = PLL_MDEC_VAL_SET(pllEncodeM(multiply_by)); - ndec = 0x302U; /* pre divide by 1 (hardcoded) */ - - SYSCON->SYSPLLCTRL = directo | - (selr << SYSCON_SYSPLLCTRL_SELR_SHIFT) | (seli << SYSCON_SYSPLLCTRL_SELI_SHIFT) | - (selp << SYSCON_SYSPLLCTRL_SELP_SHIFT); - SYSCON->SYSPLLPDEC = pdec | (1U << 7U); /* set Pdec value and assert preq */ - SYSCON->SYSPLLNDEC = ndec | (1U << 10U); /* set Pdec value and assert preq */ - SYSCON->SYSPLLMDEC = (1U << 17U) | mdec; /* select non sscg MDEC value, assert mreq and select mdec value */ -} - -/* Enable USB DEVICE FULL SPEED clock */ -bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq) -{ - bool ret = true; - - CLOCK_DisableClock(kCLOCK_Usbd0); - - if (kCLOCK_UsbSrcFro == src) - { - switch (freq) - { - case 96000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ - break; - - case 48000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ - break; - - default: - ret = false; - break; - } - /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */ - SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK | - SYSCON_FROCTRL_USBCLKADJ_MASK; - /* Select FRO 96 or 48 MHz */ - CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); - } - else - { - /*Set the USB PLL as the Usb0 CLK*/ - POWER_DisablePD(kPDRUNCFG_PD_USB_PLL); - - usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U }; - - CLOCK_SetUsbPLLFreq(&pll_setup); - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk,1U, false); - CLOCK_AttachClk(kUSB_PLL_to_USB0_CLK); - uint32_t delay = 100000; - while (delay --) - { - __asm("nop"); - } - } - CLOCK_EnableClock(kCLOCK_Usbd0); - CLOCK_EnableClock(kCLOCK_UsbRam1); - - return ret; -} - -/* Enable USB HOST FULL SPEED clock */ -bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq) -{ - bool ret = true; - - CLOCK_DisableClock(kCLOCK_Usbhmr0); - CLOCK_DisableClock(kCLOCK_Usbhsl0); - - if (kCLOCK_UsbSrcFro == src) - { - switch (freq) - { - case 96000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ - break; - - case 48000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ - break; - - default: - ret = false; - break; - } - /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */ - SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK | - SYSCON_FROCTRL_USBCLKADJ_MASK; - /* Select FRO 96 or 48 MHz */ - CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); - } - else - { - /*Set the USB PLL as the Usb0 CLK*/ - POWER_DisablePD(kPDRUNCFG_PD_USB_PLL); - - usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U }; - - CLOCK_SetUsbPLLFreq(&pll_setup); - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk,1U, false); - CLOCK_AttachClk(kUSB_PLL_to_USB0_CLK); - uint32_t delay = 100000; - while (delay --) - { - __asm("nop"); - } - } - CLOCK_EnableClock(kCLOCK_Usbhmr0); - CLOCK_EnableClock(kCLOCK_Usbhsl0); - CLOCK_EnableClock(kCLOCK_UsbRam1); - - return ret; -} - -/* Enable USB DEVICE HIGH SPEED clock */ -bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq) -{ - bool ret = true; - uint32_t delay; - CLOCK_DisableClock(kCLOCK_Usbd1); - /* Power on the VD5 for USB PHY */ - POWER_SetUsbPhy(); - if (kCLOCK_UsbSrcFro == src) - { - switch (freq) - { - case 96000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ - break; - - case 48000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ - break; - - default: - ret = false; - break; - } - /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */ - SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK | - SYSCON_FROCTRL_USBCLKADJ_MASK; - /* Select FRO 96 or 48 MHz */ - CLOCK_AttachClk(kFRO_HF_to_USB1_CLK); - } - else - { - delay = 100000; - while (delay --) - { - __asm("nop"); - } - usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U }; - - CLOCK_SetUsbPLLFreq(&pll_setup); - - /* Select USB PLL output as USB clock src */ - CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk,1U, false); - CLOCK_AttachClk(kUSB_PLL_to_USB1_CLK); - } - - delay = 100000; - while (delay --) - { - __asm("nop"); - } - /* Enable USB1D and USB1RAM */ - CLOCK_EnableClock(kCLOCK_Usbd1); - CLOCK_EnableClock(kCLOCK_UsbRam1); - POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /* Turn on power for USB PHY */ - return ret; -} - - -/* Enable USB HOST HIGH SPEED clock */ -bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq) -{ - bool ret = true; - uint32_t delay; - CLOCK_DisableClock(kCLOCK_Usbh1); - /* Power on the VD5 for USB PHY */ - POWER_SetUsbPhy(); - if (kCLOCK_UsbSrcFro == src) - { - switch (freq) - { - case 96000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ - break; - - case 48000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ - break; - - default: - ret = false; - break; - } - /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */ - SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK | - SYSCON_FROCTRL_USBCLKADJ_MASK; - /* Select FRO 96 or 48 MHz */ - CLOCK_AttachClk(kFRO_HF_to_USB1_CLK); - } - else - { - delay = 100000; - while (delay --) - { - __asm("nop"); - } - usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U }; - - CLOCK_SetUsbPLLFreq(&pll_setup); - - /* Select USB PLL output as USB clock src */ - CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk,1U, false); - CLOCK_AttachClk(kUSB_PLL_to_USB1_CLK); - } - - delay = 100000; - while (delay --) - { - __asm("nop"); - } - /* Enable USBh1 and USB1RAM */ - CLOCK_EnableClock(kCLOCK_Usbh1); - CLOCK_EnableClock(kCLOCK_UsbRam1); - POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /* Turn on power for USB PHY */ - return ret; -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_clock.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_clock.h deleted file mode 100644 index 3c5be8ac1ef..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_clock.h +++ /dev/null @@ -1,1277 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016 - 2017 , NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name ofcopyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_CLOCK_H_ -#define _FSL_CLOCK_H_ - -#include "fsl_device_registers.h" -#include -#include -#include - -/*! @addtogroup clock */ -/*! @{ */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *****************************************************************************/ - -/*! @brief Configure whether driver controls clock - * - * When set to 0, peripheral drivers will enable clock in initialize function - * and disable clock in de-initialize function. When set to 1, peripheral - * driver will not control the clock, application could contol the clock out of - * the driver. - * - * @note All drivers share this feature switcher. If it is set to 1, application - * should handle clock enable and disable for all drivers. - */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) -#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 -#endif - -/*! - * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. - * - * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function - * would cache the recent calulation and accelerate the execution to get the - * right settings. - */ -#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT -#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U -#endif - -/*! @brief Clock ip name array for ROM. */ -#define ADC_CLOCKS \ - { \ - kCLOCK_Adc0 \ - } -/*! @brief Clock ip name array for ROM. */ -#define ROM_CLOCKS \ - { \ - kCLOCK_Rom \ - } -/*! @brief Clock ip name array for SRAM. */ -#define SRAM_CLOCKS \ - { \ - kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3 \ - } -/*! @brief Clock ip name array for FLASH. */ -#define FLASH_CLOCKS \ - { \ - kCLOCK_Flash \ - } -/*! @brief Clock ip name array for FMC. */ -#define FMC_CLOCKS \ - { \ - kCLOCK_Fmc \ - } -/*! @brief Clock ip name array for EEPROM. */ -#define EEPROM_CLOCKS \ - { \ - kCLOCK_Eeprom \ - } -/*! @brief Clock ip name array for SPIFI. */ -#define SPIFI_CLOCKS \ - { \ - kCLOCK_Spifi \ - } -/*! @brief Clock ip name array for INPUTMUX. */ -#define INPUTMUX_CLOCKS \ - { \ - kCLOCK_InputMux \ - } -/*! @brief Clock ip name array for IOCON. */ -#define IOCON_CLOCKS \ - { \ - kCLOCK_Iocon \ - } -/*! @brief Clock ip name array for GPIO. */ -#define GPIO_CLOCKS \ - { \ - kCLOCK_Gpio0,kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ - } -/*! @brief Clock ip name array for PINT. */ -#define PINT_CLOCKS \ - { \ - kCLOCK_Pint \ - } -/*! @brief Clock ip name array for GINT. */ -#define GINT_CLOCKS \ - { \ - kCLOCK_Gint, kCLOCK_Gint \ - } -/*! @brief Clock ip name array for DMA. */ -#define DMA_CLOCKS \ - { \ - kCLOCK_Dma \ - } -/*! @brief Clock ip name array for CRC. */ -#define CRC_CLOCKS \ - { \ - kCLOCK_Crc \ - } -/*! @brief Clock ip name array for WWDT. */ -#define WWDT_CLOCKS \ - { \ - kCLOCK_Wwdt \ - } -/*! @brief Clock ip name array for RTC. */ -#define RTC_CLOCKS \ - { \ - kCLOCK_Rtc \ - } -/*! @brief Clock ip name array for ADC0. */ -#define ADC0_CLOCKS \ - { \ - kCLOCK_Adc0 \ - } -/*! @brief Clock ip name array for MRT. */ -#define MRT_CLOCKS \ - { \ - kCLOCK_Mrt \ - } -/*! @brief Clock ip name array for RIT. */ -#define RIT_CLOCKS \ - { \ - kCLOCK_Rit \ - } -/*! @brief Clock ip name array for SCT0. */ -#define SCT_CLOCKS \ - { \ - kCLOCK_Sct0 \ - } -/*! @brief Clock ip name array for MCAN. */ -#define MCAN_CLOCKS \ - { \ - kCLOCK_Mcan0, kCLOCK_Mcan1 \ - } -/*! @brief Clock ip name array for UTICK. */ -#define UTICK_CLOCKS \ - { \ - kCLOCK_Utick \ - } -/*! @brief Clock ip name array for FLEXCOMM. */ -#define FLEXCOMM_CLOCKS \ - { \ - kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, \ - kCLOCK_FlexComm4, kCLOCK_FlexComm5, kCLOCK_FlexComm6, kCLOCK_FlexComm7, \ - kCLOCK_FlexComm8, kCLOCK_FlexComm9 \ - } -/*! @brief Clock ip name array for LPUART. */ -#define LPUART_CLOCKS \ - { \ - kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \ - kCLOCK_MinUart6, kCLOCK_MinUart7, kCLOCK_MinUart8,kCLOCK_MinUart9 \ - } - -/*! @brief Clock ip name array for BI2C. */ -#define BI2C_CLOCKS \ - { \ - kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7, \ - kCLOCK_BI2c8, kCLOCK_BI2c9 \ - } -/*! @brief Clock ip name array for LSPI. */ -#define LPSI_CLOCKS \ - { \ - kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7, \ - kCLOCK_LSpi8, kCLOCK_LSpi9 \ - } -/*! @brief Clock ip name array for FLEXI2S. */ -#define FLEXI2S_CLOCKS \ - { \ - kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \ - kCLOCK_FlexI2s6, kCLOCK_FlexI2s7, kCLOCK_FlexI2s8, kCLOCK_FlexI2s9 \ - } -/*! @brief Clock ip name array for DMIC. */ -#define DMIC_CLOCKS \ - { \ - kCLOCK_DMic \ - } -/*! @brief Clock ip name array for CT32B. */ -#define CTIMER_CLOCKS \ - { \ - kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \ - } -/*! @brief Clock ip name array for LCD. */ -#define LCD_CLOCKS \ - { \ - kCLOCK_Lcd \ - } -/*! @brief Clock ip name array for SDIO. */ -#define SDIO_CLOCKS \ - { \ - kCLOCK_Sdio \ - } -/*! @brief Clock ip name array for USBRAM. */ -#define USBRAM_CLOCKS \ - { \ - kCLOCK_UsbRam1 \ - } -/*! @brief Clock ip name array for EMC. */ -#define EMC_CLOCKS \ - { \ - kCLOCK_Emc \ - } -/*! @brief Clock ip name array for ETH. */ -#define ETH_CLOCKS \ - { \ - kCLOCK_Eth \ - } -/*! @brief Clock ip name array for AES. */ -#define AES_CLOCKS \ - { \ - kCLOCK_Aes \ - } -/*! @brief Clock ip name array for OTP. */ -#define OTP_CLOCKS \ - { \ - kCLOCK_Otp \ - } -/*! @brief Clock ip name array for RNG. */ -#define RNG_CLOCKS \ - { \ - kCLOCK_Rng \ - } -/*! @brief Clock ip name array for USBHMR0. */ -#define USBHMR0_CLOCKS \ - { \ - kCLOCK_Usbhmr0 \ - } -/*! @brief Clock ip name array for USBHSL0. */ -#define USBHSL0_CLOCKS \ - { \ - kCLOCK_Usbhsl0 \ - } -/*! @brief Clock ip name array for SHA0. */ -#define SHA0_CLOCKS \ - { \ - kCLOCK_Sha0 \ - } -/*! @brief Clock ip name array for SMARTCARD. */ -#define SMARTCARD_CLOCKS \ - { \ - kCLOCK_SmartCard0, kCLOCK_SmartCard1 \ - } -/*! @brief Clock ip name array for USBD. */ -#define USBD_CLOCKS \ - { \ - kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \ - } -/*! @brief Clock ip name array for USBH. */ -#define USBH_CLOCKS \ - { \ - kCLOCK_Usbh1 \ - } -/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ -/*------------------------------------------------------------------------------ - clock_ip_name_t definition: -------------------------------------------------------------------------------*/ - -#define CLK_GATE_REG_OFFSET_SHIFT 8U -#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U -#define CLK_GATE_BIT_SHIFT_SHIFT 0U -#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU - -#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ - ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ - (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) - -#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) -#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) - -#define AHB_CLK_CTRL0 0 -#define AHB_CLK_CTRL1 1 -#define AHB_CLK_CTRL2 2 -#define ASYNC_CLK_CTRL0 3 - -/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ -typedef enum _clock_ip_name -{ - kCLOCK_IpInvalid = 0U, - kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), - kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), - kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), - kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), - kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), - kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), - kCLOCK_Eeprom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9), - kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), - kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), - kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), - kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), - kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), - kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), - kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), - kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), - kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), - kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), - kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), - kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), - kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), - kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), - kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), - kCLOCK_Rit = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), - kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), - kCLOCK_Mcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7), - kCLOCK_Mcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 8), - kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), - kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19), - kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), - kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), - kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), - kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), - kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29), - kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), - kCLOCK_Lcd = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), - kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3), - kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), - kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), - kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), - kCLOCK_Emc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), - kCLOCK_Eth = CLK_GATE_DEFINE(AHB_CLK_CTRL2,8), - kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9), - kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10), - kCLOCK_Aes = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11), - kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12), - kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), - kCLOCK_FlexComm8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), - kCLOCK_FlexComm9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), - kCLOCK_MinUart8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), - kCLOCK_MinUart9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), - kCLOCK_LSpi8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), - kCLOCK_LSpi9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), - kCLOCK_BI2c8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), - kCLOCK_BI2c9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), - kCLOCK_FlexI2s8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), - kCLOCK_FlexI2s9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), - kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), - kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), - kCLOCK_Sha0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), - kCLOCK_SmartCard0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19), - kCLOCK_SmartCard1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), - - kCLOCK_Ct32b3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13), - kCLOCK_Ct32b4 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14) -} clock_ip_name_t; - -/*! @brief Clock name used to get clock frequency. */ -typedef enum _clock_name -{ - kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ - kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ - kCLOCK_ClockOut, /*!< CLOCKOUT */ - kCLOCK_FroHf, /*!< FRO48/96 */ - kCLOCK_SpiFi, /*!< SPIFI */ - kCLOCK_Adc, /*!< ADC */ - kCLOCK_Usb0, /*!< USB0 */ - kCLOCK_Usb1, /*!< USB1 */ - kCLOCK_UsbPll, /*!< USB1 PLL */ - kCLOCK_Mclk, /*!< MCLK */ - kCLOCK_Sct, /*!< SCT */ - kCLOCK_SDio, /*!< SDIO */ - kCLOCK_EMC, /*!< EMC */ - kCLOCK_LCD, /*!< LCD */ - kCLOCK_MCAN0, /*!< MCAN0 */ - kCLOCK_MCAN1, /*!< MCAN1 */ - kCLOCK_Fro12M, /*!< FRO12M */ - kCLOCK_ExtClk, /*!< External Clock */ - kCLOCK_PllOut, /*!< PLL Output */ - kCLOCK_UsbClk, /*!< USB input */ - kClock_WdtOsc, /*!< Watchdog Oscillator */ - kCLOCK_Frg, /*!< Frg Clock */ - kCLOCK_Dmic, /*!< Digital Mic clock */ - kCLOCK_AsyncApbClk, /*!< Async APB clock */ - kCLOCK_FlexI2S, /*!< FlexI2S clock */ - kCLOCK_Flexcomm0, /*!< Flexcomm0Clock */ - kCLOCK_Flexcomm1, /*!< Flexcomm1Clock */ - kCLOCK_Flexcomm2, /*!< Flexcomm2Clock */ - kCLOCK_Flexcomm3, /*!< Flexcomm3Clock */ - kCLOCK_Flexcomm4, /*!< Flexcomm4Clock */ - kCLOCK_Flexcomm5, /*!< Flexcomm5Clock */ - kCLOCK_Flexcomm6, /*!< Flexcomm6Clock */ - kCLOCK_Flexcomm7, /*!< Flexcomm7Clock */ - kCLOCK_Flexcomm8, /*!< Flexcomm8Clock */ - kCLOCK_Flexcomm9, /*!< Flexcomm9Clock */ - -} clock_name_t; - -/** - * Clock source selections for the asynchronous APB clock - */ -typedef enum _async_clock_src -{ - kCLOCK_AsyncMainClk = 0, /*!< Main System clock */ - kCLOCK_AsyncFro12Mhz, /*!< 12MHz FRO */ - kCLOCK_AsyncAudioPllClk, - kCLOCK_AsyncI2cClkFc6, - -} async_clock_src_t; - -/*! @brief Clock Mux Switches -* The encoding is as follows each connection identified is 64bits wide -* starting from LSB upwards -* -* [4 bits for choice, where 1 is A, 2 is B, 3 is C and 4 is D, 0 means end of descriptor] [8 bits mux ID]* -* -*/ - -#define MUX_A(m, choice) (((m) << 0) | ((choice + 1) << 8)) -#define MUX_B(m, choice) (((m) << 12) | ((choice + 1) << 20)) -#define MUX_C(m, choice) (((m) << 24) | ((choice + 1) << 32)) -#define MUX_D(m, choice) (((m) << 36) | ((choice + 1) << 44)) -#define MUX_E(m, choice) (((m) << 48) | ((choice + 1) << 56)) - -#define CM_MAINCLKSELA 0 -#define CM_MAINCLKSELB 1 -#define CM_CLKOUTCLKSELA 2 -#define CM_SYSPLLCLKSEL 4 -#define CM_AUDPLLCLKSEL 6 -#define CM_SPIFICLKSEL 8 -#define CM_ADCASYNCCLKSEL 9 -#define CM_USB0CLKSEL 10 -#define CM_USB1CLKSEL 11 -#define CM_FXCOMCLKSEL0 12 -#define CM_FXCOMCLKSEL1 13 -#define CM_FXCOMCLKSEL2 14 -#define CM_FXCOMCLKSEL3 15 -#define CM_FXCOMCLKSEL4 16 -#define CM_FXCOMCLKSEL5 17 -#define CM_FXCOMCLKSEL6 18 -#define CM_FXCOMCLKSEL7 19 -#define CM_FXCOMCLKSEL8 20 -#define CM_FXCOMCLKSEL9 21 -#define CM_MCLKCLKSEL 24 -#define CM_FRGCLKSEL 26 -#define CM_DMICCLKSEL 27 -#define CM_SCTCLKSEL 28 -#define CM_LCDCLKSEL 29 -#define CM_SDIOCLKSEL 30 - -#define CM_ASYNCAPB 31 - -typedef enum _clock_attach_id -{ - - kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0), - kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0), - kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0), - kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0), - kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 2), - kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 3), - - kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0), - kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1), - kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2), - kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3), - kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4), - kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5), - kAUDIO_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6), - kOSC32K_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7), - - kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0), - kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1), - kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2), - kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3), - kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7), - - kFRO12M_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 0), - kEXT_CLK_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 1), - kNONE_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 7), - - kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0), - kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1), - kUSB_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 2), - kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3), - kAUDIO_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 4), - kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7), - - kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), - kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), - kUSB_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), - kAUDIO_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3), - kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), - - kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0), - kSYS_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1), - kUSB_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 2), - kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7), - - kFRO_HF_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 0), - kSYS_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 1), - kUSB_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 2), - kNONE_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 7), - - kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), - kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), - kAUDIO_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), - kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), - kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), - kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), - - kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), - kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), - kAUDIO_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), - kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), - kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), - kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), - - kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), - kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), - kAUDIO_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), - kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), - kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), - kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), - - kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), - kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), - kAUDIO_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), - kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), - kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), - kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), - - kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), - kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), - kAUDIO_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), - kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), - kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), - kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), - - kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), - kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), - kAUDIO_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), - kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), - kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), - kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), - - kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), - kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), - kAUDIO_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), - kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), - kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), - kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), - - kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), - kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), - kAUDIO_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), - kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), - kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), - kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), - - kFRO12M_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 0), - kFRO_HF_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 1), - kAUDIO_PLL_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 2), - kMCLK_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 3), - kFRG_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 4), - kNONE_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 7), - - kFRO12M_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 0), - kFRO_HF_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 1), - kAUDIO_PLL_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 2), - kMCLK_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 3), - kFRG_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 4), - kNONE_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 7), - - kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), - kAUDIO_PLL_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), - kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), - - kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0), - kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1), - kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2), - kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3), - kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7), - - kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0), - kFRO_HF_DIV_to_DMIC = MUX_A(CM_DMICCLKSEL, 1), - kAUDIO_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2), - kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3), - kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7), - - kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), - kSYS_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), - kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), - kAUDIO_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), - kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), - - kMCLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0), - kSYS_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1), - kUSB_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 2), - kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3), - kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 4), - kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7), - - kMCLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0), - kLCDCLKIN_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 1), - kFRO_HF_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 2), - kNONE_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 3), - - kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0), - kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1), - kAUDIO_PLL_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 2), - kI2C_CLK_FC6_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 3), - kNONE_to_NONE = 0x80000000U, -} clock_attach_id_t; - -/* Clock dividers */ -typedef enum _clock_div_name -{ - kCLOCK_DivSystickClk = 0, - kCLOCK_DivArmTrClkDiv = 1, - kCLOCK_DivCan0Clk = 2, - kCLOCK_DivCan1Clk = 3, - kCLOCK_DivSmartCard0Clk = 4, - kCLOCK_DivSmartCard1Clk = 5, - kCLOCK_DivAhbClk = 32, - kCLOCK_DivClkOut = 33, - kCLOCK_DivFrohfClk = 34, - kCLOCK_DivSpifiClk = 36, - kCLOCK_DivAdcAsyncClk = 37, - kCLOCK_DivUsb0Clk = 38, - kCLOCK_DivUsb1Clk = 39, - kCLOCK_DivFrg = 40, - kCLOCK_DivDmicClk = 42, - kCLOCK_DivMClk = 43, - kCLOCK_DivLcdClk = 44, - kCLOCK_DivSctClk = 45, - kCLOCK_DivEmcClk = 46, - kCLOCK_DivSdioClk = 47 -} clock_div_name_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -static inline void CLOCK_EnableClock(clock_ip_name_t clk) -{ - uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - if (index < 3) - { - SYSCON->AHBCLKCTRLSET[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); - } - else - { - SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1); - ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); - } -} - -static inline void CLOCK_DisableClock(clock_ip_name_t clk) -{ - uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - if (index < 3) - { - SYSCON->AHBCLKCTRLCLR[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); - } - else - { - ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); - SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(0); - - } -} -/** - * @brief FLASH Access time definitions - */ -typedef enum _clock_flashtim -{ - kCLOCK_Flash1Cycle = 0, /*!< Flash accesses use 1 CPU clocks */ - kCLOCK_Flash2Cycle, /*!< Flash accesses use 2 CPU clocks */ - kCLOCK_Flash3Cycle, /*!< Flash accesses use 3 CPU clocks */ - kCLOCK_Flash4Cycle, /*!< Flash accesses use 4 CPU clocks */ - kCLOCK_Flash5Cycle, /*!< Flash accesses use 5 CPU clocks */ - kCLOCK_Flash6Cycle, /*!< Flash accesses use 6 CPU clocks */ - kCLOCK_Flash7Cycle, /*!< Flash accesses use 7 CPU clocks */ - kCLOCK_Flash8Cycle, /*!< Flash accesses use 8 CPU clocks */ - kCLOCK_Flash9Cycle /*!< Flash accesses use 9 CPU clocks */ -} clock_flashtim_t; - -/** - * @brief Set FLASH memory access time in clocks - * @param clks : Clock cycles for FLASH access - * @return Nothing - */ -static inline void CLOCK_SetFLASHAccessCycles(clock_flashtim_t clks) -{ - uint32_t tmp; - - tmp = SYSCON->FLASHCFG & ~(SYSCON_FLASHCFG_FLASHTIM_MASK); - - /* Don't alter lower bits */ - SYSCON->FLASHCFG = tmp | ((uint32_t)clks << SYSCON_FLASHCFG_FLASHTIM_SHIFT); -} - -/** - * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). - * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is - * enabled. - * @param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ) - * @return returns success or fail status. - */ -status_t CLOCK_SetupFROClocking(uint32_t iFreq); -/** - * @brief Configure the clock selection muxes. - * @param connection : Clock to be configured. - * @return Nothing - */ -void CLOCK_AttachClk(clock_attach_id_t connection); -/** - * @brief Setup peripheral clock dividers. - * @param div_name : Clock divider name - * @param divided_by_value: Value to be divided - * @param reset : Whether to reset the divider counter. - * @return Nothing - */ -void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset); -/** - * @brief Set the flash wait states for the input freuqency. - * @param iFreq : Input frequency - * @return Nothing - */ -void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq); -/*! @brief Return Frequency of selected clock - * @return Frequency of selected clock - */ -uint32_t CLOCK_GetFreq(clock_name_t clockName); -/*! @brief Return Frequency of FRO 12MHz - * @return Frequency of FRO 12MHz - */ -uint32_t CLOCK_GetFro12MFreq(void); -/*! @brief Return Frequency of ClockOut - * @return Frequency of ClockOut - */ -uint32_t CLOCK_GetClockOutClkFreq(void); -/*! @brief Return Frequency of Spifi Clock - * @return Frequency of Spifi. - */ -uint32_t CLOCK_GetSpifiClkFreq(void); -/*! @brief Return Frequency of Adc Clock - * @return Frequency of Adc Clock. - */ -uint32_t CLOCK_GetAdcClkFreq(void); -/*! @brief Return Frequency of Usb0 Clock - * @return Frequency of Usb0 Clock. - */ -uint32_t CLOCK_GetUsb0ClkFreq(void); -/*! @brief Return Frequency of Usb1 Clock - * @return Frequency of Usb1 Clock. - */ -uint32_t CLOCK_GetUsb1ClkFreq(void); -/*! @brief Return Frequency of MClk Clock - * @return Frequency of MClk Clock. - */ -uint32_t CLOCK_GetMclkClkFreq(void); -/*! @brief Return Frequency of SCTimer Clock - * @return Frequency of SCTimer Clock. - */ -uint32_t CLOCK_GetSctClkFreq(void); -/*! @brief Return Frequency of SDIO Clock - * @return Frequency of SDIO Clock. - */ -uint32_t CLOCK_GetSdioClkFreq(void); -/*! @brief Return Frequency of LCD Clock - * @return Frequency of LCD Clock. - */ -uint32_t CLOCK_GetLcdClkFreq(void); -/*! @brief Return Frequency of LCD CLKIN Clock - * @return Frequency of LCD CLKIN Clock. - */ -uint32_t CLOCK_GetLcdClkIn(void); -/*! @brief Return Frequency of External Clock - * @return Frequency of External Clock. If no external clock is used returns 0. - */ -uint32_t CLOCK_GetExtClkFreq(void); -/*! @brief Return Frequency of Watchdog Oscillator - * @return Frequency of Watchdog Oscillator - */ -uint32_t CLOCK_GetWdtOscFreq(void); -/*! @brief Return Frequency of High-Freq output of FRO - * @return Frequency of High-Freq output of FRO - */ -uint32_t CLOCK_GetFroHfFreq(void); -/*! @brief Return Frequency of PLL - * @return Frequency of PLL - */ -uint32_t CLOCK_GetPllOutFreq(void); -/*! @brief Return Frequency of USB PLL - * @return Frequency of PLL - */ -uint32_t CLOCK_GetUsbPllOutFreq(void); -/*! @brief Return Frequency of AUDIO PLL - * @return Frequency of PLL - */ -uint32_t CLOCK_GetAudioPllOutFreq(void); -/*! @brief Return Frequency of 32kHz osc - * @return Frequency of 32kHz osc - */ -uint32_t CLOCK_GetOsc32KFreq(void); -/*! @brief Return Frequency of Core System - * @return Frequency of Core System - */ -uint32_t CLOCK_GetCoreSysClkFreq(void); -/*! @brief Return Frequency of I2S MCLK Clock - * @return Frequency of I2S MCLK Clock - */ -uint32_t CLOCK_GetI2SMClkFreq(void); -/*! @brief Return Frequency of Flexcomm functional Clock - * @return Frequency of Flexcomm functional Clock - */ -uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id); -/*! @brief Return Asynchronous APB Clock source - * @return Asynchronous APB CLock source - */ -__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void) -{ - return (async_clock_src_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3); -} -/*! @brief Return Frequency of Asynchronous APB Clock - * @return Frequency of Asynchronous APB Clock Clock - */ -uint32_t CLOCK_GetAsyncApbClkFreq(void); -/*! @brief Return Audio PLL input clock rate - * @return Audio PLL input clock rate - */ -uint32_t CLOCK_GetAudioPLLInClockRate(void); -/*! @brief Return System PLL input clock rate - * @return System PLL input clock rate - */ -uint32_t CLOCK_GetSystemPLLInClockRate(void); - -/*! @brief Return System PLL output clock rate - * @param recompute : Forces a PLL rate recomputation if true - * @return System PLL output clock rate - * @note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute); - -/*! @brief Return System AUDIO PLL output clock rate - * @param recompute : Forces a AUDIO PLL rate recomputation if true - * @return System AUDIO PLL output clock rate - * @note The AUDIO PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute); - -/*! @brief Return System USB PLL output clock rate - * @param recompute : Forces a USB PLL rate recomputation if true - * @return System USB PLL output clock rate - * @note The USB PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetUSbPLLOutClockRate(bool recompute); - -/*! @brief Enables and disables PLL bypass mode - * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass - * @return System PLL output clock rate - */ -__STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass) -{ - if (bypass) - { - SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT); - } - else - { - SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT); - } -} - -/*! @brief Check if PLL is locked or not - * @return true if the PLL is locked, false if not locked - */ -__STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void) -{ - return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0); -} - -/*! @brief Check if USB PLL is locked or not - * @return true if the USB PLL is locked, false if not locked - */ -__STATIC_INLINE bool CLOCK_IsUsbPLLLocked(void) -{ - return (bool)((SYSCON->USBPLLSTAT & SYSCON_USBPLLSTAT_LOCK_MASK) != 0); -} - -/*! @brief Check if AUDIO PLL is locked or not - * @return true if the AUDIO PLL is locked, false if not locked - */ -__STATIC_INLINE bool CLOCK_IsAudioPLLLocked(void) -{ - return (bool)((SYSCON->AUDPLLSTAT & SYSCON_AUDPLLSTAT_LOCK_MASK) != 0); -} - -/*! @brief Enables and disables SYS OSC - * @brief enable : true to enable SYS OSC, false to disable SYS OSC -*/ -__STATIC_INLINE void CLOCK_Enable_SysOsc(bool enable) -{ - if(enable) - { - SYSCON->PDRUNCFGCLR[0] |= SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK; - SYSCON->PDRUNCFGCLR[1] |= SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK; - } - - else - { - SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK; - SYSCON->PDRUNCFGSET[1] = SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK; - - } -} - -/*! @brief Store the current PLL rate - * @param rate: Current rate of the PLL - * @return Nothing - **/ -void CLOCK_SetStoredPLLClockRate(uint32_t rate); - -/*! @brief Store the current AUDIO PLL rate - * @param rate: Current rate of the PLL - * @return Nothing - **/ -void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate); - -/*! @brief PLL configuration structure flags for 'flags' field - * These flags control how the PLL configuration function sets up the PLL setup structure.
- * - * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the - * configuration structure must be assigned with the expected PLL frequency. If the - * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration - * function and the driver will determine the PLL rate from the currently selected - * PLL source. This flag might be used to configure the PLL input clock more accurately - * when using the WDT oscillator or a more dyanmic CLKIN source.
- * - * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the - * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider - * are not used.
- */ -#define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */ -#define PLL_CONFIGFLAG_FORCENOFRACT \ - (1 \ - << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS \ \ - \ \ \ \ - \ \ \ \ \ \ - \ \ \ \ \ \ \ \ - hardware */ - -/*! @brief PLL configuration structure - * - * This structure can be used to configure the settings for a PLL - * setup structure. Fill in the desired configuration for the PLL - * and call the PLL setup function to fill in a PLL setup structure. - */ -typedef struct _pll_config -{ - uint32_t desiredRate; /*!< Desired PLL rate in Hz */ - uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */ - uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ -} pll_config_t; - -/*! @brief PLL setup structure flags for 'flags' field -* These flags control how the PLL setup function sets up the PLL -*/ -#define PLL_SETUPFLAG_POWERUP (1 << 0) /*!< Setup will power on the PLL after setup */ -#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ -#define PLL_SETUPFLAG_ADGVOLT (1 << 2) /*!< Optimize system voltage for the new PLL rate */ - -/*! @brief PLL setup structure -* This structure can be used to pre-build a PLL setup configuration -* at run-time and quickly set the PLL to the configuration. It can be -* populated with the PLL setup function. If powering up or waiting -* for PLL lock, the PLL input clock source should be configured prior -* to PLL setup. -*/ -typedef struct _pll_setup -{ - uint32_t pllctrl; /*!< PLL control register SYSPLLCTRL */ - uint32_t pllndec; /*!< PLL NDEC register SYSPLLNDEC */ - uint32_t pllpdec; /*!< PLL PDEC register SYSPLLPDEC */ - uint32_t pllmdec; /*!< PLL MDEC registers SYSPLLPDEC */ - uint32_t pllRate; /*!< Acutal PLL rate */ - uint32_t audpllfrac; /*!< only aduio PLL has this function*/ - uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ -} pll_setup_t; - -/*! @brief PLL status definitions - */ -typedef enum _pll_error -{ - kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ - kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ - kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ - kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ - kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ - kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */ - kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */ - kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */ -} pll_error_t; - -/*! @brief USB clock source definition. */ -typedef enum _clock_usb_src -{ - kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */ - kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */ - kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */ - kCLOCK_UsbSrcUsbPll = (uint32_t)kCLOCK_UsbPll, /*!< Use USB PLL clock. */ - - kCLOCK_UsbSrcNone = SYSCON_USB0CLKSEL_SEL(7) /*!< Use None, this may be selected in order to reduce power when no output is needed.. */ -} clock_usb_src_t; - -/*! @brief USB PDEL Divider. */ -typedef enum _usb_pll_psel -{ - pSel_Divide_1 = 0U, - pSel_Divide_2, - pSel_Divide_4, - pSel_Divide_8 -}usb_pll_psel; - -/*! @brief PLL setup structure -* This structure can be used to pre-build a USB PLL setup configuration -* at run-time and quickly set the usb PLL to the configuration. It can be -* populated with the USB PLL setup function. If powering up or waiting -* for USB PLL lock, the PLL input clock source should be configured prior -* to USB PLL setup. -*/ -typedef struct _usb_pll_setup -{ - uint8_t msel; /*!< USB PLL control register msel:1U-256U */ - uint8_t psel; /*!< USB PLL control register psel:only support inter 1U 2U 4U 8U */ - uint8_t nsel; /*!< USB PLL control register nsel:only suppoet inter 1U 2U 3U 4U */ - bool direct; /*!< USB PLL CCO output control */ - bool bypass; /*!< USB PLL inout clock bypass control */ - bool fbsel; /*!< USB PLL ineter mode and non-integer mode control*/ - uint32_t inputRate; /*!< USB PLL input rate */ -} usb_pll_setup_t; - -/*! @brief Return System PLL output clock rate from setup structure - * @param pSetup : Pointer to a PLL setup structure - * @return System PLL output clock rate the setup structure will generate - */ -uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup); - -/*! @brief Return System AUDIO PLL output clock rate from setup structure - * @param pSetup : Pointer to a PLL setup structure - * @return System PLL output clock rate the setup structure will generate - */ -uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup); - -/*! @brief Return System USB PLL output clock rate from setup structure - * @param pSetup : Pointer to a PLL setup structure - * @return System PLL output clock rate the setup structure will generate - */ -uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup); - -/*! @brief Set PLL output based on the passed PLL setup data - * @param pControl : Pointer to populated PLL control structure to generate setup with - * @param pSetup : Pointer to PLL setup structure to be filled - * @return PLL_ERROR_SUCCESS on success, or PLL setup error code - * @note Actual frequency for setup may vary from the desired frequency based on the - * accuracy of input clocks, rounding, non-fractional PLL mode, etc. - */ -pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup); - -/*! @brief Set AUDIO PLL output based on the passed AUDIO PLL setup data - * @param pControl : Pointer to populated PLL control structure to generate setup with - * @param pSetup : Pointer to PLL setup structure to be filled - * @return PLL_ERROR_SUCCESS on success, or PLL setup error code - * @note Actual frequency for setup may vary from the desired frequency based on the - * accuracy of input clocks, rounding, non-fractional PLL mode, etc. - */ -pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup); - -/*! @brief Set PLL output from PLL setup structure (precise frequency) - * @param pSetup : Pointer to populated PLL setup structure -* @param flagcfg : Flag configuration for PLL config structure - * @return PLL_ERROR_SUCCESS on success, or PLL setup error code - * @note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg); - -/*! @brief Set AUDIO PLL output from AUDIOPLL setup structure (precise frequency) - * @param pSetup : Pointer to populated PLL setup structure -* @param flagcfg : Flag configuration for PLL config structure - * @return PLL_ERROR_SUCCESS on success, or PLL setup error code - * @note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock, - * and adjust system voltages to the new AUDIOPLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg); - -/** - * @brief Set PLL output from PLL setup structure (precise frequency) - * @param pSetup : Pointer to populated PLL setup structure - * @return kStatus_PLL_Success on success, or PLL setup error code - * @note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup); - -/** - * @brief Set Audio PLL output from Audio PLL setup structure (precise frequency) - * @param pSetup : Pointer to populated PLL setup structure - * @return kStatus_PLL_Success on success, or Audio PLL setup error code - * @note This function will power off the PLL, setup the Audio PLL with the - * new setup data, and then optionally powerup the PLL, wait for Audio PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the Audio PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup); - -/** - * @brief Set USB PLL output from USB PLL setup structure (precise frequency) - * @param pSetup : Pointer to populated USB PLL setup structure - * @return kStatus_PLL_Success on success, or USB PLL setup error code - * @note This function will power off the USB PLL, setup the PLL with the - * new setup data, and then optionally powerup the USB PLL, wait for USB PLL lock, - * and adjust system voltages to the new USB PLL rate. The function will not - * alter any source clocks (ie, usb pll clock) that may use the USB PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup); - -/*! @brief Set PLL output based on the multiplier and input frequency - * @param multiply_by : multiplier - * @param input_freq : Clock input frequency of the PLL - * @return Nothing - * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this - * function does not disable or enable PLL power, wait for PLL lock, - * or adjust system voltages. These must be done in the application. - * The function will not alter any source clocks (ie, main systen clock) - * that may use the PLL, so these should be setup prior to and after - * exiting the function. - */ -void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq); - -/*! @brief Disable USB clock. - * - * Disable USB clock. - */ -static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk) -{ - CLOCK_DisableClock(clk); -} - -/*! @brief Enable USB Device FS clock. - * @param src : clock source - * @param freq: clock frequency - * Enable USB Device Full Speed clock. - */ -bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq); - -/*! @brief Enable USB HOST FS clock. - * @param src : clock source - * @param freq: clock frequency - * Enable USB HOST Full Speed clock. - */ -bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq); - -/*! @brief Enable USB Device HS clock. - * @param src : clock source - * @param freq: clock frequency - * Enable USB Device High Speed clock. - */ -bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq); - -/*! @brief Enable USB HOST HS clock. - * @param src : clock source - * @param freq: clock frequency - * Enable USB HOST High Speed clock. - */ -bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @} */ - -#endif /* _FSL_CLOCK_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_common.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_common.c deleted file mode 100644 index f8ceee3bd8a..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_common.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_common.h" -#include "fsl_debug_console.h" - -#ifndef NDEBUG -#if (defined(__CC_ARM)) || (defined(__ICCARM__)) -void __aeabi_assert(const char *failedExpr, const char *file, int line) -{ - PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); - for (;;) - { - __BKPT(0); - } -} -#elif(defined(__REDLIB__)) - -#if SDK_DEBUGCONSOLE -void __assertion_failed(char *_Expr) -{ - PRINTF("%s\n", _Expr); - for (;;) - { - __asm("bkpt #0"); - } -} -#endif - -#elif(defined(__GNUC__)) -void __assert_func(const char *file, int line, const char *func, const char *failedExpr) -{ - PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func); - for (;;) - { - __BKPT(0); - } -} -#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */ -#endif /* NDEBUG */ - -//#ifndef __GIC_PRIO_BITS -//uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) -//{ -///* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ -//#if defined(__CC_ARM) -// extern uint32_t Image$$VECTOR_ROM$$Base[]; -// extern uint32_t Image$$VECTOR_RAM$$Base[]; -// extern uint32_t Image$$RW_m_data$$Base[]; - -//#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base -//#define __VECTOR_RAM Image$$VECTOR_RAM$$Base -//#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) -//#elif defined(__ICCARM__) -// extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; -// extern uint32_t __VECTOR_TABLE[]; -// extern uint32_t __VECTOR_RAM[]; -//#elif defined(__GNUC__) -// extern uint32_t __VECTOR_TABLE[]; -// extern uint32_t __VECTOR_RAM[]; -// extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; -// uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); -//#endif /* defined(__CC_ARM) */ -// uint32_t n; -// uint32_t ret; -// uint32_t irqMaskValue; - -// irqMaskValue = DisableGlobalIRQ(); -// if (SCB->VTOR != (uint32_t)__VECTOR_RAM) -// { -// /* Copy the vector table from ROM to RAM */ -// for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) -// { -// __VECTOR_RAM[n] = __VECTOR_TABLE[n]; -// } -// /* Point the VTOR to the position of vector table */ -// SCB->VTOR = (uint32_t)__VECTOR_RAM; -// } - -// ret = __VECTOR_RAM[irq + 16]; -// /* make sure the __VECTOR_RAM is noncachable */ -// __VECTOR_RAM[irq + 16] = irqHandler; - -// EnableGlobalIRQ(irqMaskValue); - -// return ret; -//} -//#endif - -#ifndef CPU_QN908X -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - -void EnableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t index = 0; - uint32_t intNumber = (uint32_t)interrupt; - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERSET[index] = 1u << intNumber; - EnableIRQ(interrupt); /* also enable interrupt at NVIC */ -} - -void DisableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t index = 0; - uint32_t intNumber = (uint32_t)interrupt; - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - DisableIRQ(interrupt); /* also disable interrupt at NVIC */ - SYSCON->STARTERCLR[index] = 1u << intNumber; -} -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ -#else -void EnableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t index = 0; - uint32_t intNumber = (uint32_t)interrupt; - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - /* SYSCON->STARTERSET[index] = 1u << intNumber; */ - EnableIRQ(interrupt); /* also enable interrupt at NVIC */ -} - -void DisableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t index = 0; - uint32_t intNumber = (uint32_t)interrupt; - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - DisableIRQ(interrupt); /* also disable interrupt at NVIC */ - /* SYSCON->STARTERCLR[index] = 1u << intNumber; */ -} -#endif /*CPU_QN908X */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_common.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_common.h deleted file mode 100644 index f20c09027e9..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_common.h +++ /dev/null @@ -1,348 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_COMMON_H_ -#define _FSL_COMMON_H_ - -#include -#include -#include -#include - -#if defined(__ICCARM__) -#include -#endif - -#include "fsl_device_registers.h" - -/*! - * @addtogroup ksdk_common - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Construct a status code value from a group and code number. */ -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) - -/*! @brief Construct the version number for drivers. */ -#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) - -/* Debug console type definition. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */ - -/*! @brief Status group numbers. */ -enum _status_groups -{ - kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ - kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ - kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ - kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ - kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ - kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ - kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ - kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ - kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ - kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ - kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ - kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ - kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ - kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ - kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ - kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ - kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ - kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ - kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ - kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ - kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ - kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ - kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ - kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ - kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ - kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ - kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ - kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ - kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ - kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ - kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ - kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ - kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ - kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ - kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ - kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ - kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ - kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ - kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ - kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ - kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ - kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ - kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ - kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ - kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ - kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ - kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ - kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ - kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ - kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ - kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ - kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ - kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ - kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ - kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ - kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */ -}; - -/*! @brief Generic status return codes. */ -enum _generic_status -{ - kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), - kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), - kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), - kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), - kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), - kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), - kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), -}; - -/*! @brief Type used for all status and error return values. */ -typedef int32_t status_t; - -/* - * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t - * defined in previous of this file. - */ -#include "fsl_clock.h" - -/* - * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral - */ -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) -#include "fsl_reset.h" -#endif - -/*! @name Min/max macros */ -/* @{ */ -#if !defined(MIN) -#define MIN(a, b) ((a) < (b) ? (a) : (b)) -#endif - -#if !defined(MAX) -#define MAX(a, b) ((a) > (b) ? (a) : (b)) -#endif -/* @} */ - -/*! @brief Computes the number of elements in an array. */ -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - -/*! @name UINT16_MAX/UINT32_MAX value */ -/* @{ */ -#if !defined(UINT16_MAX) -#define UINT16_MAX ((uint16_t)-1) -#endif - -#if !defined(UINT32_MAX) -#define UINT32_MAX ((uint32_t)-1) -#endif -/* @} */ - -/*! @name Timer utilities */ -/* @{ */ -/*! Macro to convert a microsecond period to raw count value */ -#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) -/*! Macro to convert a raw count value to microsecond */ -#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) - -/*! Macro to convert a millisecond period to raw count value */ -#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) -/*! Macro to convert a raw count value to millisecond */ -#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) -/* @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Enable specific interrupt. - * - * Enable the interrupt not routed from intmux. - * - * @param interrupt The IRQ number. - */ -static inline void EnableIRQ(IRQn_Type interrupt) -{ - if (NotAvail_IRQn == interrupt) - { - return; - } - -#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0) - if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX) -#endif - { -#if defined(__GIC_PRIO_BITS) - GIC_EnableIRQ(interrupt); -#else - NVIC_EnableIRQ(interrupt); -#endif - } -} - -/*! - * @brief Disable specific interrupt. - * - * Disable the interrupt not routed from intmux. - * - * @param interrupt The IRQ number. - */ -static inline void DisableIRQ(IRQn_Type interrupt) -{ - if (NotAvail_IRQn == interrupt) - { - return; - } - -#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0) - if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX) -#endif - { -#if defined(__GIC_PRIO_BITS) - GIC_DisableIRQ(interrupt); -#else - NVIC_DisableIRQ(interrupt); -#endif - } -} - -/*! - * @brief Disable the global IRQ - * - * Disable the global interrupt and return the current primask register. User is required to provided the primask - * register for the EnableGlobalIRQ(). - * - * @return Current primask value. - */ -static inline uint32_t DisableGlobalIRQ(void) -{ -#if defined(CPSR_I_Msk) - uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; - - __disable_irq(); - - return cpsr; -#else - uint32_t regPrimask = __get_PRIMASK(); - - __disable_irq(); - - return regPrimask; -#endif -} - -/*! - * @brief Enaable the global IRQ - * - * Set the primask register with the provided primask value but not just enable the primask. The idea is for the - * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to - * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. - * - * @param primask value of primask register to be restored. The primask value is supposed to be provided by the - * DisableGlobalIRQ(). - */ -static inline void EnableGlobalIRQ(uint32_t primask) -{ -#if defined(CPSR_I_Msk) - __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); -#else - __set_PRIMASK(primask); -#endif -} - -/*! - * @brief install IRQ handler - * - * @param irq IRQ number - * @param irqHandler IRQ handler address - * @return The old IRQ handler address - */ -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) -/*! - * @brief Enable specific interrupt for wake-up from deep-sleep mode. - * - * Enable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally). - * - * @param interrupt The IRQ number. - */ -void EnableDeepSleepIRQ(IRQn_Type interrupt); - -/*! - * @brief Disable specific interrupt for wake-up from deep-sleep mode. - * - * Disable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally). - * - * @param interrupt The IRQ number. - */ -void DisableDeepSleepIRQ(IRQn_Type interrupt); -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_COMMON_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_crc.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_crc.c deleted file mode 100644 index e413222dec8..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_crc.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_crc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT -/* @brief Default user configuration structure for CRC-CCITT */ -#define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT -/*< CRC-CCIT polynomial x^16 + x^12 + x^5 + x^0 */ -#define CRC_DRIVER_DEFAULT_REVERSE_IN false -/*< Default is no bit reverse */ -#define CRC_DRIVER_DEFAULT_COMPLEMENT_IN false -/*< Default is without complement of written data */ -#define CRC_DRIVER_DEFAULT_REVERSE_OUT false -/*< Default is no bit reverse */ -#define CRC_DRIVER_DEFAULT_COMPLEMENT_OUT false -/*< Default is without complement of CRC data register read data */ -#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU -/*< Default initial checksum */ -#endif /* CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -void CRC_Init(CRC_Type *base, const crc_config_t *config) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* enable clock to CRC */ - CLOCK_EnableClock(kCLOCK_Crc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* configure CRC module and write the seed */ - base->MODE = 0 | CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) | - CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) | - CRC_MODE_CMPL_SUM(config->complementOut); - base->SEED = config->seed; -} - -void CRC_GetDefaultConfig(crc_config_t *config) -{ - static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_REVERSE_IN, - CRC_DRIVER_DEFAULT_COMPLEMENT_IN, CRC_DRIVER_DEFAULT_REVERSE_OUT, - CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED}; - - *config = default_config; -} - -void CRC_Reset(CRC_Type *base) -{ - crc_config_t config; - CRC_GetDefaultConfig(&config); - CRC_Init(base, &config); -} - -void CRC_GetConfig(CRC_Type *base, crc_config_t *config) -{ - /* extract CRC mode settings */ - uint32_t mode = base->MODE; - config->polynomial = (crc_polynomial_t)((mode & CRC_MODE_CRC_POLY_MASK) >> CRC_MODE_CRC_POLY_SHIFT); - config->reverseIn = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK); - config->complementIn = (bool)(mode & CRC_MODE_CMPL_WR_MASK); - config->reverseOut = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK); - config->complementOut = (bool)(mode & CRC_MODE_CMPL_SUM_MASK); - - /* reset CRC sum bit reverse and 1's complement setting, so its value can be used as a seed */ - base->MODE = mode & ~((1U << CRC_MODE_BIT_RVS_SUM_SHIFT) | (1U << CRC_MODE_CMPL_SUM_SHIFT)); - - /* now we can obtain intermediate raw CRC sum value */ - config->seed = base->SUM; - - /* restore original CRC sum bit reverse and 1's complement setting */ - base->MODE = mode; -} - -void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) -{ - const uint32_t *data32; - - /* 8-bit reads and writes till source address is aligned 4 bytes */ - while ((dataSize) && ((uint32_t)data & 3U)) - { - *((__O uint8_t *)&(base->WR_DATA)) = *data; - data++; - dataSize--; - } - - /* use 32-bit reads and writes as long as possible */ - data32 = (const uint32_t *)data; - while (dataSize >= sizeof(uint32_t)) - { - *((__O uint32_t *)&(base->WR_DATA)) = *data32; - data32++; - dataSize -= sizeof(uint32_t); - } - - data = (const uint8_t *)data32; - - /* 8-bit reads and writes till end of data buffer */ - while (dataSize) - { - *((__O uint8_t *)&(base->WR_DATA)) = *data; - data++; - dataSize--; - } -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_crc.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_crc.h deleted file mode 100644 index 5b1338d9b19..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_crc.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_CRC_H_ -#define _FSL_CRC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup crc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CRC driver version. Version 2.0.1. - * - * Current version: 2.0.1 - * - * Change log: - * - Version 2.0.0 - * - initial version - * - Version 2.0.1 - * - add explicit type cast when writing to WR_DATA - */ -#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -#ifndef CRC_DRIVER_CUSTOM_DEFAULTS -/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Uses CRC-16/CCITT-FALSE as default. */ -#define CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT 1 -#endif - -/*! @brief CRC polynomials to use. */ -typedef enum _crc_polynomial -{ - kCRC_Polynomial_CRC_CCITT = 0U, /*!< x^16+x^12+x^5+1 */ - kCRC_Polynomial_CRC_16 = 1U, /*!< x^16+x^15+x^2+1 */ - kCRC_Polynomial_CRC_32 = 2U /*!< x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */ -} crc_polynomial_t; - -/*! -* @brief CRC protocol configuration. -* -* This structure holds the configuration for the CRC protocol. -* -*/ -typedef struct _crc_config -{ - crc_polynomial_t polynomial; /*!< CRC polynomial. */ - bool reverseIn; /*!< Reverse bits on input. */ - bool complementIn; /*!< Perform 1's complement on input. */ - bool reverseOut; /*!< Reverse bits on output. */ - bool complementOut; /*!< Perform 1's complement on output. */ - uint32_t seed; /*!< Starting checksum value. */ -} crc_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Enables and configures the CRC peripheral module. - * - * This functions enables the CRC peripheral clock in the LPC SYSCON block. - * It also configures the CRC engine and starts checksum computation by writing the seed. - * - * @param base CRC peripheral address. - * @param config CRC module configuration structure. - */ -void CRC_Init(CRC_Type *base, const crc_config_t *config); - -/*! - * @brief Disables the CRC peripheral module. - * - * This functions disables the CRC peripheral clock in the LPC SYSCON block. - * - * @param base CRC peripheral address. - */ -static inline void CRC_Deinit(CRC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* disable clock to CRC */ - CLOCK_DisableClock(kCLOCK_Crc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief resets CRC peripheral module. - * - * @param base CRC peripheral address. - */ -void CRC_Reset(CRC_Type *base); - -/*! - * @brief Loads default values to CRC protocol configuration structure. - * - * Loads default values to CRC protocol configuration structure. The default values are: - * @code - * config->polynomial = kCRC_Polynomial_CRC_CCITT; - * config->reverseIn = false; - * config->complementIn = false; - * config->reverseOut = false; - * config->complementOut = false; - * config->seed = 0xFFFFU; - * @endcode - * - * @param config CRC protocol configuration structure - */ -void CRC_GetDefaultConfig(crc_config_t *config); - -/*! - * @brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure. - * - * The values, including seed, can be used to resume CRC calculation later. - - * @param base CRC peripheral address. - * @param config CRC protocol configuration structure - */ -void CRC_GetConfig(CRC_Type *base, crc_config_t *config); - -/*! - * @brief Writes data to the CRC module. - * - * Writes input data buffer bytes to CRC data register. - * - * @param base CRC peripheral address. - * @param data Input data stream, MSByte in data[0]. - * @param dataSize Size of the input data buffer in bytes. - */ -void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize); - -/*! - * @brief Reads 32-bit checksum from the CRC module. - * - * Reads CRC data register. - * - * @param base CRC peripheral address. - * @return final 32-bit checksum, after configured bit reverse and complement operations. - */ -static inline uint32_t CRC_Get32bitResult(CRC_Type *base) -{ - return base->SUM; -} - -/*! - * @brief Reads 16-bit checksum from the CRC module. - * - * Reads CRC data register. - * - * @param base CRC peripheral address. - * @return final 16-bit checksum, after configured bit reverse and complement operations. - */ -static inline uint16_t CRC_Get16bitResult(CRC_Type *base) -{ - return (uint16_t)base->SUM; -} - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_CRC_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_ctimer.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_ctimer.c deleted file mode 100644 index ac69e33344b..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_ctimer.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_ctimer.h" - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base Ctimer peripheral base address - * - * @return The Timer instance - */ -static uint32_t CTIMER_GetInstance(CTIMER_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to Timer bases for each instance. */ -static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to Timer clocks for each instance. */ -static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Pointers to Timer resets for each instance. */ -static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; - -/*! @brief Pointers real ISRs installed by drivers for each instance. */ -static ctimer_callback_t *s_ctimerCallback[FSL_FEATURE_SOC_CTIMER_COUNT] = {0}; - -/*! @brief Callback type installed by drivers for each instance. */ -static ctimer_callback_type_t ctimerCallbackType[FSL_FEATURE_SOC_CTIMER_COUNT] = {kCTIMER_SingleCallback}; - -/*! @brief Array to map timer instance to IRQ number. */ -static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t CTIMER_GetInstance(CTIMER_Type *base) -{ - uint32_t instance; - uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ctimerArrayCount; instance++) - { - if (s_ctimerBases[instance] == base) - { - break; - } - } - - assert(instance < ctimerArrayCount); - - return instance; -} - -void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) -{ - assert(config); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the timer clock*/ - CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the module */ - RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]); - - /* Setup the cimer mode and count select */ - base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input); - - /* Setup the timer prescale value */ - base->PR = CTIMER_PR_PRVAL(config->prescale); -} - -void CTIMER_Deinit(CTIMER_Type *base) -{ - uint32_t index = CTIMER_GetInstance(base); - /* Stop the timer */ - base->TCR &= ~CTIMER_TCR_CEN_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the timer clock*/ - CLOCK_DisableClock(s_ctimerClocks[index]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Disable IRQ at NVIC Level */ - DisableIRQ(s_ctimerIRQ[index]); -} - -void CTIMER_GetDefaultConfig(ctimer_config_t *config) -{ - assert(config); - - /* Run as a timer */ - config->mode = kCTIMER_TimerMode; - /* This field is ignored when mode is timer */ - config->input = kCTIMER_Capture_0; - /* Timer counter is incremented on every APB bus clock */ - config->prescale = 0; -} - -status_t CTIMER_SetupPwm(CTIMER_Type *base, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - bool enableInt) -{ - assert(pwmFreq_Hz > 0); - - uint32_t reg; - uint32_t period, pulsePeriod = 0; - uint32_t timerClock = srcClock_Hz / (base->PR + 1); - uint32_t index = CTIMER_GetInstance(base); - - if (matchChannel == kCTIMER_Match_3) - { - return kStatus_Fail; - } - - /* Enable PWM mode on the channel */ - base->PWMC |= (1U << matchChannel); - - /* Clear the stop, reset and interrupt bits for this channel */ - reg = base->MCR; - reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); - - /* If call back function is valid then enable match interrupt for the channel */ - if (enableInt) - { - reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); - } - - /* Reset the counter when match on channel 3 */ - reg |= CTIMER_MCR_MR3R_MASK; - - base->MCR = reg; - - /* Calculate PWM period match value */ - period = (timerClock / pwmFreq_Hz) - 1; - - /* Calculate pulse width match value */ - if (dutyCyclePercent == 0) - { - pulsePeriod = period + 1; - } - else - { - pulsePeriod = (period * (100 - dutyCyclePercent)) / 100; - } - - /* Match on channel 3 will define the PWM period */ - base->MR[kCTIMER_Match_3] = period; - - /* This will define the PWM pulse period */ - base->MR[matchChannel] = pulsePeriod; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); - /* If call back function is valid then enable interrupt and update the call back function */ - if (enableInt) - { - EnableIRQ(s_ctimerIRQ[index]); - } - - return kStatus_Success; -} - -void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent) -{ - uint32_t pulsePeriod = 0, period; - - /* Match channel 3 defines the PWM period */ - period = base->MR[kCTIMER_Match_3]; - - /* Calculate pulse width match value */ - pulsePeriod = (period * dutyCyclePercent) / 100; - - /* For 0% dutycyle, make pulse period greater than period so the event will never occur */ - if (dutyCyclePercent == 0) - { - pulsePeriod = period + 1; - } - else - { - pulsePeriod = (period * (100 - dutyCyclePercent)) / 100; - } - - /* Update dutycycle */ - base->MR[matchChannel] = pulsePeriod; -} - -void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config) -{ - uint32_t reg; - uint32_t index = CTIMER_GetInstance(base); - - /* Set the counter operation when a match on this channel occurs */ - reg = base->MCR; - reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); - reg |= (uint32_t)((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + (matchChannel * 3))); - reg |= (uint32_t)((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + (matchChannel * 3))); - reg |= (uint32_t)((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); - base->MCR = reg; - - reg = base->EMR; - /* Set the match output operation when a match on this channel occurs */ - reg &= ~(CTIMER_EMR_EMC0_MASK << (matchChannel * 2)); - reg |= (uint32_t)config->outControl << (CTIMER_EMR_EMC0_SHIFT + (matchChannel * 2)); - - /* Set the initial state of the EM bit/output */ - reg &= ~(CTIMER_EMR_EM0_MASK << matchChannel); - reg |= (uint32_t)config->outPinInitState << matchChannel; - base->EMR = reg; - - /* Set the match value */ - base->MR[matchChannel] = config->matchValue; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); - /* If interrupt is enabled then enable interrupt and update the call back function */ - if (config->enableInterrupt) - { - EnableIRQ(s_ctimerIRQ[index]); - } -} - -void CTIMER_SetupCapture(CTIMER_Type *base, - ctimer_capture_channel_t capture, - ctimer_capture_edge_t edge, - bool enableInt) -{ - uint32_t reg = base->CCR; - uint32_t index = CTIMER_GetInstance(base); - - /* Set the capture edge */ - reg &= ~((CTIMER_CCR_CAP0RE_MASK | CTIMER_CCR_CAP0FE_MASK | CTIMER_CCR_CAP0I_MASK) << (capture * 3)); - reg |= (uint32_t)edge << (CTIMER_CCR_CAP0RE_SHIFT + (capture * 3)); - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, (kCTIMER_Capture0Flag << capture)); - /* If call back function is valid then enable capture interrupt for the channel and update the call back function */ - if (enableInt) - { - reg |= CTIMER_CCR_CAP0I_MASK << (capture * 3); - EnableIRQ(s_ctimerIRQ[index]); - } - base->CCR = reg; -} - -void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type) -{ - uint32_t index = CTIMER_GetInstance(base); - s_ctimerCallback[index] = cb_func; - ctimerCallbackType[index] = cb_type; -} - -void CTIMER_GenericIRQHandler(uint32_t index) -{ - uint32_t int_stat, i, mask; - /* Get Interrupt status flags */ - int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]); - /* Clear the status flags that were set */ - CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat); - if (ctimerCallbackType[index] == kCTIMER_SingleCallback) - { - if (s_ctimerCallback[index][0]) - { - s_ctimerCallback[index][0](int_stat); - } - } - else - { - for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) - { - mask = 0x01 << i; - /* For each status flag bit that was set call the callback function if it is valid */ - if ((int_stat & mask) && (s_ctimerCallback[index][i])) - { - s_ctimerCallback[index][i](int_stat); - } - } - } -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(CTIMER0) -void CTIMER0_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(0); -} -#endif - -#if defined(CTIMER1) -void CTIMER1_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(1); -} -#endif - -#if defined(CTIMER2) -void CTIMER2_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(2); -} -#endif - -#if defined(CTIMER3) -void CTIMER3_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(3); -} -#endif - -#if defined(CTIMER4) -void CTIMER4_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(4); -} - -#endif diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_ctimer.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_ctimer.h deleted file mode 100644 index 6d4e9ae11a3..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_ctimer.h +++ /dev/null @@ -1,434 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_CTIMER_H_ -#define _FSL_CTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup ctimer - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! @brief List of Timer capture channels */ -typedef enum _ctimer_capture_channel -{ - kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ - kCTIMER_Capture_1, /*!< Timer capture channel 1 */ - kCTIMER_Capture_2, /*!< Timer capture channel 2 */ - kCTIMER_Capture_3 /*!< Timer capture channel 3 */ -} ctimer_capture_channel_t; - -/*! @brief List of capture edge options */ -typedef enum _ctimer_capture_edge -{ - kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */ - kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */ - kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */ -} ctimer_capture_edge_t; - -/*! @brief List of Timer match registers */ -typedef enum _ctimer_match -{ - kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */ - kCTIMER_Match_1, /*!< Timer match register 1 */ - kCTIMER_Match_2, /*!< Timer match register 2 */ - kCTIMER_Match_3 /*!< Timer match register 3 */ -} ctimer_match_t; - -/*! @brief List of output control options */ -typedef enum _ctimer_match_output_control -{ - kCTIMER_Output_NoAction = 0U, /*!< No action is taken */ - kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */ - kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */ - kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */ -} ctimer_match_output_control_t; - -/*! @brief List of Timer modes */ -typedef enum _ctimer_timer_mode -{ - kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */ - kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */ - kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */ - kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */ -} ctimer_timer_mode_t; - -/*! @brief List of Timer interrupts */ -typedef enum _ctimer_interrupt_enable -{ - kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ - kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ - kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ - kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ - kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ - kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ - kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ - kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ -} ctimer_interrupt_enable_t; - -/*! @brief List of Timer flags */ -typedef enum _ctimer_status_flags -{ - kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ - kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ - kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ - kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ - kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ - kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ - kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ - kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ -} ctimer_status_flags_t; - -typedef void (*ctimer_callback_t)(uint32_t flags); - -/*! @brief Callback type when registering for a callback. When registering a callback - * an array of function pointers is passed the size could be 1 or 8, the callback - * type will tell that. - */ -typedef enum -{ - kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. - based on the status flags different channels needs to be handled differently */ - kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. - for both match/capture */ -} ctimer_callback_type_t; - -/*! - * @brief Match configuration - * - * This structure holds the configuration settings for each match register. - */ -typedef struct _ctimer_match_config -{ - uint32_t matchValue; /*!< This is stored in the match register */ - bool enableCounterReset; /*!< true: Match will reset the counter - false: Match will not reser the counter */ - bool enableCounterStop; /*!< true: Match will stop the counter - false: Match will not stop the counter */ - ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */ - bool outPinInitState; /*!< Initial value of the EM bit/output */ - bool enableInterrupt; /*!< true: Generate interrupt upon match - false: Do not generate interrupt on match */ - -} ctimer_match_config_t; - -/*! - * @brief Timer configuration structure - * - * This structure holds the configuration settings for the Timer peripheral. To initialize this - * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a - * pointer to the configuration structure instance. - * - * The configuration structure can be made constant so as to reside in flash. - */ -typedef struct _ctimer_config -{ - ctimer_timer_mode_t mode; /*!< Timer mode */ - ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer - modes that rely on this input signal to increment TC */ - uint32_t prescale; /*!< Prescale value */ -} ctimer_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application before using the driver. - * - * @param base Ctimer peripheral base address - * @param config Pointer to the user configuration structure. - */ -void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config); - -/*! - * @brief Gates the timer clock. - * - * @param base Ctimer peripheral base address - */ -void CTIMER_Deinit(CTIMER_Type *base); - -/*! - * @brief Fills in the timers configuration structure with the default settings. - * - * The default values are: - * @code - * config->mode = kCTIMER_TimerMode; - * config->input = kCTIMER_Capture_0; - * config->prescale = 0; - * @endcode - * @param config Pointer to the user configuration structure. - */ -void CTIMER_GetDefaultConfig(ctimer_config_t *config); - -/*! @}*/ - -/*! - * @name PWM setup operations - * @{ - */ - -/*! - * @brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function will assign match channel 3 to set the PWM cycle. - * - * @note When setting PWM output from multiple output pins, all should use the same PWM - * frequency - * - * @param base Ctimer peripheral base address - * @param matchChannel Match pin to be used to output the PWM signal - * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz Timer counter clock in Hz - * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt is generated - * - * @return kStatus_Success on success - * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle - */ -status_t CTIMER_SetupPwm(CTIMER_Type *base, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - bool enableInt); - -/*! - * @brief Updates the duty cycle of an active PWM signal. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match pin to be used to output the PWM signal - * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 - */ -void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent); - -/*! @}*/ - -/*! - * @brief Setup the match register. - * - * User configuration is used to setup the match value and action to be taken when a match occurs. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match register to configure - * @param config Pointer to the match configuration structure - */ -void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config); - -/*! - * @brief Setup the capture. - * - * @param base Ctimer peripheral base address - * @param capture Capture channel to configure - * @param edge Edge on the channel that will trigger a capture - * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back - * is called upon capture - */ -void CTIMER_SetupCapture(CTIMER_Type *base, - ctimer_capture_channel_t capture, - ctimer_capture_edge_t edge, - bool enableInt); - -/*! - * @brief Register callback. - * - * @param base Ctimer peripheral base address - * @param cb_func callback function - * @param cb_type callback function type, singular or multiple - */ -void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type); - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected Timer interrupts. - * - * @param base Ctimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) -{ - /* Enable match interrupts */ - base->MCR |= mask; - - /* Enable capture interrupts */ - base->CCR |= mask; -} - -/*! - * @brief Disables the selected Timer interrupts. - * - * @param base Ctimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) -{ - /* Disable match interrupts */ - base->MCR &= ~mask; - - /* Disable capture interrupts */ - base->CCR &= ~mask; -} - -/*! - * @brief Gets the enabled Timer interrupts. - * - * @param base Ctimer peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) -{ - uint32_t enabledIntrs = 0; - - /* Get all the match interrupts enabled */ - enabledIntrs = - base->MCR & (CTIMER_MCR_MR0I_SHIFT | CTIMER_MCR_MR1I_SHIFT | CTIMER_MCR_MR2I_SHIFT | CTIMER_MCR_MR3I_SHIFT); - - /* Get all the capture interrupts enabled */ - enabledIntrs |= - base->CCR & (CTIMER_CCR_CAP0I_SHIFT | CTIMER_CCR_CAP1I_SHIFT | CTIMER_CCR_CAP2I_SHIFT | CTIMER_CCR_CAP3I_SHIFT); - - return enabledIntrs; -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the Timer status flags. - * - * @param base Ctimer peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::ctimer_status_flags_t - */ -static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base) -{ - return base->IR; -} - -/*! - * @brief Clears the Timer status flags. - * - * @param base Ctimer peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::ctimer_status_flags_t - */ -static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask) -{ - base->IR = mask; -} - -/*! @}*/ - -/*! - * @name Counter Start and Stop - * @{ - */ - -/*! - * @brief Starts the Timer counter. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_StartTimer(CTIMER_Type *base) -{ - base->TCR |= CTIMER_TCR_CEN_MASK; -} - -/*! - * @brief Stops the Timer counter. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_StopTimer(CTIMER_Type *base) -{ - base->TCR &= ~CTIMER_TCR_CEN_MASK; -} - -/*! @}*/ - -/*! - * @brief Reset the counter. - * - * The timer counter and prescale counter are reset on the next positive edge of the APB clock. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_Reset(CTIMER_Type *base) -{ - base->TCR |= CTIMER_TCR_CRST_MASK; - base->TCR &= ~CTIMER_TCR_CRST_MASK; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_CTIMER_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dma.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dma.c deleted file mode 100644 index 99b9dd8a4ce..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dma.c +++ /dev/null @@ -1,421 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_dma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for DMA. - * - * @param base DMA peripheral base address. - */ -static int32_t DMA_GetInstance(DMA_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map DMA instance number to base pointer. */ -static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS; - -/*! @brief Array to map DMA instance number to IRQ number. */ -static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS; - -/*! @brief Pointers to transfer handle for each DMA channel. */ -static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS]; - -/*! @brief Static table of descriptors */ -#if defined(__ICCARM__) -#pragma data_alignment = 512 -dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0}; -#elif defined(__CC_ARM) -__attribute__((aligned(512))) dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0}; -#elif defined(__GNUC__) -__attribute__((aligned(512))) dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0}; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -static int32_t DMA_GetInstance(DMA_Type *base) -{ - int32_t instance; - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++) - { - if (s_dmaBases[instance] == base) - { - break; - } - } - assert(instance < ARRAY_SIZE(s_dmaBases)); - return instance < ARRAY_SIZE(s_dmaBases) ? instance : -1; -} - -void DMA_Init(DMA_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* enable dma clock gate */ - CLOCK_EnableClock(kCLOCK_Dma); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* set descriptor table */ - base->SRAMBASE = (uint32_t)s_dma_descriptor_table; - /* enable dma peripheral */ - base->CTRL |= DMA_CTRL_ENABLE_MASK; -} - -void DMA_Deinit(DMA_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable DMA peripheral */ - base->CTRL &= ~(DMA_CTRL_ENABLE_MASK); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger) -{ - assert((channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS) && (NULL != trigger)); - - uint32_t tmp = ( - DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | - DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | - DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK - ); - tmp = base->CHANNEL[channel].CFG & (~tmp); - tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); - base->CHANNEL[channel].CFG = tmp; -} - -/*! - * @brief Gets the remaining bytes of the current DMA descriptor transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return The number of bytes which have not been transferred yet. - */ -uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); - - /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes - * impossible to distinguish between: - * - transfer finishes (represented by value '0x3FF') - * - and remaining 1024 bytes to transfer (value 0x3FF) - * for all descriptor in chain, except the last one. - * If you decide to use this function, please use 1023 transfers as maximal value */ - - /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */ - if ( - (!(base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << (DMA_CHANNEL_INDEX(channel))))) && - (0x3FF == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) - ) - { - return 0; - } - - return base->CHANNEL[channel].XFERCFG + 1; -} - -static void DMA_SetupDescriptor( - dma_descriptor_t *desc, - uint32_t xfercfg, - void *srcEndAddr, - void *dstEndAddr, - void *nextDesc -) -{ - desc->xfercfg = xfercfg; - desc->srcEndAddr = srcEndAddr; - desc->dstEndAddr = dstEndAddr; - desc->linkToNextDesc = nextDesc; -} - -/* Verify and convert dma_xfercfg_t to XFERCFG register */ -static void DMA_SetupXferCFG( - dma_xfercfg_t *xfercfg, - uint32_t *xfercfg_addr -) -{ - assert(xfercfg != NULL); - /* check source increment */ - assert((xfercfg->srcInc == 0) || (xfercfg->srcInc == 1) || (xfercfg->srcInc == 2) || (xfercfg->srcInc == 4)); - /* check destination increment */ - assert((xfercfg->dstInc == 0) || (xfercfg->dstInc == 1) || (xfercfg->dstInc == 2) || (xfercfg->dstInc == 4)); - /* check data width */ - assert((xfercfg->byteWidth == 1) || (xfercfg->byteWidth == 2) || (xfercfg->byteWidth == 4)); - /* check transfer count */ - assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT); - - uint32_t xfer = 0, tmp; - /* set valid flag - descriptor is ready now */ - xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid ? 1 : 0); - /* set reload - allow link to next descriptor */ - xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload ? 1 : 0); - /* set swtrig flag - start transfer */ - xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig? 1 : 0); - /* set transfer count */ - xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig? 1 : 0); - /* set INTA */ - xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA ? 1 : 0); - /* set INTB */ - xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB ? 1 : 0); - /* set data width */ - tmp = xfercfg->byteWidth == 4 ? 2 : xfercfg->byteWidth - 1; - xfer |= DMA_CHANNEL_XFERCFG_WIDTH(tmp); - /* set source increment value */ - tmp = xfercfg->srcInc == 4 ? 3 : xfercfg->srcInc; - xfer |= DMA_CHANNEL_XFERCFG_SRCINC(tmp); - /* set destination increment value */ - tmp = xfercfg->dstInc == 4 ? 3 : xfercfg->dstInc; - xfer |= DMA_CHANNEL_XFERCFG_DSTINC(tmp); - /* set transfer count */ - xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1); - - /* store xferCFG */ - *xfercfg_addr = xfer; -} - -void DMA_CreateDescriptor( - dma_descriptor_t *desc, - dma_xfercfg_t *xfercfg, - void *srcAddr, - void *dstAddr, - void *nextDesc -) -{ - uint32_t xfercfg_reg = 0; - - assert((NULL != desc) && (0 == (uint32_t)desc % 16) && (NULL != xfercfg)); - assert((NULL != srcAddr) && (0 == (uint32_t)srcAddr % xfercfg->byteWidth)); - assert((NULL != dstAddr) && (0 == (uint32_t)dstAddr % xfercfg->byteWidth)); - assert((NULL == nextDesc) || (0 == (uint32_t)nextDesc % 16)); - - /* Setup channel configuration */ - DMA_SetupXferCFG(xfercfg, &xfercfg_reg); - - /* Set descriptor structure */ - DMA_SetupDescriptor(desc, xfercfg_reg, - (uint8_t*)srcAddr + (xfercfg->srcInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)), - (uint8_t*)dstAddr + (xfercfg->dstInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)), - nextDesc - ); -} - -void DMA_AbortTransfer(dma_handle_t *handle) -{ - assert(NULL != handle); - - DMA_DisableChannel(handle->base, handle->channel); - while (handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].BUSY & (1U << DMA_CHANNEL_INDEX(handle->channel))) - { } - handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].ABORT |= 1U << DMA_CHANNEL_INDEX(handle->channel); - DMA_EnableChannel(handle->base, handle->channel); -} - -void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel) -{ - int32_t dmaInstance; - assert((NULL != handle) && (channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS)); - - /* base address is invalid DMA instance */ - dmaInstance = DMA_GetInstance(base); - - memset(handle, 0, sizeof(*handle)); - handle->base = base; - handle->channel = channel; - s_DMAHandle[channel] = handle; - /* Enable NVIC interrupt */ - EnableIRQ(s_dmaIRQNumber[dmaInstance]); -} - -void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData) -{ - assert(handle != NULL); - - handle->callback = callback; - handle->userData = userData; -} - -void DMA_PrepareTransfer(dma_transfer_config_t *config, - void *srcAddr, - void *dstAddr, - uint32_t byteWidth, - uint32_t transferBytes, - dma_transfer_type_t type, - void *nextDesc) -{ - uint32_t xfer_count; - assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr)); - assert((byteWidth == 1) || (byteWidth == 2) || (byteWidth == 4)); - - /* check max */ - xfer_count = transferBytes / byteWidth; - assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0 == transferBytes % byteWidth)); - - memset(config, 0, sizeof(*config)); - switch (type) - { - case kDMA_MemoryToMemory: - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 1; - config->isPeriph = false; - break; - case kDMA_PeripheralToMemory: - /* Peripheral register - source doesn't increment */ - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 1; - config->isPeriph = true; - break; - case kDMA_MemoryToPeripheral: - /* Peripheral register - destination doesn't increment */ - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - break; - case kDMA_StaticToStatic: - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - break; - default: - return; - } - - config->dstAddr = (uint8_t*)dstAddr; - config->srcAddr = (uint8_t*)srcAddr; - config->nextDesc = (uint8_t*)nextDesc; - config->xfercfg.transferCount = xfer_count; - config->xfercfg.byteWidth = byteWidth; - config->xfercfg.intA = true; - config->xfercfg.reload = nextDesc != NULL; - config->xfercfg.valid = true; -} - -status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) -{ - assert((NULL != handle) && (NULL != config)); - - /* Previous transfer has not finished */ - if (DMA_ChannelIsActive(handle->base, handle->channel)) - { - return kStatus_DMA_Busy; - } - - /* enable/disable peripheral request */ - if (config->isPeriph) - { - DMA_EnableChannelPeriphRq(handle->base, handle->channel); - } - else - { - DMA_DisableChannelPeriphRq(handle->base, handle->channel); - } - - DMA_CreateDescriptor( - &s_dma_descriptor_table[ handle->channel ], &config->xfercfg, - config->srcAddr, config->dstAddr, config->nextDesc - ); - - return kStatus_Success; -} - -void DMA_StartTransfer(dma_handle_t *handle) -{ - assert(NULL != handle); - - /* Enable channel interrupt */ - handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].INTENSET |= 1U << DMA_CHANNEL_INDEX(handle->channel); - - /* If HW trigger is enabled - disable SW trigger */ - if (handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK) - { - s_dma_descriptor_table[ handle->channel ].xfercfg &= ~(DMA_CHANNEL_XFERCFG_SWTRIG_MASK); - } - /* Otherwise enable SW trigger */ - else - { - s_dma_descriptor_table[ handle->channel ].xfercfg |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; - } - - /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = s_dma_descriptor_table[ handle->channel ].xfercfg; - /* At this moment, the channel ACTIVE bit is set and application cannot modify - * or start another transfer using this channel. Channel ACTIVE bit is cleared by - * 'AbortTransfer' function or when the transfer finishes */ -} - -void DMA0_DriverIRQHandler(void) -{ - dma_handle_t *handle; - int32_t channel_group; - int32_t channel_index; - - /* Find channels that have completed transfer */ - for (int i = 0; i < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS; i++) - { - handle = s_DMAHandle[i]; - /* Handle is not present */ - if (NULL == handle) - { - continue; - } - channel_group = DMA_CHANNEL_GROUP(handle->channel); - channel_index = DMA_CHANNEL_INDEX(handle->channel); - /* Channel uses INTA flag */ - if (handle->base->COMMON[channel_group].INTA & (1U << channel_index)) - { - /* Clear INTA flag */ - handle->base->COMMON[channel_group].INTA = 1U << channel_index; - if (handle->callback) - { - (handle->callback)(handle, handle->userData, true, kDMA_IntA); - } - } - /* Channel uses INTB flag */ - if (handle->base->COMMON[channel_group].INTB & (1U << channel_index)) - { - /* Clear INTB flag */ - handle->base->COMMON[channel_group].INTB = 1U << channel_index; - if (handle->callback) - { - (handle->callback)(handle, handle->userData, true, kDMA_IntB); - } - } - } -} - diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dma.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dma.h deleted file mode 100644 index fbe7d007abe..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dma.h +++ /dev/null @@ -1,476 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_DMA_H_ -#define _FSL_DMA_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup dma - * @{ - */ - -/*! @file */ -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief DMA driver version */ -#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ -/*@}*/ - -#define DMA_MAX_TRANSFER_COUNT 0x400 - -/* Channel group consists of 32 channels. channel_group = (channel / 32) */ -#define DMA_CHANNEL_GROUP(channel) (((uint8_t)channel) >> 5U) -/* Channel index in channel group. channel_index = (channel % 32) */ -#define DMA_CHANNEL_INDEX(channel) (((uint8_t)channel) & 0x1F) - - -/*! @brief DMA descriptor structure */ -typedef struct _dma_descriptor { - uint32_t xfercfg; /*!< Transfer configuration */ - void *srcEndAddr; /*!< Last source address of DMA transfer */ - void *dstEndAddr; /*!< Last destination address of DMA transfer */ - void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */ -} dma_descriptor_t; - -/*! @brief DMA transfer configuration */ -typedef struct _dma_xfercfg { - bool valid; /*!< Descriptor is ready to transfer */ - bool reload; /*!< Reload channel configuration register after - current descriptor is exhausted */ - bool swtrig; /*!< Perform software trigger. Transfer if fired - when 'valid' is set */ - bool clrtrig; /*!< Clear trigger */ - bool intA; /*!< Raises IRQ when transfer is done and set IRQA status register flag */ - bool intB; /*!< Raises IRQ when transfer is done and set IRQB status register flag */ - uint8_t byteWidth; /*!< Byte width of data to transfer */ - uint8_t srcInc; /*!< Increment source address by 'srcInc' x 'byteWidth' */ - uint8_t dstInc; /*!< Increment destination address by 'dstInc' x 'byteWidth' */ - uint16_t transferCount; /*!< Number of transfers */ -} dma_xfercfg_t; - -/*! @brief DMA channel priority */ -typedef enum _dma_priority { - kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */ - kDMA_ChannelPriority1, /*!< Channel priority 1 */ - kDMA_ChannelPriority2, /*!< Channel priority 2 */ - kDMA_ChannelPriority3, /*!< Channel priority 3 */ - kDMA_ChannelPriority4, /*!< Channel priority 4 */ - kDMA_ChannelPriority5, /*!< Channel priority 5 */ - kDMA_ChannelPriority6, /*!< Channel priority 6 */ - kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */ -} dma_priority_t; - -/*! @brief DMA interrupt flags */ -typedef enum _dma_int { - kDMA_IntA, /*!< DMA interrupt flag A */ - kDMA_IntB, /*!< DMA interrupt flag B */ -} dma_irq_t; - -/*! @brief DMA trigger type*/ -typedef enum _dma_trigger_type { - kDMA_NoTrigger = 0, /*!< Trigger is disabled */ - kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */ - kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */ - kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */ - kDMA_RisingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */ -} dma_trigger_type_t; - -/*! @brief DMA trigger burst */ -typedef enum _dma_trigger_burst { - kDMA_SingleTransfer = 0, /*!< Single transfer */ - kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */ - kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */ - kDMA_EdgeBurstTransfer2 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */ - kDMA_EdgeBurstTransfer4 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */ - kDMA_EdgeBurstTransfer8 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */ - kDMA_EdgeBurstTransfer16 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */ - kDMA_EdgeBurstTransfer32 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */ - kDMA_EdgeBurstTransfer64 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */ - kDMA_EdgeBurstTransfer128 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */ - kDMA_EdgeBurstTransfer256 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */ - kDMA_EdgeBurstTransfer512 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */ - kDMA_EdgeBurstTransfer1024 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */ -} dma_trigger_burst_t; - -/*! @brief DMA burst wrapping */ -typedef enum _dma_burst_wrap { - kDMA_NoWrap = 0, /*!< Wrapping is disabled */ - kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */ - kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */ - kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */ -} dma_burst_wrap_t; - -/*! @brief DMA transfer type */ -typedef enum _dma_transfer_type -{ - kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */ - kDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory (increment only destination) */ - kDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral (increment only source)*/ - kDMA_StaticToStatic, /*!< Peripheral to static memory (do not increment source or destination) */ -} dma_transfer_type_t; - -/*! @brief DMA channel trigger */ -typedef struct _dma_channel_trigger { - dma_trigger_type_t type; - dma_trigger_burst_t burst; - dma_burst_wrap_t wrap; -} dma_channel_trigger_t; - -/*! @brief DMA transfer status */ -enum _dma_transfer_status -{ - kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the - transfer request. */ -}; - -/*! @brief DMA transfer configuration */ -typedef struct _dma_transfer_config -{ - uint8_t *srcAddr; /*!< Source data address */ - uint8_t *dstAddr; /*!< Destination data address */ - uint8_t *nextDesc; /*!< Chain custom descriptor */ - dma_xfercfg_t xfercfg; /*!< Transfer options */ - bool isPeriph; /*!< DMA transfer is driven by peripheral */ -} dma_transfer_config_t; - -/*! @brief Callback for DMA */ -struct _dma_handle; - -/*! @brief Define Callback function for DMA. */ -typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode); - -/*! @brief DMA transfer handle structure */ -typedef struct _dma_handle -{ - dma_callback callback; /*!< Callback function. Invoked when transfer - of descriptor with interrupt flag finishes */ - void *userData; /*!< Callback function parameter */ - DMA_Type *base; /*!< DMA peripheral base address */ - uint8_t channel; /*!< DMA channel number */ -} dma_handle_t; - -/******************************************************************************* - * APIs - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name DMA initialization and De-initialization - * @{ - */ - -/*! - * @brief Initializes DMA peripheral. - * - * This function enable the DMA clock, set descriptor table and - * enable DMA peripheral. - * - * @param base DMA peripheral base address. - */ -void DMA_Init(DMA_Type *base); - -/*! - * @brief Deinitializes DMA peripheral. - * - * This function gates the DMA clock. - * - * @param base DMA peripheral base address. - */ -void DMA_Deinit(DMA_Type *base); - -/* @} */ -/*! - * @name DMA Channel Operation - * @{ - */ - - /*! - * @brief Return whether DMA channel is processing transfer - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return True for active state, false otherwise. - */ -static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); - return (base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << DMA_CHANNEL_INDEX(channel))) ? true : false; -} - -/*! - * @brief Enables the interrupt source for the DMA transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); - base->COMMON[DMA_CHANNEL_GROUP(channel)].INTENSET |= 1U << DMA_CHANNEL_INDEX(channel); -} - -/*! - * @brief Disables the interrupt source for the DMA transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); - base->COMMON[DMA_CHANNEL_GROUP(channel)].INTENCLR |= 1U << DMA_CHANNEL_INDEX(channel); -} - -/*! - * @brief Enable DMA channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); - base->COMMON[DMA_CHANNEL_GROUP(channel)].ENABLESET |= 1U << DMA_CHANNEL_INDEX(channel); -} - -/*! - * @brief Disable DMA channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); - base->COMMON[DMA_CHANNEL_GROUP(channel)].ENABLECLR |= 1U << DMA_CHANNEL_INDEX(channel); -} - -/*! - * @brief Set PERIPHREQEN of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK; -} - -/*! - * @brief Get PERIPHREQEN value of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return True for enabled PeriphRq, false for disabled. - */ -static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK; -} - -/*! - * @brief Set trigger settings of DMA channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param trigger trigger configuration. - */ -void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger); - -/*! - * @brief Gets the remaining bytes of the current DMA descriptor transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return The number of bytes which have not been transferred yet. - */ -uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel); - -/*! - * @brief Set priority of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param priority Channel priority value. - */ -static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].CFG = (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority); -} - -/*! - * @brief Get priority of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return Channel priority value. - */ -static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); - return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> DMA_CHANNEL_CFG_CHPRIORITY_SHIFT); -} - -/*! - * @brief Create application specific DMA descriptor - * to be used in a chain in transfer - * - * @param desc DMA descriptor address. - * @param xfercfg Transfer configuration for DMA descriptor. - * @param srcAddr Address of last item to transmit - * @param dstAddr Address of last item to receive. - * @param nextDesc Address of next descriptor in chain. - */ -void DMA_CreateDescriptor( - dma_descriptor_t *desc, - dma_xfercfg_t *xfercfg, - void *srcAddr, - void *dstAddr, - void *nextDesc -); - -/* @} */ - -/*! - * @name DMA Transactional Operation - * @{ - */ - -/*! - * @brief Abort running transfer by handle. - * - * This function aborts DMA transfer specified by handle. - * - * @param handle DMA handle pointer. - */ -void DMA_AbortTransfer(dma_handle_t *handle); - -/*! - * @brief Creates the DMA handle. - * - * This function is called if using transaction API for DMA. This function - * initializes the internal state of DMA handle. - * - * @param handle DMA handle pointer. The DMA handle stores callback function and - * parameters. - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel); - -/*! - * @brief Installs a callback function for the DMA transfer. - * - * This callback is called in DMA IRQ handler. Use the callback to do something after - * the current major loop transfer completes. - * - * @param handle DMA handle pointer. - * @param callback DMA callback function pointer. - * @param userData Parameter for callback function. - */ -void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData); - -/*! - * @brief Prepares the DMA transfer structure. - * - * This function prepares the transfer configuration structure according to the user input. - * - * @param config The user configuration structure of type dma_transfer_t. - * @param srcAddr DMA transfer source address. - * @param dstAddr DMA transfer destination address. - * @param byteWidth DMA transfer destination address width(bytes). - * @param transferBytes DMA transfer bytes to be transferred. - * @param type DMA transfer type. - * @param nextDesc Chain custom descriptor to transfer. - * @note The data address and the data width must be consistent. For example, if the SRC - * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in - * source address error(SAE). - */ -void DMA_PrepareTransfer(dma_transfer_config_t *config, - void *srcAddr, - void *dstAddr, - uint32_t byteWidth, - uint32_t transferBytes, - dma_transfer_type_t type, - void *nextDesc); - -/*! - * @brief Submits the DMA transfer request. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * - * @param handle DMA handle pointer. - * @param config Pointer to DMA transfer configuration structure. - * @retval kStatus_DMA_Success It means submit transfer request succeed. - * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config); - -/*! - * @brief DMA start transfer. - * - * This function enables the channel request. User can call this function after submitting the transfer request - * or before submitting the transfer request. - * - * @param handle DMA handle pointer. - */ -void DMA_StartTransfer(dma_handle_t *handle); - -/*! - * @brief DMA IRQ handler for descriptor transfer complete. - * - * This function clears the channel major interrupt flag and call - * the callback function if it is not NULL. - */ -void DMA_HandleIRQ(void); - -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/* @} */ - -#endif /*_FSL_DMA_H_*/ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dmic.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dmic.c deleted file mode 100644 index bf88fd76b96..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dmic.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_dmic.h" - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* Array of DMIC peripheral base address. */ -static DMIC_Type *const s_dmicBases[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_BASE_PTRS; - -/* Array of DMIC clock name. */ -static const clock_ip_name_t s_dmicClock[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_CLOCKS; - -/* Array of DMIC IRQ number. */ -static const IRQn_Type s_dmicIRQ[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_IRQS; - -/*! @brief Callback function array for DMIC(s). */ -static dmic_callback_t s_dmicCallback[FSL_FEATURE_SOC_DMIC_COUNT]; - -/* Array of HWVAD IRQ number. */ -static const IRQn_Type s_dmicHwvadIRQ[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_HWVAD_IRQS; - -/*! @brief Callback function array for HWVAD(s). */ -static dmic_hwvad_callback_t s_dmicHwvadCallback[FSL_FEATURE_SOC_DMIC_COUNT]; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get the DMIC instance from peripheral base address. - * - * @param base DMIC peripheral base address. - * @return DMIC instance. - */ -uint32_t DMIC_GetInstance(DMIC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_dmicBases); instance++) - { - if (s_dmicBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_dmicBases)); - - return instance; -} - -void DMIC_Init(DMIC_Type *base) -{ - assert(base); - - /* Enable the clock to the register interface */ - CLOCK_EnableClock(s_dmicClock[DMIC_GetInstance(base)]); - - /* Reset the peripheral */ - RESET_PeripheralReset(kDMIC_RST_SHIFT_RSTn); - - /* Disable DMA request*/ - base->CHANNEL[0].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_DMAEN(1); - base->CHANNEL[1].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_DMAEN(1); - - /* Disable DMIC interrupt. */ - base->CHANNEL[0].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN(1); - base->CHANNEL[1].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN(1); -} - -void DMIC_DeInit(DMIC_Type *base) -{ - assert(base); - /* Disable the clock to the register interface */ - CLOCK_DisableClock(s_dmicClock[DMIC_GetInstance(base)]); -} - -void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config) -{ - base->IOCFG = config; -} - -void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode) -{ - if (mode == kDMIC_OperationModeInterrupt) - { - /* Enable DMIC interrupt. */ - base->CHANNEL[0].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN(1); - base->CHANNEL[1].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN(1); - } - if (mode == kDMIC_OperationModeDma) - { - /* enable DMA request*/ - base->CHANNEL[0].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN(1); - base->CHANNEL[1].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN(1); - } -} - -void DMIC_ConfigChannel(DMIC_Type *base, - dmic_channel_t channel, - stereo_side_t side, - dmic_channel_config_t *channel_config) -{ - base->CHANNEL[channel].DIVHFCLK = channel_config->divhfclk; - base->CHANNEL[channel].OSR = channel_config->osr; - base->CHANNEL[channel].GAINSHIFT = channel_config->gainshft; - base->CHANNEL[channel].PREAC2FSCOEF = channel_config->preac2coef; - base->CHANNEL[channel].PREAC4FSCOEF = channel_config->preac4coef; - base->CHANNEL[channel].PHY_CTRL = - DMIC_CHANNEL_PHY_CTRL_PHY_FALL(side) | DMIC_CHANNEL_PHY_CTRL_PHY_HALF(channel_config->sample_rate); - base->CHANNEL[channel].DC_CTRL = DMIC_CHANNEL_DC_CTRL_DCPOLE(channel_config->dc_cut_level) | - DMIC_CHANNEL_DC_CTRL_DCGAIN(channel_config->post_dc_gain_reduce) | - DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(channel_config->saturate16bit); -} - -void DMIC_CfgChannelDc(DMIC_Type *base, - dmic_channel_t channel, - dc_removal_t dc_cut_level, - uint32_t post_dc_gain_reduce, - bool saturate16bit) -{ - base->CHANNEL[channel].DC_CTRL = DMIC_CHANNEL_DC_CTRL_DCPOLE(dc_cut_level) | - DMIC_CHANNEL_DC_CTRL_DCGAIN(post_dc_gain_reduce) | - DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(saturate16bit); -} - -void DMIC_Use2fs(DMIC_Type *base, bool use2fs) -{ - base->USE2FS = (use2fs) ? 0x1 : 0x0; -} - -void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask) -{ - base->CHANEN = channelmask; -} - -void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn) -{ - base->CHANNEL[channel].FIFO_CTRL |= - (base->CHANNEL[channel].FIFO_CTRL & (DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK | DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)) | - DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(trig_level) | DMIC_CHANNEL_FIFO_CTRL_ENABLE(enable) | - DMIC_CHANNEL_FIFO_CTRL_RESETN(resetn); -} - -void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb) -{ - uint32_t instance; - - instance = DMIC_GetInstance(base); - NVIC_ClearPendingIRQ(s_dmicIRQ[instance]); - /* Save callback pointer */ - s_dmicCallback[instance] = cb; - EnableIRQ(s_dmicIRQ[instance]); -} - -void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb) -{ - uint32_t instance; - - instance = DMIC_GetInstance(base); - DisableIRQ(s_dmicIRQ[instance]); - s_dmicCallback[instance] = NULL; - NVIC_ClearPendingIRQ(s_dmicIRQ[instance]); -} - -void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb) -{ - uint32_t instance; - - instance = DMIC_GetInstance(base); - NVIC_ClearPendingIRQ(s_dmicHwvadIRQ[instance]); - /* Save callback pointer */ - s_dmicHwvadCallback[instance] = vadcb; - EnableIRQ(s_dmicHwvadIRQ[instance]); -} - -void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb) -{ - uint32_t instance; - - instance = DMIC_GetInstance(base); - DisableIRQ(s_dmicHwvadIRQ[instance]); - s_dmicHwvadCallback[instance] = NULL; - NVIC_ClearPendingIRQ(s_dmicHwvadIRQ[instance]); -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(DMIC0) -/*DMIC0 IRQ handler */ -void DMIC0_DriverIRQHandler(void) -{ - if (s_dmicCallback[0] != NULL) - { - s_dmicCallback[0](); - } -} -/*DMIC0 HWVAD IRQ handler */ -void HWVAD0_IRQHandler(void) -{ - if (s_dmicHwvadCallback[0] != NULL) - { - s_dmicHwvadCallback[0](); - } -} -#endif diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dmic.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dmic.h deleted file mode 100644 index a97948d7df7..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dmic.h +++ /dev/null @@ -1,439 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_DMIC_H_ -#define _FSL_DMIC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup dmic_driver - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @name DMIC version - * @{ - */ - -/*! @brief DMIC driver version 2.0.0. */ -#define FSL_DMIC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @brief DMIC different operation modes. */ -typedef enum _operation_mode -{ - kDMIC_OperationModePoll = 0U, /*!< Polling mode */ - kDMIC_OperationModeInterrupt = 1U, /*!< Interrupt mode */ - kDMIC_OperationModeDma = 2U, /*!< DMA mode */ -} operation_mode_t; - -/*! @brief DMIC left/right values. */ -typedef enum _stereo_side -{ - kDMIC_Left = 0U, /*!< Left Stereo channel */ - kDMIC_Right = 1U, /*!< Right Stereo channel */ -} stereo_side_t; - -/*! @brief DMIC Clock pre-divider values. */ -typedef enum -{ - kDMIC_PdmDiv1 = 0U, /*!< DMIC pre-divider set in divide by 1 */ - kDMIC_PdmDiv2 = 1U, /*!< DMIC pre-divider set in divide by 2 */ - kDMIC_PdmDiv3 = 2U, /*!< DMIC pre-divider set in divide by 3 */ - kDMIC_PdmDiv4 = 3U, /*!< DMIC pre-divider set in divide by 4 */ - kDMIC_PdmDiv6 = 4U, /*!< DMIC pre-divider set in divide by 6 */ - kDMIC_PdmDiv8 = 5U, /*!< DMIC pre-divider set in divide by 8 */ - kDMIC_PdmDiv12 = 6U, /*!< DMIC pre-divider set in divide by 12 */ - kDMIC_PdmDiv16 = 7U, /*!< DMIC pre-divider set in divide by 16*/ - kDMIC_PdmDiv24 = 8U, /*!< DMIC pre-divider set in divide by 24*/ - kDMIC_PdmDiv32 = 9U, /*!< DMIC pre-divider set in divide by 32 */ - kDMIC_PdmDiv48 = 10U, /*!< DMIC pre-divider set in divide by 48 */ - kDMIC_PdmDiv64 = 11U, /*!< DMIC pre-divider set in divide by 64*/ - kDMIC_PdmDiv96 = 12U, /*!< DMIC pre-divider set in divide by 96*/ - kDMIC_PdmDiv128 = 13U, /*!< DMIC pre-divider set in divide by 128 */ -} pdm_div_t; - -/*! @brief Pre-emphasis Filter coefficient value for 2FS and 4FS modes. */ -typedef enum _compensation -{ - kDMIC_CompValueZero = 0U, /*!< Compensation 0 */ - kDMIC_CompValueNegativePoint16 = 1U, /*!< Compensation -0.16 */ - kDMIC_CompValueNegativePoint15 = 2U, /*!< Compensation -0.15 */ - kDMIC_CompValueNegativePoint13 = 3U, /*!< Compensation -0.13 */ -} compensation_t; - -/*! @brief DMIC DC filter control values. */ -typedef enum _dc_removal -{ - kDMIC_DcNoRemove = 0U, /*!< Flat response no filter */ - kDMIC_DcCut155 = 1U, /*!< Cut off Frequency is 155 Hz */ - kDMIC_DcCut78 = 2U, /*!< Cut off Frequency is 78 Hz */ - kDMIC_DcCut39 = 3U, /*!< Cut off Frequency is 39 Hz */ -} dc_removal_t; - -/*! @brief DMIC IO configiration. */ -typedef enum _dmic_io -{ - kDMIC_PdmDual = 0U, /*!< Two separate pairs of PDM wires */ - kDMIC_PdmStereo = 4U, /*!< Stereo Mic */ - kDMIC_PdmBypass = 3U, /*!< Clk Bypass clocks both channels */ - kDMIC_PdmBypassClk0 = 1U, /*!< Clk Bypass clocks only channel0 */ - kDMIC_PdmBypassClk1 = 2U, /*!< Clk Bypas clocks only channel1 */ -} dmic_io_t; - -/*! @brief DMIC Channel number. */ -typedef enum _dmic_channel -{ - kDMIC_Channel0 = 0U, /*!< DMIC channel 0 */ - kDMIC_Channel1 = 1U, /*!< DMIC channel 1 */ -} dmic_channel_t; - -/*! @brief DMIC and decimator sample rates. */ -typedef enum _dmic_phy_sample_rate -{ - kDMIC_PhyFullSpeed = 0U, /*!< Decimator gets one sample per each chosen clock edge of PDM interface */ - kDMIC_PhyHalfSpeed = 1U, /*!< PDM clock to Microphone is halved, decimator receives each sample twice */ -} dmic_phy_sample_rate_t; - -/*! @brief DMIC transfer status.*/ -enum _dmic_status -{ - kStatus_DMIC_Busy = MAKE_STATUS(kStatusGroup_DMIC, 0), /*!< DMIC is busy */ - kStatus_DMIC_Idle = MAKE_STATUS(kStatusGroup_DMIC, 1), /*!< DMIC is idle */ - kStatus_DMIC_OverRunError = MAKE_STATUS(kStatusGroup_DMIC, 2), /*!< DMIC over run Error */ - kStatus_DMIC_UnderRunError = MAKE_STATUS(kStatusGroup_DMIC, 3), /*!< DMIC under run Error */ -}; - -/*! @brief DMIC Channel configuration structure. */ -typedef struct _dmic_channel_config -{ - pdm_div_t divhfclk; /*!< DMIC Clock pre-divider values */ - uint32_t osr; /*!< oversampling rate(CIC decimation rate) for PCM */ - int32_t gainshft; /*!< 4FS PCM data gain control */ - compensation_t preac2coef; /*!< Pre-emphasis Filter coefficient value for 2FS */ - compensation_t preac4coef; /*!< Pre-emphasis Filter coefficient value for 4FS */ - dc_removal_t dc_cut_level; /*!< DMIC DC filter control values. */ - uint32_t post_dc_gain_reduce; /*!< Fine gain adjustment in the form of a number of bits to downshift */ - dmic_phy_sample_rate_t sample_rate; /*!< DMIC and decimator sample rates */ - bool saturate16bit; /*!< Selects 16-bit saturation. 0 means results roll over if out range and do not saturate. - 1 means if the result overflows, it saturates at 0xFFFF for positive overflow and - 0x8000 for negative overflow.*/ -} dmic_channel_config_t; - -/*! @brief DMIC Callback function. */ -typedef void (*dmic_callback_t)(void); - -/*! @brief HWVAD Callback function. */ -typedef void (*dmic_hwvad_callback_t)(void); - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * API - ******************************************************************************/ -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @brief Get the DMIC instance from peripheral base address. - * - * @param base DMIC peripheral base address. - * @return DMIC instance. - */ -uint32_t DMIC_GetInstance(DMIC_Type *base); - -/*! - * @brief Turns DMIC Clock on - * @param base : DMIC base - * @return Nothing - */ -void DMIC_Init(DMIC_Type *base); - -/*! - * @brief Turns DMIC Clock off - * @param base : DMIC base - * @return Nothing - */ -void DMIC_DeInit(DMIC_Type *base); - -/*! - * @brief Configure DMIC io - * @param base : The base address of DMIC interface - * @param config : DMIC io configuration - * @return Nothing - */ -void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config); - -/*! - * @brief Set DMIC operating mode - * @param base : The base address of DMIC interface - * @param mode : DMIC mode - * @return Nothing - */ -void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode); - -/*! - * @brief Configure DMIC channel - * @param base : The base address of DMIC interface - * @param channel : DMIC channel - * @param side : stereo_side_t, choice of left or right - * @param channel_config : Channel configuration - * @return Nothing - */ -void DMIC_ConfigChannel(DMIC_Type *base, - dmic_channel_t channel, - stereo_side_t side, - dmic_channel_config_t *channel_config); - -/*! - * @brief Configure Clock scaling - * @param base : The base address of DMIC interface - * @param use2fs : clock scaling - * @return Nothing - */ -void DMIC_Use2fs(DMIC_Type *base, bool use2fs); - -/*! - * @brief Enable a particualr channel - * @param base : The base address of DMIC interface - * @param channelmask : Channel selection - * @return Nothing - */ -void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask); - -/*! - * @brief Configure fifo settings for DMIC channel - * @param base : The base address of DMIC interface - * @param channel : DMIC channel - * @param trig_level : FIFO trigger level - * @param enable : FIFO level - * @param resetn : FIFO reset - * @return Nothing - */ -void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn); - -/*! - * @brief Get FIFO status - * @param base : The base address of DMIC interface - * @param channel : DMIC channel - * @return FIFO status - */ -static inline uint32_t DMIC_FifoGetStatus(DMIC_Type *base, uint32_t channel) -{ - return base->CHANNEL[channel].FIFO_STATUS; -} - -/*! - * @brief Clear FIFO status - * @param base : The base address of DMIC interface - * @param channel : DMIC channel - * @param mask : Bits to be cleared - * @return FIFO status - */ -static inline void DMIC_FifoClearStatus(DMIC_Type *base, uint32_t channel, uint32_t mask) -{ - base->CHANNEL[channel].FIFO_STATUS = mask; -} - -/*! - * @brief Get FIFO data - * @param base : The base address of DMIC interface - * @param channel : DMIC channel - * @return FIFO data - */ -static inline uint32_t DMIC_FifoGetData(DMIC_Type *base, uint32_t channel) -{ - return base->CHANNEL[channel].FIFO_DATA; -} - -/*! - * @brief Enable callback. - - * This function enables the interrupt for the selected DMIC peripheral. - * The callback function is not enabled until this function is called. - * - * @param base Base address of the DMIC peripheral. - * @param cb callback Pointer to store callback function. - * @retval None. - */ -void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb); - -/*! - * @brief Disable callback. - - * This function disables the interrupt for the selected DMIC peripheral. - * - * @param base Base address of the DMIC peripheral. - * @param cb callback Pointer to store callback function.. - * @retval None. - */ -void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb); - -/** - * @} - */ - -/*! - * @name hwvad - * @{ - */ - -/*! - * @brief Sets the gain value for the noise estimator. - * - * @param base DMIC base pointer - * @param value gain value for the noise estimator. - * @retval None. - */ -static inline void DMIC_SetGainNoiseEstHwvad(DMIC_Type *base, uint32_t value) -{ - assert(NULL != base); - base->HWVADTHGN = value & 0xFu; -} - -/*! - * @brief Sets the gain value for the signal estimator. - * - * @param base DMIC base pointer - * @param value gain value for the signal estimator. - * @retval None. - */ -static inline void DMIC_SetGainSignalEstHwvad(DMIC_Type *base, uint32_t value) -{ - assert(NULL != base); - base->HWVADTHGS = value & 0xFu; -} - -/*! - * @brief Sets the hwvad filter cutoff frequency parameter. - * - * @param base DMIC base pointer - * @param value cut off frequency value. - * @retval None. - */ -static inline void DMIC_SetFilterCtrlHwvad(DMIC_Type *base, uint32_t value) -{ - assert(NULL != base); - base->HWVADHPFS = value & 0x3u; -} - -/*! - * @brief Sets the input gain of hwvad. - * - * @param base DMIC base pointer - * @param value input gain value for hwvad. - * @retval None. - */ -static inline void DMIC_SetInputGainHwvad(DMIC_Type *base, uint32_t value) -{ - assert(NULL != base); - base->HWVADGAIN = value & 0xFu; -} - -/*! - * @brief Clears hwvad internal interrupt flag. - * - * @param base DMIC base pointer - * @param st10 bit value. - * @retval None. - */ -static inline void DMIC_CtrlClrIntrHwvad(DMIC_Type *base, bool st10) -{ - assert(NULL != base); - base->HWVADST10 = (st10) ? 0x1 : 0x0; -} - -/*! - * @brief Resets hwvad filters. - * - * @param base DMIC base pointer - * @param rstt Reset bit value. - * @retval None. - */ -static inline void DMIC_FilterResetHwvad(DMIC_Type *base, bool rstt) -{ - assert(NULL != base); - base->HWVADRSTT = (rstt) ? 0x1 : 0x0; -} - -/*! - * @brief Gets the value from output of the filter z7. - * - * @param base DMIC base pointer - * @retval output of filter z7. - */ -static inline uint16_t DMIC_GetNoiseEnvlpEst(DMIC_Type *base) -{ - assert(NULL != base); - return (base->HWVADLOWZ & 0xFFFFu); -} - -/*! - * @brief Enable hwvad callback. - - * This function enables the hwvad interrupt for the selected DMIC peripheral. - * The callback function is not enabled until this function is called. - * - * @param base Base address of the DMIC peripheral. - * @param vadcb callback Pointer to store callback function. - * @retval None. - */ -void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb); - -/*! - * @brief Disable callback. - - * This function disables the hwvad interrupt for the selected DMIC peripheral. - * - * @param base Base address of the DMIC peripheral. - * @param vadcb callback Pointer to store callback function.. - * @retval None. - */ -void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb); - -/*! @} */ - -#ifdef __cplusplus -} -#endif - -/*! @}*/ - -#endif /* __FSL_DMIC_H */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dmic_dma.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dmic_dma.c deleted file mode 100644 index 8ac8ffffc47..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dmic_dma.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_dmic_dma.h" -#include "fsl_dmic.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define DMIC_HANDLE_ARRAY_SIZE 1 - -/*handle->state = kDMIC_Idle; - - if (dmicPrivateHandle->handle->callback) - { - dmicPrivateHandle->handle->callback(dmicPrivateHandle->base, dmicPrivateHandle->handle, kStatus_DMIC_Idle, - dmicPrivateHandle->handle->userData); - } -} - -status_t DMIC_TransferCreateHandleDMA(DMIC_Type *base, - dmic_dma_handle_t *handle, - dmic_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *rxDmaHandle) -{ - int32_t instance = 0; - - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } - /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - /* check DMIC instance by 'base'*/ - instance = DMIC_GetInstance(base); - assert(!(instance < 0)); - if (instance < 0) - { - return kStatus_InvalidArgument; - } - - memset(handle, 0, sizeof(*handle)); - /* assign 'base' and 'handle' */ - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - handle->callback = callback; - handle->userData = userData; - - handle->rxDmaHandle = rxDmaHandle; - - /* Set DMIC state to idle */ - handle->state = kDMIC_Idle; - /* Configure RX. */ - if (rxDmaHandle) - { - DMA_SetCallback(rxDmaHandle, DMIC_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]); - } - - return kStatus_Success; -} - -status_t DMIC_TransferReceiveDMA(DMIC_Type *base, - dmic_dma_handle_t *handle, - dmic_transfer_t *xfer, - uint32_t dmic_channel) -{ - assert(handle); - assert(handle->rxDmaHandle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - dma_transfer_config_t xferConfig; - status_t status; - - /* Check if the device is busy. If previous RX not finished.*/ - if (handle->state == kDMIC_Busy) - { - status = kStatus_DMIC_Busy; - } - else - { - handle->state = kDMIC_Busy; - handle->transferSize = xfer->dataSize; - - /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, (void *)&base->CHANNEL[dmic_channel].FIFO_DATA, xfer->data, sizeof(uint16_t), - xfer->dataSize, kDMA_PeripheralToMemory, NULL); - - /* Submit transfer. */ - DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); - - DMA_StartTransfer(handle->rxDmaHandle); - - status = kStatus_Success; - } - return status; -} - -void DMIC_TransferAbortReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle) -{ - assert(NULL != handle); - assert(NULL != handle->rxDmaHandle); - - /* Stop transfer. */ - DMA_AbortTransfer(handle->rxDmaHandle); - handle->state = kDMIC_Idle; -} - -status_t DMIC_TransferGetReceiveCountDMA(DMIC_Type *base, dmic_dma_handle_t *handle, uint32_t *count) -{ - assert(handle); - assert(handle->rxDmaHandle); - assert(count); - - if (kDMIC_Idle == handle->state) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->transferSize - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); - - return kStatus_Success; -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dmic_dma.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dmic_dma.h deleted file mode 100644 index 8d3be059b0a..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dmic_dma.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_DMIC_DMA_H_ -#define _FSL_DMIC_DMA_H_ - -#include "fsl_common.h" -#include "fsl_dma.h" - -/*! - * @addtogroup dmic_dma_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief DMIC transfer structure. */ -typedef struct _dmic_transfer -{ - uint16_t *data; /*!< The buffer of data to be transfer.*/ - size_t dataSize; /*!< The byte count to be transfer. */ -} dmic_transfer_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _dmic_dma_handle dmic_dma_handle_t; - -/*! @brief DMIC transfer callback function. */ -typedef void (*dmic_dma_transfer_callback_t)(DMIC_Type *base, - dmic_dma_handle_t *handle, - status_t status, - void *userData); - -/*! -* @brief DMIC DMA handle -*/ -struct _dmic_dma_handle -{ - DMIC_Type *base; /*!< DMIC peripheral base address. */ - dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ - dmic_dma_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< DMIC callback function parameter.*/ - size_t transferSize; /*!< Size of the data to receive. */ - volatile uint8_t state; /*!< Internal state of DMIC DMA transfer */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name DMA transactional - * @{ - */ - -/*! - * @brief Initializes the DMIC handle which is used in transactional functions. - * @param base DMIC peripheral base address. - * @param handle Pointer to dmic_dma_handle_t structure. - * @param callback Callback function. - * @param userData User data. - * @param rxDmaHandle User-requested DMA handle for RX DMA transfer. - */ -status_t DMIC_TransferCreateHandleDMA(DMIC_Type *base, - dmic_dma_handle_t *handle, - dmic_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *rxDmaHandle); - -/*! - * @brief Receives data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * @param base USART peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param xfer DMIC DMA transfer structure. See #dmic_transfer_t. - * @param dmic_channel DMIC channel - * @retval kStatus_Success - */ -status_t DMIC_TransferReceiveDMA(DMIC_Type *base, - dmic_dma_handle_t *handle, - dmic_transfer_t *xfer, - uint32_t dmic_channel); - -/*! - * @brief Aborts the received data using DMA. - * - * This function aborts the received data using DMA. - * - * @param base DMIC peripheral base address - * @param handle Pointer to dmic_dma_handle_t structure - */ -void DMIC_TransferAbortReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base DMIC peripheral base address. - * @param handle DMIC handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter count; - */ -status_t DMIC_TransferGetReceiveCountDMA(DMIC_Type *base, dmic_dma_handle_t *handle, uint32_t *count); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_DMIC_DMA_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_eeprom.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_eeprom.c deleted file mode 100644 index c8099b6dea8..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_eeprom.c +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_eeprom.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get the EEPROM instance from peripheral base address. - * - * @param base EEPROM peripheral base address. - * @return EEPROM instance. - */ -static uint32_t EEPROM_GetInstance(EEPROM_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* Array of EEPROM peripheral base address. */ -static EEPROM_Type *const s_eepromBases[] = EEPROM_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of EEPROM clock name. */ -static const clock_ip_name_t s_eepromClock[] = EEPROM_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t EEPROM_GetInstance(EEPROM_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_eepromBases); instance++) - { - if (s_eepromBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_eepromBases)); - - return instance; -} - -void EEPROM_GetDefaultConfig(eeprom_config_t *config) -{ - config->autoProgram = kEEPROM_AutoProgramWriteWord; - config->writeWaitPhase1 = 0x5U; - config->writeWaitPhase2 = 0x9U; - config->writeWaitPhase3 = 0x3U; - config->readWaitPhase1 = 0xFU; - config->readWaitPhase2 = 0x8U; - config->lockTimingParam = false; -} - -void EEPROM_Init(EEPROM_Type *base, const eeprom_config_t *config, uint32_t sourceClock_Hz) -{ - assert(config); - - uint32_t clockDiv = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the SAI clock */ - CLOCK_EnableClock(s_eepromClock[EEPROM_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Set the clock divider */ - clockDiv = sourceClock_Hz / FSL_FEATURE_EEPROM_INTERNAL_FREQ; - if ((sourceClock_Hz % FSL_FEATURE_EEPROM_INTERNAL_FREQ) > (FSL_FEATURE_EEPROM_INTERNAL_FREQ / 2U)) - { - clockDiv += 1U; - } - base->CLKDIV = clockDiv - 1U; - - /* Set the auto program feature */ - EEPROM_SetAutoProgram(base, config->autoProgram); - - /* Set time delay parameter */ - base->RWSTATE = - EEPROM_RWSTATE_RPHASE1(config->readWaitPhase1 - 1U) | EEPROM_RWSTATE_RPHASE2(config->readWaitPhase2 - 1U); - base->WSTATE = EEPROM_WSTATE_PHASE1(config->writeWaitPhase1 - 1U) | - EEPROM_WSTATE_PHASE2(config->writeWaitPhase2 - 1U) | - EEPROM_WSTATE_PHASE3(config->writeWaitPhase3 - 1U); - base->WSTATE |= EEPROM_WSTATE_LCK_PARWEP(config->lockTimingParam); - - /* Clear the remaining write operation */ - base->CMD = FSL_FEATURE_EEPROM_PROGRAM_CMD; - while ((EEPROM_GetInterruptStatus(base) & kEEPROM_ProgramFinishInterruptEnable) == 0U) - {} -} - -void EEPROM_Deinit(EEPROM_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the SAI clock */ - CLOCK_DisableClock(s_eepromClock[EEPROM_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -status_t EEPROM_WriteWord(EEPROM_Type *base, uint32_t offset, uint32_t data) -{ - uint32_t *addr = 0; - - if ((offset % 4U) || (offset > FSL_FEATURE_EEPROM_SIZE)) - { - return kStatus_InvalidArgument; - } - - /* Set auto program settings */ - if (base->AUTOPROG != kEEPROM_AutoProgramDisable) - { - EEPROM_SetAutoProgram(base, kEEPROM_AutoProgramWriteWord); - } - - EEPROM_ClearInterruptFlag(base, kEEPROM_ProgramFinishInterruptEnable); - - /* Compute the page */ - addr = (uint32_t *)(FSL_FEATURE_EEPROM_BASE_ADDRESS + offset); - *addr = data; - - /* Check if need to do program erase manually */ - if (base->AUTOPROG != kEEPROM_AutoProgramWriteWord) - { - base->CMD = FSL_FEATURE_EEPROM_PROGRAM_CMD; - } - - /* Waiting for operation finished */ - while ((EEPROM_GetInterruptStatus(base) & kEEPROM_ProgramFinishInterruptEnable) == 0U) - {} - - return kStatus_Success; -} - -status_t EEPROM_WritePage(EEPROM_Type *base, uint32_t pageNum, uint32_t *data) -{ - uint32_t i = 0; - uint32_t *addr = NULL; - - if ((pageNum > FSL_FEATURE_EEPROM_PAGE_COUNT) || (!data)) - { - return kStatus_InvalidArgument; - } - - /* Set auto program settings */ - if (base->AUTOPROG != kEEPROM_AutoProgramDisable) - { - EEPROM_SetAutoProgram(base, kEEPROM_AutoProgramLastWord); - } - - EEPROM_ClearInterruptFlag(base, kEEPROM_ProgramFinishInterruptEnable); - - addr = (uint32_t *)(FSL_FEATURE_EEPROM_BASE_ADDRESS + pageNum * (FSL_FEATURE_EEPROM_SIZE/FSL_FEATURE_EEPROM_PAGE_COUNT)); - for (i = 0; i < (FSL_FEATURE_EEPROM_SIZE/FSL_FEATURE_EEPROM_PAGE_COUNT) / 4U; i++) - { - addr[i] = data[i]; - } - - if (base->AUTOPROG == kEEPROM_AutoProgramDisable) - { - base->CMD = FSL_FEATURE_EEPROM_PROGRAM_CMD; - } - - /* Waiting for operation finished */ - while ((EEPROM_GetInterruptStatus(base) & kEEPROM_ProgramFinishInterruptEnable) == 0U) - {} - - return kStatus_Success; -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_eeprom.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_eeprom.h deleted file mode 100644 index 67f20df058c..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_eeprom.h +++ /dev/null @@ -1,258 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_EEPROM_H_ -#define _FSL_EEPROM_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup eeprom - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief EEPROM driver version 2.0.0. */ -#define FSL_EEPROM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @brief EEPROM automatic program option */ -typedef enum _eeprom_auto_program -{ - kEEPROM_AutoProgramDisable = 0x0, /*!< Disable auto program */ - kEEPROM_AutoProgramWriteWord = 0x1, /*!< Auto program triggered after 1 word is written */ - kEEPROM_AutoProgramLastWord = 0x2 /*!< Auto program triggered after last word of a page written */ -} eeprom_auto_program_t; - -/*! @brief EEPROM interrupt source */ -typedef enum _eeprom_interrupt_enable -{ - kEEPROM_ProgramFinishInterruptEnable = EEPROM_INTENSET_PROG_SET_EN_MASK, /*!< Interrupt while program finished */ -} eeprom_interrupt_enable_t; - -/*! - * @brief EEPROM region configuration structure. - */ -typedef struct _eeprom_config -{ - eeprom_auto_program_t autoProgram; /*!< Automatic program feature. */ - uint8_t readWaitPhase1; /*!< EEPROM read waiting phase 1 */ - uint8_t readWaitPhase2; /*!< EEPROM read waiting phase 2 */ - uint8_t writeWaitPhase1; /*!< EEPROM write waiting phase 1 */ - uint8_t writeWaitPhase2; /*!< EEPROM write waiting phase 2 */ - uint8_t writeWaitPhase3; /*!< EEPROM write waiting phase 3 */ - bool lockTimingParam; /*!< If lock the read and write wait phase settings */ -} eeprom_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the EEPROM with the user configuration structure. - * - * This function configures the EEPROM module with the user-defined configuration. This function also sets the - * internal clock frequency to about 155kHz according to the source clock frequency. - * - * @param base EEPROM peripheral base address. - * @param config The pointer to the configuration structure. - * @param sourceClock_Hz EEPROM source clock frequency in Hz. - */ -void EEPROM_Init(EEPROM_Type *base, const eeprom_config_t *config, uint32_t sourceClock_Hz); - -/*! - * @brief Get EEPROM default configure settings. - * - * @param config EEPROM config structure pointer. - */ -void EEPROM_GetDefaultConfig(eeprom_config_t *config); - -/*! - * @brief Deinitializes the EEPROM regions. - * - * @param base EEPROM peripheral base address. - */ -void EEPROM_Deinit(EEPROM_Type *base); - -/* @}*/ - -/*! - * @name Basic Control Operations - * @{ - */ - -/*! - * @brief Set EEPROM automatic program feature. - * - * EEPROM write always needs a program and erase cycle to write the data into EEPROM. This program and erase cycle can - * be finished automaticlly or manually. If users want to use or disable auto program feature, users can call this API. - * - * @param base EEPROM peripheral base address. - * @param autoProgram EEPROM auto program feature need to set. - */ -static inline void EEPROM_SetAutoProgram(EEPROM_Type *base, eeprom_auto_program_t autoProgram) -{ - base->AUTOPROG = autoProgram; -} - -/*! - * @brief Set EEPROM to in/out power down mode. - * - * This function make EEPROM eneter or out of power mode. Notice that, users shall not put EEPROM into power down mode - * while there is still any pending EEPROM operation. While EEPROM is wakes up from power down mode, any EEPROM - * operation has to be suspended for 100 us. - * - * @param base EEPROM peripheral base address. - * @param enable True means enter to power down mode, false means wake up. - */ -static inline void EEPROM_SetPowerDownMode(EEPROM_Type *base, bool enable) -{ - base->PWRDWN = enable; -} - -/*! - * @brief Enable EEPROM interrupt. - * - * @param base EEPROM peripheral base address. - * @param mask EEPROM interrupt enable mask. It is a logic OR of members the - * enumeration :: eeprom_interrupt_enable_t - */ -static inline void EEPROM_EnableInterrupt(EEPROM_Type *base, uint32_t mask) -{ - base->INTENSET = mask; -} - -/*! - * @brief Disable EEPROM interrupt. - * - * @param base EEPROM peripheral base address. - * @param mask EEPROM interrupt enable mask. It is a logic OR of members the - * enumeration :: eeprom_interrupt_enable_t - */ -static inline void EEPROM_DisableInterrupt(EEPROM_Type *base, uint32_t mask) -{ - base->INTENCLR = mask; -} - -/*! - * @brief Get the status of all interrupt flags for ERPROM. - * - * @param base EEPROM peripheral base address. - * @return EEPROM interrupt flag status - */ -static inline uint32_t EEPROM_GetInterruptStatus(EEPROM_Type *base) -{ - return base->INTSTAT; -} - -/*! - * @brief Get the status of enabled interrupt flags for ERPROM. - * - * @param base EEPROM peripheral base address. - * @return EEPROM enabled interrupt flag status - */ -static inline uint32_t EEPROM_GetEnabledInterruptStatus(EEPROM_Type *base) -{ - return base->INTEN; -} - -/*! - * @brief Set interrupt flags manually. - * - * This API trigger a interrupt manually, users can no need to wait for hardware trigger interrupt. Call this API will - * set the corresponding bit in INSTAT register. - * - * @param base EEPROM peripheral base address. - * @param mask EEPROM interrupt flag need to be set. It is a logic OR of members of - * enumeration:: eeprom_interrupt_enable_t - */ -static inline void EEPROM_SetInterruptFlag(EEPROM_Type *base, uint32_t mask) -{ - base->INTSTATSET = mask; -} - -/*! - * @brief Clear interrupt flags manually. - * - * This API clears interrupt flags manually. Call this API will clear the corresponding bit in INSTAT register. - * - * @param base EEPROM peripheral base address. - * @param mask EEPROM interrupt flag need to be cleared. It is a logic OR of members of - * enumeration:: eeprom_interrupt_enable_t - */ -static inline void EEPROM_ClearInterruptFlag(EEPROM_Type *base, uint32_t mask) -{ - base->INTSTATCLR = mask; -} - -/*! - * @brief Write a word data in address of EEPROM. - * - * Users can write a page or at least a word data into EEPROM address. - * - * @param base EEPROM peripheral base address. - * @param offset Offset from the begining address of EEPROM. This value shall be 4-byte aligned. - * @param data Data need be write. - */ -status_t EEPROM_WriteWord(EEPROM_Type *base, uint32_t offset, uint32_t data); - -/*! - * @brief Write a page data into EEPROM. - * - * Users can write a page or at least a word data into EEPROM address. - * - * @param base EEPROM peripheral base address. - * @param pageNum Page number to be written. - * @param data Data need be write. This array data size shall equals to the page size. - */ -status_t EEPROM_WritePage(EEPROM_Type *base, uint32_t pageNum, uint32_t *data); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_EEPROM_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_emc.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_emc.c deleted file mode 100644 index 7ed4f646571..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_emc.c +++ /dev/null @@ -1,380 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_emc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Define macros for EMC driver. */ -#define EMC_REFRESH_CLOCK_PARAM (16U) -#define EMC_SDRAM_WAIT_CYCLES (2000U) -#define EMC_DYNCTL_COLUMNBASE_OFFSET (0U) -#define EMC_DYNCTL_COLUMNBASE_MASK (0x3U) -#define EMC_DYNCTL_COLUMNPLUS_OFFSET (3U) -#define EMC_DYNCTL_COLUMNPLUS_MASK (0x18U) -#define EMC_DYNCTL_BUSWIDTH_MASK (0x80U) -#define EMC_DYNCTL_BUSADDRMAP_MASK (0x20U) -#define EMC_DYNCTL_DEVBANKS_BITS_MASK (0x1cU) -#define EMC_SDRAM_BANKCS_BA0_MASK (uint32_t)(0x2000) -#define EMC_SDRAM_BANKCS_BA1_MASK (uint32_t)(0x4000) -#define EMC_SDRAM_BANKCS_BA_MASK (EMC_SDRAM_BANKCS_BA0_MASK|EMC_SDRAM_BANKCS_BA1_MASK) -#define EMC_DIV_ROUND_UP(n, m) ((n + m -1)/m) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for EMC module. - * - * @param base EMC peripheral base address - */ -static uint32_t EMC_GetInstance(EMC_Type *base); - -/*! - * @brief Get the clock cycles of EMC clock. - * The function is used to calculate the multiple of the - * 16 EMCCLKs between the timer_Ns period. - * - * @param base EMC peripheral base address - * @param timer_Ns The timer/period in unit of nanosecond - * @param plus The plus added to the register settings to reach the calculated cycles. - * @return The calculated cycles. - */ -static uint32_t EMC_CalculateTimerCycles(EMC_Type *base, uint32_t timer_Ns, uint32_t plus); - -/*! - * @brief Get the shift value to shift the mode register content by. - * - * @param addrMap EMC address map for the dynamic memory configuration. - * It is the bit 14 ~ bit 7 of the EMC_DYNAMICCONFIG. - * @return The offset value to shift the mode register content by. - */ -static uint32_t EMC_ModeOffset(uint32_t addrMap); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Pointers to EMC clocks for each instance. */ -static const clock_ip_name_t s_EMCClock[FSL_FEATURE_SOC_EMC_COUNT] = EMC_CLOCKS; - -/*! @brief Pointers to EMC bases for each instance. */ -static EMC_Type *const s_EMCBases[] = EMC_BASE_PTRS; - -/*! @brief Define the the start address for each chip controlled by EMC. */ -static uint32_t s_EMCDYCSBases[] = EMC_DYCS_ADDRESS; -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t EMC_GetInstance(EMC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_EMCBases); instance++) - { - if (s_EMCBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_EMCBases)); - - return instance; -} - -static uint32_t EMC_CalculateTimerCycles(EMC_Type *base, uint32_t timer_Ns, uint32_t plus) -{ - uint32_t cycles; - - cycles = CLOCK_GetFreq(kCLOCK_EMC) / EMC_HZ_ONEMHZ * timer_Ns; - cycles = EMC_DIV_ROUND_UP(cycles, EMC_MILLISECS_ONESEC); /* Round up. */ - - /* Decrese according to the plus. */ - if (cycles >= plus) - { - cycles = cycles - plus; - } - else - { - cycles = 0; - } - - return cycles; -} - -static uint32_t EMC_ModeOffset(uint32_t addrMap) -{ - uint8_t offset = 0; - uint32_t columbase = addrMap & EMC_DYNCTL_COLUMNBASE_MASK; - - /* First calculate the column length. */ - if (columbase == 0x10) - { - offset = 8; - } - else - { - if (!columbase) - { - offset = 9; - } - else - { - offset = 8; - } - /* Add column length increase check. */ - if (((addrMap & EMC_DYNCTL_COLUMNPLUS_MASK) >> EMC_DYNCTL_COLUMNPLUS_OFFSET) == 1) - { - offset += 1; - } - else if (((addrMap & EMC_DYNCTL_COLUMNPLUS_MASK) >> EMC_DYNCTL_COLUMNPLUS_OFFSET) == 2) - { - offset += 2; - } - else - { - /* To avoid MISRA rule 14.10 error. */ - } - } - - /* Add Buswidth/16. */ - if (addrMap & EMC_DYNCTL_BUSWIDTH_MASK) - { - offset += 2; - } - else - { - offset += 1; - } - - /* Add bank select bit if the sdram address map mode is RBC(row-bank-column) mode. */ - if (!(addrMap & EMC_DYNCTL_BUSADDRMAP_MASK)) - { - if (!(addrMap & EMC_DYNCTL_DEVBANKS_BITS_MASK)) - { - offset += 1; - } - else - { - offset += 2; - } - } - - return offset; -} - -void EMC_Init(EMC_Type *base, emc_basic_config_t *config) -{ - /* Enable EMC clock. */ - CLOCK_EnableClock((s_EMCClock[EMC_GetInstance(base)])); - - /* Reset the EMC. */ - SYSCON->PRESETCTRL[2] |= SYSCON_PRESETCTRL_EMC_RESET_MASK; - SYSCON->PRESETCTRL[2] &= ~ SYSCON_PRESETCTRL_EMC_RESET_MASK; - - /* Set the EMC sytem configure. */ - SYSCON->EMCCLKDIV = SYSCON_EMCCLKDIV_DIV(config->emcClkDiv); - - SYSCON->EMCSYSCTRL = SYSCON_EMCSYSCTRL_EMCFBCLKINSEL(config->fbClkSrc); - - /* Set the endian mode. */ - base->CONFIG = config->endian; - /* Enable the EMC module with normal memory map mode and normal work mode. */ - base->CONTROL = EMC_CONTROL_E_MASK; -} - -void EMC_DynamicMemInit(EMC_Type *base, emc_dynamic_timing_config_t *timing, - emc_dynamic_chip_config_t *config, uint32_t totalChips) -{ - assert(config); - assert(timing); - assert(totalChips <= EMC_DYNAMIC_MEMDEV_NUM); - - uint32_t count; - uint8_t casLatency; - uint32_t addr; - uint32_t offset; - uint32_t data; - emc_dynamic_chip_config_t *dynamicConfig = config; - - /* Setting for dynamic memory controller chip independent configuration. */ - for (count = 0; (count < totalChips) && (dynamicConfig != NULL); count ++) - { - base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICCONFIG = EMC_DYNAMIC_DYNAMICCONFIG_MD(dynamicConfig->dynamicDevice) | - EMC_ADDRMAP(dynamicConfig->devAddrMap); - /* Abstract CAS latency from the sdram mode reigster setting values. */ - casLatency = (dynamicConfig->sdramModeReg & EMC_SDRAM_MODE_CL_MASK) >> EMC_SDRAM_MODE_CL_SHIFT; - base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICRASCAS = EMC_DYNAMIC_DYNAMICRASCAS_RAS(dynamicConfig->rAS_Nclk) | - EMC_DYNAMIC_DYNAMICRASCAS_CAS(casLatency); - - dynamicConfig ++; - } - - /* Configure the Dynamic Memory controller timing/latency for all chips. */ - base->DYNAMICREADCONFIG = EMC_DYNAMICREADCONFIG_RD(timing->readConfig); - base->DYNAMICRP = EMC_CalculateTimerCycles(base, timing->tRp_Ns, 1) & EMC_DYNAMICRP_TRP_MASK; - base->DYNAMICRAS = EMC_CalculateTimerCycles(base, timing->tRas_Ns, 1) & EMC_DYNAMICRAS_TRAS_MASK; - base->DYNAMICSREX = EMC_CalculateTimerCycles(base, timing->tSrex_Ns, 1) & EMC_DYNAMICSREX_TSREX_MASK; - base->DYNAMICAPR = EMC_CalculateTimerCycles(base, timing->tApr_Ns, 1) & EMC_DYNAMICAPR_TAPR_MASK; - base->DYNAMICDAL = EMC_CalculateTimerCycles(base, timing->tDal_Ns, 0) & EMC_DYNAMICDAL_TDAL_MASK; - base->DYNAMICWR = EMC_CalculateTimerCycles(base, timing->tWr_Ns, 1) & EMC_DYNAMICWR_TWR_MASK; - base->DYNAMICRC = EMC_CalculateTimerCycles(base, timing->tRc_Ns, 1) & EMC_DYNAMICRC_TRC_MASK; - base->DYNAMICRFC = EMC_CalculateTimerCycles(base, timing->tRfc_Ns, 1) &EMC_DYNAMICRFC_TRFC_MASK; - base->DYNAMICXSR = EMC_CalculateTimerCycles(base, timing->tXsr_Ns, 1) & EMC_DYNAMICXSR_TXSR_MASK; - base->DYNAMICRRD = EMC_CalculateTimerCycles(base, timing->tRrd_Ns, 1) & EMC_DYNAMICRRD_TRRD_MASK; - base->DYNAMICMRD = EMC_DYNAMICMRD_TMRD((timing->tMrd_Nclk > 0)?timing->tMrd_Nclk - 1:0); - - /* Initialize the SDRAM.*/ - for (count = 0; count < EMC_SDRAM_WAIT_CYCLES; count ++) - { - } - /* Step 2. issue nop command. */ - base->DYNAMICCONTROL = 0x00000183; - for (count = 0; count < EMC_SDRAM_WAIT_CYCLES; count ++) - { - } - /* Step 3. issue precharge all command. */ - base->DYNAMICCONTROL = 0x00000103; - - /* Step 4. issue two auto-refresh command. */ - base->DYNAMICREFRESH = 2; - for (count = 0; count < EMC_SDRAM_WAIT_CYCLES/2; count ++) - { - } - - base->DYNAMICREFRESH = EMC_CalculateTimerCycles(base, timing->refreshPeriod_Nanosec, 0)/EMC_REFRESH_CLOCK_PARAM; - - /* Step 5. issue a mode command and set the mode value. */ - base->DYNAMICCONTROL = 0x00000083; - - /* Calculate the mode settings here and to reach the 8 auto-refresh time requirement. */ - dynamicConfig = config; - for (count = 0; (count < totalChips) && (dynamicConfig != NULL); count ++) - { - /* Get the shift value first. */ - offset = EMC_ModeOffset(dynamicConfig->devAddrMap); - addr = (s_EMCDYCSBases[dynamicConfig->chipIndex] | - ((uint32_t)(dynamicConfig->sdramModeReg & ~EMC_SDRAM_BANKCS_BA_MASK ) << offset)); - /* Set the right mode setting value. */ - data = *(volatile uint32_t *)addr; - data = data; - dynamicConfig ++; - } - - if (config->dynamicDevice) - { - /* Add extended mode register if the low-power sdram is used. */ - base->DYNAMICCONTROL = 0x00000083; - /* Calculate the mode settings for extended mode register. */ - dynamicConfig = config; - for (count = 0; (count < totalChips) && (dynamicConfig != NULL); count ++) - { - /* Get the shift value first. */ - offset = EMC_ModeOffset(dynamicConfig->devAddrMap); - addr = (s_EMCDYCSBases[dynamicConfig->chipIndex] | (((uint32_t)(dynamicConfig->sdramExtModeReg & ~EMC_SDRAM_BANKCS_BA_MASK) | - EMC_SDRAM_BANKCS_BA1_MASK) << offset)); - /* Set the right mode setting value. */ - data = *(volatile uint32_t *)addr; - data = data; - dynamicConfig ++; - } - } - - /* Step 6. issue normal operation command. */ - base->DYNAMICCONTROL = 0x00000000; /* Issue NORMAL command */ - - /* The buffer shall be disabled when do the sdram initialization and - * enabled after the initialization during normal opeation. - */ - dynamicConfig = config; - for (count = 0; (count < totalChips) && (dynamicConfig != NULL); count ++) - { - base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICCONFIG |= EMC_DYNAMIC_DYNAMICCONFIG_B_MASK; - dynamicConfig ++; - } -} - -void EMC_StaticMemInit(EMC_Type *base, uint32_t *extWait_Ns, - emc_static_chip_config_t *config, uint32_t totalChips) -{ - assert(config); - - uint32_t count; - emc_static_chip_config_t *staticConfig = config; - - /* Initialize extended wait. */ - if (extWait_Ns) - { - for (count = 0; (count < totalChips) && (staticConfig != NULL); count ++) - { - assert(staticConfig->specailConfig & kEMC_AsynchronosPageEnable); - } - - base->STATICEXTENDEDWAIT = EMC_CalculateTimerCycles(base, *extWait_Ns, 1); - staticConfig ++; - } - - /* Initialize the static memory chip specific configure. */ - staticConfig = config; - for (count = 0; (count < totalChips) && (staticConfig != NULL); count ++) - { - - base->STATIC[staticConfig->chipIndex].STATICCONFIG = - (staticConfig->specailConfig | staticConfig->memWidth); - base->STATIC[staticConfig->chipIndex].STATICWAITWEN = - EMC_CalculateTimerCycles(base, staticConfig->tWaitWriteEn_Ns, 1); - base->STATIC[staticConfig->chipIndex].STATICWAITOEN = - EMC_CalculateTimerCycles(base, staticConfig->tWaitOutEn_Ns, 0); - base->STATIC[staticConfig->chipIndex].STATICWAITRD = - EMC_CalculateTimerCycles(base, staticConfig->tWaitReadNoPage_Ns, 1); - base->STATIC[staticConfig->chipIndex].STATICWAITPAGE = - EMC_CalculateTimerCycles(base, staticConfig->tWaitReadPage_Ns, 1); - base->STATIC[staticConfig->chipIndex].STATICWAITWR = - EMC_CalculateTimerCycles(base, staticConfig->tWaitWrite_Ns, 2); - base->STATIC[staticConfig->chipIndex].STATICWAITTURN = - EMC_CalculateTimerCycles(base, staticConfig->tWaitTurn_Ns, 1); - - staticConfig ++; - } -} - -void EMC_Deinit(EMC_Type *base) -{ - /* Deinit the EMC. */ - base->CONTROL &= ~EMC_CONTROL_E_MASK; - - /* Disable EMC clock. */ - CLOCK_DisableClock(s_EMCClock[EMC_GetInstance(base)]); -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_emc.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_emc.h deleted file mode 100644 index 1afce0b6b88..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_emc.h +++ /dev/null @@ -1,372 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_EMC_H_ -#define _FSL_EMC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup emc - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief EMC driver version 2.0.0. */ -#define FSL_EMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @brief Define the chip numbers for dynamic and static memory devices. */ -#define EMC_STATIC_MEMDEV_NUM (4U) -#define EMC_DYNAMIC_MEMDEV_NUM (4U) -#define EMC_ADDRMAP_SHIFT EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT -#define EMC_ADDRMAP_MASK (EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK |EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK) -#define EMC_ADDRMAP(x) (((uint32_t)(((uint32_t)(x)) << EMC_ADDRMAP_SHIFT)) & EMC_ADDRMAP_MASK) -#define EMC_HZ_ONEMHZ (1000000U) -#define EMC_MILLISECS_ONESEC (1000U) -#define EMC_SDRAM_MODE_CL_SHIFT (4U) -#define EMC_SDRAM_MODE_CL_MASK (0x70U) - -/*! - * @brief Define EMC memory width for static memory device. - */ -typedef enum _emc_static_memwidth -{ - kEMC_8BitWidth = 0x0U, /*!< 8 bit memory width. */ - kEMC_16BitWidth, /*!< 16 bit memory width. */ - kEMC_32BitWidth /*!< 32 bit memory width. */ -} emc_static_memwidth_t; - -/*! - * @brief Define EMC static configuration. - */ -typedef enum _emc_static_special_config -{ - kEMC_AsynchronosPageEnable = 0x0008U,/*!< Enable the asynchronous page mode. page length four. */ - kEMC_ActiveHighChipSelect = 0x0040U, /*!< Chip select active high. */ - kEMC_ByteLaneStateAllLow = 0x0080U, /*!< Reads/writes the respective valuie bits in BLS3:0 are low. */ - kEMC_ExtWaitEnable = 0x0100U, /*!< Extended wait enable. */ - kEMC_BufferEnable = 0x80000U /*!< Buffer enable. */ -} emc_static_special_config_t; - -/*! @brief EMC dynamic memory device. */ -typedef enum _emc_dynamic_device -{ - kEMC_Sdram = 0x0U, /*!< Dynamic memory device: SDRAM. */ - kEMC_Lpsdram, /*!< Dynamic memory device: Low-power SDRAM. */ -} emc_dynamic_device_t; - -/*! @brief EMC dynamic read strategy. */ -typedef enum _emc_dynamic_read -{ - kEMC_NoDelay = 0x0U, /*!< No delay. */ - kEMC_Cmddelay, /*!< Command delayed strategy, using EMCCLKDELAY. */ - kEMC_CmdDelayPulseOneclk, /*!< Command delayed strategy pluse one clock cycle using EMCCLKDELAY. */ - kEMC_CmddelayPulsetwoclk, /*!< Command delayed strategy pulse two clock cycle using EMCCLKDELAY. */ -} emc_dynamic_read_t; - -/*! @brief EMC endian mode. */ -typedef enum _emc_endian_mode -{ - kEMC_LittleEndian = 0x0U, /*!< Little endian mode. */ - kEMC_BigEndian, /*!< Big endian mode. */ -} emc_endian_mode_t; - -/*! @brief EMC Feedback clock input source select. */ -typedef enum _emc_fbclk_src -{ - kEMC_IntloopbackEmcclk = 0U, /*!< Use the internal loop back from EMC_CLK output. */ - kEMC_EMCFbclkInput /*!< Use the external EMC_FBCLK input. */ -} emc_fbclk_src_t; - -/*! @brief EMC dynamic timing/delay configure structure. */ -typedef struct _emc_dynamic_timing_config -{ - emc_dynamic_read_t readConfig; /* Dynamic read strategy. */ - uint32_t refreshPeriod_Nanosec; /*!< The refresh period in unit of nanosecond. */ - uint32_t tRp_Ns; /*!< Precharge command period in unit of nanosecond. */ - uint32_t tRas_Ns; /*!< Active to precharge command period in unit of nanosecond. */ - uint32_t tSrex_Ns; /*!< Self-refresh exit time in unit of nanosecond. */ - uint32_t tApr_Ns; /*!< Last data out to active command time in unit of nanosecond. */ - uint32_t tDal_Ns; /*!< Data-in to active command in unit of nanosecond. */ - uint32_t tWr_Ns; /*!< Write recovery time in unit of nanosecond. */ - uint32_t tRc_Ns; /*!< Active to active command period in unit of nanosecond. */ - uint32_t tRfc_Ns; /*!< Auto-refresh period and auto-refresh to active command period in unit of nanosecond. */ - uint32_t tXsr_Ns; /*!< Exit self-refresh to active command time in unit of nanosecond. */ - uint32_t tRrd_Ns; /*!< Active bank A to active bank B latency in unit of nanosecond. */ - uint8_t tMrd_Nclk; /*!< Load mode register to active command time in unit of EMCCLK cycles.*/ -} emc_dynamic_timing_config_t; - -/*! - * @brief EMC dynamic memory controller independent chip configuration structure. - * Please take refer to the address mapping table in the RM in EMC chapter when you - * set the "devAddrMap". Choose the right Bit 14 Bit12 ~ Bit 7 group in the table - * according to the bus width/banks/row/colum length for you device. - * Set devAddrMap with the value make up with the seven bits (bit14 bit12 ~ bit 7) - * and inset the bit 13 with 0. - * for example, if the bit 14 and bit12 ~ bit7 is 1000001 is choosen according to the - * 32bit high-performance bus width with 2 banks, 11 row lwngth, 8 column length. - * Set devAddrMap with 0x81. - */ -typedef struct _emc_dynamic_chip_config -{ - uint8_t chipIndex; /*!< Chip Index, range from 0 ~ EMC_DYNAMIC_MEMDEV_NUM - 1. */ - emc_dynamic_device_t dynamicDevice; /*!< All chips shall use the same device setting. mixed use are not supported. */ - uint8_t rAS_Nclk; /*!< Active to read/write delay tRCD. */ - uint16_t sdramModeReg; /*!< Sdram mode register setting. */ - uint16_t sdramExtModeReg; /*!< Used for low-power sdram device. The extended mode register. */ - uint8_t devAddrMap; /*!< dynamic device address mapping, choose the address mapping for your specific device. */ -} emc_dynamic_chip_config_t; - -/*! - * @brief EMC static memory controller independent chip configuration structure. - */ -typedef struct _emc_static_chip_config -{ - uint8_t chipIndex; - emc_static_memwidth_t memWidth; /*!< Memory width. */ - uint32_t specailConfig; /*!< Static configuration,a logical OR of "emc_static_special_config_t". */ - uint32_t tWaitWriteEn_Ns;/*!< The delay form chip select to write enable in unit of nanosecond. */ - uint32_t tWaitOutEn_Ns; /*!< The delay from chip selcet to output enable in unit of nanosecond. */ - uint32_t tWaitReadNoPage_Ns;/*!< In No-page mode, the delay from chip select to read access in unit of nanosecond. */ - uint32_t tWaitReadPage_Ns; /*!< In page mode, the read after the first read wait states in unit of nanosecond. */ - uint32_t tWaitWrite_Ns; /*!< The delay from chip select to write access in unit of nanosecond. */ - uint32_t tWaitTurn_Ns; /*!< The Bus turn-around time in unit of nanosecond. */ -} emc_static_chip_config_t; - -/*! - * @brief EMC module basic configuration structure. - * - * Defines the static memory controller configure structure and - * uses the EMC_Init() function to make necessary initializations. - * - */ -typedef struct _emc_basic_config -{ - emc_endian_mode_t endian; /*!< Endian mode . */ - emc_fbclk_src_t fbClkSrc; /*!< The feedback clock source. */ - uint8_t emcClkDiv; /*!< EMC_CLK = AHB_CLK / (emc_clkDiv + 1). */ -} emc_basic_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name EMC Initialize and de-initialize opeartion - * @{ - */ -/*! - * @brief Initializes the basic for EMC. - * This function ungates the EMC clock, initializes the emc system configure - * and enable the EMC module. This function must be called in the first step to initialize - * the external memory. - * - * @param base EMC peripheral base address. - * @param config The EMC basic configuration. - */ -void EMC_Init(EMC_Type *base, emc_basic_config_t *config); - -/*! - * @brief Initializes the dynamic memory controller. - * This function initializes the dynamic memory controller in external memory controller. - * This function must be called after EMC_Init and before accessing the external dynamic memory. - * - * @param base EMC peripheral base address. - * @param timing The timing and latency for dynamica memory controller setting. It shall - * be used for all dynamica memory chips, threfore the worst timing value for all - * used chips must be given. - * @param configure The EMC dynamic memory controller chip independent configuration pointer. - * This configuration pointer is actually pointer to a configration array. the array number - * depends on the "totalChips". - * @param totalChips The total dynamic memory chip numbers been used or the length of the - * "emc_dynamic_chip_config_t" type memory. - */ -void EMC_DynamicMemInit(EMC_Type *base, emc_dynamic_timing_config_t *timing, - emc_dynamic_chip_config_t *config, uint32_t totalChips); - -/*! - * @brief Initializes the static memory controller. - * This function initializes the static memory controller in external memory controller. - * This function must be called after EMC_Init and before accessing the external static memory. - * - * @param base EMC peripheral base address. - * @param extWait_Ns The extended wait timeout or the read/write transfer time. - * This is common for all static memory chips and set with NULL if not required. - * @param configure The EMC static memory controller chip independent configuration pointer. - * This configuration pointer is actually pointer to a configration array. the array number - * depends on the "totalChips". - * @param totalChips The total static memory chip numbers been used or the length of the - * "emc_static_chip_config_t" type memory. - */ -void EMC_StaticMemInit(EMC_Type *base, uint32_t *extWait_Ns, emc_static_chip_config_t *config, uint32_t totalChips); - -/*! - * @brief Deinitializes the EMC module and gates the clock. - * This function gates the EMC controller clock. As a result, the EMC - * module doesn't work after calling this function. - * - * @param base EMC peripheral base address. - */ -void EMC_Deinit(EMC_Type *base); - -/* @} */ - -/*! - * @name EMC Basic Operation - * @{ - */ - -/*! - * @brief Enables/disables the EMC module. - * - * @param base EMC peripheral base address. - * @param enable True enable EMC module, false disable. - */ -static inline void EMC_Enable(EMC_Type *base, bool enable) -{ - if (enable) - { - base->CONTROL |= EMC_CONTROL_E_MASK; - } - else - { - base->CONTROL &= ~EMC_CONTROL_E_MASK; - } -} - -/*! - * @brief Enables/disables the EMC Dynaimc memory controller. - * - * @param base EMC peripheral base address. - * @param enable True enable EMC dynamic memory controller, false disable. - */ -static inline void EMC_EnableDynamicMemControl(EMC_Type *base, bool enable) -{ - if (enable) - { - base->DYNAMICCONTROL |= (EMC_DYNAMICCONTROL_CE_MASK | EMC_DYNAMICCONTROL_CS_MASK); - } - else - { - base->DYNAMICCONTROL &= ~(EMC_DYNAMICCONTROL_CE_MASK | EMC_DYNAMICCONTROL_CS_MASK); - } -} - -/*! - * @brief Enables/disables the EMC address mirror. - * Enable the address mirror the EMC_CS1is mirrored to both EMC_CS0 - * and EMC_DYCS0 memory areas. Disable the address mirror enables - * EMC_cS0 and EMC_DYCS0 memory to be accessed. - * - * @param base EMC peripheral base address. - * @param enable True enable the address mirror, false disable the address mirror. - */ -static inline void EMC_MirrorChipAddr(EMC_Type *base, bool enable) -{ - if (enable) - { - base->CONTROL |= EMC_CONTROL_M_MASK; - } - else - { - base->CONTROL &= ~EMC_CONTROL_M_MASK; - } -} - -/*! - * @brief Enter the self-refresh mode for dynamic memory controller. - * This function provided self-refresh mode enter or exit for application. - * - * @param base EMC peripheral base address. - * @param enable True enter the self-refresh mode, false to exit self-refresh - * and enter the normal mode. - */ -static inline void EMC_EnterSelfRefreshCommand(EMC_Type *base, bool enable) -{ - if (enable) - { - base->DYNAMICCONTROL |= EMC_DYNAMICCONTROL_SR_MASK; - } - else - { - base->DYNAMICCONTROL &= ~EMC_DYNAMICCONTROL_SR_MASK; - } -} - -/*! - * @brief Get the operating mode of the EMC. - * This function can be used to get the operating mode of the EMC. - * - * @param base EMC peripheral base address. - * @return The EMC in self-refresh mode if true, else in normal mode. - */ -static inline bool EMC_IsInSelfrefreshMode(EMC_Type *base) -{ - return ((base->STATUS & EMC_STATUS_SA_MASK) ? true : false); -} - -/*! - * @brief Enter/exit the low-power mode. - * - * @param base EMC peripheral base address. - * @param enable True Enter the low-power mode, false exit low-power mode - * and return to normal mode. - */ -static inline void EMC_EnterLowPowerMode(EMC_Type *base, bool enable) -{ - if (enable) - { - base->CONTROL |= EMC_CONTROL_L_MASK; - } - else - { - base->CONTROL &= ~ EMC_CONTROL_L_MASK; - } -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_EMC_H_*/ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_enet.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_enet.c deleted file mode 100644 index 8dfada5e4f1..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_enet.c +++ /dev/null @@ -1,1810 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_enet.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief IPv4 PTP message IP version offset. */ -#define ENET_PTP1588_IPVERSION_OFFSET 0x0EU -/*! @brief IPv4 PTP message UDP protocol offset. */ -#define ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET 0x17U -/*! @brief IPv4 PTP message UDP port offset. */ -#define ENET_PTP1588_IPV4_UDP_PORT_OFFSET 0x24U -/*! @brief IPv4 PTP message UDP message type offset. */ -#define ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET 0x2AU -/*! @brief IPv4 PTP message UDP version offset. */ -#define ENET_PTP1588_IPV4_UDP_VERSION_OFFSET 0x2BU -/*! @brief IPv4 PTP message UDP clock id offset. */ -#define ENET_PTP1588_IPV4_UDP_CLKID_OFFSET 0x3EU -/*! @brief IPv4 PTP message UDP sequence id offset. */ -#define ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET 0x48U -/*! @brief IPv4 PTP message UDP control offset. */ -#define ENET_PTP1588_IPV4_UDP_CTL_OFFSET 0x4AU -/*! @brief IPv6 PTP message UDP protocol offset. */ -#define ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET 0x14U -/*! @brief IPv6 PTP message UDP port offset. */ -#define ENET_PTP1588_IPV6_UDP_PORT_OFFSET 0x38U -/*! @brief IPv6 PTP message UDP message type offset. */ -#define ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET 0x3EU -/*! @brief IPv6 PTP message UDP version offset. */ -#define ENET_PTP1588_IPV6_UDP_VERSION_OFFSET 0x3FU -/*! @brief IPv6 PTP message UDP clock id offset. */ -#define ENET_PTP1588_IPV6_UDP_CLKID_OFFSET 0x52U -/*! @brief IPv6 PTP message UDP sequence id offset. */ -#define ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET 0x5CU -/*! @brief IPv6 PTP message UDP control offset. */ -#define ENET_PTP1588_IPV6_UDP_CTL_OFFSET 0x5EU -/*! @brief PTPv2 message Ethernet packet type offset. */ -#define ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET 0x0CU -/*! @brief PTPv2 message Ethernet message type offset. */ -#define ENET_PTP1588_ETHL2_MSGTYPE_OFFSET 0x0EU -/*! @brief PTPv2 message Ethernet version type offset. */ -#define ENET_PTP1588_ETHL2_VERSION_OFFSET 0X0FU -/*! @brief PTPv2 message Ethernet clock id offset. */ -#define ENET_PTP1588_ETHL2_CLOCKID_OFFSET 0x22 -/*! @brief PTPv2 message Ethernet sequence id offset. */ -#define ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET 0x2c -/*! @brief Packet type Ethernet IEEE802.3 for PTPv2. */ -#define ENET_ETHERNETL2 0x88F7U -/*! @brief Packet type IPv4. */ -#define ENET_IPV4 0x0800U -/*! @brief Packet type IPv6. */ -#define ENET_IPV6 0x86ddU -/*! @brief Packet type VLAN. */ -#define ENET_8021QVLAN 0x8100U -/*! @brief UDP protocol type. */ -#define ENET_UDPVERSION 0x0011U -/*! @brief Packet IP version IPv4. */ -#define ENET_IPV4VERSION 0x0004U -/*! @brief Packet IP version IPv6. */ -#define ENET_IPV6VERSION 0x0006U - -/*! @brief Defines 10^9 nanosecond. */ -#define ENET_NANOSECS_ONESECOND (1000000000U) -/*! @brief Defines 10^6 microsecond.*/ -#define ENET_MICRSECS_ONESECOND (1000000U) - -/*! @brief Rx buffer LSB ignore bits. */ -#define ENET_RXBUFF_IGNORELSB_BITS (2U) -/*! @brief ENET FIFO size unit. */ -#define ENET_FIFOSIZE_UNIT (256U) -/*! @brief ENET half-dulpex default IPG. */ -#define ENET_HALFDUPLEX_DEFAULTIPG (4U) -/*! @breif ENET miminum ring length. */ -#define ENET_MIN_RINGLEN (4U) -/*! @breif ENET wakeup filter numbers. */ -#define ENET_WAKEUPFILTER_NUM (8U) -/*! @breif Requried systime timer frequency. */ -#define ENET_SYSTIME_REQUIRED_CLK_MHZ (50U) -/*! @brief Ethernet VLAN tag length. */ -#define ENET_FRAME_VLAN_TAGLEN 4U - -/*! @brief AVB TYPE */ -#define ENET_AVBTYPE 0x22F0U -#define ENET_HEAD_TYPE_OFFSET (12) -#define ENET_HEAD_AVBTYPE_OFFSET (16) - -/*! @brief Defines the macro for converting constants from host byte order to network byte order. */ -#define ENET_HTONS(n) __REV16(n) -#define ENET_HTONL(n) __REV(n) -#define ENET_NTOHS(n) __REV16(n) -#define ENET_NTOHL(n) __REV(n) - -/* Typedef for interrupt handler. */ -typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get the ENET instance from peripheral base address. - * - * @param base ENET peripheral base address. - * @return ENET instance. - */ -uint32_t ENET_GetInstance(ENET_Type *base); - -/*! - * @brief Increase the index in the ring. - * - * @param index The current index. - * @param max The size. - * @return the increased index. - */ -static uint32_t ENET_IncreaseIndex(uint32_t index, uint32_t max); - -/*! - * @brief Set ENET system configuration. - * This function reset the ethernet module and set the phy selection. - * It should be called before any other ethernet operation. - * - * @param miiMode The MII/RMII mode for interface between the phy and ethernet. - */ -static void ENET_SetSYSControl(enet_mii_mode_t miiMode); - -/*! - * @brief Set ENET DMA controller with the configuration. - * - * @param base ENET peripheral base address. - * @param config ENET Mac configuration. - */ -static void ENET_SetDMAControl(ENET_Type *base, const enet_config_t *config); - -/*! - * @brief Set ENET MAC controller with the configuration. - * - * @param base ENET peripheral base address. - * @param config ENET Mac configuration. - * @param macAddr ENET six-byte mac address. - */ -static void ENET_SetMacControl(ENET_Type *base, const enet_config_t *config, uint8_t *macAddr); -/*! - * @brief Set ENET MTL with the configuration. - * - * @param base ENET peripheral base address. - * @param config ENET Mac configuration. - */ -static void ENET_SetMTL(ENET_Type *base, const enet_config_t *config); - -/*! - * @brief Set ENET DMA transmit buffer descriptors for one channel. - * - * @param base ENET peripheral base address. - * @param bufferConfig ENET buffer configuration. - * @param intTxEnable tx interrupt enable. - * @param channel The channel number, 0 , 1. - */ -static status_t ENET_TxDescriptorsInit(ENET_Type *base, - const enet_buffer_config_t *bufferConfig, - bool intTxEnable, - uint8_t channel); - -/*! - * @brief Set ENET DMA receive buffer descriptors for one channel. - * - * @param base ENET peripheral base address. - * @param bufferConfig ENET buffer configuration. - * @param intRxEnable tx interrupt enable. - * @param channel The channel number, 0 , 1. - * @param doubleBuffEnable Two buffers are enabled. - */ -static status_t ENET_RxDescriptorsInit(ENET_Type *base, - const enet_buffer_config_t *bufferConfig, - bool intRxEnable, - uint8_t channel, - bool doubleBuffEnable); - -/*! - * @brief Set ENET get transmit ring descriptors. - * - * @param data The ENET data to be transfered. - * @param handle ENET handler. - */ -static uint8_t ENET_GetTxRingId(uint8_t *data, enet_handle_t *handle); - -#ifdef ENET_PTP1588FEATURE_REQUIRED -/*! - * @brief Sets the ENET 1588 feature. - * - * Enable the enhacement 1588 buffer descriptor mode and start - * the 1588 timer. - * - * @param base ENET peripheral base address. - * @param config The ENET configuration. - * @param refClk_Hz The reference clock for ptp 1588. - */ -static void ENET_SetPtp1588(ENET_Type *base, const enet_config_t *config, uint32_t refClk_Hz); - -/*! - * @brief Parses the ENET frame for time-stamp process of PTP 1588 frame. - * - * @param data The ENET read data for frame parse. - * @param ptpTsData The ENET PTP message and time-stamp data pointer. - * @param isFastEnabled The fast parse flag. - * - true , Fast processing, only check if this is a PTP message. - * - false, Store the PTP message data after check the PTP message. - */ -static bool ENET_Ptp1588ParseFrame(uint8_t *data, enet_ptp_time_data_t *ptpTsData, bool isFastEnabled); - -/*! - * @brief Updates the new PTP 1588 time-stamp to the time-stamp buffer ring. - * - * @param ptpTsDataRing The PTP message and time-stamp data ring pointer. - * @param ptpTimeData The new PTP 1588 time-stamp data pointer. - */ -static status_t ENET_Ptp1588UpdateTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimeData); - -/*! - * @brief Search up the right PTP 1588 time-stamp from the time-stamp buffer ring. - * - * @param ptpTsDataRing The PTP message and time-stamp data ring pointer. - * @param ptpTimeData The find out right PTP 1588 time-stamp data pointer with the specific PTP message. - */ -static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimedata); - -/*! - * @brief Store the receive time-stamp for event PTP frame in the time-stamp buffer ring. - * - * @param base ENET peripheral base address. - * @param handle ENET handler. - * @param rxDesc The ENET receive descriptor pointer. - * @param channel The rx channel. - * @param ptpTimeData The PTP 1588 time-stamp data pointer. - */ -static status_t ENET_StoreRxFrameTime(ENET_Type *base, - enet_handle_t *handle, - enet_rx_bd_struct_t *rxDesc, - uint8_t channel, - enet_ptp_time_data_t *ptpTimeData); -#endif /* ENET_PTP1588FEATURE_REQUIRED */ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Pointers to enet handles for each instance. */ -static enet_handle_t *s_ENETHandle[FSL_FEATURE_SOC_LPC_ENET_COUNT] = {NULL}; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to enet clocks for each instance. */ -const clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_LPC_ENET_COUNT] = ETH_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Pointers to enet bases for each instance. */ -static ENET_Type *const s_enetBases[] = ENET_BASE_PTRS; - -/*! @brief Pointers to enet IRQ number for each instance. */ -static const IRQn_Type s_enetIrqId[] = ENET_IRQS; - -/* ENET ISR for transactional APIs. */ -static enet_isr_t s_enetIsr; -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t ENET_IncreaseIndex(uint32_t index, uint32_t max) -{ - /* Increase the index. */ - index++; - if (index >= max) - { - index = 0; - } - return index; -} - -static void ENET_SetSYSControl(enet_mii_mode_t miiMode) -{ - /* Reset first. */ - SYSCON->PRESETCTRL[2] = SYSCON_PRESETCTRL_ETH_RST_MASK; - SYSCON->PRESETCTRL[2] &= ~SYSCON_PRESETCTRL_ETH_RST_MASK; - /* Set MII/RMII before the peripheral ethernet dma reset. */ - SYSCON->ETHPHYSEL = (SYSCON->ETHPHYSEL & ~SYSCON_ETHPHYSEL_PHY_SEL_MASK) | SYSCON_ETHPHYSEL_PHY_SEL(miiMode); -} - -static void ENET_SetDMAControl(ENET_Type *base, const enet_config_t *config) -{ - assert(config); - - uint8_t index; - uint32_t reg; - uint32_t burstLen; - - /* Reset first and wait for the complete - * The reset bit will automatically be cleared after complete. */ - base->DMA_MODE |= ENET_DMA_MODE_SWR_MASK; - while (base->DMA_MODE & ENET_DMA_MODE_SWR_MASK) - { - } - - /* Set the burst length. */ - for (index = 0; index < ENET_RING_NUM_MAX; index++) - { - burstLen = kENET_BurstLen1; - if (config->multiqueueCfg) - { - burstLen = config->multiqueueCfg->burstLen; - } - base->DMA_CH[index].DMA_CHX_CTRL = burstLen & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK; - - reg = base->DMA_CH[index].DMA_CHX_TX_CTRL & ~ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK; - base->DMA_CH[index].DMA_CHX_TX_CTRL = reg | ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(burstLen & 0x3F); - - reg = base->DMA_CH[index].DMA_CHX_RX_CTRL & ~ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK; - base->DMA_CH[index].DMA_CHX_RX_CTRL = reg | ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(burstLen & 0x3F); - } -} - -static void ENET_SetMTL(ENET_Type *base, const enet_config_t *config) -{ - assert(config); - - uint32_t txqOpreg = 0; - uint32_t rxqOpReg = 0; - enet_multiqueue_config_t *multiqCfg = config->multiqueueCfg; - uint8_t index; - - /* Set transmit operation mode. */ - if (config->specialControl & kENET_StoreAndForward) - { - txqOpreg = ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK; - rxqOpReg = ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK; - } - txqOpreg |= ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK | - ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(ENET_MTL_TXFIFOSIZE / ENET_FIFOSIZE_UNIT - 1); - base->MTL_QUEUE[0].MTL_TXQX_OP_MODE = txqOpreg | ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(2); - base->MTL_QUEUE[1].MTL_TXQX_OP_MODE = txqOpreg; - - /* Set receive operation mode. */ - rxqOpReg |= ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK | - ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(ENET_MTL_RXFIFOSIZE / ENET_FIFOSIZE_UNIT - 1); - base->MTL_QUEUE[0].MTL_RXQX_OP_MODE = rxqOpReg; - - /* Set the schedule/arbitration(set for multiple queues). */ - if (multiqCfg) - { - base->MTL_OP_MODE = ENET_MTL_OP_MODE_SCHALG(multiqCfg->mtltxSche) | ENET_MTL_OP_MODE_RAA(multiqCfg->mtlrxSche); - /* Set the rx queue mapping to dma channel. */ - base->MTL_RXQ_DMA_MAP = multiqCfg->mtlrxQuemap; - /* Set the tx/rx queue operation mode for multi-queue. */ - base->MTL_QUEUE[1].MTL_TXQX_OP_MODE |= ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(2); - base->MTL_QUEUE[1].MTL_RXQX_OP_MODE = rxqOpReg; - - /* Set the tx/rx queue weight. */ - for (index = 0; index < ENET_RING_NUM_MAX; index++) - { - base->MTL_QUEUE[index].MTL_TXQX_QNTM_WGHT = multiqCfg->txqueweight[index]; - base->MTL_QUEUE[index].MTL_RXQX_CTRL = ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(multiqCfg->rxqueweight[index]); - } - } -} - -static void ENET_SetMacControl(ENET_Type *base, const enet_config_t *config, uint8_t *macAddr) -{ - assert(config); - - uint32_t reg = 0; - - /* Set Macaddr */ - /* The dma channel 0 is set as to which the rx packet - * whose DA matches the MAC address content is routed. */ - if (macAddr) - { - ENET_SetMacAddr(base, macAddr); - } - - /* Set the receive filter. */ - reg = ENET_MAC_FRAME_FILTER_PR(!!(config->specialControl & kENET_PromiscuousEnable)) | - ENET_MAC_FRAME_FILTER_DBF(!!(config->specialControl & kENET_BroadCastRxDisable)) | - ENET_MAC_FRAME_FILTER_PM(!!(config->specialControl & kENET_MulticastAllEnable)); - base->MAC_FRAME_FILTER = reg; - /* Flow control. */ - if (config->specialControl & kENET_FlowControlEnable) - { - base->MAC_RX_FLOW_CTRL = ENET_MAC_RX_FLOW_CTRL_RFE_MASK | ENET_MAC_RX_FLOW_CTRL_UP_MASK; - base->MAC_TX_FLOW_CTRL_Q[0] = ENET_MAC_TX_FLOW_CTRL_Q_PT(config->pauseDuration); - base->MAC_TX_FLOW_CTRL_Q[1] = ENET_MAC_TX_FLOW_CTRL_Q_PT(config->pauseDuration); - } - - /* Set the 1us ticket. */ - reg = CLOCK_GetFreq(kCLOCK_CoreSysClk) / ENET_MICRSECS_ONESECOND - 1; - base->MAC_1US_TIC_COUNTR = ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(reg); - - /* Set the speed and duplex. */ - reg = ENET_MAC_CONFIG_ECRSFD_MASK | ENET_MAC_CONFIG_PS_MASK | ENET_MAC_CONFIG_DM(config->miiDuplex) | - ENET_MAC_CONFIG_FES(config->miiSpeed) | - ENET_MAC_CONFIG_S2KP(!!(config->specialControl & kENET_8023AS2KPacket)); - if (config->miiDuplex == kENET_MiiHalfDuplex) - { - reg |= ENET_MAC_CONFIG_IPG(ENET_HALFDUPLEX_DEFAULTIPG); - } - base->MAC_CONFIG = reg; - - /* Enable channel. */ - base->MAC_RXQ_CTRL[0] = ENET_MAC_RXQ_CTRL_RXQ0EN(1) | ENET_MAC_RXQ_CTRL_RXQ1EN(1); -} - -static status_t ENET_TxDescriptorsInit(ENET_Type *base, - const enet_buffer_config_t *bufferConfig, - bool intTxEnable, - uint8_t channel) -{ - uint16_t j; - enet_tx_bd_struct_t *txbdPtr; - uint32_t control = intTxEnable ? ENET_TXDESCRIP_RD_IOC_MASK : 0; - const enet_buffer_config_t *buffCfg = bufferConfig; - - if (!buffCfg) - { - return kStatus_InvalidArgument; - } - - /* Check the ring length. */ - if (buffCfg->txRingLen < ENET_MIN_RINGLEN) - { - return kStatus_InvalidArgument; - } - /* Set the tx descriptor start/tail pointer, shall be word aligned. */ - base->DMA_CH[channel].DMA_CHX_TXDESC_LIST_ADDR = - (uint32_t)buffCfg->txDescStartAddrAlign & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK; - base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR = - (uint32_t)buffCfg->txDescTailAddrAlign & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK; - /* Set the tx ring length. */ - base->DMA_CH[channel].DMA_CHX_TXDESC_RING_LENGTH = - (uint16_t)(buffCfg->txRingLen - 1) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK; - - /* Init the txbdPtr to the transmit descriptor start address. */ - txbdPtr = (enet_tx_bd_struct_t *)(buffCfg->txDescStartAddrAlign); - for (j = 0; j < buffCfg->txRingLen; j++) - { - txbdPtr->buff1Addr = 0; - txbdPtr->buff2Addr = 0; - txbdPtr->buffLen = control; - txbdPtr->controlStat = 0; - txbdPtr++; - } - - return kStatus_Success; -} - -static status_t ENET_RxDescriptorsInit( - ENET_Type *base, const enet_buffer_config_t *bufferConfig, bool intRxEnable, uint8_t channel, bool doubleBuffEnable) -{ - uint16_t j; - uint32_t reg; - enet_rx_bd_struct_t *rxbdPtr; - uint16_t index; - const enet_buffer_config_t *buffCfg = bufferConfig; - uint32_t control = ENET_RXDESCRIP_WR_OWN_MASK | ENET_RXDESCRIP_RD_BUFF1VALID_MASK; - - if (!buffCfg) - { - return kStatus_InvalidArgument; - } - - if (intRxEnable) - { - control |= ENET_RXDESCRIP_RD_IOC_MASK; - } - - if (doubleBuffEnable) - { - control |= ENET_RXDESCRIP_RD_BUFF2VALID_MASK; - } - - /* Check the ring length. */ - if (buffCfg->rxRingLen < ENET_MIN_RINGLEN) - { - return kStatus_InvalidArgument; - } - - /* Set the rx descriptor start/tail pointer, shall be word aligned. */ - base->DMA_CH[channel].DMA_CHX_RXDESC_LIST_ADDR = - (uint32_t)buffCfg->rxDescStartAddrAlign & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK; - base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = - (uint32_t)buffCfg->rxDescTailAddrAlign & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK; - base->DMA_CH[channel].DMA_CHX_RXDESC_RING_LENGTH = - (uint16_t)(buffCfg->rxRingLen - 1) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK; - reg = base->DMA_CH[channel].DMA_CHX_RX_CTRL & ~ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK; - reg |= ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(buffCfg->rxBuffSizeAlign >> ENET_RXBUFF_IGNORELSB_BITS); - base->DMA_CH[channel].DMA_CHX_RX_CTRL = reg; - - /* Init the rxbdPtr to the receive descriptor start address. */ - rxbdPtr = (enet_rx_bd_struct_t *)(buffCfg->rxDescStartAddrAlign); - - for (j = 0; j < buffCfg->rxRingLen; j++) - { - if (doubleBuffEnable) - { - index = 2 * j; - } - else - { - index = j; - } - rxbdPtr->buff1Addr = *(buffCfg->rxBufferStartAddr + index); - /* The second buffer is set with 0 because it is not required for normal case. */ - if (doubleBuffEnable) - { - rxbdPtr->buff2Addr = *(buffCfg->rxBufferStartAddr + index + 1); - } - else - { - rxbdPtr->buff2Addr = 0; - } - - /* Set the valid and DMA own flag.*/ - rxbdPtr->control = control; - rxbdPtr++; - } - - return kStatus_Success; -} - -static uint8_t ENET_GetTxRingId(uint8_t *data, enet_handle_t *handle) -{ - /* Defuault use the queue/ring 0. */ - uint8_t ringId = 0; - - if (handle->multiQueEnable) - { - /* Parse the frame and choose the queue id for different avb frames - * AVB Class frame in queue 1. - * non-AVB frame in queue 0. - */ - if ((*(uint16_t *)(data + ENET_HEAD_TYPE_OFFSET) == ENET_HTONS(ENET_8021QVLAN)) && - ((*(uint16_t *)(data + ENET_HEAD_AVBTYPE_OFFSET)) == ENET_HTONS(ENET_AVBTYPE))) - { - /* AVBTP stream data frame. */ - ringId = 1; - } - } - - return ringId; -} - -#ifdef ENET_PTP1588FEATURE_REQUIRED -static void ENET_SetPtp1588(ENET_Type *base, const enet_config_t *config, uint32_t refClk_Hz) -{ - assert(config); - assert(config->ptpConfig); - assert(refClk_Hz); - - uint32_t control; - enet_ptp_config_t *ptpConfig = config->ptpConfig; - - /* Clear the timestamp interrupt first. */ - base->MAC_INTR_EN &= ~ENET_MAC_INTR_EN_TSIE_MASK; - - if (ptpConfig->fineUpdateEnable) - { - base->MAC_TIMESTAMP_CTRL |= ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK; - /* Set the initial added value for the fine update. */ - control = 100000000U / (refClk_Hz / ENET_MICRSECS_ONESECOND / ENET_SYSTIME_REQUIRED_CLK_MHZ); - base->MAC_SYS_TIMESTMP_ADDEND = control; - base->MAC_TIMESTAMP_CTRL |= ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK; - while (base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK) - { - } - } - - /* Enable the IEEE 1588 timestamping and snapshot for event message. */ - control = ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK | ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK | - ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK | ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK | - ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK | ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK | - ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(ptpConfig->tsRollover); - - if (ptpConfig->ptp1588V2Enable) - { - control |= ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK | ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK; - } - - /* Initialize the sub-second increment register. */ - if (ptpConfig->tsRollover) - { - base->MAC_SUB_SCND_INCR = ENET_MAC_SUB_SCND_INCR_SSINC(ENET_NANOSECS_ONESECOND / refClk_Hz); - base->MAC_SYS_TIME_NSCND_UPD = 0; - } - else - { - /* round up. */ - uint32_t data = ENET_MAC_SYS_TIME_NSCND_TSSS_MASK / refClk_Hz; - base->MAC_SUB_SCND_INCR = ENET_MAC_SUB_SCND_INCR_SSINC(data); - base->MAC_SYS_TIME_NSCND_UPD = 0; - } - /* Set the second.*/ - base->MAC_SYS_TIME_SCND_UPD = 0; - base->MAC_SYS_TIME_HWORD_SCND = 0; - - /* Initialize the system timer. */ - base->MAC_TIMESTAMP_CTRL = control | ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK; -} - -static bool ENET_Ptp1588ParseFrame(uint8_t *data, enet_ptp_time_data_t *ptpTsData, bool isFastEnabled) -{ - assert(data); - if (!isFastEnabled) - { - assert(ptpTsData); - } - - bool isPtpMsg = false; - uint8_t *buffer = data; - uint16_t ptpType; - - /* Check for VLAN frame. */ - if (*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET) == ENET_HTONS(ENET_8021QVLAN)) - { - buffer += ENET_FRAME_VLAN_TAGLEN; - } - - ptpType = *(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET); - switch (ENET_HTONS(ptpType)) - { /* Ethernet layer 2. */ - case ENET_ETHERNETL2: - if (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET) <= kENET_PtpEventMsgType) - { - isPtpMsg = true; - if (!isFastEnabled) - { - /* It's a ptpv2 message and store the ptp header information. */ - ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_VERSION_OFFSET)) & 0x0F; - ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET)) & 0x0F; - ptpTsData->sequenceId = ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET)); - memcpy((void *)&ptpTsData->sourcePortId[0], (void *)(buffer + ENET_PTP1588_ETHL2_CLOCKID_OFFSET), - kENET_PtpSrcPortIdLen); - } - } - break; - /* IPV4. */ - case ENET_IPV4: - if ((*(uint8_t *)(buffer + ENET_PTP1588_IPVERSION_OFFSET) >> 4) == ENET_IPV4VERSION) - { - if (((*(uint16_t *)(buffer + ENET_PTP1588_IPV4_UDP_PORT_OFFSET)) == ENET_HTONS(kENET_PtpEventPort)) && - (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET) == ENET_UDPVERSION)) - { - /* Set the PTP message flag. */ - isPtpMsg = true; - if (!isFastEnabled) - { - /* It's a IPV4 ptp message and store the ptp header information. */ - ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_VERSION_OFFSET)) & 0x0F; - ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET)) & 0x0F; - ptpTsData->sequenceId = - ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET)); - memcpy((void *)&ptpTsData->sourcePortId[0], - (void *)(buffer + ENET_PTP1588_IPV4_UDP_CLKID_OFFSET), kENET_PtpSrcPortIdLen); - } - } - } - break; - /* IPV6. */ - case ENET_IPV6: - if ((*(uint8_t *)(buffer + ENET_PTP1588_IPVERSION_OFFSET) >> 4) == ENET_IPV6VERSION) - { - if (((*(uint16_t *)(buffer + ENET_PTP1588_IPV6_UDP_PORT_OFFSET)) == ENET_HTONS(kENET_PtpEventPort)) && - (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET) == ENET_UDPVERSION)) - { - /* Set the PTP message flag. */ - isPtpMsg = true; - if (!isFastEnabled) - { - /* It's a IPV6 ptp message and store the ptp header information. */ - ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_VERSION_OFFSET)) & 0x0F; - ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET)) & 0x0F; - ptpTsData->sequenceId = - ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET)); - memcpy((void *)&ptpTsData->sourcePortId[0], - (void *)(buffer + ENET_PTP1588_IPV6_UDP_CLKID_OFFSET), kENET_PtpSrcPortIdLen); - } - } - } - break; - default: - break; - } - return isPtpMsg; -} - -static status_t ENET_Ptp1588UpdateTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimeData) -{ - assert(ptpTsDataRing); - assert(ptpTsDataRing->ptpTsData); - assert(ptpTimeData); - - uint16_t usedBuffer = 0; - - /* Check if the buffers ring is full. */ - if (ptpTsDataRing->end >= ptpTsDataRing->front) - { - usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front; - } - else - { - usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end); - } - - if (usedBuffer == ptpTsDataRing->size) - { - return kStatus_ENET_PtpTsRingFull; - } - - /* Copy the new data into the buffer. */ - memcpy((ptpTsDataRing->ptpTsData + ptpTsDataRing->end), ptpTimeData, sizeof(enet_ptp_time_data_t)); - - /* Increase the buffer pointer to the next empty one. */ - ptpTsDataRing->end = (ptpTsDataRing->end + 1) % ptpTsDataRing->size; - - return kStatus_Success; -} - -static status_t ENET_StoreRxFrameTime(ENET_Type *base, - enet_handle_t *handle, - enet_rx_bd_struct_t *rxDesc, - uint8_t channel, - enet_ptp_time_data_t *ptpTimeData) -{ - assert(ptpTimeData); - - uint32_t nanosecond; - uint32_t nanoOverSize = ENET_NANOSECS_ONESECOND; /* Default use the digital rollover. */ - - /* Get transmit time stamp second. */ - nanosecond = rxDesc->reserved | rxDesc->buff1Addr; - if (!(base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)) - { - /* Binary rollover. */ - nanoOverSize = ENET_MAC_SYS_TIME_NSCND_TSSS_MASK; - } - ptpTimeData->timeStamp.second = nanosecond / nanoOverSize; - ptpTimeData->timeStamp.nanosecond = nanosecond % nanoOverSize; - - /* Store the timestamp to the receive time stamp ring. */ - /* Check if the buffers ring is full. */ - return ENET_Ptp1588UpdateTimeRing(&handle->rxBdRing[channel].rxPtpTsDataRing, ptpTimeData); -} - -static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimedata) -{ - assert(ptpTsDataRing); - assert(ptpTsDataRing->ptpTsData); - assert(ptpTimedata); - - uint32_t index; - uint32_t size; - uint16_t usedBuffer = 0; - - /* Check the PTP 1588 timestamp ring. */ - if (ptpTsDataRing->front == ptpTsDataRing->end) - { - return kStatus_ENET_PtpTsRingEmpty; - } - - /* Search the element in the ring buffer */ - index = ptpTsDataRing->front; - size = ptpTsDataRing->size; - while (index != ptpTsDataRing->end) - { - if (((ptpTsDataRing->ptpTsData + index)->sequenceId == ptpTimedata->sequenceId) && - (!memcmp(((void *)&(ptpTsDataRing->ptpTsData + index)->sourcePortId[0]), - (void *)&ptpTimedata->sourcePortId[0], kENET_PtpSrcPortIdLen)) && - ((ptpTsDataRing->ptpTsData + index)->version == ptpTimedata->version) && - ((ptpTsDataRing->ptpTsData + index)->messageType == ptpTimedata->messageType)) - { - break; - } - - /* Increase the ptp ring index. */ - index = (index + 1) % size; - } - - if (index == ptpTsDataRing->end) - { - /* Check if buffers is full. */ - if (ptpTsDataRing->end >= ptpTsDataRing->front) - { - usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front; - } - else - { - usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end); - } - - if (usedBuffer == ptpTsDataRing->size) - { /* Drop one in the front. */ - ptpTsDataRing->front = (ptpTsDataRing->front + 1) % size; - } - return kStatus_ENET_PtpTsRingFull; - } - - /* Get the right timestamp of the required ptp messag. */ - ptpTimedata->timeStamp.second = (ptpTsDataRing->ptpTsData + index)->timeStamp.second; - ptpTimedata->timeStamp.nanosecond = (ptpTsDataRing->ptpTsData + index)->timeStamp.nanosecond; - - /* Increase the index. */ - ptpTsDataRing->front = (ptpTsDataRing->front + 1) % size; - - return kStatus_Success; -} -#endif /* ENET_PTP1588FEATURE_REQUIRED */ - -uint32_t ENET_GetInstance(ENET_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < FSL_FEATURE_SOC_LPC_ENET_COUNT; instance++) - { - if (s_enetBases[instance] == base) - { - break; - } - } - - assert(instance < FSL_FEATURE_SOC_LPC_ENET_COUNT); - - return instance; -} - -void ENET_GetDefaultConfig(enet_config_t *config) -{ - /* Checks input parameter. */ - assert(config); - - /* Sets MII mode, full duplex, 100Mbps for MAC and PHY data interface. */ - config->miiMode = kENET_RmiiMode; - config->miiSpeed = kENET_MiiSpeed100M; - config->miiDuplex = kENET_MiiFullDuplex; - - /* Sets default configuration for other options. */ - config->specialControl = false; - config->multiqueueCfg = NULL; - config->pauseDuration = 0; - -#ifdef ENET_PTP1588FEATURE_REQUIRED - config->ptpConfig = NULL; -#endif /* ENET_PTP1588FEATURE_REQUIRED */ -} - -void ENET_Init(ENET_Type *base, const enet_config_t *config, uint8_t *macAddr, uint32_t refclkSrc_Hz) -{ - assert(config); - - uint32_t instance = ENET_GetInstance(base); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate ENET clock. */ - CLOCK_EnableClock(s_enetClock[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* System configure fistly. */ - ENET_SetSYSControl(config->miiMode); - - /* Initializes the ENET DMA with basic function. */ - ENET_SetDMAControl(base, config); - - /* Initializes the ENET MTL with basic function. */ - ENET_SetMTL(base, config); - - /* Initializes the ENET MAC with basic function. */ - ENET_SetMacControl(base, config, macAddr); - -#ifdef ENET_PTP1588FEATURE_REQUIRED - ENET_SetPtp1588(base, config, refclkSrc_Hz); -#endif /* ENET_PTP1588FEATURE_REQUIRED */ -} - -void ENET_Deinit(ENET_Type *base) -{ - /* Reset first and wait for the complete - * The reset bit will automatically be cleared after complete. */ - base->DMA_MODE |= ENET_DMA_MODE_SWR_MASK; - while (base->DMA_MODE & ENET_DMA_MODE_SWR_MASK) - { - } - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disables the clock source. */ - CLOCK_DisableClock(s_enetClock[ENET_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -status_t ENET_DescriptorInit(ENET_Type *base, enet_config_t *config, enet_buffer_config_t *bufferConfig) -{ - assert(config); - assert(bufferConfig); - - bool intTxEnable; - bool intRxEnable; - bool doubleBuffEnable = (config->specialControl & kENET_DescDoubleBuffer) ? true : false; - uint8_t ringNum = config->multiqueueCfg == NULL ? 1 : 2; - uint8_t channel; - - for (channel = 0; channel < ringNum; channel++) - { - intRxEnable = (base->DMA_CH[channel].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK) ? true : false; - - if (ENET_TxDescriptorsInit(base, bufferConfig, intTxEnable, channel) != kStatus_Success) - { - return kStatus_Fail; - } - intTxEnable = (base->DMA_CH[channel].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK) ? true : false; - - if (ENET_RxDescriptorsInit(base, bufferConfig, intRxEnable, channel, doubleBuffEnable) != kStatus_Success) - { - return kStatus_Fail; - } - - bufferConfig++; - if (!bufferConfig) - { - return kStatus_InvalidArgument; - } - } - return kStatus_Success; -} - -void ENET_StartRxTx(ENET_Type *base, uint8_t txRingNum, uint8_t rxRingNum) -{ - assert(txRingNum); - assert(rxRingNum); - - uint8_t index; - - if (txRingNum > ENET_RING_NUM_MAX) - { - txRingNum = ENET_RING_NUM_MAX; - } - if (rxRingNum > ENET_RING_NUM_MAX) - { - rxRingNum = ENET_RING_NUM_MAX; - } - /* Start/Acive the DMA first. */ - for (index = 0; index < rxRingNum; index++) - { - base->DMA_CH[index].DMA_CHX_RX_CTRL |= ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK; - } - for (index = 0; index < txRingNum; index++) - { - base->DMA_CH[index].DMA_CHX_TX_CTRL |= ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK; - } - - /* Enable the RX/TX then. */ - base->MAC_CONFIG |= ENET_MAC_CONFIG_RE_MASK; - base->MAC_CONFIG |= ENET_MAC_CONFIG_TE_MASK; -} - -void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask) -{ - uint32_t interrupt = mask & 0xFFFFU; - uint8_t index; - - /* For dma interrupt. */ - if (interrupt) - { - for (index = 0; index < ENET_RING_NUM_MAX; index++) - { - /* Set for all abnormal interrupts. */ - if (ENET_ABNORM_INT_MASK & interrupt) - { - interrupt |= ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK; - } - /* Set for all normal interrupts. */ - if (ENET_NORM_INT_MASK & interrupt) - { - interrupt |= ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK; - } - base->DMA_CH[index].DMA_CHX_INT_EN = interrupt; - } - } - interrupt = interrupt >> ENET_MACINT_ENUM_OFFSET; - if (interrupt) - { - /* MAC interrupt */ - base->MAC_INTR_EN |= interrupt; - } -} - -void ENET_ClearMacInterruptStatus(ENET_Type *base, uint32_t mask) -{ - volatile uint32_t dummy; - - if (mask & kENET_MacTimestamp) - { - dummy = base->MAC_SYS_TIMESTMP_STAT; - } - else if (mask & kENET_MacPmt) - { - dummy = base->MAC_PMT_CRTL_STAT; - } - else - { - /* Add for avoid the misra 2004 rule 14.10 */ - } - (void)dummy; -} - -void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask) -{ - uint32_t interrupt = mask & 0xFFFFU; - uint8_t index; - - /* For dma interrupt. */ - if (interrupt) - { - for (index = 0; index < ENET_RING_NUM_MAX; index++) - { - /* Set for all abnormal interrupts. */ - if (ENET_ABNORM_INT_MASK & interrupt) - { - interrupt |= ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK; - } - /* Set for all normal interrupts. */ - if (ENET_NORM_INT_MASK & interrupt) - { - interrupt |= ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK; - } - base->DMA_CH[index].DMA_CHX_INT_EN &= ~interrupt; - } - } - interrupt = interrupt >> ENET_MACINT_ENUM_OFFSET; - if (interrupt) - { - /* MAC interrupt */ - base->MAC_INTR_EN &= ~interrupt; - } -} - -void ENET_CreateHandler(ENET_Type *base, - enet_handle_t *handle, - enet_config_t *config, - enet_buffer_config_t *bufferConfig, - enet_callback_t callback, - void *userData) -{ - assert(config); - assert(bufferConfig); - assert(callback); - - uint8_t ringNum = 1; - uint8_t count = 0; - uint8_t rxIntEnable = 0; - enet_buffer_config_t *buffConfig = bufferConfig; - - if (config->multiqueueCfg) - { - ringNum = 2; - handle->multiQueEnable = true; - } - - /* Store transfer parameters in handle pointer. */ - memset(handle, 0, sizeof(enet_handle_t)); - if (config->specialControl & kENET_DescDoubleBuffer) - { - handle->doubleBuffEnable = true; - } - if (config->multiqueueCfg) - { - handle->multiQueEnable = true; - } - for (count = 0; count < ringNum; count++) - { - handle->rxBdRing[count].rxBdBase = buffConfig->rxDescStartAddrAlign; - handle->rxBdRing[count].rxGenIdx = 0; - handle->rxBdRing[count].rxRingLen = buffConfig->rxRingLen; - handle->rxBdRing[count].rxBuffSizeAlign = buffConfig->rxBuffSizeAlign; - - handle->txBdRing[count].txBdBase = buffConfig->txDescStartAddrAlign; - handle->txBdRing[count].txRingLen = buffConfig->txRingLen; - handle->txBdRing[count].txGenIdx = 0; - handle->txBdRing[count].txConsumIdx = 0; - handle->txBdRing[count].txDescUsed = 0; -#ifdef ENET_PTP1588FEATURE_REQUIRED - assert(bufferConfig->rxPtpTsData); - assert(bufferConfig->txPtpTsData); - assert(buffConfig->rxRingLen <= ENET_RXBUFFSTORE_NUM); - - uint32_t index; - - handle->rxBdRing[count].rxPtpTsDataRing.ptpTsData = buffConfig->rxPtpTsData; - handle->rxBdRing[count].rxPtpTsDataRing.front = 0; - handle->rxBdRing[count].rxPtpTsDataRing.end = 0; - handle->rxBdRing[count].rxPtpTsDataRing.size = buffConfig->ptpTsRxBuffNum; - handle->txBdRing[count].txPtpTsDataRing.ptpTsData = buffConfig->txPtpTsData; - handle->txBdRing[count].txPtpTsDataRing.front = 0; - handle->txBdRing[count].txPtpTsDataRing.end = 0; - handle->txBdRing[count].txPtpTsDataRing.size = buffConfig->ptpTsTxBuffNum; - - for (index = 0; index < buffConfig->rxRingLen; index++) - { - handle->rxbuffers[index] = *(buffConfig->rxBufferStartAddr + index); - } -#endif /* ENET_PTP1588FEATURE_REQUIRED */ - /* Enable tx interrupt for use transactional API to do tx buffer free/requeue. */ - base->DMA_CH[count].DMA_CHX_INT_EN |= ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK; - /* Check if the rx interrrupt is enabled. */ - rxIntEnable |= (base->DMA_CH[count].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK); - buffConfig++; - } - - handle->rxintEnable = rxIntEnable ? true : false; - - /* Save the handle pointer in the global variables. */ - s_ENETHandle[ENET_GetInstance(base)] = handle; - - /* Set callback and userData. */ - handle->callback = callback; - handle->userData = userData; - - /* Enable the NVIC for tx. */ - s_enetIsr = ENET_IRQHandler; - EnableIRQ(s_enetIrqId[ENET_GetInstance(base)]); -} - -void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr) -{ - assert(macAddr); - - uint32_t address = base->MAC_ADDR_LOW; - - /* Get from physical address lower register. */ - macAddr[2] = 0xFFU & (address >> 24U); - macAddr[3] = 0xFFU & (address >> 16U); - macAddr[4] = 0xFFU & (address >> 8U); - macAddr[5] = 0xFFU & address; - - /* Get from physical address high register. */ - address = base->MAC_ADDR_HIGH; - macAddr[0] = 0xFFU & (address >> 8U); - macAddr[1] = 0xFFU & address; -} - -void ENET_SetSMI(ENET_Type *base) -{ - uint32_t crDiv; - uint32_t srcClock_Hz = CLOCK_GetFreq(kCLOCK_CoreSysClk) / 1000000U; - - if ((srcClock_Hz >= 20U) && (srcClock_Hz < 35)) - { - crDiv = 2; - } - else if ((srcClock_Hz >= 35) && (srcClock_Hz < 60)) - { - crDiv = 3; - } - else if ((srcClock_Hz >= 100) && (srcClock_Hz < 150)) - { - crDiv = 1; - } - else - { - crDiv = 0; - } - - base->MAC_MDIO_ADDR = ENET_MAC_MDIO_ADDR_CR(crDiv); -} - -void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) -{ - uint32_t reg = base->MAC_MDIO_ADDR & ENET_MAC_MDIO_ADDR_CR_MASK; - - /* Build MII write command. */ - base->MAC_MDIO_ADDR = reg | ENET_MAC_MDIO_ADDR_MOC(kENET_MiiWriteFrame) | ENET_MAC_MDIO_ADDR_PA(phyAddr) | - ENET_MAC_MDIO_ADDR_RDA(phyReg); - base->MAC_MDIO_DATA = data; - base->MAC_MDIO_ADDR |= ENET_MAC_MDIO_ADDR_MB_MASK; -} - -void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg) -{ - uint32_t reg = base->MAC_MDIO_ADDR & ENET_MAC_MDIO_ADDR_CR_MASK; - - /* Build MII read command. */ - base->MAC_MDIO_ADDR = reg | ENET_MAC_MDIO_ADDR_MOC(kENET_MiiReadFrame) | ENET_MAC_MDIO_ADDR_PA(phyAddr) | - ENET_MAC_MDIO_ADDR_RDA(phyReg); - base->MAC_MDIO_ADDR |= ENET_MAC_MDIO_ADDR_MB_MASK; -} - -void ENET_EnterPowerDown(ENET_Type *base, uint32_t *wakeFilter) -{ - uint8_t index; - uint32_t *reg = wakeFilter; - - /* Disable the tx dma. */ - base->DMA_CH[0].DMA_CHX_TX_CTRL &= ~ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK; - base->DMA_CH[1].DMA_CHX_TX_CTRL &= ~ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK; - - /* Disable the mac tx/rx. */ - base->MAC_CONFIG &= ~(ENET_MAC_CONFIG_RE_MASK | ENET_MAC_CONFIG_TE_MASK); - /* Enable the remote wakeup packet and enable the power down mode. */ - if (wakeFilter) - { - for (index = 0; index < ENET_WAKEUPFILTER_NUM; index++) - { - base->MAC_RWAKE_FRFLT = *reg; - reg++; - } - } - base->MAC_PMT_CRTL_STAT = ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK | ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK | - ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK; - - /* Enable the MAC rx. */ - base->MAC_CONFIG |= ENET_MAC_CONFIG_RE_MASK; -} - -status_t ENET_GetRxFrameSize(ENET_Type *base, enet_handle_t *handle, uint32_t *length, uint8_t channel) -{ - assert(handle); - assert(length); - - enet_rx_bd_ring_t *rxBdRing = (enet_rx_bd_ring_t *)&handle->rxBdRing[channel]; - enet_rx_bd_struct_t *rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx; - uint16_t index; - - /* Reset the length to zero. */ - *length = 0; - - if (rxDesc->control & ENET_RXDESCRIP_WR_OWN_MASK) - { - return kStatus_ENET_RxFrameEmpty; - } - else - { - do - { - /* Application owns the buffer descriptor, get the length. */ - if (rxDesc->control & ENET_RXDESCRIP_WR_LD_MASK) - { - if (rxDesc->control & ENET_RXDESCRIP_WR_ERRSUM_MASK) - { - return kStatus_ENET_RxFrameError; - } - *length = rxDesc->control & ENET_RXDESCRIP_WR_PACKETLEN_MASK; - return kStatus_Success; - } - - index = ENET_IncreaseIndex(index, rxBdRing->rxRingLen); - rxDesc = rxBdRing->rxBdBase + index; - } while (index != rxBdRing->rxGenIdx); - - return kStatus_ENET_RxFrameError; - } -} - -status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint8_t channel) -{ - assert(handle); - - uint32_t len = 0; - uint32_t offset = 0; - uint32_t control; - bool isLastBuff = false; - enet_rx_bd_ring_t *rxBdRing = (enet_rx_bd_ring_t *)&handle->rxBdRing[channel]; - enet_rx_bd_struct_t *rxDesc; - status_t result = kStatus_Fail; - uint16_t index = rxBdRing->rxGenIdx; - bool suspend = false; -#ifdef ENET_PTP1588FEATURE_REQUIRED - uint32_t buffer; - uint32_t bufferAdd; -#endif /* ENET_PTP1588FEATURE_REQUIRED */ - - /* Suspend and command for rx. */ - if (base->DMA_CH[channel].DMA_CHX_STAT & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK) - { - suspend = true; - } - - /* For data-NULL input, only update the buffer descriptor. */ - if ((!data)) - { - do - { - /* Get the control flag. */ - rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx; - rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen); - control = rxDesc->control; - /* Updates the receive buffer descriptors. */ - ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable); - - /* Find the last buffer descriptor for the frame. */ - if (control & ENET_RXDESCRIP_WR_LD_MASK) - { -#ifdef ENET_PTP1588FEATURE_REQUIRED - /* Reinit for the context descritor which has been updated by DMA. */ - rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx; - if (rxDesc->control & ENET_RXDESCRIP_WR_CTXT_MASK) - { - if (!handle->doubleBuffEnable) - { - buffer = handle->rxbuffers[rxBdRing->rxGenIdx]; - ENET_UpdateRxDescriptor(rxDesc, (void *)buffer, NULL, handle->rxintEnable, - handle->doubleBuffEnable); - } - else - { - buffer = handle->rxbuffers[2 * rxBdRing->rxGenIdx]; - bufferAdd = handle->rxbuffers[2 * rxBdRing->rxGenIdx + 1]; - ENET_UpdateRxDescriptor(rxDesc, (void *)buffer, (void *)bufferAdd, handle->rxintEnable, - handle->doubleBuffEnable); - } - rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen); - } -#endif /* ENET_PTP1588FEATURE_REQUIRED */ - break; - } - } while (rxBdRing->rxGenIdx != index); - - result = kStatus_Success; - } - else - { -#ifdef ENET_PTP1588FEATURE_REQUIRED - enet_ptp_time_data_t ptpTsData; - bool ptp1588 = false; -#endif /* ENET_PTP1588FEATURE_REQUIRED */ - - while ((!isLastBuff)) - { - /* The last buffer descriptor of a frame. */ - rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx; - rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen); -#ifdef ENET_PTP1588FEATURE_REQUIRED - if (rxDesc->control & ENET_RXDESCRIP_WR_FD_MASK) - { - ptp1588 = ENET_Ptp1588ParseFrame((uint8_t *)rxDesc->buff1Addr, &ptpTsData, false); - } -#endif - if (rxDesc->control & ENET_RXDESCRIP_WR_LD_MASK) - { - /* This is a valid frame. */ - isLastBuff = true; - if (length == (rxDesc->control & ENET_RXDESCRIP_WR_PACKETLEN_MASK)) - { - /* Copy the frame to user's buffer. */ - len = (rxDesc->control & ENET_RXDESCRIP_WR_PACKETLEN_MASK) - offset; - if (len > rxBdRing->rxBuffSizeAlign) - { - memcpy(data + offset, (void *)rxDesc->buff1Addr, rxBdRing->rxBuffSizeAlign); - offset += rxBdRing->rxBuffSizeAlign; - memcpy(data + offset, (void *)rxDesc->buff2Addr, len - rxBdRing->rxBuffSizeAlign); - } - else - { - memcpy(data + offset, (void *)rxDesc->buff1Addr, len); - } - - result = kStatus_Success; - } - - /* Updates the receive buffer descriptors. */ - ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable); -#ifdef ENET_PTP1588FEATURE_REQUIRED - /* Store the rx timestamp which is in the next buffer descriptor of the last - * descriptor of a frame. */ - rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx; - - /* Reinit for the context descritor which has been updated by DMA. */ - if (rxDesc->control & ENET_RXDESCRIP_WR_CTXT_MASK) - { - if (ptp1588) - { - ENET_StoreRxFrameTime(base, handle, rxDesc, channel, &ptpTsData); - } - - if (!handle->doubleBuffEnable) - { - buffer = handle->rxbuffers[rxBdRing->rxGenIdx]; - ENET_UpdateRxDescriptor(rxDesc, (void *)buffer, NULL, handle->rxintEnable, - handle->doubleBuffEnable); - } - else - { - buffer = handle->rxbuffers[2 * rxBdRing->rxGenIdx]; - bufferAdd = handle->rxbuffers[2 * rxBdRing->rxGenIdx + 1]; - ENET_UpdateRxDescriptor(rxDesc, (void *)buffer, (void *)bufferAdd, handle->rxintEnable, - handle->doubleBuffEnable); - } - rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen); - } - base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR; -#endif /* ENET_PTP1588FEATURE_REQUIRED */ - } - else - { - /* Store a frame on several buffer descriptors. */ - isLastBuff = false; - /* Length check. */ - if (offset >= length) - { - /* Updates the receive buffer descriptors. */ - ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable); - break; - } - - memcpy(data + offset, (void *)rxDesc->buff1Addr, rxBdRing->rxBuffSizeAlign); - offset += rxBdRing->rxBuffSizeAlign; - if ((rxDesc->buff2Addr) && (handle->doubleBuffEnable)) - { - memcpy(data + offset, (void *)rxDesc->buff2Addr, rxBdRing->rxBuffSizeAlign); - offset += rxBdRing->rxBuffSizeAlign; - } - - /* Updates the receive buffer descriptors. */ - ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable); - } - } - } - - /* Set command for rx when it is suspend. */ - if (suspend) - { - base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR; - } - - return result; -} - -void ENET_UpdateRxDescriptor( - enet_rx_bd_struct_t *rxDesc, void *buffer1, void *buffer2, bool intEnable, bool doubleBuffEnable) -{ - assert(rxDesc); - uint32_t control = ENET_RXDESCRIP_RD_OWN_MASK | ENET_RXDESCRIP_RD_BUFF1VALID_MASK; - - if (intEnable) - { - control |= ENET_RXDESCRIP_RD_IOC_MASK; - } - - if (doubleBuffEnable) - { - control |= ENET_RXDESCRIP_RD_BUFF2VALID_MASK; - } - - /* Update the buffer if needed. */ - if (buffer1) - { - rxDesc->buff1Addr = (uint32_t)buffer1; - } - if (buffer2) - { - rxDesc->buff2Addr = (uint32_t)buffer2; - } - else - { - rxDesc->buff2Addr = 0; - } - - rxDesc->reserved = 0; - rxDesc->control = control; -} - -void ENET_SetupTxDescriptor(enet_tx_bd_struct_t *txDesc, - void *buffer1, - uint32_t bytes1, - void *buffer2, - uint32_t bytes2, - uint32_t framelen, - bool intEnable, - bool tsEnable, - enet_desc_flag flag, - uint8_t slotNum) -{ - uint32_t control = ENET_TXDESCRIP_RD_BL1(bytes1) | ENET_TXDESCRIP_RD_BL2(bytes2); - - if (tsEnable) - { - control |= ENET_TXDESCRIP_RD_TTSE_MASK; - } - else - { - control &= ~ENET_TXDESCRIP_RD_TTSE_MASK; - } - - if (intEnable) - { - control |= ENET_TXDESCRIP_RD_IOC_MASK; - } - else - { - control &= ~ENET_TXDESCRIP_RD_IOC_MASK; - } - - /* Preare the descriptor for transmit. */ - txDesc->buff1Addr = (uint32_t)buffer1; - txDesc->buff2Addr = (uint32_t)buffer2; - txDesc->buffLen = control; - - control = ENET_TXDESCRIP_RD_FL(framelen) | ENET_TXDESCRIP_RD_LDFD(flag) | ENET_TXDESCRIP_RD_OWN_MASK; - - txDesc->controlStat = control; -} - -void ENET_ReclaimTxDescriptor(ENET_Type *base, enet_handle_t *handle, uint8_t channel) -{ - enet_tx_bd_ring_t *txBdRing = &handle->txBdRing[channel]; - enet_tx_bd_struct_t *txDesc = txBdRing->txBdBase + txBdRing->txConsumIdx; - - /* Need to update the first index for transmit buffer free. */ - while ((txBdRing->txDescUsed > 0) && (!(txDesc->controlStat & ENET_TXDESCRIP_RD_OWN_MASK))) - { -#ifdef ENET_PTP1588FEATURE_REQUIRED - uint32_t nanosecond; - uint32_t nanoOverSize = ENET_NANOSECS_ONESECOND; /* Default use the digital rollover. */ - - if (txDesc->controlStat & ENET_TXDESCRIP_RD_LD_MASK) - { - enet_ptp_time_data_t *ptpTsData = txBdRing->txPtpTsDataRing.ptpTsData + txBdRing->txPtpTsDataRing.end; - if (txDesc->controlStat & ENET_TXDESCRIP_WB_TTSS_MASK) - { - /* Get transmit time stamp second. */ - nanosecond = txDesc->buff2Addr | txDesc->buff1Addr; - if (!(base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)) - { - /* Binary rollover. */ - nanoOverSize = ENET_MAC_SYS_TIME_NSCND_TSSS_MASK; - } - ptpTsData->timeStamp.second = nanosecond / nanoOverSize; - ptpTsData->timeStamp.nanosecond = nanosecond % nanoOverSize; - - /* Store the timestamp to the transmit timestamp ring. */ - ENET_Ptp1588UpdateTimeRing(&txBdRing->txPtpTsDataRing, ptpTsData); - } - } -#endif /* ENET_PTP1588FEATURE_REQUIRED */ - - /* For tx buffer free or requeue for each descriptor. - * The tx interrupt callback should free/requeue the tx buffer. */ - if (handle->callback) - { - handle->callback(base, handle, kENET_TxIntEvent, channel, handle->userData); - } - - txBdRing->txDescUsed--; - - /* Update the txConsumIdx/txDesc. */ - txBdRing->txConsumIdx = ENET_IncreaseIndex(txBdRing->txConsumIdx, txBdRing->txRingLen); - txDesc = txBdRing->txBdBase + txBdRing->txConsumIdx; - } -} - -status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length) -{ - assert(handle); - assert(data); - - enet_tx_bd_ring_t *txBdRing; - enet_tx_bd_struct_t *txDesc; - uint8_t channel = 0; - bool ptp1588 = false; - - if (length > 2 * ENET_TXDESCRIP_RD_BL1_MASK) - { - return kStatus_ENET_TxFrameOverLen; - } - - /* Choose the transit queue. */ - channel = ENET_GetTxRingId(data, handle); - - /* Check if the DMA owns the descriptor. */ - txBdRing = (enet_tx_bd_ring_t *)&handle->txBdRing[channel]; - txDesc = txBdRing->txBdBase + txBdRing->txGenIdx; - if (txBdRing->txRingLen == txBdRing->txDescUsed) - { - return kStatus_ENET_TxFrameBusy; - } - -#ifdef ENET_PTP1588FEATURE_REQUIRED - enet_ptp_time_data_t ptpTsData; - - ptp1588 = ENET_Ptp1588ParseFrame(data, &ptpTsData, true); -#endif /* ENET_PTP1588FEATURE_REQUIRED */ - - /* Fill the descriptor. */ - if (length <= ENET_TXDESCRIP_RD_BL1_MASK) - { - ENET_SetupTxDescriptor(txDesc, data, length, NULL, 0, length, true, ptp1588, kENET_FirstLastFlag, 0); - } - else - { - ENET_SetupTxDescriptor(txDesc, data, ENET_TXDESCRIP_RD_BL1_MASK, data + ENET_TXDESCRIP_RD_BL1_MASK, - (length - ENET_TXDESCRIP_RD_BL1_MASK), length, true, ptp1588, kENET_FirstLastFlag, 0); - } - - /* Increase the index. */ - txBdRing->txGenIdx = ENET_IncreaseIndex(txBdRing->txGenIdx, txBdRing->txRingLen); - /* Disable interrupt first and then enable interrupt to avoid the race condition. */ - DisableIRQ(s_enetIrqId[ENET_GetInstance(base)]); - txBdRing->txDescUsed++; - EnableIRQ(s_enetIrqId[ENET_GetInstance(base)]); - - /* Update the transmit tail address. */ - txDesc = txBdRing->txBdBase + txBdRing->txGenIdx; - if (!txBdRing->txGenIdx) - { - txDesc = txBdRing->txBdBase + txBdRing->txRingLen; - } - base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR = (uint32_t)txDesc & ~ENET_ADDR_ALIGNMENT; - - return kStatus_Success; -} - -#ifdef ENET_PTP1588FEATURE_REQUIRED -void ENET_Ptp1588GetTimer(ENET_Type *base, uint64_t *second, uint32_t *nanosecond) -{ - assert(second); - assert(nanosecond); - - uint32_t primask; - - /* Disables the interrupt. */ - primask = DisableGlobalIRQ(); - - /* Get the current PTP time. */ - *second = ((uint64_t)(base->MAC_SYS_TIME_HWORD_SCND & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK) << 32U) | - base->MAC_SYS_TIME_SCND; - *nanosecond = base->MAC_SYS_TIME_NSCND & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK; - if (!(base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)) - { - /* Binary rollover, the unit of the increment is ~ 0.466 ns. */ - *nanosecond = *nanosecond / 1000U * 466U; - } - - /* Enables the interrupt. */ - EnableGlobalIRQ(primask); -} - -void ENET_Ptp1588CorrectTimerInCoarse(ENET_Type *base, enet_systime_op operation, uint32_t second, uint32_t nanosecond) -{ - uint32_t corrSecond = second; - uint32_t corrNanosecond; - - /* Set the system timer. */ - if (base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK) - { - if (operation == kENET_SystimeSubtract) - { - /* Set with the complement of the sub-second. */ - corrSecond = ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK - (second - 1); - corrNanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK | - ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(ENET_NANOSECS_ONESECOND - nanosecond); - } - else - { - corrNanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(nanosecond); - } - } - else - { - nanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK / ENET_NANOSECS_ONESECOND * nanosecond; - if (operation == kENET_SystimeSubtract) - { - /* Set with the complement of the sub-second. */ - corrSecond = ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK - (second - 1); - corrNanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK | - ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK + 1 - nanosecond); - } - else - { - corrNanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(nanosecond); - } - } - - base->MAC_SYS_TIME_SCND_UPD = corrSecond; - base->MAC_SYS_TIME_NSCND_UPD = corrNanosecond; - - /* Update the timer. */ - base->MAC_TIMESTAMP_CTRL |= ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK; - while (base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK) - ; -} - -status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) -{ - assert(handle); - assert(ptpTimeData); - - uint32_t result = kStatus_Success; - uint8_t count; - uint8_t index = handle->multiQueEnable ? 2 : 1; - - for (count = 0; count < index; count++) - { - result = ENET_Ptp1588SearchTimeRing(&handle->txBdRing[count].txPtpTsDataRing, ptpTimeData); - if (result == kStatus_Success) - { - break; - } - } - - return result; -} - -status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) -{ - assert(handle); - assert(ptpTimeData); - - uint32_t result = kStatus_Success; - uint8_t count; - uint8_t index = handle->multiQueEnable ? 2 : 1; - - for (count = 0; count < index; count++) - { - result = ENET_Ptp1588SearchTimeRing(&handle->rxBdRing[count].rxPtpTsDataRing, ptpTimeData); - if (result == kStatus_Success) - { - break; - } - } - - return result; -} - -#endif /* ENET_PTP1588FEATURE_REQUIRED */ - -void ENET_IRQHandler(ENET_Type *base, enet_handle_t *handle) -{ - /* Check for the interrupt source type. */ - /* DMA CHANNEL 0. */ - if (base->DMA_INTR_STAT & ENET_DMA_INTR_STAT_DC0IS_MASK) - { - uint32_t flag = base->DMA_CH[0].DMA_CHX_STAT; - if (flag & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK) - { - base->DMA_CH[0].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_RI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK; - if (handle->callback) - { - handle->callback(base, handle, kENET_RxIntEvent, 0, handle->userData); - } - } - if (flag & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK) - { - base->DMA_CH[0].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_TI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK; - ENET_ReclaimTxDescriptor(base, handle, 0); - } - } - - /* DMA CHANNEL 1. */ - if (base->DMA_INTR_STAT & ENET_DMA_INTR_STAT_DC1IS_MASK) - { - uint32_t flag = base->DMA_CH[1].DMA_CHX_STAT; - if (flag & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK) - { - base->DMA_CH[1].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_RI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK; - if (handle->callback) - { - handle->callback(base, handle, kENET_RxIntEvent, 1, handle->userData); - } - } - if (flag & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK) - { - base->DMA_CH[1].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_TI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK; - ENET_ReclaimTxDescriptor(base, handle, 1); - } - } - -#ifdef ENET_PTP1588FEATURE_REQUIRED - /* MAC TIMESTAMP. */ - if (base->DMA_INTR_STAT & ENET_DMA_INTR_STAT_MACIS_MASK) - { - if (base->MAC_INTR_STAT & ENET_MAC_INTR_STAT_TSIS_MASK) - { - if (handle->callback) - { - handle->callback(base, handle, kENET_TimeStampIntEvent, 0, handle->userData); - } - } - } -#endif /* ENET_PTP1588FEATURE_REQUIRED */ -} - -void ETHERNET_DriverIRQHandler(void) -{ - s_enetIsr(ENET, s_ENETHandle[0]); -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_enet.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_enet.h deleted file mode 100644 index 631fd88121a..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_enet.h +++ /dev/null @@ -1,1178 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_ENET_H_ -#define _FSL_ENET_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_enet - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Defines the driver version. */ -#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ -/*@}*/ - -/*! @name Control and status region bit masks of the receive buffer descriptor. */ -/*@{*/ -/*! @brief Defines for read format. */ -#define ENET_RXDESCRIP_RD_BUFF1VALID_MASK (1U << 24) /*!< Buffer1 address valid. */ -#define ENET_RXDESCRIP_RD_BUFF2VALID_MASK (1U << 25) /*!< Buffer2 address valid. */ -#define ENET_RXDESCRIP_RD_IOC_MASK (1U << 30) /*!< Interrupt enable on complete. */ -#define ENET_RXDESCRIP_RD_OWN_MASK (1U << 31) /*!< Own bit. */ - -/*! @brief Defines for write back format. */ -#define ENET_RXDESCRIP_WR_ERR_MASK ((1U << 3) | (1U << 7)) -#define ENET_RXDESCRIP_WR_PYLOAD_MASK (0x7U) -#define ENET_RXDESCRIP_WR_PTPMSGTYPE_MASK (0xF00U) -#define ENET_RXDESCRIP_WR_PTPTYPE_MASK (1U << 12) -#define ENET_RXDESCRIP_WR_PTPVERSION_MASK (1U << 13) -#define ENET_RXDESCRIP_WR_PTPTSA_MASK (1U << 14) -#define ENET_RXDESCRIP_WR_PACKETLEN_MASK (0x7FFFU) -#define ENET_RXDESCRIP_WR_ERRSUM_MASK (1U << 15) -#define ENET_RXDESCRIP_WR_TYPE_MASK (0x30000U) -#define ENET_RXDESCRIP_WR_DE_MASK (1U << 19) -#define ENET_RXDESCRIP_WR_RE_MASK (1U << 20) -#define ENET_RXDESCRIP_WR_OE_MASK (1U << 21) -#define ENET_RXDESCRIP_WR_RS0V_MASK (1U << 25) -#define ENET_RXDESCRIP_WR_RS1V_MASK (1U << 26) -#define ENET_RXDESCRIP_WR_RS2V_MASK (1U << 27) -#define ENET_RXDESCRIP_WR_LD_MASK (1U << 28) -#define ENET_RXDESCRIP_WR_FD_MASK (1U << 29) -#define ENET_RXDESCRIP_WR_CTXT_MASK (1U << 30) -#define ENET_RXDESCRIP_WR_OWN_MASK (1U << 31) -/*@}*/ - -/*! @name Control and status bit masks of the transmit buffer descriptor. */ -/*@{*/ -/*! @brief Defines for read format. */ -#define ENET_TXDESCRIP_RD_BL1_MASK (0x3fffU) -#define ENET_TXDESCRIP_RD_BL2_MASK (ENET_TXDESCRIP_RD_BL1_MASK << 16) -#define ENET_TXDESCRIP_RD_BL1(n) ((uint32_t)(n) & ENET_TXDESCRIP_RD_BL1_MASK) -#define ENET_TXDESCRIP_RD_BL2(n) (((uint32_t)(n) & ENET_TXDESCRIP_RD_BL1_MASK) << 16) -#define ENET_TXDESCRIP_RD_TTSE_MASK (1U << 30) -#define ENET_TXDESCRIP_RD_IOC_MASK (1U << 31) - -#define ENET_TXDESCRIP_RD_FL_MASK (0x7FFFU) -#define ENET_TXDESCRIP_RD_FL(n) ((uint32_t)(n) & ENET_TXDESCRIP_RD_FL_MASK) -#define ENET_TXDESCRIP_RD_CIC(n) (((uint32_t)(n) & 0x3) << 16) -#define ENET_TXDESCRIP_RD_TSE_MASK (1U << 18) -#define ENET_TXDESCRIP_RD_SLOT(n) (((uint32_t)(n) & 0x0f) << 19) -#define ENET_TXDESCRIP_RD_SAIC(n) (((uint32_t)(n) & 0x07) << 23) -#define ENET_TXDESCRIP_RD_CPC(n) (((uint32_t)(n) & 0x03) << 26) -#define ENET_TXDESCRIP_RD_LDFD(n) (((uint32_t)(n) & 0x03) << 28) -#define ENET_TXDESCRIP_RD_LD_MASK (1U << 28) -#define ENET_TXDESCRIP_RD_FD_MASK (1U << 29) -#define ENET_TXDESCRIP_RD_CTXT_MASK (1U << 30) -#define ENET_TXDESCRIP_RD_OWN_MASK (1UL << 31) - -/*! @brief Defines for write back format. */ -#define ENET_TXDESCRIP_WB_TTSS_MASK (1UL << 17) -/*@}*/ - -/*! @name Bit mask for interrupt enable type. */ -/*@{*/ -#define ENET_ABNORM_INT_MASK \ - (ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK | \ - ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK | \ - ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK) -#define ENET_NORM_INT_MASK \ - (ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK | \ - ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK) -/*@}*/ - -/*! @name Defines some Ethernet parameters. */ -/*@{*/ - -#define ENET_FRAME_MAX_FRAMELEN (1518U)/*!< Default maximum Ethernet frame size. */ -#define ENET_ADDR_ALIGNMENT (0x3U) /*!< Recommended ethernet buffer alignment. */ -#define ENET_BUFF_ALIGNMENT (4U) /*!< Receive buffer alignment shall be 4bytes-aligned. */ -#define ENET_RING_NUM_MAX (2U) /*!< The Maximum number of tx/rx descriptor rings. */ -#define ENET_MTL_RXFIFOSIZE (2048U) /*!< The rx fifo size. */ -#define ENET_MTL_TXFIFOSIZE (2048U) /*!< The tx fifo size. */ -#define ENET_MACINT_ENUM_OFFSET (16U) /*!< The offest for mac interrupt in enum type. */ -/*@}*/ - -#ifdef ENET_PTP1588FEATURE_REQUIRED -/* Define the buffer length to store the rx buffers address. - * because the context descriptor will be updated for store the time - * stamp for rx frame. so we need to reinit the descriptors. - * This macro shall at least equal to the rxRingLen - * assigned in the enet_buffer_config. That means if the rx descriptor - * length is larger than 5, please increse this macro. */ -#define ENET_RXBUFFSTORE_NUM (6) -#endif /* ENET_PTP1588FEATURE_REQUIRED */ - -/*! @brief Defines the status return codes for transaction. */ -enum _enet_status -{ - kStatus_ENET_RxFrameError = MAKE_STATUS(kStatusGroup_ENET, 0U), /*!< A frame received but data error happen. */ - kStatus_ENET_RxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 1U), /*!< Failed to receive a frame. */ - kStatus_ENET_RxFrameEmpty = MAKE_STATUS(kStatusGroup_ENET, 2U), /*!< No frame arrive. */ - kStatus_ENET_TxFrameBusy = MAKE_STATUS(kStatusGroup_ENET, 3U), /*!< Transmit descriptors are under process. */ - kStatus_ENET_TxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 4U), /*!< Transmit frame fail. */ - kStatus_ENET_TxFrameOverLen = MAKE_STATUS(kStatusGroup_ENET, 5U) /*!< Transmit oversize. */ -#ifdef ENET_PTP1588FEATURE_REQUIRED - , - kStatus_ENET_PtpTsRingFull = MAKE_STATUS(kStatusGroup_ENET, 6U), /*!< Timestamp ring full. */ - kStatus_ENET_PtpTsRingEmpty = MAKE_STATUS(kStatusGroup_ENET, 7U) /*!< Timestamp ring empty. */ -#endif /* ENET_PTP1588FEATURE_REQUIRED */ -}; - -/*! @brief Defines the MII/RMII mode for data interface between the MAC and the PHY. */ -typedef enum _enet_mii_mode { - kENET_MiiMode = 0U, /*!< MII mode for data interface. */ - kENET_RmiiMode = 1U /*!< RMII mode for data interface. */ -} enet_mii_mode_t; - -/*! @brief Defines the 10/100 Mbps speed for the MII data interface. */ -typedef enum _enet_mii_speed { - kENET_MiiSpeed10M = 0U, /*!< Speed 10 Mbps. */ - kENET_MiiSpeed100M = 1U, /*!< Speed 100 Mbps. */ -} enet_mii_speed_t; - -/*! @brief Defines the half or full duplex for the MII data interface. */ -typedef enum _enet_mii_duplex { - kENET_MiiHalfDuplex = 0U, /*!< Half duplex mode. */ - kENET_MiiFullDuplex /*!< Full duplex mode. */ -} enet_mii_duplex_t; - -/*! @brief Define the MII opcode for normal MDIO_CLAUSES_22 Frame. */ -typedef enum _enet_mii_normal_opcode { - kENET_MiiWriteFrame = 1U, /*!< Write frame operation for a valid MII management frame. */ - kENET_MiiReadFrame = 3U /*!< Read frame operation for a valid MII management frame. */ -} enet_mii_normal_opcode; - -/*! @brief Define the DMA maximum transmit burst length. */ -typedef enum _enet_dma_burstlen { - kENET_BurstLen1 = 0x00001U, /*!< DMA burst length 1. */ - kENET_BurstLen2 = 0x00002U, /*!< DMA burst length 2. */ - kENET_BurstLen4 = 0x00004U, /*!< DMA burst length 4. */ - kENET_BurstLen8 = 0x00008U, /*!< DMA burst length 8. */ - kENET_BurstLen16 = 0x00010U, /*!< DMA burst length 16. */ - kENET_BurstLen32 = 0x00020U, /*!< DMA burst length 32. */ - kENET_BurstLen64 = 0x10008U, /*!< DMA burst length 64. eight times enabled. */ - kENET_BurstLen128 = 0x10010U, /*!< DMA burst length 128. eight times enabled. */ - kENET_BurstLen256 = 0x10020U, /*!< DMA burst length 256. eight times enabled. */ -} enet_dma_burstlen; - -/*! @brief Define the flag for the descriptor. */ -typedef enum _enet_desc_flag { - kENET_MiddleFlag = 0, /*!< It's a middle descriptor of the frame. */ - kENET_FirstFlagOnly, /*!< It's the first descriptor of the frame. */ - kENET_LastFlagOnly, /*!< It's the last descriptor of the frame. */ - kENET_FirstLastFlag /*!< It's the first and last descriptor of the frame. */ -} enet_desc_flag; - -/*! @brief Define the system time adjust operation control. */ -typedef enum _enet_systime_op { - kENET_SystimeAdd = 0U, /*!< System time add to. */ - kENET_SystimeSubtract = 1U /*!< System time subtract. */ -} enet_systime_op; - -/*! @brief Define the system time rollover control. */ -typedef enum _enet_ts_rollover_type { - kENET_BinaryRollover = 0, /*!< System time binary rollover.*/ - kENET_DigitalRollover = 1 /*!< System time digital rollover.*/ -} enet_ts_rollover_type; - -/*! @brief Defines some special configuration for ENET. - * - * These control flags are provided for special user requirements. - * Normally, these is no need to set this control flags for ENET initialization. - * But if you have some special requirements, set the flags to specialControl - * in the enet_config_t. - * @note "kENET_StoreAndForward" is recommended to be set when the - * ENET_PTP1588FEATURE_REQUIRED is defined or else the timestamp will be mess-up - * when the overflow happens. - */ -typedef enum _enet_special_config { - - /***********************DMA CONFGI**********************************************/ - kENET_DescDoubleBuffer = 0x0001U, /*!< The double buffer is used in the tx/rx descriptor. */ - /**************************MTL************************************/ - kENET_StoreAndForward = 0x0002U, /*!< The rx/tx store and forward enable. */ - /***********************MAC****************************************/ - kENET_PromiscuousEnable = 0x0004U, /*!< The promiscuous enabled. */ - kENET_FlowControlEnable = 0x0008U, /*!< The flow control enabled. */ - kENET_BroadCastRxDisable = 0x0010U, /*!< The broadcast disabled. */ - kENET_MulticastAllEnable = 0x0020U, /*!< All multicast are passed. */ - kENET_8023AS2KPacket = 0x0040U /*!< 8023as support for 2K packets. */ -} enet_special_config_t; - -/*! @brief List of DMA interrupts supported by the ENET interrupt. This - * enumeration uses one-bot encoding to allow a logical OR of multiple - * members. - */ -typedef enum _enet_dma_interrupt_enable { - kENET_DmaTx = ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK, /*!< Tx interrupt. */ - kENET_DmaTxStop = ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK, /*!< Tx stop interrupt. */ - kENET_DmaTxBuffUnavail = ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK, /*!< Tx buffer unavailable. */ - kENET_DmaRx = ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK, /*!< Rx interrupt. */ - kENET_DmaRxBuffUnavail = ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK, /*!< Rx buffer unavailable. */ - kENET_DmaRxStop = ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK, /*!< Rx stop. */ - kENET_DmaRxWatchdogTimeout = ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK, /*!< Rx watchdog timeout. */ - kENET_DmaEarlyTx = ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK, /*!< Early transmit. */ - kENET_DmaEarlyRx = ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK, /*!< Early receive. */ - kENET_DmaBusErr = ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK, /*!< Fatal bus error. */ -} enet_dma_interrupt_enable_t; - -/*! @brief List of mac interrupts supported by the ENET interrupt. This - * enumeration uses one-bot encoding to allow a logical OR of multiple - * members. - */ -typedef enum _enet_mac_interrupt_enable { - kENET_MacPmt = (ENET_MAC_INTR_EN_PMTIE_MASK << ENET_MACINT_ENUM_OFFSET), - kENET_MacTimestamp = (ENET_MAC_INTR_EN_TSIE_MASK << ENET_MACINT_ENUM_OFFSET), -} enet_mac_interrupt_enable_t; - -/*! @brief Defines the common interrupt event for callback use. */ -typedef enum _enet_event { - kENET_RxIntEvent, /*!< Receive interrupt event. */ - kENET_TxIntEvent, /*!< Transmit interrupt event. */ - kENET_WakeUpIntEvent, /*!< Wake up interrupt event. */ - kENET_TimeStampIntEvent, /*!< Time stamp interrupt event. */ -} enet_event_t; - -/*! @brief Define the DMA transmit arbitration for multi-queue. */ -typedef enum _enet_dma_tx_sche { - kENET_FixPri = 0, /*!< Fixed priority. channel 0 has lower priority than channel 1. */ - kENET_WeightStrPri, /*!< Weighted(burst length) strict priority. */ - kENET_WeightRoundRobin /*!< Weighted (weight factor) round robin. */ -} enet_dma_tx_sche; - -/*! @brief Define the MTL tx scheduling algorithm for multiple queues/rings. */ -typedef enum _enet_mtl_multiqueue_txsche { - kENET_txWeightRR = 0U, /*!< Tx weight round-robin. */ - kENET_txStrPrio = 3U, /*!< Tx strict priority. */ -} enet_mtl_multiqueue_txsche; - -/*! @brief Define the MTL rx scheduling algorithm for multiple queues/rings. */ -typedef enum _enet_mtl_multiqueue_rxsche { - kENET_rxStrPrio = 0U, /*!< Tx weight round-robin, rx strict priority. */ - kENET_rxWeightStrPrio, /*!< Tx strict priority, rx weight strict priority. */ -} enet_mtl_multiqueue_rxsche; - -/*! @brief Define the MTL rx queue and DMA channel mapping. */ -typedef enum _enet_mtl_rxqueuemap { - kENET_StaticDirctMap = 0x100U, /*!< The received fame in rx Qn(n = 0,1) direclty map to dma channel n. */ - kENET_DynamicMap = - 0x1010U, /*!< The received frame in rx Qn(n = 0,1) map to the dma channel m(m = 0,1) related with the same Mac. - */ -} enet_mtl_rxqueuemap; - -/*! @brief Defines the ENET PTP message related constant. */ -typedef enum _enet_ptp_event_type { - kENET_PtpEventMsgType = 3U, /*!< PTP event message type. */ - kENET_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */ - kENET_PtpEventPort = 319U, /*!< PTP event port number. */ - kENET_PtpGnrlPort = 320U /*!< PTP general port number. */ -} enet_ptp_event_type_t; - -/*! @brief Defines the receive descriptor structure - * has the read-format and write-back format structure. They both - * has the same size with different region definition. so - * we define the read-format region as the recive descriptor structure - * Use the read-format region mask bits in the descriptor initialization - * Use the write-back format region mask bits in the receive data process. - */ -typedef struct _enet_rx_bd_struct -{ - __IO uint32_t buff1Addr; /*!< Buffer 1 address */ - __IO uint32_t reserved; /*!< Reserved */ - __IO uint32_t buff2Addr; /*!< Buffer 2 or next descriptor address */ - __IO uint32_t control; /*!< Buffer 1/2 byte counts and control */ -} enet_rx_bd_struct_t; - -/*! @brief Defines the transmit descriptor structure - * has the read-format and write-back format structure. They both - * has the same size with different region definition. so - * we define the read-format region as the transmit descriptor structure - * Use the read-format region mask bits in the descriptor initialization - * Use the write-back format region mask bits in the transmit data process. - */ -typedef struct _enet_tx_bd_struct -{ - __IO uint32_t buff1Addr; /*!< Buffer 1 address */ - __IO uint32_t buff2Addr; /*!< Buffer 2 address */ - __IO uint32_t buffLen; /*!< Buffer 1/2 byte counts */ - __IO uint32_t controlStat; /*!< TDES control and status word */ -} enet_tx_bd_struct_t; - -#ifdef ENET_PTP1588FEATURE_REQUIRED -/*! @brief Defines the ENET PTP time stamp structure. */ -typedef struct _enet_ptp_time -{ - uint64_t second; /*!< Second. */ - uint32_t nanosecond; /*!< Nanosecond. */ -} enet_ptp_time_t; - -/*! @brief Defines the structure for the ENET PTP message data and timestamp data.*/ -typedef struct _enet_ptp_time_data -{ - uint8_t version; /*!< PTP version. */ - uint8_t sourcePortId[kENET_PtpSrcPortIdLen]; /*!< PTP source port ID. */ - uint16_t sequenceId; /*!< PTP sequence ID. */ - uint8_t messageType; /*!< PTP message type. */ - enet_ptp_time_t timeStamp; /*!< PTP timestamp. */ -} enet_ptp_time_data_t; - -/*! @brief Defines the ENET PTP ring buffer structure for the PTP message timestamp store.*/ -typedef struct _enet_ptp_time_data_ring -{ - uint32_t front; /*!< The first index of the ring. */ - uint32_t end; /*!< The end index of the ring. */ - uint32_t size; /*!< The size of the ring. */ - enet_ptp_time_data_t *ptpTsData; /*!< PTP message data structure. */ -} enet_ptp_time_data_ring_t; - -/*! @brief Defines the ENET PTP configuration structure. */ -typedef struct _enet_ptp_config -{ - bool fineUpdateEnable; /*!< Use the fine update. */ - bool ptp1588V2Enable; /*!< ptp 1588 version 2 is used. */ - enet_ts_rollover_type tsRollover; /*!< 1588 time nanosecond rollover. */ -} enet_ptp_config_t; -#endif /* ENET_PTP1588FEATURE_REQUIRED */ - -/*! @brief Defines the buffer descriptor configure structure. - * - * Notes: - * 1. The receive and transmit descriptor start address pointer and tail pointer must be word-aligned. - * 2. The recommended minimum tx/rx ring length is 4. - * 3. The tx/rx descriptor tail address shall be the address pointer to the address just after the end - * of the last last descriptor. because only the descriptors between the start address and the - * tail address will be used by DMA. - * 4. The decriptor address is the start address of all used contiguous memory. - * for example, the rxDescStartAddrAlign is the start address of rxRingLen contiguous descriptor memorise - * for rx descriptor ring 0. - * 5. The "*rxBufferstartAddr" is the first element of rxRingLen (2*rxRingLen for double buffers) - * rx buffers. It means the *rxBufferStartAddr is the rx buffer for the first descriptor - * the *rxBufferStartAddr + 1 is the rx buffer for the second descriptor or the rx buffer for - * the second buffer in the first descriptor. so please make sure the rxBufferStartAddr is the - * address of a rxRingLen or 2*rxRingLen array. - */ -typedef struct _enet_buffer_config -{ - uint8_t rxRingLen; /*!< The length of receive buffer descriptor ring. */ - uint8_t txRingLen; /*!< The length of transmit buffer descriptor ring. */ - enet_tx_bd_struct_t *txDescStartAddrAlign; /*!< Aligned transmit descriptor start address. */ - enet_tx_bd_struct_t *txDescTailAddrAlign; /*!< Aligned transmit descriptor tail address. */ - enet_rx_bd_struct_t *rxDescStartAddrAlign; /*!< Aligned receive descriptor start address. */ - enet_rx_bd_struct_t *rxDescTailAddrAlign; /*!< Aligned receive descriptor tail address. */ - uint32_t *rxBufferStartAddr; /*!< Start address of the rx buffers. */ - uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ -#ifdef ENET_PTP1588FEATURE_REQUIRED - uint8_t ptpTsRxBuffNum; /*!< Receive 1588 timestamp buffer number*/ - uint8_t ptpTsTxBuffNum; /*!< Transmit 1588 timestamp buffer number*/ - enet_ptp_time_data_t *rxPtpTsData; /*!< The start address of 1588 receive timestamp buffers */ - enet_ptp_time_data_t *txPtpTsData; /*!< The start address of 1588 transmit timestamp buffers */ -#endif /* ENET_PTP1588FEATURE_REQUIRED */ -} enet_buffer_config_t; - -/*! @brief Defines the configuration when multi-queue is used. */ -typedef struct enet_multiqueue_config -{ - /***********************DMA block*******************************/ - enet_dma_tx_sche dmaTxSche; /*!< Transmit arbitation. */ - enet_dma_burstlen burstLen; /*!< Burset len for the queue 1. */ - uint8_t txdmaChnWeight[ENET_RING_NUM_MAX]; /*!< Transmit channel weight. */ - /***********************MTL block*******************************/ - enet_mtl_multiqueue_txsche mtltxSche; /*!< Transmit schedule for multi-queue. */ - enet_mtl_multiqueue_rxsche mtlrxSche; /*!< Receive schedule for multi-queue. */ - uint8_t rxqueweight[ENET_RING_NUM_MAX]; /*!< Refer to the MTL RxQ Control register. */ - uint32_t txqueweight[ENET_RING_NUM_MAX]; /*!< Refer to the MTL TxQ Quantum Weight register. */ - uint8_t rxqueuePrio[ENET_RING_NUM_MAX]; /*!< Receive queue priority. */ - uint8_t txqueuePrio[ENET_RING_NUM_MAX]; /*!< Refer to Transmit Queue Priority Mapping register. */ - enet_mtl_rxqueuemap mtlrxQuemap; /*!< Rx queue DMA Channel mapping. */ -} enet_multiqueue_config_t; - -/*! @brief Defines the basic configuration structure for the ENET device. - * - * Note: - * 1. Default the signal queue is used so the "*multiqueueCfg" is set default - * with NULL. Set the pointer with a valid configration pointer if the multiple - * queues are required. If multiple queue is enabled, please make sure the - * buffer configuration for all are prepared also. - */ -typedef struct _enet_config -{ - uint16_t specialControl; /*!< The logicl or of enet_special_config_t */ - enet_multiqueue_config_t *multiqueueCfg; /*!< Use both tx/rx queue(dma channel) 0 and 1. */ - /* -----------------MAC block-------------------------------*/ - enet_mii_mode_t miiMode; /*!< MII mode. */ - enet_mii_speed_t miiSpeed; /*!< MII Speed. */ - enet_mii_duplex_t miiDuplex; /*!< MII duplex. */ - uint16_t pauseDuration; /*!< Used in the tx flow control frame, only valid when kENET_FlowControlEnable is set. */ -/* -----------------Timestamp -------------------------------*/ -#ifdef ENET_PTP1588FEATURE_REQUIRED - enet_ptp_config_t *ptpConfig; /*!< PTP 1588 feature configuration */ -#endif /* ENET_PTP1588FEATURE_REQUIRED */ -} enet_config_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _enet_handle enet_handle_t; - -/*! @brief ENET callback function. */ -typedef void (*enet_callback_t)( - ENET_Type *base, enet_handle_t *handle, enet_event_t event, uint8_t channel, void *userData); - -/*! @brief Defines the ENET transmit buffer descriptor ring/queue structure. */ -typedef struct _enet_tx_bd_ring -{ - enet_tx_bd_struct_t *txBdBase; /*!< Buffer descriptor base address pointer. */ - uint16_t txGenIdx; /*!< tx generate index. */ - uint16_t txConsumIdx; /*!< tx consum index. */ - volatile uint16_t txDescUsed; /*!< tx descriptor used number. */ - uint16_t txRingLen; /*!< tx ring length. */ -#ifdef ENET_PTP1588FEATURE_REQUIRED - enet_ptp_time_data_ring_t txPtpTsDataRing; /*!< Transmit PTP 1588 time stamp data ring buffer. */ -#endif /* ENET_PTP1588FEATURE_REQUIRED */ -} enet_tx_bd_ring_t; - -/*! @brief Defines the ENET receive buffer descriptor ring/queue structure. */ -typedef struct _enet_rx_bd_ring -{ - enet_rx_bd_struct_t *rxBdBase; /*!< Buffer descriptor base address pointer. */ - uint16_t rxGenIdx; /*!< The current available receive buffer descriptor pointer. */ - uint16_t rxRingLen; /*!< Receive ring length. */ - uint32_t rxBuffSizeAlign; /*!< Receive buffer size. */ -#ifdef ENET_PTP1588FEATURE_REQUIRED - enet_ptp_time_data_ring_t rxPtpTsDataRing; /*!< Receive PTP 1588 time stamp data ring buffer. */ -#endif /* ENET_PTP1588FEATURE_REQUIRED*/ -} enet_rx_bd_ring_t; - -/*! @brief Defines the ENET handler structure. */ -struct _enet_handle -{ - bool multiQueEnable; /*!< Enable multi-queue. */ - bool doubleBuffEnable; /*!< The double buffer is used in the descriptor. */ - bool rxintEnable; /*!< Rx interrup enabled. */ - enet_rx_bd_ring_t rxBdRing[ENET_RING_NUM_MAX]; /*!< Receive buffer descriptor. */ - enet_tx_bd_ring_t txBdRing[ENET_RING_NUM_MAX]; /*!< Transmit buffer descriptor. */ -#ifdef ENET_PTP1588FEATURE_REQUIRED - uint32_t rxbuffers[ENET_RXBUFFSTORE_NUM]; /*!< The Initi-rx buffers will be used for reInitialize. */ -#endif - enet_callback_t callback; /*!< Callback function. */ - void *userData; /*!< Callback function parameter.*/ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and De-initialization - * @{ - */ - -/*! - * @brief Gets the ENET default configuration structure. - * - * The purpose of this API is to get the default ENET configure - * structure for ENET_Init(). User may use the initialized - * structure unchanged in ENET_Init(), or modify some fields of the - * structure before calling ENET_Init(). - * Example: - @code - enet_config_t config; - ENET_GetDefaultConfig(&config); - @endcode - * @param config The ENET mac controller configuration structure pointer. - */ -void ENET_GetDefaultConfig(enet_config_t *config); - -/*! - * @brief Initializes the ENET module. - * - * This function ungates the module clock and initializes it with the ENET basic - * configuration. - * - * @param base ENET peripheral base address. - * @param config ENET mac configuration structure pointer. - * The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig - * can be used directly. It is also possible to verify the Mac configuration using other methods. - * @param macAddr ENET mac address of Ethernet device. This MAC address should be - * provided. - * @param refclkSrc_Hz ENET input reference clock. - */ -void ENET_Init(ENET_Type *base, const enet_config_t *config, uint8_t *macAddr, uint32_t refclkSrc_Hz); - -/*! - * @brief Deinitializes the ENET module. - - * This function gates the module clock and disables the ENET module. - * - * @param base ENET peripheral base address. - */ -void ENET_Deinit(ENET_Type *base); - -/*! - * @brief Initialize for all ENET descriptors. - * - * @note This function is do all tx/rx descriptors initialization. Because this API - * read all interrupt registers first and then set the interrupt flag for all descriptos, - * if the interrupt register is set. so the descriptor initialization should be called - * after ENET_Init(), ENET_EnableInterrupts() and ENET_CreateHandle()(if transactional APIs - * are used). - * - * @param base ENET peripheral base address. - * @param config The configuration for ENET. - * @param bufferConfig All buffers configuration. - */ -status_t ENET_DescriptorInit(ENET_Type *base, enet_config_t *config, enet_buffer_config_t *bufferConfig); - -/*! - * @brief Starts the ENET rx/tx. - * This function enable the tx/rx and starts the rx/tx DMA. - * This shall be set after ENET initialization and before - * starting to receive the data. - * - * @param base ENET peripheral base address. - * @param rxRingNum The number of the used rx rings. It shall not be - * larger than the ENET_RING_NUM_MAX(2). If the ringNum is set with - * 1, the ring 0 will be used. - * @param txRingNum The number of the used tx rings. It shall not be - * larger than the ENET_RING_NUM_MAX(2). If the ringNum is set with - * 1, the ring 0 will be used. - * - * @note This must be called after all the ENET initilization. - * And should be called when the ENET receive/transmit is required. - */ -void ENET_StartRxTx(ENET_Type *base, uint8_t txRingNum, uint8_t rxRingNum); - -/* @} */ - -/*! - * @name MII interface operation - * @{ - */ - -/*! - * @brief Sets the ENET MII speed and duplex. - * - * This API is provided to dynamically change the speed and dulpex for MAC. - * - * @param base ENET peripheral base address. - * @param speed The speed of the RMII mode. - * @param duplex The duplex of the RMII mode. - */ -static inline void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex) -{ - uint32_t reg = base->MAC_CONFIG & ~(ENET_MAC_CONFIG_DM_MASK | ENET_MAC_CONFIG_FES_MASK); - reg |= ENET_MAC_CONFIG_DM(duplex) | ENET_MAC_CONFIG_FES(speed); - - base->MAC_CONFIG = reg; -} - -/*! - * @brief Sets the ENET SMI(serial management interface)- MII management interface. - * - * @param base ENET peripheral base address. - */ -void ENET_SetSMI(ENET_Type *base); - -/*! - * @brief Checks if the SMI is busy. - * - * @param base ENET peripheral base address. - * @return The status of MII Busy status. - */ -static inline bool ENET_IsSMIBusy(ENET_Type *base) -{ - return (base->MAC_MDIO_ADDR & ENET_MAC_MDIO_ADDR_MB_MASK) ? true : false; -} - -/*! - * @brief Reads data from the PHY register through SMI interface. - * - * @param base ENET peripheral base address. - * @return The data read from PHY - */ -static inline uint16_t ENET_ReadSMIData(ENET_Type *base) -{ - return (uint16_t)(base->MAC_MDIO_DATA & ENET_MAC_MDIO_DATA_MD_MASK); -} - -/*! - * @brief Starts an SMI read command. - * support both MDIO IEEE802.3 Clause 22 and clause 45. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param phyReg The PHY register. - */ -void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg); - -/*! - * @brief Starts a SMI write command. - * support both MDIO IEEE802.3 Clause 22 and clause 45. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param phyReg The PHY register. - * @param data The data written to PHY. - */ -void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data); -/* @} */ - -/*! - * @name Other basic operation - * @{ - */ - -/*! - * @brief Sets the ENET module Mac address. - * - * @param base ENET peripheral base address. - * @param macAddr The six-byte Mac address pointer. - * The pointer is allocated by application and input into the API. - */ -static inline void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr) -{ - assert(macAddr); - - /* Set Macaddr */ - base->MAC_ADDR_LOW = ((uint32_t)macAddr[3] << 24) | ((uint32_t)macAddr[2] << 16) | ((uint32_t)macAddr[1] << 8) | - ((uint32_t)macAddr[0]); - base->MAC_ADDR_HIGH = ((uint32_t)macAddr[5] << 8) | ((uint32_t)macAddr[4]); -} - -/*! - * @brief Gets the ENET module Mac address. - * - * @param base ENET peripheral base address. - * @param macAddr The six-byte Mac address pointer. - * The pointer is allocated by application and input into the API. - */ -void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr); - -/*! - * @brief Set the MAC to enter into power down mode. - * the remote power wake up frame and magic frame can wake up - * the ENET from the power down mode. - * - * @param base ENET peripheral base address. - * @param wakeFilter The wakeFilter provided to configure the wake up frame fitlter. - * Set the wakeFilter to NULL is not required. But if you have the filter requirement, - * please make sure the wakeFilter pointer shall be eight continous - * 32-bits configuration. - */ -void ENET_EnterPowerDown(ENET_Type *base, uint32_t *wakeFilter); - -/*! - * @brief Set the MAC to exit power down mode. - * Eixt from the power down mode and recover to noraml work mode. - * - * @param base ENET peripheral base address. - */ -static inline void ENET_ExitPowerDown(ENET_Type *base) -{ - /* Clear and status ans reset the power down. */ - base->MAC_PMT_CRTL_STAT &= ~ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK; - - /* Restore the tx which is disabled when enter power down mode. */ - base->DMA_CH[0].DMA_CHX_TX_CTRL |= ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK; - base->DMA_CH[1].DMA_CHX_TX_CTRL |= ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK; - base->MAC_CONFIG |= ENET_MAC_CONFIG_TE_MASK; -} - -/* @} */ - -/*! - * @name Interrupts. - * @{ - */ - -/*! - * @brief Enables the ENET DMA and MAC interrupts. - * - * This function enables the ENET interrupt according to the provided mask. The mask - * is a logical OR of enet_dma_interrupt_enable_t and enet_mac_interrupt_enable_t. - * For example, to enable the dma and mac interrupt, do the following. - * @code - * ENET_EnableInterrupts(ENET, kENET_DmaRx | kENET_DmaTx | kENET_MacPmt); - * @endcode - * - * @param base ENET peripheral base address. - * @param mask ENET interrupts to enable. This is a logical OR of both - * enumeration :: enet_dma_interrupt_enable_t and enet_mac_interrupt_enable_t. - */ -void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask); - -/*! - * @brief Disables the ENET DMA and MAC interrupts. - * - * This function disables the ENET interrupt according to the provided mask. The mask - * is a logical OR of enet_dma_interrupt_enable_t and enet_mac_interrupt_enable_t. - * For example, to disable the dma and mac interrupt, do the following. - * @code - * ENET_DisableInterrupts(ENET, kENET_DmaRx | kENET_DmaTx | kENET_MacPmt); - * @endcode - * - * @param base ENET peripheral base address. - * @param mask ENET interrupts to disables. This is a logical OR of both - * enumeration :: enet_dma_interrupt_enable_t and enet_mac_interrupt_enable_t. - */ -void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask); - -/*! - * @brief Gets the ENET DMA interrupt status flag. - * - * @param base ENET peripheral base address. - * @param channel The DMA Channel. Shall not be larger than ENET_RING_NUM_MAX. - * @return The event status of the interrupt source. This is the logical OR of members - * of the enumeration :: enet_dma_interrupt_enable_t. - */ -static inline uint32_t ENET_GetDmaInterruptStatus(ENET_Type *base, uint8_t channel) -{ - return base->DMA_CH[channel].DMA_CHX_STAT; -} - -/*! - * @brief Clear the ENET DMA interrupt status flag. - * - * @param base ENET peripheral base address. - * @param channel The DMA Channel. Shall not be larger than ENET_RING_NUM_MAX. - * @return The event status of the interrupt source. This is the logical OR of members - * of the enumeration :: enet_dma_interrupt_enable_t. - */ -static inline void ENET_ClearDmaInterruptStatus(ENET_Type *base, uint8_t channel, uint32_t mask) -{ - /* Clear the dam interrupt status bit in dma channel interrupt status register. */ - base->DMA_CH[channel].DMA_CHX_STAT = mask; -} - -/*! - * @brief Gets the ENET MAC interrupt status flag. - * - * @param base ENET peripheral base address. - * @return The event status of the interrupt source. - * Use the enum in enet_mac_interrupt_enable_t and right shift - * ENET_MACINT_ENUM_OFFSET to mask the returned value to get the - * exact interrupt status. - */ -static inline uint32_t ENET_GetMacInterruptStatus(ENET_Type *base) -{ - return base->MAC_INTR_STAT; -} - -/*! - * @brief Clears the ENET mac interrupt events status flag. - * - * This function clears enabled ENET interrupts according to the provided mask. The mask - * is a logical OR of enumeration members. See the @ref enet_mac_interrupt_enable_t. - * For example, to clear the TX frame interrupt and RX frame interrupt, do the following. - * @code - * ENET_ClearMacInterruptStatus(ENET, kENET_MacPmt); - * @endcode - * - * @param base ENET peripheral base address. - * @param mask ENET interrupt source to be cleared. - * This is the logical OR of members of the enumeration :: enet_mac_interrupt_enable_t. - */ -void ENET_ClearMacInterruptStatus(ENET_Type *base, uint32_t mask); - -/* @} */ - -/*! - * @name Functional operation. - * @{ - */ - -/*! - * @brief Get the tx descriptor DMA Own flag. - * - * @param txDesc The given tx descriptor. - * @retval True the dma own tx descriptor, false application own tx descriptor. - * - */ -static inline bool ENET_IsTxDescriptorDmaOwn(enet_tx_bd_struct_t *txDesc) -{ - return (txDesc->controlStat & ENET_TXDESCRIP_RD_OWN_MASK) ? true : false; -} - -/*! - * @brief Setup a given tx descriptor. - * This function is a low level functional API to setup or prepare - * a given tx descriptor. - * - * @param txDesc The given tx descriptor. - * @param buffer1 The first buffer address in the descriptor. - * @param bytes1 The bytes in the fist buffer. - * @param buffer2 The second buffer address in the descriptor. - * @param bytes1 The bytes in the second buffer. - * @param framelen The length of the frame to be transmitted. - * @param intEnable Interrupt enable flag. - * @param tsEnable The timestamp enable. - * @param flag The flag of this tx desciriptor, see "enet_desc_flag" . - * @param slotNum The slot num used for AV only. - * - * @note This must be called after all the ENET initilization. - * And should be called when the ENET receive/transmit is required. - * Transmit buffers are 'zero-copy' buffers, so the buffer must remain in - * memory until the packet has been fully transmitted. The buffers - * should be free or requeued in the transmit interrupt irq handler. - */ -void ENET_SetupTxDescriptor(enet_tx_bd_struct_t *txDesc, - void *buffer1, - uint32_t bytes1, - void *buffer2, - uint32_t bytes2, - uint32_t framelen, - bool intEnable, - bool tsEnable, - enet_desc_flag flag, - uint8_t slotNum); - -/*! - * @brief Update the tx descriptor tail pointer. - * This function is a low level functional API to update the - * the tx descriptor tail. - * This is called after you setup a new tx descriptor to update - * the tail pointer to make the new descritor accessable by DMA. - * - * @param base ENET peripheral base address. - * @param channel The tx DMA channel. - * @param txDescTailAddrAlign The new tx tail pointer address. - * - */ -static inline void ENET_UpdateTxDescriptorTail(ENET_Type *base, uint8_t channel, uint32_t txDescTailAddrAlign) -{ - base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR = txDescTailAddrAlign & ~ENET_ADDR_ALIGNMENT; -} - -/*! - * @brief Update the rx descriptor tail pointer. - * This function is a low level functional API to update the - * the rx descriptor tail. - * This is called after you setup a new rx descriptor to update - * the tail pointer to make the new descritor accessable by DMA - * and to anouse the rx poll command for DMA. - * - * @param base ENET peripheral base address. - * @param channel The rx DMA channel. - * @param rxDescTailAddrAlign The new rx tail pointer address. - * - */ -static inline void ENET_UpdateRxDescriptorTail(ENET_Type *base, uint8_t channel, uint32_t rxDescTailAddrAlign) -{ - base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = rxDescTailAddrAlign & ~ENET_ADDR_ALIGNMENT; -} - -/*! - * @brief Gets the context in the ENET rx descriptor. - * This function is a low level functional API to get the - * the status flag from a given rx descriptor. - * - * @param rxDesc The given rx descriptor. - * @retval The RDES3 regions for write-back format rx buffer descriptor. - * - * @note This must be called after all the ENET initilization. - * And should be called when the ENET receive/transmit is required. - */ -static inline uint32_t ENET_GetRxDescriptor(enet_rx_bd_struct_t *rxDesc) -{ - assert(rxDesc); - - return rxDesc->control; -} -/*! - * @brief Updates the buffers and the own status for a given rx descriptor. - * This function is a low level functional API to Updates the - * buffers and the own status for a given rx descriptor. - * - * @param rxDesc The given rx descriptor. - * @param buffer1 The first buffer address in the descriptor. - * @param buffer2 The second buffer address in the descriptor. - * @param intEnable Interrupt enable flag. - * @param doubleBuffEnable The double buffer enable flag. - * - * @note This must be called after all the ENET initilization. - * And should be called when the ENET receive/transmit is required. - */ -void ENET_UpdateRxDescriptor( - enet_rx_bd_struct_t *rxDesc, void *buffer1, void *buffer2, bool intEnable, bool doubleBuffEnable); - -/* @} */ - -/*! - * @name Transactional operation - * @{ - */ - -/*! - * @brief Create ENET Handler - * - * This is a transactional API and it's provided to store all datas which are needed - * during the whole transactional process. This API should not be used when you use - * functional APIs to do data tx/rx. This is funtion will store many data/flag for - * transactional use, so all configure API such as ENET_Init(), ENET_DescriptorInit(), - * ENET_EnableInterrupts() etc. - * - * @note as our transactional transmit API use the zero-copy transmit buffer. - * so there are two thing we emphasize here: - * 1. tx buffer free/requeue for application should be done in the tx - * interrupt handler. Please set callback: kENET_TxIntEvent with tx buffer free/requeue - * process APIs. - * 2. the tx interrupt is forced to open. - * - * @param base ENET peripheral base address. - * @param handle ENET handler. - * @param config ENET configuration. - * @param bufferConfig ENET buffer configuration. - * @param callback The callback function. - * @param userData The application data. - */ -void ENET_CreateHandler(ENET_Type *base, - enet_handle_t *handle, - enet_config_t *config, - enet_buffer_config_t *bufferConfig, - enet_callback_t callback, - void *userData); - -/*! -* @brief Gets the size of the read frame. -* This function gets a received frame size from the ENET buffer descriptors. -* @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. -* After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the -* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". -* -* @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. -* @param length The length of the valid frame received. -* @param channel The DMAC channel for the rx. -* @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame. -* @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data -* and NULL length to update the receive buffers. -* @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame -* should be called with the right data buffer and the captured data length input. -*/ -status_t ENET_GetRxFrameSize(ENET_Type *base, enet_handle_t *handle, uint32_t *length, uint8_t channel); - -/*! - * @brief Reads a frame from the ENET device. - * This function reads a frame from the ENET DMA descriptors. - * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer. - * For example use rx dma channel 0: - * @code - * uint32_t length; - * enet_handle_t g_handle; - * //Get the received frame size firstly. - * status = ENET_GetRxFrameSize(&g_handle, &length, 0); - * if (length != 0) - * { - * //Allocate memory here with the size of "length" - * uint8_t *data = memory allocate interface; - * if (!data) - * { - * ENET_ReadFrame(ENET, &g_handle, NULL, 0, 0); - * //Add the console warning log. - * } - * else - * { - * status = ENET_ReadFrame(ENET, &g_handle, data, length, 0); - * //Call stack input API to deliver the data to stack - * } - * } - * else if (status == kStatus_ENET_RxFrameError) - * { - * //Update the received buffer when a error frame is received. - * ENET_ReadFrame(ENET, &g_handle, NULL, 0, 0); - * } - * @endcode - * @param base ENET peripheral base address. - * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. - * @param data The data buffer provided by user to store the frame which memory size should be at least "length". - * @param length The size of the data buffer which is still the length of the received frame. - * @param channel The rx DMA channel. shall not be larger than 2. - * @return The execute status, successful or failure. - */ -status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint8_t channel); - -/*! - * @brief Transmits an ENET frame. - * @note The CRC is automatically appended to the data. Input the data - * to send without the CRC. - * - * @param base ENET peripheral base address. - * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. - * @param data The data buffer provided by user to be send. - * @param length The length of the data to be send. - * @retval kStatus_Success Send frame succeed. - * @retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. - * The transmit busy happens when the data send rate is over the MAC capacity. - * The waiting mechanism is recommended to be added after each call return with - * kStatus_ENET_TxFrameBusy. - */ -status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length); - -/*! - * @brief Reclaim tx descriptors. - * This function is used to update the tx descriptor status and - * store the tx timestamp when the 1588 feature is enabled. - * This is called by the transmit interupt IRQ handler after the - * complete of a frame transmission. - * - * @param base ENET peripheral base address. - * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. - * @param channel The tx DMA channnel. - * - */ -void ENET_ReclaimTxDescriptor(ENET_Type *base, enet_handle_t *handle, uint8_t channel); - -/*! - * @brief The ENET PMT IRQ handler. - * - * @param base ENET peripheral base address. - * @param handle The ENET handler pointer. - */ -void ENET_PMTIRQHandler(ENET_Type *base, enet_handle_t *handle); - -/*! - * @brief The ENET IRQ handler. - * - * @param base ENET peripheral base address. - * @param handle The ENET handler pointer. - */ -void ENET_IRQHandler(ENET_Type *base, enet_handle_t *handle); - -/* @} */ - -#ifdef ENET_PTP1588FEATURE_REQUIRED -/*! - * @name ENET Enhanced function operation - * @{ - */ - -/*! - * @brief Starts the ENET PTP 1588 Timer. - * This function is used to initialize the PTP timer. After the PTP starts, - * the PTP timer starts running. - * - * @param base ENET peripheral base address. - * @param ptpClkSrc The clock source of the PTP timer. - */ -void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc); - -/*! - * @brief Coreect the ENET PTP 1588 timer in coarse method. - * - * @param base ENET peripheral base address. - * @param operation The system time operation, refer to "enet_systime_op" - * @param second The correction second. - * @param nanosecond The correction nanosecond. - */ -void ENET_Ptp1588CorrectTimerInCoarse(ENET_Type *base, enet_systime_op operation, uint32_t second, uint32_t nanosecond); - -/*! - * @brief Coreect the ENET PTP 1588 timer in fine method. - * - * - * @param base ENET peripheral base address. - * @param addend The addend value to be set in the fine method - * @note Should take refer to the chapter "System time corretion" and - * see the description for the "fine correction method". - */ -static inline void ENET_Ptp1588CorrectTimerInFine(ENET_Type *base, uint32_t addend) -{ - /* Set the freqCompensation value. */ - base->MAC_SYS_TIMESTMP_ADDEND = addend; - base->MAC_TIMESTAMP_CTRL |= ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK; -} - -/*! - * @brief Get the ENET Time stamp current addend value. - * - * @param base ENET peripheral base address. - * @return The addend value. - */ -static inline uint32_t ENET_Ptp1588GetAddend(ENET_Type *base) -{ - return base->MAC_SYS_TIMESTMP_ADDEND; -} - -/*! - * @brief Gets the current ENET time from the PTP 1588 timer. - * - * @param base ENET peripheral base address. - * @param second The PTP 1588 system timer second. - * @param nanosecond The PTP 1588 system timer nanosecond. - * For the unit of the nanosecond is 1ns. so the nanosecond is the real nanosecond. - */ -void ENET_Ptp1588GetTimer(ENET_Type *base, uint64_t *second, uint32_t *nanosecond); - -/*! - * @brief Gets the time stamp of the received frame. - * - * This function is used for PTP stack to get the timestamp captured by the ENET driver. - * - * @param handle The ENET handler pointer.This is the same state pointer used in - * ENET_Init. - * @param ptpTimeData The special PTP timestamp data for search the receive timestamp. - * @retval kStatus_Success Get 1588 timestamp success. - * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. - * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. - */ -status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); - -/*! - * @brief Gets the time stamp of the transmit frame. - * - * This function is used for PTP stack to get the timestamp captured by the ENET driver. - * - * @param handle The ENET handler pointer.This is the same state pointer used in - * ENET_Init. - * @param ptpTimeData The special PTP timestamp data for search the receive timestamp. - * @retval kStatus_Success Get 1588 timestamp success. - * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. - * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. - */ -status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); -#endif /* ENET_PTP1588FEATURE_REQUIRED */ -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_ENET_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_flashiap.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_flashiap.c deleted file mode 100644 index 862fd2d227a..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_flashiap.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_flashiap.h" - -#define HZ_TO_KHZ_DIV 1000 - -/******************************************************************************* - * Code - ******************************************************************************/ - -static status_t translate_iap_status(uint32_t status) -{ - /* Translate IAP return code to sdk status code */ - if (status == kStatus_Success) - { - return status; - } - else - { - return MAKE_STATUS(kStatusGroup_FLASHIAP, status); - } -} - -status_t FLASHIAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector) -{ - uint32_t command[5], result[4]; - - command[0] = kIapCmd_FLASHIAP_PrepareSectorforWrite; - command[1] = startSector; - command[2] = endSector; - iap_entry(command, result); - - return translate_iap_status(result[0]); -} - -status_t FLASHIAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock) -{ - uint32_t command[5], result[4]; - - command[0] = kIapCmd_FLASHIAP_CopyRamToFlash; - command[1] = dstAddr; - command[2] = (uint32_t)srcAddr; - command[3] = numOfBytes; - command[4] = systemCoreClock / HZ_TO_KHZ_DIV; - iap_entry(command, result); - - return translate_iap_status(result[0]); -} - -status_t FLASHIAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock) -{ - uint32_t command[5], result[4]; - - command[0] = kIapCmd_FLASHIAP_EraseSector; - command[1] = startSector; - command[2] = endSector; - command[3] = systemCoreClock / HZ_TO_KHZ_DIV; - iap_entry(command, result); - - return translate_iap_status(result[0]); -} - -status_t FLASHIAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t systemCoreClock) -{ - uint32_t command[5], result[4]; - - command[0] = kIapCmd_FLASHIAP_ErasePage; - command[1] = startPage; - command[2] = endPage; - command[3] = systemCoreClock / HZ_TO_KHZ_DIV; - iap_entry(command, result); - - return translate_iap_status(result[0]); -} - -status_t FLASHIAP_BlankCheckSector(uint32_t startSector, uint32_t endSector) -{ - uint32_t command[5], result[4]; - - command[0] = kIapCmd_FLASHIAP_BlankCheckSector; - command[1] = startSector; - command[2] = endSector; - iap_entry(command, result); - - return translate_iap_status(result[0]); -} - -status_t FLASHIAP_Compare(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes) -{ - uint32_t command[5], result[4]; - - command[0] = kIapCmd_FLASHIAP_Compare; - command[1] = dstAddr; - command[2] = (uint32_t)srcAddr; - command[3] = numOfBytes; - iap_entry(command, result); - - return translate_iap_status(result[0]); -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_flashiap.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_flashiap.h deleted file mode 100644 index 3325ea7ce98..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_flashiap.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_FLASHIAP_H_ -#define _FSL_FLASHIAP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup flashiap_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_FLASHIAP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ - /*@}*/ - -/*! - * @brief Flashiap status codes. - */ -enum _flashiap_status -{ - kStatus_FLASHIAP_Success = kStatus_Success, /*!< Api is executed successfully */ - kStatus_FLASHIAP_InvalidCommand = MAKE_STATUS(kStatusGroup_FLASHIAP, 1U), /*!< Invalid command */ - kStatus_FLASHIAP_SrcAddrError = - MAKE_STATUS(kStatusGroup_FLASHIAP, 2U), /*!< Source address is not on word boundary */ - kStatus_FLASHIAP_DstAddrError = - MAKE_STATUS(kStatusGroup_FLASHIAP, 3U), /*!< Destination address is not on a correct boundary */ - kStatus_FLASHIAP_SrcAddrNotMapped = - MAKE_STATUS(kStatusGroup_FLASHIAP, 4U), /*!< Source address is not mapped in the memory map */ - kStatus_FLASHIAP_DstAddrNotMapped = - MAKE_STATUS(kStatusGroup_FLASHIAP, 5U), /*!< Destination address is not mapped in the memory map */ - kStatus_FLASHIAP_CountError = - MAKE_STATUS(kStatusGroup_FLASHIAP, 6U), /*!< Byte count is not multiple of 4 or is not a permitted value */ - kStatus_FLASHIAP_InvalidSector = - MAKE_STATUS(kStatusGroup_FLASHIAP, - 7), /*!< Sector number is invalid or end sector number is greater than start sector number */ - kStatus_FLASHIAP_SectorNotblank = MAKE_STATUS(kStatusGroup_FLASHIAP, 8U), /*!< One or more sectors are not blank */ - kStatus_FLASHIAP_NotPrepared = - MAKE_STATUS(kStatusGroup_FLASHIAP, 9U), /*!< Command to prepare sector for write operation was not executed */ - kStatus_FLASHIAP_CompareError = - MAKE_STATUS(kStatusGroup_FLASHIAP, 10U), /*!< Destination and source memory contents do not match */ - kStatus_FLASHIAP_Busy = - MAKE_STATUS(kStatusGroup_FLASHIAP, 11U), /*!< Flash programming hardware interface is busy */ - kStatus_FLASHIAP_ParamError = - MAKE_STATUS(kStatusGroup_FLASHIAP, 12U), /*!< Insufficient number of parameters or invalid parameter */ - kStatus_FLASHIAP_AddrError = MAKE_STATUS(kStatusGroup_FLASHIAP, 13U), /*!< Address is not on word boundary */ - kStatus_FLASHIAP_AddrNotMapped = - MAKE_STATUS(kStatusGroup_FLASHIAP, 14U), /*!< Address is not mapped in the memory map */ - kStatus_FLASHIAP_NoPower = MAKE_STATUS(kStatusGroup_FLASHIAP, 24U), /*!< Flash memory block is powered down */ - kStatus_FLASHIAP_NoClock = - MAKE_STATUS(kStatusGroup_FLASHIAP, 27U), /*!< Flash memory block or controller is not clocked */ -}; - -/*! - * @brief Flashiap command codes. - */ -enum _flashiap_commands -{ - kIapCmd_FLASHIAP_PrepareSectorforWrite = 50U, /*!< Prepare Sector for write */ - kIapCmd_FLASHIAP_CopyRamToFlash = 51U, /*!< Copy RAM to flash */ - kIapCmd_FLASHIAP_EraseSector = 52U, /*!< Erase Sector */ - kIapCmd_FLASHIAP_BlankCheckSector = 53U, /*!< Blank check sector */ - kIapCmd_FLASHIAP_ReadPartId = 54U, /*!< Read part id */ - kIapCmd_FLASHIAP_Read_BootromVersion = 55U, /*!< Read bootrom version */ - kIapCmd_FLASHIAP_Compare = 56U, /*!< Compare */ - kIapCmd_FLASHIAP_ReinvokeISP = 57U, /*!< Reinvoke ISP */ - kIapCmd_FLASHIAP_ReadUid = 58U, /*!< Read Uid isp */ - kIapCmd_FLASHIAP_ErasePage = 59U, /*!< Erase Page */ - kIapCmd_FLASHIAP_ReadMisr = 70U, /*!< Read Misr */ - kIapCmd_FLASHIAP_ReinvokeI2cSpiISP = 71U /*!< Reinvoke I2C/SPI isp */ -}; - -/*! @brief IAP_ENTRY API function type */ -typedef void (*IAP_ENTRY_T)(uint32_t cmd[5], uint32_t stat[4]); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief IAP_ENTRY API function type - * - * Wrapper for rom iap call - * - * @param cmd_param IAP command and relevant parameter array. - * @param status_result IAP status result array. - * - * @retval None. Status/Result is returned via status_result array. - */ -static inline void iap_entry(uint32_t *cmd_param, uint32_t *status_result) -{ - ((IAP_ENTRY_T)FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION)(cmd_param, status_result); -} - -/*! - * @brief Prepare sector for write operation - - * This function prepares sector(s) for write/erase operation. This function must be - * called before calling the FLASHIAP_CopyRamToFlash() or FLASHIAP_EraseSector() or - * FLASHIAP_ErasePage() function. The end sector must be greater than or equal to - * start sector number. - * - * @param startSector Start sector number. - * @param endSector End sector number. - * - * @retval #kStatus_FLASHIAP_Success Api was executed successfully. - * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. - * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. - * @retval #kStatus_FLASHIAP_InvalidSector Sector number is invalid or end sector number - * is greater than start sector number. - * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy. - */ -status_t FLASHIAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector); - -/*! - * @brief Copy RAM to flash. - - * This function programs the flash memory. Corresponding sectors must be prepared - * via FLASHIAP_PrepareSectorForWrite before calling calling this function. The addresses - * should be a 256 byte boundary and the number of bytes should be 256 | 512 | 1024 | 4096. - * - * @param dstAddr Destination flash address where data bytes are to be written. - * @param srcAddr Source ram address from where data bytes are to be read. - * @param numOfBytes Number of bytes to be written. - * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the - * rom IAP function. - * - * @retval #kStatus_FLASHIAP_Success Api was executed successfully. - * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. - * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. - * @retval #kStatus_FLASHIAP_SrcAddrError Source address is not on word boundary. - * @retval #kStatus_FLASHIAP_DstAddrError Destination address is not on a correct boundary. - * @retval #kStatus_FLASHIAP_SrcAddrNotMapped Source address is not mapped in the memory map. - * @retval #kStatus_FLASHIAP_DstAddrNotMapped Destination address is not mapped in the memory map. - * @retval #kStatus_FLASHIAP_CountError Byte count is not multiple of 4 or is not a permitted value. - * @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed. - * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy. - */ -status_t FLASHIAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock); - -/*! - * @brief Erase sector - - * This function erases sector(s). The end sector must be greater than or equal to - * start sector number. FLASHIAP_PrepareSectorForWrite must be called before - * calling this function. - * - * @param startSector Start sector number. - * @param endSector End sector number. - * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the - * rom IAP function. - * - * @retval #kStatus_FLASHIAP_Success Api was executed successfully. - * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. - * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. - * @retval #kStatus_FLASHIAP_InvalidSector Sector number is invalid or end sector number - * is greater than start sector number. - * @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed. - * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy. - */ -status_t FLASHIAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock); - -/*! - - * This function erases page(s). The end page must be greater than or equal to - * start page number. Corresponding sectors must be prepared via FLASHIAP_PrepareSectorForWrite - * before calling calling this function. - * - * @param startPage Start page number - * @param endPage End page number - * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the - * rom IAP function. - * - * @retval #kStatus_FLASHIAP_Success Api was executed successfully. - * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. - * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. - * @retval #kStatus_FLASHIAP_InvalidSector Page number is invalid or end page number - * is greater than start page number - * @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed. - * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy. - */ -status_t FLASHIAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t systemCoreClock); - -/*! - * @brief Blank check sector(s) - * - * Blank check single or multiples sectors of flash memory. The end sector must be greater than or equal to - * start sector number. It can be used to verify the sector eraseure after FLASHIAP_EraseSector call. - * - * @param startSector : Start sector number. Must be greater than or equal to start sector number - * @param endSector : End sector number - * @retval #kStatus_FLASHIAP_Success One or more sectors are in erased state. - * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. - * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. - * @retval #kStatus_FLASHIAP_SectorNotblank One or more sectors are not blank. - */ -status_t FLASHIAP_BlankCheckSector(uint32_t startSector, uint32_t endSector); - -/*! - * @brief Compare memory contents of flash with ram. - - * This function compares the contents of flash and ram. It can be used to verify the flash - * memory contents after FLASHIAP_CopyRamToFlash call. - * - * @param dstAddr Destination flash address. - * @param srcAddr Source ram address. - * @param numOfBytes Number of bytes to be compared. - * - * @retval #kStatus_FLASHIAP_Success Contents of flash and ram match. - * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. - * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. - * @retval #kStatus_FLASHIAP_AddrError Address is not on word boundary. - * @retval #kStatus_FLASHIAP_AddrNotMapped Address is not mapped in the memory map. - * @retval #kStatus_FLASHIAP_CountError Byte count is not multiple of 4 or is not a permitted value. - * @retval #kStatus_FLASHIAP_CompareError Destination and source memory contents do not match. - */ -status_t FLASHIAP_Compare(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_FLASHIAP_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_flexcomm.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_flexcomm.c deleted file mode 100644 index ffb240e0648..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_flexcomm.c +++ /dev/null @@ -1,240 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ -static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT]; - -/*! @brief Pointers to handles for each instance to provide context to interrupt routines */ -static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT]; - -/*! @brief Array to map FLEXCOMM instance number to IRQ number. */ -IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS; - -/*! @brief Array to map FLEXCOMM instance number to base address. */ -static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief IDs of clock for each FLEXCOMM module */ -static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* check whether flexcomm supports peripheral type */ -static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph) -{ - if (periph == FLEXCOMM_PERIPH_NONE) - { - return true; - } - else if ((periph >= FLEXCOMM_PERIPH_USART) && (periph <= FLEXCOMM_PERIPH_I2S_TX)) - { - return (base->PSELID & (uint32_t)(1 << ((uint32_t)periph + 3))) > 0 ? true : false; - } - else if (periph == FLEXCOMM_PERIPH_I2S_RX) - { - return (base->PSELID & (1 << 7)) > 0 ? true : false; - } - else - { - return false; - } -} - -/* Get the index corresponding to the FLEXCOMM */ -uint32_t FLEXCOMM_GetInstance(void *base) -{ - int i; - - for (i = 0; i < FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++) - { - if ((uint32_t)base == s_flexcommBaseAddrs[i]) - { - return i; - } - } - - assert(false); - return 0; -} - -/* Changes FLEXCOMM mode */ -status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock) -{ - /* Check whether peripheral type is present */ - if (!FLEXCOMM_PeripheralIsPresent(base, periph)) - { - return kStatus_OutOfRange; - } - - /* Flexcomm is locked to different peripheral type than expected */ - if ((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) && ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != periph)) - { - return kStatus_Fail; - } - - /* Check if we are asked to lock */ - if (lock) - { - base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK; - } - else - { - base->PSELID = (uint32_t)periph; - } - - return kStatus_Success; -} - -status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) -{ - int idx = FLEXCOMM_GetInstance(base); - - if (idx < 0) - { - return kStatus_InvalidArgument; - } - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the peripheral clock */ - CLOCK_EnableClock(s_flexcommClocks[idx]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Set the FLEXCOMM to given peripheral */ - return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0); -} - -void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(base); - - /* Clear handler first to avoid execution of the handler with wrong handle */ - s_flexcommIrqHandler[instance] = NULL; - s_flexcommHandle[instance] = handle; - s_flexcommIrqHandler[instance] = handler; -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(FLEXCOMM0) -void FLEXCOMM0_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[0]); - s_flexcommIrqHandler[0]((void *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]); -} -#endif - -#if defined(FLEXCOMM1) -void FLEXCOMM1_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[1]); - s_flexcommIrqHandler[1]((void *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]); -} -#endif - -#if defined(FLEXCOMM2) -void FLEXCOMM2_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[2]); - s_flexcommIrqHandler[2]((void *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]); -} -#endif - -#if defined(FLEXCOMM3) -void FLEXCOMM3_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[3]); - s_flexcommIrqHandler[3]((void *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]); -} -#endif - -#if defined(FLEXCOMM4) -void FLEXCOMM4_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[4]); - s_flexcommIrqHandler[4]((void *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]); -} - -#endif - -#if defined(FLEXCOMM5) -void FLEXCOMM5_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[5]); - s_flexcommIrqHandler[5]((void *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]); -} -#endif - -#if defined(FLEXCOMM6) -void FLEXCOMM6_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[6]); - s_flexcommIrqHandler[6]((void *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]); -} -#endif - -#if defined(FLEXCOMM7) -void FLEXCOMM7_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[7]); - s_flexcommIrqHandler[7]((void *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]); -} -#endif - -#if defined(FLEXCOMM8) -void FLEXCOMM8_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[8]); - s_flexcommIrqHandler[8]((void *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]); -} -#endif - -#if defined(FLEXCOMM9) -void FLEXCOMM9_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[9]); - s_flexcommIrqHandler[9]((void *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]); -} -#endif diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_flexcomm.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_flexcomm.h deleted file mode 100644 index 3e305dc6202..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_flexcomm.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_FLEXCOMM_H_ -#define _FSL_FLEXCOMM_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup flexcomm_driver - * @{ - */ - -/*! @brief FLEXCOMM peripheral modes. */ -typedef enum -{ - FLEXCOMM_PERIPH_NONE, /*!< No peripheral */ - FLEXCOMM_PERIPH_USART, /*!< USART peripheral */ - FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */ - FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */ - FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */ - FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */ -} FLEXCOMM_PERIPH_T; - -/*! @brief Typedef for interrupt handler. */ -typedef void (*flexcomm_irq_handler_t)(void *base, void *handle); - -/*! @brief Array with IRQ number for each FLEXCOMM module. */ -extern IRQn_Type const kFlexcommIrqs[]; - -/*! @brief Returns instance number for FLEXCOMM module with given base address. */ -uint32_t FLEXCOMM_GetInstance(void *base); - -/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ -status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph); - -/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM - * mode */ -void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle); - -/*@}*/ - -#endif /* _FSL_FLEXCOMM_H_*/ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_fmc.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_fmc.c deleted file mode 100644 index c985d323db9..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_fmc.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_fmc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -void FMC_GetDefaultConfig(fmc_config_t *config) -{ - config->waitStates = 0x05; -} - -void FMC_Init(FMC_Type *base, fmc_config_t *config) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* enable clock to FMC */ - CLOCK_EnableClock(kCLOCK_Fmc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Set control register, FS_RD0 = 0, FS_RD1 = 1. */ - base->FCTR &= ~(FMC_FCTR_FS_RD0_MASK | FMC_FCTR_FS_RD1_MASK); - base->FCTR |= FMC_FCTR_FS_RD1_MASK; - - /* Set wait state, same as FLASHTIM in SYSCON->FLASHCFG register. */ - base->FBWST &= ~FMC_FBWST_WAITSTATES_MASK; - base->FBWST |= config->waitStates; -} - -void FMC_Denit(FMC_Type *base) -{ - /* Reset FMC module */ - RESET_PeripheralReset(kFMC_RST_SHIFT_RSTn); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* enable clock to FMC */ - CLOCK_DisableClock(kCLOCK_Fmc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void FMC_GenerateFlashSignature(FMC_Type *base, - uint32_t startAddress, - uint32_t length, - fmc_flash_signature_t *flashSignature) -{ - uint32_t stopAddress; - - /* Clear generation done flag. */ - base->FMSTATCLR = kFMC_SignatureGenerationDoneFlag; - - /* Calculate flash stop address */ - stopAddress = ((startAddress + length - 1) >> 4) & FMC_FMSSTOP_STOP_MASK; - - /* Calculate flash start address. */ - startAddress = (startAddress >> 4) & FMC_FMSSTART_START_MASK; - - /* Start flash signature generation. */ - base->FMSSTART = startAddress; - base->FMSSTOP = stopAddress; - - base->FMSSTOP |= FMC_FMSSTOP_SIG_START_MASK; - - /* Wait for signature done. */ - while ((base->FMSTAT & kFMC_SignatureGenerationDoneFlag) != kFMC_SignatureGenerationDoneFlag) - { - } - - /* Clear generation done flag. */ - base->FMSTATCLR = kFMC_SignatureGenerationDoneFlag; - - /* Get the generated flash signature. */ - flashSignature->word0 = base->FMSW[0]; - flashSignature->word1 = base->FMSW[1]; - flashSignature->word2 = base->FMSW[2]; - flashSignature->word3 = base->FMSW[3]; - - return; -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_fmc.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_fmc.h deleted file mode 100644 index 8c5ccd4bebc..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_fmc.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_FMC_H_ -#define _FSL_FMC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup fmc - * @{ - */ - -/****************************************************************************** - * Definitions. - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Driver version 2.0.0. */ -#define FSL_FMC_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U)) -/*@}*/ - -/*! - * @addtogroup fmc_driver - * @{ - */ - -/*! - * @brief fmc peripheral flag. - * - */ -enum _fmc_flags -{ - kFMC_SignatureGenerationDoneFlag = FMC_FMSTAT_SIG_DONE_MASK, /*!< Flash signature generation done. */ -}; - -/*! @brief Defines the generated 128-bit signature. */ -typedef struct _fmc_flash_signature -{ - uint32_t word0; /* Signature bits [31:0]. */ - uint32_t word1; /* Signature bits [63:32]. */ - uint32_t word2; /* Signature bits [95:64]. */ - uint32_t word3; /* Signature bits [127:96]. */ -} fmc_flash_signature_t; - -/*! @brief fmc config structure. */ -typedef struct _fmc_config -{ - uint8_t waitStates; /* flash timing value for flash signature generation. */ -} fmc_config_t; - -/*! @} */ - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize FMC module. - * - * This function initialize FMC module with user configuration - * - * @param base The FMC peripheral base address. - * @param config pointer to user configuration structure. - */ -void FMC_Init(FMC_Type *base, fmc_config_t *config); - -/*! - * @brief Deinit FMC module. - * - * This function De-initialize FMC module. - * - * @param base The FMC peripheral base address. - */ -void FMC_Deinit(FMC_Type *base); - -/*! - * @brief Provides default configuration for fmc module. - * - * This function provides default configuration for fmc module, the default wait states value is - * 5. - * - * @param config pointer to user configuration structure. - */ -void FMC_GetDefaultConfig(fmc_config_t *config); - -/*! - * @brief Generate hardware flash signature. - * - * This function generates hardware flash signature for specified address range. - * - * @note This function needs to be excuted out of flash memory. - * @param base The FMC peripheral base address. - * @param startAddress Flash start address for signature generation. - * @param length Length of address range. - * @param flashSignature Pointer which stores the generated flash signarue. - */ -void FMC_GenerateFlashSignature(FMC_Type *base, - uint32_t startAddress, - uint32_t length, - fmc_flash_signature_t *flashSignature); - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_fmeas.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_fmeas.c deleted file mode 100644 index 6e6e7c0c663..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_fmeas.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_fmeas.h" - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @brief Target clock counter value. - * According to user manual, 2 has to be subtracted from captured value (CAPVAL). */ -#define TARGET_CLOCK_COUNT(base) \ - ((uint32_t)( \ - ((((SYSCON_Type *)base)->FREQMECTRL & SYSCON_FREQMECTRL_CAPVAL_MASK) >> SYSCON_FREQMECTRL_CAPVAL_SHIFT) - 2)) - -/*! @brief Reference clock counter value. */ -#define REFERENCE_CLOCK_COUNT ((uint32_t)((SYSCON_FREQMECTRL_CAPVAL_MASK >> SYSCON_FREQMECTRL_CAPVAL_SHIFT) + 1)) - -/******************************************************************************* - * Code - ******************************************************************************/ - -uint32_t FMEAS_GetFrequency(SYSCON_Type *base, uint32_t refClockRate) -{ - uint32_t targetClockCount = TARGET_CLOCK_COUNT(base); - uint64_t clkrate = 0; - - if (targetClockCount > 0) - { - clkrate = (((uint64_t)targetClockCount) * (uint64_t)refClockRate) / REFERENCE_CLOCK_COUNT; - } - - return (uint32_t)clkrate; -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_fmeas.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_fmeas.h deleted file mode 100644 index 354f513e972..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_fmeas.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_FMEAS_H_ -#define _FSL_FMEAS_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup fmeas - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Defines LPC Frequency Measure driver version 2.0.0. - * - * Change log: - * - Version 2.0.0 - * - initial version - */ -#define FSL_FMEAS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name FMEAS Functional Operation - * @{ - */ - -/*! - * @brief Starts a frequency measurement cycle. - * - * @param base : SYSCON peripheral base address. - */ -static inline void FMEAS_StartMeasure(SYSCON_Type *base) -{ - base->FREQMECTRL = 0; - base->FREQMECTRL = (1UL << 31); -} - -/*! - * @brief Indicates when a frequency measurement cycle is complete. - * - * @param base : SYSCON peripheral base address. - * @return true if a measurement cycle is active, otherwise false. - */ -static inline bool FMEAS_IsMeasureComplete(SYSCON_Type *base) -{ - return (bool)((base->FREQMECTRL & (1UL << 31)) == 0); -} - -/*! - * @brief Returns the computed value for a frequency measurement cycle - * - * @param base : SYSCON peripheral base address. - * @param refClockRate : Reference clock rate used during the frequency measurement cycle. - * - * @return Frequency in Hz. - */ -uint32_t FMEAS_GetFrequency(SYSCON_Type *base, uint32_t refClockRate); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_FMEAS_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_gint.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_gint.c deleted file mode 100644 index ac7c615df8c..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_gint.c +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_gint.h" - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to GINT bases for each instance. */ -static GINT_Type *const s_gintBases[FSL_FEATURE_SOC_GINT_COUNT] = GINT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Clocks for each instance. */ -static const clock_ip_name_t s_gintClocks[FSL_FEATURE_SOC_GINT_COUNT] = GINT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Resets for each instance. */ -static const reset_ip_name_t s_gintResets[FSL_FEATURE_SOC_GINT_COUNT] = GINT_RSTS; - -/* @brief Irq number for each instance */ -static const IRQn_Type s_gintIRQ[FSL_FEATURE_SOC_GINT_COUNT] = GINT_IRQS; - -/*! @brief Callback function array for GINT(s). */ -static gint_cb_t s_gintCallback[FSL_FEATURE_SOC_GINT_COUNT]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t GINT_GetInstance(GINT_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_gintBases); instance++) - { - if (s_gintBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_gintBases)); - - return instance; -} - -void GINT_Init(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - s_gintCallback[instance] = NULL; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the peripheral clock */ - CLOCK_EnableClock(s_gintClocks[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the peripheral */ - RESET_PeripheralReset(s_gintResets[instance]); -} - -void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - base->CTRL = (GINT_CTRL_COMB(comb) | GINT_CTRL_TRIG(trig)); - - /* Save callback pointer */ - s_gintCallback[instance] = callback; -} - -void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - *comb = (gint_comb_t)((base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT); - *trig = (gint_trig_t)((base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT); - *callback = s_gintCallback[instance]; -} - -void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask) -{ - base->PORT_POL[port] = polarityMask; - base->PORT_ENA[port] = enableMask; -} - -void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask) -{ - *polarityMask = base->PORT_POL[port]; - *enableMask = base->PORT_ENA[port]; -} - -void GINT_EnableCallback(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - /* If GINT is configured in "AND" mode a spurious interrupt is generated. - Clear status and pending interrupt before enabling the irq in NVIC. */ - GINT_ClrStatus(base); - NVIC_ClearPendingIRQ(s_gintIRQ[instance]); - EnableIRQ(s_gintIRQ[instance]); -} - -void GINT_DisableCallback(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - DisableIRQ(s_gintIRQ[instance]); - GINT_ClrStatus(base); - NVIC_ClearPendingIRQ(s_gintIRQ[instance]); -} - -void GINT_Deinit(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - /* Cleanup */ - GINT_DisableCallback(base); - s_gintCallback[instance] = NULL; - - /* Reset the peripheral */ - RESET_PeripheralReset(s_gintResets[instance]); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the peripheral clock */ - CLOCK_DisableClock(s_gintClocks[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(GINT0) -void GINT0_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[0]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[0] != NULL) - { - s_gintCallback[0](); - } -} -#endif - -#if defined(GINT1) -void GINT1_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[1]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[1] != NULL) - { - s_gintCallback[1](); - } -} -#endif - -#if defined(GINT2) -void GINT2_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[2]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[2] != NULL) - { - s_gintCallback[2](); - } -} -#endif - -#if defined(GINT3) -void GINT3_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[3]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[3] != NULL) - { - s_gintCallback[3](); - } -} -#endif - -#if defined(GINT4) -void GINT4_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[4]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[4] != NULL) - { - s_gintCallback[4](); - } -} -#endif - -#if defined(GINT5) -void GINT5_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[5]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[5] != NULL) - { - s_gintCallback[5](); - } -} -#endif - -#if defined(GINT6) -void GINT6_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[6]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[6] != NULL) - { - s_gintCallback[6](); - } -} -#endif - -#if defined(GINT7) -void GINT7_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[7]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[7] != NULL) - { - s_gintCallback[7](); - } -} -#endif diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_gint.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_gint.h deleted file mode 100644 index 499536c4ae3..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_gint.h +++ /dev/null @@ -1,244 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_GINT_H_ -#define _FSL_GINT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup gint_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ -/*@}*/ - -/*! @brief GINT combine inputs type */ -typedef enum _gint_comb -{ - kGINT_CombineOr = 0U, /*!< A grouped interrupt is generated when any one of the enabled inputs is active */ - kGINT_CombineAnd = 1U /*!< A grouped interrupt is generated when all enabled inputs are active */ -} gint_comb_t; - -/*! @brief GINT trigger type */ -typedef enum _gint_trig -{ - kGINT_TrigEdge = 0U, /*!< Edge triggered based on polarity */ - kGINT_TrigLevel = 1U /*!< Level triggered based on polarity */ -} gint_trig_t; - -/* @brief GINT port type */ -typedef enum _gint_port -{ - kGINT_Port0 = 0U, - kGINT_Port1 = 1U, -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 2U) - kGINT_Port2 = 2U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 3U) - kGINT_Port3 = 3U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 4U) - kGINT_Port4 = 4U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 5U) - kGINT_Port5 = 5U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 6U) - kGINT_Port6 = 6U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 7U) - kGINT_Port7 = 7U, -#endif -} gint_port_t; - -/*! @brief GINT Callback function. */ -typedef void (*gint_cb_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize GINT peripheral. - - * This function initializes the GINT peripheral and enables the clock. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_Init(GINT_Type *base); - -/*! - * @brief Setup GINT peripheral control parameters. - - * This function sets the control parameters of GINT peripheral. - * - * @param base Base address of the GINT peripheral. - * @param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. - * @param trig Controls if the enabled inputs are level or edge sensitive based on polarity. - * @param callback This function is called when configured group interrupt is generated. - * - * @retval None. - */ -void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback); - -/*! - * @brief Get GINT peripheral control parameters. - - * This function returns the control parameters of GINT peripheral. - * - * @param base Base address of the GINT peripheral. - * @param comb Pointer to store combine input value. - * @param trig Pointer to store trigger value. - * @param callback Pointer to store callback function. - * - * @retval None. - */ -void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback); - -/*! - * @brief Configure GINT peripheral pins. - - * This function enables and controls the polarity of enabled pin(s) of a given port. - * - * @param base Base address of the GINT peripheral. - * @param port Port number. - * @param polarityMask Each bit position selects the polarity of the corresponding enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * @param enableMask Each bit position selects if the corresponding pin is enabled or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * @retval None. - */ -void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask); - -/*! - * @brief Get GINT peripheral pin configuration. - - * This function returns the pin configuration of a given port. - * - * @param base Base address of the GINT peripheral. - * @param port Port number. - * @param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding - enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * @param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled - or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * @retval None. - */ -void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask); - -/*! - * @brief Enable callback. - - * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_EnableCallback(GINT_Type *base); - -/*! - * @brief Disable callback. - - * This function disables the interrupt for the selected GINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * @param base Base address of the peripheral. - * - * @retval None. - */ -void GINT_DisableCallback(GINT_Type *base); - -/*! - * @brief Clear GINT status. - - * This function clears the GINT status bit. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -static inline void GINT_ClrStatus(GINT_Type *base) -{ - base->CTRL |= GINT_CTRL_INT_MASK; -} - -/*! - * @brief Get GINT status. - - * This function returns the GINT status. - * - * @param base Base address of the GINT peripheral. - * - * @retval status = 0 No group interrupt request. = 1 Group interrupt request active. - */ -static inline uint32_t GINT_GetStatus(GINT_Type *base) -{ - return (base->CTRL & GINT_CTRL_INT_MASK); -} - -/*! - * @brief Deinitialize GINT peripheral. - - * This function disables the GINT clock. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_Deinit(GINT_Type *base); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_GINT_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_gpio.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_gpio.c deleted file mode 100644 index 3b70fb467ba..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_gpio.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_gpio.h" - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* -* Prototypes -************ ******************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) -{ - if (config->pinDirection == kGPIO_DigitalInput) - { - base->DIR[port] &= ~(1U << pin); - } - else - { - /* Set default output value */ - if (config->outputLogic == 0U) - { - base->CLR[port] = (1U << pin); - } - else - { - base->SET[port] = (1U << pin); - } - /* Set pin direction */ - base->DIR[port] |= 1U << pin; - } -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_gpio.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_gpio.h deleted file mode 100644 index f92b60f3326..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_gpio.h +++ /dev/null @@ -1,250 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _LPC_GPIO_H_ -#define _LPC_GPIO_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_gpio - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPC GPIO driver version 2.0.0. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @brief LPC GPIO direction definition */ -typedef enum _gpio_pin_direction -{ - kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ - kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ -} gpio_pin_direction_t; - -/*! - * @brief The GPIO pin configuration structure. - * - * Every pin can only be configured as either output pin or input pin at a time. - * If configured as a input pin, then leave the outputConfig unused. - */ -typedef struct _gpio_pin_config -{ - gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ - /* Output configurations, please ignore if configured as a input one */ - uint8_t outputLogic; /*!< Set default output logic, no use in input */ -} gpio_pin_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @name GPIO Configuration */ -/*@{*/ - -/*! - * @brief Initializes a GPIO pin used by the board. - * - * To initialize the GPIO, define a pin configuration, either input or output, in the user file. - * Then, call the GPIO_PinInit() function. - * - * This is an example to define an input pin or output pin configuration: - * @code - * // Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * //Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * @endcode - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @param config GPIO pin configuration pointer - */ -void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config); - -/*@}*/ - -/*! @name GPIO Output Operations */ -/*@{*/ - -/*! - * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @param output GPIO pin output logic level. - * - 0: corresponding pin output low-logic level. - * - 1: corresponding pin output high-logic level. - */ -static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) -{ - base->B[port][pin] = output; -} -/*@}*/ -/*! @name GPIO Input Operations */ -/*@{*/ - -/*! - * @brief Reads the current input value of the GPIO PIN. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @retval GPIO port input value - * - 0: corresponding pin input low-logic level. - * - 1: corresponding pin input high-logic level. - */ -static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t port, uint32_t pin) -{ - return (uint32_t)base->B[port][pin]; -} -/*@}*/ - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 1. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->SET[port] = mask; -} - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 0. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->CLR[port] = mask; -} - -/*! - * @brief Reverses current output logic of the multiple GPIO pins. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->NOT[port] = mask; -} -/*@}*/ - -/*! - * @brief Reads the current input value of the whole GPIO port. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - */ -static inline uint32_t GPIO_ReadPinsInput(GPIO_Type *base, uint32_t port) -{ - return (uint32_t)base->PIN[port]; -} - -/*@}*/ -/*! @name GPIO Mask Operations */ -/*@{*/ - -/*! - * @brief Sets port mask, 0 - enable pin, 1 - disable pin. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_SetPortMask(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->MASK[port] = mask; -} - -/*! - * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param output GPIO port output value. - */ -static inline void GPIO_WriteMPort(GPIO_Type *base, uint32_t port, uint32_t output) -{ - base->MPIN[port] = output; -} - -/*! - * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be - * affected. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @retval masked GPIO port value - */ -static inline uint32_t GPIO_ReadMPort(GPIO_Type *base, uint32_t port) -{ - return (uint32_t)base->MPIN[port]; -} - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* _LPC_GPIO_H_*/ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2c.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2c.c deleted file mode 100644 index ad519e41080..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2c.c +++ /dev/null @@ -1,1398 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_i2c.h" -#include "fsl_flexcomm.h" -#include -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Common sets of flags used by the driver. */ -enum _i2c_flag_constants -{ - kI2C_MasterIrqFlags = I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK, - kI2C_SlaveIrqFlags = I2C_INTSTAT_SLVPENDING_MASK | I2C_INTSTAT_SLVDESEL_MASK, -}; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); -static void I2C_SlaveInternalStateMachineReset(I2C_Type *base); -static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal); -static uint32_t I2C_SlavePollPending(I2C_Type *base); -static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event); -static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle); -static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, - i2c_slave_handle_t *handle, - const void *txData, - size_t txSize, - void *rxData, - size_t rxSize, - uint32_t eventMask); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map i2c instance number to base address. */ -static const uint32_t s_i2cBaseAddrs[FSL_FEATURE_SOC_I2C_COUNT] = I2C_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_i2cIRQ[] = I2C_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * @brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * @param base The I2C peripheral base address. - * @return I2C instance number starting from 0. - */ -uint32_t I2C_GetInstance(I2C_Type *base) -{ - int i; - for (i = 0; i < FSL_FEATURE_SOC_I2C_COUNT; i++) - { - if ((uint32_t)base == s_i2cBaseAddrs[i]) - { - return i; - } - } - assert(false); - return 0; -} - -void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) -{ - masterConfig->enableMaster = true; - masterConfig->baudRate_Bps = 100000U; - masterConfig->enableTimeout = false; -} - -void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) -{ - FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); - I2C_MasterEnable(base, masterConfig->enableMaster); - I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); -} - -void I2C_MasterDeinit(I2C_Type *base) -{ - I2C_MasterEnable(base, false); -} - -void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) -{ - uint32_t scl, divider; - uint32_t best_scl, best_div; - uint32_t err, best_err; - - best_err = 0; - - for (scl = 9; scl >= 2; scl--) - { - /* calculated ideal divider value for given scl */ - divider = srcClock_Hz / (baudRate_Bps * scl * 2u); - - /* adjust it if it is out of range */ - divider = (divider > 0x10000u) ? 0x10000 : divider; - - /* calculate error */ - err = srcClock_Hz - (baudRate_Bps * scl * 2u * divider); - if ((err < best_err) || (best_err == 0)) - { - best_div = divider; - best_scl = scl; - best_err = err; - } - - if ((err == 0) || (divider >= 0x10000u)) - { - /* either exact value was found - or divider is at its max (it would even greater in the next iteration for sure) */ - break; - } - } - - base->CLKDIV = I2C_CLKDIV_DIVVAL(best_div - 1); - base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl - 2u) | I2C_MSTTIME_MSTSCLHIGH(best_scl - 2u); -} - -static uint32_t I2C_PendingStatusWait(I2C_Type *base) -{ - uint32_t status; - - do - { - status = I2C_GetStatusFlags(base); - } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); - - /* Clear controller state. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - return status; -} - -status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) -{ - I2C_PendingStatusWait(base); - - /* Write Address and RW bit to data register */ - base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1u); - /* Start the transfer */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - - return kStatus_Success; -} - -status_t I2C_MasterStop(I2C_Type *base) -{ - I2C_PendingStatusWait(base); - - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - return kStatus_Success; -} - -status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags) -{ - uint32_t status; - uint32_t master_state; - status_t err; - - const uint8_t *buf = (const uint8_t *)(uintptr_t)txBuff; - - assert(txBuff); - - err = kStatus_Success; - while (txSize) - { - status = I2C_PendingStatusWait(base); - - if (status & I2C_STAT_MSTARBLOSS_MASK) - { - return kStatus_I2C_ArbitrationLost; - } - - if (status & I2C_STAT_MSTSTSTPERR_MASK) - { - return kStatus_I2C_StartStopError; - } - - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - switch (master_state) - { - case I2C_STAT_MSTCODE_TXREADY: - /* ready to send next byte */ - base->MSTDAT = *buf++; - txSize--; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - break; - - case I2C_STAT_MSTCODE_NACKADR: - case I2C_STAT_MSTCODE_NACKDAT: - /* slave nacked the last byte */ - err = kStatus_I2C_Nak; - break; - - default: - /* unexpected state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - if (err != kStatus_Success) - { - return err; - } - } - - status = I2C_PendingStatusWait(base); - - if ((status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK)) == 0) - { - if (!(flags & kI2C_TransferNoStopFlag)) - { - /* Initiate stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - status = I2C_PendingStatusWait(base); - } - } - - if (status & I2C_STAT_MSTARBLOSS_MASK) - { - return kStatus_I2C_ArbitrationLost; - } - - if (status & I2C_STAT_MSTSTSTPERR_MASK) - { - return kStatus_I2C_StartStopError; - } - - return kStatus_Success; -} - -status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags) -{ - uint32_t status = 0; - uint32_t master_state; - status_t err; - - uint8_t *buf = (uint8_t *)(rxBuff); - - assert(rxBuff); - - err = kStatus_Success; - while (rxSize) - { - status = I2C_PendingStatusWait(base); - - if (status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK)) - { - break; - } - - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - switch (master_state) - { - case I2C_STAT_MSTCODE_RXREADY: - /* ready to send next byte */ - *(buf++) = base->MSTDAT; - if (--rxSize) - { - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - } - else - { - if ((flags & kI2C_TransferNoStopFlag) == 0) - { - /* initiate NAK and stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - status = I2C_PendingStatusWait(base); - } - } - break; - - case I2C_STAT_MSTCODE_NACKADR: - case I2C_STAT_MSTCODE_NACKDAT: - /* slave nacked the last byte */ - err = kStatus_I2C_Nak; - break; - - default: - /* unexpected state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - if (err != kStatus_Success) - { - return err; - } - } - - if (status & I2C_STAT_MSTARBLOSS_MASK) - { - return kStatus_I2C_ArbitrationLost; - } - - if (status & I2C_STAT_MSTSTSTPERR_MASK) - { - return kStatus_I2C_StartStopError; - } - - return kStatus_Success; -} - -status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) -{ - status_t result = kStatus_Success; - uint32_t subaddress; - uint8_t subaddrBuf[4]; - int i; - - assert(xfer); - - /* If repeated start is requested, send repeated start. */ - if (!(xfer->flags & kI2C_TransferNoStartFlag)) - { - if (xfer->subaddressSize) - { - result = I2C_MasterStart(base, xfer->slaveAddress, kI2C_Write); - if (result == kStatus_Success) - { - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = xfer->subaddressSize - 1; i >= 0; i--) - { - subaddrBuf[i] = subaddress & 0xff; - subaddress >>= 8; - } - /* Send subaddress. */ - result = I2C_MasterWriteBlocking(base, subaddrBuf, xfer->subaddressSize, kI2C_TransferNoStopFlag); - if ((result == kStatus_Success) && (xfer->direction == kI2C_Read)) - { - result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction); - } - } - } - else if (xfer->flags & kI2C_TransferRepeatedStartFlag) - { - result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction); - } - else - { - result = I2C_MasterStart(base, xfer->slaveAddress, xfer->direction); - } - } - - if (result == kStatus_Success) - { - if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0)) - { - /* Transmit data. */ - result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); - } - else - { - if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0)) - { - /* Receive Data. */ - result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags); - } - } - } - - if (result == kStatus_I2C_Nak) - { - I2C_MasterStop(base); - } - - return result; -} - -void I2C_MasterTransferCreateHandle(I2C_Type *base, - i2c_master_handle_t *handle, - i2c_master_transfer_callback_t callback, - void *userData) -{ - uint32_t instance; - - assert(handle); - - /* Clear out the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Save base and instance. */ - handle->completionCallback = callback; - handle->userData = userData; - - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2C_MasterTransferHandleIRQ, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); - EnableIRQ(s_i2cIRQ[instance]); -} - -status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) -{ - status_t result; - - assert(handle); - assert(xfer); - assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); - - /* Return busy if another transaction is in progress. */ - if (handle->state != kIdleState) - { - return kStatus_I2C_Busy; - } - - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); - - /* Prepare transfer state machine. */ - result = I2C_InitTransferStateMachine(base, handle, xfer); - - /* Clear error flags. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Enable I2C internal IRQ sources. */ - I2C_EnableInterrupts(base, kI2C_MasterIrqFlags); - - return result; -} - -status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state == kIdleState) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* There is no necessity to disable interrupts as we read a single integer value */ - *count = handle->transferCount; - return kStatus_Success; -} - -void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) -{ - uint32_t status; - uint32_t master_state; - - if (handle->state != kIdleState) - { - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); - - /* Wait until module is ready */ - status = I2C_PendingStatusWait(base); - - /* Get the state of the I2C module */ - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if (master_state != I2C_STAT_MSTCODE_IDLE) - { - /* Send a stop command to finalize the transfer. */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - - /* Wait until the STOP is completed */ - I2C_PendingStatusWait(base); - } - - /* Reset handle. */ - handle->state = kIdleState; - } -} - -/*! - * @brief Prepares the transfer state machine and fills in the command buffer. - * @param handle Master nonblocking driver handle. - */ -static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) -{ - struct _i2c_master_transfer *transfer; - - handle->transfer = *xfer; - transfer = &(handle->transfer); - - handle->transferCount = 0; - handle->remainingBytes = transfer->dataSize; - handle->buf = (uint8_t *)transfer->data; - handle->remainingSubaddr = 0; - - if (transfer->flags & kI2C_TransferNoStartFlag) - { - /* Start condition shall be ommited, switch directly to next phase */ - if (transfer->dataSize == 0) - { - handle->state = kStopState; - } - else if (handle->transfer.direction == kI2C_Write) - { - handle->state = kTransmitDataState; - } - else if (handle->transfer.direction == kI2C_Read) - { - handle->state = kReceiveDataState; - } - else - { - return kStatus_I2C_InvalidParameter; - } - } - else - { - if (transfer->subaddressSize != 0) - { - int i; - uint32_t subaddress; - - if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) - { - return kStatus_I2C_InvalidParameter; - } - - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = xfer->subaddressSize - 1; i >= 0; i--) - { - handle->subaddrBuf[i] = subaddress & 0xff; - subaddress >>= 8; - } - handle->remainingSubaddr = transfer->subaddressSize; - } - handle->state = kStartState; - } - - return kStatus_Success; -} - -/*! - * @brief Execute states until FIFOs are exhausted. - * @param handle Master nonblocking driver handle. - * @param[out] isDone Set to true if the transfer has completed. - * @retval #kStatus_Success - * @retval #kStatus_I2C_ArbitrationLost - * @retval #kStatus_I2C_Nak - */ -static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) -{ - uint32_t status; - uint32_t master_state; - struct _i2c_master_transfer *transfer; - status_t err; - - transfer = &(handle->transfer); - - *isDone = false; - - status = I2C_GetStatusFlags(base); - - if (status & I2C_STAT_MSTARBLOSS_MASK) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); - return kStatus_I2C_ArbitrationLost; - } - - if (status & I2C_STAT_MSTSTSTPERR_MASK) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); - return kStatus_I2C_StartStopError; - } - - if ((status & I2C_STAT_MSTPENDING_MASK) == 0) - { - return kStatus_I2C_Busy; - } - - /* Get the state of the I2C module */ - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT)) - { - /* Slave NACKed last byte, issue stop and return error */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; - return kStatus_I2C_Nak; - } - - err = kStatus_Success; - switch (handle->state) - { - case kStartState: - if (handle->remainingSubaddr) - { - /* Subaddress takes precedence over the data transfer, direction is always "write" in this case */ - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = kTransmitSubaddrState; - } - else if (transfer->direction == kI2C_Write) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = handle->remainingBytes ? kTransmitDataState : kStopState; - } - else - { - base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; - handle->state = handle->remainingBytes ? kReceiveDataState : kStopState; - } - /* Send start condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - break; - - case kTransmitSubaddrState: - if (master_state != I2C_STAT_MSTCODE_TXREADY) - { - return kStatus_I2C_UnexpectedState; - } - - /* Most significant subaddress byte comes first */ - base->MSTDAT = handle->subaddrBuf[handle->transfer.subaddressSize - handle->remainingSubaddr]; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - if (--(handle->remainingSubaddr)) - { - /* There are still subaddress bytes to be transmitted */ - break; - } - if (handle->remainingBytes) - { - /* There is data to be transferred, if there is write to read turnaround it is necessary to perform - * repeated start */ - handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState; - } - else - { - /* No more data, schedule stop condition */ - handle->state = kStopState; - } - break; - - case kTransmitDataState: - if (master_state != I2C_STAT_MSTCODE_TXREADY) - { - return kStatus_I2C_UnexpectedState; - } - base->MSTDAT = *(handle->buf)++; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - if (--handle->remainingBytes == 0) - { - /* No more data, schedule stop condition */ - handle->state = kStopState; - } - handle->transferCount++; - break; - - case kReceiveDataState: - if (master_state != I2C_STAT_MSTCODE_RXREADY) - { - return kStatus_I2C_UnexpectedState; - } - *(handle->buf)++ = base->MSTDAT; - if (--handle->remainingBytes) - { - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - } - else - { - /* No more data expected, issue NACK and STOP right away */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; - } - handle->transferCount++; - break; - - case kStopState: - if (transfer->flags & kI2C_TransferNoStopFlag) - { - /* Stop condition is omitted, we are done */ - *isDone = true; - handle->state = kIdleState; - break; - } - /* Send stop condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; - break; - - case kWaitForCompletionState: - *isDone = true; - handle->state = kIdleState; - break; - - case kIdleState: - default: - /* State machine shall not be invoked again once it enters the idle state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - return err; -} - -void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle) -{ - bool isDone; - status_t result; - - /* Don't do anything if we don't have a valid handle. */ - if (!handle) - { - return; - } - - result = I2C_RunTransferStateMachine(base, handle, &isDone); - - if (isDone || (result != kStatus_Success)) - { - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); - - /* Invoke callback. */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } -} - -/*! - * @brief Sets the hardware slave state machine to reset - * - * Per documentation, the only the state machine is reset, the configuration settings remain. - * - * @param base The I2C peripheral base address. - */ -static void I2C_SlaveInternalStateMachineReset(I2C_Type *base) -{ - I2C_SlaveEnable(base, false); /* clear SLVEN Slave enable bit */ -} - -/*! - * @brief Compute CLKDIV - * - * This function computes CLKDIV value according to the given bus speed and Flexcomm source clock frequency. - * This setting is used by hardware during slave clock stretching. - * - * @param base The I2C peripheral base address. - * @return status of the operation - */ -static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal) -{ - uint32_t dataSetupTime_ns; - - switch (busSpeed) - { - case kI2C_SlaveStandardMode: - dataSetupTime_ns = 250u; - break; - - case kI2C_SlaveFastMode: - dataSetupTime_ns = 100u; - break; - - case kI2C_SlaveFastModePlus: - dataSetupTime_ns = 50u; - break; - - case kI2C_SlaveHsMode: - dataSetupTime_ns = 10u; - break; - - default: - dataSetupTime_ns = 0; - break; - } - - if (0 == dataSetupTime_ns) - { - return kStatus_InvalidArgument; - } - - /* divVal = (sourceClock_Hz / 1000000) * (dataSetupTime_ns / 1000) */ - *divVal = srcClock_Hz / 1000u; - *divVal = (*divVal) * dataSetupTime_ns; - *divVal = (*divVal) / 1000000u; - - if ((*divVal) > I2C_CLKDIV_DIVVAL_MASK) - { - *divVal = I2C_CLKDIV_DIVVAL_MASK; - } - - return kStatus_Success; -} - -/*! - * @brief Poll wait for the SLVPENDING flag. - * - * Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register. - * - * @param base The I2C peripheral base address. - * @return status register at time the SLVPENDING bit is read as set - */ -static uint32_t I2C_SlavePollPending(I2C_Type *base) -{ - uint32_t stat; - - do - { - stat = base->STAT; - } while (0u == (stat & I2C_STAT_SLVPENDING_MASK)); - - return stat; -} - -/*! - * @brief Invoke event from I2C_SlaveTransferHandleIRQ(). - * - * Sets the event type to transfer structure and invokes the event callback, if it has been - * enabled by eventMask. - * - * @param base The I2C peripheral base address. - * @param handle The I2C slave handle for non-blocking APIs. - * @param event The I2C slave event to invoke. - */ -static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event) -{ - handle->transfer.event = event; - if ((handle->callback) && (handle->transfer.eventMask & event)) - { - handle->callback(base, &handle->transfer, handle->userData); - - /* if after event callback we have data buffer (callback func has added new data), keep transfer busy */ - if (false == handle->isBusy) - { - if (((handle->transfer.txData) && (handle->transfer.txSize)) || - ((handle->transfer.rxData) && (handle->transfer.rxSize))) - { - handle->isBusy = true; - } - } - - /* Clear the transferred count now that we have a new buffer. */ - if ((event == kI2C_SlaveReceiveEvent) || (event == kI2C_SlaveTransmitEvent)) - { - handle->transfer.transferredCount = 0; - } - } -} - -/*! - * @brief Handle slave address match event. - * - * Called by Slave interrupt routine to ACK or NACK the matched address. - * It also determines master direction (read or write). - * - * @param base The I2C peripheral base address. - * @return true if the matched address is ACK'ed - * @return false if the matched address is NACK'ed - */ -static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle) -{ - uint8_t addressByte0; - - addressByte0 = (uint8_t)base->SLVDAT; - - /* store the matched address */ - handle->transfer.receivedAddress = addressByte0; - - /* R/nW */ - if (addressByte0 & 1u) - { - /* if we have no data in this transfer, call callback to get new */ - if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); - } - - /* NACK if we have no data in this transfer. */ - if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0)) - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - return false; - } - - /* master wants to read, so slave transmit is next state */ - handle->slaveFsm = kI2C_SlaveFsmTransmit; - } - else - { - /* if we have no receive buffer in this transfer, call callback to get new */ - if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); - } - - /* NACK if we have no data in this transfer */ - if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0)) - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - return false; - } - - /* master wants write, so slave receive is next state */ - handle->slaveFsm = kI2C_SlaveFsmReceive; - } - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - return true; -} - -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. - * @param txData Data to be transmitted to master in response to master read from slave requests. NULL if slave RX only. - * @param txSize Size of txData buffer in bytes. - * @param rxData Data where received data from master will be stored in response to master write to slave requests. NULL - * if slave TX only. - * @param rxSize Size of rxData buffer in bytes. - * - * @retval #kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, - i2c_slave_handle_t *handle, - const void *txData, - size_t txSize, - void *rxData, - size_t rxSize, - uint32_t eventMask) -{ - status_t status; - - assert(handle); - - status = kStatus_Success; - - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags); - - /* Return busy if another transaction is in progress. */ - if (handle->isBusy) - { - status = kStatus_I2C_Busy; - } - - /* Save transfer into handle. */ - handle->transfer.txData = (const uint8_t *)(uintptr_t)txData; - handle->transfer.txSize = txSize; - handle->transfer.rxData = (uint8_t *)rxData; - handle->transfer.rxSize = rxSize; - handle->transfer.transferredCount = 0; - handle->transfer.eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent; - handle->isBusy = true; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* Clear w1c flags. */ - base->STAT |= 0u; - - /* Enable I2C internal IRQ sources. */ - I2C_EnableInterrupts(base, kI2C_SlaveIrqFlags); - - return status; -} - -status_t I2C_SlaveSetSendBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, txData, txSize, NULL, 0u, eventMask); -} - -status_t I2C_SlaveSetReceiveBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, NULL, 0u, rxData, rxSize, eventMask); -} - -void I2C_SlaveSetAddress(I2C_Type *base, - i2c_slave_address_register_t addressRegister, - uint8_t address, - bool addressDisable) -{ - base->SLVADR[addressRegister] = I2C_SLVADR_SLVADR(address) | I2C_SLVADR_SADISABLE(addressDisable); -} - -void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) -{ - assert(slaveConfig); - - i2c_slave_config_t mySlaveConfig = {0}; - - /* default config enables slave address 0 match to general I2C call address zero */ - mySlaveConfig.enableSlave = true; - mySlaveConfig.address1.addressDisable = true; - mySlaveConfig.address2.addressDisable = true; - mySlaveConfig.address3.addressDisable = true; - - *slaveConfig = mySlaveConfig; -} - -status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz) -{ - status_t status; - uint32_t divVal = 0; - - /* configure data setup time used when slave stretches clock */ - status = I2C_SlaveDivVal(srcClock_Hz, slaveConfig->busSpeed, &divVal); - if (kStatus_Success != status) - { - return status; - } - - FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); - - /* I2C Clock Divider register */ - base->CLKDIV = divVal; - - /* set Slave address */ - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister0, slaveConfig->address0.address, - slaveConfig->address0.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister1, slaveConfig->address1.address, - slaveConfig->address1.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister2, slaveConfig->address2.address, - slaveConfig->address2.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister3, slaveConfig->address3.address, - slaveConfig->address3.addressDisable); - - /* set Slave address 0 qual */ - base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(slaveConfig->qualMode) | I2C_SLVQUAL0_SLVQUAL0(slaveConfig->qualAddress); - - /* set Slave enable */ - base->CFG = I2C_CFG_SLVEN(slaveConfig->enableSlave); - - return status; -} - -void I2C_SlaveDeinit(I2C_Type *base) -{ - I2C_SlaveEnable(base, false); -} - -status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) -{ - const uint8_t *buf = txBuff; - uint32_t stat; - bool slaveAddress; - bool slaveTransmit; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - - /* Get slave machine state */ - slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); - slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX); - - /* in I2C_SlaveSend() it shall be either slaveAddress or slaveTransmit */ - if (!(slaveAddress || slaveTransmit)) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - if (slaveAddress) - { - /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - } - - /* send bytes up to txSize */ - while (txSize) - { - slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX); - - if (!slaveTransmit) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - /* Write 8 bits of data to the SLVDAT register */ - base->SLVDAT = I2C_SLVDAT_DATA(*buf); - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* advance counters and pointers for next data */ - buf++; - txSize--; - - if (txSize) - { - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - } - } - - return kStatus_Success; -} - -status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) -{ - uint8_t *buf = rxBuff; - uint32_t stat; - bool slaveAddress; - bool slaveReceive; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - - /* Get slave machine state */ - slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); - slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX); - - /* in I2C_SlaveReceive() it shall be either slaveAddress or slaveReceive */ - if (!(slaveAddress || slaveReceive)) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - if (slaveAddress) - { - /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - } - - /* receive bytes up to rxSize */ - while (rxSize) - { - slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX); - - if (!slaveReceive) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - /* Read 8 bits of data from the SLVDAT register */ - *buf = (uint8_t)base->SLVDAT; - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* advance counters and pointers for next data */ - buf++; - rxSize--; - - if (rxSize) - { - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - } - } - - return kStatus_Success; -} - -void I2C_SlaveTransferCreateHandle(I2C_Type *base, - i2c_slave_handle_t *handle, - i2c_slave_transfer_callback_t callback, - void *userData) -{ - uint32_t instance; - - assert(handle); - - /* Clear out the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Save base and instance. */ - handle->callback = callback; - handle->userData = userData; - - /* initialize fsm */ - handle->slaveFsm = kI2C_SlaveFsmAddressMatch; - - /* store pointer to handle into transfer struct */ - handle->transfer.handle = handle; - - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2C_SlaveTransferHandleIRQ, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags); - EnableIRQ(s_i2cIRQ[instance]); -} - -status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, handle, NULL, 0u, NULL, 0u, eventMask); -} - -status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (!handle->isBusy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* For an active transfer, just return the count from the handle. */ - *count = handle->transfer.transferredCount; - - return kStatus_Success; -} - -void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) -{ - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags); - - /* Set the SLVEN bit to 0 in the CFG register. */ - I2C_SlaveEnable(base, false); - - handle->isBusy = false; - handle->transfer.txSize = 0; - handle->transfer.rxSize = 0; -} - -void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle) -{ - uint32_t i2cStatus = base->STAT; - - if (i2cStatus & I2C_STAT_SLVDESEL_MASK) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveDeselectedEvent); - I2C_SlaveClearStatusFlags(base, I2C_STAT_SLVDESEL_MASK); - } - - /* SLVPENDING flag is cleared by writing I2C_SLVCTL_SLVCONTINUE_MASK to SLVCTL register */ - if (i2cStatus & I2C_STAT_SLVPENDING_MASK) - { - bool slaveAddress = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); - - if (slaveAddress) - { - I2C_SlaveAddressIRQ(base, handle); - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveAddressMatchEvent); - } - else - { - switch (handle->slaveFsm) - { - case kI2C_SlaveFsmReceive: - { - bool slaveReceive = - (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX); - - if (slaveReceive) - { - /* if we have no receive buffer in this transfer, call callback to get new */ - if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); - } - - /* receive a byte */ - if ((handle->transfer.rxData) && (handle->transfer.rxSize)) - { - *(handle->transfer.rxData) = (uint8_t)base->SLVDAT; - (handle->transfer.rxSize)--; - (handle->transfer.rxData)++; - (handle->transfer.transferredCount)++; - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - } - - /* is this last transaction for this transfer? allow next transaction */ - if ((0 == handle->transfer.rxSize) && (0 == handle->transfer.txSize)) - { - handle->isBusy = false; - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); - } - } - else - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - } - } - break; - - case kI2C_SlaveFsmTransmit: - { - bool slaveTransmit = - (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX); - - if (slaveTransmit) - { - /* if we have no data in this transfer, call callback to get new */ - if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); - } - - /* transmit a byte */ - if ((handle->transfer.txData) && (handle->transfer.txSize)) - { - base->SLVDAT = *(handle->transfer.txData); - (handle->transfer.txSize)--; - (handle->transfer.txData)++; - (handle->transfer.transferredCount)++; - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - } - - /* is this last transaction for this transfer? allow next transaction */ - if ((0 == handle->transfer.rxSize) && (0 == handle->transfer.txSize)) - { - handle->isBusy = false; - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); - } - } - else - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - } - } - break; - - default: - /* incorrect state, slv_abort()? */ - break; - } - } - } -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2c.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2c.h deleted file mode 100644 index bda2d815f5c..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2c.h +++ /dev/null @@ -1,1039 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_I2C_H_ -#define _FSL_I2C_H_ - -#include -#include "fsl_device_registers.h" -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define I2C_CFG_MASK 0x1f - -/*! - * @addtogroup i2c_driver - * @{ - */ - -/*! @file */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2C driver version 1.0.0. */ -#define NXP_I2C_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) -/*@}*/ - -/* definitions for MSTCODE bits in I2C Status register STAT */ -#define I2C_STAT_MSTCODE_IDLE (0) /*!< Master Idle State Code */ -#define I2C_STAT_MSTCODE_RXREADY (1) /*!< Master Receive Ready State Code */ -#define I2C_STAT_MSTCODE_TXREADY (2) /*!< Master Transmit Ready State Code */ -#define I2C_STAT_MSTCODE_NACKADR (3) /*!< Master NACK by slave on address State Code */ -#define I2C_STAT_MSTCODE_NACKDAT (4) /*!< Master NACK by slave on data State Code */ - -/* definitions for SLVSTATE bits in I2C Status register STAT */ -#define I2C_STAT_SLVST_ADDR (0) -#define I2C_STAT_SLVST_RX (1) -#define I2C_STAT_SLVST_TX (2) - -/*! @brief I2C status return codes. */ -enum _i2c_status -{ - kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 0), /*!< The master is already performing a transfer. */ - kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 1), /*!< The slave driver is idle. */ - kStatus_I2C_Nak = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 2), /*!< The slave device sent a NAK in response to a byte. */ - kStatus_I2C_InvalidParameter = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 3), /*!< Unable to proceed due to invalid parameter. */ - kStatus_I2C_BitError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 4), /*!< Transferred bit was not seen on the bus. */ - kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 5), /*!< Arbitration lost error. */ - kStatus_I2C_NoTransferInProgress = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< Attempt to abort a transfer when one is not in progress. */ - kStatus_I2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */ - kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8), - kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9), -}; - -/*! @} */ - -/*! - * @addtogroup i2c_master_driver - * @{ - */ - -/*! - * @brief I2C master peripheral flags. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -enum _i2c_master_flags -{ - kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. */ - kI2C_MasterArbitrationLostFlag = I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus */ - kI2C_MasterStartStopErrorFlag = I2C_STAT_MSTSTSTPERR_MASK /*!< There was an error during start or stop phase of the transaction. */ -}; - -/*! @brief Direction of master and slave transfers. */ -typedef enum _i2c_direction -{ - kI2C_Write = 0U, /*!< Master transmit. */ - kI2C_Read = 1U /*!< Master receive. */ -} i2c_direction_t; - -/*! - * @brief Structure with settings to initialize the I2C master module. - * - * This structure holds configuration settings for the I2C peripheral. To initialize this - * structure to reasonable defaults, call the I2C_MasterGetDefaultConfig() function and - * pass a pointer to your configuration structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _i2c_master_config -{ - bool enableMaster; /*!< Whether to enable master mode. */ - uint32_t baudRate_Bps; /*!< Desired baud rate in bits per second. */ - bool enableTimeout; /*!< Enable internal timeout function. */ -} i2c_master_config_t; - -/* Forward declaration of the transfer descriptor and handle typedefs. */ -/*! @brief I2C master transfer typedef */ -typedef struct _i2c_master_transfer i2c_master_transfer_t; - -/*! @brief I2C master handle typedef */ -typedef struct _i2c_master_handle i2c_master_handle_t; - -/*! - * @brief Master completion callback function pointer type. - * - * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use - * in the call to I2C_MasterTransferCreateHandle(). - * - * @param base The I2C peripheral base address. - * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, - i2c_master_handle_t *handle, - status_t completionStatus, - void *userData); - -/*! - * @brief Transfer option flags. - * - * @note These enumerations are intended to be OR'd together to form a bit mask of options for - * the #_i2c_master_transfer::flags field. - */ -enum _i2c_master_transfer_flags -{ - kI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ - kI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ - kI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ - kI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ -}; - -/*! @brief States for the state machine used by transactional APIs. */ -enum _i2c_transfer_states -{ - kIdleState = 0, - kTransmitSubaddrState, - kTransmitDataState, - kReceiveDataState, - kReceiveLastDataState, - kStartState, - kStopState, - kWaitForCompletionState -}; - -/*! - * @brief Non-blocking transfer descriptor structure. - * - * This structure is used to pass transaction parameters to the I2C_MasterTransferNonBlocking() API. - */ -struct _i2c_master_transfer -{ - uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i2c_master_transfer_flags for available - options. Set to 0 or #kI2C_TransferDefaultFlag for normal transfers. */ - uint16_t slaveAddress; /*!< The 7-bit slave address. */ - i2c_direction_t direction; /*!< Either #kI2C_Read or #kI2C_Write. */ - uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ - size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ - void *data; /*!< Pointer to data to transfer. */ - size_t dataSize; /*!< Number of bytes to transfer. */ -}; - -/*! - * @brief Driver handle for master non-blocking APIs. - * @note The contents of this structure are private and subject to change. - */ -struct _i2c_master_handle -{ - uint8_t state; /*!< Transfer state machine current state. */ - uint32_t transferCount; /*!< Indicates progress of the transfer */ - uint32_t remainingBytes; /*!< Remaining byte count in current state. */ - uint8_t *buf; /*!< Buffer pointer for current state. */ - uint32_t remainingSubaddr; - uint8_t subaddrBuf[4]; - i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ - i2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ - void *userData; /*!< Application data passed to callback. */ -}; - -/*! @} */ - -/*! - * @addtogroup i2c_slave_driver - * @{ - */ - - /*! - * @brief I2C slave peripheral flags. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -enum _i2c_slave_flags -{ - kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. */ - kI2C_SlaveNotStretching = I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 = yes, 1 = no). */ - kI2C_SlaveSelected = I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. */ - kI2C_SaveDeselected = I2C_STAT_SLVDESEL_MASK /*!< Indicates that slave was previously deselected (deselect event took place, w1c). */ -}; - -/*! @brief I2C slave address register. */ -typedef enum _i2c_slave_address_register -{ - kI2C_SlaveAddressRegister0 = 0U, /*!< Slave Address 0 register. */ - kI2C_SlaveAddressRegister1 = 1U, /*!< Slave Address 1 register. */ - kI2C_SlaveAddressRegister2 = 2U, /*!< Slave Address 2 register. */ - kI2C_SlaveAddressRegister3 = 3U, /*!< Slave Address 3 register. */ -} i2c_slave_address_register_t; - -/*! @brief Data structure with 7-bit Slave address and Slave address disable. */ -typedef struct _i2c_slave_address -{ - uint8_t address; /*!< 7-bit Slave address SLVADR. */ - bool addressDisable; /*!< Slave address disable SADISABLE. */ -} i2c_slave_address_t; - -/*! @brief I2C slave address match options. */ -typedef enum _i2c_slave_address_qual_mode -{ - kI2C_QualModeMask = 0U, /*!< The SLVQUAL0 field (qualAddress) is used as a logical mask for matching address0. */ - kI2C_QualModeExtend = - 1U, /*!< The SLVQUAL0 (qualAddress) field is used to extend address 0 matching in a range of addresses. */ -} i2c_slave_address_qual_mode_t; - -/*! @brief I2C slave bus speed options. */ -typedef enum _i2c_slave_bus_speed -{ - kI2C_SlaveStandardMode = 0U, - kI2C_SlaveFastMode = 1U, - kI2C_SlaveFastModePlus = 2U, - kI2C_SlaveHsMode = 3U, -} i2c_slave_bus_speed_t; - -/*! - * @brief Structure with settings to initialize the I2C slave module. - * - * This structure holds configuration settings for the I2C slave peripheral. To initialize this - * structure to reasonable defaults, call the I2C_SlaveGetDefaultConfig() function and - * pass a pointer to your configuration structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _i2c_slave_config -{ - i2c_slave_address_t address0; /*!< Slave's 7-bit address and disable. */ - i2c_slave_address_t address1; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_t address2; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_t address3; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_qual_mode_t qualMode; /*!< Qualify mode for slave address 0. */ - uint8_t qualAddress; /*!< Slave address qualifier for address 0. */ - i2c_slave_bus_speed_t - busSpeed; /*!< Slave bus speed mode. If the slave function stretches SCL to allow for software response, it must - provide sufficient data setup time to the master before releasing the stretched clock. - This is accomplished by inserting one clock time of CLKDIV at that point. - The #busSpeed value is used to configure CLKDIV - such that one clock time is greater than the tSU;DAT value noted - in the I2C bus specification for the I2C mode that is being used. - If the #busSpeed mode is unknown at compile time, use the longest data setup time - kI2C_SlaveStandardMode (250 ns) */ - bool enableSlave; /*!< Enable slave mode. */ -} i2c_slave_config_t; - -/*! - * @brief Set of events sent to the callback for non blocking slave transfers. - * - * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together - * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable. - * Then, when the slave callback is invoked, it is passed the current event through its @a transfer - * parameter. - * - * @note These enumerations are meant to be OR'd together to form a bit mask of events. - */ -typedef enum _i2c_slave_transfer_event -{ - kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ - kI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit - (slave-transmitter role). */ - kI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received - data (slave-receiver role). */ - kI2C_SlaveCompletionEvent = 0x20U, /*!< All data in the active transfer have been consumed. */ - kI2C_SlaveDeselectedEvent = - 0x40U, /*!< The slave function has become deselected (SLVSEL flag changing from 1 to 0. */ - - /*! Bit mask of all available events. */ - kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | - kI2C_SlaveCompletionEvent | kI2C_SlaveDeselectedEvent, -} i2c_slave_transfer_event_t; - -/*! @brief I2C slave handle typedef. */ -typedef struct _i2c_slave_handle i2c_slave_handle_t; - -/*! @brief I2C slave transfer structure */ -typedef struct _i2c_slave_transfer -{ - i2c_slave_handle_t *handle; /*!< Pointer to handle that contains this transfer. */ - i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ - uint8_t receivedAddress; /*!< Matching address send by master. 7-bits plus R/nW bit0 */ - uint32_t eventMask; /*!< Mask of enabled events. */ - uint8_t *rxData; /*!< Transfer buffer for receive data */ - const uint8_t *txData; /*!< Transfer buffer for transmit data */ - size_t txSize; /*!< Transfer size */ - size_t rxSize; /*!< Transfer size */ - size_t transferredCount; /*!< Number of bytes transferred during this transfer. */ - status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for - #kI2C_SlaveCompletionEvent. */ -} i2c_slave_transfer_t; - -/*! - * @brief Slave event callback function pointer type. - * - * This callback is used only for the slave non-blocking transfer API. To install a callback, - * use the I2C_SlaveSetCallback() function after you have created a handle. - * - * @param base Base address for the I2C instance on which the event occurred. - * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *userData); - -/*! - * @brief I2C slave software finite state machine states. - */ -typedef enum _i2c_slave_fsm -{ - kI2C_SlaveFsmAddressMatch = 0u, - kI2C_SlaveFsmReceive = 2u, - kI2C_SlaveFsmTransmit = 3u, -} i2c_slave_fsm_t; - -/*! - * @brief I2C slave handle structure. - * @note The contents of this structure are private and subject to change. - */ -struct _i2c_slave_handle -{ - volatile i2c_slave_transfer_t transfer; /*!< I2C slave transfer. */ - volatile bool isBusy; /*!< Whether transfer is busy. */ - volatile i2c_slave_fsm_t slaveFsm; /*!< slave transfer state machine. */ - i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ - void *userData; /*!< Callback parameter passed to callback. */ -}; - -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup i2c_master_driver - * @{ - */ - -/*! @name Initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the I2C master peripheral. - * - * This function provides the following default configuration for the I2C master peripheral: - * @code - * masterConfig->enableMaster = true; - * masterConfig->baudRate_Bps = 100000U; - * masterConfig->enableTimeout = false; - * @endcode - * - * After calling this function, you can override any settings in order to customize the configuration, - * prior to initializing the master driver with I2C_MasterInit(). - * - * @param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. - */ -void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); - -/*! - * @brief Initializes the I2C master peripheral. - * - * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user - * provided configuration. A software reset is performed prior to configuration. - * - * @param base The I2C peripheral base address. - * @param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of - * defaults - * that you can override. - * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, - * filter widths, and timeout periods. - */ -void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); - -/*! -* @brief Deinitializes the I2C master peripheral. -* - * This function disables the I2C master peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -void I2C_MasterDeinit(I2C_Type *base); - -/*! - * @brief Performs a software reset. - * - * Restores the I2C master peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -static inline void I2C_MasterReset(I2C_Type *base) -{ -} - -/*! - * @brief Enables or disables the I2C module as master. - * - * @param base The I2C peripheral base address. - * @param enable Pass true to enable or false to disable the specified I2C as master. - */ -static inline void I2C_MasterEnable(I2C_Type *base, bool enable) -{ - if (enable) - { - base->CFG = (base->CFG & I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK; - } - else - { - base->CFG = (base->CFG & I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK; - } -} - -/*@}*/ - -/*! @name Status */ -/*@{*/ - -/*! - * @brief Gets the I2C status flags. - * - * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit - * in the return value is set if the flag is asserted. - * - * @param base The I2C peripheral base address. - * @return State of the status flags: - * - 1: related status flag is set. - * - 0: related status flag is not set. - * @see _i2c_master_flags - */ -static inline uint32_t I2C_GetStatusFlags(I2C_Type *base) -{ - return base->STAT; -} - -/*! - * @brief Clears the I2C master status flag state. - * - * The following status register flags can be cleared: - * - #kI2C_MasterArbitrationLostFlag - * - #kI2C_MasterStartStopErrorFlag - * - * Attempts to clear other flags has no effect. - * - * @param base The I2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * #_i2c_master_flags enumerators OR'd together. You may pass the result of a previous call to - * I2C_GetStatusFlags(). - * @see _i2c_master_flags. - */ -static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - /* Allow clearing just master status flags */ - base->STAT = statusMask & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); -} - -/*@}*/ - -/*! @name Interrupts */ -/*@{*/ - -/*! - * @brief Enables the I2C master interrupt requests. - * - * @param base The I2C peripheral base address. - * @param interruptMask Bit mask of interrupts to enable. See #_i2c_master_flags for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2C_EnableInterrupts(I2C_Type *base, uint32_t interruptMask) -{ - base->INTENSET = interruptMask; -} - -/*! - * @brief Disables the I2C master interrupt requests. - * - * @param base The I2C peripheral base address. - * @param interruptMask Bit mask of interrupts to disable. See #_i2c_master_flags for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2C_DisableInterrupts(I2C_Type *base, uint32_t interruptMask) -{ - base->INTENCLR = interruptMask; -} - -/*! - * @brief Returns the set of currently enabled I2C master interrupt requests. - * - * @param base The I2C peripheral base address. - * @return A bitmask composed of #_i2c_master_flags enumerators OR'd together to indicate the - * set of enabled interrupts. - */ -static inline uint32_t I2C_GetEnabledInterrupts(I2C_Type *base) -{ - return base->INTSTAT; -} - -/*@}*/ - -/*! @name Bus operations */ -/*@{*/ - -/*! - * @brief Sets the I2C bus frequency for master transactions. - * - * The I2C master is automatically disabled and re-enabled as necessary to configure the baud - * rate. Do not call this function during a transfer, or the transfer is aborted. - * - * @param base The I2C peripheral base address. - * @param srcClock_Hz I2C functional clock frequency in Hertz. - * @param baudRate_Bps Requested bus frequency in bits per second. - */ -void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Returns whether the bus is idle. - * - * Requires the master mode to be enabled. - * - * @param base The I2C peripheral base address. - * @retval true Bus is busy. - * @retval false Bus is idle. - */ -static inline bool I2C_MasterGetBusIdleState(I2C_Type *base) -{ - /* True if MSTPENDING flag is set and MSTSTATE is zero == idle */ - return ((base->STAT & (I2C_STAT_MSTPENDING_MASK | I2C_STAT_MSTSTATE_MASK)) == I2C_STAT_MSTPENDING_MASK); -} - -/*! - * @brief Sends a START on the I2C bus. - * - * This function is used to initiate a new master mode transfer by sending the START signal. - * The slave address is sent following the I2C START signal. - * - * @param base I2C peripheral base pointer - * @param address 7-bit slave device address. - * @param direction Master transfer directions(transmit/receive). - * @retval kStatus_Success Successfully send the start signal. - * @retval kStatus_I2C_Busy Current bus is busy. - */ -status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); - -/*! - * @brief Sends a STOP signal on the I2C bus. - * - * @retval kStatus_Success Successfully send the stop signal. - * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. - */ -status_t I2C_MasterStop(I2C_Type *base); - -/*! - * @brief Sends a REPEATED START on the I2C bus. - * - * @param base I2C peripheral base pointer - * @param address 7-bit slave device address. - * @param direction Master transfer directions(transmit/receive). - * @retval kStatus_Success Successfully send the start signal. - * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. - */ -static inline status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) -{ - return I2C_MasterStart(base, address, direction); -} - -/*! - * @brief Performs a polling send transfer on the I2C bus. - * - * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may - * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this - * function returns #kStatus_I2C_Nak. - * - * @param base The I2C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers use kI2C_TransferDefaultFlag - * @retval kStatus_Success Data was sent successfully. - * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags); - -/*! - * @brief Performs a polling receive transfer on the I2C bus. - * - * @param base The I2C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers use kI2C_TransferDefaultFlag - * @retval kStatus_Success Data was received successfully. - * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags); - -/*! - * @brief Performs a master polling transfer on the I2C bus. - * - * @note The API does not return until the transfer succeeds or fails due - * to arbitration lost or receiving a NAK. - * - * @param base I2C peripheral base address. - * @param xfer Pointer to the transfer structure. - * @retval kStatus_Success Successfully complete the data transmission. - * @retval kStatus_I2C_Busy Previous transmission still not finished. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - */ -status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); - -/*@}*/ - -/*! @name Non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the I2C master non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. - * - * @param base The I2C peripheral base address. - * @param[out] handle Pointer to the I2C master driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void I2C_MasterTransferCreateHandle(I2C_Type *base, - i2c_master_handle_t *handle, - i2c_master_transfer_callback_t callback, - void *userData); - -/*! - * @brief Performs a non-blocking transaction on the I2C bus. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @param xfer The pointer to the transfer descriptor. - * @retval kStatus_Success The transaction was started successfully. - * @retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking - * transaction is already in progress. - */ -status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Returns number of bytes transferred so far. - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @param[out] count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_Success - * @retval #kStatus_I2C_Busy - */ -status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); - -/*! - * @brief Terminates a non-blocking I2C master transmission early. - * - * @note It is not safe to call this function from an IRQ handler that has a higher priority than the - * I2C peripheral's IRQ priority. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @retval kStatus_Success A transaction was successfully aborted. - * @retval #kStatus_I2C_Idle There is not a non-blocking transaction currently in progress. - */ -void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); - -/*@}*/ - -/*! @name IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle master interrupts. - * @note This function does not need to be called unless you are reimplementing the - * nonblocking API's interrupt handler routines to add special functionality. - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - */ -void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle); - -/*@}*/ - -/*! @} */ /* end of i2c_master_driver */ - -/*! - * @addtogroup i2c_slave_driver - * @{ - */ - -/*! @name Slave initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the I2C slave peripheral. - * - * This function provides the following default configuration for the I2C slave peripheral: - * @code - * slaveConfig->enableSlave = true; - * slaveConfig->address0.disable = false; - * slaveConfig->address0.address = 0u; - * slaveConfig->address1.disable = true; - * slaveConfig->address2.disable = true; - * slaveConfig->address3.disable = true; - * slaveConfig->busSpeed = kI2C_SlaveStandardMode; - * @endcode - * - * After calling this function, override any settings to customize the configuration, - * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the @a - * address0.address member of the configuration structure with the desired slave address. - * - * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to - * #i2c_slave_config_t. - */ -void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); - -/*! - * @brief Initializes the I2C slave peripheral. - * - * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user - * provided configuration. - * - * @param base The I2C peripheral base address. - * @param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults - * that you can override. - * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide - * enough - * data setup time for master when slave stretches the clock. - */ -status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz); - -/*! - * @brief Configures Slave Address n register. - * - * This function writes new value to Slave Address register. - * - * @param base The I2C peripheral base address. - * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be changed. - * @param address The slave address to be stored to the address register for matching. - * @param addressDisable Disable matching of the specified address register. - */ -void I2C_SlaveSetAddress(I2C_Type *base, - i2c_slave_address_register_t addressRegister, - uint8_t address, - bool addressDisable); - -/*! -* @brief Deinitializes the I2C slave peripheral. -* - * This function disables the I2C slave peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -void I2C_SlaveDeinit(I2C_Type *base); - -/*! - * @brief Enables or disables the I2C module as slave. - * - * @param base The I2C peripheral base address. - * @param enable True to enable or flase to disable. - */ -static inline void I2C_SlaveEnable(I2C_Type *base, bool enable) -{ - /* Set or clear the SLVEN bit in the CFG register. */ - base->CFG = I2C_CFG_SLVEN(enable); -} - -/*@}*/ /* end of Slave initialization and deinitialization */ - -/*! @name Slave status */ -/*@{*/ - -/*! - * @brief Clears the I2C status flag state. - * - * The following status register flags can be cleared: - * - slave deselected flag - * - * Attempts to clear other flags has no effect. - * - * @param base The I2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * #_i2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to - * I2C_SlaveGetStatusFlags(). - * @see _i2c_slave_flags. - */ -static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - /* Allow clearing just slave status flags */ - base->STAT = statusMask & I2C_STAT_SLVDESEL_MASK; -} - -/*@}*/ /* end of Slave status */ - -/*! @name Slave bus operations */ -/*@{*/ - -/*! - * @brief Performs a polling send transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * @param base The I2C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @return kStatus_Success Data has been sent. - * @return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). - */ -status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); - -/*! - * @brief Performs a polling receive transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * @param base The I2C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @return kStatus_Success Data has been received. - * @return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). - */ -status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); - -/*@}*/ /* end of Slave bus operations */ - -/*! @name Slave non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the I2C slave non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. - * - * @param base The I2C peripheral base address. - * @param[out] handle Pointer to the I2C slave driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void I2C_SlaveTransferCreateHandle(I2C_Type *base, - i2c_slave_handle_t *handle, - i2c_slave_transfer_callback_t callback, - void *userData); - -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. - * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); - -/*! - * @brief Starts accepting master read from slave requests. - * - * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param transfer Pointer to #i2c_slave_transfer_t structure. - * @param txData Pointer to data to send to master. - * @param txSize Size of txData in bytes. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetSendBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask); - -/*! - * @brief Starts accepting master write to slave requests. - * - * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param transfer Pointer to #i2c_slave_transfer_t structure. - * @param rxData Pointer to data to store data from master. - * @param rxSize Size of rxData in bytes. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetReceiveBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask); - -/*! - * @brief Returns the slave address sent by the I2C master. - * - * This function should only be called from the address match event callback #kI2C_SlaveAddressMatchEvent. - * - * @param base The I2C peripheral base address. - * @param transfer The I2C slave transfer. - * @return The 8-bit address matched by the I2C slave. Bit 0 contains the R/w direction bit, and - * the 7-bit slave address is in the upper 7 bits. - */ -static inline uint32_t I2C_SlaveGetReceivedAddress(I2C_Type *base, volatile i2c_slave_transfer_t *transfer) -{ - return transfer->receivedAddress; -} - -/*! - * @brief Aborts the slave non-blocking transfers. - * @note This API could be called at any time to stop slave for handling the bus events. - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * @retval kStatus_Success - * @retval #kStatus_I2C_Idle - */ -void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); - -/*! - * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_slave_handle_t structure. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_InvalidArgument count is Invalid. - * @retval kStatus_Success Successfully return the count. - */ -status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); - -/*@}*/ /* end of Slave non-blocking */ - -/*! @name Slave IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle slave interrupts. - * @note This function does not need to be called unless you are reimplementing the - * non blocking API's interrupt handler routines to add special functionality. - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - */ -void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle); - -/*@}*/ /* end of Slave IRQ handler */ - -/*! @} */ /* end of i2c_slave_driver */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2C_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2c_dma.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2c_dma.c deleted file mode 100644 index 17c0f3f5098..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2c_dma.c +++ /dev/null @@ -1,579 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_i2c_dma.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*transfer = *xfer; - transfer = &(handle->transfer); - - handle->transferCount = 0; - handle->remainingBytesDMA = 0; - handle->buf = (uint8_t *)transfer->data; - handle->remainingSubaddr = 0; - - if (transfer->flags & kI2C_TransferNoStartFlag) - { - /* Start condition shall be ommited, switch directly to next phase */ - if (transfer->dataSize == 0) - { - handle->state = kStopState; - } - else if (handle->transfer.direction == kI2C_Write) - { - handle->state = xfer->dataSize = kTransmitDataState; - } - else if (handle->transfer.direction == kI2C_Read) - { - handle->state = (xfer->dataSize == 1) ? kReceiveLastDataState : kReceiveDataState; - } - else - { - return kStatus_I2C_InvalidParameter; - } - } - else - { - if (transfer->subaddressSize != 0) - { - int i; - uint32_t subaddress; - - if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) - { - return kStatus_I2C_InvalidParameter; - } - - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = xfer->subaddressSize - 1; i >= 0; i--) - { - handle->subaddrBuf[i] = subaddress & 0xff; - subaddress >>= 8; - } - handle->remainingSubaddr = transfer->subaddressSize; - } - - handle->state = kStartState; - } - - return kStatus_Success; -} - -static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - int transfer_size; - dma_transfer_config_t xferConfig; - - /* Update transfer count */ - handle->transferCount = handle->buf - (uint8_t *)handle->transfer.data; - - /* Check if there is anything to be transferred at all */ - if (handle->remainingBytesDMA == 0) - { - /* No data to be transferrred, disable DMA */ - base->MSTCTL = 0; - return; - } - - /* Calculate transfer size */ - transfer_size = handle->remainingBytesDMA; - if (transfer_size > I2C_MAX_DMA_TRANSFER_COUNT) - { - transfer_size = I2C_MAX_DMA_TRANSFER_COUNT; - } - - switch (handle->transfer.direction) - { - case kI2C_Write: - DMA_PrepareTransfer(&xferConfig, handle->buf, (void *)&base->MSTDAT, sizeof(uint8_t), transfer_size, - kDMA_MemoryToPeripheral, NULL); - break; - - case kI2C_Read: - DMA_PrepareTransfer(&xferConfig, (void *)&base->MSTDAT, handle->buf, sizeof(uint8_t), transfer_size, - kDMA_PeripheralToMemory, NULL); - break; - - default: - /* This should never happen */ - assert(0); - break; - } - - DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - DMA_StartTransfer(handle->dmaHandle); - - handle->remainingBytesDMA -= transfer_size; - handle->buf += transfer_size; -} - -/*! - * @brief Execute states until the transfer is done. - * @param handle Master nonblocking driver handle. - * @param[out] isDone Set to true if the transfer has completed. - * @retval #kStatus_Success - * @retval #kStatus_I2C_ArbitrationLost - * @retval #kStatus_I2C_Nak - */ -static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone) -{ - uint32_t status; - uint32_t master_state; - struct _i2c_master_transfer *transfer; - dma_transfer_config_t xferConfig; - status_t err; - uint32_t start_flag = 0; - - transfer = &(handle->transfer); - - *isDone = false; - - status = I2C_GetStatusFlags(base); - - if (status & I2C_STAT_MSTARBLOSS_MASK) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_ArbitrationLost; - } - - if (status & I2C_STAT_MSTSTSTPERR_MASK) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_StartStopError; - } - - if ((status & I2C_STAT_MSTPENDING_MASK) == 0) - { - return kStatus_I2C_Busy; - } - - /* Get the state of the I2C module */ - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT)) - { - /* Slave NACKed last byte, issue stop and return error */ - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; - return kStatus_I2C_Nak; - } - - err = kStatus_Success; - - if (handle->state == kStartState) - { - /* set start flag for later use */ - start_flag = I2C_MSTCTL_MSTSTART_MASK; - - if (handle->remainingSubaddr) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = kTransmitSubaddrState; - } - else if (transfer->direction == kI2C_Write) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - if (transfer->dataSize == 0) - { - /* No data to be transferred, initiate start and schedule stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - handle->state = kStopState; - return err; - } - handle->state = kTransmitDataState; - } - else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0)) - { - base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; - if (transfer->dataSize == 1) - { - /* The very last byte is always received by means of SW */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - handle->state = kReceiveLastDataState; - return err; - } - handle->state = kReceiveDataState; - } - else - { - handle->state = kIdleState; - err = kStatus_I2C_UnexpectedState; - return err; - } - } - - switch (handle->state) - { - case kTransmitSubaddrState: - if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag)) - { - return kStatus_I2C_UnexpectedState; - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - - /* Prepare and submit DMA transfer. */ - DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (void *)&base->MSTDAT, sizeof(uint8_t), - handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL); - DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - - handle->remainingSubaddr = 0; - if (transfer->dataSize) - { - /* There is data to be transferred, if there is write to read turnaround it is necessary to perform - * repeated start */ - handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState; - } - else - { - /* No more data, schedule stop condition */ - handle->state = kStopState; - } - break; - - case kTransmitDataState: - if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag)) - { - return kStatus_I2C_UnexpectedState; - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - handle->remainingBytesDMA = handle->transfer.dataSize; - - I2C_RunDMATransfer(base, handle); - - /* Schedule stop condition */ - handle->state = kStopState; - break; - - case kReceiveDataState: - if ((master_state != I2C_STAT_MSTCODE_RXREADY) && (!start_flag)) - { - return kStatus_I2C_UnexpectedState; - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - handle->remainingBytesDMA = handle->transfer.dataSize - 1; - - I2C_RunDMATransfer(base, handle); - - /* Schedule reception of last data byte */ - handle->state = kReceiveLastDataState; - break; - - case kReceiveLastDataState: - if (master_state != I2C_STAT_MSTCODE_RXREADY) - { - return kStatus_I2C_UnexpectedState; - } - - ((uint8_t *)transfer->data)[transfer->dataSize - 1] = base->MSTDAT; - handle->transferCount++; - - /* No more data expected, issue NACK and STOP right away */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; - break; - - case kStopState: - if (transfer->flags & kI2C_TransferNoStopFlag) - { - /* Stop condition is omitted, we are done */ - *isDone = true; - handle->state = kIdleState; - break; - } - /* Send stop condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; - break; - - case kWaitForCompletionState: - *isDone = true; - handle->state = kIdleState; - break; - - case kStartState: - case kIdleState: - default: - /* State machine shall not be invoked again once it enters the idle state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - return err; -} - -void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - bool isDone; - status_t result; - - /* Don't do anything if we don't have a valid handle. */ - if (!handle) - { - return; - } - - result = I2C_RunTransferStateMachineDMA(base, handle, &isDone); - - if (isDone || (result != kStatus_Success)) - { - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, - I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK); - - /* Invoke callback. */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } -} - -static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData) -{ - i2c_master_dma_private_handle_t *dmaPrivateHandle; - - /* Don't do anything if we don't have a valid handle. */ - if (!handle) - { - return; - } - - dmaPrivateHandle = (i2c_master_dma_private_handle_t *)userData; - I2C_RunDMATransfer(dmaPrivateHandle->base, dmaPrivateHandle->handle); -} - -void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, - i2c_master_dma_handle_t *handle, - i2c_master_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *dmaHandle) -{ - uint32_t instance; - - assert(handle); - assert(dmaHandle); - - /* Zero handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Set the user callback and userData. */ - handle->completionCallback = callback; - handle->userData = userData; - - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2C_MasterTransferDMAHandleIRQ, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, - I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK); - EnableIRQ(s_i2cIRQ[instance]); - - /* Set the handle for DMA. */ - handle->dmaHandle = dmaHandle; - - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - DMA_SetCallback(dmaHandle, (dma_callback)(uintptr_t)I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]); -} - -status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer) -{ - status_t result; - - assert(handle); - assert(xfer); - assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); - - /* Return busy if another transaction is in progress. */ - if (handle->state != kIdleState) - { - return kStatus_I2C_Busy; - } - - /* Prepare transfer state machine. */ - result = I2C_InitTransferStateMachineDMA(base, handle, xfer); - - /* Clear error flags. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Enable I2C internal IRQ sources */ - I2C_EnableInterrupts(base, - I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_MSTPENDING_MASK); - - return result; -} - -status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state == kIdleState) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* There is no necessity to disable interrupts as we read a single integer value */ - *count = handle->transferCount; - return kStatus_Success; -} - -void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - uint32_t status; - uint32_t master_state; - - if (handle->state != kIdleState) - { - DMA_AbortTransfer(handle->dmaHandle); - - /* Disable DMA */ - base->MSTCTL = 0; - - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, - I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK); - - /* Wait until module is ready */ - do - { - status = I2C_GetStatusFlags(base); - } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); - - /* Clear controller state. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Get the state of the I2C module */ - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if (master_state != I2C_STAT_MSTCODE_IDLE) - { - /* Send a stop command to finalize the transfer. */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - - /* Wait until module is ready */ - do - { - status = I2C_GetStatusFlags(base); - } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); - - /* Clear controller state. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - } - - /* Reset the state to idle. */ - handle->state = kIdleState; - } -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2c_dma.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2c_dma.h deleted file mode 100644 index 794e8ec0ba4..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2c_dma.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_I2C_DMA_H_ -#define _FSL_I2C_DMA_H_ - -#include "fsl_i2c.h" -#include "fsl_dma.h" - -/*! - * @addtogroup i2c_dma_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */ -#define I2C_MAX_DMA_TRANSFER_COUNT 1024 - -/*! @brief I2C master dma handle typedef. */ -typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t; - -/*! @brief I2C master dma transfer callback typedef. */ -typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base, - i2c_master_dma_handle_t *handle, - status_t status, - void *userData); - -/*! @brief I2C master dma transfer structure. */ -struct _i2c_master_dma_handle -{ - uint8_t state; /*!< Transfer state machine current state. */ - uint32_t transferCount; /*!< Indicates progress of the transfer */ - uint32_t remainingBytesDMA; /*!< Remaining byte count to be transferred using DMA. */ - uint8_t *buf; /*!< Buffer pointer for current state. */ - uint32_t remainingSubaddr; - uint8_t subaddrBuf[4]; - dma_handle_t *dmaHandle; /*!< The DMA handler used. */ - i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ - i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */ - void *userData; /*!< Callback parameter passed to callback function. */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus. */ - -/*! - * @name I2C Block DMA Transfer Operation - * @{ - */ - -/*! - * @brief Init the I2C handle which is used in transcational functions - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param callback pointer to user callback function - * @param userData user param passed to the callback function - * @param dmaHandle DMA handle pointer - */ -void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, - i2c_master_dma_handle_t *handle, - i2c_master_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *dmaHandle); - -/*! - * @brief Performs a master dma non-blocking transfer on the I2C bus - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param xfer pointer to transfer structure of i2c_master_transfer_t - * @retval kStatus_Success Sucessully complete the data transmission. - * @retval kStatus_I2C_Busy Previous transmission still not finished. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. - */ -status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Get master transfer status during a dma non-blocking transfer - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param count Number of bytes transferred so far by the non-blocking transaction. - */ -status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count); - -/*! - * @brief Abort a master dma non-blocking transfer in a early time - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - */ -void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle); - -/* @} */ -#if defined(__cplusplus) -} -#endif /*_cplusplus. */ -/*@}*/ -#endif /*_FSL_I2C_DMA_H_*/ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2s.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2s.c deleted file mode 100644 index 878f71e7217..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2s.c +++ /dev/null @@ -1,825 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_i2s.h" -#include "fsl_flexcomm.h" -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* TODO - absent in device header files, should be there */ -#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) -#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) -#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) -#define I2S_FIFOCFG_PACK48_MASK (0x8U) -#define I2S_FIFOCFG_PACK48_SHIFT (3U) -#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) - -/*! @brief I2S states. */ -enum _i2s_state -{ - kI2S_StateIdle = 0x0, /*!< Not performing transfer */ - kI2S_StateTx, /*!< Performing transmit */ - kI2S_StateTxWaitToWriteDummyData, /*!< Wait on FIFO in order to write final dummy data there */ - kI2S_StateTxWaitForEmptyFifo, /*!< Wait for FIFO to be flushed */ - kI2S_StateRx, /*!< Performing receive */ -}; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -static void I2S_Config(I2S_Type *base, const i2s_config_t *config); -static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer); - -/******************************************************************************* - * Code - ******************************************************************************/ - -void I2S_TxInit(I2S_Type *base, const i2s_config_t *config) -{ - uint32_t cfg = 0U; - uint32_t trig = 0U; - - FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_TX); - I2S_Config(base, config); - - /* Configure FIFO */ - - cfg |= I2S_FIFOCFG_ENABLETX(1U); /* enable TX FIFO */ - cfg |= I2S_FIFOCFG_EMPTYTX(1U); /* empty TX FIFO */ - cfg |= I2S_FIFOCFG_TXI2SE0(config->txEmptyZero); /* transmit zero when buffer becomes empty or last item */ - cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ - trig |= I2S_FIFOTRIG_TXLVLENA(1U); /* enable TX FIFO trigger */ - trig |= I2S_FIFOTRIG_TXLVL(config->watermark); /* set TX FIFO trigger level */ - - base->FIFOCFG = cfg; - base->FIFOTRIG = trig; -} - -void I2S_RxInit(I2S_Type *base, const i2s_config_t *config) -{ - uint32_t cfg = 0U; - uint32_t trig = 0U; - - FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_RX); - I2S_Config(base, config); - - /* Configure FIFO */ - - cfg |= I2S_FIFOCFG_ENABLERX(1U); /* enable RX FIFO */ - cfg |= I2S_FIFOCFG_EMPTYRX(1U); /* empty RX FIFO */ - cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ - trig |= I2S_FIFOTRIG_RXLVLENA(1U); /* enable RX FIFO trigger */ - trig |= I2S_FIFOTRIG_RXLVL(config->watermark); /* set RX FIFO trigger level */ - - base->FIFOCFG = cfg; - base->FIFOTRIG = trig; -} - -void I2S_TxGetDefaultConfig(i2s_config_t *config) -{ - config->masterSlave = kI2S_MasterSlaveNormalMaster; - config->mode = kI2S_ModeI2sClassic; - config->rightLow = false; - config->leftJust = false; - config->pdmData = false; - config->sckPol = false; - config->wsPol = false; - config->divider = 1U; - config->oneChannel = false; - config->dataLength = 16U; - config->frameLength = 32U; - config->position = 0U; - config->watermark = 4U; - config->txEmptyZero = true; - config->pack48 = false; -} - -void I2S_RxGetDefaultConfig(i2s_config_t *config) -{ - config->masterSlave = kI2S_MasterSlaveNormalSlave; - config->mode = kI2S_ModeI2sClassic; - config->rightLow = false; - config->leftJust = false; - config->pdmData = false; - config->sckPol = false; - config->wsPol = false; - config->divider = 1U; - config->oneChannel = false; - config->dataLength = 16U; - config->frameLength = 32U; - config->position = 0U; - config->watermark = 4U; - config->txEmptyZero = false; - config->pack48 = false; -} - -static void I2S_Config(I2S_Type *base, const i2s_config_t *config) -{ - assert(config); - - uint32_t cfg1 = 0U; - uint32_t cfg2 = 0U; - - /* set master/slave configuration */ - cfg1 |= I2S_CFG1_MSTSLVCFG(config->masterSlave); - - /* set I2S mode */ - cfg1 |= I2S_CFG1_MODE(config->mode); - - /* set right low (channel swap) */ - cfg1 |= I2S_CFG1_RIGHTLOW(config->rightLow); - - /* set data justification */ - cfg1 |= I2S_CFG1_LEFTJUST(config->leftJust); - - /* set source to PDM dmic */ - cfg1 |= I2S_CFG1_PDMDATA(config->pdmData); - - /* set SCLK polarity */ - cfg1 |= I2S_CFG1_SCK_POL(config->sckPol); - - /* set WS polarity */ - cfg1 |= I2S_CFG1_WS_POL(config->wsPol); - - /* set mono mode */ - cfg1 |= I2S_CFG1_ONECHANNEL(config->oneChannel); - - /* set data length */ - cfg1 |= I2S_CFG1_DATALEN(config->dataLength - 1U); - - /* set frame length */ - cfg2 |= I2S_CFG2_FRAMELEN(config->frameLength - 1U); - - /* set data position of this channel pair within the frame */ - cfg2 |= I2S_CFG2_POSITION(config->position); - - /* write to registers */ - base->CFG1 = cfg1; - base->CFG2 = cfg2; - - /* set the clock divider */ - base->DIV = I2S_DIV_DIV(config->divider - 1U); -} - -void I2S_Deinit(I2S_Type *base) -{ - /* TODO gate FLEXCOMM clock via FLEXCOMM driver */ -} - -void I2S_TxEnable(I2S_Type *base, bool enable) -{ - if (enable) - { - I2S_EnableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag); - I2S_Enable(base); - } - else - { - I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag); - I2S_Disable(base); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - } -} - -void I2S_RxEnable(I2S_Type *base, bool enable) -{ - if (enable) - { - I2S_EnableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag); - I2S_Enable(base); - } - else - { - I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag); - I2S_Disable(base); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - } -} - -static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer) -{ - assert(transfer->data); - if (!transfer->data) - { - return kStatus_InvalidArgument; - } - - assert(transfer->dataSize > 0U); - if (transfer->dataSize <= 0U) - { - return kStatus_InvalidArgument; - } - - if (handle->dataLength == 4U) - { - /* No alignment and data length requirements */ - } - else if ((handle->dataLength >= 5U) && (handle->dataLength <= 8U)) - { - assert((((uint32_t)transfer->data) % 2U) == 0U); - if ((((uint32_t)transfer->data) % 2U) != 0U) - { - /* Data not 2-bytes aligned */ - return kStatus_InvalidArgument; - } - - assert((transfer->dataSize % 2U) == 0U); - if ((transfer->dataSize % 2U) != 0U) - { - /* Data not in pairs of left/right channel bytes */ - return kStatus_InvalidArgument; - } - } - else if ((handle->dataLength >= 9U) && (handle->dataLength <= 16U)) - { - assert((((uint32_t)transfer->data) % 4U) == 0U); - if ((((uint32_t)transfer->data) % 4U) != 0U) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - - assert((transfer->dataSize % 4U) == 0U); - if ((transfer->dataSize % 4U) != 0U) - { - /* Data lenght not multiply of 4 */ - return kStatus_InvalidArgument; - } - } - else if ((handle->dataLength >= 17U) && (handle->dataLength <= 24U)) - { - assert((transfer->dataSize % 6U) == 0U); - if ((transfer->dataSize % 6U) != 0U) - { - /* Data lenght not multiply of 6 */ - return kStatus_InvalidArgument; - } - - assert(!((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U))); - if ((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U)) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - } - else /* if (handle->dataLength >= 25U) */ - { - assert((((uint32_t)transfer->data) % 4U) == 0U); - if ((((uint32_t)transfer->data) % 4U) != 0U) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - - if (handle->oneChannel) - { - assert((transfer->dataSize % 4U) == 0U); - if ((transfer->dataSize % 4U) != 0U) - { - /* Data lenght not multiply of 4 */ - return kStatus_InvalidArgument; - } - } - else - { - assert((transfer->dataSize % 8U) == 0U); - if ((transfer->dataSize % 8U) != 0U) - { - /* Data lenght not multiply of 8 */ - return kStatus_InvalidArgument; - } - } - } - - return kStatus_Success; -} - -void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) -{ - assert(handle); - - /* Clear out the handle */ - memset(handle, 0U, sizeof(*handle)); - - /* Save callback and user data */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Remember some items set previously by configuration */ - handle->watermark = ((base->FIFOTRIG & I2S_FIFOTRIG_TXLVL_MASK) >> I2S_FIFOTRIG_TXLVL_SHIFT); - handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT); - handle->dataLength = ((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; - handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT); - - handle->useFifo48H = false; - - /* Register IRQ handling */ - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2S_TxHandleIRQ, handle); -} - -status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) -{ - assert(handle); - if (!handle) - { - return kStatus_InvalidArgument; - } - - status_t result; - - result = I2S_ValidateBuffer(handle, &transfer); - if (result != kStatus_Success) - { - return result; - } - - if (handle->i2sQueue[handle->queueUser].dataSize) - { - /* Previously prepared buffers not processed yet */ - return kStatus_I2S_Busy; - } - - handle->state = kI2S_StateTx; - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_TXLVL_MASK)) | I2S_FIFOTRIG_TXLVL(handle->watermark); - I2S_TxEnable(base, true); - - return kStatus_Success; -} - -void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle) -{ - assert(handle); - - /* Disable I2S operation and interrupts */ - I2S_TxEnable(base, false); - - /* Reset state */ - handle->state = kI2S_StateIdle; - - /* Clear transfer queue */ - memset((void *)&handle->i2sQueue, 0U, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); - handle->queueDriver = 0U; - handle->queueUser = 0U; -} - -void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) -{ - assert(handle); - - /* Clear out the handle */ - memset(handle, 0U, sizeof(*handle)); - - /* Save callback and user data */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Remember some items set previously by configuration */ - handle->watermark = ((base->FIFOTRIG & I2S_FIFOTRIG_RXLVL_MASK) >> I2S_FIFOTRIG_RXLVL_SHIFT); - handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT); - handle->dataLength = ((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; - handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT); - - handle->useFifo48H = false; - - /* Register IRQ handling */ - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2S_RxHandleIRQ, handle); -} - -status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) -{ - assert(handle); - if (!handle) - { - return kStatus_InvalidArgument; - } - - status_t result; - - result = I2S_ValidateBuffer(handle, &transfer); - if (result != kStatus_Success) - { - return result; - } - - if (handle->i2sQueue[handle->queueUser].dataSize) - { - /* Previously prepared buffers not processed yet */ - return kStatus_I2S_Busy; - } - - handle->state = kI2S_StateRx; - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_RXLVL_MASK)) | I2S_FIFOTRIG_RXLVL(handle->watermark); - I2S_RxEnable(base, true); - - return kStatus_Success; -} - -void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle) -{ - assert(handle); - - /* Disable I2S operation and interrupts */ - I2S_RxEnable(base, false); - - /* Reset state */ - handle->state = kI2S_StateIdle; - - /* Clear transfer queue */ - memset((void *)&handle->i2sQueue, 0U, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); - handle->queueDriver = 0U; - handle->queueUser = 0U; -} - -status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) -{ - assert(handle); - if (!handle) - { - return kStatus_InvalidArgument; - } - - assert(count); - if (!count) - { - return kStatus_InvalidArgument; - } - - if (handle->state == kI2S_StateIdle) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->transferCount; - - return kStatus_Success; -} - -status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) -{ - assert(handle); - if (!handle) - { - return kStatus_InvalidArgument; - } - - assert(count); - if (!count) - { - return kStatus_InvalidArgument; - } - - if (handle->state == kI2S_StateIdle) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->errorCount; - - return kStatus_Success; -} - -void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) -{ - uint32_t intstat = base->FIFOINTSTAT; - uint32_t data; - - if (intstat & I2S_FIFOINTSTAT_TXERR_MASK) - { - handle->errorCount++; - - /* Clear TX error interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_TXERR(1U); - } - - if (intstat & I2S_FIFOINTSTAT_TXLVL_MASK) - { - if (handle->state == kI2S_StateTx) - { - /* Send data */ - - while ((base->FIFOSTAT & I2S_FIFOSTAT_TXNOTFULL_MASK) && - (handle->i2sQueue[handle->queueDriver].dataSize > 0U)) - { - /* Write output data */ - if (handle->dataLength == 4U) - { - data = *(handle->i2sQueue[handle->queueDriver].data); - base->FIFOWR = ((data & 0xF0U) << 12U) | (data & 0xFU); - handle->i2sQueue[handle->queueDriver].data++; - handle->transferCount++; - handle->i2sQueue[handle->queueDriver].dataSize--; - } - else if (handle->dataLength <= 8U) - { - data = *((uint16_t *)handle->i2sQueue[handle->queueDriver].data); - base->FIFOWR = ((data & 0xFF00U) << 8U) | (data & 0xFFU); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); - } - else if (handle->dataLength <= 16U) - { - base->FIFOWR = *((uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); - } - else if (handle->dataLength <= 24U) - { - if (handle->pack48) - { - if (handle->useFifo48H) - { - base->FIFOWR48H = *((uint16_t *)(handle->i2sQueue[handle->queueDriver].data)); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); - handle->useFifo48H = false; - } - else - { - base->FIFOWR = *((uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); - handle->useFifo48H = true; - } - } - else - { - data = (uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++)); - data |= ((uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++))) << 8U; - data |= ((uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++))) << 16U; - if (handle->useFifo48H) - { - base->FIFOWR48H = data; - handle->useFifo48H = false; - } - else - { - base->FIFOWR = data; - handle->useFifo48H = true; - } - handle->transferCount += 3U; - handle->i2sQueue[handle->queueDriver].dataSize -= 3U; - } - } - else /* if (handle->dataLength <= 32U) */ - { - base->FIFOWR = *((uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); - } - - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* Actual data buffer sent out, switch to a next one */ - handle->queueDriver = (handle->queueDriver + 1U) % I2S_NUM_BUFFERS; - - /* Notify user */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); - } - - /* Check if the next buffer contains anything to send */ - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* Everything has been written to FIFO */ - handle->state = kI2S_StateTxWaitToWriteDummyData; - break; - } - } - } - } - else if (handle->state == kI2S_StateTxWaitToWriteDummyData) - { - /* Write dummy data */ - if ((handle->dataLength > 16U) && (handle->dataLength < 25U)) - { - if (handle->useFifo48H) - { - base->FIFOWR48H = 0U; - handle->useFifo48H = false; - } - else - { - base->FIFOWR = 0U; - base->FIFOWR48H = 0U; - } - } - else - { - base->FIFOWR = 0U; - } - - /* Next time invoke this handler when FIFO becomes empty (TX level 0) */ - base->FIFOTRIG &= ~I2S_FIFOTRIG_TXLVL_MASK; - handle->state = kI2S_StateTxWaitForEmptyFifo; - } - else if (handle->state == kI2S_StateTxWaitForEmptyFifo) - { - /* FIFO, including additional dummy data, has been emptied now, - * all relevant data should have been output from peripheral */ - - /* Stop transfer */ - I2S_Disable(base); - I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - - /* Reset state */ - handle->state = kI2S_StateIdle; - - /* Notify user */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); - } - } - else - { - /* Do nothing */ - } - - /* Clear TX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_TXLVL(1U); - } -} - -void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) -{ - uint32_t intstat = base->FIFOINTSTAT; - uint32_t data; - - if (intstat & I2S_FIFOINTSTAT_RXERR_MASK) - { - handle->errorCount++; - - /* Clear RX error interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXERR(1U); - } - - if (intstat & I2S_FIFOINTSTAT_RXLVL_MASK) - { - while ((base->FIFOSTAT & I2S_FIFOSTAT_RXNOTEMPTY_MASK) && (handle->i2sQueue[handle->queueDriver].dataSize > 0U)) - { - /* Read input data */ - if (handle->dataLength == 4U) - { - data = base->FIFORD; - *(handle->i2sQueue[handle->queueDriver].data) = ((data & 0x000F0000U) >> 12U) | (data & 0x0000000FU); - handle->i2sQueue[handle->queueDriver].data++; - handle->transferCount++; - handle->i2sQueue[handle->queueDriver].dataSize--; - } - else if (handle->dataLength <= 8U) - { - data = base->FIFORD; - *((uint16_t *)handle->i2sQueue[handle->queueDriver].data) = ((data >> 8U) & 0xFF00U) | (data & 0xFFU); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); - } - else if (handle->dataLength <= 16U) - { - data = base->FIFORD; - *((uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); - } - else if (handle->dataLength <= 24U) - { - if (handle->pack48) - { - if (handle->useFifo48H) - { - data = base->FIFORD48H; - handle->useFifo48H = false; - - *((uint16_t *)handle->i2sQueue[handle->queueDriver].data) = data; - handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); - } - else - { - data = base->FIFORD; - handle->useFifo48H = true; - - *((uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); - } - } - else - { - if (handle->useFifo48H) - { - data = base->FIFORD48H; - handle->useFifo48H = false; - } - else - { - data = base->FIFORD; - handle->useFifo48H = true; - } - - *(handle->i2sQueue[handle->queueDriver].data++) = data & 0xFFU; - *(handle->i2sQueue[handle->queueDriver].data++) = (data >> 8U) & 0xFFU; - *(handle->i2sQueue[handle->queueDriver].data++) = (data >> 16U) & 0xFFU; - handle->transferCount += 3U; - handle->i2sQueue[handle->queueDriver].dataSize -= 3U; - } - } - else /* if (handle->dataLength <= 32U) */ - { - data = base->FIFORD; - *((uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); - } - - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* Actual data buffer filled with input data, switch to a next one */ - handle->queueDriver = (handle->queueDriver + 1U) % I2S_NUM_BUFFERS; - - /* Notify user */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); - } - - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* No other buffer prepared to receive data into */ - - /* Disable I2S operation and interrupts */ - I2S_Disable(base); - I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - - /* Reset state */ - handle->state = kI2S_StateIdle; - - /* Notify user */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); - } - - /* Clear RX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); - - return; - } - } - } - - /* Clear RX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); - } -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2s.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2s.h deleted file mode 100644 index d7bc3e1ba57..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2s.h +++ /dev/null @@ -1,484 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_I2S_H_ -#define _FSL_I2S_H_ - -#include "fsl_device_registers.h" -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup i2s_driver - * @{ - */ - -/*! @file */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2S driver version 2.0.0. - * - * Current version: 2.0.0 - * - * Change log: - * - Version 2.0.0 - * - initial version - */ -#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -#ifndef I2S_NUM_BUFFERS - -/*! @brief Number of buffers . */ -#define I2S_NUM_BUFFERS (4) - -#endif - -/*! @brief I2S status codes. */ -enum _i2s_status -{ - kStatus_I2S_BufferComplete = - MAKE_STATUS(kStatusGroup_I2S, 0), /*!< Transfer from/into a single buffer has completed */ - kStatus_I2S_Done = MAKE_STATUS(kStatusGroup_I2S, 1), /*!< All buffers transfers have completed */ - kStatus_I2S_Busy = - MAKE_STATUS(kStatusGroup_I2S, 2), /*!< Already performing a transfer and cannot queue another buffer */ -}; - -/*! - * @brief I2S flags. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -typedef enum _i2s_flags -{ - kI2S_TxErrorFlag = I2S_FIFOINTENSET_TXERR_MASK, /*!< TX error interrupt */ - kI2S_TxLevelFlag = I2S_FIFOINTENSET_TXLVL_MASK, /*!< TX level interrupt */ - kI2S_RxErrorFlag = I2S_FIFOINTENSET_RXERR_MASK, /*!< RX error interrupt */ - kI2S_RxLevelFlag = I2S_FIFOINTENSET_RXLVL_MASK /*!< RX level interrupt */ -} i2s_flags_t; - -/*! @brief Master / slave mode. */ -typedef enum _i2s_master_slave -{ - kI2S_MasterSlaveNormalSlave = 0x0, /*!< Normal slave */ - kI2S_MasterSlaveWsSyncMaster = 0x1, /*!< WS synchronized master */ - kI2S_MasterSlaveExtSckMaster = 0x2, /*!< Master using existing SCK */ - kI2S_MasterSlaveNormalMaster = 0x3 /*!< Normal master */ -} i2s_master_slave_t; - -/*! @brief I2S mode. */ -typedef enum _i2s_mode -{ - kI2S_ModeI2sClassic = 0x0, /*!< I2S classic mode */ - kI2S_ModeDspWs50 = 0x1, /*!< DSP mode, WS having 50% duty cycle */ - kI2S_ModeDspWsShort = 0x2, /*!< DSP mode, WS having one clock long pulse */ - kI2S_ModeDspWsLong = 0x3 /*!< DSP mode, WS having one data slot long pulse */ -} i2s_mode_t; - -/*! @brief I2S configuration structure. */ -typedef struct _i2s_config -{ - i2s_master_slave_t masterSlave; /*!< Master / slave configuration */ - i2s_mode_t mode; /*!< I2S mode */ - bool rightLow; /*!< Right channel data in low portion of FIFO */ - bool leftJust; /*!< Left justify data in FIFO */ - bool pdmData; /*!< Data source is the D-Mic subsystem */ - bool sckPol; /*!< SCK polarity */ - bool wsPol; /*!< WS polarity */ - uint16_t divider; /*!< Flexcomm function clock divider (1 - 4096) */ - bool oneChannel; /*!< true mono, false stereo */ - uint8_t dataLength; /*!< Data length (4 - 32) */ - uint16_t frameLength; /*!< Frame width (4 - 512) */ - uint16_t position; /*!< Data position in the frame */ - uint8_t watermark; /*!< FIFO trigger level */ - bool txEmptyZero; /*!< Transmit zero when buffer becomes empty or last item */ - bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit - values) */ -} i2s_config_t; - -/*! @brief Buffer to transfer from or receive audio data into. */ -typedef struct _i2s_transfer -{ - volatile uint8_t *data; /*!< Pointer to data buffer. */ - volatile size_t dataSize; /*!< Buffer size in bytes. */ -} i2s_transfer_t; - -/*! @brief Transactional state of the intialized transfer or receive I2S operation. */ -typedef struct _i2s_handle i2s_handle_t; - -/*! - * @brief Callback function invoked from transactional API - * on completion of a single buffer transfer. - * - * @param base I2S base pointer. - * @param handle pointer to I2S transaction. - * @param completionStatus status of the transaction. - * @param userData optional pointer to user arguments data. - */ -typedef void (*i2s_transfer_callback_t)(I2S_Type *base, - i2s_handle_t *handle, - status_t completionStatus, - void *userData); - -/*! @brief Members not to be accessed / modified outside of the driver. */ -struct _i2s_handle -{ - uint32_t state; /*!< State of transfer */ - i2s_transfer_callback_t completionCallback; /*!< Callback function pointer */ - void *userData; /*!< Application data passed to callback */ - bool oneChannel; /*!< true mono, false stereo */ - uint8_t dataLength; /*!< Data length (4 - 32) */ - bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit - values) */ - bool useFifo48H; /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */ - volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ - volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ - volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ - volatile uint32_t errorCount; /*!< Number of buffer underruns/overruns */ - volatile uint32_t transferCount; /*!< Number of bytes transferred */ - volatile uint8_t watermark; /*!< FIFO trigger level */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S transmission using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_TxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the I2S driver. - * - * @param base I2S base pointer. - * @param config pointer to I2S configuration structure. - */ -void I2S_TxInit(I2S_Type *base, const i2s_config_t *config); - -/*! - * @brief Initializes the FLEXCOMM peripheral for I2S receive functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S receive using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_RxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the I2S driver. - * - * @param base I2S base pointer. - * @param config pointer to I2S configuration structure. - */ -void I2S_RxInit(I2S_Type *base, const i2s_config_t *config); - -/*! - * @brief Sets the I2S Tx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_TxInit(). - * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified - * before calling I2S_TxInit(). - * Example: - @code - i2s_config_t config; - I2S_TxGetDefaultConfig(&config); - @endcode - * - * Default values: - * @code - * config->masterSlave = kI2S_MasterSlaveNormalMaster; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = true; - * config->pack48 = false; - * @endcode - * - * @param config pointer to I2S configuration structure. - */ -void I2S_TxGetDefaultConfig(i2s_config_t *config); - -/*! - * @brief Sets the I2S Rx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_RxInit(). - * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified - * before calling I2S_RxInit(). - * Example: - @code - i2s_config_t config; - I2S_RxGetDefaultConfig(&config); - @endcode - * - * Default values: - * @code - * config->masterSlave = kI2S_MasterSlaveNormalSlave; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = false; - * config->pack48 = false; - * @endcode - * - * @param config pointer to I2S configuration structure. - */ -void I2S_RxGetDefaultConfig(i2s_config_t *config); - -/*! - * @brief De-initializes the I2S peripheral. - * - * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit - * or I2S_RxInit is called to enable the clock. - * - * @param base I2S base pointer. - */ -void I2S_Deinit(I2S_Type *base); - -/*! @} */ - -/*! - * @name Non-blocking API - * @{ - */ - -/*! - * @brief Initializes handle for transfer of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); - -/*! - * @brief Begins or queue sending of the given data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts sending of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Initializes handle for reception of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); - -/*! - * @brief Begins or queue reception of data into given buffer. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. - */ -status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts receiving of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Returns number of bytes transferred so far. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param[out] count number of bytes transferred so far by the non-blocking transaction. - * - * @retval kStatus_Success - * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); - -/*! - * @brief Returns number of buffer underruns or overruns. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param[out] count number of transmit errors encountered so far by the non-blocking transaction. - * - * @retval kStatus_Success - * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); - -/*! @} */ - -/*! - * @name Enable / disable - * @{ - */ - -/*! - * @brief Enables I2S operation. - * - * @param base I2S base pointer. - */ -static inline void I2S_Enable(I2S_Type *base) -{ - base->CFG1 |= I2S_CFG1_MAINENABLE(1U); -} - -/*! - * @brief Disables I2S operation. - * - * @param base I2S base pointer. - */ -static inline void I2S_Disable(I2S_Type *base) -{ - base->CFG1 &= (~I2S_CFG1_MAINENABLE(1U)); -} - -/*! @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables I2S FIFO interrupts. - * - * @param base I2S base pointer. - * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2S_EnableInterrupts(I2S_Type *base, uint32_t interruptMask) -{ - base->FIFOINTENSET = interruptMask; -} - -/*! - * @brief Disables I2S FIFO interrupts. - * - * @param base I2S base pointer. - * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2S_DisableInterrupts(I2S_Type *base, uint32_t interruptMask) -{ - base->FIFOINTENCLR = interruptMask; -} - -/*! - * @brief Returns the set of currently enabled I2S FIFO interrupts. - * - * @param base I2S base pointer. - * - * @return A bitmask composed of #i2s_flags_t enumerators OR'd together - * to indicate the set of enabled interrupts. - */ -static inline uint32_t I2S_GetEnabledInterrupts(I2S_Type *base) -{ - return base->FIFOINTENSET; -} - -/*! - * @brief Invoked from interrupt handler when transmit FIFO level decreases. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Invoked from interrupt handler when receive FIFO level decreases. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); - -/*! @} */ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2S_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2s_dma.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2s_dma.c deleted file mode 100644 index 3b69be4772e..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2s_dma.c +++ /dev/null @@ -1,626 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_dma.h" -#include "fsl_i2s_dma.h" -#include "fsl_flexcomm.h" -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define DMA_MAX_TRANSFER_BYTES (DMA_MAX_TRANSFER_COUNT * sizeof(uint32_t)) -#define DMA_DESCRIPTORS (2U) - -/*i2sQueue[handle->queueUser].dataSize) - { - /* Previously prepared buffers not processed yet, reject request */ - return kStatus_I2S_Busy; - } - - /* Enqueue data */ - privateHandle->descriptorQueue[handle->queueUser].data = transfer.data; - privateHandle->descriptorQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - return kStatus_Success; -} - -static uint32_t I2S_GetInstance(I2S_Type *base) -{ - uint32_t i; - - for (i = 0U; i < ARRAY_SIZE(s_I2sBaseAddrs); i++) - { - if ((uint32_t)base == s_I2sBaseAddrs[i]) - { - return i; - } - } - - assert(false); - return 0U; -} - -static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle) -{ - DMA_DisableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); -} - -static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle) -{ - if (handle->state != kI2S_DmaStateIdle) - { - DMA_EnableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); - } -} - -void I2S_TxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData) -{ - assert(handle); - assert(dmaHandle); - - uint32_t instance = I2S_GetInstance(base); - i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - - memset(handle, 0U, sizeof(*handle)); - handle->state = kI2S_DmaStateIdle; - handle->dmaHandle = dmaHandle; - handle->completionCallback = callback; - handle->userData = userData; - - memset(privateHandle, 0U, sizeof(*privateHandle)); - privateHandle->base = base; - privateHandle->handle = handle; - - DMA_SetCallback(dmaHandle, I2S_DMACallback, privateHandle); -} - -status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) -{ - status_t status; - - I2S_DisableDMAInterrupts(handle); - - /* Enqueue transfer buffer */ - status = I2S_EnqueueUserBuffer(base, handle, transfer); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - - /* Initialize DMA transfer */ - if (handle->state == kI2S_DmaStateIdle) - { - handle->state = kI2S_DmaStateTx; - status = I2S_StartTransferDMA(base, handle); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - } - - I2S_AddTransferDMA(base, handle); - I2S_EnableDMAInterrupts(handle); - - return kStatus_Success; -} - -void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - assert(handle); - assert(handle->dmaHandle); - - uint32_t instance = I2S_GetInstance(base); - i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - - I2S_DisableDMAInterrupts(handle); - - /* Abort operation */ - DMA_AbortTransfer(handle->dmaHandle); - - if (handle->state == kI2S_DmaStateTx) - { - /* Wait until all transmitted data get out of FIFO */ - while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) - { - } - /* The last piece of valid data can be still being transmitted from I2S at this moment */ - - /* Write additional data to FIFO */ - base->FIFOWR = 0U; - while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) - { - } - /* At this moment the additional data are out of FIFO, starting being transmitted. - * This means the preceding valid data has been just transmitted and we can stop I2S. */ - I2S_TxEnableDMA(base, false); - } - else - { - I2S_RxEnableDMA(base, false); - } - - I2S_Disable(base); - - /* Reset state */ - handle->state = kI2S_DmaStateIdle; - - /* Clear transfer queue */ - memset((void *)&(handle->i2sQueue), 0U, sizeof(handle->i2sQueue)); - handle->queueDriver = 0U; - handle->queueUser = 0U; - - /* Clear internal state */ - memset((void *)&(privateHandle->descriptorQueue), 0U, sizeof(privateHandle->descriptorQueue)); - memset((void *)&(privateHandle->enqueuedBytes), 0U, sizeof(privateHandle->enqueuedBytes)); - privateHandle->enqueuedBytesStart = 0U; - privateHandle->enqueuedBytesEnd = 0U; - privateHandle->dmaDescriptorsUsed = 0U; - privateHandle->descriptor = 0U; - privateHandle->queueDescriptor = 0U; - privateHandle->intA = false; -} - -void I2S_RxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData) -{ - I2S_TxTransferCreateHandleDMA(base, handle, dmaHandle, callback, userData); -} - -status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) -{ - status_t status; - - I2S_DisableDMAInterrupts(handle); - - /* Enqueue transfer buffer */ - status = I2S_EnqueueUserBuffer(base, handle, transfer); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - - /* Initialize DMA transfer */ - if (handle->state == kI2S_DmaStateIdle) - { - handle->state = kI2S_DmaStateRx; - status = I2S_StartTransferDMA(base, handle); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - } - - I2S_AddTransferDMA(base, handle); - I2S_EnableDMAInterrupts(handle); - - return kStatus_Success; -} - -static void I2S_TxEnableDMA(I2S_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= I2S_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= (~I2S_FIFOCFG_DMATX_MASK); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - } -} - -static void I2S_RxEnableDMA(I2S_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= I2S_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= (~I2S_FIFOCFG_DMARX_MASK); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - } -} - -static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer) -{ - assert(transfer); - - uint16_t transferBytes; - - if (transfer->dataSize >= (2 * DMA_MAX_TRANSFER_BYTES)) - { - transferBytes = DMA_MAX_TRANSFER_BYTES; - } - else if (transfer->dataSize > DMA_MAX_TRANSFER_BYTES) - { - transferBytes = transfer->dataSize / 2U; - if ((transferBytes % 4U) != 0U) - { - transferBytes -= (transferBytes % 4U); - } - } - else - { - transferBytes = transfer->dataSize; - } - - return transferBytes; -} - -static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - status_t status; - dma_transfer_config_t xferConfig = {0}; - i2s_dma_private_handle_t *privateHandle; - volatile i2s_transfer_t *transfer; - uint16_t transferBytes; - uint32_t instance; - int i; - dma_descriptor_t *descriptor; - dma_descriptor_t *nextDescriptor; - dma_xfercfg_t xfercfg; - - instance = I2S_GetInstance(base); - privateHandle = &(s_DmaPrivateHandle[instance]); - transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); - - transferBytes = I2S_GetTransferBytes(transfer); - - /* Prepare transfer of data via initial DMA transfer descriptor */ - DMA_PrepareTransfer( - &xferConfig, (handle->state == kI2S_DmaStateTx) ? (void *)transfer->data : (void *)&(base->FIFORD), - (handle->state == kI2S_DmaStateTx) ? (void *)&(base->FIFOWR) : (void *)transfer->data, sizeof(uint32_t), - transferBytes, (handle->state == kI2S_DmaStateTx) ? kDMA_MemoryToPeripheral : kDMA_PeripheralToMemory, - (void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U])); - - /* Initial descriptor is stored in another place in memory, but treat it as another descriptor for simplicity */ - privateHandle->dmaDescriptorsUsed = 1U; - privateHandle->intA = false; - - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; - privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; - - transfer->dataSize -= transferBytes; - transfer->data += transferBytes; - - if (transfer->dataSize == 0U) - { - transfer->data = NULL; - privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; - } - - /* Link the DMA descriptors for the case when no additional transfer is queued before the initial one finishes */ - for (i = 0; i < DMA_DESCRIPTORS; i++) - { - descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + i]); - nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + ((i + 1) % DMA_DESCRIPTORS)]); - - xfercfg.valid = true; - xfercfg.reload = true; - xfercfg.swtrig = false; - xfercfg.clrtrig = false; - xfercfg.intA = false; - xfercfg.intB = false; - xfercfg.byteWidth = sizeof(uint32_t); - xfercfg.srcInc = 0U; - xfercfg.dstInc = 0U; - xfercfg.transferCount = 8U; - - DMA_CreateDescriptor(descriptor, &xfercfg, - (handle->state == kI2S_DmaStateTx) ? (void *)&s_DummyBufferTx : (void *)&(base->FIFORD), - (handle->state == kI2S_DmaStateTx) ? (void *)&(base->FIFOWR) : (void *)&s_DummyBufferRx, - (void *)nextDescriptor); - } - - /* Submit and start initial DMA transfer */ - - if (handle->state == kI2S_DmaStateTx) - { - I2S_TxEnableDMA(base, true); - } - else - { - I2S_RxEnableDMA(base, true); - } - - status = DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - if (status != kStatus_Success) - { - return status; - } - - DMA_StartTransfer(handle->dmaHandle); - - I2S_Enable(base); - return kStatus_Success; -} - -static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - dma_xfercfg_t xfercfg; - volatile i2s_transfer_t *transfer; - uint16_t transferBytes; - uint32_t instance; - i2s_dma_private_handle_t *privateHandle; - dma_descriptor_t *descriptor; - dma_descriptor_t *nextDescriptor; - - instance = I2S_GetInstance(base); - privateHandle = &(s_DmaPrivateHandle[instance]); - - while (privateHandle->dmaDescriptorsUsed < DMA_DESCRIPTORS) - { - transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); - - if (transfer->dataSize == 0U) - { - /* Nothing to be added */ - return; - } - - /* Determine currently configured descriptor and the other which it will link to */ - descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); - privateHandle->descriptor = (privateHandle->descriptor + 1U) % DMA_DESCRIPTORS; - nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); - - transferBytes = I2S_GetTransferBytes(transfer); - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; - privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; - - /* Configure descriptor */ - - xfercfg.valid = true; - xfercfg.reload = true; - xfercfg.swtrig = false; - xfercfg.clrtrig = false; - xfercfg.intA = privateHandle->intA; - xfercfg.intB = !privateHandle->intA; - xfercfg.byteWidth = sizeof(uint32_t); - xfercfg.srcInc = (handle->state == kI2S_DmaStateTx) ? 1U : 0U; - xfercfg.dstInc = (handle->state == kI2S_DmaStateTx) ? 0U : 1U; - xfercfg.transferCount = transferBytes / sizeof(uint32_t); - - DMA_CreateDescriptor(descriptor, &xfercfg, - (handle->state == kI2S_DmaStateTx) ? (void *)transfer->data : (void *)&(base->FIFORD), - (handle->state == kI2S_DmaStateTx) ? (void *)&(base->FIFOWR) : (void *)transfer->data, - (void *)nextDescriptor); - - /* Advance internal state */ - - privateHandle->dmaDescriptorsUsed++; - privateHandle->intA = !privateHandle->intA; - - transfer->dataSize -= transferBytes; - transfer->data += transferBytes; - if (transfer->dataSize == 0U) - { - transfer->data = NULL; - privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; - } - } -} - -void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds) -{ - i2s_dma_private_handle_t *privateHandle = (i2s_dma_private_handle_t *)userData; - i2s_dma_handle_t *i2sHandle = privateHandle->handle; - I2S_Type *base = privateHandle->base; - - if (!transferDone || (i2sHandle->state == kI2S_DmaStateIdle)) - { - return; - } - - if (privateHandle->dmaDescriptorsUsed > 0U) - { - /* Finished descriptor, decrease amount of data to be processed */ - - i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize -= - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart]; - i2sHandle->i2sQueue[i2sHandle->queueDriver].data += - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart]; - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] = 0U; - privateHandle->enqueuedBytesStart = (privateHandle->enqueuedBytesStart + 1U) % DMA_DESCRIPTORS; - - privateHandle->dmaDescriptorsUsed--; - - if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U) - { - /* Entire user buffer sent or received - advance to next one */ - i2sHandle->i2sQueue[i2sHandle->queueDriver].data = NULL; - i2sHandle->queueDriver = (i2sHandle->queueDriver + 1U) % I2S_NUM_BUFFERS; - - /* Notify user about buffer completion */ - if (i2sHandle->completionCallback) - { - (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_BufferComplete, i2sHandle->userData); - } - } - } - - if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U) - { - /* All user buffers processed */ - I2S_TransferAbortDMA(base, i2sHandle); - - /* Notify user about completion of the final buffer */ - if (i2sHandle->completionCallback) - { - (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_Done, i2sHandle->userData); - } - } - else - { - /* Enqueue another user buffer to DMA if it could not be done when in I2S_Rx/TxTransferSendDMA */ - I2S_AddTransferDMA(base, i2sHandle); - } -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2s_dma.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2s_dma.h deleted file mode 100644 index 72a39e4da6e..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2s_dma.h +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_I2S_DMA_H_ -#define _FSL_I2S_DMA_H_ - -#include "fsl_device_registers.h" -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -#include "fsl_dma.h" -#include "fsl_i2s.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup i2s_dma_driver - * @{ - */ - -/*! @file */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2S DMA driver version 2.0.0. - * - * Current version: 2.0.0 - * - * Change log: - * - Version 2.0.0 - * - initial version - */ -#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @brief Members not to be accessed / modified outside of the driver. */ -typedef struct _i2s_dma_handle i2s_dma_handle_t; - -/*! - * @brief Callback function invoked from DMA API on completion. - * - * @param base I2S base pointer. - * @param handle pointer to I2S transaction. - * @param completionStatus status of the transaction. - * @param userData optional pointer to user arguments data. - */ -typedef void (*i2s_dma_transfer_callback_t)(I2S_Type *base, - i2s_dma_handle_t *handle, - status_t completionStatus, - void *userData); - -struct _i2s_dma_handle -{ - uint32_t state; /*!< Internal state of I2S DMA transfer */ - i2s_dma_transfer_callback_t completionCallback; /*!< Callback function pointer */ - void *userData; /*!< Application data passed to callback */ - dma_handle_t *dmaHandle; /*!< DMA handle */ - volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ - volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ - volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! @} */ - -/*! - * @name DMA API - * @{ - */ - -/*! - * @brief Initializes handle for transfer of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param dmaHandle pointer to dma handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData); - -/*! - * @brief Begins or queue sending of the given data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts transfer of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle); - -/*! - * @brief Initializes handle for reception of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param dmaHandle pointer to dma handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData); - -/*! - * @brief Begins or queue reception of data into given buffer. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers - * which are not full. - */ -status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Invoked from DMA interrupt handler. - * - * @param handle pointer to DMA handle structure. - * @param userData argument for user callback. - * @param transferDone if transfer was done. - * @param tcds - */ -void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds); - -/*! @} */ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2S_DMA_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_inputmux.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_inputmux.c deleted file mode 100644 index 923585174b0..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_inputmux.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_inputmux.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -void INPUTMUX_Init(INPUTMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_InputMux); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection) -{ - uint32_t pmux_id; - uint32_t output_id; - - /* extract pmux to be used */ - pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT; - /* extract function number */ - output_id = ((uint32_t)(connection)) & 0xffffU; - /* programm signal */ - *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4)) = output_id; -} - -void INPUTMUX_Deinit(INPUTMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_InputMux); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_inputmux.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_inputmux.h deleted file mode 100644 index 3d298558bcd..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_inputmux.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_INPUTMUX_H_ -#define _FSL_INPUTMUX_H_ - -#include "fsl_inputmux_connections.h" -#include "fsl_common.h" - -/*! - * @addtogroup inputmux_driver - * @{ - */ - -/*! @file */ -/*! @file fsl_inputmux_connections.h */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Group interrupt driver version for SDK */ -#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ - /*@}*/ - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @brief Initialize INPUTMUX peripheral. - - * This function enables the INPUTMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * - * @retval None. - */ -void INPUTMUX_Init(INPUTMUX_Type *base); - -/*! - * @brief Attaches a signal - * - * This function gates the INPUTPMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * @param index Destination peripheral to attach the signal to. - * @param connection Selects connection. - * - * @retval None. -*/ -void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection); - -/*! - * @brief Deinitialize INPUTMUX peripheral. - - * This function disables the INPUTMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * - * @retval None. - */ -void INPUTMUX_Deinit(INPUTMUX_Type *base); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_INPUTMUX_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_inputmux_connections.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_inputmux_connections.h deleted file mode 100644 index 5def09224d6..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_inputmux_connections.h +++ /dev/null @@ -1,217 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016, NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_INPUTMUX_CONNECTIONS_ -#define _FSL_INPUTMUX_CONNECTIONS_ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup inputmux_driver - * @{ - */ - -/*! - * @name Input multiplexing connections - * @{ - */ - -/*! @brief Periphinmux IDs */ -#define SCT0_PMUX_ID 0x00U -#define PINTSEL_PMUX_ID 0xC0U -#define DMA_TRIG0_PMUX_ID 0xE0U -#define DMA_OTRIG_PMUX_ID 0x160U -#define FREQMEAS_PMUX_ID 0x180U -#define PMUX_SHIFT 20U - -/*! @brief INPUTMUX connections type */ -typedef enum _inputmux_connection_t -{ - /*!< SCT INMUX. */ - kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_T0Out0ToSct0 = 8U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_T1Out0ToSct0 = 9U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_T2Out0ToSct0 = 10U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_T3Out0ToSct0 = 11U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_T4Out0ToSct0 = 12U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_AdcThcmpIrqToSct0 = 13U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioIntBmatchToSct0 = 14U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToSct0 = 16U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_ArmTxevToSct0 = 17U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DebugHaltedToSct0 = 18U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_SmartCard0TxActivreToSct0 = 19U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_SmartCard0RxActivreToSct0 = 20U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_SmartCard1TxActivreToSct0 = 21U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_SmartCard1RxActivreToSct0 = 22U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_I2s6SclkToSct0 = 23U + (SCT0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_I2sS7clkToSct0 = 24U + (SCT0_PMUX_ID << PMUX_SHIFT), - - /*!< Frequency measure. */ - kINPUTMUX_MainOscToFreqmeas = 0U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Fro12MhzToFreqmeas = 1U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Fro96MhzToFreqmeas = 2U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_WdtOscToFreqmeas = 3U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_32KhzOscToFreqmeas = 4U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_MainClkToFreqmeas = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_a = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_b = 6U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), - - /*!< Pin Interrupt. */ - kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_GpioPort4Pin0ToPintsel = 128U + (PINTSEL_PMUX_ID << PMUX_SHIFT), - /*!< DMA ITRIG. */ - kINPUTMUX_Adc0SeqaIrqToDma = 0U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Adc0SeqbIrqToDma = 1U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq0ToDma = 2U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq1ToDma = 3U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToDma = 4U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer0M1ToDma = 5U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToDma = 6U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToDma = 7U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer2M1ToDma = 8U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToDma = 9U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToDma = 10U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Ctimer4M1ToDma = 11U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_PinInt0ToDma = 12U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_PinInt1ToDma = 13U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_PinInt2ToDma = 14U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_PinInt3ToDma = 15U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Otrig0ToDma = 16U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Otrig1ToDma = 17U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Otrig2ToDma = 18U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Otrig3ToDma = 19U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), - /*!< DMA OTRIG. */ - kINPUTMUX_DmaFlexcomm0RxTrigoutToTriginChannels = 0U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm0TxTrigoutToTriginChannels = 1U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm1RxTrigoutToTriginChannels = 2U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm1TxTrigoutToTriginChannels = 3U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm2RxTrigoutToTriginChannels = 4U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm2TxTrigoutToTriginChannels = 5U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm3RxTrigoutToTriginChannels = 6U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm3TxTrigoutToTriginChannels = 7U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm4RxTrigoutToTriginChannels = 8U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm4TxTrigoutToTriginChannels = 9U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm5RxTrigoutToTriginChannels = 10U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm5TxTrigoutToTriginChannels = 11U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm6RxTrigoutToTriginChannels = 12U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm6TxTrigoutToTriginChannels = 13U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm7RxTrigoutToTriginChannels = 14U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm7TxTrigoutToTriginChannels = 15U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaDmic0Ch0TrigoutToTriginChannels = 16U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_Dmamic0Ch1TrigoutToTriginChannels = 17U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaSpifi0TrigoutToTriginChannels = 18U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaChannel9_TrigoutToTriginChannels = 19U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm8RxTrigoutToTriginChannels = 20U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm8TxTrigoutToTriginChannels = 21U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm9RxTrigoutToTriginChannels = 22U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaFlexcomm9TxTrigoutToTriginChannels = 23U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaSmartcard0RxTrigoutToTriginChannels = 24U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaSmartcard0TxTrigoutToTriginChannels = 25U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaSmartcard1RxTrigoutToTriginChannels = 26U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), - kINPUTMUX_DmaSmartcard1TxTrigoutToTriginChannels = 27U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), -} inputmux_connection_t; - -/*@}*/ - -#endif /* _FSL_INPUTMUX_CONNECTIONS_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_iocon.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_iocon.h deleted file mode 100644 index f175e959020..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_iocon.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_IOCON_H_ -#define _FSL_IOCON_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_iocon - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief IOCON driver version 2.0.0. */ -#define LPC_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/** - * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format - */ -typedef struct _iocon_group -{ - uint32_t port : 8; /* Pin port */ - uint32_t pin : 8; /* Pin number */ - uint32_t modefunc : 16; /* Function and mode */ -} iocon_group_t; - -/** - * @brief IOCON function and mode selection definitions - * @note See the User Manual for specific modes and functions supported by the various pins. - */ - #if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH== 4) - #define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ - #define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ - #define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ - #define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ - #define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ - #define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ - #define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ - #define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ - #define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ - #define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ - #define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ - #define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ - #define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ - #define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ - #define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ - #define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ - #define IOCON_MODE_INACT (0x0 << 4) /*!< No addition pin function */ - #define IOCON_MODE_PULLDOWN (0x1 << 4) /*!< Selects pull-down function */ - #define IOCON_MODE_PULLUP (0x2 << 4) /*!< Selects pull-up function */ - #define IOCON_MODE_REPEATER (0x3 << 4) /*!< Selects pin repeater function */ - #define IOCON_HYS_EN (0x1 << 6) /*!< Enables hysteresis */ - #define IOCON_GPIO_MODE (0x1 << 6) /*!< GPIO Mode */ - #define IOCON_I2C_SLEW (0x1 << 6) /*!< I2C Slew Rate Control */ - #define IOCON_INV_EN (0x1 << 7) /*!< Enables invert function on input */ - #define IOCON_ANALOG_EN (0x0 << 8) /*!< Enables analog function by setting 0 to bit 7 */ - #define IOCON_DIGITAL_EN (0x1 << 8) /*!< Enables digital function by setting 1 to bit 7(default) */ - #define IOCON_STDI2C_EN (0x1 << 9) /*!< I2C standard mode/fast-mode */ - #define IOCON_FASTI2C_EN (0x3 << 9) /*!< I2C Fast-mode Plus and high-speed slave */ - #define IOCON_INPFILT_OFF (0x1 << 9) /*!< Input filter Off for GPIO pins */ - #define IOCON_INPFILT_ON (0x0 << 9) /*!< Input filter On for GPIO pins */ - #define IOCON_OPENDRAIN_EN (0x1 << 11) /*!< Enables open-drain function */ - #define IOCON_S_MODE_0CLK (0x0 << 12) /*!< Bypass input filter */ - #define IOCON_S_MODE_1CLK (0x1 << 12) /*!< Input pulses shorter than 1 filter clock are rejected */ - #define IOCON_S_MODE_2CLK (0x2 << 12) /*!< Input pulses shorter than 2 filter clock2 are rejected */ - #define IOCON_S_MODE_3CLK (0x3 << 12) /*!< Input pulses shorter than 3 filter clock2 are rejected */ - #define IOCON_S_MODE(clks) ((clks) << 12) /*!< Select clocks for digital input filter mode */ - #define IOCON_CLKDIV(div) ((div) << 14) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ -#else - #define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ - #define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ - #define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ - #define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ - #define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ - #define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ - #define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ - #define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ - #define IOCON_MODE_INACT (0x0 << 3) /*!< No addition pin function */ - #define IOCON_MODE_PULLDOWN (0x1 << 3) /*!< Selects pull-down function */ - #define IOCON_MODE_PULLUP (0x2 << 3) /*!< Selects pull-up function */ - #define IOCON_MODE_REPEATER (0x3 << 3) /*!< Selects pin repeater function */ - #define IOCON_HYS_EN (0x1 << 5) /*!< Enables hysteresis */ - #define IOCON_GPIO_MODE (0x1 << 5) /*!< GPIO Mode */ - #define IOCON_I2C_SLEW (0x1 << 5) /*!< I2C Slew Rate Control */ - #define IOCON_INV_EN (0x1 << 6) /*!< Enables invert function on input */ - #define IOCON_ANALOG_EN (0x0 << 7) /*!< Enables analog function by setting 0 to bit 7 */ - #define IOCON_DIGITAL_EN (0x1 << 7) /*!< Enables digital function by setting 1 to bit 7(default) */ - #define IOCON_STDI2C_EN (0x1 << 8) /*!< I2C standard mode/fast-mode */ - #define IOCON_FASTI2C_EN (0x3 << 8) /*!< I2C Fast-mode Plus and high-speed slave */ - #define IOCON_INPFILT_OFF (0x1 << 8) /*!< Input filter Off for GPIO pins */ - #define IOCON_INPFILT_ON (0x0 << 8) /*!< Input filter On for GPIO pins */ - #define IOCON_OPENDRAIN_EN (0x1 << 10) /*!< Enables open-drain function */ - #define IOCON_S_MODE_0CLK (0x0 << 11) /*!< Bypass input filter */ - #define IOCON_S_MODE_1CLK (0x1 << 11) /*!< Input pulses shorter than 1 filter clock are rejected */ - #define IOCON_S_MODE_2CLK (0x2 << 11) /*!< Input pulses shorter than 2 filter clock2 are rejected */ - #define IOCON_S_MODE_3CLK (0x3 << 11) /*!< Input pulses shorter than 3 filter clock2 are rejected */ - #define IOCON_S_MODE(clks) ((clks) << 11) /*!< Select clocks for digital input filter mode */ - #define IOCON_CLKDIV(div) \ - ((div) << 13) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ -#endif -#if defined(__cplusplus) -extern "C" { -#endif - -/** - * @brief Sets I/O Control pin mux - * @param base : The base of IOCON peripheral on the chip - * @param port : GPIO port to mux - * @param pin : GPIO pin to mux - * @param modefunc : OR'ed values of type IOCON_* - * @return Nothing - */ -__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc) -{ - base->PIO[port][pin] = modefunc; -} - -/** - * @brief Set all I/O Control pin muxing - * @param base : The base of IOCON peripheral on the chip - * @param pinArray : Pointer to array of pin mux selections - * @param arrayLength : Number of entries in pinArray - * @return Nothing - */ -__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength) -{ - uint32_t i; - - for (i = 0; i < arrayLength; i++) - { - IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc); - } -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_IOCON_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_lcdc.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_lcdc.c deleted file mode 100644 index b3358a59a8d..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_lcdc.c +++ /dev/null @@ -1,508 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_lcdc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Max value of LCD_POL[PCD]. */ -#define LCD_PCD_MAX \ - ((LCD_POL_PCD_LO_MASK >> LCD_POL_PCD_LO_SHIFT) | \ - (LCD_POL_PCD_HI_MASK >> (LCD_POL_PCD_HI_SHIFT - LCD_POL_PCD_LO_SHIFT))) - -/* Macro to contruct the LCD_POL[PCD]. */ -#if (LCD_POL_PCD_LO_MASK != 0x1F) -#error LCD_POL_PCD_LO is not 5-bit. The macro LCD_POL_PCD_LO_WIDTH should be updated. -#endif -#define LCD_POL_PCD_LO_WIDTH 5U -#define LCD_POL_PCD(pcd) (LCD_POL_PCD_LO(pcd) | LCD_POL_PCD_HI((pcd) >> LCD_POL_PCD_LO_WIDTH)) - -/* Cursor interrupt. */ -#define LCDC_CURSOR_INT_MASK LCD_CRSR_INTMSK_CRSRIM_MASK - -/* Interrupts except cursor interrupt. */ -#define LCDC_NORMAL_INT_MASK \ - (LCD_INTMSK_FUFIM_MASK | LCD_INTMSK_LNBUIM_MASK | LCD_INTMSK_VCOMPIM_MASK | LCD_INTMSK_BERIM_MASK) - -/* Detect the cursor interrupt and normal interrupt bits overlap. */ -#if (LCDC_CURSOR_INT_MASK & LCDC_NORMAL_INT_MASK) -#error Cursor interrupt and normal interrupt overlap. The driver should be updated. -#endif - -/* The max cursor clip value. */ -#define LCDC_CLIP_MAX (LCD_CRSR_CLIP_CRSRCLIPX_MASK >> LCD_CRSR_CLIP_CRSRCLIPX_SHIFT) - -/******************************************************************************* - * Variables - ******************************************************************************/ -static LCD_Type *const s_lcdBases[] = LCD_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -static const clock_ip_name_t s_lcdClocks[] = LCD_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -static const reset_ip_name_t s_lcdResets[] = LCD_RSTS; - -/******************************************************************************* -* Prototypes -******************************************************************************/ - -/*! - * @brief Gets the LCD instance according to the LCD base - * - * @param base LCD peripheral base address. - * @return LCD instance. - */ -static uint32_t LCDC_GetInstance(LCD_Type *base); - -/*! - * @brief Calculate the clock divider to generate desired panel clock. - * - * @param config Pointer to the LCD configuration. - * @param srcClock_Hz The LCD input clock (LCDCLK) frequency in Hz. - * @param divider The divider result. - * @return Return false if no divider available to generate the desired clock, - * otherwise return true; - */ -static bool LCDC_GetClockDivider(const lcdc_config_t *config, uint32_t srcClock_Hz, uint32_t *divider); - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t LCDC_GetInstance(LCD_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_lcdBases); instance++) - { - if (s_lcdBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_lcdBases)); - - return instance; -} - -static bool LCDC_GetClockDivider(const lcdc_config_t *config, uint32_t srcClock_Hz, uint32_t *divider) -{ - uint16_t cpl; - uint32_t pcd; - - *divider = 0U; - - /* Find the PCD. */ - pcd = (srcClock_Hz + (config->panelClock_Hz / 2U)) / config->panelClock_Hz; - - if (pcd <= 1U) - { - if (kLCDC_DisplayTFT == config->display) - { - pcd = 0U; - *divider = LCD_POL_BCD_MASK; - } - else - { - return false; - } - } - else - { - pcd -= 2U; - - /* Verify the PCD value. */ - if (pcd > LCD_PCD_MAX) - { - return false; - } - - if (((kLCDC_DisplaySingleColorSTN8Bit == config->display) && (pcd < 1U)) || - ((kLCDC_DisplayDualColorSTN8Bit == config->display) && (pcd < 4U)) || - ((kLCDC_DisplaySingleMonoSTN4Bit == config->display) && (pcd < 2U)) || - ((kLCDC_DisplaySingleMonoSTN8Bit == config->display) && (pcd < 8U)) || - ((kLCDC_DisplayDualMonoSTN4Bit == config->display) && (pcd < 8U)) || - ((kLCDC_DisplayDualMonoSTN8Bit == config->display) && (pcd < 14U))) - { - return false; - } - } - - if (config->display & LCD_CTRL_LCDTFT_MASK) - { - /* TFT panel. */ - cpl = config->ppl - 1U; - } - else - { - if (config->display & LCD_CTRL_LCDBW_MASK) - { - if (config->display & LCD_CTRL_LCDMONO8_MASK) - { - /* 8-bit monochrome STN panel. */ - cpl = (config->ppl / 8U) - 1U; - } - else - { - /* 4-bit monochrome STN panel. */ - cpl = (config->ppl / 4U) - 1U; - } - } - else - { - /* Color STN panel. */ - cpl = ((config->ppl * 3U) / 8U) - 1U; - } - } - - *divider |= (LCD_POL_CPL(cpl) | LCD_POL_PCD(pcd)); - - return true; -} - -status_t LCDC_Init(LCD_Type *base, const lcdc_config_t *config, uint32_t srcClock_Hz) -{ - assert(config); - assert(srcClock_Hz); - assert((config->ppl & 0xFU) == 0U); - assert((config->upperPanelAddr & 0x07U) == 0U); - assert((config->lowerPanelAddr & 0x07U) == 0U); - - uint32_t reg; - uint32_t divider; - uint32_t instance; - - /* Verify the clock here. */ - if (!LCDC_GetClockDivider(config, srcClock_Hz, ÷r)) - { - return kStatus_InvalidArgument; - } - - instance = LCDC_GetInstance(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(s_lcdClocks[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the module */ - RESET_PeripheralReset(s_lcdResets[instance]); - - /* Set register CTRL. */ - reg = base->CTRL & (LCD_CTRL_LCDVCOMP_MASK | LCD_CTRL_WATERMARK_MASK); - reg |= (uint32_t)(config->dataFormat) | (uint32_t)(config->display) | LCD_CTRL_LCDBPP(config->bpp); - - if (config->swapRedBlue) - { - reg |= LCD_CTRL_BGR_MASK; - } - - base->CTRL = reg; - - /* Clean pending interrupts and disable all interrupts. */ - base->INTCLR = LCDC_NORMAL_INT_MASK; - base->CRSR_INTCLR = LCDC_CURSOR_INT_MASK; - base->INTMSK = 0U; - base->CRSR_INTMSK = 0U; - - /* Configure timing. */ - base->TIMH = LCD_TIMH_PPL((config->ppl / 16U) - 1U) | LCD_TIMH_HSW(config->hsw - 1U) | - LCD_TIMH_HFP(config->hfp - 1U) | LCD_TIMH_HBP(config->hbp - 1U); - - base->TIMV = LCD_TIMV_LPP(config->lpp - 1U) | LCD_TIMV_VSW(config->vsw - 1U) | LCD_TIMV_VFP(config->vfp - 1U) | - LCD_TIMV_VBP(config->vbp - 1U); - - base->POL = (uint32_t)(config->polarityFlags) | LCD_POL_ACB(config->acBiasFreq - 1U) | divider; - - /* Line end configuration. */ - if (config->enableLineEnd) - { - base->LE = LCD_LE_LED(config->lineEndDelay - 1U) | LCD_LE_LEE_MASK; - } - else - { - base->LE = 0U; - } - - /* Set panel frame base address. */ - base->UPBASE = config->upperPanelAddr; - base->LPBASE = config->lowerPanelAddr; - - return kStatus_Success; -} - -void LCDC_Deinit(LCD_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(s_lcdClocks[LCDC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void LCDC_GetDefaultConfig(lcdc_config_t *config) -{ - config->panelClock_Hz = 0U; - config->ppl = 0U; - config->hsw = 0U; - config->hfp = 0U; - config->hbp = 0U; - config->lpp = 0U; - config->vsw = 0U; - config->vfp = 0U; - config->vbp = 0U; - config->acBiasFreq = 1U; - config->polarityFlags = 0U; - config->enableLineEnd = false; - config->lineEndDelay = 0U; - config->upperPanelAddr = 0U; - config->lowerPanelAddr = 0U; - config->bpp = kLCDC_1BPP; - config->dataFormat = kLCDC_LittleEndian; - config->swapRedBlue = false; - config->display = kLCDC_DisplayTFT; -} - -void LCDC_SetPanelAddr(LCD_Type *base, lcdc_panel_t panel, uint32_t addr) -{ - /* The base address must be doubleword aligned. */ - assert((addr & 0x07U) == 0U); - - if (kLCDC_UpperPanel == panel) - { - base->UPBASE = addr; - } - else - { - base->LPBASE = addr; - } -} - -void LCDC_SetPalette(LCD_Type *base, const uint32_t *palette, uint8_t count_words) -{ - assert(count_words <= ARRAY_SIZE(base->PAL)); - - uint32_t i; - - for (i = 0; i < count_words; i++) - { - base->PAL[i] = palette[i]; - } -} - -void LCDC_EnableInterrupts(LCD_Type *base, uint32_t mask) -{ - uint32_t reg; - - reg = mask & LCDC_CURSOR_INT_MASK; - if (reg) - { - base->CRSR_INTMSK |= reg; - } - - reg = mask & LCDC_NORMAL_INT_MASK; - if (reg) - { - base->INTMSK |= reg; - } -} - -void LCDC_DisableInterrupts(LCD_Type *base, uint32_t mask) -{ - uint32_t reg; - - reg = mask & LCDC_CURSOR_INT_MASK; - if (reg) - { - base->CRSR_INTMSK &= ~reg; - } - - reg = mask & LCDC_NORMAL_INT_MASK; - if (reg) - { - base->INTMSK &= ~reg; - } -} - -uint32_t LCDC_GetInterruptsPendingStatus(LCD_Type *base) -{ - uint32_t reg; - - reg = base->CRSR_INTRAW; - reg |= base->INTRAW; - - return reg; -} - -uint32_t LCDC_GetEnabledInterruptsPendingStatus(LCD_Type *base) -{ - uint32_t reg; - - reg = base->CRSR_INTSTAT; - reg |= base->INTSTAT; - - return reg; -} - -void LCDC_ClearInterruptsStatus(LCD_Type *base, uint32_t mask) -{ - uint32_t reg; - - reg = mask & LCDC_CURSOR_INT_MASK; - if (reg) - { - base->CRSR_INTCLR = reg; - } - - reg = mask & LCDC_NORMAL_INT_MASK; - if (reg) - { - base->INTCLR = reg; - } -} - -void LCDC_SetCursorConfig(LCD_Type *base, const lcdc_cursor_config_t *config) -{ - assert(config); - - uint32_t i; - - base->CRSR_CFG = LCD_CRSR_CFG_CRSRSIZE(config->size) | LCD_CRSR_CFG_FRAMESYNC(config->syncMode); - - /* Set position. */ - LCDC_SetCursorPosition(base, 0, 0); - - /* Palette. */ - base->CRSR_PAL0 = ((uint32_t)config->palette0.red << LCD_CRSR_PAL0_RED_SHIFT) | - ((uint32_t)config->palette0.blue << LCD_CRSR_PAL0_BLUE_SHIFT) | - ((uint32_t)config->palette0.green << LCD_CRSR_PAL0_GREEN_SHIFT); - base->CRSR_PAL1 = ((uint32_t)config->palette1.red << LCD_CRSR_PAL1_RED_SHIFT) | - ((uint32_t)config->palette1.blue << LCD_CRSR_PAL1_BLUE_SHIFT) | - ((uint32_t)config->palette1.green << LCD_CRSR_PAL1_GREEN_SHIFT); - - /* Image of cursors. */ - if (kLCDC_CursorSize64 == config->size) - { - assert(config->image[0]); - LCDC_SetCursorImage(base, config->size, 0, config->image[0]); - } - else - { - for (i = 0; i < LCDC_CURSOR_COUNT; i++) - { - if (config->image[i]) - { - LCDC_SetCursorImage(base, config->size, i, config->image[i]); - } - } - } -} - -void LCDC_CursorGetDefaultConfig(lcdc_cursor_config_t *config) -{ - uint32_t i; - - config->size = kLCDC_CursorSize32; - config->syncMode = kLCDC_CursorAsync; - config->palette0.red = 0U; - config->palette0.green = 0U; - config->palette0.blue = 0U; - config->palette1.red = 255U; - config->palette1.green = 255U; - config->palette1.blue = 255U; - - for (i = 0; i < LCDC_CURSOR_COUNT; i++) - { - config->image[i] = (uint32_t *)0; - } -} - -void LCDC_SetCursorPosition(LCD_Type *base, int32_t positionX, int32_t positionY) -{ - uint32_t clipX; - uint32_t clipY; - - if (positionX < 0) - { - clipX = -positionX; - positionX = 0U; - - /* If clip value too large, set to the max value. */ - if (clipX > LCDC_CLIP_MAX) - { - clipX = LCDC_CLIP_MAX; - } - } - else - { - clipX = 0U; - } - - if (positionY < 0) - { - clipY = -positionY; - positionY = 0U; - - /* If clip value too large, set to the max value. */ - if (clipY > LCDC_CLIP_MAX) - { - clipY = LCDC_CLIP_MAX; - } - } - else - { - clipY = 0U; - } - - base->CRSR_CLIP = LCD_CRSR_CLIP_CRSRCLIPX(clipX) | LCD_CRSR_CLIP_CRSRCLIPY(clipY); - base->CRSR_XY = LCD_CRSR_XY_CRSRX(positionX) | LCD_CRSR_XY_CRSRY(positionY); -} - -void LCDC_SetCursorImage(LCD_Type *base, lcdc_cursor_size_t size, uint8_t index, const uint32_t *image) -{ - uint32_t regStart; - uint32_t i; - uint32_t len; - - if (kLCDC_CursorSize64 == size) - { - regStart = 0U; - len = LCDC_CURSOR_IMG_64X64_WORDS; - } - else - { - regStart = index * LCDC_CURSOR_IMG_32X32_WORDS; - len = LCDC_CURSOR_IMG_32X32_WORDS; - } - - for (i = 0U; i < len; i++) - { - base->CRSR_IMG[regStart + i] = image[i]; - } -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_lcdc.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_lcdc.h deleted file mode 100644 index 882038a5bf5..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_lcdc.h +++ /dev/null @@ -1,608 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __FSL_LCDC_H__ -#define __FSL_LCDC_H__ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_lcdc - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LCDC driver version 2.0.0. */ -#define LPC_LCDC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*!@brief How many hardware cursors supports. */ -#define LCDC_CURSOR_COUNT 4 - -/*!@brief LCD cursor image bits per pixel. */ -#define LCDC_CURSOR_IMG_BPP 2 - -/*!@brief LCD 32x32 cursor image size in word(32-bit). */ -#define LCDC_CURSOR_IMG_32X32_WORDS (32 * 32 * LCDC_CURSOR_IMG_BPP / (8 * sizeof(uint32_t))) - -/*!@brief LCD 64x64 cursor image size in word(32-bit). */ -#define LCDC_CURSOR_IMG_64X64_WORDS (64 * 64 * LCDC_CURSOR_IMG_BPP / (8 * sizeof(uint32_t))) - -/*!@brief LCD palette size in words(32-bit). */ -#define LCDC_PALETTE_SIZE_WORDS (ARRAY_SIZE(((LCD_Type *)0)->PAL)) - -/*! - * @brief LCD sigal polarity flags. - */ -enum _lcdc_polarity_flags -{ - kLCDC_InvertVsyncPolarity = LCD_POL_IVS_MASK, /*!< Invert the VSYNC polarity, set to active low. */ - kLCDC_InvertHsyncPolarity = LCD_POL_IHS_MASK, /*!< Invert the HSYNC polarity, set to active low. */ - kLCDC_InvertClkPolarity = LCD_POL_IPC_MASK, /*!< Invert the panel clock polarity, set to - drive data on falling edge. */ - kLCDC_InvertDePolarity = LCD_POL_IOE_MASK, /*!< Invert the data enable (DE) polarity, set to active low. */ -}; - -/*! - * @brief LCD bits per pixel. - */ -typedef enum _lcdc_bpp -{ - kLCDC_1BPP = 0U, /*!< 1 bpp. */ - kLCDC_2BPP = 1U, /*!< 2 bpp. */ - kLCDC_4BPP = 2U, /*!< 4 bpp. */ - kLCDC_8BPP = 3U, /*!< 8 bpp. */ - kLCDC_16BPP = 4U, /*!< 16 bpp. */ - kLCDC_24BPP = 5U, /*!< 24 bpp, TFT panel only. */ - kLCDC_16BPP565 = 6U, /*!< 16 bpp, 5:6:5 mode. */ - kLCDC_12BPP = 7U, /*!< 12 bpp, 4:4:4 mode. */ -} lcdc_bpp_t; - -/*! - * @brief The types of display panel. - */ -typedef enum _lcdc_display -{ - kLCDC_DisplayTFT = LCD_CTRL_LCDTFT_MASK, /*!< Active matrix TFT panels with up to 24-bit bus interface. */ - kLCDC_DisplaySingleMonoSTN4Bit = LCD_CTRL_LCDBW_MASK, /*!< Single-panel monochrome STN (4-bit bus interface). */ - kLCDC_DisplaySingleMonoSTN8Bit = - LCD_CTRL_LCDBW_MASK | LCD_CTRL_LCDMONO8_MASK, /*!< Single-panel monochrome STN (8-bit bus interface). */ - kLCDC_DisplayDualMonoSTN4Bit = - LCD_CTRL_LCDBW_MASK | LCD_CTRL_LCDDUAL_MASK, /*!< Dual-panel monochrome STN (4-bit bus interface). */ - kLCDC_DisplayDualMonoSTN8Bit = LCD_CTRL_LCDBW_MASK | LCD_CTRL_LCDMONO8_MASK | - LCD_CTRL_LCDDUAL_MASK, /*!< Dual-panel monochrome STN (8-bit bus interface). */ - kLCDC_DisplaySingleColorSTN8Bit = 0U, /*!< Single-panel color STN (8-bit bus interface). */ - kLCDC_DisplayDualColorSTN8Bit = LCD_CTRL_LCDDUAL_MASK, /*!< Dual-panel coor STN (8-bit bus interface). */ -} lcdc_display_t; - -/*! - * @brief LCD panel buffer data format. - */ -typedef enum _lcdc_data_format -{ - kLCDC_LittleEndian = 0U, /*!< Little endian byte, little endian pixel. */ - kLCDC_BigEndian = LCD_CTRL_BEPO_MASK | LCD_CTRL_BEBO_MASK, /*!< Big endian byte, big endian pixel. */ - kLCDC_WinCeMode = LCD_CTRL_BEPO_MASK, /*!< little-endian byte, big-endian pixel for Windows CE mode. */ -} lcdc_data_format_t; - -/*! - * @brief LCD configuration structure. - */ -typedef struct _lcdc_config -{ - uint32_t panelClock_Hz; /*!< Panel clock in Hz. */ - uint16_t ppl; /*!< Pixels per line, it must could be divided by 16. */ - uint8_t hsw; /*!< HSYNC pulse width. */ - uint8_t hfp; /*!< Horizontal front porch. */ - uint8_t hbp; /*!< Horizontal back porch. */ - uint16_t lpp; /*!< Lines per panal. */ - uint8_t vsw; /*!< VSYNC pulse width. */ - uint8_t vfp; /*!< Vrtical front porch. */ - uint8_t vbp; /*!< Vertical back porch. */ - uint8_t acBiasFreq; /*!< The number of line clocks between AC bias pin toggling. Only used for STN display. */ - uint16_t polarityFlags; /*!< OR'ed value of @ref _lcdc_polarity_flags, used to contol the signal polarity. */ - bool enableLineEnd; /*!< Enable line end or not, the line end is a positive pulse with 4 panel clock. */ - uint8_t lineEndDelay; /*!< The panel clocks between the last pixel of line and the start of line end. */ - uint32_t upperPanelAddr; /*!< LCD upper panel base address, must be double-word(64-bit) align. */ - uint32_t lowerPanelAddr; /*!< LCD lower panel base address, must be double-word(64-bit) align. */ - lcdc_bpp_t bpp; /*!< LCD bits per pixel. */ - lcdc_data_format_t dataFormat; /*!< Data format. */ - bool swapRedBlue; /*!< Set true to use BGR format, set false to choose RGB format. */ - lcdc_display_t display; /*!< The display type. */ -} lcdc_config_t; - -/*! - * @brief LCD vertical compare interrupt mode. - */ -typedef enum _lcdc_vertical_compare_interrupt_mode -{ - kLCDC_StartOfVsync, /*!< Generate vertical compare interrupt at start of VSYNC. */ - kLCDC_StartOfBackPorch, /*!< Generate vertical compare interrupt at start of back porch. */ - kLCDC_StartOfActiveVideo, /*!< Generate vertical compare interrupt at start of active video. */ - kLCDC_StartOfFrontPorch, /*!< Generate vertical compare interrupt at start of front porch. */ -} lcdc_vertical_compare_interrupt_mode_t; - -/*! - * @brief LCD interrupts. - */ -enum _lcdc_interrupts -{ - kLCDC_CursorInterrupt = LCD_CRSR_INTMSK_CRSRIM_MASK, /*!< Cursor image read finished interrupt. */ - kLCDC_FifoUnderflowInterrupt = LCD_INTMSK_FUFIM_MASK, /*!< FIFO underflow interrupt. */ - kLCDC_BaseAddrUpdateInterrupt = LCD_INTMSK_LNBUIM_MASK, /*!< Panel frame base address update interrupt. */ - kLCDC_VerticalCompareInterrupt = LCD_INTMSK_VCOMPIM_MASK, /*!< Vertical compare interrupt. */ - kLCDC_AhbErrorInterrupt = LCD_INTMSK_BERIM_MASK, /*!< AHB master error interrupt. */ -}; - -/*! - * @brief LCD panel frame. - */ -typedef enum _lcdc_panel -{ - kLCDC_UpperPanel, /*!< Upper panel frame. */ - kLCDC_LowerPanel /*!< Lower panel frame. */ -} lcdc_panel_t; - -/*! - * @brief LCD hardware cursor size - */ -typedef enum _lcdc_cursor_size -{ - kLCDC_CursorSize32, /*!< 32x32 pixel cursor. */ - kLCDC_CursorSize64, /*!< 64x64 pixel cursor. */ -} lcdc_cursor_size_t; - -/*! - * @brief LCD hardware cursor palette - */ -typedef struct _lcdc_cursor_palette -{ - uint8_t red; /*!< Red color component. */ - uint8_t green; /*!< Red color component. */ - uint8_t blue; /*!< Red color component. */ -} lcdc_cursor_palette_t; - -/*! - * @brief LCD hardware cursor frame synchronization mode. - */ -typedef enum _lcdc_cursor_sync_mode -{ - kLCDC_CursorAsync, /*!< Cursor change will be displayed immediately. */ - kLCDC_CursorSync, /*!< Cursor change will be displayed in next frame. */ -} lcdc_cursor_sync_mode_t; - -/*! - * @brief LCD hardware cursor configuration structure. - */ -typedef struct _lcdc_cursor_config -{ - lcdc_cursor_size_t size; /*!< Cursor size. */ - lcdc_cursor_sync_mode_t syncMode; /*!< Cursor synchronization mode. */ - lcdc_cursor_palette_t palette0; /*!< Cursor palette 0. */ - lcdc_cursor_palette_t palette1; /*!< Cursor palette 1. */ - uint32_t *image[LCDC_CURSOR_COUNT]; /*!< Pointer to cursor image data. */ -} lcdc_cursor_config_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @name Initialization and Deinitialization - * @{ - */ - -/*! - * @brief Initialize the LCD module. - * - * @param base LCD peripheral base address. - * @param config Pointer to configuration structure, see to @ref lcdc_config_t. - * @param srcClock_Hz The LCD input clock (LCDCLK) frequency in Hz. - * @retval kStatus_Success LCD is initialized successfully. - * @retval kStatus_InvalidArgument Initlialize failed because of invalid argument. - */ -status_t LCDC_Init(LCD_Type *base, const lcdc_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Deinitialize the LCD module. - * - * @param base LCD peripheral base address. - */ -void LCDC_Deinit(LCD_Type *base); - -/*! - * @brief Gets default pre-defined settings for initial configuration. - * - * This function initializes the configuration structure. The default values are: - * - @code - config->panelClock_Hz = 0U; - config->ppl = 0U; - config->hsw = 0U; - config->hfp = 0U; - config->hbp = 0U; - config->lpp = 0U; - config->vsw = 0U; - config->vfp = 0U; - config->vbp = 0U; - config->acBiasFreq = 1U; - config->polarityFlags = 0U; - config->enableLineEnd = false; - config->lineEndDelay = 0U; - config->upperPanelAddr = 0U; - config->lowerPanelAddr = 0U; - config->bpp = kLCDC_1BPP; - config->dataFormat = kLCDC_LittleEndian; - config->swapRedBlue = false; - config->display = kLCDC_DisplayTFT; - @endcode - * - * @param config Pointer to configuration structure. - */ -void LCDC_GetDefaultConfig(lcdc_config_t *config); - -/* @} */ - -/*! - * @name Start and stop - * @{ - */ - -/*! - * @brief Start to output LCD timing signal. - * - * The LCD power up sequence should be: - * 1. Apply power to LCD, here all output signals are held low. - * 2. When LCD power stablized, call @ref LCDC_Start to output the timing signals. - * 3. Apply contrast voltage to LCD panel. Delay if the display requires. - * 4. Call @ref LCDC_PowerUp. - * - * @param base LCD peripheral base address. - */ -static inline void LCDC_Start(LCD_Type *base) -{ - base->CTRL |= LCD_CTRL_LCDEN_MASK; -} - -/*! - * @brief Stop the LCD timing signal. - * - * The LCD power down sequence should be: - * 1. Call @ref LCDC_PowerDown. - * 2. Delay if the display requires. Disable contrast voltage to LCD panel. - * 3. Call @ref LCDC_Stop to disable the timing signals. - * 4. Disable power to LCD. - * - * @param base LCD peripheral base address. - */ -static inline void LCDC_Stop(LCD_Type *base) -{ - base->CTRL &= ~LCD_CTRL_LCDEN_MASK; -} - -/*! - * @brief Power up the LCD and output the pixel signal. - * - * @param base LCD peripheral base address. - */ -static inline void LCDC_PowerUp(LCD_Type *base) -{ - base->CTRL |= LCD_CTRL_LCDPWR_MASK; -} - -/*! - * @brief Power down the LCD and disable the output pixel signal. - * - * @param base LCD peripheral base address. - */ -static inline void LCDC_PowerDown(LCD_Type *base) -{ - base->CTRL &= ~LCD_CTRL_LCDPWR_MASK; -} - -/* @} */ - -/*! - * @name LCD control - * @{ - */ - -/*! - * @brief Sets panel frame base address - * - * @param base LCD peripheral base address. - * @param panel Which panel to set. - * @param addr Frame base address, must be doubleword(64-bit) aligned. - */ -void LCDC_SetPanelAddr(LCD_Type *base, lcdc_panel_t panel, uint32_t addr); - -/*! - * @brief Sets palette - * - * @param base LCD peripheral base address. - * @param palette Pointer to the palette array. - * @param count_words Length of the palette array to set (how many words), it should - * not be larger than LCDC_PALETTE_SIZE_WORDS. - */ -void LCDC_SetPalette(LCD_Type *base, const uint32_t *palette, uint8_t count_words); - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Sets the vertical compare interrupt mode. - * - * @param base LCD peripheral base address. - * @param mode The vertical compare interrupt mode. - */ -static inline void LCDC_SetVerticalInterruptMode(LCD_Type *base, lcdc_vertical_compare_interrupt_mode_t mode) -{ - base->CTRL = (base->CTRL & ~LCD_CTRL_LCDVCOMP_MASK) | LCD_CTRL_LCDVCOMP(mode); -} - -/*! - * @brief Enable LCD interrupts. - * - * Example to enable LCD base address update interrupt and vertical compare - * interrupt: - * - * @code - LCDC_EnableInterrupts(LCD, kLCDC_BaseAddrUpdateInterrupt | kLCDC_VerticalCompareInterrupt); - @endcode - * - * @param base LCD peripheral base address. - * @param mask Interrupts to enable, it is OR'ed value of @ref _lcdc_interrupts. - */ -void LCDC_EnableInterrupts(LCD_Type *base, uint32_t mask); - -/*! - * @brief Disable LCD interrupts. - * - * Example to disable LCD base address update interrupt and vertical compare - * interrupt: - * - * @code - LCDC_DisableInterrupts(LCD, kLCDC_BaseAddrUpdateInterrupt | kLCDC_VerticalCompareInterrupt); - @endcode - * - * @param base LCD peripheral base address. - * @param mask Interrupts to disable, it is OR'ed value of @ref _lcdc_interrupts. - */ -void LCDC_DisableInterrupts(LCD_Type *base, uint32_t mask); - -/*! - * @brief Get LCD interrupt pending status. - * - * Example: - * - * @code - uint32_t status; - - status = LCDC_GetInterruptsPendingStatus(LCD); - - if (kLCDC_BaseAddrUpdateInterrupt & status) - { - // LCD base address update interrupt occurred. - } - - if (kLCDC_VerticalCompareInterrupt & status) - { - // LCD vertical compare interrupt occurred. - } - @endcode - * - * @param base LCD peripheral base address. - * @return Interrupts pending status, it is OR'ed value of @ref _lcdc_interrupts. - */ -uint32_t LCDC_GetInterruptsPendingStatus(LCD_Type *base); - -/*! - * @brief Get LCD enabled interrupt pending status. - * - * This function is similar with @ref LCDC_GetInterruptsPendingStatus, the only - * difference is, this function only returns the pending status of the - * interrupts that have been enabled using @ref LCDC_EnableInterrupts. - * - * @param base LCD peripheral base address. - * @return Interrupts pending status, it is OR'ed value of @ref _lcdc_interrupts. - */ -uint32_t LCDC_GetEnabledInterruptsPendingStatus(LCD_Type *base); - -/*! - * @brief Clear LCD interrupts pending status. - * - * Example to clear LCD base address update interrupt and vertical compare - * interrupt pending status: - * - * @code - LCDC_ClearInterruptsStatus(LCD, kLCDC_BaseAddrUpdateInterrupt | kLCDC_VerticalCompareInterrupt); - @endcode - * - * @param base LCD peripheral base address. - * @param mask Interrupts to disable, it is OR'ed value of @ref _lcdc_interrupts. - */ -void LCDC_ClearInterruptsStatus(LCD_Type *base, uint32_t mask); - -/* @} */ - -/*! - * @name Hardware cursor - * @{ - */ - -/*! - * @brief Set the hardware cursor configuration - * - * This function should be called before enabling the hardware cursor. - * It supports initializing multiple cursor images at a time when using - * 32x32 pixels cursor. - * - * For example: - * - * @code - uint32_t cursor0Img[LCDC_CURSOR_IMG_32X32_WORDS] = {...}; - uint32_t cursor2Img[LCDC_CURSOR_IMG_32X32_WORDS] = {...}; - - lcdc_cursor_config_t cursorConfig; - - LCDC_CursorGetDefaultConfig(&cursorConfig); - - cursorConfig.image[0] = cursor0Img; - cursorConfig.image[2] = cursor2Img; - - LCDC_SetCursorConfig(LCD, &cursorConfig); - - LCDC_ChooseCursor(LCD, 0); - LCDC_SetCursorPosition(LCD, 0, 0); - - LCDC_EnableCursor(LCD); - @endcode - * - * In this example, cursor 0 and cursor 2 image data are initialized, but cursor 1 - * and cursor 3 image data are not initialized because image[1] and image[2] are - * all NULL. With this, application could initializes all cursor images it will - * use at the beginning and call @ref LCDC_SetCursorImage directly to display the - * one which it needs. - * - * @param base LCD peripheral base address. - * @param config Pointer to the hardware cursor configuration structure. - */ -void LCDC_SetCursorConfig(LCD_Type *base, const lcdc_cursor_config_t *config); - -/*! - * @brief Get the hardware cursor default configuration - * - * The default configuration values are: - * - * @code - config->size = kLCDC_CursorSize32; - config->syncMode = kLCDC_CursorAsync; - config->palette0.red = 0U; - config->palette0.green = 0U; - config->palette0.blue = 0U; - config->palette1.red = 255U; - config->palette1.green = 255U; - config->palette1.blue = 255U; - config->image[0] = (uint32_t *)0; - config->image[1] = (uint32_t *)0; - config->image[2] = (uint32_t *)0; - config->image[3] = (uint32_t *)0; - @endcode - * - * @param config Pointer to the hardware cursor configuration structure. - */ -void LCDC_CursorGetDefaultConfig(lcdc_cursor_config_t *config); - -/*! - * @brief Enable or disable the cursor. - * - * @param base LCD peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void LCDC_EnableCursor(LCD_Type *base, bool enable) -{ - if (enable) - { - base->CRSR_CTRL |= LCD_CRSR_CTRL_CRSRON_MASK; - } - else - { - base->CRSR_CTRL &= ~LCD_CRSR_CTRL_CRSRON_MASK; - } -} - -/*! - * @brief Choose which cursor to display. - * - * When using 32x32 cursor, the number of cursors supports is @ref LCDC_CURSOR_COUNT. - * When using 64x64 cursor, the LCD only supports one cursor. - * This function selects which cursor to display when using 32x32 cursor. - * When synchronization mode is @ref kLCDC_CursorSync, the change effects in the - * next frame. When synchronization mode is @ref * kLCDC_CursorAsync, change effects - * immediately. - * - * @param base LCD peripheral base address. - * @param index Index of the cursor to display. - * @note The function @ref LCDC_SetCursorPosition must be called after this function - * to show the new cursor. - */ -static inline void LCDC_ChooseCursor(LCD_Type *base, uint8_t index) -{ - base->CRSR_CTRL = (base->CRSR_CTRL & ~LCD_CRSR_CTRL_CRSRNUM1_0_MASK) | LCD_CRSR_CTRL_CRSRNUM1_0(index); -} - -/*! - * @brief Set the position of cursor - * - * When synchronization mode is @ref kLCDC_CursorSync, position change effects - * in the next frame. When synchronization mode is @ref kLCDC_CursorAsync, - * position change effects immediately. - * - * @param base LCD peripheral base address. - * @param positionX X ordinate of the cursor top-left measured in pixels - * @param positionY Y ordinate of the cursor top-left measured in pixels - */ -void LCDC_SetCursorPosition(LCD_Type *base, int32_t positionX, int32_t positionY); - -/*! - * @brief Set the cursor image. - * - * The interrupt @ref kLCDC_CursorInterrupt indicates that last cursor pixel is - * displayed. When the hardware cursor is enabled, - * - * @param base LCD peripheral base address. - * @param size The cursor size. - * @param index Index of the cursor to set when using 32x32 cursor. - * @param image Pointer to the cursor image. When using 32x32 cursor, the image - * size should be LCDC_CURSOR_IMG_32X32_WORDS. When using 64x64 cursor, the image - * size should be LCDC_CURSOR_IMG_64X64_WORDS. - */ -void LCDC_SetCursorImage(LCD_Type *base, lcdc_cursor_size_t size, uint8_t index, const uint32_t *image); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* __FSL_LCDC_H__ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_mcan.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_mcan.c deleted file mode 100644 index 0e70a0385e8..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_mcan.c +++ /dev/null @@ -1,862 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_mcan.h" - -/******************************************************************************* - * Definitons - ******************************************************************************/ - -#define MCAN_TIME_QUANTA_NUM (16U) - -/*! @brief MCAN Internal State. */ -enum _mcan_state -{ - kMCAN_StateIdle = 0x0, /*!< MB/RxFIFO idle.*/ - kMCAN_StateRxData = 0x1, /*!< MB receiving.*/ - kMCAN_StateRxRemote = 0x2, /*!< MB receiving remote reply.*/ - kMCAN_StateTxData = 0x3, /*!< MB transmitting.*/ - kMCAN_StateTxRemote = 0x4, /*!< MB transmitting remote request.*/ - kMCAN_StateRxFifo = 0x5, /*!< RxFIFO receiving.*/ -}; - -/* Typedef for interrupt handler. */ -typedef void (*mcan_isr_t)(CAN_Type *base, mcan_handle_t *handle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get the MCAN instance from peripheral base address. - * - * @param base MCAN peripheral base address. - * @return MCAN instance. - */ -uint32_t MCAN_GetInstance(CAN_Type *base); - -/*! - * @brief Reset the MCAN instance. - * - * @param base MCAN peripheral base address. - */ -static void MCAN_Reset(CAN_Type *base); - -/*! - * @brief Set Baud Rate of MCAN. - * - * This function set the baud rate of MCAN. - * - * @param base MCAN peripheral base address. - * @param sourceClock_Hz Source Clock in Hz. - * @param baudRate_Bps Baud Rate in Bps. - */ -static void MCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateA_Bps); - -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) -/*! - * @brief Set Baud Rate of MCAN FD. - * - * This function set the baud rate of MCAN FD. - * - * @param base MCAN peripheral base address. - * @param sourceClock_Hz Source Clock in Hz. - * @param baudRateD_Bps Baud Rate in Bps. - */ -static void MCAN_SetBaudRateFD(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateD_Bps); -#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */ - -/*! - * @brief Get the element's address when read receive fifo 0. - * - * @param base MCAN peripheral base address. - * @return Address of the element in receive fifo 0. - */ -static uint32_t MCAN_GetRxFifo0ElementAddress(CAN_Type *base); - -/*! - * @brief Get the element's address when read receive fifo 1. - * - * @param base MCAN peripheral base address. - * @return Address of the element in receive fifo 1. - */ -static uint32_t MCAN_GetRxFifo1ElementAddress(CAN_Type *base); - -/*! - * @brief Get the element's address when read receive buffer. - * - * @param base MCAN peripheral base address. - * @param idx Number of the erceive buffer element. - * @return Address of the element in receive buffer. - */ -static uint32_t MCAN_GetRxBufferElementAddress(CAN_Type *base, uint8_t idx); - -/*! - * @brief Get the element's address when read transmit buffer. - * - * @param base MCAN peripheral base address. - * @param idx Number of the transmit buffer element. - * @return Address of the element in transmit buffer. - */ -static uint32_t MCAN_GetTxBufferElementAddress(CAN_Type *base, uint8_t idx); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of MCAN handle. */ -static mcan_handle_t *s_mcanHandle[FSL_FEATURE_SOC_LPC_CAN_COUNT]; - -/* Array of MCAN peripheral base address. */ -static CAN_Type *const s_mcanBases[] = CAN_BASE_PTRS; - -/* Array of MCAN IRQ number. */ -static const IRQn_Type s_mcanIRQ[][2] = CAN_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of MCAN clock name. */ -static const clock_ip_name_t s_mcanClock[] = MCAN_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/* MCAN ISR for transactional APIs. */ -static mcan_isr_t s_mcanIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ - -uint32_t MCAN_GetInstance(CAN_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_mcanBases); instance++) - { - if (s_mcanBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_mcanBases)); - - return instance; -} - -static void MCAN_Reset(CAN_Type *base) -{ - /* Set INIT bit. */ - base->CCCR |= CAN_CCCR_INIT_MASK; - /* Confirm the value has been accepted. */ - while (!((base->CCCR & CAN_CCCR_INIT_MASK) >> CAN_CCCR_INIT_SHIFT)) - { - } - - /* Set CCE bit to have access to the protected configuration registers, - and clear some status registers. */ - base->CCCR |= CAN_CCCR_CCE_MASK; -} - -static void MCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateA_Bps) -{ - mcan_timing_config_t timingConfigA; - uint32_t preDivA = baudRateA_Bps * MCAN_TIME_QUANTA_NUM; - - if (0 == preDivA) - { - preDivA = 1U; - } - - preDivA = (sourceClock_Hz / preDivA) - 1U; - - /* Desired baud rate is too low. */ - if (preDivA > 0x1FFU) - { - preDivA = 0x1FFU; - } - - /* MCAN timing setting formula: - * MCAN_TIME_QUANTA_NUM = 1 + (xTSEG1 + 1) + (xTSEG2 + 1)); - */ - timingConfigA.preDivider = preDivA; - timingConfigA.seg1 = 0xAU; - timingConfigA.seg2 = 0x3U; - timingConfigA.rJumpwidth = 0x3U; - - /* Update actual timing characteristic. */ - MCAN_SetArbitrationTimingConfig(base, &timingConfigA); -} - -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) -static void MCAN_SetBaudRateFD(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateD_Bps) -{ - mcan_timing_config_t timingConfigD; - uint32_t preDivD = baudRateD_Bps * MCAN_TIME_QUANTA_NUM; - - if (0 == preDivD) - { - preDivD = 1U; - } - - preDivD = (sourceClock_Hz / preDivD) - 1U; - - /* Desired baud rate is too low. */ - if (preDivD > 0x1FU) - { - preDivD = 0x1FU; - } - - /* MCAN timing setting formula: - * MCAN_TIME_QUANTA_NUM = 1 + (xTSEG1 + 1) + (xTSEG2 + 1)); - */ - timingConfigD.preDivider = preDivD; - timingConfigD.seg1 = 0xAU; - timingConfigD.seg2 = 0x3U; - timingConfigD.rJumpwidth = 0x3U; - - /* Update actual timing characteristic. */ - MCAN_SetDataTimingConfig(base, &timingConfigD); -} -#endif - -void MCAN_Init(CAN_Type *base, const mcan_config_t *config, uint32_t sourceClock_Hz) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable MCAN clock. */ - CLOCK_EnableClock(s_mcanClock[MCAN_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - MCAN_Reset(base); - - if (config->enableLoopBackInt) - { - base->CCCR |= CAN_CCCR_TEST_MASK | CAN_CCCR_MON_MASK; - base->TEST |= CAN_TEST_LBCK_MASK; - } - if (config->enableLoopBackExt) - { - base->CCCR |= CAN_CCCR_TEST_MASK; - base->TEST |= CAN_TEST_LBCK_MASK; - } - if (config->enableBusMon) - { - base->CCCR |= CAN_CCCR_MON_MASK; - } -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) - if (config->enableCanfdNormal) - { - base->CCCR |= CAN_CCCR_FDOE_MASK; - } - if (config->enableCanfdSwitch) - { - base->CCCR |= CAN_CCCR_FDOE_MASK | CAN_CCCR_BRSE_MASK; - } -#endif - - /* Set baud rate of arbitration and data phase. */ - MCAN_SetBaudRate(base, sourceClock_Hz, config->baudRateA); -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) - MCAN_SetBaudRateFD(base, sourceClock_Hz, config->baudRateD); -#endif -} - -void MCAN_Deinit(CAN_Type *base) -{ - /* Reset all Register Contents. */ - MCAN_Reset(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable MCAN clock. */ - CLOCK_DisableClock(s_mcanClock[MCAN_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void MCAN_EnterNormalMode(CAN_Type *base) -{ - /* Reset INIT bit to enter normal mode. */ - base->CCCR &= ~CAN_CCCR_INIT_MASK; - while (((base->CCCR & CAN_CCCR_INIT_MASK) >> CAN_CCCR_INIT_SHIFT)) - { - } -} - -void MCAN_GetDefaultConfig(mcan_config_t *config) -{ - /* Assertion. */ - assert(config); - - /* Initialize MCAN Module config struct with default value. */ - config->baudRateA = 500000U; - config->baudRateD = 500000U; - config->enableCanfdNormal = false; - config->enableCanfdSwitch = false; - config->enableLoopBackInt = false; - config->enableLoopBackExt = false; - config->enableBusMon = false; -} - -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) -void MCAN_SetDataTimingConfig(CAN_Type *base, const mcan_timing_config_t *config) -{ - /* Assertion. */ - assert(config); - - /* Cleaning previous Timing Setting. */ - base->DBTP &= ~(CAN_DBTP_DSJW_MASK | CAN_DBTP_DTSEG2_MASK | CAN_DBTP_DTSEG1_MASK | CAN_DBTP_DBRP_MASK); - - /* Updating Timing Setting according to configuration structure. */ - base->DBTP |= (CAN_DBTP_DBRP(config->preDivider) | CAN_DBTP_DSJW(config->rJumpwidth) | - CAN_DBTP_DTSEG1(config->seg1) | CAN_DBTP_DTSEG2(config->seg2)); -} -#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */ - -void MCAN_SetArbitrationTimingConfig(CAN_Type *base, const mcan_timing_config_t *config) -{ - /* Assertion. */ - assert(config); - - /* Cleaning previous Timing Setting. */ - base->NBTP &= ~(CAN_NBTP_NSJW_MASK | CAN_NBTP_NTSEG2_MASK | CAN_NBTP_NTSEG1_MASK | CAN_NBTP_NBRP_MASK); - - /* Updating Timing Setting according to configuration structure. */ - base->NBTP |= (CAN_NBTP_NBRP(config->preDivider) | CAN_NBTP_NSJW(config->rJumpwidth) | - CAN_NBTP_NTSEG1(config->seg1) | CAN_NBTP_NTSEG2(config->seg2)); -} - -void MCAN_SetFilterConfig(CAN_Type *base, const mcan_frame_filter_config_t *config) -{ - /* Set global configuration of remote/nonmasking frames, set filter address and list size. */ - if (config->idFormat == kMCAN_FrameIDStandard) - { - base->GFC |= CAN_GFC_RRFS(config->remFrame) | CAN_GFC_ANFS(config->nmFrame); - base->SIDFC |= CAN_SIDFC_FLSSA(config->address >> CAN_SIDFC_FLSSA_SHIFT) | CAN_SIDFC_LSS(config->listSize); - } - else - { - base->GFC |= CAN_GFC_RRFE(config->remFrame) | CAN_GFC_ANFE(config->nmFrame); - base->XIDFC |= CAN_XIDFC_FLESA(config->address >> CAN_XIDFC_FLESA_SHIFT) | CAN_XIDFC_LSE(config->listSize); - } -} - -void MCAN_SetRxFifo0Config(CAN_Type *base, const mcan_rx_fifo_config_t *config) -{ - /* Set Rx FIFO 0 start address, element size, watermark, operation mode. */ - base->RXF0C |= CAN_RXF0C_F0SA(config->address >> CAN_RXF0C_F0SA_SHIFT) | CAN_RXF0C_F0S(config->elementSize) | - CAN_RXF0C_F0WM(config->watermark) | CAN_RXF0C_F0OM(config->opmode); - /* Set Rx FIFO 0 data field size */ - base->RXESC |= CAN_RXESC_F0DS(config->datafieldSize); -} - -void MCAN_SetRxFifo1Config(CAN_Type *base, const mcan_rx_fifo_config_t *config) -{ - /* Set Rx FIFO 1 start address, element size, watermark, operation mode. */ - base->RXF1C |= CAN_RXF1C_F1SA(config->address >> CAN_RXF1C_F1SA_SHIFT) | CAN_RXF1C_F1S(config->elementSize) | - CAN_RXF1C_F1WM(config->watermark) | CAN_RXF1C_F1OM(config->opmode); - /* Set Rx FIFO 1 data field size */ - base->RXESC |= CAN_RXESC_F1DS(config->datafieldSize); -} - -void MCAN_SetRxBufferConfig(CAN_Type *base, const mcan_rx_buffer_config_t *config) -{ - /* Set Rx Buffer start address. */ - base->RXBC |= CAN_RXBC_RBSA(config->address >> CAN_RXBC_RBSA_SHIFT); - /* Set Rx Buffer data field size */ - base->RXESC |= CAN_RXESC_RBDS(config->datafieldSize); -} - -void MCAN_SetTxEventFifoConfig(CAN_Type *base, const mcan_tx_fifo_config_t *config) -{ - /* Set TX Event FIFO start address, element size, watermark. */ - base->TXEFC |= CAN_TXEFC_EFSA(config->address >> CAN_TXEFC_EFSA_SHIFT) | CAN_TXEFC_EFS(config->elementSize) | - CAN_TXEFC_EFWM(config->watermark); -} - -void MCAN_SetTxBufferConfig(CAN_Type *base, const mcan_tx_buffer_config_t *config) -{ - assert((config->dedicatedSize + config->fqSize) <= 32U); - - /* Set Tx Buffer start address, size, fifo/queue mode. */ - base->TXBC |= CAN_TXBC_TBSA(config->address >> CAN_TXBC_TBSA_SHIFT) | CAN_TXBC_NDTB(config->dedicatedSize) | - CAN_TXBC_TFQS(config->fqSize) | CAN_TXBC_TFQM(config->mode); - /* Set Tx Buffer data field size */ - base->TXESC |= CAN_TXESC_TBDS(config->datafieldSize); -} - -void MCAN_SetSTDFilterElement(CAN_Type *base, - const mcan_frame_filter_config_t *config, - const mcan_std_filter_element_config_t *filter, - uint8_t idx) -{ - uint8_t *elementAddress = 0; - elementAddress = (uint8_t *)(MCAN_GetMsgRAMBase(base) + config->address + idx * 4U); - memcpy(elementAddress, filter, sizeof(*filter)); -} - -void MCAN_SetEXTFilterElement(CAN_Type *base, - const mcan_frame_filter_config_t *config, - const mcan_ext_filter_element_config_t *filter, - uint8_t idx) -{ - uint8_t *elementAddress = 0; - elementAddress = (uint8_t *)(MCAN_GetMsgRAMBase(base) + config->address + idx * 8U); - memcpy(elementAddress, filter, sizeof(*filter)); -} - -static uint32_t MCAN_GetRxFifo0ElementAddress(CAN_Type *base) -{ - uint32_t eSize; - eSize = (base->RXESC & CAN_RXESC_F0DS_MASK) >> CAN_RXESC_F0DS_SHIFT; - if (eSize < 5U) - { - eSize += 4U; - } - else - { - eSize = eSize * 4U - 10U; - } - return (base->RXF0C & CAN_RXF0C_F0SA_MASK) + - ((base->RXF0S & CAN_RXF0S_F0GI_MASK) >> CAN_RXF0S_F0GI_SHIFT) * eSize * 4U; -} - -static uint32_t MCAN_GetRxFifo1ElementAddress(CAN_Type *base) -{ - uint32_t eSize; - eSize = (base->RXESC & CAN_RXESC_F1DS_MASK) >> CAN_RXESC_F1DS_SHIFT; - if (eSize < 5U) - { - eSize += 4U; - } - else - { - eSize = eSize * 4U - 10U; - } - return (base->RXF1C & CAN_RXF1C_F1SA_MASK) + - ((base->RXF1S & CAN_RXF1S_F1GI_MASK) >> CAN_RXF1S_F1GI_SHIFT) * eSize * 4U; -} - -static uint32_t MCAN_GetRxBufferElementAddress(CAN_Type *base, uint8_t idx) -{ - assert(idx <= 63U); - uint32_t eSize; - eSize = (base->RXESC & CAN_RXESC_RBDS_MASK) >> CAN_RXESC_RBDS_SHIFT; - if (eSize < 5U) - { - eSize += 4U; - } - else - { - eSize = eSize * 4U - 10U; - } - return (base->RXBC & CAN_RXBC_RBSA_MASK) + idx * eSize * 4U; -} - -static uint32_t MCAN_GetTxBufferElementAddress(CAN_Type *base, uint8_t idx) -{ - assert(idx <= 31U); - uint32_t eSize; - eSize = (base->TXESC & CAN_TXESC_TBDS_MASK) >> CAN_TXESC_TBDS_SHIFT; - if (eSize < 5U) - { - eSize += 4U; - } - else - { - eSize = eSize * 4U - 10U; - } - return (base->TXBC & CAN_TXBC_TBSA_MASK) + idx * eSize * 4U; -} - -uint32_t MCAN_IsTransmitRequestPending(CAN_Type *base, uint8_t idx) -{ - return (base->TXBRP & (uint32_t)(1U << idx)) >> (uint32_t)idx; -} - -uint32_t MCAN_IsTransmitOccurred(CAN_Type *base, uint8_t idx) -{ - return (base->TXBTO & (uint32_t)(1U << idx)) >> (uint32_t)idx; -} - -status_t MCAN_WriteTxBuffer(CAN_Type *base, uint8_t idx, const mcan_tx_buffer_frame_t *txFrame) -{ - if (!MCAN_IsTransmitRequestPending(base, idx)) - { - uint8_t *elementAddress = 0; - elementAddress = (uint8_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetTxBufferElementAddress(base, idx)); - - /* Write 2 words configuration field. */ - memcpy(elementAddress, (uint8_t *)txFrame, 8U); - /* Write data field. */ - memcpy(elementAddress + 8U, txFrame->data, txFrame->size); - return kStatus_Success; - } - else - { - return kStatus_Fail; - } -} - -status_t MCAN_ReadRxBuffer(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *rxFrame) -{ - mcan_rx_buffer_frame_t *elementAddress = 0; - elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxBufferElementAddress(base, idx)); - memcpy(rxFrame, elementAddress, (rxFrame->size + 8U) * 4U); - return kStatus_Success; -} - -status_t MCAN_ReadRxFifo(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *rxFrame) -{ - assert((fifoBlock == 0) || (fifoBlock == 1U)); - mcan_rx_buffer_frame_t *elementAddress = 0; - if (0 == fifoBlock) - { - elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxFifo0ElementAddress(base)); - } - else - { - elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxFifo1ElementAddress(base)); - } - memcpy(rxFrame, elementAddress, 8U); - rxFrame->data = (uint8_t *)elementAddress + 8U; - /* Acknowledge the read. */ - if (0 == fifoBlock) - { - base->RXF0A = (base->RXF0S & CAN_RXF0S_F0GI_MASK) >> CAN_RXF0S_F0GI_SHIFT; - } - else - { - base->RXF1A = (base->RXF1S & CAN_RXF1S_F1GI_MASK) >> CAN_RXF1S_F1GI_SHIFT; - } - return kStatus_Success; -} - -status_t MCAN_TransferSendBlocking(CAN_Type *base, uint8_t idx, mcan_tx_buffer_frame_t *txFrame) -{ - if (kStatus_Success == MCAN_WriteTxBuffer(base, idx, txFrame)) - { - MCAN_TransmitAddRequest(base, idx); - - /* Wait until message sent out. */ - while (!MCAN_IsTransmitOccurred(base, idx)) - { - } - return kStatus_Success; - } - else - { - return kStatus_Fail; - } -} - -status_t MCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t bufferIdx, mcan_rx_buffer_frame_t *rxFrame) -{ - assert(bufferIdx <= 63U); - - while (!MCAN_GetRxBufferStatusFlag(base, bufferIdx)) - { - } - MCAN_ClearRxBufferStatusFlag(base, bufferIdx); - return MCAN_ReadRxBuffer(base, bufferIdx, rxFrame); -} - -status_t MCAN_TransferReceiveFifoBlocking(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *rxFrame) -{ - assert((fifoBlock == 0) || (fifoBlock == 1U)); - if (0 == fifoBlock) - { - while (!MCAN_GetStatusFlag(base, CAN_IR_RF0N_MASK)) - { - } - MCAN_ClearStatusFlag(base, CAN_IR_RF0N_MASK); - } - else - { - while (!MCAN_GetStatusFlag(base, CAN_IR_RF1N_MASK)) - { - } - MCAN_ClearStatusFlag(base, CAN_IR_RF1N_MASK); - } - return MCAN_ReadRxFifo(base, fifoBlock, rxFrame); -} - -void MCAN_TransferCreateHandle(CAN_Type *base, mcan_handle_t *handle, mcan_transfer_callback_t callback, void *userData) -{ - assert(handle); - - uint8_t instance; - - /* Clean MCAN transfer handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Get instance from peripheral base address. */ - instance = MCAN_GetInstance(base); - - /* Save the context in global variables to support the double weak mechanism. */ - s_mcanHandle[instance] = handle; - - /* Register Callback function. */ - handle->callback = callback; - handle->userData = userData; - - s_mcanIsr = MCAN_TransferHandleIRQ; - - /* We Enable Error & Status interrupt here, because this interrupt just - * report current status of MCAN module through Callback function. - * It is insignificance without a available callback function. - */ - if (handle->callback != NULL) - { - MCAN_EnableInterrupts(base, 0, - kMCAN_BusOffInterruptEnable | kMCAN_ErrorInterruptEnable | kMCAN_WarningInterruptEnable); - } - else - { - MCAN_DisableInterrupts(base, - kMCAN_BusOffInterruptEnable | kMCAN_ErrorInterruptEnable | kMCAN_WarningInterruptEnable); - } - - /* Enable interrupts in NVIC. */ - EnableIRQ((IRQn_Type)(s_mcanIRQ[instance][0])); - EnableIRQ((IRQn_Type)(s_mcanIRQ[instance][1])); -} - -status_t MCAN_TransferSendNonBlocking(CAN_Type *base, mcan_handle_t *handle, mcan_buffer_transfer_t *xfer) -{ - /* Assertion. */ - assert(handle); - assert(xfer); - assert(xfer->bufferIdx <= 63U); - - /* Check if Tx Buffer is idle. */ - if (kMCAN_StateIdle == handle->bufferState[xfer->bufferIdx]) - { - handle->txbufferIdx = xfer->bufferIdx; - /* Distinguish transmit type. */ - if (kMCAN_FrameTypeRemote == xfer->frame->xtd) - { - handle->bufferState[xfer->bufferIdx] = kMCAN_StateTxRemote; - - /* Register user Frame buffer to receive remote Frame. */ - handle->bufferFrameBuf[xfer->bufferIdx] = xfer->frame; - } - else - { - handle->bufferState[xfer->bufferIdx] = kMCAN_StateTxData; - } - - if (kStatus_Success == MCAN_WriteTxBuffer(base, xfer->bufferIdx, xfer->frame)) - { - /* Enable Buffer Interrupt. */ - MCAN_EnableTransmitBufferInterrupts(base, xfer->bufferIdx); - MCAN_EnableInterrupts(base, 0, CAN_IE_TCE_MASK); - - MCAN_TransmitAddRequest(base, xfer->bufferIdx); - - return kStatus_Success; - } - else - { - handle->bufferState[xfer->bufferIdx] = kMCAN_StateIdle; - return kStatus_Fail; - } - } - else - { - return kStatus_MCAN_TxBusy; - } -} - -status_t MCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, - uint8_t fifoBlock, - mcan_handle_t *handle, - mcan_fifo_transfer_t *xfer) -{ - /* Assertion. */ - assert((fifoBlock == 0) || (fifoBlock == 1U)); - assert(handle); - assert(xfer); - - /* Check if Message Buffer is idle. */ - if (kMCAN_StateIdle == handle->rxFifoState) - { - handle->rxFifoState = kMCAN_StateRxFifo; - - /* Register Message Buffer. */ - handle->rxFifoFrameBuf = xfer->frame; - - /* Enable FIFO Interrupt. */ - if (fifoBlock) - { - MCAN_EnableInterrupts(base, 0, CAN_IE_RF1NE_MASK); - } - else - { - MCAN_EnableInterrupts(base, 0, CAN_IE_RF0NE_MASK); - } - return kStatus_Success; - } - else - { - return fifoBlock ? kStatus_MCAN_RxFifo1Busy : kStatus_MCAN_RxFifo0Busy; - } -} - -void MCAN_TransferAbortSend(CAN_Type *base, mcan_handle_t *handle, uint8_t bufferIdx) -{ - /* Assertion. */ - assert(handle); - assert(bufferIdx <= 63U); - - /* Disable Buffer Interrupt. */ - MCAN_DisableTransmitBufferInterrupts(base, bufferIdx); - MCAN_DisableInterrupts(base, CAN_IE_TCE_MASK); - - /* Cancel send request. */ - MCAN_TransmitCancelRequest(base, bufferIdx); - - /* Un-register handle. */ - handle->bufferFrameBuf[bufferIdx] = 0x0; - - handle->bufferState[bufferIdx] = kMCAN_StateIdle; -} - -void MCAN_TransferAbortReceiveFifo(CAN_Type *base, uint8_t fifoBlock, mcan_handle_t *handle) -{ - /* Assertion. */ - assert(handle); - assert((fifoBlock == 0) || (fifoBlock == 1)); - - /* Check if Rx FIFO is enabled. */ - if (fifoBlock) - { - /* Disable Rx Message FIFO Interrupts. */ - MCAN_DisableInterrupts(base, CAN_IE_RF1NE_MASK); - } - else - { - MCAN_DisableInterrupts(base, CAN_IE_RF0NE_MASK); - } - /* Un-register handle. */ - handle->rxFifoFrameBuf = 0x0; - - handle->rxFifoState = kMCAN_StateIdle; -} - -void MCAN_TransferHandleIRQ(CAN_Type *base, mcan_handle_t *handle) -{ - /* Assertion. */ - assert(handle); - - status_t status = kStatus_MCAN_UnHandled; - uint32_t result; - - /* Store Current MCAN Module Error and Status. */ - result = base->IR; - - do - { - /* Solve Rx FIFO, Tx interrupt. */ - if (result & kMCAN_TxTransmitCompleteFlag) - { - status = kStatus_MCAN_TxIdle; - MCAN_TransferAbortSend(base, handle, handle->txbufferIdx); - } - else if (result & kMCAN_RxFifo0NewFlag) - { - MCAN_ReadRxFifo(base, 0, handle->rxFifoFrameBuf); - status = kStatus_MCAN_RxFifo0Idle; - MCAN_TransferAbortReceiveFifo(base, 0, handle); - } - else if (result & kMCAN_RxFifo0LostFlag) - { - status = kStatus_MCAN_RxFifo0Lost; - } - else if (result & kMCAN_RxFifo1NewFlag) - { - MCAN_ReadRxFifo(base, 1, handle->rxFifoFrameBuf); - status = kStatus_MCAN_RxFifo1Idle; - MCAN_TransferAbortReceiveFifo(base, 1, handle); - } - else if (result & kMCAN_RxFifo1LostFlag) - { - status = kStatus_MCAN_RxFifo0Lost; - } - else - { - ; - } - - /* Clear resolved Rx FIFO, Tx Buffer IRQ. */ - MCAN_ClearStatusFlag(base, result); - - /* Calling Callback Function if has one. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, status, result, handle->userData); - } - - /* Reset return status */ - status = kStatus_MCAN_UnHandled; - - /* Store Current MCAN Module Error and Status. */ - result = base->IR; - } while ((0 != MCAN_GetStatusFlag(base, 0xFFFFFFFFU)) || - (0 != (result & (kMCAN_ErrorWarningIntFlag | kMCAN_BusOffIntFlag | kMCAN_ErrorPassiveIntFlag)))); -} - -#if defined(CAN0) -void CAN0_IRQ0_DriverIRQHandler(void) -{ - assert(s_mcanHandle[0]); - - s_mcanIsr(CAN0, s_mcanHandle[0]); -} - -void CAN0_IRQ1_DriverIRQHandler(void) -{ - assert(s_mcanHandle[0]); - - s_mcanIsr(CAN0, s_mcanHandle[0]); -} -#endif - -#if defined(CAN1) -void CAN1_IRQ0_DriverIRQHandler(void) -{ - assert(s_mcanHandle[1]); - - s_mcanIsr(CAN1, s_mcanHandle[1]); -} - -void CAN1_IRQ1_DriverIRQHandler(void) -{ - assert(s_mcanHandle[1]); - - s_mcanIsr(CAN1, s_mcanHandle[1]); -} -#endif diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_mcan.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_mcan.h deleted file mode 100644 index 4a8a4bd7272..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_mcan.h +++ /dev/null @@ -1,966 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_MCAN_H_ -#define _FSL_MCAN_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup mcan - * @{ - */ - -/****************************************************************************** - * Definitions - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief MCAN driver version 2.0.0. */ -#define MCAN_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @brief MCAN transfer status. */ -enum _mcan_status -{ - kStatus_MCAN_TxBusy = MAKE_STATUS(kStatusGroup_MCAN, 0), /*!< Tx Buffer is Busy. */ - kStatus_MCAN_TxIdle = MAKE_STATUS(kStatusGroup_MCAN, 1), /*!< Tx Buffer is Idle. */ - kStatus_MCAN_RxBusy = MAKE_STATUS(kStatusGroup_MCAN, 2), /*!< Rx Buffer is Busy. */ - kStatus_MCAN_RxIdle = MAKE_STATUS(kStatusGroup_MCAN, 3), /*!< Rx Buffer is Idle. */ - kStatus_MCAN_RxFifo0New = MAKE_STATUS(kStatusGroup_MCAN, 4), /*!< New message written to Rx FIFO 0. */ - kStatus_MCAN_RxFifo0Idle = MAKE_STATUS(kStatusGroup_MCAN, 5), /*!< Rx FIFO 0 is Idle. */ - kStatus_MCAN_RxFifo0Watermark = MAKE_STATUS(kStatusGroup_MCAN, 6), /*!< Rx FIFO 0 fill level reached watermark. */ - kStatus_MCAN_RxFifo0Full = MAKE_STATUS(kStatusGroup_MCAN, 7), /*!< Rx FIFO 0 full. */ - kStatus_MCAN_RxFifo0Lost = MAKE_STATUS(kStatusGroup_MCAN, 8), /*!< Rx FIFO 0 message lost. */ - kStatus_MCAN_RxFifo1New = MAKE_STATUS(kStatusGroup_MCAN, 9), /*!< New message written to Rx FIFO 1. */ - kStatus_MCAN_RxFifo1Idle = MAKE_STATUS(kStatusGroup_MCAN, 10), /*!< Rx FIFO 1 is Idle. */ - kStatus_MCAN_RxFifo1Watermark = MAKE_STATUS(kStatusGroup_MCAN, 11), /*!< Rx FIFO 1 fill level reached watermark. */ - kStatus_MCAN_RxFifo1Full = MAKE_STATUS(kStatusGroup_MCAN, 12), /*!< Rx FIFO 1 full. */ - kStatus_MCAN_RxFifo1Lost = MAKE_STATUS(kStatusGroup_MCAN, 13), /*!< Rx FIFO 1 message lost. */ - kStatus_MCAN_RxFifo0Busy = MAKE_STATUS(kStatusGroup_MCAN, 14), /*!< Rx FIFO 0 is busy. */ - kStatus_MCAN_RxFifo1Busy = MAKE_STATUS(kStatusGroup_MCAN, 15), /*!< Rx FIFO 1 is busy. */ - kStatus_MCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_MCAN, 16), /*!< MCAN Module Error and Status. */ - kStatus_MCAN_UnHandled = MAKE_STATUS(kStatusGroup_MCAN, 17), /*!< UnHadled Interrupt asserted. */ -}; - -/*! - * @brief MCAN status flags. - * - * This provides constants for the MCAN status flags for use in the MCAN functions. - * Note: The CPU read action clears MCAN_ErrorFlag, therefore user need to - * read MCAN_ErrorFlag and distinguish which error is occur using - * @ref _mcan_error_flags enumerations. - */ -enum _mcan_flags -{ - kMCAN_AccesstoRsvdFlag = CAN_IR_ARA_MASK, /*!< CAN Synchronization Status. */ - kMCAN_ProtocolErrDIntFlag = CAN_IR_PED_MASK, /*!< Tx Warning Interrupt Flag. */ - kMCAN_ProtocolErrAIntFlag = CAN_IR_PEA_MASK, /*!< Rx Warning Interrupt Flag. */ - kMCAN_BusOffIntFlag = CAN_IR_BO_MASK, /*!< Tx Error Warning Status. */ - kMCAN_ErrorWarningIntFlag = CAN_IR_EW_MASK, /*!< Rx Error Warning Status. */ - kMCAN_ErrorPassiveIntFlag = CAN_IR_EP_MASK, /*!< Rx Error Warning Status. */ -}; - -/*! - * @brief MCAN Rx FIFO status flags. - * - * The MCAN Rx FIFO Status enumerations are used to determine the status of the - * Rx FIFO. - */ -enum _mcan_rx_fifo_flags -{ - kMCAN_RxFifo0NewFlag = CAN_IR_RF0N_MASK, /*!< Rx FIFO 0 new message flag. */ - kMCAN_RxFifo0WatermarkFlag = CAN_IR_RF0W_MASK, /*!< Rx FIFO 0 watermark reached flag. */ - kMCAN_RxFifo0FullFlag = CAN_IR_RF0F_MASK, /*!< Rx FIFO 0 full flag. */ - kMCAN_RxFifo0LostFlag = CAN_IR_RF0L_MASK, /*!< Rx FIFO 0 message lost flag. */ - kMCAN_RxFifo1NewFlag = CAN_IR_RF1N_MASK, /*!< Rx FIFO 0 new message flag. */ - kMCAN_RxFifo1WatermarkFlag = CAN_IR_RF1W_MASK, /*!< Rx FIFO 0 watermark reached flag. */ - kMCAN_RxFifo1FullFlag = CAN_IR_RF1F_MASK, /*!< Rx FIFO 0 full flag. */ - kMCAN_RxFifo1LostFlag = CAN_IR_RF1L_MASK, /*!< Rx FIFO 0 message lost flag. */ -}; - -/*! - * @brief MCAN Tx status flags. - * - * The MCAN Tx Status enumerations are used to determine the status of the - * Tx Buffer/Event FIFO. - */ -enum _mcan_tx_flags -{ - kMCAN_TxTransmitCompleteFlag = CAN_IR_TC_MASK, /*!< Transmission completed flag. */ - kMCAN_TxTransmitCancelFinishFlag = CAN_IR_TCF_MASK, /*!< Transmission cancellation finished flag. */ - kMCAN_TxEventFifoLostFlag = CAN_IR_TEFL_MASK, /*!< Tx Event FIFO element lost. */ - kMCAN_TxEventFifoFullFlag = CAN_IR_TEFF_MASK, /*!< Tx Event FIFO full. */ - kMCAN_TxEventFifoWatermarkFlag = CAN_IR_TEFW_MASK, /*!< Tx Event FIFO fill level reached watermark. */ - kMCAN_TxEventFifoNewFlag = CAN_IR_TEFN_MASK, /*!< Tx Handler wrote Tx Event FIFO element flag. */ - kMCAN_TxEventFifoEmptyFlag = CAN_IR_TFE_MASK, /*!< Tx FIFO empty flag. */ -}; - -/*! - * @brief MCAN interrupt configuration structure, default settings all disabled. - * - * This structure contains the settings for all of the MCAN Module interrupt configurations. - */ -enum _mcan_interrupt_enable -{ - kMCAN_BusOffInterruptEnable = CAN_IE_BOE_MASK, /*!< Bus Off interrupt. */ - kMCAN_ErrorInterruptEnable = CAN_IE_EPE_MASK, /*!< Error interrupt. */ - kMCAN_WarningInterruptEnable = CAN_IE_EWE_MASK, /*!< Rx Warning interrupt. */ -}; - -/*! @brief MCAN frame format. */ -typedef enum _mcan_frame_idformat -{ - kMCAN_FrameIDStandard = 0x0U, /*!< Standard frame format attribute. */ - kMCAN_FrameIDExtend = 0x1U, /*!< Extend frame format attribute. */ -} mcan_frame_idformat_t; - -/*! @brief MCAN frame type. */ -typedef enum _mcan_frame_type -{ - kMCAN_FrameTypeData = 0x0U, /*!< Data frame type attribute. */ - kMCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */ -} mcan_frame_type_t; - -/*! @brief MCAN frame datafield size. */ -typedef enum _mcan_bytes_in_datafield -{ - kMCAN_8ByteDatafield = 0x0U, /*!< 8 byte data field. */ - kMCAN_12ByteDatafield = 0x1U, /*!< 12 byte data field. */ - kMCAN_16ByteDatafield = 0x2U, /*!< 16 byte data field. */ - kMCAN_20ByteDatafield = 0x3U, /*!< 20 byte data field. */ - kMCAN_24ByteDatafield = 0x4U, /*!< 24 byte data field. */ - kMCAN_32ByteDatafield = 0x5U, /*!< 32 byte data field. */ - kMCAN_48ByteDatafield = 0x6U, /*!< 48 byte data field. */ - kMCAN_64ByteDatafield = 0x7U, /*!< 64 byte data field. */ -} mcan_bytes_in_datafield_t; - -#if defined(__CC_ARM) -#pragma anon_unions -#endif -/*! @brief MCAN Tx Buffer structure. */ -typedef struct _mcan_tx_buffer_frame -{ - struct - { - uint32_t id : 29; /*!< CAN Frame Identifier. */ - uint32_t rtr : 1; /*!< CAN Frame Type(DATA or REMOTE). */ - uint32_t xtd : 1; /*!< CAN Frame Type(STD or EXT). */ - uint32_t esi : 1; /*!< CAN Frame Error State Indicator. */ - }; - struct - { - uint32_t : 16; - uint32_t dlc : 4; /*!< Data Length Code. */ - uint32_t brs : 1; /*!< Bit Rate Switch. */ - uint32_t fdf : 1; /*!< CAN FD format. */ - uint32_t : 1; /*!< Reserved. */ - uint32_t efc : 1; /*!< Event FIFO control. */ - uint32_t mm : 8; /*!< Message Marker. */ - }; - uint8_t *data; - uint8_t size; -} mcan_tx_buffer_frame_t; - -/*! @brief MCAN Rx FIFO/Buffer structure. */ -typedef struct _mcan_rx_buffer_frame -{ - struct - { - uint32_t id : 29; /*!< CAN Frame Identifier. */ - uint32_t rtr : 1; /*!< CAN Frame Type(DATA or REMOTE). */ - uint32_t xtd : 1; /*!< CAN Frame Type(STD or EXT). */ - uint32_t esi : 1; /*!< CAN Frame Error State Indicator. */ - }; - struct - { - uint32_t rxts : 16; /*!< Rx Timestamp. */ - uint32_t dlc : 4; /*!< Data Length Code. */ - uint32_t brs : 1; /*!< Bit Rate Switch. */ - uint32_t fdf : 1; /*!< CAN FD format. */ - uint32_t : 2; /*!< Reserved. */ - uint32_t fidx : 7; /*!< Filter Index. */ - uint32_t anmf : 1; /*!< Accepted Non-matching Frame. */ - }; - uint8_t *data; - uint8_t size; -} mcan_rx_buffer_frame_t; - -/*! @brief MCAN Rx FIFO block number. */ -typedef enum _mcan_fifo_type -{ - kMCAN_Fifo0 = 0x0U, /*!< CAN Rx FIFO 0. */ - kMCAN_Fifo1 = 0x1U, /*!< CAN Rx FIFO 1. */ -} mcan_fifo_type_t; - -/*! @brief MCAN FIFO Operation Mode. */ -typedef enum _mcan_fifo_opmode_config -{ - kMCAN_FifoBlocking = 0, /*!< FIFO blocking mode. */ - kMCAN_FifoOverwrite = 1, /*!< FIFO overwrite mode. */ -} mcan_fifo_opmode_config_t; - -/*! @brief MCAN Tx FIFO/Queue Mode. */ -typedef enum _mcan_txmode_config -{ - kMCAN_txFifo = 0, /*!< Tx FIFO operation. */ - kMCAN_txQueue = 1, /*!< Tx Queue operation. */ -} mcan_txmode_config_t; - -/*! @brief MCAN remote frames treatment. */ -typedef enum _mcan_remote_frame_config -{ - kMCAN_filterFrame = 0, /*!< Filter remote frames. */ - kMCAN_rejectFrame = 1, /*!< Reject all remote frames. */ -} mcan_remote_frame_config_t; - -/*! @brief MCAN non-masking frames treatment. */ -typedef enum _mcan_nonmasking_frame_config -{ - kMCAN_acceptinFifo0 = 0, /*!< Accept non-masking frames in Rx FIFO 0. */ - kMCAN_acceptinFifo1 = 1, /*!< Accept non-masking frames in Rx FIFO 1. */ - kMCAN_reject0 = 2, /*!< Reject non-masking frames. */ - kMCAN_reject1 = 3, /*!< Reject non-masking frames. */ -} mcan_nonmasking_frame_config_t; - -/*! @brief MCAN Filter Element Configuration. */ -typedef enum _mcan_fec_config -{ - kMCAN_disable = 0, /*!< Disable filter element. */ - kMCAN_storeinFifo0 = 1, /*!< Store in Rx FIFO 0 if filter matches. */ - kMCAN_storeinFifo1 = 2, /*!< Store in Rx FIFO 1 if filter matches. */ - kMCAN_reject = 3, /*!< Reject ID if filter matches. */ - kMCAN_setprio = 4, /*!< Set priority if filter matches. */ - kMCAN_setpriofifo0 = 5, /*!< Set priority and store in FIFO 0 if filter matches. */ - kMCAN_setpriofifo1 = 6, /*!< Set priority and store in FIFO 1 if filter matches. */ - kMCAN_storeinbuffer = 7, /*!< Store into Rx Buffer or as debug message. */ -} mcan_fec_config_t; - -/*! @brief MCAN Rx FIFO configuration. */ -typedef struct _mcan_rx_fifo_config -{ - uint32_t address; /*!< FIFOn start address. */ - uint32_t elementSize; /*!< FIFOn element number. */ - uint32_t watermark; /*!< FIFOn watermark level. */ - mcan_fifo_opmode_config_t opmode; /*!< FIFOn blocking/overwrite mode. */ - mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */ -} mcan_rx_fifo_config_t; - -/*! @brief MCAN Rx Buffer configuration. */ -typedef struct _mcan_rx_buffer_config -{ - uint32_t address; /*!< Rx Buffer start address. */ - mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */ -} mcan_rx_buffer_config_t; - -/*! @brief MCAN Tx Event FIFO configuration. */ -typedef struct _mcan_tx_fifo_config -{ - uint32_t address; /*!< Event fifo start address. */ - uint32_t elementSize; /*!< FIFOn element number. */ - uint32_t watermark; /*!< FIFOn watermark level. */ -} mcan_tx_fifo_config_t; - -/*! @brief MCAN Tx Buffer configuration. */ -typedef struct _mcan_tx_buffer_config -{ - uint32_t address; /*!< Tx Buffers Start Address. */ - uint32_t dedicatedSize; /*!< Number of Dedicated Transmit Buffers. */ - uint32_t fqSize; /*!< Transmit FIFO/Queue Size. */ - mcan_txmode_config_t mode; /*!< Tx FIFO/Queue Mode.*/ - mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */ -} mcan_tx_buffer_config_t; - -/*! @brief MCAN Filter Type. */ -typedef enum _mcan_std_filter_type -{ - kMCAN_range = 0, /*!< Range filter from SFID1 to SFID2. */ - kMCAN_dual = 1, /*!< Dual ID filter for SFID1 or SFID2. */ - kMCAN_classic = 2, /*!< Classic filter: SFID1 = filter, SFID2 = mask. */ - kMCAN_disableORrange2 = 3, /*!< Filter element disabled for standard filter - or Range filter, XIDAM mask not applied for extended filter. */ -} mcan_filter_type_t; - -/*! @brief MCAN Standard Message ID Filter Element. */ -typedef struct _mcan_std_filter_element_config -{ - uint32_t sfid2 : 11; /*!< Standard Filter ID 2. */ - uint32_t : 5; /*!< Reserved. */ - uint32_t sfid1 : 11; /*!< Standard Filter ID 1. */ - mcan_fec_config_t sfec : 3; /*!< Standard Filter Element Configuration. */ - mcan_filter_type_t sft : 2; /*!< Standard Filter Type/ */ -} mcan_std_filter_element_config_t; - -/*! @brief MCAN Extended Message ID Filter Element. */ -typedef struct _mcan_ext_filter_element_config -{ - uint32_t efid1 : 29; /*!< Extended Filter ID 1. */ - mcan_fec_config_t efec : 3; /*!< Extended Filter Element Configuration. */ - uint32_t efid2 : 29; /*!< Extended Filter ID 2. */ - uint32_t : 1; /*!< Reserved. */ - mcan_filter_type_t eft : 2; /*!< Extended Filter Type. */ -} mcan_ext_filter_element_config_t; - -/*! @brief MCAN Rx filter configuration. */ -typedef struct _mcan_frame_filter_config -{ - uint32_t address; /*!< Filter start address. */ - uint32_t listSize; /*!< Filter list size. */ - mcan_frame_idformat_t idFormat; /*!< Frame format. */ - mcan_remote_frame_config_t remFrame; /*!< Remote frame treatment. */ - mcan_nonmasking_frame_config_t nmFrame; /*!< Non-masking frame treatment. */ -} mcan_frame_filter_config_t; - -/*! @brief MCAN module configuration structure. */ -typedef struct _mcan_config -{ - uint32_t baudRateA; /*!< Baud rate of Arbitration phase in bps. */ - uint32_t baudRateD; /*!< Baud rate of Data phase in bps. */ - bool enableCanfdNormal; /*!< Enable or Disable CANFD normal. */ - bool enableCanfdSwitch; /*!< Enable or Disable CANFD with baudrate switch. */ - bool enableLoopBackInt; /*!< Enable or Disable Internal Back. */ - bool enableLoopBackExt; /*!< Enable or Disable External Loop Back. */ - bool enableBusMon; /*!< Enable or Disable Bus Monitoring Mode. */ -} mcan_config_t; - -/*! @brief MCAN protocol timing characteristic configuration structure. */ -typedef struct _mcan_timing_config -{ - uint16_t preDivider; /*!< Clock Pre-scaler Division Factor. */ - uint8_t rJumpwidth; /*!< Re-sync Jump Width. */ - uint8_t seg1; /*!< Data Time Segment 1. */ - uint8_t seg2; /*!< Data Time Segment 2. */ -} mcan_timing_config_t; - -/*! @brief MCAN Buffer transfer. */ -typedef struct _mcan_buffer_transfer -{ - mcan_tx_buffer_frame_t *frame; /*!< The buffer of CAN Message to be transfer. */ - uint8_t bufferIdx; /*!< The index of Message buffer used to transfer Message. */ -} mcan_buffer_transfer_t; - -/*! @brief MCAN Rx FIFO transfer. */ -typedef struct _mcan_fifo_transfer -{ - mcan_rx_buffer_frame_t *frame; /*!< The buffer of CAN Message to be received from Rx FIFO. */ -} mcan_fifo_transfer_t; - -/*! @brief MCAN handle structure definition. */ -typedef struct _mcan_handle mcan_handle_t; - -/*! @brief MCAN transfer callback function. - * - * The MCAN transfer callback returns a value from the underlying layer. - * If the status equals to kStatus_MCAN_ErrorStatus, the result parameter is the Content of - * MCAN status register which can be used to get the working status(or error status) of MCAN module. - * If the status equals to other MCAN Message Buffer transfer status, the result is the index of - * Message Buffer that generate transfer event. - * If the status equals to other MCAN Message Buffer transfer status, the result is meaningless and should be - * Ignored. - */ -typedef void (*mcan_transfer_callback_t)( - CAN_Type *base, mcan_handle_t *handle, status_t status, uint32_t result, void *userData); - -/*! @brief MCAN handle structure. */ -struct _mcan_handle -{ - mcan_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< MCAN callback function parameter.*/ - mcan_tx_buffer_frame_t *volatile bufferFrameBuf[64]; /*!< The buffer for received data from Buffers. */ - mcan_rx_buffer_frame_t *volatile rxFifoFrameBuf; /*!< The buffer for received data from Rx FIFO. */ - volatile uint8_t txbufferIdx; /*!< Message Buffer transfer state. */ - volatile uint8_t bufferState[64]; /*!< Message Buffer transfer state. */ - volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */ -}; - -/****************************************************************************** - * API - *****************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes an MCAN instance. - * - * This function initializes the MCAN module with user-defined settings. - * This example shows how to set up the mcan_config_t parameters and how - * to call the MCAN_Init function by passing in these parameters. - * @code - * mcan_config_t config; - * config->baudRateA = 500000U; - * config->baudRateD = 500000U; - * config->enableCanfdNormal = false; - * config->enableCanfdSwitch = false; - * config->enableLoopBackInt = false; - * config->enableLoopBackExt = false; - * config->enableBusMon = false; - * MCAN_Init(CANFD0, &config, 8000000UL); - * @endcode - * - * @param base MCAN peripheral base address. - * @param config Pointer to the user-defined configuration structure. - * @param sourceClock_Hz MCAN Protocol Engine clock source frequency in Hz. - */ -void MCAN_Init(CAN_Type *base, const mcan_config_t *config, uint32_t sourceClock_Hz); - -/*! - * @brief Deinitializes an MCAN instance. - * - * This function deinitializes the MCAN module. - * - * @param base MCAN peripheral base address. - */ -void MCAN_Deinit(CAN_Type *base); - -/*! - * @brief Gets the default configuration structure. - * - * This function initializes the MCAN configuration structure to default values. The default - * values are as follows. - * config->baudRateA = 500000U; - * config->baudRateD = 500000U; - * config->enableCanfdNormal = false; - * config->enableCanfdSwitch = false; - * config->enableLoopBackInt = false; - * config->enableLoopBackExt = false; - * config->enableBusMon = false; - * - * @param config Pointer to the MCAN configuration structure. - */ -void MCAN_GetDefaultConfig(mcan_config_t *config); - -/*! - * @brief MCAN enters normal mode. - * - * After initialization, INIT bit in CCCR register must be cleared to enter - * normal mode thus synchronizes to the CAN bus and ready for communication. - * - * @param base MCAN peripheral base address. - */ -void MCAN_EnterNormalMode(CAN_Type *base); - -/*! - * @name Configuration. - * @{ - */ - -/*! - * @brief Sets the MCAN Message RAM base address. - * - * This function sets the Message RAM base address. - * - * @param base MCAN peripheral base address. - * @param value Desired Message RAM base. - */ -static inline void MCAN_SetMsgRAMBase(CAN_Type *base, uint32_t value) -{ - assert((value >= 0x20000000U) && (value <= 0x20027FFFU)); - - base->MRBA = CAN_MRBA_BA(value); -} - -/*! - * @brief Gets the MCAN Message RAM base address. - * - * This function gets the Message RAM base address. - * - * @param base MCAN peripheral base address. - * @return Message RAM base address. - */ -static inline uint32_t MCAN_GetMsgRAMBase(CAN_Type *base) -{ - return base->MRBA; -} - -/*! - * @brief Sets the MCAN protocol arbitration phase timing characteristic. - * - * This function gives user settings to CAN bus timing characteristic. - * The function is for an experienced user. For less experienced users, call - * the MCAN_Init() and fill the baud rate field with a desired value. - * This provides the default arbitration phase timing characteristics. - * - * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate - * set in MCAN_Init(). - * - * @param base MCAN peripheral base address. - * @param config Pointer to the timing configuration structure. - */ -void MCAN_SetArbitrationTimingConfig(CAN_Type *base, const mcan_timing_config_t *config); - -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) -/*! - * @brief Sets the MCAN protocol data phase timing characteristic. - * - * This function gives user settings to CAN bus timing characteristic. - * The function is for an experienced user. For less experienced users, call - * the MCAN_Init() and fill the baud rate field with a desired value. - * This provides the default data phase timing characteristics. - * - * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate - * set in MCAN_Init(). - * - * @param base MCAN peripheral base address. - * @param config Pointer to the timing configuration structure. - */ -void MCAN_SetDataTimingConfig(CAN_Type *base, const mcan_timing_config_t *config); -#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */ - -/*! - * @brief Configures an MCAN receive fifo 0 buffer. - * - * This function sets start address, element size, watermark, operation mode - * and datafield size of the recieve fifo 0. - * - * @param base MCAN peripheral base address. - * @param config The receive fifo 0 configuration structure. - */ -void MCAN_SetRxFifo0Config(CAN_Type *base, const mcan_rx_fifo_config_t *config); - -/*! - * @brief Configures an MCAN receive fifo 1 buffer. - * - * This function sets start address, element size, watermark, operation mode - * and datafield size of the recieve fifo 1. - * - * @param base MCAN peripheral base address. - * @param config The receive fifo 1 configuration structure. - */ -void MCAN_SetRxFifo1Config(CAN_Type *base, const mcan_rx_fifo_config_t *config); - -/*! - * @brief Configures an MCAN receive buffer. - * - * This function sets start address and datafield size of the recieve buffer. - * - * @param base MCAN peripheral base address. - * @param config The receive buffer configuration structure. - */ -void MCAN_SetRxBufferConfig(CAN_Type *base, const mcan_rx_buffer_config_t *config); - -/*! - * @brief Configures an MCAN transmit event fifo. - * - * This function sets start address, element size, watermark of the transmit event fifo. - * - * @param base MCAN peripheral base address. - * @param config The transmit event fifo configuration structure. - */ -void MCAN_SetTxEventfifoConfig(CAN_Type *base, const mcan_tx_fifo_config_t *config); - -/*! - * @brief Configures an MCAN transmit buffer. - * - * This function sets start address, element size, fifo/queue mode and datafield - * size of the transmit buffer. - * - * @param base MCAN peripheral base address. - * @param config The transmit buffer configuration structure. - */ -void MCAN_SetTxBufferConfig(CAN_Type *base, const mcan_tx_buffer_config_t *config); - -/*! - * @brief Set filter configuration. - * - * This function sets remote and non masking frames in global filter configuration, - * also the start address, list size in standard/extended ID filter configuration. - * - * @param base MCAN peripheral base address. - * @param config The MCAN filter configuration. - */ -void MCAN_SetFilterConfig(CAN_Type *base, const mcan_frame_filter_config_t *config); - -/*! - * @brief Set filter configuration. - * - * This function sets remote and non masking frames in global filter configuration, - * also the start address, list size in standard/extended ID filter configuration. - * - * @param base MCAN peripheral base address. - * @param config The MCAN filter configuration. - */ -void MCAN_SetSTDFilterElement(CAN_Type *base, - const mcan_frame_filter_config_t *config, - const mcan_std_filter_element_config_t *filter, - uint8_t idx); - -/*! - * @brief Set filter configuration. - * - * This function sets remote and non masking frames in global filter configuration, - * also the start address, list size in standard/extended ID filter configuration. - * - * @param base MCAN peripheral base address. - * @param config The MCAN filter configuration. - */ -void MCAN_SetEXTFilterElement(CAN_Type *base, - const mcan_frame_filter_config_t *config, - const mcan_ext_filter_element_config_t *filter, - uint8_t idx); - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the MCAN module interrupt flags. - * - * This function gets all MCAN interrupt status flags. - * - * @param base MCAN peripheral base address. - * @param mask The ORed MCAN interrupt mask. - * @return MCAN status flags which are ORed. - */ -static inline uint32_t MCAN_GetStatusFlag(CAN_Type *base, uint32_t mask) -{ - return (bool)(base->IR & mask); -} - -/*! - * @brief Clears the MCAN module interrupt flags. - * - * This function clears MCAN interrupt status flags. - * - * @param base MCAN peripheral base address. - * @param mask The ORed MCAN interrupt mask. - */ -static inline void MCAN_ClearStatusFlag(CAN_Type *base, uint32_t mask) -{ - /* Write 1 to clear status flag. */ - base->IR |= mask; -} - -/*! - * @brief Gets the new data flag of specific Rx Buffer. - * - * This function gets new data flag of specific Rx Buffer. - * - * @param base MCAN peripheral base address. - * @param idx Rx Buffer index. - * @return Rx Buffer new data status flag. - */ -static inline bool MCAN_GetRxBufferStatusFlag(CAN_Type *base, uint8_t idx) -{ - assert(idx <= 63U); - - if (idx <= 31U) - { - return (bool)(base->NDAT1 & (1U << idx)); - } - else - { - return (bool)(base->NDAT2 & (1U << (idx - 31U))); - } -} - -/*! - * @brief Clears the new data flag of specific Rx Buffer. - * - * This function clears new data flag of specific Rx Buffer. - * - * @param base MCAN peripheral base address. - * @param idx Rx Buffer index. - */ -static inline void MCAN_ClearRxBufferStatusFlag(CAN_Type *base, uint8_t idx) -{ - assert(idx <= 63U); - - if (idx <= 31U) - { - base->NDAT1 &= ~(1U << idx); - } - else - { - base->NDAT2 &= ~(1U << (idx - 31U)); - } -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables MCAN interrupts according to the provided interrupt line and mask. - * - * This function enables the MCAN interrupts according to the provided interrupt line and mask. - * The mask is a logical OR of enumeration members. - * - * @param base MCAN peripheral base address. - * @param line Interrupt line number, 0 or 1. - * @param mask The interrupts to enable. - */ -static inline void MCAN_EnableInterrupts(CAN_Type *base, uint32_t line, uint32_t mask) -{ - base->ILE |= (1U << line); - if (0 == line) - { - base->ILS &= ~mask; - } - else - { - base->ILS |= mask; - } - base->IE |= mask; -} - -/*! - * @brief Enables MCAN Tx Buffer interrupts according to the provided index. - * - * This function enables the MCAN Tx Buffer interrupts. - * - * @param base MCAN peripheral base address. - * @param idx Tx Buffer index. - */ -static inline void MCAN_EnableTransmitBufferInterrupts(CAN_Type *base, uint8_t idx) -{ - base->TXBTIE |= (uint32_t)(1U << idx); -} - -/*! - * @brief Disables MCAN Tx Buffer interrupts according to the provided index. - * - * This function disables the MCAN Tx Buffer interrupts. - * - * @param base MCAN peripheral base address. - * @param idx Tx Buffer index. - */ -static inline void MCAN_DisableTransmitBufferInterrupts(CAN_Type *base, uint8_t idx) -{ - base->TXBTIE &= (uint32_t)(~(1U << idx)); -} - -/*! - * @brief Disables MCAN interrupts according to the provided mask. - * - * This function disables the MCAN interrupts according to the provided mask. - * The mask is a logical OR of enumeration members. - * - * @param base MCAN peripheral base address. - * @param mask The interrupts to disable. - */ -static inline void MCAN_DisableInterrupts(CAN_Type *base, uint32_t mask) -{ - base->IE &= ~mask; -} - -/* @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Writes an MCAN Message to the Transmit Buffer. - * - * This function writes a CAN Message to the specified Transmit Message Buffer - * and changes the Message Buffer state to start CAN Message transmit. After - * that the function returns immediately. - * - * @param base MCAN peripheral base address. - * @param idx The MCAN Tx Buffer index. - * @param txFrame Pointer to CAN message frame to be sent. - */ -status_t MCAN_WriteTxBuffer(CAN_Type *base, uint8_t idx, const mcan_tx_buffer_frame_t *txFrame); - -/*! - * @brief Reads an MCAN Message from Rx FIFO. - * - * This function reads a CAN message from the Rx FIFO in the Message RAM. - * - * @param base MCAN peripheral base address. - * @param fifoBlock Rx FIFO block 0 or 1. - * @param rxFrame Pointer to CAN message frame structure for reception. - * @retval kStatus_Success - Read Message from Rx FIFO successfully. - */ -status_t MCAN_ReadRxFifo(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *rxFrame); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Tx Buffer add request to send message out. - * - * This function add sending request to corresponding Tx Buffer. - * - * @param base MCAN peripheral base address. - * @param idx Tx Buffer index. - */ -static inline void MCAN_TransmitAddRequest(CAN_Type *base, uint8_t idx) -{ - base->TXBAR |= (uint32_t)(1U << idx); -} - -/*! - * @brief Tx Buffer cancel sending request. - * - * This function clears Tx buffer request pending bit. - * - * @param base MCAN peripheral base address. - * @param idx Tx Buffer index. - */ -static inline void MCAN_TransmitCancelRequest(CAN_Type *base, uint8_t idx) -{ - base->TXBCR |= (uint32_t)(1U << idx); -} - -/*! - * @brief Performs a polling send transaction on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * @param base MCAN peripheral base pointer. - * @param idx The MCAN buffer index. - * @param txFrame Pointer to CAN message frame to be sent. - * @retval kStatus_Success - Write Tx Message Buffer Successfully. - * @retval kStatus_Fail - Tx Message Buffer is currently in use. - */ -status_t MCAN_TransferSendBlocking(CAN_Type *base, uint8_t idx, mcan_tx_buffer_frame_t *txFrame); - -/*! - * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * @param base MCAN peripheral base pointer. - * @param fifoBlock Rx FIFO block, 0 or 1. - * @param rxFrame Pointer to CAN message frame structure for reception. - * @retval kStatus_Success - Read Message from Rx FIFO successfully. - * @retval kStatus_Fail - No new message in Rx FIFO. - */ -status_t MCAN_TransferReceiveFifoBlocking(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *rxFrame); - -/*! - * @brief Initializes the MCAN handle. - * - * This function initializes the MCAN handle, which can be used for other MCAN - * transactional APIs. Usually, for a specified MCAN instance, - * call this API once to get the initialized handle. - * - * @param base MCAN peripheral base address. - * @param handle MCAN handle pointer. - * @param callback The callback function. - * @param userData The parameter of the callback function. - */ -void MCAN_TransferCreateHandle(CAN_Type *base, - mcan_handle_t *handle, - mcan_transfer_callback_t callback, - void *userData); - -/*! - * @brief Sends a message using IRQ. - * - * This function sends a message using IRQ. This is a non-blocking function, which returns - * right away. When messages have been sent out, the send callback function is called. - * - * @param base MCAN peripheral base address. - * @param handle MCAN handle pointer. - * @param xfer MCAN Buffer transfer structure. See the #mcan_buffer_transfer_t. - * @retval kStatus_Success Start Tx Buffer sending process successfully. - * @retval kStatus_Fail Write Tx Buffer failed. - * @retval kStatus_MCAN_TxBusy Tx Buffer is in use. - */ -status_t MCAN_TransferSendNonBlocking(CAN_Type *base, mcan_handle_t *handle, mcan_buffer_transfer_t *xfer); - -/*! - * @brief Receives a message from Rx FIFO using IRQ. - * - * This function receives a message using IRQ. This is a non-blocking function, which returns - * right away. When all messages have been received, the receive callback function is called. - * - * @param base MCAN peripheral base address. - * @param handle MCAN handle pointer. - * @param fifoBlock Rx FIFO block, 0 or 1. - * @param xfer MCAN Rx FIFO transfer structure. See the @ref mcan_fifo_transfer_t. - * @retval kStatus_Success - Start Rx FIFO receiving process successfully. - * @retval kStatus_MCAN_RxFifo0Busy - Rx FIFO 0 is currently in use. - * @retval kStatus_MCAN_RxFifo1Busy - Rx FIFO 1 is currently in use. - */ -status_t MCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, - uint8_t fifoBlock, - mcan_handle_t *handle, - mcan_fifo_transfer_t *xfer); - -/*! - * @brief Aborts the interrupt driven message send process. - * - * This function aborts the interrupt driven message send process. - * - * @param base MCAN peripheral base address. - * @param handle MCAN handle pointer. - * @param bufferIdx The MCAN Buffer index. - */ -void MCAN_TransferAbortSend(CAN_Type *base, mcan_handle_t *handle, uint8_t bufferIdx); - -/*! - * @brief Aborts the interrupt driven message receive from Rx FIFO process. - * - * This function aborts the interrupt driven message receive from Rx FIFO process. - * - * @param base MCAN peripheral base address. - * @param fifoBlock MCAN Fifo block, 0 or 1. - * @param handle MCAN handle pointer. - */ -void MCAN_TransferAbortReceiveFifo(CAN_Type *base, uint8_t fifoBlock, mcan_handle_t *handle); - -/*! - * @brief MCAN IRQ handle function. - * - * This function handles the MCAN Error, the Buffer, and the Rx FIFO IRQ request. - * - * @param base MCAN peripheral base address. - * @param handle MCAN handle pointer. - */ -void MCAN_TransferHandleIRQ(CAN_Type *base, mcan_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_MCAN_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_mrt.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_mrt.c deleted file mode 100644 index cd36ab2b4ac..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_mrt.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_mrt.h" - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base Multi-Rate timer peripheral base address - * - * @return The MRT instance - */ -static uint32_t MRT_GetInstance(MRT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to MRT bases for each instance. */ -static MRT_Type *const s_mrtBases[] = MRT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to MRT clocks for each instance. */ -static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Pointers to MRT resets for each instance. */ -static const reset_ip_name_t s_mrtResets[] = MRT_RSTS; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t MRT_GetInstance(MRT_Type *base) -{ - uint32_t instance; - uint32_t mrtArrayCount = (sizeof(s_mrtBases) / sizeof(s_mrtBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < mrtArrayCount; instance++) - { - if (s_mrtBases[instance] == base) - { - break; - } - } - - assert(instance < mrtArrayCount); - - return instance; -} - -void MRT_Init(MRT_Type *base, const mrt_config_t *config) -{ - assert(config); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate the MRT clock */ - CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the module */ - RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]); - - /* Set timer operating mode */ - base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask); -} - -void MRT_Deinit(MRT_Type *base) -{ - /* Stop all the timers */ - MRT_StopTimer(base, kMRT_Channel_0); - MRT_StopTimer(base, kMRT_Channel_1); - MRT_StopTimer(base, kMRT_Channel_2); - MRT_StopTimer(base, kMRT_Channel_3); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the MRT clock*/ - CLOCK_DisableClock(s_mrtClocks[MRT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad) -{ - uint32_t newValue = count; - if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == kMRT_OneShotMode) || (immediateLoad)) - { - /* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */ - newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK; - } - - /* Update the timer interval value */ - base->CHANNEL[channel].INTVAL = newValue; -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_mrt.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_mrt.h deleted file mode 100644 index 5638bf16755..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_mrt.h +++ /dev/null @@ -1,371 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_MRT_H_ -#define _FSL_MRT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup mrt - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! @brief List of MRT channels */ -typedef enum _mrt_chnl -{ - kMRT_Channel_0 = 0U, /*!< MRT channel number 0*/ - kMRT_Channel_1, /*!< MRT channel number 1 */ - kMRT_Channel_2, /*!< MRT channel number 2 */ - kMRT_Channel_3 /*!< MRT channel number 3 */ -} mrt_chnl_t; - -/*! @brief List of MRT timer modes */ -typedef enum _mrt_timer_mode -{ - kMRT_RepeatMode = (0 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< Repeat Interrupt mode */ - kMRT_OneShotMode = (1 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< One-shot Interrupt mode */ - kMRT_OneShotStallMode = (2 << MRT_CHANNEL_CTRL_MODE_SHIFT) /*!< One-shot stall mode */ -} mrt_timer_mode_t; - -/*! @brief List of MRT interrupts */ -typedef enum _mrt_interrupt_enable -{ - kMRT_TimerInterruptEnable = MRT_CHANNEL_CTRL_INTEN_MASK /*!< Timer interrupt enable*/ -} mrt_interrupt_enable_t; - -/*! @brief List of MRT status flags */ -typedef enum _mrt_status_flags -{ - kMRT_TimerInterruptFlag = MRT_CHANNEL_STAT_INTFLAG_MASK, /*!< Timer interrupt flag */ - kMRT_TimerRunFlag = MRT_CHANNEL_STAT_RUN_MASK, /*!< Indicates state of the timer */ -} mrt_status_flags_t; - -/*! - * @brief MRT configuration structure - * - * This structure holds the configuration settings for the MRT peripheral. To initialize this - * structure to reasonable defaults, call the MRT_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _mrt_config -{ - bool enableMultiTask; /*!< true: Timers run in multi-task mode; false: Timers run in hardware status mode */ -} mrt_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the MRT clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the MRT driver. - * - * @param base Multi-Rate timer peripheral base address - * @param config Pointer to user's MRT config structure - */ -void MRT_Init(MRT_Type *base, const mrt_config_t *config); - -/*! - * @brief Gate the MRT clock - * - * @param base Multi-Rate timer peripheral base address - */ -void MRT_Deinit(MRT_Type *base); - -/*! - * @brief Fill in the MRT config struct with the default settings - * - * The default values are: - * @code - * config->enableMultiTask = false; - * @endcode - * @param config Pointer to user's MRT config structure. - */ -static inline void MRT_GetDefaultConfig(mrt_config_t *config) -{ - assert(config); - - /* Use hardware status operating mode */ - config->enableMultiTask = false; -} - -/*! - * @brief Sets up an MRT channel mode. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Channel that is being configured. - * @param mode Timer mode to use for the channel. - */ -static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode) -{ - uint32_t reg = base->CHANNEL[channel].CTRL; - - /* Clear old value */ - reg &= ~MRT_CHANNEL_CTRL_MODE_MASK; - /* Add the new mode */ - reg |= mode; - - base->CHANNEL[channel].CTRL = reg; -} - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the MRT interrupt. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - base->CHANNEL[channel].CTRL |= mask; -} - -/*! - * @brief Disables the selected MRT interrupt. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to disable. This is a logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - base->CHANNEL[channel].CTRL &= ~mask; -} - -/*! - * @brief Gets the enabled MRT interrupts. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel) -{ - return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the MRT status flags - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::mrt_status_flags_t - */ -static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel) -{ - return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK)); -} - -/*! - * @brief Clears the MRT status flags. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::mrt_status_flags_t - */ -static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK); -} - -/*! @}*/ - -/*! - * @name Read and Write the timer period - * @{ - */ - -/*! - * @brief Used to update the timer period in units of count. - * - * The new value will be immediately loaded or will be loaded at the end of the current time - * interval. For one-shot interrupt mode the new value will be immediately loaded. - * - * @note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param count Timer period in units of ticks - * @param immediateLoad true: Load the new value immediately into the TIMER register; - * false: Load the new value at the end of current timer interval - */ -void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad); - -/*! - * @brief Reads the current timer counting value. - * - * This function returns the real-time timer counting value, in a range from 0 to a - * timer period. - * - * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return Current timer counting value in ticks - */ -static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel) -{ - return base->CHANNEL[channel].TIMER; -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the timer counting. - * - * After calling this function, timers load period value, counts down to 0 and - * depending on the timer mode it will either load the respective start value again or stop. - * - * @note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - * @param count Timer period in units of ticks - */ -static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count) -{ - /* Write the timer interval value */ - base->CHANNEL[channel].INTVAL = count; -} - -/*! - * @brief Stops the timer counting. - * - * This function stops the timer from counting. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - */ -static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel) -{ - /* Stop the timer immediately */ - base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK; -} - -/*! @}*/ - -/*! - * @name Get & release channel - * @{ - */ - -/*! - * @brief Find the available channel. - * - * This function returns the lowest available channel number. - * - * @param base Multi-Rate timer peripheral base address - */ -static inline uint32_t MRT_GetIdleChannel(MRT_Type *base) -{ - return base->IDLE_CH; -} - -/*! - * @brief Release the channel when the timer is using the multi-task mode. - * - * In multi-task mode, the INUSE flags allow more control over when MRT channels are released for - * further use. The user can hold on to a channel acquired by calling MRT_GetIdleChannel() for as - * long as it is needed and release it by calling this function. This removes the need to ask for - * an available channel for every use. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - */ -static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel) -{ - uint32_t reg = base->CHANNEL[channel].STAT; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg = ~MRT_CHANNEL_STAT_INTFLAG_MASK; - reg |= MRT_CHANNEL_STAT_INUSE_MASK; - - base->CHANNEL[channel].STAT = reg; -} - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_MRT_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_otp.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_otp.h deleted file mode 100644 index 45242b16329..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_otp.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_OTP_H_ -#define _FSL_OTP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup otp - * @{ - */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief OTP driver version 2.0.0. - * - * Current version: 2.0.0 - * - * Change log: - * - Version 2.0.0 - * - Initial version. - */ -#define FSL_OTP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @brief Bank bit flags. */ -typedef enum _otp_bank -{ - kOTP_Bank0 = 0x1U, /*!< Bank 0. */ - kOTP_Bank1 = 0x2U, /*!< Bank 1. */ - kOTP_Bank2 = 0x4U, /*!< Bank 2. */ - kOTP_Bank3 = 0x8U /*!< Bank 3. */ -} otp_bank_t; - -/*! @brief Bank word bit flags. */ -typedef enum _otp_word -{ - kOTP_Word0 = 0x1U, /*!< Word 0. */ - kOTP_Word1 = 0x2U, /*!< Word 1. */ - kOTP_Word2 = 0x4U, /*!< Word 2. */ - kOTP_Word3 = 0x8U /*!< Word 3. */ -} otp_word_t; - -/*! @brief Lock modifications of a read or write access to a bank register. */ -typedef enum _otp_lock -{ - kOTP_LockDontLock = 0U, /*!< Do not lock. */ - kOTP_LockLock = 1U /*!< Lock till reset. */ -} otp_lock_t; - -/*! @brief OTP error codes. */ -enum _otp_status -{ - kStatus_OTP_WrEnableInvalid = MAKE_STATUS(kStatusGroup_OTP, 0x1U), /*!< Write enable invalid. */ - kStatus_OTP_SomeBitsAlreadyProgrammed = MAKE_STATUS(kStatusGroup_OTP, 0x2U), /*!< Some bits already programmed. */ - kStatus_OTP_AllDataOrMaskZero = MAKE_STATUS(kStatusGroup_OTP, 0x3U), /*!< All data or mask zero. */ - kStatus_OTP_WriteAccessLocked = MAKE_STATUS(kStatusGroup_OTP, 0x4U), /*!< Write access locked. */ - kStatus_OTP_ReadDataMismatch = MAKE_STATUS(kStatusGroup_OTP, 0x5U), /*!< Read data mismatch. */ - kStatus_OTP_UsbIdEnabled = MAKE_STATUS(kStatusGroup_OTP, 0x6U), /*!< USB ID enabled. */ - kStatus_OTP_EthMacEnabled = MAKE_STATUS(kStatusGroup_OTP, 0x7U), /*!< Ethernet MAC enabled. */ - kStatus_OTP_AesKeysEnabled = MAKE_STATUS(kStatusGroup_OTP, 0x8U), /*!< AES keys enabled. */ - kStatus_OTP_IllegalBank = MAKE_STATUS(kStatusGroup_OTP, 0x9U), /*!< Illegal bank. */ - kStatus_OTP_ShufflerConfigNotValid = MAKE_STATUS(kStatusGroup_OTP, 0xAU), /*!< Shuffler config not valid. */ - kStatus_OTP_ShufflerNotEnabled = MAKE_STATUS(kStatusGroup_OTP, 0xBU), /*!< Shuffler not enabled. */ - kStatus_OTP_ShufflerCanOnlyProgSingleKey = - MAKE_STATUS(kStatusGroup_OTP, 0xBU), /*!< Shuffler can only program single key. */ - kStatus_OTP_IllegalProgramData = MAKE_STATUS(kStatusGroup_OTP, 0xCU), /*!< Illegal program data. */ - kStatus_OTP_ReadAccessLocked = MAKE_STATUS(kStatusGroup_OTP, 0xDU), /*!< Read access locked. */ -}; - -#define _OTP_ERR_BASE (0x70000U) -#define _OTP_MAKE_STATUS(errorCode) \ - ((errorCode == 0U) ? kStatus_Success : MAKE_STATUS(kStatusGroup_OTP, ((errorCode)-_OTP_ERR_BASE))) - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initializes OTP controller. - * - * @return kStatus_Success upon successful execution, error status otherwise. - */ -static inline status_t OTP_Init(void) -{ - uint32_t status = OTP_API->otpInit(); - return _OTP_MAKE_STATUS(status); -} - -/*! - * @brief Unlock one or more OTP banks for write access. - * - * @param bankMask bit flag that specifies which banks to unlock. - * - * @return kStatus_Success upon successful execution, error status otherwise. - */ -static inline status_t OTP_EnableBankWriteMask(otp_bank_t bankMask) -{ - uint32_t status = OTP_API->otpEnableBankWriteMask(bankMask); - return _OTP_MAKE_STATUS(status); -} - -/*! - * @brief Lock one or more OTP banks for write access. - * - * @param bankMask bit flag that specifies which banks to lock. - * - * @return kStatus_Success upon successful execution, error status otherwise. - */ -static inline status_t OTP_DisableBankWriteMask(otp_bank_t bankMask) -{ - uint32_t status = OTP_API->otpDisableBankWriteMask(bankMask); - return _OTP_MAKE_STATUS(status); -} - -/*! - * @brief Locks or unlocks write access to a register of an OTP bank and possibly lock un/locking of it. - * - * @param bankIndex OTP bank index, 0 = bank 0, 1 = bank 1 etc. - * @param regEnableMask bit flag that specifies for which words to enable writing. - * @param regDisableMask bit flag that specifies for which words to disable writing. - * @param lockWrite specifies if access set can be modified or is locked till reset. - * - * @return kStatus_Success upon successful execution, error status otherwise. - */ -static inline status_t OTP_EnableBankWriteLock(uint32_t bankIndex, - otp_word_t regEnableMask, - otp_word_t regDisableMask, - otp_lock_t lockWrite) -{ - uint32_t status = OTP_API->otpEnableBankWriteLock(bankIndex, regEnableMask, regDisableMask, lockWrite); - return _OTP_MAKE_STATUS(status); -} - -/*! - * @brief Locks or unlocks read access to a register of an OTP bank and possibly lock un/locking of it. - * - * @param bankIndex OTP bank index, 0 = bank 0, 1 = bank 1 etc. - * @param regEnableMask bit flag that specifies for which words to enable reading. - * @param regDisableMask bit flag that specifies for which words to disable reading. - * @param lockWrite specifies if access set can be modified or is locked till reset. - * - * @return kStatus_Success upon successful execution, error status otherwise. - */ -static inline status_t OTP_EnableBankReadLock(uint32_t bankIndex, - otp_word_t regEnableMask, - otp_word_t regDisableMask, - otp_lock_t lockWrite) -{ - uint32_t status = OTP_API->otpEnableBankReadLock(bankIndex, regEnableMask, regDisableMask, lockWrite); - return _OTP_MAKE_STATUS(status); -} - -/*! - * @brief Program a single register in an OTP bank. - * - * @param bankIndex OTP bank index, 0 = bank 0, 1 = bank 1 etc. - * @param regIndex OTP register index. - * @param value value to write. - * - * @return kStatus_Success upon successful execution, error status otherwise. - */ -static inline status_t OTP_ProgramRegister(uint32_t bankIndex, uint32_t regIndex, uint32_t value) -{ - uint32_t status = OTP_API->otpProgramReg(bankIndex, regIndex, value); - return _OTP_MAKE_STATUS(status); -} - -/*! - * @brief Returns the version of the OTP driver in ROM. - * - * @return version. - */ -static inline uint32_t OTP_GetDriverVersion(void) -{ - return OTP_API->otpGetDriverVersion(); -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_OTP_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_pint.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_pint.c deleted file mode 100644 index c707a251392..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_pint.c +++ /dev/null @@ -1,427 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_pint.h" - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Irq number array */ -static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; - -/*! @brief Callback function array for PINT(s). */ -static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -void PINT_Init(PINT_Type *base) -{ - uint32_t i; - uint32_t pmcfg; - - assert(base); - - pmcfg = 0; - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_pintCallback[i] = NULL; - } - - /* Disable all bit slices */ - for (i = 0; i < PINT_PIN_INT_COUNT; i++) - { - pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U))); - } - - /* Enable the peripheral clock */ - CLOCK_EnableClock(kCLOCK_Pint); - - /* Reset the peripheral */ - RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); - - /* Disable all pattern match bit slices */ - base->PMCFG = pmcfg; -} - -void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback) -{ - assert(base); - - /* Clear Rise and Fall flags first */ - PINT_PinInterruptClrRiseFlag(base, intr); - PINT_PinInterruptClrFallFlag(base, intr); - - /* select level or edge sensitive */ - base->ISEL = (base->ISEL & ~(1U << intr)) | ((enable & PINT_PIN_INT_LEVEL) ? (1U << intr) : 0U); - - /* enable rising or level interrupt */ - if (enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE)) - { - base->SIENR = 1U << intr; - } - else - { - base->CIENR = 1U << intr; - } - - /* Enable falling or select high level */ - if (enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL) - { - base->SIENF = 1U << intr; - } - else - { - base->CIENF = 1U << intr; - } - - s_pintCallback[intr] = callback; -} - -void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback) -{ - uint32_t mask; - bool level; - - assert(base); - - *enable = kPINT_PinIntEnableNone; - level = false; - - mask = 1U << pintr; - if (base->ISEL & mask) - { - /* Pin interrupt is level sensitive */ - level = true; - } - - if (base->IENR & mask) - { - if (level) - { - /* Level interrupt is enabled */ - *enable = kPINT_PinIntEnableLowLevel; - } - else - { - /* Rising edge interrupt */ - *enable = kPINT_PinIntEnableRiseEdge; - } - } - - if (base->IENF & mask) - { - if (level) - { - /* Level interrupt is active high */ - *enable = kPINT_PinIntEnableHighLevel; - } - else - { - /* Either falling or both edge */ - if (*enable == kPINT_PinIntEnableRiseEdge) - { - /* Rising and faling edge */ - *enable = kPINT_PinIntEnableBothEdges; - } - else - { - /* Falling edge */ - *enable = kPINT_PinIntEnableFallEdge; - } - } - } - - *callback = s_pintCallback[pintr]; -} - -void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) -{ - uint32_t src_shift; - uint32_t cfg_shift; - uint32_t pmcfg; - - assert(base); - - src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U); - cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U); - - /* Input source selection for selected bit slice */ - base->PMSRC = (base->PMSRC & ~(PININT_BITSLICE_SRC_MASK << src_shift)) | (cfg->bs_src << src_shift); - - /* Bit slice configuration */ - pmcfg = base->PMCFG; - pmcfg = (pmcfg & ~(PININT_BITSLICE_CFG_MASK << cfg_shift)) | (cfg->bs_cfg << cfg_shift); - - /* If end point is true, enable the bits */ - if (bslice != 7U) - { - if (cfg->end_point) - { - pmcfg |= (0x1U << bslice); - } - else - { - pmcfg &= ~(0x1U << bslice); - } - } - - base->PMCFG = pmcfg; - - /* Save callback pointer */ - s_pintCallback[bslice] = cfg->callback; -} - -void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) -{ - uint32_t src_shift; - uint32_t cfg_shift; - - assert(base); - - src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U); - cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U); - - cfg->bs_src = (pint_pmatch_input_src_t)((base->PMSRC & (PININT_BITSLICE_SRC_MASK << src_shift)) >> src_shift); - cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)((base->PMCFG & (PININT_BITSLICE_CFG_MASK << cfg_shift)) >> cfg_shift); - - if (bslice == 7U) - { - cfg->end_point = true; - } - else - { - cfg->end_point = (base->PMCFG & (0x1U << bslice)) >> bslice; - } - cfg->callback = s_pintCallback[bslice]; -} - -uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base) -{ - uint32_t pmctrl; - uint32_t pmstatus; - uint32_t pmsrc; - - pmctrl = PINT->PMCTRL; - pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT; - if (pmstatus) - { - /* Reset Pattern match engine detection logic */ - pmsrc = base->PMSRC; - base->PMSRC = pmsrc; - } - return (pmstatus); -} - -void PINT_EnableCallback(PINT_Type *base) -{ - uint32_t i; - - assert(base); - - PINT_PinInterruptClrStatusAll(base); - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - NVIC_ClearPendingIRQ(s_pintIRQ[i]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - EnableIRQ(s_pintIRQ[i]); - } -} - -void PINT_DisableCallback(PINT_Type *base) -{ - uint32_t i; - - assert(base); - - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - DisableIRQ(s_pintIRQ[i]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i]); - } -} - -void PINT_Deinit(PINT_Type *base) -{ - uint32_t i; - - assert(base); - - /* Cleanup */ - PINT_DisableCallback(base); - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_pintCallback[i] = NULL; - } - - /* Reset the peripheral */ - RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); - - /* Disable the peripheral clock */ - CLOCK_DisableClock(kCLOCK_Pint); -} - -/* IRQ handler functions overloading weak symbols in the startup */ -void PIN_INT0_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Clear Pin interrupt before callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt0] != NULL) - { - s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus); - } -} - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) -void PIN_INT1_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Clear Pin interrupt before callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt1] != NULL) - { - s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus); - } -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) -void PIN_INT2_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Clear Pin interrupt before callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt2] != NULL) - { - s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus); - } -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) -void PIN_INT3_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Clear Pin interrupt before callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt3] != NULL) - { - s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus); - } -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) -void PIN_INT4_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Clear Pin interrupt before callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt4] != NULL) - { - s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus); - } -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) -void PIN_INT5_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Clear Pin interrupt before callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt5] != NULL) - { - s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus); - } -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) -void PIN_INT6_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Clear Pin interrupt before callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt6] != NULL) - { - s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus); - } -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) -void PIN_INT7_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Clear Pin interrupt before callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt7] != NULL) - { - s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus); - } -} -#endif diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_pint.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_pint.h deleted file mode 100644 index ae3ce30428c..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_pint.h +++ /dev/null @@ -1,568 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_PINT_H_ -#define _FSL_PINT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup pint_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/* Number of interrupt line supported by PINT */ -#define PINT_PIN_INT_COUNT 8U - -/* Number of input sources supported by PINT */ -#define PINT_INPUT_COUNT 8U - -/* PININT Bit slice source register bits */ -#define PININT_BITSLICE_SRC_START 8U -#define PININT_BITSLICE_SRC_MASK 7U - -/* PININT Bit slice configuration register bits */ -#define PININT_BITSLICE_CFG_START 8U -#define PININT_BITSLICE_CFG_MASK 7U -#define PININT_BITSLICE_ENDP_MASK 7U - -#define PINT_PIN_INT_LEVEL 0x10U -#define PINT_PIN_INT_EDGE 0x00U -#define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U -#define PINT_PIN_INT_RISE 0x01U -#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE) -#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) -#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) -#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL) -#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) - -/*! @brief PINT Pin Interrupt enable type */ -typedef enum _pint_pin_enable -{ - kPINT_PinIntEnableNone = 0U, /*!< Do not generate Pin Interrupt */ - kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE, /*!< Generate Pin Interrupt on rising edge */ - kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE, /*!< Generate Pin Interrupt on falling edge */ - kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */ - kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL, /*!< Generate Pin Interrupt on low level */ - kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */ -} pint_pin_enable_t; - -/*! @brief PINT Pin Interrupt type */ -typedef enum _pint_int -{ - kPINT_PinInt0 = 0U, /*!< Pin Interrupt 0 */ -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_PinInt1 = 1U, /*!< Pin Interrupt 1 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) - kPINT_PinInt2 = 2U, /*!< Pin Interrupt 2 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) - kPINT_PinInt3 = 3U, /*!< Pin Interrupt 3 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) - kPINT_PinInt4 = 4U, /*!< Pin Interrupt 4 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) - kPINT_PinInt5 = 5U, /*!< Pin Interrupt 5 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) - kPINT_PinInt6 = 6U, /*!< Pin Interrupt 6 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) - kPINT_PinInt7 = 7U, /*!< Pin Interrupt 7 */ -#endif -} pint_pin_int_t; - -/*! @brief PINT Pattern Match bit slice input source type */ -typedef enum _pint_pmatch_input_src -{ - kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */ - kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */ - kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */ - kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */ - kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */ - kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */ - kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */ - kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */ -} pint_pmatch_input_src_t; - -/*! @brief PINT Pattern Match bit slice type */ -typedef enum _pint_pmatch_bslice -{ - kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) - kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) - kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) - kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) - kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) - kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) - kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */ -#endif -} pint_pmatch_bslice_t; - -/*! @brief PINT Pattern Match configuration type */ -typedef enum _pint_pmatch_bslice_cfg -{ - kPINT_PatternMatchAlways = 0U, /*!< Always Contributes to product term match */ - kPINT_PatternMatchStickyRise = 1U, /*!< Sticky Rising edge */ - kPINT_PatternMatchStickyFall = 2U, /*!< Sticky Falling edge */ - kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */ - kPINT_PatternMatchHigh = 4U, /*!< High level */ - kPINT_PatternMatchLow = 5U, /*!< Low level */ - kPINT_PatternMatchNever = 6U, /*!< Never contributes to product term match */ - kPINT_PatternMatchBothEdges = 7U, /*!< Either rising or falling edge */ -} pint_pmatch_bslice_cfg_t; - -/*! @brief PINT Callback function. */ -typedef void (*pint_cb_t)(pint_pin_int_t pintr, uint32_t pmatch_status); - -typedef struct _pint_pmatch_cfg -{ - pint_pmatch_input_src_t bs_src; - pint_pmatch_bslice_cfg_t bs_cfg; - bool end_point; - pint_cb_t callback; -} pint_pmatch_cfg_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize PINT peripheral. - - * This function initializes the PINT peripheral and enables the clock. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_Init(PINT_Type *base); - -/*! - * @brief Configure PINT peripheral pin interrupt. - - * This function configures a given pin interrupt. - * - * @param base Base address of the PINT peripheral. - * @param intr Pin interrupt. - * @param enable Selects detection logic. - * @param callback Callback. - * - * @retval None. - */ -void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback); - -/*! - * @brief Get PINT peripheral pin interrupt configuration. - - * This function returns the configuration of a given pin interrupt. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * @param enable Pointer to store the detection logic. - * @param callback Callback. - * - * @retval None. - */ -void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback); - -/*! - * @brief Clear Selected pin interrupt status. - - * This function clears the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr) -{ - base->IST = (1U << pintr); -} - -/*! - * @brief Get Selected pin interrupt status. - - * This function returns the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval status = 0 No pin interrupt request. = 1 Selected Pin interrupt request active. - */ -static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->IST & (1U << pintr)) ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupts status. - - * This function clears the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrStatusAll(PINT_Type *base) -{ - base->IST = PINT_IST_PSTAT_MASK; -} - -/*! - * @brief Get all pin interrupts status. - - * This function returns the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval status Each bit position indicates the status of corresponding pin interrupt. - * = 0 No pin interrupt request. = 1 Pin interrupt request active. - */ -static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base) -{ - return (base->IST); -} - -/*! - * @brief Clear Selected pin interrupt fall flag. - - * This function clears the selected pin interrupt fall flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - base->FALL = (1U << pintr); -} - -/*! - * @brief Get selected pin interrupt fall flag. - - * This function returns the selected pin interrupt fall flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval flag = 0 Falling edge has not been detected. = 1 Falling edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->FALL & (1U << pintr)) ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupt fall flags. - - * This function clears the fall flag for all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base) -{ - base->FALL = PINT_FALL_FDET_MASK; -} - -/*! - * @brief Get all pin interrupt fall flags. - - * This function returns the fall flag of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval flags Each bit position indicates the falling edge detection of the corresponding pin interrupt. - * 0 Falling edge has not been detected. = 1 Falling edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base) -{ - return (base->FALL); -} - -/*! - * @brief Clear Selected pin interrupt rise flag. - - * This function clears the selected pin interrupt rise flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - base->RISE = (1U << pintr); -} - -/*! - * @brief Get selected pin interrupt rise flag. - - * This function returns the selected pin interrupt rise flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval flag = 0 Rising edge has not been detected. = 1 Rising edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->RISE & (1U << pintr)) ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupt rise flags. - - * This function clears the rise flag for all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base) -{ - base->RISE = PINT_RISE_RDET_MASK; -} - -/*! - * @brief Get all pin interrupt rise flags. - - * This function returns the rise flag of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval flags Each bit position indicates the rising edge detection of the corresponding pin interrupt. - * 0 Rising edge has not been detected. = 1 Rising edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base) -{ - return (base->RISE); -} - -/*! - * @brief Configure PINT pattern match. - - * This function configures a given pattern match bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * @param cfg Pointer to bit slice configuration. - * - * @retval None. - */ -void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); - -/*! - * @brief Get PINT pattern match configuration. - - * This function returns the configuration of a given pattern match bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * @param cfg Pointer to bit slice configuration. - * - * @retval None. - */ -void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); - -/*! - * @brief Get pattern match bit slice status. - - * This function returns the status of selected bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * - * @retval status = 0 Match has not been detected. = 1 Match has been detected. - */ -static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_bslice_t bslice) -{ - return ((base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT) & (0x1U << bslice)) >> bslice; -} - -/*! - * @brief Get status of all pattern match bit slices. - - * This function returns the status of all bit slices. - * - * @param base Base address of the PINT peripheral. - * - * @retval status Each bit position indicates the match status of corresponding bit slice. - * = 0 Match has not been detected. = 1 Match has been detected. - */ -static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base) -{ - return base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT; -} - -/*! - * @brief Reset pattern match detection logic. - - * This function resets the pattern match detection logic if any of the product term is matching. - * - * @param base Base address of the PINT peripheral. - * - * @retval pmstatus Each bit position indicates the match status of corresponding bit slice. - * = 0 Match was detected. = 1 Match was not detected. - */ -uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base); - -/*! - * @brief Enable pattern match function. - - * This function enables the pattern match function. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchEnable(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) | PINT_PMCTRL_SEL_PMATCH_MASK; -} - -/*! - * @brief Disable pattern match function. - - * This function disables the pattern match function. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchDisable(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) & ~PINT_PMCTRL_SEL_PMATCH_MASK; -} - -/*! - * @brief Enable RXEV output. - - * This function enables the pattern match RXEV output. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) | PINT_PMCTRL_ENA_RXEV_MASK; -} - -/*! - * @brief Disable RXEV output. - - * This function disables the pattern match RXEV output. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) & ~PINT_PMCTRL_ENA_RXEV_MASK; -} - -/*! - * @brief Enable callback. - - * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_EnableCallback(PINT_Type *base); - -/*! - * @brief Disable callback. - - * This function disables the interrupt for the selected PINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * @param base Base address of the peripheral. - * - * @retval None. - */ -void PINT_DisableCallback(PINT_Type *base); - -/*! - * @brief Deinitialize PINT peripheral. - - * This function disables the PINT clock. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_Deinit(PINT_Type *base); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_PINT_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_power.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_power.c deleted file mode 100644 index 69b53d1f604..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_power.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016, NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_common.h" -#include "fsl_power.h" - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Empty file since implementation is in header file and power library */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_power.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_power.h deleted file mode 100644 index ef1a5434bd2..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_power.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016, NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_POWER_H_ -#define _FSL_POWER_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define MAKE_PD_BITS(reg, slot) ((reg << 8) | slot) -#define PDRCFG0 0x0U -#define PDRCFG1 0x1U - -typedef enum pd_bits -{ - kPDRUNCFG_LP_REG = MAKE_PD_BITS(PDRCFG0, 2U), - kPDRUNCFG_PD_FRO_EN = MAKE_PD_BITS(PDRCFG0, 4U), - kPDRUNCFG_PD_TS = MAKE_PD_BITS(PDRCFG0, 6U), - kPDRUNCFG_PD_BOD_RESET = MAKE_PD_BITS(PDRCFG0, 7U), - kPDRUNCFG_PD_BOD_INTR = MAKE_PD_BITS(PDRCFG0, 8U), - kPDRUNCFG_PD_VD2_ANA = MAKE_PD_BITS(PDRCFG0, 9U), - kPDRUNCFG_PD_ADC0 = MAKE_PD_BITS(PDRCFG0, 10U), - kPDRUNCFG_PD_RAM0 = MAKE_PD_BITS(PDRCFG0, 13U), - kPDRUNCFG_PD_RAM1 = MAKE_PD_BITS(PDRCFG0, 14U), - kPDRUNCFG_PD_RAM2 = MAKE_PD_BITS(PDRCFG0, 15U), - kPDRUNCFG_PD_RAM3 = MAKE_PD_BITS(PDRCFG0, 16U), - kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG0, 17U), - kPDRUNCFG_PD_VDDA = MAKE_PD_BITS(PDRCFG0, 19U), - kPDRUNCFG_PD_WDT_OSC = MAKE_PD_BITS(PDRCFG0, 20U), - kPDRUNCFG_PD_USB0_PHY = MAKE_PD_BITS(PDRCFG0, 21U), - kPDRUNCFG_PD_SYS_PLL0 = MAKE_PD_BITS(PDRCFG0, 22U), - kPDRUNCFG_PD_VREFP = MAKE_PD_BITS(PDRCFG0, 23U), - kPDRUNCFG_PD_FLASH_BG = MAKE_PD_BITS(PDRCFG0, 25U), - kPDRUNCFG_PD_VD3 = MAKE_PD_BITS(PDRCFG0, 26U), - kPDRUNCFG_PD_VD4 = MAKE_PD_BITS(PDRCFG0, 27U), - kPDRUNCFG_PD_VD5 = MAKE_PD_BITS(PDRCFG0, 28U), - kPDRUNCFG_PD_VD6 = MAKE_PD_BITS(PDRCFG0, 29U), - kPDRUNCFG_REQ_DELAY = MAKE_PD_BITS(PDRCFG0, 30U), - kPDRUNCFG_FORCE_RBB = MAKE_PD_BITS(PDRCFG0, 31U), - - kPDRUNCFG_PD_USB1_PHY = MAKE_PD_BITS(PDRCFG1, 0U), - kPDRUNCFG_PD_USB_PLL = MAKE_PD_BITS(PDRCFG1, 1U), - kPDRUNCFG_PD_AUDIO_PLL = MAKE_PD_BITS(PDRCFG1, 2U), - kPDRUNCFG_PD_SYS_OSC = MAKE_PD_BITS(PDRCFG1, 3U), - kPDRUNCFG_PD_EEPROM = MAKE_PD_BITS(PDRCFG1, 5U), - kPDRUNCFG_PD_rng = MAKE_PD_BITS(PDRCFG1, 6U), - - kPDRUNCFG_ForceUnsigned = 0x80000000U, -} pd_bit_t; - -/* Power mode configuration API parameter */ -typedef enum _power_mode_config -{ - kPmu_Sleep = 0U, - kPmu_Deep_Sleep = 1U, - kPmu_Deep_PowerDown = 2U, -} power_mode_cfg_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! -* @name Power Configuration -* @{ -*/ - -/*! - * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral - * - * @param en peripheral for which to enable the PDRUNCFG bit - * @return none - */ -static inline void POWER_EnablePD(pd_bit_t en) -{ - /* PDRUNCFGSET */ - SYSCON->PDRUNCFGSET[(en >> 8UL)] = (1UL << (en & 0xffU)); -} - -/*! - * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral - * - * @param en peripheral for which to disable the PDRUNCFG bit - * @return none - */ -static inline void POWER_DisablePD(pd_bit_t en) -{ - /* PDRUNCFGCLR */ - SYSCON->PDRUNCFGCLR[(en >> 8UL)] = (1UL << (en & 0xffU)); -} - -/*! - * @brief API to enable deep sleep bit in the ARM Core. - * - * @param none - * @return none - */ -static inline void POWER_EnableDeepSleep(void) -{ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; -} - -/*! - * @brief API to disable deep sleep bit in the ARM Core. - * - * @param none - * @return none - */ -static inline void POWER_DisableDeepSleep(void) -{ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; -} - -/*! - * @brief API to power down flash controller. - * - * @param none - * @return none - */ -static inline void POWER_PowerDownFlash(void) -{ - /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */ - CLOCK_DisableClock(kCLOCK_Flash); - - /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */ - CLOCK_DisableClock(kCLOCK_Fmc); -} - -/*! - * @brief API to power up flash controller. - * - * @param none - * @return none - */ -static inline void POWER_PowerUpFlash(void) -{ - /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */ - CLOCK_EnableClock(kCLOCK_Fmc); -} - -/*! - * @brief Power Library API to power the PLLs. - * - * @param none - * @return none - */ -void POWER_SetPLL(void); - -/*! - * @brief Power Library API to power the USB PHY. - * - * @param none - * @return none - */ -void POWER_SetUsbPhy(void); - -/*! - * @brief Power Library API to enter different power mode. - * - * @param exclude_from_pd Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on during power mode selected. - * @return none - */ -void POWER_EnterPowerMode(power_mode_cfg_t mode, uint64_t exclude_from_pd); - -/*! - * @brief Power Library API to enter sleep mode. - * - * @return none - */ -void POWER_EnterSleep(void); - -/*! - * @brief Power Library API to enter deep sleep mode. - * - * @param exclude_from_pd Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) bits that needs to be powered on during deep sleep - * @return none - */ -void POWER_EnterDeepSleep(uint64_t exclude_from_pd); - -/*! - * @brief Power Library API to enter deep power down mode. - * - * @param exclude_from_pd Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on during deep power - * down mode, but this is has no effect as the voltages are cut off. - - * @return none - */ -void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd); - -/*! - * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency. - * - * @param freq - The desired frequency at which the part would like to operate, - * note that the voltage and flash wait states should be set before changing frequency - * @return none - */ -void POWER_SetVoltageForFreq(uint32_t freq); - -/*! - * @brief Power Library API to return the library version. - * - * @param none - * @return version number of the power library - */ -uint32_t POWER_GetLibVersion(void); - -#ifdef __cplusplus -} -#endif - -#endif /* _FSL_POWER_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_reset.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_reset.c deleted file mode 100644 index 07a9ed9e2fc..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_reset.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016, NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_common.h" -#include "fsl_reset.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) - -void RESET_SetPeripheralReset(reset_ip_name_t peripheral) -{ - const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; - const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); - const uint32_t bitMask = 1u << bitPos; - - assert(bitPos < 32u); - - /* ASYNC_SYSCON registers have offset 1024 */ - if (regIndex >= SYSCON_PRESETCTRL_COUNT) - { - /* reset register is in ASYNC_SYSCON */ - - /* set bit */ - ASYNC_SYSCON->ASYNCPRESETCTRLSET = bitMask; - /* wait until it reads 0b1 */ - while (0u == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask)) - { - } - } - else - { - /* reset register is in SYSCON */ - - /* set bit */ - SYSCON->PRESETCTRLSET[regIndex] = bitMask; - /* wait until it reads 0b1 */ - while (0u == (SYSCON->PRESETCTRL[regIndex] & bitMask)) - { - } - } -} - -void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) -{ - const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; - const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); - const uint32_t bitMask = 1u << bitPos; - - assert(bitPos < 32u); - - /* ASYNC_SYSCON registers have offset 1024 */ - if (regIndex >= SYSCON_PRESETCTRL_COUNT) - { - /* reset register is in ASYNC_SYSCON */ - - /* clear bit */ - ASYNC_SYSCON->ASYNCPRESETCTRLCLR = bitMask; - /* wait until it reads 0b0 */ - while (bitMask == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask)) - { - } - } - else - { - /* reset register is in SYSCON */ - - /* clear bit */ - SYSCON->PRESETCTRLCLR[regIndex] = bitMask; - /* wait until it reads 0b0 */ - while (bitMask == (SYSCON->PRESETCTRL[regIndex] & bitMask)) - { - } - } -} - -void RESET_PeripheralReset(reset_ip_name_t peripheral) -{ - RESET_SetPeripheralReset(peripheral); - RESET_ClearPeripheralReset(peripheral); -} - -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_reset.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_reset.h deleted file mode 100644 index 95dea0a97dc..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_reset.h +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016, NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_RESET_H_ -#define _FSL_RESET_H_ - -#include -#include -#include -#include -#include "fsl_device_registers.h" - -/*! - * @addtogroup ksdk_common - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief Enumeration for peripheral reset control bits - * - * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers - */ -typedef enum _SYSCON_RSTn -{ - kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ - kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ - kEEPROM_RST_SHIFT_RSTn = 0 | 9U, /**< EEPROM reset control */ - kSPIFI_RST_SHIFT_RSTn = 0 | 10U, /**< SPIFI reset control */ - kMUX_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux reset control */ - kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ - kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ - kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ - kGPIO2_RST_SHIFT_RSTn = 0 | 16U, /**< GPIO2 reset control */ - kGPIO3_RST_SHIFT_RSTn = 0 | 17U, /**< GPIO3 reset control */ - kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ - kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ - kDMA_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ - kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ - kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ - kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ - - kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ - kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ - kMCAN0_RST_SHIFT_RSTn = 65536 | 7U, /**< MCAN0 reset control */ - kMCAN1_RST_SHIFT_RSTn = 65536 | 8U, /**< MCAN1 reset control */ - kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ - kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ - kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ - kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ - kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ - kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ - kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ - kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ - kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ - kDMIC_RST_SHIFT_RSTn = 65536 | 19U, /**< Digital microphone interface reset control */ - kCT32B2_RST_SHIFT_RSTn = 65536 | 22U, /**< CT32B2 reset control */ - kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0D reset control */ - kCT32B0_RST_SHIFT_RSTn = 65536 | 26U, /**< CT32B0 reset control */ - kCT32B1_RST_SHIFT_RSTn = 65536 | 27U, /**< CT32B1 reset control */ - - kLCD_RST_SHIFT_RSTn = 131072 | 2U, /**< LCD reset control */ - kSDIO_RST_SHIFT_RSTn = 131072 | 3U, /**< SDIO reset control */ - kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USB1H reset control */ - kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USB1D reset control */ - kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB1RAM reset control */ - kEMC_RST_SHIFT_RSTn = 131072 | 7U, /**< EMC reset control */ - kETH_RST_SHIFT_RSTn = 131072 | 8U, /**< ETH reset control */ - kGPIO4_RST_SHIFT_RSTn = 131072 | 9U, /**< GPIO4 reset control */ - kGPIO5_RST_SHIFT_RSTn = 131072 | 10U, /**< GPIO5 reset control */ - kAES_RST_SHIFT_RSTn = 131072 | 11U, /**< AES reset control */ - kOTP_RST_SHIFT_RSTn = 131072 | 12U, /**< OTP reset control */ - kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */ - kFC8_RST_SHIFT_RSTn = 131072 | 14U, /**< Flexcomm Interface 8 reset control */ - kFC9_RST_SHIFT_RSTn = 131072 | 15U, /**< Flexcomm Interface 9 reset control */ - kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */ - kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */ - kSHA_RST_SHIFT_RSTn = 131072 | 18U, /**< SHA reset control */ - kSC0_RST_SHIFT_RSTn = 131072 | 19U, /**< SC0 reset control */ - kSC1_RST_SHIFT_RSTn = 131072 | 20U, /**< SC1 reset control */ - - kCT32B3_RST_SHIFT_RSTn = 67108864 | 13U, /**< CT32B3 reset control */ - kCT32B4_RST_SHIFT_RSTn = 67108864 | 14U, /**< CT32B4 reset control */ -} SYSCON_RSTn_t; - -/** Array initializers with peripheral reset bits **/ -#define ADC_RSTS \ - { \ - kADC0_RST_SHIFT_RSTn \ - } /* Reset bits for ADC peripheral */ -#define AES_RSTS \ - { \ - kAES_RST_SHIFT_RSTn \ - } /* Reset bits for AES peripheral */ -#define CRC_RSTS \ - { \ - kCRC_RST_SHIFT_RSTn \ - } /* Reset bits for CRC peripheral */ -#define CTIMER_RSTS \ - { \ - kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \ - kCT32B4_RST_SHIFT_RSTn \ - } /* Reset bits for CTIMER peripheral */ -#define DMA_RSTS \ - { \ - kDMA_RST_SHIFT_RSTn \ - } /* Reset bits for DMA peripheral */ -#define DMIC_RSTS \ - { \ - kDMIC_RST_SHIFT_RSTn \ - } /* Reset bits for DMIC peripheral */ -#define EMC_RSTS \ - { \ - kEMC_RST_SHIFT_RSTn \ - } /* Reset bits for EMC peripheral */ -#define ETH_RST \ - { \ - kETH_RST_SHIFT_RSTn \ - } /* Reset bits for EMC peripheral */ -#define FLEXCOMM_RSTS \ - { \ - kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ - kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kFC8_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn \ - } /* Reset bits for FLEXCOMM peripheral */ -#define GINT_RSTS \ - { \ - kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ - } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ -#define GPIO_RSTS \ - { \ - kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \ - kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn \ - } /* Reset bits for GPIO peripheral */ -#define INPUTMUX_RSTS \ - { \ - kMUX_RST_SHIFT_RSTn \ - } /* Reset bits for INPUTMUX peripheral */ -#define IOCON_RSTS \ - { \ - kIOCON_RST_SHIFT_RSTn \ - } /* Reset bits for IOCON peripheral */ -#define FLASH_RSTS \ - { \ - kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ - } /* Reset bits for Flash peripheral */ -#define LCD_RSTS \ - { \ - kLCD_RST_SHIFT_RSTn \ - } /* Reset bits for LCD peripheral */ -#define MRT_RSTS \ - { \ - kMRT_RST_SHIFT_RSTn \ - } /* Reset bits for MRT peripheral */ -#define MCAN_RSTS \ - { \ - kMCAN0_RST_SHIFT_RSTn,kMCAN1_RST_SHIFT_RSTn \ - } /* Reset bits for MCAN0&MACN1 peripheral */ -#define OTP_RSTS \ - { \ - kOTP_RST_SHIFT_RSTn \ - } /* Reset bits for OTP peripheral */ -#define PINT_RSTS \ - { \ - kPINT_RST_SHIFT_RSTn \ - } /* Reset bits for PINT peripheral */ -#define RNG_RSTS \ - { \ - kRNG_RST_SHIFT_RSTn \ - } /* Reset bits for RNG peripheral */ -#define SDIO_RST \ - { \ - kSDIO_RST_SHIFT_RSTn \ - } /* Reset bits for SDIO peripheral */ -#define SCT_RSTS \ - { \ - kSCT0_RST_SHIFT_RSTn \ - } /* Reset bits for SCT peripheral */ -#define SHA_RST \ - { \ - kSHA_RST_SHIFT_RSTn \ - } /* Reset bits for SHA peripheral */ -#define USB0D_RST \ - { \ - kUSB0D_RST_SHIFT_RSTn \ - } /* Reset bits for USB0D peripheral */ -#define USB0HMR_RST \ - { \ - kUSB0HMR_RST_SHIFT_RSTn \ - } /* Reset bits for USB0HMR peripheral */ -#define USB0HSL_RST \ - { \ - kUSB0HSL_RST_SHIFT_RSTn \ - } /* Reset bits for USB0HSL peripheral */ -#define USB1H_RST \ - { \ - kUSB1H_RST_SHIFT_RSTn \ - } /* Reset bits for USB1H peripheral */ -#define USB1D_RST \ - { \ - kUSB1D_RST_SHIFT_RSTn \ - } /* Reset bits for USB1D peripheral */ -#define USB1RAM_RST \ - { \ - kUSB1RAM_RST_SHIFT_RSTn \ - } /* Reset bits for USB1RAM peripheral */ -#define UTICK_RSTS \ - { \ - kUTICK_RST_SHIFT_RSTn \ - } /* Reset bits for UTICK peripheral */ -#define WWDT_RSTS \ - { \ - kWWDT_RST_SHIFT_RSTn \ - } /* Reset bits for WWDT peripheral */ - -typedef SYSCON_RSTn_t reset_ip_name_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Assert reset to peripheral. - * - * Asserts reset signal to specified peripheral module. - * - * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_SetPeripheralReset(reset_ip_name_t peripheral); - -/*! - * @brief Clear reset to peripheral. - * - * Clears reset signal to specified peripheral module, allows it to operate. - * - * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); - -/*! - * @brief Reset peripheral module. - * - * Reset peripheral module. - * - * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_PeripheralReset(reset_ip_name_t peripheral); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_RESET_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_rit.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_rit.c deleted file mode 100644 index 23c9c9257c2..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_rit.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_rit.h" - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address to be used to gate or ungate the module clock - * - * @param base RIT peripheral base address - * - * @return The RIT instance - */ -static uint32_t RIT_GetInstance(RIT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to RIT bases for each instance. */ -static RIT_Type *const s_ritBases[] = RIT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to PIT clocks for each instance. */ -static const clock_ip_name_t s_ritClocks[] = RIT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t RIT_GetInstance(RIT_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_ritBases); instance++) - { - if (s_ritBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_ritBases)); - - return instance; -} - -void RIT_GetDefaultConfig(rit_config_t *config) -{ - assert(config); - /* Timer operation are no effect in Debug mode */ - config->enableRunInDebug = false; -} - -void RIT_Init(RIT_Type *base, const rit_config_t *config) -{ - assert(config); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate the RIT clock*/ - CLOCK_EnableClock(s_ritClocks[RIT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Enable RIT timers */ - base->CTRL &= ~RIT_CTRL_RITEN_MASK; - - /* Config timer operation is no effect in debug mode */ - if (!config->enableRunInDebug) - { - base->CTRL &= ~RIT_CTRL_RITENBR_MASK; - } - else - { - base->CTRL |= RIT_CTRL_RITENBR_MASK; - } -} - -void RIT_Deinit(RIT_Type *base) -{ - /* Disable RIT timers */ - base->CTRL |= ~RIT_CTRL_RITEN_MASK; -#ifdef FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL - /* Gate the RIT clock*/ - CLOCK_DisableClock(s_ritClocks[RIT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void RIT_SetTimerCompare(RIT_Type *base, uint64_t count) -{ - /* Disable RIT timers */ - base->CTRL &= ~RIT_CTRL_RITEN_MASK; - base->COMPVAL = (uint32_t)count; - base->COMPVAL_H = (uint16_t)(count >> 32U); -} - -void RIT_SetMaskBit(RIT_Type *base, uint64_t count) -{ - base->MASK = (uint32_t)count; - base->MASK_H = (uint16_t)(count >> 32U); -} - -uint64_t RIT_GetCompareTimerCount(RIT_Type *base) -{ - uint16_t valueH = 0U; - uint32_t valueL = 0U; - - /* COMPVAL_H should be read before COMPVAL */ - valueH = base->COMPVAL_H; - valueL = base->COMPVAL; - - return (((uint64_t)valueH << 32U) + (uint64_t)(valueL)); -} - -uint64_t RIT_GetCounterTimerCount(RIT_Type *base) -{ - uint16_t valueH = 0U; - uint32_t valueL = 0U; - - /* COUNTER_H should be read before COUNTER */ - valueH = base->COUNTER_H; - valueL = base->COUNTER; - - return (((uint64_t)valueH << 32U) + (uint64_t)(valueL)); -} - -uint64_t RIT_GetMaskTimerCount(RIT_Type *base) -{ - uint16_t valueH = 0U; - uint32_t valueL = 0U; - - /* MASK_H should be read before MASK */ - valueH = base->MASK_H; - valueL = base->MASK; - - return (((uint64_t)valueH << 32U) + (uint64_t)(valueL)); -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_rit.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_rit.h deleted file mode 100644 index e6f5e6be868..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_rit.h +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_RIT_H_ -#define _FSL_RIT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup rit - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_RIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! @brief List of RIT status flags */ -typedef enum _rit_status_flags -{ - kRIT_TimerFlag = RIT_CTRL_RITINT_MASK, /*!< Timer flag */ -} rit_status_flags_t; - -/*! - * @brief RIT config structure - * - * This structure holds the configuration settings for the RIT peripheral. To initialize this - * structure to reasonable defaults, call the RIT_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _rit_config -{ - bool enableRunInDebug; /*!< true: The timer is halted when the processor is halted for debugging.; false: Debug has - no effect on the timer operation. */ -} rit_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the RIT clock, enables the RIT module, and configures the peripheral for basic operations. - * - * @note This API should be called at the beginning of the application using the RIT driver. - * - * @param base RIT peripheral base address - * @param config Pointer to the user's RIT config structure - */ -void RIT_Init(RIT_Type *base, const rit_config_t *config); - -/*! - * @brief Gates the RIT clock and disables the RIT module. - * - * @param base RIT peripheral base address - */ -void RIT_Deinit(RIT_Type *base); - -/*! - * @brief Fills in the RIT configuration structure with the default settings. - * - * The default values are as follows. - * @code - * config->enableRunInDebug = false; - * @endcode - * @param config Pointer to the onfiguration structure. - */ -void RIT_GetDefaultConfig(rit_config_t *config); - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the RIT status flags. - * - * @param base RIT peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::rit_status_flags_t - */ -static inline uint32_t RIT_GetStatusFlags(RIT_Type *base) -{ - return (base->CTRL); -} - -/*! - * @brief Clears the RIT status flags. - * - * @param base RIT peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::rit_status_flags_t - */ -static inline void RIT_ClearStatusFlags(RIT_Type *base, uint32_t mask) -{ - base->CTRL |= mask; -} - -/*! @}*/ - -/*! - * @name Read and Write the timer period - * @{ - */ - -/*! - * @brief Sets the timer period in units of count. - * - * Timers begin counting from the value set by this function until it XXXXXXX, - * then it counting the value again. - * Software must stop the counter before reloading it with a new value.. - * - * @note Users can call the utility macros provided in fsl_common.h to convert to ticks - * - * @param base RIT peripheral base address - * @param count Timer period in units of ticks - */ -void RIT_SetTimerCompare(RIT_Type *base, uint64_t count); - -/*! - * @brief Sets the mask bit of count compare. - * - * Timers begin counting from the value set by this function until it XXXXXXX, - * then it counting the value again. - * Software must stop the counter before reloading it with a new value.. - * - * @note Users can call the utility macros provided in fsl_common.h to convert to ticks - * - * @param base RIT peripheral base address - * @param count Timer period in units of ticks - */ -void RIT_SetMaskBit(RIT_Type *base, uint64_t count); - -/*! - * @brief Reads the current timer counting value of compare register. - * - * This function returns the real-time timer counting value, in a range from 0 to a - * timer period. - * - * @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec - * - * @param base RIT peripheral base address - * - * @return Current timer counting value in ticks - */ -uint64_t RIT_GetCompareTimerCount(RIT_Type *base); - -/*! - * @brief Reads the current timer counting value of counter register. - * - * This function returns the real-time timer counting value, in a range from 0 to a - * timer period. - * - * @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec - * - * @param base RIT peripheral base address - * - * @return Current timer counting value in ticks - */ -uint64_t RIT_GetCounterTimerCount(RIT_Type *base); - -/*! - * @brief Reads the current timer counting value of mask register. - * - * This function returns the real-time timer counting value, in a range from 0 to a - * timer period. - * - * @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec - * - * @param base RIT peripheral base address - * - * @return Current timer counting value in ticks - */ -uint64_t RIT_GetMaskTimerCount(RIT_Type *base); - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the timer counting. - * - * After calling this function, timers load initial value(0U), count up to desired value or over-flow - * then the counter will count up again. Each time a timer reaches desired value, - * it generates a XXXXXXX and sets XXXXXXX. - * - * @param base RIT peripheral base address - */ -static inline void RIT_StartTimer(RIT_Type *base) -{ - base->CTRL |= RIT_CTRL_RITEN_MASK; -} - -/*! - * @brief Stops the timer counting. - * - * This function stop timer counting. Timer reload their new value - * after the next time they call the RIT_StartTimer. - * - * @param base RIT peripheral base address - * @param channel Timer channel number. - */ -static inline void RIT_StopTimer(RIT_Type *base) -{ - /* Disable RIT timers */ - base->CTRL &= ~RIT_CTRL_RITEN_MASK; -} - -/*! @}*/ - -static inline void RIT_ClearCounter(RIT_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= RIT_CTRL_RITENCLR_MASK; - } - else - { - base->CTRL &= ~RIT_CTRL_RITENCLR_MASK; - } -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_RIT_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_rng.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_rng.h deleted file mode 100644 index f08bdc4221d..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_rng.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_RNG_DRIVER_H_ -#define _FSL_RNG_DRIVER_H_ - -#include "fsl_common.h" - -#if defined(FSL_FEATURE_SOC_LPC_RNG_COUNT) && FSL_FEATURE_SOC_LPC_RNG_COUNT - -/*! - * @addtogroup rng - * @{ - */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief RNG driver version 2.0.0. - * - * Current version: 2.0.0 - * - * Change log: - * - Version 2.0.0 - * - Initial version. - */ -#define FSL_RNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Gets random data. - * - * This function returns single 32 bit random number. - * - * @return random data - */ -static inline uint32_t RNG_GetRandomData(void) -{ - return OTP_API->rngRead(); -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* FSL_FEATURE_SOC_LPC_RNG_COUNT */ -#endif /*_FSL_TRNG_H_*/ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_rtc.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_rtc.c deleted file mode 100644 index 4165af84e3f..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_rtc.c +++ /dev/null @@ -1,288 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_rtc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define SECONDS_IN_A_DAY (86400U) -#define SECONDS_IN_A_HOUR (3600U) -#define SECONDS_IN_A_MINUTE (60U) -#define DAYS_IN_A_YEAR (365U) -#define YEAR_RANGE_START (1970U) -#define YEAR_RANGE_END (2099U) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Checks whether the date and time passed in is valid - * - * @param datetime Pointer to structure where the date and time details are stored - * - * @return Returns false if the date & time details are out of range; true if in range - */ -static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime); - -/*! - * @brief Converts time data from datetime to seconds - * - * @param datetime Pointer to datetime structure where the date and time details are stored - * - * @return The result of the conversion in seconds - */ -static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime); - -/*! - * @brief Converts time data from seconds to a datetime structure - * - * @param seconds Seconds value that needs to be converted to datetime format - * @param datetime Pointer to the datetime structure where the result of the conversion is stored - */ -static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime); - -/******************************************************************************* - * Code - ******************************************************************************/ -static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Check year, month, hour, minute, seconds */ - if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || - (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) - { - /* If not correct then error*/ - return false; - } - - /* Adjust the days in February for a leap year */ - if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0)) - { - daysPerMonth[2] = 29U; - } - - /* Check the validity of the day */ - if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) - { - return false; - } - - return true; -} - -static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Number of days from begin of the non Leap-year*/ - /* Number of days from begin of the non Leap-year*/ - uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; - uint32_t seconds; - - /* Compute number of days from 1970 till given year*/ - seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; - /* Add leap year days */ - seconds += ((datetime->year / 4) - (1970U / 4)); - /* Add number of days till given month*/ - seconds += monthDays[datetime->month]; - /* Add days in given month. We subtract the current day as it is - * represented in the hours, minutes and seconds field*/ - seconds += (datetime->day - 1); - /* For leap year if month less than or equal to Febraury, decrement day counter*/ - if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) - { - seconds--; - } - - seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + - (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; - - return seconds; -} - -static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t x; - uint32_t secondsRemaining, days; - uint16_t daysInYear; - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Start with the seconds value that is passed in to be converted to date time format */ - secondsRemaining = seconds; - - /* Calcuate the number of days, we add 1 for the current day which is represented in the - * hours and seconds field - */ - days = secondsRemaining / SECONDS_IN_A_DAY + 1; - - /* Update seconds left*/ - secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; - - /* Calculate the datetime hour, minute and second fields */ - datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; - secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; - datetime->minute = secondsRemaining / 60U; - datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; - - /* Calculate year */ - daysInYear = DAYS_IN_A_YEAR; - datetime->year = YEAR_RANGE_START; - while (days > daysInYear) - { - /* Decrease day count by a year and increment year by 1 */ - days -= daysInYear; - datetime->year++; - - /* Adjust the number of days for a leap year */ - if (datetime->year & 3U) - { - daysInYear = DAYS_IN_A_YEAR; - } - else - { - daysInYear = DAYS_IN_A_YEAR + 1; - } - } - - /* Adjust the days in February for a leap year */ - if (!(datetime->year & 3U)) - { - daysPerMonth[2] = 29U; - } - - for (x = 1U; x <= 12U; x++) - { - if (days <= daysPerMonth[x]) - { - datetime->month = x; - break; - } - else - { - days -= daysPerMonth[x]; - } - } - - datetime->day = days; -} - -void RTC_Init(RTC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the RTC peripheral clock */ - CLOCK_EnableClock(kCLOCK_Rtc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Make sure the reset bit is cleared */ - base->CTRL &= ~RTC_CTRL_SWRESET_MASK; - - /* Make sure the RTC OSC is powered up */ - base->CTRL &= ~RTC_CTRL_RTC_OSC_PD_MASK; -} - -status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Return error if the time provided is not valid */ - if (!(RTC_CheckDatetimeFormat(datetime))) - { - return kStatus_InvalidArgument; - } - - /* Set time in seconds */ - base->COUNT = RTC_ConvertDatetimeToSeconds(datetime); - - return kStatus_Success; -} - -void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t seconds = 0; - - seconds = base->COUNT; - RTC_ConvertSecondsToDatetime(seconds, datetime); -} - -status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) -{ - assert(alarmTime); - - uint32_t alarmSeconds = 0; - uint32_t currSeconds = 0; - - /* Return error if the alarm time provided is not valid */ - if (!(RTC_CheckDatetimeFormat(alarmTime))) - { - return kStatus_InvalidArgument; - } - - alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime); - - /* Get the current time */ - currSeconds = base->COUNT; - - /* Return error if the alarm time has passed */ - if (alarmSeconds < currSeconds) - { - return kStatus_Fail; - } - - /* Set alarm in seconds*/ - base->MATCH = alarmSeconds; - - return kStatus_Success; -} - -void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t alarmSeconds = 0; - - /* Get alarm in seconds */ - alarmSeconds = base->MATCH; - - RTC_ConvertSecondsToDatetime(alarmSeconds, datetime); -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_rtc.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_rtc.h deleted file mode 100644 index 83c5ba85496..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_rtc.h +++ /dev/null @@ -1,340 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_RTC_H_ -#define _FSL_RTC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup rtc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! @brief List of RTC interrupts */ -typedef enum _rtc_interrupt_enable -{ - kRTC_AlarmInterruptEnable = RTC_CTRL_ALARMDPD_EN_MASK, /*!< Alarm interrupt.*/ - kRTC_WakeupInterruptEnable = RTC_CTRL_WAKEDPD_EN_MASK /*!< Wake-up interrupt.*/ -} rtc_interrupt_enable_t; - -/*! @brief List of RTC flags */ -typedef enum _rtc_status_flags -{ - kRTC_AlarmFlag = RTC_CTRL_ALARM1HZ_MASK, /*!< Alarm flag*/ - kRTC_WakeupFlag = RTC_CTRL_WAKE1KHZ_MASK /*!< 1kHz wake-up timer flag*/ -} rtc_status_flags_t; - -/*! @brief Structure is used to hold the date and time */ -typedef struct _rtc_datetime -{ - uint16_t year; /*!< Range from 1970 to 2099.*/ - uint8_t month; /*!< Range from 1 to 12.*/ - uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ - uint8_t hour; /*!< Range from 0 to 23.*/ - uint8_t minute; /*!< Range from 0 to 59.*/ - uint8_t second; /*!< Range from 0 to 59.*/ -} rtc_datetime_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the RTC clock and enables the RTC oscillator. - * - * @note This API should be called at the beginning of the application using the RTC driver. - * - * @param base RTC peripheral base address - */ -void RTC_Init(RTC_Type *base); - -/*! - * @brief Stop the timer and gate the RTC clock - * - * @param base RTC peripheral base address - */ -static inline void RTC_Deinit(RTC_Type *base) -{ - /* Stop the RTC timer */ - base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the module clock */ - CLOCK_DisableClock(kCLOCK_Rtc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! @}*/ - -/*! - * @name Current Time & Alarm - * @{ - */ - -/*! - * @brief Sets the RTC date and time according to the given time structure. - * - * The RTC counter must be stopped prior to calling this function as writes to the RTC - * seconds register will fail if the RTC counter is running. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the date and time details to set are stored - * - * @return kStatus_Success: Success in setting the time and starting the RTC - * kStatus_InvalidArgument: Error because the datetime format is incorrect - */ -status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime); - -/*! - * @brief Gets the RTC time and stores it in the given time structure. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the date and time details are stored. - */ -void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime); - -/*! - * @brief Sets the RTC alarm time - * - * The function checks whether the specified alarm time is greater than the present - * time. If not, the function does not set the alarm and returns an error. - * - * @param base RTC peripheral base address - * @param alarmTime Pointer to structure where the alarm time is stored. - * - * @return kStatus_Success: success in setting the RTC alarm - * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect - * kStatus_Fail: Error because the alarm time has already passed - */ -status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime); - -/*! - * @brief Returns the RTC alarm time. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the alarm date and time details are stored. - */ -void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime); - -/*! @}*/ - -/*! - * @brief Enable the RTC high resolution timer and set the wake-up time. - * - * @param base RTC peripheral base address - * @param wakeupValue The value to be loaded into the RTC WAKE register - */ -static inline void RTC_SetWakeupCount(RTC_Type *base, uint16_t wakeupValue) -{ - /* Enable the 1kHz RTC timer */ - base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK; - - /* Set the start count value into the wake-up timer */ - base->WAKE = wakeupValue; -} - -/*! - * @brief Read actual RTC counter value. - * - * @param base RTC peripheral base address - */ -static inline uint16_t RTC_GetWakeupCount(RTC_Type *base) -{ - /* Read wake-up counter */ - return RTC_WAKE_VAL(base->WAKE); -} - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected RTC interrupts. - * - * @param base RTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) -{ - uint32_t reg = base->CTRL; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK); - reg |= mask; - - base->CTRL = reg; -} - -/*! - * @brief Disables the selected RTC interrupts. - * - * @param base RTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) -{ - uint32_t reg = base->CTRL; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK | mask); - - base->CTRL = reg; -} - -/*! - * @brief Gets the enabled RTC interrupts. - * - * @param base RTC peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) -{ - return (base->CTRL & (RTC_CTRL_ALARMDPD_EN_MASK | RTC_CTRL_WAKEDPD_EN_MASK)); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the RTC status flags - * - * @param base RTC peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::rtc_status_flags_t - */ -static inline uint32_t RTC_GetStatusFlags(RTC_Type *base) -{ - return (base->CTRL & (RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK)); -} - -/*! - * @brief Clears the RTC status flags. - * - * @param base RTC peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::rtc_status_flags_t - */ -static inline void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) -{ - uint32_t reg = base->CTRL; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK); - - /* Write 1 to the flags we wish to clear */ - reg |= mask; - - base->CTRL = reg; -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the RTC time counter. - * - * After calling this function, the timer counter increments once a second provided SR[TOF] or - * SR[TIF] are not set. - * - * @param base RTC peripheral base address - */ -static inline void RTC_StartTimer(RTC_Type *base) -{ - base->CTRL |= RTC_CTRL_RTC_EN_MASK; -} - -/*! - * @brief Stops the RTC time counter. - * - * RTC's seconds register can be written to only when the timer is stopped. - * - * @param base RTC peripheral base address - */ -static inline void RTC_StopTimer(RTC_Type *base) -{ - base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; -} - -/*! @}*/ - -/*! - * @brief Performs a software reset on the RTC module. - * - * This resets all RTC registers to their reset value. The bit is cleared by software explicitly clearing it. - * - * @param base RTC peripheral base address - */ -static inline void RTC_Reset(RTC_Type *base) -{ - base->CTRL |= RTC_CTRL_SWRESET_MASK; - base->CTRL &= ~RTC_CTRL_SWRESET_MASK; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_RTC_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_sctimer.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_sctimer.c deleted file mode 100644 index 22f9d3df138..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_sctimer.c +++ /dev/null @@ -1,535 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_sctimer.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief Typedef for interrupt handler. */ -typedef void (*sctimer_isr_t)(SCT_Type *base); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base SCTimer peripheral base address - * - * @return The SCTimer instance - */ -static uint32_t SCTIMER_GetInstance(SCT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to SCT bases for each instance. */ -static SCT_Type *const s_sctBases[] = SCT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to SCT clocks for each instance. */ -static const clock_ip_name_t s_sctClocks[] = SCT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Pointers to SCT resets for each instance. */ -static const reset_ip_name_t s_sctResets[] = SCT_RSTS; - -/*!< @brief SCTimer event Callback function. */ -static sctimer_event_callback_t s_eventCallback[FSL_FEATURE_SCT_NUMBER_OF_EVENTS]; - -/*!< @brief Keep track of SCTimer event number */ -static uint32_t s_currentEvent; - -/*!< @brief Keep track of SCTimer state number */ -static uint32_t s_currentState; - -/*!< @brief Keep track of SCTimer match/capture register number */ -static uint32_t s_currentMatch; - -/*! @brief Pointer to SCTimer IRQ handler */ -static sctimer_isr_t s_sctimerIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t SCTIMER_GetInstance(SCT_Type *base) -{ - uint32_t instance; - uint32_t sctArrayCount = (sizeof(s_sctBases) / sizeof(s_sctBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < sctArrayCount; instance++) - { - if (s_sctBases[instance] == base) - { - break; - } - } - - assert(instance < sctArrayCount); - - return instance; -} - -status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config) -{ - assert(config); - uint32_t i; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the SCTimer clock*/ - CLOCK_EnableClock(s_sctClocks[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the module */ - RESET_PeripheralReset(s_sctResets[SCTIMER_GetInstance(base)]); - - /* Setup the counter operation */ - base->CONFIG = SCT_CONFIG_CKSEL(config->clockSelect) | SCT_CONFIG_CLKMODE(config->clockMode) | - SCT_CONFIG_UNIFY(config->enableCounterUnify); - - /* Write to the control register, clear the counter and keep the counters halted */ - base->CTRL = SCT_CTRL_BIDIR_L(config->enableBidirection_l) | SCT_CTRL_PRE_L(config->prescale_l) | - SCT_CTRL_CLRCTR_L_MASK | SCT_CTRL_HALT_L_MASK; - - if (!(config->enableCounterUnify)) - { - base->CTRL |= SCT_CTRL_BIDIR_H(config->enableBidirection_h) | SCT_CTRL_PRE_H(config->prescale_h) | - SCT_CTRL_CLRCTR_H_MASK | SCT_CTRL_HALT_H_MASK; - } - - /* Initial state of channel output */ - base->OUTPUT = config->outInitState; - - /* Clear the global variables */ - s_currentEvent = 0; - s_currentState = 0; - s_currentMatch = 0; - - /* Clear the callback array */ - for (i = 0; i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) - { - s_eventCallback[i] = NULL; - } - - /* Save interrupt handler */ - s_sctimerIsr = SCTIMER_EventHandleIRQ; - - return kStatus_Success; -} - -void SCTIMER_Deinit(SCT_Type *base) -{ - /* Halt the counters */ - base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the SCTimer clock*/ - CLOCK_DisableClock(s_sctClocks[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void SCTIMER_GetDefaultConfig(sctimer_config_t *config) -{ - assert(config); - - /* SCT operates as a unified 32-bit counter */ - config->enableCounterUnify = true; - /* System clock clocks the entire SCT module */ - config->clockMode = kSCTIMER_System_ClockMode; - /* This is used only by certain clock modes */ - config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - /* Up count mode only for the unified counter */ - config->enableBidirection_l = false; - /* Up count mode only for Counte_H */ - config->enableBidirection_h = false; - /* Prescale factor of 1 */ - config->prescale_l = 0; - /* Prescale factor of 1 for Counter_H*/ - config->prescale_h = 0; - /* Clear outputs */ - config->outInitState = 0; -} - -status_t SCTIMER_SetupPwm(SCT_Type *base, - const sctimer_pwm_signal_param_t *pwmParams, - sctimer_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - uint32_t *event) -{ - assert(pwmParams); - assert(srcClock_Hz); - assert(pwmFreq_Hz); - - uint32_t period, pulsePeriod = 0; - uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1); - uint32_t periodEvent, pulseEvent; - uint32_t reg; - - /* This function will create 2 events, return an error if we do not have enough events available */ - if ((s_currentEvent + 2) > FSL_FEATURE_SCT_NUMBER_OF_EVENTS) - { - return kStatus_Fail; - } - - if (pwmParams->dutyCyclePercent == 0) - { - return kStatus_Fail; - } - - /* Set unify bit to operate in 32-bit counter mode */ - base->CONFIG |= SCT_CONFIG_UNIFY_MASK; - - /* Use bi-directional mode for center-aligned PWM */ - if (mode == kSCTIMER_CenterAlignedPwm) - { - base->CTRL |= SCT_CTRL_BIDIR_L_MASK; - } - - /* Calculate PWM period match value */ - if (mode == kSCTIMER_EdgeAlignedPwm) - { - period = (sctClock / pwmFreq_Hz) - 1; - } - else - { - period = sctClock / (pwmFreq_Hz * 2); - } - - /* Calculate pulse width match value */ - pulsePeriod = (period * pwmParams->dutyCyclePercent) / 100; - - /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ - if (pwmParams->dutyCyclePercent >= 100) - { - pulsePeriod = period + 2; - } - - /* Schedule an event when we reach the PWM period */ - SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, period, 0, kSCTIMER_Counter_L, &periodEvent); - - /* Schedule an event when we reach the pulse width */ - SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, pulsePeriod, 0, kSCTIMER_Counter_L, &pulseEvent); - - /* Reset the counter when we reach the PWM period */ - SCTIMER_SetupCounterLimitAction(base, kSCTIMER_Counter_L, periodEvent); - - /* Return the period event to the user */ - *event = periodEvent; - - /* For high-true level */ - if (pwmParams->level == kSCTIMER_HighTrue) - { - /* Set the initial output level to low which is the inactive state */ - base->OUTPUT &= ~(1U << pwmParams->output); - - if (mode == kSCTIMER_EdgeAlignedPwm) - { - /* Set the output when we reach the PWM period */ - SCTIMER_SetupOutputSetAction(base, pwmParams->output, periodEvent); - /* Clear the output when we reach the PWM pulse value */ - SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent); - } - else - { - /* Clear the output when we reach the PWM pulse event */ - SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent); - /* Reverse output when down counting */ - reg = base->OUTPUTDIRCTRL; - reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output)); - reg |= (1U << (2 * pwmParams->output)); - base->OUTPUTDIRCTRL = reg; - } - } - /* For low-true level */ - else - { - /* Set the initial output level to high which is the inactive state */ - base->OUTPUT |= (1U << pwmParams->output); - - if (mode == kSCTIMER_EdgeAlignedPwm) - { - /* Clear the output when we reach the PWM period */ - SCTIMER_SetupOutputClearAction(base, pwmParams->output, periodEvent); - /* Set the output when we reach the PWM pulse value */ - SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent); - } - else - { - /* Set the output when we reach the PWM pulse event */ - SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent); - /* Reverse output when down counting */ - reg = base->OUTPUTDIRCTRL; - reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output)); - reg |= (1U << (2 * pwmParams->output)); - base->OUTPUTDIRCTRL = reg; - } - } - - return kStatus_Success; -} - -void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event) - -{ - assert(dutyCyclePercent > 0); - - uint32_t periodMatchReg, pulseMatchReg; - uint32_t pulsePeriod = 0, period; - - /* Retrieve the match register number for the PWM period */ - periodMatchReg = base->EVENT[event].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK; - - /* Retrieve the match register number for the PWM pulse period */ - pulseMatchReg = base->EVENT[event + 1].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK; - - period = base->SCTMATCH[periodMatchReg]; - - /* Calculate pulse width match value */ - pulsePeriod = (period * dutyCyclePercent) / 100; - - /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ - if (dutyCyclePercent >= 100) - { - pulsePeriod = period + 2; - } - - /* Stop the counter before updating match register */ - SCTIMER_StopTimer(base, kSCTIMER_Counter_L); - - /* Update dutycycle */ - base->SCTMATCH[pulseMatchReg] = SCT_SCTMATCH_MATCHn_L(pulsePeriod); - base->SCTMATCHREL[pulseMatchReg] = SCT_SCTMATCHREL_RELOADn_L(pulsePeriod); - - /* Restart the counter */ - SCTIMER_StartTimer(base, kSCTIMER_Counter_L); -} - -status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, - sctimer_event_t howToMonitor, - uint32_t matchValue, - uint32_t whichIO, - sctimer_counter_t whichCounter, - uint32_t *event) -{ - uint32_t combMode = (((uint32_t)howToMonitor & SCT_EVENT_CTRL_COMBMODE_MASK) >> SCT_EVENT_CTRL_COMBMODE_SHIFT); - uint32_t currentCtrlVal = howToMonitor; - - /* Return an error if we have hit the limit in terms of number of events created */ - if (s_currentEvent >= FSL_FEATURE_SCT_NUMBER_OF_EVENTS) - { - return kStatus_Fail; - } - - /* IO only mode */ - if (combMode == 0x2U) - { - base->EVENT[s_currentEvent].CTRL = currentCtrlVal | SCT_EVENT_CTRL_IOSEL(whichIO); - } - /* Match mode only */ - else if (combMode == 0x1U) - { - /* Return an error if we have hit the limit in terms of number of number of match registers */ - if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - return kStatus_Fail; - } - - currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch); - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue); - base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue); - } - else - { - /* Select the counter, no need for this if operating in 32-bit mode */ - currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter); - base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue); - base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue); - } - base->EVENT[s_currentEvent].CTRL = currentCtrlVal; - /* Increment the match register number */ - s_currentMatch++; - } - /* Use both Match & IO */ - else - { - /* Return an error if we have hit the limit in terms of number of number of match registers */ - if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - return kStatus_Fail; - } - - currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch) | SCT_EVENT_CTRL_IOSEL(whichIO); - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue); - base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue); - } - else - { - /* Select the counter, no need for this if operating in 32-bit mode */ - currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter); - base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue); - base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue); - } - base->EVENT[s_currentEvent].CTRL = currentCtrlVal; - /* Increment the match register number */ - s_currentMatch++; - } - - /* Enable the event in the current state */ - base->EVENT[s_currentEvent].STATE = (1U << s_currentState); - - /* Return the event number */ - *event = s_currentEvent; - - /* Increment the event number */ - s_currentEvent++; - - return kStatus_Success; -} - -void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event) -{ - /* Enable event in the current state */ - base->EVENT[event].STATE |= (1U << s_currentState); -} - -status_t SCTIMER_IncreaseState(SCT_Type *base) -{ - /* Return an error if we have hit the limit in terms of states used */ - if (s_currentState >= FSL_FEATURE_SCT_NUMBER_OF_STATES) - { - return kStatus_Fail; - } - - s_currentState++; - - return kStatus_Success; -} - -uint32_t SCTIMER_GetCurrentState(SCT_Type *base) -{ - return s_currentState; -} - -void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - uint32_t reg; - - /* Set the same event to set and clear the output */ - base->OUT[whichIO].CLR |= (1U << event); - base->OUT[whichIO].SET |= (1U << event); - - /* Set the conflict resolution to toggle output */ - reg = base->RES; - reg &= ~(SCT_RES_O0RES_MASK << (2 * whichIO)); - reg |= (uint32_t)(kSCTIMER_ResolveToggle << (2 * whichIO)); - base->RES = reg; -} - -status_t SCTIMER_SetupCaptureAction(SCT_Type *base, - sctimer_counter_t whichCounter, - uint32_t *captureRegister, - uint32_t event) -{ - /* Return an error if we have hit the limit in terms of number of capture/match registers used */ - if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - return kStatus_Fail; - } - - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - /* Set the bit to enable event */ - base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_L(1 << event); - - /* Set this resource to be a capture rather than match */ - base->REGMODE |= SCT_REGMODE_REGMOD_L(1 << s_currentMatch); - } - else - { - /* Set bit to enable event */ - base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_H(1 << event); - - /* Set this resource to be a capture rather than match */ - base->REGMODE |= SCT_REGMODE_REGMOD_H(1 << s_currentMatch); - } - - /* Return the match register number */ - *captureRegister = s_currentMatch; - - /* Increase the match register number */ - s_currentMatch++; - - return kStatus_Success; -} - -void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event) -{ - s_eventCallback[event] = callback; -} - -void SCTIMER_EventHandleIRQ(SCT_Type *base) -{ - uint32_t eventFlag = SCT0->EVFLAG; - /* Only clear the flags whose interrupt field is enabled */ - uint32_t clearFlag = (eventFlag & SCT0->EVEN); - uint32_t mask = eventFlag; - int i = 0; - - /* Invoke the callback for certain events */ - for (i = 0; (i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS) && (mask != 0); i++) - { - if (mask & 0x1) - { - if (s_eventCallback[i] != NULL) - { - s_eventCallback[i](); - } - } - mask >>= 1; - } - - /* Clear event interrupt flag */ - SCT0->EVFLAG = clearFlag; -} - -void SCT0_IRQHandler(void) -{ - s_sctimerIsr(SCT0); -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_sctimer.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_sctimer.h deleted file mode 100644 index e799e1eceff..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_sctimer.h +++ /dev/null @@ -1,822 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_SCTIMER_H_ -#define _FSL_SCTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup sctimer - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! @brief SCTimer PWM operation modes */ -typedef enum _sctimer_pwm_mode -{ - kSCTIMER_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */ - kSCTIMER_CenterAlignedPwm /*!< Center-aligned PWM */ -} sctimer_pwm_mode_t; - -/*! @brief SCTimer counters when working as two independent 16-bit counters */ -typedef enum _sctimer_counter -{ - kSCTIMER_Counter_L = 0U, /*!< Counter L */ - kSCTIMER_Counter_H /*!< Counter H */ -} sctimer_counter_t; - -/*! @brief List of SCTimer input pins */ -typedef enum _sctimer_input -{ - kSCTIMER_Input_0 = 0U, /*!< SCTIMER input 0 */ - kSCTIMER_Input_1, /*!< SCTIMER input 1 */ - kSCTIMER_Input_2, /*!< SCTIMER input 2 */ - kSCTIMER_Input_3, /*!< SCTIMER input 3 */ - kSCTIMER_Input_4, /*!< SCTIMER input 4 */ - kSCTIMER_Input_5, /*!< SCTIMER input 5 */ - kSCTIMER_Input_6, /*!< SCTIMER input 6 */ - kSCTIMER_Input_7 /*!< SCTIMER input 7 */ -} sctimer_input_t; - -/*! @brief List of SCTimer output pins */ -typedef enum _sctimer_out -{ - kSCTIMER_Out_0 = 0U, /*!< SCTIMER output 0*/ - kSCTIMER_Out_1, /*!< SCTIMER output 1 */ - kSCTIMER_Out_2, /*!< SCTIMER output 2 */ - kSCTIMER_Out_3, /*!< SCTIMER output 3 */ - kSCTIMER_Out_4, /*!< SCTIMER output 4 */ - kSCTIMER_Out_5, /*!< SCTIMER output 5 */ - kSCTIMER_Out_6, /*!< SCTIMER output 6 */ - kSCTIMER_Out_7 /*!< SCTIMER output 7 */ -} sctimer_out_t; - -/*! @brief SCTimer PWM output pulse mode: high-true, low-true or no output */ -typedef enum _sctimer_pwm_level_select -{ - kSCTIMER_LowTrue = 0U, /*!< Low true pulses */ - kSCTIMER_HighTrue /*!< High true pulses */ -} sctimer_pwm_level_select_t; - -/*! @brief Options to configure a SCTimer PWM signal */ -typedef struct _sctimer_pwm_signal_param -{ - sctimer_out_t output; /*!< The output pin to use to generate the PWM signal */ - sctimer_pwm_level_select_t level; /*!< PWM output active level select. */ - uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 1 to 100 - 100 = always active signal (100% duty cycle).*/ -} sctimer_pwm_signal_param_t; - -/*! @brief SCTimer clock mode options */ -typedef enum _sctimer_clock_mode -{ - kSCTIMER_System_ClockMode = 0U, /*!< System Clock Mode */ - kSCTIMER_Sampled_ClockMode, /*!< Sampled System Clock Mode */ - kSCTIMER_Input_ClockMode, /*!< SCT Input Clock Mode */ - kSCTIMER_Asynchronous_ClockMode /*!< Asynchronous Mode */ -} sctimer_clock_mode_t; - -/*! @brief SCTimer clock select options */ -typedef enum _sctimer_clock_select -{ - kSCTIMER_Clock_On_Rise_Input_0 = 0U, /*!< Rising edges on input 0 */ - kSCTIMER_Clock_On_Fall_Input_0, /*!< Falling edges on input 0 */ - kSCTIMER_Clock_On_Rise_Input_1, /*!< Rising edges on input 1 */ - kSCTIMER_Clock_On_Fall_Input_1, /*!< Falling edges on input 1 */ - kSCTIMER_Clock_On_Rise_Input_2, /*!< Rising edges on input 2 */ - kSCTIMER_Clock_On_Fall_Input_2, /*!< Falling edges on input 2 */ - kSCTIMER_Clock_On_Rise_Input_3, /*!< Rising edges on input 3 */ - kSCTIMER_Clock_On_Fall_Input_3, /*!< Falling edges on input 3 */ - kSCTIMER_Clock_On_Rise_Input_4, /*!< Rising edges on input 4 */ - kSCTIMER_Clock_On_Fall_Input_4, /*!< Falling edges on input 4 */ - kSCTIMER_Clock_On_Rise_Input_5, /*!< Rising edges on input 5 */ - kSCTIMER_Clock_On_Fall_Input_5, /*!< Falling edges on input 5 */ - kSCTIMER_Clock_On_Rise_Input_6, /*!< Rising edges on input 6 */ - kSCTIMER_Clock_On_Fall_Input_6, /*!< Falling edges on input 6 */ - kSCTIMER_Clock_On_Rise_Input_7, /*!< Rising edges on input 7 */ - kSCTIMER_Clock_On_Fall_Input_7 /*!< Falling edges on input 7 */ -} sctimer_clock_select_t; - -/*! - * @brief SCTimer output conflict resolution options. - * - * Specifies what action should be taken if multiple events dictate that a given output should be - * both set and cleared at the same time - */ -typedef enum _sctimer_conflict_resolution -{ - kSCTIMER_ResolveNone = 0U, /*!< No change */ - kSCTIMER_ResolveSet, /*!< Set output */ - kSCTIMER_ResolveClear, /*!< Clear output */ - kSCTIMER_ResolveToggle /*!< Toggle output */ -} sctimer_conflict_resolution_t; - -/*! @brief List of SCTimer event types */ -typedef enum _sctimer_event -{ - kSCTIMER_InputLowOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - - kSCTIMER_MatchEventOnly = - (1 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - - kSCTIMER_InputLowEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - - kSCTIMER_InputLowAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT) -} sctimer_event_t; - -/*! @brief SCTimer callback typedef. */ -typedef void (*sctimer_event_callback_t)(void); - -/*! @brief List of SCTimer interrupts */ -typedef enum _sctimer_interrupt_enable -{ - kSCTIMER_Event0InterruptEnable = (1U << 0), /*!< Event 0 interrupt */ - kSCTIMER_Event1InterruptEnable = (1U << 1), /*!< Event 1 interrupt */ - kSCTIMER_Event2InterruptEnable = (1U << 2), /*!< Event 2 interrupt */ - kSCTIMER_Event3InterruptEnable = (1U << 3), /*!< Event 3 interrupt */ - kSCTIMER_Event4InterruptEnable = (1U << 4), /*!< Event 4 interrupt */ - kSCTIMER_Event5InterruptEnable = (1U << 5), /*!< Event 5 interrupt */ - kSCTIMER_Event6InterruptEnable = (1U << 6), /*!< Event 6 interrupt */ - kSCTIMER_Event7InterruptEnable = (1U << 7), /*!< Event 7 interrupt */ - kSCTIMER_Event8InterruptEnable = (1U << 8), /*!< Event 8 interrupt */ - kSCTIMER_Event9InterruptEnable = (1U << 9), /*!< Event 9 interrupt */ - kSCTIMER_Event10InterruptEnable = (1U << 10), /*!< Event 10 interrupt */ - kSCTIMER_Event11InterruptEnable = (1U << 11), /*!< Event 11 interrupt */ - kSCTIMER_Event12InterruptEnable = (1U << 12), /*!< Event 12 interrupt */ -} sctimer_interrupt_enable_t; - -/*! @brief List of SCTimer flags */ -typedef enum _sctimer_status_flags -{ - kSCTIMER_Event0Flag = (1U << 0), /*!< Event 0 Flag */ - kSCTIMER_Event1Flag = (1U << 1), /*!< Event 1 Flag */ - kSCTIMER_Event2Flag = (1U << 2), /*!< Event 2 Flag */ - kSCTIMER_Event3Flag = (1U << 3), /*!< Event 3 Flag */ - kSCTIMER_Event4Flag = (1U << 4), /*!< Event 4 Flag */ - kSCTIMER_Event5Flag = (1U << 5), /*!< Event 5 Flag */ - kSCTIMER_Event6Flag = (1U << 6), /*!< Event 6 Flag */ - kSCTIMER_Event7Flag = (1U << 7), /*!< Event 7 Flag */ - kSCTIMER_Event8Flag = (1U << 8), /*!< Event 8 Flag */ - kSCTIMER_Event9Flag = (1U << 9), /*!< Event 9 Flag */ - kSCTIMER_Event10Flag = (1U << 10), /*!< Event 10 Flag */ - kSCTIMER_Event11Flag = (1U << 11), /*!< Event 11 Flag */ - kSCTIMER_Event12Flag = (1U << 12), /*!< Event 12 Flag */ - kSCTIMER_BusErrorLFlag = - (1U << SCT_CONFLAG_BUSERRL_SHIFT), /*!< Bus error due to write when L counter was not halted */ - kSCTIMER_BusErrorHFlag = - (1U << SCT_CONFLAG_BUSERRH_SHIFT) /*!< Bus error due to write when H counter was not halted */ -} sctimer_status_flags_t; - -/*! - * @brief SCTimer configuration structure - * - * This structure holds the configuration settings for the SCTimer peripheral. To initialize this - * structure to reasonable defaults, call the SCTMR_GetDefaultConfig() function and pass a - * pointer to the configuration structure instance. - * - * The configuration structure can be made constant so as to reside in flash. - */ -typedef struct _sctimer_config -{ - bool enableCounterUnify; /*!< true: SCT operates as a unified 32-bit counter; - false: SCT operates as two 16-bit counters */ - sctimer_clock_mode_t clockMode; /*!< SCT clock mode value */ - sctimer_clock_select_t clockSelect; /*!< SCT clock select value */ - bool enableBidirection_l; /*!< true: Up-down count mode for the L or unified counter - false: Up count mode only for the L or unified counter */ - bool enableBidirection_h; /*!< true: Up-down count mode for the H or unified counter - false: Up count mode only for the H or unified counter. - This field is used only if the enableCounterUnify is set - to false */ - uint8_t prescale_l; /*!< Prescale value to produce the L or unified counter clock */ - uint8_t prescale_h; /*!< Prescale value to produce the H counter clock. - This field is used only if the enableCounterUnify is set - to false */ - uint8_t outInitState; /*!< Defines the initial output value */ -} sctimer_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the SCTimer clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the SCTimer driver. - * - * @param base SCTimer peripheral base address - * @param config Pointer to the user configuration structure. - * - * @return kStatus_Success indicates success; Else indicates failure. - */ -status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config); - -/*! - * @brief Gates the SCTimer clock. - * - * @param base SCTimer peripheral base address - */ -void SCTIMER_Deinit(SCT_Type *base); - -/*! - * @brief Fills in the SCTimer configuration structure with the default settings. - * - * The default values are: - * @code - * config->enableCounterUnify = true; - * config->clockMode = kSCTIMER_System_ClockMode; - * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - * config->enableBidirection_l = false; - * config->enableBidirection_h = false; - * config->prescale_l = 0; - * config->prescale_h = 0; - * config->outInitState = 0; - * @endcode - * @param config Pointer to the user configuration structure. - */ -void SCTIMER_GetDefaultConfig(sctimer_config_t *config); - -/*! @}*/ - -/*! - * @name PWM setup operations - * @{ - */ - -/*! - * @brief Configures the PWM signal parameters. - * - * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This - * function will create 2 events; one of the events will trigger on match with the pulse value - * and the other will trigger when the counter matches the PWM period. The PWM period event is - * also used as a limit event to reset the counter or change direction. Both events are enabled - * for the same state. The state number can be retrieved by calling the function - * SCTIMER_GetCurrentStateNumber(). - * The counter is set to operate as one 32-bit counter (unify bit is set to 1). - * The counter operates in bi-directional mode when generating a center-aligned PWM. - * - * @note When setting PWM output from multiple output pins, they all should use the same PWM mode - * i.e all PWM's should be either edge-aligned or center-aligned. - * When using this API, the PWM signal frequency of all the initialized channels must be the same. - * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the - * API's pwmFreq_Hz. - * - * @param base SCTimer peripheral base address - * @param pwmParams PWM parameters to configure the output - * @param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz SCTimer counter clock in Hz - * @param event Pointer to a variable where the PWM period event number is stored - * - * @return kStatus_Success on success - * kStatus_Fail If we have hit the limit in terms of number of events created or if - * an incorrect PWM dutycylce is passed in. - */ -status_t SCTIMER_SetupPwm(SCT_Type *base, - const sctimer_pwm_signal_param_t *pwmParams, - sctimer_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - uint32_t *event); - -/*! - * @brief Updates the duty cycle of an active PWM signal. - * - * @param base SCTimer peripheral base address - * @param output The output to configure - * @param dutyCyclePercent New PWM pulse width; the value should be between 1 to 100 - * @param event Event number associated with this PWM signal. This was returned to the user by the - * function SCTIMER_SetupPwm(). - */ -void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event); - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline void SCTIMER_EnableInterrupts(SCT_Type *base, uint32_t mask) -{ - base->EVEN |= mask; -} - -/*! - * @brief Disables the selected SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline void SCTIMER_DisableInterrupts(SCT_Type *base, uint32_t mask) -{ - base->EVEN &= ~mask; -} - -/*! - * @brief Gets the enabled SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline uint32_t SCTIMER_GetEnabledInterrupts(SCT_Type *base) -{ - return (base->EVEN & 0xFFFFU); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the SCTimer status flags. - * - * @param base SCTimer peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::sctimer_status_flags_t - */ -static inline uint32_t SCTIMER_GetStatusFlags(SCT_Type *base) -{ - uint32_t statusFlags = 0; - - /* Add the recorded events */ - statusFlags = (base->EVFLAG & 0xFFFFU); - - /* Add bus error flags */ - statusFlags |= (base->CONFLAG & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); - - return statusFlags; -} - -/*! - * @brief Clears the SCTimer status flags. - * - * @param base SCTimer peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::sctimer_status_flags_t - */ -static inline void SCTIMER_ClearStatusFlags(SCT_Type *base, uint32_t mask) -{ - /* Write to the flag registers */ - base->EVFLAG = (mask & 0xFFFFU); - base->CONFLAG = (mask & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); -} - -/*! @}*/ - -/*! - * @name Counter Start and Stop - * @{ - */ - -/*! - * @brief Starts the SCTimer counter. - * - * @param base SCTimer peripheral base address - * @param countertoStart SCTimer counter to start; if unify mode is set then function always - * writes to HALT_L bit - */ -static inline void SCTIMER_StartTimer(SCT_Type *base, sctimer_counter_t countertoStart) -{ - /* Clear HALT_L bit if counter is operating in 32-bit mode or user wants to start L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStart == kSCTIMER_Counter_L)) - { - base->CTRL &= ~(SCT_CTRL_HALT_L_MASK); - } - else - { - /* Start H counter */ - base->CTRL &= ~(SCT_CTRL_HALT_H_MASK); - } -} - -/*! - * @brief Halts the SCTimer counter. - * - * @param base SCTimer peripheral base address - * @param countertoStop SCTimer counter to stop; if unify mode is set then function always - * writes to HALT_L bit - */ -static inline void SCTIMER_StopTimer(SCT_Type *base, sctimer_counter_t countertoStop) -{ - /* Set HALT_L bit if counter is operating in 32-bit mode or user wants to stop L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStop == kSCTIMER_Counter_L)) - { - base->CTRL |= (SCT_CTRL_HALT_L_MASK); - } - else - { - /* Stop H counter */ - base->CTRL |= (SCT_CTRL_HALT_H_MASK); - } -} - -/*! @}*/ - -/*! - * @name Functions to create a new event and manage the state logic - * @{ - */ - -/*! - * @brief Create an event that is triggered on a match or IO and schedule in current state. - * - * This function will configure an event using the options provided by the user. If the event type uses - * the counter match, then the function will set the user provided match value into a match register - * and put this match register number into the event control register. - * The event is enabled for the current state and the event number is increased by one at the end. - * The function returns the event number; this event number can be used to configure actions to be - * done when this event is triggered. - * - * @param base SCTimer peripheral base address - * @param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t - * @param matchValue The match value that will be programmed to a match register - * @param whichIO The input or output that will be involved in event triggering. This field - * is ignored if the event type is "match only" - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as we have only 1 unified counter; hence ignored. - * @param event Pointer to a variable where the new event number is stored - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of events created or - if we have reached the limit in terms of number of match registers - */ -status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, - sctimer_event_t howToMonitor, - uint32_t matchValue, - uint32_t whichIO, - sctimer_counter_t whichCounter, - uint32_t *event); - -/*! - * @brief Enable an event in the current state. - * - * This function will allow the event passed in to trigger in the current state. The event must - * be created earlier by either calling the function SCTIMER_SetupPwm() or function - * SCTIMER_CreateAndScheduleEvent() . - * - * @param base SCTimer peripheral base address - * @param event Event number to enable in the current state - * - */ -void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event); - -/*! - * @brief Increase the state by 1 - * - * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new - * state. - * - * @param base SCTimer peripheral base address - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of states used - - */ -status_t SCTIMER_IncreaseState(SCT_Type *base); - -/*! - * @brief Provides the current state - * - * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). - * - * @param base SCTimer peripheral base address - * - * @return The current state - */ -uint32_t SCTIMER_GetCurrentState(SCT_Type *base); - -/*! @}*/ - -/*! - * @name Actions to take in response to an event - * @{ - */ - -/*! - * @brief Setup capture of the counter value on trigger of a selected event - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. - * @param captureRegister Pointer to a variable where the capture register number will be returned. User - * can read the captured value from this register when the specified event is triggered. - * @param event Event number that will trigger the capture - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of match/capture registers available - */ -status_t SCTIMER_SetupCaptureAction(SCT_Type *base, - sctimer_counter_t whichCounter, - uint32_t *captureRegister, - uint32_t event); - -/*! - * @brief Receive noticification when the event trigger an interrupt. - * - * If the interrupt for the event is enabled by the user, then a callback can be registered - * which will be invoked when the event is triggered - * - * @param base SCTimer peripheral base address - * @param event Event number that will trigger the interrupt - * @param callback Function to invoke when the event is triggered - */ - -void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event); - -/*! - * @brief Transition to the specified state. - * - * This transition will be triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param nextState The next state SCTimer will transition to - * @param event Event number that will trigger the state transition - */ -static inline void SCTIMER_SetupNextStateAction(SCT_Type *base, uint32_t nextState, uint32_t event) -{ - uint32_t reg = base->EVENT[event].CTRL; - - reg &= ~(SCT_EVENT_CTRL_STATEV_MASK); - /* Load the STATEV value when the event occurs to be the next state */ - reg |= SCT_EVENT_CTRL_STATEV(nextState) | SCT_EVENT_CTRL_STATELD_MASK; - - base->EVENT[event].CTRL = reg; -} - -/*! - * @brief Set the Output. - * - * This output will be set when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to set - * @param event Event number that will trigger the output change - */ -static inline void SCTIMER_SetupOutputSetAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - base->OUT[whichIO].SET |= (1U << event); -} - -/*! - * @brief Clear the Output. - * - * This output will be cleared when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to clear - * @param event Event number that will trigger the output change - */ -static inline void SCTIMER_SetupOutputClearAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - base->OUT[whichIO].CLR |= (1U << event); -} - -/*! - * @brief Toggle the output level. - * - * This change in the output level is triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to toggle - * @param event Event number that will trigger the output change - */ -void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event); - -/*! - * @brief Limit the running counter. - * - * The counter is limited when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. - * @param event Event number that will trigger the counter to be limited - */ -static inline void SCTIMER_SetupCounterLimitAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - base->LIMIT |= SCT_LIMIT_LIMMSK_L(1U << event); - } - else - { - base->LIMIT |= SCT_LIMIT_LIMMSK_H(1U << event); - } -} - -/*! - * @brief Stop the running counter. - * - * The counter is stopped when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. - * @param event Event number that will trigger the counter to be stopped - */ -static inline void SCTIMER_SetupCounterStopAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - base->STOP |= SCT_STOP_STOPMSK_L(1U << event); - } - else - { - base->STOP |= SCT_STOP_STOPMSK_H(1U << event); - } -} - -/*! - * @brief Re-start the stopped counter. - * - * The counter will re-start when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. - * @param event Event number that will trigger the counter to re-start - */ -static inline void SCTIMER_SetupCounterStartAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - base->START |= SCT_START_STARTMSK_L(1U << event); - } - else - { - base->START |= SCT_START_STARTMSK_H(1U << event); - } -} - -/*! - * @brief Halt the running counter. - * - * The counter is disabled (halted) when the event number that is passed in by the user is - * triggered. When the counter is halted, all further events are disabled. The HALT condition - * can only be removed by calling the SCTIMER_StartTimer() function. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. - * @param event Event number that will trigger the counter to be halted - */ -static inline void SCTIMER_SetupCounterHaltAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - base->HALT |= SCT_HALT_HALTMSK_L(1U << event); - } - else - { - base->HALT |= SCT_HALT_HALTMSK_H(1U << event); - } -} - -/*! - * @brief Generate a DMA request. - * - * DMA request will be triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param dmaNumber The DMA request to generate - * @param event Event number that will trigger the DMA request - */ -static inline void SCTIMER_SetupDmaTriggerAction(SCT_Type *base, uint32_t dmaNumber, uint32_t event) -{ - if (dmaNumber == 0) - { - base->DMA0REQUEST |= (1U << event); - } - else - { - base->DMA1REQUEST |= (1U << event); - } -} - -/*! - * @brief SCTimer interrupt handler. - * - * @param base SCTimer peripheral base address. - */ -void SCTIMER_EventHandleIRQ(SCT_Type *base); - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_SCTIMER_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_sdif.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_sdif.c deleted file mode 100644 index 7b3ef75b735..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_sdif.c +++ /dev/null @@ -1,1303 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_sdif.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Typedef for interrupt handler. */ -typedef void (*sdif_isr_t)(SDIF_Type *base, sdif_handle_t *handle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get the instance. - * - * @param base SDIF peripheral base address. - * @return Instance number. - */ -static uint32_t SDIF_GetInstance(SDIF_Type *base); - -/* -* @brief config the SDIF interface before transfer between the card and host -* @param SDIF base address -* @param transfer config structure -*/ -static status_t SDIF_TransferConfig(SDIF_Type *base, sdif_transfer_t *transfer); - -/* -* @brief wait the command done function and check error status -* @param SDIF base address -* @param command config structure -*/ -static status_t SDIF_WaitCommandDone(SDIF_Type *base, sdif_command_t *command); - -/* -* @brief transfer data in a blocking way -* @param SDIF base address -* @param data config structure -* @param indicate current transfer mode:DMA or polling -*/ -static status_t SDIF_TransferDataBlocking(SDIF_Type *base, sdif_data_t *data, bool isDMA); - -/* -* @brief read the command response -* @param SDIF base address -* @param sdif command pointer -*/ -static status_t SDIF_ReadCommandResponse(SDIF_Type *base, sdif_command_t *command); - -/* -* @brief handle transfer command interrupt -* @param SDIF base address -* @param sdif handle -* @param interrupt mask flags -*/ -static void SDIF_TransferHandleCommand(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags); - -/* -* @brief handle transfer data interrupt -* @param SDIF base address -* @param sdif handle -* @param interrupt mask flags -*/ -static void SDIF_TransferHandleData(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags); - -/* -* @brief handle DMA transfer -* @param SDIF base address -* @param sdif handle -* @param interrupt mask flag -*/ -static void SDIF_TransferHandleDMA(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags); - -/* -* @brief driver IRQ handler -* @param SDIF base address -* @param sdif handle -*/ -static void SDIF_TransferHandleIRQ(SDIF_Type *base, sdif_handle_t *handle); - -/* -* @brief read data port -* @param SDIF base address -* @param sdif data -* @param the number of data been transferred -*/ -static uint32_t SDIF_ReadDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords); - -/* -* @brief write data port -* @param SDIF base address -* @param sdif data -* @param the number of data been transferred -*/ -static uint32_t SDIF_WriteDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords); - -/* -* @brief read data by blocking way -* @param SDIF base address -* @param sdif data -*/ -static status_t SDIF_ReadDataPortBlocking(SDIF_Type *base, sdif_data_t *data); - -/* -* @brief write data by blocking way -* @param SDIF base address -* @param sdif data -*/ -static status_t SDIF_WriteDataPortBlocking(SDIF_Type *base, sdif_data_t *data); - -/* -* @brief handle sdio interrupt -* This function will call the SDIO interrupt callback -* @param SDIF handle -*/ -static void SDIF_TransferHandleSDIOInterrupt(sdif_handle_t *handle); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief SDIF internal handle pointer array */ -static sdif_handle_t *s_sdifHandle[FSL_FEATURE_SOC_SDIF_COUNT]; - -/*! @brief SDIF base pointer array */ -static SDIF_Type *const s_sdifBase[] = SDIF_BASE_PTRS; - -/*! @brief SDIF IRQ name array */ -static const IRQn_Type s_sdifIRQ[] = SDIF_IRQS; - -/* SDIF ISR for transactional APIs. */ -static sdif_isr_t s_sdifIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t SDIF_GetInstance(SDIF_Type *base) -{ - uint8_t instance = 0U; - - while ((instance < ARRAY_SIZE(s_sdifBase)) && (s_sdifBase[instance] != base)) - { - instance++; - } - - assert(instance < ARRAY_SIZE(s_sdifBase)); - - return instance; -} - -static status_t SDIF_TransferConfig(SDIF_Type *base, sdif_transfer_t *transfer) -{ - sdif_command_t *command = transfer->command; - sdif_data_t *data = transfer->data; - - if ((command == NULL) || (data && (data->blockSize > SDIF_BLKSIZ_BLOCK_SIZE_MASK))) - { - return kStatue_SDIF_InvalidArgument; - } - - if (data != NULL) - { - /* config the block size register ,the block size maybe smaller than FIFO - depth, will test on the board */ - base->BLKSIZ = SDIF_BLKSIZ_BLOCK_SIZE(data->blockSize); - /* config the byte count register */ - base->BYTCNT = SDIF_BYTCNT_BYTE_COUNT(data->blockSize * data->blockCount); - - command->flags |= kSDIF_DataExpect; /* need transfer data flag */ - - if (data->txData != NULL) - { - command->flags |= kSDIF_DataWriteToCard; /* data transfer direction */ - } - else - { - /* config the card read threshold,enable the card read threshold */ - if (data->blockSize <= (SDIF_FIFO_COUNT * sizeof(uint32_t))) - { - base->CARDTHRCTL = SDIF_CARDTHRCTL_CARDRDTHREN_MASK | SDIF_CARDTHRCTL_CARDTHRESHOLD(data->blockSize); - } - else - { - base->CARDTHRCTL &= ~SDIF_CARDTHRCTL_CARDRDTHREN_MASK; - } - } - - if (data->streamTransfer) - { - command->flags |= kSDIF_DataStreamTransfer; /* indicate if use stream transfer or block transfer */ - } - - if ((data->enableAutoCommand12) && - (data->blockCount > 1U)) /* indicate if auto stop will send after the data transfer done */ - { - command->flags |= kSDIF_DataTransferAutoStop; - } - } - /* R2 response length long */ - if (command->responseType == kCARD_ResponseTypeR2) - { - command->flags |= (kSDIF_CmdCheckResponseCRC | kSDIF_CmdResponseLengthLong | kSDIF_CmdResponseExpect); - } - else if ((command->responseType == kCARD_ResponseTypeR3) || (command->responseType == kCARD_ResponseTypeR4)) - { - command->flags |= kSDIF_CmdResponseExpect; /* response R3 do not check Response CRC */ - } - else - { - if (command->responseType != kCARD_ResponseTypeNone) - { - command->flags |= (kSDIF_CmdCheckResponseCRC | kSDIF_CmdResponseExpect); - } - } - - if (command->type == kCARD_CommandTypeAbort) - { - command->flags |= kSDIF_TransferStopAbort; - } - - /* wait pre-transfer complete */ - command->flags |= kSDIF_WaitPreTransferComplete | kSDIF_CmdDataUseHoldReg; - - return kStatus_Success; -} - -static status_t SDIF_ReadCommandResponse(SDIF_Type *base, sdif_command_t *command) -{ - /* check if command exsit,if not, do not read the response */ - if (NULL != command) - { - /* read reponse */ - command->response[0U] = base->RESP[0U]; - if (command->responseType == kCARD_ResponseTypeR2) - { - command->response[1U] = base->RESP[1U]; - command->response[2U] = base->RESP[2U]; - command->response[3U] = base->RESP[3U]; - } - - if ((command->responseErrorFlags != 0U) && - ((command->responseType == kCARD_ResponseTypeR1) || (command->responseType == kCARD_ResponseTypeR1b) || - (command->responseType == kCARD_ResponseTypeR6) || (command->responseType == kCARD_ResponseTypeR5))) - { - if (((command->responseErrorFlags) & (command->response[0U])) != 0U) - { - return kStatus_SDIF_ResponseError; - } - } - } - - return kStatus_Success; -} - -static status_t SDIF_WaitCommandDone(SDIF_Type *base, sdif_command_t *command) -{ - uint32_t status = 0U; - - do - { - status = SDIF_GetInterruptStatus(base); - if ((status & - (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout | kSDIF_HardwareLockError)) != 0u) - { - SDIF_ClearInterruptStatus(base, status & (kSDIF_ResponseError | kSDIF_ResponseCRCError | - kSDIF_ResponseTimeout | kSDIF_HardwareLockError)); - return kStatus_SDIF_SendCmdFail; - } - } while ((status & kSDIF_CommandDone) != kSDIF_CommandDone); - - /* clear the command done bit */ - SDIF_ClearInterruptStatus(base, status & kSDIF_CommandDone); - - return SDIF_ReadCommandResponse(base, command); -} - -status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig) -{ - assert(NULL != dmaConfig); - assert(NULL != dmaConfig->dmaDesBufferStartAddr); - - sdif_dma_descriptor_t *dmaDesAddr; - uint32_t *tempDMADesBuffer = dmaConfig->dmaDesBufferStartAddr; - uint32_t dmaDesBufferSize = 0U; - - dmaDesAddr = (sdif_dma_descriptor_t *)tempDMADesBuffer; - - /* chain descriptor mode */ - if (dmaConfig->mode == kSDIF_ChainDMAMode) - { - while (((dmaDesAddr->dmaDesAttribute & kSDIF_DMADescriptorDataBufferEnd) != kSDIF_DMADescriptorDataBufferEnd) && - (dmaDesBufferSize < dmaConfig->dmaDesBufferLen * sizeof(uint32_t))) - { - /* set the OWN bit */ - dmaDesAddr->dmaDesAttribute |= kSDIF_DMADescriptorOwnByDMA; - dmaDesAddr++; - dmaDesBufferSize += sizeof(sdif_dma_descriptor_t); - } - /* if access dma des address overflow, return fail */ - if (dmaDesBufferSize > dmaConfig->dmaDesBufferLen * sizeof(uint32_t)) - { - return kStatus_Fail; - } - dmaDesAddr->dmaDesAttribute |= kSDIF_DMADescriptorOwnByDMA; - } - /* dual descriptor mode */ - else - { - while (((dmaDesAddr->dmaDesAttribute & kSDIF_DMADescriptorEnd) != kSDIF_DMADescriptorEnd) && - (dmaDesBufferSize < dmaConfig->dmaDesBufferLen * sizeof(uint32_t))) - { - dmaDesAddr = (sdif_dma_descriptor_t *)tempDMADesBuffer; - dmaDesAddr->dmaDesAttribute |= kSDIF_DMADescriptorOwnByDMA; - tempDMADesBuffer += dmaConfig->dmaDesSkipLen; - } - /* if access dma des address overflow, return fail */ - if (dmaDesBufferSize > dmaConfig->dmaDesBufferLen * sizeof(uint32_t)) - { - return kStatus_Fail; - } - dmaDesAddr->dmaDesAttribute |= kSDIF_DMADescriptorOwnByDMA; - } - /* reload DMA descriptor */ - base->PLDMND = SDIF_POLL_DEMAND_VALUE; - - return kStatus_Success; -} - -static uint32_t SDIF_ReadDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords) -{ - uint32_t i; - uint32_t totalWords; - uint32_t wordsCanBeRead; /* The words can be read at this time. */ - uint32_t readWatermark = ((base->FIFOTH & SDIF_FIFOTH_RX_WMARK_MASK) >> SDIF_FIFOTH_RX_WMARK_SHIFT); - - if (data->blockSize % sizeof(uint32_t) != 0U) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */ - if (readWatermark >= totalWords) - { - wordsCanBeRead = totalWords; - } - /* If watermark level is less than totalWords and left words to be sent is equal or bigger than readWatermark, - transfers watermark level words. */ - else if ((readWatermark < totalWords) && ((totalWords - transferredWords) >= readWatermark)) - { - wordsCanBeRead = readWatermark; - } - /* If watermark level is less than totalWords and left words to be sent is less than readWatermark, transfers left - words. */ - else - { - wordsCanBeRead = (totalWords - transferredWords); - } - - i = 0U; - while (i < wordsCanBeRead) - { - data->rxData[transferredWords++] = base->FIFO[i]; - i++; - } - - return transferredWords; -} - -static uint32_t SDIF_WriteDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords) -{ - uint32_t i; - uint32_t totalWords; - uint32_t wordsCanBeWrite; /* The words can be read at this time. */ - uint32_t writeWatermark = ((base->FIFOTH & SDIF_FIFOTH_TX_WMARK_MASK) >> SDIF_FIFOTH_TX_WMARK_SHIFT); - - if (data->blockSize % sizeof(uint32_t) != 0U) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */ - if (writeWatermark >= totalWords) - { - wordsCanBeWrite = totalWords; - } - /* If watermark level is less than totalWords and left words to be sent is equal or bigger than writeWatermark, - transfers watermark level words. */ - else if ((writeWatermark < totalWords) && ((totalWords - transferredWords) >= writeWatermark)) - { - wordsCanBeWrite = writeWatermark; - } - /* If watermark level is less than totalWords and left words to be sent is less than writeWatermark, transfers left - words. */ - else - { - wordsCanBeWrite = (totalWords - transferredWords); - } - - i = 0U; - while (i < wordsCanBeWrite) - { - base->FIFO[i] = data->txData[transferredWords++]; - i++; - } - - return transferredWords; -} - -static status_t SDIF_ReadDataPortBlocking(SDIF_Type *base, sdif_data_t *data) -{ - uint32_t totalWords; - uint32_t transferredWords = 0U; - status_t error = kStatus_Success; - uint32_t status; - bool transferOver = false; - - if (data->blockSize % sizeof(uint32_t) != 0U) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - while ((transferredWords < totalWords) && (error == kStatus_Success)) - { - /* wait data transfer complete or reach RX watermark */ - do - { - status = SDIF_GetInterruptStatus(base); - if (status & kSDIF_DataTransferError) - { - if (!(data->enableIgnoreError)) - { - error = kStatus_Fail; - } - } - } while (((status & (kSDIF_DataTransferOver | kSDIF_ReadFIFORequest)) == 0U) && (!transferOver)); - - if ((status & kSDIF_DataTransferOver) == kSDIF_DataTransferOver) - { - transferOver = true; - } - - if (error == kStatus_Success) - { - transferredWords = SDIF_ReadDataPort(base, data, transferredWords); - } - - /* clear interrupt status */ - SDIF_ClearInterruptStatus(base, status); - } - - return error; -} - -static status_t SDIF_WriteDataPortBlocking(SDIF_Type *base, sdif_data_t *data) -{ - uint32_t totalWords; - uint32_t transferredWords = 0U; - status_t error = kStatus_Success; - uint32_t status; - - if (data->blockSize % sizeof(uint32_t) != 0U) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - while ((transferredWords < totalWords) && (error == kStatus_Success)) - { - /* wait data transfer complete or reach RX watermark */ - do - { - status = SDIF_GetInterruptStatus(base); - if (status & kSDIF_DataTransferError) - { - if (!(data->enableIgnoreError)) - { - error = kStatus_Fail; - } - } - } while ((status & kSDIF_WriteFIFORequest) == 0U); - - if (error == kStatus_Success) - { - transferredWords = SDIF_WriteDataPort(base, data, transferredWords); - } - - /* clear interrupt status */ - SDIF_ClearInterruptStatus(base, status); - } - - while ((SDIF_GetInterruptStatus(base) & kSDIF_DataTransferOver) != kSDIF_DataTransferOver) - { - } - - if (SDIF_GetInterruptStatus(base) & kSDIF_DataTransferError) - { - if (!(data->enableIgnoreError)) - { - error = kStatus_Fail; - } - } - SDIF_ClearInterruptStatus(base, (kSDIF_DataTransferOver | kSDIF_DataTransferError)); - - return error; -} - -bool SDIF_Reset(SDIF_Type *base, uint32_t mask, uint32_t timeout) -{ - base->CTRL |= mask; - - /* check software DMA reset here for DMA reset also need to check this bit */ - while ((base->CTRL & mask) != 0U) - { - if (!timeout) - { - break; - } - timeout--; - } - - return timeout ? true : false; -} - -static status_t SDIF_TransferDataBlocking(SDIF_Type *base, sdif_data_t *data, bool isDMA) -{ - assert(NULL != data); - - uint32_t dmaStatus = 0U; - status_t error = kStatus_Success; - - /* in DMA mode, only need to wait the complete flag and check error */ - if (isDMA) - { - do - { - dmaStatus = SDIF_GetInternalDMAStatus(base); - if ((dmaStatus & kSDIF_DMAFatalBusError) == kSDIF_DMAFatalBusError) - { - SDIF_ClearInternalDMAStatus(base, kSDIF_DMAFatalBusError | kSDIF_AbnormalInterruptSummary); - error = kStatus_SDIF_DMATransferFailWithFBE; /* in this condition,need reset */ - } - /* Card error summary, include EBE,SBE,Data CRC,RTO,DRTO,Response error */ - if ((dmaStatus & kSDIF_DMACardErrorSummary) == kSDIF_DMACardErrorSummary) - { - SDIF_ClearInternalDMAStatus(base, kSDIF_DMACardErrorSummary | kSDIF_AbnormalInterruptSummary); - if (!(data->enableIgnoreError)) - { - error = kStatus_SDIF_DataTransferFail; - } - - /* if error occur, then return */ - break; - } - } while ((dmaStatus & (kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor)) == 0U); - - /* clear the corresponding status bit */ - SDIF_ClearInternalDMAStatus(base, (kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor | - kSDIF_NormalInterruptSummary)); - - SDIF_ClearInterruptStatus(base, SDIF_GetInterruptStatus(base)); - } - else - { - if (data->rxData != NULL) - { - error = SDIF_ReadDataPortBlocking(base, data); - } - else - { - error = SDIF_WriteDataPortBlocking(base, data); - } - } - - return error; -} - -status_t SDIF_SendCommand(SDIF_Type *base, sdif_command_t *cmd, uint32_t timeout) -{ - assert(NULL != cmd); - - base->CMDARG = cmd->argument; - base->CMD = SDIF_CMD_CMD_INDEX(cmd->index) | SDIF_CMD_START_CMD_MASK | (cmd->flags & (~SDIF_CMD_CMD_INDEX_MASK)); - - /* wait start_cmd bit auto clear within timeout */ - while ((base->CMD & SDIF_CMD_START_CMD_MASK) == SDIF_CMD_START_CMD_MASK) - { - if (!timeout) - { - break; - } - - --timeout; - } - - return timeout ? kStatus_Success : kStatus_Fail; -} - -bool SDIF_SendCardActive(SDIF_Type *base, uint32_t timeout) -{ - bool enINT = false; - sdif_command_t command; - - memset(&command, 0U, sizeof(sdif_command_t)); - - /* add for confict with interrupt mode,close the interrupt temporary */ - if ((base->CTRL & SDIF_CTRL_INT_ENABLE_MASK) == SDIF_CTRL_INT_ENABLE_MASK) - { - enINT = true; - base->CTRL &= ~SDIF_CTRL_INT_ENABLE_MASK; - } - - command.flags = SDIF_CMD_SEND_INITIALIZATION_MASK; - - if (SDIF_SendCommand(base, &command, timeout) == kStatus_Fail) - { - return false; - } - - /* wait command done */ - while ((SDIF_GetInterruptStatus(base) & kSDIF_CommandDone) != kSDIF_CommandDone) - { - } - - /* clear status */ - SDIF_ClearInterruptStatus(base, kSDIF_CommandDone); - - /* add for confict with interrupt mode */ - if (enINT) - { - base->CTRL |= SDIF_CTRL_INT_ENABLE_MASK; - } - - return true; -} - -void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider) -{ - /*config the clock delay and pharse shift - *should config the clk_in_drv, - *clk_in_sample to meet the min hold and - *setup time - */ - if (target_HZ <= kSDIF_Freq400KHZ) - { - /*min hold time:5ns - * min setup time: 5ns - * delay = (x+1)*250ps - */ - SYSCON->SDIOCLKCTRL = SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_INDENTIFICATION_MODE_SAMPLE_DELAY) | - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_INDENTIFICATION_MODE_DRV_DELAY); - } - else if (target_HZ >= kSDIF_Freq50MHZ) - { - /* - * user need to pay attention to this parameter - * can be change the setting for you card and board - * min hold time:2ns - * min setup time: 6ns - * delay = (x+1)*250ps - */ - SYSCON->SDIOCLKCTRL = SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_HIGHSPEED_50MHZ_SAMPLE_DELAY) | - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_HIGHSPEED_50MHZ_DRV_DELAY); - /* means the input clock = 2 * card clock, - * can use clock pharse shift tech - */ - if (divider == 1U) - { - SYSCON->SDIOCLKCTRL |= SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(kSDIF_ClcokPharseShift90) | - SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(kSDIF_ClcokPharseShift180); - } - } - else - { - /* - * user need to pay attention to this parameter - * can be change the setting for you card and board - * min hold time:5ns - * min setup time: 5ns - * delay = (x+1)*250ps - */ - SYSCON->SDIOCLKCTRL = SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_HIGHSPEED_25MHZ_SAMPLE_DELAY) | - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_HIGHSPEED_25MHZ_DRV_DELAY); - /* means the input clock = 2 * card clock, - * can use clock pharse shift tech - */ - if (divider == 1U) - { - SYSCON->SDIOCLKCTRL |= SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(kSDIF_ClcokPharseShift90) | - SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(kSDIF_ClcokPharseShift90); - } - } -} - -uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t target_HZ) -{ - assert(srcClock_Hz <= FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK); - - sdif_command_t cmd = {0U}; - uint32_t divider = 0U, targetFreq = target_HZ; - - /* if target freq bigger than the source clk, set the target_HZ to - src clk, this interface can run up to 52MHZ with card */ - if (srcClock_Hz < targetFreq) - { - targetFreq = srcClock_Hz; - } - - /* disable the clock first,need sync to CIU*/ - SDIF_EnableCardClock(base, false); - - /* update the clock register and wait the pre-transfer complete */ - cmd.flags = kSDIF_CmdUpdateClockRegisterOnly | kSDIF_WaitPreTransferComplete; - SDIF_SendCommand(base, &cmd, SDIF_TIMEOUT_VALUE); - - /*calucate the divider*/ - if (targetFreq != srcClock_Hz) - { - divider = (srcClock_Hz / targetFreq + 1U) / 2U; - } - /* load the clock divider */ - base->CLKDIV = SDIF_CLKDIV_CLK_DIVIDER0(divider); - - /* update the divider to CIU */ - cmd.flags = kSDIF_CmdUpdateClockRegisterOnly | kSDIF_WaitPreTransferComplete; - SDIF_SendCommand(base, &cmd, SDIF_TIMEOUT_VALUE); - - /* enable the card clock and sync to CIU */ - SDIF_EnableCardClock(base, true); - SDIF_SendCommand(base, &cmd, SDIF_TIMEOUT_VALUE); - - /* config the clock delay to meet the hold time and setup time */ - SDIF_ConfigClockDelay(target_HZ, divider); - - /* return the actual card clock freq */ - - return (divider != 0U) ? (srcClock_Hz / (divider * 2U)) : srcClock_Hz; -} - -bool SDIF_AbortReadData(SDIF_Type *base, uint32_t timeout) -{ - /* assert this bit to reset the data machine to abort the read data */ - base->CTRL |= SDIF_CTRL_ABORT_READ_DATA_MASK; - /* polling the bit self clear */ - while ((base->CTRL & SDIF_CTRL_ABORT_READ_DATA_MASK) == SDIF_CTRL_ABORT_READ_DATA_MASK) - { - if (!timeout) - { - break; - } - timeout--; - } - - return base->CTRL & SDIF_CTRL_ABORT_READ_DATA_MASK ? false : true; -} - -status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, const uint32_t *data, uint32_t dataSize) -{ - assert(NULL != config); - assert(NULL != data); - - uint32_t dmaEntry = 0U, i, dmaBufferSize = 0U, dmaBuffer1Size = 0U; - uint32_t *tempDMADesBuffer = config->dmaDesBufferStartAddr; - const uint32_t *dataBuffer = data; - sdif_dma_descriptor_t *descriptorPoniter = NULL; - uint32_t maxDMABuffer = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE * (config->mode); - - /* check the dma descriptor buffer length , it is user's responsibility to make sure the DMA descriptor table - size is bigger enough to hold the transfer descriptor */ - if (config->dmaDesBufferLen * sizeof(uint32_t) < sizeof(sdif_dma_descriptor_t)) - { - return kStatus_SDIF_DescriptorBufferLenError; - } - - /* check the read/write data size,must be a multiple of 4 */ - if (dataSize % sizeof(uint32_t) != 0U) - { - dataSize += sizeof(uint32_t) - (dataSize % sizeof(uint32_t)); - } - - /*config the bus mode*/ - if (config->enableFixBurstLen) - { - base->BMOD |= SDIF_BMOD_FB_MASK; - } - - /* calucate the dma descriptor entry due to DMA buffer size limit */ - /* if datasize smaller than one descriptor buffer size */ - if (dataSize > maxDMABuffer) - { - dmaEntry = dataSize / maxDMABuffer + (dataSize % maxDMABuffer ? 1U : 0U); - } - else /* need one dma descriptor */ - { - dmaEntry = 1U; - } - - /* check the DMA descriptor buffer len one more time,it is user's responsibility to make sure the DMA descriptor - table - size is bigger enough to hold the transfer descriptor */ - if (config->dmaDesBufferLen * sizeof(uint32_t) < (dmaEntry * sizeof(sdif_dma_descriptor_t) + config->dmaDesSkipLen)) - { - return kStatus_SDIF_DescriptorBufferLenError; - } - - switch (config->mode) - { - case kSDIF_DualDMAMode: - base->BMOD |= SDIF_BMOD_DSL(config->dmaDesSkipLen); /* config the distance between the DMA descriptor */ - for (i = 0U; i < dmaEntry; i++) - { - if (dataSize > FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE) - { - dmaBufferSize = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE; - dataSize -= dmaBufferSize; - dmaBuffer1Size = dataSize > FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE ? - FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE : - dataSize; - dataSize -= dmaBuffer1Size; - } - else - { - dmaBufferSize = dataSize; - dmaBuffer1Size = 0U; - } - - descriptorPoniter = (sdif_dma_descriptor_t *)tempDMADesBuffer; - if (i == 0U) - { - descriptorPoniter->dmaDesAttribute = kSDIF_DMADescriptorDataBufferStart; - } - descriptorPoniter->dmaDesAttribute |= kSDIF_DMADescriptorOwnByDMA | kSDIF_DisableCompleteInterrupt; - descriptorPoniter->dmaDataBufferSize = - SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(dmaBufferSize) | SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(dmaBuffer1Size); - - descriptorPoniter->dmaDataBufferAddr0 = dataBuffer; - descriptorPoniter->dmaDataBufferAddr1 = dataBuffer + dmaBufferSize / sizeof(uint32_t); - dataBuffer += (dmaBufferSize + dmaBuffer1Size) / sizeof(uint32_t); - - /* descriptor skip length */ - tempDMADesBuffer += config->dmaDesSkipLen + sizeof(sdif_dma_descriptor_t) / sizeof(uint32_t); - } - /* enable the completion interrupt when reach the last descriptor */ - descriptorPoniter->dmaDesAttribute &= ~kSDIF_DisableCompleteInterrupt; - descriptorPoniter->dmaDesAttribute |= kSDIF_DMADescriptorDataBufferEnd | kSDIF_DMADescriptorEnd; - break; - - case kSDIF_ChainDMAMode: - for (i = 0U; i < dmaEntry; i++) - { - if (dataSize > FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE) - { - dmaBufferSize = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE; - dataSize -= FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE; - } - else - { - dmaBufferSize = dataSize; - } - - descriptorPoniter = (sdif_dma_descriptor_t *)tempDMADesBuffer; - if (i == 0U) - { - descriptorPoniter->dmaDesAttribute = kSDIF_DMADescriptorDataBufferStart; - } - descriptorPoniter->dmaDesAttribute |= - kSDIF_DMADescriptorOwnByDMA | kSDIF_DMASecondAddrChained | kSDIF_DisableCompleteInterrupt; - descriptorPoniter->dmaDataBufferSize = - SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(dmaBufferSize); /* use only buffer 1 for data buffer*/ - descriptorPoniter->dmaDataBufferAddr0 = dataBuffer; - dataBuffer += dmaBufferSize / sizeof(uint32_t); - tempDMADesBuffer += - sizeof(sdif_dma_descriptor_t) / sizeof(uint32_t); /* calucate the next descriptor address */ - /* this descriptor buffer2 pointer to the next descriptor address */ - descriptorPoniter->dmaDataBufferAddr1 = tempDMADesBuffer; - } - /* enable the completion interrupt when reach the last descriptor */ - descriptorPoniter->dmaDesAttribute &= ~kSDIF_DisableCompleteInterrupt; - descriptorPoniter->dmaDesAttribute |= kSDIF_DMADescriptorDataBufferEnd; - break; - - default: - break; - } - - /* use internal DMA interface */ - base->CTRL |= SDIF_CTRL_USE_INTERNAL_DMAC_MASK; - /* enable the internal SD/MMC DMA */ - base->BMOD |= SDIF_BMOD_DE_MASK; - /* enable DMA status check */ - base->IDINTEN |= kSDIF_DMAAllStatus; - /* clear write/read FIFO request interrupt in DMA mode, DMA will handle the data transfer*/ - SDIF_DisableInterrupt(base, kSDIF_WriteFIFORequest | kSDIF_ReadFIFORequest | kSDIF_DataTransferOver); - /* load DMA descriptor buffer address */ - base->DBADDR = (uint32_t)config->dmaDesBufferStartAddr; - - return kStatus_Success; -} - -void SDIF_Init(SDIF_Type *base, sdif_config_t *config) -{ - assert(NULL != config); - - uint32_t timeout; - - /* enable SDIF clock */ - CLOCK_EnableClock(kCLOCK_Sdio); - - /* do software reset */ - base->BMOD |= SDIF_BMOD_SWR_MASK; - - /* reset all */ - SDIF_Reset(base, kSDIF_ResetAll, SDIF_TIMEOUT_VALUE); - - /*config timeout register */ - timeout = base->TMOUT; - timeout &= ~(SDIF_TMOUT_RESPONSE_TIMEOUT_MASK | SDIF_TMOUT_DATA_TIMEOUT_MASK); - timeout |= SDIF_TMOUT_RESPONSE_TIMEOUT(config->responseTimeout) | SDIF_TMOUT_DATA_TIMEOUT(config->dataTimeout); - - base->TMOUT = timeout; - - /* config the card detect debounce clock count */ - base->DEBNCE = SDIF_DEBNCE_DEBOUNCE_COUNT(config->cardDetDebounce_Clock); - - /*config the watermark/burst transfer value */ - base->FIFOTH = - SDIF_FIFOTH_TX_WMARK(SDIF_TX_WATERMARK) | SDIF_FIFOTH_RX_WMARK(SDIF_RX_WATERMARK) | SDIF_FIFOTH_DMA_MTS(1U); - - /* enable the interrupt status */ - SDIF_EnableInterrupt(base, kSDIF_AllInterruptStatus); - - /* clear all interrupt/DMA status */ - SDIF_ClearInterruptStatus(base, kSDIF_AllInterruptStatus); - SDIF_ClearInternalDMAStatus(base, kSDIF_DMAAllStatus); -} - -status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sdif_transfer_t *transfer) -{ - assert(NULL != transfer); - - bool isDMA = false; - sdif_data_t *data = transfer->data; - - /* config the transfer parameter */ - if (SDIF_TransferConfig(base, transfer) != kStatus_Success) - { - return kStatue_SDIF_InvalidArgument; - } - - /* if need transfer data in dma mode, config the DMA descriptor first */ - if ((data != NULL) && (dmaConfig != NULL)) - { - /* use internal DMA mode to transfer between the card and host*/ - isDMA = true; - - if (SDIF_InternalDMAConfig(base, dmaConfig, data->rxData ? data->rxData : data->txData, - data->blockSize * data->blockCount) != kStatus_Success) - { - return kStatus_SDIF_DescriptorBufferLenError; - } - } - - /* send command first */ - if (SDIF_SendCommand(base, transfer->command, SDIF_TIMEOUT_VALUE) != kStatus_Success) - { - return kStatus_SDIF_SyncCmdTimeout; - } - - /* wait the command transfer done and check if error occurs */ - if (SDIF_WaitCommandDone(base, transfer->command) != kStatus_Success) - { - return kStatus_SDIF_SendCmdFail; - } - - /* if use DMA transfer mode ,check the corresponding status bit */ - if (data != NULL) - { - /* check the if has DMA descriptor featch error */ - if (isDMA && - ((SDIF_GetInternalDMAStatus(base) & kSDIF_DMADescriptorUnavailable) == kSDIF_DMADescriptorUnavailable)) - { - SDIF_ClearInternalDMAStatus(base, kSDIF_DMADescriptorUnavailable | kSDIF_AbnormalInterruptSummary); - - /* release the DMA descriptor to DMA */ - SDIF_ReleaseDMADescriptor(base, dmaConfig); - } - /* handle data transfer */ - if (SDIF_TransferDataBlocking(base, data, isDMA) != kStatus_Success) - { - return kStatus_SDIF_DataTransferFail; - } - } - - return kStatus_Success; -} - -status_t SDIF_TransferNonBlocking(SDIF_Type *base, - sdif_handle_t *handle, - sdif_dma_config_t *dmaConfig, - sdif_transfer_t *transfer) -{ - assert(NULL != transfer); - - sdif_data_t *data = transfer->data; - - /* save the data and command before transfer */ - handle->data = transfer->data; - handle->command = transfer->command; - handle->transferredWords = 0U; - handle->interruptFlags = 0U; - handle->dmaInterruptFlags = 0U; - - /* config the transfer parameter */ - if (SDIF_TransferConfig(base, transfer) != kStatus_Success) - { - return kStatue_SDIF_InvalidArgument; - } - - if ((data != NULL) && (dmaConfig != NULL)) - { - /* use internal DMA mode to transfer between the card and host*/ - if (SDIF_InternalDMAConfig(base, dmaConfig, data->rxData ? data->rxData : data->txData, - data->blockSize * data->blockCount) != kStatus_Success) - { - return kStatus_SDIF_DescriptorBufferLenError; - } - } - - /* send command first */ - if (SDIF_SendCommand(base, transfer->command, SDIF_TIMEOUT_VALUE) != kStatus_Success) - { - return kStatus_SDIF_SyncCmdTimeout; - } - - return kStatus_Success; -} - -void SDIF_TransferCreateHandle(SDIF_Type *base, - sdif_handle_t *handle, - sdif_transfer_callback_t *callback, - void *userData) -{ - assert(handle); - assert(callback); - - /* reset the handle. */ - memset(handle, 0U, sizeof(*handle)); - - /* Set the callback. */ - handle->callback.SDIOInterrupt = callback->SDIOInterrupt; - handle->callback.DMADesUnavailable = callback->DMADesUnavailable; - handle->callback.CommandReload = callback->CommandReload; - handle->callback.TransferComplete = callback->TransferComplete; - - handle->userData = userData; - - /* Save the handle in global variables to support the double weak mechanism. */ - s_sdifHandle[SDIF_GetInstance(base)] = handle; - - /* save IRQ handler */ - s_sdifIsr = SDIF_TransferHandleIRQ; - - /* enable the global interrupt */ - SDIF_EnableGlobalInterrupt(base, true); - - EnableIRQ(s_sdifIRQ[SDIF_GetInstance(base)]); -} - -void SDIF_GetCapability(SDIF_Type *base, sdif_capability_t *capability) -{ - assert(NULL != capability); - - capability->sdVersion = SDIF_SUPPORT_SD_VERSION; - capability->mmcVersion = SDIF_SUPPORT_MMC_VERSION; - capability->maxBlockLength = SDIF_BLKSIZ_BLOCK_SIZE_MASK; - /* set the max block count = max byte conut / max block size */ - capability->maxBlockCount = SDIF_BYTCNT_BYTE_COUNT_MASK / SDIF_BLKSIZ_BLOCK_SIZE_MASK; - capability->flags = kSDIF_SupportHighSpeedFlag | kSDIF_SupportDmaFlag | kSDIF_SupportSuspendResumeFlag | - kSDIF_SupportV330Flag | kSDIF_Support4BitFlag | kSDIF_Support8BitFlag; -} - -static void SDIF_TransferHandleCommand(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags) -{ - assert(handle->command); - - /* transfer error */ - if (interruptFlags & (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout)) - { - handle->callback.TransferComplete(base, handle, kStatus_SDIF_SendCmdFail, handle->userData); - } - /* cmd buffer full, in this condition user need re-send the command */ - else if (interruptFlags & kSDIF_HardwareLockError) - { - if (handle->callback.CommandReload) - { - handle->callback.CommandReload(); - } - } - /* transfer command success */ - else - { - SDIF_ReadCommandResponse(base, handle->command); - if (((handle->data) == NULL) && (handle->callback.TransferComplete)) - { - handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); - } - } -} - -static void SDIF_TransferHandleData(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags) -{ - assert(handle->data); - - /* data starvation by host time out, software should read/write FIFO*/ - if (interruptFlags & kSDIF_DataStarvationByHostTimeout) - { - if (handle->data->rxData != NULL) - { - handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords); - } - else if (handle->data->txData != NULL) - { - handle->transferredWords = SDIF_WriteDataPort(base, handle->data, handle->transferredWords); - } - else - { - handle->callback.TransferComplete(base, handle, kStatus_SDIF_DataTransferFail, handle->userData); - } - } - /* data transfer fail */ - else if (interruptFlags & kSDIF_DataTransferError) - { - if (!handle->data->enableIgnoreError) - { - handle->callback.TransferComplete(base, handle, kStatus_SDIF_DataTransferFail, handle->userData); - } - } - /* need fill data to FIFO */ - else if (interruptFlags & kSDIF_WriteFIFORequest) - { - handle->transferredWords = SDIF_WriteDataPort(base, handle->data, handle->transferredWords); - } - /* need read data from FIFO */ - else if (interruptFlags & kSDIF_ReadFIFORequest) - { - handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords); - } - else - { - } - - /* data transfer over */ - if (interruptFlags & kSDIF_DataTransferOver) - { - while ((handle->data->rxData != NULL) && ((base->STATUS & SDIF_STATUS_FIFO_COUNT_MASK) != 0U)) - { - handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords); - } - handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); - } -} - -static void SDIF_TransferHandleDMA(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags) -{ - if (interruptFlags & kSDIF_DMAFatalBusError) - { - handle->callback.TransferComplete(base, handle, kStatus_SDIF_DMATransferFailWithFBE, handle->userData); - } - else if (interruptFlags & kSDIF_DMADescriptorUnavailable) - { - if (handle->callback.DMADesUnavailable) - { - handle->callback.DMADesUnavailable(); - } - } - else if ((interruptFlags & (kSDIF_AbnormalInterruptSummary | kSDIF_DMACardErrorSummary)) && - (!handle->data->enableIgnoreError)) - { - handle->callback.TransferComplete(base, handle, kStatus_SDIF_DataTransferFail, handle->userData); - } - /* card normal summary */ - else - { - handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); - } -} - -static void SDIF_TransferHandleSDIOInterrupt(sdif_handle_t *handle) -{ - if (handle->callback.SDIOInterrupt != NULL) - { - handle->callback.SDIOInterrupt(); - } -} - -static void SDIF_TransferHandleIRQ(SDIF_Type *base, sdif_handle_t *handle) -{ - assert(handle); - - uint32_t interruptFlags, dmaInterruptFlags; - - interruptFlags = SDIF_GetInterruptStatus(base); - dmaInterruptFlags = SDIF_GetInternalDMAStatus(base); - - handle->interruptFlags = interruptFlags; - handle->dmaInterruptFlags = dmaInterruptFlags; - - if ((interruptFlags & kSDIF_CommandTransferStatus) != 0U) - { - SDIF_TransferHandleCommand(base, handle, (interruptFlags & kSDIF_CommandTransferStatus)); - } - if ((interruptFlags & kSDIF_DataTransferStatus) != 0U) - { - SDIF_TransferHandleData(base, handle, (interruptFlags & kSDIF_DataTransferStatus)); - } - if (interruptFlags & kSDIF_SDIOInterrupt) - { - SDIF_TransferHandleSDIOInterrupt(handle); - } - if (dmaInterruptFlags & kSDIF_DMAAllStatus) - { - SDIF_TransferHandleDMA(base, handle, dmaInterruptFlags); - } - - SDIF_ClearInterruptStatus(base, interruptFlags); - SDIF_ClearInternalDMAStatus(base, dmaInterruptFlags); -} - -void SDIF_Deinit(SDIF_Type *base) -{ - /* disable clock here*/ - CLOCK_DisableClock(kCLOCK_Sdio); - /* disable the SDIOCLKCTRL */ - SYSCON->SDIOCLKCTRL &= ~(SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK); - RESET_PeripheralReset(kSDIO_RST_SHIFT_RSTn); -} - -#if defined(SDIF) - -#include -#include - -void SDIF_DriverIRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - assert(s_sdifHandle[0]); - - s_sdifIsr(SDIF, s_sdifHandle[0]); - - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_sdif.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_sdif.h deleted file mode 100644 index 6b1b7e8c08c..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_sdif.h +++ /dev/null @@ -1,824 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_SDIF_H_ -#define _FSL_SDIF_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup sdif - * @{ - */ - -/****************************************************************************** - * Definitions. - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Driver version 2.0.1. */ -#define FSL_SDIF_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U)) -/*@}*/ - -#define SDIF_DriverIRQHandler SDIO_DriverIRQHandler /*!< convert the name here, due to RM use SDIO */ - -#define SDIF_SUPPORT_SD_VERSION (0x20) /*!< define the controller support sd/sdio card version 2.0 */ -#define SDIF_SUPPORT_MMC_VERSION (0x44) /*!< define the controller support mmc card version 4.4 */ - -#define SDIF_TIMEOUT_VALUE (65535U) /*!< define the timeout counter */ -#define SDIF_POLL_DEMAND_VALUE (0xFFU) /*!< this value can be any value */ - -#define SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(x) (x & 0x1FFFU) /*!< DMA descriptor buffer1 size */ -#define SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(x) ((x & 0x1FFFU) << 13U) /*!STATUS & SDIF_STATUS_DATA_3_STATUS_MASK; - } - else - { - return base->CDETECT & SDIF_CDETECT_CARD_DETECT_MASK; - } -} - -/*! - * @brief SDIF module enable/disable card clock. - * @param base SDIF peripheral base address. - * @param enable/disable flag - */ -static inline void SDIF_EnableCardClock(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CLKENA |= SDIF_CLKENA_CCLK_ENABLE_MASK; - } - else - { - base->CLKENA &= ~SDIF_CLKENA_CCLK_ENABLE_MASK; - } -} - -/*! - * @brief SDIF module enable/disable module disable the card clock - * to enter low power mode when card is idle,for SDIF cards, if - * interrupts must be detected, clock should not be stopped - * @param base SDIF peripheral base address. - * @param enable/disable flag - */ -static inline void SDIF_EnableLowPowerMode(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CLKENA |= SDIF_CLKENA_CCLK_LOW_POWER_MASK; - } - else - { - base->CLKENA &= ~SDIF_CLKENA_CCLK_LOW_POWER_MASK; - } -} - -/*! - * @brief Sets the card bus clock frequency. - * - * @param base SDIF peripheral base address. - * @param srcClock_Hz SDIF source clock frequency united in Hz. - * @param target_HZ card bus clock frequency united in Hz. - * @return The nearest frequency of busClock_Hz configured to SD bus. - */ -uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t target_HZ); - -/*! - * @brief reset the different block of the interface. - * @param base SDIF peripheral base address. - * @param mask indicate which block to reset. - * @param timeout value,set to wait the bit self clear - * @return reset result. - */ -bool SDIF_Reset(SDIF_Type *base, uint32_t mask, uint32_t timeout); - -/*! - * @brief enable/disable the card power. - * once turn power on, software should wait for regulator/switch - * ramp-up time before trying to initialize card. - * @param base SDIF peripheral base address. - * @param enable/disable flag. - */ -static inline void SDIF_EnableCardPower(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->PWREN |= SDIF_PWREN_POWER_ENABLE_MASK; - } - else - { - base->PWREN &= ~SDIF_PWREN_POWER_ENABLE_MASK; - } -} - -/*! - * @brief get the card write protect status - * @param base SDIF peripheral base address. - */ -static inline uint32_t SDIF_GetCardWriteProtect(SDIF_Type *base) -{ - return base->WRTPRT & SDIF_WRTPRT_WRITE_PROTECT_MASK; -} - -/*! - * @brief set card data bus width - * @param base SDIF peripheral base address. - * @param data bus width type - */ -static inline void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type) -{ - base->CTYPE = type; -} - -/*! - * @brief toggle state on hardware reset PIN - * This is used which card has a reset PIN typically. - * @param base SDIF peripheral base address. - */ -static inline void SDIF_AssertHardwareReset(SDIF_Type *base) -{ - base->RST_N &= ~SDIF_RST_N_CARD_RESET_MASK; -} - -/*! - * @brief send command to the card - * @param base SDIF peripheral base address. - * @param command configuration collection - * @param timeout value - * @return command excute status - */ -status_t SDIF_SendCommand(SDIF_Type *base, sdif_command_t *cmd, uint32_t timeout); - -/*! - * @brief SDIF enable/disable global interrupt - * @param base SDIF peripheral base address. - * @param enable/disable flag - */ -static inline void SDIF_EnableGlobalInterrupt(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= SDIF_CTRL_INT_ENABLE_MASK; - } - else - { - base->CTRL &= ~SDIF_CTRL_INT_ENABLE_MASK; - } -} - -/*! - * @brief SDIF enable interrupt - * @param base SDIF peripheral base address. - * @param interrupt mask - */ -static inline void SDIF_EnableInterrupt(SDIF_Type *base, uint32_t mask) -{ - base->INTMASK |= mask; -} - -/*! - * @brief SDIF disable interrupt - * @param base SDIF peripheral base address. - * @param interrupt mask - */ -static inline void SDIF_DisableInterrupt(SDIF_Type *base, uint32_t mask) -{ - base->INTMASK &= ~mask; -} - -/*! - * @brief SDIF get interrupt status - * @param base SDIF peripheral base address. - */ -static inline uint32_t SDIF_GetInterruptStatus(SDIF_Type *base) -{ - return base->MINTSTS; -} - -/*! - * @brief SDIF clear interrupt status - * @param base SDIF peripheral base address. - * @param status mask to clear - */ -static inline void SDIF_ClearInterruptStatus(SDIF_Type *base, uint32_t mask) -{ - base->RINTSTS &= mask; -} - -/*! - * @brief Creates the SDIF handle. - * register call back function for interrupt and enable the interrupt - * @param base SDIF peripheral base address. - * @param handle SDIF handle pointer. - * @param callback Structure pointer to contain all callback functions. - * @param userData Callback function parameter. - */ -void SDIF_TransferCreateHandle(SDIF_Type *base, - sdif_handle_t *handle, - sdif_transfer_callback_t *callback, - void *userData); - -/*! - * @brief SDIF enable DMA interrupt - * @param base SDIF peripheral base address. - * @param interrupt mask to set - */ -static inline void SDIF_EnableDmaInterrupt(SDIF_Type *base, uint32_t mask) -{ - base->IDINTEN |= mask; -} - -/*! - * @brief SDIF disable DMA interrupt - * @param base SDIF peripheral base address. - * @param interrupt mask to clear - */ -static inline void SDIF_DisableDmaInterrupt(SDIF_Type *base, uint32_t mask) -{ - base->IDINTEN &= ~mask; -} - -/*! - * @brief SDIF get internal DMA status - * @param base SDIF peripheral base address. - * @return the internal DMA status register - */ -static inline uint32_t SDIF_GetInternalDMAStatus(SDIF_Type *base) -{ - return base->IDSTS; -} - -/*! - * @brief SDIF clear internal DMA status - * @param base SDIF peripheral base address. - * @param status mask to clear - */ -static inline void SDIF_ClearInternalDMAStatus(SDIF_Type *base, uint32_t mask) -{ - base->IDSTS &= mask; -} - -/*! - * @brief SDIF internal DMA config function - * @param base SDIF peripheral base address. - * @param internal DMA configuration collection - * @param data buffer pointer - * @param data buffer size - */ -status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, const uint32_t *data, uint32_t dataSize); - -/*! - * @brief SDIF send read wait to SDIF card function - * @param base SDIF peripheral base address. - */ -static inline void SDIF_SendReadWait(SDIF_Type *base) -{ - base->CTRL |= SDIF_CTRL_READ_WAIT_MASK; -} - -/*! - * @brief SDIF abort the read data when SDIF card is in suspend state - * Once assert this bit,data state machine will be reset which is waiting for the - * next blocking data,used in SDIO card suspend sequence,should call after suspend - * cmd send - * @param base SDIF peripheral base address. - * @param timeout value to wait this bit self clear which indicate the data machine - * reset to idle - */ -bool SDIF_AbortReadData(SDIF_Type *base, uint32_t timeout); - -/*! - * @brief SDIF enable/disable CE-ATA card interrupt - * this bit should set together with the card register - * @param base SDIF peripheral base address. - * @param enable/disable flag - */ -static inline void SDIF_EnableCEATAInterrupt(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK; - } - else - { - base->CTRL &= ~SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK; - } -} - -/*! - * @brief SDIF transfer function data/cmd in a non-blocking way - * this API should be use in interrupt mode, when use this API user - * must call SDIF_TransferCreateHandle first, all status check through - * interrupt - * @param base SDIF peripheral base address. - * @param sdif handle - * @param DMA config structure - * This parameter can be config as: - * 1. NULL - In this condition, polling transfer mode is selected - 2. avaliable DMA config - In this condition, DMA transfer mode is selected - * @param sdif transfer configuration collection - */ -status_t SDIF_TransferNonBlocking(SDIF_Type *base, - sdif_handle_t *handle, - sdif_dma_config_t *dmaConfig, - sdif_transfer_t *transfer); - -/*! - * @brief SDIF transfer function data/cmd in a blocking way - * @param base SDIF peripheral base address. - * @param DMA config structure - * 1. NULL - * In this condition, polling transfer mode is selected - * 2. avaliable DMA config - * In this condition, DMA transfer mode is selected - * @param sdif transfer configuration collection - */ -status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sdif_transfer_t *transfer); - -/*! - * @brief SDIF release the DMA descriptor to DMA engine - * this function should be called when DMA descriptor unavailable status occurs - * @param base SDIF peripheral base address. - * @param sdif DMA config pointer - */ -status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig); - -/*! - * @brief SDIF return the controller capability - * @param base SDIF peripheral base address. - * @param sdif capability pointer - */ -void SDIF_GetCapability(SDIF_Type *base, sdif_capability_t *capability); - -/*! - * @brief SDIF return the controller status - * @param base SDIF peripheral base address. - */ -static inline uint32_t SDIF_GetControllerStatus(SDIF_Type *base) -{ - return base->STATUS; -} - -/*! - * @brief SDIF send command complete signal disable to CE-ATA card - * @param base SDIF peripheral base address. - * @param send auto stop flag - */ -static inline void SDIF_SendCCSD(SDIF_Type *base, bool withAutoStop) -{ - if (withAutoStop) - { - base->CTRL |= SDIF_CTRL_SEND_CCSD_MASK | SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK; - } - else - { - base->CTRL |= SDIF_CTRL_SEND_CCSD_MASK; - } -} - -/*! - * @brief SDIF config the clock delay - * This function is used to config the cclk_in delay to - * sample and drvive the data ,should meet the min setup - * time and hold time, and user need to config this paramter - * according to your board setting - * @param target freq work mode - * @param clock divider which is used to decide if use pharse shift for delay - */ -void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider); - -/* @} */ - -#if defined(__cplusplus) -} -#endif -/*! @} */ - -#endif /* _FSL_sdif_H_*/ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spi.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spi.c deleted file mode 100644 index c205e95a071..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spi.c +++ /dev/null @@ -1,712 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_spi.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitons - ******************************************************************************/ -/* Note: FIFOCFG[SIZE] has always value 1 = 8 items depth */ -#define SPI_FIFO_DEPTH(base) ((((base)->FIFOCFG & SPI_FIFOCFG_SIZE_MASK) >> SPI_FIFOCFG_SIZE_SHIFT) << 3) - -/* Convert transfer count to transfer bytes. dataWidth is a - * range <0,15>. Range <8,15> represents 2B transfer */ -#define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U)) -#define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U)) - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief internal SPI config array */ -static spi_config_t g_configs[FSL_FEATURE_SOC_SPI_COUNT] = {(spi_data_width_t)0}; - -/*! @brief Array to map SPI instance number to base address. */ -static const uint32_t s_spiBaseAddrs[FSL_FEATURE_SOC_SPI_COUNT] = SPI_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_spiIRQ[] = SPI_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Get the index corresponding to the FLEXCOMM */ -uint32_t SPI_GetInstance(SPI_Type *base) -{ - int i; - - for (i = 0; i < FSL_FEATURE_SOC_SPI_COUNT; i++) - { - if ((uint32_t)base == s_spiBaseAddrs[i]) - { - return i; - } - } - - assert(false); - return 0; -} - -void *SPI_GetConfig(SPI_Type *base) -{ - int32_t instance; - instance = SPI_GetInstance(base); - if (instance < 0) - { - return NULL; - } - return &g_configs[instance]; -} - -void SPI_MasterGetDefaultConfig(spi_master_config_t *config) -{ - assert(NULL != config); - - config->enableLoopback = false; - config->enableMaster = true; - config->polarity = kSPI_ClockPolarityActiveHigh; - config->phase = kSPI_ClockPhaseFirstEdge; - config->direction = kSPI_MsbFirst; - config->baudRate_Bps = 500000U; - config->dataWidth = kSPI_Data8Bits; - config->sselNum = kSPI_Ssel0; - config->txWatermark = kSPI_TxFifo0; - config->rxWatermark = kSPI_RxFifo1; -} - -status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz) -{ - int32_t result = 0, instance = 0; - uint32_t tmp; - - /* assert params */ - assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz))); - if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* initialize flexcomm to SPI mode */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); - assert(kStatus_Success == result); - if (kStatus_Success != result) - { - return result; - } - - /* set divider */ - result = SPI_MasterSetBaud(base, config->baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - /* get instance number */ - instance = SPI_GetInstance(base); - assert(instance >= 0); - - /* configure SPI mode */ - tmp = base->CFG; - tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | SPI_CFG_ENABLE_MASK); - /* phase */ - tmp |= SPI_CFG_CPHA(config->phase); - /* polarity */ - tmp |= SPI_CFG_CPOL(config->polarity); - /* direction */ - tmp |= SPI_CFG_LSBF(config->direction); - /* master mode */ - tmp |= SPI_CFG_MASTER(1); - /* loopback */ - tmp |= SPI_CFG_LOOP(config->enableLoopback); - base->CFG = tmp; - - /* store configuration */ - g_configs[instance].dataWidth = config->dataWidth; - g_configs[instance].sselNum = config->sselNum; - /* enable FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; - /* trigger level - empty txFIFO, one item in rxFIFO */ - tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); - tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable generating interrupts for FIFOTRIG levels */ - tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; - /* set FIFOTRIG */ - base->FIFOTRIG = tmp; - - SPI_Enable(base, config->enableMaster); - return kStatus_Success; -} - -void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config) -{ - assert(NULL != config); - - config->enableSlave = true; - config->polarity = kSPI_ClockPolarityActiveHigh; - config->phase = kSPI_ClockPhaseFirstEdge; - config->direction = kSPI_MsbFirst; - config->dataWidth = kSPI_Data8Bits; - config->txWatermark = kSPI_TxFifo0; - config->rxWatermark = kSPI_RxFifo1; -} - -status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) -{ - int32_t result = 0, instance; - uint32_t tmp; - - /* assert params */ - assert(!((NULL == base) || (NULL == config))); - if ((NULL == base) || (NULL == config)) - { - return kStatus_InvalidArgument; - } - /* configure flexcomm to SPI, enable clock gate */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); - assert(kStatus_Success == result); - if (kStatus_Success != result) - { - return result; - } - - instance = SPI_GetInstance(base); - - /* configure SPI mode */ - tmp = base->CFG; - tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_ENABLE_MASK); - /* phase */ - tmp |= SPI_CFG_CPHA(config->phase); - /* polarity */ - tmp |= SPI_CFG_CPOL(config->polarity); - /* direction */ - tmp |= SPI_CFG_LSBF(config->direction); - base->CFG = tmp; - - /* store configuration */ - g_configs[instance].dataWidth = config->dataWidth; - /* empty and enable FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; - /* trigger level - empty txFIFO, one item in rxFIFO */ - tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); - tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable generating interrupts for FIFOTRIG levels */ - tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; - /* set FIFOTRIG */ - base->FIFOTRIG = tmp; - - SPI_Enable(base, config->enableSlave); - return kStatus_Success; -} - -void SPI_Deinit(SPI_Type *base) -{ - /* Assert arguments */ - assert(NULL != base); - /* Disable interrupts, disable dma requests, disable peripheral */ - base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXERR_MASK | SPI_FIFOINTENCLR_RXERR_MASK | SPI_FIFOINTENCLR_TXLVL_MASK | - SPI_FIFOINTENCLR_RXLVL_MASK; - base->FIFOCFG &= ~(SPI_FIFOCFG_DMATX_MASK | SPI_FIFOCFG_DMARX_MASK); - base->CFG &= ~(SPI_CFG_ENABLE_MASK); -} - -void SPI_EnableTxDMA(SPI_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= SPI_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= ~SPI_FIFOCFG_DMATX_MASK; - } -} - -void SPI_EnableRxDMA(SPI_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= SPI_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= ~SPI_FIFOCFG_DMARX_MASK; - } -} - -status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) -{ - uint32_t tmp; - - /* assert params */ - assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))); - if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* calculate baudrate */ - tmp = (srcClock_Hz / baudrate_Bps) - 1; - if (tmp > 0xFFFF) - { - return kStatus_SPI_BaudrateNotSupport; - } - base->DIV &= ~SPI_DIV_DIVVAL_MASK; - base->DIV |= SPI_DIV_DIVVAL(tmp); - return kStatus_Success; -} - -void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags) -{ - uint32_t control = 0; - int32_t instance; - - /* check params */ - assert(NULL != base); - /* get and check instance */ - instance = SPI_GetInstance(base); - assert(!(instance < 0)); - if (instance < 0) - { - return; - } - - /* set data width */ - control |= SPI_FIFOWR_LEN(g_configs[instance].dataWidth); - /* set sssel */ - control |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum))); - /* mask configFlags */ - control |= (configFlags & SPI_FIFOWR_FLAGS_MASK); - /* control should not affect lower 16 bits */ - assert(!(control & 0xFFFF)); - base->FIFOWR = data | control; -} - -status_t SPI_MasterTransferCreateHandle(SPI_Type *base, - spi_master_handle_t *handle, - spi_master_callback_t callback, - void *userData) -{ - int32_t instance = 0; - - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } - /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - /* get flexcomm instance by 'base' param */ - instance = SPI_GetInstance(base); - assert(!(instance < 0)); - if (instance < 0) - { - return kStatus_InvalidArgument; - } - - memset(handle, 0, sizeof(*handle)); - /* Initialize the handle */ - if (base->CFG & SPI_CFG_MASTER_MASK) - { - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)SPI_MasterTransferHandleIRQ, handle); - } - else - { - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)SPI_SlaveTransferHandleIRQ, handle); - } - - handle->dataWidth = g_configs[instance].dataWidth; - /* in slave mode, the sselNum is not important */ - handle->sselNum = g_configs[instance].sselNum; - handle->txWatermark = (spi_txfifo_watermark_t)SPI_FIFOTRIG_TXLVL_GET(base); - handle->rxWatermark = (spi_rxfifo_watermark_t)SPI_FIFOTRIG_RXLVL_GET(base); - handle->callback = callback; - handle->userData = userData; - - /* Enable SPI NVIC */ - EnableIRQ(s_spiIRQ[instance]); - - return kStatus_Success; -} - -status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) -{ - int32_t instance; - uint32_t tx_ctrl = 0, last_ctrl = 0; - uint32_t tmp32, rxRemainingBytes, txRemainingBytes, dataWidth; - uint32_t toReceiveCount = 0; - uint8_t *txData, *rxData; - uint32_t fifoDepth; - - /* check params */ - assert(!((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); - if ((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) - { - return kStatus_InvalidArgument; - } - - fifoDepth = SPI_FIFO_DEPTH(base); - txData = xfer->txData; - rxData = xfer->rxData; - txRemainingBytes = txData ? xfer->dataSize : 0; - rxRemainingBytes = rxData ? xfer->dataSize : 0; - - instance = SPI_GetInstance(base); - assert(instance >= 0); - dataWidth = g_configs[instance].dataWidth; - - /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ - assert(!((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))); - if ((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)) - { - return kStatus_InvalidArgument; - } - - /* clear tx/rx errors and empty FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - /* select slave to talk with */ - tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum))); - /* set width of data - range asserted at entry */ - tx_ctrl |= SPI_FIFOWR_LEN(dataWidth); - /* end of transfer */ - last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0; - /* delay end of transfer */ - last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; - /* last index of loop */ - while (txRemainingBytes || rxRemainingBytes || toReceiveCount) - { - /* if rxFIFO is not empty */ - if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) - { - tmp32 = base->FIFORD; - /* rxBuffer is not empty */ - if (rxRemainingBytes) - { - *(rxData++) = tmp32; - rxRemainingBytes--; - /* read 16 bits at once */ - if (dataWidth > 8) - { - *(rxData++) = tmp32 >> 8; - rxRemainingBytes--; - } - } - /* decrease number of data expected to receive */ - toReceiveCount -= 1; - } - /* transmit if txFIFO is not full and data to receive does not exceed FIFO depth */ - if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (toReceiveCount < fifoDepth) && - ((txRemainingBytes) || (rxRemainingBytes >= SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1)))) - { - /* txBuffer is not empty */ - if (txRemainingBytes) - { - tmp32 = *(txData++); - txRemainingBytes--; - /* write 16 bit at once */ - if (dataWidth > 8) - { - tmp32 |= ((uint32_t)(*(txData++))) << 8U; - txRemainingBytes--; - } - if (!txRemainingBytes) - { - tx_ctrl |= last_ctrl; - } - } - else - { - tmp32 = SPI_DUMMYDATA; - /* last transfer */ - if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1)) - { - tx_ctrl |= last_ctrl; - } - } - /* send data */ - tmp32 = tx_ctrl | tmp32; - base->FIFOWR = tmp32; - toReceiveCount += 1; - } - } - /* wait if TX FIFO of previous transfer is not empty */ - while (!(base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) - { - } - return kStatus_Success; -} - -status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer) -{ - /* check params */ - assert( - !((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) - { - return kStatus_InvalidArgument; - } - - /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ - assert(!((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))); - if ((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)) - { - return kStatus_InvalidArgument; - } - - /* Check if SPI is busy */ - if (handle->state == kStatus_SPI_Busy) - { - return kStatus_SPI_Busy; - } - - /* Set the handle information */ - handle->txData = xfer->txData; - handle->rxData = xfer->rxData; - /* set count */ - handle->txRemainingBytes = xfer->txData ? xfer->dataSize : 0; - handle->rxRemainingBytes = xfer->rxData ? xfer->dataSize : 0; - handle->totalByteCount = xfer->dataSize; - /* other options */ - handle->toReceiveCount = 0; - handle->configFlags = xfer->configFlags; - /* Set the SPI state to busy */ - handle->state = kStatus_SPI_Busy; - /* clear FIFOs when transfer starts */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - /* enable generating txIRQ and rxIRQ, first transfer is fired by empty txFIFO */ - base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK; - return kStatus_Success; -} - -status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count) -{ - assert(NULL != handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != kStatus_SPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - *count = handle->totalByteCount - handle->rxRemainingBytes; - return kStatus_Success; -} - -void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle) -{ - assert(NULL != handle); - - /* Disable interrupt requests*/ - base->FIFOINTENSET &= ~(SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK); - /* Empty FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - - handle->state = kStatus_SPI_Idle; - handle->txRemainingBytes = 0; - handle->rxRemainingBytes = 0; -} - -static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *handle) -{ - uint32_t tx_ctrl = 0, last_ctrl = 0, tmp32; - bool loopContinue; - uint32_t fifoDepth; - - /* check params */ - assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData))); - - fifoDepth = SPI_FIFO_DEPTH(base); - /* select slave to talk with */ - tx_ctrl |= (SPI_DEASSERT_ALL & SPI_ASSERTNUM_SSEL(handle->sselNum)); - /* set width of data */ - tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth); - /* end of transfer */ - last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0; - /* delay end of transfer */ - last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; - do - { - loopContinue = false; - - /* rxFIFO is not empty */ - if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) - { - tmp32 = base->FIFORD; - /* rxBuffer is not empty */ - if (handle->rxRemainingBytes) - { - /* low byte must go first */ - *(handle->rxData++) = tmp32; - handle->rxRemainingBytes--; - /* read 16 bits at once */ - if (handle->dataWidth > kSPI_Data8Bits) - { - *(handle->rxData++) = tmp32 >> 8; - handle->rxRemainingBytes--; - } - } - /* decrease number of data expected to receive */ - handle->toReceiveCount -= 1; - loopContinue = true; - } - - /* - txFIFO is not full - * - we cannot cause rxFIFO overflow by sending more data than is the depth of FIFO - * - txBuffer is not empty or the next 'toReceiveCount' data can fit into rxBuffer - */ - if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (handle->toReceiveCount < fifoDepth) && - ((handle->txRemainingBytes) || - (handle->rxRemainingBytes >= SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1)))) - { - /* txBuffer is not empty */ - if (handle->txRemainingBytes) - { - /* low byte must go first */ - tmp32 = *(handle->txData++); - handle->txRemainingBytes--; - /* write 16 bit at once */ - if (handle->dataWidth > kSPI_Data8Bits) - { - tmp32 |= ((uint32_t)(*(handle->txData++))) << 8U; - handle->txRemainingBytes--; - } - /* last transfer */ - if (!handle->txRemainingBytes) - { - tx_ctrl |= last_ctrl; - } - } - else - { - tmp32 = SPI_DUMMYDATA; - /* last transfer */ - if (handle->rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1)) - { - tx_ctrl |= last_ctrl; - } - } - /* send data */ - tmp32 = tx_ctrl | tmp32; - base->FIFOWR = tmp32; - /* increase number of expected data to receive */ - handle->toReceiveCount += 1; - loopContinue = true; - } - } while (loopContinue); -} - -void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle) -{ - assert((NULL != base) && (NULL != handle)); - - /* IRQ behaviour: - * - first interrupt is triggered by empty txFIFO. The transfer function - * then tries empty rxFIFO and fill txFIFO interleaved that results to - * strategy to process as many items as possible. - * - the next IRQs can be: - * rxIRQ from nonempty rxFIFO which requires to empty rxFIFO. - * txIRQ from empty txFIFO which requires to refill txFIFO. - * - last interrupt is triggered by empty txFIFO. The last state is - * known by empty rxBuffer and txBuffer. If there is nothing to receive - * or send - both operations have been finished and interrupts can be - * disabled. - */ - - /* Data to send or read or expected to receive */ - if ((handle->txRemainingBytes) || (handle->rxRemainingBytes) || (handle->toReceiveCount)) - { - /* Transmit or receive data */ - SPI_TransferHandleIRQInternal(base, handle); - /* No data to send or read or receive. Transfer ends. Set txTrigger to 0 level and - * enable txIRQ to confirm when txFIFO becomes empty */ - if ((!handle->txRemainingBytes) && (!handle->rxRemainingBytes) && (!handle->toReceiveCount)) - { - base->FIFOTRIG = base->FIFOTRIG & (~SPI_FIFOTRIG_TXLVL_MASK); - base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK; - } - else - { - uint32_t rxRemainingCount = SPI_BYTES_TO_COUNT(handle->dataWidth, handle->rxRemainingBytes); - /* If, there are no data to send or rxFIFO is already filled with necessary number of dummy data, - * disable txIRQ. From this point only rxIRQ is used to receive data without any transmission */ - if ((!handle->txRemainingBytes) && (rxRemainingCount <= handle->toReceiveCount)) - { - base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXLVL_MASK; - } - /* Nothing to receive or transmit, but we still have pending data which are bellow rxLevel. - * Cannot clear rxFIFO, txFIFO might be still active */ - if (rxRemainingCount == 0) - { - if ((handle->txRemainingBytes == 0) && (handle->toReceiveCount != 0) && - (handle->toReceiveCount < SPI_FIFOTRIG_RXLVL_GET(base) + 1)) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(handle->toReceiveCount - 1); - } - } - /* Expected to receive less data than rxLevel value, we have to update rxLevel */ - else - { - if (rxRemainingCount < (SPI_FIFOTRIG_RXLVL_GET(base) + 1)) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(rxRemainingCount - 1); - } - } - } - } - else - { - /* Empty txFIFO is confirmed. Disable IRQs and restore triggers values */ - base->FIFOINTENCLR = SPI_FIFOINTENCLR_RXLVL_MASK | SPI_FIFOINTENCLR_TXLVL_MASK; - base->FIFOTRIG = (base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_RXLVL_MASK))) | - SPI_FIFOTRIG_RXLVL(handle->rxWatermark) | SPI_FIFOTRIG_TXLVL(handle->txWatermark); - /* set idle state and call user callback */ - handle->state = kStatus_SPI_Idle; - if (handle->callback) - { - (handle->callback)(base, handle, handle->state, handle->userData); - } - } -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spi.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spi.h deleted file mode 100644 index e444774a7ba..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spi.h +++ /dev/null @@ -1,629 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_SPI_H_ -#define _FSL_SPI_H_ - -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/*! - * @addtogroup spi_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief USART driver version 2.0.0. */ -#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -#define SPI_DUMMYDATA (0xFFFF) -#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFF) -#define SPI_CTRLMASK (0xFFFF0000) - -#define SPI_ASSERTNUM_SSEL(n) ((~(1U << ((n) + 16))) & 0xF0000) -#define SPI_DEASSERTNUM_SSEL(n) (1U << ((n) + 16)) -#define SPI_DEASSERT_ALL (0xF0000) - -#define SPI_FIFOWR_FLAGS_MASK (~(SPI_DEASSERT_ALL | SPI_FIFOWR_TXDATA_MASK | SPI_FIFOWR_LEN_MASK)) - -#define SPI_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_TXLVL_MASK) >> SPI_FIFOTRIG_TXLVL_SHIFT) -#define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT) - -/*! @brief SPI transfer option.*/ -typedef enum _spi_xfer_option { - kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), /*!< Delay chip select */ - kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< When transfer ends, assert chip select */ -} spi_xfer_option_t; - -/*! @brief SPI data shifter direction options.*/ -typedef enum _spi_shift_direction { - kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */ - kSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. */ -} spi_shift_direction_t; - -/*! @brief SPI clock polarity configuration.*/ -typedef enum _spi_clock_polarity { - kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */ - kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */ -} spi_clock_polarity_t; - -/*! @brief SPI clock phase configuration.*/ -typedef enum _spi_clock_phase { - kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first - * cycle of a data transfer. */ - kSPI_ClockPhaseSecondEdge /*!< First edge on SCK occurs at the start of the - * first cycle of a data transfer. */ -} spi_clock_phase_t; - -/*! @brief txFIFO watermark values */ -typedef enum _spi_txfifo_watermark { - kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */ - kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */ - kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */ - kSPI_TxFifo3 = 3, /*!< SPI tx watermark at 3 items */ - kSPI_TxFifo4 = 4, /*!< SPI tx watermark at 4 items */ - kSPI_TxFifo5 = 5, /*!< SPI tx watermark at 5 items */ - kSPI_TxFifo6 = 6, /*!< SPI tx watermark at 6 items */ - kSPI_TxFifo7 = 7, /*!< SPI tx watermark at 7 items */ -} spi_txfifo_watermark_t; - -/*! @brief rxFIFO watermark values */ -typedef enum _spi_rxfifo_watermark { - kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */ - kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */ - kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */ - kSPI_RxFifo4 = 3, /*!< SPI rx watermark at 4 items */ - kSPI_RxFifo5 = 4, /*!< SPI rx watermark at 5 items */ - kSPI_RxFifo6 = 5, /*!< SPI rx watermark at 6 items */ - kSPI_RxFifo7 = 6, /*!< SPI rx watermark at 7 items */ - kSPI_RxFifo8 = 7, /*!< SPI rx watermark at 8 items */ -} spi_rxfifo_watermark_t; - -/*! @brief Transfer data width */ -typedef enum _spi_data_width { - kSPI_Data4Bits = 3, /*!< 4 bits data width */ - kSPI_Data5Bits = 4, /*!< 5 bits data width */ - kSPI_Data6Bits = 5, /*!< 6 bits data width */ - kSPI_Data7Bits = 6, /*!< 7 bits data width */ - kSPI_Data8Bits = 7, /*!< 8 bits data width */ - kSPI_Data9Bits = 8, /*!< 9 bits data width */ - kSPI_Data10Bits = 9, /*!< 10 bits data width */ - kSPI_Data11Bits = 10, /*!< 11 bits data width */ - kSPI_Data12Bits = 11, /*!< 12 bits data width */ - kSPI_Data13Bits = 12, /*!< 13 bits data width */ - kSPI_Data14Bits = 13, /*!< 14 bits data width */ - kSPI_Data15Bits = 14, /*!< 15 bits data width */ - kSPI_Data16Bits = 15, /*!< 16 bits data width */ -} spi_data_width_t; - -/*! @brief Slave select */ -typedef enum _spi_ssel { - kSPI_Ssel0 = 0, /*!< Slave select 0 */ - kSPI_Ssel1 = 1, /*!< Slave select 1 */ - kSPI_Ssel2 = 2, /*!< Slave select 2 */ - kSPI_Ssel3 = 3, /*!< Slave select 3 */ -} spi_ssel_t; - -/*! @brief SPI master user configure structure.*/ -typedef struct _spi_master_config -{ - bool enableLoopback; /*!< Enable loopback for test purpose */ - bool enableMaster; /*!< Enable SPI at initialization time */ - spi_clock_polarity_t polarity; /*!< Clock polarity */ - spi_clock_phase_t phase; /*!< Clock phase */ - spi_shift_direction_t direction; /*!< MSB or LSB */ - uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */ - spi_data_width_t dataWidth; /*!< Width of the data */ - spi_ssel_t sselNum; /*!< Slave select number */ - spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ -} spi_master_config_t; - -/*! @brief SPI slave user configure structure.*/ -typedef struct _spi_slave_config -{ - bool enableSlave; /*!< Enable SPI at initialization time */ - spi_clock_polarity_t polarity; /*!< Clock polarity */ - spi_clock_phase_t phase; /*!< Clock phase */ - spi_shift_direction_t direction; /*!< MSB or LSB */ - spi_data_width_t dataWidth; /*!< Width of the data */ - spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ -} spi_slave_config_t; - -/*! @brief SPI transfer status.*/ -enum _spi_status -{ - kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0), /*!< SPI bus is busy */ - kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1), /*!< SPI is idle */ - kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI error */ - kStatus_SPI_BaudrateNotSupport = - MAKE_STATUS(kStatusGroup_LPC_SPI, 3) /*!< Baudrate is not support in current clock source */ -}; - -/*! @brief SPI interrupt sources.*/ -enum _spi_interrupt_enable -{ - kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, /*!< Rx level interrupt */ - kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, /*!< Tx level interrupt */ -}; - -/*! @brief SPI status flags.*/ -enum _spi_statusflags -{ - kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK, /*!< txFifo is empty */ - kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK, /*!< txFifo is not full */ - kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, /*!< rxFIFO is not empty */ - kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK, /*!< rxFIFO is full */ -}; - -/*! @brief SPI transfer structure */ -typedef struct _spi_transfer -{ - uint8_t *txData; /*!< Send buffer */ - uint8_t *rxData; /*!< Receive buffer */ - uint32_t configFlags; /*!< Additional option to control transfer */ - size_t dataSize; /*!< Transfer bytes */ -} spi_transfer_t; - -/*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */ -typedef struct _spi_config -{ - spi_data_width_t dataWidth; - spi_ssel_t sselNum; -} spi_config_t; - -/*! @brief Master handle type */ -typedef struct _spi_master_handle spi_master_handle_t; - -/*! @brief Slave handle type */ -typedef spi_master_handle_t spi_slave_handle_t; - -/*! @brief SPI master callback for finished transmit */ -typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI slave callback for finished transmit */ -typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI transfer handle structure */ -struct _spi_master_handle -{ - uint8_t *volatile txData; /*!< Transfer buffer */ - uint8_t *volatile rxData; /*!< Receive buffer */ - volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */ - volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */ - volatile size_t toReceiveCount; /*!< Receive data remaining in bytes */ - size_t totalByteCount; /*!< A number of transfer bytes */ - volatile uint32_t state; /*!< SPI internal state */ - spi_master_callback_t callback; /*!< SPI callback */ - void *userData; /*!< Callback parameter */ - uint8_t dataWidth; /*!< Width of the data [Valid values: 1 to 16] */ - uint8_t sselNum; /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */ - uint32_t configFlags; /*!< Additional option to control transfer */ - spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ -}; - -#if defined(__cplusplus) -extern "C" { -#endif -/******************************************************************************* - * API - ******************************************************************************/ - -/*! @brief Returns instance number for SPI peripheral base address. */ -uint32_t SPI_GetInstance(SPI_Type *base); - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Sets the SPI master configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). - * User may use the initialized structure unchanged in SPI_MasterInit(), or modify - * some fields of the structure before calling SPI_MasterInit(). After calling this API, - * the master is ready to transfer. - * Example: - @code - spi_master_config_t config; - SPI_MasterGetDefaultConfig(&config); - @endcode - * - * @param config pointer to master config structure - */ -void SPI_MasterGetDefaultConfig(spi_master_config_t *config); - -/*! - * @brief Initializes the SPI with master configuration. - * - * The configuration structure can be filled by user from scratch, or be set with default - * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. - * Example - @code - spi_master_config_t config = { - .baudRate_Bps = 400000, - ... - }; - SPI_MasterInit(SPI0, &config); - @endcode - * - * @param base SPI base pointer - * @param config pointer to master configuration structure - * @param srcClock_Hz Source clock frequency. - */ -status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Sets the SPI slave configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). - * Modify some fields of the structure before calling SPI_SlaveInit(). - * Example: - @code - spi_slave_config_t config; - SPI_SlaveGetDefaultConfig(&config); - @endcode - * - * @param config pointer to slave configuration structure - */ -void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config); - -/*! - * @brief Initializes the SPI with slave configuration. - * - * The configuration structure can be filled by user from scratch or be set with - * default values by SPI_SlaveGetDefaultConfig(). - * After calling this API, the slave is ready to transfer. - * Example - @code - spi_slave_config_t config = { - .polarity = flexSPIClockPolarity_ActiveHigh; - .phase = flexSPIClockPhase_FirstEdge; - .direction = flexSPIMsbFirst; - ... - }; - SPI_SlaveInit(SPI0, &config); - @endcode - * - * @param base SPI base pointer - * @param config pointer to slave configuration structure - */ -status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config); - -/*! - * @brief De-initializes the SPI. - * - * Calling this API resets the SPI module, gates the SPI clock. - * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. - * - * @param base SPI base pointer - */ -void SPI_Deinit(SPI_Type *base); - -/*! - * @brief Enable or disable the SPI Master or Slave - * @param base SPI base pointer - * @param enable or disable ( true = enable, false = disable) - */ -static inline void SPI_Enable(SPI_Type *base, bool enable) -{ - if (enable) - { - base->CFG |= SPI_CFG_ENABLE_MASK; - } - else - { - base->CFG &= ~SPI_CFG_ENABLE_MASK; - } -} - -/*! @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the status flag. - * - * @param base SPI base pointer - * @return SPI Status, use status flag to AND @ref _spi_statusflags could get the related status. - */ -static inline uint32_t SPI_GetStatusFlags(SPI_Type *base) -{ - assert(NULL != base); - return base->FIFOSTAT; -} - -/*! @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the interrupt for the SPI. - * - * @param base SPI base pointer - * @param irqs SPI interrupt source. The parameter can be any combination of the following values: - * @arg kSPI_RxLvlIrq - * @arg kSPI_TxLvlIrq - */ -static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs) -{ - assert(NULL != base); - base->FIFOINTENSET = irqs; -} - -/*! - * @brief Disables the interrupt for the SPI. - * - * @param base SPI base pointer - * @param irqs SPI interrupt source. The parameter can be any combination of the following values: - * @arg kSPI_RxLvlIrq - * @arg kSPI_TxLvlIrq - */ -static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs) -{ - assert(NULL != base); - base->FIFOINTENCLR = irqs; -} - -/*! @} */ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Enables the DMA request from SPI txFIFO. - * - * @param base SPI base pointer - * @param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableTxDMA(SPI_Type *base, bool enable); - -/*! - * @brief Enables the DMA request from SPI rxFIFO. - * - * @param base SPI base pointer - * @param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableRxDMA(SPI_Type *base, bool enable); - -/*! @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Sets the baud rate for SPI transfer. This is only used in master. - * - * @param base SPI base pointer - * @param baudrate_Bps baud rate needed in Hz. - * @param srcClock_Hz SPI source clock frequency in Hz. - */ -status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Writes a data into the SPI data register. - * - * @param base SPI base pointer - * @param data needs to be write. - * @param configFlags transfer configuration options @ref spi_xfer_option_t - */ -void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags); - -/*! - * @brief Gets a data from the SPI data register. - * - * @param base SPI base pointer - * @return Data in the register. - */ -static inline uint32_t SPI_ReadData(SPI_Type *base) -{ - assert(NULL != base); - return base->FIFORD; -} - -/*! @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the SPI master handle. - * - * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback Callback function. - * @param userData User data. - */ -status_t SPI_MasterTransferCreateHandle(SPI_Type *base, - spi_master_handle_t *handle, - spi_master_callback_t callback, - void *userData); - -/*! - * @brief Transfers a block of data using a polling method. - * - * @param base SPI base pointer - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - */ -status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer); - -/*! - * @brief Performs a non-blocking SPI interrupt transfer. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer); - -/*! - * @brief Gets the master transfer count. - * - * This function gets the master transfer count. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * @param count The number of bytes transferred by using the non-blocking transaction. - * @return status of status_t. - */ -status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count); - -/*! - * @brief SPI master aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle); - -/*! - * @brief Interrupts the handler for the SPI. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle); - -/*! - * @brief Initializes the SPI slave handle. - * - * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback Callback function. - * @param userData User data. - */ -static inline status_t SPI_SlaveTransferCreateHandle(SPI_Type *base, - spi_slave_handle_t *handle, - spi_slave_callback_t callback, - void *userData) -{ - return SPI_MasterTransferCreateHandle(base, handle, callback, userData); -} - -/*! - * @brief Performs a non-blocking SPI slave interrupt transfer. - * - * @note The API returns immediately after the transfer initialization is finished. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer) -{ - return SPI_MasterTransferNonBlocking(base, handle, xfer); -} - -/*! - * @brief Gets the slave transfer count. - * - * This function gets the slave transfer count. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * @param count The number of bytes transferred by using the non-blocking transaction. - * @return status of status_t. - */ -static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count) -{ - return SPI_MasterTransferGetCount(base, (spi_master_handle_t*)handle, count); -} - -/*! - * @brief SPI slave aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state. - */ -static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle) -{ - SPI_MasterTransferAbort(base, (spi_master_handle_t*)handle); -} - -/*! - * @brief Interrupts a handler for the SPI slave. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_slave_handle_t structure which stores the transfer state - */ -static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle) -{ - SPI_MasterTransferHandleIRQ(base, handle); -} - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_SPI_H_*/ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spi_dma.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spi_dma.c deleted file mode 100644 index 4ac9007952a..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spi_dma.c +++ /dev/null @@ -1,411 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_spi_dma.h" - -/******************************************************************************* - * Definitons - ******************************************************************************/ -/*configFlags & (uint32_t)kSPI_FrameDelay ? (uint32_t)kSPI_FrameDelay : 0; - *fifowr |= xfer->configFlags & (uint32_t)kSPI_FrameAssert ? (uint32_t)kSPI_FrameAssert : 0; -} - -static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr) -{ - *fifowr |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(config->sselNum))); - /* set width of data - range asserted at entry */ - *fifowr |= SPI_FIFOWR_LEN(config->dataWidth); -} - -static void PrepareTxFIFO(uint32_t *fifo, uint32_t count, uint32_t ctrl) -{ - assert(!(fifo == NULL)); - if (fifo == NULL) - { - return; - } - /* CS deassert and CS delay are relevant only for last word */ - uint32_t tx_ctrl = ctrl & (~(SPI_FIFOWR_EOT_MASK | SPI_FIFOWR_EOF_MASK)); - uint32_t i = 0; - for (; i + 1 < count; i++) - { - fifo[i] = (fifo[i] & 0xFFFFU) | (tx_ctrl & 0xFFFF0000U); - } - if (i < count) - { - fifo[i] = (fifo[i] & 0xFFFFU) | (ctrl & 0xFFFF0000U); - } -} - -static void SPI_SetupDummy(uint32_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p) -{ - *dummy = SPI_DUMMYDATA; - XferToFifoWR(xfer, dummy); - SpiConfigToFifoWR(spi_config_p, dummy); -} - -status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle) -{ - int32_t instance = 0; - - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } - /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - instance = SPI_GetInstance(base); - - memset(handle, 0, sizeof(*handle)); - /* Set spi base to handle */ - handle->txHandle = txHandle; - handle->rxHandle = rxHandle; - handle->callback = callback; - handle->userData = userData; - - /* Set SPI state to idle */ - handle->state = kSPI_Idle; - - /* Set handle to global state */ - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - /* Install callback for Tx dma channel */ - DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]); - DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]); - - return kStatus_Success; -} - -status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) -{ - int32_t instance; - status_t result = kStatus_Success; - spi_config_t *spi_config_p; - - assert(!((NULL == handle) || (NULL == xfer))); - if ((NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - /* txData set and not aligned to sizeof(uint32_t) */ - assert(!((NULL != xfer->txData) && ((uint32_t)xfer->txData % sizeof(uint32_t)))); - if ((NULL != xfer->txData) && ((uint32_t)xfer->txData % sizeof(uint32_t))) - { - return kStatus_InvalidArgument; - } - /* rxData set and not aligned to sizeof(uint32_t) */ - assert(!((NULL != xfer->rxData) && ((uint32_t)xfer->rxData % sizeof(uint32_t)))); - if ((NULL != xfer->rxData) && ((uint32_t)xfer->rxData % sizeof(uint32_t))) - { - return kStatus_InvalidArgument; - } - /* byte size is zero or not aligned to sizeof(uint32_t) */ - assert(!((xfer->dataSize == 0) || (xfer->dataSize % sizeof(uint32_t)))); - if ((xfer->dataSize == 0) || (xfer->dataSize % sizeof(uint32_t))) - { - return kStatus_InvalidArgument; - } - /* cannot get instance from base address */ - instance = SPI_GetInstance(base); - assert(!(instance < 0)); - if (instance < 0) - { - return kStatus_InvalidArgument; - } - - /* Check if the device is busy */ - if (handle->state == kSPI_Busy) - { - return kStatus_SPI_Busy; - } - else - { - uint32_t tmp; - dma_transfer_config_t xferConfig = {0}; - spi_config_p = (spi_config_t *)SPI_GetConfig(base); - - handle->state = kStatus_SPI_Busy; - handle->transferSize = xfer->dataSize; - - /* receive */ - SPI_EnableRxDMA(base, true); - if (xfer->rxData) - { - DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, xfer->rxData, sizeof(uint32_t), xfer->dataSize, - kDMA_PeripheralToMemory, NULL); - } - else - { - DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, &s_rxDummy, sizeof(uint32_t), xfer->dataSize, - kDMA_StaticToStatic, NULL); - } - DMA_SubmitTransfer(handle->rxHandle, &xferConfig); - handle->rxInProgress = true; - DMA_StartTransfer(handle->rxHandle); - - /* transmit */ - SPI_EnableTxDMA(base, true); - if (xfer->txData) - { - tmp = 0; - XferToFifoWR(xfer, &tmp); - SpiConfigToFifoWR(spi_config_p, &tmp); - PrepareTxFIFO((uint32_t *)xfer->txData, xfer->dataSize / sizeof(uint32_t), tmp); - DMA_PrepareTransfer(&xferConfig, xfer->txData, (void *)&base->FIFOWR, sizeof(uint32_t), xfer->dataSize, - kDMA_MemoryToPeripheral, NULL); - DMA_SubmitTransfer(handle->txHandle, &xferConfig); - } - else - { - if ((xfer->configFlags & kSPI_FrameAssert) && (xfer->dataSize > sizeof(uint32_t))) - { - dma_xfercfg_t tmp_xfercfg = { 0 }; - tmp_xfercfg.valid = true; - tmp_xfercfg.swtrig = true; - tmp_xfercfg.intA = true; - tmp_xfercfg.byteWidth = sizeof(uint32_t); - tmp_xfercfg.srcInc = 0; - tmp_xfercfg.dstInc = 0; - tmp_xfercfg.transferCount = 1; - /* create chained descriptor to transmit last word */ - SPI_SetupDummy(&s_txDummy[instance].lastWord, xfer, spi_config_p); - DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord, - (uint32_t *)&base->FIFOWR, NULL); - /* use common API to setup first descriptor */ - SPI_SetupDummy(&s_txDummy[instance].word, NULL, spi_config_p); - DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR, sizeof(uint32_t), - xfer->dataSize - sizeof(uint32_t), kDMA_StaticToStatic, - &s_spi_descriptor_table[instance]); - /* disable interrupts for first descriptor - * to avoid calling callback twice */ - xferConfig.xfercfg.intA = false; - xferConfig.xfercfg.intB = false; - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - else - { - SPI_SetupDummy(&s_txDummy[instance].word, xfer, spi_config_p); - DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR, sizeof(uint32_t), - xfer->dataSize, kDMA_StaticToStatic, NULL); - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - } - handle->txInProgress = true; - DMA_StartTransfer(handle->txHandle); - } - - return result; -} - -static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) -{ - spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; - spi_dma_handle_t *spiHandle = privHandle->handle; - SPI_Type *base = privHandle->base; - - /* change the state */ - spiHandle->rxInProgress = false; - - /* All finished, call the callback */ - if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) - { - spiHandle->state = kSPI_Idle; - if (spiHandle->callback) - { - (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); - } - } -} - -static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) -{ - spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; - spi_dma_handle_t *spiHandle = privHandle->handle; - SPI_Type *base = privHandle->base; - - /* change the state */ - spiHandle->txInProgress = false; - - /* All finished, call the callback */ - if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) - { - spiHandle->state = kSPI_Idle; - if (spiHandle->callback) - { - (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); - } - } -} - -void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) -{ - assert(NULL != handle); - - /* Stop tx transfer first */ - DMA_AbortTransfer(handle->txHandle); - /* Then rx transfer */ - DMA_AbortTransfer(handle->rxHandle); - - /* Set the handle state */ - handle->txInProgress = false; - handle->rxInProgress = false; - handle->state = kSPI_Idle; -} - -status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != kSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - size_t bytes; - - bytes = DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel); - - *count = handle->transferSize - bytes; - - return kStatus_Success; -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spi_dma.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spi_dma.h deleted file mode 100644 index d4bdf8b16c7..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spi_dma.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_SPI_DMA_H_ -#define _FSL_SPI_DMA_H_ - -#include "fsl_dma.h" -#include "fsl_spi.h" - -/*! - * @addtogroup spi_dma_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -typedef struct _spi_dma_handle spi_dma_handle_t; - -/*! @brief SPI DMA callback called at the end of transfer. */ -typedef void (*spi_dma_callback_t)(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI DMA transfer handle, users should not touch the content of the handle.*/ -struct _spi_dma_handle -{ - volatile bool txInProgress; /*!< Send transfer finished */ - volatile bool rxInProgress; /*!< Receive transfer finished */ - dma_handle_t *txHandle; /*!< DMA handler for SPI send */ - dma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ - uint8_t bytesPerFrame; /*!< Bytes in a frame for SPI tranfer */ - spi_dma_callback_t callback; /*!< Callback for SPI DMA transfer */ - void *userData; /*!< User Data for SPI DMA callback */ - uint32_t state; /*!< Internal state of SPI DMA transfer */ - size_t transferSize; /*!< Bytes need to be transfer */ -}; - -/******************************************************************************* - * APIs - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name DMA Transactional - * @{ - */ - -/*! - * @brief Initialize the SPI master DMA handle. - * - * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback User callback function called at the end of a transfer. - * @param userData User data for callback. - * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle); - -/*! - * @brief Perform a non-blocking SPI transfer using DMA. - * - * @note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - * @param xfer Pointer to dma transfer structure. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer); - -/*! - * @brief Initialize the SPI slave DMA handle. - * - * This function initializes the SPI slave DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback User callback function called at the end of a transfer. - * @param userData User data for callback. - * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -static inline status_t SPI_SlaveTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle) -{ - return SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle); -} - -/*! - * @brief Perform a non-blocking SPI transfer using DMA. - * - * @note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - * @param xfer Pointer to dma transfer structure. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -static inline status_t SPI_SlaveTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) -{ - return SPI_MasterTransferDMA(base, handle, xfer); -} - -/*! - * @brief Abort a SPI transfer using DMA. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - */ -void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle); - -/*! - * @brief Gets the master DMA transfer remaining bytes. - * - * This function gets the master DMA transfer remaining bytes. - * - * @param base SPI peripheral base address. - * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * @param count A number of bytes transferred by the non-blocking transaction. - * @return status of status_t. - */ -status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count); - -/*! - * @brief Abort a SPI transfer using DMA. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - */ -static inline void SPI_SlaveTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) -{ - SPI_MasterTransferAbortDMA(base, handle); -} - -/*! - * @brief Gets the slave DMA transfer remaining bytes. - * - * This function gets the slave DMA transfer remaining bytes. - * - * @param base SPI peripheral base address. - * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * @param count A number of bytes transferred by the non-blocking transaction. - * @return status of status_t. - */ -static inline status_t SPI_SlaveTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) -{ - return SPI_MasterTransferGetCountDMA(base, handle, count); -} - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_SPI_DMA_H_*/ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spifi.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spifi.c deleted file mode 100644 index 60176a2c9c2..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spifi.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_spifi.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get the SPIFI instance from peripheral base address. - * - * @param base SPIFI peripheral base address. - * @return SPIFI instance. - */ -uint32_t SPIFI_GetInstance(SPIFI_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* Array of SPIFI peripheral base address. */ -static SPIFI_Type *const s_spifiBases[] = SPIFI_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of SPIFI clock name. */ -static const clock_ip_name_t s_spifiClock[] = SPIFI_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -uint32_t SPIFI_GetInstance(SPIFI_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_spifiBases); instance++) - { - if (s_spifiBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_spifiBases)); - - return instance; -} - -void SPIFI_GetDefaultConfig(spifi_config_t *config) -{ - config->timeout = 0xFFFFU; - config->csHighTime = 0xFU; - config->disablePrefetch = false; - config->disableCachePrefech = false; - config->isFeedbackClock = true; - config->spiMode = kSPIFI_SPISckLow; - config->isReadFullClockCycle = false; - config->dualMode = kSPIFI_QuadMode; -} - -void SPIFI_Init(SPIFI_Type *base, const spifi_config_t *config) -{ - assert(config); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the SAI clock */ - CLOCK_EnableClock(s_spifiClock[SPIFI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the Command register */ - SPIFI_ResetCommand(base); - - /* Set time delay parameter */ - base->CTRL = SPIFI_CTRL_TIMEOUT(config->timeout) | SPIFI_CTRL_CSHIGH(config->csHighTime) | - SPIFI_CTRL_D_PRFTCH_DIS(config->disablePrefetch) | SPIFI_CTRL_MODE3(config->spiMode) | - SPIFI_CTRL_PRFTCH_DIS(config->disableCachePrefech) | SPIFI_CTRL_DUAL(config->dualMode) | - SPIFI_CTRL_RFCLK(config->isReadFullClockCycle) | SPIFI_CTRL_FBCLK(config->isFeedbackClock); -} - -void SPIFI_Deinit(SPIFI_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the SAI clock */ - CLOCK_DisableClock(s_spifiClock[SPIFI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void SPIFI_SetCommand(SPIFI_Type *base, spifi_command_t *cmd) -{ - /* Wait for the CMD and MCINT flag all be 0 */ - while (SPIFI_GetStatusFlag(base) & (SPIFI_STAT_MCINIT_MASK | SPIFI_STAT_CMD_MASK)) - { - } - base->CMD = SPIFI_CMD_DATALEN(cmd->dataLen) | SPIFI_CMD_POLL(cmd->isPollMode) | SPIFI_CMD_DOUT(cmd->direction) | - SPIFI_CMD_INTLEN(cmd->intermediateBytes) | SPIFI_CMD_FIELDFORM(cmd->format) | - SPIFI_CMD_FRAMEFORM(cmd->type) | SPIFI_CMD_OPCODE(cmd->opcode); - - /* Wait for the command written */ - while ((base->STAT & SPIFI_STAT_CMD_MASK) == 0U) - { - } -} - -void SPIFI_SetMemoryCommand(SPIFI_Type *base, spifi_command_t *cmd) -{ - /* Wait for the CMD and MCINT flag all be 0 */ - while (SPIFI_GetStatusFlag(base) & (SPIFI_STAT_MCINIT_MASK | SPIFI_STAT_CMD_MASK)) - { - } - - base->MCMD = SPIFI_MCMD_POLL(0U) | SPIFI_MCMD_DOUT(0U) | SPIFI_MCMD_INTLEN(cmd->intermediateBytes) | - SPIFI_MCMD_FIELDFORM(cmd->format) | SPIFI_MCMD_FRAMEFORM(cmd->type) | SPIFI_MCMD_OPCODE(cmd->opcode); -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spifi.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spifi.h deleted file mode 100644 index 39890b9fe5c..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spifi.h +++ /dev/null @@ -1,379 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_SPIFI_H_ -#define _FSL_SPIFI_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup spifi - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SPIFI driver version 2.0.0. */ -#define FSL_SPIFI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @brief Status structure of SPIFI.*/ -enum _status_t -{ - kStatus_SPIFI_Idle = MAKE_STATUS(kStatusGroup_SPIFI, 0), /*!< SPIFI is in idle state */ - kStatus_SPIFI_Busy = MAKE_STATUS(kStatusGroup_SPIFI, 1), /*!< SPIFI is busy */ - kStatus_SPIFI_Error = MAKE_STATUS(kStatusGroup_SPIFI, 2), /*!< Error occurred during SPIFI transfer */ -}; - -/*! @brief SPIFI interrupt source */ -typedef enum _spifi_interrupt_enable -{ - kSPIFI_CommandFinishInterruptEnable = SPIFI_CTRL_INTEN_MASK, /*!< Interrupt while command finished */ -} spifi_interrupt_enable_t; - -/*! @brief SPIFI SPI mode select */ -typedef enum _spifi_spi_mode -{ - kSPIFI_SPISckLow = 0x0U, /*!< SCK low after last bit of command, keeps low while CS high */ - kSPIFI_SPISckHigh = 0x1U /*!< SCK high after last bit of command and while CS high */ -} spifi_spi_mode_t; - -/*! @brief SPIFI dual mode select */ -typedef enum _spifi_dual_mode -{ - kSPIFI_QuadMode = 0x0U, /*!< SPIFI uses IO3:0 */ - kSPIFI_DualMode = 0x1U /*!< SPIFI uses IO1:0 */ -} spifi_dual_mode_t; - -/*! @brief SPIFI data direction */ -typedef enum _spifi_data_direction -{ - kSPIFI_DataInput = 0x0U, /*!< Data input from serial flash. */ - kSPIFI_DataOutput = 0x1U /*!< Data output to serial flash. */ -} spifi_data_direction_t; - -/*! @brief SPIFI command opcode format */ -typedef enum _spifi_command_format -{ - kSPIFI_CommandAllSerial = 0x0, /*!< All fields of command are serial. */ - kSPIFI_CommandDataQuad = 0x1U, /*!< Only data field is dual/quad, others are serial. */ - kSPIFI_CommandOpcodeSerial = 0x2U, /*!< Only opcode field is serial, others are quad/dual. */ - kSPIFI_CommandAllQuad = 0x3U /*!< All fields of command are dual/quad mode. */ -} spifi_command_format_t; - -/*! @brief SPIFI command type */ -typedef enum _spifi_command_type -{ - kSPIFI_CommandOpcodeOnly = 0x1U, /*!< Command only have opcode, no address field */ - kSPIFI_CommandOpcodeAddrOneByte = 0x2U, /*!< Command have opcode and also one byte address field */ - kSPIFI_CommandOpcodeAddrTwoBytes = 0x3U, /*!< Command have opcode and also two bytes address field */ - kSPIFI_CommandOpcodeAddrThreeBytes = 0x4U, /*!< Command have opcode and also three bytes address field. */ - kSPIFI_CommandOpcodeAddrFourBytes = 0x5U, /*!< Command have opcode and also four bytes address field */ - kSPIFI_CommandNoOpcodeAddrThreeBytes = 0x6U, /*!< Command have no opcode and three bytes address field */ - kSPIFI_CommandNoOpcodeAddrFourBytes = 0x7U /*!< Command have no opcode and four bytes address field */ -} spifi_command_type_t; - -/*! @brief SPIFI status flags */ -enum _spifi_status_flags -{ - kSPIFI_MemoryCommandWriteFinished = SPIFI_STAT_MCINIT_MASK, /*!< Memory command write finished */ - kSPIFI_CommandWriteFinished = SPIFI_STAT_CMD_MASK, /*!< Command write finished */ - kSPIFI_InterruptRequest = SPIFI_STAT_INTRQ_MASK /*!< CMD flag from 1 to 0, means command execute finished */ -}; - -/*! @brief SPIFI command structure */ -typedef struct _spifi_command -{ - uint16_t dataLen; /*!< How many data bytes are needed in this command. */ - bool isPollMode; /*!< For command need to read data from serial flash */ - spifi_data_direction_t direction; /*!< Data direction of this command. */ - uint8_t intermediateBytes; /*!< How many intermediate bytes needed */ - spifi_command_format_t format; /*!< Command format */ - spifi_command_type_t type; /*!< Command type */ - uint8_t opcode; /*!< Command opcode value */ -} spifi_command_t; - -/*! - * @brief SPIFI region configuration structure. - */ -typedef struct _spifi_config -{ - uint16_t timeout; /*!< SPI transfer timeout, the unit is SCK cycles */ - uint8_t csHighTime; /*!< CS high time cycles */ - bool disablePrefetch; /*!< True means SPIFI will not attempt a speculative prefetch. */ - bool disableCachePrefech; /*!< Disable prefetch of cache line */ - bool isFeedbackClock; /*!< Is data sample uses feedback clock. */ - spifi_spi_mode_t spiMode; /*!< SPIFI spi mode select */ - bool isReadFullClockCycle; /*!< If enable read full clock cycle. */ - spifi_dual_mode_t dualMode; /*!< SPIFI dual mode, dual or quad. */ -} spifi_config_t; - -/*! @brief Transfer structure for SPIFI */ -typedef struct _spifi_transfer -{ - uint8_t *data; /*!< Pointer to data to transmit */ - size_t dataSize; /*!< Bytes to be transmit */ -} spifi_transfer_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the SPIFI with the user configuration structure. - * - * This function configures the SPIFI module with the user-defined configuration. - * - * @param base SPIFI peripheral base address. - * @param config The pointer to the configuration structure. - */ -void SPIFI_Init(SPIFI_Type *base, const spifi_config_t *config); - -/*! - * @brief Get SPIFI default configure settings. - * - * @param config SPIFI config structure pointer. - */ -void SPIFI_GetDefaultConfig(spifi_config_t *config); - -/*! - * @brief Deinitializes the SPIFI regions. - * - * @param base SPIFI peripheral base address. - */ -void SPIFI_Deinit(SPIFI_Type *base); - -/* @}*/ - -/*! - * @name Basic Control Operations - * @{ - */ - -/*! - * @brief Set SPIFI flash command. - * - * @param base SPIFI peripheral base address. - * @param cmd SPIFI command structure pointer. - */ -void SPIFI_SetCommand(SPIFI_Type *base, spifi_command_t *cmd); - -/*! - * @brief Set SPIFI command address. - * - * @param base SPIFI peripheral base address. - * @param addr Address value for the command. - */ -static inline void SPIFI_SetCommandAddress(SPIFI_Type *base, uint32_t addr) -{ - base->ADDR = addr; -} - -/*! - * @brief Set SPIFI intermediate data. - * - * Before writing a command wihch needs specific intermediate value, users shall call this function to write it. - * The main use of this function for current serial flash is to select no-opcode mode and cancelling this mode. As - * dummy cycle do not care about the value, no need to call this function. - * - * @param base SPIFI peripheral base address. - * @param val Intermediate data. - */ -static inline void SPIFI_SetIntermediateData(SPIFI_Type *base, uint32_t val) -{ - base->IDATA = val; -} - -/*! - * @brief Set SPIFI Cache limit value. - * - * SPIFI includes caching of prevously-accessed data to improve performance. Software can write an address to this - * function, to prevent such caching at and above the address. - * - * @param base SPIFI peripheral base address. - * @param val Zero-based upper limit of cacheable memory. - */ -static inline void SPIFI_SetCacheLimit(SPIFI_Type *base, uint32_t val) -{ - base->CLIMIT = val; -} - -/*! - * @brief Reset the command field of SPIFI. - * - * This function is used to abort the current command or memory mode. - * - * @param base SPIFI peripheral base address. - */ -static inline void SPIFI_ResetCommand(SPIFI_Type *base) -{ - base->STAT = SPIFI_STAT_RESET_MASK; - /* Wait for the RESET flag cleared by HW */ - while (base->STAT & SPIFI_STAT_RESET_MASK) - { - } -} - -/*! - * @brief Set SPIFI flash AHB read command. - * - * Call this function means SPIFI enters to memory mode, while users need to use command, a SPIFI_ResetCommand shall - * be called. - * - * @param base SPIFI peripheral base address. - * @param cmd SPIFI command structure pointer. - */ -void SPIFI_SetMemoryCommand(SPIFI_Type *base, spifi_command_t *cmd); - -/*! - * @brief Enable SPIFI interrupt. - * - * The interrupt is triggered only in command mode, and it means the command now is finished. - * - * @param base SPIFI peripheral base address. - * @param mask SPIFI interrupt enable mask. It is a logic OR of members the - * enumeration :: spifi_interrupt_enable_t - */ -static inline void SPIFI_EnableInterrupt(SPIFI_Type *base, uint32_t mask) -{ - base->CTRL |= mask; -} - -/*! - * @brief Disable SPIFI interrupt. - * - * The interrupt is triggered only in command mode, and it means the command now is finished. - * - * @param base SPIFI peripheral base address. - * @param mask SPIFI interrupt enable mask. It is a logic OR of members the - * enumeration :: spifi_interrupt_enable_t - */ -static inline void SPIFI_DisableInterrupt(SPIFI_Type *base, uint32_t mask) -{ - base->CTRL &= ~mask; -} - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Get the status of all interrupt flags for SPIFI. - * - * @param base SPIFI peripheral base address. - * @return SPIFI flag status - */ -static inline uint32_t SPIFI_GetStatusFlag(SPIFI_Type *base) -{ - return base->STAT; -} - -/* @}*/ - -/*! - * @brief Enable or disable DMA request for SPIFI. - * - * @param base SPIFI peripheral base address. - * @param enable True means enable DMA and false means disable DMA. - */ -static inline void SPIFI_EnableDMA(SPIFI_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= SPIFI_CTRL_DMAEN_MASK; - } - else - { - base->CTRL &= ~SPIFI_CTRL_DMAEN_MASK; - } -} - -/*! - * @brief Gets the SPIFI data register address. - * - * This API is used to provide a transfer address for the SPIFI DMA transfer configuration. - * - * @param base SPIFI base pointer - * @return data register address - */ -static inline uint32_t SPIFI_GetDataRegisterAddress(SPIFI_Type *base) -{ - return (uint32_t)(&(base->DATA)); -} - -/*! - * @brief Write a word data in address of SPIFI. - * - * Users can write a page or at least a word data into SPIFI address. - * - * @param base SPIFI peripheral base address. - * @param data Data need be write. - */ -static inline void SPIFI_WriteData(SPIFI_Type *base, uint32_t data) -{ - base->DATA = data; -} - -/*! - * @brief Read data from serial flash. - * - * Users should notice before call this function, the data length field in command register shall larger - * than 4, otherwise a hardfault will happen. - * - * @param base SPIFI peripheral base address. - * @return Data input from flash. - */ -static inline uint32_t SPIFI_ReadData(SPIFI_Type *base) -{ - return base->DATA; -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_SPIFI_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spifi_dma.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spifi_dma.c deleted file mode 100644 index 6fcafb2136a..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spifi_dma.c +++ /dev/null @@ -1,313 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_spifi_dma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*base, spifiPrivateHandle->handle); - - if (spifiPrivateHandle->handle->callback) - { - spifiPrivateHandle->handle->callback(spifiPrivateHandle->base, spifiPrivateHandle->handle, - kStatus_SPIFI_Idle, spifiPrivateHandle->handle->userData); - } - } -} - -static void SPIFI_ReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode) -{ - spifi_dma_private_handle_t *spifiPrivateHandle = (spifi_dma_private_handle_t *)param; - - /* Avoid warning for unused parameters. */ - handle = handle; - intmode = intmode; - - if (transferDone) - { - /* Disable transfer. */ - SPIFI_TransferAbortReceiveDMA(spifiPrivateHandle->base, spifiPrivateHandle->handle); - - if (spifiPrivateHandle->handle->callback) - { - spifiPrivateHandle->handle->callback(spifiPrivateHandle->base, spifiPrivateHandle->handle, - kStatus_SPIFI_Idle, spifiPrivateHandle->handle->userData); - } - } -} - -void SPIFI_TransferTxCreateHandleDMA(SPIFI_Type *base, - spifi_dma_handle_t *handle, - spifi_dma_callback_t callback, - void *userData, - dma_handle_t *dmaHandle) -{ - assert(handle); - - uint32_t instance = SPIFI_GetInstance(base); - - s_dmaPrivateHandle[instance][0].base = base; - s_dmaPrivateHandle[instance][0].handle = handle; - - memset(handle, 0, sizeof(*handle)); - - handle->state = kSPIFI_Idle; - handle->dmaHandle = dmaHandle; - - handle->callback = callback; - handle->userData = userData; - - /* Configure TX dma callback */ - DMA_SetCallback(handle->dmaHandle, SPIFI_SendDMACallback, &s_dmaPrivateHandle[instance][0]); -} - -void SPIFI_TransferRxCreateHandleDMA(SPIFI_Type *base, - spifi_dma_handle_t *handle, - spifi_dma_callback_t callback, - void *userData, - dma_handle_t *dmaHandle) -{ - assert(handle); - - uint32_t instance = SPIFI_GetInstance(base); - - s_dmaPrivateHandle[instance][1].base = base; - s_dmaPrivateHandle[instance][1].handle = handle; - - memset(handle, 0, sizeof(*handle)); - - handle->state = kSPIFI_Idle; - handle->dmaHandle = dmaHandle; - - handle->callback = callback; - handle->userData = userData; - - /* Configure RX dma callback */ - DMA_SetCallback(handle->dmaHandle, SPIFI_ReceiveDMACallback, &s_dmaPrivateHandle[instance][1]); -} - -status_t SPIFI_TransferSendDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, spifi_transfer_t *xfer) -{ - assert(handle && (handle->dmaHandle)); - - dma_transfer_config_t xferConfig; - status_t status; - - /* If previous TX not finished. */ - if (kSPIFI_BusBusy == handle->state) - { - status = kStatus_SPIFI_Busy; - } - else - { - handle->state = kSPIFI_BusBusy; - - /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, xfer->data, (void *)SPIFI_GetDataRegisterAddress(base), sizeof(uint32_t), - xfer->dataSize, kDMA_MemoryToPeripheral, NULL); - - /* Submit transfer. */ - DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - DMA_StartTransfer(handle->dmaHandle); - - /* Enable SPIFI TX DMA. */ - SPIFI_EnableDMA(base, true); - - status = kStatus_Success; - } - - return status; -} - -status_t SPIFI_TransferReceiveDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, spifi_transfer_t *xfer) -{ - assert(handle && (handle->dmaHandle)); - - dma_transfer_config_t xferConfig; - status_t status; - - /* If previous TX not finished. */ - if (kSPIFI_BusBusy == handle->state) - { - status = kStatus_SPIFI_Busy; - } - else - { - handle->state = kSPIFI_BusBusy; - - /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, (void *)SPIFI_GetDataRegisterAddress(base), xfer->data, sizeof(uint32_t), - xfer->dataSize, kDMA_PeripheralToMemory, NULL); - - /* Submit transfer. */ - DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - DMA_StartTransfer(handle->dmaHandle); - - /* Enable SPIFI TX DMA. */ - SPIFI_EnableDMA(base, true); - - status = kStatus_Success; - } - - return status; -} - -void SPIFI_TransferAbortSendDMA(SPIFI_Type *base, spifi_dma_handle_t *handle) -{ - assert(handle && (handle->dmaHandle)); - - /* Disable SPIFI TX DMA. */ - SPIFI_EnableDMA(base, false); - - /* Stop transfer. */ - DMA_AbortTransfer(handle->dmaHandle); - - handle->state = kSPIFI_Idle; -} - -void SPIFI_TransferAbortReceiveDMA(SPIFI_Type *base, spifi_dma_handle_t *handle) -{ - assert(handle && (handle->dmaHandle)); - - /* Disable SPIFI RX DMA. */ - SPIFI_EnableDMA(base, false); - - /* Stop transfer. */ - DMA_AbortTransfer(handle->dmaHandle); - - handle->state = kSPIFI_Idle; -} - -status_t SPIFI_TransferGetSendCountDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, size_t *count) -{ - assert(handle); - - status_t status = kStatus_Success; - - if (handle->state != kSPIFI_BusBusy) - { - status = kStatus_NoTransferInProgress; - } - else - { - *count = handle->transferSize - DMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel); - } - - return status; -} - -status_t SPIFI_TransferGetReceiveCountDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, size_t *count) -{ - assert(handle); - - status_t status = kStatus_Success; - - if (handle->state != kSPIFI_BusBusy) - { - status = kStatus_NoTransferInProgress; - } - else - { - *count = handle->transferSize - DMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel); - } - - return status; -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spifi_dma.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spifi_dma.h deleted file mode 100644 index 89b3a09b6a1..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spifi_dma.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_SPIFI_DMA_H_ -#define _FSL_SPIFI_DMA_H_ - -#include "fsl_dma.h" -#include "fsl_spifi.h" - -/*! - * @addtogroup spifi - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -typedef struct _spifi_dma_handle spifi_dma_handle_t; - -/*! @brief SPIFI DMA transfer callback function for finish and error */ -typedef void (*spifi_dma_callback_t)(SPIFI_Type *base, spifi_dma_handle_t *handle, status_t status, void *userData); - -/*! @brief SPIFI DMA transfer handle, users should not touch the content of the handle.*/ -struct _spifi_dma_handle -{ - dma_handle_t *dmaHandle; /*!< DMA handler for SPIFI send */ - size_t transferSize; /*!< Bytes need to transfer. */ - uint32_t state; /*!< Internal state for SPIFI DMA transfer */ - spifi_dma_callback_t callback; /*!< Callback for users while transfer finish or error occurred */ - void *userData; /*!< User callback parameter */ -}; - -/******************************************************************************* - * APIs - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name DMA Transactional - * @{ - */ - -/*! - * @brief Initializes the SPIFI handle for send which is used in transactional functions and set the callback. - * - * @param base SPIFI peripheral base address - * @param handle Pointer to spifi_dma_handle_t structure - * @param callback SPIFI callback, NULL means no callback. - * @param userData User callback function data. - * @param rxDmaHandle User requested DMA handle for DMA transfer - */ -void SPIFI_TransferTxCreateHandleDMA(SPIFI_Type *base, - spifi_dma_handle_t *handle, - spifi_dma_callback_t callback, - void *userData, - dma_handle_t *dmaHandle); - -/*! - * @brief Initializes the SPIFI handle for receive which is used in transactional functions and set the callback. - * - * @param base SPIFI peripheral base address - * @param handle Pointer to spifi_dma_handle_t structure - * @param callback SPIFI callback, NULL means no callback. - * @param userData User callback function data. - * @param rxDmaHandle User requested DMA handle for DMA transfer - */ -void SPIFI_TransferRxCreateHandleDMA(SPIFI_Type *base, - spifi_dma_handle_t *handle, - spifi_dma_callback_t callback, - void *userData, - dma_handle_t *dmaHandle); - -/*! - * @brief Transfers SPIFI data using an DMA non-blocking method. - * - * This function writes data to the SPIFI transmit FIFO. This function is non-blocking. - * @param base Pointer to QuadSPI Type. - * @param handle Pointer to spifi_dma_handle_t structure - * @param xfer SPIFI transfer structure. - */ -status_t SPIFI_TransferSendDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, spifi_transfer_t *xfer); - -/*! - * @brief Receives data using an DMA non-blocking method. - * - * This function receive data from the SPIFI receive buffer/FIFO. This function is non-blocking. - * @param base Pointer to QuadSPI Type. - * @param handle Pointer to spifi_dma_handle_t structure - * @param xfer SPIFI transfer structure. - */ -status_t SPIFI_TransferReceiveDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, spifi_transfer_t *xfer); - -/*! - * @brief Aborts the sent data using DMA. - * - * This function aborts the sent data using DMA. - * - * @param base SPIFI peripheral base address. - * @param handle Pointer to spifi_dma_handle_t structure - */ -void SPIFI_TransferAbortSendDMA(SPIFI_Type *base, spifi_dma_handle_t *handle); - -/*! - * @brief Aborts the receive data using DMA. - * - * This function abort receive data which using DMA. - * - * @param base SPIFI peripheral base address. - * @param handle Pointer to spifi_dma_handle_t structure - */ -void SPIFI_TransferAbortReceiveDMA(SPIFI_Type *base, spifi_dma_handle_t *handle); - -/*! - * @brief Gets the transferred counts of send. - * - * @param base Pointer to QuadSPI Type. - * @param handle Pointer to spifi_dma_handle_t structure. - * @param count Bytes sent. - * @retval kStatus_Success Succeed get the transfer count. - * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. - */ -status_t SPIFI_TransferGetSendCountDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, size_t *count); - -/*! - * @brief Gets the status of the receive transfer. - * - * @param base Pointer to QuadSPI Type. - * @param handle Pointer to spifi_dma_handle_t structure - * @param count Bytes received. - * @retval kStatus_Success Succeed get the transfer count. - * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. - */ -status_t SPIFI_TransferGetReceiveCountDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, size_t *count); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/* @} */ - -#endif /* _FSL_SPIFI_DMA_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_usart.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_usart.c deleted file mode 100644 index 7e276d3091b..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_usart.c +++ /dev/null @@ -1,708 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_usart.h" -#include "fsl_device_registers.h" -#include "fsl_flexcomm.h" - -enum _usart_transfer_states -{ - kUSART_TxIdle, /* TX idle. */ - kUSART_TxBusy, /* TX busy. */ - kUSART_RxIdle, /* RX idle. */ - kUSART_RxBusy /* RX busy. */ -}; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief IRQ name array */ -static const IRQn_Type s_usartIRQ[] = USART_IRQS; - -/*! @brief Array to map USART instance number to base address. */ -static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Get the index corresponding to the USART */ -uint32_t USART_GetInstance(USART_Type *base) -{ - int i; - - for (i = 0; i < FSL_FEATURE_SOC_USART_COUNT; i++) - { - if ((uint32_t)base == s_usartBaseAddrs[i]) - { - return i; - } - } - - assert(false); - return 0; -} - -static size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) -{ - size_t size; - - /* Check arguments */ - assert(NULL != handle); - - if (handle->rxRingBufferTail > handle->rxRingBufferHead) - { - size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); - } - else - { - size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); - } - return size; -} - -static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle) -{ - bool full; - - /* Check arguments */ - assert(NULL != handle); - - if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) - { - full = true; - } - else - { - full = false; - } - return full; -} - -void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) -{ - /* Check arguments */ - assert(NULL != base); - assert(NULL != handle); - assert(NULL != ringBuffer); - - /* Setup the ringbuffer address */ - handle->rxRingBuffer = ringBuffer; - handle->rxRingBufferSize = ringBufferSize; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; - /* ring buffer is ready we can start receiving data */ - base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -} - -void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) -{ - /* Check arguments */ - assert(NULL != base); - assert(NULL != handle); - - if (handle->rxState == kUSART_RxIdle) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK; - } - handle->rxRingBuffer = NULL; - handle->rxRingBufferSize = 0U; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; -} - -status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz) -{ - int result; - - /* check arguments */ - assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz))); - if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* initialize flexcomm to USART mode */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART); - if (kStatus_Success != result) - { - return result; - } - - /* setup baudrate */ - result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - - if (config->enableTx) - { - /* empty and enable txFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK; - /* setup trigger level */ - base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK); - base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark); - /* enable trigger interrupt */ - base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK; - } - - /* empty and enable rxFIFO */ - if (config->enableRx) - { - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK; - /* setup trigger level */ - base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK); - base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable trigger interrupt */ - base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK; - } - /* setup configuration and enable USART */ - base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | - USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | USART_CFG_ENABLE_MASK; - return kStatus_Success; -} - -void USART_Deinit(USART_Type *base) -{ - /* Check arguments */ - assert(NULL != base); - while (!(base->STAT & USART_STAT_TXIDLE_MASK)) - { - } - /* Disable interrupts, disable dma requests, disable peripheral */ - base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK | - USART_FIFOINTENCLR_RXLVL_MASK; - base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK); - base->CFG &= ~(USART_CFG_ENABLE_MASK); -} - -void USART_GetDefaultConfig(usart_config_t *config) -{ - /* Check arguments */ - assert(NULL != config); - - /* Set always all members ! */ - config->baudRate_Bps = 115200U; - config->parityMode = kUSART_ParityDisabled; - config->stopBitCount = kUSART_OneStopBit; - config->bitCountPerChar = kUSART_8BitsPerChar; - config->loopback = false; - config->enableRx = false; - config->enableTx = false; - config->txWatermark = kUSART_TxFifo0; - config->rxWatermark = kUSART_RxFifo1; -} - -status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) -{ - uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1; - uint32_t osrval, brgval, diff, baudrate; - - /* check arguments */ - assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))); - if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* - * Smaller values of OSR can make the sampling position within a data bit less accurate and may - * potentially cause more noise errors or incorrect data. - */ - for (osrval = best_osrval; osrval >= 8; osrval--) - { - brgval = (srcClock_Hz / ((osrval + 1) * baudrate_Bps)) - 1; - if (brgval > 0xFFFF) - { - continue; - } - baudrate = srcClock_Hz / ((osrval + 1) * (brgval + 1)); - diff = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate; - if (diff < best_diff) - { - best_diff = diff; - best_osrval = osrval; - best_brgval = brgval; - } - } - - /* value over range */ - if (best_brgval > 0xFFFF) - { - return kStatus_USART_BaudrateNotSupport; - } - - base->OSR = best_osrval; - base->BRG = best_brgval; - return kStatus_Success; -} - -void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) -{ - /* Check arguments */ - assert(!((NULL == base) || (NULL == data))); - if ((NULL == base) || (NULL == data)) - { - return; - } - /* Check whether txFIFO is enabled */ - if (!(base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK)) - { - return; - } - for (; length > 0; length--) - { - /* Loop until txFIFO get some space for new data */ - while (!(base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) - { - } - base->FIFOWR = *data; - data++; - } - /* Wait to finish transfer */ - while (!(base->STAT & USART_STAT_TXIDLE_MASK)) - { - } -} - -status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) -{ - uint32_t status; - - /* check arguments */ - assert(!((NULL == base) || (NULL == data))); - if ((NULL == base) || (NULL == data)) - { - return kStatus_InvalidArgument; - } - - /* Check whether rxFIFO is enabled */ - if (!(base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK)) - { - return kStatus_Fail; - } - for (; length > 0; length--) - { - /* loop until rxFIFO have some data to read */ - while (!(base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) - { - } - /* check receive status */ - status = base->STAT; - if (status & USART_STAT_FRAMERRINT_MASK) - { - base->STAT |= USART_STAT_FRAMERRINT_MASK; - return kStatus_USART_FramingError; - } - if (status & USART_STAT_PARITYERRINT_MASK) - { - base->STAT |= USART_STAT_PARITYERRINT_MASK; - return kStatus_USART_ParityError; - } - if (status & USART_STAT_RXNOISEINT_MASK) - { - base->STAT |= USART_STAT_RXNOISEINT_MASK; - return kStatus_USART_NoiseError; - } - /* check rxFIFO status */ - if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) - { - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; - return kStatus_USART_RxError; - } - - *data = base->FIFORD; - data++; - } - return kStatus_Success; -} - -status_t USART_TransferCreateHandle(USART_Type *base, - usart_handle_t *handle, - usart_transfer_callback_t callback, - void *userData) -{ - int32_t instance = 0; - - /* Check 'base' */ - assert(!((NULL == base) || (NULL == handle))); - if ((NULL == base) || (NULL == handle)) - { - return kStatus_InvalidArgument; - } - - instance = USART_GetInstance(base); - - memset(handle, 0, sizeof(*handle)); - /* Set the TX/RX state. */ - handle->rxState = kUSART_RxIdle; - handle->txState = kUSART_TxIdle; - /* Set the callback and user data. */ - handle->callback = callback; - handle->userData = userData; - handle->rxWatermark = (usart_rxfifo_watermark_t)USART_FIFOTRIG_RXLVL_GET(base); - handle->txWatermark = (usart_txfifo_watermark_t)USART_FIFOTRIG_TXLVL_GET(base); - - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)USART_TransferHandleIRQ, handle); - - /* Enable interrupt in NVIC. */ - EnableIRQ(s_usartIRQ[instance]); - - return kStatus_Success; -} - -status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer) -{ - /* Check arguments */ - assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - /* Check xfer members */ - assert(!((0 == xfer->dataSize) || (NULL == xfer->data))); - if ((0 == xfer->dataSize) || (NULL == xfer->data)) - { - return kStatus_InvalidArgument; - } - - /* Return error if current TX busy. */ - if (kUSART_TxBusy == handle->txState) - { - return kStatus_USART_TxBusy; - } - else - { - handle->txData = xfer->data; - handle->txDataSize = xfer->dataSize; - handle->txDataSizeAll = xfer->dataSize; - handle->txState = kUSART_TxBusy; - /* Enable transmiter interrupt. */ - base->FIFOINTENSET |= USART_FIFOINTENSET_TXLVL_MASK; - } - return kStatus_Success; -} - -void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) -{ - assert(NULL != handle); - - /* Disable interrupts */ - base->FIFOINTENSET &= ~USART_FIFOINTENSET_TXLVL_MASK; - /* Empty txFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK; - - handle->txDataSize = 0; - handle->txState = kUSART_TxIdle; -} - -status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != count); - - if (kUSART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - handle->txDataSize; - - return kStatus_Success; -} - -status_t USART_TransferReceiveNonBlocking(USART_Type *base, - usart_handle_t *handle, - usart_transfer_t *xfer, - size_t *receivedBytes) -{ - uint32_t i; - /* How many bytes to copy from ring buffer to user memory. */ - size_t bytesToCopy = 0U; - /* How many bytes to receive. */ - size_t bytesToReceive; - /* How many bytes currently have received. */ - size_t bytesCurrentReceived; - uint32_t regPrimask = 0U; - - /* Check arguments */ - assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - /* Check xfer members */ - assert(!((0 == xfer->dataSize) || (NULL == xfer->data))); - if ((0 == xfer->dataSize) || (NULL == xfer->data)) - { - return kStatus_InvalidArgument; - } - - /* How to get data: - 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize - to uart handle, enable interrupt to store received data to xfer->data. When - all data received, trigger callback. - 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. - If there are enough data in ring buffer, copy them to xfer->data and return. - If there are not enough data in ring buffer, copy all of them to xfer->data, - save the xfer->data remained empty space to uart handle, receive data - to this empty space and trigger callback when finished. */ - if (kUSART_RxBusy == handle->rxState) - { - return kStatus_USART_RxBusy; - } - else - { - bytesToReceive = xfer->dataSize; - bytesCurrentReceived = 0U; - /* If RX ring buffer is used. */ - if (handle->rxRingBuffer) - { - /* Disable IRQ, protect ring buffer. */ - regPrimask = DisableGlobalIRQ(); - /* How many bytes in RX ring buffer currently. */ - bytesToCopy = USART_TransferGetRxRingBufferLength(handle); - if (bytesToCopy) - { - bytesToCopy = MIN(bytesToReceive, bytesToCopy); - bytesToReceive -= bytesToCopy; - /* Copy data from ring buffer to user memory. */ - for (i = 0U; i < bytesToCopy; i++) - { - xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; - /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - } - /* If ring buffer does not have enough data, still need to read more data. */ - if (bytesToReceive) - { - /* No data in ring buffer, save the request to UART handle. */ - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kUSART_RxBusy; - } - /* Enable IRQ if previously enabled. */ - EnableGlobalIRQ(regPrimask); - /* Call user callback since all data are received. */ - if (0 == bytesToReceive) - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); - } - } - } - /* Ring buffer not used. */ - else - { - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kUSART_RxBusy; - - /* Enable RX interrupt. */ - base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK; - } - /* Return the how many bytes have read. */ - if (receivedBytes) - { - *receivedBytes = bytesCurrentReceived; - } - } - return kStatus_Success; -} - -void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) -{ - assert(NULL != handle); - - /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ - if (!handle->rxRingBuffer) - { - /* Disable interrupts */ - base->FIFOINTENSET &= ~USART_FIFOINTENSET_RXLVL_MASK; - /* Empty rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - } - - handle->rxDataSize = 0U; - handle->rxState = kUSART_RxIdle; -} - -status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != count); - - if (kUSART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - handle->rxDataSize; - - return kStatus_Success; -} - -void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) -{ - /* Check arguments */ - assert((NULL != base) && (NULL != handle)); - - bool receiveEnabled = (handle->rxDataSize) || (handle->rxRingBuffer); - bool sendEnabled = handle->txDataSize; - - /* If RX overrun. */ - if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) - { - /* Clear rx error state. */ - base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback) - { - handle->callback(base, handle, kStatus_USART_RxError, handle->userData); - } - } - while ((receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) || - (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))) - { - /* Receive data */ - if (receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) - { - /* Receive to app bufffer if app buffer is present */ - if (handle->rxDataSize) - { - *handle->rxData = base->FIFORD; - handle->rxDataSize--; - handle->rxData++; - receiveEnabled = ((handle->rxDataSize != 0) || (handle->rxRingBuffer)); - if (!handle->rxDataSize) - { - if (!handle->rxRingBuffer) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; - } - handle->rxState = kUSART_RxIdle; - if (handle->callback) - { - handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); - } - } - } - /* Otherwise receive to ring buffer if ring buffer is present */ - else - { - if (handle->rxRingBuffer) - { - /* If RX ring buffer is full, trigger callback to notify over run. */ - if (USART_TransferIsRxRingBufferFull(handle)) - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData); - } - } - /* If ring buffer is still full after callback function, the oldest data is overrided. */ - if (USART_TransferIsRxRingBufferFull(handle)) - { - /* Increase handle->rxRingBufferTail to make room for new data. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - /* Read data. */ - handle->rxRingBuffer[handle->rxRingBufferHead] = base->FIFORD; - /* Increase handle->rxRingBufferHead. */ - if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferHead = 0U; - } - else - { - handle->rxRingBufferHead++; - } - } - } - } - /* Send data */ - if (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) - { - base->FIFOWR = *handle->txData; - handle->txDataSize--; - handle->txData++; - sendEnabled = handle->txDataSize != 0; - if (!sendEnabled) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK; - handle->txState = kUSART_TxIdle; - if (handle->callback) - { - handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); - } - } - } - } - - /* ring buffer is not used */ - if (NULL == handle->rxRingBuffer) - { - /* restore if rx transfer ends and rxLevel is different from default value */ - if ((handle->rxDataSize == 0) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark)) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark); - } - /* decrease level if rx transfer is bellow */ - if ((handle->rxDataSize != 0) && (handle->rxDataSize < (USART_FIFOTRIG_RXLVL_GET(base) + 1))) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(handle->rxDataSize - 1)); - } - } -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_usart.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_usart.h deleted file mode 100644 index 3fea97e6ec2..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_usart.h +++ /dev/null @@ -1,643 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_USART_H_ -#define _FSL_USART_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup usart_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief USART driver version 2.0.0. */ -#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT) -#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT) - -/*! @brief Error codes for the USART driver. */ -enum _usart_status -{ - kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */ - kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */ - kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */ - kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */ - kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */ - kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */ - kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */ - kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */ - kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */ - kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */ - kStatus_USART_BaudrateNotSupport = - MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */ -}; - -/*! @brief USART parity mode. */ -typedef enum _usart_parity_mode -{ - kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */ - kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ - kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ -} usart_parity_mode_t; - -/*! @brief USART stop bit count. */ -typedef enum _usart_stop_bit_count -{ - kUSART_OneStopBit = 0U, /*!< One stop bit */ - kUSART_TwoStopBit = 1U, /*!< Two stop bits */ -} usart_stop_bit_count_t; - -/*! @brief USART data size. */ -typedef enum _usart_data_len -{ - kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */ - kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */ -} usart_data_len_t; - -/*! @brief txFIFO watermark values */ -typedef enum _usart_txfifo_watermark -{ - kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */ - kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */ - kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */ - kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */ - kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */ - kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */ - kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */ - kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */ -} usart_txfifo_watermark_t; - -/*! @brief rxFIFO watermark values */ -typedef enum _usart_rxfifo_watermark -{ - kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */ - kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */ - kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */ - kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */ - kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */ - kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */ - kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */ - kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */ -} usart_rxfifo_watermark_t; - -/*! - * @brief USART interrupt configuration structure, default settings all disabled. - */ -enum _usart_interrupt_enable -{ - kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK), - kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK), - kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK), - kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK), -}; - -/*! - * @brief USART status flags. - * - * This provides constants for the USART status flags for use in the USART functions. - */ -enum _usart_flags -{ - kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */ - kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */ - kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */ - kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */ - kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */ - kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */ -}; - -/*! @brief USART configuration structure. */ -typedef struct _usart_config -{ - uint32_t baudRate_Bps; /*!< USART baud rate */ - usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ - usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ - usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */ - bool loopback; /*!< Enable peripheral loopback */ - bool enableRx; /*!< Enable RX */ - bool enableTx; /*!< Enable TX */ - usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ -} usart_config_t; - -/*! @brief USART transfer structure. */ -typedef struct _usart_transfer -{ - uint8_t *data; /*!< The buffer of data to be transfer.*/ - size_t dataSize; /*!< The byte count to be transfer. */ -} usart_transfer_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _usart_handle usart_handle_t; - -/*! @brief USART transfer callback function. */ -typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData); - -/*! @brief USART handle structure. */ -struct _usart_handle -{ - uint8_t *volatile txData; /*!< Address of remaining data to send. */ - volatile size_t txDataSize; /*!< Size of the remaining data to send. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ - volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - - uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ - size_t rxRingBufferSize; /*!< Size of the ring buffer. */ - volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ - volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ - - usart_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< USART callback function parameter.*/ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ - - usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! @brief Returns instance number for USART peripheral base address. */ -uint32_t USART_GetInstance(USART_Type *base); - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes a USART instance with user configuration structure and peripheral clock. - * - * This function configures the USART module with the user-defined settings. The user can configure the configuration - * structure and also get the default configuration by using the USART_GetDefaultConfig() function. - * Example below shows how to use this API to configure USART. - * @code - * usart_config_t usartConfig; - * usartConfig.baudRate_Bps = 115200U; - * usartConfig.parityMode = kUSART_ParityDisabled; - * usartConfig.stopBitCount = kUSART_OneStopBit; - * USART_Init(USART1, &usartConfig, 20000000U); - * @endcode - * - * @param base USART peripheral base address. - * @param config Pointer to user-defined configuration structure. - * @param srcClock_Hz USART clock source frequency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_InvalidArgument USART base address is not valid - * @retval kStatus_Success Status USART initialize succeed - */ -status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes a USART instance. - * - * This function waits for TX complete, disables TX and RX, and disables the USART clock. - * - * @param base USART peripheral base address. - */ -void USART_Deinit(USART_Type *base); - -/*! - * @brief Gets the default configuration structure. - * - * This function initializes the USART configuration structure to a default value. The default - * values are: - * usartConfig->baudRate_Bps = 115200U; - * usartConfig->parityMode = kUSART_ParityDisabled; - * usartConfig->stopBitCount = kUSART_OneStopBit; - * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; - * usartConfig->loopback = false; - * usartConfig->enableTx = false; - * usartConfig->enableRx = false; - * - * @param config Pointer to configuration structure. - */ -void USART_GetDefaultConfig(usart_config_t *config); - -/*! - * @brief Sets the USART instance baud rate. - * - * This function configures the USART module baud rate. This function is used to update - * the USART module baud rate after the USART module is initialized by the USART_Init. - * @code - * USART_SetBaudRate(USART1, 115200U, 20000000U); - * @endcode - * - * @param base USART peripheral base address. - * @param baudrate_Bps USART baudrate to be set. - * @param srcClock_Hz USART clock source freqency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_Success Set baudrate succeed. - * @retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Get USART status flags. - * - * This function get all USART status flags, the flags are returned as the logical - * OR value of the enumerators @ref _usart_flags. To check a specific status, - * compare the return value with enumerators in @ref _usart_flags. - * For example, to check whether the TX is empty: - * @code - * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1)) - * { - * ... - * } - * @endcode - * - * @param base USART peripheral base address. - * @return USART status flags which are ORed by the enumerators in the _usart_flags. - */ -static inline uint32_t USART_GetStatusFlags(USART_Type *base) -{ - return base->FIFOSTAT; -} - -/*! - * @brief Clear USART status flags. - * - * This function clear supported USART status flags - * Flags that can be cleared or set are: - * kUSART_TxError - * kUSART_RxError - * For example: - * @code - * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError) - * @endcode - * - * @param base USART peripheral base address. - * @param mask status flags to be cleared. - */ -static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask) -{ - /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */ - base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK); -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables USART interrupts according to the provided mask. - * - * This function enables the USART interrupts according to the provided mask. The mask - * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. - * For example, to enable TX empty interrupt and RX full interrupt: - * @code - * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); - * @endcode - * - * @param base USART peripheral base address. - * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable. - */ -static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) -{ - base->FIFOINTENSET = mask & 0xF; -} - -/*! - * @brief Disables USART interrupts according to a provided mask. - * - * This function disables the USART interrupts according to a provided mask. The mask - * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. - * This example shows how to disable the TX empty interrupt and RX full interrupt: - * @code - * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); - * @endcode - * - * @param base USART peripheral base address. - * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable. - */ -static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) -{ - base->FIFOINTENSET = ~(mask & 0xF); -} - -/*! -* @brief Enable DMA for Tx -*/ -static inline void USART_EnableTxDMA(USART_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK); - } -} - -/*! -* @brief Enable DMA for Rx -*/ -static inline void USART_EnableRxDMA(USART_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK); - } -} - -/* @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Writes to the FIFOWR register. - * - * This function writes data to the txFIFO directly. The upper layer must ensure - * that txFIFO has space for data to write before calling this function. - * - * @param base USART peripheral base address. - * @param data The byte to write. - */ -static inline void USART_WriteByte(USART_Type *base, uint8_t data) -{ - base->FIFOWR = data; -} - -/*! - * @brief Reads the FIFORD register directly. - * - * This function reads data from the rxFIFO directly. The upper layer must - * ensure that the rxFIFO is not empty before calling this function. - * - * @param base USART peripheral base address. - * @return The byte read from USART data register. - */ -static inline uint8_t USART_ReadByte(USART_Type *base) -{ - return base->FIFORD; -} - -/*! - * @brief Writes to the TX register using a blocking method. - * - * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO - * to have room and writes data to the TX buffer. - * - * @param base USART peripheral base address. - * @param data Start address of the data to write. - * @param length Size of the data to write. - */ -void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length); - -/*! - * @brief Read RX data register using a blocking method. - * - * This function polls the RX register, waits for the RX register to be full or for RX FIFO to - * have data and read data from the TX register. - * - * @param base USART peripheral base address. - * @param data Start address of the buffer to store the received data. - * @param length Size of the buffer. - * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data. - * @retval kStatus_USART_ParityError Noise error happened while receiving data. - * @retval kStatus_USART_NoiseError Framing error happened while receiving data. - * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. - * @retval kStatus_Success Successfully received all data. - */ -status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the USART handle. - * - * This function initializes the USART handle which can be used for other USART - * transactional APIs. Usually, for a specified USART instance, - * call this API once to get the initialized handle. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param callback The callback function. - * @param userData The parameter of the callback function. - */ -status_t USART_TransferCreateHandle(USART_Type *base, - usart_handle_t *handle, - usart_transfer_callback_t callback, - void *userData); - -/*! - * @brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in the IRQ handler, the USART driver calls the callback - * function and passes the @ref kStatus_USART_TxIdle as status parameter. - * - * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written - * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, - * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART transfer structure. See #usart_transfer_t. - * @retval kStatus_Success Successfully start the data transmission. - * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific USART handle. - * - * When the RX ring buffer is used, data received are stored into the ring buffer even when the - * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * - * @note When using the RX ring buffer, one byte is reserved for internal use. In other - * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. - * @param ringBufferSize size of the ring buffer. - */ -void USART_TransferStartRingBuffer(USART_Type *base, - usart_handle_t *handle, - uint8_t *ringBuffer, - size_t ringBufferSize); - -/*! - * @brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out - * how many bytes are still not sent out. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been written to USART TX register. - * - * This function gets the number of bytes that have been written to USART TX - * register by interrupt method. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Send bytes count. - * @retval kStatus_NoTransferInProgress No send in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); - -/*! - * @brief Receives a buffer of data using an interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function, which - * returns without waiting for all data to be received. - * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and - * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in the ring buffer is not enough to read, the receive - * request is saved by the USART driver. When the new data arrives, the receive request - * is serviced first. When all data is received, the USART driver notifies the upper layer - * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle. - * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. - * The 5 bytes are copied to the xfer->data and this function returns with the - * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is - * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to the xfer->data. When all data is received, the upper layer is notified. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART transfer structure, see #usart_transfer_t. - * @param receivedBytes Bytes received from the ring buffer directly. - * @retval kStatus_Success Successfully queue the transfer into transmit queue. - * @retval kStatus_USART_RxBusy Previous receive request is not finished. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveNonBlocking(USART_Type *base, - usart_handle_t *handle, - usart_transfer_t *xfer, - size_t *receivedBytes); - -/*! - * @brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out - * how many bytes not received yet. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); - -/*! - * @brief USART IRQ handle function. - * - * This function handles the USART transmit and receive IRQ request. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_USART_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_usart_dma.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_usart_dma.c deleted file mode 100644 index 129419eace6..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_usart_dma.c +++ /dev/null @@ -1,261 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_usart.h" -#include "fsl_device_registers.h" -#include "fsl_dma.h" -#include "fsl_flexcomm.h" -#include "fsl_usart_dma.h" - -/*base, false); - - usartPrivateHandle->handle->txState = kUSART_TxIdle; - - if (usartPrivateHandle->handle->callback) - { - usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_TxIdle, - usartPrivateHandle->handle->userData); - } -} - -static void USART_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode) -{ - assert(handle); - assert(param); - - usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param; - - /* Disable UART RX DMA. */ - USART_EnableRxDMA(usartPrivateHandle->base, false); - - usartPrivateHandle->handle->rxState = kUSART_RxIdle; - - if (usartPrivateHandle->handle->callback) - { - usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_RxIdle, - usartPrivateHandle->handle->userData); - } -} - -status_t USART_TransferCreateHandleDMA(USART_Type *base, - usart_dma_handle_t *handle, - usart_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *txDmaHandle, - dma_handle_t *rxDmaHandle) -{ - int32_t instance = 0; - - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } - /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - instance = USART_GetInstance(base); - - memset(handle, 0, sizeof(*handle)); - /* assign 'base' and 'handle' */ - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - /* set tx/rx 'idle' state */ - handle->rxState = kUSART_RxIdle; - handle->txState = kUSART_TxIdle; - - handle->callback = callback; - handle->userData = userData; - - handle->rxDmaHandle = rxDmaHandle; - handle->txDmaHandle = txDmaHandle; - - /* Configure TX. */ - if (txDmaHandle) - { - DMA_SetCallback(txDmaHandle, USART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]); - } - - /* Configure RX. */ - if (rxDmaHandle) - { - DMA_SetCallback(rxDmaHandle, USART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]); - } - - return kStatus_Success; -} - -status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) -{ - assert(handle); - assert(handle->txDmaHandle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - dma_transfer_config_t xferConfig; - status_t status; - - /* If previous TX not finished. */ - if (kUSART_TxBusy == handle->txState) - { - status = kStatus_USART_TxBusy; - } - else - { - handle->txState = kUSART_TxBusy; - handle->txDataSizeAll = xfer->dataSize; - - /* Enable DMA request from txFIFO */ - USART_EnableTxDMA(base, true); - - /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, xfer->data, (void *)&base->FIFOWR, sizeof(uint8_t), xfer->dataSize, - kDMA_MemoryToPeripheral, NULL); - - /* Submit transfer. */ - DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); - DMA_StartTransfer(handle->txDmaHandle); - - status = kStatus_Success; - } - - return status; -} - -status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) -{ - assert(handle); - assert(handle->rxDmaHandle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - dma_transfer_config_t xferConfig; - status_t status; - - /* If previous RX not finished. */ - if (kUSART_RxBusy == handle->rxState) - { - status = kStatus_USART_RxBusy; - } - else - { - handle->rxState = kUSART_RxBusy; - handle->rxDataSizeAll = xfer->dataSize; - - /* Enable DMA request from rxFIFO */ - USART_EnableRxDMA(base, true); - - /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, xfer->data, sizeof(uint8_t), xfer->dataSize, - kDMA_PeripheralToMemory, NULL); - - /* Submit transfer. */ - DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); - DMA_StartTransfer(handle->rxDmaHandle); - - status = kStatus_Success; - } - - return status; -} - -void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle) -{ - assert(NULL != handle); - assert(NULL != handle->txDmaHandle); - - /* Stop transfer. */ - DMA_AbortTransfer(handle->txDmaHandle); - handle->txState = kUSART_TxIdle; -} - -void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle) -{ - assert(NULL != handle); - assert(NULL != handle->rxDmaHandle); - - /* Stop transfer. */ - DMA_AbortTransfer(handle->rxDmaHandle); - handle->rxState = kUSART_RxIdle; -} - -status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) -{ - assert(handle); - assert(handle->rxDmaHandle); - assert(count); - - if (kUSART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); - - return kStatus_Success; -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_usart_dma.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_usart_dma.h deleted file mode 100644 index e28692cf3f5..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_usart_dma.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_USART_DMA_H_ -#define _FSL_USART_DMA_H_ - -#include "fsl_common.h" -#include "fsl_dma.h" -#include "fsl_usart.h" - -/*! - * @addtogroup usart_dma_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Forward declaration of the handle typedef. */ -typedef struct _usart_dma_handle usart_dma_handle_t; - -/*! @brief UART transfer callback function. */ -typedef void (*usart_dma_transfer_callback_t)(USART_Type *base, - usart_dma_handle_t *handle, - status_t status, - void *userData); - -/*! -* @brief UART DMA handle -*/ -struct _usart_dma_handle -{ - USART_Type *base; /*!< UART peripheral base address. */ - - usart_dma_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< UART callback function parameter.*/ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - - dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */ - dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name DMA transactional - * @{ - */ - -/*! - * @brief Initializes the USART handle which is used in transactional functions. - * @param base USART peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param callback Callback function. - * @param userData User data. - * @param txDmaHandle User-requested DMA handle for TX DMA transfer. - * @param rxDmaHandle User-requested DMA handle for RX DMA transfer. - */ -status_t USART_TransferCreateHandleDMA(USART_Type *base, - usart_dma_handle_t *handle, - usart_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *txDmaHandle, - dma_handle_t *rxDmaHandle); - -/*! - * @brief Sends data using DMA. - * - * This function sends data using DMA. This is a non-blocking function, which returns - * right away. When all data is sent, the send callback function is called. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART DMA transfer structure. See #usart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_USART_TxBusy Previous transfer on going. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Receives data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * @param base USART peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param xfer USART DMA transfer structure. See #usart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_USART_RxBusy Previous transfer on going. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Aborts the sent data using DMA. - * - * This function aborts send data using DMA. - * - * @param base USART peripheral base address - * @param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle); - -/*! - * @brief Aborts the received data using DMA. - * - * This function aborts the received data using DMA. - * - * @param base USART peripheral base address - * @param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_USART_DMA_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_utick.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_utick.c deleted file mode 100644 index b1b208e8561..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_utick.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_utick.h" -#include "fsl_power.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Typedef for interrupt handler. */ -typedef void (*utick_isr_t)(UTICK_Type *base, utick_callback_t cb); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base UTICK peripheral base address - * - * @return The UTICK instance - */ -static uint32_t UTICK_GetInstance(UTICK_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of UTICK handle. */ -static utick_callback_t s_utickHandle[FSL_FEATURE_SOC_UTICK_COUNT]; -/* Array of UTICK peripheral base address. */ -static UTICK_Type *const s_utickBases[] = UTICK_BASE_PTRS; -/* Array of UTICK IRQ number. */ -static const IRQn_Type s_utickIRQ[] = UTICK_IRQS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of UTICK clock name. */ -static const clock_ip_name_t s_utickClock[] = UTICK_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -/* UTICK ISR for transactional APIs. */ -static utick_isr_t s_utickIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t UTICK_GetInstance(UTICK_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_utickBases); instance++) - { - if (s_utickBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_utickBases)); - - return instance; -} - -void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb) -{ - uint32_t instance; - - /* Get instance from peripheral base address. */ - instance = UTICK_GetInstance(base); - - /* Save the handle in global variables to support the double weak mechanism. */ - s_utickHandle[instance] = cb; - EnableDeepSleepIRQ(s_utickIRQ[instance]); - base->CTRL = count | UTICK_CTRL_REPEAT(mode); -} - -void UTICK_Init(UTICK_Type *base) -{ - /* Enable utick clock */ - CLOCK_EnableClock(s_utickClock[UTICK_GetInstance(base)]); - /* Power up Watchdog oscillator*/ - POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC); - s_utickIsr = UTICK_HandleIRQ; -} - -void UTICK_Deinit(UTICK_Type *base) -{ - /* Turn off utick */ - base->CTRL = 0; - /* Disable utick clock */ - CLOCK_DisableClock(s_utickClock[UTICK_GetInstance(base)]); -} - -uint32_t UTICK_GetStatusFlags(UTICK_Type *base) -{ - return (base->STAT); -} - -void UTICK_ClearStatusFlags(UTICK_Type *base) -{ - base->STAT = UTICK_STAT_INTR_MASK; -} - -void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb) -{ - UTICK_ClearStatusFlags(base); - if (cb) - { - cb(); - } -} - -#if defined(UTICK0) -void UTICK0_DriverIRQHandler(void) -{ - s_utickIsr(UTICK0, s_utickHandle[0]); -} -#endif -#if defined(UTICK1) -void UTICK1_DriverIRQHandler(void) -{ - s_utickIsr(UTICK1, s_utickHandle[1]); -} -#endif -#if defined(UTICK2) -void UTICK2_DriverIRQHandler(void) -{ - s_utickIsr(UTICK2, s_utickHandle[2]); -} -#endif diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_utick.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_utick.h deleted file mode 100644 index 6aa617d9335..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_utick.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_UTICK_H_ -#define _FSL_UTICK_H_ - -#include "fsl_common.h" -/*! - * @addtogroup utick - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief UTICK driver version 2.0.0. */ -#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @brief UTICK timer operational mode. */ -typedef enum _utick_mode -{ - kUTICK_Onetime = 0x0U, /*!< Trigger once*/ - kUTICK_Repeat = 0x1U, /*!< Trigger repeatedly */ -} utick_mode_t; - -/*! @brief UTICK callback function. */ -typedef void (*utick_callback_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! -* @brief Initializes an UTICK by turning its bus clock on -* -*/ -void UTICK_Init(UTICK_Type *base); - -/*! - * @brief Deinitializes a UTICK instance. - * - * This function shuts down Utick bus clock - * - * @param base UTICK peripheral base address. - */ -void UTICK_Deinit(UTICK_Type *base); -/*! - * @brief Get Status Flags. - * - * This returns the status flag - * - * @param base UTICK peripheral base address. - * @return status register value - */ -uint32_t UTICK_GetStatusFlags(UTICK_Type *base); -/*! - * @brief Clear Status Interrupt Flags. - * - * This clears intr status flag - * - * @param base UTICK peripheral base address. - * @return none - */ -void UTICK_ClearStatusFlags(UTICK_Type *base); - -/*! - * @brief Starts UTICK. - * - * This function starts a repeat/onetime countdown with an optional callback - * - * @param base UTICK peripheral base address. - * @param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * @param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * @param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) - * @return none - */ -void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb); -/*! - * @brief UTICK Interrupt Service Handler. - * - * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request - * in UTICK_SetTick()). - * if no user callback is scheduled, the interrupt will simply be cleared. - * - * @param base UTICK peripheral base address. - * @param cb callback scheduled for this instance of UTICK - * @return none - */ -void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_UTICK_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_wwdt.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_wwdt.c deleted file mode 100644 index 43c44de667b..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_wwdt.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_wwdt.h" - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Gets the instance from the base address - * - * @param base WWDT peripheral base address - * - * @return The WWDT instance - */ -static uint32_t WWDT_GetInstance(WWDT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to WWDT bases for each instance. */ -static WWDT_Type *const s_wwdtBases[] = WWDT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to WWDT clocks for each instance. */ -static const clock_ip_name_t s_wwdtClocks[] = WWDT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Pointers to WWDT resets for each instance. */ -static const reset_ip_name_t s_wwdtResets[] = WWDT_RSTS; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t WWDT_GetInstance(WWDT_Type *base) -{ - uint32_t instance; - uint32_t wwdtArrayCount = (sizeof(s_wwdtBases) / sizeof(s_wwdtBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < wwdtArrayCount; instance++) - { - if (s_wwdtBases[instance] == base) - { - break; - } - } - - assert(instance < wwdtArrayCount); - - return instance; -} - -/******************************************************************************* - * Code - ******************************************************************************/ - -void WWDT_GetDefaultConfig(wwdt_config_t *config) -{ - assert(config); - - /* Enable the watch dog */ - config->enableWwdt = true; - /* Disable the watchdog timeout reset */ - config->enableWatchdogReset = false; - /* Disable the watchdog protection for updating the timeout value */ - config->enableWatchdogProtect = false; - /* Do not lock the watchdog oscillator */ - config->enableLockOscillator = false; - /* Windowing is not in effect */ - config->windowValue = 0xFFFFFFU; - /* Set the timeout value to the max */ - config->timeoutValue = 0xFFFFFFU; - /* No warning is provided */ - config->warningValue = 0; -} - -void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config) -{ - assert(config); - - uint32_t value = 0U; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the WWDT clock */ - CLOCK_EnableClock(s_wwdtClocks[WWDT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the WWDT module */ - RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]); - - value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) | - WWDT_MOD_WDPROTECT(config->enableWatchdogProtect) | WWDT_MOD_LOCK(config->enableLockOscillator); - /* Set configruation */ - base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue); - base->TC = WWDT_TC_COUNT(config->timeoutValue); - base->WARNINT = WWDT_WARNINT_WARNINT(config->warningValue); - base->MOD = value; -} - -void WWDT_Deinit(WWDT_Type *base) -{ - WWDT_Disable(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the WWDT clock */ - CLOCK_DisableClock(s_wwdtClocks[WWDT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void WWDT_Refresh(WWDT_Type *base) -{ - uint32_t primaskValue = 0U; - - /* Disable the global interrupt to protect refresh sequence */ - primaskValue = DisableGlobalIRQ(); - base->FEED = WWDT_FIRST_WORD_OF_REFRESH; - base->FEED = WWDT_SECOND_WORD_OF_REFRESH; - EnableGlobalIRQ(primaskValue); -} - -void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask) -{ - /* Clear the WDINT bit so that we don't accidentally clear it */ - uint32_t reg = (base->MOD & (~WWDT_MOD_WDINT_MASK)); - - /* Clear timeout by writing a zero */ - if (mask & kWWDT_TimeoutFlag) - { - reg &= ~WWDT_MOD_WDTOF_MASK; - } - - /* Clear warning interrupt flag by writing a one */ - if (mask & kWWDT_WarningFlag) - { - reg |= WWDT_MOD_WDINT_MASK; - } - - base->MOD = reg; -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_wwdt.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_wwdt.h deleted file mode 100644 index 02916aa2f24..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_wwdt.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_WWDT_H_ -#define _FSL_WWDT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup wwdt - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Defines WWDT driver version 2.0.0. */ -#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @name Refresh sequence */ -/*@{*/ -#define WWDT_FIRST_WORD_OF_REFRESH (0xAAU) /*!< First word of refresh sequence */ -#define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */ -/*@}*/ - -/*! @brief Describes WWDT configuration structure. */ -typedef struct _wwdt_config -{ - bool enableWwdt; /*!< Enables or disables WWDT */ - bool enableWatchdogReset; /*!< true: Watchdog timeout will cause a chip reset - false: Watchdog timeout will not cause a chip reset */ - bool enableWatchdogProtect; /*!< true: Enable watchdog protect i.e timeout value can only be - changed after counter is below warning & window values - false: Disable watchdog protect; timeout value can be changed - at any time */ - bool enableLockOscillator; /*!< true: Disabling or powering down the watchdog oscillator is prevented - Once set, this bit can only be cleared by a reset - false: Do not lock oscillator */ - uint32_t windowValue; /*!< Window value, set this to 0xFFFFFF if windowing is not in effect */ - uint32_t timeoutValue; /*!< Timeout value */ - uint32_t warningValue; /*!< Watchdog time counter value that will generate a - warning interrupt. Set this to 0 for no warning */ - -} wwdt_config_t; - -/*! - * @brief WWDT status flags. - * - * This structure contains the WWDT status flags for use in the WWDT functions. - */ -enum _wwdt_status_flags_t -{ - kWWDT_TimeoutFlag = WWDT_MOD_WDTOF_MASK, /*!< Time-out flag, set when the timer times out */ - kWWDT_WarningFlag = WWDT_MOD_WDINT_MASK /*!< Warning interrupt flag, set when timer is below the value WDWARNINT */ -}; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name WWDT Initialization and De-initialization - * @{ - */ - -/*! - * @brief Initializes WWDT configure sturcture. - * - * This function initializes the WWDT configure structure to default value. The default - * value are: - * @code - * config->enableWwdt = true; - * config->enableWatchdogReset = false; - * config->enableWatchdogProtect = false; - * config->enableLockOscillator = false; - * config->windowValue = 0xFFFFFFU; - * config->timeoutValue = 0xFFFFFFU; - * config->warningValue = 0; - * @endcode - * - * @param config Pointer to WWDT config structure. - * @see wwdt_config_t - */ -void WWDT_GetDefaultConfig(wwdt_config_t *config); - -/*! - * @brief Initializes the WWDT. - * - * This function initializes the WWDT. When called, the WWDT runs according to the configuration. - * - * Example: - * @code - * wwdt_config_t config; - * WWDT_GetDefaultConfig(&config); - * config.timeoutValue = 0x7ffU; - * WWDT_Init(wwdt_base,&config); - * @endcode - * - * @param base WWDT peripheral base address - * @param config The configuration of WWDT - */ -void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config); - -/*! - * @brief Shuts down the WWDT. - * - * This function shuts down the WWDT. - * - * @param base WWDT peripheral base address - */ -void WWDT_Deinit(WWDT_Type *base); - -/* @} */ - -/*! - * @name WWDT Functional Operation - * @{ - */ - -/*! - * @brief Enables the WWDT module. - * - * This function write value into WWDT_MOD register to enable the WWDT, it is a write-once bit; - * once this bit is set to one and a watchdog feed is performed, the watchdog timer will run - * permanently. - * - * @param base WWDT peripheral base address - */ -static inline void WWDT_Enable(WWDT_Type *base) -{ - base->MOD |= WWDT_MOD_WDEN_MASK; -} - -/*! - * @brief Disables the WWDT module. - * - * This function write value into WWDT_MOD register to disable the WWDT. - * - * @param base WWDT peripheral base address - */ -static inline void WWDT_Disable(WWDT_Type *base) -{ - base->MOD &= ~WWDT_MOD_WDEN_MASK; -} - -/*! - * @brief Gets all WWDT status flags. - * - * This function gets all status flags. - * - * Example for getting Timeout Flag: - * @code - * uint32_t status; - * status = WWDT_GetStatusFlags(wwdt_base) & kWWDT_TimeoutFlag; - * @endcode - * @param base WWDT peripheral base address - * @return The status flags. This is the logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -static inline uint32_t WWDT_GetStatusFlags(WWDT_Type *base) -{ - return (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); -} - -/*! - * @brief Clear WWDT flag. - * - * This function clears WWDT status flag. - * - * Example for clearing warning flag: - * @code - * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); - * @endcode - * @param base WWDT peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask); - -/*! - * @brief Set the WWDT warning value. - * - * The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog - * interrupt. When the watchdog timer counter is no longer greater than the value defined by - * WARNINT, an interrupt will be generated after the subsequent WDCLK. - * - * @param base WWDT peripheral base address - * @param warningValue WWDT warning value. - */ -static inline void WWDT_SetWarningValue(WWDT_Type *base, uint32_t warningValue) -{ - base->WARNINT = WWDT_WARNINT_WARNINT(warningValue); -} - -/*! - * @brief Set the WWDT timeout value. - * - * This function sets the timeout value. Every time a feed sequence occurs the value in the TC - * register is loaded into the Watchdog timer. Writing a value below 0xFF will cause 0xFF to be - * loaded into the TC register. Thus the minimum time-out interval is TWDCLK*256*4. - * If enableWatchdogProtect flag is true in wwdt_config_t config structure, any attempt to change - * the timeout value before the watchdog counter is below the warning and window values - * will cause a watchdog reset and set the WDTOF flag. - * - * @param base WWDT peripheral base address - * @param timeoutCount WWDT timeout value, count of WWDT clock tick. - */ -static inline void WWDT_SetTimeoutValue(WWDT_Type *base, uint32_t timeoutCount) -{ - base->TC = WWDT_TC_COUNT(timeoutCount); -} - -/*! - * @brief Sets the WWDT window value. - * - * The WINDOW register determines the highest TV value allowed when a watchdog feed is performed. - * If a feed sequence occurs when timer value is greater than the value in WINDOW, a watchdog - * event will occur. To disable windowing, set windowValue to 0xFFFFFF (maximum possible timer - * value) so windowing is not in effect. - * - * @param base WWDT peripheral base address - * @param windowValue WWDT window value. - */ -static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue) -{ - base->WINDOW = WWDT_WINDOW_WINDOW(windowValue); -} - -/*! - * @brief Refreshes the WWDT timer. - * - * This function feeds the WWDT. - * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. - * - * @param base WWDT peripheral base address - */ -void WWDT_Refresh(WWDT_Type *base); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_WWDT_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/fsl_device_registers.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/fsl_device_registers.h deleted file mode 100644 index ac8dd79f0e3..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/fsl_device_registers.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016 - 2017 NXP - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __FSL_DEVICE_REGISTERS_H__ -#define __FSL_DEVICE_REGISTERS_H__ - -/* - * Include the cpu specific register header files. - * - * The CPU macro should be declared in the project or makefile. - */ -#if (defined(CPU_LPC54608J512BD208) || defined(CPU_LPC54608J512ET180)) - -#define LPC54608_SERIES - -/* CMSIS-style register definitions */ -#include "LPC54608.h" -/* CPU specific feature definitions */ -#include "LPC54608_features.h" - -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_DEVICE_REGISTERS_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/iar/LPC54608J512_flash.icf b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/iar/LPC54608J512_flash.icf deleted file mode 100644 index 12a13db29cc..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/iar/LPC54608J512_flash.icf +++ /dev/null @@ -1,119 +0,0 @@ -/* -** ################################################################### -** Processors: LPC54608J512BD208 -** LPC54608J512ET180 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC54S60x/LPC5460x User manual Rev.0.9 7 Nov 2016 -** Version: rev. 1.1, 2016-11-25 -** Build: b161227 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0; -define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0; - -define symbol m_interrupts_start = 0x00000000; -define symbol m_interrupts_end = 0x000003FF; - -define symbol m_text_start = 0x00000400; -define symbol m_text_end = 0x0007FFFF; - -define symbol m_interrupts_ram_start = 0x20000000; -define symbol m_interrupts_ram_end = 0x20000000 + __ram_vector_table_offset__; - -define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__; -define symbol m_data_end = 0x20027FFF; - -define symbol m_usb_sram_start = 0x40100000; -define symbol m_usb_sram_end = 0x40101FFF; - -/* USB BDT size */ -define symbol usb_bdt_size = 0x0; -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__; - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - -/* regions for USB */ -define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; -define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; -place in USB_BDT_region { section m_usb_bdt }; -place in USB_SRAM_region { section m_usb_global }; - -initialize by copy { readwrite, section .textrw }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - /* Required in a multi-threaded application */ - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; -place in m_interrupts_ram_region { section m_interrupts_ram }; - diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/iar/LPC54608J512_ram.icf b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/iar/LPC54608J512_ram.icf deleted file mode 100644 index d2109c49a4b..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/iar/LPC54608J512_ram.icf +++ /dev/null @@ -1,111 +0,0 @@ -/* -** ################################################################### -** Processors: LPC54608J512BD208 -** LPC54608J512ET180 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC54S60x/LPC5460x User manual Rev.0.9 7 Nov 2016 -** Version: rev. 1.1, 2016-11-25 -** Build: b161227 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol m_interrupts_start = 0x20000000; -define symbol m_interrupts_end = 0x200003FF; - -define symbol m_text_start = 0x20000400; -define symbol m_text_end = 0x200141FF; - -define symbol m_data_start = 0x20014200; -define symbol m_data_end = 0x20027FFF; - -define symbol m_usb_sram_start = 0x40100000; -define symbol m_usb_sram_end = 0x40101FFF; - -/* USB BDT size */ -define symbol usb_bdt_size = 0x0; -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - -/* regions for USB */ -define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; -define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; -place in USB_BDT_region { section m_usb_bdt }; -place in USB_SRAM_region { section m_usb_global }; - -initialize by copy { readwrite, section .textrw }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - /* Required in a multi-threaded application */ - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; - diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/iar/SConscript b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/iar/SConscript deleted file mode 100644 index 297ac635845..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/iar/SConscript +++ /dev/null @@ -1,10 +0,0 @@ -from building import * - -cwd = GetCurrentDir() -src = Split(''' -startup_LPC54608.s -''') - -group = DefineGroup('CMSIS', src, depend = [''], LIBS=['iar_lib_power'], LIBPATH=[cwd]) - -Return('group') diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/iar/iar_lib_power.a b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/iar/iar_lib_power.a deleted file mode 100644 index 755b29878d6..00000000000 Binary files a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/iar/iar_lib_power.a and /dev/null differ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/iar/startup_LPC54608.s b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/iar/startup_LPC54608.s deleted file mode 100644 index bc7e9e45502..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/iar/startup_LPC54608.s +++ /dev/null @@ -1,615 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC54608.s -; * @purpose: CMSIS Cortex-M4 Core Device Startup File -; * LPC54608 -; * @version: 1.1 -; * @date: 2016-11-25 -; *---------------------------------------------------------------------------- -; * -; * Copyright 1997 - 2016 Freescale Semiconductor. -; * Copyright 2016 - 2017 NXP -; * -; Redistribution and use in source and binary forms, with or without modification, -; are permitted provided that the following conditions are met: -; -; o Redistributions of source code must retain the above copyright notice, this list -; of conditions and the following disclaimer. -; -; o Redistributions in binary form must reproduce the above copyright notice, this -; list of conditions and the following disclaimer in the documentation and/or -; other materials provided with the distribution. -; -; o Neither the name of the copyright holder nor the names of its -; contributors may be used to endorse or promote products derived from this -; software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0xFFFFFFFF ;ECRP - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect - DCD DMA0_IRQHandler ; DMA controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) - DCD ADC0_SEQA_IRQHandler ; ADC0 sequence A completion. - DCD ADC0_SEQB_IRQHandler ; ADC0 sequence B completion. - DCD ADC0_THCMP_IRQHandler ; ADC0 threshold compare and error. - DCD DMIC0_IRQHandler ; Digital microphone and DMIC subsystem - DCD HWVAD0_IRQHandler ; Hardware Voice Activity Detector - DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt - DCD USB0_IRQHandler ; USB device - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD Reserved46_IRQHandler ; Reserved interrupt - DCD Reserved47_IRQHandler ; Reserved interrupt - DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int - DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int - DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int - DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int - DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 - DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 - DCD RIT_IRQHandler ; Repetitive Interrupt Timer - DCD SPIFI0_IRQHandler ; SPI flash interface - DCD FLEXCOMM8_IRQHandler ; Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM9_IRQHandler ; Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) - DCD SDIO_IRQHandler ; SD/MMC - DCD CAN0_IRQ0_IRQHandler ; CAN0 interrupt0 - DCD CAN0_IRQ1_IRQHandler ; CAN0 interrupt1 - DCD CAN1_IRQ0_IRQHandler ; CAN1 interrupt0 - DCD CAN1_IRQ1_IRQHandler ; CAN1 interrupt1 - DCD USB1_IRQHandler ; USB1 interrupt - DCD USB1_NEEDCLK_IRQHandler ; USB1 activity - DCD ETHERNET_IRQHandler ; Ethernet - DCD ETHERNET_PMT_IRQHandler ; Ethernet power management interrupt - DCD ETHERNET_MACLP_IRQHandler ; Ethernet MAC interrupt - DCD EEPROM_IRQHandler ; EEPROM interrupt - DCD LCD_IRQHandler ; LCD interrupt - DCD SHA_IRQHandler ; SHA interrupt - DCD SMARTCARD0_IRQHandler ; Smart card 0 interrupt - DCD SMARTCARD1_IRQHandler ; Smart card 1 interrupt -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR r0, =SystemInit - BLX r0 - LDR r0, =__iar_program_start - BX r0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK WDT_BOD_IRQHandler - PUBWEAK WDT_BOD_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -WDT_BOD_IRQHandler - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler - LDR R0, =DMA0_DriverIRQHandler - BX R0 - PUBWEAK GINT0_IRQHandler - PUBWEAK GINT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT0_IRQHandler - LDR R0, =GINT0_DriverIRQHandler - BX R0 - PUBWEAK GINT1_IRQHandler - PUBWEAK GINT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT1_IRQHandler - LDR R0, =GINT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT0_IRQHandler - PUBWEAK PIN_INT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT0_IRQHandler - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT1_IRQHandler - PUBWEAK PIN_INT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT1_IRQHandler - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT2_IRQHandler - PUBWEAK PIN_INT2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT2_IRQHandler - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT3_IRQHandler - PUBWEAK PIN_INT3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT3_IRQHandler - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - PUBWEAK UTICK0_IRQHandler - PUBWEAK UTICK0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UTICK0_IRQHandler - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - PUBWEAK MRT0_IRQHandler - PUBWEAK MRT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -MRT0_IRQHandler - LDR R0, =MRT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER0_IRQHandler - PUBWEAK CTIMER0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER0_IRQHandler - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER1_IRQHandler - PUBWEAK CTIMER1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER1_IRQHandler - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - PUBWEAK SCT0_IRQHandler - PUBWEAK SCT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SCT0_IRQHandler - LDR R0, =SCT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER3_IRQHandler - PUBWEAK CTIMER3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER3_IRQHandler - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM0_IRQHandler - PUBWEAK FLEXCOMM0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM0_IRQHandler - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM1_IRQHandler - PUBWEAK FLEXCOMM1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM1_IRQHandler - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM2_IRQHandler - PUBWEAK FLEXCOMM2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM2_IRQHandler - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM3_IRQHandler - PUBWEAK FLEXCOMM3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM3_IRQHandler - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM4_IRQHandler - PUBWEAK FLEXCOMM4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM4_IRQHandler - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM5_IRQHandler - PUBWEAK FLEXCOMM5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM5_IRQHandler - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM6_IRQHandler - PUBWEAK FLEXCOMM6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM6_IRQHandler - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM7_IRQHandler - PUBWEAK FLEXCOMM7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM7_IRQHandler - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - PUBWEAK ADC0_SEQA_IRQHandler - PUBWEAK ADC0_SEQA_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_SEQA_IRQHandler - LDR R0, =ADC0_SEQA_DriverIRQHandler - BX R0 - PUBWEAK ADC0_SEQB_IRQHandler - PUBWEAK ADC0_SEQB_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_SEQB_IRQHandler - LDR R0, =ADC0_SEQB_DriverIRQHandler - BX R0 - PUBWEAK ADC0_THCMP_IRQHandler - PUBWEAK ADC0_THCMP_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_THCMP_IRQHandler - LDR R0, =ADC0_THCMP_DriverIRQHandler - BX R0 - PUBWEAK DMIC0_IRQHandler - PUBWEAK DMIC0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMIC0_IRQHandler - LDR R0, =DMIC0_DriverIRQHandler - BX R0 - PUBWEAK HWVAD0_IRQHandler - PUBWEAK HWVAD0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -HWVAD0_IRQHandler - LDR R0, =HWVAD0_DriverIRQHandler - BX R0 - PUBWEAK USB0_NEEDCLK_IRQHandler - PUBWEAK USB0_NEEDCLK_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_NEEDCLK_IRQHandler - LDR R0, =USB0_NEEDCLK_DriverIRQHandler - BX R0 - PUBWEAK USB0_IRQHandler - PUBWEAK USB0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_IRQHandler - LDR R0, =USB0_DriverIRQHandler - BX R0 - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -RTC_IRQHandler - LDR R0, =RTC_DriverIRQHandler - BX R0 - PUBWEAK Reserved46_IRQHandler - PUBWEAK Reserved46_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved46_IRQHandler - LDR R0, =Reserved46_DriverIRQHandler - BX R0 - PUBWEAK Reserved47_IRQHandler - PUBWEAK Reserved47_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved47_IRQHandler - LDR R0, =Reserved47_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT4_IRQHandler - PUBWEAK PIN_INT4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT4_IRQHandler - LDR R0, =PIN_INT4_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT5_IRQHandler - PUBWEAK PIN_INT5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT5_IRQHandler - LDR R0, =PIN_INT5_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT6_IRQHandler - PUBWEAK PIN_INT6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT6_IRQHandler - LDR R0, =PIN_INT6_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT7_IRQHandler - PUBWEAK PIN_INT7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT7_IRQHandler - LDR R0, =PIN_INT7_DriverIRQHandler - BX R0 - PUBWEAK CTIMER2_IRQHandler - PUBWEAK CTIMER2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER2_IRQHandler - LDR R0, =CTIMER2_DriverIRQHandler - BX R0 - PUBWEAK CTIMER4_IRQHandler - PUBWEAK CTIMER4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER4_IRQHandler - LDR R0, =CTIMER4_DriverIRQHandler - BX R0 - PUBWEAK RIT_IRQHandler - PUBWEAK RIT_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -RIT_IRQHandler - LDR R0, =RIT_DriverIRQHandler - BX R0 - PUBWEAK SPIFI0_IRQHandler - PUBWEAK SPIFI0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPIFI0_IRQHandler - LDR R0, =SPIFI0_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM8_IRQHandler - PUBWEAK FLEXCOMM8_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM8_IRQHandler - LDR R0, =FLEXCOMM8_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM9_IRQHandler - PUBWEAK FLEXCOMM9_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM9_IRQHandler - LDR R0, =FLEXCOMM9_DriverIRQHandler - BX R0 - PUBWEAK SDIO_IRQHandler - PUBWEAK SDIO_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SDIO_IRQHandler - LDR R0, =SDIO_DriverIRQHandler - BX R0 - PUBWEAK CAN0_IRQ0_IRQHandler - PUBWEAK CAN0_IRQ0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CAN0_IRQ0_IRQHandler - LDR R0, =CAN0_IRQ0_DriverIRQHandler - BX R0 - PUBWEAK CAN0_IRQ1_IRQHandler - PUBWEAK CAN0_IRQ1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CAN0_IRQ1_IRQHandler - LDR R0, =CAN0_IRQ1_DriverIRQHandler - BX R0 - PUBWEAK CAN1_IRQ0_IRQHandler - PUBWEAK CAN1_IRQ0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CAN1_IRQ0_IRQHandler - LDR R0, =CAN1_IRQ0_DriverIRQHandler - BX R0 - PUBWEAK CAN1_IRQ1_IRQHandler - PUBWEAK CAN1_IRQ1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CAN1_IRQ1_IRQHandler - LDR R0, =CAN1_IRQ1_DriverIRQHandler - BX R0 - PUBWEAK USB1_IRQHandler - PUBWEAK USB1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB1_IRQHandler - LDR R0, =USB1_DriverIRQHandler - BX R0 - PUBWEAK USB1_NEEDCLK_IRQHandler - PUBWEAK USB1_NEEDCLK_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB1_NEEDCLK_IRQHandler - LDR R0, =USB1_NEEDCLK_DriverIRQHandler - BX R0 - PUBWEAK ETHERNET_IRQHandler - PUBWEAK ETHERNET_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ETHERNET_IRQHandler - LDR R0, =ETHERNET_DriverIRQHandler - BX R0 - PUBWEAK ETHERNET_PMT_IRQHandler - PUBWEAK ETHERNET_PMT_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ETHERNET_PMT_IRQHandler - LDR R0, =ETHERNET_PMT_DriverIRQHandler - BX R0 - PUBWEAK ETHERNET_MACLP_IRQHandler - PUBWEAK ETHERNET_MACLP_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ETHERNET_MACLP_IRQHandler - LDR R0, =ETHERNET_MACLP_DriverIRQHandler - BX R0 - PUBWEAK EEPROM_IRQHandler - PUBWEAK EEPROM_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -EEPROM_IRQHandler - LDR R0, =EEPROM_DriverIRQHandler - BX R0 - PUBWEAK LCD_IRQHandler - PUBWEAK LCD_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LCD_IRQHandler - LDR R0, =LCD_DriverIRQHandler - BX R0 - PUBWEAK SHA_IRQHandler - PUBWEAK SHA_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SHA_IRQHandler - LDR R0, =SHA_DriverIRQHandler - BX R0 - PUBWEAK SMARTCARD0_IRQHandler - PUBWEAK SMARTCARD0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SMARTCARD0_IRQHandler - LDR R0, =SMARTCARD0_DriverIRQHandler - BX R0 - PUBWEAK SMARTCARD1_IRQHandler - PUBWEAK SMARTCARD1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SMARTCARD1_IRQHandler - LDR R0, =SMARTCARD1_DriverIRQHandler - BX R0 -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_SEQA_DriverIRQHandler -ADC0_SEQB_DriverIRQHandler -ADC0_THCMP_DriverIRQHandler -DMIC0_DriverIRQHandler -HWVAD0_DriverIRQHandler -USB0_NEEDCLK_DriverIRQHandler -USB0_DriverIRQHandler -RTC_DriverIRQHandler -Reserved46_DriverIRQHandler -Reserved47_DriverIRQHandler -PIN_INT4_DriverIRQHandler -PIN_INT5_DriverIRQHandler -PIN_INT6_DriverIRQHandler -PIN_INT7_DriverIRQHandler -CTIMER2_DriverIRQHandler -CTIMER4_DriverIRQHandler -RIT_DriverIRQHandler -SPIFI0_DriverIRQHandler -FLEXCOMM8_DriverIRQHandler -FLEXCOMM9_DriverIRQHandler -SDIO_DriverIRQHandler -CAN0_IRQ0_DriverIRQHandler -CAN0_IRQ1_DriverIRQHandler -CAN1_IRQ0_DriverIRQHandler -CAN1_IRQ1_DriverIRQHandler -USB1_DriverIRQHandler -USB1_NEEDCLK_DriverIRQHandler -ETHERNET_DriverIRQHandler -ETHERNET_PMT_DriverIRQHandler -ETHERNET_MACLP_DriverIRQHandler -EEPROM_DriverIRQHandler -LCD_DriverIRQHandler -SHA_DriverIRQHandler -SMARTCARD0_DriverIRQHandler -SMARTCARD1_DriverIRQHandler -DefaultISR - B . - - END diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/mcuxpresso/SConscript b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/mcuxpresso/SConscript deleted file mode 100644 index 4bc6992a4ee..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/mcuxpresso/SConscript +++ /dev/null @@ -1,26 +0,0 @@ -from building import * -Import('rtconfig') - -# handle softfp or hard -flags = rtconfig.CFLAGS.split(' ') -softfp = 'softfp' -for item in flags: - if item.find('-mfloat-abi='): - if item.find('hard'): - softfp = 'hard' - else: - softfp = 'softfp' - -cwd = GetCurrentDir() -src = Split(''' -startup_LPC54608.c -''') - -if softfp == 'softfp': - LIBS = ['fsl_power_lib_softabi'] -else: - LIBS = ['fsl_power_lib'] - -group = DefineGroup('CMSIS', src, depend = [''], LIBS=LIBS, LIBPATH=[cwd]) - -Return('group') diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/mcuxpresso/libfsl_power_lib.a b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/mcuxpresso/libfsl_power_lib.a deleted file mode 100644 index cea3fb8e017..00000000000 Binary files a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/mcuxpresso/libfsl_power_lib.a and /dev/null differ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/mcuxpresso/libfsl_power_lib_softabi.a b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/mcuxpresso/libfsl_power_lib_softabi.a deleted file mode 100644 index 207d0c95556..00000000000 Binary files a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/mcuxpresso/libfsl_power_lib_softabi.a and /dev/null differ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/mcuxpresso/startup_LPC54608.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/mcuxpresso/startup_LPC54608.c deleted file mode 100644 index a504256227d..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/mcuxpresso/startup_LPC54608.c +++ /dev/null @@ -1,778 +0,0 @@ -//***************************************************************************** -// LPC54608 startup code for use with MCUXpresso IDE -// -// Version : 070217 -//***************************************************************************** -// -// Copyright(C) NXP Semiconductors, 2017 -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// -// o Redistributions of source code must retain the above copyright notice, this list -// of conditions and the following disclaimer. -// -// o Redistributions in binary form must reproduce the above copyright notice, this -// list of conditions and the following disclaimer in the documentation and/or -// other materials provided with the distribution. -// -// o Neither the name of copyright holder nor the names of its -// contributors may be used to endorse or promote products derived from this -// software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -//***************************************************************************** - -#if defined (DEBUG) -#pragma GCC push_options -#pragma GCC optimize ("Og") -#endif // (DEBUG) - -#if defined (__cplusplus) -#ifdef __REDLIB__ -#error Redlib does not support C++ -#else -//***************************************************************************** -// -// The entry point for the C++ library startup -// -//***************************************************************************** -extern "C" { - extern void __libc_init_array(void); -} -#endif -#endif - -#define WEAK __attribute__ ((weak)) -#define WEAK_AV __attribute__ ((weak, section(".after_vectors"))) -#define ALIAS(f) __attribute__ ((weak, alias (#f))) - -//***************************************************************************** -#if defined (__cplusplus) -extern "C" { -#endif - -//***************************************************************************** -// Variable to store CRP value in. Will be placed automatically -// by the linker when "Enable Code Read Protect" selected. -// See crp.h header for more information -//***************************************************************************** -// #include -// __CRP const unsigned int CRP_WORD = CRP_NO_CRP ; - -//***************************************************************************** -// Declaration of external SystemInit function -//***************************************************************************** -#if defined (__USE_CMSIS) -extern void SystemInit(void); -#endif // (__USE_CMSIS) - -//***************************************************************************** -// Forward declaration of the core exception handlers. -// When the application defines a handler (with the same name), this will -// automatically take precedence over these weak definitions -//***************************************************************************** - void Reset_Handler(void); -WEAK void NMI_Handler(void); -WEAK void HardFault_Handler(void); -WEAK void MemManage_Handler(void); -WEAK void BusFault_Handler(void); -WEAK void UsageFault_Handler(void); -WEAK void SVC_Handler(void); -WEAK void DebugMon_Handler(void); -WEAK void PendSV_Handler(void); -WEAK void SysTick_Handler(void); -WEAK void IntDefaultHandler(void); - -//***************************************************************************** -// Forward declaration of the application IRQ handlers. When the application -// defines a handler (with the same name), this will automatically take -// precedence over weak definitions below -//***************************************************************************** -WEAK void WDT_BOD_IRQHandler(void); -WEAK void DMA0_IRQHandler(void); -WEAK void GINT0_IRQHandler(void); -WEAK void GINT1_IRQHandler(void); -WEAK void PIN_INT0_IRQHandler(void); -WEAK void PIN_INT1_IRQHandler(void); -WEAK void PIN_INT2_IRQHandler(void); -WEAK void PIN_INT3_IRQHandler(void); -WEAK void UTICK0_IRQHandler(void); -WEAK void MRT0_IRQHandler(void); -WEAK void CTIMER0_IRQHandler(void); -WEAK void CTIMER1_IRQHandler(void); -WEAK void SCT0_IRQHandler(void); -WEAK void CTIMER3_IRQHandler(void); -WEAK void FLEXCOMM0_IRQHandler(void); -WEAK void FLEXCOMM1_IRQHandler(void); -WEAK void FLEXCOMM2_IRQHandler(void); -WEAK void FLEXCOMM3_IRQHandler(void); -WEAK void FLEXCOMM4_IRQHandler(void); -WEAK void FLEXCOMM5_IRQHandler(void); -WEAK void FLEXCOMM6_IRQHandler(void); -WEAK void FLEXCOMM7_IRQHandler(void); -WEAK void ADC0_SEQA_IRQHandler(void); -WEAK void ADC0_SEQB_IRQHandler(void); -WEAK void ADC0_THCMP_IRQHandler(void); -WEAK void DMIC0_IRQHandler(void); -WEAK void HWVAD0_IRQHandler(void); -WEAK void USB0_NEEDCLK_IRQHandler(void); -WEAK void USB0_IRQHandler(void); -WEAK void RTC_IRQHandler(void); -WEAK void Reserved46_IRQHandler(void); -WEAK void Reserved47_IRQHandler(void); -WEAK void PIN_INT4_IRQHandler(void); -WEAK void PIN_INT5_IRQHandler(void); -WEAK void PIN_INT6_IRQHandler(void); -WEAK void PIN_INT7_IRQHandler(void); -WEAK void CTIMER2_IRQHandler(void); -WEAK void CTIMER4_IRQHandler(void); -WEAK void RIT_IRQHandler(void); -WEAK void SPIFI0_IRQHandler(void); -WEAK void FLEXCOMM8_IRQHandler(void); -WEAK void FLEXCOMM9_IRQHandler(void); -WEAK void SDIO_IRQHandler(void); -WEAK void CAN0_IRQ0_IRQHandler(void); -WEAK void CAN0_IRQ1_IRQHandler(void); -WEAK void CAN1_IRQ0_IRQHandler(void); -WEAK void CAN1_IRQ1_IRQHandler(void); -WEAK void USB1_IRQHandler(void); -WEAK void USB1_NEEDCLK_IRQHandler(void); -WEAK void ETHERNET_IRQHandler(void); -WEAK void ETHERNET_PMT_IRQHandler(void); -WEAK void ETHERNET_MACLP_IRQHandler(void); -WEAK void EEPROM_IRQHandler(void); -WEAK void LCD_IRQHandler(void); -WEAK void SHA_IRQHandler(void); -WEAK void SMARTCARD0_IRQHandler(void); -WEAK void SMARTCARD1_IRQHandler(void); - -//***************************************************************************** -// Forward declaration of the driver IRQ handlers. These are aliased -// to the IntDefaultHandler, which is a 'forever' loop. When the driver -// defines a handler (with the same name), this will automatically take -// precedence over these weak definitions -//***************************************************************************** -void WDT_BOD_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void DMA0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void GINT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void GINT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void UTICK0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void MRT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void SCT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void CTIMER3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void ADC0_SEQA_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void ADC0_SEQB_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void ADC0_THCMP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void DMIC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void HWVAD0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void USB0_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void USB0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void Reserved46_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void Reserved47_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void CTIMER2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void CTIMER4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void RIT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void SPIFI0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM8_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM9_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void SDIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void CAN0_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void CAN0_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void CAN1_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void CAN1_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void USB1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void USB1_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void ETHERNET_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void ETHERNET_PMT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void ETHERNET_MACLP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void EEPROM_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void LCD_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void SHA_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void SMARTCARD0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void SMARTCARD1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); - -//***************************************************************************** -// The entry point for the application. -// __main() is the entry point for Redlib based applications -// main() is the entry point for Newlib based applications -//***************************************************************************** -#if defined (__REDLIB__) -extern void __main(void); -#endif -extern int main(void); - -//***************************************************************************** -// External declaration for the pointer to the stack top from the Linker Script -//***************************************************************************** -extern void _estack(void); - -//***************************************************************************** -// External declaration for LPC MCU vector table checksum from Linker Script -//***************************************************************************** -WEAK extern void __valid_user_code_checksum(); - -//***************************************************************************** -#if defined (__cplusplus) -} // extern "C" -#endif - -//***************************************************************************** -// The vector table. -// This relies on the linker script to place at correct location in memory. -//***************************************************************************** -extern void (* const g_pfnVectors[])(void); -extern void * __Vectors __attribute__ ((alias ("g_pfnVectors"))); - -__attribute__ ((used, section(".isr_vector"))) -void (* const g_pfnVectors[])(void) = { - // Core Level - CM4 - &_estack, // The initial stack pointer - Reset_Handler, // The reset handler - NMI_Handler, // The NMI handler - HardFault_Handler, // The hard fault handler - MemManage_Handler, // The MPU fault handler - BusFault_Handler, // The bus fault handler - UsageFault_Handler, // The usage fault handler - __valid_user_code_checksum, // LPC MCU checksum - 0, // ECRP - 0, // Reserved - 0, // Reserved - SVC_Handler, // SVCall handler - DebugMon_Handler, // Debug monitor handler - 0, // Reserved - PendSV_Handler, // The PendSV handler - SysTick_Handler, // The SysTick handler - - // Chip Level - LPC54608 - WDT_BOD_IRQHandler, // 16: Windowed watchdog timer, Brownout detect - DMA0_IRQHandler, // 17: DMA controller - GINT0_IRQHandler, // 18: GPIO group 0 - GINT1_IRQHandler, // 19: GPIO group 1 - PIN_INT0_IRQHandler, // 20: Pin interrupt 0 or pattern match engine slice 0 - PIN_INT1_IRQHandler, // 21: Pin interrupt 1or pattern match engine slice 1 - PIN_INT2_IRQHandler, // 22: Pin interrupt 2 or pattern match engine slice 2 - PIN_INT3_IRQHandler, // 23: Pin interrupt 3 or pattern match engine slice 3 - UTICK0_IRQHandler, // 24: Micro-tick Timer - MRT0_IRQHandler, // 25: Multi-rate timer - CTIMER0_IRQHandler, // 26: Standard counter/timer CTIMER0 - CTIMER1_IRQHandler, // 27: Standard counter/timer CTIMER1 - SCT0_IRQHandler, // 28: SCTimer/PWM - CTIMER3_IRQHandler, // 29: Standard counter/timer CTIMER3 - FLEXCOMM0_IRQHandler, // 30: Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) - FLEXCOMM1_IRQHandler, // 31: Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) - FLEXCOMM2_IRQHandler, // 32: Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) - FLEXCOMM3_IRQHandler, // 33: Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) - FLEXCOMM4_IRQHandler, // 34: Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) - FLEXCOMM5_IRQHandler, // 35: Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) - FLEXCOMM6_IRQHandler, // 36: Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) - FLEXCOMM7_IRQHandler, // 37: Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) - ADC0_SEQA_IRQHandler, // 38: ADC0 sequence A completion. - ADC0_SEQB_IRQHandler, // 39: ADC0 sequence B completion. - ADC0_THCMP_IRQHandler, // 40: ADC0 threshold compare and error. - DMIC0_IRQHandler, // 41: Digital microphone and DMIC subsystem - HWVAD0_IRQHandler, // 42: Hardware Voice Activity Detector - USB0_NEEDCLK_IRQHandler, // 43: USB Activity Wake-up Interrupt - USB0_IRQHandler, // 44: USB device - RTC_IRQHandler, // 45: RTC alarm and wake-up interrupts - Reserved46_IRQHandler, // 46: Reserved interrupt - Reserved47_IRQHandler, // 47: Reserved interrupt - PIN_INT4_IRQHandler, // 48: Pin interrupt 4 or pattern match engine slice 4 int - PIN_INT5_IRQHandler, // 49: Pin interrupt 5 or pattern match engine slice 5 int - PIN_INT6_IRQHandler, // 50: Pin interrupt 6 or pattern match engine slice 6 int - PIN_INT7_IRQHandler, // 51: Pin interrupt 7 or pattern match engine slice 7 int - CTIMER2_IRQHandler, // 52: Standard counter/timer CTIMER2 - CTIMER4_IRQHandler, // 53: Standard counter/timer CTIMER4 - RIT_IRQHandler, // 54: Repetitive Interrupt Timer - SPIFI0_IRQHandler, // 55: SPI flash interface - FLEXCOMM8_IRQHandler, // 56: Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) - FLEXCOMM9_IRQHandler, // 57: Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) - SDIO_IRQHandler, // 58: SD/MMC - CAN0_IRQ0_IRQHandler, // 59: CAN0 interrupt0 - CAN0_IRQ1_IRQHandler, // 60: CAN0 interrupt1 - CAN1_IRQ0_IRQHandler, // 61: CAN1 interrupt0 - CAN1_IRQ1_IRQHandler, // 62: CAN1 interrupt1 - USB1_IRQHandler, // 63: USB1 interrupt - USB1_NEEDCLK_IRQHandler, // 64: USB1 activity - ETHERNET_IRQHandler, // 65: Ethernet - ETHERNET_PMT_IRQHandler, // 66: Ethernet power management interrupt - ETHERNET_MACLP_IRQHandler, // 67: Ethernet MAC interrupt - EEPROM_IRQHandler, // 68: EEPROM interrupt - LCD_IRQHandler, // 69: LCD interrupt - SHA_IRQHandler, // 70: SHA interrupt - SMARTCARD0_IRQHandler, // 71: Smart card 0 interrupt - SMARTCARD1_IRQHandler, // 72: Smart card 1 interrupt -}; /* End of g_pfnVectors */ - -//***************************************************************************** -// Functions to carry out the initialization of RW and BSS data sections. These -// are written as separate functions rather than being inlined within the -// Reset_Handler() function in order to cope with MCUs with multiple banks of -// memory. -//***************************************************************************** -__attribute__ ((section(".after_vectors.init_data"))) -void data_init(unsigned int romstart, unsigned int start, unsigned int len) { - unsigned int *pulDest = (unsigned int*) start; - unsigned int *pulSrc = (unsigned int*) romstart; - unsigned int loop; - for (loop = 0; loop < len; loop = loop + 4) - *pulDest++ = *pulSrc++; -} - -__attribute__ ((section(".after_vectors.init_bss"))) -void bss_init(unsigned int start, unsigned int len) { - unsigned int *pulDest = (unsigned int*) start; - unsigned int loop; - for (loop = 0; loop < len; loop = loop + 4) - *pulDest++ = 0; -} - -//***************************************************************************** -// The following symbols are constructs generated by the linker, indicating -// the location of various points in the "Global Section Table". This table is -// created by the linker via the Code Red managed linker script mechanism. It -// contains the load address, execution address and length of each RW data -// section and the execution and length of each BSS (zero initialized) section. -//***************************************************************************** -extern unsigned int _sdata; -extern unsigned int _edata; -extern unsigned int _sidata; - -extern unsigned int _sbss; -extern unsigned int _ebss; - -//***************************************************************************** -//Reset entry point for your code. -//Sets up a simple runtime environment and initializes the C/C++ -//library. -//***************************************************************************** -__attribute__ ((section(".after_vectors.reset"))) -void Reset_Handler(void) { - /* Data and BSS variables */ - unsigned int *srcdata, *dstdata, *sbss; - - // Disable interrupts - __asm volatile ("cpsid i"); - - // Enable SRAM clock used by Stack - __asm volatile ("LDR R0, =0x40000220\n\t" - "MOV R1, #56\n\t" - "STR R1, [R0]"); - - // extern void Reset_ASM_Handler(); - // Reset_ASM_Handler(); - - srcdata = &_sidata; - dstdata = &_sdata; - sbss = &_sbss; - - /* Copy data */ - while(dstdata != &_edata) - { - *(dstdata++) = *(srcdata++); - } - - /* Clear BSS */ - while(sbss != &_ebss) - { - *(sbss++) = '\0'; - } - -#if defined (__USE_CMSIS) -// If __USE_CMSIS defined, then call CMSIS SystemInit code - SystemInit(); -#endif // (__USE_CMSIS) - - // // - // // Copy the data sections from flash to SRAM. - // // - // //data_init(_sidata, _sdata, _edata - _sdata); - - // // At this point, SectionTableAddr = &__bss_section_table; - // // Zero fill the bss segment - // //bss_init(_sbss, _ebss - _sbss); - //bss_init(_sbss, _ebss - _sbss); - - -#if !defined (__USE_CMSIS) -// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code -// will enable the FPU -#if defined (__VFP_FP__) && !defined (__SOFTFP__) - // - // Code to enable the Cortex-M4 FPU only included - // if appropriate build options have been selected. - // Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C) - // - // Read CPACR (located at address 0xE000ED88) - // Set bits 20-23 to enable CP10 and CP11 coprocessors - // Write back the modified value to the CPACR - __asm volatile ("LDR.W R0, =0xE000ED88\n\t" - "LDR R1, [R0]\n\t" - "ORR R1, R1, #(0xF << 20)\n\t" - "STR R1, [R0]"); -#endif // (__VFP_FP__) && !(__SOFTFP__) -#endif // (__USE_CMSIS) - -#if !defined (__USE_CMSIS) -// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code -// will setup the VTOR register - - // Check to see if we are running the code from a non-zero - // address (eg RAM, external flash), in which case we need - // to modify the VTOR register to tell the CPU that the - // vector table is located at a non-0x0 address. - unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; - if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) { - *pSCB_VTOR = (unsigned int)g_pfnVectors; - } -#endif // (__USE_CMSIS) - -#if defined (__cplusplus) - // - // Call C++ library initialisation - // - __libc_init_array(); -#endif - - // Reenable interrupts - __asm volatile ("cpsie i"); - -#if defined(__REDLIB__) - // Call the Redlib library, which in turn calls main() - __main(); -#elif defined(__GNUC__) - extern void entry(void); - entry(); -#elif defined(__ICCARM__) - extern void __low_level_init(void); - __low_level_init(); -#else - /* Jump to main. */ - main(); - -#endif - - // - // main() shouldn't return, but if it does, we'll just enter an infinite loop - // - while (1) { - ; - } -} - -//***************************************************************************** -// Default core exception handlers. Override the ones here by defining your own -// handler routines in your application code. -//***************************************************************************** -WEAK_AV void NMI_Handler(void) -{ while(1) {} -} - -WEAK_AV void HardFault_Handler(void) -{ while(1) {} -} - -WEAK_AV void MemManage_Handler(void) -{ while(1) {} -} - -WEAK_AV void BusFault_Handler(void) -{ while(1) {} -} - -WEAK_AV void UsageFault_Handler(void) -{ while(1) {} -} - -WEAK_AV void SVC_Handler(void) -{ while(1) {} -} - -WEAK_AV void DebugMon_Handler(void) -{ while(1) {} -} - -WEAK_AV void PendSV_Handler(void) -{ while(1) {} -} - -WEAK_AV void SysTick_Handler(void) -{ while(1) {} -} - -//***************************************************************************** -// Processor ends up here if an unexpected interrupt occurs or a specific -// handler is not present in the application code. -//***************************************************************************** -WEAK_AV void IntDefaultHandler(void) -{ while(1) {} -} - -//***************************************************************************** -// Default application exception handlers. Override the ones here by defining -// your own handler routines in your application code. These routines call -// driver exception handlers or IntDefaultHandler() if no driver exception -// handler is included. -//***************************************************************************** -WEAK void WDT_BOD_IRQHandler(void) -{ WDT_BOD_DriverIRQHandler(); -} - -WEAK void DMA0_IRQHandler(void) -{ DMA0_DriverIRQHandler(); -} - -WEAK void GINT0_IRQHandler(void) -{ GINT0_DriverIRQHandler(); -} - -WEAK void GINT1_IRQHandler(void) -{ GINT1_DriverIRQHandler(); -} - -WEAK void PIN_INT0_IRQHandler(void) -{ PIN_INT0_DriverIRQHandler(); -} - -WEAK void PIN_INT1_IRQHandler(void) -{ PIN_INT1_DriverIRQHandler(); -} - -WEAK void PIN_INT2_IRQHandler(void) -{ PIN_INT2_DriverIRQHandler(); -} - -WEAK void PIN_INT3_IRQHandler(void) -{ PIN_INT3_DriverIRQHandler(); -} - -WEAK void UTICK0_IRQHandler(void) -{ UTICK0_DriverIRQHandler(); -} - -WEAK void MRT0_IRQHandler(void) -{ MRT0_DriverIRQHandler(); -} - -WEAK void CTIMER0_IRQHandler(void) -{ CTIMER0_DriverIRQHandler(); -} - -WEAK void CTIMER1_IRQHandler(void) -{ CTIMER1_DriverIRQHandler(); -} - -WEAK void SCT0_IRQHandler(void) -{ SCT0_DriverIRQHandler(); -} - -WEAK void CTIMER3_IRQHandler(void) -{ CTIMER3_DriverIRQHandler(); -} - -WEAK void FLEXCOMM0_IRQHandler(void) -{ FLEXCOMM0_DriverIRQHandler(); -} - -WEAK void FLEXCOMM1_IRQHandler(void) -{ FLEXCOMM1_DriverIRQHandler(); -} - -WEAK void FLEXCOMM2_IRQHandler(void) -{ FLEXCOMM2_DriverIRQHandler(); -} - -WEAK void FLEXCOMM3_IRQHandler(void) -{ FLEXCOMM3_DriverIRQHandler(); -} - -WEAK void FLEXCOMM4_IRQHandler(void) -{ FLEXCOMM4_DriverIRQHandler(); -} - -WEAK void FLEXCOMM5_IRQHandler(void) -{ FLEXCOMM5_DriverIRQHandler(); -} - -WEAK void FLEXCOMM6_IRQHandler(void) -{ FLEXCOMM6_DriverIRQHandler(); -} - -WEAK void FLEXCOMM7_IRQHandler(void) -{ FLEXCOMM7_DriverIRQHandler(); -} - -WEAK void ADC0_SEQA_IRQHandler(void) -{ ADC0_SEQA_DriverIRQHandler(); -} - -WEAK void ADC0_SEQB_IRQHandler(void) -{ ADC0_SEQB_DriverIRQHandler(); -} - -WEAK void ADC0_THCMP_IRQHandler(void) -{ ADC0_THCMP_DriverIRQHandler(); -} - -WEAK void DMIC0_IRQHandler(void) -{ DMIC0_DriverIRQHandler(); -} - -WEAK void HWVAD0_IRQHandler(void) -{ HWVAD0_DriverIRQHandler(); -} - -WEAK void USB0_NEEDCLK_IRQHandler(void) -{ USB0_NEEDCLK_DriverIRQHandler(); -} - -WEAK void USB0_IRQHandler(void) -{ USB0_DriverIRQHandler(); -} - -WEAK void RTC_IRQHandler(void) -{ RTC_DriverIRQHandler(); -} - -WEAK void Reserved46_IRQHandler(void) -{ Reserved46_DriverIRQHandler(); -} - -WEAK void Reserved47_IRQHandler(void) -{ Reserved47_DriverIRQHandler(); -} - -WEAK void PIN_INT4_IRQHandler(void) -{ PIN_INT4_DriverIRQHandler(); -} - -WEAK void PIN_INT5_IRQHandler(void) -{ PIN_INT5_DriverIRQHandler(); -} - -WEAK void PIN_INT6_IRQHandler(void) -{ PIN_INT6_DriverIRQHandler(); -} - -WEAK void PIN_INT7_IRQHandler(void) -{ PIN_INT7_DriverIRQHandler(); -} - -WEAK void CTIMER2_IRQHandler(void) -{ CTIMER2_DriverIRQHandler(); -} - -WEAK void CTIMER4_IRQHandler(void) -{ CTIMER4_DriverIRQHandler(); -} - -WEAK void RIT_IRQHandler(void) -{ RIT_DriverIRQHandler(); -} - -WEAK void SPIFI0_IRQHandler(void) -{ SPIFI0_DriverIRQHandler(); -} - -WEAK void FLEXCOMM8_IRQHandler(void) -{ FLEXCOMM8_DriverIRQHandler(); -} - -WEAK void FLEXCOMM9_IRQHandler(void) -{ FLEXCOMM9_DriverIRQHandler(); -} - -WEAK void SDIO_IRQHandler(void) -{ SDIO_DriverIRQHandler(); -} - -WEAK void CAN0_IRQ0_IRQHandler(void) -{ CAN0_IRQ0_DriverIRQHandler(); -} - -WEAK void CAN0_IRQ1_IRQHandler(void) -{ CAN0_IRQ1_DriverIRQHandler(); -} - -WEAK void CAN1_IRQ0_IRQHandler(void) -{ CAN1_IRQ0_DriverIRQHandler(); -} - -WEAK void CAN1_IRQ1_IRQHandler(void) -{ CAN1_IRQ1_DriverIRQHandler(); -} - -WEAK void USB1_IRQHandler(void) -{ USB1_DriverIRQHandler(); -} - -WEAK void USB1_NEEDCLK_IRQHandler(void) -{ USB1_NEEDCLK_DriverIRQHandler(); -} - -WEAK void ETHERNET_IRQHandler(void) -{ ETHERNET_DriverIRQHandler(); -} - -WEAK void ETHERNET_PMT_IRQHandler(void) -{ ETHERNET_PMT_DriverIRQHandler(); -} - -WEAK void ETHERNET_MACLP_IRQHandler(void) -{ ETHERNET_MACLP_DriverIRQHandler(); -} - -WEAK void EEPROM_IRQHandler(void) -{ EEPROM_DriverIRQHandler(); -} - -WEAK void LCD_IRQHandler(void) -{ LCD_DriverIRQHandler(); -} - -WEAK void SHA_IRQHandler(void) -{ SHA_DriverIRQHandler(); -} - -WEAK void SMARTCARD0_IRQHandler(void) -{ SMARTCARD0_DriverIRQHandler(); -} - -WEAK void SMARTCARD1_IRQHandler(void) -{ SMARTCARD1_DriverIRQHandler(); -} - -//***************************************************************************** - -#if defined (DEBUG) -#pragma GCC pop_options -#endif // (DEBUG) diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/mcuxpresso/startup_LPC54608.cpp b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/mcuxpresso/startup_LPC54608.cpp deleted file mode 100644 index 6d975a864f1..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/mcuxpresso/startup_LPC54608.cpp +++ /dev/null @@ -1,761 +0,0 @@ -//***************************************************************************** -// LPC54608 startup code for use with MCUXpresso IDE -// -// Version : 070217 -//***************************************************************************** -// -// Copyright(C) NXP Semiconductors, 2017 -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// -// o Redistributions of source code must retain the above copyright notice, this list -// of conditions and the following disclaimer. -// -// o Redistributions in binary form must reproduce the above copyright notice, this -// list of conditions and the following disclaimer in the documentation and/or -// other materials provided with the distribution. -// -// o Neither the name of copyright holder nor the names of its -// contributors may be used to endorse or promote products derived from this -// software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -//***************************************************************************** - -#if defined (DEBUG) -#pragma GCC push_options -#pragma GCC optimize ("Og") -#endif // (DEBUG) - -#if defined (__cplusplus) -#ifdef __REDLIB__ -#error Redlib does not support C++ -#else -//***************************************************************************** -// -// The entry point for the C++ library startup -// -//***************************************************************************** -extern "C" { - extern void __libc_init_array(void); -} -#endif -#endif - -#define WEAK __attribute__ ((weak)) -#define WEAK_AV __attribute__ ((weak, section(".after_vectors"))) -#define ALIAS(f) __attribute__ ((weak, alias (#f))) - -//***************************************************************************** -#if defined (__cplusplus) -extern "C" { -#endif - -//***************************************************************************** -// Variable to store CRP value in. Will be placed automatically -// by the linker when "Enable Code Read Protect" selected. -// See crp.h header for more information -//***************************************************************************** -#include -__CRP const unsigned int CRP_WORD = CRP_NO_CRP ; - -//***************************************************************************** -// Declaration of external SystemInit function -//***************************************************************************** -#if defined (__USE_CMSIS) -extern void SystemInit(void); -#endif // (__USE_CMSIS) - -//***************************************************************************** -// Forward declaration of the core exception handlers. -// When the application defines a handler (with the same name), this will -// automatically take precedence over these weak definitions -//***************************************************************************** - void ResetISR(void); -WEAK void NMI_Handler(void); -WEAK void HardFault_Handler(void); -WEAK void MemManage_Handler(void); -WEAK void BusFault_Handler(void); -WEAK void UsageFault_Handler(void); -WEAK void SVC_Handler(void); -WEAK void DebugMon_Handler(void); -WEAK void PendSV_Handler(void); -WEAK void SysTick_Handler(void); -WEAK void IntDefaultHandler(void); - -//***************************************************************************** -// Forward declaration of the application IRQ handlers. When the application -// defines a handler (with the same name), this will automatically take -// precedence over weak definitions below -//***************************************************************************** -WEAK void WDT_BOD_IRQHandler(void); -WEAK void DMA0_IRQHandler(void); -WEAK void GINT0_IRQHandler(void); -WEAK void GINT1_IRQHandler(void); -WEAK void PIN_INT0_IRQHandler(void); -WEAK void PIN_INT1_IRQHandler(void); -WEAK void PIN_INT2_IRQHandler(void); -WEAK void PIN_INT3_IRQHandler(void); -WEAK void UTICK0_IRQHandler(void); -WEAK void MRT0_IRQHandler(void); -WEAK void CTIMER0_IRQHandler(void); -WEAK void CTIMER1_IRQHandler(void); -WEAK void SCT0_IRQHandler(void); -WEAK void CTIMER3_IRQHandler(void); -WEAK void FLEXCOMM0_IRQHandler(void); -WEAK void FLEXCOMM1_IRQHandler(void); -WEAK void FLEXCOMM2_IRQHandler(void); -WEAK void FLEXCOMM3_IRQHandler(void); -WEAK void FLEXCOMM4_IRQHandler(void); -WEAK void FLEXCOMM5_IRQHandler(void); -WEAK void FLEXCOMM6_IRQHandler(void); -WEAK void FLEXCOMM7_IRQHandler(void); -WEAK void ADC0_SEQA_IRQHandler(void); -WEAK void ADC0_SEQB_IRQHandler(void); -WEAK void ADC0_THCMP_IRQHandler(void); -WEAK void DMIC0_IRQHandler(void); -WEAK void HWVAD0_IRQHandler(void); -WEAK void USB0_NEEDCLK_IRQHandler(void); -WEAK void USB0_IRQHandler(void); -WEAK void RTC_IRQHandler(void); -WEAK void Reserved46_IRQHandler(void); -WEAK void Reserved47_IRQHandler(void); -WEAK void PIN_INT4_IRQHandler(void); -WEAK void PIN_INT5_IRQHandler(void); -WEAK void PIN_INT6_IRQHandler(void); -WEAK void PIN_INT7_IRQHandler(void); -WEAK void CTIMER2_IRQHandler(void); -WEAK void CTIMER4_IRQHandler(void); -WEAK void RIT_IRQHandler(void); -WEAK void SPIFI0_IRQHandler(void); -WEAK void FLEXCOMM8_IRQHandler(void); -WEAK void FLEXCOMM9_IRQHandler(void); -WEAK void SDIO_IRQHandler(void); -WEAK void CAN0_IRQ0_IRQHandler(void); -WEAK void CAN0_IRQ1_IRQHandler(void); -WEAK void CAN1_IRQ0_IRQHandler(void); -WEAK void CAN1_IRQ1_IRQHandler(void); -WEAK void USB1_IRQHandler(void); -WEAK void USB1_NEEDCLK_IRQHandler(void); -WEAK void ETHERNET_IRQHandler(void); -WEAK void ETHERNET_PMT_IRQHandler(void); -WEAK void ETHERNET_MACLP_IRQHandler(void); -WEAK void EEPROM_IRQHandler(void); -WEAK void LCD_IRQHandler(void); -WEAK void SHA_IRQHandler(void); -WEAK void SMARTCARD0_IRQHandler(void); -WEAK void SMARTCARD1_IRQHandler(void); - -//***************************************************************************** -// Forward declaration of the driver IRQ handlers. These are aliased -// to the IntDefaultHandler, which is a 'forever' loop. When the driver -// defines a handler (with the same name), this will automatically take -// precedence over these weak definitions -//***************************************************************************** -void WDT_BOD_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void DMA0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void GINT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void GINT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void UTICK0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void MRT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void SCT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void CTIMER3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void ADC0_SEQA_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void ADC0_SEQB_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void ADC0_THCMP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void DMIC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void HWVAD0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void USB0_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void USB0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void Reserved46_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void Reserved47_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void CTIMER2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void CTIMER4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void RIT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void SPIFI0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM8_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM9_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void SDIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void CAN0_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void CAN0_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void CAN1_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void CAN1_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void USB1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void USB1_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void ETHERNET_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void ETHERNET_PMT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void ETHERNET_MACLP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void EEPROM_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void LCD_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void SHA_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void SMARTCARD0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void SMARTCARD1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); - -//***************************************************************************** -// The entry point for the application. -// __main() is the entry point for Redlib based applications -// main() is the entry point for Newlib based applications -//***************************************************************************** -#if defined (__REDLIB__) -extern void __main(void); -#endif -extern int main(void); - -//***************************************************************************** -// External declaration for the pointer to the stack top from the Linker Script -//***************************************************************************** -extern void _vStackTop(void); - -//***************************************************************************** -// External declaration for LPC MCU vector table checksum from Linker Script -//***************************************************************************** -WEAK extern void __valid_user_code_checksum(); - -//***************************************************************************** -#if defined (__cplusplus) -} // extern "C" -#endif - -//***************************************************************************** -// The vector table. -// This relies on the linker script to place at correct location in memory. -//***************************************************************************** -extern void (* const g_pfnVectors[])(void); -extern void * __Vectors __attribute__ ((alias ("g_pfnVectors"))); - -__attribute__ ((used, section(".isr_vector"))) -void (* const g_pfnVectors[])(void) = { - // Core Level - CM4 - &_vStackTop, // The initial stack pointer - ResetISR, // The reset handler - NMI_Handler, // The NMI handler - HardFault_Handler, // The hard fault handler - MemManage_Handler, // The MPU fault handler - BusFault_Handler, // The bus fault handler - UsageFault_Handler, // The usage fault handler - __valid_user_code_checksum, // LPC MCU checksum - 0, // ECRP - 0, // Reserved - 0, // Reserved - SVC_Handler, // SVCall handler - DebugMon_Handler, // Debug monitor handler - 0, // Reserved - PendSV_Handler, // The PendSV handler - SysTick_Handler, // The SysTick handler - - // Chip Level - LPC54608 - WDT_BOD_IRQHandler, // 16: Windowed watchdog timer, Brownout detect - DMA0_IRQHandler, // 17: DMA controller - GINT0_IRQHandler, // 18: GPIO group 0 - GINT1_IRQHandler, // 19: GPIO group 1 - PIN_INT0_IRQHandler, // 20: Pin interrupt 0 or pattern match engine slice 0 - PIN_INT1_IRQHandler, // 21: Pin interrupt 1or pattern match engine slice 1 - PIN_INT2_IRQHandler, // 22: Pin interrupt 2 or pattern match engine slice 2 - PIN_INT3_IRQHandler, // 23: Pin interrupt 3 or pattern match engine slice 3 - UTICK0_IRQHandler, // 24: Micro-tick Timer - MRT0_IRQHandler, // 25: Multi-rate timer - CTIMER0_IRQHandler, // 26: Standard counter/timer CTIMER0 - CTIMER1_IRQHandler, // 27: Standard counter/timer CTIMER1 - SCT0_IRQHandler, // 28: SCTimer/PWM - CTIMER3_IRQHandler, // 29: Standard counter/timer CTIMER3 - FLEXCOMM0_IRQHandler, // 30: Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) - FLEXCOMM1_IRQHandler, // 31: Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) - FLEXCOMM2_IRQHandler, // 32: Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) - FLEXCOMM3_IRQHandler, // 33: Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) - FLEXCOMM4_IRQHandler, // 34: Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) - FLEXCOMM5_IRQHandler, // 35: Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) - FLEXCOMM6_IRQHandler, // 36: Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) - FLEXCOMM7_IRQHandler, // 37: Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) - ADC0_SEQA_IRQHandler, // 38: ADC0 sequence A completion. - ADC0_SEQB_IRQHandler, // 39: ADC0 sequence B completion. - ADC0_THCMP_IRQHandler, // 40: ADC0 threshold compare and error. - DMIC0_IRQHandler, // 41: Digital microphone and DMIC subsystem - HWVAD0_IRQHandler, // 42: Hardware Voice Activity Detector - USB0_NEEDCLK_IRQHandler, // 43: USB Activity Wake-up Interrupt - USB0_IRQHandler, // 44: USB device - RTC_IRQHandler, // 45: RTC alarm and wake-up interrupts - Reserved46_IRQHandler, // 46: Reserved interrupt - Reserved47_IRQHandler, // 47: Reserved interrupt - PIN_INT4_IRQHandler, // 48: Pin interrupt 4 or pattern match engine slice 4 int - PIN_INT5_IRQHandler, // 49: Pin interrupt 5 or pattern match engine slice 5 int - PIN_INT6_IRQHandler, // 50: Pin interrupt 6 or pattern match engine slice 6 int - PIN_INT7_IRQHandler, // 51: Pin interrupt 7 or pattern match engine slice 7 int - CTIMER2_IRQHandler, // 52: Standard counter/timer CTIMER2 - CTIMER4_IRQHandler, // 53: Standard counter/timer CTIMER4 - RIT_IRQHandler, // 54: Repetitive Interrupt Timer - SPIFI0_IRQHandler, // 55: SPI flash interface - FLEXCOMM8_IRQHandler, // 56: Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) - FLEXCOMM9_IRQHandler, // 57: Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) - SDIO_IRQHandler, // 58: SD/MMC - CAN0_IRQ0_IRQHandler, // 59: CAN0 interrupt0 - CAN0_IRQ1_IRQHandler, // 60: CAN0 interrupt1 - CAN1_IRQ0_IRQHandler, // 61: CAN1 interrupt0 - CAN1_IRQ1_IRQHandler, // 62: CAN1 interrupt1 - USB1_IRQHandler, // 63: USB1 interrupt - USB1_NEEDCLK_IRQHandler, // 64: USB1 activity - ETHERNET_IRQHandler, // 65: Ethernet - ETHERNET_PMT_IRQHandler, // 66: Ethernet power management interrupt - ETHERNET_MACLP_IRQHandler, // 67: Ethernet MAC interrupt - EEPROM_IRQHandler, // 68: EEPROM interrupt - LCD_IRQHandler, // 69: LCD interrupt - SHA_IRQHandler, // 70: SHA interrupt - SMARTCARD0_IRQHandler, // 71: Smart card 0 interrupt - SMARTCARD1_IRQHandler, // 72: Smart card 1 interrupt -}; /* End of g_pfnVectors */ - -//***************************************************************************** -// Functions to carry out the initialization of RW and BSS data sections. These -// are written as separate functions rather than being inlined within the -// ResetISR() function in order to cope with MCUs with multiple banks of -// memory. -//***************************************************************************** -__attribute__ ((section(".after_vectors.init_data"))) -void data_init(unsigned int romstart, unsigned int start, unsigned int len) { - unsigned int *pulDest = (unsigned int*) start; - unsigned int *pulSrc = (unsigned int*) romstart; - unsigned int loop; - for (loop = 0; loop < len; loop = loop + 4) - *pulDest++ = *pulSrc++; -} - -__attribute__ ((section(".after_vectors.init_bss"))) -void bss_init(unsigned int start, unsigned int len) { - unsigned int *pulDest = (unsigned int*) start; - unsigned int loop; - for (loop = 0; loop < len; loop = loop + 4) - *pulDest++ = 0; -} - -//***************************************************************************** -// The following symbols are constructs generated by the linker, indicating -// the location of various points in the "Global Section Table". This table is -// created by the linker via the Code Red managed linker script mechanism. It -// contains the load address, execution address and length of each RW data -// section and the execution and length of each BSS (zero initialized) section. -//***************************************************************************** -extern unsigned int __data_section_table; -extern unsigned int __data_section_table_end; -extern unsigned int __bss_section_table; -extern unsigned int __bss_section_table_end; - -//***************************************************************************** -// Reset entry point for your code. -// Sets up a simple runtime environment and initializes the C/C++ -// library. -//***************************************************************************** -__attribute__ ((section(".after_vectors.reset"))) -void ResetISR(void) { - - // Disable interrupts - __asm volatile ("cpsid i"); - - // Enable SRAM clock used by Stack - __asm volatile ("LDR R0, =0x40000220\n\t" - "MOV R1, #56\n\t" - "STR R1, [R0]"); - -#if defined (__USE_CMSIS) -// If __USE_CMSIS defined, then call CMSIS SystemInit code - SystemInit(); -#endif // (__USE_CMSIS) - - // - // Copy the data sections from flash to SRAM. - // - unsigned int LoadAddr, ExeAddr, SectionLen; - unsigned int *SectionTableAddr; - - // Load base address of Global Section Table - SectionTableAddr = &__data_section_table; - - // Copy the data sections from flash to SRAM. - while (SectionTableAddr < &__data_section_table_end) { - LoadAddr = *SectionTableAddr++; - ExeAddr = *SectionTableAddr++; - SectionLen = *SectionTableAddr++; - data_init(LoadAddr, ExeAddr, SectionLen); - } - - // At this point, SectionTableAddr = &__bss_section_table; - // Zero fill the bss segment - while (SectionTableAddr < &__bss_section_table_end) { - ExeAddr = *SectionTableAddr++; - SectionLen = *SectionTableAddr++; - bss_init(ExeAddr, SectionLen); - } - -#if !defined (__USE_CMSIS) -// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code -// will enable the FPU -#if defined (__VFP_FP__) && !defined (__SOFTFP__) - // - // Code to enable the Cortex-M4 FPU only included - // if appropriate build options have been selected. - // Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C) - // - // Read CPACR (located at address 0xE000ED88) - // Set bits 20-23 to enable CP10 and CP11 coprocessors - // Write back the modified value to the CPACR - asm volatile ("LDR.W R0, =0xE000ED88\n\t" - "LDR R1, [R0]\n\t" - "ORR R1, R1, #(0xF << 20)\n\t" - "STR R1, [R0]"); -#endif // (__VFP_FP__) && !(__SOFTFP__) -#endif // (__USE_CMSIS) - -#if !defined (__USE_CMSIS) -// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code -// will setup the VTOR register - - // Check to see if we are running the code from a non-zero - // address (eg RAM, external flash), in which case we need - // to modify the VTOR register to tell the CPU that the - // vector table is located at a non-0x0 address. - unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; - if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) { - *pSCB_VTOR = (unsigned int)g_pfnVectors; - } -#endif // (__USE_CMSIS) - -#if defined (__cplusplus) - // - // Call C++ library initialisation - // - __libc_init_array(); -#endif - - // Reenable interrupts - __asm volatile ("cpsie i"); - -#if defined (__REDLIB__) - // Call the Redlib library, which in turn calls main() - __main(); -#else - main(); -#endif - - // - // main() shouldn't return, but if it does, we'll just enter an infinite loop - // - while (1) { - ; - } -} - -//***************************************************************************** -// Default core exception handlers. Override the ones here by defining your own -// handler routines in your application code. -//***************************************************************************** -WEAK_AV void NMI_Handler(void) -{ while(1) {} -} - -WEAK_AV void HardFault_Handler(void) -{ while(1) {} -} - -WEAK_AV void MemManage_Handler(void) -{ while(1) {} -} - -WEAK_AV void BusFault_Handler(void) -{ while(1) {} -} - -WEAK_AV void UsageFault_Handler(void) -{ while(1) {} -} - -WEAK_AV void SVC_Handler(void) -{ while(1) {} -} - -WEAK_AV void DebugMon_Handler(void) -{ while(1) {} -} - -WEAK_AV void PendSV_Handler(void) -{ while(1) {} -} - -WEAK_AV void SysTick_Handler(void) -{ while(1) {} -} - -//***************************************************************************** -// Processor ends up here if an unexpected interrupt occurs or a specific -// handler is not present in the application code. -//***************************************************************************** -WEAK_AV void IntDefaultHandler(void) -{ while(1) {} -} - -//***************************************************************************** -// Default application exception handlers. Override the ones here by defining -// your own handler routines in your application code. These routines call -// driver exception handlers or IntDefaultHandler() if no driver exception -// handler is included. -//***************************************************************************** -WEAK void WDT_BOD_IRQHandler(void) -{ WDT_BOD_DriverIRQHandler(); -} - -WEAK void DMA0_IRQHandler(void) -{ DMA0_DriverIRQHandler(); -} - -WEAK void GINT0_IRQHandler(void) -{ GINT0_DriverIRQHandler(); -} - -WEAK void GINT1_IRQHandler(void) -{ GINT1_DriverIRQHandler(); -} - -WEAK void PIN_INT0_IRQHandler(void) -{ PIN_INT0_DriverIRQHandler(); -} - -WEAK void PIN_INT1_IRQHandler(void) -{ PIN_INT1_DriverIRQHandler(); -} - -WEAK void PIN_INT2_IRQHandler(void) -{ PIN_INT2_DriverIRQHandler(); -} - -WEAK void PIN_INT3_IRQHandler(void) -{ PIN_INT3_DriverIRQHandler(); -} - -WEAK void UTICK0_IRQHandler(void) -{ UTICK0_DriverIRQHandler(); -} - -WEAK void MRT0_IRQHandler(void) -{ MRT0_DriverIRQHandler(); -} - -WEAK void CTIMER0_IRQHandler(void) -{ CTIMER0_DriverIRQHandler(); -} - -WEAK void CTIMER1_IRQHandler(void) -{ CTIMER1_DriverIRQHandler(); -} - -WEAK void SCT0_IRQHandler(void) -{ SCT0_DriverIRQHandler(); -} - -WEAK void CTIMER3_IRQHandler(void) -{ CTIMER3_DriverIRQHandler(); -} - -WEAK void FLEXCOMM0_IRQHandler(void) -{ FLEXCOMM0_DriverIRQHandler(); -} - -WEAK void FLEXCOMM1_IRQHandler(void) -{ FLEXCOMM1_DriverIRQHandler(); -} - -WEAK void FLEXCOMM2_IRQHandler(void) -{ FLEXCOMM2_DriverIRQHandler(); -} - -WEAK void FLEXCOMM3_IRQHandler(void) -{ FLEXCOMM3_DriverIRQHandler(); -} - -WEAK void FLEXCOMM4_IRQHandler(void) -{ FLEXCOMM4_DriverIRQHandler(); -} - -WEAK void FLEXCOMM5_IRQHandler(void) -{ FLEXCOMM5_DriverIRQHandler(); -} - -WEAK void FLEXCOMM6_IRQHandler(void) -{ FLEXCOMM6_DriverIRQHandler(); -} - -WEAK void FLEXCOMM7_IRQHandler(void) -{ FLEXCOMM7_DriverIRQHandler(); -} - -WEAK void ADC0_SEQA_IRQHandler(void) -{ ADC0_SEQA_DriverIRQHandler(); -} - -WEAK void ADC0_SEQB_IRQHandler(void) -{ ADC0_SEQB_DriverIRQHandler(); -} - -WEAK void ADC0_THCMP_IRQHandler(void) -{ ADC0_THCMP_DriverIRQHandler(); -} - -WEAK void DMIC0_IRQHandler(void) -{ DMIC0_DriverIRQHandler(); -} - -WEAK void HWVAD0_IRQHandler(void) -{ HWVAD0_DriverIRQHandler(); -} - -WEAK void USB0_NEEDCLK_IRQHandler(void) -{ USB0_NEEDCLK_DriverIRQHandler(); -} - -WEAK void USB0_IRQHandler(void) -{ USB0_DriverIRQHandler(); -} - -WEAK void RTC_IRQHandler(void) -{ RTC_DriverIRQHandler(); -} - -WEAK void Reserved46_IRQHandler(void) -{ Reserved46_DriverIRQHandler(); -} - -WEAK void Reserved47_IRQHandler(void) -{ Reserved47_DriverIRQHandler(); -} - -WEAK void PIN_INT4_IRQHandler(void) -{ PIN_INT4_DriverIRQHandler(); -} - -WEAK void PIN_INT5_IRQHandler(void) -{ PIN_INT5_DriverIRQHandler(); -} - -WEAK void PIN_INT6_IRQHandler(void) -{ PIN_INT6_DriverIRQHandler(); -} - -WEAK void PIN_INT7_IRQHandler(void) -{ PIN_INT7_DriverIRQHandler(); -} - -WEAK void CTIMER2_IRQHandler(void) -{ CTIMER2_DriverIRQHandler(); -} - -WEAK void CTIMER4_IRQHandler(void) -{ CTIMER4_DriverIRQHandler(); -} - -WEAK void RIT_IRQHandler(void) -{ RIT_DriverIRQHandler(); -} - -WEAK void SPIFI0_IRQHandler(void) -{ SPIFI0_DriverIRQHandler(); -} - -WEAK void FLEXCOMM8_IRQHandler(void) -{ FLEXCOMM8_DriverIRQHandler(); -} - -WEAK void FLEXCOMM9_IRQHandler(void) -{ FLEXCOMM9_DriverIRQHandler(); -} - -WEAK void SDIO_IRQHandler(void) -{ SDIO_DriverIRQHandler(); -} - -WEAK void CAN0_IRQ0_IRQHandler(void) -{ CAN0_IRQ0_DriverIRQHandler(); -} - -WEAK void CAN0_IRQ1_IRQHandler(void) -{ CAN0_IRQ1_DriverIRQHandler(); -} - -WEAK void CAN1_IRQ0_IRQHandler(void) -{ CAN1_IRQ0_DriverIRQHandler(); -} - -WEAK void CAN1_IRQ1_IRQHandler(void) -{ CAN1_IRQ1_DriverIRQHandler(); -} - -WEAK void USB1_IRQHandler(void) -{ USB1_DriverIRQHandler(); -} - -WEAK void USB1_NEEDCLK_IRQHandler(void) -{ USB1_NEEDCLK_DriverIRQHandler(); -} - -WEAK void ETHERNET_IRQHandler(void) -{ ETHERNET_DriverIRQHandler(); -} - -WEAK void ETHERNET_PMT_IRQHandler(void) -{ ETHERNET_PMT_DriverIRQHandler(); -} - -WEAK void ETHERNET_MACLP_IRQHandler(void) -{ ETHERNET_MACLP_DriverIRQHandler(); -} - -WEAK void EEPROM_IRQHandler(void) -{ EEPROM_DriverIRQHandler(); -} - -WEAK void LCD_IRQHandler(void) -{ LCD_DriverIRQHandler(); -} - -WEAK void SHA_IRQHandler(void) -{ SHA_DriverIRQHandler(); -} - -WEAK void SMARTCARD0_IRQHandler(void) -{ SMARTCARD0_DriverIRQHandler(); -} - -WEAK void SMARTCARD1_IRQHandler(void) -{ SMARTCARD1_DriverIRQHandler(); -} - -//***************************************************************************** - -#if defined (DEBUG) -#pragma GCC pop_options -#endif // (DEBUG) diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/system_LPC54608.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/system_LPC54608.c deleted file mode 100644 index b16179714ae..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/system_LPC54608.c +++ /dev/null @@ -1,361 +0,0 @@ -/* -** ################################################################### -** Processors: LPC54608J512BD208 -** LPC54608J512ET180 -** -** Compilers: Keil ARM C/C++ Compiler -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: LPC54S60x/LPC5460x User manual Rev.0.9 7 Nov 2016 -** Version: rev. 1.1, 2016-11-25 -** Build: b170214 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2016-08-12) -** Initial version. -** - rev. 1.1 (2016-11-25) -** Update CANFD and Classic CAN register. -** Add MAC TIMERSTAMP registers. -** -** ################################################################### -*/ - -/*! - * @file LPC54608 - * @version 1.1 - * @date 2016-11-25 - * @brief Device specific configuration file for LPC54608 (implementation file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include -#include "fsl_device_registers.h" - -#define NVALMAX (0x100) -#define PVALMAX (0x20) -#define MVALMAX (0x8000) -#define PLL_MDEC_VAL_P (0) /* MDEC is in bits 16:0 */ -#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P) -#define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0 */ -#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P) -#define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0 */ -#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P) - -extern void *__Vectors; - -static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46, - 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61}; -/* Get WATCH DOG Clk */ -static uint32_t getWdtOscFreq(void) -{ - uint8_t freq_sel, div_sel; - if (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) - { - return 0U; - } - else - { - div_sel = ((SYSCON->WDTOSCCTRL & 0x1f) + 1) << 1; - freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)]; - return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel); - } -} -/* Find decoded N value for raw NDEC value */ -static uint32_t pllDecodeN(uint32_t NDEC) -{ - uint32_t n, x, i; - - /* Find NDec */ - switch (NDEC) - { - case 0x3FF: - n = 0; - break; - case 0x302: - n = 1; - break; - case 0x202: - n = 2; - break; - default: - x = 0x080; - n = 0xFFFFFFFFU; - for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFFU)); i--) - { - x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F); - if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC) - { - /* Decoded value of NDEC */ - n = i; - } - } - break; - } - return n; -} - -/* Find decoded P value for raw PDEC value */ -static uint32_t pllDecodeP(uint32_t PDEC) -{ - uint32_t p, x, i; - /* Find PDec */ - switch (PDEC) - { - case 0x7F: - p = 0; - break; - case 0x62: - p = 1; - break; - case 0x42: - p = 2; - break; - default: - x = 0x10; - p = 0xFFFFFFFFU; - for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFFU)); i--) - { - x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xFU); - if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC) - { - /* Decoded value of PDEC */ - p = i; - } - } - break; - } - return p; -} - -/* Find decoded M value for raw MDEC value */ -static uint32_t pllDecodeM(uint32_t MDEC) -{ - uint32_t m, i, x; - - /* Find MDec */ - switch (MDEC) - { - case 0x1FFFF: - m = 0; - break; - case 0x18003: - m = 1; - break; - case 0x10003: - m = 2; - break; - default: - x = 0x04000; - m = 0xFFFFFFFFU; - for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFFU)); i--) - { - x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFFU); - if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC) - { - /* Decoded value of MDEC */ - m = i; - } - } - break; - } - return m; -} - -/* Get predivider (N) from PLL NDEC setting */ -static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg) -{ - uint32_t preDiv = 1; - - /* Direct input is not used? */ - if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0) - { - /* Decode NDEC value to get (N) pre divider */ - preDiv = pllDecodeN(nDecReg & 0x3FF); - if (preDiv == 0) - { - preDiv = 1; - } - } - /* Adjusted by 1, directi is used to bypass */ - return preDiv; -} - -/* Get postdivider (P) from PLL PDEC setting */ -static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg) -{ - uint32_t postDiv = 1; - - /* Direct input is not used? */ - if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0) - { - /* Decode PDEC value to get (P) post divider */ - postDiv = 2 * pllDecodeP(pDecReg & 0x7F); - if (postDiv == 0) - { - postDiv = 2; - } - } - /* Adjusted by 1, directo is used to bypass */ - return postDiv; -} - -/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ -static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg) -{ - uint32_t mMult = 1; - - /* Decode MDEC value to get (M) multiplier */ - mMult = pllDecodeM(mDecReg & 0x1FFFF); - if (mMult == 0) - { - mMult = 1; - } - return mMult; -} - - - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ - -void SystemInit (void) { -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ - -#if defined(__MCUXPRESSO) - extern void(*const g_pfnVectors[]) (void); - SCB->VTOR = (uint32_t) &g_pfnVectors; -#else - extern void *__Vectors; - SCB->VTOR = (uint32_t) &__Vectors; -#endif - SYSCON->ARMTRACECLKDIV = 0; -/* Optionally enable RAM banks that may be off by default at reset */ -#if !defined(DONT_ENABLE_DISABLED_RAMBANKS) - SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK; -#endif -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate (void) { -uint32_t clkRate = 0; - uint32_t prediv, postdiv; - uint64_t workRate; - - switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) - { - case 0x00: /* MAINCLKSELA clock (main_clk_a)*/ - switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = CLK_FRO_12MHZ; - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = CLK_CLK_IN; - break; - case 0x02: /* Watchdog oscillator (wdt_clk) */ - clkRate = getWdtOscFreq(); - break; - default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */ - if (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) - { - clkRate = CLK_FRO_96MHZ; - } - else - { - clkRate = CLK_FRO_48MHZ; - } - break; - } - break; - case 0x02: /* System PLL clock (pll_clk)*/ - switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = CLK_FRO_12MHZ; - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = CLK_CLK_IN; - break; - case 0x02: /* Watchdog oscillator (wdt_clk) */ - clkRate = getWdtOscFreq(); - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = CLK_RTC_32K_CLK; - break; - default: - break; - } - if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0) - { - /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ - prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC); - postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC); - /* Adjust input clock */ - clkRate = clkRate / prediv; - - /* MDEC used for rate */ - workRate = (uint64_t)clkRate * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC); - clkRate = workRate / ((uint64_t)postdiv); - clkRate = workRate * 2; /* PLL CCO output is divided by 2 before to M-Divider */ - } - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = CLK_RTC_32K_CLK; - break; - default: - break; - } - SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1); -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/system_LPC54608.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/system_LPC54608.h deleted file mode 100644 index 79194524e49..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/system_LPC54608.h +++ /dev/null @@ -1,121 +0,0 @@ -/* -** ################################################################### -** Processors: LPC54608J512BD208 -** LPC54608J512ET180 -** -** Compilers: Keil ARM C/C++ Compiler -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: LPC54S60x/LPC5460x User manual Rev.0.9 7 Nov 2016 -** Version: rev. 1.1, 2016-11-25 -** Build: b161227 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2016-08-12) -** Initial version. -** - rev. 1.1 (2016-11-25) -** Update CANFD and Classic CAN register. -** Add MAC TIMERSTAMP registers. -** -** ################################################################### -*/ - -/*! - * @file LPC54608 - * @version 1.1 - * @date 2016-11-25 - * @brief Device specific configuration file for LPC54608 (header file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef _SYSTEM_LPC54608_H_ -#define _SYSTEM_LPC54608_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ -#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ -#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ -#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ -#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ -#define CLK_CLK_IN 0u /* Default CLK_IN pin clock */ - - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_LPC54608_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/utilities/SConscript b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/utilities/SConscript deleted file mode 100644 index 6897da05ef0..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/utilities/SConscript +++ /dev/null @@ -1,13 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -CPPPATH = [cwd] -src = [] - -CPPDEFINES = ['SDK_DEBUGCONSOLE=0'] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) - -Return('group') diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/utilities/fsl_debug_console.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/utilities/fsl_debug_console.c deleted file mode 100644 index bd0b2412de9..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/utilities/fsl_debug_console.c +++ /dev/null @@ -1,1959 +0,0 @@ -/* - * This is a modified version of the file printf.c, which was distributed - * by Motorola as part of the M5407C3BOOT.zip package used to initialize - * the M5407C3 evaluation board. - * - * Copyright: - * 1999-2000 MOTOROLA, INC. All Rights Reserved. - * You are hereby granted a copyright license to use, modify, and - * distribute the SOFTWARE so long as this entire notice is - * retained without alteration in any modified and/or redistributed - * versions, and that such modified versions are clearly identified - * as such. No licenses are granted by implication, estoppel or - * otherwise under any patents or trademarks of Motorola, Inc. This - * software is provided on an "AS IS" basis and without warranty. - * - * To the maximum extent permitted by applicable law, MOTOROLA - * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING - * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR - * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE - * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY - * ACCOMPANYING WRITTEN MATERIALS. - * - * To the maximum extent permitted by applicable law, IN NO EVENT - * SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING - * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS - * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY - * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. - * - * Motorola assumes no responsibility for the maintenance and support - * of this software - - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#if defined(__CC_ARM) -#include -#endif -#include -#include "fsl_debug_console.h" - -#if (defined(FSL_FEATURE_SOC_UART_COUNT) && (FSL_FEATURE_SOC_UART_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_IUART_COUNT) && (FSL_FEATURE_SOC_IUART_COUNT > 0)) -#include "fsl_uart.h" -#endif /* FSL_FEATURE_SOC_UART_COUNT || FSL_FEATURE_SOC_IUART_COUNT */ - -#if defined(FSL_FEATURE_SOC_LPSCI_COUNT) && (FSL_FEATURE_SOC_LPSCI_COUNT > 0) -#include "fsl_lpsci.h" -#endif /* FSL_FEATURE_SOC_LPSCI_COUNT */ - -#if defined(FSL_FEATURE_SOC_LPUART_COUNT) && (FSL_FEATURE_SOC_LPUART_COUNT > 0) -#include "fsl_lpuart.h" -#endif /* FSL_FEATURE_SOC_LPUART_COUNT */ - -#if defined(FSL_FEATURE_SOC_USB_COUNT) && (FSL_FEATURE_SOC_USB_COUNT > 0) && defined(BOARD_USE_VIRTUALCOM) -#include "usb_device_config.h" -#include "usb.h" -#include "usb_device_cdc_acm.h" -#include "usb_device_ch9.h" -#include "virtual_com.h" -#endif - -#if defined(FSL_FEATURE_SOC_FLEXCOMM_COUNT) && (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 0) -#include "fsl_usart.h" -#endif /* FSL_FEATURE_SOC_FLEXCOMM_COUNT */ - -/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */ -#if defined(__CC_ARM) -#pragma diag_suppress 1256 -#endif /* __CC_ARM */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief This definition is maximum line that debugconsole can scanf each time.*/ -#define IO_MAXLINE 20U - -/*! @brief The overflow value.*/ -#ifndef HUGE_VAL -#define HUGE_VAL (99.e99) -#endif /* HUGE_VAL */ - -#if SCANF_FLOAT_ENABLE -static double fnum = 0.0; -#endif /* SCANF_FLOAT_ENABLE */ - -/*! @brief Operation functions definitions for debug console. */ -typedef struct DebugConsoleOperationFunctions -{ - union - { - void (*PutChar)(void *base, const uint8_t *buffer, size_t length); -#if (defined(FSL_FEATURE_SOC_UART_COUNT) && (FSL_FEATURE_SOC_UART_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_IUART_COUNT) && (FSL_FEATURE_SOC_IUART_COUNT > 0)) - void (*UART_PutChar)(UART_Type *base, const uint8_t *buffer, size_t length); -#endif /* FSL_FEATURE_SOC_UART_COUNT || FSL_FEATURE_SOC_IUART_COUNT */ -#if defined(FSL_FEATURE_SOC_LPSCI_COUNT) && (FSL_FEATURE_SOC_LPSCI_COUNT > 0) - void (*LPSCI_PutChar)(UART0_Type *base, const uint8_t *buffer, size_t length); -#endif /* FSL_FEATURE_SOC_LPSCI_COUNT */ -#if defined(FSL_FEATURE_SOC_LPUART_COUNT) && (FSL_FEATURE_SOC_LPUART_COUNT > 0) - void (*LPUART_PutChar)(LPUART_Type *base, const uint8_t *buffer, size_t length); -#endif /* FSL_FEATURE_SOC_LPUART_COUNT */ -#if defined(FSL_FEATURE_SOC_USB_COUNT) && (FSL_FEATURE_SOC_USB_COUNT > 0) && defined(BOARD_USE_VIRTUALCOM) - void (*USB_PutChar)(usb_device_handle base, const uint8_t *buf, size_t count); -#endif /* FSL_FEATURE_SOC_USB_COUNT && BOARD_USE_VIRTUALCOM*/ -#if defined(FSL_FEATURE_SOC_FLEXCOMM_COUNT) && (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 0) - void (*USART_PutChar)(USART_Type *base, const uint8_t *data, size_t length); -#endif /* FSL_FEATURE_SOC_FLEXCOMM_COUNT */ - } tx_union; - union - { - status_t (*GetChar)(void *base, const uint8_t *buffer, size_t length); -#if (defined(FSL_FEATURE_SOC_UART_COUNT) && (FSL_FEATURE_SOC_UART_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_IUART_COUNT) && (FSL_FEATURE_SOC_IUART_COUNT > 0)) - status_t (*UART_GetChar)(UART_Type *base, uint8_t *buffer, size_t length); -#endif /* FSL_FEATURE_SOC_UART_COUNT || FSL_FEATURE_SOC_IUART_COUNT*/ -#if defined(FSL_FEATURE_SOC_LPSCI_COUNT) && (FSL_FEATURE_SOC_LPSCI_COUNT > 0) - status_t (*LPSCI_GetChar)(UART0_Type *base, uint8_t *buffer, size_t length); -#endif /* FSL_FEATURE_SOC_LPSCI_COUNT */ -#if defined(FSL_FEATURE_SOC_LPUART_COUNT) && (FSL_FEATURE_SOC_LPUART_COUNT > 0) - status_t (*LPUART_GetChar)(LPUART_Type *base, uint8_t *buffer, size_t length); -#endif /* FSL_FEATURE_SOC_LPUART_COUNT */ -#if defined(FSL_FEATURE_SOC_USB_COUNT) && (FSL_FEATURE_SOC_USB_COUNT > 0) && defined(BOARD_USE_VIRTUALCOM) - status_t (*USB_GetChar)(usb_device_handle base, uint8_t *buf, size_t count); -#endif /* FSL_FEATURE_SOC_USB_COUNT && BOARD_USE_VIRTUALCOM*/ -#if defined(FSL_FEATURE_SOC_FLEXCOMM_COUNT) && (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 0) - status_t (*USART_GetChar)(USART_Type *base, uint8_t *data, size_t length); -#endif - } rx_union; -} debug_console_ops_t; - -/*! @brief State structure storing debug console. */ -typedef struct DebugConsoleState -{ - uint8_t type; /*!< Indicator telling whether the debug console is initialized. */ - void *base; /*!< Base of the IP register. */ - debug_console_ops_t ops; /*!< Operation function pointers for debug UART operations. */ -} debug_console_state_t; - -/*! @brief Type of KSDK printf function pointer. */ -typedef int (*PUTCHAR_FUNC)(int a); - -#if PRINTF_ADVANCED_ENABLE -/*! @brief Specification modifier flags for printf. */ -enum _debugconsole_printf_flag -{ - kPRINTF_Minus = 0x01U, /*!< Minus FLag. */ - kPRINTF_Plus = 0x02U, /*!< Plus Flag. */ - kPRINTF_Space = 0x04U, /*!< Space Flag. */ - kPRINTF_Zero = 0x08U, /*!< Zero Flag. */ - kPRINTF_Pound = 0x10U, /*!< Pound Flag. */ - kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */ - kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */ - kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */ - kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */ -}; -#endif /* PRINTF_ADVANCED_ENABLE */ - -/*! @brief Specification modifier flags for scanf. */ -enum _debugconsole_scanf_flag -{ - kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */ - kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */ - kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */ - kSCANF_DestString = 0x8U, /*!< Destination String FLag. */ - kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */ - kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */ - kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */ - kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */ -#if SCANF_ADVANCED_ENABLE - kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */ - kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */ - kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */ - kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */ -#endif /* SCANF_ADVANCED_ENABLE */ -#if PRINTF_FLOAT_ENABLE - kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */ -#endif /*PRINTF_FLOAT_ENABLE */ - kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */ -}; - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Debug UART state information. */ -static debug_console_state_t s_debugConsole = {.type = DEBUG_CONSOLE_DEVICE_TYPE_NONE, .base = NULL, .ops = {{0}, {0}}}; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -#if SDK_DEBUGCONSOLE -static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt, va_list ap); -static int DbgConsole_ScanfFormattedData(const char *line_ptr, char *format, va_list args_ptr); -double modf(double input_dbl, double *intpart_ptr); -#endif /* SDK_DEBUGCONSOLE */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/ - -/* See fsl_debug_console.h for documentation of this function. */ -status_t DbgConsole_Init(uint32_t baseAddr, uint32_t baudRate, uint8_t device, uint32_t clkSrcFreq) -{ - if (s_debugConsole.type != DEBUG_CONSOLE_DEVICE_TYPE_NONE) - { - return kStatus_Fail; - } - - /* Set debug console to initialized to avoid duplicated initialized operation. */ - s_debugConsole.type = device; - - /* Switch between different device. */ - switch (device) - { -#if (defined(FSL_FEATURE_SOC_UART_COUNT) && (FSL_FEATURE_SOC_UART_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_IUART_COUNT) && (FSL_FEATURE_SOC_IUART_COUNT > 0)) - case DEBUG_CONSOLE_DEVICE_TYPE_UART: - case DEBUG_CONSOLE_DEVICE_TYPE_IUART: - { - uart_config_t uart_config; - s_debugConsole.base = (UART_Type *)baseAddr; - UART_GetDefaultConfig(&uart_config); - uart_config.baudRate_Bps = baudRate; - /* Enable clock and initial UART module follow user configure structure. */ - UART_Init(s_debugConsole.base, &uart_config, clkSrcFreq); - UART_EnableTx(s_debugConsole.base, true); - UART_EnableRx(s_debugConsole.base, true); - /* Set the function pointer for send and receive for this kind of device. */ - s_debugConsole.ops.tx_union.UART_PutChar = UART_WriteBlocking; - s_debugConsole.ops.rx_union.UART_GetChar = UART_ReadBlocking; - } - break; -#endif /* FSL_FEATURE_SOC_UART_COUNT */ -#if defined(FSL_FEATURE_SOC_LPSCI_COUNT) && (FSL_FEATURE_SOC_LPSCI_COUNT > 0) - case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI: - { - lpsci_config_t lpsci_config; - s_debugConsole.base = (UART0_Type *)baseAddr; - LPSCI_GetDefaultConfig(&lpsci_config); - lpsci_config.baudRate_Bps = baudRate; - /* Enable clock and initial UART module follow user configure structure. */ - LPSCI_Init(s_debugConsole.base, &lpsci_config, clkSrcFreq); - LPSCI_EnableTx(s_debugConsole.base, true); - LPSCI_EnableRx(s_debugConsole.base, true); - /* Set the function pointer for send and receive for this kind of device. */ - s_debugConsole.ops.tx_union.LPSCI_PutChar = LPSCI_WriteBlocking; - s_debugConsole.ops.rx_union.LPSCI_GetChar = LPSCI_ReadBlocking; - } - break; -#endif /* FSL_FEATURE_SOC_LPSCI_COUNT */ -#if defined(FSL_FEATURE_SOC_LPUART_COUNT) && (FSL_FEATURE_SOC_LPUART_COUNT > 0) - case DEBUG_CONSOLE_DEVICE_TYPE_LPUART: - { - lpuart_config_t lpuart_config; - s_debugConsole.base = (LPUART_Type *)baseAddr; - LPUART_GetDefaultConfig(&lpuart_config); - lpuart_config.baudRate_Bps = baudRate; - /* Enable clock and initial UART module follow user configure structure. */ - LPUART_Init(s_debugConsole.base, &lpuart_config, clkSrcFreq); - LPUART_EnableTx(s_debugConsole.base, true); - LPUART_EnableRx(s_debugConsole.base, true); - /* Set the function pointer for send and receive for this kind of device. */ - s_debugConsole.ops.tx_union.LPUART_PutChar = LPUART_WriteBlocking; - s_debugConsole.ops.rx_union.LPUART_GetChar = LPUART_ReadBlocking; - } - break; -#endif /* FSL_FEATURE_SOC_LPUART_COUNT */ -#if defined(FSL_FEATURE_SOC_USB_COUNT) && (FSL_FEATURE_SOC_USB_COUNT > 0) && defined(BOARD_USE_VIRTUALCOM) - case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC: - { - s_debugConsole.base = USB_VcomInit(); - s_debugConsole.ops.tx_union.USB_PutChar = USB_VcomWriteBlocking; - s_debugConsole.ops.rx_union.USB_GetChar = USB_VcomReadBlocking; - } - break; -#endif /* FSL_FEATURE_SOC_USB_COUNT && BOARD_USE_VIRTUALCOM*/ -#if defined(FSL_FEATURE_SOC_FLEXCOMM_COUNT) && (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 0) - case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM: - { - usart_config_t usart_config; - s_debugConsole.base = (USART_Type *)baseAddr; - USART_GetDefaultConfig(&usart_config); - usart_config.baudRate_Bps = baudRate; - /* Enable clock and initial UART module follow user configure structure. */ - USART_Init(s_debugConsole.base, &usart_config, clkSrcFreq); - /* Set the function pointer for send and receive for this kind of device. */ - s_debugConsole.ops.tx_union.USART_PutChar = USART_WriteBlocking; - s_debugConsole.ops.rx_union.USART_GetChar = USART_ReadBlocking; - } - break; -#endif /* FSL_FEATURE_SOC_FLEXCOMM_COUNT*/ - /* If new device is required as the low level device for debug console, - * Add the case branch and add the preprocessor macro to judge whether - * this kind of device exist in this SOC. */ - default: - /* Device identified is invalid, return invalid device error code. */ - return kStatus_InvalidArgument; - } - - return kStatus_Success; -} - -/* See fsl_debug_console.h for documentation of this function. */ -status_t DbgConsole_Deinit(void) -{ - if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE) - { - return kStatus_Success; - } - - switch (s_debugConsole.type) - { -#if (defined(FSL_FEATURE_SOC_UART_COUNT) && (FSL_FEATURE_SOC_UART_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_IUART_COUNT) && (FSL_FEATURE_SOC_IUART_COUNT > 0)) - case DEBUG_CONSOLE_DEVICE_TYPE_UART: - case DEBUG_CONSOLE_DEVICE_TYPE_IUART: - /* Disable UART module. */ - UART_Deinit(s_debugConsole.base); - break; -#endif /* FSL_FEATURE_SOC_UART_COUNT */ -#if defined(FSL_FEATURE_SOC_LPSCI_COUNT) && (FSL_FEATURE_SOC_LPSCI_COUNT > 0) - case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI: - /* Disable LPSCI module. */ - LPSCI_Deinit(s_debugConsole.base); - break; -#endif /* FSL_FEATURE_SOC_LPSCI_COUNT */ -#if defined(FSL_FEATURE_SOC_LPUART_COUNT) && (FSL_FEATURE_SOC_LPUART_COUNT > 0) - case DEBUG_CONSOLE_DEVICE_TYPE_LPUART: - /* Disable LPUART module. */ - LPUART_Deinit(s_debugConsole.base); - break; -#endif /* FSL_FEATURE_SOC_LPUART_COUNT */ -#if defined(FSL_FEATURE_SOC_USB_COUNT) && (FSL_FEATURE_SOC_USB_COUNT > 0) && defined(BOARD_USE_VIRTUALCOM) - case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC: - /* Disable USBCDC module. */ - USB_VcomDeinit(s_debugConsole.base); - break; -#endif /* FSL_FEATURE_SOC_USB_COUNT && BOARD_USE_VIRTUALCOM*/ -#if defined(FSL_FEATURE_SOC_FLEXCOMM_COUNT) && (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 0) - case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM: - { - USART_Deinit((USART_Type *)s_debugConsole.base); - } - break; -#endif /* FSL_FEATURE_SOC_FLEXCOMM_COUNT*/ - default: - s_debugConsole.type = DEBUG_CONSOLE_DEVICE_TYPE_NONE; - break; - } - - /* Device identified is invalid, return invalid device error code. */ - if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE) - { - return kStatus_InvalidArgument; - } - - s_debugConsole.type = DEBUG_CONSOLE_DEVICE_TYPE_NONE; - return kStatus_Success; -} - -#if SDK_DEBUGCONSOLE -/* See fsl_debug_console.h for documentation of this function. */ -int DbgConsole_Printf(const char *fmt_s, ...) -{ - va_list ap; - int result; - - /* Do nothing if the debug UART is not initialized. */ - if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE) - { - return -1; - } - va_start(ap, fmt_s); - result = DbgConsole_PrintfFormattedData(DbgConsole_Putchar, fmt_s, ap); - va_end(ap); - - return result; -} - -/* See fsl_debug_console.h for documentation of this function. */ -int DbgConsole_Putchar(int ch) -{ - /* Do nothing if the debug UART is not initialized. */ - if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE) - { - return -1; - } - s_debugConsole.ops.tx_union.PutChar(s_debugConsole.base, (uint8_t *)(&ch), 1); - - return 1; -} - -/* See fsl_debug_console.h for documentation of this function. */ -int DbgConsole_Scanf(char *fmt_ptr, ...) -{ - /* Plus one to store end of string char */ - char temp_buf[IO_MAXLINE + 1]; - va_list ap; - int32_t i; - char result; - - /* Do nothing if the debug UART is not initialized. */ - if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE) - { - return -1; - } - va_start(ap, fmt_ptr); - temp_buf[0] = '\0'; - - for (i = 0; i < IO_MAXLINE; i++) - { - temp_buf[i] = result = DbgConsole_Getchar(); - - if ((result == '\r') || (result == '\n')) - { - /* End of Line. */ - if (i == 0) - { - temp_buf[i] = '\0'; - i = -1; - } - else - { - break; - } - } - } - - if ((i == IO_MAXLINE)) - { - temp_buf[i] = '\0'; - } - else - { - temp_buf[i + 1] = '\0'; - } - result = DbgConsole_ScanfFormattedData(temp_buf, fmt_ptr, ap); - va_end(ap); - - return result; -} - -/* See fsl_debug_console.h for documentation of this function. */ -int DbgConsole_Getchar(void) -{ - char ch; - /* Do nothing if the debug UART is not initialized. */ - if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE) - { - return -1; - } - while (kStatus_Success != s_debugConsole.ops.rx_union.GetChar(s_debugConsole.base, (uint8_t *)(&ch), 1)) - { - return -1; - } - - return ch; -} - -/*************Code for process formatted data*******************************/ -/*! - * @brief Scanline function which ignores white spaces. - * - * @param[in] s The address of the string pointer to update. - * @return String without white spaces. - */ -static uint32_t DbgConsole_ScanIgnoreWhiteSpace(const char **s) -{ - uint8_t count = 0; - uint8_t c; - - c = **s; - while ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f')) - { - count++; - (*s)++; - c = **s; - } - return count; -} - -/*! - * @brief This function puts padding character. - * - * @param[in] c Padding character. - * @param[in] curlen Length of current formatted string . - * @param[in] width Width of expected formatted string. - * @param[in] count Number of characters. - * @param[in] func_ptr Function to put character out. - */ -static void DbgConsole_PrintfPaddingCharacter( - char c, int32_t curlen, int32_t width, int32_t *count, PUTCHAR_FUNC func_ptr) -{ - int32_t i; - - for (i = curlen; i < width; i++) - { - func_ptr(c); - (*count)++; - } -} - -/*! - * @brief Converts a radix number to a string and return its length. - * - * @param[in] numstr Converted string of the number. - * @param[in] nump Pointer to the number. - * @param[in] neg Polarity of the number. - * @param[in] radix The radix to be converted to. - * @param[in] use_caps Used to identify %x/X output format. - - * @return Length of the converted string. - */ -static int32_t DbgConsole_ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps) -{ -#if PRINTF_ADVANCED_ENABLE - int64_t a; - int64_t b; - int64_t c; - - uint64_t ua; - uint64_t ub; - uint64_t uc; -#else - int32_t a; - int32_t b; - int32_t c; - - uint32_t ua; - uint32_t ub; - uint32_t uc; -#endif /* PRINTF_ADVANCED_ENABLE */ - - int32_t nlen; - char *nstrp; - - nlen = 0; - nstrp = numstr; - *nstrp++ = '\0'; - - if (neg) - { -#if PRINTF_ADVANCED_ENABLE - a = *(int64_t *)nump; -#else - a = *(int32_t *)nump; -#endif /* PRINTF_ADVANCED_ENABLE */ - if (a == 0) - { - *nstrp = '0'; - ++nlen; - return nlen; - } - while (a != 0) - { -#if PRINTF_ADVANCED_ENABLE - b = (int64_t)a / (int64_t)radix; - c = (int64_t)a - ((int64_t)b * (int64_t)radix); - if (c < 0) - { - uc = (uint64_t)c; - c = (int64_t)(~uc) + 1 + '0'; - } -#else - b = a / radix; - c = a - (b * radix); - if (c < 0) - { - uc = (uint32_t)c; - c = (uint32_t)(~uc) + 1 + '0'; - } -#endif /* PRINTF_ADVANCED_ENABLE */ - else - { - c = c + '0'; - } - a = b; - *nstrp++ = (char)c; - ++nlen; - } - } - else - { -#if PRINTF_ADVANCED_ENABLE - ua = *(uint64_t *)nump; -#else - ua = *(uint32_t *)nump; -#endif /* PRINTF_ADVANCED_ENABLE */ - if (ua == 0) - { - *nstrp = '0'; - ++nlen; - return nlen; - } - while (ua != 0) - { -#if PRINTF_ADVANCED_ENABLE - ub = (uint64_t)ua / (uint64_t)radix; - uc = (uint64_t)ua - ((uint64_t)ub * (uint64_t)radix); -#else - ub = ua / (uint32_t)radix; - uc = ua - (ub * (uint32_t)radix); -#endif /* PRINTF_ADVANCED_ENABLE */ - - if (uc < 10) - { - uc = uc + '0'; - } - else - { - uc = uc - 10 + (use_caps ? 'A' : 'a'); - } - ua = ub; - *nstrp++ = (char)uc; - ++nlen; - } - } - return nlen; -} - -#if PRINTF_FLOAT_ENABLE -/*! - * @brief Converts a floating radix number to a string and return its length. - * - * @param[in] numstr Converted string of the number. - * @param[in] nump Pointer to the number. - * @param[in] radix The radix to be converted to. - * @param[in] precision_width Specify the precision width. - - * @return Length of the converted string. - */ -static int32_t DbgConsole_ConvertFloatRadixNumToString(char *numstr, - void *nump, - int32_t radix, - uint32_t precision_width) -{ - int32_t a; - int32_t b; - int32_t c; - int32_t i; - uint32_t uc; - double fa; - double dc; - double fb; - double r; - double fractpart; - double intpart; - - int32_t nlen; - char *nstrp; - nlen = 0; - nstrp = numstr; - *nstrp++ = '\0'; - r = *(double *)nump; - if (!r) - { - *nstrp = '0'; - ++nlen; - return nlen; - } - fractpart = modf((double)r, (double *)&intpart); - /* Process fractional part. */ - for (i = 0; i < precision_width; i++) - { - fractpart *= radix; - } - if (r >= 0) - { - fa = fractpart + (double)0.5; - if (fa >= pow(10, precision_width)) - { - intpart++; - } - } - else - { - fa = fractpart - (double)0.5; - if (fa <= -pow(10, precision_width)) - { - intpart--; - } - } - for (i = 0; i < precision_width; i++) - { - fb = fa / (int32_t)radix; - dc = (fa - (int64_t)fb * (int32_t)radix); - c = (int32_t)dc; - if (c < 0) - { - uc = (uint32_t)c; - c = (int32_t)(~uc) + 1 + '0'; - } - else - { - c = c + '0'; - } - fa = fb; - *nstrp++ = (char)c; - ++nlen; - } - *nstrp++ = (char)'.'; - ++nlen; - a = (int32_t)intpart; - if (a == 0) - { - *nstrp++ = '0'; - ++nlen; - } - else - { - while (a != 0) - { - b = (int32_t)a / (int32_t)radix; - c = (int32_t)a - ((int32_t)b * (int32_t)radix); - if (c < 0) - { - uc = (uint32_t)c; - c = (int32_t)(~uc) + 1 + '0'; - } - else - { - c = c + '0'; - } - a = b; - *nstrp++ = (char)c; - ++nlen; - } - } - return nlen; -} -#endif /* PRINTF_FLOAT_ENABLE */ - -/*! - * @brief This function outputs its parameters according to a formatted string. - * - * @note I/O is performed by calling given function pointer using following - * (*func_ptr)(c); - * - * @param[in] func_ptr Function to put character out. - * @param[in] fmt_ptr Format string for printf. - * @param[in] args_ptr Arguments to printf. - * - * @return Number of characters - */ -static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt, va_list ap) -{ - /* va_list ap; */ - char *p; - int32_t c; - - char vstr[33]; - char *vstrp = NULL; - int32_t vlen = 0; - - int32_t done; - int32_t count = 0; - - uint32_t field_width; - uint32_t precision_width; - char *sval; - int32_t cval; - bool use_caps; - uint8_t radix = 0; - -#if PRINTF_ADVANCED_ENABLE - uint32_t flags_used; - int32_t schar, dschar; - int64_t ival; - uint64_t uval = 0; - bool valid_precision_width; -#else - int32_t ival; - uint32_t uval = 0; -#endif /* PRINTF_ADVANCED_ENABLE */ - -#if PRINTF_FLOAT_ENABLE - double fval; -#endif /* PRINTF_FLOAT_ENABLE */ - - /* Start parsing apart the format string and display appropriate formats and data. */ - for (p = (char *)fmt; (c = *p) != 0; p++) - { - /* - * All formats begin with a '%' marker. Special chars like - * '\n' or '\t' are normally converted to the appropriate - * character by the __compiler__. Thus, no need for this - * routine to account for the '\' character. - */ - if (c != '%') - { - func_ptr(c); - count++; - /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */ - continue; - } - - use_caps = true; - -#if PRINTF_ADVANCED_ENABLE - /* First check for specification modifier flags. */ - flags_used = 0; - done = false; - while (!done) - { - switch (*++p) - { - case '-': - flags_used |= kPRINTF_Minus; - break; - case '+': - flags_used |= kPRINTF_Plus; - break; - case ' ': - flags_used |= kPRINTF_Space; - break; - case '0': - flags_used |= kPRINTF_Zero; - break; - case '#': - flags_used |= kPRINTF_Pound; - break; - default: - /* We've gone one char too far. */ - --p; - done = true; - break; - } - } -#endif /* PRINTF_ADVANCED_ENABLE */ - - /* Next check for minimum field width. */ - field_width = 0; - done = false; - while (!done) - { - c = *++p; - if ((c >= '0') && (c <= '9')) - { - field_width = (field_width * 10) + (c - '0'); - } -#if PRINTF_ADVANCED_ENABLE - else if (c == '*') - { - field_width = (uint32_t)va_arg(ap, uint32_t); - } -#endif /* PRINTF_ADVANCED_ENABLE */ - else - { - /* We've gone one char too far. */ - --p; - done = true; - } - } - /* Next check for the width and precision field separator. */ - precision_width = 6; -#if PRINTF_ADVANCED_ENABLE - valid_precision_width = false; -#endif /* PRINTF_ADVANCED_ENABLE */ - if (*++p == '.') - { - /* Must get precision field width, if present. */ - precision_width = 0; - done = false; - while (!done) - { - c = *++p; - if ((c >= '0') && (c <= '9')) - { - precision_width = (precision_width * 10) + (c - '0'); -#if PRINTF_ADVANCED_ENABLE - valid_precision_width = true; -#endif /* PRINTF_ADVANCED_ENABLE */ - } -#if PRINTF_ADVANCED_ENABLE - else if (c == '*') - { - precision_width = (uint32_t)va_arg(ap, uint32_t); - valid_precision_width = true; - } -#endif /* PRINTF_ADVANCED_ENABLE */ - else - { - /* We've gone one char too far. */ - --p; - done = true; - } - } - } - else - { - /* We've gone one char too far. */ - --p; - } -#if PRINTF_ADVANCED_ENABLE - /* - * Check for the length modifier. - */ - switch (/* c = */ *++p) - { - case 'h': - if (*++p != 'h') - { - flags_used |= kPRINTF_LengthShortInt; - --p; - } - else - { - flags_used |= kPRINTF_LengthChar; - } - break; - case 'l': - if (*++p != 'l') - { - flags_used |= kPRINTF_LengthLongInt; - --p; - } - else - { - flags_used |= kPRINTF_LengthLongLongInt; - } - break; - default: - /* we've gone one char too far */ - --p; - break; - } -#endif /* PRINTF_ADVANCED_ENABLE */ - /* Now we're ready to examine the format. */ - c = *++p; - { - if ((c == 'd') || (c == 'i') || (c == 'f') || (c == 'F') || (c == 'x') || (c == 'X') || (c == 'o') || - (c == 'b') || (c == 'p') || (c == 'u')) - { - if ((c == 'd') || (c == 'i')) - { -#if PRINTF_ADVANCED_ENABLE - if (flags_used & kPRINTF_LengthLongLongInt) - { - ival = (int64_t)va_arg(ap, int64_t); - } - else -#endif /* PRINTF_ADVANCED_ENABLE */ - { - ival = (int32_t)va_arg(ap, int32_t); - } - vlen = DbgConsole_ConvertRadixNumToString(vstr, &ival, true, 10, use_caps); - vstrp = &vstr[vlen]; -#if PRINTF_ADVANCED_ENABLE - if (ival < 0) - { - schar = '-'; - ++vlen; - } - else - { - if (flags_used & kPRINTF_Plus) - { - schar = '+'; - ++vlen; - } - else - { - if (flags_used & kPRINTF_Space) - { - schar = ' '; - ++vlen; - } - else - { - schar = 0; - } - } - } - dschar = false; - /* Do the ZERO pad. */ - if (flags_used & kPRINTF_Zero) - { - if (schar) - { - func_ptr(schar); - count++; - } - dschar = true; - - DbgConsole_PrintfPaddingCharacter('0', vlen, field_width, &count, func_ptr); - vlen = field_width; - } - else - { - if (!(flags_used & kPRINTF_Minus)) - { - DbgConsole_PrintfPaddingCharacter(' ', vlen, field_width, &count, func_ptr); - if (schar) - { - func_ptr(schar); - count++; - } - dschar = true; - } - } - /* The string was built in reverse order, now display in correct order. */ - if ((!dschar) && schar) - { - func_ptr(schar); - count++; - } -#endif /* PRINTF_ADVANCED_ENABLE */ - } - -#if PRINTF_FLOAT_ENABLE - if ((c == 'f') || (c == 'F')) - { - fval = (double)va_arg(ap, double); - vlen = DbgConsole_ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width); - vstrp = &vstr[vlen]; - -#if PRINTF_ADVANCED_ENABLE - if (fval < 0) - { - schar = '-'; - ++vlen; - } - else - { - if (flags_used & kPRINTF_Plus) - { - schar = '+'; - ++vlen; - } - else - { - if (flags_used & kPRINTF_Space) - { - schar = ' '; - ++vlen; - } - else - { - schar = 0; - } - } - } - dschar = false; - if (flags_used & kPRINTF_Zero) - { - if (schar) - { - func_ptr(schar); - count++; - } - dschar = true; - DbgConsole_PrintfPaddingCharacter('0', vlen, field_width, &count, func_ptr); - vlen = field_width; - } - else - { - if (!(flags_used & kPRINTF_Minus)) - { - DbgConsole_PrintfPaddingCharacter(' ', vlen, field_width, &count, func_ptr); - if (schar) - { - func_ptr(schar); - count++; - } - dschar = true; - } - } - if ((!dschar) && schar) - { - func_ptr(schar); - count++; - } -#endif /* PRINTF_ADVANCED_ENABLE */ - } -#endif /* PRINTF_FLOAT_ENABLE */ - if ((c == 'X') || (c == 'x')) - { - if (c == 'x') - { - use_caps = false; - } -#if PRINTF_ADVANCED_ENABLE - if (flags_used & kPRINTF_LengthLongLongInt) - { - uval = (uint64_t)va_arg(ap, uint64_t); - } - else -#endif /* PRINTF_ADVANCED_ENABLE */ - { - uval = (uint32_t)va_arg(ap, uint32_t); - } - vlen = DbgConsole_ConvertRadixNumToString(vstr, &uval, false, 16, use_caps); - vstrp = &vstr[vlen]; - -#if PRINTF_ADVANCED_ENABLE - dschar = false; - if (flags_used & kPRINTF_Zero) - { - if (flags_used & kPRINTF_Pound) - { - func_ptr('0'); - func_ptr((use_caps ? 'X' : 'x')); - count += 2; - /*vlen += 2;*/ - dschar = true; - } - DbgConsole_PrintfPaddingCharacter('0', vlen, field_width, &count, func_ptr); - vlen = field_width; - } - else - { - if (!(flags_used & kPRINTF_Minus)) - { - if (flags_used & kPRINTF_Pound) - { - vlen += 2; - } - DbgConsole_PrintfPaddingCharacter(' ', vlen, field_width, &count, func_ptr); - if (flags_used & kPRINTF_Pound) - { - func_ptr('0'); - func_ptr(use_caps ? 'X' : 'x'); - count += 2; - - dschar = true; - } - } - } - - if ((flags_used & kPRINTF_Pound) && (!dschar)) - { - func_ptr('0'); - func_ptr(use_caps ? 'X' : 'x'); - count += 2; - vlen += 2; - } -#endif /* PRINTF_ADVANCED_ENABLE */ - } - if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u')) - { -#if PRINTF_ADVANCED_ENABLE - if (flags_used & kPRINTF_LengthLongLongInt) - { - uval = (uint64_t)va_arg(ap, uint64_t); - } - else -#endif /* PRINTF_ADVANCED_ENABLE */ - { - uval = (uint32_t)va_arg(ap, uint32_t); - } - switch (c) - { - case 'o': - radix = 8; - break; - case 'b': - radix = 2; - break; - case 'p': - radix = 16; - break; - case 'u': - radix = 10; - break; - default: - break; - } - vlen = DbgConsole_ConvertRadixNumToString(vstr, &uval, false, radix, use_caps); - vstrp = &vstr[vlen]; -#if PRINTF_ADVANCED_ENABLE - if (flags_used & kPRINTF_Zero) - { - DbgConsole_PrintfPaddingCharacter('0', vlen, field_width, &count, func_ptr); - vlen = field_width; - } - else - { - if (!(flags_used & kPRINTF_Minus)) - { - DbgConsole_PrintfPaddingCharacter(' ', vlen, field_width, &count, func_ptr); - } - } -#endif /* PRINTF_ADVANCED_ENABLE */ - } -#if !PRINTF_ADVANCED_ENABLE - DbgConsole_PrintfPaddingCharacter(' ', vlen, field_width, &count, func_ptr); -#endif /* !PRINTF_ADVANCED_ENABLE */ - if (vstrp != NULL) - { - while (*vstrp) - { - func_ptr(*vstrp--); - count++; - } - } -#if PRINTF_ADVANCED_ENABLE - if (flags_used & kPRINTF_Minus) - { - DbgConsole_PrintfPaddingCharacter(' ', vlen, field_width, &count, func_ptr); - } -#endif /* PRINTF_ADVANCED_ENABLE */ - } - else if (c == 'c') - { - cval = (char)va_arg(ap, uint32_t); - func_ptr(cval); - count++; - } - else if (c == 's') - { - sval = (char *)va_arg(ap, char *); - if (sval) - { -#if PRINTF_ADVANCED_ENABLE - if (valid_precision_width) - { - vlen = precision_width; - } - else - { - vlen = strlen(sval); - } -#else - vlen = strlen(sval); -#endif /* PRINTF_ADVANCED_ENABLE */ -#if PRINTF_ADVANCED_ENABLE - if (!(flags_used & kPRINTF_Minus)) -#endif /* PRINTF_ADVANCED_ENABLE */ - { - DbgConsole_PrintfPaddingCharacter(' ', vlen, field_width, &count, func_ptr); - } - -#if PRINTF_ADVANCED_ENABLE - if (valid_precision_width) - { - while ((*sval) && (vlen > 0)) - { - func_ptr(*sval++); - count++; - vlen--; - } - /* In case that vlen sval is shorter than vlen */ - vlen = precision_width - vlen; - } - else - { -#endif /* PRINTF_ADVANCED_ENABLE */ - while (*sval) - { - func_ptr(*sval++); - count++; - } -#if PRINTF_ADVANCED_ENABLE - } -#endif /* PRINTF_ADVANCED_ENABLE */ - -#if PRINTF_ADVANCED_ENABLE - if (flags_used & kPRINTF_Minus) - { - DbgConsole_PrintfPaddingCharacter(' ', vlen, field_width, &count, func_ptr); - } -#endif /* PRINTF_ADVANCED_ENABLE */ - } - } - else - { - func_ptr(c); - count++; - } - } - } - return count; -} - -/*! - * @brief Converts an input line of ASCII characters based upon a provided - * string format. - * - * @param[in] line_ptr The input line of ASCII data. - * @param[in] format Format first points to the format string. - * @param[in] args_ptr The list of parameters. - * - * @return Number of input items converted and assigned. - * @retval IO_EOF When line_ptr is empty string "". - */ -static int DbgConsole_ScanfFormattedData(const char *line_ptr, char *format, va_list args_ptr) -{ - uint8_t base; - int8_t neg; - /* Identifier for the format string. */ - char *c = format; - char temp; - char *buf; - /* Flag telling the conversion specification. */ - uint32_t flag = 0; - /* Filed width for the matching input streams. */ - uint32_t field_width; - /* How many arguments are assigned except the suppress. */ - uint32_t nassigned = 0; - /* How many characters are read from the input streams. */ - uint32_t n_decode = 0; - - int32_t val; - - const char *s; - /* Identifier for the input string. */ - const char *p = line_ptr; - - /* Return EOF error before any conversion. */ - if (*p == '\0') - { - return -1; - } - - /* Decode directives. */ - while ((*c) && (*p)) - { - /* Ignore all white-spaces in the format strings. */ - if (DbgConsole_ScanIgnoreWhiteSpace((const char **)&c)) - { - n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p); - } - else if ((*c != '%') || ((*c == '%') && (*(c + 1) == '%'))) - { - /* Ordinary characters. */ - c++; - if (*p == *c) - { - n_decode++; - p++; - c++; - } - else - { - /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream. - * However, it is deserted now. */ - break; - } - } - else - { - /* convernsion specification */ - c++; - /* Reset. */ - flag = 0; - field_width = 0; - base = 0; - - /* Loop to get full conversion specification. */ - while ((*c) && (!(flag & kSCANF_DestMask))) - { - switch (*c) - { -#if SCANF_ADVANCED_ENABLE - case '*': - if (flag & kSCANF_Suppress) - { - /* Match failure. */ - return nassigned; - } - flag |= kSCANF_Suppress; - c++; - break; - case 'h': - if (flag & kSCANF_LengthMask) - { - /* Match failure. */ - return nassigned; - } - - if (c[1] == 'h') - { - flag |= kSCANF_LengthChar; - c++; - } - else - { - flag |= kSCANF_LengthShortInt; - } - c++; - break; - case 'l': - if (flag & kSCANF_LengthMask) - { - /* Match failure. */ - return nassigned; - } - - if (c[1] == 'l') - { - flag |= kSCANF_LengthLongLongInt; - c++; - } - else - { - flag |= kSCANF_LengthLongInt; - } - c++; - break; -#endif /* SCANF_ADVANCED_ENABLE */ -#if SCANF_FLOAT_ENABLE - case 'L': - if (flag & kSCANF_LengthMask) - { - /* Match failure. */ - return nassigned; - } - flag |= kSCANF_LengthLongLongDouble; - c++; - break; -#endif /* SCANF_FLOAT_ENABLE */ - case '0': - case '1': - case '2': - case '3': - case '4': - case '5': - case '6': - case '7': - case '8': - case '9': - if (field_width) - { - /* Match failure. */ - return nassigned; - } - do - { - field_width = field_width * 10 + *c - '0'; - c++; - } while ((*c >= '0') && (*c <= '9')); - break; - case 'd': - base = 10; - flag |= kSCANF_TypeSinged; - flag |= kSCANF_DestInt; - c++; - break; - case 'u': - base = 10; - flag |= kSCANF_DestInt; - c++; - break; - case 'o': - base = 8; - flag |= kSCANF_DestInt; - c++; - break; - case 'x': - case 'X': - base = 16; - flag |= kSCANF_DestInt; - c++; - break; - case 'i': - base = 0; - flag |= kSCANF_DestInt; - c++; - break; -#if SCANF_FLOAT_ENABLE - case 'a': - case 'A': - case 'e': - case 'E': - case 'f': - case 'F': - case 'g': - case 'G': - flag |= kSCANF_DestFloat; - c++; - break; -#endif /* SCANF_FLOAT_ENABLE */ - case 'c': - flag |= kSCANF_DestChar; - if (!field_width) - { - field_width = 1; - } - c++; - break; - case 's': - flag |= kSCANF_DestString; - c++; - break; - default: - return nassigned; - } - } - - if (!(flag & kSCANF_DestMask)) - { - /* Format strings are exhausted. */ - return nassigned; - } - - if (!field_width) - { - /* Large than length of a line. */ - field_width = 99; - } - - /* Matching strings in input streams and assign to argument. */ - switch (flag & kSCANF_DestMask) - { - case kSCANF_DestChar: - s = (const char *)p; - buf = va_arg(args_ptr, char *); - while ((field_width--) && (*p)) - { - if (!(flag & kSCANF_Suppress)) - { - *buf++ = *p++; - } - else - { - p++; - } - n_decode++; - } - - if ((!(flag & kSCANF_Suppress)) && (s != p)) - { - nassigned++; - } - break; - case kSCANF_DestString: - n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p); - s = p; - buf = va_arg(args_ptr, char *); - while ((field_width--) && (*p != '\0') && (*p != ' ') && (*p != '\t') && (*p != '\n') && - (*p != '\r') && (*p != '\v') && (*p != '\f')) - { - if (flag & kSCANF_Suppress) - { - p++; - } - else - { - *buf++ = *p++; - } - n_decode++; - } - - if ((!(flag & kSCANF_Suppress)) && (s != p)) - { - /* Add NULL to end of string. */ - *buf = '\0'; - nassigned++; - } - break; - case kSCANF_DestInt: - n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p); - s = p; - val = 0; - if ((base == 0) || (base == 16)) - { - if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) - { - base = 16; - if (field_width >= 1) - { - p += 2; - n_decode += 2; - field_width -= 2; - } - } - } - - if (base == 0) - { - if (s[0] == '0') - { - base = 8; - } - else - { - base = 10; - } - } - - neg = 1; - switch (*p) - { - case '-': - neg = -1; - n_decode++; - p++; - field_width--; - break; - case '+': - neg = 1; - n_decode++; - p++; - field_width--; - break; - default: - break; - } - - while ((*p) && (field_width--)) - { - if ((*p <= '9') && (*p >= '0')) - { - temp = *p - '0'; - } - else if ((*p <= 'f') && (*p >= 'a')) - { - temp = *p - 'a' + 10; - } - else if ((*p <= 'F') && (*p >= 'A')) - { - temp = *p - 'A' + 10; - } - else - { - temp = base; - } - - if (temp >= base) - { - break; - } - else - { - val = base * val + temp; - } - p++; - n_decode++; - } - val *= neg; - if (!(flag & kSCANF_Suppress)) - { -#if SCANF_ADVANCED_ENABLE - switch (flag & kSCANF_LengthMask) - { - case kSCANF_LengthChar: - if (flag & kSCANF_TypeSinged) - { - *va_arg(args_ptr, signed char *) = (signed char)val; - } - else - { - *va_arg(args_ptr, unsigned char *) = (unsigned char)val; - } - break; - case kSCANF_LengthShortInt: - if (flag & kSCANF_TypeSinged) - { - *va_arg(args_ptr, signed short *) = (signed short)val; - } - else - { - *va_arg(args_ptr, unsigned short *) = (unsigned short)val; - } - break; - case kSCANF_LengthLongInt: - if (flag & kSCANF_TypeSinged) - { - *va_arg(args_ptr, signed long int *) = (signed long int)val; - } - else - { - *va_arg(args_ptr, unsigned long int *) = (unsigned long int)val; - } - break; - case kSCANF_LengthLongLongInt: - if (flag & kSCANF_TypeSinged) - { - *va_arg(args_ptr, signed long long int *) = (signed long long int)val; - } - else - { - *va_arg(args_ptr, unsigned long long int *) = (unsigned long long int)val; - } - break; - default: - /* The default type is the type int. */ - if (flag & kSCANF_TypeSinged) - { - *va_arg(args_ptr, signed int *) = (signed int)val; - } - else - { - *va_arg(args_ptr, unsigned int *) = (unsigned int)val; - } - break; - } -#else - /* The default type is the type int. */ - if (flag & kSCANF_TypeSinged) - { - *va_arg(args_ptr, signed int *) = (signed int)val; - } - else - { - *va_arg(args_ptr, unsigned int *) = (unsigned int)val; - } -#endif /* SCANF_ADVANCED_ENABLE */ - nassigned++; - } - break; -#if SCANF_FLOAT_ENABLE - case kSCANF_DestFloat: - n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p); - fnum = strtod(p, (char **)&s); - - if ((fnum >= HUGE_VAL) || (fnum <= -HUGE_VAL)) - { - break; - } - - n_decode += (int)(s) - (int)(p); - p = s; - if (!(flag & kSCANF_Suppress)) - { - if (flag & kSCANF_LengthLongLongDouble) - { - *va_arg(args_ptr, double *) = fnum; - } - else - { - *va_arg(args_ptr, float *) = (float)fnum; - } - nassigned++; - } - break; -#endif /* SCANF_FLOAT_ENABLE */ - default: - return nassigned; - } - } - } - return nassigned; -} -#endif /* SDK_DEBUGCONSOLE */ -/*************Code to support toolchain's printf, scanf *******************************/ -/* These function __write and __read is used to support IAR toolchain to printf and scanf*/ -#if (defined(__ICCARM__)) -#pragma weak __write -size_t __write(int handle, const unsigned char *buffer, size_t size) -{ - if (buffer == 0) - { - /* - * This means that we should flush internal buffers. Since we don't we just return. - * (Remember, "handle" == -1 means that all handles should be flushed.) - */ - return 0; - } - - /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ - if ((handle != 1) && (handle != 2)) - { - return ((size_t)-1); - } - - /* Do nothing if the debug UART is not initialized. */ - if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE) - { - return ((size_t)-1); - } - - /* Send data. */ - s_debugConsole.ops.tx_union.PutChar(s_debugConsole.base, buffer, 1); - return size; -} - -#pragma weak __read -size_t __read(int handle, unsigned char *buffer, size_t size) -{ - /* This function only reads from "standard in", for all other file handles it returns failure. */ - if (handle != 0) - { - return ((size_t)-1); - } - - /* Do nothing if the debug UART is not initialized. */ - if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE) - { - return ((size_t)-1); - } - - /* Receive data. */ - s_debugConsole.ops.rx_union.GetChar(s_debugConsole.base, buffer, size); - - return size; -} - -/* support LPC Xpresso with RedLib */ -#elif(defined(__REDLIB__)) - -#if (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART)) -int __attribute__((weak)) __sys_write(int handle, char *buffer, int size) -{ - if (buffer == 0) - { - /* return -1 if error. */ - return -1; - } - - /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ - if ((handle != 1) && (handle != 2)) - { - return -1; - } - - /* Do nothing if the debug UART is not initialized. */ - if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE) - { - return -1; - } - - /* Send data. */ - s_debugConsole.ops.tx_union.PutChar(s_debugConsole.base, (uint8_t *)buffer, size); - return 0; -} - -int __attribute__((weak)) __sys_readc(void) -{ - char tmp; - /* Do nothing if the debug UART is not initialized. */ - if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE) - { - return -1; - } - - /* Receive data. */ - s_debugConsole.ops.rx_union.GetChar(s_debugConsole.base, (uint8_t *)&tmp, sizeof(tmp)); - return tmp; -} -#endif - -/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/ -#elif(defined(__GNUC__)) - -#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO))) || \ - (defined(__MCUXPRESSO) && (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART)))) - -int __attribute__((weak)) _write(int handle, char *buffer, int size) -{ - if (buffer == 0) - { - /* return -1 if error. */ - return -1; - } - - /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ - if ((handle != 1) && (handle != 2)) - { - return -1; - } - - /* Do nothing if the debug UART is not initialized. */ - if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE) - { - return -1; - } - - /* Send data. */ - s_debugConsole.ops.tx_union.PutChar(s_debugConsole.base, (uint8_t *)buffer, size); - return size; -} - -int __attribute__((weak)) _read(int handle, char *buffer, int size) -{ - /* This function only reads from "standard in", for all other file handles it returns failure. */ - if (handle != 0) - { - return -1; - } - - /* Do nothing if the debug UART is not initialized. */ - if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE) - { - return -1; - } - - /* Receive data. */ - s_debugConsole.ops.rx_union.GetChar(s_debugConsole.base, (uint8_t *)buffer, size); - return size; -} -#endif - -/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/ -#elif defined(__CC_ARM) -struct __FILE -{ - int handle; - /* - * Whatever you require here. If the only file you are using is standard output using printf() for debugging, - * no file handling is required. - */ -}; - -/* FILE is typedef in stdio.h. */ -#pragma weak __stdout -#pragma weak __stdin -FILE __stdout; -FILE __stdin; - -#pragma weak fputc -int fputc(int ch, FILE *f) -{ - /* Do nothing if the debug UART is not initialized. */ - if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE) - { - return -1; - } - - /* Send data. */ - s_debugConsole.ops.tx_union.PutChar(s_debugConsole.base, (uint8_t *)(&ch), 1); - return 1; -} - -#pragma weak fgetc -int fgetc(FILE *f) -{ - char ch; - /* Do nothing if the debug UART is not initialized. */ - if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE) - { - return -1; - } - - /* Receive data. */ - s_debugConsole.ops.rx_union.GetChar(s_debugConsole.base, (uint8_t *)(&ch), 1); - return ch; -} -#endif /* __ICCARM__ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/utilities/fsl_debug_console.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/utilities/fsl_debug_console.h deleted file mode 100644 index 6c50de58290..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/LPC54608/utilities/fsl_debug_console.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Debug console shall provide input and output functions to scan and print formatted data. - * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier" - * - [flags] :'-', '+', '#', ' ', '0' - * - [width]: number (0,1...) - * - [.precision]: number (0,1...) - * - [length]: do not support - * - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n' - * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier" - * - [*]: is supported. - * - [width]: number (0,1...) - * - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t') - * - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's' - */ - -#ifndef _FSL_DEBUGCONSOLE_H_ -#define _FSL_DEBUGCONSOLE_H_ - -#include "fsl_common.h" - -/* - * @addtogroup debugconsole - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Definition to select sdk or toolchain printf, scanf. */ -#ifndef SDK_DEBUGCONSOLE -#define SDK_DEBUGCONSOLE 1U -#endif - -#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE) -#include -#endif - -/*! @brief Definition to printf the float number. */ -#ifndef PRINTF_FLOAT_ENABLE -#define PRINTF_FLOAT_ENABLE 0U -#endif /* PRINTF_FLOAT_ENABLE */ - -/*! @brief Definition to scanf the float number. */ -#ifndef SCANF_FLOAT_ENABLE -#define SCANF_FLOAT_ENABLE 0U -#endif /* SCANF_FLOAT_ENABLE */ - -/*! @brief Definition to support advanced format specifier for printf. */ -#ifndef PRINTF_ADVANCED_ENABLE -#define PRINTF_ADVANCED_ENABLE 0U -#endif /* PRINTF_ADVANCED_ENABLE */ - -/*! @brief Definition to support advanced format specifier for scanf. */ -#ifndef SCANF_ADVANCED_ENABLE -#define SCANF_ADVANCED_ENABLE 0U -#endif /* SCANF_ADVANCED_ENABLE */ - -#if SDK_DEBUGCONSOLE /* Select printf, scanf, putchar, getchar of SDK version. */ -#define PRINTF DbgConsole_Printf -#define SCANF DbgConsole_Scanf -#define PUTCHAR DbgConsole_Putchar -#define GETCHAR DbgConsole_Getchar -#else /* Select printf, scanf, putchar, getchar of toolchain. */ -#define PRINTF printf -#define SCANF scanf -#define PUTCHAR putchar -#define GETCHAR getchar -#endif /* SDK_DEBUGCONSOLE */ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! @name Initialization*/ -/* @{ */ - -/*! - * @brief Initializes the the peripheral used for debug messages. - * - * Call this function to enable debug log messages to be output via the specified peripheral, - * frequency of peripheral source clock, and base address at the specified baud rate. - * After this function has returned, stdout and stdin are connected to the selected peripheral. - * - * @param baseAddr Indicates the address of the peripheral used to send debug messages. - * @param baudRate The desired baud rate in bits per second. - * @param device Low level device type for the debug console, can be one of the following. - * @arg DEBUG_CONSOLE_DEVICE_TYPE_UART, - * @arg DEBUG_CONSOLE_DEVICE_TYPE_LPUART, - * @arg DEBUG_CONSOLE_DEVICE_TYPE_LPSCI, - * @arg DEBUG_CONSOLE_DEVICE_TYPE_USBCDC. - * @param clkSrcFreq Frequency of peripheral source clock. - * - * @return Indicates whether initialization was successful or not. - * @retval kStatus_Success Execution successfully - * @retval kStatus_Fail Execution failure - * @retval kStatus_InvalidArgument Invalid argument existed - */ -status_t DbgConsole_Init(uint32_t baseAddr, uint32_t baudRate, uint8_t device, uint32_t clkSrcFreq); - -/*! - * @brief De-initializes the peripheral used for debug messages. - * - * Call this function to disable debug log messages to be output via the specified peripheral - * base address and at the specified baud rate. - * - * @return Indicates whether de-initialization was successful or not. - */ -status_t DbgConsole_Deinit(void); - -#if SDK_DEBUGCONSOLE -/*! - * @brief Writes formatted output to the standard output stream. - * - * Call this function to write a formatted output to the standard output stream. - * - * @param fmt_s Format control string. - * @return Returns the number of characters printed or a negative value if an error occurs. - */ -int DbgConsole_Printf(const char *fmt_s, ...); - -/*! - * @brief Writes a character to stdout. - * - * Call this function to write a character to stdout. - * - * @param ch Character to be written. - * @return Returns the character written. - */ -int DbgConsole_Putchar(int ch); - -/*! - * @brief Reads formatted data from the standard input stream. - * - * Call this function to read formatted data from the standard input stream. - * - * @param fmt_ptr Format control string. - * @return Returns the number of fields successfully converted and assigned. - */ -int DbgConsole_Scanf(char *fmt_ptr, ...); - -/*! - * @brief Reads a character from standard input. - * - * Call this function to read a character from standard input. - * - * @return Returns the character read. - */ -int DbgConsole_Getchar(void); - -#endif /* SDK_DEBUGCONSOLE */ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @} */ - -#endif /* _FSL_DEBUGCONSOLE_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/SConscript b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/SConscript deleted file mode 100644 index 4c815c49b83..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/devices/SConscript +++ /dev/null @@ -1,15 +0,0 @@ -# RT-Thread building script for bridge - -import os -from building import * - -cwd = GetCurrentDir() -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/SConscript b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/SConscript deleted file mode 100644 index 4c815c49b83..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/SConscript +++ /dev/null @@ -1,15 +0,0 @@ -# RT-Thread building script for bridge - -import os -from building import * - -cwd = GetCurrentDir() -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc/SConscript b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc/SConscript deleted file mode 100644 index f905bd300bb..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc/SConscript +++ /dev/null @@ -1,11 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -CPPPATH = [cwd] -src = Glob('*.c') - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc/fsl_card.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc/fsl_card.h deleted file mode 100644 index f6cec76e1ce..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc/fsl_card.h +++ /dev/null @@ -1,665 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_CARD_H_ -#define _FSL_CARD_H_ - -#include "fsl_common.h" -#include "fsl_specification.h" -#include "fsl_host.h" - -/*! - * @addtogroup CARD - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief Driver version. */ -#define FSL_SDMMC_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 2U)) /*2.1.2*/ - -/*! @brief Default block size */ -#define FSL_SDMMC_DEFAULT_BLOCK_SIZE (512U) - -/*! @brief SD/MMC card API's running status. */ -enum _sdmmc_status -{ - kStatus_SDMMC_NotSupportYet = MAKE_STATUS(kStatusGroup_SDMMC, 0U), /*!< Haven't supported */ - kStatus_SDMMC_TransferFailed = MAKE_STATUS(kStatusGroup_SDMMC, 1U), /*!< Send command failed */ - kStatus_SDMMC_SetCardBlockSizeFailed = MAKE_STATUS(kStatusGroup_SDMMC, 2U), /*!< Set block size failed */ - kStatus_SDMMC_HostNotSupport = MAKE_STATUS(kStatusGroup_SDMMC, 3U), /*!< Host doesn't support */ - kStatus_SDMMC_CardNotSupport = MAKE_STATUS(kStatusGroup_SDMMC, 4U), /*!< Card doesn't support */ - kStatus_SDMMC_AllSendCidFailed = MAKE_STATUS(kStatusGroup_SDMMC, 5U), /*!< Send CID failed */ - kStatus_SDMMC_SendRelativeAddressFailed = MAKE_STATUS(kStatusGroup_SDMMC, 6U), /*!< Send relative address failed */ - kStatus_SDMMC_SendCsdFailed = MAKE_STATUS(kStatusGroup_SDMMC, 7U), /*!< Send CSD failed */ - kStatus_SDMMC_SelectCardFailed = MAKE_STATUS(kStatusGroup_SDMMC, 8U), /*!< Select card failed */ - kStatus_SDMMC_SendScrFailed = MAKE_STATUS(kStatusGroup_SDMMC, 9U), /*!< Send SCR failed */ - kStatus_SDMMC_SetDataBusWidthFailed = MAKE_STATUS(kStatusGroup_SDMMC, 10U), /*!< Set bus width failed */ - kStatus_SDMMC_GoIdleFailed = MAKE_STATUS(kStatusGroup_SDMMC, 11U), /*!< Go idle failed */ - kStatus_SDMMC_HandShakeOperationConditionFailed = - MAKE_STATUS(kStatusGroup_SDMMC, 12U), /*!< Send Operation Condition failed */ - kStatus_SDMMC_SendApplicationCommandFailed = - MAKE_STATUS(kStatusGroup_SDMMC, 13U), /*!< Send application command failed */ - kStatus_SDMMC_SwitchFailed = MAKE_STATUS(kStatusGroup_SDMMC, 14U), /*!< Switch command failed */ - kStatus_SDMMC_StopTransmissionFailed = MAKE_STATUS(kStatusGroup_SDMMC, 15U), /*!< Stop transmission failed */ - kStatus_SDMMC_WaitWriteCompleteFailed = MAKE_STATUS(kStatusGroup_SDMMC, 16U), /*!< Wait write complete failed */ - kStatus_SDMMC_SetBlockCountFailed = MAKE_STATUS(kStatusGroup_SDMMC, 17U), /*!< Set block count failed */ - kStatus_SDMMC_SetRelativeAddressFailed = MAKE_STATUS(kStatusGroup_SDMMC, 18U), /*!< Set relative address failed */ - kStatus_SDMMC_SwitchBusTimingFailed = MAKE_STATUS(kStatusGroup_SDMMC, 19U), /*!< Switch high speed failed */ - kStatus_SDMMC_SendExtendedCsdFailed = MAKE_STATUS(kStatusGroup_SDMMC, 20U), /*!< Send EXT_CSD failed */ - kStatus_SDMMC_ConfigureBootFailed = MAKE_STATUS(kStatusGroup_SDMMC, 21U), /*!< Configure boot failed */ - kStatus_SDMMC_ConfigureExtendedCsdFailed = MAKE_STATUS(kStatusGroup_SDMMC, 22U), /*!< Configure EXT_CSD failed */ - kStatus_SDMMC_EnableHighCapacityEraseFailed = - MAKE_STATUS(kStatusGroup_SDMMC, 23U), /*!< Enable high capacity erase failed */ - kStatus_SDMMC_SendTestPatternFailed = MAKE_STATUS(kStatusGroup_SDMMC, 24U), /*!< Send test pattern failed */ - kStatus_SDMMC_ReceiveTestPatternFailed = MAKE_STATUS(kStatusGroup_SDMMC, 25U), /*!< Receive test pattern failed */ - kStatus_SDMMC_SDIO_ResponseError = MAKE_STATUS(kStatusGroup_SDMMC, 26U), /*!< sdio response error */ - kStatus_SDMMC_SDIO_InvalidArgument = - MAKE_STATUS(kStatusGroup_SDMMC, 27U), /*!< sdio invalid argument response error */ - kStatus_SDMMC_SDIO_SendOperationConditionFail = - MAKE_STATUS(kStatusGroup_SDMMC, 28U), /*!< sdio send operation condition fail */ - kStatus_SDMMC_InvalidVoltage = MAKE_STATUS(kStatusGroup_SDMMC, 29U), /*!< invaild voltage */ - kStatus_SDMMC_SDIO_SwitchHighSpeedFail = MAKE_STATUS(kStatusGroup_SDMMC, 30U), /*!< switch to high speed fail */ - kStatus_SDMMC_SDIO_ReadCISFail = MAKE_STATUS(kStatusGroup_SDMMC, 31U), /*!< read CIS fail */ - kStatus_SDMMC_SDIO_InvalidCard = MAKE_STATUS(kStatusGroup_SDMMC, 32U), /*!< invaild SDIO card */ - kStatus_SDMMC_TuningFail = MAKE_STATUS(kStatusGroup_SDMMC, 33U), /*!< tuning fail */ - kStatus_SDMMC_SwitchVoltageFail = MAKE_STATUS(kStatusGroup_SDMMC, 34U), /*!< switch voltage fail*/ - kStatus_SDMMC_ReTuningRequest = MAKE_STATUS(kStatusGroup_SDMMC, 35U), /*!< retuning request */ - kStatus_SDMMC_SetDriverStrengthFail = MAKE_STATUS(kStatusGroup_SDMMC, 36U), /*!< set driver strength fail */ - kStatus_SDMMC_SetPowerClassFail = MAKE_STATUS(kStatusGroup_SDMMC, 37U), /*!< set power class fail */ -}; - -/*! @brief SD card flags */ -enum _sd_card_flag -{ - kSD_SupportHighCapacityFlag = (1U << 1U), /*!< Support high capacity */ - kSD_Support4BitWidthFlag = (1U << 2U), /*!< Support 4-bit data width */ - kSD_SupportSdhcFlag = (1U << 3U), /*!< Card is SDHC */ - kSD_SupportSdxcFlag = (1U << 4U), /*!< Card is SDXC */ - kSD_SupportVoltage180v = (1U << 5U), /*!< card support 1.8v voltage*/ - kSD_SupportSetBlockCountCmd = (1U << 6U), /*!< card support cmd23 flag*/ - kSD_SupportSpeedClassControlCmd = (1U << 7U), /*!< card support speed class control flag */ -}; - -/*! @brief MMC card flags */ -enum _mmc_card_flag -{ - kMMC_SupportHighSpeed26MHZFlag = (1U << 0U), /*!< Support high speed 26MHZ */ - kMMC_SupportHighSpeed52MHZFlag = (1U << 1U), /*!< Support high speed 52MHZ */ - kMMC_SupportHighSpeedDDR52MHZ180V300VFlag = (1 << 2U), /*!< ddr 52MHZ 1.8V or 3.0V */ - kMMC_SupportHighSpeedDDR52MHZ120VFlag = (1 << 3U), /*!< DDR 52MHZ 1.2V */ - kMMC_SupportHS200200MHZ180VFlag = (1 << 4U), /*!< HS200 ,200MHZ,1.8V */ - kMMC_SupportHS200200MHZ120VFlag = (1 << 5U), /*!< HS200, 200MHZ, 1.2V */ - kMMC_SupportHS400DDR200MHZ180VFlag = (1 << 6U), /*!< HS400, DDR, 200MHZ,1.8V */ - kMMC_SupportHS400DDR200MHZ120VFlag = (1 << 7U), /*!< HS400, DDR, 200MHZ,1.2V */ - kMMC_SupportHighCapacityFlag = (1U << 8U), /*!< Support high capacity */ - kMMC_SupportAlternateBootFlag = (1U << 9U), /*!< Support alternate boot */ - kMMC_SupportDDRBootFlag = (1U << 10U), /*!< support DDR boot flag*/ - kMMC_SupportHighSpeedBootFlag = (1U << 11U), /*!< support high speed boot flag*/ - - kMMC_DataBusWidth4BitFlag = (1U << 12U), /*!< current data bus is 4 bit mode*/ - kMMC_DataBusWidth8BitFlag = (1U << 13U), /*!< current data bus is 8 bit mode*/ - kMMC_DataBusWidth1BitFlag = (1U << 14U), /*!< current data bus is 1 bit mode */ - -}; - -/*! @brief card operation voltage */ -typedef enum _card_operation_voltage -{ - kCARD_OperationVoltageNone = 0U, /*!< indicate current voltage setting is not setting bu suser*/ - kCARD_OperationVoltage330V = 1U, /*!< card operation voltage around 3.3v */ - kCARD_OperationVoltage300V = 2U, /*!< card operation voltage around 3.0v */ - kCARD_OperationVoltage180V = 3U, /*!< card operation voltage around 31.8v */ -} card_operation_voltage_t; - -/*! - * @brief SD card state - * - * Define the card structure including the necessary fields to identify and describe the card. - */ -typedef struct _sd_card -{ - HOST_CONFIG host; /*!< Host information */ - - bool isHostReady; /*!< use this flag to indicate if need host re-init or not*/ - uint32_t busClock_Hz; /*!< SD bus clock frequency united in Hz */ - uint32_t relativeAddress; /*!< Relative address of the card */ - uint32_t version; /*!< Card version */ - uint32_t flags; /*!< Flags in _sd_card_flag */ - uint32_t rawCid[4U]; /*!< Raw CID content */ - uint32_t rawCsd[4U]; /*!< Raw CSD content */ - uint32_t rawScr[2U]; /*!< Raw CSD content */ - uint32_t ocr; /*!< Raw OCR content */ - sd_cid_t cid; /*!< CID */ - sd_csd_t csd; /*!< CSD */ - sd_scr_t scr; /*!< SCR */ - uint32_t blockCount; /*!< Card total block number */ - uint32_t blockSize; /*!< Card block size */ - sd_timing_mode_t currentTiming; /*!< current timing mode */ - sd_driver_strength_t driverStrength; /*!< driver strength */ - sd_max_current_t maxCurrent; /*!< card current limit */ - card_operation_voltage_t operationVoltage; /*!< card operation voltage */ -} sd_card_t; - -/*! - * @brief SDIO card state - * - * Define the card structure including the necessary fields to identify and describe the card. - */ -typedef struct _sdio_card -{ - HOST_CONFIG host; /*!< Host information */ - - bool isHostReady; /*!< use this flag to indicate if need host re-init or not*/ - bool memPresentFlag; /*!< indicate if memory present */ - - uint32_t busClock_Hz; /*!< SD bus clock frequency united in Hz */ - uint32_t relativeAddress; /*!< Relative address of the card */ - uint8_t sdVersion; /*!< SD version */ - uint8_t sdioVersion; /*!< SDIO version */ - uint8_t cccrVersioin; /*!< CCCR version */ - uint8_t ioTotalNumber; /*!< total number of IO function */ - uint32_t cccrflags; /*!< Flags in _sd_card_flag */ - uint32_t io0blockSize; /*!< record the io0 block size*/ - uint32_t ocr; /*!< Raw OCR content, only 24bit avalible for SDIO card */ - uint32_t commonCISPointer; /*!< point to common CIS */ - - sdio_fbr_t ioFBR[7U]; /*!< FBR table */ - - sdio_common_cis_t commonCIS; /*!< CIS table */ - sdio_func_cis_t funcCIS[7U]; /*!< function CIS table*/ - -} sdio_card_t; - -/*! - * @brief SD card state - * - * Define the card structure including the necessary fields to identify and describe the card. - */ -typedef struct _mmc_card -{ - HOST_CONFIG host; /*!< Host information */ - - bool isHostReady; /*!< use this flag to indicate if need host re-init or not*/ - uint32_t busClock_Hz; /*!< MMC bus clock united in Hz */ - uint32_t relativeAddress; /*!< Relative address of the card */ - bool enablePreDefinedBlockCount; /*!< Enable PRE-DEFINED block count when read/write */ - uint32_t flags; /*!< Capability flag in _mmc_card_flag */ - uint32_t rawCid[4U]; /*!< Raw CID content */ - uint32_t rawCsd[4U]; /*!< Raw CSD content */ - uint32_t rawExtendedCsd[MMC_EXTENDED_CSD_BYTES / 4U]; /*!< Raw MMC Extended CSD content */ - uint32_t ocr; /*!< Raw OCR content */ - mmc_cid_t cid; /*!< CID */ - mmc_csd_t csd; /*!< CSD */ - mmc_extended_csd_t extendedCsd; /*!< Extended CSD */ - uint32_t blockSize; /*!< Card block size */ - uint32_t userPartitionBlocks; /*!< Card total block number in user partition */ - uint32_t bootPartitionBlocks; /*!< Boot partition size united as block size */ - uint32_t eraseGroupBlocks; /*!< Erase group size united as block size */ - mmc_access_partition_t currentPartition; /*!< Current access partition */ - mmc_voltage_window_t hostVoltageWindow; /*!< Host voltage window */ - mmc_high_speed_timing_t currentTiming; /*!< indicate the current host timing mode*/ - -} mmc_card_t; - -/*! @brief MMC card boot configuration definition. */ -typedef struct _mmc_boot_config -{ - bool enableBootAck; /*!< Enable boot ACK */ - mmc_boot_partition_enable_t bootPartition; /*!< Boot partition */ - bool retainBootBusWidth; /*!< If retain boot bus width */ - mmc_data_bus_width_t bootDataBusWidth; /*!< Boot data bus width */ -} mmc_boot_config_t; - -/* define a function pointer for tuning */ -typedef status_t (*card_send_tuning_func)(void *cardType); - -/************************************************************************************************* - * API - ************************************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name SDCARD Function - * @{ - */ - -/*! - * @brief Initializes the card on a specific host controller. - * - * This function initializes the card on a specific host controller. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_GoIdleFailed Go idle failed. - * @retval kStatus_SDMMC_NotSupportYet Card not support. - * @retval kStatus_SDMMC_SendOperationConditionFailed Send operation condition failed. - * @retval kStatus_SDMMC_AllSendCidFailed Send CID failed. - * @retval kStatus_SDMMC_SendRelativeAddressFailed Send relative address failed. - * @retval kStatus_SDMMC_SendCsdFailed Send CSD failed. - * @retval kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed. - * @retval kStatus_SDMMC_SendScrFailed Send SCR failed. - * @retval kStatus_SDMMC_SetBusWidthFailed Set bus width failed. - * @retval kStatus_SDMMC_SwitchHighSpeedFailed Switch high speed failed. - * @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. - * @retval kStatus_Success Operate successfully. - */ -status_t SD_Init(sd_card_t *card); - -/*! - * @brief Deinitializes the card. - * - * This function deinitializes the specific card. - * - * @param card Card descriptor. - */ -void SD_Deinit(sd_card_t *card); - -/*! - * @brief Checks whether the card is write-protected. - * - * This function checks if the card is write-protected via the CSD register. - * - * @param card The specific card. - * @retval true Card is read only. - * @retval false Card isn't read only. - */ -bool SD_CheckReadOnly(sd_card_t *card); - -/*! - * @brief Reads blocks from the specific card. - * - * This function reads blocks from the specific card with default block size defined by the - * SDHC_CARD_DEFAULT_BLOCK_SIZE. - * - * @param card Card descriptor. - * @param buffer The buffer to save the data read from card. - * @param startBlock The start block index. - * @param blockCount The number of blocks to read. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_SDMMC_CardNotSupport Card not support. - * @retval kStatus_SDMMC_NotSupportYet Not support now. - * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. - * @retval kStatus_Success Operate successfully. - */ -status_t SD_ReadBlocks(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); - -/*! - * @brief Writes blocks of data to the specific card. - * - * This function writes blocks to the specific card with default block size 512 bytes. - * - * @param card Card descriptor. - * @param buffer The buffer holding the data to be written to the card. - * @param startBlock The start block index. - * @param blockCount The number of blocks to write. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_SDMMC_NotSupportYet Not support now. - * @retval kStatus_SDMMC_CardNotSupport Card not support. - * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. - * @retval kStatus_Success Operate successfully. - */ -status_t SD_WriteBlocks(sd_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); - -/*! - * @brief Erases blocks of the specific card. - * - * This function erases blocks of the specific card with default block size 512 bytes. - * - * @param card Card descriptor. - * @param startBlock The start block index. - * @param blockCount The number of blocks to erase. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. - * @retval kStatus_Success Operate successfully. - */ -status_t SD_EraseBlocks(sd_card_t *card, uint32_t startBlock, uint32_t blockCount); - -/* @} */ - -/*! - * @name MMCCARD Function - * @{ - */ - -/*! - * @brief Initializes the MMC card. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_GoIdleFailed Go idle failed. - * @retval kStatus_SDMMC_SendOperationConditionFailed Send operation condition failed. - * @retval kStatus_SDMMC_AllSendCidFailed Send CID failed. - * @retval kStatus_SDMMC_SetRelativeAddressFailed Set relative address failed. - * @retval kStatus_SDMMC_SendCsdFailed Send CSD failed. - * @retval kStatus_SDMMC_CardNotSupport Card not support. - * @retval kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed. - * @retval kStatus_SDMMC_SendExtendedCsdFailed Send EXT_CSD failed. - * @retval kStatus_SDMMC_SetBusWidthFailed Set bus width failed. - * @retval kStatus_SDMMC_SwitchHighSpeedFailed Switch high speed failed. - * @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. - * @retval kStatus_Success Operate successfully. - */ -status_t MMC_Init(mmc_card_t *card); - -/*! - * @brief Deinitializes the card. - * - * @param card Card descriptor. - */ - -void MMC_Deinit(mmc_card_t *card); - -/*! - * @brief Checks if the card is read-only. - * - * @param card Card descriptor. - * @retval true Card is read only. - * @retval false Card isn't read only. - */ -bool MMC_CheckReadOnly(mmc_card_t *card); - -/*! - * @brief Reads data blocks from the card. - * - * @param card Card descriptor. - * @param buffer The buffer to save data. - * @param startBlock The start block index. - * @param blockCount The number of blocks to read. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_SDMMC_CardNotSupport Card not support. - * @retval kStatus_SDMMC_SetBlockCountFailed Set block count failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. - * @retval kStatus_Success Operate successfully. - */ -status_t MMC_ReadBlocks(mmc_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); - -/*! - * @brief Writes data blocks to the card. - * - * @param card Card descriptor. - * @param buffer The buffer to save data blocks. - * @param startBlock Start block number to write. - * @param blockCount Block count. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_SDMMC_NotSupportYet Not support now. - * @retval kStatus_SDMMC_SetBlockCountFailed Set block count failed. - * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. - * @retval kStatus_Success Operate successfully. - */ -status_t MMC_WriteBlocks(mmc_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); - -/*! - * @brief Erases groups of the card. - * - * Erase group is the smallest erase unit in MMC card. The erase range is [startGroup, endGroup]. - * - * @param card Card descriptor. - * @param startGroup Start group number. - * @param endGroup End group number. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -status_t MMC_EraseGroups(mmc_card_t *card, uint32_t startGroup, uint32_t endGroup); - -/*! - * @brief Selects the partition to access. - * - * @param card Card descriptor. - * @param partitionNumber The partition number. - * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure EXT_CSD failed. - * @retval kStatus_Success Operate successfully. - */ -status_t MMC_SelectPartition(mmc_card_t *card, mmc_access_partition_t partitionNumber); - -/*! - * @brief Configures the boot activity of the card. - * - * @param card Card descriptor. - * @param config Boot configuration structure. - * @retval kStatus_SDMMC_NotSupportYet Not support now. - * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure EXT_CSD failed. - * @retval kStatus_SDMMC_ConfigureBootFailed Configure boot failed. - * @retval kStatus_Success Operate successfully. - */ -status_t MMC_SetBootConfig(mmc_card_t *card, const mmc_boot_config_t *config); - -/*! - * @brief set SDIO card to inactive state - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed - * @retval kStatus_Success - */ -status_t SDIO_CardInActive(sdio_card_t *card); - -/*! - * @brief IO direct write transfer function - * - * @param card Card descriptor. - * @param function IO numner - * @param register address - * @param the data pinter to write - * @param raw flag, indicate read after write or write only - * @retval kStatus_SDMMC_TransferFailed - * @retval kStatus_Success - */ -status_t SDIO_IO_Write_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data, bool raw); - -/*! - * @brief IO direct read transfer function - * - * @param card Card descriptor. - * @param function IO number - * @param register address - * @param data pointer to read - * @retval kStatus_SDMMC_TransferFailed - * @retval kStatus_Success - */ -status_t SDIO_IO_Read_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data); - -/*! - * @brief IO extended write transfer function - * - * @param card Card descriptor. - * @param function IO number - * @param register address - * @param data buffer to write - * @param data count - * @param write flags - * @retval kStatus_SDMMC_TransferFailed - * @retval kStatus_SDMMC_SDIO_InvalidArgument - * @retval kStatus_Success - */ -status_t SDIO_IO_Write_Extended( - sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags); -/*! - * @brief IO extended read transfer function - * - * @param card Card descriptor. - * @param function IO number - * @param register address - * @param data buffer to read - * @param data count - * @param write flags - * @retval kStatus_SDMMC_TransferFailed - * @retval kStatus_SDMMC_SDIO_InvalidArgument - * @retval kStatus_Success - */ -status_t SDIO_IO_Read_Extended( - sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags); -/*! - * @brief get SDIO card capability - * - * @param card Card descriptor. - * @param function IO number - * @retval kStatus_SDMMC_TransferFailed - * @retval kStatus_Success - */ -status_t SDIO_GetCardCapability(sdio_card_t *card, sdio_func_num_t func); - -/*! - * @brief set SDIO card block size - * - * @param card Card descriptor. - * @param function io number - * @param block size - * @retval kStatus_SDMMC_SetCardBlockSizeFailed - * @retval kStatus_SDMMC_SDIO_InvalidArgument - * @retval kStatus_Success - */ -status_t SDIO_SetBlockSize(sdio_card_t *card, sdio_func_num_t func, uint32_t blockSize); - -/*! - * @brief set SDIO card reset - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed - * @retval kStatus_Success - */ -status_t SDIO_CardReset(sdio_card_t *card); - -/*! - * @brief set SDIO card data bus width - * - * @param card Card descriptor. - * @param data bus width - * @retval kStatus_SDMMC_TransferFailed - * @retval kStatus_Success - */ -status_t SDIO_SetDataBusWidth(sdio_card_t *card, sdio_bus_width_t busWidth); - -/*! - * @brief switch the card to high speed - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed - * @retval kStatus_SDMMC_SDIO_SwitchHighSpeedFail - * @retval kStatus_Success - */ -status_t SDIO_SwitchToHighSpeed(sdio_card_t *card); - -/*! - * @brief read SDIO card CIS for each function - * - * @param card Card descriptor. - * @param function io number - * @param tuple code list - * @param tuple code number - * @retval kStatus_SDMMC_SDIO_ReadCISFail - * @retval kStatus_SDMMC_TransferFailed - * @retval kStatus_Success - */ -status_t SDIO_ReadCIS(sdio_card_t *card, sdio_func_num_t func, const uint32_t *tupleList, uint32_t tupleNum); - -/*! - * @brief SDIO card init function - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_GoIdleFailed - * @retval kStatus_SDMMC_HandShakeOperationConditionFailed - * @retval kStatus_SDMMC_SDIO_InvalidCard - * @retval kStatus_SDMMC_SDIO_InvalidVoltage - * @retval kStatus_SDMMC_SendRelativeAddressFailed - * @retval kStatus_SDMMC_SelectCardFailed - * @retval kStatus_SDMMC_SDIO_SwitchHighSpeedFail - * @retval kStatus_SDMMC_SDIO_ReadCISFail - * @retval kStatus_SDMMC_TransferFailed - * @retval kStatus_Success - */ -status_t SDIO_Init(sdio_card_t *card); - -/*! - * @brief enable IO interrupt - * - * @param card Card descriptor. - * @param function IO number - * @param enable/disable flag - * @retval kStatus_SDMMC_TransferFailed - * @retval kStatus_Success - */ -status_t SDIO_EnableIOInterrupt(sdio_card_t *card, sdio_func_num_t func, bool enable); - -/*! - * @brief enable IO and wait IO ready - * - * @param card Card descriptor. - * @param function IO number - * @param enable/disable flag - * @retval kStatus_SDMMC_TransferFailed - * @retval kStatus_Success - */ -status_t SDIO_EnableIO(sdio_card_t *card, sdio_func_num_t func, bool enable); - -/*! - * @brief select IO - * - * @param card Card descriptor. - * @param function IO number - * @retval kStatus_SDMMC_TransferFailed - * @retval kStatus_Success - */ -status_t SDIO_SelectIO(sdio_card_t *card, sdio_func_num_t func); - -/*! - * @brief Abort IO transfer - * - * @param card Card descriptor. - * @param function IO number - * @retval kStatus_SDMMC_TransferFailed - * @retval kStatus_Success - */ -status_t SDIO_AbortIO(sdio_card_t *card, sdio_func_num_t func); - -/*! - * @brief SDIO card deinit - * - * @param card Card descriptor. - */ -void SDIO_DeInit(sdio_card_t *card); - -/* @} */ -#if defined(__cplusplus) -} -#endif -/*! @} */ -#endif /* _FSL_CARD_H_*/ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc/fsl_host.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc/fsl_host.h deleted file mode 100644 index 305b44ab0df..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc/fsl_host.h +++ /dev/null @@ -1,527 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_HOST_H -#define _FSL_HOST_H - -#include "fsl_common.h" -#include "board.h" -#if defined(FSL_FEATURE_SOC_SDHC_COUNT) && FSL_FEATURE_SOC_SDHC_COUNT > 0U -#include "fsl_sdhc.h" -#elif defined(FSL_FEATURE_SOC_SDIF_COUNT) && FSL_FEATURE_SOC_SDIF_COUNT > 0U -#include "fsl_sdif.h" -#elif defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT > 0U -#include "fsl_usdhc.h" -#include "fsl_iomuxc.h" -#endif - -/*! - * @addtogroup CARD - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define HOST_NOT_SUPPORT 0U /*!< use this define to indicate the host not support feature*/ -#define HOST_SUPPORT 1U /*!< use this define to indicate the host support feature*/ -/* select host */ -#if defined(FSL_FEATURE_SOC_SDHC_COUNT) && FSL_FEATURE_SOC_SDHC_COUNT > 0U - -/* SDR104 mode freq */ -#if defined BOARD_SD_HOST_SUPPORT_SDR104_FREQ -#define HOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ -#else -#define HOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ -#endif -/* HS200 mode freq */ -#if defined BOARD_SD_HOST_SUPPORT_HS200_FREQ -#define HOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200 -#else -#define HOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200 -#endif -/* HS400 mode freq */ -#if defined BOARD_SD_HOST_SUPPORT_HS400_FREQ -#define HOST_SUPPORT_HS400_FREQ BOARD_SD_HOST_SUPPORT_HS400_FREQ /* host do not support HS400 */ -#else -#define HOST_SUPPORT_HS400_FREQ MMC_CLOCK_HS400 -#endif - -/*define host baseaddr ,clk freq, IRQ number*/ -#define MMC_HOST_BASEADDR BOARD_SDHC_BASEADDR -#define MMC_HOST_CLK_FREQ BOARD_SDHC_CLK_FREQ -#define MMC_HOST_IRQ BOARD_SDHC_IRQ -#define SD_HOST_BASEADDR BOARD_SDHC_BASEADDR -#define SD_HOST_CLK_FREQ BOARD_SDHC_CLK_FREQ -#define SD_HOST_IRQ BOARD_SDHC_IRQ - -/* define for card bus speed/strength cnofig */ -#define CARD_BUS_FREQ_50MHZ (0U) -#define CARD_BUS_FREQ_100MHZ0 (0U) -#define CARD_BUS_FREQ_100MHZ1 (0U) -#define CARD_BUS_FREQ_200MHZ (0U) - -#define CARD_BUS_STRENGTH_0 (0U) -#define CARD_BUS_STRENGTH_1 (0U) -#define CARD_BUS_STRENGTH_2 (0U) -#define CARD_BUS_STRENGTH_3 (0U) -#define CARD_BUS_STRENGTH_4 (0U) -#define CARD_BUS_STRENGTH_5 (0U) -#define CARD_BUS_STRENGTH_6 (0U) -#define CARD_BUS_STRENGTH_7 (0U) - -#define HOST_TYPE SDHC_Type -#define HOST_CONFIG sdhc_host_t -#define HOST_TRANSFER sdhc_transfer_t -#define HOST_COMMAND sdhc_command_t -#define HOST_DATA sdhc_data_t -#define HOST_BUS_WIDTH_TYPE sdhc_data_bus_width_t -#define HOST_CAPABILITY sdhc_capability_t - -#define CARD_DATA0_STATUS_MASK kSDHC_Data0LineLevelFlag -#define CARD_DATA0_NOT_BUSY kSDHC_Data0LineLevelFlag -#define CARD_DATA1_STATUS_MASK kSDHC_Data1LineLevelFlag -#define CARD_DATA2_STATUS_MASK kSDHC_Data2LineLevelFlag -#define CARD_DATA3_STATUS_MASK kSDHC_Data3LineLevelFlag - -#define kHOST_DATABUSWIDTH1BIT kSDHC_DataBusWidth1Bit /*!< 1-bit mode */ -#define kHOST_DATABUSWIDTH4BIT kSDHC_DataBusWidth4Bit /*!< 4-bit mode */ -#define kHOST_DATABUSWIDTH8BIT kSDHC_DataBusWidth8Bit /*!< 8-bit mode */ - -#define HOST_STANDARD_TUNING_START (0U) /*!< standard tuning start point */ -#define HOST_TUINIG_STEP (1U) /*!< standard tuning step */ -#define HOST_RETUNING_TIMER_COUNT (4U) /*!< Re-tuning timer */ -#define HOST_TUNING_DELAY_MAX (0x7FU) -#define HOST_RETUNING_REQUEST (1U) - -/* function pointer define */ -#define HOST_TRANSFER_FUNCTION sdhc_transfer_function_t -#define GET_HOST_CAPABILITY(base, capability) (SDHC_GetCapability(base, capability)) -#define GET_HOST_STATUS(base) (SDHC_GetPresentStatusFlags(base)) -#define HOST_SET_CARD_CLOCK(base, sourceClock_HZ, busClock_HZ) (SDHC_SetSdClock(base, sourceClock_HZ, busClock_HZ)) -#define HOST_SET_CARD_BUS_WIDTH(base, busWidth) (SDHC_SetDataBusWidth(base, busWidth)) -#define HOST_SEND_CARD_ACTIVE(base, timeout) (SDHC_SetCardActive(base, timeout)) -#define HOST_SWITCH_VOLTAGE180V(base, enable18v) -#define HOST_CONFIG_IO_STRENGTH(speed, strength) -#define HOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag) -#define HOST_EXECUTE_STANDARD_TUNING_STATUS(base) (0U) -#define HOST_EXECUTE_STANDARD_TUNING_RESULT(base) (1U) -#define HOST_CONFIG_SD_IO(speed, strength) -#define HOST_CONFIG_MMC_IO(speed, strength) -#define HOST_ENABLE_DDR_MODE(base, flag) -#define HOST_FORCE_SDCLOCK_ON(base, enable) -#define HOST_EXECUTE_MANUAL_TUNING_ENABLE(base, flag) -#define HOST_ADJUST_MANUAL_TUNING_DELAY(base, delay) -#define HOST_AUTO_MANUAL_TUNING_ENABLE(base, flag) -#define HOST_ENABLE_CARD_CLOCK(base, enable) (SDHC_EnableSdClock(base, enable)) -#define HOST_RESET_TUNING(base, timeout) -#define HOST_EXECUTE_STANDARD_TUNING(base, transfer) (HOST_NotSupport(transfer)) -#define HOST_CHECK_TUNING_ERROR(base) (0U) -#define HOST_ADJUST_TUNING_DELAY(base, delay) -#define HOST_AUTO_STANDARD_RETUNING_TIMER(base) -#define HOST_ENABLE_HS400_MODE(base, flag) - -/*! @brief SDHC host capability*/ -enum _host_capability -{ - kHOST_SupportAdma = kSDHC_SupportAdmaFlag, - kHOST_SupportHighSpeed = kSDHC_SupportHighSpeedFlag, - kHOST_SupportDma = kSDHC_SupportDmaFlag, - kHOST_SupportSuspendResume = kSDHC_SupportSuspendResumeFlag, - kHOST_SupportV330 = kSDHC_SupportV330Flag, - kHOST_SupportV300 = HOST_NOT_SUPPORT, - kHOST_SupportV180 = HOST_NOT_SUPPORT, - kHOST_Support4BitBusWidth = kSDHC_Support4BitFlag, - kHOST_Support8BitBusWidth = kSDHC_Support8BitFlag, - kHOST_SupportDDR50 = HOST_NOT_SUPPORT, - kHOST_SupportSDR104 = HOST_NOT_SUPPORT, - kHOST_SupportSDR50 = HOST_NOT_SUPPORT, - kHOST_SupportHS200 = HOST_NOT_SUPPORT, - kHOST_SupportHS400 = HOST_NOT_SUPPORT, - -}; - -/* Endian mode. */ -#define SDHC_ENDIAN_MODE kSDHC_EndianModeLittle - -/* DMA mode */ -#define SDHC_DMA_MODE kSDHC_DmaModeAdma2 - -/* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */ -#define SDHC_READ_WATERMARK_LEVEL (0x80U) -#define SDHC_WRITE_WATERMARK_LEVEL (0x80U) - -/* ADMA table length united as word. - * - * SD card driver can't support ADMA1 transfer mode currently. - * One ADMA2 table item occupy two words which can transfer maximum 0xFFFFU bytes one time. - * The more data to be transferred in one time, the bigger value of SDHC_ADMA_TABLE_WORDS need to be set. - */ -#define SDHC_ADMA_TABLE_WORDS (8U) - -#elif defined(FSL_FEATURE_SOC_SDIF_COUNT) && FSL_FEATURE_SOC_SDIF_COUNT > 0U - -/* SDR104 mode freq */ -#if defined BOARD_SD_HOST_SUPPORT_SDR104_FREQ -#define HOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ -#else -#define HOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ -#endif -/* HS200 mode freq */ -#if defined BOARD_SD_HOST_SUPPORT_HS200_FREQ -#define HOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200 -#else -#define HOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200 -#endif -/* HS400 mode freq */ -#if defined BOARD_SD_HOST_SUPPORT_HS400_FREQ -#define HOST_SUPPORT_HS400_FREQ BOARD_SD_HOST_SUPPORT_HS400_FREQ /* host do not support HS400 */ -#else -#define HOST_SUPPORT_HS400_FREQ MMC_CLOCK_HS400 -#endif - -/*define host baseaddr ,clk freq, IRQ number*/ -#define MMC_HOST_BASEADDR BOARD_SDIF_BASEADDR -#define MMC_HOST_CLK_FREQ BOARD_SDIF_CLK_FREQ -#define MMC_HOST_IRQ BOARD_SDIF_IRQ -#define SD_HOST_BASEADDR BOARD_SDIF_BASEADDR -#define SD_HOST_CLK_FREQ BOARD_SDIF_CLK_FREQ -#define SD_HOST_IRQ BOARD_SDIF_IRQ - -/* define for card bus speed/strength cnofig */ -#define CARD_BUS_FREQ_50MHZ (0U) -#define CARD_BUS_FREQ_100MHZ0 (0U) -#define CARD_BUS_FREQ_100MHZ1 (0U) -#define CARD_BUS_FREQ_200MHZ (0U) - -#define CARD_BUS_STRENGTH_0 (0U) -#define CARD_BUS_STRENGTH_1 (0U) -#define CARD_BUS_STRENGTH_2 (0U) -#define CARD_BUS_STRENGTH_3 (0U) -#define CARD_BUS_STRENGTH_4 (0U) -#define CARD_BUS_STRENGTH_5 (0U) -#define CARD_BUS_STRENGTH_6 (0U) -#define CARD_BUS_STRENGTH_7 (0U) - -#define HOST_TYPE SDIF_Type -#define HOST_CONFIG sdif_host_t -#define HOST_TRANSFER sdif_transfer_t -#define HOST_COMMAND sdif_command_t -#define HOST_DATA sdif_data_t -#define HOST_BUS_WIDTH_TYPE sdif_bus_width_t -#define HOST_CAPABILITY sdif_capability_t - -#define CARD_DATA0_STATUS_MASK SDIF_STATUS_DATA_BUSY_MASK -#define CARD_DATA0_NOT_BUSY 0U - -#define CARD_DATA1_STATUS_MASK (0U) -#define CARD_DATA2_STATUS_MASK (0U) -#define CARD_DATA3_STATUS_MASK (0U) - -#define kHOST_DATABUSWIDTH1BIT kSDIF_Bus1BitWidth /*!< 1-bit mode */ -#define kHOST_DATABUSWIDTH4BIT kSDIF_Bus4BitWidth /*!< 4-bit mode */ -#define kHOST_DATABUSWIDTH8BIT kSDIF_Bus8BitWidth /*!< 8-bit mode */ - -#define HOST_STANDARD_TUNING_START (0U) /*!< standard tuning start point */ -#define HOST_TUINIG_STEP (1U) /*!< standard tuning step */ -#define HOST_RETUNING_TIMER_COUNT (4U) /*!< Re-tuning timer */ -#define HOST_TUNING_DELAY_MAX (0x7FU) -#define HOST_RETUNING_REQUEST (1U) -/* function pointer define */ -#define HOST_TRANSFER_FUNCTION sdif_transfer_function_t -#define GET_HOST_CAPABILITY(base, capability) (SDIF_GetCapability(base, capability)) -#define GET_HOST_STATUS(base) (SDIF_GetControllerStatus(base)) -#define HOST_SET_CARD_CLOCK(base, sourceClock_HZ, busClock_HZ) (SDIF_SetCardClock(base, sourceClock_HZ, busClock_HZ)) -#define HOST_SET_CARD_BUS_WIDTH(base, busWidth) (SDIF_SetCardBusWidth(base, busWidth)) -#define HOST_SEND_CARD_ACTIVE(base, timeout) (SDIF_SendCardActive(base, timeout)) -#define HOST_SWITCH_VOLTAGE180V(base, enable18v) -#define HOST_CONFIG_IO_STRENGTH(speed, strength) -#define HOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag) -#define HOST_EXECUTE_STANDARD_TUNING_STATUS(base) (0U) -#define HOST_EXECUTE_STANDARD_TUNING_RESULT(base) (1U) -#define HOST_CONFIG_SD_IO(speed, strength) -#define HOST_CONFIG_MMC_IO(speed, strength) -#define HOST_ENABLE_DDR_MODE(base, flag) -#define HOST_FORCE_SDCLOCK_ON(base, enable) -#define HOST_EXECUTE_MANUAL_TUNING_ENABLE(base, flag) -#define HOST_ADJUST_MANUAL_TUNING_DELAY(base, delay) -#define HOST_AUTO_MANUAL_TUNING_ENABLE(base, flag) -#define HOST_ENABLE_CARD_CLOCK(base, enable) (SDIF_EnableCardClock(base, enable)) -#define HOST_RESET_TUNING(base, timeout) -#define HOST_EXECUTE_STANDARD_TUNING(base, transfer) (HOST_NotSupport(transfer)) -#define HOST_CHECK_TUNING_ERROR(base) (0U) -#define HOST_ADJUST_TUNING_DELAY(base, delay) -#define HOST_AUTO_STANDARD_RETUNING_TIMER(base) -#define HOST_ENABLE_HS400_MODE(base, flag) -/*! @brief SDIF host capability*/ -enum _host_capability -{ - kHOST_SupportHighSpeed = kSDIF_SupportHighSpeedFlag, - kHOST_SupportDma = kSDIF_SupportDmaFlag, - kHOST_SupportSuspendResume = kSDIF_SupportSuspendResumeFlag, - kHOST_SupportV330 = kSDIF_SupportV330Flag, - kHOST_SupportV300 = HOST_NOT_SUPPORT, - kHOST_SupportV180 = HOST_NOT_SUPPORT, - kHOST_Support4BitBusWidth = kSDIF_Support4BitFlag, - kHOST_Support8BitBusWidth = HOST_NOT_SUPPORT, /* mask the 8 bit here,user can change depend on your board */ - kHOST_SupportDDR50 = HOST_NOT_SUPPORT, - kHOST_SupportSDR104 = HOST_NOT_SUPPORT, - kHOST_SupportSDR50 = HOST_NOT_SUPPORT, - kHOST_SupportHS200 = HOST_NOT_SUPPORT, - kHOST_SupportHS400 = HOST_NOT_SUPPORT, - -}; - -/*! @brief DMA table length united as word - * One dma table item occupy four words which can transfer maximum 2*8188 bytes in dual DMA mode - * and 8188 bytes in chain mode - * The more data to be transferred in one time, the bigger value of SDHC_ADMA_TABLE_WORDS need to be set. - * user need check the DMA descriptor table lenght if bigger enough. - */ -#define SDIF_DMA_TABLE_WORDS (0x40U) - -#elif defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT > 0U -/* SDR104 mode freq */ -#if defined BOARD_SD_HOST_SUPPORT_SDR104_FREQ -#define HOST_SUPPORT_SDR104_FREQ BOARD_SD_HOST_SUPPORT_SDR104_FREQ -#else -#define HOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ -#endif -/* HS200 mode freq */ -#if defined BOARD_SD_HOST_SUPPORT_HS200_FREQ -#define HOST_SUPPORT_HS200_FREQ BOARD_SD_HOST_SUPPORT_HS200_FREQ -#else -#define HOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200 -#endif -/* HS400 mode freq */ -#if defined BOARD_SD_HOST_SUPPORT_HS400_FREQ -#define HOST_SUPPORT_HS400_FREQ BOARD_SD_HOST_SUPPORT_HS400_FREQ -#else -#define HOST_SUPPORT_HS400_FREQ MMC_CLOCK_HS400 -#endif - -/*define host baseaddr ,clk freq, IRQ number*/ -#define MMC_HOST_BASEADDR BOARD_MMC_HOST_BASEADDR -#define MMC_HOST_CLK_FREQ BOARD_MMC_HOST_CLK_FREQ -#define MMC_HOST_IRQ BOARD_MMC_HOST_IRQ -#define SD_HOST_BASEADDR BOARD_SD_HOST_BASEADDR -#define SD_HOST_CLK_FREQ BOARD_SD_HOST_CLK_FREQ -#define SD_HOST_IRQ BOARD_SD_HOST_IRQ - -#define HOST_TYPE USDHC_Type -#define HOST_CONFIG usdhc_host_t -#define HOST_TRANSFER usdhc_transfer_t -#define HOST_COMMAND usdhc_command_t -#define HOST_DATA usdhc_data_t - -#define CARD_DATA0_STATUS_MASK kUSDHC_Data0LineLevelFlag -#define CARD_DATA1_STATUS_MASK kUSDHC_Data1LineLevelFlag -#define CARD_DATA2_STATUS_MASK kUSDHC_Data2LineLevelFlag -#define CARD_DATA3_STATUS_MASK kUSDHC_Data3LineLevelFlag -#define CARD_DATA0_NOT_BUSY kUSDHC_Data0LineLevelFlag - -#define HOST_BUS_WIDTH_TYPE usdhc_data_bus_width_t -#define HOST_CAPABILITY usdhc_capability_t - -#define kHOST_DATABUSWIDTH1BIT kUSDHC_DataBusWidth1Bit /*!< 1-bit mode */ -#define kHOST_DATABUSWIDTH4BIT kUSDHC_DataBusWidth4Bit /*!< 4-bit mode */ -#define kHOST_DATABUSWIDTH8BIT kUSDHC_DataBusWidth8Bit /*!< 8-bit mode */ - -#define HOST_STANDARD_TUNING_START (10U) /*!< standard tuning start point */ -#define HOST_TUINIG_STEP (2U) /*!< standard tuning step */ -#define HOST_RETUNING_TIMER_COUNT (0U) /*!< Re-tuning timer */ -#define HOST_TUNING_DELAY_MAX (0x7FU) -#define HOST_RETUNING_REQUEST kStatus_USDHC_ReTuningRequest - -/* define for card bus speed/strength cnofig */ -#define CARD_BUS_FREQ_50MHZ (0U) -#define CARD_BUS_FREQ_100MHZ0 (1U) -#define CARD_BUS_FREQ_100MHZ1 (2U) -#define CARD_BUS_FREQ_200MHZ (3U) - -#define CARD_BUS_STRENGTH_0 (0U) -#define CARD_BUS_STRENGTH_1 (1U) -#define CARD_BUS_STRENGTH_2 (2U) -#define CARD_BUS_STRENGTH_3 (3U) -#define CARD_BUS_STRENGTH_4 (4U) -#define CARD_BUS_STRENGTH_5 (5U) -#define CARD_BUS_STRENGTH_6 (6U) -#define CARD_BUS_STRENGTH_7 (7U) - -/* function pointer define */ -#define HOST_TRANSFER_FUNCTION usdhc_transfer_function_t -#define GET_HOST_CAPABILITY(base, capability) (USDHC_GetCapability(base, capability)) -#define GET_HOST_STATUS(base) (USDHC_GetPresentStatusFlags(base)) -#define HOST_SET_CARD_CLOCK(base, sourceClock_HZ, busClock_HZ) (USDHC_SetSdClock(base, sourceClock_HZ, busClock_HZ)) -#define HOST_ENABLE_CARD_CLOCK(base, enable) (USDHC_EnableSdClock(base, enable)) -#define HOST_FORCE_SDCLOCK_ON(base, enable) (USDHC_ForceClockOn(base, enable)) -#define HOST_SET_CARD_BUS_WIDTH(base, busWidth) (USDHC_SetDataBusWidth(base, busWidth)) -#define HOST_SEND_CARD_ACTIVE(base, timeout) (USDHC_SetCardActive(base, timeout)) -#define HOST_SWITCH_VOLTAGE180V(base, enable18v) (UDSHC_SelectVoltage(base, enable18v)) -#define HOST_CONFIG_SD_IO(speed, strength) BOARD_SD_PIN_CONFIG(speed, strength) -#define HOST_CONFIG_MMC_IO(speed, strength) BOARD_MMC_PIN_CONFIG(speed, strength) - -#define HOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag) \ - (USDHC_EnableStandardTuning(base, HOST_STANDARD_TUNING_START, HOST_TUINIG_STEP, flag)) -#define HOST_EXECUTE_STANDARD_TUNING_STATUS(base) (USDHC_GetExecuteStdTuningStatus(base)) -#define HOST_EXECUTE_STANDARD_TUNING_RESULT(base) (USDHC_CheckStdTuningResult(base)) -#define HOST_AUTO_STANDARD_RETUNING_TIMER(base) (USDHC_SetRetuningTimer(base, HOST_RETUNING_TIMER_COUNT)) -#define HOST_AUTO_TUNING_CONFIG(base) (USDHC_EnableAutoTuningForCmdAndData(base)) -#define HOST_EXECUTE_MANUAL_TUNING_ENABLE(base, flag) (USDHC_EnableManualTuning(base, flag)) - -#define HOST_ADJUST_TUNING_DELAY(base, delay) (USDHC_AdjustDelayForManualTuning(base, delay)) -#define HOST_AUTO_MANUAL_TUNING_ENABLE(base, flag) (USDHC_EnableAutoTuningForManualTuning(base, flag)) -#define HOST_RESET_TUNING(base, timeout) \ - { \ - HOST_EXECUTE_MANUAL_TUNING_ENABLE(base, false); \ - (USDHC_Reset(base, kUSDHC_ResetTuning | kUSDHC_ResetData | kUSDHC_ResetCommand, timeout)); \ - } - -#define HOST_ENABLE_DDR_MODE(base, flag) (USDHC_EnableDDRMode(base, flag, 1U)) - -#if FSL_FEATURE_USDHC_HAS_HS400_MODE -#define HOST_ENABLE_HS400_MODE(base, flag) (USDHC_EnableHS400Mode(base, flag)) -#else -#define HOST_ENABLE_HS400_MODE(base, flag) -#endif - -#define HOST_EXECUTE_STANDARD_TUNING(base, transfer) (USDHC_ExecuteStdTuning(base, transfer)) -#define HOST_CHECK_TUNING_ERROR(base) (USDHC_CheckTuningError(base)) -/*! @brief USDHC host capability*/ -enum _host_capability -{ - kHOST_SupportAdma = kUSDHC_SupportAdmaFlag, - kHOST_SupportHighSpeed = kUSDHC_SupportHighSpeedFlag, - kHOST_SupportDma = kUSDHC_SupportDmaFlag, - kHOST_SupportSuspendResume = kUSDHC_SupportSuspendResumeFlag, - kHOST_SupportV330 = kUSDHC_SupportV330Flag, - kHOST_SupportV300 = kUSDHC_SupportV300Flag, - kHOST_SupportV180 = kUSDHC_SupportV180Flag, - kHOST_Support4BitBusWidth = kUSDHC_Support4BitFlag, - kHOST_Support8BitBusWidth = kUSDHC_Support8BitFlag, - kHOST_SupportDDR50 = kUSDHC_SupportDDR50Flag, - kHOST_SupportSDR104 = kUSDHC_SupportSDR104Flag, - kHOST_SupportSDR50 = kUSDHC_SupportSDR50Flag, - kHOST_SupportHS200 = kUSDHC_SupportSDR104Flag, -#if FSL_FEATURE_USDHC_HAS_HS400_MODE - kHOST_SupportHS400 = HOST_SUPPORT -#else - kHOST_SupportHS400 = HOST_NOT_SUPPORT, -#endif -}; - -/* Endian mode. */ -#define USDHC_ENDIAN_MODE kUSDHC_EndianModeLittle - -/* DMA mode */ -#define USDHC_DMA_MODE kUSDHC_DmaModeAdma2 - -/* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */ -#define USDHC_READ_WATERMARK_LEVEL (0x80U) -#define USDHC_WRITE_WATERMARK_LEVEL (0x80U) - -/* ADMA table length united as word. - * - * One ADMA2 table item occupy two words which can transfer maximum 0xFFFFU bytes one time. - * The more data to be transferred in one time, the bigger value of SDHC_ADMA_TABLE_WORDS need to be set. - */ -#define USDHC_ADMA_TABLE_WORDS (8U) - -#define USDHC_READ_BURST_LEN (8U) /*!< number of words USDHC read in a single burst */ -#define USDHC_WRITE_BURST_LEN (8U) /*!< number of words USDHC write in a single burst */ -#define USDHC_DATA_TIMEOUT (0xFU) /*!< data timeout counter value */ - -#endif - -/*! @brief host Endian mode -* corresponding to driver define -*/ -enum _host_endian_mode -{ - kHOST_EndianModeBig = 0U, /*!< Big endian mode */ - kHOST_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */ - kHOST_EndianModeLittle = 2U, /*!< Little endian mode */ -}; - -#define EVENT_TIMEOUT_TRANSFER_COMPLETE (1000U) -#define EVENT_TIMEOUT_CARD_DETECT (~0U) - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name adaptor function - * @{ - */ - -/*! - * @brief host not support function, this function is used for host not support feature - * @param void parameter ,used to avoid build warning - * @retval kStatus_Fail ,host do not suppport - */ -static inline status_t HOST_NotSupport(void *parameter) -{ - parameter = parameter; - return kStatus_Success; -} - -/*! - * @brief Detect card insert, only need for SD cases. - * @param hostBase the pointer to host base address - * @retval kStatus_Success detect card insert - * @retval kStatus_Fail card insert event fail - */ -status_t CardInsertDetect(HOST_TYPE *hostBase); - -/*! - * @brief Init host controller. - * @param host the pointer to host structure in card structure. - * @retval kStatus_Success host init success - * @retval kStatus_Fail event fail - */ -status_t HOST_Init(void *host); - -/*! - * @brief Deinit host controller. - * @param host the pointer to host structure in card structure. - */ -void HOST_Deinit(void *host); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -#endif diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc/fsl_sd_event.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc/fsl_sd_event.h deleted file mode 100644 index e4d2c8d12d6..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc/fsl_sd_event.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_SD_EVENT_H_ -#define _FSL_SD_EVENT_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief Event type */ -typedef enum _event -{ - kEVENT_TransferComplete = 0U, /*!< Transfer complete event */ - kEVENT_CardDetect = 1U, /*!< Card detect event */ -} event_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Event Function - * @{ - */ - -/*! - * @brief Initialize timer to implement wait event timeout. - */ -void EVENT_InitTimer(void); - -/* Callback function for SDHC */ - -/*! - * @brief Create event. - * @param eventType The event type - * @retval true Create event successfully. - * @retval false Create event failed. - */ -bool EVENT_Create(event_t eventType); - -/*! - * @brief Wait event. - * - * @param eventType The event type - * @param timeoutMilliseconds Timeout time in milliseconds. - * @retval true Wait event successfully. - * @retval false Wait event failed. - */ -bool EVENT_Wait(event_t eventType, uint32_t timeoutMilliseconds); - -/*! - * @brief Notify event. - * @param eventType The event type - * @retval true Notify event successfully. - * @retval false Notify event failed. - */ -bool EVENT_Notify(event_t eventType); - -/*! - * @brief Delete event. - * @param eventType The event type - */ -void EVENT_Delete(event_t eventType); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_SD_EVENT_H_*/ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc/fsl_sdmmc.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc/fsl_sdmmc.h deleted file mode 100644 index 13e516a7342..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc/fsl_sdmmc.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_SDMMC_H_ -#define _FSL_SDMMC_H_ - -#include "fsl_card.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief Reverse byte sequence in uint32_t */ -#define SWAP_WORD_BYTE_SEQUENCE(x) (__REV(x)) -/*! @brief Reverse byte sequence for each half word in uint32_t */ -#define SWAP_HALF_WROD_BYTE_SEQUENCE(x) (__REV16(x)) - -/*! @brief Maximum loop count to check the card operation voltage range */ -#define FSL_SDMMC_MAX_VOLTAGE_RETRIES (1000U) -/*! @brief Maximum loop count to send the cmd */ -#define FSL_SDMMC_MAX_CMD_RETRIES (10U) -/************************************************************************************************* - * API - ************************************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Selects the card to put it into transfer state. - * - * @param base HOST peripheral base address. - * @param transfer HOST transfer function. - * @param relativeAddress Relative address. - * @param isSelected True to put card into transfer state. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -status_t SDMMC_SelectCard(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t relativeAddress, bool isSelected); - -/*! - * @brief Sends an application command. - * - * @param base HOST peripheral base address. - * @param transfer HOST transfer function. - * @param relativeAddress Card relative address. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. - * @retval kStatus_Success Operate successfully. - */ -status_t SDMMC_SendApplicationCommand(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t relativeAddress); - -/*! - * @brief Sets the block count. - * - * @param base HOST peripheral base address. - * @param transfer HOST transfer function. - * @param blockCount Block count. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -status_t SDMMC_SetBlockCount(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t blockCount); - -/*! - * @brief Sets the card to be idle state. - * - * @param base HOST peripheral base address. - * @param transfer HOST transfer function. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -status_t SDMMC_GoIdle(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer); - -/*! - * @brief Sets data block size. - * - * @param base HOST peripheral base address. - * @param transfer HOST transfer function. - * @param blockSize Block size. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -status_t SDMMC_SetBlockSize(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t blockSize); - -/*! - * @brief Sets card to inactive status - * - * @param base HOST peripheral base address. - * @param transfer HOST transfer function. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -status_t SDMMC_SetCardInactive(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer); - -/*! - * @brief provide a simple delay function for sdmmc - * - * @param delay num*10000. - */ -void SDMMC_Delay(uint32_t num); - -/*! - * @brief provide a voltage switch function for SD/SDIO card - * - * @param base HOST peripheral base address. - * @param transfer HOST transfer function. - */ -status_t SDMMC_SwitchVoltage(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer); - -/*! - * @brief excute tuning - * - * @param base HOST peripheral base address. - * @param tuning cmd - * @param tuning block size - */ -status_t SDMMC_ExecuteTuning(HOST_TYPE *base, uint32_t tuningCmd, uint32_t blockSize); - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_SDMMC_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc/fsl_sdspi.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc/fsl_sdspi.h deleted file mode 100644 index ee5c8a71f72..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc/fsl_sdspi.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_SDSPI_H_ -#define _FSL_SDSPI_H_ - -#include "fsl_common.h" -#include "fsl_specification.h" - -/****************************************************************************** - * Definitions - *****************************************************************************/ -/*! @brief Driver version. */ -#define FSL_SDSPI_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 1U)) /*2.1.1*/ - -/*! @brief Default block size */ -#define FSL_SDSPI_DEFAULT_BLOCK_SIZE (512U) - -/*! - * @addtogroup SDSPI - * @{ - */ - -/*! @brief SDSPI API status */ -enum _sdspi_status -{ - kStatus_SDSPI_SetFrequencyFailed = MAKE_STATUS(kStatusGroup_SDSPI, 0U), /*!< Set frequency failed */ - kStatus_SDSPI_ExchangeFailed = MAKE_STATUS(kStatusGroup_SDSPI, 1U), /*!< Exchange data on SPI bus failed */ - kStatus_SDSPI_WaitReadyFailed = MAKE_STATUS(kStatusGroup_SDSPI, 2U), /*!< Wait card ready failed */ - kStatus_SDSPI_ResponseError = MAKE_STATUS(kStatusGroup_SDSPI, 3U), /*!< Response is error */ - kStatus_SDSPI_WriteProtected = MAKE_STATUS(kStatusGroup_SDSPI, 4U), /*!< Write protected */ - kStatus_SDSPI_GoIdleFailed = MAKE_STATUS(kStatusGroup_SDSPI, 5U), /*!< Go idle failed */ - kStatus_SDSPI_SendCommandFailed = MAKE_STATUS(kStatusGroup_SDSPI, 6U), /*!< Send command failed */ - kStatus_SDSPI_ReadFailed = MAKE_STATUS(kStatusGroup_SDSPI, 7U), /*!< Read data failed */ - kStatus_SDSPI_WriteFailed = MAKE_STATUS(kStatusGroup_SDSPI, 8U), /*!< Write data failed */ - kStatus_SDSPI_SendInterfaceConditionFailed = - MAKE_STATUS(kStatusGroup_SDSPI, 9U), /*!< Send interface condition failed */ - kStatus_SDSPI_SendOperationConditionFailed = - MAKE_STATUS(kStatusGroup_SDSPI, 10U), /*!< Send operation condition failed */ - kStatus_SDSPI_ReadOcrFailed = MAKE_STATUS(kStatusGroup_SDSPI, 11U), /*!< Read OCR failed */ - kStatus_SDSPI_SetBlockSizeFailed = MAKE_STATUS(kStatusGroup_SDSPI, 12U), /*!< Set block size failed */ - kStatus_SDSPI_SendCsdFailed = MAKE_STATUS(kStatusGroup_SDSPI, 13U), /*!< Send CSD failed */ - kStatus_SDSPI_SendCidFailed = MAKE_STATUS(kStatusGroup_SDSPI, 14U), /*!< Send CID failed */ - kStatus_SDSPI_StopTransmissionFailed = MAKE_STATUS(kStatusGroup_SDSPI, 15U), /*!< Stop transmission failed */ - kStatus_SDSPI_SendApplicationCommandFailed = - MAKE_STATUS(kStatusGroup_SDSPI, 16U), /*!< Send application command failed */ -}; - -/*! @brief SDSPI card flag */ -enum _sdspi_card_flag -{ - kSDSPI_SupportHighCapacityFlag = (1U << 0U), /*!< Card is high capacity */ - kSDSPI_SupportSdhcFlag = (1U << 1U), /*!< Card is SDHC */ - kSDSPI_SupportSdxcFlag = (1U << 2U), /*!< Card is SDXC */ - kSDSPI_SupportSdscFlag = (1U << 3U), /*!< Card is SDSC */ -}; - -/*! @brief SDSPI response type */ -typedef enum _sdspi_response_type -{ - kSDSPI_ResponseTypeR1 = 0U, /*!< Response 1 */ - kSDSPI_ResponseTypeR1b = 1U, /*!< Response 1 with busy */ - kSDSPI_ResponseTypeR2 = 2U, /*!< Response 2 */ - kSDSPI_ResponseTypeR3 = 3U, /*!< Response 3 */ - kSDSPI_ResponseTypeR7 = 4U, /*!< Response 7 */ -} sdspi_response_type_t; - -/*! @brief SDSPI command */ -typedef struct _sdspi_command -{ - uint8_t index; /*!< Command index */ - uint32_t argument; /*!< Command argument */ - uint8_t responseType; /*!< Response type */ - uint8_t response[5U]; /*!< Response content */ -} sdspi_command_t; - -/*! @brief SDSPI host state. */ -typedef struct _sdspi_host -{ - uint32_t busBaudRate; /*!< Bus baud rate */ - - status_t (*setFrequency)(uint32_t frequency); /*!< Set frequency of SPI */ - status_t (*exchange)(uint8_t *in, uint8_t *out, uint32_t size); /*!< Exchange data over SPI */ - uint32_t (*getCurrentMilliseconds)(void); /*!< Get current time in milliseconds */ -} sdspi_host_t; - -/*! - * @brief SD Card Structure - * - * Define the card structure including the necessary fields to identify and describe the card. - */ -typedef struct _sdspi_card -{ - sdspi_host_t *host; /*!< Host state information */ - uint32_t relativeAddress; /*!< Relative address of the card */ - uint32_t flags; /*!< Flags defined in _sdspi_card_flag. */ - uint8_t rawCid[16U]; /*!< Raw CID content */ - uint8_t rawCsd[16U]; /*!< Raw CSD content */ - uint8_t rawScr[8U]; /*!< Raw SCR content */ - uint32_t ocr; /*!< Raw OCR content */ - sd_cid_t cid; /*!< CID */ - sd_csd_t csd; /*!< CSD */ - sd_scr_t scr; /*!< SCR */ - uint32_t blockCount; /*!< Card total block number */ - uint32_t blockSize; /*!< Card block size */ -} sdspi_card_t; - -/************************************************************************************************* - * API - ************************************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name SDSPI Function - * @{ - */ - -/*! - * @brief Initializes the card on a specific SPI instance. - * - * This function initializes the card on a specific SPI instance. - * - * @param card Card descriptor - * @retval kStatus_SDSPI_SetFrequencyFailed Set frequency failed. - * @retval kStatus_SDSPI_GoIdleFailed Go idle failed. - * @retval kStatus_SDSPI_SendInterfaceConditionFailed Send interface condition failed. - * @retval kStatus_SDSPI_SendOperationConditionFailed Send operation condition failed. - * @retval kStatus_Timeout Send command timeout. - * @retval kStatus_SDSPI_NotSupportYet Not support yet. - * @retval kStatus_SDSPI_ReadOcrFailed Read OCR failed. - * @retval kStatus_SDSPI_SetBlockSizeFailed Set block size failed. - * @retval kStatus_SDSPI_SendCsdFailed Send CSD failed. - * @retval kStatus_SDSPI_SendCidFailed Send CID failed. - * @retval kStatus_Success Operate successfully. - */ -status_t SDSPI_Init(sdspi_card_t *card); - -/*! - * @brief Deinitializes the card. - * - * This function deinitializes the specific card. - * - * @param card Card descriptor - */ -void SDSPI_Deinit(sdspi_card_t *card); - -/*! - * @brief Checks whether the card is write-protected. - * - * This function checks if the card is write-protected via CSD register. - * - * @param card Card descriptor. - * @retval true Card is read only. - * @retval false Card isn't read only. - */ -bool SDSPI_CheckReadOnly(sdspi_card_t *card); - -/*! - * @brief Reads blocks from the specific card. - * - * This function reads blocks from specific card. - * - * @param card Card descriptor. - * @param buffer the buffer to hold the data read from card - * @param startBlock the start block index - * @param blockCount the number of blocks to read - * @retval kStatus_SDSPI_SendCommandFailed Send command failed. - * @retval kStatus_SDSPI_ReadFailed Read data failed. - * @retval kStatus_SDSPI_StopTransmissionFailed Stop transmission failed. - * @retval kStatus_Success Operate successfully. - */ -status_t SDSPI_ReadBlocks(sdspi_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); - -/*! - * @brief Writes blocks of data to the specific card. - * - * This function writes blocks to specific card - * - * @param card Card descriptor. - * @param buffer the buffer holding the data to be written to the card - * @param startBlock the start block index - * @param blockCount the number of blocks to write - * @retval kStatus_SDSPI_WriteProtected Card is write protected. - * @retval kStatus_SDSPI_SendCommandFailed Send command failed. - * @retval kStatus_SDSPI_ResponseError Response is error. - * @retval kStatus_SDSPI_WriteFailed Write data failed. - * @retval kStatus_SDSPI_ExchangeFailed Exchange data over SPI failed. - * @retval kStatus_SDSPI_WaitReadyFailed Wait card to be ready status failed. - * @retval kStatus_Success Operate successfully. - */ -status_t SDSPI_WriteBlocks(sdspi_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); - -/* @} */ -#if defined(__cplusplus) -} -#endif -/*! @} */ -#endif /* _FSL_SDSPI_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc/fsl_specification.h b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc/fsl_specification.h deleted file mode 100644 index 5410f82559d..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc/fsl_specification.h +++ /dev/null @@ -1,1081 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_SPECIFICATION_H_ -#define _FSL_SPECIFICATION_H_ - -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief SD/MMC card initialization clock frequency */ -#define SDMMC_CLOCK_400KHZ (400000U) -/*! @brief SD card bus frequency 1 in high-speed mode */ -#define SD_CLOCK_25MHZ (25000000U) -/*! @brief SD card bus frequency 2 in high-speed mode */ -#define SD_CLOCK_50MHZ (50000000U) -/*! @brief SD card bus frequency in SDR50 mode */ -#define SD_CLOCK_100MHZ (100000000U) -/*! @brief SD card bus frequency in SDR104 mode */ -#define SD_CLOCK_208MHZ (208000000U) -/*! @brief MMC card bus frequency 1 in high-speed mode */ -#define MMC_CLOCK_26MHZ (26000000U) -/*! @brief MMC card bus frequency 2 in high-speed mode */ -#define MMC_CLOCK_52MHZ (52000000U) -/*! @brief MMC card bus frequency in high-speed DDR52 mode */ -#define MMC_CLOCK_DDR52 (104000000U) -/*! @brief MMC card bus frequency in high-speed HS200 mode */ -#define MMC_CLOCK_HS200 (200000000U) -/*! @brief MMC card bus frequency in high-speed HS400 mode */ -#define MMC_CLOCK_HS400 (400000000U) - -/*! @brief Card status bit in R1 */ -enum _sdmmc_r1_card_status_flag -{ - kSDMMC_R1OutOfRangeFlag = (1U << 31U), /*!< Out of range status bit */ - kSDMMC_R1AddressErrorFlag = (1U << 30U), /*!< Address error status bit */ - kSDMMC_R1BlockLengthErrorFlag = (1U << 29U), /*!< Block length error status bit */ - kSDMMC_R1EraseSequenceErrorFlag = (1U << 28U), /*!< Erase sequence error status bit */ - kSDMMC_R1EraseParameterErrorFlag = (1U << 27U), /*!< Erase parameter error status bit */ - kSDMMC_R1WriteProtectViolationFlag = (1U << 26U), /*!< Write protection violation status bit */ - kSDMMC_R1CardIsLockedFlag = (1U << 25U), /*!< Card locked status bit */ - kSDMMC_R1LockUnlockFailedFlag = (1U << 24U), /*!< lock/unlock error status bit */ - kSDMMC_R1CommandCrcErrorFlag = (1U << 23U), /*!< CRC error status bit */ - kSDMMC_R1IllegalCommandFlag = (1U << 22U), /*!< Illegal command status bit */ - kSDMMC_R1CardEccFailedFlag = (1U << 21U), /*!< Card ecc error status bit */ - kSDMMC_R1CardControllerErrorFlag = (1U << 20U), /*!< Internal card controller error status bit */ - kSDMMC_R1ErrorFlag = (1U << 19U), /*!< A general or an unknown error status bit */ - kSDMMC_R1CidCsdOverwriteFlag = (1U << 16U), /*!< Cid/csd overwrite status bit */ - kSDMMC_R1WriteProtectEraseSkipFlag = (1U << 15U), /*!< Write protection erase skip status bit */ - kSDMMC_R1CardEccDisabledFlag = (1U << 14U), /*!< Card ecc disabled status bit */ - kSDMMC_R1EraseResetFlag = (1U << 13U), /*!< Erase reset status bit */ - kSDMMC_R1ReadyForDataFlag = (1U << 8U), /*!< Ready for data status bit */ - kSDMMC_R1SwitchErrorFlag = (1U << 7U), /*!< Switch error status bit */ - kSDMMC_R1ApplicationCommandFlag = (1U << 5U), /*!< Application command enabled status bit */ - kSDMMC_R1AuthenticationSequenceErrorFlag = (1U << 3U), /*!< error in the sequence of authentication process */ - - kSDMMC_R1ErrorAllFlag = - (kSDMMC_R1OutOfRangeFlag | kSDMMC_R1AddressErrorFlag | kSDMMC_R1BlockLengthErrorFlag | - kSDMMC_R1EraseSequenceErrorFlag | kSDMMC_R1EraseParameterErrorFlag | kSDMMC_R1WriteProtectViolationFlag | - kSDMMC_R1CardIsLockedFlag | kSDMMC_R1LockUnlockFailedFlag | kSDMMC_R1CommandCrcErrorFlag | - kSDMMC_R1IllegalCommandFlag | kSDMMC_R1CardEccFailedFlag | kSDMMC_R1CardControllerErrorFlag | - kSDMMC_R1ErrorFlag | kSDMMC_R1CidCsdOverwriteFlag | - kSDMMC_R1AuthenticationSequenceErrorFlag), /*!< Card error status */ -}; - -/*! @brief R1: current state */ -#define SDMMC_R1_CURRENT_STATE(x) (((x)&0x00001E00U) >> 9U) - -/*! @brief CURRENT_STATE filed in R1 */ -typedef enum _sdmmc_r1_current_state -{ - kSDMMC_R1StateIdle = 0U, /*!< R1: current state: idle */ - kSDMMC_R1StateReady = 1U, /*!< R1: current state: ready */ - kSDMMC_R1StateIdentify = 2U, /*!< R1: current state: identification */ - kSDMMC_R1StateStandby = 3U, /*!< R1: current state: standby */ - kSDMMC_R1StateTransfer = 4U, /*!< R1: current state: transfer */ - kSDMMC_R1StateSendData = 5U, /*!< R1: current state: sending data */ - kSDMMC_R1StateReceiveData = 6U, /*!< R1: current state: receiving data */ - kSDMMC_R1StateProgram = 7U, /*!< R1: current state: programming */ - kSDMMC_R1StateDisconnect = 8U, /*!< R1: current state: disconnect */ -} sdmmc_r1_current_state_t; - -/*! @brief Error bit in SPI mode R1 */ -enum _sdspi_r1_error_status_flag -{ - kSDSPI_R1InIdleStateFlag = (1U << 0U), /*!< In idle state */ - kSDSPI_R1EraseResetFlag = (1U << 1U), /*!< Erase reset */ - kSDSPI_R1IllegalCommandFlag = (1U << 2U), /*!< Illegal command */ - kSDSPI_R1CommandCrcErrorFlag = (1U << 3U), /*!< Com crc error */ - kSDSPI_R1EraseSequenceErrorFlag = (1U << 4U), /*!< Erase sequence error */ - kSDSPI_R1AddressErrorFlag = (1U << 5U), /*!< Address error */ - kSDSPI_R1ParameterErrorFlag = (1U << 6U), /*!< Parameter error */ -}; - -/*! @brief Error bit in SPI mode R2 */ -enum _sdspi_r2_error_status_flag -{ - kSDSPI_R2CardLockedFlag = (1U << 0U), /*!< Card is locked */ - kSDSPI_R2WriteProtectEraseSkip = (1U << 1U), /*!< Write protect erase skip */ - kSDSPI_R2LockUnlockFailed = (1U << 1U), /*!< Lock/unlock command failed */ - kSDSPI_R2ErrorFlag = (1U << 2U), /*!< Unknown error */ - kSDSPI_R2CardControllerErrorFlag = (1U << 3U), /*!< Card controller error */ - kSDSPI_R2CardEccFailedFlag = (1U << 4U), /*!< Card ecc failed */ - kSDSPI_R2WriteProtectViolationFlag = (1U << 5U), /*!< Write protect violation */ - kSDSPI_R2EraseParameterErrorFlag = (1U << 6U), /*!< Erase parameter error */ - kSDSPI_R2OutOfRangeFlag = (1U << 7U), /*!< Out of range */ - kSDSPI_R2CsdOverwriteFlag = (1U << 7U), /*!< CSD overwrite */ -}; - -/*! @brief The bit mask for COMMAND VERSION field in R7 */ -#define SDSPI_R7_VERSION_SHIFT (28U) -/*! @brief The bit mask for COMMAND VERSION field in R7 */ -#define SDSPI_R7_VERSION_MASK (0xFU) -/*! @brief The bit shift for VOLTAGE ACCEPTED field in R7 */ -#define SDSPI_R7_VOLTAGE_SHIFT (8U) -/*! @brief The bit mask for VOLTAGE ACCEPTED field in R7 */ -#define SDSPI_R7_VOLTAGE_MASK (0xFU) -/*! @brief The bit mask for VOLTAGE 2.7V to 3.6V field in R7 */ -#define SDSPI_R7_VOLTAGE_27_36_MASK (0x1U << SDSPI_R7_VOLTAGE_SHIFT) -/*! @brief The bit shift for ECHO field in R7 */ -#define SDSPI_R7_ECHO_SHIFT (0U) -/*! @brief The bit mask for ECHO field in R7 */ -#define SDSPI_R7_ECHO_MASK (0xFFU) - -/*! @brief Data error token mask */ -#define SDSPI_DATA_ERROR_TOKEN_MASK (0xFU) -/*! @brief Data Error Token mask bit */ -enum _sdspi_data_error_token -{ - kSDSPI_DataErrorTokenError = (1U << 0U), /*!< Data error */ - kSDSPI_DataErrorTokenCardControllerError = (1U << 1U), /*!< Card controller error */ - kSDSPI_DataErrorTokenCardEccFailed = (1U << 2U), /*!< Card ecc error */ - kSDSPI_DataErrorTokenOutOfRange = (1U << 3U), /*!< Out of range */ -}; - -/*! @brief Data Token */ -typedef enum _sdspi_data_token -{ - kSDSPI_DataTokenBlockRead = 0xFEU, /*!< Single block read, multiple block read */ - kSDSPI_DataTokenSingleBlockWrite = 0xFEU, /*!< Single block write */ - kSDSPI_DataTokenMultipleBlockWrite = 0xFCU, /*!< Multiple block write */ - kSDSPI_DataTokenStopTransfer = 0xFDU, /*!< Stop transmission */ -} sdspi_data_token_t; - -/* Data Response Token mask */ -#define SDSPI_DATA_RESPONSE_TOKEN_MASK (0x1FU) /*!< Mask for data response bits */ -/*! @brief Data Response Token */ -typedef enum _sdspi_data_response_token -{ - kSDSPI_DataResponseTokenAccepted = 0x05U, /*!< Data accepted */ - kSDSPI_DataResponseTokenCrcError = 0x0BU, /*!< Data rejected due to CRC error */ - kSDSPI_DataResponseTokenWriteError = 0x0DU, /*!< Data rejected due to write error */ -} sdspi_data_response_token_t; - -/*! @brief SD card individual commands */ -typedef enum _sd_command -{ - kSD_SendRelativeAddress = 3U, /*!< Send Relative Address */ - kSD_Switch = 6U, /*!< Switch Function */ - kSD_SendInterfaceCondition = 8U, /*!< Send Interface Condition */ - kSD_VoltageSwitch = 11U, /*!< Voltage Switch */ - kSD_SpeedClassControl = 20U, /*!< Speed Class control */ - kSD_EraseWriteBlockStart = 32U, /*!< Write Block Start */ - kSD_EraseWriteBlockEnd = 33U, /*!< Write Block End */ - kSD_SendTuningBlock = 19U, /*!< Send Tuning Block */ -} sd_command_t; - -/*! @brief SD card individual application commands */ -typedef enum _sd_application_command -{ - kSD_ApplicationSetBusWdith = 6U, /*!< Set Bus Width */ - kSD_ApplicationStatus = 13U, /*!< Send SD status */ - kSD_ApplicationSendNumberWriteBlocks = 22U, /*!< Send Number Of Written Blocks */ - kSD_ApplicationSetWriteBlockEraseCount = 23U, /*!< Set Write Block Erase Count */ - kSD_ApplicationSendOperationCondition = 41U, /*!< Send Operation Condition */ - kSD_ApplicationSetClearCardDetect = 42U, /*!< Set Connnect/Disconnect pull up on detect pin */ - kSD_ApplicationSendScr = 51U, /*!< Send Scr */ -} sd_application_command_t; - -/*! @brief SD card command class */ -enum _sdmmc_command_class -{ - kSDMMC_CommandClassBasic = (1U << 0U), /*!< Card command class 0 */ - kSDMMC_CommandClassBlockRead = (1U << 2U), /*!< Card command class 2 */ - kSDMMC_CommandClassBlockWrite = (1U << 4U), /*!< Card command class 4 */ - kSDMMC_CommandClassErase = (1U << 5U), /*!< Card command class 5 */ - kSDMMC_CommandClassWriteProtect = (1U << 6U), /*!< Card command class 6 */ - kSDMMC_CommandClassLockCard = (1U << 7U), /*!< Card command class 7 */ - kSDMMC_CommandClassApplicationSpecific = (1U << 8U), /*!< Card command class 8 */ - kSDMMC_CommandClassInputOutputMode = (1U << 9U), /*!< Card command class 9 */ - kSDMMC_CommandClassSwitch = (1U << 10U), /*!< Card command class 10 */ -}; - -/*! @brief OCR register in SD card */ -enum _sd_ocr_flag -{ - kSD_OcrPowerUpBusyFlag = (1U << 31U), /*!< Power up busy status */ - kSD_OcrHostCapacitySupportFlag = (1U << 30U), /*!< Card capacity status */ - kSD_OcrCardCapacitySupportFlag = kSD_OcrHostCapacitySupportFlag, /*!< Card capacity status */ - kSD_OcrSwitch18RequestFlag = (1U << 24U), /*!< Switch to 1.8V request */ - kSD_OcrSwitch18AcceptFlag = kSD_OcrSwitch18RequestFlag, /*!< Switch to 1.8V accepted */ - kSD_OcrVdd27_28Flag = (1U << 15U), /*!< VDD 2.7-2.8 */ - kSD_OcrVdd28_29Flag = (1U << 16U), /*!< VDD 2.8-2.9 */ - kSD_OcrVdd29_30Flag = (1U << 17U), /*!< VDD 2.9-3.0 */ - kSD_OcrVdd30_31Flag = (1U << 18U), /*!< VDD 2.9-3.0 */ - kSD_OcrVdd31_32Flag = (1U << 19U), /*!< VDD 3.0-3.1 */ - kSD_OcrVdd32_33Flag = (1U << 20U), /*!< VDD 3.1-3.2 */ - kSD_OcrVdd33_34Flag = (1U << 21U), /*!< VDD 3.2-3.3 */ - kSD_OcrVdd34_35Flag = (1U << 22U), /*!< VDD 3.3-3.4 */ - kSD_OcrVdd35_36Flag = (1U << 23U), /*!< VDD 3.4-3.5 */ -}; - -/*! @brief SD card specification version number */ -enum _sd_specification_version -{ - kSD_SpecificationVersion1_0 = (1U << 0U), /*!< SD card version 1.0-1.01 */ - kSD_SpecificationVersion1_1 = (1U << 1U), /*!< SD card version 1.10 */ - kSD_SpecificationVersion2_0 = (1U << 2U), /*!< SD card version 2.00 */ - kSD_SpecificationVersion3_0 = (1U << 3U), /*!< SD card version 3.0 */ -}; - -/*! @brief SD card bus width */ -typedef enum _sd_data_bus_width -{ - kSD_DataBusWidth1Bit = 0U, /*!< SD data bus width 1-bit mode */ - kSD_DataBusWidth4Bit = 1U, /*!< SD data bus width 4-bit mode */ -} sd_data_bus_width_t; - -/*! @brief SD card switch mode */ -typedef enum _sd_switch_mode -{ - kSD_SwitchCheck = 0U, /*!< SD switch mode 0: check function */ - kSD_SwitchSet = 1U, /*!< SD switch mode 1: set function */ -} sd_switch_mode_t; - -/*! @brief SD card CSD register flags */ -enum _sd_csd_flag -{ - kSD_CsdReadBlockPartialFlag = (1U << 0U), /*!< Partial blocks for read allowed [79:79] */ - kSD_CsdWriteBlockMisalignFlag = (1U << 1U), /*!< Write block misalignment [78:78] */ - kSD_CsdReadBlockMisalignFlag = (1U << 2U), /*!< Read block misalignment [77:77] */ - kSD_CsdDsrImplementedFlag = (1U << 3U), /*!< DSR implemented [76:76] */ - kSD_CsdEraseBlockEnabledFlag = (1U << 4U), /*!< Erase single block enabled [46:46] */ - kSD_CsdWriteProtectGroupEnabledFlag = (1U << 5U), /*!< Write protect group enabled [31:31] */ - kSD_CsdWriteBlockPartialFlag = (1U << 6U), /*!< Partial blocks for write allowed [21:21] */ - kSD_CsdFileFormatGroupFlag = (1U << 7U), /*!< File format group [15:15] */ - kSD_CsdCopyFlag = (1U << 8U), /*!< Copy flag [14:14] */ - kSD_CsdPermanentWriteProtectFlag = (1U << 9U), /*!< Permanent write protection [13:13] */ - kSD_CsdTemporaryWriteProtectFlag = (1U << 10U), /*!< Temporary write protection [12:12] */ -}; - -/*! @brief SD card SCR register flags */ -enum _sd_scr_flag -{ - kSD_ScrDataStatusAfterErase = (1U << 0U), /*!< Data status after erases [55:55] */ - kSD_ScrSdSpecification3 = (1U << 1U), /*!< Specification version 3.00 or higher [47:47]*/ -}; - -/*! @brief SD timing function number */ -enum _sd_timing_function -{ - kSD_FunctionSDR12Deafult = 0U, /*!< SDR12 mode & default*/ - kSD_FunctionSDR25HighSpeed = 1U, /*!< SDR25 & high speed*/ - kSD_FunctionSDR50 = 2U, /*!< SDR50 mode*/ - kSD_FunctionSDR104 = 3U, /*!< SDR104 mode*/ - kSD_FunctionDDR50 = 4U, /*!< DDR50 mode*/ -}; - -/*! @brief SD group number */ -enum _sd_group_num -{ - kSD_GroupTimingMode = 0U, /*!< acess mode group*/ - kSD_GroupCommandSystem = 1U, /*!< command system group*/ - kSD_GroupDriverStrength = 2U, /*!< driver strength group*/ - kSD_GroupCurrentLimit = 3U, /*!< current limit group*/ -}; - -/*! @brief SD card timing mode flags */ -typedef enum _sd_timing_mode -{ - kSD_TimingSDR12DefaultMode = 0U, /*!< Identification mode & SDR12 */ - kSD_TimingSDR25HighSpeedMode = 1U, /*!< High speed mode & SDR25 */ - kSD_TimingSDR50Mode = 2U, /*!< SDR50 mode*/ - kSD_TimingSDR104Mode = 3U, /*!< SDR104 mode */ - kSD_TimingDDR50Mode = 4U, /*!< DDR50 mode */ -} sd_timing_mode_t; - -/*! @brief SD card driver strength */ -typedef enum _sd_driver_strength -{ - kSD_DriverStrengthTypeB = 0U, /*!< default driver strength*/ - kSD_DriverStrengthTypeA = 1U, /*!< driver strength TYPE A */ - kSD_DriverStrengthTypeC = 2U, /*!< driver strength TYPE C */ - kSD_DriverStrengthTypeD = 3U, /*!< driver strength TYPE D */ -} sd_driver_strength_t; - -/*! @brief SD card current limit */ -typedef enum _sd_max_current -{ - kSD_CurrentLimit200MA = 0U, /*!< default current limit */ - kSD_CurrentLimit400MA = 1U, /*!< current limit to 400MA */ - kSD_CurrentLimit600MA = 2U, /*!< current limit to 600MA */ - kSD_CurrentLimit800MA = 3U, /*!< current limit to 800MA */ -} sd_max_current_t; - -/*! @brief SD/MMC card common commands */ -typedef enum _sdmmc_command -{ - kSDMMC_GoIdleState = 0U, /*!< Go Idle State */ - kSDMMC_AllSendCid = 2U, /*!< All Send CID */ - kSDMMC_SetDsr = 4U, /*!< Set DSR */ - kSDMMC_SelectCard = 7U, /*!< Select Card */ - kSDMMC_SendCsd = 9U, /*!< Send CSD */ - kSDMMC_SendCid = 10U, /*!< Send CID */ - kSDMMC_StopTransmission = 12U, /*!< Stop Transmission */ - kSDMMC_SendStatus = 13U, /*!< Send Status */ - kSDMMC_GoInactiveState = 15U, /*!< Go Inactive State */ - kSDMMC_SetBlockLength = 16U, /*!< Set Block Length */ - kSDMMC_ReadSingleBlock = 17U, /*!< Read Single Block */ - kSDMMC_ReadMultipleBlock = 18U, /*!< Read Multiple Block */ - kSDMMC_SetBlockCount = 23U, /*!< Set Block Count */ - kSDMMC_WriteSingleBlock = 24U, /*!< Write Single Block */ - kSDMMC_WriteMultipleBlock = 25U, /*!< Write Multiple Block */ - kSDMMC_ProgramCsd = 27U, /*!< Program CSD */ - kSDMMC_SetWriteProtect = 28U, /*!< Set Write Protect */ - kSDMMC_ClearWriteProtect = 29U, /*!< Clear Write Protect */ - kSDMMC_SendWriteProtect = 30U, /*!< Send Write Protect */ - kSDMMC_Erase = 38U, /*!< Erase */ - kSDMMC_LockUnlock = 42U, /*!< Lock Unlock */ - kSDMMC_ApplicationCommand = 55U, /*!< Send Application Command */ - kSDMMC_GeneralCommand = 56U, /*!< General Purpose Command */ - kSDMMC_ReadOcr = 58U, /*!< Read OCR */ -} sdmmc_command_t; - -/*! @brief sdio card cccr register addr */ -enum _sdio_cccr_reg -{ - kSDIO_RegCCCRSdioVer = 0x00U, /*!< CCCR & SDIO version*/ - kSDIO_RegSDVersion = 0x01U, /*!< SD version */ - kSDIO_RegIOEnable = 0x02U, /*!< io enable register */ - kSDIO_RegIOReady = 0x03U, /*!< io ready register */ - kSDIO_RegIOIntEnable = 0x04U, /*!< io interrupt enable register */ - kSDIO_RegIOIntPending = 0x05U, /*!< io interrupt pending register */ - kSDIO_RegIOAbort = 0x06U, /*!< io abort register */ - kSDIO_RegBusInterface = 0x07U, /*!< bus interface register */ - kSDIO_RegCardCapability = 0x08U, /*!< card capability register */ - kSDIO_RegCommonCISPointer = 0x09U, /*!< common CIS pointer register */ - kSDIO_RegBusSuspend = 0x0C, /*!< bus suspend register */ - kSDIO_RegFunctionSelect = 0x0DU, /*!< function select register */ - kSDIO_RegExecutionFlag = 0x0EU, /*!< execution flag register */ - kSDIO_RegReadyFlag = 0x0FU, /*!< ready flag register */ - kSDIO_RegFN0BlockSizeLow = 0x10U, /*!< FN0 block size register */ - kSDIO_RegFN0BlockSizeHigh = 0x11U, /*!< FN0 block size register */ - kSDIO_RegPowerControl = 0x12U, /*!< power control register */ - kSDIO_RegHighSpeed = 0x13U, /*!< high speed register */ -}; - -/*! @brief sdio card individual commands */ -typedef enum _sdio_command -{ - kSDIO_SendRelativeAddress = 3U, /*!< send relative address */ - kSDIO_SendOperationCondition = 5U, /*!< send operation condition */ - kSDIO_SendInterfaceCondition = 8U, /*!< send interface condition */ - kSDIO_RWIODirect = 52U, /*!< read/write IO direct command */ - kSDIO_RWIOExtended = 53U, /*!< read/write IO extended command */ -} sdio_command_t; - -/*! @brief sdio card individual commands */ -typedef enum _sdio_func_num -{ - kSDIO_FunctionNum0, /*!< sdio function0*/ - kSDIO_FunctionNum1, /*!< sdio function1*/ - kSDIO_FunctionNum2, /*!< sdio function2*/ - kSDIO_FunctionNum3, /*!< sdio function3*/ - kSDIO_FunctionNum4, /*!< sdio function4*/ - kSDIO_FunctionNum5, /*!< sdio function5*/ - kSDIO_FunctionNum6, /*!< sdio function6*/ - kSDIO_FunctionNum7, /*!< sdio function7*/ - kSDIO_FunctionMemory, /*!< for combo card*/ -} sdio_func_num_t; - -#define SDIO_CMD_ARGUMENT_RW_POS (31U) /*!< read/write flag position */ -#define SDIO_CMD_ARGUMENT_FUNC_NUM_POS (28U) /*!< function number position */ -#define SDIO_DIRECT_CMD_ARGUMENT_RAW_POS (27U) /*!< direct raw flag position */ -#define SDIO_CMD_ARGUMENT_REG_ADDR_POS (9U) /*!< direct reg addr position */ -#define SDIO_CMD_ARGUMENT_REG_ADDR_MASK (0x1FFFFU) /*!< direct reg addr mask */ -#define SDIO_DIRECT_CMD_DATA_MASK (0xFFU) /*!< data mask */ - -#define SDIO_EXTEND_CMD_ARGUMENT_BLOCK_MODE_POS (27U) /*!< extended command argument block mode bit position */ -#define SDIO_EXTEND_CMD_ARGUMENT_OP_CODE_POS (26U) /*!< extended command argument OP Code bit position */ -#define SDIO_EXTEND_CMD_BLOCK_MODE_MASK (0x08000000U) /*!< block mode mask */ -#define SDIO_EXTEND_CMD_OP_CODE_MASK (0x04000000U) /*!< op code mask */ -#define SDIO_EXTEND_CMD_COUNT_MASK (0x1FFU) /*!< byte/block count mask */ -#define SDIO_MAX_BLOCK_SIZE (2048U) /*!< max block size */ -#define SDIO_FBR_BASE(x) (x * 0x100U) /*!< function basic register */ -#define SDIO_TPL_CODE_END (0xFFU) /*!< tuple end */ -#define SDIO_TPL_CODE_MANIFID (0x20U) /*!< manufacturer ID */ -#define SDIO_TPL_CODE_FUNCID (0x21U) /*!< function ID */ -#define SDIO_TPL_CODE_FUNCE (0x22U) /*!< function extension tuple*/ -/*! @brief sdio command response flag */ -enum _sdio_status_flag -{ - kSDIO_StatusCmdCRCError = 0x8000U, /*!< the CRC check of the previous cmd fail*/ - kSDIO_StatusIllegalCmd = 0x4000U, /*!< cmd illegal for the card state */ - kSDIO_StatusR6Error = 0x2000U, /*!< special for R6 error status */ - kSDIO_StatusError = 0x0800U, /*!< A general or an unknown error occurred */ - kSDIO_StatusFunctionNumError = 0x0200U, /*!< invail function error */ - kSDIO_StatusOutofRange = 0x0100U, /*!< cmd argument was out of the allowed range*/ -}; - -/*! @brief sdio operation condition flag */ -enum _sdio_ocr_flag -{ - kSDIO_OcrPowerUpBusyFlag = (1U << 31U), /*!< Power up busy status */ - kSDIO_OcrIONumber = (7U << 28U), /*!< number of IO function */ - kSDIO_OcrMemPresent = (1U << 27U), /*!< memory present flag */ - - kSDIO_OcrVdd20_21Flag = (1U << 8U), /*!< VDD 2.0-2.1 */ - kSDIO_OcrVdd21_22Flag = (1U << 9U), /*!< VDD 2.1-2.2 */ - kSDIO_OcrVdd22_23Flag = (1U << 10U), /*!< VDD 2.2-2.3 */ - kSDIO_OcrVdd23_24Flag = (1U << 11U), /*!< VDD 2.3-2.4 */ - kSDIO_OcrVdd24_25Flag = (1U << 12U), /*!< VDD 2.4-2.5 */ - kSDIO_OcrVdd25_26Flag = (1U << 13U), /*!< VDD 2.5-2.6 */ - kSDIO_OcrVdd26_27Flag = (1U << 14U), /*!< VDD 2.6-2.7 */ - kSDIO_OcrVdd27_28Flag = (1U << 15U), /*!< VDD 2.7-2.8 */ - kSDIO_OcrVdd28_29Flag = (1U << 16U), /*!< VDD 2.8-2.9 */ - kSDIO_OcrVdd29_30Flag = (1U << 17U), /*!< VDD 2.9-3.0 */ - kSDIO_OcrVdd30_31Flag = (1U << 18U), /*!< VDD 2.9-3.0 */ - kSDIO_OcrVdd31_32Flag = (1U << 19U), /*!< VDD 3.0-3.1 */ - kSDIO_OcrVdd32_33Flag = (1U << 20U), /*!< VDD 3.1-3.2 */ - kSDIO_OcrVdd33_34Flag = (1U << 21U), /*!< VDD 3.2-3.3 */ - kSDIO_OcrVdd34_35Flag = (1U << 22U), /*!< VDD 3.3-3.4 */ - kSDIO_OcrVdd35_36Flag = (1U << 23U), /*!< VDD 3.4-3.5 */ - -}; - -/*! @brief sdio capability flag */ -enum _sdio_capability_flag -{ - kSDIO_CCCRSupportDirectCmdDuringDataTrans = (1U << 0U), /*!< support direct cmd during data transfer */ - kSDIO_CCCRSupportMultiBlock = (1U << 1U), /*!< support multi block mode */ - kSDIO_CCCRSupportReadWait = (1U << 2U), /*!< support read wait */ - kSDIO_CCCRSupportSuspendResume = (1U << 3U), /*!< support suspend resume */ - kSDIO_CCCRSupportIntDuring4BitDataTrans = (1U << 4U), /*!< support interrupt during 4-bit data transfer */ - kSDIO_CCCRSupportLowSpeed1Bit = (1U << 6U), /*!< support low speed 1bit mode */ - kSDIO_CCCRSupportLowSpeed4Bit = (1U << 7U), /*!< support low speed 4bit mode */ - kSDIO_CCCRSupportMasterPowerControl = (1U << 8U), /*!< support master power control */ - kSDIO_CCCRSupportHighSpeed = (1U << 9U), /*!< support high speed */ - kSDIO_CCCRSupportContinuousSPIInt = (1U << 10U), /*!< support continuous SPI interrupt */ - kSDIO_FBRSupportCSA = (1U << 11U), /*!< function support CSA */ - kSDIO_FBRSupportPowerSelection = (1U << 12U), /*!< function support power selection */ - -}; - -/*! @brief sdio bus width */ -typedef enum _sdio_bus_width -{ - kSDIO_DataBus1Bit = 0x00U, /*!< 1bit bus mode */ - kSDIO_DataBus4Bit = 0X02U, /*!< 4 bit bus mode*/ -} sdio_bus_width_t; - -/*! @brief MMC card individual commands */ -typedef enum _mmc_command -{ - kMMC_SendOperationCondition = 1U, /*!< Send Operation Condition */ - kMMC_SetRelativeAddress = 3U, /*!< Set Relative Address */ - kMMC_SleepAwake = 5U, /*!< Sleep Awake */ - kMMC_Switch = 6U, /*!< Switch */ - kMMC_SendExtendedCsd = 8U, /*!< Send EXT_CSD */ - kMMC_ReadDataUntilStop = 11U, /*!< Read Data Until Stop */ - kMMC_BusTestRead = 14U, /*!< Test Read */ - kMMC_SendingBusTest = 19U, /*!< test bus width cmd*/ - kMMC_WriteDataUntilStop = 20U, /*!< Write Data Until Stop */ - kMMC_SendTuningBlock = 21U, /*!< MMC sending tuning block */ - kMMC_ProgramCid = 26U, /*!< Program CID */ - kMMC_EraseGroupStart = 35U, /*!< Erase Group Start */ - kMMC_EraseGroupEnd = 36U, /*!< Erase Group End */ - kMMC_FastInputOutput = 39U, /*!< Fast IO */ - kMMC_GoInterruptState = 40U, /*!< Go interrupt State */ -} mmc_command_t; - -/*! @brief MMC card classified as voltage range */ -typedef enum _mmc_classified_voltage -{ - kMMC_ClassifiedVoltageHigh = 0U, /*!< High-voltage MMC card */ - kMMC_ClassifiedVoltageDual = 1U, /*!< Dual-voltage MMC card */ -} mmc_classified_voltage_t; - -/*! @brief MMC card classified as density level */ -typedef enum _mmc_classified_density -{ - kMMC_ClassifiedDensityWithin2GB = 0U, /*!< Density byte is less than or equal 2GB */ - kMMC_ClassifiedDensityHigher2GB = 1U, /* Density byte is higher than 2GB */ -} mmc_classified_density_t; - -/*! @brief The bit mask for VOLTAGE WINDOW 1.70V to 1.95V field in OCR */ -#define MMC_OCR_V170TO195_SHIFT (7U) -/*! @brief The bit mask for VOLTAGE WINDOW 1.70V to 1.95V field in OCR */ -#define MMC_OCR_V170TO195_MASK (0x00000080U) -/*! @brief The bit shift for VOLTAGE WINDOW 2.00V to 2.60V field in OCR */ -#define MMC_OCR_V200TO260_SHIFT (8U) -/*! @brief The bit mask for VOLTAGE WINDOW 2.00V to 2.60V field in OCR */ -#define MMC_OCR_V200TO260_MASK (0x00007F00U) -/*! @brief The bit shift for VOLTAGE WINDOW 2.70V to 3.60V field in OCR */ -#define MMC_OCR_V270TO360_SHIFT (15U) -/*! @brief The bit mask for VOLTAGE WINDOW 2.70V to 3.60V field in OCR */ -#define MMC_OCR_V270TO360_MASK (0x00FF8000U) -/*! @brief The bit shift for ACCESS MODE field in OCR */ -#define MMC_OCR_ACCESS_MODE_SHIFT (29U) -/*! @brief The bit mask for ACCESS MODE field in OCR */ -#define MMC_OCR_ACCESS_MODE_MASK (0x60000000U) -/*! @brief The bit shift for BUSY field in OCR */ -#define MMC_OCR_BUSY_SHIFT (31U) -/*! @brief The bit mask for BUSY field in OCR */ -#define MMC_OCR_BUSY_MASK (1U << MMC_OCR_BUSY_SHIFT) - -/*! @brief MMC card access mode(Access mode in OCR). */ -typedef enum _mmc_access_mode -{ - kMMC_AccessModeByte = 0U, /*!< The card should be accessed as byte */ - kMMC_AccessModeSector = 2U, /*!< The card should be accessed as sector */ -} mmc_access_mode_t; - -/*! @brief MMC card voltage window(VDD voltage window in OCR). */ -typedef enum _mmc_voltage_window -{ - kMMC_VoltageWindowNone = 0U, /*!< voltage window is not define by user*/ - kMMC_VoltageWindow120 = 0x01U, /*!< Voltage window is 1.20V */ - kMMC_VoltageWindow170to195 = 0x02U, /*!< Voltage window is 1.70V to 1.95V */ - kMMC_VoltageWindows270to360 = 0x1FFU, /*!< Voltage window is 2.70V to 3.60V */ -} mmc_voltage_window_t; - -/*! @brief CSD structure version(CSD_STRUCTURE in CSD). */ -typedef enum _mmc_csd_structure_version -{ - kMMC_CsdStrucureVersion10 = 0U, /*!< CSD version No. 1.0 */ - kMMC_CsdStrucureVersion11 = 1U, /*!< CSD version No. 1.1 */ - kMMC_CsdStrucureVersion12 = 2U, /*!< CSD version No. 1.2 */ - kMMC_CsdStrucureVersionInExtcsd = 3U, /*!< Version coded in Extended CSD */ -} mmc_csd_structure_version_t; - -/*! @brief MMC card specification version(SPEC_VERS in CSD). */ -typedef enum _mmc_specification_version -{ - kMMC_SpecificationVersion0 = 0U, /*!< Allocated by MMCA */ - kMMC_SpecificationVersion1 = 1U, /*!< Allocated by MMCA */ - kMMC_SpecificationVersion2 = 2U, /*!< Allocated by MMCA */ - kMMC_SpecificationVersion3 = 3U, /*!< Allocated by MMCA */ - kMMC_SpecificationVersion4 = 4U, /*!< Version 4.1/4.2/4.3/4.41-4.5-4.51-5.0 */ -} mmc_specification_version_t; - -/*! @brief The bit shift for FREQUENCY UNIT field in TRANSFER SPEED(TRAN-SPEED in Extended CSD) */ -#define MMC_TRANSFER_SPEED_FREQUENCY_UNIT_SHIFT (0U) -/*! @brief The bit mask for FRQEUENCY UNIT in TRANSFER SPEED */ -#define MMC_TRANSFER_SPEED_FREQUENCY_UNIT_MASK (0x07U) -/*! @brief The bit shift for MULTIPLIER field in TRANSFER SPEED */ -#define MMC_TRANSFER_SPEED_MULTIPLIER_SHIFT (3U) -/*! @brief The bit mask for MULTIPLIER field in TRANSFER SPEED */ -#define MMC_TRANSFER_SPEED_MULTIPLIER_MASK (0x78U) - -/*! @brief Read the value of FREQUENCY UNIT in TRANSFER SPEED. */ -#define READ_MMC_TRANSFER_SPEED_FREQUENCY_UNIT(CSD) \ - (((CSD.transferSpeed) & MMC_TRANSFER_SPEED_FREQUENCY_UNIT_MASK) >> MMC_TRANSFER_SPEED_FREQUENCY_UNIT_SHIFT) -/*! @brief Read the value of MULTIPLER filed in TRANSFER SPEED. */ -#define READ_MMC_TRANSFER_SPEED_MULTIPLIER(CSD) \ - (((CSD.transferSpeed) & MMC_TRANSFER_SPEED_MULTIPLIER_MASK) >> MMC_TRANSFER_SPEED_MULTIPLIER_SHIFT) - -/*! @brief MMC card Extended CSD fix version(EXT_CSD_REV in Extended CSD) */ -typedef enum _mmc_extended_csd_revision -{ - kMMC_ExtendedCsdRevision10 = 0U, /*!< Revision 1.0 */ - kMMC_ExtendedCsdRevision11 = 1U, /*!< Revision 1.1 */ - kMMC_ExtendedCsdRevision12 = 2U, /*!< Revision 1.2 */ - kMMC_ExtendedCsdRevision13 = 3U, /*!< Revision 1.3 MMC4.3*/ - kMMC_ExtendedCsdRevision14 = 4U, /*!< Revision 1.4 obsolete*/ - kMMC_ExtendedCsdRevision15 = 5U, /*!< Revision 1.5 MMC4.41*/ - kMMC_ExtendedCsdRevision16 = 6U, /*!< Revision 1.6 MMC4.5*/ - kMMC_ExtendedCsdRevision17 = 7U, /*!< Revision 1.7 MMC5.0 */ -} mmc_extended_csd_revision_t; - -/*! @brief MMC card command set(COMMAND_SET in Extended CSD) */ -typedef enum _mmc_command_set -{ - kMMC_CommandSetStandard = 0U, /*!< Standard MMC */ - kMMC_CommandSet1 = 1U, /*!< Command set 1 */ - kMMC_CommandSet2 = 2U, /*!< Command set 2 */ - kMMC_CommandSet3 = 3U, /*!< Command set 3 */ - kMMC_CommandSet4 = 4U, /*!< Command set 4 */ -} mmc_command_set_t; - -/*! @brief boot support(BOOT_INFO in Extended CSD) */ -enum _mmc_support_boot_mode -{ - kMMC_SupportAlternateBoot = 1U, /*!< support alternative boot mode*/ - kMMC_SupportDDRBoot = 2U, /*!< support DDR boot mode*/ - kMMC_SupportHighSpeedBoot = 4U, /*!< support high speed boot mode*/ -}; -/*! @brief The power class value bit mask when bus in 4 bit mode */ -#define MMC_POWER_CLASS_4BIT_MASK (0x0FU) -/*! @brief The power class current value bit mask when bus in 8 bit mode */ -#define MMC_POWER_CLASS_8BIT_MASK (0xF0U) - -/*! @brief MMC card high-speed timing(HS_TIMING in Extended CSD) */ -typedef enum _mmc_high_speed_timing -{ - kMMC_HighSpeedTimingNone = 0U, /*!< MMC card using none high-speed timing */ - kMMC_HighSpeedTiming = 1U, /*!< MMC card using high-speed timing */ - kMMC_HighSpeed200Timing = 2U, /*!< MMC card high speed 200 timing*/ - kMMC_HighSpeed400Timing = 3U, /*!< MMC card high speed 400 timing*/ - kMMC_HighSpeed26MHZTiming = 4U, /*!< MMC high speed 26MHZ timing */ - kMMC_HighSpeed52MHZTiming = 5U, /*!< MMC high speed 52MHZ timing */ - kMMC_HighSpeedDDR52180V300VTiming = 6U, /*!< MMC high speed timing DDR52 1.8V */ - kMMC_HighSpeedDDR52120VTiming = 7U, /*!< MMC high speed timing DDR52 1.2V */ -} mmc_high_speed_timing_t; - -/*! @brief The number of data bus width type */ -#define MMC_DATA_BUS_WIDTH_TYPE_NUMBER (3U) -/*! @brief MMC card data bus width(BUS_WIDTH in Extended CSD) */ -typedef enum _mmc_data_bus_width -{ - kMMC_DataBusWidth1bit = 0U, /*!< MMC data bus width is 1 bit */ - kMMC_DataBusWidth4bit = 1U, /*!< MMC data bus width is 4 bits */ - kMMC_DataBusWidth8bit = 2U, /*!< MMC data bus width is 8 bits */ - kMMC_DataBusWidth4bitDDR = 5U, /*!< MMC data bus width is 4 bits ddr */ - kMMC_DataBusWidth8bitDDR = 6U, /*!< MMC data bus width is 8 bits ddr */ -} mmc_data_bus_width_t; - -/*! @brief MMC card boot partition enabled(BOOT_PARTITION_ENABLE in Extended CSD) */ -typedef enum _mmc_boot_partition_enable -{ - kMMC_BootPartitionEnableNot = 0U, /*!< Device not boot enabled (default) */ - kMMC_BootPartitionEnablePartition1 = 1U, /*!< Boot partition 1 enabled for boot */ - kMMC_BootPartitionEnablePartition2 = 2U, /*!< Boot partition 2 enabled for boot */ - kMMC_BootPartitionEnableUserAera = 7U, /*!< User area enabled for boot */ -} mmc_boot_partition_enable_t; - -/*! @brief MMC card partition to be accessed(BOOT_PARTITION_ACCESS in Extended CSD) */ -typedef enum _mmc_access_partition -{ - kMMC_AccessPartitionUserAera = 0U, /*!< No access to boot partition (default), normal partition */ - kMMC_AccessPartitionBoot1 = 1U, /*!< Read/Write boot partition 1 */ - kMMC_AccessPartitionBoot2 = 2U, /*!< Read/Write boot partition 2*/ - kMMC_AccessRPMB = 3U, /*!< Replay protected mem block */ - kMMC_AccessGeneralPurposePartition1 = 4U, /*!< access to general purpose partition 1 */ - kMMC_AccessGeneralPurposePartition2 = 5U, /*!< access to general purpose partition 2 */ - kMMC_AccessGeneralPurposePartition3 = 6U, /*!< access to general purpose partition 3 */ - kMMC_AccessGeneralPurposePartition4 = 7U, /*!< access to general purpose partition 4 */ -} mmc_access_partition_t; - -/*! @brief The bit shift for PARTITION ACCESS filed in BOOT CONFIG (BOOT_CONFIG in Extend CSD) */ -#define MMC_BOOT_CONFIG_PARTITION_ACCESS_SHIFT (0U) -/*! @brief The bit mask for PARTITION ACCESS field in BOOT CONFIG */ -#define MMC_BOOT_CONFIG_PARTITION_ACCESS_MASK (0x00000007U) -/*! @brief The bit shift for PARTITION ENABLE field in BOOT CONFIG */ -#define MMC_BOOT_CONFIG_PARTITION_ENABLE_SHIFT (3U) -/*! @brief The bit mask for PARTITION ENABLE field in BOOT CONFIG */ -#define MMC_BOOT_CONFIG_PARTITION_ENABLE_MASK (0x00000038U) -/*! @brief The bit shift for ACK field in BOOT CONFIG */ -#define MMC_BOOT_CONFIG_ACK_SHIFT (6U) -/*! @brief The bit mask for ACK field in BOOT CONFIG */ -#define MMC_BOOT_CONFIG_ACK_MASK (0x00000040U) -/*! @brief The bit shift for BOOT BUS WIDTH field in BOOT CONFIG */ -#define MMC_BOOT_BUS_WIDTH_WIDTH_SHIFT (8U) -/*! @brief The bit mask for BOOT BUS WIDTH field in BOOT CONFIG */ -#define MMC_BOOT_BUS_WIDTH_WIDTH_MASK (0x00000300U) -/*! @brief The bit shift for BOOT BUS WIDTH RESET field in BOOT CONFIG */ -#define MMC_BOOT_BUS_WIDTH_RESET_SHIFT (10U) -/*! @brief The bit mask for BOOT BUS WIDTH RESET field in BOOT CONFIG */ -#define MMC_BOOT_BUS_WIDTH_RESET_MASK (0x00000400U) - -/*! @brief MMC card CSD register flags */ -enum _mmc_csd_flag -{ - kMMC_CsdReadBlockPartialFlag = (1U << 0U), /*!< Partial blocks for read allowed */ - kMMC_CsdWriteBlockMisalignFlag = (1U << 1U), /*!< Write block misalignment */ - kMMC_CsdReadBlockMisalignFlag = (1U << 2U), /*!< Read block misalignment */ - kMMC_CsdDsrImplementedFlag = (1U << 3U), /*!< DSR implemented */ - kMMC_CsdWriteProtectGroupEnabledFlag = (1U << 4U), /*!< Write protect group enabled */ - kMMC_CsdWriteBlockPartialFlag = (1U << 5U), /*!< Partial blocks for write allowed */ - kMMC_ContentProtectApplicationFlag = (1U << 6U), /*!< Content protect application */ - kMMC_CsdFileFormatGroupFlag = (1U << 7U), /*!< File format group */ - kMMC_CsdCopyFlag = (1U << 8U), /*!< Copy flag */ - kMMC_CsdPermanentWriteProtectFlag = (1U << 9U), /*!< Permanent write protection */ - kMMC_CsdTemporaryWriteProtectFlag = (1U << 10U), /*!< Temporary write protection */ -}; - -/*! @brief Extended CSD register access mode(Access mode in CMD6). */ -typedef enum _mmc_extended_csd_access_mode -{ - kMMC_ExtendedCsdAccessModeCommandSet = 0U, /*!< Command set related setting */ - kMMC_ExtendedCsdAccessModeSetBits = 1U, /*!< Set bits in specific byte in Extended CSD */ - kMMC_ExtendedCsdAccessModeClearBits = 2U, /*!< Clear bits in specific byte in Extended CSD */ - kMMC_ExtendedCsdAccessModeWriteBits = 3U, /*!< Write a value to specific byte in Extended CSD */ -} mmc_extended_csd_access_mode_t; - -/*! @brief EXT CSD byte index */ -typedef enum _mmc_extended_csd_index -{ - kMMC_ExtendedCsdIndexEraseGroupDefinition = 175U, /*!< Erase Group Def */ - kMMC_ExtendedCsdIndexBootBusWidth = 177U, /*!< Boot Bus Width */ - kMMC_ExtendedCsdIndexBootConfig = 179U, /*!< Boot Config */ - kMMC_ExtendedCsdIndexBusWidth = 183U, /*!< Bus Width */ - kMMC_ExtendedCsdIndexHighSpeedTiming = 185U, /*!< High-speed Timing */ - kMMC_ExtendedCsdIndexPowerClass = 187U, /*!< Power Class */ - kMMC_ExtendedCsdIndexCommandSet = 191U, /*!< Command Set */ -} mmc_extended_csd_index_t; - -/*! @brief mmc driver strength */ -enum _mmc_driver_strength -{ - kMMC_DriverStrength0 = 0U, /*!< Driver type0 ,nominal impedance 50ohm */ - kMMC_DriverStrength1 = 1U, /*!< Driver type1 ,nominal impedance 33ohm */ - kMMC_DriverStrength2 = 2U, /*!< Driver type2 ,nominal impedance 66ohm */ - kMMC_DriverStrength3 = 3U, /*!< Driver type3 ,nominal impedance 100ohm */ - kMMC_DriverStrength4 = 4U, /*!< Driver type4 ,nominal impedance 40ohm */ -}; - -/*! @brief mmc extended csd flags*/ -typedef enum _mmc_extended_csd_flags -{ - kMMC_ExtCsdExtPartitionSupport = (1 << 0U), /*!< partitioning support[160] */ - kMMC_ExtCsdEnhancePartitionSupport = (1 << 1U), /*!< partitioning support[160] */ - kMMC_ExtCsdPartitioningSupport = (1 << 2U), /*!< partitioning support[160] */ - kMMC_ExtCsdPrgCIDCSDInDDRModeSupport = (1 << 3U), /*!< CMD26 and CMD27 are support dual data rate [130]*/ - kMMC_ExtCsdBKOpsSupport = (1 << 4U), /*!< background operation feature support [502]*/ - kMMC_ExtCsdDataTagSupport = (1 << 5U), /*!< data tag support[499]*/ - kMMC_ExtCsdModeOperationCodeSupport = (1 << 6U), /*!< mode operation code support[493]*/ -} mmc_extended_csd_flags_t; - -/*! @brief The length of Extended CSD register, unit as bytes. */ -#define MMC_EXTENDED_CSD_BYTES (512U) - -/*! @brief MMC card default relative address */ -#define MMC_DEFAULT_RELATIVE_ADDRESS (2U) - -/*! @brief SD card product name length united as bytes. */ -#define SD_PRODUCT_NAME_BYTES (5U) - -/*! @brief sdio card FBR register */ -typedef struct _sdio_fbr -{ - uint8_t flags; /*!< current io flags */ - uint8_t ioStdFunctionCode; /*!< current io standard function code */ - uint8_t ioExtFunctionCode; /*!< current io extended function code*/ - uint32_t ioPointerToCIS; /*!< current io pointer to CIS */ - uint32_t ioPointerToCSA; /*!< current io pointer to CSA*/ - uint16_t ioBlockSize; /*!< current io block size */ -} sdio_fbr_t; - -/*! @brief sdio card common CIS */ -typedef struct _sdio_common_cis -{ - /* manufacturer identification string tuple */ - uint16_t mID; /*!< manufacturer code */ - uint16_t mInfo; /*!< manufacturer information */ - - /*function identification tuple */ - uint8_t funcID; /*!< function ID */ - - /* function extension tuple */ - uint16_t fn0MaxBlkSize; /*!< function 0 max block size */ - uint8_t maxTransSpeed; /*!< max data transfer speed for all function */ - -} sdio_common_cis_t; - -/*! @brief sdio card function CIS */ -typedef struct _sdio_func_cis -{ - /*function identification tuple */ - uint8_t funcID; /*!< function ID */ - - /* function extension tuple */ - uint8_t funcInfo; /*!< function info */ - uint8_t ioVersion; /*!< level of application specification this io support */ - uint32_t cardPSN; /*!< product serial number */ - uint32_t ioCSASize; /*!< avaliable CSA size for io */ - uint8_t ioCSAProperty; /*!< CSA property */ - uint16_t ioMaxBlockSize; /*!< io max transfer data size */ - uint32_t ioOCR; /*!< io ioeration condition */ - uint8_t ioOPMinPwr; /*!< min current in operation mode */ - uint8_t ioOPAvgPwr; /*!< average current in operation mode */ - uint8_t ioOPMaxPwr; /*!< max current in operation mode */ - uint8_t ioSBMinPwr; /*!< min current in standby mode */ - uint8_t ioSBAvgPwr; /*!< average current in standby mode */ - uint8_t ioSBMaxPwr; /*!< max current in standby mode */ - - uint16_t ioMinBandWidth; /*!< io min transfer bandwidth */ - uint16_t ioOptimumBandWidth; /*!< io optimum transfer bandwidth */ - uint16_t ioReadyTimeout; /*!< timeout value from enalbe to ready */ - uint16_t ioHighCurrentAvgCurrent; /*!< the average peak current (mA) - when IO operating in high current mode */ - uint16_t ioHighCurrentMaxCurrent; /*!< the max peak current (mA) - when IO operating in high current mode */ - uint16_t ioLowCurrentAvgCurrent; /*!< the average peak current (mA) - when IO operating in lower current mode */ - uint16_t ioLowCurrentMaxCurrent; /*!< the max peak current (mA) - when IO operating in lower current mode */ -} sdio_func_cis_t; - -/*! @brief SD card CID register */ -typedef struct _sd_cid -{ - uint8_t manufacturerID; /*!< Manufacturer ID [127:120] */ - uint16_t applicationID; /*!< OEM/Application ID [119:104] */ - uint8_t productName[SD_PRODUCT_NAME_BYTES]; /*!< Product name [103:64] */ - uint8_t productVersion; /*!< Product revision [63:56] */ - uint32_t productSerialNumber; /*!< Product serial number [55:24] */ - uint16_t manufacturerData; /*!< Manufacturing date [19:8] */ -} sd_cid_t; - -/*! @brief SD card CSD register */ -typedef struct _sd_csd -{ - uint8_t csdStructure; /*!< CSD structure [127:126] */ - uint8_t dataReadAccessTime1; /*!< Data read access-time-1 [119:112] */ - uint8_t dataReadAccessTime2; /*!< Data read access-time-2 in clock cycles (NSAC*100) [111:104] */ - uint8_t transferSpeed; /*!< Maximum data transfer rate [103:96] */ - uint16_t cardCommandClass; /*!< Card command classes [95:84] */ - uint8_t readBlockLength; /*!< Maximum read data block length [83:80] */ - uint16_t flags; /*!< Flags in _sd_csd_flag */ - uint32_t deviceSize; /*!< Device size [73:62] */ - /* Following fields from 'readCurrentVddMin' to 'deviceSizeMultiplier' exist in CSD version 1 */ - uint8_t readCurrentVddMin; /*!< Maximum read current at VDD min [61:59] */ - uint8_t readCurrentVddMax; /*!< Maximum read current at VDD max [58:56] */ - uint8_t writeCurrentVddMin; /*!< Maximum write current at VDD min [55:53] */ - uint8_t writeCurrentVddMax; /*!< Maximum write current at VDD max [52:50] */ - uint8_t deviceSizeMultiplier; /*!< Device size multiplier [49:47] */ - - uint8_t eraseSectorSize; /*!< Erase sector size [45:39] */ - uint8_t writeProtectGroupSize; /*!< Write protect group size [38:32] */ - uint8_t writeSpeedFactor; /*!< Write speed factor [28:26] */ - uint8_t writeBlockLength; /*!< Maximum write data block length [25:22] */ - uint8_t fileFormat; /*!< File format [11:10] */ -} sd_csd_t; - -/*! @brief The bit shift for RATE UNIT field in TRANSFER SPEED */ -#define SD_TRANSFER_SPEED_RATE_UNIT_SHIFT (0U) -/*! @brief The bit mask for RATE UNIT field in TRANSFER SPEED */ -#define SD_TRANSFER_SPEED_RATE_UNIT_MASK (0x07U) -/*! @brief The bit shift for TIME VALUE field in TRANSFER SPEED */ -#define SD_TRANSFER_SPEED_TIME_VALUE_SHIFT (2U) -/*! @brief The bit mask for TIME VALUE field in TRANSFER SPEED */ -#define SD_TRANSFER_SPEED_TIME_VALUE_MASK (0x78U) -/*! @brief Read the value of FREQUENCY UNIT in TRANSFER SPEED field */ -#define SD_RD_TRANSFER_SPEED_RATE_UNIT(x) \ - (((x.transferSpeed) & SD_TRANSFER_SPEED_RATE_UNIT_MASK) >> SD_TRANSFER_SPEED_RATE_UNIT_SHIFT) -/*! @brief Read the value of TIME VALUE in TRANSFER SPEED field */ -#define SD_RD_TRANSFER_SPEED_TIME_VALUE(x) \ - (((x.transferSpeed) & SD_TRANSFER_SPEED_TIME_VALUE_MASK) >> SD_TRANSFER_SPEED_TIME_VALUE_SHIFT) - -/*! @brief SD card SCR register */ -typedef struct _sd_scr -{ - uint8_t scrStructure; /*!< SCR Structure [63:60] */ - uint8_t sdSpecification; /*!< SD memory card specification version [59:56] */ - uint16_t flags; /*!< SCR flags in _sd_scr_flag */ - uint8_t sdSecurity; /*!< Security specification supported [54:52] */ - uint8_t sdBusWidths; /*!< Data bus widths supported [51:48] */ - uint8_t extendedSecurity; /*!< Extended security support [46:43] */ - uint8_t commandSupport; /*!< Command support bits [33:32] 33-support CMD23, 32-support cmd20*/ - uint32_t reservedForManufacturer; /*!< reserved for manufacturer usage [31:0] */ -} sd_scr_t; - -/*! @brief MMC card product name length united as bytes. */ -#define MMC_PRODUCT_NAME_BYTES (6U) -/*! @brief MMC card CID register. */ -typedef struct _mmc_cid -{ - uint8_t manufacturerID; /*!< Manufacturer ID */ - uint16_t applicationID; /*!< OEM/Application ID */ - uint8_t productName[MMC_PRODUCT_NAME_BYTES]; /*!< Product name */ - uint8_t productVersion; /*!< Product revision */ - uint32_t productSerialNumber; /*!< Product serial number */ - uint8_t manufacturerData; /*!< Manufacturing date */ -} mmc_cid_t; - -/*! @brief MMC card CSD register. */ -typedef struct _mmc_csd -{ - uint8_t csdStructureVersion; /*!< CSD structure [127:126] */ - uint8_t systemSpecificationVersion; /*!< System specification version [125:122] */ - uint8_t dataReadAccessTime1; /*!< Data read access-time 1 [119:112] */ - uint8_t dataReadAccessTime2; /*!< Data read access-time 2 in CLOCK cycles (NSAC*100) [111:104] */ - uint8_t transferSpeed; /*!< Max. bus clock frequency [103:96] */ - uint16_t cardCommandClass; /*!< card command classes [95:84] */ - uint8_t readBlockLength; /*!< Max. read data block length [83:80] */ - uint16_t flags; /*!< Contain flags in _mmc_csd_flag */ - uint16_t deviceSize; /*!< Device size [73:62] */ - uint8_t readCurrentVddMin; /*!< Max. read current @ VDD min [61:59] */ - uint8_t readCurrentVddMax; /*!< Max. read current @ VDD max [58:56] */ - uint8_t writeCurrentVddMin; /*!< Max. write current @ VDD min [55:53] */ - uint8_t writeCurrentVddMax; /*!< Max. write current @ VDD max [52:50] */ - uint8_t deviceSizeMultiplier; /*!< Device size multiplier [49:47] */ - uint8_t eraseGroupSize; /*!< Erase group size [46:42] */ - uint8_t eraseGroupSizeMultiplier; /*!< Erase group size multiplier [41:37] */ - uint8_t writeProtectGroupSize; /*!< Write protect group size [36:32] */ - uint8_t defaultEcc; /*!< Manufacturer default ECC [30:29] */ - uint8_t writeSpeedFactor; /*!< Write speed factor [28:26] */ - uint8_t maxWriteBlockLength; /*!< Max. write data block length [25:22] */ - uint8_t fileFormat; /*!< File format [11:10] */ - uint8_t eccCode; /*!< ECC code [9:8] */ -} mmc_csd_t; - -/*! @brief MMC card Extended CSD register (unit: byte). */ -typedef struct _mmc_extended_csd -{ - uint32_t flags; - uint8_t SecureRemoveType; /*!< secure removal type[16]*/ - uint8_t enProductStateAware; /*!< product state awareness enablement[17]*/ - uint32_t maxPreLoadDataSize; /*!< max preload data size[21-18]*/ - uint32_t preLoadDataSize; /*!< pre-load data size[25-22]*/ - uint8_t ffuStatus; /*!< FFU status [26]*/ - uint8_t modeOperationCode; /*!< mode operation code[29]*/ - uint8_t modeConfig; /*!< mode config [30]*/ - uint8_t cacheCtrl; /*!< control to turn on/off cache[33]*/ - uint8_t pwroffNotify; /*!< power off notification[34]*/ - uint8_t packedCmdFailIndex; /*!< packed cmd fail index [35]*/ - uint8_t packedCmdStatus; /*!< packed cmd status[36]*/ - uint32_t contextConfig[4U]; /*!< context configuration[51-37]*/ - uint16_t extPartitionAttr; /*!< extended partitions attribut[53-52]*/ - uint16_t exceptEventStatus; /*!< exception events status[55-54]*/ - uint16_t exceptEventControl; /*!< exception events control[57-56]*/ - uint8_t toReleaseAddressedGroup; /*!< number of group to be released[58]*/ - uint8_t class6CmdCtrl; /*!< class 6 command control[59]*/ - uint8_t intTimeoutEmu; /*!< 1st initiallization after disabling sector size emu[60]*/ - uint8_t sectorSize; /*!< sector size[61] */ - uint8_t sectorSizeEmu; /*!< sector size emulation[62]*/ - uint8_t nativeSectorSize; /*!< native sector size[63]*/ - uint8_t periodWakeup; /*!< period wakeup [131]*/ - uint8_t tCASESupport; /*!< package case temperature is controlled[132]*/ - uint8_t productionStateAware; /*!< production state awareness[133]*/ - uint32_t enhanceUsrDataStartAddr; /*!< enhanced user data start addr [139-136]*/ - uint32_t enhanceUsrDataSize; /*!< enhanced user data area size[142-140]*/ - uint32_t generalPartitionSize[3]; /*!< general purpose partition size[154-143]*/ - uint8_t partitionAttribute; /*!< partition attribute [156]*/ - uint32_t maxEnhanceAreaSize; /*!< max enhance area size [159-157]*/ - uint8_t hpiManagementEn; /*!< HPI management [161]*/ - uint8_t writeReliabilityParameter; /*!< write reliability parameter register[166] */ - uint8_t writeReliabilitySet; /*!< write reliability setting register[167] */ - uint8_t rpmbSizeMult; /*!< RPMB size multi [168]*/ - uint8_t fwConfig; /*!< FW configuration[169]*/ - uint8_t userWPRegister; /*!< user write protect register[171] */ - uint8_t bootWPRegister; /*!< boot write protect register[173]*/ - uint8_t bootWPStatusRegister; /*!< boot write protect status register[174]*/ - uint8_t highDensityEraseGroupDefinition; /*!< High-density erase group definition [175] */ - uint8_t bootDataBusWidth; /*!< Boot bus width [177] */ - uint8_t bootConfigProtect; /*!< Boot config protection [178]*/ - uint8_t partitionConfig; /*!< Boot configuration [179] */ - uint8_t eraseMemoryContent; /*!< Erased memory content [181] */ - uint8_t dataBusWidth; /*!< Data bus width mode [183] */ - uint8_t highSpeedTiming; /*!< High-speed interface timing [185] */ - uint8_t powerClass; /*!< Power class [187] */ - uint8_t commandSetRevision; /*!< Command set revision [189] */ - uint8_t commandSet; /*!< Command set [191] */ - uint8_t extendecCsdVersion; /*!< Extended CSD revision [192] */ - uint8_t csdStructureVersion; /*!< CSD structure version [194] */ - uint8_t cardType; /*!< Card Type [196] */ - uint8_t ioDriverStrength; /*!< IO driver strength [197] */ - uint8_t OutofInterruptBusyTiming; /*!< out of interrupt busy timing [198] */ - uint8_t partitionSwitchTiming; /*!< partition switch timing [199] */ - uint8_t powerClass52MHz195V; /*!< Power Class for 52MHz @ 1.95V [200] */ - uint8_t powerClass26MHz195V; /*!< Power Class for 26MHz @ 1.95V [201] */ - uint8_t powerClass52MHz360V; /*!< Power Class for 52MHz @ 3.6V [202] */ - uint8_t powerClass26MHz360V; /*!< Power Class for 26MHz @ 3.6V [203] */ - uint8_t minimumReadPerformance4Bit26MHz; /*!< Minimum Read Performance for 4bit at 26MHz [205] */ - uint8_t minimumWritePerformance4Bit26MHz; /*!< Minimum Write Performance for 4bit at 26MHz [206] */ - uint8_t minimumReadPerformance8Bit26MHz4Bit52MHz; - /*!< Minimum read Performance for 8bit at 26MHz/4bit @52MHz [207] */ - uint8_t minimumWritePerformance8Bit26MHz4Bit52MHz; - /*!< Minimum Write Performance for 8bit at 26MHz/4bit @52MHz [208] */ - uint8_t minimumReadPerformance8Bit52MHz; /*!< Minimum Read Performance for 8bit at 52MHz [209] */ - uint8_t minimumWritePerformance8Bit52MHz; /*!< Minimum Write Performance for 8bit at 52MHz [210] */ - uint32_t sectorCount; /*!< Sector Count [215:212] */ - uint8_t sleepNotificationTimeout; /*!< sleep notification timeout [216]*/ - uint8_t sleepAwakeTimeout; /*!< Sleep/awake timeout [217] */ - uint8_t productionStateAwareTimeout; /*!< Production state awareness timeout [218]*/ - uint8_t sleepCurrentVCCQ; /*!< Sleep current (VCCQ) [219] */ - uint8_t sleepCurrentVCC; /*!< Sleep current (VCC) [220] */ - uint8_t highCapacityWriteProtectGroupSize; /*!< High-capacity write protect group size [221] */ - uint8_t reliableWriteSectorCount; /*!< Reliable write sector count [222] */ - uint8_t highCapacityEraseTimeout; /*!< High-capacity erase timeout [223] */ - uint8_t highCapacityEraseUnitSize; /*!< High-capacity erase unit size [224] */ - uint8_t accessSize; /*!< Access size [225] */ - uint8_t bootSizeMultiplier; /*!< Boot partition size [226] */ - uint8_t bootInformation; /*!< Boot information [228] */ - uint8_t secureTrimMultiplier; /*!< secure trim multiplier[229]*/ - uint8_t secureEraseMultiplier; /*!< secure erase multiplier[230]*/ - uint8_t secureFeatureSupport; /*!< secure feature support[231]*/ - uint32_t trimMultiplier; /*!< trim multiplier[232]*/ - uint8_t minReadPerformance8bitAt52MHZDDR; /*!< Minimum read performance for 8bit at DDR 52MHZ[234]*/ - uint8_t minWritePerformance8bitAt52MHZDDR; /*!< Minimum write performance for 8bit at DDR 52MHZ[235]*/ - uint8_t powerClass200MHZVCCQ130VVCC360V; /*!< power class for 200MHZ, at VCCQ= 1.3V,VCC=3.6V[236]*/ - uint8_t powerClass200MHZVCCQ195VVCC360V; /*!< power class for 200MHZ, at VCCQ= 1.95V,VCC=3.6V[237]*/ - uint8_t powerClass52MHZDDR195V; /*!< power class for 52MHZ,DDR at Vcc 1.95V[238]*/ - uint8_t powerClass52MHZDDR360V; /*!< power class for 52MHZ,DDR at Vcc 3.6V[239]*/ - uint8_t iniTimeoutAP; /*!< 1st initialization time after partitioning[241]*/ - uint32_t correctPrgSectorNum; /*!< correct prg sectors number[245-242]*/ - uint8_t bkOpsStatus; /*!< background operations status[246]*/ - uint8_t powerOffNotifyTimeout; /*!< power off notification timeout[247]*/ - uint8_t genericCMD6Timeout; /*!< generic CMD6 timeout[248]*/ - uint32_t cacheSize; /*!< cache size[252-249]*/ - uint8_t powerClass200MHZDDR360V; /*!< power class for 200MHZ, DDR at VCC=2.6V[253]*/ - uint32_t fwVer[2U]; /*!< fw VERSION [261-254]*/ - uint16_t deviveVer; /*!< device version[263-262]*/ - uint8_t optimalTrimSize; /*!< optimal trim size[264]*/ - uint8_t optimalWriteSize; /*!< optimal write size[265]*/ - uint8_t optimalReadSize; /*!< optimal read size[266]*/ - uint8_t preEolInfo; /*!< pre EOL information[267]*/ - uint8_t deviceLifeTimeEstimationA; /*!< device life time estimation typeA[268]*/ - uint8_t deviceLifeTimeEstimationB; /*!< device life time estimation typeB[269]*/ - uint32_t correctPrgFWSectorNum; /*!< number of FW sectors correctly programmed[305-302]*/ - uint32_t ffuArg; /*!< FFU argument[490-487]*/ - uint8_t operationCodeTimeout; /*!< operation code timeout[491]*/ - uint8_t supportMode; /*!< support mode [493]*/ - uint8_t extPartitionSupport; /*!< extended partition attribute support[494]*/ - uint8_t largeUnitSize; /*!< large unit size[495]*/ - uint8_t contextManageCap; /*!< context management capability[496]*/ - uint8_t tagResourceSize; /*!< tag resource size[497]*/ - uint8_t tagUnitSize; /*!< tag unit size[498]*/ - uint8_t maxPackedWriteCmd; /*!< max packed write cmd[500]*/ - uint8_t maxPackedReadCmd; /*!< max packed read cmd[501]*/ - uint8_t hpiFeature; /*!< HPI feature[503]*/ - uint8_t supportedCommandSet; /*!< Supported Command Sets [504] */ - uint8_t extSecurityCmdError; /*!< extended security commands error[505]*/ -} mmc_extended_csd_t; - -/*! @brief The bit shift for COMMAND SET field in SWITCH command. */ -#define MMC_SWITCH_COMMAND_SET_SHIFT (0U) -/*! @brief The bit mask for COMMAND set field in SWITCH command. */ -#define MMC_SWITCH_COMMAND_SET_MASK (0x00000007U) -/*! @brief The bit shift for VALUE field in SWITCH command */ -#define MMC_SWITCH_VALUE_SHIFT (8U) -/*! @brief The bit mask for VALUE field in SWITCH command */ -#define MMC_SWITCH_VALUE_MASK (0x0000FF00U) -/*! @brief The bit shift for BYTE INDEX field in SWITCH command */ -#define MMC_SWITCH_BYTE_INDEX_SHIFT (16U) -/*! @brief The bit mask for BYTE INDEX field in SWITCH command */ -#define MMC_SWITCH_BYTE_INDEX_MASK (0x00FF0000U) -/*! @brief The bit shift for ACCESS MODE field in SWITCH command */ -#define MMC_SWITCH_ACCESS_MODE_SHIFT (24U) -/*! @brief The bit mask for ACCESS MODE field in SWITCH command */ -#define MMC_SWTICH_ACCESS_MODE_MASK (0x03000000U) - -/*! @brief MMC Extended CSD configuration. */ -typedef struct _mmc_extended_csd_config -{ - mmc_command_set_t commandSet; /*!< Command set */ - uint8_t ByteValue; /*!< The value to set */ - uint8_t ByteIndex; /*!< The byte index in Extended CSD(mmc_extended_csd_index_t) */ - mmc_extended_csd_access_mode_t accessMode; /*!< Access mode */ -} mmc_extended_csd_config_t; - -#endif /* _FSL_SPECIFICATION_H_ */ diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/SConscript b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/SConscript deleted file mode 100644 index 0ed9537feb2..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/SConscript +++ /dev/null @@ -1,17 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -CPPPATH = [cwd] -src = Split(''' -fsl_sd.c -fsl_sdmmc.c -fsl_host.c -fsl_sd_event.c -''') -#src = Glob('*.c') - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_host.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_host.c deleted file mode 100644 index 8ed1f949bb6..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_host.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_host.h" -#include "fsl_sd_event.h" -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -static sdif_handle_t g_sdifHandle; -static uint32_t g_sdifDmaTable[SDIF_DMA_TABLE_WORDS * 2]; -//extern volatile uint32_t g_timeMilliseconds; -static volatile bool g_sdifTransferSuccessFlag = true; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Delay some time united in milliseconds. */ -static void Delay(uint32_t milliseconds) -{ - uint32_t startTime = rt_tick_get() * 1000 / RT_TICK_PER_SECOND;//g_timeMilliseconds; - uint32_t periodTime = 0; - while (periodTime < milliseconds) - { - periodTime = rt_tick_get() * 1000 / RT_TICK_PER_SECOND - startTime; - } -} - -status_t CardInsertDetect(HOST_TYPE *hostBase) -{ - uint32_t startTime; - uint32_t elapsedTime; - uint32_t timeoutMilliseconds = RT_TICK_PER_SECOND;//EVENT_TIMEOUT_CARD_DETECT; - - /* Wait card insert */ - - if (!timeoutMilliseconds) - { - while (SDIF_DetectCardInsert(hostBase, false) != 0U) - ; - } - else - { - startTime = rt_tick_get(); - do - { - elapsedTime = (rt_tick_get() - startTime); - } while ((SDIF_DetectCardInsert(hostBase, false)) && (elapsedTime < timeoutMilliseconds)); - if (elapsedTime > timeoutMilliseconds) - { - return kStatus_Fail; - } - } - - /* Enable the card power */ - SDIF_EnableCardPower(hostBase, true); - /* Delay some time to make card stable. */ - Delay(500U); - - return kStatus_Success; -} - -/* Transfer complete callback function. */ -static void SDIF_TransferCompleteCallback(SDIF_Type *base, void *handle, status_t status, void *userData) -{ - /* receive the right status, notify the event */ - if (status == kStatus_Success) - { - g_sdifTransferSuccessFlag = true; - } - else - { - g_sdifTransferSuccessFlag = false; - } - - EVENT_Notify(kEVENT_TransferComplete); -} - -/* User defined transfer function. */ -static status_t SDIF_TransferFunction(SDIF_Type *base, sdif_transfer_t *content) -{ - status_t error = kStatus_Success; - - sdif_dma_config_t dmaConfig; - - memset(g_sdifDmaTable, 0, sizeof(g_sdifDmaTable)); - memset(&dmaConfig, 0, sizeof(dmaConfig)); - - /* user DMA mode transfer data */ - if (content->data != NULL) - { - dmaConfig.enableFixBurstLen = false; - dmaConfig.mode = kSDIF_DualDMAMode; - dmaConfig.dmaDesBufferStartAddr = g_sdifDmaTable; - dmaConfig.dmaDesBufferLen = SDIF_DMA_TABLE_WORDS; - dmaConfig.dmaDesSkipLen = 0U; - } - - do - { - error = SDIF_TransferNonBlocking(base, &g_sdifHandle, &dmaConfig, content); - } while (error == kStatus_SDIF_SyncCmdTimeout); - - if ((error != kStatus_Success) || (false == EVENT_Wait(kEVENT_TransferComplete, EVENT_TIMEOUT_TRANSFER_COMPLETE)) || - (!g_sdifTransferSuccessFlag)) - { - error = kStatus_Fail; - } - - EVENT_Delete(kEVENT_TransferComplete); - - return error; -} - -status_t HOST_Init(void *host) -{ - sdif_transfer_callback_t sdifCallback = {0}; - sdif_host_t *sdifHost = (sdif_host_t *)host; - - /* Sets callback in host driver. */ - EVENT_InitTimer(); - - /* Initialize SDIF. */ - sdifHost->config.endianMode = kHOST_EndianModeLittle; - sdifHost->config.responseTimeout = 0xFFU; - sdifHost->config.cardDetDebounce_Clock = 0xFFFFFFU; - sdifHost->config.dataTimeout = 0xFFFFFFU; - SDIF_Init(sdifHost->base, &(sdifHost->config)); - - /* Set callback for SDHC driver. */ - sdifCallback.TransferComplete = SDIF_TransferCompleteCallback; - /* Create handle for SDHC driver */ - SDIF_TransferCreateHandle(sdifHost->base, &g_sdifHandle, &sdifCallback, NULL); - - /* Create transfer complete event. */ - if (false == EVENT_Create(kEVENT_TransferComplete)) - { - return kStatus_Fail; - } - - /* Define transfer function. */ - sdifHost->transfer = SDIF_TransferFunction; - - /* Enable the card power here for mmc card case, because mmc card don't need card detect*/ - SDIF_EnableCardPower(sdifHost->base, true); - - return kStatus_Success; -} - -void HOST_Deinit(void *host) -{ - sdif_host_t *sdifHost = (sdif_host_t *)host; - SDIF_Deinit(sdifHost->base); -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_mmc.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_mmc.c deleted file mode 100644 index 88fac6e295a..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_mmc.c +++ /dev/null @@ -1,2212 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include "fsl_card.h" -#include "fsl_sdmmc.h" - -/******************************************************************************* - * Definitons - ******************************************************************************/ -/*! @brief The divide value used to avoid float point calculation when calculate max speed in normal mode. */ -#define DIVIDER_IN_TRANSFER_SPEED (10U) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Send SELECT_CARD command to set the card enter or exit transfer state. - * - * @param card Card descriptor. - * @param isSelected True to enter transfer state. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t inline MMC_SelectCard(mmc_card_t *card, bool isSelected); - -/*! - * @brief Wait write process complete. - * - * @param card Card descriptor. - * @retval kStatus_Timeout Operation timeout. - * @retval kStatus_Success Operate successfully. - */ -static status_t inline MMC_WaitWriteComplete(mmc_card_t *card); - -/*! - * @brief Send SET_BLOCK_COUNT command. - * - * @param card Card descriptor. - * @param blockCount Block count. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t inline MMC_SetBlockCount(mmc_card_t *card, uint32_t blockCount); - -/*! - * @brief Send GO_IDLE command to reset all cards to idle state - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t inline MMC_GoIdle(mmc_card_t *card); - -/*! - * @brief Send STOP_TRANSMISSION command to card to stop ongoing data transferring. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_StopTransmission(mmc_card_t *card); - -/*! - * @brief Send SET_BLOCK_SIZE command to set the block length in bytes for MMC cards. - * - * @param card Card descriptor. - * @param blockSize Block size. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t inline MMC_SetBlockSize(mmc_card_t *card, uint32_t blockSize); - -/*! - * @brief switch voltage. - * - * @param card Card descriptor. - * @param opcode use to send operation condition - * @retval kStatus_SDMMC_HostNotSupport Host doesn't support the voltage window to access the card. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SwitchVoltage(mmc_card_t *card, uint32_t *opCode); - -/*! - * @brief Send SEND_OPERATION_CONDITION command to validate if the card support host's voltage window - * - * @param card Card descriptor. - * @param cmd argument - * @retval kStatus_SDMMC_TransferFailed Transfers failed. - * @retval kStatus_Timeout Operation timeout. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SendOperationCondition(mmc_card_t *card, uint32_t arg); - -/*! - * @brief Send SET_RCA command to set the relative address of the card. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SetRelativeAddress(mmc_card_t *card); - -/*! - * @brief Decode CSD register content. - * - * @param card Card descriptor. - * @param rawCsd raw CSD register content. - */ -static void MMC_DecodeCsd(mmc_card_t *card, uint32_t *rawCsd); - -/*! - * @brief Set the card to max transfer speed in non-high speed mode. - * - * @param card Card descriptor. - */ -static void MMC_SetMaxFrequency(mmc_card_t *card); - -/*! - * @brief Set erase unit size of the card - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure Extended CSD failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SetMaxEraseUnitSize(mmc_card_t *card); - -/*! - * @brief Send SWITCH command to set the specific byte in Extended CSD. - * - * Example: - @code - mmc_extended_csd_config_t config; - config.accessMode = kMMC_ExtendedCsdAccessModeSetBits; - config.ByteIndex = 1U; - config.ByteValue = 0x033U; - config.commandSet = kMMC_CommandSetStandard; - MMC_SetExtendedCsdConfig(card, &config); - @endcode - * - * @param card Card descriptor. - * @param config Configuration for Extended CSD. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_WaitWriteCompleteFailed Wait write complete failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SetExtendedCsdConfig(mmc_card_t *card, const mmc_extended_csd_config_t *config); - -/*! - * @brief Decode the Extended CSD register - * - * @param card Card descriptor. - * @param rawExtendedCsd Raw extended CSD register content. - */ -static void MMC_DecodeExtendedCsd(mmc_card_t *card, uint32_t *rawExtendedCsd); - -/*! - * @brief Send SEND_EXTENDED_CSD command to get the content of the Extended CSD register - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SendExtendedCsd(mmc_card_t *card); - -/*! - * @brief Set the power class of the card at specific bus width and host intended voltage window. - * - * @param card Card descriptor. - * @param width Data bus width. - * @return The power class value. - */ -static status_t MMC_SetPowerClass(mmc_card_t *card, mmc_data_bus_width_t width); - -/*! - * @brief Send test pattern to get the functional pin in the MMC bus - * - * @param card Card descriptor. - * @param blockSize Test pattern block size. - * @param pattern Test pattern data buffer. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SendTestPattern(mmc_card_t *card, uint32_t blockSize, uint32_t *pattern); - -/*! - * @brief Receive test pattern reversed by the card. - * - * @param card Card descriptor. - * @param blockSize Test pattern block size. - * @param pattern Test pattern data buffer. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_ReceiveTestPattern(mmc_card_t *card, uint32_t blockSize, uint32_t *pattern); - -/*! - * @brief Bus test procedure to get the functional data pin in the bus - * - * @param card Card descriptor. - * @param width Data bus width. - * @retval kStatus_SDMMC_SendTestPatternFailed Send test pattern failed. - * @retval kStatus_SDMMC_ReceiveTestPatternFailed Receive test pattern failed. - * @retval kStatus_Fail Test failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_TestDataBusWidth(mmc_card_t *card, mmc_data_bus_width_t width); - -/*! - * @brief Send SET_BUS_WIDTH command to set the bus width. - * - * @param card Card descriptor. - * @param width Data bus width. - * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure extended CSD failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SetDataBusWidth(mmc_card_t *card, mmc_data_bus_width_t width); - -/*! - * @brief Set max the bus width automatically - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_SetDataBusWidthFailed switch fail - * @retval kStatus_Success switch success - */ -static status_t MMC_SetMaxDataBusWidth(mmc_card_t *card); - -/*! - * @brief Switch the card to high speed mode - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure extended CSD failed. - * @retval kStatus_SDMMC_CardNotSupport Card doesn't support high speed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SelectBusTiming(mmc_card_t *card); - -/*! - * @brief select card driver strength - * - * @param card Card descriptor. - * @retval kStatus_Success switch success - * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed , config extend csd register fail - */ -static status_t MMC_SelectCardDriverStrength(mmc_card_t *card, uint8_t driverStrength); -/*! - * @brief Decode CID register - * - * @param card Card descriptor. - * @param rawCid Raw CID register content. - */ -static void MMC_DecodeCid(mmc_card_t *card, uint32_t *rawCid); - -/*! - * @brief Send ALL_SEND_CID command - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_AllSendCid(mmc_card_t *card); - -/*! - * @brief Send SEND_CSD command to get CSD from card - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SendCsd(mmc_card_t *card); - -/*! - * @brief Check if the block range accessed is within current partition. - * - * @param card Card descriptor. - * @param startBlock Start block to access. - * @param blockCount Block count to access. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_CheckBlockRange(mmc_card_t *card, uint32_t startBlock, uint32_t blockCount); - -/*! - * @brief Check if the erase group range accessed is within current partition. - * - * @param card Card descriptor. - * @param startGroup Start group to access. - * @param endGroup End group to access. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_CheckEraseGroupRange(mmc_card_t *card, uint32_t startGroup, uint32_t endGroup); - -/*! - * @brief MMC excute tuning function. - * - * @param card Card descriptor. - */ -static status_t inline MMC_ExecuteTuning(mmc_card_t *card); - -/*! - * @brief Read data from specific MMC card - * - * @param card Card descriptor. - * @param buffer Buffer to save received data. - * @param startBlock Start block to read. - * @param blockSize Block size. - * @param blockCount Block count to read. - * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. - * @retval kStatus_SDMMC_WaitWriteCompleteFailed Wait write complete failed. - * @retval kStatus_SDMMC_SetBlockCountFailed Set block count failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_Read( - mmc_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount); - -/*! - * @brief Write data from specific MMC card - * - * @param card Card descriptor. - * @param buffer Buffer to hold the data to write. - * @param startBlock Start block to write. - * @param blockSize Block size. - * @param blockCount Block count to write. - * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. - * @retval kStatus_SDMMC_SetBlockCountFailed Set block count failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_Write( - mmc_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount); - -/*! - * @brief card transfer function wrapper - * This function is used to do tuning before transfer if the cmd won't casue re-tuning - * request, then you can call host transfer function directly - * @param base HOST peripheral base address. - * @param transfer function pointer - * @param transfer content - * @param retry times - * @retval kStatus_SDMMC_TransferFailed transfer fail - * @retval kStatus_SDMMC_TuningFail tuning fail - * @retval kStatus_Success transfer success - */ -static status_t MMC_Transfer(mmc_card_t *card, HOST_TRANSFER *content, uint32_t retry); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Frequency unit defined in TRANSFER SPEED field in CSD */ -static const uint32_t g_transerSpeedFrequencyUnit[] = {100000U, 1000000U, 10000000U, 100000000U}; -/* The multiplying value defined in TRANSFER SPEED field in CSD */ -static const uint32_t g_transerSpeedMultiplierFactor[] = {0U, 10U, 12U, 13U, 15U, 20U, 26U, 30U, - 35U, 40U, 45U, 52U, 55U, 60U, 70U, 80U}; -/******************************************************************************* - * Code - ******************************************************************************/ -static status_t inline MMC_SelectCard(mmc_card_t *card, bool isSelected) -{ - assert(card); - - return SDMMC_SelectCard(card->host.base, card->host.transfer, card->relativeAddress, isSelected); -} - -static status_t inline MMC_SetBlockCount(mmc_card_t *card, uint32_t blockCount) -{ - assert(card); - - return SDMMC_SetBlockCount(card->host.base, card->host.transfer, blockCount); -} - -static status_t inline MMC_GoIdle(mmc_card_t *card) -{ - assert(card); - - return SDMMC_GoIdle(card->host.base, card->host.transfer); -} - -static status_t inline MMC_SetBlockSize(mmc_card_t *card, uint32_t blockSize) -{ - assert(card); - - return SDMMC_SetBlockSize(card->host.base, card->host.transfer, blockSize); -} - -static status_t MMC_ExecuteTuning(mmc_card_t *card) -{ - assert(card); - - uint32_t blockSize = 0U; - - if (card->flags & kMMC_DataBusWidth4BitFlag) - { - blockSize = 64U; - } - else if (card->flags & kMMC_DataBusWidth8BitFlag) - { - blockSize = 128U; - } - else - { - /* do not need tuning in this situation */ - return kStatus_Success; - } - - return SDMMC_ExecuteTuning(card->host.base, kMMC_SendTuningBlock, blockSize); -} - -static status_t MMC_Transfer(mmc_card_t *card, HOST_TRANSFER *content, uint32_t retry) -{ - assert(card->host.transfer); - assert(content); - status_t error; - - do - { - error = card->host.transfer(card->host.base, content); - if ((error == HOST_RETUNING_REQUEST) && - ((card->currentTiming == kMMC_HighSpeed200Timing) || (card->currentTiming == kMMC_HighSpeed400Timing))) - { - /* execute re-tuning */ - if (MMC_ExecuteTuning(card) != kStatus_Success) - { - error = kStatus_SDMMC_TuningFail; - break; - } - else - { - continue; - } - } - else if (error != kStatus_Success) - { - error = kStatus_SDMMC_TransferFailed; - } - else - { - } - - if (retry != 0U) - { - retry--; - } - else - { - break; - } - - } while ((error != kStatus_Success) && (error != kStatus_SDMMC_TuningFail)); - - return error; -} - -static status_t inline MMC_WaitWriteComplete(mmc_card_t *card) -{ - assert(card); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - - command.index = kSDMMC_SendStatus; - command.argument = card->relativeAddress << 16U; - command.responseType = kCARD_ResponseTypeR1; - command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; - - do - { - content.command = &command; - content.data = 0U; - if (kStatus_Success != MMC_Transfer(card, &content, 1U)) - { - return kStatus_SDMMC_TransferFailed; - } - - if ((command.response[0U] & kSDMMC_R1ReadyForDataFlag) && - (SDMMC_R1_CURRENT_STATE(command.response[0U]) != kSDMMC_R1StateProgram)) - { - break; - } - } while (true); - - return kStatus_Success; -} - -static status_t MMC_StopTransmission(mmc_card_t *card) -{ - assert(card); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - - command.index = kSDMMC_StopTransmission; - command.argument = 0U; - command.type = kCARD_CommandTypeAbort; - command.responseType = kCARD_ResponseTypeR1b; - command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; - - content.command = &command; - content.data = 0U; - if (kStatus_Success != MMC_Transfer(card, &content, 2U)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -static status_t MMC_SwitchVoltage(mmc_card_t *card, uint32_t *opCode) -{ - mmc_voltage_window_t tempVoltage; - /* Get host's voltage window. */ - if (((card->host.capability.flags & kHOST_SupportV330) || (card->host.capability.flags & kHOST_SupportV300)) && - (card->ocr & MMC_OCR_V270TO360_MASK) && ((card->hostVoltageWindow == kMMC_VoltageWindowNone) || - (card->hostVoltageWindow == kMMC_VoltageWindows270to360))) - { - /* Save host intended voltage range */ - tempVoltage = kMMC_VoltageWindows270to360; - /* set the opcode */ - *opCode = MMC_OCR_V270TO360_MASK; - /*do not need switch voltage here*/ - HOST_SWITCH_VOLTAGE180V(card->host.base, false); - } - - if ((card->host.capability.flags & kHOST_SupportV180) && (card->ocr & MMC_OCR_V170TO195_MASK) && - ((card->hostVoltageWindow == kMMC_VoltageWindowNone) || - (card->hostVoltageWindow == kMMC_VoltageWindow170to195))) - { - /* Save host intended voltage range */ - tempVoltage = kMMC_VoltageWindow170to195; - /* set the opcode */ - *opCode = MMC_OCR_V170TO195_MASK; - /*switch voltage to 1.8V here*/ - HOST_SWITCH_VOLTAGE180V(card->host.base, true); - } - - card->hostVoltageWindow = tempVoltage; - /* reserve 1.2V voltage case */ - - return kStatus_Success; -} - -static status_t MMC_SendOperationCondition(mmc_card_t *card, uint32_t arg) -{ - assert(card); - assert(card->host.transfer); - - HOST_COMMAND command = {0}; - HOST_TRANSFER content = {0}; - status_t error; - uint32_t i = FSL_SDMMC_MAX_VOLTAGE_RETRIES; - - /* Send CMD1 with the intended voltage range in the argument(either 0x00FF8000 or 0x00000080) */ - command.index = kMMC_SendOperationCondition; - command.argument = arg; - command.responseType = kCARD_ResponseTypeR3; - - content.command = &command; - content.data = NULL; - do - { - if (kStatus_Success != card->host.transfer(card->host.base, &content)) - { - return kStatus_SDMMC_TransferFailed; - } - - if (arg == 0U) - { - error = kStatus_Success; - card->ocr = command.response[0U]; - } - /* Repeat CMD1 until the busy bit is cleared. */ - else if (!(command.response[0U] & MMC_OCR_BUSY_MASK)) - { - error = kStatus_Timeout; - } - else - { - error = kStatus_Success; - } - } while ((i--) && (error != kStatus_Success)); - - return error; -} - -static status_t MMC_SetRelativeAddress(mmc_card_t *card) -{ - assert(card); - assert(card->host.transfer); - - HOST_COMMAND command = {0}; - HOST_TRANSFER content = {0}; - - /* Send CMD3 with a chosen relative address, with value greater than 1 */ - command.index = kMMC_SetRelativeAddress; - command.argument = (MMC_DEFAULT_RELATIVE_ADDRESS << 16U); - command.responseType = kCARD_ResponseTypeR1; - - content.command = &command; - content.data = NULL; - if ((kStatus_Success == card->host.transfer(card->host.base, &content)) || - (!((command.response[0U]) & kSDMMC_R1ErrorAllFlag))) - { - card->relativeAddress = MMC_DEFAULT_RELATIVE_ADDRESS; - return kStatus_Success; - } - - return kStatus_SDMMC_TransferFailed; -} - -static void MMC_DecodeCsd(mmc_card_t *card, uint32_t *rawCsd) -{ - assert(card); - assert(rawCsd); - - mmc_csd_t *csd; - uint32_t multiplier; - - csd = &(card->csd); - csd->csdStructureVersion = (uint8_t)((rawCsd[3U] & 0xC0000000U) >> 30U); - csd->systemSpecificationVersion = (uint8_t)((rawCsd[3U] & 0x3C000000U) >> 26U); - csd->dataReadAccessTime1 = (uint8_t)((rawCsd[3U] & 0xFF0000U) >> 16U); - csd->dataReadAccessTime2 = (uint8_t)((rawCsd[3U] & 0xFF00U) >> 8U); - csd->transferSpeed = (uint8_t)(rawCsd[3U] & 0xFFU); - csd->cardCommandClass = (uint16_t)((rawCsd[2U] & 0xFFF00000U) >> 20U); - /* Max block length read/write one time */ - csd->readBlockLength = (uint8_t)((rawCsd[2U] & 0xF0000U) >> 16U); - if (rawCsd[2U] & 0x8000U) - { - csd->flags |= kMMC_CsdReadBlockPartialFlag; - } - if (rawCsd[2U] & 0x4000U) - { - csd->flags |= kMMC_CsdWriteBlockMisalignFlag; - } - if (rawCsd[2U] & 0x2000U) - { - csd->flags |= kMMC_CsdReadBlockMisalignFlag; - } - if (rawCsd[2U] & 0x1000U) - { - csd->flags |= kMMC_CsdDsrImplementedFlag; - } - csd->deviceSize = (uint16_t)(((rawCsd[2U] & 0x3FFU) << 2U) + ((rawCsd[1U] & 0xC0000000U) >> 30U)); - csd->readCurrentVddMin = (uint8_t)((rawCsd[1U] & 0x38000000U) >> 27U); - csd->readCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x07000000U) >> 24U); - csd->writeCurrentVddMin = (uint8_t)((rawCsd[1U] & 0x00E00000U) >> 21U); - csd->writeCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x001C0000U) >> 18U); - csd->deviceSizeMultiplier = (uint8_t)((rawCsd[1U] & 0x00038000U) >> 15U); - csd->eraseGroupSize = (uint8_t)((rawCsd[1U] & 0x00007C00U) >> 10U); - csd->eraseGroupSizeMultiplier = (uint8_t)((rawCsd[1U] & 0x000003E0U) >> 5U); - csd->writeProtectGroupSize = (uint8_t)(rawCsd[1U] & 0x0000001FU); - if (rawCsd[0U] & 0x80000000U) - { - csd->flags |= kMMC_CsdWriteProtectGroupEnabledFlag; - } - csd->defaultEcc = (uint8_t)((rawCsd[0U] & 0x60000000U) >> 29U); - csd->writeSpeedFactor = (uint8_t)((rawCsd[0U] & 0x1C000000U) >> 26U); - csd->maxWriteBlockLength = (uint8_t)((rawCsd[0U] & 0x03C00000U) >> 22U); - if (rawCsd[0U] & 0x00200000U) - { - csd->flags |= kMMC_CsdWriteBlockPartialFlag; - } - if (rawCsd[0U] & 0x00010000U) - { - csd->flags |= kMMC_ContentProtectApplicationFlag; - } - if (rawCsd[0U] & 0x00008000U) - { - csd->flags |= kMMC_CsdFileFormatGroupFlag; - } - if (rawCsd[0U] & 0x00004000U) - { - csd->flags |= kMMC_CsdCopyFlag; - } - if (rawCsd[0U] & 0x00002000U) - { - csd->flags |= kMMC_CsdPermanentWriteProtectFlag; - } - if (rawCsd[0U] & 0x00001000U) - { - csd->flags |= kMMC_CsdTemporaryWriteProtectFlag; - } - csd->fileFormat = (uint8_t)((rawCsd[0U] & 0x00000C00U) >> 10U); - csd->eccCode = (uint8_t)((rawCsd[0U] & 0x00000300U) >> 8U); - - /* Calculate the device total block count. */ - /* For the card capacity of witch higher than 2GB, the maximum possible value should be set to this register - is 0xFFF. */ - if (card->csd.deviceSize != 0xFFFU) - { - multiplier = (2U << (card->csd.deviceSizeMultiplier + 2U - 1U)); - card->userPartitionBlocks = (((card->csd.deviceSize + 1U) * multiplier) / FSL_SDMMC_DEFAULT_BLOCK_SIZE); - } - else - { - card->flags |= kMMC_SupportHighCapacityFlag; - } - card->blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; -} - -static void MMC_SetMaxFrequency(mmc_card_t *card) -{ - assert(card); - - uint32_t frequencyUnit; - uint32_t multiplierFactor; - uint32_t maxBusClock_Hz; - - /* g_fsdhcCommandUnitInTranSpeed and g_transerSpeedMultiplierFactor are used to calculate the max speed in normal - mode not high speed mode. - For cards supporting version 4.0, 4.1, and 4.2 of the specification, the value shall be 20MHz(0x2A). - For cards supporting version 4.3, the value shall be 26 MHz (0x32H). In High speed mode, the max - frequency is decided by CARD_TYPE in Extended CSD. */ - frequencyUnit = g_transerSpeedFrequencyUnit[READ_MMC_TRANSFER_SPEED_FREQUENCY_UNIT(card->csd)]; - multiplierFactor = g_transerSpeedMultiplierFactor[READ_MMC_TRANSFER_SPEED_MULTIPLIER(card->csd)]; - maxBusClock_Hz = (frequencyUnit * multiplierFactor) / DIVIDER_IN_TRANSFER_SPEED; - card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, maxBusClock_Hz); -} - -static status_t MMC_SetMaxEraseUnitSize(mmc_card_t *card) -{ - assert(card); - - uint32_t erase_group_size; - uint32_t erase_group_multiplier; - mmc_extended_csd_config_t extendedCsdconfig; - - if (((!(card->flags & kMMC_SupportHighCapacityFlag)) || (card->extendedCsd.highCapacityEraseUnitSize == 0)) || - (card->extendedCsd.highCapacityEraseTimeout == 0)) - { - erase_group_size = card->csd.eraseGroupSize; - erase_group_multiplier = card->csd.eraseGroupSizeMultiplier; - card->eraseGroupBlocks = ((erase_group_size + 1U) * (erase_group_multiplier + 1U)); - } - else - { - /* Erase Unit Size = 512Kbyte * HC_ERASE_GRP_SIZE. Block size is 512 bytes. */ - card->eraseGroupBlocks = (card->extendedCsd.highCapacityEraseUnitSize * 1024U); - /* Enable high capacity erase unit size. */ - extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeSetBits; - extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexEraseGroupDefinition; - extendedCsdconfig.ByteValue = 0x01U; /* The high capacity erase unit size enable bit is bit 0 */ - extendedCsdconfig.commandSet = kMMC_CommandSetStandard; - if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) - { - return kStatus_SDMMC_ConfigureExtendedCsdFailed; - } - } - - return kStatus_Success; -} - -static status_t MMC_SetExtendedCsdConfig(mmc_card_t *card, const mmc_extended_csd_config_t *config) -{ - assert(card); - assert(card->host.transfer); - assert(config); - - uint32_t parameter = 0U; - HOST_COMMAND command = {0}; - HOST_TRANSFER content = {0}; - - parameter |= ((uint32_t)(config->commandSet) << MMC_SWITCH_COMMAND_SET_SHIFT); - parameter |= ((uint32_t)(config->ByteValue) << MMC_SWITCH_VALUE_SHIFT); - parameter |= ((uint32_t)(config->ByteIndex) << MMC_SWITCH_BYTE_INDEX_SHIFT); - parameter |= ((uint32_t)(config->accessMode) << MMC_SWITCH_ACCESS_MODE_SHIFT); - - command.index = kMMC_Switch; - command.argument = parameter; - command.responseType = kCARD_ResponseTypeR1b; /* Send switch command to set the pointed byte in Extended CSD. */ - - content.command = &command; - content.data = NULL; - if (kStatus_Success != MMC_Transfer(card, &content, 2U)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* Wait for the card write process complete because of that card read process and write process use one buffer. */ - if (kStatus_Success != MMC_WaitWriteComplete(card)) - { - return kStatus_SDMMC_WaitWriteCompleteFailed; - } - - return kStatus_Success; -} - -static void MMC_DecodeExtendedCsd(mmc_card_t *card, uint32_t *rawExtendedCsd) -{ - assert(card); - assert(rawExtendedCsd); - - uint8_t *buffer = (uint8_t *)rawExtendedCsd; - mmc_extended_csd_t *extendedCsd = &(card->extendedCsd); - - /* Extended CSD is transferred as a data block from least byte indexed 0. */ - extendedCsd->highDensityEraseGroupDefinition = buffer[175U]; - extendedCsd->bootDataBusWidth = buffer[177U]; - extendedCsd->partitionConfig = buffer[179U]; - extendedCsd->eraseMemoryContent = buffer[181U]; - extendedCsd->dataBusWidth = buffer[183U]; - extendedCsd->highSpeedTiming = buffer[185U]; - extendedCsd->powerClass = buffer[187U]; - extendedCsd->commandSetRevision = buffer[189U]; - extendedCsd->commandSet = buffer[191U]; - extendedCsd->extendecCsdVersion = buffer[192U]; - extendedCsd->csdStructureVersion = buffer[194U]; - - extendedCsd->cardType = buffer[196U]; - /* This field define the type of the card. The only currently valid values for this field are 0x01 and 0x03. */ - card->flags |= extendedCsd->cardType; - - extendedCsd->ioDriverStrength = buffer[197U]; - - extendedCsd->powerClass52MHz195V = buffer[200U]; - extendedCsd->powerClass26MHz195V = buffer[201U]; - extendedCsd->powerClass52MHz360V = buffer[202U]; - extendedCsd->powerClass26MHz360V = buffer[203U]; - extendedCsd->powerClass200MHZVCCQ130VVCC360V = buffer[236U]; - extendedCsd->powerClass200MHZVCCQ195VVCC360V = buffer[237U]; - extendedCsd->powerClass52MHZDDR195V = buffer[238U]; - extendedCsd->powerClass52MHZDDR360V = buffer[239U]; - extendedCsd->powerClass200MHZDDR360V = buffer[253U]; - extendedCsd->minimumReadPerformance4Bit26MHz = buffer[205U]; - extendedCsd->minimumWritePerformance4Bit26MHz = buffer[206U]; - extendedCsd->minimumReadPerformance8Bit26MHz4Bit52MHz = buffer[207U]; - extendedCsd->minimumWritePerformance8Bit26MHz4Bit52MHz = buffer[208U]; - extendedCsd->minimumReadPerformance8Bit52MHz = buffer[209U]; - extendedCsd->minimumWritePerformance8Bit52MHz = buffer[210U]; - extendedCsd->minReadPerformance8bitAt52MHZDDR = buffer[234U]; - extendedCsd->minWritePerformance8bitAt52MHZDDR = buffer[235U]; - /* Get user partition size. */ - extendedCsd->sectorCount = ((((uint32_t)buffer[215U]) << 24U) + (((uint32_t)buffer[214U]) << 16U) + - (((uint32_t)buffer[213U]) << 8U) + (uint32_t)buffer[212U]); - if (card->flags & kMMC_SupportHighCapacityFlag) - { - card->userPartitionBlocks = card->extendedCsd.sectorCount; - } - - extendedCsd->sleepAwakeTimeout = buffer[217U]; - extendedCsd->sleepCurrentVCCQ = buffer[219U]; - extendedCsd->sleepCurrentVCC = buffer[220U]; - extendedCsd->highCapacityWriteProtectGroupSize = buffer[221U]; - extendedCsd->reliableWriteSectorCount = buffer[222U]; - extendedCsd->highCapacityEraseTimeout = buffer[223U]; - extendedCsd->highCapacityEraseUnitSize = buffer[224U]; - extendedCsd->accessSize = buffer[225U]; - - /* Get boot partition size. */ - extendedCsd->bootSizeMultiplier = buffer[226U]; - card->bootPartitionBlocks = ((128U * 1024U * extendedCsd->bootSizeMultiplier) / FSL_SDMMC_DEFAULT_BLOCK_SIZE); - - /* Check if card support alternate boot. */ - extendedCsd->bootInformation = buffer[228U]; - if (extendedCsd->bootInformation & kMMC_SupportAlternateBoot) - { - card->flags |= kMMC_SupportAlternateBootFlag; - } - else if (extendedCsd->bootInformation & kMMC_SupportDDRBootFlag) - { - card->flags |= kMMC_SupportDDRBootFlag; - } - else if (extendedCsd->bootInformation & kMMC_SupportHighSpeedBoot) - { - card->flags |= kMMC_SupportHighSpeedBootFlag; - } - else - { - } - /* cache size unit 1kb */ - extendedCsd->cacheSize = (((uint32_t)buffer[252U]) << 24) | (((uint32_t)buffer[251U]) << 16) | - (((uint32_t)buffer[250U]) << 8) | (((uint32_t)buffer[249U])); - - extendedCsd->supportedCommandSet = buffer[504U]; -} - -static status_t MMC_SendExtendedCsd(mmc_card_t *card) -{ - assert(card); - assert(card->host.transfer); - - HOST_COMMAND command = {0}; - HOST_TRANSFER content = {0}; - HOST_DATA data = {0}; - uint32_t i; - - command.index = kMMC_SendExtendedCsd; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeR1; - - data.blockCount = 1U; - data.blockSize = MMC_EXTENDED_CSD_BYTES; - data.rxData = card->rawExtendedCsd; - - content.command = &command; - content.data = &data; - if ((kStatus_Success == card->host.transfer(card->host.base, &content)) && - (!(command.response[0U] & kSDMMC_R1ErrorAllFlag))) - { - /* The response is from bit 127:8 in R2, corresponding to command.response[3][31:0] to - command.response[0U][31:8] */ - for (i = 0U; i < MMC_EXTENDED_CSD_BYTES / 4U; i++) - { - switch (card->host.config.endianMode) - { - case kHOST_EndianModeLittle: - /* Doesn't need to switch byte sequence when decode bytes as little endian sequence. */ - break; - case kHOST_EndianModeBig: - /* In big endian mode, the SD bus byte transferred first is the byte stored in highest position - in a word which cause 4 byte's sequence in a word is not consistent with their original sequence - from card. */ - card->rawExtendedCsd[i] = SWAP_WORD_BYTE_SEQUENCE(card->rawExtendedCsd[i]); - break; - case kHOST_EndianModeHalfWordBig: - card->rawExtendedCsd[i] = SWAP_HALF_WROD_BYTE_SEQUENCE(card->rawExtendedCsd[i]); - break; - default: - return kStatus_SDMMC_NotSupportYet; - } - } - MMC_DecodeExtendedCsd(card, card->rawExtendedCsd); - - return kStatus_Success; - } - - return kStatus_SDMMC_TransferFailed; -} - -static status_t MMC_SetPowerClass(mmc_card_t *card, mmc_data_bus_width_t width) -{ - assert(card); - - uint8_t mask = 0, shift = 0U; - uint8_t powerClass = 0; - mmc_extended_csd_config_t extendedCsdconfig; - - switch (width) - { - case kMMC_DataBusWidth4bit: - mask = MMC_POWER_CLASS_4BIT_MASK; /* The mask of 4 bit bus width's power class */ - shift = 0U; - break; - case kMMC_DataBusWidth8bit: - mask = MMC_POWER_CLASS_8BIT_MASK; /* The mask of 8 bit bus width's power class */ - shift = 4U; - break; - case kMMC_DataBusWidth1bit: - default: - break; - } - - switch (card->hostVoltageWindow) - { - case kMMC_VoltageWindow170to195: - - if (card->currentTiming == kMMC_HighSpeed200Timing) - { - powerClass = ((card->extendedCsd.powerClass200MHZVCCQ195VVCC360V) & mask); - } - else if (card->currentTiming == kMMC_HighSpeed400Timing) - { - powerClass = ((card->extendedCsd.powerClass200MHZDDR360V) & mask); - } - else if (card->currentTiming == kMMC_HighSpeedDDR52180V300VTiming) - { - powerClass = ((card->extendedCsd.powerClass52MHZDDR195V) & mask); - } - else if (card->currentTiming == kMMC_HighSpeed52MHZTiming) - { - powerClass = ((card->extendedCsd.powerClass52MHz195V) & mask); - } - else if (card->currentTiming == kMMC_HighSpeed26MHZTiming) - { - powerClass = ((card->extendedCsd.powerClass26MHz195V) & mask); - } - else - { - } - break; - case kMMC_VoltageWindows270to360: - - if (card->currentTiming == kMMC_HighSpeed26MHZTiming) - { - powerClass = ((card->extendedCsd.powerClass26MHz360V) & mask); - } - else if (card->currentTiming == kMMC_HighSpeed52MHZTiming) - { - powerClass = ((card->extendedCsd.powerClass52MHz360V) & mask); - } - else if (card->currentTiming == kMMC_HighSpeedDDR52180V300VTiming) - { - powerClass = ((card->extendedCsd.powerClass52MHZDDR360V) & mask); - } - else - { - } - - break; - default: - powerClass = 0; - break; - } - /* due to 8bit power class position [7:4] */ - powerClass >>= shift; - - extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; - extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexPowerClass; - extendedCsdconfig.ByteValue = powerClass; - extendedCsdconfig.commandSet = kMMC_CommandSetStandard; - if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) - { - return kStatus_SDMMC_ConfigureExtendedCsdFailed; - } - /* restore power class */ - card->extendedCsd.powerClass = powerClass; - - return kStatus_Success; -} - -static status_t MMC_SendTestPattern(mmc_card_t *card, uint32_t blockSize, uint32_t *pattern) -{ - assert(card); - assert(card->host.transfer); - assert(blockSize <= FSL_SDMMC_DEFAULT_BLOCK_SIZE); - assert(pattern); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - HOST_DATA data = {0}; - - command.index = kMMC_SendingBusTest; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeR1; - - /* Ignore errors in bus test procedure to improve chances that the test will work. */ - data.enableIgnoreError = true; - data.blockCount = 1U; - data.blockSize = blockSize; - data.txData = pattern; - - content.command = &command; - content.data = &data; - if ((kStatus_Success != card->host.transfer(card->host.base, &content)) || - (command.response[0U] & kSDMMC_R1ErrorAllFlag)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -static status_t MMC_ReceiveTestPattern(mmc_card_t *card, uint32_t blockSize, uint32_t *pattern) -{ - assert(card); - assert(card->host.transfer); - assert(blockSize <= FSL_SDMMC_DEFAULT_BLOCK_SIZE); - assert(pattern); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - HOST_DATA data = {0}; - - command.index = kMMC_BusTestRead; - command.responseType = kCARD_ResponseTypeR1; - - /* Ignore errors in bus test procedure to improve chances that the test will work. */ - data.enableIgnoreError = true; - data.blockCount = 1U; - data.blockSize = blockSize; - data.rxData = pattern; - - content.command = &command; - content.data = &data; - if ((kStatus_Success != card->host.transfer(card->host.base, &content)) || - ((command.response[0U]) & kSDMMC_R1ErrorAllFlag)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -static status_t MMC_TestDataBusWidth(mmc_card_t *card, mmc_data_bus_width_t width) -{ - assert(card); - - uint32_t blockSize; - uint32_t sendPattern[2U] = {0}; - uint32_t receivedPattern[2U] = {0}; - uint32_t xorMask; - uint32_t xorResult, tempResult = 0U; - - /* For 8 data lines the data block would be (MSB to LSB): 0x0000_0000_0000_AA55, - For 4 data lines the data block would be (MSB to LSB): 0x0000_005A, - For only 1 data line the data block would be: 0x80 */ - switch (width) - { - case kMMC_DataBusWidth8bit: - blockSize = 8U; - sendPattern[0U] = 0xAA55U; - xorMask = 0xFFFFU; - xorResult = 0xFFFFU; - break; - case kMMC_DataBusWidth4bit: - blockSize = 4U; - sendPattern[0U] = 0x5AU; - xorMask = 0xFFU; - xorResult = 0xFFU; - break; - default: - blockSize = 4U; - sendPattern[0U] = 0x80U; - xorMask = 0xFFU; - xorResult = 0xC0U; - break; - } - switch (card->host.config.endianMode) - { - case kHOST_EndianModeLittle: - /* Doesn't need to switch byte sequence when decodes bytes as little endian sequence. */ - break; - case kHOST_EndianModeBig: - /* In big endian mode, the byte transferred first is the byte stored in highest byte position in a word - which will cause the card receive the inverted byte sequence in a word in bus test procedure. So the - sequence of 4 bytes stored in a word should be converted. */ - sendPattern[0] = SWAP_WORD_BYTE_SEQUENCE(sendPattern[0]); - xorMask = SWAP_WORD_BYTE_SEQUENCE(xorMask); - xorResult = SWAP_WORD_BYTE_SEQUENCE(xorResult); - break; - case kHOST_EndianModeHalfWordBig: - /* In half word big endian mode, the byte transferred first is the lower byte in the higher half word. - 0xAA55U should be converted to 0xAA550000U to set the 0x55 to be the first byte to transfer. */ - sendPattern[0] = SWAP_HALF_WROD_BYTE_SEQUENCE(sendPattern[0]); - xorMask = SWAP_HALF_WROD_BYTE_SEQUENCE(xorMask); - xorResult = SWAP_HALF_WROD_BYTE_SEQUENCE(xorResult); - sendPattern[0] = SWAP_WORD_BYTE_SEQUENCE(sendPattern[0]); - xorMask = SWAP_WORD_BYTE_SEQUENCE(xorMask); - xorResult = SWAP_WORD_BYTE_SEQUENCE(xorResult); - break; - default: - return kStatus_SDMMC_NotSupportYet; - } - - if (kStatus_Success != MMC_SendTestPattern(card, blockSize, sendPattern)) - { - return kStatus_SDMMC_SendTestPatternFailed; - } - if (kStatus_Success != MMC_ReceiveTestPattern(card, blockSize, receivedPattern)) - { - return kStatus_SDMMC_ReceiveTestPatternFailed; - } - - tempResult = (sendPattern[0U] ^ receivedPattern[0U]) & xorMask; - /* XOR the send pattern and receive pattern */ - if (tempResult != xorResult) - { - return kStatus_Fail; - } - - return kStatus_Success; -} - -static status_t MMC_SetDataBusWidth(mmc_card_t *card, mmc_data_bus_width_t width) -{ - assert(card); - - mmc_extended_csd_config_t extendedCsdconfig; - - /* Set power class corresponding to bus width. From the Extended CSD the host can learn the power class of the card - and choose to work with a wider data bus. */ - if (kStatus_Success != MMC_SetPowerClass(card, width)) - { - return kStatus_SDMMC_SetPowerClassFail; - } - - if ((width == kMMC_DataBusWidth4bit) && ((card->currentTiming == kMMC_HighSpeedDDR52180V300VTiming) || - (card->currentTiming == kMMC_HighSpeedDDR52120VTiming))) - { - width = kMMC_DataBusWidth4bitDDR; - } - - if ((width == kMMC_DataBusWidth8bit) && - ((card->currentTiming == kMMC_HighSpeedDDR52180V300VTiming) || - (card->currentTiming == kMMC_HighSpeedDDR52120VTiming) || (card->currentTiming == kMMC_HighSpeed400Timing))) - { - width = kMMC_DataBusWidth8bitDDR; - } - - /* Set data bus width */ - extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; - extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexBusWidth; - extendedCsdconfig.ByteValue = width; - extendedCsdconfig.commandSet = kMMC_CommandSetStandard; - if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) - { - return kStatus_SDMMC_ConfigureExtendedCsdFailed; - } - /* restore data bus width */ - card->extendedCsd.dataBusWidth = width; - - return kStatus_Success; -} - -static status_t MMC_SetMaxDataBusWidth(mmc_card_t *card) -{ - assert(card); - - status_t error = kStatus_Fail; - - /* Test and set the data bus width for card. */ - if (card->host.capability.flags & kHOST_Support8BitBusWidth) - { - HOST_SET_CARD_BUS_WIDTH(card->host.base, kHOST_DATABUSWIDTH8BIT); - if ((kStatus_Success == MMC_TestDataBusWidth(card, kMMC_DataBusWidth8bit)) && - (kStatus_Success == MMC_SetDataBusWidth(card, kMMC_DataBusWidth8bit))) - { - card->flags |= kMMC_DataBusWidth8BitFlag; - error = kStatus_Success; - } - } - /* HS400 mode only support 8bit data bus */ - if ((error == kStatus_Fail) && (card->currentTiming == kMMC_HighSpeed400Timing)) - { - return kStatus_SDMMC_SetDataBusWidthFailed; - } - - if ((error == kStatus_Fail) && (card->host.capability.flags & kHOST_Support4BitBusWidth)) - { - HOST_SET_CARD_BUS_WIDTH(card->host.base, kHOST_DATABUSWIDTH4BIT); - if ((kStatus_Success == MMC_TestDataBusWidth(card, kMMC_DataBusWidth4bit)) && - (kStatus_Success == MMC_SetDataBusWidth(card, kMMC_DataBusWidth4bit))) - { - card->flags |= kMMC_DataBusWidth4BitFlag; - error = kStatus_Success; - } - } - - /* HS200/DDR mode only support 4bit/8bit data bus */ - if ((error == kStatus_Fail) && ((card->currentTiming == kMMC_HighSpeed200Timing) || - (card->currentTiming == kMMC_HighSpeedDDR52180V300VTiming) || - (card->currentTiming == kMMC_HighSpeedDDR52120VTiming))) - { - return kStatus_SDMMC_SetDataBusWidthFailed; - } - - if (error == kStatus_Fail) - { - card->flags |= kMMC_DataBusWidth1BitFlag; - /* Card's data bus width will be default 1 bit mode. */ - HOST_SET_CARD_BUS_WIDTH(card->host.base, kHOST_DATABUSWIDTH1BIT); - } - - return kStatus_Success; -} - -static status_t MMC_SelectCardDriverStrength(mmc_card_t *card, uint8_t driverStrength) -{ - assert(card); - - uint8_t ioStrength = 0U; - mmc_extended_csd_config_t extendedCsdconfig; - - ioStrength = card->extendedCsd.highSpeedTiming | (uint8_t)(driverStrength << 4U); - - /* Switch to high speed timing. */ - extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; - extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexHighSpeedTiming; - extendedCsdconfig.ByteValue = ioStrength; - extendedCsdconfig.commandSet = kMMC_CommandSetStandard; - if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) - { - return kStatus_SDMMC_ConfigureExtendedCsdFailed; - } - - card->extendedCsd.highSpeedTiming |= ioStrength; - - return kStatus_Success; -} - -static status_t MMC_SelectBusTiming(mmc_card_t *card) -{ - assert(card); - - uint32_t value = 0U; - uint32_t targetFreq = 0U; - - mmc_extended_csd_config_t extendedCsdconfig; - - /* 1.8V and 1.2V timing select */ - if (((kHOST_SupportHS200 != HOST_NOT_SUPPORT) || (kHOST_SupportHS400 != HOST_NOT_SUPPORT) || - (kHOST_SupportDDR50 != HOST_NOT_SUPPORT)) && - ((card->hostVoltageWindow == kMMC_VoltageWindow170to195) || (card->hostVoltageWindow == kMMC_VoltageWindow120))) - { - switch (card->currentTiming) - { - case kMMC_HighSpeedTimingNone: - case kMMC_HighSpeed400Timing: - if ((card->host.capability.flags & kHOST_SupportHS400) && - (card->flags & kMMC_SupportHS400DDR200MHZ180VFlag)) - { - value = kMMC_HighSpeed400Timing; - card->currentTiming = kMMC_HighSpeed400Timing; - targetFreq = HOST_SUPPORT_HS400_FREQ; - break; - } - case kMMC_HighSpeed200Timing: - if ((card->flags & kMMC_SupportHS200200MHZ180VFlag) && - ((card->host.capability.flags & kHOST_SupportHS200))) - { - value = kMMC_HighSpeed200Timing; - card->currentTiming = kMMC_HighSpeed200Timing; - targetFreq = HOST_SUPPORT_HS200_FREQ; - break; - } - case kMMC_HighSpeedDDR52120VTiming: - case kMMC_HighSpeedDDR52180V300VTiming: - if ((card->hostVoltageWindow == kMMC_VoltageWindow170to195)) - { - if ((card->flags & kMMC_SupportHighSpeedDDR52MHZ180V300VFlag) && - (card->host.capability.flags & kHOST_SupportDDR50)) - { - targetFreq = MMC_CLOCK_DDR52; - value = kMMC_HighSpeedTiming; - card->currentTiming = kMMC_HighSpeedDDR52180V300VTiming; - break; - } - } - else - { - if ((card->flags & kMMC_SupportHighSpeedDDR52MHZ120VFlag) && - (card->host.capability.flags & kHOST_SupportDDR50)) - { - value = kMMC_HighSpeedTiming; - targetFreq = MMC_CLOCK_DDR52; - card->currentTiming = kMMC_HighSpeedDDR52120VTiming; - break; - } - } - case kMMC_HighSpeed52MHZTiming: - if (card->flags & kMMC_SupportHighSpeed52MHZFlag) - { - value = kMMC_HighSpeedTiming; - targetFreq = MMC_CLOCK_52MHZ; - card->currentTiming = kMMC_HighSpeed52MHZTiming; - break; - } - case kMMC_HighSpeed26MHZTiming: - if (card->flags & kMMC_SupportHighSpeed26MHZFlag) - { - value = kMMC_HighSpeedTiming; - targetFreq = MMC_CLOCK_26MHZ; - card->currentTiming = kMMC_HighSpeed26MHZTiming; - break; - } - - default: - return kStatus_SDMMC_SwitchBusTimingFailed; - } - } - /* 3.3V timing */ - else if (((card->host.capability.flags) & kHOST_SupportHighSpeed) || (kHOST_SupportDDR50 != HOST_NOT_SUPPORT)) - { - /* high speed mode */ - value = kMMC_HighSpeedTiming; - - switch (card->currentTiming) - { - case kMMC_HighSpeedTimingNone: - case kMMC_HighSpeed400Timing: - case kMMC_HighSpeed200Timing: - case kMMC_HighSpeedDDR52120VTiming: - case kMMC_HighSpeedDDR52180V300VTiming: - if ((card->flags & kMMC_SupportHighSpeedDDR52MHZ180V300VFlag) && - (kHOST_SupportDDR50 != HOST_NOT_SUPPORT)) - { - targetFreq = MMC_CLOCK_DDR52; - card->currentTiming = kMMC_HighSpeedDDR52180V300VTiming; - break; - } - case kMMC_HighSpeed52MHZTiming: - if (card->flags & kMMC_SupportHighSpeed52MHZFlag) - { - targetFreq = MMC_CLOCK_52MHZ; - card->currentTiming = kMMC_HighSpeed52MHZTiming; - break; - } - case kMMC_HighSpeed26MHZTiming: - if (card->flags & kMMC_SupportHighSpeed26MHZFlag) - { - targetFreq = MMC_CLOCK_26MHZ; - card->currentTiming = kMMC_HighSpeed26MHZTiming; - break; - } - default: - return kStatus_SDMMC_SwitchBusTimingFailed; - } - } - else - { - /*default mode*/ - value = 0U; - card->currentTiming = kMMC_HighSpeedTimingNone; - } - - if (card->currentTiming == kMMC_HighSpeed200Timing) - { - /* select bus width before select bus timing for HS200 mode */ - if (MMC_SetMaxDataBusWidth(card) != kStatus_Success) - { - return kStatus_SDMMC_SetDataBusWidthFailed; - } - } - - if (card->currentTiming != kMMC_HighSpeedTimingNone) - { - /* Switch to high speed timing. */ - extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; - extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexHighSpeedTiming; - extendedCsdconfig.ByteValue = value; - extendedCsdconfig.commandSet = kMMC_CommandSetStandard; - if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) - { - return kStatus_SDMMC_ConfigureExtendedCsdFailed; - } - card->extendedCsd.highSpeedTiming |= value; - - /* Set card data width, it is nessesary to config the the data bus here, to meet emmc5.0 specification, - * when you are working in DDR mode , HS_TIMING must set before set bus width - */ - if (card->currentTiming != kMMC_HighSpeed200Timing) - { - if (MMC_SetMaxDataBusWidth(card) != kStatus_Success) - { - return kStatus_SDMMC_SetDataBusWidthFailed; - } - } - card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, targetFreq); - } - - if ((card->currentTiming == kMMC_HighSpeedDDR52180V300VTiming) || - (card->currentTiming == kMMC_HighSpeedDDR52120VTiming) || (card->currentTiming == kMMC_HighSpeed400Timing)) - { - HOST_ENABLE_DDR_MODE(card->host.base, true); - /* enable HS400 mode */ - if (card->currentTiming == kMMC_HighSpeed400Timing) - { - HOST_ENABLE_HS400_MODE(card->host.base, true); - } - } - return kStatus_Success; -} - -static void MMC_DecodeCid(mmc_card_t *card, uint32_t *rawCid) -{ - assert(card); - assert(rawCid); - - mmc_cid_t *cid; - - cid = &(card->cid); - cid->manufacturerID = (uint8_t)((rawCid[3U] & 0xFF000000U) >> 24U); - cid->applicationID = (uint16_t)((rawCid[3U] & 0xFFFF00U) >> 8U); - - cid->productName[0U] = (uint8_t)((rawCid[3U] & 0xFFU)); - cid->productName[1U] = (uint8_t)((rawCid[2U] & 0xFF000000U) >> 24U); - cid->productName[2U] = (uint8_t)((rawCid[2U] & 0xFF0000U) >> 16U); - cid->productName[3U] = (uint8_t)((rawCid[2U] & 0xFF00U) >> 8U); - cid->productName[4U] = (uint8_t)((rawCid[2U] & 0xFFU)); - - cid->productVersion = (uint8_t)((rawCid[1U] & 0xFF000000U) >> 24U); - - cid->productSerialNumber = (uint32_t)((rawCid[1U] & 0xFFFFFFU) << 8U); - cid->productSerialNumber |= (uint32_t)((rawCid[0U] & 0xFF000000U) >> 24U); - - cid->manufacturerData = (uint16_t)((rawCid[0U] & 0xFFF00U) >> 8U); -} - -static status_t MMC_AllSendCid(mmc_card_t *card) -{ - assert(card); - assert(card->host.transfer); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - - command.index = kSDMMC_AllSendCid; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeR2; - - content.command = &command; - content.data = NULL; - if (kStatus_Success == card->host.transfer(card->host.base, &content)) - { - memcpy(card->rawCid, command.response, sizeof(card->rawCid)); - MMC_DecodeCid(card, command.response); - - return kStatus_Success; - } - - return kStatus_SDMMC_TransferFailed; -} - -static status_t MMC_SendCsd(mmc_card_t *card) -{ - assert(card); - assert(card->host.transfer); - - HOST_COMMAND command = {0}; - HOST_TRANSFER content = {0}; - - command.index = kSDMMC_SendCsd; - command.argument = (card->relativeAddress << 16U); - command.responseType = kCARD_ResponseTypeR2; - - content.command = &command; - content.data = 0U; - if (kStatus_Success == card->host.transfer(card->host.base, &content)) - { - memcpy(card->rawCsd, command.response, sizeof(card->rawCsd)); - /* The response is from bit 127:8 in R2, corresponding to command.response[3][31:0] to - command.response[0U][31:8]. */ - MMC_DecodeCsd(card, card->rawCsd); - - return kStatus_Success; - } - - return kStatus_SDMMC_TransferFailed; -} - -static status_t MMC_CheckBlockRange(mmc_card_t *card, uint32_t startBlock, uint32_t blockCount) -{ - assert(card); - assert(blockCount); - - status_t error = kStatus_Success; - uint32_t partitionBlocks; - - switch (card->currentPartition) - { - case kMMC_AccessPartitionUserAera: - { - partitionBlocks = card->userPartitionBlocks; - break; - } - case kMMC_AccessPartitionBoot1: - case kMMC_AccessPartitionBoot2: - { - /* Boot partition 1 and partition 2 have the same partition size. */ - partitionBlocks = card->bootPartitionBlocks; - break; - } - default: - error = kStatus_InvalidArgument; - break; - } - /* Check if the block range accessed is within current partition's block boundary. */ - if ((error == kStatus_Success) && ((startBlock + blockCount) > partitionBlocks)) - { - error = kStatus_InvalidArgument; - } - - return error; -} - -static status_t MMC_CheckEraseGroupRange(mmc_card_t *card, uint32_t startGroup, uint32_t endGroup) -{ - assert(card); - - status_t error = kStatus_Success; - uint32_t partitionBlocks; - uint32_t eraseGroupBoundary; - - switch (card->currentPartition) - { - case kMMC_AccessPartitionUserAera: - { - partitionBlocks = card->userPartitionBlocks; - break; - } - case kMMC_AccessPartitionBoot1: - case kMMC_AccessPartitionBoot2: - { - /* Boot partition 1 and partition 2 have the same partition size. */ - partitionBlocks = card->bootPartitionBlocks; - break; - } - default: - error = kStatus_InvalidArgument; - break; - } - - if (error == kStatus_Success) - { - /* Check if current partition's total block count is integer multiples of the erase group size. */ - if ((partitionBlocks % card->eraseGroupBlocks) == 0U) - { - eraseGroupBoundary = (partitionBlocks / card->eraseGroupBlocks); - } - else - { - /* Card will ignore the unavailable blocks within the last erase group automatically. */ - eraseGroupBoundary = (partitionBlocks / card->eraseGroupBlocks + 1U); - } - - /* Check if the group range accessed is within current partition's erase group boundary. */ - if ((startGroup > eraseGroupBoundary) || (endGroup > eraseGroupBoundary)) - { - error = kStatus_InvalidArgument; - } - } - - return error; -} - -static status_t MMC_Read( - mmc_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount) -{ - assert(card); - assert(card->host.transfer); - assert(buffer); - assert(blockCount); - assert(blockSize); - assert(blockSize == FSL_SDMMC_DEFAULT_BLOCK_SIZE); - - HOST_COMMAND command = {0}; - HOST_DATA data = {0}; - HOST_TRANSFER content = {0}; - status_t error; - - if (((card->flags & kMMC_SupportHighCapacityFlag) && (blockSize != 512U)) || (blockSize > card->blockSize) || - (blockSize > card->host.capability.maxBlockLength) || (blockSize % 4U)) - { - return kStatus_SDMMC_CardNotSupport; - } - - /* Wait for the card write process complete because of that card read process and write process use one buffer. */ - if (kStatus_Success != MMC_WaitWriteComplete(card)) - { - return kStatus_SDMMC_WaitWriteCompleteFailed; - } - - data.blockSize = blockSize; - data.blockCount = blockCount; - data.rxData = (uint32_t *)buffer; - data.enableAutoCommand12 = true; - command.index = kSDMMC_ReadMultipleBlock; - if (data.blockCount == 1U) - { - command.index = kSDMMC_ReadSingleBlock; - } - else - { - if ((!(data.enableAutoCommand12)) && (card->enablePreDefinedBlockCount)) - { - /* If enabled the pre-define count read/write feature of the card, need to set block count firstly. */ - if (kStatus_Success != MMC_SetBlockCount(card, blockCount)) - { - return kStatus_SDMMC_SetBlockCountFailed; - } - } - } - command.argument = startBlock; - if (!(card->flags & kMMC_SupportHighCapacityFlag)) - { - command.argument *= data.blockSize; - } - command.responseType = kCARD_ResponseTypeR1; - command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; - - content.command = &command; - content.data = &data; - - /* should check tuning error during every transfer */ - error = MMC_Transfer(card, &content, 0U); - if (kStatus_Success != error) - { - return error; - } - - /* When host's AUTO_COMMAND12 feature isn't enabled and PRE_DEFINED_COUNT command isn't enabled in multiple - blocks transmission, sends STOP_TRANSMISSION command. */ - if ((blockCount > 1U) && (!(data.enableAutoCommand12)) && (!card->enablePreDefinedBlockCount)) - { - if (kStatus_Success != MMC_StopTransmission(card)) - { - return kStatus_SDMMC_StopTransmissionFailed; - } - } - - return kStatus_Success; -} - -static status_t MMC_Write( - mmc_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount) -{ - assert(card); - assert(card->host.transfer); - assert(buffer); - assert(blockCount); - assert(blockSize); - assert(blockSize == FSL_SDMMC_DEFAULT_BLOCK_SIZE); - - HOST_COMMAND command = {0}; - HOST_DATA data = {0}; - HOST_TRANSFER content = {0}; - status_t error; - - /* Check address range */ - if (((card->flags & kMMC_SupportHighCapacityFlag) && (blockSize != 512U)) || (blockSize > card->blockSize) || - (blockSize > card->host.capability.maxBlockLength) || (blockSize % 4U)) - { - return kStatus_SDMMC_CardNotSupport; - } - - /* Wait for the card's buffer to be not full to write to improve the write performance. */ - while ((GET_HOST_STATUS(card->host.base) & CARD_DATA0_STATUS_MASK) != CARD_DATA0_NOT_BUSY) - { - } - - data.blockSize = blockSize; - data.blockCount = blockCount; - data.txData = (const uint32_t *)buffer; - data.enableAutoCommand12 = true; - - command.index = kSDMMC_WriteMultipleBlock; - if (data.blockCount == 1U) - { - command.index = kSDMMC_WriteSingleBlock; - } - else - { - if ((!(data.enableAutoCommand12)) && (card->enablePreDefinedBlockCount)) - { - /* If enabled the pre-define count read/write featue of the card, need to set block count firstly */ - if (kStatus_Success != MMC_SetBlockCount(card, blockCount)) - { - return kStatus_SDMMC_SetBlockCountFailed; - } - } - } - command.argument = startBlock; - if (!(card->flags & kMMC_SupportHighCapacityFlag)) - { - command.argument *= blockSize; - } - command.responseType = kCARD_ResponseTypeR1; - command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; - - content.command = &command; - content.data = &data; - - /* should check tuning error during every transfer */ - error = MMC_Transfer(card, &content, 0U); - if (kStatus_Success != error) - { - return error; - } - - /* When host's AUTO_COMMAND12 feature isn't enabled and PRE_DEFINED_COUNT command isn't enabled in multiple - blocks transmission, sends STOP_TRANSMISSION command. */ - if ((blockCount > 1U) && (!(data.enableAutoCommand12)) && (!card->enablePreDefinedBlockCount)) - { - if (kStatus_Success != MMC_StopTransmission(card)) - { - return kStatus_SDMMC_StopTransmissionFailed; - } - } - - return kStatus_Success; -} - -status_t MMC_Init(mmc_card_t *card) -{ - assert(card); - - status_t error = kStatus_Success; - uint32_t opcode = 0U; - - if (!card->isHostReady) - { - error = HOST_Init(&(card->host)); - if (error != kStatus_Success) - { - return error; - } - /* set the host status flag, after the card re-plug in, don't need init host again */ - card->isHostReady = true; - } - - /* voltage switch to normal but not 1.8V */ - HOST_SWITCH_VOLTAGE180V(card->host.base, false); - /* reset DATA bus width */ - HOST_SET_CARD_BUS_WIDTH(card->host.base, kHOST_DATABUSWIDTH1BIT); - /* disable tuning */ - HOST_EXECUTE_STANDARD_TUNING_ENABLE(card->host.base, false); - /* Disable DDR mode */ - HOST_ENABLE_DDR_MODE(card->host.base, false); - /* get host capability first */ - GET_HOST_CAPABILITY(card->host.base, &(card->host.capability)); - /* Set clock to 400KHz. */ - card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SDMMC_CLOCK_400KHZ); - /* Send CMD0 to reset the bus */ - if (kStatus_Success != MMC_GoIdle(card)) - { - return kStatus_SDMMC_GoIdleFailed; - } - - /* Hand-shaking with card to validata the voltage range Host first sending its expected - information.*/ - if (kStatus_Success != MMC_SendOperationCondition(card, 0U)) - { - return kStatus_SDMMC_HandShakeOperationConditionFailed; - } - - /* switch the host voltage which the card can support */ - if (kStatus_Success != MMC_SwitchVoltage(card, &opcode)) - { - return kStatus_SDMMC_HandShakeOperationConditionFailed; - } - - /* Get host's access mode. */ - if (card->host.capability.maxBlockLength >= FSL_SDMMC_DEFAULT_BLOCK_SIZE) - { - opcode |= kMMC_AccessModeSector << MMC_OCR_ACCESS_MODE_SHIFT; - } - else - { - opcode |= kMMC_AccessModeSector << MMC_OCR_ACCESS_MODE_SHIFT; - } - - if (kStatus_Success != MMC_SendOperationCondition(card, opcode)) - { - return kStatus_SDMMC_HandShakeOperationConditionFailed; - } - - /* Get card CID */ - if (kStatus_Success != MMC_AllSendCid(card)) - { - return kStatus_SDMMC_AllSendCidFailed; - } - - /* Set the card relative address */ - if (kStatus_Success != MMC_SetRelativeAddress(card)) - { - return kStatus_SDMMC_SetRelativeAddressFailed; - } - - /* Get the CSD register content */ - if (kStatus_Success != MMC_SendCsd(card)) - { - return kStatus_SDMMC_SendCsdFailed; - } - - /* Set to maximum speed in normal mode. */ - MMC_SetMaxFrequency(card); - - /* Send CMD7 with the card's relative address to place the card in transfer state. Puts current selected card in - transfer state. */ - if (kStatus_Success != MMC_SelectCard(card, true)) - { - return kStatus_SDMMC_SelectCardFailed; - } - - /* Get Extended CSD register content. */ - if (kStatus_Success != MMC_SendExtendedCsd(card)) - { - return kStatus_SDMMC_SendExtendedCsdFailed; - } - /* set block size */ - if (MMC_SetBlockSize(card, FSL_SDMMC_DEFAULT_BLOCK_SIZE)) - { - return kStatus_SDMMC_SetCardBlockSizeFailed; - } - - /* switch to host support speed mode, then switch MMC data bus width and select power class */ - if (kStatus_Success != MMC_SelectBusTiming(card)) - { - return kStatus_SDMMC_SwitchBusTimingFailed; - } - - if ((card->currentTiming == kMMC_HighSpeed200Timing) || (card->currentTiming == kMMC_HighSpeed400Timing)) - { - /* config IO strength */ - HOST_CONFIG_MMC_IO(CARD_BUS_FREQ_200MHZ, CARD_BUS_STRENGTH_7); - /* excute tuning for HS200 and HS400*/ - if (MMC_ExecuteTuning(card) != kStatus_Success) - { - return kStatus_SDMMC_TuningFail; - } - /* config driver strength */ - if (kStatus_Success != MMC_SelectCardDriverStrength(card, kMMC_DriverStrength0)) - { - return kStatus_SDMMC_SetDriverStrengthFail; - } - } - else if ((card->currentTiming == kMMC_HighSpeedDDR52180V300VTiming) || - (card->currentTiming == kMMC_HighSpeedDDR52120VTiming)) - { - /*config IO strength*/ - HOST_CONFIG_MMC_IO(CARD_BUS_FREQ_100MHZ1, CARD_BUS_STRENGTH_4); - } - else - { - HOST_CONFIG_MMC_IO(CARD_BUS_FREQ_50MHZ, CARD_BUS_STRENGTH_3); - } - - /* Set to max erase unit size */ - if (kStatus_Success != MMC_SetMaxEraseUnitSize(card)) - { - return kStatus_SDMMC_EnableHighCapacityEraseFailed; - } - - /* Set card default to access non-boot partition */ - card->currentPartition = kMMC_AccessPartitionUserAera; - - return kStatus_Success; -} - -void MMC_Deinit(mmc_card_t *card) -{ - assert(card); - - MMC_SelectCard(card, false); - HOST_Deinit(&(card->host)); - /* should re-init host */ - card->isHostReady = false; -} - -bool MMC_CheckReadOnly(mmc_card_t *card) -{ - assert(card); - - return ((card->csd.flags & kMMC_CsdPermanentWriteProtectFlag) || - (card->csd.flags & kMMC_CsdTemporaryWriteProtectFlag)); -} - -status_t MMC_SelectPartition(mmc_card_t *card, mmc_access_partition_t partitionNumber) -{ - assert(card); - - uint8_t bootConfig; - mmc_extended_csd_config_t extendedCsdconfig; - - bootConfig = card->extendedCsd.partitionConfig; - bootConfig &= ~MMC_BOOT_CONFIG_PARTITION_ACCESS_MASK; - bootConfig |= ((uint32_t)partitionNumber << MMC_BOOT_CONFIG_PARTITION_ACCESS_SHIFT); - - extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; - extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexBootConfig; - extendedCsdconfig.ByteValue = bootConfig; - extendedCsdconfig.commandSet = kMMC_CommandSetStandard; - if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) - { - return kStatus_SDMMC_ConfigureExtendedCsdFailed; - } - - /* Save current configuration. */ - card->extendedCsd.partitionConfig = bootConfig; - card->currentPartition = partitionNumber; - - return kStatus_Success; -} - -status_t MMC_ReadBlocks(mmc_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) -{ - assert(card); - assert(buffer); - assert(blockCount); - - uint32_t blockCountOneTime; /* The block count can be erased in one time sending READ_BLOCKS command. */ - uint32_t blockDone; /* The blocks has been read. */ - uint32_t blockLeft; /* Left blocks to be read. */ - uint8_t *nextBuffer; - status_t error = kStatus_Success; - - blockLeft = blockCount; - blockDone = 0U; - if (kStatus_Success != MMC_CheckBlockRange(card, startBlock, blockCount)) - { - return kStatus_InvalidArgument; - } - - while (blockLeft) - { - if (blockLeft > card->host.capability.maxBlockCount) - { - blockLeft = blockLeft - card->host.capability.maxBlockCount; - blockCountOneTime = card->host.capability.maxBlockCount; - } - else - { - blockCountOneTime = blockLeft; - blockLeft = 0U; - } - - nextBuffer = (buffer + blockDone * FSL_SDMMC_DEFAULT_BLOCK_SIZE); - error = MMC_Read(card, nextBuffer, (startBlock + blockDone), FSL_SDMMC_DEFAULT_BLOCK_SIZE, blockCount); - if (error != kStatus_Success) - { - return error; - } - - blockDone += blockCountOneTime; - } - - return error; -} - -status_t MMC_WriteBlocks(mmc_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) -{ - assert(card); - assert(buffer); - assert(blockCount); - - uint32_t blockCountOneTime; - uint32_t blockLeft; - uint32_t blockDone; - const uint8_t *nextBuffer; - status_t error = kStatus_Success; - - blockLeft = blockCount; - blockDone = 0U; - if (kStatus_Success != MMC_CheckBlockRange(card, startBlock, blockCount)) - { - return kStatus_InvalidArgument; - } - - while (blockLeft) - { - if (blockLeft > card->host.capability.maxBlockCount) - { - blockLeft = blockLeft - card->host.capability.maxBlockCount; - blockCountOneTime = card->host.capability.maxBlockCount; - } - else - { - blockCountOneTime = blockLeft; - blockLeft = 0U; - } - - nextBuffer = (buffer + blockDone * FSL_SDMMC_DEFAULT_BLOCK_SIZE); - error = MMC_Write(card, nextBuffer, (startBlock + blockDone), FSL_SDMMC_DEFAULT_BLOCK_SIZE, blockCount); - if (error != kStatus_Success) - { - return error; - } - - blockDone += blockCountOneTime; - } - - return error; -} - -status_t MMC_EraseGroups(mmc_card_t *card, uint32_t startGroup, uint32_t endGroup) -{ - assert(card); - assert(card->host.transfer); - - uint32_t startGroupAddress; - uint32_t endGroupAddress; - HOST_COMMAND command = {0}; - HOST_TRANSFER content = {0}; - - if (kStatus_Success != MMC_CheckEraseGroupRange(card, startGroup, endGroup)) - { - return kStatus_InvalidArgument; - } - - /* Wait for the card's buffer to be not full to write to improve the write performance. */ - while ((GET_HOST_STATUS(card->host.base) & CARD_DATA0_STATUS_MASK) != CARD_DATA0_NOT_BUSY) - { - } - - /* Calculate the start group address and end group address */ - startGroupAddress = startGroup; - endGroupAddress = endGroup; - if (card->flags & kMMC_SupportHighCapacityFlag) - { - /* The implementation of a higher than 2GB of density of memory will not be backwards compatible with the - lower densities.First of all the address argument for higher than 2GB of density of memory is changed to - be sector address (512B sectors) instead of byte address */ - startGroupAddress = (startGroupAddress * (card->eraseGroupBlocks)); - endGroupAddress = (endGroupAddress * (card->eraseGroupBlocks)); - } - else - { - /* The address unit is byte when card capacity is lower than 2GB */ - startGroupAddress = (startGroupAddress * (card->eraseGroupBlocks) * FSL_SDMMC_DEFAULT_BLOCK_SIZE); - endGroupAddress = (endGroupAddress * (card->eraseGroupBlocks) * FSL_SDMMC_DEFAULT_BLOCK_SIZE); - } - - /* Set the start erase group address */ - command.index = kMMC_EraseGroupStart; - command.argument = startGroupAddress; - command.responseType = kCARD_ResponseTypeR1; - command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; - - content.command = &command; - content.data = NULL; - if (kStatus_Success != MMC_Transfer(card, &content, 0U)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* Set the end erase group address */ - command.index = kMMC_EraseGroupEnd; - command.argument = endGroupAddress; - - content.command = &command; - content.data = NULL; - if (kStatus_Success != MMC_Transfer(card, &content, 0U)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* Start the erase process */ - command.index = kSDMMC_Erase; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeR1b; - command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; - - content.command = &command; - content.data = NULL; - if (kStatus_Success != MMC_Transfer(card, &content, 0U)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t MMC_SetBootConfig(mmc_card_t *card, const mmc_boot_config_t *config) -{ - assert(card); - assert(config); - - uint8_t bootParameter; - mmc_extended_csd_config_t extendedCsdconfig; - - if (kMMC_ExtendedCsdRevision13 != card->extendedCsd.extendecCsdVersion) /* Only V4.3 support fast boot */ - { - return kStatus_SDMMC_NotSupportYet; - } - - /* Set the BOOT_CONFIG field of Extended CSD */ - bootParameter = card->extendedCsd.partitionConfig; - bootParameter &= ~(MMC_BOOT_CONFIG_ACK_MASK); - bootParameter &= ~(MMC_BOOT_CONFIG_PARTITION_ENABLE_MASK); - bootParameter |= ((config->enableBootAck ? 1U : 0U) << MMC_BOOT_CONFIG_ACK_SHIFT); - bootParameter |= ((uint32_t)(config->bootPartition) << MMC_BOOT_CONFIG_PARTITION_ENABLE_SHIFT); - - extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; - extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexBootConfig; - extendedCsdconfig.ByteValue = bootParameter; - extendedCsdconfig.commandSet = kMMC_CommandSetStandard; - if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) - { - return kStatus_SDMMC_ConfigureExtendedCsdFailed; - } - - card->extendedCsd.partitionConfig = bootParameter; - - /*Set BOOT_BUS_WIDTH in Extended CSD */ - bootParameter = card->extendedCsd.bootDataBusWidth; - bootParameter &= ~(MMC_BOOT_BUS_WIDTH_RESET_MASK); - bootParameter &= ~(MMC_BOOT_BUS_WIDTH_WIDTH_MASK); - bootParameter |= ((config->retainBootBusWidth ? 1U : 0U) << MMC_BOOT_BUS_WIDTH_RESET_SHIFT); - bootParameter |= ((uint32_t)(config->bootDataBusWidth) << MMC_BOOT_BUS_WIDTH_WIDTH_SHIFT); - - extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; - extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexBootBusWidth; - extendedCsdconfig.ByteValue = bootParameter; - if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) - { - return kStatus_SDMMC_ConfigureBootFailed; - } - - card->extendedCsd.bootDataBusWidth = bootParameter; - - return kStatus_Success; -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sd.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sd.c deleted file mode 100644 index 16f908113b0..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sd.c +++ /dev/null @@ -1,1679 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_card.h" -#include "fsl_sdmmc.h" - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Send SELECT_CARD command to set the card to be transfer state or not. - * - * @param card Card descriptor. - * @param isSelected True to set the card into transfer state. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t inline SD_SelectCard(sd_card_t *card, bool isSelected); - -/*! - * @brief Wait write process complete. - * - * @param card Card descriptor. - * @retval kStatus_Timeout Send command timeout. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_WaitWriteComplete(sd_card_t *card); - -/*! - * @brief Send SEND_APPLICATION_COMMAND command. - * - * @param card Card descriptor. - * @param relativeaddress - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. - * @retval kStatus_Success Operate successfully. - */ -static status_t inline SD_SendApplicationCmd(sd_card_t *card, uint32_t relativeAddress); - -/*! - * @brief Send GO_IDLE command to set the card to be idle state. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t inline SD_GoIdle(sd_card_t *card); - -/*! - * @brief Send STOP_TRANSMISSION command after multiple blocks read/write. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_StopTransmission(sd_card_t *card); - -/*! - * @brief Send SET_BLOCK_SIZE command. - * - * @param card Card descriptor. - * @param blockSize Block size. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t inline SD_SetBlockSize(sd_card_t *card, uint32_t blockSize); - -/*! - * @brief Send GET_RCA command to get card relative address. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_SendRca(sd_card_t *card); - -/*! - * @brief Send SWITCH_FUNCTION command to switch the card function group. - * - * @param card Card descriptor. - * @param mode 0 to check function group. 1 to switch function group - * @param group Function group - * @param number Function number in the function group. - * @param status Switch function status. - * @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_SwitchFunction(sd_card_t *card, uint32_t mode, uint32_t group, uint32_t number, uint32_t *status); - -/*! - * @brief Decode raw SCR register content in the data blocks. - * - * @param card Card descriptor. - * @param rawScr Raw SCR register content. - */ -static void SD_DecodeScr(sd_card_t *card, uint32_t *rawScr); - -/*! - * @brief Send GET_SCR command. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_SendApplicationCommandFailed Send application command failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_NotSupportYet Not support yet. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_SendScr(sd_card_t *card); - -/*! - * @brief Switch the card to be high speed mode. - * - * @param card Card descriptor. - * @param group number - * @param functio number - * @retval kStatus_SDMMC_CardNotSupport Card not support. - * @retval kStatus_SDMMC_SwitchFailed Switch failed. - * @retval kStatus_SDMMC_NotSupportYet Not support yet. - * @retval kStatus_Fail Switch failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_SelectFunction(sd_card_t *card, uint32_t group, uint32_t function); - -/*! - * @brief Send SET_DATA_WIDTH command to set SD bus width. - * - * @param card Card descriptor. - * @param width Data bus width. - * @retval kStatus_SDMMC_SendApplicationCommandFailed Send application command failed. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_SetDataBusWidth(sd_card_t *card, sd_data_bus_width_t width); - -/*! - * @brief Decode raw CSD register content in the data blocks. - * - * @param card Card descriptor. - * @param rawCsd Raw CSD register content. - */ -static void SD_DecodeCsd(sd_card_t *card, uint32_t *rawCsd); - -/*! - * @brief Send SEND_CSD command to get CSD register content from Card. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_SendCsd(sd_card_t *card); - -/*! - * @brief Decode raw CID register content in the data blocks. - * - * @param rawCid raw CID register content. - * @param card Card descriptor. - */ -static void SD_DecodeCid(sd_card_t *card, uint32_t *rawCid); - -/*! - * @brief Send GET_CID command to get CID from card. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_AllSendCid(sd_card_t *card); - -/*! - * @brief Send SEND_OPERATION_CONDITION command. - * - * This function sends host capacity support information and asks the accessed card to send its operating condition - * register content. - * - * @param card Card descriptor. - * @param argument The argument of the send operation condition ncomamnd. - * @retval kStatus_SDMMC_SendApplicationCommandFailed Send application command failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Timeout Timeout. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_ApplicationSendOperationCondition(sd_card_t *card, uint32_t argument); - -/*! - * @brief Send GET_INTERFACE_CONDITION command to get card interface condition. - * - * This function checks card interface condition, which includes host supply voltage information and asks the card - * whether card supports the specified host voltage. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_SendInterfaceCondition(sd_card_t *card); - -/*! - * @brief Send switch voltage command - * switch card voltage to 1.8v - * - * @param card Card descriptor. - */ -static status_t SD_SwitchVoltage(sd_card_t *card); - -/*! - * @brief select bus timing - * select card timing - * @param card Card descriptor. - */ -static status_t SD_SelectBusTiming(sd_card_t *card); - -/*! - * @brief select card driver strength - * select card driver strength - * @param card Card descriptor. - * @param driver strength - */ -static status_t SD_SetDriverStrength(sd_card_t *card, sd_driver_strength_t driverStrength); - -/*! - * @brief select max current - * select max operation current - * @param card Card descriptor. - * @param max current - */ -static status_t SD_SetMaxCurrent(sd_card_t *card, sd_max_current_t maxCurrent); - -/*! - * @brief Read data from specific SD card. - * - * @param card Card descriptor. - * @param buffer Buffer to save data blocks read. - * @param startBlock Card start block number to be read. - * @param blockSize Block size. - * @param blockCount Block count. - * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. - * @retval kStatus_SDMMC_WaitWriteCompleteFailed Wait write complete failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_Read(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount); - -/*! - * @brief Write data to specific card - * - * @param card Card descriptor. - * @param buffer Buffer to be sent. - * @param startBlock Card start block number to be written. - * @param blockSize Block size. - * @param blockCount Block count. - * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_Write( - sd_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount); - -/*! - * @brief Erase data for the given block range. - * - * @param card Card descriptor. - * @param startBlock Card start block number to be erased. - * @param blockCount The block count to be erased. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_Erase(sd_card_t *card, uint32_t startBlock, uint32_t blockCount); - -/*! - * @brief card transfer function. - * - * @param card Card descriptor. - * @param transfer content. - * @param retry times - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - * @retval kStatus_SDMMC_TuningFail tuning fail - */ -static status_t SD_Transfer(sd_card_t *card, HOST_TRANSFER *content, uint32_t retry); - -/*! - * @brief card execute tuning function. - * - * @param card Card descriptor. - * @retval kStatus_Success Operate successfully. - * @retval kStatus_SDMMC_TuningFail tuning fail. - * @retval kStatus_SDMMC_TransferFailed transfer fail - */ -static status_t inline SD_ExecuteTuning(sd_card_t *card); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -static status_t inline SD_SelectCard(sd_card_t *card, bool isSelected) -{ - assert(card); - - return SDMMC_SelectCard(card->host.base, card->host.transfer, card->relativeAddress, isSelected); -} - -static status_t inline SD_SendApplicationCmd(sd_card_t *card, uint32_t relativeAddress) -{ - assert(card); - - return SDMMC_SendApplicationCommand(card->host.base, card->host.transfer, relativeAddress); -} - -static status_t inline SD_GoIdle(sd_card_t *card) -{ - assert(card); - - return SDMMC_GoIdle(card->host.base, card->host.transfer); -} - -static status_t inline SD_SetBlockSize(sd_card_t *card, uint32_t blockSize) -{ - assert(card); - - return SDMMC_SetBlockSize(card->host.base, card->host.transfer, blockSize); -} - -static status_t inline SD_ExecuteTuning(sd_card_t *card) -{ - assert(card); - - return SDMMC_ExecuteTuning(card->host.base, kSD_SendTuningBlock, 64U); -} - -static status_t SD_SwitchVoltage(sd_card_t *card) -{ - assert(card); - - return SDMMC_SwitchVoltage(card->host.base, card->host.transfer); -} - -static status_t SD_Transfer(sd_card_t *card, HOST_TRANSFER *content, uint32_t retry) -{ - assert(card->host.transfer); - assert(content); - status_t error; - - do - { - error = card->host.transfer(card->host.base, content); - if (((error == HOST_RETUNING_REQUEST) || (content->command->response[0U] & kSDMMC_R1ErrorAllFlag)) && - ((card->currentTiming == kSD_TimingSDR104Mode) || (card->currentTiming == kSD_TimingSDR50Mode))) - { - /* execute re-tuning */ - if (SD_ExecuteTuning(card) != kStatus_Success) - { - error = kStatus_SDMMC_TuningFail; - } - else - { - continue; - } - } - else if (error != kStatus_Success) - { - error = kStatus_SDMMC_TransferFailed; - } - - if (retry != 0U) - { - retry--; - } - else - { - break; - } - - } while ((error != kStatus_Success) && (error != kStatus_SDMMC_TuningFail)); - - return error; -} - -static status_t SD_WaitWriteComplete(sd_card_t *card) -{ - assert(card); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - - command.index = kSDMMC_SendStatus; - command.argument = card->relativeAddress << 16U; - command.responseType = kCARD_ResponseTypeR1; - command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; - - do - { - content.command = &command; - content.data = 0U; - if (kStatus_Success != SD_Transfer(card, &content, 2U)) - { - return kStatus_SDMMC_TransferFailed; - } - - if ((command.response[0U] & kSDMMC_R1ReadyForDataFlag) && - (SDMMC_R1_CURRENT_STATE(command.response[0U]) != kSDMMC_R1StateProgram)) - { - break; - } - } while (true); - - return kStatus_Success; -} - -static status_t SD_StopTransmission(sd_card_t *card) -{ - assert(card); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - - command.index = kSDMMC_StopTransmission; - command.argument = 0U; - command.type = kCARD_CommandTypeAbort; - command.responseType = kCARD_ResponseTypeR1b; - command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; - - content.command = &command; - content.data = 0U; - if (kStatus_Success != SD_Transfer(card, &content, 1U)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -static status_t SD_SendRca(sd_card_t *card) -{ - assert(card); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - - command.index = kSD_SendRelativeAddress; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeR6; - - content.command = &command; - content.data = NULL; - if (kStatus_Success == card->host.transfer(card->host.base, &content)) - { - card->relativeAddress = (command.response[0U] >> 16U); - return kStatus_Success; - } - - return kStatus_SDMMC_TransferFailed; -} - -static status_t SD_SwitchFunction(sd_card_t *card, uint32_t mode, uint32_t group, uint32_t number, uint32_t *status) -{ - assert(card); - assert(status); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - HOST_DATA data = {0}; - - command.index = kSD_Switch; - command.argument = (mode << 31U | 0x00FFFFFFU); - command.argument &= ~((uint32_t)(0xFU) << (group * 4U)); - command.argument |= (number << (group * 4U)); - command.responseType = kCARD_ResponseTypeR1; - - data.blockSize = 64U; - data.blockCount = 1U; - data.rxData = status; - - if (kStatus_Success != SD_SetBlockSize(card, data.blockSize)) - { - return kStatus_SDMMC_SetCardBlockSizeFailed; - } - - content.command = &command; - content.data = &data; - if ((kStatus_Success != card->host.transfer(card->host.base, &content)) || - ((command.response[0U]) & kSDMMC_R1ErrorAllFlag)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -static void SD_DecodeScr(sd_card_t *card, uint32_t *rawScr) -{ - assert(card); - assert(rawScr); - - sd_scr_t *scr; - - scr = &(card->scr); - scr->scrStructure = (uint8_t)((rawScr[0U] & 0xF0000000U) >> 28U); - scr->sdSpecification = (uint8_t)((rawScr[0U] & 0xF000000U) >> 24U); - if ((uint8_t)((rawScr[0U] & 0x800000U) >> 23U)) - { - scr->flags |= kSD_ScrDataStatusAfterErase; - } - scr->sdSecurity = (uint8_t)((rawScr[0U] & 0x700000U) >> 20U); - scr->sdBusWidths = (uint8_t)((rawScr[0U] & 0xF0000U) >> 16U); - if ((uint8_t)((rawScr[0U] & 0x8000U) >> 15U)) - { - scr->flags |= kSD_ScrSdSpecification3; - } - scr->extendedSecurity = (uint8_t)((rawScr[0U] & 0x7800U) >> 10U); - scr->commandSupport = (uint8_t)(rawScr[0U] & 0x3U); - scr->reservedForManufacturer = rawScr[1U]; - /* Get specification version. */ - switch (scr->sdSpecification) - { - case 0U: - card->version = kSD_SpecificationVersion1_0; - break; - case 1U: - card->version = kSD_SpecificationVersion1_1; - break; - case 2U: - card->version = kSD_SpecificationVersion2_0; - if (card->scr.flags & kSD_ScrSdSpecification3) - { - card->version = kSD_SpecificationVersion3_0; - } - break; - default: - break; - } - if (card->scr.sdBusWidths & 0x4U) - { - card->flags |= kSD_Support4BitWidthFlag; - } - /* speed class control cmd */ - if (card->scr.commandSupport & 0x01U) - { - card->flags |= kSD_SupportSpeedClassControlCmd; - } - /* set block count cmd */ - if (card->scr.commandSupport & 0x02U) - { - card->flags |= kSD_SupportSetBlockCountCmd; - } -} - -static status_t SD_SendScr(sd_card_t *card) -{ - assert(card); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - HOST_DATA data = {0}; - uint32_t rawScr[2U] = {0U}; - - if (kStatus_Success != SD_SendApplicationCmd(card, card->relativeAddress)) - { - return kStatus_SDMMC_SendApplicationCommandFailed; - } - - command.index = kSD_ApplicationSendScr; - command.responseType = kCARD_ResponseTypeR1; - command.argument = 0U; - - data.blockSize = 8U; - data.blockCount = 1U; - data.rxData = rawScr; - - content.data = &data; - content.command = &command; - if ((kStatus_Success != card->host.transfer(card->host.base, &content)) || - ((command.response[0U]) & kSDMMC_R1ErrorAllFlag)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* SCR register data byte sequence from card is big endian(MSB first). */ - switch (card->host.config.endianMode) - { - case kHOST_EndianModeLittle: - /* In little endian mode, SD bus byte transferred first is the byte stored in lowest byte position in a - word which will cause 4 byte's sequence in a word is not consistent with their original sequence from - card. So the sequence of 4 bytes received in a word should be converted. */ - rawScr[0U] = SWAP_WORD_BYTE_SEQUENCE(rawScr[0U]); - rawScr[1U] = SWAP_WORD_BYTE_SEQUENCE(rawScr[1U]); - break; - case kHOST_EndianModeBig: - break; /* Doesn't need to switch byte sequence when decodes bytes as big endian sequence. */ - case kHOST_EndianModeHalfWordBig: - rawScr[0U] = SWAP_HALF_WROD_BYTE_SEQUENCE(rawScr[0U]); - rawScr[1U] = SWAP_HALF_WROD_BYTE_SEQUENCE(rawScr[1U]); - break; - default: - return kStatus_SDMMC_NotSupportYet; - } - memcpy(card->rawScr, rawScr, sizeof(card->rawScr)); - SD_DecodeScr(card, rawScr); - - return kStatus_Success; -} - -static status_t SD_SelectFunction(sd_card_t *card, uint32_t group, uint32_t function) -{ - assert(card); - - uint32_t functionStatus[16U] = {0U}; - uint16_t functionGroupInfo[6U] = {0}; - uint32_t currentFunctionStatus = 0U; - /* check if card support CMD6 */ - if ((card->version < kSD_SpecificationVersion1_0) || (!(card->csd.cardCommandClass & kSDMMC_CommandClassSwitch))) - { - return kStatus_SDMMC_NotSupportYet; - } - - /* Check if card support high speed mode. */ - if (kStatus_Success != SD_SwitchFunction(card, kSD_SwitchCheck, group, function, functionStatus)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* Switch function status byte sequence from card is big endian(MSB first). */ - switch (card->host.config.endianMode) - { - case kHOST_EndianModeLittle: - /* In little endian mode, SD bus byte transferred first is the byte stored in lowest byte position in - a word which will cause 4 byte's sequence in a word is not consistent with their original sequence from - card. So the sequence of 4 bytes received in a word should be converted. */ - functionStatus[0U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[0U]); - functionStatus[1U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[1U]); - functionStatus[2U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[2U]); - functionStatus[3U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[3U]); - functionStatus[4U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[4U]); - break; - case kHOST_EndianModeBig: - break; /* Doesn't need to switch byte sequence when decodes bytes as big endian sequence. */ - case kHOST_EndianModeHalfWordBig: - functionStatus[0U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[0U]); - functionStatus[1U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[1U]); - functionStatus[2U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[2U]); - functionStatus[3U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[3U]); - functionStatus[4U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[4U]); - break; - default: - return kStatus_SDMMC_NotSupportYet; - } - /* -functionStatus[0U]---bit511~bit480; - -functionStatus[1U]---bit479~bit448; - -functionStatus[2U]---bit447~bit416; - -functionStatus[3U]---bit415~bit384; - -functionStatus[4U]---bit383~bit352; - According to the "switch function status[bits 511~0]" return by switch command in mode "check function": - -Check if function 1(high speed) in function group 1 is supported by checking if bit 401 is set; - -check if function 1 is ready and can be switched by checking if bits 379~376 equal value 1; - */ - functionGroupInfo[5U] = (uint16_t)functionStatus[0U]; - functionGroupInfo[4U] = (uint16_t)(functionStatus[1U] >> 16U); - functionGroupInfo[3U] = (uint16_t)(functionStatus[1U]); - functionGroupInfo[2U] = (uint16_t)(functionStatus[2U] >> 16U); - functionGroupInfo[1U] = (uint16_t)(functionStatus[2U]); - functionGroupInfo[0U] = (uint16_t)(functionStatus[3U] >> 16U); - currentFunctionStatus = ((functionStatus[3U] & 0xFFU) << 8U) | (functionStatus[4U] >> 24U); - - /* check if function is support */ - if (((functionGroupInfo[group] & (1 << function)) == 0U) || - ((currentFunctionStatus >> (group * 4U)) & 0xFU) != function) - { - return kStatus_SDMMC_CardNotSupport; - } - - /* Switch to high speed mode. */ - if (kStatus_Success != SD_SwitchFunction(card, kSD_SwitchSet, group, function, functionStatus)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* Switch function status byte sequence from card is big endian(MSB first). */ - switch (card->host.config.endianMode) - { - case kHOST_EndianModeLittle: - /* In little endian mode is little endian, SD bus byte transferred first is the byte stored in lowest byte - position in a word which will cause 4 byte's sequence in a word is not consistent with their original - sequence from card. So the sequence of 4 bytes received in a word should be converted. */ - functionStatus[3U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[3U]); - functionStatus[4U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[4U]); - break; - case kHOST_EndianModeBig: - break; /* Doesn't need to switch byte sequence when decodes bytes as big endian sequence. */ - case kHOST_EndianModeHalfWordBig: - functionStatus[3U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[3U]); - functionStatus[4U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[4U]); - break; - default: - return kStatus_SDMMC_NotSupportYet; - } - /* According to the "switch function status[bits 511~0]" return by switch command in mode "set function": - -check if group 1 is successfully changed to function 1 by checking if bits 379~376 equal value 1; - */ - currentFunctionStatus = ((functionStatus[3U] & 0xFFU) << 8U) | (functionStatus[4U] >> 24U); - - if (((currentFunctionStatus >> (group * 4U)) & 0xFU) != function) - { - return kStatus_SDMMC_SwitchFailed; - } - - return kStatus_Success; -} - -static status_t SD_SetDataBusWidth(sd_card_t *card, sd_data_bus_width_t width) -{ - assert(card); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - - if (kStatus_Success != SD_SendApplicationCmd(card, card->relativeAddress)) - { - return kStatus_SDMMC_SendApplicationCommandFailed; - } - - command.index = kSD_ApplicationSetBusWdith; - command.responseType = kCARD_ResponseTypeR1; - switch (width) - { - case kSD_DataBusWidth1Bit: - command.argument = 0U; - break; - case kSD_DataBusWidth4Bit: - command.argument = 2U; - break; - default: - return kStatus_InvalidArgument; - } - - content.command = &command; - content.data = NULL; - if ((kStatus_Success != card->host.transfer(card->host.base, &content)) || - ((command.response[0U]) & kSDMMC_R1ErrorAllFlag)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -static void SD_DecodeCsd(sd_card_t *card, uint32_t *rawCsd) -{ - assert(card); - assert(rawCsd); - - sd_csd_t *csd; - - csd = &(card->csd); - csd->csdStructure = (uint8_t)((rawCsd[3U] & 0xC0000000U) >> 30U); - csd->dataReadAccessTime1 = (uint8_t)((rawCsd[3U] & 0xFF0000U) >> 16U); - csd->dataReadAccessTime2 = (uint8_t)((rawCsd[3U] & 0xFF00U) >> 8U); - csd->transferSpeed = (uint8_t)(rawCsd[3U] & 0xFFU); - csd->cardCommandClass = (uint16_t)((rawCsd[2U] & 0xFFF00000U) >> 20U); - csd->readBlockLength = (uint8_t)((rawCsd[2U] & 0xF0000U) >> 16U); - if (rawCsd[2U] & 0x8000U) - { - csd->flags |= kSD_CsdReadBlockPartialFlag; - } - if (rawCsd[2U] & 0x4000U) - { - csd->flags |= kSD_CsdReadBlockPartialFlag; - } - if (rawCsd[2U] & 0x2000U) - { - csd->flags |= kSD_CsdReadBlockMisalignFlag; - } - if (rawCsd[2U] & 0x1000U) - { - csd->flags |= kSD_CsdDsrImplementedFlag; - } - switch (csd->csdStructure) - { - case 0: - csd->deviceSize = (uint32_t)((rawCsd[2U] & 0x3FFU) << 2U); - csd->deviceSize |= (uint32_t)((rawCsd[1U] & 0xC0000000U) >> 30U); - csd->readCurrentVddMin = (uint8_t)((rawCsd[1U] & 0x38000000U) >> 27U); - csd->readCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x7000000U) >> 24U); - csd->writeCurrentVddMin = (uint8_t)((rawCsd[1U] & 0xE00000U) >> 20U); - csd->writeCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x1C0000U) >> 18U); - csd->deviceSizeMultiplier = (uint8_t)((rawCsd[1U] & 0x38000U) >> 15U); - - /* Get card total block count and block size. */ - card->blockCount = ((csd->deviceSize + 1U) << (csd->deviceSizeMultiplier + 2U)); - card->blockSize = (1U << (csd->readBlockLength)); - if (card->blockSize != FSL_SDMMC_DEFAULT_BLOCK_SIZE) - { - card->blockCount = (card->blockCount * card->blockSize); - card->blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; - card->blockCount = (card->blockCount / card->blockSize); - } - break; - case 1: - card->blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; - - csd->deviceSize = (uint32_t)((rawCsd[2U] & 0x3FU) << 16U); - csd->deviceSize |= (uint32_t)((rawCsd[1U] & 0xFFFF0000U) >> 16U); - if (csd->deviceSize >= 0xFFFFU) - { - card->flags |= kSD_SupportSdxcFlag; - } - - card->blockCount = ((csd->deviceSize + 1U) * 1024U); - break; - default: - break; - } - if ((uint8_t)((rawCsd[1U] & 0x4000U) >> 14U)) - { - csd->flags |= kSD_CsdEraseBlockEnabledFlag; - } - csd->eraseSectorSize = (uint8_t)((rawCsd[1U] & 0x3F80U) >> 7U); - csd->writeProtectGroupSize = (uint8_t)(rawCsd[1U] & 0x7FU); - if ((uint8_t)(rawCsd[0U] & 0x80000000U)) - { - csd->flags |= kSD_CsdWriteProtectGroupEnabledFlag; - } - csd->writeSpeedFactor = (uint8_t)((rawCsd[0U] & 0x1C000000U) >> 26U); - csd->writeBlockLength = (uint8_t)((rawCsd[0U] & 0x3C00000U) >> 22U); - if ((uint8_t)((rawCsd[0U] & 0x200000U) >> 21U)) - { - csd->flags |= kSD_CsdWriteBlockPartialFlag; - } - if ((uint8_t)((rawCsd[0U] & 0x8000U) >> 15U)) - { - csd->flags |= kSD_CsdFileFormatGroupFlag; - } - if ((uint8_t)((rawCsd[0U] & 0x4000U) >> 14U)) - { - csd->flags |= kSD_CsdCopyFlag; - } - if ((uint8_t)((rawCsd[0U] & 0x2000U) >> 13U)) - { - csd->flags |= kSD_CsdPermanentWriteProtectFlag; - } - if ((uint8_t)((rawCsd[0U] & 0x1000U) >> 12U)) - { - csd->flags |= kSD_CsdTemporaryWriteProtectFlag; - } - csd->fileFormat = (uint8_t)((rawCsd[0U] & 0xC00U) >> 10U); -} - -static status_t SD_SendCsd(sd_card_t *card) -{ - assert(card); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - - command.index = kSDMMC_SendCsd; - command.argument = (card->relativeAddress << 16U); - command.responseType = kCARD_ResponseTypeR2; - - content.command = &command; - content.data = NULL; - if (kStatus_Success == card->host.transfer(card->host.base, &content)) - { - memcpy(card->rawCsd, command.response, sizeof(card->rawCsd)); - /* The response is from bit 127:8 in R2, corrisponding to command.response[3U]:command.response[0U][31U:8]. */ - SD_DecodeCsd(card, command.response); - - return kStatus_Success; - } - - return kStatus_SDMMC_TransferFailed; -} - -static void SD_DecodeCid(sd_card_t *card, uint32_t *rawCid) -{ - assert(card); - assert(rawCid); - - sd_cid_t *cid; - - cid = &(card->cid); - cid->manufacturerID = (uint8_t)((rawCid[3U] & 0xFF000000U) >> 24U); - cid->applicationID = (uint16_t)((rawCid[3U] & 0xFFFF00U) >> 8U); - - cid->productName[0U] = (uint8_t)((rawCid[3U] & 0xFFU)); - cid->productName[1U] = (uint8_t)((rawCid[2U] & 0xFF000000U) >> 24U); - cid->productName[2U] = (uint8_t)((rawCid[2U] & 0xFF0000U) >> 16U); - cid->productName[3U] = (uint8_t)((rawCid[2U] & 0xFF00U) >> 8U); - cid->productName[4U] = (uint8_t)((rawCid[2U] & 0xFFU)); - - cid->productVersion = (uint8_t)((rawCid[1U] & 0xFF000000U) >> 24U); - - cid->productSerialNumber = (uint32_t)((rawCid[1U] & 0xFFFFFFU) << 8U); - cid->productSerialNumber |= (uint32_t)((rawCid[0U] & 0xFF000000U) >> 24U); - - cid->manufacturerData = (uint16_t)((rawCid[0U] & 0xFFF00U) >> 8U); -} - -static status_t SD_AllSendCid(sd_card_t *card) -{ - assert(card); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - - command.index = kSDMMC_AllSendCid; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeR2; - - content.command = &command; - content.data = NULL; - if (kStatus_Success == card->host.transfer(card->host.base, &content)) - { - memcpy(card->rawCid, command.response, sizeof(card->rawCid)); - SD_DecodeCid(card, command.response); - - return kStatus_Success; - } - - return kStatus_SDMMC_TransferFailed; -} - -static status_t SD_ApplicationSendOperationCondition(sd_card_t *card, uint32_t argument) -{ - assert(card); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - status_t error = kStatus_Fail; - uint32_t i = FSL_SDMMC_MAX_VOLTAGE_RETRIES; - - command.index = kSD_ApplicationSendOperationCondition; - command.argument = argument; - command.responseType = kCARD_ResponseTypeR3; - - while (i--) - { - if (kStatus_Success != SD_SendApplicationCmd(card, 0U)) - { - continue; - } - - content.command = &command; - content.data = NULL; - if (kStatus_Success != card->host.transfer(card->host.base, &content)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* Wait until card exit busy state. */ - if (command.response[0U] & kSD_OcrPowerUpBusyFlag) - { - /* high capacity check */ - if (command.response[0U] & kSD_OcrCardCapacitySupportFlag) - { - card->flags |= kSD_SupportHighCapacityFlag; - } - /* 1.8V support */ - if (command.response[0U] & kSD_OcrSwitch18AcceptFlag) - { - card->flags |= kSD_SupportVoltage180v; - } - error = kStatus_Success; - card->ocr = command.response[0U]; - break; - } - error = kStatus_Timeout; - } - - return error; -} - -static status_t SD_SendInterfaceCondition(sd_card_t *card) -{ - assert(card); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - uint32_t i = FSL_SDMMC_MAX_CMD_RETRIES; - status_t error; - - command.index = kSD_SendInterfaceCondition; - command.argument = 0x1AAU; - command.responseType = kCARD_ResponseTypeR7; - - content.command = &command; - content.data = NULL; - do - { - if (kStatus_Success != card->host.transfer(card->host.base, &content)) - { - error = kStatus_SDMMC_TransferFailed; - } - else - { - if ((command.response[0U] & 0xFFU) != 0xAAU) - { - error = kStatus_SDMMC_CardNotSupport; - } - else - { - error = kStatus_Success; - } - } - } while (--i && (error != kStatus_Success)); - - return error; -} - -static status_t SD_SelectBusTiming(sd_card_t *card) -{ - assert(card); - - status_t error = kStatus_SDMMC_SwitchBusTimingFailed; - - if (card->operationVoltage != kCARD_OperationVoltage180V) - { - /* Switch the card to high speed mode */ - if (card->host.capability.flags & kHOST_SupportHighSpeed) - { - /* group 1, function 1 ->high speed mode*/ - error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR25HighSpeed); - /* If the result isn't "switching to high speed mode(50MHZ) successfully or card doesn't support high speed - * mode". Return failed status. */ - if (error == kStatus_Success) - { - card->currentTiming = kSD_TimingSDR25HighSpeedMode; - card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_50MHZ); - } - } - else - { - /* if not support high speed, keep the card work at default mode */ - return kStatus_Success; - } - } - /* card is in UHS_I mode */ - else if ((kHOST_SupportSDR104 != HOST_NOT_SUPPORT) || (kHOST_SupportSDR50 != HOST_NOT_SUPPORT) || - (kHOST_SupportDDR50 != HOST_NOT_SUPPORT)) - { - switch (card->currentTiming) - { - /* if not select timing mode, sdmmc will handle it automatically*/ - case kSD_TimingSDR12DefaultMode: - case kSD_TimingSDR104Mode: - error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR104); - if (error == kStatus_Success) - { - card->currentTiming = kSD_TimingSDR104Mode; - card->busClock_Hz = - HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, HOST_SUPPORT_SDR104_FREQ); - break; - } - case kSD_TimingDDR50Mode: - error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionDDR50); - if (error == kStatus_Success) - { - card->currentTiming = kSD_TimingDDR50Mode; - card->busClock_Hz = - HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_100MHZ); - HOST_ENABLE_DDR_MODE(card->host.base, true); - } - break; - case kSD_TimingSDR50Mode: - error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR50); - if (error == kStatus_Success) - { - card->currentTiming = kSD_TimingSDR50Mode; - card->busClock_Hz = - HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_100MHZ); - } - break; - case kSD_TimingSDR25HighSpeedMode: - error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR25HighSpeed); - if (error == kStatus_Success) - { - card->currentTiming = kSD_TimingSDR25HighSpeedMode; - card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_50MHZ); - } - break; - - default: - break; - } - } - else - { - } - - return error; -} - -static status_t SD_SetDriverStrength(sd_card_t *card, sd_driver_strength_t driverStrength) -{ - assert(card); - - status_t error; - uint32_t strength = driverStrength; - - error = SD_SelectFunction(card, kSD_GroupDriverStrength, strength); - - return error; -} - -static status_t SD_SetMaxCurrent(sd_card_t *card, sd_max_current_t maxCurrent) -{ - assert(card); - - status_t error; - uint32_t current = maxCurrent; - - error = SD_SelectFunction(card, kSD_GroupCurrentLimit, current); - - return error; -} - -static status_t SD_Read(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount) -{ - assert(card); - assert(buffer); - assert(blockCount); - assert(blockSize); - assert(blockSize == FSL_SDMMC_DEFAULT_BLOCK_SIZE); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - HOST_DATA data = {0}; - status_t error; - - if (((card->flags & kSD_SupportHighCapacityFlag) && (blockSize != 512U)) || (blockSize > card->blockSize) || - (blockSize > card->host.capability.maxBlockLength) || (blockSize % 4)) - { - return kStatus_SDMMC_CardNotSupport; - } - - /* Wait for the card write process complete because of that card read process and write process use one buffer. */ - if (kStatus_Success != SD_WaitWriteComplete(card)) - { - return kStatus_SDMMC_WaitWriteCompleteFailed; - } - - data.blockSize = blockSize; - data.blockCount = blockCount; - data.rxData = (uint32_t *)buffer; - - command.index = kSDMMC_ReadMultipleBlock; - if (data.blockCount == 1U) - { - command.index = kSDMMC_ReadSingleBlock; - } - command.argument = startBlock; - if (!(card->flags & kSD_SupportHighCapacityFlag)) - { - command.argument *= data.blockSize; - } - command.responseType = kCARD_ResponseTypeR1; - command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; - - content.command = &command; - content.data = &data; - - error = SD_Transfer(card, &content, 1U); - if (kStatus_Success != error) - { - return error; - } - - /* Send STOP_TRANSMISSION command in multiple block transmission and host's AUTO_COMMAND12 isn't enabled. */ - if ((data.blockCount > 1U) && (!(data.enableAutoCommand12))) - { - if (kStatus_Success != SD_StopTransmission(card)) - { - return kStatus_SDMMC_StopTransmissionFailed; - } - } - - return kStatus_Success; -} - -static status_t SD_Write( - sd_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount) -{ - assert(card); - assert(buffer); - assert(blockCount); - assert(blockSize); - assert(blockSize == FSL_SDMMC_DEFAULT_BLOCK_SIZE); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - HOST_DATA data = {0}; - status_t error; - - if (((card->flags & kSD_SupportHighCapacityFlag) && (blockSize != 512U)) || (blockSize > card->blockSize) || - (blockSize > card->host.capability.maxBlockLength) || (blockSize % 4U)) - { - return kStatus_SDMMC_CardNotSupport; - } - - /* Wait for the card's buffer to be not full to write to improve the write performance. */ - while ((GET_HOST_STATUS(card->host.base) & CARD_DATA0_STATUS_MASK) != CARD_DATA0_NOT_BUSY) - { - } - - /* Wait for the card write process complete because of that card read process and write process use one buffer.*/ - if (kStatus_Success != SD_WaitWriteComplete(card)) - { - return kStatus_SDMMC_WaitWriteCompleteFailed; - } - - data.blockSize = blockSize; - data.blockCount = blockCount; - data.txData = (const uint32_t *)buffer; - - command.index = kSDMMC_WriteMultipleBlock; - if (data.blockCount == 1U) - { - command.index = kSDMMC_WriteSingleBlock; - } - command.argument = startBlock; - if (!(card->flags & kSD_SupportHighCapacityFlag)) - { - command.argument *= data.blockSize; - } - command.responseType = kCARD_ResponseTypeR1; - command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; - - content.command = &command; - content.data = &data; - - error = SD_Transfer(card, &content, 1U); - if (kStatus_Success != error) - { - return error; - } - - /* Send STOP_TRANSMISSION command in multiple block transmission and host's AUTO_COMMAND12 isn't enabled. */ - if ((data.blockCount > 1U) && (!(data.enableAutoCommand12))) - { - if (kStatus_Success != SD_StopTransmission(card)) - { - return kStatus_SDMMC_StopTransmissionFailed; - } - } - - return kStatus_Success; -} - -static status_t SD_Erase(sd_card_t *card, uint32_t startBlock, uint32_t blockCount) -{ - assert(card); - assert(blockCount); - - uint32_t eraseBlockStart; - uint32_t eraseBlockEnd; - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - - /* Wait for the card's buffer to be not full to write to improve the write performance. */ - while ((GET_HOST_STATUS(card->host.base) & CARD_DATA0_STATUS_MASK) != CARD_DATA0_NOT_BUSY) - { - } - - /* Wait for the card write process complete because of that card read process and write process use one buffer.*/ - if (kStatus_Success != SD_WaitWriteComplete(card)) - { - return kStatus_SDMMC_WaitWriteCompleteFailed; - } - - eraseBlockStart = startBlock; - eraseBlockEnd = eraseBlockStart + blockCount - 1U; - if (!(card->flags & kSD_SupportHighCapacityFlag)) - { - eraseBlockStart = eraseBlockStart * FSL_SDMMC_DEFAULT_BLOCK_SIZE; - eraseBlockEnd = eraseBlockEnd * FSL_SDMMC_DEFAULT_BLOCK_SIZE; - } - - /* Send ERASE_WRITE_BLOCK_START command to set the start block number to erase. */ - command.index = kSD_EraseWriteBlockStart; - command.argument = eraseBlockStart; - command.responseType = kCARD_ResponseTypeR1; - command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; - - content.command = &command; - content.data = NULL; - - if (kStatus_Success != SD_Transfer(card, &content, 1U)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* Send ERASE_WRITE_BLOCK_END command to set the end block number to erase. */ - command.index = kSD_EraseWriteBlockEnd; - command.argument = eraseBlockEnd; - - content.command = &command; - content.data = NULL; - if (kStatus_Success != SD_Transfer(card, &content, 0U)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* Send ERASE command to start erase process. */ - command.index = kSDMMC_Erase; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeR1b; - command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; - - content.command = &command; - content.data = NULL; - if (kStatus_Success != SD_Transfer(card, &content, 0U)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t SD_Init(sd_card_t *card) -{ - assert(card); - - uint32_t applicationCommand41Argument = 0U; - status_t error = kStatus_Success; - card_operation_voltage_t tempVoltage = kCARD_OperationVoltageNone; - - if (!card->isHostReady) - { - error = HOST_Init(&(card->host)); - if (error != kStatus_Success) - { - return error; - } - /* set the host status flag, after the card re-plug in, don't need init host again */ - card->isHostReady = true; - } - - /* voltage switch to normal but not 1.8V */ - HOST_SWITCH_VOLTAGE180V(card->host.base, false); - /* Disable DDR mode */ - HOST_ENABLE_DDR_MODE(card->host.base, false); - /* disable tuning */ - HOST_EXECUTE_STANDARD_TUNING_ENABLE(card->host.base, false); - /* set data bus width to 1bit */ - HOST_SET_CARD_BUS_WIDTH(card->host.base, kHOST_DATABUSWIDTH1BIT); - - /*detect card insert*/ - error = CardInsertDetect(card->host.base); - if (error != kStatus_Success) - { - return error; - } - /* delay for power up ramp time*/ - SDMMC_Delay(200U); - /*set card freq to 400KHZ*/ - card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SDMMC_CLOCK_400KHZ); - /* send card active */ - HOST_SEND_CARD_ACTIVE(card->host.base, 100U); - /* reset variables */ - card->flags = 0U; - - if (kStatus_Success != SD_GoIdle(card)) - { - return kStatus_SDMMC_GoIdleFailed; - } - - /* Hand-shaking with card to validate the interface voltage range. */ - /* Get host capability. */ - GET_HOST_CAPABILITY(card->host.base, &(card->host.capability)); - if (kHOST_SupportV330 != HOST_NOT_SUPPORT) - { - applicationCommand41Argument |= (kSD_OcrVdd32_33Flag | kSD_OcrVdd33_34Flag); - tempVoltage = kCARD_OperationVoltage330V; - } - else if (kHOST_SupportV300 != HOST_NOT_SUPPORT) - { - applicationCommand41Argument |= kSD_OcrVdd29_30Flag; - tempVoltage = kCARD_OperationVoltage330V; - } - - /* allow user select the work voltage, if not select, sdmmc will handle it automatically */ - if ((kHOST_SupportV180 != HOST_NOT_SUPPORT) && ((card->operationVoltage == kCARD_OperationVoltageNone) || - (card->operationVoltage == kCARD_OperationVoltage180V))) - { - /*switch to 1.8V request*/ - applicationCommand41Argument |= kSD_OcrSwitch18RequestFlag; - } - - /* Check card's supported interface condition. */ - if (kStatus_Success == SD_SendInterfaceCondition(card)) - { - /* SDHC or SDXC card */ - applicationCommand41Argument |= kSD_OcrHostCapacitySupportFlag; - card->flags |= kSD_SupportSdhcFlag; - } - else - { - /* SDSC card */ - if (kStatus_Success != SD_GoIdle(card)) - { - return kStatus_SDMMC_GoIdleFailed; - } - } - /* Set card interface condition according to SDHC capability and card's supported interface condition. */ - if (kStatus_Success != SD_ApplicationSendOperationCondition(card, applicationCommand41Argument)) - { - return kStatus_SDMMC_HandShakeOperationConditionFailed; - } - - /* check if card support 1.8V */ - if ((card->flags & kSD_SupportVoltage180v)) - { - if (kStatus_Success != SD_SwitchVoltage(card)) - { - return kStatus_SDMMC_InvalidVoltage; - } - card->operationVoltage = kCARD_OperationVoltage180V; - } - else - { - card->operationVoltage = tempVoltage; - } - - /* Initialize card if the card is SD card. */ - if (kStatus_Success != SD_AllSendCid(card)) - { - return kStatus_SDMMC_AllSendCidFailed; - } - if (kStatus_Success != SD_SendRca(card)) - { - return kStatus_SDMMC_SendRelativeAddressFailed; - } - if (kStatus_Success != SD_SendCsd(card)) - { - return kStatus_SDMMC_SendCsdFailed; - } - if (kStatus_Success != SD_SelectCard(card, true)) - { - return kStatus_SDMMC_SelectCardFailed; - } - - if (kStatus_Success != SD_SendScr(card)) - { - return kStatus_SDMMC_SendScrFailed; - } - - /* Set to max frequency in non-high speed mode. */ - card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_25MHZ); - - /* Set to 4-bit data bus mode. */ - /*if (((card->host.capability.flags) & kHOST_Support4BitBusWidth) && (card->flags & kSD_Support4BitWidthFlag)) - { - if (kStatus_Success != SD_SetDataBusWidth(card, kSD_DataBusWidth4Bit)) - { - return kStatus_SDMMC_SetDataBusWidthFailed; - } - HOST_SET_CARD_BUS_WIDTH(card->host.base, kHOST_DATABUSWIDTH4BIT); - }*/ - - /* set sd card driver strength */ - SD_SetDriverStrength(card, card->driverStrength); - /* set sd card current limit */ - SD_SetMaxCurrent(card, card->maxCurrent); - - /* set block size */ - if (SD_SetBlockSize(card, FSL_SDMMC_DEFAULT_BLOCK_SIZE)) - { - return kStatus_SDMMC_SetCardBlockSizeFailed; - } - - /* select bus timing */ - if (kStatus_Success != SD_SelectBusTiming(card)) - { - return kStatus_SDMMC_SwitchBusTimingFailed; - } - - /* SDR50 and SDR104 mode need tuning */ - if ((card->currentTiming == kSD_TimingSDR50Mode) || (card->currentTiming == kSD_TimingSDR104Mode)) - { - /* config IO strength in IOMUX*/ - if (card->currentTiming == kSD_TimingSDR50Mode) - { - HOST_CONFIG_SD_IO(CARD_BUS_FREQ_100MHZ1, CARD_BUS_STRENGTH_7); - } - else - { - HOST_CONFIG_SD_IO(CARD_BUS_FREQ_200MHZ, CARD_BUS_STRENGTH_7); - } - /* execute tuning */ - if (SD_ExecuteTuning(card) != kStatus_Success) - { - return kStatus_SDMMC_TuningFail; - } - } - else if (card->currentTiming == kSD_TimingDDR50Mode) - { - HOST_CONFIG_SD_IO(CARD_BUS_FREQ_100MHZ1, CARD_BUS_STRENGTH_3); - } - - return kStatus_Success; -} - -void SD_Deinit(sd_card_t *card) -{ - assert(card); - - SD_SelectCard(card, false); - HOST_Deinit(&(card->host)); - /* should re-init host */ - card->isHostReady = false; -} - -bool SD_CheckReadOnly(sd_card_t *card) -{ - assert(card); - - return ((card->csd.flags & kSD_CsdPermanentWriteProtectFlag) || - (card->csd.flags & kSD_CsdTemporaryWriteProtectFlag)); -} - -status_t SD_ReadBlocks(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) -{ - assert(card); - assert(buffer); - assert(blockCount); - - uint32_t blockCountOneTime; - uint32_t blockLeft; - uint32_t blockDone; - uint8_t *nextBuffer; - status_t error; - - if ((blockCount + startBlock) > card->blockCount) - { - return kStatus_InvalidArgument; - } - - blockLeft = blockCount; - blockDone = 0U; - while (blockLeft) - { - if (blockLeft > card->host.capability.maxBlockCount) - { - blockLeft = (blockLeft - card->host.capability.maxBlockCount); - blockCountOneTime = card->host.capability.maxBlockCount; - } - else - { - blockCountOneTime = blockLeft; - blockLeft = 0U; - } - - nextBuffer = (buffer + blockDone * FSL_SDMMC_DEFAULT_BLOCK_SIZE); - error = SD_Read(card, nextBuffer, (startBlock + blockDone), FSL_SDMMC_DEFAULT_BLOCK_SIZE, blockCountOneTime); - if (error != kStatus_Success) - { - return error; - } - - blockDone += blockCountOneTime; - } - - return kStatus_Success; -} - -status_t SD_WriteBlocks(sd_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) -{ - assert(card); - assert(buffer); - assert(blockCount); - - uint32_t blockCountOneTime; /* The block count can be wrote in one time sending WRITE_BLOCKS command. */ - uint32_t blockLeft; /* Left block count to be wrote. */ - uint32_t blockDone = 0U; /* The block count has been wrote. */ - const uint8_t *nextBuffer; - status_t error; - - if ((blockCount + startBlock) > card->blockCount) - { - return kStatus_InvalidArgument; - } - - blockLeft = blockCount; - while (blockLeft) - { - if (blockLeft > card->host.capability.maxBlockCount) - { - blockLeft = (blockLeft - card->host.capability.maxBlockCount); - blockCountOneTime = card->host.capability.maxBlockCount; - } - else - { - blockCountOneTime = blockLeft; - blockLeft = 0U; - } - - nextBuffer = (buffer + blockDone * FSL_SDMMC_DEFAULT_BLOCK_SIZE); - error = SD_Write(card, nextBuffer, (startBlock + blockDone), FSL_SDMMC_DEFAULT_BLOCK_SIZE, blockCountOneTime); - if (error != kStatus_Success) - { - return error; - } - - blockDone += blockCountOneTime; - } - - return kStatus_Success; -} - -status_t SD_EraseBlocks(sd_card_t *card, uint32_t startBlock, uint32_t blockCount) -{ - assert(card); - assert(blockCount); - - uint32_t blockCountOneTime; /* The block count can be erased in one time sending ERASE_BLOCKS command. */ - uint32_t blockDone = 0U; /* The block count has been erased. */ - uint32_t blockLeft; /* Left block count to be erase. */ - status_t error; - - if ((blockCount + startBlock) > card->blockCount) - { - return kStatus_InvalidArgument; - } - - blockLeft = blockCount; - while (blockLeft) - { - if (blockLeft > (card->csd.eraseSectorSize + 1U)) - { - blockCountOneTime = card->csd.eraseSectorSize + 1U; - blockLeft = blockLeft - blockCountOneTime; - } - else - { - blockCountOneTime = blockLeft; - blockLeft = 0U; - } - - error = SD_Erase(card, (startBlock + blockDone), blockCountOneTime); - if (error != kStatus_Success) - { - return error; - } - - blockDone += blockCountOneTime; - } - - return kStatus_Success; -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sd_event.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sd_event.c deleted file mode 100644 index 020c19953c7..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sd_event.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_sd_event.h" -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get event instance. - * @param eventType The event type - * @return The event instance's pointer. - */ -static volatile uint32_t *EVENT_GetInstance(event_t eventType); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Card detect event. */ -static volatile uint32_t g_eventCardDetect; - -/*! @brief transfer complete event. */ -static volatile uint32_t g_eventTransferComplete; - -/*! @brief Time variable unites as milliseconds. */ -//volatile uint32_t g_timeMilliseconds; - -/******************************************************************************* - * Code - ******************************************************************************/ -void EVENT_InitTimer(void) -{ - /* Set systick reload value to generate 1ms interrupt */ - //SysTick_Config(CLOCK_GetFreq(kCLOCK_CoreSysClk) / 1000U); -} - -//void SysTick_Handler(void) -//{ -// g_timeMilliseconds++; -//} - -static volatile uint32_t *EVENT_GetInstance(event_t eventType) -{ - volatile uint32_t *event; - - switch (eventType) - { - case kEVENT_TransferComplete: - event = &g_eventTransferComplete; - break; - case kEVENT_CardDetect: - event = &g_eventCardDetect; - break; - default: - event = NULL; - break; - } - - return event; -} - -bool EVENT_Create(event_t eventType) -{ - volatile uint32_t *event = EVENT_GetInstance(eventType); - - if (event) - { - *event = 0; - return true; - } - else - { - return false; - } -} - -bool EVENT_Wait(event_t eventType, uint32_t timeoutMilliseconds) -{ - uint32_t startTime; - uint32_t elapsedTime; - - volatile uint32_t *event = EVENT_GetInstance(eventType); - - if (timeoutMilliseconds && event) - { - startTime = rt_tick_get() * 1000 / RT_TICK_PER_SECOND; - do - { - elapsedTime = (rt_tick_get() * 1000 / RT_TICK_PER_SECOND - startTime); - } while ((*event == 0U) && (elapsedTime < timeoutMilliseconds)); - *event = 0U; - - return ((elapsedTime < timeoutMilliseconds) ? true : false); - } - else - { - return false; - } -} - -bool EVENT_Notify(event_t eventType) -{ - volatile uint32_t *event = EVENT_GetInstance(eventType); - - if (event) - { - *event = 1U; - return true; - } - else - { - return false; - } -} - -void EVENT_Delete(event_t eventType) -{ - volatile uint32_t *event = EVENT_GetInstance(eventType); - - if (event) - { - *event = 0U; - } -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sdio.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sdio.c deleted file mode 100644 index a19d2238ae7..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sdio.c +++ /dev/null @@ -1,1017 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_card.h" -#include "fsl_sdmmc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define SDIO_COMMON_CIS_TUPLE_NUM (3U) /*!< define the tuple number will be read during init */ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief send card operation condition - * @param card Card descriptor. - * @param command argment - * argument = 0U , means to get the operation condition - * argument !=0 , set the operation condition register - */ -static status_t SDIO_SendOperationCondition(sdio_card_t *card, uint32_t argument); - -/*! - * @brief card Send relative address - * @param card Card descriptor. - */ -static status_t SDIO_SendRca(sdio_card_t *card); - -/*! - * @brief card select card - * @param card Card descriptor. - * @param select/diselect flag - */ -static status_t inline SDIO_SelectCard(sdio_card_t *card, bool isSelected); - -/*! - * @brief decode CIS - * @param card Card descriptor. - * @param func number - * @param data buffer pointer - * @param tuple code - * @param tuple link - */ -static status_t SDIO_DecodeCIS( - sdio_card_t *card, sdio_func_num_t func, uint8_t *dataBuffer, uint32_t tplCode, uint32_t tplLink); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* define the tuple list */ -static const uint32_t g_tupleList[SDIO_COMMON_CIS_TUPLE_NUM] = { - SDIO_TPL_CODE_MANIFID, SDIO_TPL_CODE_FUNCID, SDIO_TPL_CODE_FUNCE, -}; - -/******************************************************************************* - * Code - ******************************************************************************/ -static status_t inline SDIO_SelectCard(sdio_card_t *card, bool isSelected) -{ - assert(card); - - return SDMMC_SelectCard(card->host.base, card->host.transfer, card->relativeAddress, isSelected); -} - -static status_t SDIO_SendRca(sdio_card_t *card) -{ - assert(card); - - uint32_t i = FSL_SDMMC_MAX_CMD_RETRIES; - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - - command.index = kSDIO_SendRelativeAddress; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeR6; - command.responseErrorFlags = kSDIO_StatusR6Error | kSDIO_StatusIllegalCmd | kSDIO_StatusCmdCRCError; - - content.command = &command; - content.data = NULL; - - while (--i) - { - if (kStatus_Success == card->host.transfer(card->host.base, &content)) - { - /* check illegal state and cmd CRC error, may be the voltage or clock not stable, retry the cmd*/ - if (command.response[0U] & (kSDIO_StatusIllegalCmd | kSDIO_StatusCmdCRCError)) - { - continue; - } - - card->relativeAddress = (command.response[0U] >> 16U); - - return kStatus_Success; - } - } - - return kStatus_SDMMC_TransferFailed; -} - -status_t SDIO_CardInActive(sdio_card_t *card) -{ - assert(card); - - return SDMMC_SetCardInactive(card->host.base, card->host.transfer); -} - -static status_t SDIO_SendOperationCondition(sdio_card_t *card, uint32_t argument) -{ - assert(card); - - HOST_TRANSFER content = {0U}; - HOST_COMMAND command = {0U}; - uint32_t i = FSL_SDMMC_MAX_VOLTAGE_RETRIES; - - command.index = kSDIO_SendOperationCondition; - command.argument = argument; - command.responseType = kCARD_ResponseTypeR4; - - content.command = &command; - content.data = NULL; - - while (--i) - { - if (kStatus_Success != card->host.transfer(card->host.base, &content)) - { - continue; - } - - /* if argument equal 0, then should check and save the info */ - if (argument == 0U) - { - /* check if memory present */ - if ((command.response[0U] & kSDIO_OcrMemPresent) == kSDIO_OcrMemPresent) - { - card->memPresentFlag = true; - } - /* save the io number */ - card->ioTotalNumber = (command.response[0U] & kSDIO_OcrIONumber) >> 28U; - /* save the operation condition */ - card->ocr = command.response[0U] & 0xFFFFFFU; - - break; - } - /* wait the card is ready for after initialization */ - else if (command.response[0U] & kSDIO_OcrPowerUpBusyFlag) - { - break; - } - } - - return ((i != 0U) ? kStatus_Success : kStatus_Fail); -} - -status_t SDIO_IO_Write_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data, bool raw) -{ - assert(card); - assert(func <= kSDIO_FunctionNum7); - - HOST_TRANSFER content = {0U}; - HOST_COMMAND command = {0U}; - - command.index = kSDIO_RWIODirect; - command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | - ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS) | - (1U << SDIO_CMD_ARGUMENT_RW_POS) | ((raw ? 1U : 0U) << SDIO_DIRECT_CMD_ARGUMENT_RAW_POS) | - (*data & SDIO_DIRECT_CMD_DATA_MASK); - command.responseType = kCARD_ResponseTypeR5; - command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | - kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); - - content.command = &command; - content.data = NULL; - - if (kStatus_Success != card->host.transfer(card->host.base, &content)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* read data from response */ - *data = command.response[0U] & SDIO_DIRECT_CMD_DATA_MASK; - - return kStatus_Success; -} - -status_t SDIO_IO_Read_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data) -{ - assert(card); - assert(func <= kSDIO_FunctionNum7); - - HOST_TRANSFER content = {0U}; - HOST_COMMAND command = {0U}; - - command.index = kSDIO_RWIODirect; - command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | - ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS); - command.responseType = kCARD_ResponseTypeR5; - command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | - kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); - - content.command = &command; - content.data = NULL; - - if (kStatus_Success != card->host.transfer(card->host.base, &content)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* read data from response */ - *data = command.response[0U] & SDIO_DIRECT_CMD_DATA_MASK; - - return kStatus_Success; -} - -status_t SDIO_IO_Write_Extended( - sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags) -{ - assert(card); - assert(buffer); - assert(func <= kSDIO_FunctionNum7); - - HOST_TRANSFER content = {0U}; - HOST_COMMAND command = {0U}; - HOST_DATA data = {0U}; - bool blockMode = false; - bool opCode = false; - - /* check if card support block mode */ - if ((card->cccrflags & kSDIO_CCCRSupportMultiBlock) && (flags & SDIO_EXTEND_CMD_BLOCK_MODE_MASK)) - { - blockMode = true; - } - - if (flags & SDIO_EXTEND_CMD_OP_CODE_MASK) - { - opCode = true; - } - - /* check the byte size counter in non-block mode - * so you need read CIS for each function first,before you do read/write - */ - if (!blockMode) - { - if ((func == kSDIO_FunctionNum0) && (card->commonCIS.fn0MaxBlkSize != 0U) && - (count > card->commonCIS.fn0MaxBlkSize)) - { - return kStatus_SDMMC_SDIO_InvalidArgument; - } - else if ((func != kSDIO_FunctionNum0) && (card->funcCIS[func - 1U].ioMaxBlockSize != 0U) && - (count > card->funcCIS[func - 1U].ioMaxBlockSize)) - { - return kStatus_SDMMC_SDIO_InvalidArgument; - } - } - - command.index = kSDIO_RWIOExtended; - command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | - ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS) | - (1U << SDIO_CMD_ARGUMENT_RW_POS) | (count & SDIO_EXTEND_CMD_COUNT_MASK) | - ((blockMode ? 1 : 0) << SDIO_EXTEND_CMD_ARGUMENT_BLOCK_MODE_POS | - ((opCode ? 1 : 0) << SDIO_EXTEND_CMD_ARGUMENT_OP_CODE_POS)); - command.responseType = kCARD_ResponseTypeR5; - command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | - kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); - - if (blockMode) - { - if (func == kSDIO_FunctionNum0) - { - data.blockSize = card->io0blockSize; - } - else - { - data.blockSize = card->ioFBR[func - 1U].ioBlockSize; - } - data.blockCount = count; - } - else - { - data.blockSize = count; - data.blockCount = 1U; - } - data.txData = (uint32_t *)buffer; - - content.command = &command; - content.data = &data; - - if (kStatus_Success != card->host.transfer(card->host.base, &content)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t SDIO_IO_Read_Extended( - sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags) -{ - assert(card); - assert(buffer); - assert(func <= kSDIO_FunctionNum7); - - HOST_TRANSFER content = {0U}; - HOST_COMMAND command = {0U}; - HOST_DATA data = {0U}; - bool blockMode = false; - bool opCode = false; - - /* check if card support block mode */ - if ((card->cccrflags & kSDIO_CCCRSupportMultiBlock) && (flags & SDIO_EXTEND_CMD_BLOCK_MODE_MASK)) - { - blockMode = true; - } - - /* op code =0 : read/write to fixed addr - * op code =1 :read/write addr incrementing - */ - if (flags & SDIO_EXTEND_CMD_OP_CODE_MASK) - { - opCode = true; - } - - /* check the byte size counter in non-block mode - * so you need read CIS for each function first,before you do read/write - */ - if (!blockMode) - { - if ((func == kSDIO_FunctionNum0) && (card->commonCIS.fn0MaxBlkSize != 0U) && - (count > card->commonCIS.fn0MaxBlkSize)) - { - return kStatus_SDMMC_SDIO_InvalidArgument; - } - else if ((func != kSDIO_FunctionNum0) && (card->funcCIS[func - 1U].ioMaxBlockSize != 0U) && - (count > card->funcCIS[func - 1U].ioMaxBlockSize)) - { - return kStatus_SDMMC_SDIO_InvalidArgument; - } - } - - command.index = kSDIO_RWIOExtended; - command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | - ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS) | - (count & SDIO_EXTEND_CMD_COUNT_MASK) | - ((blockMode ? 1U : 0U) << SDIO_EXTEND_CMD_ARGUMENT_BLOCK_MODE_POS | - ((opCode ? 1U : 0U) << SDIO_EXTEND_CMD_ARGUMENT_OP_CODE_POS)); - command.responseType = kCARD_ResponseTypeR5; - command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | - kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); - - if (blockMode) - { - if (func == kSDIO_FunctionNum0) - { - data.blockSize = card->io0blockSize; - } - else - { - data.blockSize = card->ioFBR[func - 1U].ioBlockSize; - } - data.blockCount = count; - } - else - { - data.blockSize = count; - data.blockCount = 1U; - } - data.rxData = (uint32_t *)buffer; - - content.command = &command; - content.data = &data; - - if (kStatus_Success != card->host.transfer(card->host.base, &content)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t SDIO_GetCardCapability(sdio_card_t *card, sdio_func_num_t func) -{ - assert(card); - assert(func <= kSDIO_FunctionNum7); - - uint8_t tempBuffer[20] = {0U}; - uint32_t i = 0U; - - for (i = 0U; i < 20U; i++) - { - if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, SDIO_FBR_BASE(func) + i, &tempBuffer[i])) - { - return kStatus_SDMMC_TransferFailed; - } - } - - switch (func) - { - case kSDIO_FunctionNum0: - - card->sdVersion = tempBuffer[1U]; - card->sdioVersion = tempBuffer[0U] >> 4U; - card->cccrVersioin = tempBuffer[0U] & 0xFU; - /* continuous SPI interrupt */ - if (tempBuffer[7U] & 0x40U) - { - card->cccrflags |= kSDIO_CCCRSupportContinuousSPIInt; - } - /* card capability register */ - card->cccrflags |= (tempBuffer[8U] & 0xDFU); - /* master power control */ - if (tempBuffer[18U] & 0x01U) - { - card->cccrflags |= kSDIO_CCCRSupportMasterPowerControl; - } - /* high speed flag */ - if (tempBuffer[19U] & 0x01U) - { - card->cccrflags |= kSDIO_CCCRSupportHighSpeed; - } - /* common CIS pointer */ - card->commonCISPointer = tempBuffer[9U] | (tempBuffer[10U] << 8U) | (tempBuffer[11U] << 16U); - - break; - - case kSDIO_FunctionNum1: - case kSDIO_FunctionNum2: - case kSDIO_FunctionNum3: - case kSDIO_FunctionNum4: - case kSDIO_FunctionNum5: - case kSDIO_FunctionNum6: - case kSDIO_FunctionNum7: - card->ioFBR[func - 1U].ioStdFunctionCode = tempBuffer[0U] & 0x0FU; - card->ioFBR[func - 1U].ioExtFunctionCode = tempBuffer[1U]; - card->ioFBR[func - 1U].ioPointerToCIS = tempBuffer[9U] | (tempBuffer[10U] << 8U) | (tempBuffer[11U] << 16U); - card->ioFBR[func - 1U].ioPointerToCSA = - tempBuffer[12U] | (tempBuffer[13U] << 8U) | (tempBuffer[14U] << 16U); - if (tempBuffer[2U] & 0x01U) - { - card->ioFBR[func - 1U].flags |= kSDIO_FBRSupportPowerSelection; - } - if (tempBuffer[0U] & 0x40U) - { - card->ioFBR[func - 1U].flags |= kSDIO_FBRSupportCSA; - } - - break; - - default: - break; - } - - return kStatus_Success; -} - -status_t SDIO_SetBlockSize(sdio_card_t *card, sdio_func_num_t func, uint32_t blockSize) -{ - assert(card); - assert(func <= kSDIO_FunctionNum7); - assert(blockSize <= SDIO_MAX_BLOCK_SIZE); - - uint8_t temp = 0U; - - /* check the block size for block mode - * so you need read CIS for each function first,before you do read/write - */ - if ((func == kSDIO_FunctionNum0) && (card->commonCIS.fn0MaxBlkSize != 0U) && - (blockSize > card->commonCIS.fn0MaxBlkSize)) - { - return kStatus_SDMMC_SDIO_InvalidArgument; - } - else if ((func != kSDIO_FunctionNum0) && (card->funcCIS[func - 1U].ioMaxBlockSize != 0U) && - (blockSize > card->funcCIS[func - 1U].ioMaxBlockSize)) - { - return kStatus_SDMMC_SDIO_InvalidArgument; - } - - temp = blockSize & 0xFFU; - - if (kStatus_Success != - SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, SDIO_FBR_BASE(func) + kSDIO_RegFN0BlockSizeLow, &temp, true)) - { - return kStatus_SDMMC_SetCardBlockSizeFailed; - } - - temp = (blockSize >> 8U) & 0xFFU; - - if (kStatus_Success != - SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, SDIO_FBR_BASE(func) + kSDIO_RegFN0BlockSizeHigh, &temp, true)) - { - return kStatus_SDMMC_SetCardBlockSizeFailed; - } - - /* record the current block size */ - if (func == kSDIO_FunctionNum0) - { - card->io0blockSize = blockSize; - } - else - { - card->ioFBR[func - 1U].ioBlockSize = blockSize; - } - - return kStatus_Success; -} - -status_t SDIO_CardReset(sdio_card_t *card) -{ - uint8_t reset = 0x08U; - - return SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, kSDIO_RegIOAbort, &reset, false); -} - -status_t SDIO_SetDataBusWidth(sdio_card_t *card, sdio_bus_width_t busWidth) -{ - assert(card); - - uint8_t regBusInterface = 0U; - - /* load bus interface register */ - if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, kSDIO_RegBusInterface, ®BusInterface)) - { - return kStatus_SDMMC_TransferFailed; - } - /* set bus width */ - regBusInterface |= busWidth; - - /* write to register */ - if (kStatus_Success != - SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, kSDIO_RegBusInterface, ®BusInterface, true)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t SDIO_SwitchToHighSpeed(sdio_card_t *card) -{ - assert(card); - - uint8_t temp = 0U; - - if (card->cccrflags & kSDIO_CCCRSupportHighSpeed) - { - /* enable high speed mode */ - temp = 0x02U; - if (kStatus_Success != SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, kSDIO_RegHighSpeed, &temp, true)) - { - return kStatus_SDMMC_TransferFailed; - } - /* either EHS=0 and SHS=0 ,the card is still in default mode */ - if ((temp & 0x03U) == 0x03U) - { - /* set to 4bit data bus */ - SDIO_SetDataBusWidth(card, kSDIO_DataBus4Bit); - HOST_SET_CARD_BUS_WIDTH(card->host.base, kHOST_DATABUSWIDTH4BIT); - /* high speed mode , set freq to 50MHZ */ - card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_50MHZ); - } - else - { - return kStatus_SDMMC_SDIO_SwitchHighSpeedFail; - } - } - - return kStatus_Success; -} - -static status_t SDIO_DecodeCIS( - sdio_card_t *card, sdio_func_num_t func, uint8_t *dataBuffer, uint32_t tplCode, uint32_t tplLink) -{ - assert(card); - assert(func <= kSDIO_FunctionNum7); - - if (func == kSDIO_FunctionNum0) - { - /* only decode MANIFID,FUNCID,FUNCE here */ - if (tplCode == SDIO_TPL_CODE_MANIFID) - { - card->commonCIS.mID = dataBuffer[0U] | (dataBuffer[1U] << 8U); - card->commonCIS.mInfo = dataBuffer[2U] | (dataBuffer[3U] << 8U); - } - else if (tplCode == SDIO_TPL_CODE_FUNCID) - { - card->commonCIS.funcID = dataBuffer[0U]; - } - else if (tplCode == SDIO_TPL_CODE_FUNCE) - { - /* max transfer block size and data size */ - card->commonCIS.fn0MaxBlkSize = dataBuffer[1U] | (dataBuffer[2U] << 8U); - /* max transfer speed */ - card->commonCIS.maxTransSpeed = dataBuffer[3U]; - } - else - { - /* reserved here */ - return kStatus_Fail; - } - } - else - { - /* only decode FUNCID,FUNCE here */ - if (tplCode == SDIO_TPL_CODE_FUNCID) - { - card->funcCIS[func].funcID = dataBuffer[0U]; - } - else if (tplCode == SDIO_TPL_CODE_FUNCE) - { - if (tplLink == 0x2A) - { - card->funcCIS[func - 1U].funcInfo = dataBuffer[1U]; - card->funcCIS[func - 1U].ioVersion = dataBuffer[2U]; - card->funcCIS[func - 1U].cardPSN = - dataBuffer[3U] | (dataBuffer[4U] << 8U) | (dataBuffer[5U] << 16U) | (dataBuffer[6U] << 24U); - card->funcCIS[func - 1U].ioCSASize = - dataBuffer[7U] | (dataBuffer[8U] << 8U) | (dataBuffer[9U] << 16U) | (dataBuffer[10U] << 24U); - card->funcCIS[func - 1U].ioCSAProperty = dataBuffer[11U]; - card->funcCIS[func - 1U].ioMaxBlockSize = dataBuffer[12U] | (dataBuffer[13U] << 8U); - card->funcCIS[func - 1U].ioOCR = - dataBuffer[14U] | (dataBuffer[15U] << 8U) | (dataBuffer[16U] << 16U) | (dataBuffer[17U] << 24U); - card->funcCIS[func - 1U].ioOPMinPwr = dataBuffer[18U]; - card->funcCIS[func - 1U].ioOPAvgPwr = dataBuffer[19U]; - card->funcCIS[func - 1U].ioOPMaxPwr = dataBuffer[20U]; - card->funcCIS[func - 1U].ioSBMinPwr = dataBuffer[21U]; - card->funcCIS[func - 1U].ioSBAvgPwr = dataBuffer[22U]; - card->funcCIS[func - 1U].ioSBMaxPwr = dataBuffer[23U]; - card->funcCIS[func - 1U].ioMinBandWidth = dataBuffer[24U] | (dataBuffer[25U] << 8U); - card->funcCIS[func - 1U].ioOptimumBandWidth = dataBuffer[26U] | (dataBuffer[27U] << 8U); - card->funcCIS[func - 1U].ioReadyTimeout = dataBuffer[28U] | (dataBuffer[29U] << 8U); - - card->funcCIS[func - 1U].ioHighCurrentAvgCurrent = dataBuffer[34U] | (dataBuffer[35U] << 8U); - card->funcCIS[func - 1U].ioHighCurrentMaxCurrent = dataBuffer[36U] | (dataBuffer[37U] << 8U); - card->funcCIS[func - 1U].ioLowCurrentAvgCurrent = dataBuffer[38U] | (dataBuffer[39U] << 8U); - card->funcCIS[func - 1U].ioLowCurrentMaxCurrent = dataBuffer[40U] | (dataBuffer[41U] << 8U); - } - else - { - return kStatus_Fail; - } - } - else - { - return kStatus_Fail; - } - } - - return kStatus_Success; -} - -status_t SDIO_ReadCIS(sdio_card_t *card, sdio_func_num_t func, const uint32_t *tupleList, uint32_t tupleNum) -{ - assert(card); - assert(func <= kSDIO_FunctionNum7); - assert(tupleList); - - uint8_t tplCode = 0U; - uint8_t tplLink = 0U; - uint32_t cisPtr = 0U; - uint32_t i = 0U, num = 0U; - bool tupleMatch = false; - - uint8_t dataBuffer[255U] = {0U}; - - /* get the CIS pointer for each function */ - if (func == kSDIO_FunctionNum0) - { - cisPtr = card->commonCISPointer; - } - else - { - cisPtr = card->ioFBR[func - 1U].ioPointerToCIS; - } - - if (0U == cisPtr) - { - return kStatus_SDMMC_SDIO_ReadCISFail; - } - - do - { - if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, cisPtr++, &tplCode)) - { - return kStatus_SDMMC_TransferFailed; - } - /* end of chain tuple */ - if (tplCode == 0xFFU) - { - break; - } - - if (tplCode == 0U) - { - continue; - } - - for (i = 0; i < tupleNum; i++) - { - if (tplCode == tupleList[i]) - { - tupleMatch = true; - break; - } - } - - if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, cisPtr++, &tplLink)) - { - return kStatus_SDMMC_TransferFailed; - } - /* end of chain tuple */ - if (tplLink == 0xFFU) - { - break; - } - - if (tupleMatch) - { - memset(dataBuffer, 0U, 255U); - for (i = 0; i < tplLink; i++) - { - if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, cisPtr++, &dataBuffer[i])) - { - return kStatus_SDMMC_TransferFailed; - } - } - tupleMatch = false; - /* pharse the data */ - SDIO_DecodeCIS(card, func, dataBuffer, tplCode, tplLink); - /* read finish then return */ - if (++num == tupleNum) - { - break; - } - } - else - { - /* move pointer */ - cisPtr += tplLink; - /* tuple code not match,continue read tuple code */ - continue; - } - } while (1); - return kStatus_Success; -} - -status_t SDIO_Init(sdio_card_t *card) -{ - assert(card); - assert(card->host.base); - - status_t error = kStatus_Success; - - if (!card->isHostReady) - { - error = HOST_Init(&(card->host)); - if (error != kStatus_Success) - { - return error; - } - /* set the host status flag, after the card re-plug in, don't need init host again */ - card->isHostReady = true; - } - - error = CardInsertDetect(card->host.base); - if (error != kStatus_Success) - { - return error; - } - - /* Identify mode ,set clock to 400KHZ. */ - card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SDMMC_CLOCK_400KHZ); - HOST_SET_CARD_BUS_WIDTH(card->host.base, kHOST_DATABUSWIDTH1BIT); - HOST_SEND_CARD_ACTIVE(card->host.base, 100U); - - /* get host capability */ - GET_HOST_CAPABILITY(card->host.base, &(card->host.capability)); - - /* Get IO OCR-CMD5 with arg0 ,set new voltage if needed*/ - if (kStatus_Success != SDIO_SendOperationCondition(card, 0U)) - { - return kStatus_SDMMC_HandShakeOperationConditionFailed; - } - - /* there is a memonly card */ - if ((card->ioTotalNumber == 0U) && (card->memPresentFlag)) - { - return kStatus_SDMMC_SDIO_InvalidCard; - } - /* verify the voltage and set the new voltage */ - if (card->host.capability.flags & kHOST_SupportV330) - { - if (kStatus_Success != SDIO_SendOperationCondition(card, kSDIO_OcrVdd32_33Flag | kSDIO_OcrVdd33_34Flag)) - { - return kStatus_SDMMC_InvalidVoltage; - } - } - else - { - return kStatus_SDMMC_InvalidVoltage; - } - - /* send relative address ,cmd3*/ - if (kStatus_Success != SDIO_SendRca(card)) - { - return kStatus_SDMMC_SendRelativeAddressFailed; - } - /* select card cmd7 */ - if (kStatus_Success != SDIO_SelectCard(card, true)) - { - return kStatus_SDMMC_SelectCardFailed; - } - - /* get card capability */ - if (kStatus_Success != SDIO_GetCardCapability(card, kSDIO_FunctionNum0)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* read common CIS here */ - if (SDIO_ReadCIS(card, kSDIO_FunctionNum0, g_tupleList, SDIO_COMMON_CIS_TUPLE_NUM)) - { - return kStatus_SDMMC_SDIO_ReadCISFail; - } - - /* freq and bus width setting */ - if (card->cccrflags & kSDIO_CCCRSupportLowSpeed4Bit) - { - /* set to 4bit data bus */ - SDIO_SetDataBusWidth(card, kSDIO_DataBus4Bit); - HOST_SET_CARD_BUS_WIDTH(card->host.base, kHOST_DATABUSWIDTH4BIT); - } - else if (card->cccrflags & kSDIO_CCCRSupportHighSpeed) - { - if (kStatus_Success != SDIO_SwitchToHighSpeed(card)) - { - return kStatus_SDMMC_SDIO_SwitchHighSpeedFail; - } - - return kStatus_Success; - } - - /* default mode 25MHZ */ - card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_25MHZ); - - return kStatus_Success; -} - -status_t SDIO_EnableIOInterrupt(sdio_card_t *card, sdio_func_num_t func, bool enable) -{ - assert(card); - assert(func <= kSDIO_FunctionNum7); - - uint8_t intEn = 0U; - - /* load io interrupt enable register */ - if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, kSDIO_RegIOIntEnable, &intEn)) - { - return kStatus_SDMMC_TransferFailed; - } - - if (enable) - { - /* if already enable , do not need enable again */ - if ((((intEn >> func) & 0x01U) == 0x01U) && (intEn & 0x01U)) - { - return kStatus_Success; - } - - /* enable the interrupt and interrupt master */ - intEn |= (1U << func) | 0x01U; - } - else - { - /* if already disable , do not need enable again */ - if (((intEn >> func) & 0x01U) == 0x00U) - { - return kStatus_Success; - } - - /* disable the interrupt, don't disable the interrupt master here */ - intEn &= ~(1U << func); - } - - /* write to register */ - if (kStatus_Success != SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, kSDIO_RegIOIntEnable, &intEn, true)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t SDIO_EnableIO(sdio_card_t *card, sdio_func_num_t func, bool enable) -{ - assert(card); - assert(func <= kSDIO_FunctionNum7); - - uint8_t ioEn = 0U, ioReady = 0U; - uint32_t i = FSL_SDMMC_MAX_VOLTAGE_RETRIES; - - /* load io enable register */ - if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, kSDIO_RegIOEnable, &ioEn)) - { - return kStatus_SDMMC_TransferFailed; - } - /* if already enable/disable , do not need enable/disable again */ - if (((ioEn >> func) & 0x01U) == (enable ? 1U : 0U)) - { - return kStatus_Success; - } - - /* enable the io */ - if (enable) - { - ioEn |= (1U << func); - } - else - { - ioEn &= ~(1U << func); - } - - /* write to register */ - if (kStatus_Success != SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, kSDIO_RegIOEnable, &ioEn, true)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* if enable io, need check the IO ready status */ - if (enable) - { - while (i--) - { - /* wait IO ready */ - if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, kSDIO_RegIOReady, &ioReady)) - { - return kStatus_SDMMC_TransferFailed; - } - /* check if IO ready */ - if ((ioReady & (1 << func)) != 0U) - { - return kStatus_Success; - } - } - } - - return (i == 0U) ? kStatus_Fail : kStatus_Success; -} - -status_t SDIO_SelectIO(sdio_card_t *card, sdio_func_num_t func) -{ - assert(card); - assert(func <= kSDIO_FunctionMemory); - - uint8_t ioSel = func; - - /* write to register */ - if (kStatus_Success != SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, kSDIO_RegFunctionSelect, &ioSel, true)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t SDIO_AbortIO(sdio_card_t *card, sdio_func_num_t func) -{ - assert(card); - assert(func <= kSDIO_FunctionNum7); - - uint8_t ioAbort = func; - - /* write to register */ - if (kStatus_Success != SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, kSDIO_RegIOAbort, &ioAbort, true)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -void SDIO_DeInit(sdio_card_t *card) -{ - assert(card); - /* disselect card */ - SDIO_CardReset(card); - SDIO_SelectCard(card, false); - HOST_Deinit(&(card->host)); - /* should re-init host */ - card->isHostReady = false; -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sdmmc.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sdmmc.c deleted file mode 100644 index 8bc7721368a..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sdmmc.c +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_specification.h" -#include "fsl_card.h" - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -void SDMMC_Delay(uint32_t num) -{ - volatile uint32_t i, j; - - for (i = 0U; i < num; i++) - { - for (j = 0U; j < 10000U; j++) - { - __asm("nop"); - } - } -} - -status_t SDMMC_SelectCard(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t relativeAddress, bool isSelected) -{ - assert(transfer); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - - command.index = kSDMMC_SelectCard; - if (isSelected) - { - command.argument = relativeAddress << 16U; - command.responseType = kCARD_ResponseTypeR1; - } - else - { - command.argument = 0U; - command.responseType = kCARD_ResponseTypeNone; - } - - content.command = &command; - content.data = NULL; - if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & kSDMMC_R1ErrorAllFlag)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* Wait until card to transfer state */ - return kStatus_Success; -} - -status_t SDMMC_SendApplicationCommand(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t relativeAddress) -{ - assert(transfer); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - - command.index = kSDMMC_ApplicationCommand; - command.argument = 0U; - command.argument = (relativeAddress << 16U); - command.responseType = kCARD_ResponseTypeR1; - - content.command = &command; - content.data = 0U; - if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & kSDMMC_R1ErrorAllFlag)) - { - return kStatus_SDMMC_TransferFailed; - } - - if (!(command.response[0U] & kSDMMC_R1ApplicationCommandFlag)) - { - return kStatus_SDMMC_CardNotSupport; - } - - return kStatus_Success; -} - -status_t SDMMC_SetBlockCount(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t blockCount) -{ - assert(transfer); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - - command.index = kSDMMC_SetBlockCount; - command.argument = blockCount; - command.responseType = kCARD_ResponseTypeR1; - - content.command = &command; - content.data = 0U; - if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & kSDMMC_R1ErrorAllFlag)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t SDMMC_GoIdle(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer) -{ - assert(transfer); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - - command.index = kSDMMC_GoIdleState; - - content.command = &command; - content.data = 0U; - if (kStatus_Success != transfer(base, &content)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t SDMMC_SetBlockSize(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t blockSize) -{ - assert(transfer); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - - command.index = kSDMMC_SetBlockLength; - command.argument = blockSize; - command.responseType = kCARD_ResponseTypeR1; - - content.command = &command; - content.data = 0U; - if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & kSDMMC_R1ErrorAllFlag)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t SDMMC_SetCardInactive(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer) -{ - assert(transfer); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - - command.index = kSDMMC_GoInactiveState; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeNone; - - content.command = &command; - content.data = 0U; - if ((kStatus_Success != transfer(base, &content))) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t SDMMC_SwitchVoltage(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer) -{ - assert(transfer); - - HOST_TRANSFER content = {0}; - HOST_COMMAND command = {0}; - - command.index = kSD_VoltageSwitch; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeR1; - - content.command = &command; - content.data = NULL; - if (kStatus_Success != transfer(base, &content)) - { - return kStatus_SDMMC_TransferFailed; - } - /* disable card clock */ - HOST_ENABLE_CARD_CLOCK(base, false); - - /* check data line and cmd line status */ - if ((GET_HOST_STATUS(base) & - (CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY)) != 0U) - { - return kStatus_SDMMC_SwitchVoltageFail; - } - - /* host switch to 1.8V */ - HOST_SWITCH_VOLTAGE180V(base, true); - - SDMMC_Delay(100U); - - /*enable sd clock*/ - HOST_ENABLE_CARD_CLOCK(base, true); - HOST_FORCE_SDCLOCK_ON(base, true); - /* dealy 1ms,not exactly correct when use while */ - SDMMC_Delay(10U); - - HOST_FORCE_SDCLOCK_ON(base, false); - - /* check data line and cmd line status */ - if ((GET_HOST_STATUS(base) & - (CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY)) == 0U) - { - return kStatus_SDMMC_SwitchVoltageFail; - } - - return kStatus_Success; -} - -status_t SDMMC_ExecuteTuning(HOST_TYPE *base, uint32_t tuningCmd, uint32_t blockSize) -{ - HOST_TRANSFER content = {0U}; - HOST_COMMAND command = {0U}; - HOST_DATA data = {0U}; - uint32_t buffer[32U] = {0U}; - bool tuningError = true; - - command.index = tuningCmd; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeR1; - - data.blockSize = blockSize; - data.blockCount = 1U; - data.rxData = buffer; - - content.command = &command; - content.data = &data; - - HOST_RESET_TUNING(base, 100U); - - /* enable the standard tuning */ - HOST_EXECUTE_STANDARD_TUNING_ENABLE(base, true); - - while (true) - { - /* send tuning block */ - if ((kStatus_Success != HOST_EXECUTE_STANDARD_TUNING(base, &content))) - { - return kStatus_SDMMC_TransferFailed; - } - SDMMC_Delay(1U); - - /*wait excute tuning bit clear*/ - if ((HOST_EXECUTE_STANDARD_TUNING_STATUS(base) != 0U)) - { - continue; - } - - /* if tuning error , re-tuning again */ - if ((HOST_CHECK_TUNING_ERROR(base) != 0U) && tuningError) - { - tuningError = false; - /* enable the standard tuning */ - HOST_EXECUTE_STANDARD_TUNING_ENABLE(base, true); - HOST_ADJUST_TUNING_DELAY(base, HOST_STANDARD_TUNING_START); - } - else - { - break; - } - } - - /* check tuning result*/ - if (HOST_EXECUTE_STANDARD_TUNING_RESULT(base) == 0U) - { - return kStatus_SDMMC_TuningFail; - } - - HOST_AUTO_STANDARD_RETUNING_TIMER(base); - - return kStatus_Success; -} diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sdspi.c b/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sdspi.c deleted file mode 100644 index 4055e16d8c8..00000000000 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sdspi.c +++ /dev/null @@ -1,1273 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - -#include "fsl_sdspi.h" - -/******************************************************************************* - * Definitons - ******************************************************************************/ -#define IS_BLOCK_ACCESS(x) ((x)->flags & kSDSPI_SupportHighCapacityFlag) - -/* Card command maximum timeout value */ -#define FSL_SDSPI_TIMEOUT (1000U) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Wait card to be ready state. - * - * @param host Host state. - * @param milliseconds Timeout time in millseconds. - * @retval kStatus_SDSPI_ExchangeFailed Exchange data over SPI failed. - * @retval kStatus_SDSPI_ResponseError Response is error. - * @retval kStatus_Success Operate successfully. - */ -static status_t SDSPI_WaitReady(sdspi_host_t *host, uint32_t milliseconds); - -/*! - * @brief Calculate CRC7 - * - * @param buffer Data buffer. - * @param length Data length. - * @param crc The orginal crc value. - * @return Generated CRC7. - */ -static uint32_t SDSPI_GenerateCRC7(uint8_t *buffer, uint32_t length, uint32_t crc); - -/*! - * @brief Send command. - * - * @param host Host state. - * @param command The command to be wrote. - * @param timeout The timeout value. - * @retval kStatus_SDSPI_WaitReadyFailed Wait ready failed. - * @retval kStatus_SDSPI_ExchangeFailed Exchange data over SPI failed. - * @retval kStatus_SDSPI_ResponseError Response is error. - * @retval kStatus_Fail Send command failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SDSPI_SendCommand(sdspi_host_t *host, sdspi_command_t *command, uint32_t timeout); - -/*! - * @brief Send GO_IDLE command. - * - * @param card Card descriptor. - * @retval kStatus_SDSPI_ExchangeFailed Send timing byte failed. - * @retval kStatus_SDSPI_SendCommandFailed Send command failed. - * @retval kStatus_SDSPI_ResponseError Response is error. - * @retval kStatus_Success Operate successfully. - */ -static status_t SDSPI_GoIdle(sdspi_card_t *card); - -/*! - * @brief Send GET_INTERFACE_CONDITION command. - * - * This function checks card interface condition, which includes host supply voltage information and asks the card - * whether it supports voltage. - * - * @param card Card descriptor. - * @param pattern The check pattern. - * @param response Buffer to save the command response. - * @retval kStatus_SDSPI_SendCommandFailed Send command failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SDSPI_SendInterfaceCondition(sdspi_card_t *card, uint8_t pattern, uint8_t *response); - -/*! - * @brief Send SEND_APPLICATION_COMMAND command. - * - * @param card Card descriptor. - * @retval kStatus_SDSPI_SendCommandFailed Send command failed. - * @retval kStatus_SDSPI_ResponseError Response is error. - * @retval kStatus_Success Operate successfully. - */ -static status_t SDSPI_SendApplicationCmd(sdspi_card_t *card); - -/*! - * @brief Send GET_OPERATION_CONDITION command. - * - * @param card Card descriptor. - * @param argument Operation condition. - * @param response Buffer to save command response. - * @retval kStatus_Timeout Timeout. - * @retval kStatus_Success Operate successfully. - */ -static status_t SDSPI_ApplicationSendOperationCondition(sdspi_card_t *card, uint32_t argument, uint8_t *response); - -/*! - * @brief Send READ_OCR command to get OCR register content. - * - * @param card Card descriptor. - * @retval kStatus_SDSPI_SendCommandFailed Send command failed. - * @retval kStatus_SDSPI_ResponseError Response is error. - * @retval kStatus_Success Operate successfully. - */ -static status_t SDSPI_ReadOcr(sdspi_card_t *card); - -/*! - * @brief Send SET_BLOCK_SIZE command. - * - * This function sets the block length in bytes for SDSC cards. For SDHC cards, it does not affect memory - * read or write commands, always 512 bytes fixed block length is used. - * @param card Card descriptor. - * @param blockSize Block size. - * @retval kStatus_SDSPI_SendCommandFailed Send command failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SDSPI_SetBlockSize(sdspi_card_t *card, uint32_t blockSize); - -/*! - * @brief Read data from card - * - * @param host Host state. - * @param buffer Buffer to save data. - * @param size The data size to read. - * @retval kStatus_SDSPI_ResponseError Response is error. - * @retval kStatus_SDSPI_ExchangeFailed Exchange data over SPI failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SDSPI_Read(sdspi_host_t *host, uint8_t *buffer, uint32_t size); - -/*! - * @brief Decode CSD register - * - * @param card Card descriptor. - * @param rawCsd Raw CSD register content. - */ -static void SDSPI_DecodeCsd(sdspi_card_t *card, uint8_t *rawCsd); - -/*! - * @brief Send GET-CSD command. - * - * @param card Card descriptor. - * @retval kStatus_SDSPI_SendCommandFailed Send command failed. - * @retval kStatus_SDSPI_ReadFailed Read data blocks failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SDSPI_SendCsd(sdspi_card_t *card); - -/*! - * @brief Set card to max frequence in normal mode. - * - * @param card Card descriptor. - * @retval kStatus_SDSPI_SetFrequencyFailed Set frequency failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SDSPI_SetMaxFrequencyNormalMode(sdspi_card_t *card); - -/*! - * @brief Check the capacity of the card - * - * @param card Card descriptor. - */ -static void SDSPI_CheckCapacity(sdspi_card_t *card); - -/*! - * @brief Decode raw CID register. - * - * @param card Card descriptor. - * @param rawCid Raw CID register content. - */ -static void SDSPI_DecodeCid(sdspi_card_t *card, uint8_t *rawCid); - -/*! - * @brief Send GET-CID command - * - * @param card Card descriptor. - * @retval kStatus_SDSPI_SendCommandFailed Send command failed. - * @retval kStatus_SDSPI_ReadFailed Read data blocks failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SDSPI_SendCid(sdspi_card_t *card); - -/*! - * @brief Decode SCR register. - * - * @param card Card descriptor. - * @param rawScr Raw SCR register content. - */ -static void SDSPI_DecodeScr(sdspi_card_t *card, uint8_t *rawScr); - -/*! - * @brief Send SEND_SCR command. - * - * @param card Card descriptor. - * @retval kStatus_SDSPI_SendCommandFailed Send command failed. - * @retval kStatus_SDSPI_ReadFailed Read data blocks failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SDSPI_SendScr(sdspi_card_t *card); - -/*! - * @brief Send STOP_TRANSMISSION command to card to stop ongoing data transferring. - * - * @param card Card descriptor. - * @retval kStatus_SDSPI_SendCommandFailed Send command failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SDSPI_StopTransmission(sdspi_card_t *card); - -/*! - * @brief Write data to card - * - * @param host Host state. - * @param buffer Data to send. - * @param size Data size. - * @param token The data token. - * @retval kStatus_SDSPI_WaitReadyFailed Card is busy error. - * @retval kStatus_SDSPI_ExchangeFailed Exchange data over SPI failed. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_SDSPI_ResponseError Response is error. - * @retval kStatus_Success Operate successfully. - */ -static status_t SDSPI_Write(sdspi_host_t *host, uint8_t *buffer, uint32_t size, uint8_t token); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Rate unit(divided by 1000) of transfer speed in non-high-speed mode. */ -static const uint32_t g_transferSpeedRateUnit[] = { - /* 100Kbps, 1Mbps, 10Mbps, 100Mbps*/ - 100U, 1000U, 10000U, 100000U, -}; - -/* Multiplier factor(multiplied by 1000) of transfer speed in non-high-speed mode. */ -static const uint32_t g_transferSpeedMultiplierFactor[] = { - 0U, 1000U, 1200U, 1300U, 1500U, 2000U, 2500U, 3000U, 3500U, 4000U, 4500U, 5000U, 5500U, 6000U, 7000U, 8000U, -}; - -/******************************************************************************* - * Code - ******************************************************************************/ -static status_t SDSPI_WaitReady(sdspi_host_t *host, uint32_t milliseconds) -{ - uint8_t response; - uint8_t timingByte = 0xFFU; /* The byte need to be sent as read/write data block timing requirement */ - uint32_t startTime; - uint32_t currentTime; - uint32_t elapsedTime; - - startTime = host->getCurrentMilliseconds(); - do - { - if (kStatus_Success != host->exchange(&timingByte, &response, 1U)) - { - return kStatus_SDSPI_ExchangeFailed; - } - - currentTime = host->getCurrentMilliseconds(); - elapsedTime = (currentTime - startTime); - } while ((response != 0xFFU) && (elapsedTime < milliseconds)); - - /* Response 0xFF means card is still busy. */ - if (response != 0xFFU) - { - return kStatus_SDSPI_ResponseError; - } - - return kStatus_Success; -} - -static uint32_t SDSPI_GenerateCRC7(uint8_t *buffer, uint32_t length, uint32_t crc) -{ - uint32_t index; - - static const uint8_t crcTable[] = {0x00U, 0x09U, 0x12U, 0x1BU, 0x24U, 0x2DU, 0x36U, 0x3FU, - 0x48U, 0x41U, 0x5AU, 0x53U, 0x6CU, 0x65U, 0x7EU, 0x77U}; - - while (length) - { - index = (((crc >> 3U) & 0x0FU) ^ ((*buffer) >> 4U)); - crc = ((crc << 4U) ^ crcTable[index]); - - index = (((crc >> 3U) & 0x0FU) ^ ((*buffer) & 0x0FU)); - crc = ((crc << 4U) ^ crcTable[index]); - - buffer++; - length--; - } - - return (crc & 0x7FU); -} - -static status_t SDSPI_SendCommand(sdspi_host_t *host, sdspi_command_t *command, uint32_t timeout) -{ - assert(host); - assert(command); - - uint8_t buffer[6U]; - uint8_t response; - uint8_t i; - uint8_t timingByte = 0xFFU; /* The byte need to be sent as read/write data block timing requirement */ - - if ((kStatus_Success != SDSPI_WaitReady(host, timeout)) && (command->index != kSDMMC_GoIdleState)) - { - return kStatus_SDSPI_WaitReadyFailed; - } - - /* Send command. */ - buffer[0U] = (command->index | 0x40U); - buffer[1U] = ((command->argument >> 24U) & 0xFFU); - buffer[2U] = ((command->argument >> 16U) & 0xFFU); - buffer[3U] = ((command->argument >> 8U) & 0xFFU); - buffer[4U] = (command->argument & 0xFFU); - buffer[5U] = ((SDSPI_GenerateCRC7(buffer, 5U, 0U) << 1U) | 1U); - if (host->exchange(buffer, NULL, sizeof(buffer))) - { - return kStatus_SDSPI_ExchangeFailed; - } - - /* Wait for the response coming, the left most bit which is transfered first in first response byte is 0 */ - for (i = 0U; i < 9U; i++) - { - if (kStatus_Success != host->exchange(&timingByte, &response, 1U)) - { - return kStatus_SDSPI_ExchangeFailed; - } - - /* Check if response 0 coming. */ - if (!(response & 0x80U)) - { - break; - } - } - if (response & 0x80U) /* Max index byte is high means response comming. */ - { - return kStatus_SDSPI_ResponseError; - } - - /* Receve all the response content. */ - command->response[0U] = response; - switch (command->responseType) - { - case kSDSPI_ResponseTypeR1: - break; - case kSDSPI_ResponseTypeR1b: - if (kStatus_Success != SDSPI_WaitReady(host, timeout)) - { - return kStatus_SDSPI_WaitReadyFailed; - } - break; - case kSDSPI_ResponseTypeR2: - if (kStatus_Success != host->exchange(&timingByte, &(command->response[1U]), 1U)) - { - return kStatus_SDSPI_ExchangeFailed; - } - break; - case kSDSPI_ResponseTypeR3: - case kSDSPI_ResponseTypeR7: - /* Left 4 bytes in response type R3 and R7(total 5 bytes in SPI mode) */ - if (kStatus_Success != host->exchange(&timingByte, &(command->response[1U]), 4U)) - { - return kStatus_SDSPI_ExchangeFailed; - } - break; - default: - return kStatus_Fail; - } - - return kStatus_Success; -} - -static status_t SDSPI_GoIdle(sdspi_card_t *card) -{ - assert(card); - assert(card->host); - - sdspi_host_t *host; - sdspi_command_t command = {0}; - uint32_t retryCount = 200U; - - host = card->host; - /* SD card will enter SPI mode if the CS is asserted (negative) during the reception of the reset command (CMD0) - and the card will be IDLE state. */ - while (retryCount--) - { - command.index = kSDMMC_GoIdleState; - command.responseType = kSDSPI_ResponseTypeR1; - if ((kStatus_Success == SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) && - (command.response[0U] == kSDSPI_R1InIdleStateFlag)) - { - break; - } - } - - return kStatus_Success; -} - -static status_t SDSPI_SendInterfaceCondition(sdspi_card_t *card, uint8_t pattern, uint8_t *response) -{ - assert(card); - assert(card->host); - - sdspi_command_t command = {0}; - sdspi_host_t *host; - - host = card->host; - command.index = kSD_SendInterfaceCondition; - command.argument = (0x100U | (pattern & 0xFFU)); - command.responseType = kSDSPI_ResponseTypeR7; - if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) - { - return kStatus_SDSPI_SendCommandFailed; - } - - memcpy(response, command.response, sizeof(command.response)); - - return kStatus_Success; -} - -static status_t SDSPI_SendApplicationCmd(sdspi_card_t *card) -{ - assert(card); - assert(card->host); - - sdspi_host_t *host; - sdspi_command_t command = {0}; - - host = card->host; - command.index = kSDMMC_ApplicationCommand; - command.responseType = kSDSPI_ResponseTypeR1; - if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) - { - return kStatus_SDSPI_SendCommandFailed; - } - - if ((command.response[0U]) && (!(command.response[0U] & kSDSPI_R1InIdleStateFlag))) - { - return kStatus_SDSPI_ResponseError; - } - - return kStatus_Success; -} - -static status_t SDSPI_ApplicationSendOperationCondition(sdspi_card_t *card, uint32_t argument, uint8_t *response) -{ - assert(card); - assert(card->host); - assert(response); - - sdspi_command_t command = {0}; - uint32_t startTime; - uint32_t currentTime; - uint32_t elapsedTime = 0U; - sdspi_host_t *host; - - host = card->host; - command.index = kSD_ApplicationSendOperationCondition; - command.argument = argument; - command.responseType = kSDSPI_ResponseTypeR1; - startTime = host->getCurrentMilliseconds(); - do - { - if (kStatus_Success == SDSPI_SendApplicationCmd(card)) - { - if (kStatus_Success == SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) - { - if (!command.response[0U]) - { - break; - } - } - } - - currentTime = host->getCurrentMilliseconds(); - elapsedTime = (currentTime - startTime); - } while (elapsedTime < FSL_SDSPI_TIMEOUT); - - if (response) - { - memcpy(response, command.response, sizeof(command.response)); - } - if (elapsedTime < FSL_SDSPI_TIMEOUT) - { - return kStatus_Success; - } - - return kStatus_Timeout; -} - -static status_t SDSPI_ReadOcr(sdspi_card_t *card) -{ - assert(card); - assert(card->host); - - uint32_t i; - sdspi_host_t *host; - sdspi_command_t command = {0}; - - host = card->host; - command.index = kSDMMC_ReadOcr; - command.responseType = kSDSPI_ResponseTypeR3; - if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) - { - return kStatus_SDSPI_SendCommandFailed; - } - - if (command.response[0U]) - { - return kStatus_SDSPI_ResponseError; - } - - /* Switch the bytes sequence. All register's content is transferred from highest byte to lowest byte. */ - card->ocr = 0U; - for (i = 4U; i > 0U; i--) - { - card->ocr |= (uint32_t)command.response[i] << ((4U - i) * 8U); - } - - return kStatus_Success; -} - -static status_t SDSPI_SetBlockSize(sdspi_card_t *card, uint32_t blockSize) -{ - assert(card); - assert(card->host); - - sdspi_command_t command = {0}; - sdspi_host_t *host; - - host = card->host; - command.index = kSDMMC_SetBlockLength; - command.argument = blockSize; - command.responseType = kSDSPI_ResponseTypeR1; - if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) - { - return kStatus_SDSPI_SendCommandFailed; - } - - return kStatus_Success; -} - -static status_t SDSPI_Read(sdspi_host_t *host, uint8_t *buffer, uint32_t size) -{ - assert(host); - assert(host->exchange); - assert(buffer); - assert(size); - - uint32_t startTime; - uint32_t currentTime; - uint32_t elapsedTime; - uint8_t response, i; - uint8_t timingByte = 0xFFU; /* The byte need to be sent as read/write data block timing requirement */ - - memset(buffer, 0xFFU, size); - - /* Wait data token comming */ - startTime = host->getCurrentMilliseconds(); - do - { - if (kStatus_Success != host->exchange(&timingByte, &response, 1U)) - { - return kStatus_SDSPI_ExchangeFailed; - } - - currentTime = host->getCurrentMilliseconds(); - elapsedTime = (currentTime - startTime); - } while ((response == 0xFFU) && (elapsedTime < 100U)); - - /* Check data token and exchange data. */ - if (response != kSDSPI_DataTokenBlockRead) - { - return kStatus_SDSPI_ResponseError; - } - if (host->exchange(buffer, buffer, size)) - { - return kStatus_SDSPI_ExchangeFailed; - } - - /* Get 16 bit CRC */ - for (i = 0U; i < 2U; i++) - { - if (kStatus_Success != host->exchange(&timingByte, &response, 1U)) - { - return kStatus_SDSPI_ExchangeFailed; - } - } - - return kStatus_Success; -} - -static void SDSPI_DecodeCsd(sdspi_card_t *card, uint8_t *rawCsd) -{ - assert(rawCsd); - assert(card); - - sd_csd_t *csd; - - csd = &(card->csd); - csd->csdStructure = (rawCsd[0U] >> 6U); - csd->dataReadAccessTime1 = rawCsd[1U]; - csd->dataReadAccessTime2 = rawCsd[2U]; - csd->transferSpeed = rawCsd[3U]; - csd->cardCommandClass = (((uint32_t)rawCsd[4U] << 4U) | ((uint32_t)rawCsd[5U] >> 4U)); - csd->readBlockLength = ((rawCsd)[5U] & 0xFU); - if (rawCsd[6U] & 0x80U) - { - csd->flags |= kSD_CsdReadBlockPartialFlag; - } - if (rawCsd[6U] & 0x40U) - { - csd->flags |= kSD_CsdWriteBlockMisalignFlag; - } - if (rawCsd[6U] & 0x20U) - { - csd->flags |= kSD_CsdReadBlockMisalignFlag; - } - if (rawCsd[6U] & 0x10U) - { - csd->flags |= kSD_CsdDsrImplementedFlag; - } - - /* Some fileds is different when csdStructure is different. */ - if (csd->csdStructure == 0U) /* Decode the bits when CSD structure is version 1.0 */ - { - csd->deviceSize = - ((((uint32_t)rawCsd[6] & 0x3U) << 10U) | ((uint32_t)rawCsd[7U] << 2U) | ((uint32_t)rawCsd[8U] >> 6U)); - csd->readCurrentVddMin = ((rawCsd[8U] >> 3U) & 7U); - csd->readCurrentVddMax = (rawCsd[8U] >> 7U); - csd->writeCurrentVddMin = ((rawCsd[9U] >> 5U) & 7U); - csd->writeCurrentVddMax = (rawCsd[9U] >> 2U); - csd->deviceSizeMultiplier = (((rawCsd[9U] & 3U) << 1U) | (rawCsd[10U] >> 7U)); - card->blockCount = (csd->deviceSize + 1U) << (csd->deviceSizeMultiplier + 2U); - card->blockSize = (1U << (csd->readBlockLength)); - if (card->blockSize != FSL_SDSPI_DEFAULT_BLOCK_SIZE) - { - card->blockCount = (card->blockCount * card->blockSize); - card->blockSize = FSL_SDSPI_DEFAULT_BLOCK_SIZE; - card->blockCount = (card->blockCount / card->blockSize); - } - } - else if (csd->csdStructure == 1U) /* Decode the bits when CSD structure is version 2.0 */ - { - card->blockSize = FSL_SDSPI_DEFAULT_BLOCK_SIZE; - csd->deviceSize = - ((((uint32_t)rawCsd[7U] & 0x3FU) << 16U) | ((uint32_t)rawCsd[8U] << 8U) | ((uint32_t)rawCsd[9U])); - if (csd->deviceSize >= 0xFFFFU) - { - card->flags |= kSDSPI_SupportSdxcFlag; - } - card->blockCount = ((csd->deviceSize + 1U) * 1024U); - } - else - { - } - - if ((rawCsd[10U] >> 6U) & 1U) - { - csd->flags |= kSD_CsdEraseBlockEnabledFlag; - } - csd->eraseSectorSize = (((rawCsd[10U] & 0x3FU) << 1U) | (rawCsd[11U] >> 7U)); - csd->writeProtectGroupSize = (rawCsd[11U] & 0x7FU); - if (rawCsd[12U] >> 7U) - { - csd->flags |= kSD_CsdWriteProtectGroupEnabledFlag; - } - csd->writeSpeedFactor = ((rawCsd[12U] >> 2U) & 7U); - csd->writeBlockLength = (((rawCsd[12U] & 3U) << 2U) | (rawCsd[13U] >> 6U)); - if ((rawCsd[13U] >> 5U) & 1U) - { - csd->flags |= kSD_CsdWriteBlockPartialFlag; - } - if (rawCsd[14U] >> 7U) - { - csd->flags |= kSD_CsdFileFormatGroupFlag; - } - if ((rawCsd[14U] >> 6U) & 1U) - { - csd->flags |= kSD_CsdCopyFlag; - } - if ((rawCsd[14U] >> 5U) & 1U) - { - csd->flags |= kSD_CsdPermanentWriteProtectFlag; - } - if ((rawCsd[14U] >> 4U) & 1U) - { - csd->flags |= kSD_CsdTemporaryWriteProtectFlag; - } - csd->fileFormat = ((rawCsd[14U] >> 2U) & 3U); -} - -static status_t SDSPI_SendCsd(sdspi_card_t *card) -{ - assert(card); - assert(card->host); - - sdspi_command_t command = {0}; - sdspi_host_t *host; - - host = card->host; - command.index = kSDMMC_SendCsd; - command.responseType = kSDSPI_ResponseTypeR1; - if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) - { - return kStatus_SDSPI_SendCommandFailed; - } - - if (kStatus_Success != SDSPI_Read(host, card->rawCsd, sizeof(card->rawCsd))) - { - return kStatus_SDSPI_ReadFailed; - } - - SDSPI_DecodeCsd(card, card->rawCsd); - - return kStatus_Success; -} - -static status_t SDSPI_SetMaxFrequencyNormalMode(sdspi_card_t *card) -{ - uint32_t maxFrequency; - - /* Calculate max frequency card supported in non-high-speed mode. */ - maxFrequency = g_transferSpeedRateUnit[SD_RD_TRANSFER_SPEED_RATE_UNIT(card->csd)] * - g_transferSpeedMultiplierFactor[SD_RD_TRANSFER_SPEED_TIME_VALUE(card->csd)]; - if (maxFrequency > card->host->busBaudRate) - { - maxFrequency = card->host->busBaudRate; - } - - if (kStatus_Success != card->host->setFrequency(maxFrequency)) - { - return kStatus_SDSPI_SetFrequencyFailed; - } - - return kStatus_Success; -} - -static void SDSPI_CheckCapacity(sdspi_card_t *card) -{ - uint32_t deviceSize; - uint32_t deviceSizeMultiplier; - uint32_t readBlockLength; - - if (card->csd.csdStructure) - { - /* SD CSD structure v2.xx */ - deviceSize = card->csd.deviceSize; - if (deviceSize >= 0xFFFFU) /* Bigger than 32GB */ - { - /* extended capacity */ - card->flags |= kSDSPI_SupportSdxcFlag; - } - else - { - card->flags |= kSDSPI_SupportSdhcFlag; - } - deviceSizeMultiplier = 10U; - deviceSize += 1U; - readBlockLength = 9U; - } - else - { - /* SD CSD structure v1.xx */ - deviceSize = (card->csd.deviceSize + 1U); - deviceSizeMultiplier = (card->csd.deviceSizeMultiplier + 2U); - readBlockLength = card->csd.readBlockLength; - /* Card maximum capacity is 2GB when CSD structure version is 1.0 */ - card->flags |= kSDSPI_SupportSdscFlag; - } - if (readBlockLength != 9U) - { - /* Force to use 512-byte length block */ - deviceSizeMultiplier += (readBlockLength - 9U); - readBlockLength = 9U; - } - - card->blockSize = (1U << readBlockLength); - card->blockCount = (deviceSize << deviceSizeMultiplier); -} - -static void SDSPI_DecodeCid(sdspi_card_t *card, uint8_t *rawCid) -{ - assert(card); - assert(rawCid); - - sd_cid_t *cid = &(card->cid); - cid->manufacturerID = rawCid[0U]; - cid->applicationID = (((uint32_t)rawCid[1U] << 8U) | (uint32_t)(rawCid[2U])); - memcpy(cid->productName, &rawCid[3U], SD_PRODUCT_NAME_BYTES); - cid->productVersion = rawCid[8U]; - cid->productSerialNumber = (((uint32_t)rawCid[9U] << 24U) | ((uint32_t)rawCid[10U] << 16U) | - ((uint32_t)rawCid[11U] << 8U) | ((uint32_t)rawCid[12U])); - cid->manufacturerData = ((((uint32_t)rawCid[13U] & 0x0FU) << 8U) | ((uint32_t)rawCid[14U])); -} - -static status_t SDSPI_SendCid(sdspi_card_t *card) -{ - assert(card); - assert(card->host); - - sdspi_command_t command = {0}; - sdspi_host_t *host; - - host = card->host; - command.index = kSDMMC_SendCid; - command.responseType = kSDSPI_ResponseTypeR1; - if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) - { - return kStatus_SDSPI_SendCommandFailed; - } - - if (kStatus_Success != (SDSPI_Read(host, card->rawCid, sizeof(card->rawCid)))) - { - return kStatus_SDSPI_ReadFailed; - } - - SDSPI_DecodeCid(card, card->rawCid); - - return kStatus_Success; -} - -static void SDSPI_DecodeScr(sdspi_card_t *card, uint8_t *rawScr) -{ - assert(card); - assert(rawScr); - - sd_scr_t *scr = &(card->scr); - scr->scrStructure = ((rawScr[0U] & 0xF0U) >> 4U); - scr->sdSpecification = (rawScr[0U] & 0x0FU); - if (rawScr[1U] & 0x80U) - { - scr->flags |= kSD_ScrDataStatusAfterErase; - } - scr->sdSecurity = ((rawScr[1U] & 0x70U) >> 4U); - scr->sdBusWidths = (rawScr[1U] & 0x0FU); - if (rawScr[2U] & 0x80U) - { - scr->flags |= kSD_ScrSdSpecification3; - } - scr->extendedSecurity = ((rawScr[2U] & 0x78U) >> 3U); - scr->commandSupport = (rawScr[3U] & 0x03U); - scr->reservedForManufacturer = (((uint32_t)rawScr[4U] << 24U) | ((uint32_t)rawScr[5U] << 16U) | - ((uint32_t)rawScr[6U] << 8U) | (uint32_t)rawScr[7U]); -} - -static status_t SDSPI_SendScr(sdspi_card_t *card) -{ - assert(card); - assert(card->host); - - sdspi_command_t command = {0}; - sdspi_host_t *host; - - host = card->host; - if (kStatus_Success != SDSPI_SendApplicationCmd(card)) - { - return kStatus_SDSPI_SendApplicationCommandFailed; - } - - command.index = kSD_ApplicationSendScr; - command.responseType = kSDSPI_ResponseTypeR1; - if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) - { - return kStatus_SDSPI_SendCommandFailed; - } - - if (kStatus_Success != (SDSPI_Read(host, card->rawScr, sizeof(card->rawScr)))) - { - return kStatus_SDSPI_ReadFailed; - } - - SDSPI_DecodeScr(card, card->rawScr); - - return kStatus_Success; -} - -static status_t SDSPI_StopTransmission(sdspi_card_t *card) -{ - sdspi_command_t command = {0}; - sdspi_host_t *host; - - host = card->host; - command.index = kSDMMC_StopTransmission; - command.responseType = kSDSPI_ResponseTypeR1b; - if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) - { - return kStatus_SDSPI_SendCommandFailed; - } - - return kStatus_Success; -} - -static status_t SDSPI_Write(sdspi_host_t *host, uint8_t *buffer, uint32_t size, uint8_t token) -{ - assert(host); - assert(host->exchange); - - uint8_t response; - uint8_t i; - uint8_t timingByte = 0xFFU; /* The byte need to be sent as read/write data block timing requirement */ - - if (kStatus_Success != SDSPI_WaitReady(host, FSL_SDSPI_TIMEOUT)) - { - return kStatus_SDSPI_WaitReadyFailed; - } - - /* Write data token. */ - if (host->exchange(&token, NULL, 1U)) - { - return kStatus_SDSPI_ExchangeFailed; - } - if (token == kSDSPI_DataTokenStopTransfer) - { - return kStatus_Success; - } - - if ((!size) || (!buffer)) - { - return kStatus_InvalidArgument; - } - - /* Write data. */ - if (kStatus_Success != host->exchange(buffer, NULL, size)) - { - return kStatus_SDSPI_ExchangeFailed; - } - - /* Get the last two bytes CRC */ - for (i = 0U; i < 2U; i++) - { - if (host->exchange(&timingByte, NULL, 1U)) - { - return kStatus_SDSPI_ExchangeFailed; - } - } - - /* Get the response token. */ - if (host->exchange(&timingByte, &response, 1U)) - { - return kStatus_SDSPI_ExchangeFailed; - } - if ((response & SDSPI_DATA_RESPONSE_TOKEN_MASK) != kSDSPI_DataResponseTokenAccepted) - { - return kStatus_SDSPI_ResponseError; - } - - return kStatus_Success; -} - -status_t SDSPI_Init(sdspi_card_t *card) -{ - assert(card); - assert(card->host); - assert(card->host->setFrequency); - assert(card->host->exchange); - assert(card->host->getCurrentMilliseconds); - - sdspi_host_t *host; - uint32_t applicationCommand41Argument = 0U; - uint32_t startTime; - uint32_t currentTime; - uint32_t elapsedTime; - uint8_t response[5U]; - uint8_t applicationCommand41Response[5U]; - bool likelySdV1 = false; - - host = card->host; - /* Card must be initialized in 400KHZ. */ - if (host->setFrequency(SDMMC_CLOCK_400KHZ)) - { - return kStatus_SDSPI_SetFrequencyFailed; - } - - /* Reset the card by CMD0. */ - if (kStatus_Success != SDSPI_GoIdle(card)) - { - return kStatus_SDSPI_GoIdleFailed; - } - - /* Check the card's supported interface condition. */ - if (kStatus_Success != SDSPI_SendInterfaceCondition(card, 0xAAU, response)) - { - likelySdV1 = true; - } - else if ((response[3U] == 0x1U) || (response[4U] == 0xAAU)) - { - applicationCommand41Argument |= kSD_OcrHostCapacitySupportFlag; - } - else - { - return kStatus_SDSPI_SendInterfaceConditionFailed; - } - - /* Set card's interface condition according to host's capability and card's supported interface condition */ - startTime = host->getCurrentMilliseconds(); - do - { - if (kStatus_Success != - SDSPI_ApplicationSendOperationCondition(card, applicationCommand41Argument, applicationCommand41Response)) - { - return kStatus_SDSPI_SendOperationConditionFailed; - } - - currentTime = host->getCurrentMilliseconds(); - elapsedTime = (currentTime - startTime); - if (elapsedTime > 500U) - { - return kStatus_Timeout; - } - - if (!applicationCommand41Response[0U]) - { - break; - } - } while (applicationCommand41Response[0U] & kSDSPI_R1InIdleStateFlag); - - if (!likelySdV1) - { - if (kStatus_Success != SDSPI_ReadOcr(card)) - { - return kStatus_SDSPI_ReadOcrFailed; - } - if (card->ocr & kSD_OcrCardCapacitySupportFlag) - { - card->flags |= kSDSPI_SupportHighCapacityFlag; - } - } - - /* Force to use 512-byte length block, no matter which version. */ - if (kStatus_Success != SDSPI_SetBlockSize(card, 512U)) - { - return kStatus_SDSPI_SetBlockSizeFailed; - } - if (kStatus_Success != SDSPI_SendCsd(card)) - { - return kStatus_SDSPI_SendCsdFailed; - } - - /* Set to max frequency according to the max frequency information in CSD register. */ - SDSPI_SetMaxFrequencyNormalMode(card); - - /* Save capacity, read only attribute and CID, SCR registers. */ - SDSPI_CheckCapacity(card); - SDSPI_CheckReadOnly(card); - if (kStatus_Success != SDSPI_SendCid(card)) - { - return kStatus_SDSPI_SendCidFailed; - } - if (kStatus_Success != SDSPI_SendScr(card)) - { - return kStatus_SDSPI_SendCidFailed; - } - - return kStatus_Success; -} - -void SDSPI_Deinit(sdspi_card_t *card) -{ - assert(card); - - memset(card, 0, sizeof(sdspi_card_t)); -} - -bool SDSPI_CheckReadOnly(sdspi_card_t *card) -{ - assert(card); - - if ((card->csd.flags & kSD_CsdPermanentWriteProtectFlag) || (card->csd.flags & kSD_CsdTemporaryWriteProtectFlag)) - { - return true; - } - - return false; -} - -status_t SDSPI_ReadBlocks(sdspi_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) -{ - assert(card); - assert(card->host); - assert(buffer); - assert(blockCount); - - uint32_t offset; - uint32_t i; - sdspi_command_t command = {0}; - sdspi_host_t *host; - - offset = startBlock; - if (!IS_BLOCK_ACCESS(card)) - { - offset *= card->blockSize; - } - - /* Send command and reads data. */ - host = card->host; - command.argument = offset; - command.responseType = kSDSPI_ResponseTypeR1; - if (blockCount == 1U) - { - command.index = kSDMMC_ReadSingleBlock; - if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) - { - return kStatus_SDSPI_SendCommandFailed; - } - - if (kStatus_Success != SDSPI_Read(host, buffer, card->blockSize)) - { - return kStatus_SDSPI_ReadFailed; - } - } - else - { - command.index = kSDMMC_ReadMultipleBlock; - if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) - { - return kStatus_SDSPI_SendCommandFailed; - } - - for (i = 0U; i < blockCount; i++) - { - if (kStatus_Success != SDSPI_Read(host, buffer, card->blockSize)) - { - return kStatus_SDSPI_ReadFailed; - } - buffer += card->blockSize; - } - - /* Write stop transmission command after the last data block. */ - if (kStatus_Success != SDSPI_StopTransmission(card)) - { - return kStatus_SDSPI_StopTransmissionFailed; - } - } - - return kStatus_Success; -} - -status_t SDSPI_WriteBlocks(sdspi_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) -{ - assert(card); - assert(card->host); - assert(buffer); - assert(blockCount); - - uint32_t offset; - uint32_t i; - sdspi_host_t *host; - sdspi_command_t command = {0}; - - if (SDSPI_CheckReadOnly(card)) - { - return kStatus_SDSPI_WriteProtected; - } - - offset = startBlock; - if (!IS_BLOCK_ACCESS(card)) - { - offset *= card->blockSize; - } - - /* Send command and writes data. */ - host = card->host; - if (blockCount == 1U) - { - command.index = kSDMMC_WriteSingleBlock; - command.argument = offset; - command.responseType = kSDSPI_ResponseTypeR1; - if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) - { - return kStatus_SDSPI_SendCommandFailed; - } - - if (command.response[0U]) - { - return kStatus_SDSPI_ResponseError; - } - - if (kStatus_Success != SDSPI_Write(host, buffer, card->blockSize, kSDSPI_DataTokenSingleBlockWrite)) - { - return kStatus_SDSPI_WriteFailed; - } - } - else - { -#if defined FSL_SDSPI_ENABLE_PRE_ERASE_ON_WRITE - /* Pre-erase before writing data */ - if (kStatus_Success != SDSPI_SendApplicationCmd(card)) - { - return kStatus_SDSPI_SendApplicationCommandFailed; - } - - command.index = kSDAppSetWrBlkEraseCount; - command.argument = blockCount; - command.responseType = kSDSPI_ResponseTypeR1; - if (kStatus_Success != SDSPI_SendCommand(host->base, &command, FSL_SDSPI_TIMEOUT)) - { - return kStatus_SDSPI_SendCommandFailed; - } - - if (req->response[0U]) - { - return kStatus_SDSPI_ResponseError; - } -#endif - - memset(&command, 0U, sizeof(sdspi_command_t)); - command.index = kSDMMC_WriteMultipleBlock; - command.argument = offset; - command.responseType = kSDSPI_ResponseTypeR1; - if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) - { - return kStatus_SDSPI_SendCommandFailed; - } - - if (command.response[0U]) - { - return kStatus_SDSPI_ResponseError; - } - - for (i = 0U; i < blockCount; i++) - { - if (kStatus_Success != SDSPI_Write(host, buffer, card->blockSize, kSDSPI_DataTokenMultipleBlockWrite)) - { - return kStatus_SDSPI_WriteFailed; - } - buffer += card->blockSize; - } - if (kStatus_Success != SDSPI_Write(host, 0U, 0U, kSDSPI_DataTokenStopTransfer)) - { - return kStatus_SDSPI_WriteFailed; - } - - /* Wait the card programming end. */ - if (kStatus_Success != SDSPI_WaitReady(host, FSL_SDSPI_TIMEOUT)) - { - return kStatus_SDSPI_WaitReadyFailed; - } - } - - return kStatus_Success; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/.ignore_format.yml b/bsp/nxp/lpc/lpc55sxx/Libraries/.ignore_format.yml index edfd508c1fe..6235c0a1e14 100644 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/.ignore_format.yml +++ b/bsp/nxp/lpc/lpc55sxx/Libraries/.ignore_format.yml @@ -5,4 +5,4 @@ dir_path: - LPC55S06 - LPC5502 - LPC55S28 -- LPC55S36 +- LPC55S36 \ No newline at end of file diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_armcc.h b/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_armcc.h deleted file mode 100644 index a955d471391..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_armcc.h +++ /dev/null @@ -1,888 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file - * @version V5.3.2 - * @date 27. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use Arm Compiler Toolchain V4.0.677 or later!" -#endif - -/* CMSIS compiler control architecture macros */ -#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ - (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) - #define __ARM_ARCH_6M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) - #define __ARM_ARCH_7M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) - #define __ARM_ARCH_7EM__ 1 -#endif - - /* __ARM_ARCH_8M_BASE__ not applicable */ - /* __ARM_ARCH_8M_MAIN__ not applicable */ - /* __ARM_ARCH_8_1M_MAIN__ not applicable */ - -/* CMSIS compiler control DSP macros */ -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - #define __ARM_FEATURE_DSP 1 -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE static __forceinline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __declspec(noreturn) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed)) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT __packed struct -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION __packed union -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __memory_changed() -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) -#endif - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return result; -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; - __ISB(); -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1U); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#else - (void)fpscr; -#endif -} - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_armclang.h b/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_armclang.h deleted file mode 100644 index 69114177477..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_armclang.h +++ /dev/null @@ -1,1503 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armclang.h - * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V5.4.3 - * @date 27. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#pragma clang system_header /* treat file as system include file */ - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF) - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __builtin_bswap32(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __ROR(__REV(value), 16) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) (int16_t)__builtin_bswap16(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __builtin_arm_rbit - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __builtin_arm_ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} -#endif - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} -#endif - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr -#else -#define __get_FPSCR() ((uint32_t)0U) -#endif - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __set_FPSCR __builtin_arm_set_fpscr -#else -#define __set_FPSCR(x) ((void)(x)) -#endif - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -#define __SADD8 __builtin_arm_sadd8 -#define __QADD8 __builtin_arm_qadd8 -#define __SHADD8 __builtin_arm_shadd8 -#define __UADD8 __builtin_arm_uadd8 -#define __UQADD8 __builtin_arm_uqadd8 -#define __UHADD8 __builtin_arm_uhadd8 -#define __SSUB8 __builtin_arm_ssub8 -#define __QSUB8 __builtin_arm_qsub8 -#define __SHSUB8 __builtin_arm_shsub8 -#define __USUB8 __builtin_arm_usub8 -#define __UQSUB8 __builtin_arm_uqsub8 -#define __UHSUB8 __builtin_arm_uhsub8 -#define __SADD16 __builtin_arm_sadd16 -#define __QADD16 __builtin_arm_qadd16 -#define __SHADD16 __builtin_arm_shadd16 -#define __UADD16 __builtin_arm_uadd16 -#define __UQADD16 __builtin_arm_uqadd16 -#define __UHADD16 __builtin_arm_uhadd16 -#define __SSUB16 __builtin_arm_ssub16 -#define __QSUB16 __builtin_arm_qsub16 -#define __SHSUB16 __builtin_arm_shsub16 -#define __USUB16 __builtin_arm_usub16 -#define __UQSUB16 __builtin_arm_uqsub16 -#define __UHSUB16 __builtin_arm_uhsub16 -#define __SASX __builtin_arm_sasx -#define __QASX __builtin_arm_qasx -#define __SHASX __builtin_arm_shasx -#define __UASX __builtin_arm_uasx -#define __UQASX __builtin_arm_uqasx -#define __UHASX __builtin_arm_uhasx -#define __SSAX __builtin_arm_ssax -#define __QSAX __builtin_arm_qsax -#define __SHSAX __builtin_arm_shsax -#define __USAX __builtin_arm_usax -#define __UQSAX __builtin_arm_uqsax -#define __UHSAX __builtin_arm_uhsax -#define __USAD8 __builtin_arm_usad8 -#define __USADA8 __builtin_arm_usada8 -#define __SSAT16 __builtin_arm_ssat16 -#define __USAT16 __builtin_arm_usat16 -#define __UXTB16 __builtin_arm_uxtb16 -#define __UXTAB16 __builtin_arm_uxtab16 -#define __SXTB16 __builtin_arm_sxtb16 -#define __SXTAB16 __builtin_arm_sxtab16 -#define __SMUAD __builtin_arm_smuad -#define __SMUADX __builtin_arm_smuadx -#define __SMLAD __builtin_arm_smlad -#define __SMLADX __builtin_arm_smladx -#define __SMLALD __builtin_arm_smlald -#define __SMLALDX __builtin_arm_smlaldx -#define __SMUSD __builtin_arm_smusd -#define __SMUSDX __builtin_arm_smusdx -#define __SMLSD __builtin_arm_smlsd -#define __SMLSDX __builtin_arm_smlsdx -#define __SMLSLD __builtin_arm_smlsld -#define __SMLSLDX __builtin_arm_smlsldx -#define __SEL __builtin_arm_sel -#define __QADD __builtin_arm_qadd -#define __QSUB __builtin_arm_qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_armclang_ltm.h b/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_armclang_ltm.h deleted file mode 100644 index 1e255d5907f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_armclang_ltm.h +++ /dev/null @@ -1,1928 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armclang_ltm.h - * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V1.5.3 - * @date 27. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2018-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#pragma clang system_header /* treat file as system include file */ - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF) - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __builtin_bswap32(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __ROR(__REV(value), 16) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) (int16_t)__builtin_bswap16(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __builtin_arm_rbit - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __builtin_arm_ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} -#endif - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} -#endif - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr -#else -#define __get_FPSCR() ((uint32_t)0U) -#endif - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __set_FPSCR __builtin_arm_set_fpscr -#else -#define __set_FPSCR(x) ((void)(x)) -#endif - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_compiler.h b/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_compiler.h deleted file mode 100644 index adbf296f15a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_compiler.h +++ /dev/null @@ -1,283 +0,0 @@ -/**************************************************************************//** - * @file cmsis_compiler.h - * @brief CMSIS compiler generic header file - * @version V5.1.0 - * @date 09. October 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_COMPILER_H -#define __CMSIS_COMPILER_H - -#include - -/* - * Arm Compiler 4/5 - */ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - - -/* - * Arm Compiler 6.6 LTM (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) - #include "cmsis_armclang_ltm.h" - - /* - * Arm Compiler above 6.10.1 (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) - #include "cmsis_armclang.h" - - -/* - * GNU Compiler - */ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - - -/* - * IAR Compiler - */ -#elif defined ( __ICCARM__ ) - #include - - -/* - * TI Arm Compiler - */ -#elif defined ( __TI_ARM__ ) - #include - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __attribute__((packed)) - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed)) - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed)) - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) - #endif - #ifndef __RESTRICT - #define __RESTRICT __restrict - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -/* - * TASKING Compiler - */ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __packed__ - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __packed__ - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __packed__ - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __packed__ T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __align(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -/* - * COSMIC Compiler - */ -#elif defined ( __CSMC__ ) - #include - - #ifndef __ASM - #define __ASM _asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - // NO RETURN is automatically detected hence no warning here - #define __NO_RETURN - #endif - #ifndef __USED - #warning No compiler specific solution for __USED. __USED is ignored. - #define __USED - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __PACKED - #define __PACKED @packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT @packed struct - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION @packed union - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - @packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -#else - #error Unknown compiler. -#endif - - -#endif /* __CMSIS_COMPILER_H */ - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_gcc.h b/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_gcc.h deleted file mode 100644 index 67bda4ef3c3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_gcc.h +++ /dev/null @@ -1,2211 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS compiler GCC header file - * @version V5.4.1 - * @date 27. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -/* Fallback for __has_builtin */ -#ifndef __has_builtin - #define __has_builtin(x) (0) -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START - -/** - \brief Initializes data and bss sections - \details This default implementations initialized all data and additional bss - sections relying on .copy.table and .zero.table specified properly - in the used linker script. - - */ -__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) -{ - extern void _start(void) __NO_RETURN; - - typedef struct { - uint32_t const* src; - uint32_t* dest; - uint32_t wlen; - } __copy_table_t; - - typedef struct { - uint32_t* dest; - uint32_t wlen; - } __zero_table_t; - - extern const __copy_table_t __copy_table_start__; - extern const __copy_table_t __copy_table_end__; - extern const __zero_table_t __zero_table_start__; - extern const __zero_table_t __zero_table_end__; - - for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = pTable->src[i]; - } - } - - for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = 0u; - } - } - - _start(); -} - -#define __PROGRAM_START __cmsis_start -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP __StackTop -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT __StackLimit -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL __StackSeal -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __ASM volatile ("nop") - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __ASM volatile ("wfi":::"memory") - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __ASM volatile ("wfe":::"memory") - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __ASM volatile ("sev") - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__STATIC_FORCEINLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__STATIC_FORCEINLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__STATIC_FORCEINLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (int16_t)__builtin_bswap16(value); -#else - int16_t result; - - __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return result; -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__STATIC_FORCEINLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1, ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1, ARG2) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - return __builtin_arm_get_fpscr(); -#else - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#endif -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_set_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - __builtin_arm_set_fpscr(fpscr); -#else - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); -#endif -#else - (void)fpscr; -#endif -} - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1, ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - -#define __USAT16(ARG1, ARG2) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) -{ - uint32_t result; - if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { - __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); - } else { - result = __SXTB16(__ROR(op1, rotate)) ; - } - return result; -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) -{ - uint32_t result; - if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { - __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); - } else { - result = __SXTAB16(op1, __ROR(op2, rotate)); - } - return result; -} - - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -#define __PKHBT(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#pragma GCC diagnostic pop - -#endif /* __CMSIS_GCC_H */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_iccarm.h b/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_iccarm.h deleted file mode 100644 index 65b824b009c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_iccarm.h +++ /dev/null @@ -1,1002 +0,0 @@ -/**************************************************************************//** - * @file cmsis_iccarm.h - * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.3.0 - * @date 14. April 2021 - ******************************************************************************/ - -//------------------------------------------------------------------------------ -// -// Copyright (c) 2017-2021 IAR Systems -// Copyright (c) 2017-2021 Arm Limited. All rights reserved. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License") -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -//------------------------------------------------------------------------------ - - -#ifndef __CMSIS_ICCARM_H__ -#define __CMSIS_ICCARM_H__ - -#ifndef __ICCARM__ - #error This file should only be compiled by ICCARM -#endif - -#pragma system_include - -#define __IAR_FT _Pragma("inline=forced") __intrinsic - -#if (__VER__ >= 8000000) - #define __ICCARM_V8 1 -#else - #define __ICCARM_V8 0 -#endif - -#ifndef __ALIGNED - #if __ICCARM_V8 - #define __ALIGNED(x) __attribute__((aligned(x))) - #elif (__VER__ >= 7080000) - /* Needs IAR language extensions */ - #define __ALIGNED(x) __attribute__((aligned(x))) - #else - #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. - #define __ALIGNED(x) - #endif -#endif - - -/* Define compiler macros for CPU architecture, used in CMSIS 5. - */ -#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ -/* Macros already defined */ -#else - #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' - #if __ARM_ARCH == 6 - #define __ARM_ARCH_6M__ 1 - #elif __ARM_ARCH == 7 - #if __ARM_FEATURE_DSP - #define __ARM_ARCH_7EM__ 1 - #else - #define __ARM_ARCH_7M__ 1 - #endif - #endif /* __ARM_ARCH */ - #endif /* __ARM_ARCH_PROFILE == 'M' */ -#endif - -/* Alternativ core deduction for older ICCARM's */ -#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ - !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) - #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) - #define __ARM_ARCH_6M__ 1 - #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) - #define __ARM_ARCH_7M__ 1 - #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) - #define __ARM_ARCH_7EM__ 1 - #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #else - #error "Unknown target." - #endif -#endif - - - -#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 - #define __IAR_M0_FAMILY 1 -#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 - #define __IAR_M0_FAMILY 1 -#else - #define __IAR_M0_FAMILY 0 -#endif - - -#ifndef __ASM - #define __ASM __asm -#endif - -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -#ifndef __INLINE - #define __INLINE inline -#endif - -#ifndef __NO_RETURN - #if __ICCARM_V8 - #define __NO_RETURN __attribute__((__noreturn__)) - #else - #define __NO_RETURN _Pragma("object_attribute=__noreturn") - #endif -#endif - -#ifndef __PACKED - #if __ICCARM_V8 - #define __PACKED __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED __packed - #endif -#endif - -#ifndef __PACKED_STRUCT - #if __ICCARM_V8 - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_STRUCT __packed struct - #endif -#endif - -#ifndef __PACKED_UNION - #if __ICCARM_V8 - #define __PACKED_UNION union __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_UNION __packed union - #endif -#endif - -#ifndef __RESTRICT - #if __ICCARM_V8 - #define __RESTRICT __restrict - #else - /* Needs IAR language extensions */ - #define __RESTRICT restrict - #endif -#endif - -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif - -#ifndef __FORCEINLINE - #define __FORCEINLINE _Pragma("inline=forced") -#endif - -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE -#endif - -#ifndef __UNALIGNED_UINT16_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint16_t __iar_uint16_read(void const *ptr) -{ - return *(__packed uint16_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) -#endif - - -#ifndef __UNALIGNED_UINT16_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) -{ - *(__packed uint16_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint32_t __iar_uint32_read(void const *ptr) -{ - return *(__packed uint32_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) -#endif - -#ifndef __UNALIGNED_UINT32_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) -{ - *(__packed uint32_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32 /* deprecated */ -#pragma language=save -#pragma language=extended -__packed struct __iar_u32 { uint32_t v; }; -#pragma language=restore -#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) -#endif - -#ifndef __USED - #if __ICCARM_V8 - #define __USED __attribute__((used)) - #else - #define __USED _Pragma("__root") - #endif -#endif - -#undef __WEAK /* undo the definition from DLib_Defaults.h */ -#ifndef __WEAK - #if __ICCARM_V8 - #define __WEAK __attribute__((weak)) - #else - #define __WEAK _Pragma("__weak") - #endif -#endif - -#ifndef __PROGRAM_START -#define __PROGRAM_START __iar_program_start -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP CSTACK$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT CSTACK$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __vector_table -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE @".intvec" -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL STACKSEAL$$Base -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - -#ifndef __ICCARM_INTRINSICS_VERSION__ - #define __ICCARM_INTRINSICS_VERSION__ 0 -#endif - -#if __ICCARM_INTRINSICS_VERSION__ == 2 - - #if defined(__CLZ) - #undef __CLZ - #endif - #if defined(__REVSH) - #undef __REVSH - #endif - #if defined(__RBIT) - #undef __RBIT - #endif - #if defined(__SSAT) - #undef __SSAT - #endif - #if defined(__USAT) - #undef __USAT - #endif - - #include "iccarm_builtin.h" - - #define __disable_fault_irq __iar_builtin_disable_fiq - #define __disable_irq __iar_builtin_disable_interrupt - #define __enable_fault_irq __iar_builtin_enable_fiq - #define __enable_irq __iar_builtin_enable_interrupt - #define __arm_rsr __iar_builtin_rsr - #define __arm_wsr __iar_builtin_wsr - - - #define __get_APSR() (__arm_rsr("APSR")) - #define __get_BASEPRI() (__arm_rsr("BASEPRI")) - #define __get_CONTROL() (__arm_rsr("CONTROL")) - #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) - - #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - #define __get_FPSCR() (__arm_rsr("FPSCR")) - #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) - #else - #define __get_FPSCR() ( 0 ) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #define __get_IPSR() (__arm_rsr("IPSR")) - #define __get_MSP() (__arm_rsr("MSP")) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __get_MSPLIM() (0U) - #else - #define __get_MSPLIM() (__arm_rsr("MSPLIM")) - #endif - #define __get_PRIMASK() (__arm_rsr("PRIMASK")) - #define __get_PSP() (__arm_rsr("PSP")) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __get_PSPLIM() (0U) - #else - #define __get_PSPLIM() (__arm_rsr("PSPLIM")) - #endif - - #define __get_xPSR() (__arm_rsr("xPSR")) - - #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) - #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) - -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __arm_wsr("CONTROL", control); - __iar_builtin_ISB(); -} - - #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) - #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __set_MSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) - #endif - #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) - #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __set_PSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) - #endif - - #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) - -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __arm_wsr("CONTROL_NS", control); - __iar_builtin_ISB(); -} - - #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) - #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) - #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) - #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) - #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) - #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) - #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) - #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) - #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) - #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) - #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) - #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __TZ_get_PSPLIM_NS() (0U) - #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) - #else - #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) - #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) - #endif - - #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) - #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) - - #define __NOP __iar_builtin_no_operation - - #define __CLZ __iar_builtin_CLZ - #define __CLREX __iar_builtin_CLREX - - #define __DMB __iar_builtin_DMB - #define __DSB __iar_builtin_DSB - #define __ISB __iar_builtin_ISB - - #define __LDREXB __iar_builtin_LDREXB - #define __LDREXH __iar_builtin_LDREXH - #define __LDREXW __iar_builtin_LDREX - - #define __RBIT __iar_builtin_RBIT - #define __REV __iar_builtin_REV - #define __REV16 __iar_builtin_REV16 - - __IAR_FT int16_t __REVSH(int16_t val) - { - return (int16_t) __iar_builtin_REVSH(val); - } - - #define __ROR __iar_builtin_ROR - #define __RRX __iar_builtin_RRX - - #define __SEV __iar_builtin_SEV - - #if !__IAR_M0_FAMILY - #define __SSAT __iar_builtin_SSAT - #endif - - #define __STREXB __iar_builtin_STREXB - #define __STREXH __iar_builtin_STREXH - #define __STREXW __iar_builtin_STREX - - #if !__IAR_M0_FAMILY - #define __USAT __iar_builtin_USAT - #endif - - #define __WFE __iar_builtin_WFE - #define __WFI __iar_builtin_WFI - - #if __ARM_MEDIA__ - #define __SADD8 __iar_builtin_SADD8 - #define __QADD8 __iar_builtin_QADD8 - #define __SHADD8 __iar_builtin_SHADD8 - #define __UADD8 __iar_builtin_UADD8 - #define __UQADD8 __iar_builtin_UQADD8 - #define __UHADD8 __iar_builtin_UHADD8 - #define __SSUB8 __iar_builtin_SSUB8 - #define __QSUB8 __iar_builtin_QSUB8 - #define __SHSUB8 __iar_builtin_SHSUB8 - #define __USUB8 __iar_builtin_USUB8 - #define __UQSUB8 __iar_builtin_UQSUB8 - #define __UHSUB8 __iar_builtin_UHSUB8 - #define __SADD16 __iar_builtin_SADD16 - #define __QADD16 __iar_builtin_QADD16 - #define __SHADD16 __iar_builtin_SHADD16 - #define __UADD16 __iar_builtin_UADD16 - #define __UQADD16 __iar_builtin_UQADD16 - #define __UHADD16 __iar_builtin_UHADD16 - #define __SSUB16 __iar_builtin_SSUB16 - #define __QSUB16 __iar_builtin_QSUB16 - #define __SHSUB16 __iar_builtin_SHSUB16 - #define __USUB16 __iar_builtin_USUB16 - #define __UQSUB16 __iar_builtin_UQSUB16 - #define __UHSUB16 __iar_builtin_UHSUB16 - #define __SASX __iar_builtin_SASX - #define __QASX __iar_builtin_QASX - #define __SHASX __iar_builtin_SHASX - #define __UASX __iar_builtin_UASX - #define __UQASX __iar_builtin_UQASX - #define __UHASX __iar_builtin_UHASX - #define __SSAX __iar_builtin_SSAX - #define __QSAX __iar_builtin_QSAX - #define __SHSAX __iar_builtin_SHSAX - #define __USAX __iar_builtin_USAX - #define __UQSAX __iar_builtin_UQSAX - #define __UHSAX __iar_builtin_UHSAX - #define __USAD8 __iar_builtin_USAD8 - #define __USADA8 __iar_builtin_USADA8 - #define __SSAT16 __iar_builtin_SSAT16 - #define __USAT16 __iar_builtin_USAT16 - #define __UXTB16 __iar_builtin_UXTB16 - #define __UXTAB16 __iar_builtin_UXTAB16 - #define __SXTB16 __iar_builtin_SXTB16 - #define __SXTAB16 __iar_builtin_SXTAB16 - #define __SMUAD __iar_builtin_SMUAD - #define __SMUADX __iar_builtin_SMUADX - #define __SMMLA __iar_builtin_SMMLA - #define __SMLAD __iar_builtin_SMLAD - #define __SMLADX __iar_builtin_SMLADX - #define __SMLALD __iar_builtin_SMLALD - #define __SMLALDX __iar_builtin_SMLALDX - #define __SMUSD __iar_builtin_SMUSD - #define __SMUSDX __iar_builtin_SMUSDX - #define __SMLSD __iar_builtin_SMLSD - #define __SMLSDX __iar_builtin_SMLSDX - #define __SMLSLD __iar_builtin_SMLSLD - #define __SMLSLDX __iar_builtin_SMLSLDX - #define __SEL __iar_builtin_SEL - #define __QADD __iar_builtin_QADD - #define __QSUB __iar_builtin_QSUB - #define __PKHBT __iar_builtin_PKHBT - #define __PKHTB __iar_builtin_PKHTB - #endif - -#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #define __CLZ __cmsis_iar_clz_not_active - #define __SSAT __cmsis_iar_ssat_not_active - #define __USAT __cmsis_iar_usat_not_active - #define __RBIT __cmsis_iar_rbit_not_active - #define __get_APSR __cmsis_iar_get_APSR_not_active - #endif - - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #define __get_FPSCR __cmsis_iar_get_FPSR_not_active - #define __set_FPSCR __cmsis_iar_set_FPSR_not_active - #endif - - #ifdef __INTRINSICS_INCLUDED - #error intrinsics.h is already included previously! - #endif - - #include - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #undef __CLZ - #undef __SSAT - #undef __USAT - #undef __RBIT - #undef __get_APSR - - __STATIC_INLINE uint8_t __CLZ(uint32_t data) - { - if (data == 0U) { return 32U; } - - uint32_t count = 0U; - uint32_t mask = 0x80000000U; - - while ((data & mask) == 0U) - { - count += 1U; - mask = mask >> 1U; - } - return count; - } - - __STATIC_INLINE uint32_t __RBIT(uint32_t v) - { - uint8_t sc = 31U; - uint32_t r = v; - for (v >>= 1U; v; v >>= 1U) - { - r <<= 1U; - r |= v & 1U; - sc--; - } - return (r << sc); - } - - __STATIC_INLINE uint32_t __get_APSR(void) - { - uint32_t res; - __asm("MRS %0,APSR" : "=r" (res)); - return res; - } - - #endif - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #undef __get_FPSCR - #undef __set_FPSCR - #define __get_FPSCR() (0) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #pragma diag_suppress=Pe940 - #pragma diag_suppress=Pe177 - - #define __enable_irq __enable_interrupt - #define __disable_irq __disable_interrupt - #define __NOP __no_operation - - #define __get_xPSR __get_PSR - - #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) - - __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) - { - return __LDREX((unsigned long *)ptr); - } - - __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) - { - return __STREX(value, (unsigned long *)ptr); - } - #endif - - - /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - #if (__CORTEX_M >= 0x03) - - __IAR_FT uint32_t __RRX(uint32_t value) - { - uint32_t result; - __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); - return(result); - } - - __IAR_FT void __set_BASEPRI_MAX(uint32_t value) - { - __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); - } - - - #define __enable_fault_irq __enable_fiq - #define __disable_fault_irq __disable_fiq - - - #endif /* (__CORTEX_M >= 0x03) */ - - __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) - { - return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); - } - - #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - __IAR_FT uint32_t __get_MSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,MSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_MSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR MSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __get_PSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,PSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_PSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR PSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) - { - __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); - __iar_builtin_ISB(); - } - - __IAR_FT uint32_t __TZ_get_PSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PSP_NS(uint32_t value) - { - __asm volatile("MSR PSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_MSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSP_NS(uint32_t value) - { - __asm volatile("MSR MSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_SP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,SP_NS" : "=r" (res)); - return res; - } - __IAR_FT void __TZ_set_SP_NS(uint32_t value) - { - __asm volatile("MSR SP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) - { - __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) - { - __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) - { - __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) - { - __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); - } - - #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - -#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) - -#if __IAR_M0_FAMILY - __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) - { - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; - } - - __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) - { - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; - } -#endif - -#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - - __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) - { - uint32_t res; - __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) - { - uint32_t res; - __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) - { - uint32_t res; - __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return res; - } - - __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) - { - __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) - { - __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) - { - __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); - } - -#endif /* (__CORTEX_M >= 0x03) */ - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - - __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return res; - } - - __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) - { - __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) - { - __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) - { - __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - -#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#undef __IAR_FT -#undef __IAR_M0_FAMILY -#undef __ICCARM_V8 - -#pragma diag_default=Pe940 -#pragma diag_default=Pe177 - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_version.h b/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_version.h deleted file mode 100644 index 2f048e4552d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/cmsis_version.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************//** - * @file cmsis_version.h - * @brief CMSIS Core(M) Version definitions - * @version V5.0.4 - * @date 23. July 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CMSIS_VERSION_H -#define __CMSIS_VERSION_H - -/* CMSIS Version definitions */ -#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */ -#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ - __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/core_cm33.h b/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/core_cm33.h deleted file mode 100644 index f9cf6ab183a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/core_cm33.h +++ /dev/null @@ -1,3265 +0,0 @@ -/**************************************************************************//** - * @file core_cm33.h - * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File - * @version V5.2.2 - * @date 04. June 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_CM33_H_GENERIC -#define __CORE_CM33_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M33 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM33 definitions */ -#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ - __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (33U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined (__TARGET_FPU_VFP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined (__ARM_FP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined (__ARMVFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined (__TI_VFP_SUPPORT__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined (__FPU_VFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM33_H_DEPENDANT -#define __CORE_CM33_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM33_REV - #define __CM33_REV 0x0000U - #warning "__CM33_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M33 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ - __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ - __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration Test FIFO Test Data 0 Register Definitions */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ -#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ -#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ -#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ - -/* TPI Integration Test ATB Control Register 2 Register Definitions */ -#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ -#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ - -#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ -#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ - -#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ -#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ - -#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ -#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ - -/* TPI Integration Test FIFO Test Data 1 Register Definitions */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ -#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ -#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ -#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ - -/* TPI Integration Test ATB Control Register 0 Definitions */ -#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ -#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ - -#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ -#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ - -#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ -#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ - -#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ -#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and VFP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and VFP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and VFP Feature Register 2 Definitions */ -#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ -#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ - -/*@} end of group CMSIS_FPU */ - -/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/* DHCSR, Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ -#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/* DCRSR, Debug Core Register Select Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/* DCRDR, Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ -#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ - -#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ -#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ - -#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ -#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ - -#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ -#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ - -#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ -#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ - -#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ -#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ - -#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ -#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ - -#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ -#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ -#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ - -#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ -#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ - -#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ -#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ - -#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ -#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ - -#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ -#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ - -#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ -#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/* DSCSR, Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/* DLAR, SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/* DLSR, SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/* DDEVARCH, SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/* DDEVTYPE, SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ - #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ - #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ - #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ - #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ - #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ - #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/mpu_armv8.h b/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/mpu_armv8.h deleted file mode 100644 index 3de16efc86a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/mpu_armv8.h +++ /dev/null @@ -1,352 +0,0 @@ -/****************************************************************************** - * @file mpu_armv8.h - * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU - * @version V5.1.3 - * @date 03. February 2021 - ******************************************************************************/ -/* - * Copyright (c) 2017-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_MPU_ARMV8_H -#define ARM_MPU_ARMV8_H - -/** \brief Attribute for device memory (outer only) */ -#define ARM_MPU_ATTR_DEVICE ( 0U ) - -/** \brief Attribute for non-cacheable, normal memory */ -#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) - -/** \brief Attribute for normal memory (outer and inner) -* \param NT Non-Transient: Set to 1 for non-transient data. -* \param WB Write-Back: Set to 1 to use write-back update policy. -* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. -* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. -*/ -#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ - ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) - -/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) - -/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) - -/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGRE (2U) - -/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_GRE (3U) - -/** \brief Memory Attribute -* \param O Outer memory attributes -* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes -*/ -#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) - -/** \brief Normal memory non-shareable */ -#define ARM_MPU_SH_NON (0U) - -/** \brief Normal memory outer shareable */ -#define ARM_MPU_SH_OUTER (2U) - -/** \brief Normal memory inner shareable */ -#define ARM_MPU_SH_INNER (3U) - -/** \brief Memory access permissions -* \param RO Read-Only: Set to 1 for read-only memory. -* \param NP Non-Privileged: Set to 1 for non-privileged memory. -*/ -#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) - -/** \brief Region Base Address Register value -* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. -* \param SH Defines the Shareability domain for this memory region. -* \param RO Read-Only: Set to 1 for a read-only memory region. -* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. -* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. -*/ -#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ - (((BASE) & MPU_RBAR_BASE_Msk) | \ - (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ - ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ - (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) - -/** \brief Region Limit Address Register value -* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -* \param IDX The attribute index to be associated with this memory region. -*/ -#define ARM_MPU_RLAR(LIMIT, IDX) \ - (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ - (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ - (MPU_RLAR_EN_Msk)) - -#if defined(MPU_RLAR_PXN_Pos) - -/** \brief Region Limit Address Register with PXN value -* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. -* \param IDX The attribute index to be associated with this memory region. -*/ -#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ - (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ - (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ - (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ - (MPU_RLAR_EN_Msk)) - -#endif - -/** -* Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; /*!< Region Base Address Register value */ - uint32_t RLAR; /*!< Region Limit Address Register value */ -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DMB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} - -#ifdef MPU_NS -/** Enable the Non-secure MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) -{ - __DMB(); - MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the Non-secure MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable_NS(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} -#endif - -/** Set the memory attribute encoding to the given MPU. -* \param mpu Pointer to the MPU to be configured. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) -{ - const uint8_t reg = idx / 4U; - const uint32_t pos = ((idx % 4U) * 8U); - const uint32_t mask = 0xFFU << pos; - - if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { - return; // invalid index - } - - mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); -} - -/** Set the memory attribute encoding. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU, idx, attr); -} - -#ifdef MPU_NS -/** Set the memory attribute encoding to the Non-secure MPU. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); -} -#endif - -/** Clear and disable the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) -{ - mpu->RNR = rnr; - mpu->RLAR = 0U; -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU, rnr); -} - -#ifdef MPU_NS -/** Clear and disable the given Non-secure MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU_NS, rnr); -} -#endif - -/** Configure the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - mpu->RNR = rnr; - mpu->RBAR = rbar; - mpu->RLAR = rlar; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); -} - -#ifdef MPU_NS -/** Configure the given Non-secure MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); -} -#endif - -/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table to the given MPU. -* \param mpu Pointer to the MPU registers to be used. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - if (cnt == 1U) { - mpu->RNR = rnr; - ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); - } else { - uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); - uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; - - mpu->RNR = rnrBase; - while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { - uint32_t c = MPU_TYPE_RALIASES - rnrOffset; - ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); - table += c; - cnt -= c; - rnrOffset = 0U; - rnrBase += MPU_TYPE_RALIASES; - mpu->RNR = rnrBase; - } - - ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); - } -} - -/** Load the given number of MPU regions from a table. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU, rnr, table, cnt); -} - -#ifdef MPU_NS -/** Load the given number of MPU regions from a table to the Non-secure MPU. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); -} -#endif - -#endif - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/tz_context.h b/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/tz_context.h deleted file mode 100644 index 0d09749f3a5..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/Core/Include/tz_context.h +++ /dev/null @@ -1,70 +0,0 @@ -/****************************************************************************** - * @file tz_context.h - * @brief Context Management for Armv8-M TrustZone - * @version V1.0.1 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2017-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef TZ_CONTEXT_H -#define TZ_CONTEXT_H - -#include - -#ifndef TZ_MODULEID_T -#define TZ_MODULEID_T -/// \details Data type that identifies secure software modules called by a process. -typedef uint32_t TZ_ModuleId_t; -#endif - -/// \details TZ Memory ID identifies an allocated memory slot. -typedef uint32_t TZ_MemoryId_t; - -/// Initialize secure context memory system -/// \return execution status (1: success, 0: error) -uint32_t TZ_InitContextSystem_S (void); - -/// Allocate context memory for calling secure software modules in TrustZone -/// \param[in] module identifies software modules called from non-secure mode -/// \return value != 0 id TrustZone memory slot identifier -/// \return value 0 no memory available or internal error -TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); - -/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); - -/// Load secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); - -/// Store secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); - -#endif // TZ_CONTEXT_H diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/LICENSE.txt b/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/LICENSE.txt deleted file mode 100644 index 8dada3edaf5..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/CMSIS/LICENSE.txt +++ /dev/null @@ -1,201 +0,0 @@ - Apache License - Version 2.0, January 2004 - http://www.apache.org/licenses/ - - TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION - - 1. 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rev. 1.0 (2020-04-09) -** Initial version based on Niobe4mini -** -** ################################################################### -*/ - -/*! - * @file LPC55S06.h - * @version 1.0 - * @date 2020-04-09 - * @brief CMSIS Peripheral Access Layer for LPC55S06 - * - * CMSIS Peripheral Access Layer for LPC55S06 - */ - -#ifndef _LPC55S06_H_ -#define _LPC55S06_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0000U - - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 77 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Auxiliary constants */ - NotAvail_IRQn = -128, /**< Not available device specific interrupt */ - - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ - - /* Device specific interrupts */ - WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */ - DMA0_IRQn = 1, /**< DMA0 controller */ - GINT0_IRQn = 2, /**< GPIO group 0 */ - GINT1_IRQn = 3, /**< GPIO group 1 */ - PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ - PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ - PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ - PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ - UTICK0_IRQn = 8, /**< Micro-tick Timer */ - MRT0_IRQn = 9, /**< Multi-rate timer */ - CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ - CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ - SCT0_IRQn = 12, /**< SCTimer/PWM */ - CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ - FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - ADC0_IRQn = 22, /**< ADC0 */ - Reserved39_IRQn = 23, /**< Reserved interrupt */ - ACMP_IRQn = 24, /**< ACMP interrupts */ - Reserved41_IRQn = 25, /**< Reserved interrupt */ - Reserved42_IRQn = 26, /**< Reserved interrupt */ - Reserved43_IRQn = 27, /**< Reserved interrupt */ - Reserved44_IRQn = 28, /**< Reserved interrupt */ - RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ - Reserved46_IRQn = 30, /**< Reserved interrupt */ - Reserved47_IRQn = 31, /**< Reserved interrupt */ - PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ - PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ - PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ - PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ - CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ - CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ - OS_EVENT_IRQn = 38, /**< OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ - Reserved55_IRQn = 39, /**< Reserved interrupt */ - Reserved56_IRQn = 40, /**< Reserved interrupt */ - Reserved57_IRQn = 41, /**< Reserved interrupt */ - Reserved58_IRQn = 42, /**< Reserved interrupt */ - CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */ - CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */ - Reserved61_IRQn = 45, /**< Reserved interrupt */ - Reserved62_IRQn = 46, /**< Reserved interrupt */ - Reserved63_IRQn = 47, /**< Reserved interrupt */ - Reserved64_IRQn = 48, /**< Reserved interrupt */ - SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */ - SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */ - SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */ - PLU_IRQn = 52, /**< PLU interrupt */ - SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */ - HASHCRYPT_IRQn = 54, /**< SHA interrupt */ - CASER_IRQn = 55, /**< CASPER interrupt */ - PUF_IRQn = 56, /**< PUF interrupt */ - Reserved73_IRQn = 57, /**< Reserved interrupt */ - DMA1_IRQn = 58, /**< DMA1 interrupt */ - FLEXCOMM8_IRQn = 59, /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */ - CDOG_IRQn = 60 /**< CDOG interrupt */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M33 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration - * @{ - */ - -#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ -#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ -#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ -#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ - -#include "core_cm33.h" /* Core Peripheral Access Layer */ -#include "system_LPC55S06.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Mapping Information - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Mapping_Information Mapping Information - * @{ - */ - -/** Mapping Information */ -/*! - * @addtogroup dma_request - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief Structure for the DMA hardware request - * - * Defines the structure for the DMA hardware request collections. The user can configure the - * hardware request to trigger the DMA transfer accordingly. The index - * of the hardware request varies according to the to SoC. - */ -typedef enum _dma_request_source -{ - kDma0RequestHashCrypt = 0U, /**< HashCrypt */ - kDma1RequestHashCrypt = 0U, /**< HashCrypt */ - kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ - kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ - kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ - kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ - kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ - kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ - kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ - kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ - kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ - kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ - kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ - kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ - kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ - kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ - kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ - kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ - kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ - kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ - kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */ - kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */ - kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */ - kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */ - kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */ - kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */ - kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */ - kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */ - kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */ - kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */ - kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */ - kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */ - kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */ -} dma_request_source_t; - -/* @} */ - - -/*! - * @} - */ /* end of group Mapping_Information */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #else - #pragma push - #pragma anon_unions - #endif -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ - __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ - __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ - __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ - __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ - __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ - uint8_t RESERVED_1[12]; - __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ - __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ - uint8_t RESERVED_2[4]; - __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ - uint8_t RESERVED_3[92]; - __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ - __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ - uint8_t RESERVED_4[8]; - __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ - __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ - struct { /* offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ - } CMD[15]; - uint8_t RESERVED_5[136]; - __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_6[240]; - __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ - uint8_t RESERVED_7[248]; - __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ - uint8_t RESERVED_8[124]; - __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ - -#define ADC_VERID_RES_MASK (0x1U) -#define ADC_VERID_RES_SHIFT (0U) -/*! RES - Resolution - * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. - * 0b1..Up to 16-bit differential/16-bit single ended resolution supported. - */ -#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) - -#define ADC_VERID_DIFFEN_MASK (0x2U) -#define ADC_VERID_DIFFEN_SHIFT (1U) -/*! DIFFEN - Differential Supported - * 0b0..Differential operation not supported. - * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented. - */ -#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) - -#define ADC_VERID_MVI_MASK (0x8U) -#define ADC_VERID_MVI_SHIFT (3U) -/*! MVI - Multi Vref Implemented - * 0b0..Single voltage reference high (VREFH) input supported. - * 0b1..Multiple voltage reference high (VREFH) inputs supported. - */ -#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) - -#define ADC_VERID_CSW_MASK (0x70U) -#define ADC_VERID_CSW_SHIFT (4U) -/*! CSW - Channel Scale Width - * 0b000..Channel scaling not supported. - * 0b001..Channel scaling supported. 1-bit CSCALE control field. - * 0b110..Channel scaling supported. 6-bit CSCALE control field. - */ -#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) - -#define ADC_VERID_VR1RNGI_MASK (0x100U) -#define ADC_VERID_VR1RNGI_SHIFT (8U) -/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented - * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. - * 0b1..Range control required. CFG[VREF1RNG] is implemented. - */ -#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) - -#define ADC_VERID_IADCKI_MASK (0x200U) -#define ADC_VERID_IADCKI_SHIFT (9U) -/*! IADCKI - Internal ADC Clock implemented - * 0b0..Internal clock source not implemented. - * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. - */ -#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) - -#define ADC_VERID_CALOFSI_MASK (0x400U) -#define ADC_VERID_CALOFSI_SHIFT (10U) -/*! CALOFSI - Calibration Function Implemented - * 0b0..Calibration Not Implemented. - * 0b1..Calibration Implemented. - */ -#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) - -#define ADC_VERID_NUM_SEC_MASK (0x800U) -#define ADC_VERID_NUM_SEC_SHIFT (11U) -/*! NUM_SEC - Number of Single Ended Outputs Supported - * 0b0..This design supports one single ended conversion at a time. - * 0b1..This design supports two simultanious single ended conversions. - */ -#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) - -#define ADC_VERID_NUM_FIFO_MASK (0x7000U) -#define ADC_VERID_NUM_FIFO_SHIFT (12U) -/*! NUM_FIFO - Number of FIFOs - * 0b000..N/A - * 0b001..This design supports one result FIFO. - * 0b010..This design supports two result FIFOs. - * 0b011..This design supports three result FIFOs. - * 0b100..This design supports four result FIFOs. - */ -#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) - -#define ADC_VERID_MINOR_MASK (0xFF0000U) -#define ADC_VERID_MINOR_SHIFT (16U) -/*! MINOR - Minor Version Number - */ -#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) - -#define ADC_VERID_MAJOR_MASK (0xFF000000U) -#define ADC_VERID_MAJOR_SHIFT (24U) -/*! MAJOR - Major Version Number - */ -#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ - -#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) -#define ADC_PARAM_TRIG_NUM_SHIFT (0U) -/*! TRIG_NUM - Trigger Number - */ -#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) - -#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) -#define ADC_PARAM_FIFOSIZE_SHIFT (8U) -/*! FIFOSIZE - Result FIFO Depth - * 0b00000001..Result FIFO depth = 1 dataword. - * 0b00000100..Result FIFO depth = 4 datawords. - * 0b00001000..Result FIFO depth = 8 datawords. - * 0b00010000..Result FIFO depth = 16 datawords. - * 0b00100000..Result FIFO depth = 32 datawords. - * 0b01000000..Result FIFO depth = 64 datawords. - */ -#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) - -#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) -#define ADC_PARAM_CV_NUM_SHIFT (16U) -/*! CV_NUM - Compare Value Number - */ -#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) - -#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) -#define ADC_PARAM_CMD_NUM_SHIFT (24U) -/*! CMD_NUM - Command Buffer Number - */ -#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) -/*! @} */ - -/*! @name CTRL - ADC Control Register */ -/*! @{ */ - -#define ADC_CTRL_ADCEN_MASK (0x1U) -#define ADC_CTRL_ADCEN_SHIFT (0U) -/*! ADCEN - ADC Enable - * 0b0..ADC is disabled. - * 0b1..ADC is enabled. - */ -#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) - -#define ADC_CTRL_RST_MASK (0x2U) -#define ADC_CTRL_RST_SHIFT (1U) -/*! RST - Software Reset - * 0b0..ADC logic is not reset. - * 0b1..ADC logic is reset. - */ -#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) - -#define ADC_CTRL_DOZEN_MASK (0x4U) -#define ADC_CTRL_DOZEN_SHIFT (2U) -/*! DOZEN - Doze Enable - * 0b0..ADC is enabled in Doze mode. - * 0b1..ADC is disabled in Doze mode. - */ -#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) - -#define ADC_CTRL_CAL_REQ_MASK (0x8U) -#define ADC_CTRL_CAL_REQ_SHIFT (3U) -/*! CAL_REQ - Auto-Calibration Request - * 0b0..No request for auto-calibration has been made. - * 0b1..A request for auto-calibration has been made - */ -#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) - -#define ADC_CTRL_CALOFS_MASK (0x10U) -#define ADC_CTRL_CALOFS_SHIFT (4U) -/*! CALOFS - Configure for offset calibration function - * 0b0..Calibration function disabled - * 0b1..Request for offset calibration function - */ -#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) - -#define ADC_CTRL_RSTFIFO0_MASK (0x100U) -#define ADC_CTRL_RSTFIFO0_SHIFT (8U) -/*! RSTFIFO0 - Reset FIFO 0 - * 0b0..No effect. - * 0b1..FIFO 0 is reset. - */ -#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) - -#define ADC_CTRL_RSTFIFO1_MASK (0x200U) -#define ADC_CTRL_RSTFIFO1_SHIFT (9U) -/*! RSTFIFO1 - Reset FIFO 1 - * 0b0..No effect. - * 0b1..FIFO 1 is reset. - */ -#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) - -#define ADC_CTRL_CAL_AVGS_MASK (0x70000U) -#define ADC_CTRL_CAL_AVGS_SHIFT (16U) -/*! CAL_AVGS - Auto-Calibration Averages - * 0b000..Single conversion. - * 0b001..2 conversions averaged. - * 0b010..4 conversions averaged. - * 0b011..8 conversions averaged. - * 0b100..16 conversions averaged. - * 0b101..32 conversions averaged. - * 0b110..64 conversions averaged. - * 0b111..128 conversions averaged. - */ -#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) -/*! @} */ - -/*! @name STAT - ADC Status Register */ -/*! @{ */ - -#define ADC_STAT_RDY0_MASK (0x1U) -#define ADC_STAT_RDY0_SHIFT (0U) -/*! RDY0 - Result FIFO 0 Ready Flag - * 0b0..Result FIFO 0 data level not above watermark level. - * 0b1..Result FIFO 0 holding data above watermark level. - */ -#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) - -#define ADC_STAT_FOF0_MASK (0x2U) -#define ADC_STAT_FOF0_SHIFT (1U) -/*! FOF0 - Result FIFO 0 Overflow Flag - * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) - -#define ADC_STAT_RDY1_MASK (0x4U) -#define ADC_STAT_RDY1_SHIFT (2U) -/*! RDY1 - Result FIFO1 Ready Flag - * 0b0..Result FIFO1 data level not above watermark level. - * 0b1..Result FIFO1 holding data above watermark level. - */ -#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) - -#define ADC_STAT_FOF1_MASK (0x8U) -#define ADC_STAT_FOF1_SHIFT (3U) -/*! FOF1 - Result FIFO1 Overflow Flag - * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) - -#define ADC_STAT_TEXC_INT_MASK (0x100U) -#define ADC_STAT_TEXC_INT_SHIFT (8U) -/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception - * 0b0..No trigger exceptions have occurred. - * 0b1..A trigger exception has occurred and is pending acknowledgement. - */ -#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) - -#define ADC_STAT_TCOMP_INT_MASK (0x200U) -#define ADC_STAT_TCOMP_INT_SHIFT (9U) -/*! TCOMP_INT - Interrupt Flag For Trigger Completion - * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. - * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. - */ -#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) - -#define ADC_STAT_CAL_RDY_MASK (0x400U) -#define ADC_STAT_CAL_RDY_SHIFT (10U) -/*! CAL_RDY - Calibration Ready - * 0b0..Calibration is incomplete or hasn't been ran. - * 0b1..The ADC is calibrated. - */ -#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) - -#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) -#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) -/*! ADC_ACTIVE - ADC Active - * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. - * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. - */ -#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) - -#define ADC_STAT_TRGACT_MASK (0xF0000U) -#define ADC_STAT_TRGACT_SHIFT (16U) -/*! TRGACT - Trigger Active - * 0b0000..Command (sequence) associated with Trigger 0 currently being executed. - * 0b0001..Command (sequence) associated with Trigger 1 currently being executed. - * 0b0010..Command (sequence) associated with Trigger 2 currently being executed. - * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed. - */ -#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) - -#define ADC_STAT_CMDACT_MASK (0xF000000U) -#define ADC_STAT_CMDACT_SHIFT (24U) -/*! CMDACT - Command Active - * 0b0000..No command is currently in progress. - * 0b0001..Command 1 currently being executed. - * 0b0010..Command 2 currently being executed. - * 0b0011-0b1111..Associated command number is currently being executed. - */ -#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) -/*! @} */ - -/*! @name IE - Interrupt Enable Register */ -/*! @{ */ - -#define ADC_IE_FWMIE0_MASK (0x1U) -#define ADC_IE_FWMIE0_SHIFT (0U) -/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable - * 0b0..FIFO 0 watermark interrupts are not enabled. - * 0b1..FIFO 0 watermark interrupts are enabled. - */ -#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) - -#define ADC_IE_FOFIE0_MASK (0x2U) -#define ADC_IE_FOFIE0_SHIFT (1U) -/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable - * 0b0..FIFO 0 overflow interrupts are not enabled. - * 0b1..FIFO 0 overflow interrupts are enabled. - */ -#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) - -#define ADC_IE_FWMIE1_MASK (0x4U) -#define ADC_IE_FWMIE1_SHIFT (2U) -/*! FWMIE1 - FIFO1 Watermark Interrupt Enable - * 0b0..FIFO1 watermark interrupts are not enabled. - * 0b1..FIFO1 watermark interrupts are enabled. - */ -#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) - -#define ADC_IE_FOFIE1_MASK (0x8U) -#define ADC_IE_FOFIE1_SHIFT (3U) -/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable - * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) - -#define ADC_IE_TEXC_IE_MASK (0x100U) -#define ADC_IE_TEXC_IE_SHIFT (8U) -/*! TEXC_IE - Trigger Exception Interrupt Enable - * 0b0..Trigger exception interrupts are disabled. - * 0b1..Trigger exception interrupts are enabled. - */ -#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) - -#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U) -#define ADC_IE_TCOMP_IE_SHIFT (16U) -/*! TCOMP_IE - Trigger Completion Interrupt Enable - * 0b0000000000000000..Trigger completion interrupts are disabled. - * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only. - * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only. - * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled. - * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source. - */ -#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) -/*! @} */ - -/*! @name DE - DMA Enable Register */ -/*! @{ */ - -#define ADC_DE_FWMDE0_MASK (0x1U) -#define ADC_DE_FWMDE0_SHIFT (0U) -/*! FWMDE0 - FIFO 0 Watermark DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) - -#define ADC_DE_FWMDE1_MASK (0x2U) -#define ADC_DE_FWMDE1_SHIFT (1U) -/*! FWMDE1 - FIFO1 Watermark DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) -/*! @} */ - -/*! @name CFG - ADC Configuration Register */ -/*! @{ */ - -#define ADC_CFG_TPRICTRL_MASK (0x3U) -#define ADC_CFG_TPRICTRL_SHIFT (0U) -/*! TPRICTRL - ADC trigger priority control - * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted - * and the new command specified by the trigger is started. - * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after - * after completing the current conversion. If averaging is enabled, the averaging loop will be completed. - * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. - * 0b10..If a higher priority trigger is received during command processing, the current command will be - * completed (averaging, looping, compare) before servicing the higher priority trigger. - * 0b11..RESERVED - */ -#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) - -#define ADC_CFG_PWRSEL_MASK (0x30U) -#define ADC_CFG_PWRSEL_SHIFT (4U) -/*! PWRSEL - Power Configuration Select - * 0b00..Lowest power setting. - * 0b01..Higher power setting than 0b0. - * 0b10..Higher power setting than 0b1. - * 0b11..Highest power setting. - */ -#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) - -#define ADC_CFG_REFSEL_MASK (0xC0U) -#define ADC_CFG_REFSEL_SHIFT (6U) -/*! REFSEL - Voltage Reference Selection - * 0b00..(Default) Option 1 setting. - * 0b01..Option 2 setting. - * 0b10..Option 3 setting. - * 0b11..Reserved - */ -#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) - -#define ADC_CFG_TRES_MASK (0x100U) -#define ADC_CFG_TRES_SHIFT (8U) -/*! TRES - Trigger Resume Enable - * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. - * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. - */ -#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) - -#define ADC_CFG_TCMDRES_MASK (0x200U) -#define ADC_CFG_TCMDRES_SHIFT (9U) -/*! TCMDRES - Trigger Command Resume - * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. - * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. - */ -#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) - -#define ADC_CFG_HPT_EXDI_MASK (0x400U) -#define ADC_CFG_HPT_EXDI_SHIFT (10U) -/*! HPT_EXDI - High Priority Trigger Exception Disable - * 0b0..High priority trigger exceptions are enabled. - * 0b1..High priority trigger exceptions are disabled. - */ -#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) - -#define ADC_CFG_PUDLY_MASK (0xFF0000U) -#define ADC_CFG_PUDLY_SHIFT (16U) -/*! PUDLY - Power Up Delay - */ -#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) - -#define ADC_CFG_PWREN_MASK (0x10000000U) -#define ADC_CFG_PWREN_SHIFT (28U) -/*! PWREN - ADC Analog Pre-Enable - * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. - * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost - * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN - * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. - * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be - * executed. - */ -#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) -/*! @} */ - -/*! @name PAUSE - ADC Pause Register */ -/*! @{ */ - -#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) -#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) -/*! PAUSEDLY - Pause Delay - */ -#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) - -#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) -#define ADC_PAUSE_PAUSEEN_SHIFT (31U) -/*! PAUSEEN - PAUSE Option Enable - * 0b0..Pause operation disabled - * 0b1..Pause operation enabled - */ -#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) -/*! @} */ - -/*! @name SWTRIG - Software Trigger Register */ -/*! @{ */ - -#define ADC_SWTRIG_SWT0_MASK (0x1U) -#define ADC_SWTRIG_SWT0_SHIFT (0U) -/*! SWT0 - Software trigger 0 event - * 0b0..No trigger 0 event generated. - * 0b1..Trigger 0 event generated. - */ -#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) - -#define ADC_SWTRIG_SWT1_MASK (0x2U) -#define ADC_SWTRIG_SWT1_SHIFT (1U) -/*! SWT1 - Software trigger 1 event - * 0b0..No trigger 1 event generated. - * 0b1..Trigger 1 event generated. - */ -#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) - -#define ADC_SWTRIG_SWT2_MASK (0x4U) -#define ADC_SWTRIG_SWT2_SHIFT (2U) -/*! SWT2 - Software trigger 2 event - * 0b0..No trigger 2 event generated. - * 0b1..Trigger 2 event generated. - */ -#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) - -#define ADC_SWTRIG_SWT3_MASK (0x8U) -#define ADC_SWTRIG_SWT3_SHIFT (3U) -/*! SWT3 - Software trigger 3 event - * 0b0..No trigger 3 event generated. - * 0b1..Trigger 3 event generated. - */ -#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) - -#define ADC_SWTRIG_SWT4_MASK (0x10U) -#define ADC_SWTRIG_SWT4_SHIFT (4U) -/*! SWT4 - Software trigger 4 event - * 0b0..No trigger 4 event generated. - * 0b1..Trigger 4 event generated. - */ -#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) - -#define ADC_SWTRIG_SWT5_MASK (0x20U) -#define ADC_SWTRIG_SWT5_SHIFT (5U) -/*! SWT5 - Software trigger 5 event - * 0b0..No trigger 5 event generated. - * 0b1..Trigger 5 event generated. - */ -#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) - -#define ADC_SWTRIG_SWT6_MASK (0x40U) -#define ADC_SWTRIG_SWT6_SHIFT (6U) -/*! SWT6 - Software trigger 6 event - * 0b0..No trigger 6 event generated. - * 0b1..Trigger 6 event generated. - */ -#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) - -#define ADC_SWTRIG_SWT7_MASK (0x80U) -#define ADC_SWTRIG_SWT7_SHIFT (7U) -/*! SWT7 - Software trigger 7 event - * 0b0..No trigger 7 event generated. - * 0b1..Trigger 7 event generated. - */ -#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) - -#define ADC_SWTRIG_SWT8_MASK (0x100U) -#define ADC_SWTRIG_SWT8_SHIFT (8U) -/*! SWT8 - Software trigger 8 event - * 0b0..No trigger 8 event generated. - * 0b1..Trigger 8 event generated. - */ -#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK) - -#define ADC_SWTRIG_SWT9_MASK (0x200U) -#define ADC_SWTRIG_SWT9_SHIFT (9U) -/*! SWT9 - Software trigger 9 event - * 0b0..No trigger 9 event generated. - * 0b1..Trigger 9 event generated. - */ -#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK) - -#define ADC_SWTRIG_SWT10_MASK (0x400U) -#define ADC_SWTRIG_SWT10_SHIFT (10U) -/*! SWT10 - Software trigger 10 event - * 0b0..No trigger 10 event generated. - * 0b1..Trigger 10 event generated. - */ -#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK) - -#define ADC_SWTRIG_SWT11_MASK (0x800U) -#define ADC_SWTRIG_SWT11_SHIFT (11U) -/*! SWT11 - Software trigger 11 event - * 0b0..No trigger 11 event generated. - * 0b1..Trigger 11 event generated. - */ -#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK) - -#define ADC_SWTRIG_SWT12_MASK (0x1000U) -#define ADC_SWTRIG_SWT12_SHIFT (12U) -/*! SWT12 - Software trigger 12 event - * 0b0..No trigger 12 event generated. - * 0b1..Trigger 12 event generated. - */ -#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK) - -#define ADC_SWTRIG_SWT13_MASK (0x2000U) -#define ADC_SWTRIG_SWT13_SHIFT (13U) -/*! SWT13 - Software trigger 13 event - * 0b0..No trigger 13 event generated. - * 0b1..Trigger 13 event generated. - */ -#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK) - -#define ADC_SWTRIG_SWT14_MASK (0x4000U) -#define ADC_SWTRIG_SWT14_SHIFT (14U) -/*! SWT14 - Software trigger 14 event - * 0b0..No trigger 14 event generated. - * 0b1..Trigger 14 event generated. - */ -#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK) - -#define ADC_SWTRIG_SWT15_MASK (0x8000U) -#define ADC_SWTRIG_SWT15_SHIFT (15U) -/*! SWT15 - Software trigger 15 event - * 0b0..No trigger 15 event generated. - * 0b1..Trigger 15 event generated. - */ -#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK) -/*! @} */ - -/*! @name TSTAT - Trigger Status Register */ -/*! @{ */ - -#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU) -#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) -/*! TEXC_NUM - Trigger Exception Number - * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. - * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception. - * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception. - * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception. - * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception. - */ -#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) - -#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U) -#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) -/*! TCOMP_FLAG - Trigger Completion Flag - * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled. - * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts. - * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts. - * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts. - * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. - */ -#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) -/*! @} */ - -/*! @name OFSTRIM - ADC Offset Trim Register */ -/*! @{ */ - -#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) -#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) -/*! OFSTRIM_A - Trim for offset - */ -#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) - -#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) -#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) -/*! OFSTRIM_B - Trim for offset - */ -#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) -/*! @} */ - -/*! @name TCTRL - Trigger Control Register */ -/*! @{ */ - -#define ADC_TCTRL_HTEN_MASK (0x1U) -#define ADC_TCTRL_HTEN_SHIFT (0U) -/*! HTEN - Trigger enable - * 0b0..Hardware trigger source disabled - * 0b1..Hardware trigger source enabled - */ -#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) - -#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) -#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) -/*! FIFO_SEL_A - SAR Result Destination For Channel A - * 0b0..Result written to FIFO 0 - * 0b1..Result written to FIFO 1 - */ -#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) - -#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) -#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) -/*! FIFO_SEL_B - SAR Result Destination For Channel B - * 0b0..Result written to FIFO 0 - * 0b1..Result written to FIFO 1 - */ -#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) - -#define ADC_TCTRL_TPRI_MASK (0xF00U) -#define ADC_TCTRL_TPRI_SHIFT (8U) -/*! TPRI - Trigger priority setting - * 0b0000..Set to highest priority, Level 1 - * 0b0001-0b1110..Set to corresponding priority level - * 0b1111..Set to lowest priority, Level 16 - */ -#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) - -#define ADC_TCTRL_RSYNC_MASK (0x8000U) -#define ADC_TCTRL_RSYNC_SHIFT (15U) -/*! RSYNC - Trigger Resync - */ -#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) - -#define ADC_TCTRL_TDLY_MASK (0xF0000U) -#define ADC_TCTRL_TDLY_SHIFT (16U) -/*! TDLY - Trigger delay select - */ -#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) - -#define ADC_TCTRL_TCMD_MASK (0xF000000U) -#define ADC_TCTRL_TCMD_SHIFT (24U) -/*! TCMD - Trigger command select - * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. - * 0b0001..CMD1 is executed - * 0b0010-0b1110..Corresponding CMD is executed - * 0b1111..CMD15 is executed - */ -#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) -/*! @} */ - -/* The count of ADC_TCTRL */ -#define ADC_TCTRL_COUNT (16U) - -/*! @name FCTRL - FIFO Control Register */ -/*! @{ */ - -#define ADC_FCTRL_FCOUNT_MASK (0x1FU) -#define ADC_FCTRL_FCOUNT_SHIFT (0U) -/*! FCOUNT - Result FIFO counter - */ -#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) - -#define ADC_FCTRL_FWMARK_MASK (0xF0000U) -#define ADC_FCTRL_FWMARK_SHIFT (16U) -/*! FWMARK - Watermark level selection - */ -#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) -/*! @} */ - -/* The count of ADC_FCTRL */ -#define ADC_FCTRL_COUNT (2U) - -/*! @name GCC - Gain Calibration Control */ -/*! @{ */ - -#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) -#define ADC_GCC_GAIN_CAL_SHIFT (0U) -/*! GAIN_CAL - Gain Calibration Value - */ -#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) - -#define ADC_GCC_RDY_MASK (0x1000000U) -#define ADC_GCC_RDY_SHIFT (24U) -/*! RDY - Gain Calibration Value Valid - * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. - * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. - */ -#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) -/*! @} */ - -/* The count of ADC_GCC */ -#define ADC_GCC_COUNT (2U) - -/*! @name GCR - Gain Calculation Result */ -/*! @{ */ - -#define ADC_GCR_GCALR_MASK (0xFFFFU) -#define ADC_GCR_GCALR_SHIFT (0U) -/*! GCALR - Gain Calculation Result - */ -#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) - -#define ADC_GCR_RDY_MASK (0x1000000U) -#define ADC_GCR_RDY_SHIFT (24U) -/*! RDY - Gain Calculation Ready - * 0b0..The gain offset calculation value is invalid. - * 0b1..The gain calibration value is valid. - */ -#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) -/*! @} */ - -/* The count of ADC_GCR */ -#define ADC_GCR_COUNT (2U) - -/*! @name CMDL - ADC Command Low Buffer Register */ -/*! @{ */ - -#define ADC_CMDL_ADCH_MASK (0x1FU) -#define ADC_CMDL_ADCH_SHIFT (0U) -/*! ADCH - Input channel select - * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. - * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. - * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. - * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. - * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. - * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. - */ -#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) - -#define ADC_CMDL_CTYPE_MASK (0x60U) -#define ADC_CMDL_CTYPE_SHIFT (5U) -/*! CTYPE - Conversion Type - * 0b00..Single-Ended Mode. Only A side channel is converted. - * 0b01..Single-Ended Mode. Only B side channel is converted. - * 0b10..Differential Mode. A-B. - * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - */ -#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) - -#define ADC_CMDL_MODE_MASK (0x80U) -#define ADC_CMDL_MODE_SHIFT (7U) -/*! MODE - Select resolution of conversions - * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - */ -#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) -/*! @} */ - -/* The count of ADC_CMDL */ -#define ADC_CMDL_COUNT (15U) - -/*! @name CMDH - ADC Command High Buffer Register */ -/*! @{ */ - -#define ADC_CMDH_CMPEN_MASK (0x3U) -#define ADC_CMDH_CMPEN_SHIFT (0U) -/*! CMPEN - Compare Function Enable - * 0b00..Compare disabled. - * 0b01..Reserved - * 0b10..Compare enabled. Store on true. - * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - */ -#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) - -#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) -#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) -/*! WAIT_TRIG - Wait for trigger assertion before execution. - * 0b0..This command will be automatically executed. - * 0b1..The active trigger must be asserted again before executing this command. - */ -#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) - -#define ADC_CMDH_LWI_MASK (0x80U) -#define ADC_CMDH_LWI_SHIFT (7U) -/*! LWI - Loop with Increment - * 0b0..Auto channel increment disabled - * 0b1..Auto channel increment enabled - */ -#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) - -#define ADC_CMDH_STS_MASK (0x700U) -#define ADC_CMDH_STS_SHIFT (8U) -/*! STS - Sample Time Select - * 0b000..Minimum sample time of 3 ADCK cycles. - * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - */ -#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) - -#define ADC_CMDH_AVGS_MASK (0x7000U) -#define ADC_CMDH_AVGS_SHIFT (12U) -/*! AVGS - Hardware Average Select - * 0b000..Single conversion. - * 0b001..2 conversions averaged. - * 0b010..4 conversions averaged. - * 0b011..8 conversions averaged. - * 0b100..16 conversions averaged. - * 0b101..32 conversions averaged. - * 0b110..64 conversions averaged. - * 0b111..128 conversions averaged. - */ -#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) - -#define ADC_CMDH_LOOP_MASK (0xF0000U) -#define ADC_CMDH_LOOP_SHIFT (16U) -/*! LOOP - Loop Count Select - * 0b0000..Looping not enabled. Command executes 1 time. - * 0b0001..Loop 1 time. Command executes 2 times. - * 0b0010..Loop 2 times. Command executes 3 times. - * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. - * 0b1111..Loop 15 times. Command executes 16 times. - */ -#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) - -#define ADC_CMDH_NEXT_MASK (0xF000000U) -#define ADC_CMDH_NEXT_SHIFT (24U) -/*! NEXT - Next Command Select - * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority - * trigger pending, begin command associated with lower priority trigger. - * 0b0001..Select CMD1 command buffer register as next command. - * 0b0010-0b1110..Select corresponding CMD command buffer register as next command - * 0b1111..Select CMD15 command buffer register as next command. - */ -#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) -/*! @} */ - -/* The count of ADC_CMDH */ -#define ADC_CMDH_COUNT (15U) - -/*! @name CV - Compare Value Register */ -/*! @{ */ - -#define ADC_CV_CVL_MASK (0xFFFFU) -#define ADC_CV_CVL_SHIFT (0U) -/*! CVL - Compare Value Low. - */ -#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) - -#define ADC_CV_CVH_MASK (0xFFFF0000U) -#define ADC_CV_CVH_SHIFT (16U) -/*! CVH - Compare Value High. - */ -#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) -/*! @} */ - -/* The count of ADC_CV */ -#define ADC_CV_COUNT (4U) - -/*! @name RESFIFO - ADC Data Result FIFO Register */ -/*! @{ */ - -#define ADC_RESFIFO_D_MASK (0xFFFFU) -#define ADC_RESFIFO_D_SHIFT (0U) -/*! D - Data result - */ -#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) - -#define ADC_RESFIFO_TSRC_MASK (0xF0000U) -#define ADC_RESFIFO_TSRC_SHIFT (16U) -/*! TSRC - Trigger Source - * 0b0000..Trigger source 0 initiated this conversion. - * 0b0001..Trigger source 1 initiated this conversion. - * 0b0010-0b1110..Corresponding trigger source initiated this conversion. - * 0b1111..Trigger source 15 initiated this conversion. - */ -#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) - -#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) -#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) -/*! LOOPCNT - Loop count value - * 0b0000..Result is from initial conversion in command. - * 0b0001..Result is from second conversion in command. - * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. - * 0b1111..Result is from 16th conversion in command. - */ -#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) - -#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) -#define ADC_RESFIFO_CMDSRC_SHIFT (24U) -/*! CMDSRC - Command Buffer Source - * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state - * prior to an ADC conversion result dataword being stored to a RESFIFO buffer. - * 0b0001..CMD1 buffer used as control settings for this conversion. - * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. - * 0b1111..CMD15 buffer used as control settings for this conversion. - */ -#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) - -#define ADC_RESFIFO_VALID_MASK (0x80000000U) -#define ADC_RESFIFO_VALID_SHIFT (31U) -/*! VALID - FIFO entry is valid - * 0b0..FIFO is empty. Discard any read from RESFIFO. - * 0b1..FIFO record read from RESFIFO is valid. - */ -#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) -/*! @} */ - -/* The count of ADC_RESFIFO */ -#define ADC_RESFIFO_COUNT (2U) - -/*! @name CAL_GAR - Calibration General A-Side Registers */ -/*! @{ */ - -#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) -#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) -/*! CAL_GAR_VAL - Calibration General A Side Register Element - */ -#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) -/*! @} */ - -/* The count of ADC_CAL_GAR */ -#define ADC_CAL_GAR_COUNT (33U) - -/*! @name CAL_GBR - Calibration General B-Side Registers */ -/*! @{ */ - -#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) -#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) -/*! CAL_GBR_VAL - Calibration General B Side Register Element - */ -#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) -/*! @} */ - -/* The count of ADC_CAL_GBR */ -#define ADC_CAL_GBR_COUNT (33U) - - -/*! - * @} - */ /* end of group ADC_Register_Masks */ - - -/* ADC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral ADC0 base address */ - #define ADC0_BASE (0x500A0000u) - /** Peripheral ADC0 base address */ - #define ADC0_BASE_NS (0x400A0000u) - /** Peripheral ADC0 base pointer */ - #define ADC0 ((ADC_Type *)ADC0_BASE) - /** Peripheral ADC0 base pointer */ - #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS { ADC0_BASE } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS { ADC0 } - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS_NS { ADC0_NS } -#else - /** Peripheral ADC0 base address */ - #define ADC0_BASE (0x400A0000u) - /** Peripheral ADC0 base pointer */ - #define ADC0 ((ADC_Type *)ADC0_BASE) - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS { ADC0_BASE } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS { ADC0 } -#endif -/** Interrupt vectors for the ADC peripheral type */ -#define ADC_IRQS { ADC0_IRQn } - -/*! - * @} - */ /* end of group ADC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- AHB_SECURE_CTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer - * @{ - */ - -/** AHB_SECURE_CTRL - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x30 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */ - uint8_t RESERVED_0[12]; - __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[1]; /**< Security access rules for FLASH sector 0 to sector 7. Each Flash sector is 32 Kbytes. There are 8 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */ - uint8_t RESERVED_1[12]; - __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */ - } SEC_CTRL_FLASH_ROM[1]; - struct { /* offset: 0x30, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAMX slaves., array offset: 0x40, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_RAMX[1]; - uint8_t RESERVED_0[12]; - struct { /* offset: 0x50, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM0 slaves., array offset: 0x60, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_RAM0[1]; - uint8_t RESERVED_1[12]; - struct { /* offset: 0x70, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM1 slaves., array offset: 0x80, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_RAM1[1]; - uint8_t RESERVED_2[12]; - struct { /* offset: 0x90, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_RAM2[1]; - uint8_t RESERVED_3[12]; - struct { /* offset: 0xB0, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM3 slaves., array offset: 0xB0, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM3., array offset: 0xC0, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_RAM3[1]; - uint8_t RESERVED_4[12]; - struct { /* offset: 0xD0, array step: 0x30 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for both APB Bridges slaves., array offset: 0xD0, array step: 0x30 */ - uint8_t RESERVED_0[12]; - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0xE0, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0xE4, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0xE8, array step: 0x30 */ - uint8_t RESERVED_1[4]; - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xF0, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xF4, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xF8, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xFC, array step: 0x30 */ - } SEC_CTRL_APB_BRIDGE[1]; - __IO uint32_t SEC_CTRL_AHB_PORT7_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x100 */ - __IO uint32_t SEC_CTRL_AHB_PORT7_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x104 */ - uint8_t RESERVED_5[8]; - __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x110 */ - __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x114 */ - uint8_t RESERVED_6[8]; - struct { /* offset: 0x120, array step: 0x14 */ - __IO uint32_t SLAVE0_RULE; /**< Security access rules for AHB peripherals., array offset: 0x120, array step: 0x14 */ - __IO uint32_t SLAVE1_RULE; /**< Security access rules for AHB peripherals., array offset: 0x124, array step: 0x14 */ - uint8_t RESERVED_0[8]; - __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x130, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_AHB_PORT9[1]; - uint8_t RESERVED_7[3276]; - __I uint32_t SEC_VIO_ADDR[10]; /**< most recent security violation address for AHB layer n, array offset: 0xE00, array step: 0x4 */ - uint8_t RESERVED_8[88]; - __I uint32_t SEC_VIO_MISC_INFO[10]; /**< most recent security violation miscellaneous information for AHB layer n, array offset: 0xE80, array step: 0x4 */ - uint8_t RESERVED_9[88]; - __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */ - uint8_t RESERVED_10[124]; - __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */ - __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */ - uint8_t RESERVED_11[52]; - __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */ - uint8_t RESERVED_12[16]; - __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */ - __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */ - uint8_t RESERVED_13[20]; - __IO uint32_t CPU0_LOCK_REG; /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */ - uint8_t RESERVED_14[8]; - __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */ - __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */ -} AHB_SECURE_CTRL_Type; - -/* ---------------------------------------------------------------------------- - -- AHB_SECURE_CTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks - * @{ - */ - -/*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U) -/*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0003_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U) -/*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 7. Each Flash sector is 32 Kbytes. There are 8 FLASH sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U) - -/*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U) -/*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAMX_MEM_RULE - Security access rules for RAMX slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U) -/*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_7FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM0_MEM_RULE - Security access rules for RAM0 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT (0U) -/*! RAM1_RULE - Security access rules for the whole RAM1 : 0x2000_8000 - 0x2000_BFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM1_MEM_RULE - Security access rules for RAM1 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U) -/*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2000_C000 - 0x2000_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM2_MEM_RULE - Security access rules for RAM2 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT (0U) -/*! RAM3_RULE - Security access rules for the whole RAM3 : 0x2001_0000 - 0x2001_3FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM3_MEM_RULE - Security access rules for RAM3. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U) -/*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U) -/*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U) -/*! SYSCON_RULE - System Configuration - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U) -/*! IOCON_RULE - I/O Configuration - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U) -/*! GINT0_RULE - GPIO input Interrupt 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U) -/*! GINT1_RULE - GPIO input Interrupt 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U) -/*! PINT_RULE - Pin Interrupt and Pattern match - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U) -/*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT (24U) -/*! INPUTMUX_RULE - Peripheral input multiplexing - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U) -/*! CTIMER0_RULE - Standard counter/Timer 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U) -/*! CTIMER1_RULE - Standard counter/Timer 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U) -/*! WWDT_RULE - Windiwed wtachdog Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U) -/*! MRT_RULE - Multi-rate Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U) -/*! UTICK_RULE - Micro-Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U) -/*! ANACTRL_RULE - Analog Modules controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U) -/*! PMC_RULE - Power Management Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U) -/*! SYSCTRL_RULE - System Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_SHIFT (16U) -/*! SPI_FILTER_RULE - SPI FILTER control - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U) -/*! CTIMER2_RULE - Standard counter/Timer 2 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U) -/*! CTIMER3_RULE - Standard counter/Timer 3 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U) -/*! CTIMER4_RULE - Standard counter/Timer 4 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U) -/*! RTC_RULE - Real Time Counter - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U) -/*! OSEVENT_RULE - OS Event Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U) -/*! FLASH_CTRL_RULE - Flash Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U) -/*! PRINCE_RULE - Prince - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U) -/*! RNG_RULE - True Random Number Generator - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT (12U) -/*! PUF_RULE - PUF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U) -/*! PLU_RULE - Programmable Look-Up logic - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U) - -/*! @name SEC_CTRL_AHB_PORT7_SLAVE0_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_SHIFT (8U) -/*! DMA0_RULE - DMA Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_SHIFT (20U) -/*! SCT_RULE - SCTimer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT (24U) -/*! FLEXCOMM0_RULE - Flexcomm interface 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT (28U) -/*! FLEXCOMM1_RULE - Flexcomm interface 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB_PORT7_SLAVE1_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT (0U) -/*! FLEXCOMM2_RULE - Flexcomm interface 2 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT (4U) -/*! FLEXCOMM3_RULE - Flexcomm interface 3 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT (8U) -/*! FLEXCOMM4_RULE - Flexcomm interface 4 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_SHIFT (16U) -/*! GPIO0_RULE - High Speed GPIO - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_SHIFT (20U) -/*! CRC_RULE - CRC engine - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT (24U) -/*! FLEXCOMM5_RULE - Flexcomm interface 5 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT (28U) -/*! FLEXCOMM6_RULE - Flexcomm interface 6 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT (0U) -/*! FLEXCOMM7_RULE - Flexcomm interface 7 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT (16U) -/*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_SHIFT (20U) -/*! CAN0_RULE - CAN-FD - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_SHIFT (28U) -/*! HS_LSPI_RULE - High Speed SPI - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_SHIFT (0U) -/*! ADC_RULE - ADC - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_SHIFT (16U) -/*! HASH_RULE - SHA-2 crypto registers - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_SHIFT (20U) -/*! CASPER_RULE - RSA/ECC crypto accelerator - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_SHIFT (28U) -/*! DMA1_RULE - DMA Controller (Secure) - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_COUNT (1U) - -/*! @name SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_SHIFT (0U) -/*! GPIO1_RULE - Secure High Speed GPIO - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U) -/*! AHB_SEC_CTRL_RULE - AHB Secure Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_COUNT (1U) - -/*! @name SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U) -/*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U) -/*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U) -/*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U) -/*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_VIO_ADDR - most recent security violation address for AHB layer n */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) -/*! SEC_VIO_ADDR - security violation address for AHB layer - */ -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */ -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (10U) - -/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB layer n */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) -/*! SEC_VIO_INFO_WRITE - security violation access read/write indicator. - * 0b0..Read access. - * 0b1..Write access. - */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) -/*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator. - * 0b0..Code access. - * 0b1..Data access. - */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) -/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level - */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) -/*! SEC_VIO_INFO_MASTER - security violation master number - * 0b0000..CPU0 Code. - * 0b0001..CPU0 System. - * 0b0101..SDMA0. - * 0b1010..HASH. - * 0b1100..SDMA1. - * 0b1101..CAN-FD. - */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (10U) - -/*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) -/*! VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) -/*! VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) -/*! VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) -/*! VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) -/*! VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) -/*! VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) -/*! VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) -/*! VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) -/*! VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) -/*! VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) -/*! @} */ - -/*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U) -/*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U) -/*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U) -/*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U) -/*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U) -/*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U) -/*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U) -/*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U) -/*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U) -/*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U) -/*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U) -/*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U) -/*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U) -/*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U) -/*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U) -/*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U) -/*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U) -/*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U) -/*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U) -/*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U) -/*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U) -/*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U) -/*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U) -/*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U) -/*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U) -/*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U) -/*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U) -/*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U) -/*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U) -/*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U) -/*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U) -/*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U) -/*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK) -/*! @} */ - -/*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U) -/*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U) -/*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U) -/*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U) -/*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U) -/*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U) -/*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U) -/*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U) -/*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U) -/*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U) -/*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U) -/*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U) -/*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U) -/*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U) -/*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U) -/*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U) -/*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U) -/*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U) -/*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U) -/*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U) -/*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U) -/*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U) -/*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U) -/*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U) -/*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U) -/*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U) -/*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U) -/*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U) -/*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U) -/*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U) -/*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U) -/*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U) -/*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK) -/*! @} */ - -/*! @name SEC_MASK_LOCK - Security General Purpose register access control. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) -/*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK) - -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) -/*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK) -/*! @} */ - -/*! @name MASTER_SEC_LEVEL - master secure level register */ -/*! @{ */ - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U) -/*! SDMA0 - System DMA 0. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U) -/*! HASH - Hash. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U) -/*! SDMA1 - System DMA 1 security level. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_MASK (0xC000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_SHIFT (26U) -/*! CANFD - CAN FD. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) -/*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) -/*! @} */ - -/*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */ -/*! @{ */ - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U) -/*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U) -/*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U) -/*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_MASK (0xC000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_SHIFT (26U) -/*! CANFD - CAN FD. Must be equal to NOT(MASTER_SEC_LEVEL.CANFD) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) -/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) -/*! @} */ - -/*! @name CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) */ -/*! @{ */ - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) -/*! LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) -/*! LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) -/*! LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U) -/*! LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U) -/*! LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT (30U) -/*! CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK) -/*! @} */ - -/*! @name MISC_CTRL_DP_REG - secure control duplicate register */ -/*! @{ */ - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) -/*! WRITE_LOCK - Write lock. - * 0b10..Secure control registers can be written. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) -/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. - * 0b10..Disable check. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) -/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. - * 0b10..Disable check. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) -/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. - * 0b10..Disable check. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) -/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. - * 0b10..Enable abort fort secure checker. - * 0b01..Disable abort fort secure checker. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) -/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. - * 0b10..Simple master in strict mode. - * 0b01..Simple master in tier mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) -/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. - * 0b10..Smart master in strict mode. - * 0b01..Smart master in tier mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) -/*! IDAU_ALL_NS - Disable IDAU. - * 0b10..IDAU is enabled. - * 0b01..IDAU is disable. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) -/*! @} */ - -/*! @name MISC_CTRL_REG - secure control register */ -/*! @{ */ - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) -/*! WRITE_LOCK - Write lock. - * 0b10..Secure control registers can be written. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) -/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. - * 0b10..Disable check. - * 0b01..Enabled (restricted mode) - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) -/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. - * 0b10..Disable check. - * 0b01..Enabled (restricted mode) - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) -/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. - * 0b10..Disable check. - * 0b01..Enabled (restricted mode) - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) -/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. - * 0b10..Enable abort fort secure checker. - * 0b01..Disable abort fort secure checker. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) -/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. - * 0b10..Simple master in strict mode. - * 0b01..Simple master in tier mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) -/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. - * 0b10..Smart master in strict mode. - * 0b01..Smart master in tier mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) -/*! IDAU_ALL_NS - Disable IDAU. - * 0b10..IDAU is enabled. - * 0b01..IDAU is disable. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group AHB_SECURE_CTRL_Register_Masks */ - - -/* AHB_SECURE_CTRL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral AHB_SECURE_CTRL base address */ - #define AHB_SECURE_CTRL_BASE (0x500AC000u) - /** Peripheral AHB_SECURE_CTRL base address */ - #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u) - /** Peripheral AHB_SECURE_CTRL base pointer */ - #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) - /** Peripheral AHB_SECURE_CTRL base pointer */ - #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS) - /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ - #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } - /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ - #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } - /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ - #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS } - /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ - #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS } -#else - /** Peripheral AHB_SECURE_CTRL base address */ - #define AHB_SECURE_CTRL_BASE (0x400AC000u) - /** Peripheral AHB_SECURE_CTRL base pointer */ - #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) - /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ - #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } - /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ - #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } -#endif - -/*! - * @} - */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ANACTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer - * @{ - */ - -/** ANACTRL - Register Layout Typedef */ -typedef struct { - __IO uint32_t ANALOG_CTRL_CFG; /**< Various Analog blocks configuration (like FRO 192MHz trimmings source ...), offset: 0x0 */ - __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */ - __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */ - __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */ - __IO uint32_t ADC_CTRL; /**< ADC control static configuration., offset: 0x18 */ - uint8_t RESERVED_1[4]; - __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */ - __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status register, offset: 0x24 */ - uint8_t RESERVED_2[8]; - __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */ - __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */ - uint8_t RESERVED_3[8]; - __IO uint32_t RINGO0_CTRL; /**< First Ring Oscillator module control register., offset: 0x40 */ - __IO uint32_t RINGO1_CTRL; /**< Second Ring Oscillator module control register., offset: 0x44 */ - __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */ - uint8_t RESERVED_4[100]; - __IO uint32_t LDO_XO32M; /**< High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register, offset: 0xB0 */ - __IO uint32_t AUX_BIAS; /**< AUX_BIAS, offset: 0xB4 */ - uint8_t RESERVED_5[64]; - __IO uint32_t DUMMY_CTRL; /**< Dummy Control bus to analog modules, offset: 0xF8 */ -} ANACTRL_Type; - -/* ---------------------------------------------------------------------------- - -- ANACTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks - * @{ - */ - -/*! @name ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) */ -/*! @{ */ - -#define ANACTRL_ANALOG_CTRL_CFG_CONFIG_MASK (0xFFFFFFFFU) -#define ANACTRL_ANALOG_CTRL_CFG_CONFIG_SHIFT (0U) -/*! CONFIG - Analog blocks configuration. - */ -#define ANACTRL_ANALOG_CTRL_CFG_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_CFG_CONFIG_SHIFT)) & ANACTRL_ANALOG_CTRL_CFG_CONFIG_MASK) -/*! @} */ - -/*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */ -/*! @{ */ - -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U) -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U) -/*! FLASH_PWRDWN - Flash Power Down status. - * 0b0..Flash is not in power down mode. - * 0b1..Flash is in power down mode. - */ -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK) - -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U) -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U) -/*! FLASH_INIT_ERROR - Flash initialization error status. - * 0b0..No error. - * 0b1..At least one error occured during flash initialization.. - */ -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK) -/*! @} */ - -/*! @name FREQ_ME_CTRL - Frequency Measure function control register */ -/*! @{ */ - -#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU) -#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U) -/*! CAPVAL_SCALE - Frequency measure result /Frequency measur scale - */ -#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK) - -#define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U) -#define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U) -/*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit - * when the measurement cycle has completed and there is valid capture data in the CAPVAL field - * (bits 30:0). - */ -#define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK) -/*! @} */ - -/*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */ -/*! @{ */ - -#define ANACTRL_FRO192M_CTRL_BIAS_TRIM_MASK (0x3FU) -#define ANACTRL_FRO192M_CTRL_BIAS_TRIM_SHIFT (0U) -/*! BIAS_TRIM - Bias trimming bits (course frequency trimming). - */ -#define ANACTRL_FRO192M_CTRL_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_BIAS_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_BIAS_TRIM_MASK) - -#define ANACTRL_FRO192M_CTRL_TEMP_TRIM_MASK (0x3F80U) -#define ANACTRL_FRO192M_CTRL_TEMP_TRIM_SHIFT (7U) -/*! TEMP_TRIM - Temperature coefficient trimming bits. - */ -#define ANACTRL_FRO192M_CTRL_TEMP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_TEMP_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_TEMP_TRIM_MASK) - -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U) -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U) -/*! ENA_12MHZCLK - 12 MHz clock control. - * 0b0..12 MHz clock is disabled. - * 0b1..12 MHz clock is enabled. - */ -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) - -#define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U) -#define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U) -/*! DAC_TRIM - Frequency trim. - */ -#define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK) - -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U) -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U) -/*! ENA_96MHZCLK - 96 MHz clock control. - * 0b0..96 MHz clock is disabled. - * 0b1..96 MHz clock is enabled. - */ -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) - -#define ANACTRL_FRO192M_CTRL_WRTRIM_MASK (0x80000000U) -#define ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT (31U) -/*! WRTRIM - This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields. - */ -#define ANACTRL_FRO192M_CTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_WRTRIM_MASK) -/*! @} */ - -/*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */ -/*! @{ */ - -#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U) -#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U) -/*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. - * 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). - * 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by - * FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). - */ -#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK) - -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U) -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U) -/*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses - * the threshold voltage of a SLVT transistor, this output signal will go high. It is also - * possible to observe the clk_valid signal. - */ -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK) -/*! @} */ - -/*! @name ADC_CTRL - ADC control static configuration. */ -/*! @{ */ - -#define ANACTRL_ADC_CTRL_CONFIG_MASK (0xFFFFFFFFU) -#define ANACTRL_ADC_CTRL_CONFIG_SHIFT (0U) -/*! CONFIG - ADC control static configuration. - */ -#define ANACTRL_ADC_CTRL_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ADC_CTRL_CONFIG_SHIFT)) & ANACTRL_ADC_CTRL_CONFIG_MASK) -/*! @} */ - -/*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */ -/*! @{ */ - -#define ANACTRL_XO32M_CTRL_GM_MASK (0xEU) -#define ANACTRL_XO32M_CTRL_GM_SHIFT (1U) -/*! GM - Gm value for Xo. - */ -#define ANACTRL_XO32M_CTRL_GM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_GM_SHIFT)) & ANACTRL_XO32M_CTRL_GM_MASK) - -#define ANACTRL_XO32M_CTRL_SLAVE_MASK (0x10U) -#define ANACTRL_XO32M_CTRL_SLAVE_SHIFT (4U) -/*! SLAVE - Xo in slave mode. - */ -#define ANACTRL_XO32M_CTRL_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_SLAVE_SHIFT)) & ANACTRL_XO32M_CTRL_SLAVE_MASK) - -#define ANACTRL_XO32M_CTRL_AMP_MASK (0xE0U) -#define ANACTRL_XO32M_CTRL_AMP_SHIFT (5U) -/*! AMP - Amplitude selection , Min amp : 001, Max amp : 110. - */ -#define ANACTRL_XO32M_CTRL_AMP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_AMP_SHIFT)) & ANACTRL_XO32M_CTRL_AMP_MASK) - -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK (0x7F00U) -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT (8U) -/*! OSC_CAP_IN - Tune capa banks of High speed Crystal Oscillator input pin - */ -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK) - -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK (0x3F8000U) -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT (15U) -/*! OSC_CAP_OUT - Tune capa banks of High speed Crystal Oscillator output pin - */ -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK) - -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U) -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U) -/*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. - * 0b0..XO AC buffer bypass is disabled. - * 0b1..XO AC buffer bypass is enabled. - */ -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK) - -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U) -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U) -/*! ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system. - * 0b0..High speed Crystal oscillator output to CPU system is disabled. - * 0b1..High speed Crystal oscillator output to CPU system is enabled. - */ -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) -/*! @} */ - -/*! @name XO32M_STATUS - High speed Crystal Oscillator Status register */ -/*! @{ */ - -#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U) -#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U) -/*! XO_READY - Indicates XO out frequency statibilty. - * 0b0..XO output frequency is not yet stable. - * 0b1..XO output frequency is stable. - */ -#define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK) -/*! @} */ - -/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */ -/*! @{ */ - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U) -/*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control. - * 0b0..BOD VBAT interrupt is disabled. - * 0b1..BOD VBAT interrupt is enabled. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U) -/*! BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U) -/*! BODCORE_INT_ENABLE - BOD CORE interrupt control. - * 0b0..BOD CORE interrupt is disabled. - * 0b1..BOD CORE interrupt is enabled. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U) -/*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U) -/*! DCDC_INT_ENABLE - DCDC interrupt control. - * 0b0..DCDC interrupt is disabled. - * 0b1..DCDC interrupt is enabled. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U) -/*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK) -/*! @} */ - -/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */ -/*! @{ */ - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U) -/*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U) -/*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U) -/*! BODVBAT_VAL - Current value of BOD VBAT power status output. - * 0b0..VBAT voltage level is below the threshold. - * 0b1..VBAT voltage level is above the threshold. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U) -/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U) -/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U) -/*! BODCORE_VAL - Current value of BOD CORE power status output. - * 0b0..CORE voltage level is below the threshold. - * 0b1..CORE voltage level is above the threshold. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U) -/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U) -/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U) -/*! DCDC_VAL - Current value of DCDC power status output. - * 0b0..DCDC output Voltage is below the targeted regulation level. - * 0b1..DCDC output Voltage is above the targeted regulation level. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK) -/*! @} */ - -/*! @name RINGO0_CTRL - First Ring Oscillator module control register. */ -/*! @{ */ - -#define ANACTRL_RINGO0_CTRL_CONFIG_MASK (0xFFFFFFFFU) -#define ANACTRL_RINGO0_CTRL_CONFIG_SHIFT (0U) -/*! CONFIG - First ring oscillator configuration. - */ -#define ANACTRL_RINGO0_CTRL_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_CONFIG_SHIFT)) & ANACTRL_RINGO0_CTRL_CONFIG_MASK) -/*! @} */ - -/*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */ -/*! @{ */ - -#define ANACTRL_RINGO1_CTRL_CONFIG_MASK (0xFFFFFFFFU) -#define ANACTRL_RINGO1_CTRL_CONFIG_SHIFT (0U) -/*! CONFIG - Second ring oscillator configuration. - */ -#define ANACTRL_RINGO1_CTRL_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_CONFIG_SHIFT)) & ANACTRL_RINGO1_CTRL_CONFIG_MASK) -/*! @} */ - -/*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */ -/*! @{ */ - -#define ANACTRL_RINGO2_CTRL_CONFIG_MASK (0xFFFFFFFFU) -#define ANACTRL_RINGO2_CTRL_CONFIG_SHIFT (0U) -/*! CONFIG - Third ring oscillator configuration. - */ -#define ANACTRL_RINGO2_CTRL_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_CONFIG_SHIFT)) & ANACTRL_RINGO2_CTRL_CONFIG_MASK) -/*! @} */ - -/*! @name LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register */ -/*! @{ */ - -#define ANACTRL_LDO_XO32M_BYPASS_MASK (0x2U) -#define ANACTRL_LDO_XO32M_BYPASS_SHIFT (1U) -/*! BYPASS - Activate LDO bypass. - * 0b0..Disable bypass mode (for normal operations). - * 0b1..Activate LDO bypass. - */ -#define ANACTRL_LDO_XO32M_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_BYPASS_SHIFT)) & ANACTRL_LDO_XO32M_BYPASS_MASK) - -#define ANACTRL_LDO_XO32M_HIGHZ_MASK (0x4U) -#define ANACTRL_LDO_XO32M_HIGHZ_SHIFT (2U) -/*! HIGHZ - . - * 0b0..Output in High normal state. - * 0b1..Output in High Impedance state. - */ -#define ANACTRL_LDO_XO32M_HIGHZ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_HIGHZ_SHIFT)) & ANACTRL_LDO_XO32M_HIGHZ_MASK) - -#define ANACTRL_LDO_XO32M_VOUT_MASK (0x38U) -#define ANACTRL_LDO_XO32M_VOUT_SHIFT (3U) -/*! VOUT - Sets the LDO output level. - * 0b000..0.750 V. - * 0b001..0.775 V. - * 0b010..0.800 V. - * 0b011..0.825 V. - * 0b100..0.850 V. - * 0b101..0.875 V. - * 0b110..0.900 V. - * 0b111..0.925 V. - */ -#define ANACTRL_LDO_XO32M_VOUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_VOUT_SHIFT)) & ANACTRL_LDO_XO32M_VOUT_MASK) - -#define ANACTRL_LDO_XO32M_IBIAS_MASK (0xC0U) -#define ANACTRL_LDO_XO32M_IBIAS_SHIFT (6U) -/*! IBIAS - Adjust the biasing current. - */ -#define ANACTRL_LDO_XO32M_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_IBIAS_SHIFT)) & ANACTRL_LDO_XO32M_IBIAS_MASK) - -#define ANACTRL_LDO_XO32M_STABMODE_MASK (0x300U) -#define ANACTRL_LDO_XO32M_STABMODE_SHIFT (8U) -/*! STABMODE - Stability configuration. - */ -#define ANACTRL_LDO_XO32M_STABMODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_STABMODE_SHIFT)) & ANACTRL_LDO_XO32M_STABMODE_MASK) -/*! @} */ - -/*! @name AUX_BIAS - AUX_BIAS */ -/*! @{ */ - -#define ANACTRL_AUX_BIAS_VREF1VENABLE_MASK (0x2U) -#define ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT (1U) -/*! VREF1VENABLE - Control output of 1V reference voltage. - * 0b0..Output of 1V reference voltage buffer is bypassed. - * 0b1..Output of 1V reference voltage is enabled. - */ -#define ANACTRL_AUX_BIAS_VREF1VENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VENABLE_MASK) - -#define ANACTRL_AUX_BIAS_ITRIM_MASK (0x7CU) -#define ANACTRL_AUX_BIAS_ITRIM_SHIFT (2U) -/*! ITRIM - current trimming control word. - */ -#define ANACTRL_AUX_BIAS_ITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIM_SHIFT)) & ANACTRL_AUX_BIAS_ITRIM_MASK) - -#define ANACTRL_AUX_BIAS_PTATITRIM_MASK (0xF80U) -#define ANACTRL_AUX_BIAS_PTATITRIM_SHIFT (7U) -/*! PTATITRIM - current trimming control word for ptat current. - */ -#define ANACTRL_AUX_BIAS_PTATITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_PTATITRIM_SHIFT)) & ANACTRL_AUX_BIAS_PTATITRIM_MASK) - -#define ANACTRL_AUX_BIAS_VREF1VTRIM_MASK (0x1F000U) -#define ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT (12U) -/*! VREF1VTRIM - voltage trimming control word. - */ -#define ANACTRL_AUX_BIAS_VREF1VTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VTRIM_MASK) - -#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK (0xE0000U) -#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT (17U) -/*! VREF1VCURVETRIM - Control bit to configure trimming state of mirror. - */ -#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK) - -#define ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK (0x100000U) -#define ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT (20U) -/*! ITRIMCTRL0 - Control bit to configure trimming state of mirror. - */ -#define ANACTRL_AUX_BIAS_ITRIMCTRL0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK) - -#define ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK (0x200000U) -#define ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT (21U) -/*! ITRIMCTRL1 - Control bit to configure trimming state of mirror. - */ -#define ANACTRL_AUX_BIAS_ITRIMCTRL1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK) -/*! @} */ - -/*! @name DUMMY_CTRL - Dummy Control bus to analog modules */ -/*! @{ */ - -#define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK (0xC00U) -#define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_SHIFT (10U) -/*! XO32M_ADC_CLK_MODE - Control High speed Crystal oscillator mode of the ADC clock. - * 0b00..High speed Crystal oscillator output to ADC is disabled. - * 0b01..High speed Crystal oscillator output to ADC is enable. - */ -#define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_SHIFT)) & ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ANACTRL_Register_Masks */ - - -/* ANACTRL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE (0x50013000u) - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE_NS (0x40013000u) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS) - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS { ANACTRL } - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS } -#else - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE (0x40013000u) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS { ANACTRL } -#endif - -/*! - * @} - */ /* end of group ANACTRL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CAN Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer - * @{ - */ - -/** CAN - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[12]; - __IO uint32_t DBTP; /**< Data Bit Timing Prescaler Register, offset: 0xC */ - __IO uint32_t TEST; /**< Test Register, offset: 0x10 */ - uint8_t RESERVED_1[4]; - __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */ - __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */ - __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */ - __I uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */ - __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */ - __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */ - uint8_t RESERVED_2[16]; - __I uint32_t ECR; /**< Error Counter Register, offset: 0x40 */ - __I uint32_t PSR; /**< Protocol Status Register, offset: 0x44 */ - __IO uint32_t TDCR; /**< Transmitter Delay Compensator Register, offset: 0x48 */ - uint8_t RESERVED_3[4]; - __IO uint32_t IR; /**< Interrupt Register, offset: 0x50 */ - __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */ - __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */ - __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */ - uint8_t RESERVED_4[32]; - __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */ - __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */ - __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */ - uint8_t RESERVED_5[4]; - __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */ - __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */ - __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */ - __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */ - __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */ - __I uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */ - __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */ - __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */ - __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */ - __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */ - __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */ - __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */ - __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */ - __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */ - __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */ - __I uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */ - __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */ - __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */ - __I uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */ - __I uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */ - __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */ - __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */ - uint8_t RESERVED_6[8]; - __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */ - __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */ - __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */ - uint8_t RESERVED_7[260]; - __IO uint32_t MRBA; /**< CAN Message RAM Base Address, offset: 0x200 */ - uint8_t RESERVED_8[508]; - __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */ - uint8_t RESERVED_9[508]; - __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */ -} CAN_Type; - -/* ---------------------------------------------------------------------------- - -- CAN Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CAN_Register_Masks CAN Register Masks - * @{ - */ - -/*! @name DBTP - Data Bit Timing Prescaler Register */ -/*! @{ */ - -#define CAN_DBTP_DSJW_MASK (0xFU) -#define CAN_DBTP_DSJW_SHIFT (0U) -/*! DSJW - Data (re)synchronization jump width. - */ -#define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK) - -#define CAN_DBTP_DTSEG2_MASK (0xF0U) -#define CAN_DBTP_DTSEG2_SHIFT (4U) -/*! DTSEG2 - Data time segment after sample point. - */ -#define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK) - -#define CAN_DBTP_DTSEG1_MASK (0x1F00U) -#define CAN_DBTP_DTSEG1_SHIFT (8U) -/*! DTSEG1 - Data time segment before sample point. - */ -#define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK) - -#define CAN_DBTP_DBRP_MASK (0x1F0000U) -#define CAN_DBTP_DBRP_SHIFT (16U) -/*! DBRP - Data bit rate prescaler. - */ -#define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK) - -#define CAN_DBTP_TDC_MASK (0x800000U) -#define CAN_DBTP_TDC_SHIFT (23U) -/*! TDC - Transmitter delay compensation. - */ -#define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK) -/*! @} */ - -/*! @name TEST - Test Register */ -/*! @{ */ - -#define CAN_TEST_LBCK_MASK (0x10U) -#define CAN_TEST_LBCK_SHIFT (4U) -/*! LBCK - Loop back mode. - */ -#define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK) - -#define CAN_TEST_TX_MASK (0x60U) -#define CAN_TEST_TX_SHIFT (5U) -/*! TX - Control of transmit pin. - */ -#define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK) - -#define CAN_TEST_RX_MASK (0x80U) -#define CAN_TEST_RX_SHIFT (7U) -/*! RX - Monitors the actual value of the CAN_RXD. - */ -#define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK) -/*! @} */ - -/*! @name CCCR - CC Control Register */ -/*! @{ */ - -#define CAN_CCCR_INIT_MASK (0x1U) -#define CAN_CCCR_INIT_SHIFT (0U) -/*! INIT - Initialization. - */ -#define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK) - -#define CAN_CCCR_CCE_MASK (0x2U) -#define CAN_CCCR_CCE_SHIFT (1U) -/*! CCE - Configuration change enable. - */ -#define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK) - -#define CAN_CCCR_ASM_MASK (0x4U) -#define CAN_CCCR_ASM_SHIFT (2U) -/*! ASM - Restricted operational mode. - */ -#define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK) - -#define CAN_CCCR_CSA_MASK (0x8U) -#define CAN_CCCR_CSA_SHIFT (3U) -/*! CSA - Clock Stop Acknowledge. - */ -#define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK) - -#define CAN_CCCR_CSR_MASK (0x10U) -#define CAN_CCCR_CSR_SHIFT (4U) -/*! CSR - Clock Stop Request. - */ -#define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK) - -#define CAN_CCCR_MON_MASK (0x20U) -#define CAN_CCCR_MON_SHIFT (5U) -/*! MON - Bus monitoring mode. - */ -#define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK) - -#define CAN_CCCR_DAR_MASK (0x40U) -#define CAN_CCCR_DAR_SHIFT (6U) -/*! DAR - Disable automatic retransmission. - */ -#define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK) - -#define CAN_CCCR_TEST_MASK (0x80U) -#define CAN_CCCR_TEST_SHIFT (7U) -/*! TEST - Test mode enable. - */ -#define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK) - -#define CAN_CCCR_FDOE_MASK (0x100U) -#define CAN_CCCR_FDOE_SHIFT (8U) -/*! FDOE - CAN FD operation enable. - */ -#define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK) - -#define CAN_CCCR_BRSE_MASK (0x200U) -#define CAN_CCCR_BRSE_SHIFT (9U) -/*! BRSE - When CAN FD operation is disabled, this bit is not evaluated. - */ -#define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK) - -#define CAN_CCCR_PXHD_MASK (0x1000U) -#define CAN_CCCR_PXHD_SHIFT (12U) -/*! PXHD - Protocol exception handling disable. - */ -#define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK) - -#define CAN_CCCR_EFBI_MASK (0x2000U) -#define CAN_CCCR_EFBI_SHIFT (13U) -/*! EFBI - Edge filtering during bus integration. - */ -#define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK) - -#define CAN_CCCR_TXP_MASK (0x4000U) -#define CAN_CCCR_TXP_SHIFT (14U) -/*! TXP - Transmit pause. - */ -#define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK) - -#define CAN_CCCR_NISO_MASK (0x8000U) -#define CAN_CCCR_NISO_SHIFT (15U) -/*! NISO - Non ISO operation. - */ -#define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK) -/*! @} */ - -/*! @name NBTP - Nominal Bit Timing and Prescaler Register */ -/*! @{ */ - -#define CAN_NBTP_NTSEG2_MASK (0x7FU) -#define CAN_NBTP_NTSEG2_SHIFT (0U) -/*! NTSEG2 - Nominal time segment after sample point. - */ -#define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK) - -#define CAN_NBTP_NTSEG1_MASK (0xFF00U) -#define CAN_NBTP_NTSEG1_SHIFT (8U) -/*! NTSEG1 - Nominal time segment before sample point. - */ -#define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK) - -#define CAN_NBTP_NBRP_MASK (0x1FF0000U) -#define CAN_NBTP_NBRP_SHIFT (16U) -/*! NBRP - Nominal bit rate prescaler. - */ -#define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK) - -#define CAN_NBTP_NSJW_MASK (0xFE000000U) -#define CAN_NBTP_NSJW_SHIFT (25U) -/*! NSJW - Nominal (re)synchronization jump width. - */ -#define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK) -/*! @} */ - -/*! @name TSCC - Timestamp Counter Configuration */ -/*! @{ */ - -#define CAN_TSCC_TSS_MASK (0x3U) -#define CAN_TSCC_TSS_SHIFT (0U) -/*! TSS - Timestamp select. - */ -#define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK) - -#define CAN_TSCC_TCP_MASK (0xF0000U) -#define CAN_TSCC_TCP_SHIFT (16U) -/*! TCP - Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times. - */ -#define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK) -/*! @} */ - -/*! @name TSCV - Timestamp Counter Value */ -/*! @{ */ - -#define CAN_TSCV_TSC_MASK (0xFFFFU) -#define CAN_TSCV_TSC_SHIFT (0U) -/*! TSC - Timestamp counter. - */ -#define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK) -/*! @} */ - -/*! @name TOCC - Timeout Counter Configuration */ -/*! @{ */ - -#define CAN_TOCC_ETOC_MASK (0x1U) -#define CAN_TOCC_ETOC_SHIFT (0U) -/*! ETOC - Enable timeout counter. - */ -#define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK) - -#define CAN_TOCC_TOS_MASK (0x6U) -#define CAN_TOCC_TOS_SHIFT (1U) -/*! TOS - Timeout select. - */ -#define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK) - -#define CAN_TOCC_TOP_MASK (0xFFFF0000U) -#define CAN_TOCC_TOP_SHIFT (16U) -/*! TOP - Timeout period. - */ -#define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK) -/*! @} */ - -/*! @name TOCV - Timeout Counter Value */ -/*! @{ */ - -#define CAN_TOCV_TOC_MASK (0xFFFFU) -#define CAN_TOCV_TOC_SHIFT (0U) -/*! TOC - Timeout counter. - */ -#define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK) -/*! @} */ - -/*! @name ECR - Error Counter Register */ -/*! @{ */ - -#define CAN_ECR_TEC_MASK (0xFFU) -#define CAN_ECR_TEC_SHIFT (0U) -/*! TEC - Transmit error counter. - */ -#define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK) - -#define CAN_ECR_REC_MASK (0x7F00U) -#define CAN_ECR_REC_SHIFT (8U) -/*! REC - Receive error counter. - */ -#define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK) - -#define CAN_ECR_RP_MASK (0x8000U) -#define CAN_ECR_RP_SHIFT (15U) -/*! RP - Receive error passive. - */ -#define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK) - -#define CAN_ECR_CEL_MASK (0xFF0000U) -#define CAN_ECR_CEL_SHIFT (16U) -/*! CEL - CAN error logging. - */ -#define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK) -/*! @} */ - -/*! @name PSR - Protocol Status Register */ -/*! @{ */ - -#define CAN_PSR_LEC_MASK (0x7U) -#define CAN_PSR_LEC_SHIFT (0U) -/*! LEC - Last error code. - */ -#define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK) - -#define CAN_PSR_ACT_MASK (0x18U) -#define CAN_PSR_ACT_SHIFT (3U) -/*! ACT - Activity. - */ -#define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK) - -#define CAN_PSR_EP_MASK (0x20U) -#define CAN_PSR_EP_SHIFT (5U) -/*! EP - Error Passive. - */ -#define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK) - -#define CAN_PSR_EW_MASK (0x40U) -#define CAN_PSR_EW_SHIFT (6U) -/*! EW - Warning status. - */ -#define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK) - -#define CAN_PSR_BO_MASK (0x80U) -#define CAN_PSR_BO_SHIFT (7U) -/*! BO - Bus Off Status. - */ -#define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK) - -#define CAN_PSR_DLEC_MASK (0x700U) -#define CAN_PSR_DLEC_SHIFT (8U) -/*! DLEC - Data phase last error code. - */ -#define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK) - -#define CAN_PSR_RESI_MASK (0x800U) -#define CAN_PSR_RESI_SHIFT (11U) -/*! RESI - ESI flag of the last received CAN FD message. - */ -#define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK) - -#define CAN_PSR_RBRS_MASK (0x1000U) -#define CAN_PSR_RBRS_SHIFT (12U) -/*! RBRS - BRS flag of last received CAN FD message. - */ -#define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK) - -#define CAN_PSR_RFDF_MASK (0x2000U) -#define CAN_PSR_RFDF_SHIFT (13U) -/*! RFDF - Received a CAN FD message. - */ -#define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK) - -#define CAN_PSR_PXE_MASK (0x4000U) -#define CAN_PSR_PXE_SHIFT (14U) -/*! PXE - Protocol exception event. - */ -#define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK) - -#define CAN_PSR_TDCV_MASK (0x7F0000U) -#define CAN_PSR_TDCV_SHIFT (16U) -/*! TDCV - Transmitter delay compensation value. - */ -#define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK) -/*! @} */ - -/*! @name TDCR - Transmitter Delay Compensator Register */ -/*! @{ */ - -#define CAN_TDCR_TDCF_MASK (0x7FU) -#define CAN_TDCR_TDCF_SHIFT (0U) -/*! TDCF - Transmitter delay compensation filter window length. - */ -#define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK) - -#define CAN_TDCR_TDCO_MASK (0x7F00U) -#define CAN_TDCR_TDCO_SHIFT (8U) -/*! TDCO - Transmitter delay compensation offset. - */ -#define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK) -/*! @} */ - -/*! @name IR - Interrupt Register */ -/*! @{ */ - -#define CAN_IR_RF0N_MASK (0x1U) -#define CAN_IR_RF0N_SHIFT (0U) -/*! RF0N - Rx FIFO 0 new message. - */ -#define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK) - -#define CAN_IR_RF0W_MASK (0x2U) -#define CAN_IR_RF0W_SHIFT (1U) -/*! RF0W - Rx FIFO 0 watermark reached. - */ -#define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK) - -#define CAN_IR_RF0F_MASK (0x4U) -#define CAN_IR_RF0F_SHIFT (2U) -/*! RF0F - Rx FIFO 0 full. - */ -#define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK) - -#define CAN_IR_RF0L_MASK (0x8U) -#define CAN_IR_RF0L_SHIFT (3U) -/*! RF0L - Rx FIFO 0 message lost. - */ -#define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK) - -#define CAN_IR_RF1N_MASK (0x10U) -#define CAN_IR_RF1N_SHIFT (4U) -/*! RF1N - Rx FIFO 1 new message. - */ -#define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK) - -#define CAN_IR_RF1W_MASK (0x20U) -#define CAN_IR_RF1W_SHIFT (5U) -/*! RF1W - Rx FIFO 1 watermark reached. - */ -#define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK) - -#define CAN_IR_RF1F_MASK (0x40U) -#define CAN_IR_RF1F_SHIFT (6U) -/*! RF1F - Rx FIFO 1 full. - */ -#define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK) - -#define CAN_IR_RF1L_MASK (0x80U) -#define CAN_IR_RF1L_SHIFT (7U) -/*! RF1L - Rx FIFO 1 message lost. - */ -#define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK) - -#define CAN_IR_HPM_MASK (0x100U) -#define CAN_IR_HPM_SHIFT (8U) -/*! HPM - High priority message. - */ -#define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK) - -#define CAN_IR_TC_MASK (0x200U) -#define CAN_IR_TC_SHIFT (9U) -/*! TC - Transmission completed. - */ -#define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK) - -#define CAN_IR_TCF_MASK (0x400U) -#define CAN_IR_TCF_SHIFT (10U) -/*! TCF - Transmission cancellation finished. - */ -#define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK) - -#define CAN_IR_TFE_MASK (0x800U) -#define CAN_IR_TFE_SHIFT (11U) -/*! TFE - Tx FIFO empty. - */ -#define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK) - -#define CAN_IR_TEFN_MASK (0x1000U) -#define CAN_IR_TEFN_SHIFT (12U) -/*! TEFN - Tx event FIFO new entry. - */ -#define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK) - -#define CAN_IR_TEFW_MASK (0x2000U) -#define CAN_IR_TEFW_SHIFT (13U) -/*! TEFW - Tx event FIFO watermark reached. - */ -#define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK) - -#define CAN_IR_TEFF_MASK (0x4000U) -#define CAN_IR_TEFF_SHIFT (14U) -/*! TEFF - Tx event FIFO full. - */ -#define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK) - -#define CAN_IR_TEFL_MASK (0x8000U) -#define CAN_IR_TEFL_SHIFT (15U) -/*! TEFL - Tx event FIFO element lost. - */ -#define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK) - -#define CAN_IR_TSW_MASK (0x10000U) -#define CAN_IR_TSW_SHIFT (16U) -/*! TSW - Timestamp wraparound. - */ -#define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK) - -#define CAN_IR_MRAF_MASK (0x20000U) -#define CAN_IR_MRAF_SHIFT (17U) -/*! MRAF - Message RAM access failure. - */ -#define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK) - -#define CAN_IR_TOO_MASK (0x40000U) -#define CAN_IR_TOO_SHIFT (18U) -/*! TOO - Timeout occurred. - */ -#define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK) - -#define CAN_IR_DRX_MASK (0x80000U) -#define CAN_IR_DRX_SHIFT (19U) -/*! DRX - Message stored in dedicated Rx buffer. - */ -#define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK) - -#define CAN_IR_BEC_MASK (0x100000U) -#define CAN_IR_BEC_SHIFT (20U) -/*! BEC - Bit error corrected. - */ -#define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK) - -#define CAN_IR_BEU_MASK (0x200000U) -#define CAN_IR_BEU_SHIFT (21U) -/*! BEU - Bit error uncorrected. - */ -#define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK) - -#define CAN_IR_ELO_MASK (0x400000U) -#define CAN_IR_ELO_SHIFT (22U) -/*! ELO - Error logging overflow. - */ -#define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK) - -#define CAN_IR_EP_MASK (0x800000U) -#define CAN_IR_EP_SHIFT (23U) -/*! EP - Error passive. - */ -#define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK) - -#define CAN_IR_EW_MASK (0x1000000U) -#define CAN_IR_EW_SHIFT (24U) -/*! EW - Warning status. - */ -#define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK) - -#define CAN_IR_BO_MASK (0x2000000U) -#define CAN_IR_BO_SHIFT (25U) -/*! BO - Bus_Off Status. - */ -#define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK) - -#define CAN_IR_WDI_MASK (0x4000000U) -#define CAN_IR_WDI_SHIFT (26U) -/*! WDI - Watchdog interrupt. - */ -#define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK) - -#define CAN_IR_PEA_MASK (0x8000000U) -#define CAN_IR_PEA_SHIFT (27U) -/*! PEA - Protocol error in arbitration phase. - */ -#define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK) - -#define CAN_IR_PED_MASK (0x10000000U) -#define CAN_IR_PED_SHIFT (28U) -/*! PED - Protocol error in data phase. - */ -#define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK) - -#define CAN_IR_ARA_MASK (0x20000000U) -#define CAN_IR_ARA_SHIFT (29U) -/*! ARA - Access to reserved address. - */ -#define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK) -/*! @} */ - -/*! @name IE - Interrupt Enable */ -/*! @{ */ - -#define CAN_IE_RF0NE_MASK (0x1U) -#define CAN_IE_RF0NE_SHIFT (0U) -/*! RF0NE - Rx FIFO 0 new message interrupt enable. - */ -#define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK) - -#define CAN_IE_RF0WE_MASK (0x2U) -#define CAN_IE_RF0WE_SHIFT (1U) -/*! RF0WE - Rx FIFO 0 watermark reached interrupt enable. - */ -#define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK) - -#define CAN_IE_RF0FE_MASK (0x4U) -#define CAN_IE_RF0FE_SHIFT (2U) -/*! RF0FE - Rx FIFO 0 full interrupt enable. - */ -#define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK) - -#define CAN_IE_RF0LE_MASK (0x8U) -#define CAN_IE_RF0LE_SHIFT (3U) -/*! RF0LE - Rx FIFO 0 message lost interrupt enable. - */ -#define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK) - -#define CAN_IE_RF1NE_MASK (0x10U) -#define CAN_IE_RF1NE_SHIFT (4U) -/*! RF1NE - Rx FIFO 1 new message interrupt enable. - */ -#define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK) - -#define CAN_IE_RF1WE_MASK (0x20U) -#define CAN_IE_RF1WE_SHIFT (5U) -/*! RF1WE - Rx FIFO 1 watermark reached interrupt enable. - */ -#define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK) - -#define CAN_IE_RF1FE_MASK (0x40U) -#define CAN_IE_RF1FE_SHIFT (6U) -/*! RF1FE - Rx FIFO 1 full interrupt enable. - */ -#define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK) - -#define CAN_IE_RF1LE_MASK (0x80U) -#define CAN_IE_RF1LE_SHIFT (7U) -/*! RF1LE - Rx FIFO 1 message lost interrupt enable. - */ -#define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK) - -#define CAN_IE_HPME_MASK (0x100U) -#define CAN_IE_HPME_SHIFT (8U) -/*! HPME - High priority message interrupt enable. - */ -#define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK) - -#define CAN_IE_TCE_MASK (0x200U) -#define CAN_IE_TCE_SHIFT (9U) -/*! TCE - Transmission completed interrupt enable. - */ -#define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK) - -#define CAN_IE_TCFE_MASK (0x400U) -#define CAN_IE_TCFE_SHIFT (10U) -/*! TCFE - Transmission cancellation finished interrupt enable. - */ -#define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK) - -#define CAN_IE_TFEE_MASK (0x800U) -#define CAN_IE_TFEE_SHIFT (11U) -/*! TFEE - Tx FIFO empty interrupt enable. - */ -#define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK) - -#define CAN_IE_TEFNE_MASK (0x1000U) -#define CAN_IE_TEFNE_SHIFT (12U) -/*! TEFNE - Tx event FIFO new entry interrupt enable. - */ -#define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK) - -#define CAN_IE_TEFWE_MASK (0x2000U) -#define CAN_IE_TEFWE_SHIFT (13U) -/*! TEFWE - Tx event FIFO watermark reached interrupt enable. - */ -#define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK) - -#define CAN_IE_TEFFE_MASK (0x4000U) -#define CAN_IE_TEFFE_SHIFT (14U) -/*! TEFFE - Tx event FIFO full interrupt enable. - */ -#define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK) - -#define CAN_IE_TEFLE_MASK (0x8000U) -#define CAN_IE_TEFLE_SHIFT (15U) -/*! TEFLE - Tx event FIFO element lost interrupt enable. - */ -#define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK) - -#define CAN_IE_TSWE_MASK (0x10000U) -#define CAN_IE_TSWE_SHIFT (16U) -/*! TSWE - Timestamp wraparound interrupt enable. - */ -#define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK) - -#define CAN_IE_MRAFE_MASK (0x20000U) -#define CAN_IE_MRAFE_SHIFT (17U) -/*! MRAFE - Message RAM access failure interrupt enable. - */ -#define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK) - -#define CAN_IE_TOOE_MASK (0x40000U) -#define CAN_IE_TOOE_SHIFT (18U) -/*! TOOE - Timeout occurred interrupt enable. - */ -#define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK) - -#define CAN_IE_DRXE_MASK (0x80000U) -#define CAN_IE_DRXE_SHIFT (19U) -/*! DRXE - Message stored in dedicated Rx buffer interrupt enable. - */ -#define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK) - -#define CAN_IE_BECE_MASK (0x100000U) -#define CAN_IE_BECE_SHIFT (20U) -/*! BECE - Bit error corrected interrupt enable. - */ -#define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK) - -#define CAN_IE_BEUE_MASK (0x200000U) -#define CAN_IE_BEUE_SHIFT (21U) -/*! BEUE - Bit error uncorrected interrupt enable. - */ -#define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK) - -#define CAN_IE_ELOE_MASK (0x400000U) -#define CAN_IE_ELOE_SHIFT (22U) -/*! ELOE - Error logging overflow interrupt enable. - */ -#define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK) - -#define CAN_IE_EPE_MASK (0x800000U) -#define CAN_IE_EPE_SHIFT (23U) -/*! EPE - Error passive interrupt enable. - */ -#define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK) - -#define CAN_IE_EWE_MASK (0x1000000U) -#define CAN_IE_EWE_SHIFT (24U) -/*! EWE - Warning status interrupt enable. - */ -#define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK) - -#define CAN_IE_BOE_MASK (0x2000000U) -#define CAN_IE_BOE_SHIFT (25U) -/*! BOE - Bus_Off Status interrupt enable. - */ -#define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK) - -#define CAN_IE_WDIE_MASK (0x4000000U) -#define CAN_IE_WDIE_SHIFT (26U) -/*! WDIE - Watchdog interrupt enable. - */ -#define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK) - -#define CAN_IE_PEAE_MASK (0x8000000U) -#define CAN_IE_PEAE_SHIFT (27U) -/*! PEAE - Protocol error in arbitration phase interrupt enable. - */ -#define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK) - -#define CAN_IE_PEDE_MASK (0x10000000U) -#define CAN_IE_PEDE_SHIFT (28U) -/*! PEDE - Protocol error in data phase interrupt enable. - */ -#define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK) - -#define CAN_IE_ARAE_MASK (0x20000000U) -#define CAN_IE_ARAE_SHIFT (29U) -/*! ARAE - Access to reserved address interrupt enable. - */ -#define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK) -/*! @} */ - -/*! @name ILS - Interrupt Line Select */ -/*! @{ */ - -#define CAN_ILS_RF0NL_MASK (0x1U) -#define CAN_ILS_RF0NL_SHIFT (0U) -/*! RF0NL - Rx FIFO 0 new message interrupt line. - */ -#define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK) - -#define CAN_ILS_RF0WL_MASK (0x2U) -#define CAN_ILS_RF0WL_SHIFT (1U) -/*! RF0WL - Rx FIFO 0 watermark reached interrupt line. - */ -#define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK) - -#define CAN_ILS_RF0FL_MASK (0x4U) -#define CAN_ILS_RF0FL_SHIFT (2U) -/*! RF0FL - Rx FIFO 0 full interrupt line. - */ -#define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK) - -#define CAN_ILS_RF0LL_MASK (0x8U) -#define CAN_ILS_RF0LL_SHIFT (3U) -/*! RF0LL - Rx FIFO 0 message lost interrupt line. - */ -#define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK) - -#define CAN_ILS_RF1NL_MASK (0x10U) -#define CAN_ILS_RF1NL_SHIFT (4U) -/*! RF1NL - Rx FIFO 1 new message interrupt line. - */ -#define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK) - -#define CAN_ILS_RF1WL_MASK (0x20U) -#define CAN_ILS_RF1WL_SHIFT (5U) -/*! RF1WL - Rx FIFO 1 watermark reached interrupt line. - */ -#define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK) - -#define CAN_ILS_RF1FL_MASK (0x40U) -#define CAN_ILS_RF1FL_SHIFT (6U) -/*! RF1FL - Rx FIFO 1 full interrupt line. - */ -#define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK) - -#define CAN_ILS_RF1LL_MASK (0x80U) -#define CAN_ILS_RF1LL_SHIFT (7U) -/*! RF1LL - Rx FIFO 1 message lost interrupt line. - */ -#define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK) - -#define CAN_ILS_HPML_MASK (0x100U) -#define CAN_ILS_HPML_SHIFT (8U) -/*! HPML - High priority message interrupt line. - */ -#define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK) - -#define CAN_ILS_TCL_MASK (0x200U) -#define CAN_ILS_TCL_SHIFT (9U) -/*! TCL - Transmission completed interrupt line. - */ -#define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK) - -#define CAN_ILS_TCFL_MASK (0x400U) -#define CAN_ILS_TCFL_SHIFT (10U) -/*! TCFL - Transmission cancellation finished interrupt line. - */ -#define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK) - -#define CAN_ILS_TFEL_MASK (0x800U) -#define CAN_ILS_TFEL_SHIFT (11U) -/*! TFEL - Tx FIFO empty interrupt line. - */ -#define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK) - -#define CAN_ILS_TEFNL_MASK (0x1000U) -#define CAN_ILS_TEFNL_SHIFT (12U) -/*! TEFNL - Tx event FIFO new entry interrupt line. - */ -#define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK) - -#define CAN_ILS_TEFWL_MASK (0x2000U) -#define CAN_ILS_TEFWL_SHIFT (13U) -/*! TEFWL - Tx event FIFO watermark reached interrupt line. - */ -#define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK) - -#define CAN_ILS_TEFFL_MASK (0x4000U) -#define CAN_ILS_TEFFL_SHIFT (14U) -/*! TEFFL - Tx event FIFO full interrupt line. - */ -#define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK) - -#define CAN_ILS_TEFLL_MASK (0x8000U) -#define CAN_ILS_TEFLL_SHIFT (15U) -/*! TEFLL - Tx event FIFO element lost interrupt line. - */ -#define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK) - -#define CAN_ILS_TSWL_MASK (0x10000U) -#define CAN_ILS_TSWL_SHIFT (16U) -/*! TSWL - Timestamp wraparound interrupt line. - */ -#define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK) - -#define CAN_ILS_MRAFL_MASK (0x20000U) -#define CAN_ILS_MRAFL_SHIFT (17U) -/*! MRAFL - Message RAM access failure interrupt line. - */ -#define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK) - -#define CAN_ILS_TOOL_MASK (0x40000U) -#define CAN_ILS_TOOL_SHIFT (18U) -/*! TOOL - Timeout occurred interrupt line. - */ -#define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK) - -#define CAN_ILS_DRXL_MASK (0x80000U) -#define CAN_ILS_DRXL_SHIFT (19U) -/*! DRXL - Message stored in dedicated Rx buffer interrupt line. - */ -#define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK) - -#define CAN_ILS_BECL_MASK (0x100000U) -#define CAN_ILS_BECL_SHIFT (20U) -/*! BECL - Bit error corrected interrupt line. - */ -#define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK) - -#define CAN_ILS_BEUL_MASK (0x200000U) -#define CAN_ILS_BEUL_SHIFT (21U) -/*! BEUL - Bit error uncorrected interrupt line. - */ -#define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK) - -#define CAN_ILS_ELOL_MASK (0x400000U) -#define CAN_ILS_ELOL_SHIFT (22U) -/*! ELOL - Error logging overflow interrupt line. - */ -#define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK) - -#define CAN_ILS_EPL_MASK (0x800000U) -#define CAN_ILS_EPL_SHIFT (23U) -/*! EPL - Error passive interrupt line. - */ -#define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK) - -#define CAN_ILS_EWL_MASK (0x1000000U) -#define CAN_ILS_EWL_SHIFT (24U) -/*! EWL - Warning status interrupt line. - */ -#define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK) - -#define CAN_ILS_BOL_MASK (0x2000000U) -#define CAN_ILS_BOL_SHIFT (25U) -/*! BOL - Bus_Off Status interrupt line. - */ -#define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK) - -#define CAN_ILS_WDIL_MASK (0x4000000U) -#define CAN_ILS_WDIL_SHIFT (26U) -/*! WDIL - Watchdog interrupt line. - */ -#define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK) - -#define CAN_ILS_PEAL_MASK (0x8000000U) -#define CAN_ILS_PEAL_SHIFT (27U) -/*! PEAL - Protocol error in arbitration phase interrupt line. - */ -#define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK) - -#define CAN_ILS_PEDL_MASK (0x10000000U) -#define CAN_ILS_PEDL_SHIFT (28U) -/*! PEDL - Protocol error in data phase interrupt line. - */ -#define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK) - -#define CAN_ILS_ARAL_MASK (0x20000000U) -#define CAN_ILS_ARAL_SHIFT (29U) -/*! ARAL - Access to reserved address interrupt line. - */ -#define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK) -/*! @} */ - -/*! @name ILE - Interrupt Line Enable */ -/*! @{ */ - -#define CAN_ILE_EINT0_MASK (0x1U) -#define CAN_ILE_EINT0_SHIFT (0U) -/*! EINT0 - Enable interrupt line 0. - */ -#define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK) - -#define CAN_ILE_EINT1_MASK (0x2U) -#define CAN_ILE_EINT1_SHIFT (1U) -/*! EINT1 - Enable interrupt line 1. - */ -#define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK) -/*! @} */ - -/*! @name GFC - Global Filter Configuration */ -/*! @{ */ - -#define CAN_GFC_RRFE_MASK (0x1U) -#define CAN_GFC_RRFE_SHIFT (0U) -/*! RRFE - Reject remote frames extended. - */ -#define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK) - -#define CAN_GFC_RRFS_MASK (0x2U) -#define CAN_GFC_RRFS_SHIFT (1U) -/*! RRFS - Reject remote frames standard. - */ -#define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK) - -#define CAN_GFC_ANFE_MASK (0xCU) -#define CAN_GFC_ANFE_SHIFT (2U) -/*! ANFE - Accept non-matching frames extended. - */ -#define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK) - -#define CAN_GFC_ANFS_MASK (0x30U) -#define CAN_GFC_ANFS_SHIFT (4U) -/*! ANFS - Accept non-matching frames standard. - */ -#define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK) -/*! @} */ - -/*! @name SIDFC - Standard ID Filter Configuration */ -/*! @{ */ - -#define CAN_SIDFC_FLSSA_MASK (0xFFFCU) -#define CAN_SIDFC_FLSSA_SHIFT (2U) -/*! FLSSA - Filter list standard start address. - */ -#define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK) - -#define CAN_SIDFC_LSS_MASK (0xFF0000U) -#define CAN_SIDFC_LSS_SHIFT (16U) -/*! LSS - List size standard 0 = No standard message ID filter. - */ -#define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK) -/*! @} */ - -/*! @name XIDFC - Extended ID Filter Configuration */ -/*! @{ */ - -#define CAN_XIDFC_FLESA_MASK (0xFFFCU) -#define CAN_XIDFC_FLESA_SHIFT (2U) -/*! FLESA - Filter list extended start address. - */ -#define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK) - -#define CAN_XIDFC_LSE_MASK (0xFF0000U) -#define CAN_XIDFC_LSE_SHIFT (16U) -/*! LSE - List size extended 0 = No extended message ID filter. - */ -#define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK) -/*! @} */ - -/*! @name XIDAM - Extended ID AND Mask */ -/*! @{ */ - -#define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU) -#define CAN_XIDAM_EIDM_SHIFT (0U) -/*! EIDM - Extended ID mask. - */ -#define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK) -/*! @} */ - -/*! @name HPMS - High Priority Message Status */ -/*! @{ */ - -#define CAN_HPMS_BIDX_MASK (0x3FU) -#define CAN_HPMS_BIDX_SHIFT (0U) -/*! BIDX - Buffer index. - */ -#define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK) - -#define CAN_HPMS_MSI_MASK (0xC0U) -#define CAN_HPMS_MSI_SHIFT (6U) -/*! MSI - Message storage indicator. - */ -#define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK) - -#define CAN_HPMS_FIDX_MASK (0x7F00U) -#define CAN_HPMS_FIDX_SHIFT (8U) -/*! FIDX - Filter index. - */ -#define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK) - -#define CAN_HPMS_FLST_MASK (0x8000U) -#define CAN_HPMS_FLST_SHIFT (15U) -/*! FLST - Filter list. - */ -#define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK) -/*! @} */ - -/*! @name NDAT1 - New Data 1 */ -/*! @{ */ - -#define CAN_NDAT1_ND_MASK (0xFFFFFFFFU) -#define CAN_NDAT1_ND_SHIFT (0U) -/*! ND - New Data. - */ -#define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK) -/*! @} */ - -/*! @name NDAT2 - New Data 2 */ -/*! @{ */ - -#define CAN_NDAT2_ND_MASK (0xFFFFFFFFU) -#define CAN_NDAT2_ND_SHIFT (0U) -/*! ND - New Data. - */ -#define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK) -/*! @} */ - -/*! @name RXF0C - Rx FIFO 0 Configuration */ -/*! @{ */ - -#define CAN_RXF0C_F0SA_MASK (0xFFFCU) -#define CAN_RXF0C_F0SA_SHIFT (2U) -/*! F0SA - Rx FIFO 0 start address. - */ -#define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK) - -#define CAN_RXF0C_F0S_MASK (0x7F0000U) -#define CAN_RXF0C_F0S_SHIFT (16U) -/*! F0S - Rx FIFO 0 size. - */ -#define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK) - -#define CAN_RXF0C_F0WM_MASK (0x7F000000U) -#define CAN_RXF0C_F0WM_SHIFT (24U) -/*! F0WM - Rx FIFO 0 watermark 0 = Watermark interrupt disabled. - */ -#define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK) - -#define CAN_RXF0C_F0OM_MASK (0x80000000U) -#define CAN_RXF0C_F0OM_SHIFT (31U) -/*! F0OM - FIFO 0 operation mode. - */ -#define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK) -/*! @} */ - -/*! @name RXF0S - Rx FIFO 0 Status */ -/*! @{ */ - -#define CAN_RXF0S_F0FL_MASK (0x7FU) -#define CAN_RXF0S_F0FL_SHIFT (0U) -/*! F0FL - Rx FIFO 0 fill level. - */ -#define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK) - -#define CAN_RXF0S_F0GI_MASK (0x3F00U) -#define CAN_RXF0S_F0GI_SHIFT (8U) -/*! F0GI - Rx FIFO 0 get index. - */ -#define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK) - -#define CAN_RXF0S_F0PI_MASK (0x3F0000U) -#define CAN_RXF0S_F0PI_SHIFT (16U) -/*! F0PI - Rx FIFO 0 put index. - */ -#define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK) - -#define CAN_RXF0S_F0F_MASK (0x1000000U) -#define CAN_RXF0S_F0F_SHIFT (24U) -/*! F0F - Rx FIFO 0 full. - */ -#define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK) - -#define CAN_RXF0S_RF0L_MASK (0x2000000U) -#define CAN_RXF0S_RF0L_SHIFT (25U) -/*! RF0L - Rx FIFO 0 message lost. - */ -#define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK) -/*! @} */ - -/*! @name RXF0A - Rx FIFO 0 Acknowledge */ -/*! @{ */ - -#define CAN_RXF0A_F0AI_MASK (0x3FU) -#define CAN_RXF0A_F0AI_SHIFT (0U) -/*! F0AI - Rx FIFO 0 acknowledge index. - */ -#define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK) -/*! @} */ - -/*! @name RXBC - Rx Buffer Configuration */ -/*! @{ */ - -#define CAN_RXBC_RBSA_MASK (0xFFFCU) -#define CAN_RXBC_RBSA_SHIFT (2U) -/*! RBSA - Rx buffer start address. - */ -#define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK) -/*! @} */ - -/*! @name RXF1C - Rx FIFO 1 Configuration */ -/*! @{ */ - -#define CAN_RXF1C_F1SA_MASK (0xFFFCU) -#define CAN_RXF1C_F1SA_SHIFT (2U) -/*! F1SA - Rx FIFO 1 start address. - */ -#define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK) - -#define CAN_RXF1C_F1S_MASK (0x7F0000U) -#define CAN_RXF1C_F1S_SHIFT (16U) -/*! F1S - Rx FIFO 1 size 0 = No Rx FIFO 1. - */ -#define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK) - -#define CAN_RXF1C_F1WM_MASK (0x7F000000U) -#define CAN_RXF1C_F1WM_SHIFT (24U) -/*! F1WM - Rx FIFO 1 watermark 0 = Watermark interrupt disabled. - */ -#define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK) - -#define CAN_RXF1C_F1OM_MASK (0x80000000U) -#define CAN_RXF1C_F1OM_SHIFT (31U) -/*! F1OM - FIFO 1 operation mode. - */ -#define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK) -/*! @} */ - -/*! @name RXF1S - Rx FIFO 1 Status */ -/*! @{ */ - -#define CAN_RXF1S_F1FL_MASK (0x7FU) -#define CAN_RXF1S_F1FL_SHIFT (0U) -/*! F1FL - Rx FIFO 1 fill level. - */ -#define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK) - -#define CAN_RXF1S_F1GI_MASK (0x3F00U) -#define CAN_RXF1S_F1GI_SHIFT (8U) -/*! F1GI - Rx FIFO 1 get index. - */ -#define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK) - -#define CAN_RXF1S_F1PI_MASK (0x3F0000U) -#define CAN_RXF1S_F1PI_SHIFT (16U) -/*! F1PI - Rx FIFO 1 put index. - */ -#define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK) - -#define CAN_RXF1S_F1F_MASK (0x1000000U) -#define CAN_RXF1S_F1F_SHIFT (24U) -/*! F1F - Rx FIFO 1 full. - */ -#define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK) - -#define CAN_RXF1S_RF1L_MASK (0x2000000U) -#define CAN_RXF1S_RF1L_SHIFT (25U) -/*! RF1L - Rx FIFO 1 message lost. - */ -#define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK) -/*! @} */ - -/*! @name RXF1A - Rx FIFO 1 Acknowledge */ -/*! @{ */ - -#define CAN_RXF1A_F1AI_MASK (0x3FU) -#define CAN_RXF1A_F1AI_SHIFT (0U) -/*! F1AI - Rx FIFO 1 acknowledge index. - */ -#define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK) -/*! @} */ - -/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */ -/*! @{ */ - -#define CAN_RXESC_F0DS_MASK (0x7U) -#define CAN_RXESC_F0DS_SHIFT (0U) -/*! F0DS - Rx FIFO 0 data field size. - */ -#define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK) - -#define CAN_RXESC_F1DS_MASK (0x70U) -#define CAN_RXESC_F1DS_SHIFT (4U) -/*! F1DS - Rx FIFO 1 data field size. - */ -#define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK) - -#define CAN_RXESC_RBDS_MASK (0x700U) -#define CAN_RXESC_RBDS_SHIFT (8U) -/*! RBDS - . - */ -#define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK) -/*! @} */ - -/*! @name TXBC - Tx Buffer Configuration */ -/*! @{ */ - -#define CAN_TXBC_TBSA_MASK (0xFFFCU) -#define CAN_TXBC_TBSA_SHIFT (2U) -/*! TBSA - Tx buffers start address. - */ -#define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK) - -#define CAN_TXBC_NDTB_MASK (0x3F0000U) -#define CAN_TXBC_NDTB_SHIFT (16U) -/*! NDTB - Number of dedicated transmit buffers 0 = No dedicated Tx buffers. - */ -#define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK) - -#define CAN_TXBC_TFQS_MASK (0x3F000000U) -#define CAN_TXBC_TFQS_SHIFT (24U) -/*! TFQS - Transmit FIFO/queue size 0 = No tx FIFO/Queue. - */ -#define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK) - -#define CAN_TXBC_TFQM_MASK (0x40000000U) -#define CAN_TXBC_TFQM_SHIFT (30U) -/*! TFQM - Tx FIFO/queue mode. - */ -#define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK) -/*! @} */ - -/*! @name TXFQS - Tx FIFO/Queue Status */ -/*! @{ */ - -#define CAN_TXFQS_TFGI_MASK (0x1F00U) -#define CAN_TXFQS_TFGI_SHIFT (8U) -/*! TFGI - Tx FIFO get index. - */ -#define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK) - -#define CAN_TXFQS_TFQPI_MASK (0x1F0000U) -#define CAN_TXFQS_TFQPI_SHIFT (16U) -/*! TFQPI - Tx FIFO/queue put index. - */ -#define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK) - -#define CAN_TXFQS_TFQF_MASK (0x200000U) -#define CAN_TXFQS_TFQF_SHIFT (21U) -/*! TFQF - Tx FIFO/queue full. - */ -#define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK) -/*! @} */ - -/*! @name TXESC - Tx Buffer Element Size Configuration */ -/*! @{ */ - -#define CAN_TXESC_TBDS_MASK (0x7U) -#define CAN_TXESC_TBDS_SHIFT (0U) -/*! TBDS - Tx buffer data field size. - */ -#define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK) -/*! @} */ - -/*! @name TXBRP - Tx Buffer Request Pending */ -/*! @{ */ - -#define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU) -#define CAN_TXBRP_TRP_SHIFT (0U) -/*! TRP - Transmission request pending. - */ -#define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK) -/*! @} */ - -/*! @name TXBAR - Tx Buffer Add Request */ -/*! @{ */ - -#define CAN_TXBAR_AR_MASK (0xFFFFFFFFU) -#define CAN_TXBAR_AR_SHIFT (0U) -/*! AR - Add request. - */ -#define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK) -/*! @} */ - -/*! @name TXBCR - Tx Buffer Cancellation Request */ -/*! @{ */ - -#define CAN_TXBCR_CR_MASK (0xFFFFFFFFU) -#define CAN_TXBCR_CR_SHIFT (0U) -/*! CR - Cancellation request. - */ -#define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK) -/*! @} */ - -/*! @name TXBTO - Tx Buffer Transmission Occurred */ -/*! @{ */ - -#define CAN_TXBTO_TO_MASK (0xFFFFFFFFU) -#define CAN_TXBTO_TO_SHIFT (0U) -/*! TO - Transmission occurred. - */ -#define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK) -/*! @} */ - -/*! @name TXBCF - Tx Buffer Cancellation Finished */ -/*! @{ */ - -#define CAN_TXBCF_TO_MASK (0xFFFFFFFFU) -#define CAN_TXBCF_TO_SHIFT (0U) -/*! TO - Cancellation finished. - */ -#define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK) -/*! @} */ - -/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */ -/*! @{ */ - -#define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU) -#define CAN_TXBTIE_TIE_SHIFT (0U) -/*! TIE - Transmission interrupt enable. - */ -#define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK) -/*! @} */ - -/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */ -/*! @{ */ - -#define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU) -#define CAN_TXBCIE_CFIE_SHIFT (0U) -/*! CFIE - Cancellation finished interrupt enable. - */ -#define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK) -/*! @} */ - -/*! @name TXEFC - Tx Event FIFO Configuration */ -/*! @{ */ - -#define CAN_TXEFC_EFSA_MASK (0xFFFCU) -#define CAN_TXEFC_EFSA_SHIFT (2U) -/*! EFSA - Event FIFO start address. - */ -#define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK) - -#define CAN_TXEFC_EFS_MASK (0x3F0000U) -#define CAN_TXEFC_EFS_SHIFT (16U) -/*! EFS - Event FIFO size 0 = Tx event FIFO disabled. - */ -#define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK) - -#define CAN_TXEFC_EFWM_MASK (0x3F000000U) -#define CAN_TXEFC_EFWM_SHIFT (24U) -/*! EFWM - Event FIFO watermark 0 = Watermark interrupt disabled. - */ -#define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK) -/*! @} */ - -/*! @name TXEFS - Tx Event FIFO Status */ -/*! @{ */ - -#define CAN_TXEFS_EFFL_MASK (0x3FU) -#define CAN_TXEFS_EFFL_SHIFT (0U) -/*! EFFL - Event FIFO fill level. - */ -#define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK) - -#define CAN_TXEFS_EFGI_MASK (0x1F00U) -#define CAN_TXEFS_EFGI_SHIFT (8U) -/*! EFGI - Event FIFO get index. - */ -#define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK) - -#define CAN_TXEFS_EFPI_MASK (0x3F0000U) -#define CAN_TXEFS_EFPI_SHIFT (16U) -/*! EFPI - Event FIFO put index. - */ -#define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK) - -#define CAN_TXEFS_EFF_MASK (0x1000000U) -#define CAN_TXEFS_EFF_SHIFT (24U) -/*! EFF - Event FIFO full. - */ -#define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK) - -#define CAN_TXEFS_TEFL_MASK (0x2000000U) -#define CAN_TXEFS_TEFL_SHIFT (25U) -/*! TEFL - Tx event FIFO element lost. - */ -#define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK) -/*! @} */ - -/*! @name TXEFA - Tx Event FIFO Acknowledge */ -/*! @{ */ - -#define CAN_TXEFA_EFAI_MASK (0x1FU) -#define CAN_TXEFA_EFAI_SHIFT (0U) -/*! EFAI - Event FIFO acknowledge index. - */ -#define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK) -/*! @} */ - -/*! @name MRBA - CAN Message RAM Base Address */ -/*! @{ */ - -#define CAN_MRBA_BA_MASK (0xFFFF0000U) -#define CAN_MRBA_BA_SHIFT (16U) -/*! BA - Base address for the message RAM in the chip memory map. - */ -#define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK) -/*! @} */ - -/*! @name ETSCC - External Timestamp Counter Configuration */ -/*! @{ */ - -#define CAN_ETSCC_ETCP_MASK (0x7FFU) -#define CAN_ETSCC_ETCP_SHIFT (0U) -/*! ETCP - External timestamp prescaler value. - */ -#define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK) - -#define CAN_ETSCC_ETCE_MASK (0x80000000U) -#define CAN_ETSCC_ETCE_SHIFT (31U) -/*! ETCE - External timestamp counter enable. - */ -#define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK) -/*! @} */ - -/*! @name ETSCV - External Timestamp Counter Value */ -/*! @{ */ - -#define CAN_ETSCV_ETSC_MASK (0xFFFFU) -#define CAN_ETSCV_ETSC_SHIFT (0U) -/*! ETSC - External timestamp counter. - */ -#define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CAN_Register_Masks */ - - -/* CAN - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CAN0 base address */ - #define CAN0_BASE (0x5009D000u) - /** Peripheral CAN0 base address */ - #define CAN0_BASE_NS (0x4009D000u) - /** Peripheral CAN0 base pointer */ - #define CAN0 ((CAN_Type *)CAN0_BASE) - /** Peripheral CAN0 base pointer */ - #define CAN0_NS ((CAN_Type *)CAN0_BASE_NS) - /** Array initializer of CAN peripheral base addresses */ - #define CAN_BASE_ADDRS { CAN0_BASE } - /** Array initializer of CAN peripheral base pointers */ - #define CAN_BASE_PTRS { CAN0 } - /** Array initializer of CAN peripheral base addresses */ - #define CAN_BASE_ADDRS_NS { CAN0_BASE_NS } - /** Array initializer of CAN peripheral base pointers */ - #define CAN_BASE_PTRS_NS { CAN0_NS } -#else - /** Peripheral CAN0 base address */ - #define CAN0_BASE (0x4009D000u) - /** Peripheral CAN0 base pointer */ - #define CAN0 ((CAN_Type *)CAN0_BASE) - /** Array initializer of CAN peripheral base addresses */ - #define CAN_BASE_ADDRS { CAN0_BASE } - /** Array initializer of CAN peripheral base pointers */ - #define CAN_BASE_PTRS { CAN0 } -#endif -/** Interrupt vectors for the CAN peripheral type */ -#define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn } } - -/*! - * @} - */ /* end of group CAN_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CASPER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CASPER_Peripheral_Access_Layer CASPER Peripheral Access Layer - * @{ - */ - -/** CASPER - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL0; /**< Contains the offsets of AB and CD in the RAM., offset: 0x0 */ - __IO uint32_t CTRL1; /**< Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR., offset: 0x4 */ - __IO uint32_t LOADER; /**< Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations., offset: 0x8 */ - __IO uint32_t STATUS; /**< Indicates operational status and would contain the carry bit if used., offset: 0xC */ - __IO uint32_t INTENSET; /**< Sets interrupts, offset: 0x10 */ - __IO uint32_t INTENCLR; /**< Clears interrupts, offset: 0x14 */ - __I uint32_t INTSTAT; /**< Interrupt status bits (mask of INTENSET and STATUS), offset: 0x18 */ - uint8_t RESERVED_0[4]; - __IO uint32_t AREG; /**< A register, offset: 0x20 */ - __IO uint32_t BREG; /**< B register, offset: 0x24 */ - __IO uint32_t CREG; /**< C register, offset: 0x28 */ - __IO uint32_t DREG; /**< D register, offset: 0x2C */ - __IO uint32_t RES0; /**< Result register 0, offset: 0x30 */ - __IO uint32_t RES1; /**< Result register 1, offset: 0x34 */ - __IO uint32_t RES2; /**< Result register 2, offset: 0x38 */ - __IO uint32_t RES3; /**< Result register 3, offset: 0x3C */ - uint8_t RESERVED_1[32]; - __IO uint32_t MASK; /**< Optional mask register, offset: 0x60 */ - __IO uint32_t REMASK; /**< Optional re-mask register, offset: 0x64 */ - uint8_t RESERVED_2[24]; - __IO uint32_t LOCK; /**< Security lock register, offset: 0x80 */ -} CASPER_Type; - -/* ---------------------------------------------------------------------------- - -- CASPER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CASPER_Register_Masks CASPER Register Masks - * @{ - */ - -/*! @name CTRL0 - Contains the offsets of AB and CD in the RAM. */ -/*! @{ */ - -#define CASPER_CTRL0_ABBPAIR_MASK (0x1U) -#define CASPER_CTRL0_ABBPAIR_SHIFT (0U) -/*! ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_CTRL0_ABBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK) - -#define CASPER_CTRL0_ABOFF_MASK (0x1FFCU) -#define CASPER_CTRL0_ABOFF_SHIFT (2U) -/*! ABOFF - Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code - * sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed - * if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up - */ -#define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK) - -#define CASPER_CTRL0_CDBPAIR_MASK (0x10000U) -#define CASPER_CTRL0_CDBPAIR_SHIFT (16U) -/*! CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_CTRL0_CDBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK) - -#define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U) -#define CASPER_CTRL0_CDOFF_SHIFT (18U) -/*! CDOFF - Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees - * (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 - * bit operation. Ideally not in the same RAM as the AB values - */ -#define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK) -/*! @} */ - -/*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */ -/*! @{ */ - -#define CASPER_CTRL1_ITER_MASK (0xFFU) -#define CASPER_CTRL1_ITER_SHIFT (0U) -/*! ITER - Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate. - */ -#define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK) - -#define CASPER_CTRL1_MODE_MASK (0xFF00U) -#define CASPER_CTRL1_MODE_SHIFT (8U) -/*! MODE - Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active. - */ -#define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK) - -#define CASPER_CTRL1_RESBPAIR_MASK (0x10000U) -#define CASPER_CTRL1_RESBPAIR_SHIFT (16U) -/*! RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally - * this is not the same bank as ABBPAIR (when 4-up supported) - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_CTRL1_RESBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK) - -#define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U) -#define CASPER_CTRL1_RESOFF_SHIFT (18U) -/*! RESOFF - Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally - * not in the same RAM as the AB and CD values - */ -#define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK) - -#define CASPER_CTRL1_CSKIP_MASK (0xC0000000U) -#define CASPER_CTRL1_CSKIP_SHIFT (30U) -/*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: - * 0b00..No Skip - * 0b01..Skip if Carry is 1 - * 0b10..Skip if Carry is 0 - * 0b11..Set CTRLOFF to CDOFF and Skip - */ -#define CASPER_CTRL1_CSKIP(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK) -/*! @} */ - -/*! @name LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. */ -/*! @{ */ - -#define CASPER_LOADER_COUNT_MASK (0xFFU) -#define CASPER_LOADER_COUNT_SHIFT (0U) -/*! COUNT - Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one - * op - does not iterate, write N means N control pairs to load - */ -#define CASPER_LOADER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK) - -#define CASPER_LOADER_CTRLBPAIR_MASK (0x10000U) -#define CASPER_LOADER_CTRLBPAIR_SHIFT (16U) -/*! CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not - * matter which bank is used as this is loaded when not performing an operation. - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_LOADER_CTRLBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK) - -#define CASPER_LOADER_CTRLOFF_MASK (0x1FFC0000U) -#define CASPER_LOADER_CTRLOFF_SHIFT (18U) -/*! CTRLOFF - DWord Offset of CTRL pair to load next. - */ -#define CASPER_LOADER_CTRLOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK) -/*! @} */ - -/*! @name STATUS - Indicates operational status and would contain the carry bit if used. */ -/*! @{ */ - -#define CASPER_STATUS_DONE_MASK (0x1U) -#define CASPER_STATUS_DONE_SHIFT (0U) -/*! DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. - * 0b0..Busy or just cleared - * 0b1..Completed last operation - */ -#define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK) - -#define CASPER_STATUS_CARRY_MASK (0x10U) -#define CASPER_STATUS_CARRY_SHIFT (4U) -/*! CARRY - Last carry value if operation produced a carry bit - * 0b0..Carry was 0 or no carry - * 0b1..Carry was 1 - */ -#define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK) - -#define CASPER_STATUS_BUSY_MASK (0x20U) -#define CASPER_STATUS_BUSY_SHIFT (5U) -/*! BUSY - Indicates if the accelerator is busy performing an operation - * 0b0..Not busy - is idle - * 0b1..Is busy - */ -#define CASPER_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK) -/*! @} */ - -/*! @name INTENSET - Sets interrupts */ -/*! @{ */ - -#define CASPER_INTENSET_DONE_MASK (0x1U) -#define CASPER_INTENSET_DONE_SHIFT (0U) -/*! DONE - Set if the accelerator should interrupt when done. - * 0b0..Do not interrupt when done - * 0b1..Interrupt when done - */ -#define CASPER_INTENSET_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK) -/*! @} */ - -/*! @name INTENCLR - Clears interrupts */ -/*! @{ */ - -#define CASPER_INTENCLR_DONE_MASK (0x1U) -#define CASPER_INTENCLR_DONE_SHIFT (0U) -/*! DONE - Written to clear an interrupt set with INTENSET. - * 0b0..If written 0, ignored - * 0b1..If written 1, do not Interrupt when done - */ -#define CASPER_INTENCLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) */ -/*! @{ */ - -#define CASPER_INTSTAT_DONE_MASK (0x1U) -#define CASPER_INTSTAT_DONE_SHIFT (0U) -/*! DONE - If set, interrupt is caused by accelerator being done. - * 0b0..Not caused by accelerator being done - * 0b1..Caused by accelerator being done - */ -#define CASPER_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK) -/*! @} */ - -/*! @name AREG - A register */ -/*! @{ */ - -#define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_AREG_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, - * but is available when accelerator not busy. - */ -#define CASPER_AREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name BREG - B register */ -/*! @{ */ - -#define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_BREG_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, - * but is available when accelerator not busy. - */ -#define CASPER_BREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name CREG - C register */ -/*! @{ */ - -#define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_CREG_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, - * but is available when accelerator not busy. - */ -#define CASPER_CREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name DREG - D register */ -/*! @{ */ - -#define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_DREG_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, - * but is available when accelerator not busy. - */ -#define CASPER_DREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES0 - Result register 0 */ -/*! @{ */ - -#define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES0_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally - * written or read by application, but is available when accelerator not busy. - */ -#define CASPER_RES0_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES1 - Result register 1 */ -/*! @{ */ - -#define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES1_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally - * written or read by application, but is available when accelerator not busy. - */ -#define CASPER_RES1_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES2 - Result register 2 */ -/*! @{ */ - -#define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES2_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally - * written or read by application, but is available when accelerator not busy. - */ -#define CASPER_RES2_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES3 - Result register 3 */ -/*! @{ */ - -#define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES3_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally - * written or read by application, but is available when accelerator not busy. - */ -#define CASPER_RES3_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK) -/*! @} */ - -/*! @name MASK - Optional mask register */ -/*! @{ */ - -#define CASPER_MASK_MASK_MASK (0xFFFFFFFFU) -#define CASPER_MASK_MASK_SHIFT (0U) -/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values - */ -#define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK) -/*! @} */ - -/*! @name REMASK - Optional re-mask register */ -/*! @{ */ - -#define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU) -#define CASPER_REMASK_MASK_SHIFT (0U) -/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values - */ -#define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK) -/*! @} */ - -/*! @name LOCK - Security lock register */ -/*! @{ */ - -#define CASPER_LOCK_LOCK_MASK (0x1U) -#define CASPER_LOCK_LOCK_SHIFT (0U) -/*! LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. - * 0b0..unlock - * 0b1..Lock to current security level - */ -#define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK) - -#define CASPER_LOCK_KEY_MASK (0x1FFF0U) -#define CASPER_LOCK_KEY_SHIFT (4U) -/*! KEY - Must be written as 0x73D to change the register. - * 0b0011100111101..If set during write, will allow lock or unlock - */ -#define CASPER_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CASPER_Register_Masks */ - - -/* CASPER - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CASPER base address */ - #define CASPER_BASE (0x500A5000u) - /** Peripheral CASPER base address */ - #define CASPER_BASE_NS (0x400A5000u) - /** Peripheral CASPER base pointer */ - #define CASPER ((CASPER_Type *)CASPER_BASE) - /** Peripheral CASPER base pointer */ - #define CASPER_NS ((CASPER_Type *)CASPER_BASE_NS) - /** Array initializer of CASPER peripheral base addresses */ - #define CASPER_BASE_ADDRS { CASPER_BASE } - /** Array initializer of CASPER peripheral base pointers */ - #define CASPER_BASE_PTRS { CASPER } - /** Array initializer of CASPER peripheral base addresses */ - #define CASPER_BASE_ADDRS_NS { CASPER_BASE_NS } - /** Array initializer of CASPER peripheral base pointers */ - #define CASPER_BASE_PTRS_NS { CASPER_NS } -#else - /** Peripheral CASPER base address */ - #define CASPER_BASE (0x400A5000u) - /** Peripheral CASPER base pointer */ - #define CASPER ((CASPER_Type *)CASPER_BASE) - /** Array initializer of CASPER peripheral base addresses */ - #define CASPER_BASE_ADDRS { CASPER_BASE } - /** Array initializer of CASPER peripheral base pointers */ - #define CASPER_BASE_PTRS { CASPER } -#endif -/** Interrupt vectors for the CASPER peripheral type */ -#define CASPER_IRQS { CASER_IRQn } - -/*! - * @} - */ /* end of group CASPER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CDOG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer - * @{ - */ - -/** CDOG - Register Layout Typedef */ -typedef struct { - __IO uint32_t CONTROL; /**< The control fields, which constitute CONTROL, control all controllable attributes of the module, including those of CONTROL itself., offset: 0x0 */ - __IO uint32_t RELOAD; /**< Instruction timer reload, offset: 0x4 */ - __IO uint32_t INSTRUCTION_TIMER; /**< The INSTRUCTION TIMER itself, offset: 0x8 */ - __IO uint32_t SECURE_COUNTER; /**< Also known as SEC_CNT, offset: 0xC */ - __I uint32_t STATUS; /**< Status register (1 of 2), offset: 0x10 */ - __I uint32_t STATUS2; /**< STATUS register (2 of 2), offset: 0x14 */ - __IO uint32_t FLAGS; /**< Hardware flags, offset: 0x18 */ - __IO uint32_t PERSISTENT; /**< Persistent (Ad. Hoc., quasi-NV) data storage, offset: 0x1C */ - __O uint32_t START; /**< Write address for issuing the START command., offset: 0x20 */ - __O uint32_t STOP; /**< Write address for issuing the STOP command., offset: 0x24 */ - __O uint32_t RESTART; /**< Write address for issuing the RESTART command., offset: 0x28 */ - __O uint32_t ADD; /**< Write address for issuing the ADD command., offset: 0x2C */ - __O uint32_t ADD1; /**< Write address for issuing the ADD1 command., offset: 0x30 */ - __O uint32_t ADD16; /**< Write address for issuing the ADD16 command., offset: 0x34 */ - __O uint32_t ADD256; /**< Write address for issuing the ADD16 command., offset: 0x38 */ - __O uint32_t SUB; /**< Write address for issuing the SUB command., offset: 0x3C */ - __O uint32_t SUB1; /**< Write address for issuing the SUB1 command., offset: 0x40 */ - __O uint32_t SUB16; /**< Write address for issuing the SUB16 command., offset: 0x44 */ - __O uint32_t SUB256; /**< Write address for issuing the SUB256 command., offset: 0x48 */ -} CDOG_Type; - -/* ---------------------------------------------------------------------------- - -- CDOG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CDOG_Register_Masks CDOG Register Masks - * @{ - */ - -/*! @name CONTROL - The control fields, which constitute CONTROL, control all controllable attributes of the module, including those of CONTROL itself. */ -/*! @{ */ - -#define CDOG_CONTROL_LOCK_CTRL_MASK (0x3U) -#define CDOG_CONTROL_LOCK_CTRL_SHIFT (0U) -/*! LOCK_CTRL - Lock control field - */ -#define CDOG_CONTROL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK) - -#define CDOG_CONTROL_TIMEOUT_CTRL_MASK (0x1CU) -#define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT (2U) -/*! TIMEOUT_CTRL - TIMEOUT control - */ -#define CDOG_CONTROL_TIMEOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK) - -#define CDOG_CONTROL_MISCOMPARE_CTRL_MASK (0xE0U) -#define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT (5U) -/*! MISCOMPARE_CTRL - MISCOMPARE control field - */ -#define CDOG_CONTROL_MISCOMPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK) - -#define CDOG_CONTROL_SEQUENCE_CTRL_MASK (0x700U) -#define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT (8U) -/*! SEQUENCE_CTRL - SEQUENCE control field - */ -#define CDOG_CONTROL_SEQUENCE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK) - -#define CDOG_CONTROL_CONTROL_CTRL_MASK (0x3800U) -#define CDOG_CONTROL_CONTROL_CTRL_SHIFT (11U) -/*! CONTROL_CTRL - CONTROL control field - */ -#define CDOG_CONTROL_CONTROL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_CONTROL_CTRL_SHIFT)) & CDOG_CONTROL_CONTROL_CTRL_MASK) - -#define CDOG_CONTROL_STATE_CTRL_MASK (0x1C000U) -#define CDOG_CONTROL_STATE_CTRL_SHIFT (14U) -/*! STATE_CTRL - STATE control field - */ -#define CDOG_CONTROL_STATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK) - -#define CDOG_CONTROL_ADDRESS_CTRL_MASK (0xE0000U) -#define CDOG_CONTROL_ADDRESS_CTRL_SHIFT (17U) -/*! ADDRESS_CTRL - ADDRESS control field - */ -#define CDOG_CONTROL_ADDRESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK) - -#define CDOG_CONTROL_Un_Imps_MASK (0xFF00000U) -#define CDOG_CONTROL_Un_Imps_SHIFT (20U) -/*! Un_Imps - The un-imps are un-IMPs! - */ -#define CDOG_CONTROL_Un_Imps(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_Un_Imps_SHIFT)) & CDOG_CONTROL_Un_Imps_MASK) - -#define CDOG_CONTROL_IRQ_PAUSE_MASK (0x30000000U) -#define CDOG_CONTROL_IRQ_PAUSE_SHIFT (28U) -/*! IRQ_PAUSE - IRQ pause control field - */ -#define CDOG_CONTROL_IRQ_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK) - -#define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK (0xC0000000U) -#define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT (30U) -/*! DEBUG_HALT_CTRL - DEBUG_HALT control field - */ -#define CDOG_CONTROL_DEBUG_HALT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK) -/*! @} */ - -/*! @name RELOAD - Instruction timer reload */ -/*! @{ */ - -#define CDOG_RELOAD_RLOAD_MASK (0xFFFFFFFFU) -#define CDOG_RELOAD_RLOAD_SHIFT (0U) -/*! RLOAD - Inst. Timer reload value - */ -#define CDOG_RELOAD_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK) -/*! @} */ - -/*! @name INSTRUCTION_TIMER - The INSTRUCTION TIMER itself */ -/*! @{ */ - -#define CDOG_INSTRUCTION_TIMER_INSTIM_MASK (0xFFFFFFFFU) -#define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT (0U) -/*! INSTIM - INSTRUCTION TIMER 32-bit value - */ -#define CDOG_INSTRUCTION_TIMER_INSTIM(x) (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK) -/*! @} */ - -/*! @name SECURE_COUNTER - Also known as SEC_CNT */ -/*! @{ */ - -#define CDOG_SECURE_COUNTER_SECCNT_MASK (0xFFFFFFFFU) -#define CDOG_SECURE_COUNTER_SECCNT_SHIFT (0U) -/*! SECCNT - Secure Counter - */ -#define CDOG_SECURE_COUNTER_SECCNT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SECURE_COUNTER_SECCNT_SHIFT)) & CDOG_SECURE_COUNTER_SECCNT_MASK) -/*! @} */ - -/*! @name STATUS - Status register (1 of 2) */ -/*! @{ */ - -#define CDOG_STATUS_NUMTOF_MASK (0xFFU) -#define CDOG_STATUS_NUMTOF_SHIFT (0U) -/*! NUMTOF - Number of Timeout Faults - */ -#define CDOG_STATUS_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK) - -#define CDOG_STATUS_NUMMISCOMPF_MASK (0xFF00U) -#define CDOG_STATUS_NUMMISCOMPF_SHIFT (8U) -/*! NUMMISCOMPF - Number of Miscompare Faults - */ -#define CDOG_STATUS_NUMMISCOMPF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK) - -#define CDOG_STATUS_NUMILSEQF_MASK (0xFF0000U) -#define CDOG_STATUS_NUMILSEQF_SHIFT (16U) -/*! NUMILSEQF - Number of illegal sequence faults - */ -#define CDOG_STATUS_NUMILSEQF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK) - -#define CDOG_STATUS_CURST_MASK (0xF000000U) -#define CDOG_STATUS_CURST_SHIFT (24U) -/*! CURST - Current State - */ -#define CDOG_STATUS_CURST(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK) - -#define CDOG_STATUS_uN_iMps_MASK (0xF0000000U) -#define CDOG_STATUS_uN_iMps_SHIFT (28U) -/*! uN_iMps - Un implemented - */ -#define CDOG_STATUS_uN_iMps(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_uN_iMps_SHIFT)) & CDOG_STATUS_uN_iMps_MASK) -/*! @} */ - -/*! @name STATUS2 - STATUS register (2 of 2) */ -/*! @{ */ - -#define CDOG_STATUS2_NUMCNTF_MASK (0xFFU) -#define CDOG_STATUS2_NUMCNTF_SHIFT (0U) -/*! NUMCNTF - Number (of) control faults - */ -#define CDOG_STATUS2_NUMCNTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK) - -#define CDOG_STATUS2_NUMILLSTF_MASK (0xFF00U) -#define CDOG_STATUS2_NUMILLSTF_SHIFT (8U) -/*! NUMILLSTF - Number (of) state faults - */ -#define CDOG_STATUS2_NUMILLSTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK) - -#define CDOG_STATUS2_NUMILLA_MASK (0xFF0000U) -#define CDOG_STATUS2_NUMILLA_SHIFT (16U) -/*! NUMILLA - Number of (illegal) address faults - */ -#define CDOG_STATUS2_NUMILLA(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK) - -#define CDOG_STATUS2_un_imPs_MASK (0xFF000000U) -#define CDOG_STATUS2_un_imPs_SHIFT (24U) -/*! un_imPs - Unimplemented bits, such as these here, aren't there. - */ -#define CDOG_STATUS2_un_imPs(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_un_imPs_SHIFT)) & CDOG_STATUS2_un_imPs_MASK) -/*! @} */ - -/*! @name FLAGS - Hardware flags */ -/*! @{ */ - -#define CDOG_FLAGS_TO_FLAG_MASK (0x1U) -#define CDOG_FLAGS_TO_FLAG_SHIFT (0U) -/*! TO_FLAG - Timeout flag - */ -#define CDOG_FLAGS_TO_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK) - -#define CDOG_FLAGS_MISCOM_FLAG_MASK (0x2U) -#define CDOG_FLAGS_MISCOM_FLAG_SHIFT (1U) -/*! MISCOM_FLAG - Miscompare flag - */ -#define CDOG_FLAGS_MISCOM_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK) - -#define CDOG_FLAGS_SEQ_FLAG_MASK (0x4U) -#define CDOG_FLAGS_SEQ_FLAG_SHIFT (2U) -/*! SEQ_FLAG - Sequence flag - */ -#define CDOG_FLAGS_SEQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK) - -#define CDOG_FLAGS_CNT_FLAG_MASK (0x8U) -#define CDOG_FLAGS_CNT_FLAG_SHIFT (3U) -/*! CNT_FLAG - Control (fault) flag - */ -#define CDOG_FLAGS_CNT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK) - -#define CDOG_FLAGS_STATE_FLAG_MASK (0x10U) -#define CDOG_FLAGS_STATE_FLAG_SHIFT (4U) -/*! STATE_FLAG - State flag - */ -#define CDOG_FLAGS_STATE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK) - -#define CDOG_FLAGS_ADDR_FLAG_MASK (0x20U) -#define CDOG_FLAGS_ADDR_FLAG_SHIFT (5U) -/*! ADDR_FLAG - Address flag - */ -#define CDOG_FLAGS_ADDR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK) - -#define CDOG_FLAGS_POR_FLAG_MASK (0x10000U) -#define CDOG_FLAGS_POR_FLAG_SHIFT (16U) -/*! POR_FLAG - Power-on reset flag - */ -#define CDOG_FLAGS_POR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK) -/*! @} */ - -/*! @name PERSISTENT - Persistent (Ad. Hoc., quasi-NV) data storage */ -/*! @{ */ - -#define CDOG_PERSISTENT_PERSIS_MASK (0xFFFFFFFFU) -#define CDOG_PERSISTENT_PERSIS_SHIFT (0U) -/*! PERSIS - 32 regs free for user SW to enjoy - */ -#define CDOG_PERSISTENT_PERSIS(x) (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK) -/*! @} */ - -/*! @name START - Write address for issuing the START command. */ -/*! @{ */ - -#define CDOG_START_STRT_MASK (0xFFFFFFFFU) -#define CDOG_START_STRT_SHIFT (0U) -/*! STRT - Address of start command access - */ -#define CDOG_START_STRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK) -/*! @} */ - -/*! @name STOP - Write address for issuing the STOP command. */ -/*! @{ */ - -#define CDOG_STOP_STP_MASK (0xFFFFFFFFU) -#define CDOG_STOP_STP_SHIFT (0U) -/*! STP - Address of stop command access - */ -#define CDOG_STOP_STP(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK) -/*! @} */ - -/*! @name RESTART - Write address for issuing the RESTART command. */ -/*! @{ */ - -#define CDOG_RESTART_RSTRT_MASK (0xFFFFFFFFU) -#define CDOG_RESTART_RSTRT_SHIFT (0U) -/*! RSTRT - Write address for issuing the RESTART command. - */ -#define CDOG_RESTART_RSTRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK) -/*! @} */ - -/*! @name ADD - Write address for issuing the ADD command. */ -/*! @{ */ - -#define CDOG_ADD_AD_MASK (0xFFFFFFFFU) -#define CDOG_ADD_AD_SHIFT (0U) -/*! AD - Address of ADD command - */ -#define CDOG_ADD_AD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK) -/*! @} */ - -/*! @name ADD1 - Write address for issuing the ADD1 command. */ -/*! @{ */ - -#define CDOG_ADD1_AD1_MASK (0xFFFFFFFFU) -#define CDOG_ADD1_AD1_SHIFT (0U) -/*! AD1 - Address of ADD1 command. - */ -#define CDOG_ADD1_AD1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK) -/*! @} */ - -/*! @name ADD16 - Write address for issuing the ADD16 command. */ -/*! @{ */ - -#define CDOG_ADD16_AD16_MASK (0xFFFFFFFFU) -#define CDOG_ADD16_AD16_SHIFT (0U) -/*! AD16 - Address of ADD16 - */ -#define CDOG_ADD16_AD16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK) -/*! @} */ - -/*! @name ADD256 - Write address for issuing the ADD16 command. */ -/*! @{ */ - -#define CDOG_ADD256_AD256_MASK (0xFFFFFFFFU) -#define CDOG_ADD256_AD256_SHIFT (0U) -/*! AD256 - Address of ADD256 command - */ -#define CDOG_ADD256_AD256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK) -/*! @} */ - -/*! @name SUB - Write address for issuing the SUB command. */ -/*! @{ */ - -#define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) -#define CDOG_SUB_S0B_SHIFT (0U) -/*! S0B - Address of SUB command. - */ -#define CDOG_SUB_S0B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK) -/*! @} */ - -/*! @name SUB1 - Write address for issuing the SUB1 command. */ -/*! @{ */ - -#define CDOG_SUB1_S1B_MASK (0xFFFFFFFFU) -#define CDOG_SUB1_S1B_SHIFT (0U) -/*! S1B - Address of SUB1 command. - */ -#define CDOG_SUB1_S1B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_S1B_SHIFT)) & CDOG_SUB1_S1B_MASK) -/*! @} */ - -/*! @name SUB16 - Write address for issuing the SUB16 command. */ -/*! @{ */ - -#define CDOG_SUB16_SB16_MASK (0xFFFFFFFFU) -#define CDOG_SUB16_SB16_SHIFT (0U) -/*! SB16 - Address of SUB16 command. - */ -#define CDOG_SUB16_SB16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK) -/*! @} */ - -/*! @name SUB256 - Write address for issuing the SUB256 command. */ -/*! @{ */ - -#define CDOG_SUB256_SB256_MASK (0xFFFFFFFFU) -#define CDOG_SUB256_SB256_SHIFT (0U) -/*! SB256 - Address of (you guessed it) SUB256 command. - */ -#define CDOG_SUB256_SB256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CDOG_Register_Masks */ - - -/* CDOG - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CDOG base address */ - #define CDOG_BASE (0x500A1000u) - /** Peripheral CDOG base address */ - #define CDOG_BASE_NS (0x400A1000u) - /** Peripheral CDOG base pointer */ - #define CDOG ((CDOG_Type *)CDOG_BASE) - /** Peripheral CDOG base pointer */ - #define CDOG_NS ((CDOG_Type *)CDOG_BASE_NS) - /** Array initializer of CDOG peripheral base addresses */ - #define CDOG_BASE_ADDRS { CDOG_BASE } - /** Array initializer of CDOG peripheral base pointers */ - #define CDOG_BASE_PTRS { CDOG } - /** Array initializer of CDOG peripheral base addresses */ - #define CDOG_BASE_ADDRS_NS { CDOG_BASE_NS } - /** Array initializer of CDOG peripheral base pointers */ - #define CDOG_BASE_PTRS_NS { CDOG_NS } -#else - /** Peripheral CDOG base address */ - #define CDOG_BASE (0x400A1000u) - /** Peripheral CDOG base pointer */ - #define CDOG ((CDOG_Type *)CDOG_BASE) - /** Array initializer of CDOG peripheral base addresses */ - #define CDOG_BASE_ADDRS { CDOG_BASE } - /** Array initializer of CDOG peripheral base pointers */ - #define CDOG_BASE_PTRS { CDOG } -#endif -/** Interrupt vectors for the CDOG peripheral type */ -#define CDOG_IRQS { CDOG_IRQn } - -/*! - * @} - */ /* end of group CDOG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CRC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer - * @{ - */ - -/** CRC - Register Layout Typedef */ -typedef struct { - __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ - __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ - union { /* offset: 0x8 */ - __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ - __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ - }; -} CRC_Type; - -/* ---------------------------------------------------------------------------- - -- CRC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Register_Masks CRC Register Masks - * @{ - */ - -/*! @name MODE - CRC mode register */ -/*! @{ */ - -#define CRC_MODE_CRC_POLY_MASK (0x3U) -#define CRC_MODE_CRC_POLY_SHIFT (0U) -/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial - */ -#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) - -#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) -#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) -/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) - */ -#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) - -#define CRC_MODE_CMPL_WR_MASK (0x8U) -#define CRC_MODE_CMPL_WR_SHIFT (3U) -/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA - */ -#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) - -#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) -#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) -/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM - */ -#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) - -#define CRC_MODE_CMPL_SUM_MASK (0x20U) -#define CRC_MODE_CMPL_SUM_SHIFT (5U) -/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM - */ -#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) -/*! @} */ - -/*! @name SEED - CRC seed register */ -/*! @{ */ - -#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) -#define CRC_SEED_CRC_SEED_SHIFT (0U) -/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with - * selected bit order and 1's complement pre-processes. A write access to this register will - * overrule the CRC calculation in progresses. - */ -#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) -/*! @} */ - -/*! @name SUM - CRC checksum register */ -/*! @{ */ - -#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) -#define CRC_SUM_CRC_SUM_SHIFT (0U) -/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. - */ -#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) -/*! @} */ - -/*! @name WR_DATA - CRC data register */ -/*! @{ */ - -#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) -#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) -/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with - * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and - * accept back-to-back transactions. - */ -#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CRC_Register_Masks */ - - -/* CRC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CRC_ENGINE base address */ - #define CRC_ENGINE_BASE (0x50095000u) - /** Peripheral CRC_ENGINE base address */ - #define CRC_ENGINE_BASE_NS (0x40095000u) - /** Peripheral CRC_ENGINE base pointer */ - #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) - /** Peripheral CRC_ENGINE base pointer */ - #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS) - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS { CRC_ENGINE } - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS } -#else - /** Peripheral CRC_ENGINE base address */ - #define CRC_ENGINE_BASE (0x40095000u) - /** Peripheral CRC_ENGINE base pointer */ - #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS { CRC_ENGINE } -#endif - -/*! - * @} - */ /* end of group CRC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CTIMER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer - * @{ - */ - -/** CTIMER - Register Layout Typedef */ -typedef struct { - __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ - __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ - __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ - __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ - __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ - __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ - __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ - __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ - __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ - __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ - uint8_t RESERVED_0[48]; - __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ - __IO uint32_t PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */ - __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ -} CTIMER_Type; - -/* ---------------------------------------------------------------------------- - -- CTIMER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Register_Masks CTIMER Register Masks - * @{ - */ - -/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ -/*! @{ */ - -#define CTIMER_IR_MR0INT_MASK (0x1U) -#define CTIMER_IR_MR0INT_SHIFT (0U) -/*! MR0INT - Interrupt flag for match channel 0. - */ -#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) - -#define CTIMER_IR_MR1INT_MASK (0x2U) -#define CTIMER_IR_MR1INT_SHIFT (1U) -/*! MR1INT - Interrupt flag for match channel 1. - */ -#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) - -#define CTIMER_IR_MR2INT_MASK (0x4U) -#define CTIMER_IR_MR2INT_SHIFT (2U) -/*! MR2INT - Interrupt flag for match channel 2. - */ -#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) - -#define CTIMER_IR_MR3INT_MASK (0x8U) -#define CTIMER_IR_MR3INT_SHIFT (3U) -/*! MR3INT - Interrupt flag for match channel 3. - */ -#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) - -#define CTIMER_IR_CR0INT_MASK (0x10U) -#define CTIMER_IR_CR0INT_SHIFT (4U) -/*! CR0INT - Interrupt flag for capture channel 0 event. - */ -#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) - -#define CTIMER_IR_CR1INT_MASK (0x20U) -#define CTIMER_IR_CR1INT_SHIFT (5U) -/*! CR1INT - Interrupt flag for capture channel 1 event. - */ -#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) - -#define CTIMER_IR_CR2INT_MASK (0x40U) -#define CTIMER_IR_CR2INT_SHIFT (6U) -/*! CR2INT - Interrupt flag for capture channel 2 event. - */ -#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) - -#define CTIMER_IR_CR3INT_MASK (0x80U) -#define CTIMER_IR_CR3INT_SHIFT (7U) -/*! CR3INT - Interrupt flag for capture channel 3 event. - */ -#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) -/*! @} */ - -/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ -/*! @{ */ - -#define CTIMER_TCR_CEN_MASK (0x1U) -#define CTIMER_TCR_CEN_SHIFT (0U) -/*! CEN - Counter enable. - * 0b0..Disabled.The counters are disabled. - * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. - */ -#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) - -#define CTIMER_TCR_CRST_MASK (0x2U) -#define CTIMER_TCR_CRST_SHIFT (1U) -/*! CRST - Counter reset. - * 0b0..Disabled. Do nothing. - * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of - * the APB bus clock. The counters remain reset until TCR[1] is returned to zero. - */ -#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) -/*! @} */ - -/*! @name TC - Timer Counter */ -/*! @{ */ - -#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_TC_TCVAL_SHIFT (0U) -/*! TCVAL - Timer counter value. - */ -#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) -/*! @} */ - -/*! @name PR - Prescale Register */ -/*! @{ */ - -#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PR_PRVAL_SHIFT (0U) -/*! PRVAL - Prescale counter value. - */ -#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) -/*! @} */ - -/*! @name PC - Prescale Counter */ -/*! @{ */ - -#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PC_PCVAL_SHIFT (0U) -/*! PCVAL - Prescale counter value. - */ -#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) -/*! @} */ - -/*! @name MCR - Match Control Register */ -/*! @{ */ - -#define CTIMER_MCR_MR0I_MASK (0x1U) -#define CTIMER_MCR_MR0I_SHIFT (0U) -/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. - */ -#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) - -#define CTIMER_MCR_MR0R_MASK (0x2U) -#define CTIMER_MCR_MR0R_SHIFT (1U) -/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. - */ -#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) - -#define CTIMER_MCR_MR0S_MASK (0x4U) -#define CTIMER_MCR_MR0S_SHIFT (2U) -/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. - */ -#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) - -#define CTIMER_MCR_MR1I_MASK (0x8U) -#define CTIMER_MCR_MR1I_SHIFT (3U) -/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. - */ -#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) - -#define CTIMER_MCR_MR1R_MASK (0x10U) -#define CTIMER_MCR_MR1R_SHIFT (4U) -/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. - */ -#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) - -#define CTIMER_MCR_MR1S_MASK (0x20U) -#define CTIMER_MCR_MR1S_SHIFT (5U) -/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. - */ -#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) - -#define CTIMER_MCR_MR2I_MASK (0x40U) -#define CTIMER_MCR_MR2I_SHIFT (6U) -/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. - */ -#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) - -#define CTIMER_MCR_MR2R_MASK (0x80U) -#define CTIMER_MCR_MR2R_SHIFT (7U) -/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. - */ -#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) - -#define CTIMER_MCR_MR2S_MASK (0x100U) -#define CTIMER_MCR_MR2S_SHIFT (8U) -/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. - */ -#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) - -#define CTIMER_MCR_MR3I_MASK (0x200U) -#define CTIMER_MCR_MR3I_SHIFT (9U) -/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. - */ -#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) - -#define CTIMER_MCR_MR3R_MASK (0x400U) -#define CTIMER_MCR_MR3R_SHIFT (10U) -/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it. - */ -#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) - -#define CTIMER_MCR_MR3S_MASK (0x800U) -#define CTIMER_MCR_MR3S_SHIFT (11U) -/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. - */ -#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) - -#define CTIMER_MCR_MR0RL_MASK (0x1000000U) -#define CTIMER_MCR_MR0RL_SHIFT (24U) -/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero - * (either via a match event or a write to bit 1 of the TCR). - */ -#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) - -#define CTIMER_MCR_MR1RL_MASK (0x2000000U) -#define CTIMER_MCR_MR1RL_SHIFT (25U) -/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero - * (either via a match event or a write to bit 1 of the TCR). - */ -#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) - -#define CTIMER_MCR_MR2RL_MASK (0x4000000U) -#define CTIMER_MCR_MR2RL_SHIFT (26U) -/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero - * (either via a match event or a write to bit 1 of the TCR). - */ -#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) - -#define CTIMER_MCR_MR3RL_MASK (0x8000000U) -#define CTIMER_MCR_MR3RL_SHIFT (27U) -/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero - * (either via a match event or a write to bit 1 of the TCR). - */ -#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) -/*! @} */ - -/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ -/*! @{ */ - -#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) -#define CTIMER_MR_MATCH_SHIFT (0U) -/*! MATCH - Timer counter match value. - */ -#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) -/*! @} */ - -/* The count of CTIMER_MR */ -#define CTIMER_MR_COUNT (4U) - -/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ -/*! @{ */ - -#define CTIMER_CCR_CAP0RE_MASK (0x1U) -#define CTIMER_CCR_CAP0RE_SHIFT (0U) -/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) - -#define CTIMER_CCR_CAP0FE_MASK (0x2U) -#define CTIMER_CCR_CAP0FE_SHIFT (1U) -/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) - -#define CTIMER_CCR_CAP0I_MASK (0x4U) -#define CTIMER_CCR_CAP0I_SHIFT (2U) -/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. - */ -#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) - -#define CTIMER_CCR_CAP1RE_MASK (0x8U) -#define CTIMER_CCR_CAP1RE_SHIFT (3U) -/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) - -#define CTIMER_CCR_CAP1FE_MASK (0x10U) -#define CTIMER_CCR_CAP1FE_SHIFT (4U) -/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) - -#define CTIMER_CCR_CAP1I_MASK (0x20U) -#define CTIMER_CCR_CAP1I_SHIFT (5U) -/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. - */ -#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) - -#define CTIMER_CCR_CAP2RE_MASK (0x40U) -#define CTIMER_CCR_CAP2RE_SHIFT (6U) -/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) - -#define CTIMER_CCR_CAP2FE_MASK (0x80U) -#define CTIMER_CCR_CAP2FE_SHIFT (7U) -/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) - -#define CTIMER_CCR_CAP2I_MASK (0x100U) -#define CTIMER_CCR_CAP2I_SHIFT (8U) -/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. - */ -#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) - -#define CTIMER_CCR_CAP3RE_MASK (0x200U) -#define CTIMER_CCR_CAP3RE_SHIFT (9U) -/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) - -#define CTIMER_CCR_CAP3FE_MASK (0x400U) -#define CTIMER_CCR_CAP3FE_SHIFT (10U) -/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) - -#define CTIMER_CCR_CAP3I_MASK (0x800U) -#define CTIMER_CCR_CAP3I_SHIFT (11U) -/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. - */ -#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) -/*! @} */ - -/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ -/*! @{ */ - -#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) -#define CTIMER_CR_CAP_SHIFT (0U) -/*! CAP - Timer counter capture value. - */ -#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) -/*! @} */ - -/* The count of CTIMER_CR */ -#define CTIMER_CR_COUNT (4U) - -/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ -/*! @{ */ - -#define CTIMER_EMR_EM0_MASK (0x1U) -#define CTIMER_EMR_EM0_SHIFT (0U) -/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output - * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, - * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if - * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - */ -#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) - -#define CTIMER_EMR_EM1_MASK (0x2U) -#define CTIMER_EMR_EM1_SHIFT (1U) -/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output - * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, - * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if - * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - */ -#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) - -#define CTIMER_EMR_EM2_MASK (0x4U) -#define CTIMER_EMR_EM2_SHIFT (2U) -/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output - * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, - * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if - * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - */ -#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) - -#define CTIMER_EMR_EM3_MASK (0x8U) -#define CTIMER_EMR_EM3_SHIFT (3U) -/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output - * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, - * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins - * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - */ -#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) - -#define CTIMER_EMR_EMC0_MASK (0x30U) -#define CTIMER_EMR_EMC0_SHIFT (4U) -/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) - -#define CTIMER_EMR_EMC1_MASK (0xC0U) -#define CTIMER_EMR_EMC1_SHIFT (6U) -/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) - -#define CTIMER_EMR_EMC2_MASK (0x300U) -#define CTIMER_EMR_EMC2_SHIFT (8U) -/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) - -#define CTIMER_EMR_EMC3_MASK (0xC00U) -#define CTIMER_EMR_EMC3_SHIFT (10U) -/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) -/*! @} */ - -/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ -/*! @{ */ - -#define CTIMER_CTCR_CTMODE_MASK (0x3U) -#define CTIMER_CTCR_CTMODE_SHIFT (0U) -/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment - * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC - * is incremented when the Prescale Counter matches the Prescale Register. - * 0b00..Timer Mode. Incremented every rising APB bus clock edge. - * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. - * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. - * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. - */ -#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) - -#define CTIMER_CTCR_CINSEL_MASK (0xCU) -#define CTIMER_CTCR_CINSEL_SHIFT (2U) -/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which - * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input - * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be - * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the - * same timer. - * 0b00..Channel 0. CAPn.0 for CTIMERn - * 0b01..Channel 1. CAPn.1 for CTIMERn - * 0b10..Channel 2. CAPn.2 for CTIMERn - * 0b11..Channel 3. CAPn.3 for CTIMERn - */ -#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) - -#define CTIMER_CTCR_ENCC_MASK (0x10U) -#define CTIMER_CTCR_ENCC_SHIFT (4U) -/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the - * capture-edge event specified in bits 7:5 occurs. - */ -#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) - -#define CTIMER_CTCR_SELCC_MASK (0xE0U) -#define CTIMER_CTCR_SELCC_SHIFT (5U) -/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the - * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to - * 0x3 and 0x6 to 0x7 are reserved. - * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - */ -#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) -/*! @} */ - -/*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */ -/*! @{ */ - -#define CTIMER_PWMC_PWMEN0_MASK (0x1U) -#define CTIMER_PWMC_PWMEN0_SHIFT (0U) -/*! PWMEN0 - PWM mode enable for channel0. - * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. - */ -#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) - -#define CTIMER_PWMC_PWMEN1_MASK (0x2U) -#define CTIMER_PWMC_PWMEN1_SHIFT (1U) -/*! PWMEN1 - PWM mode enable for channel1. - * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. - */ -#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) - -#define CTIMER_PWMC_PWMEN2_MASK (0x4U) -#define CTIMER_PWMC_PWMEN2_SHIFT (2U) -/*! PWMEN2 - PWM mode enable for channel2. - * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. - */ -#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) - -#define CTIMER_PWMC_PWMEN3_MASK (0x8U) -#define CTIMER_PWMC_PWMEN3_SHIFT (3U) -/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. - * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. - * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. - */ -#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) -/*! @} */ - -/*! @name MSR - Match Shadow Register */ -/*! @{ */ - -#define CTIMER_MSR_SHADOW_MASK (0xFFFFFFFFU) -#define CTIMER_MSR_SHADOW_SHIFT (0U) -/*! SHADOW - Timer counter match shadow value. - */ -#define CTIMER_MSR_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOW_SHIFT)) & CTIMER_MSR_SHADOW_MASK) -/*! @} */ - -/* The count of CTIMER_MSR */ -#define CTIMER_MSR_COUNT (4U) - - -/*! - * @} - */ /* end of group CTIMER_Register_Masks */ - - -/* CTIMER - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE (0x50008000u) - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE_NS (0x40008000u) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE (0x50009000u) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE_NS (0x40009000u) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE (0x50028000u) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE_NS (0x40028000u) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE (0x50029000u) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE_NS (0x40029000u) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE (0x5002A000u) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE_NS (0x4002A000u) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } -#else - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE (0x40008000u) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE (0x40009000u) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE (0x40028000u) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE (0x40029000u) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE (0x4002A000u) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } -#endif -/** Interrupt vectors for the CTIMER peripheral type */ -#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } - -/*! - * @} - */ /* end of group CTIMER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DBGMAILBOX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DBGMAILBOX_Peripheral_Access_Layer DBGMAILBOX Peripheral Access Layer - * @{ - */ - -/** DBGMAILBOX - Register Layout Typedef */ -typedef struct { - __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */ - __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */ - __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */ - uint8_t RESERVED_0[240]; - __I uint32_t ID; /**< Identification register, offset: 0xFC */ -} DBGMAILBOX_Type; - -/* ---------------------------------------------------------------------------- - -- DBGMAILBOX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DBGMAILBOX_Register_Masks DBGMAILBOX Register Masks - * @{ - */ - -/*! @name CSW - CRC mode register */ -/*! @{ */ - -#define DBGMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) -#define DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) -/*! RESYNCH_REQ - Debugger will set this bit to 1 to request a resynchronrisation - */ -#define DBGMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DBGMAILBOX_CSW_RESYNCH_REQ_MASK) - -#define DBGMAILBOX_CSW_REQ_PENDING_MASK (0x2U) -#define DBGMAILBOX_CSW_REQ_PENDING_SHIFT (1U) -/*! REQ_PENDING - Request is pending from debugger (i.e unread value in REQUEST) - */ -#define DBGMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DBGMAILBOX_CSW_REQ_PENDING_MASK) - -#define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) -#define DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) -/*! DBG_OR_ERR - Debugger overrun error (previous REQUEST overwritten before being picked up by ROM) - */ -#define DBGMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK) - -#define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) -#define DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) -/*! AHB_OR_ERR - AHB overrun Error (Return value overwritten by ROM) - */ -#define DBGMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK) - -#define DBGMAILBOX_CSW_SOFT_RESET_MASK (0x10U) -#define DBGMAILBOX_CSW_SOFT_RESET_SHIFT (4U) -/*! SOFT_RESET - Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to - * this bit will cause a soft reset for DM. - */ -#define DBGMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DBGMAILBOX_CSW_SOFT_RESET_MASK) - -#define DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) -#define DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) -/*! CHIP_RESET_REQ - Write only bit. Once written will cause the chip to reset (note that the DM is - * not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event) - */ -#define DBGMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK) -/*! @} */ - -/*! @name REQUEST - CRC seed register */ -/*! @{ */ - -#define DBGMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU) -#define DBGMAILBOX_REQUEST_REQ_SHIFT (0U) -/*! REQ - Request Value - */ -#define DBGMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_REQUEST_REQ_SHIFT)) & DBGMAILBOX_REQUEST_REQ_MASK) -/*! @} */ - -/*! @name RETURN - Return value from ROM. */ -/*! @{ */ - -#define DBGMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) -#define DBGMAILBOX_RETURN_RET_SHIFT (0U) -/*! RET - The Return value from ROM. - */ -#define DBGMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_RETURN_RET_SHIFT)) & DBGMAILBOX_RETURN_RET_MASK) -/*! @} */ - -/*! @name ID - Identification register */ -/*! @{ */ - -#define DBGMAILBOX_ID_ID_MASK (0xFFFFFFFFU) -#define DBGMAILBOX_ID_ID_SHIFT (0U) -/*! ID - Identification value. - */ -#define DBGMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_ID_ID_SHIFT)) & DBGMAILBOX_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group DBGMAILBOX_Register_Masks */ - - -/* DBGMAILBOX - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral DBGMAILBOX base address */ - #define DBGMAILBOX_BASE (0x5009C000u) - /** Peripheral DBGMAILBOX base address */ - #define DBGMAILBOX_BASE_NS (0x4009C000u) - /** Peripheral DBGMAILBOX base pointer */ - #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) - /** Peripheral DBGMAILBOX base pointer */ - #define DBGMAILBOX_NS ((DBGMAILBOX_Type *)DBGMAILBOX_BASE_NS) - /** Array initializer of DBGMAILBOX peripheral base addresses */ - #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } - /** Array initializer of DBGMAILBOX peripheral base pointers */ - #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } - /** Array initializer of DBGMAILBOX peripheral base addresses */ - #define DBGMAILBOX_BASE_ADDRS_NS { DBGMAILBOX_BASE_NS } - /** Array initializer of DBGMAILBOX peripheral base pointers */ - #define DBGMAILBOX_BASE_PTRS_NS { DBGMAILBOX_NS } -#else - /** Peripheral DBGMAILBOX base address */ - #define DBGMAILBOX_BASE (0x4009C000u) - /** Peripheral DBGMAILBOX base pointer */ - #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) - /** Array initializer of DBGMAILBOX peripheral base addresses */ - #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } - /** Array initializer of DBGMAILBOX peripheral base pointers */ - #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } -#endif - -/*! - * @} - */ /* end of group DBGMAILBOX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer - * @{ - */ - -/** DMA - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ - __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ - __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ - uint8_t RESERVED_0[20]; - struct { /* offset: 0x20, array step: 0x5C */ - __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ - uint8_t RESERVED_0[4]; - __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ - uint8_t RESERVED_1[4]; - __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ - uint8_t RESERVED_2[4]; - __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ - uint8_t RESERVED_3[4]; - __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ - uint8_t RESERVED_4[4]; - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ - uint8_t RESERVED_5[4]; - __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ - uint8_t RESERVED_6[4]; - __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ - uint8_t RESERVED_7[4]; - __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ - uint8_t RESERVED_8[4]; - __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ - uint8_t RESERVED_9[4]; - __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ - uint8_t RESERVED_10[4]; - __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ - } COMMON[1]; - uint8_t RESERVED_1[900]; - struct { /* offset: 0x400, array step: 0x10 */ - __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ - __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ - __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } CHANNEL[23]; -} DMA_Type; - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/*! @name CTRL - DMA control. */ -/*! @{ */ - -#define DMA_CTRL_ENABLE_MASK (0x1U) -#define DMA_CTRL_ENABLE_SHIFT (0U) -/*! ENABLE - DMA controller master enable. - * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when - * disabled, but does not prevent re-triggering when the DMA controller is re-enabled. - * 0b1..Enabled. The DMA controller is enabled. - */ -#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status. */ -/*! @{ */ - -#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) -#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) -/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. - * 0b0..Not pending. No enabled interrupts are pending. - * 0b1..Pending. At least one enabled interrupt is pending. - */ -#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) - -#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) -#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) -/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. - * 0b0..Not pending. No error interrupts are pending. - * 0b1..Pending. At least one error interrupt is pending. - */ -#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) -/*! @} */ - -/*! @name SRAMBASE - SRAM address of the channel configuration table. */ -/*! @{ */ - -#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) -#define DMA_SRAMBASE_OFFSET_SHIFT (9U) -/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the - * table must begin on a 512 byte boundary. - */ -#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) -/*! @} */ - -/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) -/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = - * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. - */ -#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLESET */ -#define DMA_COMMON_ENABLESET_COUNT (1U) - -/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) -/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears - * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits - * are reserved. - */ -#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLECLR */ -#define DMA_COMMON_ENABLECLR_COUNT (1U) - -/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) -/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = - * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. - */ -#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ACTIVE */ -#define DMA_COMMON_ACTIVE_COUNT (1U) - -/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) -#define DMA_COMMON_BUSY_BSY_SHIFT (0U) -/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = - * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. - */ -#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) -/*! @} */ - -/* The count of DMA_COMMON_BUSY */ -#define DMA_COMMON_BUSY_COUNT (1U) - -/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) -/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of - * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is - * not active. 1 = error interrupt is active. - */ -#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ERRINT */ -#define DMA_COMMON_ERRINT_COUNT (1U) - -/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) -/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The - * number of bits = number of DMA channels in this device. Other bits are reserved. 0 = - * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENSET */ -#define DMA_COMMON_INTENSET_COUNT (1U) - -/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) -/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n - * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are - * reserved. - */ -#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENCLR */ -#define DMA_COMMON_INTENCLR_COUNT (1U) - -/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTA_IA_SHIFT (0U) -/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of - * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel - * interrupt A is not active. 1 = the DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTA */ -#define DMA_COMMON_INTA_COUNT (1U) - -/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTB_IB_SHIFT (0U) -/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of - * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel - * interrupt B is not active. 1 = the DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTB */ -#define DMA_COMMON_INTB_COUNT (1U) - -/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETVALID_SV_SHIFT (0U) -/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits - * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the - * VALIDPENDING control bit for DMA channel n - */ -#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETVALID */ -#define DMA_COMMON_SETVALID_COUNT (1U) - -/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) -/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number - * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = - * sets the TRIG bit for DMA channel n. - */ -#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETTRIG */ -#define DMA_COMMON_SETTRIG_COUNT (1U) - -/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) -/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. - * 1 = aborts DMA operations on channel n. - */ -#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ABORT */ -#define DMA_COMMON_ABORT_COUNT (1U) - -/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ -/*! @{ */ - -#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) -#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) -/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory - * move, any peripheral DMA request associated with that channel can be disabled to prevent any - * interaction between the peripheral and the DMA controller. - * 0b0..Disabled. Peripheral DMA requests are disabled. - * 0b1..Enabled. Peripheral DMA requests are enabled. - */ -#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) - -#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) -#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) -/*! HWTRIGEN - Hardware Triggering Enable for this channel. - * 0b0..Disabled. Hardware triggering is not used. - * 0b1..Enabled. Use hardware triggering. - */ -#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) - -#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) -#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) -/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. - * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. - * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. - */ -#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) - -#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) -#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) -/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. - * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. - * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = - * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the - * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger - * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the - * current BURSTPOWER length are completed. - */ -#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) - -#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) -#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) -/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. - * 0b0..Single transfer. Hardware trigger causes a single transfer. - * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a - * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a - * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is - * complete. - */ -#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) - -#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) -#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) -/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when - * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). - * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many - * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that - * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: - * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = - * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The - * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even - * multiple of the burst size. - */ -#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) - -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) -/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is - * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this - * could be used to read several sequential registers from a peripheral for each DMA burst, - * reading the same registers again for each burst. - * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. - * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. - */ -#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) - -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) -/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is - * 'wrapped', meaning that the destination address range for each burst will be the same. As an - * example, this could be used to write several sequential registers to a peripheral for each DMA - * burst, writing the same registers again for each burst. - * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. - * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. - */ -#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) - -#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) -#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) -/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority - * levels are supported: 0x0 = highest priority. 0x7 = lowest priority. - */ -#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CFG */ -#define DMA_CHANNEL_CFG_COUNT (23U) - -/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ -/*! @{ */ - -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) -/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the - * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. - * 0b0..No effect. No effect on DMA operation. - * 0b1..Valid pending. - */ -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) - -#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) -#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) -/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is - * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. - * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. - * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. - */ -#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CTLSTAT */ -#define DMA_CHANNEL_CTLSTAT_COUNT (23U) - -/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ -/*! @{ */ - -#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) -#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) -/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor - * is valid and can potentially be acted upon, if all other activation criteria are fulfilled. - * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. - * 0b1..Valid. The current channel descriptor is considered valid. - */ -#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) - -#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) -#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) -/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current - * descriptor is exhausted. Reloading allows ping-pong and linked transfers. - * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. - * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) - -#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) -#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) -/*! SWTRIG - Software Trigger. - * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by - * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. - * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not - * be used with level triggering when TRIGBURST = 0. - */ -#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) - -#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) -#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) -/*! CLRTRIG - Clear Trigger. - * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. - * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted - */ -#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) - -#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) -#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) -/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between - * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By - * convention, interrupt A may be used when only one interrupt flag is needed. - * 0b0..No effect. - * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) - -#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) -#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) -/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between - * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By - * convention, interrupt A may be used when only one interrupt flag is needed. - * 0b0..No effect. - * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) - -#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) -#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) -/*! WIDTH - Transfer width used for this DMA channel. - * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). - * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). - * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). - * 0b11..Reserved. Reserved setting, do not use. - */ -#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) - -#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) -#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) -/*! SRCINC - Determines whether the source address is incremented for each DMA transfer. - * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. - * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is - * the usual case when the source is memory. - * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. - * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. - */ -#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) - -#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) -#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) -/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. - * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when - * the destination is a peripheral device. - * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. - * This is the usual case when the destination is memory. - * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. - * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. - */ -#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) - -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) -/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes - * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller - * uses this bit field during transfer to count down. Hence, it cannot be used by software to read - * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 - * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of - * 1,024 transfers will be performed. - */ -#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_XFERCFG */ -#define DMA_CHANNEL_XFERCFG_COUNT (23U) - - -/*! - * @} - */ /* end of group DMA_Register_Masks */ - - -/* DMA - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral DMA0 base address */ - #define DMA0_BASE (0x50082000u) - /** Peripheral DMA0 base address */ - #define DMA0_BASE_NS (0x40082000u) - /** Peripheral DMA0 base pointer */ - #define DMA0 ((DMA_Type *)DMA0_BASE) - /** Peripheral DMA0 base pointer */ - #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) - /** Peripheral DMA1 base address */ - #define DMA1_BASE (0x500A7000u) - /** Peripheral DMA1 base address */ - #define DMA1_BASE_NS (0x400A7000u) - /** Peripheral DMA1 base pointer */ - #define DMA1 ((DMA_Type *)DMA1_BASE) - /** Peripheral DMA1 base pointer */ - #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS { DMA0, DMA1 } - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } -#else - /** Peripheral DMA0 base address */ - #define DMA0_BASE (0x40082000u) - /** Peripheral DMA0 base pointer */ - #define DMA0 ((DMA_Type *)DMA0_BASE) - /** Peripheral DMA1 base address */ - #define DMA1_BASE (0x400A7000u) - /** Peripheral DMA1 base pointer */ - #define DMA1 ((DMA_Type *)DMA1_BASE) - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS { DMA0, DMA1 } -#endif -/** Interrupt vectors for the DMA peripheral type */ -#define DMA_IRQS { DMA0_IRQn, DMA1_IRQn } - -/*! - * @} - */ /* end of group DMA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer - * @{ - */ - -/** FLASH - Register Layout Typedef */ -typedef struct { - __O uint32_t CMD; /**< command register, offset: 0x0 */ - __O uint32_t EVENT; /**< event register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */ - __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */ - uint8_t RESERVED_1[104]; - __IO uint32_t DATAW[4]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_2[3912]; - __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */ - __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */ - __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ - __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ - __O uint32_t INT_CLR_STATUS; /**< Clear interrupt status bits, offset: 0xFE8 */ - __O uint32_t INT_SET_STATUS; /**< Set interrupt status bits, offset: 0xFEC */ - uint8_t RESERVED_3[12]; - __I uint32_t MODULE_ID; /**< Controller+Memory module identification, offset: 0xFFC */ -} FLASH_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_Register_Masks FLASH Register Masks - * @{ - */ - -/*! @name CMD - command register */ -/*! @{ */ - -#define FLASH_CMD_CMD_MASK (0xFFFFFFFFU) -#define FLASH_CMD_CMD_SHIFT (0U) -/*! CMD - command register. - */ -#define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK) -/*! @} */ - -/*! @name EVENT - event register */ -/*! @{ */ - -#define FLASH_EVENT_RST_MASK (0x1U) -#define FLASH_EVENT_RST_SHIFT (0U) -/*! RST - When bit is set, the controller and flash are reset. - */ -#define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK) - -#define FLASH_EVENT_WAKEUP_MASK (0x2U) -#define FLASH_EVENT_WAKEUP_SHIFT (1U) -/*! WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active. - */ -#define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK) - -#define FLASH_EVENT_ABORT_MASK (0x4U) -#define FLASH_EVENT_ABORT_SHIFT (2U) -/*! ABORT - When bit is set, a running program/erase command is aborted. - */ -#define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK) -/*! @} */ - -/*! @name STARTA - start (or only) address for next flash command */ -/*! @{ */ - -#define FLASH_STARTA_STARTA_MASK (0x3FFFFU) -#define FLASH_STARTA_STARTA_SHIFT (0U) -/*! STARTA - Address / Start address for commands that take an address (range) as a parameter. - */ -#define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK) -/*! @} */ - -/*! @name STOPA - end address for next flash command, if command operates on address ranges */ -/*! @{ */ - -#define FLASH_STOPA_STOPA_MASK (0x3FFFFU) -#define FLASH_STOPA_STOPA_SHIFT (0U) -/*! STOPA - Stop address for commands that take an address range as a parameter (the word specified - * by STOPA is included in the address range). - */ -#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK) -/*! @} */ - -/*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */ -/*! @{ */ - -#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU) -#define FLASH_DATAW_DATAW_SHIFT (0U) -#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK) -/*! @} */ - -/* The count of FLASH_DATAW */ -#define FLASH_DATAW_COUNT (4U) - -/*! @name INT_CLR_ENABLE - Clear interrupt enable bits */ -/*! @{ */ - -#define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U) -#define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U) -/*! FAIL - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - */ -#define FLASH_INT_CLR_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK) - -#define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U) -#define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U) -/*! ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - */ -#define FLASH_INT_CLR_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK) - -#define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U) -#define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U) -/*! DONE - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - */ -#define FLASH_INT_CLR_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK) - -#define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U) -#define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - */ -#define FLASH_INT_CLR_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_SET_ENABLE - Set interrupt enable bits */ -/*! @{ */ - -#define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U) -#define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U) -/*! FAIL - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - */ -#define FLASH_INT_SET_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK) - -#define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U) -#define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U) -/*! ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - */ -#define FLASH_INT_SET_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK) - -#define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U) -#define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U) -/*! DONE - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - */ -#define FLASH_INT_SET_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK) - -#define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U) -#define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - */ -#define FLASH_INT_SET_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_STATUS - Interrupt status bits */ -/*! @{ */ - -#define FLASH_INT_STATUS_FAIL_MASK (0x1U) -#define FLASH_INT_STATUS_FAIL_SHIFT (0U) -/*! FAIL - This status bit is set if execution of a (legal) command failed. - */ -#define FLASH_INT_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK) - -#define FLASH_INT_STATUS_ERR_MASK (0x2U) -#define FLASH_INT_STATUS_ERR_SHIFT (1U) -/*! ERR - This status bit is set if execution of an illegal command is detected. - */ -#define FLASH_INT_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK) - -#define FLASH_INT_STATUS_DONE_MASK (0x4U) -#define FLASH_INT_STATUS_DONE_SHIFT (2U) -/*! DONE - This status bit is set at the end of command execution. - */ -#define FLASH_INT_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK) - -#define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U) -#define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested - * read, or a speculative read, or reads performed by a controller command), a correctable or - * uncorrectable error is detected by ECC decoding logic. - */ -#define FLASH_INT_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_ENABLE - Interrupt enable bits */ -/*! @{ */ - -#define FLASH_INT_ENABLE_FAIL_MASK (0x1U) -#define FLASH_INT_ENABLE_FAIL_SHIFT (0U) -/*! FAIL - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - */ -#define FLASH_INT_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK) - -#define FLASH_INT_ENABLE_ERR_MASK (0x2U) -#define FLASH_INT_ENABLE_ERR_SHIFT (1U) -/*! ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - */ -#define FLASH_INT_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK) - -#define FLASH_INT_ENABLE_DONE_MASK (0x4U) -#define FLASH_INT_ENABLE_DONE_SHIFT (2U) -/*! DONE - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - */ -#define FLASH_INT_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK) - -#define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U) -#define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - */ -#define FLASH_INT_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_CLR_STATUS - Clear interrupt status bits */ -/*! @{ */ - -#define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U) -#define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U) -/*! FAIL - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - */ -#define FLASH_INT_CLR_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK) - -#define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U) -#define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U) -/*! ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - */ -#define FLASH_INT_CLR_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK) - -#define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U) -#define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U) -/*! DONE - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - */ -#define FLASH_INT_CLR_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK) - -#define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U) -#define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - */ -#define FLASH_INT_CLR_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_SET_STATUS - Set interrupt status bits */ -/*! @{ */ - -#define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U) -#define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U) -/*! FAIL - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - */ -#define FLASH_INT_SET_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK) - -#define FLASH_INT_SET_STATUS_ERR_MASK (0x2U) -#define FLASH_INT_SET_STATUS_ERR_SHIFT (1U) -/*! ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - */ -#define FLASH_INT_SET_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK) - -#define FLASH_INT_SET_STATUS_DONE_MASK (0x4U) -#define FLASH_INT_SET_STATUS_DONE_SHIFT (2U) -/*! DONE - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - */ -#define FLASH_INT_SET_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK) - -#define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U) -#define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - */ -#define FLASH_INT_SET_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK) -/*! @} */ - -/*! @name MODULE_ID - Controller+Memory module identification */ -/*! @{ */ - -#define FLASH_MODULE_ID_APERTURE_MASK (0xFFU) -#define FLASH_MODULE_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture i. - */ -#define FLASH_MODULE_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK) - -#define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U) -#define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision i. - */ -#define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK) - -#define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U) -#define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision i. - */ -#define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK) - -#define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U) -#define FLASH_MODULE_ID_ID_SHIFT (16U) -/*! ID - Identifier. - */ -#define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLASH_Register_Masks */ - - -/* FLASH - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH base address */ - #define FLASH_BASE (0x50034000u) - /** Peripheral FLASH base address */ - #define FLASH_BASE_NS (0x40034000u) - /** Peripheral FLASH base pointer */ - #define FLASH ((FLASH_Type *)FLASH_BASE) - /** Peripheral FLASH base pointer */ - #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS) - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS { FLASH_BASE } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS { FLASH } - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS_NS { FLASH_NS } -#else - /** Peripheral FLASH base address */ - #define FLASH_BASE (0x40034000u) - /** Peripheral FLASH base pointer */ - #define FLASH ((FLASH_Type *)FLASH_BASE) - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS { FLASH_BASE } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS { FLASH } -#endif - -/*! - * @} - */ /* end of group FLASH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_CFPA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CFPA_Peripheral_Access_Layer FLASH_CFPA Peripheral Access Layer - * @{ - */ - -/** FLASH_CFPA - Register Layout Typedef */ -typedef struct { - __IO uint32_t HEADER; /**< , offset: 0x0 */ - __IO uint32_t VERSION; /**< , offset: 0x4 */ - __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */ - __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */ - __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */ - uint8_t RESERVED_0[4]; - __IO uint32_t ROTKH_REVOKE; /**< , offset: 0x18 */ - __IO uint32_t VENDOR_USAGE; /**< , offset: 0x1C */ - __IO uint32_t DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */ - __IO uint32_t DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */ - __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */ - __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */ - union { /* offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< , array offset: 0x30, array step: 0x4 */ - struct { /* offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< , offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< , offset: 0x34 */ - __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< , array offset: 0x38, array step: 0x4 */ - } PRINCE_REGION0_IV_CODE_CORE; - }; - union { /* offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< , array offset: 0x68, array step: 0x4 */ - struct { /* offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< , offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< , offset: 0x6C */ - __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< , array offset: 0x70, array step: 0x4 */ - } PRINCE_REGION1_IV_CODE_CORE; - }; - union { /* offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< , array offset: 0xA0, array step: 0x4 */ - struct { /* offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< , offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< , offset: 0xA4 */ - __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< , array offset: 0xA8, array step: 0x4 */ - } PRINCE_REGION2_IV_CODE_CORE; - }; - uint8_t RESERVED_1[40]; - __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ - __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ -} FLASH_CFPA_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_CFPA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CFPA_Register_Masks FLASH_CFPA Register Masks - * @{ - */ - -/*! @name HEADER - */ -/*! @{ */ - -#define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_HEADER_FIELD_SHIFT (0U) -#define FLASH_CFPA_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK) -/*! @} */ - -/*! @name VERSION - */ -/*! @{ */ - -#define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_VERSION_FIELD_SHIFT (0U) -#define FLASH_CFPA_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK) -/*! @} */ - -/*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */ -/*! @{ */ - -#define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U) -#define FLASH_CFPA_S_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK) -/*! @} */ - -/*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */ -/*! @{ */ - -#define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U) -#define FLASH_CFPA_NS_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK) -/*! @} */ - -/*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */ -/*! @{ */ - -#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U) -#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK) -/*! @} */ - -/*! @name ROTKH_REVOKE - */ -/*! @{ */ - -#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U) -/*! RoTK0_EN - RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK) - -#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U) -/*! RoTK1_EN - RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK) - -#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U) -/*! RoTK2_EN - RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK) - -#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK (0xC0U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT (6U) -/*! RoTK3_EN - RoT Key 3 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK) -/*! @} */ - -/*! @name VENDOR_USAGE - */ -/*! @{ */ - -#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU) -#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U) -/*! DBG_VENDOR_USAGE - DBG_VENDOR_USAGE. - */ -#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK) - -#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ -/*! @{ */ - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_ME_CMD_EN_MASK (0x80U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_ME_CMD_EN_SHIFT (7U) -/*! FA_ME_CMD_EN - FA Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_ME_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) -/*! UUID_CHECK - Enforce UUID match during Debug authentication. - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ -/*! @{ */ - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_ME_CMD_EN_MASK (0x80U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_ME_CMD_EN_SHIFT (7U) -/*! FA_ME_CMD_EN - FA Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_ME_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */ -/*! @{ */ - -#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK) -/*! @} */ - -/*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */ -/*! @{ */ - -#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U) -#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_IV_CODE - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */ -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U) - -/*! @name PRINCE_REGION0_IV_HEADER0 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_IV_HEADER1 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK) - -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK) - -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_IV_BODY - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */ -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U) - -/*! @name PRINCE_REGION1_IV_CODE - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */ -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U) - -/*! @name PRINCE_REGION1_IV_HEADER0 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_IV_HEADER1 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK) - -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK) - -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_IV_BODY - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */ -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U) - -/*! @name PRINCE_REGION2_IV_CODE - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */ -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U) - -/*! @name PRINCE_REGION2_IV_HEADER0 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_IV_HEADER1 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK) - -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK) - -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_IV_BODY - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION2_IV_BODY */ -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_COUNT (12U) - -/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ -/*! @{ */ - -#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) -#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_CUSTOMER_DEFINED */ -#define FLASH_CFPA_CUSTOMER_DEFINED_COUNT (56U) - -/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ -/*! @{ */ - -#define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U) -#define FLASH_CFPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_SHA256_DIGEST */ -#define FLASH_CFPA_SHA256_DIGEST_COUNT (8U) - - -/*! - * @} - */ /* end of group FLASH_CFPA_Register_Masks */ - - -/* FLASH_CFPA - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH_CFPA0 base address */ - #define FLASH_CFPA0_BASE (0x1003E000u) - /** Peripheral FLASH_CFPA0 base address */ - #define FLASH_CFPA0_BASE_NS (0x3E000u) - /** Peripheral FLASH_CFPA0 base pointer */ - #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) - /** Peripheral FLASH_CFPA0 base pointer */ - #define FLASH_CFPA0_NS ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS) - /** Peripheral FLASH_CFPA1 base address */ - #define FLASH_CFPA1_BASE (0x1003E200u) - /** Peripheral FLASH_CFPA1 base address */ - #define FLASH_CFPA1_BASE_NS (0x3E200u) - /** Peripheral FLASH_CFPA1 base pointer */ - #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) - /** Peripheral FLASH_CFPA1 base pointer */ - #define FLASH_CFPA1_NS ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS) - /** Peripheral FLASH_CFPA_SCRATCH base address */ - #define FLASH_CFPA_SCRATCH_BASE (0x1003DE00u) - /** Peripheral FLASH_CFPA_SCRATCH base address */ - #define FLASH_CFPA_SCRATCH_BASE_NS (0x3DE00u) - /** Peripheral FLASH_CFPA_SCRATCH base pointer */ - #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) - /** Peripheral FLASH_CFPA_SCRATCH base pointer */ - #define FLASH_CFPA_SCRATCH_NS ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS) - /** Array initializer of FLASH_CFPA peripheral base addresses */ - #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } - /** Array initializer of FLASH_CFPA peripheral base pointers */ - #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } - /** Array initializer of FLASH_CFPA peripheral base addresses */ - #define FLASH_CFPA_BASE_ADDRS_NS { FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS } - /** Array initializer of FLASH_CFPA peripheral base pointers */ - #define FLASH_CFPA_BASE_PTRS_NS { FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS } -#else - /** Peripheral FLASH_CFPA0 base address */ - #define FLASH_CFPA0_BASE (0x3E000u) - /** Peripheral FLASH_CFPA0 base pointer */ - #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) - /** Peripheral FLASH_CFPA1 base address */ - #define FLASH_CFPA1_BASE (0x3E200u) - /** Peripheral FLASH_CFPA1 base pointer */ - #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) - /** Peripheral FLASH_CFPA_SCRATCH base address */ - #define FLASH_CFPA_SCRATCH_BASE (0x3DE00u) - /** Peripheral FLASH_CFPA_SCRATCH base pointer */ - #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) - /** Array initializer of FLASH_CFPA peripheral base addresses */ - #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } - /** Array initializer of FLASH_CFPA peripheral base pointers */ - #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } -#endif - -/*! - * @} - */ /* end of group FLASH_CFPA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_CMPA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CMPA_Peripheral_Access_Layer FLASH_CMPA Peripheral Access Layer - * @{ - */ - -/** FLASH_CMPA - Register Layout Typedef */ -typedef struct { - __IO uint32_t BOOT_CFG; /**< , offset: 0x0 */ - __IO uint32_t SPI_FLASH_CFG; /**< , offset: 0x4 */ - __IO uint32_t USB_ID; /**< , offset: 0x8 */ - __IO uint32_t SDIO_CFG; /**< , offset: 0xC */ - __IO uint32_t CC_SOCU_PIN; /**< , offset: 0x10 */ - __IO uint32_t CC_SOCU_DFLT; /**< , offset: 0x14 */ - __IO uint32_t VENDOR_USAGE; /**< , offset: 0x18 */ - __IO uint32_t SECURE_BOOT_CFG; /**< Secure boot configuration flags., offset: 0x1C */ - __IO uint32_t PRINCE_BASE_ADDR; /**< , offset: 0x20 */ - __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */ - __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */ - __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */ - __IO uint32_t XTAL_32KHZ_CAPABANK_TRIM; /**< Xtal 32kHz capabank triming., offset: 0x30 */ - __IO uint32_t XTAL_16MHZ_CAPABANK_TRIM; /**< Xtal 16MHz capabank triming., offset: 0x34 */ - __IO uint32_t FLASH_REMAP_SIZE; /**< This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB., offset: 0x38 */ - __IO uint32_t FLASH_REMAP_OFFSET; /**< This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB., offset: 0x3C */ - uint8_t RESERVED_0[16]; - __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */ - uint8_t RESERVED_1[144]; - __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ - __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ -} FLASH_CMPA_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_CMPA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CMPA_Register_Masks FLASH_CMPA Register Masks - * @{ - */ - -/*! @name BOOT_CFG - */ -/*! @{ */ - -#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U) -#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U) -/*! DEFAULT_ISP_MODE - Default ISP mode: - * 0b000..Auto ISP - * 0b001..USB_HID_ISP - * 0b010..UART ISP - * 0b011..SPI Slave ISP - * 0b100..I2C Slave ISP - * 0b111..Disable ISP fall through - */ -#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK) - -#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U) -#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U) -/*! BOOT_SPEED - Core clock: - * 0b00..Defined by NMPA.SYSTEM_SPEED_CODE - * 0b10..48MHz FRO - */ -#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK) - -#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U) -#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U) -/*! BOOT_FAILURE_PIN - GPIO port and pin number to use for indicating failure reason. The toggle - * rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO - * pin - */ -#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK) -/*! @} */ - -/*! @name SPI_FLASH_CFG - */ -/*! @{ */ - -#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK (0x1FU) -#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT (0U) -/*! SPI_RECOVERY_BOOT_EN - SPI flash recovery boot is enabled, if non-zero value is written to this field. - */ -#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK) -/*! @} */ - -/*! @name USB_ID - */ -/*! @{ */ - -#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU) -#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U) -#define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK) - -#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U) -#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U) -#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK) -/*! @} */ - -/*! @name SDIO_CFG - */ -/*! @{ */ - -#define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U) -#define FLASH_CMPA_SDIO_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK) -/*! @} */ - -/*! @name CC_SOCU_PIN - */ -/*! @{ */ - -#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK (0x1U) -#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK (0x2U) -#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) -#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK (0x8U) -#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK (0x10U) -#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_FA_ME_CMD_EN_MASK (0x80U) -#define FLASH_CMPA_CC_SOCU_PIN_FA_ME_CMD_EN_SHIFT (7U) -/*! FA_ME_CMD_EN - FA Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_FA_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_FA_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_FA_ME_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) -#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) -/*! UUID_CHECK - Enforce UUID match during Debug authentication. - */ -#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name CC_SOCU_DFLT - */ -/*! @{ */ - -#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK (0x1U) -#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK (0x2U) -#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) -#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) -#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK (0x10U) -#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_FA_ME_CMD_EN_MASK (0x80U) -#define FLASH_CMPA_CC_SOCU_DFLT_FA_ME_CMD_EN_SHIFT (7U) -/*! FA_ME_CMD_EN - FA Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_FA_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_FA_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_FA_ME_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name VENDOR_USAGE - */ -/*! @{ */ - -#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK (0xFFFF0000U) -#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT (16U) -/*! VENDOR_USAGE - Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area. - */ -#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK) -/*! @} */ - -/*! @name SECURE_BOOT_CFG - Secure boot configuration flags. */ -/*! @{ */ - -#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U) -#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U) -/*! RSA4K - Use RSA4096 keys only. - * 0b00..Allow RSA2048 and higher - * 0b01..RSA4096 only - * 0b10..RSA4096 only - * 0b11..RSA4096 only - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK (0xCU) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT (2U) -/*! DICE_INC_NXP_CFG - Include NXP area in DICE computation. - * 0b00..not included - * 0b01..included - * 0b10..included - * 0b11..included - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U) -/*! DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. - * 0b00..not included - * 0b01..included - * 0b10..included - * 0b11..included - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U) -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U) -/*! SKIP_DICE - Skip DICE computation - * 0b00..Enable DICE - * 0b01..Disable DICE - * 0b10..Disable DICE - * 0b11..Disable DICE - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U) -#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U) -/*! TZM_IMAGE_TYPE - TrustZone-M mode - * 0b00..TZ-M image mode is taken from application image header - * 0b01..TZ-M disabled image, boots to non-secure mode - * 0b10..TZ-M enabled image, boots to secure mode - * 0b11..TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U) -/*! BLOCK_SET_KEY - Block PUF key code generation - * 0b00..Allow PUF Key Code generation - * 0b01..Disable PUF Key Code generation - * 0b10..Disable PUF Key Code generation - * 0b11..Disable PUF Key Code generation - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U) -/*! BLOCK_ENROLL - Block PUF enrollement - * 0b00..Allow PUF enroll operation - * 0b01..Disable PUF enroll operation - * 0b10..Disable PUF enroll operation - * 0b11..Disable PUF enroll operation - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK (0xC000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT (14U) -/*! DICE_INC_SEC_EPOCH - Include security EPOCH in DICE - * 0b00..not included - * 0b01..included - * 0b10..included - * 0b11..included - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_BOOT_SEED_MASK (0x30000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_BOOT_SEED_SHIFT (16U) -/*! SKIP_BOOT_SEED - Skip boot seed computation - * 0b00..Enable BOOT_SEED - * 0b01..Disable BOOT_SEED - * 0b10..Disable BOOT_SEED - * 0b11..Disable BOOT_SEED - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_BOOT_SEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_BOOT_SEED_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_BOOT_SEED_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_NXP_CFG_MASK (0xC0000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_NXP_CFG_SHIFT (18U) -/*! BOOT_SEED_INC_NXP_CFG - Include NXP area in BOOT SEED computation - * 0b00..not included - * 0b01..included - * 0b10..included - * 0b11..included - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_NXP_CFG_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_CUST_CFG_MASK (0x300000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_CUST_CFG_SHIFT (20U) -/*! BOOT_SEED_CUST_CFG - Include CMPA area in BOOT SEED computation - * 0b00..not included - * 0b01..included - * 0b10..included - * 0b11..included - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_CUST_CFG_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_EPOCH_MASK (0xC00000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_EPOCH_SHIFT (22U) -/*! BOOT_SEED_INC_EPOCH - Include security epoch area in BOOT_SEED computation. - * 0b00..not included - * 0b01..included - * 0b10..included - * 0b11..included - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_EPOCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_EPOCH_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_EPOCH_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U) -/*! SEC_BOOT_EN - Secure boot enable - * 0b00..Plain image (internal flash with or without CRC) - * 0b01..Boot signed images. (internal flash, RSA signed) - * 0b10..Boot signed images. (internal flash, RSA signed) - * 0b11..Boot signed images. (internal flash, RSA signed) - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK) -/*! @} */ - -/*! @name PRINCE_BASE_ADDR - */ -/*! @{ */ - -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U) -/*! ADDR0_PRG - Programmable portion of the base address of region 0 - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U) -/*! ADDR1_PRG - Programmable portion of the base address of region 1 - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U) -/*! ADDR2_PRG - Programmable portion of the base address of region 2 - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0xC0000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (18U) -/*! LOCK_REG0 - Lock PRINCE region0 settings - * 0b00..Region is not locked - * 0b01..Region is locked - * 0b10..Region is locked - * 0b11..Region is locked - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0x300000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (20U) -/*! LOCK_REG1 - Lock PRINCE region1 settings - * 0b00..Region is not locked - * 0b01..Region is locked - * 0b10..Region is locked - * 0b11..Region is locked - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U) -/*! REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased together - * 0b00..Region is disabled - * 0b01..Region is enabled - * 0b10..Region is enabled - * 0b11..Region is enabled - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U) -/*! REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased together - * 0b00..Region is disabled - * 0b01..Region is enabled - * 0b10..Region is enabled - * 0b11..Region is enabled - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U) -/*! REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased together - * 0b00..Region is disabled - * 0b01..Region is enabled - * 0b10..Region is enabled - * 0b11..Region is enabled - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK) -/*! @} */ - -/*! @name PRINCE_SR_0 - Region 0, sub-region enable */ -/*! @{ */ - -#define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U) -#define FLASH_CMPA_PRINCE_SR_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_SR_1 - Region 1, sub-region enable */ -/*! @{ */ - -#define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U) -#define FLASH_CMPA_PRINCE_SR_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_SR_2 - Region 2, sub-region enable */ -/*! @{ */ - -#define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U) -#define FLASH_CMPA_PRINCE_SR_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK) -/*! @} */ - -/*! @name XTAL_32KHZ_CAPABANK_TRIM - Xtal 32kHz capabank triming. */ -/*! @{ */ - -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) -/*! TRIM_VALID - XTAL 32kHz capa bank trimmings - * 0b0..Capa Bank trimmings not valid. Default trimmings value are used - * 0b1..Capa Bank trimmings valid - */ -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK) - -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) -/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) - -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) -/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) - -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) -/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) -/*! @} */ - -/*! @name XTAL_16MHZ_CAPABANK_TRIM - Xtal 16MHz capabank triming. */ -/*! @{ */ - -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) -/*! TRIM_VALID - XTAL 16MHz capa bank trimmings - * 0b0..Capa Bank trimmings not valid. Default trimmings value are used - * 0b1..Capa Bank trimmings valid - */ -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK) - -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) -/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) - -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) -/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) - -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) -/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) -/*! @} */ - -/*! @name FLASH_REMAP_SIZE - This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB. */ -/*! @{ */ - -#define FLASH_CMPA_FLASH_REMAP_SIZE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_FLASH_REMAP_SIZE_FIELD_SHIFT (0U) -#define FLASH_CMPA_FLASH_REMAP_SIZE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_FLASH_REMAP_SIZE_FIELD_SHIFT)) & FLASH_CMPA_FLASH_REMAP_SIZE_FIELD_MASK) -/*! @} */ - -/*! @name FLASH_REMAP_OFFSET - This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB. */ -/*! @{ */ - -#define FLASH_CMPA_FLASH_REMAP_OFFSET_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_FLASH_REMAP_OFFSET_FIELD_SHIFT (0U) -#define FLASH_CMPA_FLASH_REMAP_OFFSET_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_FLASH_REMAP_OFFSET_FIELD_SHIFT)) & FLASH_CMPA_FLASH_REMAP_OFFSET_FIELD_MASK) -/*! @} */ - -/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0] */ -/*! @{ */ - -#define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U) -#define FLASH_CMPA_ROTKH_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CMPA_ROTKH */ -#define FLASH_CMPA_ROTKH_COUNT (8U) - -/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ -/*! @{ */ - -#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) -#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CMPA_CUSTOMER_DEFINED */ -#define FLASH_CMPA_CUSTOMER_DEFINED_COUNT (56U) - -/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ -/*! @{ */ - -#define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U) -#define FLASH_CMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CMPA_SHA256_DIGEST */ -#define FLASH_CMPA_SHA256_DIGEST_COUNT (8U) - - -/*! - * @} - */ /* end of group FLASH_CMPA_Register_Masks */ - - -/* FLASH_CMPA - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH_CMPA base address */ - #define FLASH_CMPA_BASE (0x1003E400u) - /** Peripheral FLASH_CMPA base address */ - #define FLASH_CMPA_BASE_NS (0x3E400u) - /** Peripheral FLASH_CMPA base pointer */ - #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) - /** Peripheral FLASH_CMPA base pointer */ - #define FLASH_CMPA_NS ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS) - /** Array initializer of FLASH_CMPA peripheral base addresses */ - #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } - /** Array initializer of FLASH_CMPA peripheral base pointers */ - #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } - /** Array initializer of FLASH_CMPA peripheral base addresses */ - #define FLASH_CMPA_BASE_ADDRS_NS { FLASH_CMPA_BASE_NS } - /** Array initializer of FLASH_CMPA peripheral base pointers */ - #define FLASH_CMPA_BASE_PTRS_NS { FLASH_CMPA_NS } -#else - /** Peripheral FLASH_CMPA base address */ - #define FLASH_CMPA_BASE (0x3E400u) - /** Peripheral FLASH_CMPA base pointer */ - #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) - /** Array initializer of FLASH_CMPA peripheral base addresses */ - #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } - /** Array initializer of FLASH_CMPA peripheral base pointers */ - #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } -#endif - -/*! - * @} - */ /* end of group FLASH_CMPA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_KEY_STORE Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_KEY_STORE_Peripheral_Access_Layer FLASH_KEY_STORE Peripheral Access Layer - * @{ - */ - -/** FLASH_KEY_STORE - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0 */ - __IO uint32_t HEADER; /**< Valid Key Sore Header : 0x95959595, offset: 0x0 */ - __IO uint32_t PUF_DISCHARGE_TIME_IN_MS; /**< puf discharge time in ms., offset: 0x4 */ - } KEY_STORE_HEADER; - __IO uint32_t ACTIVATION_CODE[298]; /**< ., array offset: 0x8, array step: 0x4 */ - union { /* offset: 0x4B0 */ - __IO uint32_t SBKEY_KEY_CODE[14]; /**< ., array offset: 0x4B0, array step: 0x4 */ - struct { /* offset: 0x4B0 */ - __IO uint32_t SBKEY_HEADER0; /**< ., offset: 0x4B0 */ - __IO uint32_t SBKEY_HEADER1; /**< ., offset: 0x4B4 */ - __IO uint32_t SBKEY_BODY[12]; /**< ., array offset: 0x4B8, array step: 0x4 */ - } SBKEY_KEY_CODE_CORE; - }; - union { /* offset: 0x4E8 */ - __IO uint32_t USER_KEK_KEY_CODE[14]; /**< ., array offset: 0x4E8, array step: 0x4 */ - struct { /* offset: 0x4E8 */ - __IO uint32_t USER_KEK_HEADER0; /**< ., offset: 0x4E8 */ - __IO uint32_t USER_KEK_HEADER1; /**< ., offset: 0x4EC */ - __IO uint32_t USER_KEK_BODY[12]; /**< ., array offset: 0x4F0, array step: 0x4 */ - } USER_KEK_KEY_CODE_CORE; - }; - union { /* offset: 0x520 */ - __IO uint32_t UDS_KEY_CODE[14]; /**< ., array offset: 0x520, array step: 0x4 */ - struct { /* offset: 0x520 */ - __IO uint32_t UDS_HEADER0; /**< ., offset: 0x520 */ - __IO uint32_t UDS_HEADER1; /**< ., offset: 0x524 */ - __IO uint32_t UDS_BODY[12]; /**< ., array offset: 0x528, array step: 0x4 */ - } UDS_KEY_CODE_CORE; - }; - union { /* offset: 0x558 */ - __IO uint32_t PRINCE_REGION0_KEY_CODE[14]; /**< ., array offset: 0x558, array step: 0x4 */ - struct { /* offset: 0x558 */ - __IO uint32_t PRINCE_REGION0_HEADER0; /**< ., offset: 0x558 */ - __IO uint32_t PRINCE_REGION0_HEADER1; /**< ., offset: 0x55C */ - __IO uint32_t PRINCE_REGION0_BODY[12]; /**< ., array offset: 0x560, array step: 0x4 */ - } PRINCE_REGION0_KEY_CODE_CORE; - }; - union { /* offset: 0x590 */ - __IO uint32_t PRINCE_REGION1_KEY_CODE[14]; /**< ., array offset: 0x590, array step: 0x4 */ - struct { /* offset: 0x590 */ - __IO uint32_t PRINCE_REGION1_HEADER0; /**< ., offset: 0x590 */ - __IO uint32_t PRINCE_REGION1_HEADER1; /**< ., offset: 0x594 */ - __IO uint32_t PRINCE_REGION1_BODY[12]; /**< ., array offset: 0x598, array step: 0x4 */ - } PRINCE_REGION1_KEY_CODE_CORE; - }; - union { /* offset: 0x5C8 */ - __IO uint32_t PRINCE_REGION2_KEY_CODE[14]; /**< ., array offset: 0x5C8, array step: 0x4 */ - struct { /* offset: 0x5C8 */ - __IO uint32_t PRINCE_REGION2_HEADER0; /**< ., offset: 0x5C8 */ - __IO uint32_t PRINCE_REGION2_HEADER1; /**< ., offset: 0x5CC */ - __IO uint32_t PRINCE_REGION2_BODY[12]; /**< ., array offset: 0x5D0, array step: 0x4 */ - } PRINCE_REGION2_KEY_CODE_CORE; - }; -} FLASH_KEY_STORE_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_KEY_STORE Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_KEY_STORE_Register_Masks FLASH_KEY_STORE Register Masks - * @{ - */ - -/*! @name HEADER - Valid Key Sore Header : 0x95959595 */ -/*! @{ */ - -#define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK) -/*! @} */ - -/*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */ -/*! @{ */ - -#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK) -/*! @} */ - -/*! @name ACTIVATION_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_ACTIVATION_CODE */ -#define FLASH_KEY_STORE_ACTIVATION_CODE_COUNT (298U) - -/*! @name SBKEY_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_SBKEY_KEY_CODE */ -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_COUNT (14U) - -/*! @name SBKEY_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name SBKEY_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name SBKEY_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_SBKEY_BODY */ -#define FLASH_KEY_STORE_SBKEY_BODY_COUNT (12U) - -/*! @name USER_KEK_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_USER_KEK_KEY_CODE */ -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_COUNT (14U) - -/*! @name USER_KEK_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name USER_KEK_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name USER_KEK_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_USER_KEK_BODY */ -#define FLASH_KEY_STORE_USER_KEK_BODY_COUNT (12U) - -/*! @name UDS_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_UDS_KEY_CODE */ -#define FLASH_KEY_STORE_UDS_KEY_CODE_COUNT (14U) - -/*! @name UDS_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name UDS_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name UDS_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_UDS_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_UDS_BODY */ -#define FLASH_KEY_STORE_UDS_BODY_COUNT (12U) - -/*! @name PRINCE_REGION0_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE */ -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_COUNT (14U) - -/*! @name PRINCE_REGION0_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION0_BODY */ -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_COUNT (12U) - -/*! @name PRINCE_REGION1_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE */ -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_COUNT (14U) - -/*! @name PRINCE_REGION1_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION1_BODY */ -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_COUNT (12U) - -/*! @name PRINCE_REGION2_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE */ -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_COUNT (14U) - -/*! @name PRINCE_REGION2_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION2_BODY */ -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_COUNT (12U) - - -/*! - * @} - */ /* end of group FLASH_KEY_STORE_Register_Masks */ - - -/* FLASH_KEY_STORE - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH_KEY_STORE base address */ - #define FLASH_KEY_STORE_BASE (0x1003E600u) - /** Peripheral FLASH_KEY_STORE base address */ - #define FLASH_KEY_STORE_BASE_NS (0x3E600u) - /** Peripheral FLASH_KEY_STORE base pointer */ - #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) - /** Peripheral FLASH_KEY_STORE base pointer */ - #define FLASH_KEY_STORE_NS ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS) - /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ - #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } - /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ - #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } - /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ - #define FLASH_KEY_STORE_BASE_ADDRS_NS { FLASH_KEY_STORE_BASE_NS } - /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ - #define FLASH_KEY_STORE_BASE_PTRS_NS { FLASH_KEY_STORE_NS } -#else - /** Peripheral FLASH_KEY_STORE base address */ - #define FLASH_KEY_STORE_BASE (0x3E600u) - /** Peripheral FLASH_KEY_STORE base pointer */ - #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) - /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ - #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } - /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ - #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } -#endif - -/*! - * @} - */ /* end of group FLASH_KEY_STORE_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_NMPA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_NMPA_Peripheral_Access_Layer FLASH_NMPA Peripheral Access Layer - * @{ - */ - -/** FLASH_NMPA - Register Layout Typedef */ -typedef struct { - union { /* offset: 0x0 */ - struct { /* offset: 0x0 */ - __IO uint32_t GPO0_0; /**< GPO0 register 0 description, offset: 0x0 */ - __IO uint32_t GPO0_1; /**< GPO0 register 1 description, offset: 0x4 */ - __IO uint32_t GPO0_2; /**< GPO0 register 2 description, offset: 0x8 */ - __IO uint32_t GPO0_3; /**< GPO0 register 3 description, offset: 0xC */ - } GPO0; - __IO uint32_t GPO0_ARRAY[4]; /**< GPO0 array description, array offset: 0x0, array step: 0x4 */ - }; - union { /* offset: 0x10 */ - struct { /* offset: 0x10 */ - __IO uint32_t GPO1_0; /**< GPO1 register 0 description, offset: 0x10 */ - __IO uint32_t GPO1_1; /**< GPO1 register 1 description, offset: 0x14 */ - __IO uint32_t GPO1_2; /**< GPO1 register 2 description, offset: 0x18 */ - __IO uint32_t GPO1_3; /**< GPO1 register 3 description, offset: 0x1C */ - } GPO1; - __IO uint32_t GPO1_ARRAY[4]; /**< GPO1 array description, array offset: 0x10, array step: 0x4 */ - }; - union { /* offset: 0x20 */ - struct { /* offset: 0x20 */ - __IO uint32_t GPO2_0; /**< GPO2 register 0 description, offset: 0x20 */ - __IO uint32_t GPO2_1; /**< GPO2 register 1 description, offset: 0x24 */ - __IO uint32_t GPO2_2; /**< GPO2 register 2 description, offset: 0x28 */ - __IO uint32_t GPO2_3; /**< GPO2 register 3 description, offset: 0x2C */ - } GPO2; - __IO uint32_t GPO2_ARRAY[4]; /**< GPO2 array description, array offset: 0x20, array step: 0x4 */ - }; - union { /* offset: 0x30 */ - struct { /* offset: 0x30 */ - __IO uint32_t GPO3_0; /**< GPO3 register 0 description, offset: 0x30 */ - __IO uint32_t GPO3_1; /**< GPO3 register 1 description, offset: 0x34 */ - __IO uint32_t GPO3_2; /**< GPO3 register 2 description, offset: 0x38 */ - __IO uint32_t GPO3_3; /**< GPO3 register 3 description, offset: 0x3C */ - } GPO3; - __IO uint32_t GPO3_ARRAY[4]; /**< GPO3 array description, array offset: 0x30, array step: 0x4 */ - }; - union { /* offset: 0x40 */ - struct { /* offset: 0x40 */ - __IO uint32_t GPO_CHECKSUM_0; /**< checksum of the GPO data in words 0, offset: 0x40 */ - __IO uint32_t GPO_CHECKSUM_1; /**< checksum of the GPO data in words 1, offset: 0x44 */ - __IO uint32_t GPO_CHECKSUM_2; /**< checksum of the GPO data in words 2, offset: 0x48 */ - __IO uint32_t GPO_CHECKSUM_3; /**< checksum of the GPO data in words 3, offset: 0x4C */ - } GPO_CHECKSUM; - __IO uint32_t GPO_CHECKSUM_ARRAY[4]; /**< checksum of the GPO data in words [3:0], array offset: 0x40, array step: 0x4 */ - }; - union { /* offset: 0x50 */ - struct { /* offset: 0x50 */ - __IO uint32_t FINAL_TEST_BATCH_ID_0; /**< , offset: 0x50 */ - __IO uint32_t FINAL_TEST_BATCH_ID_1; /**< , offset: 0x54 */ - __IO uint32_t FINAL_TEST_BATCH_ID_2; /**< , offset: 0x58 */ - __IO uint32_t FINAL_TEST_BATCH_ID_3; /**< , offset: 0x5C */ - } FINAL_TEST_BATCH_ID; - __IO uint32_t FINAL_TEST_BATCH_ID_ARRAY[4]; /**< , array offset: 0x50, array step: 0x4 */ - }; - __IO uint32_t DEVICE_TYPE; /**< , offset: 0x60 */ - __IO uint32_t FINAL_TEST_PROGRAM_VERSION; /**< , offset: 0x64 */ - __IO uint32_t FINAL_TEST_DATE; /**< , offset: 0x68 */ - __IO uint32_t FINAL_TEST_TIME; /**< , offset: 0x6C */ - union { /* offset: 0x70 */ - struct { /* offset: 0x70 */ - __IO uint32_t UUID_0; /**< , offset: 0x70 */ - __IO uint32_t UUID_1; /**< , offset: 0x74 */ - __IO uint32_t UUID_2; /**< , offset: 0x78 */ - __IO uint32_t UUID_3; /**< , offset: 0x7C */ - } UUID; - __IO uint32_t UUID_ARRAY[4]; /**< , array offset: 0x70, array step: 0x4 */ - }; - __IO uint32_t WAFER_TEST1_PROGRAM_VERSION; /**< , offset: 0x80 */ - __IO uint32_t WAFER_TEST1_DATE; /**< , offset: 0x84 */ - __IO uint32_t WAFER_TEST1_TIME; /**< , offset: 0x88 */ - uint8_t RESERVED_0[4]; - __IO uint32_t WAFER_TEST2_PROGRAM_VERSION; /**< , offset: 0x90 */ - __IO uint32_t WAFER_TEST2_DATE; /**< , offset: 0x94 */ - __IO uint32_t WAFER_TEST2_TIME; /**< , offset: 0x98 */ - __IO uint32_t USBCFG; /**< , offset: 0x9C */ - __IO uint32_t PERIPHENCFG; /**< , offset: 0xA0 */ - __IO uint32_t RAMSIZECFG; /**< , offset: 0xA4 */ - __IO uint32_t FLASHSIZECFG; /**< , offset: 0xA8 */ - uint8_t RESERVED_1[4]; - __IO uint32_t RINGO_0; /**< , offset: 0xB0 */ - __IO uint32_t RINGO_1; /**< , offset: 0xB4 */ - __IO uint32_t RINGO_2; /**< , offset: 0xB8 */ - uint8_t RESERVED_2[4]; - __IO uint32_t FRO_192MHZ; /**< , offset: 0xC0 */ - uint8_t RESERVED_3[4]; - __IO uint32_t XO_32MHZ; /**< , offset: 0xC8 */ - __IO uint32_t XO_32KHZ; /**< , offset: 0xCC */ - __IO uint32_t FRO_1MHZ; /**< , offset: 0xD0 */ - uint8_t RESERVED_4[4]; - union { /* offset: 0xD8 */ - struct { /* offset: 0xD8 */ - __IO uint32_t DCDC_POWER_PROFILE_HIGH_0; /**< , offset: 0xD8 */ - __IO uint32_t DCDC_POWER_PROFILE_HIGH_1; /**< , offset: 0xDC */ - } DCDC_POWER_PROFILE_HIGH; - __IO uint32_t DCDC_POWER_PROFILE_HIGH_ARRAY[2]; /**< , array offset: 0xD8, array step: 0x4 */ - }; - union { /* offset: 0xE0 */ - struct { /* offset: 0xE0 */ - __IO uint32_t DCDC_POWER_PROFILE_LOW_0; /**< , offset: 0xE0 */ - __IO uint32_t DCDC_POWER_PROFILE_LOW_1; /**< , offset: 0xE4 */ - } DCDC_POWER_PROFILE_LOW; - __IO uint32_t DCDC_POWER_PROFILE_LOW_ARRAY[2]; /**< , array offset: 0xE0, array step: 0x4 */ - }; - union { /* offset: 0xE8 */ - struct { /* offset: 0xE8 */ - __IO uint32_t DCDC_POWER_PROFILE_MEDIUM_0; /**< , offset: 0xE8 */ - __IO uint32_t DCDC_POWER_PROFILE_MEDIUM_1; /**< , offset: 0xEC */ - } DCDC_POWER_PROFILE_MEDIUM; - __IO uint32_t DCDC_POWER_PROFILE_MEDIUM_ARRAY[2]; /**< , array offset: 0xE8, array step: 0x4 */ - }; - __IO uint32_t BOD; /**< , offset: 0xF0 */ - __IO uint32_t LDO_AO; /**< , offset: 0xF4 */ - __IO uint32_t SDIO_DELAY; /**< , offset: 0xF8 */ - uint8_t RESERVED_5[4]; - union { /* offset: 0x100 */ - struct { /* offset: 0x100 */ - __IO uint32_t AUX_BIAS_CURVE_AMBIENT_0; /**< , offset: 0x100 */ - __IO uint32_t AUX_BIAS_CURVE_AMBIENT_1; /**< , offset: 0x104 */ - __IO uint32_t AUX_BIAS_CURVE_AMBIENT_2; /**< , offset: 0x108 */ - __IO uint32_t AUX_BIAS_CURVE_AMBIENT_3; /**< , offset: 0x10C */ - } AUX_BIAS_CURVE_AMBIENT; - __IO uint32_t AUX_BIAS_CURVE_AMBIENT_ARRAY[4]; /**< Aux Bias Curve Ambient (30degC), array offset: 0x100, array step: 0x4 */ - }; - union { /* offset: 0x110 */ - struct { /* offset: 0x110 */ - __IO uint32_t AUX_BIAS_CURVE_TEMP_0; /**< , offset: 0x110 */ - __IO uint32_t AUX_BIAS_CURVE_TEMP_1; /**< , offset: 0x114 */ - __IO uint32_t AUX_BIAS_CURVE_TEMP_2; /**< , offset: 0x118 */ - __IO uint32_t AUX_BIAS_CURVE_TEMP_3; /**< , offset: 0x11C */ - } AUX_BIAS_CURVE_TEMP; - __IO uint32_t AUX_BIAS_CURVE_TEMP_ARRAY[4]; /**< Aux Bias Curve TEMP (105degC), array offset: 0x110, array step: 0x4 */ - }; - __IO uint32_t TEMP_SENS_VBE1VBE8_REF_1; /**< , offset: 0x120 */ - __IO uint32_t TEMP_SENS_VBE1VBE8_REF_2; /**< , offset: 0x124 */ - __IO uint32_t TEMP_SENS_SLOPE; /**< , offset: 0x128 */ - __IO uint32_t TEMP_SENS_OFFSET; /**< , offset: 0x12C */ - union { /* offset: 0x130 */ - struct { /* offset: 0x130 */ - __IO uint32_t PVT_MONITOR_0_RINGO; /**< , offset: 0x130 */ - __IO uint32_t PVT_MONITOR_0_DELAYS_LSB; /**< , offset: 0x134 */ - __IO uint32_t PVT_MONITOR_0_DELAYS_MSB; /**< , offset: 0x138 */ - } PVT_MONITOR_0; - __IO uint32_t PVT_MONITOR_0_ARRAY[3]; /**< , array offset: 0x130, array step: 0x4 */ - }; - uint8_t RESERVED_6[4]; - union { /* offset: 0x140 */ - struct { /* offset: 0x140 */ - __IO uint32_t PVT_MONITOR_1_RINGO; /**< , offset: 0x140 */ - __IO uint32_t PVT_MONITOR_1_DELAYS_LSB; /**< , offset: 0x144 */ - __IO uint32_t PVT_MONITOR_1_DELAYS_MSB; /**< , offset: 0x148 */ - } PVT_MONITOR_1; - __IO uint32_t PVT_MONITOR_1_ARRAY[3]; /**< , array offset: 0x140, array step: 0x4 */ - }; - __IO uint32_t NXP_DEVICE_PRIVATE_KEY[13]; /**< , array offset: 0x14C, array step: 0x4 */ - __IO uint32_t NXP_DEVICE_CERTIFICATE_0[4]; /**< NXP Device Certificate (ECDSA_sign - r[255:128]), array offset: 0x180, array step: 0x4 */ - __IO uint32_t NXP_DEVICE_CERTIFICATE_1[4]; /**< NXP Device Certificate (ECDSA_sign - r[127:0]), array offset: 0x190, array step: 0x4 */ - __IO uint32_t NXP_DEVICE_CERTIFICATE_2[4]; /**< NXP Device Certificate (ECDSA_sign - s[255:128]), array offset: 0x1A0, array step: 0x4 */ - __IO uint32_t NXP_DEVICE_CERTIFICATE_3[4]; /**< NXP Device Certificate (ECDSA_sign - s[127:0]), array offset: 0x1B0, array step: 0x4 */ - __IO uint32_t SHA256_DIGEST[8]; /**< SHA-256 DIGEST (9EC00 - 9FDBC) ROM Patch Area + NXP Area (IMPORTANT NOTE: Pages used for Repair (N-8 to N-3) are excluded from the computation) SHA256_DIGEST0 for DIGEST[31:0]..SHA-256 DIGEST (9EC00 - 9FDBC) ROM Patch Area + NXP Area (IMPORTANT NOTE: Pages used for Repair (N-8 to N-3) are excluded from the computation) SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1C0, array step: 0x4 */ - union { /* offset: 0x1E0 */ - struct { /* offset: 0x1E0 */ - __IO uint32_t ECID_BACKUP_0; /**< , offset: 0x1E0 */ - __IO uint32_t ECID_BACKUP_1; /**< , offset: 0x1E4 */ - __IO uint32_t ECID_BACKUP_2; /**< , offset: 0x1E8 */ - __IO uint32_t ECID_BACKUP_3; /**< , offset: 0x1EC */ - } ECID_BACKUP; - __IO uint32_t ECID_BACKUP_ARRAY[4]; /**< ECID backup (the original is in page n-1), array offset: 0x1E0, array step: 0x4 */ - }; - uint32_t CHECKSUM[4]; /**< Checksum of the whole page, array offset: 0x1F0, array step: 0x4 */ - uint8_t RESERVED_7[2732]; - __IO uint32_t DIS_ROM_HIDING; /**< , offset: 0xCAC */ - uint8_t RESERVED_8[12]; - __IO uint32_t PUF_SRAM; /**< , offset: 0xCBC */ -} FLASH_NMPA_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_NMPA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_NMPA_Register_Masks FLASH_NMPA Register Masks - * @{ - */ - -/*! @name GPO0_0 - GPO0 register 0 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO0_0_FRO_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_GPO0_0_FRO_TRIM_VALID_SHIFT (0U) -#define FLASH_NMPA_GPO0_0_FRO_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_0_FRO_TRIM_VALID_SHIFT)) & FLASH_NMPA_GPO0_0_FRO_TRIM_VALID_MASK) - -#define FLASH_NMPA_GPO0_0_FRO32K_NTAT_MASK (0xEU) -#define FLASH_NMPA_GPO0_0_FRO32K_NTAT_SHIFT (1U) -#define FLASH_NMPA_GPO0_0_FRO32K_NTAT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_0_FRO32K_NTAT_SHIFT)) & FLASH_NMPA_GPO0_0_FRO32K_NTAT_MASK) - -#define FLASH_NMPA_GPO0_0_FRO32K_PTAT_MASK (0x70U) -#define FLASH_NMPA_GPO0_0_FRO32K_PTAT_SHIFT (4U) -#define FLASH_NMPA_GPO0_0_FRO32K_PTAT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_0_FRO32K_PTAT_SHIFT)) & FLASH_NMPA_GPO0_0_FRO32K_PTAT_MASK) - -#define FLASH_NMPA_GPO0_0_FRO32K_CAPCAL_MASK (0xFF80U) -#define FLASH_NMPA_GPO0_0_FRO32K_CAPCAL_SHIFT (7U) -#define FLASH_NMPA_GPO0_0_FRO32K_CAPCAL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_0_FRO32K_CAPCAL_SHIFT)) & FLASH_NMPA_GPO0_0_FRO32K_CAPCAL_MASK) - -#define FLASH_NMPA_GPO0_0_FIELD_MASK (0xFFFF0000U) -#define FLASH_NMPA_GPO0_0_FIELD_SHIFT (16U) -#define FLASH_NMPA_GPO0_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_0_FIELD_SHIFT)) & FLASH_NMPA_GPO0_0_FIELD_MASK) -/*! @} */ - -/*! @name GPO0_1 - GPO0 register 1 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO0_1_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO0_1_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO0_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_1_FIELD_SHIFT)) & FLASH_NMPA_GPO0_1_FIELD_MASK) -/*! @} */ - -/*! @name GPO0_2 - GPO0 register 2 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO0_2_SYSTEM_SPEED_CODE_MASK (0x3U) -#define FLASH_NMPA_GPO0_2_SYSTEM_SPEED_CODE_SHIFT (0U) -/*! SYSTEM_SPEED_CODE - 00 : FRO12MHz 01 : FRO24MHz 10 : FRO48MHz 11 : FRO96MHz - */ -#define FLASH_NMPA_GPO0_2_SYSTEM_SPEED_CODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_2_SYSTEM_SPEED_CODE_SHIFT)) & FLASH_NMPA_GPO0_2_SYSTEM_SPEED_CODE_MASK) - -#define FLASH_NMPA_GPO0_2_FLASH_CTRL_OPMODE_MASK (0xCU) -#define FLASH_NMPA_GPO0_2_FLASH_CTRL_OPMODE_SHIFT (2U) -/*! FLASH_CTRL_OPMODE - 00 : Delay Line 01 : RCLK (back up clock) 10 : PCLK (back up clock) - */ -#define FLASH_NMPA_GPO0_2_FLASH_CTRL_OPMODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_2_FLASH_CTRL_OPMODE_SHIFT)) & FLASH_NMPA_GPO0_2_FLASH_CTRL_OPMODE_MASK) - -#define FLASH_NMPA_GPO0_2_FIELD_MASK (0xFFFFFFF0U) -#define FLASH_NMPA_GPO0_2_FIELD_SHIFT (4U) -#define FLASH_NMPA_GPO0_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_2_FIELD_SHIFT)) & FLASH_NMPA_GPO0_2_FIELD_MASK) -/*! @} */ - -/*! @name GPO0_3 - GPO0 register 3 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO0_3_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO0_3_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO0_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_3_FIELD_SHIFT)) & FLASH_NMPA_GPO0_3_FIELD_MASK) -/*! @} */ - -/*! @name GPO0_ARRAY - GPO0 array description */ -/*! @{ */ - -#define FLASH_NMPA_GPO0_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO0_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO0_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_GPO0_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_GPO0_ARRAY */ -#define FLASH_NMPA_GPO0_ARRAY_COUNT (4U) - -/*! @name GPO1_0 - GPO1 register 0 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO1_0_FINAL_TEST_NOT_DONE_MASK (0xFU) -#define FLASH_NMPA_GPO1_0_FINAL_TEST_NOT_DONE_SHIFT (0U) -/*! FINAL_TEST_NOT_DONE - FINAL_TEST_NOT_DONE[3:0]: 1010 : Final Test Not Done. All Other values: Final Test Done. - */ -#define FLASH_NMPA_GPO1_0_FINAL_TEST_NOT_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_FINAL_TEST_NOT_DONE_SHIFT)) & FLASH_NMPA_GPO1_0_FINAL_TEST_NOT_DONE_MASK) - -#define FLASH_NMPA_GPO1_0_PARTCONFIG_MASK (0x7F0U) -#define FLASH_NMPA_GPO1_0_PARTCONFIG_SHIFT (4U) -/*! PARTCONFIG - Device type number. (E.g : LPC5569 stored as 69 decimal) - */ -#define FLASH_NMPA_GPO1_0_PARTCONFIG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_PARTCONFIG_SHIFT)) & FLASH_NMPA_GPO1_0_PARTCONFIG_MASK) - -#define FLASH_NMPA_GPO1_0_DEVICE_TYPE_SEC_MASK (0x800U) -#define FLASH_NMPA_GPO1_0_DEVICE_TYPE_SEC_SHIFT (11U) -/*! DEVICE_TYPE_SEC - Security device type: 0: LPC55xxx (Non Secure Familly) 1: LPC55Sxxx (Secure Familly) - */ -#define FLASH_NMPA_GPO1_0_DEVICE_TYPE_SEC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_DEVICE_TYPE_SEC_SHIFT)) & FLASH_NMPA_GPO1_0_DEVICE_TYPE_SEC_MASK) - -#define FLASH_NMPA_GPO1_0_SRAM_SIZE_MASK (0xF000U) -#define FLASH_NMPA_GPO1_0_SRAM_SIZE_SHIFT (12U) -/*! SRAM_SIZE - SRAM_SIZE[3:0]: (For Niobe4) 0000 : 320 KB 0001 : 256 KB 0010 : 144 KB 0011 : 80 KB - * (For Niobe4 Mini) 0100 : 96 KB 0101 : 80 KB 0110 : 64 KB 0111 : 48 KB All others : RESERVED - */ -#define FLASH_NMPA_GPO1_0_SRAM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_SRAM_SIZE_SHIFT)) & FLASH_NMPA_GPO1_0_SRAM_SIZE_MASK) - -#define FLASH_NMPA_GPO1_0_CPU0_SECURITY_EXTENSION_DISABLE_MASK (0xF0000U) -#define FLASH_NMPA_GPO1_0_CPU0_SECURITY_EXTENSION_DISABLE_SHIFT (16U) -/*! CPU0_SECURITY_EXTENSION_DISABLE - CPU0_SECURITY_EXTENSION_DISABLE[3:0]: 1010 : CPU0 Security - * Extension is disabled. All Other values: CPU0 Security Extension is enabled. - */ -#define FLASH_NMPA_GPO1_0_CPU0_SECURITY_EXTENSION_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_CPU0_SECURITY_EXTENSION_DISABLE_SHIFT)) & FLASH_NMPA_GPO1_0_CPU0_SECURITY_EXTENSION_DISABLE_MASK) - -#define FLASH_NMPA_GPO1_0_FIELD_MASK (0xF00000U) -#define FLASH_NMPA_GPO1_0_FIELD_SHIFT (20U) -#define FLASH_NMPA_GPO1_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_FIELD_SHIFT)) & FLASH_NMPA_GPO1_0_FIELD_MASK) - -#define FLASH_NMPA_GPO1_0_ROM_REVISION_MINOR_MASK (0xF000000U) -#define FLASH_NMPA_GPO1_0_ROM_REVISION_MINOR_SHIFT (24U) -/*! ROM_REVISION_MINOR - ROM Revision-Minor [3:0] - */ -#define FLASH_NMPA_GPO1_0_ROM_REVISION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_ROM_REVISION_MINOR_SHIFT)) & FLASH_NMPA_GPO1_0_ROM_REVISION_MINOR_MASK) - -#define FLASH_NMPA_GPO1_0_METAL_REVISION_ID_MASK (0xF0000000U) -#define FLASH_NMPA_GPO1_0_METAL_REVISION_ID_SHIFT (28U) -/*! METAL_REVISION_ID - METAL REVISION ID[3:0] - */ -#define FLASH_NMPA_GPO1_0_METAL_REVISION_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_METAL_REVISION_ID_SHIFT)) & FLASH_NMPA_GPO1_0_METAL_REVISION_ID_MASK) -/*! @} */ - -/*! @name GPO1_1 - GPO1 register 1 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO1_1_ROM_PATCH_VERSION_MASK (0xFU) -#define FLASH_NMPA_GPO1_1_ROM_PATCH_VERSION_SHIFT (0U) -/*! ROM_PATCH_VERSION - ROM Patch Version [3:0] - */ -#define FLASH_NMPA_GPO1_1_ROM_PATCH_VERSION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_1_ROM_PATCH_VERSION_SHIFT)) & FLASH_NMPA_GPO1_1_ROM_PATCH_VERSION_MASK) - -#define FLASH_NMPA_GPO1_1_CUSTOMER_REVISION_ID_MASK (0xF0U) -#define FLASH_NMPA_GPO1_1_CUSTOMER_REVISION_ID_SHIFT (4U) -/*! CUSTOMER_REVISION_ID - CUSTOMER REVISION ID[3:0] - */ -#define FLASH_NMPA_GPO1_1_CUSTOMER_REVISION_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_1_CUSTOMER_REVISION_ID_SHIFT)) & FLASH_NMPA_GPO1_1_CUSTOMER_REVISION_ID_MASK) - -#define FLASH_NMPA_GPO1_1_FIELD_MASK (0xFFFFFF00U) -#define FLASH_NMPA_GPO1_1_FIELD_SHIFT (8U) -#define FLASH_NMPA_GPO1_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_1_FIELD_SHIFT)) & FLASH_NMPA_GPO1_1_FIELD_MASK) -/*! @} */ - -/*! @name GPO1_2 - GPO1 register 2 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO1_2_HVST_MASK (0x1U) -#define FLASH_NMPA_GPO1_2_HVST_SHIFT (0U) -/*! HVST - High Voltage Stress: 0=not done; 1=done. - */ -#define FLASH_NMPA_GPO1_2_HVST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_2_HVST_SHIFT)) & FLASH_NMPA_GPO1_2_HVST_MASK) - -#define FLASH_NMPA_GPO1_2_FIELD_MASK (0xFFFFFFFEU) -#define FLASH_NMPA_GPO1_2_FIELD_SHIFT (1U) -#define FLASH_NMPA_GPO1_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_2_FIELD_SHIFT)) & FLASH_NMPA_GPO1_2_FIELD_MASK) -/*! @} */ - -/*! @name GPO1_3 - GPO1 register 3 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO1_3_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO1_3_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO1_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_3_FIELD_SHIFT)) & FLASH_NMPA_GPO1_3_FIELD_MASK) -/*! @} */ - -/*! @name GPO1_ARRAY - GPO1 array description */ -/*! @{ */ - -#define FLASH_NMPA_GPO1_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO1_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO1_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_GPO1_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_GPO1_ARRAY */ -#define FLASH_NMPA_GPO1_ARRAY_COUNT (4U) - -/*! @name GPO2_0 - GPO2 register 0 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO2_0_USBHS_PHY_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_GPO2_0_USBHS_PHY_TRIM_VALID_SHIFT (0U) -#define FLASH_NMPA_GPO2_0_USBHS_PHY_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_USBHS_PHY_TRIM_VALID_SHIFT)) & FLASH_NMPA_GPO2_0_USBHS_PHY_TRIM_VALID_MASK) - -#define FLASH_NMPA_GPO2_0_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0x6U) -#define FLASH_NMPA_GPO2_0_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (1U) -#define FLASH_NMPA_GPO2_0_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & FLASH_NMPA_GPO2_0_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK) - -#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_D_CAL_MASK (0x78U) -#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_D_CAL_SHIFT (3U) -#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_D_CAL_SHIFT)) & FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_D_CAL_MASK) - -#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DP_MASK (0xF80U) -#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DP_SHIFT (7U) -#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DP_MASK) - -#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DN_MASK (0x1F000U) -#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DN_SHIFT (12U) -#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DN_MASK) - -#define FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_TST_MASK (0x60000U) -#define FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_TST_SHIFT (17U) -#define FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_TST_SHIFT)) & FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_TST_MASK) - -#define FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x380000U) -#define FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (19U) -#define FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_VBGADJ_MASK) - -#define FLASH_NMPA_GPO2_0_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x1C00000U) -#define FLASH_NMPA_GPO2_0_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (22U) -#define FLASH_NMPA_GPO2_0_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & FLASH_NMPA_GPO2_0_TRIM_PLL_CTRL0_DIV_SEL_MASK) - -#define FLASH_NMPA_GPO2_0_FLASH_SIZE_MASK (0xE000000U) -#define FLASH_NMPA_GPO2_0_FLASH_SIZE_SHIFT (25U) -/*! FLASH_SIZE - (For Niobe4) 000 : 640 KB 001 : 512 KB 010 : 256 KB 011 : 128 KB 100 : 0 KB All - * others : RESERVED (For Niobe4 Mini) FLASH_SIZE[2:0] 000 : 256 KB 001 : 128 KB 010 : 80 KB - * (reserved) 011 : 64 KB 100 : 0 kB (reserved) All others : RESERVED - */ -#define FLASH_NMPA_GPO2_0_FLASH_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_FLASH_SIZE_SHIFT)) & FLASH_NMPA_GPO2_0_FLASH_SIZE_MASK) - -#define FLASH_NMPA_GPO2_0_CPU0_SECURITY_EXTENSION_DISABLE_MASK (0xF0000000U) -#define FLASH_NMPA_GPO2_0_CPU0_SECURITY_EXTENSION_DISABLE_SHIFT (28U) -/*! CPU0_SECURITY_EXTENSION_DISABLE - CPU0_SECURITY_EXTENSION_DISABLE[3:0]: 1010 : CPU0 Security - * Extension is disabled. All Other values: CPU0 Security Extension is enabled. - */ -#define FLASH_NMPA_GPO2_0_CPU0_SECURITY_EXTENSION_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_CPU0_SECURITY_EXTENSION_DISABLE_SHIFT)) & FLASH_NMPA_GPO2_0_CPU0_SECURITY_EXTENSION_DISABLE_MASK) -/*! @} */ - -/*! @name GPO2_1 - GPO2 register 1 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO2_1_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO2_1_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO2_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_1_FIELD_SHIFT)) & FLASH_NMPA_GPO2_1_FIELD_MASK) -/*! @} */ - -/*! @name GPO2_2 - GPO2 register 2 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO2_2_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO2_2_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO2_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_2_FIELD_SHIFT)) & FLASH_NMPA_GPO2_2_FIELD_MASK) -/*! @} */ - -/*! @name GPO2_3 - GPO2 register 3 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO2_3_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO2_3_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO2_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_3_FIELD_SHIFT)) & FLASH_NMPA_GPO2_3_FIELD_MASK) -/*! @} */ - -/*! @name GPO2_ARRAY - GPO2 array description */ -/*! @{ */ - -#define FLASH_NMPA_GPO2_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO2_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO2_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_GPO2_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_GPO2_ARRAY */ -#define FLASH_NMPA_GPO2_ARRAY_COUNT (4U) - -/*! @name GPO3_0 - GPO3 register 0 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO3_0_AUX_BIAS_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_GPO3_0_AUX_BIAS_TRIM_VALID_SHIFT (0U) -#define FLASH_NMPA_GPO3_0_AUX_BIAS_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_AUX_BIAS_TRIM_VALID_SHIFT)) & FLASH_NMPA_GPO3_0_AUX_BIAS_TRIM_VALID_MASK) - -#define FLASH_NMPA_GPO3_0_AUX_BIAS_ITRIM_MASK (0x3EU) -#define FLASH_NMPA_GPO3_0_AUX_BIAS_ITRIM_SHIFT (1U) -#define FLASH_NMPA_GPO3_0_AUX_BIAS_ITRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_AUX_BIAS_ITRIM_SHIFT)) & FLASH_NMPA_GPO3_0_AUX_BIAS_ITRIM_MASK) - -#define FLASH_NMPA_GPO3_0_AUX_BIAS_PTAT_ITRIM_MASK (0x7C0U) -#define FLASH_NMPA_GPO3_0_AUX_BIAS_PTAT_ITRIM_SHIFT (6U) -#define FLASH_NMPA_GPO3_0_AUX_BIAS_PTAT_ITRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_AUX_BIAS_PTAT_ITRIM_SHIFT)) & FLASH_NMPA_GPO3_0_AUX_BIAS_PTAT_ITRIM_MASK) - -#define FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VTRIM_MASK (0xF800U) -#define FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VTRIM_SHIFT (11U) -#define FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VTRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VTRIM_SHIFT)) & FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VTRIM_MASK) - -#define FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VCURVE_TRIM_MASK (0x70000U) -#define FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VCURVE_TRIM_SHIFT (16U) -#define FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VCURVE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VCURVE_TRIM_SHIFT)) & FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VCURVE_TRIM_MASK) - -#define FLASH_NMPA_GPO3_0_FIELD_MASK (0x1F80000U) -#define FLASH_NMPA_GPO3_0_FIELD_SHIFT (19U) -#define FLASH_NMPA_GPO3_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_FIELD_SHIFT)) & FLASH_NMPA_GPO3_0_FIELD_MASK) - -#define FLASH_NMPA_GPO3_0_MODELNUM_EXTENSION_MASK (0xE000000U) -#define FLASH_NMPA_GPO3_0_MODELNUM_EXTENSION_SHIFT (25U) -/*! MODELNUM_EXTENSION - ModelNumber extension[2:0] - */ -#define FLASH_NMPA_GPO3_0_MODELNUM_EXTENSION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_MODELNUM_EXTENSION_SHIFT)) & FLASH_NMPA_GPO3_0_MODELNUM_EXTENSION_MASK) - -#define FLASH_NMPA_GPO3_0_FINAL_TEST_NOT_DONE_MASK (0xF0000000U) -#define FLASH_NMPA_GPO3_0_FINAL_TEST_NOT_DONE_SHIFT (28U) -/*! FINAL_TEST_NOT_DONE - FINAL_TEST_NOT_DONE[3:0]: 1010 : Final Test Not Done. All Other values: Final Test Done. - */ -#define FLASH_NMPA_GPO3_0_FINAL_TEST_NOT_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_FINAL_TEST_NOT_DONE_SHIFT)) & FLASH_NMPA_GPO3_0_FINAL_TEST_NOT_DONE_MASK) -/*! @} */ - -/*! @name GPO3_1 - GPO3 register 1 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO3_1_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO3_1_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO3_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_1_FIELD_SHIFT)) & FLASH_NMPA_GPO3_1_FIELD_MASK) -/*! @} */ - -/*! @name GPO3_2 - GPO3 register 2 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO3_2_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO3_2_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO3_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_2_FIELD_SHIFT)) & FLASH_NMPA_GPO3_2_FIELD_MASK) -/*! @} */ - -/*! @name GPO3_3 - GPO3 register 3 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO3_3_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO3_3_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO3_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_3_FIELD_SHIFT)) & FLASH_NMPA_GPO3_3_FIELD_MASK) -/*! @} */ - -/*! @name GPO3_ARRAY - GPO3 array description */ -/*! @{ */ - -#define FLASH_NMPA_GPO3_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO3_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO3_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_GPO3_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_GPO3_ARRAY */ -#define FLASH_NMPA_GPO3_ARRAY_COUNT (4U) - -/*! @name GPO_CHECKSUM_0 - checksum of the GPO data in words 0 */ -/*! @{ */ - -#define FLASH_NMPA_GPO_CHECKSUM_0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO_CHECKSUM_0_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO_CHECKSUM_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO_CHECKSUM_0_FIELD_SHIFT)) & FLASH_NMPA_GPO_CHECKSUM_0_FIELD_MASK) -/*! @} */ - -/*! @name GPO_CHECKSUM_1 - checksum of the GPO data in words 1 */ -/*! @{ */ - -#define FLASH_NMPA_GPO_CHECKSUM_1_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO_CHECKSUM_1_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO_CHECKSUM_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO_CHECKSUM_1_FIELD_SHIFT)) & FLASH_NMPA_GPO_CHECKSUM_1_FIELD_MASK) -/*! @} */ - -/*! @name GPO_CHECKSUM_2 - checksum of the GPO data in words 2 */ -/*! @{ */ - -#define FLASH_NMPA_GPO_CHECKSUM_2_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO_CHECKSUM_2_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO_CHECKSUM_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO_CHECKSUM_2_FIELD_SHIFT)) & FLASH_NMPA_GPO_CHECKSUM_2_FIELD_MASK) -/*! @} */ - -/*! @name GPO_CHECKSUM_3 - checksum of the GPO data in words 3 */ -/*! @{ */ - -#define FLASH_NMPA_GPO_CHECKSUM_3_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO_CHECKSUM_3_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO_CHECKSUM_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO_CHECKSUM_3_FIELD_SHIFT)) & FLASH_NMPA_GPO_CHECKSUM_3_FIELD_MASK) -/*! @} */ - -/*! @name GPO_CHECKSUM_ARRAY - checksum of the GPO data in words [3:0] */ -/*! @{ */ - -#define FLASH_NMPA_GPO_CHECKSUM_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO_CHECKSUM_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO_CHECKSUM_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO_CHECKSUM_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_GPO_CHECKSUM_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_GPO_CHECKSUM_ARRAY */ -#define FLASH_NMPA_GPO_CHECKSUM_ARRAY_COUNT (4U) - -/*! @name FINAL_TEST_BATCH_ID_0 - */ -/*! @{ */ - -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_0_FIELD_SHIFT (0U) -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_BATCH_ID_0_FIELD_SHIFT)) & FLASH_NMPA_FINAL_TEST_BATCH_ID_0_FIELD_MASK) -/*! @} */ - -/*! @name FINAL_TEST_BATCH_ID_1 - */ -/*! @{ */ - -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_1_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_1_FIELD_SHIFT (0U) -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_BATCH_ID_1_FIELD_SHIFT)) & FLASH_NMPA_FINAL_TEST_BATCH_ID_1_FIELD_MASK) -/*! @} */ - -/*! @name FINAL_TEST_BATCH_ID_2 - */ -/*! @{ */ - -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_2_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_2_FIELD_SHIFT (0U) -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_BATCH_ID_2_FIELD_SHIFT)) & FLASH_NMPA_FINAL_TEST_BATCH_ID_2_FIELD_MASK) -/*! @} */ - -/*! @name FINAL_TEST_BATCH_ID_3 - */ -/*! @{ */ - -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_3_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_3_FIELD_SHIFT (0U) -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_BATCH_ID_3_FIELD_SHIFT)) & FLASH_NMPA_FINAL_TEST_BATCH_ID_3_FIELD_MASK) -/*! @} */ - -/*! @name FINAL_TEST_BATCH_ID_ARRAY - */ -/*! @{ */ - -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_BATCH_ID_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_FINAL_TEST_BATCH_ID_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_FINAL_TEST_BATCH_ID_ARRAY */ -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_ARRAY_COUNT (4U) - -/*! @name DEVICE_TYPE - */ -/*! @{ */ - -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_NUM_MASK (0xFFFFU) -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_NUM_SHIFT (0U) -/*! DEVICE_TYPE_NUM - Device type number. (E.g : LPC5569 stored as 5569 decimal) - */ -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_NUM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_NUM_SHIFT)) & FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_NUM_MASK) - -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_SEC_MASK (0x10000U) -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_SEC_SHIFT (16U) -/*! DEVICE_TYPE_SEC - Security device type: 0: LPC55xxx (Non Secure Familly) 1: LPC55Sxxx (Secure Familly) - */ -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_SEC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_SEC_SHIFT)) & FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_SEC_MASK) - -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PKG_MASK (0xF00000U) -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PKG_SHIFT (20U) -/*! DEVICE_TYPE_PKG - Device package type: 0000 : HLQFP 0001 : HTQFP 0010 : HVQFN 0100 : VFBGA 1000 : WLCSP - */ -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PKG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PKG_SHIFT)) & FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PKG_MASK) - -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PIN_MASK (0xFF000000U) -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PIN_SHIFT (24U) -/*! DEVICE_TYPE_PIN - Number of pins on the package. - */ -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PIN_SHIFT)) & FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PIN_MASK) -/*! @} */ - -/*! @name FINAL_TEST_PROGRAM_VERSION - */ -/*! @{ */ - -#define FLASH_NMPA_FINAL_TEST_PROGRAM_VERSION_PROGRAM_VERSION_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_FINAL_TEST_PROGRAM_VERSION_PROGRAM_VERSION_SHIFT (0U) -/*! PROGRAM_VERSION - PROGRAM_VERSION [xx.yy stored as : 100*x+y] - */ -#define FLASH_NMPA_FINAL_TEST_PROGRAM_VERSION_PROGRAM_VERSION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_PROGRAM_VERSION_PROGRAM_VERSION_SHIFT)) & FLASH_NMPA_FINAL_TEST_PROGRAM_VERSION_PROGRAM_VERSION_MASK) -/*! @} */ - -/*! @name FINAL_TEST_DATE - */ -/*! @{ */ - -#define FLASH_NMPA_FINAL_TEST_DATE_DATE_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_FINAL_TEST_DATE_DATE_SHIFT (0U) -/*! DATE - DATE [stored as : year*10000+month*100+day] - */ -#define FLASH_NMPA_FINAL_TEST_DATE_DATE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_DATE_DATE_SHIFT)) & FLASH_NMPA_FINAL_TEST_DATE_DATE_MASK) -/*! @} */ - -/*! @name FINAL_TEST_TIME - */ -/*! @{ */ - -#define FLASH_NMPA_FINAL_TEST_TIME_TIME_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_FINAL_TEST_TIME_TIME_SHIFT (0U) -/*! TIME - TIME [stored as : hour*10000+minute*100+seconde] - */ -#define FLASH_NMPA_FINAL_TEST_TIME_TIME(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_TIME_TIME_SHIFT)) & FLASH_NMPA_FINAL_TEST_TIME_TIME_MASK) -/*! @} */ - -/*! @name UUID_0 - */ -/*! @{ */ - -#define FLASH_NMPA_UUID_0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_UUID_0_FIELD_SHIFT (0U) -#define FLASH_NMPA_UUID_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_UUID_0_FIELD_SHIFT)) & FLASH_NMPA_UUID_0_FIELD_MASK) -/*! @} */ - -/*! @name UUID_1 - */ -/*! @{ */ - -#define FLASH_NMPA_UUID_1_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_UUID_1_FIELD_SHIFT (0U) -#define FLASH_NMPA_UUID_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_UUID_1_FIELD_SHIFT)) & FLASH_NMPA_UUID_1_FIELD_MASK) -/*! @} */ - -/*! @name UUID_2 - */ -/*! @{ */ - -#define FLASH_NMPA_UUID_2_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_UUID_2_FIELD_SHIFT (0U) -#define FLASH_NMPA_UUID_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_UUID_2_FIELD_SHIFT)) & FLASH_NMPA_UUID_2_FIELD_MASK) -/*! @} */ - -/*! @name UUID_3 - */ -/*! @{ */ - -#define FLASH_NMPA_UUID_3_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_UUID_3_FIELD_SHIFT (0U) -#define FLASH_NMPA_UUID_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_UUID_3_FIELD_SHIFT)) & FLASH_NMPA_UUID_3_FIELD_MASK) -/*! @} */ - -/*! @name UUID_ARRAY - */ -/*! @{ */ - -#define FLASH_NMPA_UUID_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_UUID_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_UUID_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_UUID_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_UUID_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_UUID_ARRAY */ -#define FLASH_NMPA_UUID_ARRAY_COUNT (4U) - -/*! @name WAFER_TEST1_PROGRAM_VERSION - */ -/*! @{ */ - -#define FLASH_NMPA_WAFER_TEST1_PROGRAM_VERSION_WT1_PROGRAM_VERSION_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_WAFER_TEST1_PROGRAM_VERSION_WT1_PROGRAM_VERSION_SHIFT (0U) -/*! WT1_PROGRAM_VERSION - WT1_PROGRAM_VERSION [xx.yy stored as : 100*x+y] - */ -#define FLASH_NMPA_WAFER_TEST1_PROGRAM_VERSION_WT1_PROGRAM_VERSION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_WAFER_TEST1_PROGRAM_VERSION_WT1_PROGRAM_VERSION_SHIFT)) & FLASH_NMPA_WAFER_TEST1_PROGRAM_VERSION_WT1_PROGRAM_VERSION_MASK) -/*! @} */ - -/*! @name WAFER_TEST1_DATE - */ -/*! @{ */ - -#define FLASH_NMPA_WAFER_TEST1_DATE_WT1_DATE_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_WAFER_TEST1_DATE_WT1_DATE_SHIFT (0U) -/*! WT1_DATE - WT1_DATE [stored as : year*10000+month*100+day] - */ -#define FLASH_NMPA_WAFER_TEST1_DATE_WT1_DATE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_WAFER_TEST1_DATE_WT1_DATE_SHIFT)) & FLASH_NMPA_WAFER_TEST1_DATE_WT1_DATE_MASK) -/*! @} */ - -/*! @name WAFER_TEST1_TIME - */ -/*! @{ */ - -#define FLASH_NMPA_WAFER_TEST1_TIME_WT1_TIME_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_WAFER_TEST1_TIME_WT1_TIME_SHIFT (0U) -/*! WT1_TIME - WT1_TIME [stored as : hour*10000+minute*100+seconde] - */ -#define FLASH_NMPA_WAFER_TEST1_TIME_WT1_TIME(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_WAFER_TEST1_TIME_WT1_TIME_SHIFT)) & FLASH_NMPA_WAFER_TEST1_TIME_WT1_TIME_MASK) -/*! @} */ - -/*! @name WAFER_TEST2_PROGRAM_VERSION - */ -/*! @{ */ - -#define FLASH_NMPA_WAFER_TEST2_PROGRAM_VERSION_WT2_PROGRAM_VERSION_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_WAFER_TEST2_PROGRAM_VERSION_WT2_PROGRAM_VERSION_SHIFT (0U) -/*! WT2_PROGRAM_VERSION - WT2_PROGRAM_VERSION [xx.yy stored as : 100*x+y] - */ -#define FLASH_NMPA_WAFER_TEST2_PROGRAM_VERSION_WT2_PROGRAM_VERSION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_WAFER_TEST2_PROGRAM_VERSION_WT2_PROGRAM_VERSION_SHIFT)) & FLASH_NMPA_WAFER_TEST2_PROGRAM_VERSION_WT2_PROGRAM_VERSION_MASK) -/*! @} */ - -/*! @name WAFER_TEST2_DATE - */ -/*! @{ */ - -#define FLASH_NMPA_WAFER_TEST2_DATE_WT2_DATE_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_WAFER_TEST2_DATE_WT2_DATE_SHIFT (0U) -/*! WT2_DATE - WT2_DATE [stored as : year*10000+month*100+day] - */ -#define FLASH_NMPA_WAFER_TEST2_DATE_WT2_DATE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_WAFER_TEST2_DATE_WT2_DATE_SHIFT)) & FLASH_NMPA_WAFER_TEST2_DATE_WT2_DATE_MASK) -/*! @} */ - -/*! @name WAFER_TEST2_TIME - */ -/*! @{ */ - -#define FLASH_NMPA_WAFER_TEST2_TIME_WT2_TIME_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_WAFER_TEST2_TIME_WT2_TIME_SHIFT (0U) -/*! WT2_TIME - WT2_TIME [stored as : hour*10000+minute*100+seconde] - */ -#define FLASH_NMPA_WAFER_TEST2_TIME_WT2_TIME(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_WAFER_TEST2_TIME_WT2_TIME_SHIFT)) & FLASH_NMPA_WAFER_TEST2_TIME_WT2_TIME_MASK) -/*! @} */ - -/*! @name USBCFG - */ -/*! @{ */ - -#define FLASH_NMPA_USBCFG_XO32M_READY_TIME_OUT_MS_MASK (0xFFU) -#define FLASH_NMPA_USBCFG_XO32M_READY_TIME_OUT_MS_SHIFT (0U) -#define FLASH_NMPA_USBCFG_XO32M_READY_TIME_OUT_MS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_USBCFG_XO32M_READY_TIME_OUT_MS_SHIFT)) & FLASH_NMPA_USBCFG_XO32M_READY_TIME_OUT_MS_MASK) - -#define FLASH_NMPA_USBCFG_USB_SPEED_MASK (0xFF00U) -#define FLASH_NMPA_USBCFG_USB_SPEED_SHIFT (8U) -/*! USB_SPEED - USB_SPEED[7:0]= 0x00 : USB High Speed Module used for ISP 0x01 : USB Full SPeed - * Module used for ISP 0x02 : Neither USB High Speed module nor USB Full Speed module used for ISP - * 0x03 - 0xFF : RESERVED - */ -#define FLASH_NMPA_USBCFG_USB_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_USBCFG_USB_SPEED_SHIFT)) & FLASH_NMPA_USBCFG_USB_SPEED_MASK) - -#define FLASH_NMPA_USBCFG_USB_USE_XO32M_CAPA_BANKS_MASK (0x10000U) -#define FLASH_NMPA_USBCFG_USB_USE_XO32M_CAPA_BANKS_SHIFT (16U) -/*! USB_USE_XO32M_CAPA_BANKS - Enable the use of Crystal 32 MHz internal Capa Banks during the - * configuration of the High Speed USB for ISP: 0: Disable Crystal 32 MHz CapaBanks. 1: Enable Crystal - * 32 MHz CapaBanks. - */ -#define FLASH_NMPA_USBCFG_USB_USE_XO32M_CAPA_BANKS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_USBCFG_USB_USE_XO32M_CAPA_BANKS_SHIFT)) & FLASH_NMPA_USBCFG_USB_USE_XO32M_CAPA_BANKS_MASK) -/*! @} */ - -/*! @name PERIPHENCFG - */ -/*! @{ */ - -#define FLASH_NMPA_PERIPHENCFG_PERIPHERAL_CONFIGURATION_MASK (0xFFFFU) -#define FLASH_NMPA_PERIPHENCFG_PERIPHERAL_CONFIGURATION_SHIFT (0U) -#define FLASH_NMPA_PERIPHENCFG_PERIPHERAL_CONFIGURATION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PERIPHENCFG_PERIPHERAL_CONFIGURATION_SHIFT)) & FLASH_NMPA_PERIPHENCFG_PERIPHERAL_CONFIGURATION_MASK) - -#define FLASH_NMPA_PERIPHENCFG_CPU1_ENABLE_MASK (0x80000000U) -#define FLASH_NMPA_PERIPHENCFG_CPU1_ENABLE_SHIFT (31U) -#define FLASH_NMPA_PERIPHENCFG_CPU1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PERIPHENCFG_CPU1_ENABLE_SHIFT)) & FLASH_NMPA_PERIPHENCFG_CPU1_ENABLE_MASK) -/*! @} */ - -/*! @name RAMSIZECFG - */ -/*! @{ */ - -#define FLASH_NMPA_RAMSIZECFG_SRAM_CONFIGURATION_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_RAMSIZECFG_SRAM_CONFIGURATION_SHIFT (0U) -#define FLASH_NMPA_RAMSIZECFG_SRAM_CONFIGURATION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_RAMSIZECFG_SRAM_CONFIGURATION_SHIFT)) & FLASH_NMPA_RAMSIZECFG_SRAM_CONFIGURATION_MASK) -/*! @} */ - -/*! @name FLASHSIZECFG - */ -/*! @{ */ - -#define FLASH_NMPA_FLASHSIZECFG_FLASH_CONFIGURATION_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_FLASHSIZECFG_FLASH_CONFIGURATION_SHIFT (0U) -#define FLASH_NMPA_FLASHSIZECFG_FLASH_CONFIGURATION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FLASHSIZECFG_FLASH_CONFIGURATION_SHIFT)) & FLASH_NMPA_FLASHSIZECFG_FLASH_CONFIGURATION_MASK) -/*! @} */ - -/*! @name RINGO_0 - */ -/*! @{ */ - -#define FLASH_NMPA_RINGO_0_RINGO_0_CTRL_VALID_MASK (0x1U) -#define FLASH_NMPA_RINGO_0_RINGO_0_CTRL_VALID_SHIFT (0U) -/*! RINGO_0_CTRL_VALID - 1: RINGO_0_CTRL is valid. - */ -#define FLASH_NMPA_RINGO_0_RINGO_0_CTRL_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_RINGO_0_RINGO_0_CTRL_VALID_SHIFT)) & FLASH_NMPA_RINGO_0_RINGO_0_CTRL_VALID_MASK) - -#define FLASH_NMPA_RINGO_0_RINGO_0_CTRL_MASK (0xFFFFFFFEU) -#define FLASH_NMPA_RINGO_0_RINGO_0_CTRL_SHIFT (1U) -/*! RINGO_0_CTRL - To copy RINGO_0_CTRL = ANACTRL->RINGO0_CTRL[30:0] - */ -#define FLASH_NMPA_RINGO_0_RINGO_0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_RINGO_0_RINGO_0_CTRL_SHIFT)) & FLASH_NMPA_RINGO_0_RINGO_0_CTRL_MASK) -/*! @} */ - -/*! @name RINGO_1 - */ -/*! @{ */ - -#define FLASH_NMPA_RINGO_1_RINGO_1_CTRL_VALID_MASK (0x1U) -#define FLASH_NMPA_RINGO_1_RINGO_1_CTRL_VALID_SHIFT (0U) -/*! RINGO_1_CTRL_VALID - 1: RINGO_1_CTRL is valid. - */ -#define FLASH_NMPA_RINGO_1_RINGO_1_CTRL_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_RINGO_1_RINGO_1_CTRL_VALID_SHIFT)) & FLASH_NMPA_RINGO_1_RINGO_1_CTRL_VALID_MASK) - -#define FLASH_NMPA_RINGO_1_RINGO_1_CTRL_MASK (0xFFFFFFFEU) -#define FLASH_NMPA_RINGO_1_RINGO_1_CTRL_SHIFT (1U) -/*! RINGO_1_CTRL - To copy RINGO_1_CTRL = ANACTRL->RINGO1_CTRL[30:0] - */ -#define FLASH_NMPA_RINGO_1_RINGO_1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_RINGO_1_RINGO_1_CTRL_SHIFT)) & FLASH_NMPA_RINGO_1_RINGO_1_CTRL_MASK) -/*! @} */ - -/*! @name RINGO_2 - */ -/*! @{ */ - -#define FLASH_NMPA_RINGO_2_RINGO_2_CTRL_VALID_MASK (0x1U) -#define FLASH_NMPA_RINGO_2_RINGO_2_CTRL_VALID_SHIFT (0U) -/*! RINGO_2_CTRL_VALID - 1: RINGO_2_CTRL is valid. - */ -#define FLASH_NMPA_RINGO_2_RINGO_2_CTRL_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_RINGO_2_RINGO_2_CTRL_VALID_SHIFT)) & FLASH_NMPA_RINGO_2_RINGO_2_CTRL_VALID_MASK) - -#define FLASH_NMPA_RINGO_2_RINGO_2_CTRL_MASK (0xFFFFFFFEU) -#define FLASH_NMPA_RINGO_2_RINGO_2_CTRL_SHIFT (1U) -/*! RINGO_2_CTRL - To copy RINGO_2_CTRL = ANACTRL->RINGO2_CTRL[30:0] - */ -#define FLASH_NMPA_RINGO_2_RINGO_2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_RINGO_2_RINGO_2_CTRL_SHIFT)) & FLASH_NMPA_RINGO_2_RINGO_2_CTRL_MASK) -/*! @} */ - -/*! @name FRO_192MHZ - */ -/*! @{ */ - -#define FLASH_NMPA_FRO_192MHZ_FRO192M_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_FRO_192MHZ_FRO192M_TRIM_VALID_SHIFT (0U) -#define FLASH_NMPA_FRO_192MHZ_FRO192M_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FRO_192MHZ_FRO192M_TRIM_VALID_SHIFT)) & FLASH_NMPA_FRO_192MHZ_FRO192M_TRIM_VALID_MASK) - -#define FLASH_NMPA_FRO_192MHZ_FRO192M_BIASTRIM_MASK (0x7EU) -#define FLASH_NMPA_FRO_192MHZ_FRO192M_BIASTRIM_SHIFT (1U) -/*! FRO192M_BIASTRIM - FRO192M_BIASTRIM[5:0]. - */ -#define FLASH_NMPA_FRO_192MHZ_FRO192M_BIASTRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FRO_192MHZ_FRO192M_BIASTRIM_SHIFT)) & FLASH_NMPA_FRO_192MHZ_FRO192M_BIASTRIM_MASK) - -#define FLASH_NMPA_FRO_192MHZ_FRO192M_TEMPTRIM_MASK (0x7F00U) -#define FLASH_NMPA_FRO_192MHZ_FRO192M_TEMPTRIM_SHIFT (8U) -/*! FRO192M_TEMPTRIM - FRO192M_TEMPTRIM[6:0]. - */ -#define FLASH_NMPA_FRO_192MHZ_FRO192M_TEMPTRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FRO_192MHZ_FRO192M_TEMPTRIM_SHIFT)) & FLASH_NMPA_FRO_192MHZ_FRO192M_TEMPTRIM_MASK) - -#define FLASH_NMPA_FRO_192MHZ_FRO192M_DACTRIM_MASK (0x1FE0000U) -#define FLASH_NMPA_FRO_192MHZ_FRO192M_DACTRIM_SHIFT (17U) -/*! FRO192M_DACTRIM - FRO192M_DACTRIM[7:0]. - */ -#define FLASH_NMPA_FRO_192MHZ_FRO192M_DACTRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FRO_192MHZ_FRO192M_DACTRIM_SHIFT)) & FLASH_NMPA_FRO_192MHZ_FRO192M_DACTRIM_MASK) -/*! @} */ - -/*! @name XO_32MHZ - */ -/*! @{ */ - -#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_TRIM_VALID_SHIFT (0U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XIN_TRIM_VALID_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XIN_TRIM_VALID_MASK) - -#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_6PF_MASK (0xFEU) -#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_6PF_SHIFT (1U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_6PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_6PF_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_6PF_MASK) - -#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_8PF_MASK (0x7F00U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_8PF_SHIFT (8U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_8PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_8PF_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_8PF_MASK) - -#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_TRIM_VALID_MASK (0x8000U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_TRIM_VALID_SHIFT (15U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XOUT_TRIM_VALID_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XOUT_TRIM_VALID_MASK) - -#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_6PF_MASK (0x7F0000U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_6PF_SHIFT (16U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_6PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_6PF_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_6PF_MASK) - -#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_8PF_MASK (0x3F800000U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_8PF_SHIFT (23U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_8PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_8PF_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_8PF_MASK) - -#define FLASH_NMPA_XO_32MHZ_XO32M_XO_SLAVE_STATUS_MASK (0x40000000U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XO_SLAVE_STATUS_SHIFT (30U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XO_SLAVE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XO_SLAVE_STATUS_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XO_SLAVE_STATUS_MASK) - -#define FLASH_NMPA_XO_32MHZ_XO32M_XO_AC_BUF_STATUS_MASK (0x80000000U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XO_AC_BUF_STATUS_SHIFT (31U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XO_AC_BUF_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XO_AC_BUF_STATUS_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XO_AC_BUF_STATUS_MASK) -/*! @} */ - -/*! @name XO_32KHZ - */ -/*! @{ */ - -#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_TRIM_VALID_SHIFT (0U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32KHZ_XO32K_XIN_TRIM_VALID_SHIFT)) & FLASH_NMPA_XO_32KHZ_XO32K_XIN_TRIM_VALID_MASK) - -#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_6PF_MASK (0xFEU) -#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_6PF_SHIFT (1U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_6PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_6PF_SHIFT)) & FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_6PF_MASK) - -#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_8PF_MASK (0x7F00U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_8PF_SHIFT (8U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_8PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_8PF_SHIFT)) & FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_8PF_MASK) - -#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_TRIM_VALID_MASK (0x8000U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_TRIM_VALID_SHIFT (15U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32KHZ_XO32K_XOUT_TRIM_VALID_SHIFT)) & FLASH_NMPA_XO_32KHZ_XO32K_XOUT_TRIM_VALID_MASK) - -#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_6PF_MASK (0x7F0000U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_6PF_SHIFT (16U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_6PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_6PF_SHIFT)) & FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_6PF_MASK) - -#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_8PF_MASK (0x3F800000U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_8PF_SHIFT (23U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_8PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_8PF_SHIFT)) & FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_8PF_MASK) -/*! @} */ - -/*! @name FRO_1MHZ - */ -/*! @{ */ - -#define FLASH_NMPA_FRO_1MHZ_FRO1M_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_FRO_1MHZ_FRO1M_TRIM_VALID_SHIFT (0U) -#define FLASH_NMPA_FRO_1MHZ_FRO1M_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FRO_1MHZ_FRO1M_TRIM_VALID_SHIFT)) & FLASH_NMPA_FRO_1MHZ_FRO1M_TRIM_VALID_MASK) - -#define FLASH_NMPA_FRO_1MHZ_FRO1M_FREQSEL_MASK (0xFEU) -#define FLASH_NMPA_FRO_1MHZ_FRO1M_FREQSEL_SHIFT (1U) -/*! FRO1M_FREQSEL - Frequency trimming bits. - */ -#define FLASH_NMPA_FRO_1MHZ_FRO1M_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FRO_1MHZ_FRO1M_FREQSEL_SHIFT)) & FLASH_NMPA_FRO_1MHZ_FRO1M_FREQSEL_MASK) -/*! @} */ - -/*! @name DCDC_POWER_PROFILE_HIGH_0 - */ -/*! @{ */ - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DCDC_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DCDC_TRIM_VALID_SHIFT (0U) -/*! DCDC_TRIM_VALID - DCDC is trimed. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DCDC_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DCDC_TRIM_VALID_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DCDC_TRIM_VALID_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_RC_MASK (0x7EU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_RC_SHIFT (1U) -/*! RC - Constant On-Time calibration. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_RC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_RC_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_RC_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICOMP_MASK (0x180U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICOMP_SHIFT (7U) -/*! ICOMP - Select the type of ZCD comparator. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICOMP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICOMP_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICOMP_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ISEL_MASK (0x600U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ISEL_SHIFT (9U) -/*! ISEL - Alter Internal biasing currents. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ISEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ISEL_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ISEL_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICENABLE_MASK (0x800U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICENABLE_SHIFT (11U) -/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_TMOS_MASK (0x1F000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_TMOS_SHIFT (12U) -/*! TMOS - One-shot generator reference current trimming signal. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_TMOS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_TMOS_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_TMOS_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DISABLEISENSE_MASK (0x20000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DISABLEISENSE_SHIFT (17U) -/*! DISABLEISENSE - Disable Current sensing. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DISABLEISENSE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DISABLEISENSE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DISABLEISENSE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_MASK (0x3C0000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_SHIFT (18U) -/*! VOUT - Set output regulation voltage. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_SLICINGENABLE_MASK (0x400000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_SLICINGENABLE_SHIFT (22U) -/*! SLICINGENABLE - Enable staggered switching of power switches. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_SLICINGENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_SLICINGENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_SLICINGENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_INDUCTORCLAMPENABLE_MASK (0x800000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_INDUCTORCLAMPENABLE_SHIFT (23U) -/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_INDUCTORCLAMPENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_INDUCTORCLAMPENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_INDUCTORCLAMPENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_PWD_MASK (0xF000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_PWD_SHIFT (24U) -/*! VOUT_PWD - Set output regulation voltage during Deep Sleep. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_PWD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_PWD_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_PWD_MASK) -/*! @} */ - -/*! @name DCDC_POWER_PROFILE_HIGH_1 - */ -/*! @{ */ - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RTRIMOFFET_MASK (0xFU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RTRIMOFFET_SHIFT (0U) -/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RTRIMOFFET(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RTRIMOFFET_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RTRIMOFFET_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RSENSETRIM_MASK (0xF0U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RSENSETRIM_SHIFT (4U) -/*! RSENSETRIM - Adjust Max inductor peak current limiting. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RSENSETRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RSENSETRIM_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RSENSETRIM_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTENABLE_MASK (0x100U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTENABLE_SHIFT (8U) -/*! DTESTENABLE - Enable Digital test signals. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETCURVE_MASK (0x600U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETCURVE_SHIFT (9U) -/*! SETCURVE - Bandgap calibration parameter. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETCURVE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETCURVE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETCURVE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETDC_MASK (0x7800U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETDC_SHIFT (11U) -/*! SETDC - Bandgap calibration parameter. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETDC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETDC_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETDC_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTSEL_MASK (0x38000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTSEL_SHIFT (15U) -/*! DTESTSEL - Select the output signal for test. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTSEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTSEL_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTSEL_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ISCALEENABLE_MASK (0x40000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ISCALEENABLE_SHIFT (18U) -/*! ISCALEENABLE - Modify COT behavior. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ISCALEENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ISCALEENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ISCALEENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEBYPASS_MASK (0x80000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEBYPASS_SHIFT (19U) -/*! FORCEBYPASS - Force bypass mode. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEBYPASS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEBYPASS_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEBYPASS_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TRIMAUTOCOT_MASK (0xF00000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TRIMAUTOCOT_SHIFT (20U) -/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TRIMAUTOCOT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TRIMAUTOCOT_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TRIMAUTOCOT_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEFULLCYCLE_MASK (0x1000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEFULLCYCLE_SHIFT (24U) -/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEFULLCYCLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEFULLCYCLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEFULLCYCLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_LCENABLE_MASK (0x2000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_LCENABLE_SHIFT (25U) -/*! LCENABLE - Change the range of the peak detector of current inside the inductor. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_LCENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_LCENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_LCENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFF_MASK (0x7C000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFF_SHIFT (26U) -/*! TOFF - Constant Off-Time calibration input. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFF_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFF_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFFENABLE_MASK (0x80000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFFENABLE_SHIFT (31U) -/*! TOFFENABLE - Enable Constant Off-Time feature. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFFENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFFENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFFENABLE_MASK) -/*! @} */ - -/*! @name DCDC_POWER_PROFILE_HIGH_ARRAY - */ -/*! @{ */ - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY_COUNT (2U) - -/*! @name DCDC_POWER_PROFILE_LOW_0 - */ -/*! @{ */ - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DCDC_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DCDC_TRIM_VALID_SHIFT (0U) -/*! DCDC_TRIM_VALID - DCDC is trimed. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DCDC_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DCDC_TRIM_VALID_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DCDC_TRIM_VALID_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_RC_MASK (0x7EU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_RC_SHIFT (1U) -/*! RC - Constant On-Time calibration. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_RC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_RC_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_RC_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICOMP_MASK (0x180U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICOMP_SHIFT (7U) -/*! ICOMP - Select the type of ZCD comparator. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICOMP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICOMP_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICOMP_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ISEL_MASK (0x600U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ISEL_SHIFT (9U) -/*! ISEL - Alter Internal biasing currents. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ISEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ISEL_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ISEL_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICENABLE_MASK (0x800U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICENABLE_SHIFT (11U) -/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_TMOS_MASK (0x1F000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_TMOS_SHIFT (12U) -/*! TMOS - One-shot generator reference current trimming signal. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_TMOS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_TMOS_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_TMOS_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DISABLEISENSE_MASK (0x20000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DISABLEISENSE_SHIFT (17U) -/*! DISABLEISENSE - Disable Current sensing. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DISABLEISENSE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DISABLEISENSE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DISABLEISENSE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_MASK (0x3C0000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_SHIFT (18U) -/*! VOUT - Set output regulation voltage. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_SLICINGENABLE_MASK (0x400000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_SLICINGENABLE_SHIFT (22U) -/*! SLICINGENABLE - Enable staggered switching of power switches. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_SLICINGENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_SLICINGENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_SLICINGENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_INDUCTORCLAMPENABLE_MASK (0x800000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_INDUCTORCLAMPENABLE_SHIFT (23U) -/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_INDUCTORCLAMPENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_INDUCTORCLAMPENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_INDUCTORCLAMPENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_PWD_MASK (0xF000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_PWD_SHIFT (24U) -/*! VOUT_PWD - Set output regulation voltage during Deep Sleep. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_PWD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_PWD_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_PWD_MASK) -/*! @} */ - -/*! @name DCDC_POWER_PROFILE_LOW_1 - */ -/*! @{ */ - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RTRIMOFFET_MASK (0xFU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RTRIMOFFET_SHIFT (0U) -/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RTRIMOFFET(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RTRIMOFFET_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RTRIMOFFET_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RSENSETRIM_MASK (0xF0U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RSENSETRIM_SHIFT (4U) -/*! RSENSETRIM - Adjust Max inductor peak current limiting. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RSENSETRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RSENSETRIM_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RSENSETRIM_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTENABLE_MASK (0x100U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTENABLE_SHIFT (8U) -/*! DTESTENABLE - Enable Digital test signals. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETCURVE_MASK (0x600U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETCURVE_SHIFT (9U) -/*! SETCURVE - Bandgap calibration parameter. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETCURVE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETCURVE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETCURVE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETDC_MASK (0x7800U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETDC_SHIFT (11U) -/*! SETDC - Bandgap calibration parameter. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETDC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETDC_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETDC_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTSEL_MASK (0x38000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTSEL_SHIFT (15U) -/*! DTESTSEL - Select the output signal for test. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTSEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTSEL_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTSEL_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ISCALEENABLE_MASK (0x40000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ISCALEENABLE_SHIFT (18U) -/*! ISCALEENABLE - Modify COT behavior. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ISCALEENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ISCALEENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ISCALEENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEBYPASS_MASK (0x80000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEBYPASS_SHIFT (19U) -/*! FORCEBYPASS - Force bypass mode. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEBYPASS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEBYPASS_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEBYPASS_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TRIMAUTOCOT_MASK (0xF00000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TRIMAUTOCOT_SHIFT (20U) -/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TRIMAUTOCOT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TRIMAUTOCOT_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TRIMAUTOCOT_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEFULLCYCLE_MASK (0x1000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEFULLCYCLE_SHIFT (24U) -/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEFULLCYCLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEFULLCYCLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEFULLCYCLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_LCENABLE_MASK (0x2000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_LCENABLE_SHIFT (25U) -/*! LCENABLE - Change the range of the peak detector of current inside the inductor. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_LCENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_LCENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_LCENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFF_MASK (0x7C000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFF_SHIFT (26U) -/*! TOFF - Constant Off-Time calibration input. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFF_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFF_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFFENABLE_MASK (0x80000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFFENABLE_SHIFT (31U) -/*! TOFFENABLE - Enable Constant Off-Time feature. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFFENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFFENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFFENABLE_MASK) -/*! @} */ - -/*! @name DCDC_POWER_PROFILE_LOW_ARRAY - */ -/*! @{ */ - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY_COUNT (2U) - -/*! @name DCDC_POWER_PROFILE_MEDIUM_0 - */ -/*! @{ */ - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DCDC_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DCDC_TRIM_VALID_SHIFT (0U) -/*! DCDC_TRIM_VALID - DCDC is trimed. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DCDC_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DCDC_TRIM_VALID_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DCDC_TRIM_VALID_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_RC_MASK (0x7EU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_RC_SHIFT (1U) -/*! RC - Constant On-Time calibration. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_RC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_RC_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_RC_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICOMP_MASK (0x180U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICOMP_SHIFT (7U) -/*! ICOMP - Select the type of ZCD comparator. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICOMP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICOMP_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICOMP_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ISEL_MASK (0x600U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ISEL_SHIFT (9U) -/*! ISEL - Alter Internal biasing currents. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ISEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ISEL_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ISEL_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICENABLE_MASK (0x800U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICENABLE_SHIFT (11U) -/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_TMOS_MASK (0x1F000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_TMOS_SHIFT (12U) -/*! TMOS - One-shot generator reference current trimming signal. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_TMOS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_TMOS_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_TMOS_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DISABLEISENSE_MASK (0x20000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DISABLEISENSE_SHIFT (17U) -/*! DISABLEISENSE - Disable Current sensing. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DISABLEISENSE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DISABLEISENSE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DISABLEISENSE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_MASK (0x3C0000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_SHIFT (18U) -/*! VOUT - Set output regulation voltage. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_SLICINGENABLE_MASK (0x400000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_SLICINGENABLE_SHIFT (22U) -/*! SLICINGENABLE - Enable staggered switching of power switches. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_SLICINGENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_SLICINGENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_SLICINGENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_INDUCTORCLAMPENABLE_MASK (0x800000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_INDUCTORCLAMPENABLE_SHIFT (23U) -/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_INDUCTORCLAMPENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_INDUCTORCLAMPENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_INDUCTORCLAMPENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_PWD_MASK (0xF000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_PWD_SHIFT (24U) -/*! VOUT_PWD - Set output regulation voltage during Deep Sleep. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_PWD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_PWD_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_PWD_MASK) -/*! @} */ - -/*! @name DCDC_POWER_PROFILE_MEDIUM_1 - */ -/*! @{ */ - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RTRIMOFFET_MASK (0xFU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RTRIMOFFET_SHIFT (0U) -/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RTRIMOFFET(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RTRIMOFFET_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RTRIMOFFET_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RSENSETRIM_MASK (0xF0U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RSENSETRIM_SHIFT (4U) -/*! RSENSETRIM - Adjust Max inductor peak current limiting. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RSENSETRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RSENSETRIM_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RSENSETRIM_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTENABLE_MASK (0x100U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTENABLE_SHIFT (8U) -/*! DTESTENABLE - Enable Digital test signals. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETCURVE_MASK (0x600U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETCURVE_SHIFT (9U) -/*! SETCURVE - Bandgap calibration parameter. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETCURVE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETCURVE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETCURVE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETDC_MASK (0x7800U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETDC_SHIFT (11U) -/*! SETDC - Bandgap calibration parameter. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETDC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETDC_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETDC_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTSEL_MASK (0x38000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTSEL_SHIFT (15U) -/*! DTESTSEL - Select the output signal for test. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTSEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTSEL_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTSEL_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ISCALEENABLE_MASK (0x40000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ISCALEENABLE_SHIFT (18U) -/*! ISCALEENABLE - Modify COT behavior. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ISCALEENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ISCALEENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ISCALEENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEBYPASS_MASK (0x80000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEBYPASS_SHIFT (19U) -/*! FORCEBYPASS - Force bypass mode. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEBYPASS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEBYPASS_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEBYPASS_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TRIMAUTOCOT_MASK (0xF00000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TRIMAUTOCOT_SHIFT (20U) -/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TRIMAUTOCOT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TRIMAUTOCOT_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TRIMAUTOCOT_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEFULLCYCLE_MASK (0x1000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEFULLCYCLE_SHIFT (24U) -/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEFULLCYCLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEFULLCYCLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEFULLCYCLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_LCENABLE_MASK (0x2000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_LCENABLE_SHIFT (25U) -/*! LCENABLE - Change the range of the peak detector of current inside the inductor. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_LCENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_LCENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_LCENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFF_MASK (0x7C000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFF_SHIFT (26U) -/*! TOFF - Constant Off-Time calibration input. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFF_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFF_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFFENABLE_MASK (0x80000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFFENABLE_SHIFT (31U) -/*! TOFFENABLE - Enable Constant Off-Time feature. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFFENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFFENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFFENABLE_MASK) -/*! @} */ - -/*! @name DCDC_POWER_PROFILE_MEDIUM_ARRAY - */ -/*! @{ */ - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY_COUNT (2U) - -/*! @name BOD - */ -/*! @{ */ - -#define FLASH_NMPA_BOD_BOD_VBAT_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_BOD_BOD_VBAT_TRIM_VALID_SHIFT (0U) -#define FLASH_NMPA_BOD_BOD_VBAT_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_BOD_BOD_VBAT_TRIM_VALID_SHIFT)) & FLASH_NMPA_BOD_BOD_VBAT_TRIM_VALID_MASK) - -#define FLASH_NMPA_BOD_BOD_VBAT_TRIGLVL_MASK (0x3EU) -#define FLASH_NMPA_BOD_BOD_VBAT_TRIGLVL_SHIFT (1U) -#define FLASH_NMPA_BOD_BOD_VBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_BOD_BOD_VBAT_TRIGLVL_SHIFT)) & FLASH_NMPA_BOD_BOD_VBAT_TRIGLVL_MASK) - -#define FLASH_NMPA_BOD_BOD_VBAT_HYST_MASK (0xC0U) -#define FLASH_NMPA_BOD_BOD_VBAT_HYST_SHIFT (6U) -#define FLASH_NMPA_BOD_BOD_VBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_BOD_BOD_VBAT_HYST_SHIFT)) & FLASH_NMPA_BOD_BOD_VBAT_HYST_MASK) - -#define FLASH_NMPA_BOD_BOD_CORE_TRIM_VALID_MASK (0x10000U) -#define FLASH_NMPA_BOD_BOD_CORE_TRIM_VALID_SHIFT (16U) -#define FLASH_NMPA_BOD_BOD_CORE_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_BOD_BOD_CORE_TRIM_VALID_SHIFT)) & FLASH_NMPA_BOD_BOD_CORE_TRIM_VALID_MASK) - -#define FLASH_NMPA_BOD_BOD_CORE_TRIGLVL_MASK (0xE0000U) -#define FLASH_NMPA_BOD_BOD_CORE_TRIGLVL_SHIFT (17U) -#define FLASH_NMPA_BOD_BOD_CORE_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_BOD_BOD_CORE_TRIGLVL_SHIFT)) & FLASH_NMPA_BOD_BOD_CORE_TRIGLVL_MASK) - -#define FLASH_NMPA_BOD_BOD_CORE_HYST_MASK (0x600000U) -#define FLASH_NMPA_BOD_BOD_CORE_HYST_SHIFT (21U) -#define FLASH_NMPA_BOD_BOD_CORE_HYST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_BOD_BOD_CORE_HYST_SHIFT)) & FLASH_NMPA_BOD_BOD_CORE_HYST_MASK) -/*! @} */ - -/*! @name LDO_AO - */ -/*! @{ */ - -#define FLASH_NMPA_LDO_AO_ACTIVE_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_LDO_AO_ACTIVE_TRIM_VALID_SHIFT (0U) -#define FLASH_NMPA_LDO_AO_ACTIVE_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_ACTIVE_TRIM_VALID_SHIFT)) & FLASH_NMPA_LDO_AO_ACTIVE_TRIM_VALID_MASK) - -#define FLASH_NMPA_LDO_AO_ACTIVE_TRIM_MASK (0x3EU) -#define FLASH_NMPA_LDO_AO_ACTIVE_TRIM_SHIFT (1U) -#define FLASH_NMPA_LDO_AO_ACTIVE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_ACTIVE_TRIM_SHIFT)) & FLASH_NMPA_LDO_AO_ACTIVE_TRIM_MASK) - -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK (0x100U) -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_SHIFT (8U) -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_SHIFT)) & FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK) - -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK (0x3E00U) -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT (9U) -#define FLASH_NMPA_LDO_AO_DSLP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT)) & FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK) - -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK (0x10000U) -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_SHIFT (16U) -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_SHIFT)) & FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK) - -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK (0x3E0000U) -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT (17U) -#define FLASH_NMPA_LDO_AO_PDWN_TRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT)) & FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK) - -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK (0x1000000U) -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_SHIFT (24U) -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_SHIFT)) & FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK) - -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK (0x3E000000U) -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT (25U) -#define FLASH_NMPA_LDO_AO_DPDW_TRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT)) & FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK) -/*! @} */ - -/*! @name SDIO_DELAY - */ -/*! @{ */ - -#define FLASH_NMPA_SDIO_DELAY_SDIO_0_VALID_MASK (0x1U) -#define FLASH_NMPA_SDIO_DELAY_SDIO_0_VALID_SHIFT (0U) -#define FLASH_NMPA_SDIO_DELAY_SDIO_0_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_SDIO_DELAY_SDIO_0_VALID_SHIFT)) & FLASH_NMPA_SDIO_DELAY_SDIO_0_VALID_MASK) - -#define FLASH_NMPA_SDIO_DELAY_SDIO_0_DELAY_MASK (0x7FEU) -#define FLASH_NMPA_SDIO_DELAY_SDIO_0_DELAY_SHIFT (1U) -/*! SDIO_0_DELAY - SDIO_0_DELAY (unit: 100 ps). - */ -#define FLASH_NMPA_SDIO_DELAY_SDIO_0_DELAY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_SDIO_DELAY_SDIO_0_DELAY_SHIFT)) & FLASH_NMPA_SDIO_DELAY_SDIO_0_DELAY_MASK) -/*! @} */ - -/*! @name AUX_BIAS_CURVE_AMBIENT_0 - */ -/*! @{ */ - -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_0_MASK (0xFFFFU) -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_0_SHIFT (0U) -/*! VREF1VCURVETRIM_0 - VREF1VCURVETRIM_0 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_0_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_0_MASK) - -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_1_MASK (0xFFFF0000U) -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_1_SHIFT (16U) -/*! VREF1VCURVETRIM_1 - VREF1VCURVETRIM_1 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_1_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_1_MASK) -/*! @} */ - -/*! @name AUX_BIAS_CURVE_AMBIENT_1 - */ -/*! @{ */ - -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_2_MASK (0xFFFFU) -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_2_SHIFT (0U) -/*! VREF1VCURVETRIM_2 - VREF1VCURVETRIM_2 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_2_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_2_MASK) - -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_3_MASK (0xFFFF0000U) -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_3_SHIFT (16U) -/*! VREF1VCURVETRIM_3 - VREF1VCURVETRIM_3 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_3_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_3_MASK) -/*! @} */ - -/*! @name AUX_BIAS_CURVE_AMBIENT_2 - */ -/*! @{ */ - -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_4_MASK (0xFFFFU) -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_4_SHIFT (0U) -/*! VREF1VCURVETRIM_4 - VREF1VCURVETRIM_4 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_4(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_4_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_4_MASK) - -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_5_MASK (0xFFFF0000U) -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_5_SHIFT (16U) -/*! VREF1VCURVETRIM_5 - VREF1VCURVETRIM_5 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_5(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_5_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_5_MASK) -/*! @} */ - -/*! @name AUX_BIAS_CURVE_AMBIENT_3 - */ -/*! @{ */ - -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_6_MASK (0xFFFFU) -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_6_SHIFT (0U) -/*! VREF1VCURVETRIM_6 - VREF1VCURVETRIM_6 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_6(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_6_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_6_MASK) - -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_7_MASK (0xFFFF0000U) -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_7_SHIFT (16U) -/*! VREF1VCURVETRIM_7 - VREF1VCURVETRIM_7 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_7(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_7_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_7_MASK) -/*! @} */ - -/*! @name AUX_BIAS_CURVE_AMBIENT_ARRAY - Aux Bias Curve Ambient (30degC) */ -/*! @{ */ - -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_ARRAY */ -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_ARRAY_COUNT (4U) - -/*! @name AUX_BIAS_CURVE_TEMP_0 - */ -/*! @{ */ - -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_0_MASK (0xFFFFU) -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_0_SHIFT (0U) -/*! VREF1VCURVETRIM_0 - VREF1VCURVETRIM_0 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_0_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_0_MASK) - -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_1_MASK (0xFFFF0000U) -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_1_SHIFT (16U) -/*! VREF1VCURVETRIM_1 - VREF1VCURVETRIM_1 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_1_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_1_MASK) -/*! @} */ - -/*! @name AUX_BIAS_CURVE_TEMP_1 - */ -/*! @{ */ - -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_2_MASK (0xFFFFU) -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_2_SHIFT (0U) -/*! VREF1VCURVETRIM_2 - VREF1VCURVETRIM_2 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_2_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_2_MASK) - -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_3_MASK (0xFFFF0000U) -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_3_SHIFT (16U) -/*! VREF1VCURVETRIM_3 - VREF1VCURVETRIM_3 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_3_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_3_MASK) -/*! @} */ - -/*! @name AUX_BIAS_CURVE_TEMP_2 - */ -/*! @{ */ - -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_4_MASK (0xFFFFU) -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_4_SHIFT (0U) -/*! VREF1VCURVETRIM_4 - VREF1VCURVETRIM_4 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_4(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_4_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_4_MASK) - -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_5_MASK (0xFFFF0000U) -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_5_SHIFT (16U) -/*! VREF1VCURVETRIM_5 - VREF1VCURVETRIM_5 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_5(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_5_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_5_MASK) -/*! @} */ - -/*! @name AUX_BIAS_CURVE_TEMP_3 - */ -/*! @{ */ - -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_6_MASK (0xFFFFU) -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_6_SHIFT (0U) -/*! VREF1VCURVETRIM_6 - VREF1VCURVETRIM_6 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_6(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_6_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_6_MASK) - -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_7_MASK (0xFFFF0000U) -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_7_SHIFT (16U) -/*! VREF1VCURVETRIM_7 - VREF1VCURVETRIM_7 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_7(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_7_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_7_MASK) -/*! @} */ - -/*! @name AUX_BIAS_CURVE_TEMP_ARRAY - Aux Bias Curve TEMP (105degC) */ -/*! @{ */ - -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_AUX_BIAS_CURVE_TEMP_ARRAY */ -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_ARRAY_COUNT (4U) - -/*! @name TEMP_SENS_VBE1VBE8_REF_1 - */ -/*! @{ */ - -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE1_MASK (0xFFFFU) -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE1_SHIFT (0U) -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE1_SHIFT)) & FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE1_MASK) - -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE8_MASK (0xFFFF0000U) -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE8_SHIFT (16U) -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE8(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE8_SHIFT)) & FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE8_MASK) -/*! @} */ - -/*! @name TEMP_SENS_VBE1VBE8_REF_2 - */ -/*! @{ */ - -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE1_MASK (0xFFFFU) -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE1_SHIFT (0U) -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE1_SHIFT)) & FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE1_MASK) - -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE8_MASK (0xFFFF0000U) -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE8_SHIFT (16U) -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE8(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE8_SHIFT)) & FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE8_MASK) -/*! @} */ - -/*! @name TEMP_SENS_SLOPE - */ -/*! @{ */ - -#define FLASH_NMPA_TEMP_SENS_SLOPE_VALID_MASK (0x1U) -#define FLASH_NMPA_TEMP_SENS_SLOPE_VALID_SHIFT (0U) -#define FLASH_NMPA_TEMP_SENS_SLOPE_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_SLOPE_VALID_SHIFT)) & FLASH_NMPA_TEMP_SENS_SLOPE_VALID_MASK) - -#define FLASH_NMPA_TEMP_SENS_SLOPE_SLOPE_x1024_MASK (0xFFFFFFFEU) -#define FLASH_NMPA_TEMP_SENS_SLOPE_SLOPE_x1024_SHIFT (1U) -/*! SLOPE_x1024 - SLOPE_x1024[30:0] - */ -#define FLASH_NMPA_TEMP_SENS_SLOPE_SLOPE_x1024(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_SLOPE_SLOPE_x1024_SHIFT)) & FLASH_NMPA_TEMP_SENS_SLOPE_SLOPE_x1024_MASK) -/*! @} */ - -/*! @name TEMP_SENS_OFFSET - */ -/*! @{ */ - -#define FLASH_NMPA_TEMP_SENS_OFFSET_VALID_MASK (0x1U) -#define FLASH_NMPA_TEMP_SENS_OFFSET_VALID_SHIFT (0U) -#define FLASH_NMPA_TEMP_SENS_OFFSET_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_OFFSET_VALID_SHIFT)) & FLASH_NMPA_TEMP_SENS_OFFSET_VALID_MASK) - -#define FLASH_NMPA_TEMP_SENS_OFFSET_OFFSET_x1024_MASK (0xFFFFFFFEU) -#define FLASH_NMPA_TEMP_SENS_OFFSET_OFFSET_x1024_SHIFT (1U) -/*! OFFSET_x1024 - OFFSET_x1024[30:0] - */ -#define FLASH_NMPA_TEMP_SENS_OFFSET_OFFSET_x1024(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_OFFSET_OFFSET_x1024_SHIFT)) & FLASH_NMPA_TEMP_SENS_OFFSET_OFFSET_x1024_MASK) -/*! @} */ - -/*! @name PVT_MONITOR_0_RINGO - */ -/*! @{ */ - -#define FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_VALID_MASK (0x1U) -#define FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_VALID_SHIFT (0U) -#define FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_VALID_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_VALID_MASK) - -#define FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_FREQ_HZ_MASK (0xFFFFFFFEU) -#define FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_FREQ_HZ_SHIFT (1U) -#define FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_FREQ_HZ(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_FREQ_HZ_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_FREQ_HZ_MASK) -/*! @} */ - -/*! @name PVT_MONITOR_0_DELAYS_LSB - */ -/*! @{ */ - -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_VALID_MASK (0x1U) -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_VALID_SHIFT (0U) -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_VALID_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_VALID_MASK) - -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_0_MASK (0x7FEU) -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_0_SHIFT (1U) -/*! DELAY_0 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_0_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_0_MASK) - -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_1_MASK (0x1FF800U) -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_1_SHIFT (11U) -/*! DELAY_1 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_1_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_1_MASK) - -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_2_MASK (0x7FE00000U) -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_2_SHIFT (21U) -/*! DELAY_2 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_2_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_2_MASK) -/*! @} */ - -/*! @name PVT_MONITOR_0_DELAYS_MSB - */ -/*! @{ */ - -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_3_MASK (0x3FFU) -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_3_SHIFT (0U) -/*! DELAY_3 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_3_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_3_MASK) - -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_4_MASK (0xFFC00U) -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_4_SHIFT (10U) -/*! DELAY_4 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_4(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_4_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_4_MASK) - -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_5_MASK (0x3FF00000U) -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_5_SHIFT (20U) -/*! DELAY_5 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_5(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_5_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_5_MASK) -/*! @} */ - -/*! @name PVT_MONITOR_0_ARRAY - */ -/*! @{ */ - -#define FLASH_NMPA_PVT_MONITOR_0_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_PVT_MONITOR_0_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_PVT_MONITOR_0_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_PVT_MONITOR_0_ARRAY */ -#define FLASH_NMPA_PVT_MONITOR_0_ARRAY_COUNT (3U) - -/*! @name PVT_MONITOR_1_RINGO - */ -/*! @{ */ - -#define FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_VALID_MASK (0x1U) -#define FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_VALID_SHIFT (0U) -#define FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_VALID_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_VALID_MASK) - -#define FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_FREQ_HZ_MASK (0xFFFFFFFEU) -#define FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_FREQ_HZ_SHIFT (1U) -#define FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_FREQ_HZ(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_FREQ_HZ_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_FREQ_HZ_MASK) -/*! @} */ - -/*! @name PVT_MONITOR_1_DELAYS_LSB - */ -/*! @{ */ - -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_VALID_MASK (0x1U) -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_VALID_SHIFT (0U) -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_VALID_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_VALID_MASK) - -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_0_MASK (0x7FEU) -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_0_SHIFT (1U) -/*! DELAY_0 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_0_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_0_MASK) - -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_1_MASK (0x1FF800U) -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_1_SHIFT (11U) -/*! DELAY_1 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_1_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_1_MASK) - -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_2_MASK (0x7FE00000U) -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_2_SHIFT (21U) -/*! DELAY_2 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_2_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_2_MASK) -/*! @} */ - -/*! @name PVT_MONITOR_1_DELAYS_MSB - */ -/*! @{ */ - -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_3_MASK (0x3FFU) -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_3_SHIFT (0U) -/*! DELAY_3 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_3_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_3_MASK) - -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_4_MASK (0xFFC00U) -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_4_SHIFT (10U) -/*! DELAY_4 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_4(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_4_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_4_MASK) - -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_5_MASK (0x3FF00000U) -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_5_SHIFT (20U) -/*! DELAY_5 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_5(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_5_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_5_MASK) -/*! @} */ - -/*! @name PVT_MONITOR_1_ARRAY - */ -/*! @{ */ - -#define FLASH_NMPA_PVT_MONITOR_1_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_PVT_MONITOR_1_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_PVT_MONITOR_1_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_PVT_MONITOR_1_ARRAY */ -#define FLASH_NMPA_PVT_MONITOR_1_ARRAY_COUNT (3U) - -/*! @name NXP_DEVICE_PRIVATE_KEY - */ -/*! @{ */ - -#define FLASH_NMPA_NXP_DEVICE_PRIVATE_KEY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_NXP_DEVICE_PRIVATE_KEY_FIELD_SHIFT (0U) -#define FLASH_NMPA_NXP_DEVICE_PRIVATE_KEY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_NXP_DEVICE_PRIVATE_KEY_FIELD_SHIFT)) & FLASH_NMPA_NXP_DEVICE_PRIVATE_KEY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_NXP_DEVICE_PRIVATE_KEY */ -#define FLASH_NMPA_NXP_DEVICE_PRIVATE_KEY_COUNT (13U) - -/*! @name NXP_DEVICE_CERTIFICATE_0 - NXP Device Certificate (ECDSA_sign - r[255:128]) */ -/*! @{ */ - -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_0_FIELD_SHIFT (0U) -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_NXP_DEVICE_CERTIFICATE_0_FIELD_SHIFT)) & FLASH_NMPA_NXP_DEVICE_CERTIFICATE_0_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_NXP_DEVICE_CERTIFICATE_0 */ -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_0_COUNT (4U) - -/*! @name NXP_DEVICE_CERTIFICATE_1 - NXP Device Certificate (ECDSA_sign - r[127:0]) */ -/*! @{ */ - -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_1_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_1_FIELD_SHIFT (0U) -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_NXP_DEVICE_CERTIFICATE_1_FIELD_SHIFT)) & FLASH_NMPA_NXP_DEVICE_CERTIFICATE_1_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_NXP_DEVICE_CERTIFICATE_1 */ -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_1_COUNT (4U) - -/*! @name NXP_DEVICE_CERTIFICATE_2 - NXP Device Certificate (ECDSA_sign - s[255:128]) */ -/*! @{ */ - -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_2_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_2_FIELD_SHIFT (0U) -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_NXP_DEVICE_CERTIFICATE_2_FIELD_SHIFT)) & FLASH_NMPA_NXP_DEVICE_CERTIFICATE_2_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_NXP_DEVICE_CERTIFICATE_2 */ -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_2_COUNT (4U) - -/*! @name NXP_DEVICE_CERTIFICATE_3 - NXP Device Certificate (ECDSA_sign - s[127:0]) */ -/*! @{ */ - -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_3_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_3_FIELD_SHIFT (0U) -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_NXP_DEVICE_CERTIFICATE_3_FIELD_SHIFT)) & FLASH_NMPA_NXP_DEVICE_CERTIFICATE_3_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_NXP_DEVICE_CERTIFICATE_3 */ -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_3_COUNT (4U) - -/*! @name SHA256_DIGEST - SHA-256 DIGEST (9EC00 - 9FDBC) ROM Patch Area + NXP Area (IMPORTANT NOTE: Pages used for Repair (N-8 to N-3) are excluded from the computation) SHA256_DIGEST0 for DIGEST[31:0]..SHA-256 DIGEST (9EC00 - 9FDBC) ROM Patch Area + NXP Area (IMPORTANT NOTE: Pages used for Repair (N-8 to N-3) are excluded from the computation) SHA256_DIGEST7 for DIGEST[255:224] */ -/*! @{ */ - -#define FLASH_NMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_SHA256_DIGEST_FIELD_SHIFT (0U) -#define FLASH_NMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_NMPA_SHA256_DIGEST_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_SHA256_DIGEST */ -#define FLASH_NMPA_SHA256_DIGEST_COUNT (8U) - -/*! @name ECID_BACKUP_0 - */ -/*! @{ */ - -#define FLASH_NMPA_ECID_BACKUP_0_COORD_Y_MASK (0xFFFFU) -#define FLASH_NMPA_ECID_BACKUP_0_COORD_Y_SHIFT (0U) -#define FLASH_NMPA_ECID_BACKUP_0_COORD_Y(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_ECID_BACKUP_0_COORD_Y_SHIFT)) & FLASH_NMPA_ECID_BACKUP_0_COORD_Y_MASK) - -#define FLASH_NMPA_ECID_BACKUP_0_COORD_X_MASK (0xFFFF0000U) -#define FLASH_NMPA_ECID_BACKUP_0_COORD_X_SHIFT (16U) -#define FLASH_NMPA_ECID_BACKUP_0_COORD_X(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_ECID_BACKUP_0_COORD_X_SHIFT)) & FLASH_NMPA_ECID_BACKUP_0_COORD_X_MASK) -/*! @} */ - -/*! @name ECID_BACKUP_1 - */ -/*! @{ */ - -#define FLASH_NMPA_ECID_BACKUP_1_WAFER_MASK (0xFFU) -#define FLASH_NMPA_ECID_BACKUP_1_WAFER_SHIFT (0U) -#define FLASH_NMPA_ECID_BACKUP_1_WAFER(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_ECID_BACKUP_1_WAFER_SHIFT)) & FLASH_NMPA_ECID_BACKUP_1_WAFER_MASK) -/*! @} */ - -/*! @name ECID_BACKUP_2 - */ -/*! @{ */ - -#define FLASH_NMPA_ECID_BACKUP_2_LOTID_LSB_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_ECID_BACKUP_2_LOTID_LSB_SHIFT (0U) -#define FLASH_NMPA_ECID_BACKUP_2_LOTID_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_ECID_BACKUP_2_LOTID_LSB_SHIFT)) & FLASH_NMPA_ECID_BACKUP_2_LOTID_LSB_MASK) -/*! @} */ - -/*! @name ECID_BACKUP_3 - */ -/*! @{ */ - -#define FLASH_NMPA_ECID_BACKUP_3_LOTID_MSB_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_ECID_BACKUP_3_LOTID_MSB_SHIFT (0U) -#define FLASH_NMPA_ECID_BACKUP_3_LOTID_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_ECID_BACKUP_3_LOTID_MSB_SHIFT)) & FLASH_NMPA_ECID_BACKUP_3_LOTID_MSB_MASK) -/*! @} */ - -/*! @name ECID_BACKUP_ARRAY - ECID backup (the original is in page n-1) */ -/*! @{ */ - -#define FLASH_NMPA_ECID_BACKUP_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_ECID_BACKUP_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_ECID_BACKUP_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_ECID_BACKUP_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_ECID_BACKUP_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_ECID_BACKUP_ARRAY */ -#define FLASH_NMPA_ECID_BACKUP_ARRAY_COUNT (4U) - -/* The count of FLASH_NMPA_CHECKSUM */ -#define FLASH_NMPA_CHECKSUM_COUNT (4U) - -/*! @name DIS_ROM_HIDING - */ -/*! @{ */ - -#define FLASH_NMPA_DIS_ROM_HIDING_DIS_ROM_HIDING_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_DIS_ROM_HIDING_DIS_ROM_HIDING_SHIFT (0U) -/*! DIS_ROM_HIDING - When 0x3CC35AA5 ROM hiding feture is disabled. All other values critical ROM is hidden. - */ -#define FLASH_NMPA_DIS_ROM_HIDING_DIS_ROM_HIDING(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DIS_ROM_HIDING_DIS_ROM_HIDING_SHIFT)) & FLASH_NMPA_DIS_ROM_HIDING_DIS_ROM_HIDING_MASK) -/*! @} */ - -/*! @name PUF_SRAM - */ -/*! @{ */ - -#define FLASH_NMPA_PUF_SRAM_PUF_SRAM_VALID_MASK (0x1U) -#define FLASH_NMPA_PUF_SRAM_PUF_SRAM_VALID_SHIFT (0U) -/*! PUF_SRAM_VALID - 1: PUF_SRAM is valid. - */ -#define FLASH_NMPA_PUF_SRAM_PUF_SRAM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_PUF_SRAM_VALID_SHIFT)) & FLASH_NMPA_PUF_SRAM_PUF_SRAM_VALID_MASK) - -#define FLASH_NMPA_PUF_SRAM_mode_MASK (0x2U) -#define FLASH_NMPA_PUF_SRAM_mode_SHIFT (1U) -/*! mode - PUF SRAM Controller operating mode - */ -#define FLASH_NMPA_PUF_SRAM_mode(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_mode_SHIFT)) & FLASH_NMPA_PUF_SRAM_mode_MASK) - -#define FLASH_NMPA_PUF_SRAM_ckgating_MASK (0x4U) -#define FLASH_NMPA_PUF_SRAM_ckgating_SHIFT (2U) -/*! ckgating - PUF SRAM Clock Gating control - */ -#define FLASH_NMPA_PUF_SRAM_ckgating(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_ckgating_SHIFT)) & FLASH_NMPA_PUF_SRAM_ckgating_MASK) - -#define FLASH_NMPA_PUF_SRAM_SMB_MASK (0x300U) -#define FLASH_NMPA_PUF_SRAM_SMB_SHIFT (8U) -/*! SMB - Source Biasing voltage. - * 0b00..Low leakage. - * 0b01..Medium leakage. - * 0b10..Highest leakage. - * 0b11..Disable. - */ -#define FLASH_NMPA_PUF_SRAM_SMB(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_SMB_SHIFT)) & FLASH_NMPA_PUF_SRAM_SMB_MASK) - -#define FLASH_NMPA_PUF_SRAM_RM_MASK (0x1C00U) -#define FLASH_NMPA_PUF_SRAM_RM_SHIFT (10U) -/*! RM - Read Margin control settings. - */ -#define FLASH_NMPA_PUF_SRAM_RM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_RM_SHIFT)) & FLASH_NMPA_PUF_SRAM_RM_MASK) - -#define FLASH_NMPA_PUF_SRAM_WM_MASK (0xE000U) -#define FLASH_NMPA_PUF_SRAM_WM_SHIFT (13U) -/*! WM - Write Margin control settings. - */ -#define FLASH_NMPA_PUF_SRAM_WM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_WM_SHIFT)) & FLASH_NMPA_PUF_SRAM_WM_MASK) - -#define FLASH_NMPA_PUF_SRAM_WRME_MASK (0x10000U) -#define FLASH_NMPA_PUF_SRAM_WRME_SHIFT (16U) -/*! WRME - Write read margin enable. - */ -#define FLASH_NMPA_PUF_SRAM_WRME(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_WRME_SHIFT)) & FLASH_NMPA_PUF_SRAM_WRME_MASK) - -#define FLASH_NMPA_PUF_SRAM_RAEN_MASK (0x20000U) -#define FLASH_NMPA_PUF_SRAM_RAEN_SHIFT (17U) -/*! RAEN - SRAM Read Assist Enable - */ -#define FLASH_NMPA_PUF_SRAM_RAEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_RAEN_SHIFT)) & FLASH_NMPA_PUF_SRAM_RAEN_MASK) - -#define FLASH_NMPA_PUF_SRAM_RAM_MASK (0x3C0000U) -#define FLASH_NMPA_PUF_SRAM_RAM_SHIFT (18U) -/*! RAM - SRAM Read Assist settings - */ -#define FLASH_NMPA_PUF_SRAM_RAM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_RAM_SHIFT)) & FLASH_NMPA_PUF_SRAM_RAM_MASK) - -#define FLASH_NMPA_PUF_SRAM_WAEN_MASK (0x400000U) -#define FLASH_NMPA_PUF_SRAM_WAEN_SHIFT (22U) -/*! WAEN - SRAM Write Assist Enable - */ -#define FLASH_NMPA_PUF_SRAM_WAEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_WAEN_SHIFT)) & FLASH_NMPA_PUF_SRAM_WAEN_MASK) - -#define FLASH_NMPA_PUF_SRAM_WAM_MASK (0x1800000U) -#define FLASH_NMPA_PUF_SRAM_WAM_SHIFT (23U) -/*! WAM - SRAM Write Assist settings - */ -#define FLASH_NMPA_PUF_SRAM_WAM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_WAM_SHIFT)) & FLASH_NMPA_PUF_SRAM_WAM_MASK) - -#define FLASH_NMPA_PUF_SRAM_STBP_MASK (0x2000000U) -#define FLASH_NMPA_PUF_SRAM_STBP_SHIFT (25U) -/*! STBP - STBP - */ -#define FLASH_NMPA_PUF_SRAM_STBP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_STBP_SHIFT)) & FLASH_NMPA_PUF_SRAM_STBP_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLASH_NMPA_Register_Masks */ - - -/* FLASH_NMPA - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH_NMPA base address */ - #define FLASH_NMPA_BASE (0x1003FC00u) - /** Peripheral FLASH_NMPA base address */ - #define FLASH_NMPA_BASE_NS (0x3FC00u) - /** Peripheral FLASH_NMPA base pointer */ - #define FLASH_NMPA ((FLASH_NMPA_Type *)FLASH_NMPA_BASE) - /** Peripheral FLASH_NMPA base pointer */ - #define FLASH_NMPA_NS ((FLASH_NMPA_Type *)FLASH_NMPA_BASE_NS) - /** Array initializer of FLASH_NMPA peripheral base addresses */ - #define FLASH_NMPA_BASE_ADDRS { FLASH_NMPA_BASE } - /** Array initializer of FLASH_NMPA peripheral base pointers */ - #define FLASH_NMPA_BASE_PTRS { FLASH_NMPA } - /** Array initializer of FLASH_NMPA peripheral base addresses */ - #define FLASH_NMPA_BASE_ADDRS_NS { FLASH_NMPA_BASE_NS } - /** Array initializer of FLASH_NMPA peripheral base pointers */ - #define FLASH_NMPA_BASE_PTRS_NS { FLASH_NMPA_NS } -#else - /** Peripheral FLASH_NMPA base address */ - #define FLASH_NMPA_BASE (0x3FC00u) - /** Peripheral FLASH_NMPA base pointer */ - #define FLASH_NMPA ((FLASH_NMPA_Type *)FLASH_NMPA_BASE) - /** Array initializer of FLASH_NMPA peripheral base addresses */ - #define FLASH_NMPA_BASE_ADDRS { FLASH_NMPA_BASE } - /** Array initializer of FLASH_NMPA peripheral base pointers */ - #define FLASH_NMPA_BASE_PTRS { FLASH_NMPA } -#endif - -/*! - * @} - */ /* end of group FLASH_NMPA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_ROMPATCH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_ROMPATCH_Peripheral_Access_Layer FLASH_ROMPATCH Peripheral Access Layer - * @{ - */ - -/** FLASH_ROMPATCH - Register Layout Typedef */ -typedef struct { - __IO uint32_t HEADER; /**< ., offset: 0x0 */ - __IO uint32_t PATCH[255]; /**< ., array offset: 0x4, array step: 0x4 */ -} FLASH_ROMPATCH_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_ROMPATCH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_ROMPATCH_Register_Masks FLASH_ROMPATCH Register Masks - * @{ - */ - -/*! @name HEADER - . */ -/*! @{ */ - -#define FLASH_ROMPATCH_HEADER_ENTRIES_MASK (0xFFU) -#define FLASH_ROMPATCH_HEADER_ENTRIES_SHIFT (0U) -/*! ENTRIES - . - */ -#define FLASH_ROMPATCH_HEADER_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ROMPATCH_HEADER_ENTRIES_SHIFT)) & FLASH_ROMPATCH_HEADER_ENTRIES_MASK) - -#define FLASH_ROMPATCH_HEADER_SUB_TYPE_MASK (0xFF00U) -#define FLASH_ROMPATCH_HEADER_SUB_TYPE_SHIFT (8U) -/*! SUB_TYPE - . - */ -#define FLASH_ROMPATCH_HEADER_SUB_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ROMPATCH_HEADER_SUB_TYPE_SHIFT)) & FLASH_ROMPATCH_HEADER_SUB_TYPE_MASK) - -#define FLASH_ROMPATCH_HEADER_TYPE_MASK (0xFF0000U) -#define FLASH_ROMPATCH_HEADER_TYPE_SHIFT (16U) -/*! TYPE - . - */ -#define FLASH_ROMPATCH_HEADER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ROMPATCH_HEADER_TYPE_SHIFT)) & FLASH_ROMPATCH_HEADER_TYPE_MASK) - -#define FLASH_ROMPATCH_HEADER_IDENTIFIER_MASK (0xFF000000U) -#define FLASH_ROMPATCH_HEADER_IDENTIFIER_SHIFT (24U) -/*! IDENTIFIER - . - */ -#define FLASH_ROMPATCH_HEADER_IDENTIFIER(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ROMPATCH_HEADER_IDENTIFIER_SHIFT)) & FLASH_ROMPATCH_HEADER_IDENTIFIER_MASK) -/*! @} */ - -/*! @name PATCH - . */ -/*! @{ */ - -#define FLASH_ROMPATCH_PATCH_PATCH_MASK (0xFFFFFFFFU) -#define FLASH_ROMPATCH_PATCH_PATCH_SHIFT (0U) -/*! PATCH - . - */ -#define FLASH_ROMPATCH_PATCH_PATCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ROMPATCH_PATCH_PATCH_SHIFT)) & FLASH_ROMPATCH_PATCH_PATCH_MASK) -/*! @} */ - -/* The count of FLASH_ROMPATCH_PATCH */ -#define FLASH_ROMPATCH_PATCH_COUNT (255U) - - -/*! - * @} - */ /* end of group FLASH_ROMPATCH_Register_Masks */ - - -/* FLASH_ROMPATCH - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH_ROMPATCH base address */ - #define FLASH_ROMPATCH_BASE (0x1003EC00u) - /** Peripheral FLASH_ROMPATCH base address */ - #define FLASH_ROMPATCH_BASE_NS (0x3EC00u) - /** Peripheral FLASH_ROMPATCH base pointer */ - #define FLASH_ROMPATCH ((FLASH_ROMPATCH_Type *)FLASH_ROMPATCH_BASE) - /** Peripheral FLASH_ROMPATCH base pointer */ - #define FLASH_ROMPATCH_NS ((FLASH_ROMPATCH_Type *)FLASH_ROMPATCH_BASE_NS) - /** Array initializer of FLASH_ROMPATCH peripheral base addresses */ - #define FLASH_ROMPATCH_BASE_ADDRS { FLASH_ROMPATCH_BASE } - /** Array initializer of FLASH_ROMPATCH peripheral base pointers */ - #define FLASH_ROMPATCH_BASE_PTRS { FLASH_ROMPATCH } - /** Array initializer of FLASH_ROMPATCH peripheral base addresses */ - #define FLASH_ROMPATCH_BASE_ADDRS_NS { FLASH_ROMPATCH_BASE_NS } - /** Array initializer of FLASH_ROMPATCH peripheral base pointers */ - #define FLASH_ROMPATCH_BASE_PTRS_NS { FLASH_ROMPATCH_NS } -#else - /** Peripheral FLASH_ROMPATCH base address */ - #define FLASH_ROMPATCH_BASE (0x3EC00u) - /** Peripheral FLASH_ROMPATCH base pointer */ - #define FLASH_ROMPATCH ((FLASH_ROMPATCH_Type *)FLASH_ROMPATCH_BASE) - /** Array initializer of FLASH_ROMPATCH peripheral base addresses */ - #define FLASH_ROMPATCH_BASE_ADDRS { FLASH_ROMPATCH_BASE } - /** Array initializer of FLASH_ROMPATCH peripheral base pointers */ - #define FLASH_ROMPATCH_BASE_PTRS { FLASH_ROMPATCH } -#endif - -/*! - * @} - */ /* end of group FLASH_ROMPATCH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer - * @{ - */ - -/** FLEXCOMM - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4088]; - __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ - __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ -} FLEXCOMM_Type; - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks - * @{ - */ - -/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ -/*! @{ */ - -#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) -#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) -/*! PERSEL - Peripheral Select. This field is writable by software. - * 0b000..No peripheral selected. - * 0b001..USART function selected. - * 0b010..SPI function selected. - * 0b011..I2C function selected. - * 0b100..I2S transmit function selected. - * 0b101..I2S receive function selected. - * 0b110..Reserved - * 0b111..Reserved - */ -#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) - -#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) -#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) -/*! LOCK - Lock the peripheral select. This field is writable by software. - * 0b0..Peripheral select can be changed by software. - * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. - */ -#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) - -#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) -#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) -/*! USARTPRESENT - USART present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the USART function. - * 0b1..This Flexcomm includes the USART function. - */ -#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) - -#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) -#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) -/*! SPIPRESENT - SPI present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the SPI function. - * 0b1..This Flexcomm includes the SPI function. - */ -#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) - -#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) -#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) -/*! I2CPRESENT - I2C present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the I2C function. - * 0b1..This Flexcomm includes the I2C function. - */ -#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) - -#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) -#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) -/*! I2SPRESENT - I 2S present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the I2S function. - * 0b1..This Flexcomm includes the I2S function. - */ -#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) - -#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) -#define FLEXCOMM_PSELID_ID_SHIFT (12U) -/*! ID - Flexcomm ID. - */ -#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) -/*! @} */ - -/*! @name PID - Peripheral identification register. */ -/*! @{ */ - -#define FLEXCOMM_PID_MINOR_REV_MASK (0xF00U) -#define FLEXCOMM_PID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation. - */ -#define FLEXCOMM_PID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MINOR_REV_SHIFT)) & FLEXCOMM_PID_MINOR_REV_MASK) - -#define FLEXCOMM_PID_MAJOR_REV_MASK (0xF000U) -#define FLEXCOMM_PID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation. - */ -#define FLEXCOMM_PID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MAJOR_REV_SHIFT)) & FLEXCOMM_PID_MAJOR_REV_MASK) - -#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) -#define FLEXCOMM_PID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function. - */ -#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLEXCOMM_Register_Masks */ - - -/* FLEXCOMM - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE (0x50086000u) - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE_NS (0x40086000u) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE (0x50087000u) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE_NS (0x40087000u) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE (0x50088000u) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE_NS (0x40088000u) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE (0x50089000u) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE_NS (0x40089000u) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE (0x5008A000u) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE_NS (0x4008A000u) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE (0x50096000u) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE_NS (0x40096000u) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE (0x50097000u) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE_NS (0x40097000u) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE (0x50098000u) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE_NS (0x40098000u) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE (0x5009F000u) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE_NS (0x4009F000u) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS) - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS_NS { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS_NS { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS } -#else - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE (0x40086000u) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE (0x40087000u) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE (0x40088000u) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE (0x40089000u) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE (0x4008A000u) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE (0x40096000u) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE (0x40097000u) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE (0x40098000u) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE (0x4009F000u) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } -#endif -/** Interrupt vectors for the FLEXCOMM peripheral type */ -#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } - -/*! - * @} - */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer - * @{ - */ - -/** GINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ - uint8_t RESERVED_0[28]; - __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[24]; - __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ -} GINT_Type; - -/* ---------------------------------------------------------------------------- - -- GINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Register_Masks GINT Register Masks - * @{ - */ - -/*! @name CTRL - GPIO grouped interrupt control register */ -/*! @{ */ - -#define GINT_CTRL_INT_MASK (0x1U) -#define GINT_CTRL_INT_SHIFT (0U) -/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. - * 0b0..No request. No interrupt request is pending. - * 0b1..Request active. Interrupt request is active. - */ -#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) - -#define GINT_CTRL_COMB_MASK (0x2U) -#define GINT_CTRL_COMB_SHIFT (1U) -/*! COMB - Combine enabled inputs for group interrupt - * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). - * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). - */ -#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) - -#define GINT_CTRL_TRIG_MASK (0x4U) -#define GINT_CTRL_TRIG_SHIFT (2U) -/*! TRIG - Group interrupt trigger - * 0b0..Edge-triggered. - * 0b1..Level-triggered. - */ -#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) -/*! @} */ - -/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ -/*! @{ */ - -#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) -#define GINT_PORT_POL_POL_SHIFT (0U) -/*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n - * of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to - * the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin - * contributes to the group interrupt. - */ -#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) -/*! @} */ - -/* The count of GINT_PORT_POL */ -#define GINT_PORT_POL_COUNT (2U) - -/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ -/*! @{ */ - -#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) -#define GINT_PORT_ENA_ENA_SHIFT (0U) -/*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the - * port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is - * enabled and contributes to the grouped interrupt. - */ -#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) -/*! @} */ - -/* The count of GINT_PORT_ENA */ -#define GINT_PORT_ENA_COUNT (2U) - - -/*! - * @} - */ /* end of group GINT_Register_Masks */ - - -/* GINT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral GINT0 base address */ - #define GINT0_BASE (0x50002000u) - /** Peripheral GINT0 base address */ - #define GINT0_BASE_NS (0x40002000u) - /** Peripheral GINT0 base pointer */ - #define GINT0 ((GINT_Type *)GINT0_BASE) - /** Peripheral GINT0 base pointer */ - #define GINT0_NS ((GINT_Type *)GINT0_BASE_NS) - /** Peripheral GINT1 base address */ - #define GINT1_BASE (0x50003000u) - /** Peripheral GINT1 base address */ - #define GINT1_BASE_NS (0x40003000u) - /** Peripheral GINT1 base pointer */ - #define GINT1 ((GINT_Type *)GINT1_BASE) - /** Peripheral GINT1 base pointer */ - #define GINT1_NS ((GINT_Type *)GINT1_BASE_NS) - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS { GINT0, GINT1 } - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS_NS { GINT0_BASE_NS, GINT1_BASE_NS } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS_NS { GINT0_NS, GINT1_NS } -#else - /** Peripheral GINT0 base address */ - #define GINT0_BASE (0x40002000u) - /** Peripheral GINT0 base pointer */ - #define GINT0 ((GINT_Type *)GINT0_BASE) - /** Peripheral GINT1 base address */ - #define GINT1_BASE (0x40003000u) - /** Peripheral GINT1 base pointer */ - #define GINT1 ((GINT_Type *)GINT1_BASE) - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS { GINT0, GINT1 } -#endif -/** Interrupt vectors for the GINT peripheral type */ -#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } - -/*! - * @} - */ /* end of group GINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer - * @{ - */ - -/** GPIO - Register Layout Typedef */ -typedef struct { - __IO uint8_t B[2][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ - uint8_t RESERVED_0[4032]; - __IO uint32_t W[2][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ - uint8_t RESERVED_1[3840]; - __IO uint32_t DIR[2]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */ - uint8_t RESERVED_2[120]; - __IO uint32_t MASK[2]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */ - uint8_t RESERVED_3[120]; - __IO uint32_t PIN[2]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */ - uint8_t RESERVED_4[120]; - __IO uint32_t MPIN[2]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */ - uint8_t RESERVED_5[120]; - __IO uint32_t SET[2]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */ - uint8_t RESERVED_6[120]; - __O uint32_t CLR[2]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */ - uint8_t RESERVED_7[120]; - __O uint32_t NOT[2]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */ - uint8_t RESERVED_8[120]; - __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ - uint8_t RESERVED_9[120]; - __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ - uint8_t RESERVED_10[120]; - __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ -} GPIO_Type; - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/*! @name B - Byte pin registers for all port GPIO pins */ -/*! @{ */ - -#define GPIO_B_PBYTE_MASK (0x1U) -#define GPIO_B_PBYTE_SHIFT (0U) -/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, - * except that pins configured as analog I/O always read as 0. One register for each port pin. - * Supported pins depends on the specific device and package. Write: loads the pin's output bit. - * One register for each port pin. Supported pins depends on the specific device and package. - */ -#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) -/*! @} */ - -/* The count of GPIO_B */ -#define GPIO_B_COUNT (2U) - -/* The count of GPIO_B */ -#define GPIO_B_COUNT2 (32U) - -/*! @name W - Word pin registers for all port GPIO pins */ -/*! @{ */ - -#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) -#define GPIO_W_PWORD_SHIFT (0U) -/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is - * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be - * read. Writing any value other than 0 will set the output bit. One register for each port pin. - * Supported pins depends on the specific device and package. - */ -#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) -/*! @} */ - -/* The count of GPIO_W */ -#define GPIO_W_COUNT (2U) - -/* The count of GPIO_W */ -#define GPIO_W_COUNT2 (32U) - -/*! @name DIR - Direction registers for all port GPIO pins */ -/*! @{ */ - -#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) -#define GPIO_DIR_DIRP_SHIFT (0U) -/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported - * pins depends on the specific device and package. 0 = input. 1 = output. - */ -#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) -/*! @} */ - -/* The count of GPIO_DIR */ -#define GPIO_DIR_COUNT (2U) - -/*! @name MASK - Mask register for all port GPIO pins */ -/*! @{ */ - -#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) -#define GPIO_MASK_MASKP_SHIFT (0U) -/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = - * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = - * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit - * not affected. - */ -#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) -/*! @} */ - -/* The count of GPIO_MASK */ -#define GPIO_MASK_COUNT (2U) - -/*! @name PIN - Port pin register for all port GPIO pins */ -/*! @{ */ - -#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) -#define GPIO_PIN_PORT_SHIFT (0U) -/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported - * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. - * 1 = Read: pin is high; write: set output bit. - */ -#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) -/*! @} */ - -/* The count of GPIO_PIN */ -#define GPIO_PIN_COUNT (2U) - -/*! @name MPIN - Masked port register for all port GPIO pins */ -/*! @{ */ - -#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) -#define GPIO_MPIN_MPORTP_SHIFT (0U) -/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on - * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK - * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 - * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit - * if the corresponding bit in the MASK register is 0. - */ -#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) -/*! @} */ - -/* The count of GPIO_MPIN */ -#define GPIO_MPIN_COUNT (2U) - -/*! @name SET - Write: Set register for port. Read: output bits for port */ -/*! @{ */ - -#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) -#define GPIO_SET_SETP_SHIFT (0U) -/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on - * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output - * bit; write: set output bit. - */ -#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) -/*! @} */ - -/* The count of GPIO_SET */ -#define GPIO_SET_COUNT (2U) - -/*! @name CLR - Clear port for all port GPIO pins */ -/*! @{ */ - -#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) -#define GPIO_CLR_CLRP_SHIFT (0U) -/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the - * specific device and package. 0 = No operation. 1 = Clear output bit. - */ -#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) -/*! @} */ - -/* The count of GPIO_CLR */ -#define GPIO_CLR_COUNT (2U) - -/*! @name NOT - Toggle port for all port GPIO pins */ -/*! @{ */ - -#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) -#define GPIO_NOT_NOTP_SHIFT (0U) -/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the - * specific device and package. 0 = no operation. 1 = Toggle output bit. - */ -#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) -/*! @} */ - -/* The count of GPIO_NOT */ -#define GPIO_NOT_COUNT (2U) - -/*! @name DIRSET - Set pin direction bits for port */ -/*! @{ */ - -#define GPIO_DIRSET_DIRSETP_MASK (0xFFFFFFFFU) -#define GPIO_DIRSET_DIRSETP_SHIFT (0U) -/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on - * the specific device and package. 0 = No operation. 1 = Set direction bit. - */ -#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) -/*! @} */ - -/* The count of GPIO_DIRSET */ -#define GPIO_DIRSET_COUNT (2U) - -/*! @name DIRCLR - Clear pin direction bits for port */ -/*! @{ */ - -#define GPIO_DIRCLR_DIRCLRP_MASK (0xFFFFFFFFU) -#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) -/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on - * the specific device and package. 0 = No operation. 1 = Clear direction bit. - */ -#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) -/*! @} */ - -/* The count of GPIO_DIRCLR */ -#define GPIO_DIRCLR_COUNT (2U) - -/*! @name DIRNOT - Toggle pin direction bits for port */ -/*! @{ */ - -#define GPIO_DIRNOT_DIRNOTP_MASK (0xFFFFFFFFU) -#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) -/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends - * on the specific device and package. 0 = no operation. 1 = Toggle direction bit. - */ -#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) -/*! @} */ - -/* The count of GPIO_DIRNOT */ -#define GPIO_DIRNOT_COUNT (2U) - - -/*! - * @} - */ /* end of group GPIO_Register_Masks */ - - -/* GPIO - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral GPIO base address */ - #define GPIO_BASE (0x5008C000u) - /** Peripheral GPIO base address */ - #define GPIO_BASE_NS (0x4008C000u) - /** Peripheral GPIO base pointer */ - #define GPIO ((GPIO_Type *)GPIO_BASE) - /** Peripheral GPIO base pointer */ - #define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE (0x500A8000u) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE_NS (0x400A8000u) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS) - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO, SECGPIO } - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS_NS { GPIO_BASE_NS, SECGPIO_BASE_NS } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS_NS { GPIO_NS, SECGPIO_NS } -#else - /** Peripheral GPIO base address */ - #define GPIO_BASE (0x4008C000u) - /** Peripheral GPIO base pointer */ - #define GPIO ((GPIO_Type *)GPIO_BASE) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE (0x400A8000u) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO, SECGPIO } -#endif - -/*! - * @} - */ /* end of group GPIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- HASHCRYPT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup HASHCRYPT_Peripheral_Access_Layer HASHCRYPT Peripheral Access Layer - * @{ - */ - -/** HASHCRYPT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register to enable and operate Hash and Crypto, offset: 0x0 */ - __IO uint32_t STATUS; /**< Indicates status of Hash peripheral., offset: 0x4 */ - __IO uint32_t INTENSET; /**< Write 1 to enable interrupts; reads back with which are set., offset: 0x8 */ - __IO uint32_t INTENCLR; /**< Write 1 to clear interrupts., offset: 0xC */ - __IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available), offset: 0x10 */ - __IO uint32_t MEMADDR; /**< Address to start memory access from (if available)., offset: 0x14 */ - uint8_t RESERVED_0[8]; - __O uint32_t INDATA; /**< Input of 16 words at a time to load up buffer., offset: 0x20 */ - __O uint32_t ALIAS[7]; /**< Aliases to allow writing words in a burst., array offset: 0x24, array step: 0x4 */ - __I uint32_t DIGEST0[8]; /**< Result digest (when status says so): • Is 1st 5 words if SHA1 used • Is all 8 words if SHA2 used • Is all 8 words if crypto or SHA512, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_1[32]; - __IO uint32_t CRYPTCFG; /**< Crypto settings for AES and Salsa and ChaCha, offset: 0x80 */ - __I uint32_t CONFIG; /**< Returns the configuration of this block in this chip - indicates what services are available., offset: 0x84 */ - uint8_t RESERVED_2[4]; - __IO uint32_t LOCK; /**< Lock register allows locking to the current security level or unlocking by the lock holding level., offset: 0x8C */ - __O uint32_t MASK[4]; /**< Allows Application to write a random mask for ICB use. Normally only a new one on each system reset (including power up)., array offset: 0x90, array step: 0x4 */ - __O uint32_t RELOAD[8]; /**< The WO digest-reload registers may be written with a saved Hash digest, to allow continuation from where left off. These registers may only be written if the Reload field in CTRL is 1. If SHA1, only the 1st 5 are used., array offset: 0xA0, array step: 0x4 */ - uint8_t RESERVED_3[16]; - __O uint32_t PRNG_SEED; /**< PRNG random input value used as an entropy source, offset: 0xD0 */ - uint8_t RESERVED_4[4]; - __I uint32_t PRNG_OUT; /**< Provide random number., offset: 0xD8 */ -} HASHCRYPT_Type; - -/* ---------------------------------------------------------------------------- - -- HASHCRYPT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup HASHCRYPT_Register_Masks HASHCRYPT Register Masks - * @{ - */ - -/*! @name CTRL - Control register to enable and operate Hash and Crypto */ -/*! @{ */ - -#define HASHCRYPT_CTRL_MODE_MASK (0x7U) -#define HASHCRYPT_CTRL_MODE_SHIFT (0U) -/*! Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if - * specific modes beyond SHA1 and SHA2-256 are available. - * 0b000..Disabled - * 0b001..SHA1 is enabled - * 0b010..SHA2-256 is enabled - * 0b100..AES if available (see also CRYPTCFG register for more controls) - * 0b101..Reserved - */ -#define HASHCRYPT_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK) - -#define HASHCRYPT_CTRL_NEW_HASH_MASK (0x10U) -#define HASHCRYPT_CTRL_NEW_HASH_SHIFT (4U) -/*! New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING - * Status bit will clear for a cycle during the initialization from New=1. - * 0b1..Starts a new Hash/Crypto and initializes the Digest/Result. - */ -#define HASHCRYPT_CTRL_NEW_HASH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK) - -#define HASHCRYPT_CTRL_RELOAD_MASK (0x20U) -#define HASHCRYPT_CTRL_RELOAD_SHIFT (5U) -/*! Reload - If 1, allows the SHA RELOAD registers to be used. This is used to save a partial Hash - * Digest (e.g. when need to run AES) and then reload it later for continuation. - * 0b1..Allow RELOAD registers to be used. - */ -#define HASHCRYPT_CTRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_RELOAD_SHIFT)) & HASHCRYPT_CTRL_RELOAD_MASK) - -#define HASHCRYPT_CTRL_DMA_I_MASK (0x100U) -#define HASHCRYPT_CTRL_DMA_I_SHIFT (8U) -/*! DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words - * and then will process the Hash. If Cryptographic, it will load as many words as needed, - * including key if not already loaded. It will then request again. Normal model is that the DMA - * interrupts the processor when its length expires. Note that if the processor will write the key and - * optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be - * expected to load those for the 1st block (when needed). - * 0b0..DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used. - * 0b1..DMA will push in the data. - */ -#define HASHCRYPT_CTRL_DMA_I(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK) - -#define HASHCRYPT_CTRL_DMA_O_MASK (0x200U) -#define HASHCRYPT_CTRL_DMA_O_SHIFT (9U) -/*! DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the - * DMA has to know to switch direction and the locations. This can be used for crypto uses. - * 0b0..DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. - */ -#define HASHCRYPT_CTRL_DMA_O(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK) - -#define HASHCRYPT_CTRL_HASHSWPB_MASK (0x1000U) -#define HASHCRYPT_CTRL_HASHSWPB_SHIFT (12U) -/*! HASHSWPB - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB - * is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For - * cryptographic swapping, see the CRYPTCFG register. - */ -#define HASHCRYPT_CTRL_HASHSWPB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK) - -#define HASHCRYPT_CTRL_AESFLUSH_MASK (0x2000U) -#define HASHCRYPT_CTRL_AESFLUSH_SHIFT (13U) -/*! AESFLUSH - Flushes the AES engine registers. This bit self clears. - * 0b1..Flush the AES engine registers. - * 0b0..Do not flush the AES engine registers. - */ -#define HASHCRYPT_CTRL_AESFLUSH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_AESFLUSH_SHIFT)) & HASHCRYPT_CTRL_AESFLUSH_MASK) -/*! @} */ - -/*! @name STATUS - Indicates status of Hash peripheral. */ -/*! @{ */ - -#define HASHCRYPT_STATUS_WAITING_MASK (0x1U) -#define HASHCRYPT_STATUS_WAITING_SHIFT (0U) -/*! WAITING - If 1, the block is waiting for more data to process. - * 0b0..Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set - * if IsLast is set nor will it set until at least 1 word is read of the output. - * 0b1..Waiting for data to be written in (16 words) - */ -#define HASHCRYPT_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK) - -#define HASHCRYPT_STATUS_DIGEST_MASK (0x2U) -#define HASHCRYPT_STATUS_DIGEST_SHIFT (1U) -/*! DIGEST - For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block - * already started. For Cryptographic uses, this will be set for each block processed, indicating - * OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared - * when any data is written, when New is written, for Cryptographic uses when the last word is read - * out, or when the block is disabled. - * 0b0..No Digest is ready - * 0b1..Digest is ready. Application may read it or may write more data - */ -#define HASHCRYPT_STATUS_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_SHIFT)) & HASHCRYPT_STATUS_DIGEST_MASK) - -#define HASHCRYPT_STATUS_ERROR_MASK (0x4U) -#define HASHCRYPT_STATUS_ERROR_SHIFT (2U) -/*! ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA - * was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT - * field will indicate which block it was on. - * 0b0..No error. - * 0b1..An error occurred since last cleared (written 1 to clear). - */ -#define HASHCRYPT_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK) - -#define HASHCRYPT_STATUS_FAULT_MASK (0x8U) -#define HASHCRYPT_STATUS_FAULT_SHIFT (3U) -/*! FAULT - Indicates if an AES or PRNG fault has occurred - * 0b0..No AES or PRNG fault has occurred. - * 0b1..An AES or PRNG fault has occurred. - */ -#define HASHCRYPT_STATUS_FAULT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_FAULT_SHIFT)) & HASHCRYPT_STATUS_FAULT_MASK) - -#define HASHCRYPT_STATUS_NEEDKEY_MASK (0x10U) -#define HASHCRYPT_STATUS_NEEDKEY_SHIFT (4U) -/*! NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING) - * 0b0..No Key is needed and writes will not be treated as Key - * 0b1..Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. - */ -#define HASHCRYPT_STATUS_NEEDKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK) - -#define HASHCRYPT_STATUS_NEEDIV_MASK (0x20U) -#define HASHCRYPT_STATUS_NEEDIV_SHIFT (5U) -/*! NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING) - * 0b0..No IV/Nonce is needed, either because written already or because not needed. - * 0b1..IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. - */ -#define HASHCRYPT_STATUS_NEEDIV(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK) - -#define HASHCRYPT_STATUS_AESFAULT_MASK (0x100U) -#define HASHCRYPT_STATUS_AESFAULT_SHIFT (8U) -/*! AESFAULT - AES fault status - * 0b0..No AES fault has occurred. - * 0b1..An AES fault has occurred. - */ -#define HASHCRYPT_STATUS_AESFAULT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_AESFAULT_SHIFT)) & HASHCRYPT_STATUS_AESFAULT_MASK) - -#define HASHCRYPT_STATUS_PRNGFAULT_MASK (0x200U) -#define HASHCRYPT_STATUS_PRNGFAULT_SHIFT (9U) -/*! PRNGFAULT - PRNG fault status - * 0b0..No PRNG fault has occurred. - * 0b1..A PRNG fault has occurred. - */ -#define HASHCRYPT_STATUS_PRNGFAULT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_PRNGFAULT_SHIFT)) & HASHCRYPT_STATUS_PRNGFAULT_MASK) -/*! @} */ - -/*! @name INTENSET - Write 1 to enable interrupts; reads back with which are set. */ -/*! @{ */ - -#define HASHCRYPT_INTENSET_WAITING_MASK (0x1U) -#define HASHCRYPT_INTENSET_WAITING_SHIFT (0U) -/*! WAITING - Indicates if should interrupt when waiting for data input. - * 0b0..Will not interrupt when waiting. - * 0b1..Will interrupt when waiting - */ -#define HASHCRYPT_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK) - -#define HASHCRYPT_INTENSET_DIGEST_MASK (0x2U) -#define HASHCRYPT_INTENSET_DIGEST_SHIFT (1U) -/*! DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). - * 0b0..Will not interrupt when Digest is ready - * 0b1..Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). - */ -#define HASHCRYPT_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK) - -#define HASHCRYPT_INTENSET_ERROR_MASK (0x4U) -#define HASHCRYPT_INTENSET_ERROR_SHIFT (2U) -/*! ERROR - Indicates if should interrupt on an ERROR (as defined in Status) - * 0b0..Will not interrupt on Error. - * 0b1..Will interrupt on Error (until cleared). - */ -#define HASHCRYPT_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_ERROR_SHIFT)) & HASHCRYPT_INTENSET_ERROR_MASK) - -#define HASHCRYPT_INTENSET_FAULT_MASK (0x8U) -#define HASHCRYPT_INTENSET_FAULT_SHIFT (3U) -/*! FAULT - Indicates if should interrupt on an AES or PRNG fault as indicated in the STATUS register - * 0b0..No interrupt on an AES or PRNG fault - * 0b1..Interrupt on an AES or PRNG fault - */ -#define HASHCRYPT_INTENSET_FAULT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_FAULT_SHIFT)) & HASHCRYPT_INTENSET_FAULT_MASK) -/*! @} */ - -/*! @name INTENCLR - Write 1 to clear interrupts. */ -/*! @{ */ - -#define HASHCRYPT_INTENCLR_WAITING_MASK (0x1U) -#define HASHCRYPT_INTENCLR_WAITING_SHIFT (0U) -/*! WAITING - Write 1 to clear mask. - */ -#define HASHCRYPT_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK) - -#define HASHCRYPT_INTENCLR_DIGEST_MASK (0x2U) -#define HASHCRYPT_INTENCLR_DIGEST_SHIFT (1U) -/*! DIGEST - Write 1 to clear mask. - */ -#define HASHCRYPT_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK) - -#define HASHCRYPT_INTENCLR_ERROR_MASK (0x4U) -#define HASHCRYPT_INTENCLR_ERROR_SHIFT (2U) -/*! ERROR - Write 1 to clear mask. - */ -#define HASHCRYPT_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK) - -#define HASHCRYPT_INTENCLR_FAULT_MASK (0x8U) -#define HASHCRYPT_INTENCLR_FAULT_SHIFT (3U) -/*! FAULT - Write 1 to clear mask. - */ -#define HASHCRYPT_INTENCLR_FAULT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_FAULT_SHIFT)) & HASHCRYPT_INTENCLR_FAULT_MASK) -/*! @} */ - -/*! @name MEMCTRL - Setup Master to access memory (if available) */ -/*! @{ */ - -#define HASHCRYPT_MEMCTRL_MASTER_MASK (0x1U) -#define HASHCRYPT_MEMCTRL_MASTER_SHIFT (0U) -/*! MASTER - Enables mastering. - * 0b0..Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. - * 0b1..Mastering is enabled and DMA and INDATA should not be used. - */ -#define HASHCRYPT_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK) - -#define HASHCRYPT_MEMCTRL_COUNT_MASK (0x7FF0000U) -#define HASHCRYPT_MEMCTRL_COUNT_SHIFT (16U) -/*! COUNT - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks - * to copy starting at MEMADDR. This register will decrement after each block is copied, ending - * in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA - * interrupt will occur on ever block. If a bus error occurs, it will stop with this field set - * to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) - * blocks to hash. - */ -#define HASHCRYPT_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK) -/*! @} */ - -/*! @name MEMADDR - Address to start memory access from (if available). */ -/*! @{ */ - -#define HASHCRYPT_MEMADDR_BASE_MASK (0xFFFFFFFFU) -#define HASHCRYPT_MEMADDR_BASE_SHIFT (0U) -/*! BASE - Address base to start copying from, word aligned (so bits 1:0 must be 0). This field will - * advance as it processes the words. If it fails with a bus error, the register will contain - * the failing word. N:Address in Flash or RAM space; RAM only as mapped in this part. May also be - * able to address SPIFI. - */ -#define HASHCRYPT_MEMADDR_BASE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK) -/*! @} */ - -/*! @name INDATA - Input of 16 words at a time to load up buffer. */ -/*! @{ */ - -#define HASHCRYPT_INDATA_DATA_MASK (0xFFFFFFFFU) -#define HASHCRYPT_INDATA_DATA_SHIFT (0U) -/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this - * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as - * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block - * will swap the word to restore into big endian. - */ -#define HASHCRYPT_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK) -/*! @} */ - -/*! @name ALIAS - Aliases to allow writing words in a burst. */ -/*! @{ */ - -#define HASHCRYPT_ALIAS_DATA_MASK (0xFFFFFFFFU) -#define HASHCRYPT_ALIAS_DATA_SHIFT (0U) -/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this - * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as - * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block - * will swap the word to restore into big endian. - */ -#define HASHCRYPT_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK) -/*! @} */ - -/* The count of HASHCRYPT_ALIAS */ -#define HASHCRYPT_ALIAS_COUNT (7U) - -/*! @name DIGEST0 - Result digest (when status says so): • Is 1st 5 words if SHA1 used • Is all 8 words if SHA2 used • Is all 8 words if crypto or SHA512 */ -/*! @{ */ - -#define HASHCRYPT_DIGEST0_DIGEST_MASK (0xFFFFFFFFU) -#define HASHCRYPT_DIGEST0_DIGEST_SHIFT (0U) -/*! DIGEST - One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1. - */ -#define HASHCRYPT_DIGEST0_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_DIGEST0_DIGEST_SHIFT)) & HASHCRYPT_DIGEST0_DIGEST_MASK) -/*! @} */ - -/* The count of HASHCRYPT_DIGEST0 */ -#define HASHCRYPT_DIGEST0_COUNT (8U) - -/*! @name CRYPTCFG - Crypto settings for AES and Salsa and ChaCha */ -/*! @{ */ - -#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK (0x1U) -#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT (0U) -/*! MSW1ST_OUT - If 1, OUTDATA0 will be read Most significant word 1st for AES. Else it will be read - * in normal little endian - Least significant word 1st. Note: only if allowed by configuration. - */ -#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK) - -#define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK (0x2U) -#define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT (1U) -/*! SWAPKEY - If 1, will Swap the key input (bytes in each word). - */ -#define HASHCRYPT_CRYPTCFG_SWAPKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK) - -#define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK (0x4U) -#define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT (2U) -/*! SWAPDAT - If 1, will SWAP the data and IV inputs (bytes in each word). - */ -#define HASHCRYPT_CRYPTCFG_SWAPDAT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK) - -#define HASHCRYPT_CRYPTCFG_MSW1ST_MASK (0x8U) -#define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT (3U) -/*! MSW1ST - If 1, load of key, IV, and data is MSW 1st for AES. Else, the words are little endian. - * Note: only if allowed by configuration. - */ -#define HASHCRYPT_CRYPTCFG_MSW1ST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK) - -#define HASHCRYPT_CRYPTCFG_AESMODE_MASK (0x30U) -#define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT (4U) -/*! AESMODE - AES Cipher mode to use if plain AES - * 0b00..ECB - used as is - * 0b01..CBC mode (see details on IV/nonce) - * 0b10..CTR mode (see details on IV/nonce). See also AESCTRPOS. - * 0b11..reserved - */ -#define HASHCRYPT_CRYPTCFG_AESMODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK) - -#define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK (0x40U) -#define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT (6U) -/*! AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB - * 0b0..Encrypt - * 0b1..Decrypt - */ -#define HASHCRYPT_CRYPTCFG_AESDECRYPT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK) - -#define HASHCRYPT_CRYPTCFG_AESSECRET_MASK (0x80U) -#define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT (7U) -/*! AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are - * used, only the highest level is permitted to select this. - * 0b0..User key provided in normal way - * 0b1..Secret key provided in hidden way by HW - */ -#define HASHCRYPT_CRYPTCFG_AESSECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK) - -#define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK (0x300U) -#define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT (8U) -/*! AESKEYSZ - Sets the AES key size - * 0b00..128 bit key - * 0b01..192 bit key - * 0b10..256 bit key - * 0b11..reserved - */ -#define HASHCRYPT_CRYPTCFG_AESKEYSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK) - -#define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK (0x1C00U) -#define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT (10U) -/*! AESCTRPOS - Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for - * Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if - * using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other - * use CTR should use ECB directly and do its own XOR and so on. - */ -#define HASHCRYPT_CRYPTCFG_AESCTRPOS(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK) - -#define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK (0x10000U) -#define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT (16U) -/*! STREAMLAST - Is 1 if last stream block. If not 1, then the engine will compute the next "hash". - */ -#define HASHCRYPT_CRYPTCFG_STREAMLAST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK) -/*! @} */ - -/*! @name CONFIG - Returns the configuration of this block in this chip - indicates what services are available. */ -/*! @{ */ - -#define HASHCRYPT_CONFIG_DUAL_MASK (0x1U) -#define HASHCRYPT_CONFIG_DUAL_SHIFT (0U) -/*! DUAL - 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit - */ -#define HASHCRYPT_CONFIG_DUAL(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK) - -#define HASHCRYPT_CONFIG_DMA_MASK (0x2U) -#define HASHCRYPT_CONFIG_DMA_SHIFT (1U) -/*! DMA - 1 if DMA is connected - */ -#define HASHCRYPT_CONFIG_DMA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK) - -#define HASHCRYPT_CONFIG_AHB_MASK (0x8U) -#define HASHCRYPT_CONFIG_AHB_SHIFT (3U) -/*! AHB - 1 if AHB Master is enabled - */ -#define HASHCRYPT_CONFIG_AHB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK) - -#define HASHCRYPT_CONFIG_AES_MASK (0x40U) -#define HASHCRYPT_CONFIG_AES_SHIFT (6U) -/*! AES - 1 if AES 128 included - */ -#define HASHCRYPT_CONFIG_AES(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK) - -#define HASHCRYPT_CONFIG_AESKEY_MASK (0x80U) -#define HASHCRYPT_CONFIG_AESKEY_SHIFT (7U) -/*! AESKEY - 1 if AES 192 and 256 also included - */ -#define HASHCRYPT_CONFIG_AESKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK) - -#define HASHCRYPT_CONFIG_SECRET_MASK (0x100U) -#define HASHCRYPT_CONFIG_SECRET_SHIFT (8U) -/*! SECRET - 1 if AES Secret key available - */ -#define HASHCRYPT_CONFIG_SECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK) -/*! @} */ - -/*! @name LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. */ -/*! @{ */ - -#define HASHCRYPT_LOCK_SECLOCK_MASK (0x3U) -#define HASHCRYPT_LOCK_SECLOCK_SHIFT (0U) -/*! SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. - * If locked already, may only write if at same or higher security level as lock. Reads as: 0 if - * unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the - * only readable registers if locked and current state is lower than lock level. - * 0b00..Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests. - * 0b01..Locks to the current security level. AHB Master will issue requests at this level. - */ -#define HASHCRYPT_LOCK_SECLOCK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK) - -#define HASHCRYPT_LOCK_PATTERN_MASK (0xFFF0U) -#define HASHCRYPT_LOCK_PATTERN_SHIFT (4U) -/*! PATTERN - Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0 - */ -#define HASHCRYPT_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK) -/*! @} */ - -/*! @name MASK - Allows Application to write a random mask for ICB use. Normally only a new one on each system reset (including power up). */ -/*! @{ */ - -#define HASHCRYPT_MASK_MASK_MASK (0xFFFFFFFFU) -#define HASHCRYPT_MASK_MASK_SHIFT (0U) -/*! MASK - A random word. - */ -#define HASHCRYPT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK) -/*! @} */ - -/* The count of HASHCRYPT_MASK */ -#define HASHCRYPT_MASK_COUNT (4U) - -/*! @name RELOAD - The WO digest-reload registers may be written with a saved Hash digest, to allow continuation from where left off. These registers may only be written if the Reload field in CTRL is 1. If SHA1, only the 1st 5 are used. */ -/*! @{ */ - -#define HASHCRYPT_RELOAD_DIGEST_MASK (0xFFFFFFFFU) -#define HASHCRYPT_RELOAD_DIGEST_SHIFT (0U) -/*! DIGEST - SHA Digest word to reload. - */ -#define HASHCRYPT_RELOAD_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_RELOAD_DIGEST_SHIFT)) & HASHCRYPT_RELOAD_DIGEST_MASK) -/*! @} */ - -/* The count of HASHCRYPT_RELOAD */ -#define HASHCRYPT_RELOAD_COUNT (8U) - -/*! @name PRNG_SEED - PRNG random input value used as an entropy source */ -/*! @{ */ - -#define HASHCRYPT_PRNG_SEED_PRNG_SEED_MASK (0xFFFFFFFFU) -#define HASHCRYPT_PRNG_SEED_PRNG_SEED_SHIFT (0U) -/*! PRNG_SEED - Random input value used as an entropy source - */ -#define HASHCRYPT_PRNG_SEED_PRNG_SEED(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_PRNG_SEED_PRNG_SEED_SHIFT)) & HASHCRYPT_PRNG_SEED_PRNG_SEED_MASK) -/*! @} */ - -/*! @name PRNG_OUT - Provide random number. */ -/*! @{ */ - -#define HASHCRYPT_PRNG_OUT_PRNG_OUT_MASK (0xFFFFFFFFU) -#define HASHCRYPT_PRNG_OUT_PRNG_OUT_SHIFT (0U) -/*! PRNG_OUT - Provide random number. - */ -#define HASHCRYPT_PRNG_OUT_PRNG_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_PRNG_OUT_PRNG_OUT_SHIFT)) & HASHCRYPT_PRNG_OUT_PRNG_OUT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group HASHCRYPT_Register_Masks */ - - -/* HASHCRYPT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral HASHCRYPT base address */ - #define HASHCRYPT_BASE (0x500A4000u) - /** Peripheral HASHCRYPT base address */ - #define HASHCRYPT_BASE_NS (0x400A4000u) - /** Peripheral HASHCRYPT base pointer */ - #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) - /** Peripheral HASHCRYPT base pointer */ - #define HASHCRYPT_NS ((HASHCRYPT_Type *)HASHCRYPT_BASE_NS) - /** Array initializer of HASHCRYPT peripheral base addresses */ - #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } - /** Array initializer of HASHCRYPT peripheral base pointers */ - #define HASHCRYPT_BASE_PTRS { HASHCRYPT } - /** Array initializer of HASHCRYPT peripheral base addresses */ - #define HASHCRYPT_BASE_ADDRS_NS { HASHCRYPT_BASE_NS } - /** Array initializer of HASHCRYPT peripheral base pointers */ - #define HASHCRYPT_BASE_PTRS_NS { HASHCRYPT_NS } -#else - /** Peripheral HASHCRYPT base address */ - #define HASHCRYPT_BASE (0x400A4000u) - /** Peripheral HASHCRYPT base pointer */ - #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) - /** Array initializer of HASHCRYPT peripheral base addresses */ - #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } - /** Array initializer of HASHCRYPT peripheral base pointers */ - #define HASHCRYPT_BASE_PTRS { HASHCRYPT } -#endif - -/*! - * @} - */ /* end of group HASHCRYPT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2C Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer - * @{ - */ - -/** I2C - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[2048]; - __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ - __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ - __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ - __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ - __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ - __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ - uint8_t RESERVED_1[4]; - __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ - __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ - __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ - uint8_t RESERVED_2[20]; - __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ - __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ - __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ - __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ - uint8_t RESERVED_3[36]; - __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ - uint8_t RESERVED_4[1912]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} I2C_Type; - -/* ---------------------------------------------------------------------------- - -- I2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Register_Masks I2C Register Masks - * @{ - */ - -/*! @name CFG - Configuration for shared functions. */ -/*! @{ */ - -#define I2C_CFG_MSTEN_MASK (0x1U) -#define I2C_CFG_MSTEN_SHIFT (0U) -/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not - * changed, but the Master function is internally reset. - * 0b0..Disabled. The I2C Master function is disabled. - * 0b1..Enabled. The I2C Master function is enabled. - */ -#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) - -#define I2C_CFG_SLVEN_MASK (0x2U) -#define I2C_CFG_SLVEN_SHIFT (1U) -/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not - * changed, but the Slave function is internally reset. - * 0b0..Disabled. The I2C slave function is disabled. - * 0b1..Enabled. The I2C slave function is enabled. - */ -#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) - -#define I2C_CFG_MONEN_MASK (0x4U) -#define I2C_CFG_MONEN_SHIFT (2U) -/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not - * changed, but the Monitor function is internally reset. - * 0b0..Disabled. The I2C Monitor function is disabled. - * 0b1..Enabled. The I2C Monitor function is enabled. - */ -#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) - -#define I2C_CFG_TIMEOUTEN_MASK (0x8U) -#define I2C_CFG_TIMEOUTEN_SHIFT (3U) -/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. - * 0b0..Disabled. Time-out function is disabled. - * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause - * interrupts if they are enabled. Typically, only one time-out will be used in a system. - */ -#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) - -#define I2C_CFG_MONCLKSTR_MASK (0x10U) -#define I2C_CFG_MONCLKSTR_SHIFT (4U) -/*! MONCLKSTR - Monitor function Clock Stretching. - * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able - * to read data provided by the Monitor function before it is overwritten. This mode may be used when - * non-invasive monitoring is critical. - * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can - * read all incoming data supplied by the Monitor function. - */ -#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) - -#define I2C_CFG_HSCAPABLE_MASK (0x20U) -#define I2C_CFG_HSCAPABLE_SHIFT (5U) -/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive - * and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies - * to all functions: Master, Slave, and Monitor. - * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the - * extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, - * such as changing the drive strength or filtering, must be made by software via the IOCON register associated - * with each I2C pin, - * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support - * High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more - * information. - */ -#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) -/*! @} */ - -/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ -/*! @{ */ - -#define I2C_STAT_MSTPENDING_MASK (0x1U) -#define I2C_STAT_MSTPENDING_SHIFT (0U) -/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on - * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what - * type of software service if any the master expects. This flag will cause an interrupt when set - * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling - * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle - * state, and no communication is needed, mask this interrupt. - * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. - * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the - * idle state, it is waiting to receive or transmit data or the NACK bit. - */ -#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) - -#define I2C_STAT_MSTSTATE_MASK (0xEU) -#define I2C_STAT_MSTSTATE_SHIFT (1U) -/*! MSTSTATE - Master State code. The master state code reflects the master state when the - * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field - * indicates a specific required service for the Master function. All other values are reserved. See - * Table 400 for details of state values and appropriate responses. - * 0b000..Idle. The Master function is available to be used for a new transaction. - * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. - * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. - * 0b011..NACK Address. Slave NACKed address. - * 0b100..NACK Data. Slave NACKed transmitted data. - */ -#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) - -#define I2C_STAT_MSTARBLOSS_MASK (0x10U) -#define I2C_STAT_MSTARBLOSS_SHIFT (4U) -/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to - * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - * 0b0..No Arbitration Loss has occurred. - * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master - * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, - * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. - */ -#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) - -#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) -/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to - * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - * 0b0..No Start/Stop Error has occurred. - * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is - * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an - * idle state, no action is required. A request for a Start could be made, or software could attempt to insure - * that the bus has not stalled. - */ -#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) - -#define I2C_STAT_SLVPENDING_MASK (0x100U) -#define I2C_STAT_SLVPENDING_SHIFT (8U) -/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue - * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if - * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the - * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is - * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time - * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section - * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are - * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must - * also be detected automatically, since the address must be acknowledged before the clock can be - * stretched. - * 0b0..In progress. The Slave function does not currently need service. - * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. - */ -#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) - -#define I2C_STAT_SLVSTATE_MASK (0x600U) -#define I2C_STAT_SLVSTATE_SHIFT (9U) -/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for - * the Slave function. All other values are reserved. See Table 401 for state values and actions. - * note that the occurrence of some states and how they are handled are affected by DMA mode and - * Automatic Operation modes. - * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. - * 0b01..Slave receive. Received data is available (Slave Receiver mode). - * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). - */ -#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) - -#define I2C_STAT_SLVNOTSTR_MASK (0x800U) -#define I2C_STAT_SLVNOTSTR_SHIFT (11U) -/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. - * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave - * operation. This read-only flag reflects the slave function status in real time. - * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. - * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or - * Power-down mode could be entered at this time. - */ -#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) - -#define I2C_STAT_SLVIDX_MASK (0x3000U) -#define I2C_STAT_SLVIDX_SHIFT (12U) -/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been - * selected by receiving an address that matches one of the slave addresses defined by any enabled - * slave address registers, and provides an identification of the address that was matched. It is - * possible that more than one address could be matched, but only one match can be reported here. - * 0b00..Address 0. Slave address 0 was matched. - * 0b01..Address 1. Slave address 1 was matched. - * 0b10..Address 2. Slave address 2 was matched. - * 0b11..Address 3. Slave address 3 was matched. - */ -#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) - -#define I2C_STAT_SLVSEL_MASK (0x4000U) -#define I2C_STAT_SLVSEL_SHIFT (14U) -/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave - * function to acknowledge the address, or when the address has been automatically acknowledged. - * It is cleared when another address cycle presents an address that does not match an enabled - * address on the Slave function, when slave software decides to NACK a matched address, when - * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of - * Automatic Operation. SLVSEL is not cleared if software NACKs data. - * 0b0..Not selected. The Slave function is not currently selected. - * 0b1..Selected. The Slave function is currently selected. - */ -#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) - -#define I2C_STAT_SLVDESEL_MASK (0x8000U) -#define I2C_STAT_SLVDESEL_SHIFT (15U) -/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via - * INTENSET. This flag can be cleared by writing a 1 to this bit. - * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently - * selected. That information can be found in the SLVSEL flag. - * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag - * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. - */ -#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) - -#define I2C_STAT_MONRDY_MASK (0x10000U) -#define I2C_STAT_MONRDY_SHIFT (16U) -/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. - * 0b0..No data. The Monitor function does not currently have data available. - * 0b1..Data waiting. The Monitor function has data waiting to be read. - */ -#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) - -#define I2C_STAT_MONOV_MASK (0x20000U) -#define I2C_STAT_MONOV_SHIFT (17U) -/*! MONOV - Monitor Overflow flag. - * 0b0..No overrun. Monitor data has not overrun. - * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not - * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. - */ -#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) - -#define I2C_STAT_MONACTIVE_MASK (0x40000U) -#define I2C_STAT_MONACTIVE_SHIFT (18U) -/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to - * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred - * more recently than a bus Stop. - * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. - * 0b1..Active. The Monitor function considers the I2C bus to be active. - */ -#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) - -#define I2C_STAT_MONIDLE_MASK (0x80000U) -#define I2C_STAT_MONIDLE_SHIFT (19U) -/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change - * from active to inactive. This can be used by software to decide when to process data - * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the - * INTENSET register. The flag can be cleared by writing a 1 to this bit. - * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. - * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. - */ -#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) - -#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) -/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been - * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock - * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus - * is idle. - * 0b0..No time-out. I2C bus events have not caused a time-out. - * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. - */ -#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) - -#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) -/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the - * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. - * 0b0..No time-out. SCL low time has not caused a time-out. - * 0b1..Time-out. SCL low time has caused a time-out. - */ -#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable Set and read register. */ -/*! @{ */ - -#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) -#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) -/*! MSTPENDINGEN - Master Pending interrupt Enable. - * 0b0..Disabled. The MstPending interrupt is disabled. - * 0b1..Enabled. The MstPending interrupt is enabled. - */ -#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) - -#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) -#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) -/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. - * 0b0..Disabled. The MstArbLoss interrupt is disabled. - * 0b1..Enabled. The MstArbLoss interrupt is enabled. - */ -#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) - -#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) -#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) -/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. - * 0b0..Disabled. The MstStStpErr interrupt is disabled. - * 0b1..Enabled. The MstStStpErr interrupt is enabled. - */ -#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) - -#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) -#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) -/*! SLVPENDINGEN - Slave Pending interrupt Enable. - * 0b0..Disabled. The SlvPending interrupt is disabled. - * 0b1..Enabled. The SlvPending interrupt is enabled. - */ -#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) - -#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) -#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) -/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. - * 0b0..Disabled. The SlvNotStr interrupt is disabled. - * 0b1..Enabled. The SlvNotStr interrupt is enabled. - */ -#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) - -#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) -#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) -/*! SLVDESELEN - Slave Deselect interrupt Enable. - * 0b0..Disabled. The SlvDeSel interrupt is disabled. - * 0b1..Enabled. The SlvDeSel interrupt is enabled. - */ -#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) - -#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) -#define I2C_INTENSET_MONRDYEN_SHIFT (16U) -/*! MONRDYEN - Monitor data Ready interrupt Enable. - * 0b0..Disabled. The MonRdy interrupt is disabled. - * 0b1..Enabled. The MonRdy interrupt is enabled. - */ -#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) - -#define I2C_INTENSET_MONOVEN_MASK (0x20000U) -#define I2C_INTENSET_MONOVEN_SHIFT (17U) -/*! MONOVEN - Monitor Overrun interrupt Enable. - * 0b0..Disabled. The MonOv interrupt is disabled. - * 0b1..Enabled. The MonOv interrupt is enabled. - */ -#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) - -#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) -#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) -/*! MONIDLEEN - Monitor Idle interrupt Enable. - * 0b0..Disabled. The MonIdle interrupt is disabled. - * 0b1..Enabled. The MonIdle interrupt is enabled. - */ -#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) - -#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) -#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) -/*! EVENTTIMEOUTEN - Event time-out interrupt Enable. - * 0b0..Disabled. The Event time-out interrupt is disabled. - * 0b1..Enabled. The Event time-out interrupt is enabled. - */ -#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) - -#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) -#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) -/*! SCLTIMEOUTEN - SCL time-out interrupt Enable. - * 0b0..Disabled. The SCL time-out interrupt is disabled. - * 0b1..Enabled. The SCL time-out interrupt is enabled. - */ -#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear register. */ -/*! @{ */ - -#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) -#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) -/*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding - * bit in the INTENSET register if implemented. - */ -#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) - -#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) -#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) -/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear. - */ -#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) - -#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) -#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) -/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear. - */ -#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) - -#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) -#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) -/*! SLVPENDINGCLR - Slave Pending interrupt clear. - */ -#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) - -#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) -#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) -/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear. - */ -#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) - -#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) -#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) -/*! SLVDESELCLR - Slave Deselect interrupt clear. - */ -#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) - -#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) -#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) -/*! MONRDYCLR - Monitor data Ready interrupt clear. - */ -#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) - -#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) -#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) -/*! MONOVCLR - Monitor Overrun interrupt clear. - */ -#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) - -#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) -#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) -/*! MONIDLECLR - Monitor Idle interrupt clear. - */ -#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) - -#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) -#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) -/*! EVENTTIMEOUTCLR - Event time-out interrupt clear. - */ -#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) - -#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) -#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) -/*! SCLTIMEOUTCLR - SCL time-out interrupt clear. - */ -#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) -/*! @} */ - -/*! @name TIMEOUT - Time-out value register. */ -/*! @{ */ - -#define I2C_TIMEOUT_TOMIN_MASK (0xFU) -#define I2C_TIMEOUT_TOMIN_SHIFT (0U) -/*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum - * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. - */ -#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) - -#define I2C_TIMEOUT_TO_MASK (0xFFF0U) -#define I2C_TIMEOUT_TO_SHIFT (4U) -/*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C - * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, - * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A - * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after - * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the - * I2C function clock. - */ -#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) -/*! @} */ - -/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ -/*! @{ */ - -#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) -#define I2C_CLKDIV_DIVVAL_SHIFT (0U) -/*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that - * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = - * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is - * divided by 65,536 before use. - */ -#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ -/*! @{ */ - -#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) -#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) -/*! MSTPENDING - Master Pending. - */ -#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) - -#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) -#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) -/*! MSTARBLOSS - Master Arbitration Loss flag. - */ -#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) - -#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) -/*! MSTSTSTPERR - Master Start/Stop Error flag. - */ -#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) - -#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) -#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) -/*! SLVPENDING - Slave Pending. - */ -#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) - -#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) -#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) -/*! SLVNOTSTR - Slave Not Stretching status. - */ -#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) - -#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) -#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) -/*! SLVDESEL - Slave Deselected flag. - */ -#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) - -#define I2C_INTSTAT_MONRDY_MASK (0x10000U) -#define I2C_INTSTAT_MONRDY_SHIFT (16U) -/*! MONRDY - Monitor Ready. - */ -#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) - -#define I2C_INTSTAT_MONOV_MASK (0x20000U) -#define I2C_INTSTAT_MONOV_SHIFT (17U) -/*! MONOV - Monitor Overflow flag. - */ -#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) - -#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) -#define I2C_INTSTAT_MONIDLE_SHIFT (19U) -/*! MONIDLE - Monitor Idle flag. - */ -#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) - -#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) -/*! EVENTTIMEOUT - Event time-out Interrupt flag. - */ -#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) - -#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) -/*! SCLTIMEOUT - SCL time-out Interrupt flag. - */ -#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name MSTCTL - Master control register. */ -/*! @{ */ - -#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) -#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) -/*! MSTCONTINUE - Master Continue. This bit is write-only. - * 0b0..No effect. - * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing - * transmit data, reading received data, or any other housekeeping related to the next bus operation. - */ -#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) - -#define I2C_MSTCTL_MSTSTART_MASK (0x2U) -#define I2C_MSTCTL_MSTSTART_SHIFT (1U) -/*! MSTSTART - Master Start control. This bit is write-only. - * 0b0..No effect. - * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. - */ -#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) - -#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) -#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) -/*! MSTSTOP - Master Stop control. This bit is write-only. - * 0b0..No effect. - * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave - * if the master is receiving data from the slave (Master Receiver mode). - */ -#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) - -#define I2C_MSTCTL_MSTDMA_MASK (0x8U) -#define I2C_MSTCTL_MSTDMA_SHIFT (3U) -/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type - * operations such as Start, address, Stop, and address match must always be done with software, - * typically via an interrupt. Address acknowledgement must also be done by software except when - * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by - * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA - * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is - * read/write. - * 0b0..Disable. No DMA requests are generated for master operation. - * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating - * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. - */ -#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) -/*! @} */ - -/*! @name MSTTIME - Master timing configuration. */ -/*! @{ */ - -#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) -#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) -/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this - * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This - * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters - * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. - * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. - * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. - * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. - * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. - * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. - * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. - * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. - * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. - */ -#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) - -#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) -#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) -/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this - * master on SCL. Other masters in a multi-master system could shorten this time. This - * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters - * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. - * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. - * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . - * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. - * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. - * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. - * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. - * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. - * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. - */ -#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) -/*! @} */ - -/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ -/*! @{ */ - -#define I2C_MSTDAT_DATA_MASK (0xFFU) -#define I2C_MSTDAT_DATA_SHIFT (0U) -/*! DATA - Master function data register. Read: read the most recently received data for the Master - * function. Write: transmit data using the Master function. - */ -#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVCTL - Slave control register. */ -/*! @{ */ - -#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) -#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) -/*! SLVCONTINUE - Slave Continue. - * 0b0..No effect. - * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag - * in the STAT register. This must be done after writing transmit data, reading received data, or any other - * housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE - * should not be set unless SLVPENDING = 1. - */ -#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) - -#define I2C_SLVCTL_SLVNACK_MASK (0x2U) -#define I2C_SLVCTL_SLVNACK_SHIFT (1U) -/*! SLVNACK - Slave NACK. - * 0b0..No effect. - * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). - */ -#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) - -#define I2C_SLVCTL_SLVDMA_MASK (0x8U) -#define I2C_SLVCTL_SLVDMA_SHIFT (3U) -/*! SLVDMA - Slave DMA enable. - * 0b0..Disabled. No DMA requests are issued for Slave mode operation. - * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. - */ -#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) - -#define I2C_SLVCTL_AUTOACK_MASK (0x100U) -#define I2C_SLVCTL_AUTOACK_SHIFT (8U) -/*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches - * SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA - * to allow processing of the data without intervention. If this bit is clear and a header - * matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or - * interrupt. - * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching - * address is received. If AUTONACK = 1, received addresses are NACKed (ignored). - * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, - * allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does - * not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK - * is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. - */ -#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) - -#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) -#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) -/*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write - * request on the next header with an address matching SLVADR0. Since DMA needs to be configured to - * match the transfer direction, the direction needs to be specified. This bit allows a direction to - * be chosen for the next operation. - * 0b0..The expected next operation in Automatic Mode is an I2C write. - * 0b1..The expected next operation in Automatic Mode is an I2C read. - */ -#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) -/*! @} */ - -/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ -/*! @{ */ - -#define I2C_SLVDAT_DATA_MASK (0xFFU) -#define I2C_SLVDAT_DATA_SHIFT (0U) -/*! DATA - Slave function data register. Read: read the most recently received data for the Slave - * function. Write: transmit data using the Slave function. - */ -#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVADR - Slave address register. */ -/*! @{ */ - -#define I2C_SLVADR_SADISABLE_MASK (0x1U) -#define I2C_SLVADR_SADISABLE_SHIFT (0U) -/*! SADISABLE - Slave Address n Disable. - * 0b0..Enabled. Slave Address n is enabled. - * 0b1..Ignored Slave Address n is ignored. - */ -#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) - -#define I2C_SLVADR_SLVADR_MASK (0xFEU) -#define I2C_SLVADR_SLVADR_SHIFT (1U) -/*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. - */ -#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) - -#define I2C_SLVADR_AUTONACK_MASK (0x8000U) -#define I2C_SLVADR_AUTONACK_SHIFT (15U) -/*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows - * software to ignore I2C traffic while handling previous I2C data or other operations. - * 0b0..Normal operation, matching I2C addresses are not ignored. - * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches - * SLVADRn, and AUTOMATCHREAD matches the direction. - */ -#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) -/*! @} */ - -/* The count of I2C_SLVADR */ -#define I2C_SLVADR_COUNT (4U) - -/*! @name SLVQUAL0 - Slave Qualification for address 0. */ -/*! @{ */ - -#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) -#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) -/*! QUALMODE0 - Qualify mode for slave address 0. - * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. - * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. - */ -#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) - -#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) -#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) -/*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to - * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is - * set to 1 will cause an automatic match of the corresponding bit of the received address when it - * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for - * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 - * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). - */ -#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) -/*! @} */ - -/*! @name MONRXDAT - Monitor receiver data register. */ -/*! @{ */ - -#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) -#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) -/*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. - */ -#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) - -#define I2C_MONRXDAT_MONSTART_MASK (0x100U) -#define I2C_MONRXDAT_MONSTART_SHIFT (8U) -/*! MONSTART - Monitor Received Start. - * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. - * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. - */ -#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) - -#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) -#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) -/*! MONRESTART - Monitor Received Repeated Start. - * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. - * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. - */ -#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) - -#define I2C_MONRXDAT_MONNACK_MASK (0x400U) -#define I2C_MONRXDAT_MONNACK_SHIFT (10U) -/*! MONNACK - Monitor Received NACK. - * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. - * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. - */ -#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ - -#define I2C_ID_MINOR_REV_MASK (0xF00U) -#define I2C_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation. - */ -#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) - -#define I2C_ID_MAJOR_REV_MASK (0xF000U) -#define I2C_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation. - */ -#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) - -#define I2C_ID_ID_MASK (0xFFFF0000U) -#define I2C_ID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function. - */ -#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2C_Register_Masks */ - - -/* I2C - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral I2C0 base address */ - #define I2C0_BASE (0x50086000u) - /** Peripheral I2C0 base address */ - #define I2C0_BASE_NS (0x40086000u) - /** Peripheral I2C0 base pointer */ - #define I2C0 ((I2C_Type *)I2C0_BASE) - /** Peripheral I2C0 base pointer */ - #define I2C0_NS ((I2C_Type *)I2C0_BASE_NS) - /** Peripheral I2C1 base address */ - #define I2C1_BASE (0x50087000u) - /** Peripheral I2C1 base address */ - #define I2C1_BASE_NS (0x40087000u) - /** Peripheral I2C1 base pointer */ - #define I2C1 ((I2C_Type *)I2C1_BASE) - /** Peripheral I2C1 base pointer */ - #define I2C1_NS ((I2C_Type *)I2C1_BASE_NS) - /** Peripheral I2C2 base address */ - #define I2C2_BASE (0x50088000u) - /** Peripheral I2C2 base address */ - #define I2C2_BASE_NS (0x40088000u) - /** Peripheral I2C2 base pointer */ - #define I2C2 ((I2C_Type *)I2C2_BASE) - /** Peripheral I2C2 base pointer */ - #define I2C2_NS ((I2C_Type *)I2C2_BASE_NS) - /** Peripheral I2C3 base address */ - #define I2C3_BASE (0x50089000u) - /** Peripheral I2C3 base address */ - #define I2C3_BASE_NS (0x40089000u) - /** Peripheral I2C3 base pointer */ - #define I2C3 ((I2C_Type *)I2C3_BASE) - /** Peripheral I2C3 base pointer */ - #define I2C3_NS ((I2C_Type *)I2C3_BASE_NS) - /** Peripheral I2C4 base address */ - #define I2C4_BASE (0x5008A000u) - /** Peripheral I2C4 base address */ - #define I2C4_BASE_NS (0x4008A000u) - /** Peripheral I2C4 base pointer */ - #define I2C4 ((I2C_Type *)I2C4_BASE) - /** Peripheral I2C4 base pointer */ - #define I2C4_NS ((I2C_Type *)I2C4_BASE_NS) - /** Peripheral I2C5 base address */ - #define I2C5_BASE (0x50096000u) - /** Peripheral I2C5 base address */ - #define I2C5_BASE_NS (0x40096000u) - /** Peripheral I2C5 base pointer */ - #define I2C5 ((I2C_Type *)I2C5_BASE) - /** Peripheral I2C5 base pointer */ - #define I2C5_NS ((I2C_Type *)I2C5_BASE_NS) - /** Peripheral I2C6 base address */ - #define I2C6_BASE (0x50097000u) - /** Peripheral I2C6 base address */ - #define I2C6_BASE_NS (0x40097000u) - /** Peripheral I2C6 base pointer */ - #define I2C6 ((I2C_Type *)I2C6_BASE) - /** Peripheral I2C6 base pointer */ - #define I2C6_NS ((I2C_Type *)I2C6_BASE_NS) - /** Peripheral I2C7 base address */ - #define I2C7_BASE (0x50098000u) - /** Peripheral I2C7 base address */ - #define I2C7_BASE_NS (0x40098000u) - /** Peripheral I2C7 base pointer */ - #define I2C7 ((I2C_Type *)I2C7_BASE) - /** Peripheral I2C7 base pointer */ - #define I2C7_NS ((I2C_Type *)I2C7_BASE_NS) - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS_NS { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS_NS { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS } -#else - /** Peripheral I2C0 base address */ - #define I2C0_BASE (0x40086000u) - /** Peripheral I2C0 base pointer */ - #define I2C0 ((I2C_Type *)I2C0_BASE) - /** Peripheral I2C1 base address */ - #define I2C1_BASE (0x40087000u) - /** Peripheral I2C1 base pointer */ - #define I2C1 ((I2C_Type *)I2C1_BASE) - /** Peripheral I2C2 base address */ - #define I2C2_BASE (0x40088000u) - /** Peripheral I2C2 base pointer */ - #define I2C2 ((I2C_Type *)I2C2_BASE) - /** Peripheral I2C3 base address */ - #define I2C3_BASE (0x40089000u) - /** Peripheral I2C3 base pointer */ - #define I2C3 ((I2C_Type *)I2C3_BASE) - /** Peripheral I2C4 base address */ - #define I2C4_BASE (0x4008A000u) - /** Peripheral I2C4 base pointer */ - #define I2C4 ((I2C_Type *)I2C4_BASE) - /** Peripheral I2C5 base address */ - #define I2C5_BASE (0x40096000u) - /** Peripheral I2C5 base pointer */ - #define I2C5 ((I2C_Type *)I2C5_BASE) - /** Peripheral I2C6 base address */ - #define I2C6_BASE (0x40097000u) - /** Peripheral I2C6 base pointer */ - #define I2C6 ((I2C_Type *)I2C6_BASE) - /** Peripheral I2C7 base address */ - #define I2C7_BASE (0x40098000u) - /** Peripheral I2C7 base pointer */ - #define I2C7 ((I2C_Type *)I2C7_BASE) - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } -#endif -/** Interrupt vectors for the I2C peripheral type */ -#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2C_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2S Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer - * @{ - */ - -/** I2S - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[3072]; - __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ - __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ - __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ - struct { /* offset: 0xC20, array step: 0x20 */ - __IO uint32_t PCFG1; /**< Configuration register 1 for channel pair, array offset: 0xC20, array step: 0x20 */ - __IO uint32_t PCFG2; /**< Configuration register 2 for channel pair, array offset: 0xC24, array step: 0x20 */ - __IO uint32_t PSTAT; /**< Status register for channel pair, array offset: 0xC28, array step: 0x20 */ - uint8_t RESERVED_0[20]; - } SECCHANNEL[3]; - uint8_t RESERVED_2[384]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ - uint8_t RESERVED_5[8]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ - uint8_t RESERVED_6[8]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ - __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ - uint8_t RESERVED_7[432]; - __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */ -} I2S_Type; - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ -/*! @{ */ - -#define I2S_CFG1_MAINENABLE_MASK (0x1U) -#define I2S_CFG1_MAINENABLE_SHIFT (0U) -/*! MAINENABLE - Main enable for I 2S function in this Flexcomm - * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags - * are reset. No other channel pairs can be enabled. - * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. - */ -#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) - -#define I2S_CFG1_DATAPAUSE_MASK (0x2U) -#define I2S_CFG1_DATAPAUSE_SHIFT (1U) -/*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer - * and the FIFO. This could be done in order to change streams, or while restarting after a data - * underflow or overflow. When paused, FIFO operations can be done without corrupting data that is - * in the process of being sent or received. Once a data pause has been requested, the interface - * may need to complete sending data that was in progress before interrupting the flow of data. - * Software must check that the pause is actually in effect before taking action. This is done by - * monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer - * will resume at the beginning of the next frame. - * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. - * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. - */ -#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) - -#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) -#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) -/*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field - * whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this - * Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs - * in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. - * 0b00..1 I2S channel pairs in this flexcomm - * 0b01..2 I2S channel pairs in this flexcomm - * 0b10..3 I2S channel pairs in this flexcomm - * 0b11..4 I2S channel pairs in this flexcomm - */ -#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) - -#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) -#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) -/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. - * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. - * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of - * SCK, when divided from the Flexcomm function clock. - * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. - * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. - */ -#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) - -#define I2S_CFG1_MODE_MASK (0xC0U) -#define I2S_CFG1_MODE_SHIFT (6U) -/*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all - * supported cases. See Formats and modes for examples. - * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece - * of left channel data occurring during the first phase, and one pieces of right channel data occurring - * during the second phase. In this mode, the data region begins one clock after the leading WS edge for the - * frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If - * FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. - * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0. - * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame. - * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame. - */ -#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) - -#define I2S_CFG1_RIGHTLOW_MASK (0x100U) -#define I2S_CFG1_RIGHTLOW_SHIFT (8U) -/*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left - * and right channel data as it is transferred to or from the FIFO. This bit is not used if the - * data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 - * of this register) = 1, the one channel to be used is the nominally the left channel. POSITION - * can still place that data in the frame where right channel data is normally located. if all - * enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. - * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO - * bits 31:16 are used for the right channel. - * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO - * bits 15:0 are used for the right channel. - */ -#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) - -#define I2S_CFG1_LEFTJUST_MASK (0x200U) -#define I2S_CFG1_LEFTJUST_SHIFT (9U) -/*! LEFTJUST - Left Justify data. - * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting - * from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data - * in the stream on the data bus. - * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting - * from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would - * correspond to left justified data in the stream on the data bus. - */ -#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) - -#define I2S_CFG1_ONECHANNEL_MASK (0x400U) -#define I2S_CFG1_ONECHANNEL_SHIFT (10U) -/*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit - * applies only to the first I2S channel pair. Other channel pairs may select this mode - * independently in their separate CFG1 registers. - * 0b0..I2S data for this channel pair is treated as left and right channels. - * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this - * pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a - * clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel - * of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side - * (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data - * for the single channel of data is placed at the clock defined by POSITION. - */ -#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) - -#define I2S_CFG1_SCK_POL_MASK (0x1000U) -#define I2S_CFG1_SCK_POL_SHIFT (12U) -/*! SCK_POL - SCK polarity. - * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). - * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges. - */ -#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) - -#define I2S_CFG1_WS_POL_MASK (0x2000U) -#define I2S_CFG1_WS_POL_SHIFT (13U) -/*! WS_POL - WS polarity. - * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S). - * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). - */ -#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) - -#define I2S_CFG1_DATALEN_MASK (0x1F0000U) -#define I2S_CFG1_DATALEN_SHIFT (16U) -/*! DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or - * received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received - * from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the - * I2S: Determines the size of data transfers between the FIFO and the I2S - * serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of - * right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse - * at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to - * 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = - * data is 32 bits in length - */ -#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) -/*! @} */ - -/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ -/*! @{ */ - -#define I2S_CFG2_FRAMELEN_MASK (0x7FFU) -#define I2S_CFG2_FRAMELEN_SHIFT (0U) -/*! FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the - * frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported - * 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x7FF = frame is - * 2048 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in - * mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger - * than DATALEN in order for the WS pulse to be generated correctly. - */ -#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) - -#define I2S_CFG2_POSITION_MASK (0x1FF0000U) -#define I2S_CFG2_POSITION_SHIFT (16U) -/*! POSITION - Data Position. Defines the location within the frame of the data for this channel - * pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION - * defines the location of data in both the left phase and right phase, starting one clock after - * the WS edge. In other modes, POSITION defines the location of data within the entire frame. - * ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The - * combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels - * do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit - * position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS - * phase. 0x002 = data begins at bit position 2 within the frame or WS phase. - */ -#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) -/*! @} */ - -/*! @name STAT - Status register for the primary channel pair. */ -/*! @{ */ - -#define I2S_STAT_BUSY_MASK (0x1U) -#define I2S_STAT_BUSY_SHIFT (0U) -/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. - * 0b0..The transmitter/receiver for channel pair is currently idle. - * 0b1..The transmitter/receiver for channel pair is currently processing data. - */ -#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) - -#define I2S_STAT_SLVFRMERR_MASK (0x2U) -#define I2S_STAT_SLVFRMERR_SHIFT (1U) -/*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as - * a slave. An error indicates that the incoming WS signal did not transition as expected due to - * a mismatch between FRAMELEN and the actual incoming I2S stream. - * 0b0..No error has been recorded. - * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. - */ -#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) - -#define I2S_STAT_LR_MASK (0x4U) -#define I2S_STAT_LR_SHIFT (2U) -/*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to - * be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data - * being processed for the currently busy channel pair. - * 0b0..Left channel. - * 0b1..Right channel. - */ -#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) - -#define I2S_STAT_DATAPAUSED_MASK (0x8U) -#define I2S_STAT_DATAPAUSED_SHIFT (3U) -/*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels - * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for - * an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. - * 0b1..A data pause has been requested and is now in force. - */ -#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) -/*! @} */ - -/*! @name DIV - Clock divider, used by all channel pairs. */ -/*! @{ */ - -#define I2S_DIV_DIV_MASK (0xFFFU) -#define I2S_DIV_DIV_SHIFT (0U) -/*! DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The - * Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. - * 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is - * divided by 4,096. - */ -#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) -/*! @} */ - -/*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */ -/*! @{ */ - -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U) -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U) -/*! PAIRENABLE - Enable for this channel pair. - * 0b0..This I2S channel pair is disabled. - * 0b1..This I2S channel pair is enabled. - */ -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK) - -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U) -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U) -/*! ONECHANNEL - Single channel mode. - * 0b0..I2S data for this channel pair is treated as left and right channels. - * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. - */ -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK) -/*! @} */ - -/* The count of I2S_SECCHANNEL_PCFG1 */ -#define I2S_SECCHANNEL_PCFG1_COUNT (3U) - -/*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */ -/*! @{ */ - -#define I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U) -#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U) -/*! POSITION - Data Position. - */ -#define I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK) -/*! @} */ - -/* The count of I2S_SECCHANNEL_PCFG2 */ -#define I2S_SECCHANNEL_PCFG2_COUNT (3U) - -/*! @name SECCHANNEL_PSTAT - Status register for channel pair */ -/*! @{ */ - -#define I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U) -#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U) -/*! BUSY - Busy status for this channel pair. - * 0b0..The transmitter/receiver for this channel pair is currently idle. - * 0b1..The transmitter/receiver for this channel pair is currently processing data. - */ -#define I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK) - -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U) -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U) -/*! SLVFRMERR - Save Frame Error flag. - */ -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK) - -#define I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U) -#define I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U) -/*! LR - Left/Right indication. - */ -#define I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK) - -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U) -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U) -/*! DATAPAUSED - Data Paused status flag. - * 0b0..Data is not currently paused. - * 0b1..A data pause has been requested and is now in force. - */ -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK) -/*! @} */ - -/* The count of I2S_SECCHANNEL_PSTAT */ -#define I2S_SECCHANNEL_PSTAT_COUNT (3U) - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ - -#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) -#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) - -#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) -#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) - -#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) -#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) -/*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX - * FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is - * cleared, new data is provided, and the I2S is un-paused. - * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 - * bits or less, or when MONO = 1 for this channel pair. - * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. - */ -#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) - -#define I2S_FIFOCFG_PACK48_MASK (0x8U) -#define I2S_FIFOCFG_PACK48_SHIFT (3U) -/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. - * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values. - * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. - */ -#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) - -#define I2S_FIFOCFG_SIZE_MASK (0x30U) -#define I2S_FIFOCFG_SIZE_SHIFT (4U) -/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 - * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - */ -#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) - -#define I2S_FIFOCFG_DMATX_MASK (0x1000U) -#define I2S_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) - -#define I2S_FIFOCFG_DMARX_MASK (0x2000U) -#define I2S_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) - -#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) -#define I2S_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in - * FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) - -#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) -#define I2S_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in - * FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) - -#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) -/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - */ -#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) - -#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) -/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - */ -#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ - -#define I2S_FIFOSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow - * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is - * needed. Cleared by writing a 1 to this bit. - */ -#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) - -#define I2S_FIFOSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA - * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - */ -#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) - -#define I2S_FIFOSTAT_PERINT_MASK (0x8U) -#define I2S_FIFOSTAT_PERINT_SHIFT (3U) -/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted - * an interrupt. The details can be found by reading the peripheral's STAT register. - */ -#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) - -#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) -/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - */ -#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) - -#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) -/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be - * written. When 0, the transmit FIFO is full and another write would cause it to overflow. - */ -#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) - -#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - */ -#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) - -#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) -#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) -/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to - * prevent the peripheral from causing an overflow. - */ -#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) - -#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY - * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at - * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be - * 0. - */ -#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) - -#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and - * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the - * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be - * 1. - */ -#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ - -#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) - -#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) - -#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) -#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled - * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to - * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO - * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX - * FIFO level decreases to 15 entries (is no longer full). - */ -#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) - -#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data - * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level - * can wake up the device just enough to perform DMA, then return to the reduced power mode. See - * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no - * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX - * FIFO has received 16 entries (has become full). - */ -#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ - -#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) -#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) - -#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) -#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) - -#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases - * to the level specified by TXLVL in the FIFOTRIG register. - */ -#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) - -#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level - * increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ - -#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) -#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) -/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) - -#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) -#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) -/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) - -#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) -/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) - -#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) -/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ - -#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. - */ -#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) - -#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. - */ -#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) - -#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO level interrupt. - */ -#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) - -#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO level interrupt. - */ -#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) - -#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) -#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) -/*! PERINT - Peripheral interrupt. - */ -#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ - -#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFOWR_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details. - */ -#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ - -#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) -#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. - */ -#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ - -#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORD_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. The number of bits used depends on configuration details. - */ -#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ - -#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48H_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. - */ -#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ - -#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. - */ -#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ - -#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. - */ -#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) -/*! @} */ - -/*! @name FIFOSIZE - FIFO size register */ -/*! @{ */ - -#define I2S_FIFOSIZE_FIFOSIZE_MASK (0x1FU) -#define I2S_FIFOSIZE_FIFOSIZE_SHIFT (0U) -/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - */ -#define I2S_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSIZE_FIFOSIZE_SHIFT)) & I2S_FIFOSIZE_FIFOSIZE_MASK) -/*! @} */ - -/*! @name ID - I2S Module identification */ -/*! @{ */ - -#define I2S_ID_MINOR_REV_MASK (0xF00U) -#define I2S_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation, starting at 0. - */ -#define I2S_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK) - -#define I2S_ID_MAJOR_REV_MASK (0xF000U) -#define I2S_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation, starting at 0. - */ -#define I2S_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK) - -#define I2S_ID_ID_MASK (0xFFFF0000U) -#define I2S_ID_ID_SHIFT (16U) -/*! ID - Unique module identifier for this IP block. - */ -#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2S_Register_Masks */ - - -/* I2S - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral I2S0 base address */ - #define I2S0_BASE (0x50086000u) - /** Peripheral I2S0 base address */ - #define I2S0_BASE_NS (0x40086000u) - /** Peripheral I2S0 base pointer */ - #define I2S0 ((I2S_Type *)I2S0_BASE) - /** Peripheral I2S0 base pointer */ - #define I2S0_NS ((I2S_Type *)I2S0_BASE_NS) - /** Peripheral I2S1 base address */ - #define I2S1_BASE (0x50087000u) - /** Peripheral I2S1 base address */ - #define I2S1_BASE_NS (0x40087000u) - /** Peripheral I2S1 base pointer */ - #define I2S1 ((I2S_Type *)I2S1_BASE) - /** Peripheral I2S1 base pointer */ - #define I2S1_NS ((I2S_Type *)I2S1_BASE_NS) - /** Peripheral I2S2 base address */ - #define I2S2_BASE (0x50088000u) - /** Peripheral I2S2 base address */ - #define I2S2_BASE_NS (0x40088000u) - /** Peripheral I2S2 base pointer */ - #define I2S2 ((I2S_Type *)I2S2_BASE) - /** Peripheral I2S2 base pointer */ - #define I2S2_NS ((I2S_Type *)I2S2_BASE_NS) - /** Peripheral I2S3 base address */ - #define I2S3_BASE (0x50089000u) - /** Peripheral I2S3 base address */ - #define I2S3_BASE_NS (0x40089000u) - /** Peripheral I2S3 base pointer */ - #define I2S3 ((I2S_Type *)I2S3_BASE) - /** Peripheral I2S3 base pointer */ - #define I2S3_NS ((I2S_Type *)I2S3_BASE_NS) - /** Peripheral I2S4 base address */ - #define I2S4_BASE (0x5008A000u) - /** Peripheral I2S4 base address */ - #define I2S4_BASE_NS (0x4008A000u) - /** Peripheral I2S4 base pointer */ - #define I2S4 ((I2S_Type *)I2S4_BASE) - /** Peripheral I2S4 base pointer */ - #define I2S4_NS ((I2S_Type *)I2S4_BASE_NS) - /** Peripheral I2S5 base address */ - #define I2S5_BASE (0x50096000u) - /** Peripheral I2S5 base address */ - #define I2S5_BASE_NS (0x40096000u) - /** Peripheral I2S5 base pointer */ - #define I2S5 ((I2S_Type *)I2S5_BASE) - /** Peripheral I2S5 base pointer */ - #define I2S5_NS ((I2S_Type *)I2S5_BASE_NS) - /** Peripheral I2S6 base address */ - #define I2S6_BASE (0x50097000u) - /** Peripheral I2S6 base address */ - #define I2S6_BASE_NS (0x40097000u) - /** Peripheral I2S6 base pointer */ - #define I2S6 ((I2S_Type *)I2S6_BASE) - /** Peripheral I2S6 base pointer */ - #define I2S6_NS ((I2S_Type *)I2S6_BASE_NS) - /** Peripheral I2S7 base address */ - #define I2S7_BASE (0x50098000u) - /** Peripheral I2S7 base address */ - #define I2S7_BASE_NS (0x40098000u) - /** Peripheral I2S7 base pointer */ - #define I2S7 ((I2S_Type *)I2S7_BASE) - /** Peripheral I2S7 base pointer */ - #define I2S7_NS ((I2S_Type *)I2S7_BASE_NS) - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS_NS { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS_NS { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS } -#else - /** Peripheral I2S0 base address */ - #define I2S0_BASE (0x40086000u) - /** Peripheral I2S0 base pointer */ - #define I2S0 ((I2S_Type *)I2S0_BASE) - /** Peripheral I2S1 base address */ - #define I2S1_BASE (0x40087000u) - /** Peripheral I2S1 base pointer */ - #define I2S1 ((I2S_Type *)I2S1_BASE) - /** Peripheral I2S2 base address */ - #define I2S2_BASE (0x40088000u) - /** Peripheral I2S2 base pointer */ - #define I2S2 ((I2S_Type *)I2S2_BASE) - /** Peripheral I2S3 base address */ - #define I2S3_BASE (0x40089000u) - /** Peripheral I2S3 base pointer */ - #define I2S3 ((I2S_Type *)I2S3_BASE) - /** Peripheral I2S4 base address */ - #define I2S4_BASE (0x4008A000u) - /** Peripheral I2S4 base pointer */ - #define I2S4 ((I2S_Type *)I2S4_BASE) - /** Peripheral I2S5 base address */ - #define I2S5_BASE (0x40096000u) - /** Peripheral I2S5 base pointer */ - #define I2S5 ((I2S_Type *)I2S5_BASE) - /** Peripheral I2S6 base address */ - #define I2S6_BASE (0x40097000u) - /** Peripheral I2S6 base pointer */ - #define I2S6 ((I2S_Type *)I2S6_BASE) - /** Peripheral I2S7 base address */ - #define I2S7_BASE (0x40098000u) - /** Peripheral I2S7 base pointer */ - #define I2S7 ((I2S_Type *)I2S7_BASE) - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } -#endif -/** Interrupt vectors for the I2S peripheral type */ -#define I2S_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2S_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer - * @{ - */ - -/** INPUTMUX - Register Layout Typedef */ -typedef struct { - __IO uint32_t SCT0_INMUX[7]; /**< Input mux register for SCT0 input, array offset: 0x0, array step: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t TIMER0CAPTSEL[4]; /**< Capture select registers for TIMER0 inputs, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[16]; - __IO uint32_t TIMER1CAPTSEL[4]; /**< Capture select registers for TIMER1 inputs, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_2[16]; - __IO uint32_t TIMER2CAPTSEL[4]; /**< Capture select registers for TIMER2 inputs, array offset: 0x60, array step: 0x4 */ - uint8_t RESERVED_3[80]; - __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ - __IO uint32_t DMA0_ITRIG_INMUX[23]; /**< Trigger select register for DMA0 channel, array offset: 0xE0, array step: 0x4 */ - uint8_t RESERVED_4[36]; - __IO uint32_t DMA0_OTRIG_INMUX[4]; /**< DMA0 output trigger selection to become DMA0 trigger, array offset: 0x160, array step: 0x4 */ - uint8_t RESERVED_5[16]; - __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ - __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ - uint8_t RESERVED_6[24]; - __IO uint32_t TIMER3CAPTSEL[4]; /**< Capture select registers for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */ - uint8_t RESERVED_7[16]; - __IO uint32_t TIMER4CAPTSEL[4]; /**< Capture select registers for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */ - uint8_t RESERVED_8[16]; - __IO uint32_t PINTSECSEL[2]; /**< Pin interrupt secure select register, array offset: 0x1E0, array step: 0x4 */ - uint8_t RESERVED_9[24]; - __IO uint32_t DMA1_ITRIG_INMUX[10]; /**< Trigger select register for DMA1 channel, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_10[24]; - __IO uint32_t DMA1_OTRIG_INMUX[4]; /**< DMA1 output trigger selection to become DMA1 trigger, array offset: 0x240, array step: 0x4 */ - uint8_t RESERVED_11[1264]; - __IO uint32_t DMA0_REQ_ENA; /**< Enable DMA0 requests, offset: 0x740 */ - uint8_t RESERVED_12[4]; - __O uint32_t DMA0_REQ_ENA_SET; /**< Set one or several bits in DMA0_REQ_ENA register, offset: 0x748 */ - uint8_t RESERVED_13[4]; - __O uint32_t DMA0_REQ_ENA_CLR; /**< Clear one or several bits in DMA0_REQ_ENA register, offset: 0x750 */ - uint8_t RESERVED_14[12]; - __IO uint32_t DMA1_REQ_ENA; /**< Enable DMA1 requests, offset: 0x760 */ - uint8_t RESERVED_15[4]; - __O uint32_t DMA1_REQ_ENA_SET; /**< Set one or several bits in DMA1_REQ_ENA register, offset: 0x768 */ - uint8_t RESERVED_16[4]; - __O uint32_t DMA1_REQ_ENA_CLR; /**< Clear one or several bits in DMA1_REQ_ENA register, offset: 0x770 */ - uint8_t RESERVED_17[12]; - __IO uint32_t DMA0_ITRIG_ENA; /**< Enable DMA0 triggers, offset: 0x780 */ - uint8_t RESERVED_18[4]; - __O uint32_t DMA0_ITRIG_ENA_SET; /**< Set one or several bits in DMA0_ITRIG_ENA register, offset: 0x788 */ - uint8_t RESERVED_19[4]; - __O uint32_t DMA0_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA0_ITRIG_ENA register, offset: 0x790 */ - uint8_t RESERVED_20[12]; - __IO uint32_t DMA1_ITRIG_ENA; /**< Enable DMA1 triggers, offset: 0x7A0 */ - uint8_t RESERVED_21[4]; - __O uint32_t DMA1_ITRIG_ENA_SET; /**< Set one or several bits in DMA1_ITRIG_ENA register, offset: 0x7A8 */ - uint8_t RESERVED_22[4]; - __O uint32_t DMA1_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA1_ITRIG_ENA register, offset: 0x7B0 */ -} INPUTMUX_Type; - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks - * @{ - */ - -/*! @name SCT0_INMUX - Input mux register for SCT0 input */ -/*! @{ */ - -#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU) -#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) -/*! INP_N - Input number to SCT0 inputs 0 to 6.. - * 0b00000..SCT_GPI0 function selected from IOCON register - * 0b00001..SCT_GPI1 function selected from IOCON register - * 0b00010..SCT_GPI2 function selected from IOCON register - * 0b00011..SCT_GPI3 function selected from IOCON register - * 0b00100..SCT_GPI4 function selected from IOCON register - * 0b00101..SCT_GPI5 function selected from IOCON register - * 0b00110..SCT_GPI6 function selected from IOCON register - * 0b00111..SCT_GPI7 function selected from IOCON register - * 0b01000..T0_OUT0 ctimer 0 match[0] output - * 0b01001..T1_OUT0 ctimer 1 match[0] output - * 0b01010..T2_OUT0 ctimer 2 match[0] output - * 0b01011..T3_OUT0 ctimer 3 match[0] output - * 0b01100..T4_OUT0 ctimer 4 match[0] output - * 0b01101..ADC_IRQ interrupt request from ADC - * 0b01110..GPIOINT_BMATCH - * 0b01111..None - * 0b10000..None - * 0b10001..COMP_OUTPUT output from analog comparator - * 0b10010..I2S_SHARED_SCK[0] output from I2S pin sharing - * 0b10011..I2S_SHARED_SCK[1] output from I2S pin sharing - * 0b10100..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b10101..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b10110..ARM_TXEV interrupt event from cpu0 or cpu1 - * 0b10111..DEBUG_HALTED from cpu0 or cpu1 - * 0b11000-0b11111..None - */ -#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK) -/*! @} */ - -/* The count of INPUTMUX_SCT0_INMUX */ -#define INPUTMUX_SCT0_INMUX_COUNT (7U) - -/*! @name TIMER0CAPTSEL - Capture select registers for TIMER0 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..None - * 0b10010..None - * 0b10011..None - * 0b10100..None - * 0b10101..None - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER0CAPTSEL */ -#define INPUTMUX_TIMER0CAPTSEL_COUNT (4U) - -/*! @name TIMER1CAPTSEL - Capture select registers for TIMER1 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..None - * 0b10010..None - * 0b10011..None - * 0b10100..None - * 0b10101..None - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER1CAPTSEL */ -#define INPUTMUX_TIMER1CAPTSEL_COUNT (4U) - -/*! @name TIMER2CAPTSEL - Capture select registers for TIMER2 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..None - * 0b10010..None - * 0b10011..None - * 0b10100..None - * 0b10101..None - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER2CAPTSEL */ -#define INPUTMUX_TIMER2CAPTSEL_COUNT (4U) - -/*! @name PINTSEL - Pin interrupt select register */ -/*! @{ */ - -#define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU) -#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) -/*! INTPIN - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = - * (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. - */ -#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PINTSEL */ -#define INPUTMUX_PINTSEL_COUNT (8U) - -/*! @name DMA0_ITRIG_INMUX - Trigger select register for DMA0 channel */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U) -/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22). - * 0b00000..Pin interrupt 0 - * 0b00001..Pin interrupt 1 - * 0b00010..Pin interrupt 2 - * 0b00011..Pin interrupt 3 - * 0b00100..Timer CTIMER0 Match 0 - * 0b00101..Timer CTIMER0 Match 1 - * 0b00110..Timer CTIMER1 Match 0 - * 0b00111..Timer CTIMER1 Match 1 - * 0b01000..Timer CTIMER2 Match 0 - * 0b01001..Timer CTIMER2 Match 1 - * 0b01010..Timer CTIMER3 Match 0 - * 0b01011..Timer CTIMER3 Match 1 - * 0b01100..Timer CTIMER4 Match 0 - * 0b01101..Timer CTIMER4 Match 1 - * 0b01110..COMP_OUTPUT - * 0b01111..DMA0 output trigger mux 0 - * 0b10000..DMA0 output trigger mux 1 - * 0b10001..DMA0 output trigger mux 1 - * 0b10010..DMA0 output trigger mux 3 - * 0b10011..SCT0 DMA request 0 - * 0b10100..SCT0 DMA request 1 - * 0b10101..HASH DMA RX trigger - * 0b10110-0b11111..None - */ -#define INPUTMUX_DMA0_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA0_ITRIG_INMUX */ -#define INPUTMUX_DMA0_ITRIG_INMUX_COUNT (23U) - -/*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection to become DMA0 trigger */ -/*! @{ */ - -#define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U) -/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22). - */ -#define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA0_OTRIG_INMUX */ -#define INPUTMUX_DMA0_OTRIG_INMUX_COUNT (4U) - -/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ -/*! @{ */ - -#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) -/*! CLKIN - Clock source number (decimal value) for frequency measure function reference clock: - * 0b00000..External main crystal oscilator (Clock_in). - * 0b00001..FRO 12MHz clock. - * 0b00010..FRO 96MHz clock. - * 0b00011..Watchdog oscillator / FRO1MHz clock. - * 0b00100..32 kHz oscillator (32k_clk) clock. - * 0b00101..main clock (main_clock). - * 0b00110..FREQME_GPIO_CLK_A. - * 0b00111..FREQME_GPIO_CLK_B. - */ -#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) -/*! @} */ - -/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ -/*! @{ */ - -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) -/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: - * 0b00000..External main crystal oscilator (Clock_in). - * 0b00001..FRO 12MHz clock. - * 0b00010..FRO 96MHz clock. - * 0b00011..Watchdog oscillator / FRO1MHz clock. - * 0b00100..32 kHz oscillator (32k_clk) clock. - * 0b00101..main clock (main_clock). - * 0b00110..FREQME_GPIO_CLK_A. - * 0b00111..FREQME_GPIO_CLK_B. - */ -#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) -/*! @} */ - -/*! @name TIMER3CAPTSEL - Capture select registers for TIMER3 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..None - * 0b10010..None - * 0b10011..None - * 0b10100..None - * 0b10101..None - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER3CAPTSEL */ -#define INPUTMUX_TIMER3CAPTSEL_COUNT (4U) - -/*! @name TIMER4CAPTSEL - Capture select registers for TIMER4 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..None - * 0b10010..None - * 0b10011..None - * 0b10100..None - * 0b10101..None - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER4CAPTSEL */ -#define INPUTMUX_TIMER4CAPTSEL_COUNT (4U) - -/*! @name PINTSECSEL - Pin interrupt secure select register */ -/*! @{ */ - -#define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU) -#define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U) -/*! INTPIN - Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: - * INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31. - */ -#define INPUTMUX_PINTSECSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PINTSECSEL */ -#define INPUTMUX_PINTSECSEL_COUNT (2U) - -/*! @name DMA1_ITRIG_INMUX - Trigger select register for DMA1 channel */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0xFU) -#define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U) -/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9). - * 0b0000..Pin interrupt 0 - * 0b0001..Pin interrupt 1 - * 0b0010..Pin interrupt 2 - * 0b0011..Pin interrupt 3 - * 0b0100..Timer CTIMER0 Match 0 - * 0b0101..Timer CTIMER0 Match 1 - * 0b0110..Timer CTIMER2 Match 0 - * 0b0111..Timer CTIMER4 Match 0 - * 0b1000..DMA1 output trigger mux 0 - * 0b1001..DMA1 output trigger mux 1 - * 0b1010..DMA1 output trigger mux 2 - * 0b1011..DMA1 output trigger mux 3 - * 0b1100..SCT0 DMA request 0 - * 0b1101..SCT0 DMA request 1 - * 0b1110..HASH DMA RX trigger - * 0b1111..None - */ -#define INPUTMUX_DMA1_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA1_ITRIG_INMUX */ -#define INPUTMUX_DMA1_ITRIG_INMUX_COUNT (10U) - -/*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection to become DMA1 trigger */ -/*! @{ */ - -#define INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK (0xFU) -#define INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT (0U) -/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9). - */ -#define INPUTMUX_DMA1_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA1_OTRIG_INMUX */ -#define INPUTMUX_DMA1_OTRIG_INMUX_COUNT (4U) - -/*! @name DMA0_REQ_ENA - Enable DMA0 requests */ -/*! @{ */ - -#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK (0x7FFFFFU) -#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT (0U) -/*! REQ_ENA - Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - * 0b00000000000000000000000..Hash-Crypt DMA request. - * 0b00000000000000000000010..High Speed SPI (Flexcomm 8) RX. - * 0b00000000000000000000011..High Speed SPI (Flexcomm 8) TX. - * 0b00000000000000000000100..Flexcomm Interface 0 RX / I2C Slave. - * 0b00000000000000000000101..Flexcomm Interface 0 TX / I2C Master. - * 0b00000000000000000000110..Flexcomm Interface 1 RX / I2C Slave. - * 0b00000000000000000000111..Flexcomm Interface 1 TX / I2C Master. - * 0b00000000000000000001000..Flexcomm Interface 3 RX / I2C Slave. - * 0b00000000000000000001001..Flexcomm Interface 3 TX / I2C Master. - * 0b00000000000000000001010..Flexcomm Interface 2 RX / I2C Slave. - * 0b00000000000000000001011..Flexcomm Interface 2 TX / I2C Master. - * 0b00000000000000000001100..Flexcomm Interface 4 RX / I2C Slave. - * 0b00000000000000000001101..Flexcomm Interface 4 TX / I2C Master. - * 0b00000000000000000001110..Flexcomm Interface 5 RX / I2C Slave. - * 0b00000000000000000001111..Flexcomm Interface 5 TX / I2C Master. - * 0b00000000000000000010000..Flexcomm Interface 6 RX / I2C Slave. - * 0b00000000000000000010001..Flexcomm Interface 6 TX / I2C Master. - * 0b00000000000000000010010..Flexcomm Interface 7 RX / I2C Slave. - * 0b00000000000000000010011..Flexcomm Interface 6 TX / I2C Master. - * 0b00000000000000000010101..ADC0 FIFO 0. - * 0b00000000000000000010110..ADC0 FIFO 1. - */ -#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK) -/*! @} */ - -/*! @name DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK (0x7FFFFFU) -#define INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT (0U) -/*! SET - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register - */ -#define INPUTMUX_DMA0_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK (0x7FFFFFU) -#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT (0U) -/*! CLR - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register - */ -#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK) -/*! @} */ - -/*! @name DMA1_REQ_ENA - Enable DMA1 requests */ -/*! @{ */ - -#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK (0x3FFU) -#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT (0U) -/*! REQ_ENA - Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - * 0b0000000000..Hash-Crypt input DMA request. - * 0b0000000010..High Speed SPI (Flexcomm 8) RX. - * 0b0000000011..High Speed SPI (Flexcomm 8) TX. - * 0b0000000100..Flexcomm Interface 0 RX /I2C Slave. - * 0b0000000101..Flexcomm Interface 0 TX / I2C Master. - * 0b0000000110..Flexcomm Interface 1 RX /I2C Slave. - * 0b0000000111..Flexcomm Interface 1 TX / I2C Master. - * 0b0000001000..Flexcomm Interface 3 RX / I2C Slave. - * 0b0000001001..Flexcomm Interface 3 TX / I2C Master. - */ -#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK) -/*! @} */ - -/*! @name DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK (0x3FFU) -#define INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT (0U) -/*! SET - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register - */ -#define INPUTMUX_DMA1_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK (0x3FFU) -#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT (0U) -/*! CLR - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register - */ -#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_ENA - Enable DMA0 triggers */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK (0x3FFFFFU) -#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) -/*! ITRIG_ENA - Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK (0x3FFFFFU) -#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT (0U) -/*! SET - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIG_ENA register - */ -#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK (0x3FFFFFU) -#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT (0U) -/*! CLR - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIG_ENA register - */ -#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK) -/*! @} */ - -/*! @name DMA1_ITRIG_ENA - Enable DMA1 triggers */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK (0x7FFFU) -#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) -/*! ITRIG_ENA - Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK) -/*! @} */ - -/*! @name DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK (0x7FFFU) -#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT (0U) -/*! SET - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no - * change in DMA1_ITRIG_ENA register - */ -#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK (0x7FFFU) -#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT (0U) -/*! CLR - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no - * change in DMA1_ITRIG_ENA register - */ -#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group INPUTMUX_Register_Masks */ - - -/* INPUTMUX - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE (0x50006000u) - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE_NS (0x40006000u) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS) - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS { INPUTMUX } - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX_BASE_NS } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS_NS { INPUTMUX_NS } -#else - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE (0x40006000u) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS { INPUTMUX } -#endif - -/*! - * @} - */ /* end of group INPUTMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- IOCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer - * @{ - */ - -/** IOCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ -} IOCON_Type; - -/* ---------------------------------------------------------------------------- - -- IOCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Register_Masks IOCON Register Masks - * @{ - */ - -/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ -/*! @{ */ - -#define IOCON_PIO_FUNC_MASK (0xFU) -#define IOCON_PIO_FUNC_SHIFT (0U) -/*! FUNC - Selects pin function. - * 0b0000..Alternative connection 0. - * 0b0001..Alternative connection 1. - * 0b0010..Alternative connection 2. - * 0b0011..Alternative connection 3. - * 0b0100..Alternative connection 4. - * 0b0101..Alternative connection 5. - * 0b0110..Alternative connection 6. - * 0b0111..Alternative connection 7. - */ -#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) - -#define IOCON_PIO_MODE_MASK (0x30U) -#define IOCON_PIO_MODE_SHIFT (4U) -/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) - -#define IOCON_PIO_SLEW_MASK (0x40U) -#define IOCON_PIO_SLEW_SHIFT (6U) -/*! SLEW - Driver slew rate. - * 0b0..Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - * 0b1..Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - */ -#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) - -#define IOCON_PIO_INVERT_MASK (0x80U) -#define IOCON_PIO_INVERT_SHIFT (7U) -/*! INVERT - Input polarity. - * 0b0..Disabled. Input function is not inverted. - * 0b1..Enabled. Input is function inverted. - */ -#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) - -#define IOCON_PIO_DIGIMODE_MASK (0x100U) -#define IOCON_PIO_DIGIMODE_SHIFT (8U) -/*! DIGIMODE - Select Digital mode. - * 0b0..Disable digital mode. Digital input set to 0. - * 0b1..Enable Digital mode. Digital input is enabled. - */ -#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) - -#define IOCON_PIO_OD_MASK (0x200U) -#define IOCON_PIO_OD_SHIFT (9U) -/*! OD - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). - * 0b0..Normal. Normal push-pull output - * 0b1..Open-drain. Simulated open-drain output (high drive disabled). - */ -#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) - -#define IOCON_PIO_ASW_MASK (0x400U) -#define IOCON_PIO_ASW_SHIFT (10U) -/*! ASW - Analog switch input control. - * 0b0..Analog switch is open. (disable) - * 0b1..Analog switch is closed. (enable) - */ -#define IOCON_PIO_ASW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW_SHIFT)) & IOCON_PIO_ASW_MASK) - -#define IOCON_PIO_SSEL_MASK (0x800U) -#define IOCON_PIO_SSEL_SHIFT (11U) -/*! SSEL - Supply Selection bit. - * 0b0..3V3 Signaling in I2C Mode. - * 0b1..1V8 Signaling in I2C Mode. - */ -#define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK) - -#define IOCON_PIO_FILTEROFF_MASK (0x1000U) -#define IOCON_PIO_FILTEROFF_SHIFT (12U) -/*! FILTEROFF - Controls input glitch filter. - * 0b0..Filter enabled. - * 0b1..Filter disabled. - */ -#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) - -#define IOCON_PIO_ECS_MASK (0x2000U) -#define IOCON_PIO_ECS_SHIFT (13U) -/*! ECS - Pull-up current source enable in I2C mode. - * 0b1..Enabled. Pull resistor is conencted. - * 0b0..Disabled. IO is in open drain cell. - */ -#define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK) - -#define IOCON_PIO_EGP_MASK (0x4000U) -#define IOCON_PIO_EGP_SHIFT (14U) -/*! EGP - Switch between GPIO mode and I2C mode. - * 0b0..I2C mode. - * 0b1..GPIO mode. - */ -#define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK) - -#define IOCON_PIO_I2CFILTER_MASK (0x8000U) -#define IOCON_PIO_I2CFILTER_SHIFT (15U) -/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. - * 0b0..I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. - * 0b1..I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. - */ -#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) -/*! @} */ - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT (2U) - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT2 (32U) - - -/*! - * @} - */ /* end of group IOCON_Register_Masks */ - - -/* IOCON - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral IOCON base address */ - #define IOCON_BASE (0x50001000u) - /** Peripheral IOCON base address */ - #define IOCON_BASE_NS (0x40001000u) - /** Peripheral IOCON base pointer */ - #define IOCON ((IOCON_Type *)IOCON_BASE) - /** Peripheral IOCON base pointer */ - #define IOCON_NS ((IOCON_Type *)IOCON_BASE_NS) - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS { IOCON_BASE } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS { IOCON } - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS_NS { IOCON_BASE_NS } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS_NS { IOCON_NS } -#else - /** Peripheral IOCON base address */ - #define IOCON_BASE (0x40001000u) - /** Peripheral IOCON base pointer */ - #define IOCON ((IOCON_Type *)IOCON_BASE) - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS { IOCON_BASE } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS { IOCON } -#endif - -/*! - * @} - */ /* end of group IOCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MRT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer - * @{ - */ - -/** MRT - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x10 */ - __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ - __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ - __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ - __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ - } CHANNEL[4]; - uint8_t RESERVED_0[176]; - __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ - __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ - __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ -} MRT_Type; - -/* ---------------------------------------------------------------------------- - -- MRT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Register_Masks MRT Register Masks - * @{ - */ - -/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ -/*! @{ */ - -#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) -/*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT - * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to - * this bit field starts the timer immediately. If the timer is running, writing a zero to this - * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer - * stops at the end of the time interval. - */ -#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) - -#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) -#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) -/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. - * This bit is write-only. Reading this bit always returns 0. - * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the - * time interval if the repeat mode is selected. - * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. - */ -#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_INTVAL */ -#define MRT_CHANNEL_INTVAL_COUNT (4U) - -/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ -/*! @{ */ - -#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) -/*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn - * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval - * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn - * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields - * returns -1 (0x00FF FFFF). - */ -#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_TIMER */ -#define MRT_CHANNEL_TIMER_COUNT (4U) - -/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ -/*! @{ */ - -#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) -#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) -/*! INTEN - Enable the TIMERn interrupt. - * 0b0..Disabled. TIMERn interrupt is disabled. - * 0b1..Enabled. TIMERn interrupt is enabled. - */ -#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) - -#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) -#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) -/*! MODE - Selects timer mode. - * 0b00..Repeat interrupt mode. - * 0b01..One-shot interrupt mode. - * 0b10..One-shot stall mode. - * 0b11..Reserved. - */ -#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_CTRL */ -#define MRT_CHANNEL_CTRL_COUNT (4U) - -/*! @name CHANNEL_STAT - MRT Status register. */ -/*! @{ */ - -#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) -#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) -/*! INTFLAG - Monitors the interrupt flag. - * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. - * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If - * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt - * are raised. Writing a 1 to this bit clears the interrupt request. - */ -#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) - -#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) -#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) -/*! RUN - Indicates the state of TIMERn. This bit is read-only. - * 0b0..Idle state. TIMERn is stopped. - * 0b1..Running. TIMERn is running. - */ -#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) - -#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) -#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) -/*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG - * register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating - * modes. - * 0b0..This channel is not in use. - * 0b1..This channel is in use. - */ -#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_STAT */ -#define MRT_CHANNEL_STAT_COUNT (4U) - -/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ -/*! @{ */ - -#define MRT_MODCFG_NOC_MASK (0xFU) -#define MRT_MODCFG_NOC_SHIFT (0U) -/*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.) - */ -#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) - -#define MRT_MODCFG_NOB_MASK (0x1F0U) -#define MRT_MODCFG_NOB_SHIFT (4U) -/*! NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.) - */ -#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) - -#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) -#define MRT_MODCFG_MULTITASK_SHIFT (31U) -/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. - * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. - * 0b1..Multi-task mode. - */ -#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) -/*! @} */ - -/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ -/*! @{ */ - -#define MRT_IDLE_CH_CHAN_MASK (0xF0U) -#define MRT_IDLE_CH_CHAN_SHIFT (4U) -/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is - * positioned such that it can be used as an offset from the MRT base address in order to access - * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See - * text above for more details. - */ -#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) -/*! @} */ - -/*! @name IRQ_FLAG - Global interrupt flag register */ -/*! @{ */ - -#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) -#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) -/*! GFLAG0 - Monitors the interrupt flag of TIMER0. - * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. - * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If - * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global - * interrupt are raised. Writing a 1 to this bit clears the interrupt request. - */ -#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) - -#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) -#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) -/*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0. - */ -#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) - -#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) -#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) -/*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0. - */ -#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) - -#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) -#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) -/*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0. - */ -#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MRT_Register_Masks */ - - -/* MRT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral MRT0 base address */ - #define MRT0_BASE (0x5000D000u) - /** Peripheral MRT0 base address */ - #define MRT0_BASE_NS (0x4000D000u) - /** Peripheral MRT0 base pointer */ - #define MRT0 ((MRT_Type *)MRT0_BASE) - /** Peripheral MRT0 base pointer */ - #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS { MRT0_BASE } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS { MRT0 } - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS_NS { MRT0_NS } -#else - /** Peripheral MRT0 base address */ - #define MRT0_BASE (0x4000D000u) - /** Peripheral MRT0 base pointer */ - #define MRT0 ((MRT_Type *)MRT0_BASE) - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS { MRT0_BASE } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS { MRT0 } -#endif -/** Interrupt vectors for the MRT peripheral type */ -#define MRT_IRQS { MRT0_IRQn } - -/*! - * @} - */ /* end of group MRT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- OSTIMER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer - * @{ - */ - -/** OSTIMER - Register Layout Typedef */ -typedef struct { - __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */ - __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */ - __I uint32_t CAPTURE_L; /**< Capture Low Register, offset: 0x8 */ - __I uint32_t CAPTURE_H; /**< Capture High Register, offset: 0xC */ - __IO uint32_t MATCH_L; /**< Match Low Register, offset: 0x10 */ - __IO uint32_t MATCH_H; /**< Match High Register, offset: 0x14 */ - uint8_t RESERVED_0[4]; - __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register, offset: 0x1C */ -} OSTIMER_Type; - -/* ---------------------------------------------------------------------------- - -- OSTIMER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks - * @{ - */ - -/*! @name EVTIMERL - EVTIMER Low Register */ -/*! @{ */ - -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) -/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the lower 32 bits of the 42-bits - * EVTIMER. Note there is only one EVTIMER, readable from all domains. - */ -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) -/*! @} */ - -/*! @name EVTIMERH - EVTIMER High Register */ -/*! @{ */ - -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU) -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) -/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the upper 10 bits of the 42-bits - * EVTIMER. Note there is only one EVTIMER, readable from all domains. - */ -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) -/*! @} */ - -/*! @name CAPTURE_L - Capture Low Register */ -/*! @{ */ - -#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U) -/*! CAPTURE_VALUE - A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at - * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). - */ -#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK) -/*! @} */ - -/*! @name CAPTURE_H - Capture High Register */ -/*! @{ */ - -#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0x3FFU) -#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U) -/*! CAPTURE_VALUE - A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at - * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). - */ -#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK) -/*! @} */ - -/*! @name MATCH_L - Match Low Register */ -/*! @{ */ - -#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U) -/*! MATCH_VALUE - The value written to the MATCH (L/H) register pair is compared against the central - * EVTIMER. When a match occurs, an interrupt request is generated if enabled. - */ -#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK) -/*! @} */ - -/*! @name MATCH_H - Match High Register */ -/*! @{ */ - -#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0x3FFU) -#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U) -/*! MATCH_VALUE - The value written (upper 10 bits) to the MATCH (L/H) register pair is compared - * against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. - */ -#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK) -/*! @} */ - -/*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register */ -/*! @{ */ - -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) -/*! OSTIMER_INTRFLAG - This bit is set when a match occurs between the central 42-bits EVTIMER and - * the value programmed in the match-register pair. This bit is cleared by writing a '1'. Writes - * to clear this bit are asynchronous. It should be done before a new match value is written into - * the MATCH_L/H registers. - */ -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) - -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) -/*! OSTIMER_INTENA - When this bit is '1' an interrupt/wakeup request to the domain processor will - * be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests - * due to the OSTIMER_INTR flag are blocked. - */ -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) - -#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U) -#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U) -/*! MATCH_WR_RDY - This bit will be low when it is safe to write to reload the Match Registers. In - * typical applications it should not be necessary to test this bit. [1] - */ -#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group OSTIMER_Register_Masks */ - - -/* OSTIMER - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral OSTIMER base address */ - #define OSTIMER_BASE (0x5002D000u) - /** Peripheral OSTIMER base address */ - #define OSTIMER_BASE_NS (0x4002D000u) - /** Peripheral OSTIMER base pointer */ - #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) - /** Peripheral OSTIMER base pointer */ - #define OSTIMER_NS ((OSTIMER_Type *)OSTIMER_BASE_NS) - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS { OSTIMER } - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS_NS { OSTIMER_BASE_NS } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS_NS { OSTIMER_NS } -#else - /** Peripheral OSTIMER base address */ - #define OSTIMER_BASE (0x4002D000u) - /** Peripheral OSTIMER base pointer */ - #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS { OSTIMER } -#endif -/** Interrupt vectors for the OSTIMER peripheral type */ -#define OSTIMER_IRQS { OS_EVENT_IRQn } - -/*! - * @} - */ /* end of group OSTIMER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer - * @{ - */ - -/** PINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ - __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ - __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ - __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ - __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ - __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ - __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ - __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ - __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ - __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ - __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ - __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ - __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ -} PINT_Type; - -/* ---------------------------------------------------------------------------- - -- PINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Register_Masks PINT Register Masks - * @{ - */ - -/*! @name ISEL - Pin Interrupt Mode register */ -/*! @{ */ - -#define PINT_ISEL_PMODE_MASK (0xFFU) -#define PINT_ISEL_PMODE_SHIFT (0U) -/*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt - * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive - */ -#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) -/*! @} */ - -/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ -/*! @{ */ - -#define PINT_IENR_ENRL_MASK (0xFFU) -#define PINT_IENR_ENRL_SHIFT (0U) -/*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the - * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable - * rising edge or level interrupt. - */ -#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) -/*! @} */ - -/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ -/*! @{ */ - -#define PINT_SIENR_SETENRL_MASK (0xFFU) -#define PINT_SIENR_SETENRL_SHIFT (0U) -/*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n - * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. - */ -#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) -/*! @} */ - -/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ -/*! @{ */ - -#define PINT_CIENR_CENRL_MASK (0xFFU) -#define PINT_CIENR_CENRL_SHIFT (0U) -/*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit - * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level - * interrupt. - */ -#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) -/*! @} */ - -/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ -/*! @{ */ - -#define PINT_IENF_ENAF_MASK (0xFFU) -#define PINT_IENF_ENAF_SHIFT (0U) -/*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt. - * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt - * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active - * interrupt level HIGH. - */ -#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) -/*! @} */ - -/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ -/*! @{ */ - -#define PINT_SIENF_SETENAF_MASK (0xFFU) -#define PINT_SIENF_SETENAF_SHIFT (0U) -/*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n - * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable - * falling edge interrupt. - */ -#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) -/*! @} */ - -/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ -/*! @{ */ - -#define PINT_CIENF_CENAF_MASK (0xFFU) -#define PINT_CIENF_CENAF_SHIFT (0U) -/*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n - * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or - * falling edge interrupt disabled. - */ -#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) -/*! @} */ - -/*! @name RISE - Pin interrupt rising edge register */ -/*! @{ */ - -#define PINT_RISE_RDET_MASK (0xFFU) -#define PINT_RISE_RDET_SHIFT (0U) -/*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read - * 0: No rising edge has been detected on this pin since Reset or the last time a one was written - * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the - * last time a one was written to this bit. Write 1: clear rising edge detection for this pin. - */ -#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) -/*! @} */ - -/*! @name FALL - Pin interrupt falling edge register */ -/*! @{ */ - -#define PINT_FALL_FDET_MASK (0xFFU) -#define PINT_FALL_FDET_SHIFT (0U) -/*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read - * 0: No falling edge has been detected on this pin since Reset or the last time a one was - * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or - * the last time a one was written to this bit. Write 1: clear falling edge detection for this - * pin. - */ -#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) -/*! @} */ - -/*! @name IST - Pin interrupt status register */ -/*! @{ */ - -#define PINT_IST_PSTAT_MASK (0xFFU) -#define PINT_IST_PSTAT_SHIFT (0U) -/*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts - * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for - * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this - * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. - * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). - */ -#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) -/*! @} */ - -/*! @name PMCTRL - Pattern match interrupt control register */ -/*! @{ */ - -#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) -#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) -/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. - * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. - * 0b1..Pattern match. Interrupts are driven in response to pattern matches. - */ -#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) - -#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) -#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) -/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. - * 0b0..Disabled. RXEV output to the CPU is disabled. - * 0b1..Enabled. RXEV output to the CPU is enabled. - */ -#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) - -#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) -#define PINT_PMCTRL_PMAT_SHIFT (24U) -/*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field - * indicates that the corresponding product term is matched by the current state of the appropriate - * inputs. - */ -#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) -/*! @} */ - -/*! @name PMSRC - Pattern match interrupt bit-slice source register */ -/*! @{ */ - -#define PINT_PMSRC_SRC0_MASK (0x700U) -#define PINT_PMSRC_SRC0_SHIFT (8U) -/*! SRC0 - Selects the input source for bit slice 0 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. - */ -#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) - -#define PINT_PMSRC_SRC1_MASK (0x3800U) -#define PINT_PMSRC_SRC1_SHIFT (11U) -/*! SRC1 - Selects the input source for bit slice 1 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. - */ -#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) - -#define PINT_PMSRC_SRC2_MASK (0x1C000U) -#define PINT_PMSRC_SRC2_SHIFT (14U) -/*! SRC2 - Selects the input source for bit slice 2 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. - */ -#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) - -#define PINT_PMSRC_SRC3_MASK (0xE0000U) -#define PINT_PMSRC_SRC3_SHIFT (17U) -/*! SRC3 - Selects the input source for bit slice 3 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. - */ -#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) - -#define PINT_PMSRC_SRC4_MASK (0x700000U) -#define PINT_PMSRC_SRC4_SHIFT (20U) -/*! SRC4 - Selects the input source for bit slice 4 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. - */ -#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) - -#define PINT_PMSRC_SRC5_MASK (0x3800000U) -#define PINT_PMSRC_SRC5_SHIFT (23U) -/*! SRC5 - Selects the input source for bit slice 5 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. - */ -#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) - -#define PINT_PMSRC_SRC6_MASK (0x1C000000U) -#define PINT_PMSRC_SRC6_SHIFT (26U) -/*! SRC6 - Selects the input source for bit slice 6 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. - */ -#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) - -#define PINT_PMSRC_SRC7_MASK (0xE0000000U) -#define PINT_PMSRC_SRC7_SHIFT (29U) -/*! SRC7 - Selects the input source for bit slice 7 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. - */ -#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) -/*! @} */ - -/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ -/*! @{ */ - -#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) -#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) -/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. - * 0b0..No effect. Slice 0 is not an endpoint. - * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) - -#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) -#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) -/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. - * 0b0..No effect. Slice 1 is not an endpoint. - * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) - -#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) -#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) -/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. - * 0b0..No effect. Slice 2 is not an endpoint. - * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) - -#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) -#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) -/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. - * 0b0..No effect. Slice 3 is not an endpoint. - * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) - -#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) -#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) -/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. - * 0b0..No effect. Slice 4 is not an endpoint. - * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) - -#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) -#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) -/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. - * 0b0..No effect. Slice 5 is not an endpoint. - * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) - -#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) -#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) -/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. - * 0b0..No effect. Slice 6 is not an endpoint. - * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) - -#define PINT_PMCFG_CFG0_MASK (0x700U) -#define PINT_PMCFG_CFG0_SHIFT (8U) -/*! CFG0 - Specifies the match contribution condition for bit slice 0. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) - -#define PINT_PMCFG_CFG1_MASK (0x3800U) -#define PINT_PMCFG_CFG1_SHIFT (11U) -/*! CFG1 - Specifies the match contribution condition for bit slice 1. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) - -#define PINT_PMCFG_CFG2_MASK (0x1C000U) -#define PINT_PMCFG_CFG2_SHIFT (14U) -/*! CFG2 - Specifies the match contribution condition for bit slice 2. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) - -#define PINT_PMCFG_CFG3_MASK (0xE0000U) -#define PINT_PMCFG_CFG3_SHIFT (17U) -/*! CFG3 - Specifies the match contribution condition for bit slice 3. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) - -#define PINT_PMCFG_CFG4_MASK (0x700000U) -#define PINT_PMCFG_CFG4_SHIFT (20U) -/*! CFG4 - Specifies the match contribution condition for bit slice 4. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) - -#define PINT_PMCFG_CFG5_MASK (0x3800000U) -#define PINT_PMCFG_CFG5_SHIFT (23U) -/*! CFG5 - Specifies the match contribution condition for bit slice 5. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) - -#define PINT_PMCFG_CFG6_MASK (0x1C000000U) -#define PINT_PMCFG_CFG6_SHIFT (26U) -/*! CFG6 - Specifies the match contribution condition for bit slice 6. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) - -#define PINT_PMCFG_CFG7_MASK (0xE0000000U) -#define PINT_PMCFG_CFG7_SHIFT (29U) -/*! CFG7 - Specifies the match contribution condition for bit slice 7. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PINT_Register_Masks */ - - -/* PINT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PINT base address */ - #define PINT_BASE (0x50004000u) - /** Peripheral PINT base address */ - #define PINT_BASE_NS (0x40004000u) - /** Peripheral PINT base pointer */ - #define PINT ((PINT_Type *)PINT_BASE) - /** Peripheral PINT base pointer */ - #define PINT_NS ((PINT_Type *)PINT_BASE_NS) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE (0x50005000u) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE_NS (0x40005000u) - /** Peripheral SECPINT base pointer */ - #define SECPINT ((PINT_Type *)SECPINT_BASE) - /** Peripheral SECPINT base pointer */ - #define SECPINT_NS ((PINT_Type *)SECPINT_BASE_NS) - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS { PINT, SECPINT } - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS_NS { PINT_BASE_NS, SECPINT_BASE_NS } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS_NS { PINT_NS, SECPINT_NS } -#else - /** Peripheral PINT base address */ - #define PINT_BASE (0x40004000u) - /** Peripheral PINT base pointer */ - #define PINT ((PINT_Type *)PINT_BASE) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE (0x40005000u) - /** Peripheral SECPINT base pointer */ - #define SECPINT ((PINT_Type *)SECPINT_BASE) - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS { PINT, SECPINT } -#endif -/** Interrupt vectors for the PINT peripheral type */ -#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn } - -/*! - * @} - */ /* end of group PINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PLU Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PLU_Peripheral_Access_Layer PLU Peripheral Access Layer - * @{ - */ - -/** PLU - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x20 */ - __IO uint32_t INP_MUX[5]; /**< LUTn input x MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */ - uint8_t RESERVED_0[12]; - } LUT[26]; - uint8_t RESERVED_0[1216]; - __IO uint32_t LUT_TRUTH[26]; /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25, array offset: 0x800, array step: 0x4 */ - uint8_t RESERVED_1[152]; - __I uint32_t OUTPUTS; /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */ - __IO uint32_t WAKEINT_CTRL; /**< Wakeup interrupt control for PLU, offset: 0x904 */ - uint8_t RESERVED_2[760]; - __IO uint32_t OUTPUT_MUX[8]; /**< Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */ -} PLU_Type; - -/* ---------------------------------------------------------------------------- - -- PLU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PLU_Register_Masks PLU Register Masks - * @{ - */ - -/*! @name LUT_INP_MUX - LUTn input x MUX */ -/*! @{ */ - -#define PLU_LUT_INP_MUX_LUTn_INPx_MASK (0x3FU) -#define PLU_LUT_INP_MUX_LUTn_INPx_SHIFT (0U) -/*! LUTn_INPx - Selects the input source to be connected to LUT25 input4. For each LUT, the slot - * associated with the output from LUTn itself is tied low. - * 0b000000..The PLU primary inputs 0. - * 0b000001..The PLU primary inputs 1. - * 0b000010..The PLU primary inputs 2. - * 0b000011..The PLU primary inputs 3. - * 0b000100..The PLU primary inputs 4. - * 0b000101..The PLU primary inputs 5. - * 0b000110..The output of LUT0. - * 0b000111..The output of LUT1. - * 0b001000..The output of LUT2. - * 0b001001..The output of LUT3. - * 0b001010..The output of LUT4. - * 0b001011..The output of LUT5. - * 0b001100..The output of LUT6. - * 0b001101..The output of LUT7. - * 0b001110..The output of LUT8. - * 0b001111..The output of LUT9. - * 0b010000..The output of LUT10. - * 0b010001..The output of LUT11. - * 0b010010..The output of LUT12. - * 0b010011..The output of LUT13. - * 0b010100..The output of LUT14. - * 0b010101..The output of LUT15. - * 0b010110..The output of LUT16. - * 0b010111..The output of LUT17. - * 0b011000..The output of LUT18. - * 0b011001..The output of LUT19. - * 0b011010..The output of LUT20. - * 0b011011..The output of LUT21. - * 0b011100..The output of LUT22. - * 0b011101..The output of LUT23. - * 0b011110..The output of LUT24. - * 0b011111..The output of LUT25. - * 0b100000..state(0). - * 0b100001..state(1). - * 0b100010..state(2). - * 0b100011..state(3). - */ -#define PLU_LUT_INP_MUX_LUTn_INPx(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_MUX_LUTn_INPx_SHIFT)) & PLU_LUT_INP_MUX_LUTn_INPx_MASK) -/*! @} */ - -/* The count of PLU_LUT_INP_MUX */ -#define PLU_LUT_INP_MUX_COUNT (26U) - -/* The count of PLU_LUT_INP_MUX */ -#define PLU_LUT_INP_MUX_COUNT2 (5U) - -/*! @name LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */ -/*! @{ */ - -#define PLU_LUT_TRUTH_LUTn_TRUTH_MASK (0xFFFFFFFFU) -#define PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT (0U) -/*! LUTn_TRUTH - Specifies the Truth Table contents for LUT25.. - */ -#define PLU_LUT_TRUTH_LUTn_TRUTH(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT)) & PLU_LUT_TRUTH_LUTn_TRUTH_MASK) -/*! @} */ - -/* The count of PLU_LUT_TRUTH */ -#define PLU_LUT_TRUTH_COUNT (26U) - -/*! @name OUTPUTS - Provides the current state of the 8 designated PLU Outputs. */ -/*! @{ */ - -#define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU) -#define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U) -/*! OUTPUT_STATE - Provides the current state of the 8 designated PLU Outputs.. - */ -#define PLU_OUTPUTS_OUTPUT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK) -/*! @} */ - -/*! @name WAKEINT_CTRL - Wakeup interrupt control for PLU */ -/*! @{ */ - -#define PLU_WAKEINT_CTRL_MASK_MASK (0xFFU) -#define PLU_WAKEINT_CTRL_MASK_SHIFT (0U) -/*! MASK - Interrupt mask (which of the 8 PLU Outputs contribute to interrupt) - */ -#define PLU_WAKEINT_CTRL_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_MASK_SHIFT)) & PLU_WAKEINT_CTRL_MASK_MASK) - -#define PLU_WAKEINT_CTRL_FILTER_MODE_MASK (0x300U) -#define PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT (8U) -/*! FILTER_MODE - control input of the PLU, add filtering for glitch. - * 0b00..Bypass mode. - * 0b01..Filter 1 clock period. - * 0b10..Filter 2 clock period. - * 0b11..Filter 3 clock period. - */ -#define PLU_WAKEINT_CTRL_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_MODE_MASK) - -#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK (0xC00U) -#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT (10U) -/*! FILTER_CLKSEL - hclk is divided by 2**filter_clksel. - * 0b00..Selects the 1 MHz low-power oscillator as the filter clock. - * 0b01..Selects the 12 Mhz FRO as the filter clock. - * 0b10..Selects a third filter clock source, if provided. - * 0b11..Reserved. - */ -#define PLU_WAKEINT_CTRL_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK) - -#define PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK (0x1000U) -#define PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT (12U) -/*! LATCH_ENABLE - latch the interrupt , then can be cleared with next bit INTR_CLEAR - */ -#define PLU_WAKEINT_CTRL_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK) - -#define PLU_WAKEINT_CTRL_INTR_CLEAR_MASK (0x2000U) -#define PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT (13U) -/*! INTR_CLEAR - Write to clear wakeint_latched - */ -#define PLU_WAKEINT_CTRL_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK) -/*! @} */ - -/*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7 */ -/*! @{ */ - -#define PLU_OUTPUT_MUX_OUTPUTn_MASK (0x1FU) -#define PLU_OUTPUT_MUX_OUTPUTn_SHIFT (0U) -/*! OUTPUTn - Selects the source to be connected to PLU Output 7. - * 0b00000..The PLU output 0. - * 0b00001..The PLU output 1. - * 0b00010..The PLU output 2. - * 0b00011..The PLU output 3. - * 0b00100..The PLU output 4. - * 0b00101..The PLU output 5. - * 0b00110..The PLU output 6. - * 0b00111..The PLU output 7. - * 0b01000..The PLU output 8. - * 0b01001..The PLU output 9. - * 0b01010..The PLU output 10. - * 0b01011..The PLU output 11. - * 0b01100..The PLU output 12. - * 0b01101..The PLU output 13. - * 0b01110..The PLU output 14. - * 0b01111..The PLU output 15. - * 0b10000..The PLU output 16. - * 0b10001..The PLU output 17. - * 0b10010..The PLU output 18. - * 0b10011..The PLU output 19. - * 0b10100..The PLU output 20. - * 0b10101..The PLU output 21. - * 0b10110..The PLU output 22. - * 0b10111..The PLU output 23. - * 0b11000..The PLU output 24. - * 0b11001..The PLU output 25. - * 0b11010..state(0). - * 0b11011..state(1). - * 0b11100..state(2). - * 0b11101..state(3). - */ -#define PLU_OUTPUT_MUX_OUTPUTn(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUTn_SHIFT)) & PLU_OUTPUT_MUX_OUTPUTn_MASK) -/*! @} */ - -/* The count of PLU_OUTPUT_MUX */ -#define PLU_OUTPUT_MUX_COUNT (8U) - - -/*! - * @} - */ /* end of group PLU_Register_Masks */ - - -/* PLU - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PLU base address */ - #define PLU_BASE (0x5003D000u) - /** Peripheral PLU base address */ - #define PLU_BASE_NS (0x4003D000u) - /** Peripheral PLU base pointer */ - #define PLU ((PLU_Type *)PLU_BASE) - /** Peripheral PLU base pointer */ - #define PLU_NS ((PLU_Type *)PLU_BASE_NS) - /** Array initializer of PLU peripheral base addresses */ - #define PLU_BASE_ADDRS { PLU_BASE } - /** Array initializer of PLU peripheral base pointers */ - #define PLU_BASE_PTRS { PLU } - /** Array initializer of PLU peripheral base addresses */ - #define PLU_BASE_ADDRS_NS { PLU_BASE_NS } - /** Array initializer of PLU peripheral base pointers */ - #define PLU_BASE_PTRS_NS { PLU_NS } -#else - /** Peripheral PLU base address */ - #define PLU_BASE (0x4003D000u) - /** Peripheral PLU base pointer */ - #define PLU ((PLU_Type *)PLU_BASE) - /** Array initializer of PLU peripheral base addresses */ - #define PLU_BASE_ADDRS { PLU_BASE } - /** Array initializer of PLU peripheral base pointers */ - #define PLU_BASE_PTRS { PLU } -#endif - -/*! - * @} - */ /* end of group PLU_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer - * @{ - */ - -/** PMC - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4]; - __I uint32_t STATUS; /**< Power Management Controller FSM (Finite State Machines) status, offset: 0x4 */ - __IO uint32_t RESETCTRL; /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x8 */ - uint8_t RESERVED_1[4]; - __IO uint32_t DCDC0; /**< DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x10 */ - __IO uint32_t DCDC1; /**< DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x14 */ - uint8_t RESERVED_2[4]; - __IO uint32_t LDOPMU; /**< Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x1C */ - uint8_t RESERVED_3[16]; - __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */ - uint8_t RESERVED_4[12]; - __IO uint32_t REFFASTWKUP; /**< Analog References fast wake-up Control register [Reset by: PoR], offset: 0x40 */ - uint8_t RESERVED_5[8]; - __IO uint32_t XTAL32K; /**< 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x4C */ - __IO uint32_t COMP; /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x50 */ - uint8_t RESERVED_6[16]; - __IO uint32_t WAKEUPIOCTRL; /**< Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset], offset: 0x64 */ - __IO uint32_t WAKEIOCAUSE; /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */ - uint8_t RESERVED_7[8]; - __IO uint32_t STATUSCLK; /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */ - uint8_t RESERVED_8[12]; - __IO uint32_t AOREG1; /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset], offset: 0x84 */ - uint8_t RESERVED_9[8]; - __IO uint32_t MISCCTRL; /**< Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x90 */ - uint8_t RESERVED_10[4]; - __IO uint32_t RTCOSC32K; /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x98 */ - __IO uint32_t OSTIMERr; /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C */ - uint8_t RESERVED_11[24]; - __IO uint32_t PDRUNCFG0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */ - uint8_t RESERVED_12[4]; - __O uint32_t PDRUNCFGSET0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */ - uint8_t RESERVED_13[4]; - __O uint32_t PDRUNCFGCLR0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */ - uint8_t RESERVED_14[8]; - __IO uint32_t SRAMCTRL; /**< All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xD4 */ -} PMC_Type; - -/* ---------------------------------------------------------------------------- - -- PMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Register_Masks PMC Register Masks - * @{ - */ - -/*! @name STATUS - Power Management Controller FSM (Finite State Machines) status */ -/*! @{ */ - -#define PMC_STATUS_BOOTMODE_MASK (0xC0000U) -#define PMC_STATUS_BOOTMODE_SHIFT (18U) -/*! BOOTMODE - Latest IC Boot cause:. - * 0b00..Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset). - * 0b01..Latest IC boot was from DEEP SLEEP low power mode. - * 0b10..Latest IC boot was from POWER DOWN low power mode. - * 0b11..Latest IC boot was from DEEP POWER DOWN low power mode. - */ -#define PMC_STATUS_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_BOOTMODE_SHIFT)) & PMC_STATUS_BOOTMODE_MASK) -/*! @} */ - -/*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U) -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U) -/*! DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). - * 0b0..Reset event from DEEP POWER DOWN mode is disable. - * 0b1..Reset event from DEEP POWER DOWN mode is enable. - */ -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK) - -#define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U) -#define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U) -/*! SWRRESETENABLE - Software reset enable. - * 0b0..Software reset is disable. - * 0b1..Software reset is enable. - */ -#define PMC_RESETCTRL_SWRRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK) - -#define PMC_RESETCTRL_BODVBATRESETENA_SECURE_MASK (0x30U) -#define PMC_RESETCTRL_BODVBATRESETENA_SECURE_SHIFT (4U) -/*! BODVBATRESETENA_SECURE - BOD VBAT reset enable. - * 0b10..BOD VBAT reset is disable. - * 0b01..Any other value than b10, BOD VBAT reset is enable. - */ -#define PMC_RESETCTRL_BODVBATRESETENA_SECURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENA_SECURE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENA_SECURE_MASK) - -#define PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK (0xC0U) -#define PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT (6U) -/*! BODCORERESETENA_SECURE - BOD Core reset enable. - * 0b10..BOD Core reset is disable. - * 0b01..Any other value than b10, BOD Core reset is enable. - */ -#define PMC_RESETCTRL_BODCORERESETENA_SECURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT)) & PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK) - -#define PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_MASK (0x30000000U) -#define PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_SHIFT (28U) -/*! BODVBATRESETENA_SECURE_DP - BOD VBAT reset enable. - * 0b10..BOD VBAT reset is disable. - * 0b01..Any other value than b10, BOD VBAT reset is enable. - */ -#define PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_MASK) - -#define PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK (0xC0000000U) -#define PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT (30U) -/*! BODCORERESETENA_SECURE_DP - BOD Core reset enable. - * 0b10..BOD Core reset is disable. - * 0b01..Any other value than b10, BOD Core reset is enable. - */ -#define PMC_RESETCTRL_BODCORERESETENA_SECURE_DP(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT)) & PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK) -/*! @} */ - -/*! @name DCDC0 - DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_DCDC0_CONFIG0_MASK (0x1FFFFU) -#define PMC_DCDC0_CONFIG0_SHIFT (0U) -/*! CONFIG0 - DCDC configuration. - */ -#define PMC_DCDC0_CONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_CONFIG0_SHIFT)) & PMC_DCDC0_CONFIG0_MASK) - -#define PMC_DCDC0_VOUT_MASK (0x1E0000U) -#define PMC_DCDC0_VOUT_SHIFT (17U) -/*! VOUT - Set output regulation voltage. - * 0b0000..0.95 V. - * 0b0001..0.975 V. - * 0b0010..1 V. - * 0b0011..1.025 V. - * 0b0100..1.05 V. - * 0b0101..1.075 V. - * 0b0110..1.1 V. - * 0b0111..1.125 V. - * 0b1000..1.15 V. - * 0b1001..1.175 V. - * 0b1010..1.2 V. - */ -#define PMC_DCDC0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_SHIFT)) & PMC_DCDC0_VOUT_MASK) - -#define PMC_DCDC0_CONFIG1_MASK (0x7E00000U) -#define PMC_DCDC0_CONFIG1_SHIFT (21U) -/*! CONFIG1 - DCDC configuration. - */ -#define PMC_DCDC0_CONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_CONFIG1_SHIFT)) & PMC_DCDC0_CONFIG1_MASK) -/*! @} */ - -/*! @name DCDC1 - DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_DCDC1_CONFIG2_MASK (0xFFFFFFFFU) -#define PMC_DCDC1_CONFIG2_SHIFT (0U) -/*! CONFIG2 - DCDC configuration. - */ -#define PMC_DCDC1_CONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_CONFIG2_SHIFT)) & PMC_DCDC1_CONFIG2_MASK) -/*! @} */ - -/*! @name LDOPMU - Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_LDOPMU_VADJ_MASK (0x1FU) -#define PMC_LDOPMU_VADJ_SHIFT (0U) -/*! VADJ - Sets the Always-On domain LDO output level. - * 0b00000..1.22 V. - * 0b00001..0.7 V. - * 0b00010..0.725 V. - * 0b00011..0.75 V. - * 0b00100..0.775 V. - * 0b00101..0.8 V. - * 0b00110..0.825 V. - * 0b00111..0.85 V. - * 0b01000..0.875 V. - * 0b01001..0.9 V. - * 0b01010..0.96 V. - * 0b01011..0.97 V. - * 0b01100..0.98 V. - * 0b01101..0.99 V. - * 0b01110..1 V. - * 0b01111..1.01 V. - * 0b10000..1.02 V. - * 0b10001..1.03 V. - * 0b10010..1.04 V. - * 0b10011..1.05 V. - * 0b10100..1.06 V. - * 0b10101..1.07 V. - * 0b10110..1.08 V. - * 0b10111..1.09 V. - * 0b11000..1.1 V. - * 0b11001..1.11 V. - * 0b11010..1.12 V. - * 0b11011..1.13 V. - * 0b11100..1.14 V. - * 0b11101..1.15 V. - * 0b11110..1.16 V. - * 0b11111..1.22 V. - */ -#define PMC_LDOPMU_VADJ(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_SHIFT)) & PMC_LDOPMU_VADJ_MASK) - -#define PMC_LDOPMU_VADJ_BOOST_MASK (0x7C00U) -#define PMC_LDOPMU_VADJ_BOOST_SHIFT (10U) -/*! VADJ_BOOST - Sets the Always-On domain LDO Boost output level. - */ -#define PMC_LDOPMU_VADJ_BOOST(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_MASK) -/*! @} */ - -/*! @name BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] */ -/*! @{ */ - -#define PMC_BODVBAT_TRIGLVL_MASK (0x1FU) -#define PMC_BODVBAT_TRIGLVL_SHIFT (0U) -/*! TRIGLVL - BoD trigger level. - * 0b00000..1.00 V. - * 0b00001..1.10 V. - * 0b00010..1.20 V. - * 0b00011..1.30 V. - * 0b00100..1.40 V. - * 0b00101..1.50 V. - * 0b00110..1.60 V. - * 0b00111..1.65 V. - * 0b01000..1.70 V. - * 0b01001..1.75 V. - * 0b01010..1.80 V. - * 0b01011..1.90 V. - * 0b01100..2.00 V. - * 0b01101..2.10 V. - * 0b01110..2.20 V. - * 0b01111..2.30 V. - * 0b10000..2.40 V. - * 0b10001..2.50 V. - * 0b10010..2.60 V. - * 0b10011..2.70 V. - * 0b10100..2.806 V. - * 0b10101..2.90 V. - * 0b10110..3.00 V. - * 0b10111..3.10 V. - * 0b11000..3.20 V. - * 0b11001..3.30 V. - * 0b11010..3.30 V. - * 0b11011..3.30 V. - * 0b11100..3.30 V. - * 0b11101..3.30 V. - * 0b11110..3.30 V. - * 0b11111..3.30 V. - */ -#define PMC_BODVBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_TRIGLVL_SHIFT)) & PMC_BODVBAT_TRIGLVL_MASK) - -#define PMC_BODVBAT_HYST_MASK (0x60U) -#define PMC_BODVBAT_HYST_SHIFT (5U) -/*! HYST - BoD Hysteresis control. - * 0b00..25 mV. - * 0b01..50 mV. - * 0b10..75 mV. - * 0b11..100 mV. - */ -#define PMC_BODVBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK) -/*! @} */ - -/*! @name REFFASTWKUP - Analog References fast wake-up Control register [Reset by: PoR] */ -/*! @{ */ - -#define PMC_REFFASTWKUP_LPWKUP_MASK (0x1U) -#define PMC_REFFASTWKUP_LPWKUP_SHIFT (0U) -/*! LPWKUP - Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP POWER DOWN): . - * 0b0..Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode. - * 0b1..Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode. - */ -#define PMC_REFFASTWKUP_LPWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_LPWKUP_SHIFT)) & PMC_REFFASTWKUP_LPWKUP_MASK) - -#define PMC_REFFASTWKUP_HWWKUP_MASK (0x2U) -#define PMC_REFFASTWKUP_HWWKUP_SHIFT (1U) -/*! HWWKUP - Analog References fast wake-up in case of Hardware Pin reset: . - * 0b0..Analog References fast wake-up feature is disabled in case of Hardware Pin reset. - * 0b1..Analog References fast wake-up feature is enabled in case of Hardware Pin reset. - */ -#define PMC_REFFASTWKUP_HWWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_HWWKUP_SHIFT)) & PMC_REFFASTWKUP_HWWKUP_MASK) -/*! @} */ - -/*! @name XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_XTAL32K_CAPBANKIN_MASK (0x7F00U) -#define PMC_XTAL32K_CAPBANKIN_SHIFT (8U) -/*! CAPBANKIN - Capa bank setting input. - */ -#define PMC_XTAL32K_CAPBANKIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKIN_SHIFT)) & PMC_XTAL32K_CAPBANKIN_MASK) - -#define PMC_XTAL32K_CAPBANKOUT_MASK (0x3F8000U) -#define PMC_XTAL32K_CAPBANKOUT_SHIFT (15U) -/*! CAPBANKOUT - Capa bank setting output. - */ -#define PMC_XTAL32K_CAPBANKOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKOUT_SHIFT)) & PMC_XTAL32K_CAPBANKOUT_MASK) -/*! @} */ - -/*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_COMP_HYST_MASK (0x2U) -#define PMC_COMP_HYST_SHIFT (1U) -/*! HYST - Hysteris when hyst = '1'. - * 0b0..Hysteresis is disable. - * 0b1..Hysteresis is enable. - */ -#define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK) - -#define PMC_COMP_VREFINPUT_MASK (0x4U) -#define PMC_COMP_VREFINPUT_SHIFT (2U) -/*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). - * 0b0..Select internal VREF. - * 0b1..Select VDDA. - */ -#define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK) - -#define PMC_COMP_LOWPOWER_MASK (0x8U) -#define PMC_COMP_LOWPOWER_SHIFT (3U) -/*! LOWPOWER - Low power mode. - * 0b0..High speed mode. - * 0b1..Low power mode (Low speed). - */ -#define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK) - -#define PMC_COMP_PMUX_MASK (0x70U) -#define PMC_COMP_PMUX_SHIFT (4U) -/*! PMUX - Control word for P multiplexer:. - * 0b000..VREF (See fiedl VREFINPUT). - * 0b001..Pin P0_0. - * 0b010..Pin P0_9. - * 0b011..Pin P0_18. - * 0b100..Pin P1_14. - * 0b101..Pin P2_23. - */ -#define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK) - -#define PMC_COMP_NMUX_MASK (0x380U) -#define PMC_COMP_NMUX_SHIFT (7U) -/*! NMUX - Control word for N multiplexer:. - * 0b000..VREF (See field VREFINPUT). - * 0b001..Pin P0_0. - * 0b010..Pin P0_9. - * 0b011..Pin P0_18. - * 0b100..Pin P1_14. - * 0b101..Pin P2_23. - */ -#define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK) - -#define PMC_COMP_VREF_MASK (0x7C00U) -#define PMC_COMP_VREF_SHIFT (10U) -/*! VREF - Control reference voltage step, per steps of (VREFINPUT/31). - */ -#define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK) - -#define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U) -#define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U) -/*! FILTERCGF_SAMPLEMODE - Control the filtering of the Analog Comparator output. - * 0b00..Bypass mode. - * 0b01..Filter 1 clock period. - * 0b10..Filter 2 clock period. - * 0b11..Filter 3 clock period. - */ -#define PMC_COMP_FILTERCGF_SAMPLEMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK) - -#define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U) -#define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U) -/*! FILTERCGF_CLKDIV - Filter Clock divider. - * 0b000..Filter clock period duration equals 1 Analog Comparator clock period. - * 0b001..Filter clock period duration equals 2 Analog Comparator clock period. - * 0b010..Filter clock period duration equals 4 Analog Comparator clock period. - * 0b011..Filter clock period duration equals 8 Analog Comparator clock period. - * 0b100..Filter clock period duration equals 16 Analog Comparator clock period. - * 0b101..Filter clock period duration equals 32 Analog Comparator clock period. - * 0b110..Filter clock period duration equals 64 Analog Comparator clock period. - * 0b111..Filter clock period duration equals 128 Analog Comparator clock period. - */ -#define PMC_COMP_FILTERCGF_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK) -/*! @} */ - -/*! @name WAKEUPIOCTRL - Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] */ -/*! @{ */ - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK (0x1U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT (0U) -/*! RISINGEDGEWAKEUP0 - Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disable. - * 0b1..Rising edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK (0x2U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT (1U) -/*! FALLINGEDGEWAKEUP0 - Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disable. - * 0b1..Falling edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK) - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK (0x4U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT (2U) -/*! RISINGEDGEWAKEUP1 - Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disable. - * 0b1..Rising edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK (0x8U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT (3U) -/*! FALLINGEDGEWAKEUP1 - Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disable. - * 0b1..Falling edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK) - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK (0x10U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT (4U) -/*! RISINGEDGEWAKEUP2 - Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disable. - * 0b1..Rising edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK (0x20U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT (5U) -/*! FALLINGEDGEWAKEUP2 - Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disable. - * 0b1..Falling edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK) - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK (0x40U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT (6U) -/*! RISINGEDGEWAKEUP3 - Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disable. - * 0b1..Rising edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK (0x80U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT (7U) -/*! FALLINGEDGEWAKEUP3 - Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disable. - * 0b1..Falling edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_MASK (0x3000U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_SHIFT (12U) -/*! MODEWAKEUPIOPAD0 - Selects function mode (on-chip pull-up/pull-down resistor control). - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_MASK (0xC000U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_SHIFT (14U) -/*! MODEWAKEUPIOPAD1 - Selects function mode (on-chip pull-up/pull-down resistor control). - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_MASK (0x30000U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_SHIFT (16U) -/*! MODEWAKEUPIOPAD2 - Selects function mode (on-chip pull-up/pull-down resistor control). - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_MASK (0xC0000U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_SHIFT (18U) -/*! MODEWAKEUPIOPAD3 - Selects function mode (on-chip pull-up/pull-down resistor control). - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_MASK) - -#define PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK (0x100000U) -#define PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_SHIFT (20U) -/*! WAKEUPIO_ENABLE_CTRL - Enable WAKEUP IO PAD control from MODEWAKEUPIOPAD (bits 12 to 19). - * 0b0..WAKEUP IO PAD mode control comes from IOCON. - * 0b1..WAKEUP IO PAD mode control comes from MODEWAKEUPIOPAD (bits 12 to 19). - */ -#define PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_SHIFT)) & PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK) - -#define PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_MASK (0x200000U) -#define PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_SHIFT (21U) -/*! WAKEUPIO_RSTN - WAKEUP IO event detector reset control. - * 0b0..Bloc is reset. - * 0b1..Bloc is not reset. - */ -#define PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_SHIFT)) & PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_MASK) -/*! @} */ - -/*! @name WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode */ -/*! @{ */ - -#define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U) -#define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U) -/*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0. - */ -#define PMC_WAKEIOCAUSE_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK) - -#define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U) -#define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U) -/*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1. - */ -#define PMC_WAKEIOCAUSE_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK) - -#define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U) -#define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U) -/*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2. - */ -#define PMC_WAKEIOCAUSE_WAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK) - -#define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U) -#define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U) -/*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 3. - */ -#define PMC_WAKEIOCAUSE_WAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK) -/*! @} */ - -/*! @name STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U) -#define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U) -/*! XTAL32KOK - XTAL oscillator 32 K OK signal. - */ -#define PMC_STATUSCLK_XTAL32KOK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK) - -#define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U) -#define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U) -/*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. - * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared. - * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared. - */ -#define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK) -/*! @} */ - -/*! @name AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_AOREG1_POR_MASK (0x10U) -#define PMC_AOREG1_POR_SHIFT (4U) -/*! POR - The last chip reset was caused by a Power On Reset. - */ -#define PMC_AOREG1_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_POR_SHIFT)) & PMC_AOREG1_POR_MASK) - -#define PMC_AOREG1_PADRESET_MASK (0x20U) -#define PMC_AOREG1_PADRESET_SHIFT (5U) -/*! PADRESET - The last chip reset was caused by a Pin Reset. - */ -#define PMC_AOREG1_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_PADRESET_SHIFT)) & PMC_AOREG1_PADRESET_MASK) - -#define PMC_AOREG1_BODRESET_MASK (0x40U) -#define PMC_AOREG1_BODRESET_SHIFT (6U) -/*! BODRESET - The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. - */ -#define PMC_AOREG1_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BODRESET_SHIFT)) & PMC_AOREG1_BODRESET_MASK) - -#define PMC_AOREG1_SYSTEMRESET_MASK (0x80U) -#define PMC_AOREG1_SYSTEMRESET_SHIFT (7U) -/*! SYSTEMRESET - The last chip reset was caused by a System Reset requested by the ARM CPU. - */ -#define PMC_AOREG1_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SYSTEMRESET_SHIFT)) & PMC_AOREG1_SYSTEMRESET_MASK) - -#define PMC_AOREG1_WDTRESET_MASK (0x100U) -#define PMC_AOREG1_WDTRESET_SHIFT (8U) -/*! WDTRESET - The last chip reset was caused by the Watchdog Timer. - */ -#define PMC_AOREG1_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_WDTRESET_SHIFT)) & PMC_AOREG1_WDTRESET_MASK) - -#define PMC_AOREG1_SWRRESET_MASK (0x200U) -#define PMC_AOREG1_SWRRESET_SHIFT (9U) -/*! SWRRESET - The last chip reset was caused by a Software event. - */ -#define PMC_AOREG1_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SWRRESET_SHIFT)) & PMC_AOREG1_SWRRESET_MASK) - -#define PMC_AOREG1_DPDRESET_WAKEUPIO_MASK (0x400U) -#define PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT (10U) -/*! DPDRESET_WAKEUPIO - The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode. - */ -#define PMC_AOREG1_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT)) & PMC_AOREG1_DPDRESET_WAKEUPIO_MASK) - -#define PMC_AOREG1_DPDRESET_RTC_MASK (0x800U) -#define PMC_AOREG1_DPDRESET_RTC_SHIFT (11U) -/*! DPDRESET_RTC - The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode. - */ -#define PMC_AOREG1_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_RTC_SHIFT)) & PMC_AOREG1_DPDRESET_RTC_MASK) - -#define PMC_AOREG1_DPDRESET_OSTIMER_MASK (0x1000U) -#define PMC_AOREG1_DPDRESET_OSTIMER_SHIFT (12U) -/*! DPDRESET_OSTIMER - The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode. - */ -#define PMC_AOREG1_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_OSTIMER_SHIFT)) & PMC_AOREG1_DPDRESET_OSTIMER_MASK) - -#define PMC_AOREG1_CDOGRESET_MASK (0x2000U) -#define PMC_AOREG1_CDOGRESET_SHIFT (13U) -/*! CDOGRESET - The last chip reset was caused by the code Watchdog. - */ -#define PMC_AOREG1_CDOGRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_CDOGRESET_SHIFT)) & PMC_AOREG1_CDOGRESET_MASK) - -#define PMC_AOREG1_BOOTERRORCOUNTER_MASK (0xF0000U) -#define PMC_AOREG1_BOOTERRORCOUNTER_SHIFT (16U) -/*! BOOTERRORCOUNTER - ROM Boot Fatal Error Counter. - */ -#define PMC_AOREG1_BOOTERRORCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BOOTERRORCOUNTER_SHIFT)) & PMC_AOREG1_BOOTERRORCOUNTER_MASK) -/*! @} */ - -/*! @name MISCCTRL - Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK (0x2U) -#define PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT (1U) -/*! LDOMEMHIGHZMODE - Control the activation of LDO MEM High Z mode. - * 0b0..LDO MEM High Z mode is disabled. - * 0b1..LDO MEM High Z mode is enabled. - */ -#define PMC_MISCCTRL_LDOMEMHIGHZMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT)) & PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK) - -#define PMC_MISCCTRL_DISABLE_BLEED_MASK (0x1000U) -#define PMC_MISCCTRL_DISABLE_BLEED_SHIFT (12U) -/*! DISABLE_BLEED - Controls LDO MEM bleed current. This field is expected to be controlled by the - * Low Power Software only in DEEP SLEEP low power mode. - * 0b0..LDO_MEM bleed current is enabled. - * 0b1..LDO_MEM bleed current is disabled. Should be set before entering in Deep Sleep low power mode and cleared - * after wake up from Deep SLeep low power mode. - */ -#define PMC_MISCCTRL_DISABLE_BLEED(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_DISABLE_BLEED_SHIFT)) & PMC_MISCCTRL_DISABLE_BLEED_MASK) -/*! @} */ - -/*! @name RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_RTCOSC32K_SEL_MASK (0x1U) -#define PMC_RTCOSC32K_SEL_SHIFT (0U) -/*! SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . - * 0b0..FRO 32 KHz. - * 0b1..XTAL 32KHz. - */ -#define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK) - -#define PMC_RTCOSC32K_CLK1KHZDIV_MASK (0xEU) -#define PMC_RTCOSC32K_CLK1KHZDIV_SHIFT (1U) -/*! CLK1KHZDIV - Actual division ratio is : 28 + CLK1KHZDIV. - */ -#define PMC_RTCOSC32K_CLK1KHZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIV_MASK) - -#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK (0x8000U) -#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT (15U) -/*! CLK1KHZDIVUPDATEREQ - RTC 1KHz clock Divider status flag. - */ -#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK) - -#define PMC_RTCOSC32K_CLK1HZDIV_MASK (0x7FF0000U) -#define PMC_RTCOSC32K_CLK1HZDIV_SHIFT (16U) -/*! CLK1HZDIV - Actual division ratio is : 31744 + CLK1HZDIV. - */ -#define PMC_RTCOSC32K_CLK1HZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIV_MASK) - -#define PMC_RTCOSC32K_CLK1HZDIVHALT_MASK (0x40000000U) -#define PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT (30U) -/*! CLK1HZDIVHALT - Halts the divider counter. - */ -#define PMC_RTCOSC32K_CLK1HZDIVHALT(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVHALT_MASK) - -#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK (0x80000000U) -#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT (31U) -/*! CLK1HZDIVUPDATEREQ - RTC 1Hz Divider status flag. - */ -#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK) -/*! @} */ - -/*! @name OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_OSTIMER_SOFTRESET_MASK (0x1U) -#define PMC_OSTIMER_SOFTRESET_SHIFT (0U) -/*! SOFTRESET - Active high reset. - */ -#define PMC_OSTIMER_SOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_SOFTRESET_SHIFT)) & PMC_OSTIMER_SOFTRESET_MASK) - -#define PMC_OSTIMER_CLOCKENABLE_MASK (0x2U) -#define PMC_OSTIMER_CLOCKENABLE_SHIFT (1U) -/*! CLOCKENABLE - Enable OS event timer clock. - */ -#define PMC_OSTIMER_CLOCKENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_CLOCKENABLE_SHIFT)) & PMC_OSTIMER_CLOCKENABLE_MASK) - -#define PMC_OSTIMER_DPDWAKEUPENABLE_MASK (0x4U) -#define PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT (2U) -/*! DPDWAKEUPENABLE - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode). - */ -#define PMC_OSTIMER_DPDWAKEUPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSTIMER_DPDWAKEUPENABLE_MASK) - -#define PMC_OSTIMER_OSC32KPD_MASK (0x8U) -#define PMC_OSTIMER_OSC32KPD_SHIFT (3U) -/*! OSC32KPD - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K. - */ -#define PMC_OSTIMER_OSC32KPD(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSC32KPD_SHIFT)) & PMC_OSTIMER_OSC32KPD_MASK) - -#define PMC_OSTIMER_OSTIMERCLKSEL_MASK (0x30U) -#define PMC_OSTIMER_OSTIMERCLKSEL_SHIFT (4U) -/*! OSTIMERCLKSEL - OS event timer clock select. - * 0b00..Oscillator 32 kHz clock. - * 0b01..FRO 1MHz clock. - * 0b10..Main clock for OS timer. - * 0b11..No clock. - */ -#define PMC_OSTIMER_OSTIMERCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSTIMERCLKSEL_SHIFT)) & PMC_OSTIMER_OSTIMERCLKSEL_MASK) -/*! @} */ - -/*! @name PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_PDRUNCFG0_PDEN_BODVBAT_MASK (0x8U) -#define PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT (3U) -/*! PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD). - * 0b0..BOD VBAT is powered. - * 0b1..BOD VBAT is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVBAT_MASK) - -#define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U) -#define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U) -/*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. - * 0b0..FRO32KHz is powered. - * 0b1..FRO32KHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK) - -#define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U) -#define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U) -/*! PDEN_XTAL32K - Controls power to crystal 32 KHz. - * 0b0..Crystal 32KHz is powered. - * 0b1..Crystal 32KHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK) - -#define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK (0x100U) -#define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT (8U) -/*! PDEN_XTAL32M - Controls power to high speed crystal. - * 0b0..High speed crystal is powered. - * 0b1..High speed crystal is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK) - -#define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U) -#define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U) -/*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). - * 0b0..PLL0 is powered. - * 0b1..PLL0 is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK) - -#define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U) -#define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U) -/*! PDEN_PLL1 - Controls power to PLL1. - * 0b0..PLL1 is powered. - * 0b1..PLL1 is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK) - -#define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U) -#define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U) -/*! PDEN_COMP - Controls power to Analog Comparator. - * 0b0..Analog Comparator is powered. - * 0b1..Analog Comparator is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK) - -#define PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK (0x80000U) -#define PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT (19U) -/*! PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS) - * 0b0..auxiliary biasing is powered. - * 0b1..auxiliary biasing is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK) - -#define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK (0x100000U) -#define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT (20U) -/*! PDEN_LDOXO32M - Controls power to high speed crystal LDO. - * 0b0..High speed crystal LDO is powered. - * 0b1..High speed crystal LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK) - -#define PMC_PDRUNCFG0_PDEN_RNG_MASK (0x400000U) -#define PMC_PDRUNCFG0_PDEN_RNG_SHIFT (22U) -/*! PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources. - * 0b0..TRNG clocks are powered. - * 0b1..TRNG clocks are powered down. - */ -#define PMC_PDRUNCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_RNG_SHIFT)) & PMC_PDRUNCFG0_PDEN_RNG_MASK) - -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U) -/*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. - * 0b0..PLL0 Sread spectrum module is powered. - * 0b1..PLL0 Sread spectrum module is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) -/*! @} */ - -/*! @name PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU) -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U) -/*! PDRUNCFGSET0 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. - */ -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK) -/*! @} */ - -/*! @name PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU) -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U) -/*! PDRUNCFGCLR0 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. - */ -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK) -/*! @} */ - -/*! @name SRAMCTRL - All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ -/*! @{ */ - -#define PMC_SRAMCTRL_SMB_MASK (0x3U) -#define PMC_SRAMCTRL_SMB_SHIFT (0U) -/*! SMB - Source Biasing voltage. - * 0b00..Low leakage. - * 0b01..Medium leakage. - * 0b10..Highest leakage. - * 0b11..Disable. - */ -#define PMC_SRAMCTRL_SMB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_SMB_SHIFT)) & PMC_SRAMCTRL_SMB_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PMC_Register_Masks */ - - -/* PMC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PMC base address */ - #define PMC_BASE (0x50020000u) - /** Peripheral PMC base address */ - #define PMC_BASE_NS (0x40020000u) - /** Peripheral PMC base pointer */ - #define PMC ((PMC_Type *)PMC_BASE) - /** Peripheral PMC base pointer */ - #define PMC_NS ((PMC_Type *)PMC_BASE_NS) - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS { PMC_BASE } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS { PMC } - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS_NS { PMC_BASE_NS } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS_NS { PMC_NS } -#else - /** Peripheral PMC base address */ - #define PMC_BASE (0x40020000u) - /** Peripheral PMC base pointer */ - #define PMC ((PMC_Type *)PMC_BASE) - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS { PMC_BASE } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS { PMC } -#endif - -/*! - * @} - */ /* end of group PMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PRINCE Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PRINCE_Peripheral_Access_Layer PRINCE Peripheral Access Layer - * @{ - */ - -/** PRINCE - Register Layout Typedef */ -typedef struct { - __IO uint32_t ENC_ENABLE; /**< Encryption Enable register, offset: 0x0 */ - __O uint32_t MASK_LSB; /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */ - __O uint32_t MASK_MSB; /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */ - __IO uint32_t LOCK; /**< Lock register, offset: 0xC */ - __O uint32_t IV_LSB0; /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */ - __O uint32_t IV_MSB0; /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */ - __IO uint32_t BASE_ADDR0; /**< Base Address for region 0 register, offset: 0x18 */ - __IO uint32_t SR_ENABLE0; /**< Sub-Region Enable register for region 0, offset: 0x1C */ - __O uint32_t IV_LSB1; /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */ - __O uint32_t IV_MSB1; /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */ - __IO uint32_t BASE_ADDR1; /**< Base Address for region 1 register, offset: 0x28 */ - __IO uint32_t SR_ENABLE1; /**< Sub-Region Enable register for region 1, offset: 0x2C */ - __O uint32_t IV_LSB2; /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */ - __O uint32_t IV_MSB2; /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */ - __IO uint32_t BASE_ADDR2; /**< Base Address for region 2 register, offset: 0x38 */ - __IO uint32_t SR_ENABLE2; /**< Sub-Region Enable register for region 2, offset: 0x3C */ - uint8_t RESERVED_0[80]; - __IO uint32_t ERR; /**< Error status register, offset: 0x90 */ -} PRINCE_Type; - -/* ---------------------------------------------------------------------------- - -- PRINCE Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PRINCE_Register_Masks PRINCE Register Masks - * @{ - */ - -/*! @name ENC_ENABLE - Encryption Enable register */ -/*! @{ */ - -#define PRINCE_ENC_ENABLE_EN_MASK (0x1U) -#define PRINCE_ENC_ENABLE_EN_SHIFT (0U) -/*! EN - Enables PRINCE encryption for flash programming. - * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled. - * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled. Reading of PRINCE-encrypted flash regions is disabled. - */ -#define PRINCE_ENC_ENABLE_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK) -/*! @} */ - -/*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */ -/*! @{ */ - -#define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU) -#define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U) -/*! MASKVAL - Value of the 32 Least Significant Bits of the 64-bit data mask. - */ -#define PRINCE_MASK_LSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK) -/*! @} */ - -/*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */ -/*! @{ */ - -#define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU) -#define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U) -/*! MASKVAL - Value of the 32 Most Significant Bits of the 64-bit data mask. - */ -#define PRINCE_MASK_MSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK) -/*! @} */ - -/*! @name LOCK - Lock register */ -/*! @{ */ - -#define PRINCE_LOCK_LOCKREG0_MASK (0x1U) -#define PRINCE_LOCK_LOCKREG0_SHIFT (0U) -/*! LOCKREG0 - Lock Region 0 registers. - * 0b0..Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. - * 0b1..Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. - */ -#define PRINCE_LOCK_LOCKREG0(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK) - -#define PRINCE_LOCK_LOCKREG1_MASK (0x2U) -#define PRINCE_LOCK_LOCKREG1_SHIFT (1U) -/*! LOCKREG1 - Lock Region 1 registers. - * 0b0..Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. - * 0b1..Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. - */ -#define PRINCE_LOCK_LOCKREG1(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK) - -#define PRINCE_LOCK_LOCKREG2_MASK (0x4U) -#define PRINCE_LOCK_LOCKREG2_SHIFT (2U) -/*! LOCKREG2 - Lock Region 2 registers. - * 0b0..Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. - * 0b1..Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. - */ -#define PRINCE_LOCK_LOCKREG2(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK) - -#define PRINCE_LOCK_LOCKMASK_MASK (0x100U) -#define PRINCE_LOCK_LOCKMASK_SHIFT (8U) -/*! LOCKMASK - Lock the Mask registers. - * 0b0..Disabled. MASK_LSB, and MASK_MSB are writable.. - * 0b1..Enabled. MASK_LSB, and MASK_MSB are not writable.. - */ -#define PRINCE_LOCK_LOCKMASK(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK) -/*! @} */ - -/*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB0_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_LSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB0_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_MSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR0 - Base Address for region 0 register */ -/*! @{ */ - -#define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U) -/*! ADDR_FIXED - Fixed portion of the base address of region 0. - */ -#define PRINCE_BASE_ADDR0_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK) - -#define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U) -/*! ADDR_PRG - Programmable portion of the base address of region 0. - */ -#define PRINCE_BASE_ADDR0_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */ -/*! @{ */ - -#define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE0_EN_SHIFT (0U) -/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0. - */ -#define PRINCE_SR_ENABLE0_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK) -/*! @} */ - -/*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB1_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_LSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB1_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_MSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR1 - Base Address for region 1 register */ -/*! @{ */ - -#define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U) -/*! ADDR_FIXED - Fixed portion of the base address of region 1. - */ -#define PRINCE_BASE_ADDR1_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK) - -#define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U) -/*! ADDR_PRG - Programmable portion of the base address of region 1. - */ -#define PRINCE_BASE_ADDR1_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */ -/*! @{ */ - -#define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE1_EN_SHIFT (0U) -/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1. - */ -#define PRINCE_SR_ENABLE1_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK) -/*! @} */ - -/*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB2_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_LSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB2_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_MSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR2 - Base Address for region 2 register */ -/*! @{ */ - -#define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U) -/*! ADDR_FIXED - Fixed portion of the base address of region 2. - */ -#define PRINCE_BASE_ADDR2_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK) - -#define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U) -/*! ADDR_PRG - Programmable portion of the base address of region 2. - */ -#define PRINCE_BASE_ADDR2_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */ -/*! @{ */ - -#define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE2_EN_SHIFT (0U) -/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2. - */ -#define PRINCE_SR_ENABLE2_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK) -/*! @} */ - -/*! @name ERR - Error status register */ -/*! @{ */ - -#define PRINCE_ERR_ERRSTAT_MASK (0x1U) -#define PRINCE_ERR_ERRSTAT_SHIFT (0U) -/*! ERRSTAT - PRINCE Error Status. This bit is write-1 to clear. - * 0b0..No PRINCE error. - * 0b1..Error. A read of a PRINCE-encrypted region was attempted while ENC_ENABLE.EN=1. - */ -#define PRINCE_ERR_ERRSTAT(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ERR_ERRSTAT_SHIFT)) & PRINCE_ERR_ERRSTAT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PRINCE_Register_Masks */ - - -/* PRINCE - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PRINCE base address */ - #define PRINCE_BASE (0x50035000u) - /** Peripheral PRINCE base address */ - #define PRINCE_BASE_NS (0x40035000u) - /** Peripheral PRINCE base pointer */ - #define PRINCE ((PRINCE_Type *)PRINCE_BASE) - /** Peripheral PRINCE base pointer */ - #define PRINCE_NS ((PRINCE_Type *)PRINCE_BASE_NS) - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS { PRINCE_BASE } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS { PRINCE } - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS_NS { PRINCE_BASE_NS } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS_NS { PRINCE_NS } -#else - /** Peripheral PRINCE base address */ - #define PRINCE_BASE (0x40035000u) - /** Peripheral PRINCE base pointer */ - #define PRINCE ((PRINCE_Type *)PRINCE_BASE) - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS { PRINCE_BASE } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS { PRINCE } -#endif - -/*! - * @} - */ /* end of group PRINCE_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PUF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer - * @{ - */ - -/** PUF - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< PUF Control register, offset: 0x0 */ - __IO uint32_t KEYINDEX; /**< PUF Key Index register, offset: 0x4 */ - __IO uint32_t KEYSIZE; /**< PUF Key Size register, offset: 0x8 */ - uint8_t RESERVED_0[20]; - __I uint32_t STAT; /**< PUF Status register, offset: 0x20 */ - uint8_t RESERVED_1[4]; - __I uint32_t ALLOW; /**< PUF Allow register, offset: 0x28 */ - uint8_t RESERVED_2[20]; - __O uint32_t KEYINPUT; /**< PUF Key Input register, offset: 0x40 */ - __O uint32_t CODEINPUT; /**< PUF Code Input register, offset: 0x44 */ - __I uint32_t CODEOUTPUT; /**< PUF Code Output register, offset: 0x48 */ - uint8_t RESERVED_3[20]; - __I uint32_t KEYOUTINDEX; /**< PUF Key Output Index register, offset: 0x60 */ - __I uint32_t KEYOUTPUT; /**< PUF Key Output register, offset: 0x64 */ - uint8_t RESERVED_4[116]; - __IO uint32_t IFSTAT; /**< PUF Interface Status and clear register, offset: 0xDC */ - uint8_t RESERVED_5[32]; - __IO uint32_t INTEN; /**< PUF Interrupt Enable, offset: 0x100 */ - __IO uint32_t INTSTAT; /**< PUF interrupt status, offset: 0x104 */ - uint8_t RESERVED_6[4]; - __IO uint32_t CFG; /**< PUF config register for block bits, offset: 0x10C */ - uint8_t RESERVED_7[240]; - __IO uint32_t KEYLOCK; /**< Only reset in case of full IC reset, offset: 0x200 */ - __IO uint32_t KEYENABLE; /**< , offset: 0x204 */ - __O uint32_t KEYRESET; /**< Reinitialize Keys shift registers counters, offset: 0x208 */ - __O uint32_t IDXBLK; /**< , offset: 0x20C */ - __O uint32_t IDXBLK_DP; /**< , offset: 0x210 */ - __O uint32_t KEYMASK[4]; /**< Only reset in case of full IC reset, array offset: 0x214, array step: 0x4 */ - uint8_t RESERVED_8[48]; - __I uint32_t IDXBLK_STATUS; /**< Index block status, offset: 0x254 */ - __I uint32_t SHIFT_STATUS; /**< , offset: 0x258 */ -} PUF_Type; - -/* ---------------------------------------------------------------------------- - -- PUF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_Register_Masks PUF Register Masks - * @{ - */ - -/*! @name CTRL - PUF Control register */ -/*! @{ */ - -#define PUF_CTRL_ZEROIZE_MASK (0x1U) -#define PUF_CTRL_ZEROIZE_SHIFT (0U) -/*! zeroize - Begin Zeroize operation for PUF and go to Error state - */ -#define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK) - -#define PUF_CTRL_ENROLL_MASK (0x2U) -#define PUF_CTRL_ENROLL_SHIFT (1U) -/*! enroll - Begin Enroll operation - */ -#define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK) - -#define PUF_CTRL_START_MASK (0x4U) -#define PUF_CTRL_START_SHIFT (2U) -/*! start - Begin Start operation - */ -#define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK) - -#define PUF_CTRL_GENERATEKEY_MASK (0x8U) -#define PUF_CTRL_GENERATEKEY_SHIFT (3U) -/*! GENERATEKEY - Begin Set Intrinsic Key operation - */ -#define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK) - -#define PUF_CTRL_SETKEY_MASK (0x10U) -#define PUF_CTRL_SETKEY_SHIFT (4U) -/*! SETKEY - Begin Set User Key operation - */ -#define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK) - -#define PUF_CTRL_GETKEY_MASK (0x40U) -#define PUF_CTRL_GETKEY_SHIFT (6U) -/*! GETKEY - Begin Get Key operation - */ -#define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK) -/*! @} */ - -/*! @name KEYINDEX - PUF Key Index register */ -/*! @{ */ - -#define PUF_KEYINDEX_KEYIDX_MASK (0xFU) -#define PUF_KEYINDEX_KEYIDX_SHIFT (0U) -/*! KEYIDX - Key index for Set Key operations - */ -#define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK) -/*! @} */ - -/*! @name KEYSIZE - PUF Key Size register */ -/*! @{ */ - -#define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU) -#define PUF_KEYSIZE_KEYSIZE_SHIFT (0U) -/*! KEYSIZE - Key size for Set Key operations - */ -#define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK) -/*! @} */ - -/*! @name STAT - PUF Status register */ -/*! @{ */ - -#define PUF_STAT_BUSY_MASK (0x1U) -#define PUF_STAT_BUSY_SHIFT (0U) -/*! busy - Indicates that operation is in progress - */ -#define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK) - -#define PUF_STAT_SUCCESS_MASK (0x2U) -#define PUF_STAT_SUCCESS_SHIFT (1U) -/*! SUCCESS - Last operation was successful - */ -#define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK) - -#define PUF_STAT_ERROR_MASK (0x4U) -#define PUF_STAT_ERROR_SHIFT (2U) -/*! error - PUF is in the Error state and no operations can be performed - */ -#define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK) - -#define PUF_STAT_KEYINREQ_MASK (0x10U) -#define PUF_STAT_KEYINREQ_SHIFT (4U) -/*! KEYINREQ - Request for next part of key - */ -#define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK) - -#define PUF_STAT_KEYOUTAVAIL_MASK (0x20U) -#define PUF_STAT_KEYOUTAVAIL_SHIFT (5U) -/*! KEYOUTAVAIL - Next part of key is available - */ -#define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK) - -#define PUF_STAT_CODEINREQ_MASK (0x40U) -#define PUF_STAT_CODEINREQ_SHIFT (6U) -/*! CODEINREQ - Request for next part of AC/KC - */ -#define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK) - -#define PUF_STAT_CODEOUTAVAIL_MASK (0x80U) -#define PUF_STAT_CODEOUTAVAIL_SHIFT (7U) -/*! CODEOUTAVAIL - Next part of AC/KC is available - */ -#define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK) -/*! @} */ - -/*! @name ALLOW - PUF Allow register */ -/*! @{ */ - -#define PUF_ALLOW_ALLOWENROLL_MASK (0x1U) -#define PUF_ALLOW_ALLOWENROLL_SHIFT (0U) -/*! ALLOWENROLL - Enroll operation is allowed - */ -#define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK) - -#define PUF_ALLOW_ALLOWSTART_MASK (0x2U) -#define PUF_ALLOW_ALLOWSTART_SHIFT (1U) -/*! ALLOWSTART - Start operation is allowed - */ -#define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK) - -#define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U) -#define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U) -/*! ALLOWSETKEY - Set Key operations are allowed - */ -#define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK) - -#define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U) -#define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U) -/*! ALLOWGETKEY - Get Key operation is allowed - */ -#define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK) -/*! @} */ - -/*! @name KEYINPUT - PUF Key Input register */ -/*! @{ */ - -#define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU) -#define PUF_KEYINPUT_KEYIN_SHIFT (0U) -/*! KEYIN - Key input data - */ -#define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK) -/*! @} */ - -/*! @name CODEINPUT - PUF Code Input register */ -/*! @{ */ - -#define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU) -#define PUF_CODEINPUT_CODEIN_SHIFT (0U) -/*! CODEIN - AC/KC input data - */ -#define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK) -/*! @} */ - -/*! @name CODEOUTPUT - PUF Code Output register */ -/*! @{ */ - -#define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU) -#define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U) -/*! CODEOUT - AC/KC output data - */ -#define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK) -/*! @} */ - -/*! @name KEYOUTINDEX - PUF Key Output Index register */ -/*! @{ */ - -#define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFU) -#define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U) -/*! KEYOUTIDX - Key index for the key that is currently output via the Key Output register - */ -#define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK) -/*! @} */ - -/*! @name KEYOUTPUT - PUF Key Output register */ -/*! @{ */ - -#define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU) -#define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U) -/*! KEYOUT - Key output data - */ -#define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK) -/*! @} */ - -/*! @name IFSTAT - PUF Interface Status and clear register */ -/*! @{ */ - -#define PUF_IFSTAT_ERROR_MASK (0x1U) -#define PUF_IFSTAT_ERROR_SHIFT (0U) -/*! ERROR - Indicates that an APB error has occurred,Writing logic1 clears the if_error bit - */ -#define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK) -/*! @} */ - -/*! @name INTEN - PUF Interrupt Enable */ -/*! @{ */ - -#define PUF_INTEN_READYEN_MASK (0x1U) -#define PUF_INTEN_READYEN_SHIFT (0U) -/*! READYEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK) - -#define PUF_INTEN_SUCCESEN_MASK (0x2U) -#define PUF_INTEN_SUCCESEN_SHIFT (1U) -/*! SUCCESEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_SUCCESEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK) - -#define PUF_INTEN_ERROREN_MASK (0x4U) -#define PUF_INTEN_ERROREN_SHIFT (2U) -/*! ERROREN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK) - -#define PUF_INTEN_KEYINREQEN_MASK (0x10U) -#define PUF_INTEN_KEYINREQEN_SHIFT (4U) -/*! KEYINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK) - -#define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U) -#define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U) -/*! KEYOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK) - -#define PUF_INTEN_CODEINREQEN_MASK (0x40U) -#define PUF_INTEN_CODEINREQEN_SHIFT (6U) -/*! CODEINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK) - -#define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U) -#define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U) -/*! CODEOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK) -/*! @} */ - -/*! @name INTSTAT - PUF interrupt status */ -/*! @{ */ - -#define PUF_INTSTAT_READY_MASK (0x1U) -#define PUF_INTSTAT_READY_SHIFT (0U) -/*! READY - Triggers on falling edge of busy, write 1 to clear - */ -#define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK) - -#define PUF_INTSTAT_SUCCESS_MASK (0x2U) -#define PUF_INTSTAT_SUCCESS_SHIFT (1U) -/*! SUCCESS - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK) - -#define PUF_INTSTAT_ERROR_MASK (0x4U) -#define PUF_INTSTAT_ERROR_SHIFT (2U) -/*! ERROR - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK) - -#define PUF_INTSTAT_KEYINREQ_MASK (0x10U) -#define PUF_INTSTAT_KEYINREQ_SHIFT (4U) -/*! KEYINREQ - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK) - -#define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U) -#define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U) -/*! KEYOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK) - -#define PUF_INTSTAT_CODEINREQ_MASK (0x40U) -#define PUF_INTSTAT_CODEINREQ_SHIFT (6U) -/*! CODEINREQ - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK) - -#define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U) -#define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U) -/*! CODEOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK) -/*! @} */ - -/*! @name CFG - PUF config register for block bits */ -/*! @{ */ - -#define PUF_CFG_BLOCKENROLL_SETKEY_MASK (0x1U) -#define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT (0U) -/*! BLOCKENROLL_SETKEY - Block enroll operation. Write 1 to set, cleared on reset. - */ -#define PUF_CFG_BLOCKENROLL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK) - -#define PUF_CFG_BLOCKKEYOUTPUT_MASK (0x2U) -#define PUF_CFG_BLOCKKEYOUTPUT_SHIFT (1U) -/*! BLOCKKEYOUTPUT - Block set key operation. Write 1 to set, cleared on reset. - */ -#define PUF_CFG_BLOCKKEYOUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK) -/*! @} */ - -/*! @name KEYLOCK - Only reset in case of full IC reset */ -/*! @{ */ - -#define PUF_KEYLOCK_KEY0_MASK (0x3U) -#define PUF_KEYLOCK_KEY0_SHIFT (0U) -/*! KEY0 - "10:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is allowed. 00, 01, - * 11:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is NOT allowed. Important Note : Once - * this field is written with a value different from '10', its value can no longer be modified - * until un Power On Reset occurs." - */ -#define PUF_KEYLOCK_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK) - -#define PUF_KEYLOCK_KEY1_MASK (0xCU) -#define PUF_KEYLOCK_KEY1_SHIFT (2U) -/*! KEY1 - "10:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is allowed. 00, 01, - * 11:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is NOT allowed. Important Note : Once - * this field is written with a value different from '10', its value can no longer be modified - * until un Power On Reset occurs." - */ -#define PUF_KEYLOCK_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK) - -#define PUF_KEYLOCK_KEY2_MASK (0x30U) -#define PUF_KEYLOCK_KEY2_SHIFT (4U) -/*! KEY2 - "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, - * 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once - * this field is written with a value different from '10', its value can no longer be modified - * until un Power On Reset occurs." - */ -#define PUF_KEYLOCK_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK) - -#define PUF_KEYLOCK_KEY3_MASK (0xC0U) -#define PUF_KEYLOCK_KEY3_SHIFT (6U) -/*! KEY3 - "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, - * 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once - * this field is written with a value different from '10', its value can no longer be modified - * until un Power On Reset occurs." - */ -#define PUF_KEYLOCK_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK) -/*! @} */ - -/*! @name KEYENABLE - */ -/*! @{ */ - -#define PUF_KEYENABLE_KEY0_MASK (0x3U) -#define PUF_KEYENABLE_KEY0_SHIFT (0U) -/*! KEY0 - "10: Data coming out from PUF Index 0 interface are shifted in KEY0 register. 00, 01, 11 - * : Data coming out from PUF Index 0 interface are NOT shifted in KEY0 register." - */ -#define PUF_KEYENABLE_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK) - -#define PUF_KEYENABLE_KEY1_MASK (0xCU) -#define PUF_KEYENABLE_KEY1_SHIFT (2U) -/*! KEY1 - "10: Data coming out from PUF Index 0 interface are shifted in KEY1 register. 00, 01, 11 - * : Data coming out from PUF Index 0 interface are NOT shifted in KEY1 register." - */ -#define PUF_KEYENABLE_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK) - -#define PUF_KEYENABLE_KEY2_MASK (0x30U) -#define PUF_KEYENABLE_KEY2_SHIFT (4U) -/*! KEY2 - "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 - * : Data coming out from PUF Index 0 interface are NOT shifted in KEY2 register." - */ -#define PUF_KEYENABLE_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK) - -#define PUF_KEYENABLE_KEY3_MASK (0xC0U) -#define PUF_KEYENABLE_KEY3_SHIFT (6U) -/*! KEY3 - "10: Data coming out from PUF Index 0 interface are shifted in KEY3 register. 00, 01, 11 - * : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." - */ -#define PUF_KEYENABLE_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK) -/*! @} */ - -/*! @name KEYRESET - Reinitialize Keys shift registers counters */ -/*! @{ */ - -#define PUF_KEYRESET_KEY0_MASK (0x3U) -#define PUF_KEYRESET_KEY0_SHIFT (0U) -/*! KEY0 - 10: Reset KEY0 shift register. Self clearing. Must be done before loading any new key. - */ -#define PUF_KEYRESET_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK) - -#define PUF_KEYRESET_KEY1_MASK (0xCU) -#define PUF_KEYRESET_KEY1_SHIFT (2U) -/*! KEY1 - 10: Reset KEY1 shift register. Self clearing. Must be done before loading any new key. - */ -#define PUF_KEYRESET_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK) - -#define PUF_KEYRESET_KEY2_MASK (0x30U) -#define PUF_KEYRESET_KEY2_SHIFT (4U) -/*! KEY2 - 10: Reset KEY2 shift register. Self clearing. Must be done before loading any new key. - */ -#define PUF_KEYRESET_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK) - -#define PUF_KEYRESET_KEY3_MASK (0xC0U) -#define PUF_KEYRESET_KEY3_SHIFT (6U) -/*! KEY3 - 10: Reset KEY3 shift register. Self clearing. Must be done before loading any new key. - */ -#define PUF_KEYRESET_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK) -/*! @} */ - -/*! @name IDXBLK - */ -/*! @{ */ - -#define PUF_IDXBLK_IDX0_MASK (0x3U) -#define PUF_IDXBLK_IDX0_SHIFT (0U) -/*! IDX0 - Use to block PUF index 0 - */ -#define PUF_IDXBLK_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX0_SHIFT)) & PUF_IDXBLK_IDX0_MASK) - -#define PUF_IDXBLK_IDX1_MASK (0xCU) -#define PUF_IDXBLK_IDX1_SHIFT (2U) -/*! IDX1 - Use to block PUF index 1 - */ -#define PUF_IDXBLK_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX1_SHIFT)) & PUF_IDXBLK_IDX1_MASK) - -#define PUF_IDXBLK_IDX2_MASK (0x30U) -#define PUF_IDXBLK_IDX2_SHIFT (4U) -/*! IDX2 - Use to block PUF index 2 - */ -#define PUF_IDXBLK_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX2_SHIFT)) & PUF_IDXBLK_IDX2_MASK) - -#define PUF_IDXBLK_IDX3_MASK (0xC0U) -#define PUF_IDXBLK_IDX3_SHIFT (6U) -/*! IDX3 - Use to block PUF index 3 - */ -#define PUF_IDXBLK_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX3_SHIFT)) & PUF_IDXBLK_IDX3_MASK) - -#define PUF_IDXBLK_IDX4_MASK (0x300U) -#define PUF_IDXBLK_IDX4_SHIFT (8U) -/*! IDX4 - Use to block PUF index 4 - */ -#define PUF_IDXBLK_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX4_SHIFT)) & PUF_IDXBLK_IDX4_MASK) - -#define PUF_IDXBLK_IDX5_MASK (0xC00U) -#define PUF_IDXBLK_IDX5_SHIFT (10U) -/*! IDX5 - Use to block PUF index 5 - */ -#define PUF_IDXBLK_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX5_SHIFT)) & PUF_IDXBLK_IDX5_MASK) - -#define PUF_IDXBLK_IDX6_MASK (0x3000U) -#define PUF_IDXBLK_IDX6_SHIFT (12U) -/*! IDX6 - Use to block PUF index 6 - */ -#define PUF_IDXBLK_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX6_SHIFT)) & PUF_IDXBLK_IDX6_MASK) - -#define PUF_IDXBLK_IDX7_MASK (0xC000U) -#define PUF_IDXBLK_IDX7_SHIFT (14U) -/*! IDX7 - Use to block PUF index 7 - */ -#define PUF_IDXBLK_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX7_SHIFT)) & PUF_IDXBLK_IDX7_MASK) - -#define PUF_IDXBLK_IDX8_MASK (0x30000U) -#define PUF_IDXBLK_IDX8_SHIFT (16U) -/*! IDX8 - Use to block PUF index 8 - */ -#define PUF_IDXBLK_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX8_SHIFT)) & PUF_IDXBLK_IDX8_MASK) - -#define PUF_IDXBLK_IDX9_MASK (0xC0000U) -#define PUF_IDXBLK_IDX9_SHIFT (18U) -/*! IDX9 - Use to block PUF index 9 - */ -#define PUF_IDXBLK_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX9_SHIFT)) & PUF_IDXBLK_IDX9_MASK) - -#define PUF_IDXBLK_IDX10_MASK (0x300000U) -#define PUF_IDXBLK_IDX10_SHIFT (20U) -/*! IDX10 - Use to block PUF index 10 - */ -#define PUF_IDXBLK_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX10_SHIFT)) & PUF_IDXBLK_IDX10_MASK) - -#define PUF_IDXBLK_IDX11_MASK (0xC00000U) -#define PUF_IDXBLK_IDX11_SHIFT (22U) -/*! IDX11 - Use to block PUF index 11 - */ -#define PUF_IDXBLK_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX11_SHIFT)) & PUF_IDXBLK_IDX11_MASK) - -#define PUF_IDXBLK_IDX12_MASK (0x3000000U) -#define PUF_IDXBLK_IDX12_SHIFT (24U) -/*! IDX12 - Use to block PUF index 12 - */ -#define PUF_IDXBLK_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX12_SHIFT)) & PUF_IDXBLK_IDX12_MASK) - -#define PUF_IDXBLK_IDX13_MASK (0xC000000U) -#define PUF_IDXBLK_IDX13_SHIFT (26U) -/*! IDX13 - Use to block PUF index 13 - */ -#define PUF_IDXBLK_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX13_SHIFT)) & PUF_IDXBLK_IDX13_MASK) - -#define PUF_IDXBLK_IDX14_MASK (0x30000000U) -#define PUF_IDXBLK_IDX14_SHIFT (28U) -/*! IDX14 - Use to block PUF index 14 - */ -#define PUF_IDXBLK_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX14_SHIFT)) & PUF_IDXBLK_IDX14_MASK) - -#define PUF_IDXBLK_IDX15_MASK (0xC0000000U) -#define PUF_IDXBLK_IDX15_SHIFT (30U) -/*! IDX15 - Use to block PUF index 15 - */ -#define PUF_IDXBLK_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX15_SHIFT)) & PUF_IDXBLK_IDX15_MASK) -/*! @} */ - -/*! @name IDXBLK_DP - */ -/*! @{ */ - -#define PUF_IDXBLK_DP_IDX0_MASK (0x3U) -#define PUF_IDXBLK_DP_IDX0_SHIFT (0U) -/*! IDX0 - Use to block PUF index 0 - */ -#define PUF_IDXBLK_DP_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX0_SHIFT)) & PUF_IDXBLK_DP_IDX0_MASK) - -#define PUF_IDXBLK_DP_IDX1_MASK (0xCU) -#define PUF_IDXBLK_DP_IDX1_SHIFT (2U) -/*! IDX1 - Use to block PUF index 1 - */ -#define PUF_IDXBLK_DP_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX1_SHIFT)) & PUF_IDXBLK_DP_IDX1_MASK) - -#define PUF_IDXBLK_DP_IDX2_MASK (0x30U) -#define PUF_IDXBLK_DP_IDX2_SHIFT (4U) -/*! IDX2 - Use to block PUF index 2 - */ -#define PUF_IDXBLK_DP_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX2_SHIFT)) & PUF_IDXBLK_DP_IDX2_MASK) - -#define PUF_IDXBLK_DP_IDX3_MASK (0xC0U) -#define PUF_IDXBLK_DP_IDX3_SHIFT (6U) -/*! IDX3 - Use to block PUF index 3 - */ -#define PUF_IDXBLK_DP_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX3_SHIFT)) & PUF_IDXBLK_DP_IDX3_MASK) - -#define PUF_IDXBLK_DP_IDX4_MASK (0x300U) -#define PUF_IDXBLK_DP_IDX4_SHIFT (8U) -/*! IDX4 - Use to block PUF index 4 - */ -#define PUF_IDXBLK_DP_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX4_SHIFT)) & PUF_IDXBLK_DP_IDX4_MASK) - -#define PUF_IDXBLK_DP_IDX5_MASK (0xC00U) -#define PUF_IDXBLK_DP_IDX5_SHIFT (10U) -/*! IDX5 - Use to block PUF index 5 - */ -#define PUF_IDXBLK_DP_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX5_SHIFT)) & PUF_IDXBLK_DP_IDX5_MASK) - -#define PUF_IDXBLK_DP_IDX6_MASK (0x3000U) -#define PUF_IDXBLK_DP_IDX6_SHIFT (12U) -/*! IDX6 - Use to block PUF index 6 - */ -#define PUF_IDXBLK_DP_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX6_SHIFT)) & PUF_IDXBLK_DP_IDX6_MASK) - -#define PUF_IDXBLK_DP_IDX7_MASK (0xC000U) -#define PUF_IDXBLK_DP_IDX7_SHIFT (14U) -/*! IDX7 - Use to block PUF index 7 - */ -#define PUF_IDXBLK_DP_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX7_SHIFT)) & PUF_IDXBLK_DP_IDX7_MASK) - -#define PUF_IDXBLK_DP_IDX8_MASK (0x30000U) -#define PUF_IDXBLK_DP_IDX8_SHIFT (16U) -/*! IDX8 - Use to block PUF index 8 - */ -#define PUF_IDXBLK_DP_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX8_SHIFT)) & PUF_IDXBLK_DP_IDX8_MASK) - -#define PUF_IDXBLK_DP_IDX9_MASK (0xC0000U) -#define PUF_IDXBLK_DP_IDX9_SHIFT (18U) -/*! IDX9 - Use to block PUF index 9 - */ -#define PUF_IDXBLK_DP_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX9_SHIFT)) & PUF_IDXBLK_DP_IDX9_MASK) - -#define PUF_IDXBLK_DP_IDX10_MASK (0x300000U) -#define PUF_IDXBLK_DP_IDX10_SHIFT (20U) -/*! IDX10 - Use to block PUF index 10 - */ -#define PUF_IDXBLK_DP_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX10_SHIFT)) & PUF_IDXBLK_DP_IDX10_MASK) - -#define PUF_IDXBLK_DP_IDX11_MASK (0xC00000U) -#define PUF_IDXBLK_DP_IDX11_SHIFT (22U) -/*! IDX11 - Use to block PUF index 11 - */ -#define PUF_IDXBLK_DP_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX11_SHIFT)) & PUF_IDXBLK_DP_IDX11_MASK) - -#define PUF_IDXBLK_DP_IDX12_MASK (0x3000000U) -#define PUF_IDXBLK_DP_IDX12_SHIFT (24U) -/*! IDX12 - Use to block PUF index 12 - */ -#define PUF_IDXBLK_DP_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX12_SHIFT)) & PUF_IDXBLK_DP_IDX12_MASK) - -#define PUF_IDXBLK_DP_IDX13_MASK (0xC000000U) -#define PUF_IDXBLK_DP_IDX13_SHIFT (26U) -/*! IDX13 - Use to block PUF index 13 - */ -#define PUF_IDXBLK_DP_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX13_SHIFT)) & PUF_IDXBLK_DP_IDX13_MASK) - -#define PUF_IDXBLK_DP_IDX14_MASK (0x30000000U) -#define PUF_IDXBLK_DP_IDX14_SHIFT (28U) -/*! IDX14 - Use to block PUF index 14 - */ -#define PUF_IDXBLK_DP_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX14_SHIFT)) & PUF_IDXBLK_DP_IDX14_MASK) - -#define PUF_IDXBLK_DP_IDX15_MASK (0xC0000000U) -#define PUF_IDXBLK_DP_IDX15_SHIFT (30U) -/*! IDX15 - Use to block PUF index 15 - */ -#define PUF_IDXBLK_DP_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX15_SHIFT)) & PUF_IDXBLK_DP_IDX15_MASK) -/*! @} */ - -/*! @name KEYMASK - Only reset in case of full IC reset */ -/*! @{ */ - -#define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU) -#define PUF_KEYMASK_KEYMASK_SHIFT (0U) -#define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK) -/*! @} */ - -/* The count of PUF_KEYMASK */ -#define PUF_KEYMASK_COUNT (4U) - -/*! @name IDXBLK_STATUS - Index block status */ -/*! @{ */ - -#define PUF_IDXBLK_STATUS_IDX0_MASK (0x3U) -#define PUF_IDXBLK_STATUS_IDX0_SHIFT (0U) -/*! IDX0 - Status block index 0 - */ -#define PUF_IDXBLK_STATUS_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX0_SHIFT)) & PUF_IDXBLK_STATUS_IDX0_MASK) - -#define PUF_IDXBLK_STATUS_IDX1_MASK (0xCU) -#define PUF_IDXBLK_STATUS_IDX1_SHIFT (2U) -/*! IDX1 - Status block index 1 - */ -#define PUF_IDXBLK_STATUS_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX1_SHIFT)) & PUF_IDXBLK_STATUS_IDX1_MASK) - -#define PUF_IDXBLK_STATUS_IDX2_MASK (0x30U) -#define PUF_IDXBLK_STATUS_IDX2_SHIFT (4U) -/*! IDX2 - Status block index 2 - */ -#define PUF_IDXBLK_STATUS_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX2_SHIFT)) & PUF_IDXBLK_STATUS_IDX2_MASK) - -#define PUF_IDXBLK_STATUS_IDX3_MASK (0xC0U) -#define PUF_IDXBLK_STATUS_IDX3_SHIFT (6U) -/*! IDX3 - Status block index 3 - */ -#define PUF_IDXBLK_STATUS_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX3_SHIFT)) & PUF_IDXBLK_STATUS_IDX3_MASK) - -#define PUF_IDXBLK_STATUS_IDX4_MASK (0x300U) -#define PUF_IDXBLK_STATUS_IDX4_SHIFT (8U) -/*! IDX4 - Status block index 4 - */ -#define PUF_IDXBLK_STATUS_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX4_SHIFT)) & PUF_IDXBLK_STATUS_IDX4_MASK) - -#define PUF_IDXBLK_STATUS_IDX5_MASK (0xC00U) -#define PUF_IDXBLK_STATUS_IDX5_SHIFT (10U) -/*! IDX5 - Status block index 5 - */ -#define PUF_IDXBLK_STATUS_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX5_SHIFT)) & PUF_IDXBLK_STATUS_IDX5_MASK) - -#define PUF_IDXBLK_STATUS_IDX6_MASK (0x3000U) -#define PUF_IDXBLK_STATUS_IDX6_SHIFT (12U) -/*! IDX6 - Status block index 6 - */ -#define PUF_IDXBLK_STATUS_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX6_SHIFT)) & PUF_IDXBLK_STATUS_IDX6_MASK) - -#define PUF_IDXBLK_STATUS_IDX7_MASK (0xC000U) -#define PUF_IDXBLK_STATUS_IDX7_SHIFT (14U) -/*! IDX7 - Status block index 7 - */ -#define PUF_IDXBLK_STATUS_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX7_SHIFT)) & PUF_IDXBLK_STATUS_IDX7_MASK) - -#define PUF_IDXBLK_STATUS_IDX8_MASK (0x30000U) -#define PUF_IDXBLK_STATUS_IDX8_SHIFT (16U) -/*! IDX8 - Status block index 8 - */ -#define PUF_IDXBLK_STATUS_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX8_SHIFT)) & PUF_IDXBLK_STATUS_IDX8_MASK) - -#define PUF_IDXBLK_STATUS_IDX9_MASK (0xC0000U) -#define PUF_IDXBLK_STATUS_IDX9_SHIFT (18U) -/*! IDX9 - Status block index 9 - */ -#define PUF_IDXBLK_STATUS_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX9_SHIFT)) & PUF_IDXBLK_STATUS_IDX9_MASK) - -#define PUF_IDXBLK_STATUS_IDX10_MASK (0x300000U) -#define PUF_IDXBLK_STATUS_IDX10_SHIFT (20U) -/*! IDX10 - Status block index 10 - */ -#define PUF_IDXBLK_STATUS_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX10_SHIFT)) & PUF_IDXBLK_STATUS_IDX10_MASK) - -#define PUF_IDXBLK_STATUS_IDX11_MASK (0xC00000U) -#define PUF_IDXBLK_STATUS_IDX11_SHIFT (22U) -/*! IDX11 - Status block index 11 - */ -#define PUF_IDXBLK_STATUS_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX11_SHIFT)) & PUF_IDXBLK_STATUS_IDX11_MASK) - -#define PUF_IDXBLK_STATUS_IDX12_MASK (0x3000000U) -#define PUF_IDXBLK_STATUS_IDX12_SHIFT (24U) -/*! IDX12 - Status block index 12 - */ -#define PUF_IDXBLK_STATUS_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX12_SHIFT)) & PUF_IDXBLK_STATUS_IDX12_MASK) - -#define PUF_IDXBLK_STATUS_IDX13_MASK (0xC000000U) -#define PUF_IDXBLK_STATUS_IDX13_SHIFT (26U) -/*! IDX13 - Status block index 13 - */ -#define PUF_IDXBLK_STATUS_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX13_SHIFT)) & PUF_IDXBLK_STATUS_IDX13_MASK) - -#define PUF_IDXBLK_STATUS_IDX14_MASK (0x30000000U) -#define PUF_IDXBLK_STATUS_IDX14_SHIFT (28U) -/*! IDX14 - Status block index 14 - */ -#define PUF_IDXBLK_STATUS_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX14_SHIFT)) & PUF_IDXBLK_STATUS_IDX14_MASK) - -#define PUF_IDXBLK_STATUS_IDX15_MASK (0xC0000000U) -#define PUF_IDXBLK_STATUS_IDX15_SHIFT (30U) -/*! IDX15 - Status block index 15 - */ -#define PUF_IDXBLK_STATUS_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX15_SHIFT)) & PUF_IDXBLK_STATUS_IDX15_MASK) -/*! @} */ - -/*! @name SHIFT_STATUS - */ -/*! @{ */ - -#define PUF_SHIFT_STATUS_KEY0_MASK (0xFU) -#define PUF_SHIFT_STATUS_KEY0_SHIFT (0U) -/*! KEY0 - Index counter from key 0 shift register - */ -#define PUF_SHIFT_STATUS_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY0_SHIFT)) & PUF_SHIFT_STATUS_KEY0_MASK) - -#define PUF_SHIFT_STATUS_KEY1_MASK (0xF0U) -#define PUF_SHIFT_STATUS_KEY1_SHIFT (4U) -/*! KEY1 - Index counter from key 1 shift register - */ -#define PUF_SHIFT_STATUS_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY1_SHIFT)) & PUF_SHIFT_STATUS_KEY1_MASK) - -#define PUF_SHIFT_STATUS_KEY2_MASK (0xF00U) -#define PUF_SHIFT_STATUS_KEY2_SHIFT (8U) -/*! KEY2 - Index counter from key 2 shift register - */ -#define PUF_SHIFT_STATUS_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY2_SHIFT)) & PUF_SHIFT_STATUS_KEY2_MASK) - -#define PUF_SHIFT_STATUS_KEY3_MASK (0xF000U) -#define PUF_SHIFT_STATUS_KEY3_SHIFT (12U) -/*! KEY3 - Index counter from key 3 shift register - */ -#define PUF_SHIFT_STATUS_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY3_SHIFT)) & PUF_SHIFT_STATUS_KEY3_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PUF_Register_Masks */ - - -/* PUF - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PUF base address */ - #define PUF_BASE (0x5003B000u) - /** Peripheral PUF base address */ - #define PUF_BASE_NS (0x4003B000u) - /** Peripheral PUF base pointer */ - #define PUF ((PUF_Type *)PUF_BASE) - /** Peripheral PUF base pointer */ - #define PUF_NS ((PUF_Type *)PUF_BASE_NS) - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS { PUF_BASE } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS { PUF } - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS_NS { PUF_BASE_NS } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS_NS { PUF_NS } -#else - /** Peripheral PUF base address */ - #define PUF_BASE (0x4003B000u) - /** Peripheral PUF base pointer */ - #define PUF ((PUF_Type *)PUF_BASE) - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS { PUF_BASE } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS { PUF } -#endif -/** Interrupt vectors for the PUF peripheral type */ -#define PUF_IRQS { PUF_IRQn } - -/*! - * @} - */ /* end of group PUF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PUF_SRAM_CTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_SRAM_CTRL_Peripheral_Access_Layer PUF_SRAM_CTRL Peripheral Access Layer - * @{ - */ - -/** PUF_SRAM_CTRL - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[768]; - __IO uint32_t CFG; /**< Configuration Register, offset: 0x300 */ - __I uint32_t STATUS; /**< Status Register, offset: 0x304 */ - uint8_t RESERVED_1[208]; - __O uint32_t INT_CLR_ENABLE; /**< Interrupt Enable Clear Register, offset: 0x3D8 */ - __O uint32_t INT_SET_ENABLE; /**< Interrupt Enable Set Register, offset: 0x3DC */ - __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x3E0 */ - __I uint32_t INT_ENABLE; /**< Interrupt Enable Register, offset: 0x3E4 */ - __O uint32_t INT_CLR_STATUS; /**< Interrupt Status Clear Register, offset: 0x3E8 */ - __O uint32_t INT_SET_STATUS; /**< Interrupt Status set, offset: 0x3EC */ -} PUF_SRAM_CTRL_Type; - -/* ---------------------------------------------------------------------------- - -- PUF_SRAM_CTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_SRAM_CTRL_Register_Masks PUF_SRAM_CTRL Register Masks - * @{ - */ - -/*! @name CFG - Configuration Register */ -/*! @{ */ - -#define PUF_SRAM_CTRL_CFG_ENABLE_MASK (0x1U) -#define PUF_SRAM_CTRL_CFG_ENABLE_SHIFT (0U) -/*! enable - PUF SRAM Controller activation - */ -#define PUF_SRAM_CTRL_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_CFG_ENABLE_SHIFT)) & PUF_SRAM_CTRL_CFG_ENABLE_MASK) - -#define PUF_SRAM_CTRL_CFG_CKGATING_MASK (0x4U) -#define PUF_SRAM_CTRL_CFG_CKGATING_SHIFT (2U) -/*! ckgating - PUF SRAM Clock Gating control - */ -#define PUF_SRAM_CTRL_CFG_CKGATING(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_CFG_CKGATING_SHIFT)) & PUF_SRAM_CTRL_CFG_CKGATING_MASK) -/*! @} */ - -/*! @name STATUS - Status Register */ -/*! @{ */ - -#define PUF_SRAM_CTRL_STATUS_READY_MASK (0x1U) -#define PUF_SRAM_CTRL_STATUS_READY_SHIFT (0U) -/*! READY - PUF SRAM Controller State - */ -#define PUF_SRAM_CTRL_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_STATUS_READY_SHIFT)) & PUF_SRAM_CTRL_STATUS_READY_MASK) -/*! @} */ - -/*! @name INT_CLR_ENABLE - Interrupt Enable Clear Register */ -/*! @{ */ - -#define PUF_SRAM_CTRL_INT_CLR_ENABLE_READY_MASK (0x1U) -#define PUF_SRAM_CTRL_INT_CLR_ENABLE_READY_SHIFT (0U) -/*! READY - READY Interrupt Enable clear - */ -#define PUF_SRAM_CTRL_INT_CLR_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_CLR_ENABLE_READY_SHIFT)) & PUF_SRAM_CTRL_INT_CLR_ENABLE_READY_MASK) - -#define PUF_SRAM_CTRL_INT_CLR_ENABLE_APB_ERR_MASK (0x2U) -#define PUF_SRAM_CTRL_INT_CLR_ENABLE_APB_ERR_SHIFT (1U) -/*! APB_ERR - APB_ERR Interrupt Enable clear - */ -#define PUF_SRAM_CTRL_INT_CLR_ENABLE_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_CLR_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_CTRL_INT_CLR_ENABLE_APB_ERR_MASK) -/*! @} */ - -/*! @name INT_SET_ENABLE - Interrupt Enable Set Register */ -/*! @{ */ - -#define PUF_SRAM_CTRL_INT_SET_ENABLE_READY_MASK (0x1U) -#define PUF_SRAM_CTRL_INT_SET_ENABLE_READY_SHIFT (0U) -/*! READY - READY Interrupt Enable set - */ -#define PUF_SRAM_CTRL_INT_SET_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_CTRL_INT_SET_ENABLE_READY_MASK) - -#define PUF_SRAM_CTRL_INT_SET_ENABLE_APB_ERR_MASK (0x2U) -#define PUF_SRAM_CTRL_INT_SET_ENABLE_APB_ERR_SHIFT (1U) -/*! APB_ERR - APB_ERR Interrupt Enable set - */ -#define PUF_SRAM_CTRL_INT_SET_ENABLE_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_SET_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_CTRL_INT_SET_ENABLE_APB_ERR_MASK) -/*! @} */ - -/*! @name INT_STATUS - Interrupt Status Register */ -/*! @{ */ - -#define PUF_SRAM_CTRL_INT_STATUS_READY_MASK (0x1U) -#define PUF_SRAM_CTRL_INT_STATUS_READY_SHIFT (0U) -/*! READY - READY Interrupt Status - */ -#define PUF_SRAM_CTRL_INT_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_STATUS_READY_SHIFT)) & PUF_SRAM_CTRL_INT_STATUS_READY_MASK) - -#define PUF_SRAM_CTRL_INT_STATUS_APB_ERR_MASK (0x2U) -#define PUF_SRAM_CTRL_INT_STATUS_APB_ERR_SHIFT (1U) -/*! APB_ERR - APB_ERR Interrupt Status - */ -#define PUF_SRAM_CTRL_INT_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_CTRL_INT_STATUS_APB_ERR_MASK) -/*! @} */ - -/*! @name INT_ENABLE - Interrupt Enable Register */ -/*! @{ */ - -#define PUF_SRAM_CTRL_INT_ENABLE_READY_MASK (0x1U) -#define PUF_SRAM_CTRL_INT_ENABLE_READY_SHIFT (0U) -/*! READY - READY Interrupt Enable - */ -#define PUF_SRAM_CTRL_INT_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_ENABLE_READY_SHIFT)) & PUF_SRAM_CTRL_INT_ENABLE_READY_MASK) - -#define PUF_SRAM_CTRL_INT_ENABLE_APB_ERR_MASK (0x2U) -#define PUF_SRAM_CTRL_INT_ENABLE_APB_ERR_SHIFT (1U) -/*! APB_ERR - APB_ERR Interrupt Enable - */ -#define PUF_SRAM_CTRL_INT_ENABLE_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_CTRL_INT_ENABLE_APB_ERR_MASK) -/*! @} */ - -/*! @name INT_CLR_STATUS - Interrupt Status Clear Register */ -/*! @{ */ - -#define PUF_SRAM_CTRL_INT_CLR_STATUS_READY_MASK (0x1U) -#define PUF_SRAM_CTRL_INT_CLR_STATUS_READY_SHIFT (0U) -/*! READY - READY Interrupt Status clear - */ -#define PUF_SRAM_CTRL_INT_CLR_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_CLR_STATUS_READY_SHIFT)) & PUF_SRAM_CTRL_INT_CLR_STATUS_READY_MASK) - -#define PUF_SRAM_CTRL_INT_CLR_STATUS_APB_ERR_MASK (0x2U) -#define PUF_SRAM_CTRL_INT_CLR_STATUS_APB_ERR_SHIFT (1U) -/*! APB_ERR - APB_ERR Interrupt Status Clear - */ -#define PUF_SRAM_CTRL_INT_CLR_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_CLR_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_CTRL_INT_CLR_STATUS_APB_ERR_MASK) -/*! @} */ - -/*! @name INT_SET_STATUS - Interrupt Status set */ -/*! @{ */ - -#define PUF_SRAM_CTRL_INT_SET_STATUS_READY_MASK (0x1U) -#define PUF_SRAM_CTRL_INT_SET_STATUS_READY_SHIFT (0U) -/*! READY - READY Interrupt Status set - */ -#define PUF_SRAM_CTRL_INT_SET_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_SET_STATUS_READY_SHIFT)) & PUF_SRAM_CTRL_INT_SET_STATUS_READY_MASK) - -#define PUF_SRAM_CTRL_INT_SET_STATUS_APB_ERR_MASK (0x2U) -#define PUF_SRAM_CTRL_INT_SET_STATUS_APB_ERR_SHIFT (1U) -/*! APB_ERR - APB_ERR Interrupt Status Set - */ -#define PUF_SRAM_CTRL_INT_SET_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_SET_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_CTRL_INT_SET_STATUS_APB_ERR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PUF_SRAM_CTRL_Register_Masks */ - - -/* PUF_SRAM_CTRL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PUF_SRAM_CTRL base address */ - #define PUF_SRAM_CTRL_BASE (0x5003B000u) - /** Peripheral PUF_SRAM_CTRL base address */ - #define PUF_SRAM_CTRL_BASE_NS (0x4003B000u) - /** Peripheral PUF_SRAM_CTRL base pointer */ - #define PUF_SRAM_CTRL ((PUF_SRAM_CTRL_Type *)PUF_SRAM_CTRL_BASE) - /** Peripheral PUF_SRAM_CTRL base pointer */ - #define PUF_SRAM_CTRL_NS ((PUF_SRAM_CTRL_Type *)PUF_SRAM_CTRL_BASE_NS) - /** Array initializer of PUF_SRAM_CTRL peripheral base addresses */ - #define PUF_SRAM_CTRL_BASE_ADDRS { PUF_SRAM_CTRL_BASE } - /** Array initializer of PUF_SRAM_CTRL peripheral base pointers */ - #define PUF_SRAM_CTRL_BASE_PTRS { PUF_SRAM_CTRL } - /** Array initializer of PUF_SRAM_CTRL peripheral base addresses */ - #define PUF_SRAM_CTRL_BASE_ADDRS_NS { PUF_SRAM_CTRL_BASE_NS } - /** Array initializer of PUF_SRAM_CTRL peripheral base pointers */ - #define PUF_SRAM_CTRL_BASE_PTRS_NS { PUF_SRAM_CTRL_NS } -#else - /** Peripheral PUF_SRAM_CTRL base address */ - #define PUF_SRAM_CTRL_BASE (0x4003B000u) - /** Peripheral PUF_SRAM_CTRL base pointer */ - #define PUF_SRAM_CTRL ((PUF_SRAM_CTRL_Type *)PUF_SRAM_CTRL_BASE) - /** Array initializer of PUF_SRAM_CTRL peripheral base addresses */ - #define PUF_SRAM_CTRL_BASE_ADDRS { PUF_SRAM_CTRL_BASE } - /** Array initializer of PUF_SRAM_CTRL peripheral base pointers */ - #define PUF_SRAM_CTRL_BASE_PTRS { PUF_SRAM_CTRL } -#endif - -/*! - * @} - */ /* end of group PUF_SRAM_CTRL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RNG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer - * @{ - */ - -/** RNG - Register Layout Typedef */ -typedef struct { - __I uint32_t RANDOM_NUMBER; /**< This register contains a random 32 bit number which is computed on demand, at each time it is read, offset: 0x0 */ - __IO uint32_t ENCRYPTED_NUMBER; /**< This register contains a random 32 bit number which is pre-computed, offset: 0x4 */ - __I uint32_t COUNTER_VAL; /**< , offset: 0x8 */ - __IO uint32_t COUNTER_CFG; /**< , offset: 0xC */ - __IO uint32_t ONLINE_TEST_CFG; /**< , offset: 0x10 */ - __I uint32_t ONLINE_TEST_VAL; /**< , offset: 0x14 */ - __IO uint32_t ENTROPY_INJECT; /**< , offset: 0x18 */ - __IO uint32_t MISC_CFG; /**< , offset: 0x1C */ - uint8_t RESERVED_0[4052]; - __IO uint32_t POWERDOWN; /**< Powerdown mode (standard but certainly useless here), offset: 0xFF4 */ - uint8_t RESERVED_1[4]; - __I uint32_t MODULEID; /**< IP identifier, offset: 0xFFC */ -} RNG_Type; - -/* ---------------------------------------------------------------------------- - -- RNG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RNG_Register_Masks RNG Register Masks - * @{ - */ - -/*! @name RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read */ -/*! @{ */ - -#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK (0xFFFFFFFFU) -#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT (0U) -/*! RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read. - */ -#define RNG_RANDOM_NUMBER_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT)) & RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK) -/*! @} */ - -/*! @name ENCRYPTED_NUMBER - This register contains a random 32 bit number which is pre-computed */ -/*! @{ */ - -#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_MASK (0xFFFFFFFFU) -#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_SHIFT (0U) -/*! ENCRYPTED_NUMBER - This register contains a random 32 bit number which is pre-computed. - */ -#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_SHIFT)) & RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_MASK) -/*! @} */ - -/*! @name COUNTER_VAL - */ -/*! @{ */ - -#define RNG_COUNTER_VAL_CLK_RATIO_MASK (0xFFU) -#define RNG_COUNTER_VAL_CLK_RATIO_SHIFT (0U) -/*! CLK_RATIO - Gives the ratio between the internal clocks frequencies and the register clock - * frequency for evaluation and certification purposes. - */ -#define RNG_COUNTER_VAL_CLK_RATIO(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_CLK_RATIO_SHIFT)) & RNG_COUNTER_VAL_CLK_RATIO_MASK) - -#define RNG_COUNTER_VAL_REFRESH_CNT_MASK (0x3FFF00U) -#define RNG_COUNTER_VAL_REFRESH_CNT_SHIFT (8U) -/*! REFRESH_CNT - Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER. - */ -#define RNG_COUNTER_VAL_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_REFRESH_CNT_SHIFT)) & RNG_COUNTER_VAL_REFRESH_CNT_MASK) -/*! @} */ - -/*! @name COUNTER_CFG - */ -/*! @{ */ - -#define RNG_COUNTER_CFG_MODE_MASK (0x3U) -#define RNG_COUNTER_CFG_MODE_SHIFT (0U) -/*! MODE - 00: disabled 01: update once. - */ -#define RNG_COUNTER_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_MODE_SHIFT)) & RNG_COUNTER_CFG_MODE_MASK) - -#define RNG_COUNTER_CFG_CLOCK_SEL_MASK (0x1CU) -#define RNG_COUNTER_CFG_CLOCK_SEL_SHIFT (2U) -/*! CLOCK_SEL - Selects the internal clock on which to compute statistics. - */ -#define RNG_COUNTER_CFG_CLOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_CLOCK_SEL_SHIFT)) & RNG_COUNTER_CFG_CLOCK_SEL_MASK) - -#define RNG_COUNTER_CFG_SHIFT4X_MASK (0xE0U) -#define RNG_COUNTER_CFG_SHIFT4X_SHIFT (5U) -/*! SHIFT4X - To be used to add precision to clock_ratio and determine 'entropy refill'. - */ -#define RNG_COUNTER_CFG_SHIFT4X(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_SHIFT4X_SHIFT)) & RNG_COUNTER_CFG_SHIFT4X_MASK) -/*! @} */ - -/*! @name ONLINE_TEST_CFG - */ -/*! @{ */ - -#define RNG_ONLINE_TEST_CFG_ACTIVATE_MASK (0x1U) -#define RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT (0U) -/*! ACTIVATE - 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER. - */ -#define RNG_ONLINE_TEST_CFG_ACTIVATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT)) & RNG_ONLINE_TEST_CFG_ACTIVATE_MASK) - -#define RNG_ONLINE_TEST_CFG_DATA_SEL_MASK (0x6U) -#define RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT (1U) -/*! DATA_SEL - Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one - * or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10: - * RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this - * field. - */ -#define RNG_ONLINE_TEST_CFG_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT)) & RNG_ONLINE_TEST_CFG_DATA_SEL_MASK) -/*! @} */ - -/*! @name ONLINE_TEST_VAL - */ -/*! @{ */ - -#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK (0xFU) -#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT (0U) -/*! LIVE_CHI_SQUARED - This value is updated as described in field 'activate'. - */ -#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK) - -#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK (0xF0U) -#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT (4U) -/*! MIN_CHI_SQUARED - This field is reset when 'activate'==0. - */ -#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) - -#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK (0xF00U) -#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT (8U) -/*! MAX_CHI_SQUARED - This field is reset when 'activate'==0. - */ -#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) -/*! @} */ - -/*! @name ENTROPY_INJECT - */ -/*! @{ */ - -#define RNG_ENTROPY_INJECT_ENTROPY_MASK (0xFFFFFFFFU) -#define RNG_ENTROPY_INJECT_ENTROPY_SHIFT (0U) -/*! ENTROPY - Use this register to inject or restore entropy 32 bits at a time. Writing is blocking - * thus see to it to have analog clocks activated. Injection can be usefull to add contribution - * from an external source of entropy, like for example LSBs of an ADC or of a temperature sensor. - * Restore can be usefull to store N random numbers in central memory before going powerdown - * then restore this entropy to RNG IP after power-up. It is useless to inject or restore more than - * 1*(number of RNGs) 32b words consecutively. Recommendation is to inject 1*(number of RNGs) - * words, and possibly later (2*32 clock cycles of slowest analog clock) inject again 1*(number of - * RNGs) words. Then maximum capacity of restoration is reached: about 44 bits per RNG (not to be - * mistaken with maximum capacity of entropy accumulation which is about 100 bits per RNG). You - * can inject less than 32 bits words (let unused bits to 0). Injection cannot degrade overall - * performance due to the fact that some internal PRNGs are excluded on purpose from this external - * action. - */ -#define RNG_ENTROPY_INJECT_ENTROPY(x) (((uint32_t)(((uint32_t)(x)) << RNG_ENTROPY_INJECT_ENTROPY_SHIFT)) & RNG_ENTROPY_INJECT_ENTROPY_MASK) -/*! @} */ - -/*! @name MISC_CFG - */ -/*! @{ */ - -#define RNG_MISC_CFG_AES_RESEED_MASK (0x1U) -#define RNG_MISC_CFG_AES_RESEED_SHIFT (0U) -/*! AES_RESEED - If set, ENCRYPTED_NUMBER generation becomes predictable, provided all secrets and - * current internal state are known: independant from entropy source. - */ -#define RNG_MISC_CFG_AES_RESEED(x) (((uint32_t)(((uint32_t)(x)) << RNG_MISC_CFG_AES_RESEED_SHIFT)) & RNG_MISC_CFG_AES_RESEED_MASK) - -#define RNG_MISC_CFG_AES_DT_CFG_MASK (0x2U) -#define RNG_MISC_CFG_AES_DT_CFG_SHIFT (1U) -/*! AES_DT_CFG - Set this bit to re-seed AES. - */ -#define RNG_MISC_CFG_AES_DT_CFG(x) (((uint32_t)(((uint32_t)(x)) << RNG_MISC_CFG_AES_DT_CFG_SHIFT)) & RNG_MISC_CFG_AES_DT_CFG_MASK) -/*! @} */ - -/*! @name POWERDOWN - Powerdown mode (standard but certainly useless here) */ -/*! @{ */ - -#define RNG_POWERDOWN_SOFT_RESET_MASK (0x1U) -#define RNG_POWERDOWN_SOFT_RESET_SHIFT (0U) -/*! SOFT_RESET - Request softreset that will go low automaticaly after acknowledge from CORE. - */ -#define RNG_POWERDOWN_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_SOFT_RESET_SHIFT)) & RNG_POWERDOWN_SOFT_RESET_MASK) - -#define RNG_POWERDOWN_FORCE_SOFT_RESET_MASK (0x2U) -#define RNG_POWERDOWN_FORCE_SOFT_RESET_SHIFT (1U) -/*! FORCE_SOFT_RESET - When used with softreset it forces CORE_RESETN to low on acknowledge from CORE. - */ -#define RNG_POWERDOWN_FORCE_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_FORCE_SOFT_RESET_SHIFT)) & RNG_POWERDOWN_FORCE_SOFT_RESET_MASK) - -#define RNG_POWERDOWN_POWERDOWN_MASK (0x80000000U) -#define RNG_POWERDOWN_POWERDOWN_SHIFT (31U) -/*! POWERDOWN - When set all accesses to standard registers are blocked. - */ -#define RNG_POWERDOWN_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_POWERDOWN_SHIFT)) & RNG_POWERDOWN_POWERDOWN_MASK) -/*! @} */ - -/*! @name MODULEID - IP identifier */ -/*! @{ */ - -#define RNG_MODULEID_APERTURE_MASK (0xFFU) -#define RNG_MODULEID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture i. - */ -#define RNG_MODULEID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_APERTURE_SHIFT)) & RNG_MODULEID_APERTURE_MASK) - -#define RNG_MODULEID_MIN_REV_MASK (0xF00U) -#define RNG_MODULEID_MIN_REV_SHIFT (8U) -/*! MIN_REV - Minor revision i. - */ -#define RNG_MODULEID_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MIN_REV_SHIFT)) & RNG_MODULEID_MIN_REV_MASK) - -#define RNG_MODULEID_MAJ_REV_MASK (0xF000U) -#define RNG_MODULEID_MAJ_REV_SHIFT (12U) -/*! MAJ_REV - Major revision i. - */ -#define RNG_MODULEID_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MAJ_REV_SHIFT)) & RNG_MODULEID_MAJ_REV_MASK) - -#define RNG_MODULEID_ID_MASK (0xFFFF0000U) -#define RNG_MODULEID_ID_SHIFT (16U) -/*! ID - Identifier. - */ -#define RNG_MODULEID_ID(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_ID_SHIFT)) & RNG_MODULEID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group RNG_Register_Masks */ - - -/* RNG - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral RNG base address */ - #define RNG_BASE (0x5003A000u) - /** Peripheral RNG base address */ - #define RNG_BASE_NS (0x4003A000u) - /** Peripheral RNG base pointer */ - #define RNG ((RNG_Type *)RNG_BASE) - /** Peripheral RNG base pointer */ - #define RNG_NS ((RNG_Type *)RNG_BASE_NS) - /** Array initializer of RNG peripheral base addresses */ - #define RNG_BASE_ADDRS { RNG_BASE } - /** Array initializer of RNG peripheral base pointers */ - #define RNG_BASE_PTRS { RNG } - /** Array initializer of RNG peripheral base addresses */ - #define RNG_BASE_ADDRS_NS { RNG_BASE_NS } - /** Array initializer of RNG peripheral base pointers */ - #define RNG_BASE_PTRS_NS { RNG_NS } -#else - /** Peripheral RNG base address */ - #define RNG_BASE (0x4003A000u) - /** Peripheral RNG base pointer */ - #define RNG ((RNG_Type *)RNG_BASE) - /** Array initializer of RNG peripheral base addresses */ - #define RNG_BASE_ADDRS { RNG_BASE } - /** Array initializer of RNG peripheral base pointers */ - #define RNG_BASE_PTRS { RNG } -#endif - -/*! - * @} - */ /* end of group RNG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RTC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer - * @{ - */ - -/** RTC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ - __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ - __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ - __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ - __I uint32_t SUBSEC; /**< Sub-second counter register, offset: 0x10 */ - uint8_t RESERVED_0[44]; - __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */ -} RTC_Type; - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/*! @name CTRL - RTC control register */ -/*! @{ */ - -#define RTC_CTRL_SWRESET_MASK (0x1U) -#define RTC_CTRL_SWRESET_SHIFT (0U) -/*! SWRESET - Software reset control - * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. - * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value - * except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes - * to set any of the other bits within this register. Do not attempt to write to any bits of this register at - * the same time that the reset bit is being cleared. - */ -#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) - -#define RTC_CTRL_ALARM1HZ_MASK (0x4U) -#define RTC_CTRL_ALARM1HZ_SHIFT (2U) -/*! ALARM1HZ - RTC 1 Hz timer alarm flag status. - * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. - * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt - * request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. - */ -#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) - -#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) -#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) -/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status. - * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. - * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up - * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. - */ -#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) - -#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) -#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) -/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. - * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. - */ -#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) - -#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) -#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) -/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. - * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. - */ -#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) - -#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) -#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) -/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz - * timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). - * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. The 1 kHz RTC timer is enabled. - */ -#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) - -#define RTC_CTRL_RTC_EN_MASK (0x80U) -#define RTC_CTRL_RTC_EN_SHIFT (7U) -/*! RTC_EN - RTC enable. - * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should - * be 0 when writing to load a value in the RTC counter register. - * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate - * operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the - * high-resolution, 1 kHz clock, set bit 6 in this register. - */ -#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) - -#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) -#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) -/*! RTC_OSC_PD - RTC oscillator power-down control. - * 0b0..See RTC_OSC_BYPASS - * 0b1..RTC oscillator is powered-down. - */ -#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) - -#define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) -#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) -/*! RTC_OSC_BYPASS - RTC oscillator bypass control. - * 0b0..The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. - * 0b1..The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. - */ -#define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) - -#define RTC_CTRL_RTC_SUBSEC_ENA_MASK (0x400U) -#define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT (10U) -/*! RTC_SUBSEC_ENA - RTC Sub-second counter control. - * 0b0..The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD - * reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second - * counter, this bit will always read-back as a '0'. - * 0b1..The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first - * one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is - * set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip - * exits deep power-down mode. - */ -#define RTC_CTRL_RTC_SUBSEC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK) -/*! @} */ - -/*! @name MATCH - RTC match register */ -/*! @{ */ - -#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) -#define RTC_MATCH_MATVAL_SHIFT (0U) -/*! MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the - * alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. - */ -#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) -/*! @} */ - -/*! @name COUNT - RTC counter register */ -/*! @{ */ - -#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) -#define RTC_COUNT_VAL_SHIFT (0U) -/*! VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial - * value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC - * Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this - * register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after - * the RTC_EN bit is set. - */ -#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) -/*! @} */ - -/*! @name WAKE - High-resolution/wake-up timer control register */ -/*! @{ */ - -#define RTC_WAKE_VAL_MASK (0xFFFFU) -#define RTC_WAKE_VAL_SHIFT (0U) -/*! VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads - * a start count value into the wake-up timer and initializes a count-down sequence. Do not write - * to this register while counting is in progress. - */ -#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) -/*! @} */ - -/*! @name SUBSEC - Sub-second counter register */ -/*! @{ */ - -#define RTC_SUBSEC_SUBSEC_MASK (0x7FFFU) -#define RTC_SUBSEC_SUBSEC_SHIFT (0U) -/*! SUBSEC - A read reflects the current value of the 32KHz sub-second counter. This counter is - * cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz - * rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This - * counter must be re-enabled after exiting deep power-down mode or after the main RTC module is - * disabled and re-enabled. On modules not equipped with a sub-second counter, this register - * will read-back as all zeroes. - */ -#define RTC_SUBSEC_SUBSEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_SUBSEC_SHIFT)) & RTC_SUBSEC_SUBSEC_MASK) -/*! @} */ - -/*! @name GPREG - General Purpose register */ -/*! @{ */ - -#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU) -#define RTC_GPREG_GPDATA_SHIFT (0U) -/*! GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied. - */ -#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK) -/*! @} */ - -/* The count of RTC_GPREG */ -#define RTC_GPREG_COUNT (8U) - - -/*! - * @} - */ /* end of group RTC_Register_Masks */ - - -/* RTC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral RTC base address */ - #define RTC_BASE (0x5002C000u) - /** Peripheral RTC base address */ - #define RTC_BASE_NS (0x4002C000u) - /** Peripheral RTC base pointer */ - #define RTC ((RTC_Type *)RTC_BASE) - /** Peripheral RTC base pointer */ - #define RTC_NS ((RTC_Type *)RTC_BASE_NS) - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS { RTC_BASE } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS { RTC } - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS_NS { RTC_BASE_NS } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS_NS { RTC_NS } -#else - /** Peripheral RTC base address */ - #define RTC_BASE (0x4002C000u) - /** Peripheral RTC base pointer */ - #define RTC ((RTC_Type *)RTC_BASE) - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS { RTC_BASE } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS { RTC } -#endif -/** Interrupt vectors for the RTC peripheral type */ -#define RTC_IRQS { RTC_IRQn } - -/*! - * @} - */ /* end of group RTC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SCT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer - * @{ - */ - -/** SCT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ - union { /* offset: 0x4 */ - struct { /* offset: 0x4 */ - __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */ - __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */ - } CTRL_ACCESS16BIT; - __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ - }; - union { /* offset: 0x8 */ - struct { /* offset: 0x8 */ - __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */ - __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */ - } LIMIT_ACCESS16BIT; - __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ - }; - union { /* offset: 0xC */ - struct { /* offset: 0xC */ - __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */ - __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */ - } HALT_ACCESS16BIT; - __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ - }; - union { /* offset: 0x10 */ - struct { /* offset: 0x10 */ - __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */ - __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */ - } STOP_ACCESS16BIT; - __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ - }; - union { /* offset: 0x14 */ - struct { /* offset: 0x14 */ - __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */ - __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */ - } START_ACCESS16BIT; - __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ - }; - uint8_t RESERVED_0[40]; - union { /* offset: 0x40 */ - struct { /* offset: 0x40 */ - __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */ - __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */ - } COUNT_ACCESS16BIT; - __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ - }; - union { /* offset: 0x44 */ - struct { /* offset: 0x44 */ - __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */ - __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */ - } STATE_ACCESS16BIT; - __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ - }; - __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ - union { /* offset: 0x4C */ - struct { /* offset: 0x4C */ - __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */ - __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */ - } REGMODE_ACCESS16BIT; - __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ - }; - __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ - __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ - __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ - __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */ - __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */ - uint8_t RESERVED_1[140]; - __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ - __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ - __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ - __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ - union { /* offset: 0x100 */ - union { /* offset: 0x100, array step: 0x4 */ - struct { /* offset: 0x100, array step: 0x4 */ - __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */ - __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */ - } CAP_ACCESS16BIT[16]; - __IO uint32_t CAP[16]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ - }; - union { /* offset: 0x100, array step: 0x4 */ - struct { /* offset: 0x100, array step: 0x4 */ - __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */ - __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */ - } MATCH_ACCESS16BIT[16]; - __IO uint32_t MATCH[16]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ - }; - }; - uint8_t RESERVED_2[192]; - union { /* offset: 0x200 */ - union { /* offset: 0x200, array step: 0x4 */ - struct { /* offset: 0x200, array step: 0x4 */ - __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */ - __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */ - } CAPCTRL_ACCESS16BIT[16]; - __IO uint32_t CAPCTRL[16]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ - }; - union { /* offset: 0x200, array step: 0x4 */ - struct { /* offset: 0x200, array step: 0x4 */ - __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */ - __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */ - } MATCHREL_ACCESS16BIT[16]; - __IO uint32_t MATCHREL[16]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ - }; - }; - uint8_t RESERVED_3[192]; - struct { /* offset: 0x300, array step: 0x8 */ - __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ - __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ - } EV[16]; - uint8_t RESERVED_4[384]; - struct { /* offset: 0x500, array step: 0x8 */ - __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ - __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ - } OUT[10]; -} SCT_Type; - -/* ---------------------------------------------------------------------------- - -- SCT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Register_Masks SCT Register Masks - * @{ - */ - -/*! @name CONFIG - SCT configuration register */ -/*! @{ */ - -#define SCT_CONFIG_UNIFY_MASK (0x1U) -#define SCT_CONFIG_UNIFY_SHIFT (0U) -/*! UNIFY - SCT operation - * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. - * 0b1..The SCT operates as a unified 32-bit counter. - */ -#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) - -#define SCT_CONFIG_CLKMODE_MASK (0x6U) -#define SCT_CONFIG_CLKMODE_SHIFT (1U) -/*! CLKMODE - SCT clock mode - * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. - * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are - * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The - * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the - * high-performance, sampled-clock mode. - * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the - * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the - * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. - * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL - * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system - * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than - * the system clock. - */ -#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) - -#define SCT_CONFIG_CKSEL_MASK (0x78U) -#define SCT_CONFIG_CKSEL_SHIFT (3U) -/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent - * on the CLKMODE bit selection in this register. - * 0b0000..Rising edges on input 0. - * 0b0001..Falling edges on input 0. - * 0b0010..Rising edges on input 1. - * 0b0011..Falling edges on input 1. - * 0b0100..Rising edges on input 2. - * 0b0101..Falling edges on input 2. - * 0b0110..Rising edges on input 3. - * 0b0111..Falling edges on input 3. - * 0b1000..Rising edges on input 4. - * 0b1001..Falling edges on input 4. - * 0b1010..Rising edges on input 5. - * 0b1011..Falling edges on input 5. - * 0b1100..Rising edges on input 6. - * 0b1101..Falling edges on input 6. - * 0b1110..Rising edges on input 7. - * 0b1111..Falling edges on input 7. - */ -#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) - -#define SCT_CONFIG_NORELOAD_L_MASK (0x80U) -#define SCT_CONFIG_NORELOAD_L_SHIFT (7U) -/*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their - * respective reload registers. Setting this bit eliminates the need to write to the reload - * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any - * time. This bit applies to both the higher and lower registers when the UNIFY bit is set. - */ -#define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK) - -#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) -#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) -/*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their - * respective reload registers. Setting this bit eliminates the need to write to the reload - * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at - * any time. This bit is not used when the UNIFY bit is set. - */ -#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) - -#define SCT_CONFIG_INSYNC_MASK (0x1E00U) -#define SCT_CONFIG_INSYNC_SHIFT (9U) -/*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all - * other bits are reserved. A 1 in one of these bits subjects the corresponding input to - * synchronization to the SCT clock, before it is used to create an event. If an input is known to - * already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: - * The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input - * clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. - * It does not apply to the clock input specified in the CKSEL field. - */ -#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) - -#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) -#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) -/*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto - * LIMIT condition without the need to define an associated event. As with any LIMIT event, this - * automatic limit causes the counter to be cleared to zero in unidirectional mode or to change - * the direction of count in bi-directional mode. Software can write to set or clear this bit at - * any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. - */ -#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) - -#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) -#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) -/*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a - * de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, - * this automatic limit causes the counter to be cleared to zero in unidirectional mode or to - * change the direction of count in bi-directional mode. Software can write to set or clear this bit - * at any time. This bit is not used when the UNIFY bit is set. - */ -#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) -/*! @} */ - -/*! @name CTRLL - SCT_CTRLL register */ -/*! @{ */ - -#define SCT_CTRLL_DOWN_L_MASK (0x1U) -#define SCT_CTRLL_DOWN_L_SHIFT (0U) -/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit - * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit - * when the counter is counting down and a limit condition occurs or when the counter reaches 0. - */ -#define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK) - -#define SCT_CTRLL_STOP_L_MASK (0x2U) -#define SCT_CTRLL_STOP_L_SHIFT (1U) -/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events - * related to the counter can occur. If a designated start event occurs, this bit is cleared and - * counting resumes. - */ -#define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK) - -#define SCT_CTRLL_HALT_L_MASK (0x4U) -#define SCT_CTRLL_HALT_L_SHIFT (2U) -/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A - * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to - * remove the halt condition while keeping the SCT in the stop condition (not running) with a - * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, - * only software can clear this bit to restore counter operation. This bit is set on reset. - */ -#define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK) - -#define SCT_CTRLL_CLRCTR_L_MASK (0x8U) -#define SCT_CTRLL_CLRCTR_L_SHIFT (3U) -/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. - */ -#define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK) - -#define SCT_CTRLL_BIDIR_L_MASK (0x10U) -#define SCT_CTRLL_BIDIR_L_SHIFT (4U) -/*! BIDIR_L - L or unified counter direction select - * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. - * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK) - -#define SCT_CTRLL_PRE_L_MASK (0x1FE0U) -#define SCT_CTRLL_PRE_L_SHIFT (5U) -/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified - * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. - * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - */ -#define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK) -/*! @} */ - -/*! @name CTRLH - SCT_CTRLH register */ -/*! @{ */ - -#define SCT_CTRLH_DOWN_H_MASK (0x1U) -#define SCT_CTRLH_DOWN_H_SHIFT (0U) -/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the - * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit - * when the counter is counting down and a limit condition occurs or when the counter reaches 0. - */ -#define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK) - -#define SCT_CTRLH_STOP_H_MASK (0x2U) -#define SCT_CTRLH_STOP_H_SHIFT (1U) -/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to - * the counter can occur. If such an event matches the mask in the Start register, this bit is - * cleared and counting resumes. - */ -#define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK) - -#define SCT_CTRLH_HALT_H_MASK (0x4U) -#define SCT_CTRLH_HALT_H_SHIFT (2U) -/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets - * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the - * halt condition while keeping the SCT in the stop condition (not running) with a single write to - * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit - * can only be cleared by software to restore counter operation. This bit is set on reset. - */ -#define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK) - -#define SCT_CTRLH_CLRCTR_H_MASK (0x8U) -#define SCT_CTRLH_CLRCTR_H_SHIFT (3U) -/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. - */ -#define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK) - -#define SCT_CTRLH_BIDIR_H_MASK (0x10U) -#define SCT_CTRLH_BIDIR_H_SHIFT (4U) -/*! BIDIR_H - Direction select - * 0b0..The H counter counts up to its limit condition, then is cleared to zero. - * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK) - -#define SCT_CTRLH_PRE_H_MASK (0x1FE0U) -#define SCT_CTRLH_PRE_H_SHIFT (5U) -/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. - * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the - * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - */ -#define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK) -/*! @} */ - -/*! @name CTRL - SCT control register */ -/*! @{ */ - -#define SCT_CTRL_DOWN_L_MASK (0x1U) -#define SCT_CTRL_DOWN_L_SHIFT (0U) -/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit - * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit - * when the counter is counting down and a limit condition occurs or when the counter reaches 0. - */ -#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) - -#define SCT_CTRL_STOP_L_MASK (0x2U) -#define SCT_CTRL_STOP_L_SHIFT (1U) -/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events - * related to the counter can occur. If a designated start event occurs, this bit is cleared and - * counting resumes. - */ -#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) - -#define SCT_CTRL_HALT_L_MASK (0x4U) -#define SCT_CTRL_HALT_L_SHIFT (2U) -/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A - * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to - * remove the halt condition while keeping the SCT in the stop condition (not running) with a - * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, - * only software can clear this bit to restore counter operation. This bit is set on reset. - */ -#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) - -#define SCT_CTRL_CLRCTR_L_MASK (0x8U) -#define SCT_CTRL_CLRCTR_L_SHIFT (3U) -/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. - */ -#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) - -#define SCT_CTRL_BIDIR_L_MASK (0x10U) -#define SCT_CTRL_BIDIR_L_SHIFT (4U) -/*! BIDIR_L - L or unified counter direction select - * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. - * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) - -#define SCT_CTRL_PRE_L_MASK (0x1FE0U) -#define SCT_CTRL_PRE_L_SHIFT (5U) -/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified - * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. - * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - */ -#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) - -#define SCT_CTRL_DOWN_H_MASK (0x10000U) -#define SCT_CTRL_DOWN_H_SHIFT (16U) -/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the - * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit - * when the counter is counting down and a limit condition occurs or when the counter reaches 0. - */ -#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) - -#define SCT_CTRL_STOP_H_MASK (0x20000U) -#define SCT_CTRL_STOP_H_SHIFT (17U) -/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to - * the counter can occur. If such an event matches the mask in the Start register, this bit is - * cleared and counting resumes. - */ -#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) - -#define SCT_CTRL_HALT_H_MASK (0x40000U) -#define SCT_CTRL_HALT_H_SHIFT (18U) -/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets - * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the - * halt condition while keeping the SCT in the stop condition (not running) with a single write to - * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit - * can only be cleared by software to restore counter operation. This bit is set on reset. - */ -#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) - -#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) -#define SCT_CTRL_CLRCTR_H_SHIFT (19U) -/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. - */ -#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) - -#define SCT_CTRL_BIDIR_H_MASK (0x100000U) -#define SCT_CTRL_BIDIR_H_SHIFT (20U) -/*! BIDIR_H - Direction select - * 0b0..The H counter counts up to its limit condition, then is cleared to zero. - * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) - -#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) -#define SCT_CTRL_PRE_H_SHIFT (21U) -/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. - * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the - * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - */ -#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) -/*! @} */ - -/*! @name LIMITL - SCT_LIMITL register */ -/*! @{ */ - -#define SCT_LIMITL_LIMITL_MASK (0xFFFFU) -#define SCT_LIMITL_LIMITL_SHIFT (0U) -#define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK) -/*! @} */ - -/*! @name LIMITH - SCT_LIMITH register */ -/*! @{ */ - -#define SCT_LIMITH_LIMITH_MASK (0xFFFFU) -#define SCT_LIMITH_LIMITH_SHIFT (0U) -#define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK) -/*! @} */ - -/*! @name LIMIT - SCT limit event select register */ -/*! @{ */ - -#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) -#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) -/*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter - * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) - -#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) -#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) -/*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit - * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) -/*! @} */ - -/*! @name HALTL - SCT_HALTL register */ -/*! @{ */ - -#define SCT_HALTL_HALTL_MASK (0xFFFFU) -#define SCT_HALTL_HALTL_SHIFT (0U) -#define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK) -/*! @} */ - -/*! @name HALTH - SCT_HALTH register */ -/*! @{ */ - -#define SCT_HALTH_HALTH_MASK (0xFFFFU) -#define SCT_HALTH_HALTH_SHIFT (0U) -#define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK) -/*! @} */ - -/*! @name HALT - SCT halt event select register */ -/*! @{ */ - -#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) -#define SCT_HALT_HALTMSK_L_SHIFT (0U) -/*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, - * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) - -#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) -#define SCT_HALT_HALTMSK_H_SHIFT (16U) -/*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, - * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) -/*! @} */ - -/*! @name STOPL - SCT_STOPL register */ -/*! @{ */ - -#define SCT_STOPL_STOPL_MASK (0xFFFFU) -#define SCT_STOPL_STOPL_SHIFT (0U) -#define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK) -/*! @} */ - -/*! @name STOPH - SCT_STOPH register */ -/*! @{ */ - -#define SCT_STOPH_STOPH_MASK (0xFFFFU) -#define SCT_STOPH_STOPH_SHIFT (0U) -#define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK) -/*! @} */ - -/*! @name STOP - SCT stop event select register */ -/*! @{ */ - -#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) -#define SCT_STOP_STOPMSK_L_SHIFT (0U) -/*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, - * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) - -#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) -#define SCT_STOP_STOPMSK_H_SHIFT (16U) -/*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, - * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) -/*! @} */ - -/*! @name STARTL - SCT_STARTL register */ -/*! @{ */ - -#define SCT_STARTL_STARTL_MASK (0xFFFFU) -#define SCT_STARTL_STARTL_SHIFT (0U) -#define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK) -/*! @} */ - -/*! @name STARTH - SCT_STARTH register */ -/*! @{ */ - -#define SCT_STARTH_STARTH_MASK (0xFFFFU) -#define SCT_STARTH_STARTH_SHIFT (0U) -#define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK) -/*! @} */ - -/*! @name START - SCT start event select register */ -/*! @{ */ - -#define SCT_START_STARTMSK_L_MASK (0xFFFFU) -#define SCT_START_STARTMSK_L_SHIFT (0U) -/*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit - * 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) - -#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) -#define SCT_START_STARTMSK_H_SHIFT (16U) -/*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit - * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) -/*! @} */ - -/*! @name COUNTL - SCT_COUNTL register */ -/*! @{ */ - -#define SCT_COUNTL_COUNTL_MASK (0xFFFFU) -#define SCT_COUNTL_COUNTL_SHIFT (0U) -#define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK) -/*! @} */ - -/*! @name COUNTH - SCT_COUNTH register */ -/*! @{ */ - -#define SCT_COUNTH_COUNTH_MASK (0xFFFFU) -#define SCT_COUNTH_COUNTH_SHIFT (0U) -#define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK) -/*! @} */ - -/*! @name COUNT - SCT counter register */ -/*! @{ */ - -#define SCT_COUNT_CTR_L_MASK (0xFFFFU) -#define SCT_COUNT_CTR_L_SHIFT (0U) -/*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write - * the lower 16 bits of the 32-bit unified counter. - */ -#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) - -#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) -#define SCT_COUNT_CTR_H_SHIFT (16U) -/*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write - * the upper 16 bits of the 32-bit unified counter. - */ -#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) -/*! @} */ - -/*! @name STATEL - SCT_STATEL register */ -/*! @{ */ - -#define SCT_STATEL_STATEL_MASK (0xFFFFU) -#define SCT_STATEL_STATEL_SHIFT (0U) -#define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK) -/*! @} */ - -/*! @name STATEH - SCT_STATEH register */ -/*! @{ */ - -#define SCT_STATEH_STATEH_MASK (0xFFFFU) -#define SCT_STATEH_STATEH_SHIFT (0U) -#define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK) -/*! @} */ - -/*! @name STATE - SCT state register */ -/*! @{ */ - -#define SCT_STATE_STATE_L_MASK (0x1FU) -#define SCT_STATE_STATE_L_SHIFT (0U) -/*! STATE_L - State variable. - */ -#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) - -#define SCT_STATE_STATE_H_MASK (0x1F0000U) -#define SCT_STATE_STATE_H_SHIFT (16U) -/*! STATE_H - State variable. - */ -#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) -/*! @} */ - -/*! @name INPUT - SCT input register */ -/*! @{ */ - -#define SCT_INPUT_AIN0_MASK (0x1U) -#define SCT_INPUT_AIN0_SHIFT (0U) -/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) - -#define SCT_INPUT_AIN1_MASK (0x2U) -#define SCT_INPUT_AIN1_SHIFT (1U) -/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) - -#define SCT_INPUT_AIN2_MASK (0x4U) -#define SCT_INPUT_AIN2_SHIFT (2U) -/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) - -#define SCT_INPUT_AIN3_MASK (0x8U) -#define SCT_INPUT_AIN3_SHIFT (3U) -/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) - -#define SCT_INPUT_AIN4_MASK (0x10U) -#define SCT_INPUT_AIN4_SHIFT (4U) -/*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) - -#define SCT_INPUT_AIN5_MASK (0x20U) -#define SCT_INPUT_AIN5_SHIFT (5U) -/*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) - -#define SCT_INPUT_AIN6_MASK (0x40U) -#define SCT_INPUT_AIN6_SHIFT (6U) -/*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) - -#define SCT_INPUT_AIN7_MASK (0x80U) -#define SCT_INPUT_AIN7_SHIFT (7U) -/*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) - -#define SCT_INPUT_AIN8_MASK (0x100U) -#define SCT_INPUT_AIN8_SHIFT (8U) -/*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) - -#define SCT_INPUT_AIN9_MASK (0x200U) -#define SCT_INPUT_AIN9_SHIFT (9U) -/*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) - -#define SCT_INPUT_AIN10_MASK (0x400U) -#define SCT_INPUT_AIN10_SHIFT (10U) -/*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) - -#define SCT_INPUT_AIN11_MASK (0x800U) -#define SCT_INPUT_AIN11_SHIFT (11U) -/*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) - -#define SCT_INPUT_AIN12_MASK (0x1000U) -#define SCT_INPUT_AIN12_SHIFT (12U) -/*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) - -#define SCT_INPUT_AIN13_MASK (0x2000U) -#define SCT_INPUT_AIN13_SHIFT (13U) -/*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) - -#define SCT_INPUT_AIN14_MASK (0x4000U) -#define SCT_INPUT_AIN14_SHIFT (14U) -/*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) - -#define SCT_INPUT_AIN15_MASK (0x8000U) -#define SCT_INPUT_AIN15_SHIFT (15U) -/*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) - -#define SCT_INPUT_SIN0_MASK (0x10000U) -#define SCT_INPUT_SIN0_SHIFT (16U) -/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) - -#define SCT_INPUT_SIN1_MASK (0x20000U) -#define SCT_INPUT_SIN1_SHIFT (17U) -/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) - -#define SCT_INPUT_SIN2_MASK (0x40000U) -#define SCT_INPUT_SIN2_SHIFT (18U) -/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) - -#define SCT_INPUT_SIN3_MASK (0x80000U) -#define SCT_INPUT_SIN3_SHIFT (19U) -/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) - -#define SCT_INPUT_SIN4_MASK (0x100000U) -#define SCT_INPUT_SIN4_SHIFT (20U) -/*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) - -#define SCT_INPUT_SIN5_MASK (0x200000U) -#define SCT_INPUT_SIN5_SHIFT (21U) -/*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) - -#define SCT_INPUT_SIN6_MASK (0x400000U) -#define SCT_INPUT_SIN6_SHIFT (22U) -/*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) - -#define SCT_INPUT_SIN7_MASK (0x800000U) -#define SCT_INPUT_SIN7_SHIFT (23U) -/*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) - -#define SCT_INPUT_SIN8_MASK (0x1000000U) -#define SCT_INPUT_SIN8_SHIFT (24U) -/*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) - -#define SCT_INPUT_SIN9_MASK (0x2000000U) -#define SCT_INPUT_SIN9_SHIFT (25U) -/*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) - -#define SCT_INPUT_SIN10_MASK (0x4000000U) -#define SCT_INPUT_SIN10_SHIFT (26U) -/*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) - -#define SCT_INPUT_SIN11_MASK (0x8000000U) -#define SCT_INPUT_SIN11_SHIFT (27U) -/*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) - -#define SCT_INPUT_SIN12_MASK (0x10000000U) -#define SCT_INPUT_SIN12_SHIFT (28U) -/*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) - -#define SCT_INPUT_SIN13_MASK (0x20000000U) -#define SCT_INPUT_SIN13_SHIFT (29U) -/*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) - -#define SCT_INPUT_SIN14_MASK (0x40000000U) -#define SCT_INPUT_SIN14_SHIFT (30U) -/*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) - -#define SCT_INPUT_SIN15_MASK (0x80000000U) -#define SCT_INPUT_SIN15_SHIFT (31U) -/*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) -/*! @} */ - -/*! @name REGMODEL - SCT_REGMODEL register */ -/*! @{ */ - -#define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU) -#define SCT_REGMODEL_REGMODEL_SHIFT (0U) -#define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK) -/*! @} */ - -/*! @name REGMODEH - SCT_REGMODEH register */ -/*! @{ */ - -#define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU) -#define SCT_REGMODEH_REGMODEH_SHIFT (0U) -#define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK) -/*! @} */ - -/*! @name REGMODE - SCT match/capture mode register */ -/*! @{ */ - -#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) -#define SCT_REGMODE_REGMOD_L_SHIFT (0U) -/*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, - * etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as - * match register. 1 = register operates as capture register. - */ -#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) - -#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) -#define SCT_REGMODE_REGMOD_H_SHIFT (16U) -/*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit - * 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as - * match registers. 1 = register operates as capture registers. - */ -#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) -/*! @} */ - -/*! @name OUTPUT - SCT output register */ -/*! @{ */ - -#define SCT_OUTPUT_OUT_MASK (0xFFFFU) -#define SCT_OUTPUT_OUT_SHIFT (0U) -/*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the - * corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of - * outputs in this SCT. - */ -#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) -/*! @} */ - -/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ -/*! @{ */ - -#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) -#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) -/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) -#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) -/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) -#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) -/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) -#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) -/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) -#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) -/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) -#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) -/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) -#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) -/*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) -#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) -/*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) -#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) -/*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) -#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) -/*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) -#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) -/*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) -#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) -/*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) -/*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) -/*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) -/*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) -/*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) -/*! @} */ - -/*! @name RES - SCT conflict resolution register */ -/*! @{ */ - -#define SCT_RES_O0RES_MASK (0x3U) -#define SCT_RES_O0RES_SHIFT (0U) -/*! O0RES - Effect of simultaneous set and clear on output 0. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR0 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) - -#define SCT_RES_O1RES_MASK (0xCU) -#define SCT_RES_O1RES_SHIFT (2U) -/*! O1RES - Effect of simultaneous set and clear on output 1. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR1 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) - -#define SCT_RES_O2RES_MASK (0x30U) -#define SCT_RES_O2RES_SHIFT (4U) -/*! O2RES - Effect of simultaneous set and clear on output 2. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output n (or set based on the SETCLR2 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) - -#define SCT_RES_O3RES_MASK (0xC0U) -#define SCT_RES_O3RES_SHIFT (6U) -/*! O3RES - Effect of simultaneous set and clear on output 3. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR3 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) - -#define SCT_RES_O4RES_MASK (0x300U) -#define SCT_RES_O4RES_SHIFT (8U) -/*! O4RES - Effect of simultaneous set and clear on output 4. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR4 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) - -#define SCT_RES_O5RES_MASK (0xC00U) -#define SCT_RES_O5RES_SHIFT (10U) -/*! O5RES - Effect of simultaneous set and clear on output 5. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR5 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) - -#define SCT_RES_O6RES_MASK (0x3000U) -#define SCT_RES_O6RES_SHIFT (12U) -/*! O6RES - Effect of simultaneous set and clear on output 6. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR6 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) - -#define SCT_RES_O7RES_MASK (0xC000U) -#define SCT_RES_O7RES_SHIFT (14U) -/*! O7RES - Effect of simultaneous set and clear on output 7. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output n (or set based on the SETCLR7 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) - -#define SCT_RES_O8RES_MASK (0x30000U) -#define SCT_RES_O8RES_SHIFT (16U) -/*! O8RES - Effect of simultaneous set and clear on output 8. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR8 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) - -#define SCT_RES_O9RES_MASK (0xC0000U) -#define SCT_RES_O9RES_SHIFT (18U) -/*! O9RES - Effect of simultaneous set and clear on output 9. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR9 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) - -#define SCT_RES_O10RES_MASK (0x300000U) -#define SCT_RES_O10RES_SHIFT (20U) -/*! O10RES - Effect of simultaneous set and clear on output 10. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR10 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) - -#define SCT_RES_O11RES_MASK (0xC00000U) -#define SCT_RES_O11RES_SHIFT (22U) -/*! O11RES - Effect of simultaneous set and clear on output 11. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR11 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) - -#define SCT_RES_O12RES_MASK (0x3000000U) -#define SCT_RES_O12RES_SHIFT (24U) -/*! O12RES - Effect of simultaneous set and clear on output 12. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR12 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) - -#define SCT_RES_O13RES_MASK (0xC000000U) -#define SCT_RES_O13RES_SHIFT (26U) -/*! O13RES - Effect of simultaneous set and clear on output 13. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR13 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) - -#define SCT_RES_O14RES_MASK (0x30000000U) -#define SCT_RES_O14RES_SHIFT (28U) -/*! O14RES - Effect of simultaneous set and clear on output 14. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR14 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) - -#define SCT_RES_O15RES_MASK (0xC0000000U) -#define SCT_RES_O15RES_SHIFT (30U) -/*! O15RES - Effect of simultaneous set and clear on output 15. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR15 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) -/*! @} */ - -/*! @name DMAREQ0 - SCT DMA request 0 register */ -/*! @{ */ - -#define SCT_DMAREQ0_DEV_0_MASK (0xFFFFU) -#define SCT_DMAREQ0_DEV_0_SHIFT (0U) -/*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, - * etc.). The number of bits = number of events in this SCT. - */ -#define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK) - -#define SCT_DMAREQ0_DRL0_MASK (0x40000000U) -#define SCT_DMAREQ0_DRL0_SHIFT (30U) -/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. - */ -#define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK) - -#define SCT_DMAREQ0_DRQ0_MASK (0x80000000U) -#define SCT_DMAREQ0_DRQ0_SHIFT (31U) -/*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA - * channel is enabled and properly set up, it is unlikely that software will see this flag, it will - * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA - * setup. - */ -#define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK) -/*! @} */ - -/*! @name DMAREQ1 - SCT DMA request 1 register */ -/*! @{ */ - -#define SCT_DMAREQ1_DEV_1_MASK (0xFFFFU) -#define SCT_DMAREQ1_DEV_1_SHIFT (0U) -/*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, - * etc.). The number of bits = number of events in this SCT. - */ -#define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK) - -#define SCT_DMAREQ1_DRL1_MASK (0x40000000U) -#define SCT_DMAREQ1_DRL1_SHIFT (30U) -/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. - */ -#define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK) - -#define SCT_DMAREQ1_DRQ1_MASK (0x80000000U) -#define SCT_DMAREQ1_DRQ1_SHIFT (31U) -/*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA - * channel is enabled and properly set up, it is unlikely that software will see this flag, it will - * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA - * setup. - */ -#define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK) -/*! @} */ - -/*! @name EVEN - SCT event interrupt enable register */ -/*! @{ */ - -#define SCT_EVEN_IEN_MASK (0xFFFFU) -#define SCT_EVEN_IEN_SHIFT (0U) -/*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are - * both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in - * this SCT. - */ -#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) -/*! @} */ - -/*! @name EVFLAG - SCT event flag register */ -/*! @{ */ - -#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) -#define SCT_EVFLAG_FLAG_SHIFT (0U) -/*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit - * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) -/*! @} */ - -/*! @name CONEN - SCT conflict interrupt enable register */ -/*! @{ */ - -#define SCT_CONEN_NCEN_MASK (0xFFFFU) -#define SCT_CONEN_NCEN_SHIFT (0U) -/*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag - * register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of - * outputs in this SCT. - */ -#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) -/*! @} */ - -/*! @name CONFLAG - SCT conflict flag register */ -/*! @{ */ - -#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) -#define SCT_CONFLAG_NCFLAG_SHIFT (0U) -/*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was - * last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = - * number of outputs in this SCT. - */ -#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) - -#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) -#define SCT_CONFLAG_BUSERRL_SHIFT (30U) -/*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE - * L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write - * to certain L and H registers can be half successful and half unsuccessful. - */ -#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) - -#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) -#define SCT_CONFLAG_BUSERRH_SHIFT (31U) -/*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or - * the Output register when the H counter was not halted. - */ -#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) -/*! @} */ - -/*! @name CAPL - SCT_CAPL register */ -/*! @{ */ - -#define SCT_CAPL_CAPL_MASK (0xFFFFU) -#define SCT_CAPL_CAPL_SHIFT (0U) -#define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK) -/*! @} */ - -/* The count of SCT_CAPL */ -#define SCT_CAPL_COUNT (16U) - -/*! @name CAPH - SCT_CAPH register */ -/*! @{ */ - -#define SCT_CAPH_CAPH_MASK (0xFFFFU) -#define SCT_CAPH_CAPH_SHIFT (0U) -#define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK) -/*! @} */ - -/* The count of SCT_CAPH */ -#define SCT_CAPH_COUNT (16U) - -/*! @name CAP - SCT capture register of capture channel */ -/*! @{ */ - -#define SCT_CAP_CAPn_L_MASK (0xFFFFU) -#define SCT_CAP_CAPn_L_SHIFT (0U) -/*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. - * When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last - * captured. - */ -#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK) - -#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U) -#define SCT_CAP_CAPn_H_SHIFT (16U) -/*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. - * When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last - * captured. - */ -#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK) -/*! @} */ - -/* The count of SCT_CAP */ -#define SCT_CAP_COUNT (16U) - -/*! @name MATCHL - SCT_MATCHL register */ -/*! @{ */ - -#define SCT_MATCHL_MATCHL_MASK (0xFFFFU) -#define SCT_MATCHL_MATCHL_SHIFT (0U) -#define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK) -/*! @} */ - -/* The count of SCT_MATCHL */ -#define SCT_MATCHL_COUNT (16U) - -/*! @name MATCHH - SCT_MATCHH register */ -/*! @{ */ - -#define SCT_MATCHH_MATCHH_MASK (0xFFFFU) -#define SCT_MATCHH_MATCHH_SHIFT (0U) -#define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK) -/*! @} */ - -/* The count of SCT_MATCHH */ -#define SCT_MATCHH_COUNT (16U) - -/*! @name MATCH - SCT match value register of match channels */ -/*! @{ */ - -#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU) -#define SCT_MATCH_MATCHn_L_SHIFT (0U) -/*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When - * UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified - * counter. - */ -#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK) - -#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U) -#define SCT_MATCH_MATCHn_H_SHIFT (16U) -/*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When - * UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified - * counter. - */ -#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK) -/*! @} */ - -/* The count of SCT_MATCH */ -#define SCT_MATCH_COUNT (16U) - -/*! @name CAPCTRLL - SCT_CAPCTRLL register */ -/*! @{ */ - -#define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU) -#define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U) -#define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK) -/*! @} */ - -/* The count of SCT_CAPCTRLL */ -#define SCT_CAPCTRLL_COUNT (16U) - -/*! @name CAPCTRLH - SCT_CAPCTRLH register */ -/*! @{ */ - -#define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU) -#define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U) -#define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK) -/*! @} */ - -/* The count of SCT_CAPCTRLH */ -#define SCT_CAPCTRLH_COUNT (16U) - -/*! @name CAPCTRL - SCT capture control register */ -/*! @{ */ - -#define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU) -#define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U) -/*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) - * register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of - * match/captures in this SCT. - */ -#define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK) - -#define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) -#define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U) -/*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event - * 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - */ -#define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK) -/*! @} */ - -/* The count of SCT_CAPCTRL */ -#define SCT_CAPCTRL_COUNT (16U) - -/*! @name MATCHRELL - SCT_MATCHRELL register */ -/*! @{ */ - -#define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU) -#define SCT_MATCHRELL_MATCHRELL_SHIFT (0U) -#define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK) -/*! @} */ - -/* The count of SCT_MATCHRELL */ -#define SCT_MATCHRELL_COUNT (16U) - -/*! @name MATCHRELH - SCT_MATCHRELH register */ -/*! @{ */ - -#define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU) -#define SCT_MATCHRELH_MATCHRELH_SHIFT (0U) -#define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK) -/*! @} */ - -/* The count of SCT_MATCHRELH */ -#define SCT_MATCHRELH_COUNT (16U) - -/*! @name MATCHREL - SCT match reload value register */ -/*! @{ */ - -#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU) -#define SCT_MATCHREL_RELOADn_L_SHIFT (0U) -/*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. - * When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn - * register. - */ -#define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK) - -#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U) -#define SCT_MATCHREL_RELOADn_H_SHIFT (16U) -/*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When - * UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn - * register. - */ -#define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK) -/*! @} */ - -/* The count of SCT_MATCHREL */ -#define SCT_MATCHREL_COUNT (16U) - -/*! @name EV_STATE - SCT event state register 0 */ -/*! @{ */ - -#define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFU) -#define SCT_EV_STATE_STATEMSKn_SHIFT (0U) -/*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT - * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of - * bits = number of states in this SCT. - */ -#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK) -/*! @} */ - -/* The count of SCT_EV_STATE */ -#define SCT_EV_STATE_COUNT (16U) - -/*! @name EV_CTRL - SCT event control register 0 */ -/*! @{ */ - -#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU) -#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U) -/*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur - * only when the counter selected by the HEVENT bit is running. - */ -#define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK) - -#define SCT_EV_CTRL_HEVENT_MASK (0x10U) -#define SCT_EV_CTRL_HEVENT_SHIFT (4U) -/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. - * 0b0..Selects the L state and the L match register selected by MATCHSEL. - * 0b1..Selects the H state and the H match register selected by MATCHSEL. - */ -#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK) - -#define SCT_EV_CTRL_OUTSEL_MASK (0x20U) -#define SCT_EV_CTRL_OUTSEL_SHIFT (5U) -/*! OUTSEL - Input/output select - * 0b0..Selects the inputs selected by IOSEL. - * 0b1..Selects the outputs selected by IOSEL. - */ -#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK) - -#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U) -#define SCT_EV_CTRL_IOSEL_SHIFT (6U) -/*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not - * select an input in this register if CKMODE is 1x. In this case the clock input is an implicit - * ingredient of every event. - */ -#define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK) - -#define SCT_EV_CTRL_IOCOND_MASK (0xC00U) -#define SCT_EV_CTRL_IOCOND_SHIFT (10U) -/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the - * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state - * detection, an input must have a minimum pulse width of at least one SCT clock period . - * 0b00..LOW - * 0b01..Rise - * 0b10..Fall - * 0b11..HIGH - */ -#define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK) - -#define SCT_EV_CTRL_COMBMODE_MASK (0x3000U) -#define SCT_EV_CTRL_COMBMODE_SHIFT (12U) -/*! COMBMODE - Selects how the specified match and I/O condition are used and combined. - * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. - * 0b01..MATCH. Uses the specified match only. - * 0b10..IO. Uses the specified I/O condition only. - * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. - */ -#define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK) - -#define SCT_EV_CTRL_STATELD_MASK (0x4000U) -#define SCT_EV_CTRL_STATELD_SHIFT (14U) -/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this - * event is the highest-numbered event occurring for that state. - * 0b0..STATEV value is added into STATE (the carry-out is ignored). - * 0b1..STATEV value is loaded into STATE. - */ -#define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK) - -#define SCT_EV_CTRL_STATEV_MASK (0xF8000U) -#define SCT_EV_CTRL_STATEV_SHIFT (15U) -/*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on - * STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and - * STATEV are both zero, there is no change to the STATE value. - */ -#define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK) - -#define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U) -#define SCT_EV_CTRL_MATCHMEM_SHIFT (20U) -/*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the - * triggering of this event, then a match is considered to be active whenever the counter value is - * GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR - * EQUAL TO the match value when counting down. If this bit is zero, a match is only be active - * during the cycle when the counter is equal to the match value. - */ -#define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK) - -#define SCT_EV_CTRL_DIRECTION_MASK (0x600000U) -#define SCT_EV_CTRL_DIRECTION_SHIFT (21U) -/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters - * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. - * 0b00..Direction independent. This event is triggered regardless of the count direction. - * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. - * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. - */ -#define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK) -/*! @} */ - -/* The count of SCT_EV_CTRL */ -#define SCT_EV_CTRL_COUNT (16U) - -/*! @name OUT_SET - SCT output 0 set register */ -/*! @{ */ - -#define SCT_OUT_SET_SET_MASK (0xFFFFU) -#define SCT_OUT_SET_SET_SHIFT (0U) -/*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output - * 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the - * counter is used in bi-directional mode, it is possible to reverse the action specified by the - * output set and clear registers when counting down, See the OUTPUTCTRL register. - */ -#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) -/*! @} */ - -/* The count of SCT_OUT_SET */ -#define SCT_OUT_SET_COUNT (10U) - -/*! @name OUT_CLR - SCT output 0 clear register */ -/*! @{ */ - -#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) -#define SCT_OUT_CLR_CLR_SHIFT (0U) -/*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 - * = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the - * counter is used in bi-directional mode, it is possible to reverse the action specified by the - * output set and clear registers when counting down, See the OUTPUTCTRL register. - */ -#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) -/*! @} */ - -/* The count of SCT_OUT_CLR */ -#define SCT_OUT_CLR_COUNT (10U) - - -/*! - * @} - */ /* end of group SCT_Register_Masks */ - - -/* SCT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SCT0 base address */ - #define SCT0_BASE (0x50085000u) - /** Peripheral SCT0 base address */ - #define SCT0_BASE_NS (0x40085000u) - /** Peripheral SCT0 base pointer */ - #define SCT0 ((SCT_Type *)SCT0_BASE) - /** Peripheral SCT0 base pointer */ - #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS { SCT0_BASE } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS { SCT0 } - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS_NS { SCT0_NS } -#else - /** Peripheral SCT0 base address */ - #define SCT0_BASE (0x40085000u) - /** Peripheral SCT0 base pointer */ - #define SCT0 ((SCT_Type *)SCT0_BASE) - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS { SCT0_BASE } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS { SCT0 } -#endif -/** Interrupt vectors for the SCT peripheral type */ -#define SCT_IRQS { SCT0_IRQn } - -/*! - * @} - */ /* end of group SCT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer - * @{ - */ - -/** SPI - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[1024]; - __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ - __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ - __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ - __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ - __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ - __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ - uint8_t RESERVED_2[2516]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_6[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_7[4]; - __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ - uint8_t RESERVED_8[432]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} SPI_Type; - -/* ---------------------------------------------------------------------------- - -- SPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Register_Masks SPI Register Masks - * @{ - */ - -/*! @name CFG - SPI Configuration register */ -/*! @{ */ - -#define SPI_CFG_ENABLE_MASK (0x1U) -#define SPI_CFG_ENABLE_SHIFT (0U) -/*! ENABLE - SPI enable. - * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. - * 0b1..Enabled. The SPI is enabled for operation. - */ -#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) - -#define SPI_CFG_MASTER_MASK (0x4U) -#define SPI_CFG_MASTER_SHIFT (2U) -/*! MASTER - Master mode select. - * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. - * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. - */ -#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) - -#define SPI_CFG_LSBF_MASK (0x8U) -#define SPI_CFG_LSBF_SHIFT (3U) -/*! LSBF - LSB First mode enable. - * 0b0..Standard. Data is transmitted and received in standard MSB first order. - * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). - */ -#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) - -#define SPI_CFG_CPHA_MASK (0x10U) -#define SPI_CFG_CPHA_SHIFT (4U) -/*! CPHA - Clock Phase select. - * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock - * changes away from the rest state). Data is changed on the following edge. - * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock - * changes away from the rest state). Data is captured on the following edge. - */ -#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) - -#define SPI_CFG_CPOL_MASK (0x20U) -#define SPI_CFG_CPOL_SHIFT (5U) -/*! CPOL - Clock Polarity select. - * 0b0..Low. The rest state of the clock (between transfers) is low. - * 0b1..High. The rest state of the clock (between transfers) is high. - */ -#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) - -#define SPI_CFG_LOOP_MASK (0x80U) -#define SPI_CFG_LOOP_SHIFT (7U) -/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit - * and receive data connected together to allow simple software testing. - * 0b0..Disabled. - * 0b1..Enabled. - */ -#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) - -#define SPI_CFG_SPOL0_MASK (0x100U) -#define SPI_CFG_SPOL0_SHIFT (8U) -/*! SPOL0 - SSEL0 Polarity select. - * 0b0..Low. The SSEL0 pin is active low. - * 0b1..High. The SSEL0 pin is active high. - */ -#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) - -#define SPI_CFG_SPOL1_MASK (0x200U) -#define SPI_CFG_SPOL1_SHIFT (9U) -/*! SPOL1 - SSEL1 Polarity select. - * 0b0..Low. The SSEL1 pin is active low. - * 0b1..High. The SSEL1 pin is active high. - */ -#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) - -#define SPI_CFG_SPOL2_MASK (0x400U) -#define SPI_CFG_SPOL2_SHIFT (10U) -/*! SPOL2 - SSEL2 Polarity select. - * 0b0..Low. The SSEL2 pin is active low. - * 0b1..High. The SSEL2 pin is active high. - */ -#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) - -#define SPI_CFG_SPOL3_MASK (0x800U) -#define SPI_CFG_SPOL3_SHIFT (11U) -/*! SPOL3 - SSEL3 Polarity select. - * 0b0..Low. The SSEL3 pin is active low. - * 0b1..High. The SSEL3 pin is active high. - */ -#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) -/*! @} */ - -/*! @name DLY - SPI Delay register */ -/*! @{ */ - -#define SPI_DLY_PRE_DELAY_MASK (0xFU) -#define SPI_DLY_PRE_DELAY_SHIFT (0U) -/*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data - * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This - * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI - * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are - * inserted. - */ -#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) - -#define SPI_DLY_POST_DELAY_MASK (0xF0U) -#define SPI_DLY_POST_DELAY_SHIFT (4U) -/*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL - * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock - * times are inserted. 0xF = 15 SPI clock times are inserted. - */ -#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) - -#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) -#define SPI_DLY_FRAME_DELAY_SHIFT (8U) -/*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current - * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 - * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock - * times are inserted. - */ -#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) - -#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) -#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) -/*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between - * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 - * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that - * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 - * SPI clock times. - */ -#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) -/*! @} */ - -/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ -/*! @{ */ - -#define SPI_STAT_SSA_MASK (0x10U) -#define SPI_STAT_SSA_SHIFT (4U) -/*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from - * deasserted to asserted, in both master and slave modes. This allows determining when the SPI - * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a - * slave mode access begins. This flag is cleared by software. - */ -#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) - -#define SPI_STAT_SSD_MASK (0x20U) -#define SPI_STAT_SSD_SHIFT (5U) -/*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to - * deasserted, in both master and slave modes. This allows determining when the SPI - * transmit/receive functions become idle. This flag is cleared by software. - */ -#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) - -#define SPI_STAT_STALLED_MASK (0x40U) -#define SPI_STAT_STALLED_SHIFT (6U) -/*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition. - */ -#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) - -#define SPI_STAT_ENDTRANSFER_MASK (0x80U) -#define SPI_STAT_ENDTRANSFER_SHIFT (7U) -/*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current - * transfer when the transmitter finishes any activity already in progress, as if the EOT flag - * had been set prior to the last transmission. This capability is included to support cases where - * it is not known when transmit data is written that it will be the end of a transfer. The bit - * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end - * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. - */ -#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) - -#define SPI_STAT_MSTIDLE_MASK (0x100U) -#define SPI_STAT_MSTIDLE_SHIFT (8U) -/*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. - * This means that the transmit holding register is empty and the transmitter is not in the - * process of sending data. - */ -#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -/*! @{ */ - -#define SPI_INTENSET_SSAEN_MASK (0x10U) -#define SPI_INTENSET_SSAEN_SHIFT (4U) -/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. - * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. - * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. - */ -#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) - -#define SPI_INTENSET_SSDEN_MASK (0x20U) -#define SPI_INTENSET_SSDEN_SHIFT (5U) -/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. - * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. - * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. - */ -#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) - -#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) -#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) -/*! MSTIDLEEN - Master idle interrupt enable. - * 0b0..No interrupt will be generated when the SPI master function is idle. - * 0b1..An interrupt will be generated when the SPI master function is fully idle. - */ -#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) -/*! @} */ - -/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ -/*! @{ */ - -#define SPI_INTENCLR_SSAEN_MASK (0x10U) -#define SPI_INTENCLR_SSAEN_SHIFT (4U) -/*! SSAEN - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) - -#define SPI_INTENCLR_SSDEN_MASK (0x20U) -#define SPI_INTENCLR_SSDEN_SHIFT (5U) -/*! SSDEN - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) - -#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) -#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) -/*! MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) -/*! @} */ - -/*! @name DIV - SPI clock Divider */ -/*! @{ */ - -#define SPI_DIV_DIVVAL_MASK (0xFFFFU) -#define SPI_DIV_DIVVAL_SHIFT (0U) -/*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the - * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, - * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results - * in FCLK/65536. - */ -#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - SPI Interrupt Status */ -/*! @{ */ - -#define SPI_INTSTAT_SSA_MASK (0x10U) -#define SPI_INTSTAT_SSA_SHIFT (4U) -/*! SSA - Slave Select Assert. - */ -#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) - -#define SPI_INTSTAT_SSD_MASK (0x20U) -#define SPI_INTSTAT_SSD_SHIFT (5U) -/*! SSD - Slave Select Deassert. - */ -#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) - -#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) -#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) -/*! MSTIDLE - Master Idle status flag. - */ -#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ - -#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) -#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) - -#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) -#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) - -#define SPI_FIFOCFG_SIZE_MASK (0x30U) -#define SPI_FIFOCFG_SIZE_SHIFT (4U) -/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 - * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - */ -#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) - -#define SPI_FIFOCFG_DMATX_MASK (0x1000U) -#define SPI_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) - -#define SPI_FIFOCFG_DMARX_MASK (0x2000U) -#define SPI_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) - -#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) -#define SPI_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in - * FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) - -#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) -#define SPI_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in - * FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) - -#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) -/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - */ -#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) - -#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) -/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - */ -#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ - -#define SPI_FIFOSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow - * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is - * needed. Cleared by writing a 1 to this bit. - */ -#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) - -#define SPI_FIFOSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA - * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - */ -#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) - -#define SPI_FIFOSTAT_PERINT_MASK (0x8U) -#define SPI_FIFOSTAT_PERINT_SHIFT (3U) -/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted - * an interrupt. The details can be found by reading the peripheral's STAT register. - */ -#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) - -#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) -/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - */ -#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) - -#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) -/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be - * written. When 0, the transmit FIFO is full and another write would cause it to overflow. - */ -#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) - -#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - */ -#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) - -#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) -#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) -/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to - * prevent the peripheral from causing an overflow. - */ -#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) - -#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY - * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at - * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be - * 0. - */ -#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) - -#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and - * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the - * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be - * 1. - */ -#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ - -#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) - -#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) - -#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) -#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled - * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to - * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO - * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX - * FIFO level decreases to 15 entries (is no longer full). - */ -#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) - -#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data - * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level - * can wake up the device just enough to perform DMA, then return to the reduced power mode. See - * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no - * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX - * FIFO has received 16 entries (has become full). - */ -#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ - -#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) -#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) - -#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) -#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) - -#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases - * to the level specified by TXLVL in the FIFOTRIG register. - */ -#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) - -#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level - * increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ - -#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) -#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) -/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) - -#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) -#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) -/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) - -#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) -/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) - -#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) -/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ - -#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. - */ -#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) - -#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. - */ -#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) - -#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO level interrupt. - */ -#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) - -#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO level interrupt. - */ -#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) - -#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) -#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) -/*! PERINT - Peripheral interrupt. - */ -#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ - -#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) -#define SPI_FIFOWR_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit data to the FIFO. - */ -#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) - -#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) -#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) -/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL0 asserted. - * 0b1..SSEL0 not asserted. - */ -#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) - -#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) -#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) -/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL1 asserted. - * 0b1..SSEL1 not asserted. - */ -#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) - -#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) -#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) -/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL2 asserted. - * 0b1..SSEL2 not asserted. - */ -#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) - -#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) -#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) -/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL3 asserted. - * 0b1..SSEL3 not asserted. - */ -#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) - -#define SPI_FIFOWR_EOT_MASK (0x100000U) -#define SPI_FIFOWR_EOT_SHIFT (20U) -/*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain - * so far at least the time specified by the Transfer_delay value in the DLY register. - * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. - * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. - */ -#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) - -#define SPI_FIFOWR_EOF_MASK (0x200000U) -#define SPI_FIFOWR_EOF_SHIFT (21U) -/*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value - * in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay - * value = 0. This control can be used as part of the support for frame lengths greater than 16 - * bits. - * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame. - * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be - * inserted before subsequent data is transmitted. - */ -#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) - -#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) -#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) -/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to - * read unneeded data from the receiver. Setting this bit simplifies the transmit process and can - * be used with the DMA. - * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit - * will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data - * is not read before new data is received. - * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received - * data. No receiver flags are generated. - */ -#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) - -#define SPI_FIFOWR_TXIGNORE_MASK (0x800000U) -#define SPI_FIFOWR_TXIGNORE_SHIFT (23U) -/*! TXIGNORE - Transmit Ignore. This allows data to be received using the SPI without the need to - * read unneeded data from the receiver. Setting this bit simplifies the transmit process and can - * be used with the DMA.This bit can only be set by writing to the upper 16 bits only of FIFOWR, - * i.e., a half-word write to offset 0xE22. - * 0b0..Write transmit data. Transmit data must be written for each data exchange between master and slave. In - * slave mode, an underrun error occurs if transmit data is not provided before needed in a data frame. - * 0b1..Ignore transmit data. Data can be received without transmitting data (after FIFOWR has been initialized - * to set TXIGNORE). No transmitter flags are generated. When configured with TXIGNORE =1, the slave will set - * the data to always 0. - */ -#define SPI_FIFOWR_TXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXIGNORE_SHIFT)) & SPI_FIFOWR_TXIGNORE_MASK) - -#define SPI_FIFOWR_LEN_MASK (0xF000000U) -#define SPI_FIFOWR_LEN_SHIFT (24U) -/*! LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths - * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. - * 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data - * transfer is 16 bits in length. - */ -#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ - -#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORD_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. - */ -#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) - -#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) -/*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved - * along with received data. The value will reflect the SSEL0 pin for both master and slave - * operation. A zero indicates that a slave select is active. The actual polarity of each slave select - * pin is configured by the related SPOL bit in CFG. - */ -#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) - -#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) -/*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved - * along with received data. The value will reflect the SSEL1 pin for both master and slave - * operation. A zero indicates that a slave select is active. The actual polarity of each slave select - * pin is configured by the related SPOL bit in CFG. - */ -#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) - -#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) -/*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved - * along with received data. The value will reflect the SSEL2 pin for both master and slave - * operation. A zero indicates that a slave select is active. The actual polarity of each slave select - * pin is configured by the related SPOL bit in CFG. - */ -#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) - -#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) -/*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved - * along with received data. The value will reflect the SSEL3 pin for both master and slave - * operation. A zero indicates that a slave select is active. The actual polarity of each slave select - * pin is configured by the related SPOL bit in CFG. - */ -#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) - -#define SPI_FIFORD_SOT_MASK (0x100000U) -#define SPI_FIFORD_SOT_SHIFT (20U) -/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went - * from deasserted to asserted (i.e., any previous transfer has ended). This information can be - * used to identify the first piece of data in cases where the transfer length is greater than 16 - * bits. - */ -#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ - -#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. - */ -#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) -/*! RXSSEL0_N - Slave Select for receive. - */ -#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) -/*! RXSSEL1_N - Slave Select for receive. - */ -#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) -/*! RXSSEL2_N - Slave Select for receive. - */ -#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) -/*! RXSSEL3_N - Slave Select for receive. - */ -#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) - -#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) -#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) -/*! SOT - Start of transfer flag. - */ -#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) -/*! @} */ - -/*! @name FIFOSIZE - FIFO size register */ -/*! @{ */ - -#define SPI_FIFOSIZE_FIFOSIZE_MASK (0x1FU) -#define SPI_FIFOSIZE_FIFOSIZE_SHIFT (0U) -/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - */ -#define SPI_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSIZE_FIFOSIZE_SHIFT)) & SPI_FIFOSIZE_FIFOSIZE_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ - -#define SPI_ID_MINOR_REV_MASK (0xF00U) -#define SPI_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation. - */ -#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) - -#define SPI_ID_MAJOR_REV_MASK (0xF000U) -#define SPI_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation. - */ -#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) - -#define SPI_ID_ID_MASK (0xFFFF0000U) -#define SPI_ID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function. - */ -#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SPI_Register_Masks */ - - -/* SPI - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SPI0 base address */ - #define SPI0_BASE (0x50086000u) - /** Peripheral SPI0 base address */ - #define SPI0_BASE_NS (0x40086000u) - /** Peripheral SPI0 base pointer */ - #define SPI0 ((SPI_Type *)SPI0_BASE) - /** Peripheral SPI0 base pointer */ - #define SPI0_NS ((SPI_Type *)SPI0_BASE_NS) - /** Peripheral SPI1 base address */ - #define SPI1_BASE (0x50087000u) - /** Peripheral SPI1 base address */ - #define SPI1_BASE_NS (0x40087000u) - /** Peripheral SPI1 base pointer */ - #define SPI1 ((SPI_Type *)SPI1_BASE) - /** Peripheral SPI1 base pointer */ - #define SPI1_NS ((SPI_Type *)SPI1_BASE_NS) - /** Peripheral SPI3 base address */ - #define SPI3_BASE (0x50089000u) - /** Peripheral SPI3 base address */ - #define SPI3_BASE_NS (0x40089000u) - /** Peripheral SPI3 base pointer */ - #define SPI3 ((SPI_Type *)SPI3_BASE) - /** Peripheral SPI3 base pointer */ - #define SPI3_NS ((SPI_Type *)SPI3_BASE_NS) - /** Peripheral SPI4 base address */ - #define SPI4_BASE (0x5008A000u) - /** Peripheral SPI4 base address */ - #define SPI4_BASE_NS (0x4008A000u) - /** Peripheral SPI4 base pointer */ - #define SPI4 ((SPI_Type *)SPI4_BASE) - /** Peripheral SPI4 base pointer */ - #define SPI4_NS ((SPI_Type *)SPI4_BASE_NS) - /** Peripheral SPI6 base address */ - #define SPI6_BASE (0x50097000u) - /** Peripheral SPI6 base address */ - #define SPI6_BASE_NS (0x40097000u) - /** Peripheral SPI6 base pointer */ - #define SPI6 ((SPI_Type *)SPI6_BASE) - /** Peripheral SPI6 base pointer */ - #define SPI6_NS ((SPI_Type *)SPI6_BASE_NS) - /** Peripheral SPI7 base address */ - #define SPI7_BASE (0x50098000u) - /** Peripheral SPI7 base address */ - #define SPI7_BASE_NS (0x40098000u) - /** Peripheral SPI7 base pointer */ - #define SPI7 ((SPI_Type *)SPI7_BASE) - /** Peripheral SPI7 base pointer */ - #define SPI7_NS ((SPI_Type *)SPI7_BASE_NS) - /** Peripheral SPI8 base address */ - #define SPI8_BASE (0x5009F000u) - /** Peripheral SPI8 base address */ - #define SPI8_BASE_NS (0x4009F000u) - /** Peripheral SPI8 base pointer */ - #define SPI8 ((SPI_Type *)SPI8_BASE) - /** Peripheral SPI8 base pointer */ - #define SPI8_NS ((SPI_Type *)SPI8_BASE_NS) - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI3_BASE, SPI4_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS { SPI0, SPI1, SPI3, SPI4, SPI6, SPI7, SPI8 } - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS_NS { SPI0_BASE_NS, SPI1_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS_NS { SPI0_NS, SPI1_NS, SPI3_NS, SPI4_NS, SPI6_NS, SPI7_NS, SPI8_NS } -#else - /** Peripheral SPI0 base address */ - #define SPI0_BASE (0x40086000u) - /** Peripheral SPI0 base pointer */ - #define SPI0 ((SPI_Type *)SPI0_BASE) - /** Peripheral SPI1 base address */ - #define SPI1_BASE (0x40087000u) - /** Peripheral SPI1 base pointer */ - #define SPI1 ((SPI_Type *)SPI1_BASE) - /** Peripheral SPI3 base address */ - #define SPI3_BASE (0x40089000u) - /** Peripheral SPI3 base pointer */ - #define SPI3 ((SPI_Type *)SPI3_BASE) - /** Peripheral SPI4 base address */ - #define SPI4_BASE (0x4008A000u) - /** Peripheral SPI4 base pointer */ - #define SPI4 ((SPI_Type *)SPI4_BASE) - /** Peripheral SPI6 base address */ - #define SPI6_BASE (0x40097000u) - /** Peripheral SPI6 base pointer */ - #define SPI6 ((SPI_Type *)SPI6_BASE) - /** Peripheral SPI7 base address */ - #define SPI7_BASE (0x40098000u) - /** Peripheral SPI7 base pointer */ - #define SPI7 ((SPI_Type *)SPI7_BASE) - /** Peripheral SPI8 base address */ - #define SPI8_BASE (0x4009F000u) - /** Peripheral SPI8 base pointer */ - #define SPI8 ((SPI_Type *)SPI8_BASE) - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI3_BASE, SPI4_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS { SPI0, SPI1, SPI3, SPI4, SPI6, SPI7, SPI8 } -#endif -/** Interrupt vectors for the SPI peripheral type */ -#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } - -/*! - * @} - */ /* end of group SPI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SYSCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer - * @{ - */ - -/** SYSCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t MEMORYREMAP; /**< Memory Remap control register, offset: 0x0 */ - uint8_t RESERVED_0[12]; - __IO uint32_t AHBMATPRIO; /**< AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest, offset: 0x10 */ - uint8_t RESERVED_1[36]; - __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */ - __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */ - uint8_t RESERVED_2[8]; - __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ - uint8_t RESERVED_3[180]; - union { /* offset: 0x100 */ - struct { /* offset: 0x100 */ - __IO uint32_t PRESETCTRL0; /**< Peripheral reset control 0, offset: 0x100 */ - __IO uint32_t PRESETCTRL1; /**< Peripheral reset control 1, offset: 0x104 */ - __IO uint32_t PRESETCTRL2; /**< Peripheral reset control 2, offset: 0x108 */ - } PRESETCTRL; - __IO uint32_t PRESETCTRLX[3]; /**< Peripheral reset control register, array offset: 0x100, array step: 0x4 */ - }; - uint8_t RESERVED_4[20]; - __IO uint32_t PRESETCTRLSET[3]; /**< Peripheral reset control set register, array offset: 0x120, array step: 0x4 */ - uint8_t RESERVED_5[20]; - __IO uint32_t PRESETCTRLCLR[3]; /**< Peripheral reset control clear register, array offset: 0x140, array step: 0x4 */ - uint8_t RESERVED_6[20]; - __O uint32_t SWR_RESET; /**< generate a software_reset, offset: 0x160 */ - uint8_t RESERVED_7[156]; - union { /* offset: 0x200 */ - struct { /* offset: 0x200 */ - __IO uint32_t AHBCLKCTRL0; /**< AHB Clock control 0, offset: 0x200 */ - __IO uint32_t AHBCLKCTRL1; /**< AHB Clock control 1, offset: 0x204 */ - __IO uint32_t AHBCLKCTRL2; /**< AHB Clock control 2, offset: 0x208 */ - } AHBCLKCTRL; - __IO uint32_t AHBCLKCTRLX[3]; /**< Peripheral reset control register, array offset: 0x200, array step: 0x4 */ - }; - uint8_t RESERVED_8[20]; - __IO uint32_t AHBCLKCTRLSET[3]; /**< Peripheral reset control register, array offset: 0x220, array step: 0x4 */ - uint8_t RESERVED_9[20]; - __IO uint32_t AHBCLKCTRLCLR[3]; /**< Peripheral reset control register, array offset: 0x240, array step: 0x4 */ - uint8_t RESERVED_10[20]; - union { /* offset: 0x260 */ - __IO uint32_t SYSTICKCLKSEL0; /**< System Tick Timer for CPU0 source select, offset: 0x260 */ - __IO uint32_t SYSTICKCLKSELX[1]; /**< Peripheral reset control register, array offset: 0x260, array step: 0x4 */ - }; - uint8_t RESERVED_11[4]; - __IO uint32_t TRACECLKSEL; /**< Trace clock source select, offset: 0x268 */ - union { /* offset: 0x26C */ - struct { /* offset: 0x26C */ - __IO uint32_t CTIMERCLKSEL0; /**< CTimer 0 clock source select, offset: 0x26C */ - __IO uint32_t CTIMERCLKSEL1; /**< CTimer 1 clock source select, offset: 0x270 */ - __IO uint32_t CTIMERCLKSEL2; /**< CTimer 2 clock source select, offset: 0x274 */ - __IO uint32_t CTIMERCLKSEL3; /**< CTimer 3 clock source select, offset: 0x278 */ - __IO uint32_t CTIMERCLKSEL4; /**< CTimer 4 clock source select, offset: 0x27C */ - } CTIMERCLKSEL; - __IO uint32_t CTIMERCLKSELX[5]; /**< Peripheral reset control register, array offset: 0x26C, array step: 0x4 */ - }; - __IO uint32_t MAINCLKSELA; /**< Main clock A source select, offset: 0x280 */ - __IO uint32_t MAINCLKSELB; /**< Main clock source select, offset: 0x284 */ - __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0x288 */ - uint8_t RESERVED_12[4]; - __IO uint32_t PLL0CLKSEL; /**< PLL0 clock source select, offset: 0x290 */ - __IO uint32_t PLL1CLKSEL; /**< PLL1 clock source select, offset: 0x294 */ - uint8_t RESERVED_13[8]; - __IO uint32_t CANCLKSEL; /**< CAN clock source select, offset: 0x2A0 */ - __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ - uint8_t RESERVED_14[8]; - union { /* offset: 0x2B0 */ - struct { /* offset: 0x2B0 */ - __IO uint32_t FCCLKSEL0; /**< Flexcomm Interface 0 clock source select for Fractional Rate Divider, offset: 0x2B0 */ - __IO uint32_t FCCLKSEL1; /**< Flexcomm Interface 1 clock source select for Fractional Rate Divider, offset: 0x2B4 */ - __IO uint32_t FCCLKSEL2; /**< Flexcomm Interface 2 clock source select for Fractional Rate Divider, offset: 0x2B8 */ - __IO uint32_t FCCLKSEL3; /**< Flexcomm Interface 3 clock source select for Fractional Rate Divider, offset: 0x2BC */ - __IO uint32_t FCCLKSEL4; /**< Flexcomm Interface 4 clock source select for Fractional Rate Divider, offset: 0x2C0 */ - __IO uint32_t FCCLKSEL5; /**< Flexcomm Interface 5 clock source select for Fractional Rate Divider, offset: 0x2C4 */ - __IO uint32_t FCCLKSEL6; /**< Flexcomm Interface 6 clock source select for Fractional Rate Divider, offset: 0x2C8 */ - __IO uint32_t FCCLKSEL7; /**< Flexcomm Interface 7 clock source select for Fractional Rate Divider, offset: 0x2CC */ - } FCCLKSEL; - __IO uint32_t FCCLKSELX[8]; /**< Peripheral reset control register, array offset: 0x2B0, array step: 0x4 */ - }; - __IO uint32_t HSLSPICLKSEL; /**< HS LSPI clock source select, offset: 0x2D0 */ - uint8_t RESERVED_15[12]; - __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ - uint8_t RESERVED_16[12]; - __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ - uint8_t RESERVED_17[12]; - __IO uint32_t SYSTICKCLKDIV0; /**< System Tick Timer divider for CPU0, offset: 0x300 */ - uint8_t RESERVED_18[4]; - __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */ - __IO uint32_t CANCLKDIV; /**< CAN clock divider, offset: 0x30C */ - uint8_t RESERVED_19[16]; - union { /* offset: 0x320 */ - struct { /* offset: 0x320 */ - __IO uint32_t FLEXFRG0CTRL; /**< Fractional rate divider for flexcomm 0, offset: 0x320 */ - __IO uint32_t FLEXFRG1CTRL; /**< Fractional rate divider for flexcomm 1, offset: 0x324 */ - __IO uint32_t FLEXFRG2CTRL; /**< Fractional rate divider for flexcomm 2, offset: 0x328 */ - __IO uint32_t FLEXFRG3CTRL; /**< Fractional rate divider for flexcomm 3, offset: 0x32C */ - __IO uint32_t FLEXFRG4CTRL; /**< Fractional rate divider for flexcomm 4, offset: 0x330 */ - __IO uint32_t FLEXFRG5CTRL; /**< Fractional rate divider for flexcomm 5, offset: 0x334 */ - __IO uint32_t FLEXFRG6CTRL; /**< Fractional rate divider for flexcomm 6, offset: 0x338 */ - __IO uint32_t FLEXFRG7CTRL; /**< Fractional rate divider for flexcomm 7, offset: 0x33C */ - } FLEXFRGCTRL; - __IO uint32_t FLEXFRGXCTRL[8]; /**< Peripheral reset control register, array offset: 0x320, array step: 0x4 */ - }; - uint8_t RESERVED_20[64]; - __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */ - __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ - __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */ - __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */ - uint8_t RESERVED_21[4]; - __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ - uint8_t RESERVED_22[20]; - __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ - uint8_t RESERVED_23[4]; - __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ - uint8_t RESERVED_24[12]; - __IO uint32_t PLL0CLKDIV; /**< PLL0 clock divider, offset: 0x3C4 */ - uint8_t RESERVED_25[52]; - __IO uint32_t CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */ - __IO uint32_t FMCCR; /**< FMC configuration register, offset: 0x400 */ - uint8_t RESERVED_26[24]; - __O uint32_t FMCFLUSH; /**< FMCflush control, offset: 0x41C */ - __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */ - uint8_t RESERVED_27[28]; - __IO uint32_t FLASHREMAP_SIZE; /**< This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB., offset: 0x440 */ - __IO uint32_t FLASHREMAP_SIZE_DP; /**< This 32-bit register is a duplicate of FLASHREMAPSIZE for increased security., offset: 0x444 */ - __IO uint32_t FLASHREMAP_OFFSET; /**< This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB., offset: 0x448 */ - __IO uint32_t FLASHREMAP_OFFSET_DP; /**< This 32-bit register is a duplicate of FLASHREMAPOFFSET for increased security., offset: 0x44C */ - uint8_t RESERVED_28[12]; - __IO uint32_t FLASHREMAP_LOCK; /**< Control write access to FLASHREMAP_SIZE and FLASHREMAP_OFFSET registers., offset: 0x45C */ - uint8_t RESERVED_29[16]; - __IO uint32_t CASPER_CTRL; /**< Control CASPER integration., offset: 0x470 */ - uint8_t RESERVED_30[236]; - __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */ - __I uint32_t PLL1STAT; /**< PLL1 550m status, offset: 0x564 */ - __IO uint32_t PLL1NDEC; /**< PLL1 550m N divider, offset: 0x568 */ - __IO uint32_t PLL1MDEC; /**< PLL1 550m M divider, offset: 0x56C */ - __IO uint32_t PLL1PDEC; /**< PLL1 550m P divider, offset: 0x570 */ - uint8_t RESERVED_31[12]; - __IO uint32_t PLL0CTRL; /**< PLL0 550m control, offset: 0x580 */ - __I uint32_t PLL0STAT; /**< PLL0 550m status, offset: 0x584 */ - __IO uint32_t PLL0NDEC; /**< PLL0 550m N divider, offset: 0x588 */ - __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */ - __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */ - __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */ - uint8_t RESERVED_32[364]; - __IO uint32_t FUNCRETENTIONCTRL; /**< Functional retention control register, offset: 0x704 */ - uint8_t RESERVED_33[260]; - __I uint32_t CPSTAT; /**< CPU Status, offset: 0x80C */ - uint8_t RESERVED_34[272]; - __IO uint32_t BOOT_SEED_REG0; /**< boot seed (256-bit random value), offset: 0x920 */ - __IO uint32_t BOOT_SEED_REG1; /**< boot seed (256-bit random value), offset: 0x924 */ - __IO uint32_t BOOT_SEED_REG2; /**< boot seed (256-bit random value), offset: 0x928 */ - __IO uint32_t BOOT_SEED_REG3; /**< boot seed (256-bit random value), offset: 0x92C */ - __IO uint32_t BOOT_SEED_REG4; /**< boot seed (256-bit random value), offset: 0x930 */ - __IO uint32_t BOOT_SEED_REG5; /**< boot seed (256-bit random value), offset: 0x934 */ - __IO uint32_t BOOT_SEED_REG6; /**< boot seed (256-bit random value), offset: 0x938 */ - __IO uint32_t BOOT_SEED_REG7; /**< boot seed (256-bit random value), offset: 0x93C */ - __IO uint32_t HMAC_REG0; /**< HMAC, offset: 0x940 */ - __IO uint32_t HMAC_REG1; /**< HMAC, offset: 0x944 */ - __IO uint32_t HMAC_REG2; /**< HMAC, offset: 0x948 */ - __IO uint32_t HMAC_REG3; /**< HMAC, offset: 0x94C */ - __IO uint32_t HMAC_REG4; /**< HMAC, offset: 0x950 */ - __IO uint32_t HMAC_REG5; /**< HMAC, offset: 0x954 */ - __IO uint32_t HMAC_REG6; /**< HMAC, offset: 0x958 */ - __IO uint32_t HMAC_REG7; /**< HMAC, offset: 0x95C */ - __IO uint32_t BOOT_LOCK; /**< Control write access to boot seed security registers., offset: 0x960 */ - uint8_t RESERVED_35[180]; - __IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures, offset: 0xA18 */ - uint8_t RESERVED_36[244]; - __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */ - __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */ - uint8_t RESERVED_37[748]; - __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */ - __IO uint32_t GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */ - uint8_t RESERVED_38[380]; - __IO uint32_t HASHRESTHWKEY; /**< Controls whether the HASH AES hardware secret key is restricted to use by secure code, offset: 0xF88 */ - uint8_t RESERVED_39[20]; - __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers., offset: 0xFA0 */ - __IO uint32_t DEBUG_FEATURES; /**< Cortex debug features control., offset: 0xFA4 */ - __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex debug features control. (duplicate), offset: 0xFA8 */ - uint8_t RESERVED_40[8]; - __IO uint32_t SWD_ACCESS_CPU0; /**< This register is used by ROM during DEBUG authentication mechanism to enable debug access port for CPU0., offset: 0xFB4 */ - uint8_t RESERVED_41[4]; - __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index., offset: 0xFBC */ - __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug authentication BEACON register, offset: 0xFC0 */ - uint8_t RESERVED_42[52]; - __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ - __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */ -} SYSCON_Type; - -/* ---------------------------------------------------------------------------- - -- SYSCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Register_Masks SYSCON Register Masks - * @{ - */ - -/*! @name MEMORYREMAP - Memory Remap control register */ -/*! @{ */ - -#define SYSCON_MEMORYREMAP_MAP_MASK (0x3U) -#define SYSCON_MEMORYREMAP_MAP_SHIFT (0U) -/*! MAP - Select the location of the vector table :. - * 0b00..Vector Table in ROM. - * 0b01..Vector Table in RAM. - * 0b10..Vector Table in Flash. - * 0b11..Vector Table in Flash. - */ -#define SYSCON_MEMORYREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK) -/*! @} */ - -/*! @name AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest */ -/*! @{ */ - -#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK (0x3U) -#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT (0U) -/*! PRI_CPU0_CBUS - CPU0 C-AHB bus. - */ -#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK (0xCU) -#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT (2U) -/*! PRI_CPU0_SBUS - CPU0 S-AHB bus. - */ -#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0x30U) -#define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (4U) -/*! PRI_SDMA0 - DMA0 controller priority. - */ -#define SYSCON_AHBMATPRIO_PRI_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK) - -#define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0xC0U) -#define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (6U) -/*! PRI_SDMA1 - DMA1 controller priority. - */ -#define SYSCON_AHBMATPRIO_PRI_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK) - -#define SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK (0x30000U) -#define SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT (16U) -/*! PRI_HASH_AES - HASH_AES. - */ -#define SYSCON_AHBMATPRIO_PRI_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT)) & SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK) - -#define SYSCON_AHBMATPRIO_PRI_CANFD_MASK (0xC0000U) -#define SYSCON_AHBMATPRIO_PRI_CANFD_SHIFT (18U) -/*! PRI_CANFD - CANFD. - */ -#define SYSCON_AHBMATPRIO_PRI_CANFD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CANFD_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CANFD_MASK) -/*! @} */ - -/*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */ -/*! @{ */ - -#define SYSCON_CPU0STCKCAL_TENMS_MASK (0xFFFFFFU) -#define SYSCON_CPU0STCKCAL_TENMS_SHIFT (0U) -/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value - * reads as zero, the calibration value is not known. - */ -#define SYSCON_CPU0STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK) - -#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) -/*! SKEW - Initial value for the Systick timer. - */ -#define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) - -#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) -/*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference - * clock provided; 1 = no reference clock provided. - */ -#define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */ -/*! @{ */ - -#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) -#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) -/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the - * value reads as zero, the calibration value is not known. - */ -#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) - -#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) -/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. - */ -#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) - -#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) -/*! NOREF - Initial value for the Systick timer. - */ -#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name NMISRC - NMI Source Select */ -/*! @{ */ - -#define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU) -#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) -/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0. - */ -#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) - -#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) -#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) -/*! NMIENCPU0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. - */ -#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) -/*! @} */ - -/*! @name PRESETCTRL0 - Peripheral reset control 0 */ -/*! @{ */ - -#define SYSCON_PRESETCTRL0_ROM_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL0_ROM_RST_SHIFT (1U) -/*! ROM_RST - ROM reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_ROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ROM_RST_SHIFT)) & SYSCON_PRESETCTRL0_ROM_RST_MASK) - -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U) -/*! SRAM_CTRL1_RST - SRAM Controller 1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK) - -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U) -/*! SRAM_CTRL2_RST - SRAM Controller 2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK) - -#define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U) -/*! FLASH_RST - Flash controller reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK) - -#define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U) -/*! FMC_RST - FMC controller reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK) - -#define SYSCON_PRESETCTRL0_MUX_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL0_MUX_RST_SHIFT (11U) -/*! MUX_RST - Input Mux reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK) - -#define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U) -/*! IOCON_RST - I/O controller reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK) - -#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U) -/*! GPIO0_RST - GPIO0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) - -#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U) -/*! GPIO1_RST - GPIO1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) - -#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U) -/*! PINT_RST - Pin interrupt (PINT) reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) - -#define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U) -/*! GINT_RST - Group interrupt (GINT) reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK) - -#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U) -#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U) -/*! DMA0_RST - DMA0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) - -#define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U) -#define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U) -/*! CRCGEN_RST - CRCGEN reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_CRCGEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK) - -#define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U) -/*! WWDT_RST - Watchdog Timer reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK) - -#define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U) -#define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U) -/*! RTC_RST - Real Time Clock (RTC) reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK) - -#define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U) -#define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U) -/*! MAILBOX_RST - Inter CPU communication Mailbox reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK) - -#define SYSCON_PRESETCTRL0_ADC_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL0_ADC_RST_SHIFT (27U) -/*! ADC_RST - ADC reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_ADC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRL1 - Peripheral reset control 1 */ -/*! @{ */ - -#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) -#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) -/*! MRT_RST - MRT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) - -#define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT (1U) -/*! OSTIMER_RST - OS Event Timer reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_OSTIMER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK) - -#define SYSCON_PRESETCTRL1_SCT_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL1_SCT_RST_SHIFT (2U) -/*! SCT_RST - SCT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_SCT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT_RST_MASK) - -#define SYSCON_PRESETCTRL1_CAN_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL1_CAN_RST_SHIFT (7U) -/*! CAN_RST - CAN reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_CAN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_CAN_RST_SHIFT)) & SYSCON_PRESETCTRL1_CAN_RST_MASK) - -#define SYSCON_PRESETCTRL1_UTICK_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT (10U) -/*! UTICK_RST - UTICK reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) -/*! FC0_RST - FC0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) -#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) -/*! FC1_RST - FC1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) -/*! FC2_RST - FC2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) -/*! FC3_RST - FC3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) -/*! FC4_RST - FC4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) -/*! FC5_RST - FC5 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) -/*! FC6_RST - FC6 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) -/*! FC7_RST - FC7 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) - -#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) -/*! TIMER2_RST - Timer 2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) - -#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) -#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) -/*! TIMER0_RST - Timer 0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) - -#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) -/*! TIMER1_RST - Timer 1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRL2 - Peripheral reset control 2 */ -/*! @{ */ - -#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) -/*! DMA1_RST - DMA1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) - -#define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U) -/*! COMP_RST - Comparator reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_COMP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK) - -#define SYSCON_PRESETCTRL2_SRAM_CTRL3_RST_MASK (0x40U) -#define SYSCON_PRESETCTRL2_SRAM_CTRL3_RST_SHIFT (6U) -/*! SRAM_CTRL3_RST - SRAM Controller 3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_SRAM_CTRL3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL2_SRAM_CTRL3_RST_MASK) - -#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) -/*! FREQME_RST - Frequency meter reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) - -#define SYSCON_PRESETCTRL2_CDOG_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL2_CDOG_RST_SHIFT (11U) -/*! CDOG_RST - Code Watchdog reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_CDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CDOG_RST_SHIFT)) & SYSCON_PRESETCTRL2_CDOG_RST_MASK) - -#define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U) -/*! RNG_RST - RNG reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK) - -#define SYSCON_PRESETCTRL2_SYSCTL_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT (15U) -/*! SYSCTL_RST - SYSCTL Block reset. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_SYSCTL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT)) & SYSCON_PRESETCTRL2_SYSCTL_RST_MASK) - -#define SYSCON_PRESETCTRL2_HASH_AES_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT (18U) -/*! HASH_AES_RST - HASH_AES reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_HASH_AES_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH_AES_RST_MASK) - -#define SYSCON_PRESETCTRL2_PLULUT_RST_MASK (0x100000U) -#define SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT (20U) -/*! PLULUT_RST - PLU LUT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_PLULUT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLULUT_RST_MASK) - -#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) -#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) -/*! TIMER3_RST - Timer 3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) - -#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) -/*! TIMER4_RST - Timer 4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) - -#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) -#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) -/*! PUF_RST - PUF reset control reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) - -#define SYSCON_PRESETCTRL2_CASPER_RST_MASK (0x1000000U) -#define SYSCON_PRESETCTRL2_CASPER_RST_SHIFT (24U) -/*! CASPER_RST - Casper reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_CASPER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CASPER_RST_SHIFT)) & SYSCON_PRESETCTRL2_CASPER_RST_MASK) - -#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT (27U) -/*! ANALOG_CTRL_RST - analog control reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK) - -#define SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK (0x10000000U) -#define SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT (28U) -/*! HS_LSPI_RST - HS LSPI reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_HS_LSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK) - -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U) -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U) -/*! GPIO_SEC_RST - GPIO secure reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK) - -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U) -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U) -/*! GPIO_SEC_INT_RST - GPIO secure int reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRLX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_PRESETCTRLX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_PRESETCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLX_DATA_SHIFT)) & SYSCON_PRESETCTRLX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLX */ -#define SYSCON_PRESETCTRLX_COUNT (3U) - -/*! @name PRESETCTRLSET - Peripheral reset control set register */ -/*! @{ */ - -#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLSET */ -#define SYSCON_PRESETCTRLSET_COUNT (3U) - -/*! @name PRESETCTRLCLR - Peripheral reset control clear register */ -/*! @{ */ - -#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLCLR */ -#define SYSCON_PRESETCTRLCLR_COUNT (3U) - -/*! @name SWR_RESET - generate a software_reset */ -/*! @{ */ - -#define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU) -#define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U) -/*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset. - * 0b01011010000000000000000000000001..Generate a software reset. - * 0b00000000000000000000000000000000..Bloc is not reset. - */ -#define SYSCON_SWR_RESET_SWR_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL0 - AHB Clock control 0 */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) -#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) -/*! ROM - Enables the clock for the ROM. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) - -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U) -/*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK) - -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U) -/*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK) - -#define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U) -#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U) -/*! FLASH - Enables the clock for the Flash controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK) - -#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U) -#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U) -/*! FMC - Enables the clock for the FMC controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) - -#define SYSCON_AHBCLKCTRL0_MUX_MASK (0x800U) -#define SYSCON_AHBCLKCTRL0_MUX_SHIFT (11U) -/*! MUX - Enables the clock for the Input Mux. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_MUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK) - -#define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U) -/*! IOCON - Enables the clock for the I/O controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK) - -#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U) -/*! GPIO0 - Enables the clock for the GPIO0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) - -#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U) -/*! GPIO1 - Enables the clock for the GPIO1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) - -#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U) -/*! PINT - Enables the clock for the Pin interrupt (PINT). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) - -#define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U) -/*! GINT - Enables the clock for the Group interrupt (GINT). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK) - -#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U) -#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U) -/*! DMA0 - Enables the clock for the DMA0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) - -#define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U) -#define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U) -/*! CRCGEN - Enables the clock for the CRCGEN. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK) - -#define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U) -/*! WWDT - Enables the clock for the Watchdog Timer. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK) - -#define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U) -#define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U) -/*! RTC - Enables the clock for the Real Time Clock (RTC). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK) - -#define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U) -/*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK) - -#define SYSCON_AHBCLKCTRL0_ADC_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL0_ADC_SHIFT (27U) -/*! ADC - Enables the clock for the ADC. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL1 - AHB Clock control 1 */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) -#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) -/*! MRT - Enables the clock for the MRT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) - -#define SYSCON_AHBCLKCTRL1_OSTIMER_MASK (0x2U) -#define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT (1U) -/*! OSTIMER - Enables the clock for the OS Event Timer. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK) - -#define SYSCON_AHBCLKCTRL1_SCT_MASK (0x4U) -#define SYSCON_AHBCLKCTRL1_SCT_SHIFT (2U) -/*! SCT - Enables the clock for the SCT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_SCT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT_MASK) - -#define SYSCON_AHBCLKCTRL1_CAN_MASK (0x80U) -#define SYSCON_AHBCLKCTRL1_CAN_SHIFT (7U) -/*! CAN - Enables the clock for the CAN. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_CAN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_CAN_SHIFT)) & SYSCON_AHBCLKCTRL1_CAN_MASK) - -#define SYSCON_AHBCLKCTRL1_UTICK_MASK (0x400U) -#define SYSCON_AHBCLKCTRL1_UTICK_SHIFT (10U) -/*! UTICK - Enables the clock for the UTICK. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK) - -#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) -#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) -/*! FC0 - Enables the clock for the FC0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) - -#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) -#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) -/*! FC1 - Enables the clock for the FC1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) - -#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) -/*! FC2 - Enables the clock for the FC2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) - -#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) -/*! FC3 - Enables the clock for the FC3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) - -#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) -/*! FC4 - Enables the clock for the FC4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) - -#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) -/*! FC5 - Enables the clock for the FC5. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) - -#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) -/*! FC6 - Enables the clock for the FC6. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) - -#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) -/*! FC7 - Enables the clock for the FC7. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) - -#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) -/*! TIMER2 - Enables the clock for the Timer 2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) - -#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) -/*! TIMER0 - Enables the clock for the Timer 0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) - -#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) -/*! TIMER1 - Enables the clock for the Timer 1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL2 - AHB Clock control 2 */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) -#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) -/*! DMA1 - Enables the clock for the DMA1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) - -#define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U) -#define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U) -/*! COMP - Enables the clock for the Comparator. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK) - -#define SYSCON_AHBCLKCTRL2_SRAM_CTRL3_MASK (0x40U) -#define SYSCON_AHBCLKCTRL2_SRAM_CTRL3_SHIFT (6U) -/*! SRAM_CTRL3 - Enables the clock for the SRAM Controller 3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_SRAM_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL2_SRAM_CTRL3_MASK) - -#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) -#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) -/*! FREQME - Enables the clock for the Frequency meter. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) - -#define SYSCON_AHBCLKCTRL2_CDOG_MASK (0x800U) -#define SYSCON_AHBCLKCTRL2_CDOG_SHIFT (11U) -/*! CDOG - Enables the clock for the code watchdog. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_CDOG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CDOG_SHIFT)) & SYSCON_AHBCLKCTRL2_CDOG_MASK) - -#define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U) -/*! RNG - Enables the clock for the RNG. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK) - -#define SYSCON_AHBCLKCTRL2_SYSCTL_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT (15U) -/*! SYSCTL - SYSCTL block clock. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_SYSCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT)) & SYSCON_AHBCLKCTRL2_SYSCTL_MASK) - -#define SYSCON_AHBCLKCTRL2_HASH_AES_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT (18U) -/*! HASH_AES - Enables the clock for the HASH_AES. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH_AES_MASK) - -#define SYSCON_AHBCLKCTRL2_PLULUT_MASK (0x100000U) -#define SYSCON_AHBCLKCTRL2_PLULUT_SHIFT (20U) -/*! PLULUT - Enables the clock for the PLU LUT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PLULUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLULUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLULUT_MASK) - -#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) -#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) -/*! TIMER3 - Enables the clock for the Timer 3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) - -#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) -/*! TIMER4 - Enables the clock for the Timer 4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) - -#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) -#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) -/*! PUF - Enables the clock for the PUF reset control. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) - -#define SYSCON_AHBCLKCTRL2_CASPER_MASK (0x1000000U) -#define SYSCON_AHBCLKCTRL2_CASPER_SHIFT (24U) -/*! CASPER - Enables the clock for the Casper. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CASPER_SHIFT)) & SYSCON_AHBCLKCTRL2_CASPER_MASK) - -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U) -/*! ANALOG_CTRL - Enables the clock for the analog control. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK) - -#define SYSCON_AHBCLKCTRL2_HS_LSPI_MASK (0x10000000U) -#define SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT (28U) -/*! HS_LSPI - Enables the clock for the HS LSPI. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_LSPI_MASK) - -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U) -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U) -/*! GPIO_SEC - Enables the clock for the GPIO secure. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK) - -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U) -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U) -/*! GPIO_SEC_INT - Enables the clock for the GPIO secure int. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK) -/*! @} */ - -/*! @name AHBCLKCTRLX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRLX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_AHBCLKCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLX_DATA_SHIFT)) & SYSCON_AHBCLKCTRLX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLX */ -#define SYSCON_AHBCLKCTRLX_COUNT (3U) - -/*! @name AHBCLKCTRLSET - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLSET */ -#define SYSCON_AHBCLKCTRLSET_COUNT (3U) - -/*! @name AHBCLKCTRLCLR - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLCLR */ -#define SYSCON_AHBCLKCTRLCLR_COUNT (3U) - -/*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) -/*! SEL - System Tick Timer for CPU0 source select. - * 0b000..System Tick 0 divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKSELX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKSELX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_SYSTICKCLKSELX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_SYSTICKCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSELX_DATA_SHIFT)) & SYSCON_SYSTICKCLKSELX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_SYSTICKCLKSELX */ -#define SYSCON_SYSTICKCLKSELX_COUNT (1U) - -/*! @name TRACECLKSEL - Trace clock source select */ -/*! @{ */ - -#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) -#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) -/*! SEL - Trace clock source select. - * 0b000..Trace divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL0 - CTimer 0 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL0_SEL_SHIFT (0U) -/*! SEL - CTimer 0 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL0_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL1 - CTimer 1 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL1_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL1_SEL_SHIFT (0U) -/*! SEL - CTimer 1 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL1_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL1_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL2 - CTimer 2 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL2_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL2_SEL_SHIFT (0U) -/*! SEL - CTimer 2 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL2_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL2_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL3 - CTimer 3 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL3_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL3_SEL_SHIFT (0U) -/*! SEL - CTimer 3 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL3_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL3_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL4 - CTimer 4 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL4_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL4_SEL_SHIFT (0U) -/*! SEL - CTimer 4 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL4_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL4_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSELX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSELX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_CTIMERCLKSELX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_CTIMERCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSELX_DATA_SHIFT)) & SYSCON_CTIMERCLKSELX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_CTIMERCLKSELX */ -#define SYSCON_CTIMERCLKSELX_COUNT (5U) - -/*! @name MAINCLKSELA - Main clock A source select */ -/*! @{ */ - -#define SYSCON_MAINCLKSELA_SEL_MASK (0x7U) -#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) -/*! SEL - Main clock A source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..Reserved. - * 0b101..Reserved. - * 0b110..Reserved. - * 0b111..Reserved. - */ -#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) -/*! @} */ - -/*! @name MAINCLKSELB - Main clock source select */ -/*! @{ */ - -#define SYSCON_MAINCLKSELB_SEL_MASK (0x7U) -#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) -/*! SEL - Main clock source select. - * 0b000..Main Clock A. - * 0b001..PLL0 clock. - * 0b010..PLL1 clock. - * 0b011..Oscillator 32 kHz clock. - * 0b100..Reserved. - * 0b101..Reserved. - * 0b110..Reserved. - * 0b111..Reserved. - */ -#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) -/*! @} */ - -/*! @name CLKOUTSEL - CLKOUT clock source select */ -/*! @{ */ - -#define SYSCON_CLKOUTSEL_SEL_MASK (0xFU) -#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) -/*! SEL - CLKOUT clock source select. - * 0b0000..Main clock. - * 0b0001..PLL0 clock. - * 0b0010..CLKIN clock. - * 0b0011..FRO 96 MHz clock. - * 0b0100..FRO 1MHz clock. - * 0b0101..PLL1 clock. - * 0b0110..Oscillator 32kHz clock. - * 0b0111..No clock. - * 0b1000..Reserved. - * 0b1001..Reserved. - * 0b1010..Reserved. - * 0b1011..Reserved. - * 0b1100..No clock. - * 0b1101..No clock. - * 0b1110..No clock. - * 0b1111..No clock. - */ -#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) -/*! @} */ - -/*! @name PLL0CLKSEL - PLL0 clock source select */ -/*! @{ */ - -#define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U) -#define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U) -/*! SEL - PLL0 clock source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..Oscillator 32kHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_PLL0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name PLL1CLKSEL - PLL1 clock source select */ -/*! @{ */ - -#define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U) -#define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U) -/*! SEL - PLL1 clock source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..Oscillator 32kHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_PLL1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name CANCLKSEL - CAN clock source select */ -/*! @{ */ - -#define SYSCON_CANCLKSEL_SEL_MASK (0x7U) -#define SYSCON_CANCLKSEL_SEL_SHIFT (0U) -/*! SEL - CAN clock source select. - * 0b000..CAN divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_CANCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKSEL_SEL_SHIFT)) & SYSCON_CANCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name ADCCLKSEL - ADC clock source select */ -/*! @{ */ - -#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) -#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) -/*! SEL - ADC clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..FRO 96 MHz clock. - * 0b011..Reserved. - * 0b100..Xtal clock coming directly. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL0_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL0_SEL_SHIFT)) & SYSCON_FCCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL1_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL1_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL1_SEL_SHIFT)) & SYSCON_FCCLKSEL1_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL2_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL2_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL2_SEL_SHIFT)) & SYSCON_FCCLKSEL2_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL3_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL3_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL3_SEL_SHIFT)) & SYSCON_FCCLKSEL3_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL4_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL4_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL4_SEL_SHIFT)) & SYSCON_FCCLKSEL4_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL5_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL5_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL5_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL5_SEL_SHIFT)) & SYSCON_FCCLKSEL5_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL6_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL6_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL6_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL6_SEL_SHIFT)) & SYSCON_FCCLKSEL6_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL7_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL7_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL7_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL7_SEL_SHIFT)) & SYSCON_FCCLKSEL7_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSELX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_FCCLKSELX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_FCCLKSELX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_FCCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSELX_DATA_SHIFT)) & SYSCON_FCCLKSELX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_FCCLKSELX */ -#define SYSCON_FCCLKSELX_COUNT (8U) - -/*! @name HSLSPICLKSEL - HS LSPI clock source select */ -/*! @{ */ - -#define SYSCON_HSLSPICLKSEL_SEL_MASK (0x7U) -#define SYSCON_HSLSPICLKSEL_SEL_SHIFT (0U) -/*! SEL - HS LSPI clock source select. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..No clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_HSLSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HSLSPICLKSEL_SEL_SHIFT)) & SYSCON_HSLSPICLKSEL_SEL_MASK) -/*! @} */ - -/*! @name MCLKCLKSEL - MCLK clock source select */ -/*! @{ */ - -#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) -#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) -/*! SEL - MCLK clock source select. - * 0b000..FRO 96 MHz clock. - * 0b001..PLL0 clock. - * 0b010..Reserved. - * 0b011..Reserved. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SCTCLKSEL - SCTimer/PWM clock source select */ -/*! @{ */ - -#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) -#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) -/*! SEL - SCTimer/PWM clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..CLKIN clock. - * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..MCLK clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKDIV0_DIV_MASK (0xFFU) -#define SYSCON_SYSTICKCLKDIV0_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_SYSTICKCLKDIV0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV0_DIV_MASK) - -#define SYSCON_SYSTICKCLKDIV0_RESET_MASK (0x20000000U) -#define SYSCON_SYSTICKCLKDIV0_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SYSTICKCLKDIV0_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV0_RESET_MASK) - -#define SYSCON_SYSTICKCLKDIV0_HALT_MASK (0x40000000U) -#define SYSCON_SYSTICKCLKDIV0_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SYSTICKCLKDIV0_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV0_HALT_MASK) - -#define SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK (0x80000000U) -#define SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SYSTICKCLKDIV0_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK) -/*! @} */ - -/*! @name TRACECLKDIV - TRACE clock divider */ -/*! @{ */ - -#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) -#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) - -#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) - -#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) - -#define SYSCON_TRACECLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_TRACECLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_TRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_TRACECLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name CANCLKDIV - CAN clock divider */ -/*! @{ */ - -#define SYSCON_CANCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_CANCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_CANCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_DIV_SHIFT)) & SYSCON_CANCLKDIV_DIV_MASK) - -#define SYSCON_CANCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_CANCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_CANCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_RESET_SHIFT)) & SYSCON_CANCLKDIV_RESET_MASK) - -#define SYSCON_CANCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_CANCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_CANCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_HALT_SHIFT)) & SYSCON_CANCLKDIV_HALT_MASK) - -#define SYSCON_CANCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_CANCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_CANCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_REQFLAG_SHIFT)) & SYSCON_CANCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 */ -/*! @{ */ - -#define SYSCON_FLEXFRG0CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG0CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG0CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG0CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG0CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG0CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG0CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG0CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 */ -/*! @{ */ - -#define SYSCON_FLEXFRG1CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG1CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG1CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG1CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG1CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG1CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG1CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG1CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 */ -/*! @{ */ - -#define SYSCON_FLEXFRG2CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG2CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG2CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG2CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG2CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG2CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG2CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG2CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 */ -/*! @{ */ - -#define SYSCON_FLEXFRG3CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG3CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG3CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG3CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG3CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG3CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG3CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG3CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 */ -/*! @{ */ - -#define SYSCON_FLEXFRG4CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG4CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG4CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG4CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG4CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG4CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG4CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG4CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 */ -/*! @{ */ - -#define SYSCON_FLEXFRG5CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG5CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG5CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG5CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG5CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG5CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG5CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG5CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 */ -/*! @{ */ - -#define SYSCON_FLEXFRG6CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG6CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG6CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG6CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG6CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG6CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG6CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG6CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 */ -/*! @{ */ - -#define SYSCON_FLEXFRG7CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG7CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG7CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG7CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG7CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG7CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG7CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG7CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRGXCTRL - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_FLEXFRGXCTRL_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_FLEXFRGXCTRL_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_FLEXFRGXCTRL_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRGXCTRL_DATA_SHIFT)) & SYSCON_FLEXFRGXCTRL_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_FLEXFRGXCTRL */ -#define SYSCON_FLEXFRGXCTRL_COUNT (8U) - -/*! @name AHBCLKDIV - System clock divider */ -/*! @{ */ - -#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) - -#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) - -#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) - -#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name CLKOUTDIV - CLKOUT clock divider */ -/*! @{ */ - -#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) -#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) - -#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) -#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) - -#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) -#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) - -#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name FROHFDIV - FRO_HF (96MHz) clock divider */ -/*! @{ */ - -#define SYSCON_FROHFDIV_DIV_MASK (0xFFU) -#define SYSCON_FROHFDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) - -#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U) -#define SYSCON_FROHFDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK) - -#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) -#define SYSCON_FROHFDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) - -#define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_FROHFDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name WDTCLKDIV - WDT clock divider */ -/*! @{ */ - -#define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU) -#define SYSCON_WDTCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_WDTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK) - -#define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_WDTCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_WDTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK) - -#define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_WDTCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_WDTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK) - -#define SYSCON_WDTCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_WDTCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_WDTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_REQFLAG_SHIFT)) & SYSCON_WDTCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name ADCCLKDIV - ADC clock divider */ -/*! @{ */ - -#define SYSCON_ADCCLKDIV_DIV_MASK (0x7U) -#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) - -#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) - -#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) - -#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name MCLKDIV - I2S MCLK clock divider */ -/*! @{ */ - -#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_MCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) - -#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_MCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) - -#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_MCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) - -#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name SCTCLKDIV - SCT/PWM clock divider */ -/*! @{ */ - -#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) - -#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) - -#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) - -#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name PLL0CLKDIV - PLL0 clock divider */ -/*! @{ */ - -#define SYSCON_PLL0CLKDIV_DIV_MASK (0xFFU) -#define SYSCON_PLL0CLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_PLL0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_DIV_SHIFT)) & SYSCON_PLL0CLKDIV_DIV_MASK) - -#define SYSCON_PLL0CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_PLL0CLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_PLL0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_RESET_SHIFT)) & SYSCON_PLL0CLKDIV_RESET_MASK) - -#define SYSCON_PLL0CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_PLL0CLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_PLL0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_HALT_SHIFT)) & SYSCON_PLL0CLKDIV_HALT_MASK) - -#define SYSCON_PLL0CLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_PLL0CLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_PLL0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_REQFLAG_SHIFT)) & SYSCON_PLL0CLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) */ -/*! @{ */ - -#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK (0xFFFFFFFFU) -#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT (0U) -/*! CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (for example, xxxDIV, xxxSEL). - * 0b00000000000000000000000000000001..update all clock configuration. - * 0b00000000000000000000000000000000..all hardware clock configruration are freeze. - */ -#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK) -/*! @} */ - -/*! @name FMCCR - FMC configuration register */ -/*! @{ */ - -#define SYSCON_FMCCR_FETCHCFG_MASK (0x3U) -#define SYSCON_FMCCR_FETCHCFG_SHIFT (0U) -/*! FETCHCFG - Instruction fetch configuration. - * 0b00..Instruction fetches from flash are not buffered. - * 0b01..One buffer is used for all instruction fetches. - * 0b10..All buffers may be used for instruction fetches. - */ -#define SYSCON_FMCCR_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCFG_SHIFT)) & SYSCON_FMCCR_FETCHCFG_MASK) - -#define SYSCON_FMCCR_DATACFG_MASK (0xCU) -#define SYSCON_FMCCR_DATACFG_SHIFT (2U) -/*! DATACFG - Data read configuration. - * 0b00..Data accesses from flash are not buffered. - * 0b01..One buffer is used for all data accesses. - * 0b10..All buffers can be used for data accesses. - */ -#define SYSCON_FMCCR_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACFG_SHIFT)) & SYSCON_FMCCR_DATACFG_MASK) - -#define SYSCON_FMCCR_ACCEL_MASK (0x10U) -#define SYSCON_FMCCR_ACCEL_SHIFT (4U) -/*! ACCEL - Acceleration enable. - * 0b0..Flash acceleration is disabled. - * 0b1..Flash acceleration is enabled. - */ -#define SYSCON_FMCCR_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK) - -#define SYSCON_FMCCR_PREFEN_MASK (0x20U) -#define SYSCON_FMCCR_PREFEN_SHIFT (5U) -/*! PREFEN - Prefetch enable. - * 0b0..No instruction prefetch is performed. - * 0b1..Instruction prefetch is enabled. - */ -#define SYSCON_FMCCR_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK) - -#define SYSCON_FMCCR_PREFOVR_MASK (0x40U) -#define SYSCON_FMCCR_PREFOVR_SHIFT (6U) -/*! PREFOVR - Prefetch override. - * 0b0..Any previously initiated prefetch will be completed. - * 0b1..Any previously initiated prefetch will be aborted, and the next flash line following the current - * execution address will be prefetched if not already buffered. - */ -#define SYSCON_FMCCR_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK) - -#define SYSCON_FMCCR_FLASHTIM_MASK (0xF000U) -#define SYSCON_FMCCR_FLASHTIM_SHIFT (12U) -/*! FLASHTIM - Flash memory access time. - * 0b0000..1 system clock flash access time (for system clock rates up to 11 MHz). - * 0b0001..2 system clocks flash access time (for system clock rates up to 22 MHz). - * 0b0010..3 system clocks flash access time (for system clock rates up to 33 MHz). - * 0b0011..4 system clocks flash access time (for system clock rates up to 44 MHz). - * 0b0100..5 system clocks flash access time (for system clock rates up to 55 MHz). - * 0b0101..6 system clocks flash access time (for system clock rates up to 66 MHz). - * 0b0110..7 system clocks flash access time (for system clock rates up to 84 MHz). - * 0b0111..8 system clocks flash access time (for system clock rates up to 104 MHz). - * 0b1000..9 system clocks flash access time (for system clock rates up to 119 MHz). - * 0b1001..10 system clocks flash access time (for system clock rates up to 129 MHz). - * 0b1010..11 system clocks flash access time (for system clock rates up to 144 MHz). - * 0b1011..12 system clocks flash access time (for system clock rates up to 150 MHz). - */ -#define SYSCON_FMCCR_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FLASHTIM_SHIFT)) & SYSCON_FMCCR_FLASHTIM_MASK) -/*! @} */ - -/*! @name FMCFLUSH - FMCflush control */ -/*! @{ */ - -#define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U) -#define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U) -/*! FLUSH - Flush control - * 0b1..Flush the FMC buffer contents. - * 0b0..No action is performed. - */ -#define SYSCON_FMCFLUSH_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK) -/*! @} */ - -/*! @name MCLKIO - MCLK control */ -/*! @{ */ - -#define SYSCON_MCLKIO_MCLKIO_MASK (0x1U) -#define SYSCON_MCLKIO_MCLKIO_SHIFT (0U) -/*! MCLKIO - MCLK control. - * 0b0..input mode. - * 0b1..output mode. - */ -#define SYSCON_MCLKIO_MCLKIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK) -/*! @} */ - -/*! @name FLASHREMAP_SIZE - This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB. */ -/*! @{ */ - -#define SYSCON_FLASHREMAP_SIZE_FLASHREMAP_SIZE_MASK (0xFFFFFFFFU) -#define SYSCON_FLASHREMAP_SIZE_FLASHREMAP_SIZE_SHIFT (0U) -#define SYSCON_FLASHREMAP_SIZE_FLASHREMAP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHREMAP_SIZE_FLASHREMAP_SIZE_SHIFT)) & SYSCON_FLASHREMAP_SIZE_FLASHREMAP_SIZE_MASK) -/*! @} */ - -/*! @name FLASHREMAP_SIZE_DP - This 32-bit register is a duplicate of FLASHREMAPSIZE for increased security. */ -/*! @{ */ - -#define SYSCON_FLASHREMAP_SIZE_DP_FLASHREMAP_SIZE_MASK (0xFFFFFFFFU) -#define SYSCON_FLASHREMAP_SIZE_DP_FLASHREMAP_SIZE_SHIFT (0U) -#define SYSCON_FLASHREMAP_SIZE_DP_FLASHREMAP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHREMAP_SIZE_DP_FLASHREMAP_SIZE_SHIFT)) & SYSCON_FLASHREMAP_SIZE_DP_FLASHREMAP_SIZE_MASK) -/*! @} */ - -/*! @name FLASHREMAP_OFFSET - This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB. */ -/*! @{ */ - -#define SYSCON_FLASHREMAP_OFFSET_FLASHREMAP_OFFSET_MASK (0xFFFFFFFFU) -#define SYSCON_FLASHREMAP_OFFSET_FLASHREMAP_OFFSET_SHIFT (0U) -#define SYSCON_FLASHREMAP_OFFSET_FLASHREMAP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHREMAP_OFFSET_FLASHREMAP_OFFSET_SHIFT)) & SYSCON_FLASHREMAP_OFFSET_FLASHREMAP_OFFSET_MASK) -/*! @} */ - -/*! @name FLASHREMAP_OFFSET_DP - This 32-bit register is a duplicate of FLASHREMAPOFFSET for increased security. */ -/*! @{ */ - -#define SYSCON_FLASHREMAP_OFFSET_DP_FLASHREMAP_OFFSET_DP_MASK (0xFFFFFFFFU) -#define SYSCON_FLASHREMAP_OFFSET_DP_FLASHREMAP_OFFSET_DP_SHIFT (0U) -#define SYSCON_FLASHREMAP_OFFSET_DP_FLASHREMAP_OFFSET_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHREMAP_OFFSET_DP_FLASHREMAP_OFFSET_DP_SHIFT)) & SYSCON_FLASHREMAP_OFFSET_DP_FLASHREMAP_OFFSET_DP_MASK) -/*! @} */ - -/*! @name FLASHREMAP_LOCK - Control write access to FLASHREMAP_SIZE and FLASHREMAP_OFFSET registers. */ -/*! @{ */ - -#define SYSCON_FLASHREMAP_LOCK_LOCK_MASK (0xFFFFFFFFU) -#define SYSCON_FLASHREMAP_LOCK_LOCK_SHIFT (0U) -/*! LOCK - Control write access to FLASHREMAP_SIZE and FLASHREMAP_OFFSET registers. Any value other - * than 0xC33CA55A and 0x3CC35AA5 does not modify the state. - * 0b00111100110000110101101010100101..Write access to 4 registers FLASHREMAP_SIZE* and FLASHREMAP_OFFSET* is unlocked. - * 0b11000011001111001010010101011010..Write access to 4 registers FLASHREMAP_SIZE* and FLASHREMAP_OFFSET* is locked. - */ -#define SYSCON_FLASHREMAP_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHREMAP_LOCK_LOCK_SHIFT)) & SYSCON_FLASHREMAP_LOCK_LOCK_MASK) -/*! @} */ - -/*! @name CASPER_CTRL - Control CASPER integration. */ -/*! @{ */ - -#define SYSCON_CASPER_CTRL_INTERLEAVE_MASK (0x1U) -#define SYSCON_CASPER_CTRL_INTERLEAVE_SHIFT (0U) -/*! INTERLEAVE - Control RAM access for RAMX0 and RAMX1. - * 0b1..RAM access to RAMX0 and RAMX1 is interleaved. - * 0b0..RAM access to RAMX0 and RAMX1 is consecutive. - */ -#define SYSCON_CASPER_CTRL_INTERLEAVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CASPER_CTRL_INTERLEAVE_SHIFT)) & SYSCON_CASPER_CTRL_INTERLEAVE_MASK) -/*! @} */ - -/*! @name PLL1CTRL - PLL1 550m control */ -/*! @{ */ - -#define SYSCON_PLL1CTRL_SELR_MASK (0xFU) -#define SYSCON_PLL1CTRL_SELR_SHIFT (0U) -/*! SELR - Bandwidth select R value. - */ -#define SYSCON_PLL1CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK) - -#define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U) -#define SYSCON_PLL1CTRL_SELI_SHIFT (4U) -/*! SELI - Bandwidth select I value. - */ -#define SYSCON_PLL1CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK) - -#define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U) -#define SYSCON_PLL1CTRL_SELP_SHIFT (10U) -/*! SELP - Bandwidth select P value. - */ -#define SYSCON_PLL1CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U) -#define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U) -/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - * 0b1..PLL input clock is sent directly to the PLL output. - * 0b0..use PLL. - */ -#define SYSCON_PLL1CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U) -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U) -/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - * 0b1..bypass of the divide-by-2 divider in the post-divider. - * 0b0..use the divide-by-2 divider in the post-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) - -#define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U) -#define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U) -/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. - */ -#define SYSCON_PLL1CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK) - -#define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U) -#define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U) -/*! BWDIRECT - control of the bandwidth of the PLL. - * 0b1..modify the bandwidth of the PLL directly. - * 0b0..the bandwidth is changed synchronously with the feedback-divider. - */ -#define SYSCON_PLL1CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U) -#define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U) -/*! BYPASSPREDIV - bypass of the pre-divider. - * 0b1..bypass of the pre-divider. - * 0b0..use the pre-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U) -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U) -/*! BYPASSPOSTDIV - bypass of the post-divider. - * 0b1..bypass of the post-divider. - * 0b0..use the post-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) - -#define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U) -#define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U) -/*! CLKEN - enable the output clock. - * 0b1..Enable the output clock. - * 0b0..Disable the output clock. - */ -#define SYSCON_PLL1CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK) - -#define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U) -#define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U) -/*! FRMEN - 1: free running mode. - */ -#define SYSCON_PLL1CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK) - -#define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U) -#define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U) -/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable. - */ -#define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK) - -#define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U) -#define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U) -/*! SKEWEN - Skew mode. - * 0b1..skewmode is enable. - * 0b0..skewmode is disable. - */ -#define SYSCON_PLL1CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK) -/*! @} */ - -/*! @name PLL1STAT - PLL1 550m status */ -/*! @{ */ - -#define SYSCON_PLL1STAT_LOCK_MASK (0x1U) -#define SYSCON_PLL1STAT_LOCK_SHIFT (0U) -/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. - */ -#define SYSCON_PLL1STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK) - -#define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U) -#define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U) -/*! PREDIVACK - pre-divider ratio change acknowledge. - */ -#define SYSCON_PLL1STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK) - -#define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U) -#define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U) -/*! FEEDDIVACK - feedback divider ratio change acknowledge. - */ -#define SYSCON_PLL1STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK) - -#define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U) -#define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U) -/*! POSTDIVACK - post-divider ratio change acknowledge. - */ -#define SYSCON_PLL1STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK) - -#define SYSCON_PLL1STAT_FRMDET_MASK (0x10U) -#define SYSCON_PLL1STAT_FRMDET_SHIFT (4U) -/*! FRMDET - free running detector output (active high). - */ -#define SYSCON_PLL1STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK) -/*! @} */ - -/*! @name PLL1NDEC - PLL1 550m N divider */ -/*! @{ */ - -#define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU) -#define SYSCON_PLL1NDEC_NDIV_SHIFT (0U) -/*! NDIV - pre-divider divider ratio (N-divider). - */ -#define SYSCON_PLL1NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK) - -#define SYSCON_PLL1NDEC_NREQ_MASK (0x100U) -#define SYSCON_PLL1NDEC_NREQ_SHIFT (8U) -/*! NREQ - pre-divider ratio change request. - */ -#define SYSCON_PLL1NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK) -/*! @} */ - -/*! @name PLL1MDEC - PLL1 550m M divider */ -/*! @{ */ - -#define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU) -#define SYSCON_PLL1MDEC_MDIV_SHIFT (0U) -/*! MDIV - feedback divider divider ratio (M-divider). - */ -#define SYSCON_PLL1MDEC_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK) - -#define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U) -#define SYSCON_PLL1MDEC_MREQ_SHIFT (16U) -/*! MREQ - feedback ratio change request. - */ -#define SYSCON_PLL1MDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK) -/*! @} */ - -/*! @name PLL1PDEC - PLL1 550m P divider */ -/*! @{ */ - -#define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU) -#define SYSCON_PLL1PDEC_PDIV_SHIFT (0U) -/*! PDIV - post-divider divider ratio (P-divider) - */ -#define SYSCON_PLL1PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK) - -#define SYSCON_PLL1PDEC_PREQ_MASK (0x20U) -#define SYSCON_PLL1PDEC_PREQ_SHIFT (5U) -/*! PREQ - feedback ratio change request. - */ -#define SYSCON_PLL1PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK) -/*! @} */ - -/*! @name PLL0CTRL - PLL0 550m control */ -/*! @{ */ - -#define SYSCON_PLL0CTRL_SELR_MASK (0xFU) -#define SYSCON_PLL0CTRL_SELR_SHIFT (0U) -/*! SELR - Bandwidth select R value. - */ -#define SYSCON_PLL0CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK) - -#define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U) -#define SYSCON_PLL0CTRL_SELI_SHIFT (4U) -/*! SELI - Bandwidth select I value. - */ -#define SYSCON_PLL0CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK) - -#define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U) -#define SYSCON_PLL0CTRL_SELP_SHIFT (10U) -/*! SELP - Bandwidth select P value. - */ -#define SYSCON_PLL0CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U) -#define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U) -/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - * 0b1..Bypass PLL input clock is sent directly to the PLL output. - * 0b0..use PLL. - */ -#define SYSCON_PLL0CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U) -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U) -/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - * 0b1..bypass of the divide-by-2 divider in the post-divider. - * 0b0..use the divide-by-2 divider in the post-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) - -#define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U) -#define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U) -/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. - */ -#define SYSCON_PLL0CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK) - -#define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U) -#define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U) -/*! BWDIRECT - Control of the bandwidth of the PLL. - * 0b1..modify the bandwidth of the PLL directly. - * 0b0..the bandwidth is changed synchronously with the feedback-divider. - */ -#define SYSCON_PLL0CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U) -#define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U) -/*! BYPASSPREDIV - bypass of the pre-divider. - * 0b1..bypass of the pre-divider. - * 0b0..use the pre-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U) -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U) -/*! BYPASSPOSTDIV - bypass of the post-divider. - * 0b1..bypass of the post-divider. - * 0b0..use the post-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) - -#define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U) -#define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U) -/*! CLKEN - enable the output clock. - * 0b1..enable the output clock. - * 0b0..disable the output clock. - */ -#define SYSCON_PLL0CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK) - -#define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U) -#define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U) -/*! FRMEN - free running mode. - * 0b1..free running mode is enable. - * 0b0..free running mode is disable. - */ -#define SYSCON_PLL0CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK) - -#define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U) -#define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U) -/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable. - */ -#define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK) - -#define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U) -#define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U) -/*! SKEWEN - skew mode. - * 0b1..skew mode is enable. - * 0b0..skew mode is disable. - */ -#define SYSCON_PLL0CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK) -/*! @} */ - -/*! @name PLL0STAT - PLL0 550m status */ -/*! @{ */ - -#define SYSCON_PLL0STAT_LOCK_MASK (0x1U) -#define SYSCON_PLL0STAT_LOCK_SHIFT (0U) -/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. - */ -#define SYSCON_PLL0STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK) - -#define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U) -#define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U) -/*! PREDIVACK - pre-divider ratio change acknowledge. - */ -#define SYSCON_PLL0STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK) - -#define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U) -#define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U) -/*! FEEDDIVACK - feedback divider ratio change acknowledge. - */ -#define SYSCON_PLL0STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK) - -#define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U) -#define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U) -/*! POSTDIVACK - post-divider ratio change acknowledge. - */ -#define SYSCON_PLL0STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK) - -#define SYSCON_PLL0STAT_FRMDET_MASK (0x10U) -#define SYSCON_PLL0STAT_FRMDET_SHIFT (4U) -/*! FRMDET - free running detector output (active high). - */ -#define SYSCON_PLL0STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK) -/*! @} */ - -/*! @name PLL0NDEC - PLL0 550m N divider */ -/*! @{ */ - -#define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU) -#define SYSCON_PLL0NDEC_NDIV_SHIFT (0U) -/*! NDIV - pre-divider divider ratio (N-divider). - */ -#define SYSCON_PLL0NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK) - -#define SYSCON_PLL0NDEC_NREQ_MASK (0x100U) -#define SYSCON_PLL0NDEC_NREQ_SHIFT (8U) -/*! NREQ - pre-divider ratio change request. - */ -#define SYSCON_PLL0NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK) -/*! @} */ - -/*! @name PLL0PDEC - PLL0 550m P divider */ -/*! @{ */ - -#define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU) -#define SYSCON_PLL0PDEC_PDIV_SHIFT (0U) -/*! PDIV - post-divider divider ratio (P-divider) - */ -#define SYSCON_PLL0PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK) - -#define SYSCON_PLL0PDEC_PREQ_MASK (0x20U) -#define SYSCON_PLL0PDEC_PREQ_SHIFT (5U) -/*! PREQ - feedback ratio change request. - */ -#define SYSCON_PLL0PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK) -/*! @} */ - -/*! @name PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 */ -/*! @{ */ - -#define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU) -#define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U) -/*! MD_LBS - input word of the wrapper bit 31 to 0. - */ -#define SYSCON_PLL0SSCG0_MD_LBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK) -/*! @} */ - -/*! @name PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 */ -/*! @{ */ - -#define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U) -#define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U) -/*! MD_MBS - input word of the wrapper bit 32. - */ -#define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK) - -#define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U) -#define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U) -/*! MD_REQ - md change request. - */ -#define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK) - -#define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) -#define SYSCON_PLL0SSCG1_MF_SHIFT (2U) -/*! MF - programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3. - */ -#define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK) - -#define SYSCON_PLL0SSCG1_MR_MASK (0xE0U) -#define SYSCON_PLL0SSCG1_MR_SHIFT (5U) -/*! MR - programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) - * mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1. - */ -#define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK) - -#define SYSCON_PLL0SSCG1_MC_MASK (0x300U) -#define SYSCON_PLL0SSCG1_MC_SHIFT (8U) -/*! MC - modulation waveform control Compensation for low pass filtering of the PLL to get a - * triangular modulation at the output of the PLL, giving a flat frequency spectrum. - */ -#define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK) - -#define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U) -#define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U) -/*! MDIV_EXT - to select an external mdiv value. - */ -#define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) - -#define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U) -#define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U) -/*! MREQ - to select an external mreq value. - */ -#define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK) - -#define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U) -#define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U) -/*! DITHER - dithering between two modulation frequencies in a random way or in a pseudo random way - * (white noise), in order to decrease the probability that the modulated waveform will occur - * with the same phase on a particular point on the screen. - */ -#define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK) - -#define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U) -#define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U) -/*! SEL_EXT - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext. - */ -#define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK) -/*! @} */ - -/*! @name FUNCRETENTIONCTRL - Functional retention control register */ -/*! @{ */ - -#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK (0x1U) -#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT (0U) -/*! FUNCRETENA - functional retention in power down only. - * 0b1..enable functional retention. - * 0b0..disable functional retention. - */ -#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK) - -#define SYSCON_FUNCRETENTIONCTRL_RET_START_MASK (0x3FFEU) -#define SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT (1U) -/*! RET_START - Start address divided by 4 inside SRAMX bank. - */ -#define SYSCON_FUNCRETENTIONCTRL_RET_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_START_MASK) - -#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK (0xFFC000U) -#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT (14U) -/*! RET_LENTH - lenth of Scan chains to save. - */ -#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) -/*! @} */ - -/*! @name CPSTAT - CPU Status */ -/*! @{ */ - -#define SYSCON_CPSTAT_CPU0SLEEPING_MASK (0x1U) -#define SYSCON_CPSTAT_CPU0SLEEPING_SHIFT (0U) -/*! CPU0SLEEPING - The CPU0 sleeping state. - * 0b1..the CPU is sleeping. - * 0b0..the CPU is not sleeping. - */ -#define SYSCON_CPSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU0SLEEPING_MASK) - -#define SYSCON_CPSTAT_CPU0LOCKUP_MASK (0x4U) -#define SYSCON_CPSTAT_CPU0LOCKUP_SHIFT (2U) -/*! CPU0LOCKUP - The CPU0 lockup state. - * 0b1..the CPU is in lockup. - * 0b0..the CPU is not in lockup. - */ -#define SYSCON_CPSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU0LOCKUP_MASK) -/*! @} */ - -/*! @name BOOT_SEED_REG0 - boot seed (256-bit random value) */ -/*! @{ */ - -#define SYSCON_BOOT_SEED_REG0_BOOT_SEED_REG0_MASK (0xFFFFFFFFU) -#define SYSCON_BOOT_SEED_REG0_BOOT_SEED_REG0_SHIFT (0U) -#define SYSCON_BOOT_SEED_REG0_BOOT_SEED_REG0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG0_BOOT_SEED_REG0_SHIFT)) & SYSCON_BOOT_SEED_REG0_BOOT_SEED_REG0_MASK) -/*! @} */ - -/*! @name BOOT_SEED_REG1 - boot seed (256-bit random value) */ -/*! @{ */ - -#define SYSCON_BOOT_SEED_REG1_BOOT_SEED_REG1_MASK (0xFFFFFFFFU) -#define SYSCON_BOOT_SEED_REG1_BOOT_SEED_REG1_SHIFT (0U) -#define SYSCON_BOOT_SEED_REG1_BOOT_SEED_REG1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG1_BOOT_SEED_REG1_SHIFT)) & SYSCON_BOOT_SEED_REG1_BOOT_SEED_REG1_MASK) -/*! @} */ - -/*! @name BOOT_SEED_REG2 - boot seed (256-bit random value) */ -/*! @{ */ - -#define SYSCON_BOOT_SEED_REG2_BOOT_SEED_REG2_MASK (0xFFFFFFFFU) -#define SYSCON_BOOT_SEED_REG2_BOOT_SEED_REG2_SHIFT (0U) -#define SYSCON_BOOT_SEED_REG2_BOOT_SEED_REG2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG2_BOOT_SEED_REG2_SHIFT)) & SYSCON_BOOT_SEED_REG2_BOOT_SEED_REG2_MASK) -/*! @} */ - -/*! @name BOOT_SEED_REG3 - boot seed (256-bit random value) */ -/*! @{ */ - -#define SYSCON_BOOT_SEED_REG3_BOOT_SEED_REG3_MASK (0xFFFFFFFFU) -#define SYSCON_BOOT_SEED_REG3_BOOT_SEED_REG3_SHIFT (0U) -#define SYSCON_BOOT_SEED_REG3_BOOT_SEED_REG3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG3_BOOT_SEED_REG3_SHIFT)) & SYSCON_BOOT_SEED_REG3_BOOT_SEED_REG3_MASK) -/*! @} */ - -/*! @name BOOT_SEED_REG4 - boot seed (256-bit random value) */ -/*! @{ */ - -#define SYSCON_BOOT_SEED_REG4_BOOT_SEED_REG4_MASK (0xFFFFFFFFU) -#define SYSCON_BOOT_SEED_REG4_BOOT_SEED_REG4_SHIFT (0U) -#define SYSCON_BOOT_SEED_REG4_BOOT_SEED_REG4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG4_BOOT_SEED_REG4_SHIFT)) & SYSCON_BOOT_SEED_REG4_BOOT_SEED_REG4_MASK) -/*! @} */ - -/*! @name BOOT_SEED_REG5 - boot seed (256-bit random value) */ -/*! @{ */ - -#define SYSCON_BOOT_SEED_REG5_BOOT_SEED_REG5_MASK (0xFFFFFFFFU) -#define SYSCON_BOOT_SEED_REG5_BOOT_SEED_REG5_SHIFT (0U) -#define SYSCON_BOOT_SEED_REG5_BOOT_SEED_REG5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG5_BOOT_SEED_REG5_SHIFT)) & SYSCON_BOOT_SEED_REG5_BOOT_SEED_REG5_MASK) -/*! @} */ - -/*! @name BOOT_SEED_REG6 - boot seed (256-bit random value) */ -/*! @{ */ - -#define SYSCON_BOOT_SEED_REG6_BOOT_SEED_REG6_MASK (0xFFFFFFFFU) -#define SYSCON_BOOT_SEED_REG6_BOOT_SEED_REG6_SHIFT (0U) -#define SYSCON_BOOT_SEED_REG6_BOOT_SEED_REG6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG6_BOOT_SEED_REG6_SHIFT)) & SYSCON_BOOT_SEED_REG6_BOOT_SEED_REG6_MASK) -/*! @} */ - -/*! @name BOOT_SEED_REG7 - boot seed (256-bit random value) */ -/*! @{ */ - -#define SYSCON_BOOT_SEED_REG7_BOOT_SEED_REG7_MASK (0xFFFFFFFFU) -#define SYSCON_BOOT_SEED_REG7_BOOT_SEED_REG7_SHIFT (0U) -#define SYSCON_BOOT_SEED_REG7_BOOT_SEED_REG7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG7_BOOT_SEED_REG7_SHIFT)) & SYSCON_BOOT_SEED_REG7_BOOT_SEED_REG7_MASK) -/*! @} */ - -/*! @name HMAC_REG0 - HMAC */ -/*! @{ */ - -#define SYSCON_HMAC_REG0_HMAC_REG0_MASK (0xFFFFFFFFU) -#define SYSCON_HMAC_REG0_HMAC_REG0_SHIFT (0U) -#define SYSCON_HMAC_REG0_HMAC_REG0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG0_HMAC_REG0_SHIFT)) & SYSCON_HMAC_REG0_HMAC_REG0_MASK) -/*! @} */ - -/*! @name HMAC_REG1 - HMAC */ -/*! @{ */ - -#define SYSCON_HMAC_REG1_HMAC_REG1_MASK (0xFFFFFFFFU) -#define SYSCON_HMAC_REG1_HMAC_REG1_SHIFT (0U) -#define SYSCON_HMAC_REG1_HMAC_REG1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG1_HMAC_REG1_SHIFT)) & SYSCON_HMAC_REG1_HMAC_REG1_MASK) -/*! @} */ - -/*! @name HMAC_REG2 - HMAC */ -/*! @{ */ - -#define SYSCON_HMAC_REG2_HMAC_REG2_MASK (0xFFFFFFFFU) -#define SYSCON_HMAC_REG2_HMAC_REG2_SHIFT (0U) -#define SYSCON_HMAC_REG2_HMAC_REG2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG2_HMAC_REG2_SHIFT)) & SYSCON_HMAC_REG2_HMAC_REG2_MASK) -/*! @} */ - -/*! @name HMAC_REG3 - HMAC */ -/*! @{ */ - -#define SYSCON_HMAC_REG3_HMAC_REG3_MASK (0xFFFFFFFFU) -#define SYSCON_HMAC_REG3_HMAC_REG3_SHIFT (0U) -#define SYSCON_HMAC_REG3_HMAC_REG3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG3_HMAC_REG3_SHIFT)) & SYSCON_HMAC_REG3_HMAC_REG3_MASK) -/*! @} */ - -/*! @name HMAC_REG4 - HMAC */ -/*! @{ */ - -#define SYSCON_HMAC_REG4_HMAC_REG4_MASK (0xFFFFFFFFU) -#define SYSCON_HMAC_REG4_HMAC_REG4_SHIFT (0U) -#define SYSCON_HMAC_REG4_HMAC_REG4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG4_HMAC_REG4_SHIFT)) & SYSCON_HMAC_REG4_HMAC_REG4_MASK) -/*! @} */ - -/*! @name HMAC_REG5 - HMAC */ -/*! @{ */ - -#define SYSCON_HMAC_REG5_HMAC_REG5_MASK (0xFFFFFFFFU) -#define SYSCON_HMAC_REG5_HMAC_REG5_SHIFT (0U) -#define SYSCON_HMAC_REG5_HMAC_REG5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG5_HMAC_REG5_SHIFT)) & SYSCON_HMAC_REG5_HMAC_REG5_MASK) -/*! @} */ - -/*! @name HMAC_REG6 - HMAC */ -/*! @{ */ - -#define SYSCON_HMAC_REG6_HMAC_REG6_MASK (0xFFFFFFFFU) -#define SYSCON_HMAC_REG6_HMAC_REG6_SHIFT (0U) -#define SYSCON_HMAC_REG6_HMAC_REG6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG6_HMAC_REG6_SHIFT)) & SYSCON_HMAC_REG6_HMAC_REG6_MASK) -/*! @} */ - -/*! @name HMAC_REG7 - HMAC */ -/*! @{ */ - -#define SYSCON_HMAC_REG7_HMAC_REG7_MASK (0xFFFFFFFFU) -#define SYSCON_HMAC_REG7_HMAC_REG7_SHIFT (0U) -#define SYSCON_HMAC_REG7_HMAC_REG7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG7_HMAC_REG7_SHIFT)) & SYSCON_HMAC_REG7_HMAC_REG7_MASK) -/*! @} */ - -/*! @name BOOT_LOCK - Control write access to boot seed security registers. */ -/*! @{ */ - -#define SYSCON_BOOT_LOCK_LOCK_BOOT_SEED_MASK (0x1U) -#define SYSCON_BOOT_LOCK_LOCK_BOOT_SEED_SHIFT (0U) -/*! LOCK_BOOT_SEED - Control write access to BOOT_SEED_REG registers. - * 0b1..write access to all 8 registers BOOT_SEED_REG is locked. This register is write once. - */ -#define SYSCON_BOOT_LOCK_LOCK_BOOT_SEED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_LOCK_LOCK_BOOT_SEED_SHIFT)) & SYSCON_BOOT_LOCK_LOCK_BOOT_SEED_MASK) - -#define SYSCON_BOOT_LOCK_LOCK_HMAC_MASK (0x2U) -#define SYSCON_BOOT_LOCK_LOCK_HMAC_SHIFT (1U) -/*! LOCK_HMAC - Control write access to HMAC_REG registers. - * 0b1..write access to all 8 registers HMAC_REG is locked. This register is write once. - */ -#define SYSCON_BOOT_LOCK_LOCK_HMAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_LOCK_LOCK_HMAC_SHIFT)) & SYSCON_BOOT_LOCK_LOCK_HMAC_MASK) -/*! @} */ - -/*! @name CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures */ -/*! @{ */ - -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U) -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U) -/*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U) -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U) -/*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U) -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U) -/*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U) -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U) -/*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) -#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) -/*! CLKIN_ENA - Enable clock_in clock for clock module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) -/*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U) -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U) -/*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U) -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U) -/*! XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U) -#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U) -/*! PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK) -/*! @} */ - -/*! @name COMP_INT_CTRL - Comparator Interrupt control */ -/*! @{ */ - -#define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U) -#define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U) -/*! INT_ENABLE - Analog Comparator interrupt enable control:. - * 0b1..interrupt enable. - * 0b0..interrupt disable. - */ -#define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK) - -#define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U) -#define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U) -/*! INT_CLEAR - Analog Comparator interrupt clear. - * 0b0..No effect. - * 0b1..Clear the interrupt. Self-cleared bit. - */ -#define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK) - -#define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU) -#define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U) -/*! INT_CTRL - Comparator interrupt type selector:. - * 0b000..The analog comparator interrupt edge sensitive is disabled. - * 0b010..analog comparator interrupt is rising edge sensitive. - * 0b100..analog comparator interrupt is falling edge sensitive. - * 0b110..analog comparator interrupt is rising and falling edge sensitive. - * 0b001..The analog comparator interrupt level sensitive is disabled. - * 0b011..Analog Comparator interrupt is high level sensitive. - * 0b101..Analog Comparator interrupt is low level sensitive. - * 0b111..The analog comparator interrupt level sensitive is disabled. - */ -#define SYSCON_COMP_INT_CTRL_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK) - -#define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U) -#define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U) -/*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. - * 0b0..Select Analog Comparator filtered output as input for interrupt detection. - * 0b1..Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when - * Analog comparator is used as wake up source in Power down mode. - */ -#define SYSCON_COMP_INT_CTRL_INT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK) -/*! @} */ - -/*! @name COMP_INT_STATUS - Comparator Interrupt status */ -/*! @{ */ - -#define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U) -#define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U) -/*! STATUS - Interrupt status BEFORE Interrupt Enable. - * 0b0..no interrupt pending. - * 0b1..interrupt pending. - */ -#define SYSCON_COMP_INT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK) - -#define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U) -#define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U) -/*! INT_STATUS - Interrupt status AFTER Interrupt Enable. - * 0b0..no interrupt pending. - * 0b1..interrupt pending. - */ -#define SYSCON_COMP_INT_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) - -#define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U) -#define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U) -/*! VAL - comparator analog output. - * 0b1..P+ is greater than P-. - * 0b0..P+ is smaller than P-. - */ -#define SYSCON_COMP_INT_STATUS_VAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK) -/*! @} */ - -/*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */ -/*! @{ */ - -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U) -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U) -/*! ROM - Control automatic clock gating of ROM controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK (0x2U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT (1U) -/*! RAMX_CTRL - Control automatic clock gating of RAMX controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK (0x4U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT (2U) -/*! RAM0_CTRL - Control automatic clock gating of RAM0 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK (0x8U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT (3U) -/*! RAM1_CTRL - Control automatic clock gating of RAM1 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK (0x10U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT (4U) -/*! RAM2_CTRL - Control automatic clock gating of RAM2 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U) -/*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U) -/*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U) -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U) -/*! CRCGEN - Control automatic clock gating of CRCGEN controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U) -/*! SDMA0 - Control automatic clock gating of DMA0 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U) -/*! SDMA1 - Control automatic clock gating of DMA1 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U) -/*! SYSCON - Control automatic clock gating of synchronous system controller registers bank. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U) -/*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. - * 0b1100000011011110..Bit Fields 0 - 15 of this register are updated - * 0b0000000000000000..Bit Fields 0 - 15 of this register are not updated - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK) -/*! @} */ - -/*! @name GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module */ -/*! @{ */ - -#define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U) -#define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U) -/*! PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module. - * 0b1..bypass of the first stage of synchonization inside GPIO_INT module. - * 0b0..use the first stage of synchonization inside GPIO_INT module. - */ -#define SYSCON_GPIOPSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK) -/*! @} */ - -/*! @name HASHRESTHWKEY - Controls whether the HASH AES hardware secret key is restricted to use by secure code */ -/*! @{ */ - -#define SYSCON_HASHRESTHWKEY_UNLOCKCODE_MASK (0xFFFFFFFFU) -#define SYSCON_HASHRESTHWKEY_UNLOCKCODE_SHIFT (0U) -/*! UNLOCKCODE - Code value that controls whether HASH AES hardware secret key is unlocked - * 0b11000011001111001010010101011010..HASH AES hardware secret key is unlocked for use by non-secure code. Any - * other value means that the hardware secret key is restricted to use by - * secure code only. - */ -#define SYSCON_HASHRESTHWKEY_UNLOCKCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HASHRESTHWKEY_UNLOCKCODE_SHIFT)) & SYSCON_HASHRESTHWKEY_UNLOCKCODE_MASK) -/*! @} */ - -/*! @name DEBUG_LOCK_EN - Control write access to security registers. */ -/*! @{ */ - -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) -/*! LOCK_ALL - Control write access to security registers. - * 0b1010..1010: Enable write access to all registers. - * 0b0000..Any other value than b1010: disable write access to all registers. - */ -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) -/*! @} */ - -/*! @name DEBUG_FEATURES - Cortex debug features control. */ -/*! @{ */ - -#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) -#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) -/*! CPU0_DBGEN - CPU0 Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) -#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) -/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK (0x30U) -#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (4U) -/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0xC0U) -#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U) -/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK) -/*! @} */ - -/*! @name DEBUG_FEATURES_DP - Cortex debug features control. (duplicate) */ -/*! @{ */ - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) -/*! CPU0_DBGEN - CPU0 (CPU0) Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) -/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U) -/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U) -/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK) -/*! @} */ - -/*! @name SWD_ACCESS_CPU0 - This register is used by ROM during DEBUG authentication mechanism to enable debug access port for CPU0. */ -/*! @{ */ - -#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE_MASK (0xFFFFFFFFU) -#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE_SHIFT (0U) -/*! SEC_CODE - CPU0 SWD-AP: 0x12345678. - * 0b00010010001101000101011001111000..Value to write to enable CPU0 SWD access. Reading back register will be read as 0xA. - * 0b00000000000000000000000000000000..CPU0 DAP is not allowed. Reading back register will be read as 0x5. - */ -#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU0_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU0_SEC_CODE_MASK) -/*! @} */ - -/*! @name KEY_BLOCK - block quiddikey/PUF all index. */ -/*! @{ */ - -#define SYSCON_KEY_BLOCK_KEY_BLOCK_MASK (0xFFFFFFFFU) -#define SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT (0U) -/*! KEY_BLOCK - Write a value to block quiddikey/PUF all index. - */ -#define SYSCON_KEY_BLOCK_KEY_BLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCON_KEY_BLOCK_KEY_BLOCK_MASK) -/*! @} */ - -/*! @name DEBUG_AUTH_BEACON - Debug authentication BEACON register */ -/*! @{ */ - -#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) -#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) -/*! BEACON - Set by the debug authentication code in ROM to pass the debug beacons (Credential - * Beacon and Authentication Beacon) to application code. - */ -#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) -/*! @} */ - -/*! @name DEVICE_ID0 - Device ID */ -/*! @{ */ - -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) -/*! ROM_REV_MINOR - ROM revision. - */ -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) -/*! @} */ - -/*! @name DIEID - Chip revision ID and Number */ -/*! @{ */ - -#define SYSCON_DIEID_REV_ID_MASK (0xFU) -#define SYSCON_DIEID_REV_ID_SHIFT (0U) -/*! REV_ID - Chip Metal Revision ID. - */ -#define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK) - -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U) -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U) -/*! MCO_NUM_IN_DIE_ID - Chip Number 0x426B. - */ -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SYSCON_Register_Masks */ - - -/* SYSCON - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SYSCON base address */ - #define SYSCON_BASE (0x50000000u) - /** Peripheral SYSCON base address */ - #define SYSCON_BASE_NS (0x40000000u) - /** Peripheral SYSCON base pointer */ - #define SYSCON ((SYSCON_Type *)SYSCON_BASE) - /** Peripheral SYSCON base pointer */ - #define SYSCON_NS ((SYSCON_Type *)SYSCON_BASE_NS) - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS { SYSCON_BASE } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS { SYSCON } - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS_NS { SYSCON_BASE_NS } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS_NS { SYSCON_NS } -#else - /** Peripheral SYSCON base address */ - #define SYSCON_BASE (0x40000000u) - /** Peripheral SYSCON base pointer */ - #define SYSCON ((SYSCON_Type *)SYSCON_BASE) - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS { SYSCON_BASE } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS { SYSCON } -#endif - -/*! - * @} - */ /* end of group SYSCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SYSCTL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCTL_Peripheral_Access_Layer SYSCTL Peripheral Access Layer - * @{ - */ - -/** SYSCTL - Register Layout Typedef */ -typedef struct { - __IO uint32_t UPDATELCKOUT; /**< update lock out control, offset: 0x0 */ - uint8_t RESERVED_0[60]; - __IO uint32_t FCCTRLSEL[8]; /**< Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_1[32]; - __IO uint32_t SHAREDCTRLSET[2]; /**< Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1., array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_2[248]; - __IO uint32_t CODE_GRAY_LSB; /**< CODE_GRAY LSB input Register, offset: 0x180 */ - __IO uint32_t CODE_GRAY_MSB; /**< CODE_GRAY MSB input Register, offset: 0x184 */ - __I uint32_t CODE_BIN_LSB; /**< CODE_BIN LSB output Register, offset: 0x188 */ - __I uint32_t CODE_BIN_MSB; /**< CODE_BIN MSB output Register, offset: 0x18C */ -} SYSCTL_Type; - -/* ---------------------------------------------------------------------------- - -- SYSCTL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCTL_Register_Masks SYSCTL Register Masks - * @{ - */ - -/*! @name UPDATELCKOUT - update lock out control */ -/*! @{ */ - -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U) -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U) -/*! UPDATELCKOUT - All Registers - * 0b0..Normal Mode. Can be written to. - * 0b1..Protected Mode. Cannot be written to. - */ -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK) -/*! @} */ - -/*! @name FCCTRLSEL - Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7 */ -/*! @{ */ - -#define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U) -#define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U) -/*! SCKINSEL - Selects the source for SCK going into this Flexcomm. - * 0b00..Selects the dedicated FCn_SCK function for this Flexcomm. - * 0b01..SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK) - -#define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U) -#define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U) -/*! WSINSEL - Selects the source for WS going into this Flexcomm. - * 0b00..Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. - * 0b01..WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK) - -#define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U) -#define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U) -/*! DATAINSEL - Selects the source for DATA input to this Flexcomm. - * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. - * 0b01..Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK) - -#define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U) -#define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U) -/*! DATAOUTSEL - Selects the source for DATA output from this Flexcomm. - * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. - * 0b01..Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_DATAOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK) -/*! @} */ - -/* The count of SYSCTL_FCCTRLSEL */ -#define SYSCTL_FCCTRLSEL_COUNT (8U) - -/*! @name SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */ -/*! @{ */ - -#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U) -#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U) -/*! SHAREDSCKSEL - Selects the source for SCK of this shared signal set. - * 0b000..SCK for this shared signal set comes from Flexcomm 0. - * 0b001..SCK for this shared signal set comes from Flexcomm 1. - * 0b010..SCK for this shared signal set comes from Flexcomm 2. - * 0b011..SCK for this shared signal set comes from Flexcomm 3. - * 0b100..SCK for this shared signal set comes from Flexcomm 4. - * 0b101..SCK for this shared signal set comes from Flexcomm 5. - * 0b110..SCK for this shared signal set comes from Flexcomm 6. - * 0b111..SCK for this shared signal set comes from Flexcomm 7. - */ -#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK) - -#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U) -#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U) -/*! SHAREDWSSEL - Selects the source for WS of this shared signal set. - * 0b000..WS for this shared signal set comes from Flexcomm 0. - * 0b001..WS for this shared signal set comes from Flexcomm 1. - * 0b010..WS for this shared signal set comes from Flexcomm 2. - * 0b011..WS for this shared signal set comes from Flexcomm 3. - * 0b100..WS for this shared signal set comes from Flexcomm 4. - * 0b101..WS for this shared signal set comes from Flexcomm 5. - * 0b110..WS for this shared signal set comes from Flexcomm 6. - * 0b111..WS for this shared signal set comes from Flexcomm 7. - */ -#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK) - -#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U) -#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U) -/*! SHAREDDATASEL - Selects the source for DATA input for this shared signal set. - * 0b000..DATA input for this shared signal set comes from Flexcomm 0. - * 0b001..DATA input for this shared signal set comes from Flexcomm 1. - * 0b010..DATA input for this shared signal set comes from Flexcomm 2. - * 0b011..DATA input for this shared signal set comes from Flexcomm 3. - * 0b100..DATA input for this shared signal set comes from Flexcomm 4. - * 0b101..DATA input for this shared signal set comes from Flexcomm 5. - * 0b110..DATA input for this shared signal set comes from Flexcomm 6. - * 0b111..DATA input for this shared signal set comes from Flexcomm 7. - */ -#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U) -#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U) -/*! FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC0 does not contribute to this shared set. - * 0b1..Data output from FC0 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U) -#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U) -/*! FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC1 does not contribute to this shared set. - * 0b1..Data output from FC1 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK (0x40000U) -#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT (18U) -/*! FC2DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC2 does not contribute to this shared set. - * 0b1..Data output from FC2 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U) -#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U) -/*! FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC4 does not contribute to this shared set. - * 0b1..Data output from FC4 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U) -#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U) -/*! FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC5 does not contribute to this shared set. - * 0b1..Data output from FC5 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U) -#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U) -/*! FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC6 does not contribute to this shared set. - * 0b1..Data output from FC6 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U) -#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U) -/*! FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC7 does not contribute to this shared set. - * 0b1..Data output from FC7 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK) -/*! @} */ - -/* The count of SYSCTL_SHAREDCTRLSET */ -#define SYSCTL_SHAREDCTRLSET_COUNT (2U) - -/*! @name CODE_GRAY_LSB - CODE_GRAY LSB input Register */ -/*! @{ */ - -#define SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_MASK (0xFFFFFFFFU) -#define SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_SHIFT (0U) -/*! CODE_GRAY_LSB - Gray code (42bits) to be converted back to binary - */ -#define SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_SHIFT)) & SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_MASK) -/*! @} */ - -/*! @name CODE_GRAY_MSB - CODE_GRAY MSB input Register */ -/*! @{ */ - -#define SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_MASK (0x3FFU) -#define SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_SHIFT (0U) -/*! CODE_GRAY_MSB - Gray code (42bits) to be converted back to binary - */ -#define SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_SHIFT)) & SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_MASK) -/*! @} */ - -/*! @name CODE_BIN_LSB - CODE_BIN LSB output Register */ -/*! @{ */ - -#define SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_MASK (0xFFFFFFFFU) -#define SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_SHIFT (0U) -/*! CODE_BIN_LSB - Binary converted code (42bits) - */ -#define SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_SHIFT)) & SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_MASK) -/*! @} */ - -/*! @name CODE_BIN_MSB - CODE_BIN MSB output Register */ -/*! @{ */ - -#define SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_MASK (0x3FFU) -#define SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_SHIFT (0U) -/*! CODE_BIN_MSB - Binary converted code (42bits) - */ -#define SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_SHIFT)) & SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SYSCTL_Register_Masks */ - - -/* SYSCTL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE (0x50023000u) - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE_NS (0x40023000u) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL_NS ((SYSCTL_Type *)SYSCTL_BASE_NS) - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS { SYSCTL } - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS_NS { SYSCTL_BASE_NS } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS_NS { SYSCTL_NS } -#else - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE (0x40023000u) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS { SYSCTL } -#endif - -/*! - * @} - */ /* end of group SYSCTL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USART Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer - * @{ - */ - -/** USART - Register Layout Typedef */ -typedef struct { - __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ - __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ - __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ - uint8_t RESERVED_0[12]; - __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ - __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ - __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ - __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ - uint8_t RESERVED_1[3536]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_2[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_3[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_4[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_6[4]; - __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ - uint8_t RESERVED_7[432]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} USART_Type; - -/* ---------------------------------------------------------------------------- - -- USART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Register_Masks USART Register Masks - * @{ - */ - -/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ -/*! @{ */ - -#define USART_CFG_ENABLE_MASK (0x1U) -#define USART_CFG_ENABLE_SHIFT (0U) -/*! ENABLE - USART Enable. - * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, - * all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control - * bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the - * transmitter has been reset and is therefore available. - * 0b1..Enabled. The USART is enabled for operation. - */ -#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) - -#define USART_CFG_DATALEN_MASK (0xCU) -#define USART_CFG_DATALEN_SHIFT (2U) -/*! DATALEN - Selects the data size for the USART. - * 0b00..7 bit Data length. - * 0b01..8 bit Data length. - * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. - * 0b11..Reserved. - */ -#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) - -#define USART_CFG_PARITYSEL_MASK (0x30U) -#define USART_CFG_PARITYSEL_SHIFT (4U) -/*! PARITYSEL - Selects what type of parity is used by the USART. - * 0b00..No parity. - * 0b01..Reserved. - * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, - * and the number of 1s in a received character is expected to be even. - * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, - * and the number of 1s in a received character is expected to be odd. - */ -#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) - -#define USART_CFG_STOPLEN_MASK (0x40U) -#define USART_CFG_STOPLEN_SHIFT (6U) -/*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. - * 0b0..1 stop bit. - * 0b1..2 stop bits. This setting should only be used for asynchronous communication. - */ -#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) - -#define USART_CFG_MODE32K_MASK (0x80U) -#define USART_CFG_MODE32K_SHIFT (7U) -/*! MODE32K - Selects standard or 32 kHz clocking mode. - * 0b0..Disabled. USART uses standard clocking. - * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. - */ -#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) - -#define USART_CFG_LINMODE_MASK (0x100U) -#define USART_CFG_LINMODE_SHIFT (8U) -/*! LINMODE - LIN break mode enable. - * 0b0..Disabled. Break detect and generate is configured for normal operation. - * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. - */ -#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) - -#define USART_CFG_CTSEN_MASK (0x200U) -#define USART_CFG_CTSEN_SHIFT (9U) -/*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input - * pin, or from the USART's own RTS if loopback mode is enabled. - * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. - * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. - */ -#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) - -#define USART_CFG_SYNCEN_MASK (0x800U) -#define USART_CFG_SYNCEN_SHIFT (11U) -/*! SYNCEN - Selects synchronous or asynchronous operation. - * 0b0..Asynchronous mode. - * 0b1..Synchronous mode. - */ -#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) - -#define USART_CFG_CLKPOL_MASK (0x1000U) -#define USART_CFG_CLKPOL_SHIFT (12U) -/*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. - * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK. - * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. - */ -#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) - -#define USART_CFG_SYNCMST_MASK (0x4000U) -#define USART_CFG_SYNCMST_SHIFT (14U) -/*! SYNCMST - Synchronous mode Master select. - * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. - * 0b1..Master. When synchronous mode is enabled, the USART is a master. - */ -#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) - -#define USART_CFG_LOOP_MASK (0x8000U) -#define USART_CFG_LOOP_SHIFT (15U) -/*! LOOP - Selects data loopback mode. - * 0b0..Normal operation. - * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial - * data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD - * and Un_RTS activity will also appear on external pins if these functions are configured to appear on device - * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. - */ -#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) - -#define USART_CFG_OETA_MASK (0x40000U) -#define USART_CFG_OETA_SHIFT (18U) -/*! OETA - Output Enable Turnaround time enable for RS-485 operation. - * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. - * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the - * end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins - * before it is deasserted. - */ -#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) - -#define USART_CFG_AUTOADDR_MASK (0x80000U) -#define USART_CFG_AUTOADDR_SHIFT (19U) -/*! AUTOADDR - Automatic Address matching enable. - * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the - * possibility of versatile addressing (e.g. respond to more than one address). - * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in - * the ADDR register as the address to match. - */ -#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) - -#define USART_CFG_OESEL_MASK (0x100000U) -#define USART_CFG_OESEL_SHIFT (20U) -/*! OESEL - Output Enable Select. - * 0b0..Standard. The RTS signal is used as the standard flow control function. - * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. - */ -#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) - -#define USART_CFG_OEPOL_MASK (0x200000U) -#define USART_CFG_OEPOL_SHIFT (21U) -/*! OEPOL - Output Enable Polarity. - * 0b0..Low. If selected by OESEL, the output enable is active low. - * 0b1..High. If selected by OESEL, the output enable is active high. - */ -#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) - -#define USART_CFG_RXPOL_MASK (0x400000U) -#define USART_CFG_RXPOL_SHIFT (22U) -/*! RXPOL - Receive data polarity. - * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start - * bit is 0, data is not inverted, and the stop bit is 1. - * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is - * 0, start bit is 1, data is inverted, and the stop bit is 0. - */ -#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) - -#define USART_CFG_TXPOL_MASK (0x800000U) -#define USART_CFG_TXPOL_SHIFT (23U) -/*! TXPOL - Transmit data polarity. - * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is - * 0, data is not inverted, and the stop bit is 1. - * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value - * is 0, start bit is 1, data is inverted, and the stop bit is 0. - */ -#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) -/*! @} */ - -/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ -/*! @{ */ - -#define USART_CTL_TXBRKEN_MASK (0x2U) -#define USART_CTL_TXBRKEN_SHIFT (1U) -/*! TXBRKEN - Break Enable. - * 0b0..Normal operation. - * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit - * is cleared. A break may be sent without danger of corrupting any currently transmitting character if the - * transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled - * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. - */ -#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) - -#define USART_CTL_ADDRDET_MASK (0x4U) -#define USART_CTL_ADDRDET_SHIFT (2U) -/*! ADDRDET - Enable address detect mode. - * 0b0..Disabled. The USART presents all incoming data. - * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data - * (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, - * generating a received data interrupt. Software can then check the data to see if this is an address that - * should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled - * normally. - */ -#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) - -#define USART_CTL_TXDIS_MASK (0x40U) -#define USART_CTL_TXDIS_SHIFT (6U) -/*! TXDIS - Transmit Disable. - * 0b0..Not disabled. USART transmitter is not disabled. - * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This - * feature can be used to facilitate software flow control. - */ -#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) - -#define USART_CTL_CC_MASK (0x100U) -#define USART_CTL_CC_SHIFT (8U) -/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. - * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to - * complete a character that is being received. - * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on - * Un_RxD independently from transmission on Un_TXD). - */ -#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) - -#define USART_CTL_CLRCCONRX_MASK (0x200U) -#define USART_CTL_CLRCCONRX_SHIFT (9U) -/*! CLRCCONRX - Clear Continuous Clock. - * 0b0..No effect. No effect on the CC bit. - * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. - */ -#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) - -#define USART_CTL_AUTOBAUD_MASK (0x10000U) -#define USART_CTL_AUTOBAUD_SHIFT (16U) -/*! AUTOBAUD - Autobaud enable. - * 0b0..Disabled. USART is in normal operating mode. - * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The - * first start bit of RX is measured and used the update the BRG register to match the received data rate. - * AUTOBAUD is cleared once this process is complete, or if there is an AERR. - */ -#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) -/*! @} */ - -/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ -/*! @{ */ - -#define USART_STAT_RXIDLE_MASK (0x2U) -#define USART_STAT_RXIDLE_SHIFT (1U) -/*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of - * receiving data. When 1, indicates that the receiver is not currently in the process of receiving - * data. - */ -#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) - -#define USART_STAT_TXIDLE_MASK (0x8U) -#define USART_STAT_TXIDLE_SHIFT (3U) -/*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of - * sending data.When 1, indicate that the transmitter is not currently in the process of sending - * data. - */ -#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) - -#define USART_STAT_CTS_MASK (0x10U) -#define USART_STAT_CTS_SHIFT (4U) -/*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the - * CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode - * is enabled. - */ -#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) - -#define USART_STAT_DELTACTS_MASK (0x20U) -#define USART_STAT_DELTACTS_SHIFT (5U) -/*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. - */ -#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) - -#define USART_STAT_TXDISSTAT_MASK (0x40U) -#define USART_STAT_TXDISSTAT_SHIFT (6U) -/*! TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART - * transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). - */ -#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) - -#define USART_STAT_RXBRK_MASK (0x400U) -#define USART_STAT_RXBRK_SHIFT (10U) -/*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection - * logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also - * be set when this condition occurs because the stop bit(s) for the character would be missing. - * RXBRK is cleared when the Un_RXD pin goes high. - */ -#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) - -#define USART_STAT_DELTARXBRK_MASK (0x800U) -#define USART_STAT_DELTARXBRK_SHIFT (11U) -/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software. - */ -#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) - -#define USART_STAT_START_MASK (0x1000U) -#define USART_STAT_START_SHIFT (12U) -/*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily - * to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. - * Cleared by software. - */ -#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) - -#define USART_STAT_FRAMERRINT_MASK (0x2000U) -#define USART_STAT_FRAMERRINT_SHIFT (13U) -/*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a - * missing stop bit at the expected location. This could be an indication of a baud rate or - * configuration mismatch with the transmitting source. - */ -#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) - -#define USART_STAT_PARITYERRINT_MASK (0x4000U) -#define USART_STAT_PARITYERRINT_SHIFT (14U) -/*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. - */ -#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) - -#define USART_STAT_RXNOISEINT_MASK (0x8000U) -#define USART_STAT_RXNOISEINT_SHIFT (15U) -/*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to - * determine the value of each received data bit, except in synchronous mode. This acts as a - * noise filter if one sample disagrees. This flag is set when a received data bit contains one - * disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or - * loss of synchronization during data reception. - */ -#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) - -#define USART_STAT_ABERR_MASK (0x10000U) -#define USART_STAT_ABERR_SHIFT (16U) -/*! ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the - * end of the start bit that is being measured, essentially an auto baud time-out. - */ -#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -/*! @{ */ - -#define USART_INTENSET_TXIDLEEN_MASK (0x8U) -#define USART_INTENSET_TXIDLEEN_SHIFT (3U) -/*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). - */ -#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) - -#define USART_INTENSET_DELTACTSEN_MASK (0x20U) -#define USART_INTENSET_DELTACTSEN_SHIFT (5U) -/*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input. - */ -#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) - -#define USART_INTENSET_TXDISEN_MASK (0x40U) -#define USART_INTENSET_TXDISEN_SHIFT (6U) -/*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by - * the TXDISINT flag in STAT. See description of the TXDISINT bit for details. - */ -#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) - -#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) -#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) -/*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection - * of a received break condition (break condition asserted or deasserted). - */ -#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) - -#define USART_INTENSET_STARTEN_MASK (0x1000U) -#define USART_INTENSET_STARTEN_SHIFT (12U) -/*! STARTEN - When 1, enables an interrupt when a received start bit has been detected. - */ -#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) - -#define USART_INTENSET_FRAMERREN_MASK (0x2000U) -#define USART_INTENSET_FRAMERREN_SHIFT (13U) -/*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected. - */ -#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) - -#define USART_INTENSET_PARITYERREN_MASK (0x4000U) -#define USART_INTENSET_PARITYERREN_SHIFT (14U) -/*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected. - */ -#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) - -#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) -#define USART_INTENSET_RXNOISEEN_SHIFT (15U) -/*! RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. - */ -#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) - -#define USART_INTENSET_ABERREN_MASK (0x10000U) -#define USART_INTENSET_ABERREN_SHIFT (16U) -/*! ABERREN - When 1, enables an interrupt when an auto baud error occurs. - */ -#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ -/*! @{ */ - -#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) -#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) -/*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) - -#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) -#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) -/*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) - -#define USART_INTENCLR_TXDISCLR_MASK (0x40U) -#define USART_INTENCLR_TXDISCLR_SHIFT (6U) -/*! TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) - -#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) -#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) -/*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) - -#define USART_INTENCLR_STARTCLR_MASK (0x1000U) -#define USART_INTENCLR_STARTCLR_SHIFT (12U) -/*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) - -#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) -#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) -/*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) - -#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) -#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) -/*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) - -#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) -#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) -/*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) - -#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) -#define USART_INTENCLR_ABERRCLR_SHIFT (16U) -/*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) -/*! @} */ - -/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ -/*! @{ */ - -#define USART_BRG_BRGVAL_MASK (0xFFFFU) -#define USART_BRG_BRGVAL_SHIFT (0U) -/*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on - * the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is - * divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART - * function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. - */ -#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ -/*! @{ */ - -#define USART_INTSTAT_TXIDLE_MASK (0x8U) -#define USART_INTSTAT_TXIDLE_SHIFT (3U) -/*! TXIDLE - Transmitter Idle status. - */ -#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) - -#define USART_INTSTAT_DELTACTS_MASK (0x20U) -#define USART_INTSTAT_DELTACTS_SHIFT (5U) -/*! DELTACTS - This bit is set when a change in the state of the CTS input is detected. - */ -#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) - -#define USART_INTSTAT_TXDISINT_MASK (0x40U) -#define USART_INTSTAT_TXDISINT_SHIFT (6U) -/*! TXDISINT - Transmitter Disabled Interrupt flag. - */ -#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) - -#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) -#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) -/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. - */ -#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) - -#define USART_INTSTAT_START_MASK (0x1000U) -#define USART_INTSTAT_START_SHIFT (12U) -/*! START - This bit is set when a start is detected on the receiver input. - */ -#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) - -#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) -#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) -/*! FRAMERRINT - Framing Error interrupt flag. - */ -#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) - -#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) -#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) -/*! PARITYERRINT - Parity Error interrupt flag. - */ -#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) - -#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) -#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) -/*! RXNOISEINT - Received Noise interrupt flag. - */ -#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) - -#define USART_INTSTAT_ABERRINT_MASK (0x10000U) -#define USART_INTSTAT_ABERRINT_SHIFT (16U) -/*! ABERRINT - Auto baud Error Interrupt flag. - */ -#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) -/*! @} */ - -/*! @name OSR - Oversample selection register for asynchronous communication. */ -/*! @{ */ - -#define USART_OSR_OSRVAL_MASK (0xFU) -#define USART_OSR_OSRVAL_SHIFT (0U) -/*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to - * transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive - * each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. - */ -#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) -/*! @} */ - -/*! @name ADDR - Address register for automatic address matching. */ -/*! @{ */ - -#define USART_ADDR_ADDRESS_MASK (0xFFU) -#define USART_ADDR_ADDRESS_SHIFT (0U) -/*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is - * enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). - */ -#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ - -#define USART_FIFOCFG_ENABLETX_MASK (0x1U) -#define USART_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) - -#define USART_FIFOCFG_ENABLERX_MASK (0x2U) -#define USART_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) - -#define USART_FIFOCFG_SIZE_MASK (0x30U) -#define USART_FIFOCFG_SIZE_SHIFT (4U) -/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 - * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - */ -#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) - -#define USART_FIFOCFG_DMATX_MASK (0x1000U) -#define USART_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) - -#define USART_FIFOCFG_DMARX_MASK (0x2000U) -#define USART_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) - -#define USART_FIFOCFG_WAKETX_MASK (0x4000U) -#define USART_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in - * FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) - -#define USART_FIFOCFG_WAKERX_MASK (0x8000U) -#define USART_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in - * FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) - -#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) -/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - */ -#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) - -#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) -/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - */ -#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ - -#define USART_FIFOSTAT_TXERR_MASK (0x1U) -#define USART_FIFOSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow - * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is - * needed. Cleared by writing a 1 to this bit. - */ -#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) - -#define USART_FIFOSTAT_RXERR_MASK (0x2U) -#define USART_FIFOSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA - * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - */ -#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) - -#define USART_FIFOSTAT_PERINT_MASK (0x8U) -#define USART_FIFOSTAT_PERINT_SHIFT (3U) -/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted - * an interrupt. The details can be found by reading the peripheral's STAT register. - */ -#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) - -#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) -/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - */ -#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) - -#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) -/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be - * written. When 0, the transmit FIFO is full and another write would cause it to overflow. - */ -#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) - -#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - */ -#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) - -#define USART_FIFOSTAT_RXFULL_MASK (0x80U) -#define USART_FIFOSTAT_RXFULL_SHIFT (7U) -/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to - * prevent the peripheral from causing an overflow. - */ -#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) - -#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define USART_FIFOSTAT_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY - * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at - * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be - * 0. - */ -#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) - -#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define USART_FIFOSTAT_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and - * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the - * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be - * 1. - */ -#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ - -#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) - -#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) - -#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) -#define USART_FIFOTRIG_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled - * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to - * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO - * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX - * FIFO level decreases to 15 entries (is no longer full). - */ -#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) - -#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define USART_FIFOTRIG_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data - * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level - * can wake up the device just enough to perform DMA, then return to the reduced power mode. See - * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no - * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX - * FIFO has received 16 entries (has become full). - */ -#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ - -#define USART_FIFOINTENSET_TXERR_MASK (0x1U) -#define USART_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) - -#define USART_FIFOINTENSET_RXERR_MASK (0x2U) -#define USART_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) - -#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) -#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases - * to the level specified by TXLVL in the FIFOTRIG register. - */ -#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) - -#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) -#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level - * increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ - -#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) -#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) -/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) - -#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) -#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) -/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) - -#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) -/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) - -#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) -/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ - -#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) -#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. - */ -#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) - -#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) -#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. - */ -#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) - -#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO level interrupt. - */ -#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) - -#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO level interrupt. - */ -#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) - -#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) -#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) -/*! PERINT - Peripheral interrupt. - */ -#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ - -#define USART_FIFOWR_TXDATA_MASK (0x1FFU) -#define USART_FIFOWR_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit data to the FIFO. - */ -#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ - -#define USART_FIFORD_RXDATA_MASK (0x1FFU) -#define USART_FIFORD_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. - */ -#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) - -#define USART_FIFORD_FRAMERR_MASK (0x2000U) -#define USART_FIFORD_FRAMERR_SHIFT (13U) -/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along - * with from the FIFO, and indicates that the character was received with a missing stop bit at - * the expected location. This could be an indication of a baud rate or configuration mismatch - * with the transmitting source. - */ -#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) - -#define USART_FIFORD_PARITYERR_MASK (0x4000U) -#define USART_FIFORD_PARITYERR_SHIFT (14U) -/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along - * with from the FIFO. This bit will be set when a parity error is detected in a received - * character. - */ -#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) - -#define USART_FIFORD_RXNOISE_MASK (0x8000U) -#define USART_FIFORD_RXNOISE_SHIFT (15U) -/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. - */ -#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ - -#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) -#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. - */ -#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) - -#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) -#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) -/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along - * with from the FIFO, and indicates that the character was received with a missing stop bit at - * the expected location. This could be an indication of a baud rate or configuration mismatch - * with the transmitting source. - */ -#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) - -#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) -#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) -/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along - * with from the FIFO. This bit will be set when a parity error is detected in a received - * character. - */ -#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) - -#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) -#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) -/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. - */ -#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) -/*! @} */ - -/*! @name FIFOSIZE - FIFO size register */ -/*! @{ */ - -#define USART_FIFOSIZE_FIFOSIZE_MASK (0x1FU) -#define USART_FIFOSIZE_FIFOSIZE_SHIFT (0U) -/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - */ -#define USART_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSIZE_FIFOSIZE_SHIFT)) & USART_FIFOSIZE_FIFOSIZE_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ - -#define USART_ID_MINOR_REV_MASK (0xF00U) -#define USART_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation. - */ -#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) - -#define USART_ID_MAJOR_REV_MASK (0xF000U) -#define USART_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation. - */ -#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) - -#define USART_ID_ID_MASK (0xFFFF0000U) -#define USART_ID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function. - */ -#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USART_Register_Masks */ - - -/* USART - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USART0 base address */ - #define USART0_BASE (0x50086000u) - /** Peripheral USART0 base address */ - #define USART0_BASE_NS (0x40086000u) - /** Peripheral USART0 base pointer */ - #define USART0 ((USART_Type *)USART0_BASE) - /** Peripheral USART0 base pointer */ - #define USART0_NS ((USART_Type *)USART0_BASE_NS) - /** Peripheral USART1 base address */ - #define USART1_BASE (0x50087000u) - /** Peripheral USART1 base address */ - #define USART1_BASE_NS (0x40087000u) - /** Peripheral USART1 base pointer */ - #define USART1 ((USART_Type *)USART1_BASE) - /** Peripheral USART1 base pointer */ - #define USART1_NS ((USART_Type *)USART1_BASE_NS) - /** Peripheral USART2 base address */ - #define USART2_BASE (0x50088000u) - /** Peripheral USART2 base address */ - #define USART2_BASE_NS (0x40088000u) - /** Peripheral USART2 base pointer */ - #define USART2 ((USART_Type *)USART2_BASE) - /** Peripheral USART2 base pointer */ - #define USART2_NS ((USART_Type *)USART2_BASE_NS) - /** Peripheral USART3 base address */ - #define USART3_BASE (0x50089000u) - /** Peripheral USART3 base address */ - #define USART3_BASE_NS (0x40089000u) - /** Peripheral USART3 base pointer */ - #define USART3 ((USART_Type *)USART3_BASE) - /** Peripheral USART3 base pointer */ - #define USART3_NS ((USART_Type *)USART3_BASE_NS) - /** Peripheral USART4 base address */ - #define USART4_BASE (0x5008A000u) - /** Peripheral USART4 base address */ - #define USART4_BASE_NS (0x4008A000u) - /** Peripheral USART4 base pointer */ - #define USART4 ((USART_Type *)USART4_BASE) - /** Peripheral USART4 base pointer */ - #define USART4_NS ((USART_Type *)USART4_BASE_NS) - /** Peripheral USART5 base address */ - #define USART5_BASE (0x50096000u) - /** Peripheral USART5 base address */ - #define USART5_BASE_NS (0x40096000u) - /** Peripheral USART5 base pointer */ - #define USART5 ((USART_Type *)USART5_BASE) - /** Peripheral USART5 base pointer */ - #define USART5_NS ((USART_Type *)USART5_BASE_NS) - /** Peripheral USART6 base address */ - #define USART6_BASE (0x50097000u) - /** Peripheral USART6 base address */ - #define USART6_BASE_NS (0x40097000u) - /** Peripheral USART6 base pointer */ - #define USART6 ((USART_Type *)USART6_BASE) - /** Peripheral USART6 base pointer */ - #define USART6_NS ((USART_Type *)USART6_BASE_NS) - /** Peripheral USART7 base address */ - #define USART7_BASE (0x50098000u) - /** Peripheral USART7 base address */ - #define USART7_BASE_NS (0x40098000u) - /** Peripheral USART7 base pointer */ - #define USART7 ((USART_Type *)USART7_BASE) - /** Peripheral USART7 base pointer */ - #define USART7_NS ((USART_Type *)USART7_BASE_NS) - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS_NS { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS_NS { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS } -#else - /** Peripheral USART0 base address */ - #define USART0_BASE (0x40086000u) - /** Peripheral USART0 base pointer */ - #define USART0 ((USART_Type *)USART0_BASE) - /** Peripheral USART1 base address */ - #define USART1_BASE (0x40087000u) - /** Peripheral USART1 base pointer */ - #define USART1 ((USART_Type *)USART1_BASE) - /** Peripheral USART2 base address */ - #define USART2_BASE (0x40088000u) - /** Peripheral USART2 base pointer */ - #define USART2 ((USART_Type *)USART2_BASE) - /** Peripheral USART3 base address */ - #define USART3_BASE (0x40089000u) - /** Peripheral USART3 base pointer */ - #define USART3 ((USART_Type *)USART3_BASE) - /** Peripheral USART4 base address */ - #define USART4_BASE (0x4008A000u) - /** Peripheral USART4 base pointer */ - #define USART4 ((USART_Type *)USART4_BASE) - /** Peripheral USART5 base address */ - #define USART5_BASE (0x40096000u) - /** Peripheral USART5 base pointer */ - #define USART5 ((USART_Type *)USART5_BASE) - /** Peripheral USART6 base address */ - #define USART6_BASE (0x40097000u) - /** Peripheral USART6 base pointer */ - #define USART6 ((USART_Type *)USART6_BASE) - /** Peripheral USART7 base address */ - #define USART7_BASE (0x40098000u) - /** Peripheral USART7 base pointer */ - #define USART7 ((USART_Type *)USART7_BASE) - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } -#endif -/** Interrupt vectors for the USART peripheral type */ -#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group USART_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- UTICK Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer - * @{ - */ - -/** UTICK - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ - __IO uint32_t STAT; /**< Status register., offset: 0x4 */ - __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ - __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ - __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ -} UTICK_Type; - -/* ---------------------------------------------------------------------------- - -- UTICK Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Register_Masks UTICK Register Masks - * @{ - */ - -/*! @name CTRL - Control register. */ -/*! @{ */ - -#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) -#define UTICK_CTRL_DELAYVAL_SHIFT (0U) -/*! DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer - * clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer. - */ -#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) - -#define UTICK_CTRL_REPEAT_MASK (0x80000000U) -#define UTICK_CTRL_REPEAT_SHIFT (31U) -/*! REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. - */ -#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) -/*! @} */ - -/*! @name STAT - Status register. */ -/*! @{ */ - -#define UTICK_STAT_INTR_MASK (0x1U) -#define UTICK_STAT_INTR_SHIFT (0U) -/*! INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any - * value to this register clears this flag. - */ -#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) - -#define UTICK_STAT_ACTIVE_MASK (0x2U) -#define UTICK_STAT_ACTIVE_SHIFT (1U) -/*! ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. - */ -#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) -/*! @} */ - -/*! @name CFG - Capture configuration register. */ -/*! @{ */ - -#define UTICK_CFG_CAPEN0_MASK (0x1U) -#define UTICK_CFG_CAPEN0_SHIFT (0U) -/*! CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled. - */ -#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) - -#define UTICK_CFG_CAPEN1_MASK (0x2U) -#define UTICK_CFG_CAPEN1_SHIFT (1U) -/*! CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled. - */ -#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) - -#define UTICK_CFG_CAPEN2_MASK (0x4U) -#define UTICK_CFG_CAPEN2_SHIFT (2U) -/*! CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled. - */ -#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) - -#define UTICK_CFG_CAPEN3_MASK (0x8U) -#define UTICK_CFG_CAPEN3_SHIFT (3U) -/*! CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled. - */ -#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) - -#define UTICK_CFG_CAPPOL0_MASK (0x100U) -#define UTICK_CFG_CAPPOL0_SHIFT (8U) -/*! CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. - */ -#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) - -#define UTICK_CFG_CAPPOL1_MASK (0x200U) -#define UTICK_CFG_CAPPOL1_SHIFT (9U) -/*! CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. - */ -#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) - -#define UTICK_CFG_CAPPOL2_MASK (0x400U) -#define UTICK_CFG_CAPPOL2_SHIFT (10U) -/*! CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. - */ -#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) - -#define UTICK_CFG_CAPPOL3_MASK (0x800U) -#define UTICK_CFG_CAPPOL3_SHIFT (11U) -/*! CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. - */ -#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) -/*! @} */ - -/*! @name CAPCLR - Capture clear register. */ -/*! @{ */ - -#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) -#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) -/*! CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value. - */ -#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) - -#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) -#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) -/*! CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value. - */ -#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) - -#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) -#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) -/*! CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value. - */ -#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) - -#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) -#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) -/*! CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value. - */ -#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) -/*! @} */ - -/*! @name CAP - Capture register . */ -/*! @{ */ - -#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) -#define UTICK_CAP_CAP_VALUE_SHIFT (0U) -/*! CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower - * than the actual value of the Micro-tick Timer at the moment of the capture event. - */ -#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) - -#define UTICK_CAP_VALID_MASK (0x80000000U) -#define UTICK_CAP_VALID_SHIFT (31U) -/*! VALID - Capture Valid. When 1, a value has been captured based on a transition of the related - * UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. - */ -#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) -/*! @} */ - -/* The count of UTICK_CAP */ -#define UTICK_CAP_COUNT (4U) - - -/*! - * @} - */ /* end of group UTICK_Register_Masks */ - - -/* UTICK - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE (0x5000E000u) - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE_NS (0x4000E000u) - /** Peripheral UTICK0 base pointer */ - #define UTICK0 ((UTICK_Type *)UTICK0_BASE) - /** Peripheral UTICK0 base pointer */ - #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS { UTICK0_BASE } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS { UTICK0 } - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS_NS { UTICK0_NS } -#else - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE (0x4000E000u) - /** Peripheral UTICK0 base pointer */ - #define UTICK0 ((UTICK_Type *)UTICK0_BASE) - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS { UTICK0_BASE } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS { UTICK0 } -#endif -/** Interrupt vectors for the UTICK peripheral type */ -#define UTICK_IRQS { UTICK0_IRQn } - -/*! - * @} - */ /* end of group UTICK_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- WWDT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer - * @{ - */ - -/** WWDT - Register Layout Typedef */ -typedef struct { - __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ - __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ - __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ - __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ - uint8_t RESERVED_0[4]; - __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ - __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ -} WWDT_Type; - -/* ---------------------------------------------------------------------------- - -- WWDT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Register_Masks WWDT Register Masks - * @{ - */ - -/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ -/*! @{ */ - -#define WWDT_MOD_WDEN_MASK (0x1U) -#define WWDT_MOD_WDEN_SHIFT (0U) -/*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the - * watchdog timer will run permanently. - * 0b0..Stop. The watchdog timer is stopped. - * 0b1..Run. The watchdog timer is running. - */ -#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) - -#define WWDT_MOD_WDRESET_MASK (0x2U) -#define WWDT_MOD_WDRESET_SHIFT (1U) -/*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. - * 0b0..Interrupt. A watchdog time-out will not cause a chip reset. - * 0b1..Reset. A watchdog time-out will cause a chip reset. - */ -#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) - -#define WWDT_MOD_WDTOF_MASK (0x4U) -#define WWDT_MOD_WDTOF_SHIFT (2U) -/*! WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by - * events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a - * chip reset if WDRESET = 1. - */ -#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) - -#define WWDT_MOD_WDINT_MASK (0x8U) -#define WWDT_MOD_WDINT_SHIFT (3U) -/*! WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. - * Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the - * WARNINT value is equal to the value of the TV register. This can occur if the value of - * WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. - */ -#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) - -#define WWDT_MOD_WDPROTECT_MASK (0x10U) -#define WWDT_MOD_WDPROTECT_SHIFT (4U) -/*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. - * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time. - * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. - */ -#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) -/*! @} */ - -/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ -/*! @{ */ - -#define WWDT_TC_COUNT_MASK (0xFFFFFFU) -#define WWDT_TC_COUNT_SHIFT (0U) -/*! COUNT - Watchdog time-out value. - */ -#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) -/*! @} */ - -/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ -/*! @{ */ - -#define WWDT_FEED_FEED_MASK (0xFFU) -#define WWDT_FEED_FEED_SHIFT (0U) -/*! FEED - Feed value should be 0xAA followed by 0x55. - */ -#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) -/*! @} */ - -/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ -/*! @{ */ - -#define WWDT_TV_COUNT_MASK (0xFFFFFFU) -#define WWDT_TV_COUNT_SHIFT (0U) -/*! COUNT - Counter timer value. - */ -#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) -/*! @} */ - -/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ -/*! @{ */ - -#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) -#define WWDT_WARNINT_WARNINT_SHIFT (0U) -/*! WARNINT - Watchdog warning interrupt compare value. - */ -#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) -/*! @} */ - -/*! @name WINDOW - Watchdog Window compare value. */ -/*! @{ */ - -#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) -#define WWDT_WINDOW_WINDOW_SHIFT (0U) -/*! WINDOW - Watchdog window value. - */ -#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group WWDT_Register_Masks */ - - -/* WWDT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral WWDT base address */ - #define WWDT_BASE (0x5000C000u) - /** Peripheral WWDT base address */ - #define WWDT_BASE_NS (0x4000C000u) - /** Peripheral WWDT base pointer */ - #define WWDT ((WWDT_Type *)WWDT_BASE) - /** Peripheral WWDT base pointer */ - #define WWDT_NS ((WWDT_Type *)WWDT_BASE_NS) - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS { WWDT_BASE } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS { WWDT } - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS_NS { WWDT_BASE_NS } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS_NS { WWDT_NS } -#else - /** Peripheral WWDT base address */ - #define WWDT_BASE (0x4000C000u) - /** Peripheral WWDT base pointer */ - #define WWDT ((WWDT_Type *)WWDT_BASE) - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS { WWDT_BASE } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS { WWDT } -#endif -/** Interrupt vectors for the WWDT peripheral type */ -#define WWDT_IRQS { WDT_BOD_IRQn } - -/*! - * @} - */ /* end of group WWDT_Peripheral_Access_Layer */ - - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop - #else - #pragma pop - #endif -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -/*! - * @} - */ /* end of group Peripheral_access_layer */ - - -/* ---------------------------------------------------------------------------- - -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - * @{ - */ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang system_header - #endif -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma system_include -#endif - -/** - * @brief Mask and left-shift a bit field value for use in a register bit range. - * @param field Name of the register bit field. - * @param value Value of the bit field. - * @return Masked and shifted value. - */ -#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) -/** - * @brief Mask and right-shift a register value to extract a bit field value. - * @param field Name of the register bit field. - * @param value Value of the register. - * @return Masked and shifted bit field value. - */ -#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) - -/*! - * @} - */ /* end of group Bit_Field_Generic_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SDK Compatibility - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDK_Compatibility_Symbols SDK Compatibility - * @{ - */ - -/** High Speed SPI (Flexcomm 8) interrupt name */ -#define LSPI_HS_IRQn FLEXCOMM8_IRQn - - -/*! - * @} - */ /* end of group SDK_Compatibility_Symbols */ - - -#endif /* _LPC55S06_H_ */ - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/LPC55S06_features.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/LPC55S06_features.h deleted file mode 100644 index dae59489ea4..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/LPC55S06_features.h +++ /dev/null @@ -1,512 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2020-04-09 -** Build: b220303 -** -** Abstract: -** Chip specific module features. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2020-04-09) -** Initial version based on Niobe4mini -** -** ################################################################### -*/ - -#ifndef _LPC55S06_FEATURES_H_ -#define _LPC55S06_FEATURES_H_ - -/* SOC module features */ - -#if defined(CPU_LPC55S06JBD64) - /* @brief LPC_CAN availability on the SoC. */ - #define FSL_FEATURE_SOC_LPC_CAN_COUNT (1) - /* @brief CASPER availability on the SoC. */ - #define FSL_FEATURE_SOC_CASPER_COUNT (1) - /* @brief CRC availability on the SoC. */ - #define FSL_FEATURE_SOC_CRC_COUNT (1) - /* @brief CTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_CTIMER_COUNT (5) - /* @brief CDOG availability on the SoC. */ - #define FSL_FEATURE_SOC_CDOG_COUNT (1) - /* @brief DMA availability on the SoC. */ - #define FSL_FEATURE_SOC_DMA_COUNT (2) - /* @brief FLASH availability on the SoC. */ - #define FSL_FEATURE_SOC_FLASH_COUNT (1) - /* @brief FLEXCOMM availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) - /* @brief GINT availability on the SoC. */ - #define FSL_FEATURE_SOC_GINT_COUNT (2) - /* @brief GPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_GPIO_COUNT (1) - /* @brief SECGPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_SECGPIO_COUNT (1) - /* @brief HASHCRYPT availability on the SoC. */ - #define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) - /* @brief I2C availability on the SoC. */ - #define FSL_FEATURE_SOC_I2C_COUNT (8) - /* @brief I2S availability on the SoC. */ - #define FSL_FEATURE_SOC_I2S_COUNT (8) - /* @brief INPUTMUX availability on the SoC. */ - #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) - /* @brief IOCON availability on the SoC. */ - #define FSL_FEATURE_SOC_IOCON_COUNT (1) - /* @brief LPADC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPADC_COUNT (1) - /* @brief MRT availability on the SoC. */ - #define FSL_FEATURE_SOC_MRT_COUNT (1) - /* @brief OSTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) - /* @brief PINT availability on the SoC. */ - #define FSL_FEATURE_SOC_PINT_COUNT (1) - /* @brief SECPINT availability on the SoC. */ - #define FSL_FEATURE_SOC_SECPINT_COUNT (1) - /* @brief PMC availability on the SoC. */ - #define FSL_FEATURE_SOC_PMC_COUNT (1) - /* @brief PUF availability on the SoC. */ - #define FSL_FEATURE_SOC_PUF_COUNT (1) - /* @brief PUF_SRAM_CTRL availability on the SoC. */ - #define FSL_FEATURE_SOC_PUF_SRAM_CTRL_COUNT (1) - /* @brief LPC_RNG1 availability on the SoC. */ - #define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) - /* @brief RTC availability on the SoC. */ - #define FSL_FEATURE_SOC_RTC_COUNT (1) - /* @brief SCT availability on the SoC. */ - #define FSL_FEATURE_SOC_SCT_COUNT (1) - /* @brief SPI availability on the SoC. */ - #define FSL_FEATURE_SOC_SPI_COUNT (7) - /* @brief SYSCON availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSCON_COUNT (1) - /* @brief SYSCTL1 availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) - /* @brief USART availability on the SoC. */ - #define FSL_FEATURE_SOC_USART_COUNT (8) - /* @brief UTICK availability on the SoC. */ - #define FSL_FEATURE_SOC_UTICK_COUNT (1) - /* @brief WWDT availability on the SoC. */ - #define FSL_FEATURE_SOC_WWDT_COUNT (1) -#elif defined(CPU_LPC55S06JHI48) - /* @brief LPC_CAN availability on the SoC. */ - #define FSL_FEATURE_SOC_LPC_CAN_COUNT (1) - /* @brief CASPER availability on the SoC. */ - #define FSL_FEATURE_SOC_CASPER_COUNT (1) - /* @brief CRC availability on the SoC. */ - #define FSL_FEATURE_SOC_CRC_COUNT (1) - /* @brief CTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_CTIMER_COUNT (5) - /* @brief CDOG availability on the SoC. */ - #define FSL_FEATURE_SOC_CDOG_COUNT (1) - /* @brief DMA availability on the SoC. */ - #define FSL_FEATURE_SOC_DMA_COUNT (2) - /* @brief FLASH availability on the SoC. */ - #define FSL_FEATURE_SOC_FLASH_COUNT (1) - /* @brief FLEXCOMM availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (8) - /* @brief GINT availability on the SoC. */ - #define FSL_FEATURE_SOC_GINT_COUNT (2) - /* @brief GPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_GPIO_COUNT (1) - /* @brief SECGPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_SECGPIO_COUNT (1) - /* @brief HASHCRYPT availability on the SoC. */ - #define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) - /* @brief I2C availability on the SoC. */ - #define FSL_FEATURE_SOC_I2C_COUNT (7) - /* @brief I2S availability on the SoC. */ - #define FSL_FEATURE_SOC_I2S_COUNT (4) - /* @brief INPUTMUX availability on the SoC. */ - #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) - /* @brief IOCON availability on the SoC. */ - #define FSL_FEATURE_SOC_IOCON_COUNT (1) - /* @brief LPADC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPADC_COUNT (1) - /* @brief MRT availability on the SoC. */ - #define FSL_FEATURE_SOC_MRT_COUNT (1) - /* @brief OSTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) - /* @brief PINT availability on the SoC. */ - #define FSL_FEATURE_SOC_PINT_COUNT (1) - /* @brief SECPINT availability on the SoC. */ - #define FSL_FEATURE_SOC_SECPINT_COUNT (1) - /* @brief PMC availability on the SoC. */ - #define FSL_FEATURE_SOC_PMC_COUNT (1) - /* @brief PUF availability on the SoC. */ - #define FSL_FEATURE_SOC_PUF_COUNT (1) - /* @brief PUF_SRAM_CTRL availability on the SoC. */ - #define FSL_FEATURE_SOC_PUF_SRAM_CTRL_COUNT (1) - /* @brief LPC_RNG1 availability on the SoC. */ - #define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) - /* @brief RTC availability on the SoC. */ - #define FSL_FEATURE_SOC_RTC_COUNT (1) - /* @brief SCT availability on the SoC. */ - #define FSL_FEATURE_SOC_SCT_COUNT (1) - /* @brief SPI availability on the SoC. */ - #define FSL_FEATURE_SOC_SPI_COUNT (4) - /* @brief SYSCON availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSCON_COUNT (1) - /* @brief SYSCTL1 availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) - /* @brief USART availability on the SoC. */ - #define FSL_FEATURE_SOC_USART_COUNT (7) - /* @brief UTICK availability on the SoC. */ - #define FSL_FEATURE_SOC_UTICK_COUNT (1) - /* @brief WWDT availability on the SoC. */ - #define FSL_FEATURE_SOC_WWDT_COUNT (1) -#endif - -/* LPADC module features */ - -/* @brief FIFO availability on the SoC. */ -#define FSL_FEATURE_LPADC_FIFO_COUNT (2) -/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) -/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) -/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) -/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) -/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) -/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) -/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) -/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) -/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) -/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) -/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) -/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) -/* @brief Has calibration (bitfield CFG[CALOFS]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) -/* @brief Has offset trim (register OFSTRIM). */ -#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) -/* @brief Has Trigger status register. */ -#define FSL_FEATURE_LPADC_HAS_TSTAT (1) -/* @brief Has power select (bitfield CFG[PWRSEL]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) -/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) -/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) -/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) -/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) -/* @brief Conversion averaged bitfiled width. */ -#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) -/* @brief Has internal temperature sensor. */ -#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) -/* @brief Temperature sensor parameter A (slope). */ -#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (799.0f) -/* @brief Temperature sensor parameter B (offset). */ -#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (280.0f) -/* @brief Temperature sensor parameter Alpha. */ -#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (8.5f) -/* @brief Temperature sensor need calibration. */ -#define FSL_FEATURE_LPADC_TEMP_NEED_CALIBRATION (1) -/* @brief the address of temperature sensor parameter A (slope) in Flash. */ -#define FSL_FEATURE_FLASH_NMPA_TEMP_SLOPE_ADDRS (0x3FD28U) -/* @brief the address of temperature sensor parameter B (offset) in Flash. */ -#define FSL_FEATURE_FLASH_NMPA_TEMP_OFFSET_ADDRS (0x3FD2CU) -/* @brief the buffer size of temperature sensor. */ -#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) - -/* ANALOGCTRL module features */ - -/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ -#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) -/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ -#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (1) -/* @brief Has auxiliary bias(register AUX_BIAS). */ -#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1) - -/* CAN module features */ - -/* @brief Support CANFD or not */ -#define FSL_FEATURE_CAN_SUPPORT_CANFD (1) - -/* CASPER module features */ - -/* @brief Base address of the CASPER dedicated RAM */ -#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) -/* @brief HW interleaving of the CASPER dedicated RAM */ -#define FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE (1) - -/* CTIMER module features */ - -/* @brief CTIMER has no capture channel. */ -#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) -/* @brief CTIMER has no capture 2 interrupt. */ -#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) -/* @brief CTIMER capture 3 interrupt. */ -#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) -/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ -#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) -/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ -#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) - -/* DMA module features */ - -/* @brief Number of channels */ -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23) -/* @brief Align size of DMA descriptor */ -#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) -/* @brief DMA head link descriptor table align size */ -#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) - -/* FLEXCOMM module features */ - -#if defined(CPU_LPC55S06JBD64) - /* @brief FLEXCOMM0 USART INDEX 0 */ - #define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) - /* @brief FLEXCOMM0 SPI INDEX 0 */ - #define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) - /* @brief FLEXCOMM0 I2C INDEX 0 */ - #define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) - /* @brief FLEXCOMM0 I2S INDEX 0 */ - #define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) - /* @brief FLEXCOMM1 USART INDEX 1 */ - #define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) - /* @brief FLEXCOMM1 SPI INDEX 1 */ - #define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) - /* @brief FLEXCOMM1 I2C INDEX 1 */ - #define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) - /* @brief FLEXCOMM1 I2S INDEX 1 */ - #define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) - /* @brief FLEXCOMM2 USART INDEX 2 */ - #define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) - /* @brief FLEXCOMM2 I2C INDEX 2 */ - #define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) - /* @brief FLEXCOMM2 I2S INDEX 2 */ - #define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) - /* @brief FLEXCOMM3 USART INDEX 3 */ - #define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) - /* @brief FLEXCOMM3 SPI INDEX 3 */ - #define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) - /* @brief FLEXCOMM3 I2C INDEX 3 */ - #define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) - /* @brief FLEXCOMM3 I2S INDEX 3 */ - #define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) - /* @brief FLEXCOMM4 USART INDEX 4 */ - #define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) - /* @brief FLEXCOMM4 SPI INDEX 4 */ - #define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) - /* @brief FLEXCOMM4 I2C INDEX 4 */ - #define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) - /* @brief FLEXCOMM4 I2S INDEX 4 */ - #define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) - /* @brief FLEXCOMM5 USART INDEX 5 */ - #define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) - /* @brief FLEXCOMM5 I2C INDEX 5 */ - #define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) - /* @brief FLEXCOMM5 I2S INDEX 5 */ - #define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) - /* @brief FLEXCOMM6 USART INDEX 6 */ - #define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) - /* @brief FLEXCOMM6 SPI INDEX 6 */ - #define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) - /* @brief FLEXCOMM6 I2C INDEX 6 */ - #define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) - /* @brief FLEXCOMM6 I2S INDEX 6 */ - #define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) - /* @brief FLEXCOMM7 USART INDEX 7 */ - #define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) - /* @brief FLEXCOMM7 SPI INDEX 7 */ - #define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) - /* @brief FLEXCOMM7 I2C INDEX 7 */ - #define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) - /* @brief FLEXCOMM7 I2S INDEX 7 */ - #define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) - /* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ - #define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) - /* @brief I2S has DMIC interconnection */ - #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) - /* @brief I2S support dual channel transfer */ - #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn(x) \ - (((x) == FLEXCOMM0) ? (0) : \ - (((x) == FLEXCOMM1) ? (0) : \ - (((x) == FLEXCOMM2) ? (0) : \ - (((x) == FLEXCOMM3) ? (0) : \ - (((x) == FLEXCOMM4) ? (0) : \ - (((x) == FLEXCOMM5) ? (0) : \ - (((x) == FLEXCOMM6) ? (1) : \ - (((x) == FLEXCOMM7) ? (1) : \ - (((x) == FLEXCOMM8) ? (0) : (-1)))))))))) -#elif defined(CPU_LPC55S06JHI48) - /* @brief FLEXCOMM0 USART INDEX 0 */ - #define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) - /* @brief FLEXCOMM0 SPI INDEX 0 */ - #define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) - /* @brief FLEXCOMM0 I2C INDEX 0 */ - #define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) - /* @brief FLEXCOMM0 I2S INDEX 0 */ - #define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) - /* @brief FLEXCOMM1 USART INDEX 1 */ - #define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) - /* @brief FLEXCOMM1 I2C INDEX 1 */ - #define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) - /* @brief FLEXCOMM2 USART INDEX 2 */ - #define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) - /* @brief FLEXCOMM2 I2C INDEX 2 */ - #define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) - /* @brief FLEXCOMM3 USART INDEX 3 */ - #define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) - /* @brief FLEXCOMM3 SPI INDEX 3 */ - #define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) - /* @brief FLEXCOMM3 I2C INDEX 3 */ - #define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) - /* @brief FLEXCOMM3 I2S INDEX 3 */ - #define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) - /* @brief FLEXCOMM4 USART INDEX 4 */ - #define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) - /* @brief FLEXCOMM4 I2C INDEX 4 */ - #define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) - /* @brief FLEXCOMM4 I2S INDEX 4 */ - #define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) - /* @brief FLEXCOMM5 USART INDEX 5 */ - #define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) - /* @brief FLEXCOMM5 I2C INDEX 5 */ - #define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) - /* @brief FLEXCOMM6 USART INDEX 6 */ - #define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) - /* @brief FLEXCOMM6 SPI INDEX 6 */ - #define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) - /* @brief FLEXCOMM6 I2C INDEX 6 */ - #define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) - /* @brief FLEXCOMM6 I2S INDEX 6 */ - #define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) - /* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ - #define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) - /* @brief I2S has DMIC interconnection */ - #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) - /* @brief I2S support dual channel transfer */ - #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn(x) \ - (((x) == FLEXCOMM0) ? (0) : \ - (((x) == FLEXCOMM1) ? (0) : \ - (((x) == FLEXCOMM2) ? (0) : \ - (((x) == FLEXCOMM3) ? (0) : \ - (((x) == FLEXCOMM4) ? (0) : \ - (((x) == FLEXCOMM5) ? (0) : \ - (((x) == FLEXCOMM6) ? (1) : \ - (((x) == FLEXCOMM8) ? (0) : (-1))))))))) -#endif /* defined(CPU_LPC55S06JBD64) */ - -/* HASHCRYPT module features */ - -/* @brief the address of alias offset */ -#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000) -/* @brief hashcrypt has reload feature */ -#define FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE (1) - -/* I2S module features */ - -/* @brief I2S6 and I2S7 support dual channel transfer. */ -#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) -/* @brief I2S has DMIC interconnection */ -#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) - -/* IOCON module features */ - -/* @brief Func bit field width */ -#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) - -/* MRT module features */ - -/* @brief number of channels. */ -#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) - -/* PINT module features */ - -/* @brief Number of connected outputs */ -#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) - -/* PLU module features */ - -/* @brief Has WAKEINT_CTRL register. */ -#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) - -/* PMC module features */ - -/* @brief UTICK does not support PD configure. */ -#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) -/* @brief WDT OSC does not support PD configure. */ -#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) - -/* POWERLIB module features */ - -/* @brief Powerlib API is different with other LPC series devices. */ -#define FSL_FEATURE_POWERLIB_EXTEND (1) - -/* PUF module features */ - -/* @brief Number of PUF key slots available on device. */ -#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4) -/* @brief the shift status value */ -#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) -/* @brief PUF has dedicated SRAM control */ -#define FSL_FEATURE_PUF_HAS_SRAM_CTRL (1) - -/* RTC module features */ - -/* No feature definitions */ - -/* SCT module features */ - -/* @brief Number of events */ -#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) -/* @brief Number of states */ -#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) -/* @brief Number of match capture */ -#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) -/* @brief Number of outputs */ -#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) - -/* SECPINT module features */ - -/* @brief Number of connected outputs */ -#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) - -/* SYSCON module features */ - -/* @brief Flash page size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) -/* @brief Flash sector size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) -/* @brief Flash size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (251904) -/* @brief Has Power Down mode */ -#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) -/* @brief CCM_ANALOG availability on the SoC. */ -#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) -/* @brief Starter register discontinuous. */ -#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) - -/* SYSCTL1 module features */ - -/* @brief SYSCTRL has Code Gray feature. */ -#define FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY (1) - -/* WWDT module features */ - -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) -/* @brief WWDT does not support oscillator lock. */ -#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) - -#endif /* _LPC55S06_FEATURES_H_ */ - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/arm/LPC550XX_256.FLM b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/arm/LPC550XX_256.FLM deleted file mode 100644 index 506abbff0d4..00000000000 Binary files a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/arm/LPC550XX_256.FLM and /dev/null differ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/arm/LPC550XX_S_256.FLM b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/arm/LPC550XX_S_256.FLM deleted file mode 100644 index 84d12337c80..00000000000 Binary files a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/arm/LPC550XX_S_256.FLM and /dev/null differ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/arm/LPC55S06_flash.scf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/arm/LPC55S06_flash.scf deleted file mode 100644 index 46655c0dde5..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/arm/LPC55S06_flash.scf +++ /dev/null @@ -1,77 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c -/* -** ################################################################### -** Processors: LPC55S06JBD64 -** LPC55S06JHI48 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55S0x/LPC550x User manual Rev.0.3 14 August 2020 -** Version: rev. 1.0, 2020-04-09 -** Build: b220622 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#define m_interrupts_start 0x00000000 -#define m_interrupts_size 0x00000200 - -#define m_text_start 0x00000200 -#define m_text_size 0x0003CE00 - -#define m_data_start 0x20000000 -#define m_data_size 0x00010000 - -#define m_sramx_start 0x04000000 -#define m_sramx_size 0x00004000 - -#define m_sram3_start 0x20010000 -#define m_sram3_size 0x00004000 - -LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region - - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/arm/LPC55S06_ram.scf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/arm/LPC55S06_ram.scf deleted file mode 100644 index 3b9f4f116c2..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/arm/LPC55S06_ram.scf +++ /dev/null @@ -1,74 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c -/* -** ################################################################### -** Processors: LPC55S06JBD64 -** LPC55S06JHI48 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55S0x/LPC550x User manual Rev.0.3 14 August 2020 -** Version: rev. 1.0, 2020-04-09 -** Build: b220622 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#define m_interrupts_start 0x20000000 -#define m_interrupts_size 0x00000200 - -#define m_text_start 0x20000200 -#define m_text_size 0x0000FE00 - -#define m_data_start 0x04000000 -#define m_data_size 0x00004000 - -#define m_sram3_start 0x20010000 -#define m_sram3_size 0x00004000 - -LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region - - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/arm/LPC55S0xx.dbgconf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/arm/LPC55S0xx.dbgconf deleted file mode 100644 index 1cc3a2af84a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/arm/LPC55S0xx.dbgconf +++ /dev/null @@ -1,18 +0,0 @@ -// <<< Use Configuration Wizard in Context Menu >>> - -// SWO pin -// The SWO (Serial Wire Output) pin optionally provides data from the ITM -// for an external debug tool to evaluate. -// <0=> PIO0_10 -// <1=> PIO0_8 -SWO_Pin = 0; -// - -// Debug Configuration -// StopAfterBootloader Stop after Bootloader -// -Dbg_CR = 0x00000001; -// - - -// <<< end of configuration section >>> \ No newline at end of file diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/arm/startup_LPC55S06.S b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/arm/startup_LPC55S06.S deleted file mode 100644 index 1f63f2d1ee0..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/arm/startup_LPC55S06.S +++ /dev/null @@ -1,812 +0,0 @@ -/* --------------------------------------------------------------------------------------- - * @file: startup_LPC55S06.s - * @purpose: CMSIS Cortex-M33 Core Device Startup File for the LPC55S06 - * @version: 1.0 - * @date: 2020-4-9 - * ---------------------------------------------------------------------------------------*/ -/* - * Copyright 1997-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - - .syntax unified - .arch armv8-m.main - .eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */ - - .section .isr_vector, "a" - .align 2 - .globl __Vectors - -__Vectors: - .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long MemManage_Handler /* MPU Fault Handler*/ - .long BusFault_Handler /* Bus Fault Handler*/ - .long UsageFault_Handler /* Usage Fault Handler*/ - .long SecureFault_Handler /* Secure Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long DebugMon_Handler /* Debug Monitor Handler*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts*/ - .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ - .long DMA0_IRQHandler /* DMA0 controller */ - .long GINT0_IRQHandler /* GPIO group 0 */ - .long GINT1_IRQHandler /* GPIO group 1 */ - .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - .long UTICK0_IRQHandler /* Micro-tick Timer */ - .long MRT0_IRQHandler /* Multi-rate timer */ - .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ - .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ - .long SCT0_IRQHandler /* SCTimer/PWM */ - .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ - .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long ADC0_IRQHandler /* ADC0 */ - .long Reserved39_IRQHandler /* Reserved interrupt */ - .long ACMP_IRQHandler /* ACMP interrupts */ - .long Reserved41_IRQHandler /* Reserved interrupt */ - .long Reserved42_IRQHandler /* Reserved interrupt */ - .long Reserved43_IRQHandler /* Reserved interrupt */ - .long Reserved44_IRQHandler /* Reserved interrupt */ - .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ - .long Reserved46_IRQHandler /* Reserved interrupt */ - .long Reserved47_IRQHandler /* Reserved interrupt */ - .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ - .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ - .long OS_EVENT_IRQHandler /* OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ - .long Reserved55_IRQHandler /* Reserved interrupt */ - .long Reserved56_IRQHandler /* Reserved interrupt */ - .long Reserved57_IRQHandler /* Reserved interrupt */ - .long Reserved58_IRQHandler /* Reserved interrupt */ - .long CAN0_IRQ0_IRQHandler /* CAN0 interrupt0 */ - .long CAN0_IRQ1_IRQHandler /* CAN0 interrupt1 */ - .long Reserved61_IRQHandler /* Reserved interrupt */ - .long Reserved62_IRQHandler /* Reserved interrupt */ - .long Reserved63_IRQHandler /* Reserved interrupt */ - .long Reserved64_IRQHandler /* Reserved interrupt */ - .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ - .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ - .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ - .long PLU_IRQHandler /* PLU interrupt */ - .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ - .long HASHCRYPT_IRQHandler /* SHA interrupt */ - .long CASER_IRQHandler /* CASPER interrupt */ - .long PUF_IRQHandler /* PUF interrupt */ - .long Reserved73_IRQHandler /* Reserved interrupt */ - .long DMA1_IRQHandler /* DMA1 interrupt */ - .long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ - .long CDOG_IRQHandler /* CDOG interrupt */ - .size __Vectors, . - __Vectors - - .text - .thumb - -/* Reset Handler */ - .thumb_func - .align 2 - .weak Reset_Handler - .type Reset_Handler, %function - -Reset_Handler: - cpsid i /* Mask interrupts */ - .equ VTOR, 0xE000ED08 - ldr r0, =VTOR - ldr r1, =__Vectors - str r1, [r0] - ldr r2, [r1] - msr msp, r2 - ldr R0, =Image$$ARM_LIB_STACK$$ZI$$Base - msr msplim, R0 - ldr r0,=SystemInit - blx r0 - cpsie i /* Unmask interrupts */ - ldr r0,=__main - bx r0 - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - .align 1 - .thumb_func - .weak WDT_BOD_IRQHandler - .type WDT_BOD_IRQHandler, %function -WDT_BOD_IRQHandler: - ldr r0,=WDT_BOD_DriverIRQHandler - bx r0 - .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler - - .align 1 - .thumb_func - .weak DMA0_IRQHandler - .type DMA0_IRQHandler, %function -DMA0_IRQHandler: - ldr r0,=DMA0_DriverIRQHandler - bx r0 - .size DMA0_IRQHandler, . - DMA0_IRQHandler - - .align 1 - .thumb_func - .weak GINT0_IRQHandler - .type GINT0_IRQHandler, %function -GINT0_IRQHandler: - ldr r0,=GINT0_DriverIRQHandler - bx r0 - .size GINT0_IRQHandler, . - GINT0_IRQHandler - - .align 1 - .thumb_func - .weak GINT1_IRQHandler - .type GINT1_IRQHandler, %function -GINT1_IRQHandler: - ldr r0,=GINT1_DriverIRQHandler - bx r0 - .size GINT1_IRQHandler, . - GINT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT0_IRQHandler - .type PIN_INT0_IRQHandler, %function -PIN_INT0_IRQHandler: - ldr r0,=PIN_INT0_DriverIRQHandler - bx r0 - .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT1_IRQHandler - .type PIN_INT1_IRQHandler, %function -PIN_INT1_IRQHandler: - ldr r0,=PIN_INT1_DriverIRQHandler - bx r0 - .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT2_IRQHandler - .type PIN_INT2_IRQHandler, %function -PIN_INT2_IRQHandler: - ldr r0,=PIN_INT2_DriverIRQHandler - bx r0 - .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT3_IRQHandler - .type PIN_INT3_IRQHandler, %function -PIN_INT3_IRQHandler: - ldr r0,=PIN_INT3_DriverIRQHandler - bx r0 - .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler - - .align 1 - .thumb_func - .weak UTICK0_IRQHandler - .type UTICK0_IRQHandler, %function -UTICK0_IRQHandler: - ldr r0,=UTICK0_DriverIRQHandler - bx r0 - .size UTICK0_IRQHandler, . - UTICK0_IRQHandler - - .align 1 - .thumb_func - .weak MRT0_IRQHandler - .type MRT0_IRQHandler, %function -MRT0_IRQHandler: - ldr r0,=MRT0_DriverIRQHandler - bx r0 - .size MRT0_IRQHandler, . - MRT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER0_IRQHandler - .type CTIMER0_IRQHandler, %function -CTIMER0_IRQHandler: - ldr r0,=CTIMER0_DriverIRQHandler - bx r0 - .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER1_IRQHandler - .type CTIMER1_IRQHandler, %function -CTIMER1_IRQHandler: - ldr r0,=CTIMER1_DriverIRQHandler - bx r0 - .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler - - .align 1 - .thumb_func - .weak SCT0_IRQHandler - .type SCT0_IRQHandler, %function -SCT0_IRQHandler: - ldr r0,=SCT0_DriverIRQHandler - bx r0 - .size SCT0_IRQHandler, . - SCT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER3_IRQHandler - .type CTIMER3_IRQHandler, %function -CTIMER3_IRQHandler: - ldr r0,=CTIMER3_DriverIRQHandler - bx r0 - .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM0_IRQHandler - .type FLEXCOMM0_IRQHandler, %function -FLEXCOMM0_IRQHandler: - ldr r0,=FLEXCOMM0_DriverIRQHandler - bx r0 - .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM1_IRQHandler - .type FLEXCOMM1_IRQHandler, %function -FLEXCOMM1_IRQHandler: - ldr r0,=FLEXCOMM1_DriverIRQHandler - bx r0 - .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM2_IRQHandler - .type FLEXCOMM2_IRQHandler, %function -FLEXCOMM2_IRQHandler: - ldr r0,=FLEXCOMM2_DriverIRQHandler - bx r0 - .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM3_IRQHandler - .type FLEXCOMM3_IRQHandler, %function -FLEXCOMM3_IRQHandler: - ldr r0,=FLEXCOMM3_DriverIRQHandler - bx r0 - .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM4_IRQHandler - .type FLEXCOMM4_IRQHandler, %function -FLEXCOMM4_IRQHandler: - ldr r0,=FLEXCOMM4_DriverIRQHandler - bx r0 - .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM5_IRQHandler - .type FLEXCOMM5_IRQHandler, %function -FLEXCOMM5_IRQHandler: - ldr r0,=FLEXCOMM5_DriverIRQHandler - bx r0 - .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM6_IRQHandler - .type FLEXCOMM6_IRQHandler, %function -FLEXCOMM6_IRQHandler: - ldr r0,=FLEXCOMM6_DriverIRQHandler - bx r0 - .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM7_IRQHandler - .type FLEXCOMM7_IRQHandler, %function -FLEXCOMM7_IRQHandler: - ldr r0,=FLEXCOMM7_DriverIRQHandler - bx r0 - .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_IRQHandler - .type ADC0_IRQHandler, %function -ADC0_IRQHandler: - ldr r0,=ADC0_DriverIRQHandler - bx r0 - .size ADC0_IRQHandler, . - ADC0_IRQHandler - - .align 1 - .thumb_func - .weak Reserved39_IRQHandler - .type Reserved39_IRQHandler, %function -Reserved39_IRQHandler: - ldr r0,=Reserved39_DriverIRQHandler - bx r0 - .size Reserved39_IRQHandler, . - Reserved39_IRQHandler - - .align 1 - .thumb_func - .weak ACMP_IRQHandler - .type ACMP_IRQHandler, %function -ACMP_IRQHandler: - ldr r0,=ACMP_DriverIRQHandler - bx r0 - .size ACMP_IRQHandler, . - ACMP_IRQHandler - - .align 1 - .thumb_func - .weak Reserved41_IRQHandler - .type Reserved41_IRQHandler, %function -Reserved41_IRQHandler: - ldr r0,=Reserved41_DriverIRQHandler - bx r0 - .size Reserved41_IRQHandler, . - Reserved41_IRQHandler - - .align 1 - .thumb_func - .weak Reserved42_IRQHandler - .type Reserved42_IRQHandler, %function -Reserved42_IRQHandler: - ldr r0,=Reserved42_DriverIRQHandler - bx r0 - .size Reserved42_IRQHandler, . - Reserved42_IRQHandler - - .align 1 - .thumb_func - .weak Reserved43_IRQHandler - .type Reserved43_IRQHandler, %function -Reserved43_IRQHandler: - ldr r0,=Reserved43_DriverIRQHandler - bx r0 - .size Reserved43_IRQHandler, . - Reserved43_IRQHandler - - .align 1 - .thumb_func - .weak Reserved44_IRQHandler - .type Reserved44_IRQHandler, %function -Reserved44_IRQHandler: - ldr r0,=Reserved44_DriverIRQHandler - bx r0 - .size Reserved44_IRQHandler, . - Reserved44_IRQHandler - - .align 1 - .thumb_func - .weak RTC_IRQHandler - .type RTC_IRQHandler, %function -RTC_IRQHandler: - ldr r0,=RTC_DriverIRQHandler - bx r0 - .size RTC_IRQHandler, . - RTC_IRQHandler - - .align 1 - .thumb_func - .weak Reserved46_IRQHandler - .type Reserved46_IRQHandler, %function -Reserved46_IRQHandler: - ldr r0,=Reserved46_DriverIRQHandler - bx r0 - .size Reserved46_IRQHandler, . - Reserved46_IRQHandler - - .align 1 - .thumb_func - .weak Reserved47_IRQHandler - .type Reserved47_IRQHandler, %function -Reserved47_IRQHandler: - ldr r0,=Reserved47_DriverIRQHandler - bx r0 - .size Reserved47_IRQHandler, . - Reserved47_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT4_IRQHandler - .type PIN_INT4_IRQHandler, %function -PIN_INT4_IRQHandler: - ldr r0,=PIN_INT4_DriverIRQHandler - bx r0 - .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT5_IRQHandler - .type PIN_INT5_IRQHandler, %function -PIN_INT5_IRQHandler: - ldr r0,=PIN_INT5_DriverIRQHandler - bx r0 - .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT6_IRQHandler - .type PIN_INT6_IRQHandler, %function -PIN_INT6_IRQHandler: - ldr r0,=PIN_INT6_DriverIRQHandler - bx r0 - .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT7_IRQHandler - .type PIN_INT7_IRQHandler, %function -PIN_INT7_IRQHandler: - ldr r0,=PIN_INT7_DriverIRQHandler - bx r0 - .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER2_IRQHandler - .type CTIMER2_IRQHandler, %function -CTIMER2_IRQHandler: - ldr r0,=CTIMER2_DriverIRQHandler - bx r0 - .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER4_IRQHandler - .type CTIMER4_IRQHandler, %function -CTIMER4_IRQHandler: - ldr r0,=CTIMER4_DriverIRQHandler - bx r0 - .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler - - .align 1 - .thumb_func - .weak OS_EVENT_IRQHandler - .type OS_EVENT_IRQHandler, %function -OS_EVENT_IRQHandler: - ldr r0,=OS_EVENT_DriverIRQHandler - bx r0 - .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler - - .align 1 - .thumb_func - .weak Reserved55_IRQHandler - .type Reserved55_IRQHandler, %function -Reserved55_IRQHandler: - ldr r0,=Reserved55_DriverIRQHandler - bx r0 - .size Reserved55_IRQHandler, . - Reserved55_IRQHandler - - .align 1 - .thumb_func - .weak Reserved56_IRQHandler - .type Reserved56_IRQHandler, %function -Reserved56_IRQHandler: - ldr r0,=Reserved56_DriverIRQHandler - bx r0 - .size Reserved56_IRQHandler, . - Reserved56_IRQHandler - - .align 1 - .thumb_func - .weak Reserved57_IRQHandler - .type Reserved57_IRQHandler, %function -Reserved57_IRQHandler: - ldr r0,=Reserved57_DriverIRQHandler - bx r0 - .size Reserved57_IRQHandler, . - Reserved57_IRQHandler - - .align 1 - .thumb_func - .weak Reserved58_IRQHandler - .type Reserved58_IRQHandler, %function -Reserved58_IRQHandler: - ldr r0,=Reserved58_DriverIRQHandler - bx r0 - .size Reserved58_IRQHandler, . - Reserved58_IRQHandler - - .align 1 - .thumb_func - .weak CAN0_IRQ0_IRQHandler - .type CAN0_IRQ0_IRQHandler, %function -CAN0_IRQ0_IRQHandler: - ldr r0,=CAN0_IRQ0_DriverIRQHandler - bx r0 - .size CAN0_IRQ0_IRQHandler, . - CAN0_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak CAN0_IRQ1_IRQHandler - .type CAN0_IRQ1_IRQHandler, %function -CAN0_IRQ1_IRQHandler: - ldr r0,=CAN0_IRQ1_DriverIRQHandler - bx r0 - .size CAN0_IRQ1_IRQHandler, . - CAN0_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak Reserved61_IRQHandler - .type Reserved61_IRQHandler, %function -Reserved61_IRQHandler: - ldr r0,=Reserved61_DriverIRQHandler - bx r0 - .size Reserved61_IRQHandler, . - Reserved61_IRQHandler - - .align 1 - .thumb_func - .weak Reserved62_IRQHandler - .type Reserved62_IRQHandler, %function -Reserved62_IRQHandler: - ldr r0,=Reserved62_DriverIRQHandler - bx r0 - .size Reserved62_IRQHandler, . - Reserved62_IRQHandler - - .align 1 - .thumb_func - .weak Reserved63_IRQHandler - .type Reserved63_IRQHandler, %function -Reserved63_IRQHandler: - ldr r0,=Reserved63_DriverIRQHandler - bx r0 - .size Reserved63_IRQHandler, . - Reserved63_IRQHandler - - .align 1 - .thumb_func - .weak Reserved64_IRQHandler - .type Reserved64_IRQHandler, %function -Reserved64_IRQHandler: - ldr r0,=Reserved64_DriverIRQHandler - bx r0 - .size Reserved64_IRQHandler, . - Reserved64_IRQHandler - - .align 1 - .thumb_func - .weak SEC_HYPERVISOR_CALL_IRQHandler - .type SEC_HYPERVISOR_CALL_IRQHandler, %function -SEC_HYPERVISOR_CALL_IRQHandler: - ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler - bx r0 - .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ0_IRQHandler - .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function -SEC_GPIO_INT0_IRQ0_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ1_IRQHandler - .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function -SEC_GPIO_INT0_IRQ1_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak PLU_IRQHandler - .type PLU_IRQHandler, %function -PLU_IRQHandler: - ldr r0,=PLU_DriverIRQHandler - bx r0 - .size PLU_IRQHandler, . - PLU_IRQHandler - - .align 1 - .thumb_func - .weak SEC_VIO_IRQHandler - .type SEC_VIO_IRQHandler, %function -SEC_VIO_IRQHandler: - ldr r0,=SEC_VIO_DriverIRQHandler - bx r0 - .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler - - .align 1 - .thumb_func - .weak HASHCRYPT_IRQHandler - .type HASHCRYPT_IRQHandler, %function -HASHCRYPT_IRQHandler: - ldr r0,=HASHCRYPT_DriverIRQHandler - bx r0 - .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler - - .align 1 - .thumb_func - .weak CASER_IRQHandler - .type CASER_IRQHandler, %function -CASER_IRQHandler: - ldr r0,=CASER_DriverIRQHandler - bx r0 - .size CASER_IRQHandler, . - CASER_IRQHandler - - .align 1 - .thumb_func - .weak PUF_IRQHandler - .type PUF_IRQHandler, %function -PUF_IRQHandler: - ldr r0,=PUF_DriverIRQHandler - bx r0 - .size PUF_IRQHandler, . - PUF_IRQHandler - - .align 1 - .thumb_func - .weak Reserved73_IRQHandler - .type Reserved73_IRQHandler, %function -Reserved73_IRQHandler: - ldr r0,=Reserved73_DriverIRQHandler - bx r0 - .size Reserved73_IRQHandler, . - Reserved73_IRQHandler - - .align 1 - .thumb_func - .weak DMA1_IRQHandler - .type DMA1_IRQHandler, %function -DMA1_IRQHandler: - ldr r0,=DMA1_DriverIRQHandler - bx r0 - .size DMA1_IRQHandler, . - DMA1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM8_IRQHandler - .type FLEXCOMM8_IRQHandler, %function -FLEXCOMM8_IRQHandler: - ldr r0,=FLEXCOMM8_DriverIRQHandler - bx r0 - .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler - - .align 1 - .thumb_func - .weak CDOG_IRQHandler - .type CDOG_IRQHandler, %function -CDOG_IRQHandler: - ldr r0,=CDOG_DriverIRQHandler - bx r0 - .size CDOG_IRQHandler, . - CDOG_IRQHandler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm -/* Exception Handlers */ - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SecureFault_Handler - def_irq_handler DebugMon_Handler - def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ - def_irq_handler DMA0_DriverIRQHandler /* DMA0 controller */ - def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */ - def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */ - def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */ - def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */ - def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */ - def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */ - def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */ - def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */ - def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler ADC0_DriverIRQHandler /* ADC0 */ - def_irq_handler Reserved39_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler ACMP_DriverIRQHandler /* ACMP interrupts */ - def_irq_handler Reserved41_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved42_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved43_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved44_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */ - def_irq_handler Reserved46_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved47_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler PIN_INT4_DriverIRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - def_irq_handler PIN_INT5_DriverIRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - def_irq_handler PIN_INT6_DriverIRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - def_irq_handler PIN_INT7_DriverIRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - def_irq_handler CTIMER2_DriverIRQHandler /* Standard counter/timer CTIMER2 */ - def_irq_handler CTIMER4_DriverIRQHandler /* Standard counter/timer CTIMER4 */ - def_irq_handler OS_EVENT_DriverIRQHandler /* OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ - def_irq_handler Reserved55_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved56_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved57_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved58_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler CAN0_IRQ0_DriverIRQHandler /* CAN0 interrupt0 */ - def_irq_handler CAN0_IRQ1_DriverIRQHandler /* CAN0 interrupt1 */ - def_irq_handler Reserved61_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved62_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved63_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved64_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler /* SEC_HYPERVISOR_CALL interrupt */ - def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ - def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ - def_irq_handler PLU_DriverIRQHandler /* PLU interrupt */ - def_irq_handler SEC_VIO_DriverIRQHandler /* SEC_VIO interrupt */ - def_irq_handler HASHCRYPT_DriverIRQHandler /* SHA interrupt */ - def_irq_handler CASER_DriverIRQHandler /* CASPER interrupt */ - def_irq_handler PUF_DriverIRQHandler /* PUF interrupt */ - def_irq_handler Reserved73_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler DMA1_DriverIRQHandler /* DMA1 interrupt */ - def_irq_handler FLEXCOMM8_DriverIRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ - def_irq_handler CDOG_DriverIRQHandler /* CDOG interrupt */ - - .end diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_anactrl.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_anactrl.c deleted file mode 100644 index 68175b880a3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_anactrl.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright 2018-2021, NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_anactrl.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.anactrl" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for ANACTRL module. - * - * @param base ANACTRL peripheral base address - */ -static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to ANACTRL bases for each instance. */ -static ANACTRL_Type *const s_anactrlBases[] = ANACTRL_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to ANACTRL clocks for each instance. */ -static const clock_ip_name_t s_anactrlClocks[] = ANALOGCTRL_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! - * brief Get the ANACTRL instance from peripheral base address. - * - * param base ANACTRL peripheral base address. - * return ANACTRL instance. - */ -static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_anactrlBases); instance++) - { - if (s_anactrlBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_anactrlBases)); - - return instance; -} - -/*! - * brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function. - * - * param base ANACTRL peripheral base address. - */ -void ANACTRL_Init(ANACTRL_Type *base) -{ - assert(NULL != base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock for ANACTRL instance. */ - CLOCK_EnableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function. - * - * param base ANACTRL peripheral base address. - */ -void ANACTRL_Deinit(ANACTRL_Type *base) -{ - assert(NULL != base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock for ANACTRL instance. */ - CLOCK_DisableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock output - * and enable/disable 96MHZ clock output. - * - * param base ANACTRL peripheral base address. - * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure. - */ -void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32 = base->FRO192M_CTRL; - - tmp32 &= ~(ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK); - - if (config->enable12MHzClk) - { - tmp32 |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK; - } - if (config->enable96MHzClk) - { - tmp32 |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; - } - - base->FRO192M_CTRL |= tmp32; -} - -/*! - * brief Gets the default configuration of FRO192M. - * The default values are: - * code - config->enable12MHzClk = true; - config->enable96MHzClk = false; - endcode - * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure. - */ -void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enable12MHzClk = true; - config->enable96MHzClk = false; -} - -/*! - * brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU - * system, and so on. - * - * param base ANACTRL peripheral base address. - * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure. - */ -void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32 = base->XO32M_CTRL; - - tmp32 &= ~(ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK | ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK); - - /* Set XO32M CTRL. */ -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) - tmp32 &= ~ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; - if (config->enablePllUsbOutput) - { - tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; - } -#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ - - if (config->enableACBufferBypass) - { - tmp32 |= ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; - } - - if (config->enableSysCLkOutput) - { - tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; - } - base->XO32M_CTRL = tmp32; - -#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) - if (config->enableADCOutput) - { - base->DUMMY_CTRL |= ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK; - } - else - { - base->DUMMY_CTRL &= ~ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK; - } -#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ -} - -/*! - * brief Gets the default configuration of XO32M. - * The default values are: - * code - config->enableSysCLkOutput = false; - config->enableACBufferBypass = false; - endcode - * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure. - */ -void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) - config->enablePllUsbOutput = false; -#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ - config->enableSysCLkOutput = false; - config->enableACBufferBypass = false; -#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) - config->enableADCOutput = true; -#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ -} - -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) -/*! - * brief Measures the frequency of the target clock source. - * - * This function measures target frequency according to a accurate reference frequency.The formula is: - * Ftarget = (CAPVAL * Freference) / ((1<= 2U); - - uint32_t targetClkFreq = 0U; - uint32_t capval = 0U; - - /* Init a measurement cycle. */ - base->FREQ_ME_CTRL = ANACTRL_FREQ_ME_CTRL_PROG_MASK + ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(scale); - while (ANACTRL_FREQ_ME_CTRL_PROG_MASK == (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_PROG_MASK)) - { - } - - /* Calculate the target clock frequency. */ - capval = (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK); - targetClkFreq = (capval * refClkFreq) / ((1UL << scale) - 1UL); - - return targetClkFreq; -} -#endif /* FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_anactrl.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_anactrl.h deleted file mode 100644 index 4ca845b5a9a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_anactrl.h +++ /dev/null @@ -1,377 +0,0 @@ -/* - * Copyright 2018-2021, NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __FSL_ANACTRL_H__ -#define __FSL_ANACTRL_H__ - -#include "fsl_common.h" - -/*! - * @addtogroup anactrl - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief ANACTRL driver version. */ -#define FSL_ANACTRL_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*!< Version 2.3.0. */` - -/*! - * @brief ANACTRL interrupt flags - */ -enum _anactrl_interrupt_flags -{ -#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) - kANACTRL_BodVDDMainFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_MASK, /*!< BOD VDDMAIN Interrupt status - before Interrupt Enable. */ - kANACTRL_BodVDDMainInterruptFlag = - ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_MASK, /*!< BOD VDDMAIN Interrupt status - after Interrupt Enable. */ - kANACTRL_BodVDDMainPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_MASK, /*!< Current value of BOD VDDMAIN - power status output. */ -#else - kANACTRL_BodVbatFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK, /*!< BOD VBAT Interrupt status before - Interrupt Enable. */ - kANACTRL_BodVbatInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK, /*!< BOD VBAT Interrupt status - after Interrupt Enable. */ - kANACTRL_BodVbatPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK, /*!< Current value of BOD VBAT power - status output. */ -#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */ - kANACTRL_BodCoreFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK, /*!< BOD CORE Interrupt status before - Interrupt Enable. */ - kANACTRL_BodCoreInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK, /*!< BOD CORE Interrupt status - after Interrupt Enable. */ - kANACTRL_BodCorePowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK, /*!< Current value of BOD CORE power - status output. */ - kANACTRL_DcdcFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK, /*!< DCDC Interrupt status before - Interrupt Enable. */ - kANACTRL_DcdcInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK, /*!< DCDC Interrupt status after - Interrupt Enable. */ - kANACTRL_DcdcPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK, /*!< Current value of DCDC power - status output. */ -}; - -/*! - * @brief ANACTRL interrupt control - */ -enum _anactrl_interrupt -{ -#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) - kANACTRL_BodVDDMainInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_MASK, /*!< BOD VDDMAIN - interrupt control. */ -#else - kANACTRL_BodVbatInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK, /*!< BOD VBAT interrupt - control. */ -#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */ - kANACTRL_BodCoreInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK, /*!< BOD CORE interrupt - control. */ - kANACTRL_DcdcInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK, /*!< DCDC interrupt control. */ -}; - -/*! - * @brief ANACTRL status flags - */ -enum _anactrl_flags -{ - kANACTRL_FlashPowerDownFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK, /*!< Flash power-down status. */ - kANACTRL_FlashInitErrorFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK, /*!< Flash initialization - error status. */ -}; - -/*! - * @brief ANACTRL FRO192M and XO32M status flags - */ -enum _anactrl_osc_flags -{ - kANACTRL_OutputClkValidFlag = ANACTRL_FRO192M_STATUS_CLK_VALID_MASK, /*!< Output clock valid signal. */ - kANACTRL_CCOThresholdVoltageFlag = ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK, /*!< CCO threshold voltage detector - output (signal vcco_ok). */ - kANACTRL_XO32MOutputReadyFlag = ANACTRL_XO32M_STATUS_XO_READY_MASK << 16U, /*!< Indicates XO out - frequency statibilty. */ -}; - -/*! - * @brief Configuration for FRO192M - * - * This structure holds the configuration settings for the on-chip high-speed Free Running Oscillator. To initialize - * this structure to reasonable defaults, call the ANACTRL_GetDefaultFro192MConfig() function and pass a - * pointer to your config structure instance. - */ -typedef struct _anactrl_fro192M_config -{ - bool enable12MHzClk; /*!< Enable 12MHz clock. */ - bool enable96MHzClk; /*!< Enable 96MHz clock. */ -} anactrl_fro192M_config_t; - -/*! - * @brief Configuration for XO32M - * - * This structure holds the configuration settings for the 32 MHz crystal oscillator. To initialize this - * structure to reasonable defaults, call the ANACTRL_GetDefaultXo32MConfig() function and pass a - * pointer to your config structure instance. - */ -typedef struct _anactrl_xo32M_config -{ - bool enableACBufferBypass; /*!< Enable XO AC buffer bypass in pll and top level. */ -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) - bool enablePllUsbOutput; /*!< Enable XO 32 MHz output to USB HS PLL. */ -#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ - bool enableSysCLkOutput; /*!< Enable XO 32 MHz output to CPU system, SCT, and CLKOUT */ -#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) - bool enableADCOutput; /*!< Enable High speed crystal oscillator output to ADC. */ -#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ -} anactrl_xo32M_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function. - * - * @param base ANACTRL peripheral base address. - */ -void ANACTRL_Init(ANACTRL_Type *base); - -/*! - * @brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function. - * - * @param base ANACTRL peripheral base address. - */ -void ANACTRL_Deinit(ANACTRL_Type *base); -/* @} */ - -/*! - * @name Set oscillators - * @{ - */ - -/*! - * @brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock - * output and enable/disable 96MHZ clock output. - * - * @param base ANACTRL peripheral base address. - * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure. - */ -void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config); - -/*! - * @brief Gets the default configuration of FRO192M. - * The default values are: - * @code - config->enable12MHzClk = true; - config->enable96MHzClk = false; - @endcode - * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure. - */ -void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config); - -/*! - * @brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU - * system, and so on. - * - * @param base ANACTRL peripheral base address. - * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure. - */ -void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config); - -/*! - * @brief Gets the default configuration of XO32M. - * The default values are: - * @code - config->enableSysCLkOutput = false; - config->enableACBufferBypass = false; - @endcode - * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure. - */ -void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config); - -/* @} */ - -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) -/*! - * @name Measure Frequency - * @{ - */ - -/*! - * @brief Measures the frequency of the target clock source. - * - * This function measures target frequency according to a accurate reference frequency.The formula is: - * Ftarget = (CAPVAL * Freference) / ((1<BOD_DCDC_INT_CTRL |= (0x15U & mask); -} - -/*! - * @brief Disables the ANACTRL interrupts. - * - * @param base ANACTRL peripheral base address. - * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration. - */ -static inline void ANACTRL_DisableInterrupts(ANACTRL_Type *base, uint32_t mask) -{ - base->BOD_DCDC_INT_CTRL &= ~(0x15U & mask); -} - -/*! - * @brief Clears the ANACTRL interrupts. - * - * @param base ANACTRL peripheral base address. - * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration. - */ -static inline void ANACTRL_ClearInterrupts(ANACTRL_Type *base, uint32_t mask) -{ - base->BOD_DCDC_INT_CTRL |= (uint32_t)(mask << 1UL); -} -/* @} */ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets ANACTRL status flags. - * - * This function gets Analog control status flags. The flags are returned as the logical - * OR value of the enumerators @ref _anactrl_flags. To check for a specific status, - * compare the return value with enumerators in the @ref _anactrl_flags. - * For example, to check whether the flash is in power down mode: - * @code - * if (kANACTRL_FlashPowerDownFlag & ANACTRL_ANACTRL_GetStatusFlags(ANACTRL)) - * { - * ... - * } - * @endcode - * - * @param base ANACTRL peripheral base address. - * @return ANACTRL status flags which are given in the enumerators in the @ref _anactrl_flags. - */ -static inline uint32_t ANACTRL_GetStatusFlags(ANACTRL_Type *base) -{ - return base->ANALOG_CTRL_STATUS; -} - -/*! - * @brief Gets ANACTRL oscillators status flags. - * - * This function gets Anactrl oscillators status flags. The flags are returned as the logical - * OR value of the enumerators @ref _anactrl_osc_flags. To check for a specific status, - * compare the return value with enumerators in the @ref _anactrl_osc_flags. - * For example, to check whether the FRO192M clock output is valid: - * @code - * if (kANACTRL_OutputClkValidFlag & ANACTRL_ANACTRL_GetOscStatusFlags(ANACTRL)) - * { - * ... - * } - * @endcode - * - * @param base ANACTRL peripheral base address. - * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags. - */ -static inline uint32_t ANACTRL_GetOscStatusFlags(ANACTRL_Type *base) -{ - return (base->FRO192M_STATUS & 0xFFU) | ((base->XO32M_STATUS & 0xFFU) << 16U); -} - -/*! - * @brief Gets ANACTRL interrupt status flags. - * - * This function gets Anactrl interrupt status flags. The flags are returned as the logical - * OR value of the enumerators @ref _anactrl_interrupt_flags. To check for a specific status, - * compare the return value with enumerators in the @ref _anactrl_interrupt_flags. - * For example, to check whether the VBAT voltage level is above the threshold: - * @code - * if (kANACTRL_BodVbatPowerFlag & ANACTRL_ANACTRL_GetInterruptStatusFlags(ANACTRL)) - * { - * ... - * } - * @endcode - * - * @param base ANACTRL peripheral base address. - * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags. - */ -static inline uint32_t ANACTRL_GetInterruptStatusFlags(ANACTRL_Type *base) -{ - return base->BOD_DCDC_INT_STATUS & 0x1FFU; -} -/* @} */ - -#if (defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) && (FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG == 1U)) -/*! - * @brief Aux_Bias Control Interfaces - * @{ - */ - -/*! - * @brief Enables/disabless 1V reference voltage buffer. - * - * @param base ANACTRL peripheral base address. - * @param enable Used to enable or disable 1V reference voltage buffer. - */ -static inline void ANACTRL_EnableVref1V(ANACTRL_Type *base, bool enable) -{ - if (enable) - { - base->AUX_BIAS |= ANACTRL_AUX_BIAS_VREF1VENABLE_MASK; - } - else - { - base->AUX_BIAS &= ~ANACTRL_AUX_BIAS_VREF1VENABLE_MASK; - } -} - -/* @} */ -#endif /* defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) */ - -#if defined(__cplusplus) -} -#endif - -/* @}*/ - -#endif /* __FSL_ANACTRL_H__ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_casper.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_casper.c deleted file mode 100644 index 97c2613fd16..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_casper.c +++ /dev/null @@ -1,3433 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_casper.h" -#include /* ceil TODO check if really need it */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.casper" -#endif - -/* Recoding length for the secure scalar multiplication: - * Use n=256 and w=4 --> compute ciel(384/3) = 86 + 1 digits - * Use n=384 and w=4 --> compute ciel(384/3) = 128 + 1 digits - * Use n=521 and w=4 --> compute ciel(521/3) = 174 + 1 digits - */ - -/*!< Recoding length for the secure scalar multiplication */ -enum _casper_ecc_recode_len -{ - kCASPER_ECC_P256_recode_len = 87u, - kCASPER_ECC_P384_recode_len = 129u, - kCASPER_ECC_P521_recode_len = 175u, -}; - -enum _casper_ecc_N_bitlen -{ - kCASPER_ECC_P256_N_bitlen = 256u, - kCASPER_ECC_P384_N_bitlen = 384u, - kCASPER_ECC_P521_N_bitlen = 576u, -}; - -enum _casper_ecc_N_wordlen -{ - kCASPER_ECC_P256_wordlen = 256U / 32U, - kCASPER_ECC_P384_wordlen = 384u / 32U, - kCASPER_ECC_P521_wordlen = 576u / 32U, -}; - -#if defined(__GNUC__) -/* Enforce O1 optimize level, specifically to remove strict-aliasing option. - (-fno-strict-aliasing is required for this driver). */ -#pragma GCC push_options -#pragma GCC optimize("-O1") -#endif - -#if (defined(__CC_ARM) || defined(__ARMCC_VERSION)) -/* Enforce optimization off for clang, specifically to remove strict-aliasing option. -(-fno-strict-aliasing is required for this driver). */ -#pragma clang optimize off -#endif - -/* CASPER driver allows usage of 256, 384 and 521 ECC */ -#define CASPER_MAX_ECC_SIZE_WORDLEN (576u / 32U) -#define CASPER_RECODE_LENGTH_MAX 175 - -#define CASPER_RAM_BASE_NS (FSL_FEATURE_CASPER_RAM_BASE_ADDRESS) - -#if defined(FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED) && FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED -#define CASPER_RAM_OFFSET (FSL_FEATURE_CASPER_RAM_OFFSET) -#define INTERLEAVE(addr) \ - (((((((addr) >> 2U) & 0x00000001U) << CASPER_RAM_OFFSET) + (((addr) >> 3U) << 2U) + ((addr)&0x00000003U)) & \ - 0xFFFFU) | \ - s_casperRamBase) -#define DEINTERLEAVE(addr) INTERLEAVE(addr) -#define GET_WORD(addr) (*((uint32_t *)DEINTERLEAVE((uint32_t)(addr)))) -#define GET_DWORD(addr) (((uint64_t)GET_WORD(addr)) | (((uint64_t)GET_WORD(((uint32_t)(addr)) + 4U)) << 32U)) -#define SET_WORD(addr, value) *((uint32_t *)INTERLEAVE((uint32_t)(addr))) = ((uint32_t)(value)) -#define SET_DWORD(addr, value) \ - do \ - { \ - SET_WORD(addr, (uint32_t)(value & 0xFFFFFFFFU)); \ - SET_WORD(((uint32_t)(addr)) + 4U, (uint32_t)((value & 0xFFFFFFFF00000000U) >> 32U)); \ - } while (false) - -/* memcopy is always word aligned */ -/* interleaved to interleaved - static void CASPER_MEMCPY_I2I(void *dst, const void *src, size_t siz) - */ -#define CASPER_MEMCPY_I2I(dst, src, siz) \ - \ - { \ - uint32_t *dst32 = (uint32_t *)(dst); \ - const uint32_t *src32 = (const uint32_t *)(const uint32_t *)(src); \ - uint32_t i; \ - for (i = 0U; i < (siz) / 4U; i++) \ - { \ - SET_WORD(&dst32[i], GET_WORD(&src32[i])); \ - } \ - } - -/* interleaved to non-interleaved - static void CASPER_MEMCPY_I2N(void *dst, const void *src, size_t siz) - */ -#define CASPER_MEMCPY_I2N(dst, src, siz) \ - \ - { \ - uint32_t *dst32 = (uint32_t *)(dst); \ - const uint32_t *src32 = (const uint32_t *)(const uint32_t *)(src); \ - uint32_t i; \ - for (i = 0U; i < (siz) / 4U; i++) \ - { \ - dst32[i] = GET_WORD(&src32[i]); \ - } \ - } - -/* non-interleaved to interleaved - static void CASPER_MEMCPY_N2I(void *dst, const void *src, size_t siz) - */ -#define CASPER_MEMCPY_N2I(dst, src, siz) \ - \ - { \ - volatile uint32_t *dst32 = (uint32_t *)(dst); \ - const uint32_t *src32 = (const uint32_t *)(const uint32_t *)(src); \ - uint32_t i; \ - for (i = 0U; i < (siz) / 4U; i++) \ - { \ - SET_WORD(&dst32[i], src32[i]); \ - } \ - } -#else -#define GET_WORD(addr) (*((uint32_t *)(uint32_t)(addr))) -#define GET_DWORD(addr) (*((uint64_t *)(addr))) -#define SET_WORD(addr, value) *((uint32_t *)(uint32_t)(addr)) = ((uint32_t)(value)) -#define SET_DWORD(addr, value) *((uint64_t *)(addr)) = ((uint64_t)(value)) - -#define CASPER_MEMCPY_I2I(dst, src, siz) (void)memcpy(dst, src, siz) -#define CASPER_MEMCPY_I2N(dst, src, siz) (void)memcpy(dst, src, siz) -#define CASPER_MEMCPY_N2I(dst, src, siz) (void)memcpy(dst, src, siz) -#endif - -#define WORK_BUFF_MUL4 (N_wordlen_max * 4 + 2) /* ! working buffer is 4xN_wordlen to allow in place math */ -#define N_bytelen (N_wordlen * 4U) /* for memory copy and the like */ -#define N_dwordlen (unsigned)(N_wordlen / 2U) - -#define PreZeroW(i, w_out) \ - for ((i) = 0U; (i) < N_wordlen; (i) += 4U) \ - { \ - SET_WORD(&(w_out)[(i) + 0U], 0U); \ - SET_WORD(&(w_out)[(i) + 1U], 0U); \ - SET_WORD(&(w_out)[(i) + 2U], 0U); \ - SET_WORD(&(w_out)[(i) + 3U], 0U); \ - } /* unrolled partly */ -#define PreZeroW2up(i, w_out) \ - for (i = N_wordlen; i <= N_wordlen * 2U; i += 4U) \ - { \ - SET_WORD(&w_out[i + 0U], 0U); \ - SET_WORD(&w_out[i + 1U], 0U); \ - SET_WORD(&w_out[i + 2U], 0U); \ - SET_WORD(&w_out[i + 3U], 0U); \ - } /* unrolled partly */ - -/* Macros for the ECC component in Casper */ - -/* CASPER memory layout for ECC */ - -#define CASPER_MEM ((uint32_t *)msg_ret) - -/* Currently these macros work on 32-bit platforms */ - -#define add(c1, c0, a, b) \ - \ - do \ - { \ - uint32_t _t; \ - _t = a + b; \ - c1 = (uint32_t)(_t < a); \ - c0 = _t; \ - \ - } while (false) - -#define add_cout(carry, c, a, b) add((carry), (c), (a), (b)) - -#define add_cout_cin(carryout, c, a, b, carryin) \ - do \ - { \ - uint64_t _t = (uint64_t)(a) + (b) + (carryin); \ - (c) = (uint32_t)_t; \ - (carryout) = (uint32_t)(_t >> 32); \ - } while (false) - -#define sub_borrowout(borrow, c, a, b) \ - do \ - { \ - uint32_t _b = (uint32_t)((b) > (a)); \ - (c) = (a) - (b); \ - (borrow) = _b; \ - } while (false) - -#define sub_borrowin_borrowout(borrowout, c, a, b, borrowin) \ - do \ - { \ - uint32_t _t, _borrow1, _borrow2; \ - sub_borrowout(_borrow1, _t, (a), (b)); \ - sub_borrowout(_borrow2, (c), _t, (borrowin)); \ - (borrowout) = _borrow1 + _borrow2; \ - } while (false) - -#define sub_borrowout_1(borrow, c, a) \ - do \ - { \ - uint32_t _b = 0; \ - c = a - b; \ - borrow = _b; \ - } while (false) - -#define sub_borrowin_borrowout_1(borrowout, c, a, borrowin) \ - do \ - { \ - uint32_t _t, _borrow1, _borrow2; \ - sub_borrowout_1(_borrow1, _t, a); \ - sub_borrowout(_borrow2, c, _t, borrowin); \ - borrowout = _borrow1 + _borrow2; \ - } while (false) - -/* 32 x 32 --> 64-bit multiplication - * (c1,c0) = a * b - */ -#define mul(c1, c0, a, b) \ - \ - do \ - { \ - uint64_t __m; \ - __m = (uint64_t)a * (uint64_t)b; \ - c0 = (uint32_t)__m; \ - c1 = (uint32_t)(__m >> (uint64_t)32); \ - \ - } while (false) - -/* Multiply-and-accumulate - * (c1,c0) = a*b+c0 - */ -#define muladd(c1, c0, a, b) \ - \ - do \ - { \ - uint32_t __ma = c0; \ - mul(c1, c0, a, b); \ - c0 = c0 + __ma; \ - c1 = c1 + (c0 < __ma); \ - \ - } while (0) - -/* Multiply-and-accumulate-accumulate - * (c1,c0) = a*b+c0+c1 - */ -#define muladdadd(c1, c0, a, b) \ - \ - do \ - { \ - uint32_t __maa0 = c0, __maa1 = c1; \ - mul(c1, c0, a, b); \ - c0 = c0 + __maa0; \ - c1 = c1 + (c0 < __maa0); \ - c0 = c0 + __maa1; \ - c1 = c1 + (c0 < __maa1); \ - \ - } while (0) - -#define square_casper(c, a) multiply_casper(c, a, a) -#define sub_casper(c, a, b) CASPER_montsub(c, a, b, &CASPER_MEM[(N_wordlen + 4U)]) -#define add_casper(c, a, b) CASPER_montadd(c, a, b, &CASPER_MEM[(N_wordlen + 4U)]) -#define mul2_casper(c, a) add_casper(c, a, a) -#define half(c, a, b) CASPER_half(c, a, b) -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* The model for this algo is that it can be implemented for a fixed size RSA key */ -/* for max speed. If this is made into a variable (to allow varying size), then */ -/* it will be slower by a bit. */ -/* The file is compiled with N_bitlen passed in as number of bits of the RSA key */ -/* #define N_bitlen 2048 */ -static size_t N_wordlen = 0U; /* ! number of words (e.g. 4096/32 is 128 words) */ - -static uint32_t s_casperRamBase = CASPER_RAM_BASE_NS; -static uint32_t *msg_ret = (uint32_t *)CASPER_RAM_BASE_NS; - -/* NISTp-256 = 2^256-2^224+2^192+2^96-1 */ -static uint32_t NISTp256[256 / 32u] = {0xffffffffU, 0xffffffffU, 0xffffffffU, 0x00000000, - 0x00000000, 0x00000000, 0x00000001, 0xffffffffU}; - -/* The cardinality of the curve E(F_p) */ -static uint32_t NISTp256_q[256 / 32u] = {0xfc632551U, 0xf3b9cac2U, 0xa7179e84U, 0xbce6faadU, - 0xffffffffU, 0xffffffffU, 0x00000000, 0xffffffffU}; - -/* R = 2^256 mod p, the value "1" in Montgomery form. */ -static uint32_t NISTr256[256 / 32u] = {0x00000001, 0x00000000, 0x00000000, 0xffffffffU, - 0xffffffffU, 0xffffffffU, 0xfffffffeU, 0x00000000}; - -static uint32_t Np256[2] = {1, 0}; - -/* NISTp-384 = 2^384 - 2^128 - 2^96 + 2^32 - 1 */ -static uint32_t NISTp384[384 / 32u] = {0xffffffffU, 0x00000000, 0x00000000, 0xffffffffU, 0xfffffffeU, 0xffffffffU, - 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU}; - -/* The cardinality of the curve E(F_p) */ -static uint32_t NISTp384_q[384 / 32u] = {0xccc52973U, 0xecec196aU, 0x48b0a77aU, 0x581a0db2U, 0xf4372ddfU, 0xc7634d81U, - 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU}; - -/* R = 2^256 mod p, the value "1" in Montgomery form. */ -static uint32_t NISTr384[384 / 32u] = {0x00000001, 0xffffffffU, 0xffffffffU, 0x00000000, 0x1, 0, 0, 0, 0, 0, 0, 0}; - -// -p^-1 mod 2^64 = 0x100000001 -static uint32_t Np384[2] = {1, 1}; - -/* NISTp-521 = 2^521 - 1 */ -static uint32_t NISTp521[576 / 32U] = {0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, - 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, - 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0x1ffU, 0}; - -/* The cardinality of the curve E(F_p) */ -static uint32_t NISTp521_q[576 / 32U] = {0x91386409U, 0xbb6fb71eU, 0x899c47aeU, 0x3bb5c9b8U, 0xf709a5d0U, 0x7fcc0148U, - 0xbf2f966bU, 0x51868783U, 0xfffffffaU, 0xffffffffU, 0xffffffffU, 0xffffffffU, - 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0x1ffU, 0}; - -/* R = 2^576 mod p, the value "1" in Montgomery form. */ -static uint32_t NISTr521[576 / 32U] = {0, 0x800000, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - -/* -p^-1 mod 2^64 = 1 */ -static uint32_t Np521[2] = {1, 0}; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/* Convert a projective point (X1 : Y1 : Z1) - * to the affine point (X3, Y3) = (X1/Z1^2,Y1/Z1^3) - * The memory of (X3, Y3) and (X1 : Y1 : Z1) should not overlap - */ -void Jac_toAffine(uint32_t *X3, uint32_t *Y3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1); - -/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2 : Y2 : Z2) - * where (X1: Y1: Z1) != (X2 : Y2 : Z2) - * (X3 : Y3: Z3) may be the same as one of the inputs. - */ -void Jac_addition(uint32_t *X3, - uint32_t *Y3, - uint32_t *Z3, - uint32_t *X1, - uint32_t *Y1, - uint32_t *Z1, - uint32_t *X2, - uint32_t *Y2, - uint32_t *Z2); - -/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2, Y2) - * where (X1: Y1: Z1) != (X2, Y2) - * (X3 : Y3: Z3) may not overlap with (X1: Y1: Z1). - * Source: 2004 Hankerson?Menezes?Vanstone, page 91. - */ -void Jac_add_affine( - uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *X2, uint32_t *Y2); - -/* Point doubling from: 2004 Hankerson?Menezes?Vanstone, page 91. - * Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X1 : Y1 : Z1) - * (X3 : Y3: Z3) may be the same as the input. - */ -void Jac_double(uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1); - -/* Constant time elliptic curve scalar multiplication. - * Source: https://eprint.iacr.org/2014/130.pdf - * when using w = 4. - * Computes (X3 : Y3 : Z3) = k * (X1, Y1) \in E(F_p) - * p is the prime used to define the finite field F_p - * q is the (prime) order of the curve - */ -void Jac_scalar_multiplication( - uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *k, uint32_t *p, uint32_t *q); - -/* Compute the double scalar multiplication - * (X3 : Y3 : Z3) = k1 * (X1, Y1) + k2 * (X2, Y2) - * Using Shamir's trick and precomputing 16 points. - * This code is *not* constant time since this is used - * for verification only. - */ -void double_scalar_multiplication(uint32_t *X3, - uint32_t *Y3, - uint32_t *Z3, - uint32_t *X1, - uint32_t *Y1, - uint32_t *k1, - uint32_t *X2, - uint32_t *Y2, - uint32_t *k2); - -/* Compute inversion modulo NIST-p384 using Fermats little theorem. - * Using c = a^(p-2) = a^(-1) mod p. - * This computes the modular inversion if all arithmetic is "regular" - * modular arithmetic or computes automatically the Montgomery inverse - * if all arithmetic is Montgomery arithmetic. - */ -static void invert_mod_p384(uint32_t *c, uint32_t *a); - -/* Modular inversion for NIST-P256 */ -static void invert_mod_p256(uint32_t *c, uint32_t *a); - -/* Modular inversion for NIST-P521 */ -static void invert_mod_p521(uint32_t *c, uint32_t *a); - -// A and C do not need to be in Casper memory -static void toMontgomery_ECC_P256(uint32_t *C, uint32_t *A); -static void toMontgomery_ECC_P384(uint32_t *C, uint32_t *A); -static void toMontgomery_ECC_P521(uint32_t *C, uint32_t *A); - -static void CASPER_montsub(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod); -static void CASPER_montadd(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod); - -/* Compute c = a/2 mod p where b is scratch space. */ -static void CASPER_half(uint32_t *c, uint32_t *a, uint32_t *b); - -void CASPER_MEMCPY(void *dst, const void *src, size_t siz); - -static void multiply_casper(uint32_t w_out[], const uint32_t a[], const uint32_t b[]); - -static uint8_t int8abs(int8_t v); - -/* Constant time select c = a if m = 0 or - * c = b if m = 1 - * a, b, c are n words - */ -static void casper_select(uint32_t *c, uint32_t *a, uint32_t *b, int m, int n); - -/* Dumb n-limb addition of c=a+b, return carry. */ -static uint32_t add_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n); - -#if 0 -/* Dumb n-limb addition of c=a+b, return carry. */ -static uint32_t add_n(uint32_t *c, uint32_t *a, uint32_t *b, int n); - -/* Dumb n-limb subtraction of c=a-b, return borrow. */ -static uint32_t sub_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n); -#endif - -/* Dumb n-limb subtraction of c=a-b, return borrow. */ -static uint32_t sub_n(uint32_t *c, uint32_t *a, uint32_t *b, int n); - -int RSA_SignatureToPlaintextFast(const unsigned signature[N_wordlen_max], - const unsigned exp_pubkey, - const unsigned pubkey[N_wordlen_max], - unsigned MsgRet[WORK_BUFF_MUL4]); - -int RSA_MontSignatureToPlaintextFast(const unsigned mont_signature[N_wordlen_max], - const unsigned exp_pubkey, - const unsigned pubkey[N_wordlen_max], - unsigned MsgRet[WORK_BUFF_MUL4]); - -void MultprecMultiply(unsigned w_out[], const unsigned u[], const unsigned v[]); - -void MultprecGenNp64(const unsigned *Nmod, unsigned *np64_ret); -void MultprecMontPrepareX(unsigned Xmont_out[], const unsigned x[], const unsigned Rp[], const unsigned Nmod[]); -void MultprecModulo(unsigned r_out[], const unsigned v[], int top); -void MultprecCiosMul( - unsigned w_out[], const unsigned a[], const unsigned b[], const unsigned Nmod[], const unsigned *Np); -void MultprecMontCalcRp(unsigned Rp[], const unsigned exp_pubkey, const unsigned Nmod[]); - -static void MultprecCiosMul_ct( - uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np); - -static void MultprecCiosMul521_ct( - uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np); - -static void shiftrightSysram(uint32_t *z, uint32_t *x, uint32_t c); -static void shiftright(uint32_t *z, uint32_t *x, uint32_t c); -static void shiftleft(uint32_t *z, uint32_t *x, uint32_t c); - -/******************************************************************************* - * Code - ******************************************************************************/ - -__STATIC_FORCEINLINE uint32_t CA_MK_OFF(const void *addr) -{ - return ((uint32_t)(const uint32_t *)addr - s_casperRamBase); -} - -#if 1 -__STATIC_FORCEINLINE void Accel_done(void) -{ - register uint32_t status; - do - { - status = CASPER->STATUS; - } while (0U == (status & CASPER_STATUS_DONE_MASK)); -} - -__STATIC_FORCEINLINE void Accel_SetABCD_Addr(uint32_t ab, uint32_t cd) -{ - CASPER->CTRL0 = ab | (cd << 16); /* CDoffset << 16 | ABoffset */ -} - -__STATIC_FORCEINLINE void Accel_crypto_mul(uint32_t ctrl1) -{ - CASPER->CTRL1 = ctrl1; -} -#else -#include "intrinsics.h" -#define Accel_done() \ - { \ - register uint32_t status; \ - do \ - { \ - status = CASPER_Rd32b(CASPER_CP_STATUS); \ - } while (0 == (status & CASPER_STATUS_DONE_MASK)); \ - } -#if 0 -__STATIC_FORCEINLINE void Accel_done(void) -{ - register uint32_t status; - do - { - status = CASPER->STATUS; - } while (0 == (status & CASPER_STATUS_DONE_MASK)); -} -#endif -#define Accel_SetABCD_Addr(ab, cd) CASPER_Wr32b((uint32_t)ab | ((uint32_t)cd << 16), CASPER_CP_CTRL0); -#define Accel_crypto_mul(ctrl1) CASPER_Wr32b((uint32_t)ctrl1, CASPER_CP_CTRL1); -#endif - -__STATIC_FORCEINLINE uint32_t Accel_IterOpcodeResaddr(uint32_t iter, uint32_t opcode, uint32_t resAddr) -{ - return CASPER_CTRL1_ITER(iter) | CASPER_CTRL1_MODE(opcode) | (resAddr << 16); -} - -void CASPER_MEMCPY(void *dst, const void *src, size_t siz) -{ - bool bdst = - ((((uint32_t)(uint32_t *)dst) | 0x10000000u) >= ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) && - (((uint32_t)(uint32_t *)dst) | 0x10000000u) < - ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) + 8u * 1024u); - - bool bsrc = ((((uint32_t)(const uint32_t *)src) | 0x10000000u) >= - ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) && - (((uint32_t)(const uint32_t *)src) | 0x10000000u) < - ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) + 8u * 1024u); - - if (bdst && bsrc) - { - CASPER_MEMCPY_I2I(dst, src, siz); - } - else if (bdst && !bsrc) - { - CASPER_MEMCPY_N2I(dst, src, siz); - } - else if (!bdst && bsrc) - { - CASPER_MEMCPY_I2N(dst, src, siz); - } - else - { - (void)memcpy(dst, src, siz); - } -} - -/* Constant time select c = a if m = 0 or - * c = b if m = 1 - * a, b, c are n words - */ -static void casper_select(uint32_t *c, uint32_t *a, uint32_t *b, int m, int n) -{ - uint32_t m1 = 0U - (uint32_t)m, m2 = ~m1; - int i; - - for (i = 0; i < n; i++) - { - SET_WORD(&c[i], (GET_WORD(&a[i]) & m2) | (GET_WORD(&b[i]) & m1)); - } -} - -/* Compute R`, which is R mod N. This is done using subtraction */ -/* R has 1 in N_wordlen, but we do not fill it in since borrowed. */ -/* Exp-pubkey only used to optimize for exp=3 */ -void MultprecMontCalcRp(unsigned Rp[], const unsigned exp_pubkey, const unsigned Nmod[]) -{ - uint32_t i; - - /* R is 2^n where n is 1 bit longer than Nmod, so 1 followed by 32 or 64 0 words for example */ - /* Note that Nmod's upper most bit has to be 1 by definition, so one subtract is enough. We */ - /* do not set the 1 since it is "borrowed" so no point */ - PreZeroW(i, Rp); - Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(Rp))); - Accel_done(); - /* final borrow cannot happen since we know we started with a larger number */ -} - -/* MultprecMultiply - multiple w=u*v (per Knuth) */ -/* w_out is 2x the size of u and v */ -void MultprecMultiply(unsigned w_out[], const unsigned u[], const unsigned v[]) -{ - uint32_t i, j; - - /* Knuth 4.3.1 - Algorithm M */ - /* Compute w = u * v */ - /* u and v are N bits long in 32 bit word form */ - /* w is 2*N bits long in 32 bit word form */ - /* Note: We just multiply in place */ - - /* Step 1. Fill w[t-1:0] with 0s, the upper half will be written as we go */ - PreZeroW(i, w_out); - - /* We do 1st pass NOSUM so we do not have to 0 output */ - Accel_SetABCD_Addr(CA_MK_OFF(&v[0]), CA_MK_OFF(u)); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpMul6464NoSum, CA_MK_OFF(&w_out[0]))); - Accel_done(); - /* Step 2. iterate over N words of v using j */ - for (j = 2U; j < N_wordlen; j += 2U) - { - /* Step 2b. Check for 0 on v word - skip if so since we 0ed already */ - /* Step 3. Iterate over N words of u using i - perform Multiply-accumulate */ - if (0U != (GET_WORD(&v[j])) || 0U != (GET_WORD(&v[j + 1U]))) - { - Accel_SetABCD_Addr(CA_MK_OFF(&v[j]), CA_MK_OFF(u)); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpMul6464Sum, CA_MK_OFF(&w_out[j]))); - Accel_done(); - } - } -} - -/* MultprecModulo performs divide to get remainer as needed for RSA */ -/* This performs (q,r) = u/v, but we do not keep q */ -/* r_out is module (remainder) and is 2*N */ -/* u is in r_out (1st N) at start (passed in) */ -/* v is N long */ -void MultprecModulo(unsigned r_out[], const unsigned v[], int top) -{ - uint64_t u64; /* use 64 bit math mixed with 32 bit */ - unsigned u32; /* allows us to work on U in 32 bit */ - unsigned u_n, ul16, uh16, *u_shft; /* u_shft is because r_out is u initially */ - unsigned vl16, vh16, v_Nm1; - unsigned q_hat, r_hat, q_over; - unsigned borrow, carry; - uint32_t i; - int j, tmp; - - /* Knuth 4.3.1 - Algorithm D */ - /* Compute q = u / v giving remainder r = u mod v */ - /* -- we only want r, so we build qhat but do not store the Qs */ - /* v is N long, with u,q,r 2N long because u is slowly replavced by r. */ - /* We normalize/unnormlize per Knuth in the buffer (not copied) */ - - /* Step 1. Normalize value so MSb is in v[n-1]. Remember that v is */ - /* the public key - to call it a 2048 bit number, they cannot have 0 */ - /* in the MSb (or it would be less than 2048 bits) and so we know we */ - /* are normalized already. Therefore, u is effectively shifted already. */ - /* For u, we have it in r_out. u[n] holds any overflow */ - /* Since divide on CM3/4 is 32/32=32, we break into 16 bit halves, but */ - /* multiply can be 32x32=64. */ - u_n = 0; - u_shft = r_out; /* u (shifted) is in r_out */ - - v_Nm1 = GET_WORD(&v[N_wordlen - 1U]); /* MSw of public key */ - vl16 = v_Nm1 & 0xFFFFU; /* lower 16 */ - vh16 = v_Nm1 >> 16; /* upper 16 */ - /* Step 2. Iterate j from m-n down to 0 (M selected per Knuth as 2*N) */ - for (j = top; j >= 0; j--) - { - /* Step 3. estimate q_hat as (U[j+n]*B + U[j+n-1]) / V[n-1] */ - /* Note: using subset of Knuth algo since v is 1/2 len of u (which is */ - /* from multiply or x^2 leading into this). */ - u32 = u_n; /* pickup u4u3u2, knowing u4 is 0 */ - u64 = ((uint64_t)u_n << 32) | GET_WORD(&u_shft[(uint32_t)j + N_wordlen - 1U]); - ul16 = (unsigned int)(u64 & 0xFFFFU); /* lower 16 */ - uh16 = (unsigned int)((u64 >> 16) & 0xFFFFU); /* upper 16 */ - - /* we see if even possible (u large enough relative to v) */ - if ((u32 - v_Nm1) <= u32) - { - u32 -= v_Nm1; - q_over = 1; /* overflow from the sub */ - } - else - { - q_over = 0; - } - /* q_hat = u32 / vh16 -- is the upper partial value */ - /* estimate; if too much, then back down by 1 or 2 */ - q_hat = u32 / vh16; - r_hat = u32 - (q_hat * vh16); - /* see if Q is more than 16 bits or remainder is too large (over div) */ - if ((q_hat == 0x10000U) || ((q_hat * vl16) > ((r_hat << 16) | uh16))) - { - /* too much - undo a division */ - q_hat--; - r_hat += vh16; - /* check if still too much */ - if ((r_hat < 0x10000U) && ((q_hat * vl16) > ((r_hat << 16) | uh16))) - { - q_hat--; /* yes, so undo a 2nd */ - } - } - - /* compose u3u2uh16, then sub q_hat*v if OK */ - u64 = (((uint64_t)u32 << 16) | uh16) - ((uint64_t)q_hat * v_Nm1); - if (0U != (u64 >> 48)) - { - /* no, so add v back */ - u32 = (unsigned)(u64 + v_Nm1); - q_hat--; - } - else - { - u32 = (unsigned)u64; - } - tmp = (int32_t)(uint32_t)(q_hat << 16); /* quotient upper part */ - - /* divide lower part: q = u2uh16ul16 / v. */ - /* estimate and add back if over divdied */ - q_hat = u32 / vh16; - r_hat = u32 - (q_hat * vh16); - if ((q_hat == 0x10000U) || ((q_hat * vl16) > ((r_hat << 16) | ul16))) - { - /* too much - undo a division */ - q_hat--; - r_hat += vh16; - /* check if still too much */ - if ((r_hat < 0x10000U) && ((q_hat * vl16) > ((r_hat << 16) | ul16))) - { - q_hat--; /* yes, so undo a 2nd */ - } - } - - /* compose u2uh16ul16, then sub q_hat*v if OK */ - u64 = (((uint64_t)u32 << 16) | ul16) - ((uint64_t)q_hat * v_Nm1); - if (0U != (u64 >> 48)) - { - /* no, so add v back */ - r_hat = (unsigned)(u64 + v_Nm1); - q_hat--; - } - else - { - r_hat = (unsigned)u64; - } - q_hat |= (unsigned)tmp; /* other half of the quotient */ - while ((q_over != 0U) || ((uint64_t)q_hat * GET_WORD(&v[N_wordlen - 2U])) > - ((1ULL << 32) * r_hat) + (uint64_t)GET_WORD(&u_shft[(uint32_t)j + N_wordlen - 2U])) - { /* if Qhat>b, then reduce to b-1, then adjust up Rhat */ - q_hat--; - r_hat += v_Nm1; - if (r_hat < v_Nm1) - { - break; /* no overflow */ - /* else repeat since Rhat >= b */ - } - } - - /* Step 4. Multiply and subtract. We know the amount, */ - /* so we do the schoolboy math. Have to do on */ - /* the large value. */ - if (q_hat != 0U) - { - borrow = 0; - for (i = 0; i < N_wordlen; i++) - { - u64 = (uint64_t)q_hat * GET_WORD(&v[i]) + borrow; - borrow = (unsigned)(u64 >> 32); - if (GET_WORD(&u_shft[i + (unsigned)j]) < (unsigned)u64) - { - borrow++; /* carry the overflow */ - } - SET_WORD(&u_shft[i + (unsigned)j], GET_WORD(&u_shft[i + (unsigned)j]) - (unsigned)u64); - } - u_n -= borrow; /* overflow from shift left does not fit otherwise */ - } - - /* Store 5. (update Q - we don't), and add back V to remainder if we over-subtracted */ - /* That restores remainder to correct (we could only be off by 1) */ - /* This should happen very rarely. */ - if (u_n != 0U) - { - carry = 0; - for (i = 0; i < N_wordlen; i++) - { - SET_WORD(&u_shft[i + (unsigned)j], GET_WORD(&u_shft[i + (unsigned)j]) + carry); - carry = (GET_WORD(&u_shft[i + (unsigned)j]) < carry) ? 1U : 0U; - SET_WORD(&u_shft[i + (unsigned)j], GET_WORD(&u_shft[i + (unsigned)j]) + GET_WORD(&v[i])); - if (GET_WORD(&u_shft[i + (unsigned)j]) < GET_WORD(&v[i])) - { - carry++; - } - } - } - u_n = GET_WORD( - &u_shft[(uint32_t)j + N_wordlen - 1U]); /* hold upper part of u to catch overflow (to borrow from) */ - } - /* low N bits of r are valid as remainder */ -} - -/* We convert X into a Mont form number. Note length of arrays: */ -/* x is N_wordlen, Nmod is N_wordlen */ -/* Rp is N_wordlen (it is R` which is R mod N) */ -/* Xmont_out is N_wordlen*2+1 */ -void MultprecMontPrepareX(unsigned Xmont_out[], const unsigned x[], const unsigned Rp[], const unsigned Nmod[]) -{ - MultprecMultiply(Xmont_out, x, Rp); - MultprecModulo(Xmont_out, Nmod, (int32_t)N_wordlen); -} - -void MultprecGenNp64(const unsigned *Nmod, unsigned *np64_ret) /* only pass the low order double word */ -{ - uint64_t nprime, Nmod_0; - Nmod_0 = GET_WORD(&Nmod[0]) | ((uint64_t)GET_WORD(&Nmod[1]) << 32); - -#define COMP_NPN_1 ((2U - Nmod_0 * nprime) * nprime) /* computes N`*N0=1 mod 2^P where P is the partial built up */ - nprime = (((2U + Nmod_0) & 4U) << 1) + Nmod_0; /* mod 2^4 */ - nprime = COMP_NPN_1; - nprime = COMP_NPN_1; - nprime = COMP_NPN_1; - nprime = COMP_NPN_1; - /* 8 multiplies of uint64_t */ - *((uint64_t *)(uintptr_t)np64_ret) = (~0ULL - nprime) + 1ULL; -} - -/* CIOS Multiply. This is the Coarse Integrated form where the values are */ -/* multiplied and reduced for each step of "i". This uses less memory and */ -/* is faster as a result. Note that this is used to square as well as mul, */ -/* so not as fast as pure squaring could be. */ -void MultprecCiosMul( - unsigned w_out[], const unsigned a[], const unsigned b[], const unsigned Nmod[], const unsigned *Np) -{ - int j; - uint32_t i; - uint64_t *m64 = (uint64_t *)(uintptr_t)&msg_ret[kCASPER_RamOffset_M64]; - uint64_t Np64; - uint64_t carry; - uint64_t *a64, *b64, *w64, *N64; - - Np64 = *(uint64_t *)(uintptr_t)Np; - - a64 = (uint64_t *)(uintptr_t)a; - b64 = (uint64_t *)(uintptr_t)b; - w64 = (uint64_t *)(uintptr_t)w_out; - N64 = (uint64_t *)(uintptr_t)Nmod; - - if (a != NULL) - { /* if !a, we are reducing only */ - PreZeroW(i, w_out); - } - SET_DWORD(&w64[N_dwordlen], 0ULL); - SET_DWORD(&w64[N_dwordlen + 1U], 0ULL); - /* with accelerator */ - - /* loop i and then reduce after each j round */ - for (i = 0; i < N_dwordlen; i++) - { - /* Step 3. Iterate over N words of u using i - perform Multiply-accumulate */ - /* push-pull: we do a*b and then separately m*n (reduce) */ - if (a != NULL) - { /* if mul&reduce vs. reduce only */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(&b64[i]), CA_MK_OFF(a64)); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); - Accel_done(); - /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ - /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ - /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ - /* w64[N_dwordlen+1] = g_carry; */ - carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); - SET_DWORD(&w64[N_dwordlen + 1U], carry); - } - SET_DWORD(&m64[0], GET_DWORD(&w64[0]) * Np64); /* prime for 1st; modulo a double-word */ - - /* we are reducing, so the 1st [0th] 64 bit value product is tossed, but we */ - /* need its carry. We let the accel do this separately - really need a mode to */ - /* do this "reduce" since it is natural */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(m64), CA_MK_OFF(&N64[0])); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(&w64[0]))); - Accel_done(); - carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); - - Accel_SetABCD_Addr(CA_MK_OFF(&w64[1]), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpCopy, CA_MK_OFF(&w64[0]))); - - Accel_done(); - SET_DWORD(&w64[N_dwordlen], (GET_DWORD(&w64[N_dwordlen + 1U]) + carry)); - } - - /* now check if need to subtract Nmod */ - if (0U != (GET_WORD(&w_out[N_wordlen]))) - { - j = 1; /* we have to subtract for sure if carry up */ - } - else - { - j = 0; - for (i = N_wordlen - 1U; i > 0U; i--) - { - if (GET_WORD(&w_out[i]) != GET_WORD(&Nmod[i])) - { - j = (int32_t)(GET_WORD(&w_out[i]) > GET_WORD(&Nmod[i])); /* if larger sub */ - break; /* we would remove the break if worrying about side channel */ - } - } - } - if (0 == j) - { - return; /* Is smaller than Nmod, so done. */ - } - Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(w_out))); - Accel_done(); - /* last borrow is OK since we know it could only be <2N and */ -} - -/* RSA_MontSignatureToPlaintextFast: */ -/* MsgRet[] = Message return buffer - must be large enough to hold input and output (4*N+2) */ -/* exp_pubkey = the "e" that the value is raised to. Usually 3 or 0x10001. */ -/* signature = N bitpos len long "message" to process in Montgomery form - so saving conversion (divide) */ -/* pubkey = N bitpos len long public key to process signature with */ -/* returns: 0 */ -/* */ -/* Algo: compute M = signaturen^e mod public_key */ -/* where M is original plaintext, signature is signed value */ -/* note: e is usually either 0x3 or 0x10001 */ -int RSA_MontSignatureToPlaintextFast(const unsigned mont_signature[N_wordlen_max], - const unsigned exp_pubkey, - const unsigned pubkey[N_wordlen_max], - unsigned MsgRet[WORK_BUFF_MUL4]) -{ - int bidx = 0; - int bitpos; - unsigned np64[2]; - - /* MsgRet working area: */ - /* 0..N = RESULT, starting with S` */ - /* N..N*2 = S` and then working BASE during math. */ - /* N*2..N*4+2 = temp working area for Mont mul */ - - /* 1. Copy sig into MsgRet so we have one working result buffer */ - CASPER_MEMCPY_I2I((uint32_t *)(uintptr_t)&MsgRet[kCASPER_RamOffset_Result], - (const uint32_t *)(uintptr_t)mont_signature, N_bytelen); - MultprecGenNp64(pubkey, np64); /* Generate N` from LSW of N (LSW being lowest 64b word) */ - bitpos = (int8_t)(uint8_t)(31U - __CLZ(exp_pubkey)); /* count of bits after the left most 1 */ - while (--bitpos >= 0) - { - /* This operates on: */ - /* result = 1; */ - /* base = signature */ - /* loop while exponent bits from MSb to LSb */ - /* if (exp bit is 1) */ - /* result = result * base */ - /* base = base^2 */ - /* Because the MSb of exp is always 1 by definition, we can invert this a bit: */ - /* base = signature` */ - /* result = base; equivalent to result = 1*base from 1st pass, but now square is needed 1st */ - /* loop while exponent bits from MSb-1 to LSb */ - /* base = base^2 */ - /* if (exp bit is 1) */ - /* result = result * base */ - /* This ends up doing the same thing but skips two wasteful steps of multiplying by 1 and */ - /* a final squaring never used. */ - /* */ - /* Next we have the problem that CIOS mul needs a separate dest buffer. So, we bounce */ - /* base between base and temp, and likewise for result. */ - MultprecCiosMul(&MsgRet[(bidx != 0) ? kCASPER_RamOffset_Base : kCASPER_RamOffset_TempBase], - &MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], - &MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], pubkey, np64); - if (0U != (exp_pubkey & (uint32_t)(uint8_t)(1U << (uint8_t)bitpos))) /* where e is 1 */ - { - /* result has result, so we need to work into other temp area */ - MultprecCiosMul(&MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], - &MsgRet[kCASPER_RamOffset_Result], - &MsgRet[(bidx != 0) ? kCASPER_RamOffset_Base : kCASPER_RamOffset_TempBase], pubkey, np64); - /* we have to copy back to result */ - - // CASPER_MEMCPY_I2I(&MsgRet[kCASPER_RamOffset_Result], - // &MsgRet[bidx ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], N_bytelen); - } - else - { - bidx = (int32_t)(uint32_t) ~(unsigned)bidx; - } - } - - CASPER_MEMCPY_I2I((uint32_t *)(uintptr_t)&MsgRet[kCASPER_RamOffset_Result], - (uint32_t *)(uintptr_t)&MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], - N_bytelen); - - /* final step is one more reduction to get back to normal form (ie. divide R out) */ - MultprecCiosMul(&MsgRet[kCASPER_RamOffset_Result], NULL, NULL, pubkey, np64); - return (0); /* always 0 */ -} - -/* RSA_SignatureToPlaintextFast: */ -/* MsgRet[] = Message return buffer - must be large enough to hold input and output (4*N+2) */ -/* exp_pubkey = the "e" that the value is raised to. Usually 3 or 0x10001. */ -/* signature = N bitpos len long "message" to process in normal form - so converted to Mont form */ -/* pubkey = N bitpos len long public key to process signature with */ -/* returns: 0 */ -/* */ -/* Algo: compute M = signaturen^e mod public_key */ -/* where M is original plaintext, signature is signed value */ -/* note: e is usually either 0x3 or 0x10001 */ -int RSA_SignatureToPlaintextFast(const unsigned signature[N_wordlen_max], - const unsigned exp_pubkey, - const unsigned pubkey[N_wordlen_max], - unsigned MsgRet[WORK_BUFF_MUL4]) -{ - /* MsgRet working area: */ - /* 0..N = RESULT, starting with S`; it is used for R` just during creation of S` */ - /* N..N*2 = S` and then working BASE during math. Note overflow beyond N*2 when making S` */ - /* N*2..N*4+2 = temp working area for Mont mul */ - - MultprecMontCalcRp(&MsgRet[kCASPER_RamOffset_Result], exp_pubkey, pubkey); /* calculate R` (=R mod N) */ - MultprecMontPrepareX(&MsgRet[kCASPER_RamOffset_Base], signature, &MsgRet[kCASPER_RamOffset_Result], - pubkey); /* X*R1` mod N */ - return (RSA_MontSignatureToPlaintextFast(&MsgRet[kCASPER_RamOffset_Base], exp_pubkey, pubkey, MsgRet)); -} - -/*! - * brief Performs modular exponentiation - (A^E) mod N. - * - * This function performs modular exponentiation. - * - * param base CASPER base address - * param signature first addend (in little endian format) - * param pubN modulus (in little endian format) - * param wordLen Size of pubN in bytes - * param pubE exponent - * param[out] plaintext Output array to store result of operation (in little endian format) - */ -void CASPER_ModExp( - CASPER_Type *base, const uint8_t *signature, const uint8_t *pubN, size_t wordLen, uint32_t pubE, uint8_t *plaintext) -{ -#define PK_LOC &msg_ret[kCASPER_RamOffset_Modulus] -#define SIG_LOC &msg_ret[(unsigned)kCASPER_RamOffset_Modulus + N_wordlen_max] - - N_wordlen = wordLen; /* set global variable for key length - used by RSA_SignatureToPlaintextFast() */ - CASPER_MEMCPY_N2I(PK_LOC, (const uint32_t *)(uintptr_t)pubN, N_bytelen); - CASPER_MEMCPY_N2I(SIG_LOC, (const uint32_t *)(uintptr_t)signature, N_bytelen); - (void)RSA_SignatureToPlaintextFast((const unsigned *)(uintptr_t)(SIG_LOC), pubE, - (const unsigned *)(uintptr_t)(PK_LOC), (unsigned int *)(uintptr_t)msg_ret); - - CASPER_MEMCPY_I2N((uint32_t *)(uintptr_t)plaintext, msg_ret, N_bytelen); -} - -/*! - * brief Enables clock and disables reset for CASPER peripheral. - * - * Enable clock and disable reset for CASPER. - * - * param base CASPER base address - */ -void CASPER_Init(CASPER_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(CASPER_CLOCKS) - CLOCK_EnableClock(kCLOCK_Casper); -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if defined(CASPER_RSTS) - RESET_PeripheralReset(kCASPER_RST_SHIFT_RSTn); -#endif -#if defined(FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE) && (FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE > 0) - /* Enable hardware interleaving to RAMX0 and RAMX1 for CASPER */ - SYSCON->CASPER_CTRL = SYSCON_CASPER_CTRL_INTERLEAVE(1); -#endif /* FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE */ - /* If Casper init is called with secure address, use secure addres also for accessing Casper RAM. */ - s_casperRamBase = (unsigned)CASPER_RAM_BASE_NS | ((uint32_t)base & 0x10000000u); - msg_ret = (uint32_t *)s_casperRamBase; -} - -/*! - * brief Disables clock for CASPER peripheral. - * - * Disable clock and enable reset. - * - * param base CASPER base address - */ -void CASPER_Deinit(CASPER_Type *base) -{ -#if defined(CASPER_RSTS) - RESET_SetPeripheralReset(kCASPER_RST_SHIFT_RSTn); -#endif -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(CASPER_CLOCKS) - CLOCK_DisableClock(kCLOCK_Casper); -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/* New ECC code which uses Casper. */ - -/* Set the prime modulus mod in Casper memory. - */ -void CASPER_ecc_init(casper_algo_t curve) -{ - uint32_t *mod; - - if (curve == kCASPER_ECC_P256) - { - N_wordlen = 256U / 32U; - mod = NISTp256; - } - - if (curve == kCASPER_ECC_P384) - { - N_wordlen = 384U / 32U; - mod = NISTp384; - } - - if (curve == kCASPER_ECC_P521) - { - N_wordlen = 576U / 32U; - mod = NISTp521; - } - - CASPER_MEMCPY(&CASPER_MEM[(N_wordlen + 4U)], mod, N_wordlen * sizeof(uint32_t)); - uint8_t a[((CASPER_MAX_ECC_SIZE_WORDLEN + 4U) - CASPER_MAX_ECC_SIZE_WORDLEN) * sizeof(uint32_t)] = {0}; - CASPER_MEMCPY(&CASPER_MEM[(N_wordlen + 4U) + N_wordlen], a, ((N_wordlen + 4U) - N_wordlen) * sizeof(uint32_t)); -} - -void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2) -{ - uint32_t a[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; - uint32_t b[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; - uint32_t c = 0; - CASPER_MEMCPY(a, op1, N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(b, op2, N_wordlen * sizeof(uint32_t)); - - do - { - uint32_t _i; - c = (a[0] ^ b[0]); - for (_i = 1; _i < N_wordlen; _i++) - { - c |= (a[_i] ^ b[_i]); - } - } while (false); - - *res = (int32_t)c; -} - -void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1) -{ - uint32_t a[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; - uint32_t c = 0; - CASPER_MEMCPY(a, op1, N_wordlen * sizeof(uint32_t)); - - do - { - uint32_t _i; - c = a[0]; - for (_i = 1; _i < N_wordlen; _i++) - { - c |= a[_i]; - } - } while (false); - - *res = (int32_t)c; -} - -void CASPER_ECC_SECP256R1_Mul( - CASPER_Type *base, uint32_t resX[8], uint32_t resY[8], uint32_t X[8], uint32_t Y[8], uint32_t scalar[8]) -{ - uint32_t X1[8] = {0}; - uint32_t Y1[8] = {0}; - toMontgomery_ECC_P256(X1, X); - toMontgomery_ECC_P256(Y1, Y); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - - Jac_scalar_multiplication( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - scalar, NISTp256, NISTp256_q); - - Jac_toAffine( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - - /* Montgomery to Normal */ - /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ - uint32_t one[(kCASPER_ECC_P256_wordlen + 4U)] = {0x0}; - one[0] = 0x1u; - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - one, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - - /* copy out to result */ - CASPER_MEMCPY( - resX, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - resY, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP256R1_MulAdd(CASPER_Type *base, - uint32_t resX[8], - uint32_t resY[8], - uint32_t X1[8], - uint32_t Y1[8], - uint32_t scalar1[8], - uint32_t X2[8], - uint32_t Y2[8], - uint32_t scalar2[8]) -{ - uint32_t zeroes[(kCASPER_ECC_P256_wordlen + 4U)] = {0}; - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - X2, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - Y2, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - - toMontgomery_ECC_P256( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - toMontgomery_ECC_P256( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - toMontgomery_ECC_P256( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - toMontgomery_ECC_P256( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); - double_scalar_multiplication( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - scalar1, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - scalar2); - - Jac_toAffine( - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - - uint32_t one[(kCASPER_ECC_P256_wordlen + 4U)] = {0x0}; - one[0] = 0x1u; - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - one, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - - CASPER_MEMCPY(resX, - (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(resY, - (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP384R1_Mul( - CASPER_Type *base, uint32_t resX[12], uint32_t resY[12], uint32_t X[12], uint32_t Y[12], uint32_t scalar[12]) -{ - uint32_t X1[12] = {0}; - uint32_t Y1[12] = {0}; - toMontgomery_ECC_P384(X1, X); - toMontgomery_ECC_P384(Y1, Y); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - - Jac_scalar_multiplication( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - scalar, NISTp384, NISTp384_q); - - Jac_toAffine( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - - /* Montgomery to Normal */ - /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ - uint32_t one[12] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - one, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - - /* copy out to result */ - CASPER_MEMCPY( - resX, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - resY, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base, - uint32_t resX[12], - uint32_t resY[12], - uint32_t X1[12], - uint32_t Y1[12], - uint32_t scalar1[12], - uint32_t X2[12], - uint32_t Y2[12], - uint32_t scalar2[12]) -{ - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - X2, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - Y2, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - - toMontgomery_ECC_P384( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - toMontgomery_ECC_P384( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - toMontgomery_ECC_P384( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - toMontgomery_ECC_P384( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - - double_scalar_multiplication( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - scalar1, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - scalar2); - - Jac_toAffine( - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - - uint32_t one[12] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - one, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - - CASPER_MEMCPY(resX, - (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + - 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(resY, - (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + - 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP521R1_Mul( - CASPER_Type *base, uint32_t resX[18], uint32_t resY[18], uint32_t X[18], uint32_t Y[18], uint32_t scalar[18]) -{ - uint32_t X1[18] = {0}; - uint32_t Y1[18] = {0}; - toMontgomery_ECC_P521(X1, X); - toMontgomery_ECC_P521(Y1, Y); - - CASPER_MEMCPY( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - - Jac_scalar_multiplication( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 7U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 8U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - scalar, NISTp521, NISTp521_q); - - Jac_toAffine( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 7U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 8U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - - /* Montgomery to Normal */ - /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ - uint32_t one[18] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; - CASPER_MEMCPY( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - one, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - - /* copy out to result */ - CASPER_MEMCPY( - resX, - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - resY, - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP521R1_MulAdd(CASPER_Type *base, - uint32_t resX[18], - uint32_t resY[18], - uint32_t X1[18], - uint32_t Y1[18], - uint32_t scalar1[18], - uint32_t X2[18], - uint32_t Y2[18], - uint32_t scalar2[18]) -{ - uint32_t zeroes[(kCASPER_ECC_P521_wordlen + 4U)] = {0}; - - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - X2, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - Y2, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - - toMontgomery_ECC_P521( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - toMontgomery_ECC_P521( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - toMontgomery_ECC_P521( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - toMontgomery_ECC_P521( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); - double_scalar_multiplication( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - scalar1, - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - scalar2); - - Jac_toAffine( - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - - uint32_t one[(kCASPER_ECC_P521_wordlen + 4U)] = {0x0}; - one[0] = 0x1u; - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - one, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + - 2U * ((uint32_t)(uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - - CASPER_MEMCPY( - resX, - (&CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - resY, - (&CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); -} - -// CIOS Multiply. This is the Coarse Integrated form where the values are -// multiplied and reduced for each step of "i". This uses less memory and -// is faster as a result. Note that this is used to square as well as mul, -// so not as fast as pure squaring could be. -static void MultprecCiosMul_ct( - uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np) -{ - uint32_t j; - uint64_t *m64 = (uint64_t *)(uintptr_t)&msg_ret[kCASPER_RamOffset_M64]; - uint64_t Np64; - uint64_t carry; - uint64_t *a64, *b64, *w64, *N64; - uint32_t *T1 = &CASPER_MEM[0], borrow; - - Np64 = *(uint64_t *)(uintptr_t)Np; - - a64 = (uint64_t *)(uintptr_t)a; - b64 = (uint64_t *)(uintptr_t)b; - w64 = (uint64_t *)(uintptr_t)w_out; - N64 = (uint64_t *)(uintptr_t)Nmod; - - if (a != NULL) - { /* if !a, we are reducing only */ - PreZeroW(j, w_out); - } - SET_DWORD(&w64[N_dwordlen], 0ULL); - SET_DWORD(&w64[N_dwordlen + 1U], 0ULL); - /* with accelerator */ - - /* loop j and then reduce after each j round */ - for (j = 0; j < N_dwordlen; j++) - { - /* Step 3. Iterate over N words of u using j - perform Multiply-accumulate */ - /* push-pull: we do a*b and then separately m*n (reduce) */ - if (a != NULL) - { /* if mul&reduce vs. reduce only */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(&b64[j]), CA_MK_OFF(a64)); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); - Accel_done(); - /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ - /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ - /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ - /* w64[N_dwordlen+1] = g_carry; */ - carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); - SET_DWORD(&w64[N_dwordlen + 1U], carry); - } - SET_DWORD(&m64[0], GET_DWORD(&w64[0]) * Np64); /* prime for 1st; modulo a double-word */ - - /* we are reducing, so the 1st [0th] 64 bit value product is tossed, but we */ - /* need its carry. We let the accel do this separately - really need a mode to */ - /* do this "reduce" since it is natural */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(m64), CA_MK_OFF(&N64[0])); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(&w64[0]))); - Accel_done(); - carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); - - Accel_SetABCD_Addr(CA_MK_OFF(&w64[1]), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpCopy, CA_MK_OFF(&w64[0]))); - - Accel_done(); - SET_DWORD(&w64[N_dwordlen], (GET_DWORD(&w64[N_dwordlen + 1U]) + carry)); - } - - /* now check if need to subtract Nmod */ - CASPER_MEMCPY_I2I(T1, w_out, (N_wordlen + 1U) * sizeof(uint32_t)); - - /* Compute w = w - N */ - Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(w_out))); - Accel_done(); - - // if w_out > T1 then there was a borrow - borrow = (uint32_t)(GET_WORD(&((uint32_t *)w_out)[N_wordlen]) > GET_WORD(&T1[N_wordlen])); - - SET_WORD(&w_out[N_wordlen + 1U], 0); - SET_WORD(&w_out[N_wordlen], 0); - casper_select(w_out, w_out, T1, (int32_t)borrow, (int16_t)(uint16_t)N_wordlen); -} - -/* Compute C = A - B % mod - * Assumes all operand have two extra limbs to store carry. - */ -static void CASPER_montsub(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod) -{ - uint64_t *b64, *c64, *m64, *tmp; - int borrow; - - b64 = (uint64_t *)(uintptr_t)B; - c64 = (uint64_t *)(uintptr_t)C; - m64 = (uint64_t *)(uintptr_t)mod; - - tmp = (uint64_t *)(uintptr_t)&CASPER_MEM[0]; - - CASPER_MEMCPY(tmp, A, N_wordlen * sizeof(uint32_t)); - - /* Compute tmp = A - B. */ - Accel_SetABCD_Addr(CA_MK_OFF(b64), 0); - - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(tmp))); - Accel_done(); - - borrow = (int32_t)((GET_WORD(&((uint32_t *)(uintptr_t)tmp)[N_wordlen - 1U])) > GET_WORD(&A[N_wordlen - 1U])); - CASPER_MEMCPY(c64, tmp, N_wordlen * sizeof(uint32_t)); - - /* Compute C = Mod + tmp */ - Accel_SetABCD_Addr(CA_MK_OFF(m64), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpAdd64, CA_MK_OFF(c64))); - Accel_done(); - - casper_select(C, (uint32_t *)(uintptr_t)tmp, C, borrow, (int16_t)(uint16_t)N_wordlen); -} - -/* Compute C = A + B % mod - * Assumes all operand have two extra limbs to store carry. - */ -static void CASPER_montadd(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod) -{ - uint64_t *b64, *c64, *m64, *tmp; - int borrow; - - b64 = (uint64_t *)(uintptr_t)B; - c64 = (uint64_t *)(uintptr_t)C; - m64 = (uint64_t *)(uintptr_t)mod; - - tmp = (uint64_t *)(uintptr_t)&CASPER_MEM[0]; - - CASPER_MEMCPY(tmp, A, N_wordlen * sizeof(uint32_t)); - SET_DWORD(&tmp[N_wordlen / 2U], 0ULL); - SET_DWORD(&b64[N_wordlen / 2U], 0ULL); - SET_DWORD(&m64[N_wordlen / 2U], 0ULL); - - /* Compute tmp = A + B using one additonal double-length limb. */ - Accel_SetABCD_Addr(CA_MK_OFF(b64), 0); - - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U, (uint32_t)kCASPER_OpAdd64, CA_MK_OFF(tmp))); - Accel_done(); - - CASPER_MEMCPY(c64, tmp, (N_wordlen + 2U) * sizeof(uint32_t)); - - /* Compute C = Mod - tmp */ - Accel_SetABCD_Addr(CA_MK_OFF(m64), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(c64))); - Accel_done(); - - // borrow = g_carry; - borrow = (int32_t)(GET_WORD(&C[N_wordlen]) > GET_WORD(&(((uint32_t *)(uintptr_t)tmp)[N_wordlen]))); - casper_select(C, C, (uint32_t *)(uintptr_t)tmp, borrow, (int16_t)(uint16_t)N_wordlen); -} - -/* Compute c = a/2 mod p where b is scratch space. */ -static void CASPER_half(uint32_t *c, uint32_t *a, uint32_t *b) -{ - shiftright(b, a, 1U); /* Compute a/2 and (a+p)/2 */ - - /* Compute tmp = a + p using one additonal double-length limb. */ - CASPER_MEMCPY(c, a, N_wordlen * sizeof(uint32_t)); - SET_WORD(&c[N_wordlen], 0); - SET_WORD(&c[N_wordlen + 1U], 0U); - - Accel_SetABCD_Addr(CA_MK_OFF(((uint64_t *)(uintptr_t)&CASPER_MEM[(N_wordlen + 4U)])), 0); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_wordlen / 2U, (uint32_t)kCASPER_OpAdd64, CA_MK_OFF(((uint64_t *)(uintptr_t)c)))); - Accel_done(); - - shiftright(c, c, 1U); - SET_WORD(&c[N_wordlen - 1U], GET_WORD(&c[N_wordlen - 1U]) | (GET_WORD(&c[N_wordlen]) << 31)); - SET_WORD(&c[N_wordlen], 0U); - casper_select(c, b, c, (int32_t)(uint32_t)(GET_WORD(&a[0]) & 1U), (int16_t)(uint16_t)(N_wordlen)); -} - -static uint32_t casper_get_word(uint32_t *addr) -{ - return GET_WORD(addr); -} - -/* Shift right by 1 <= c <= 31. z[] and x[] in system RAM, no interleaving macros used. */ -static void shiftrightSysram(uint32_t *z, uint32_t *x, uint32_t c) -{ - z[0] = (x[1] << (32U - (c))) | (x[0] >> (c)); - z[1] = (x[2] << (32U - (c))) | (x[1] >> (c)); - z[2] = (x[3] << (32U - (c))) | (x[2] >> (c)); - z[3] = (x[4] << (32U - (c))) | (x[3] >> (c)); - z[4] = (x[5] << (32U - (c))) | (x[4] >> (c)); - z[5] = (x[6] << (32U - (c))) | (x[5] >> (c)); - z[6] = (x[7] << (32U - (c))) | (x[6] >> (c)); - - if (N_wordlen == 18U) - { - z[7] = (x[8] << (32U - (c))) | (x[7] >> (c)); - z[8] = (x[9] << (32U - (c))) | (x[8] >> (c)); - z[9] = (x[10] << (32U - (c))) | (x[9] >> (c)); - z[10] = (x[11] << (32U - (c))) | (x[10] >> (c)); - z[11] = (x[12] << (32U - (c))) | (x[11] >> (c)); - z[12] = (x[13] << (32U - (c))) | (x[12] >> (c)); - z[13] = (x[14] << (32U - (c))) | (x[13] >> (c)); - z[14] = (x[15] << (32U - (c))) | (x[14] >> (c)); - z[15] = (x[16] << (32U - (c))) | (x[15] >> (c)); - z[16] = (x[17] << (32U - (c))) | (x[16] >> (c)); - z[17] = (x[17] >> (c)); - } - - if (N_wordlen == 12U) - { - z[7] = (x[8] << (32U - (c))) | (x[7] >> (c)); - z[8] = (x[9] << (32U - (c))) | (x[8] >> (c)); - z[9] = (x[10] << (32U - (c))) | (x[9] >> (c)); - z[10] = (x[11] << (32U - (c))) | (x[10] >> (c)); - z[11] = (x[11] >> (c)); - } - if (N_wordlen == 8U) - { - z[7] = (x[7] >> (c)); - } -} -/* Shift right by 1 <= c <= 31. */ -static void shiftright(uint32_t *z, uint32_t *x, uint32_t c) -{ - SET_WORD(&z[0], (GET_WORD(&x[1]) << (32U - (c))) | (GET_WORD(&x[0]) >> (c))); - SET_WORD(&z[1], (GET_WORD(&x[2]) << (32U - (c))) | (GET_WORD(&x[1]) >> (c))); - SET_WORD(&z[2], (GET_WORD(&x[3]) << (32U - (c))) | (GET_WORD(&x[2]) >> (c))); - SET_WORD(&z[3], (GET_WORD(&x[4]) << (32U - (c))) | (GET_WORD(&x[3]) >> (c))); - SET_WORD(&z[4], (GET_WORD(&x[5]) << (32U - (c))) | (GET_WORD(&x[4]) >> (c))); - SET_WORD(&z[5], (GET_WORD(&x[6]) << (32U - (c))) | (GET_WORD(&x[5]) >> (c))); - SET_WORD(&z[6], (GET_WORD(&x[7]) << (32U - (c))) | (GET_WORD(&x[6]) >> (c))); - - if (N_wordlen == 18U) - { - SET_WORD(&z[7], (GET_WORD(&x[8]) << (32U - (c))) | (GET_WORD(&x[7]) >> (c))); - SET_WORD(&z[8], (GET_WORD(&x[9]) << (32U - (c))) | (GET_WORD(&x[8]) >> (c))); - SET_WORD(&z[9], (GET_WORD(&x[10]) << (32U - (c))) | (GET_WORD(&x[9]) >> (c))); - SET_WORD(&z[10], (GET_WORD(&x[11]) << (32U - (c))) | (GET_WORD(&x[10]) >> (c))); - SET_WORD(&z[11], (GET_WORD(&x[12]) << (32U - (c))) | (GET_WORD(&x[11]) >> (c))); - SET_WORD(&z[12], (GET_WORD(&x[13]) << (32U - (c))) | (GET_WORD(&x[12]) >> (c))); - SET_WORD(&z[13], (GET_WORD(&x[14]) << (32U - (c))) | (GET_WORD(&x[13]) >> (c))); - SET_WORD(&z[14], (GET_WORD(&x[15]) << (32U - (c))) | (GET_WORD(&x[14]) >> (c))); - SET_WORD(&z[15], (GET_WORD(&x[16]) << (32U - (c))) | (GET_WORD(&x[15]) >> (c))); - SET_WORD(&z[16], (GET_WORD(&x[17]) << (32U - (c))) | (GET_WORD(&x[16]) >> (c))); - SET_WORD(&z[17], (GET_WORD(&x[17]) >> (c))); - } - if (N_wordlen == 12U) - { - SET_WORD(&z[7], (GET_WORD(&x[8]) << (32U - (c))) | (GET_WORD(&x[7]) >> (c))); - SET_WORD(&z[8], (GET_WORD(&x[9]) << (32U - (c))) | (GET_WORD(&x[8]) >> (c))); - SET_WORD(&z[9], (GET_WORD(&x[10]) << (32U - (c))) | (GET_WORD(&x[9]) >> (c))); - SET_WORD(&z[10], (GET_WORD(&x[11]) << (32U - (c))) | (GET_WORD(&x[10]) >> (c))); - SET_WORD(&z[11], (GET_WORD(&x[11]) >> (c))); - } - if (N_wordlen == 8U) - { - SET_WORD((&z[7]), (GET_WORD(&x[7]) >> (c))); - } -} -/* Shift left by 1 <= c <= 31. */ -static void shiftleft(uint32_t *z, uint32_t *x, uint32_t c) -{ - if (N_wordlen == 18U) - { - SET_WORD(&z[17], (GET_WORD(&x[17]) << (c)) | GET_WORD(&z[16]) >> (32U - (c))); - SET_WORD(&z[16], (GET_WORD(&x[16]) << (c)) | GET_WORD(&z[15]) >> (32U - (c))); - SET_WORD(&z[15], (GET_WORD(&x[15]) << (c)) | GET_WORD(&z[14]) >> (32U - (c))); - SET_WORD(&z[14], (GET_WORD(&x[14]) << (c)) | GET_WORD(&z[13]) >> (32U - (c))); - SET_WORD(&z[13], (GET_WORD(&x[13]) << (c)) | GET_WORD(&z[12]) >> (32U - (c))); - SET_WORD(&z[12], (GET_WORD(&x[12]) << (c)) | GET_WORD(&z[11]) >> (32U - (c))); - SET_WORD(&z[11], (GET_WORD(&x[11]) << (c)) | GET_WORD(&z[10]) >> (32U - (c))); - SET_WORD(&z[10], (GET_WORD(&x[10]) << (c)) | GET_WORD(&z[9]) >> (32U - (c))); - SET_WORD(&z[9], (GET_WORD(&x[9]) << (c)) | GET_WORD(&z[8]) >> (32U - (c))); - SET_WORD(&z[8], (GET_WORD(&x[8]) << (c)) | GET_WORD(&z[7]) >> (32U - (c))); - } - if (N_wordlen == 12U) - { - SET_WORD(&z[11], (GET_WORD(&x[11]) << (c)) | GET_WORD(&z[10]) >> (32U - (c))); - SET_WORD(&z[10], (GET_WORD(&x[10]) << (c)) | GET_WORD(&z[9]) >> (32U - (c))); - SET_WORD(&z[9], (GET_WORD(&x[9]) << (c)) | GET_WORD(&z[8]) >> (32U - (c))); - SET_WORD(&z[8], (GET_WORD(&x[8]) << (c)) | GET_WORD(&z[7]) >> (32U - (c))); - } - SET_WORD(&z[7], (GET_WORD(&x[7]) << (c)) | GET_WORD(&z[6]) >> (32U - (c))); - SET_WORD(&z[6], (GET_WORD(&x[6]) << (c)) | GET_WORD(&z[5]) >> (32U - (c))); - SET_WORD(&z[5], (GET_WORD(&x[5]) << (c)) | GET_WORD(&z[4]) >> (32U - (c))); - SET_WORD(&z[4], (GET_WORD(&x[4]) << (c)) | GET_WORD(&z[3]) >> (32U - (c))); - SET_WORD(&z[3], (GET_WORD(&x[3]) << (c)) | GET_WORD(&z[2]) >> (32U - (c))); - SET_WORD(&z[2], (GET_WORD(&x[2]) << (c)) | GET_WORD(&z[1]) >> (32U - (c))); - SET_WORD(&z[1], (GET_WORD(&x[1]) << (c)) | GET_WORD(&z[0]) >> (32U - (c))); - SET_WORD(&z[0], (GET_WORD(&x[0]) << (c))); -} - -static void multiply_casper(uint32_t w_out[], const uint32_t a[], const uint32_t b[]) -{ - uint32_t *Np; - - if (N_wordlen == 8U) - { - Np = Np256; - MultprecCiosMul_ct(w_out, a, b, &CASPER_MEM[(N_wordlen + 4U)], Np); - } - if (N_wordlen == 12U) - { - Np = Np384; - MultprecCiosMul_ct(w_out, a, b, &CASPER_MEM[(N_wordlen + 4U)], Np); - } - - if (N_wordlen == 18U) - { - Np = Np521; - MultprecCiosMul521_ct(w_out, a, b, &CASPER_MEM[(N_wordlen + 4U)], Np); - } -} -/* Convert a projective point (X1 : Y1 : Z1) - * to the affine point (X3, Y3) = (X1/Z1^2,Y1/Z1^3) - * The memory of (X3, Y3) and (X1 : Y1 : Z1) should not overlap - */ -void Jac_toAffine(uint32_t *X3, uint32_t *Y3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1) -{ - uint32_t *T1, *T2; - - T1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; - T2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; - - square_casper(T1, Z1); // Z^2 - multiply_casper(T2, T1, Z1); // Z^3 - - // Montgomery inverse - if (N_wordlen == 8U) - { - invert_mod_p256(T1, T2); - } - - if (N_wordlen == 12U) - { - invert_mod_p384(T1, T2); - } - - if (N_wordlen == 18U) - { - invert_mod_p521(T1, T2); - } - - multiply_casper(Y3, Y1, T1); // Y3 = Y/Z^3 - multiply_casper(T2, T1, Z1); // Z^-2 - multiply_casper(X3, X1, T2); // X3 = X/Z^2 -} - -/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2 : Y2 : Z2) - * where (X1: Y1: Z1) != (X2 : Y2 : Z2) - * (X3 : Y3: Z3) may be the same as one of the inputs. - */ -void Jac_addition(uint32_t *X3, - uint32_t *Y3, - uint32_t *Z3, - uint32_t *X1, - uint32_t *Y1, - uint32_t *Z1, - uint32_t *X2, - uint32_t *Y2, - uint32_t *Z2) -{ - uint32_t *Z1Z1, *Z2Z2, *U1, *S1, *J, *H, *V, *t0, *t1; - int m1, m2; - - Z1Z1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; - Z2Z2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; - U1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 2U * (N_wordlen + 4U)]; - S1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 3U * (N_wordlen + 4U)]; - J = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 4U * (N_wordlen + 4U)]; - H = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 5U * (N_wordlen + 4U)]; - V = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 6U * (N_wordlen + 4U)]; - t0 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 7U * (N_wordlen + 4U)]; - t1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 8U * (N_wordlen + 4U)]; - - CASPER_ECC_equal_to_zero(&m1, Z1); - CASPER_ECC_equal_to_zero(&m2, Z2); - if (m1 == 0) - { - CASPER_MEMCPY(X3, X2, N_wordlen * 4U); - CASPER_MEMCPY(Y3, Y2, N_wordlen * 4U); - CASPER_MEMCPY(Z3, Z2, N_wordlen * 4U); - return; - } - if (m2 == 0) - { - CASPER_MEMCPY(X3, X1, N_wordlen * 4U); - CASPER_MEMCPY(Y3, Y1, N_wordlen * 4U); - CASPER_MEMCPY(Z3, Z1, N_wordlen * 4U); - return; - } - - square_casper(Z1Z1, Z1); - square_casper(Z2Z2, Z2); - multiply_casper(U1, X1, Z2Z2); - multiply_casper(H, X2, Z1Z1); /* if H equals U1 then X's are the same */ - multiply_casper(t0, Z2, Z2Z2); - multiply_casper(S1, Y1, t0); - multiply_casper(t0, Z1, Z1Z1); - multiply_casper(J, Y2, t0); /* if (S1 == J) then Y's are the same */ - - CASPER_ECC_equal(&m1, H, U1); /* If H and U1 match then the X-coordinates are the same. */ - CASPER_ECC_equal(&m2, S1, J); /* If S1 and J match then the Y-coordinates are the same. */ - if (m1 == 0) - { - if (m2 == 0) - { - Jac_double(X3, Y3, Z3, X1, Y1, Z1); - return; - } - /* else { - We work with the point at infinity. - The Z-coordinate will be set to zero in this function. - } */ - } - - sub_casper(H, H, U1); - mul2_casper(t0, H); - square_casper(t1, t0); - sub_casper(t0, J, S1); - multiply_casper(J, H, t1); - multiply_casper(V, U1, t1); - mul2_casper(U1, t0); - square_casper(t0, U1); - mul2_casper(t1, V); - sub_casper(t0, t0, J); - sub_casper(X3, t0, t1); - sub_casper(t0, V, X3); - multiply_casper(t1, S1, J); - mul2_casper(t1, t1); - multiply_casper(V, U1, t0); - sub_casper(Y3, V, t1); - add_casper(V, Z1, Z2); - square_casper(t1, V); - sub_casper(t1, t1, Z1Z1); - sub_casper(t1, t1, Z2Z2); - multiply_casper(Z3, t1, H); -} - -/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2, Y2) - * where (X1: Y1: Z1) != (X2, Y2) - * (X3 : Y3: Z3) may not overlap with (X1: Y1: Z1). - * Source: 2004 Hankerson?Menezes?Vanstone, page 91. - */ -void Jac_add_affine( - uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *X2, uint32_t *Y2) -{ - uint32_t *T1, *T2, *T3, *T4, *T5; - uint32_t *ONE = NULL; - int m1, m2; - - if (N_wordlen == 8U) - { - ONE = NISTr256; - } - if (N_wordlen == 12U) - { - ONE = NISTr384; - } - if (N_wordlen == 18U) - { - ONE = NISTr521; - } - - T1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; - T2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; - T3 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 2U * (N_wordlen + 4U)]; - T4 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 3U * (N_wordlen + 4U)]; - T5 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 4U * (N_wordlen + 4U)]; - - CASPER_ECC_equal_to_zero(&m1, Z1); - if (m1 == 0) - { - CASPER_MEMCPY(X3, X2, N_wordlen * 4U); - CASPER_MEMCPY(Y3, Y2, N_wordlen * 4U); - CASPER_MEMCPY(Z3, ONE, N_wordlen * 4U); - return; - } - - CASPER_MEMCPY(T5, Z1, N_wordlen * sizeof(uint32_t)); - square_casper(T3, Z1); - multiply_casper(T2, T3, Z1); - multiply_casper(T4, T3, X2); - multiply_casper(T3, T2, Y2); - - CASPER_ECC_equal(&m1, T4, X1); - CASPER_ECC_equal(&m2, T3, Y1); - if (m1 == 0) - { - if (m2 == 0) - { - Jac_double(X3, Y3, Z3, X1, Y1, Z1); - return; - } - /* else { - We work with the point at infinity. - The Z-coordinate will be set to zero in this function. - } */ - } - - sub_casper(T1, T4, X1); - sub_casper(T2, T3, Y1); - multiply_casper(Z3, T5, T1); - square_casper(T3, T1); - multiply_casper(T4, T3, T1); - multiply_casper(T5, T3, X1); - mul2_casper(T1, T5); - square_casper(X3, T2); - sub_casper(X3, X3, T1); - sub_casper(X3, X3, T4); - sub_casper(T3, T5, X3); - multiply_casper(T1, T3, T2); - multiply_casper(T2, T4, Y1); - sub_casper(Y3, T1, T2); -} - -static uint32_t casper_get_word(uint32_t *addr); - -/* Point doubling from: 2004 Hankerson?Menezes?Vanstone, page 91. - * Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X1 : Y1 : Z1) - * (X3 : Y3: Z3) may be the same as the input. - */ -void Jac_double(uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1) -{ - uint32_t *T1, *T2, *T3, *T4, *T5; - - T1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; - T2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; - T3 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 2U * (N_wordlen + 4U)]; - T4 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 3U * (N_wordlen + 4U)]; - T5 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 4U * (N_wordlen + 4U)]; - - square_casper(T1, Z1); - sub_casper(T3, X1, T1); - add_casper(T1, X1, T1); - multiply_casper(T4, T3, T1); - - mul2_casper(T3, T4); - - add_casper(T2, T3, T4); - - mul2_casper(Y3, Y1); - - CASPER_MEMCPY(T5, Z1, N_wordlen * sizeof(uint32_t)); - multiply_casper(Z3, Y3, T5); - - square_casper(T5, Y3); - - multiply_casper(T3, T5, X1); - - square_casper(Y3, T5); - - half(T5, Y3, T4); - - square_casper(X3, T2); - - mul2_casper(T1, T3); - - sub_casper(X3, X3, T1); - - sub_casper(T1, T3, X3); - - multiply_casper(T3, T1, T2); - - sub_casper(Y3, T3, T5); -} - -/* Recoding for a signed fixed window. - * Source: https://eprint.iacr.org/2014/130.pdf, Algorithm 6 - * Recode the n-bit integer k into ciel(log2(n)/(w-1)) digits - * where each digit is in - * { +/- 1, +/- 3, ..., +/- 2^(w-1)-1 } - * and put the result in c. - */ -static void recode(int8_t *c, uint32_t *k, int n, int w) -{ - int i, t; - uint32_t K[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; - (void)memcpy(K, k, (size_t)ceil(((double)n / 8.))); - t = (n + (w - 2)) / (w - 1); - for (i = 0; i < t; i++) - { - c[i] = (int8_t)(uint8_t)((K[0] & ((uint32_t)(uint32_t)(1UL << (uint32_t)w) - 1UL)) - - (uint32_t)(uint32_t)(1UL << ((uint32_t)w - 1UL))); - shiftrightSysram(K, K, (unsigned)w - 1U); - (void)add_n_1(K, K, (uint32_t)c[i] >> 31, (int16_t)(uint16_t)N_wordlen); - } - c[t] = (int8_t)K[0]; -} - -static uint32_t sub_n(uint32_t *c, uint32_t *a, uint32_t *b, int n) -{ - int i; - uint32_t borrow; - sub_borrowout(borrow, GET_WORD(&c[0]), a[0], GET_WORD(&b[0])); - for (i = 1; i < n; i++) - { - sub_borrowin_borrowout(borrow, GET_WORD(&c[i]), a[i], GET_WORD(&b[i]), borrow); - } - return borrow; -} - -#if 0 -/* Dumb n-limb subtraction of c=a-b, return borrow. */ -static uint32_t sub_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n) { - int i; - uint32_t borrow; - sub_borrowout(borrow, c[0], a[0], b); - for (i = 1; i < n; i++) { - sub_borrowin_borrowout_1(borrow, c[i], a[i], borrow); - } - return borrow; -} - -/* Dumb n-limb addition of c=a+b, return carry. */ -static uint32_t add_n(uint32_t *c, uint32_t *a, uint32_t *b, int n) { - int i; - uint32_t carry; - add_cout(carry, c[0], a[0], b[0]); - for (i = 1; i < n; i++) { - add_cout_cin(carry, c[i], a[i], b[i], carry); - } - return carry; -} -#endif - -/* Dumb n-limb addition of c=a+b, return carry. */ -static uint32_t add_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n) -{ - int i; - uint32_t carry; - add_cout(carry, c[0], a[0], b); - for (i = 1; i < n; i++) - { - add_cout_cin(carry, c[i], a[i], 0U, carry); - } - return carry; -} - -static uint8_t int8abs(int8_t v) -{ - return ((v < 0) ? ((uint8_t)-v) : ((uint8_t)v)); -} - -/* Constant time elliptic curve scalar multiplication. - * Source: https://eprint.iacr.org/2014/130.pdf - * when using w = 4. - * Computes (X3 : Y3 : Z3) = k * (X1, Y1) \in E(F_p) - * p is the prime used to define the finite field F_p - * q is the (prime) order of the curve - */ -void Jac_scalar_multiplication( - uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *k, uint32_t *p, uint32_t *q) -{ - uint32_t *scalar, *M, *X, *Y, *Z, *mem; - uint32_t *ONE = NULL; - int i, sign, odd; - uint8_t index; - size_t recodeLength = 175u; - size_t bitlen = 0u; - int8_t rec[CASPER_RECODE_LENGTH_MAX] = {0}; - - if (N_wordlen == 8U) - { - recodeLength = (size_t)kCASPER_ECC_P256_recode_len; - bitlen = (size_t)kCASPER_ECC_P256_N_bitlen; - ONE = NISTr256; - } - - if (N_wordlen == 12U) - { - recodeLength = (size_t)kCASPER_ECC_P384_recode_len; - bitlen = (size_t)kCASPER_ECC_P384_N_bitlen; - ONE = NISTr384; - } - - if (N_wordlen == 18U) - { - recodeLength = (size_t)kCASPER_ECC_P521_recode_len; - bitlen = (size_t)521U; - ONE = NISTr521; - } - - /* Point to the start of the LUT table space. */ - mem = &CASPER_MEM[(20U * N_wordlen + 80U)]; - - scalar = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * (N_wordlen + 4U)]; - X = &CASPER_MEM[(20U * N_wordlen + 80U) + 13U * (N_wordlen + 4U)]; - Y = &CASPER_MEM[(20U * N_wordlen + 80U) + 14U * (N_wordlen + 4U)]; - Z = &CASPER_MEM[(20U * N_wordlen + 80U) + 15U * (N_wordlen + 4U)]; - M = &CASPER_MEM[(20U * N_wordlen + 80U) + 16U * (N_wordlen + 4U)]; - - /* Point to memory the recoded scalar. - */ - CASPER_MEMCPY(scalar, k, sizeof(uint32_t) * N_wordlen); - -/* Precomputation: compute 1*P, 3*P, 5*P, and 7*P */ -#define FSL_CASPER_LUT(P, x) (mem + (3U * ((P)-1U) / 2U + (x)) * (N_wordlen + 4U)) - - /* Set 1*P */ - CASPER_MEMCPY(Z3, ONE, N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(FSL_CASPER_LUT(1U, 0U), X1, N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(FSL_CASPER_LUT(1U, 1U), Y1, N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(FSL_CASPER_LUT(1U, 2U), Z3, N_wordlen * sizeof(uint32_t)); - - /* Compute 2*P */ - Jac_double(X3, Y3, Z3, X1, Y1, Z3); - - /* Compute 3*P = 2P + P */ - Jac_add_affine(FSL_CASPER_LUT(3U, 0U), FSL_CASPER_LUT(3U, 1U), FSL_CASPER_LUT(3U, 2U), X3, Y3, Z3, X1, Y1); - - /* Compute 5*P = 3P + 2P */ - Jac_addition(FSL_CASPER_LUT(5U, 0U), FSL_CASPER_LUT(5U, 1U), FSL_CASPER_LUT(5U, 2U), FSL_CASPER_LUT(3U, 0U), - FSL_CASPER_LUT(3U, 1U), FSL_CASPER_LUT(3U, 2U), X3, Y3, Z3); - - /* Compute 7*P = 5P + 2P */ - Jac_addition(FSL_CASPER_LUT(7U, 0U), FSL_CASPER_LUT(7U, 1U), FSL_CASPER_LUT(7U, 2U), FSL_CASPER_LUT(5U, 0U), - FSL_CASPER_LUT(5U, 1U), FSL_CASPER_LUT(5U, 2U), X3, Y3, Z3); - - /* Recode the scalar */ - odd = (int32_t)((uint32_t)(casper_get_word(&scalar[0]) & 1U)); - (void)sub_n(M, q, scalar, (int16_t)(uint16_t)N_wordlen); // todo!!! - casper_select(scalar, M, scalar, odd, (int16_t)(uint16_t)N_wordlen); - - /* Use n=384 and w=4 --> compute ciel(384/3) = 128 + 1 digits */ - uint32_t scalarSysram[CASPER_MAX_ECC_SIZE_WORDLEN]; - CASPER_MEMCPY(scalarSysram, scalar, /*CASPER_*/ N_wordlen * sizeof(uint32_t)); - recode(rec, scalarSysram, (int32_t)bitlen, 4); - - /* Set the first value. */ - index = int8abs(rec[recodeLength - 1U]); - sign = (int32_t)(uint32_t)(uint8_t)(((uint8_t)rec[recodeLength - 1U]) >> 7); - - CASPER_MEMCPY(X3, FSL_CASPER_LUT((uint32_t)index, 0U), N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Y3, FSL_CASPER_LUT((uint32_t)index, 1U), N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Z3, FSL_CASPER_LUT((uint32_t)index, 2U), N_wordlen * sizeof(uint32_t)); - - /* Get the correct LUT element in constant time by touching - * all elements and masking out the correct one. - */ - -#define GET_LUT(x, y, z, index) \ - do \ - { \ - int m; \ - CASPER_MEMCPY((x), FSL_CASPER_LUT(1U, 0U), N_wordlen * sizeof(uint32_t)); \ - CASPER_MEMCPY((y), FSL_CASPER_LUT(1U, 1U), N_wordlen * sizeof(uint32_t)); \ - CASPER_MEMCPY((z), FSL_CASPER_LUT(1U, 2U), N_wordlen * sizeof(uint32_t)); \ - m = (int32_t)((index) == 3U); \ - casper_select((x), (x), FSL_CASPER_LUT(3U, 0U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((y), (y), FSL_CASPER_LUT(3U, 1U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((z), (z), FSL_CASPER_LUT(3U, 2U), m, (int16_t)(uint16_t)N_wordlen); \ - m = (int32_t)((index) == 5U); \ - casper_select((x), (x), FSL_CASPER_LUT(5U, 0U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((y), (y), FSL_CASPER_LUT(5U, 1U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((z), (z), FSL_CASPER_LUT(5U, 2U), m, (int16_t)(uint16_t)N_wordlen); \ - m = (int32_t)((index) == 7U); \ - casper_select((x), (x), FSL_CASPER_LUT(7U, 0U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((y), (y), FSL_CASPER_LUT(7U, 1U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((z), (z), FSL_CASPER_LUT(7U, 2U), m, (int16_t)(uint16_t)N_wordlen); \ - } while (false) - - GET_LUT(X3, Y3, Z3, index); - - /* Compute -y and select the positive or negative point. */ - (void)sub_n(M, p, Y3, (int16_t)(uint16_t)N_wordlen); // todo!!! - casper_select(Y3, Y3, M, sign, (int16_t)(uint16_t)N_wordlen); - - for (i = (int)(uint32_t)(recodeLength - 2U); i >= 0; i--) - { - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - - index = int8abs(rec[i]); - sign = (int32_t)(uint32_t)(uint8_t)(((uint8_t)rec[i]) >> 7); - - GET_LUT(X, Y, Z, index); - - /* Compute -y and select the positive or negative point. */ - (void)sub_n(scalar, p, Y, (int16_t)(uint16_t)N_wordlen); // todo!!! - casper_select(scalar, Y, scalar, sign, (int16_t)(uint16_t)N_wordlen); - - Jac_addition(X3, Y3, Z3, X3, Y3, Z3, X, scalar, Z); - } - - (void)sub_n(M, p, Y3, (int16_t)(uint16_t)N_wordlen); // todo!!! - - casper_select(Y3, M, Y3, odd, (int16_t)(uint16_t)N_wordlen); -} - -#undef FSL_CASPER_LUT -#undef GET_LUT - -/* - * Pre-compute the following 16 points: - * 00 00 = 0*P + 0*Q <-- Not needed when using sliding windows - * 00 01 = 0*P + 1*Q <-- Not needed when using sliding windows - * 00 10 = 0*P + 2*Q - * 00 11 = 0*P + 3*Q - * - * 01 00 = 1*P + 0*Q <-- Not needed when using sliding windows - * 01 01 = 1*P + 1*Q <-- Not needed when using sliding windows - * 01 10 = 1*P + 2*Q - * 01 11 = 1*P + 3*Q - * - * 10 00 = 2*P + 0*Q - * 10 01 = 2*P + 1*Q - * 10 10 = 2*P + 2*Q - * 10 11 = 2*P + 3*Q - * - * 11 00 = 3*P + 0*Q - * 11 01 = 3*P + 1*Q - * 11 10 = 3*P + 2*Q - * 11 11 = 3*P + 3*Q - * - * index = (bitsi||bitsj)-2 - (biti != 0)*2 - * - * Input: P = (X1 : Y1 : Z1) and - * Q = (X2 : Y2 : Z2) - * Output: mem, memory location for the LUT. - */ - -static void precompute_double_scalar_LUT16(uint32_t *Px, uint32_t *Py, uint32_t *Qx, uint32_t *Qy) -{ - uint32_t *Q2x, *Q2y, *Q2z, *P2x, *P2y, *P2z, *Z, *mem; - uint32_t *ONE = NULL; - uint32_t index = 0; - - if (N_wordlen == 8U) - { - ONE = NISTr256; - } - - if (N_wordlen == 12U) - { - ONE = NISTr384; - } - - Q2x = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 0U * (N_wordlen + 4U)]; - Q2y = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 1U * (N_wordlen + 4U)]; - Q2z = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 2U * (N_wordlen + 4U)]; - - /* Re-use memory from different scratch space since no - * projective point addition is used below. */ - P2x = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 5U * (N_wordlen + 4U)]; - P2z = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 6U * (N_wordlen + 4U)]; - P2y = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 7U * (N_wordlen + 4U)]; - Z = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 8U * (N_wordlen + 4U)]; - - mem = &CASPER_MEM[(20U * N_wordlen + 80U)]; - - CASPER_MEMCPY(Z, ONE, N_wordlen * sizeof(uint32_t)); - - // 00 10 = 0*P + 2*Q - Jac_double(Q2x, Q2y, Q2z, Qx, Qy, Z); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 00 11 = 0*P + 3*Q - Jac_add_affine(P2x, P2y, P2z, Q2x, Q2y, Q2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 01 10 = 1*P + 2*Q - Jac_add_affine(P2x, P2y, P2z, Q2x, Q2y, Q2z, Px, Py); - CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 01 11 = 1*P + 3*Q - Jac_add_affine(P2x, P2y, P2z, P2x, P2y, P2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 10 00 = 2*P + 0*Q - Jac_double(P2x, P2y, P2z, Px, Py, Z); - CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 10 01 = 2*P + 1*Q - Jac_add_affine(Q2x, Q2y, Q2z, P2x, P2y, P2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 10 10 = 2*P + 2*Q - Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 10 11 = 2*P + 3*Q - Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 11 00 = 3*P + 0*Q - Jac_add_affine(P2x, P2y, P2z, P2x, P2y, P2z, Px, Py); - CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 11 01 = 3*P + 1*Q - Jac_add_affine(Q2x, Q2y, Q2z, P2x, P2y, P2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 11 10 = 3*P + 2*Q - Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 11 11 = 3*P + 3*Q - Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; -} - -/* - * Pre-compute the following 4 points: - * 0 0 = 0*P + 0*Q <-- Not needed when using sliding windows - * 0 1 = 0*P + 1*Q - * - * 1 0 = 1*P + 0*Q - * 1 1 = 1*P + 1*Q - * - * index = (bitsj+1) & (0-bitsi) - * - * Input: P = (X1 : Y1 : Z1) and - * Q = (X2 : Y2 : Z2) - * Output: mem, memory location for the LUT. - */ - -static void precompute_double_scalar_LUT4(uint32_t *Px, uint32_t *Py, uint32_t *Qx, uint32_t *Qy) -{ - uint32_t *Z, *mem, *ONE; - uint32_t index = 0; - - ONE = NISTr521; - - /* Re-use memory from different scratch space since no - * projective point addition is used below. */ - Z = &CASPER_MEM[(11U * N_wordlen + 4U) + 5U * (N_wordlen + 4U)]; - mem = &CASPER_MEM[(20U * N_wordlen + 80U)]; - - CASPER_MEMCPY(Z, ONE, N_wordlen * sizeof(uint32_t)); - - // 0*P + 1*Q - CASPER_MEMCPY(&mem[index], Qx, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Qy, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 1*P + 0*Q - CASPER_MEMCPY(&mem[index], Px, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Py, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 1*P + 1*Q - Jac_add_affine(&mem[index], &mem[index + N_wordlen], &mem[index + 2U * N_wordlen], Px, Py, Z, Qx, Qy); -} - -#define GETLUTX(x) (3U * (x)*N_wordlen) -#define GETLUTY(x) (3U * (x)*N_wordlen + 1U * N_wordlen) -#define GETLUTZ(x) (3U * (x)*N_wordlen + 2U * N_wordlen) - -/* Compute the double scalar multiplication - * (X3 : Y3 : Z3) = k1 * (X1, Y1) + k2 * (X2, Y2) - * Using Shamir's trick and precomputing 16 points. - * This code is *not* constant time since this is used - * for verification only. - */ -void double_scalar_multiplication(uint32_t *X3, - uint32_t *Y3, - uint32_t *Z3, - uint32_t *X1, - uint32_t *Y1, - uint32_t *k1, - uint32_t *X2, - uint32_t *Y2, - uint32_t *k2) -{ - uint32_t index = 0, c = 0; - uint32_t *p1 = NULL, *p2 = NULL, x1, x2, *lut, *Tx = NULL, *Ty = NULL, *Tz = NULL; - size_t bitlen, shiftr, shiftl = 0u; - - if (N_wordlen == 8U) - { - bitlen = (size_t)kCASPER_ECC_P256_N_bitlen; - precompute_double_scalar_LUT16(X1, Y1, X2, Y2); - shiftr = 30U; - shiftl = 2U; - } - - if (N_wordlen == 12U) - { - bitlen = (size_t)kCASPER_ECC_P384_N_bitlen; - precompute_double_scalar_LUT16(X1, Y1, X2, Y2); - shiftr = 30U; - shiftl = 2U; - } - - if (N_wordlen == 18U) - { - bitlen = (size_t)kCASPER_ECC_P521_N_bitlen; - precompute_double_scalar_LUT4(X1, Y1, X2, Y2); - shiftr = 31U; - shiftl = 1U; - } - - lut = &CASPER_MEM[(20U * N_wordlen + 80U)]; - - if (N_wordlen == 8U || N_wordlen == 12U) - { - p1 = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen]; - p2 = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 1U * (N_wordlen + 4U)]; - - Tx = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 2U * (N_wordlen + 4U)]; - Ty = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 3U * (N_wordlen + 4U)]; - Tz = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 4U * (N_wordlen + 4U)]; - } - - if (N_wordlen == 18U) - { - p1 = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen]; - p2 = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 1U * (N_wordlen + 4U)]; - - Tx = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 2U * (N_wordlen + 4U)]; - Ty = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 3U * (N_wordlen + 4U)]; - Tz = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 4U * (N_wordlen + 4U)]; - } - - CASPER_MEMCPY(p1, k1, sizeof(uint32_t) * N_wordlen); - CASPER_MEMCPY(p2, k2, sizeof(uint32_t) * N_wordlen); - - /* Check if we can slide. */ - while (((casper_get_word(&p1[N_wordlen - 1U]) | casper_get_word(&p2[N_wordlen - 1U])) >> 31) == 0U && c < bitlen) - { - shiftleft(p1, p1, 1U); - shiftleft(p2, p2, 1U); - c++; - /* No doubling needed. */ - } - - /* Set the first value. */ - x1 = casper_get_word(&p1[N_wordlen - 1U]) >> shiftr; - x2 = casper_get_word(&p2[N_wordlen - 1U]) >> shiftr; - if (N_wordlen == 8U || N_wordlen == 12U) - { - index = (x2 | (x1 << 2)) - 2U - (uint32_t)(x1 != 0U) * 2U; - } - - if (N_wordlen == 18U) - { - index = (((x2) + 1U) & (0U - (x1))); - } - shiftleft(p1, p1, shiftl); - shiftleft(p2, p2, shiftl); - - CASPER_MEMCPY(X3, &lut[GETLUTX(index)], N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Y3, &lut[GETLUTY(index)], N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Z3, &lut[GETLUTZ(index)], N_wordlen * sizeof(uint32_t)); - c += shiftl; - - // todo: create an is_zero function - - while ((casper_get_word(&p1[0]) | casper_get_word(&p1[1]) | casper_get_word(&p1[2]) | casper_get_word(&p1[3]) | - casper_get_word(&p1[4]) | casper_get_word(&p1[5]) | casper_get_word(&p1[6]) | casper_get_word(&p1[7]) | - casper_get_word(&p1[8]) | casper_get_word(&p1[9]) | casper_get_word(&p1[10]) | casper_get_word(&p1[11]) | - casper_get_word(&p1[12]) | casper_get_word(&p1[13]) | casper_get_word(&p1[14]) | casper_get_word(&p1[15]) | - casper_get_word(&p1[16]) | casper_get_word(&p1[17]) | casper_get_word(&p2[0]) | casper_get_word(&p2[1]) | - casper_get_word(&p2[2]) | casper_get_word(&p2[3]) | casper_get_word(&p2[4]) | casper_get_word(&p2[5]) | - casper_get_word(&p2[6]) | casper_get_word(&p2[7]) | casper_get_word(&p2[8]) | casper_get_word(&p2[9]) | - casper_get_word(&p2[10]) | casper_get_word(&p2[11]) | casper_get_word(&p2[12]) | casper_get_word(&p2[13]) | - casper_get_word(&p2[14]) | casper_get_word(&p2[15]) | casper_get_word(&p2[16]) | - casper_get_word(&p2[17])) != 0U) - { - /* Check if we can slide. */ - while (((casper_get_word(&p1[N_wordlen - 1U]) | casper_get_word(&p2[N_wordlen - 1U])) >> 31) == 0U && - c < bitlen) - { - shiftleft(p1, p1, 1U); - shiftleft(p2, p2, 1U); - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - c++; - } - - if (c >= (bitlen - 1U)) - { - break; - } - - for (uint32_t i = 0; i < shiftl; i++) - { - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - } - - x1 = casper_get_word(&p1[N_wordlen - 1U]) >> shiftr; - x2 = casper_get_word(&p2[N_wordlen - 1U]) >> shiftr; - - if (N_wordlen == 8U || N_wordlen == 12U) - { - index = (x2 | (x1 << 2)) - 2U - (uint32_t)(x1 != 0U) * 2U; - } - - if (N_wordlen == 18U) - { - index = (((x2) + 1U) & (0U - (x1))); - } - - shiftleft(p1, p1, shiftl); - shiftleft(p2, p2, shiftl); - - CASPER_MEMCPY(Tx, &lut[GETLUTX(index)], N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Ty, &lut[GETLUTY(index)], N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Tz, &lut[GETLUTZ(index)], N_wordlen * sizeof(uint32_t)); - - Jac_addition(X3, Y3, Z3, X3, Y3, Z3, Tx, Ty, - Tz); //&lut[GETLUTX(index)], &lut[GETLUTY(index)], &lut[GETLUTZ(index)]); - c += shiftl; - } - - /* Special case in the end. */ - if (c == (bitlen - 1U)) - { - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - x1 = casper_get_word(&p1[N_wordlen - 1U]) >> 31; - x2 = casper_get_word(&p2[N_wordlen - 1U]) >> 31; - if (0U != x1) - { - Jac_add_affine(X3, Y3, Z3, X3, Y3, Z3, X1, Y1); - } - if (x2 != 0U) - { - Jac_add_affine(X3, Y3, Z3, X3, Y3, Z3, X2, Y2); - } - c++; - } - - while (c < bitlen) - { - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - c++; - } -} - -static void invert_mod_p256(uint32_t *c, uint32_t *a) -{ - int i; - uint32_t *t, *t2, *s1, *s2, *s4, *s8, *tmp; - - /* Assuming it is safe to use the ECC scratch size. */ - t = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - t2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - s1 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - s2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - s4 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - s8 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 7U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - tmp = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 8U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - - // t2 = n^(2^1)*n # 11 - square_casper(tmp, a); - multiply_casper(t2, tmp, a); - - // s1 = t2^(2^2)*t2 # F - square_casper(s1, t2); - square_casper(tmp, s1); - multiply_casper(s1, tmp, t2); - - // s2 = s1^(2^4)*s1 # FF - square_casper(s2, s1); - // for (i = 1; i < 4; i++) square(s2, s2); - square_casper(tmp, s2); - square_casper(s2, tmp); - square_casper(tmp, s2); - multiply_casper(s2, tmp, s1); - - // s4 = s2^(2^8)*s2 # FFFF - square_casper(s4, s2); - for (i = 1; i < 7; i += 2) - { - square_casper(tmp, s4); - square_casper(s4, tmp); - } - square_casper(tmp, s4); - multiply_casper(s4, tmp, s2); - - // s8 = s4^(2^16)*s4 # FFFFFFFF - square_casper(s8, s4); - for (i = 1; i < 15; i += 2) - { - square_casper(tmp, s8); - square_casper(s8, tmp); - } - square_casper(tmp, s8); - multiply_casper(s8, tmp, s4); - - // t = s8^(2^32)*n # ffffffff00000001 - square_casper(tmp, s8); - for (i = 1; i < 31; i += 2) - { - square_casper(t, tmp); - square_casper(tmp, t); - } - square_casper(t, tmp); - multiply_casper(tmp, t, a); - - // t = t^(2^128)*s8 # ffffffff00000001000000000000000000000000ffffffff - for (i = 0; i < 128; i += 2) - { - square_casper(t, tmp); - square_casper(tmp, t); - } - multiply_casper(t, tmp, s8); - - // t = t^(2^32)*s8 # ffffffff00000001000000000000000000000000ffffffffffffffff - for (i = 0; i < 32; i += 2) - { - square_casper(tmp, t); - square_casper(t, tmp); - } - multiply_casper(tmp, t, s8); - - // t = t^(2^16)*s4 # ffffffff00000001000000000000000000000000ffffffffffffffffffff - for (i = 0; i < 16; i += 2) - { - square_casper(t, tmp); - square_casper(tmp, t); - } - multiply_casper(t, tmp, s4); - - // t = t^(2^8)*s2 # ffffffff00000001000000000000000000000000ffffffffffffffffffffff - for (i = 0; i < 8; i += 2) - { - square_casper(tmp, t); - square_casper(t, tmp); - } - multiply_casper(tmp, t, s2); - - // t = t^(2^4)*s1 # ffffffff00000001000000000000000000000000fffffffffffffffffffffff - for (i = 0; i < 4; i += 2) - { - square_casper(t, tmp); - square_casper(tmp, t); - } - multiply_casper(t, tmp, s1); - - // t = t^(2^2)*t2 - square_casper(tmp, t); - square_casper(t, tmp); - multiply_casper(tmp, t, t2); - - // t = t^(2^2)*n # ffffffff00000001000000000000000000000000fffffffffffffffffffffffd - square_casper(t, tmp); - square_casper(tmp, t); - multiply_casper(c, tmp, a); -} - -// A and C do not need to be in Casper memory -static void toMontgomery_ECC_P256(uint32_t *C, uint32_t *A) -{ - /* R^2 = 2^512 mod p, used to convert values to Montgomery form. */ - uint32_t R2[kCASPER_ECC_P256_wordlen] = {0x00000003, 0x00000000, 0xffffffffU, 0xfffffffbU, - 0xfffffffeU, 0xffffffffU, 0xfffffffdU, 0x4}; - uint32_t *T1, *T2, *T3; - T1 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - T2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - T3 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - - CASPER_MEMCPY(T1, R2, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(T2, A, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - - multiply_casper(T3, T2, T1); - CASPER_MEMCPY(C, T3, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); -} - -/* Compute inversion modulo NIST-p384 using Fermats little theorem. - * Using c = a^(p-2) = a^(-1) mod p. - * This computes the modular inversion if all arithmetic is "regular" - * modular arithmetic or computes automatically the Montgomery inverse - * if all arithmetic is Montgomery arithmetic. - */ - -static void invert_mod_p384(uint32_t *c, uint32_t *a) -{ - int i; - uint32_t *e, *d, *tmp, *t0, *t1, *t2, *t3, *t4, *t5, *t6; // 10 residues needed - - /* Assuming it is safe to use the LUT scratch size. - * Hence, do not invert while elements in the LUT are needed. - */ - e = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - d = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - tmp = - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t0 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t1 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t4 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 7U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t5 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 8U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t6 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - - square_casper(tmp, a); // 2 - square_casper(t1, tmp); // 4 - square_casper(tmp, t1); // 8 - multiply_casper(t2, tmp, t1); // 12 - multiply_casper(d, a, t2); // 13 - multiply_casper(e, d, a); // 14 - multiply_casper(t0, e, a); // 15 - - // t1 = t0^(2^4)*t0 # ff - square_casper(tmp, t0); - square_casper(t1, tmp); - square_casper(tmp, t1); - square_casper(t2, tmp); - multiply_casper(t1, t2, t0); - - // t2 = t1^(2^8)*t1 # 4f - square_casper(tmp, t1); - for (i = 0; i < 3; i++) - { - square_casper(t3, tmp); - square_casper(tmp, t3); - } - square_casper(t3, tmp); - multiply_casper(t2, t3, t1); - - // t3 = t2^(2^16)*t2 # 8f - square_casper(tmp, t2); - for (i = 0; i < 7; i++) - { - square_casper(t4, tmp); - square_casper(tmp, t4); - } - square_casper(t4, tmp); - multiply_casper(t3, t4, t2); - - // t4 = t3^(2^32)*t3 # 16f - square_casper(tmp, t3); - for (i = 0; i < 15; i++) - { - square_casper(t5, tmp); - square_casper(tmp, t5); - } - square_casper(t5, tmp); - multiply_casper(t4, t5, t3); - - // t5 = t4^(2^64)*t4 # 32f - square_casper(tmp, t4); - for (i = 0; i < 31; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t4); - - // t5 = t5^(2^64)*t4 # 48f - square_casper(tmp, t5); - for (i = 0; i < 31; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t4); - - // t5 = t5^(2^32)*t3 # 56f - square_casper(tmp, t5); - for (i = 0; i < 15; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t3); - - // t5 = t5^(2^16)*t2 # 60f - square_casper(tmp, t5); - for (i = 0; i < 7; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t2); - - // t5 = t5^(2^8)*t1 # 62f - square_casper(tmp, t5); - for (i = 0; i < 3; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t1); - - // n = t5^(2^4)*t0 # 63f - square_casper(tmp, t5); - for (i = 0; i < 1; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t0); - - // n = n^(2^4)*e - square_casper(tmp, t5); - for (i = 0; i < 1; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, e); - - // n = n^(2^32)*t3 - square_casper(tmp, t5); - for (i = 0; i < 15; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t3); - - // n = n^(2^64) - square_casper(tmp, t5); - for (i = 0; i < 31; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t5, tmp); - - // n = n^(2^16)*t2 - square_casper(tmp, t5); - for (i = 0; i < 7; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t2); - - // n = n^(2^8)*t1 - square_casper(tmp, t5); - for (i = 0; i < 3; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t1); - - // n = n^(2^4)*t0 - square_casper(tmp, t5); - for (i = 0; i < 1; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t0); - - // n = n^(2^4)*d - square_casper(tmp, t5); - for (i = 0; i < 1; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(c, t6, d); -} - -// A and C do not need to be in Casper memory -static void toMontgomery_ECC_P384(uint32_t *C, uint32_t *A) -{ - /* R^2 = 2^768 mod p, used to convert values to Montgomery form. */ - uint32_t R2[kCASPER_ECC_P384_wordlen] = {0x00000001, 0xfffffffeU, 0x00000000, 0x00000002, 0x00000000, 0xfffffffeU, - 0x00000000, 0x00000002, 0x1, 0x0, 0x0, 0x0}; - uint32_t *T1, *T2, *T3; - T1 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - T2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U))) + - 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - T3 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U))) + - 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - - CASPER_MEMCPY(T1, R2, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(T2, A, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - - multiply_casper(T3, T2, T1); - CASPER_MEMCPY(C, T3, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); -} - -static void invert_mod_p521(uint32_t *c, uint32_t *a) -{ - int i; - uint32_t *e3, *d2, *d3, *d4, *T2, *T4; // 6 residues needed - - /* Assuming it is safe to use the LUT scratch size. - * Hence, do not invert while elements in the LUT are needed. - */ - e3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - d2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - d3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - d4 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - T2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - T4 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - - square_casper(d2, a); - multiply_casper(T2, d2, a); - - // d3 = 2^2 * T2 - square_casper(d3, T2); - square_casper(e3, d3); - multiply_casper(T4, e3, T2); - - // d3 = 2^4 * T4 - square_casper(d3, T4); - square_casper(e3, d3); - square_casper(d3, e3); - square_casper(e3, d3); - multiply_casper(d2, e3, T4); - - // d3 = 2^8 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - for (i = 0; i < 3; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d4, e3, d2); - - // d3 = 2^16 * d2 - square_casper(d3, d4); - square_casper(e3, d3); - for (i = 0; i < 7; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d2, e3, d4); - - // d3 = 2^32 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - for (i = 0; i < 15; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d4, e3, d2); - - // d3 = 2^64 * d2 - square_casper(d3, d4); - square_casper(e3, d3); - for (i = 0; i < 31; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d2, e3, d4); - - // d3 = 2^128 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - for (i = 0; i < 63; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d4, e3, d2); - - // d3 = 2^256 * d2 - square_casper(d3, d4); - square_casper(e3, d3); - for (i = 0; i < 127; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d2, e3, d4); - - // d3 = 2^2 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - multiply_casper(d2, e3, T2); - - // d3 = 2^4 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - square_casper(d3, e3); - square_casper(e3, d3); - multiply_casper(d2, e3, T4); - - square_casper(d3, d2); - multiply_casper(d2, d3, a); - - // d3 = 2 ^ 2 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - multiply_casper(c, e3, a); -} - -static void toMontgomery_ECC_P521(uint32_t *C, uint32_t *A) -{ - /* R^2 = 2^1088 mod p, used to convert values to Montgomery form. */ - // uint32_t R2[NUM_LIMBS] = { 0x00000000, 0x4000, 0, 0, - // 0, 0, 0, 0, - // 0, 0, 0, 0, - // 0 }; - /* R^2 = 2^1152 mod p, used to convert values to Montgomery form. */ - uint32_t R2[kCASPER_ECC_P521_wordlen] = {0, 0, 0, 0x4000, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - - uint32_t *T1, *T2, *T3; - T1 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - T2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - T3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - - CASPER_MEMCPY(T1, R2, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(T2, A, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - - multiply_casper(T3, T2, T1); - CASPER_MEMCPY(C, T3, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); -} - -static void MultprecCiosMul521_ct( - uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np) -{ - uint32_t j; - uint64_t carry; - uint64_t *a64, *b64, *w64; - - uint32_t *T1 = &CASPER_MEM[0], borrow; - - a64 = (uint64_t *)(uintptr_t)a; - b64 = (uint64_t *)(uintptr_t)b; - w64 = (uint64_t *)(uintptr_t)w_out; - - if (a != NULL) - { /* if !a, we are reducing only */ - PreZeroW(j, w_out); - } - SET_DWORD(&w64[N_dwordlen], 0ULL); - SET_DWORD(&w64[N_dwordlen + 1U], 0ULL); - /* with accelerator */ - - /* loop j and then reduce after each j round */ - for (j = 0; j < N_dwordlen; j++) - { - /* Step 3. Iterate over N words of u using j - perform Multiply-accumulate */ - /* push-pull: we do a*b and then separately m*n (reduce) */ - if (a != NULL) - { /* if mul&reduce vs. reduce only */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(&b64[j]), CA_MK_OFF(a64)); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); - Accel_done(); - /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ - /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ - /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ - /* w64[N_dwordlen+1] = g_carry; */ - carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); - SET_DWORD(&w64[N_dwordlen + 1U], carry); - } - - /* Fast reduction using only shifts for this special shape: - * (c - (-p^-1*c mod 2^64) * p)/2^64 = - * (c - c_0 * p)/2^64 = - * (\sum_{j=0}^9 c_i*2^64 - c_0 * p)/2^64 = - * (\sum_{j=0}^9 c_i*2^64 - c_0 * (2^521-1))/2^64 = - * (\sum_{j=0}^9 c_i*2^64 - c_0 * 2^521 - c_0)/2^64 = - * c_1 + c_2*2^64 + c_3*2^128 + c_4*2^192 + c_5*2^256 + c_6*2^320 + c_7*2^384 + c_8*2^448 + c_9*2^512 + c_0 * - * 2^{448 + 9} so one only needs to compute this 128-bit addition: [c_8, c_9] + c_0 * 2^9 - */ - - uint64_t *p64 = (uint64_t *)(uintptr_t)T1; - - /* p64[0] = w64[0] << 9;*/ - SET_DWORD(&p64[0], GET_DWORD(&w64[0]) << 9U); - /* p64[1] = w64[0] >> (64 - 9); */ - SET_DWORD(&p64[1], GET_DWORD(&w64[0]) >> (64 - 9)); - /* w64[0] = w64[1]; */ - SET_DWORD(&w64[0], GET_DWORD(&w64[1])); - /* w64[1] = w64[2]; */ - SET_DWORD(&w64[1], GET_DWORD(&w64[2])); - /* w64[2] = w64[3]; */ - SET_DWORD(&w64[2], GET_DWORD(&w64[3])); - /* w64[3] = w64[4]; */ - SET_DWORD(&w64[3], GET_DWORD(&w64[4])); - /* w64[4] = w64[5]; */ - SET_DWORD(&w64[4], GET_DWORD(&w64[5])); - /* w64[5] = w64[6]; */ - SET_DWORD(&w64[5], GET_DWORD(&w64[6])); - /* w64[6] = w64[7]; */ - SET_DWORD(&w64[6], GET_DWORD(&w64[7])); - - /* Compute p64 = p64 + {w64[8], w64[9]} using one additonal double-length limb, - * where p64 = w64[0] * 2^9. - */ - Accel_SetABCD_Addr(CA_MK_OFF(&w64[8]), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(2, (uint32_t)kCASPER_OpAdd64, /* kCASPER_OpAdd64, */ - CA_MK_OFF(p64))); - Accel_done(); - - /* w64[7] = p64[0]; */ - SET_DWORD(&w64[7], GET_DWORD(&p64[0])); - /* w64[8] = p64[1]; */ - SET_DWORD(&w64[8], GET_DWORD(&p64[1])); - /* w64[9] = 0; */ - SET_DWORD(&w64[9], (uint64_t)0U); - } - - /* memcpy(T1, w_out, (NUM_LIMBS + 1) * sizeof(uint32_t)); */ - /* now check if need to subtract Nmod */ - CASPER_MEMCPY_I2I(T1, w_out, (N_wordlen + 1U) * sizeof(uint32_t)); - - /* Compute w = w - N */ - Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(w_out))); - Accel_done(); - - /* if w_out > T1 then there was a borrow */ - /* borrow = (((uint32_t*)w_out)[NUM_LIMBS] > T1[NUM_LIMBS]); */ - borrow = (uint32_t)(GET_WORD(&((uint32_t *)w_out)[N_wordlen]) > GET_WORD(&T1[N_wordlen])); - SET_WORD(&w_out[N_wordlen + 1U], 0); - SET_WORD(&w_out[N_wordlen], 0); - /* w_out[NUM_LIMBS + 1] = 0; */ - /* w_out[NUM_LIMBS] = 0; */ - casper_select(w_out, w_out, T1, (int32_t)borrow, (int32_t)N_wordlen); -} - -#if defined(__GNUC__) -/* End of enforcing O1 optimize level for gcc*/ -#pragma GCC pop_options -#endif - -#if (defined(__CC_ARM) || defined(__ARMCC_VERSION)) -// End of enforcing optimize off for clang -#pragma clang optimize on -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_casper.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_casper.h deleted file mode 100644 index 328dc101116..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_casper.h +++ /dev/null @@ -1,386 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CASPER_H_ -#define _FSL_CASPER_H_ - -#include "fsl_common.h" - -/*! @file */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! - * @addtogroup casper_driver - * @{ - */ -/*! @name Driver version */ -/*@{*/ -/*! @brief CASPER driver version. Version 2.2.3. - * - * Current version: 2.2.3 - * - * Change log: - * - Version 2.0.0 - * - Initial version - * - Version 2.0.1 - * - Bug fix KPSDK-24531 double_scalar_multiplication() result may be all zeroes for some specific input - * - Version 2.0.2 - * - Bug fix KPSDK-25015 CASPER_MEMCPY hard-fault on LPC55xx when both source and destination buffers are outside of - * CASPER_RAM - * - Version 2.0.3 - * - Bug fix KPSDK-28107 RSUB, FILL and ZERO operations not implemented in enum _casper_operation. - * - Version 2.0.4 - * - For GCC compiler, enforce O1 optimize level, specifically to remove strict-aliasing option. - * This driver is very specific and requires -fno-strict-aliasing. - * - Version 2.0.5 - * - Fix sign-compare warning. - * - Version 2.0.6 - * - Fix IAR Pa082 warning. - * - Version 2.0.7 - * - Fix MISRA-C 2012 issue. - * - Version 2.0.8 - * - Add feature macro for CASPER_RAM_OFFSET. - * - Version 2.0.9 - * - Remove unused function Jac_oncurve(). - * - Fix ECC384 build. - * - Version 2.0.10 - * - Fix MISRA-C 2012 issue. - * - Version 2.1.0 - * - Add ECC NIST P-521 elliptic curve. - * - Version 2.2.0 - * - Rework driver to support multiple curves at once. - * - Version 2.2.1 - * - Fix MISRA-C 2012 issue. - * - Version 2.2.2 - * - Enable hardware interleaving to RAMX0 and RAMX1 for CASPER by feature macro FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE - * - Version 2.2.3 - * - Added macro into CASPER_Init and CASPER_Deinit to support devices without clock and reset control. - */ -#define FSL_CASPER_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) -/*@}*/ - -/*! @brief CASPER operation - * - */ -typedef enum _casper_operation -{ - kCASPER_OpMul6464NoSum = 0x01, /*! Walking 1 or more of J loop, doing r=a*b using 64x64=128*/ - kCASPER_OpMul6464Sum = - 0x02, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but assume inner j loop*/ - kCASPER_OpMul6464FullSum = - 0x03, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but sum all of w. */ - kCASPER_OpMul6464Reduce = - 0x04, /*! Walking 1 or more of J loop, doing c,r[-1]=r+a*b using 64x64=128, but skip 1st write*/ - kCASPER_OpAdd64 = 0x08, /*! Walking add with off_AB, and in/out off_RES doing c,r=r+a+c using 64+64=65*/ - kCASPER_OpSub64 = 0x09, /*! Walking subtract with off_AB, and in/out off_RES doing r=r-a using 64-64=64, with last - borrow implicit if any*/ - kCASPER_OpDouble64 = 0x0A, /*! Walking add to self with off_RES doing c,r=r+r+c using 64+64=65*/ - kCASPER_OpXor64 = 0x0B, /*! Walking XOR with off_AB, and in/out off_RES doing r=r^a using 64^64=64*/ - kCASPER_OpRSub64 = 0x0C, /*! Walking subtract with off_AB, and in/out off_RES using r=a-r */ - kCASPER_OpShiftLeft32 = - 0x10, /*! Walking shift left doing r1,r=(b*D)|r1, where D is 2^amt and is loaded by app (off_CD not used)*/ - kCASPER_OpShiftRight32 = 0x11, /*! Walking shift right doing r,r1=(b*D)|r1, where D is 2^(32-amt) and is loaded by - app (off_CD not used) and off_RES starts at MSW*/ - kCASPER_OpCopy = 0x14, /*! Copy from ABoff to resoff, 64b at a time*/ - kCASPER_OpRemask = 0x15, /*! Copy and mask from ABoff to resoff, 64b at a time*/ - kCASPER_OpFill = 0x16, /*! Fill RESOFF using 64 bits at a time with value in A and B */ - kCASPER_OpZero = 0x17, /*! Fill RESOFF using 64 bits at a time of 0s */ - kCASPER_OpCompare = 0x18, /*! Compare two arrays, running all the way to the end*/ - kCASPER_OpCompareFast = 0x19, /*! Compare two arrays, stopping on 1st !=*/ -} casper_operation_t; - -/*! @brief Algorithm used for CASPER operation */ -typedef enum _casper_algo_t -{ - kCASPER_ECC_P256 = 0x01, /*!< ECC_P256*/ - kCASPER_ECC_P384 = 0x02, /*!< ECC_P384 */ - kCASPER_ECC_P521 = 0x03, /*!< ECC_P521 */ -} casper_algo_t; - -#define CASPER_CP 1 -#define CASPER_CP_CTRL0 (0x0 >> 2) -#define CASPER_CP_CTRL1 (0x4 >> 2) -#define CASPER_CP_LOADER (0x8 >> 2) -#define CASPER_CP_STATUS (0xC >> 2) -#define CASPER_CP_INTENSET (0x10 >> 2) -#define CASPER_CP_INTENCLR (0x14 >> 2) -#define CASPER_CP_INTSTAT (0x18 >> 2) -#define CASPER_CP_AREG (0x20 >> 2) -#define CASPER_CP_BREG (0x24 >> 2) -#define CASPER_CP_CREG (0x28 >> 2) -#define CASPER_CP_DREG (0x2C >> 2) -#define CASPER_CP_RES0 (0x30 >> 2) -#define CASPER_CP_RES1 (0x34 >> 2) -#define CASPER_CP_RES2 (0x38 >> 2) -#define CASPER_CP_RES3 (0x3C >> 2) -#define CASPER_CP_MASK (0x60 >> 2) -#define CASPER_CP_REMASK (0x64 >> 2) -#define CASPER_CP_LOCK (0x80 >> 2) -#define CASPER_CP_ID (0xFFC >> 2) -/* mcr (cp, opc1, value, CRn, CRm, opc2) */ -#define CASPER_Wr32b(value, off) __arm_mcr(CASPER_CP, 0, value, ((off >> 4)), (off), 0) -/* mcrr(coproc, opc1, value, CRm) */ -#define CASPER_Wr64b(value, off) __arm_mcrr(CASPER_CP, 0, value, off) -/* mrc(coproc, opc1, CRn, CRm, opc2) */ -#define CASPER_Rd32b(off) __arm_mrc(CASPER_CP, 0, ((off >> 4)), (off), 0) - -/* The model for this algo is that it can be implemented for a fixed size RSA key */ -/* for max speed. If this is made into a variable (to allow varying size), then */ -/* it will be slower by a bit. */ -/* The file is compiled with N_bitlen passed in as number of bits of the RSA key */ -/* #define N_bitlen 2048 */ -#define N_wordlen_max (4096U / 32U) - -enum -{ - kCASPER_RamOffset_Result = 0x0u, - kCASPER_RamOffset_Base = (N_wordlen_max + 8u), - kCASPER_RamOffset_TempBase = (2u * N_wordlen_max + 16u), - kCASPER_RamOffset_Modulus = (kCASPER_RamOffset_TempBase + N_wordlen_max + 4u), - kCASPER_RamOffset_M64 = 1022U, -}; - -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup casper_driver - * @{ - */ - -/*! - * @brief Enables clock and disables reset for CASPER peripheral. - * - * Enable clock and disable reset for CASPER. - * - * @param base CASPER base address - */ -void CASPER_Init(CASPER_Type *base); - -/*! - * @brief Disables clock for CASPER peripheral. - * - * Disable clock and enable reset. - * - * @param base CASPER base address - */ -void CASPER_Deinit(CASPER_Type *base); - -/*! - *@} - */ /* end of casper_driver */ - -/******************************************************************************* - * PKHA API - ******************************************************************************/ - -/*! - * @addtogroup casper_driver_pkha - * @{ - */ - -/*! - * @brief Performs modular exponentiation - (A^E) mod N. - * - * This function performs modular exponentiation. - * - * @param base CASPER base address - * @param signature first addend (in little endian format) - * @param pubN modulus (in little endian format) - * @param wordLen Size of pubN in bytes - * @param pubE exponent - * @param[out] plaintext Output array to store result of operation (in little endian format) - */ -void CASPER_ModExp(CASPER_Type *base, - const uint8_t *signature, - const uint8_t *pubN, - size_t wordLen, - uint32_t pubE, - uint8_t *plaintext); - -/*! - * @brief Initialize prime modulus mod in Casper memory . - * - * Set the prime modulus mod in Casper memory and set N_wordlen - * according to selected algorithm. - * - * @param curve elliptic curve algoritm - */ -void CASPER_ecc_init(casper_algo_t curve); - -/*! - * @brief Performs ECC secp256r1 point single scalar multiplication - * - * This function performs ECC secp256r1 point single scalar multiplication - * [resX; resY] = scalar * [X; Y] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate in normal form, little endian. - * @param[out] resY Output Y affine coordinate in normal form, little endian. - * @param X Input X affine coordinate in normal form, little endian. - * @param Y Input Y affine coordinate in normal form, little endian. - * @param scalar Input scalar integer, in normal form, little endian. - */ -void CASPER_ECC_SECP256R1_Mul( - CASPER_Type *base, uint32_t resX[8], uint32_t resY[8], uint32_t X[8], uint32_t Y[8], uint32_t scalar[8]); - -/*! - * @brief Performs ECC secp256r1 point double scalar multiplication - * - * This function performs ECC secp256r1 point double scalar multiplication - * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate. - * @param[out] resY Output Y affine coordinate. - * @param X1 Input X1 affine coordinate. - * @param Y1 Input Y1 affine coordinate. - * @param scalar1 Input scalar1 integer. - * @param X2 Input X2 affine coordinate. - * @param Y2 Input Y2 affine coordinate. - * @param scalar2 Input scalar2 integer. - */ -void CASPER_ECC_SECP256R1_MulAdd(CASPER_Type *base, - uint32_t resX[8], - uint32_t resY[8], - uint32_t X1[8], - uint32_t Y1[8], - uint32_t scalar1[8], - uint32_t X2[8], - uint32_t Y2[8], - uint32_t scalar2[8]); - -/*! - * @brief Performs ECC secp384r1 point single scalar multiplication - * - * This function performs ECC secp384r1 point single scalar multiplication - * [resX; resY] = scalar * [X; Y] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate in normal form, little endian. - * @param[out] resY Output Y affine coordinate in normal form, little endian. - * @param X Input X affine coordinate in normal form, little endian. - * @param Y Input Y affine coordinate in normal form, little endian. - * @param scalar Input scalar integer, in normal form, little endian. - */ -void CASPER_ECC_SECP384R1_Mul( - CASPER_Type *base, uint32_t resX[12], uint32_t resY[12], uint32_t X[12], uint32_t Y[12], uint32_t scalar[12]); - -/*! - * @brief Performs ECC secp384r1 point double scalar multiplication - * - * This function performs ECC secp384r1 point double scalar multiplication - * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate. - * @param[out] resY Output Y affine coordinate. - * @param X1 Input X1 affine coordinate. - * @param Y1 Input Y1 affine coordinate. - * @param scalar1 Input scalar1 integer. - * @param X2 Input X2 affine coordinate. - * @param Y2 Input Y2 affine coordinate. - * @param scalar2 Input scalar2 integer. - */ -void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base, - uint32_t resX[12], - uint32_t resY[12], - uint32_t X1[12], - uint32_t Y1[12], - uint32_t scalar1[12], - uint32_t X2[12], - uint32_t Y2[12], - uint32_t scalar2[12]); - -/*! - * @brief Performs ECC secp521r1 point single scalar multiplication - * - * This function performs ECC secp521r1 point single scalar multiplication - * [resX; resY] = scalar * [X; Y] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate in normal form, little endian. - * @param[out] resY Output Y affine coordinate in normal form, little endian. - * @param X Input X affine coordinate in normal form, little endian. - * @param Y Input Y affine coordinate in normal form, little endian. - * @param scalar Input scalar integer, in normal form, little endian. - */ -void CASPER_ECC_SECP521R1_Mul( - CASPER_Type *base, uint32_t resX[18], uint32_t resY[18], uint32_t X[18], uint32_t Y[18], uint32_t scalar[18]); - -/*! - * @brief Performs ECC secp521r1 point double scalar multiplication - * - * This function performs ECC secp521r1 point double scalar multiplication - * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate. - * @param[out] resY Output Y affine coordinate. - * @param X1 Input X1 affine coordinate. - * @param Y1 Input Y1 affine coordinate. - * @param scalar1 Input scalar1 integer. - * @param X2 Input X2 affine coordinate. - * @param Y2 Input Y2 affine coordinate. - * @param scalar2 Input scalar2 integer. - */ -void CASPER_ECC_SECP521R1_MulAdd(CASPER_Type *base, - uint32_t resX[18], - uint32_t resY[18], - uint32_t X1[18], - uint32_t Y1[18], - uint32_t scalar1[18], - uint32_t X2[18], - uint32_t Y2[18], - uint32_t scalar2[18]); - -void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2); -void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1); - -/*! - *@} - */ /* end of casper_driver_pkha */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_CASPER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_cdog.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_cdog.c deleted file mode 100644 index 9b985e1cbd2..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_cdog.c +++ /dev/null @@ -1,314 +0,0 @@ -/* - * Copyright 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_cdog.h" - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.cdog" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Sets the default configuration of CDOG - * - * This function initialize CDOG config structure to default values. - * - * param conf CDOG configuration structure - */ -void CDOG_GetDefaultConfig(cdog_config_t *conf) -{ - /* Default configuration after reset */ - conf->lock = (uint8_t)kCDOG_LockCtrl_Unlock; /* Lock control */ - conf->timeout = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Timeout control */ - conf->miscompare = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Miscompare control */ - conf->sequence = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Sequence control */ - conf->state = (uint8_t)kCDOG_FaultCtrl_NoAction; /* State control */ - conf->address = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Address control */ - conf->irq_pause = (uint8_t)kCDOG_IrqPauseCtrl_Run; /* IRQ pause control */ - conf->debug_halt = (uint8_t)kCDOG_DebugHaltCtrl_Run; /* Debug halt control */ - return; -} - -/*! - * brief Sets secure counter and instruction timer values - * - * This function sets value in RELOAD and START registers for instruction timer. - * - * param base CDOG peripheral base address - * param reload reload value - * param start start value - */ -void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start) -{ - base->RELOAD = reload; - base->START = start; -} - -/*! - * brief Stops secure counter and instruction timer - * - * This function stops instruction timer and secure counter. - * This also change state of CDOG to IDLE. - * - * param base CDOG peripheral base address - * param stop expected value which will be compared with value of secure counter - */ -void CDOG_Stop(CDOG_Type *base, uint32_t stop) -{ - base->STOP = stop; -} - -/*! - * brief Sets secure counter and instruction timer values - * - * This function sets value in STOP, RELOAD and START registers - * for instruction timer and secure counter. - * - * param base CDOG peripheral base address - * param stop expected value which will be compared with value of secure counter - * param reload reload value for instruction timer - * param start start value for secure timer - */ -void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start) -{ - base->STOP = stop; - base->RELOAD = reload; - base->START = start; -} - -/*! - * brief Add value to secure counter - * - * This function add specified value to secure counter. - * - * param base CDOG peripheral base address. - * param add Value to be added. - */ -void CDOG_Add(CDOG_Type *base, uint32_t add) -{ - base->ADD = (secure_counter_t)add; -} - -/*! - * brief Add 1 to secure counter - * - * This function add 1 to secure counter. - * - * param base CDOG peripheral base address. - * param add Value to be added. - */ -void CDOG_Add1(CDOG_Type *base) -{ - base->ADD1 = (secure_counter_t)0x1U; -} - -/*! - * brief Add 16 to secure counter - * - * This function add 16 to secure counter. - * - * param base CDOG peripheral base address. - * param add Value to be added. - */ -void CDOG_Add16(CDOG_Type *base) -{ - base->ADD16 = (secure_counter_t)0x1U; -} - -/*! - * brief Add 256 to secure counter - * - * This function add 256 to secure counter. - * - * param base CDOG peripheral base address. - * param add Value to be added. - */ -void CDOG_Add256(CDOG_Type *base) -{ - base->ADD256 = (secure_counter_t)0x1U; -} - -/*! - * brief Substract value to secure counter - * - * This function substract specified value to secure counter. - * - * param base CDOG peripheral base address. - * param sub Value to be substracted. - */ -void CDOG_Sub(CDOG_Type *base, uint32_t sub) -{ - base->SUB = (secure_counter_t)sub; -} - -/*! - * brief Substract 1 from secure counter - * - * This function substract specified 1 from secure counter. - * - * param base CDOG peripheral base address. - */ -void CDOG_Sub1(CDOG_Type *base) -{ - base->SUB1 = (secure_counter_t)0x1U; -} - -/*! - * brief Substract 16 from secure counter - * - * This function substract specified 16 from secure counter. - * - * param base CDOG peripheral base address. - */ -void CDOG_Sub16(CDOG_Type *base) -{ - base->SUB16 = (secure_counter_t)0x1U; -} - -/*! - * brief Substract 256 from secure counter - * - * This function substract specified 256 from secure counter. - * - * param base CDOG peripheral base address. - */ -void CDOG_Sub256(CDOG_Type *base) -{ - base->SUB256 = (secure_counter_t)0x1U; -} - -/*! - * brief Checks secure counter. - * - * This function compares stop value with secure counter value - * by writting to RELOAD refister. - * - * param base CDOG peripheral base address - * param check expected (stop) value. - */ -void CDOG_Check(CDOG_Type *base, uint32_t check) -{ - base->RESTART = check; -} - -/*! - * brief Set the CDOG persistent word. - * - * param base CDOG peripheral base address. - * param value The value to be written. - */ -void CDOG_WritePersistent(CDOG_Type *base, uint32_t value) -{ - base->PERSISTENT = value; -} - -/*! - * brief Get the CDOG persistent word. - * - * param base CDOG peripheral base address. - * return The persistent word. - */ -uint32_t CDOG_ReadPersistent(CDOG_Type *base) -{ - return base->PERSISTENT; -} - -/*! - * brief Initialize CDOG - * - * This function initializes CDOG block and setting. - * - * param base CDOG peripheral base address - * param conf CDOG configuration structure - * return Status of the init operation - */ -status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf) -{ - /* Ungate clock to CDOG engine and reset it */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#ifdef CDOG_CLOCKS - CLOCK_EnableClock(kCLOCK_Cdog); -#endif /* CDOG_CLOCKS */ -#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET) - RESET_PeripheralReset(kCDOG_RST_SHIFT_RSTn); -#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */ - - if (base->CONTROL == 0x0U) - { - /* CDOG is not in IDLE mode, which may be cause after SW reset. */ - /* Writing to CONTROL register will trigger fault. */ - return kStatus_Fail; - } - - /* Clear pending errors, otherwise the device will reset */ - /* itself immediately after enable Code Watchdog */ - if ((uint32_t)kCDOG_LockCtrl_Lock == - ((base->CONTROL & CDOG_CONTROL_LOCK_CTRL_MASK) >> CDOG_CONTROL_LOCK_CTRL_SHIFT)) - - { - CDOG->FLAGS = CDOG_FLAGS_TO_FLAG(1U) | CDOG_FLAGS_MISCOM_FLAG(1U) | CDOG_FLAGS_SEQ_FLAG(1U) | - CDOG_FLAGS_CNT_FLAG(1U) | CDOG_FLAGS_STATE_FLAG(1U) | CDOG_FLAGS_ADDR_FLAG(1U) | - CDOG_FLAGS_POR_FLAG(1U); - } - else - { - CDOG->FLAGS = CDOG_FLAGS_TO_FLAG(0U) | CDOG_FLAGS_MISCOM_FLAG(0U) | CDOG_FLAGS_SEQ_FLAG(0U) | - CDOG_FLAGS_CNT_FLAG(0U) | CDOG_FLAGS_STATE_FLAG(0U) | CDOG_FLAGS_ADDR_FLAG(0U) | - CDOG_FLAGS_POR_FLAG(0U); - } - - base->CONTROL = - CDOG_CONTROL_TIMEOUT_CTRL(conf->timeout) | /* Action if the timeout event is triggered */ - CDOG_CONTROL_MISCOMPARE_CTRL(conf->miscompare) | /* Action if the miscompare error event is triggered */ - CDOG_CONTROL_SEQUENCE_CTRL(conf->sequence) | /* Action if the sequence error event is triggered */ - CDOG_CONTROL_STATE_CTRL(conf->state) | /* Action if the state error event is triggered */ - CDOG_CONTROL_ADDRESS_CTRL(conf->address) | /* Action if the address error event is triggered */ - CDOG_CONTROL_IRQ_PAUSE(conf->irq_pause) | /* Pause running during interrupts setup */ - CDOG_CONTROL_DEBUG_HALT_CTRL( - conf->debug_halt) | /* Halt CDOG timer during debug so we have chance to debug code */ - CDOG_CONTROL_LOCK_CTRL(conf->lock); /* Lock control register */ - - NVIC_EnableIRQ(CDOG_IRQn); - - return kStatus_Success; -} - -/*! - * brief Deinitialize CDOG - * - * This function stops CDOG secure counter. - * - * param base CDOG peripheral base address - */ -void CDOG_Deinit(CDOG_Type *base) -{ - NVIC_DisableIRQ(CDOG_IRQn); - -#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET) - RESET_SetPeripheralReset(kCDOG_RST_SHIFT_RSTn); -#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#ifdef CDOG_CLOCKS - CLOCK_DisableClock(kCLOCK_Cdog); -#endif /* CDOG_CLOCKS */ -#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_cdog.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_cdog.h deleted file mode 100644 index b93c8dbdfe7..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_cdog.h +++ /dev/null @@ -1,325 +0,0 @@ -/* - * Copyright 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_CDOG_H_ -#define _FSL_CDOG_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup CDOG - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Defines CDOG driver version 2.1.1. - * - * Change log: - * - Version 2.1.1 - * - Remove bit CONTROL[CONTROL_CTRL] - * - Version 2.1.0 - * - Rename CWT to CDOG - * - Version 2.0.2 - * - Fix MISRA-2012 issues - * - Version 2.0.1 - * - Fix doxygen issues - * - Version 2.0.0 - * - initial version - */ -#define FSL_CDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) -/*@}*/ - -typedef struct -{ - uint8_t lock : 2; - uint8_t timeout : 3; - uint8_t miscompare : 3; - uint8_t sequence : 3; - uint8_t state : 3; - uint8_t address : 3; - uint8_t reserved : 8; - uint8_t irq_pause : 2; - uint8_t debug_halt : 2; -} cdog_config_t; - -enum __cdog_debug_Action_ctrl_enum -{ - kCDOG_DebugHaltCtrl_Run = 0x1, - kCDOG_DebugHaltCtrl_Pause = 0x2, -}; - -enum __cdog_irq_pause_ctrl_enum -{ - kCDOG_IrqPauseCtrl_Run = 0x1, - kCDOG_IrqPauseCtrl_Pause = 0x2, -}; - -enum __cdog_fault_ctrl_enum -{ - kCDOG_FaultCtrl_EnableReset = 0x1U, - kCDOG_FaultCtrl_EnableInterrupt = 0x2U, - kCDOG_FaultCtrl_NoAction = 0x4U, -}; - -enum __code_lock_ctrl_enum -{ - kCDOG_LockCtrl_Lock = 0x1, - kCDOG_LockCtrl_Unlock = 0x2, -}; - -typedef uint32_t secure_counter_t; - -#define SC_ADD(add) \ - do \ - { \ - CDOG->ADD = (secure_counter_t)(add); \ - } while (0) - -#define SC_ADD1 \ - do \ - { \ - CDOG->ADD1 = (secure_counter_t)0x1U; \ - } while (0) - -#define SC_ADD16 \ - do \ - { \ - CDOG->ADD16 = (secure_counter_t)0x1U; \ - } while (0) - -#define SC_ADD256 \ - do \ - { \ - CDOG->ADD256 = (secure_counter_t)0x1U; \ - } while (0) - -#define SC_SUB(sub) \ - do \ - { \ - CDOG->SUB = (secure_counter_t)(sub); \ - } while (0) - -#define SC_SUB1 \ - do \ - { \ - CDOG->SUB1 = (secure_counter_t)0x1U; \ - } while (0) - -#define SC_SUB16 \ - do \ - { \ - CDOG->SUB16 = (secure_counter_t)0x1U; \ - } while (0) - -#define SC_SUB256 \ - do \ - { \ - CDOG->SUB256 = (secure_counter_t)0x1U; \ - } while (0) - -#define SC_CHECK(val) \ - do \ - { \ - CDOG->RESTART = (secure_counter_t)val; \ - } while (0) - -/******************************************************************************* - * API - *******************************************************************************/ - -extern void CDOG_DriverIRQHandler(void); - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name CDOG Functional Operation - * @{ - */ - -/*! - * @brief Initialize CDOG - * - * This function initializes CDOG block and setting. - * - * @param base CDOG peripheral base address - * @param conf CDOG configuration structure - * @return Status of the init operation - */ -status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf); - -/*! - * @brief Deinitialize CDOG - * - * This function deinitializes CDOG secure counter. - * - * @param base CDOG peripheral base address - */ -void CDOG_Deinit(CDOG_Type *base); - -/*! - * @brief Sets the default configuration of CDOG - * - * This function initialize CDOG config structure to default values. - * - * @param conf CDOG configuration structure - */ -void CDOG_GetDefaultConfig(cdog_config_t *conf); - -/*! - * @brief Stops secure counter and instruction timer - * - * This function stops instruction timer and secure counter. - * This also change state od CDOG to IDLE. - * - * @param base CDOG peripheral base address - * @param stop expected value which will be compared with value of secure counter - */ -void CDOG_Stop(CDOG_Type *base, uint32_t stop); - -/*! - * @brief Sets secure counter and instruction timer values - * - * This function sets value in RELOAD and START registers - * for instruction timer and secure counter - * - * @param base CDOG peripheral base address - * @param reload reload value - * @param start start value - */ -void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start); - -/*! - * @brief Checks secure counter. - * - * This function compares stop value in handler with secure counter value - * by writting to RELOAD refister. - * - * @param base CDOG peripheral base address - * @param check expected (stop) value - */ -void CDOG_Check(CDOG_Type *base, uint32_t check); - -/*! - * @brief Sets secure counter and instruction timer values - * - * This function sets value in STOP, RELOAD and START registers - * for instruction timer and secure counter. - * - * @param base CDOG peripheral base address - * @param stop expected value which will be compared with value of secure counter - * @param reload reload value for instruction timer - * @param start start value for secure timer - */ -void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start); - -/*! - * @brief Add value to secure counter - * - * This function add specified value to secure counter. - * - * @param base CDOG peripheral base address. - * @param add Value to be added. - */ -void CDOG_Add(CDOG_Type *base, uint32_t add); - -/*! - * @brief Add 1 to secure counter - * - * This function add 1 to secure counter. - * - * @param base CDOG peripheral base address. - */ -void CDOG_Add1(CDOG_Type *base); - -/*! - * @brief Add 16 to secure counter - * - * This function add 16 to secure counter. - * - * @param base CDOG peripheral base address. - */ -void CDOG_Add16(CDOG_Type *base); - -/*! - * @brief Add 256 to secure counter - * - * This function add 256 to secure counter. - * - * @param base CDOG peripheral base address. - */ -void CDOG_Add256(CDOG_Type *base); - -/*! - * brief Substract value to secure counter - * - * This function substract specified value to secure counter. - * - * param base CDOG peripheral base address. - * param sub Value to be substracted. - */ -void CDOG_Sub(CDOG_Type *base, uint32_t sub); - -/*! - * @brief Substract 1 from secure counter - * - * This function substract specified 1 from secure counter. - * - * @param base CDOG peripheral base address. - */ -void CDOG_Sub1(CDOG_Type *base); - -/*! - * @brief Substract 16 from secure counter - * - * This function substract specified 16 from secure counter. - * - * @param base CDOG peripheral base address. - */ -void CDOG_Sub16(CDOG_Type *base); - -/*! - * @brief Substract 256 from secure counter - * - * This function substract specified 256 from secure counter. - * - * @param base CDOG peripheral base address. - */ -void CDOG_Sub256(CDOG_Type *base); - -/*! - * @brief Set the CDOG persistent word. - * - * @param base CDOG peripheral base address. - * @param value The value to be written. - */ -void CDOG_WritePersistent(CDOG_Type *base, uint32_t value); - -/*! - * @brief Get the CDOG persistent word. - * - * @param base CDOG peripheral base address. - * @return The persistent word. - */ -uint32_t CDOG_ReadPersistent(CDOG_Type *base); - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ /* end of group cdog */ - -#endif /* _FSL_CDOG_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_clock.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_clock.c deleted file mode 100644 index d1b1b4b529d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_clock.c +++ /dev/null @@ -1,1904 +0,0 @@ -/* - * Copyright 2017 - 2021 , NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_clock.h" -#include "fsl_power.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.clock" -#endif -#define NVALMAX (0x100U) -#define PVALMAX (0x20U) -#define MVALMAX (0x10000U) - -#define PLL_MAX_N_DIV 0x100U - -/*-------------------------------------------------------------------------- -!!! If required these #defines can be moved to chip library file -----------------------------------------------------------------------------*/ - -#define PLL_SSCG1_MDEC_VAL_P (10U) /* MDEC is in bits 25 downto 10 */ -#define PLL_SSCG1_MDEC_VAL_M (0xFFFFULL << PLL_SSCG1_MDEC_VAL_P) -#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */ -#define PLL_NDEC_VAL_M (0xFFUL << PLL_NDEC_VAL_P) -#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */ -#define PLL_PDEC_VAL_M (0x1FUL << PLL_PDEC_VAL_P) - -#define PLL_MIN_CCO_FREQ_MHZ (275000000U) -#define PLL_MAX_CCO_FREQ_MHZ (550000000U) -#define PLL_LOWER_IN_LIMIT (2000U) /*!< Minimum PLL input rate */ -#define PLL_HIGHER_IN_LIMIT (96000000U) /*!< Maximum PLL input rate */ -#define PLL_MIN_IN_SSMODE (3000000U) -#define PLL_MAX_IN_SSMODE \ - (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */ - -/* PLL NDEC reg */ -#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) -/* PLL PDEC reg */ -#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M) -/* SSCG control1 */ -#define PLL_SSCG1_MDEC_VAL_SET(value) (((uint64_t)(value) << PLL_SSCG1_MDEC_VAL_P) & PLL_SSCG1_MDEC_VAL_M) - -/* PLL0 SSCG control1 */ -#define PLL0_SSCG_MD_FRACT_P 0U -#define PLL0_SSCG_MD_INT_P 25U -#define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) -#define PLL0_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL0_SSCG_MD_INT_P) - -#define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_FRACT_M) -#define PLL0_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_INT_P) & PLL0_SSCG_MD_INT_M) - -/* Saved value of PLL output rate, computed whenever needed to save run-time - computation on each call to retrive the PLL rate. */ -static uint32_t s_Pll0_Freq; -static uint32_t s_Pll1_Freq; - -/** External clock rate on the CLKIN pin in Hz. If not used, - set this to 0. Otherwise, set it to the exact rate in Hz this pin is - being driven at. */ -static uint32_t s_Ext_Clk_Freq = 16000000U; -static uint32_t s_I2S_Mclk_Freq = 0U; -static uint32_t s_PLU_ClkIn_Freq = 0U; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ -static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); -/* Get predivider (N) from PLL0 NDEC setting */ -static uint32_t findPll0PreDiv(void); -/* Get predivider (N) from PLL1 NDEC setting */ -static uint32_t findPll1PreDiv(void); -/* Get postdivider (P) from PLL0 PDEC setting */ -static uint32_t findPll0PostDiv(void); -/* Get postdivider (P) from PLL1 PDEC setting. */ -static uint32_t findPll1PostDiv(void); -/* Get multiplier (M) from PLL0 MDEC and SSCG settings */ -static float findPll0MMult(void); -/* Get multiplier (M) from PLL1 MDEC. */ -static uint32_t findPll1MMult(void); -/* Get the greatest common divisor */ -static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); -/* Set PLL output based on desired output rate */ -static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS); -/* Update local PLL rate variable */ -static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup); -/* Update local PLL1 rate variable */ -static void CLOCK_GetPLL1OutFromSetupUpdate(pll_setup_t *pSetup); - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Clock Selection for IP */ -/** - * brief Configure the clock selection muxes. - * param connection : Clock to be configured. - * return Nothing - */ -void CLOCK_AttachClk(clock_attach_id_t connection) -{ - uint8_t mux; - uint8_t sel; - uint16_t item; - uint32_t tmp32 = (uint32_t)connection; - uint32_t i; - volatile uint32_t *pClkSel; - - pClkSel = &(SYSCON->SYSTICKCLKSELX[0]); - - if (kNONE_to_NONE != connection) - { - for (i = 0U; i < 2U; i++) - { - if (tmp32 == 0U) - { - break; - } - item = (uint16_t)GET_ID_ITEM(tmp32); - if (item != 0U) - { - mux = (uint8_t)GET_ID_ITEM_MUX(item); - sel = (uint8_t)GET_ID_ITEM_SEL(item); - if (mux == CM_RTCOSC32KCLKSEL) - { - PMC->RTCOSC32K = (PMC->RTCOSC32K & ~PMC_RTCOSC32K_SEL_MASK) | PMC_RTCOSC32K_SEL(sel); - } - else if (mux == CM_OSTIMERCLKSEL) - { - PMC->OSTIMERr = (PMC->OSTIMERr & ~PMC_OSTIMER_OSTIMERCLKSEL_MASK) | PMC_OSTIMER_OSTIMERCLKSEL(sel); - } - else - { - pClkSel[mux] = sel; - } - } - tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */ - } - } -} - -/* Return the actual clock attach id */ -/** - * brief Get the actual clock attach id. - * This fuction uses the offset in input attach id, then it reads the actual source value in - * the register and combine the offset to obtain an actual attach id. - * param attachId : Clock attach id to get. - * return Clock source value. - */ -clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId) -{ - uint8_t mux; - uint32_t actualSel; - uint32_t tmp32 = (uint32_t)attachId; - uint32_t i; - uint32_t actualAttachId = 0U; - uint32_t selector = GET_ID_SELECTOR(tmp32); - volatile uint32_t *pClkSel; - - pClkSel = &(SYSCON->SYSTICKCLKSELX[0]); - - if (kNONE_to_NONE == attachId) - { - return kNONE_to_NONE; - } - - for (i = 0U; i < 2U; i++) - { - mux = (uint8_t)GET_ID_ITEM_MUX(tmp32); - if (tmp32 != 0UL) - { - if (mux == CM_RTCOSC32KCLKSEL) - { - actualSel = ((PMC->RTCOSC32K) & PMC_RTCOSC32K_SEL_MASK) >> PMC_RTCOSC32K_SEL_SHIFT; - } - else if (mux == CM_OSTIMERCLKSEL) - { - actualSel = ((PMC->OSTIMERr) & PMC_OSTIMER_OSTIMERCLKSEL_MASK) >> PMC_OSTIMER_OSTIMERCLKSEL_SHIFT; - } - else - { - actualSel = pClkSel[mux]; - } - - /* Consider the combination of two registers */ - actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i); - } - tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */ - } - - actualAttachId |= selector; - - return (clock_attach_id_t)actualAttachId; -} - -/* Set IP Clock Divider */ -/** - * brief Setup peripheral clock dividers. - * param div_name : Clock divider name - * param divided_by_value: Value to be divided - * param reset : Whether to reset the divider counter. - * return Nothing - */ -void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) -{ - volatile uint32_t *pClkDiv; - - pClkDiv = &(SYSCON->SYSTICKCLKDIV0); - - if ((div_name >= kCLOCK_DivFlexFrg0) && (div_name <= kCLOCK_DivFlexFrg7)) - { - /*!< Flexcomm Interface function clock = (clock selected via FCCLKSEL) / (1+ MULT /DIV), DIV = 0xFF */ - ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = - SYSCON_FLEXFRG0CTRL_DIV_MASK | SYSCON_FLEXFRG0CTRL_MULT(divided_by_value); - } - else - { - if (reset) - { - ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = 1UL << 29U; - } - if (divided_by_value == 0U) /*!< halt */ - { - ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = 1UL << 30U; - } - else - { - ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = (divided_by_value - 1U); - } - } -} - -/* Set RTC 1KHz Clock Divider */ -/** - * brief Setup rtc 1khz clock divider. - * param divided_by_value: Value to be divided - * return Nothing - */ -void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value) -{ - PMC->RTCOSC32K = - (PMC->RTCOSC32K & ~PMC_RTCOSC32K_CLK1KHZDIV_MASK) | PMC_RTCOSC32K_CLK1KHZDIV(divided_by_value - 28U); -} - -/* Set RTC 1KHz Clock Divider */ -/** - * brief Setup rtc 1hz clock divider. - * param divided_by_value: Value to be divided - * return Nothing - */ -void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value) -{ - if (divided_by_value == 0U) /*!< halt */ - { - PMC->RTCOSC32K |= (1UL << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT); - } - else - { - PMC->RTCOSC32K = - (PMC->RTCOSC32K & ~PMC_RTCOSC32K_CLK1HZDIV_MASK) | PMC_RTCOSC32K_CLK1HZDIV(divided_by_value - 31744U); - } -} - -/* Set FRO Clocking */ -/** - * brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). - * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is - * enabled. - * param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ) - * return returns success or fail status. - */ -status_t CLOCK_SetupFROClocking(uint32_t iFreq) -{ - if ((iFreq != 12000000U) && (iFreq != 96000000U)) - { - return kStatus_Fail; - } - /* Enable Analog Control module */ - SYSCON->PRESETCTRLCLR[2] = (1UL << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT); - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK; - /* Power up the FRO192M */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); - - if (iFreq == 96000000U) - { - ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(1); - } - /* always enable - else if (iFreq == 48000000U) - { - ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(1); - }*/ - else - { - ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(1); - } - return kStatus_Success; -} - -/* Set the FLASH wait states for the passed frequency */ -/** - * brief Set the flash wait states for the input freuqency. - * param iFreq: Input frequency - * return Nothing - */ -typedef struct -{ - uint32_t waitstate; - uint32_t freqMax; -} WaitStateInterval_t; - -/* clang-format off */ -/* Wait state if frequency is inferior to the one specified */ -static const WaitStateInterval_t IntervalList[] = { - {0, 11000000}, - {1, 22000000}, - {2, 33000000}, - {3, 44000000}, - {4, 55000000}, - {5, 66000000}, - {6, 84000000}, - {7, 96000000} /* Maximum allowed frequency (96 MHz) */ -}; -/* clang-format on */ - -void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz) -{ - /* Flash Controller & FMC internal number of Wait States (minus 1) */ - uint32_t num_wait_states = 15UL; /* Default to the maximum number of wait states */ - - for (size_t cnt = 0; cnt < (sizeof(IntervalList) / sizeof(WaitStateInterval_t)); cnt++) - { - if (system_freq_hz <= IntervalList[cnt].freqMax) - { - num_wait_states = IntervalList[cnt].waitstate; - break; - } - } - - FLASH->INT_CLR_STATUS = 0x1F; /* Clear all status flags */ - - FLASH->DATAW[0] = (FLASH->DATAW[0] & 0xFFFFFFF0UL) | - (num_wait_states & (SYSCON_FMCCR_FLASHTIM_MASK >> SYSCON_FMCCR_FLASHTIM_SHIFT)); - - FLASH->CMD = 0x2; /* CMD_SET_READ_MODE */ - - /* Wait until the cmd is completed (without error) */ - while ((FLASH->INT_STATUS & FLASH_INT_STATUS_DONE_MASK) == 0UL) - { - } - - /* Adjust FMC waiting time cycles (num_wait_states) */ - SYSCON->FMCCR = (SYSCON->FMCCR & ~SYSCON_FMCCR_FLASHTIM_MASK) | - ((num_wait_states << SYSCON_FMCCR_FLASHTIM_SHIFT) & SYSCON_FMCCR_FLASHTIM_MASK); -} - -/* Set EXT OSC Clk */ -/** - * brief Initialize the external osc clock to given frequency. - * Crystal oscillator with an operating frequency of 12 MHz to 32 MHz. - * Option for external clock input (bypass mode) for clock frequencies of up to 25 MHz. - * param iFreq : Desired frequency (must be equal to exact rate in Hz) - * return returns success or fail status. - */ -status_t CLOCK_SetupExtClocking(uint32_t iFreq) -{ - if (iFreq > 32000000U) - { - return kStatus_Fail; - } - /* Turn on power for crystal 32 MHz */ - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); - /* Enable clock_in clock for clock module. */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; - - s_Ext_Clk_Freq = iFreq; - return kStatus_Success; -} - -/* Set I2S MCLK Clk */ -/** - * brief Initialize the I2S MCLK clock to given frequency. - * param iFreq : Desired frequency (must be equal to exact rate in Hz) - * return returns success or fail status. - */ -status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq) -{ - s_I2S_Mclk_Freq = iFreq; - return kStatus_Success; -} - -/* Set PLU CLKIN Clk */ -/** - * brief Initialize the PLU CLKIN clock to given frequency. - * param iFreq : Desired frequency (must be equal to exact rate in Hz) - * return returns success or fail status. - */ -status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq) -{ - s_PLU_ClkIn_Freq = iFreq; - return kStatus_Success; -} - -/* Get CLOCK OUT Clk */ -/*! brief Return Frequency of ClockOut - * return Frequency of ClockOut - */ -uint32_t CLOCK_GetClockOutClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->CLKOUTSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - - case 2U: - freq = CLOCK_GetExtClkFreq(); - break; - - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - - case 5U: - freq = CLOCK_GetPll1OutFreq(); - break; - - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U); -} - -/* Get CAN Clk */ -/*! brief Return Frequency of Can Clock - * return Frequency of Can. - */ -uint32_t CLOCK_GetMCanClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->CANCLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CANCLKDIV & SYSCON_CANCLKDIV_DIV_MASK) + 1U); - break; - case 1U: - freq = CLOCK_GetFro1MFreq(); - break; - case 2U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq; -} - -/* Get ADC Clk */ -/*! brief Return Frequency of Adc Clock - * return Frequency of Adc. - */ -uint32_t CLOCK_GetAdcClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->ADCCLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 2U: - freq = CLOCK_GetFroHfFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq / ((SYSCON->ADCCLKDIV & SYSCON_ADCCLKDIV_DIV_MASK) + 1U); -} - -/* Get MCLK Clk */ -/*! brief Return Frequency of MClk Clock - * return Frequency of MClk Clock. - */ -uint32_t CLOCK_GetMclkClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->MCLKCLKSEL) - { - case 0U: - freq = CLOCK_GetFroHfFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq / ((SYSCON->MCLKDIV & 0xffU) + 1U); -} - -/* Get SCTIMER Clk */ -/*! brief Return Frequency of SCTimer Clock - * return Frequency of SCTimer Clock. - */ -uint32_t CLOCK_GetSctClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->SCTCLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 2U: - freq = CLOCK_GetExtClkFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 5U: - freq = CLOCK_GetI2SMClkFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq / ((SYSCON->SCTCLKDIV & 0xffU) + 1U); -} - -/* Get FRO 12M Clk */ -/*! brief Return Frequency of FRO 12MHz - * return Frequency of FRO 12MHz - */ -uint32_t CLOCK_GetFro12MFreq(void) -{ - return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; -} - -/* Get FRO 1M Clk */ -/*! brief Return Frequency of FRO 1MHz - * return Frequency of FRO 1MHz - */ -uint32_t CLOCK_GetFro1MFreq(void) -{ - return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; -} - -/* Get EXT OSC Clk */ -/*! brief Return Frequency of External Clock - * return Frequency of External Clock. If no external clock is used returns 0. - */ -uint32_t CLOCK_GetExtClkFreq(void) -{ - return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; -} - -/* Get WATCH DOG Clk */ -/*! brief Return Frequency of Watchdog - * return Frequency of Watchdog - */ -uint32_t CLOCK_GetWdtClkFreq(void) -{ - return CLOCK_GetFro1MFreq() / ((SYSCON->WDTCLKDIV & SYSCON_WDTCLKDIV_DIV_MASK) + 1U); -} - -/* Get HF FRO Clk */ -/*! brief Return Frequency of High-Freq output of FRO - * return Frequency of High-Freq output of FRO - */ -uint32_t CLOCK_GetFroHfFreq(void) -{ - return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; -} - -/* Get SYSTEM PLL Clk */ -/*! brief Return Frequency of PLL - * return Frequency of PLL - */ -uint32_t CLOCK_GetPll0OutFreq(void) -{ - return s_Pll0_Freq; -} - -/* Get USB PLL Clk */ -/*! brief Return Frequency of USB PLL - * return Frequency of PLL - */ -uint32_t CLOCK_GetPll1OutFreq(void) -{ - return s_Pll1_Freq; -} - -/* Get RTC OSC Clk */ -/*! brief Return Frequency of 32kHz osc - * return Frequency of 32kHz osc - */ -uint32_t CLOCK_GetOsc32KFreq(void) -{ - return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && - (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? - CLK_RTC_32K_CLK : - ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && - ((PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK) != 0UL)) ? - CLK_RTC_32K_CLK : - 0UL; -} - -/* Get MAIN Clk */ -/*! brief Return Frequency of Core System - * return Frequency of Core System - */ -uint32_t CLOCK_GetCoreSysClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->MAINCLKSELB) - { - case 0U: - if (SYSCON->MAINCLKSELA == 0U) - { - freq = CLOCK_GetFro12MFreq(); - } - else if (SYSCON->MAINCLKSELA == 1U) - { - freq = CLOCK_GetExtClkFreq(); - } - else if (SYSCON->MAINCLKSELA == 2U) - { - freq = CLOCK_GetFro1MFreq(); - } - else if (SYSCON->MAINCLKSELA == 3U) - { - freq = CLOCK_GetFroHfFreq(); - } - else - { - /* Added comments to avoid the violation of MISRA C-2012 rule 15.7 */ - } - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 2U: - freq = CLOCK_GetPll1OutFreq(); - break; - - case 3U: - freq = CLOCK_GetOsc32KFreq(); - break; - - default: - freq = 0U; - break; - } - - return freq; -} - -/* Get I2S MCLK Clk */ -/*! brief Return Frequency of I2S MCLK Clock - * return Frequency of I2S MCLK Clock - */ -uint32_t CLOCK_GetI2SMClkFreq(void) -{ - return s_I2S_Mclk_Freq; -} - -/* Get PLU CLKIN Clk */ -/*! brief Return Frequency of PLU CLKIN Clock - * return Frequency of PLU CLKIN Clock - */ -uint32_t CLOCK_GetPLUClkInFreq(void) -{ - return s_PLU_ClkIn_Freq; -} - -/* Get FLEXCOMM input clock */ -/*! brief Return Frequency of flexcomm input clock - * param id : flexcomm instance id - * return Frequency value - */ -uint32_t CLOCK_GetFlexCommInputClock(uint32_t id) -{ - uint32_t freq = 0U; - - switch (SYSCON->FCCLKSELX[id]) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U); - break; - case 2U: - freq = CLOCK_GetFro12MFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); - break; - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - case 5U: - freq = CLOCK_GetI2SMClkFreq(); - break; - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq; -} - -/* Get FLEXCOMM Clk */ -uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) -{ - uint32_t freq = 0U; - uint32_t frgMul = 0U; - uint32_t frgDiv = 0U; - - freq = CLOCK_GetFlexCommInputClock(id); - frgMul = (SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_MULT_MASK) >> 8U; - frgDiv = SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_DIV_MASK; - return (uint32_t)(((uint64_t)freq * ((uint64_t)frgDiv + 1ULL)) / (frgMul + frgDiv + 1UL)); -} - -/* Get HS_LPSI Clk */ -uint32_t CLOCK_GetHsLspiClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->HSLSPICLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U); - break; - case 2U: - freq = CLOCK_GetFro12MFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); - break; - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq; -} - -/* Get CTimer Clk */ -/*! brief Return Frequency of CTimer functional Clock - * return Frequency of CTimer functional Clock - */ -uint32_t CLOCK_GetCTimerClkFreq(uint32_t id) -{ - uint32_t freq = 0U; - - switch (SYSCON->CTIMERCLKSELX[id]) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - case 5U: - freq = CLOCK_GetI2SMClkFreq(); - break; - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq; -} - -/* Get Systick Clk */ -/*! brief Return Frequency of SystickClock - * return Frequency of Systick Clock - */ -uint32_t CLOCK_GetSystickClkFreq(uint32_t id) -{ - uint32_t freq = 0U; - - switch (SYSCON->SYSTICKCLKSELX[id]) - { - case 0U: - /*Niobe4mini just has one SYSTICKSEL and SYSTICKDIV register, Fix coverity problem in this way temporarily - */ - freq = CLOCK_GetCoreSysClkFreq() / (((SYSCON->SYSTICKCLKDIV0) & 0xffU) + 1U); - break; - case 1U: - freq = CLOCK_GetFro1MFreq(); - break; - case 2U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq; -} - -/* Set FlexComm Clock */ -/** - * brief Set the flexcomm output frequency. - * param id : flexcomm instance id - * freq : output frequency - * return 0 : the frequency range is out of range. - * 1 : switch successfully. - */ -uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq) -{ - uint32_t input = CLOCK_GetFlexCommClkFreq(id); - uint32_t mul; - - if ((freq > 48000000UL) || (freq > input) || (input / freq >= 2UL)) - { - /* FRG output frequency should be less than equal to 48MHz */ - return 0UL; - } - else - { - mul = (uint32_t)((((uint64_t)input - freq) * 256ULL) / ((uint64_t)freq)); - SYSCON->FLEXFRGXCTRL[id] = (mul << 8U) | 0xFFU; - return 1UL; - } -} - -/* Get IP Clk */ -/*! brief Return Frequency of selected clock - * return Frequency of selected clock - */ -uint32_t CLOCK_GetFreq(clock_name_t clockName) -{ - uint32_t freq; - switch (clockName) - { - case kCLOCK_CoreSysClk: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case kCLOCK_BusClk: - freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); - break; - case kCLOCK_ClockOut: - freq = CLOCK_GetClockOutClkFreq(); - break; - case kCLOCK_Pll1Out: - freq = CLOCK_GetPll1OutFreq(); - break; - case kCLOCK_Mclk: - freq = CLOCK_GetMclkClkFreq(); - break; - case kCLOCK_FroHf: - freq = CLOCK_GetFroHfFreq(); - break; - case kCLOCK_Fro12M: - freq = CLOCK_GetFro12MFreq(); - break; - case kCLOCK_Fro1M: - freq = CLOCK_GetFro1MFreq(); - break; - case kCLOCK_ExtClk: - freq = CLOCK_GetExtClkFreq(); - break; - case kCLOCK_Pll0Out: - freq = CLOCK_GetPll0OutFreq(); - break; - case kCLOCK_FlexI2S: - freq = CLOCK_GetI2SMClkFreq(); - break; - default: - freq = 0U; - break; - } - return freq; -} - -/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ -static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) -{ - uint32_t seli, selp; - /* bandwidth: compute selP from Multiplier */ - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ - { - selp = (M >> 2U) + 1U; - if (selp >= 31U) - { - selp = 31U; - } - *pSelP = selp; - - if (M >= 8000UL) - { - seli = 1UL; - } - else if (M >= 122UL) - { - seli = (uint32_t)(8000UL / M); /*floor(8000/M) */ - } - else - { - seli = 2UL * ((uint32_t)(M / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ - } - - if (seli >= 63UL) - { - seli = 63UL; - } - *pSelI = seli; - - *pSelR = 0UL; - } - else - { - /* Note: If the spread spectrum mode, choose N to ensure 3 MHz < Fin/N < 5 MHz */ - *pSelP = 3U; - *pSelI = 4U; - *pSelR = 4U; - } -} - -/* Get predivider (N) from PLL0 NDEC setting */ -static uint32_t findPll0PreDiv(void) -{ - uint32_t preDiv = 1UL; - - /* Direct input is not used? */ - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) - { - preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; - if (preDiv == 0UL) - { - preDiv = 1UL; - } - } - return preDiv; -} - -/* Get predivider (N) from PLL1 NDEC setting */ -static uint32_t findPll1PreDiv(void) -{ - uint32_t preDiv = 1UL; - - /* Direct input is not used? */ - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) - { - preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; - if (preDiv == 0UL) - { - preDiv = 1UL; - } - } - return preDiv; -} - -/* Get postdivider (P) from PLL0 PDEC setting */ -static uint32_t findPll0PostDiv(void) -{ - uint32_t postDiv = 1UL; - - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) - { - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) - { - postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; - } - else - { - postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); - } - if (postDiv == 0UL) - { - postDiv = 2UL; - } - } - return postDiv; -} - -/* Get postdivider (P) from PLL1 PDEC setting. */ -static uint32_t findPll1PostDiv(void) -{ - uint32_t postDiv = 1UL; - - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0UL) - { - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) != 0UL) - { - postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK; - } - else - { - postDiv = 2UL * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK); - } - if (postDiv == 0UL) - { - postDiv = 2UL; - } - } - - return postDiv; -} - -/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ -static float findPll0MMult(void) -{ - float mMult = 1.0F; - float mMult_fract; - uint32_t mMult_int; - - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) - { - mMult = - (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); - } - else - { - mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); - mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL0_SSCG_MD_INT_P); - mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL0_SSCG_MD_FRACT_M) / - (float)(uint32_t)(1UL << PLL0_SSCG_MD_INT_P)); - mMult = (float)mMult_int + mMult_fract; - } - if(0ULL == ((uint64_t)mMult)) - { - mMult = 1.0F; - } - return mMult; -} - -/* Get multiplier (M) from PLL1 MDEC. */ -static uint32_t findPll1MMult(void) -{ - uint32_t mMult = 1UL; - - mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK; - - if (mMult == 0UL) - { - mMult = 1UL; - } - - return mMult; -} - -/* Find greatest common divisor between m and n */ -static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) -{ - uint32_t tmp; - - while (n != 0U) - { - tmp = n; - n = m % n; - m = tmp; - } - - return m; -} - -/* - * Set PLL0 output based on desired output rate. - * In this function, the it calculates the PLL0 setting for output frequency from input clock - * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. - * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. - */ -static pll_error_t CLOCK_GetPll0ConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) -{ - uint32_t nDivOutHz, fccoHz; - uint32_t pllPreDivider, pllMultiplier, pllPostDivider; - uint32_t pllDirectInput, pllDirectOutput; - uint32_t pllSelP, pllSelI, pllSelR, uplimoff; - - /* Baseline parameters (no input or output dividers) */ - pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ - pllPostDivider = 1U; /* 1 implies post-divider will be disabled */ - pllDirectOutput = 1U; - - /* Verify output rate parameter */ - if (foutHz > PLL_MAX_CCO_FREQ_MHZ) - { - /* Maximum PLL output with post divider=1 cannot go above this frequency */ - return kStatus_PLL_OutputTooHigh; - } - if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) - { - /* Minmum PLL output with maximum post divider cannot go below this frequency */ - return kStatus_PLL_OutputTooLow; - } - - /* If using SS mode, input clock needs to be between 3MHz and 20MHz */ - if (useSS) - { - /* Verify input rate parameter */ - if (finHz < PLL_MIN_IN_SSMODE) - { - /* Input clock into the PLL cannot be lower than this */ - return kStatus_PLL_InputTooLow; - } - /* PLL input in SS mode must be under 20MHz */ - if (finHz > (PLL_MAX_IN_SSMODE * NVALMAX)) - { - return kStatus_PLL_InputTooHigh; - } - } - else - { - /* Verify input rate parameter */ - if (finHz < PLL_LOWER_IN_LIMIT) - { - /* Input clock into the PLL cannot be lower than this */ - return kStatus_PLL_InputTooLow; - } - if (finHz > PLL_HIGHER_IN_LIMIT) - { - /* Input clock into the PLL cannot be higher than this */ - return kStatus_PLL_InputTooHigh; - } - } - - /* Find the optimal CCO frequency for the output and input that - will keep it inside the PLL CCO range. This may require - tweaking the post-divider for the PLL. */ - fccoHz = foutHz; - while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) - { - /* CCO output is less than minimum CCO range, so the CCO output - needs to be bumped up and the post-divider is used to bring - the PLL output back down. */ - pllPostDivider++; - if (pllPostDivider > PVALMAX) - { - return kStatus_PLL_OutsideIntLimit; - } - - /* Target CCO goes up, PLL output goes down */ - /* divide-by-2 divider in the post-divider is always work*/ - fccoHz = foutHz * (pllPostDivider * 2U); - pllDirectOutput = 0U; - } - - /* Determine if a pre-divider is needed to get the best frequency */ - if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) - { - uint32_t a = FindGreatestCommonDivisor(fccoHz, finHz); - - if (a > PLL_LOWER_IN_LIMIT) - { - a = finHz / a; - if ((a != 0U) && (a < PLL_MAX_N_DIV)) - { - pllPreDivider = a; - } - } - } - - /* Bypass pre-divider hardware if pre-divider is 1 */ - if (pllPreDivider > 1U) - { - pllDirectInput = 0U; - } - else - { - pllDirectInput = 1U; - } - - /* Determine PLL multipler */ - nDivOutHz = (finHz / pllPreDivider); - pllMultiplier = (fccoHz / nDivOutHz); - - /* Find optimal values for filter */ - if (useSS == false) - { - /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ - if ((nDivOutHz * ((pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) - { - pllMultiplier++; - } - - /* Setup filtering */ - pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR); - uplimoff = 0U; - - /* Get encoded value for M (mult) and use manual filter, disable SS mode */ - pSetup->pllsscg[1] = - (uint32_t)((PLL_SSCG1_MDEC_VAL_SET(pllMultiplier)) | (1UL << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)); - } - else - { - uint64_t fc; - - /* Filtering will be handled by SSC */ - pllSelR = 0UL; - pllSelI = 0UL; - pllSelP = 0UL; - uplimoff = 1U; - - /* The PLL multiplier will get very close and slightly under the - desired target frequency. A small fractional component can be - added to fine tune the frequency upwards to the target. */ - fc = ((uint64_t)(uint32_t)(fccoHz % nDivOutHz) << 25UL) / nDivOutHz; - - /* Set multiplier */ - pSetup->pllsscg[0] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) | PLL0_SSCG_MD_FRACT_SET((uint32_t)fc)); - pSetup->pllsscg[1] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) >> 32U); - } - - /* Get encoded values for N (prediv) and P (postdiv) */ - pSetup->pllndec = PLL_NDEC_VAL_SET(pllPreDivider); - pSetup->pllpdec = PLL_PDEC_VAL_SET(pllPostDivider); - - /* PLL control */ - pSetup->pllctrl = (pllSelR << SYSCON_PLL0CTRL_SELR_SHIFT) | /* Filter coefficient */ - (pllSelI << SYSCON_PLL0CTRL_SELI_SHIFT) | /* Filter coefficient */ - (pllSelP << SYSCON_PLL0CTRL_SELP_SHIFT) | /* Filter coefficient */ - (0UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT) | /* PLL bypass mode disabled */ - (uplimoff << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */ - (pllDirectInput << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */ - (pllDirectOutput << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT) | /* Bypass post-divider? */ - (1UL << SYSCON_PLL0CTRL_CLKEN_SHIFT); /* Ensure the PLL clock output */ - - return kStatus_PLL_Success; -} - -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) -/* Alloct the static buffer for cache. */ -static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; -static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; -static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; -static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; -static uint32_t s_PllSetupCacheIdx = 0U; -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - -/* - * Calculate the PLL setting values from input clock freq to output freq. - */ -static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) -{ - pll_error_t retErr; -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - uint32_t i; - - for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) - { - if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && (useSS == s_UseSSCache[i])) - { - /* Hit the target in cache buffer. */ - pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl; - pSetup->pllndec = s_PllSetupCacheStruct[i].pllndec; - pSetup->pllpdec = s_PllSetupCacheStruct[i].pllpdec; - pSetup->pllsscg[0] = s_PllSetupCacheStruct[i].pllsscg[0]; - pSetup->pllsscg[1] = s_PllSetupCacheStruct[i].pllsscg[1]; - retErr = kStatus_PLL_Success; - break; - } - } - - if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - { - return retErr; - } -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - - retErr = CLOCK_GetPll0ConfigInternal(finHz, foutHz, pSetup, useSS); - -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - /* Cache the most recent calulation result into buffer. */ - s_FinHzCache[s_PllSetupCacheIdx] = finHz; - s_FoutHzCache[s_PllSetupCacheIdx] = foutHz; - s_UseSSCache[s_PllSetupCacheIdx] = useSS; - - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndec = pSetup->pllndec; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdec = pSetup->pllpdec; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[0] = pSetup->pllsscg[0]; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[1] = pSetup->pllsscg[1]; - /* Update the index for next available buffer. */ - s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - - return retErr; -} - -/* Update local PLL rate variable */ -static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup) -{ - s_Pll0_Freq = CLOCK_GetPLL0OutFromSetup(pSetup); -} - -/* Update local PLL1 rate variable */ -static void CLOCK_GetPLL1OutFromSetupUpdate(pll_setup_t *pSetup) -{ - s_Pll1_Freq = CLOCK_GetPLL1OutFromSetup(pSetup); -} - -/* Return System PLL input clock rate */ -/*! brief Return PLL0 input clock rate - * return PLL0 input clock rate - */ -uint32_t CLOCK_GetPLL0InClockRate(void) -{ - uint32_t clkRate = 0U; - - switch ((SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK)) - { - case 0x00U: - clkRate = CLK_FRO_12MHZ; - break; - - case 0x01U: - clkRate = CLOCK_GetExtClkFreq(); - break; - - case 0x02U: - clkRate = CLOCK_GetFro1MFreq(); - break; - - case 0x03U: - clkRate = CLOCK_GetOsc32KFreq(); - break; - - default: - clkRate = 0U; - break; - } - - return clkRate; -} - -/* Return PLL1 input clock rate */ -uint32_t CLOCK_GetPLL1InClockRate(void) -{ - uint32_t clkRate = 0U; - - switch ((SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK)) - { - case 0x00U: - clkRate = CLK_FRO_12MHZ; - break; - - case 0x01U: - clkRate = CLOCK_GetExtClkFreq(); - break; - - case 0x02U: - clkRate = CLOCK_GetFro1MFreq(); - break; - - case 0x03U: - clkRate = CLOCK_GetOsc32KFreq(); - break; - - default: - clkRate = 0U; - break; - } - - return clkRate; -} - -/* Return PLL0 output clock rate from setup structure */ -/*! brief Return PLL0 output clock rate from setup structure - * param pSetup : Pointer to a PLL setup structure - * return PLL0 output clock rate the setup structure will generate - */ -uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup) -{ - uint32_t clkRate = 0; - uint32_t prediv, postdiv; - float workRate = 0.0F; - - /* Get the input clock frequency of PLL. */ - clkRate = CLOCK_GetPLL0InClockRate(); - - if (((pSetup->pllctrl & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && - ((pSetup->pllctrl & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && - ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && - ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) - { - prediv = findPll0PreDiv(); - postdiv = findPll0PostDiv(); - /* Adjust input clock */ - clkRate = clkRate / prediv; - /* MDEC used for rate */ - workRate = (float)clkRate * (float)findPll0MMult(); - workRate /= (float)postdiv; - } - - return (uint32_t)workRate; -} - -/* Return PLL1 output clock rate from setup structure */ -/*! brief Return PLL1 output clock rate from setup structure - * param pSetup : Pointer to a PLL setup structure - * return PLL0 output clock rate the setup structure will generate - */ -uint32_t CLOCK_GetPLL1OutFromSetup(pll_setup_t *pSetup) -{ - uint32_t clkRate = 0; - uint32_t prediv, postdiv; - uint32_t workRate = 0UL; - - /* Get the input clock frequency of PLL. */ - clkRate = CLOCK_GetPLL1InClockRate(); - - if (((pSetup->pllctrl & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0UL) && - ((pSetup->pllctrl & SYSCON_PLL1CTRL_CLKEN_MASK) != 0UL) && - ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0UL)) - { - prediv = findPll1PreDiv(); - postdiv = findPll1PostDiv(); - /* Adjust input clock */ - clkRate = clkRate / prediv; - /* MDEC used for rate */ - workRate = clkRate * findPll1MMult(); - workRate /= postdiv; - } - - return workRate; -} - -/* Set the current PLL0 Rate */ -/*! brief Store the current PLL rate - * param rate: Current rate of the PLL - * return Nothing - **/ -void CLOCK_SetStoredPLL0ClockRate(uint32_t rate) -{ - s_Pll0_Freq = rate; -} - -/* Return PLL0 output clock rate */ -/*! brief Return PLL0 output clock rate - * param recompute : Forces a PLL rate recomputation if true - * return PLL0 output clock rate - * note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetPLL0OutClockRate(bool recompute) -{ - pll_setup_t Setup; - uint32_t rate; - - if ((recompute) || (s_Pll0_Freq == 0U)) - { - Setup.pllctrl = SYSCON->PLL0CTRL; - Setup.pllndec = SYSCON->PLL0NDEC; - Setup.pllpdec = SYSCON->PLL0PDEC; - Setup.pllsscg[0] = SYSCON->PLL0SSCG0; - Setup.pllsscg[1] = SYSCON->PLL0SSCG1; - - CLOCK_GetPLL0OutFromSetupUpdate(&Setup); - } - - rate = s_Pll0_Freq; - - return rate; -} - -/*! brief Return PLL1 output clock rate - * param recompute : Forces a PLL rate recomputation if true - * return PLL1 output clock rate - * note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetPLL1OutClockRate(bool recompute) -{ - pll_setup_t Setup; - uint32_t rate; - - if ((recompute) || (s_Pll1_Freq == 0U)) - { - Setup.pllctrl = SYSCON->PLL1CTRL; - Setup.pllndec = SYSCON->PLL1NDEC; - Setup.pllpdec = SYSCON->PLL1PDEC; - Setup.pllmdec = SYSCON->PLL1MDEC; - CLOCK_GetPLL1OutFromSetupUpdate(&Setup); - } - - rate = s_Pll1_Freq; - - return rate; -} - -/* Set PLL0 output based on the passed PLL setup data */ -/*! brief Set PLL output based on the passed PLL setup data - * param pControl : Pointer to populated PLL control structure to generate setup with - * param pSetup : Pointer to PLL setup structure to be filled - * return PLL_ERROR_SUCCESS on success, or PLL setup error code - * note Actual frequency for setup may vary from the desired frequency based on the - * accuracy of input clocks, rounding, non-fractional PLL mode, etc. - */ -pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup) -{ - uint32_t inRate; - bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0UL); - - pll_error_t pllError; - - /* Determine input rate for the PLL */ - if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0UL) - { - inRate = pControl->inputRate; - } - else - { - inRate = CLOCK_GetPLL0InClockRate(); - } - - /* PLL flag options */ - pllError = CLOCK_GetPll0Config(inRate, pControl->desiredRate, pSetup, useSS); - if ((useSS) && (pllError == kStatus_PLL_Success)) - { - /* If using SS mode, then some tweaks are made to the generated setup */ - pSetup->pllsscg[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc; - if (pControl->mfDither) - { - pSetup->pllsscg[1] |= (1UL << SYSCON_PLL0SSCG1_DITHER_SHIFT); - } - } - - return pllError; -} - -/* Set PLL0 output from PLL setup structure */ -/*! brief Set PLL output from PLL setup structure (precise frequency) - * param pSetup : Pointer to populated PLL setup structure - * param flagcfg : Flag configuration for PLL config structure - * return PLL_ERROR_SUCCESS on success, or PLL setup error code - * note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg) -{ - uint32_t inRate, clkRate, prediv; - - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_PLL0); - POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); - - pSetup->flags = flagcfg; - - /* Write PLL setup data */ - SYSCON->PLL0CTRL = pSetup->pllctrl; - SYSCON->PLL0NDEC = pSetup->pllndec; - SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ - SYSCON->PLL0PDEC = pSetup->pllpdec; - SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ - SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; - SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; - SYSCON->PLL0SSCG1 = - pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT); /* latch */ - - POWER_DisablePD(kPDRUNCFG_PD_PLL0); - POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); - - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0UL) - { - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ - { - inRate = CLOCK_GetPLL0InClockRate(); - prediv = findPll0PreDiv(); - /* Adjust input clock */ - clkRate = inRate / prediv; - /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ - if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) - { - while (CLOCK_IsPLL0Locked() == false) - { - } - } - else - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval - to insure the PLL will be stable */ - } - } - else /* spread spectrum mode */ - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to - insure the PLL will be stable */ - } - } - - /* Update current programmed PLL rate var */ - CLOCK_GetPLL0OutFromSetupUpdate(pSetup); - - /* System voltage adjustment, occurs prior to setting main system clock */ - if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0UL) - { - POWER_SetVoltageForFreq(s_Pll0_Freq); - } - - return kStatus_PLL_Success; -} - -/* Setup PLL Frequency from pre-calculated value */ -/** - * brief Set PLL0 output from PLL setup structure (precise frequency) - * param pSetup : Pointer to populated PLL setup structure - * return kStatus_PLL_Success on success, or PLL setup error code - * note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup) -{ - uint32_t inRate, clkRate, prediv; - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_PLL0); - POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); - - /* Write PLL setup data */ - SYSCON->PLL0CTRL = pSetup->pllctrl; - SYSCON->PLL0NDEC = pSetup->pllndec; - SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ - SYSCON->PLL0PDEC = pSetup->pllpdec; - SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ - SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; - SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; - SYSCON->PLL0SSCG1 = - pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* latch */ - - POWER_DisablePD(kPDRUNCFG_PD_PLL0); - POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); - - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0UL) - { - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ - { - inRate = CLOCK_GetPLL0InClockRate(); - prediv = findPll0PreDiv(); - /* Adjust input clock */ - clkRate = inRate / prediv; - /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ - if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) - { - while (CLOCK_IsPLL0Locked() == false) - { - } - } - else - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval - to insure the PLL will be stable */ - } - } - else /* spread spectrum mode */ - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to - insure the PLL will be stable */ - } - } - - /* Update current programmed PLL rate var */ - s_Pll0_Freq = pSetup->pllRate; - - return kStatus_PLL_Success; -} - -/* Setup PLL1 Frequency from pre-calculated value */ -/** - * brief Set PLL1 output from PLL setup structure (precise frequency) - * param pSetup : Pointer to populated PLL setup structure - * return kStatus_PLL_Success on success, or PLL setup error code - * note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup) -{ - uint32_t inRate, clkRate, prediv; - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_PLL1); - - /* Write PLL setup data */ - SYSCON->PLL1CTRL = pSetup->pllctrl; - SYSCON->PLL1NDEC = pSetup->pllndec; - SYSCON->PLL1NDEC = pSetup->pllndec | (1UL << SYSCON_PLL1NDEC_NREQ_SHIFT); /* latch */ - SYSCON->PLL1PDEC = pSetup->pllpdec; - SYSCON->PLL1PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL1PDEC_PREQ_SHIFT); /* latch */ - SYSCON->PLL1MDEC = pSetup->pllmdec; - SYSCON->PLL1MDEC = pSetup->pllmdec | (1UL << SYSCON_PLL1MDEC_MREQ_SHIFT); /* latch */ - - POWER_DisablePD(kPDRUNCFG_PD_PLL1); - - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0UL) - { - inRate = CLOCK_GetPLL1InClockRate(); - prediv = findPll1PreDiv(); - /* Adjust input clock */ - clkRate = inRate / prediv; - /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ - if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) - { - while (CLOCK_IsPLL1Locked() == false) - { - } - } - else - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to - insure the PLL will be stable */ - } - } - - /* Update current programmed PLL rate var */ - s_Pll1_Freq = pSetup->pllRate; - - return kStatus_PLL_Success; -} - -/* Set PLL0 clock based on the input frequency and multiplier */ -/*! brief Set PLL0 output based on the multiplier and input frequency - * param multiply_by : multiplier - * param input_freq : Clock input frequency of the PLL - * return Nothing - * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this - * function does not disable or enable PLL power, wait for PLL lock, - * or adjust system voltages. These must be done in the application. - * The function will not alter any source clocks (ie, main systen clock) - * that may use the PLL, so these should be setup prior to and after - * exiting the function. - */ -void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq) -{ - uint32_t cco_freq = input_freq * multiply_by; - uint32_t pdec = 1U; - uint32_t selr; - uint32_t seli; - uint32_t selp; - uint32_t mdec, ndec; - - while (cco_freq < 275000000U) - { - multiply_by <<= 1U; /* double value in each iteration */ - pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */ - cco_freq = input_freq * multiply_by; - } - - selr = 0U; - - if (multiply_by >= 8000UL) - { - seli = 1UL; - } - else if (multiply_by >= 122UL) - { - seli = (uint32_t)(8000UL / multiply_by); /*floor(8000/M) */ - } - else - { - seli = 2UL * ((uint32_t)(multiply_by / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ - } - - if (seli >= 63U) - { - seli = 63U; - } - - { - selp = 31U; - } - - if (pdec > 1U) - { - pdec = pdec / 2U; /* Account for minus 1 encoding */ - /* Translate P value */ - } - - mdec = (uint32_t)PLL_SSCG1_MDEC_VAL_SET(multiply_by); - ndec = 0x1U; /* pre divide by 1 (hardcoded) */ - - SYSCON->PLL0CTRL = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_BYPASSPOSTDIV(0) | - SYSCON_PLL0CTRL_BYPASSPOSTDIV2(0) | (selr << SYSCON_PLL0CTRL_SELR_SHIFT) | - (seli << SYSCON_PLL0CTRL_SELI_SHIFT) | (selp << SYSCON_PLL0CTRL_SELP_SHIFT); - SYSCON->PLL0PDEC = pdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* set Pdec value and assert preq */ - SYSCON->PLL0NDEC = ndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* set Pdec value and assert preq */ - SYSCON->PLL0SSCG1 = - mdec | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* select non sscg MDEC value, assert mreq and select mdec value */ -} - -/*! @brief Enable the OSTIMER 32k clock. - * @return Nothing - */ -void CLOCK_EnableOstimer32kClock(void) -{ - PMC->OSTIMERr |= PMC_OSTIMER_CLOCKENABLE_MASK; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_clock.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_clock.h deleted file mode 100644 index bd0bb127edc..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_clock.h +++ /dev/null @@ -1,1385 +0,0 @@ -/* - * Copyright 2017 - 2021 , NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CLOCK_H_ -#define _FSL_CLOCK_H_ - -#include "fsl_common.h" - -/*! @addtogroup clock */ -/*! @{ */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CLOCK driver version 2.3.6. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 6)) -/*@}*/ - -/*! @brief Configure whether driver controls clock - * - * When set to 0, peripheral drivers will enable clock in initialize function - * and disable clock in de-initialize function. When set to 1, peripheral - * driver will not control the clock, application could control the clock out of - * the driver. - * - * @note All drivers share this feature switcher. If it is set to 1, application - * should handle clock enable and disable for all drivers. - */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) -#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 -#endif - -/*! - * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. - * - * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function - * would cache the recent calulation and accelerate the execution to get the - * right settings. - */ -#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT -#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U -#endif - -/* Definition for delay API in clock driver, users can redefine it to the real application. */ -#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY -#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (100000000UL) -#endif - -/*! @brief Clock ip name array for ROM. */ -#define ROM_CLOCKS \ - { \ - kCLOCK_Rom \ - } -/*! @brief Clock ip name array for SRAM. */ -#define SRAM_CLOCKS \ - { \ - kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3 \ - } -/*! @brief Clock ip name array for FLASH. */ -#define FLASH_CLOCKS \ - { \ - kCLOCK_Flash \ - } -/*! @brief Clock ip name array for FMC. */ -#define FMC_CLOCKS \ - { \ - kCLOCK_Fmc \ - } -/*! @brief Clock ip name array for INPUTMUX. */ -#define INPUTMUX_CLOCKS \ - { \ - kCLOCK_InputMux0 \ - } -/*! @brief Clock ip name array for IOCON. */ -#define IOCON_CLOCKS \ - { \ - kCLOCK_Iocon \ - } -/*! @brief Clock ip name array for GPIO. */ -#define GPIO_CLOCKS \ - { \ - kCLOCK_Gpio0, kCLOCK_Gpio1 \ - } -/*! @brief Clock ip name array for PINT. */ -#define PINT_CLOCKS \ - { \ - kCLOCK_Pint \ - } -/*! @brief Clock ip name array for GINT. */ -#define GINT_CLOCKS \ - { \ - kCLOCK_Gint, kCLOCK_Gint \ - } -/*! @brief Clock ip name array for DMA. */ -#define DMA_CLOCKS \ - { \ - kCLOCK_Dma0, kCLOCK_Dma1 \ - } -/*! @brief Clock ip name array for CRC. */ -#define CRC_CLOCKS \ - { \ - kCLOCK_Crc \ - } -/*! @brief Clock ip name array for WWDT. */ -#define WWDT_CLOCKS \ - { \ - kCLOCK_Wwdt \ - } -/*! @brief Clock ip name array for RTC. */ -#define RTC_CLOCKS \ - { \ - kCLOCK_Rtc \ - } -/*! @brief Clock ip name array for Mailbox. */ -#define MAILBOX_CLOCKS \ - { \ - kCLOCK_Mailbox \ - } -/*! @brief Clock ip name array for LPADC. */ -#define LPADC_CLOCKS \ - { \ - kCLOCK_Adc0 \ - } -/*! @brief Clock ip name array for MRT. */ -#define MRT_CLOCKS \ - { \ - kCLOCK_Mrt \ - } -/*! @brief Clock ip name array for OSTIMER. */ -#define OSTIMER_CLOCKS \ - { \ - kCLOCK_OsTimer0 \ - } -/*! @brief Clock ip name array for SCT0. */ -#define SCT_CLOCKS \ - { \ - kCLOCK_Sct0 \ - } -/*! @brief Clock ip name array for MCAN. */ -#define MCAN_CLOCKS \ - { \ - kCLOCK_Mcan \ - } -/*! @brief Clock ip name array for UTICK. */ -#define UTICK_CLOCKS \ - { \ - kCLOCK_Utick0 \ - } -/*! @brief Clock ip name array for FLEXCOMM. */ -#define FLEXCOMM_CLOCKS \ - { \ - kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \ - kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi \ - } -/*! @brief Clock ip name array for LPUART. */ -#define LPUART_CLOCKS \ - { \ - kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \ - kCLOCK_MinUart6, kCLOCK_MinUart7 \ - } - -/*! @brief Clock ip name array for BI2C. */ -#define BI2C_CLOCKS \ - { \ - kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \ - } -/*! @brief Clock ip name array for LSPI. */ -#define LPSPI_CLOCKS \ - { \ - kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \ - } -/*! @brief Clock ip name array for FLEXI2S. */ -#define FLEXI2S_CLOCKS \ - { \ - kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \ - kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \ - } -/*! @brief Clock ip name array for CTIMER. */ -#define CTIMER_CLOCKS \ - { \ - kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ - } -/*! @brief Clock ip name array for COMP */ -#define COMP_CLOCKS \ - { \ - kCLOCK_Comp \ - } -/*! @brief Clock ip name array for FREQME. */ -#define FREQME_CLOCKS \ - { \ - kCLOCK_Freqme \ - } -/*! @brief Clock ip name array for CDOG. */ -#define CDOG_CLOCKS \ - { \ - kCLOCK_Cdog \ - } -/*! @brief Clock ip name array for RNG. */ -#define RNG_CLOCKS \ - { \ - kCLOCK_Rng \ - } -/*! @brief Clock ip name array for HashCrypt. */ -#define HASHCRYPT_CLOCKS \ - { \ - kCLOCK_HashCrypt \ - } -/*! @brief Clock ip name array for PLULUT. */ -#define PLULUT_CLOCKS \ - { \ - kCLOCK_PluLut \ - } -/*! @brief Clock ip name array for PUF. */ -#define PUF_CLOCKS \ - { \ - kCLOCK_Puf \ - } -/*! @brief Clock ip name array for CASPER. */ -#define CASPER_CLOCKS \ - { \ - kCLOCK_Casper \ - } -/*! @brief Clock ip name array for ANALOGCTRL. */ -#define ANALOGCTRL_CLOCKS \ - { \ - kCLOCK_AnalogCtrl \ - } -/*! @brief Clock ip name array for HS_LSPI. */ -#define HS_LSPI_CLOCKS \ - { \ - kCLOCK_Hs_Lspi \ - } -/*! @brief Clock ip name array for GPIO_SEC. */ -#define GPIO_SEC_CLOCKS \ - { \ - kCLOCK_Gpio_Sec \ - } -/*! @brief Clock ip name array for GPIO_SEC_INT. */ -#define GPIO_SEC_INT_CLOCKS \ - { \ - kCLOCK_Gpio_Sec_Int \ - } -#define PLU_CLOCKS \ - { \ - kCLOCK_PluLut \ - } -#define SYSCTL_CLOCKS \ - { \ - kCLOCK_Sysctl \ - } -/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ -/*------------------------------------------------------------------------------ - clock_ip_name_t definition: -------------------------------------------------------------------------------*/ - -#define CLK_GATE_REG_OFFSET_SHIFT 8U -#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U -#define CLK_GATE_BIT_SHIFT_SHIFT 0U -#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU - -#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ - ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ - (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) - -#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) -#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) - -#define AHB_CLK_CTRL0 0 -#define AHB_CLK_CTRL1 1 -#define AHB_CLK_CTRL2 2 - -/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ -typedef enum _clock_ip_name -{ - kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */ - kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /*!< Clock gate name: Rom. */ - - kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /*!< Clock gate name: Sram1. */ - - kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /*!< Clock gate name: Sram2. */ - - kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /*!< Clock gate name: Flash. */ - - kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /*!< Clock gate name: Fmc. */ - - kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /*!< Clock gate name: InputMux. */ - - kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Iocon. */ - - kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Gpio0. */ - - kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Gpio1. */ - - kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), /*!< Clock gate name: Pint. */ - - kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gint. */ - - kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Dma0. */ - - kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Crc. */ - - kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Wwdt. */ - - kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Rtc. */ - - kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), /*!< Clock gate name: Mailbox. */ - - kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), /*!< Clock gate name: Adc0. */ - - kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), /*!< Clock gate name: Mrt. */ - - kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), /*!< Clock gate name: OsTimer0. */ - - kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), /*!< Clock gate name: Sct0. */ - - kCLOCK_Mcan = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7), /*!< Clock gate name: Mcan. */ - - kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), /*!< Clock gate name: Utick0. */ - - kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexComm0. */ - - kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexComm1. */ - - kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexComm2. */ - - kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexComm3. */ - - kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexComm4. */ - - kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexComm5. */ - - kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexComm6. */ - - kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexComm7. */ - - kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: MinUart0. */ - - kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: MinUart1. */ - - kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: MinUart2. */ - - kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: MinUart3. */ - - kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: MinUart4. */ - - kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: MinUart5. */ - - kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: MinUart6. */ - - kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: MinUart7. */ - - kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LSpi0. */ - - kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LSpi1. */ - - kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LSpi2. */ - - kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LSpi3. */ - - kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LSpi4. */ - - kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LSpi5. */ - - kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LSpi6. */ - - kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LSpi7. */ - - kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: BI2c0. */ - - kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: BI2c1. */ - - kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: BI2c2. */ - - kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: BI2c3. */ - - kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: BI2c4. */ - - kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: BI2c5. */ - - kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: BI2c6. */ - - kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: BI2c7. */ - - kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexI2s0. */ - - kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexI2s1. */ - - kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexI2s2. */ - - kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexI2s3. */ - - kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexI2s4. */ - - kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexI2s5. */ - - kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexI2s6. */ - - kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexI2s7. */ - - kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), /*!< Clock gate name: Timer2. */ - - kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), /*!< Clock gate name: Timer0. */ - - kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), /*!< Clock gate name: Timer1. */ - - kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), /*!< Clock gate name: Dma1. */ - - kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), /*!< Clock gate name: Comp. */ - - kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), /*!< Clock gate name: Sram3. */ - - kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), /*!< Clock gate name: Freqme. */ - - kCLOCK_Cdog = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11), /*!< Clock gate name: Cdog. */ - - kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), /*!< Clock gate name: Rng. */ - - kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: Sysctl. */ - - kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), /*!< Clock gate name: HashCrypt. */ - - kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), /*!< Clock gate name: PluLut. */ - - kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), /*!< Clock gate name: Timer3. */ - - kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), /*!< Clock gate name: Timer4. */ - - kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), /*!< Clock gate name: Puf. */ - - kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), /*!< Clock gate name: Casper. */ - - kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27), /*!< Clock gate name: AnalogCtrl. */ - - kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28), /*!< Clock gate name: Lspi. */ - - kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), /*!< Clock gate name: GPIO Sec. */ - - kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30) /*!< Clock gate name: Gpio Sec Int */ -} clock_ip_name_t; - -/*! @brief Peripherals clock source definition. */ -#define BUS_CLK kCLOCK_BusClk - -#define I2C0_CLK_SRC BUS_CLK - -/*! @brief Clock name used to get clock frequency. */ -typedef enum _clock_name -{ - kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ - kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ - kCLOCK_ClockOut, /*!< CLOCKOUT */ - kCLOCK_FroHf, /*!< FRO48/96 */ - kCLOCK_Pll1Out, /*!< PLL1 Output */ - kCLOCK_Mclk, /*!< MCLK */ - kCLOCK_Fro12M, /*!< FRO12M */ - kCLOCK_Fro1M, /*!< FRO1M */ - kCLOCK_ExtClk, /*!< External Clock */ - kCLOCK_Pll0Out, /*!< PLL0 Output */ - kCLOCK_FlexI2S, /*!< FlexI2S clock */ - -} clock_name_t; - -/*! @brief Clock Mux Switches - * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable - * starting from LSB upwards - * - * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* - * - */ - -#define CLK_ATTACH_ID(mux, sel, pos) \ - ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((uint32_t)(pos)*12U)) -#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U) -#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U)) - -#define GET_ID_ITEM(connection) ((connection)&0xFFFU) -#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U) -#define GET_ID_ITEM_MUX(connection) (((uint8_t)connection) & 0xFFU) -#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF00U) >> 8U) - 1U)) -#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) - -#define CM_SYSTICKCLKSEL0 0 -#define CM_TRACECLKSEL 2 -#define CM_CTIMERCLKSEL0 3 -#define CM_CTIMERCLKSEL1 4 -#define CM_CTIMERCLKSEL2 5 -#define CM_CTIMERCLKSEL3 6 -#define CM_CTIMERCLKSEL4 7 -#define CM_MAINCLKSELA 8 -#define CM_MAINCLKSELB 9 -#define CM_CLKOUTCLKSEL 10 -#define CM_PLL0CLKSEL 12 -#define CM_PLL1CLKSEL 13 -#define CM_MCANCLKSEL 16 -#define CM_ADCASYNCCLKSEL 17 -#define CM_CLK32KCLKSEL 19 -#define CM_FXCOMCLKSEL0 20 -#define CM_FXCOMCLKSEL1 21 -#define CM_FXCOMCLKSEL2 22 -#define CM_FXCOMCLKSEL3 23 -#define CM_FXCOMCLKSEL4 24 -#define CM_FXCOMCLKSEL5 25 -#define CM_FXCOMCLKSEL6 26 -#define CM_FXCOMCLKSEL7 27 -#define CM_HSLSPICLKSEL 28 -#define CM_MCLKCLKSEL 32 -#define CM_SCTCLKSEL 36 - -#define CM_OSTIMERCLKSEL (62U) -#define CM_RTCOSC32KCLKSEL 63U - -/*! - * @brief The enumerator of clock attach Id. - */ -typedef enum _clock_attach_id -{ - - kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO12M to MAIN_CLK. */ - - kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach EXT_CLK to MAIN_CLK. */ - - kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO1M to MAIN_CLK. */ - - kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO_HF to MAIN_CLK. */ - - kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0), /*!< Attach PLL0 to MAIN_CLK. */ - - kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), /*!< Attach PLL1 to MAIN_CLK. */ - - kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), /*!< Attach OSC32K to MAIN_CLK. */ - - kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Attach MAIN_CLK to CLKOUT. */ - - kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Attach PLL0 to CLKOUT. */ - - kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Attach EXT_CLK to CLKOUT. */ - - kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Attach FRO_HF to CLKOUT. */ - - kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Attach FRO1M to CLKOUT. */ - - kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Attach PLL1 to CLKOUT. */ - - kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Attach OSC32K to CLKOUT. */ - - kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< Attach NONE to SYS_CLKOUT. */ - - kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0), /*!< Attach FRO12M to PLL0. */ - - kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1), /*!< Attach EXT_CLK to PLL0. */ - - kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2), /*!< Attach FRO1M to PLL0. */ - - kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3), /*!< Attach OSC32K to PLL0. */ - - kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7), /*!< Attach NONE to PLL0. */ - - kMCAN_DIV_to_MCAN = MUX_A(CM_MCANCLKSEL, 0), /*!< Attach MCAN_DIV to MCAN. */ - - kFRO1M_to_MCAN = MUX_A(CM_MCANCLKSEL, 1), /*!< Attach FRO1M to MCAN. */ - - kOSC32K_to_MCAN = MUX_A(CM_MCANCLKSEL, 2), /*!< Attach OSC32K to MCAN. */ - - kNONE_to_MCAN = MUX_A(CM_MCANCLKSEL, 7), /*!< Attach NONE to MCAN. */ - - kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), /*!< Attach MAIN_CLK to ADC_CLK. */ - - kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), /*!< Attach PLL0 to ADC_CLK. */ - - kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), /*!< Attach FRO_HF to ADC_CLK. */ - - kEXT_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 4), /*!< Attach EXT_CLK to ADC_CLK. */ - - kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), /*!< Attach NONE to ADC_CLK. */ - - kOSC32K_to_CLK32K = MUX_A(CM_CLK32KCLKSEL, 0), /*!< Attach OSC32K to CLK32K. */ - - kFRO1MDIV_to_CLK32K = MUX_A(CM_CLK32KCLKSEL, 1), /*!< Attach FRO1MDIV to CLK32K. */ - - kNONE_to_CLK32K = MUX_A(CM_CLK32KCLKSEL, 7), /*!< Attach NONE to CLK32K. */ - - kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), /*!< Attach MAIN_CLK to FLEXCOMM0. */ - - kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), /*!< Attach PLL0_DIV to FLEXCOMM0. */ - - kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), /*!< Attach FRO12M to FLEXCOMM0. */ - - kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM0. */ - - kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), /*!< Attach FRO1M to FLEXCOMM0. */ - - kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5), /*!< Attach MCLK to FLEXCOMM0. */ - - kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6), /*!< Attach OSC32K to FLEXCOMM0. */ - - kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */ - - kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), /*!< Attach MAIN_CLK to FLEXCOMM1. */ - - kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), /*!< Attach PLL0_DIV to FLEXCOMM1. */ - - kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), /*!< Attach FRO12M to FLEXCOMM1. */ - - kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM1. */ - - kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), /*!< Attach FRO1M to FLEXCOMM1. */ - - kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5), /*!< Attach MCLK to FLEXCOMM1. */ - - kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6), /*!< Attach OSC32K to FLEXCOMM1. */ - - kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */ - - kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), /*!< Attach MAIN_CLK to FLEXCOMM2. */ - - kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), /*!< Attach PLL0_DIV to FLEXCOMM2. */ - - kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), /*!< Attach FRO12M to FLEXCOMM2. */ - - kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM2. */ - - kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), /*!< Attach FRO1M to FLEXCOMM2. */ - - kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5), /*!< Attach MCLK to FLEXCOMM2. */ - - kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6), /*!< Attach OSC32K to FLEXCOMM2. */ - - kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */ - - kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), /*!< Attach MAIN_CLK to FLEXCOMM3. */ - - kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), /*!< Attach PLL0_DIV to FLEXCOMM3. */ - - kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), /*!< Attach FRO12M to FLEXCOMM3. */ - - kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM3. */ - - kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), /*!< Attach FRO1M to FLEXCOMM3. */ - - kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5), /*!< Attach MCLK to FLEXCOMM3. */ - - kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6), /*!< Attach OSC32K to FLEXCOMM3. */ - - kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */ - - kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), /*!< Attach MAIN_CLK to FLEXCOMM4. */ - - kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), /*!< Attach PLL0_DIV to FLEXCOMM4. */ - - kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), /*!< Attach FRO12M to FLEXCOMM4. */ - - kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM4. */ - - kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), /*!< Attach FRO1M to FLEXCOMM4. */ - - kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5), /*!< Attach MCLK to FLEXCOMM4. */ - - kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6), /*!< Attach OSC32K to FLEXCOMM4. */ - - kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */ - - kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), /*!< Attach MAIN_CLK to FLEXCOMM5. */ - - kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), /*!< Attach PLL0_DIV to FLEXCOMM5. */ - - kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), /*!< Attach FRO12M to FLEXCOMM5. */ - - kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM5. */ - - kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), /*!< Attach FRO1M to FLEXCOMM5. */ - - kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5), /*!< Attach MCLK to FLEXCOMM5. */ - - kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6), /*!< Attach OSC32K to FLEXCOMM5. */ - - kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */ - - kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), /*!< Attach MAIN_CLK to FLEXCOMM6. */ - - kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), /*!< Attach PLL0_DIV to FLEXCOMM6. */ - - kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), /*!< Attach FRO12M to FLEXCOMM6. */ - - kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM6. */ - - kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), /*!< Attach FRO1M to FLEXCOMM6. */ - - kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5), /*!< Attach MCLK to FLEXCOMM6. */ - - kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6), /*!< Attach OSC32K to FLEXCOMM6. */ - - kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */ - - kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), /*!< Attach MAIN_CLK to FLEXCOMM7. */ - - kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), /*!< Attach PLL0_DIV to FLEXCOMM7. */ - - kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), /*!< Attach FRO12M to FLEXCOMM7. */ - - kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM7. */ - - kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), /*!< Attach FRO1M to FLEXCOMM7. */ - - kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5), /*!< Attach MCLK to FLEXCOMM7. */ - - kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6), /*!< Attach OSC32K to FLEXCOMM7. */ - - kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */ - - kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0), /*!< Attach MAIN_CLK to HSLSPI. */ - - kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1), /*!< Attach PLL0_DIV to HSLSPI. */ - - kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2), /*!< Attach FRO12M to HSLSPI. */ - - kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3), /*!< Attach FRO_HF_DIV to HSLSPI. */ - - kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4), /*!< Attach FRO1M to HSLSPI. */ - - kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6), /*!< Attach OSC32K to HSLSPI. */ - - kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7), /*!< Attach NONE to HSLSPI. */ - - kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), /*!< Attach FRO_HF to MCLK. */ - - kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), /*!< Attach PLL0 to MCLK. */ - - kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), /*!< Attach NONE to MCLK. */ - - kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), /*!< Attach MAIN_CLK to SCT_CLK. */ - - kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), /*!< Attach PLL0 to SCT_CLK. */ - - kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), /*!< Attach EXT_CLK to SCT_CLK. */ - - kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), /*!< Attach FRO_HF to SCT_CLK. */ - - kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5), /*!< Attach MCLK to SCT_CLK. */ - - kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), /*!< Attach NONE to SCT_CLK. */ - - kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0), /*!< Attach FRO32K to OSC32K. */ - - kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1), /*!< Attach XTAL32K to OSC32K. */ - - kOSC32K_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 0), /*!< Attach OSC32K to OSTIMER. */ - - kFRO1M_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 1), /*!< Attach FRO1M to OSTIMER. */ - - kMAIN_CLK_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 2), /*!< Attach MAIN_CLK to OSTIMER. */ - - kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), /*!< Attach TRACE_DIV to TRACE. */ - - kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), /*!< Attach FRO1M to TRACE. */ - - kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), /*!< Attach OSC32K to TRACE. */ - - kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), /*!< Attach NONE to TRACE. */ - - kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), /*!< Attach SYSTICK_DIV0 to SYSTICK0. */ - - kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), /*!< Attach FRO1M to SYSTICK0. */ - - kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), /*!< Attach OSC32K to SYSTICK0. */ - - kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), /*!< Attach NONE to SYSTICK0. */ - - kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0), /*!< Attach FRO12M to PLL1. */ - - kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1), /*!< Attach EXT_CLK to PLL1. */ - - kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2), /*!< Attach FRO1M to PLL1. */ - - kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3), /*!< Attach OSC32K to PLL1. */ - - kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7), /*!< Attach NONE to PLL1. */ - - kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), /*!< Attach MAIN_CLK to CTIMER0. */ - - kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), /*!< Attach PLL0 to CTIMER0. */ - - kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), /*!< Attach FRO_HF to CTIMER0. */ - - kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), /*!< Attach FRO1M to CTIMER0. */ - - kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), /*!< Attach MCLK to CTIMER0. */ - - kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), /*!< Attach OSC32K to CTIMER0. */ - - kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7), /*!< Attach NONE to CTIMER0. */ - - kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), /*!< Attach MAIN_CLK to CTIMER1. */ - - kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), /*!< Attach PLL0 to CTIMER1. */ - - kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), /*!< Attach FRO_HF to CTIMER1. */ - - kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), /*!< Attach FRO1M to CTIMER1. */ - - kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), /*!< Attach MCLK to CTIMER1. */ - - kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), /*!< Attach OSC32K to CTIMER1. */ - - kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7), /*!< Attach NONE to CTIMER1. */ - - kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), /*!< Attach MAIN_CLK to CTIMER2. */ - - kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), /*!< Attach PLL0 to CTIMER2. */ - - kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), /*!< Attach FRO_HF to CTIMER2. */ - - kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), /*!< Attach FRO1M to CTIMER2. */ - - kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), /*!< Attach MCLK to CTIMER2. */ - - kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), /*!< Attach OSC32K to CTIMER2. */ - - kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7), /*!< Attach NONE to CTIMER2. */ - - kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), /*!< Attach MAIN_CLK to CTIMER3. */ - - kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), /*!< Attach PLL0 to CTIMER3. */ - - kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), /*!< Attach FRO_HF to CTIMER3. */ - - kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), /*!< Attach FRO1M to CTIMER3. */ - - kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), /*!< Attach MCLK to CTIMER3. */ - - kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), /*!< Attach OSC32K to CTIMER3. */ - - kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7), /*!< Attach NONE to CTIMER3. */ - - kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), /*!< Attach MAIN_CLK to CTIMER4. */ - - kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), /*!< Attach PLL0 to CTIMER4. */ - - kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), /*!< Attach FRO_HF to CTIMER4. */ - - kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), /*!< Attach FRO1M to CTIMER4. */ - - kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), /*!< Attach MCLK to CTIMER4. */ - - kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), /*!< Attach OSC32K to CTIMER4. */ - - kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7), /*!< Attach NONE to CTIMER4. */ - - kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */ - -} clock_attach_id_t; - -/*! @brief Clock dividers */ -typedef enum _clock_div_name -{ - kCLOCK_DivSystickClk0 = 0, /*!< Systick Clk0 Divider. */ - - kCLOCK_DivArmTrClkDiv = 2, /*!< Arm Tr Clk Div Divider. */ - - kCLOCK_DivCanClk = 3, /*!< Can Clock Divider. */ - - kCLOCK_DivFlexFrg0 = 8, /*!< Flex Frg0 Divider. */ - - kCLOCK_DivFlexFrg1 = 9, /*!< Flex Frg1 Divider. */ - - kCLOCK_DivFlexFrg2 = 10, /*!< Flex Frg2 Divider. */ - - kCLOCK_DivFlexFrg3 = 11, /*!< Flex Frg3 Divider. */ - - kCLOCK_DivFlexFrg4 = 12, /*!< Flex Frg4 Divider. */ - - kCLOCK_DivFlexFrg5 = 13, /*!< Flex Frg5 Divider. */ - - kCLOCK_DivFlexFrg6 = 14, /*!< Flex Frg6 Divider. */ - - kCLOCK_DivFlexFrg7 = 15, /*!< Flex Frg7 Divider. */ - - kCLOCK_DivAhbClk = 32, /*!< Ahb Clock Divider. */ - - kCLOCK_DivClkOut = 33, /*!< Clk Out Divider. */ - - kCLOCK_DivFrohfClk = 34, /*!< Frohf Clock Divider. */ - - kCLOCK_DivWdtClk = 35, /*!< Wdt Clock Divider. */ - - kCLOCK_DivAdcAsyncClk = 37, /*!< Adc Async Clock Divider. */ - - kCLOCK_DivFro1mClk = 40, /*!< Fro1m Clock Divider. */ - - kCLOCK_DivMClk = 43, /*!< Main Clock Divider. */ - - kCLOCK_DivSctClk = 45, /*!< Sct Clock Divider. */ - - kCLOCK_DivPll0Clk = 49 /*!< PLL0 clock divider. */ -} clock_div_name_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief Enable the clock for specific IP. - * @param clk : Clock to be enabled. - * @return Nothing - */ -static inline void CLOCK_EnableClock(clock_ip_name_t clk) -{ - uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); -} -/** - * @brief Disable the clock for specific IP. - * @param clk : Clock to be Disabled. - * @return Nothing - */ -static inline void CLOCK_DisableClock(clock_ip_name_t clk) -{ - uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); -} -/** - * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). - * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is - * enabled. - * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ) - * @return returns success or fail status. - */ -status_t CLOCK_SetupFROClocking(uint32_t iFreq); -/** - * @brief Set the flash wait states for the input freuqency. - * @param system_freq_hz : Input frequency - * @return Nothing - */ -void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz); -/** - * @brief Initialize the external osc clock to given frequency. - * @param iFreq : Desired frequency (must be equal to exact rate in Hz) - * @return returns success or fail status. - */ -status_t CLOCK_SetupExtClocking(uint32_t iFreq); -/** - * @brief Initialize the I2S MCLK clock to given frequency. - * @param iFreq : Desired frequency (must be equal to exact rate in Hz) - * @return returns success or fail status. - */ -status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq); -/** - * @brief Initialize the PLU CLKIN clock to given frequency. - * @param iFreq : Desired frequency (must be equal to exact rate in Hz) - * @return returns success or fail status. - */ -status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq); -/** - * @brief Configure the clock selection muxes. - * @param connection : Clock to be configured. - * @return Nothing - */ -void CLOCK_AttachClk(clock_attach_id_t connection); -/** - * @brief Get the actual clock attach id. - * This fuction uses the offset in input attach id, then it reads the actual source value in - * the register and combine the offset to obtain an actual attach id. - * @param attachId : Clock attach id to get. - * @return Clock source value. - */ -clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId); -/** - * @brief Setup peripheral clock dividers. - * @param div_name : Clock divider name - * @param divided_by_value: Value to be divided - * @param reset : Whether to reset the divider counter. - * @return Nothing - */ -void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset); -/** - * @brief Setup rtc 1khz clock divider. - * @param divided_by_value: Value to be divided - * @return Nothing - */ -void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value); -/** - * @brief Setup rtc 1hz clock divider. - * @param divided_by_value: Value to be divided - * @return Nothing - */ -void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value); - -/** - * @brief Set the flexcomm output frequency. - * @param id : flexcomm instance id - * @param freq : output frequency - * @return 0 : the frequency range is out of range. - * 1 : switch successfully. - */ -uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq); - -/*! @brief Return Frequency of flexcomm input clock - * @param id : flexcomm instance id - * @return Frequency value - */ -uint32_t CLOCK_GetFlexCommInputClock(uint32_t id); - -/*! @brief Return Frequency of selected clock - * @return Frequency of selected clock - */ -uint32_t CLOCK_GetFreq(clock_name_t clockName); -/*! @brief Return Frequency of FRO 12MHz - * @return Frequency of FRO 12MHz - */ -uint32_t CLOCK_GetFro12MFreq(void); -/*! @brief Return Frequency of FRO 1MHz - * @return Frequency of FRO 1MHz - */ -uint32_t CLOCK_GetFro1MFreq(void); -/*! @brief Return Frequency of ClockOut - * @return Frequency of ClockOut - */ -uint32_t CLOCK_GetClockOutClkFreq(void); -/*! @brief Return Frequency of Can Clock - * @return Frequency of Can. - */ -uint32_t CLOCK_GetMCanClkFreq(void); -/*! @brief Return Frequency of Adc Clock - * @return Frequency of Adc. - */ -uint32_t CLOCK_GetAdcClkFreq(void); -/*! @brief Return Frequency of MClk Clock - * @return Frequency of MClk Clock. - */ -uint32_t CLOCK_GetMclkClkFreq(void); -/*! @brief Return Frequency of SCTimer Clock - * @return Frequency of SCTimer Clock. - */ -uint32_t CLOCK_GetSctClkFreq(void); -/*! @brief Return Frequency of External Clock - * @return Frequency of External Clock. If no external clock is used returns 0. - */ -uint32_t CLOCK_GetExtClkFreq(void); -/*! @brief Return Frequency of Watchdog - * @return Frequency of Watchdog - */ -uint32_t CLOCK_GetWdtClkFreq(void); -/*! @brief Return Frequency of High-Freq output of FRO - * @return Frequency of High-Freq output of FRO - */ -uint32_t CLOCK_GetFroHfFreq(void); -/*! @brief Return Frequency of PLL - * @return Frequency of PLL - */ -uint32_t CLOCK_GetPll0OutFreq(void); -/*! @brief Return Frequency of USB PLL - * @return Frequency of PLL - */ -uint32_t CLOCK_GetPll1OutFreq(void); -/*! @brief Return Frequency of 32kHz osc - * @return Frequency of 32kHz osc - */ -uint32_t CLOCK_GetOsc32KFreq(void); -/*! @brief Return Frequency of Core System - * @return Frequency of Core System - */ -uint32_t CLOCK_GetCoreSysClkFreq(void); -/*! @brief Return Frequency of I2S MCLK Clock - * @return Frequency of I2S MCLK Clock - */ -uint32_t CLOCK_GetI2SMClkFreq(void); -/*! @brief Return Frequency of PLU CLKIN Clock - * @return Frequency of PLU CLKIN Clock - */ -uint32_t CLOCK_GetPLUClkInFreq(void); -/*! @brief Return Frequency of FlexComm Clock - * @return Frequency of FlexComm Clock - */ -uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id); -/*! @brief Return Frequency of High speed SPI Clock - * @return Frequency of High speed SPI Clock - */ -uint32_t CLOCK_GetHsLspiClkFreq(void); -/*! @brief Return Frequency of CTimer functional Clock - * @return Frequency of CTimer functional Clock - */ -uint32_t CLOCK_GetCTimerClkFreq(uint32_t id); -/*! @brief Return Frequency of SystickClock - * @return Frequency of Systick Clock - */ -uint32_t CLOCK_GetSystickClkFreq(uint32_t id); - -/*! @brief Return PLL0 input clock rate - * @return PLL0 input clock rate - */ -uint32_t CLOCK_GetPLL0InClockRate(void); - -/*! @brief Return PLL1 input clock rate - * @return PLL1 input clock rate - */ -uint32_t CLOCK_GetPLL1InClockRate(void); - -/*! @brief Return PLL0 output clock rate - * @param recompute : Forces a PLL rate recomputation if true - * @return PLL0 output clock rate - * @note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetPLL0OutClockRate(bool recompute); - -/*! @brief Return PLL1 output clock rate - * @param recompute : Forces a PLL rate recomputation if true - * @return PLL1 output clock rate - * @note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetPLL1OutClockRate(bool recompute); - -/*! @brief Enables and disables PLL0 bypass mode - * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass - * @return PLL0 output clock rate - */ -__STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass) -{ - if (bypass) - { - SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); - } - else - { - SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); - } -} - -/*! @brief Enables and disables PLL1 bypass mode - * @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass - * @return PLL1 output clock rate - */ -__STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass) -{ - if (bypass) - { - SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); - } - else - { - SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); - } -} - -/*! @brief Check if PLL is locked or not - * @return true if the PLL is locked, false if not locked - */ -__STATIC_INLINE bool CLOCK_IsPLL0Locked(void) -{ - return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0UL); -} - -/*! @brief Check if PLL1 is locked or not - * @return true if the PLL1 is locked, false if not locked - */ -__STATIC_INLINE bool CLOCK_IsPLL1Locked(void) -{ - return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0UL); -} - -/*! @brief Store the current PLL0 rate - * @param rate: Current rate of the PLL0 - * @return Nothing - **/ -void CLOCK_SetStoredPLL0ClockRate(uint32_t rate); - -/*! @brief PLL configuration structure flags for 'flags' field - * These flags control how the PLL configuration function sets up the PLL setup structure.
- * - * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the - * configuration structure must be assigned with the expected PLL frequency. If the - * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration - * function and the driver will determine the PLL rate from the currently selected - * PLL source. This flag might be used to configure the PLL input clock more accurately - * when using the WDT oscillator or a more dyanmic CLKIN source.
- * - * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the - * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider - * are not used.
- */ -#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */ -#define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U) -/*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */ - -/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency - * See (MF) field in the PLL0SSCG1 register in the UM. - */ -typedef enum _ss_progmodfm -{ - kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */ - kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */ - kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */ - kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */ - kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */ - kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */ - kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */ - kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */ -} ss_progmodfm_t; - -/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth - * See (MR) field in the PLL0SSCG1 register in the UM. - */ -typedef enum _ss_progmoddp -{ - kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */ - kSS_MR_K1 = (1 << 23), /*!< k = 1 */ - kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */ - kSS_MR_K2 = (3 << 23), /*!< k = 2 */ - kSS_MR_K3 = (4 << 23), /*!< k = 3 */ - kSS_MR_K4 = (5 << 23), /*!< k = 4 */ - kSS_MR_K6 = (6 << 23), /*!< k = 6 */ - kSS_MR_K8 = (7 << 23) /*!< k = 8 */ -} ss_progmoddp_t; - -/*! @brief PLL Spread Spectrum (SS) Modulation waveform control - * See (MC) field in the PLL0SSCG1 register in the UM.
- * Compensation for low pass filtering of the PLL to get a triangular - * modulation at the output of the PLL, giving a flat frequency spectrum. - */ -typedef enum _ss_modwvctrl -{ - kSS_MC_NOC = (0 << 26), /*!< no compensation */ - kSS_MC_RECC = (2 << 26), /*!< recommended setting */ - kSS_MC_MAXC = (3 << 26), /*!< max. compensation */ -} ss_modwvctrl_t; - -/*! @brief PLL configuration structure - * - * This structure can be used to configure the settings for a PLL - * setup structure. Fill in the desired configuration for the PLL - * and call the PLL setup function to fill in a PLL setup structure. - */ -typedef struct _pll_config -{ - uint32_t desiredRate; /*!< Desired PLL rate in Hz */ - uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */ - uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ - ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - ss_modwvctrl_t - ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ - bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - -} pll_config_t; - -/*! @brief PLL setup structure flags for 'flags' field - * These flags control how the PLL setup function sets up the PLL - */ -#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */ -#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ -#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */ -#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */ - -/*! @brief PLL0 setup structure - * This structure can be used to pre-build a PLL setup configuration - * at run-time and quickly set the PLL to the configuration. It can be - * populated with the PLL setup function. If powering up or waiting - * for PLL lock, the PLL input clock source should be configured prior - * to PLL setup. - */ -typedef struct _pll_setup -{ - uint32_t pllctrl; /*!< PLL control register PLL0CTRL */ - uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */ - uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */ - uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */ - uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/ - uint32_t pllRate; /*!< Acutal PLL rate */ - uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ -} pll_setup_t; - -/*! @brief PLL status definitions - */ -typedef enum _pll_error -{ - kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ - kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ - kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ - kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ - kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ - kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */ - kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */ - kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */ -} pll_error_t; - -/*! @brief Return PLL0 output clock rate from setup structure - * @param pSetup : Pointer to a PLL setup structure - * @return System PLL output clock rate the setup structure will generate - */ -uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup); - -/*! @brief Return PLL1 output clock rate from setup structure - * @param pSetup : Pointer to a PLL setup structure - * @return PLL0 output clock rate the setup structure will generate - */ -uint32_t CLOCK_GetPLL1OutFromSetup(pll_setup_t *pSetup); - -/*! @brief Set PLL0 output based on the passed PLL setup data - * @param pControl : Pointer to populated PLL control structure to generate setup with - * @param pSetup : Pointer to PLL setup structure to be filled - * @return PLL_ERROR_SUCCESS on success, or PLL setup error code - * @note Actual frequency for setup may vary from the desired frequency based on the - * accuracy of input clocks, rounding, non-fractional PLL mode, etc. - */ -pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup); - -/*! @brief Set PLL output from PLL setup structure (precise frequency) - * @param pSetup : Pointer to populated PLL setup structure - * @param flagcfg : Flag configuration for PLL config structure - * @return PLL_ERROR_SUCCESS on success, or PLL setup error code - * @note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg); - -/** - * @brief Set PLL output from PLL setup structure (precise frequency) - * @param pSetup : Pointer to populated PLL setup structure - * @return kStatus_PLL_Success on success, or PLL setup error code - * @note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup); - -/** - * @brief Set PLL output from PLL setup structure (precise frequency) - * @param pSetup : Pointer to populated PLL setup structure - * @return kStatus_PLL_Success on success, or PLL setup error code - * @note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup); - -/*! @brief Set PLL0 output based on the multiplier and input frequency - * @param multiply_by : multiplier - * @param input_freq : Clock input frequency of the PLL - * @return Nothing - * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this - * function does not disable or enable PLL power, wait for PLL lock, - * or adjust system voltages. These must be done in the application. - * The function will not alter any source clocks (ie, main systen clock) - * that may use the PLL, so these should be setup prior to and after - * exiting the function. - */ -void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq); - -/*! @brief Enable the OSTIMER 32k clock. - * @return Nothing - */ -void CLOCK_EnableOstimer32kClock(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @} */ - -#endif /* _FSL_CLOCK_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_cmp.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_cmp.c deleted file mode 100644 index c7069e5c130..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_cmp.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright 2018-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_cmp.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.cmp_1" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * @brief CMP initialization. - * - * This function enables the CMP module and do necessary settings. - * - * @param config Pointer to the configuration structure. - */ -void CMP_Init(const cmp_config_t *config) -{ - assert(NULL != config); - - uint32_t tmpReg = 0U; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Comp); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_CMP_HAS_NO_RESET) && FSL_TEATURE_CMP_HAS_NO_RESET) - /* Reset the CMP module. */ - RESET_PeripheralReset(kCMP_RST_SHIFT_RSTn); -#endif /* FSL_FEATURE_CMP_HAS_NO_RESET */ - - tmpReg = (PMC->COMP & ~(PMC_COMP_LOWPOWER_MASK | PMC_COMP_HYST_MASK | PMC_COMP_FILTERCGF_CLKDIV_MASK | - PMC_COMP_FILTERCGF_SAMPLEMODE_MASK)); - - if (true == config->enableLowPower) - { - tmpReg |= PMC_COMP_LOWPOWER_MASK; - } - else - { - tmpReg &= ~PMC_COMP_LOWPOWER_MASK; - } - - if (true == config->enableHysteresis) - { - tmpReg |= PMC_COMP_HYST_MASK; - } - else - { - tmpReg &= ~PMC_COMP_HYST_MASK; - } - - tmpReg |= (PMC_COMP_FILTERCGF_CLKDIV(config->filterClockDivider) | - PMC_COMP_FILTERCGF_SAMPLEMODE(config->filterSampleMode)); - - PMC->COMP = tmpReg; -} - -/*! - * @brief CMP deinitialization. - * - * This function gates the clock for CMP module. - */ -void CMP_Deinit(void) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(kCLOCK_Comp); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Initializes the CMP user configuration structure. - * - * This function initializes the user configuration structure to these default values. - * @code - * config->enableHysteresis = true; - * config->enableLowPower = true; - * config->filterClockDivider = kCMP_FilterClockDivide1; - * config->filterSampleMode = kCMP_FilterSampleMode0; - * @endcode - * @param config Pointer to the configuration structure. - */ -void CMP_GetDefaultConfig(cmp_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enableHysteresis = true; - config->enableLowPower = true; - config->filterClockDivider = kCMP_FilterClockDivide1; - config->filterSampleMode = kCMP_FilterSampleMode0; -} - -/*! - * @brief Configures the VREFINPUT. - * - * @param config Pointer to the configuration structure. - */ -void CMP_SetVREF(const cmp_vref_config_t *config) -{ - assert(NULL != config); - assert(config->vrefValue < 32U); - - uint32_t tmpReg = PMC->COMP & ~(PMC_COMP_VREF_MASK | PMC_COMP_VREFINPUT_MASK); - - tmpReg |= PMC_COMP_VREFINPUT(config->vrefSource) | PMC_COMP_VREF(config->vrefValue); - - PMC->COMP = tmpReg; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_cmp.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_cmp.h deleted file mode 100644 index 1afdc972808..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_cmp.h +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Copyright 2018-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __FSL_CMP_H_ -#define __FSL_CMP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup cmp_1 - * @{ - */ - -/****************************************************************************** - * Definitions. - *****************************************************************************/ -/*! @name Driver version */ -/*@{*/ -/*! @brief Driver version 2.2.1. */ -#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 1U)) -/*@}*/ - -/*! @brief CMP input mux for positive and negative sides. */ -enum _cmp_input_mux -{ - kCMP_InputVREF = 0U, /*!< Cmp input from VREF. */ - kCMP_Input1 = 1U, /*!< Cmp input source 1. */ - kCMP_Input2 = 2U, /*!< Cmp input source 2. */ - kCMP_Input3 = 3U, /*!< Cmp input source 3. */ - kCMP_Input4 = 4U, /*!< Cmp input source 4. */ - kCMP_Input5 = 5U, /*!< Cmp input source 5. */ -}; - -/*! @brief CMP interrupt type. */ -enum _cmp_interrupt_type -{ - kCMP_EdgeDisable = 0U, /*!< Disable edge interupt. */ - kCMP_EdgeRising = 2U, /*!< Interrupt on falling edge. */ - kCMP_EdgeFalling = 4U, /*!< Interrupt on rising edge. */ - kCMP_EdgeRisingFalling = 6U, /*!< Interrupt on both rising and falling edges. */ - - kCMP_LevelDisable = 1U, /*!< Disable level interupt. */ - kCMP_LevelHigh = 3U, /*!< Interrupt on high level. */ - kCMP_LevelLow = 5U, /*!< Interrupt on low level. */ -}; - -/*! @brief CMP Voltage Reference source. */ -typedef enum _cmp_vref_source -{ - KCMP_VREFSourceVDDA = 1U, /*!< Select VDDA as VREF. */ - KCMP_VREFSourceInternalVREF = 0U, /*!< Select internal VREF as VREF. */ -} cmp_vref_source_t; - -typedef struct _cmp_vref_config -{ - cmp_vref_source_t vrefSource; /*!< Reference voltage source. */ - uint8_t vrefValue; /*!< Reference voltage step. Available range is 0-31. Per step equals to VREFINPUT/31. */ -} cmp_vref_config_t; - -/*! @brief CMP Filter sample mode. */ -typedef enum _cmp_filtercgf_samplemode -{ - kCMP_FilterSampleMode0 = 0U, /*!< Bypass mode. Filtering is disabled. */ - kCMP_FilterSampleMode1 = 1U, /*!< Filter 1 clock period. */ - kCMP_FilterSampleMode2 = 2U, /*!< Filter 2 clock period. */ - kCMP_FilterSampleMode3 = 3U /*!< Filter 3 clock period. */ -} cmp_filtercgf_samplemode_t; - -/*! @brief CMP Filter clock divider. */ -typedef enum _cmp_filtercgf_clkdiv -{ - kCMP_FilterClockDivide1 = 0U, /*!< Filter clock period duration equals 1 analog comparator clock period. */ - kCMP_FilterClockDivide2 = 1U, /*!< Filter clock period duration equals 2 analog comparator clock period. */ - kCMP_FilterClockDivide4 = 2U, /*!< Filter clock period duration equals 4 analog comparator clock period. */ - kCMP_FilterClockDivide8 = 3U, /*!< Filter clock period duration equals 8 analog comparator clock period. */ - kCMP_FilterClockDivide16 = 4U, /*!< Filter clock period duration equals 16 analog comparator clock period. */ - kCMP_FilterClockDivide32 = 5U, /*!< Filter clock period duration equals 32 analog comparator clock period. */ - kCMP_FilterClockDivide64 = 6U /*!< Filter clock period duration equals 64 analog comparator clock period. */ -} cmp_filtercgf_clkdiv_t; - -/*! @brief CMP configuration structure. */ -typedef struct _cmp_config -{ - bool enableHysteresis; /*!< Enable hysteresis. */ - bool enableLowPower; /*!< Enable low power mode. */ - cmp_filtercgf_clkdiv_t filterClockDivider; /* Filter clock divider. Filter clock equals the Analog Comparator clock - divided by 2^FILTERCGF_CLKDIV. */ - cmp_filtercgf_samplemode_t - filterSampleMode; /* Filter sample mode. Control the filtering of the Analog Comparator output. */ -} cmp_config_t; - -/************************************************************************************************* - * API - ************************************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief CMP initialization. - * - * This function enables the CMP module and do necessary settings. - * - * @param config Pointer to the configuration structure. - */ -void CMP_Init(const cmp_config_t *config); - -/*! - * @brief CMP deinitialization. - * - * This function gates the clock for CMP module. - */ -void CMP_Deinit(void); - -/*! - * @brief Initializes the CMP user configuration structure. - * - * This function initializes the user configuration structure to these default values. - * @code - * config->enableHysteresis = true; - * config->enableLowPower = true; - * config->filterClockDivider = kCMP_FilterClockDivide1; - * config->filterSampleMode = kCMP_FilterSampleMode0; - * @endcode - * @param config Pointer to the configuration structure. - */ -void CMP_GetDefaultConfig(cmp_config_t *config); - -/* @} */ - -/*! - * @name Compare Interface - * @{ - */ - -/* - * @brief Set the input channels for the comparator. - * - * @param positiveChannel Positive side input channel number. See "_cmp_input_mux". - * @param negativeChannel Negative side input channel number. See "_cmp_input_mux". - */ -static inline void CMP_SetInputChannels(uint8_t positiveChannel, uint8_t negativeChannel) -{ - PMC->COMP &= ~(PMC_COMP_PMUX_MASK | PMC_COMP_NMUX_MASK); - PMC->COMP |= (PMC_COMP_PMUX(positiveChannel) | PMC_COMP_NMUX(negativeChannel)); -} - -/*! - * @brief Configures the VREFINPUT. - * - * @param config Pointer to the configuration structure. - */ -void CMP_SetVREF(const cmp_vref_config_t *config); - -/*! - * @brief Get CMP compare output. - * - * @return The output result. true: voltage on positive side is greater than negative side. - * false: voltage on positive side is lower than negative side. - */ -static inline bool CMP_GetOutput(void) -{ - return SYSCON_COMP_INT_STATUS_VAL_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_VAL_MASK); -} - -/* @} */ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief CMP enable interrupt. - * - * @param type CMP interrupt type. See "_cmp_interrupt_type". - */ -static inline void CMP_EnableInterrupt(uint32_t type) -{ - SYSCON->COMP_INT_CTRL |= (SYSCON_COMP_INT_CTRL_INT_CTRL(type) | SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK); -} - -/*! - * @brief CMP disable interrupt. - * - */ -static inline void CMP_DisableInterrupt(void) -{ - SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK; -} - -/*! - * @brief CMP clear interrupt. - * - */ -static inline void CMP_ClearInterrupt(void) -{ - SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK; -} - -/*! - * @brief Select which Analog comparator output (filtered or un-filtered) is used for interrupt detection. - * - * @param enable false: Select Analog Comparator raw output (unfiltered) as input for interrupt detection. - * true: Select Analog Comparator filtered output as input for interrupt detection. - * - * @note: When CMP is configured as the wakeup source in power down mode, this function must use the raw output as the - * interupt source, that is, call this function and set parameter enable to false. - */ -static inline void CMP_EnableFilteredInterruptSource(bool enable) -{ - if (enable) - { - SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; - } - else - { - SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; - } -} -/* @} */ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Get CMP interrupt status before interupt enable. - * - * @return Interrupt status. true: interrupt pending, - * false: no interrupt pending. - */ -static inline bool CMP_GetPreviousInterruptStatus(void) -{ - return SYSCON_COMP_INT_STATUS_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_STATUS_MASK); -} - -/*! - * @brief Get CMP interrupt status after interupt enable. - * - * @return Interrupt status. true: interrupt pending, - * false: no interrupt pending. - */ -static inline bool CMP_GetInterruptStatus(void) -{ - return SYSCON_COMP_INT_STATUS_INT_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK); -} -/* @} */ - -/*! - * @name Filter Interface - * @{ - */ - -/*! - * @brief CMP Filter Sample Config. - * - * This function allows the users to configure the sampling mode and clock divider of the CMP Filter. - * - * @param filterSampleMode CMP Select filter sample mode - * @param filterClockDivider CMP Set fileter clock divider - */ -static inline void CMP_FilterSampleConfig(cmp_filtercgf_samplemode_t filterSampleMode, - cmp_filtercgf_clkdiv_t filterClockDivider) -{ - uint32_t comp = PMC->COMP; - - comp &= ~(PMC_COMP_FILTERCGF_CLKDIV_MASK | PMC_COMP_FILTERCGF_SAMPLEMODE_MASK); - comp |= (((uint32_t)filterClockDivider << PMC_COMP_FILTERCGF_CLKDIV_SHIFT) | - ((uint32_t)filterSampleMode << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)); - - PMC->COMP = comp; -} -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ -#endif /* __FSL_CMP_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_common.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_common.c deleted file mode 100644 index d3af9fdfc67..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_common.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" - -#define SDK_MEM_MAGIC_NUMBER 12345U - -typedef struct _mem_align_control_block -{ - uint16_t identifier; /*!< Identifier for the memory control block. */ - uint16_t offset; /*!< offset from aligned address to real address */ -} mem_align_cb_t; - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.common" -#endif - -#if !((defined(__DSC__) && defined(__CW__))) -void *SDK_Malloc(size_t size, size_t alignbytes) -{ - mem_align_cb_t *p_cb = NULL; - uint32_t alignedsize; - - /* Check overflow. */ - alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes); - if (alignedsize < size) - { - return NULL; - } - - if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t)) - { - return NULL; - } - - alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t); - - union - { - void *pointer_value; - uintptr_t unsigned_value; - } p_align_addr, p_addr; - - p_addr.pointer_value = malloc((size_t)alignedsize); - - if (p_addr.pointer_value == NULL) - { - return NULL; - } - - p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes); - - p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U); - p_cb->identifier = SDK_MEM_MAGIC_NUMBER; - p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value); - - return p_align_addr.pointer_value; -} - -void SDK_Free(void *ptr) -{ - union - { - void *pointer_value; - uintptr_t unsigned_value; - } p_free; - p_free.pointer_value = ptr; - mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U); - - if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) - { - return; - } - - p_free.unsigned_value = p_free.unsigned_value - p_cb->offset; - - free(p_free.pointer_value); -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_common.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_common.h deleted file mode 100644 index d9cb304f2f8..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_common.h +++ /dev/null @@ -1,316 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_COMMON_H_ -#define _FSL_COMMON_H_ - -#include -#include -#include -#include -#include - -#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__) -#include -#endif - -#include "fsl_device_registers.h" - -/*! - * @addtogroup ksdk_common - * @{ - */ - -/******************************************************************************* - * Configurations - ******************************************************************************/ - -/*! @brief Macro to use the default weak IRQ handler in drivers. */ -#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ -#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Construct a status code value from a group and code number. */ -#define MAKE_STATUS(group, code) ((((group)*100L) + (code))) - -/*! @brief Construct the version number for drivers. - * - * The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M) - * and 16-bit platforms(such as DSC). - * - * @verbatim - - | Unused || Major Version || Minor Version || Bug Fix | - 31 25 24 17 16 9 8 0 - - @endverbatim - */ -#define MAKE_VERSION(major, minor, bugfix) (((major) * 65536L) + ((minor) * 256L) + (bugfix)) - -/*! @name Driver version */ -/*@{*/ -/*! @brief common driver version. */ -#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 2)) -/*@}*/ - -/* Debug console type definition. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */ - -/*! @brief Status group numbers. */ -enum _status_groups -{ - kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ - kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ - kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ - kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ - kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ - kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ - kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ - kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ - kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ - kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ - kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ - kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ - kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ - kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ - kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ - kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ - kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ - kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ - kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ - kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ - kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ - kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ - kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ - kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ - kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ - kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ - kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ - kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ - kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ - kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ - kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ - kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ - kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ - kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ - kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ - kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ - kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ - kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ - kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ - kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ - kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ - kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ - kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ - kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ - kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ - kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ - kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ - kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ - kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ - kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ - kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ - kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ - kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ - kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ - kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ - kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ - kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ - kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ - kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ - kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ - kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ - kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ - kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ - kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ - kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ - kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ - kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ - kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ - kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ - kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ - kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ - kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ - kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ - kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/ - kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */ - kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */ - kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */ - - kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ - kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ - kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ - kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ - kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ - kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ - kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ - kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ - kStatusGroup_HAL_I2S = 129, /*!< Group number for HAL I2S status codes. */ - kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ - kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ - kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ - kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ - kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ - kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ - kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ - kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ - kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ - kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ - kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ - kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ - kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ - kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ - kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */ - kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */ - kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */ - kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */ - kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */ - kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */ - kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */ - kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */ - kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */ - kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */ - kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */ - kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */ - kStatusGroup_CSS_PKC = 161, /*!< Group number for CSS PKC status codes. */ - kStatusGroup_HOSTIF = 162, /*!< Group number for HOSTIF status codes. */ - kStatusGroup_CLIF = 163, /*!< Group number for CLIF status codes. */ - kStatusGroup_BMA = 164, /*!< Group number for BMA status codes. */ -}; - -/*! \public - * @brief Generic status return codes. - */ -enum -{ - kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */ - kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */ - kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */ - kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */ - kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */ - kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */ - kStatus_NoTransferInProgress = - MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */ - kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */ - kStatus_NoData = - MAKE_STATUS(kStatusGroup_Generic, 8), /*!< Generic status for no data is found for the operation. */ -}; - -/*! @brief Type used for all status and error return values. */ -typedef int32_t status_t; - -/*! - * @name Min/max macros - * @{ - */ -#if !defined(MIN) -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) -#endif - -#if !defined(MAX) -#define MAX(a, b) (((a) > (b)) ? (a) : (b)) -#endif -/* @} */ - -/*! @brief Computes the number of elements in an array. */ -#if !defined(ARRAY_SIZE) -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) -#endif - -/*! @name UINT16_MAX/UINT32_MAX value */ -/* @{ */ -#if !defined(UINT16_MAX) -#define UINT16_MAX ((uint16_t)-1) -#endif - -#if !defined(UINT32_MAX) -#define UINT32_MAX ((uint32_t)-1) -#endif -/* @} */ - -/*! @name Suppress fallthrough warning macro */ -/* For switch case code block, if case section ends without "break;" statement, there wil be - fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. - To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each - case section which misses "break;"statement. - */ -/* @{ */ -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) -#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough)) -#else -#define SUPPRESS_FALL_THROUGH_WARNING() -#endif -/* @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -#if !((defined(__DSC__) && defined(__CW__))) -/*! - * @brief Allocate memory with given alignment and aligned size. - * - * This is provided to support the dynamically allocated memory - * used in cache-able region. - * @param size The length required to malloc. - * @param alignbytes The alignment size. - * @retval The allocated memory. - */ -void *SDK_Malloc(size_t size, size_t alignbytes); - -/*! - * @brief Free memory. - * - * @param ptr The memory to be release. - */ -void SDK_Free(void *ptr); -#endif - -/*! - * @brief Delay at least for some time. - * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, - * if precise delay count was needed, please implement a new delay function with hardware timer. - * - * @param delayTime_us Delay time in unit of microsecond. - * @param coreClock_Hz Core clock frequency with Hz. - */ -void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#if (defined(__DSC__) && defined(__CW__)) -#include "fsl_common_dsc.h" -#elif defined(__XCC__) -#include "fsl_common_dsp.h" -#else -#include "fsl_common_arm.h" -#endif - -#endif /* _FSL_COMMON_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_common_arm.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_common_arm.c deleted file mode 100644 index e77a265ce43..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_common_arm.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.common_arm" -#endif - -#ifndef __GIC_PRIO_BITS -#if defined(ENABLE_RAM_VECTOR_TABLE) -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) -{ -#ifdef __VECTOR_TABLE -#undef __VECTOR_TABLE -#endif - -/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) - extern uint32_t Image$$VECTOR_ROM$$Base[]; - extern uint32_t Image$$VECTOR_RAM$$Base[]; - extern uint32_t Image$$RW_m_data$$Base[]; - -#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base -#define __VECTOR_RAM Image$$VECTOR_RAM$$Base -#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) -#elif defined(__ICCARM__) - extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; -#elif defined(__GNUC__) - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; - extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; - uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); -#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ - uint32_t n; - uint32_t ret; - uint32_t irqMaskValue; - - irqMaskValue = DisableGlobalIRQ(); - if (SCB->VTOR != (uint32_t)__VECTOR_RAM) - { - /* Copy the vector table from ROM to RAM */ - for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) - { - __VECTOR_RAM[n] = __VECTOR_TABLE[n]; - } - /* Point the VTOR to the position of vector table */ - SCB->VTOR = (uint32_t)__VECTOR_RAM; - } - - ret = __VECTOR_RAM[(int32_t)irq + 16]; - /* make sure the __VECTOR_RAM is noncachable */ - __VECTOR_RAM[(int32_t)irq + 16] = irqHandler; - - EnableGlobalIRQ(irqMaskValue); - - return ret; -} -#endif /* ENABLE_RAM_VECTOR_TABLE. */ -#endif /* __GIC_PRIO_BITS. */ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - -/* - * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, - * powerlib should be used instead of these functions. - */ -#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) - -/* - * When the SYSCON STARTER registers are discontinuous, these functions are - * implemented in fsl_power.c. - */ -#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) - -void EnableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t intNumber = (uint32_t)interrupt; - - uint32_t index = 0; - - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERSET[index] = 1UL << intNumber; - (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */ -} - -void DisableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t intNumber = (uint32_t)interrupt; - - (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */ - uint32_t index = 0; - - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERCLR[index] = 1UL << intNumber; -} -#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ -#endif /* FSL_FEATURE_POWERLIB_EXTEND */ -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - -#if defined(SDK_DELAY_USE_DWT) && defined(DWT) -/* Use WDT. */ -static void enableCpuCycleCounter(void) -{ - /* Make sure the DWT trace fucntion is enabled. */ - if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) - { - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - } - - /* CYCCNT not supported on this device. */ - assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); - - /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */ - if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) - { - DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; - } -} - -static uint32_t getCpuCycleCount(void) -{ - return DWT->CYCCNT; -} -#else /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ -/* Use software loop. */ -#if defined(__CC_ARM) /* This macro is arm v5 specific */ -/* clang-format off */ -__ASM static void DelayLoop(uint32_t count) -{ -loop - SUBS R0, R0, #1 - CMP R0, #0 - BNE loop - BX LR -} -/* clang-format on */ -#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__) -/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler, - * use SUB and CMP here for compatibility */ -static void DelayLoop(uint32_t count) -{ - __ASM volatile(" MOV R0, %0" : : "r"(count)); - __ASM volatile( - "loop: \n" -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) - " SUB R0, R0, #1 \n" -#else - " SUBS R0, R0, #1 \n" -#endif - " CMP R0, #0 \n" - - " BNE loop \n" - : - : - : "r0"); -} -#endif /* defined(__CC_ARM) */ -#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ - -/*! - * @brief Delay at least for some time. - * Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have - * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and - * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports - * up to 4294967 in current code. If long time delay is needed, please implement a new delay function. - * - * @param delayTime_us Delay time in unit of microsecond. - * @param coreClock_Hz Core clock frequency with Hz. - */ -void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) -{ - uint64_t count; - - if (delayTime_us > 0U) - { - count = USEC_TO_COUNT(delayTime_us, coreClock_Hz); - - assert(count <= UINT32_MAX); - -#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */ - - enableCpuCycleCounter(); - /* Calculate the count ticks. */ - count += getCpuCycleCount(); - - if (count > UINT32_MAX) - { - count -= UINT32_MAX; - /* Wait for cyccnt overflow. */ - while (count < getCpuCycleCount()) - { - } - } - - /* Wait for cyccnt reach count value. */ - while (count > getCpuCycleCount()) - { - } -#else - /* Divide value may be different in various environment to ensure delay is precise. - * Every loop count includes three instructions, due to Cortex-M7 sometimes executes - * two instructions in one period, through test here set divide 1.5. Other M cores use - * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does - * not matter because other instructions outside while loop is enough to fill the time. - */ -#if (__CORTEX_M == 7) - count = count / 3U * 2U; -#else - count = count / 4U; -#endif - DelayLoop((uint32_t)count); -#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_common_arm.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_common_arm.h deleted file mode 100644 index 2678ff625c7..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_common_arm.h +++ /dev/null @@ -1,671 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_COMMON_ARM_H_ -#define _FSL_COMMON_ARM_H_ - -/* - * For CMSIS pack RTE. - * CMSIS pack RTE generates "RTC_Components.h" which contains the statements - * of the related element for all selected software components. - */ -#ifdef _RTE_ -#include "RTE_Components.h" -#endif - -/*! - * @addtogroup ksdk_common - * @{ - */ - -/*! @name Atomic modification - * - * These macros are used for atomic access, such as read-modify-write - * to the peripheral registers. - * - * - SDK_ATOMIC_LOCAL_ADD - * - SDK_ATOMIC_LOCAL_SET - * - SDK_ATOMIC_LOCAL_CLEAR - * - SDK_ATOMIC_LOCAL_TOGGLE - * - SDK_ATOMIC_LOCAL_CLEAR_AND_SET - * - * Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr - * means the address of the peripheral register or variable you want to modify - * atomically, the parameter @c clearBits is the bits to clear, the parameter - * @c setBits it the bits to set. - * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this: - * - * @code - volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR; - - SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02); - @endcode - * - * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result, - * register bit1:bit0 = 0b10. - * - * @note For the platforms don't support exclusive load and store, these macros - * disable the global interrupt to pretect the modification. - * - * @note These macros only guarantee the local processor atomic operations. For - * the multi-processor devices, use hardware semaphore such as SEMA42 to - * guarantee exclusive access if necessary. - * - * @{ - */ - -/* clang-format off */ -#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) -/* clang-format on */ - -/* If the LDREX and STREX are supported, use them. */ -#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \ - do \ - { \ - (val) = __LDREXB(addr); \ - (ops); \ - } while (0UL != __STREXB((val), (addr))) - -#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \ - do \ - { \ - (val) = __LDREXH(addr); \ - (ops); \ - } while (0UL != __STREXH((val), (addr))) - -#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \ - do \ - { \ - (val) = __LDREXW(addr); \ - (ops); \ - } while (0UL != __STREXW((val), (addr))) - -static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val); -} - -static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val); -} - -static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val); -} - -static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val); -} - -static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val); -} - -static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val); -} - -static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits); -} - -static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits); -} - -static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits); -} - -static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits); -} - -static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits); -} - -static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits); -} - -static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits); -} - -static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits); -} - -static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits); -} - -static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); -} - -static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); -} - -static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); -} - -#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ - ((1UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalAdd1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \ - ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \ - _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val)))) - -#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ - ((1UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ - ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ - _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) - -#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ - ((1UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalClear1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ - ((2UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalClear2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ - _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) - -#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ - ((1UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalToggle1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ - ((2UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalToggle2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ - _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) - -#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ - ((1UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(clearBits), (uint8_t)(setBits)) : \ - ((2UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(clearBits), (uint16_t)(setBits)) : \ - _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(clearBits), (uint32_t)(setBits)))) -#else - -#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ - do \ - { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) += (val); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ - do \ - { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) |= (bits); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ - do \ - { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) &= ~(bits); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ - do \ - { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) ^= (bits); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ - do \ - { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) = (*(addr) & ~(clearBits)) | (setBits); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#endif -/* @} */ - -/*! @name Timer utilities */ -/* @{ */ -/*! Macro to convert a microsecond period to raw count value */ -#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) -/*! Macro to convert a raw count value to microsecond */ -#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000000U / (clockFreqInHz)) - -/*! Macro to convert a millisecond period to raw count value */ -#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) -/*! Macro to convert a raw count value to millisecond */ -#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz)) -/* @} */ - -/*! @name ISR exit barrier - * @{ - * - * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - * exception return operation might vector to incorrect interrupt. - * For Cortex-M7, if core speed much faster than peripheral register write speed, - * the peripheral interrupt flags may be still set after exiting ISR, this results to - * the same error similar with errata 83869. - */ -#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U)) -#define SDK_ISR_EXIT_BARRIER __DSB() -#else -#define SDK_ISR_EXIT_BARRIER -#endif - -/* @} */ - -/*! @name Alignment variable definition macros */ -/* @{ */ -#if (defined(__ICCARM__)) -/* - * Workaround to disable MISRA C message suppress warnings for IAR compiler. - * http:/ /supp.iar.com/Support/?note=24725 - */ -_Pragma("diag_suppress=Pm120") -#define SDK_PRAGMA(x) _Pragma(#x) - _Pragma("diag_error=Pm120") -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var -#elif defined(__GNUC__) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) -#else -#error Toolchain not supported -#endif - -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#endif - -/*! Macro to change a value to a given size aligned value */ -#define SDK_SIZEALIGN(var, alignbytes) \ - ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) -/* @} */ - -/*! @name Non-cacheable region definition macros */ -/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or - * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable - * variables, please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, - * these zero-inited variables will be initialized to zero in system startup. - */ -/* @{ */ - -#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \ - defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) - -#if (defined(__ICCARM__)) -#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" -#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" - -#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var -#if (defined(__CC_ARM)) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var -#else -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var -#endif - -#elif (defined(__GNUC__)) -/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" - * in your projects to make sure the non-cacheable section variables will be initialized in system startup. - */ -#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) -#else -#error Toolchain not supported. -#endif - -#else - -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes) -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes) - -#endif - -/* @} */ - -/*! - * @name Time sensitive region - * @{ - */ -#if (defined(__ICCARM__)) -#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" -#define AT_QUICKACCESS_SECTION_DATA(var) var @"DataQuickAccess" -#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ - SDK_PRAGMA(data_alignment = alignbytes) var @"DataQuickAccess" -#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func -#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var -#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ - __attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var -#elif (defined(__GNUC__)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func -#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var -#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ - __attribute__((section("DataQuickAccess"))) var __attribute__((aligned(alignbytes))) -#else -#error Toolchain not supported. -#endif /* defined(__ICCARM__) */ - -/*! @name Ram Function */ -#if (defined(__ICCARM__)) -#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" -#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func -#elif (defined(__GNUC__)) -#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func -#else -#error Toolchain not supported. -#endif /* defined(__ICCARM__) */ -/* @} */ - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - void DefaultISR(void); -#endif - -/* - * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t - * defined in previous of this file. - */ -#include "fsl_clock.h" - -/* - * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral - */ -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) -#include "fsl_reset.h" -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief Enable specific interrupt. - * - * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt enabled successfully - * @retval kStatus_Fail Failed to enable the interrupt - */ -static inline status_t EnableIRQ(IRQn_Type interrupt) -{ - status_t status = kStatus_Success; - - if (NotAvail_IRQn == interrupt) - { - status = kStatus_Fail; - } - -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - status = kStatus_Fail; - } -#endif - - else - { -#if defined(__GIC_PRIO_BITS) - GIC_EnableIRQ(interrupt); -#else - NVIC_EnableIRQ(interrupt); -#endif - } - - return status; -} - -/*! - * @brief Disable specific interrupt. - * - * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt disabled successfully - * @retval kStatus_Fail Failed to disable the interrupt - */ -static inline status_t DisableIRQ(IRQn_Type interrupt) -{ - status_t status = kStatus_Success; - - if (NotAvail_IRQn == interrupt) - { - status = kStatus_Fail; - } - -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - status = kStatus_Fail; - } -#endif - - else - { -#if defined(__GIC_PRIO_BITS) - GIC_DisableIRQ(interrupt); -#else - NVIC_DisableIRQ(interrupt); -#endif - } - - return status; -} - -/*! - * @brief Disable the global IRQ - * - * Disable the global interrupt and return the current primask register. User is required to provided the primask - * register for the EnableGlobalIRQ(). - * - * @return Current primask value. - */ -static inline uint32_t DisableGlobalIRQ(void) -{ -#if defined(CPSR_I_Msk) - uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; - - __disable_irq(); - - return cpsr; -#else - uint32_t regPrimask = __get_PRIMASK(); - - __disable_irq(); - - return regPrimask; -#endif -} - -/*! - * @brief Enable the global IRQ - * - * Set the primask register with the provided primask value but not just enable the primask. The idea is for the - * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to - * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. - * - * @param primask value of primask register to be restored. The primask value is supposed to be provided by the - * DisableGlobalIRQ(). - */ -static inline void EnableGlobalIRQ(uint32_t primask) -{ -#if defined(CPSR_I_Msk) - __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); -#else - __set_PRIMASK(primask); -#endif -} - -#if defined(ENABLE_RAM_VECTOR_TABLE) -/*! - * @brief install IRQ handler - * - * @param irq IRQ number - * @param irqHandler IRQ handler address - * @return The old IRQ handler address - */ -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); -#endif /* ENABLE_RAM_VECTOR_TABLE. */ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - -/* - * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, - * powerlib should be used instead of these functions. - */ -#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) -/*! - * @brief Enable specific interrupt for wake-up from deep-sleep mode. - * - * Enable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). - * - * @param interrupt The IRQ number. - */ -void EnableDeepSleepIRQ(IRQn_Type interrupt); - -/*! - * @brief Disable specific interrupt for wake-up from deep-sleep mode. - * - * Disable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). - * - * @param interrupt The IRQ number. - */ -void DisableDeepSleepIRQ(IRQn_Type interrupt); -#endif /* FSL_FEATURE_POWERLIB_EXTEND */ -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @} */ - -#endif /* _FSL_COMMON_ARM_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_crc.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_crc.c deleted file mode 100644 index c73f84997af..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_crc.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2019-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_crc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_crc" -#endif - -#if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT -/* @brief Default user configuration structure for CRC-CCITT */ -#define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT -/*< CRC-CCIT polynomial x^16 + x^12 + x^5 + x^0 */ -#define CRC_DRIVER_DEFAULT_REVERSE_IN false -/*< Default is no bit reverse */ -#define CRC_DRIVER_DEFAULT_COMPLEMENT_IN false -/*< Default is without complement of written data */ -#define CRC_DRIVER_DEFAULT_REVERSE_OUT false -/*< Default is no bit reverse */ -#define CRC_DRIVER_DEFAULT_COMPLEMENT_OUT false -/*< Default is without complement of CRC data register read data */ -#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU -/*< Default initial checksum */ -#endif /* CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Enables and configures the CRC peripheral module. - * - * This functions enables the CRC peripheral clock in the LPC SYSCON block. - * It also configures the CRC engine and starts checksum computation by writing the seed. - * - * param base CRC peripheral address. - * param config CRC module configuration structure. - */ -void CRC_Init(CRC_Type *base, const crc_config_t *config) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* enable clock to CRC */ - CLOCK_EnableClock(kCLOCK_Crc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_CRC_HAS_NO_RESET) && FSL_FEATURE_CRC_HAS_NO_RESET) - RESET_PeripheralReset(kCRC_RST_SHIFT_RSTn); -#endif - - /* configure CRC module and write the seed */ - base->MODE = CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) | - CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) | - CRC_MODE_CMPL_SUM(config->complementOut); - base->SEED = config->seed; -} - -/*! - * brief Loads default values to CRC protocol configuration structure. - * - * Loads default values to CRC protocol configuration structure. The default values are: - * code - * config->polynomial = kCRC_Polynomial_CRC_CCITT; - * config->reverseIn = false; - * config->complementIn = false; - * config->reverseOut = false; - * config->complementOut = false; - * config->seed = 0xFFFFU; - * endcode - * - * param config CRC protocol configuration structure - */ -void CRC_GetDefaultConfig(crc_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_REVERSE_IN, - CRC_DRIVER_DEFAULT_COMPLEMENT_IN, CRC_DRIVER_DEFAULT_REVERSE_OUT, - CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED}; - - *config = default_config; -} - -/*! - * brief resets CRC peripheral module. - * - * param base CRC peripheral address. - */ -void CRC_Reset(CRC_Type *base) -{ - crc_config_t config; - CRC_GetDefaultConfig(&config); - CRC_Init(base, &config); -} - -/*! - * brief Write seed (initial checksum) to CRC peripheral module. - * - * param base CRC peripheral address. - * param seed CRC Seed value. - */ -void CRC_WriteSeed(CRC_Type *base, uint32_t seed) -{ - /* write the seed (initial checksum) */ - base->SEED = seed; -} - -/*! - * brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure. - * - * The values, including seed, can be used to resume CRC calculation later. - - * param base CRC peripheral address. - * param config CRC protocol configuration structure - */ -void CRC_GetConfig(CRC_Type *base, crc_config_t *config) -{ - /* extract CRC mode settings */ - uint32_t mode = base->MODE; - config->polynomial = - (crc_polynomial_t)(uint32_t)(((uint32_t)(mode & CRC_MODE_CRC_POLY_MASK)) >> CRC_MODE_CRC_POLY_SHIFT); - config->reverseIn = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK); - config->complementIn = (bool)(mode & CRC_MODE_CMPL_WR_MASK); - config->reverseOut = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK); - config->complementOut = (bool)(mode & CRC_MODE_CMPL_SUM_MASK); - - /* reset CRC sum bit reverse and 1's complement setting, so its value can be used as a seed */ - base->MODE = mode & ~((1U << CRC_MODE_BIT_RVS_SUM_SHIFT) | (1U << CRC_MODE_CMPL_SUM_SHIFT)); - - /* now we can obtain intermediate raw CRC sum value */ - config->seed = base->SUM; - - /* restore original CRC sum bit reverse and 1's complement setting */ - base->MODE = mode; -} - -/*! - * brief Writes data to the CRC module. - * - * Writes input data buffer bytes to CRC data register. - * - * param base CRC peripheral address. - * param data Input data stream, MSByte in data[0]. - * param dataSize Size of the input data buffer in bytes. - */ -void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) -{ - const uint32_t *data32; - - /* 8-bit reads and writes till source address is aligned 4 bytes */ - while ((0U != dataSize) && (0U != ((uint32_t)data & 3U))) - { - *((__O uint8_t *)&(base->WR_DATA)) = *data; - data++; - dataSize--; - } - - /* use 32-bit reads and writes as long as possible */ - data32 = (const uint32_t *)(uint32_t)data; - while (dataSize >= sizeof(uint32_t)) - { - *((__O uint32_t *)&(base->WR_DATA)) = *data32; - data32++; - dataSize -= sizeof(uint32_t); - } - - data = (const uint8_t *)data32; - - /* 8-bit reads and writes till end of data buffer */ - while (0U != dataSize) - { - *((__O uint8_t *)&(base->WR_DATA)) = *data; - data++; - dataSize--; - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_crc.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_crc.h deleted file mode 100644 index 08e08bd57d3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_crc.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2019-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CRC_H_ -#define _FSL_CRC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup crc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CRC driver version. Version 2.1.1. - * - * Current version: 2.1.1 - * - * Change log: - * - Version 2.0.0 - * - initial version - * - Version 2.0.1 - * - add explicit type cast when writing to WR_DATA - * - Version 2.0.2 - * - Fix MISRA issue - * - Version 2.1.0 - * - Add CRC_WriteSeed function - * - Version 2.1.1 - * - Fix MISRA issue - */ -#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) -/*@}*/ - -#ifndef CRC_DRIVER_CUSTOM_DEFAULTS -/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Uses CRC-16/CCITT-FALSE as default. */ -#define CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT 1 -#endif - -/*! @brief CRC polynomials to use. */ -typedef enum _crc_polynomial -{ - kCRC_Polynomial_CRC_CCITT = 0U, /*!< x^16+x^12+x^5+1 */ - kCRC_Polynomial_CRC_16 = 1U, /*!< x^16+x^15+x^2+1 */ - kCRC_Polynomial_CRC_32 = 2U /*!< x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */ -} crc_polynomial_t; - -/*! - * @brief CRC protocol configuration. - * - * This structure holds the configuration for the CRC protocol. - * - */ -typedef struct _crc_config -{ - crc_polynomial_t polynomial; /*!< CRC polynomial. */ - bool reverseIn; /*!< Reverse bits on input. */ - bool complementIn; /*!< Perform 1's complement on input. */ - bool reverseOut; /*!< Reverse bits on output. */ - bool complementOut; /*!< Perform 1's complement on output. */ - uint32_t seed; /*!< Starting checksum value. */ -} crc_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Enables and configures the CRC peripheral module. - * - * This functions enables the CRC peripheral clock in the LPC SYSCON block. - * It also configures the CRC engine and starts checksum computation by writing the seed. - * - * @param base CRC peripheral address. - * @param config CRC module configuration structure. - */ -void CRC_Init(CRC_Type *base, const crc_config_t *config); - -/*! - * @brief Disables the CRC peripheral module. - * - * This functions disables the CRC peripheral clock in the LPC SYSCON block. - * - * @param base CRC peripheral address. - */ -static inline void CRC_Deinit(CRC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* disable clock to CRC */ - CLOCK_DisableClock(kCLOCK_Crc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief resets CRC peripheral module. - * - * @param base CRC peripheral address. - */ -void CRC_Reset(CRC_Type *base); - -/*! - * @brief Write seed to CRC peripheral module. - * - * @param base CRC peripheral address. - * @param seed CRC Seed value. - */ -void CRC_WriteSeed(CRC_Type *base, uint32_t seed); - -/*! - * @brief Loads default values to CRC protocol configuration structure. - * - * Loads default values to CRC protocol configuration structure. The default values are: - * @code - * config->polynomial = kCRC_Polynomial_CRC_CCITT; - * config->reverseIn = false; - * config->complementIn = false; - * config->reverseOut = false; - * config->complementOut = false; - * config->seed = 0xFFFFU; - * @endcode - * - * @param config CRC protocol configuration structure - */ -void CRC_GetDefaultConfig(crc_config_t *config); - -/*! - * @brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure. - * - * The values, including seed, can be used to resume CRC calculation later. - - * @param base CRC peripheral address. - * @param config CRC protocol configuration structure - */ -void CRC_GetConfig(CRC_Type *base, crc_config_t *config); - -/*! - * @brief Writes data to the CRC module. - * - * Writes input data buffer bytes to CRC data register. - * - * @param base CRC peripheral address. - * @param data Input data stream, MSByte in data[0]. - * @param dataSize Size of the input data buffer in bytes. - */ -void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize); - -/*! - * @brief Reads 32-bit checksum from the CRC module. - * - * Reads CRC data register. - * - * @param base CRC peripheral address. - * @return final 32-bit checksum, after configured bit reverse and complement operations. - */ -static inline uint32_t CRC_Get32bitResult(CRC_Type *base) -{ - return base->SUM; -} - -/*! - * @brief Reads 16-bit checksum from the CRC module. - * - * Reads CRC data register. - * - * @param base CRC peripheral address. - * @return final 16-bit checksum, after configured bit reverse and complement operations. - */ -static inline uint16_t CRC_Get16bitResult(CRC_Type *base) -{ - return (uint16_t)base->SUM; -} - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_CRC_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_ctimer.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_ctimer.c deleted file mode 100644 index e53bebdd013..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_ctimer.c +++ /dev/null @@ -1,577 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_ctimer.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.ctimer" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base Ctimer peripheral base address - * - * @return The Timer instance - */ -static uint32_t CTIMER_GetInstance(CTIMER_Type *base); - -/*! - * @brief CTIMER generic IRQ handle function. - * - * @param index FlexCAN peripheral instance index. - */ -static void CTIMER_GenericIRQHandler(uint32_t index); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to Timer bases for each instance. */ -static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to Timer clocks for each instance. */ -static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET -/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N; -#else -/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; -#endif -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/*! @brief Pointers real ISRs installed by drivers for each instance. */ -static ctimer_callback_t *s_ctimerCallback[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = {0}; - -/*! @brief Callback type installed by drivers for each instance. */ -static ctimer_callback_type_t ctimerCallbackType[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = { - kCTIMER_SingleCallback}; - -/*! @brief Array to map timer instance to IRQ number. */ -static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t CTIMER_GetInstance(CTIMER_Type *base) -{ - uint32_t instance; - uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ctimerArrayCount; instance++) - { - if (s_ctimerBases[instance] == base) - { - break; - } - } - - assert(instance < ctimerArrayCount); - - return instance; -} - -/*! - * brief Ungates the clock and configures the peripheral for basic operation. - * - * note This API should be called at the beginning of the application before using the driver. - * - * param base Ctimer peripheral base address - * param config Pointer to the user configuration structure. - */ -void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) -{ - assert(config != NULL); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the timer clock*/ - CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -/* Reset the module. */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) - RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]); -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/* Setup the cimer mode and count select */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input); -#endif - /* Setup the timer prescale value */ - base->PR = CTIMER_PR_PRVAL(config->prescale); -} - -/*! - * brief Gates the timer clock. - * - * param base Ctimer peripheral base address - */ -void CTIMER_Deinit(CTIMER_Type *base) -{ - uint32_t index = CTIMER_GetInstance(base); - /* Stop the timer */ - base->TCR &= ~CTIMER_TCR_CEN_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the timer clock*/ - CLOCK_DisableClock(s_ctimerClocks[index]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Disable IRQ at NVIC Level */ - (void)DisableIRQ(s_ctimerIRQ[index]); -} - -/*! - * brief Fills in the timers configuration structure with the default settings. - * - * The default values are: - * code - * config->mode = kCTIMER_TimerMode; - * config->input = kCTIMER_Capture_0; - * config->prescale = 0; - * endcode - * param config Pointer to the user configuration structure. - */ -void CTIMER_GetDefaultConfig(ctimer_config_t *config) -{ - assert(config != NULL); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* Run as a timer */ - config->mode = kCTIMER_TimerMode; - /* This field is ignored when mode is timer */ - config->input = kCTIMER_Capture_0; - /* Timer counter is incremented on every APB bus clock */ - config->prescale = 0; -} - -/*! - * brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function can manually assign the specified channel to set the PWM cycle. - * - * note When setting PWM output from multiple output pins, all should use the same PWM - * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. - * - * param base Ctimer peripheral base address - * param pwmPeriodChannel Specify the channel to control the PWM period - * param matchChannel Match pin to be used to output the PWM signal - * param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 - * param pwmFreq_Hz PWM signal frequency in Hz - * param srcClock_Hz Timer counter clock in Hz - * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt will be generated. - * - * return kStatus_Success on success - * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM cycle - */ -status_t CTIMER_SetupPwm(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - bool enableInt) -{ - assert(pwmFreq_Hz > 0U); - - uint32_t reg; - uint32_t period, pulsePeriod = 0; - uint32_t timerClock = srcClock_Hz / (base->PR + 1U); - uint32_t index = CTIMER_GetInstance(base); - - if (matchChannel == pwmPeriodChannel) - { - return kStatus_Fail; - } - - /* Enable PWM mode on the match channel */ - base->PWMC |= (1UL << (uint32_t)matchChannel); - - /* Clear the stop, reset and interrupt bits for this channel */ - reg = base->MCR; - reg &= - ~(((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK)) - << ((uint32_t)matchChannel * 3U)); - - /* If call back function is valid then enable match interrupt for the channel */ - if (enableInt) - { - reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); - } - - /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ - reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); - - base->MCR = reg; - - /* Calculate PWM period match value */ - period = (timerClock / pwmFreq_Hz) - 1U; - - /* Calculate pulse width match value */ - if (dutyCyclePercent == 0U) - { - pulsePeriod = period + 1U; - } - else - { - pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; - } - - /* Specified channel pwmPeriodChannel will define the PWM period */ - base->MR[pwmPeriodChannel] = period; - - /* This will define the PWM pulse period */ - base->MR[matchChannel] = pulsePeriod; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); - /* If call back function is valid then enable interrupt and update the call back function */ - if (enableInt) - { - (void)EnableIRQ(s_ctimerIRQ[index]); - } - - return kStatus_Success; -} - -/*! - * brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function can manually assign the specified channel to set the PWM cycle. - * - * note When setting PWM output from multiple output pins, all should use the same PWM - * period - * - * param base Ctimer peripheral base address - * param pwmPeriodChannel Specify the channel to control the PWM period - * param matchChannel Match pin to be used to output the PWM signal - * param pwmPeriod PWM period match value - * param pulsePeriod Pulse width match value - * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt will be generated. - * - * return kStatus_Success on success - * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM period - */ -status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint32_t pwmPeriod, - uint32_t pulsePeriod, - bool enableInt) -{ -/* Some CTimers only have 16bits , so the value is limited*/ -#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B - assert(!((FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32) && (pulsePeriod > 0xFFFFU))); -#endif - - uint32_t reg; - uint32_t index = CTIMER_GetInstance(base); - - if (matchChannel == pwmPeriodChannel) - { - return kStatus_Fail; - } - - /* Enable PWM mode on PWM pulse channel */ - base->PWMC |= (1UL << (uint32_t)matchChannel); - - /* Clear the stop, reset and interrupt bits for PWM pulse channel */ - reg = base->MCR; - reg &= - ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) - << ((uint32_t)matchChannel * 3U)); - - /* If call back function is valid then enable match interrupt for PWM pulse channel */ - if (enableInt) - { - reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); - } - - /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ - reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); - - base->MCR = reg; - - /* Specified channel pwmPeriodChannel will define the PWM period */ - base->MR[pwmPeriodChannel] = pwmPeriod; - - /* This will define the PWM pulse period */ - base->MR[matchChannel] = pulsePeriod; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); - /* If call back function is valid then enable interrupt and update the call back function */ - if (enableInt) - { - (void)EnableIRQ(s_ctimerIRQ[index]); - } - - return kStatus_Success; -} - -/*! - * brief Updates the duty cycle of an active PWM signal. - * - * note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. - * This function can manually assign the specified channel to set the PWM cycle. - * - * param base Ctimer peripheral base address - * param pwmPeriodChannel Specify the channel to control the PWM period - * param matchChannel Match pin to be used to output the PWM signal - * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 - */ -void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent) -{ - uint32_t pulsePeriod = 0, period; - - /* Specified channel pwmPeriodChannel defines the PWM period */ - period = base->MR[pwmPeriodChannel]; - - /* For 0% dutycyle, make pulse period greater than period so the event will never occur */ - if (dutyCyclePercent == 0U) - { - pulsePeriod = period + 1U; - } - else - { - pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; - } - - /* Update dutycycle */ - base->MR[matchChannel] = pulsePeriod; -} - -/*! - * brief Setup the match register. - * - * User configuration is used to setup the match value and action to be taken when a match occurs. - * - * param base Ctimer peripheral base address - * param matchChannel Match register to configure - * param config Pointer to the match configuration structure - */ -void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config) -{ -/* Some CTimers only have 16bits , so the value is limited*/ -#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B - assert(!(FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32 && config->matchValue > 0xFFFFU)); -#endif - uint32_t reg; - uint32_t index = CTIMER_GetInstance(base); - - /* Set the counter operation when a match on this channel occurs */ - reg = base->MCR; - reg &= - ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) - << ((uint32_t)matchChannel * 3U)); - reg |= ((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)matchChannel * 3U))); - reg |= ((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)matchChannel * 3U))); - reg |= ((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); - base->MCR = reg; - - reg = base->EMR; - /* Set the match output operation when a match on this channel occurs */ - reg &= ~(((uint32_t)CTIMER_EMR_EMC0_MASK) << ((uint32_t)matchChannel * 2U)); - reg |= ((uint32_t)config->outControl) << (CTIMER_EMR_EMC0_SHIFT + ((uint32_t)matchChannel * 2U)); - - /* Set the initial state of the EM bit/output */ - reg &= ~(((uint32_t)CTIMER_EMR_EM0_MASK) << (uint32_t)matchChannel); - reg |= ((uint32_t)config->outPinInitState) << (uint32_t)matchChannel; - base->EMR = reg; - - /* Set the match value */ - base->MR[matchChannel] = config->matchValue; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); - /* If interrupt is enabled then enable interrupt and update the call back function */ - if (config->enableInterrupt) - { - (void)EnableIRQ(s_ctimerIRQ[index]); - } -} - -/*! - * brief Get the status of output match. - * - * This function gets the status of output MAT, whether or not this output is connected to a pin. - * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - * - * param base Ctimer peripheral base address - * param matchChannel External match channel, user can obtain the status of multiple match channels - * at the same time by using the logic of "|" - * enumeration ::ctimer_external_match_t - * return The mask of external match channel status flags. Users need to use the - * _ctimer_external_match type to decode the return variables. - */ -uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel) -{ - return (base->EMR & matchChannel); -} - -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) -/*! - * brief Setup the capture. - * - * param base Ctimer peripheral base address - * param capture Capture channel to configure - * param edge Edge on the channel that will trigger a capture - * param enableInt Flag to enable channel interrupts, if enabled then the registered call back - * is called upon capture - */ -void CTIMER_SetupCapture(CTIMER_Type *base, - ctimer_capture_channel_t capture, - ctimer_capture_edge_t edge, - bool enableInt) -{ - uint32_t reg = base->CCR; - uint32_t index = CTIMER_GetInstance(base); - - /* Set the capture edge */ - reg &= ~((uint32_t)((uint32_t)CTIMER_CCR_CAP0RE_MASK | (uint32_t)CTIMER_CCR_CAP0FE_MASK | - (uint32_t)CTIMER_CCR_CAP0I_MASK) - << ((uint32_t)capture * 3U)); - reg |= ((uint32_t)edge) << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U)); - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, (((uint32_t)kCTIMER_Capture0Flag) << (uint32_t)capture)); - /* If call back function is valid then enable capture interrupt for the channel and update the call back function */ - if (enableInt) - { - reg |= ((uint32_t)CTIMER_CCR_CAP0I_MASK) << ((uint32_t)capture * 3U); - (void)EnableIRQ(s_ctimerIRQ[index]); - } - base->CCR = reg; -} -#endif - -/*! - * brief Register callback. - * - * param base Ctimer peripheral base address - * param cb_func callback function - * param cb_type callback function type, singular or multiple - */ -void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type) -{ - uint32_t index = CTIMER_GetInstance(base); - s_ctimerCallback[index] = cb_func; - ctimerCallbackType[index] = cb_type; -} - -/*! - * brief CTIMER generic IRQ handle function. - * - * param index FlexCAN peripheral instance index. - */ -static void CTIMER_GenericIRQHandler(uint32_t index) -{ - uint32_t int_stat, i, mask; - /* Get Interrupt status flags */ - int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]); - /* Clear the status flags that were set */ - CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat); - if (ctimerCallbackType[index] == kCTIMER_SingleCallback) - { - if (s_ctimerCallback[index][0] != NULL) - { - s_ctimerCallback[index][0](int_stat); - } - } - else - { -#if defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE - for (i = 0; i <= CTIMER_IR_MR3INT_SHIFT; i++) -#else -#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT - for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) -#else -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) - for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) -#else - for (i = 0; i <= CTIMER_IR_CR1INT_SHIFT; i++) -#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ -#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ -#endif - { - mask = 0x01UL << i; - /* For each status flag bit that was set call the callback function if it is valid */ - if (((int_stat & mask) != 0U) && (s_ctimerCallback[index][i] != NULL)) - { - s_ctimerCallback[index][i](int_stat); - } - } - } - SDK_ISR_EXIT_BARRIER; -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(CTIMER0) -void CTIMER0_DriverIRQHandler(void); -void CTIMER0_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(0); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CTIMER1) -void CTIMER1_DriverIRQHandler(void); -void CTIMER1_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(1); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CTIMER2) -void CTIMER2_DriverIRQHandler(void); -void CTIMER2_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(2); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CTIMER3) -void CTIMER3_DriverIRQHandler(void); -void CTIMER3_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(3); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CTIMER4) -void CTIMER4_DriverIRQHandler(void); -void CTIMER4_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(4); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_ctimer.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_ctimer.h deleted file mode 100644 index ca39c95d30e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_ctimer.h +++ /dev/null @@ -1,533 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_CTIMER_H_ -#define _FSL_CTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup ctimer - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) /*!< Version 2.2.2 */ -/*@}*/ - -/*! @brief List of Timer capture channels */ -typedef enum _ctimer_capture_channel -{ - kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ - kCTIMER_Capture_1, /*!< Timer capture channel 1 */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - kCTIMER_Capture_2, /*!< Timer capture channel 2 */ -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - kCTIMER_Capture_3 /*!< Timer capture channel 3 */ -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ -} ctimer_capture_channel_t; - -/*! @brief List of capture edge options */ -typedef enum _ctimer_capture_edge -{ - kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */ - kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */ - kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */ -} ctimer_capture_edge_t; - -/*! @brief List of Timer match registers */ -typedef enum _ctimer_match -{ - kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */ - kCTIMER_Match_1, /*!< Timer match register 1 */ - kCTIMER_Match_2, /*!< Timer match register 2 */ - kCTIMER_Match_3 /*!< Timer match register 3 */ -} ctimer_match_t; - -/*! @brief List of external match */ -typedef enum _ctimer_external_match -{ - kCTIMER_External_Match_0 = (1U << 0), /*!< External match 0 */ - kCTIMER_External_Match_1 = (1U << 1), /*!< External match 1 */ - kCTIMER_External_Match_2 = (1U << 2), /*!< External match 2 */ - kCTIMER_External_Match_3 = (1U << 3) /*!< External match 3 */ -} ctimer_external_match_t; - -/*! @brief List of output control options */ -typedef enum _ctimer_match_output_control -{ - kCTIMER_Output_NoAction = 0U, /*!< No action is taken */ - kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */ - kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */ - kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */ -} ctimer_match_output_control_t; - -/*! @brief List of Timer modes */ -typedef enum _ctimer_timer_mode -{ - kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */ - kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */ - kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */ - kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */ -} ctimer_timer_mode_t; - -/*! @brief List of Timer interrupts */ -typedef enum _ctimer_interrupt_enable -{ - kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ - kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ - kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ - kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ - kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ -#endif -} ctimer_interrupt_enable_t; - -/*! @brief List of Timer flags */ -typedef enum _ctimer_status_flags -{ - kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ - kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ - kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ - kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ - kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) - kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ -#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ -#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT - kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ -#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ -#endif -} ctimer_status_flags_t; - -typedef void (*ctimer_callback_t)(uint32_t flags); - -/*! @brief Callback type when registering for a callback. When registering a callback - * an array of function pointers is passed the size could be 1 or 8, the callback - * type will tell that. - */ -typedef enum -{ - kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. - based on the status flags different channels needs to be handled differently */ - kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. - for both match/capture */ -} ctimer_callback_type_t; - -/*! - * @brief Match configuration - * - * This structure holds the configuration settings for each match register. - */ -typedef struct _ctimer_match_config -{ - uint32_t matchValue; /*!< This is stored in the match register */ - bool enableCounterReset; /*!< true: Match will reset the counter - false: Match will not reser the counter */ - bool enableCounterStop; /*!< true: Match will stop the counter - false: Match will not stop the counter */ - ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */ - bool outPinInitState; /*!< Initial value of the EM bit/output */ - bool enableInterrupt; /*!< true: Generate interrupt upon match - false: Do not generate interrupt on match */ - -} ctimer_match_config_t; - -/*! - * @brief Timer configuration structure - * - * This structure holds the configuration settings for the Timer peripheral. To initialize this - * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a - * pointer to the configuration structure instance. - * - * The configuration structure can be made constant so as to reside in flash. - */ -typedef struct _ctimer_config -{ - ctimer_timer_mode_t mode; /*!< Timer mode */ - ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer - modes that rely on this input signal to increment TC */ - uint32_t prescale; /*!< Prescale value */ -} ctimer_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application before using the driver. - * - * @param base Ctimer peripheral base address - * @param config Pointer to the user configuration structure. - */ -void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config); - -/*! - * @brief Gates the timer clock. - * - * @param base Ctimer peripheral base address - */ -void CTIMER_Deinit(CTIMER_Type *base); - -/*! - * @brief Fills in the timers configuration structure with the default settings. - * - * The default values are: - * @code - * config->mode = kCTIMER_TimerMode; - * config->input = kCTIMER_Capture_0; - * config->prescale = 0; - * @endcode - * @param config Pointer to the user configuration structure. - */ -void CTIMER_GetDefaultConfig(ctimer_config_t *config); - -/*! @}*/ - -/*! - * @name PWM setup operations - * @{ - */ - -/*! - * @brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function can manually assign the specified channel to set the PWM cycle. - * - * @note When setting PWM output from multiple output pins, all should use the same PWM - * period - * - * @param base Ctimer peripheral base address - * @param pwmPeriodChannel Specify the channel to control the PWM period - * @param matchChannel Match pin to be used to output the PWM signal - * @param pwmPeriod PWM period match value - * @param pulsePeriod Pulse width match value - * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt will be generated. - */ -status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint32_t pwmPeriod, - uint32_t pulsePeriod, - bool enableInt); - -/*! - * @brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function can manually assign the specified channel to set the PWM cycle. - * - * @note When setting PWM output from multiple output pins, all should use the same PWM - * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. - * - * @param base Ctimer peripheral base address - * @param pwmPeriodChannel Specify the channel to control the PWM period - * @param matchChannel Match pin to be used to output the PWM signal - * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz Timer counter clock in Hz - * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt will be generated. - */ -status_t CTIMER_SetupPwm(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - bool enableInt); - -/*! - * @brief Updates the pulse period of an active PWM signal. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match pin to be used to output the PWM signal - * @param pulsePeriod New PWM pulse width match value - */ -static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod) -{ - /* Update PWM pulse period match value */ - base->MR[matchChannel] = pulsePeriod; -} - -/*! - * @brief Updates the duty cycle of an active PWM signal. - * - * @note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. - * This function can manually assign the specified channel to set the PWM cycle. - * - * @param base Ctimer peripheral base address - * @param pwmPeriodChannel Specify the channel to control the PWM period - * @param matchChannel Match pin to be used to output the PWM signal - * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 - */ -void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent); - -/*! @}*/ - -/*! - * @brief Setup the match register. - * - * User configuration is used to setup the match value and action to be taken when a match occurs. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match register to configure - * @param config Pointer to the match configuration structure - */ -void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config); - -/*! - * @brief Get the status of output match. - * - * This function gets the status of output MAT, whether or not this output is connected to a pin. - * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - * - * @param base Ctimer peripheral base address - * @param matchChannel External match channel, user can obtain the status of multiple match channels - * at the same time by using the logic of "|" - * enumeration ::ctimer_external_match_t - * @return The mask of external match channel status flags. Users need to use the - * _ctimer_external_match type to decode the return variables. - */ -uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel); - -/*! - * @brief Setup the capture. - * - * @param base Ctimer peripheral base address - * @param capture Capture channel to configure - * @param edge Edge on the channel that will trigger a capture - * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back - * is called upon capture - */ -void CTIMER_SetupCapture(CTIMER_Type *base, - ctimer_capture_channel_t capture, - ctimer_capture_edge_t edge, - bool enableInt); - -/*! - * @brief Get the timer count value from TC register. - * - * @param base Ctimer peripheral base address. - * @return return the timer count value. - */ -static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base) -{ - return (base->TC); -} - -/*! - * @brief Register callback. - * - * @param base Ctimer peripheral base address - * @param cb_func callback function - * @param cb_type callback function type, singular or multiple - */ -void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type); - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected Timer interrupts. - * - * @param base Ctimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) -{ - /* Enable match interrupts */ - base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); - -/* Enable capture interrupts */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - | CTIMER_CCR_CAP2I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - ); -#endif -} - -/*! - * @brief Disables the selected Timer interrupts. - * - * @param base Ctimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) -{ - /* Disable match interrupts */ - base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK)); - -/* Disable capture interrupts */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - | CTIMER_CCR_CAP2I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - )); -#endif -} - -/*! - * @brief Gets the enabled Timer interrupts. - * - * @param base Ctimer peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) -{ - uint32_t enabledIntrs = 0; - - /* Get all the match interrupts enabled */ - enabledIntrs = - base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); - -/* Get all the capture interrupts enabled */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - | CTIMER_CCR_CAP2I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - ); -#endif - - return enabledIntrs; -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the Timer status flags. - * - * @param base Ctimer peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::ctimer_status_flags_t - */ -static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base) -{ - return base->IR; -} - -/*! - * @brief Clears the Timer status flags. - * - * @param base Ctimer peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::ctimer_status_flags_t - */ -static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask) -{ - base->IR = mask; -} - -/*! @}*/ - -/*! - * @name Counter Start and Stop - * @{ - */ - -/*! - * @brief Starts the Timer counter. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_StartTimer(CTIMER_Type *base) -{ - base->TCR |= CTIMER_TCR_CEN_MASK; -} - -/*! - * @brief Stops the Timer counter. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_StopTimer(CTIMER_Type *base) -{ - base->TCR &= ~CTIMER_TCR_CEN_MASK; -} - -/*! @}*/ - -/*! - * @brief Reset the counter. - * - * The timer counter and prescale counter are reset on the next positive edge of the APB clock. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_Reset(CTIMER_Type *base) -{ - base->TCR |= CTIMER_TCR_CRST_MASK; - base->TCR &= ~CTIMER_TCR_CRST_MASK; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_CTIMER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_dma.c deleted file mode 100644 index 6b7bc594ad0..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_dma.c +++ /dev/null @@ -1,1079 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_dma.h" -#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) -#include "fsl_memory.h" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_dma" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for DMA. - * - * @param base DMA peripheral base address. - */ -static uint32_t DMA_GetInstance(DMA_Type *base); - -/*! - * @brief Get virtual channel number. - * - * @param base DMA peripheral base address. - */ -static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map DMA instance number to base pointer. */ -static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map DMA instance number to clock name. */ -static const clock_ip_name_t s_dmaClockName[] = DMA_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET) -/*! @brief Pointers to DMA resets for each instance. */ -static const reset_ip_name_t s_dmaResets[] = DMA_RSTS_N; -#endif /*! @brief Array to map DMA instance number to IRQ number. */ -static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS; - -/*! @brief Pointers to transfer handle for each DMA channel. */ -static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_ALL_CHANNELS]; - -/*! @brief DMA driver internal descriptor table */ -#ifdef FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE -SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE); -#else -#if (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) -AT_NONCACHEABLE_SECTION_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -#else -SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -#endif /* (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) */ -#endif /* FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE */ - -#if defined(DMA1) -#ifdef FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE -SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE); -#else -#if (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) -AT_NONCACHEABLE_SECTION_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -#else -SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -#endif /* (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) */ -#endif /* FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE */ -static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0, s_dma_descriptor_table1}; -#else -static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0}; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t DMA_GetInstance(DMA_Type *base) -{ - uint32_t instance; - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++) - { - if (s_dmaBases[instance] == base) - { - break; - } - } - assert(instance < ARRAY_SIZE(s_dmaBases)); - - return instance; -} - -static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base) -{ - uint32_t startChannel = 0, instance = 0; - uint32_t i = 0; - - instance = DMA_GetInstance(base); - - /* Compute start channel */ - for (i = 0; i < instance; i++) - { - startChannel += (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(s_dmaBases[i]); - } - - return startChannel; -} - -/*! - * brief Initializes DMA peripheral. - * - * This function enable the DMA clock, set descriptor table and - * enable DMA peripheral. - * - * param base DMA peripheral base address. - */ -void DMA_Init(DMA_Type *base) -{ - uint32_t instance = DMA_GetInstance(base); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* enable dma clock gate */ - CLOCK_EnableClock(s_dmaClockName[DMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET) - /* Reset the DMA module */ - RESET_PeripheralReset(s_dmaResets[DMA_GetInstance(base)]); -#endif - /* set descriptor table */ -#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) - base->SRAMBASE = MEMORY_ConvertMemoryMapAddress((uint32_t)s_dma_descriptor_table[instance], kMEMORY_Local2DMA); -#else - base->SRAMBASE = (uint32_t)s_dma_descriptor_table[instance]; -#endif - /* enable dma peripheral */ - base->CTRL |= DMA_CTRL_ENABLE_MASK; -} - -/*! - * brief Deinitializes DMA peripheral. - * - * This function gates the DMA clock. - * - * param base DMA peripheral base address. - */ -void DMA_Deinit(DMA_Type *base) -{ - /* Disable DMA peripheral */ - base->CTRL &= ~(DMA_CTRL_ENABLE_MASK); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(s_dmaClockName[DMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Set trigger settings of DMA channel. - * deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig. - * - * param base DMA peripheral base address. - * param channel DMA channel number. - * param trigger trigger configuration. - */ -void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger) -{ - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); - assert((channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)) && (NULL != trigger)); - - uint32_t tmpReg = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | - DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | - DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK); - tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); - tmpReg |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); - base->CHANNEL[channel].CFG = tmpReg; -} - -/*! - * brief Gets the remaining bytes of the current DMA descriptor transfer. - * - * param base DMA peripheral base address. - * param channel DMA channel number. - * return The number of bytes which have not been transferred yet. - */ -uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) -{ - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); - assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - - /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes - * impossible to distinguish between: - * - transfer finishes (represented by value '0x3FF') - * - and remaining 1024 bytes to transfer (value 0x3FF) - * for all descriptor in chain, except the last one. - * If you decide to use this function, please use 1023 transfers as maximal value */ - - /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */ - if ((!DMA_ChannelIsActive(base, channel)) && - (0x3FFUL == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> - DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))) - { - return 0UL; - } - - return ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> - DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + - 1UL; -} - -/* Verify and convert dma_xfercfg_t to XFERCFG register */ -static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr) -{ - assert(xfercfg != NULL); - /* check source increment */ - assert((xfercfg->srcInc <= (uint8_t)kDMA_AddressInterleave4xWidth) && - (xfercfg->dstInc <= (uint8_t)kDMA_AddressInterleave4xWidth)); - /* check data width */ - assert(xfercfg->byteWidth <= (uint8_t)kDMA_Transfer32BitWidth); - /* check transfer count */ - assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT); - - uint32_t xfer = 0; - - /* set valid flag - descriptor is ready now */ - xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid); - /* set reload - allow link to next descriptor */ - xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload); - /* set swtrig flag - start transfer */ - xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig); - /* set transfer count */ - xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig); - /* set INTA */ - xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA); - /* set INTB */ - xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB); - /* set data width */ - xfer |= DMA_CHANNEL_XFERCFG_WIDTH(xfercfg->byteWidth == 4U ? 2U : xfercfg->byteWidth - 1UL); - /* set source increment value */ - xfer |= DMA_CHANNEL_XFERCFG_SRCINC( - (xfercfg->srcInc == (uint8_t)kDMA_AddressInterleave4xWidth) ? (xfercfg->srcInc - 1UL) : xfercfg->srcInc); - /* set destination increment value */ - xfer |= DMA_CHANNEL_XFERCFG_DSTINC( - (xfercfg->dstInc == (uint8_t)kDMA_AddressInterleave4xWidth) ? (xfercfg->dstInc - 1UL) : xfercfg->dstInc); - /* set transfer count */ - xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1UL); - - /* store xferCFG */ - *xfercfg_addr = xfer; -} - -/*! - * brief setup dma descriptor - * Note: This function do not support configure wrap descriptor. - * param desc DMA descriptor address. - * param xfercfg Transfer configuration for DMA descriptor. - * param srcStartAddr Start address of source address. - * param dstStartAddr Start address of destination address. - * param nextDesc Address of next descriptor in chain. - */ -void DMA_SetupDescriptor( - dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) -{ - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - -#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) - srcStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)srcStartAddr, kMEMORY_Local2DMA); - dstStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)dstStartAddr, kMEMORY_Local2DMA); - nextDesc = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)nextDesc, kMEMORY_Local2DMA); -#endif - - uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; - - width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT; - srcInc = (xfercfg & DMA_CHANNEL_XFERCFG_SRCINC_MASK) >> DMA_CHANNEL_XFERCFG_SRCINC_SHIFT; - dstInc = (xfercfg & DMA_CHANNEL_XFERCFG_DSTINC_MASK) >> DMA_CHANNEL_XFERCFG_DSTINC_SHIFT; - transferCount = ((xfercfg & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1U; - - /* covert register value to actual value */ - if (width == 2U) - { - width = kDMA_Transfer32BitWidth; - } - else - { - width += 1U; - } - - /* - * Transfers of 16 bit width require an address alignment to a multiple of 2 bytes. - * Transfers of 32 bit width require an address alignment to a multiple of 4 bytes. - * Transfers of 8 bit width can be at any address - */ - if (((NULL != srcStartAddr) && (0UL == ((uint32_t)(uint32_t *)srcStartAddr) % width)) && - ((NULL != dstStartAddr) && (0UL == ((uint32_t)(uint32_t *)dstStartAddr) % width))) - { - if (srcInc == 3U) - { - srcInc = kDMA_AddressInterleave4xWidth; - } - - if (dstInc == 3U) - { - dstInc = kDMA_AddressInterleave4xWidth; - } - - desc->xfercfg = xfercfg; - desc->srcEndAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); - desc->dstEndAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); - desc->linkToNextDesc = nextDesc; - } - else - { - /* if address alignment not satisfy the requirement, reset the descriptor to make sure DMA generate error */ - desc->xfercfg = 0U; - desc->srcEndAddr = NULL; - desc->dstEndAddr = NULL; - } -} - -/*! - * brief setup dma channel descriptor - * Note: This function support configure wrap descriptor. - * param desc DMA descriptor address. - * param xfercfg Transfer configuration for DMA descriptor. - * param srcStartAddr Start address of source address. - * param dstStartAddr Start address of destination address. - * param nextDesc Address of next descriptor in chain. - * param wrapType burst wrap type. - * param burstSize burst size, reference _dma_burst_size. - */ -void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, - uint32_t xfercfg, - void *srcStartAddr, - void *dstStartAddr, - void *nextDesc, - dma_burst_wrap_t wrapType, - uint32_t burstSize) -{ - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - -#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) - srcStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)srcStartAddr, kMEMORY_Local2DMA); - dstStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)dstStartAddr, kMEMORY_Local2DMA); - nextDesc = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)nextDesc, kMEMORY_Local2DMA); -#endif - - uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; - - width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT; - srcInc = (xfercfg & DMA_CHANNEL_XFERCFG_SRCINC_MASK) >> DMA_CHANNEL_XFERCFG_SRCINC_SHIFT; - dstInc = (xfercfg & DMA_CHANNEL_XFERCFG_DSTINC_MASK) >> DMA_CHANNEL_XFERCFG_DSTINC_SHIFT; - transferCount = ((xfercfg & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1U; - - /* covert register value to actual value */ - if (width == 2U) - { - width = kDMA_Transfer32BitWidth; - } - else - { - width += 1U; - } - - /* - * Transfers of 16 bit width require an address alignment to a multiple of 2 bytes. - * Transfers of 32 bit width require an address alignment to a multiple of 4 bytes. - * Transfers of 8 bit width can be at any address - */ - if (((NULL != srcStartAddr) && (0UL == ((uint32_t)(uint32_t *)srcStartAddr) % width)) && - ((NULL != dstStartAddr) && (0UL == ((uint32_t)(uint32_t *)dstStartAddr) % width))) - { - if (srcInc == 3U) - { - srcInc = kDMA_AddressInterleave4xWidth; - } - - if (dstInc == 3U) - { - dstInc = kDMA_AddressInterleave4xWidth; - } - - desc->xfercfg = xfercfg; - - if (wrapType == kDMA_NoWrap) - { - desc->srcEndAddr = - DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); - desc->dstEndAddr = - DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); - } - /* for the wrap transfer, the destination address should be determined by the burstSize/width/interleave size */ - if (wrapType == kDMA_SrcWrap) - { - desc->srcEndAddr = - (uint32_t *)((uint32_t)(uint32_t *)srcStartAddr + ((1UL << burstSize) - 1UL) * width * srcInc); - desc->dstEndAddr = - DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); - } - if (wrapType == kDMA_DstWrap) - { - desc->srcEndAddr = - DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); - desc->dstEndAddr = - (uint32_t *)((uint32_t)(uint32_t *)dstStartAddr + ((1UL << burstSize) - 1UL) * width * dstInc); - } - if (wrapType == kDMA_SrcAndDstWrap) - { - desc->srcEndAddr = - (uint32_t *)(((uint32_t)(uint32_t *)srcStartAddr) + ((1UL << burstSize) - 1UL) * width * srcInc); - desc->dstEndAddr = - (uint32_t *)(((uint32_t)(uint32_t *)dstStartAddr) + ((1UL << burstSize) - 1UL) * width * dstInc); - } - - desc->linkToNextDesc = nextDesc; - } - else - { - /* if address alignment not satisfy the requirement, reset the descriptor to make sure DMA generate error */ - desc->xfercfg = 0U; - desc->srcEndAddr = NULL; - desc->dstEndAddr = NULL; - } -} - -/*! - * brief Create application specific DMA descriptor - * to be used in a chain in transfer - * deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor - * param desc DMA descriptor address. - * param xfercfg Transfer configuration for DMA descriptor. - * param srcAddr Address of last item to transmit - * param dstAddr Address of last item to receive. - * param nextDesc Address of next descriptor in chain. - */ -void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc) -{ - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - assert((NULL != srcAddr) && (0UL == ((uint32_t)(uint32_t *)srcAddr) % xfercfg->byteWidth)); - assert((NULL != dstAddr) && (0UL == ((uint32_t)(uint32_t *)dstAddr) % xfercfg->byteWidth)); - - uint32_t xfercfg_reg = 0; - - DMA_SetupXferCFG(xfercfg, &xfercfg_reg); - - /* Set descriptor structure */ - DMA_SetupDescriptor(desc, xfercfg_reg, srcAddr, dstAddr, nextDesc); -} - -/*! - * brief Abort running transfer by handle. - * - * This function aborts DMA transfer specified by handle. - * - * param handle DMA handle pointer. - */ -void DMA_AbortTransfer(dma_handle_t *handle) -{ - assert(NULL != handle); - - DMA_DisableChannel(handle->base, handle->channel); - while ((DMA_COMMON_CONST_REG_GET(handle->base, handle->channel, BUSY) & - (1UL << DMA_CHANNEL_INDEX(handle->base, handle->channel))) != 0UL) - { - } - DMA_COMMON_REG_GET(handle->base, handle->channel, ABORT) |= 1UL << DMA_CHANNEL_INDEX(handle->base, handle->channel); - DMA_EnableChannel(handle->base, handle->channel); -} - -/*! - * brief Creates the DMA handle. - * - * This function is called if using transaction API for DMA. This function - * initializes the internal state of DMA handle. - * - * param handle DMA handle pointer. The DMA handle stores callback function and - * parameters. - * param base DMA peripheral base address. - * param channel DMA channel number. - */ -void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel) -{ - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); - assert((NULL != handle) && (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - - uint32_t dmaInstance; - uint32_t startChannel = 0; - /* base address is invalid DMA instance */ - dmaInstance = DMA_GetInstance(base); - startChannel = DMA_GetVirtualStartChannel(base); - - (void)memset(handle, 0, sizeof(*handle)); - handle->base = base; - handle->channel = (uint8_t)channel; - s_DMAHandle[startChannel + channel] = handle; - /* Enable NVIC interrupt */ - (void)EnableIRQ(s_dmaIRQNumber[dmaInstance]); - /* Enable channel interrupt */ - DMA_EnableChannelInterrupts(handle->base, channel); -} - -/*! - * brief Installs a callback function for the DMA transfer. - * - * This callback is called in DMA IRQ handler. Use the callback to do something after - * the current major loop transfer completes. - * - * param handle DMA handle pointer. - * param callback DMA callback function pointer. - * param userData Parameter for callback function. - */ -void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData) -{ - assert(handle != NULL); - - handle->callback = callback; - handle->userData = userData; -} - -/*! - * brief Prepares the DMA transfer structure. - * deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer and - * DMA_PrepareChannelXfer. - * This function prepares the transfer configuration structure according to the user input. - * - * param config The user configuration structure of type dma_transfer_t. - * param srcAddr DMA transfer source address. - * param dstAddr DMA transfer destination address. - * param byteWidth DMA transfer destination address width(bytes). - * param transferBytes DMA transfer bytes to be transferred. - * param type DMA transfer type. - * param nextDesc Chain custom descriptor to transfer. - * note The data address and the data width must be consistent. For example, if the SRC - * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in - * source address error(SAE). - */ -void DMA_PrepareTransfer(dma_transfer_config_t *config, - void *srcAddr, - void *dstAddr, - uint32_t byteWidth, - uint32_t transferBytes, - dma_transfer_type_t type, - void *nextDesc) -{ - uint32_t xfer_count; - assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr)); - assert((byteWidth == 1UL) || (byteWidth == 2UL) || (byteWidth == 4UL)); - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - - /* check max */ - xfer_count = transferBytes / byteWidth; - assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0UL == transferBytes % byteWidth)); - - (void)memset(config, 0, sizeof(*config)); - - if (type == kDMA_MemoryToMemory) - { - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 1; - config->isPeriph = false; - } - - else if (type == kDMA_PeripheralToMemory) - { - /* Peripheral register - source doesn't increment */ - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 1; - config->isPeriph = true; - } - else if (type == kDMA_MemoryToPeripheral) - { - /* Peripheral register - destination doesn't increment */ - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - } - /* kDMA_StaticToStatic */ - else - { - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - } - - config->dstAddr = (uint8_t *)dstAddr; - config->srcAddr = (uint8_t *)srcAddr; - config->nextDesc = (uint8_t *)nextDesc; - config->xfercfg.transferCount = (uint16_t)xfer_count; - config->xfercfg.byteWidth = (uint8_t)byteWidth; - config->xfercfg.intA = true; - config->xfercfg.reload = nextDesc != NULL; - config->xfercfg.valid = true; -} - -/*! - * brief set channel config. - * - * This function provide a interface to configure channel configuration reisters. - * - * param base DMA base address. - * param channel DMA channel number. - * param config channel configurations structure. - */ -void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph) -{ - assert(channel < (uint32_t)FSL_FEATURE_DMA_MAX_CHANNELS); - - uint32_t tmpReg = DMA_CHANNEL_CFG_PERIPHREQEN_MASK; - - if (trigger != NULL) - { - tmpReg |= DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | - DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | - DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK; - } - - tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); - - if (trigger != NULL) - { - tmpReg |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); - } - - tmpReg |= DMA_CHANNEL_CFG_PERIPHREQEN(isPeriph); - - base->CHANNEL[channel].CFG = tmpReg; -} - -/*! - * brief Prepare channel transfer configurations. - * - * This function used to prepare channel transfer configurations. - * - * param config Pointer to DMA channel transfer configuration structure. - * param srcStartAddr source start address. - * param dstStartAddr destination start address. - * param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * param type transfer type. - * param trigger DMA channel trigger configurations. - * param nextDesc address of next descriptor. - */ -void DMA_PrepareChannelTransfer(dma_channel_config_t *config, - void *srcStartAddr, - void *dstStartAddr, - uint32_t xferCfg, - dma_transfer_type_t type, - dma_channel_trigger_t *trigger, - void *nextDesc) -{ - assert((NULL != config) && (NULL != srcStartAddr) && (NULL != dstStartAddr)); - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - - /* check max */ - (void)memset(config, 0, sizeof(*config)); - - if (type == kDMA_MemoryToMemory) - { - config->isPeriph = false; - } - else if (type == kDMA_PeripheralToMemory) - { - config->isPeriph = true; - } - else if (type == kDMA_MemoryToPeripheral) - { - config->isPeriph = true; - } - /* kDMA_StaticToStatic */ - else - { - config->isPeriph = true; - } - - config->dstStartAddr = (uint8_t *)dstStartAddr; - config->srcStartAddr = (uint8_t *)srcStartAddr; - config->nextDesc = (uint8_t *)nextDesc; - config->trigger = trigger; - config->xferCfg = xferCfg; -} - -/*! - * brief load channel transfer decriptor. - * - * This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA - * transfer, the head descriptor table is defined in DMA driver, it is useful for the case: - * 1. for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly - * and then call this api to load the configured descriptor to driver descriptor table. code DMA_Init(DMA0); - * DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL); - * DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL); - * DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc); - * DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL); - * while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL)) - * {} - * endcode - * - * param base DMA base address. - * param channel DMA channel. - * param descriptor configured DMA descriptor. - */ -void DMA_LoadChannelDescriptor(DMA_Type *base, uint32_t channel, dma_descriptor_t *descriptor) -{ - assert(NULL != descriptor); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); - assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - - uint32_t instance = DMA_GetInstance(base); - dma_descriptor_t *channelDescriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][channel]); - - channelDescriptor->xfercfg = descriptor->xfercfg; - channelDescriptor->srcEndAddr = descriptor->srcEndAddr; - channelDescriptor->dstEndAddr = descriptor->dstEndAddr; - channelDescriptor->linkToNextDesc = descriptor->linkToNextDesc; - - /* Set channel XFERCFG register according first channel descriptor. */ - base->CHANNEL[channel].XFERCFG = descriptor->xfercfg; -} - -/*! - * brief Install DMA descriptor memory. - * - * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong - * transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has - * a default DMA descriptor buffer, but it support one DMA descriptor for one channel only. - * User should be take care about the address of DMA descriptor pool which required align with 512BYTE. - * - * param handle Pointer to DMA channel transfer handle. - * param addr DMA descriptor address - * param num DMA descriptor number. - */ -void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr) -{ - assert(addr != NULL); - -#if defined FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn - assert((((uint32_t)(uint32_t *)addr) & ((uint32_t)FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn(base) - 1UL)) == 0U); -#else - assert((((uint32_t)(uint32_t *)addr) & ((uint32_t)FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0U); -#endif - /* reconfigure the DMA descriptor base address */ - base->SRAMBASE = (uint32_t)(uint32_t *)addr; -} - -/*! - * brief Submit channel transfer paramter directly. - * - * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table - * is defined in DMA driver, it is useful for the case: - * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used - for it. - * code - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, - bytes), srcStartAddr, dstStartAddr, NULL); - DMA_StartTransfer(handle) - * endcode - * - * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is - required, then application should prepare - * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc2); - DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, NULL); - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, - bytes), srcStartAddr, dstStartAddr, nextDesc0); - DMA_StartTransfer(handle); - * endcode - * - * param handle Pointer to DMA handle. - * param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * param srcStartAddr source start address. - * param dstStartAddr destination start address. - * param nextDesc address of next descriptor. - */ -void DMA_SubmitChannelTransferParameter( - dma_handle_t *handle, uint32_t xferCfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) -{ - assert((NULL != srcStartAddr) && (NULL != dstStartAddr)); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); - assert(handle->channel < (uint8_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - - uint32_t instance = DMA_GetInstance(handle->base); - dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); - - DMA_SetupDescriptor(descriptor, xferCfg, srcStartAddr, dstStartAddr, nextDesc); - - /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = xferCfg; -} - -/*! - * brief Submit channel descriptor. - * - * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table - is defined in - * DMA driver, this functiono is typical for the ping pong case: - * - * 1. for the ping pong case, application should responsible for the descriptor, for example, application should - * prepare two descriptor table with macro. - * code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc0); - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelDescriptor(handle, nextDesc0); - DMA_StartTransfer(handle); - * endcode - * - * param handle Pointer to DMA handle. - * param descriptor descriptor to submit. - */ -void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descriptor) -{ - assert((NULL != handle) && (NULL != descriptor)); - - DMA_LoadChannelDescriptor(handle->base, handle->channel, descriptor); -} - -/*! - * brief Submits the DMA channel transfer request. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * It is used for the case: - * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used - for it. - * code - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,NULL); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * endcode - * - * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is - required, then application should prepare - * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc2); - DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, NULL); - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * endcode - * - * 3. for the ping pong case, application should responsible for link descriptor, for example, application should - prepare - * two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc0); - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * endcode - * param handle DMA handle pointer. - * param config Pointer to DMA transfer configuration structure. - * retval kStatus_DMA_Success It means submit transfer request succeed. - * retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config) -{ - assert((NULL != handle) && (NULL != config)); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); - assert(handle->channel < (uint8_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - uint32_t instance = DMA_GetInstance(handle->base); - dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); - - /* Previous transfer has not finished */ - if (DMA_ChannelIsActive(handle->base, handle->channel)) - { - return kStatus_DMA_Busy; - } - - /* setup channgel trigger configurations */ - DMA_SetChannelConfig(handle->base, handle->channel, config->trigger, config->isPeriph); - - DMA_SetupChannelDescriptor( - descriptor, config->xferCfg, config->srcStartAddr, config->dstStartAddr, config->nextDesc, - config->trigger == NULL ? kDMA_NoWrap : config->trigger->wrap, - (config->trigger == NULL ? (uint32_t)kDMA_BurstSize1 : - ((uint32_t)config->trigger->burst & (DMA_CHANNEL_CFG_BURSTPOWER_MASK)) >> - DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)); - - /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = config->xferCfg; - - return kStatus_Success; -} - -/*! - * brief Submits the DMA transfer request. - * deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * - * param handle DMA handle pointer. - * param config Pointer to DMA transfer configuration structure. - * retval kStatus_DMA_Success It means submit transfer request succeed. - * retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) -{ - assert((NULL != handle) && (NULL != config)); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); - assert(handle->channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - - uint32_t instance = DMA_GetInstance(handle->base); - dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); - - /* Previous transfer has not finished */ - if (DMA_ChannelIsActive(handle->base, handle->channel)) - { - return kStatus_DMA_Busy; - } - - /* enable/disable peripheral request */ - if (config->isPeriph) - { - DMA_EnableChannelPeriphRq(handle->base, handle->channel); - } - else - { - DMA_DisableChannelPeriphRq(handle->base, handle->channel); - } - - DMA_CreateDescriptor(descriptor, &config->xfercfg, config->srcAddr, config->dstAddr, config->nextDesc); - /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = descriptor->xfercfg; - - return kStatus_Success; -} - -/*! - * brief DMA start transfer. - * - * This function enables the channel request. User can call this function after submitting the transfer request - * It will trigger transfer start with software trigger only when hardware trigger is not used. - * - * param handle DMA handle pointer. - */ -void DMA_StartTransfer(dma_handle_t *handle) -{ - assert(NULL != handle); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); - - uint32_t channel = handle->channel; - assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - - /* enable channel */ - DMA_EnableChannel(handle->base, channel); - - /* Do software trigger only when HW trigger is not enabled. */ - if ((handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK) == 0U) - { - handle->base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; - } -} - -void DMA_IRQHandle(DMA_Type *base) -{ - dma_handle_t *handle; - uint8_t channel_index; - uint32_t startChannel = DMA_GetVirtualStartChannel(base); - uint32_t i = 0; - bool intEnabled = false, intA = false, intB = false; - - /* Find channels that have completed transfer */ - for (i = 0; i < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base); i++) - { - handle = s_DMAHandle[i + startChannel]; - /* Handle is not present */ - if (NULL == handle) - { - continue; - } - channel_index = DMA_CHANNEL_INDEX(base, handle->channel); - /* Channel uses INTA flag */ - intEnabled = ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTENSET) & (1UL << channel_index)) != 0UL); - intA = ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTA) & (1UL << channel_index)) != 0UL); - if (intEnabled && intA) - { - /* Clear INTA flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, INTA, (1UL << channel_index)); - if (handle->callback != NULL) - { - (handle->callback)(handle, handle->userData, true, kDMA_IntA); - } - } - - intB = ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTB) & (1UL << channel_index)) != 0UL); - /* Channel uses INTB flag */ - if (intEnabled && intB) - { - /* Clear INTB flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, INTB, (1UL << channel_index)); - if (handle->callback != NULL) - { - (handle->callback)(handle, handle->userData, true, kDMA_IntB); - } - } - /* Error flag */ - if ((DMA_COMMON_REG_GET(handle->base, handle->channel, ERRINT) & (1UL << channel_index)) != 0UL) - { - /* Clear error flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, ERRINT, (1UL << channel_index)); - if (handle->callback != NULL) - { - (handle->callback)(handle, handle->userData, false, kDMA_IntError); - } - } - } -} - -void DMA0_DriverIRQHandler(void); -void DMA0_DriverIRQHandler(void) -{ - DMA_IRQHandle(DMA0); - SDK_ISR_EXIT_BARRIER; -} - -#if defined(DMA1) -void DMA1_DriverIRQHandler(void); -void DMA1_DriverIRQHandler(void) -{ - DMA_IRQHandle(DMA1); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_dma.h deleted file mode 100644 index 0e857752e58..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_dma.h +++ /dev/null @@ -1,892 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_DMA_H_ -#define _FSL_DMA_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup dma - * @{ - */ - -/*! @file */ -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief DMA driver version */ -#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 4)) /*!< Version 2.4.4. */ -/*@}*/ - -/*! @brief DMA max transfer size */ -#define DMA_MAX_TRANSFER_COUNT 0x400U -/*! @brief DMA channel numbers */ -#if defined FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_MAX_CHANNELS FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_ALL_CHANNELS (FSL_FEATURE_DMA_NUMBER_OF_CHANNELS * FSL_FEATURE_SOC_DMA_COUNT) -#endif -/*! @brief DMA head link descriptor table align size */ -#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) -/*! @brief DMA head descriptor table allocate macro - * To simplify user interface, this macro will help allocate descriptor memory, - * user just need to provide the name and the number for the allocate descriptor. - * - * @param name Allocate decriptor name. - * @param number Number of descriptor to be allocated. - */ -#define DMA_ALLOCATE_HEAD_DESCRIPTORS(name, number) \ - SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE) -/*! @brief DMA head descriptor table allocate macro at noncacheable section - * To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, - * user just need to provide the name and the number for the allocate descriptor. - * - * @param name Allocate decriptor name. - * @param number Number of descriptor to be allocated. - */ -#define DMA_ALLOCATE_HEAD_DESCRIPTORS_AT_NONCACHEABLE(name, number) \ - AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE) -/*! @brief DMA link descriptor table allocate macro - * To simplify user interface, this macro will help allocate descriptor memory, - * user just need to provide the name and the number for the allocate descriptor. - * - * @param name Allocate decriptor name. - * @param number Number of descriptor to be allocated. - */ -#define DMA_ALLOCATE_LINK_DESCRIPTORS(name, number) \ - SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE) -/*! @brief DMA link descriptor table allocate macro at noncacheable section - * To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, - * user just need to provide the name and the number for the allocate descriptor. - * - * @param name Allocate decriptor name. - * @param number Number of descriptor to be allocated. - */ -#define DMA_ALLOCATE_LINK_DESCRIPTORS_AT_NONCACHEABLE(name, number) \ - AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE) -/*! @brief DMA transfer buffer address need to align with the transfer width */ -#define DMA_ALLOCATE_DATA_TRANSFER_BUFFER(name, width) SDK_ALIGN(name, width) -/* Channel group consists of 32 channels. channel_group = 0 */ -#define DMA_CHANNEL_GROUP(channel) (((uint8_t)(channel)) >> 5U) -/* Channel index in channel group. channel_index = (channel % (channel number per instance)) */ -#define DMA_CHANNEL_INDEX(base, channel) (((uint8_t)(channel)) & 0x1FU) -/*! @brief DMA linked descriptor address algin size */ -#define DMA_COMMON_REG_GET(base, channel, reg) \ - (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) -#define DMA_COMMON_CONST_REG_GET(base, channel, reg) \ - (((volatile const uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) -#define DMA_COMMON_REG_SET(base, channel, reg, value) \ - (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)] = (value)) - -/*! @brief DMA descriptor end address calculate - * @param start start address - * @param inc address interleave size - * @param bytes transfer bytes - * @param width transfer width - */ -#define DMA_DESCRIPTOR_END_ADDRESS(start, inc, bytes, width) \ - ((uint32_t *)((uint32_t)(start) + (inc) * (bytes) - (inc) * (width))) - -/*! @brief DMA channel transfer configurations macro - * @param reload true is reload link descriptor after current exhaust, false is not - * @param clrTrig true is clear trigger status, wait software trigger, false is not - * @param intA enable interruptA - * @param intB enable interruptB - * @param width transfer width - * @param srcInc source address interleave size - * @param dstInc destination address interleave size - * @param bytes transfer bytes - */ -#define DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes) \ - DMA_CHANNEL_XFERCFG_CFGVALID_MASK | DMA_CHANNEL_XFERCFG_RELOAD(reload) | DMA_CHANNEL_XFERCFG_CLRTRIG(clrTrig) | \ - DMA_CHANNEL_XFERCFG_SETINTA(intA) | DMA_CHANNEL_XFERCFG_SETINTB(intB) | \ - DMA_CHANNEL_XFERCFG_WIDTH(width == 4UL ? 2UL : (width - 1UL)) | \ - DMA_CHANNEL_XFERCFG_SRCINC(srcInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (srcInc - 1UL) : srcInc) | \ - DMA_CHANNEL_XFERCFG_DSTINC(dstInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (dstInc - 1UL) : dstInc) | \ - DMA_CHANNEL_XFERCFG_XFERCOUNT(bytes / width - 1UL) - -/*! @brief _dma_transfer_status DMA transfer status */ -enum -{ - kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the - transfer request. */ -}; - -/*! @brief _dma_addr_interleave_size dma address interleave size */ -enum -{ - kDMA_AddressInterleave0xWidth = 0U, /*!< dma source/destination address no interleave */ - kDMA_AddressInterleave1xWidth = 1U, /*!< dma source/destination address interleave 1xwidth */ - kDMA_AddressInterleave2xWidth = 2U, /*!< dma source/destination address interleave 2xwidth */ - kDMA_AddressInterleave4xWidth = 4U, /*!< dma source/destination address interleave 3xwidth */ -}; - -/*! @brief _dma_transfer_width dma transfer width */ -enum -{ - kDMA_Transfer8BitWidth = 1U, /*!< dma channel transfer bit width is 8 bit */ - kDMA_Transfer16BitWidth = 2U, /*!< dma channel transfer bit width is 16 bit */ - kDMA_Transfer32BitWidth = 4U, /*!< dma channel transfer bit width is 32 bit */ -}; - -/*! @brief DMA descriptor structure */ -typedef struct _dma_descriptor -{ - volatile uint32_t xfercfg; /*!< Transfer configuration */ - void *srcEndAddr; /*!< Last source address of DMA transfer */ - void *dstEndAddr; /*!< Last destination address of DMA transfer */ - void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */ -} dma_descriptor_t; - -/*! @brief DMA transfer configuration */ -typedef struct _dma_xfercfg -{ - bool valid; /*!< Descriptor is ready to transfer */ - bool reload; /*!< Reload channel configuration register after - current descriptor is exhausted */ - bool swtrig; /*!< Perform software trigger. Transfer if fired - when 'valid' is set */ - bool clrtrig; /*!< Clear trigger */ - bool intA; /*!< Raises IRQ when transfer is done and set IRQA status register flag */ - bool intB; /*!< Raises IRQ when transfer is done and set IRQB status register flag */ - uint8_t byteWidth; /*!< Byte width of data to transfer */ - uint8_t srcInc; /*!< Increment source address by 'srcInc' x 'byteWidth' */ - uint8_t dstInc; /*!< Increment destination address by 'dstInc' x 'byteWidth' */ - uint16_t transferCount; /*!< Number of transfers */ -} dma_xfercfg_t; - -/*! @brief DMA channel priority */ -typedef enum _dma_priority -{ - kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */ - kDMA_ChannelPriority1, /*!< Channel priority 1 */ - kDMA_ChannelPriority2, /*!< Channel priority 2 */ - kDMA_ChannelPriority3, /*!< Channel priority 3 */ - kDMA_ChannelPriority4, /*!< Channel priority 4 */ - kDMA_ChannelPriority5, /*!< Channel priority 5 */ - kDMA_ChannelPriority6, /*!< Channel priority 6 */ - kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */ -} dma_priority_t; - -/*! @brief DMA interrupt flags */ -typedef enum _dma_int -{ - kDMA_IntA, /*!< DMA interrupt flag A */ - kDMA_IntB, /*!< DMA interrupt flag B */ - kDMA_IntError, /*!< DMA interrupt flag error */ -} dma_irq_t; - -/*! @brief DMA trigger type*/ -typedef enum _dma_trigger_type -{ - kDMA_NoTrigger = 0, /*!< Trigger is disabled */ - kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */ - kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | - DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */ - kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */ - kDMA_RisingEdgeTrigger = - DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */ -} dma_trigger_type_t; - -/*! @brief _dma_burst_size DMA burst size*/ -enum -{ - kDMA_BurstSize1 = 0U, /*!< burst size 1 transfer */ - kDMA_BurstSize2 = 1U, /*!< burst size 2 transfer */ - kDMA_BurstSize4 = 2U, /*!< burst size 4 transfer */ - kDMA_BurstSize8 = 3U, /*!< burst size 8 transfer */ - kDMA_BurstSize16 = 4U, /*!< burst size 16 transfer */ - kDMA_BurstSize32 = 5U, /*!< burst size 32 transfer */ - kDMA_BurstSize64 = 6U, /*!< burst size 64 transfer */ - kDMA_BurstSize128 = 7U, /*!< burst size 128 transfer */ - kDMA_BurstSize256 = 8U, /*!< burst size 256 transfer */ - kDMA_BurstSize512 = 9U, /*!< burst size 512 transfer */ - kDMA_BurstSize1024 = 10U, /*!< burst size 1024 transfer */ -}; - -/*! @brief DMA trigger burst */ -typedef enum _dma_trigger_burst -{ - kDMA_SingleTransfer = 0, /*!< Single transfer */ - kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */ - kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */ - kDMA_EdgeBurstTransfer2 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */ - kDMA_EdgeBurstTransfer4 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */ - kDMA_EdgeBurstTransfer8 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */ - kDMA_EdgeBurstTransfer16 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */ - kDMA_EdgeBurstTransfer32 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */ - kDMA_EdgeBurstTransfer64 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */ - kDMA_EdgeBurstTransfer128 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */ - kDMA_EdgeBurstTransfer256 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */ - kDMA_EdgeBurstTransfer512 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */ - kDMA_EdgeBurstTransfer1024 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */ -} dma_trigger_burst_t; - -/*! @brief DMA burst wrapping */ -typedef enum _dma_burst_wrap -{ - kDMA_NoWrap = 0, /*!< Wrapping is disabled */ - kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */ - kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */ - kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | - DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */ -} dma_burst_wrap_t; - -/*! @brief DMA transfer type */ -typedef enum _dma_transfer_type -{ - kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */ - kDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory (increment only destination) */ - kDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral (increment only source)*/ - kDMA_StaticToStatic, /*!< Peripheral to static memory (do not increment source or destination) */ -} dma_transfer_type_t; - -/*! @brief DMA channel trigger */ -typedef struct _dma_channel_trigger -{ - dma_trigger_type_t type; /*!< Select hardware trigger as edge triggered or level triggered. */ - dma_trigger_burst_t burst; /*!< Select whether hardware triggers cause a single or burst transfer. */ - dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */ -} dma_channel_trigger_t; - -/*! @brief DMA channel trigger */ -typedef struct _dma_channel_config -{ - void *srcStartAddr; /*!< Source data address */ - void *dstStartAddr; /*!< Destination data address */ - void *nextDesc; /*!< Chain custom descriptor */ - uint32_t xferCfg; /*!< channel transfer configurations */ - dma_channel_trigger_t *trigger; /*!< DMA trigger type */ - bool isPeriph; /*!< select the request type */ -} dma_channel_config_t; - -/*! @brief DMA transfer configuration */ -typedef struct _dma_transfer_config -{ - uint8_t *srcAddr; /*!< Source data address */ - uint8_t *dstAddr; /*!< Destination data address */ - uint8_t *nextDesc; /*!< Chain custom descriptor */ - dma_xfercfg_t xfercfg; /*!< Transfer options */ - bool isPeriph; /*!< DMA transfer is driven by peripheral */ -} dma_transfer_config_t; - -/*! @brief Callback for DMA */ -struct _dma_handle; - -/*! @brief Define Callback function for DMA. */ -typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode); - -/*! @brief DMA transfer handle structure */ -typedef struct _dma_handle -{ - dma_callback callback; /*!< Callback function. Invoked when transfer - of descriptor with interrupt flag finishes */ - void *userData; /*!< Callback function parameter */ - DMA_Type *base; /*!< DMA peripheral base address */ - uint8_t channel; /*!< DMA channel number */ -} dma_handle_t; - -/******************************************************************************* - * APIs - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name DMA initialization and De-initialization - * @{ - */ - -/*! - * @brief Initializes DMA peripheral. - * - * This function enable the DMA clock, set descriptor table and - * enable DMA peripheral. - * - * @param base DMA peripheral base address. - */ -void DMA_Init(DMA_Type *base); - -/*! - * @brief Deinitializes DMA peripheral. - * - * This function gates the DMA clock. - * - * @param base DMA peripheral base address. - */ -void DMA_Deinit(DMA_Type *base); - -/*! - * @brief Install DMA descriptor memory. - * - * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong - * transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has - * a default DMA descriptor buffer, but it support one DMA descriptor for one channel only. - * - * @param base DMA base address. - * @param addr DMA descriptor address - */ -void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr); - -/* @} */ - -/*! - * @name DMA Channel Operation - * @{ - */ - -/*! - * @brief Return whether DMA channel is processing transfer - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return True for active state, false otherwise. - */ -static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - - return (DMA_COMMON_CONST_REG_GET(base, channel, ACTIVE) & (1UL << DMA_CHANNEL_INDEX(base, channel))) != 0UL; -} - -/*! - * @brief Return whether DMA channel is busy - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return True for busy state, false otherwise. - */ -static inline bool DMA_ChannelIsBusy(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - - return (DMA_COMMON_CONST_REG_GET(base, channel, BUSY) & (1UL << DMA_CHANNEL_INDEX(base, channel))) != 0UL; -} - -/*! - * @brief Enables the interrupt source for the DMA transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - DMA_COMMON_REG_GET(base, channel, INTENSET) |= 1UL << DMA_CHANNEL_INDEX(base, channel); -} - -/*! - * @brief Disables the interrupt source for the DMA transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - DMA_COMMON_REG_GET(base, channel, INTENCLR) |= 1UL << DMA_CHANNEL_INDEX(base, channel); -} - -/*! - * @brief Enable DMA channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - DMA_COMMON_REG_GET(base, channel, ENABLESET) |= 1UL << DMA_CHANNEL_INDEX(base, channel); -} - -/*! - * @brief Disable DMA channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - DMA_COMMON_REG_GET(base, channel, ENABLECLR) |= 1UL << DMA_CHANNEL_INDEX(base, channel); -} - -/*! - * @brief Set PERIPHREQEN of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK; -} - -/*! - * @brief Get PERIPHREQEN value of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return True for enabled PeriphRq, false for disabled. - */ -static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK; -} - -/*! - * @brief Set trigger settings of DMA channel. - * @deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param trigger trigger configuration. - */ -void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger); - -/*! - * @brief set channel config. - * - * This function provide a interface to configure channel configuration reisters. - * - * @param base DMA base address. - * @param channel DMA channel number. - * @param trigger channel configurations structure. - * @param isPeriph true is periph request, false is not. - */ -void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph); - -/*! - * @brief Gets the remaining bytes of the current DMA descriptor transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return The number of bytes which have not been transferred yet. - */ -uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel); - -/*! - * @brief Set priority of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param priority Channel priority value. - */ -static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - base->CHANNEL[channel].CFG = - (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority); -} - -/*! - * @brief Get priority of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return Channel priority value. - */ -static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - return (dma_priority_t)(uint8_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> - DMA_CHANNEL_CFG_CHPRIORITY_SHIFT); -} - -/*! - * @brief Set channel configuration valid. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_SetChannelConfigValid(DMA_Type *base, uint32_t channel) -{ - base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_CFGVALID_MASK; -} - -/*! - * @brief Do software trigger for the channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DoChannelSoftwareTrigger(DMA_Type *base, uint32_t channel) -{ - base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; -} - -/*! - * @brief Load channel transfer configurations. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param xfer transfer configurations. - */ -static inline void DMA_LoadChannelTransferConfig(DMA_Type *base, uint32_t channel, uint32_t xfer) -{ - base->CHANNEL[channel].XFERCFG = xfer; -} - -/*! - * @brief Create application specific DMA descriptor - * to be used in a chain in transfer - * @deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor. - * @param desc DMA descriptor address. - * @param xfercfg Transfer configuration for DMA descriptor. - * @param srcAddr Address of last item to transmit - * @param dstAddr Address of last item to receive. - * @param nextDesc Address of next descriptor in chain. - */ -void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc); - -/*! - * @brief setup dma descriptor - * - * Note: This function do not support configure wrap descriptor. - * - * @param desc DMA descriptor address. - * @param xfercfg Transfer configuration for DMA descriptor. - * @param srcStartAddr Start address of source address. - * @param dstStartAddr Start address of destination address. - * @param nextDesc Address of next descriptor in chain. - */ -void DMA_SetupDescriptor( - dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc); - -/*! - * @brief setup dma channel descriptor - * - * Note: This function support configure wrap descriptor. - * - * @param desc DMA descriptor address. - * @param xfercfg Transfer configuration for DMA descriptor. - * @param srcStartAddr Start address of source address. - * @param dstStartAddr Start address of destination address. - * @param nextDesc Address of next descriptor in chain. - * @param wrapType burst wrap type. - * @param burstSize burst size, reference _dma_burst_size. - */ -void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, - uint32_t xfercfg, - void *srcStartAddr, - void *dstStartAddr, - void *nextDesc, - dma_burst_wrap_t wrapType, - uint32_t burstSize); - -/*! - * @brief load channel transfer decriptor. - * - * This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA - * transfer, the head descriptor table is defined in DMA driver, it is useful for the case: - * 1. for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly - * and then call this api to load the configured descriptor to driver descriptor table. - * @code - * DMA_Init(DMA0); - * DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL); - * DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL); - * DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc); - * DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL); - * while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL)) - * {} - * @endcode - * - * @param base DMA base address. - * @param channel DMA channel. - * @param descriptor configured DMA descriptor. - */ -void DMA_LoadChannelDescriptor(DMA_Type *base, uint32_t channel, dma_descriptor_t *descriptor); - -/* @} */ - -/*! - * @name DMA Transactional Operation - * @{ - */ - -/*! - * @brief Abort running transfer by handle. - * - * This function aborts DMA transfer specified by handle. - * - * @param handle DMA handle pointer. - */ -void DMA_AbortTransfer(dma_handle_t *handle); - -/*! - * @brief Creates the DMA handle. - * - * This function is called if using transaction API for DMA. This function - * initializes the internal state of DMA handle. - * - * @param handle DMA handle pointer. The DMA handle stores callback function and - * parameters. - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel); - -/*! - * @brief Installs a callback function for the DMA transfer. - * - * This callback is called in DMA IRQ handler. Use the callback to do something after - * the current major loop transfer completes. - * - * @param handle DMA handle pointer. - * @param callback DMA callback function pointer. - * @param userData Parameter for callback function. - */ -void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData); - -/*! - * @brief Prepares the DMA transfer structure. - * @deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer. - * This function prepares the transfer configuration structure according to the user input. - * - * @param config The user configuration structure of type dma_transfer_t. - * @param srcAddr DMA transfer source address. - * @param dstAddr DMA transfer destination address. - * @param byteWidth DMA transfer destination address width(bytes). - * @param transferBytes DMA transfer bytes to be transferred. - * @param type DMA transfer type. - * @param nextDesc Chain custom descriptor to transfer. - * @note The data address and the data width must be consistent. For example, if the SRC - * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in - * source address error(SAE). - */ -void DMA_PrepareTransfer(dma_transfer_config_t *config, - void *srcAddr, - void *dstAddr, - uint32_t byteWidth, - uint32_t transferBytes, - dma_transfer_type_t type, - void *nextDesc); - -/*! - * @brief Prepare channel transfer configurations. - * - * This function used to prepare channel transfer configurations. - * - * @param config Pointer to DMA channel transfer configuration structure. - * @param srcStartAddr source start address. - * @param dstStartAddr destination start address. - * @param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * @param type transfer type. - * @param trigger DMA channel trigger configurations. - * @param nextDesc address of next descriptor. - */ -void DMA_PrepareChannelTransfer(dma_channel_config_t *config, - void *srcStartAddr, - void *dstStartAddr, - uint32_t xferCfg, - dma_transfer_type_t type, - dma_channel_trigger_t *trigger, - void *nextDesc); - -/*! - * @brief Submits the DMA transfer request. - * @deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * - * @param handle DMA handle pointer. - * @param config Pointer to DMA transfer configuration structure. - * @retval kStatus_DMA_Success It means submit transfer request succeed. - * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config); - -/*! - * @brief Submit channel transfer paramter directly. - * - * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table - * is defined in DMA driver, it is useful for the case: - * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used - for it. - * @code - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, - bytes), srcStartAddr, dstStartAddr, NULL); - DMA_StartTransfer(handle) - * @endcode - * - * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is - required, then application should prepare - * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * @code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc2); - DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, NULL); - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, - bytes), srcStartAddr, dstStartAddr, nextDesc0); - DMA_StartTransfer(handle); - * @endcode - * - * @param handle Pointer to DMA handle. - * @param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * @param srcStartAddr source start address. - * @param dstStartAddr destination start address. - * @param nextDesc address of next descriptor. - */ -void DMA_SubmitChannelTransferParameter( - dma_handle_t *handle, uint32_t xferCfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc); - -/*! - * @brief Submit channel descriptor. - * - * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table - is defined in - * DMA driver, this functiono is typical for the ping pong case: - * - * 1. for the ping pong case, application should responsible for the descriptor, for example, application should - * prepare two descriptor table with macro. - * @code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc0); - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelDescriptor(handle, nextDesc0); - DMA_StartTransfer(handle); - * @endcode - * - * @param handle Pointer to DMA handle. - * @param descriptor descriptor to submit. - */ -void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descriptor); - -/*! - * @brief Submits the DMA channel transfer request. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * It is used for the case: - * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used - for it. - * @code - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,NULL); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * @endcode - * - * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is - required, then application should prepare - * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * @code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc2); - DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, NULL); - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * @endcode - * - * 3. for the ping pong case, application should responsible for link descriptor, for example, application should - prepare - * two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * @code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc0); - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * @endcode - * @param handle DMA handle pointer. - * @param config Pointer to DMA transfer configuration structure. - * @retval kStatus_DMA_Success It means submit transfer request succeed. - * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config); - -/*! - * @brief DMA start transfer. - * - * This function enables the channel request. User can call this function after submitting the transfer request - * It will trigger transfer start with software trigger only when hardware trigger is not used. - * - * @param handle DMA handle pointer. - */ -void DMA_StartTransfer(dma_handle_t *handle); - -/*! - * @brief DMA IRQ handler for descriptor transfer complete. - * - * This function clears the channel major interrupt flag and call - * the callback function if it is not NULL. - * - * @param base DMA base address. - */ -void DMA_IRQHandle(DMA_Type *base); - -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/* @} */ - -#endif /*_FSL_DMA_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_flexcomm.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_flexcomm.c deleted file mode 100644 index 7a21a1ce0ea..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_flexcomm.c +++ /dev/null @@ -1,412 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm" -#endif - -/*! - * @brief Used for conversion between `void*` and `uint32_t`. - */ -typedef union pvoid_to_u32 -{ - void *pvoid; - uint32_t u32; -} pvoid_to_u32_t; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! @brief Set the FLEXCOMM mode . */ -static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock); - -/*! @brief check whether flexcomm supports peripheral type */ -static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map FLEXCOMM instance number to base address. */ -static const uint32_t s_flexcommBaseAddrs[] = FLEXCOMM_BASE_ADDRS; - -/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ -static flexcomm_irq_handler_t s_flexcommIrqHandler[ARRAY_SIZE(s_flexcommBaseAddrs)]; - -/*! @brief Pointers to handles for each instance to provide context to interrupt routines */ -static void *s_flexcommHandle[ARRAY_SIZE(s_flexcommBaseAddrs)]; - -/*! @brief Array to map FLEXCOMM instance number to IRQ number. */ -IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief IDs of clock for each FLEXCOMM module */ -static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) -/*! @brief Pointers to FLEXCOMM resets for each instance. */ -static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* check whether flexcomm supports peripheral type */ -static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph) -{ - if (periph == FLEXCOMM_PERIPH_NONE) - { - return true; - } - else if (periph <= FLEXCOMM_PERIPH_I2S_TX) - { - return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false; - } - else if (periph == FLEXCOMM_PERIPH_I2S_RX) - { - return (base->PSELID & (1U << 7U)) > (uint32_t)0U ? true : false; - } - else - { - return false; - } -} - -/* Get the index corresponding to the FLEXCOMM */ -/*! brief Returns instance number for FLEXCOMM module with given base address. */ -uint32_t FLEXCOMM_GetInstance(void *base) -{ - uint32_t i; - pvoid_to_u32_t BaseAddr; - BaseAddr.pvoid = base; - - for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++) - { - if (BaseAddr.u32 == s_flexcommBaseAddrs[i]) - { - break; - } - } - - assert(i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT); - return i; -} - -/* Changes FLEXCOMM mode */ -static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock) -{ - /* Check whether peripheral type is present */ - if (!FLEXCOMM_PeripheralIsPresent(base, periph)) - { - return kStatus_OutOfRange; - } - - /* Flexcomm is locked to different peripheral type than expected */ - if (((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) != 0U) && - ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph)) - { - return kStatus_Fail; - } - - /* Check if we are asked to lock */ - if (lock != 0) - { - base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK; - } - else - { - base->PSELID = (uint32_t)periph; - } - - return kStatus_Success; -} - -/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ -status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) -{ - uint32_t idx = FLEXCOMM_GetInstance(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the peripheral clock */ - CLOCK_EnableClock(s_flexcommClocks[idx]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) - /* Reset the FLEXCOMM module */ - RESET_PeripheralReset(s_flexcommResets[idx]); -#endif - - /* Set the FLEXCOMM to given peripheral */ - return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0); -} - -/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM - * mode */ -void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(base); - - /* Clear handler first to avoid execution of the handler with wrong handle */ - s_flexcommIrqHandler[instance] = NULL; - s_flexcommHandle[instance] = flexcommHandle; - s_flexcommIrqHandler[instance] = handler; - SDK_ISR_EXIT_BARRIER; -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(FLEXCOMM0) -void FLEXCOMM0_DriverIRQHandler(void); -void FLEXCOMM0_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM0); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM1) -void FLEXCOMM1_DriverIRQHandler(void); -void FLEXCOMM1_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM1); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM2) -void FLEXCOMM2_DriverIRQHandler(void); -void FLEXCOMM2_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM2); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM3) -void FLEXCOMM3_DriverIRQHandler(void); -void FLEXCOMM3_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM3); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM4) -void FLEXCOMM4_DriverIRQHandler(void); -void FLEXCOMM4_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM4); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} - -#endif - -#if defined(FLEXCOMM5) -void FLEXCOMM5_DriverIRQHandler(void); -void FLEXCOMM5_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM5); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM6) -void FLEXCOMM6_DriverIRQHandler(void); -void FLEXCOMM6_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM6); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM7) -void FLEXCOMM7_DriverIRQHandler(void); -void FLEXCOMM7_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM7); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM8) -void FLEXCOMM8_DriverIRQHandler(void); -void FLEXCOMM8_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM8); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM9) -void FLEXCOMM9_DriverIRQHandler(void); -void FLEXCOMM9_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM9); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM10) -void FLEXCOMM10_DriverIRQHandler(void); -void FLEXCOMM10_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM10); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM11) -void FLEXCOMM11_DriverIRQHandler(void); -void FLEXCOMM11_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM11); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM12) -void FLEXCOMM12_DriverIRQHandler(void); -void FLEXCOMM12_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM12); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM13) -void FLEXCOMM13_DriverIRQHandler(void); -void FLEXCOMM13_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM13); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM14) -void FLEXCOMM14_DriverIRQHandler(void); -void FLEXCOMM14_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM14); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM15) -void FLEXCOMM15_DriverIRQHandler(void); -void FLEXCOMM15_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM15); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM16) -void FLEXCOMM16_DriverIRQHandler(void); -void FLEXCOMM16_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM16); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_flexcomm.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_flexcomm.h deleted file mode 100644 index f96086fdecc..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_flexcomm.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_FLEXCOMM_H_ -#define _FSL_FLEXCOMM_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup flexcomm_driver - * @{ - */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FlexCOMM driver version 2.0.2. */ -#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -/*! @brief FLEXCOMM peripheral modes. */ -typedef enum -{ - FLEXCOMM_PERIPH_NONE, /*!< No peripheral */ - FLEXCOMM_PERIPH_USART, /*!< USART peripheral */ - FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */ - FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */ - FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */ - FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */ -} FLEXCOMM_PERIPH_T; - -/*! @brief Typedef for interrupt handler. */ -typedef void (*flexcomm_irq_handler_t)(void *base, void *handle); - -/*! @brief Array with IRQ number for each FLEXCOMM module. */ -extern IRQn_Type const kFlexcommIrqs[]; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @brief Returns instance number for FLEXCOMM module with given base address. */ -uint32_t FLEXCOMM_GetInstance(void *base); - -/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ -status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph); - -/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM - * mode */ -void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle); - -#if defined(__cplusplus) -} -#endif - -/*@}*/ - -#endif /* _FSL_FLEXCOMM_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_gint.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_gint.c deleted file mode 100644 index 9dc2e5eff0d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_gint.c +++ /dev/null @@ -1,372 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_gint.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.gint" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to GINT bases for each instance. */ -static GINT_Type *const s_gintBases[FSL_FEATURE_SOC_GINT_COUNT] = GINT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Clocks for each instance. */ -static const clock_ip_name_t s_gintClocks[FSL_FEATURE_SOC_GINT_COUNT] = GINT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -/*! @brief Resets for each instance. */ -static const reset_ip_name_t s_gintResets[FSL_FEATURE_SOC_GINT_COUNT] = GINT_RSTS; -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/* @brief Irq number for each instance */ -static const IRQn_Type s_gintIRQ[FSL_FEATURE_SOC_GINT_COUNT] = GINT_IRQS; - -/*! @brief Callback function array for GINT(s). */ -static gint_cb_t s_gintCallback[FSL_FEATURE_SOC_GINT_COUNT]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t GINT_GetInstance(GINT_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_gintBases); instance++) - { - if (s_gintBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_gintBases)); - - return instance; -} - -/*! - * brief Initialize GINT peripheral. - - * This function initializes the GINT peripheral and enables the clock. - * - * param base Base address of the GINT peripheral. - * - * retval None. - */ -void GINT_Init(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - s_gintCallback[instance] = NULL; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the peripheral clock */ - CLOCK_EnableClock(s_gintClocks[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_gintResets[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -} - -/*! - * brief Setup GINT peripheral control parameters. - - * This function sets the control parameters of GINT peripheral. - * - * param base Base address of the GINT peripheral. - * param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. - * param trig Controls if the enabled inputs are level or edge sensitive based on polarity. - * param callback This function is called when configured group interrupt is generated. - * - * retval None. - */ -void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - base->CTRL = (GINT_CTRL_COMB(comb) | GINT_CTRL_TRIG(trig)); - - /* Save callback pointer */ - s_gintCallback[instance] = callback; -} - -/*! - * brief Get GINT peripheral control parameters. - - * This function returns the control parameters of GINT peripheral. - * - * param base Base address of the GINT peripheral. - * param comb Pointer to store combine input value. - * param trig Pointer to store trigger value. - * param callback Pointer to store callback function. - * - * retval None. - */ -void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback) -{ - uint32_t instance; - uint32_t combValue; - uint32_t trigValue; - - instance = GINT_GetInstance(base); - - combValue = (base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT; - *comb = (gint_comb_t)combValue; - trigValue = (base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT; - *trig = (gint_trig_t)trigValue; - *callback = s_gintCallback[instance]; -} - -/*! - * brief Configure GINT peripheral pins. - - * This function enables and controls the polarity of enabled pin(s) of a given port. - * - * param base Base address of the GINT peripheral. - * param port Port number. - * param polarityMask Each bit position selects the polarity of the corresponding enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * param enableMask Each bit position selects if the corresponding pin is enabled or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * retval None. - */ -void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask) -{ - base->PORT_POL[port] = polarityMask; - base->PORT_ENA[port] = enableMask; -} - -/*! - * brief Get GINT peripheral pin configuration. - - * This function returns the pin configuration of a given port. - * - * param base Base address of the GINT peripheral. - * param port Port number. - * param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding - enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled - or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * retval None. - */ -void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask) -{ - *polarityMask = base->PORT_POL[port]; - *enableMask = base->PORT_ENA[port]; -} - -/*! - * brief Enable callback. - - * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * param base Base address of the GINT peripheral. - * - * retval None. - */ -void GINT_EnableCallback(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - /* If GINT is configured in "AND" mode a spurious interrupt is generated. - Clear status and pending interrupt before enabling the irq in NVIC. */ - GINT_ClrStatus(base); - NVIC_ClearPendingIRQ(s_gintIRQ[instance]); - (void)EnableIRQ(s_gintIRQ[instance]); -} - -/*! - * brief Disable callback. - - * This function disables the interrupt for the selected GINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * param base Base address of the peripheral. - * - * retval None. - */ -void GINT_DisableCallback(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - (void)DisableIRQ(s_gintIRQ[instance]); - GINT_ClrStatus(base); - NVIC_ClearPendingIRQ(s_gintIRQ[instance]); -} - -/*! - * brief Deinitialize GINT peripheral. - - * This function disables the GINT clock. - * - * param base Base address of the GINT peripheral. - * - * retval None. - */ -void GINT_Deinit(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - /* Cleanup */ - GINT_DisableCallback(base); - s_gintCallback[instance] = NULL; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_gintResets[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the peripheral clock */ - CLOCK_DisableClock(s_gintClocks[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(GINT0) -void GINT0_DriverIRQHandler(void); -void GINT0_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[0]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[0] != NULL) - { - s_gintCallback[0](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT1) -void GINT1_DriverIRQHandler(void); -void GINT1_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[1]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[1] != NULL) - { - s_gintCallback[1](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT2) -void GINT2_DriverIRQHandler(void); -void GINT2_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[2]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[2] != NULL) - { - s_gintCallback[2](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT3) -void GINT3_DriverIRQHandler(void); -void GINT3_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[3]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[3] != NULL) - { - s_gintCallback[3](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT4) -void GINT4_DriverIRQHandler(void); -void GINT4_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[4]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[4] != NULL) - { - s_gintCallback[4](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT5) -void GINT5_DriverIRQHandler(void); -void GINT5_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[5]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[5] != NULL) - { - s_gintCallback[5](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT6) -void GINT6_DriverIRQHandler(void); -void GINT6_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[6]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[6] != NULL) - { - s_gintCallback[6](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT7) -void GINT7_DriverIRQHandler(void); -void GINT7_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[7]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[7] != NULL) - { - s_gintCallback[7](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_gint.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_gint.h deleted file mode 100644 index adc301a9e0d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_gint.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_GINT_H_ -#define _FSL_GINT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup gint_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3. */ -/*@}*/ - -/*! @brief GINT combine inputs type */ -typedef enum _gint_comb -{ - kGINT_CombineOr = 0U, /*!< A grouped interrupt is generated when any one of the enabled inputs is active */ - kGINT_CombineAnd = 1U /*!< A grouped interrupt is generated when all enabled inputs are active */ -} gint_comb_t; - -/*! @brief GINT trigger type */ -typedef enum _gint_trig -{ - kGINT_TrigEdge = 0U, /*!< Edge triggered based on polarity */ - kGINT_TrigLevel = 1U /*!< Level triggered based on polarity */ -} gint_trig_t; - -/* @brief GINT port type */ -typedef enum _gint_port -{ - kGINT_Port0 = 0U, - kGINT_Port1 = 1U, -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 2U) - kGINT_Port2 = 2U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 3U) - kGINT_Port3 = 3U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 4U) - kGINT_Port4 = 4U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 5U) - kGINT_Port5 = 5U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 6U) - kGINT_Port6 = 6U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 7U) - kGINT_Port7 = 7U, -#endif -} gint_port_t; - -/*! @brief GINT Callback function. */ -typedef void (*gint_cb_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize GINT peripheral. - - * This function initializes the GINT peripheral and enables the clock. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_Init(GINT_Type *base); - -/*! - * @brief Setup GINT peripheral control parameters. - - * This function sets the control parameters of GINT peripheral. - * - * @param base Base address of the GINT peripheral. - * @param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. - * @param trig Controls if the enabled inputs are level or edge sensitive based on polarity. - * @param callback This function is called when configured group interrupt is generated. - * - * @retval None. - */ -void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback); - -/*! - * @brief Get GINT peripheral control parameters. - - * This function returns the control parameters of GINT peripheral. - * - * @param base Base address of the GINT peripheral. - * @param comb Pointer to store combine input value. - * @param trig Pointer to store trigger value. - * @param callback Pointer to store callback function. - * - * @retval None. - */ -void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback); - -/*! - * @brief Configure GINT peripheral pins. - - * This function enables and controls the polarity of enabled pin(s) of a given port. - * - * @param base Base address of the GINT peripheral. - * @param port Port number. - * @param polarityMask Each bit position selects the polarity of the corresponding enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * @param enableMask Each bit position selects if the corresponding pin is enabled or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * @retval None. - */ -void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask); - -/*! - * @brief Get GINT peripheral pin configuration. - - * This function returns the pin configuration of a given port. - * - * @param base Base address of the GINT peripheral. - * @param port Port number. - * @param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding - enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * @param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled - or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * @retval None. - */ -void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask); - -/*! - * @brief Enable callback. - - * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_EnableCallback(GINT_Type *base); - -/*! - * @brief Disable callback. - - * This function disables the interrupt for the selected GINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * @param base Base address of the peripheral. - * - * @retval None. - */ -void GINT_DisableCallback(GINT_Type *base); - -/*! - * @brief Clear GINT status. - - * This function clears the GINT status bit. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -static inline void GINT_ClrStatus(GINT_Type *base) -{ - base->CTRL |= GINT_CTRL_INT_MASK; -} - -/*! - * @brief Get GINT status. - - * This function returns the GINT status. - * - * @param base Base address of the GINT peripheral. - * - * @retval status = 0 No group interrupt request. = 1 Group interrupt request active. - */ -static inline uint32_t GINT_GetStatus(GINT_Type *base) -{ - return (base->CTRL & GINT_CTRL_INT_MASK); -} - -/*! - * @brief Deinitialize GINT peripheral. - - * This function disables the GINT clock. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_Deinit(GINT_Type *base); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_GINT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_gpio.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_gpio.c deleted file mode 100644 index be100d5e9e3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_gpio.c +++ /dev/null @@ -1,317 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_gpio.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map FGPIO instance number to clock name. */ -static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) -/*! @brief Pointers to GPIO resets for each instance. */ -static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N; -#endif -/******************************************************************************* - * Prototypes - ************ ******************************************************************/ -/*! - * @brief Enable GPIO port clock. - * - * @param base GPIO peripheral base pointer. - * @param port GPIO port number. - */ -static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port); - -/******************************************************************************* - * Code - ******************************************************************************/ -static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - assert(port < ARRAY_SIZE(s_gpioClockName)); - - /* Upgate the GPIO clock */ - CLOCK_EnableClock(s_gpioClockName[port]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Initializes the GPIO peripheral. - * - * This function ungates the GPIO clock. - * - * param base GPIO peripheral base pointer. - * param port GPIO port number. - */ -void GPIO_PortInit(GPIO_Type *base, uint32_t port) -{ - GPIO_EnablePortClock(base, port); - -#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) - /* Reset the GPIO module */ - RESET_PeripheralReset(s_gpioResets[port]); -#endif -} - -/*! - * brief Initializes a GPIO pin used by the board. - * - * To initialize the GPIO, define a pin configuration, either input or output, in the user file. - * Then, call the GPIO_PinInit() function. - * - * This is an example to define an input pin or output pin configuration: - * code - * Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * endcode - * - * param base GPIO peripheral base pointer(Typically GPIO) - * param port GPIO port number - * param pin GPIO pin number - * param config GPIO pin configuration pointer - */ -void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) -{ - GPIO_EnablePortClock(base, port); - - if (config->pinDirection == kGPIO_DigitalInput) - { -#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) - base->DIRCLR[port] = 1UL << pin; -#else - base->DIR[port] &= ~(1UL << pin); -#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ - } - else - { - /* Set default output value */ - if (config->outputLogic == 0U) - { - base->CLR[port] = (1UL << pin); - } - else - { - base->SET[port] = (1UL << pin); - } -/* Set pin direction */ -#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) - base->DIRSET[port] = 1UL << pin; -#else - base->DIR[port] |= 1UL << pin; -#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ - } -} - -#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT -/*! - * @brief Set the configuration of pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param pin GPIO pin number. - * @param config GPIO pin interrupt configuration.. - */ -void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config) -{ - base->INTEDG[port] = (base->INTEDG[port] & ~(1UL << pin)) | ((uint32_t)config->mode << pin); - - base->INTPOL[port] = (base->INTPOL[port] & ~(1UL << pin)) | ((uint32_t)config->polarity << pin); -} - -/*! - * @brief Enables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] | mask; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] | mask; - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Disables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] & ~mask; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] & ~mask; - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Clears multiple pins interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTSTATA[port] = mask; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTSTATB[port] = mask; - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @ Read port interrupt status. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param index GPIO interrupt number. - * @retval masked GPIO status value - */ -uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index) -{ - uint32_t status = 0U; - - if ((uint32_t)kGPIO_InterruptA == index) - { - status = base->INTSTATA[port]; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - status = base->INTSTATB[port]; - } - else - { - /*Should not enter here*/ - } - return status; -} - -/*! - * @brief Enables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] | (1UL << pin); - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] | (1UL << pin); - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Disables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] & ~(1UL << pin); - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] & ~(1UL << pin); - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Clears the specific pin interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTSTATA[port] = 1UL << pin; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTSTATB[port] = 1UL << pin; - } - else - { - /*Should not enter here*/ - } -} -#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_gpio.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_gpio.h deleted file mode 100644 index 50a33f89208..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_gpio.h +++ /dev/null @@ -1,364 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _LPC_GPIO_H_ -#define _LPC_GPIO_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_gpio - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPC GPIO driver version. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 7)) -/*@}*/ - -/*! @brief LPC GPIO direction definition */ -typedef enum _gpio_pin_direction -{ - kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ - kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ -} gpio_pin_direction_t; - -/*! - * @brief The GPIO pin configuration structure. - * - * Every pin can only be configured as either output pin or input pin at a time. - * If configured as a input pin, then leave the outputConfig unused. - */ -typedef struct _gpio_pin_config -{ - gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ - /* Output configurations, please ignore if configured as a input one */ - uint8_t outputLogic; /*!< Set default output logic, no use in input */ -} gpio_pin_config_t; - -#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT) -#define GPIO_PIN_INT_LEVEL 0x00U -#define GPIO_PIN_INT_EDGE 0x01U - -#define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U -#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U - -/*! @brief GPIO Pin Interrupt enable mode */ -typedef enum _gpio_pin_enable_mode -{ - kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */ - kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE /*!< Generate Pin Interrupt on edge mode */ -} gpio_pin_enable_mode_t; - -/*! @brief GPIO Pin Interrupt enable polarity */ -typedef enum _gpio_pin_enable_polarity -{ - kGPIO_PinIntEnableHighOrRise = - PINT_PIN_INT_HIGH_OR_RISE_TRIGGER, /*!< Generate Pin Interrupt on high level or rising edge */ - kGPIO_PinIntEnableLowOrFall = - PINT_PIN_INT_LOW_OR_FALL_TRIGGER /*!< Generate Pin Interrupt on low level or falling edge */ -} gpio_pin_enable_polarity_t; - -/*! @brief LPC GPIO interrupt index definition */ -typedef enum _gpio_interrupt_index -{ - kGPIO_InterruptA = 0U, /*!< Set current pin as interrupt A*/ - kGPIO_InterruptB = 1U, /*!< Set current pin as interrupt B*/ -} gpio_interrupt_index_t; - -/*! @brief Configures the interrupt generation condition. */ -typedef struct _gpio_interrupt_config -{ - uint8_t mode; /* The trigger mode of GPIO interrupts */ - uint8_t polarity; /* The polarity of GPIO interrupts */ -} gpio_interrupt_config_t; -#endif - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @name GPIO Configuration */ -/*@{*/ - -/*! - * @brief Initializes the GPIO peripheral. - * - * This function ungates the GPIO clock. - * - * @param base GPIO peripheral base pointer. - * @param port GPIO port number. - */ -void GPIO_PortInit(GPIO_Type *base, uint32_t port); - -/*! - * @brief Initializes a GPIO pin used by the board. - * - * To initialize the GPIO, define a pin configuration, either input or output, in the user file. - * Then, call the GPIO_PinInit() function. - * - * This is an example to define an input pin or output pin configuration: - * @code - * Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * @endcode - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @param config GPIO pin configuration pointer - */ -void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config); - -/*@}*/ - -/*! @name GPIO Output Operations */ -/*@{*/ - -/*! - * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @param output GPIO pin output logic level. - * - 0: corresponding pin output low-logic level. - * - 1: corresponding pin output high-logic level. - */ -static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) -{ - base->B[port][pin] = output; -} - -/*@}*/ -/*! @name GPIO Input Operations */ -/*@{*/ - -/*! - * @brief Reads the current input value of the GPIO PIN. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @retval GPIO port input value - * - 0: corresponding pin input low-logic level. - * - 1: corresponding pin input high-logic level. - */ -static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) -{ - return (uint32_t)base->B[port][pin]; -} - -/*@}*/ - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 1. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->SET[port] = mask; -} - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 0. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->CLR[port] = mask; -} - -/*! - * @brief Reverses current output logic of the multiple GPIO pins. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->NOT[port] = mask; -} - -/*@}*/ - -/*! - * @brief Reads the current input value of the whole GPIO port. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - */ -static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port) -{ - return (uint32_t)base->PIN[port]; -} - -/*@}*/ -/*! @name GPIO Mask Operations */ -/*@{*/ - -/*! - * @brief Sets port mask, 0 - enable pin, 1 - disable pin. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->MASK[port] = mask; -} - -/*! - * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param output GPIO port output value. - */ -static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output) -{ - base->MPIN[port] = output; -} - -/*! - * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be - * affected. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @retval masked GPIO port value - */ -static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) -{ - return (uint32_t)base->MPIN[port]; -} - -#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT -/*! - * @brief Set the configuration of pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param pin GPIO pin number. - * @param config GPIO pin interrupt configuration.. - */ -void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config); - -/*! - * @brief Enables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); - -/*! - * @brief Disables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); - -/*! - * @brief Clears pin interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); - -/*! - * @ Read port interrupt status. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param index GPIO interrupt number. - * @retval masked GPIO status value - */ -uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index); - -/*! - * @brief Enables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); - -/*! - * @brief Disables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); - -/*! - * @brief Clears the specific pin interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); - -#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* _LPC_GPIO_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_hashcrypt.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_hashcrypt.c deleted file mode 100644 index 85943dcfdd3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_hashcrypt.c +++ /dev/null @@ -1,1726 +0,0 @@ -/* - * Copyright 2017-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_hashcrypt.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.hashcrypt" -#endif - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*!< SHA-1 and SHA-256 block size */ -#define SHA_BLOCK_SIZE 64U -/*!< max number of blocks that can be proccessed in one run (master mode) */ -#define SHA_MASTER_MAX_BLOCKS 2048U - -/*!< Use standard C library memcpy */ -#define hashcrypt_memcpy memcpy - -/*! Internal states of the HASH creation process */ -typedef enum _hashcrypt_sha_algo_state -{ - kHASHCRYPT_HashInit = 1u, /*!< Init state, the NEW bit in SHA Control register has not been written yet. */ - kHASHCRYPT_HashUpdate, /*!< Update state, DIGEST registers contain running hash, NEW bit in SHA control register has - been written. */ -} hashcrypt_sha_algo_state_t; - -/*! 64-byte block represented as byte array of 16 32-bit words */ -typedef union _sha_hash_block -{ - uint32_t w[SHA_BLOCK_SIZE / 4]; /*!< array of 32-bit words */ - uint8_t b[SHA_BLOCK_SIZE]; /*!< byte array */ -} hashcrypt_sha_block_t; - -/*! internal sha context structure */ -typedef struct _hashcrypt_sha_ctx_internal -{ - hashcrypt_sha_block_t blk; /*!< memory buffer. only full 64-byte blocks are written to SHA during hash updates */ - size_t blksz; /*!< number of valid bytes in memory buffer */ - hashcrypt_algo_t algo; /*!< selected algorithm from the set of supported algorithms */ - hashcrypt_sha_algo_state_t state; /*!< finite machine state of the hash software process */ - size_t fullMessageSize; /*!< track message size during SHA_Update(). The value is used for padding. */ - uint32_t remainingBlcks; /*!< number of remaining blocks to process in AHB master mode */ - hashcrypt_callback_t hashCallback; /*!< pointer to HASH callback function */ - void - *userData; /*!< user data to be passed as an argument to callback function, once callback is invoked from isr */ -#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) - uint32_t runningHash[8]; /*!< running hash. up to SHA-256, that is 32 bytes. */ -#endif -} hashcrypt_sha_ctx_internal_t; - -#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) -#define SHA1_LEN 5u -#define SHA256_LEN 8u -#endif - -/*!< SHA-1 and SHA-256 digest length in bytes */ -enum _hashcrypt_sha_digest_len -{ - kHASHCRYPT_OutLenSha1 = 20u, - kHASHCRYPT_OutLenSha256 = 32u, -}; - -/*!< pointer to hash context structure used by isr */ -static hashcrypt_hash_ctx_t *s_ctx; - -/*!< macro for checking build time condition. It is used to assure the hashcrypt_sha_ctx_internal_t can fit into - * hashcrypt_hash_ctx_t */ -#define BUILD_ASSERT(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused)) - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * @brief Swap bytes withing 32-bit word. - * - * This function changes endianess of a 32-bit word. - * - * @param in 32-bit unsigned integer - * @return 32-bit unsigned integer with different endianess (big endian to little endian and vice versa). - */ - -#define swap_bytes(in) __REV(in) - -/*! - * @brief Increment a 16 byte integer. - * - * This function increments by one a 16 byte integer. - * - * @param input Pointer to a 16 byte integer to be incremented by one. - */ -static void ctrIncrement(uint8_t *input) -{ - int i = 15; - while (input[i] == (uint8_t)0xFFu) - { - input[i] = (uint8_t)0x00u; - i--; - if (i < 0) - { - return; - } - } - - if (i >= 0) - { - input[i] += (uint8_t)1u; - } -} - -/*! - * @brief Reads an unaligned word. - * - * This function creates a 32-bit word from an input array of four bytes. - * - * @param src Input array of four bytes. The array can start at any address in memory. - * @return 32-bit unsigned int created from the input byte array. - */ - -/* Force lower optimization for Keil, otherwise it replaces inline LDR with LDM */ -#if defined(__CC_ARM) -#pragma push -#pragma O0 -#endif - -static inline uint32_t hashcrypt_get_word_from_unaligned(const uint8_t *srcAddr) -{ -#if (!(defined(__CORTEX_M)) || (defined(__CORTEX_M) && (__CORTEX_M == 0))) - register const uint8_t *src = srcAddr; - /* Cortex M0 does not support misaligned loads */ - if (0U != ((uint32_t)src & 0x3u)) - { - union _align_bytes_t - { - uint32_t word; - uint8_t byte[sizeof(uint32_t)]; - } my_bytes; - - my_bytes.byte[0] = *src; - my_bytes.byte[1] = src[1]; - my_bytes.byte[2] = src[2]; - my_bytes.byte[3] = src[3]; - return my_bytes.word; - } - else - { - /* addr aligned to 0-modulo-4 so it is safe to type cast */ - return *((const uint32_t *)(uint32_t)src); - } -#elif defined(__CC_ARM) - /* -O3 optimization in Keil 5.15 and 5.16a uses LDM instruction here (LDM r4!, {r0}) - * which is wrong, because srcAddr might be unaligned. - * LDM on unaligned address causes hard-fault. in contrary, - * LDR supports unaligned address on Cortex M4 */ - - register uint32_t retVal; - __asm - { - LDR retVal, [srcAddr] - } - return retVal; -#else - return *((const uint32_t *)(uintptr_t)srcAddr); -#endif -} - -/* End lower optimization */ -#if defined(__CC_ARM) -#pragma pop -#endif - -static status_t hashcrypt_get_key_from_unaligned_src(uint8_t *dest, const uint8_t *src, size_t size) -{ - status_t retVal = kStatus_InvalidArgument; - uint32_t i; - - /* destination is SDK driver internal workspace and it must be aligned */ - assert(0x0u == ((uint32_t)dest & 0x1u)); - if (0U != ((uint32_t)dest & 0x1u)) - { - return retVal; - } - - for (i = 0; i < ((uint32_t)size / 4u); i++) - { - ((uint32_t *)(uintptr_t)dest)[i] = hashcrypt_get_word_from_unaligned(&src[i * sizeof(uint32_t)]); - } - - return kStatus_Success; -} - -/*! - * @brief LDM to SHA engine INDATA and ALIAS registers. - * - * This function writes 16 words starting from the src address (must be word aligned) - * to the dst address. Dst address does not increment (destination is peripheral module register INDATA). - * Src address increments to load 16 consecutive words. - * - * @param dst peripheral register address (word aligned) - * @param src address of the input 512-bit block (16 words) (word aligned) - * - */ -__STATIC_FORCEINLINE void hashcrypt_sha_ldm_stm_16_words(HASHCRYPT_Type *base, const uint32_t *src) -{ - /* Data Synchronization Barrier */ - __DSB(); - /* - typedef struct _one_block - { - uint32_t a[8]; - } one_block_t; - - volatile one_block_t *ldst = (void *)(uintptr_t)(&base->INDATA); - one_block_t *lsrc = (void *)(uintptr_t)src; - *ldst = lsrc[0]; - *ldst = lsrc[1]; - */ - - /* Data Synchronization Barrier prevent compiler from reordering memory write when -O2 or higher is used. */ - /* The address is passed to the crypto engine for hashing below, therefore out */ - /* of order memory write due to compiler optimization must be prevented. */ - __DSB(); - - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(src); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(1); - - __DSB(); -} - -/*! - * @brief Loads data to Hashcrypt engine INDATA register. - * - * This function writes desired number of bytes starting from the src address - * to the dst address. Dst address does not increment (destination is peripheral module register INDATA). - * Src address increments to load consecutive words. - * - * @param src address of the input block - * @param size number of bytes to write - * - */ -__STATIC_INLINE void hashcrypt_load_data(HASHCRYPT_Type *base, uint32_t *src, size_t size) -{ - /* 16 bytes aligned input block */ - uint32_t __attribute__((aligned(4))) inAlign[HASHCRYPT_AES_BLOCK_SIZE / sizeof(uint32_t)]; - uint32_t *in; - uint8_t i; - - in = src; - /* Check if address of src data is aligned */ - if ((0U != ((uint32_t)in & 3U))) - { - for (i = 0; i < ((uint32_t)size / 4U); i++) - { - inAlign[i] = hashcrypt_get_word_from_unaligned((uint8_t *)&src[i]); - } - in = &inAlign[0]; - } - - if (size >= sizeof(uint32_t)) - { - base->INDATA = in[0]; - size -= sizeof(uint32_t); - } - - for (uint32_t j = 0; j < size / 4U; j++) - { - base->ALIAS[j] = in[j + 1U]; - } -} - -/*! - * @brief Checks availability of HW AES key. - * - * This function checks if the AES key is present at dedicated hardware bus - * and can be used at actual security level. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @return kStatus_Success if available, kStatus_Fail otherwise. - * - */ -static status_t hashcrypt_check_need_key(HASHCRYPT_Type *base, hashcrypt_handle_t *handle) -{ - if (handle->keyType == kHASHCRYPT_SecretKey) - { - volatile uint32_t wait = 50u; - /* wait until STATUS register is non-zero */ - while ((wait > 0U) && (base->STATUS == 0U)) - { - wait--; - } - /* if NEEDKEY bit is not set, HW key is available */ - if (0U == (base->STATUS & HASHCRYPT_STATUS_NEEDKEY_MASK)) - { - return kStatus_Success; - } - /* NEEDKEY is set, HW key is not available */ - return kStatus_Fail; - } - else - { - /* in case user key is used, return success */ - return kStatus_Success; - } -} - -/*! - * @brief Read OUTDATA registers. - * - * This function copies OUTDATA to output buffer. - * - * @param base Hachcrypt peripheral base address. - * @param[out] output Output buffer. - * @param Number of bytes to copy. - */ -static void hashcrypt_get_data(HASHCRYPT_Type *base, uint32_t *output, size_t outputSize) -{ - uint32_t digest[8]; - - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - - /* Data Synchronization Barrier */ - __DSB(); - - for (int i = 0; i < 8; i++) - { - digest[i] = swap_bytes(base->DIGEST0[i]); - } - - if (outputSize > sizeof(digest)) - { - outputSize = sizeof(digest); - } - (void)hashcrypt_memcpy(output, digest, outputSize); -} - -/*! - * @brief Initialize the Hashcrypt engine for new operation. - * - * This function sets NEW and MODE fields in Hashcrypt Control register to start new operation. - * - * @param base Hashcrypt peripheral base address. - * @param hashcrypt_algo_t Internal context. - */ -static void hashcrypt_engine_init(HASHCRYPT_Type *base, hashcrypt_algo_t algo) -{ - /* NEW bit must be set before we switch from previous mode otherwise new mode will not work correctly */ - base->CTRL = HASHCRYPT_CTRL_NEW_HASH(1); - base->CTRL = HASHCRYPT_CTRL_MODE(algo) | HASHCRYPT_CTRL_NEW_HASH(1); -} - -/*! - * @brief Deinitialization of the Hashcrypt engine. - * - * This function sets MODE field in Hashcrypt Control register to zero - disabled. - * This reduces power consumption of HASHCRYPT. - * - * @param base Hashcrypt peripheral base address. - */ -static inline void hashcrypt_engine_deinit(HASHCRYPT_Type *base) -{ - base->CTRL &= ~(HASHCRYPT_CTRL_MODE_MASK); -} - -/*! - * @brief Loads user key to INDATA register. - * - * This function writes user key stored in handle into HashCrypt INDATA register. - * - * @param base Hashcrypt peripheral base address. - * @param handle Handle used for this request. - */ -static void hashcrypt_aes_load_userKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle) -{ - size_t keySize = 0; - - switch (handle->keySize) - { - case kHASHCRYPT_Aes128: - keySize = 16; - break; - case kHASHCRYPT_Aes192: - keySize = 24; - break; - case kHASHCRYPT_Aes256: - keySize = 32; - break; - default: - /* All the cases have been listed above, the default clause should not be reached. */ - break; - } - if (keySize == 0U) - { - return; - } - hashcrypt_load_data(base, &handle->keyWord[0], keySize); -} - -/*! - * @brief Performs AES encryption/decryption of one data block. - * - * This function encrypts/decrypts one block of data with specified size. - * - * @param base Hashcrypt peripheral base address. - * @param input input data - * @param output output data - * @param size size of data block to process in bytes (must be 16bytes multiple). - */ -static status_t hashcrypt_aes_one_block_aligned(HASHCRYPT_Type *base, - const uint8_t *input, - uint8_t *output, - size_t size) -{ - status_t status = kStatus_Fail; - uint32_t idx = 0; - - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(input); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(size / 16U); - while (size >= HASHCRYPT_AES_BLOCK_SIZE) - { - /* Get result */ - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - - for (int i = 0; i < 4; i++) - { - ((uint32_t *)(uintptr_t)output + idx)[i] = swap_bytes(base->DIGEST0[i]); - } - - idx += HASHCRYPT_AES_BLOCK_SIZE / 4U; - size -= HASHCRYPT_AES_BLOCK_SIZE; - } - - if (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * @brief Performs AES encryption/decryption of one data block. - * - * This function encrypts/decrypts one block of data with specified size. - * - * @param base Hashcrypt peripheral base address. - * @param input input data - * @param output output data - * @param size size of data block to process in bytes (must be 16bytes multiple). - */ -static status_t hashcrypt_aes_one_block_unaligned(HASHCRYPT_Type *base, - const uint8_t *input, - uint8_t *output, - size_t size) -{ - status_t status = kStatus_Fail; - - /* we use AHB master mode as much as possible */ - /* however, it can work only with aligned input data */ - /* so, if unaligned, we do memcpy to temp buffer on stack, which is aligned, and use AHB mode to read data in */ - /* then we read data back to it and do memcpy to the output buffer */ - uint32_t temp[256 / sizeof(uint32_t)]; - int cnt = 0; - while (size != 0U) - { - size_t actSz = size >= 256u ? 256u : size; - size_t actSzOrig = actSz; - (void)memcpy(temp, (const uint32_t *)(uintptr_t)(input + 256 * cnt), actSz); - size -= actSz; - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(temp); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(actSz / 16U); - uint32_t outidx = 0; - while (actSz != 0U) - { - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - for (int i = 0; i < 4; i++) - { - (temp + outidx)[i] = swap_bytes(base->DIGEST0[i]); - } - outidx += HASHCRYPT_AES_BLOCK_SIZE / 4U; - actSz -= HASHCRYPT_AES_BLOCK_SIZE; - } - (void)memcpy(output + 256 * cnt, (const uint8_t *)(uintptr_t)temp, actSzOrig); - cnt++; - } - - if (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * @brief Performs AES encryption/decryption of one data block. - * - * This function encrypts/decrypts one block of data with specified size. - * - * @param base Hashcrypt peripheral base address. - * @param input input data - * @param output output data - * @param size size of data block to process in bytes (must be 16bytes multiple). - */ -static status_t hashcrypt_aes_one_block(HASHCRYPT_Type *base, const uint8_t *input, uint8_t *output, size_t size) -{ - status_t status = kStatus_Fail; - - /*MEMCTRL bitfield for COUNT is 11 bits, and this limits the number of blocks to process in one Master run to 2047 - (2^11 -1) blocks . Each block is 16bytes long, so biggest data size which can we do in one Master run is (2047 - blocks *16 bytes) = 32752 So, when size is overflowing HASHCRYPT_MEMCTRL_COUNT field of MEMCTRL register, we split - our data into more smaller chunks */ - - if (size > 32752U) - - { - size_t numBlock = size / 32752U; /* number of blocks, each block is processed in one run*/ - size_t remainingSize = size - (numBlock * 32752U); /* size of last block */ - - if ((0U != ((uint32_t)input & 0x3u)) || (0U != ((uint32_t)output & 0x3u))) /* If data is unaligned*/ - { - for (uint32_t i = 0; i < numBlock; i++) - { - status = hashcrypt_aes_one_block_unaligned(base, input, output, 32752U); - input += 32752U; - output += 32752U; - } - status = hashcrypt_aes_one_block_unaligned(base, input, output, remainingSize); - } - else /* If data is aligned*/ - { - for (uint32_t i = 0; i < numBlock; i++) - { - status = hashcrypt_aes_one_block_aligned(base, input, output, 32752U); - input += 32752U; - output += 32752U; - } - status = hashcrypt_aes_one_block_aligned(base, input, output, remainingSize); - } - } - - else /* size is less than COUNT field of MEMCTRL register so we can process all data at once */ - { - /* we use AHB master mode as much as possible */ - /* however, it can work only with aligned input data */ - /* so, if unaligned, we do memcpy to temp buffer on stack, which is aligned, and use AHB mode to read data in */ - /* then we read data back to it and do memcpy to the output buffer */ - if ((0U != ((uint32_t)input & 0x3u)) || (0U != ((uint32_t)output & 0x3u))) - { - status = hashcrypt_aes_one_block_unaligned(base, input, output, size); - } - else - { - status = hashcrypt_aes_one_block_aligned(base, input, output, size); - } - } - return status; -} - -/*! - * @brief Check validity of algoritm. - * - * This function checks the validity of input argument. - * - * @param algo Tested algorithm value. - * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. - */ -static status_t hashcrypt_sha_check_input_alg(HASHCRYPT_Type *base, hashcrypt_algo_t algo) -{ - if ((algo == kHASHCRYPT_Sha1) || (algo == kHASHCRYPT_Sha256)) - { - return kStatus_Success; - } - - return kStatus_InvalidArgument; -} - -/*! - * @brief Check validity of input arguments. - * - * This function checks the validity of input arguments. - * - * @param base SHA peripheral base address. - * @param ctx Memory buffer given by user application where the SHA_Init/SHA_Update/SHA_Finish store context. - * @param algo Tested algorithm value. - * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. - */ -static status_t hashcrypt_sha_check_input_args(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo) -{ - /* Check validity of input algorithm */ - if (kStatus_Success != hashcrypt_sha_check_input_alg(base, algo)) - { - return kStatus_InvalidArgument; - } - - if ((NULL == ctx) || (NULL == base)) - { - return kStatus_InvalidArgument; - } - - return kStatus_Success; -} - -/*! - * @brief Check validity of internal software context. - * - * This function checks if the internal context structure looks correct. - * - * @param ctxInternal Internal context. - * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. - */ -static status_t hashcrypt_sha_check_context(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) -{ - if ((NULL == ctxInternal) || (kStatus_Success != hashcrypt_sha_check_input_alg(base, ctxInternal->algo))) - { - return kStatus_InvalidArgument; - } - return kStatus_Success; -} - -/*! - * @brief Load 512-bit block (16 words) into SHA engine. - * - * This function aligns the input block and moves it into SHA engine INDATA. - * CPU polls the WAITING bit and then moves data by using LDM and STM instructions. - * - * @param base SHA peripheral base address. - * @param blk 512-bit block - */ -static void hashcrypt_sha_one_block(HASHCRYPT_Type *base, const uint8_t *blk) -{ - uint32_t temp[SHA_BLOCK_SIZE / sizeof(uint32_t)]; - const uint32_t *actBlk; - - /* make sure the 512-bit block is word aligned */ - if (0U != ((uintptr_t)blk & 0x3u)) - { - (void)hashcrypt_memcpy(temp, (const uint32_t *)(uintptr_t)blk, SHA_BLOCK_SIZE); - actBlk = (const uint32_t *)(uintptr_t)temp; - } - else - { - actBlk = (const uint32_t *)(uintptr_t)blk; - } - - /* poll waiting. */ - while (0U == (base->STATUS & HASHCRYPT_STATUS_WAITING_MASK)) - { - } - /* feed INDATA (and ALIASes). use STM instruction. */ - hashcrypt_sha_ldm_stm_16_words(base, actBlk); -} - -/*! - * @brief Adds message to current hash. - * - * This function merges the message to fill the internal buffer, empties the internal buffer if - * it becomes full, then process all remaining message data. - * - * - * @param base SHA peripheral base address. - * @param ctxInternal Internal context. - * @param message Input message. - * @param messageSize Size of input message in bytes. - * @return kStatus_Success. - */ -static status_t hashcrypt_sha_process_message_data(HASHCRYPT_Type *base, - hashcrypt_sha_ctx_internal_t *ctxInternal, - const uint8_t *message, - size_t messageSize) -{ - /* first fill the internal buffer to full block */ - if (ctxInternal->blksz != 0U) - { - size_t toCopy = SHA_BLOCK_SIZE - ctxInternal->blksz; - (void)hashcrypt_memcpy(&ctxInternal->blk.b[ctxInternal->blksz], message, toCopy); - message += toCopy; - messageSize -= toCopy; - - /* process full internal block */ - hashcrypt_sha_one_block(base, &ctxInternal->blk.b[0]); - } - - /* process all full blocks in message[] */ - if (messageSize >= SHA_BLOCK_SIZE) - { - if (0U != ((uintptr_t)message & 0x3u)) - { - while (messageSize >= SHA_BLOCK_SIZE) - { - hashcrypt_sha_one_block(base, message); - message += SHA_BLOCK_SIZE; - messageSize -= SHA_BLOCK_SIZE; - } - } - else - { - /* poll waiting. */ - while (0U == (base->STATUS & HASHCRYPT_STATUS_WAITING_MASK)) - { - } - uint32_t blkNum = (messageSize >> 6); /* div by 64 bytes */ - uint32_t blkBytes = blkNum * 64u; /* number of bytes in 64 bytes blocks */ - __DSB(); - __ISB(); - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(message); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(blkNum); - message += blkBytes; - messageSize -= blkBytes; - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - } - } - - /* copy last incomplete message bytes into internal block */ - (void)hashcrypt_memcpy(&ctxInternal->blk.b[0], message, messageSize); - ctxInternal->blksz = messageSize; - return kStatus_Success; -} - -/*! - * @brief Finalize the running hash to make digest. - * - * This function empties the internal buffer, adds padding bits, and generates final digest. - * - * @param base SHA peripheral base address. - * @param ctxInternal Internal context. - * @return kStatus_Success. - */ -static status_t hashcrypt_sha_finalize(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) -{ - hashcrypt_sha_block_t lastBlock; - - (void)memset(&lastBlock, 0, sizeof(hashcrypt_sha_block_t)); - - /* this is last call, so need to flush buffered message bytes along with padding */ - if (ctxInternal->blksz <= 55u) - { - /* last data is 440 bits or less. */ - (void)hashcrypt_memcpy(&lastBlock.b[0], &ctxInternal->blk.b[0], ctxInternal->blksz); - lastBlock.b[ctxInternal->blksz] = (uint8_t)0x80U; - lastBlock.w[SHA_BLOCK_SIZE / 4U - 1U] = swap_bytes(8u * ctxInternal->fullMessageSize); - hashcrypt_sha_one_block(base, &lastBlock.b[0]); - } - else - { - if (ctxInternal->blksz < SHA_BLOCK_SIZE) - { - ctxInternal->blk.b[ctxInternal->blksz] = (uint8_t)0x80U; - for (uint32_t i = ctxInternal->blksz + 1u; i < SHA_BLOCK_SIZE; i++) - { - ctxInternal->blk.b[i] = 0; - } - } - else - { - lastBlock.b[0] = (uint8_t)0x80U; - } - - hashcrypt_sha_one_block(base, &ctxInternal->blk.b[0]); - lastBlock.w[SHA_BLOCK_SIZE / 4U - 1U] = swap_bytes(8u * ctxInternal->fullMessageSize); - hashcrypt_sha_one_block(base, &lastBlock.b[0]); - } - /* poll wait for final digest */ - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - return kStatus_Success; -} - -static void hashcrypt_save_running_hash(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) -{ -#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) - size_t len = (ctxInternal->algo == kHASHCRYPT_Sha1) ? SHA1_LEN : SHA256_LEN; - - /* Wait until digest is ready */ - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - - /* Store partial digest to context */ - for (uint32_t i = 0; i < len; i++) - { - ctxInternal->runningHash[i] = base->DIGEST0[i]; - } -#endif -} - -static void hashcrypt_restore_running_hash(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) -{ -#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) - size_t len = (ctxInternal->algo == kHASHCRYPT_Sha1) ? SHA1_LEN : SHA256_LEN; - - /* When switching from different mode, need to set NEW bit to work properly */ - if ((base->CTRL & HASHCRYPT_CTRL_MODE_MASK) != HASHCRYPT_CTRL_MODE(ctxInternal->algo)) - { - base->CTRL = HASHCRYPT_CTRL_NEW_HASH(1); - base->CTRL = HASHCRYPT_CTRL_MODE(ctxInternal->algo) | HASHCRYPT_CTRL_NEW_HASH(1); - } - /* Set RELOAD bit to allow registers to be used */ - base->CTRL |= HASHCRYPT_CTRL_RELOAD_MASK; - - /* Reload partial hash digest */ - for (uint32_t i = 0; i < len; i++) - { - base->RELOAD[i] = ctxInternal->runningHash[i]; - } - /* Clear RELOAD register before continuing */ - base->CTRL &= ~HASHCRYPT_CTRL_RELOAD_MASK; -#endif -} - -status_t HASHCRYPT_SHA(HASHCRYPT_Type *base, - hashcrypt_algo_t algo, - const uint8_t *input, - size_t inputSize, - uint8_t *output, - size_t *outputSize) -{ - hashcrypt_hash_ctx_t hashCtx; - status_t status; - - status = HASHCRYPT_SHA_Init(base, &hashCtx, algo); - if (status != kStatus_Success) - { - return status; - } - - status = HASHCRYPT_SHA_Update(base, &hashCtx, input, inputSize); - if (status != kStatus_Success) - { - return status; - } - - status = HASHCRYPT_SHA_Finish(base, &hashCtx, output, outputSize); - - return status; -} - -status_t HASHCRYPT_SHA_Init(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo) -{ - status_t status; - - hashcrypt_sha_ctx_internal_t *ctxInternal; - /* compile time check for the correct structure size */ - BUILD_ASSERT(sizeof(hashcrypt_hash_ctx_t) >= sizeof(hashcrypt_sha_ctx_internal_t), hashcrypt_hash_ctx_t_size); - - status = hashcrypt_sha_check_input_args(base, ctx, algo); - if (status != kStatus_Success) - { - return status; - } - - /* set algorithm in context struct for later use */ - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; - ctxInternal->algo = algo; - ctxInternal->blksz = 0u; -#ifdef HASHCRYPT_SHA_DO_WIPE_CONTEXT - for (int i = 0; i < sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]); i++) - { - ctxInternal->blk.w[i] = 0u; - } -#endif /* HASHCRYPT_SHA_DO_WIPE_CONTEXT */ - ctxInternal->state = kHASHCRYPT_HashInit; - ctxInternal->fullMessageSize = 0; - return kStatus_Success; -} - -status_t HASHCRYPT_SHA_Update(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize) -{ - bool isUpdateState; - status_t status; - hashcrypt_sha_ctx_internal_t *ctxInternal; - size_t blockSize; - - if (inputSize == 0U) - { - return kStatus_Success; - } - - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; -#ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT - status = hashcrypt_sha_check_context(base, ctxInternal); - if (kStatus_Success != status) - { - return status; - } -#endif /* HASHCRYPT_SHA_DO_CHECK_CONTEXT */ - - ctxInternal->fullMessageSize += inputSize; - blockSize = SHA_BLOCK_SIZE; - /* if we are still less than 64 bytes, keep only in context */ - if ((ctxInternal->blksz + inputSize) <= blockSize) - { - (void)hashcrypt_memcpy((&ctxInternal->blk.b[0]) + ctxInternal->blksz, input, inputSize); - ctxInternal->blksz += inputSize; - return kStatus_Success; - } - else - { - isUpdateState = ctxInternal->state == kHASHCRYPT_HashUpdate; - if (!isUpdateState) - { - /* start NEW hash */ - hashcrypt_engine_init(base, ctxInternal->algo); - ctxInternal->state = kHASHCRYPT_HashUpdate; - } - else - { - hashcrypt_restore_running_hash(base, ctxInternal); - } - } - - /* process message data */ - /* Data Synchronization Barrier */ - __DSB(); - status = hashcrypt_sha_process_message_data(base, ctxInternal, input, inputSize); - hashcrypt_save_running_hash(base, ctxInternal); - return status; -} - -status_t HASHCRYPT_SHA_Finish(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize) -{ - size_t algOutSize = 0; - status_t status; - hashcrypt_sha_ctx_internal_t *ctxInternal; -#ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT - uint32_t *ctxW; - uint32_t i; -#endif /* HASHCRYPT_SHA_DO_CHECK_CONTEXT */ - - if (output == NULL) - { - return kStatus_InvalidArgument; - } - - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; -#ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT - status = hashcrypt_sha_check_context(base, ctxInternal); - if (kStatus_Success != status) - { - return status; - } -#endif /* HASHCRYPT_SHA_DO_CHECK_CONTEXT */ - - if (ctxInternal->state == kHASHCRYPT_HashInit) - { - hashcrypt_engine_init(base, ctxInternal->algo); - } - else - { - hashcrypt_restore_running_hash(base, ctxInternal); - } - - size_t outSize = 0u; - - /* compute algorithm output length */ - switch (ctxInternal->algo) - { - case kHASHCRYPT_Sha1: - outSize = (size_t)kHASHCRYPT_OutLenSha1; - break; - case kHASHCRYPT_Sha256: - outSize = (size_t)kHASHCRYPT_OutLenSha256; - break; - default: - /* All the cases have been listed above, the default clause should not be reached. */ - break; - } - algOutSize = outSize; - - /* flush message last incomplete block, if there is any, and add padding bits */ - status = hashcrypt_sha_finalize(base, ctxInternal); - - if (outputSize != NULL) - { - if (algOutSize < *outputSize) - { - *outputSize = algOutSize; - } - else - { - algOutSize = *outputSize; - } - } - - hashcrypt_get_data(base, (uint32_t *)(uintptr_t)output, algOutSize); - -#ifdef HASHCRYPT_SHA_DO_WIPE_CONTEXT - ctxW = (uint32_t *)ctx; - for (i = 0; i < HASHCRYPT_HASH_CTX_SIZE; i++) - { - ctxW[i] = 0u; - } -#endif /* HASHCRYPT_SHA_DO_WIPE_CONTEXT */ - return status; -} - -void HASHCRYPT_SHA_SetCallback(HASHCRYPT_Type *base, - hashcrypt_hash_ctx_t *ctx, - hashcrypt_callback_t callback, - void *userData) -{ - hashcrypt_sha_ctx_internal_t *ctxInternal; - - s_ctx = ctx; - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; - ctxInternal->hashCallback = callback; - ctxInternal->userData = userData; - - (void)EnableIRQ(HASHCRYPT_IRQn); -} - -status_t HASHCRYPT_SHA_UpdateNonBlocking(HASHCRYPT_Type *base, - hashcrypt_hash_ctx_t *ctx, - const uint8_t *input, - size_t inputSize) -{ - hashcrypt_sha_ctx_internal_t *ctxInternal; - uint32_t numBlocks; - status_t status; - - if (inputSize == 0U) - { - return kStatus_Success; - } - - if (0U != ((uintptr_t)input & 0x3U)) - { - return kStatus_Fail; - } - - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; - status = hashcrypt_sha_check_context(base, ctxInternal); - if (kStatus_Success != status) - { - return status; - } - - ctxInternal->fullMessageSize = inputSize; - ctxInternal->remainingBlcks = inputSize / SHA_BLOCK_SIZE; - ctxInternal->blksz = inputSize % SHA_BLOCK_SIZE; - - /* copy last incomplete block to context */ - if ((ctxInternal->blksz > 0U) && (ctxInternal->blksz <= SHA_BLOCK_SIZE)) - { - (void)hashcrypt_memcpy((&ctxInternal->blk.b[0]), input + SHA_BLOCK_SIZE * ctxInternal->remainingBlcks, - ctxInternal->blksz); - } - - if (ctxInternal->remainingBlcks >= SHA_MASTER_MAX_BLOCKS) - { - numBlocks = SHA_MASTER_MAX_BLOCKS - 1U; - } - else - { - numBlocks = ctxInternal->remainingBlcks; - } - /* update remainingBlks so that ISR can run another hash if necessary */ - ctxInternal->remainingBlcks -= numBlocks; - - /* compute hash using AHB Master mode for full blocks */ - if (numBlocks > 0U) - { - ctxInternal->state = kHASHCRYPT_HashUpdate; - hashcrypt_engine_init(base, ctxInternal->algo); - - /* Enable digest and error interrupts and start hash */ - base->INTENSET = HASHCRYPT_INTENCLR_DIGEST_MASK | HASHCRYPT_INTENCLR_ERROR_MASK; - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(input); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(numBlocks); - } - /* no full blocks, invoke callback directly */ - else - { - ctxInternal->hashCallback(HASHCRYPT, ctx, status, ctxInternal->userData); - } - - return status; -} - -status_t HASHCRYPT_AES_SetKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *key, size_t keySize) -{ - status_t retVal = kStatus_InvalidArgument; - - switch (keySize) - { - case 16: - handle->keySize = kHASHCRYPT_Aes128; - break; - case 24: - handle->keySize = kHASHCRYPT_Aes192; - break; - case 32: - handle->keySize = kHASHCRYPT_Aes256; - break; - default: - handle->keySize = kHASHCRYPT_InvalidKey; - break; - } - - if (handle->keySize == kHASHCRYPT_InvalidKey) - { - return retVal; - } - - if (handle->keyType == kHASHCRYPT_SecretKey) - { - /* for kHASHCRYPT_SecretKey just return Success */ - retVal = kStatus_Success; - } - else if (handle->keyType == kHASHCRYPT_UserKey) - { - retVal = hashcrypt_get_key_from_unaligned_src((uint8_t *)&handle->keyWord[0], key, keySize); - } - else - { - retVal = kStatus_InvalidArgument; - } - - return retVal; -} - -status_t HASHCRYPT_AES_EncryptEcb( - HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size) -{ - status_t status = kStatus_Fail; - - if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesEcb) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load message and get result */ - status = hashcrypt_aes_one_block(base, plaintext, ciphertext, size); - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - - return status; -} - -status_t HASHCRYPT_AES_DecryptEcb( - HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size) -{ - status_t status = kStatus_Fail; - - if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesEcb) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_DECRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load message and get result */ - status = hashcrypt_aes_one_block(base, ciphertext, plaintext, size); - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -status_t HASHCRYPT_AES_EncryptCbc(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t iv[16]) -{ - status_t status = kStatus_Fail; - - if (0U != ((size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load 16b iv */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, 16); - - /* load message and get result */ - status = hashcrypt_aes_one_block(base, plaintext, ciphertext, size); - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -status_t HASHCRYPT_AES_DecryptCbc(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t iv[16]) -{ - status_t status = kStatus_Fail; - - if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_DECRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load iv */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, 16); - - /* load message and get result */ - status = hashcrypt_aes_one_block(base, ciphertext, plaintext, size); - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *input, - uint8_t *output, - size_t size, - uint8_t counter[HASHCRYPT_AES_BLOCK_SIZE], - uint8_t counterlast[HASHCRYPT_AES_BLOCK_SIZE], - size_t *szLeft) -{ - uint32_t lastSize; - uint8_t lastBlock[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - uint8_t *lastEncryptedCounter; - status_t status = kStatus_Fail; - - if (handle->keySize == kHASHCRYPT_InvalidKey) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCtr) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load nonce */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)counter, 16); - - lastSize = size % HASHCRYPT_AES_BLOCK_SIZE; - size -= lastSize; - - /* encrypt full 16byte blocks */ - status = hashcrypt_aes_one_block(base, input, output, size); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - - while (size != 0U) - { - ctrIncrement(counter); - size -= 16u; - input += 16; - output += 16; - } - - if (lastSize != 0U) - { - if (counterlast != NULL) - { - lastEncryptedCounter = counterlast; - } - else - { - lastEncryptedCounter = lastBlock; - } - - /* Perform encryption with all zeros to get last counter. XOR with zeros doesn't change. */ - status = hashcrypt_aes_one_block(base, lastBlock, lastEncryptedCounter, HASHCRYPT_AES_BLOCK_SIZE); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* remain output = input XOR counterlast */ - for (uint32_t i = 0; i < lastSize; i++) - { - output[i] = input[i] ^ lastEncryptedCounter[i]; - } - /* Increment counter parameter */ - ctrIncrement(counter); - } - else - { - lastSize = HASHCRYPT_AES_BLOCK_SIZE; - /* no remaining bytes in couterlast so clearing it */ - if (counterlast != NULL) - { - (void)memset(counterlast, 0, HASHCRYPT_AES_BLOCK_SIZE); - } - } - - if (szLeft != NULL) - { - *szLeft = HASHCRYPT_AES_BLOCK_SIZE - lastSize; - } - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return kStatus_Success; -} - -status_t HASHCRYPT_AES_CryptOfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *input, - uint8_t *output, - size_t size, - const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]) -{ - status_t status = kStatus_Fail; - uint8_t zeroes[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - uint8_t blockOutput[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - - if (handle->keySize == kHASHCRYPT_InvalidKey) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load iv */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, HASHCRYPT_AES_BLOCK_SIZE); - - /*Use AES CBC mode and feed input with zeroes as input*/ - /*Output block is then XORed with input*/ - - while (size >= 16u) - { - status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* XOR input with output block to get output*/ - for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) - { - output[i] = input[i] ^ blockOutput[i]; - } - size -= 16u; - output += 16; - input += 16; - } - - /* OFB can have non-block multiple size.*/ - if (size != 0U) - { - status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - - /* XOR input with output block to get output*/ - for (uint32_t i = 0; i < size; i++) - { - output[i] = input[i] ^ blockOutput[i]; - } - } - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -status_t HASHCRYPT_AES_EncryptCfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]) -{ - status_t status = kStatus_Fail; - uint8_t zeroes[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - uint8_t blockOutput[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - - /* For CFB mode size must be 16-byte multiple */ - if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load iv */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, HASHCRYPT_AES_BLOCK_SIZE); - - /*Use AES CBC mode and feed input with zeroes for first block */ - /*Output block is then XORed with plaintext to get ciphertext*/ - - status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* XOR plaintext with output block to get ciphertext*/ - for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) - { - ciphertext[i] = plaintext[i] ^ blockOutput[i]; - } - size -= 16u; - - /*Remaining blocks use previous plaintext as input for aes block function */ - while (size >= 16u) - { - status = hashcrypt_aes_one_block(base, plaintext, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - ciphertext += 16; - plaintext += 16; - - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* XOR plaintext with output block to get ciphertext*/ - for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) - { - ciphertext[i] = plaintext[i] ^ blockOutput[i]; - } - size -= 16u; - } - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -status_t HASHCRYPT_AES_DecryptCfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]) -{ - status_t status = kStatus_Fail; - uint8_t zeroes[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - uint8_t blockOutput[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - - /* For CFB mode size must be 16-byte multiple */ - if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load iv */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, HASHCRYPT_AES_BLOCK_SIZE); - - /*Use AES CBC mode and feed input with zeroes for first block */ - /*Output block is then XORed with ciphertext to get plaintext*/ - - status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* XOR ciphertext with output block to get plaintext*/ - for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) - { - plaintext[i] = ciphertext[i] ^ blockOutput[i]; - } - size -= 16u; - - /*Remaining blocks use previous plaintext as input for aes block function */ - while (size >= 16u) - { - status = hashcrypt_aes_one_block(base, plaintext, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - ciphertext += 16; - plaintext += 16; - - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* XOR plaintext with ciphertext block to get plaintext*/ - for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) - { - plaintext[i] = ciphertext[i] ^ blockOutput[i]; - } - size -= 16u; - } - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -void HASHCRYPT_DriverIRQHandler(void); -void HASHCRYPT_DriverIRQHandler(void) -{ - hashcrypt_sha_ctx_internal_t *ctxInternal; - HASHCRYPT_Type *base = HASHCRYPT; - uint32_t numBlocks; - status_t status; - - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)s_ctx; - - if (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) - { - if (ctxInternal->remainingBlcks > 0U) - { - if (ctxInternal->remainingBlcks >= SHA_MASTER_MAX_BLOCKS) - { - numBlocks = SHA_MASTER_MAX_BLOCKS - 1U; - } - else - { - numBlocks = ctxInternal->remainingBlcks; - } - /* some blocks still remaining, update remainingBlcks for next ISR and start another hash */ - ctxInternal->remainingBlcks -= numBlocks; - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(numBlocks); - return; - } - /* no full blocks left, disable interrupts and AHB master mode */ - base->INTENCLR = HASHCRYPT_INTENCLR_DIGEST_MASK | HASHCRYPT_INTENCLR_ERROR_MASK; - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(0); - hashcrypt_save_running_hash(base, ctxInternal); - status = kStatus_Success; - } - else - { - status = kStatus_Fail; - } - - /* Invoke callback if there is one */ - if (NULL != ctxInternal->hashCallback) - { - ctxInternal->hashCallback(HASHCRYPT, s_ctx, status, ctxInternal->userData); - } -} - -void HASHCRYPT_Init(HASHCRYPT_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_HashCrypt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - RESET_PeripheralReset(kHASHCRYPT_RST_SHIFT_RSTn); -} - -void HASHCRYPT_Deinit(HASHCRYPT_Type *base) -{ - RESET_SetPeripheralReset(kHASHCRYPT_RST_SHIFT_RSTn); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_HashCrypt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_hashcrypt.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_hashcrypt.h deleted file mode 100644 index fa15b8cf710..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_hashcrypt.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - * Copyright 2017-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_HASHCRYPT_H_ -#define _FSL_HASHCRYPT_H_ - -#include "fsl_common.h" - -/*! @brief HASHCRYPT status return codes. */ -enum _hashcrypt_status -{ - kStatus_HASHCRYPT_Again = - MAKE_STATUS(kStatusGroup_HASHCRYPT, 0), /*!< Non-blocking function shall be called again. */ -}; - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! - * @addtogroup hashcrypt_driver - * @{ - */ -/*! @name Driver version */ -/*@{*/ -/*! @brief HASHCRYPT driver version. Version 2.2.6. - * - * Current version: 2.2.6 - * - * Change log: - * - Version 2.0.0 - * - Initial version - * - Version 2.0.1 - * - Support loading AES key from unaligned address - * - Version 2.0.2 - * - Support loading AES key from unaligned address for different compiler and core variants - * - Version 2.0.3 - * - Remove SHA512 and AES ICB algorithm definitions - * - Version 2.0.4 - * - Add SHA context switch support - * - Version 2.1.0 - * - Update the register name and macro to align with new header. - * - Version 2.1.1 - * - Fix MISRA C-2012. - * - Version 2.1.2 - * - Support loading AES input data from unaligned address. - * - Version 2.1.3 - * - Fix MISRA C-2012. - * - Version 2.1.4 - * - Fix context switch cannot work when switching from AES. - * - Version 2.1.5 - * - Add data synchronization barrier inside hashcrypt_sha_ldm_stm_16_words() - * to prevent possible optimization issue. - * - Version 2.2.0 - * - Add AES-OFB and AES-CFB mixed IP/SW modes. - * - Version 2.2.1 - * - Add data synchronization barrier inside hashcrypt_sha_ldm_stm_16_words() - * prevent compiler from reordering memory write when -O2 or higher is used. - * - Version 2.2.2 - * - Add data synchronization barrier inside hashcrypt_sha_ldm_stm_16_words() - * to fix optimization issue - * - Version 2.2.3 - * - Added check for size in hashcrypt_aes_one_block to prevent overflowing COUNT field in MEMCTRL register, if its - * bigger than COUNT field do a multiple runs. - * - Version 2.2.4 - * - In all HASHCRYPT_AES_xx functions have been added setting CTRL_MODE bitfield to 0 after processing data, which - * decreases power consumption. - * - Version 2.2.5 - * - Add data synchronization barrier and instruction synchronization barrier inside - * hashcrypt_sha_process_message_data() to fix optimization issue - * - Version 2.2.6 - * - Add data synchronization barrier inside HASHCRYPT_SHA_Update() and hashcrypt_get_data() function to fix - * optimization issue on MDK and ARMGCC release targets - */ -#define FSL_HASHCRYPT_DRIVER_VERSION (MAKE_VERSION(2, 2, 6)) -/*@}*/ - -/*! @brief Algorithm definitions correspond with the values for Mode field in Control register !*/ -#define HASHCRYPT_MODE_SHA1 0x1 -#define HASHCRYPT_MODE_SHA256 0x2 -#define HASHCRYPT_MODE_AES 0x4 - -/*! @brief Algorithm used for Hashcrypt operation */ -typedef enum _hashcrypt_algo_t -{ - kHASHCRYPT_Sha1 = HASHCRYPT_MODE_SHA1, /*!< SHA_1 */ - kHASHCRYPT_Sha256 = HASHCRYPT_MODE_SHA256, /*!< SHA_256 */ - kHASHCRYPT_Aes = HASHCRYPT_MODE_AES, /*!< AES */ -} hashcrypt_algo_t; - -/*! @} */ - -/******************************************************************************* - * AES Definitions - *******************************************************************************/ - -/*! - * @addtogroup hashcrypt_driver_aes - * @{ - */ - -/*! AES block size in bytes */ -#define HASHCRYPT_AES_BLOCK_SIZE 16U -#define AES_ENCRYPT 0 -#define AES_DECRYPT 1 - -/*! @brief AES mode */ -typedef enum _hashcrypt_aes_mode_t -{ - kHASHCRYPT_AesEcb = 0U, /*!< AES ECB mode */ - kHASHCRYPT_AesCbc = 1U, /*!< AES CBC mode */ - kHASHCRYPT_AesCtr = 2U, /*!< AES CTR mode */ -} hashcrypt_aes_mode_t; - -/*! @brief Size of AES key */ -typedef enum _hashcrypt_aes_keysize_t -{ - kHASHCRYPT_Aes128 = 0U, /*!< AES 128 bit key */ - kHASHCRYPT_Aes192 = 1U, /*!< AES 192 bit key */ - kHASHCRYPT_Aes256 = 2U, /*!< AES 256 bit key */ - kHASHCRYPT_InvalidKey = 3U, /*!< AES invalid key */ -} hashcrypt_aes_keysize_t; - -/*! @brief HASHCRYPT key source selection. - * - */ -typedef enum _hashcrypt_key -{ - kHASHCRYPT_UserKey = 0xc3c3U, /*!< HASHCRYPT user key */ - kHASHCRYPT_SecretKey = 0x3c3cU, /*!< HASHCRYPT secret key (dedicated hw bus from PUF) */ -} hashcrypt_key_t; - -/*! @brief Specify HASHCRYPT's key resource. */ -struct _hashcrypt_handle -{ - uint32_t keyWord[8]; /*!< Copy of user key (set by HASHCRYPT_AES_SetKey(). */ - hashcrypt_aes_keysize_t keySize; - hashcrypt_key_t keyType; /*!< For operations with key (such as AES encryption/decryption), specify key type. */ -} __attribute__((aligned)); - -typedef struct _hashcrypt_handle hashcrypt_handle_t; - -/*! - *@} - */ /* end of hashcrypt_driver_aes */ - -/******************************************************************************* - * HASH Definitions - ******************************************************************************/ -/*! - * @addtogroup hashcrypt_driver_hash - * @{ - */ - -/*! @brief HASHCRYPT HASH Context size. */ -#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) -#define HASHCRYPT_HASH_CTX_SIZE 30 -#else -#define HASHCRYPT_HASH_CTX_SIZE 22 -#endif - -/*! @brief Storage type used to save hash context. */ -typedef struct _hashcrypt_hash_ctx_t -{ - uint32_t x[HASHCRYPT_HASH_CTX_SIZE]; /*!< storage */ -} hashcrypt_hash_ctx_t; - -/*! @brief HASHCRYPT background hash callback function. */ -typedef void (*hashcrypt_callback_t)(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, status_t status, void *userData); - -/*! - *@} - */ /* end of hashcrypt_driver_hash */ - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup hashcrypt_driver - * @{ - */ - -/*! - * @brief Enables clock and disables reset for HASHCRYPT peripheral. - * - * Enable clock and disable reset for HASHCRYPT. - * - * @param base HASHCRYPT base address - */ -void HASHCRYPT_Init(HASHCRYPT_Type *base); - -/*! - * @brief Disables clock for HASHCRYPT peripheral. - * - * Disable clock and enable reset. - * - * @param base HASHCRYPT base address - */ -void HASHCRYPT_Deinit(HASHCRYPT_Type *base); - -/*! - *@} - */ /* end of hashcrypt_driver */ - -/******************************************************************************* - * AES API - ******************************************************************************/ - -/*! - * @addtogroup hashcrypt_driver_aes - * @{ - */ - -/*! - * @brief Set AES key to hashcrypt_handle_t struct and optionally to HASHCRYPT. - * - * Sets the AES key for encryption/decryption with the hashcrypt_handle_t structure. - * The hashcrypt_handle_t input argument specifies key source. - * - * @param base HASHCRYPT peripheral base address. - * @param handle Handle used for the request. - * @param key 0-mod-4 aligned pointer to AES key. - * @param keySize AES key size in bytes. Shall equal 16, 24 or 32. - * @return status from set key operation - */ -status_t HASHCRYPT_AES_SetKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *key, size_t keySize); - -/*! - * @brief Encrypts AES on one or multiple 128-bit block(s). - * - * Encrypts AES. - * The source plaintext and destination ciphertext can overlap in system memory. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @return Status from encrypt operation - */ -status_t HASHCRYPT_AES_EncryptEcb( - HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size); - -/*! - * @brief Decrypts AES on one or multiple 128-bit block(s). - * - * Decrypts AES. - * The source ciphertext and destination plaintext can overlap in system memory. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param ciphertext Input plain text to encrypt - * @param[out] plaintext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @return Status from decrypt operation - */ -status_t HASHCRYPT_AES_DecryptEcb( - HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size); - -/*! - * @brief Encrypts AES using CBC block mode. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return Status from encrypt operation - */ -status_t HASHCRYPT_AES_EncryptCbc(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t iv[16]); - -/*! - * @brief Decrypts AES using CBC block mode. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param ciphertext Input cipher text to decrypt - * @param[out] plaintext Output plain text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return Status from decrypt operation - */ -status_t HASHCRYPT_AES_DecryptCbc(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t iv[16]); - -/*! - * @brief Encrypts or decrypts AES using CTR block mode. - * - * Encrypts or decrypts AES using CTR block mode. - * AES CTR mode uses only forward AES cipher and same algorithm for encryption and decryption. - * The only difference between encryption and decryption is that, for encryption, the input argument - * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text - * and the output argument is plain text. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param input Input data for CTR block mode - * @param[out] output Output data for CTR block mode - * @param size Size of input and output data in bytes - * @param[in,out] counter Input counter (updates on return) - * @param[out] counterlast Output cipher of last counter, for chained CTR calls (statefull encryption). NULL can be - * passed if chained calls are - * not used. - * @param[out] szLeft Output number of bytes in left unused in counterlast block. NULL can be passed if chained calls - * are not used. - * @return Status from encrypt operation - */ -status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *input, - uint8_t *output, - size_t size, - uint8_t counter[HASHCRYPT_AES_BLOCK_SIZE], - uint8_t counterlast[HASHCRYPT_AES_BLOCK_SIZE], - size_t *szLeft); - -/*! - * @brief Encrypts or decrypts AES using OFB block mode. - * - * Encrypts or decrypts AES using OFB block mode. - * AES OFB mode uses only forward AES cipher and same algorithm for encryption and decryption. - * The only difference between encryption and decryption is that, for encryption, the input argument - * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text - * and the output argument is plain text. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param input Input data for OFB block mode - * @param[out] output Output data for OFB block mode - * @param size Size of input and output data in bytes - * @param iv Input initial vector to combine with the first input block. - * @return Status from encrypt operation - */ - -status_t HASHCRYPT_AES_CryptOfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *input, - uint8_t *output, - size_t size, - const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]); - -/*! - * @brief Encrypts AES using CFB block mode. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return Status from encrypt operation - */ - -status_t HASHCRYPT_AES_EncryptCfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t iv[16]); - -/*! - * @brief Decrypts AES using CFB block mode. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param ciphertext Input cipher text to decrypt - * @param[out] plaintext Output plaintext text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return Status from encrypt operation - */ - -status_t HASHCRYPT_AES_DecryptCfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t iv[16]); -/*! - *@} - */ /* end of hashcrypt_driver_aes */ - -/******************************************************************************* - * HASH API - ******************************************************************************/ - -/*! - * @addtogroup hashcrypt_driver_hash - * @{ - */ - -/*! - * @brief Create HASH on given data - * - * Perform the full SHA in one function call. The function is blocking. - * - * @param base HASHCRYPT peripheral base address - * @param algo Underlaying algorithm to use for hash computation. - * @param input Input data - * @param inputSize Size of input data in bytes - * @param[out] output Output hash data - * @param[out] outputSize Output parameter storing the size of the output hash in bytes - * @return Status of the one call hash operation. - */ -status_t HASHCRYPT_SHA(HASHCRYPT_Type *base, - hashcrypt_algo_t algo, - const uint8_t *input, - size_t inputSize, - uint8_t *output, - size_t *outputSize); - -/*! - * @brief Initialize HASH context - * - * This function initializes the HASH. - * - * @param base HASHCRYPT peripheral base address - * @param[out] ctx Output hash context - * @param algo Underlaying algorithm to use for hash computation. - * @return Status of initialization - */ -status_t HASHCRYPT_SHA_Init(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo); - -/*! - * @brief Add data to current HASH - * - * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be - * hashed. The functions blocks. If it returns kStatus_Success, the running hash - * has been updated (HASHCRYPT has processed the input data), so the memory at \p input pointer - * can be released back to system. The HASHCRYPT context buffer is updated with the running hash - * and with all necessary information to support possible context switch. - * - * @param base HASHCRYPT peripheral base address - * @param[in,out] ctx HASH context - * @param input Input data - * @param inputSize Size of input data in bytes - * @return Status of the hash update operation - */ -status_t HASHCRYPT_SHA_Update(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize); - -/*! - * @brief Finalize hashing - * - * Outputs the final hash (computed by HASHCRYPT_HASH_Update()) and erases the context. - * - * @param base HASHCRYPT peripheral base address - * @param[in,out] ctx Input hash context - * @param[out] output Output hash data - * @param[in,out] outputSize Optional parameter (can be passed as NULL). On function entry, it specifies the size of - * output[] buffer. On function return, it stores the number of updated output bytes. - * @return Status of the hash finish operation - */ -status_t HASHCRYPT_SHA_Finish(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize); - -/*! - *@} - */ /* end of hashcrypt_driver_hash */ - -/*! - * @addtogroup hashcrypt_background_driver_hash - * @{ - */ - -/*! - * @brief Initializes the HASHCRYPT handle for background hashing. - * - * This function initializes the hash context for background hashing - * (Non-blocking) APIs. This is less typical interface to hash function, but can be used - * for parallel processing, when main CPU has something else to do. - * Example is digital signature RSASSA-PKCS1-V1_5-VERIFY((n,e),M,S) algorithm, where - * background hashing of M can be started, then CPU can compute S^e mod n - * (in parallel with background hashing) and once the digest becomes available, - * CPU can proceed to comparison of EM with EM'. - * - * @param base HASHCRYPT peripheral base address. - * @param[out] ctx Hash context. - * @param callback Callback function. - * @param userData User data (to be passed as an argument to callback function, once callback is invoked from isr). - */ -void HASHCRYPT_SHA_SetCallback(HASHCRYPT_Type *base, - hashcrypt_hash_ctx_t *ctx, - hashcrypt_callback_t callback, - void *userData); - -/*! - * @brief Create running hash on given data. - * - * Configures the HASHCRYPT to compute new running hash as AHB master - * and returns immediately. HASHCRYPT AHB Master mode supports only aligned \p input - * address and can be called only once per continuous block of data. Every call to this function - * must be preceded with HASHCRYPT_SHA_Init() and finished with HASHCRYPT_SHA_Finish(). - * Once callback function is invoked by HASHCRYPT isr, it should set a flag - * for the main application to finalize the hashing (padding) and to read out the final digest - * by calling HASHCRYPT_SHA_Finish(). - * - * @param base HASHCRYPT peripheral base address - * @param ctx Specifies callback. Last incomplete 512-bit block of the input is copied into clear buffer for padding. - * @param input 32-bit word aligned pointer to Input data. - * @param inputSize Size of input data in bytes (must be word aligned) - * @return Status of the hash update operation. - */ -status_t HASHCRYPT_SHA_UpdateNonBlocking(HASHCRYPT_Type *base, - hashcrypt_hash_ctx_t *ctx, - const uint8_t *input, - size_t inputSize); -/*! - *@} - */ /* end of hashcrypt_background_driver_hash */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_HASHCRYPT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2c.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2c.c deleted file mode 100644 index 9ecde80c90a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2c.c +++ /dev/null @@ -1,2085 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_i2c.h" -#include "fsl_flexcomm.h" -#include -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c" -#endif - -/*! @brief Common sets of flags used by the driver's transactional layer internally. */ -enum _i2c_flag_constants -{ - kI2C_MasterIrqFlags = I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | - I2C_INTSTAT_EVENTTIMEOUT_MASK | I2C_INTSTAT_SCLTIMEOUT_MASK, - kI2C_SlaveIrqFlags = I2C_INTSTAT_SLVPENDING_MASK | I2C_INTSTAT_SLVDESEL_MASK, -}; - -/*! - * @brief Used for conversion from `flexcomm_irq_handler_t` to `flexcomm_i2c_master_irq_handler_t` and - * `flexcomm_i2c_slave_irq_handler_t`. - */ -typedef union i2c_to_flexcomm -{ - flexcomm_i2c_master_irq_handler_t i2c_master_handler; - flexcomm_i2c_slave_irq_handler_t i2c_slave_handler; - flexcomm_irq_handler_t flexcomm_handler; -} i2c_to_flexcomm_t; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Waits for Master Pending status bit to set and check for bus error status. - * - * @param base The I2C peripheral base address. - * @return Bus status. - */ -static status_t I2C_PendingStatusWait(I2C_Type *base); - -/*! - * @brief Prepares the transfer state machine and fills in the command buffer. - * @param base The I2C peripheral base address. - * @param handle Master nonblocking driver handle. - * @param xfer The I2C transfer configuration structure. - */ -static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Resets the slave hardware state machine. - * According to documentation, after disabling slave to rest the slave hardware state machine, the register - * configuration remains unchanged. - * @param base The I2C peripheral base address. - */ -static void I2C_SlaveInternalStateMachineReset(I2C_Type *base); - -/*! - * @brief Compute CLKDIV - * - * This function computes CLKDIV value according to the given bus speed and Flexcomm source clock frequency. - * This setting is used by hardware during slave clock stretching. - * - * @param base The I2C peripheral base address. - * @return status of the operation - */ -static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal); - -/*! - * @brief Poll wait for the SLVPENDING flag. - * - * Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register. - * - * @param base The I2C peripheral base address. - * @return status register at time the SLVPENDING bit is read as set - */ -static uint32_t I2C_SlavePollPending(I2C_Type *base); - -/*! - * @brief Invoke event from I2C_SlaveTransferHandleIRQ(). - * - * Sets the event type to transfer structure and invokes the event callback, if it has been - * enabled by eventMask. - * - * @param base The I2C peripheral base address. - * @param handle The I2C slave handle for non-blocking APIs. - * @param event The I2C slave event to invoke. - */ -static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event); - -/*! - * @brief Handle slave address match event. - * - * Called by Slave interrupt routine to ACK or NACK the matched address. - * It also determines master direction (read or write). - * - * @param base The I2C peripheral base address. - * @return true if the matched address is ACK'ed - * @return false if the matched address is NACK'ed - */ -static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle); - -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. - * @param txData Data to be transmitted to master in response to master read from slave requests. NULL if slave RX only. - * @param txSize Size of txData buffer in bytes. - * @param rxData Data where received data from master will be stored in response to master write to slave requests. NULL - * if slave TX only. - * @param rxSize Size of rxData buffer in bytes. - * @retval #kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, - i2c_slave_handle_t *handle, - const void *txData, - size_t txSize, - void *rxData, - size_t rxSize, - uint32_t eventMask); - -/*! - * @brief Execute master transfer software state machine until FIFOs are exhausted. - * - * For master transmit, the states would be kStartState->kTransmitSubaddrState->kTransmitDataState->kStopState - * For master receive, the states would be kStartState->kTransmitSubaddrState->kStartState->kReceiveDataState-> - * kWaitForCompletionState - * - * @param handle Master nonblocking driver handle. - * @param[out] isDone Set to true if the transfer has completed. - * @retval #kStatus_Success - * @retval #kStatus_I2C_ArbitrationLost - * @retval #kStatus_I2C_Nak - */ -static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone); - -/*! - * @brief Checks the slave response to master's start signal. - * - * @param base I2C peripheral base address. - * @retval kStatus_Success Successfully complete the data transmission. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStataus_I2C_Nak Transfer error, receive NAK during addressing. - */ -static status_t I2C_MasterCheckStartResponse(I2C_Type *base); -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map i2c instance number to base address. */ -static const uint32_t s_i2cBaseAddrs[FSL_FEATURE_SOC_I2C_COUNT] = I2C_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_i2cIRQ[] = I2C_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * param base The I2C peripheral base address. - * return I2C instance number starting from 0. - */ -uint32_t I2C_GetInstance(I2C_Type *base) -{ - uint32_t i; - for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_I2C_COUNT; i++) - { - if ((uint32_t)base == s_i2cBaseAddrs[i]) - { - break; - } - } - assert(i < (uint32_t)FSL_FEATURE_SOC_I2C_COUNT); - return i; -} - -/*! - * brief Provides a default configuration for the I2C master peripheral. - * - * This function provides the following default configuration for the I2C master peripheral: - * code - * masterConfig->enableMaster = true; - * masterConfig->baudRate_Bps = 100000U; - * masterConfig->enableTimeout = false; - * endcode - * - * After calling this function, you can override any settings in order to customize the configuration, - * prior to initializing the master driver with I2C_MasterInit(). - * - * param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. - */ -void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) -{ - /* Initializes the configure structure to zero. */ - (void)memset(masterConfig, 0, sizeof(*masterConfig)); - - masterConfig->enableMaster = true; - masterConfig->baudRate_Bps = 100000U; - masterConfig->enableTimeout = false; - masterConfig->timeout_Ms = 35; -} - -/*! - * brief Initializes the I2C master peripheral. - * - * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user - * provided configuration. A software reset is performed prior to configuration. - * - * param base The I2C peripheral base address. - * param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of - * defaults - * that you can override. - * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, - * filter widths, and timeout periods. - */ -void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) -{ - (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); - I2C_MasterEnable(base, masterConfig->enableMaster); - I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); - I2C_MasterSetTimeoutValue(base, masterConfig->timeout_Ms, srcClock_Hz); -} - -/*! - * brief Deinitializes the I2C master peripheral. - * - * This function disables the I2C master peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * param base The I2C peripheral base address. - */ -void I2C_MasterDeinit(I2C_Type *base) -{ - I2C_MasterEnable(base, false); -} - -/*! - * brief Gets the I2C status flags. - * - * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit - * in the return value is set if the flag is asserted. - * - * param base The I2C peripheral base address. - * return State of the status flags: - * - 1: related status flag is set. - * - 0: related status flag is not set. - * see ref _i2c_status_flags, ref _i2c_master_status_flags and ref _i2c_slave_status_flags. - */ -uint32_t I2C_GetStatusFlags(I2C_Type *base) -{ - uint32_t statusMask = base->STAT; - if ((statusMask & (uint32_t)I2C_STAT_MSTSTATE_MASK) == 0UL) - { - statusMask |= (uint32_t)kI2C_MasterIdleFlag; - } - if (((statusMask & (uint32_t)I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == 3UL) - { - statusMask = (statusMask & ~(uint32_t)I2C_STAT_MSTSTATE_MASK) | (uint32_t)kI2C_MasterAddrNackFlag; - } - if ((statusMask & (uint32_t)I2C_STAT_SLVSTATE_MASK) == 0UL) - { - statusMask |= (uint32_t)kI2C_SlaveAddressedFlag; - } - if ((statusMask & (uint32_t)I2C_STAT_SLVIDX_MASK) == 0UL) - { - statusMask |= (uint32_t)kI2C_SlaveAddress0MatchFlag; - } - if (((statusMask & (uint32_t)I2C_STAT_SLVIDX_MASK) >> I2C_STAT_SLVIDX_SHIFT) == 3UL) - { - statusMask = (statusMask & ~(uint32_t)I2C_STAT_SLVIDX_MASK) | (uint32_t)kI2C_SlaveAddress3MatchFlag; - } - return statusMask; -} - -/*! - * brief Sets the I2C bus frequency for master transactions. - * - * The I2C master is automatically disabled and re-enabled as necessary to configure the baud - * rate. Do not call this function during a transfer, or the transfer is aborted. - * - * param base The I2C peripheral base address. - * param srcClock_Hz I2C functional clock frequency in Hertz. - * param baudRate_Bps Requested bus frequency in bits per second. - */ -void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) -{ - uint32_t scl, divider; - uint32_t mindivider; - uint32_t err, best_err; - uint32_t best_scl = 0U; - uint32_t best_div = 0U; - -#if defined(FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) && (FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) - /* - * RFT1717/RFT1437: workaround for hardware bug when using DMA - * I2C peripheral clock frequency has to be fixed at 8MHz - * source clock is 32MHz or 48MHz so divider is a round integer value - */ - best_div = srcClock_Hz / 8000000U; - best_scl = 8000000U / baudRate_Bps; - - if ((8000000U / best_scl - baudRate_Bps) > (baudRate_Bps - (8000000U / (best_scl + 1U)))) - { - best_scl = best_scl + 1U; - } - - /* - * Fallback to usual baudrate computation method, when: - * 1.Master SCL frequency does not fit in workaround range, - * 2.User's setting of baudRate_Bps is 400kHz while the clock frequency after divval is larger than 2MHz - */ - if ((best_scl > 18U) || ((best_scl < 4U)) || ((baudRate_Bps == 400000U) && (srcClock_Hz / best_div > 2000000U))) - { -#endif /*FSL_FEATURE_I2C_PREPCLKFRG_8MHZ*/ - - /* Calculate the minimal divider value to make sure the clock frequency after divval is not larger than 2MHz */ - /* This is required in RM in order to generate 400kHz baudrate */ - mindivider = ((srcClock_Hz * 10U) / 2000000U + 5U) / 10U; - /* If the scl value with current mindivider is smaller than 4, which is the minimal value register can achieve, - update mindivider */ - if ((srcClock_Hz / mindivider / baudRate_Bps) < 4U) - { - mindivider = srcClock_Hz / 4U / baudRate_Bps; - } - /* Calculate the ideal div and scl value*/ - best_err = 0U; - for (divider = mindivider; divider <= 0x10000U; divider++) - { - /* Calculte ideal scl value, round up the value */ - scl = ((srcClock_Hz * 10U) / (divider * baudRate_Bps) + 5U) / 10U; - - /* adjust it if it is out of range */ - scl = (scl > 18U) ? 18U : scl; - - /* calculate error */ - err = srcClock_Hz - (baudRate_Bps * scl * divider); - if ((err < best_err) || (best_err == 0U)) - { - best_div = divider; - best_scl = scl; - best_err = err; - } - - if ((err == 0U) || (scl <= 4U)) - { - /* either exact value was found - or scl is at its min (it would be even smaller in the next iteration for sure) */ - break; - } - } -#if defined(FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) && (FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) - } -#endif /*FSL_FEATURE_I2C_PREPCLKFRG_8MHZ*/ - base->CLKDIV = I2C_CLKDIV_DIVVAL(best_div - 1U); - if (best_scl % 2U == 0U) - { - base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl / 2U - 2U) | I2C_MSTTIME_MSTSCLHIGH(best_scl / 2U - 2U); - } - else - { - base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl / 2U - 1U) | I2C_MSTTIME_MSTSCLHIGH(best_scl / 2U - 2U); - } -} - -/*! - * brief Sets the I2C bus timeout value. - * - * If the SCL signal remains low or bus does not have event longer than the timeout value, kI2C_SclTimeoutFlag or - * kI2C_EventTimeoutFlag is set. This can indicete the bus is held by slave or any fault occurs to the I2C module. - * - * param base The I2C peripheral base address. - * param timeout_Ms Timeout value in millisecond. - * param srcClock_Hz I2C functional clock frequency in Hertz. - */ -void I2C_MasterSetTimeoutValue(I2C_Type *base, uint8_t timeout_Ms, uint32_t srcClock_Hz) -{ - assert((timeout_Ms != 0U) && (srcClock_Hz != 0U)); - - /* The low 4 bits of the timout reister TIMEOUT is hard-wired to be 1, so the the time out value is always 16 times - the I2C functional clock, we only need to calculate the high bits. */ - uint32_t timeoutValue = ((uint32_t)timeout_Ms * srcClock_Hz / 16UL / 100UL + 5UL) / 10UL; - if (timeoutValue > 0x1000UL) - { - timeoutValue = 0x1000UL; - } - timeoutValue = ((timeoutValue - 1UL) << 4UL) | 0xFUL; - base->TIMEOUT = timeoutValue; -} - -static status_t I2C_PendingStatusWait(I2C_Type *base) -{ - status_t result = kStatus_Success; - uint32_t status; - -#if I2C_RETRY_TIMES != 0U - uint32_t waitTimes = I2C_RETRY_TIMES; -#endif - - do - { - status = I2C_GetStatusFlags(base); - if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) - { - result = kStatus_I2C_EventTimeout; - } - if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) - { - result = kStatus_I2C_SclLowTimeout; - } -#if defined(FSL_FEATURE_I2C_TIMEOUT_RECOVERY) && FSL_FEATURE_I2C_TIMEOUT_RECOVERY - if (result != kStatus_Success) - { - I2C_MasterEnable(base, false); - I2C_MasterEnable(base, true); - break; - } -#endif -#if I2C_RETRY_TIMES != 0U - waitTimes--; - } while (((status & (uint32_t)kI2C_MasterPendingFlag) == 0U) && (waitTimes != 0U)); - - if (waitTimes == 0U) - { -#if defined(FSL_FEATURE_I2C_TIMEOUT_RECOVERY) && FSL_FEATURE_I2C_TIMEOUT_RECOVERY - I2C_MasterEnable(base, false); - I2C_MasterEnable(base, true); -#endif - return kStatus_I2C_Timeout; - } -#else - } while ((status & (uint32_t)kI2C_MasterPendingFlag) == 0U); -#endif - - if ((status & (uint32_t)kI2C_MasterArbitrationLostFlag) != 0U) - { - result = kStatus_I2C_ArbitrationLost; - } - - if ((status & (uint32_t)kI2C_MasterStartStopErrorFlag) != 0U) - { - result = kStatus_I2C_StartStopError; - } - - /* Clear controller state. */ - I2C_ClearStatusFlags( - base, (uint32_t)kI2C_MasterAllClearFlags | (uint32_t)kI2C_EventTimeoutFlag | (uint32_t)kI2C_SclTimeoutFlag); - - return result; -} - -/*! - * brief Sends a START on the I2C bus. - * - * This function is used to initiate a new master mode transfer by sending the START signal. - * The slave address is sent following the I2C START signal. - * - * param base I2C peripheral base pointer - * param address 7-bit slave device address. - * param direction Master transfer directions(transmit/receive). - * retval kStatus_Success Successfully send the start signal. - * retval kStatus_I2C_Busy Current bus is busy. - */ -status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) -{ - status_t result; - result = I2C_PendingStatusWait(base); - if (result != kStatus_Success) - { - return result; - } - - /* Write Address and RW bit to data register */ - base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1U); - /* Start the transfer */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - - return kStatus_Success; -} - -/*! - * brief Sends a STOP signal on the I2C bus. - * - * retval kStatus_Success Successfully send the stop signal. - * retval kStatus_I2C_Timeout Send stop signal failed, timeout. - */ -status_t I2C_MasterStop(I2C_Type *base) -{ - status_t result = I2C_PendingStatusWait(base); - if (result != kStatus_Success) - { - return result; - } - - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - return kStatus_Success; -} - -/*! - * brief Performs a polling send transfer on the I2C bus. - * - * Sends up to a txSize number of bytes to the previously addressed slave device. The slave may - * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this - * function returns #kStatus_I2C_Nak. - * - * param base The I2C peripheral base address. - * param txBuff The pointer to the data to be transferred. - * param txSize The length in bytes of the data to be transferred. - * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * retval kStatus_Success Data was sent successfully. - * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags) -{ - uint32_t master_state; - status_t err; - - const uint8_t *buf = (const uint8_t *)txBuff; - - assert(txBuff != NULL); - - err = kStatus_Success; - while (txSize != 0U) - { - err = I2C_PendingStatusWait(base); - - if (err != kStatus_Success) - { - return err; - } - - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - switch (master_state) - { - case I2C_STAT_MSTCODE_TXREADY: - /* ready to send next byte */ - base->MSTDAT = *buf++; - txSize--; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - break; - - case I2C_STAT_MSTCODE_NACKADR: - case I2C_STAT_MSTCODE_NACKDAT: - err = kStatus_I2C_Nak; - /* Issue nack signal when nacked by slave. */ - (void)I2C_MasterStop(base); - break; - - default: - /* unexpected state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - if (err != kStatus_Success) - { - return err; - } - } - - err = I2C_PendingStatusWait(base); - - if (err != kStatus_Success) - { - return err; - } - -#if !I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK - /* Check nack signal. If master is nacked by slave of the last byte, return kStatus_I2C_Nak. */ - if (((base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == (uint32_t)I2C_STAT_MSTCODE_NACKDAT) - { - (void)I2C_MasterStop(base); - return kStatus_I2C_Nak; - } -#endif - - if (0U == (flags & (uint32_t)kI2C_TransferNoStopFlag)) - { - /* Initiate stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - err = I2C_PendingStatusWait(base); - if (err != kStatus_Success) - { - return err; - } - } - - return kStatus_Success; -} - -/*! - * brief Performs a polling receive transfer on the I2C bus. - * - * param base The I2C peripheral base address. - * param rxBuff The pointer to the data to be transferred. - * param rxSize The length in bytes of the data to be transferred. - * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * retval kStatus_Success Data was received successfully. - * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags) -{ - uint32_t master_state; - status_t err; - - uint8_t *buf = (uint8_t *)(rxBuff); - - assert(rxBuff != NULL); - - err = kStatus_Success; - while (rxSize != 0U) - { - err = I2C_PendingStatusWait(base); - - if (err != kStatus_Success) - { - return err; - } - - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - switch (master_state) - { - case I2C_STAT_MSTCODE_RXREADY: - /* ready to send next byte */ - *(buf++) = (uint8_t)base->MSTDAT; - if (--rxSize != 0U) - { - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - } - else - { - if ((flags & (uint32_t)kI2C_TransferNoStopFlag) == 0U) - { - /* initiate NAK and stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - err = I2C_PendingStatusWait(base); - } - } - break; - - case I2C_STAT_MSTCODE_NACKADR: - case I2C_STAT_MSTCODE_NACKDAT: - /* slave nacked the last byte */ - err = kStatus_I2C_Nak; - break; - - default: - /* unexpected state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - if (err != kStatus_Success) - { - return err; - } - } - - return kStatus_Success; -} - -static status_t I2C_MasterCheckStartResponse(I2C_Type *base) -{ - /* Wait for start signal to be transmitted. */ - status_t result = I2C_PendingStatusWait(base); - - if (result != kStatus_Success) - { - return result; - } - - if (((base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == I2C_STAT_MSTCODE_NACKADR) - { - (void)I2C_MasterStop(base); - return kStatus_I2C_Addr_Nak; - } - return kStatus_Success; -} - -/*! - * brief Performs a master polling transfer on the I2C bus. - * - * note The API does not return until the transfer succeeds or fails due - * to arbitration lost or receiving a NAK. - * - * param base I2C peripheral base address. - * param xfer Pointer to the transfer structure. - * retval kStatus_Success Successfully complete the data transmission. - * retval kStatus_I2C_Busy Previous transmission still not finished. - * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - * retval kStataus_I2C_Addr_Nak Transfer error, receive NAK during addressing. - */ -status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) -{ - status_t result = kStatus_Success; - uint32_t subaddress; - uint8_t subaddrBuf[4]; - i2c_direction_t direction; - int i; - - assert(xfer != NULL); - - /* If start signal is requested, send start signal. */ - if (0U == (xfer->flags & (uint32_t)kI2C_TransferNoStartFlag)) - { - direction = (xfer->subaddressSize != 0U) ? kI2C_Write : xfer->direction; - result = I2C_MasterStart(base, xfer->slaveAddress, direction); - if (result == kStatus_Success) - { - result = I2C_MasterCheckStartResponse(base); - if (result != kStatus_Success) - { - return result; - } - if ((xfer->subaddressSize) != 0U) - { - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) - { - subaddrBuf[i] = (uint8_t)subaddress & 0xffU; - subaddress >>= 8; - } - /* Send subaddress. */ - result = - I2C_MasterWriteBlocking(base, subaddrBuf, xfer->subaddressSize, (uint32_t)kI2C_TransferNoStopFlag); - if (result != kStatus_Success) - { - if (result == kStatus_I2C_Nak) - { - (void)I2C_MasterStop(base); - return kStatus_I2C_Addr_Nak; - } - } - else if (xfer->direction == kI2C_Read) - { - result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction); - if (result == kStatus_Success) - { - result = I2C_MasterCheckStartResponse(base); - if (result != kStatus_Success) - { - return result; - } - } - } - else - { - /* Empty else block to avoid MISRA 14.1 violation. */ - } - } - } - } - - if (result == kStatus_Success) - { - if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0U)) - { - /* Transmit data. */ - result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); - } - else - { - if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0U)) - { - /* Receive Data. */ - result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags); - } - } - } - - if (result == kStatus_I2C_Nak) - { - (void)I2C_MasterStop(base); - } - - return result; -} - -/*! - * brief Creates a new handle for the I2C master non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. - * - * param base The I2C peripheral base address. - * param[out] handle Pointer to the I2C master driver handle. - * param callback User provided pointer to the asynchronous callback function. - * param userData User provided pointer to the application callback data. - */ -void I2C_MasterTransferCreateHandle(I2C_Type *base, - i2c_master_handle_t *handle, - i2c_master_transfer_callback_t callback, - void *userData) -{ - assert(handle != NULL); - - uint32_t instance; - i2c_to_flexcomm_t handler; - handler.i2c_master_handler = I2C_MasterTransferHandleIRQ; - - /* Clear out the handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Save base and instance. */ - handle->completionCallback = callback; - handle->userData = userData; - - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - (void)EnableIRQ(s_i2cIRQ[instance]); -} - -/*! - * brief Performs a non-blocking transaction on the I2C bus. - * - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - * param xfer The pointer to the transfer descriptor. - * retval kStatus_Success The transaction was started successfully. - * retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking - * transaction is already in progress. - */ -status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) -{ - status_t result; - - assert(handle != NULL); - assert(xfer != NULL); - assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); - - /* Return busy if another transaction is in progress. */ - if (handle->state != (uint8_t)kIdleState) - { - return kStatus_I2C_Busy; - } - - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - - /* Prepare transfer state machine. */ - result = I2C_InitTransferStateMachine(base, handle, xfer); - - /* Clear error flags. */ - I2C_ClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Enable I2C internal IRQ sources. */ - I2C_EnableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - - return result; -} - -/*! - * brief Returns number of bytes transferred so far. - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - * param[out] count Number of bytes transferred so far by the non-blocking transaction. - * retval kStatus_Success - * retval #kStatus_I2C_Busy - */ -status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state == (uint8_t)kIdleState) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* There is no necessity to disable interrupts as we read a single integer value */ - *count = handle->transferCount; - return kStatus_Success; -} - -/*! - * brief Terminates a non-blocking I2C master transmission early. - * - * note It is not safe to call this function from an IRQ handler that has a higher priority than the - * I2C peripheral's IRQ priority. - * - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - * retval kStatus_Success A transaction was successfully aborted. - * retval #kStatus_I2C_Timeout Timeout during polling for flags. - */ -status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) -{ - status_t result = kStatus_Success; - uint32_t master_state; - - if (handle->state != (uint8_t)kIdleState) - { - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - - /* Wait until module is ready */ - result = I2C_PendingStatusWait(base); - - if (result != kStatus_Success) - { - handle->state = (uint8_t)kIdleState; - return result; - } - - /* Get the state of the I2C module */ - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if (master_state != (uint32_t)I2C_STAT_MSTCODE_IDLE) - { - /* Send a stop command to finalize the transfer. */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - - /* Wait until the STOP is completed */ - result = I2C_PendingStatusWait(base); - - if (result != kStatus_Success) - { - handle->state = (uint8_t)kIdleState; - return result; - } - } - - /* Reset handle. */ - handle->state = (uint8_t)kIdleState; - handle->checkAddrNack = false; - } - return kStatus_Success; -} - -static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) -{ - struct _i2c_master_transfer *transfer; - - handle->transfer = *xfer; - transfer = &(handle->transfer); - - handle->transferCount = 0; - handle->remainingBytes = transfer->dataSize; - handle->buf = (uint8_t *)transfer->data; - handle->remainingSubaddr = 0; - handle->checkAddrNack = false; - - if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) - { - /* Start condition shall be ommited, switch directly to next phase */ - if (transfer->dataSize == 0U) - { - handle->state = (uint8_t)kStopState; - } - else if (handle->transfer.direction == kI2C_Write) - { - handle->state = (uint8_t)kTransmitDataState; - } - else if (handle->transfer.direction == kI2C_Read) - { - handle->state = (uint8_t)kReceiveDataBeginState; - } - else - { - return kStatus_I2C_InvalidParameter; - } - } - else - { - if (transfer->subaddressSize != 0U) - { - int i; - uint32_t subaddress; - - if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) - { - return kStatus_I2C_InvalidParameter; - } - - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) - { - handle->subaddrBuf[i] = (uint8_t)subaddress & 0xffU; - subaddress >>= 8; - } - handle->remainingSubaddr = transfer->subaddressSize; - } - handle->state = (uint8_t)kStartState; - handle->checkAddrNack = true; - } - - return kStatus_Success; -} - -static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) -{ - uint32_t status; - uint32_t master_state; - struct _i2c_master_transfer *transfer; - status_t err; - - transfer = &(handle->transfer); - bool ignoreNak = ((handle->state == (uint8_t)kWaitForCompletionState) && (handle->remainingBytes == 0U)) -#if I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK - /* If master is nacked by slave after the last byte during transmit, ignore the nack. */ - || ((handle->state == (uint8_t)kStopState) && (handle->remainingBytes == 0U)) -#endif - ; - - *isDone = false; - - status = I2C_GetStatusFlags(base); - - if ((status & I2C_STAT_MSTARBLOSS_MASK) != 0U) - { - I2C_ClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); - return kStatus_I2C_ArbitrationLost; - } - - if ((status & I2C_STAT_MSTSTSTPERR_MASK) != 0U) - { - I2C_ClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); - return kStatus_I2C_StartStopError; - } - - /* Event timeout happens when the time since last bus event has been longer than the time specified by TIMEOUT - register. eg: Start signal fails to generate, no error status is set and transfer hangs if glitch on bus happens - before, the timeout status can be used to avoid the transfer hangs indefinitely. */ - if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) - { - I2C_ClearStatusFlags(base, (uint32_t)kI2C_EventTimeoutFlag); - return kStatus_I2C_EventTimeout; - } - - /* SCL timeout happens when the slave is holding the SCL line low and the time has been longer than the time - specified by TIMEOUT register. */ - if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) - { - I2C_ClearStatusFlags(base, (uint32_t)kI2C_SclTimeoutFlag); - return kStatus_I2C_SclLowTimeout; - } - - if ((status & I2C_STAT_MSTPENDING_MASK) == 0U) - { - return kStatus_I2C_Busy; - } - - /* Get the hardware state of the I2C module */ - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - if (((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || - (master_state == (uint32_t)I2C_STAT_MSTCODE_NACKDAT)) && - (ignoreNak != true)) - { - /* Slave NACKed last byte, issue stop and return error */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = (uint8_t)kWaitForCompletionState; - /* If master is nacked during slave probe or during sending subaddress, return kStatus_I2C_ADDR_Nak. */ - if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (handle->checkAddrNack)) - { - return kStatus_I2C_Addr_Nak; - } - else /* Otherwise just return kStatus_I2C_Nak */ - { - return kStatus_I2C_Nak; - } - } - - err = kStatus_Success; - switch (handle->state) - { - case (uint8_t)kStartState: - if (handle->remainingSubaddr != 0U) - { - /* Subaddress takes precedence over the data transfer, direction is always "write" in this case */ - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1U; - handle->state = (uint8_t)kTransmitSubaddrState; - } - else if (transfer->direction == kI2C_Write) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = (handle->remainingBytes != 0U) ? (uint8_t)kTransmitDataState : (uint8_t)kStopState; - } - else - { - base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; - handle->state = (handle->remainingBytes != 0U) ? (uint8_t)kReceiveDataState : (uint8_t)kStopState; - } - /* Send start condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - break; - - case (uint8_t)kTransmitSubaddrState: - if (master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) - { - return kStatus_I2C_UnexpectedState; - } - /* Most significant subaddress byte comes first */ - base->MSTDAT = handle->subaddrBuf[handle->transfer.subaddressSize - handle->remainingSubaddr]; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - if (--(handle->remainingSubaddr) != 0U) - { - /* There are still subaddress bytes to be transmitted */ - break; - } - if (handle->remainingBytes != 0U) - { - /* There is data to be transferred, if there is write to read turnaround it is necessary to perform - * repeated start */ - handle->state = (transfer->direction == kI2C_Read) ? (uint8_t)kStartState : (uint8_t)kTransmitDataState; - } - else - { - /* No more data, schedule stop condition */ - handle->state = (uint8_t)kStopState; - } - break; - - case (uint8_t)kTransmitDataState: - handle->checkAddrNack = false; - if (master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) - { - return kStatus_I2C_UnexpectedState; - } - base->MSTDAT = *(handle->buf)++; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - if (--handle->remainingBytes == 0U) - { - /* No more data, schedule stop condition */ - handle->state = (uint8_t)kStopState; - } - handle->transferCount++; - break; - - case (uint8_t)kReceiveDataBeginState: - handle->checkAddrNack = false; - if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) - { - return kStatus_I2C_UnexpectedState; - } - (void)base->MSTDAT; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - handle->state = (uint8_t)kReceiveDataState; - break; - - case (uint8_t)kReceiveDataState: - handle->checkAddrNack = false; - if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) - { - return kStatus_I2C_UnexpectedState; - } - *(handle->buf)++ = (uint8_t)base->MSTDAT; - if (--handle->remainingBytes != 0U) - { - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - } - else - { - /* No more data expected, issue NACK and STOP right away */ - if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStopFlag)) - { - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - } - handle->state = (uint8_t)kWaitForCompletionState; - } - handle->transferCount++; - break; - - case (uint8_t)kStopState: - handle->checkAddrNack = false; - if ((transfer->flags & (uint32_t)kI2C_TransferNoStopFlag) != 0U) - { - /* Stop condition is omitted, we are done */ - *isDone = true; - handle->state = (uint8_t)kIdleState; - break; - } - /* Send stop condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = (uint8_t)kWaitForCompletionState; - break; - - case (uint8_t)kWaitForCompletionState: - *isDone = true; - handle->state = (uint8_t)kIdleState; - break; - - case (uint8_t)kIdleState: - default: - /* State machine shall not be invoked again once it enters the idle state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - return err; -} - -/*! - * brief Reusable routine to handle master interrupts. - * note This function does not need to be called unless you are reimplementing the - * nonblocking API's interrupt handler routines to add special functionality. - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - */ -void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle) -{ - bool isDone; - status_t result; - - /* Don't do anything if we don't have a valid handle. */ - if (NULL == handle) - { - return; - } - - result = I2C_RunTransferStateMachine(base, handle, &isDone); - - if ((result != kStatus_Success) || isDone) - { - /* Restore handle to idle state. */ - handle->state = (uint8_t)kIdleState; - - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - - /* Invoke callback. */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } -} - -static void I2C_SlaveInternalStateMachineReset(I2C_Type *base) -{ - I2C_SlaveEnable(base, false); /* clear SLVEN Slave enable bit */ -} - -static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal) -{ - uint32_t dataSetupTime_ns; - - switch ((uint8_t)(busSpeed)) - { - case (uint8_t)kI2C_SlaveStandardMode: - dataSetupTime_ns = 250U; - break; - - case (uint8_t)kI2C_SlaveFastMode: - dataSetupTime_ns = 100U; - break; - - case (uint8_t)kI2C_SlaveFastModePlus: - dataSetupTime_ns = 50U; - break; - - case (uint8_t)kI2C_SlaveHsMode: - dataSetupTime_ns = 10U; - break; - - default: - dataSetupTime_ns = 0U; - break; - } - - if (0U == dataSetupTime_ns) - { - return kStatus_InvalidArgument; - } - - /* divVal = (sourceClock_Hz / 1000000) * (dataSetupTime_ns / 1000) */ - *divVal = srcClock_Hz / 1000U; - *divVal = (*divVal) * dataSetupTime_ns; - *divVal = (*divVal) / 1000000U; - - if ((*divVal) > I2C_CLKDIV_DIVVAL_MASK) - { - *divVal = I2C_CLKDIV_DIVVAL_MASK; - } - - return kStatus_Success; -} - -static uint32_t I2C_SlavePollPending(I2C_Type *base) -{ - uint32_t stat; - -#if I2C_RETRY_TIMES != 0U - uint32_t waitTimes = I2C_RETRY_TIMES; -#endif - do - { - stat = base->STAT; -#if I2C_RETRY_TIMES != 0U - waitTimes--; - } while ((0U == (stat & I2C_STAT_SLVPENDING_MASK)) && (waitTimes != 0U)); - - if (waitTimes == 0U) - { - return (uint32_t)kStatus_I2C_Timeout; - } -#else - } while (0U == (stat & I2C_STAT_SLVPENDING_MASK)); -#endif - - return stat; -} - -static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event) -{ - uint32_t eventMask = handle->transfer.eventMask; - handle->transfer.event = event; - if (((handle->callback) != NULL) && ((eventMask & (uint32_t)event) != 0U)) - { - handle->callback(base, &handle->transfer, handle->userData); - - size_t txSize = handle->transfer.txSize; - size_t rxSize = handle->transfer.rxSize; - /* if after event callback we have data buffer (callback func has added new data), keep transfer busy */ - if (false == handle->isBusy) - { - if (((handle->transfer.txData != NULL) && (txSize != 0U)) || - ((handle->transfer.rxData != NULL) && (rxSize != 0U))) - { - handle->isBusy = true; - } - } - - /* Clear the transferred count now that we have a new buffer. */ - if ((event == kI2C_SlaveReceiveEvent) || (event == kI2C_SlaveTransmitEvent)) - { - handle->transfer.transferredCount = 0; - } - } -} - -static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle) -{ - uint8_t addressByte0; - size_t txSize; - size_t rxSize; - - addressByte0 = (uint8_t)base->SLVDAT; - - /* store the matched address */ - handle->transfer.receivedAddress = addressByte0; - - /* R/nW */ - if ((addressByte0 & 1U) != 0U) - { - txSize = handle->transfer.txSize; - /* if we have no data in this transfer, call callback to get new */ - if ((handle->transfer.txData == NULL) || (txSize == 0U)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); - } - - txSize = handle->transfer.txSize; - /* NACK if we have no data in this transfer. */ - if ((handle->transfer.txData == NULL) || (txSize == 0U)) - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - return false; - } - - /* master wants to read, so slave transmit is next state */ - handle->slaveFsm = kI2C_SlaveFsmTransmit; - } - else - { - rxSize = handle->transfer.rxSize; - /* if we have no receive buffer in this transfer, call callback to get new */ - if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); - } - - rxSize = handle->transfer.rxSize; - /* NACK if we have no data in this transfer */ - if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - return false; - } - - /* master wants write, so slave receive is next state */ - handle->slaveFsm = kI2C_SlaveFsmReceive; - } - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - return true; -} - -static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, - i2c_slave_handle_t *handle, - const void *txData, - size_t txSize, - void *rxData, - size_t rxSize, - uint32_t eventMask) -{ - assert(handle != NULL); - - status_t status; - status = kStatus_Success; - - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); - - /* Return busy if another transaction is in progress. */ - if (handle->isBusy) - { - status = kStatus_I2C_Busy; - } - - /* Save transfer into handle. */ - handle->transfer.txData = (const uint8_t *)txData; - handle->transfer.txSize = txSize; - handle->transfer.rxData = (uint8_t *)rxData; - handle->transfer.rxSize = rxSize; - handle->transfer.transferredCount = 0; - handle->transfer.eventMask = eventMask | (uint32_t)kI2C_SlaveTransmitEvent | (uint32_t)kI2C_SlaveReceiveEvent; - handle->isBusy = true; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* Clear w1c flags. */ - base->STAT |= 0u; - - /* Enable I2C internal IRQ sources. */ - I2C_EnableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); - - return status; -} - -/*! - * brief Starts accepting master read from slave requests. - * - * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * param base The I2C peripheral base address. - * param transfer Pointer to #i2c_slave_transfer_t structure. - * param txData Pointer to data to send to master. - * param txSize Size of txData in bytes. - * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * retval kStatus_Success Slave transfers were successfully started. - * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetSendBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, txData, txSize, NULL, 0u, eventMask); -} - -/*! - * brief Starts accepting master write to slave requests. - * - * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * param base The I2C peripheral base address. - * param transfer Pointer to #i2c_slave_transfer_t structure. - * param rxData Pointer to data to store data from master. - * param rxSize Size of rxData in bytes. - * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * retval kStatus_Success Slave transfers were successfully started. - * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetReceiveBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, NULL, 0u, rxData, rxSize, eventMask); -} - -/*! - * brief Configures Slave Address n register. - * - * This function writes new value to Slave Address register. - * - * param base The I2C peripheral base address. - * param addressRegister The module supports multiple address registers. The parameter determines which one shall be - * changed. - * param address The slave address to be stored to the address register for matching. - * param addressDisable Disable matching of the specified address register. - */ -void I2C_SlaveSetAddress(I2C_Type *base, - i2c_slave_address_register_t addressRegister, - uint8_t address, - bool addressDisable) -{ - base->SLVADR[addressRegister] = I2C_SLVADR_SLVADR(address) | I2C_SLVADR_SADISABLE(addressDisable); -} - -/*! - * brief Provides a default configuration for the I2C slave peripheral. - * - * This function provides the following default configuration for the I2C slave peripheral: - * code - * slaveConfig->enableSlave = true; - * slaveConfig->address0.disable = false; - * slaveConfig->address0.address = 0u; - * slaveConfig->address1.disable = true; - * slaveConfig->address2.disable = true; - * slaveConfig->address3.disable = true; - * slaveConfig->busSpeed = kI2C_SlaveStandardMode; - * endcode - * - * After calling this function, override any settings to customize the configuration, - * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the a - * address0.address member of the configuration structure with the desired slave address. - * - * param[out] slaveConfig User provided configuration structure that is set to default values. Refer to - * #i2c_slave_config_t. - */ -void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) -{ - assert(slaveConfig != NULL); - - i2c_slave_config_t mySlaveConfig = {0}; - - /* default config enables slave address 0 match to general I2C call address zero */ - mySlaveConfig.enableSlave = true; - mySlaveConfig.address1.addressDisable = true; - mySlaveConfig.address2.addressDisable = true; - mySlaveConfig.address3.addressDisable = true; - - *slaveConfig = mySlaveConfig; -} - -/*! - * brief Initializes the I2C slave peripheral. - * - * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user - * provided configuration. - * - * param base The I2C peripheral base address. - * param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults - * that you can override. - * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide - * enough - * data setup time for master when slave stretches the clock. - */ -status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz) -{ - status_t status; - uint32_t divVal = 0; - - /* configure data setup time used when slave stretches clock */ - status = I2C_SlaveDivVal(srcClock_Hz, slaveConfig->busSpeed, &divVal); - if (kStatus_Success != status) - { - return status; - } - - (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); - - /* I2C Clock Divider register */ - base->CLKDIV = divVal; - - /* set Slave address */ - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister0, slaveConfig->address0.address, - slaveConfig->address0.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister1, slaveConfig->address1.address, - slaveConfig->address1.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister2, slaveConfig->address2.address, - slaveConfig->address2.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister3, slaveConfig->address3.address, - slaveConfig->address3.addressDisable); - - /* set Slave address 0 qual */ - base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(slaveConfig->qualMode) | I2C_SLVQUAL0_SLVQUAL0(slaveConfig->qualAddress); - - /* set Slave enable */ - base->CFG = I2C_CFG_SLVEN(slaveConfig->enableSlave); - - return status; -} - -/*! - * brief Deinitializes the I2C slave peripheral. - * - * This function disables the I2C slave peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * param base The I2C peripheral base address. - */ -void I2C_SlaveDeinit(I2C_Type *base) -{ - I2C_SlaveEnable(base, false); -} - -/*! - * brief Performs a polling send transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * param base The I2C peripheral base address. - * param txBuff The pointer to the data to be transferred. - * param txSize The length in bytes of the data to be transferred. - * return kStatus_Success Data has been sent. - * return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). - */ -status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) -{ - const uint8_t *buf = txBuff; - uint32_t stat; - bool slaveAddress; - bool slaveTransmit; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - - /* Get slave machine state */ - slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); - slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_TX); - - /* in I2C_SlaveSend() it shall be either slaveAddress or slaveTransmit */ - if (!(slaveAddress || slaveTransmit)) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - if (slaveAddress) - { - /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - - /* send bytes up to txSize */ - while (txSize != 0U) - { - slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_TX); - - if (!slaveTransmit) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - /* Write 8 bits of data to the SLVDAT register */ - base->SLVDAT = I2C_SLVDAT_DATA(*buf); - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* advance counters and pointers for next data */ - buf++; - txSize--; - - if (txSize != 0U) - { - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - } - - return kStatus_Success; -} - -/*! - * brief Performs a polling receive transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * param base The I2C peripheral base address. - * param rxBuff The pointer to the data to be transferred. - * param rxSize The length in bytes of the data to be transferred. - * return kStatus_Success Data has been received. - * return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). - */ -status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) -{ - uint8_t *buf = rxBuff; - uint32_t stat; - bool slaveAddress; - bool slaveReceive; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - - /* Get slave machine state */ - slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); - slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_RX); - - /* in I2C_SlaveReceive() it shall be either slaveAddress or slaveReceive */ - if (!(slaveAddress || slaveReceive)) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - if (slaveAddress) - { - /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - - /* receive bytes up to rxSize */ - while (rxSize != 0U) - { - slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_RX); - - if (!slaveReceive) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - /* Read 8 bits of data from the SLVDAT register */ - *buf = (uint8_t)base->SLVDAT; - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* advance counters and pointers for next data */ - buf++; - rxSize--; - - if (rxSize != 0U) - { - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - } - - return kStatus_Success; -} - -/*! - * brief Creates a new handle for the I2C slave non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. - * - * param base The I2C peripheral base address. - * param[out] handle Pointer to the I2C slave driver handle. - * param callback User provided pointer to the asynchronous callback function. - * param userData User provided pointer to the application callback data. - */ -void I2C_SlaveTransferCreateHandle(I2C_Type *base, - i2c_slave_handle_t *handle, - i2c_slave_transfer_callback_t callback, - void *userData) -{ - assert(handle != NULL); - - uint32_t instance; - i2c_to_flexcomm_t handler; - handler.i2c_slave_handler = I2C_SlaveTransferHandleIRQ; - - /* Clear out the handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Save base and instance. */ - handle->callback = callback; - handle->userData = userData; - - /* initialize fsm */ - handle->slaveFsm = kI2C_SlaveFsmAddressMatch; - - /* store pointer to handle into transfer struct */ - handle->transfer.handle = handle; - - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); - (void)EnableIRQ(s_i2cIRQ[instance]); -} - -/*! - * brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. - * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. - * - * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * param base The I2C peripheral base address. - * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * retval kStatus_Success Slave transfers were successfully started. - * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, handle, NULL, 0u, NULL, 0u, eventMask); -} - -/*! - * brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. - * - * param base I2C base pointer. - * param handle pointer to i2c_slave_handle_t structure. - * param count Number of bytes transferred so far by the non-blocking transaction. - * retval kStatus_InvalidArgument count is Invalid. - * retval kStatus_Success Successfully return the count. - */ -status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (!handle->isBusy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* For an active transfer, just return the count from the handle. */ - *count = handle->transfer.transferredCount; - - return kStatus_Success; -} - -/*! - * brief Aborts the slave non-blocking transfers. - * note This API could be called at any time to stop slave for handling the bus events. - * param base The I2C peripheral base address. - * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * retval kStatus_Success - * retval #kStatus_I2C_Idle - */ -void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) -{ - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); - - /* Set the SLVEN bit to 0 in the CFG register. */ - I2C_SlaveEnable(base, false); - - handle->isBusy = false; - handle->transfer.txSize = 0U; - handle->transfer.rxSize = 0U; -} - -/*! - * brief Reusable routine to handle slave interrupts. - * note This function does not need to be called unless you are reimplementing the - * non blocking API's interrupt handler routines to add special functionality. - * param base The I2C peripheral base address. - * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - */ -void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle) -{ - uint32_t i2cStatus = base->STAT; - uint8_t tmpdata; - size_t txSize; - size_t rxSize; - - if ((i2cStatus & I2C_STAT_SLVDESEL_MASK) != 0U) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveDeselectedEvent); - I2C_SlaveClearStatusFlags(base, I2C_STAT_SLVDESEL_MASK); - } - - /* SLVPENDING flag is cleared by writing I2C_SLVCTL_SLVCONTINUE_MASK to SLVCTL register */ - if ((i2cStatus & I2C_STAT_SLVPENDING_MASK) != 0U) - { - bool slaveAddress = - (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); - - if (slaveAddress) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveAddressMatchEvent); - (void)I2C_SlaveAddressIRQ(base, handle); - } - else - { - switch (handle->slaveFsm) - { - case kI2C_SlaveFsmReceive: - { - bool slaveReceive = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == - (uint32_t)I2C_STAT_SLVST_RX); - - if (slaveReceive) - { - rxSize = handle->transfer.rxSize; - /* if we have no receive buffer in this transfer, call callback to get new */ - if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); - } - - rxSize = handle->transfer.rxSize; - /* receive a byte */ - if ((handle->transfer.rxData != NULL) && (rxSize != 0U)) - { - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - tmpdata = (uint8_t)base->SLVDAT; - *(handle->transfer.rxData) = tmpdata; - (handle->transfer.rxSize)--; - (handle->transfer.rxData)++; - (handle->transfer.transferredCount)++; - } - - rxSize = handle->transfer.rxSize; - txSize = handle->transfer.txSize; - /* is this last transaction for this transfer? allow next transaction */ - if ((0U == rxSize) && (0U == txSize)) - { - handle->isBusy = false; - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); - } - } - else - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - } - } - break; - - case kI2C_SlaveFsmTransmit: - { - bool slaveTransmit = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == - (uint32_t)I2C_STAT_SLVST_TX); - - if (slaveTransmit) - { - txSize = handle->transfer.txSize; - /* if we have no data in this transfer, call callback to get new */ - if ((handle->transfer.txData == NULL) || (txSize == 0U)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); - } - - txSize = handle->transfer.txSize; - /* transmit a byte */ - if ((handle->transfer.txData != NULL) && (txSize != 0U)) - { - base->SLVDAT = *(handle->transfer.txData); - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - (handle->transfer.txSize)--; - (handle->transfer.txData)++; - (handle->transfer.transferredCount)++; - } - - rxSize = handle->transfer.rxSize; - txSize = handle->transfer.txSize; - /* is this last transaction for this transfer? allow next transaction */ - if ((0U == rxSize) && (0U == txSize)) - { - handle->isBusy = false; - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); - } - } - else - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - } - } - break; - - default: - /* incorrect state, slv_abort()? */ - break; - } - } - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2c.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2c.h deleted file mode 100644 index b521a1ad756..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2c.h +++ /dev/null @@ -1,1148 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2C_H_ -#define _FSL_I2C_H_ - -#include -#include "fsl_device_registers.h" -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define I2C_CFG_MASK 0x1f - -/*! - * @addtogroup i2c_driver - * @{ - */ - -/*! @file */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2C driver version. */ -#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) -/*@}*/ - -/*! @brief Retry times for waiting flag. */ -#ifndef I2C_RETRY_TIMES -#define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ -#endif - -/*! @brief Whether to ignore the nack signal of the last byte during master transmit. */ -#ifndef I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK -#define I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK \ - 1U /* Define to one means master ignores the last byte's nack and considers the transfer successful. */ -#endif - -/* definitions for MSTCODE bits in I2C Status register STAT */ -#define I2C_STAT_MSTCODE_IDLE (0U) /*!< Master Idle State Code */ -#define I2C_STAT_MSTCODE_RXREADY (1U) /*!< Master Receive Ready State Code */ -#define I2C_STAT_MSTCODE_TXREADY (2U) /*!< Master Transmit Ready State Code */ -#define I2C_STAT_MSTCODE_NACKADR (3U) /*!< Master NACK by slave on address State Code */ -#define I2C_STAT_MSTCODE_NACKDAT (4U) /*!< Master NACK by slave on data State Code */ - -/* definitions for SLVSTATE bits in I2C Status register STAT */ -#define I2C_STAT_SLVST_ADDR (0) -#define I2C_STAT_SLVST_RX (1) -#define I2C_STAT_SLVST_TX (2) - -/*! @brief I2C status return codes. */ -enum -{ - kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 0), /*!< The master is already performing a transfer. */ - kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 1), /*!< The slave driver is idle. */ - kStatus_I2C_Nak = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 2), /*!< The slave device sent a NAK in response to a byte. */ - kStatus_I2C_InvalidParameter = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 3), /*!< Unable to proceed due to invalid parameter. */ - kStatus_I2C_BitError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 4), /*!< Transferred bit was not seen on the bus. */ - kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 5), /*!< Arbitration lost error. */ - kStatus_I2C_NoTransferInProgress = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 6), /*!< Attempt to abort a transfer when one is not in progress. */ - kStatus_I2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */ - kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8), /*!< Start and stop error. */ - kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9), /*!< Unexpected state. */ - kStatus_I2C_Timeout = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, - 10), /*!< Timeout when waiting for I2C master/slave pending status to set to continue transfer. */ - kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 11), /*!< NAK received for Address */ - kStatus_I2C_EventTimeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 12), /*!< Timeout waiting for bus event. */ - kStatus_I2C_SclLowTimeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 13), /*!< Timeout SCL signal remains low. */ -}; - -/*! @} */ - -/*! - * @addtogroup i2c_driver - * @{ - */ - -/*! - * @brief I2C status flags. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -enum _i2c_status_flags -{ - kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. bit 0 */ - kI2C_MasterArbitrationLostFlag = - I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus. bit 4*/ - kI2C_MasterStartStopErrorFlag = - I2C_STAT_MSTSTSTPERR_MASK, /*!< There was an error during start or stop phase of the transaction. bit 6 */ - kI2C_MasterIdleFlag = 1UL << 5U, /*!< The I2C master idle status. bit 5 */ - kI2C_MasterRxReadyFlag = 1UL << I2C_STAT_MSTSTATE_SHIFT, /*!< The I2C master rx ready status. bit 1 */ - kI2C_MasterTxReadyFlag = 1UL << (I2C_STAT_MSTSTATE_SHIFT + 1U), /*!< The I2C master tx ready status. bit 2 */ - kI2C_MasterAddrNackFlag = 1UL << 7U, /*!< The I2C master address nack status. bit 7 */ - kI2C_MasterDataNackFlag = 1UL << (I2C_STAT_MSTSTATE_SHIFT + 2U), /*!< The I2C master data nack status. bit 3 */ - kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. bit 8 */ - kI2C_SlaveNotStretching = I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 - = yes, 1 = no). bit 11 */ - kI2C_SlaveSelected = - I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. bit 14 */ - kI2C_SaveDeselected = I2C_STAT_SLVDESEL_MASK, /*!< Indicates that slave was previously deselected (deselect event - took place, w1c). bit 15 */ - kI2C_SlaveAddressedFlag = 1UL << 22U, /*!< One of the I2C slave's 4 addresses is matched. bit 22 */ - kI2C_SlaveReceiveFlag = 1UL << I2C_STAT_SLVSTATE_SHIFT, /*!< Slave receive data available. bit 9 */ - kI2C_SlaveTransmitFlag = 1UL << (I2C_STAT_SLVSTATE_SHIFT + 1U), /*!< Slave data can be transmitted. bit 10 */ - kI2C_SlaveAddress0MatchFlag = 1UL << 20U, /*!< Slave address0 match. bit 20 */ - kI2C_SlaveAddress1MatchFlag = 1UL << I2C_STAT_SLVIDX_SHIFT, /*!< Slave address1 match. bit 12 */ - kI2C_SlaveAddress2MatchFlag = 1UL << (I2C_STAT_SLVIDX_SHIFT + 1U), /*!< Slave address2 match. bit 13 */ - kI2C_SlaveAddress3MatchFlag = 1UL << 21U, /*!< Slave address3 match. bit 21 */ - kI2C_MonitorReadyFlag = I2C_STAT_MONRDY_MASK, /*!< The I2C monitor ready interrupt. bit 16 */ - kI2C_MonitorOverflowFlag = I2C_STAT_MONOV_MASK, /*!< The monitor data overrun interrupt. bit 17 */ - kI2C_MonitorActiveFlag = I2C_STAT_MONACTIVE_MASK, /*!< The monitor is active. bit 18 */ - kI2C_MonitorIdleFlag = I2C_STAT_MONIDLE_MASK, /*!< The monitor idle interrupt. bit 19 */ - kI2C_EventTimeoutFlag = I2C_STAT_EVENTTIMEOUT_MASK, /*!< The bus event timeout interrupt. bit 24 */ - kI2C_SclTimeoutFlag = I2C_STAT_SCLTIMEOUT_MASK, /*!< The SCL timeout interrupt. bit 25 */ - - /* All master flags that can be cleared by software */ - kI2C_MasterAllClearFlags = kI2C_MasterArbitrationLostFlag | kI2C_MasterStartStopErrorFlag, - /* All slave flags that can be cleared by software */ - kI2C_SlaveAllClearFlags = kI2C_SaveDeselected, - /* All common flags that can be cleared by software */ - kI2C_CommonAllClearFlags = - kI2C_MonitorOverflowFlag | kI2C_MonitorIdleFlag | kI2C_EventTimeoutFlag | kI2C_SclTimeoutFlag, -}; - -/*! - * @brief I2C interrupt enable. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -enum _i2c_interrupt_enable -{ - kI2C_MasterPendingInterruptEnable = - I2C_STAT_MSTPENDING_MASK, /*!< The I2C master communication pending interrupt. */ - kI2C_MasterArbitrationLostInterruptEnable = - I2C_STAT_MSTARBLOSS_MASK, /*!< The I2C master arbitration lost interrupt. */ - kI2C_MasterStartStopErrorInterruptEnable = - I2C_STAT_MSTSTSTPERR_MASK, /*!< The I2C master start/stop timing error interrupt. */ - kI2C_SlavePendingInterruptEnable = I2C_STAT_SLVPENDING_MASK, /*!< The I2C slave communication pending interrupt. */ - kI2C_SlaveNotStretchingInterruptEnable = - I2C_STAT_SLVNOTSTR_MASK, /*!< The I2C slave not streching interrupt, deep-sleep mode can be entered only when - this interrupt occurs. */ - kI2C_SlaveDeselectedInterruptEnable = I2C_STAT_SLVDESEL_MASK, /*!< The I2C slave deselection interrupt. */ - kI2C_MonitorReadyInterruptEnable = I2C_STAT_MONRDY_MASK, /*!< The I2C monitor ready interrupt. */ - kI2C_MonitorOverflowInterruptEnable = I2C_STAT_MONOV_MASK, /*!< The monitor data overrun interrupt. */ - kI2C_MonitorIdleInterruptEnable = I2C_STAT_MONIDLE_MASK, /*!< The monitor idle interrupt. */ - kI2C_EventTimeoutInterruptEnable = I2C_STAT_EVENTTIMEOUT_MASK, /*!< The bus event timeout interrupt. */ - kI2C_SclTimeoutInterruptEnable = I2C_STAT_SCLTIMEOUT_MASK, /*!< The SCL timeout interrupt. */ - - /* All master interrupt sources */ - kI2C_MasterAllInterruptEnable = kI2C_MasterPendingInterruptEnable | kI2C_MasterArbitrationLostInterruptEnable | - kI2C_MasterStartStopErrorInterruptEnable, - /* All slave interrupt sources */ - kI2C_SlaveAllInterruptEnable = - kI2C_SlavePendingInterruptEnable | kI2C_SlaveNotStretchingInterruptEnable | kI2C_SlaveDeselectedInterruptEnable, - /* All common interrupt sources */ - kI2C_CommonAllInterruptEnable = kI2C_MonitorReadyInterruptEnable | kI2C_MonitorOverflowInterruptEnable | - kI2C_MonitorIdleInterruptEnable | kI2C_EventTimeoutInterruptEnable | - kI2C_SclTimeoutInterruptEnable, -}; -/*! @} */ - -/*! - * @addtogroup i2c_master_driver - * @{ - */ - -/*! @brief Direction of master and slave transfers. */ -typedef enum _i2c_direction -{ - kI2C_Write = 0U, /*!< Master transmit. */ - kI2C_Read = 1U /*!< Master receive. */ -} i2c_direction_t; - -/*! - * @brief Structure with settings to initialize the I2C master module. - * - * This structure holds configuration settings for the I2C peripheral. To initialize this - * structure to reasonable defaults, call the I2C_MasterGetDefaultConfig() function and - * pass a pointer to your configuration structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _i2c_master_config -{ - bool enableMaster; /*!< Whether to enable master mode. */ - uint32_t baudRate_Bps; /*!< Desired baud rate in bits per second. */ - bool enableTimeout; /*!< Enable internal timeout function. */ - uint8_t timeout_Ms; /*!< Event timeout and SCL low timeout value. */ -} i2c_master_config_t; - -/* Forward declaration of the transfer descriptor and handle typedefs. */ -/*! @brief I2C master transfer typedef */ -typedef struct _i2c_master_transfer i2c_master_transfer_t; - -/*! @brief I2C master handle typedef */ -typedef struct _i2c_master_handle i2c_master_handle_t; - -/*! - * @brief Master completion callback function pointer type. - * - * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use - * in the call to I2C_MasterTransferCreateHandle(). - * - * @param base The I2C peripheral base address. - * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, - i2c_master_handle_t *handle, - status_t completionStatus, - void *userData); - -/*! - * @brief Transfer option flags. - * - * @note These enumerations are intended to be OR'd together to form a bit mask of options for - * the #_i2c_master_transfer::flags field. - */ -enum _i2c_master_transfer_flags -{ - kI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ - kI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ - kI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ - kI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ -}; - -/*! @brief States for the state machine used by transactional APIs. */ -enum _i2c_transfer_states -{ - kIdleState = 0, - kTransmitSubaddrState, - kTransmitDataState, - kReceiveDataBeginState, - kReceiveDataState, - kReceiveLastDataState, - kStartState, - kStopState, - kWaitForCompletionState -}; - -/*! - * @brief Non-blocking transfer descriptor structure. - * - * This structure is used to pass transaction parameters to the I2C_MasterTransferNonBlocking() API. - */ -struct _i2c_master_transfer -{ - uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i2c_master_transfer_flags for available - options. Set to 0 or #kI2C_TransferDefaultFlag for normal transfers. */ - uint8_t slaveAddress; /*!< The 7-bit slave address. */ - i2c_direction_t direction; /*!< Either #kI2C_Read or #kI2C_Write. */ - uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ - size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ - void *data; /*!< Pointer to data to transfer. */ - size_t dataSize; /*!< Number of bytes to transfer. */ -}; - -/*! - * @brief Driver handle for master non-blocking APIs. - * @note The contents of this structure are private and subject to change. - */ -struct _i2c_master_handle -{ - uint8_t state; /*!< Transfer state machine current state. */ - uint32_t transferCount; /*!< Indicates progress of the transfer */ - uint32_t remainingBytes; /*!< Remaining byte count in current state. */ - uint8_t *buf; /*!< Buffer pointer for current state. */ - uint32_t remainingSubaddr; - uint8_t subaddrBuf[4]; - bool checkAddrNack; /*!< Whether to check the nack signal is detected during addressing. */ - i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ - i2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ - void *userData; /*!< Application data passed to callback. */ -}; - -/*! @} */ - -/*! - * @addtogroup i2c_slave_driver - * @{ - */ -/*! @brief I2C slave address register. */ -typedef enum _i2c_slave_address_register -{ - kI2C_SlaveAddressRegister0 = 0U, /*!< Slave Address 0 register. */ - kI2C_SlaveAddressRegister1 = 1U, /*!< Slave Address 1 register. */ - kI2C_SlaveAddressRegister2 = 2U, /*!< Slave Address 2 register. */ - kI2C_SlaveAddressRegister3 = 3U, /*!< Slave Address 3 register. */ -} i2c_slave_address_register_t; - -/*! @brief Data structure with 7-bit Slave address and Slave address disable. */ -typedef struct _i2c_slave_address -{ - uint8_t address; /*!< 7-bit Slave address SLVADR. */ - bool addressDisable; /*!< Slave address disable SADISABLE. */ -} i2c_slave_address_t; - -/*! @brief I2C slave address match options. */ -typedef enum _i2c_slave_address_qual_mode -{ - kI2C_QualModeMask = 0U, /*!< The SLVQUAL0 field (qualAddress) is used as a logical mask for matching address0. */ - kI2C_QualModeExtend = - 1U, /*!< The SLVQUAL0 (qualAddress) field is used to extend address 0 matching in a range of addresses. */ -} i2c_slave_address_qual_mode_t; - -/*! @brief I2C slave bus speed options. */ -typedef enum _i2c_slave_bus_speed -{ - kI2C_SlaveStandardMode = 0U, - kI2C_SlaveFastMode = 1U, - kI2C_SlaveFastModePlus = 2U, - kI2C_SlaveHsMode = 3U, -} i2c_slave_bus_speed_t; - -/*! - * @brief Structure with settings to initialize the I2C slave module. - * - * This structure holds configuration settings for the I2C slave peripheral. To initialize this - * structure to reasonable defaults, call the I2C_SlaveGetDefaultConfig() function and - * pass a pointer to your configuration structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _i2c_slave_config -{ - i2c_slave_address_t address0; /*!< Slave's 7-bit address and disable. */ - i2c_slave_address_t address1; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_t address2; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_t address3; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_qual_mode_t qualMode; /*!< Qualify mode for slave address 0. */ - uint8_t qualAddress; /*!< Slave address qualifier for address 0. */ - i2c_slave_bus_speed_t - busSpeed; /*!< Slave bus speed mode. If the slave function stretches SCL to allow for software response, it must - provide sufficient data setup time to the master before releasing the stretched clock. - This is accomplished by inserting one clock time of CLKDIV at that point. - The #busSpeed value is used to configure CLKDIV - such that one clock time is greater than the tSU;DAT value noted - in the I2C bus specification for the I2C mode that is being used. - If the #busSpeed mode is unknown at compile time, use the longest data setup time - kI2C_SlaveStandardMode (250 ns) */ - bool enableSlave; /*!< Enable slave mode. */ -} i2c_slave_config_t; - -/*! - * @brief Set of events sent to the callback for non blocking slave transfers. - * - * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together - * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable. - * Then, when the slave callback is invoked, it is passed the current event through its @a transfer - * parameter. - * - * @note These enumerations are meant to be OR'd together to form a bit mask of events. - */ -typedef enum _i2c_slave_transfer_event -{ - kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ - kI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit - (slave-transmitter role). */ - kI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received - data (slave-receiver role). */ - kI2C_SlaveCompletionEvent = 0x20U, /*!< All data in the active transfer have been consumed. */ - kI2C_SlaveDeselectedEvent = - 0x40U, /*!< The slave function has become deselected (SLVSEL flag changing from 1 to 0. */ - - /*! Bit mask of all available events. */ - kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | - kI2C_SlaveCompletionEvent | kI2C_SlaveDeselectedEvent, -} i2c_slave_transfer_event_t; - -/*! @brief I2C slave handle typedef. */ -typedef struct _i2c_slave_handle i2c_slave_handle_t; - -/*! @brief I2C slave transfer structure */ -typedef struct _i2c_slave_transfer -{ - i2c_slave_handle_t *handle; /*!< Pointer to handle that contains this transfer. */ - i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ - uint8_t receivedAddress; /*!< Matching address send by master. 7-bits plus R/nW bit0 */ - uint32_t eventMask; /*!< Mask of enabled events. */ - uint8_t *rxData; /*!< Transfer buffer for receive data */ - const uint8_t *txData; /*!< Transfer buffer for transmit data */ - size_t txSize; /*!< Transfer size */ - size_t rxSize; /*!< Transfer size */ - size_t transferredCount; /*!< Number of bytes transferred during this transfer. */ - status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for - #kI2C_SlaveCompletionEvent. */ -} i2c_slave_transfer_t; - -/*! - * @brief Slave event callback function pointer type. - * - * This callback is used only for the slave non-blocking transfer API. To install a callback, - * use the I2C_SlaveSetCallback() function after you have created a handle. - * - * @param base Base address for the I2C instance on which the event occurred. - * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *userData); - -/*! - * @brief I2C slave software finite state machine states. - */ -typedef enum _i2c_slave_fsm -{ - kI2C_SlaveFsmAddressMatch = 0u, - kI2C_SlaveFsmReceive = 2u, - kI2C_SlaveFsmTransmit = 3u, -} i2c_slave_fsm_t; - -/*! - * @brief I2C slave handle structure. - * @note The contents of this structure are private and subject to change. - */ -struct _i2c_slave_handle -{ - volatile i2c_slave_transfer_t transfer; /*!< I2C slave transfer. */ - volatile bool isBusy; /*!< Whether transfer is busy. */ - volatile i2c_slave_fsm_t slaveFsm; /*!< slave transfer state machine. */ - i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ - void *userData; /*!< Callback parameter passed to callback. */ -}; - -/*! @brief Typedef for master interrupt handler. */ -typedef void (*flexcomm_i2c_master_irq_handler_t)(I2C_Type *base, i2c_master_handle_t *handle); - -/*! @brief Typedef for slave interrupt handler. */ -typedef void (*flexcomm_i2c_slave_irq_handler_t)(I2C_Type *base, i2c_slave_handle_t *handle); -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup i2c_master_driver - * @{ - */ - -/*! @name Initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the I2C master peripheral. - * - * This function provides the following default configuration for the I2C master peripheral: - * @code - * masterConfig->enableMaster = true; - * masterConfig->baudRate_Bps = 100000U; - * masterConfig->enableTimeout = false; - * @endcode - * - * After calling this function, you can override any settings in order to customize the configuration, - * prior to initializing the master driver with I2C_MasterInit(). - * - * @param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. - */ -void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); - -/*! - * @brief Initializes the I2C master peripheral. - * - * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user - * provided configuration. A software reset is performed prior to configuration. - * - * @param base The I2C peripheral base address. - * @param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of - * defaults - * that you can override. - * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, - * filter widths, and timeout periods. - */ -void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes the I2C master peripheral. - * - * This function disables the I2C master peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -void I2C_MasterDeinit(I2C_Type *base); - -/*! - * @brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * @param base The I2C peripheral base address. - * @return I2C instance number starting from 0. - */ -uint32_t I2C_GetInstance(I2C_Type *base); - -/*! - * @brief Performs a software reset. - * - * Restores the I2C master peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -static inline void I2C_MasterReset(I2C_Type *base) -{ -} - -/*! - * @brief Enables or disables the I2C module as master. - * - * @param base The I2C peripheral base address. - * @param enable Pass true to enable or false to disable the specified I2C as master. - */ -static inline void I2C_MasterEnable(I2C_Type *base, bool enable) -{ - if (enable) - { - base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK; - } - else - { - base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK; - } -} - -/*@}*/ - -/*! @name Status */ -/*@{*/ -/*! - * @brief Gets the I2C status flags. - * - * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit - * in the return value is set if the flag is asserted. - * - * @param base The I2C peripheral base address. - * @return State of the status flags: - * - 1: related status flag is set. - * - 0: related status flag is not set. - * @see @ref _i2c_status_flags. - */ -uint32_t I2C_GetStatusFlags(I2C_Type *base); - -/*! - * @brief Clears the I2C status flag state. - * - * Refer to kI2C_CommonAllClearStatusFlags, kI2C_MasterAllClearStatusFlags and kI2C_SlaveAllClearStatusFlags to see - * the clearable flags. Attempts to clear other flags has no effect. - * - * @param base The I2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of the members in - * kI2C_CommonAllClearStatusFlags, kI2C_MasterAllClearStatusFlags and kI2C_SlaveAllClearStatusFlags. You may pass - * the result of a previous call to I2C_GetStatusFlags(). - * @see #_i2c_status_flags, _i2c_master_status_flags and _i2c_slave_status_flags. - */ -static inline void I2C_ClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - /* Only deal with the clearable flags */ - statusMask &= - ((uint32_t)kI2C_CommonAllClearFlags | (uint32_t)kI2C_MasterAllClearFlags | (uint32_t)kI2C_SlaveAllClearFlags); - base->STAT = statusMask; -} - -/*! - * @brief Clears the I2C master status flag state. - * @deprecated Do not use this function. It has been superceded by @ref I2C_ClearStatusFlags - * The following status register flags can be cleared: - * - #kI2C_MasterArbitrationLostFlag - * - #kI2C_MasterStartStopErrorFlag - * - * Attempts to clear other flags has no effect. - * - * @param base The I2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * #_i2c_status_flags enumerators OR'd together. You may pass the result of a previous call to - * I2C_GetStatusFlags(). - * @see _i2c_status_flags. - */ -static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - /* Allow clearing just master status flags */ - base->STAT = statusMask & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); -} - -/*@}*/ - -/*! @name Interrupts */ -/*@{*/ - -/*! - * @brief Enables the I2C interrupt requests. - * - * @param base The I2C peripheral base address. - * @param interruptMask Bit mask of interrupts to enable. See #_i2c_interrupt_enable for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2C_EnableInterrupts(I2C_Type *base, uint32_t interruptMask) -{ - base->INTENSET = interruptMask; -} - -/*! - * @brief Disables the I2C interrupt requests. - * - * @param base The I2C peripheral base address. - * @param interruptMask Bit mask of interrupts to disable. See #_i2c_interrupt_enable for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2C_DisableInterrupts(I2C_Type *base, uint32_t interruptMask) -{ - base->INTENCLR = interruptMask; -} - -/*! - * @brief Returns the set of currently enabled I2C interrupt requests. - * - * @param base The I2C peripheral base address. - * @return A bitmask composed of #_i2c_interrupt_enable enumerators OR'd together to indicate the - * set of enabled interrupts. - */ -static inline uint32_t I2C_GetEnabledInterrupts(I2C_Type *base) -{ - return base->INTSTAT; -} - -/*@}*/ - -/*! @name Bus operations */ -/*@{*/ - -/*! - * @brief Sets the I2C bus frequency for master transactions. - * - * The I2C master is automatically disabled and re-enabled as necessary to configure the baud - * rate. Do not call this function during a transfer, or the transfer is aborted. - * - * @param base The I2C peripheral base address. - * @param srcClock_Hz I2C functional clock frequency in Hertz. - * @param baudRate_Bps Requested bus frequency in bits per second. - */ -void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Sets the I2C bus timeout value. - * - * If the SCL signal remains low or bus does not have event longer than the timeout value, kI2C_SclTimeoutFlag or - * kI2C_EventTimeoutFlag is set. This can indicete the bus is held by slave or any fault occurs to the I2C module. - * - * @param base The I2C peripheral base address. - * @param timeout_Ms Timeout value in millisecond. - * @param srcClock_Hz I2C functional clock frequency in Hertz. - */ -void I2C_MasterSetTimeoutValue(I2C_Type *base, uint8_t timeout_Ms, uint32_t srcClock_Hz); - -/*! - * @brief Returns whether the bus is idle. - * - * Requires the master mode to be enabled. - * - * @param base The I2C peripheral base address. - * @retval true Bus is busy. - * @retval false Bus is idle. - */ -static inline bool I2C_MasterGetBusIdleState(I2C_Type *base) -{ - /* True if MSTPENDING flag is set and MSTSTATE is zero == idle */ - return ((base->STAT & (I2C_STAT_MSTPENDING_MASK | I2C_STAT_MSTSTATE_MASK)) == I2C_STAT_MSTPENDING_MASK); -} - -/*! - * @brief Sends a START on the I2C bus. - * - * This function is used to initiate a new master mode transfer by sending the START signal. - * The slave address is sent following the I2C START signal. - * - * @param base I2C peripheral base pointer - * @param address 7-bit slave device address. - * @param direction Master transfer directions(transmit/receive). - * @retval kStatus_Success Successfully send the start signal. - * @retval kStatus_I2C_Busy Current bus is busy. - */ -status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); - -/*! - * @brief Sends a STOP signal on the I2C bus. - * - * @retval kStatus_Success Successfully send the stop signal. - * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. - */ -status_t I2C_MasterStop(I2C_Type *base); - -/*! - * @brief Sends a REPEATED START on the I2C bus. - * - * @param base I2C peripheral base pointer - * @param address 7-bit slave device address. - * @param direction Master transfer directions(transmit/receive). - * @retval kStatus_Success Successfully send the start signal. - * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. - */ -static inline status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) -{ - return I2C_MasterStart(base, address, direction); -} - -/*! - * @brief Performs a polling send transfer on the I2C bus. - * - * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may - * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this - * function returns #kStatus_I2C_Nak. - * - * @param base The I2C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * @retval kStatus_Success Data was sent successfully. - * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags); - -/*! - * @brief Performs a polling receive transfer on the I2C bus. - * - * @param base The I2C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * @retval kStatus_Success Data was received successfully. - * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags); - -/*! - * @brief Performs a master polling transfer on the I2C bus. - * - * @note The API does not return until the transfer succeeds or fails due - * to arbitration lost or receiving a NAK. - * - * @param base I2C peripheral base address. - * @param xfer Pointer to the transfer structure. - * @retval kStatus_Success Successfully complete the data transmission. - * @retval kStatus_I2C_Busy Previous transmission still not finished. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - * @retval kStataus_I2C_Addr_Nak Transfer error, receive NAK during addressing. - */ -status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); - -/*@}*/ - -/*! @name Non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the I2C master non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. - * - * @param base The I2C peripheral base address. - * @param[out] handle Pointer to the I2C master driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void I2C_MasterTransferCreateHandle(I2C_Type *base, - i2c_master_handle_t *handle, - i2c_master_transfer_callback_t callback, - void *userData); - -/*! - * @brief Performs a non-blocking transaction on the I2C bus. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @param xfer The pointer to the transfer descriptor. - * @retval kStatus_Success The transaction was started successfully. - * @retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking - * transaction is already in progress. - */ -status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Returns number of bytes transferred so far. - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @param[out] count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_Success - * @retval #kStatus_I2C_Busy - */ -status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); - -/*! - * @brief Terminates a non-blocking I2C master transmission early. - * - * @note It is not safe to call this function from an IRQ handler that has a higher priority than the - * I2C peripheral's IRQ priority. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @retval kStatus_Success A transaction was successfully aborted. - * @retval #kStatus_I2C_Timeout Timeout during polling for flags. - */ -status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); - -/*@}*/ - -/*! @name IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle master interrupts. - * @note This function does not need to be called unless you are reimplementing the - * nonblocking API's interrupt handler routines to add special functionality. - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - */ -void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle); - -/*@}*/ - -/*! @} */ /* end of i2c_master_driver */ - -/*! - * @addtogroup i2c_slave_driver - * @{ - */ - -/*! @name Slave initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the I2C slave peripheral. - * - * This function provides the following default configuration for the I2C slave peripheral: - * @code - * slaveConfig->enableSlave = true; - * slaveConfig->address0.disable = false; - * slaveConfig->address0.address = 0u; - * slaveConfig->address1.disable = true; - * slaveConfig->address2.disable = true; - * slaveConfig->address3.disable = true; - * slaveConfig->busSpeed = kI2C_SlaveStandardMode; - * @endcode - * - * After calling this function, override any settings to customize the configuration, - * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the @a - * address0.address member of the configuration structure with the desired slave address. - * - * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to - * #i2c_slave_config_t. - */ -void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); - -/*! - * @brief Initializes the I2C slave peripheral. - * - * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user - * provided configuration. - * - * @param base The I2C peripheral base address. - * @param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults - * that you can override. - * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide - * enough - * data setup time for master when slave stretches the clock. - */ -status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz); - -/*! - * @brief Configures Slave Address n register. - * - * This function writes new value to Slave Address register. - * - * @param base The I2C peripheral base address. - * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be - * changed. - * @param address The slave address to be stored to the address register for matching. - * @param addressDisable Disable matching of the specified address register. - */ -void I2C_SlaveSetAddress(I2C_Type *base, - i2c_slave_address_register_t addressRegister, - uint8_t address, - bool addressDisable); - -/*! - * @brief Deinitializes the I2C slave peripheral. - * - * This function disables the I2C slave peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -void I2C_SlaveDeinit(I2C_Type *base); - -/*! - * @brief Enables or disables the I2C module as slave. - * - * @param base The I2C peripheral base address. - * @param enable True to enable or flase to disable. - */ -static inline void I2C_SlaveEnable(I2C_Type *base, bool enable) -{ - /* Set or clear the SLVEN bit in the CFG register. */ - base->CFG = I2C_CFG_SLVEN(enable); -} - -/*@}*/ /* end of Slave initialization and deinitialization */ - -/*! @name Slave status */ -/*@{*/ - -/*! - * @brief Clears the I2C status flag state. - * - * The following status register flags can be cleared: - * - slave deselected flag - * - * Attempts to clear other flags has no effect. - * - * @param base The I2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * _i2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to - * I2C_SlaveGetStatusFlags(). - * @see _i2c_slave_flags. - */ -static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - /* Allow clearing just slave status flags */ - base->STAT = statusMask & I2C_STAT_SLVDESEL_MASK; -} - -/*@}*/ /* end of Slave status */ - -/*! @name Slave bus operations */ -/*@{*/ - -/*! - * @brief Performs a polling send transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * @param base The I2C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @return kStatus_Success Data has been sent. - * @return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). - */ -status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); - -/*! - * @brief Performs a polling receive transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * @param base The I2C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @return kStatus_Success Data has been received. - * @return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). - */ -status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); - -/*@}*/ /* end of Slave bus operations */ - -/*! @name Slave non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the I2C slave non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. - * - * @param base The I2C peripheral base address. - * @param[out] handle Pointer to the I2C slave driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void I2C_SlaveTransferCreateHandle(I2C_Type *base, - i2c_slave_handle_t *handle, - i2c_slave_transfer_callback_t callback, - void *userData); - -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. - * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); - -/*! - * @brief Starts accepting master read from slave requests. - * - * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param transfer Pointer to #i2c_slave_transfer_t structure. - * @param txData Pointer to data to send to master. - * @param txSize Size of txData in bytes. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetSendBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask); - -/*! - * @brief Starts accepting master write to slave requests. - * - * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param transfer Pointer to #i2c_slave_transfer_t structure. - * @param rxData Pointer to data to store data from master. - * @param rxSize Size of rxData in bytes. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetReceiveBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask); - -/*! - * @brief Returns the slave address sent by the I2C master. - * - * This function should only be called from the address match event callback #kI2C_SlaveAddressMatchEvent. - * - * @param base The I2C peripheral base address. - * @param transfer The I2C slave transfer. - * @return The 8-bit address matched by the I2C slave. Bit 0 contains the R/w direction bit, and - * the 7-bit slave address is in the upper 7 bits. - */ -static inline uint32_t I2C_SlaveGetReceivedAddress(I2C_Type *base, volatile i2c_slave_transfer_t *transfer) -{ - return transfer->receivedAddress; -} - -/*! - * @brief Aborts the slave non-blocking transfers. - * @note This API could be called at any time to stop slave for handling the bus events. - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * @retval kStatus_Success - * @retval #kStatus_I2C_Idle - */ -void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); - -/*! - * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_slave_handle_t structure. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_InvalidArgument count is Invalid. - * @retval kStatus_Success Successfully return the count. - */ -status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); - -/*@}*/ /* end of Slave non-blocking */ - -/*! @name Slave IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle slave interrupts. - * @note This function does not need to be called unless you are reimplementing the - * non blocking API's interrupt handler routines to add special functionality. - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - */ -void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle); - -/*@}*/ /* end of Slave IRQ handler */ - -/*! @} */ /* end of i2c_slave_driver */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2C_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2c_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2c_dma.c deleted file mode 100644 index 45d47e59073..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2c_dma.c +++ /dev/null @@ -1,652 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_i2c_dma.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c_dma" -#endif - -/*transfer = *xfer; - transfer = &(handle->transfer); - - handle->transferCount = 0U; - handle->remainingBytesDMA = 0U; - handle->buf = (uint8_t *)transfer->data; - handle->remainingSubaddr = 0U; - - if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) - { - handle->checkAddrNack = false; - /* Start condition shall not be ommited, switch directly to next phase */ - if (transfer->dataSize == 0U) - { - handle->state = (uint8_t)kStopState; - } - else if (handle->transfer.direction == kI2C_Write) - { - handle->state = (uint8_t)kTransmitDataState; - } - else if (handle->transfer.direction == kI2C_Read) - { - handle->state = (xfer->dataSize == 1U) ? (uint8_t)kReceiveLastDataState : (uint8_t)kReceiveDataState; - } - else - { - return kStatus_I2C_InvalidParameter; - } - } - else - { - if (transfer->subaddressSize != 0U) - { - int i; - uint32_t subaddress; - - if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) - { - return kStatus_I2C_InvalidParameter; - } - - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) - { - handle->subaddrBuf[i] = (uint8_t)subaddress & 0xffU; - subaddress >>= 8; - } - handle->remainingSubaddr = transfer->subaddressSize; - } - - handle->state = (uint8_t)kStartState; - handle->checkAddrNack = true; - } - - return kStatus_Success; -} - -static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - uint32_t transfer_size; - dma_transfer_config_t xferConfig; - uint32_t address; - address = (uint32_t)&base->MSTDAT; - - /* Update transfer count */ - int32_t count = handle->buf - (uint8_t *)handle->transfer.data; - assert(count >= 0); - handle->transferCount = (uint32_t)count; - - /* Check if there is anything to be transferred at all */ - if (handle->remainingBytesDMA == 0U) - { - /* No data to be transferrred, disable DMA */ - base->MSTCTL = 0; - return; - } - - /* Calculate transfer size */ - transfer_size = handle->remainingBytesDMA; - if (transfer_size > (uint32_t)I2C_MAX_DMA_TRANSFER_COUNT) - { - transfer_size = (uint32_t)I2C_MAX_DMA_TRANSFER_COUNT; - } - - switch (handle->transfer.direction) - { - case kI2C_Write: - DMA_PrepareTransfer(&xferConfig, handle->buf, (uint32_t *)address, sizeof(uint8_t), transfer_size, - kDMA_MemoryToPeripheral, NULL); - break; - - case kI2C_Read: - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, handle->buf, sizeof(uint8_t), transfer_size, - kDMA_PeripheralToMemory, NULL); - break; - - default: - /* This should never happen */ - assert(0); - break; - } - - (void)DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - DMA_StartTransfer(handle->dmaHandle); - - handle->remainingBytesDMA -= transfer_size; - handle->buf += transfer_size; - handle->checkAddrNack = false; -} - -static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone) -{ - uint32_t status; - uint32_t master_state; - struct _i2c_master_transfer *transfer; - dma_transfer_config_t xferConfig; - status_t err; - uint32_t start_flag = 0U; - uint32_t address; - address = (uint32_t)&base->MSTDAT; - - transfer = &(handle->transfer); - - *isDone = false; - - status = I2C_GetStatusFlags(base); - - if ((status & (uint32_t)I2C_STAT_MSTARBLOSS_MASK) != 0U) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_ArbitrationLost; - } - - if ((status & (uint32_t)I2C_STAT_MSTSTSTPERR_MASK) != 0U) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_StartStopError; - } - - /* Event timeout happens when the time since last bus event has been longer than the time specified by TIMEOUT - register. eg: Start signal fails to generate, no error status is set and transfer hangs if glitch on bus happens - before, the timeout status can be used to avoid the transfer hangs indefinitely. */ - if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) - { - I2C_ClearStatusFlags(base, (uint32_t)kI2C_EventTimeoutFlag); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_EventTimeout; - } - - /* SCL timeout happens when the slave is holding the SCL line low and the time has been longer than the time - specified by TIMEOUT register. */ - if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) - { - I2C_ClearStatusFlags(base, (uint32_t)kI2C_SclTimeoutFlag); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_SclLowTimeout; - } - - if ((status & (uint32_t)I2C_STAT_MSTPENDING_MASK) == 0U) - { - return kStatus_I2C_Busy; - } - - /* Get the state of the I2C module */ - master_state = (base->STAT & (uint32_t)I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (master_state == (uint32_t)I2C_STAT_MSTCODE_NACKDAT)) - { - /* Slave NACKed last byte, issue stop and return error */ - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = (uint8_t)kWaitForCompletionState; - if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (handle->checkAddrNack == true)) - { - return kStatus_I2C_Addr_Nak; - } - else - { - return kStatus_I2C_Nak; - } - } - - err = kStatus_Success; - - if (handle->state == (uint8_t)kStartState) - { - /* set start flag for later use */ - start_flag = I2C_MSTCTL_MSTSTART_MASK; - - if (handle->remainingSubaddr != 0U) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = (uint8_t)kTransmitSubaddrState; - } - else if (transfer->direction == kI2C_Write) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - if (transfer->dataSize == 0U) - { - /* No data to be transferred, initiate start and schedule stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - handle->state = (uint8_t)kStopState; - return err; - } - handle->state = (uint8_t)kTransmitDataState; - } - else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0U)) - { - base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; - if (transfer->dataSize == 1U) - { - /* The very last byte is always received by means of SW */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - handle->state = (uint8_t)kReceiveLastDataState; - return err; - } - handle->state = (uint8_t)kReceiveDataState; - } - else - { - handle->state = (uint8_t)kIdleState; - err = kStatus_I2C_UnexpectedState; - return err; - } - } - - switch (handle->state) - { - case (uint8_t)kTransmitSubaddrState: - if ((master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) && (0U == start_flag)) - { - return kStatus_I2C_UnexpectedState; - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - - /* Prepare and submit DMA transfer. */ - DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (uint32_t *)address, sizeof(uint8_t), - handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL); - (void)DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - DMA_StartTransfer(handle->dmaHandle); - handle->remainingSubaddr = 0; - if (transfer->dataSize != 0U) - { - /* There is data to be transferred, if there is write to read turnaround it is necessary to perform - * repeated start */ - handle->state = (transfer->direction == kI2C_Read) ? (uint8_t)kStartState : (uint8_t)kTransmitDataState; - } - else - { - /* No more data, schedule stop condition */ - handle->state = (uint8_t)kStopState; - } - break; - - case (uint8_t)kTransmitDataState: - if ((master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) && (0U == start_flag)) - { - return kStatus_I2C_UnexpectedState; - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - handle->remainingBytesDMA = handle->transfer.dataSize; - - I2C_RunDMATransfer(base, handle); - - /* Schedule stop condition */ - handle->state = (uint8_t)kStopState; - handle->checkAddrNack = false; - break; - - case (uint8_t)kReceiveDataState: - if ((master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) && (0U == start_flag)) - { - if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStartFlag)) - { - return kStatus_I2C_UnexpectedState; - } - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - handle->remainingBytesDMA = handle->transfer.dataSize - 1U; - - if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) - { - /* Read the master data register to avoid the data be read again */ - (void)base->MSTDAT; - } - I2C_RunDMATransfer(base, handle); - - /* Schedule reception of last data byte */ - handle->state = (uint8_t)kReceiveLastDataState; - handle->checkAddrNack = false; - break; - - case (uint8_t)kReceiveLastDataState: - if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) - { - return kStatus_I2C_UnexpectedState; - } - - ((uint8_t *)transfer->data)[transfer->dataSize - 1U] = (uint8_t)base->MSTDAT; - handle->transferCount++; - - /* No more data expected, issue NACK and STOP right away */ - if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStopFlag)) - { - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - } - handle->state = (uint8_t)kWaitForCompletionState; - break; - - case (uint8_t)kStopState: - if ((transfer->flags & (uint32_t)kI2C_TransferNoStopFlag) != 0U) - { - /* Stop condition is omitted, we are done */ - *isDone = true; - handle->state = (uint8_t)kIdleState; - break; - } - /* Send stop condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = (uint8_t)kWaitForCompletionState; - break; - - case (uint8_t)kWaitForCompletionState: - *isDone = true; - handle->state = (uint8_t)kIdleState; - break; - - case (uint8_t)kStartState: - case (uint8_t)kIdleState: - default: - /* State machine shall not be invoked again once it enters the idle state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - return err; -} - -static void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - bool isDone; - status_t result; - - /* Don't do anything if we don't have a valid handle. */ - if (NULL == handle) - { - return; - } - - result = I2C_RunTransferStateMachineDMA(base, handle, &isDone); - - if ((result != kStatus_Success) || isDone) - { - /* Restore handle to idle state. */ - handle->state = (uint8_t)kIdleState; - - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | - I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); - - /* Invoke callback. */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } -} - -static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) -{ - i2c_master_dma_private_handle_t *dmaPrivateHandle; - - /* Don't do anything if we don't have a valid handle. */ - if (NULL == handle) - { - return; - } - - dmaPrivateHandle = (i2c_master_dma_private_handle_t *)userData; - I2C_RunDMATransfer(dmaPrivateHandle->base, dmaPrivateHandle->handle); -} - -/*! - * brief Init the I2C handle which is used in transactional functions - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - * param callback pointer to user callback function - * param userData user param passed to the callback function - * param dmaHandle DMA handle pointer - */ -void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, - i2c_master_dma_handle_t *handle, - i2c_master_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *dmaHandle) -{ - assert(handle != NULL); - assert(dmaHandle != NULL); - - uint32_t instance; - i2c_dma_to_flexcomm_t handler; - handler.i2c_dma_master_handler = I2C_MasterTransferDMAHandleIRQ; - - /* Zero handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Set the user callback and userData. */ - handle->completionCallback = callback; - handle->userData = userData; - - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | - I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); - (void)EnableIRQ(s_i2cIRQ[instance]); - - /* Set the handle for DMA. */ - handle->dmaHandle = dmaHandle; - - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - DMA_SetCallback(dmaHandle, I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]); -} - -/*! - * brief Performs a master dma non-blocking transfer on the I2C bus - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - * param xfer pointer to transfer structure of i2c_master_transfer_t - * retval kStatus_Success Sucessully complete the data transmission. - * retval kStatus_I2C_Busy Previous transmission still not finished. - * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. - */ -status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer) -{ - status_t result; - - assert(handle != NULL); - assert(xfer != NULL); - assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); - - /* Return busy if another transaction is in progress. */ - if (handle->state != (uint8_t)kIdleState) - { - return kStatus_I2C_Busy; - } - - /* Prepare transfer state machine. */ - result = I2C_InitTransferStateMachineDMA(base, handle, xfer); - - /* Clear error flags. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Enable I2C internal IRQ sources */ - /* Enable arbitration lost interrupt, start/stop error interrupt and master pending interrupt. - The master pending flag is not set during dma transfer. */ - I2C_EnableInterrupts(base, I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | - I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); - - return result; -} - -/*! - * brief Get master transfer status during a dma non-blocking transfer - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - * param count Number of bytes transferred so far by the non-blocking transaction. - */ -status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state == (uint8_t)kIdleState) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* There is no necessity to disable interrupts as we read a single integer value */ - *count = handle->transferCount; - return kStatus_Success; -} - -/*! - * brief Abort a master dma non-blocking transfer in a early time - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - */ -void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - uint32_t status; - uint32_t master_state; - - if (handle->state != (uint8_t)kIdleState) - { - DMA_AbortTransfer(handle->dmaHandle); - - /* Disable DMA */ - base->MSTCTL = 0; - - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | - I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); - - /* Wait until module is ready */ - do - { - status = I2C_GetStatusFlags(base); - } while ((status & (uint8_t)I2C_STAT_MSTPENDING_MASK) == 0U); - - /* Clear controller state. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Get the state of the I2C module */ - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if (master_state != (uint32_t)I2C_STAT_MSTCODE_IDLE) - { - /* Send a stop command to finalize the transfer. */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - - /* Wait until module is ready */ - do - { - status = I2C_GetStatusFlags(base); - } while ((status & (uint32_t)I2C_STAT_MSTPENDING_MASK) == 0U); - - /* Clear controller state. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - } - - /* Reset the state to idle. */ - handle->state = (uint8_t)kIdleState; - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2c_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2c_dma.h deleted file mode 100644 index 07899f9c7c9..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2c_dma.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2C_DMA_H_ -#define _FSL_I2C_DMA_H_ - -#include "fsl_i2c.h" -#include "fsl_dma.h" - -/*! - * @addtogroup i2c_dma_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2C DMA driver version. */ -#define FSL_I2C_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) -/*@}*/ - -/*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */ -#define I2C_MAX_DMA_TRANSFER_COUNT 1024 - -/*! @brief I2C master dma handle typedef. */ -typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t; - -/*! @brief I2C master dma transfer callback typedef. */ -typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base, - i2c_master_dma_handle_t *handle, - status_t status, - void *userData); - -/*! @brief Typedef for master dma handler. */ -typedef void (*flexcomm_i2c_dma_master_irq_handler_t)(I2C_Type *base, i2c_master_dma_handle_t *handle); - -/*! @brief I2C master dma transfer structure. */ -struct _i2c_master_dma_handle -{ - uint8_t state; /*!< Transfer state machine current state. */ - uint32_t transferCount; /*!< Indicates progress of the transfer */ - uint32_t remainingBytesDMA; /*!< Remaining byte count to be transferred using DMA. */ - uint8_t *buf; /*!< Buffer pointer for current state. */ - uint32_t remainingSubaddr; - uint8_t subaddrBuf[4]; - bool checkAddrNack; /*!< Whether to check the nack signal is detected during addressing. */ - dma_handle_t *dmaHandle; /*!< The DMA handler used. */ - i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ - i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */ - void *userData; /*!< Callback parameter passed to callback function. */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus. */ - -/*! - * @name I2C Block DMA Transfer Operation - * @{ - */ - -/*! - * @brief Init the I2C handle which is used in transactional functions - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param callback pointer to user callback function - * @param userData user param passed to the callback function - * @param dmaHandle DMA handle pointer - */ -void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, - i2c_master_dma_handle_t *handle, - i2c_master_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *dmaHandle); - -/*! - * @brief Performs a master dma non-blocking transfer on the I2C bus - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param xfer pointer to transfer structure of i2c_master_transfer_t - * @retval kStatus_Success Sucessully complete the data transmission. - * @retval kStatus_I2C_Busy Previous transmission still not finished. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. - */ -status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Get master transfer status during a dma non-blocking transfer - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param count Number of bytes transferred so far by the non-blocking transaction. - */ -status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count); - -/*! - * @brief Abort a master dma non-blocking transfer in a early time - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - */ -void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle); - -/* @} */ -#if defined(__cplusplus) -} -#endif /*_cplusplus. */ -/*@}*/ -#endif /*_FSL_I2C_DMA_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2s.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2s.c deleted file mode 100644 index c13f2f4bcd4..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2s.c +++ /dev/null @@ -1,1198 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_i2s.h" -#include "fsl_flexcomm.h" -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s" -#endif - -/* TODO - absent in device header files, should be there */ -#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) -#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) -#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) -#define I2S_FIFOCFG_PACK48_MASK (0x8U) -#define I2S_FIFOCFG_PACK48_SHIFT (3U) -#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) -/*! @brief i2s empty tx fifo timeout value */ -#define I2S_FIFO_DEPTH (8U) -#define I2S_TX_ONE_SAMPLE_MAX_TIMEOUT (125U) /* 8K/8bit one sample need 125us*/ -#define I2S_TX_FIFO_EMPTY_TIMEOUT(count) (count) * I2S_TX_ONE_SAMPLE_MAX_TIMEOUT -/*! @brief _i2s_state I2S states. */ -enum -{ - kI2S_StateIdle = 0x0, /*!< Not performing transfer */ - kI2S_StateTx, /*!< Performing transmit */ - kI2S_StateTxWaitToWriteDummyData, /*!< Wait on FIFO in order to write final dummy data there */ - kI2S_StateTxWaitForEmptyFifo, /*!< Wait for FIFO to be flushed */ - kI2S_StateRx, /*!< Performing receive */ -}; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -static void I2S_Config(I2S_Type *base, const i2s_config_t *config); -static void I2S_TxEnable(I2S_Type *base, bool enable); -static void I2S_RxEnable(I2S_Type *base, bool enable); -static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map i2c instance number to base address. */ -static const uint32_t s_i2sBaseAddrs[] = I2S_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_i2sIRQ[] = I2S_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! - * @brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * @param base The I2S peripheral base address. - * @return I2S instance number starting from 0. - */ -static uint32_t I2S_GetInstance(I2S_Type *base) -{ - uint32_t i; - for (i = 0; i < (uint32_t)ARRAY_SIZE(s_i2sBaseAddrs); i++) - { - if ((uint32_t)base == s_i2sBaseAddrs[i]) - { - return i; - } - } - assert(false); - return 0; -} - -/*! - * brief Transmitter bit clock rate configurations. - * - * param base SAI base pointer. - * param sourceClockHz, bit clock source frequency. - * param sampleRate audio data sample rate. - * param bitWidth, audio data bitWidth. - * param channelNumbers, audio channel numbers. - */ -void I2S_SetBitClockRate( - I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers) -{ - uint32_t bitClockDivider = sourceClockHz / sampleRate / bitWidth / channelNumbers; - - assert(bitClockDivider >= 1U); - base->DIV = I2S_DIV_DIV(bitClockDivider - 1U); -} - -/*! - * brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S transmission using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_TxGetDefaultConfig(). - * - * note This API should be called at the beginning of the application to use - * the I2S driver. - * - * param base I2S base pointer. - * param config pointer to I2S configuration structure. - */ -void I2S_TxInit(I2S_Type *base, const i2s_config_t *config) -{ - uint32_t cfg = 0U; - uint32_t trig = 0U; - - (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_TX); - I2S_Config(base, config); - - /* Configure FIFO */ - - cfg |= I2S_FIFOCFG_ENABLETX(1U); /* enable TX FIFO */ - cfg |= I2S_FIFOCFG_EMPTYTX(1U); /* empty TX FIFO */ - cfg |= I2S_FIFOCFG_TXI2SE0(config->txEmptyZero); /* transmit zero when buffer becomes empty or last item */ - cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ - trig |= I2S_FIFOTRIG_TXLVLENA(1U); /* enable TX FIFO trigger */ - trig |= I2S_FIFOTRIG_TXLVL(config->watermark); /* set TX FIFO trigger level */ - - base->FIFOCFG = cfg; - base->FIFOTRIG = trig; -} - -/*! - * brief Initializes the FLEXCOMM peripheral for I2S receive functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S receive using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_RxGetDefaultConfig(). - * - * note This API should be called at the beginning of the application to use - * the I2S driver. - * - * param base I2S base pointer. - * param config pointer to I2S configuration structure. - */ -void I2S_RxInit(I2S_Type *base, const i2s_config_t *config) -{ - uint32_t cfg = 0U; - uint32_t trig = 0U; - - (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_RX); - I2S_Config(base, config); - - /* Configure FIFO */ - - cfg |= I2S_FIFOCFG_ENABLERX(1U); /* enable RX FIFO */ - cfg |= I2S_FIFOCFG_EMPTYRX(1U); /* empty RX FIFO */ - cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ - trig |= I2S_FIFOTRIG_RXLVLENA(1U); /* enable RX FIFO trigger */ - trig |= I2S_FIFOTRIG_RXLVL(config->watermark); /* set RX FIFO trigger level */ - - base->FIFOCFG = cfg; - base->FIFOTRIG = trig; -} - -/*! - * brief Flush the valid data in TX fifo. - * - * param base I2S base pointer. - * return kStatus_Fail empty TX fifo failed, kStatus_Success empty tx fifo success. - */ -status_t I2S_EmptyTxFifo(I2S_Type *base) -{ - uint32_t timeout = I2S_TX_FIFO_EMPTY_TIMEOUT(I2S_FIFO_DEPTH); - - while (((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) && (timeout != 0U)) - { - timeout -= I2S_TX_ONE_SAMPLE_MAX_TIMEOUT; - SDK_DelayAtLeastUs(I2S_TX_ONE_SAMPLE_MAX_TIMEOUT, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - } - - /* The last piece of valid data can be still being transmitted from I2S at this moment */ - timeout = I2S_TX_ONE_SAMPLE_MAX_TIMEOUT; - /* Write additional data to FIFO */ - base->FIFOWR = 0U; - while (((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) && (timeout != 0U)) - { - timeout -= I2S_TX_ONE_SAMPLE_MAX_TIMEOUT; - SDK_DelayAtLeastUs(I2S_TX_ONE_SAMPLE_MAX_TIMEOUT, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - } - - return ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) ? kStatus_Fail : kStatus_Success; -} - -/*! - * brief Sets the I2S Tx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_TxInit(). - * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified - * before calling I2S_TxInit(). - * Example: - code - i2s_config_t config; - I2S_TxGetDefaultConfig(&config); - endcode - * - * Default values: - * code - * config->masterSlave = kI2S_MasterSlaveNormalMaster; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = true; - * config->pack48 = false; - * endcode - * - * param config pointer to I2S configuration structure. - */ -void I2S_TxGetDefaultConfig(i2s_config_t *config) -{ - config->masterSlave = kI2S_MasterSlaveNormalMaster; - config->mode = kI2S_ModeI2sClassic; - config->rightLow = false; - config->leftJust = false; -#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) - config->pdmData = false; -#endif - config->sckPol = false; - config->wsPol = false; - config->divider = 1U; - config->oneChannel = false; - config->dataLength = 16U; - config->frameLength = 32U; - config->position = 0U; - config->watermark = 4U; - config->txEmptyZero = true; - config->pack48 = false; -} - -/*! - * brief Sets the I2S Rx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_RxInit(). - * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified - * before calling I2S_RxInit(). - * Example: - code - i2s_config_t config; - I2S_RxGetDefaultConfig(&config); - endcode - * - * Default values: - * code - * config->masterSlave = kI2S_MasterSlaveNormalSlave; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = false; - * config->pack48 = false; - * endcode - * - * param config pointer to I2S configuration structure. - */ -void I2S_RxGetDefaultConfig(i2s_config_t *config) -{ - config->masterSlave = kI2S_MasterSlaveNormalSlave; - config->mode = kI2S_ModeI2sClassic; - config->rightLow = false; - config->leftJust = false; -#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) - config->pdmData = false; -#endif - config->sckPol = false; - config->wsPol = false; - config->divider = 1U; - config->oneChannel = false; - config->dataLength = 16U; - config->frameLength = 32U; - config->position = 0U; - config->watermark = 4U; - config->txEmptyZero = false; - config->pack48 = false; -} - -static void I2S_Config(I2S_Type *base, const i2s_config_t *config) -{ - assert(config != NULL); - - uint32_t cfg1 = 0U; - uint32_t cfg2 = 0U; - - /* set master/slave configuration */ - cfg1 |= I2S_CFG1_MSTSLVCFG(config->masterSlave); - - /* set I2S mode */ - cfg1 |= I2S_CFG1_MODE(config->mode); - - /* set right low (channel swap) */ - cfg1 |= I2S_CFG1_RIGHTLOW(config->rightLow); - - /* set data justification */ - cfg1 |= I2S_CFG1_LEFTJUST(config->leftJust); - -#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) - if (FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn((FLEXCOMM_Type *)(uint32_t)base) > 0) - { - /* set source to PDM dmic */ - cfg1 |= I2S_CFG1_PDMDATA(config->pdmData); - } -#endif - - /* set SCLK polarity */ - cfg1 |= I2S_CFG1_SCK_POL(config->sckPol); - - /* set WS polarity */ - cfg1 |= I2S_CFG1_WS_POL(config->wsPol); - - /* set mono mode */ - cfg1 |= I2S_CFG1_ONECHANNEL(config->oneChannel); - - /* set data length */ - cfg1 |= I2S_CFG1_DATALEN(config->dataLength - 1UL); - - /* set frame length */ - cfg2 |= I2S_CFG2_FRAMELEN(config->frameLength - 1UL); - - /* set data position of this channel pair within the frame */ - cfg2 |= I2S_CFG2_POSITION(config->position); - - /* write to registers */ - base->CFG1 = cfg1; - base->CFG2 = cfg2; - - /* set the clock divider */ - base->DIV = I2S_DIV_DIV(config->divider - 1UL); -} - -/*! - * brief De-initializes the I2S peripheral. - * - * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit - * or I2S_RxInit is called to enable the clock. - * - * param base I2S base pointer. - */ -void I2S_Deinit(I2S_Type *base) -{ - /* TODO gate FLEXCOMM clock via FLEXCOMM driver */ -} - -static void I2S_TxEnable(I2S_Type *base, bool enable) -{ - if (enable) - { - I2S_Enable(base); - I2S_EnableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); - } - else - { - I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); - I2S_Disable(base); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - } -} - -static void I2S_RxEnable(I2S_Type *base, bool enable) -{ - if (enable) - { - I2S_Enable(base); - I2S_EnableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); - } - else - { - I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); - I2S_Disable(base); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - } -} - -static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer) -{ - assert(transfer->data != NULL); - - if (transfer->data == NULL) - { - return kStatus_InvalidArgument; - } - - assert(transfer->dataSize > 0U); - if (transfer->dataSize <= 0U) - { - return kStatus_InvalidArgument; - } - - if (handle->dataLength == 4U) - { - /* No alignment and data length requirements */ - } - else if ((handle->dataLength >= 5U) && (handle->dataLength <= 8U)) - { - assert((((uint32_t)transfer->data) % 2U) == 0U); - if ((((uint32_t)transfer->data) % 2U) != 0U) - { - /* Data not 2-bytes aligned */ - return kStatus_InvalidArgument; - } - - assert((transfer->dataSize % 2U) == 0U); - if ((transfer->dataSize % 2U) != 0U) - { - /* Data not in pairs of left/right channel bytes */ - return kStatus_InvalidArgument; - } - } - else if ((handle->dataLength >= 9U) && (handle->dataLength <= 16U)) - { - assert((((uint32_t)transfer->data) % 4U) == 0U); - if ((((uint32_t)transfer->data) % 4U) != 0U) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - - assert((transfer->dataSize % 4U) == 0U); - if ((transfer->dataSize % 4U) != 0U) - { - /* Data lenght not multiply of 4 */ - return kStatus_InvalidArgument; - } - } - else if ((handle->dataLength >= 17U) && (handle->dataLength <= 24U)) - { - assert((transfer->dataSize % 6U) == 0U); - if ((transfer->dataSize % 6U) != 0U) - { - /* Data lenght not multiply of 6 */ - return kStatus_InvalidArgument; - } - - assert(!((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U))); - if ((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U)) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - } - else /* if (handle->dataLength >= 25U) */ - { - assert((((uint32_t)transfer->data) % 4U) == 0U); - if ((((uint32_t)transfer->data) % 4U) != 0U) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - - if (handle->oneChannel) - { - assert((transfer->dataSize % 4U) == 0U); - if ((transfer->dataSize % 4U) != 0U) - { - /* Data lenght not multiply of 4 */ - return kStatus_InvalidArgument; - } - } - else - { - assert((transfer->dataSize % 8U) == 0U); - if ((transfer->dataSize % 8U) != 0U) - { - /* Data lenght not multiply of 8 */ - return kStatus_InvalidArgument; - } - } - } - - return kStatus_Success; -} - -#if (defined(FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) && FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) -/*! - * brief Enables I2S secondary channel. - * - * param base I2S base pointer. - * param channel seondary channel channel number, reference _i2s_secondary_channel. - * param oneChannel true is treated as single channel, functionality left channel for this pair. - * param position define the location within the frame of the data, should not bigger than 0x1FFU. - */ -void I2S_EnableSecondaryChannel(I2S_Type *base, uint32_t channel, bool oneChannel, uint32_t position) -{ - assert(channel <= (uint32_t)kI2S_SecondaryChannel3); -#if defined FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn - assert(FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn((FLEXCOMM_Type *)(uint32_t)base) == 1); -#endif - - uint32_t pcfg1 = base->SECCHANNEL[channel].PCFG1; - uint32_t pcfg2 = base->SECCHANNEL[channel].PCFG2; - - pcfg1 &= ~I2S_CFG1_ONECHANNEL_MASK; - pcfg1 |= I2S_CFG1_MAINENABLE_MASK | I2S_CFG1_ONECHANNEL(oneChannel); - - pcfg2 &= ~I2S_CFG2_POSITION_MASK; - pcfg2 |= I2S_CFG2_POSITION(position); - - base->SECCHANNEL[channel].PCFG1 = pcfg1; - base->SECCHANNEL[channel].PCFG2 = pcfg2; -} -#endif - -/*! - * brief Initializes handle for transfer of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) -{ - assert(handle != NULL); - - uint32_t instance; - - /* Clear out the handle */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2S_GetInstance(base); - - /* Save callback and user data */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Remember some items set previously by configuration */ - handle->watermark = (uint8_t)((base->FIFOTRIG & I2S_FIFOTRIG_TXLVL_MASK) >> I2S_FIFOTRIG_TXLVL_SHIFT); - handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT) != 0U ? true : false; - handle->dataLength = (uint8_t)((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; - handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT) != 0u ? true : false; - - handle->useFifo48H = false; - - /* Register IRQ handling */ - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_TxHandleIRQ, handle); - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); - (void)EnableIRQ(s_i2sIRQ[instance]); -} - -/*! - * brief Begins or queue sending of the given data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) -{ - assert(handle != NULL); - - status_t result; - - if (handle == NULL) - { - return kStatus_InvalidArgument; - } - - result = I2S_ValidateBuffer(handle, &transfer); - if (result != kStatus_Success) - { - return result; - } - - if (handle->i2sQueue[handle->queueUser].dataSize != 0UL) - { - /* Previously prepared buffers not processed yet */ - return kStatus_I2S_Busy; - } - - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_TXLVL_MASK)) | I2S_FIFOTRIG_TXLVL(handle->watermark); - I2S_TxEnable(base, true); - - return kStatus_Success; -} - -/*! - * brief Aborts sending of data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle) -{ - assert(handle != NULL); - - /* Disable I2S operation and interrupts */ - I2S_TxEnable(base, false); - - /* Reset state */ - handle->state = (uint32_t)kI2S_StateIdle; - - /* Clear transfer queue */ - (void)memset((void *)&handle->i2sQueue, 0, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); - handle->queueDriver = 0U; - handle->queueUser = 0U; -} - -/*! - * brief Initializes handle for reception of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) -{ - assert(handle != NULL); - - uint32_t instance; - - /* Clear out the handle */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2S_GetInstance(base); - - /* Save callback and user data */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Remember some items set previously by configuration */ - handle->watermark = (uint8_t)((base->FIFOTRIG & I2S_FIFOTRIG_RXLVL_MASK) >> I2S_FIFOTRIG_RXLVL_SHIFT); - handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT) != 0UL ? true : false; - handle->dataLength = (uint8_t)((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; - handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT) != 0UL ? true : false; - - handle->useFifo48H = false; - - /* Register IRQ handling */ - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_RxHandleIRQ, handle); - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); - - (void)EnableIRQ(s_i2sIRQ[instance]); -} - -/*! - * brief Begins or queue reception of data into given buffer. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. - */ -status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) -{ - assert(handle != NULL); - - status_t result; - - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - result = I2S_ValidateBuffer(handle, &transfer); - if (result != kStatus_Success) - { - return result; - } - - if (handle->i2sQueue[handle->queueUser].dataSize != 0UL) - { - /* Previously prepared buffers not processed yet */ - return kStatus_I2S_Busy; - } - - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_RXLVL_MASK)) | I2S_FIFOTRIG_RXLVL(handle->watermark); - I2S_RxEnable(base, true); - - return kStatus_Success; -} - -/*! - * brief Aborts receiving of data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle) -{ - assert(handle != NULL); - - /* Disable I2S operation and interrupts */ - I2S_RxEnable(base, false); - - /* Reset state */ - handle->state = (uint32_t)kI2S_StateIdle; - - /* Clear transfer queue */ - (void)memset((void *)&handle->i2sQueue, 0, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); - handle->queueDriver = 0U; - handle->queueUser = 0U; -} - -/*! - * brief Returns number of bytes transferred so far. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param[out] count number of bytes transferred so far by the non-blocking transaction. - * - * retval kStatus_Success - * retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - assert(count != NULL); - - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - if (handle->state == (uint32_t)kI2S_StateIdle) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->transferCount; - - return kStatus_Success; -} - -/*! - * brief Returns number of buffer underruns or overruns. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param[out] count number of transmit errors encountered so far by the non-blocking transaction. - * - * retval kStatus_Success - * retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - assert(count != NULL); - - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - if (handle->state == (uint32_t)kI2S_StateIdle) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->errorCount; - - return kStatus_Success; -} - -/*! - * brief Invoked from interrupt handler when transmit FIFO level decreases. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) -{ - uint32_t intstat = base->FIFOINTSTAT; - uint32_t data; - uint8_t queueDriverIndex = handle->queueDriver; - uint32_t dataAddr = (uint32_t)handle->i2sQueue[queueDriverIndex].data; - uint32_t dataSize = handle->i2sQueue[queueDriverIndex].dataSize; - - if ((intstat & I2S_FIFOINTSTAT_TXERR_MASK) != 0UL) - { - handle->errorCount++; - - /* Clear TX error interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_TXERR(1U); - } - - if ((intstat & I2S_FIFOINTSTAT_TXLVL_MASK) != 0UL) - { - if ((handle->state != (uint32_t)kI2S_StateTx) && (dataSize != 0U) && (dataAddr != 0U)) - { - handle->state = (uint32_t)kI2S_StateTx; - } - - if (handle->state == (uint32_t)kI2S_StateTx) - { - /* Send data */ - - while (((base->FIFOSTAT & I2S_FIFOSTAT_TXNOTFULL_MASK) != 0UL) && (dataSize > 0U)) - { - /* Write output data */ - if (handle->dataLength == 4U) - { - data = *((uint8_t *)dataAddr); - base->FIFOWR = ((data & 0xF0U) << 12U) | (data & 0xFU); - dataAddr++; - handle->transferCount++; - dataSize--; - } - else if (handle->dataLength <= 8U) - { - data = *((volatile uint16_t *)dataAddr); - if (handle->oneChannel) - { - base->FIFOWR = (data & 0xFFU); - dataAddr += sizeof(uint8_t); - handle->transferCount += sizeof(uint8_t); - dataSize -= sizeof(uint8_t); - } - else - { - base->FIFOWR = ((data & 0xFF00U) << 8U) | (data & 0xFFU); - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - } - else if (handle->dataLength <= 16U) - { - data = *((volatile uint32_t *)(dataAddr)); - if (handle->oneChannel) - { - base->FIFOWR = data & 0xFFFFU; - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - else - { - base->FIFOWR = data; - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - } - else if (handle->dataLength <= 24U) - { - if (handle->pack48) - { - if (handle->useFifo48H) - { - base->FIFOWR48H = *((volatile uint16_t *)(dataAddr)); - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - handle->useFifo48H = false; - } - else - { - base->FIFOWR = *((volatile uint32_t *)(dataAddr)); - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - handle->useFifo48H = true; - } - } - else - { - data = (uint32_t)(*(uint8_t *)(dataAddr++)); - data |= ((uint32_t)(*(uint8_t *)(dataAddr++))) << 8U; - data |= ((uint32_t)(*(uint8_t *)(dataAddr++))) << 16U; - if ((handle->useFifo48H) && (handle->oneChannel == false)) - { - base->FIFOWR48H = data; - handle->useFifo48H = false; - } - else - { - base->FIFOWR = data; - handle->useFifo48H = true; - } - handle->transferCount += 3U; - dataSize -= 3U; - } - } - else /* if (handle->dataLength <= 32U) */ - { - base->FIFOWR = *((volatile uint32_t *)(dataAddr)); - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - - if (dataSize == 0U) - { - handle->i2sQueue[queueDriverIndex].dataSize = 0U; - /* Actual data buffer sent out, switch to a next one */ - handle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; - - /* Notify user */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); - } - - /* Check if the next buffer contains anything to send */ - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* Everything has been written to FIFO */ - handle->state = kI2S_StateTxWaitToWriteDummyData; - break; - } - } - else - { - handle->i2sQueue[queueDriverIndex].dataSize = dataSize; - handle->i2sQueue[queueDriverIndex].data = (uint8_t *)dataAddr; - } - } - } - else if (handle->state == (uint32_t)kI2S_StateTxWaitToWriteDummyData) - { - /* Write dummy data */ - if ((handle->dataLength > 16U) && (handle->dataLength < 25U)) - { - if (handle->useFifo48H) - { - base->FIFOWR48H = 0U; - handle->useFifo48H = false; - } - else - { - base->FIFOWR = 0U; - base->FIFOWR48H = 0U; - } - } - else - { - base->FIFOWR = 0U; - } - - /* Next time invoke this handler when FIFO becomes empty (TX level 0) */ - base->FIFOTRIG &= ~I2S_FIFOTRIG_TXLVL_MASK; - handle->state = (uint32_t)kI2S_StateTxWaitForEmptyFifo; - } - else if (handle->state == (uint32_t)kI2S_StateTxWaitForEmptyFifo) - { - /* FIFO, including additional dummy data, has been emptied now, - * all relevant data should have been output from peripheral */ - - /* Stop transfer */ - I2S_Disable(base); - I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - - /* Reset state */ - handle->state = (uint32_t)kI2S_StateIdle; - - /* Notify user */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); - } - } - else - { - /* Do nothing */ - } - - /* Clear TX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_TXLVL(1U); - } -} - -/*! - * brief Invoked from interrupt handler when receive FIFO level decreases. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) -{ - uint32_t intstat = base->FIFOINTSTAT; - uint32_t data; - uint8_t queueDriverIndex = handle->queueDriver; - uint32_t dataAddr = (uint32_t)handle->i2sQueue[queueDriverIndex].data; - uint32_t dataSize = handle->i2sQueue[queueDriverIndex].dataSize; - - if ((intstat & I2S_FIFOINTSTAT_RXERR_MASK) != 0UL) - { - handle->errorCount++; - - /* Clear RX error interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXERR(1U); - } - - if ((intstat & I2S_FIFOINTSTAT_RXLVL_MASK) != 0UL) - { - while (((base->FIFOSTAT & I2S_FIFOSTAT_RXNOTEMPTY_MASK) != 0UL) && (dataSize > 0U)) - { - /* Read input data */ - if (handle->dataLength == 4U) - { - data = base->FIFORD; - *((uint8_t *)dataAddr) = (uint8_t)(((data & 0x000F0000U) >> 12U) | (data & 0x0000000FU)); - dataAddr++; - handle->transferCount++; - dataSize--; - } - else if (handle->dataLength <= 8U) - { - data = base->FIFORD; - - if (handle->oneChannel) - { - *((volatile uint8_t *)dataAddr) = (uint8_t)(data & 0xFFU); - dataAddr += sizeof(uint8_t); - handle->transferCount += sizeof(uint8_t); - dataSize -= sizeof(uint8_t); - } - else - { - *((volatile uint16_t *)dataAddr) = (uint16_t)(((data >> 8U) & 0xFF00U) | (data & 0xFFU)); - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - } - else if (handle->dataLength <= 16U) - { - data = base->FIFORD; - - if (handle->oneChannel) - { - *((volatile uint16_t *)dataAddr) = (uint16_t)(data & 0xFFFFU); - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - else - { - *((volatile uint32_t *)dataAddr) = data; - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - } - else if (handle->dataLength <= 24U) - { - if (handle->pack48) - { - if (handle->useFifo48H) - { - data = base->FIFORD48H; - handle->useFifo48H = false; - - *((volatile uint16_t *)dataAddr) = (uint16_t)data; - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - else - { - data = base->FIFORD; - handle->useFifo48H = true; - - *((volatile uint32_t *)dataAddr) = data; - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - } - else - { - if (handle->useFifo48H) - { - data = base->FIFORD48H; - handle->useFifo48H = false; - } - else - { - data = base->FIFORD; - handle->useFifo48H = true; - } - - *(uint8_t *)(dataAddr++) = (uint8_t)(data & 0xFFU); - *(uint8_t *)(dataAddr++) = (uint8_t)((data >> 8U) & 0xFFU); - *(uint8_t *)(dataAddr++) = (uint8_t)((data >> 16U) & 0xFFU); - handle->transferCount += 3U; - dataSize -= 3U; - } - } - else /* if (handle->dataLength <= 32U) */ - { - data = base->FIFORD; - *((volatile uint32_t *)dataAddr) = data; - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - - if (dataSize == 0U) - { - handle->i2sQueue[queueDriverIndex].dataSize = 0U; - /* Actual data buffer filled with input data, switch to a next one */ - handle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; - - /* Notify user */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); - } - - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* No other buffer prepared to receive data into */ - - /* Disable I2S operation and interrupts */ - I2S_Disable(base); - I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - - /* Reset state */ - handle->state = (uint32_t)kI2S_StateIdle; - - /* Notify user */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); - } - - /* Clear RX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); - - return; - } - } - else - { - handle->i2sQueue[queueDriverIndex].dataSize = dataSize; - handle->i2sQueue[queueDriverIndex].data = (uint8_t *)dataAddr; - } - } - - /* Clear RX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2s.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2s.h deleted file mode 100644 index e0787d6b145..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2s.h +++ /dev/null @@ -1,513 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2S_H_ -#define _FSL_I2S_H_ - -#include "fsl_device_registers.h" -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup i2s_driver - * @{ - */ - -/*! @file */ - -/*! @name Driver version */ -/*@{*/ - -/*! @brief I2S driver version 2.3.1. */ -#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) -/*@}*/ - -#ifndef I2S_NUM_BUFFERS - -/*! @brief Number of buffers . */ -#define I2S_NUM_BUFFERS (4U) - -#endif - -/*! @brief _i2s_status I2S status codes. */ -enum -{ - kStatus_I2S_BufferComplete = - MAKE_STATUS(kStatusGroup_I2S, 0), /*!< Transfer from/into a single buffer has completed */ - kStatus_I2S_Done = MAKE_STATUS(kStatusGroup_I2S, 1), /*!< All buffers transfers have completed */ - kStatus_I2S_Busy = - MAKE_STATUS(kStatusGroup_I2S, 2), /*!< Already performing a transfer and cannot queue another buffer */ -}; - -/*! - * @brief I2S flags. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -typedef enum _i2s_flags -{ - kI2S_TxErrorFlag = I2S_FIFOINTENSET_TXERR_MASK, /*!< TX error interrupt */ - kI2S_TxLevelFlag = I2S_FIFOINTENSET_TXLVL_MASK, /*!< TX level interrupt */ - kI2S_RxErrorFlag = I2S_FIFOINTENSET_RXERR_MASK, /*!< RX error interrupt */ - kI2S_RxLevelFlag = I2S_FIFOINTENSET_RXLVL_MASK /*!< RX level interrupt */ -} i2s_flags_t; - -/*! @brief Master / slave mode. */ -typedef enum _i2s_master_slave -{ - kI2S_MasterSlaveNormalSlave = 0x0, /*!< Normal slave */ - kI2S_MasterSlaveWsSyncMaster = 0x1, /*!< WS synchronized master */ - kI2S_MasterSlaveExtSckMaster = 0x2, /*!< Master using existing SCK */ - kI2S_MasterSlaveNormalMaster = 0x3 /*!< Normal master */ -} i2s_master_slave_t; - -/*! @brief I2S mode. */ -typedef enum _i2s_mode -{ - kI2S_ModeI2sClassic = 0x0, /*!< I2S classic mode */ - kI2S_ModeDspWs50 = 0x1, /*!< DSP mode, WS having 50% duty cycle */ - kI2S_ModeDspWsShort = 0x2, /*!< DSP mode, WS having one clock long pulse */ - kI2S_ModeDspWsLong = 0x3 /*!< DSP mode, WS having one data slot long pulse */ -} i2s_mode_t; - -/*! @brief _i2s_secondary_channel I2S secondary channel. */ -enum -{ - kI2S_SecondaryChannel1 = 0U, /*!< secondary channel 1 */ - kI2S_SecondaryChannel2 = 1U, /*!< secondary channel 2 */ - kI2S_SecondaryChannel3 = 2U, /*!< secondary channel 3 */ -}; - -/*! @brief I2S configuration structure. */ -typedef struct _i2s_config -{ - i2s_master_slave_t masterSlave; /*!< Master / slave configuration */ - i2s_mode_t mode; /*!< I2S mode */ - bool rightLow; /*!< Right channel data in low portion of FIFO */ - bool leftJust; /*!< Left justify data in FIFO */ -#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) - bool pdmData; /*!< Data source is the D-Mic subsystem */ -#endif - bool sckPol; /*!< SCK polarity */ - bool wsPol; /*!< WS polarity */ - uint16_t divider; /*!< Flexcomm function clock divider (1 - 4096) */ - bool oneChannel; /*!< true mono, false stereo */ - uint8_t dataLength; /*!< Data length (4 - 32) */ - uint16_t frameLength; /*!< Frame width (4 - 512) */ - uint16_t position; /*!< Data position in the frame */ - uint8_t watermark; /*!< FIFO trigger level */ - bool txEmptyZero; /*!< Transmit zero when buffer becomes empty or last item */ - bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit - values) */ -} i2s_config_t; - -/*! @brief Buffer to transfer from or receive audio data into. */ -typedef struct _i2s_transfer -{ - uint8_t *data; /*!< Pointer to data buffer. */ - size_t dataSize; /*!< Buffer size in bytes. */ -} i2s_transfer_t; - -/*! @brief Transactional state of the intialized transfer or receive I2S operation. */ -typedef struct _i2s_handle i2s_handle_t; - -/*! - * @brief Callback function invoked from transactional API - * on completion of a single buffer transfer. - * - * @param base I2S base pointer. - * @param handle pointer to I2S transaction. - * @param completionStatus status of the transaction. - * @param userData optional pointer to user arguments data. - */ -typedef void (*i2s_transfer_callback_t)(I2S_Type *base, - i2s_handle_t *handle, - status_t completionStatus, - void *userData); - -/*! @brief Members not to be accessed / modified outside of the driver. */ -struct _i2s_handle -{ - volatile uint32_t state; /*!< State of transfer */ - i2s_transfer_callback_t completionCallback; /*!< Callback function pointer */ - void *userData; /*!< Application data passed to callback */ - bool oneChannel; /*!< true mono, false stereo */ - uint8_t dataLength; /*!< Data length (4 - 32) */ - bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit - values) */ - uint8_t watermark; /*!< FIFO trigger level */ - bool useFifo48H; /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */ - - volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ - volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ - volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ - volatile uint32_t errorCount; /*!< Number of buffer underruns/overruns */ - volatile uint32_t transferCount; /*!< Number of bytes transferred */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S transmission using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_TxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the I2S driver. - * - * @param base I2S base pointer. - * @param config pointer to I2S configuration structure. - */ -void I2S_TxInit(I2S_Type *base, const i2s_config_t *config); - -/*! - * @brief Initializes the FLEXCOMM peripheral for I2S receive functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S receive using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_RxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the I2S driver. - * - * @param base I2S base pointer. - * @param config pointer to I2S configuration structure. - */ -void I2S_RxInit(I2S_Type *base, const i2s_config_t *config); - -/*! - * @brief Sets the I2S Tx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_TxInit(). - * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified - * before calling I2S_TxInit(). - * Example: - @code - i2s_config_t config; - I2S_TxGetDefaultConfig(&config); - @endcode - * - * Default values: - * @code - * config->masterSlave = kI2S_MasterSlaveNormalMaster; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = true; - * config->pack48 = false; - * @endcode - * - * @param config pointer to I2S configuration structure. - */ -void I2S_TxGetDefaultConfig(i2s_config_t *config); - -/*! - * @brief Sets the I2S Rx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_RxInit(). - * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified - * before calling I2S_RxInit(). - * Example: - @code - i2s_config_t config; - I2S_RxGetDefaultConfig(&config); - @endcode - * - * Default values: - * @code - * config->masterSlave = kI2S_MasterSlaveNormalSlave; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = false; - * config->pack48 = false; - * @endcode - * - * @param config pointer to I2S configuration structure. - */ -void I2S_RxGetDefaultConfig(i2s_config_t *config); - -/*! - * @brief De-initializes the I2S peripheral. - * - * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit - * or I2S_RxInit is called to enable the clock. - * - * @param base I2S base pointer. - */ -void I2S_Deinit(I2S_Type *base); - -/*! - * @brief Transmitter/Receiver bit clock rate configurations. - * - * @param base SAI base pointer. - * @param sourceClockHz bit clock source frequency. - * @param sampleRate audio data sample rate. - * @param bitWidth audio data bitWidth. - * @param channelNumbers audio channel numbers. - */ -void I2S_SetBitClockRate( - I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers); - -/*! @} */ - -/*! - * @name Non-blocking API - * @{ - */ - -/*! - * @brief Initializes handle for transfer of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); - -/*! - * @brief Begins or queue sending of the given data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts sending of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Initializes handle for reception of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); - -/*! - * @brief Begins or queue reception of data into given buffer. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. - */ -status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts receiving of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Returns number of bytes transferred so far. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param[out] count number of bytes transferred so far by the non-blocking transaction. - * - * @retval kStatus_Success - * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); - -/*! - * @brief Returns number of buffer underruns or overruns. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param[out] count number of transmit errors encountered so far by the non-blocking transaction. - * - * @retval kStatus_Success - * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); - -/*! @} */ - -/*! - * @name Enable / disable - * @{ - */ - -/*! - * @brief Enables I2S operation. - * - * @param base I2S base pointer. - */ -static inline void I2S_Enable(I2S_Type *base) -{ - base->CFG1 |= I2S_CFG1_MAINENABLE(1U); -} - -#if (defined(FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) && FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) -/*! - * @brief Enables I2S secondary channel. - * - * @param base I2S base pointer. - * @param channel seondary channel channel number, reference _i2s_secondary_channel. - * @param oneChannel true is treated as single channel, functionality left channel for this pair. - * @param position define the location within the frame of the data, should not bigger than 0x1FFU. - */ -void I2S_EnableSecondaryChannel(I2S_Type *base, uint32_t channel, bool oneChannel, uint32_t position); - -/*! - * @brief Disables I2S secondary channel. - * - * @param base I2S base pointer. - * @param channel seondary channel channel number, reference _i2s_secondary_channel. - */ -static inline void I2S_DisableSecondaryChannel(I2S_Type *base, uint32_t channel) -{ -#if defined FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn - assert(FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn((FLEXCOMM_Type *)(uint32_t)base) == 1); -#endif - - base->SECCHANNEL[channel].PCFG1 &= ~I2S_CFG1_MAINENABLE_MASK; -} -#endif -/*! - * @brief Disables I2S operation. - * - * @param base I2S base pointer. - */ -static inline void I2S_Disable(I2S_Type *base) -{ - base->CFG1 &= (~I2S_CFG1_MAINENABLE(1U)); -} - -/*! @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables I2S FIFO interrupts. - * - * @param base I2S base pointer. - * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2S_EnableInterrupts(I2S_Type *base, uint32_t interruptMask) -{ - base->FIFOINTENSET = interruptMask; -} - -/*! - * @brief Disables I2S FIFO interrupts. - * - * @param base I2S base pointer. - * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2S_DisableInterrupts(I2S_Type *base, uint32_t interruptMask) -{ - base->FIFOINTENCLR = interruptMask; -} - -/*! - * @brief Returns the set of currently enabled I2S FIFO interrupts. - * - * @param base I2S base pointer. - * - * @return A bitmask composed of #i2s_flags_t enumerators OR'd together - * to indicate the set of enabled interrupts. - */ -static inline uint32_t I2S_GetEnabledInterrupts(I2S_Type *base) -{ - return base->FIFOINTENSET; -} - -/*! - * @brief Flush the valid data in TX fifo. - * - * @param base I2S base pointer. - * @return kStatus_Fail empty TX fifo failed, kStatus_Success empty tx fifo success. - */ -status_t I2S_EmptyTxFifo(I2S_Type *base); - -/*! - * @brief Invoked from interrupt handler when transmit FIFO level decreases. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Invoked from interrupt handler when receive FIFO level decreases. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); - -/*! @} */ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2S_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2s_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2s_dma.c deleted file mode 100644 index 84f25b30e91..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2s_dma.c +++ /dev/null @@ -1,848 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_dma.h" -#include "fsl_i2s_dma.h" -#include "fsl_flexcomm.h" -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s_dma" -#endif - -#define DMA_MAX_TRANSFER_BYTES (DMA_MAX_TRANSFER_COUNT * sizeof(uint32_t)) -#define DMA_DESCRIPTORS (2U) - -/*i2sQueue[handle->queueUser].dataSize != 0UL) - { - /* Previously prepared buffers not processed yet, reject request */ - return kStatus_I2S_Busy; - } - - /* Enqueue data */ - privateHandle->descriptorQueue[handle->queueUser].data = transfer.data; - privateHandle->descriptorQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - return kStatus_Success; -} - -static uint32_t I2S_GetInstance(I2S_Type *base) -{ - uint32_t i; - - for (i = 0U; i < ARRAY_SIZE(s_I2sBaseAddrs); i++) - { - if ((uint32_t)base == s_I2sBaseAddrs[i]) - { - return i; - } - } - - assert(false); - return 0U; -} - -static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle) -{ - DMA_DisableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); -} - -static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle) -{ - if (handle->state != (uint32_t)kI2S_DmaStateIdle) - { - DMA_EnableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); - } -} - -/*! - * brief Initializes handle for transfer of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param dmaHandle pointer to dma handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData) -{ - assert(handle != NULL); - assert(dmaHandle != NULL); - - uint32_t instance = I2S_GetInstance(base); - i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - - (void)memset(handle, 0, sizeof(*handle)); - handle->state = (uint32_t)kI2S_DmaStateIdle; - handle->dmaHandle = dmaHandle; - handle->completionCallback = callback; - handle->userData = userData; - - handle->bytesPerFrame = (uint8_t)((((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U) / 8U); - /* if one channel is disabled, bytesPerFrame should be 4U, user should pay attention that when data length is - * shorter than 16, the data format: left data put in 0-15 bit and right data should put in 16-31 - */ - if (((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) == 0U)) - { - handle->bytesPerFrame = 4U; - } - /* since DMA do not support 24bit transfer width, use 32bit instead */ - if (handle->bytesPerFrame == 3U) - { - handle->bytesPerFrame = 4U; - } - - (void)memset(privateHandle, 0, sizeof(*privateHandle)); - privateHandle->base = base; - privateHandle->handle = handle; - - DMA_SetCallback(dmaHandle, I2S_DMACallback, privateHandle); -} - -/*! - * brief Begins or queue sending of the given data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) -{ - status_t status; - - I2S_DisableDMAInterrupts(handle); - - /* Enqueue transfer buffer */ - status = I2S_EnqueueUserBuffer(base, handle, transfer); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - - /* Initialize DMA transfer */ - if (handle->state == (uint32_t)kI2S_DmaStateIdle) - { - handle->state = (uint32_t)kI2S_DmaStateTx; - status = I2S_StartTransferDMA(base, handle); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - } - - I2S_AddTransferDMA(base, handle); - I2S_EnableDMAInterrupts(handle); - - return kStatus_Success; -} - -/*! - * brief Aborts transfer of data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - assert(handle != NULL); - assert(handle->dmaHandle != NULL); - - uint32_t instance = I2S_GetInstance(base); - i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - - I2S_DisableDMAInterrupts(handle); - - /* Abort operation */ - DMA_AbortTransfer(handle->dmaHandle); - - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - /* Disable TX */ - I2S_TxEnableDMA(base, false); - } - else - { - /* Disable RX */ - I2S_RxEnableDMA(base, false); - } - - I2S_Disable(base); - - /* Reset state */ - handle->state = (uint32_t)kI2S_DmaStateIdle; - - /* Clear transfer queue */ - (void)memset((void *)&(handle->i2sQueue), 0, sizeof(handle->i2sQueue)); - handle->queueDriver = 0U; - handle->queueUser = 0U; - - /* Clear internal state */ - (void)memset((void *)&(privateHandle->descriptorQueue), 0, sizeof(privateHandle->descriptorQueue)); - (void)memset((void *)&(privateHandle->enqueuedBytes), 0, sizeof(privateHandle->enqueuedBytes)); - privateHandle->enqueuedBytesStart = 0U; - privateHandle->enqueuedBytesEnd = 0U; - privateHandle->dmaDescriptorsUsed = 0U; - privateHandle->descriptor = 0U; - privateHandle->queueDescriptor = 0U; - privateHandle->intA = false; -} - -/*! - * brief Initializes handle for reception of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param dmaHandle pointer to dma handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData) -{ - I2S_TxTransferCreateHandleDMA(base, handle, dmaHandle, callback, userData); -} - -/*! - * brief Begins or queue reception of data into given buffer. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with buffers - * which are not full. - */ -status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) -{ - status_t status; - - I2S_DisableDMAInterrupts(handle); - - /* Enqueue transfer buffer */ - status = I2S_EnqueueUserBuffer(base, handle, transfer); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - - /* Initialize DMA transfer */ - if (handle->state == (uint32_t)kI2S_DmaStateIdle) - { - handle->state = (uint32_t)kI2S_DmaStateRx; - status = I2S_StartTransferDMA(base, handle); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - } - - I2S_AddTransferDMA(base, handle); - I2S_EnableDMAInterrupts(handle); - - return kStatus_Success; -} - -static void I2S_TxEnableDMA(I2S_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= I2S_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= (~I2S_FIFOCFG_DMATX_MASK); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - } -} - -static void I2S_RxEnableDMA(I2S_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= I2S_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= (~I2S_FIFOCFG_DMARX_MASK); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - } -} - -static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer) -{ - assert(transfer != NULL); - - uint16_t transferBytes; - - if (transfer->dataSize >= (2UL * DMA_MAX_TRANSFER_BYTES)) - { - transferBytes = DMA_MAX_TRANSFER_BYTES; - } - else if (transfer->dataSize > DMA_MAX_TRANSFER_BYTES) - { - transferBytes = (uint16_t)(transfer->dataSize / 2U); - if ((transferBytes % 4U) != 0U) - { - transferBytes -= (transferBytes % 4U); - } - } - else - { - transferBytes = (uint16_t)transfer->dataSize; - } - - return transferBytes; -} - -/*! - * brief Install DMA descriptor memory for loop transfer only. - * - * This function used to register DMA descriptor memory for the i2s loop dma transfer. - * - * It must be callbed before I2S_TransferSendLoopDMA/I2S_TransferReceiveLoopDMA and after - * I2S_RxTransferCreateHandleDMA/I2S_TxTransferCreateHandleDMA. - * - * User should be take care about the address of DMA descriptor pool which required align with 16BYTE at least. - * - * param handle Pointer to i2s DMA transfer handle. - * param dmaDescriptorAddr DMA descriptor start address. - * param dmaDescriptorNum DMA descriptor number. - */ -void I2S_TransferInstallLoopDMADescriptorMemory(i2s_dma_handle_t *handle, - void *dmaDescriptorAddr, - size_t dmaDescriptorNum) -{ - assert(handle != NULL); - assert((((uint32_t)(uint32_t *)dmaDescriptorAddr) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == - 0UL); - - handle->i2sLoopDMADescriptor = (dma_descriptor_t *)dmaDescriptorAddr; - handle->i2sLoopDMADescriptorNum = dmaDescriptorNum; -} - -static status_t I2S_TransferLoopDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - i2s_transfer_t *xfer, - uint32_t loopTransferCount) -{ - assert(handle != NULL); - assert(handle->dmaHandle != NULL); - assert(xfer != NULL); - - uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; - i2s_transfer_t *currentTransfer = xfer; - bool intA = true; - - if (handle->i2sLoopDMADescriptor == NULL) - { - return kStatus_InvalidArgument; - } - - if (handle->state == (uint32_t)kI2S_DmaStateBusyLoopTransfer) - { - return kStatus_I2S_Busy; - } - - for (uint32_t i = 0U; i < loopTransferCount; i++) - { - currentTransfer = &xfer[i]; - - if ((currentTransfer->data == NULL) || (currentTransfer->dataSize == 0U) || - (i >= handle->i2sLoopDMADescriptorNum) || - (currentTransfer->dataSize / handle->bytesPerFrame > DMA_MAX_TRANSFER_COUNT)) - { - return kStatus_InvalidArgument; - } - - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - srcAddr = (uint32_t *)(uint32_t)currentTransfer->data; - destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); - srcInc = 1U; - destInc = 0UL; - } - else - { - srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); - destAddr = (uint32_t *)(uint32_t)currentTransfer->data; - srcInc = 0U; - destInc = 1UL; - } - - intA = intA == true ? false : true; - - if (i == (loopTransferCount - 1U)) - { - /* set up linked descriptor */ - DMA_SetupDescriptor(&handle->i2sLoopDMADescriptor[i], - DMA_CHANNEL_XFER(1UL, 0UL, intA, !intA, handle->bytesPerFrame, srcInc, destInc, - currentTransfer->dataSize), - srcAddr, destAddr, &handle->i2sLoopDMADescriptor[0U]); - } - else - { - /* set up linked descriptor */ - DMA_SetupDescriptor(&handle->i2sLoopDMADescriptor[i], - DMA_CHANNEL_XFER(1UL, 0UL, intA, !intA, handle->bytesPerFrame, srcInc, destInc, - currentTransfer->dataSize), - srcAddr, destAddr, &handle->i2sLoopDMADescriptor[i + 1U]); - } - } - - /* transferSize make sense to non link transfer only */ - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - srcAddr = (uint32_t *)(uint32_t)xfer->data; - destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); - srcInc = 1U; - destInc = 0UL; - } - else - { - srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); - destAddr = (uint32_t *)(uint32_t)xfer->data; - srcInc = 0U; - destInc = 1UL; - } - - DMA_SubmitChannelTransferParameter( - handle->dmaHandle, - DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 1UL, handle->bytesPerFrame, srcInc, destInc, (uint32_t)xfer->dataSize), srcAddr, - destAddr, (void *)&handle->i2sLoopDMADescriptor[1U]); - - /* Submit and start initial DMA transfer */ - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - I2S_TxEnableDMA(base, true); - } - else - { - I2S_RxEnableDMA(base, true); - } - DMA_EnableChannelPeriphRq(handle->dmaHandle->base, handle->dmaHandle->channel); - /* start transfer */ - DMA_StartTransfer(handle->dmaHandle); - I2S_Enable(base); - - handle->state = (uint32_t)kI2S_DmaStateBusyLoopTransfer; - - return kStatus_Success; -} - -/*! - * brief Send loop transfer data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * This function support loop transfer, such as A->B->...->A, the loop transfer chain - * will be converted into a chain of descriptor and submit to dma. - * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, - * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. - * - * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support - * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop - * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. - * - * param base I2S peripheral base address. - * param handle Pointer to usart_dma_handle_t structure. - * param xfer I2S DMA transfer structure. See #i2s_transfer_t. - * param i2s_channel I2S start channel number - * retval kStatus_Success - */ -status_t I2S_TransferSendLoopDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - i2s_transfer_t *xfer, - uint32_t loopTransferCount) -{ - assert(handle != NULL); - assert(handle->i2sLoopDMADescriptor != NULL); - - handle->state = (uint32_t)kI2S_DmaStateTx; - - return I2S_TransferLoopDMA(base, handle, xfer, loopTransferCount); -} - -/*! - * brief Receive loop transfer data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * This function support loop transfer, such as A->B->...->A, the loop transfer chain - * will be converted into a chain of descriptor and submit to dma. - * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, - * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. - * - * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support - * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop - * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. - * - * param base I2S peripheral base address. - * param handle Pointer to usart_dma_handle_t structure. - * param xfer I2S DMA transfer structure. See #i2s_transfer_t. - * param i2s_channel I2S start channel number - * retval kStatus_Success - */ -status_t I2S_TransferReceiveLoopDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - i2s_transfer_t *xfer, - uint32_t loopTransferCount) -{ - assert(handle != NULL); - assert(handle->i2sLoopDMADescriptor != NULL); - - handle->state = (uint32_t)kI2S_DmaStateRx; - - return I2S_TransferLoopDMA(base, handle, xfer, loopTransferCount); -} - -static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - uint32_t instance = I2S_GetInstance(base); - i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - volatile i2s_transfer_t *transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); - uint16_t transferBytes = I2S_GetTransferBytes(transfer); - uint32_t i = 0U; - uint32_t xferConfig = 0U; - uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; - - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - srcAddr = (uint32_t *)(uint32_t)transfer->data; - destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); - srcInc = 1U; - destInc = 0UL; - } - else - { - srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); - destAddr = (uint32_t *)(uint32_t)transfer->data; - srcInc = 0U; - destInc = 1UL; - } - /* Initial descriptor is stored in another place in memory, but treat it as another descriptor for simplicity */ - privateHandle->dmaDescriptorsUsed = 1U; - privateHandle->intA = false; - - /* submit transfer parameter directly */ - xferConfig = DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 1UL, handle->bytesPerFrame, srcInc, destInc, (uint32_t)transferBytes); - - DMA_SubmitChannelTransferParameter(handle->dmaHandle, xferConfig, srcAddr, destAddr, - (void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U])); - - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; - privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; - - transfer->dataSize -= transferBytes; - transfer->data = (uint8_t *)((uint32_t)transfer->data + transferBytes); - - if (transfer->dataSize == 0U) - { - transfer->data = NULL; - privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; - } - - /* Link the DMA descriptors for the case when no additional transfer is queued before the initial one finishes - * The configuration for the DMA dummy descriptor make no sense to tx or rx transfer, since it will be overwritten - * when another transfer request comes before the previous finished. - * To make sure the audio data transfer continuously, application must request another transfer by call - * I2S_RxTransferReceiveDMA or I2S_TxTransferSendDMA before previous transfer finished. - */ - for (i = 0; i < DMA_DESCRIPTORS; i++) - { - /* DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 0UL, sizeof(uint32_t), 0U, 0U, 8U) = 0x10203UL */ - DMA_SetupDescriptor( - &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + i]), 0x10203UL, - ((handle->state == (uint32_t)kI2S_DmaStateTx) ? &s_DummyBufferTx : (uint32_t *)(uint32_t)(&(base->FIFORD))), - ((handle->state == (uint32_t)kI2S_DmaStateTx) ? (uint32_t *)(uint32_t)(&(base->FIFOWR)) : &s_DummyBufferRx), - &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + ((i + 1U) % DMA_DESCRIPTORS)])); - } - - /* Submit and start initial DMA transfer */ - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - I2S_TxEnableDMA(base, true); - } - else - { - I2S_RxEnableDMA(base, true); - } - /* enable I2S peripheral request and put the channel into triggered status */ - DMA_EnableChannelPeriphRq(handle->dmaHandle->base, handle->dmaHandle->channel); - DMA_StartTransfer(handle->dmaHandle); - - I2S_Enable(base); - - return kStatus_Success; -} - -static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - volatile i2s_transfer_t *transfer; - uint16_t transferBytes; - uint32_t instance; - i2s_dma_private_handle_t *privateHandle; - dma_descriptor_t *descriptor; - dma_descriptor_t *nextDescriptor; - uint32_t xferConfig = 0U; - bool intA = false; - uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; - - instance = I2S_GetInstance(base); - privateHandle = &(s_DmaPrivateHandle[instance]); - - while (privateHandle->dmaDescriptorsUsed < DMA_DESCRIPTORS) - { - transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); - intA = privateHandle->intA; - if (transfer->dataSize == 0U) - { - /* Nothing to be added */ - return; - } - - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - srcAddr = (uint32_t *)(uint32_t)transfer->data; - destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); - srcInc = 1U; - destInc = 0UL; - } - else - { - srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); - destAddr = (uint32_t *)(uint32_t)transfer->data; - srcInc = 0U; - destInc = 1UL; - } - - /* Determine currently configured descriptor and the other which it will link to */ - descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); - privateHandle->descriptor = (privateHandle->descriptor + 1U) % DMA_DESCRIPTORS; - nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); - - transferBytes = I2S_GetTransferBytes(transfer); - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; - privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; - - xferConfig = - DMA_CHANNEL_XFER(1UL, 0UL, !intA, intA, handle->bytesPerFrame, srcInc, destInc, (uint32_t)transferBytes); - - DMA_SetupDescriptor(descriptor, xferConfig, srcAddr, destAddr, nextDescriptor); - - /* Advance internal state */ - privateHandle->dmaDescriptorsUsed++; - privateHandle->intA = !privateHandle->intA; - - transfer->dataSize -= transferBytes; - transfer->data += transferBytes; - if (transfer->dataSize == 0U) - { - transfer->data = NULL; - privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; - } - } -} - -/*! - * brief Invoked from DMA interrupt handler. - * - * param handle pointer to DMA handle structure. - * param userData argument for user callback. - * param transferDone if transfer was done. - * param tcds - */ -void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds) -{ - i2s_dma_private_handle_t *privateHandle = (i2s_dma_private_handle_t *)userData; - i2s_dma_handle_t *i2sHandle = privateHandle->handle; - I2S_Type *base = privateHandle->base; - uint8_t queueDriverIndex = i2sHandle->queueDriver; - uint32_t enqueueBytes = privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart]; - uint32_t queueDataAddr = (uint32_t)i2sHandle->i2sQueue[queueDriverIndex].data; - - if ((!transferDone) || (i2sHandle->state == (uint32_t)kI2S_DmaStateIdle)) - { - return; - } - - if (privateHandle->dmaDescriptorsUsed > 0U) - { - /* Finished descriptor, decrease amount of data to be processed */ - - i2sHandle->i2sQueue[queueDriverIndex].dataSize -= enqueueBytes; - i2sHandle->i2sQueue[queueDriverIndex].data = (uint8_t *)(queueDataAddr + enqueueBytes); - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] = 0U; - privateHandle->enqueuedBytesStart = (privateHandle->enqueuedBytesStart + 1U) % DMA_DESCRIPTORS; - privateHandle->dmaDescriptorsUsed--; - } - - if (i2sHandle->i2sQueue[queueDriverIndex].dataSize == 0U) - { - /* Entire user buffer sent or received - advance to next one */ - i2sHandle->i2sQueue[queueDriverIndex].data = NULL; - i2sHandle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; - /* Notify user about buffer completion */ - if (i2sHandle->completionCallback != NULL) - { - (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_BufferComplete, i2sHandle->userData); - } - } - - if (i2sHandle->state != (uint32_t)kI2S_DmaStateBusyLoopTransfer) - { - /* check next buffer queue is avaliable or not */ - if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U) - { - if (i2sHandle->state == (uint32_t)kI2S_DmaStateTx) - { - (void)I2S_EmptyTxFifo(base); - } - /* All user buffers processed */ - I2S_TransferAbortDMA(base, i2sHandle); - } - else - { - /* Enqueue another user buffer to DMA if it could not be done when in I2S_Rx/TxTransferSendDMA */ - I2S_AddTransferDMA(base, i2sHandle); - } - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2s_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2s_dma.h deleted file mode 100644 index ec63472653a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_i2s_dma.h +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2S_DMA_H_ -#define _FSL_I2S_DMA_H_ - -#include "fsl_device_registers.h" -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -#include "fsl_dma.h" -#include "fsl_i2s.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup i2s_dma_driver - * @{ - */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2S DMA driver version 2.3.1. */ -#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) -/*@}*/ - -/*! @brief Members not to be accessed / modified outside of the driver. */ -typedef struct _i2s_dma_handle i2s_dma_handle_t; - -/*! - * @brief Callback function invoked from DMA API on completion. - * - * @param base I2S base pointer. - * @param handle pointer to I2S transaction. - * @param completionStatus status of the transaction. - * @param userData optional pointer to user arguments data. - */ -typedef void (*i2s_dma_transfer_callback_t)(I2S_Type *base, - i2s_dma_handle_t *handle, - status_t completionStatus, - void *userData); -/*! @brief i2s dma handle */ -struct _i2s_dma_handle -{ - uint32_t state; /*!< Internal state of I2S DMA transfer */ - uint8_t bytesPerFrame; /*!< bytes per frame */ - i2s_dma_transfer_callback_t completionCallback; /*!< Callback function pointer */ - void *userData; /*!< Application data passed to callback */ - dma_handle_t *dmaHandle; /*!< DMA handle */ - volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ - volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ - volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ - - dma_descriptor_t *i2sLoopDMADescriptor; /*!< descriptor pool pointer */ - size_t i2sLoopDMADescriptorNum; /*!< number of descriptor in descriptors pool */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! @} */ - -/*! - * @name DMA API - * @{ - */ - -/*! - * @brief Initializes handle for transfer of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param dmaHandle pointer to dma handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData); - -/*! - * @brief Begins or queue sending of the given data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts transfer of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle); - -/*! - * @brief Initializes handle for reception of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param dmaHandle pointer to dma handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData); - -/*! - * @brief Begins or queue reception of data into given buffer. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers - * which are not full. - */ -status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Invoked from DMA interrupt handler. - * - * @param handle pointer to DMA handle structure. - * @param userData argument for user callback. - * @param transferDone if transfer was done. - * @param tcds - */ -void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds); - -/*! - * @brief Install DMA descriptor memory for loop transfer only. - * - * This function used to register DMA descriptor memory for the i2s loop dma transfer. - * - * It must be callbed before I2S_TransferSendLoopDMA/I2S_TransferReceiveLoopDMA and after - * I2S_RxTransferCreateHandleDMA/I2S_TxTransferCreateHandleDMA. - * - * User should be take care about the address of DMA descriptor pool which required align with 16BYTE at least. - * - * @param handle Pointer to i2s DMA transfer handle. - * @param dmaDescriptorAddr DMA descriptor start address. - * @param dmaDescriptorNum DMA descriptor number. - */ -void I2S_TransferInstallLoopDMADescriptorMemory(i2s_dma_handle_t *handle, - void *dmaDescriptorAddr, - size_t dmaDescriptorNum); - -/*! - * @brief Send link transfer data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * This function support loop transfer, such as A->B->...->A, the loop transfer chain - * will be converted into a chain of descriptor and submit to dma. - * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, - * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. - * - * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support - * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop - * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. - * - * @param base I2S peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param xfer I2S DMA transfer structure. See #i2s_transfer_t. - * @param loopTransferCount loop count - * @retval kStatus_Success - */ -status_t I2S_TransferSendLoopDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - i2s_transfer_t *xfer, - uint32_t loopTransferCount); - -/*! - * @brief Receive link transfer data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * This function support loop transfer, such as A->B->...->A, the loop transfer chain - * will be converted into a chain of descriptor and submit to dma. - * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, - * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. - * - * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support - * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop - * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. - * - * @param base I2S peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param xfer I2S DMA transfer structure. See #i2s_transfer_t. - * @param loopTransferCount loop count - * @retval kStatus_Success - */ -status_t I2S_TransferReceiveLoopDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - i2s_transfer_t *xfer, - uint32_t loopTransferCount); - -/*! @} */ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2S_DMA_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_iap.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_iap.c deleted file mode 100644 index 712b0faef71..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_iap.c +++ /dev/null @@ -1,666 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "fsl_iap.h" -#include "fsl_iap_ffr.h" -#include "fsl_iap_kbp.h" -#include "fsl_iap_skboot_authenticate.h" -#include "fsl_device_registers.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.iap1" -#endif - -#if (defined(LPC5512_SERIES) || defined(LPC5514_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ - defined(LPC55S16_SERIES) || defined(LPC5524_SERIES) || defined(LPC5502_SERIES) || defined(LPC5504_SERIES) || \ - defined(LPC5506_SERIES) || defined(LPC55S04_SERIES) || defined(LPC55S06_SERIES)) - -#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1301fe00U) - -#elif (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || defined(LPC5526_SERIES) || \ - defined(LPC55S26_SERIES) || defined(LPC5528_SERIES) || defined(LPC55S28_SERIES) || \ - defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES)) - -#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x130010f0U) - -#else -#error "No valid CPU defined!" - -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -static status_t get_cfpa_higher_version(flash_config_t *config); - -/*! - * @name flash and ffr Structure - * @{ - */ - -typedef union functionCommandOption -{ - uint32_t commandAddr; - status_t (*eraseCommand)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - status_t (*programCommand)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); - status_t (*verifyProgramCommand)(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - status_t (*flashReadCommand)(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); -} function_command_option_t; - -/* - *!@brief Structure of version property. - * - *!@ingroup bl_core - */ -typedef union StandardVersion -{ - struct - { - uint32_t bugfix : 8; /*!< bugfix version [7:0] */ - uint32_t minor : 8; /*!< minor version [15:8] */ - uint32_t major : 8; /*!< major version [23:16] */ - uint32_t name : 8; /*!< name [31:24] */ - }; - uint32_t version; /*!< combined version numbers. */ -#if defined(__cplusplus) - StandardVersion() : version(0) - { - } - StandardVersion(uint32_t version) : version(version) - { - } -#endif -} standard_version_t; - -/*! @brief Interface for the flash driver.*/ -typedef struct version1FlashDriverInterface -{ - standard_version_t version; /*!< flash driver API version number.*/ - - /*!< Flash driver.*/ - status_t (*flash_init)(flash_config_t *config); - status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); - status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); - status_t (*flash_verify_program)(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); - uint32_t reserved[3]; /*! Reserved for future use */ - /*!< Flash FFR driver*/ - status_t (*ffr_init)(flash_config_t *config); - status_t (*ffr_lock_all)(flash_config_t *config); - status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); - status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); - status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); - status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode); - status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); - status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); - status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); -} version1_flash_driver_interface_t; - -/*! @brief Interface for the flash driver.*/ -typedef struct version0FlashDriverInterface -{ - standard_version_t version; /*!< flash driver API version number.*/ - - /*!< Flash driver.*/ - status_t (*flash_init)(flash_config_t *config); - status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); - status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); - status_t (*flash_verify_program)(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); - - /*!< Flash FFR driver*/ - status_t (*ffr_init)(flash_config_t *config); - status_t (*ffr_lock_all)(flash_config_t *config); - status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); - status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); - status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); - status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode); - status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); - status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); - status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); -} version0_flash_driver_interface_t; - -typedef union flashDriverInterface -{ - const version1_flash_driver_interface_t *version1FlashDriver; - const version0_flash_driver_interface_t *version0FlashDriver; -} flash_driver_interface_t; - -/*! @}*/ - -/*! - * @name Bootloader API and image authentication Structure - * @{ - */ - -/*! @brief Interface for Bootloader API functions. */ -typedef struct _kb_interface -{ - /*!< Initialize the API. */ - status_t (*kb_init_function)(kb_session_ref_t **session, const kb_options_t *options); - status_t (*kb_deinit_function)(kb_session_ref_t *session); - status_t (*kb_execute_function)(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength); -} kb_interface_t; - -//! @brief Interface for image authentication API -typedef struct _skboot_authenticate_interface -{ - skboot_status_t (*skboot_authenticate_function)(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified); - void (*skboot_hashcrypt_irq_handler)(void); -} skboot_authenticate_interface_t; -/*! @}*/ - -/*! - * @brief Root of the bootloader API tree. - * - * An instance of this struct resides in read-only memory in the bootloader. It - * provides a user application access to APIs exported by the bootloader. - * - * @note The order of existing fields must not be changed. - */ -typedef struct BootloaderTree -{ - void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing. */ - standard_version_t bootloader_version; /*!< Bootloader version number. */ - const char *copyright; /*!< Copyright string. */ - const uint32_t reserved0; /*!< Do NOT use. */ - flash_driver_interface_t flashDriver; - const kb_interface_t *kbApi; /*!< Bootloader API. */ - const uint32_t reserved1[4]; /*!< Do NOT use. */ - const skboot_authenticate_interface_t *skbootAuthenticate; /*!< Image authentication API. */ -} bootloader_tree_t; - -/******************************************************************************* - * Prototype - ******************************************************************************/ -static uint32_t get_rom_api_version(void); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! Get pointer to flash driver API table in ROM. */ -#define VERSION1_FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver.version1FlashDriver -#define VERSION0_FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver.version0FlashDriver -#define LPC55S69_REV0_FLASH_READ_ADDR (0x130043a3U) -#define LPC55S69_REV1_FLASH_READ_ADDR (0x13007539U) -#define LPC55S16_REV0_FLASH_READ_ADDR (0x1300ade5U) - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t get_rom_api_version(void) -{ - if (BOOTLOADER_API_TREE_POINTER->bootloader_version.major == 3u) - { - return 1u; - } - else - { - return 0u; - } -} - -/*! - * @brief Initializes the global flash properties structure members. - * - * This function checks and initializes the Flash module for the other Flash APIs. - */ -status_t FLASH_Init(flash_config_t *config) -{ - status_t status; - /* Initialize the clock to 96MHz */ - config->modeConfig.sysFreqInMHz = (uint32_t)kSysToFlashFreq_defaultInMHz; - if (get_rom_api_version() == 1u) - { - status = VERSION1_FLASH_API_TREE->flash_init(config); - } - else - { - status = VERSION0_FLASH_API_TREE->flash_init(config); - } - - if (config->PFlashTotalSize == 0xA0000U) - { - config->PFlashTotalSize -= 17U * config->PFlashPageSize; - } - - return status; -} - -/*! - * @brief Erases the flash sectors encompassed by parameters passed into function. - * - * This function erases the appropriate number of flash sectors based on the - * desired start address and length. - */ -status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) -{ - if (get_rom_api_version() == 0u) - { - function_command_option_t runCmdFuncOption; - runCmdFuncOption.commandAddr = 0x1300413bU; /*!< get the flash erase api location adress in rom */ - return runCmdFuncOption.eraseCommand(config, start, lengthInBytes, key); - } - else - { - return VERSION1_FLASH_API_TREE->flash_erase(config, start, lengthInBytes, key); - } -} - -/*! See fsl_iap.h for documentation of this function. */ -status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) -{ - if (get_rom_api_version() == 0u) - { - function_command_option_t runCmdFuncOption; - runCmdFuncOption.commandAddr = 0x1300419dU; /*!< get the flash program api location adress in rom*/ - return runCmdFuncOption.programCommand(config, start, src, lengthInBytes); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->flash_program(config, start, src, lengthInBytes); - } -} - -/*! See fsl_iap.h for documentation of this function. */ -status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes) -{ - if (get_rom_api_version() == 0u) - { - /*!< get the flash read api location adress in rom*/ - function_command_option_t runCmdFuncOption; - runCmdFuncOption.commandAddr = LPC55S69_REV0_FLASH_READ_ADDR; - return runCmdFuncOption.flashReadCommand(config, start, dest, lengthInBytes); - } - else - { - /*!< get the flash read api location adress in rom*/ - function_command_option_t runCmdFuncOption; - if ((SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK) != 0u) - { - runCmdFuncOption.commandAddr = LPC55S69_REV1_FLASH_READ_ADDR; - } - else - { - runCmdFuncOption.commandAddr = LPC55S16_REV0_FLASH_READ_ADDR; - } - return runCmdFuncOption.flashReadCommand(config, start, dest, lengthInBytes); - } -} - -/*! See fsl_iap.h for documentation of this function. */ -status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) -{ - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->flash_verify_erase(config, start, lengthInBytes); -} - -/*! - * @brief Verifies programming of the desired flash area at a specified margin level. - * - * This function verifies the data programed in the flash memory using the - * Flash Program Check Command and compares it to the expected data for a given - * flash area as determined by the start address and length. - */ -status_t FLASH_VerifyProgram(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData) -{ - if (get_rom_api_version() == 0u) - { - function_command_option_t runCmdFuncOption; - runCmdFuncOption.commandAddr = 0x1300427dU; /*!< get the flash verify program api location adress in rom*/ - return runCmdFuncOption.verifyProgramCommand(config, start, lengthInBytes, expectedData, failedAddress, - failedData); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->flash_verify_program(config, start, lengthInBytes, expectedData, failedAddress, - failedData); - } -} - -/*! - * @brief Returns the desired flash property. - */ -status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) -{ - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->flash_get_property(config, whichProperty, value); -} -/******************************************************************************** - * fsl iap ffr CODE - *******************************************************************************/ - -static status_t get_cfpa_higher_version(flash_config_t *config) -{ - uint32_t pageData[FLASH_FFR_MAX_PAGE_SIZE / sizeof(uint32_t)]; - uint32_t versionPing = 0U; - uint32_t versionPong = 0U; - - /* Get the CFPA ping page data and the corresponding version */ - config->ffrConfig.cfpaPageOffset = 1U; - status_t status = FFR_GetCustomerInfieldData(config, (uint8_t *)pageData, 0U, FLASH_FFR_MAX_PAGE_SIZE); - if (status != (int32_t)kStatus_FLASH_Success) - { - return status; - } - versionPing = pageData[1]; - - /* Get the CFPA pong page data and the corresponding version */ - config->ffrConfig.cfpaPageOffset = 2U; - status = FFR_GetCustomerInfieldData(config, (uint8_t *)pageData, 0U, FLASH_FFR_MAX_PAGE_SIZE); - if (status != (int32_t)kStatus_FLASH_Success) - { - return status; - } - versionPong = pageData[1]; - - /* Compare the CFPA ping version and pong version and set it correctly in flash_config structure */ - if (versionPing > versionPong) - { - config->ffrConfig.cfpaPageVersion = versionPing; - config->ffrConfig.cfpaPageOffset = 1U; - } - else - { - config->ffrConfig.cfpaPageVersion = versionPong; - config->ffrConfig.cfpaPageOffset = 2U; - } - return (int32_t)kStatus_FLASH_Success; -} - -/*! - * Initializes the global FFR properties structure members. - */ -status_t FFR_Init(flash_config_t *config) -{ - status_t status; - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - status = VERSION0_FLASH_API_TREE->ffr_init(config); - if (status != (status_t)kStatus_FLASH_Success) - { - return status; - } - return get_cfpa_higher_version(config); - } - else - { - assert(VERSION1_FLASH_API_TREE); - status = VERSION1_FLASH_API_TREE->ffr_init(config); - if (status != (status_t)kStatus_FLASH_Success) - { - return status; - } - return get_cfpa_higher_version(config); - } -} - -/*! - * Enable firewall for all flash banks. - */ -status_t FFR_Lock_All(flash_config_t *config) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_lock_all(config); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_lock_all(config); - } -} - -/*! - * APIs to access CMPA pages; - * This routine will erase "customer factory page" and program the page with passed data. - */ -status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part); - } -} - -/*! - * See fsl_iap_ffr.h for documentation of this function. - */ -status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_get_uuid(config, uuid); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_get_uuid(config, uuid); - } -} - -/*! - * APIs to access CMPA pages - * Read data stored in 'Customer Factory CFG Page'. - */ -status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len); - } -} - -/*! - * This routine writes the 3 pages allocated for Key store data, - * Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state. - */ -status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_keystore_write(config, pKeyStore); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_keystore_write(config, pKeyStore); - } -} - -/*! See fsl_iap_ffr.h for documentation of this function. */ -status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode); - } -} - -/*! See fsl_iap_ffr.h for documentation of this function. */ -status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex); - } -} - -/*! - * APIs to access CFPA pages - * This routine will erase CFPA and program the CFPA page with passed data. - */ -status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len); - } -} - -/*! - * APIs to access CFPA pages - * Generic read function, used by customer to read data stored in 'Customer In-field Page'. - */ -status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len); - } -} - -/******************************************************************************** - * Bootloader API - *******************************************************************************/ -/*! - * @brief Initialize ROM API for a given operation. - * - * Inits the ROM API based on the options provided by the application in the second - * argument. Every call to rom_init() should be paired with a call to rom_deinit(). - */ -status_t kb_init(kb_session_ref_t **session, const kb_options_t *options) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->kbApi->kb_init_function(session, options); -} - -/*! - * @brief Cleans up the ROM API context. - * - * After this call, the @a context parameter can be reused for another operation - * by calling rom_init() again. - */ -status_t kb_deinit(kb_session_ref_t *session) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->kbApi->kb_deinit_function(session); -} - -/*! - * Perform the operation configured during init. - * - * This application must call this API repeatedly, passing in sequential chunks of - * data from the boot image (SB file) that is to be processed. The ROM will perform - * the selected operation on this data and return. The application may call this - * function with as much or as little data as it wishes, which can be used to select - * the granularity of time given to the application in between executing the operation. - * - * @param context Current ROM context pointer. - * @param data Buffer of boot image data provided to the ROM by the application. - * @param dataLength Length in bytes of the data in the buffer provided to the ROM. - * - * @retval #kStatus_Success The operation has completed successfully. - * @retval #kStatus_Fail An error occurred while executing the operation. - * @retval #kStatus_RomApiNeedMoreData No error occurred, but the ROM needs more data to - * continue processing the boot image. - */ -status_t kb_execute(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->kbApi->kb_execute_function(session, data, dataLength); -} - -/******************************************************************************** - * Image authentication API - *******************************************************************************/ - -/*! - * @brief Authenticate entry function with ARENA allocator init - * - * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface - */ -skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->skbootAuthenticate->skboot_authenticate_function(imageStartAddr, - isSignVerified); -} - -/*! - * @brief Interface for image authentication API - */ -void HASH_IRQHandler(void) -{ - assert(BOOTLOADER_API_TREE_POINTER); - BOOTLOADER_API_TREE_POINTER->skbootAuthenticate->skboot_hashcrypt_irq_handler(); -} -/******************************************************************************** - * EOF - *******************************************************************************/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_iap.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_iap.h deleted file mode 100644 index f7b318b66bd..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_iap.h +++ /dev/null @@ -1,528 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __FSL_IAP_H_ -#define __FSL_IAP_H_ - -#include "fsl_common.h" -/*! - * @addtogroup flash_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! - * @name Flash version - * @{ - */ -/*! @brief Constructs the version number for drivers. */ -#if !defined(MAKE_VERSION) -#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) -#endif - -/*! @brief Flash driver version for SDK*/ -#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4. */ - -/*! @brief Flash driver version for ROM*/ -enum _flash_driver_version_constants -{ - kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ - kFLASH_DriverVersionMajor = 2, /*!< Major flash driver version.*/ - kFLASH_DriverVersionMinor = 1, /*!< Minor flash driver version.*/ - kFLASH_DriverVersionBugfix = 3 /*!< Bugfix for flash driver version.*/ -}; - -/*@}*/ - -/*! - * @name Flash configuration - * @{ - */ -/*! @brief Flash IP Type. */ -#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC) -#define FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC (1) -#endif -#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_FC) -#define FSL_FEATURE_FLASH_IP_IS_C040HD_FC (0) -#endif - -/*! - * @name Flash status - * @{ - */ -/*! @brief Flash driver status group. */ -#if defined(kStatusGroup_FlashDriver) -#define kStatusGroupGeneric kStatusGroup_Generic -#define kStatusGroupFlashDriver kStatusGroup_FlashDriver -#elif defined(kStatusGroup_FLASHIAP) -#define kStatusGroupGeneric kStatusGroup_Generic -#define kStatusGroupFlashDriver kStatusGroup_FLASH -#else -#define kStatusGroupGeneric 0 -#define kStatusGroupFlashDriver 1 -#endif - -/*! @brief Constructs a status code value from a group and a code number. */ -#if !defined(MAKE_STATUS) -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) -#endif - -/*! - * @brief Flash driver status codes. - */ -enum _flash_status -{ - kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ - kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ - kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ - kStatus_FLASH_AlignmentError = - MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ - kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ - kStatus_FLASH_AccessError = - MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ - kStatus_FLASH_ProtectionViolation = MAKE_STATUS( - kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ - kStatus_FLASH_CommandFailure = - MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ - kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ - kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/ - kStatus_FLASH_RegionExecuteOnly = - MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/ - kStatus_FLASH_ExecuteInRamFunctionNotReady = - MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/ - - kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Flash API is not supported.*/ - kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< The flash property is read-only.*/ - kStatus_FLASH_InvalidPropertyValue = - MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< The flash property value is out of range.*/ - kStatus_FLASH_InvalidSpeculationOption = - MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< The option of flash prefetch speculation is invalid.*/ - kStatus_FLASH_EccError = MAKE_STATUS(kStatusGroupFlashDriver, - 0x10), /*!< A correctable or uncorrectable error during command execution. */ - kStatus_FLASH_CompareError = - MAKE_STATUS(kStatusGroupFlashDriver, 0x11), /*!< Destination and source memory contents do not match. */ - kStatus_FLASH_RegulationLoss = MAKE_STATUS(kStatusGroupFlashDriver, 0x12), /*!< A loss of regulation during read. */ - kStatus_FLASH_InvalidWaitStateCycles = - MAKE_STATUS(kStatusGroupFlashDriver, 0x13), /*!< The wait state cycle set to r/w mode is invalid. */ - - kStatus_FLASH_OutOfDateCfpaPage = - MAKE_STATUS(kStatusGroupFlashDriver, 0x20), /*!< CFPA page version is out of date. */ - kStatus_FLASH_BlankIfrPageData = MAKE_STATUS(kStatusGroupFlashDriver, 0x21), /*!< Blank page cannnot be read. */ - kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce = - MAKE_STATUS(kStatusGroupFlashDriver, 0x22), /*!< Encrypted flash subregions are not erased at once. */ - kStatus_FLASH_ProgramVerificationNotAllowed = MAKE_STATUS( - kStatusGroupFlashDriver, 0x23), /*!< Program verification is not allowed when the encryption is enabled. */ - kStatus_FLASH_HashCheckError = - MAKE_STATUS(kStatusGroupFlashDriver, 0x24), /*!< Hash check of page data is failed. */ - kStatus_FLASH_SealedFfrRegion = MAKE_STATUS(kStatusGroupFlashDriver, 0x25), /*!< The FFR region is sealed. */ - kStatus_FLASH_FfrRegionWriteBroken = MAKE_STATUS( - kStatusGroupFlashDriver, 0x26), /*!< The FFR Spec region is not allowed to be written discontinuously. */ - kStatus_FLASH_NmpaAccessNotAllowed = - MAKE_STATUS(kStatusGroupFlashDriver, 0x27), /*!< The NMPA region is not allowed to be read/written/erased. */ - kStatus_FLASH_CmpaCfgDirectEraseNotAllowed = - MAKE_STATUS(kStatusGroupFlashDriver, 0x28), /*!< The CMPA Cfg region is not allowed to be erased directly. */ - kStatus_FLASH_FfrBankIsLocked = MAKE_STATUS(kStatusGroupFlashDriver, 0x29), /*!< The FFR bank region is locked. */ -}; -/*@}*/ - -/*! - * @name Flash API key - * @{ - */ -/*! @brief Constructs the four character code for the Flash driver API key. */ -#if !defined(FOUR_CHAR_CODE) -#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) -#endif - -/*! - * @brief Enumeration for Flash driver API keys. - * - * @note The resulting value is built with a byte order such that the string - * being readable in expected order when viewed in a hex editor, if the value - * is treated as a 32-bit little endian value. - */ -enum _flash_driver_api_keys -{ - kFLASH_ApiEraseKey = FOUR_CHAR_CODE('l', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ -}; -/*@}*/ - -/*! - * @brief Enumeration for various flash properties. - */ -typedef enum _flash_property_tag -{ - kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ - kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ - kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ - kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ - kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ - - kFLASH_PropertyPflashPageSize = 0x30U, /*!< Pflash page size property.*/ - kFLASH_PropertyPflashSystemFreq = 0x31U, /*!< System Frequency System Frequency.*/ - - kFLASH_PropertyFfrSectorSize = 0x40U, /*!< FFR sector size property.*/ - kFLASH_PropertyFfrTotalSize = 0x41U, /*!< FFR total size property.*/ - kFLASH_PropertyFfrBlockBaseAddr = 0x42U, /*!< FFR block base address property.*/ - kFLASH_PropertyFfrPageSize = 0x43U, /*!< FFR page size property.*/ -} flash_property_tag_t; - -/*! - * @brief Enumeration for flash max pages to erase. - */ -enum _flash_max_erase_page_value -{ - kFLASH_MaxPagesToErase = 100U /*!< The max value in pages to erase. */ -}; - -/*! - * @brief Enumeration for flash alignment property. - */ -enum _flash_alignment_property -{ - kFLASH_AlignementUnitVerifyErase = 4, /*!< The alignment unit in bytes used for verify erase operation.*/ - kFLASH_AlignementUnitProgram = 512, /*!< The alignment unit in bytes used for program operation.*/ - /*kFLASH_AlignementUnitVerifyProgram = 4,*/ /*!< The alignment unit in bytes used for verify program operation.*/ - kFLASH_AlignementUnitSingleWordRead = 16 /*!< The alignment unit in bytes used for SingleWordRead command.*/ -}; - -/*! - * @brief Enumeration for flash read ecc option - */ -enum _flash_read_ecc_option -{ - kFLASH_ReadWithEccOn = 0, /*! ECC is on */ - kFLASH_ReadWithEccOff = 1, /*! ECC is off */ -}; - -/* set flash Controller timing before flash init */ -enum _flash_freq_tag -{ - kSysToFlashFreq_lowInMHz = 12u, - kSysToFlashFreq_defaultInMHz = 96u, -}; - -/*! - * @brief Enumeration for flash read margin option - */ -enum _flash_read_margin_option -{ - kFLASH_ReadMarginNormal = 0, /*!< Normal read */ - kFLASH_ReadMarginVsProgram = 1, /*!< Margin vs. program */ - kFLASH_ReadMarginVsErase = 2, /*!< Margin vs. erase */ - kFLASH_ReadMarginIllegalBitCombination = 3 /*!< Illegal bit combination */ -}; - -/*! - * @brief Enumeration for flash read dmacc option - */ -enum _flash_read_dmacc_option -{ - kFLASH_ReadDmaccDisabled = 0, /*!< Memory word */ - kFLASH_ReadDmaccEnabled = 1, /*!< DMACC word */ -}; - -/*! - * @brief Enumeration for flash ramp control option - */ -enum _flash_ramp_control_option -{ - kFLASH_RampControlDivisionFactorReserved = 0, /*!< Reserved */ - kFLASH_RampControlDivisionFactor256 = 1, /*!< clk48mhz / 256 = 187.5KHz */ - kFLASH_RampControlDivisionFactor128 = 2, /*!< clk48mhz / 128 = 375KHz */ - kFLASH_RampControlDivisionFactor64 = 3 /*!< clk48mhz / 64 = 750KHz */ -}; - -/*! @brief Flash ECC log info. */ -typedef struct _flash_ecc_log -{ - uint32_t firstEccEventAddress; - uint32_t eccErrorCount; - uint32_t eccCorrectionCount; - uint32_t reserved; -} flash_ecc_log_t; - -/*! @brief Flash controller paramter config. */ -typedef struct _flash_mode_config -{ - uint32_t sysFreqInMHz; - /* ReadSingleWord parameter. */ - struct - { - uint8_t readWithEccOff : 1; - uint8_t readMarginLevel : 2; - uint8_t readDmaccWord : 1; - uint8_t reserved0 : 4; - uint8_t reserved1[3]; - } readSingleWord; - /* SetWriteMode parameter. */ - struct - { - uint8_t programRampControl; - uint8_t eraseRampControl; - uint8_t reserved[2]; - } setWriteMode; - /* SetReadMode parameter. */ - struct - { - uint16_t readInterfaceTimingTrim; - uint16_t readControllerTimingTrim; - uint8_t readWaitStates; - uint8_t reserved[3]; - } setReadMode; -} flash_mode_config_t; - -/*! @brief Flash controller paramter config. */ -typedef struct _flash_ffr_config -{ - uint32_t ffrBlockBase; - uint32_t ffrTotalSize; - uint32_t ffrPageSize; - uint32_t cfpaPageVersion; - uint32_t cfpaPageOffset; -} flash_ffr_config_t; - -/*! @brief Flash driver state information. - * - * An instance of this structure is allocated by the user of the flash driver and - * passed into each of the driver APIs. - */ -typedef struct _flash_config -{ - uint32_t PFlashBlockBase; /*!< A base address of the first PFlash block */ - uint32_t PFlashTotalSize; /*!< The size of the combined PFlash block. */ - uint32_t PFlashBlockCount; /*!< A number of PFlash blocks. */ - uint32_t PFlashPageSize; /*!< The size in bytes of a page of PFlash. */ - uint32_t PFlashSectorSize; /*!< The size in bytes of a sector of PFlash. */ - flash_ffr_config_t ffrConfig; - flash_mode_config_t modeConfig; -} flash_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization - * @{ - */ - -/*! - * @brief Initializes the global flash properties structure members. - * - * This function checks and initializes the Flash module for the other Flash APIs. - * - * @param config Pointer to the storage for the driver runtime state. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_Init(flash_config_t *config); - -/*@}*/ - -/*! - * @name Erasing - * @{ - */ - -/*! - * @brief Erases the flash sectors encompassed by parameters passed into function. - * - * This function erases the appropriate number of flash sectors based on the - * desired start address and length. - * - * @param config The pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be erased. - * The start address need to be 512bytes-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words) - * to be erased. Must be 512bytes-aligned. - * @param key The value used to validate all flash erase APIs. - * - * @retval #kStatus_FLASH_Success API was executed successfully; - * the appropriate number of flash sectors based on the desired - * start address and length were erased successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_AddressError The address is out of range. - * @retval #kStatus_FLASH_EraseKeyError The API erase key is invalid. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - -/*@}*/ - -/*! - * @name Programming - * @{ - */ - -/*! - * @brief Programs flash with data at locations passed in through parameters. - * - * This function programs the flash memory with the desired data for a given - * flash area as determined by the start address and the length. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be programmed. Must be - * 512bytes-aligned. - * @param src A pointer to the source buffer of data that is to be programmed - * into the flash. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be programmed. Must be 512bytes-aligned. - * - * @retval #kStatus_FLASH_Success API was executed successfully; the desired data were programed successfully - * into flash based on desired start address and length. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); - -/*@}*/ - -/*! - * @brief Reads flash at locations passed in through parameters. - * - * This function read the flash memory from a given flash area as determined - * by the start address and the length. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be read. - * @param dest A pointer to the dest buffer of data that is to be read - * from the flash. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be read. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); - -/*! - * @name Verification - * @{ - */ - -/*! - * @brief Verifies an erasure of the desired flash area at a specified margin level. - * - * This function checks the appropriate number of flash sectors based on - * the desired start address and length to check whether the flash is erased - * to the specified read margin level. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be verified. - * The start address need to be 512bytes-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be verified. Must be 512bytes-aligned. - * - * @retval #kStatus_FLASH_Success API was executed successfully; the specified FLASH region has been erased. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); - -/*! - * @brief Verifies programming of the desired flash area at a specified margin level. - * - * This function verifies the data programed in the flash memory using the - * Flash Program Check Command and compares it to the expected data for a given - * flash area as determined by the start address and length. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be verified. need be 512bytes-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be verified. need be 512bytes-aligned. - * @param expectedData A pointer to the expected data that is to be - * verified against. - * @param failedAddress A pointer to the returned failing address. - * @param failedData A pointer to the returned failing data. Some derivatives do - * not include failed data as part of the FCCOBx registers. In this - * case, zeros are returned upon failure. - * - * @retval #kStatus_FLASH_Success API was executed successfully; - * the desired data have been successfully programed into specified FLASH region. - * - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_VerifyProgram(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - -/*@}*/ - -/*! - * @name Properties - * @{ - */ - -/*! - * @brief Returns the desired flash property. - * - * @param config A pointer to the storage for the driver runtime state. - * @param whichProperty The desired property from the list of properties in - * enum flash_property_tag_t - * @param value A pointer to the value returned for the desired flash property. - * - * @retval #kStatus_FLASH_Success API was executed successfully; the flash property was stored to value. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_UnknownProperty An unknown property tag. - */ -status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); - -/*@}*/ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* __FLASH_FLASH_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_iap_ffr.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_iap_ffr.h deleted file mode 100644 index 9481e07af14..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_iap_ffr.h +++ /dev/null @@ -1,388 +0,0 @@ -/* - * Copyright 2018-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __FSL_IAP_FFR_H_ -#define __FSL_IAP_FFR_H_ - -#include "fsl_iap.h" - -/*! - * @addtogroup flash_ifr_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! - * @name Flash IFR version - * @{ - */ -/*! @brief Flash IFR driver version for SDK*/ -#define FSL_FLASH_IFR_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ -/*@}*/ - -/*! @brief Alignment(down) utility. */ -#if !defined(ALIGN_DOWN) -#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) -#endif - -/*! @brief Alignment(up) utility. */ -#if !defined(ALIGN_UP) -#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) -#endif - -#define FLASH_FFR_MAX_PAGE_SIZE (512u) -#define FLASH_FFR_HASH_DIGEST_SIZE (32u) -#define FLASH_FFR_IV_CODE_SIZE (52u) - -/*! @brief flash ffr page offset. */ -enum _flash_ffr_page_offset -{ - kFfrPageOffset_CFPA = 0, /*!< Customer In-Field programmed area*/ - kFfrPageOffset_CFPA_Scratch = 0, /*!< CFPA Scratch page */ - kFfrPageOffset_CFPA_Cfg = 1, /*!< CFPA Configuration area (Ping page)*/ - kFfrPageOffset_CFPA_CfgPong = 2, /*!< Same as CFPA page (Pong page)*/ - - kFfrPageOffset_CMPA = 3, /*!< Customer Manufacturing programmed area*/ - kFfrPageOffset_CMPA_Cfg = 3, /*!< CMPA Configuration area (Part of CMPA)*/ - kFfrPageOffset_CMPA_Key = 4, /*!< Key Store area (Part of CMPA)*/ - - kFfrPageOffset_NMPA = 7, /*!< NXP Manufacturing programmed area*/ - kFfrPageOffset_NMPA_Romcp = 7, /*!< ROM patch area (Part of NMPA)*/ - kFfrPageOffset_NMPA_Repair = 9, /*!< Repair area (Part of NMPA)*/ - kFfrPageOffset_NMPA_Cfg = 15, /*!< NMPA configuration area (Part of NMPA)*/ - kFfrPageOffset_NMPA_End = 16, /*!< Reserved (Part of NMPA)*/ -}; - -/*! @brief flash ffr page number. */ -enum _flash_ffr_page_num -{ - kFfrPageNum_CFPA = 3, /*!< Customer In-Field programmed area*/ - kFfrPageNum_CMPA = 4, /*!< Customer Manufacturing programmed area*/ - kFfrPageNum_NMPA = 10, /*!< NXP Manufacturing programmed area*/ - - kFfrPageNum_CMPA_Cfg = 1, - kFfrPageNum_CMPA_Key = 3, - kFfrPageNum_NMPA_Romcp = 2, - - kFfrPageNum_SpecArea = kFfrPageNum_CFPA + kFfrPageNum_CMPA, - kFfrPageNum_Total = (kFfrPageNum_CFPA + kFfrPageNum_CMPA + kFfrPageNum_NMPA), -}; - -enum _flash_ffr_block_size -{ - kFfrBlockSize_Key = 52u, - kFfrBlockSize_ActivationCode = 1192u, -}; - -typedef enum _cfpa_cfg_cmpa_prog_process -{ - kFfrCmpaProgProcess_Pre = 0x0u, - kFfrCmpaProgProcess_Post = 0xFFFFFFFFu, -} cmpa_prog_process_t; - -typedef struct _cfpa_cfg_iv_code -{ - uint32_t keycodeHeader; - uint8_t reserved[FLASH_FFR_IV_CODE_SIZE]; -} cfpa_cfg_iv_code_t; - -typedef struct _cfpa_cfg_info -{ - uint32_t header; /*!< [0x000-0x003] */ - uint32_t version; /*!< [0x004-0x007 */ - uint32_t secureFwVersion; /*!< [0x008-0x00b */ - uint32_t nsFwVersion; /*!< [0x00c-0x00f] */ - uint32_t imageKeyRevoke; /*!< [0x010-0x013] */ - uint8_t reserved0[4]; /*!< [0x014-0x017] */ - uint32_t rotkhRevoke; /*!< [0x018-0x01b] */ - uint32_t vendorUsage; /*!< [0x01c-0x01f] */ - uint32_t dcfgNsPin; /*!< [0x020-0x013] */ - uint32_t dcfgNsDflt; /*!< [0x024-0x017] */ - uint32_t enableFaMode; /*!< [0x028-0x02b] */ - uint8_t reserved1[4]; /*!< [0x02c-0x02f] */ - cfpa_cfg_iv_code_t ivCodePrinceRegion[3]; /*!< [0x030-0x0d7] */ - uint8_t reserved2[264]; /*!< [0x0d8-0x1df] */ - uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */ -} cfpa_cfg_info_t; - -#define FFR_BOOTCFG_BOOTSPEED_MASK (0x18U) -#define FFR_BOOTCFG_BOOTSPEED_SHIFT (7U) -#define FFR_BOOTCFG_BOOTSPEED_48MHZ (0x0U) -#define FFR_BOOTCFG_BOOTSPEED_96MHZ (0x1U) - -#define FFR_USBID_VENDORID_MASK (0xFFFFU) -#define FFR_USBID_VENDORID_SHIFT (0U) -#define FFR_USBID_PRODUCTID_MASK (0xFFFF0000U) -#define FFR_USBID_PRODUCTID_SHIFT (16U) - -typedef struct _cmpa_cfg_info -{ - uint32_t bootCfg; /*!< [0x000-0x003] */ - uint32_t spiFlashCfg; /*!< [0x004-0x007] */ - struct - { - uint16_t vid; - uint16_t pid; - } usbId; /*!< [0x008-0x00b] */ - uint32_t sdioCfg; /*!< [0x00c-0x00f] */ - uint32_t dcfgPin; /*!< [0x010-0x013] */ - uint32_t dcfgDflt; /*!< [0x014-0x017] */ - uint32_t dapVendorUsage; /*!< [0x018-0x01b] */ - uint32_t secureBootCfg; /*!< [0x01c-0x01f] */ - uint32_t princeBaseAddr; /*!< [0x020-0x023] */ - uint32_t princeSr[3]; /*!< [0x024-0x02f] */ - uint8_t reserved0[32]; /*!< [0x030-0x04f] */ - uint32_t rotkh[8]; /*!< [0x050-0x06f] */ - uint8_t reserved1[368]; /*!< [0x070-0x1df] */ - uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */ -} cmpa_cfg_info_t; - -typedef struct _cmpa_key_store_header -{ - uint32_t header; - uint8_t reserved[4]; -} cmpa_key_store_header_t; - -#define FFR_SYSTEM_SPEED_CODE_MASK (0x3U) -#define FFR_SYSTEM_SPEED_CODE_SHIFT (0U) -#define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ (0x0U) -#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_24MHZ (0x1U) -#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_48MHZ (0x2U) -#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_96MHZ (0x3U) - -#define FFR_PERIPHERALCFG_PERI_MASK (0x7FFFFFFFU) -#define FFR_PERIPHERALCFG_PERI_SHIFT (0U) -#define FFR_PERIPHERALCFG_COREEN_MASK (0x10000000U) -#define FFR_PERIPHERALCFG_COREEN_SHIFT (31U) - -typedef struct _nmpa_cfg_info -{ - uint16_t fro32kCfg; /*!< [0x000-0x001] */ - uint8_t reserved0[6]; /*!< [0x002-0x007] */ - uint8_t sysCfg; /*!< [0x008-0x008] */ - uint8_t reserved1[7]; /*!< [0x009-0x00f] */ - struct - { - uint32_t data; - uint32_t reserved[3]; - } GpoInitData[3]; /*!< [0x010-0x03f] */ - uint32_t GpoDataChecksum[4]; /*!< [0x040-0x04f] */ - uint32_t finalTestBatchId[4]; /*!< [0x050-0x05f] */ - uint32_t deviceType; /*!< [0x060-0x063] */ - uint32_t finalTestProgVersion; /*!< [0x064-0x067] */ - uint32_t finalTestDate; /*!< [0x068-0x06b] */ - uint32_t finalTestTime; /*!< [0x06c-0x06f] */ - uint32_t uuid[4]; /*!< [0x070-0x07f] */ - uint8_t reserved2[32]; /*!< [0x080-0x09f] */ - uint32_t peripheralCfg; /*!< [0x0a0-0x0a3] */ - uint32_t ramSizeCfg; /*!< [0x0a4-0x0a7] */ - uint32_t flashSizeCfg; /*!< [0x0a8-0x0ab] */ - uint8_t reserved3[36]; /*!< [0x0ac-0x0cf] */ - uint8_t fro1mCfg; /*!< [0x0d0-0x0d0] */ - uint8_t reserved4[15]; /*!< [0x0d1-0x0df] */ - uint32_t dcdc[4]; /*!< [0x0e0-0x0ef] */ - uint32_t bod; /*!< [0x0f0-0x0f3] */ - uint8_t reserved5[12]; /*!< [0x0f4-0x0ff] */ - uint8_t calcHashReserved[192]; /*!< [0x100-0x1bf] */ - uint8_t sha256[32]; /*!< [0x1c0-0x1df] */ - uint32_t ecidBackup[4]; /*!< [0x1e0-0x1ef] */ - uint32_t pageChecksum[4]; /*!< [0x1f0-0x1ff] */ -} nmpa_cfg_info_t; - -typedef struct _ffr_key_store -{ - uint8_t reserved[3][FLASH_FFR_MAX_PAGE_SIZE]; -} ffr_key_store_t; - -typedef enum _ffr_key_type -{ - kFFR_KeyTypeSbkek = 0x00U, - kFFR_KeyTypeUser = 0x01U, - kFFR_KeyTypeUds = 0x02U, - kFFR_KeyTypePrinceRegion0 = 0x03U, - kFFR_KeyTypePrinceRegion1 = 0x04U, - kFFR_KeyTypePrinceRegion2 = 0x05U, -} ffr_key_type_t; - -typedef enum _ffr_bank_type -{ - kFFR_BankTypeBank0_NMPA = 0x00U, - kFFR_BankTypeBank1_CMPA = 0x01U, - kFFR_BankTypeBank2_CFPA = 0x02U -} ffr_bank_type_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name FFR APIs - * @{ - */ - -/*! - * @brief Initializes the global FFR properties structure members. - * - * @param config A pointer to the storage for the driver runtime state. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - */ -status_t FFR_Init(flash_config_t *config); - -/*! - * @brief Enable firewall for all flash banks. - * - * CFPA, CMPA, and NMPA flash areas region will be locked, After this function executed; - * Unless the board is reset again. - * - * @param config A pointer to the storage for the driver runtime state. - * - * @retval #kStatus_FLASH_Success An invalid argument is provided. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - */ -status_t FFR_Lock_All(flash_config_t *config); - -/*! - * @brief APIs to access CFPA pages - * - * This routine will erase CFPA and program the CFPA page with passed data. - * - * @param config A pointer to the storage for the driver runtime state. - * @param page_data A pointer to the source buffer of data that is to be programmed - * into the CFPA. - * @param valid_len The length, given in bytes, to be programmed. - * - * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CFPA. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_FfrBankIsLocked The CFPA was locked. - * @retval #kStatus_FLASH_OutOfDateCfpaPage It is not newest CFPA page. - */ -status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); - -/*! - * @brief APIs to access CFPA pages - * - * Generic read function, used by customer to read data stored in 'Customer In-field Page'. - * - * @param config A pointer to the storage for the driver runtime state. - * @param pData A pointer to the dest buffer of data that is to be read from 'Customer In-field Page'. - * @param offset An offset from the 'Customer In-field Page' start address. - * @param len The length, given in bytes, to be read. - * - * @retval #kStatus_FLASH_Success Get data from 'Customer In-field Page'. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_CommandFailure access error. - */ -status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - -/*! - * @brief APIs to access CMPA pages - * - * This routine will erase "customer factory page" and program the page with passed data. - * If 'seal_part' parameter is TRUE then the routine will compute SHA256 hash of - * the page contents and then programs the pages. - * 1.During development customer code uses this API with 'seal_part' set to FALSE. - * 2.During manufacturing this parameter should be set to TRUE to seal the part - * from further modifications - * 3.This routine checks if the page is sealed or not. A page is said to be sealed if - * the SHA256 value in the page has non-zero value. On boot ROM locks the firewall for - * the region if hash is programmed anyways. So, write/erase commands will fail eventually. - * - * @param config A pointer to the storage for the driver runtime state. - * @param page_data A pointer to the source buffer of data that is to be programmed - * into the "customer factory page". - * @param seal_part Set fasle for During development customer code. - * - * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CMPA. - * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. - * @retval kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_CommandFailure access error. - */ -status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part); - -/*! - * @brief APIs to access CMPA page - * - * Read data stored in 'Customer Factory CFG Page'. - * - * @param config A pointer to the storage for the driver runtime state. - * @param pData A pointer to the dest buffer of data that is to be read - * from the Customer Factory CFG Page. - * @param offset Address offset relative to the CMPA area. - * @param len The length, given in bytes to be read. - * - * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. - * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. - * @retval kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_CommandFailure access error. - */ -status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - -/*! - * @brief APIs to access CMPA page - * - * 1.SW should use this API routine to get the UUID of the chip. - * 2.Calling routine should pass a pointer to buffer which can hold 128-bit value. - */ -status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid); - -/*! - * @brief This routine writes the 3 pages allocated for Key store data, - * - * 1.Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state. - * 2.Optional routines to set individual data members (activation code, key codes etc) to construct - * the key store structure in RAM before committing it to IFR/FFR. - * - * @param config A pointer to the storage for the driver runtime state. - * @param pKeyStore A Pointer to the 3 pages allocated for Key store data. - * that will be written to 'customer factory page'. - * - * @retval #kStatus_FLASH_Success The key were programed successfully into FFR. - * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. - * @retval kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_CommandFailure access error. - */ -status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore); - -/*! - * @brief Get/Read Key store code routines - * - * 1. Calling code should pass buffer pointer which can hold activation code 1192 bytes. - * 2. Check if flash aperture is small or regular and read the data appropriately. - */ -status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode); - -/*! - * @brief Get/Read Key store code routines - * - * 1. Calling code should pass buffer pointer which can hold key code 52 bytes. - * 2. Check if flash aperture is small or regular and read the data appropriately. - * 3. keyIndex specifies which key code is read. - */ -status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); - -/*@}*/ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /*! __FSL_FLASH_FFR_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_iap_kbp.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_iap_kbp.h deleted file mode 100644 index 453a89a8fde..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_iap_kbp.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * Copyright (c) 2020-2021, Freescale Semiconductor, Inc. - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_IAP_KBP_H_ -#define _FSL_IAP_KBP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup kb_driver - * @{ - */ -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @brief ROM API status group number */ -#define kStatusGroup_RomApi (108U) - -/*! @brief ROM API status codes. */ -enum -{ - kStatus_RomApiExecuteCompleted = kStatus_Success, /*!< ROM successfully process the whole sb file/boot image.*/ - kStatus_RomApiNeedMoreData = - MAKE_STATUS(kStatusGroup_RomApi, 1), /*!< ROM needs more data to continue processing the boot image.*/ - kStatus_RomApiBufferSizeNotEnough = - MAKE_STATUS(kStatusGroup_RomApi, - 2), /*!< The user buffer is not enough for use by Kboot during execution of the operation.*/ - kStatus_RomApiInvalidBuffer = - MAKE_STATUS(kStatusGroup_RomApi, 3), /*!< The user buffer is not ok for sbloader or authentication.*/ -}; - -/*! - * @brief Details of the operation to be performed by the ROM. - * - * The #kRomAuthenticateImage operation requires the entire signed image to be - * available to the application. - */ -typedef enum _kb_operation -{ - kRomAuthenticateImage = 1, /*!< Authenticate a signed image.*/ - kRomLoadImage = 2, /*!< Load SB file.*/ - kRomOperationCount = 3, -} kb_operation_t; - -/*! - * @brief Security constraint flags, Security profile flags. - */ -enum _kb_security_profile -{ - kKbootMinRSA4096 = (1 << 16), -}; - -/*! - * @brief Memory region definition. - */ -typedef struct _kb_region -{ - uint32_t address; - uint32_t length; -} kb_region_t; - -/*! - * @brief User-provided options passed into kb_init(). - * - * The buffer field is a pointer to memory provided by the caller for use by - * Kboot during execution of the operation. Minimum size is the size of each - * certificate in the chain plus 432 bytes additional per certificate. - * - * The profile field is a mask that specifies which features are required in - * the SB file or image being processed. This includes the minimum AES and RSA - * key sizes. See the _kb_security_profile enum for profile mask constants. - * The image being loaded or authenticated must match the profile or an error will - * be returned. - * - * minBuildNumber is an optional field that can be used to prevent version - * rollback. The API will check the build number of the image, and if it is less - * than minBuildNumber will fail with an error. - * - * maxImageLength is used to verify the offsetToCertificateBlockHeaderInBytes - * value at the beginning of a signed image. It should be set to the length of - * the SB file. If verifying an image in flash, it can be set to the internal - * flash size or a large number like 0x10000000. - * - * userRHK can optionally be used by the user to override the RHK in IFR. If - * userRHK is not NULL, it points to a 32-byte array containing the SHA-256 of - * the root certificate's RSA public key. - * - * The regions field points to an array of memory regions that the SB file being - * loaded is allowed to access. If regions is NULL, then all memory is - * accessible by the SB file. This feature is required to prevent a malicious - * image from erasing good code or RAM contents while it is being loaded, only - * for us to find that the image is inauthentic when we hit the end of the - * section. - * - * overrideSBBootSectionID lets the caller override the default section of the - * SB file that is processed during a kKbootLoadSB operation. By default, - * the section specified in the firstBootableSectionID field of the SB header - * is loaded. If overrideSBBootSectionID is non-zero, then the section with - * the given ID will be loaded instead. - * - * The userSBKEK field lets a user provide their own AES-256 key for unwrapping - * keys in an SB file during the kKbootLoadSB operation. userSBKEK should point - * to a 32-byte AES-256 key. If userSBKEK is NULL then the IFR SBKEK will be used. - * After kb_init() returns, the caller should zero out the data pointed to by - * userSBKEK, as the API will have installed the key in the CAU3. - */ - -typedef struct _kb_load_sb -{ - uint32_t profile; - uint32_t minBuildNumber; - uint32_t overrideSBBootSectionID; - uint32_t *userSBKEK; - uint32_t regionCount; - const kb_region_t *regions; -} kb_load_sb_t; - -typedef struct _kb_authenticate -{ - uint32_t profile; - uint32_t minBuildNumber; - uint32_t maxImageLength; - uint32_t *userRHK; -} kb_authenticate_t; - -typedef struct _kb_options -{ - uint32_t version; /*!< Should be set to kKbootApiVersion.*/ - uint8_t *buffer; /*!< Caller-provided buffer used by Kboot.*/ - uint32_t bufferLength; - kb_operation_t op; - union - { - kb_authenticate_t authenticate; /*! Settings for kKbootAuthenticate operation.*/ - kb_load_sb_t loadSB; /*! Settings for kKbootLoadSB operation.*/ - }; -} kb_options_t; - -/*! - * @brief Interface to memory operations for one region of memory. - */ -typedef struct _memory_region_interface -{ - status_t (*init)(void); - status_t (*read)(uint32_t address, uint32_t length, uint8_t *buffer); - status_t (*write)(uint32_t address, uint32_t length, const uint8_t *buffer); - status_t (*fill)(uint32_t address, uint32_t length, uint32_t pattern); - status_t (*flush)(void); - status_t (*erase)(uint32_t address, uint32_t length); - status_t (*config)(uint32_t *buffer); - status_t (*erase_all)(void); -} memory_region_interface_t; - -/*! - * @brief Structure of a memory map entry. - */ -typedef struct _memory_map_entry -{ - uint32_t startAddress; - uint32_t endAddress; - uint32_t memoryProperty; - uint32_t memoryId; - const memory_region_interface_t *memoryInterface; -} memory_map_entry_t; - -typedef struct _kb_opaque_session_ref -{ - kb_options_t context; - bool cau3Initialized; - memory_map_entry_t *memoryMap; -} kb_session_ref_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize ROM API for a given operation. - * - * Inits the ROM API based on the options provided by the application in the second - * argument. Every call to rom_init() should be paired with a call to rom_deinit(). - * - * @retval #kStatus_Success API was executed successfully. - * @retval #kStatus_InvalidArgument An invalid argument is provided. - * @retval #kStatus_RomApiBufferSizeNotEnough The user buffer is not enough for use by Kboot during execution of the - * operation. - * @retval #kStatus_RomApiInvalidBuffer The user buffer is not ok for sbloader or authentication. - * @retval #kStatus_SKBOOT_Fail Return the failed status of secure boot. - * @retval #kStatus_SKBOOT_KeyStoreMarkerInvalid The key code for the particular PRINCE region is not present in the - * keystore - * @retval #kStatus_SKBOOT_Success Return the successful status of secure boot. - */ -status_t kb_init(kb_session_ref_t **session, const kb_options_t *options); - -/*! - * @brief Cleans up the ROM API context. - * - * After this call, the context parameter can be reused for another operation - * by calling rom_init() again. - * - * @retval #kStatus_Success API was executed successfully - */ -status_t kb_deinit(kb_session_ref_t *session); - -/*! - * Perform the operation configured during init. - * - * This application must call this API repeatedly, passing in sequential chunks of - * data from the boot image (SB file) that is to be processed. The ROM will perform - * the selected operation on this data and return. The application may call this - * function with as much or as little data as it wishes, which can be used to select - * the granularity of time given to the application in between executing the operation. - * - * @param session Current ROM context pointer. - * @param data Buffer of boot image data provided to the ROM by the application. - * @param dataLength Length in bytes of the data in the buffer provided to the ROM. - * - * @retval #kStatus_Success ROM successfully process the part of sb file/boot image. - * @retval #kStatus_RomApiExecuteCompleted ROM successfully process the whole sb file/boot image. - * @retval #kStatus_Fail An error occurred while executing the operation. - * @retval #kStatus_RomApiNeedMoreData No error occurred, but the ROM needs more data to - * continue processing the boot image. - * @retval #kStatus_RomApiBufferSizeNotEnough user buffer is not enough for - * use by Kboot during execution of the operation. - */ -status_t kb_execute(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength); - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_IAP_KBP_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_iap_skboot_authenticate.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_iap_skboot_authenticate.h deleted file mode 100644 index 67a513bc3cf..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_iap_skboot_authenticate.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _FSL_IAP_SKBOOT_AUTHENTICATE_H_ -#define _FSL_IAP_SKBOOT_AUTHENTICATE_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup skboot_authenticate - * @{ - */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @brief SKBOOT return status*/ -typedef enum _skboot_status -{ - kStatus_SKBOOT_Success = 0x5ac3c35au, /*!< SKBOOT return success status.*/ - kStatus_SKBOOT_Fail = 0xc35ac35au, /*!< SKBOOT return fail status.*/ - kStatus_SKBOOT_InvalidArgument = 0xc35a5ac3u, /*!< SKBOOT return invalid argument status.*/ - kStatus_SKBOOT_KeyStoreMarkerInvalid = 0xc3c35a5au, /*!< SKBOOT return Keystore invalid Marker status.*/ - kStatus_SKBOOT_HashcryptFinishedWithStatusSuccess = - 0xc15a5ac3, /*!< SKBOOT return Hashcrypt finished with the success status.*/ - kStatus_SKBOOT_HashcryptFinishedWithStatusFail = - 0xc15a5acb, /*!< SKBOOT return Hashcrypt finished with the fail status.*/ -} skboot_status_t; - -/*! @brief Secure bool flag*/ -typedef enum _secure_bool -{ - kSECURE_TRUE = 0xc33cc33cU, /*!< Secure true flag.*/ - kSECURE_FALSE = 0x5aa55aa5U, /*!< Secure false flag.*/ - kSECURE_CALLPROTECT_SECURITY_FLAGS = 0xc33c5aa5U, /*!< Secure call protect the security flag.*/ - kSECURE_CALLPROTECT_IS_APP_READY = 0x5aa5c33cU, /*!< Secure call protect the app is ready flag.*/ - kSECURE_TRACKER_VERIFIED = 0x55aacc33U, /*!< Secure tracker verified flag.*/ -} secure_bool_t; - -/******************************************************************************* - * Externs - ******************************************************************************/ - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Authenticate entry function with ARENA allocator init - * - * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface - */ -skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified); - -/*! - * @brief Interface for image authentication API - */ -void HASH_IRQHandler(void); - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_IAP_SKBOOT_AUTHENTICATE_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_inputmux.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_inputmux.c deleted file mode 100644 index 5ef935985fb..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_inputmux.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_inputmux.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.inputmux" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Initialize INPUTMUX peripheral. - - * This function enables the INPUTMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * - * retval None. - */ -void INPUTMUX_Init(INPUTMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE - CLOCK_EnableClock(kCLOCK_Sct); - CLOCK_EnableClock(kCLOCK_Dma); -#else - CLOCK_EnableClock(kCLOCK_InputMux); -#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Attaches a signal - * - * This function gates the INPUTPMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * param index Destination peripheral to attach the signal to. - * param connection Selects connection. - * - * retval None. - */ -void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection) -{ - uint32_t pmux_id; - uint32_t output_id; - - /* extract pmux to be used */ - pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT; - /* extract function number */ - output_id = ((uint32_t)(connection)) & ((1UL << PMUX_SHIFT) - 1U); - /* programm signal */ - *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4U)) = output_id; -} - -#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) -/*! - * brief Enable/disable a signal - * - * This function gates the INPUTPMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * param signal Enable signal register id and bit offset. - * param enable Selects enable or disable. - * - * retval None. - */ -void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable) -{ - uint32_t ena_id; - uint32_t ena_id_mask = (1UL << (32U - ENA_SHIFT)) - 1U; - uint32_t bit_offset; - -#if defined(FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX) && FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX - uint32_t chmux_offset; - uint32_t chmux_value; - - /* Only enable need to update channel mux */ - if (enable && ((((uint32_t)signal) & (1UL << CHMUX_AVL_SHIFT)) != 0U)) - { - chmux_offset = (((uint32_t)signal) >> CHMUX_OFF_SHIFT) & ((1UL << (CHMUX_AVL_SHIFT - CHMUX_OFF_SHIFT)) - 1UL); - chmux_value = (((uint32_t)signal) >> CHMUX_VAL_SHIFT) & ((1UL << (CHMUX_OFF_SHIFT - CHMUX_VAL_SHIFT)) - 1UL); - *(volatile uint32_t *)(((uint32_t)base) + chmux_offset) = chmux_value; - } - ena_id_mask = (1UL << (CHMUX_VAL_SHIFT - ENA_SHIFT)) - 1U; -#endif - /* extract enable register to be used */ - ena_id = (((uint32_t)signal) >> ENA_SHIFT) & ena_id_mask; - /* extract enable bit offset */ - bit_offset = ((uint32_t)signal) & ((1UL << ENA_SHIFT) - 1U); - /* set signal */ - if (enable) - { - *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1UL << bit_offset); - } - else - { - *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1UL << bit_offset); - } -} -#endif - -/*! - * brief Deinitialize INPUTMUX peripheral. - - * This function disables the INPUTMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * - * retval None. - */ -void INPUTMUX_Deinit(INPUTMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE - CLOCK_DisableClock(kCLOCK_Sct); - CLOCK_DisableClock(kCLOCK_Dma); -#else - CLOCK_DisableClock(kCLOCK_InputMux); -#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_inputmux.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_inputmux.h deleted file mode 100644 index ddb9e26c55f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_inputmux.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_INPUTMUX_H_ -#define _FSL_INPUTMUX_H_ - -#include "fsl_inputmux_connections.h" -#include "fsl_common.h" - -/*! - * @addtogroup inputmux_driver - * @{ - */ - -/*! @file */ -/*! @file fsl_inputmux_connections.h */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Group interrupt driver version for SDK */ -#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) -/*@}*/ - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @brief Initialize INPUTMUX peripheral. - - * This function enables the INPUTMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * - * @retval None. - */ -void INPUTMUX_Init(INPUTMUX_Type *base); - -/*! - * @brief Attaches a signal - * - * This function gates the INPUTPMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * @param index Destination peripheral to attach the signal to. - * @param connection Selects connection. - * - * @retval None. - */ -void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection); - -#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) -/*! - * @brief Enable/disable a signal - * - * This function gates the INPUTPMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * @param signal Enable signal register id and bit offset. - * @param enable Selects enable or disable. - * - * @retval None. - */ -void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable); -#endif - -/*! - * @brief Deinitialize INPUTMUX peripheral. - - * This function disables the INPUTMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * - * @retval None. - */ -void INPUTMUX_Deinit(INPUTMUX_Type *base); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_INPUTMUX_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_inputmux_connections.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_inputmux_connections.h deleted file mode 100644 index dc1c5284d02..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_inputmux_connections.h +++ /dev/null @@ -1,469 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_INPUTMUX_CONNECTIONS_ -#define _FSL_INPUTMUX_CONNECTIONS_ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" -#endif - -/*! - * @addtogroup inputmux_driver - * @{ - */ - -/*! - * @name Input multiplexing connections - * @{ - */ - -/*! @brief Periphinmux IDs */ -#define SCT0_INMUX0 0x00U -#define TIMER0CAPTSEL0 0x20U -#define TIMER1CAPTSEL0 0x40U -#define TIMER2CAPTSEL0 0x60U -#define PINTSEL_PMUX_ID 0xC0U -#define PINTSEL0 0xC0U -#define DMA0_ITRIG_INMUX0 0xE0U -#define DMA0_OTRIG_INMUX0 0x160U -#define FREQMEAS_REF_REG 0x180U -#define FREQMEAS_TARGET_REG 0x184U -#define TIMER3CAPTSEL0 0x1A0U -#define TIMER4CAPTSEL0 0x1C0U -#define PINTSECSEL0 0x1E0U -#define DMA1_ITRIG_INMUX0 0x200U -#define DMA1_OTRIG_INMUX0 0x240U -#define DMA0_REQ_ENA_ID 0x740U -#define DMA1_REQ_ENA_ID 0x760U -#define DMA0_ITRIG_ENA_ID 0x780U -#define DMA1_ITRIG_ENA_ID 0x7A0U -#define ENA_SHIFT 8U -#define PMUX_SHIFT 20U - -/*! @brief INPUTMUX connections type */ -typedef enum _inputmux_connection_t -{ - /*!< SCT0 INMUX. */ - kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToSct0 = 8U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToSct0 = 9U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToSct0 = 10U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToSct0 = 11U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToSct0 = 12U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_AdcIrqToSct0 = 13U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToSct0 = 14U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_CompOutToSct0 = 17U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedSck0ToSct0 = 18U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedSck1ToSct0 = 19U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToSct0 = 20U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToSct0 = 21U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_ArmTxevToSct0 = 22U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_DebugHaltedToSct0 = 23U + (SCT0_INMUX0 << PMUX_SHIFT), - - /*!< TIMER0 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer0Captsel = 0U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - - /*!< TIMER1 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer1Captsel = 0U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - - /*!< TIMER2 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer2Captsel = 0U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - - /*!< Pin interrupt select. */ - kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL0 << PMUX_SHIFT), - - /*!< DMA0 Input trigger. */ - kINPUTMUX_PinInt0ToDma0 = 0U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt1ToDma0 = 1U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt2ToDma0 = 2U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt3ToDma0 = 3U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToDma0 = 4U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M1ToDma0 = 5U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToDma0 = 6U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M1ToDma0 = 7U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToDma0 = 8U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M1ToDma0 = 9U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToDma0 = 10U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M1ToDma0 = 11U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToDma0 = 12U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M1ToDma0 = 13U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_CompOutToDma0 = 14U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig0ToDma0 = 15U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig1ToDma0 = 16U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig2ToDma0 = 17U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig3ToDma0 = 18U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq0ToDma0 = 19U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq1ToDma0 = 20U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_HashDmaRxToDma0 = 21U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - - /*!< DMA0 output trigger. */ - kINPUTMUX_Dma0Hash0TxTrigoutToTriginChannels = 0U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0HsLspiRxTrigoutToTriginChannels = 2U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0HsLspiTxTrigoutToTriginChannels = 3U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm3RxTrigoutToTriginChannels = 8U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm3TxTrigoutToTriginChannels = 9U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm2RxTrigoutToTriginChannels = 10U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm2TxTrigoutToTriginChannels = 11U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm4RxTrigoutToTriginChannels = 12U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm4TxTrigoutToTriginChannels = 13U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm5RxTrigoutToTriginChannels = 14U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm5TxTrigoutToTriginChannels = 15U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm6RxTrigoutToTriginChannels = 16U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm6TxTrigoutToTriginChannels = 17U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm7RxTrigoutToTriginChannels = 18U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm7TxTrigoutToTriginChannels = 19U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Adc0Ch0TrigoutToTriginChannels = 21U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Adc0Ch1TrigoutToTriginChannels = 22U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - - /*!< Selection for frequency measurement reference clock. */ - kINPUTMUX_ExternOscToFreqmeasRef = 0U + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_Fro12MhzToFreqmeasRef = 1u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_Fro96MhzToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_WdtOscToFreqmeasRef = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_32KhzOscToFreqmeasRef = 4u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_MainClkToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_aRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_bRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT), - - /*!< Selection for frequency measurement target clock. */ - kINPUTMUX_ExternOscToFreqmeasTarget = 0U + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_Fro12MhzToFreqmeasTarget = 1u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_Fro96MhzToFreqmeasTarget = 2u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_WdtOscToFreqmeasTarget = 3u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_32KhzOscToFreqmeasTarget = 4u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_MainClkToFreqmeasTarget = 5u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_aTarget = 6u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_bTarget = 7u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - - /*!< TIMER3 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer3Captsel = 0U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - - /*!< Timer4 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer4Captsel = 0U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - - /*Pin interrupt secure select */ - kINPUTMUX_GpioPort0Pin0ToPintSecsel = 0U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin1ToPintSecsel = 1U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin2ToPintSecsel = 2U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin3ToPintSecsel = 3U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin4ToPintSecsel = 4U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin5ToPintSecsel = 5U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin6ToPintSecsel = 6U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin7ToPintSecsel = 7U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin8ToPintSecsel = 8U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin9ToPintSecsel = 9U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin10ToPintSecsel = 10U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin11ToPintSecsel = 11U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin12ToPintSecsel = 12U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin13ToPintSecsel = 13U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin14ToPintSecsel = 14U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin15ToPintSecsel = 15U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin16ToPintSecsel = 16U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin17ToPintSecsel = 17U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin18ToPintSecsel = 18U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin19ToPintSecsel = 19U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin20ToPintSecsel = 20U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin21ToPintSecsel = 21U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin22ToPintSecsel = 22U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin23ToPintSecsel = 23U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin24ToPintSecsel = 24U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin25ToPintSecsel = 25U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin26ToPintSecsel = 26U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin27ToPintSecsel = 27U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin28ToPintSecsel = 28U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin29ToPintSecsel = 29U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin30ToPintSecsel = 30U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin31ToPintSecsel = 31U + (PINTSECSEL0 << PMUX_SHIFT), - - /*!< DMA1 Input trigger. */ - kINPUTMUX_PinInt0ToDma1 = 0U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt1ToDma1 = 1U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt2ToDma1 = 2U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt3ToDma1 = 3U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToDma1 = 4U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M1ToDma1 = 5U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToDma1 = 6U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToDma1 = 7U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig0ToDma1 = 8U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig1ToDma1 = 9U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig2ToDma1 = 10U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig3ToDma1 = 11U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq0ToDma1 = 12U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq1ToDma1 = 13U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_HashDmaRxToDma1 = 14U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - - /*!< DMA1 output trigger. */ - kINPUTMUX_Dma1Hash0TxTrigoutToTriginChannels = 0U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1HsLspiRxTrigoutToTriginChannels = 2U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1HsLspiTxTrigoutToTriginChannels = 3U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm3RxTrigoutToTriginChannels = 8U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm3TxTrigoutToTriginChannels = 9U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), -} inputmux_connection_t; - -/*! @brief INPUTMUX signal enable/disable type */ -typedef enum _inputmux_signal_t -{ - /*!< DMA0 REQ signal. */ - kINPUTMUX_HashCryptToDmac0Ch0RequestEna = 0U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm8RxToDmac0Ch2RequestEna = 2U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm8TxToDmac0Ch3RequestEna = 3U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm0RxToDmac0Ch4RequestEna = 4U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm0TxToDmac0Ch5RequestEna = 5U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm1RxToDmac0Ch6RequestEna = 6U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm1TxToDmac0Ch7RequestEna = 7U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm3RxToDmac0Ch8RequestEna = 8U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm3TxToDmac0Ch9RequestEna = 9U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm2RxToDmac0Ch10RequestEna = 10U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm2TxToDmac0Ch11RequestEna = 11U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm4RxToDmac0Ch12RequestEna = 12U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm4TxToDmac0Ch13RequestEna = 13U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm5RxToDmac0Ch14RequestEna = 14U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm5TxToDmac0Ch15RequestEna = 15U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm6RxToDmac0Ch16RequestEna = 16U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm6TxToDmac0Ch17RequestEna = 17U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm7RxToDmac0Ch18RequestEna = 18U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm7TxToDmac0Ch19RequestEna = 19U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Adc0FIFO0ToDmac0Ch21RequestEna = 21U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Adc0FIFO1ToDmac0Ch22RequestEna = 22U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - - /*!< DMA1 REQ signal. */ - kINPUTMUX_HashCryptToDmac1Ch0RequestEna = 0U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm8RxToDmac1Ch2RequestEna = 2U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm8TxToDmac1Ch3RequestEna = 3U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm0RxToDmac1Ch4RequestEna = 4U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm0TxToDmac1Ch5RequestEna = 5U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm1RxToDmac1Ch6RequestEna = 6U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm1TxToDmac1Ch7RequestEna = 7U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm3RxToDmac1Ch8RequestEna = 8U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm3TxToDmac1Ch9RequestEna = 9U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - - /*!< DMA0 input trigger source enable. */ - kINPUTMUX_Dmac0InputTriggerPint0Ena = 0U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerPint1Ena = 1U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerPint2Ena = 2U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerPint3Ena = 3U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer0M0Ena = 4U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer0M1Ena = 5U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer1M0Ena = 6U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer1M1Ena = 7U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer2M0Ena = 8U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer2M1Ena = 9U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer3M0Ena = 10U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer3M1Ena = 11U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer4M0Ena = 12U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer4M1Ena = 13U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCompOutEna = 14U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerDma0Out0Ena = 15U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerDma0Out1Ena = 16U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerDma0Out2Ena = 17U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerDma0Out3Ena = 18U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerSctDmac0Ena = 19U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerSctDmac1Ena = 20U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerHashOutEna = 21U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - - /*!< DMA1 input trigger source enable. */ - kINPUTMUX_Dmac1InputTriggerPint0Ena = 0U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerPint1Ena = 1U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerPint2Ena = 2U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerPint3Ena = 3U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerCtimer0M0Ena = 4U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerCtimer0M1Ena = 5U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerCtimer2M0Ena = 6U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerCtimer4M0Ena = 7U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerDma1Out0Ena = 8U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerDma1Out1Ena = 9U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerDma1Out2Ena = 10U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerDma1Out3Ena = 11U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerSctDmac0Ena = 12U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerSctDmac1Ena = 13U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerHashOutEna = 14U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), -} inputmux_signal_t; - -/*@}*/ - -/*@}*/ - -#endif /* _FSL_INPUTMUX_CONNECTIONS_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_iocon.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_iocon.h deleted file mode 100644 index e705e91f66c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_iocon.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_IOCON_H_ -#define _FSL_IOCON_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_iocon - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon" -#endif - -/*! @name Driver version */ -/*@{*/ -/*! @brief IOCON driver version. */ -#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) -/*@}*/ - -/** - * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format - */ -typedef struct _iocon_group -{ - uint8_t port; /* Pin port */ - uint8_t pin; /* Pin number */ - uint8_t ionumber; /* IO number */ - uint16_t modefunc; /* Function and mode */ -} iocon_group_t; - -/** - * @brief IOCON function and mode selection definitions - * @note See the User Manual for specific modes and functions supported by the various pins. - */ -#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ -#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ -#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ -#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ -#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ -#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ -#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ -#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ -#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) -#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ -#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ -#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ -#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ -#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ -#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ -#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ -#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ -#endif /* FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH */ - -#if defined(IOCON_PIO_MODE_SHIFT) -#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ -#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ -#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ -#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ -#endif - -#if defined(IOCON_PIO_I2CSLEW_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_MODE (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ -#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */ -#endif - -#if defined(IOCON_PIO_EGP_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_MODE (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ -#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */ -#endif - -#if defined(IOCON_PIO_SLEW_SHIFT) -#define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ -#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ -#endif - -#if defined(IOCON_PIO_INVERT_SHIFT) -#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */ -#endif - -#if defined(IOCON_PIO_DIGIMODE_SHIFT) -#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */ -#define IOCON_DIGITAL_EN \ - (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */ -#endif - -#if defined(IOCON_PIO_FILTEROFF_SHIFT) -#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ -#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ -#endif - -#if defined(IOCON_PIO_I2CDRIVE_SHIFT) -#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ -#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ -#endif - -#if defined(IOCON_PIO_OD_SHIFT) -#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */ -#endif - -#if defined(IOCON_PIO_I2CFILTER_SHIFT) -#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ -#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */ -#endif - -#if defined(IOCON_PIO_ASW_SHIFT) -#define IOCON_AWS_EN (0x1 << IOCON_PIO_ASW_SHIFT) /*!< Enables analog switch function */ -#endif - -#if defined(IOCON_PIO_SSEL_SHIFT) -#define IOCON_SSEL_3V3 (0x0 << IOCON_PIO_SSEL_SHIFT) /*!< 3V3 signaling in I2C mode */ -#define IOCON_SSEL_1V8 (0x1 << IOCON_PIO_SSEL_SHIFT) /*!< 1V8 signaling in I2C mode */ -#endif - -#if defined(IOCON_PIO_ECS_SHIFT) -#define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */ -#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */ -#endif - -#if defined(IOCON_PIO_S_MODE_SHIFT) -#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ -#define IOCON_S_MODE_1CLK \ - (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_2CLK \ - (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_3CLK \ - (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ -#endif - -#if defined(IOCON_PIO_CLK_DIV_SHIFT) -#define IOCON_CLKDIV(div) \ - ((div) \ - << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ -#endif - -#if defined(__cplusplus) -extern "C" { -#endif - -#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) -/** - * @brief Sets I/O Control pin mux - * @param base : The base of IOCON peripheral on the chip - * @param ionumber : GPIO number to mux - * @param modefunc : OR'ed values of type IOCON_* - * @return Nothing - */ -__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc) -{ - base->PIO[ionumber] = modefunc; -} -#else -/** - * @brief Sets I/O Control pin mux - * @param base : The base of IOCON peripheral on the chip - * @param port : GPIO port to mux - * @param pin : GPIO pin to mux - * @param modefunc : OR'ed values of type IOCON_* - * @return Nothing - */ -__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc) -{ - base->PIO[port][pin] = modefunc; -} -#endif - -/** - * @brief Set all I/O Control pin muxing - * @param base : The base of IOCON peripheral on the chip - * @param pinArray : Pointer to array of pin mux selections - * @param arrayLength : Number of entries in pinArray - * @return Nothing - */ -__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength) -{ - uint32_t i; - - for (i = 0; i < arrayLength; i++) - { -#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) - IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc); -#else - IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc); -#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */ - } -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_IOCON_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_lpadc.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_lpadc.c deleted file mode 100644 index 7835e6fc454..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_lpadc.c +++ /dev/null @@ -1,612 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_lpadc.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpadc" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for LPADC module. - * - * @param base LPADC peripheral base address - */ -static uint32_t LPADC_GetInstance(ADC_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to LPADC bases for each instance. */ -static ADC_Type *const s_lpadcBases[] = ADC_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to LPADC clocks for each instance. */ -static const clock_ip_name_t s_lpadcClocks[] = LPADC_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t LPADC_GetInstance(ADC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_lpadcBases); instance++) - { - if (s_lpadcBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_lpadcBases)); - - return instance; -} - -/*! - * brief Initializes the LPADC module. - * - * param base LPADC peripheral base address. - * param config Pointer to configuration structure. See "lpadc_config_t". - */ -void LPADC_Init(ADC_Type *base, const lpadc_config_t *config) -{ - /* Check if the pointer is available. */ - assert(config != NULL); - - uint32_t tmp32 = 0U; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock for LPADC instance. */ - (void)CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the module. */ - LPADC_DoResetConfig(base); -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - LPADC_DoResetFIFO0(base); - LPADC_DoResetFIFO1(base); -#else - LPADC_DoResetFIFO(base); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - - /* Disable the module before setting configuration. */ - LPADC_Enable(base, false); - - /* Configure the module generally. */ - if (config->enableInDozeMode) - { - base->CTRL &= ~ADC_CTRL_DOZEN_MASK; - } - else - { - base->CTRL |= ADC_CTRL_DOZEN_MASK; - } - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS - /* Set calibration average mode. */ - base->CTRL |= ADC_CTRL_CAL_AVGS(config->conversionAverageMode); -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - -/* ADCx_CFG. */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - if (config->enableInternalClock) - { - tmp32 |= ADC_CFG_ADCKEN_MASK; - } -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - if (config->enableVref1LowVoltage) - { - tmp32 |= ADC_CFG_VREF1RNG_MASK; - } -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - if (config->enableAnalogPreliminary) - { - tmp32 |= ADC_CFG_PWREN_MASK; - } - tmp32 |= ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */ - | ADC_CFG_REFSEL(config->referenceVoltageSource) /* Reference voltage. */ - | ADC_CFG_PWRSEL(config->powerLevelMode) /* Power configuration. */ - | ADC_CFG_TPRICTRL(config->triggerPriorityPolicy); /* Trigger priority policy. */ - base->CFG = tmp32; - - /* ADCx_PAUSE. */ - if (config->enableConvPause) - { - base->PAUSE = ADC_PAUSE_PAUSEEN_MASK | ADC_PAUSE_PAUSEDLY(config->convPauseDelay); - } - else - { - base->PAUSE = 0U; - } - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - /* ADCx_FCTRL0. */ - base->FCTRL[0] = ADC_FCTRL_FWMARK(config->FIFO0Watermark); - /* ADCx_FCTRL1. */ - base->FCTRL[1] = ADC_FCTRL_FWMARK(config->FIFO1Watermark); -#else - /* ADCx_FCTRL. */ - base->FCTRL = ADC_FCTRL_FWMARK(config->FIFOWatermark); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - - /* Enable the module after setting configuration. */ - LPADC_Enable(base, true); -} - -/*! - * brief Gets an available pre-defined settings for initial configuration. - * - * This function initializes the converter configuration structure with an available settings. The default values are: - * code - * config->enableInDozeMode = true; - * config->conversionAverageMode = kLPADC_ConversionAverage1; - * config->enableAnalogPreliminary = false; - * config->powerUpDelay = 0x80; - * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - * config->powerLevelMode = kLPADC_PowerLevelAlt1; - * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; - * config->enableConvPause = false; - * config->convPauseDelay = 0U; - * config->FIFO0Watermark = 0U; - * config->FIFO1Watermark = 0U; - * config->FIFOWatermark = 0U; - * endcode - * param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConfig(lpadc_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - config->enableInternalClock = false; -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - config->enableVref1LowVoltage = false; -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - config->enableInDozeMode = true; -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS - /* Set calibration average mode. */ - config->conversionAverageMode = kLPADC_ConversionAverage1; -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - config->enableAnalogPreliminary = false; - config->powerUpDelay = 0x80; - config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - config->powerLevelMode = kLPADC_PowerLevelAlt1; - config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; - config->enableConvPause = false; - config->convPauseDelay = 0U; -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - config->FIFO0Watermark = 0U; - config->FIFO1Watermark = 0U; -#else - config->FIFOWatermark = 0U; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ -} - -/*! - * brief De-initializes the LPADC module. - * - * param base LPADC peripheral base address. - */ -void LPADC_Deinit(ADC_Type *base) -{ - /* Disable the module. */ - LPADC_Enable(base, false); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the clock. */ - (void)CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * brief Get the result in conversion FIFOn. - * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. - * param index Result FIFO index. - * - * return Status whether FIFOn entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index) -{ - assert(result != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - tmp32 = base->RESFIFO[index]; - - if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) - { - return false; /* FIFO is empty. Discard any read from RESFIFO. */ - } - - result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; - result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; - result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; - result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); - - return true; -} -#else -/*! - * brief Get the result in conversion FIFO. - * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFO. - * - * return Status whether FIFO entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result) -{ - assert(result != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - tmp32 = base->RESFIFO; - - if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) - { - return false; /* FIFO is empty. Discard any read from RESFIFO. */ - } - - result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; - result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; - result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; - result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); - - return true; -} -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * brief Configure the conversion trigger source. - * - * Each programmable trigger can launch the conversion command in command buffer. - * - * param base LPADC peripheral base address. - * param triggerId ID for each trigger. Typically, the available value range is from 0. - * param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. - */ -void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config) -{ - assert(triggerId < ADC_TCTRL_COUNT); /* Check if the triggerId is available in this device. */ - assert(config != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - tmp32 = ADC_TCTRL_TCMD(config->targetCommandId) /* Trigger command select. */ - | ADC_TCTRL_TDLY(config->delayPower) /* Trigger delay select. */ - | ADC_TCTRL_TPRI(config->priority) /* Trigger priority setting. */ -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - | ADC_TCTRL_FIFO_SEL_A(config->channelAFIFOSelect) -#if !(defined(FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) && FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) - | ADC_TCTRL_FIFO_SEL_B(config->channelBFIFOSelect) -#endif /* FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - ; - if (config->enableHardwareTrigger) - { - tmp32 |= ADC_TCTRL_HTEN_MASK; - } - - base->TCTRL[triggerId] = tmp32; -} - -/*! - * brief Gets an available pre-defined settings for trigger's configuration. - * - * This function initializes the trigger's configuration structure with an available settings. The default values are: - * code - * config->commandIdSource = 0U; - * config->loopCountIndex = 0U; - * config->triggerIdSource = 0U; - * config->enableHardwareTrigger = false; - * config->channelAFIFOSelect = 0U; - * config->channelBFIFOSelect = 0U; - * endcode - * param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config) -{ - assert(config != NULL); /* Check if the input pointer is available. */ - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->targetCommandId = 0U; - config->delayPower = 0U; - config->priority = 0U; -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - config->channelAFIFOSelect = 0U; - config->channelBFIFOSelect = 0U; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - config->enableHardwareTrigger = false; -} - -/*! - * brief Configure conversion command. - * - * param base LPADC peripheral base address. - * param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. - * param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. - */ -void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config) -{ - assert(commandId < (ADC_CMDL_COUNT + 1U)); /* Check if the commandId is available on this device. */ - assert(config != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32 = 0; - - commandId--; /* The available command number are 1-15, while the index of register group are 0-14. */ - - /* ADCx_CMDL. */ - tmp32 = ADC_CMDL_ADCH(config->channelNumber); /* Channel number. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - tmp32 |= ADC_CMDL_CSCALE(config->sampleScaleMode); /* Full/Part scale input voltage. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE - tmp32 |= ADC_CMDL_CTYPE(config->sampleChannelMode); -#else - switch (config->sampleChannelMode) /* Sample input. */ - { - case kLPADC_SampleChannelSingleEndSideB: - tmp32 |= ADC_CMDL_ABSEL_MASK; - break; -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF - case kLPADC_SampleChannelDiffBothSideAB: - tmp32 |= ADC_CMDL_DIFF_MASK; - break; - case kLPADC_SampleChannelDiffBothSideBA: - tmp32 |= ADC_CMDL_ABSEL_MASK | ADC_CMDL_DIFF_MASK; - break; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_DIFF */ - default: /* kLPADC_SampleChannelSingleEndSideA. */ - break; - } -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - tmp32 |= ADC_CMDL_MODE(config->conversionResolutionMode); -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ - base->CMD[commandId].CMDL = tmp32; - - /* ADCx_CMDH. */ - tmp32 = ADC_CMDH_NEXT(config->chainedNextCommandNumber) /* Next Command Select. */ - | ADC_CMDH_LOOP(config->loopCount) /* Loop Count Select. */ - | ADC_CMDH_AVGS(config->hardwareAverageMode) /* Hardware Average Select. */ - | ADC_CMDH_STS(config->sampleTimeMode) /* Sample Time Select. */ - | ADC_CMDH_CMPEN(config->hardwareCompareMode); /* Hardware compare enable. */ -#if (defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) - if (config->enableWaitTrigger) - { - tmp32 |= ADC_CMDH_WAIT_TRIG_MASK; /* Wait trigger enable. */ - } -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ - - if (config->enableAutoChannelIncrement) - { - tmp32 |= ADC_CMDH_LWI_MASK; - } - base->CMD[commandId].CMDH = tmp32; - - /* Hardware compare settings. - * Not all Command Buffers have an associated Compare Value register. The compare function is only available on - * Command Buffers that have a corresponding Compare Value register. - */ - if (kLPADC_HardwareCompareDisabled != config->hardwareCompareMode) - { - /* Check if the hardware compare feature is available for indicated command buffer. */ - assert(commandId < ADC_CV_COUNT); - - /* Set CV register. */ - base->CV[commandId] = ADC_CV_CVH(config->hardwareCompareValueHigh) /* Compare value high. */ - | ADC_CV_CVL(config->hardwareCompareValueLow); /* Compare value low. */ - } -} - -/*! - * brief Gets an available pre-defined settings for conversion command's configuration. - * - * This function initializes the conversion command's configuration structure with an available settings. The default - * values are: - * code - * config->sampleScaleMode = kLPADC_SampleFullScale; - * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; - * config->channelNumber = 0U; - * config->chainedNextCmdNumber = 0U; - * config->enableAutoChannelIncrement = false; - * config->loopCount = 0U; - * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - * config->sampleTimeMode = kLPADC_SampleTimeADCK3; - * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - * config->hardwareCompareValueHigh = 0U; - * config->hardwareCompareValueLow = 0U; - * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; - * config->enableWaitTrigger = false; - * endcode - * param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config) -{ - assert(config != NULL); /* Check if the input pointer is available. */ - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - config->sampleScaleMode = kLPADC_SampleFullScale; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ - config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; - config->channelNumber = 0U; - config->chainedNextCommandNumber = 0U; /* No next command defined. */ - config->enableAutoChannelIncrement = false; - config->loopCount = 0U; - config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - config->sampleTimeMode = kLPADC_SampleTimeADCK3; - config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - config->hardwareCompareValueHigh = 0U; /* No used. */ - config->hardwareCompareValueLow = 0U; /* No used. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG - config->enableWaitTrigger = false; -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ -} - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS -/*! - * brief Enable the calibration function. - * - * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes - * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value - * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- - * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the - * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. - * - * param base LPADC peripheral base address. - * param enable switcher to the calibration function. - */ -void LPADC_EnableCalibration(ADC_Type *base, bool enable) -{ - LPADC_Enable(base, false); - if (enable) - { - base->CFG |= ADC_CFG_CALOFS_MASK; - } - else - { - base->CFG &= ~ADC_CFG_CALOFS_MASK; - } - LPADC_Enable(base, true); -} - -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! - * brief Do auto calibration. - * - * Calibration function should be executed before using converter in application. It used the software trigger and a - * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API - * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) - * -LPADC_SetConvTriggerConfig(...) - * - * param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base) -{ - assert(0u == LPADC_GetConvResultCount(base)); - - uint32_t mLpadcCMDL; - uint32_t mLpadcCMDH; - uint32_t mLpadcTrigger; - lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct; - lpadc_conv_command_config_t mLpadcCommandConfigStruct; - lpadc_conv_result_t mLpadcResultConfigStruct; - - /* Enable the calibration function. */ - LPADC_EnableCalibration(base, true); - - /* Keep the CMD and TRG state here and restore it later if the calibration completes.*/ - mLpadcCMDL = base->CMD[0].CMDL; /* CMD1L. */ - mLpadcCMDH = base->CMD[0].CMDH; /* CMD1H. */ - mLpadcTrigger = base->TCTRL[0]; /* Trigger0. */ - - /* Set trigger0 configuration - for software trigger. */ - LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct); - mLpadcTriggerConfigStruct.targetCommandId = 1U; /* CMD1 is executed. */ - LPADC_SetConvTriggerConfig(base, 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */ - - /* Set conversion CMD configuration. */ - LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct); - mLpadcCommandConfigStruct.hardwareAverageMode = kLPADC_HardwareAverageCount128; - LPADC_SetConvCommandConfig(base, 1U, &mLpadcCommandConfigStruct); /* Set CMD1 configuration. */ - - /* Do calibration. */ - LPADC_DoSoftwareTrigger(base, 1U); /* 1U is trigger0 mask. */ - while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct)) - { - } - /* The valid bits of data are bits 14:3 in the RESFIFO register. */ - LPADC_SetOffsetValue(base, (uint32_t)(mLpadcResultConfigStruct.convValue) >> 3UL); - /* Disable the calibration function. */ - LPADC_EnableCalibration(base, false); - - /* restore CMD and TRG registers. */ - base->CMD[0].CMDL = mLpadcCMDL; /* CMD1L. */ - base->CMD[0].CMDH = mLpadcCMDH; /* CMD1H. */ - base->TCTRL[0] = mLpadcTrigger; /* Trigger0. */ -} -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS -/*! - * brief Do offset calibration. - * - * param base LPADC peripheral base address. - */ -void LPADC_DoOffsetCalibration(ADC_Type *base) -{ - LPADC_EnableOffsetCalibration(base, true); - while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) - { - } -} - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ -/*! - * brief Do auto calibration. - * - * param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base) -{ - assert((0u == LPADC_GetConvResultCount(base, 0)) && (0u == LPADC_GetConvResultCount(base, 1))); - - uint32_t GCCa; - uint32_t GCCb; - uint32_t GCRa; - uint32_t GCRb; - - /* Request gain calibration. */ - base->CTRL |= ADC_CTRL_CAL_REQ_MASK; - while ((ADC_GCC_RDY_MASK != (base->GCC[0] & ADC_GCC_RDY_MASK)) || - (ADC_GCC_RDY_MASK != (base->GCC[1] & ADC_GCC_RDY_MASK))) - { - } - - /* Calculate gain offset. */ - GCCa = (base->GCC[0] & ADC_GCC_GAIN_CAL_MASK); - GCCb = (base->GCC[1] & ADC_GCC_GAIN_CAL_MASK); - GCRa = (uint16_t)((GCCa << 16U) / - (0x1FFFFU - GCCa)); /* Gain_CalA = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[0])) - 1. */ - GCRb = (uint16_t)((GCCb << 16U) / - (0x1FFFFU - GCCb)); /* Gain_CalB = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[1])) - 1. */ - base->GCR[0] = ADC_GCR_GCALR(GCRa); - base->GCR[1] = ADC_GCR_GCALR(GCRb); - - /* Indicate the values are valid. */ - base->GCR[0] |= ADC_GCR_RDY_MASK; - base->GCR[1] |= ADC_GCR_RDY_MASK; - - while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) - { - } -} -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_lpadc.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_lpadc.h deleted file mode 100644 index d3e5a9ec30a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_lpadc.h +++ /dev/null @@ -1,964 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_LPADC_H_ -#define _FSL_LPADC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpadc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPADC driver version 2.5.1. */ -#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 5, 1)) -/*@}*/ - -/*! - * @brief Define the MACRO function to get command status from status value. - * - * The statusVal is the return value from LPADC_GetStatusFlags(). - */ -#define LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal) ((statusVal & ADC_STAT_CMDACT_MASK) >> ADC_STAT_CMDACT_SHIFT) - -/*! - * @brief Define the MACRO function to get trigger status from status value. - * - * The statusVal is the return value from LPADC_GetStatusFlags(). - */ -#define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT) - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Define hardware flags of the module. - */ -enum _lpadc_status_flags -{ - kLPADC_ResultFIFO0OverflowFlag = ADC_STAT_FOF0_MASK, /*!< Indicates that more data has been written to the Result - FIFO 0 than it can hold. */ - kLPADC_ResultFIFO0ReadyFlag = ADC_STAT_RDY0_MASK, /*!< Indicates when the number of valid datawords in the result - FIFO 0 is greater than the setting watermark level. */ - kLPADC_ResultFIFO1OverflowFlag = ADC_STAT_FOF1_MASK, /*!< Indicates that more data has been written to the Result - FIFO 1 than it can hold. */ - kLPADC_ResultFIFO1ReadyFlag = ADC_STAT_RDY1_MASK, /*!< Indicates when the number of valid datawords in the result - FIFO 1 is greater than the setting watermark level. */ -}; - -/*! - * @brief Define interrupt switchers of the module. - */ -enum _lpadc_interrupt_enable -{ - kLPADC_ResultFIFO0OverflowInterruptEnable = ADC_IE_FOFIE0_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF0 flag is asserted. */ - kLPADC_FIFO0WatermarkInterruptEnable = ADC_IE_FWMIE0_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY0 flag is asserted. */ - kLPADC_ResultFIFO1OverflowInterruptEnable = ADC_IE_FOFIE1_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF1 flag is asserted. */ - kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY1 flag is asserted. */ -#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) - kLPADC_TriggerExceptionInterruptEnable = ADC_IE_TEXC_IE_MASK, /*!< Configures ADC to generate trigger exception - interrupt. */ - kLPADC_Trigger0CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 0UL), /*!< Configures ADC to generate interrupt - when trigger 0 completion. */ - kLPADC_Trigger1CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 1UL), /*!< Configures ADC to generate interrupt - when trigger 1 completion. */ - kLPADC_Trigger2CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 2UL), /*!< Configures ADC to generate interrupt - when trigger 2 completion. */ - kLPADC_Trigger3CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 3UL), /*!< Configures ADC to generate interrupt - when trigger 3 completion. */ - kLPADC_Trigger4CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 4UL), /*!< Configures ADC to generate interrupt - when trigger 4 completion. */ - kLPADC_Trigger5CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 5UL), /*!< Configures ADC to generate interrupt - when trigger 5 completion. */ - kLPADC_Trigger6CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 6UL), /*!< Configures ADC to generate interrupt - when trigger 6 completion. */ - kLPADC_Trigger7CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 7UL), /*!< Configures ADC to generate interrupt - when trigger 7 completion. */ - kLPADC_Trigger8CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 8UL), /*!< Configures ADC to generate interrupt - when trigger 8 completion. */ - kLPADC_Trigger9CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 9UL), /*!< Configures ADC to generate interrupt - when trigger 9 completion. */ - kLPADC_Trigger10CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 10UL), /*!< Configures ADC to generate interrupt - when trigger 10 completion. */ - kLPADC_Trigger11CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 11UL), /*!< Configures ADC to generate interrupt - when trigger 11 completion. */ - kLPADC_Trigger12CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 12UL), /*!< Configures ADC to generate interrupt - when trigger 12 completion. */ - kLPADC_Trigger13CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 13UL), /*!< Configures ADC to generate interrupt - when trigger 13 completion. */ - kLPADC_Trigger14CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 14UL), /*!< Configures ADC to generate interrupt - when trigger 14 completion. */ - kLPADC_Trigger15CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 15UL), /*!< Configures ADC to generate interrupt - when trigger 15 completion. */ -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ -}; -#else -/*! - * @brief Define hardware flags of the module. - */ -enum _lpadc_status_flags -{ - kLPADC_ResultFIFOOverflowFlag = ADC_STAT_FOF_MASK, /*!< Indicates that more data has been written to the Result FIFO - than it can hold. */ - kLPADC_ResultFIFOReadyFlag = ADC_STAT_RDY_MASK, /*!< Indicates when the number of valid datawords in the result FIFO - is greater than the setting watermark level. */ -}; - -/*! - * @brief Define interrupt switchers of the module. - */ -enum _lpadc_interrupt_enable -{ - kLPADC_ResultFIFOOverflowInterruptEnable = ADC_IE_FOFIE_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF flag is asserted. */ - kLPADC_FIFOWatermarkInterruptEnable = ADC_IE_FWMIE_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY flag is asserted. */ -}; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) -/*! - * @brief The enumerator of lpadc trigger status flags, including interrupted flags and completed flags. - */ -enum _lpadc_trigger_status_flags -{ - kLPADC_Trigger0InterruptedFlag = 1UL << 0UL, /*!< Trigger 0 is interrupted by a high priority exception. */ - kLPADC_Trigger1InterruptedFlag = 1UL << 1UL, /*!< Trigger 1 is interrupted by a high priority exception. */ - kLPADC_Trigger2InterruptedFlag = 1UL << 2UL, /*!< Trigger 2 is interrupted by a high priority exception. */ - kLPADC_Trigger3InterruptedFlag = 1UL << 3UL, /*!< Trigger 3 is interrupted by a high priority exception. */ - kLPADC_Trigger4InterruptedFlag = 1UL << 4UL, /*!< Trigger 4 is interrupted by a high priority exception. */ - kLPADC_Trigger5InterruptedFlag = 1UL << 5UL, /*!< Trigger 5 is interrupted by a high priority exception. */ - kLPADC_Trigger6InterruptedFlag = 1UL << 6UL, /*!< Trigger 6 is interrupted by a high priority exception. */ - kLPADC_Trigger7InterruptedFlag = 1UL << 7UL, /*!< Trigger 7 is interrupted by a high priority exception. */ - kLPADC_Trigger8InterruptedFlag = 1UL << 8UL, /*!< Trigger 8 is interrupted by a high priority exception. */ - kLPADC_Trigger9InterruptedFlag = 1UL << 9UL, /*!< Trigger 9 is interrupted by a high priority exception. */ - kLPADC_Trigger10InterruptedFlag = 1UL << 10UL, /*!< Trigger 10 is interrupted by a high priority exception. */ - kLPADC_Trigger11InterruptedFlag = 1UL << 11UL, /*!< Trigger 11 is interrupted by a high priority exception. */ - kLPADC_Trigger12InterruptedFlag = 1UL << 12UL, /*!< Trigger 12 is interrupted by a high priority exception. */ - kLPADC_Trigger13InterruptedFlag = 1UL << 13UL, /*!< Trigger 13 is interrupted by a high priority exception. */ - kLPADC_Trigger14InterruptedFlag = 1UL << 14UL, /*!< Trigger 14 is interrupted by a high priority exception. */ - kLPADC_Trigger15InterruptedFlag = 1UL << 15UL, /*!< Trigger 15 is interrupted by a high priority exception. */ - - kLPADC_Trigger0CompletedFlag = 1UL << 16UL, /*!< Trigger 0 is completed and - trigger 0 has enabled completion interrupts. */ - kLPADC_Trigger1CompletedFlag = 1UL << 17UL, /*!< Trigger 1 is completed and - trigger 1 has enabled completion interrupts. */ - kLPADC_Trigger2CompletedFlag = 1UL << 18UL, /*!< Trigger 2 is completed and - trigger 2 has enabled completion interrupts. */ - kLPADC_Trigger3CompletedFlag = 1UL << 19UL, /*!< Trigger 3 is completed and - trigger 3 has enabled completion interrupts. */ - kLPADC_Trigger4CompletedFlag = 1UL << 20UL, /*!< Trigger 4 is completed and - trigger 4 has enabled completion interrupts. */ - kLPADC_Trigger5CompletedFlag = 1UL << 21UL, /*!< Trigger 5 is completed and - trigger 5 has enabled completion interrupts. */ - kLPADC_Trigger6CompletedFlag = 1UL << 22UL, /*!< Trigger 6 is completed and - trigger 6 has enabled completion interrupts. */ - kLPADC_Trigger7CompletedFlag = 1UL << 23UL, /*!< Trigger 7 is completed and - trigger 7 has enabled completion interrupts. */ - kLPADC_Trigger8CompletedFlag = 1UL << 24UL, /*!< Trigger 8 is completed and - trigger 8 has enabled completion interrupts. */ - kLPADC_Trigger9CompletedFlag = 1UL << 25UL, /*!< Trigger 9 is completed and - trigger 9 has enabled completion interrupts. */ - kLPADC_Trigger10CompletedFlag = 1UL << 26UL, /*!< Trigger 10 is completed and - trigger 10 has enabled completion interrupts. */ - kLPADC_Trigger11CompletedFlag = 1UL << 27UL, /*!< Trigger 11 is completed and - trigger 11 has enabled completion interrupts. */ - kLPADC_Trigger12CompletedFlag = 1UL << 28UL, /*!< Trigger 12 is completed and - trigger 12 has enabled completion interrupts. */ - kLPADC_Trigger13CompletedFlag = 1UL << 29UL, /*!< Trigger 13 is completed and - trigger 13 has enabled completion interrupts. */ - kLPADC_Trigger14CompletedFlag = 1UL << 30UL, /*!< Trigger 14 is completed and - trigger 14 has enabled completion interrupts. */ - kLPADC_Trigger15CompletedFlag = 1UL << 31UL, /*!< Trigger 15 is completed and - trigger 15 has enabled completion interrupts. */ -}; -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ - -/*! - * @brief Define enumeration of sample scale mode. - * - * The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum - * possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the - * reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows - * conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode. - */ -typedef enum _lpadc_sample_scale_mode -{ - kLPADC_SamplePartScale = 0U, /*!< Use divided input voltage signal. (Factor of 30/64). */ - kLPADC_SampleFullScale = 1U, /*!< Full scale (Factor of 1). */ -} lpadc_sample_scale_mode_t; - -/*! - * @brief Define enumeration of channel sample mode. - * - * The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B. - */ -typedef enum _lpadc_sample_channel_mode -{ - kLPADC_SampleChannelSingleEndSideA = 0U, /*!< Single end mode, using side A. */ - kLPADC_SampleChannelSingleEndSideB = 1U, /*!< Single end mode, using side B. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF - kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minus side. */ - kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minus side. */ -#elif defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE - kLPADC_SampleChannelDiffBothSide = 2U, /*!< Differential mode, using A and B. */ - kLPADC_SampleChannelDualSingleEndBothSide = - 3U, /*!< Dual-Single-Ended Mode. Both A side and B side channels are converted independently. */ -#endif -} lpadc_sample_channel_mode_t; - -/*! - * @brief Define enumeration of hardware average selection. - * - * It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to - * capture temporary results while the averaging iterations are executed. - */ -typedef enum _lpadc_hardware_average_mode -{ - kLPADC_HardwareAverageCount1 = 0U, /*!< Single conversion. */ - kLPADC_HardwareAverageCount2 = 1U, /*!< 2 conversions averaged. */ - kLPADC_HardwareAverageCount4 = 2U, /*!< 4 conversions averaged. */ - kLPADC_HardwareAverageCount8 = 3U, /*!< 8 conversions averaged. */ - kLPADC_HardwareAverageCount16 = 4U, /*!< 16 conversions averaged. */ - kLPADC_HardwareAverageCount32 = 5U, /*!< 32 conversions averaged. */ - kLPADC_HardwareAverageCount64 = 6U, /*!< 64 conversions averaged. */ - kLPADC_HardwareAverageCount128 = 7U, /*!< 128 conversions averaged. */ -} lpadc_hardware_average_mode_t; - -/*! - * @brief Define enumeration of sample time selection. - * - * The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher - * impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption - * when command looping and sequencing is configured and high conversion rates are not required. - */ -typedef enum _lpadc_sample_time_mode -{ - kLPADC_SampleTimeADCK3 = 0U, /*!< 3 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK5 = 1U, /*!< 5 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK7 = 2U, /*!< 7 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK11 = 3U, /*!< 11 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK19 = 4U, /*!< 19 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK35 = 5U, /*!< 35 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK67 = 6U, /*!< 69 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK131 = 7U, /*!< 131 ADCK cycles total sample time. */ -} lpadc_sample_time_mode_t; - -/*! - * @brief Define enumeration of hardware compare mode. - * - * After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting - * guides operation of the automatic compare function to optionally only store when the compare operation is true. - * When compare is enabled, the conversion result is compared to the compare values. - */ -typedef enum _lpadc_hardware_compare_mode -{ - kLPADC_HardwareCompareDisabled = 0U, /*!< Compare disabled. */ - kLPADC_HardwareCompareStoreOnTrue = 2U, /*!< Compare enabled. Store on true. */ - kLPADC_HardwareCompareRepeatUntilTrue = 3U, /*!< Compare enabled. Repeat channel acquisition until true. */ -} lpadc_hardware_compare_mode_t; - -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE -/*! - * @brief Define enumeration of conversion resolution mode. - * - * Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to - * #lpadc_sample_channel_mode_t - */ -typedef enum _lpadc_conversion_resolution_mode -{ - kLPADC_ConversionResolutionStandard = 0U, /*!< Standard resolution. Single-ended 12-bit conversion, Differential - 13-bit conversion with 2’s complement output. */ - kLPADC_ConversionResolutionHigh = 1U, /*!< High resolution. Single-ended 16-bit conversion; Differential 16-bit - conversion with 2’s complement output. */ -} lpadc_conversion_resolution_mode_t; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS -/*! - * @brief Define enumeration of conversion averages mode. - * - * Configure the converion average number for auto-calibration. - */ -typedef enum _lpadc_conversion_average_mode -{ - kLPADC_ConversionAverage1 = 0U, /*!< Single conversion. */ - kLPADC_ConversionAverage2 = 1U, /*!< 2 conversions averaged. */ - kLPADC_ConversionAverage4 = 2U, /*!< 4 conversions averaged. */ - kLPADC_ConversionAverage8 = 3U, /*!< 8 conversions averaged. */ - kLPADC_ConversionAverage16 = 4U, /*!< 16 conversions averaged. */ - kLPADC_ConversionAverage32 = 5U, /*!< 32 conversions averaged. */ - kLPADC_ConversionAverage64 = 6U, /*!< 64 conversions averaged. */ - kLPADC_ConversionAverage128 = 7U, /*!< 128 conversions averaged. */ -} lpadc_conversion_average_mode_t; -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - -/*! - * @brief Define enumeration of reference voltage source. - * - * For detail information, need to check the SoC's specification. - */ -typedef enum _lpadc_reference_voltage_mode -{ - kLPADC_ReferenceVoltageAlt1 = 0U, /*!< Option 1 setting. */ - kLPADC_ReferenceVoltageAlt2 = 1U, /*!< Option 2 setting. */ - kLPADC_ReferenceVoltageAlt3 = 2U, /*!< Option 3 setting. */ -} lpadc_reference_voltage_source_t; - -/*! - * @brief Define enumeration of power configuration. - * - * Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be - * possible. Refer to the device data sheet for power and performance capabilities for each setting. - */ -typedef enum _lpadc_power_level_mode -{ - kLPADC_PowerLevelAlt1 = 0U, /*!< Lowest power setting. */ - kLPADC_PowerLevelAlt2 = 1U, /*!< Next lowest power setting. */ - kLPADC_PowerLevelAlt3 = 2U, /*!< ... */ - kLPADC_PowerLevelAlt4 = 3U, /*!< Highest power setting. */ -} lpadc_power_level_mode_t; - -/*! - * @brief Define enumeration of trigger priority policy. - * - * This selection controls how higher priority triggers are handled. - */ -typedef enum _lpadc_trigger_priority_policy -{ - kLPADC_TriggerPriorityPreemptImmediately = 0U, /*!< If a higher priority trigger is detected during command - processing, the current conversion is aborted and the new - command specified by the trigger is started. */ - kLPADC_TriggerPriorityPreemptSoftly = 1U, /*!< If a higher priority trigger is received during command processing, - the current conversion is completed (including averaging iterations - and compare function if enabled) and stored to the result FIFO - before the higher priority trigger/command is initiated. */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY) && FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY - kLPADC_TriggerPriorityPreemptSubsequently = 2U, /*!< If a higher priority trigger is received during command - processing, the current command will be completed (averaging, - looping, compare) before servicing the higher priority trigger. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY */ -} lpadc_trigger_priority_policy_t; - -/*! - * @brief LPADC global configuration. - * - * This structure would used to keep the settings for initialization. - */ -typedef struct -{ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock - selection logic at the chip level and is optionally used for the ADC clock source. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - bool enableVref1LowVoltage; /*!< If voltage reference option1 input is below 1.8V, it should be "true". - If voltage reference option1 input is above 1.8V, it should be "false". */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - bool enableInDozeMode; /*!< Control system transition to Stop and Wait power modes while ADC is converting. When - enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the - ADC will wait for the current averaging iteration/FIFO storage to complete before - acknowledging stop or wait mode entry. */ -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS - lpadc_conversion_average_mode_t conversionAverageMode; /*!< Auto-Calibration Averages. */ -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - bool enableAnalogPreliminary; /*!< ADC analog circuits are pre-enabled and ready to execute conversions without - startup delays(at the cost of higher DC current consumption). */ - uint32_t powerUpDelay; /*!< When the analog circuits are not pre-enabled, the ADC analog circuits are only powered - while the ADC is active and there is a counted delay defined by this field after an - initial trigger transitions the ADC from its Idle state to allow time for the analog - circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must - result in a longer delay than the analog startup time. */ - lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for - conversions.*/ - lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */ - lpadc_trigger_priority_policy_t triggerPriorityPolicy; /*!< Control how higher priority triggers are handled, see to - lpadc_trigger_priority_policy_t. */ - bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during - command execution sequencing between LOOP iterations, between commands in a sequence, and - between conversions when command is executing in "Compare Until True" configuration. */ - uint32_t convPauseDelay; /*!< Controls the duration of pausing during command execution sequencing. The pause delay - is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing - function is enabled. The available value range is in 9-bit. */ -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - /* for FIFO0. */ - uint32_t FIFO0Watermark; /*!< FIFO0Watermark is a programmable threshold setting. When the number of datawords - stored in the ADC Result FIFO0 is greater than the value in this field, the ready flag - would be asserted to indicate stored data has reached the programmable threshold. */ - /* for FIFO1. */ - uint32_t FIFO1Watermark; /*!< FIFO1Watermark is a programmable threshold setting. When the number of datawords - stored in the ADC Result FIFO1 is greater than the value in this field, the ready flag - would be asserted to indicate stored data has reached the programmable threshold. */ -#else - /* for FIFO. */ - uint32_t FIFOWatermark; /*!< FIFOWatermark is a programmable threshold setting. When the number of datawords stored - in the ADC Result FIFO is greater than the value in this field, the ready flag would be - asserted to indicate stored data has reached the programmable threshold. */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ -} lpadc_config_t; - -/*! - * @brief Define structure to keep the configuration for conversion command. - */ -typedef struct -{ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ - lpadc_sample_channel_mode_t sampleChannelMode; /*!< Channel sample mode. */ - uint32_t channelNumber; /*!< Channel number, select the channel or channel pair. */ - uint32_t chainedNextCommandNumber; /*!< Selects the next command to be executed after this command completes. - 1-15 is available, 0 is to terminate the chain after this command. */ - bool enableAutoChannelIncrement; /*!< Loop with increment: when disabled, the "loopCount" field selects the number - of times the selected channel is converted consecutively; when enabled, the - "loopCount" field defines how many consecutive channels are converted as part - of the command execution. */ - uint32_t loopCount; /*!< Selects how many times this command executes before finish and transition to the next - command or Idle state. Command executes LOOP+1 times. 0-15 is available. */ - lpadc_hardware_average_mode_t hardwareAverageMode; /*!< Hardware average selection. */ - lpadc_sample_time_mode_t sampleTimeMode; /*!< Sample time selection. */ - - lpadc_hardware_compare_mode_t hardwareCompareMode; /*!< Hardware compare selection. */ - uint32_t hardwareCompareValueHigh; /*!< Compare Value High. The available value range is in 16-bit. */ - uint32_t hardwareCompareValueLow; /*!< Compare Value Low. The available value range is in 16-bit. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - lpadc_conversion_resolution_mode_t conversionResolutionMode; /*!< Conversion resolution mode. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG - bool enableWaitTrigger; /*!< Wait for trigger assertion before execution: when disabled, this command will be - automatically executed; when enabled, the active trigger must be asserted again before - executing this command. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ -} lpadc_conv_command_config_t; - -/*! - * @brief Define structure to keep the configuration for conversion trigger. - */ -typedef struct -{ - uint32_t targetCommandId; /*!< Select the command from command buffer to execute upon detect of the associated - trigger event. */ - uint32_t delayPower; /*!< Select the trigger delay duration to wait at the start of servicing a trigger event. - When this field is clear, then no delay is incurred. When this field is set to a non-zero - value, the duration for the delay is 2^delayPower ADCK cycles. The available value range - is 4-bit. */ - uint32_t priority; /*!< Sets the priority of the associated trigger source. If two or more triggers have the same - priority level setting, the lower order trigger event has the higher priority. The lower - value for this field is for the higher priority, the available value range is 1-bit. */ -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - uint8_t channelAFIFOSelect; /* SAR Result Destination For Channel A. */ - uint8_t channelBFIFOSelect; /* SAR Result Destination For Channel B. */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - bool enableHardwareTrigger; /*!< Enable hardware trigger source to initiate conversion on the rising edge of the - input trigger source or not. THe software trigger is always available. */ -} lpadc_conv_trigger_config_t; - -/*! - * @brief Define the structure to keep the conversion result. - */ -typedef struct -{ - uint32_t commandIdSource; /*!< Indicate the command buffer being executed that generated this result. */ - uint32_t loopCountIndex; /*!< Indicate the loop count value during command execution that generated this result. */ - uint32_t triggerIdSource; /*!< Indicate the trigger source that initiated a conversion and generated this result. */ - uint16_t convValue; /*!< Data result. */ -} lpadc_conv_result_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ -/*! - * @name Initialization & de-initialization. - * @{ - */ - -/*! - * @brief Initializes the LPADC module. - * - * @param base LPADC peripheral base address. - * @param config Pointer to configuration structure. See "lpadc_config_t". - */ -void LPADC_Init(ADC_Type *base, const lpadc_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for initial configuration. - * - * This function initializes the converter configuration structure with an available settings. The default values are: - * @code - * config->enableInDozeMode = true; - * config->enableAnalogPreliminary = false; - * config->powerUpDelay = 0x80; - * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - * config->powerLevelMode = kLPADC_PowerLevelAlt1; - * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; - * config->enableConvPause = false; - * config->convPauseDelay = 0U; - * config->FIFOWatermark = 0U; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConfig(lpadc_config_t *config); - -/*! - * @brief De-initializes the LPADC module. - * - * @param base LPADC peripheral base address. - */ -void LPADC_Deinit(ADC_Type *base); - -/*! - * @brief Switch on/off the LPADC module. - * - * @param base LPADC peripheral base address. - * @param enable switcher to the module. - */ -static inline void LPADC_Enable(ADC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= ADC_CTRL_ADCEN_MASK; - } - else - { - base->CTRL &= ~ADC_CTRL_ADCEN_MASK; - } -} - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Do reset the conversion FIFO0. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO0(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO0_MASK; -} - -/*! - * @brief Do reset the conversion FIFO1. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO1(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO1_MASK; -} -#else -/*! - * @brief Do reset the conversion FIFO. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO_MASK; -} -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * @brief Do reset the module's configuration. - * - * Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL). - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetConfig(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RST_MASK; - base->CTRL &= ~ADC_CTRL_RST_MASK; -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Get status flags. - * - * @param base LPADC peripheral base address. - * @return status flags' mask. See to #_lpadc_status_flags. - */ -static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base) -{ - return base->STAT; -} - -/*! - * @brief Clear status flags. - * - * Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for flags to be cleared. See to #_lpadc_status_flags. - */ -static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) -{ - base->STAT = mask; -} - -#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) -/*! - * @brief Get trigger status flags to indicate which trigger sequences have been completed or interrupted by a high - * priority trigger exception. - * - * @param base LPADC peripheral base address. - * @return The OR'ed value of @ref _lpadc_trigger_status_flags. - */ -static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base) -{ - return base->TSTAT; -} - -/*! - * @brief Clear trigger status flags. - * - * @param base LPADC peripheral base address. - * @param mask The mask of trigger status flags to be cleared, should be the - * OR'ed value of @ref _lpadc_trigger_status_flags. - */ -static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask) -{ - base->TSTAT = mask; -} -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enable interrupts. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. - */ -static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask) -{ - base->IE |= mask; -} - -/*! - * @brief Disable interrupts. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. - */ -static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask) -{ - base->IE &= ~mask; -} - -/*! - * @name DMA Control - * @{ - */ - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Switch on/off the DMA trigger for FIFO0 watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFO0WatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE0_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE0_MASK; - } -} - -/*! - * @brief Switch on/off the DMA trigger for FIFO1 watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFO1WatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE1_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE1_MASK; - } -} -#else -/*! - * @brief Switch on/off the DMA trigger for FIFO watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE_MASK; - } -} -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - /* @} */ - -/*! - * @name Trigger and conversion with FIFO. - * @{ - */ - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Get the count of result kept in conversion FIFOn. - * - * @param base LPADC peripheral base address. - * @param index Result FIFO index. - * @return The count of result kept in conversion FIFOn. - */ -static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index) -{ - return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL[index]) >> ADC_FCTRL_FCOUNT_SHIFT; -} - -/*! - * brief Get the result in conversion FIFOn. - * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. - * param index Result FIFO index. - * - * return Status whether FIFOn entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index); -#else -/*! - * @brief Get the count of result kept in conversion FIFO. - * - * @param base LPADC peripheral base address. - * @return The count of result kept in conversion FIFO. - */ -static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base) -{ - return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL) >> ADC_FCTRL_FCOUNT_SHIFT; -} - -/*! - * @brief Get the result in conversion FIFO. - * - * @param base LPADC peripheral base address. - * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. - * - * @return Status whether FIFO entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * @brief Configure the conversion trigger source. - * - * Each programmable trigger can launch the conversion command in command buffer. - * - * @param base LPADC peripheral base address. - * @param triggerId ID for each trigger. Typically, the available value range is from 0. - * @param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. - */ -void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for trigger's configuration. - * - * This function initializes the trigger's configuration structure with an available settings. The default values are: - * @code - * config->commandIdSource = 0U; - * config->loopCountIndex = 0U; - * config->triggerIdSource = 0U; - * config->enableHardwareTrigger = false; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config); - -/*! - * @brief Do software trigger to conversion command. - * - * @param base LPADC peripheral base address. - * @param triggerIdMask Mask value for software trigger indexes, which count from zero. - */ -static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask) -{ - /* Writes to ADCx_SWTRIG register are ignored while ADCx_CTRL[ADCEN] is clear. */ - base->SWTRIG = triggerIdMask; -} - -/*! - * @brief Configure conversion command. - * - * @param base LPADC peripheral base address. - * @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. - * @param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. - */ -void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for conversion command's configuration. - * - * This function initializes the conversion command's configuration structure with an available settings. The default - * values are: - * @code - * config->sampleScaleMode = kLPADC_SampleFullScale; - * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; - * config->channelNumber = 0U; - * config->chainedNextCmdNumber = 0U; - * config->enableAutoChannelIncrement = false; - * config->loopCount = 0U; - * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - * config->sampleTimeMode = kLPADC_SampleTimeADCK3; - * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - * config->hardwareCompareValueHigh = 0U; - * config->hardwareCompareValueLow = 0U; - * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; - * config->enableWaitTrigger = false; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config); - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS -/*! - * @brief Enable the calibration function. - * - * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes - * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value - * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- - * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the - * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. - * - * @param base LPADC peripheral base address. - * @param enable switcher to the calibration function. - */ -void LPADC_EnableCalibration(ADC_Type *base, bool enable); -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! - * @brief Set proper offset value to trim ADC. - * - * To minimize the offset during normal operation, software should read the conversion result from - * the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register. - * - * @param base LPADC peripheral base address. - * @param value Setting offset value. - */ -static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value) -{ - base->OFSTRIM = (value & ADC_OFSTRIM_OFSTRIM_MASK) >> ADC_OFSTRIM_OFSTRIM_SHIFT; -} - -/*! - * @brief Do auto calibration. - * - * Calibration function should be executed before using converter in application. It used the software trigger and a - * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API - * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) - * -LPADC_SetConvTriggerConfig(...) - * - * @param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base); -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! - * @brief Set proper offset value to trim ADC. - * - * Set the offset trim value for offset calibration manually. - * - * @param base LPADC peripheral base address. - * @param valueA Setting offset value A. - * @param valueB Setting offset value B. - * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. - */ -static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t valueA, uint32_t valueB) -{ - base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB); -} -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ - -/*! - * @brief Enable the offset calibration function. - * - * @param base LPADC peripheral base address. - * @param enable switcher to the calibration function. - */ -static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= ADC_CTRL_CALOFS_MASK; - } - else - { - base->CTRL &= ~ADC_CTRL_CALOFS_MASK; - } -} - -/*! - * @brief Do offset calibration. - * - * @param base LPADC peripheral base address. - */ -void LPADC_DoOffsetCalibration(ADC_Type *base); - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ -/*! - * brief Do auto calibration. - * - * param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base); -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ - -/* @} */ - -#if defined(__cplusplus) -} -#endif -/*! - * @} - */ -#endif /* _FSL_LPADC_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_mcan.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_mcan.c deleted file mode 100644 index 9de92174731..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_mcan.c +++ /dev/null @@ -1,1744 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_mcan.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.mcan" -#endif - -/* According to CiA doc 1301 v1.0.0, specified data/nominal phase sample point postion for CAN FD at 80 MHz. */ -#define IDEAL_DATA_SP_1 (800U) -#define IDEAL_DATA_SP_2 (750U) -#define IDEAL_DATA_SP_3 (700U) -#define IDEAL_DATA_SP_4 (625U) -#define IDEAL_NOMINAL_SP (800U) - -/* According to CiA doc 301 v4.2.0 and previous version, specified sample point postion for classic CAN. */ -#define IDEAL_SP_LOW (750U) -#define IDEAL_SP_MID (800U) -#define IDEAL_SP_HIGH (875U) -#define IDEAL_SP_FACTOR (1000U) - -#define MAX_DSJW (CAN_DBTP_DSJW_MASK >> CAN_DBTP_DSJW_SHIFT) -#define MAX_DTSEG2 (CAN_DBTP_DTSEG2_MASK >> CAN_DBTP_DTSEG2_SHIFT) -#define MAX_DTSEG1 (CAN_DBTP_DTSEG1_MASK >> CAN_DBTP_DTSEG1_SHIFT) -#define MAX_DBRP (CAN_DBTP_DBRP_MASK >> CAN_DBTP_DBRP_SHIFT) - -#define MAX_NSJW (CAN_NBTP_NSJW_MASK >> CAN_NBTP_NSJW_SHIFT) -#define MAX_NTSEG2 (CAN_NBTP_NTSEG2_MASK >> CAN_NBTP_NTSEG2_SHIFT) -#define MAX_NTSEG1 (CAN_NBTP_NTSEG1_MASK >> CAN_NBTP_NTSEG1_SHIFT) -#define MAX_NBRP (CAN_NBTP_NBRP_MASK >> CAN_NBTP_NBRP_SHIFT) - -#define DBTP_MAX_TIME_QUANTA (1U + MAX_DTSEG2 + 1U + MAX_DTSEG1 + 1U) -#define DBTP_MIN_TIME_QUANTA (3U) -#define NBTP_MAX_TIME_QUANTA (1U + MAX_NTSEG2 + 1U + MAX_NTSEG1 + 1U) -#define NBTP_MIN_TIME_QUANTA (3U) - -#define MAX_TDCOFF ((uint32_t)CAN_TDCR_TDCO_MASK >> CAN_TDCR_TDCO_SHIFT) - -#define MAX_CANFD_BAUDRATE (8000000U) -#define MAX_CAN_BAUDRATE (1000000U) - -/*! @brief MCAN Internal State. */ -enum _mcan_state -{ - kMCAN_StateIdle = 0x0, /*!< MB/RxFIFO idle.*/ - kMCAN_StateRxData = 0x1, /*!< MB receiving.*/ - kMCAN_StateRxRemote = 0x2, /*!< MB receiving remote reply.*/ - kMCAN_StateTxData = 0x3, /*!< MB transmitting.*/ - kMCAN_StateTxRemote = 0x4, /*!< MB transmitting remote request.*/ - kMCAN_StateRxFifo = 0x5, /*!< RxFIFO receiving.*/ -}; - -/* Typedef for interrupt handler. */ -typedef void (*mcan_isr_t)(CAN_Type *base, mcan_handle_t *handle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get the MCAN instance from peripheral base address. - * - * @param base MCAN peripheral base address. - * @return MCAN instance. - */ -static uint32_t MCAN_GetInstance(CAN_Type *base); - -/*! - * @brief Reset the MCAN instance. - * - * @param base MCAN peripheral base address. - */ -static void MCAN_Reset(CAN_Type *base); - -/*! - * @brief Calculates the segment values for a single bit time for classical CAN - * - * @param baudRate The data speed in bps - * @param tqNum Number of time quantas per bit, range in 4~385 - * @param pconfig Pointer to the MCAN timing configuration structure. - */ -static void MCAN_GetSegments(uint32_t baudRate, uint32_t tqNum, mcan_timing_config_t *pconfig); - -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) -/*! - * @brief Calculates the segment values for a single bit time for CANFD bus data baud Rate - * - * @param baudRate The canfd bus data speed in bps - * @param tqNum Number of time quanta per bit, range in 3 ~ 33 - * @param pconfig Pointer to the MCAN timing configuration structure. - */ -static void MCAN_FDGetSegments(uint32_t baudRateFD, uint32_t tqNum, mcan_timing_config_t *pconfig); - -#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */ - -/*! - * @brief Get the element's address when read receive fifo 0. - * - * @param base MCAN peripheral base address. - * @return Address of the element in receive fifo 0. - */ -static uint32_t MCAN_GetRxFifo0ElementAddress(CAN_Type *base); - -/*! - * @brief Get the element's address when read receive fifo 1. - * - * @param base MCAN peripheral base address. - * @return Address of the element in receive fifo 1. - */ -static uint32_t MCAN_GetRxFifo1ElementAddress(CAN_Type *base); - -/*! - * @brief Get the element's address when read receive buffer. - * - * @param base MCAN peripheral base address. - * @param idx Number of the erceive buffer element. - * @return Address of the element in receive buffer. - */ -static uint32_t MCAN_GetRxBufferElementAddress(CAN_Type *base, uint8_t idx); - -/*! - * @brief Get the element's address when read transmit buffer. - * - * @param base MCAN peripheral base address. - * @param idx Number of the transmit buffer element. - * @return Address of the element in transmit buffer. - */ -static uint32_t MCAN_GetTxBufferElementAddress(CAN_Type *base, uint8_t idx); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of MCAN handle. */ -static mcan_handle_t *s_mcanHandle[FSL_FEATURE_SOC_LPC_CAN_COUNT]; - -/* Array of MCAN peripheral base address. */ -static CAN_Type *const s_mcanBases[] = CAN_BASE_PTRS; - -/* Array of MCAN IRQ number. */ -static const IRQn_Type s_mcanIRQ[][2] = CAN_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of MCAN clock name. */ -static const clock_ip_name_t s_mcanClock[] = MCAN_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_MCAN_HAS_NO_RESET) && FSL_FEATURE_MCAN_HAS_NO_RESET) -/*! @brief Pointers to MCAN resets for each instance. */ -static const reset_ip_name_t s_mcanResets[] = MCAN_RSTS; -#endif - -/* MCAN ISR for transactional APIs. */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -static mcan_isr_t s_mcanIsr = (mcan_isr_t)DefaultISR; -#else -static mcan_isr_t s_mcanIsr; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t MCAN_GetInstance(CAN_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_mcanBases); instance++) - { - if (s_mcanBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_mcanBases)); - - return instance; -} - -static void MCAN_Reset(CAN_Type *base) -{ - /* Set INIT bit. */ - base->CCCR |= CAN_CCCR_INIT_MASK; - /* Confirm the value has been accepted. */ - while (0U == (base->CCCR & CAN_CCCR_INIT_MASK)) - { - } - - /* Set CCE bit to have access to the protected configuration registers, - and clear some status registers. */ - base->CCCR |= CAN_CCCR_CCE_MASK; -} - -/*! - * brief Initializes an MCAN instance. - * - * This function initializes the MCAN module with user-defined settings. - * This example shows how to set up the mcan_config_t parameters and how - * to call the MCAN_Init function by passing in these parameters. - * code - * mcan_config_t config; - * config->baudRateA = 500000U; - * config->baudRateD = 1000000U; - * config->enableCanfdNormal = false; - * config->enableCanfdSwitch = false; - * config->enableLoopBackInt = false; - * config->enableLoopBackExt = false; - * config->enableBusMon = false; - * MCAN_Init(CANFD0, &config, 8000000UL); - * endcode - * - * param base MCAN peripheral base address. - * param config Pointer to the user-defined configuration structure. - * param sourceClock_Hz MCAN Protocol Engine clock source frequency in Hz. - */ -void MCAN_Init(CAN_Type *base, const mcan_config_t *config, uint32_t sourceClock_Hz) -{ - mcan_timing_config_t timingCfg = config->timingConfig; - uint32_t quantum = 0U; - uint32_t tqFre = 0U; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable MCAN clock. */ - CLOCK_EnableClock(s_mcanClock[MCAN_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_MCAN_HAS_NO_RESET) && FSL_FEATURE_MCAN_HAS_NO_RESET) - /* Reset the MCAN module */ - RESET_PeripheralReset(s_mcanResets[MCAN_GetInstance(base)]); -#endif - - MCAN_Reset(base); - - if (config->enableLoopBackInt) - { - base->CCCR |= CAN_CCCR_TEST_MASK | CAN_CCCR_MON_MASK; - base->TEST |= CAN_TEST_LBCK_MASK; - } - if (config->enableLoopBackExt) - { - base->CCCR |= CAN_CCCR_TEST_MASK; - base->TEST |= CAN_TEST_LBCK_MASK; - } - if (config->enableBusMon) - { - base->CCCR |= CAN_CCCR_MON_MASK; - } - - /* Nominal quantum = 1 + (NTSEG1 + 1) + (NTSEG2 + 1) */ - quantum = (1U + ((uint32_t)timingCfg.seg1 + 1U) + ((uint32_t)timingCfg.seg2 + 1U)); - tqFre = config->baudRateA * quantum; - - /* Assertion: Source clock should greater than baud rate * quantum. */ - assert((tqFre != 0U) && (tqFre <= sourceClock_Hz)); - - /* Check whether Nominal Bit Rate Prescaler is overflow. */ - if ((sourceClock_Hz / tqFre - 1U) > 0x1FFU) - { - timingCfg.preDivider = 0x1FFU; - } - else - { - timingCfg.preDivider = (uint16_t)(sourceClock_Hz / tqFre) - 1U; - } - /* Update actual timing characteristic to set baud rate of arbitration phase. */ - MCAN_SetArbitrationTimingConfig(base, &timingCfg); - -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) - if (config->enableCanfdNormal) - { - base->CCCR |= CAN_CCCR_FDOE_MASK; - } - if (config->enableCanfdSwitch) - { - /* Enable the CAN FD mode and Bit Rate Switch feature. */ - base->CCCR |= CAN_CCCR_FDOE_MASK | CAN_CCCR_BRSE_MASK; - - /* Data quantum = 1 + (NTSEG1 + 1) + (NTSEG2 + 1) */ - quantum = (1U + ((uint32_t)timingCfg.dataseg1 + 1U) + ((uint32_t)timingCfg.dataseg2 + 1U)); - tqFre = config->baudRateD * quantum; - assert((tqFre != 0U) && (tqFre <= sourceClock_Hz)); - - /* Check whether Data Bit Rate Prescaler is overflow. */ - if ((sourceClock_Hz / tqFre - 1U) > 0x1FU) - { - timingCfg.datapreDivider = 0x1FU; - } - else - { - timingCfg.datapreDivider = (uint16_t)(sourceClock_Hz / tqFre) - 1U; - } - - /* Update actual timing characteristic to set baud rate of data phase. */ - MCAN_SetDataTimingConfig(base, &timingCfg); - if (!config->enableLoopBackInt && !config->enableLoopBackExt) - { - /* Enable the Transceiver Delay Compensation. */ - base->DBTP |= CAN_DBTP_TDC_MASK; - /* Cleaning previous TDCO Setting. */ - base->TDCR &= ~CAN_TDCR_TDCO_MASK; - /* The TDC offset should be configured as shown in this equation : offset = (DTSEG1 + 2) * (DBRP + 1) */ - if (((uint32_t)timingCfg.dataseg1 + 2U) * (timingCfg.datapreDivider + 1U) < MAX_TDCOFF) - { - base->TDCR |= CAN_TDCR_TDCO(((uint32_t)timingCfg.dataseg1 + 2U) * (timingCfg.datapreDivider + 1U)); - } - else - { - /* Set the Transceiver Delay Compensation offset to max value. */ - base->TDCR |= CAN_TDCR_TDCO(MAX_TDCOFF); - } - } - } -#endif -} - -/*! - * brief Deinitializes an MCAN instance. - * - * This function deinitializes the MCAN module. - * - * param base MCAN peripheral base address. - */ -void MCAN_Deinit(CAN_Type *base) -{ - /* Reset all Register Contents. */ - MCAN_Reset(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable MCAN clock. */ - CLOCK_DisableClock(s_mcanClock[MCAN_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief MCAN enters normal mode. - * - * After initialization, INIT bit in CCCR register must be cleared to enter - * normal mode thus synchronizes to the CAN bus and ready for communication. - * - * param base MCAN peripheral base address. - */ -void MCAN_EnterNormalMode(CAN_Type *base) -{ - /* Reset INIT bit to enter normal mode. */ - base->CCCR &= ~CAN_CCCR_INIT_MASK; - while (0U != (base->CCCR & CAN_CCCR_INIT_MASK)) - { - } -} - -/*! - * brief Gets the default configuration structure. - * - * This function initializes the MCAN configuration structure to default values. The default - * values are as follows. - * config->baudRateA = 500000U; - * config->baudRateD = 1000000U; - * config->enableCanfdNormal = false; - * config->enableCanfdSwitch = false; - * config->enableLoopBackInt = false; - * config->enableLoopBackExt = false; - * config->enableBusMon = false; - * - * param config Pointer to the MCAN configuration structure. - */ -void MCAN_GetDefaultConfig(mcan_config_t *config) -{ - /* Assertion. */ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* Initialize MCAN Module config struct with default value. */ - config->baudRateA = 500000U; - config->baudRateD = 2000000U; - config->enableCanfdNormal = false; - config->enableCanfdSwitch = false; - config->enableLoopBackInt = false; - config->enableLoopBackExt = false; - config->enableBusMon = false; - /* Default protocol timing configuration, time quantum is 16. */ - config->timingConfig.seg1 = 0xAU; - config->timingConfig.seg2 = 0x3U; - config->timingConfig.rJumpwidth = 0x3U; -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) - config->timingConfig.dataseg1 = 0xAU; - config->timingConfig.dataseg2 = 0x3U; - config->timingConfig.datarJumpwidth = 0x3U; -#endif -} - -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) -/*! - * @brief Calculates the segment values for a single bit time for CANFD bus data baud Rate - * - * @param baudRate The canfd bus data speed in bps - * @param tqNum Number of time quanta per bit, range in 3 ~ 33 - * @param pconfig Pointer to the MCAN timing configuration structure. - */ -static void MCAN_FDGetSegments(uint32_t baudRateFD, uint32_t tqNum, mcan_timing_config_t *pconfig) -{ - uint32_t ideal_sp, seg1Temp; - - /* get ideal sample point. */ - if (baudRateFD <= 1000000U) - { - ideal_sp = IDEAL_DATA_SP_1; - } - else if (baudRateFD <= 2000000U) - { - ideal_sp = IDEAL_DATA_SP_2; - } - else if (baudRateFD <= 4000000U) - { - ideal_sp = IDEAL_DATA_SP_3; - } - else - { - ideal_sp = IDEAL_DATA_SP_4; - } - /* distribute time quanta. */ - pconfig->dataseg2 = (uint8_t)(tqNum - (tqNum * ideal_sp) / (uint32_t)IDEAL_SP_FACTOR - 1U); - - if (pconfig->dataseg2 > MAX_DTSEG2) - { - pconfig->dataseg2 = MAX_DTSEG2; - } - - seg1Temp = tqNum - pconfig->dataseg2 - 3U; - - if (seg1Temp > MAX_DTSEG1) - { - pconfig->dataseg2 = (uint8_t)(tqNum - MAX_DTSEG1 - 3U); - pconfig->dataseg1 = MAX_DTSEG1; - } - else - { - pconfig->dataseg1 = (uint8_t)seg1Temp; - } - - /* sjw is the minimum value of phaseSeg1 and phaseSeg2. */ - pconfig->datarJumpwidth = (pconfig->dataseg1 > pconfig->dataseg2) ? pconfig->dataseg2 : pconfig->dataseg1; - if (pconfig->datarJumpwidth > (uint8_t)MAX_DSJW) - { - pconfig->datarJumpwidth = (uint8_t)MAX_DSJW; - } -} - -/*! - * brief Calculates the improved timing values by specific bit rate for CAN FD nominal phase. - * - * This function use to calculates the CAN FD nominal phase timing values according to the given nominal phase bit rate. - * The calculation is based on the recommendation of the CiA 1301 v1.0.0 document. - * - * param baudRate The CAN FD nominal phase speed in bps defined by user, should be less than or equal to 1Mbps. - * param sourceClock_Hz The Source clock frequency in Hz. - * param pconfig Pointer to the MCAN timing configuration structure. - * - * return TRUE if timing configuration found, FALSE if failed to find configuration. - */ -static bool MCAN_CalculateImprovedNominalTimingValues(uint32_t baudRate, - uint32_t sourceClock_Hz, - mcan_timing_config_t *pconfig) -{ - uint32_t clk; /* the clock is tqNumb x baudRate. */ - uint32_t tqNum; /* Numbers of TQ. */ - uint32_t seg1Temp; - bool fgRet = false; - uint32_t spTemp = 1000U; - mcan_timing_config_t configTemp; - - /* Auto Improved Protocal timing for NBTP. */ - for (tqNum = NBTP_MAX_TIME_QUANTA; tqNum >= NBTP_MIN_TIME_QUANTA; tqNum--) - { - clk = baudRate * tqNum; - if (clk > sourceClock_Hz) - { - continue; /* tqNum too large, clk has been exceed sourceClock_Hz. */ - } - - if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) - { - continue; /* Non-supporting: the frequency of clock source is not divisible by target baud rate, the user - should change a divisible baud rate. */ - } - - configTemp.preDivider = (uint16_t)(sourceClock_Hz / clk - 1U); - if (configTemp.preDivider > MAX_NBRP) - { - break; /* The frequency of source clock is too large or the baud rate is too small, the pre-divider could - not handle it. */ - } - /* Calculates the best timing configuration under current tqNum. */ - configTemp.seg2 = (uint8_t)(tqNum - (tqNum * IDEAL_NOMINAL_SP) / (uint32_t)IDEAL_SP_FACTOR - 1U); - - if (configTemp.seg2 > MAX_NTSEG2) - { - configTemp.seg2 = MAX_NTSEG2; - } - - seg1Temp = tqNum - configTemp.seg2 - 3U; - - if (seg1Temp > MAX_NTSEG1) - { - configTemp.seg2 = (uint8_t)(tqNum - MAX_NTSEG1 - 3U); - configTemp.seg1 = MAX_NTSEG1; - } - else - { - configTemp.seg1 = (uint8_t)seg1Temp; - } - - /* sjw is the minimum value of phaseSeg1 and phaseSeg2. */ - configTemp.rJumpwidth = (configTemp.seg1 > configTemp.seg2) ? configTemp.seg2 : configTemp.seg1; - if (configTemp.rJumpwidth > (uint8_t)MAX_NSJW) - { - configTemp.rJumpwidth = (uint8_t)MAX_NSJW; - } - /* Determine whether the calculated timing configuration can get the optimal sampling point. */ - if (((((uint32_t)configTemp.seg2 + 1U) * 1000U) / tqNum) < spTemp) - { - spTemp = (((uint32_t)configTemp.seg2 + 1U) * 1000U) / tqNum; - pconfig->preDivider = configTemp.preDivider; - pconfig->rJumpwidth = configTemp.rJumpwidth; - pconfig->seg1 = configTemp.seg1; - pconfig->seg2 = configTemp.seg2; - } - fgRet = true; - } - return fgRet; -} -/*! - * brief Calculates the improved timing values by specific baudrates for CANFD - * - * param baudRate The CANFD bus control speed in bps defined by user - * param baudRateFD The CANFD bus data speed in bps defined by user - * param sourceClock_Hz The Source clock data speed in bps. - * param pconfig Pointer to the MCAN timing configuration structure. - * - * return TRUE if timing configuration found, FALSE if failed to find configuration - */ -bool MCAN_FDCalculateImprovedTimingValues(uint32_t baudRate, - uint32_t baudRateFD, - uint32_t sourceClock_Hz, - mcan_timing_config_t *pconfig) -{ - uint32_t clk; - uint32_t tqNum; /* Numbers of TQ. */ - bool fgRet = false; - uint16_t preDividerTemp = 1U; - /* observe baud rate maximums */ - assert(baudRate <= MAX_CAN_BAUDRATE); - assert(baudRateFD <= MAX_CANFD_BAUDRATE); - /* Data phase bit rate need greater or equal to nominal phase bit rate. */ - assert(baudRate <= baudRateFD); - - if (baudRate < baudRateFD) - { - /* To minimize errors when processing FD frames, try to get the same bit rate prescaler value for nominal phase - and data phase. */ - while (MCAN_CalculateImprovedNominalTimingValues(baudRate, sourceClock_Hz / preDividerTemp, pconfig)) - { - pconfig->datapreDivider = 0U; - for (tqNum = DBTP_MAX_TIME_QUANTA; tqNum >= DBTP_MIN_TIME_QUANTA; tqNum--) - { - clk = baudRateFD * tqNum; - if (clk > sourceClock_Hz) - { - continue; /* tqNumbrs too large, clk x tqNumbrs has been exceed sourceClock_Hz. */ - } - - if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) - { - continue; /* Non-supporting: the frequency of clock source is not divisible by target bit rate. */ - } - - pconfig->datapreDivider = (uint16_t)(sourceClock_Hz / clk - 1U); - - if (pconfig->datapreDivider > MAX_DBRP) - { - break; /* The frequency of source clock is too large or the bit rate is too small, the pre-divider - could not handle it. */ - } - - if (pconfig->datapreDivider < ((pconfig->preDivider + 1U) * preDividerTemp - 1U)) - { - continue; /* try to get the same bit rate prescaler value for nominal phase and data phase. */ - } - else if (pconfig->datapreDivider == ((pconfig->preDivider + 1U) * preDividerTemp - 1U)) - { - /* Calculates the best data phase timing configuration under current tqNum. */ - MCAN_FDGetSegments(baudRateFD, tqNum, pconfig); - fgRet = true; - break; - } - else - { - break; - } - } - - if (fgRet) - { - /* Find same bit rate prescaler (BRP) configuration in both nominal and data bit timing configurations. - */ - pconfig->preDivider = (pconfig->preDivider + 1U) * preDividerTemp - 1U; - break; - } - else - { - if ((pconfig->datapreDivider <= MAX_DBRP) && (pconfig->datapreDivider != 0U)) - { - /* Can't find same data bit rate prescaler (BRP) configuration under current nominal phase bit rate - prescaler, double the nominal phase bit rate prescaler and recalculate. */ - preDividerTemp++; - } - else - { - break; - } - } - } - } - else - { - if (MCAN_CalculateImprovedTimingValues(baudRate, sourceClock_Hz, pconfig)) - { - /* No need data phase timing configuration, data phase rate equal to nominal phase rate, user don't use Brs - feature. */ - pconfig->datapreDivider = 0U; - pconfig->datarJumpwidth = 0U; - pconfig->dataseg1 = 0U; - pconfig->dataseg2 = 0U; - fgRet = true; - } - } - - return fgRet; -} - -/*! - * brief Sets the MCAN protocol data phase timing characteristic. - * - * This function gives user settings to CAN bus timing characteristic. - * The function is for an experienced user. For less experienced users, call - * the MCAN_Init() and fill the baud rate field with a desired value. - * This provides the default data phase timing characteristics. - * - * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate - * set in MCAN_Init(). - * - * param base MCAN peripheral base address. - * param config Pointer to the timing configuration structure. - */ -void MCAN_SetDataTimingConfig(CAN_Type *base, const mcan_timing_config_t *config) -{ - /* Assertion. */ - assert(NULL != config); - - /* Cleaning previous Timing Setting. */ - base->DBTP &= ~(CAN_DBTP_DSJW_MASK | CAN_DBTP_DTSEG2_MASK | CAN_DBTP_DTSEG1_MASK | CAN_DBTP_DBRP_MASK); - - /* Updating Timing Setting according to configuration structure. */ - base->DBTP |= (CAN_DBTP_DBRP(config->datapreDivider) | CAN_DBTP_DSJW(config->datarJumpwidth) | - CAN_DBTP_DTSEG1(config->dataseg1) | CAN_DBTP_DTSEG2(config->dataseg2)); -} - -/*! - * brief Set Baud Rate of MCAN FD mode. - * - * This function set the baud rate of MCAN FD base on MCAN_FDCalculateImprovedTimingValues API calculated timing values. - * - * param base MCAN peripheral base address. - * param sourceClock_Hz Source Clock in Hz. - * param baudRateN_Bps Nominal Baud Rate in Bps. - * param baudRateD_Bps Data Baud Rate in Bps. - * return kStatus_Success - Set CAN FD baud rate (include Nominal and Data phase) successfully. - */ -status_t MCAN_SetBaudRateFD(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateN_Bps, uint32_t baudRateD_Bps) -{ - mcan_timing_config_t timingCfg; - - if (MCAN_FDCalculateImprovedTimingValues(baudRateN_Bps, baudRateD_Bps, sourceClock_Hz, &timingCfg)) - { - /* Enable write access to the protected conï¬guration registers */ - base->CCCR |= CAN_CCCR_INIT_MASK; - while (0U == (base->CCCR & CAN_CCCR_INIT_MASK)) - { - } - base->CCCR |= CAN_CCCR_CCE_MASK; - /* Update actual timing characteristic. */ - MCAN_SetArbitrationTimingConfig(base, &timingCfg); - MCAN_SetDataTimingConfig(base, &timingCfg); - /* Update TDCO value when not enable loopback mode */ - if (0U == (base->TEST & CAN_TEST_LBCK_MASK)) - { - /* Cleaning previous TDCO Setting. */ - base->TDCR &= ~CAN_TDCR_TDCO_MASK; - /* The TDC offset should be configured as shown in this equation : offset = (DTSEG1 + 2) * (DBRP + 1) */ - if (((uint32_t)timingCfg.dataseg1 + 2U) * (timingCfg.datapreDivider + 1U) < MAX_TDCOFF) - { - base->TDCR |= CAN_TDCR_TDCO(((uint32_t)timingCfg.dataseg1 + 2U) * (timingCfg.datapreDivider + 1U)); - } - else - { - /* Set the Transceiver Delay Compensation offset to max value. */ - base->TDCR |= CAN_TDCR_TDCO(MAX_TDCOFF); - } - } - MCAN_EnterNormalMode(base); - return kStatus_Success; - } - else - { - return kStatus_Fail; - } -} -#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */ - -/*! - * @brief Calculates the segment values for a single bit time for classical CAN - * - * @param baudRate The data speed in bps - * @param tqNum Number of time quantas per bit, range in 4~385 - * @param pconfig Pointer to the MCAN timing configuration structure. - */ -static void MCAN_GetSegments(uint32_t baudRate, uint32_t tqNum, mcan_timing_config_t *pconfig) -{ - uint32_t ideal_sp, seg1Temp; - - /* get ideal sample point. */ - if (baudRate >= 1000000U) - { - ideal_sp = IDEAL_SP_LOW; - } - else if (baudRate >= 800000U) - { - ideal_sp = IDEAL_SP_MID; - } - else - { - ideal_sp = IDEAL_SP_HIGH; - } - - /* distribute time quanta. */ - pconfig->seg2 = (uint8_t)(tqNum - (tqNum * ideal_sp) / (uint32_t)IDEAL_SP_FACTOR - 1U); - - if (pconfig->seg2 > MAX_NTSEG2) - { - pconfig->seg2 = MAX_NTSEG2; - } - - seg1Temp = tqNum - pconfig->seg2 - 3U; - - if (seg1Temp > MAX_NTSEG1) - { - pconfig->seg2 = (uint8_t)(tqNum - MAX_NTSEG1 - 3U); - pconfig->seg1 = MAX_NTSEG1; - } - else - { - pconfig->seg1 = (uint8_t)seg1Temp; - } - - /* sjw is the minimum value of phaseSeg1 and phaseSeg2. */ - pconfig->rJumpwidth = (pconfig->seg1 > pconfig->seg2) ? pconfig->seg2 : pconfig->seg1; - if (pconfig->rJumpwidth > (uint8_t)MAX_NSJW) - { - pconfig->rJumpwidth = (uint8_t)MAX_NSJW; - } -} - -/*! - * brief Calculates the improved timing values by specific baudrates for classical CAN - * - * param baudRate The classical CAN speed in bps defined by user - * param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching - * param pconfig Pointer to the MCAN timing configuration structure. - * - * return TRUE if timing configuration found, FALSE if failed to find configuration - */ -bool MCAN_CalculateImprovedTimingValues(uint32_t baudRate, uint32_t sourceClock_Hz, mcan_timing_config_t *pconfig) -{ - uint32_t clk; /* the clock is tqNumb x baudRate. */ - uint32_t tqNum; /* Numbers of TQ. */ - bool fgRet = false; - uint32_t spTemp = 1000U; - mcan_timing_config_t configTemp = {0}; - /* observe baud rate maximums. */ - assert(baudRate <= MAX_CAN_BAUDRATE); - - /* Auto Improved Protocal timing for NBTP. */ - for (tqNum = NBTP_MAX_TIME_QUANTA; tqNum >= NBTP_MIN_TIME_QUANTA; tqNum--) - { - clk = baudRate * tqNum; - if (clk > sourceClock_Hz) - { - continue; /* tqNum too large, clk has been exceed sourceClock_Hz. */ - } - - if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) - { - continue; /* Non-supporting: the frequency of clock source is not divisible by target baud rate, the user - should change a divisible baud rate. */ - } - - configTemp.preDivider = (uint16_t)(sourceClock_Hz / clk - 1U); - if (configTemp.preDivider > MAX_NBRP) - { - break; /* The frequency of source clock is too large or the baud rate is too small, the pre-divider could - not handle it. */ - } - /* Calculates the best timing configuration under current tqNum. */ - MCAN_GetSegments(baudRate, tqNum, &configTemp); - /* Determine whether the calculated timing configuration can get the optimal sampling point. */ - if (((((uint32_t)configTemp.seg2 + 1U) * 1000U) / tqNum) < spTemp) - { - spTemp = (((uint32_t)configTemp.seg2 + 1U) * 1000U) / tqNum; - pconfig->preDivider = configTemp.preDivider; - pconfig->rJumpwidth = configTemp.rJumpwidth; - pconfig->seg1 = configTemp.seg1; - pconfig->seg2 = configTemp.seg2; - } - fgRet = true; - } - return fgRet; -} -/*! - * brief Set Baud Rate of MCAN classic mode. - * - * This function set the baud rate of MCAN base on MCAN_CalculateImprovedTimingValues() API calculated timing values. - * - * param base MCAN peripheral base address. - * param sourceClock_Hz Source Clock in Hz. - * param baudRate_Bps Baud Rate in Bps. - * return kStatus_Success - Set CAN baud rate (only has Nominal phase) successfully. - */ -status_t MCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Bps) -{ - mcan_timing_config_t timingCfg; - - if (MCAN_CalculateImprovedTimingValues(baudRate_Bps, sourceClock_Hz, &timingCfg)) - { - /* Enable write access to the protected conï¬guration registers */ - base->CCCR |= CAN_CCCR_INIT_MASK; - while (0U == (base->CCCR & CAN_CCCR_INIT_MASK)) - { - } - base->CCCR |= CAN_CCCR_CCE_MASK; - /* Update actual timing characteristic. */ - MCAN_SetArbitrationTimingConfig(base, &timingCfg); - MCAN_EnterNormalMode(base); - return kStatus_Success; - } - else - { - return kStatus_Fail; - } -} - -/*! - * brief Sets the MCAN protocol arbitration phase timing characteristic. - * - * This function gives user settings to CAN bus timing characteristic. - * The function is for an experienced user. For less experienced users, call - * the MCAN_Init() and fill the baud rate field with a desired value. - * This provides the default arbitration phase timing characteristics. - * - * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate - * set in MCAN_Init(). - * - * param base MCAN peripheral base address. - * param config Pointer to the timing configuration structure. - */ -void MCAN_SetArbitrationTimingConfig(CAN_Type *base, const mcan_timing_config_t *config) -{ - /* Assertion. */ - assert(NULL != config); - - /* Cleaning previous Timing Setting. */ - base->NBTP &= ~(CAN_NBTP_NSJW_MASK | CAN_NBTP_NTSEG2_MASK | CAN_NBTP_NTSEG1_MASK | CAN_NBTP_NBRP_MASK); - - /* Updating Timing Setting according to configuration structure. */ - base->NBTP |= (CAN_NBTP_NBRP(config->preDivider) | CAN_NBTP_NSJW(config->rJumpwidth) | - CAN_NBTP_NTSEG1(config->seg1) | CAN_NBTP_NTSEG2(config->seg2)); -} - -/*! - * brief Set filter configuration. - * - * This function sets remote and non masking frames in global filter configuration, - * also the start address, list size in standard/extended ID filter configuration. - * - * param base MCAN peripheral base address. - * param config The MCAN filter configuration. - */ -void MCAN_SetFilterConfig(CAN_Type *base, const mcan_frame_filter_config_t *config) -{ - /* Set global configuration of remote/nonmasking frames, set filter address and list size. */ - if (config->idFormat == kMCAN_FrameIDStandard) - { - base->GFC |= CAN_GFC_RRFS(config->remFrame) | CAN_GFC_ANFS(config->nmFrame); - base->SIDFC |= CAN_SIDFC_FLSSA(config->address >> CAN_SIDFC_FLSSA_SHIFT) | CAN_SIDFC_LSS(config->listSize); - } - else - { - base->GFC |= CAN_GFC_RRFE(config->remFrame) | CAN_GFC_ANFE(config->nmFrame); - base->XIDFC |= CAN_XIDFC_FLESA(config->address >> CAN_XIDFC_FLESA_SHIFT) | CAN_XIDFC_LSE(config->listSize); - } -} - -/*! - * brief Configures an MCAN receive fifo 0 buffer. - * - * This function sets start address, element size, watermark, operation mode - * and datafield size of the recieve fifo 0. - * - * param base MCAN peripheral base address. - * param config The receive fifo 0 configuration structure. - */ -void MCAN_SetRxFifo0Config(CAN_Type *base, const mcan_rx_fifo_config_t *config) -{ - /* Set Rx FIFO 0 start address, element size, watermark, operation mode. */ - base->RXF0C |= CAN_RXF0C_F0SA(config->address >> CAN_RXF0C_F0SA_SHIFT) | CAN_RXF0C_F0S(config->elementSize) | - CAN_RXF0C_F0WM(config->watermark) | CAN_RXF0C_F0OM(config->opmode); - /* Set Rx FIFO 0 data field size */ - base->RXESC |= CAN_RXESC_F0DS(config->datafieldSize); -} - -/*! - * brief Configures an MCAN receive fifo 1 buffer. - * - * This function sets start address, element size, watermark, operation mode - * and datafield size of the recieve fifo 1. - * - * param base MCAN peripheral base address. - * param config The receive fifo 1 configuration structure. - */ -void MCAN_SetRxFifo1Config(CAN_Type *base, const mcan_rx_fifo_config_t *config) -{ - /* Set Rx FIFO 1 start address, element size, watermark, operation mode. */ - base->RXF1C |= CAN_RXF1C_F1SA(config->address >> CAN_RXF1C_F1SA_SHIFT) | CAN_RXF1C_F1S(config->elementSize) | - CAN_RXF1C_F1WM(config->watermark) | CAN_RXF1C_F1OM(config->opmode); - /* Set Rx FIFO 1 data field size */ - base->RXESC |= CAN_RXESC_F1DS(config->datafieldSize); -} - -/*! - * brief Configures an MCAN receive buffer. - * - * This function sets start address and datafield size of the recieve buffer. - * - * param base MCAN peripheral base address. - * param config The receive buffer configuration structure. - */ -void MCAN_SetRxBufferConfig(CAN_Type *base, const mcan_rx_buffer_config_t *config) -{ - /* Set Rx Buffer start address. */ - base->RXBC |= CAN_RXBC_RBSA(config->address >> CAN_RXBC_RBSA_SHIFT); - /* Set Rx Buffer data field size */ - base->RXESC |= CAN_RXESC_RBDS(config->datafieldSize); -} - -/*! - * brief Configures an MCAN transmit event fifo. - * - * This function sets start address, element size, watermark of the transmit event fifo. - * - * param base MCAN peripheral base address. - * param config The transmit event fifo configuration structure. - */ -void MCAN_SetTxEventFifoConfig(CAN_Type *base, const mcan_tx_fifo_config_t *config) -{ - /* Set TX Event FIFO start address, element size, watermark. */ - base->TXEFC |= CAN_TXEFC_EFSA(config->address >> CAN_TXEFC_EFSA_SHIFT) | CAN_TXEFC_EFS(config->elementSize) | - CAN_TXEFC_EFWM(config->watermark); -} - -/*! - * brief Configures an MCAN transmit buffer. - * - * This function sets start address, element size, fifo/queue mode and datafield - * size of the transmit buffer. - * - * param base MCAN peripheral base address. - * param config The transmit buffer configuration structure. - */ -void MCAN_SetTxBufferConfig(CAN_Type *base, const mcan_tx_buffer_config_t *config) -{ - assert((config->dedicatedSize + config->fqSize) <= 32U); - - /* Set Tx Buffer start address, size, fifo/queue mode. */ - base->TXBC |= CAN_TXBC_TBSA(config->address >> CAN_TXBC_TBSA_SHIFT) | CAN_TXBC_NDTB(config->dedicatedSize) | - CAN_TXBC_TFQS(config->fqSize) | CAN_TXBC_TFQM(config->mode); - /* Set Tx Buffer data field size */ - base->TXESC |= CAN_TXESC_TBDS(config->datafieldSize); -} - -/*! - * brief Set standard message ID filter element configuration. - * - * param base MCAN peripheral base address. - * param config The MCAN filter configuration. - * param filter The MCAN standard message ID filter element configuration. - * param idx The standard message ID filter element index. - */ -void MCAN_SetSTDFilterElement(CAN_Type *base, - const mcan_frame_filter_config_t *config, - const mcan_std_filter_element_config_t *filter, - uint8_t idx) -{ - uint32_t *elementAddress = NULL; - elementAddress = (uint32_t *)(MCAN_GetMsgRAMBase(base) + config->address + idx * 4U); - (void)memcpy((void *)elementAddress, (const void *)filter, sizeof(mcan_std_filter_element_config_t)); -} - -/*! - * brief Set extended message ID filter element configuration. - * - * param base MCAN peripheral base address. - * param config The MCAN filter configuration. - * param filter The MCAN extended message ID filter element configuration. - * param idx The extended message ID filter element index. - */ -void MCAN_SetEXTFilterElement(CAN_Type *base, - const mcan_frame_filter_config_t *config, - const mcan_ext_filter_element_config_t *filter, - uint8_t idx) -{ - uint32_t *elementAddress = NULL; - elementAddress = (uint32_t *)(MCAN_GetMsgRAMBase(base) + config->address + idx * 8U); - (void)memcpy((void *)elementAddress, (const void *)filter, sizeof(mcan_ext_filter_element_config_t)); -} - -static uint32_t MCAN_GetRxFifo0ElementAddress(CAN_Type *base) -{ - uint32_t eSize; - uint32_t eAddress; - eSize = (base->RXESC & CAN_RXESC_F0DS_MASK) >> CAN_RXESC_F0DS_SHIFT; - if (eSize < 5U) - { - eSize += 4U; - } - else - { - eSize = eSize * 4U - 10U; - } - eAddress = base->RXF0C & CAN_RXF0C_F0SA_MASK; - eAddress += ((base->RXF0S & CAN_RXF0S_F0GI_MASK) >> CAN_RXF0S_F0GI_SHIFT) * eSize * 4U; - return eAddress; -} - -static uint32_t MCAN_GetRxFifo1ElementAddress(CAN_Type *base) -{ - uint32_t eSize; - uint32_t eAddress; - eSize = (base->RXESC & CAN_RXESC_F1DS_MASK) >> CAN_RXESC_F1DS_SHIFT; - if (eSize < 5U) - { - eSize += 4U; - } - else - { - eSize = eSize * 4U - 10U; - } - eAddress = base->RXF1C & CAN_RXF1C_F1SA_MASK; - eAddress += ((base->RXF1S & CAN_RXF1S_F1GI_MASK) >> CAN_RXF1S_F1GI_SHIFT) * eSize * 4U; - return eAddress; -} - -static uint32_t MCAN_GetRxBufferElementAddress(CAN_Type *base, uint8_t idx) -{ - assert(idx <= 63U); - uint32_t eSize; - eSize = (base->RXESC & CAN_RXESC_RBDS_MASK) >> CAN_RXESC_RBDS_SHIFT; - if (eSize < 5U) - { - eSize += 4U; - } - else - { - eSize = eSize * 4U - 10U; - } - return (base->RXBC & CAN_RXBC_RBSA_MASK) + idx * eSize * 4U; -} - -static uint32_t MCAN_GetTxBufferElementAddress(CAN_Type *base, uint8_t idx) -{ - assert(idx <= 31U); - uint32_t eSize; - eSize = (base->TXESC & CAN_TXESC_TBDS_MASK) >> CAN_TXESC_TBDS_SHIFT; - if (eSize < 5U) - { - eSize += 4U; - } - else - { - eSize = eSize * 4U - 10U; - } - return (base->TXBC & CAN_TXBC_TBSA_MASK) + idx * eSize * 4U; -} - -/*! - * brief Gets the Tx buffer request pending status. - * - * This function returns Tx Message Buffer transmission request pending status. - * - * param base MCAN peripheral base address. - * param idx The MCAN Tx Buffer index. - */ -uint32_t MCAN_IsTransmitRequestPending(CAN_Type *base, uint8_t idx) -{ - return (base->TXBRP & ((uint32_t)1U << idx)) >> (uint32_t)idx; -} - -/*! - * brief Gets the Tx buffer transmission occurred status. - * - * This function returns Tx Message Buffer transmission occurred status. - * - * param base MCAN peripheral base address. - * param idx The MCAN Tx Buffer index. - */ -uint32_t MCAN_IsTransmitOccurred(CAN_Type *base, uint8_t idx) -{ - return (base->TXBTO & ((uint32_t)1U << idx)) >> (uint32_t)idx; -} - -/*! - * brief Writes an MCAN Message to the Transmit Buffer. - * - * This function writes a CAN Message to the specified Transmit Message Buffer - * and changes the Message Buffer state to start CAN Message transmit. After - * that the function returns immediately. - * - * param base MCAN peripheral base address. - * param idx The MCAN Tx Buffer index. - * param pTxFrame Pointer to CAN message frame to be sent. - */ -status_t MCAN_WriteTxBuffer(CAN_Type *base, uint8_t idx, const mcan_tx_buffer_frame_t *pTxFrame) -{ - /* Assertion. */ - assert(NULL != pTxFrame); - - status_t status; - uint8_t *elementAddress = NULL; - uint8_t *elementPayloadAddress = NULL; - - if (0U == MCAN_IsTransmitRequestPending(base, idx)) - { - elementAddress = (uint8_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetTxBufferElementAddress(base, idx)); - elementPayloadAddress = (uint8_t *)((uint32_t)elementAddress + 8U); - - /* Write 2 words configuration field. */ - (void)memcpy(elementAddress, (const uint8_t *)pTxFrame, 8U); - /* Write data field. */ - (void)memcpy(elementPayloadAddress, pTxFrame->data, pTxFrame->size); - status = kStatus_Success; - } - else - { - status = kStatus_Fail; - } - - return status; -} - -/*! - * brief Reads an MCAN Message from Rx Buffer. - * - * This function reads a CAN message from the Rx Buffer in the Message RAM. - * - * param base MCAN peripheral base address. - * param idx The MCAN Rx Buffer index. - * param pRxFrame Pointer to CAN message frame structure for reception. - * retval kStatus_Success - Read Message from Rx Buffer successfully. - */ -status_t MCAN_ReadRxBuffer(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *pRxFrame) -{ - /* Assertion. */ - assert(NULL != pRxFrame); - - mcan_rx_buffer_frame_t *elementAddress = NULL; - uint32_t u4PayloadLength = (uint32_t)(pRxFrame->size) + 8U; - - elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxBufferElementAddress(base, idx)); - (void)memcpy((void *)pRxFrame, (void *)elementAddress, u4PayloadLength); - - return kStatus_Success; -} - -/*! - * brief Reads an MCAN Message from Rx FIFO. - * - * This function reads a CAN message from the Rx FIFO in the Message RAM. - * - * param base MCAN peripheral base address. - * param fifoBlock Rx FIFO block 0 or 1. - * param pRxFrame Pointer to CAN message frame structure for reception. - * retval kStatus_Success - Read Message from Rx FIFO successfully. - */ -status_t MCAN_ReadRxFifo(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *pRxFrame) -{ - /* Assertion. */ - assert((0U == fifoBlock) || (1U == fifoBlock)); - assert(NULL != pRxFrame); - - mcan_rx_buffer_frame_t *elementAddress = NULL; - - if (0U == fifoBlock) - { - if ((base->RXF0S & CAN_RXF0S_F0FL_MASK) != 0U) - { - elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxFifo0ElementAddress(base)); - } - else - { - return kStatus_Fail; - } - } - else - { - if ((base->RXF1S & CAN_RXF1S_F1FL_MASK) != 0U) - { - elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxFifo1ElementAddress(base)); - } - else - { - return kStatus_Fail; - } - } - (void)memcpy(pRxFrame, elementAddress, 8U); - pRxFrame->data = (uint8_t *)((uint32_t)elementAddress + 8U); - /* Acknowledge the read. */ - if (0U == fifoBlock) - { - base->RXF0A = (base->RXF0S & CAN_RXF0S_F0GI_MASK) >> CAN_RXF0S_F0GI_SHIFT; - } - else - { - base->RXF1A = (base->RXF1S & CAN_RXF1S_F1GI_MASK) >> CAN_RXF1S_F1GI_SHIFT; - } - return kStatus_Success; -} - -/*! - * brief Performs a polling send transaction on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * param base MCAN peripheral base pointer. - * param idx The MCAN buffer index. - * param pTxFrame Pointer to CAN message frame to be sent. - * retval kStatus_Success - Write Tx Message Buffer Successfully. - * retval kStatus_Fail - Tx Message Buffer is currently in use. - */ -status_t MCAN_TransferSendBlocking(CAN_Type *base, uint8_t idx, mcan_tx_buffer_frame_t *pTxFrame) -{ - status_t status; - - if (kStatus_Success == MCAN_WriteTxBuffer(base, idx, pTxFrame)) - { - MCAN_TransmitAddRequest(base, idx); - - /* Wait until message sent out. */ - while (0U == MCAN_IsTransmitOccurred(base, idx)) - { - } - status = kStatus_Success; - } - else - { - status = kStatus_Fail; - } - - return status; -} - -/*! - * brief Performs a polling receive transaction on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * param base MCAN peripheral base pointer. - * param idx The MCAN buffer index. - * param pRxFrame Pointer to CAN message frame structure for reception. - * retval kStatus_Success - Read Rx Message Buffer Successfully. - * retval kStatus_Fail - No new message. - */ -status_t MCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *pRxFrame) -{ - assert(idx <= 63U); - - status_t status = kStatus_Success; - -#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) - uint32_t u4Retry = MCAN_RETRY_TIMES; -#endif - - while (!MCAN_GetRxBufferStatusFlag(base, idx)) - { -#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) - if (0U == u4Retry--) - { - status = kStatus_Fail; - } -#endif - } -#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) - if (kStatus_Success == status) -#endif - { - MCAN_ClearRxBufferStatusFlag(base, idx); - status = MCAN_ReadRxBuffer(base, idx, pRxFrame); - } - - return status; -} - -/*! - * brief Performs a polling receive transaction from Rx FIFO on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * param base MCAN peripheral base pointer. - * param fifoBlock Rx FIFO block, 0 or 1. - * param pRxFrame Pointer to CAN message frame structure for reception. - * retval kStatus_Success - Read Message from Rx FIFO successfully. - * retval kStatus_Fail - No new message in Rx FIFO. - */ -status_t MCAN_TransferReceiveFifoBlocking(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *pRxFrame) -{ - assert((0U == fifoBlock) || (1U == fifoBlock)); - - status_t status = kStatus_Success; - uint32_t maskCanIR; -#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) - uint32_t u4Retry = MCAN_RETRY_TIMES; -#endif - - maskCanIR = (0U == fifoBlock) ? CAN_IR_RF0N_MASK : CAN_IR_RF1N_MASK; - - while (0U == MCAN_GetStatusFlag(base, maskCanIR)) - { -#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) - if (0U == u4Retry--) - { - status = kStatus_Fail; - } -#endif - } - -#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) - if (kStatus_Success == status) -#endif - { - MCAN_ClearStatusFlag(base, maskCanIR); - status = MCAN_ReadRxFifo(base, fifoBlock, pRxFrame); - } - - return status; -} - -/*! - * brief Initializes the MCAN handle. - * - * This function initializes the MCAN handle, which can be used for other MCAN - * transactional APIs. Usually, for a specified MCAN instance, - * call this API once to get the initialized handle. - * - * param base MCAN peripheral base address. - * param handle MCAN handle pointer. - * param callback The callback function. - * param userData The parameter of the callback function. - */ -void MCAN_TransferCreateHandle(CAN_Type *base, mcan_handle_t *handle, mcan_transfer_callback_t callback, void *userData) -{ - assert(NULL != handle); - - uint8_t instance; - - /* Clean MCAN transfer handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Get instance from peripheral base address. */ - instance = (uint8_t)MCAN_GetInstance(base); - - /* Save the context in global variables to support the double weak mechanism. */ - s_mcanHandle[instance] = handle; - - /* Register Callback function. */ - handle->callback = callback; - handle->userData = userData; - - s_mcanIsr = MCAN_TransferHandleIRQ; - - /* We Enable Error & Status interrupt here, because this interrupt just - * report current status of MCAN module through Callback function. - * It is insignificance without a available callback function. - */ - if (handle->callback != NULL) - { - MCAN_EnableInterrupts(base, 0U, - (uint32_t)kMCAN_BusOffInterruptEnable | (uint32_t)kMCAN_ErrorInterruptEnable | - (uint32_t)kMCAN_WarningInterruptEnable); - } - else - { - MCAN_DisableInterrupts(base, (uint32_t)kMCAN_BusOffInterruptEnable | (uint32_t)kMCAN_ErrorInterruptEnable | - (uint32_t)kMCAN_WarningInterruptEnable); - } - - /* Enable interrupts in NVIC. */ - (void)EnableIRQ((IRQn_Type)(s_mcanIRQ[instance][0])); - (void)EnableIRQ((IRQn_Type)(s_mcanIRQ[instance][1])); -} - -/*! - * brief Sends a message using IRQ. - * - * This function sends a message using IRQ. This is a non-blocking function, which returns - * right away. When messages have been sent out, the send callback function is called. - * - * param base MCAN peripheral base address. - * param handle MCAN handle pointer. - * param xfer MCAN Buffer transfer structure. See the #mcan_buffer_transfer_t. - * retval kStatus_Success Start Tx Buffer sending process successfully. - * retval kStatus_Fail Write Tx Buffer failed. - * retval kStatus_MCAN_TxBusy Tx Buffer is in use. - */ -status_t MCAN_TransferSendNonBlocking(CAN_Type *base, mcan_handle_t *handle, mcan_buffer_transfer_t *xfer) -{ - /* Assertion. */ - assert(NULL != handle); - assert(NULL != xfer); - assert(xfer->bufferIdx <= 63U); - - status_t status; - - /* Check if Tx Buffer is idle. */ - if ((uint8_t)kMCAN_StateIdle == handle->bufferState[xfer->bufferIdx]) - { - /* Distinguish transmit type. */ - if ((uint8_t)kMCAN_FrameTypeRemote == xfer->frame->xtd) - { - handle->bufferState[xfer->bufferIdx] = (uint8_t)kMCAN_StateTxRemote; - - /* Register user Frame buffer to receive remote Frame. */ - handle->bufferFrameBuf[xfer->bufferIdx] = xfer->frame; - } - else - { - handle->bufferState[xfer->bufferIdx] = (uint8_t)kMCAN_StateTxData; - } - - if (kStatus_Success == MCAN_WriteTxBuffer(base, xfer->bufferIdx, xfer->frame)) - { - /* Enable Buffer Interrupt. */ - MCAN_EnableTransmitBufferInterrupts(base, xfer->bufferIdx); - MCAN_EnableInterrupts(base, 0U, CAN_IE_TCE_MASK); - - MCAN_TransmitAddRequest(base, xfer->bufferIdx); - - status = kStatus_Success; - } - else - { - handle->bufferState[xfer->bufferIdx] = (uint8_t)kMCAN_StateIdle; - status = kStatus_Fail; - } - } - else - { - status = kStatus_MCAN_TxBusy; - } - - return status; -} - -/*! - * brief Receives a message from Rx FIFO using IRQ. - * - * This function receives a message using IRQ. This is a non-blocking function, which returns - * right away. When all messages have been received, the receive callback function is called. - * - * param base MCAN peripheral base address. - * param handle MCAN handle pointer. - * param fifoBlock Rx FIFO block, 0 or 1. - * param xfer MCAN Rx FIFO transfer structure. See the ref mcan_fifo_transfer_t. - * retval kStatus_Success - Start Rx FIFO receiving process successfully. - * retval kStatus_MCAN_RxFifo0Busy - Rx FIFO 0 is currently in use. - * retval kStatus_MCAN_RxFifo1Busy - Rx FIFO 1 is currently in use. - */ -status_t MCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, - uint8_t fifoBlock, - mcan_handle_t *handle, - mcan_fifo_transfer_t *xfer) -{ - /* Assertion. */ - assert((0U == fifoBlock) || (1U == fifoBlock)); - assert(NULL != handle); - assert(NULL != xfer); - - status_t status; - - /* Check if Message Buffer is idle. */ - if ((uint8_t)kMCAN_StateIdle == handle->rxFifoState) - { - handle->rxFifoState = (uint8_t)kMCAN_StateRxFifo; - - /* Register Message Buffer. */ - handle->rxFifoFrameBuf = xfer->frame; - - /* Enable FIFO Interrupt. */ - if (1U == fifoBlock) - { - MCAN_EnableInterrupts(base, 0U, CAN_IE_RF1NE_MASK); - } - else - { - MCAN_EnableInterrupts(base, 0U, CAN_IE_RF0NE_MASK); - } - status = kStatus_Success; - } - else - { - status = (1U == fifoBlock) ? kStatus_MCAN_RxFifo1Busy : kStatus_MCAN_RxFifo0Busy; - } - - return status; -} - -/*! - * brief Aborts the interrupt driven message send process. - * - * This function aborts the interrupt driven message send process. - * - * param base MCAN peripheral base address. - * param handle MCAN handle pointer. - * param bufferIdx The MCAN Buffer index. - */ -void MCAN_TransferAbortSend(CAN_Type *base, mcan_handle_t *handle, uint8_t bufferIdx) -{ - /* Assertion. */ - assert(NULL != handle); - assert(bufferIdx <= 63U); - - /* Disable Message Buffer Interrupt. */ - MCAN_DisableTransmitBufferInterrupts(base, bufferIdx); - - /* Cancel send request. */ - MCAN_TransmitCancelRequest(base, bufferIdx); - - /* Un-register handle. */ - handle->bufferFrameBuf[bufferIdx] = NULL; - - handle->bufferState[bufferIdx] = (uint8_t)kMCAN_StateIdle; -} - -/*! - * brief Aborts the interrupt driven message receive from Rx FIFO process. - * - * This function aborts the interrupt driven message receive from Rx FIFO process. - * - * param base MCAN peripheral base address. - * param fifoBlock MCAN Fifo block, 0 or 1. - * param handle MCAN handle pointer. - */ -void MCAN_TransferAbortReceiveFifo(CAN_Type *base, uint8_t fifoBlock, mcan_handle_t *handle) -{ - /* Assertion. */ - assert(NULL != handle); - assert((0U == fifoBlock) || (1U == fifoBlock)); - - /* Check if Rx FIFO is enabled. */ - if (1U == fifoBlock) - { - /* Disable Rx Message FIFO Interrupts. */ - MCAN_DisableInterrupts(base, CAN_IE_RF1NE_MASK); - } - else - { - MCAN_DisableInterrupts(base, CAN_IE_RF0NE_MASK); - } - /* Un-register handle. */ - handle->rxFifoFrameBuf = NULL; - - handle->rxFifoState = (uint8_t)kMCAN_StateIdle; -} - -/*! - * brief MCAN IRQ handle function. - * - * This function handles the MCAN Error, the Buffer, and the Rx FIFO IRQ request. - * - * param base MCAN peripheral base address. - * param handle MCAN handle pointer. - */ -void MCAN_TransferHandleIRQ(CAN_Type *base, mcan_handle_t *handle) -{ - /* Assertion. */ - assert(NULL != handle); - - status_t status = kStatus_MCAN_UnHandled; - uint32_t valueIR; - uint32_t result; - - /* Store Current MCAN Module Error and Status. */ - valueIR = base->IR; - - do - { - if (0U != (valueIR & ((uint32_t)kMCAN_ErrorWarningIntFlag | (uint32_t)kMCAN_ErrorPassiveIntFlag | - (uint32_t)kMCAN_BusOffIntFlag))) - { - /* Solve error. */ - result = (valueIR & ((uint32_t)kMCAN_ErrorWarningIntFlag | (uint32_t)kMCAN_ErrorPassiveIntFlag | - (uint32_t)kMCAN_BusOffIntFlag)); - status = kStatus_MCAN_ErrorStatus; - } - else if (0U != (valueIR & (uint32_t)kMCAN_TxTransmitCompleteFlag)) - { - /* Solve Tx interrupt. */ - uint8_t idx = 0U; - for (; idx < (uint8_t)((base->TXBC & CAN_TXBC_NDTB_MASK) >> CAN_TXBC_NDTB_SHIFT); idx++) - { - /* Get the lowest unhandled Tx Message Buffer */ - if (0U != MCAN_IsTransmitOccurred(base, idx)) - { - if ((base->TXBTIE & ((uint32_t)1U << idx)) != 0U) - { - MCAN_TransferAbortSend(base, handle, idx); - } - } - } - result = (uint32_t)kMCAN_TxTransmitCompleteFlag; - status = kStatus_MCAN_TxIdle; - } - else if (0U != (valueIR & (uint32_t)kMCAN_RxFifo0NewFlag)) - { - (void)MCAN_ReadRxFifo(base, 0U, handle->rxFifoFrameBuf); - result = (uint32_t)kMCAN_RxFifo0NewFlag; - status = kStatus_MCAN_RxFifo0Idle; - MCAN_TransferAbortReceiveFifo(base, 0U, handle); - } - else if (0U != (valueIR & (uint32_t)kMCAN_RxFifo0LostFlag)) - { - result = (uint32_t)kMCAN_RxFifo0LostFlag; - status = kStatus_MCAN_RxFifo0Lost; - } - else if (0U != (valueIR & (uint32_t)kMCAN_RxFifo1NewFlag)) - { - (void)MCAN_ReadRxFifo(base, 1U, handle->rxFifoFrameBuf); - result = (uint32_t)kMCAN_RxFifo1NewFlag; - status = kStatus_MCAN_RxFifo1Idle; - MCAN_TransferAbortReceiveFifo(base, 1U, handle); - } - else if (0U != (valueIR & (uint32_t)kMCAN_RxFifo1LostFlag)) - { - result = (uint32_t)kMCAN_RxFifo1LostFlag; - status = kStatus_MCAN_RxFifo0Lost; - } - else - { - /* Handle the interrupt flag unsupported in current version of MCAN driver. - * User can get these unsupported interrupt flags by callback function, - * we can clear directly in the handler to prevent endless loop. - */ - result = valueIR; - result &= ~((uint32_t)kMCAN_ErrorWarningIntFlag | (uint32_t)kMCAN_ErrorPassiveIntFlag | - (uint32_t)kMCAN_BusOffIntFlag | (uint32_t)kMCAN_TxTransmitCompleteFlag | - (uint32_t)kMCAN_RxFifo0NewFlag | (uint32_t)kMCAN_RxFifo0LostFlag | - (uint32_t)kMCAN_RxFifo1NewFlag | (uint32_t)kMCAN_RxFifo1LostFlag); - } - - /* Clear Error interrupt, resolved Rx FIFO, Tx Buffer IRQ and other unsupported interrupt flags. */ - MCAN_ClearStatusFlag(base, result); - - /* Calling Callback Function if has one. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, status, result, handle->userData); - } - - /* Reset return status */ - status = kStatus_MCAN_UnHandled; - - /* Store Current MCAN Module Error and Status. */ - valueIR = base->IR; - } while (0U != valueIR); -} - -#if defined(CAN0) -void CAN0_IRQ0_DriverIRQHandler(void); -void CAN0_IRQ0_DriverIRQHandler(void) -{ - assert(NULL != s_mcanHandle[0]); - - s_mcanIsr(CAN0, s_mcanHandle[0]); - SDK_ISR_EXIT_BARRIER; -} - -void CAN0_IRQ1_DriverIRQHandler(void); -void CAN0_IRQ1_DriverIRQHandler(void) -{ - assert(NULL != s_mcanHandle[0]); - - s_mcanIsr(CAN0, s_mcanHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CAN1) -void CAN1_IRQ0_DriverIRQHandler(void); -void CAN1_IRQ0_DriverIRQHandler(void) -{ - assert(NULL != s_mcanHandle[1]); - - s_mcanIsr(CAN1, s_mcanHandle[1]); - SDK_ISR_EXIT_BARRIER; -} - -void CAN1_IRQ1_DriverIRQHandler(void); -void CAN1_IRQ1_DriverIRQHandler(void) -{ - assert(NULL != s_mcanHandle[1]); - - s_mcanIsr(CAN1, s_mcanHandle[1]); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_mcan.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_mcan.h deleted file mode 100644 index 7b0ee3e1c36..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_mcan.h +++ /dev/null @@ -1,1056 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_MCAN_H_ -#define _FSL_MCAN_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup mcan - * @{ - */ - -/****************************************************************************** - * Definitions - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief MCAN driver version. */ -#define FSL_MCAN_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) -/*@}*/ - -#ifndef MCAN_RETRY_TIMES -/* Define to 0 by default means to retry infinitely until the flag is assert/de-assert. - * User can change the macro with their requirement by defined the MACRO. - */ -#define MCAN_RETRY_TIMES (0U) -#endif - -/*! @brief MCAN transfer status. */ -enum -{ - kStatus_MCAN_TxBusy = MAKE_STATUS(kStatusGroup_MCAN, 0), /*!< Tx Buffer is Busy. */ - kStatus_MCAN_TxIdle = MAKE_STATUS(kStatusGroup_MCAN, 1), /*!< Tx Buffer is Idle. */ - kStatus_MCAN_RxBusy = MAKE_STATUS(kStatusGroup_MCAN, 2), /*!< Rx Buffer is Busy. */ - kStatus_MCAN_RxIdle = MAKE_STATUS(kStatusGroup_MCAN, 3), /*!< Rx Buffer is Idle. */ - kStatus_MCAN_RxFifo0New = MAKE_STATUS(kStatusGroup_MCAN, 4), /*!< New message written to Rx FIFO 0. */ - kStatus_MCAN_RxFifo0Idle = MAKE_STATUS(kStatusGroup_MCAN, 5), /*!< Rx FIFO 0 is Idle. */ - kStatus_MCAN_RxFifo0Watermark = MAKE_STATUS(kStatusGroup_MCAN, 6), /*!< Rx FIFO 0 fill level reached watermark. */ - kStatus_MCAN_RxFifo0Full = MAKE_STATUS(kStatusGroup_MCAN, 7), /*!< Rx FIFO 0 full. */ - kStatus_MCAN_RxFifo0Lost = MAKE_STATUS(kStatusGroup_MCAN, 8), /*!< Rx FIFO 0 message lost. */ - kStatus_MCAN_RxFifo1New = MAKE_STATUS(kStatusGroup_MCAN, 9), /*!< New message written to Rx FIFO 1. */ - kStatus_MCAN_RxFifo1Idle = MAKE_STATUS(kStatusGroup_MCAN, 10), /*!< Rx FIFO 1 is Idle. */ - kStatus_MCAN_RxFifo1Watermark = MAKE_STATUS(kStatusGroup_MCAN, 11), /*!< Rx FIFO 1 fill level reached watermark. */ - kStatus_MCAN_RxFifo1Full = MAKE_STATUS(kStatusGroup_MCAN, 12), /*!< Rx FIFO 1 full. */ - kStatus_MCAN_RxFifo1Lost = MAKE_STATUS(kStatusGroup_MCAN, 13), /*!< Rx FIFO 1 message lost. */ - kStatus_MCAN_RxFifo0Busy = MAKE_STATUS(kStatusGroup_MCAN, 14), /*!< Rx FIFO 0 is busy. */ - kStatus_MCAN_RxFifo1Busy = MAKE_STATUS(kStatusGroup_MCAN, 15), /*!< Rx FIFO 1 is busy. */ - kStatus_MCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_MCAN, 16), /*!< MCAN Module Error and Status. */ - kStatus_MCAN_UnHandled = MAKE_STATUS(kStatusGroup_MCAN, 17), /*!< UnHadled Interrupt asserted. */ -}; - -/*! - * @brief MCAN status flags. - * - * This provides constants for the MCAN status flags for use in the MCAN functions. - * Note: The CPU read action clears MCAN_ErrorFlag, therefore user need to - * read MCAN_ErrorFlag and distinguish which error is occur using - * _mcan_error_flags enumerations. - */ -enum _mcan_flags -{ - kMCAN_AccesstoRsvdFlag = CAN_IR_ARA_MASK, /*!< CAN Synchronization Status. */ - kMCAN_ProtocolErrDIntFlag = CAN_IR_PED_MASK, /*!< Tx Warning Interrupt Flag. */ - kMCAN_ProtocolErrAIntFlag = CAN_IR_PEA_MASK, /*!< Rx Warning Interrupt Flag. */ - kMCAN_BusOffIntFlag = CAN_IR_BO_MASK, /*!< Tx Error Warning Status. */ - kMCAN_ErrorWarningIntFlag = CAN_IR_EW_MASK, /*!< Rx Error Warning Status. */ - kMCAN_ErrorPassiveIntFlag = CAN_IR_EP_MASK, /*!< Rx Error Warning Status. */ -}; - -/*! - * @brief MCAN Rx FIFO status flags. - * - * The MCAN Rx FIFO Status enumerations are used to determine the status of the - * Rx FIFO. - */ -enum _mcan_rx_fifo_flags -{ - kMCAN_RxFifo0NewFlag = CAN_IR_RF0N_MASK, /*!< Rx FIFO 0 new message flag. */ - kMCAN_RxFifo0WatermarkFlag = CAN_IR_RF0W_MASK, /*!< Rx FIFO 0 watermark reached flag. */ - kMCAN_RxFifo0FullFlag = CAN_IR_RF0F_MASK, /*!< Rx FIFO 0 full flag. */ - kMCAN_RxFifo0LostFlag = CAN_IR_RF0L_MASK, /*!< Rx FIFO 0 message lost flag. */ - kMCAN_RxFifo1NewFlag = CAN_IR_RF1N_MASK, /*!< Rx FIFO 0 new message flag. */ - kMCAN_RxFifo1WatermarkFlag = CAN_IR_RF1W_MASK, /*!< Rx FIFO 0 watermark reached flag. */ - kMCAN_RxFifo1FullFlag = CAN_IR_RF1F_MASK, /*!< Rx FIFO 0 full flag. */ - kMCAN_RxFifo1LostFlag = CAN_IR_RF1L_MASK, /*!< Rx FIFO 0 message lost flag. */ -}; - -/*! - * @brief MCAN Tx status flags. - * - * The MCAN Tx Status enumerations are used to determine the status of the - * Tx Buffer/Event FIFO. - */ -enum _mcan_tx_flags -{ - kMCAN_TxTransmitCompleteFlag = CAN_IR_TC_MASK, /*!< Transmission completed flag. */ - kMCAN_TxTransmitCancelFinishFlag = CAN_IR_TCF_MASK, /*!< Transmission cancellation finished flag. */ - kMCAN_TxEventFifoLostFlag = CAN_IR_TEFL_MASK, /*!< Tx Event FIFO element lost. */ - kMCAN_TxEventFifoFullFlag = CAN_IR_TEFF_MASK, /*!< Tx Event FIFO full. */ - kMCAN_TxEventFifoWatermarkFlag = CAN_IR_TEFW_MASK, /*!< Tx Event FIFO fill level reached watermark. */ - kMCAN_TxEventFifoNewFlag = CAN_IR_TEFN_MASK, /*!< Tx Handler wrote Tx Event FIFO element flag. */ - kMCAN_TxEventFifoEmptyFlag = CAN_IR_TFE_MASK, /*!< Tx FIFO empty flag. */ -}; - -/*! - * @brief MCAN interrupt configuration structure, default settings all disabled. - * - * This structure contains the settings for all of the MCAN Module interrupt configurations. - */ -enum _mcan_interrupt_enable -{ - kMCAN_BusOffInterruptEnable = CAN_IE_BOE_MASK, /*!< Bus Off interrupt. */ - kMCAN_ErrorInterruptEnable = CAN_IE_EPE_MASK, /*!< Error interrupt. */ - kMCAN_WarningInterruptEnable = CAN_IE_EWE_MASK, /*!< Rx Warning interrupt. */ -}; - -/*! @brief MCAN frame format. */ -typedef enum _mcan_frame_idformat -{ - kMCAN_FrameIDStandard = 0x0U, /*!< Standard frame format attribute. */ - kMCAN_FrameIDExtend = 0x1U, /*!< Extend frame format attribute. */ -} mcan_frame_idformat_t; - -/*! @brief MCAN frame type. */ -typedef enum _mcan_frame_type -{ - kMCAN_FrameTypeData = 0x0U, /*!< Data frame type attribute. */ - kMCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */ -} mcan_frame_type_t; - -/*! @brief MCAN frame datafield size. */ -typedef enum _mcan_bytes_in_datafield -{ - kMCAN_8ByteDatafield = 0x0U, /*!< 8 byte data field. */ - kMCAN_12ByteDatafield = 0x1U, /*!< 12 byte data field. */ - kMCAN_16ByteDatafield = 0x2U, /*!< 16 byte data field. */ - kMCAN_20ByteDatafield = 0x3U, /*!< 20 byte data field. */ - kMCAN_24ByteDatafield = 0x4U, /*!< 24 byte data field. */ - kMCAN_32ByteDatafield = 0x5U, /*!< 32 byte data field. */ - kMCAN_48ByteDatafield = 0x6U, /*!< 48 byte data field. */ - kMCAN_64ByteDatafield = 0x7U, /*!< 64 byte data field. */ -} mcan_bytes_in_datafield_t; - -#if defined(__CC_ARM) -#pragma anon_unions -#endif -/*! @brief MCAN Tx Buffer structure. */ -typedef struct _mcan_tx_buffer_frame -{ - struct - { - uint32_t id : 29; /*!< CAN Frame Identifier. */ - uint32_t rtr : 1; /*!< CAN Frame Type(DATA or REMOTE). */ - uint32_t xtd : 1; /*!< CAN Frame Type(STD or EXT). */ - uint32_t esi : 1; /*!< CAN Frame Error State Indicator. */ - }; - struct - { - uint32_t : 16; - uint32_t dlc : 4; /*!< Data Length Code 9 10 11 12 13 14 15 - Number of data bytes 12 16 20 24 32 48 64 */ - uint32_t brs : 1; /*!< Bit Rate Switch. */ - uint32_t fdf : 1; /*!< CAN FD format. */ - uint32_t : 1; /*!< Reserved. */ - uint32_t efc : 1; /*!< Event FIFO control. */ - uint32_t mm : 8; /*!< Message Marker. */ - }; - uint8_t *data; - uint8_t size; /*!< classical CAN is 8(bytes), FD is 12/64 such. */ -} mcan_tx_buffer_frame_t; - -/*! @brief MCAN Rx FIFO/Buffer structure. */ -typedef struct _mcan_rx_buffer_frame -{ - struct - { - uint32_t id : 29; /*!< CAN Frame Identifier. */ - uint32_t rtr : 1; /*!< CAN Frame Type(DATA or REMOTE). */ - uint32_t xtd : 1; /*!< CAN Frame Type(STD or EXT). */ - uint32_t esi : 1; /*!< CAN Frame Error State Indicator. */ - }; - struct - { - uint32_t rxts : 16; /*!< Rx Timestamp. */ - uint32_t dlc : 4; /*!< Data Length Code 9 10 11 12 13 14 15 - Number of data bytes 12 16 20 24 32 48 64 */ - uint32_t brs : 1; /*!< Bit Rate Switch. */ - uint32_t fdf : 1; /*!< CAN FD format. */ - uint32_t : 2; /*!< Reserved. */ - uint32_t fidx : 7; /*!< Filter Index. */ - uint32_t anmf : 1; /*!< Accepted Non-matching Frame. */ - }; - uint8_t *data; - uint8_t size; /*!< classical CAN is 8(bytes), FD is 12/64 such. */ -} mcan_rx_buffer_frame_t; - -/*! @brief MCAN Rx FIFO block number. */ -typedef enum _mcan_fifo_type -{ - kMCAN_Fifo0 = 0x0U, /*!< CAN Rx FIFO 0. */ - kMCAN_Fifo1 = 0x1U, /*!< CAN Rx FIFO 1. */ -} mcan_fifo_type_t; - -/*! @brief MCAN FIFO Operation Mode. */ -typedef enum _mcan_fifo_opmode_config -{ - kMCAN_FifoBlocking = 0x0U, /*!< FIFO blocking mode. */ - kMCAN_FifoOverwrite = 0x1U, /*!< FIFO overwrite mode. */ -} mcan_fifo_opmode_config_t; - -/*! @brief MCAN Tx FIFO/Queue Mode. */ -typedef enum _mcan_txmode_config -{ - kMCAN_txFifo = 0x0U, /*!< Tx FIFO operation. */ - kMCAN_txQueue = 0x1U, /*!< Tx Queue operation. */ -} mcan_txmode_config_t; - -/*! @brief MCAN remote frames treatment. */ -typedef enum _mcan_remote_frame_config -{ - kMCAN_filterFrame = 0x0U, /*!< Filter remote frames. */ - kMCAN_rejectFrame = 0x1U, /*!< Reject all remote frames. */ -} mcan_remote_frame_config_t; - -/*! @brief MCAN non-masking frames treatment. */ -typedef enum _mcan_nonmasking_frame_config -{ - kMCAN_acceptinFifo0 = 0x0U, /*!< Accept non-masking frames in Rx FIFO 0. */ - kMCAN_acceptinFifo1 = 0x1U, /*!< Accept non-masking frames in Rx FIFO 1. */ - kMCAN_reject0 = 0x2U, /*!< Reject non-masking frames. */ - kMCAN_reject1 = 0x3U, /*!< Reject non-masking frames. */ -} mcan_nonmasking_frame_config_t; - -/*! @brief MCAN Filter Element Configuration. */ -typedef enum _mcan_fec_config -{ - kMCAN_disable = 0x0U, /*!< Disable filter element. */ - kMCAN_storeinFifo0 = 0x1U, /*!< Store in Rx FIFO 0 if filter matches. */ - kMCAN_storeinFifo1 = 0x2U, /*!< Store in Rx FIFO 1 if filter matches. */ - kMCAN_reject = 0x3U, /*!< Reject ID if filter matches. */ - kMCAN_setprio = 0x4U, /*!< Set priority if filter matches. */ - kMCAN_setpriofifo0 = 0x5U, /*!< Set priority and store in FIFO 0 if filter matches. */ - kMCAN_setpriofifo1 = 0x6U, /*!< Set priority and store in FIFO 1 if filter matches. */ - kMCAN_storeinbuffer = 0x7U, /*!< Store into Rx Buffer or as debug message. */ -} mcan_fec_config_t; - -/*! @brief MCAN Rx FIFO configuration. */ -typedef struct _mcan_rx_fifo_config -{ - uint32_t address; /*!< FIFOn start address. */ - uint32_t elementSize; /*!< FIFOn element number. */ - uint32_t watermark; /*!< FIFOn watermark level. */ - mcan_fifo_opmode_config_t opmode; /*!< FIFOn blocking/overwrite mode. */ - mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */ -} mcan_rx_fifo_config_t; - -/*! @brief MCAN Rx Buffer configuration. */ -typedef struct _mcan_rx_buffer_config -{ - uint32_t address; /*!< Rx Buffer start address. */ - mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */ -} mcan_rx_buffer_config_t; - -/*! @brief MCAN Tx Event FIFO configuration. */ -typedef struct _mcan_tx_fifo_config -{ - uint32_t address; /*!< Event fifo start address. */ - uint32_t elementSize; /*!< FIFOn element number. */ - uint32_t watermark; /*!< FIFOn watermark level. */ -} mcan_tx_fifo_config_t; - -/*! @brief MCAN Tx Buffer configuration. */ -typedef struct _mcan_tx_buffer_config -{ - uint32_t address; /*!< Tx Buffers Start Address. */ - uint32_t dedicatedSize; /*!< Number of Dedicated Transmit Buffers. */ - uint32_t fqSize; /*!< Transmit FIFO/Queue Size. */ - mcan_txmode_config_t mode; /*!< Tx FIFO/Queue Mode.*/ - mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */ -} mcan_tx_buffer_config_t; - -/*! @brief MCAN Filter Type. */ -typedef enum _mcan_std_filter_type -{ - kMCAN_range = 0x0U, /*!< Range filter from SFID1 to SFID2. */ - kMCAN_dual = 0x1U, /*!< Dual ID filter for SFID1 or SFID2. */ - kMCAN_classic = 0x2U, /*!< Classic filter: SFID1 = filter, SFID2 = mask. */ - kMCAN_disableORrange2 = 0x3U, /*!< Filter element disabled for standard filter - or Range filter, XIDAM mask not applied for extended filter. */ -} mcan_filter_type_t; - -/*! @brief MCAN Standard Message ID Filter Element. */ -typedef struct _mcan_std_filter_element_config -{ - uint32_t sfid2 : 11; /*!< Standard Filter ID 2. */ - uint32_t : 5; /*!< Reserved. */ - uint32_t sfid1 : 11; /*!< Standard Filter ID 1. */ - uint32_t sfec : 3; /*!< Standard Filter Element Configuration. */ - uint32_t sft : 2; /*!< Standard Filter Type. */ -} mcan_std_filter_element_config_t; - -/*! @brief MCAN Extended Message ID Filter Element. */ -typedef struct _mcan_ext_filter_element_config -{ - uint32_t efid1 : 29; /*!< Extended Filter ID 1. */ - uint32_t efec : 3; /*!< Extended Filter Element Configuration. */ - uint32_t efid2 : 29; /*!< Extended Filter ID 2. */ - uint32_t : 1; /*!< Reserved. */ - uint32_t eft : 2; /*!< Extended Filter Type. */ -} mcan_ext_filter_element_config_t; - -/*! @brief MCAN Rx filter configuration. */ -typedef struct _mcan_frame_filter_config -{ - uint32_t address; /*!< Filter start address. */ - uint32_t listSize; /*!< Filter list size. */ - mcan_frame_idformat_t idFormat; /*!< Frame format. */ - mcan_remote_frame_config_t remFrame; /*!< Remote frame treatment. */ - mcan_nonmasking_frame_config_t nmFrame; /*!< Non-masking frame treatment. */ -} mcan_frame_filter_config_t; - -/*! @brief MCAN protocol timing characteristic configuration structure. */ -typedef struct _mcan_timing_config -{ - uint16_t preDivider; /*!< Nominal Clock Pre-scaler Division Factor. */ - uint8_t rJumpwidth; /*!< Nominal Re-sync Jump Width. */ - uint8_t seg1; /*!< Nominal Time Segment 1. */ - uint8_t seg2; /*!< Nominal Time Segment 2. */ -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) - uint16_t datapreDivider; /*!< Data Clock Pre-scaler Division Factor. */ - uint8_t datarJumpwidth; /*!< Data Re-sync Jump Width. */ - uint8_t dataseg1; /*!< Data Time Segment 1. */ - uint8_t dataseg2; /*!< Data Time Segment 2. */ -#endif -} mcan_timing_config_t; - -/*! @brief MCAN module configuration structure. */ -typedef struct _mcan_config -{ - uint32_t baudRateA; /*!< Baud rate of Arbitration phase in bps. */ - uint32_t baudRateD; /*!< Baud rate of Data phase in bps. */ - bool enableCanfdNormal; /*!< Enable or Disable CANFD normal. */ - bool enableCanfdSwitch; /*!< Enable or Disable CANFD with baudrate switch. */ - bool enableLoopBackInt; /*!< Enable or Disable Internal Back. */ - bool enableLoopBackExt; /*!< Enable or Disable External Loop Back. */ - bool enableBusMon; /*!< Enable or Disable Bus Monitoring Mode. */ - mcan_timing_config_t timingConfig; /*!< Protocol timing . */ -} mcan_config_t; - -/*! @brief MCAN Buffer transfer. */ -typedef struct _mcan_buffer_transfer -{ - mcan_tx_buffer_frame_t *frame; /*!< The buffer of CAN Message to be transfer. */ - uint8_t bufferIdx; /*!< The index of Message buffer used to transfer Message. */ -} mcan_buffer_transfer_t; - -/*! @brief MCAN Rx FIFO transfer. */ -typedef struct _mcan_fifo_transfer -{ - mcan_rx_buffer_frame_t *frame; /*!< The buffer of CAN Message to be received from Rx FIFO. */ -} mcan_fifo_transfer_t; - -/*! @brief MCAN handle structure definition. */ -typedef struct _mcan_handle mcan_handle_t; - -/*! @brief MCAN transfer callback function. - * - * The MCAN transfer callback returns a value from the underlying layer. - * If the status equals to kStatus_MCAN_ErrorStatus, the result parameter is the Content of - * MCAN status register which can be used to get the working status(or error status) of MCAN module. - * If the status equals to other MCAN Message Buffer transfer status, the result is the index of - * Message Buffer that generate transfer event. - * If the status equals to other MCAN Message Buffer transfer status, the result is meaningless and should be - * Ignored. - */ -typedef void (*mcan_transfer_callback_t)( - CAN_Type *base, mcan_handle_t *handle, status_t status, uint32_t result, void *userData); - -/*! @brief MCAN handle structure. */ -struct _mcan_handle -{ - mcan_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< MCAN callback function parameter.*/ - mcan_tx_buffer_frame_t *volatile bufferFrameBuf[64]; /*!< The buffer for received data from Buffers. */ - mcan_rx_buffer_frame_t *volatile rxFifoFrameBuf; /*!< The buffer for received data from Rx FIFO. */ - volatile uint8_t bufferState[64]; /*!< Message Buffer transfer state. */ - volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */ -}; - -/****************************************************************************** - * API - *****************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes an MCAN instance. - * - * This function initializes the MCAN module with user-defined settings. - * This example shows how to set up the mcan_config_t parameters and how - * to call the MCAN_Init function by passing in these parameters. - * @code - * mcan_config_t config; - * config->baudRateA = 500000U; - * config->baudRateD = 1000000U; - * config->enableCanfdNormal = false; - * config->enableCanfdSwitch = false; - * config->enableLoopBackInt = false; - * config->enableLoopBackExt = false; - * config->enableBusMon = false; - * MCAN_Init(CANFD0, &config, 8000000UL); - * @endcode - * - * @param base MCAN peripheral base address. - * @param config Pointer to the user-defined configuration structure. - * @param sourceClock_Hz MCAN Protocol Engine clock source frequency in Hz. - */ -void MCAN_Init(CAN_Type *base, const mcan_config_t *config, uint32_t sourceClock_Hz); - -/*! - * @brief Deinitializes an MCAN instance. - * - * This function deinitializes the MCAN module. - * - * @param base MCAN peripheral base address. - */ -void MCAN_Deinit(CAN_Type *base); - -/*! - * @brief Gets the default configuration structure. - * - * This function initializes the MCAN configuration structure to default values. The default - * values are as follows. - * config->baudRateA = 500000U; - * config->baudRateD = 1000000U; - * config->enableCanfdNormal = false; - * config->enableCanfdSwitch = false; - * config->enableLoopBackInt = false; - * config->enableLoopBackExt = false; - * config->enableBusMon = false; - * - * @param config Pointer to the MCAN configuration structure. - */ -void MCAN_GetDefaultConfig(mcan_config_t *config); - -/*! - * @brief MCAN enters normal mode. - * - * After initialization, INIT bit in CCCR register must be cleared to enter - * normal mode thus synchronizes to the CAN bus and ready for communication. - * - * @param base MCAN peripheral base address. - */ -void MCAN_EnterNormalMode(CAN_Type *base); - -/*! - * @name Configuration. - * @{ - */ - -/*! - * @brief Sets the MCAN Message RAM base address. - * - * This function sets the Message RAM base address. - * - * @param base MCAN peripheral base address. - * @param value Desired Message RAM base. - */ -static inline void MCAN_SetMsgRAMBase(CAN_Type *base, uint32_t value) -{ - assert(((value >= 0x20000000U) && (value <= 0x20027FFFU)) || ((value >= 0x04000000U) && (value <= 0x04007FFFU))); - - base->MRBA = CAN_MRBA_BA(value >> 16U); -} - -/*! - * @brief Gets the MCAN Message RAM base address. - * - * This function gets the Message RAM base address. - * - * @param base MCAN peripheral base address. - * @return Message RAM base address. - */ -static inline uint32_t MCAN_GetMsgRAMBase(CAN_Type *base) -{ - return base->MRBA; -} - -/*! - * @brief Calculates the improved timing values by specific baudrates for classical CAN - * - * @param baudRate The classical CAN speed in bps defined by user - * @param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching - * @param pconfig Pointer to the MCAN timing configuration structure. - * - * @return TRUE if timing configuration found, FALSE if failed to find configuration - */ -bool MCAN_CalculateImprovedTimingValues(uint32_t baudRate, uint32_t sourceClock_Hz, mcan_timing_config_t *pconfig); - -/*! - * @brief Sets the MCAN protocol arbitration phase timing characteristic. - * - * This function gives user settings to CAN bus timing characteristic. - * The function is for an experienced user. For less experienced users, call - * the MCAN_Init() and fill the baud rate field with a desired value. - * This provides the default arbitration phase timing characteristics. - * - * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate - * set in MCAN_Init(). - * - * @param base MCAN peripheral base address. - * @param config Pointer to the timing configuration structure. - */ -void MCAN_SetArbitrationTimingConfig(CAN_Type *base, const mcan_timing_config_t *config); - -/*! - * @brief Set Baud Rate of MCAN classic mode. - * - * This function set the baud rate of MCAN base on MCAN_CalculateImprovedTimingValues() API calculated timing values. - * - * @param base MCAN peripheral base address. - * @param sourceClock_Hz Source Clock in Hz. - * @param baudRate_Bps Baud Rate in Bps. - * @return kStatus_Success - Set CAN baud rate (only has Nominal phase) successfully. - */ -status_t MCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Bps); - -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) -/*! - * @brief Calculates the improved timing values by specific baudrates for CANFD - * - * @param baudRate The CANFD bus control speed in bps defined by user - * @param baudRateFD The CANFD bus data speed in bps defined by user - * @param sourceClock_Hz The Source clock data speed in bps. - * @param pconfig Pointer to the MCAN timing configuration structure. - * - * @return TRUE if timing configuration found, FALSE if failed to find configuration - */ -bool MCAN_FDCalculateImprovedTimingValues(uint32_t baudRate, - uint32_t baudRateFD, - uint32_t sourceClock_Hz, - mcan_timing_config_t *pconfig); - -/*! - * @brief Set Baud Rate of MCAN FD mode. - * - * This function set the baud rate of MCAN FD base on MCAN_FDCalculateImprovedTimingValues API calculated timing values. - * - * @param base MCAN peripheral base address. - * @param sourceClock_Hz Source Clock in Hz. - * @param baudRateN_Bps Nominal Baud Rate in Bps. - * @param baudRateD_Bps Data Baud Rate in Bps. - * @return kStatus_Success - Set CAN FD baud rate (include Nominal and Data phase) successfully. - */ -status_t MCAN_SetBaudRateFD(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateN_Bps, uint32_t baudRateD_Bps); -/*! - * @brief Sets the MCAN protocol data phase timing characteristic. - * - * This function gives user settings to CAN bus timing characteristic. - * The function is for an experienced user. For less experienced users, call - * the MCAN_Init() and fill the baud rate field with a desired value. - * This provides the default data phase timing characteristics. - * - * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate - * set in MCAN_Init(). - * - * @param base MCAN peripheral base address. - * @param config Pointer to the timing configuration structure. - */ -void MCAN_SetDataTimingConfig(CAN_Type *base, const mcan_timing_config_t *config); -#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */ - -/*! - * @brief Configures an MCAN receive fifo 0 buffer. - * - * This function sets start address, element size, watermark, operation mode - * and datafield size of the recieve fifo 0. - * - * @param base MCAN peripheral base address. - * @param config The receive fifo 0 configuration structure. - */ -void MCAN_SetRxFifo0Config(CAN_Type *base, const mcan_rx_fifo_config_t *config); - -/*! - * @brief Configures an MCAN receive fifo 1 buffer. - * - * This function sets start address, element size, watermark, operation mode - * and datafield size of the recieve fifo 1. - * - * @param base MCAN peripheral base address. - * @param config The receive fifo 1 configuration structure. - */ -void MCAN_SetRxFifo1Config(CAN_Type *base, const mcan_rx_fifo_config_t *config); - -/*! - * @brief Configures an MCAN receive buffer. - * - * This function sets start address and datafield size of the recieve buffer. - * - * @param base MCAN peripheral base address. - * @param config The receive buffer configuration structure. - */ -void MCAN_SetRxBufferConfig(CAN_Type *base, const mcan_rx_buffer_config_t *config); - -/*! - * @brief Configures an MCAN transmit event fifo. - * - * This function sets start address, element size, watermark of the transmit event fifo. - * - * @param base MCAN peripheral base address. - * @param config The transmit event fifo configuration structure. - */ -void MCAN_SetTxEventFifoConfig(CAN_Type *base, const mcan_tx_fifo_config_t *config); - -/*! - * @brief Configures an MCAN transmit buffer. - * - * This function sets start address, element size, fifo/queue mode and datafield - * size of the transmit buffer. - * - * @param base MCAN peripheral base address. - * @param config The transmit buffer configuration structure. - */ -void MCAN_SetTxBufferConfig(CAN_Type *base, const mcan_tx_buffer_config_t *config); - -/*! - * @brief Set filter configuration. - * - * This function sets remote and non masking frames in global filter configuration, - * also the start address, list size in standard/extended ID filter configuration. - * - * @param base MCAN peripheral base address. - * @param config The MCAN filter configuration. - */ -void MCAN_SetFilterConfig(CAN_Type *base, const mcan_frame_filter_config_t *config); - -/*! - * @brief Set standard message ID filter element configuration. - * - * @param base MCAN peripheral base address. - * @param config The MCAN filter configuration. - * @param filter The MCAN standard message ID filter element configuration. - * @param idx The standard message ID filter element index. - */ -void MCAN_SetSTDFilterElement(CAN_Type *base, - const mcan_frame_filter_config_t *config, - const mcan_std_filter_element_config_t *filter, - uint8_t idx); - -/*! - * @brief Set extended message ID filter element configuration. - * - * @param base MCAN peripheral base address. - * @param config The MCAN filter configuration. - * @param filter The MCAN extended message ID filter element configuration. - * @param idx The extended message ID filter element index. - */ -void MCAN_SetEXTFilterElement(CAN_Type *base, - const mcan_frame_filter_config_t *config, - const mcan_ext_filter_element_config_t *filter, - uint8_t idx); - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the MCAN module interrupt flags. - * - * This function gets all MCAN interrupt status flags. - * - * @param base MCAN peripheral base address. - * @param mask The ORed MCAN interrupt mask. - * @return MCAN status flags which are ORed. - */ -static inline uint32_t MCAN_GetStatusFlag(CAN_Type *base, uint32_t mask) -{ - return (base->IR & mask); -} - -/*! - * @brief Clears the MCAN module interrupt flags. - * - * This function clears MCAN interrupt status flags. - * - * @param base MCAN peripheral base address. - * @param mask The ORed MCAN interrupt mask. - */ -static inline void MCAN_ClearStatusFlag(CAN_Type *base, uint32_t mask) -{ - /* Write 1 to clear status flag, write 0 has no effect. */ - base->IR = mask; -} - -/*! - * @brief Gets the new data flag of specific Rx Buffer. - * - * This function gets new data flag of specific Rx Buffer. - * - * @param base MCAN peripheral base address. - * @param idx Rx Buffer index. - * @return Rx Buffer new data status flag. - */ -static inline bool MCAN_GetRxBufferStatusFlag(CAN_Type *base, uint8_t idx) -{ - assert(idx <= 63U); - - bool fgRet; - - if (idx <= 31U) - { - fgRet = (0U != (base->NDAT1 & ((uint32_t)1U << idx))); - } - else - { - fgRet = (0U != (base->NDAT2 & ((uint32_t)1U << (idx - 32U)))); - } - - return fgRet; -} - -/*! - * @brief Clears the new data flag of specific Rx Buffer. - * - * This function clears new data flag of specific Rx Buffer. - * - * @param base MCAN peripheral base address. - * @param idx Rx Buffer index. - */ -static inline void MCAN_ClearRxBufferStatusFlag(CAN_Type *base, uint8_t idx) -{ - assert(idx <= 63U); - - if (idx <= 31U) - { - base->NDAT1 = ((uint32_t)1U << idx); - } - else - { - base->NDAT2 = ((uint32_t)1U << (idx - 32U)); - } -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables MCAN interrupts according to the provided interrupt line and mask. - * - * This function enables the MCAN interrupts according to the provided interrupt line and mask. - * The mask is a logical OR of enumeration members. - * - * @param base MCAN peripheral base address. - * @param line Interrupt line number, 0 or 1. - * @param mask The interrupts to enable. - */ -static inline void MCAN_EnableInterrupts(CAN_Type *base, uint32_t line, uint32_t mask) -{ - base->ILE |= ((uint32_t)1U << line); - if (0U == line) - { - base->ILS &= ~mask; - } - else - { - base->ILS |= mask; - } - base->IE |= mask; -} - -/*! - * @brief Enables MCAN Tx Buffer interrupts according to the provided index. - * - * This function enables the MCAN Tx Buffer interrupts. - * - * @param base MCAN peripheral base address. - * @param idx Tx Buffer index. - */ -static inline void MCAN_EnableTransmitBufferInterrupts(CAN_Type *base, uint8_t idx) -{ - base->TXBTIE |= ((uint32_t)1U << idx); -} - -/*! - * @brief Disables MCAN Tx Buffer interrupts according to the provided index. - * - * This function disables the MCAN Tx Buffer interrupts. - * - * @param base MCAN peripheral base address. - * @param idx Tx Buffer index. - */ -static inline void MCAN_DisableTransmitBufferInterrupts(CAN_Type *base, uint8_t idx) -{ - base->TXBTIE &= (~((uint32_t)1U << idx)); -} - -/*! - * @brief Disables MCAN interrupts according to the provided mask. - * - * This function disables the MCAN interrupts according to the provided mask. - * The mask is a logical OR of enumeration members. - * - * @param base MCAN peripheral base address. - * @param mask The interrupts to disable. - */ -static inline void MCAN_DisableInterrupts(CAN_Type *base, uint32_t mask) -{ - base->IE &= ~mask; -} - -/* @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Gets the Tx buffer request pending status. - * - * This function returns Tx Message Buffer transmission request pending status. - * - * @param base MCAN peripheral base address. - * @param idx The MCAN Tx Buffer index. - */ -uint32_t MCAN_IsTransmitRequestPending(CAN_Type *base, uint8_t idx); - -/*! - * @brief Gets the Tx buffer transmission occurred status. - * - * This function returns Tx Message Buffer transmission occurred status. - * - * @param base MCAN peripheral base address. - * @param idx The MCAN Tx Buffer index. - */ -uint32_t MCAN_IsTransmitOccurred(CAN_Type *base, uint8_t idx); - -/*! - * @brief Writes an MCAN Message to the Transmit Buffer. - * - * This function writes a CAN Message to the specified Transmit Message Buffer - * and changes the Message Buffer state to start CAN Message transmit. After - * that the function returns immediately. - * - * @param base MCAN peripheral base address. - * @param idx The MCAN Tx Buffer index. - * @param pTxFrame Pointer to CAN message frame to be sent. - */ -status_t MCAN_WriteTxBuffer(CAN_Type *base, uint8_t idx, const mcan_tx_buffer_frame_t *pTxFrame); - -/*! - * @brief Reads an MCAN Message from Rx Buffer. - * - * This function reads a CAN message from the Rx Buffer in the Message RAM. - * - * @param base MCAN peripheral base address. - * @param idx The MCAN Rx Buffer index. - * @param pRxFrame Pointer to CAN message frame structure for reception. - * @retval kStatus_Success - Read Message from Rx Buffer successfully. - */ -status_t MCAN_ReadRxBuffer(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *pRxFrame); - -/*! - * @brief Reads an MCAN Message from Rx FIFO. - * - * This function reads a CAN message from the Rx FIFO in the Message RAM. - * - * @param base MCAN peripheral base address. - * @param fifoBlock Rx FIFO block 0 or 1. - * @param pRxFrame Pointer to CAN message frame structure for reception. - * @retval kStatus_Success - Read Message from Rx FIFO successfully. - */ -status_t MCAN_ReadRxFifo(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *pRxFrame); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Tx Buffer add request to send message out. - * - * This function add sending request to corresponding Tx Buffer. - * - * @param base MCAN peripheral base address. - * @param idx Tx Buffer index. - */ -static inline void MCAN_TransmitAddRequest(CAN_Type *base, uint8_t idx) -{ - base->TXBAR = ((uint32_t)1U << idx); -} - -/*! - * @brief Tx Buffer cancel sending request. - * - * This function clears Tx buffer request pending bit. - * - * @param base MCAN peripheral base address. - * @param idx Tx Buffer index. - */ -static inline void MCAN_TransmitCancelRequest(CAN_Type *base, uint8_t idx) -{ - base->TXBCR = ((uint32_t)1U << idx); -} - -/*! - * @brief Performs a polling send transaction on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * @param base MCAN peripheral base pointer. - * @param idx The MCAN buffer index. - * @param pTxFrame Pointer to CAN message frame to be sent. - * @retval kStatus_Success - Write Tx Message Buffer Successfully. - * @retval kStatus_Fail - Tx Message Buffer is currently in use. - */ -status_t MCAN_TransferSendBlocking(CAN_Type *base, uint8_t idx, mcan_tx_buffer_frame_t *pTxFrame); - -/*! - * @brief Performs a polling receive transaction on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * @param base MCAN peripheral base pointer. - * @param idx The MCAN buffer index. - * @param pRxFrame Pointer to CAN message frame structure for reception. - * @retval kStatus_Success - Read Rx Message Buffer Successfully. - * @retval kStatus_Fail - No new message. - */ -status_t MCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *pRxFrame); - -/*! - * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * @param base MCAN peripheral base pointer. - * @param fifoBlock Rx FIFO block, 0 or 1. - * @param pRxFrame Pointer to CAN message frame structure for reception. - * @retval kStatus_Success - Read Message from Rx FIFO successfully. - * @retval kStatus_Fail - No new message in Rx FIFO. - */ -status_t MCAN_TransferReceiveFifoBlocking(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *pRxFrame); - -/*! - * @brief Initializes the MCAN handle. - * - * This function initializes the MCAN handle, which can be used for other MCAN - * transactional APIs. Usually, for a specified MCAN instance, - * call this API once to get the initialized handle. - * - * @param base MCAN peripheral base address. - * @param handle MCAN handle pointer. - * @param callback The callback function. - * @param userData The parameter of the callback function. - */ -void MCAN_TransferCreateHandle(CAN_Type *base, - mcan_handle_t *handle, - mcan_transfer_callback_t callback, - void *userData); - -/*! - * @brief Sends a message using IRQ. - * - * This function sends a message using IRQ. This is a non-blocking function, which returns - * right away. When messages have been sent out, the send callback function is called. - * - * @param base MCAN peripheral base address. - * @param handle MCAN handle pointer. - * @param xfer MCAN Buffer transfer structure. See the #mcan_buffer_transfer_t. - * @retval kStatus_Success Start Tx Buffer sending process successfully. - * @retval kStatus_Fail Write Tx Buffer failed. - * @retval kStatus_MCAN_TxBusy Tx Buffer is in use. - */ -status_t MCAN_TransferSendNonBlocking(CAN_Type *base, mcan_handle_t *handle, mcan_buffer_transfer_t *xfer); - -/*! - * @brief Receives a message from Rx FIFO using IRQ. - * - * This function receives a message using IRQ. This is a non-blocking function, which returns - * right away. When all messages have been received, the receive callback function is called. - * - * @param base MCAN peripheral base address. - * @param handle MCAN handle pointer. - * @param fifoBlock Rx FIFO block, 0 or 1. - * @param xfer MCAN Rx FIFO transfer structure. See the @ref mcan_fifo_transfer_t. - * @retval kStatus_Success - Start Rx FIFO receiving process successfully. - * @retval kStatus_MCAN_RxFifo0Busy - Rx FIFO 0 is currently in use. - * @retval kStatus_MCAN_RxFifo1Busy - Rx FIFO 1 is currently in use. - */ -status_t MCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, - uint8_t fifoBlock, - mcan_handle_t *handle, - mcan_fifo_transfer_t *xfer); - -/*! - * @brief Aborts the interrupt driven message send process. - * - * This function aborts the interrupt driven message send process. - * - * @param base MCAN peripheral base address. - * @param handle MCAN handle pointer. - * @param bufferIdx The MCAN Buffer index. - */ -void MCAN_TransferAbortSend(CAN_Type *base, mcan_handle_t *handle, uint8_t bufferIdx); - -/*! - * @brief Aborts the interrupt driven message receive from Rx FIFO process. - * - * This function aborts the interrupt driven message receive from Rx FIFO process. - * - * @param base MCAN peripheral base address. - * @param fifoBlock MCAN Fifo block, 0 or 1. - * @param handle MCAN handle pointer. - */ -void MCAN_TransferAbortReceiveFifo(CAN_Type *base, uint8_t fifoBlock, mcan_handle_t *handle); - -/*! - * @brief MCAN IRQ handle function. - * - * This function handles the MCAN Error, the Buffer, and the Rx FIFO IRQ request. - * - * @param base MCAN peripheral base address. - * @param handle MCAN handle pointer. - */ -void MCAN_TransferHandleIRQ(CAN_Type *base, mcan_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_MCAN_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_mrt.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_mrt.c deleted file mode 100644 index 69697a21b5c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_mrt.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_mrt.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.mrt" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base Multi-Rate timer peripheral base address - * - * @return The MRT instance - */ -static uint32_t MRT_GetInstance(MRT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to MRT bases for each instance. */ -static MRT_Type *const s_mrtBases[] = MRT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to MRT clocks for each instance. */ -static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(MRT_RSTS_N) -/*! @brief Pointers to MRT resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_mrtResets[] = MRT_RSTS_N; -#elif defined(MRT_RSTS) -/*! @brief Pointers to MRT resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_mrtResets[] = MRT_RSTS; -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t MRT_GetInstance(MRT_Type *base) -{ - uint32_t instance; - uint32_t mrtArrayCount = (sizeof(s_mrtBases) / sizeof(s_mrtBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < mrtArrayCount; instance++) - { - if (s_mrtBases[instance] == base) - { - break; - } - } - - assert(instance < mrtArrayCount); - - return instance; -} - -/*! - * brief Ungates the MRT clock and configures the peripheral for basic operation. - * - * note This API should be called at the beginning of the application using the MRT driver. - * - * param base Multi-Rate timer peripheral base address - * param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in - * MODCFG reigster, param config is useless. - */ -void MRT_Init(MRT_Type *base, const mrt_config_t *config) -{ - assert(config != NULL); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate the MRT clock */ - CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(MRT_RSTS_N) || defined(MRT_RSTS) - /* Reset the module. */ - RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]); -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) - /* Set timer operating mode */ - base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask); -#endif -} - -/*! - * brief Gate the MRT clock - * - * param base Multi-Rate timer peripheral base address - */ -void MRT_Deinit(MRT_Type *base) -{ - /* Stop all the timers */ - MRT_StopTimer(base, kMRT_Channel_0); - MRT_StopTimer(base, kMRT_Channel_1); -#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 2U) - MRT_StopTimer(base, kMRT_Channel_2); -#endif -#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 3U) - MRT_StopTimer(base, kMRT_Channel_3); -#endif - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the MRT clock*/ - CLOCK_DisableClock(s_mrtClocks[MRT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Used to update the timer period in units of count. - * - * The new value will be immediately loaded or will be loaded at the end of the current time - * interval. For one-shot interrupt mode the new value will be immediately loaded. - * - * note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * param base Multi-Rate timer peripheral base address - * param channel Timer channel number - * param count Timer period in units of ticks - * param immediateLoad true: Load the new value immediately into the TIMER register; - * false: Load the new value at the end of current timer interval - */ -void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - - uint32_t newValue = count; - if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == (uint8_t)kMRT_OneShotMode) || (immediateLoad)) - { - /* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */ - newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK; - } - - /* Update the timer interval value */ - base->CHANNEL[channel].INTVAL = newValue; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_mrt.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_mrt.h deleted file mode 100644 index 7829d984e20..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_mrt.h +++ /dev/null @@ -1,366 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_MRT_H_ -#define _FSL_MRT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup mrt - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3 */ -/*@}*/ - -/*! @brief List of MRT channels */ -typedef enum _mrt_chnl -{ - kMRT_Channel_0 = 0U, /*!< MRT channel number 0*/ - kMRT_Channel_1, /*!< MRT channel number 1 */ - kMRT_Channel_2, /*!< MRT channel number 2 */ - kMRT_Channel_3 /*!< MRT channel number 3 */ -} mrt_chnl_t; - -/*! @brief List of MRT timer modes */ -typedef enum _mrt_timer_mode -{ - kMRT_RepeatMode = (0 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< Repeat Interrupt mode */ - kMRT_OneShotMode = (1 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< One-shot Interrupt mode */ - kMRT_OneShotStallMode = (2 << MRT_CHANNEL_CTRL_MODE_SHIFT) /*!< One-shot stall mode */ -} mrt_timer_mode_t; - -/*! @brief List of MRT interrupts */ -typedef enum _mrt_interrupt_enable -{ - kMRT_TimerInterruptEnable = MRT_CHANNEL_CTRL_INTEN_MASK /*!< Timer interrupt enable*/ -} mrt_interrupt_enable_t; - -/*! @brief List of MRT status flags */ -typedef enum _mrt_status_flags -{ - kMRT_TimerInterruptFlag = MRT_CHANNEL_STAT_INTFLAG_MASK, /*!< Timer interrupt flag */ - kMRT_TimerRunFlag = MRT_CHANNEL_STAT_RUN_MASK, /*!< Indicates state of the timer */ -} mrt_status_flags_t; - -/*! - * @brief MRT configuration structure - * - * This structure holds the configuration settings for the MRT peripheral. To initialize this - * structure to reasonable defaults, call the MRT_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _mrt_config -{ - bool enableMultiTask; /*!< true: Timers run in multi-task mode; false: Timers run in hardware status mode */ -} mrt_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the MRT clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the MRT driver. - * - * @param base Multi-Rate timer peripheral base address - * @param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in - * MODCFG reigster, param config is useless. - */ -void MRT_Init(MRT_Type *base, const mrt_config_t *config); - -/*! - * @brief Gate the MRT clock - * - * @param base Multi-Rate timer peripheral base address - */ -void MRT_Deinit(MRT_Type *base); - -/*! - * @brief Fill in the MRT config struct with the default settings - * - * The default values are: - * @code - * config->enableMultiTask = false; - * @endcode - * @param config Pointer to user's MRT config structure. - */ -static inline void MRT_GetDefaultConfig(mrt_config_t *config) -{ - assert(config != NULL); -#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) - /* Use hardware status operating mode */ - config->enableMultiTask = false; -#endif -} - -/*! - * @brief Sets up an MRT channel mode. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Channel that is being configured. - * @param mode Timer mode to use for the channel. - */ -static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - - uint32_t reg = base->CHANNEL[channel].CTRL; - - /* Clear old value */ - reg &= ~MRT_CHANNEL_CTRL_MODE_MASK; - /* Add the new mode */ - reg |= (uint32_t)mode; - - base->CHANNEL[channel].CTRL = reg; -} - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the MRT interrupt. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].CTRL |= mask; -} - -/*! - * @brief Disables the selected MRT interrupt. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to disable. This is a logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].CTRL &= ~mask; -} - -/*! - * @brief Gets the enabled MRT interrupts. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the MRT status flags - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::mrt_status_flags_t - */ -static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK)); -} - -/*! - * @brief Clears the MRT status flags. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::mrt_status_flags_t - */ -static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK); -} - -/*! @}*/ - -/*! - * @name Read and Write the timer period - * @{ - */ - -/*! - * @brief Used to update the timer period in units of count. - * - * The new value will be immediately loaded or will be loaded at the end of the current time - * interval. For one-shot interrupt mode the new value will be immediately loaded. - * - * @note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param count Timer period in units of ticks - * @param immediateLoad true: Load the new value immediately into the TIMER register; - * false: Load the new value at the end of current timer interval - */ -void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad); - -/*! - * @brief Reads the current timer counting value. - * - * This function returns the real-time timer counting value, in a range from 0 to a - * timer period. - * - * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return Current timer counting value in ticks - */ -static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - return base->CHANNEL[channel].TIMER; -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the timer counting. - * - * After calling this function, timers load period value, counts down to 0 and - * depending on the timer mode it will either load the respective start value again or stop. - * - * @note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - * @param count Timer period in units of ticks. Count can contain the LOAD bit, which control the force load feature. - */ -static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - assert((uint32_t)(count & ~MRT_CHANNEL_INTVAL_LOAD_MASK) <= (uint32_t)MRT_CHANNEL_INTVAL_IVALUE_MASK); - /* Write the timer interval value */ - base->CHANNEL[channel].INTVAL = count; -} - -/*! - * @brief Stops the timer counting. - * - * This function stops the timer from counting. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - */ -static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - /* Stop the timer immediately */ - base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK; -} - -/*! @}*/ - -/*! - * @name Get & release channel - * @{ - */ - -/*! - * @brief Find the available channel. - * - * This function returns the lowest available channel number. - * - * @param base Multi-Rate timer peripheral base address - */ -static inline uint32_t MRT_GetIdleChannel(MRT_Type *base) -{ - return base->IDLE_CH; -} - -#if !(defined(FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) && FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) -/*! - * @brief Release the channel when the timer is using the multi-task mode. - * - * In multi-task mode, the INUSE flags allow more control over when MRT channels are released for - * further use. The user can hold on to a channel acquired by calling MRT_GetIdleChannel() for as - * long as it is needed and release it by calling this function. This removes the need to ask for - * an available channel for every use. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - */ -static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - - uint32_t reg = base->CHANNEL[channel].STAT; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg = ~MRT_CHANNEL_STAT_INTFLAG_MASK; - reg |= MRT_CHANNEL_STAT_INUSE_MASK; - - base->CHANNEL[channel].STAT = reg; -} -#endif - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_MRT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_ostimer.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_ostimer.c deleted file mode 100644 index c3acfb0e48f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_ostimer.c +++ /dev/null @@ -1,381 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_ostimer.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.ostimer" -#endif - -/* Typedef for interrupt handler. */ -typedef void (*ostimer_isr_t)(OSTIMER_Type *base, ostimer_callback_t cb); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base OSTIMER peripheral base address - * - * @return The OSTIMER instance - */ -static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base); - -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) -/* @brief Translate the value from gray-code to decimal by the Code Gray in SYSCTL. - * - * @param gray The gray value input. - * - * @return the decimal value. - */ -static uint64_t OSTIMER_GrayToDecimalbyCodeGray(uint64_t gray); -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of OSTIMER handle. */ -static ostimer_callback_t s_ostimerHandle[FSL_FEATURE_SOC_OSTIMER_COUNT]; -/* Array of OSTIMER peripheral base address. */ -static OSTIMER_Type *const s_ostimerBases[] = OSTIMER_BASE_PTRS; -/* Array of OSTIMER IRQ number. */ -static const IRQn_Type s_ostimerIRQ[] = OSTIMER_IRQS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of OSTIMER clock name. */ -static const clock_ip_name_t s_ostimerClock[] = OSTIMER_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/* OSTIMER ISR for transactional APIs. */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -static ostimer_isr_t s_ostimerIsr = (ostimer_isr_t)DefaultISR; -#else -static ostimer_isr_t s_ostimerIsr; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* @brief Function for getting the instance number of OS timer. */ -static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_ostimerBases); instance++) - { - if (s_ostimerBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_ostimerBases)); - - return instance; -} - -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) -/* @brief Translate the value from gray-code to decimal by the Code Gray in SYSCTL. - * - * @param gray The gray value input. - * - * @return the decimal value. - */ -static uint64_t OSTIMER_GrayToDecimalbyCodeGray(uint64_t gray) -{ - uint64_t decOut; - - SYSCTL->CODE_GRAY_LSB = (uint32_t)(gray & 0xFFFFFFFFU); - SYSCTL->CODE_GRAY_MSB = (uint32_t)((gray >> 32U) & 0x3FFU); // limit to 42bits as OSevent timer - __NOP(); - decOut = ((uint64_t)(SYSCTL->CODE_BIN_MSB) & 0x3FFU) << 32U; - decOut |= (uint64_t)(SYSCTL->CODE_BIN_LSB); - - return decOut; -} -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ - -/* @brief Translate the value from gray-code to decimal. */ -/* - * @param gray The gray value input. - * - * @return the decimal value. - */ -uint64_t OSTIMER_GrayToDecimal(uint64_t gray) -{ -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) - return OSTIMER_GrayToDecimalbyCodeGray(gray); -#else - uint64_t temp = gray; - while (temp != 0U) - { - temp >>= 1U; - gray ^= temp; - } - - return gray; -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ -} - -/* @brief Enable the OSTIMER interrupt. - * - * After calling this function, the OSTIMER driver will enable/disable the IRQ and module interrupt enablement. - * - * @param base OSTIMER peripheral base address. - * @param enable enable/disable the IRQ and module interrupt enablement. - * - true: Disable the IRQ and module interrupt enablement. - * - false: Disable the IRQ and module interrupt enablement. - * @return none - */ -static void OSTIMER_EnableInterrupt(OSTIMER_Type *base, bool enable) -{ - assert(NULL != base); - - if (enable) - { - /* Enable the IRQ and module interrupt enablement. */ - (void)EnableIRQ(s_ostimerIRQ[OSTIMER_GetInstance(base)]); - base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; - } - else - { - /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ - (void)DisableIRQ(s_ostimerIRQ[OSTIMER_GetInstance(base)]); - base->OSEVENT_CTRL &= ~OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; /* Clear interrupt flag by writing 1. */ - } -} - -/*! - * @brief Initializes an OSTIMER by turning it's clock on. - * - */ -void OSTIMER_Init(OSTIMER_Type *base) -{ - assert(NULL != base); - - uint32_t instance = OSTIMER_GetInstance(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if !(defined(FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) && FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) - /* Enable the OSTIMER 32k clock in PMC module. */ - CLOCK_EnableOstimer32kClock(); -#endif - /* Enable clock for OSTIMER. */ - CLOCK_EnableClock(s_ostimerClock[instance]); -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) - CLOCK_EnableClock(kCLOCK_Sysctl); -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Deinitializes a OSTIMER instance. - * - * This function shuts down OSTIMER clock - * - * @param base OSTIMER peripheral base address. - */ -void OSTIMER_Deinit(OSTIMER_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable clock for OSTIMER. */ - CLOCK_DisableClock(s_ostimerClock[OSTIMER_GetInstance(base)]); -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) - CLOCK_DisableClock(kCLOCK_Sysctl); -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Get OSTIMER status Flags. - * - * This returns the status flag. - * Currently, only match interrupt flag can be got. - * - * @param base OSTIMER peripheral base address. - * @return status register value - */ -uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base) -{ - return base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK; -} - -/*! - * @brief Clear Status Interrupt Flags. - * - * This clears intr status flag. - * Currently, only match interrupt flag can be cleared. - * - * @param base OSTIMER peripheral base address. - * @param mask Clear bit mask. - * @return none - */ -void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask) -{ - base->OSEVENT_CTRL |= mask; -} - -/*! - * @brief Set the match raw value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. - * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is gray-code format) - * - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. - * @retval kStatus_Fail - Set match raw value fail. - */ -status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) -{ -#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK - uint64_t decValueTimer; -#endif - status_t status; - uint64_t tmp = count; - uint32_t instance = OSTIMER_GetInstance(base); - - /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ - OSTIMER_EnableInterrupt(base, false); - - s_ostimerIsr = OSTIMER_HandleIRQ; - s_ostimerHandle[instance] = cb; - - /* Set the match value. */ - base->MATCH_L = (uint32_t)tmp; - base->MATCH_H = (uint32_t)(tmp >> 32U); - -#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK - /* Workaround-2019-12-30: - * Since OSTimer's counter register is Gray-encoded, it would cost more time to write register. When EVTimer Match - * Write Ready bit is low, which means the previous match value has been updated successfully by that time, it is - * safe to reload (write) the Match Registers. Even if there is the RM comment that "In typical applications, it - * should not be necessary to test this bit", but we found the interruption would not be reported when the delta - * timer user added is smaller(IE: RT595 11us in 1MHz typical application) in release version." To prevent such - * issue from happening, we'd better wait for the match value to update successfully before enabling IRQ. - */ - while (0U != (base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)) - { - } - - /* After the WR_RDY bit became low, we need to check whether current time goes ahead of the match value we set. - * (1) If current timer value has gone ahead of the match value, the interrupt will not be reported before 64-bit - * timer value over flow. We need to check whether the interrupt flag has been set or not: if yes, we will enable - * interrupt and return success; if not, we will return fail directly. - * (2) If current timer value has not gone ahead of match value, we will enable interrupt and return success. - */ - decValueTimer = OSTIMER_GetCurrentTimerValue(base); - if ((decValueTimer >= OSTIMER_GrayToDecimal(tmp)) && - (0U == (base->OSEVENT_CTRL & (uint32_t)kOSTIMER_MatchInterruptFlag))) - { - status = kStatus_Fail; - } - else -#endif /* #ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK */ - { - /* Enable the module interrupt enablement. */ - OSTIMER_EnableInterrupt(base, true); - status = kStatus_Success; - } - - return status; -} - -/*! - * @brief Set the match value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code in - * API. ) - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @retval kStatus_Success - Set match value and enable interrupt Successfully. - * @retval kStatus_Fail - Set match value fail. - */ -status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) -{ - uint64_t tmp = OSTIMER_DecimalToGray(count); - - return OSTIMER_SetMatchRawValue(base, tmp, cb); -} - -/*! - * @brief Get current timer count value from OSTIMER. - * - * This function will get a decimal timer count value. - * The RAW value of timer count is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of OSTIMER which will formated to decimal value. - */ -uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = OSTIMER_GetCurrentTimerRawValue(base); - - return OSTIMER_GrayToDecimal(tmp); -} - -/*! - * @brief Get the capture value from OSTIMER. - * - * This function will get a capture decimal-value from OSTIMER. - * The RAW value of timer capture is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of capture register, data format is decimal. - */ -uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = OSTIMER_GetCaptureRawValue(base); - - return OSTIMER_GrayToDecimal(tmp); -} - -void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb) -{ - /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ - OSTIMER_EnableInterrupt(base, false); - - if (cb != NULL) - { - cb(); - } -} - -#if defined(OSTIMER0) -void OS_EVENT_DriverIRQHandler(void); -void OS_EVENT_DriverIRQHandler(void) -{ - s_ostimerIsr(OSTIMER0, s_ostimerHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(OSTIMER) -void OS_EVENT_DriverIRQHandler(void); -void OS_EVENT_DriverIRQHandler(void) -{ - s_ostimerIsr(OSTIMER, s_ostimerHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_ostimer.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_ostimer.h deleted file mode 100644 index c74a7931362..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_ostimer.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_OSTIMER_H_ -#define _FSL_OSTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup ostimer - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief OSTIMER driver version. */ -#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) -/*@}*/ - -/*! - * @brief OSTIMER status flags. - */ -enum _ostimer_flags -{ - kOSTIMER_MatchInterruptFlag = (OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK), /*!< Match interrupt flag bit, sets if - the match value was reached. */ -}; - -/*! @brief ostimer callback function. */ -typedef void (*ostimer_callback_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes an OSTIMER by turning its bus clock on - * - */ -void OSTIMER_Init(OSTIMER_Type *base); - -/*! - * @brief Deinitializes a OSTIMER instance. - * - * This function shuts down OSTIMER bus clock - * - * @param base OSTIMER peripheral base address. - */ -void OSTIMER_Deinit(OSTIMER_Type *base); - -/*! - * @brief Translate the value from gray-code to decimal. - * - * @param gray The gray value input. - * @return The decimal value. - */ -uint64_t OSTIMER_GrayToDecimal(uint64_t gray); - -/*! - * @brief Translate the value from decimal to gray-code. - * - * @param dec The decimal value. - * @return The gray code of the input value. - */ -static inline uint64_t OSTIMER_DecimalToGray(uint64_t dec) -{ - return (dec ^ (dec >> 1U)); -} - -/*! - * @brief Get OSTIMER status Flags. - * - * This returns the status flag. - * Currently, only match interrupt flag can be got. - * - * @param base OSTIMER peripheral base address. - * @return status register value - */ -uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base); - -/*! - * @brief Clear Status Interrupt Flags. - * - * This clears intrrupt status flag. - * Currently, only match interrupt flag can be cleared. - * - * @param base OSTIMER peripheral base address. - * @param mask Clear bit mask. - * @return none - */ -void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask); - -/*! - * @brief Set the match raw value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. - * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is gray-code format) - * - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. - * @retval kStatus_Fail - Set match raw value fail. - */ -status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); - -/*! - * @brief Set the match value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central OS TIMER. - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code - * internally.) - * - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @retval kStatus_Success - Set match value and enable interrupt Successfully. - * @retval kStatus_Fail - Set match value fail. - */ -status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); - -/*! - * @brief Set value to OSTIMER MATCH register directly. - * - * This function writes the input value to OSTIMER MATCH register directly, - * it does not touch any other registers. Note that, the data format is - * gray-code. The function @ref OSTIMER_DecimalToGray could convert decimal - * value to gray code. - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value (Value is gray-code format). - */ -static inline void OSTIMER_SetMatchRegister(OSTIMER_Type *base, uint64_t value) -{ -#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK - /* Wait for MATCH register ready for write. */ - while (0U != (base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)) - { - } -#endif - - base->MATCH_L = (uint32_t)value; - base->MATCH_H = (uint32_t)(value >> 32U); -} - -/*! - * @brief Enable the OSTIMER counter match interrupt. - * - * Enable the timer counter match interrupt. The interrupt happens when OSTIMER - * counter matches the value in MATCH registers. - * - * @param base OSTIMER peripheral base address. - */ -static inline void OSTIMER_EnableMatchInterrupt(OSTIMER_Type *base) -{ - base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; -} - -/*! - * @brief Disable the OSTIMER counter match interrupt. - * - * Disable the timer counter match interrupt. The interrupt happens when OSTIMER - * counter matches the value in MATCH registers. - * - * @param base OSTIMER peripheral base address. - */ -static inline void OSTIMER_DisableMatchInterrupt(OSTIMER_Type *base) -{ - base->OSEVENT_CTRL &= ~OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; -} - -/*! - * @brief Get current timer raw count value from OSTIMER. - * - * This function will get a gray code type timer count value from OS timer register. - * The raw value of timer count is gray code format. - * - * @param base OSTIMER peripheral base address. - * @return Raw value of OSTIMER, gray code format. - */ -static inline uint64_t OSTIMER_GetCurrentTimerRawValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = base->EVTIMERL; - tmp |= (uint64_t)(base->EVTIMERH) << 32U; - - return tmp; -} - -/*! - * @brief Get current timer count value from OSTIMER. - * - * This function will get a decimal timer count value. - * The RAW value of timer count is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of OSTIMER which will be formated to decimal value. - */ -uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base); - -/*! - * @brief Get the capture value from OSTIMER. - * - * This function will get a captured gray-code value from OSTIMER. - * The Raw value of timer capture is gray code format. - * - * @param base OSTIMER peripheral base address. - * @return Raw value of capture register, data format is gray code. - */ -static inline uint64_t OSTIMER_GetCaptureRawValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = base->CAPTURE_L; - tmp |= (uint64_t)(base->CAPTURE_H) << 32U; - - return tmp; -} - -/*! - * @brief Get the capture value from OSTIMER. - * - * This function will get a capture decimal-value from OSTIMER. - * The RAW value of timer capture is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of capture register, data format is decimal. - */ -uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base); - -/*! - * @brief OS timer interrupt Service Handler. - * - * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request - * in OSTIMER_SetMatchValue()). - * if no user callback is scheduled, the interrupt will simply be cleared. - * - * @param base OS timer peripheral base address. - * @param cb callback scheduled for this instance of OS timer - * @return none - */ -void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb); -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_OSTIMER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_pint.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_pint.c deleted file mode 100644 index c5557dd030f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_pint.c +++ /dev/null @@ -1,971 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_pint.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.pint" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -/*! @brief Irq number array */ -static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS + - FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; - -/*! @brief Callback function array for SECPINT(s). */ -static pint_cb_t s_secpintCallback[FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS]; -#else -/*! @brief Irq number array */ -static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - -/*! @brief Callback function array for PINT(s). */ -static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Initialize PINT peripheral. - - * This function initializes the PINT peripheral and enables the clock. - * - * param base Base address of the PINT peripheral. - * - * retval None. - */ -void PINT_Init(PINT_Type *base) -{ - uint32_t i; - uint32_t pmcfg = 0; - uint8_t pintcount = 0; - assert(base != NULL); - - if (base == PINT) - { - pintcount = FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; - /* clear PINT callback array*/ - for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_pintCallback[i] = NULL; - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - pintcount = FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; - /* clear SECPINT callback array*/ - for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_secpintCallback[i] = NULL; - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - - /* Disable all bit slices for pint*/ - for (i = 0; i < pintcount; i++) - { - pmcfg = pmcfg | ((uint32_t)kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U))); - } - -#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_GpioInt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) - - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio_Sec); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - -#else - - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Pint); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } - else - { - /* if need config SECURE PINT device,then enable secure pint interrupt clock */ -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio_Sec_Int); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } -#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ - - /* Disable all pattern match bit slices */ - base->PMCFG = pmcfg; -} - -/*! - * brief Configure PINT peripheral pin interrupt. - - * This function configures a given pin interrupt. - * - * param base Base address of the PINT peripheral. - * param intr Pin interrupt. - * param enable Selects detection logic. - * param callback Callback. - * - * retval None. - */ -void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback) -{ - assert(base != NULL); - - /* Clear Rise and Fall flags first */ - PINT_PinInterruptClrRiseFlag(base, intr); - PINT_PinInterruptClrFallFlag(base, intr); - - /* Security PINT uses additional callback array */ - if (base == PINT) - { - s_pintCallback[intr] = callback; - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - s_secpintCallback[intr] = callback; -#endif - } - - /* select level or edge sensitive */ - base->ISEL = (base->ISEL & ~(1UL << (uint32_t)intr)) | - ((((uint32_t)enable & PINT_PIN_INT_LEVEL) != 0U) ? (1UL << (uint32_t)intr) : 0U); - - /* enable rising or level interrupt */ - if (((unsigned)enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE)) != 0U) - { - base->SIENR = 1UL << (uint32_t)intr; - } - else - { - base->CIENR = 1UL << (uint32_t)intr; - } - - /* Enable falling or select high level */ - if (((unsigned)enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL) != 0U) - { - base->SIENF = 1UL << (uint32_t)intr; - } - else - { - base->CIENF = 1UL << (uint32_t)intr; - } -} - -/*! - * brief Get PINT peripheral pin interrupt configuration. - - * This function returns the configuration of a given pin interrupt. - * - * param base Base address of the PINT peripheral. - * param pintr Pin interrupt. - * param enable Pointer to store the detection logic. - * param callback Callback. - * - * retval None. - */ -void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback) -{ - uint32_t mask; - bool level; - - assert(base != NULL); - - *enable = kPINT_PinIntEnableNone; - level = false; - - mask = 1UL << (uint32_t)pintr; - if ((base->ISEL & mask) != 0U) - { - /* Pin interrupt is level sensitive */ - level = true; - } - - if ((base->IENR & mask) != 0U) - { - if (level) - { - /* Level interrupt is enabled */ - *enable = kPINT_PinIntEnableLowLevel; - } - else - { - /* Rising edge interrupt */ - *enable = kPINT_PinIntEnableRiseEdge; - } - } - - if ((base->IENF & mask) != 0U) - { - if (level) - { - /* Level interrupt is active high */ - *enable = kPINT_PinIntEnableHighLevel; - } - else - { - /* Either falling or both edge */ - if (*enable == kPINT_PinIntEnableRiseEdge) - { - /* Rising and faling edge */ - *enable = kPINT_PinIntEnableBothEdges; - } - else - { - /* Falling edge */ - *enable = kPINT_PinIntEnableFallEdge; - } - } - } - - /* Security PINT uses additional callback array */ - if (base == PINT) - { - *callback = s_pintCallback[pintr]; - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - *callback = s_secpintCallback[pintr]; -#endif - } -} - -/*! - * brief Configure PINT pattern match. - - * This function configures a given pattern match bit slice. - * - * param base Base address of the PINT peripheral. - * param bslice Pattern match bit slice number. - * param cfg Pointer to bit slice configuration. - * - * retval None. - */ -void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) -{ - uint32_t src_shift; - uint32_t cfg_shift; - uint32_t pmcfg; - uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; - uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; - - assert(base != NULL); - - src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); - cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); - - /* Input source selection for selected bit slice */ - base->PMSRC = (base->PMSRC & ~(tmp_src_shift << src_shift)) | ((uint32_t)(cfg->bs_src) << src_shift); - - /* Bit slice configuration */ - pmcfg = base->PMCFG; - pmcfg = (pmcfg & ~(tmp_cfg_shift << cfg_shift)) | ((uint32_t)(cfg->bs_cfg) << cfg_shift); - - /* If end point is true, enable the bits */ - if ((uint32_t)bslice != 7UL) - { - if (cfg->end_point) - { - pmcfg |= (1UL << (uint32_t)bslice); - } - else - { - pmcfg &= ~(1UL << (uint32_t)bslice); - } - } - - base->PMCFG = pmcfg; - - /* Save callback pointer */ - if (base == PINT) - { - if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) - { - s_pintCallback[bslice] = cfg->callback; - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - { - s_secpintCallback[bslice] = cfg->callback; - } -#endif - } -} - -/*! - * brief Get PINT pattern match configuration. - - * This function returns the configuration of a given pattern match bit slice. - * - * param base Base address of the PINT peripheral. - * param bslice Pattern match bit slice number. - * param cfg Pointer to bit slice configuration. - * - * retval None. - */ -void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) -{ - uint32_t src_shift; - uint32_t cfg_shift; - uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; - uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; - - assert(base != NULL); - - src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); - cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); - - cfg->bs_src = (pint_pmatch_input_src_t)(uint32_t)((base->PMSRC & (tmp_src_shift << src_shift)) >> src_shift); - cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)(uint32_t)((base->PMCFG & (tmp_cfg_shift << cfg_shift)) >> cfg_shift); - - if ((uint32_t)bslice == 7U) - { - cfg->end_point = true; - } - else - { - cfg->end_point = (((base->PMCFG & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice) != 0U) ? true : false; - } - - if (base == PINT) - { - if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) - { - cfg->callback = s_pintCallback[bslice]; - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - { - cfg->callback = s_secpintCallback[bslice]; - } -#endif - } -} - -/*! - * brief Reset pattern match detection logic. - - * This function resets the pattern match detection logic if any of the product term is matching. - * - * param base Base address of the PINT peripheral. - * - * retval pmstatus Each bit position indicates the match status of corresponding bit slice. - * = 0 Match was detected. = 1 Match was not detected. - */ -uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base) -{ - uint32_t pmctrl; - uint32_t pmstatus; - uint32_t pmsrc; - - pmctrl = base->PMCTRL; - pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT; - if (pmstatus != 0UL) - { - /* Reset Pattern match engine detection logic */ - pmsrc = base->PMSRC; - base->PMSRC = pmsrc; - } - return (pmstatus); -} - -/*! - * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. - - * This function clears the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr) -{ - uint32_t pinIntMode = base->ISEL & (1UL << (uint32_t)pintr); - uint32_t pinIntStatus = base->IST & (1UL << (uint32_t)pintr); - - /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ - if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) - { - base->IST = (1UL << (uint32_t)pintr); - } -} - -/*! - * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. - - * This function clears the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_PinInterruptClrStatusAll(PINT_Type *base) -{ - uint32_t pinIntMode = 0; - uint32_t pinIntStatus = 0; - uint32_t pinIntCount = 0; - uint32_t mask = 0; - uint32_t i; - - if (base == PINT) - { - pinIntCount = (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - pinIntCount = (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - - for (i = 0; i < pinIntCount; i++) - { - pinIntMode = base->ISEL & (1UL << i); - pinIntStatus = base->IST & (1UL << i); - - /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ - if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) - { - mask |= 1UL << i; - } - } - - base->IST = mask; -} - -/*! - * brief Enable callback. - - * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * param base Base address of the PINT peripheral. - * - * retval None. - */ -void PINT_EnableCallback(PINT_Type *base) -{ - uint32_t i; - - assert(base != NULL); - - if (base == PINT) - { - for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i]); - (void)EnableIRQ(s_pintIRQ[i]); - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - (void)EnableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } -} - -/*! - * brief enable callback by pin index. - - * This function enables callback by pin index instead of enabling all pins. - * - * param base Base address of the peripheral. - * param pinIdx pin index. - * - * retval None. - */ -void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) -{ - assert(base != NULL); - - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); - -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - /* Get the right security pint irq index in array */ - if (base == SECPINT) - { - pintIdx = - (pint_pin_int_t)(uint32_t)((uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS); - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - - NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); - (void)EnableIRQ(s_pintIRQ[pintIdx]); -} - -/*! - * brief Disable callback. - - * This function disables the interrupt for the selected PINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * param base Base address of the peripheral. - * - * retval None. - */ -void PINT_DisableCallback(PINT_Type *base) -{ - uint32_t i; - - assert(base != NULL); - - if (base == PINT) - { - for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - (void)DisableIRQ(s_pintIRQ[i]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i]); - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - (void)DisableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } -} - -/*! - * brief disable callback by pin index. - - * This function disables callback by pin index instead of disabling all pins. - * - * param base Base address of the peripheral. - * param pinIdx pin index. - * - * retval None. - */ -void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) -{ - assert(base != NULL); - - if (base == PINT) - { - (void)DisableIRQ(s_pintIRQ[pintIdx]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); - NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - (void)DisableIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); - NVIC_ClearPendingIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); -#endif - } -} - -/*! - * brief Deinitialize PINT peripheral. - - * This function disables the PINT clock. - * - * param base Base address of the PINT peripheral. - * - * retval None. - */ -void PINT_Deinit(PINT_Type *base) -{ - uint32_t i; - - assert(base != NULL); - - /* Cleanup */ - PINT_DisableCallback(base); - if (base == PINT) - { - /* clear PINT callback array*/ - for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_pintCallback[i] = NULL; - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - /* clear SECPINT callback array */ - for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_secpintCallback[i] = NULL; - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - -#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_GpioInt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) - - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio_Sec); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - -#else - - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Pint); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } - else - { - /* if need config SECURE PINT device,then enable secure pint interrupt clock */ -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio_Sec_Int); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } -#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ -} -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -/* IRQ handler functions overloading weak symbols in the startup */ -void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void); -void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void) -{ - uint32_t pmstatus = 0; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); - /* Call user function */ - if (s_secpintCallback[kPINT_SecPinInt0] != NULL) - { - s_secpintCallback[kPINT_SecPinInt0](kPINT_SecPinInt0, pmstatus); - } - if ((SECPINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt0); - } - SDK_ISR_EXIT_BARRIER; -} - -#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) -/* IRQ handler functions overloading weak symbols in the startup */ -void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void); -void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); - /* Call user function */ - if (s_secpintCallback[kPINT_SecPinInt1] != NULL) - { - s_secpintCallback[kPINT_SecPinInt1](kPINT_SecPinInt1, pmstatus); - } - if ((SECPINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt1); - } - SDK_ISR_EXIT_BARRIER; -} -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - -/* IRQ handler functions overloading weak symbols in the startup */ -void PIN_INT0_DriverIRQHandler(void); -void PIN_INT0_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt0] != NULL) - { - s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus); - } - if ((PINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); - } - SDK_ISR_EXIT_BARRIER; -} - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) -void PIN_INT1_DriverIRQHandler(void); -void PIN_INT1_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt1] != NULL) - { - s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus); - } - if ((PINT->ISEL & 0x2U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) -void PIN_INT2_DriverIRQHandler(void); -void PIN_INT2_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt2] != NULL) - { - s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus); - } - if ((PINT->ISEL & 0x4U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) -void PIN_INT3_DriverIRQHandler(void); -void PIN_INT3_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt3] != NULL) - { - s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus); - } - if ((PINT->ISEL & 0x8U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) -void PIN_INT4_DriverIRQHandler(void); -void PIN_INT4_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt4] != NULL) - { - s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus); - } - if ((PINT->ISEL & 0x10U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT5_DAC1_IRQHandler(void); -void PIN_INT5_DAC1_IRQHandler(void) -#else -void PIN_INT5_DriverIRQHandler(void); -void PIN_INT5_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt5] != NULL) - { - s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus); - } - if ((PINT->ISEL & 0x20U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT6_USART3_IRQHandler(void); -void PIN_INT6_USART3_IRQHandler(void) -#else -void PIN_INT6_DriverIRQHandler(void); -void PIN_INT6_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt6] != NULL) - { - s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus); - } - if ((PINT->ISEL & 0x40U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT7_USART4_IRQHandler(void); -void PIN_INT7_USART4_IRQHandler(void) -#else -void PIN_INT7_DriverIRQHandler(void); -void PIN_INT7_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt7] != NULL) - { - s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus); - } - if ((PINT->ISEL & 0x80U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7); - } - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_pint.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_pint.h deleted file mode 100644 index eb7ed612b92..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_pint.h +++ /dev/null @@ -1,581 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_PINT_H_ -#define _FSL_PINT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup pint_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 1, 9)) /*!< Version 2.1.9 */ -/*@}*/ - -/* Number of interrupt line supported by PINT */ -#define PINT_PIN_INT_COUNT 8U - -/* Number of interrupt line supported by SECURE PINT */ -#define SEC_PINT_PIN_INT_COUNT 2U - -/* Number of input sources supported by PINT */ -#define PINT_INPUT_COUNT 8U - -/* PININT Bit slice source register bits */ -#define PININT_BITSLICE_SRC_START 8U -#define PININT_BITSLICE_SRC_MASK 7U - -/* PININT Bit slice configuration register bits */ -#define PININT_BITSLICE_CFG_START 8U -#define PININT_BITSLICE_CFG_MASK 7U -#define PININT_BITSLICE_ENDP_MASK 7U - -#define PINT_PIN_INT_LEVEL 0x10U -#define PINT_PIN_INT_EDGE 0x00U -#define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U -#define PINT_PIN_INT_RISE 0x01U -#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE) -#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) -#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) -#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL) -#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) - -/*! @brief PINT Pin Interrupt enable type */ -typedef enum _pint_pin_enable -{ - kPINT_PinIntEnableNone = 0U, /*!< Do not generate Pin Interrupt */ - kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE, /*!< Generate Pin Interrupt on rising edge */ - kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE, /*!< Generate Pin Interrupt on falling edge */ - kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */ - kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL, /*!< Generate Pin Interrupt on low level */ - kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */ -} pint_pin_enable_t; - -/*! @brief PINT Pin Interrupt type */ -typedef enum _pint_int -{ - kPINT_PinInt0 = 0U, /*!< Pin Interrupt 0 */ -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_PinInt1 = 1U, /*!< Pin Interrupt 1 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) - kPINT_PinInt2 = 2U, /*!< Pin Interrupt 2 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) - kPINT_PinInt3 = 3U, /*!< Pin Interrupt 3 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) - kPINT_PinInt4 = 4U, /*!< Pin Interrupt 4 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) - kPINT_PinInt5 = 5U, /*!< Pin Interrupt 5 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) - kPINT_PinInt6 = 6U, /*!< Pin Interrupt 6 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) - kPINT_PinInt7 = 7U, /*!< Pin Interrupt 7 */ -#endif -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) - kPINT_SecPinInt0 = 0U, /*!< Secure Pin Interrupt 0 */ -#endif -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_SecPinInt1 = 1U, /*!< Secure Pin Interrupt 1 */ -#endif -} pint_pin_int_t; - -/*! @brief PINT Pattern Match bit slice input source type */ -typedef enum _pint_pmatch_input_src -{ - kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */ - kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */ - kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */ - kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */ - kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */ - kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */ - kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */ - kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */ - kPINT_SecPatternMatchInp0Src = 0U, /*!< Input source 0 */ - kPINT_SecPatternMatchInp1Src = 1U, /*!< Input source 1 */ -} pint_pmatch_input_src_t; - -/*! @brief PINT Pattern Match bit slice type */ -typedef enum _pint_pmatch_bslice -{ - kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) - kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) - kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) - kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) - kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) - kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) - kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */ -#endif -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) - kPINT_SecPatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ -#endif -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_SecPatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ -#endif -} pint_pmatch_bslice_t; - -/*! @brief PINT Pattern Match configuration type */ -typedef enum _pint_pmatch_bslice_cfg -{ - kPINT_PatternMatchAlways = 0U, /*!< Always Contributes to product term match */ - kPINT_PatternMatchStickyRise = 1U, /*!< Sticky Rising edge */ - kPINT_PatternMatchStickyFall = 2U, /*!< Sticky Falling edge */ - kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */ - kPINT_PatternMatchHigh = 4U, /*!< High level */ - kPINT_PatternMatchLow = 5U, /*!< Low level */ - kPINT_PatternMatchNever = 6U, /*!< Never contributes to product term match */ - kPINT_PatternMatchBothEdges = 7U, /*!< Either rising or falling edge */ -} pint_pmatch_bslice_cfg_t; - -/*! @brief PINT Callback function. */ -typedef void (*pint_cb_t)(pint_pin_int_t pintr, uint32_t pmatch_status); - -typedef struct _pint_pmatch_cfg -{ - pint_pmatch_input_src_t bs_src; - pint_pmatch_bslice_cfg_t bs_cfg; - bool end_point; - pint_cb_t callback; -} pint_pmatch_cfg_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize PINT peripheral. - - * This function initializes the PINT peripheral and enables the clock. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_Init(PINT_Type *base); - -/*! - * @brief Configure PINT peripheral pin interrupt. - - * This function configures a given pin interrupt. - * - * @param base Base address of the PINT peripheral. - * @param intr Pin interrupt. - * @param enable Selects detection logic. - * @param callback Callback. - * - * @retval None. - */ -void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback); - -/*! - * @brief Get PINT peripheral pin interrupt configuration. - - * This function returns the configuration of a given pin interrupt. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * @param enable Pointer to store the detection logic. - * @param callback Callback. - * - * @retval None. - */ -void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback); - -/*! - * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. - - * This function clears the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr); - -/*! - * @brief Get Selected pin interrupt status. - - * This function returns the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval status = 0 No pin interrupt request. = 1 Selected Pin interrupt request active. - */ -static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->IST & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. - - * This function clears the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_PinInterruptClrStatusAll(PINT_Type *base); - -/*! - * @brief Get all pin interrupts status. - - * This function returns the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval status Each bit position indicates the status of corresponding pin interrupt. - * = 0 No pin interrupt request. = 1 Pin interrupt request active. - */ -static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base) -{ - return (base->IST); -} - -/*! - * @brief Clear Selected pin interrupt fall flag. - - * This function clears the selected pin interrupt fall flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - base->FALL = (1UL << (uint32_t)pintr); -} - -/*! - * @brief Get selected pin interrupt fall flag. - - * This function returns the selected pin interrupt fall flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval flag = 0 Falling edge has not been detected. = 1 Falling edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->FALL & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupt fall flags. - - * This function clears the fall flag for all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base) -{ - base->FALL = PINT_FALL_FDET_MASK; -} - -/*! - * @brief Get all pin interrupt fall flags. - - * This function returns the fall flag of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval flags Each bit position indicates the falling edge detection of the corresponding pin interrupt. - * 0 Falling edge has not been detected. = 1 Falling edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base) -{ - return (base->FALL); -} - -/*! - * @brief Clear Selected pin interrupt rise flag. - - * This function clears the selected pin interrupt rise flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - base->RISE = (1UL << (uint32_t)pintr); -} - -/*! - * @brief Get selected pin interrupt rise flag. - - * This function returns the selected pin interrupt rise flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval flag = 0 Rising edge has not been detected. = 1 Rising edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->RISE & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupt rise flags. - - * This function clears the rise flag for all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base) -{ - base->RISE = PINT_RISE_RDET_MASK; -} - -/*! - * @brief Get all pin interrupt rise flags. - - * This function returns the rise flag of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval flags Each bit position indicates the rising edge detection of the corresponding pin interrupt. - * 0 Rising edge has not been detected. = 1 Rising edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base) -{ - return (base->RISE); -} - -/*! - * @brief Configure PINT pattern match. - - * This function configures a given pattern match bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * @param cfg Pointer to bit slice configuration. - * - * @retval None. - */ -void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); - -/*! - * @brief Get PINT pattern match configuration. - - * This function returns the configuration of a given pattern match bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * @param cfg Pointer to bit slice configuration. - * - * @retval None. - */ -void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); - -/*! - * @brief Get pattern match bit slice status. - - * This function returns the status of selected bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * - * @retval status = 0 Match has not been detected. = 1 Match has been detected. - */ -static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_bslice_t bslice) -{ - return ((base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT) & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice; -} - -/*! - * @brief Get status of all pattern match bit slices. - - * This function returns the status of all bit slices. - * - * @param base Base address of the PINT peripheral. - * - * @retval status Each bit position indicates the match status of corresponding bit slice. - * = 0 Match has not been detected. = 1 Match has been detected. - */ -static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base) -{ - return base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT; -} - -/*! - * @brief Reset pattern match detection logic. - - * This function resets the pattern match detection logic if any of the product term is matching. - * - * @param base Base address of the PINT peripheral. - * - * @retval pmstatus Each bit position indicates the match status of corresponding bit slice. - * = 0 Match was detected. = 1 Match was not detected. - */ -uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base); - -/*! - * @brief Enable pattern match function. - - * This function enables the pattern match function. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchEnable(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) | PINT_PMCTRL_SEL_PMATCH_MASK; -} - -/*! - * @brief Disable pattern match function. - - * This function disables the pattern match function. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchDisable(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) & ~PINT_PMCTRL_SEL_PMATCH_MASK; -} - -/*! - * @brief Enable RXEV output. - - * This function enables the pattern match RXEV output. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) | PINT_PMCTRL_ENA_RXEV_MASK; -} - -/*! - * @brief Disable RXEV output. - - * This function disables the pattern match RXEV output. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) & ~PINT_PMCTRL_ENA_RXEV_MASK; -} - -/*! - * @brief Enable callback. - - * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_EnableCallback(PINT_Type *base); - -/*! - * @brief Disable callback. - - * This function disables the interrupt for the selected PINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * @param base Base address of the peripheral. - * - * @retval None. - */ -void PINT_DisableCallback(PINT_Type *base); - -/*! - * @brief Deinitialize PINT peripheral. - - * This function disables the PINT clock. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_Deinit(PINT_Type *base); - -/*! - * @brief enable callback by pin index. - - * This function enables callback by pin index instead of enabling all pins. - * - * @param base Base address of the peripheral. - * @param pintIdx pin index. - * - * @retval None. - */ -void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); - -/*! - * @brief disable callback by pin index. - - * This function disables callback by pin index instead of disabling all pins. - * - * @param base Base address of the peripheral. - * @param pintIdx pin index. - * - * @retval None. - */ -void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_PINT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_plu.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_plu.c deleted file mode 100644 index b50f472675e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_plu.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_plu.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.plu" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Gets the instance from the base address - * - * @param base PLU peripheral base address - * - * @return The PLU instance - */ -static uint32_t PLU_GetInstance(PLU_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to PLU bases for each instance. */ -static PLU_Type *const s_pluBases[] = PLU_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to PLU clocks for each instance. */ -static const clock_ip_name_t s_pluClocks[] = PLU_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -/*! @brief Pointers to PLU resets for each instance. */ -static const reset_ip_name_t s_lpuResets[] = PLU_RSTS_N; -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t PLU_GetInstance(PLU_Type *base) -{ - uint32_t instance; - uint32_t pluArrayCount = (sizeof(s_pluBases) / sizeof(s_pluBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < pluArrayCount; instance++) - { - if (s_pluBases[instance] == base) - { - break; - } - } - - assert(instance < pluArrayCount); - - return instance; -} - -/*! - * brief Ungates the PLU clock and reset the module. - * - * note This API should be called at the beginning of the application using the PLU driver. - * - * param base PLU peripheral base address - */ -void PLU_Init(PLU_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the PLU peripheral clock */ - CLOCK_EnableClock(s_pluClocks[PLU_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_lpuResets[PLU_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -} - -/*! - * brief Gate the PLU clock - * - * param base PLU peripheral base address - */ -void PLU_Deinit(PLU_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the module clock */ - CLOCK_DisableClock((s_pluClocks[PLU_GetInstance(base)])); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -#if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG -/*! - * @brief Gets an available pre-defined settings for wakeup/interrupt control. - * - * This function initializes the initial configuration structure with an available settings. The default values are: - * @code - * config->filterMode = kPLU_WAKEINT_FILTER_MODE_BYPASS; - * config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC; - * @endcode - * @param config Pointer to configuration structure. - */ -void PLU_GetDefaultWakeIntConfig(plu_wakeint_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->filterMode = kPLU_WAKEINT_FILTER_MODE_BYPASS; - config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC; -} - -/*! - * @brief Enable PLU outputs wakeup/interrupt request. - * - * This function enables Any of the eight selected PLU outputs to contribute to an asynchronous wake-up or an interrupt - * request. - * - * Note: If a PLU_CLKIN is provided, the raw wake-up/interrupt request will be set on the rising-edge of the PLU_CLKIN - * whenever the raw request signal is high. This registered signal will be glitch-free and just use the default wakeint - * config by PLU_GetDefaultWakeIntConfig(). If not, have to specify the filter mode and clock source to eliminate the - * glitches caused by long and widely disparate delays through the network of LUTs making up the PLU. This way may - * increase power consumption in low-power operating modes and inject delay before the wake-up/interrupt request is - * generated. - * - * @param base PLU peripheral base address. - * @param interruptMask PLU interrupt mask (see @ref _plu_interrupt_mask enumeration). - * @param config Pointer to configuration structure (see @ref plu_wakeint_config_t typedef enumeration) - */ -void PLU_EnableWakeIntRequest(PLU_Type *base, uint32_t interruptMask, const plu_wakeint_config_t *config) -{ - uint32_t tmp32 = 0U; - - tmp32 = PLU_WAKEINT_CTRL_FILTER_MODE(config->filterMode) | PLU_WAKEINT_CTRL_FILTER_CLKSEL(config->clockSource) | - PLU_WAKEINT_CTRL_MASK(interruptMask); - - base->WAKEINT_CTRL = tmp32; -} - -/*! - * @brief Clear the latched interrupt - * - * This function clears the wake-up/interrupt request flag latched by PLU_LatchInterrupt() - * - * Note: It is not necessary for the PLU bus clock to be enabled in order to write-to or read-back this bit. - * - * @param base PLU peripheral base address. - */ -void PLU_ClearLatchedInterrupt(PLU_Type *base) -{ - base->WAKEINT_CTRL |= PLU_WAKEINT_CTRL_INTR_CLEAR_MASK; - /* It will take a delay of up to 1.5 PLU_CLKIN clock cycles before this write-to-clear takes effect. */ - while (PLU_WAKEINT_CTRL_INTR_CLEAR_MASK == (base->WAKEINT_CTRL & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK)) - { - } -} -#endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_plu.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_plu.h deleted file mode 100644 index 0c94d49091d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_plu.h +++ /dev/null @@ -1,374 +0,0 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_PLU_H_ -#define _FSL_PLU_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup plu - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_PLU_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1 */ - /*@}*/ - -/*! @brief Index of LUT */ -typedef enum _plu_lut_index -{ - kPLU_LUT_0 = 0U, /*!< 5-input Look-up Table 0 */ - kPLU_LUT_1 = 1U, /*!< 5-input Look-up Table 1 */ - kPLU_LUT_2 = 2U, /*!< 5-input Look-up Table 2 */ - kPLU_LUT_3 = 3U, /*!< 5-input Look-up Table 3 */ - kPLU_LUT_4 = 4U, /*!< 5-input Look-up Table 4 */ - kPLU_LUT_5 = 5U, /*!< 5-input Look-up Table 5 */ - kPLU_LUT_6 = 6U, /*!< 5-input Look-up Table 6 */ - kPLU_LUT_7 = 7U, /*!< 5-input Look-up Table 7 */ - kPLU_LUT_8 = 8U, /*!< 5-input Look-up Table 8 */ - kPLU_LUT_9 = 9U, /*!< 5-input Look-up Table 9 */ - kPLU_LUT_10 = 10U, /*!< 5-input Look-up Table 10 */ - kPLU_LUT_11 = 11U, /*!< 5-input Look-up Table 11 */ - kPLU_LUT_12 = 12U, /*!< 5-input Look-up Table 12 */ - kPLU_LUT_13 = 13U, /*!< 5-input Look-up Table 13 */ - kPLU_LUT_14 = 14U, /*!< 5-input Look-up Table 14 */ - kPLU_LUT_15 = 15U, /*!< 5-input Look-up Table 15 */ - kPLU_LUT_16 = 16U, /*!< 5-input Look-up Table 16 */ - kPLU_LUT_17 = 17U, /*!< 5-input Look-up Table 17 */ - kPLU_LUT_18 = 18U, /*!< 5-input Look-up Table 18 */ - kPLU_LUT_19 = 19U, /*!< 5-input Look-up Table 19 */ - kPLU_LUT_20 = 20U, /*!< 5-input Look-up Table 20 */ - kPLU_LUT_21 = 21U, /*!< 5-input Look-up Table 21 */ - kPLU_LUT_22 = 22U, /*!< 5-input Look-up Table 22 */ - kPLU_LUT_23 = 23U, /*!< 5-input Look-up Table 23 */ - kPLU_LUT_24 = 24U, /*!< 5-input Look-up Table 24 */ - kPLU_LUT_25 = 25U /*!< 5-input Look-up Table 25 */ -} plu_lut_index_t; - -/*! @brief Inputs of LUT. 5 input present for each LUT. */ -typedef enum _plu_lut_in_index -{ - kPLU_LUT_IN_0 = 0U, /*!< LUT input 0 */ - kPLU_LUT_IN_1 = 1U, /*!< LUT input 1 */ - kPLU_LUT_IN_2 = 2U, /*!< LUT input 2 */ - kPLU_LUT_IN_3 = 3U, /*!< LUT input 3 */ - kPLU_LUT_IN_4 = 4U /*!< LUT input 4 */ -} plu_lut_in_index_t; - -/*! @brief Available sources of LUT input */ -typedef enum _plu_lut_input_source -{ - kPLU_LUT_IN_SRC_PLU_IN_0 = 0U, /*!< Select PLU input 0 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_1 = 1U, /*!< Select PLU input 1 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_2 = 2U, /*!< Select PLU input 2 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_3 = 3U, /*!< Select PLU input 3 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_4 = 4U, /*!< Select PLU input 4 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_5 = 5U, /*!< Select PLU input 5 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_0 = 6U, /*!< Select LUT output 0 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_1 = 7U, /*!< Select LUT output 1 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_2 = 8U, /*!< Select LUT output 2 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_3 = 9U, /*!< Select LUT output 3 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_4 = 10U, /*!< Select LUT output 4 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_5 = 11U, /*!< Select LUT output 5 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_6 = 12U, /*!< Select LUT output 6 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_7 = 13U, /*!< Select LUT output 7 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_8 = 14U, /*!< Select LUT output 8 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_9 = 15U, /*!< Select LUT output 9 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_10 = 16U, /*!< Select LUT output 10 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_11 = 17U, /*!< Select LUT output 11 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_12 = 18U, /*!< Select LUT output 12 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_13 = 19U, /*!< Select LUT output 13 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_14 = 20U, /*!< Select LUT output 14 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_15 = 21U, /*!< Select LUT output 15 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_16 = 22U, /*!< Select LUT output 16 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_17 = 23U, /*!< Select LUT output 17 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_18 = 24U, /*!< Select LUT output 18 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_19 = 25U, /*!< Select LUT output 19 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_20 = 26U, /*!< Select LUT output 20 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_21 = 27U, /*!< Select LUT output 21 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_22 = 28U, /*!< Select LUT output 22 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_23 = 29U, /*!< Select LUT output 23 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_24 = 30U, /*!< Select LUT output 24 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_25 = 31U, /*!< Select LUT output 25 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_FLIPFLOP_0 = 32U, /*!< Select Flip-Flops state 0 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_FLIPFLOP_1 = 33U, /*!< Select Flip-Flops state 1 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_FLIPFLOP_2 = 34U, /*!< Select Flip-Flops state 2 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_FLIPFLOP_3 = 35U /*!< Select Flip-Flops state 3 to be connected to LUTn Input x */ -} plu_lut_input_source_t; - -/*! @brief PLU output multiplexer registers */ -typedef enum _plu_output_index -{ - kPLU_OUTPUT_0 = 0U, /*!< PLU OUTPUT 0 */ - kPLU_OUTPUT_1 = 1U, /*!< PLU OUTPUT 1 */ - kPLU_OUTPUT_2 = 2U, /*!< PLU OUTPUT 2 */ - kPLU_OUTPUT_3 = 3U, /*!< PLU OUTPUT 3 */ - kPLU_OUTPUT_4 = 4U, /*!< PLU OUTPUT 4 */ - kPLU_OUTPUT_5 = 5U, /*!< PLU OUTPUT 5 */ - kPLU_OUTPUT_6 = 6U, /*!< PLU OUTPUT 6 */ - kPLU_OUTPUT_7 = 7U /*!< PLU OUTPUT 7 */ -} plu_output_index_t; - -/*! @brief Available sources of PLU output */ -typedef enum _plu_output_source -{ - kPLU_OUT_SRC_LUT_0 = 0U, /*!< Select LUT0 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_1 = 1U, /*!< Select LUT1 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_2 = 2U, /*!< Select LUT2 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_3 = 3U, /*!< Select LUT3 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_4 = 4U, /*!< Select LUT4 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_5 = 5U, /*!< Select LUT5 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_6 = 6U, /*!< Select LUT6 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_7 = 7U, /*!< Select LUT7 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_8 = 8U, /*!< Select LUT8 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_9 = 9U, /*!< Select LUT9 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_10 = 10U, /*!< Select LUT10 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_11 = 11U, /*!< Select LUT11 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_12 = 12U, /*!< Select LUT12 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_13 = 13U, /*!< Select LUT13 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_14 = 14U, /*!< Select LUT14 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_15 = 15U, /*!< Select LUT15 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_16 = 16U, /*!< Select LUT16 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_17 = 17U, /*!< Select LUT17 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_18 = 18U, /*!< Select LUT18 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_19 = 19U, /*!< Select LUT19 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_20 = 20U, /*!< Select LUT20 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_21 = 21U, /*!< Select LUT21 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_22 = 22U, /*!< Select LUT22 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_23 = 23U, /*!< Select LUT23 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_24 = 24U, /*!< Select LUT24 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_25 = 25U, /*!< Select LUT25 output to be connected to PLU output */ - kPLU_OUT_SRC_FLIPFLOP_0 = 26U, /*!< Select Flip-Flops state(0) to be connected to PLU output */ - kPLU_OUT_SRC_FLIPFLOP_1 = 27U, /*!< Select Flip-Flops state(1) to be connected to PLU output */ - kPLU_OUT_SRC_FLIPFLOP_2 = 28U, /*!< Select Flip-Flops state(2) to be connected to PLU output */ - kPLU_OUT_SRC_FLIPFLOP_3 = 29U /*!< Select Flip-Flops state(3) to be connected to PLU output */ -} plu_output_source_t; - -#if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG - -/*! @brief The enumerator of PLU Interrupt. */ -enum _plu_interrupt_mask -{ - kPLU_OUTPUT_0_INTERRUPT_MASK = 1 << 0, /*!< Select PLU output 0 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_1_INTERRUPT_MASK = 1 << 1, /*!< Select PLU output 1 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_2_INTERRUPT_MASK = 1 << 2, /*!< Select PLU output 2 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_3_INTERRUPT_MASK = 1 << 3, /*!< Select PLU output 3 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_4_INTERRUPT_MASK = 1 << 4, /*!< Select PLU output 4 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_5_INTERRUPT_MASK = 1 << 5, /*!< Select PLU output 5 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_6_INTERRUPT_MASK = 1 << 6, /*!< Select PLU output 6 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_7_INTERRUPT_MASK = 1 << 7 /*!< Select PLU output 7 contribute to interrupt/wake-up generation */ -}; - -/*! @brief Control input of the PLU, add filtering for glitch. */ -typedef enum _plu_wakeint_filter_mode -{ - kPLU_WAKEINT_FILTER_MODE_BYPASS = 0U, /*!< Select Bypass mode */ - kPLU_WAKEINT_FILTER_MODE_1_CLK_PERIOD = 1U, /*!< Filter 1 clock period */ - kPLU_WAKEINT_FILTER_MODE_2_CLK_PERIOD = 2U, /*!< Filter 2 clock period */ - kPLU_WAKEINT_FILTER_MODE_3_CLK_PERIOD = 3U /*!< Filter 3 clock period */ -} plu_wakeint_filter_mode_t; - -/*! @brief Clock source for filter mode. */ -typedef enum _plu_wakeint_filter_clock_source -{ - kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC = 0U, /*!< Select the 1MHz low-power oscillator as the filter clock */ - kPLU_WAKEINT_FILTER_CLK_SRC_12MHZ_FRO = 1U, /*!< Select the 12MHz FRO as the filer clock */ - kPLU_WAKEINT_FILTER_CLK_SRC_ALT = 2U /*!< Select a third clock source */ -} plu_wakeint_filter_clock_source_t; - -/*! @brief Wake configuration. */ -typedef struct _plu_wakeint_config -{ - plu_wakeint_filter_mode_t filterMode; /*!< Filter Mode. */ - plu_wakeint_filter_clock_source_t clockSource; /*!< The clock source for filter mode. */ -} plu_wakeint_config_t; -#endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Enable the PLU clock and reset the module. - * - * @note This API should be called at the beginning of the application using the PLU driver. - * - * @param base PLU peripheral base address - */ -void PLU_Init(PLU_Type *base); - -/*! - * @brief Gate the PLU clock - * - * @param base PLU peripheral base address - */ -void PLU_Deinit(PLU_Type *base); - -/*! @}*/ - -/*! - * @name Set input/output source and Truth Table - * @{ - */ - -/*! - * @brief Set Input source of LUT. - * - * Note: An external clock must be applied to the PLU_CLKIN input when using FFs. - * For each LUT, the slot associated with the output from LUTn itself is tied low. - * - * @param base PLU peripheral base address. - * @param lutIndex LUT index (see @ref plu_lut_index_t typedef enumeration). - * @param lutInIndex LUT input index (see @ref plu_lut_in_index_t typedef enumeration). - * @param inputSrc LUT input source (see @ref plu_lut_input_source_t typedef enumeration). - */ -static inline void PLU_SetLutInputSource(PLU_Type *base, - plu_lut_index_t lutIndex, - plu_lut_in_index_t lutInIndex, - plu_lut_input_source_t inputSrc) -{ - PLU->LUT[lutIndex].INP_MUX[lutInIndex] = (uint32_t)inputSrc; -} - -/*! - * @brief Set Output source of PLU. - * - * Note: An external clock must be applied to the PLU_CLKIN input when using FFs. - * - * @param base PLU peripheral base address. - * @param outputIndex PLU output index (see @ref plu_output_index_t typedef enumeration). - * @param outputSrc PLU output source (see @ref plu_output_source_t typedef enumeration). - */ -static inline void PLU_SetOutputSource(PLU_Type *base, plu_output_index_t outputIndex, plu_output_source_t outputSrc) -{ - base->OUTPUT_MUX[outputIndex] = (uint32_t)outputSrc; -} - -/*! - * @brief Set Truth Table of LUT. - * - * @param base PLU peripheral base address. - * @param lutIndex LUT index (see @ref plu_lut_index_t typedef enumeration). - * @param truthTable Truth Table value. - */ -static inline void PLU_SetLutTruthTable(PLU_Type *base, plu_lut_index_t lutIndex, uint32_t truthTable) -{ - base->LUT_TRUTH[lutIndex] = truthTable; -} - -/*! @}*/ - -/*! - * @name Read current Output State - * @{ - */ - -/*! - * @brief Read the current state of the 8 designated PLU Outputs. - * - * Note: The PLU bus clock must be re-enabled prior to reading the Outpus Register if PLU bus clock is - * shut-off. - * - * @param base PLU peripheral base address. - * @return Current PLU output state value. - */ -static inline uint32_t PLU_ReadOutputState(PLU_Type *base) -{ - return (base->OUTPUTS & PLU_OUTPUTS_OUTPUT_STATE_MASK); -} - -/*! @}*/ - -#if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG -/*! - * @name Wake-up/Interrupt Control - * @{ - */ - -/*! - * @brief Gets an available pre-defined settings for wakeup/interrupt control. - * - * This function initializes the initial configuration structure with an available settings. The default values are: - * @code - * config->filterMode = kPLU_WAKEINT_FILTER_MODE_BYPASS; - * config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC; - * @endcode - * @param config Pointer to configuration structure. - */ -void PLU_GetDefaultWakeIntConfig(plu_wakeint_config_t *config); - -/*! - * @brief Enable PLU outputs wakeup/interrupt request. - * - * This function enables Any of the eight selected PLU outputs to contribute to an asynchronous wake-up or an interrupt - * request. - * - * Note: If a PLU_CLKIN is provided, the raw wake-up/interrupt request will be set on the rising-edge of the PLU_CLKIN - * whenever the raw request signal is high. This registered signal will be glitch-free and just use the default wakeint - * config by PLU_GetDefaultWakeIntConfig(). If not, have to specify the filter mode and clock source to eliminate the - * glitches caused by long and widely disparate delays through the network of LUTs making up the PLU. This way may - * increase power consumption in low-power operating modes and inject delay before the wake-up/interrupt request is - * generated. - * - * @param base PLU peripheral base address. - * @param interruptMask PLU interrupt mask (see @ref _plu_interrupt_mask enumeration). - * @param config Pointer to configuration structure (see @ref plu_wakeint_config_t typedef enumeration) - */ -void PLU_EnableWakeIntRequest(PLU_Type *base, uint32_t interruptMask, const plu_wakeint_config_t *config); - -/*! - * @brief Latch an interrupt - * - * This function latches the interrupt and then it can be cleared with PLU_ClearLatchedInterrupt(). - * - * Note: This mode is not compatible with use of the glitch filter. If this bit is set, the FILTER MODE should be set - * to kPLU_WAKEINT_FILTER_MODE_BYPASS (Bypass Mode) and PLU_CLKIN should be provided. If this bit is set, the - * wake-up/interrupt request will be set on the rising-edge of PLU_CLKIN whenever the raw wake-up/interrupt signal is - * high. The request must be cleared by software. - * - * @param base PLU peripheral base address. - */ -static inline void PLU_LatchInterrupt(PLU_Type *base) -{ - base->WAKEINT_CTRL |= PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK; -} - -/*! - * @brief Clear the latched interrupt - * - * This function clears the wake-up/interrupt request flag latched by PLU_LatchInterrupt() - * - * Note: It is not necessary for the PLU bus clock to be enabled in order to write-to or read-back this bit. - * - * @param base PLU peripheral base address. - */ -void PLU_ClearLatchedInterrupt(PLU_Type *base); - -/*! @}*/ -#endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_PLU_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_power.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_power.c deleted file mode 100644 index 86a13dd8dbd..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_power.c +++ /dev/null @@ -1,1949 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_common.h" -#include "fsl_power.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.power" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/** @brief Low Power main structure */ -typedef enum -{ - VD_AON = 0x0, /*!< Digital Always On power domain */ - VD_MEM = 0x1, /*!< Memories (SRAM) power domain */ - VD_DCDC = 0x2, /*!< Core logic power domain */ - VD_DEEPSLEEP = 0x3 /*!< Core logic power domain */ -} LPC_POWER_DOMAIN_T; - -/** - * @brief LDO_FLASH_NV & LDO_USB voltage settings - */ -typedef enum _v_flashnv -{ - V_LDOFLASHNV_1P650 = 0, /*!< 0.95 V */ - V_LDOFLASHNV_1P700 = 1, /*!< 0.975 V */ - V_LDOFLASHNV_1P750 = 2, /*!< 1 V */ - V_LDOFLASHNV_0P800 = 3, /*!< 1.025 V */ - V_LDOFLASHNV_1P850 = 4, /*!< 1.050 V */ - V_LDOFLASHNV_1P900 = 5, /*!< 1.075 V */ - V_LDOFLASHNV_1P950 = 6, /*!< 1.1 V */ - V_LDOFLASHNV_2P000 = 7 /*!< 1.125 V */ -} v_flashnv_t; - -/** @brief Low Power main structure */ -typedef struct -{ /* */ - __IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */ - __IO uint32_t PDCTRL0; /*!< Power Down control : controls power of various modules - in the different Low power modes, including ROM */ - __IO uint32_t SRAMRETCTRL; /*!< Power Down control : controls power SRAM instances - in the different Low power modes */ - __IO uint32_t CPURETCTRL; /*!< CPU0 retention control : controls CPU retention parameters in POWER DOWN modes */ - __IO uint64_t VOLTAGE; /*!< Voltage control in Low Power Modes */ - __IO uint64_t WAKEUPSRC; /*!< Wake up sources control for sleepcon */ - __IO uint64_t WAKEUPINT; /*!< Wake up sources control for ARM */ - __IO uint32_t HWWAKE; /*!< Interrupt that can postpone power down modes - in case an interrupt is pending when the processor request deepsleep */ - __IO uint32_t WAKEUPIOSRC; /*!< Wake up I/O sources in DEEP POWER DOWN mode */ - __IO uint32_t TIMERCFG; /*!< Wake up timers configuration */ - __IO uint32_t TIMERCOUNT; /*!< Wake up Timer count*/ - __IO uint32_t POWERCYCLE; /*!< Cancels entry in Low Power mode if set with 0xDEADABBA (might be used by some - interrupt handlers)*/ -} LPC_LOWPOWER_T; - -/* */ -#define LOWPOWER_POWERCYCLE_CANCELLED 0xDEADABBAUL /*!< */ - -/** - * @brief SRAM Low Power Modes - */ -#define LOWPOWER_SRAM_LPMODE_MASK (0xFUL) -#define LOWPOWER_SRAM_LPMODE_ACTIVE (0x6UL) /*!< SRAM functional mode */ -#define LOWPOWER_SRAM_LPMODE_SLEEP (0xFUL) /*!< SRAM Sleep mode (Data retention, fast wake up) */ -#define LOWPOWER_SRAM_LPMODE_DEEPSLEEP (0x8UL) /*!< SRAM Deep Sleep mode (Data retention, slow wake up) */ -#define LOWPOWER_SRAM_LPMODE_SHUTDOWN (0x9UL) /*!< SRAM Shut Down mode (no data retention) */ -#define LOWPOWER_SRAM_LPMODE_POWERUP (0xAUL) /*!< SRAM is powering up */ - -/** - * @brief Wake up timers configuration in Low Power Modes - */ -#define LOWPOWER_TIMERCFG_CTRL_INDEX 0 -#define LOWPOWER_TIMERCFG_CTRL_MASK (0x1UL << LOWPOWER_TIMERCFG_CTRL_INDEX) -#define LOWPOWER_TIMERCFG_TIMER_INDEX 1 -#define LOWPOWER_TIMERCFG_TIMER_MASK (0x7UL << LOWPOWER_TIMERCFG_TIMER_INDEX) -#define LOWPOWER_TIMERCFG_OSC32K_INDEX 4 -#define LOWPOWER_TIMERCFG_OSC32K_MASK (0x1UL << LOWPOWER_TIMERCFG_OSC32K_INDEX) - -#define LOWPOWER_TIMERCFG_CTRL_DISABLE 0 /*!< Wake Timer Disable */ -#define LOWPOWER_TIMERCFG_CTRL_ENABLE 1 /*!< Wake Timer Enable */ - -/** - * @brief Primary Wake up timers configuration in Low Power Modes - */ -#define LOWPOWER_TIMERCFG_TIMER_RTC1KHZ 0 /*!< 1 KHz Real Time Counter (RTC) used as wake up source */ -#define LOWPOWER_TIMERCFG_TIMER_RTC1HZ 1 /*!< 1 Hz Real Time Counter (RTC) used as wake up source */ -#define LOWPOWER_TIMERCFG_TIMER_OSTIMER 2 /*!< OS Event Timer used as wake up source */ - -#define LOWPOWER_TIMERCFG_OSC32K_FRO32KHZ 0 /*!< Wake up Timers uses FRO 32 KHz as clock source */ -#define LOWPOWER_TIMERCFG_OSC32K_XTAL32KHZ 1 /*!< Wake up Timers uses Chrystal 32 KHz as clock source */ - -//! @brief Interface for lowpower functions -typedef struct LowpowerDriverInterface -{ - void (*power_cycle_cpu_and_flash)(void); - void (*set_lowpower_mode)(LPC_LOWPOWER_T *p_lowpower_cfg); -} lowpower_driver_interface_t; - -/**< DCDC Power Profiles */ -typedef enum -{ - DCDC_POWER_PROFILE_LOW, /**< LOW (for CPU frequencies below DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ) */ - DCDC_POWER_PROFILE_MEDIUM, /**< MEDIUM (for CPU frequencies between DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ and - DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ) */ - DCDC_POWER_PROFILE_HIGH, /**< HIGH (for CPU frequencies between DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ and - DCDC_POWER_PROFILE_HIGH_MAX_FREQ_HZ) */ -} lowpower_dcdc_power_profile_enum; - -/**< Manufacturing Process Corners */ -typedef enum -{ - PROCESS_CORNER_SSS, /**< Slow Corner Process */ - PROCESS_CORNER_NNN, /**< Nominal Corner Process */ - PROCESS_CORNER_FFF, /**< Fast Corner Process */ - PROCESS_CORNER_OTHERS, /**< SFN, SNF, NFS, Poly Res ... Corner Process */ -} lowpower_process_corner_enum; - -/** - * @brief DCDC voltage settings - */ -typedef enum _v_dcdc -{ - V_DCDC_0P950 = 0, /*!< 0.95 V */ - V_DCDC_0P975 = 1, /*!< 0.975 V */ - V_DCDC_1P000 = 2, /*!< 1 V */ - V_DCDC_1P025 = 3, /*!< 1.025 V */ - V_DCDC_1P050 = 4, /*!< 1.050 V */ - V_DCDC_1P075 = 5, /*!< 1.075 V */ - V_DCDC_1P100 = 6, /*!< 1.1 V */ - V_DCDC_1P125 = 7, /*!< 1.125 V */ - V_DCDC_1P150 = 8, /*!< 1.150 V */ - V_DCDC_1P175 = 9, /*!< 1.175 V */ - V_DCDC_1P200 = 10 /*!< 1.2 V */ -} v_dcdc_t; - -/** - * @brief Deep Sleep LDO voltage settings - */ -typedef enum _v_deepsleep -{ - V_DEEPSLEEP_0P900 = 0, /*!< 0.9 V */ - V_DEEPSLEEP_0P925 = 1, /*!< 0.925 V */ - V_DEEPSLEEP_0P950 = 2, /*!< 0.95 V */ - V_DEEPSLEEP_0P975 = 3, /*!< 0.975 V */ - V_DEEPSLEEP_1P000 = 4, /*!< 1.000 V */ - V_DEEPSLEEP_1P025 = 5, /*!< 1.025 V */ - V_DEEPSLEEP_1P050 = 6, /*!< 1.050 V */ - V_DEEPSLEEP_1P075 = 7 /*!< 1.075 V */ -} v_deepsleep_t; - -/** - * @brief Always On and Memories LDO voltage settings - */ -typedef enum _v_ao -{ - V_AO_0P700 = 1, /*!< 0.7 V */ - V_AO_0P725 = 2, /*!< 0.725 V */ - V_AO_0P750 = 3, /*!< 0.75 V */ - V_AO_0P775 = 4, /*!< 0.775 V */ - V_AO_0P800 = 5, /*!< 0.8 V */ - V_AO_0P825 = 6, /*!< 0.825 V */ - V_AO_0P850 = 7, /*!< 0.85 V */ - V_AO_0P875 = 8, /*!< 0.875 V */ - V_AO_0P900 = 9, /*!< 0.9 V */ - V_AO_0P960 = 10, /*!< 0.96 V */ - V_AO_0P970 = 11, /*!< 0.97 V */ - V_AO_0P980 = 12, /*!< 0.98 V */ - V_AO_0P990 = 13, /*!< 0.99 V */ - V_AO_1P000 = 14, /*!< 1 V */ - V_AO_1P010 = 15, /*!< 1.01 V */ - V_AO_1P020 = 16, /*!< 1.02 V */ - V_AO_1P030 = 17, /*!< 1.03 V */ - V_AO_1P040 = 18, /*!< 1.04 V */ - V_AO_1P050 = 19, /*!< 1.05 V */ - V_AO_1P060 = 20, /*!< 1.06 V */ - V_AO_1P070 = 21, /*!< 1.07 V */ - V_AO_1P080 = 22, /*!< 1.08 V */ - V_AO_1P090 = 23, /*!< 1.09 V */ - V_AO_1P100 = 24, /*!< 1.1 V */ - V_AO_1P110 = 25, /*!< 1.11 V */ - V_AO_1P120 = 26, /*!< 1.12 V */ - V_AO_1P130 = 27, /*!< 1.13 V */ - V_AO_1P140 = 28, /*!< 1.14 V */ - V_AO_1P150 = 29, /*!< 1.15 V */ - V_AO_1P160 = 30, /*!< 1.16 V */ - V_AO_1P220 = 31 /*!< 1.22 V */ -} v_ao_t; - -/* Low Power modes */ -#define LOWPOWER_CFG_LPMODE_INDEX 0 -#define LOWPOWER_CFG_LPMODE_MASK (0x3UL << LOWPOWER_CFG_LPMODE_INDEX) -#define LOWPOWER_CFG_SELCLOCK_INDEX 2 -#define LOWPOWER_CFG_SELCLOCK_MASK (0x1UL << LOWPOWER_CFG_SELCLOCK_INDEX) -#define LOWPOWER_CFG_SELMEMSUPPLY_INDEX 3 -#define LOWPOWER_CFG_SELMEMSUPPLY_MASK (0x1UL << LOWPOWER_CFG_SELMEMSUPPLY_INDEX) -#define LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX 4 -#define LOWPOWER_CFG_MEMLOWPOWERMODE_MASK (0x1UL << LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX) -#define LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX 5 -#define LOWPOWER_CFG_LDODEEPSLEEPREF_MASK (0x1UL << LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX) - -#define LOWPOWER_CFG_LPMODE_ACTIVE 0 /*!< ACTIVE mode */ -#define LOWPOWER_CFG_LPMODE_DEEPSLEEP 1 /*!< DEEP SLEEP mode */ -#define LOWPOWER_CFG_LPMODE_POWERDOWN 2 /*!< POWER DOWN mode */ -#define LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN 3 /*!< DEEP POWER DOWN mode */ -#define LOWPOWER_CFG_LPMODE_SLEEP 4 /*!< SLEEP mode */ - -#define LOWPOWER_CFG_SELCLOCK_1MHZ 0 /*!< The 1 MHz clock is used during the configuration of the PMC */ -#define LOWPOWER_CFG_SELCLOCK_12MHZ \ - 1 /*!< The 12 MHz clock is used during the configuration of the PMC (to speed up PMC configuration process)*/ - -#define LOWPOWER_CFG_SELMEMSUPPLY_LDOMEM 0 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_MEM */ -#define LOWPOWER_CFG_SELMEMSUPPLY_LDODEEPSLEEP \ - 1 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_DEEP_SLEEP (or DCDC) */ - -#define LOWPOWER_CFG_MEMLOWPOWERMODE_SOURCEBIASING \ - 0 /*!< All SRAM instances use "Source Biasing" as low power mode technic (it is recommended to set LDO_MEM as high \ - as possible -- 1.1V typical -- during low power mode) */ -#define LOWPOWER_CFG_MEMLOWPOWERMODE_VOLTAGESCALING \ - 1 /*!< All SRAM instances use "Voltage Scaling" as low power mode technic (it is recommended to set LDO_MEM as low \ - as possible -- down to 0.7V -- during low power mode) */ - -/* CPU Retention Control*/ -#define LOWPOWER_CPURETCTRL_ENA_INDEX 0 -#define LOWPOWER_CPURETCTRL_ENA_MASK (0x1UL << LOWPOWER_CPURETCTRL_ENA_INDEX) -#define LOWPOWER_CPURETCTRL_MEMBASE_INDEX 1 -#define LOWPOWER_CPURETCTRL_MEMBASE_MASK (0x1FFFUL << LOWPOWER_CPURETCTRL_MEMBASE_INDEX) -#define LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX 14 -#define LOWPOWER_CPURETCTRL_RETDATALENGTH_MASK (0x3FFUL << LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX) - -/* Voltgae setting*/ -#define DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ \ - (72000000U) /* Maximum System Frequency allowed with DCDC Power Profile LOW */ -#define DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ \ - (100000000U) /* Maximum System Frequency allowed with DCDC Power Profile MEDIUM */ -#define DCDC_POWER_PROFILE_HIGH_MAX_FREQ_HZ \ - (150000000U) /* Maximum System Frequency allowed with DCDC Power Profile HIGH */ -#define PROCESS_NNN_AVG_HZ (19300000U) /* Average Ring OScillator value for Nominal (NNN) Manufacturing Process */ -#define PROCESS_NNN_STD_HZ \ - (400000U) /* Standard Deviation Ring OScillator value for Nominal (NNN) Manufacturing Process */ -#define PROCESS_NNN_LIMITS \ - (6U) /* Nominal (NNN) Manufacturing Process Ring Oscillator values limit (with respect to the Average value) */ -#define PROCESS_NNN_MIN_HZ \ - (PROCESS_NNN_AVG_HZ - \ - (PROCESS_NNN_LIMITS * \ - PROCESS_NNN_STD_HZ)) /* Minimum Ring OScillator value for Nominal (NNN) Manufacturing Process */ -#define PROCESS_NNN_MAX_HZ \ - (PROCESS_NNN_AVG_HZ + \ - (PROCESS_NNN_LIMITS * \ - PROCESS_NNN_STD_HZ)) /* Maximum Ring OScillator value for Nominal (NNN) Manufacturing Process */ -#define VOLTAGE_SSS_LOW_MV (1100U) /* Voltage Settings for : Process=SSS, DCDC Power Profile=LOW */ -#define VOLTAGE_SSS_MED_MV (1150U) /* Voltage Settings for : Process=SSS, DCDC Power Profile=MEDIUM */ -#define VOLTAGE_SSS_HIG_MV (1200U) /* Voltage Settings for : Process=SSS, DCDC Power Profile=HIGH */ -#define VOLTAGE_NNN_LOW_MV (1050U) /* Voltage Settings for : Process=NNN, DCDC Power Profile=LOW */ -#define VOLTAGE_NNN_MED_MV (1075U) /* Voltage Settings for : Process=NNN, DCDC Power Profile=MEDIUM */ -#define VOLTAGE_NNN_HIG_MV (1150U) /* Voltage Settings for : Process=NNN, DCDC Power Profile=HIGH */ -#define VOLTAGE_FFF_LOW_MV (1000U) /* Voltage Settings for : Process=FFF, DCDC Power Profile=LOW */ -#define VOLTAGE_FFF_MED_MV (1025U) /* Voltage Settings for : Process=FFF, DCDC Power Profile=MEDIUM */ -#define VOLTAGE_FFF_HIG_MV (1050U) /* Voltage Settings for : Process=FFF, DCDC Power Profile=HIGH */ - -/** - * @brief LDO Voltage control in Low Power Modes - */ -#define LOWPOWER_VOLTAGE_LDO_PMU_INDEX 0 -#define LOWPOWER_VOLTAGE_LDO_PMU_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) -#define LOWPOWER_VOLTAGE_LDO_MEM_INDEX 5 -#define LOWPOWER_VOLTAGE_LDO_MEM_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) -#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX 10 -#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_MASK (0x7ULL << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX) -#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX 19 -#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) -#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX 24 -#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) -#define LOWPOWER_VOLTAGE_DCDC_INDEX 29 -#define LOWPOWER_VOLTAGE_DCDC_MASK (0xFULL << LOWPOWER_VOLTAGE_DCDC_INDEX) - -/*! @brief set and clear bit MACRO's. */ -#define U32_SET_BITS(P, B) ((*(uint32_t *)P) |= (B)) -#define U32_CLR_BITS(P, B) ((*(uint32_t *)P) &= ~(B)) -/* Return values from Config (N-2) page of flash */ -#define GET_16MXO_TRIM() (*(uint32_t *)(FLASH_NMPA_BASE + 0xC8U)) // (0x3FCC8) -#define GET_32KXO_TRIM() (*(uint32_t *)(FLASH_NMPA_BASE + 0xCCU)) // (0x3FCCC) - -#define CPU_RETENTION_RAMX_STORAGE_START_ADDR (0x04002000) - -#define XO_SLAVE_EN (1) -/******************************************************************************* - * Codes - ******************************************************************************/ - -/******************************************************************************* - * LOCAL FUNCTIONS PROTOTYPES - ******************************************************************************/ -static uint32_t lf_set_ldo_ao_ldo_mem_voltage(uint32_t p_lp_mode, uint32_t p_dcdc_voltage); -static uint32_t lf_wakeup_io_ctrl(uint32_t p_wakeup_io_ctrl); -static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity); - -static void lowpower_set_dcdc_power_profile(lowpower_dcdc_power_profile_enum dcdc_power_profile); -static lowpower_process_corner_enum lowpower_get_part_process_corner(void); -static void lowpower_set_voltage_for_process(lowpower_dcdc_power_profile_enum dcdc_power_profile); -static lowpower_driver_interface_t *s_lowpowerDriver = (lowpower_driver_interface_t *)(0x130050e4); - -/** - * @brief Configures and enters in low power mode - * @param p_lowpower_cfg: pointer to a structure that contains all low power mode parameters - * @return Nothing - * - * !!! IMPORTANT NOTES : - * 1 - CPU Interrupt Enable registers are updated with p_lowpower_cfg->WAKEUPINT. They are NOT restored by the - * API. - * 2 - The Non Maskable Interrupt (NMI) should be disable before calling this API (otherwise, there is a risk - * of Dead Lock). - * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip - * reset) - */ -static void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg); - -/** - * @brief - * @param - * @return - */ -static void lf_set_dcdc_power_profile_low(void) -{ -#define DCDC_POWER_PROFILE_LOW_0_ADDRS (FLASH_NMPA_BASE + 0xE0U) -#define DCDC_POWER_PROFILE_LOW_1_ADDRS (FLASH_NMPA_BASE + 0xE4U) - - uint32_t dcdcTrimValue0 = (*((volatile unsigned int *)(DCDC_POWER_PROFILE_LOW_0_ADDRS))); - uint32_t dcdcTrimValue1 = (*((volatile unsigned int *)(DCDC_POWER_PROFILE_LOW_1_ADDRS))); - - if (0UL != (dcdcTrimValue0 & 0x1UL)) - { - PMC->DCDC0 = dcdcTrimValue0 >> 1; - PMC->DCDC1 = dcdcTrimValue1; - } -} - -/** - * @brief Configures and enters in low power mode - * @param : p_lowpower_cfg - * @return Nothing - */ -static void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg) -{ - /* PMC clk set to 12 MHZ */ - p_lowpower_cfg->CFG |= (uint32_t)LOWPOWER_CFG_SELCLOCK_12MHZ << LOWPOWER_CFG_SELCLOCK_INDEX; - - /* Enable Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP - * POWER DOWN) and Hardware Pin reset */ - PMC->REFFASTWKUP = (PMC->REFFASTWKUP & (~PMC_REFFASTWKUP_LPWKUP_MASK) & (~PMC_REFFASTWKUP_HWWKUP_MASK)) | - PMC_REFFASTWKUP_LPWKUP(1) | PMC_REFFASTWKUP_HWWKUP(1); - - /* SRAM uses Voltage Scaling in all Low Power modes */ - PMC->SRAMCTRL = (PMC->SRAMCTRL & (~PMC_SRAMCTRL_SMB_MASK)) | PMC_SRAMCTRL_SMB(3); - - /* CPU Retention configuration : preserve the value of FUNCRETENTIONCTRL.RET_LENTH which is a Hardware defined - * parameter. */ - p_lowpower_cfg->CPURETCTRL = (SYSCON->FUNCRETENTIONCTRL & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) | - (p_lowpower_cfg->CPURETCTRL & (~SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK)); - - /* Switch System Clock to FRO12Mhz (the configuration before calling this function will not be restored back) */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* Switch main clock to FRO12MHz */ - CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /* Main clock divided by 1 */ - SYSCON->FMCCR = (SYSCON->FMCCR & 0xFFFF0000UL) | 0x201AUL; /* Adjust FMC waiting time cycles */ - lf_set_dcdc_power_profile_low(); /* Align DCDC Power profile with the 12 MHz clock (DCDC Power Profile LOW) */ - - (*(s_lowpowerDriver->set_lowpower_mode))(p_lowpower_cfg); - - /* Restore the configuration of the MISCCTRL Register : LDOMEMBLEEDDSLP = 0, LDOMEMHIGHZMODE = - * 0 */ - PMC->MISCCTRL &= (~PMC_MISCCTRL_DISABLE_BLEED_MASK) & (~PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK); -} - -/** - * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event - * @param None - * @return Nothing - */ -void POWER_CycleCpuAndFlash(void) -{ - (*(s_lowpowerDriver->power_cycle_cpu_and_flash))(); -}; - -/** - * brief PMC Deep Sleep function call - * return nothing - */ -void POWER_EnterDeepSleep(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t hardware_wake_ctrl) -{ - LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ - uint32_t cpu0_nmi_enable; - uint32_t cpu0_int_enable_0; - uint32_t cpu0_int_enable_1; - uint32_t dcdc_voltage; - uint32_t pmc_reset_ctrl; - /* Clear Low Power Mode configuration variable */ - (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); - - /* Configure Low Power Mode configuration variable */ - lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPSLEEP - << LOWPOWER_CFG_LPMODE_INDEX; /* DEEPSLEEP mode */ - - /* DCDC will be always used during Deep Sleep (instead of LDO Deep Sleep); Make sure LDO MEM & Analog references - * will stay powered, Shut down ROM */ - lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd & ~(uint32_t)kPDRUNCFG_PD_DCDC & ~(uint32_t)kPDRUNCFG_PD_LDOMEM & - ~(uint32_t)kPDRUNCFG_PD_BIAS) | - (uint32_t)kPDRUNCFG_PD_LDODEEPSLEEP | (uint32_t)kPDRUNCFG_PD_ROM; - - /* Voltage control in DeepSleep Low Power Modes */ - /* The Memories Voltage settings below are for voltage scaling */ - dcdc_voltage = (uint32_t)V_DCDC_0P950; - lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_POWERDOWN, dcdc_voltage); - - /* SRAM retention control during POWERDOWN */ - lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; - - /* CPU Wake up & Interrupt sources control */ - lv_low_power_mode_cfg.WAKEUPINT = wakeup_interrupts; - lv_low_power_mode_cfg.WAKEUPSRC = wakeup_interrupts; - - /* Interrupts that allow DMA transfers with Flexcomm without waking up the Processor */ - if (0UL != (hardware_wake_ctrl & (LOWPOWER_HWWAKE_PERIPHERALS | LOWPOWER_HWWAKE_SDMA0 | LOWPOWER_HWWAKE_SDMA1))) - { - lv_low_power_mode_cfg.HWWAKE = (hardware_wake_ctrl & ~LOWPOWER_HWWAKE_FORCED) | LOWPOWER_HWWAKE_ENABLE_FRO192M; - } - - cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ - SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ - - /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power - * API */ - cpu0_int_enable_0 = NVIC->ISER[0]; - cpu0_int_enable_1 = NVIC->ISER[1]; - - pmc_reset_ctrl = PMC->RESETCTRL; - - if ((pmc_reset_ctrl & (PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK | PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK)) == - ((0x1UL << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT) | - (0x1UL << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT))) - { - /* BoD CORE reset is activated, so make sure BoD Core and Biasing won't be shutdown */ - lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_BODCORE & ~(uint32_t)kPDRUNCFG_PD_BIAS; - } - if ((pmc_reset_ctrl & (PMC_RESETCTRL_BODVBATRESETENA_SECURE_MASK | PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_MASK)) == - ((0x1UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_SHIFT) | - (0x1UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_SHIFT))) - { - /* BoD VBAT reset is activated, so make sure BoD VBAT and Biasing won't be shutdown */ - lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_BODVBAT & ~(uint32_t)kPDRUNCFG_PD_BIAS; - } - - /* Enter low power mode */ - POWER_EnterLowPower(&lv_low_power_mode_cfg); - - /* Restore the configuration of the NMI Register */ - SYSCON->NMISRC |= cpu0_nmi_enable; - - /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the - * low power API */ - NVIC->ISER[0] = cpu0_int_enable_0; - NVIC->ISER[1] = cpu0_int_enable_1; -} - -/** - * brief PMC power Down function call - * return nothing - */ -void POWER_EnterPowerDown(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t cpu_retention_ctrl) -{ - LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ - uint32_t cpu0_nmi_enable; - uint32_t cpu0_int_enable_0; - uint32_t cpu0_int_enable_1; - uint64_t wakeup_src_int; - uint32_t pmc_reset_ctrl; - uint32_t rng_entropy_save[6]; - - uint32_t analog_ctrl_regs[12]; /* To store Analog Controller Regristers */ - - /* Clear Low Power Mode configuration variable */ - (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); - - /* Configure Low Power Mode configuration variable */ - lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_POWERDOWN - << LOWPOWER_CFG_LPMODE_INDEX; /* POWER DOWN mode */ - - /* Only FRO32K, XTAL32K, COMP, BIAS and LDO_MEM can be stay powered during POWERDOWN (valid from application point - * of view; Hardware allows BODVBAT, LDODEEPSLEEP and FRO1M to stay powered, that's why they are excluded below) */ - lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd) | (uint32_t)kPDRUNCFG_PD_BODVBAT | (uint32_t)kPDRUNCFG_PD_FRO1M | - (uint32_t)kPDRUNCFG_PD_LDODEEPSLEEP; - - /* @TODO Guillaume: add save/restore entropy during PowerDown */ - /* Entropy for RNG need to saved */ - if ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_RNG) != 0UL) - { - CLOCK_EnableClock(kCLOCK_Rng); - RESET_ClearPeripheralReset(kRNG_RST_SHIFT_RSTn); - for (int i = 0; i < 6; i++) - { - rng_entropy_save[i] = RNG->RANDOM_NUMBER; - } - } - - /* CPU0 retention Ctrl. - * For the time being, we do not allow customer to relocate the CPU retention area in SRAMX, meaning that the - * retention area range is [0x0400_2000 - 0x0400_2600] (beginning of RAMX2) If required by customer, - * cpu_retention_ctrl[13:1] will be used for that to modify the default retention area - */ - lv_low_power_mode_cfg.CPURETCTRL = - (cpu_retention_ctrl & LOWPOWER_CPURETCTRL_ENA_MASK) | - ((((uint32_t)CPU_RETENTION_RAMX_STORAGE_START_ADDR >> 2UL) << LOWPOWER_CPURETCTRL_MEMBASE_INDEX) & - LOWPOWER_CPURETCTRL_MEMBASE_MASK); - if (0UL != (cpu_retention_ctrl & 0x1UL)) - { - /* Add RAMX2 for retention */ - sram_retention_ctrl |= LOWPOWER_SRAMRETCTRL_RETEN_RAMX2; - /* CPU retention is required: store Analog Controller Registers */ - analog_ctrl_regs[0] = ANACTRL->FRO192M_CTRL; - analog_ctrl_regs[1] = ANACTRL->ANALOG_CTRL_CFG; - analog_ctrl_regs[2] = ANACTRL->ADC_CTRL; - analog_ctrl_regs[3] = ANACTRL->XO32M_CTRL; - analog_ctrl_regs[4] = ANACTRL->BOD_DCDC_INT_CTRL; - analog_ctrl_regs[5] = ANACTRL->RINGO0_CTRL; - analog_ctrl_regs[6] = ANACTRL->RINGO1_CTRL; - analog_ctrl_regs[7] = ANACTRL->RINGO2_CTRL; - analog_ctrl_regs[8] = ANACTRL->LDO_XO32M; - analog_ctrl_regs[9] = ANACTRL->AUX_BIAS; - } - - /* SRAM retention control during POWERDOWN */ - lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; - - /* Sanity check: If retention is required for any of SRAM instances, make sure LDO MEM will stay powered */ - if ((sram_retention_ctrl & 0x7FFFUL) != 0UL) - { - lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_LDOMEM; - } - - /* Voltage control in Low Power Modes */ - /* The Memories Voltage settings below are for voltage scaling */ - lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_POWERDOWN, 0); - - /* CPU Wake up & Interrupt sources control : only WAKEUP_GPIO_GLOBALINT0, WAKEUP_GPIO_GLOBALINT1, WAKEUP_FLEXCOMM3, - * WAKEUP_ACMP_CAPT, WAKEUP_RTC_LITE_ALARM_WAKEUP, WAKEUP_OS_EVENT_TIMER, WAKEUP_ALLWAKEUPIOS */ - wakeup_src_int = (uint64_t)(WAKEUP_GPIO_GLOBALINT0 | WAKEUP_GPIO_GLOBALINT1 | WAKEUP_FLEXCOMM3 | WAKEUP_ACMP | - WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER | WAKEUP_ALLWAKEUPIOS); - lv_low_power_mode_cfg.WAKEUPINT = wakeup_interrupts & wakeup_src_int; - lv_low_power_mode_cfg.WAKEUPSRC = wakeup_interrupts & wakeup_src_int; - - cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ - SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ - - /* Save the configuration of the CPU interrupt enable Registers */ - cpu0_int_enable_0 = NVIC->ISER[0]; - cpu0_int_enable_1 = NVIC->ISER[1]; - - /* Disable BoD VBAT and BoD Core resets */ - /* BOD VBAT disable reset */ - pmc_reset_ctrl = - PMC->RESETCTRL & (~(PMC_RESETCTRL_BODVBATRESETENA_SECURE_MASK | PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_MASK)); - pmc_reset_ctrl |= (0x2UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_SHIFT) | - (0x2UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_SHIFT); - - /* BOD CORE disable reset */ - pmc_reset_ctrl &= (~(PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK | PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK)); - pmc_reset_ctrl |= (0x2UL << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT) | - (0x2UL << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT); - - PMC->RESETCTRL = pmc_reset_ctrl; - - /* Enter low power mode */ - POWER_EnterLowPower(&lv_low_power_mode_cfg); - - /* Following code is to reset PUF to remove over consumption */ - /* Enable PUF register clock to access register */ - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_PUF_MASK; - /* Release PUF reset */ - SYSCON->PRESETCTRLCLR[2] = SYSCON_PRESETCTRL2_PUF_RST_MASK; - /* Enable PUF SRAM */ - PUF_SRAM_CTRL->CFG |= PUF_SRAM_CTRL_CFG_ENABLE_MASK | PUF_SRAM_CTRL_CFG_CKGATING_MASK; - - /* Disable PUF register clock. */ - // Delaying the line of code below until the PUF State Machine execution is completed: - // Shuting down the clock to early will prevent the state machine from reaching the end. - // => Wait for status bit in PUF Controller Registers before stop PUF clock. - while (0UL == (PUF_SRAM_CTRL->INT_STATUS & PUF_SRAM_CTRL_INT_STATUS_READY_MASK)) - { - } - - SYSCON->AHBCLKCTRLCLR[2] = SYSCON_AHBCLKCTRL2_PUF_MASK; - - /* Restore the configuration of the NMI Register */ - SYSCON->NMISRC |= cpu0_nmi_enable; - - /* Restore PMC RESETCTRL register */ - PMC->RESETCTRL = pmc_reset_ctrl; - - /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the - * low power API */ - NVIC->ISER[0] = cpu0_int_enable_0; - NVIC->ISER[1] = cpu0_int_enable_1; - - if ((cpu_retention_ctrl & 0x1UL) != 0UL) - { - /* Restore Analog Controller Registers */ - ANACTRL->FRO192M_CTRL = analog_ctrl_regs[0] | ANACTRL_FRO192M_CTRL_WRTRIM_MASK; - ANACTRL->ANALOG_CTRL_CFG = analog_ctrl_regs[1]; - ANACTRL->ADC_CTRL = analog_ctrl_regs[2]; - ANACTRL->XO32M_CTRL = analog_ctrl_regs[3]; - ANACTRL->BOD_DCDC_INT_CTRL = analog_ctrl_regs[4]; - ANACTRL->RINGO0_CTRL = analog_ctrl_regs[5]; - ANACTRL->RINGO1_CTRL = analog_ctrl_regs[6]; - ANACTRL->RINGO2_CTRL = analog_ctrl_regs[7]; - ANACTRL->LDO_XO32M = analog_ctrl_regs[8]; - ANACTRL->AUX_BIAS = analog_ctrl_regs[9]; - } - - /* @TODO Guillaume: add save/restore entropy during PowerDown */ - /* Restore Entropy for RNG */ - if ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_RNG) != 0UL) - { - RNG->POWERDOWN &= ~RNG_POWERDOWN_POWERDOWN_MASK; - for (int i = 0; i < 6; i++) - { - RNG->ENTROPY_INJECT = rng_entropy_save[i]; - } - } -} - -/** - * brief PMC Deep Sleep Power Down function call - * return nothing - */ -void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t wakeup_io_ctrl) -{ - LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ - uint32_t cpu0_nmi_enable; - uint32_t cpu0_int_enable_0; - uint32_t cpu0_int_enable_1; - uint32_t pmc_reset_ctrl; - - /* Clear Low Power Mode configuration variable */ - (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); - - /* Configure Low Power Mode configuration variable */ - lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN - << LOWPOWER_CFG_LPMODE_INDEX; /* DEEP POWER DOWN mode */ - - /* Only FRO32K, XTAL32K and LDO_MEM can be stay powered during DEEPPOWERDOWN */ - lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd) | (uint32_t)kPDRUNCFG_PD_BIAS | (uint32_t)kPDRUNCFG_PD_BODVBAT | - (uint32_t)kPDRUNCFG_PD_FRO1M | (uint32_t)kPDRUNCFG_PD_COMP; - - /* SRAM retention control during DEEPPOWERDOWN */ - /* RAM00 used by ROM code to restart. */ - sram_retention_ctrl = sram_retention_ctrl & (~(LOWPOWER_SRAMRETCTRL_RETEN_RAM00)); - - /* SRAM retention control during DEEPPOWERDOWN */ - lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; - - /* Sanity check: If retention is required for any of SRAM instances, make sure LDO MEM will stay powered */ - if ((sram_retention_ctrl & 0x7FFFUL) != 0UL) - { - lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_LDOMEM; - } - - /* Voltage control in Low Power Modes */ - /* The Memories Voltage settings below are for voltage scaling */ - lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN, 0); - - lv_low_power_mode_cfg.WAKEUPINT = - wakeup_interrupts & (WAKEUP_RTC_LITE_ALARM_WAKEUP | - WAKEUP_OS_EVENT_TIMER); /* CPU Wake up sources control : only WAKEUP_RTC_LITE_ALARM_WAKEUP, - WAKEUP_OS_EVENT_TIMER */ - lv_low_power_mode_cfg.WAKEUPSRC = - wakeup_interrupts & - (WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER | - WAKEUP_ALLWAKEUPIOS); /*!< Hardware Wake up sources control: : only WAKEUP_RTC_LITE_ALARM_WAKEUP, - WAKEUP_OS_EVENT_TIMER and WAKEUP_ALLWAKEUPIOS */ - - /* Wake up I/O sources */ - lv_low_power_mode_cfg.WAKEUPIOSRC = lf_wakeup_io_ctrl(wakeup_io_ctrl); - - cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ - SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ - - /* Save the configuration of the CPU interrupt enable Registers */ - cpu0_int_enable_0 = NVIC->ISER[0]; - cpu0_int_enable_1 = NVIC->ISER[1]; - - /* Save the configuration of the PMC RESETCTRL register */ - /* BOD VBAT disable reset */ - pmc_reset_ctrl = - PMC->RESETCTRL & (~(PMC_RESETCTRL_BODVBATRESETENA_SECURE_MASK | PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_MASK)); - pmc_reset_ctrl |= (0x2UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_SHIFT) | - (0x2UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_SHIFT); - - /* BOD CORE disable reset */ - pmc_reset_ctrl &= (~(PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK | PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK)); - pmc_reset_ctrl |= (0x2UL << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT) | - (0x2UL << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT); - - PMC->RESETCTRL = pmc_reset_ctrl; - - /* Enter low power mode */ - POWER_EnterLowPower(&lv_low_power_mode_cfg); - - /* Restore the configuration of the NMI Register */ - SYSCON->NMISRC |= cpu0_nmi_enable; - - /* Restore PMC RESETCTRL register */ - PMC->RESETCTRL = pmc_reset_ctrl; - - /* Restore the configuration of the CPU interrupt enable Registers */ - NVIC->ISER[0] = cpu0_int_enable_0; - NVIC->ISER[1] = cpu0_int_enable_1; -} - -/** - * brief PMC Sleep function call - * return nothing - */ -void POWER_EnterSleep(void) -{ - uint32_t pmsk; - pmsk = __get_PRIMASK(); - __disable_irq(); - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - __WFI(); - __set_PRIMASK(pmsk); -} - -/** - * @brief - * @param - * @return - */ -static uint32_t lf_set_ldo_ao_ldo_mem_voltage(uint32_t p_lp_mode, uint32_t p_dcdc_voltage) -{ -#define FLASH_NMPA_LDO_AO_ADDRS (FLASH_NMPA_BASE + 0x0F4U) -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK (0x100U) -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK (0x3E00U) -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT (9U) -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK (0x10000U) -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK (0x3E0000U) -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT (17U) -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK (0x1000000U) -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK (0x3E000000U) -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT (25U) - - uint32_t ldo_ao_trim, voltage; - uint32_t lv_v_ldo_pmu, lv_v_ldo_pmu_boost; - - ldo_ao_trim = (*((volatile unsigned int *)(FLASH_NMPA_LDO_AO_ADDRS))); - - switch (p_lp_mode) - { - case LOWPOWER_CFG_LPMODE_DEEPSLEEP: - { - if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK) != 0UL) - { - /* Apply settings coming from Flash */ - lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK) >> FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT; - lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ - } - else - { - /* Apply default settings */ - lv_v_ldo_pmu = (uint32_t)V_AO_0P900; - lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P850; - } - } - break; - - case LOWPOWER_CFG_LPMODE_POWERDOWN: - { - if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK) != 0UL) - { - /* Apply settings coming from Flash */ - lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK) >> FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT; - lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ - } - else - { - /* Apply default settings */ - lv_v_ldo_pmu = (uint32_t)V_AO_0P800; - lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P750; - } - } - break; - - case LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN: - { - if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK) != 0UL) - { - /* Apply settings coming from Flash */ - lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK) >> FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT; - lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ - } - else - { - /* Apply default settings */ - lv_v_ldo_pmu = (uint32_t)V_AO_0P800; - lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P750; - } - } - break; - - default: - /* Should never reach this point */ - lv_v_ldo_pmu = (uint32_t)V_AO_1P100; - lv_v_ldo_pmu_boost = (uint32_t)V_AO_1P050; - break; - } - - /* The Memories Voltage settings below are for voltage scaling */ - voltage = - (lv_v_ldo_pmu << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) | /* */ - (lv_v_ldo_pmu_boost << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) | /* */ - ((uint32_t)V_AO_0P750 << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) | /* Set to 0.75V (voltage Scaling) */ - ((uint32_t)V_AO_0P700 << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) | /* Set to 0.7V (voltage Scaling) */ - ((uint32_t)V_DEEPSLEEP_0P900 - << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX) | /* Set to 0.90 V (Not used because LDO_DEEP_SLEEP is disabled)*/ - (p_dcdc_voltage << LOWPOWER_VOLTAGE_DCDC_INDEX) /* */ - ; - - return (voltage); -} - -/** - * @brief - * @param - * @return - */ -static uint32_t lf_wakeup_io_ctrl(uint32_t p_wakeup_io_ctrl) -{ - uint32_t wake_up_type; - uint32_t wakeup_io_ctrl_reg; - uint8_t use_external_pullupdown = 0; - - /* Configure Pull up & Pull down based on the required wake-up edge */ - CLOCK_EnableClock(kCLOCK_Iocon); - - wakeup_io_ctrl_reg = 0UL; - - /* Wake-up I/O 0 */ - wake_up_type = (p_wakeup_io_ctrl & 0x3UL) >> LOWPOWER_WAKEUPIOSRC_PIO0_INDEX; - wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO0_INDEX); - use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK) >> - LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX); - - if (use_external_pullupdown == 0UL) - { - if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) - { - /* Rising edge and both rising and falling edges */ - IOCON->PIO[1][1] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); - } - else - { - if (wake_up_type == 2UL) - { - /* Falling edge only */ - IOCON->PIO[1][1] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); - } - else - { - /* Wake-up I/O is disabled : set it as required by the user */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as Plain Input */ - // @TODO not used p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-up or pull-down */ - // @TODO update for mask name - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as pull-up */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-down */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); - } - } - } - } - } - else - { - wakeup_io_ctrl_reg |= ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); - } - - /* Wake-up I/O 1 */ - wake_up_type = (p_wakeup_io_ctrl & 0xCUL) >> LOWPOWER_WAKEUPIOSRC_PIO1_INDEX; - wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO1_INDEX); - use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK) >> - LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX); - - if (use_external_pullupdown == 0UL) - { - if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) - { - /* Rising edge and both rising and falling edges */ - IOCON->PIO[0][28] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); - } - else - { - if (wake_up_type == 2UL) - { - /* Falling edge only */ - IOCON->PIO[0][28] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); - } - else - { - /* Wake-up I/O is disabled : set it as required by the user */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as Plain Input */ - // @TODO not used p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-up or pull-down */ - // @TODO update for mask name - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as pull-up */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-down */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); - } - } - } - } - } - else - { - wakeup_io_ctrl_reg |= ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); - } - - /* Wake-up I/O 2 */ - wake_up_type = (p_wakeup_io_ctrl & 0x30UL) >> LOWPOWER_WAKEUPIOSRC_PIO2_INDEX; - wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO2_INDEX); - use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK) >> - LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX); - - if (use_external_pullupdown == 0UL) - { - if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) - { - /* Rising edge and both rising and falling edges */ - IOCON->PIO[1][18] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); - } - else - { - if (wake_up_type == 2UL) - { - /* Falling edge only */ - IOCON->PIO[1][18] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); - } - else - { - /* Wake-up I/O is disabled : set it as required by the user */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as Plain Input */ - // @TODO not used p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-up or pull-down */ - // @TODO update for mask name - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as pull-up */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-down */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); - } - } - } - } - } - else - { - wakeup_io_ctrl_reg |= ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); - } - - /* Wake-up I/O 3 */ - wake_up_type = (p_wakeup_io_ctrl & 0xC0UL) >> LOWPOWER_WAKEUPIOSRC_PIO3_INDEX; - wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO3_INDEX); - use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK) >> - LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX); - - if (use_external_pullupdown == 0UL) - { - if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) - { - /* Rising edge and both rising and falling edges */ - IOCON->PIO[1][30] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); - } - else - { - if (wake_up_type == 2UL) - { - /* Falling edge only */ - IOCON->PIO[1][30] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); - } - else - { - /* Wake-up I/O is disabled : set it as required by the user */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as Plain Input */ - // @TODO not used p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-up or pull-down */ - // @TODO update for mask name - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as pull-up */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-down */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); - } - } - } - } - } - else - { - wakeup_io_ctrl_reg |= ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); - } - - return (wakeup_io_ctrl_reg); -} - -/** - * @brief - * @param - * @return - */ -static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity) -{ - /* Compensate for discontinuity in the capacitor banks */ - if (u8OscCap < 64U) - { - if (u8OscCap >= u8CapBankDiscontinuity) - { - u8OscCap -= u8CapBankDiscontinuity; - } - else - { - u8OscCap = 0U; - } - } - else - { - if (u8OscCap <= (127U - u8CapBankDiscontinuity)) - { - u8OscCap += u8CapBankDiscontinuity; - } - else - { - u8OscCap = 127U; - } - } - return u8OscCap; -} - -/** - * @brief Described in fsl_common.h - * @param - * @return - */ -static void lowpower_set_system_voltage(uint32_t system_voltage_mv) -{ - /* - * Set system voltage - */ - uint32_t lv_ldo_ao = (uint32_t)V_AO_1P100; /* */ - uint32_t lv_ldo_ao_boost = (uint32_t)V_AO_1P150; /* */ - uint32_t lv_dcdc = (uint32_t)V_DCDC_1P100; /* */ - - if (system_voltage_mv <= 950UL) - { - lv_dcdc = (uint32_t)V_DCDC_0P950; - lv_ldo_ao = (uint32_t)V_AO_0P960; - lv_ldo_ao_boost = (uint32_t)V_AO_1P010; - } - else if (system_voltage_mv <= 975UL) - { - lv_dcdc = (uint32_t)V_DCDC_0P975; - lv_ldo_ao = (uint32_t)V_AO_0P980; - lv_ldo_ao_boost = (uint32_t)V_AO_1P030; - } - else if (system_voltage_mv <= 1000UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P000; - lv_ldo_ao = (uint32_t)V_AO_1P000; - lv_ldo_ao_boost = (uint32_t)V_AO_1P050; - } - else if (system_voltage_mv <= 1025UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P025; - lv_ldo_ao = (uint32_t)V_AO_1P030; - lv_ldo_ao_boost = (uint32_t)V_AO_1P080; - } - else if (system_voltage_mv <= 1050UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P050; - lv_ldo_ao = (uint32_t)V_AO_1P060; - lv_ldo_ao_boost = (uint32_t)V_AO_1P110; - } - else if (system_voltage_mv <= 1075UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P075; - lv_ldo_ao = (uint32_t)V_AO_1P080; - lv_ldo_ao_boost = (uint32_t)V_AO_1P130; - } - else if (system_voltage_mv <= 1100UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P100; - lv_ldo_ao = (uint32_t)V_AO_1P100; - lv_ldo_ao_boost = (uint32_t)V_AO_1P150; - } - else if (system_voltage_mv <= 1125UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P125; - lv_ldo_ao = (uint32_t)V_AO_1P130; - lv_ldo_ao_boost = (uint32_t)V_AO_1P160; - } - else if (system_voltage_mv <= 1150UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P150; - lv_ldo_ao = (uint32_t)V_AO_1P160; - lv_ldo_ao_boost = (uint32_t)V_AO_1P220; - } - else if (system_voltage_mv <= 1175UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P175; - lv_ldo_ao = (uint32_t)V_AO_1P160; - lv_ldo_ao_boost = (uint32_t)V_AO_1P220; - } - else - { - lv_dcdc = (uint32_t)V_DCDC_1P200; - lv_ldo_ao = (uint32_t)V_AO_1P160; - lv_ldo_ao_boost = (uint32_t)V_AO_1P220; - } - - /* Set up LDO Always-On voltages */ - PMC->LDOPMU = (PMC->LDOPMU & (~PMC_LDOPMU_VADJ_MASK) & (~PMC_LDOPMU_VADJ_BOOST_MASK)) | PMC_LDOPMU_VADJ(lv_ldo_ao) | - PMC_LDOPMU_VADJ_BOOST(lv_ldo_ao_boost); - - /* Set up DCDC voltage */ - PMC->DCDC0 = (PMC->DCDC0 & (~PMC_DCDC0_VOUT_MASK)) | PMC_DCDC0_VOUT(lv_dcdc); -} - -/** - * @brief Described in fsl_common.h - * @param - * @return - */ -static void lowpower_set_dcdc_power_profile(lowpower_dcdc_power_profile_enum dcdc_power_profile) -{ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ADDRS (FLASH_NMPA_BASE + 0xE0U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ADDRS (FLASH_NMPA_BASE + 0xE4U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ADDRS (FLASH_NMPA_BASE + 0xE8U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ADDRS (FLASH_NMPA_BASE + 0xECU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ADDRS (FLASH_NMPA_BASE + 0xD8U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ADDRS (FLASH_NMPA_BASE + 0xDCU) - - const uint32_t PMC_DCDC0_DEFAULT = 0x010C4E68; - const uint32_t PMC_DCDC1_DEFAULT = 0x01803A98; - - uint32_t dcdcTrimValue0; - uint32_t dcdcTrimValue1; - - switch (dcdc_power_profile) - { - case DCDC_POWER_PROFILE_LOW: - /* Low */ - dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ADDRS))); - dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ADDRS))); - - if (0UL != (dcdcTrimValue0 & 0x1UL)) - { - dcdcTrimValue0 = dcdcTrimValue0 >> 1; - - PMC->DCDC0 = dcdcTrimValue0; - PMC->DCDC1 = dcdcTrimValue1; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : DCDC Power Profile set to " - "LOW" - "\n"); -#endif - } - break; - - case DCDC_POWER_PROFILE_MEDIUM: - /* Medium */ - dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ADDRS))); - dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ADDRS))); - - if (0UL != (dcdcTrimValue0 & 0x1UL)) - { - dcdcTrimValue0 = dcdcTrimValue0 >> 1; - - PMC->DCDC0 = dcdcTrimValue0; - PMC->DCDC1 = dcdcTrimValue1; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : DCDC Power Profile set to " - "MEDIUM" - "\n"); -#endif - } - break; - - case DCDC_POWER_PROFILE_HIGH: - /* High */ - dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ADDRS))); - dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ADDRS))); - - if (0UL != (dcdcTrimValue0 & 0x1UL)) - { - dcdcTrimValue0 = dcdcTrimValue0 >> 1; - - PMC->DCDC0 = dcdcTrimValue0; - PMC->DCDC1 = dcdcTrimValue1; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : DCDC Power Profile set to " - "HIGH" - "\n"); -#endif - } - break; - - default: - /* Low */ - PMC->DCDC0 = PMC_DCDC0_DEFAULT; - PMC->DCDC1 = PMC_DCDC1_DEFAULT; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : DCDC Power Profile set to " - "LOW" - "\n"); -#endif - break; - } -} - -/** - * @brief - * @param - * @return - */ -static lowpower_process_corner_enum lowpower_get_part_process_corner(void) -{ -#define FLASH_NMPA_PVT_MONITOR_0_RINGO_ADDRS (FLASH_NMPA_BASE + 0x130U) -#define FLASH_NMPA_PVT_MONITOR_1_RINGO_ADDRS (FLASH_NMPA_BASE + 0x140U) - - lowpower_process_corner_enum part_process_corner; - uint32_t pvt_ringo_hz; - uint32_t pvt_ringo_0 = (*((volatile unsigned int *)(FLASH_NMPA_PVT_MONITOR_0_RINGO_ADDRS))); - uint32_t pvt_ringo_1 = (*((volatile unsigned int *)(FLASH_NMPA_PVT_MONITOR_1_RINGO_ADDRS))); - - /* - * Check that the PVT Monitors Trimmings in flash are valid. - */ - if (0UL != (pvt_ringo_0 & 0x1UL)) - { - /* PVT Trimmings in Flash are valid */ - pvt_ringo_0 = pvt_ringo_0 >> 1; - } - else - { - /* PVT Trimmings in Flash are NOT valid (average value assumed) */ - pvt_ringo_0 = PROCESS_NNN_AVG_HZ; - } - - if (0UL != (pvt_ringo_1 & 0x1UL)) - { - /* PVT Trimmings in Flash are valid */ - pvt_ringo_1 = pvt_ringo_1 >> 1; - } - else - { - /* PVT Trimmings in Flash are NOT valid (average value assumed) */ - pvt_ringo_1 = PROCESS_NNN_AVG_HZ; - } - - if (pvt_ringo_1 <= pvt_ringo_0) - { - pvt_ringo_hz = pvt_ringo_1; - } - else - { - pvt_ringo_hz = pvt_ringo_0; - } - - /* - * Determine the process corner based on the value of the Ring Oscillator frequency - */ - if (pvt_ringo_hz <= PROCESS_NNN_MIN_HZ) - { - /* SSS Process Corner */ - part_process_corner = PROCESS_CORNER_SSS; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : Process Corner : " - "SSS" - "\n"); -#endif - } - else - { - if (pvt_ringo_hz <= PROCESS_NNN_MAX_HZ) - { - /* NNN Process Corner */ - part_process_corner = PROCESS_CORNER_NNN; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : Process Corner : " - "NNN" - "\n"); -#endif - } - else - { - /* FFF Process Corner */ - part_process_corner = PROCESS_CORNER_FFF; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : Process Corner : " - "FFF" - "\n"); -#endif - } - } - - return (part_process_corner); -} - -/** - * @brief Described in fsl_common.h - * @param - * @return - */ -static void lowpower_set_voltage_for_process(lowpower_dcdc_power_profile_enum dcdc_power_profile) -{ - /* Get Sample Process Corner */ - lowpower_process_corner_enum part_process_corner = lowpower_get_part_process_corner(); - - switch (part_process_corner) - { - case PROCESS_CORNER_SSS: - /* Slow Corner */ - { - switch (dcdc_power_profile) - { - case DCDC_POWER_PROFILE_MEDIUM: - /* Medium */ - lowpower_set_system_voltage(VOLTAGE_SSS_MED_MV); - break; - - case DCDC_POWER_PROFILE_HIGH: - /* High */ - lowpower_set_system_voltage(VOLTAGE_SSS_HIG_MV); - break; - - default: - /* DCDC_POWER_PROFILE_LOW */ - lowpower_set_system_voltage(VOLTAGE_SSS_LOW_MV); - break; - } // switch(dcdc_power_profile) - } - break; - - case PROCESS_CORNER_FFF: - /* Fast Corner */ - { - switch (dcdc_power_profile) - { - case DCDC_POWER_PROFILE_MEDIUM: - /* Medium */ - lowpower_set_system_voltage(VOLTAGE_FFF_MED_MV); - break; - - case DCDC_POWER_PROFILE_HIGH: - /* High */ - lowpower_set_system_voltage(VOLTAGE_FFF_HIG_MV); - break; - - default: - /* DCDC_POWER_PROFILE_LOW */ - lowpower_set_system_voltage(VOLTAGE_FFF_LOW_MV); - break; - } // switch(dcdc_power_profile) - } - break; - - default: - /* Nominal (NNN) and all others Process Corners : assume Nominal Corner */ - { - switch (dcdc_power_profile) - { - case DCDC_POWER_PROFILE_MEDIUM: - /* Medium */ - lowpower_set_system_voltage(VOLTAGE_NNN_MED_MV); - break; - - case DCDC_POWER_PROFILE_HIGH: - /* High */ - lowpower_set_system_voltage(VOLTAGE_NNN_HIG_MV); - break; - - default: - /* DCDC_POWER_PROFILE_LOW */ - lowpower_set_system_voltage(VOLTAGE_NNN_LOW_MV); - break; - } // switch(dcdc_power_profile) - break; - } - } // switch(part_process_corner) -} - -/** - * @brief Described in fsl_common.h - * @param - * @return - */ -void POWER_SetVoltageForFreq(uint32_t system_freq_hz) -{ - if (system_freq_hz <= DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ) - { - /* [0 Hz - DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz] */ - lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_LOW); /* DCDC VOUT = 1.05 V by default */ - lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_LOW); - } - else - { - if (system_freq_hz <= DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ) - { - /* ]DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz - DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz] */ - lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_MEDIUM); /* DCDC VOUT = 1.15 V by default */ - lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_MEDIUM); - } - else - { - /* > DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz */ - lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_HIGH); /* DCDC VOUT = 1.2 V by default */ - lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_HIGH); - } - } -} - -void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, - int32_t pi32_16MfXtalPPcbParCappF_x100, - int32_t pi32_16MfXtalNPcbParCappF_x100) -{ - uint32_t u32XOTrimValue; - uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF, u8XOSlave; - int32_t iaXin_x4, ibXin, iaXout_x4, ibXout; - int32_t iXOCapInpF_x100, iXOCapOutpF_x100; - uint8_t u8XOCapInCtrl, u8XOCapOutCtrl; - uint32_t u32RegVal; - int32_t i32Tmp; - - /* Enable and set LDO, if not already done */ - POWER_SetXtal16mhzLdo(); - /* Get Cal values from Flash */ - u32XOTrimValue = GET_16MXO_TRIM(); - /* Check validity and apply */ - if ((0UL != (u32XOTrimValue & 1UL)) && (0UL != ((u32XOTrimValue >> 15UL) & 1UL))) - { - /* These fields are 7 bits, unsigned */ - u8IECXinCapCal6pF = (uint8_t)((u32XOTrimValue >> 1UL) & 0x7fUL); - u8IECXinCapCal8pF = (uint8_t)((u32XOTrimValue >> 8UL) & 0x7fUL); - u8IECXoutCapCal6pF = (uint8_t)((u32XOTrimValue >> 16UL) & 0x7fUL); - u8IECXoutCapCal8pF = (uint8_t)((u32XOTrimValue >> 23UL) & 0x7fUL); - /* This field is 1 bit */ - u8XOSlave = (uint8_t)((u32XOTrimValue >> 30UL) & 0x1UL); - /* Linear fit coefficients calculation */ - iaXin_x4 = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF; - ibXin = (int)u8IECXinCapCal6pF - iaXin_x4 * 3; - iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF; - ibXout = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3; - } - else - { - iaXin_x4 = 20; // gain in LSB/pF - ibXin = -9; // offset in LSB - iaXout_x4 = 20; // gain in LSB/pF - ibXout = -13; // offset in LSB - u8XOSlave = 0; - } - /* In & out load cap calculation with derating */ - iXOCapInpF_x100 = 2 * pi32_16MfXtalIecLoadpF_x100 - pi32_16MfXtalNPcbParCappF_x100 + - 39 * ((int32_t)XO_SLAVE_EN - (int32_t)u8XOSlave) - 15; - iXOCapOutpF_x100 = 2 * pi32_16MfXtalIecLoadpF_x100 - pi32_16MfXtalPPcbParCappF_x100 - 21; - /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */ - i32Tmp = ((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400; - u8XOCapInCtrl = (uint8_t)i32Tmp; - i32Tmp = ((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400; - u8XOCapOutCtrl = (uint8_t)i32Tmp; - /* Read register and clear fields to be written */ - u32RegVal = ANACTRL->XO32M_CTRL; - u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); - /* Configuration of 32 MHz XO output buffers */ -#if (XO_SLAVE_EN == 0) - u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); -#else - u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; -#endif - /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */ - u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT; - u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT; - /* Write back to register */ - ANACTRL->XO32M_CTRL = u32RegVal; -} - -void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, - int32_t pi32_32kfXtalPPcbParCappF_x100, - int32_t pi32_32kfXtalNPcbParCappF_x100) -{ - uint32_t u32XOTrimValue; - uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF; - int32_t iaXin_x4, ibXin, iaXout_x4, ibXout; - int32_t iXOCapInpF_x100, iXOCapOutpF_x100; - uint8_t u8XOCapInCtrl, u8XOCapOutCtrl; - uint32_t u32RegVal; - int32_t i32Tmp; - /* Get Cal values from Flash */ - u32XOTrimValue = GET_32KXO_TRIM(); - /* check validity and apply */ - if ((0UL != (u32XOTrimValue & 1UL)) && (0UL != ((u32XOTrimValue >> 15UL) & 1UL))) - { - /* These fields are 7 bits, unsigned */ - u8IECXinCapCal6pF = (uint8_t)((u32XOTrimValue >> 1UL) & 0x7fUL); - u8IECXinCapCal8pF = (uint8_t)((u32XOTrimValue >> 8UL) & 0x7fUL); - u8IECXoutCapCal6pF = (uint8_t)((u32XOTrimValue >> 16UL) & 0x7fUL); - u8IECXoutCapCal8pF = (uint8_t)((u32XOTrimValue >> 23UL) & 0x7fUL); - /* Linear fit coefficients calculation */ - iaXin_x4 = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF; - ibXin = (int)u8IECXinCapCal6pF - iaXin_x4 * 3; - iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF; - ibXout = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3; - } - else - { - iaXin_x4 = 16; // gain in LSB/pF - ibXin = 12; // offset in LSB - iaXout_x4 = 16; // gain in LSB/pF - ibXout = 11; // offset in LSB - } - - /* In & out load cap calculation with derating */ - iXOCapInpF_x100 = 2 * pi32_32kfXtalIecLoadpF_x100 - pi32_32kfXtalNPcbParCappF_x100 - 130; - iXOCapOutpF_x100 = 2 * pi32_32kfXtalIecLoadpF_x100 - pi32_32kfXtalPPcbParCappF_x100 - 41; - - /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */ - i32Tmp = ((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400; - u8XOCapInCtrl = (uint8_t)i32Tmp; - i32Tmp = ((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400; - u8XOCapOutCtrl = (uint8_t)i32Tmp; - - /* Read register and clear fields to be written */ - u32RegVal = PMC->XTAL32K; - u32RegVal &= ~(PMC_XTAL32K_CAPBANKIN_MASK | PMC_XTAL32K_CAPBANKOUT_MASK); - - /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */ - u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 23) << PMC_XTAL32K_CAPBANKIN_SHIFT; - u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 23) << PMC_XTAL32K_CAPBANKOUT_SHIFT; - - /* Write back to register */ - PMC->XTAL32K = u32RegVal; -} - -void POWER_SetXtal16mhzLdo(void) -{ - uint32_t temp; - const uint32_t u32Mask = - (ANACTRL_LDO_XO32M_VOUT_MASK | ANACTRL_LDO_XO32M_IBIAS_MASK | ANACTRL_LDO_XO32M_STABMODE_MASK); - - const uint32_t u32Value = - (ANACTRL_LDO_XO32M_VOUT(0x5) | ANACTRL_LDO_XO32M_IBIAS(0x2) | ANACTRL_LDO_XO32M_STABMODE(0x1)); - - /* Enable & set-up XTAL 32 MHz clock LDO */ - temp = ANACTRL->LDO_XO32M; - - if ((temp & u32Mask) != u32Value) - { - temp &= ~u32Mask; - - /* - * Enable the XTAL32M LDO - * Adjust the output voltage level, 0x5 for 1.1V - * Adjust the biasing current, 0x2 value - * Stability configuration, 0x1 default mode - */ - temp |= u32Value; - - ANACTRL->LDO_XO32M = temp; - - /* Delay for LDO to be up */ - // CLOCK_uDelay(20); - } - - /* Enable LDO XO32M */ - PMC->PDRUNCFGCLR0 = PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK; -} - -void POWER_SetXtal16mhzTrim(uint32_t amp, uint32_t gm) -{ - uint32_t temp; - const uint32_t u32Mask = (ANACTRL_XO32M_CTRL_AMP_MASK | ANACTRL_XO32M_CTRL_GM_MASK); - const uint32_t u32Value = (ANACTRL_XO32M_CTRL_AMP(amp) | ANACTRL_XO32M_CTRL_GM(gm)); - - /* Set-up XTAL 16-MHz Trimmings */ - temp = ANACTRL->XO32M_CTRL; - temp &= ~u32Mask; - temp |= u32Value; - ANACTRL->XO32M_CTRL = temp; -} - -/*! - * @brief set BOD VBAT level. - * - * @param level BOD detect level - * @param hyst BoD Hysteresis control - * @param enBodVbatReset VBAT brown out detect reset - */ -void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset) -{ - uint32_t pmc_reset_ctrl; - /* BOD VBAT disable reset */ - pmc_reset_ctrl = - PMC->RESETCTRL & (~(PMC_RESETCTRL_BODVBATRESETENA_SECURE_MASK | PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_MASK)); - pmc_reset_ctrl |= (0x2UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_SHIFT) | - (0x2UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_SHIFT); - - PMC->RESETCTRL = pmc_reset_ctrl; - - PMC->BODVBAT = (PMC->BODVBAT & (~(PMC_BODVBAT_TRIGLVL_MASK | PMC_BODVBAT_HYST_MASK))) | PMC_BODVBAT_TRIGLVL(level) | - PMC_BODVBAT_HYST(hyst); - - /* BOD VBAT enable reset */ - if ((uint32_t)enBodVbatReset == 1UL) - { - pmc_reset_ctrl &= (~(PMC_RESETCTRL_BODVBATRESETENA_SECURE_MASK | PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_MASK)); - pmc_reset_ctrl |= (0x1UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_SHIFT) | - (0x1UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_SHIFT); - PMC->RESETCTRL = pmc_reset_ctrl; - } -} - -#if defined(PMC_BODCORE_TRIGLVL_MASK) -/*! - * @brief set BOD core level. - * - * @param level BOD detect level - * @param hyst BoD Hysteresis control - * @param enBodCoreReset core brown out detect reset - */ -void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset) -{ - uint32_t pmc_reset_ctrl; - /* BOD CORE disable reset */ - pmc_reset_ctrl = - PMC->RESETCTRL & (~(PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK | PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK)); - pmc_reset_ctrl |= - (0x2 << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT) | (0x2 << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT); - - PMC->RESETCTRL = pmc_reset_ctrl; - - PMC->BODCORE = (PMC->BODCORE & (~(PMC_BODCORE_TRIGLVL_MASK | PMC_BODCORE_HYST_MASK))) | PMC_BODCORE_TRIGLVL(level) | - PMC_BODCORE_HYST(hyst); - - /* BOD CORE enable reset */ - if (enBodCoreReset == 1) - { - pmc_reset_ctrl &= (~(PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK | PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK)); - pmc_reset_ctrl |= (0x1 << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT) | - (0x1 << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT); - PMC->RESETCTRL = pmc_reset_ctrl; - } -} -#endif - -/** - * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes. - * @param p_reset_cause : the device reset cause, according to the definition of power_device_reset_cause_t type. - * @param p_boot_mode : the device boot mode, according to the definition of power_device_boot_mode_t type. - * @param p_wakeupio_cause: the wake-up pin sources, according to the definition of register PMC->WAKEIOCAUSE[3:0]. - - * @return Nothing - * - * !!! IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA !!! - * !!! valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06) !!! - * !!! when FALLING EDGE DETECTION is enabled on wake-up pins: !!! - * - 1. p_wakeupio_cause is NOT ACCURATE - * - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when - * several wake-up sources are enabled during DEEP-POWER-DOWN - * (like enabling wake-up on RTC and Falling edge wake-up pins) - * - */ -void POWER_GetWakeUpCause(power_device_reset_cause_t *p_reset_cause, - power_device_boot_mode_t *p_boot_mode, - uint32_t *p_wakeupio_cause) -{ - uint32_t reset_cause_reg; - uint32_t boot_mode_reg; - -#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ - defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ - defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) - reset_cause_reg = (PMC->AOREG1) & 0x3FF0UL; -#else /* LPC55S69/28 */ - reset_cause_reg = (PMC->AOREG1) & 0x1FF0UL; -#endif - - /* - * Prioritize interrupts source with respect to their critical level - */ -#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ - defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ - defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) - if (0UL != (reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK)) - { /* Code Watchdog Reset */ - *p_reset_cause = kRESET_CAUSE_CDOGRESET; - *p_boot_mode = kBOOT_MODE_POWER_UP; - *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ - } - else -#endif - { - if (0UL != (reset_cause_reg & PMC_AOREG1_WDTRESET_MASK)) - { /* Watchdog Timer Reset */ - *p_reset_cause = kRESET_CAUSE_WDTRESET; - *p_boot_mode = kBOOT_MODE_POWER_UP; - *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ - } - else - { - if (0UL != (reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK)) - { /* ARM System Reset */ - *p_reset_cause = kRESET_CAUSE_ARMSYSTEMRESET; - *p_boot_mode = kBOOT_MODE_POWER_UP; - *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ - } - else - { - boot_mode_reg = (PMC->STATUS & PMC_STATUS_BOOTMODE_MASK) >> PMC_STATUS_BOOTMODE_SHIFT; - - if (boot_mode_reg == 0UL) /* POWER-UP: Power On Reset, Pin reset, Brown Out Detectors, Software Reset */ - { - *p_boot_mode = kBOOT_MODE_POWER_UP; /* All non wake-up from a Low Power mode */ - *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ - - /* - * Prioritise Reset causes, starting from the strongest (Power On Reset) - */ - if (0UL != (reset_cause_reg & PMC_AOREG1_POR_MASK)) - { /* Power On Reset */ - *p_reset_cause = kRESET_CAUSE_POR; - } - else - { - if (0UL != (reset_cause_reg & PMC_AOREG1_BODRESET_MASK)) - { /* Brown-out Detector reset (either BODVBAT or BODCORE) */ - *p_reset_cause = kRESET_CAUSE_BODRESET; - } - else - { - if (0UL != (reset_cause_reg & PMC_AOREG1_PADRESET_MASK)) - { /* Hardware Pin Reset */ - *p_reset_cause = kRESET_CAUSE_PADRESET; - } - else - { - if (0UL != (reset_cause_reg & PMC_AOREG1_SWRRESET_MASK)) - { /* Software triggered Reset */ - *p_reset_cause = kRESET_CAUSE_SWRRESET; - } - else - { /* Unknown Reset Cause */ - *p_reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC; - } - } - } - } - -#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ - defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ - defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) - /* Transfer the control of the 4 wake-up pins to IOCON (instead of the Power Management Controller - */ - PMC->WAKEUPIOCTRL = PMC->WAKEUPIOCTRL & (~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK); -#endif - } - else /* DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN */ - { - /* - * 1- First, save wakeup_io_cause register ... - */ - *p_wakeupio_cause = PMC->WAKEIOCAUSE; - - if (boot_mode_reg == 3UL) /* DEEP-POWER-DOWN */ - { - *p_boot_mode = kBOOT_MODE_LP_DEEP_POWER_DOWN; - - switch (((reset_cause_reg >> PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT) & 0x7UL)) - { - case 1: - *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO; - break; - case 2: - *p_reset_cause = kRESET_CAUSE_DPDRESET_RTC; - break; - case 3: - *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC; - break; - case 4: - *p_reset_cause = kRESET_CAUSE_DPDRESET_OSTIMER; - break; - case 5: - *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER; - break; - case 6: - *p_reset_cause = kRESET_CAUSE_DPDRESET_RTC_OSTIMER; - break; - case 7: - *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER; - break; - default: - /* Unknown Reset Cause */ - *p_reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC; - break; - } - -#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ - defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ - defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) - /* - * 2- Next, transfer the control of the 4 wake-up pins - * to IOCON (instead of the Power Management Controller) - */ - PMC->WAKEUPIOCTRL = PMC->WAKEUPIOCTRL & (~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK); -#endif - } - else /* DEEP-SLEEP and POWER-DOWN */ - { - *p_reset_cause = kRESET_CAUSE_NOT_RELEVANT; - - /* - * The control of the 4 wake-up pins is already in IOCON, - * so there is nothing special to do. - */ - - if (boot_mode_reg == 1UL) /* DEEP-SLEEP */ - { - *p_boot_mode = kBOOT_MODE_LP_DEEP_SLEEP; - } - else /* POWER-DOWN */ - { - *p_boot_mode = kBOOT_MODE_LP_POWER_DOWN; - - } /* if ( boot_mode_reg == 1 ) DEEP-SLEEP */ - - } /* if ( boot_mode == 3 ) DEEP-POWER-DOWN */ - - } /* if ( boot_mode == 0 ) POWER-UP */ - - } /* if ( reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK ) */ - - } /* if ( reset_cause_reg & PMC_AOREG1_WDTRESET_MASK ) */ - - } /* if ( reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK ) */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_power.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_power.h deleted file mode 100644 index 596d0106e98..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_power.h +++ /dev/null @@ -1,605 +0,0 @@ -/* - * Copyright 2017, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_POWER_H_ -#define _FSL_POWER_H_ - -#include "fsl_common.h" -#include "fsl_device_registers.h" -#include - -/*! - * @addtogroup power - * @{ - */ -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief power driver version 2.3.2. */ -#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 3, 2)) -/*@}*/ - -/* Power mode configuration API parameter */ -typedef enum _power_mode_config -{ - kPmu_Sleep = 0U, - kPmu_Deep_Sleep = 1U, - kPmu_PowerDown = 2U, - kPmu_Deep_PowerDown = 3U, -} power_mode_cfg_t; - -/** - * @brief Analog components power modes control during low power modes - */ -typedef enum pd_bits -{ - kPDRUNCFG_PD_DCDC = (1UL << 0), - kPDRUNCFG_PD_BIAS = (1UL << 1), - kPDRUNCFG_PD_BODCORE = (1UL << 2), - kPDRUNCFG_PD_BODVBAT = (1UL << 3), - kPDRUNCFG_PD_FRO1M = (1UL << 4), - kPDRUNCFG_PD_FRO192M = (1UL << 5), - kPDRUNCFG_PD_FRO32K = (1UL << 6), - kPDRUNCFG_PD_XTAL32K = (1UL << 7), - kPDRUNCFG_PD_XTAL32M = (1UL << 8), - kPDRUNCFG_PD_PLL0 = (1UL << 9), - kPDRUNCFG_PD_PLL1 = (1UL << 10), - kPDRUNCFG_PD_COMP = (1UL << 13), - kPDRUNCFG_PD_TEMPSENS = (1UL << 14), - kPDRUNCFG_PD_GPADC = (1UL << 15), - kPDRUNCFG_PD_LDOMEM = (1UL << 16), - kPDRUNCFG_PD_LDODEEPSLEEP = (1UL << 17), - kPDRUNCFG_PD_LDOGPADC = (1UL << 19), - kPDRUNCFG_PD_LDOXO32M = (1UL << 20), - kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21), - kPDRUNCFG_PD_RNG = (1UL << 22), - kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23), - kPDRUNCFG_PD_ROM = (1UL << 24), - /* - This enum member has no practical meaning,it is used to avoid MISRA issue, - user should not trying to use it. - */ - kPDRUNCFG_ForceUnsigned = 0x80000000U, -} pd_bit_t; - -/** - * @brief BOD VBAT level - */ -typedef enum _power_bod_vbat_level -{ - kPOWER_BodVbatLevel1000mv = 0, /*!< Brown out detector VBAT level 1V */ - kPOWER_BodVbatLevel1100mv = 1, /*!< Brown out detector VBAT level 1.1V */ - kPOWER_BodVbatLevel1200mv = 2, /*!< Brown out detector VBAT level 1.2V */ - kPOWER_BodVbatLevel1300mv = 3, /*!< Brown out detector VBAT level 1.3V */ - kPOWER_BodVbatLevel1400mv = 4, /*!< Brown out detector VBAT level 1.4V */ - kPOWER_BodVbatLevel1500mv = 5, /*!< Brown out detector VBAT level 1.5V */ - kPOWER_BodVbatLevel1600mv = 6, /*!< Brown out detector VBAT level 1.6V */ - kPOWER_BodVbatLevel1650mv = 7, /*!< Brown out detector VBAT level 1.65V */ - kPOWER_BodVbatLevel1700mv = 8, /*!< Brown out detector VBAT level 1.7V */ - kPOWER_BodVbatLevel1750mv = 9, /*!< Brown out detector VBAT level 1.75V */ - kPOWER_BodVbatLevel1800mv = 10, /*!< Brown out detector VBAT level 1.8V */ - kPOWER_BodVbatLevel1900mv = 11, /*!< Brown out detector VBAT level 1.9V */ - kPOWER_BodVbatLevel2000mv = 12, /*!< Brown out detector VBAT level 2V */ - kPOWER_BodVbatLevel2100mv = 13, /*!< Brown out detector VBAT level 2.1V */ - kPOWER_BodVbatLevel2200mv = 14, /*!< Brown out detector VBAT level 2.2V */ - kPOWER_BodVbatLevel2300mv = 15, /*!< Brown out detector VBAT level 2.3V */ - kPOWER_BodVbatLevel2400mv = 16, /*!< Brown out detector VBAT level 2.4V */ - kPOWER_BodVbatLevel2500mv = 17, /*!< Brown out detector VBAT level 2.5V */ - kPOWER_BodVbatLevel2600mv = 18, /*!< Brown out detector VBAT level 2.6V */ - kPOWER_BodVbatLevel2700mv = 19, /*!< Brown out detector VBAT level 2.7V */ - kPOWER_BodVbatLevel2806mv = 20, /*!< Brown out detector VBAT level 2.806V */ - kPOWER_BodVbatLevel2900mv = 21, /*!< Brown out detector VBAT level 2.9V */ - kPOWER_BodVbatLevel3000mv = 22, /*!< Brown out detector VBAT level 3.0V */ - kPOWER_BodVbatLevel3100mv = 23, /*!< Brown out detector VBAT level 3.1V */ - kPOWER_BodVbatLevel3200mv = 24, /*!< Brown out detector VBAT level 3.2V */ - kPOWER_BodVbatLevel3300mv = 25, /*!< Brown out detector VBAT level 3.3V */ -} power_bod_vbat_level_t; - -/** - * @brief BOD Hysteresis control - */ -typedef enum _power_bod_hyst -{ - kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */ - kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */ - kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */ - kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */ -} power_bod_hyst_t; -/** - * @brief BOD core level - */ -typedef enum _power_bod_core_level -{ - kPOWER_BodCoreLevel600mv = 0, /*!< Brown out detector core level 600mV */ - kPOWER_BodCoreLevel650mv = 1, /*!< Brown out detector core level 650mV */ - kPOWER_BodCoreLevel700mv = 2, /*!< Brown out detector core level 700mV */ - kPOWER_BodCoreLevel750mv = 3, /*!< Brown out detector core level 750mV */ - kPOWER_BodCoreLevel800mv = 4, /*!< Brown out detector core level 800mV */ - kPOWER_BodCoreLevel850mv = 5, /*!< Brown out detector core level 850mV */ - kPOWER_BodCoreLevel900mv = 6, /*!< Brown out detector core level 900mV */ - kPOWER_BodCoreLevel950mv = 7, /*!< Brown out detector core level 950mV */ -} power_bod_core_level_t; - -/** - * @brief Device Reset Causes - */ -typedef enum _power_device_reset_cause -{ - kRESET_CAUSE_POR = 0UL, /*!< Power On Reset */ - kRESET_CAUSE_PADRESET = 1UL, /*!< Hardware Pin Reset */ - kRESET_CAUSE_BODRESET = 2UL, /*!< Brown-out Detector reset (either BODVBAT or BODCORE) */ - kRESET_CAUSE_ARMSYSTEMRESET = 3UL, /*!< ARM System Reset */ - kRESET_CAUSE_WDTRESET = 4UL, /*!< Watchdog Timer Reset */ - kRESET_CAUSE_SWRRESET = 5UL, /*!< Software Reset */ - kRESET_CAUSE_CDOGRESET = 6UL, /*!< Code Watchdog Reset */ - /* Reset causes in DEEP-POWER-DOWN low power mode */ - kRESET_CAUSE_DPDRESET_WAKEUPIO = 7UL, /*!< Any of the 4 wake-up pins */ - kRESET_CAUSE_DPDRESET_RTC = 8UL, /*!< Real Time Counter (RTC) */ - kRESET_CAUSE_DPDRESET_OSTIMER = 9UL, /*!< OS Event Timer (OSTIMER) */ - kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC = 10UL, /*!< Any of the 4 wake-up pins and RTC (it is not possible to distinguish - which of these 2 events occured first) */ - kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER = 11UL, /*!< Any of the 4 wake-up pins and OSTIMER (it is not possible to - distinguish which of these 2 events occured first) */ - kRESET_CAUSE_DPDRESET_RTC_OSTIMER = 12UL, /*!< Real Time Counter or OS Event Timer (it is not possible to - distinguish which of these 2 events occured first) */ - kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER = 13UL, /*!< Any of the 4 wake-up pins (it is not possible to distinguish - which of these 3 events occured first) */ - /* Miscallenous */ - kRESET_CAUSE_NOT_RELEVANT = - 14UL, /*!< No reset cause (for example, this code is used when waking up from DEEP-SLEEP low power mode) */ - kRESET_CAUSE_NOT_DETERMINISTIC = 15UL, /*!< Unknown Reset Cause. Should be treated like "Hardware Pin Reset" from an - application point of view. */ -} power_device_reset_cause_t; - -/** - * @brief Device Boot Modes - */ -typedef enum _power_device_boot_mode -{ - kBOOT_MODE_POWER_UP = - 0UL, /*!< All non Low Power Mode wake up (Power On Reset, Pin Reset, BoD Reset, ARM System Reset ... ) */ - kBOOT_MODE_LP_DEEP_SLEEP = 1UL, /*!< Wake up from DEEP-SLEEP Low Power mode */ - kBOOT_MODE_LP_POWER_DOWN = 2UL, /*!< Wake up from POWER-DOWN Low Power mode */ - kBOOT_MODE_LP_DEEP_POWER_DOWN = 4UL, /*!< Wake up from DEEP-POWER-DOWN Low Power mode */ -} power_device_boot_mode_t; - -/** - * @brief SRAM instances retention control during low power modes - */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 \ - (1UL << 0) /*!< Enable SRAMX_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 \ - (1UL << 1) /*!< Enable SRAMX_1 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 \ - (1UL << 2) /*!< Enable SRAMX_2 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 \ - (1UL << 3) /*!< Enable SRAMX_3 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM00 \ - (1UL << 4) /*!< Enable SRAM0_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM10 \ - (1UL << 6) /*!< Enable SRAM1_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM20 \ - (1UL << 7) /*!< Enable SRAM2_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM3 \ - (1UL << 14) /*!< Enable SRAM3 retention when entering in Low power modes */ - -/** - * @brief Low Power Modes Wake up sources - */ -#define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/ -#define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */ -#define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */ -#define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */ -#define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */ -// reserved (1ULL << 23) -#define WAKEUP_ACMP (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -// reserved (1ULL << 25) -// reserved (1ULL << 26) -// reserved (1ULL << 27) -// reserved (1ULL << 28) -#define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ -// reserved (1ULL << 30) -// reserved (1ULL << 31) -#define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ -// reserved (1ULL << 39) -// reserved (1ULL << 40) -// reserved (1ULL << 41) -// reserved (1ULL << 42) -#define CAN0_INT0 (1ULL << 43) /*!< [SLEEP, ] */ -#define CAN1_INT0 (1ULL << 44) /*!< [SLEEP, ] */ -// reserved (1ULL << 45) -// reserved (1ULL << 46) -// reserved (1ULL << 47) -// reserved (1ULL << 48) ] */ -#define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */ -#define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SEC_VIO (1ULL << 53) -#define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */ -#define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */ -#define WAKEUP_PUF (1ULL << 56) /*!< [SLEEP, ] */ -// reserved (1ULL << 57) -#define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */ -//#define CDOG (1ULL << 60) !< [SLEEP, ] -// reserved (1ULL << 61) -// reserved (1ULL << 62) -#define WAKEUP_ALLWAKEUPIOS (1ULL << 63) /*!< [ , DEEP POWER DOWN] */ - -/** - * @brief Sleep Postpone - */ -#define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */ -#define LOWPOWER_HWWAKE_PERIPHERALS \ - (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause \ - peripheral clocking to wake up temporarily while the related status is asserted */ -#define LOWPOWER_HWWAKE_SDMA0 \ - (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA \ - completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ -#define LOWPOWER_HWWAKE_SDMA1 \ - (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA \ - completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ -#define LOWPOWER_HWWAKE_ENABLE_FRO192M \ - (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of \ - LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set */ - -#define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */ -#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */ -/** - * @brief Wake up I/O sources - */ -#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */ -#define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */ -#define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */ -#define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */ - -#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */ -#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */ -#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */ -#define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */ - -#define LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX 12 /*!< Pin P1( 1) */ -#define LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX 14 /*!< Pin P0(28) */ -#define LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX 16 /*!< Pin P1(18) */ -#define LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX 18 /*!< Pin P1(30) */ - -#define LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN 0 /*!< Wake up Pad is plain input */ -#define LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN 1 /*!< Wake up Pad is pull-down */ -#define LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP 2 /*!< Wake up Pad is pull-up */ -#define LOWPOWER_WAKEUPIOSRC_IO_MODE_REPEATER 3 /*!< Wake up Pad is in repeater */ - -#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX 8 /*!< Wake-up I/O 0 pull-up/down configuration index */ -#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX 9 /*!< Wake-up I/O 1 pull-up/down configuration index */ -#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX 10 /*!< Wake-up I/O 2 pull-up/down configuration index */ -#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX 11 /*!< Wake-up I/O 3 pull-up/down configuration index */ - -#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down mask */ -#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down mask */ -#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down mask */ -#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down mask */ - -#define LOWPOWER_WAKEUPIO_PULLDOWN 0 /*!< Select pull-down */ -#define LOWPOWER_WAKEUPIO_PULLUP 1 /*!< Select pull-up */ - -#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX \ - 12 /*!< Wake-up I/O 0 pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX \ - 13 /*!< Wake-up I/O 1 pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX \ - 14 /*!< Wake-up I/O 2 pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX \ - 15 /*!< Wake-up I/O 3 pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down disable/enable mask */ -#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down disable/enable mask */ -#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down disable/enable mask */ -#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down disable/enable mask */ - -#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX \ - (16) /*!< Wake-up I/O 0 use external pull-up/down disable/enable control index*/ -#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX \ - (17) /*!< Wake-up I/O 1 use external pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX \ - (18) /*!< Wake-up I/O 2 use external pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX \ - (19) /*!< Wake-up I/O 3 use external pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 use external pull-up/down \ - disable/enable mask, 0: disable, 1: enable */ -#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 use external pull-up/down \ - disable/enable mask, 0: disable, 1: enable */ -#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 use external pull-up/down \ - disable/enable mask, 0: disable, 1: enable */ -#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 use external pull-up/down \ - disable/enable mask, 0: disable, 1: enable */ - -#ifdef __cplusplus -extern "C" { -#endif -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral - * - * @param en peripheral for which to enable the PDRUNCFG bit - * @return none - */ -static inline void POWER_EnablePD(pd_bit_t en) -{ - /* PDRUNCFGSET */ - PMC->PDRUNCFGSET0 = (uint32_t)en; -} - -/*! - * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral - * - * @param en peripheral for which to disable the PDRUNCFG bit - * @return none - */ -static inline void POWER_DisablePD(pd_bit_t en) -{ - /* PDRUNCFGCLR */ - PMC->PDRUNCFGCLR0 = (uint32_t)en; -} - -/*! - * @brief set BOD VBAT level. - * - * @param level BOD detect level - * @param hyst BoD Hysteresis control - * @param enBodVbatReset VBAT brown out detect reset - */ -void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset); - -#if defined(PMC_BODCORE_TRIGLVL_MASK) -/*! - * @brief set BOD core level. - * - * @param level BOD detect level - * @param hyst BoD Hysteresis control - * @param enBodCoreReset core brown out detect reset - */ -void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset); -#endif - -/*! - * @brief API to enable deep sleep bit in the ARM Core. - * - * @return none - */ -static inline void POWER_EnableDeepSleep(void) -{ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; -} - -/*! - * @brief API to disable deep sleep bit in the ARM Core. - * - * @return none - */ -static inline void POWER_DisableDeepSleep(void) -{ - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; -} - -/** - * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event - * This MUST BE EXECUTED outside the Flash: - * either from ROM or from SRAM. The rest could stay in Flash. But, for consistency, it is - * preferable to have all functions defined in this file implemented in ROM. - * - * @return Nothing - */ -void POWER_CycleCpuAndFlash(void); - -/** - * @brief Configures and enters in DEEP-SLEEP low power mode - * @param exclude_from_pd: - * @param sram_retention_ctrl: - * @param wakeup_interrupts: - * @param hardware_wake_ctrl: - - * @return Nothing - * - * !!! IMPORTANT NOTES : - 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. - * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back - in case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). - * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function - will be restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full - chip reset) reset) - */ -void POWER_EnterDeepSleep(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t hardware_wake_ctrl); - -/** - * @brief Configures and enters in POWERDOWN low power mode - * @param exclude_from_pd: - * @param sram_retention_ctrl: - * @param wakeup_interrupts: - * @param cpu_retention_ctrl: 0 = CPU retention is disable / 1 = CPU retention is enabled, all other values are - RESERVED. - - * @return Nothing - * - * !!! IMPORTANT NOTES : - 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. - * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back - in case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). - * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function - will be restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance - containing the stack used to call this function WILL BE preserved during low power (via parameter - "sram_retention_ctrl") - * 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full - chip reset) reset) - */ - -void POWER_EnterPowerDown(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t cpu_retention_ctrl); - -/** - * @brief Configures and enters in DEEPPOWERDOWN low power mode - * @param exclude_from_pd: - * @param sram_retention_ctrl: - * @param wakeup_interrupts: - * @param wakeup_io_ctrl: - - * @return Nothing - * - * !!! IMPORTANT NOTES : - 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. - * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back - if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function - will be restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full - chip reset) - */ -void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t wakeup_io_ctrl); - -/** - * @brief Configures and enters in SLEEP low power mode - * - * @return Nothing - */ -void POWER_EnterSleep(void); - -/*! - * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency. - * - * @param system_freq_hz - The desired frequency (in Hertz) at which the part would like to operate, - * note that the voltage and flash wait states should be set before changing frequency - * @return none - */ -void POWER_SetVoltageForFreq(uint32_t system_freq_hz); - -/** - * @brief Sets board-specific trim values for 16MHz XTAL - * @param pi32_16MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 - * @param pi32_16MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes - * 600, 1.2pF becomes 120 - * @param pi32_16MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes - * 600, 1.2pF becomes 120 - * @return none - * @note Following default Values can be used: - * pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 - * pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20 - * pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 - */ -extern void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, - int32_t pi32_16MfXtalPPcbParCappF_x100, - int32_t pi32_16MfXtalNPcbParCappF_x100); -/** - * @brief Sets board-specific trim values for 32kHz XTAL - * @param pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 - * @param pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes - 600, 1.2pF becomes 120 - * @param pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes - 600, 1.2pF becomes 120 - - * @return none - * @note Following default Values can be used: - * pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 - * pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40 - * pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 - */ -extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, - int32_t pi32_32kfXtalPPcbParCappF_x100, - int32_t pi32_32kfXtalNPcbParCappF_x100); -/** - * @brief Enables and sets LDO for 16MHz XTAL - * @return none - */ -extern void POWER_SetXtal16mhzLdo(void); - -/** - * @brief Set up 16-MHz XTAL Trimmings - * @param amp Amplitude - * @param gm Transconductance - * @return none - */ -extern void POWER_SetXtal16mhzTrim(uint32_t amp, uint32_t gm); - -/** - * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes. - * @param p_reset_cause : the device reset cause, according to the definition of power_device_reset_cause_t - type. - * @param p_boot_mode : the device boot mode, according to the definition of power_device_boot_mode_t type. - * @param p_wakeupio_cause: the wake-up pin sources, according to the definition of register - PMC->WAKEIOCAUSE[3:0]. - - * @return Nothing - * - * !!! IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA !!! - * !!! valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06) !!! - * !!! when FALLING EDGE DETECTION is enabled on wake-up pins: !!! - * - 1. p_wakeupio_cause is NOT ACCURATE - * - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when - * several wake-up sources are enabled during DEEP-POWER-DOWN - * (like enabling wake-up on RTC and Falling edge wake-up pins) - * - */ -void POWER_GetWakeUpCause(power_device_reset_cause_t *p_reset_cause, - power_device_boot_mode_t *p_boot_mode, - uint32_t *p_wakeupio_cause); -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* _FSL_POWER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_prince.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_prince.c deleted file mode 100644 index 63e4c278528..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_prince.c +++ /dev/null @@ -1,1096 +0,0 @@ -/* - * Copyright 2018 - 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_prince.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ - -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.prince" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -static secure_bool_t PRINCE_CheckerAlgorithm(uint32_t address, - uint32_t length, - prince_flags_t flag, - flash_config_t *flash_context) -{ - uint32_t temp_base = 0, temp_sr = 0, region_index = 0, contiguous_start_index = 0, contiguous_end_index = 32; - secure_bool_t is_prince_region_contiguous = kSECURE_TRUE; - uint8_t prince_iv_code[FLASH_FFR_IV_CODE_SIZE] = {0}; - - if (address >= flash_context->ffrConfig.ffrBlockBase) - { - /* If it is not in flash region, return true to allow erase/write operation. */ - return kSECURE_TRUE; - } - - /* Iterate for all PRINCE regions */ - for (region_index = (uint32_t)kPRINCE_Region0; region_index <= (uint32_t)kPRINCE_Region2; region_index++) - { - contiguous_start_index = 0; - contiguous_end_index = 32; - switch (region_index) - { - case (uint32_t)kPRINCE_Region0: - temp_base = PRINCE->BASE_ADDR0; - temp_sr = PRINCE->SR_ENABLE0; - break; - - case (uint32_t)kPRINCE_Region1: - temp_base = PRINCE->BASE_ADDR1; - temp_sr = PRINCE->SR_ENABLE1; - break; - - case (uint32_t)kPRINCE_Region2: - temp_base = PRINCE->BASE_ADDR2; - temp_sr = PRINCE->SR_ENABLE2; - break; - - default: - /* All the cases have been listed above, the default clause should not be reached. */ - break; - } - - if (((address >= temp_base) && - ((address + length) < (temp_base + (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 32U * 1024U)))) && - (temp_sr != 0U)) - { - /* Check if the mask is contiguous */ - secure_bool_t first_set_bit_found = kSECURE_FALSE; - secure_bool_t contiguous_end_found = kSECURE_FALSE; - for (uint32_t i = 0; i < 32U; i++) - { - if (0U != (temp_sr & (1UL << i))) - { - if (kSECURE_FALSE == first_set_bit_found) - { - first_set_bit_found = kSECURE_TRUE; - contiguous_start_index = i; - } - if (kSECURE_TRUE == contiguous_end_found) - { - is_prince_region_contiguous = kSECURE_FALSE; - break; - } - } - else - { - if ((kSECURE_TRUE == first_set_bit_found) && (kSECURE_FALSE == contiguous_end_found)) - { - contiguous_end_found = kSECURE_TRUE; - contiguous_end_index = i; - } - } - } - } - else - { - continue; /* No encryption enabled, continue with the next region checking. */ - } - - /* Check if the provided memory range covers all addresses defined in the SR mask */ - if ((kSECURE_TRUE == is_prince_region_contiguous) && - ((address <= (temp_base + (contiguous_start_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U)))) && - (((address + length) >= - (temp_base + (contiguous_end_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U))))) - { - /* In case of erase operation, invalidate the old PRINCE IV by regenerating the new one */ - if (kPRINCE_Flag_EraseCheck == flag) - { - /* Re-generate the PRINCE IV in case of erase operation */ - - /* Generate new IV code for the PRINCE region and store the new IV into the respective FFRs */ - if (kStatus_Success == - PRINCE_GenNewIV((prince_region_t)region_index, &prince_iv_code[0], true, flash_context)) - { - /* Store the new IV for the PRINCE region into PRINCE registers. */ - if (kStatus_Success == PRINCE_LoadIV((prince_region_t)region_index, &prince_iv_code[0])) - { - /* Encryption is enabled, all subregions are to be erased/written at once, IV successfully - * regenerated, return true to allow erase operation. */ - return kSECURE_TRUE; - } - } - /* Encryption is enabled, all subregions are to be erased/written at once but IV has not been correctly - * regenerated, return false to disable erase operation. */ - return kSECURE_FALSE; - } - - /* Encryption is enabled and all subregions are to be erased/written at once, return true to allow - * erase/write operation. */ - return kSECURE_TRUE; - } - /* The provided memory range does not cover all addresses defined in the SR mask. */ - else - { - /* Is the provided memory range outside the addresses defined by the SR mask? */ - if ((kSECURE_TRUE == is_prince_region_contiguous) && - ((((address + length) <= - (temp_base + (contiguous_start_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U)))) || - ((address >= (temp_base + (contiguous_end_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U)))))) - { - /* No encryption enabled for the provided memory range, true could be returned to allow erase/write - operation, but due to the same base address for all three prince regions on Niobe4Mini we should - continue with other regions (SR mask) checking. */ - continue; - } - else - { - /* Encryption is enabled but not all subregions are to be erased/written at once, return false to - * disable erase/write operation. */ - return kSECURE_FALSE; - } - } - } - return kSECURE_TRUE; -} -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Generate new IV code. - * - * This function generates new IV code and stores it into the persistent memory. - * Ensure about 800 bytes free space on the stack when calling this routine with the store parameter set to true! - * - * @param region PRINCE region index. - * @param iv_code IV code pointer used for storing the newly generated 52 bytes long IV code. - * @param store flag to allow storing the newly generated IV code into the persistent memory (FFR). - * @param flash_context pointer to the flash driver context structure. - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise, kStatus_Fail is also returned if the key code for the particular - * PRINCE region is not present in the keystore (though new IV code has been provided) - */ -status_t PRINCE_GenNewIV(prince_region_t region, uint8_t *iv_code, bool store, flash_config_t *flash_context) -{ - status_t status = kStatus_Fail; - uint8_t prince_iv_code[FLASH_FFR_IV_CODE_SIZE] = {0}; - uint8_t tempBuffer[FLASH_FFR_MAX_PAGE_SIZE] = {0}; - - /* Make sure PUF is started to allow key and IV code decryption and generation */ - if (true != PUF_IsGetKeyAllowed(PUF)) - { - return status; - } - - /* Generate new IV code for the PRINCE region */ - status = - PUF_SetIntrinsicKey(PUF, (puf_key_index_register_t)(uint32_t)((uint32_t)kPUF_KeyIndex_02 + (uint32_t)region), 8, - &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); - if ((kStatus_Success == status) && (true == store)) - { - /* Store the new IV code for the PRINCE region into the respective FFRs. */ - /* Create a new version of "Customer Field Programmable" (CFP) page. */ - if ((int32_t)kStatus_FLASH_Success == - FFR_GetCustomerInfieldData(flash_context, (uint8_t *)tempBuffer, 0, FLASH_FFR_MAX_PAGE_SIZE)) - { - /* Set the IV code in the page */ - (void)memcpy(&tempBuffer[offsetof(cfpa_cfg_info_t, ivCodePrinceRegion) + - (((uint32_t)region * sizeof(cfpa_cfg_iv_code_t))) + 4U], - &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); - - uint32_t *p32 = (uint32_t *)(uint32_t)tempBuffer; - uint32_t version = p32[1]; - if (version == 0xFFFFFFFFu) - { - return kStatus_Fail; - } - version++; - p32[1] = version; - - /* Program the page and enable firewall for "Customer field area" */ - if ((int32_t)kStatus_FLASH_Success == - FFR_InfieldPageWrite(flash_context, (uint8_t *)tempBuffer, FLASH_FFR_MAX_PAGE_SIZE)) - { - status = kStatus_Success; - } - else - { - status = kStatus_Fail; - } - } - } - if (status == kStatus_Success) - { - /* Pass the new IV code */ - (void)memcpy(iv_code, &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); - } - - return status; -} -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Load IV code. - * - * This function enables IV code loading into the PRINCE bus encryption engine. - * - * @param region PRINCE region index. - * @param iv_code IV code pointer used for passing the IV code. - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise - */ -status_t PRINCE_LoadIV(prince_region_t region, uint8_t *iv_code) -{ - status_t status = kStatus_Fail; - uint32_t keyIndex = (0x0Fu & (uint32_t)iv_code[1]); - uint8_t prince_iv[8] = {0}; - - /* Make sure PUF is started to allow key and IV code decryption and generation */ - if (true != PUF_IsGetKeyAllowed(PUF)) - { - return kStatus_Fail; - } - - /* Check if region number matches the PUF index value */ - if (((uint32_t)kPUF_KeyIndex_02 + (uint32_t)region) == (uint32_t)keyIndex) - { - /* Decrypt the IV */ - if (kStatus_Success == PUF_GetKey(PUF, iv_code, FLASH_FFR_IV_CODE_SIZE, &prince_iv[0], 8)) - { - /* Store the new IV for the PRINCE region into PRINCE registers. */ - (void)PRINCE_SetRegionIV(PRINCE, (prince_region_t)region, prince_iv); - status = kStatus_Success; - } - } - - return status; -} -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Allow encryption/decryption for specified address range. - * - * This function sets the encryption/decryption for specified address range. - * The SR mask value for the selected Prince region is calculated from provided - * start_address and length parameters. This calculated value is OR'ed with the - * actual SR mask value and stored into the PRINCE SR_ENABLE register and also - * into the persistent memory (FFR) to be used after the device reset. It is - * possible to define several nonadjacent encrypted areas within one Prince - * region when calling this function repeatedly. If the length parameter is set - * to 0, the SR mask value is set to 0 and thus the encryption/decryption for - * the whole selected Prince region is disabled. - * Ensure about 800 bytes free space on the stack when calling this routine! - * - * @param region PRINCE region index. - * @param start_address start address of the area to be encrypted/decrypted. - * @param length length of the area to be encrypted/decrypted. - * @param flash_context pointer to the flash driver context structure. - * @param regenerate_iv flag to allow IV code regenerating, storing into - * the persistent memory (FFR) and loading into the PRINCE engine - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise - */ -status_t PRINCE_SetEncryptForAddressRange( - prince_region_t region, uint32_t start_address, uint32_t length, flash_config_t *flash_context, bool regenerate_iv) -{ - status_t status = kStatus_Fail; - uint32_t srEnableRegister = 0; - uint32_t alignedStartAddress; - uint32_t prince_base_addr_ffr_word = 0; - uint32_t end_address = start_address + length; - uint32_t prince_region_base_address = 0; - uint8_t tempBuffer[FLASH_FFR_MAX_PAGE_SIZE] = {0}; - - /* Check input parameters. */ - if (NULL == flash_context) - { - return kStatus_Fail; - } - - /* Check the address range, region borders crossing. */ -#if (defined(FSL_PRINCE_DRIVER_LPC55S0x)) || (defined(FSL_PRINCE_DRIVER_LPC55S1x)) || \ - (defined(FSL_PRINCE_DRIVER_LPC55S2x)) || (defined(FSL_PRINCE_DRIVER_LPC55S3x)) - if ((start_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) || - ((start_address < FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) && (end_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR))) - { - return kStatus_Fail; - } -#endif -#if (defined(FSL_PRINCE_DRIVER_LPC55S6x)) - if ((start_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) || - ((start_address < 0x40000U) && (end_address > 0x40000U)) || - ((start_address < 0x80000U) && (end_address > 0x80000U)) || - ((start_address < FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) && (end_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR))) - { - return kStatus_Fail; - } -#endif - - if (true == regenerate_iv) - { - uint8_t prince_iv_code[FLASH_FFR_IV_CODE_SIZE] = {0}; - - /* Generate new IV code for the PRINCE region and store the new IV into the respective FFRs */ - status = PRINCE_GenNewIV((prince_region_t)region, &prince_iv_code[0], true, flash_context); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - /* Store the new IV for the PRINCE region into PRINCE registers. */ - status = PRINCE_LoadIV((prince_region_t)region, &prince_iv_code[0]); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - } - - alignedStartAddress = ALIGN_DOWN(start_address, (int32_t)FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024); - - uint32_t subregion = alignedStartAddress / (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U); - if (subregion < (32U)) - { - /* PRINCE_Region0 */ - prince_region_base_address = 0; - } - else if (subregion < (64U)) - { - /* PRINCE_Region1 */ - subregion = subregion - 32U; - prince_region_base_address = 0x40000; - } - else - { - /* PRINCE_Region2 */ - subregion = subregion - 64U; - prince_region_base_address = 0x80000; - } - - /* If length > 0 then srEnableRegister mask is set based on the alignedStartAddress and the length. - If the length is 0, srEnableRegister should be kept 0 (no subregion enabled). */ - if (length != 0U) - { - srEnableRegister = (1UL << subregion); - alignedStartAddress += (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U); - - while (alignedStartAddress < (start_address + length)) - { - subregion++; - srEnableRegister |= (1UL << subregion); - alignedStartAddress += (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U); - } - - uint32_t srEnableRegisterActual = 0; - (void)PRINCE_GetRegionSREnable(PRINCE, (prince_region_t)region, &srEnableRegisterActual); - srEnableRegister |= srEnableRegisterActual; - } - - /* Store BASE_ADDR into PRINCE register before storing the SR to avoid en/decryption triggering - from addresses being defined by current BASE_ADDR register content (could be 0 and the decryption - of actually executed code can be started causing the hardfault then). */ - status = PRINCE_SetRegionBaseAddress(PRINCE, (prince_region_t)region, prince_region_base_address); - if (kStatus_Success != status) - { - return status; - } - - /* Store SR into PRINCE register */ - status = PRINCE_SetRegionSREnable(PRINCE, (prince_region_t)region, srEnableRegister); - if (kStatus_Success != status) - { - return status; - } - - /* Store SR and BASE_ADDR into CMPA FFR */ - if (kStatus_Success == FFR_GetCustomerData(flash_context, (uint8_t *)&tempBuffer, 0, FLASH_FFR_MAX_PAGE_SIZE)) - { - /* Set the PRINCE_SR_X in the page */ - (void)memcpy((uint32_t *)(uintptr_t)&tempBuffer[offsetof(cmpa_cfg_info_t, princeSr) + - ((uint32_t)region * sizeof(uint32_t))], - &srEnableRegister, sizeof(uint32_t)); - /* Set the ADDRX_PRG in the page */ - (void)memcpy(&prince_base_addr_ffr_word, - (const uint32_t *)(uintptr_t)&tempBuffer[offsetof(cmpa_cfg_info_t, princeBaseAddr)], - sizeof(uint32_t)); - prince_base_addr_ffr_word &= - ~(((uint32_t)FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) << ((uint32_t)region * 4U)); - prince_base_addr_ffr_word |= (((prince_region_base_address >> PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT) & - FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) - << ((uint32_t)region * 4U)); - (void)memcpy((uint32_t *)(uintptr_t)&tempBuffer[offsetof(cmpa_cfg_info_t, princeBaseAddr)], - &prince_base_addr_ffr_word, sizeof(uint32_t)); - - /* Program the CMPA page, set seal_part parameter to false (used during development to avoid sealing the - * part) - */ - status = FFR_CustFactoryPageWrite(flash_context, (uint8_t *)tempBuffer, false); - } - - return status; -} -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -/*! - * @brief Gets the PRINCE Sub-Region Enable register. - * - * This function gets PRINCE SR_ENABLE register. - * - * @param base PRINCE peripheral address. - * @param region PRINCE region index. - * @param sr_enable Sub-Region Enable register pointer. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_GetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t *sr_enable) -{ - status_t status = kStatus_Success; - - switch (region) - { - case kPRINCE_Region0: - *sr_enable = base->SR_ENABLE0; - break; - - case kPRINCE_Region1: - *sr_enable = base->SR_ENABLE1; - break; - - case kPRINCE_Region2: - *sr_enable = base->SR_ENABLE2; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - return status; -} - -/*! - * @brief Gets the PRINCE region base address register. - * - * This function gets PRINCE BASE_ADDR register. - * - * @param base PRINCE peripheral address. - * @param region PRINCE region index. - * @param region_base_addr Region base address pointer. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_GetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t *region_base_addr) -{ - status_t status = kStatus_Success; - - switch (region) - { - case kPRINCE_Region0: - *region_base_addr = base->BASE_ADDR0; - break; - - case kPRINCE_Region1: - *region_base_addr = base->BASE_ADDR1; - break; - - case kPRINCE_Region2: - *region_base_addr = base->BASE_ADDR2; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - return status; -} - -/*! - * @brief Sets the PRINCE region IV. - * - * This function sets specified AES IV for the given region. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param iv 64-bit AES IV in little-endian byte order. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_SetRegionIV(PRINCE_Type *base, prince_region_t region, const uint8_t iv[8]) -{ - status_t status = kStatus_Fail; - volatile uint32_t *IVMsb_reg = NULL; - volatile uint32_t *IVLsb_reg = NULL; - - switch (region) - { - case kPRINCE_Region0: - IVLsb_reg = &base->IV_LSB0; - IVMsb_reg = &base->IV_MSB0; - break; - - case kPRINCE_Region1: - IVLsb_reg = &base->IV_LSB1; - IVMsb_reg = &base->IV_MSB1; - break; - - case kPRINCE_Region2: - IVLsb_reg = &base->IV_LSB2; - IVMsb_reg = &base->IV_MSB2; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - if (status != kStatus_InvalidArgument) - { - *IVLsb_reg = ((uint32_t *)(uintptr_t)iv)[0]; - *IVMsb_reg = ((uint32_t *)(uintptr_t)iv)[1]; - status = kStatus_Success; - } - - return status; -} - -/*! - * @brief Sets the PRINCE region base address. - * - * This function configures PRINCE region base address. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param region_base_addr Base Address for region. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_SetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t region_base_addr) -{ - status_t status = kStatus_Success; - - /* Check input parameters. */ -#if (defined(FSL_PRINCE_DRIVER_LPC55S0x)) || (defined(FSL_PRINCE_DRIVER_LPC55S1x)) || \ - (defined(FSL_PRINCE_DRIVER_LPC55S2x)) || (defined(FSL_PRINCE_DRIVER_LPC55S3x)) - if (region_base_addr > 0U) - { - return kStatus_InvalidArgument; - } -#endif -#if (defined(FSL_PRINCE_DRIVER_LPC55S6x)) - if (region_base_addr > 0x80000U) - { - return kStatus_InvalidArgument; - } -#endif - - switch (region) - { - case kPRINCE_Region0: - base->BASE_ADDR0 = region_base_addr; - break; - - case kPRINCE_Region1: - base->BASE_ADDR1 = region_base_addr; - break; - - case kPRINCE_Region2: - base->BASE_ADDR2 = region_base_addr; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - return status; -} - -/*! - * @brief Sets the PRINCE Sub-Region Enable register. - * - * This function configures PRINCE SR_ENABLE register. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param sr_enable Sub-Region Enable register value. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_SetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t sr_enable) -{ - status_t status = kStatus_Success; - - switch (region) - { - case kPRINCE_Region0: - base->SR_ENABLE0 = sr_enable; - break; - - case kPRINCE_Region1: - base->SR_ENABLE1 = sr_enable; - break; - - case kPRINCE_Region2: - base->SR_ENABLE2 = sr_enable; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - return status; -} - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Erases the flash sectors encompassed by parameters passed into function. - * - * This function erases the appropriate number of flash sectors based on the - * desired start address and length. It deals with the flash erase function - * complenentary to the standard erase API of the IAP1 driver. This implementation - * additionally checks if the whole encrypted PRINCE subregions are erased at once - * to avoid secrets revealing. The checker implementation is limited to one contiguous - * PRINCE-controlled memory area. - * - * @param config The pointer to the flash driver context structure. - * @param start The start address of the desired flash memory to be erased. - * The start address needs to be prince-sburegion-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words) - * to be erased. Must be prince-sburegion-size-aligned. - * @param key The value used to validate all flash erase APIs. - * - * @return #kStatus_FLASH_Success API was executed successfully. - * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @return #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. - * @return #kStatus_FLASH_AddressError The address is out of range. - * @return #kStatus_FLASH_EraseKeyError The API erase key is invalid. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @return #kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce Encrypted flash subregions are not erased at once. - */ -status_t PRINCE_FlashEraseWithChecker(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) -{ - /* Check input parameters. */ - if (NULL == config) - { - return kStatus_Fail; - } - /* Check that the whole encrypted region is erased at once. */ - if (kSECURE_TRUE != PRINCE_CheckerAlgorithm(start, lengthInBytes, kPRINCE_Flag_EraseCheck, config)) - { - return (int32_t)kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce; - } - return FLASH_Erase(config, start, lengthInBytes, key); -} - -/*! - * @brief Programs flash with data at locations passed in through parameters. - * - * This function programs the flash memory with the desired data for a given - * flash area as determined by the start address and the length. It deals with the - * flash program function complenentary to the standard program API of the IAP1 driver. - * This implementation additionally checks if the whole PRINCE subregions are - * programmed at once to avoid secrets revealing. The checker implementation is limited - * to one contiguous PRINCE-controlled memory area. - * - * @param config The pointer to the flash driver context structure. - * @param start The start address of the desired flash memory to be programmed. Must be - * prince-sburegion-aligned. - * @param src A pointer to the source buffer of data that is to be programmed - * into the flash. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be programmed. Must be prince-sburegion-size-aligned. - * - * @return #kStatus_FLASH_Success API was executed successfully. - * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @return #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @return #kStatus_FLASH_AddressError Address is out of range. - * @return #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @return #kStatus_FLASH_SizeError Encrypted flash subregions are not programmed at once. - */ -status_t PRINCE_FlashProgramWithChecker(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) -{ - /* Check input parameters. */ - if (NULL == config) - { - return kStatus_Fail; - } - /* Check that the whole encrypted subregions will be writen at once. */ - if (kSECURE_TRUE != PRINCE_CheckerAlgorithm(start, lengthInBytes, kPRINCE_Flag_WriteCheck, config)) - { - return (int32_t)kStatus_FLASH_SizeError; - } - return FLASH_Program(config, start, src, lengthInBytes); -} -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if defined(FSL_PRINCE_DRIVER_LPC55S3x) -static status_t PRINCE_CSS_generate_random(uint8_t *output, size_t outputByteLen); -static status_t PRINCE_CSS_check_key(uint8_t keyIdx, mcuxClCss_KeyProp_t *pKeyProp); -static status_t PRINCE_CSS_gen_iv_key(void); -static status_t PRINCE_CSS_enable(void); -static status_t PRINCE_CSS_calculate_iv(uint32_t *IvReg); - -/*! - * @brief Configures PRINCE setting. - * - * This function does the initial PRINCE configuration via ROM IAP API call. - * PRINCE_SR_x configuration for each region configuration is stored into FFR (CMPA). - * PRINCE IV erase counters (MCTR_INT_IV_CTRx) in CFPA are updated accordingly. - * - * Note: This function is expected to be called once in the device lifetime, - * typically during the initial device provisioning, since it is programming the CMPA pages in PFR flash. - * - * @param coreCtx The pointer to the ROM API driver context structure. - * @param config The pointer to the PRINCE driver configuration structure. - * - * @retval #kStatus_Success - * @retval #kStatus_CommandUnsupported - * @retval #kStatus_InvalidArgument - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed - * @retval #kStatusMemoryRangeInvalid - * @retval #kStatus_Fail - * @retval #kStatus_OutOfRange - * @retval #kStatus_SPI_BaudrateNotSupport - */ -status_t PRINCE_Configure(api_core_context_t *coreCtx, prince_prot_region_arg_t *config) -{ - /* Enable CSS and check keys */ - if (kStatus_Success != PRINCE_CSS_enable()) - { - return kStatus_Fail; - } - - return MEM_Config(coreCtx, (uint32_t *)config, kMemoryInternal); -} - -/*! - * @brief Configures PRINCE setting. - * - * This function is used to re-configure PRINCE IP based on configuration stored in FFR. - * This function also needs to be called after wake up from power-down mode to regenerate IV - * encryption key in CSS key store whose presence is necessary for correct PRINCE operation - * during erase and write operations to encrypted regions of internal flash memory - * (dependency for correct operation of MEM_Erase() and MEM_Write() after wake up from power-down mode). - * - * @param coreCtx The pointer to the ROM API driver context structure. - * - * @retval #kStatus_Success - * @retval #kStatus_Fail - */ -status_t PRINCE_Reconfigure(api_core_context_t *coreCtx) -{ - status_t status = kStatus_Fail; - uint64_t princeMask; - uint32_t IvReg[4] = {0}; - uint32_t ivEraseCounter[3]; - uint32_t srEnable[3]; - uint32_t uuid[4]; - flash_config_t flash_config; - uint32_t lockWord; - uint8_t lock[3]; - - /* Enable CSS and check keys */ - status = PRINCE_CSS_enable(); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - /* Set PRINCE mask value. */ - status = PRINCE_CSS_generate_random((uint8_t *)&princeMask, sizeof(princeMask)); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - PRINCE_SetMask(PRINCE, princeMask); - - /* Clean up Flash driver structure and Init*/ - memset(&flash_config, 0, sizeof(flash_config_t)); - if (FLASH_Init(&flash_config) != kStatus_Success) - { - return kStatus_Fail; - } - - /* FFR Init */ - if (FFR_Init(&flash_config) != kStatus_Success) - { - return kStatus_Fail; - } - - /* Get UUID from FFR */ - status = FFR_GetUUID(&flash_config, (uint8_t *)uuid); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - /* Check version of CFPA scratch first */ - uint32_t cfpaScratchVer = 0u; - memcpy(&cfpaScratchVer, (void *)(CFPA_SCRATCH_VER), sizeof(uint32_t)); - - /* Get CFPA version using FFR ROM API */ - uint32_t cfpaVer = 0u; - if (kStatus_Success != - FFR_GetCustomerInfieldData(&flash_config, (uint8_t *)&cfpaVer, CFPA_VER_OFFSET, sizeof(uint32_t))) - { - status = kStatus_Fail; - return status; - } - - /* Compare the version of CFPA scratch and version of CFPA returned by ROM API */ - if (cfpaScratchVer > cfpaVer) - { - /* Get PRINCE_IV_CTRs from CFPA scratch */ - memcpy(&ivEraseCounter, (void *)CFPA_SCRATCH_IV, sizeof(uint32_t) * PRINCE_REGION_COUNT); - } - else - { - /* Get PRINCE_IV_CTRs IVs from CFPA ping/pong page */ - status = FFR_GetCustomerInfieldData(&flash_config, (uint8_t *)ivEraseCounter, CFPA_PRINCE_IV_OFFSET, - sizeof(uint32_t) * PRINCE_REGION_COUNT); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - } - - /* Get PRINCE sub-region enable word from FFR */ - status = FFR_GetCustomerData(&flash_config, (uint8_t *)srEnable, CMPA_PRINCE_SR_OFFSET, - sizeof(uint32_t) * PRINCE_REGION_COUNT); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - /* Get PRINCE lock setting from FFR */ - status = FFR_GetCustomerData(&flash_config, (uint8_t *)&lockWord, CMPA_PRINCE_LOCK_OFFSET, sizeof(uint32_t)); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - lock[0] = (lockWord & PRINCE_BASE_ADDR_LOCK_REG0_MASK) >> PRINCE_BASE_ADDR_LOCK_REG0_SHIFT; - lock[1] = (lockWord & PRINCE_BASE_ADDR_LOCK_REG1_MASK) >> PRINCE_BASE_ADDR_LOCK_REG1_SHIFT; - lock[2] = (lockWord & PRINCE_BASE_ADDR_LOCK_REG2_MASK) >> PRINCE_BASE_ADDR_LOCK_REG2_SHIFT; - - /* Iterate for all internal PRINCE regions */ - for (prince_region_t region = kPRINCE_Region0; region <= kPRINCE_Region2; region++) - { - /* Set region base address. Should be always 0x0 on LPC55S36 */ - status = PRINCE_SetRegionBaseAddress(PRINCE, (prince_region_t)region, 0x0u); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - status = PRINCE_SetRegionSREnable(PRINCE, region, srEnable[region]); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - /* Prepare ivSeed for current region */ - IvReg[0] = uuid[0]; - IvReg[1] = uuid[1]; - IvReg[2] = uuid[2] ^ region; - IvReg[3] = ivEraseCounter[region]; - - /* Calculate IV as IvReg = AES_ECB_ENC(DUK_derived_key, {ctx_erase_counter, ctx_id}) */ - status = PRINCE_CSS_calculate_iv(IvReg); - if (status != kStatus_Success) - { - return kStatus_Fail; - } - - /* Load IV into PRINCE registers */ - status = PRINCE_SetRegionIV(PRINCE, (prince_region_t)region, (uint8_t *)IvReg); - if (status != kStatus_Success) - { - return kStatus_Fail; - } - - /* Lock region if required */ - if ((lock[region] == 0x1u) || (lock[region] == 0x2u) || (lock[region] == 0x3u)) - { - PRINCE_SetLock(PRINCE, (kPRINCE_Region0Lock << region)); - } - } - - /* Break the main loop in case that error occured during PRINCE configuration */ - if (status != kStatus_Success) - { - return kStatus_Fail; - } - - /* When ENC_ENABLE is set, reading from PRINCE-encrypted regions is disabled. */ - /* For LPC55S36, the ENC_ENABLE is self-cleared after programming memory. */ - PRINCE_EncryptDisable(PRINCE); - return status; -} - -static status_t PRINCE_CSS_generate_random(uint8_t *output, size_t outputByteLen) -{ - status_t status = kStatus_Fail; - - // PRNG needs to be initialized; this can be done by calling mcuxClCss_KeyDelete_Async - // (delete any key slot, can be empty) - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_KeyDelete_Async(18)); - // mcuxClCss_KeyDelete_Async is a flow-protected function: Check the protection token and the return value - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_KeyDelete_Async) != token) || (MCUXCLCSS_STATUS_OK_WAIT != result)) - return kStatus_Fail; // Expect that no error occurred, meaning that the mcuxClCss_KeyDelete_Async operation was - // started. - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - // Wait for operation to finish - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_WaitForOperation(MCUXCLCSS_ERROR_FLAGS_CLEAR)); - // mcuxClCss_WaitForOperation is a flow-protected function: Check the protection token and the return value - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_WaitForOperation) != token) || (MCUXCLCSS_STATUS_OK != result)) - return kStatus_Fail; // Expect that no error occurred, meaning that the mcuxClCss_WaitForOperation operation was - // started. - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_Prng_GetRandom(output, outputByteLen)); - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_Prng_GetRandom) != token) || (MCUXCLCSS_STATUS_OK != result)) - return kStatus_Fail; - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - status = kStatus_Success; - return status; -} - -static status_t PRINCE_CSS_check_key(uint8_t keyIdx, mcuxClCss_KeyProp_t *pKeyProp) -{ - /* Check if CSS required keys are available in CSS keystore */ - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, - mcuxClCss_GetKeyProperties(keyIdx, pKeyProp)); // Get key propertis from the CSS. - // mcuxClCss_GetKeyProperties is a flow-protected function: Check the protection token and the return value - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_GetKeyProperties) != token) || (MCUXCLCSS_STATUS_OK != result)) - return kStatus_Fail; - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - return kStatus_Success; -} - -static status_t PRINCE_CSS_gen_iv_key(void) -{ - /* The NXP_DIE_MEM_IV_ENC_SK is not loaded and needs to be regenerated (power-down wakeup) */ - /* Set KDF mask and key properties for NXP_DIE_MEM_IV_ENC_SK */ - SYSCON->CSS_KDF_MASK = SYSCON_CSS_KDF_MASK; - static const uint32_t ddata2[3] = {0x62032504, 0x72f04280, 0x87a2bbae}; - mcuxClCss_KeyProp_t keyProp; - /* Set key properties in structure */ - keyProp.word.value = CSS_CSS_KS2_ks2_uaes_MASK | CSS_CSS_KS2_ks2_fgp_MASK | CSS_CSS_KS2_ks2_kact_MASK; - status_t status = kStatus_Fail; - - /* Generate the key using CKDF */ - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN( - result, token, - mcuxClCss_Ckdf_Sp800108_Async((mcuxClCss_KeyIndex_t)0, (mcuxClCss_KeyIndex_t)NXP_DIE_MEM_IV_ENC_SK, keyProp, - (uint8_t const *)ddata2)); - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_Ckdf_Sp800108_Async) != token) && (MCUXCLCSS_STATUS_OK != result)) - { - return kStatus_Fail; - } - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - /* Wait for CKDF to finish */ - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_WaitForOperation(MCUXCLCSS_ERROR_FLAGS_CLEAR)); - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_WaitForOperation) == token) && (MCUXCLCSS_STATUS_OK == result)) - { - status = kStatus_Success; - } - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - return status; -} - -static status_t PRINCE_CSS_enable(void) -{ - mcuxClCss_KeyProp_t key_properties; - status_t status = kStatus_Fail; - - /* Enable CSS and related clocks */ - status = CSS_PowerDownWakeupInit(CSS); - if (status != kStatus_Success) - { - return kStatus_Fail; - } - - /* Check if MEM_ENC_SK key is available in CSS keystore */ - status = PRINCE_CSS_check_key(NXP_DIE_MEM_ENC_SK, &key_properties); - if (status != kStatus_Success || key_properties.bits.kactv != 1u) - { - return kStatus_Fail; - } - - /* Check if MEM_IV_ENC_SK key is available in CSS keystore */ - status = PRINCE_CSS_check_key(NXP_DIE_MEM_IV_ENC_SK, &key_properties); - if (status != kStatus_Success || key_properties.bits.kactv != 1u) - { - return PRINCE_CSS_gen_iv_key(); - } - - return kStatus_Success; -} - -static status_t PRINCE_CSS_calculate_iv(uint32_t *IvReg) -{ - mcuxClCss_CipherOption_t cipherOptions = {0}; - status_t status = kStatus_Fail; - - /* Configure CSS for AES ECB-128, using NXP_DIE_MEM_IV_ENC_SK key */ - cipherOptions.bits.cphmde = MCUXCLCSS_CIPHERPARAM_ALGORITHM_AES_ECB; - cipherOptions.bits.dcrpt = MCUXCLCSS_CIPHER_ENCRYPT; - cipherOptions.bits.extkey = MCUXCLCSS_CIPHER_INTERNAL_KEY; - - do - { - /* Calculate IV as IvReg = AES_ECB_ENC(NXP_DIE_MEM_IV_ENC_SK, ivSeed[127:0]) */ - /* ivSeed[127:0] = {UUID[96:0] ^ regionNumber[1:0], ivEraseCounter[31:0]} */ - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN( - result, token, - mcuxClCss_Cipher_Async(cipherOptions, (mcuxClCss_KeyIndex_t)NXP_DIE_MEM_IV_ENC_SK, NULL, - MCUXCLCSS_CIPHER_KEY_SIZE_AES_128, (uint8_t *)IvReg, MCUXCLCSS_CIPHER_BLOCK_SIZE_AES, - NULL, (uint8_t *)IvReg)); - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_Cipher_Async) != token) || (MCUXCLCSS_STATUS_OK_WAIT != result)) - break; - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN( - result, token, - mcuxClCss_WaitForOperation( - MCUXCLCSS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClCss_Enable_Async operation to complete. - // mcuxClCss_WaitForOperation is a flow-protected function: Check the protection token and the return value - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_WaitForOperation) == token) && (MCUXCLCSS_STATUS_OK == result)) - { - status = kStatus_Success; - } - MCUX_CSSL_FP_FUNCTION_CALL_END(); - } while (0); - - return status; -} -#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_prince.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_prince.h deleted file mode 100644 index 1d702ae499b..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_prince.h +++ /dev/null @@ -1,522 +0,0 @@ -/* - * Copyright 2018 - 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_PRINCE_H_ -#define _FSL_PRINCE_H_ - -#include "fsl_common.h" - -#include FFR_INCLUDE - -/*! - * @addtogroup prince - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief PRINCE driver version 2.5.0. - * - * Current version: 2.5.0 - * - * Change log: - * - Version 2.0.0 - * - Initial version. - * - Version 2.1.0 - * - Update for the A1 rev. of LPC55Sxx serie. - * - Version 2.2.0 - * - Add runtime checking of the A0 and A1 rev. of LPC55Sxx serie to support - * both silicone revisions. - * - Version 2.3.0 - * - Add support for LPC55S1x and LPC55S2x series - * - Version 2.3.0 - * - Fix MISRA-2012 issues. - * - Version 2.3.1 - * - Add support for LPC55S0x series - * - Version 2.3.2 - * - Fix documentation of enumeration. Extend PRINCE example. - * - Version 2.4.0 - * - Add support for LPC55S3x series - * - Version 2.5.0 - * - Add PRINCE_Config() and PRINCE_Reconfig() features. - */ -#define FSL_PRINCE_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) -/*@}*/ - -#if (defined(LPC55S04_SERIES) || defined(LPC55S06_SERIES)) -/* LPC55S0x series*/ -#define FSL_PRINCE_DRIVER_LPC55S0x -#include "fsl_puf.h" - -#elif (defined(LPC55S14_SERIES) || defined(LPC55S16_SERIES)) -/* LPC55S1x series*/ -#define FSL_PRINCE_DRIVER_LPC55S1x -#include "fsl_puf.h" - -#elif (defined(LPC55S26_SERIES) || defined(LPC55S28_SERIES)) -/* LPC55S2x series*/ -#define FSL_PRINCE_DRIVER_LPC55S2x -#include "fsl_puf.h" - -#elif (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || \ - defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES)) -/* LPC55S6x series*/ -#define FSL_PRINCE_DRIVER_LPC55S6x -#include "fsl_puf.h" - -#elif (defined(LPC55S36_SERIES)) -/* LPC55S3x series*/ -#define FSL_PRINCE_DRIVER_LPC55S3x -#define PRINCE PRINCE0 -#include "fsl_mem_interface.h" -#include "fsl_css.h" // Power Down Wake-up Init -#include // Interface to the entire nxpClCss component -#include // Code flow protection -#else -#error "No valid CPU defined!" -#endif - -#define FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB (8U) -#define FSL_PRINCE_DRIVER_MAX_FLASH_ADDR \ - ((uint32_t)FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES - (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 2U * 1024U)) - -#if !defined(ALIGN_DOWN) -#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) -#endif - -/*! @brief Secure status enumeration. */ -typedef enum _skboot_status -{ - kStatus_SKBOOT_Success = 0x5ac3c35au, /*!< PRINCE Success */ - kStatus_SKBOOT_Fail = 0xc35ac35au, /*!< PRINCE Fail */ - kStatus_SKBOOT_InvalidArgument = 0xc35a5ac3u, /*!< PRINCE Invalid argument */ - kStatus_SKBOOT_KeyStoreMarkerInvalid = 0xc3c35a5au, /*!< PRINCE Invalid marker */ -} skboot_status_t; - -/*! @brief Secure boolean enumeration. */ -typedef enum _secure_bool -{ - kSECURE_TRUE = 0xc33cc33cU, /*!< PRINCE true */ - kSECURE_FALSE = 0x5aa55aa5U, /*!< PRINCE false */ -} secure_bool_t; - -/*! @brief Prince region. */ -typedef enum _prince_region -{ - kPRINCE_Region0 = 0U, /*!< PRINCE region 0 */ - kPRINCE_Region1 = 1U, /*!< PRINCE region 1 */ - kPRINCE_Region2 = 2U, /*!< PRINCE region 2 */ -} prince_region_t; - -/*! @brief Prince lock. */ -typedef enum _prince_lock -{ - kPRINCE_Region0Lock = 1U, /*!< PRINCE region 0 lock */ - kPRINCE_Region1Lock = 2U, /*!< PRINCE region 1 lock */ - kPRINCE_Region2Lock = 4U, /*!< PRINCE region 2 lock */ - kPRINCE_MaskLock = 256U, /*!< PRINCE mask register lock */ -} prince_lock_t; - -/*! @brief Prince flag. */ -typedef enum _prince_flags -{ - kPRINCE_Flag_None = 0U, /*!< PRINCE Flag None */ - kPRINCE_Flag_EraseCheck = 1U, /*!< PRINCE Flag Erase check */ - kPRINCE_Flag_WriteCheck = 2U, /*!< PRINCE Flag Write check */ -} prince_flags_t; - -#if defined(FSL_PRINCE_DRIVER_LPC55S3x) -typedef struct -{ - uint32_t target_prince_region : 2; // 0/1/2 - uint32_t reserved : 22; - uint32_t tag : 8; // Fixed to 0x50 ('P') -} prince_prot_region_option_t; -typedef struct -{ - prince_prot_region_option_t option; - uint32_t start; - uint32_t length; -} prince_prot_region_arg_t; - -/*! @brief Prince fixed tag in prince_prot_region_option_t structure */ -#define PRINCE_TAG 0x50u -#define PRINCE_TAG_SHIFT 24u -/*! @brief Prince region count */ -#define PRINCE_REGION_COUNT 3u -/*! @brief Define for CSS key store indexes */ -#define NXP_DIE_MEM_ENC_SK 2u -#define NXP_DIE_MEM_IV_ENC_SK 4u -/*! @brief KDF mask and key properties for NXP_DIE_MEM_IV_ENC_SK (see SYSCON documentation)*/ -#define SYSCON_CSS_KDF_MASK 0x07000FCF -/*! @brief CFPA version and IV indexes (see Protected Flash Region table) */ -#define CFPA_VER_OFFSET 0x04 -#define CFPA_PRINCE_IV_OFFSET 0x14u -/*! @brief CMPA SR and lock indexes (see Protected Flash Region table) */ -#define CMPA_PRINCE_SR_OFFSET 0x24u -#define CMPA_PRINCE_LOCK_OFFSET 0x20u -/*! @brief CFPA scrach version and IV addresses (see Protected Flash Region table) */ -#define CFPA_SCRATCH_VER 0x3dc04 -#define CFPA_SCRATCH_IV 0x3dc14 -/*! @brief CMPA lock bit-field defines (see Protected Flash Region table) */ -#define PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (16u) -#define PRINCE_BASE_ADDR_LOCK_REG0_MASK (0x3u << PRINCE_BASE_ADDR_LOCK_REG0_SHIFT) -#define PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (18u) -#define PRINCE_BASE_ADDR_LOCK_REG1_MASK (0x3u << PRINCE_BASE_ADDR_LOCK_REG1_SHIFT) -#define PRINCE_BASE_ADDR_LOCK_REG2_SHIFT (20u) -#define PRINCE_BASE_ADDR_LOCK_REG2_MASK (0x3u << PRINCE_BASE_ADDR_LOCK_REG2_SHIFT) - -#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Enable data encryption. - * - * This function enables PRINCE on-the-fly data encryption. - * - * @param base PRINCE peripheral address. - */ -static inline void PRINCE_EncryptEnable(PRINCE_Type *base) -{ - base->ENC_ENABLE = 1u; -} - -/*! - * @brief Disable data encryption. - * - * This function disables PRINCE on-the-fly data encryption. - * - * @param base PRINCE peripheral address. - */ -static inline void PRINCE_EncryptDisable(PRINCE_Type *base) -{ - base->ENC_ENABLE = 0u; -} - -/*! - * @brief Is Enable data encryption. - * - * This function test if PRINCE on-the-fly data encryption is enabled. - * - * @param base PRINCE peripheral address. - * @return true if enabled, false if not - */ -static inline bool PRINCE_IsEncryptEnable(PRINCE_Type *base) -{ - return (base->ENC_ENABLE == 1u) ? true : false; -} - -/*! - * @brief Sets PRINCE data mask. - * - * This function sets the PRINCE mask that is used to mask decrypted data. - * - * @param base PRINCE peripheral address. - * @param mask 64-bit data mask value. - */ -static inline void PRINCE_SetMask(PRINCE_Type *base, uint64_t mask) -{ - base->MASK_LSB = (uint32_t)(mask & 0xffffffffu); - base->MASK_MSB = (uint32_t)(mask >> 32u); -} - -/*! - * @brief Locks access for specified region registers or data mask register. - * - * This function sets lock on specified region registers or mask register. - * - * @param base PRINCE peripheral address. - * @param lock registers to lock. This is a logical OR of members of the - * enumeration ::prince_lock_t - */ -static inline void PRINCE_SetLock(PRINCE_Type *base, uint32_t lock) -{ - base->LOCK = lock & 0x1ffu; -} - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Generate new IV code. - * - * This function generates new IV code and stores it into the persistent memory. - * Ensure about 800 bytes free space on the stack when calling this routine with the store parameter set to true! - * - * @param region PRINCE region index. - * @param iv_code IV code pointer used for storing the newly generated 52 bytes long IV code. - * @param store flag to allow storing the newly generated IV code into the persistent memory (FFR). - * @param flash_context pointer to the flash driver context structure. - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise, kStatus_Fail is also returned if the key code for the particular - * PRINCE region is not present in the keystore (though new IV code has been provided) - */ -status_t PRINCE_GenNewIV(prince_region_t region, uint8_t *iv_code, bool store, flash_config_t *flash_context); -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Load IV code. - * - * This function enables IV code loading into the PRINCE bus encryption engine. - * - * @param region PRINCE region index. - * @param iv_code IV code pointer used for passing the IV code. - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise - */ -status_t PRINCE_LoadIV(prince_region_t region, uint8_t *iv_code); -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Allow encryption/decryption for specified address range. - * - * This function sets the encryption/decryption for specified address range. - * The SR mask value for the selected Prince region is calculated from provided - * start_address and length parameters. This calculated value is OR'ed with the - * actual SR mask value and stored into the PRINCE SR_ENABLE register and also - * into the persistent memory (FFR) to be used after the device reset. It is - * possible to define several nonadjacent encrypted areas within one Prince - * region when calling this function repeatedly. If the length parameter is set - * to 0, the SR mask value is set to 0 and thus the encryption/decryption for - * the whole selected Prince region is disabled. - * Ensure about 800 bytes free space on the stack when calling this routine! - * - * @param region PRINCE region index. - * @param start_address start address of the area to be encrypted/decrypted. - * @param length length of the area to be encrypted/decrypted. - * @param flash_context pointer to the flash driver context structure. - * @param regenerate_iv flag to allow IV code regenerating, storing into - * the persistent memory (FFR) and loading into the PRINCE engine - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise - */ -status_t PRINCE_SetEncryptForAddressRange( - prince_region_t region, uint32_t start_address, uint32_t length, flash_config_t *flash_context, bool regenerate_iv); -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -/*! - * @brief Gets the PRINCE Sub-Region Enable register. - * - * This function gets PRINCE SR_ENABLE register. - * - * @param base PRINCE peripheral address. - * @param region PRINCE region index. - * @param sr_enable Sub-Region Enable register pointer. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_GetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t *sr_enable); - -/*! - * @brief Gets the PRINCE region base address register. - * - * This function gets PRINCE BASE_ADDR register. - * - * @param base PRINCE peripheral address. - * @param region PRINCE region index. - * @param region_base_addr Region base address pointer. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_GetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t *region_base_addr); - -/*! - * @brief Sets the PRINCE region IV. - * - * This function sets specified AES IV for the given region. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param iv 64-bit AES IV in little-endian byte order. - */ -status_t PRINCE_SetRegionIV(PRINCE_Type *base, prince_region_t region, const uint8_t iv[8]); - -/*! - * @brief Sets the PRINCE region base address. - * - * This function configures PRINCE region base address. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param region_base_addr Base Address for region. - */ -status_t PRINCE_SetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t region_base_addr); - -/*! - * @brief Sets the PRINCE Sub-Region Enable register. - * - * This function configures PRINCE SR_ENABLE register. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param sr_enable Sub-Region Enable register value. - */ -status_t PRINCE_SetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t sr_enable); - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Erases the flash sectors encompassed by parameters passed into function. - * - * This function erases the appropriate number of flash sectors based on the - * desired start address and length. It deals with the flash erase function - * complenentary to the standard erase API of the IAP1 driver. This implementation - * additionally checks if the whole encrypted PRINCE subregions are erased at once - * to avoid secrets revealing. The checker implementation is limited to one contiguous - * PRINCE-controlled memory area. - * - * @param config The pointer to the flash driver context structure. - * @param start The start address of the desired flash memory to be erased. - * The start address needs to be prince-sburegion-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words) - * to be erased. Must be prince-sburegion-size-aligned. - * @param key The value used to validate all flash erase APIs. - * - * @return #kStatus_FLASH_Success API was executed successfully. - * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @return #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. - * @return #kStatus_FLASH_AddressError The address is out of range. - * @return #kStatus_FLASH_EraseKeyError The API erase key is invalid. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @return #kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce Encrypted flash subregions are not erased at once. - */ -status_t PRINCE_FlashEraseWithChecker(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Programs flash with data at locations passed in through parameters. - * - * This function programs the flash memory with the desired data for a given - * flash area as determined by the start address and the length. It deals with the - * flash program function complenentary to the standard program API of the IAP1 driver. - * This implementation additionally checks if the whole PRINCE subregions are - * programmed at once to avoid secrets revealing. The checker implementation is limited - * to one contiguous PRINCE-controlled memory area. - * - * @param config The pointer to the flash driver context structure. - * @param start The start address of the desired flash memory to be programmed. Must be - * prince-sburegion-aligned. - * @param src A pointer to the source buffer of data that is to be programmed - * into the flash. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be programmed. Must be prince-sburegion-size-aligned. - * - * @return #kStatus_FLASH_Success API was executed successfully. - * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @return #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @return #kStatus_FLASH_AddressError Address is out of range. - * @return #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @return #kStatus_FLASH_SizeError Encrypted flash subregions are not programmed at once. - */ -status_t PRINCE_FlashProgramWithChecker(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Configures PRINCE setting. - * - * This function does the initial PRINCE configuration via ROM IAP API call. - * PRINCE_SR_x configuration for each region configuration is stored into FFR (CMPA). - * PRINCE IV erase counters (MCTR_INT_IV_CTRx) in CFPA are updated accordingly. - * - * Note: This function is expected to be called once in the device lifetime, - * typically during the initial device provisioning, since it is programming the CMPA pages in PFR flash. - * - * @param coreCtx The pointer to the ROM API driver context structure. - * @param config The pointer to the PRINCE driver configuration structure. - * - * @retval #kStatus_Success - * @retval #kStatus_CommandUnsupported - * @retval #kStatus_InvalidArgument - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed - * @retval #kStatusMemoryRangeInvalid - * @retval #kStatus_Fail - * @retval #kStatus_OutOfRange - * @retval #kStatus_SPI_BaudrateNotSupport - */ -status_t PRINCE_Configure(api_core_context_t *coreCtx, prince_prot_region_arg_t *config); -#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Reconfigures PRINCE setting. - * - * This function is used to re-configure PRINCE IP based on configuration stored in FFR. - * This function also needs to be called after wake up from power-down mode to regenerate IV - * encryption key in CSS key store whose presence is necessary for correct PRINCE operation - * during erase and write operations to encrypted regions of internal flash memory - * (dependency for correct operation of MEM_Erase() and MEM_Write() after wake up from power-down mode). - * - * @param coreCtx The pointer to the ROM API driver context structure. - * - * @retval #kStatus_Success - * @retval #kStatus_CommandUnsupported - * @retval #kStatus_InvalidArgument - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed - * @retval #kStatusMemoryRangeInvalid - * @retval #kStatus_Fail - * @retval #kStatus_OutOfRange - * @retval #kStatus_SPI_BaudrateNotSupport - */ -status_t PRINCE_Reconfigure(api_core_context_t *coreCtx); -#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if (defined(FSL_PRINCE_DRIVER_LPC55S0x)) || defined(FSL_PRINCE_DRIVER_LPC55S1x) || defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Gets the PRINCE Error status register. - * - * @param base PRINCE peripheral address. - * - * @return PRINCE Error status register - */ -static inline uint32_t PRINCE_GetErrorStatus(PRINCE_Type *base) -{ - return base->ERR; -} - -/*! - * @brief Clears the PRINCE Error status register. - * - * @param base PRINCE peripheral address. - */ -static inline void PRINCE_ClearErrorStatus(PRINCE_Type *base) -{ - base->ERR = 0U; -} -#endif /* defined(FSL_PRINCE_DRIVER_LPC55S0x) || defined(FSL_PRINCE_DRIVER_LPC55S1x) || \ - defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_PRINCE_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_puf.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_puf.c deleted file mode 100644 index d82299ed243..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_puf.c +++ /dev/null @@ -1,949 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_puf.h" -#include "fsl_clock.h" -#include "fsl_common.h" - -#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) -#include "fsl_reset.h" -#endif /* FSL_FEATURE_PUF_HAS_NO_RESET */ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.puf" -#endif - -/* RT6xx POWER CONTROL bit masks */ -#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) -#define PUF_PWRCTRL_CKDIS_MASK (0x4U) -#define PUF_PWRCTRL_RAMINIT_MASK (0x8U) -#define PUF_PWRCTRL_RAMPSWLARGEMA_MASK (0x10U) -#define PUF_PWRCTRL_RAMPSWLARGEMP_MASK (0x20U) -#define PUF_PWRCTRL_RAMPSWSMALLMA_MASK (0x40U) -#define PUF_PWRCTRL_RAMPSWSMALLMP_MASK (0x80U) -#endif - -#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) -#define DEFAULT_CKGATING 0x0u -#define PUF_ENABLE_MASK 0xFFFFFFFEu -#define PUF_ENABLE_CTRL 0x1u - -#else -static void puf_wait_usec(volatile uint32_t usec, uint32_t coreClockFrequencyMHz) -{ - SDK_DelayAtLeastUs(usec, coreClockFrequencyMHz * 1000000U); - - /* Instead of calling SDK_DelayAtLeastUs() implement delay loop here */ - // while (usec > 0U) - // { - // usec--; - - // number of MHz is directly number of core clocks to wait 1 usec. - // the while loop below is actually 4 clocks so divide by 4 for ~1 usec - // volatile uint32_t ticksCount = coreClockFrequencyMHz / 4u + 1u; - // while (0U != ticksCount--) - // { - // } - // } -} -#endif /* defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) */ - -static status_t puf_waitForInit(PUF_Type *base) -{ - status_t status = kStatus_Fail; - - /* wait until status register reads non-zero. All zero is not valid. It should be BUSY or OK or ERROR */ - while (0U == base->STAT) - { - } - - /* wait if busy */ - while ((base->STAT & PUF_STAT_BUSY_MASK) != 0U) - { - } - - /* return status */ - if (0U != (base->STAT & (PUF_STAT_SUCCESS_MASK | PUF_STAT_ERROR_MASK))) - { - status = kStatus_Success; - } - - return status; -} - -static void puf_powerOn(PUF_Type *base, puf_config_t *conf) -{ -#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) - /* RT6xxs */ - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK); - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_RAMINIT_MASK); -#elif defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* LPCXpresso55s16 */ - conf->puf_sram_base->CFG |= PUF_ENABLE_CTRL; - while (0U == (PUF_SRAM_CTRL_STATUS_READY_MASK & conf->puf_sram_base->STATUS)) - { - } -#else /* !FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ - /* LPCXpresso55s69 & LPCXpresso54S018 */ - base->PWRCTRL = PUF_PWRCTRL_RAMON_MASK; - while (0U == (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL)) - { - } -#endif /* FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ -} -/*! - * brief Powercycle PUF - * - * This function make powercycle of PUF. - * - * param base PUF peripheral base address - * param conf PUF configuration structure - * return Status of the powercycle operation. - */ -status_t PUF_PowerCycle(PUF_Type *base, puf_config_t *conf) -{ -#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) - /* RT6xxs */ - uint32_t coreClockFrequencyMHz = conf->coreClockFrequencyHz / 1000000u; - - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* disable RAM CK */ - - /* enter ASPS mode */ - base->PWRCTRL = (PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* SLEEP = 1 */ - base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK); /* enable RAM CK */ - base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | PUF_PWRCTRL_RAMPSWLARGEMP_MASK | - PUF_PWRCTRL_RAMPSWSMALLMA_MASK | PUF_PWRCTRL_RAMPSWSMALLMP_MASK); /* SLEEP=1, PSW*=1 */ - - /* Wait enough time to discharge fully */ - puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); - - /* write PWRCTRL=0x38. wait time > 1 us */ - base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | - PUF_PWRCTRL_RAMPSWLARGEMP_MASK); /* SLEEP=1. PSWSMALL*=0. PSWLARGE*=1. */ - puf_wait_usec(1, coreClockFrequencyMHz); - - /* write PWRCTRL=0x8. wait time > 1 us */ - base->PWRCTRL = PUF_PWRCTRL_RAMINIT_MASK; /* SLEEP=1. PSWSMALL*=0. PSWLARGE*=0 */ - puf_wait_usec(1, coreClockFrequencyMHz); - - base->PWRCTRL = (PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_RAMINIT_MASK); - - /* Generate INITN low pulse */ - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK); - base->PWRCTRL = PUF_PWRCTRL_RAM_ON_MASK; -#elif defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* LPCXpresso55s16 */ - conf->puf_sram_base->CFG &= PUF_ENABLE_MASK; -#else - /* LPCXpresso55s69 & LPCXpresso54S018 */ - base->PWRCTRL = 0x0u; - while (0U != (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL)) - { - } - - /* Wait enough time to discharge fully */ - puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); -#endif - -#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) - /* Reset PUF and reenable power to PUF SRAM */ - RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); -#endif /* FSL_TEATURE_PUF_HAS_NO_RESET */ - puf_powerOn(base, conf); - - return kStatus_Success; -} - -/*! - * brief Sets the default configuration of PUF - * - * This function initialize PUF config structure to default values. - * - * param conf PUF configuration structure - */ -void PUF_GetDefaultConfig(puf_config_t *conf) -{ -#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* LPCXpresso55s16 */ - conf->puf_sram_base = PUF_SRAM_CTRL; - - /* Default configuration after reset */ - conf->CKGATING = DEFAULT_CKGATING; /* PUF SRAM Clock Gating */ -#endif /* FSL_FEATURE_PUF_HAS_SRAM_CTRL */ - - conf->dischargeTimeMsec = KEYSTORE_PUF_DISCHARGE_TIME_FIRST_TRY_MS; - conf->coreClockFrequencyHz = CLOCK_GetFreq(kCLOCK_CoreSysClk); - - return; -} - -/*! - * brief Initialize PUF - * - * This function enables power to PUF block and waits until the block initializes. - * - * param base PUF peripheral base address - * param conf PUF configuration structure - * return Status of the init operation - */ -status_t PUF_Init(PUF_Type *base, puf_config_t *conf) -{ - status_t status = kStatus_Fail; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Puf); -#endif -#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) - /* Reset PUF */ - RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); -#endif /* FSL_FEATURE_PUF_HAS_NO_RESET */ - -#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* Set configuration for SRAM */ - conf->puf_sram_base->CFG |= PUF_SRAM_CTRL_CFG_CKGATING(conf->CKGATING); - -#endif /* FSL_FEATURE_PUF_HAS_SRAM_CTRL */ - - /* Enable power to PUF SRAM */ - puf_powerOn(base, conf); - - /* Wait for peripheral to become ready */ - status = puf_waitForInit(base); - - /* In case of error or enroll or start not allowed, do power-cycle */ - /* First try with shorter discharge time, if then it also fails try with longer time */ - /* conf->dischargeTimeMsec = KEYSTORE_PUF_DISCHARGE_TIME_FIRST_TRY_MS; */ - if ((status != kStatus_Success) || (0U == (base->ALLOW & (PUF_ALLOW_ALLOWENROLL_MASK | PUF_ALLOW_ALLOWSTART_MASK)))) - { - (void)PUF_PowerCycle(base, conf); - status = puf_waitForInit(base); - } - - /* In case of error or enroll or start not allowed, do power-cycle with worst discharge timing */ - if ((status != kStatus_Success) || (0U == (base->ALLOW & (PUF_ALLOW_ALLOWENROLL_MASK | PUF_ALLOW_ALLOWSTART_MASK)))) - { - conf->dischargeTimeMsec = KEYSTORE_PUF_DISCHARGE_TIME_MAX_MS; - (void)PUF_PowerCycle(base, conf); - status = puf_waitForInit(base); - } - - return status; -} - -/*! - * brief Denitialize PUF - * - * This function disables power to PUF SRAM and peripheral clock. - * - * param base PUF peripheral base address - * param conf PUF configuration structure - */ -void PUF_Deinit(PUF_Type *base, puf_config_t *conf) -{ -#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) - /* RT6xxs */ - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* disable RAM CK */ - - /* enter ASPS mode */ - base->PWRCTRL = (PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* SLEEP = 1 */ - base->PWRCTRL = PUF_PWRCTRL_RAMINIT_MASK; /* enable RAM CK */ - base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | PUF_PWRCTRL_RAMPSWLARGEMP_MASK | - PUF_PWRCTRL_RAMPSWSMALLMA_MASK | PUF_PWRCTRL_RAMPSWSMALLMP_MASK); /* SLEEP=1, PSW*=1 */ - puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); -#elif defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* LPCXpresso55s16 */ - conf->puf_sram_base = PUF_SRAM_CTRL; - conf->puf_sram_base->CFG &= PUF_ENABLE_MASK; -#else /* !FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ - /* LPCXpresso55s69 & LPCXpresso54S018 */ - base->PWRCTRL = 0x00u; - puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); -#endif - -#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) - RESET_SetPeripheralReset(kPUF_RST_SHIFT_RSTn); -#endif /* FSL_FEATURE_PUF_HAS_NO_RESET */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Puf); -#endif -} - -/*! - * brief Enroll PUF - * - * This function derives a digital fingerprint, generates the corresponding Activation Code (AC) - * and returns it to be stored in an NVM or a file. This step needs to be - * performed only once for each device. This function may be permanently disallowed by a fuse. - * - * param base PUF peripheral base address - * param[out] activationCode Word aligned address of the resulting activation code. - * param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. - * return Status of enroll operation. - */ -status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize) -{ - status_t status = kStatus_Fail; - uint32_t *activationCodeAligned = NULL; - register uint32_t temp32 = 0; - - /* check that activation code buffer size is at least 1192 bytes */ - if (activationCodeSize < PUF_ACTIVATION_CODE_SIZE) - { - return kStatus_InvalidArgument; - } - - /* only work with aligned activationCode */ - if (0U != (0x3u & (uintptr_t)activationCode)) - { - return kStatus_InvalidArgument; - } - - activationCodeAligned = (uint32_t *)(uintptr_t)activationCode; - - /* check if ENROLL is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWENROLL_MASK)) - { - return kStatus_EnrollNotAllowed; - } - - /* begin */ - base->CTRL = PUF_CTRL_ENROLL_MASK; - - /* check status */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* read out AC */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) - { - temp32 = base->CODEOUTPUT; - if (activationCodeSize >= sizeof(uint32_t)) - { - *activationCodeAligned = temp32; - activationCodeAligned++; - activationCodeSize -= sizeof(uint32_t); - } - } - } - - if (((base->STAT & PUF_STAT_SUCCESS_MASK) != 0U) && (activationCodeSize == 0U)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Start PUF - * - * The Activation Code generated during the Enroll operation is used to - * reconstruct the digital fingerprint. This needs to be done after every power-up - * and reset. - * - * param base PUF peripheral base address - * param activationCode Word aligned address of the input activation code. - * param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. - * return Status of start operation. - */ -status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize) -{ - status_t status = kStatus_Fail; - const uint32_t *activationCodeAligned = NULL; - register uint32_t temp32 = 0; - - /* check that activation code size is at least 1192 bytes */ - if (activationCodeSize < 1192U) - { - return kStatus_InvalidArgument; - } - - /* only work with aligned activationCode */ - if (0U != (0x3u & (uintptr_t)activationCode)) - { - return kStatus_InvalidArgument; - } - - activationCodeAligned = (const uint32_t *)(uintptr_t)activationCode; - - /* check if START is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSTART_MASK)) - { - return kStatus_StartNotAllowed; - } - - /* begin */ - base->CTRL = PUF_CTRL_START_MASK; - - /* check status */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy send AC */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_CODEINREQ_MASK & base->STAT)) - { - if (activationCodeSize >= sizeof(uint32_t)) - { - temp32 = *activationCodeAligned; - activationCodeAligned++; - activationCodeSize -= sizeof(uint32_t); - } - base->CODEINPUT = temp32; - } - } - - /* get status */ - if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Set intrinsic key - * - * The digital fingerprint generated during the Enroll/Start - * operations is used to generate a Key Code (KC) that defines a unique intrinsic - * key. This KC is returned to be stored in an NVM or a file. This operation - * needs to be done only once for each intrinsic key. - * Each time a Set Intrinsic Key operation is executed a new unique key is - * generated. - * - * param base PUF peripheral base address - * param keyIndex PUF key index register - * param keySize Size of the intrinsic key to generate in bytes. - * param[out] keyCode Word aligned address of the resulting key code. - * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * return Status of set intrinsic key operation. - */ -status_t PUF_SetIntrinsicKey( - PUF_Type *base, puf_key_index_register_t keyIndex, size_t keySize, uint8_t *keyCode, size_t keyCodeSize) -{ - status_t status = kStatus_Fail; - uint32_t *keyCodeAligned = NULL; - register uint32_t temp32 = 0; - - /* check if SET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSETKEY_MASK)) - { - return kStatus_Fail; - } - - /* only work with aligned keyCode */ - if (0U != (0x3u & (uintptr_t)keyCode)) - { - return kStatus_InvalidArgument; - } - - /* Check that keySize is in the correct range and that it is multiple of 8 */ - if ((keySize < (uint32_t)kPUF_KeySizeMin) || (keySize > (uint32_t)kPUF_KeySizeMax) || (0U != (keySize & 0x7U))) - { - return kStatus_InvalidArgument; - } - - /* check that keyCodeSize is correct for given keySize */ - if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize)) - { - return kStatus_InvalidArgument; - } - - if ((uint32_t)keyIndex > (uint32_t)kPUF_KeyIndexMax) - { - return kStatus_InvalidArgument; - } - - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - - /* program the key size and index */ - base->KEYSIZE = keySize >> 3; - base->KEYINDEX = (uint32_t)keyIndex; - - /* begin */ - base->CTRL = PUF_CTRL_GENERATEKEY_MASK; - - /* wait till command is accepted */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy read KC */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) - { - temp32 = base->CODEOUTPUT; - if (keyCodeSize >= sizeof(uint32_t)) - { - *keyCodeAligned = temp32; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - } - } - - /* get status */ - if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Set user key - * - * The digital fingerprint generated during the Enroll/Start - * operations and a user key (UK) provided as input are used to - * generate a Key Code (KC). This KC is sent returned to be stored - * in an NVM or a file. This operation needs to be done only once for each user key. - * - * param base PUF peripheral base address - * param keyIndex PUF key index register - * param userKey Word aligned address of input user key. - * param userKeySize Size of the input user key in bytes. - * param[out] keyCode Word aligned address of the resulting key code. - * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize). - * return Status of set user key operation. - */ -status_t PUF_SetUserKey(PUF_Type *base, - puf_key_index_register_t keyIndex, - const uint8_t *userKey, - size_t userKeySize, - uint8_t *keyCode, - size_t keyCodeSize) -{ - status_t status = kStatus_Fail; - uint32_t *keyCodeAligned = NULL; - const uint32_t *userKeyAligned = NULL; - register uint32_t temp32 = 0; - - /* check if SET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSETKEY_MASK)) - { - return kStatus_Fail; - } - - /* only work with aligned keyCode */ - if (0U != (0x3u & (uintptr_t)keyCode)) - { - return kStatus_InvalidArgument; - } - - /* Check that userKeySize is in the correct range and that it is multiple of 8 */ - if ((userKeySize < (uint32_t)kPUF_KeySizeMin) || (userKeySize > (uint32_t)kPUF_KeySizeMax) || - (0U != (userKeySize & 0x7U))) - { - return kStatus_InvalidArgument; - } - - /* check that keyCodeSize is correct for given userKeySize */ - if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize)) - { - return kStatus_InvalidArgument; - } - - if ((uint32_t)keyIndex > (uint32_t)kPUF_KeyIndexMax) - { - return kStatus_InvalidArgument; - } - - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - userKeyAligned = (const uint32_t *)(uintptr_t)userKey; - - /* program the key size and index */ - base->KEYSIZE = userKeySize >> 3; /* convert to 64-bit blocks */ - base->KEYINDEX = (uint32_t)keyIndex; - - /* We have to store the user key on index 0 swaped for HW bus */ - if (keyIndex == kPUF_KeyIndex_00) - { - userKeyAligned = userKeyAligned + (userKeySize / sizeof(uint32_t)); - } - - /* begin */ - base->CTRL = PUF_CTRL_SETKEY_MASK; - - /* wait till command is accepted */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy write UK and read KC */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_KEYINREQ_MASK & base->STAT)) - { - if (userKeySize >= sizeof(uint32_t)) - { -#if defined(LPC54S018_SERIES) - if (keyIndex == kPUF_KeyIndex_00) - { - userKeyAligned--; - temp32 = *userKeyAligned; - userKeySize -= sizeof(uint32_t); - } -#else - if (keyIndex == kPUF_KeyIndex_00) - { - userKeyAligned--; - temp32 = __REV(*userKeyAligned); - userKeySize--; - } -#endif /* defined(LPC54S018_SERIES) */ - else if (keyIndex != kPUF_KeyIndex_00) - { - temp32 = *userKeyAligned; - userKeyAligned++; - userKeySize -= sizeof(uint32_t); - } - else - { - /* Intentional empty */ - } - } - base->KEYINPUT = temp32; - } - - if (0U != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) - { - temp32 = base->CODEOUTPUT; - if (keyCodeSize >= sizeof(uint32_t)) - { - *keyCodeAligned = temp32; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - } - } - - /* get status */ - if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -static status_t puf_getHwKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize) -{ - status_t status = kStatus_Fail; - uint32_t *keyCodeAligned = NULL; - register uint32_t temp32 = 0; - - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - - /* begin */ - base->CTRL = PUF_CTRL_GETKEY_MASK; - - /* wait till command is accepted */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy send KC, key is reconstructed to HW bus */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_CODEINREQ_MASK & base->STAT)) - { - if (keyCodeSize >= sizeof(uint32_t)) - { - temp32 = *keyCodeAligned; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - base->CODEINPUT = temp32; - } - } - - /* get status */ - if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Reconstruct hw bus key from a key code - * - * The digital fingerprint generated during the Start operation and the KC - * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This - * operation needs to be done every time a key is needed. - * This function accepts only Key Codes created for PUF index register kPUF_KeyIndex_00. - * Such a key is output directly to a dedicated hardware bus. The reconstructed key is not exposed to system memory. - * - * param base PUF peripheral base address - * param keyCode Word aligned address of the input key code. - * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * param keySlot key slot to output on hw bus. Parameter is ignored on devices with less than two key slots. - * param keyMask key masking value. Shall be random for each POR/reset. Value does not have to be cryptographicaly - * secure. - * return Status of get key operation. - */ -status_t PUF_GetHwKey( - PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, puf_key_slot_t keySlot, uint32_t keyMask) -{ - status_t status = kStatus_Fail; - uint32_t keyIndex; - - /* check if GET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK)) - { - return kStatus_Fail; - } - - /* only work with aligned keyCode */ - if (0U != (0x3u & (uintptr_t)keyCode)) - { - return kStatus_Fail; - } - - /* check that keyCodeSize is at least PUF_MIN_KEY_CODE_SIZE */ - if (keyCodeSize < PUF_MIN_KEY_CODE_SIZE) - { - return kStatus_InvalidArgument; - } - - keyIndex = (uint32_t)(0x0Fu & (uint32_t)keyCode[1]); - - /* check the Key Code header byte 1. index must be zero for the hw key. */ - if (kPUF_KeyIndex_00 != (puf_key_index_register_t)keyIndex) - { - return kStatus_Fail; - } - -#if defined(PUF_KEYMASK_COUNT) && (PUF_KEYMASK_COUNT > 0) - volatile uint32_t *keyMask_reg = NULL; - uint32_t regVal = ((uint32_t)2U << ((uint32_t)2U * (uint32_t)keySlot)); - - switch (keySlot) - { - case kPUF_KeySlot0: - keyMask_reg = &base->KEYMASK[0]; - break; - - case kPUF_KeySlot1: - keyMask_reg = &base->KEYMASK[1]; - break; -#if (PUF_KEYMASK_COUNT > 2) - case kPUF_KeySlot2: - keyMask_reg = &base->KEYMASK[2]; - break; - - case kPUF_KeySlot3: - keyMask_reg = &base->KEYMASK[3]; - break; -#endif /* PUF_KEYMASK_COUNT > 2 */ - default: - status = kStatus_InvalidArgument; - break; - } -#endif /* PUF_KEYMASK_COUNT */ - - if (status != kStatus_InvalidArgument) - { -#if defined(PUF_KEYMASK_COUNT) && (PUF_KEYMASK_COUNT > 0) - base->KEYRESET = regVal; - base->KEYENABLE = regVal; - *keyMask_reg = keyMask; -#endif /* FSL_FEATURE_PUF_HAS_KEYSLOTS */ - - status = puf_getHwKey(base, keyCode, keyCodeSize); - -#if defined(FSL_FEATURE_PUF_HAS_SHIFT_STATUS) && (FSL_FEATURE_PUF_HAS_SHIFT_STATUS > 0) - size_t keyWords = 0; - - if (status == kStatus_Success) - { - /* if the corresponding shift count does not match, return fail anyway */ - keyWords = ((((size_t)keyCode[3]) * 2U) - 1u) << ((size_t)keySlot << 2U); - if (keyWords != ((0x0FUL << ((uint32_t)keySlot << 2U)) & base->SHIFT_STATUS)) - { - status = kStatus_Fail; - } - } -#elif defined(PUF_IDXBLK_SHIFT_IND_KEY0_MASK) && PUF_IDXBLK_SHIFT_IND_KEY0_MASK - size_t keyWords = 0; - - if (status == kStatus_Success) - { - /* if the corresponding shift count does not match, return fail anyway */ - keyWords = ((((size_t)keyCode[3]) * 2U) - 1u) << ((size_t)keySlot << 2U); - if (keyWords != ((0x0FUL << ((uint32_t)keySlot << 2U)) & base->IDXBLK_SHIFT)) - { - status = kStatus_Fail; - } - } -#endif /* FSL_FEATURE_PUF_HAS_SHIFT_STATUS || PUF_IDXBLK_SHIFT_IND_KEY0_MASK */ - } - - return status; -} - -/*! - * brief Checks if Get Key operation is allowed. - * - * This function returns true if get key operation is allowed. - * - * param base PUF peripheral base address - * return true if get key operation is allowed - */ -bool PUF_IsGetKeyAllowed(PUF_Type *base) -{ - /* check if GET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK)) - { - return false; - } - - return true; -} - -/*! - * brief Reconstruct key from a key code - * - * The digital fingerprint generated during the Start operation and the KC - * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This - * operation needs to be done every time a key is needed. - * This function accepts only Key Codes created for PUF index registers kPUF_KeyIndex_01 to kPUF_KeyIndex_15. - * - * param base PUF peripheral base address - * param keyCode Word aligned address of the input key code. - * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * param[out] key Word aligned address of output key. - * param keySize Size of the output key in bytes. - * return Status of get key operation. - */ -status_t PUF_GetKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize) -{ - status_t status = kStatus_Fail; - uint32_t *keyCodeAligned = NULL; - uint32_t *keyAligned = NULL; - uint32_t keyIndex; - register uint32_t temp32 = 0; - - /* check if GET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK)) - { - return kStatus_Fail; - } - - /* only work with aligned keyCode */ - if (0U != (0x3u & (uintptr_t)keyCode)) - { - return kStatus_Fail; - } - - /* only work with aligned key */ - if (0U != (0x3u & (uintptr_t)key)) - { - return kStatus_Fail; - } - - /* check that keyCodeSize is correct for given keySize */ - if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize)) - { - return kStatus_InvalidArgument; - } - - keyIndex = (0x0Fu & (uint32_t)keyCode[1]); - - /* check the Key Code header byte 1. index must be non-zero for the register key. */ - if (kPUF_KeyIndex_00 == (puf_key_index_register_t)keyIndex) - { - return kStatus_Fail; - } - - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - keyAligned = (uint32_t *)(uintptr_t)key; - - /* begin */ - base->CTRL = PUF_CTRL_GETKEY_MASK; - - /* wait till command is accepted */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy send KC, read key */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_CODEINREQ_MASK & base->STAT)) - { - temp32 = 0; - if (keyCodeSize >= sizeof(uint32_t)) - { - temp32 = *keyCodeAligned; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - base->CODEINPUT = temp32; - } - - if (0U != (PUF_STAT_KEYOUTAVAIL_MASK & base->STAT)) - { - keyIndex = base->KEYOUTINDEX; - temp32 = base->KEYOUTPUT; - if (keySize >= sizeof(uint32_t)) - { - *keyAligned = temp32; - keyAligned++; - keySize -= sizeof(uint32_t); - } - } - } - - /* get status */ - if ((keyIndex != 0U) && (0U != (base->STAT & PUF_STAT_SUCCESS_MASK))) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Zeroize PUF - * - * This function clears all PUF internal logic and puts the PUF to error state. - * - * param base PUF peripheral base address - * return Status of the zeroize operation. - */ -status_t PUF_Zeroize(PUF_Type *base) -{ - status_t status = kStatus_Fail; - - /* zeroize command is always allowed */ - base->CTRL = PUF_CTRL_ZEROIZE_MASK; - - /* check that command is accepted */ - if ((0U != (base->STAT & PUF_STAT_ERROR_MASK)) && (0U == base->ALLOW)) - { - status = kStatus_Success; - } - - return status; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_puf.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_puf.h deleted file mode 100644 index b8a5c51c856..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_puf.h +++ /dev/null @@ -1,335 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PUF_H_ -#define _PUF_H_ - -#include -#include - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! - * @addtogroup puf_driver - * @{ - */ -/*! @name Driver version */ -/*@{*/ -/*! @brief PUF driver version. Version 2.1.6. - * - * Current version: 2.1.6 - * - * Change log: - * - 2.0.0 - * - Initial version. - * - 2.0.1 - * - Fixed puf_wait_usec function optimization issue. - * - 2.0.2 - * - Add PUF configuration structure and support for PUF SRAM controller. - * Remove magic constants. - * - 2.0.3 - * - Fix MISRA C-2012 issue. - * - 2.1.0 - * - Align driver with PUF SRAM controller registers on LPCXpresso55s16. - * - Update initizalition logic . - * - 2.1.1 - * - Fix ARMGCC build warning . - * - 2.1.2 - * - Update: Add automatic big to little endian swap for user - * (pre-shared) keys destinated to secret hardware bus (PUF key index 0). - * - 2.1.3 - * - Fix MISRA C-2012 issue. - * - 2.1.4 - * - Replace register uint32_t ticksCount with volatile uint32_t ticksCount in puf_wait_usec() to prevent optimization - * out delay loop. - * - 2.1.5 - * - Use common SDK delay in puf_wait_usec() - * - 2.1.6 - * - Changed wait time in PUF_Init(), when initialization fails it will try PUF_Powercycle() with shorter time. If - * this shorter time will also fail, initialization will be tried with worst case time as before. - */ -#define FSL_PUF_DRIVER_VERSION (MAKE_VERSION(2, 1, 6)) -/*@}*/ - -typedef enum _puf_key_index_register -{ - kPUF_KeyIndex_00 = 0x00U, - kPUF_KeyIndex_01 = 0x01U, - kPUF_KeyIndex_02 = 0x02U, - kPUF_KeyIndex_03 = 0x03U, - kPUF_KeyIndex_04 = 0x04U, - kPUF_KeyIndex_05 = 0x05U, - kPUF_KeyIndex_06 = 0x06U, - kPUF_KeyIndex_07 = 0x07U, - kPUF_KeyIndex_08 = 0x08U, - kPUF_KeyIndex_09 = 0x09U, - kPUF_KeyIndex_10 = 0x0AU, - kPUF_KeyIndex_11 = 0x0BU, - kPUF_KeyIndex_12 = 0x0CU, - kPUF_KeyIndex_13 = 0x0DU, - kPUF_KeyIndex_14 = 0x0EU, - kPUF_KeyIndex_15 = 0x0FU, -} puf_key_index_register_t; - -typedef enum _puf_min_max -{ - kPUF_KeySizeMin = 8u, - kPUF_KeySizeMax = 512u, - kPUF_KeyIndexMax = kPUF_KeyIndex_15, -} puf_min_max_t; - -/*! @brief PUF key slot. */ -typedef enum _puf_key_slot -{ - kPUF_KeySlot0 = 0U, /*!< PUF key slot 0 */ - kPUF_KeySlot1 = 1U, /*!< PUF key slot 1 */ -#if defined(PUF_KEYMASK_COUNT) && (PUF_KEYMASK_COUNT > 2) - kPUF_KeySlot2 = 2U, /*!< PUF key slot 2 */ - kPUF_KeySlot3 = 3U, /*!< PUF key slot 3 */ -#endif -} puf_key_slot_t; - -typedef struct -{ - uint32_t dischargeTimeMsec; - uint32_t coreClockFrequencyHz; -#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* LPCXpresso55s16 */ - PUF_SRAM_CTRL_Type *puf_sram_base; - uint8_t CKGATING; -#endif /* FSL_FEATURE_PUF_HAS_SRAM_CTRL */ -} puf_config_t; -/*! @brief Get Key Code size in bytes from key size in bytes at compile time. */ -#define PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(x) ((160u + (((((x) << 3) + 255u) >> 8) << 8)) >> 3) -#define PUF_MIN_KEY_CODE_SIZE PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(8UL) -#define PUF_ACTIVATION_CODE_SIZE 1192U -#define KEYSTORE_PUF_DISCHARGE_TIME_FIRST_TRY_MS 50 -#define KEYSTORE_PUF_DISCHARGE_TIME_MAX_MS 400 - -/*! PUF status return codes. */ -enum -{ - kStatus_EnrollNotAllowed = MAKE_STATUS(kStatusGroup_PUF, 1), - kStatus_StartNotAllowed = MAKE_STATUS(kStatusGroup_PUF, 2) -}; - -/*! @} */ -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @brief Sets the default configuration of PUF - * - * This function initialize PUF config structure to default values. - * - * @param conf PUF configuration structure - */ -void PUF_GetDefaultConfig(puf_config_t *conf); - -/*! - * @brief Initialize PUF - * - * This function enables power to PUF block and waits until the block initializes. - * - * @param base PUF peripheral base address - * @param conf PUF configuration structure - * @return Status of the init operation - */ -status_t PUF_Init(PUF_Type *base, puf_config_t *conf); - -/*! - * @brief Denitialize PUF - * - * This function disables power to PUF SRAM and peripheral clock. - * - * @param base PUF peripheral base address - * @param conf PUF configuration structure - */ -void PUF_Deinit(PUF_Type *base, puf_config_t *conf); - -/*! - * @brief Enroll PUF - * - * This function derives a digital fingerprint, generates the corresponding Activation Code (AC) - * and returns it to be stored in an NVM or a file. This step needs to be - * performed only once for each device. This function may be permanently disallowed by a fuse. - * - * @param base PUF peripheral base address - * @param[out] activationCode Word aligned address of the resulting activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. - * @return Status of enroll operation. - */ -status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize); - -/*! - * @brief Start PUF - * - * The Activation Code generated during the Enroll operation is used to - * reconstruct the digital fingerprint. This needs to be done after every power-up - * and reset. - * - * @param base PUF peripheral base address - * @param activationCode Word aligned address of the input activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. - * @return Status of start operation. - */ -status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize); - -/*! - * @brief Set intrinsic key - * - * The digital fingerprint generated during the Enroll/Start - * operations is used to generate a Key Code (KC) that defines a unique intrinsic - * key. This KC is returned to be stored in an NVM or a file. This operation - * needs to be done only once for each intrinsic key. - * Each time a Set Intrinsic Key operation is executed a new unique key is - * generated. - * - * @param base PUF peripheral base address - * @param keyIndex PUF key index register - * @param keySize Size of the intrinsic key to generate in bytes. - * @param[out] keyCode Word aligned address of the resulting key code. - * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * @return Status of set intrinsic key operation. - */ -status_t PUF_SetIntrinsicKey( - PUF_Type *base, puf_key_index_register_t keyIndex, size_t keySize, uint8_t *keyCode, size_t keyCodeSize); - -/*! - * @brief Set user key - * - * The digital fingerprint generated during the Enroll/Start - * operations and a user key (UK) provided as input are used to - * generate a Key Code (KC). This KC is sent returned to be stored - * in an NVM or a file. This operation needs to be done only once for each user key. - * - * @param base PUF peripheral base address - * @param keyIndex PUF key index register - * @param userKey Word aligned address of input user key. - * @param userKeySize Size of the input user key in bytes. - * @param[out] keyCode Word aligned address of the resulting key code. - * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize). - * @return Status of set user key operation. - */ -status_t PUF_SetUserKey(PUF_Type *base, - puf_key_index_register_t keyIndex, - const uint8_t *userKey, - size_t userKeySize, - uint8_t *keyCode, - size_t keyCodeSize); - -/*! - * @brief Reconstruct key from a key code - * - * The digital fingerprint generated during the Start operation and the KC - * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This - * operation needs to be done every time a key is needed. - * This function accepts only Key Codes created for PUF index registers kPUF_KeyIndex_01 to kPUF_KeyIndex_15. - * - * @param base PUF peripheral base address - * @param keyCode Word aligned address of the input key code. - * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * @param[out] key Word aligned address of output key. - * @param keySize Size of the output key in bytes. - * @return Status of get key operation. - */ -status_t PUF_GetKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize); - -/*! - * @brief Reconstruct hw bus key from a key code - * - * The digital fingerprint generated during the Start operation and the KC - * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This - * operation needs to be done every time a key is needed. - * This function accepts only Key Codes created for PUF index register kPUF_KeyIndex_00. - * Such a key is output directly to a dedicated hardware bus. The reconstructed key is not exposed to system memory. - * - * @param base PUF peripheral base address - * @param keyCode Word aligned address of the input key code. - * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * @param keySlot key slot to output on hw bus. Parameter is ignored on devices with less than two key slots. - * @param keyMask key masking value. Shall be random for each POR/reset. Value does not have to be cryptographicaly - * secure. - * @return Status of get key operation. - */ -status_t PUF_GetHwKey( - PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, puf_key_slot_t keySlot, uint32_t keyMask); - -/*! - * @brief Zeroize PUF - * - * This function clears all PUF internal logic and puts the PUF to error state. - * - * @param base PUF peripheral base address - * @return Status of the zeroize operation. - */ -status_t PUF_Zeroize(PUF_Type *base); - -/*! - * @brief Checks if Get Key operation is allowed. - * - * This function returns true if get key operation is allowed. - * - * @param base PUF peripheral base address - * @return true if get key operation is allowed - */ -bool PUF_IsGetKeyAllowed(PUF_Type *base); - -#if defined(PUF_CFG_BLOCKKEYOUTPUT_MASK) && PUF_CFG_BLOCKKEYOUTPUT_MASK -static inline void PUF_BlockSetKey(PUF_Type *base) -{ - base->CFG |= PUF_CFG_BLOCKKEYOUTPUT_MASK; /* block set key */ -} -#endif /* PUF_CFG_BLOCKKEYOUTPUT_MASK */ - -#if defined(PUF_CFG_PUF_BLOCK_SET_KEY_MASK) && PUF_CFG_PUF_BLOCK_SET_KEY_MASK -static inline void PUF_BlockSetKey(PUF_Type *base) -{ - base->CFG |= PUF_CFG_PUF_BLOCK_SET_KEY_MASK; /* block set key */ -} -#endif /* PUF_CFG_PUF_BLOCK_SET_KEY_MASK */ - -#if defined(PUF_CFG_BLOCKENROLL_SETKEY_MASK) && PUF_CFG_BLOCKENROLL_SETKEY_MASK -static inline void PUF_BlockEnroll(PUF_Type *base) -{ - base->CFG |= PUF_CFG_BLOCKENROLL_SETKEY_MASK; /* block enroll */ -} -#endif /* PUF_CFG_BLOCKENROLL_SETKEY_MASK */ - -#if defined(PUF_CFG_PUF_BLOCK_ENROLL_MASK) && PUF_CFG_PUF_BLOCK_ENROLL_MASK -static inline void PUF_BlockEnroll(PUF_Type *base) -{ - base->CFG |= PUF_CFG_PUF_BLOCK_ENROLL_MASK; /* block enroll */ -} -#endif /* PUF_CFG_PUF_BLOCK_ENROLL_MASK */ - -/*! - * @brief Powercycle PUF - * - * This function make powercycle. - * - * @param base PUF peripheral base address - * @param conf PUF configuration structure - * @return Status of the powercycle operation. - */ -status_t PUF_PowerCycle(PUF_Type *base, puf_config_t *conf); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -#endif /* _PUF_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_reset.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_reset.c deleted file mode 100644 index 4326e0dae24..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_reset.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#include "fsl_reset.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.reset" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - -/*! - * brief Assert reset to peripheral. - * - * Asserts reset signal to specified peripheral module. - * - * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_SetPeripheralReset(reset_ip_name_t peripheral) -{ - const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; - const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); - const uint32_t bitMask = 1UL << bitPos; - - assert(bitPos < 32u); - - /* reset register is in SYSCON */ - /* set bit */ - SYSCON->PRESETCTRLSET[regIndex] = bitMask; - /* wait until it reads 0b1 */ - while (0u == (SYSCON->PRESETCTRLX[regIndex] & bitMask)) - { - } -} - -/*! - * brief Clear reset to peripheral. - * - * Clears reset signal to specified peripheral module, allows it to operate. - * - * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) -{ - const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; - const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); - const uint32_t bitMask = 1UL << bitPos; - - assert(bitPos < 32u); - - /* reset register is in SYSCON */ - - /* clear bit */ - SYSCON->PRESETCTRLCLR[regIndex] = bitMask; - /* wait until it reads 0b0 */ - while (bitMask == (SYSCON->PRESETCTRLX[regIndex] & bitMask)) - { - } -} - -/*! - * brief Reset peripheral module. - * - * Reset peripheral module. - * - * param peripheral Peripheral to reset. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_PeripheralReset(reset_ip_name_t peripheral) -{ - RESET_SetPeripheralReset(peripheral); - RESET_ClearPeripheralReset(peripheral); -} - -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_reset.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_reset.h deleted file mode 100644 index 57cfe096b46..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_reset.h +++ /dev/null @@ -1,237 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_RESET_H_ -#define _FSL_RESET_H_ - -#include -#include -#include -#include -#include "fsl_device_registers.h" - -/*! - * @addtogroup reset - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief reset driver version 2.3.3. */ -#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 3, 3)) -/*@}*/ - -/*! - * @brief Enumeration for peripheral reset control bits - * - * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers - */ -typedef enum _SYSCON_RSTn -{ - kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */ - kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */ - kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */ - kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ - kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ - kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */ - kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ - kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ - kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ - kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ - kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ - kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ - kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ - kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ - kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */ - kMAILBOX_RST_SHIFT_RSTn = 0 | 26U, /**< Mailbox reset control */ - kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ - - kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ - kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */ - kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ - kMCAN_RST_SHIFT_RSTn = 65536 | 7U, /**< MCAN reset control */ - kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ - kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ - kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ - kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ - kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ - kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ - kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ - kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ - kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ - kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */ - kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */ - kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */ - kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */ - kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */ - - kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */ - kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */ - kSRAM3_RST_SHIFT_RSTn = 131072 | 6U, /**< SRAM3 reset control */ - kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */ - kCDOG_RST_SHIFT_RSTn = 131072 | 11U, /**< Code Watchdog reset control */ - kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */ - kSYSCTL_RST_SHIFT_RSTn = 131072 | 15U, /**< SYSCTL reset control */ - kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */ - kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */ - kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */ - kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */ - kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */ - kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */ - kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */ - kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */ - kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */ - kGPIOSECINT_RST_SHIFT_RSTn = 131072 | 30U, /**< GPIO Secure int reset control */ -} SYSCON_RSTn_t; - -/** Array initializers with peripheral reset bits **/ -#define ADC_RSTS \ - { \ - kADC0_RST_SHIFT_RSTn \ - } /* Reset bits for ADC peripheral */ -#define MCAN_RSTS \ - { \ - kMCAN_RST_SHIFT_RSTn \ - } /* Reset bits for CAN peripheral */ -#define CRC_RSTS \ - { \ - kCRC_RST_SHIFT_RSTn \ - } /* Reset bits for CRC peripheral */ -#define CTIMER_RSTS \ - { \ - kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \ - kCTIMER4_RST_SHIFT_RSTn \ - } /* Reset bits for CTIMER peripheral */ -#define DMA_RSTS_N \ - { \ - kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \ - } /* Reset bits for DMA peripheral */ - -#define FLEXCOMM_RSTS \ - { \ - kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ - kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kHSLSPI_RST_SHIFT_RSTn \ - } /* Reset bits for FLEXCOMM peripheral */ -#define GINT_RSTS \ - { \ - kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ - } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ -#define GPIO_RSTS_N \ - { \ - kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn \ - } /* Reset bits for GPIO peripheral */ -#define INPUTMUX_RSTS \ - { \ - kMUX0_RST_SHIFT_RSTn \ - } /* Reset bits for INPUTMUX peripheral */ -#define IOCON_RSTS \ - { \ - kIOCON_RST_SHIFT_RSTn \ - } /* Reset bits for IOCON peripheral */ -#define FLASH_RSTS \ - { \ - kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ - } /* Reset bits for Flash peripheral */ -#define MRT_RSTS \ - { \ - kMRT_RST_SHIFT_RSTn \ - } /* Reset bits for MRT peripheral */ -#define PINT_RSTS \ - { \ - kPINT_RST_SHIFT_RSTn \ - } /* Reset bits for PINT peripheral */ -#define CDOG_RSTS \ - { \ - kCDOG_RST_SHIFT_RSTn \ - } /* Reset bits for CDOG peripheral */ -#define RNG_RSTS \ - { \ - kRNG_RST_SHIFT_RSTn \ - } /* Reset bits for RNG peripheral */ -#define SCT_RSTS \ - { \ - kSCT0_RST_SHIFT_RSTn \ - } /* Reset bits for SCT peripheral */ -#define UTICK_RSTS \ - { \ - kUTICK_RST_SHIFT_RSTn \ - } /* Reset bits for UTICK peripheral */ -#define WWDT_RSTS \ - { \ - kWWDT_RST_SHIFT_RSTn \ - } /* Reset bits for WWDT peripheral */ -#define PLU_RSTS_N \ - { \ - kPLULUT_RST_SHIFT_RSTn \ - } /* Reset bits for PLU peripheral */ -#define OSTIMER_RSTS \ - { \ - kOSTIMER0_RST_SHIFT_RSTn \ - } /* Reset bits for OSTIMER peripheral */ -#define CASPER_RSTS \ - { \ - kCASPER_RST_SHIFT_RSTn \ - } /* Reset bits for Casper peripheral */ -#define HASHCRYPT_RSTS \ - { \ - kHASHCRYPT_RST_SHIFT_RSTn \ - } /* Reset bits for Hashcrypt peripheral */ -#define PUF_RSTS \ - { \ - kPUF_RST_SHIFT_RSTn \ - } /* Reset bits for PUF peripheral */ -typedef SYSCON_RSTn_t reset_ip_name_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Assert reset to peripheral. - * - * Asserts reset signal to specified peripheral module. - * - * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_SetPeripheralReset(reset_ip_name_t peripheral); - -/*! - * @brief Clear reset to peripheral. - * - * Clears reset signal to specified peripheral module, allows it to operate. - * - * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); - -/*! - * @brief Reset peripheral module. - * - * Reset peripheral module. - * - * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_PeripheralReset(reset_ip_name_t peripheral); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_RESET_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_rng.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_rng.c deleted file mode 100644 index 1b2e9d4d61e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_rng.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright 2017, 2019, 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_rng.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.rng_1" -#endif - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/******************************************************************************* - * Prototypes - *******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -static void rng_accumulateEntropy(RNG_Type *base) -{ - uint32_t minChiSq; - uint32_t maxChiSq; - - /* Steps to accumulate entropy, more info can be found in LPC55SXX UM*/ - - /* Select fourth clock on which to compute CHI SQUARE statistics*/ - base->COUNTER_CFG = (base->COUNTER_CFG & ~RNG_COUNTER_CFG_CLOCK_SEL_MASK) | RNG_COUNTER_CFG_CLOCK_SEL(4U); - - /* Activate CHI computing */ - base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(1U); - - /* Read min chi squared value, on power on should be higher than max chi squared value */ - minChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT); - - /* Read max chi squared value */ - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - - /* Wait until minChiSq decreases and become smaller than maxChiSq*/ - while (minChiSq > (maxChiSq - 1U)) - { - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - minChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT); - } -} - -/*! - * @brief Gets a entry data from the RNG. - * - * This function gets an entropy data from RNG. - */ -static uint32_t rng_readEntropy(RNG_Type *base) -{ - uint32_t data; - uint32_t refreshCnt, maxChiSq, tmpShift4x; - - /* Activate CHI computing */ - base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(1); - - /* Wait for refresh count become 31 to refill fresh entropy since last read of random number*/ - do - { - refreshCnt = ((base->COUNTER_VAL & RNG_COUNTER_VAL_REFRESH_CNT_MASK) >> RNG_COUNTER_VAL_REFRESH_CNT_SHIFT); - } while (refreshCnt < 31U); - - /* reading RANDOM_NUMBER register will reset refCnt to 0 */ - data = base->RANDOM_NUMBER; - - /* Perform CHI computing by checking max chi squared value */ - /* Wait until maxChiSq become smaller or equal than 4, then next random number can be read*/ - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - - while (maxChiSq > 4U) - { - /* Deactivate CHI computing to reset*/ - base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(0); - - /* read Shift4x register, if is less than 7 increment it and then start accumulating entropy again */ - tmpShift4x = ((base->COUNTER_CFG & RNG_COUNTER_CFG_SHIFT4X_MASK) >> RNG_COUNTER_CFG_SHIFT4X_SHIFT); - if (tmpShift4x < 7U) - { - tmpShift4x++; - base->COUNTER_CFG = - (base->COUNTER_CFG & ~RNG_COUNTER_CFG_SHIFT4X_MASK) | RNG_COUNTER_CFG_SHIFT4X(tmpShift4x); - } - rng_accumulateEntropy(base); - - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - } - - return data; -} - -void RNG_Init(RNG_Type *base) -{ - uint32_t maxChiSq, tmpShift4x; - - /* Clear ring oscilator disable bit*/ - PMC->PDRUNCFGCLR0 = PMC_PDRUNCFG0_PDEN_RNG_MASK; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Rng); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kRNG_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - - /* Turn on CHI Squared test */ - /* Activate CHI computing and wait until min chi squared become smaller than max chi squared */ - rng_accumulateEntropy(base); - - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - - /* When maxChiSq is bigger than 4 its assumed there is not enough entropy and previous steps are repeated */ - /* When maxChiSq is 4 or less initialization is complete and random number can be read*/ - while (maxChiSq > 4U) - { - /* Deactivate CHI coputing to reset*/ - base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(0); - - /* read Shift4x register, if is less than 7 increment it and then start accumulating entropy again */ - tmpShift4x = ((base->COUNTER_CFG & RNG_COUNTER_CFG_SHIFT4X_MASK) >> RNG_COUNTER_CFG_SHIFT4X_SHIFT); - if (tmpShift4x < 7U) - { - tmpShift4x++; - base->COUNTER_CFG = - (base->COUNTER_CFG & ~RNG_COUNTER_CFG_SHIFT4X_MASK) | RNG_COUNTER_CFG_SHIFT4X(tmpShift4x); - } - rng_accumulateEntropy(base); - - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - } -} - -void RNG_Deinit(RNG_Type *base) -{ - /* Set ring oscilator disable bit*/ - PMC->PDRUNCFGSET0 = PMC_PDRUNCFG0_PDEN_RNG_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kRNG_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Rng); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -status_t RNG_GetRandomData(RNG_Type *base, void *data, size_t dataSize) -{ - status_t result = kStatus_Fail; - uint32_t random32; - uint32_t randomSize; - uint8_t *pRandom; - uint8_t *pData = (uint8_t *)data; - uint32_t i; - - /* Check input parameters.*/ - if (!((base != NULL) && (data != NULL) && (dataSize != 0U))) - { - result = kStatus_InvalidArgument; - } - else - { - /* Check that ring oscilator is enabled */ - if (0U == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_RNG_MASK)) - { - do - { - /* Read Entropy.*/ - random32 = rng_readEntropy(base); - pRandom = (uint8_t *)&random32; - - if (dataSize < sizeof(random32)) - { - randomSize = dataSize; - } - else - { - randomSize = sizeof(random32); - } - - for (i = 0; i < randomSize; i++) - { - *pData++ = *pRandom++; - } - - dataSize -= randomSize; - } while (dataSize > 0U); - - result = kStatus_Success; - } - } - - return result; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_rng.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_rng.h deleted file mode 100644 index 38279cad7fa..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_rng.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2017, 2019, 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_RNG_DRIVER_H_ -#define _FSL_RNG_DRIVER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup rng - * @{ - */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief RNG driver version. Version 2.0.3. - * - * Current version: 2.0.3 - * - * Change log: - * - Version 2.0.0 - * - Initial version - * - * - Version 2.0.1 - * - Fix MISRA C-2012 issue. - * - * - Version 2.0.2 - * - Add RESET_PeripheralReset function inside RNG_Init and RNG_Deinit functions. - * - * - Version 2.0.3 - * - Modified RNG_Init and RNG_GetRandomData functions, added rng_accumulateEntropy and rng_readEntropy functions. - * - These changes are reflecting recommended usage of RNG according to device UM. - */ -#define FSL_RNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initializes the RNG. - * - * This function initializes the RNG. - * When called, the RNG module and ring oscillator is enabled. - * - * @param base RNG base address - * @return If successful, returns the kStatus_RNG_Success. Otherwise, it returns an error. - */ -void RNG_Init(RNG_Type *base); - -/*! - * @brief Shuts down the RNG. - * - * This function shuts down the RNG. - * - * @param base RNG base address. - */ -void RNG_Deinit(RNG_Type *base); - -/*! - * @brief Gets random data. - * - * This function gets random data from the RNG. - * - * @param base RNG base address. - * @param data Pointer address used to store random data. - * @param dataSize Size of the buffer pointed by the data parameter. - * @return random data - */ -status_t RNG_GetRandomData(RNG_Type *base, void *data, size_t dataSize); - -/*! - * @brief Returns random 32-bit number. - * - * This function gets random number from the RNG. - * - * @param base RNG base address. - * @return random number - */ -static inline uint32_t RNG_GetRandomWord(RNG_Type *base) -{ - return base->RANDOM_NUMBER; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /*_FSL_RNG_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_rtc.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_rtc.c deleted file mode 100644 index b39370b6830..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_rtc.c +++ /dev/null @@ -1,322 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_rtc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_rtc" -#endif - -#define SECONDS_IN_A_DAY (86400U) -#define SECONDS_IN_A_HOUR (3600U) -#define SECONDS_IN_A_MINUTE (60U) -#define DAYS_IN_A_YEAR (365U) -#define YEAR_RANGE_START (1970U) -#define YEAR_RANGE_END (2099U) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Check whether the date and time passed in is valid - * - * @param datetime Pointer to structure where the date and time details are stored - * - * @return Returns false if the date & time details are out of range; true if in range - */ -static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime); - -/*! - * @brief Convert time data from datetime to seconds - * - * @param datetime Pointer to datetime structure where the date and time details are stored - * - * @return The result of the conversion in seconds - */ -static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime); - -/*! - * @brief Convert time data from seconds to a datetime structure - * - * @param seconds Seconds value that needs to be converted to datetime format - * @param datetime Pointer to the datetime structure where the result of the conversion is stored - */ -static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime); - -/******************************************************************************* - * Code - ******************************************************************************/ -static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Check year, month, hour, minute, seconds */ - if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || - (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) - { - /* If not correct then error*/ - return false; - } - - /* Adjust the days in February for a leap year */ - if ((((datetime->year & 3U) == 0U) && (datetime->year % 100U != 0U)) || (datetime->year % 400U == 0U)) - { - daysPerMonth[2] = 29U; - } - - /* Check the validity of the day */ - if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) - { - return false; - } - - return true; -} - -static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Number of days from begin of the non Leap-year*/ - /* Number of days from begin of the non Leap-year*/ - uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; - uint32_t seconds; - - /* Compute number of days from 1970 till given year*/ - seconds = ((uint32_t)datetime->year - 1970U) * DAYS_IN_A_YEAR; - /* Add leap year days */ - seconds += (((uint32_t)datetime->year / 4U) - (1970U / 4U)); - /* Add number of days till given month*/ - seconds += monthDays[datetime->month]; - /* Add days in given month. We subtract the current day as it is - * represented in the hours, minutes and seconds field*/ - seconds += ((uint32_t)datetime->day - 1U); - /* For leap year if month less than or equal to Febraury, decrement day counter*/ - if (((datetime->year & 3U) == 0x00U) && (datetime->month <= 2U)) - { - seconds--; - } - - seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + - (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; - - return seconds; -} - -static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint8_t i; - uint16_t daysInYear; - uint32_t secondsRemaining; - uint32_t days; - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Start with the seconds value that is passed in to be converted to date time format */ - secondsRemaining = seconds; - - /* Calcuate the number of days, we add 1 for the current day which is represented in the - * hours and seconds field - */ - days = secondsRemaining / SECONDS_IN_A_DAY + 1U; - - /* Update seconds left*/ - secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; - - /* Calculate the datetime hour, minute and second fields */ - datetime->hour = (uint8_t)(secondsRemaining / SECONDS_IN_A_HOUR); - secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; - datetime->minute = (uint8_t)(secondsRemaining / 60U); - datetime->second = (uint8_t)(secondsRemaining % SECONDS_IN_A_MINUTE); - - /* Calculate year */ - daysInYear = DAYS_IN_A_YEAR; - datetime->year = YEAR_RANGE_START; - while (days > daysInYear) - { - /* Decrease day count by a year and increment year by 1 */ - days -= daysInYear; - datetime->year++; - - /* Adjust the number of days for a leap year */ - if ((datetime->year & 3U) != 0x00U) - { - daysInYear = DAYS_IN_A_YEAR; - } - else - { - daysInYear = DAYS_IN_A_YEAR + 1U; - } - } - - /* Adjust the days in February for a leap year */ - if ((datetime->year & 3U) == 0x00U) - { - daysPerMonth[2] = 29U; - } - - for (i = 1U; i <= 12U; i++) - { - if (days <= daysPerMonth[i]) - { - datetime->month = i; - break; - } - else - { - days -= daysPerMonth[i]; - } - } - - datetime->day = (uint8_t)days; -} - -/*! - * brief Ungate the RTC clock and enables the RTC oscillator. - * - * note This API should be called at the beginning of the application using the RTC driver. - * - * param base RTC peripheral base address - */ -void RTC_Init(RTC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the RTC peripheral clock */ - CLOCK_EnableClock(kCLOCK_Rtc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_RTC_HAS_NO_RESET) && FSL_FEATURE_RTC_HAS_NO_RESET) - RESET_PeripheralReset(kRTC_RST_SHIFT_RSTn); -#endif - /* Make sure the reset bit is cleared */ - base->CTRL &= ~RTC_CTRL_SWRESET_MASK; - -#if !(defined(FSL_FEATURE_RTC_HAS_NO_OSC_PD) && FSL_FEATURE_RTC_HAS_NO_OSC_PD) - /* Make sure the RTC OSC is powered up */ - base->CTRL &= ~RTC_CTRL_RTC_OSC_PD_MASK; -#endif -} - -/*! - * brief Set the RTC date and time according to the given time structure. - * - * The RTC counter must be stopped prior to calling this function as writes to the RTC - * seconds register will fail if the RTC counter is running. - * - * param base RTC peripheral base address - * param datetime Pointer to structure where the date and time details to set are stored - * - * return kStatus_Success: Success in setting the time and starting the RTC - * kStatus_InvalidArgument: Error because the datetime format is incorrect - */ -status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Return error if the time provided is not valid */ - if (!(RTC_CheckDatetimeFormat(datetime))) - { - return kStatus_InvalidArgument; - } - - /* Set time in seconds */ - base->COUNT = RTC_ConvertDatetimeToSeconds(datetime); - - return kStatus_Success; -} - -/*! - * brief Gets the RTC time and stores it in the given time structure. - * - * param base RTC peripheral base address - * param datetime Pointer to structure where the date and time details are stored. - */ -void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t seconds = 0; - - seconds = RTC_GetSecondsTimerCount(base); - RTC_ConvertSecondsToDatetime(seconds, datetime); -} - -/*! - * brief Set the RTC alarm time - * - * The function checks whether the specified alarm time is greater than the present - * time. If not, the function does not set the alarm and returns an error. - * - * param base RTC peripheral base address - * param alarmTime Pointer to structure where the alarm time is stored. - * - * return kStatus_Success: success in setting the RTC alarm - * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect - * kStatus_Fail: Error because the alarm time has already passed - */ -status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) -{ - assert(alarmTime != NULL); - - uint32_t alarmSeconds = 0; - uint32_t currSeconds = 0; - - /* Return error if the alarm time provided is not valid */ - if (!(RTC_CheckDatetimeFormat(alarmTime))) - { - return kStatus_InvalidArgument; - } - - alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime); - - /* Get the current time */ - currSeconds = RTC_GetSecondsTimerCount(base); - - /* Return error if the alarm time has passed */ - if (alarmSeconds < currSeconds) - { - return kStatus_Fail; - } - - /* Set alarm in seconds*/ - base->MATCH = alarmSeconds; - - return kStatus_Success; -} - -/*! - * brief Return the RTC alarm time. - * - * param base RTC peripheral base address - * param datetime Pointer to structure where the alarm date and time details are stored. - */ -void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t alarmSeconds = 0; - - /* Get alarm in seconds */ - alarmSeconds = base->MATCH; - - RTC_ConvertSecondsToDatetime(alarmSeconds, datetime); -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_rtc.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_rtc.h deleted file mode 100644 index a960d8baf7c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_rtc.h +++ /dev/null @@ -1,493 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_RTC_H_ -#define _FSL_RTC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup rtc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*!< Version 2.1.2 */ -/*@}*/ - -/*! @brief List of RTC interrupts */ -typedef enum _rtc_interrupt_enable -{ - kRTC_AlarmInterruptEnable = RTC_CTRL_ALARMDPD_EN_MASK, /*!< Alarm interrupt.*/ - kRTC_WakeupInterruptEnable = RTC_CTRL_WAKEDPD_EN_MASK /*!< Wake-up interrupt.*/ -} rtc_interrupt_enable_t; - -/*! @brief List of RTC flags */ -typedef enum _rtc_status_flags -{ - kRTC_AlarmFlag = RTC_CTRL_ALARM1HZ_MASK, /*!< Alarm flag*/ - kRTC_WakeupFlag = RTC_CTRL_WAKE1KHZ_MASK /*!< 1kHz wake-up timer flag*/ -} rtc_status_flags_t; - -/*! @brief Structure is used to hold the date and time */ -typedef struct _rtc_datetime -{ - uint16_t year; /*!< Range from 1970 to 2099.*/ - uint8_t month; /*!< Range from 1 to 12.*/ - uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ - uint8_t hour; /*!< Range from 0 to 23.*/ - uint8_t minute; /*!< Range from 0 to 59.*/ - uint8_t second; /*!< Range from 0 to 59.*/ -} rtc_datetime_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Un-gate the RTC clock and enable the RTC oscillator. - * - * @note This API should be called at the beginning of the application using the RTC driver. - * - * @param base RTC peripheral base address - */ -void RTC_Init(RTC_Type *base); - -/*! - * @brief Stop the timer and gate the RTC clock - * - * @param base RTC peripheral base address - */ -static inline void RTC_Deinit(RTC_Type *base) -{ - /* Stop the RTC timer */ - base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the module clock */ - CLOCK_DisableClock(kCLOCK_Rtc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! @}*/ - -/*! - * @name Current Time & Alarm - * @{ - */ - -/*! - * @brief Set the RTC date and time according to the given time structure. - * - * The RTC counter must be stopped prior to calling this function as writes to the RTC - * seconds register will fail if the RTC counter is running. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the date and time details to set are stored - * - * @return kStatus_Success: Success in setting the time and starting the RTC - * kStatus_InvalidArgument: Error because the datetime format is incorrect - */ -status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime); - -/*! - * @brief Get the RTC time and stores it in the given time structure. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the date and time details are stored. - */ -void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime); - -/*! - * @brief Set the RTC alarm time - * - * The function checks whether the specified alarm time is greater than the present - * time. If not, the function does not set the alarm and returns an error. - * - * @param base RTC peripheral base address - * @param alarmTime Pointer to structure where the alarm time is stored. - * - * @return kStatus_Success: success in setting the RTC alarm - * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect - * kStatus_Fail: Error because the alarm time has already passed - */ -status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime); - -/*! - * @brief Return the RTC alarm time. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the alarm date and time details are stored. - */ -void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime); - -/*! @}*/ - -/*! - * @name RTC wake-up timer (1KHZ) Enable - * @{ - */ - -/*! - * @brief Enable the RTC wake-up timer (1KHZ). - * - * After calling this function, the RTC driver will use/un-use the RTC wake-up (1KHZ) at the same time. - * - * @param base RTC peripheral base address - * @param enable Use/Un-use the RTC wake-up timer. - * - true: Use RTC wake-up timer at the same time. - * - false: Un-use RTC wake-up timer, RTC only use the normal seconds timer by default. - */ -static inline void RTC_EnableWakeupTimer(RTC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK; - } - else - { - base->CTRL &= ~RTC_CTRL_RTC1KHZ_EN_MASK; - } -} - -/*! - * @brief Get the enabled status of the RTC wake-up timer (1KHZ). - * - - * @param base RTC peripheral base address - * - * @return The enabled status of RTC wake-up timer (1KHZ). - */ -static inline uint32_t RTC_GetEnabledWakeupTimer(RTC_Type *base) -{ - return (base->CTRL & RTC_CTRL_RTC1KHZ_EN_MASK); -} - -/*! @}*/ - -/*! - * @brief Set the RTC seconds timer (1HZ) MATCH value. - * - * @param base RTC peripheral base address - * @param matchValue The value to be set into the RTC MATCH register - */ -static inline void RTC_SetSecondsTimerMatch(RTC_Type *base, uint32_t matchValue) -{ - /* Set the start match value into the default RTC seconds timer (1HZ). */ - base->MATCH = matchValue; -} - -/*! - * @brief Read actual RTC seconds timer (1HZ) MATCH value. - * - * @param base RTC peripheral base address - * - * @return The actual RTC seconds timer (1HZ) MATCH value. - */ -static inline uint32_t RTC_GetSecondsTimerMatch(RTC_Type *base) -{ - /* Read the RTC default seconds timer (1HZ) MATCH value. */ - return base->MATCH; -} - -/*! - * @brief Set the RTC seconds timer (1HZ) COUNT value. - * - * @param base RTC peripheral base address - * @param countValue The value to be loaded into the RTC COUNT register - */ -static inline void RTC_SetSecondsTimerCount(RTC_Type *base, uint32_t countValue) -{ - /* Set the start count value into the default RTC seconds timer (1HZ). */ - base->COUNT = countValue; -} - -/*! - * @brief Read the actual RTC seconds timer (1HZ) COUNT value. - * - * @param base RTC peripheral base address - * - * @return The actual RTC seconds timer (1HZ) COUNT value. - */ -static inline uint32_t RTC_GetSecondsTimerCount(RTC_Type *base) -{ - uint32_t a, b; - - /* Follow the RF document to read the RTC default seconds timer (1HZ) counter value. */ - do - { - a = base->COUNT; - b = base->COUNT; - } while (a != b); - - return b; -} - -/*! - * @brief Enable the RTC wake-up timer (1KHZ) and set countdown value to the RTC WAKE register. - * - * @param base RTC peripheral base address - * @param wakeupValue The value to be loaded into the WAKE register in RTC wake-up timer (1KHZ). - */ -static inline void RTC_SetWakeupCount(RTC_Type *base, uint16_t wakeupValue) -{ - /* Use the RTC wake-up timer (1KHZ) */ - base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK; - - /* Set the start countdown value into the RTC WAKE register */ - base->WAKE = RTC_WAKE_VAL((uint32_t)wakeupValue); -} - -/*! - * @brief Read the actual value from the WAKE register value in RTC wake-up timer (1KHZ). - * - * @param base RTC peripheral base address - * - * @return The actual value of the WAKE register value in RTC wake-up timer (1HZ). - */ -static inline uint16_t RTC_GetWakeupCount(RTC_Type *base) -{ - /* Read current wake-up countdown value */ - return (uint16_t)((base->WAKE & RTC_WAKE_VAL_MASK) >> RTC_WAKE_VAL_SHIFT); -} - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enable the wake-up timer interrupt from deep power down mode. - * - * @param base RTC peripheral base address - * @param enable Enable/Disable wake-up timer interrupt from deep power down mode. - * - true: Enable wake-up timer interrupt from deep power down mode. - * - false: Disable wake-up timer interrupt from deep power down mode. - */ -static inline void RTC_EnableWakeUpTimerInterruptFromDPD(RTC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= RTC_CTRL_WAKEDPD_EN_MASK; - } - else - { - base->CTRL &= ~RTC_CTRL_WAKEDPD_EN_MASK; - } -} - -/*! - * @brief Enable the alarm timer interrupt from deep power down mode. - * - * @param base RTC peripheral base address - * @param enable Enable/Disable alarm timer interrupt from deep power down mode. - * - true: Enable alarm timer interrupt from deep power down mode. - * - false: Disable alarm timer interrupt from deep power down mode. - */ -static inline void RTC_EnableAlarmTimerInterruptFromDPD(RTC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= RTC_CTRL_ALARMDPD_EN_MASK; - } - else - { - base->CTRL &= ~RTC_CTRL_ALARMDPD_EN_MASK; - } -} - -/*! - * @brief Enables the selected RTC interrupts. - * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableAlarmTimerInterruptFromDPD - * and RTC_EnableWakeUpTimerInterruptFromDPD - * - * @param base RTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) -{ - uint32_t reg = base->CTRL; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK); - reg |= mask; - - base->CTRL = reg; -} - -/*! - * @brief Disables the selected RTC interrupts. - * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableAlarmTimerInterruptFromDPD - * and RTC_EnableWakeUpTimerInterruptFromDPD - * - * @param base RTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) -{ - uint32_t reg = base->CTRL; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK | mask); - - base->CTRL = reg; -} - -/*! - * @brief Get the enabled RTC interrupts. - * @deprecated Do not use this function. It will be deleted in next release version. - * - * @param base RTC peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) -{ - return (base->CTRL & (RTC_CTRL_ALARMDPD_EN_MASK | RTC_CTRL_WAKEDPD_EN_MASK)); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Get the RTC status flags - * - * @param base RTC peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::rtc_status_flags_t - */ -static inline uint32_t RTC_GetStatusFlags(RTC_Type *base) -{ - return (base->CTRL & (RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK)); -} - -/*! - * @brief Clear the RTC status flags. - * - * @param base RTC peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::rtc_status_flags_t - */ -static inline void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) -{ - uint32_t reg = base->CTRL; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK); - - /* Write 1 to the flags we wish to clear */ - reg |= mask; - - base->CTRL = reg; -} - -/*! @}*/ - -/*! - * @name Timer Enable - * @{ - */ - -/*! - * @brief Enable the RTC timer counter. - * - * After calling this function, the RTC inner counter increments once a second when only using the RTC seconds timer - * (1hz), while the RTC inner wake-up timer countdown once a millisecond when using RTC wake-up timer (1KHZ) at the - * same time. RTC timer contain two timers, one is the RTC normal seconds timer, the other one is the RTC wake-up timer, - * the RTC enable bit is the master switch for the whole RTC timer, so user can use the RTC seconds (1HZ) timer - * independly, but they can't use the RTC wake-up timer (1KHZ) independently. - * - * @param base RTC peripheral base address - * @param enable Enable/Disable RTC Timer counter. - * - true: Enable RTC Timer counter. - * - false: Disable RTC Timer counter. - */ -static inline void RTC_EnableTimer(RTC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= RTC_CTRL_RTC_EN_MASK; - } - else - { - base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; - } -} - -/*! - * @brief Starts the RTC time counter. - * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableTimer - * - * After calling this function, the timer counter increments once a second provided SR[TOF] or - * SR[TIF] are not set. - * - * @param base RTC peripheral base address - */ -static inline void RTC_StartTimer(RTC_Type *base) -{ - base->CTRL |= RTC_CTRL_RTC_EN_MASK; -} - -/*! - * @brief Stops the RTC time counter. - * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableTimer - * - * RTC's seconds register can be written to only when the timer is stopped. - * - * @param base RTC peripheral base address - */ -static inline void RTC_StopTimer(RTC_Type *base) -{ - base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; -} - -/*! @}*/ - -/*! - * @brief Perform a software reset on the RTC module. - * - * This resets all RTC registers to their reset value. The bit is cleared by software explicitly clearing it. - * - * @param base RTC peripheral base address - */ -static inline void RTC_Reset(RTC_Type *base) -{ - base->CTRL |= RTC_CTRL_SWRESET_MASK; - base->CTRL &= ~RTC_CTRL_SWRESET_MASK; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_RTC_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_sctimer.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_sctimer.c deleted file mode 100644 index 4208097a8b9..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_sctimer.c +++ /dev/null @@ -1,791 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sctimer.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.sctimer" -#endif - -/*! @brief Typedef for interrupt handler. */ -typedef void (*sctimer_isr_t)(SCT_Type *base); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base SCTimer peripheral base address - * - * @return The SCTimer instance - */ -static uint32_t SCTIMER_GetInstance(SCT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to SCT bases for each instance. */ -static SCT_Type *const s_sctBases[] = SCT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to SCT clocks for each instance. */ -static const clock_ip_name_t s_sctClocks[] = SCT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET -/*! @brief Pointers to SCT resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_sctResets[] = SCT_RSTS_N; -#else -/*! @brief Pointers to SCT resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_sctResets[] = SCT_RSTS; -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/*!< @brief SCTimer event Callback function. */ -static sctimer_event_callback_t s_eventCallback[FSL_FEATURE_SCT_NUMBER_OF_EVENTS]; - -/*!< @brief Keep track of SCTimer event number */ -static uint32_t s_currentEvent; - -/*!< @brief Keep track of SCTimer state number */ -static uint32_t s_currentState; - -/*!< @brief Keep track of SCTimer unify 32-bit or low 16-bit match/capture register number. */ -static uint32_t s_currentMatch; -/*!< @brief Keep track of SCTimer high 16-bit match/capture register number. */ -static uint32_t s_currentMatchhigh; - -/*! @brief Pointer to SCTimer IRQ handler */ -static sctimer_isr_t s_sctimerIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t SCTIMER_GetInstance(SCT_Type *base) -{ - uint32_t instance; - uint32_t sctArrayCount = (sizeof(s_sctBases) / sizeof(s_sctBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < sctArrayCount; instance++) - { - if (s_sctBases[instance] == base) - { - break; - } - } - - assert(instance < sctArrayCount); - - return instance; -} - -/*! - * brief Ungates the SCTimer clock and configures the peripheral for basic operation. - * - * note This API should be called at the beginning of the application using the SCTimer driver. - * - * param base SCTimer peripheral base address - * param config Pointer to the user configuration structure. - * - * return kStatus_Success indicates success; Else indicates failure. - */ -status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config) -{ - assert(NULL != config); - - uint32_t i; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the SCTimer clock*/ - CLOCK_EnableClock(s_sctClocks[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_sctResets[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - - /* Setup the counter operation. For Current Driver interface SCTIMER_Init don't know detail - * frequency of input clock, but User know it. So the INSYNC have to set by user level. */ - base->CONFIG = SCT_CONFIG_CKSEL(config->clockSelect) | SCT_CONFIG_CLKMODE(config->clockMode) | - SCT_CONFIG_UNIFY(config->enableCounterUnify) | SCT_CONFIG_INSYNC(config->inputsync); - - /* Write to the control register, keep the counters halted. */ - base->CTRL = - SCT_CTRL_BIDIR_L(config->enableBidirection_l) | SCT_CTRL_PRE_L(config->prescale_l) | SCT_CTRL_HALT_L_MASK; - /* Clear the counter after changing the PRE value. */ - base->CTRL |= SCT_CTRL_CLRCTR_L_MASK; - - if (!(config->enableCounterUnify)) - { - base->CTRL |= - SCT_CTRL_BIDIR_H(config->enableBidirection_h) | SCT_CTRL_PRE_H(config->prescale_h) | SCT_CTRL_HALT_H_MASK; - base->CTRL |= SCT_CTRL_CLRCTR_H_MASK; - } - - /* Initial state of channel output */ - base->OUTPUT = config->outInitState; - - /* Clear the global variables */ - s_currentEvent = 0U; - s_currentState = 0U; - s_currentMatch = 0U; - s_currentMatchhigh = 0U; - - /* Clear the callback array */ - for (i = 0; i < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) - { - s_eventCallback[i] = NULL; - } - - /* Save interrupt handler */ - s_sctimerIsr = SCTIMER_EventHandleIRQ; - - return kStatus_Success; -} - -/*! - * brief Gates the SCTimer clock. - * - * param base SCTimer peripheral base address - */ -void SCTIMER_Deinit(SCT_Type *base) -{ - /* Halt the counters */ - base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the SCTimer clock*/ - CLOCK_DisableClock(s_sctClocks[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Fills in the SCTimer configuration structure with the default settings. - * - * The default values are: - * code - * config->enableCounterUnify = true; - * config->clockMode = kSCTIMER_System_ClockMode; - * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - * config->enableBidirection_l = false; - * config->enableBidirection_h = false; - * config->prescale_l = 0U; - * config->prescale_h = 0U; - * config->outInitState = 0U; - * config->inputsync = 0xFU; - * endcode - * param config Pointer to the user configuration structure. - */ -void SCTIMER_GetDefaultConfig(sctimer_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* SCT operates as a unified 32-bit counter */ - config->enableCounterUnify = true; - /* System clock clocks the entire SCT module */ - config->clockMode = kSCTIMER_System_ClockMode; - /* This is used only by certain clock modes */ - config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - /* Up count mode only for the unified counter */ - config->enableBidirection_l = false; - /* Up count mode only for Counte_H */ - config->enableBidirection_h = false; - /* Prescale factor of 1 */ - config->prescale_l = 0U; - /* Prescale factor of 1 for Counter_H*/ - config->prescale_h = 0U; - /* Clear outputs */ - config->outInitState = 0U; - /* Default value is 0xFU, it can be clear as 0 when speical conditions met. - * Condition can be clear as 0: (for all Clock Modes): - * (1) The corresponding input is already synchronous to the SCTimer/PWM clock. - * (2) The SCTimer/PWM clock frequency does not exceed 100 MHz. - * Note: The SCTimer/PWM clock is the bus/system clock for CKMODE 0-2 or asynchronous input - * clock for CKMODE3. - * Another condition can be clear as 0: (for CKMODE2 only) - * (1) The corresponding input is synchronous to the designated CKMODE2 input clock. - * (2) The CKMODE2 input clock frequency is less than one-third the frequency of the bus/system clock. - * Default value set as 0U, input0~input3 are set as bypasses. */ - config->inputsync = 0xFU; -} - -/*! - * brief Configures the PWM signal parameters. - * - * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This - * function will create 2 events; one of the events will trigger on match with the pulse value - * and the other will trigger when the counter matches the PWM period. The PWM period event is - * also used as a limit event to reset the counter or change direction. Both events are enabled - * for the same state. The state number can be retrieved by calling the function - * SCTIMER_GetCurrentStateNumber(). - * The counter is set to operate as one 32-bit counter (unify bit is set to 1). - * The counter operates in bi-directional mode when generating a center-aligned PWM. - * - * note When setting PWM output from multiple output pins, they all should use the same PWM mode - * i.e all PWM's should be either edge-aligned or center-aligned. - * When using this API, the PWM signal frequency of all the initialized channels must be the same. - * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the - * API's pwmFreq_Hz. - * - * param base SCTimer peripheral base address - * param pwmParams PWM parameters to configure the output - * param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t - * param pwmFreq_Hz PWM signal frequency in Hz - * param srcClock_Hz SCTimer counter clock in Hz - * param event Pointer to a variable where the PWM period event number is stored - * - * return kStatus_Success on success - * kStatus_Fail If we have hit the limit in terms of number of events created or if - * an incorrect PWM dutycylce is passed in. - */ -status_t SCTIMER_SetupPwm(SCT_Type *base, - const sctimer_pwm_signal_param_t *pwmParams, - sctimer_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - uint32_t *event) -{ - assert(NULL != pwmParams); - assert(0U != srcClock_Hz); - assert(0U != pwmFreq_Hz); - assert((uint32_t)pwmParams->output < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - - /* If we do not have enough events available (this function will create two events), - * the function will return fail. - */ - status_t status = kStatus_Fail; - status_t status2; - uint32_t period, pulsePeriod = 0; - uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1U); - uint32_t periodEvent = 0, pulseEvent = 0; - uint32_t reg; - - if ((s_currentEvent + 2U) <= (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS) - { - /* Use bi-directional mode for center-aligned PWM */ - if (mode == kSCTIMER_CenterAlignedPwm) - { - base->CTRL |= SCT_CTRL_BIDIR_L_MASK; - } - - /* Calculate PWM period match value */ - if (mode == kSCTIMER_EdgeAlignedPwm) - { - period = (sctClock / pwmFreq_Hz) - 1U; - } - else - { - period = sctClock / (pwmFreq_Hz * 2U); - } - - /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ - if (pwmParams->dutyCyclePercent >= 100U) - { - pulsePeriod = period + 2U; - } - else - { - pulsePeriod = (uint32_t)(((uint64_t)period * pwmParams->dutyCyclePercent) / 100U); - } - - /* Schedule an event when we reach the PWM period */ - status = - SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, period, 0, kSCTIMER_Counter_U, &periodEvent); - - /* Schedule an event when we reach the pulse width */ - status2 = SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, pulsePeriod, 0, kSCTIMER_Counter_U, - &pulseEvent); - - if ((kStatus_Success == status) && (kStatus_Success == status2)) - { - /* Reset the counter when we reach the PWM period */ - SCTIMER_SetupCounterLimitAction(base, kSCTIMER_Counter_U, periodEvent); - - /* Return the period event to the user */ - *event = periodEvent; - - /* For high-true level */ - if ((uint32_t)pwmParams->level == (uint32_t)kSCTIMER_HighTrue) - { - if (mode == kSCTIMER_EdgeAlignedPwm) - { - /* Set the initial output level to low which is the inactive state */ - base->OUTPUT &= ~(1UL << (uint32_t)pwmParams->output); - /* Set the output when we reach the PWM period */ - SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, periodEvent); - /* Clear the output when we reach the PWM pulse value */ - SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, pulseEvent); - } - else - { - /* Set the initial output level to high which is the inactive state */ - base->OUTPUT |= (1UL << (uint32_t)pwmParams->output); - /* Clear the output when we reach the PWM pulse event */ - SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, pulseEvent); - /* Reverse output when down counting */ - reg = base->OUTPUTDIRCTRL; - reg &= ~((uint32_t)SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2U * (uint32_t)pwmParams->output)); - reg |= (1UL << (2U * (uint32_t)pwmParams->output)); - base->OUTPUTDIRCTRL = reg; - } - } - /* For low-true level */ - else - { - if (mode == kSCTIMER_EdgeAlignedPwm) - { - /* Set the initial output level to high which is the inactive state */ - base->OUTPUT |= (1UL << (uint32_t)pwmParams->output); - /* Clear the output when we reach the PWM period */ - SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, periodEvent); - /* Set the output when we reach the PWM pulse value */ - SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, pulseEvent); - } - else - { - /* Set the initial output level to low which is the inactive state */ - base->OUTPUT &= ~(1UL << (uint32_t)pwmParams->output); - /* Set the output when we reach the PWM pulse event */ - SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, pulseEvent); - /* Reverse output when down counting */ - reg = base->OUTPUTDIRCTRL; - reg &= ~((uint32_t)SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2U * (uint32_t)pwmParams->output)); - reg |= (1UL << (2U * (uint32_t)pwmParams->output)); - base->OUTPUTDIRCTRL = reg; - } - } - } - else - { - status = kStatus_Fail; - } - } - - return status; -} - -/*! - * brief Updates the duty cycle of an active PWM signal. - * - * Before calling this function, the counter is set to operate as one 32-bit counter (unify bit is set to 1). - * - * param base SCTimer peripheral base address - * param output The output to configure - * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 - * param event Event number associated with this PWM signal. This was returned to the user by the - * function SCTIMER_SetupPwm(). - */ -void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event) - -{ - assert(dutyCyclePercent <= 100U); - assert((uint32_t)output < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - - uint32_t periodMatchReg, pulseMatchReg; - uint32_t pulsePeriod = 0, period; - - /* Retrieve the match register number for the PWM period */ - periodMatchReg = base->EV[event].CTRL & SCT_EV_CTRL_MATCHSEL_MASK; - - /* Retrieve the match register number for the PWM pulse period */ - pulseMatchReg = base->EV[event + 1U].CTRL & SCT_EV_CTRL_MATCHSEL_MASK; - - period = base->MATCH[periodMatchReg]; - - /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ - if (dutyCyclePercent >= 100U) - { - pulsePeriod = period + 2U; - } - else - { - pulsePeriod = (uint32_t)(((uint64_t)period * dutyCyclePercent) / 100U); - } - - /* Stop the counter before updating match register */ - SCTIMER_StopTimer(base, (uint32_t)kSCTIMER_Counter_U); - - /* Update dutycycle */ - base->MATCH[pulseMatchReg] = SCT_MATCH_MATCHn_L(pulsePeriod); - base->MATCHREL[pulseMatchReg] = SCT_MATCHREL_RELOADn_L(pulsePeriod); - - /* Restart the counter */ - SCTIMER_StartTimer(base, (uint32_t)kSCTIMER_Counter_U); -} - -/*! - * brief Create an event that is triggered on a match or IO and schedule in current state. - * - * This function will configure an event using the options provided by the user. If the event type uses - * the counter match, then the function will set the user provided match value into a match register - * and put this match register number into the event control register. - * The event is enabled for the current state and the event number is increased by one at the end. - * The function returns the event number; this event number can be used to configure actions to be - * done when this event is triggered. - * - * param base SCTimer peripheral base address - * param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t - * param matchValue The match value that will be programmed to a match register - * param whichIO The input or output that will be involved in event triggering. This field - * is ignored if the event type is "match only" - * param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * param event Pointer to a variable where the new event number is stored - * - * return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of events created or - if we have reached the limit in terms of number of match registers - */ -status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, - sctimer_event_t howToMonitor, - uint32_t matchValue, - uint32_t whichIO, - sctimer_counter_t whichCounter, - uint32_t *event) -{ - uint32_t combMode = (((uint32_t)howToMonitor & SCT_EV_CTRL_COMBMODE_MASK) >> SCT_EV_CTRL_COMBMODE_SHIFT); - uint32_t currentCtrlVal = (uint32_t)howToMonitor; - status_t status = kStatus_Success; - uint32_t temp = 0; - - if (s_currentEvent < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS) - { - if (2U == combMode) - { - base->EV[s_currentEvent].CTRL = currentCtrlVal | SCT_EV_CTRL_IOSEL(whichIO); - } - else - { - if ((0U == combMode) || (3U == combMode)) - { - currentCtrlVal |= SCT_EV_CTRL_IOSEL(whichIO); - } - - if ((kSCTIMER_Counter_L == whichCounter) && (0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) - { - if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatch); - - /* Use Counter_L bits if user wants to setup the Low counter */ - base->MATCH_ACCESS16BIT[s_currentMatch].MATCHL = (uint16_t)matchValue; - base->MATCHREL_ACCESS16BIT[s_currentMatch].MATCHRELL = (uint16_t)matchValue; - base->EV[s_currentEvent].CTRL = currentCtrlVal; - - /* Increment the match register number */ - s_currentMatch++; - } - else - { - /* An error would occur if we have hit the limit in terms of number of match registers */ - status = kStatus_Fail; - } - } - else if ((kSCTIMER_Counter_H == whichCounter) && (0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) - { - if (s_currentMatchhigh < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatchhigh); - - /* Use Counter_H bits if user wants to setup the High counter */ - currentCtrlVal |= SCT_EV_CTRL_HEVENT(1U); - temp = base->MATCH_ACCESS16BIT[s_currentMatchhigh].MATCHL; - base->MATCH[s_currentMatchhigh] = temp | (matchValue << 16U); - temp = base->MATCHREL_ACCESS16BIT[s_currentMatchhigh].MATCHRELL; - base->MATCHREL[s_currentMatchhigh] = temp | (matchValue << 16U); - - base->EV[s_currentEvent].CTRL = currentCtrlVal; - /* Increment the match register number */ - s_currentMatchhigh++; - } - else - { - /* An error would occur if we have hit the limit in terms of number of match registers */ - status = kStatus_Fail; - } - } - else if ((kSCTIMER_Counter_U == whichCounter) && (0U != (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) - { - if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - /* Use Counter_L bits if counter is operating in 32-bit mode */ - currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatch); - - base->MATCH[s_currentMatch] = matchValue; - base->MATCHREL[s_currentMatch] = matchValue; - base->EV[s_currentEvent].CTRL = currentCtrlVal; - - /* Increment the match register number */ - s_currentMatch++; - } - else - { - /* An error would occur if we have hit the limit in terms of number of match registers */ - status = kStatus_Fail; - } - } - else - { - /* The used counter must match the CONFIG[UNIFY] bit selection */ - status = kStatus_Fail; - } - } - - if (kStatus_Success == status) - { - /* Enable the event in the current state */ - base->EV[s_currentEvent].STATE = (1UL << s_currentState); - - /* Return the event number */ - *event = s_currentEvent; - - /* Increment the event number */ - s_currentEvent++; - } - } - else - { - /* An error would occur if we have hit the limit in terms of number of events created */ - status = kStatus_Fail; - } - - return status; -} - -/*! - * brief Enable an event in the current state. - * - * This function will allow the event passed in to trigger in the current state. The event must - * be created earlier by either calling the function SCTIMER_SetupPwm() or function - * SCTIMER_CreateAndScheduleEvent() . - * - * param base SCTimer peripheral base address - * param event Event number to enable in the current state - * - */ -void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event) -{ - /* Enable event in the current state */ - base->EV[event].STATE |= (1UL << s_currentState); -} - -/*! - * brief Increase the state by 1 - * - * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new - * state. - * - * param base SCTimer peripheral base address - * - * return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of states used - - */ -status_t SCTIMER_IncreaseState(SCT_Type *base) -{ - status_t status = kStatus_Success; - - /* Return an error if we have hit the limit in terms of states used */ - if (s_currentState >= (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES) - { - status = kStatus_Fail; - } - else - { - s_currentState++; - } - - return status; -} - -/*! - * brief Provides the current state - * - * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). - * - * param base SCTimer peripheral base address - * - * return The current state - */ -uint32_t SCTIMER_GetCurrentState(SCT_Type *base) -{ - return s_currentState; -} - -/*! - * brief Toggle the output level. - * - * This change in the output level is triggered by the event number that is passed in by the user. - * - * param base SCTimer peripheral base address - * param whichIO The output to toggle - * param event Event number that will trigger the output change - */ -void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - uint32_t reg; - - /* Set the same event to set and clear the output */ - base->OUT[whichIO].CLR |= (1UL << event); - base->OUT[whichIO].SET |= (1UL << event); - - /* Set the conflict resolution to toggle output */ - reg = base->RES; - reg &= ~(((uint32_t)SCT_RES_O0RES_MASK) << (2U * whichIO)); - reg |= ((uint32_t)(kSCTIMER_ResolveToggle)) << (2U * whichIO); - base->RES = reg; -} - -/*! - * brief Setup capture of the counter value on trigger of a selected event - * - * param base SCTimer peripheral base address - * param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * param captureRegister Pointer to a variable where the capture register number will be returned. User - * can read the captured value from this register when the specified event is triggered. - * param event Event number that will trigger the capture - * - * return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of match/capture registers available - */ -status_t SCTIMER_SetupCaptureAction(SCT_Type *base, - sctimer_counter_t whichCounter, - uint32_t *captureRegister, - uint32_t event) -{ - status_t status; - uint32_t temp = 0; - - if ((kSCTIMER_Counter_L == whichCounter) || (kSCTIMER_Counter_U == whichCounter)) - { - if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - /* Set the bit to enable event */ - base->CAPCTRL_ACCESS16BIT[s_currentMatch].CAPCTRLL |= SCT_CAPCTRLL_CAPCTRLL(1UL << event); - - /* Set this resource to be a capture rather than match */ - base->REGMODE_ACCESS16BIT.REGMODEL |= SCT_REGMODEL_REGMODEL(1UL << s_currentMatch); - - /* Return the match register number */ - *captureRegister = s_currentMatch; - - /* Increase the match register number */ - s_currentMatch++; - - status = kStatus_Success; - } - else - { - /* Return an error if we have hit the limit in terms of number of capture/match registers used */ - status = kStatus_Fail; - } - } - else - { - if (s_currentMatchhigh < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - /* Set bit to enable event */ - temp = base->CAPCTRL_ACCESS16BIT[s_currentMatchhigh].CAPCTRLL; - base->CAPCTRL[s_currentMatchhigh] = temp | ((uint32_t)((uint32_t)(1UL << event) << 16U) & 0xFFFF000U); - /* Set this resource to be a capture rather than match */ - temp = base->REGMODE_ACCESS16BIT.REGMODEL; - base->REGMODE = temp | ((uint32_t)((uint32_t)(1UL << s_currentMatchhigh) << 16U) & 0xFFFF000U); - - /* Return the match register number */ - *captureRegister = s_currentMatchhigh; - - /* Increase the match register number */ - s_currentMatchhigh++; - - status = kStatus_Success; - } - else - { - /* Return an error if we have hit the limit in terms of number of capture/match registers used */ - status = kStatus_Fail; - } - } - - return status; -} - -/*! - * brief Receive noticification when the event trigger an interrupt. - * - * If the interrupt for the event is enabled by the user, then a callback can be registered - * which will be invoked when the event is triggered - * - * param base SCTimer peripheral base address - * param event Event number that will trigger the interrupt - * param callback Function to invoke when the event is triggered - */ - -void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event) -{ - s_eventCallback[event] = callback; -} - -/*! - * brief SCTimer interrupt handler. - * - * param base SCTimer peripheral base address. - */ -void SCTIMER_EventHandleIRQ(SCT_Type *base) -{ - uint32_t eventFlag = SCT0->EVFLAG; - /* Only clear the flags whose interrupt field is enabled */ - uint32_t clearFlag = (eventFlag & SCT0->EVEN); - uint32_t mask = eventFlag; - uint32_t i; - - /* Invoke the callback for certain events */ - for (i = 0; i < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) - { - if ((mask & 0x1U) != 0U) - { - if (s_eventCallback[i] != NULL) - { - s_eventCallback[i](); - } - } - mask >>= 1UL; - - if (0U == mask) - { - /* All events have been handled. */ - break; - } - } - - /* Clear event interrupt flag */ - SCT0->EVFLAG = clearFlag; -} - -void SCT0_DriverIRQHandler(void); -void SCT0_DriverIRQHandler(void) -{ - s_sctimerIsr(SCT0); - SDK_ISR_EXIT_BARRIER; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_sctimer.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_sctimer.h deleted file mode 100644 index 283a5b7019f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_sctimer.h +++ /dev/null @@ -1,1258 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SCTIMER_H_ -#define _FSL_SCTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup sctimer - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 4, 4)) /*!< Version */ -/*@}*/ - -#ifndef SCT_EV_STATE_STATEMSKn -#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(x) & (1UL << FSL_FEATURE_SCT_NUMBER_OF_STATES) - 1UL)) -#endif - -/*! @brief SCTimer PWM operation modes */ -typedef enum _sctimer_pwm_mode -{ - kSCTIMER_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */ - kSCTIMER_CenterAlignedPwm /*!< Center-aligned PWM */ -} sctimer_pwm_mode_t; - -/*! @brief SCTimer counters type. */ -typedef enum _sctimer_counter -{ - kSCTIMER_Counter_L = (1U << 0), /*!< 16-bit Low counter. */ - kSCTIMER_Counter_H = (1U << 1), /*!< 16-bit High counter. */ - kSCTIMER_Counter_U = (1U << 2), /*!< 32-bit Unified counter. */ -} sctimer_counter_t; - -/*! @brief List of SCTimer input pins */ -typedef enum _sctimer_input -{ - kSCTIMER_Input_0 = 0U, /*!< SCTIMER input 0 */ - kSCTIMER_Input_1, /*!< SCTIMER input 1 */ - kSCTIMER_Input_2, /*!< SCTIMER input 2 */ - kSCTIMER_Input_3, /*!< SCTIMER input 3 */ - kSCTIMER_Input_4, /*!< SCTIMER input 4 */ - kSCTIMER_Input_5, /*!< SCTIMER input 5 */ - kSCTIMER_Input_6, /*!< SCTIMER input 6 */ - kSCTIMER_Input_7 /*!< SCTIMER input 7 */ -} sctimer_input_t; - -/*! @brief List of SCTimer output pins */ -typedef enum _sctimer_out -{ - kSCTIMER_Out_0 = 0U, /*!< SCTIMER output 0*/ - kSCTIMER_Out_1, /*!< SCTIMER output 1 */ - kSCTIMER_Out_2, /*!< SCTIMER output 2 */ - kSCTIMER_Out_3, /*!< SCTIMER output 3 */ - kSCTIMER_Out_4, /*!< SCTIMER output 4 */ - kSCTIMER_Out_5, /*!< SCTIMER output 5 */ - kSCTIMER_Out_6, /*!< SCTIMER output 6 */ - kSCTIMER_Out_7, /*!< SCTIMER output 7 */ - kSCTIMER_Out_8, /*!< SCTIMER output 8 */ - kSCTIMER_Out_9 /*!< SCTIMER output 9 */ -} sctimer_out_t; - -/*! @brief SCTimer PWM output pulse mode: high-true, low-true or no output */ -typedef enum _sctimer_pwm_level_select -{ - kSCTIMER_LowTrue = 0U, /*!< Low true pulses */ - kSCTIMER_HighTrue /*!< High true pulses */ -} sctimer_pwm_level_select_t; - -/*! @brief Options to configure a SCTimer PWM signal */ -typedef struct _sctimer_pwm_signal_param -{ - sctimer_out_t output; /*!< The output pin to use to generate the PWM signal */ - sctimer_pwm_level_select_t level; /*!< PWM output active level select. */ - uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 - 0 = always inactive signal (0% duty cycle) - 100 = always active signal (100% duty cycle).*/ -} sctimer_pwm_signal_param_t; - -/*! @brief SCTimer clock mode options */ -typedef enum _sctimer_clock_mode -{ - kSCTIMER_System_ClockMode = 0U, /*!< System Clock Mode */ - kSCTIMER_Sampled_ClockMode, /*!< Sampled System Clock Mode */ - kSCTIMER_Input_ClockMode, /*!< SCT Input Clock Mode */ - kSCTIMER_Asynchronous_ClockMode /*!< Asynchronous Mode */ -} sctimer_clock_mode_t; - -/*! @brief SCTimer clock select options */ -typedef enum _sctimer_clock_select -{ - kSCTIMER_Clock_On_Rise_Input_0 = 0U, /*!< Rising edges on input 0 */ - kSCTIMER_Clock_On_Fall_Input_0, /*!< Falling edges on input 0 */ - kSCTIMER_Clock_On_Rise_Input_1, /*!< Rising edges on input 1 */ - kSCTIMER_Clock_On_Fall_Input_1, /*!< Falling edges on input 1 */ - kSCTIMER_Clock_On_Rise_Input_2, /*!< Rising edges on input 2 */ - kSCTIMER_Clock_On_Fall_Input_2, /*!< Falling edges on input 2 */ - kSCTIMER_Clock_On_Rise_Input_3, /*!< Rising edges on input 3 */ - kSCTIMER_Clock_On_Fall_Input_3, /*!< Falling edges on input 3 */ - kSCTIMER_Clock_On_Rise_Input_4, /*!< Rising edges on input 4 */ - kSCTIMER_Clock_On_Fall_Input_4, /*!< Falling edges on input 4 */ - kSCTIMER_Clock_On_Rise_Input_5, /*!< Rising edges on input 5 */ - kSCTIMER_Clock_On_Fall_Input_5, /*!< Falling edges on input 5 */ - kSCTIMER_Clock_On_Rise_Input_6, /*!< Rising edges on input 6 */ - kSCTIMER_Clock_On_Fall_Input_6, /*!< Falling edges on input 6 */ - kSCTIMER_Clock_On_Rise_Input_7, /*!< Rising edges on input 7 */ - kSCTIMER_Clock_On_Fall_Input_7 /*!< Falling edges on input 7 */ -} sctimer_clock_select_t; - -/*! - * @brief SCTimer output conflict resolution options. - * - * Specifies what action should be taken if multiple events dictate that a given output should be - * both set and cleared at the same time - */ -typedef enum _sctimer_conflict_resolution -{ - kSCTIMER_ResolveNone = 0U, /*!< No change */ - kSCTIMER_ResolveSet, /*!< Set output */ - kSCTIMER_ResolveClear, /*!< Clear output */ - kSCTIMER_ResolveToggle /*!< Toggle output */ -} sctimer_conflict_resolution_t; - -/*! @brief List of SCTimer event generation active direction when the counters are operating in BIDIR mode. */ -typedef enum _sctimer_event_active_direction -{ - kSCTIMER_ActiveIndependent = 0U, /*!< This event is triggered regardless of the count direction. */ - kSCTIMER_ActiveInCountUp, /*!< This event is triggered only during up-counting when BIDIR = 1. */ - kSCTIMER_ActiveInCountDown /*!< This event is triggered only during down-counting when BIDIR = 1. */ -} sctimer_event_active_direction_t; - -/*! @brief List of SCTimer event types */ -typedef enum _sctimer_event -{ - kSCTIMER_InputLowOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_MatchEventOnly = - (1 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_InputLowEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_InputLowAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT) -} sctimer_event_t; - -/*! @brief SCTimer callback typedef. */ -typedef void (*sctimer_event_callback_t)(void); - -/*! @brief List of SCTimer interrupts */ -typedef enum _sctimer_interrupt_enable -{ - kSCTIMER_Event0InterruptEnable = (1U << 0), /*!< Event 0 interrupt */ - kSCTIMER_Event1InterruptEnable = (1U << 1), /*!< Event 1 interrupt */ - kSCTIMER_Event2InterruptEnable = (1U << 2), /*!< Event 2 interrupt */ - kSCTIMER_Event3InterruptEnable = (1U << 3), /*!< Event 3 interrupt */ - kSCTIMER_Event4InterruptEnable = (1U << 4), /*!< Event 4 interrupt */ - kSCTIMER_Event5InterruptEnable = (1U << 5), /*!< Event 5 interrupt */ - kSCTIMER_Event6InterruptEnable = (1U << 6), /*!< Event 6 interrupt */ - kSCTIMER_Event7InterruptEnable = (1U << 7), /*!< Event 7 interrupt */ - kSCTIMER_Event8InterruptEnable = (1U << 8), /*!< Event 8 interrupt */ - kSCTIMER_Event9InterruptEnable = (1U << 9), /*!< Event 9 interrupt */ - kSCTIMER_Event10InterruptEnable = (1U << 10), /*!< Event 10 interrupt */ - kSCTIMER_Event11InterruptEnable = (1U << 11), /*!< Event 11 interrupt */ - kSCTIMER_Event12InterruptEnable = (1U << 12), /*!< Event 12 interrupt */ -} sctimer_interrupt_enable_t; - -/*! @brief List of SCTimer flags */ -typedef enum _sctimer_status_flags -{ - kSCTIMER_Event0Flag = (1U << 0), /*!< Event 0 Flag */ - kSCTIMER_Event1Flag = (1U << 1), /*!< Event 1 Flag */ - kSCTIMER_Event2Flag = (1U << 2), /*!< Event 2 Flag */ - kSCTIMER_Event3Flag = (1U << 3), /*!< Event 3 Flag */ - kSCTIMER_Event4Flag = (1U << 4), /*!< Event 4 Flag */ - kSCTIMER_Event5Flag = (1U << 5), /*!< Event 5 Flag */ - kSCTIMER_Event6Flag = (1U << 6), /*!< Event 6 Flag */ - kSCTIMER_Event7Flag = (1U << 7), /*!< Event 7 Flag */ - kSCTIMER_Event8Flag = (1U << 8), /*!< Event 8 Flag */ - kSCTIMER_Event9Flag = (1U << 9), /*!< Event 9 Flag */ - kSCTIMER_Event10Flag = (1U << 10), /*!< Event 10 Flag */ - kSCTIMER_Event11Flag = (1U << 11), /*!< Event 11 Flag */ - kSCTIMER_Event12Flag = (1U << 12), /*!< Event 12 Flag */ - kSCTIMER_BusErrorLFlag = - (1U << SCT_CONFLAG_BUSERRL_SHIFT), /*!< Bus error due to write when L counter was not halted */ - kSCTIMER_BusErrorHFlag = - (int)(1U << SCT_CONFLAG_BUSERRH_SHIFT) /*!< Bus error due to write when H counter was not halted */ -} sctimer_status_flags_t; - -/*! - * @brief SCTimer configuration structure - * - * This structure holds the configuration settings for the SCTimer peripheral. To initialize this - * structure to reasonable defaults, call the SCTMR_GetDefaultConfig() function and pass a - * pointer to the configuration structure instance. - * - * The configuration structure can be made constant so as to reside in flash. - */ -typedef struct _sctimer_config -{ - bool enableCounterUnify; /*!< true: SCT operates as a unified 32-bit counter; - false: SCT operates as two 16-bit counters. - User can use the 16-bit low counter and the 16-bit high counters at the - same time; for Hardware limit, user can not use unified 32-bit counter - and any 16-bit low/high counter at the same time. */ - sctimer_clock_mode_t clockMode; /*!< SCT clock mode value */ - sctimer_clock_select_t clockSelect; /*!< SCT clock select value */ - bool enableBidirection_l; /*!< true: Up-down count mode for the L or unified counter - false: Up count mode only for the L or unified counter */ - bool enableBidirection_h; /*!< true: Up-down count mode for the H or unified counter - false: Up count mode only for the H or unified counter. - This field is used only if the enableCounterUnify is set - to false */ - uint8_t prescale_l; /*!< Prescale value to produce the L or unified counter clock */ - uint8_t prescale_h; /*!< Prescale value to produce the H counter clock. - This field is used only if the enableCounterUnify is set - to false */ - uint8_t outInitState; /*!< Defines the initial output value */ - uint8_t inputsync; /*!< SCT INSYNC value, INSYNC field in the CONFIG register, from bit9 to bit 16. - it is used to define synchronization for input N: - bit 9 = input 0 - bit 10 = input 1 - bit 11 = input 2 - bit 12 = input 3 - All other bits are reserved (bit13 ~bit 16). - How User to set the the value for the member inputsync. - IE: delay for input0, and input 1, bypasses for input 2 and input 3 - MACRO definition in user level. - \#define INPUTSYNC0 (0U) - \#define INPUTSYNC1 (1U) - \#define INPUTSYNC2 (2U) - \#define INPUTSYNC3 (3U) - User Code. - sctimerInfo.inputsync = (1 << INPUTSYNC2) | (1 << INPUTSYNC3); */ -} sctimer_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the SCTimer clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the SCTimer driver. - * - * @param base SCTimer peripheral base address - * @param config Pointer to the user configuration structure. - * - * @return kStatus_Success indicates success; Else indicates failure. - */ -status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config); - -/*! - * @brief Gates the SCTimer clock. - * - * @param base SCTimer peripheral base address - */ -void SCTIMER_Deinit(SCT_Type *base); - -/*! - * @brief Fills in the SCTimer configuration structure with the default settings. - * - * The default values are: - * @code - * config->enableCounterUnify = true; - * config->clockMode = kSCTIMER_System_ClockMode; - * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - * config->enableBidirection_l = false; - * config->enableBidirection_h = false; - * config->prescale_l = 0U; - * config->prescale_h = 0U; - * config->outInitState = 0U; - * config->inputsync = 0xFU; - * @endcode - * @param config Pointer to the user configuration structure. - */ -void SCTIMER_GetDefaultConfig(sctimer_config_t *config); - -/*! @}*/ - -/*! - * @name PWM setup operations - * @{ - */ - -/*! - * @brief Configures the PWM signal parameters. - * - * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This - * function will create 2 events; one of the events will trigger on match with the pulse value - * and the other will trigger when the counter matches the PWM period. The PWM period event is - * also used as a limit event to reset the counter or change direction. Both events are enabled - * for the same state. The state number can be retrieved by calling the function - * SCTIMER_GetCurrentStateNumber(). - * The counter is set to operate as one 32-bit counter (unify bit is set to 1). - * The counter operates in bi-directional mode when generating a center-aligned PWM. - * - * @note When setting PWM output from multiple output pins, they all should use the same PWM mode - * i.e all PWM's should be either edge-aligned or center-aligned. - * When using this API, the PWM signal frequency of all the initialized channels must be the same. - * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the - * API's pwmFreq_Hz. - * - * @param base SCTimer peripheral base address - * @param pwmParams PWM parameters to configure the output - * @param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz SCTimer counter clock in Hz - * @param event Pointer to a variable where the PWM period event number is stored - * - * @return kStatus_Success on success - * kStatus_Fail If we have hit the limit in terms of number of events created or if - * an incorrect PWM dutycylce is passed in. - */ -status_t SCTIMER_SetupPwm(SCT_Type *base, - const sctimer_pwm_signal_param_t *pwmParams, - sctimer_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - uint32_t *event); - -/*! - * @brief Updates the duty cycle of an active PWM signal. - * - * Before calling this function, the counter is set to operate as one 32-bit counter (unify bit is set to 1). - * - * @param base SCTimer peripheral base address - * @param output The output to configure - * @param dutyCyclePercent New PWM pulse width; the value should be between 1 to 100 - * @param event Event number associated with this PWM signal. This was returned to the user by the - * function SCTIMER_SetupPwm(). - */ -void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event); - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline void SCTIMER_EnableInterrupts(SCT_Type *base, uint32_t mask) -{ - base->EVEN |= mask; -} - -/*! - * @brief Disables the selected SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline void SCTIMER_DisableInterrupts(SCT_Type *base, uint32_t mask) -{ - base->EVEN &= ~mask; -} - -/*! - * @brief Gets the enabled SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline uint32_t SCTIMER_GetEnabledInterrupts(SCT_Type *base) -{ - return (base->EVEN & 0xFFFFU); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the SCTimer status flags. - * - * @param base SCTimer peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::sctimer_status_flags_t - */ -static inline uint32_t SCTIMER_GetStatusFlags(SCT_Type *base) -{ - uint32_t statusFlags = 0; - - /* Add the recorded events */ - statusFlags = (base->EVFLAG & 0xFFFFU); - - /* Add bus error flags */ - statusFlags |= (base->CONFLAG & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); - - return statusFlags; -} - -/*! - * @brief Clears the SCTimer status flags. - * - * @param base SCTimer peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::sctimer_status_flags_t - */ -static inline void SCTIMER_ClearStatusFlags(SCT_Type *base, uint32_t mask) -{ - /* Write to the flag registers */ - base->EVFLAG = (mask & 0xFFFFU); - base->CONFLAG = (mask & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); -} - -/*! @}*/ - -/*! - * @name Counter Start and Stop - * @{ - */ - -/*! - * @brief Starts the SCTimer counter. - * - * @note In 16-bit mode, we can enable both Counter_L and Counter_H, In 32-bit mode, we only can select Counter_U. - * - * @param base SCTimer peripheral base address - * @param countertoStart The SCTimer counters to enable. This is a logical OR of members of the - * enumeration ::sctimer_counter_t. - */ -static inline void SCTIMER_StartTimer(SCT_Type *base, uint32_t countertoStart) -{ - switch (countertoStart) - { - case (uint32_t)kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_L bit when user wants to start the Low counter */ - base->CTRL_ACCESS16BIT.CTRLL &= ~((uint16_t)SCT_CTRLL_HALT_L_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_H bit when user wants to start the High counter */ - base->CTRL_ACCESS16BIT.CTRLH &= ~((uint16_t)SCT_CTRLH_HALT_H_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_L | (uint32_t)kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_L/HALT_H bit when user wants to H counter and L counter at same time */ - base->CTRL &= ~(SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_L bit when the counter is operating in 32-bit mode (unify counter). */ - base->CTRL &= ~(SCT_CTRL_HALT_L_MASK); - break; - - default: - /* Counter_L/Counter_H can't work together with Counter_U. */ - assert(false); - break; - } -} - -/*! - * @brief Halts the SCTimer counter. - * - * @param base SCTimer peripheral base address - * @param countertoStop The SCTimer counters to stop. This is a logical OR of members of the - * enumeration ::sctimer_counter_t. - */ -static inline void SCTIMER_StopTimer(SCT_Type *base, uint32_t countertoStop) -{ - switch (countertoStop) - { - case (uint32_t)kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Set HALT_L bit when user wants to start the Low counter */ - base->CTRL_ACCESS16BIT.CTRLL |= (SCT_CTRLL_HALT_L_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Set HALT_H bit when user wants to start the High counter */ - base->CTRL_ACCESS16BIT.CTRLH |= (SCT_CTRLH_HALT_H_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_L | (uint32_t)kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_L/HALT_H bit when user wants to H counter and L counter at same time */ - base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Set HALT_L bit when the counter is operating in 32-bit mode (unify counter). */ - base->CTRL |= (SCT_CTRL_HALT_L_MASK); - break; - - default: - /* Counter_L/Counter_H can't work together with Counter_U. */ - assert(false); - break; - } -} - -/*! @}*/ - -/*! - * @name Functions to create a new event and manage the state logic - * @{ - */ - -/*! - * @brief Create an event that is triggered on a match or IO and schedule in current state. - * - * This function will configure an event using the options provided by the user. If the event type uses - * the counter match, then the function will set the user provided match value into a match register - * and put this match register number into the event control register. - * The event is enabled for the current state and the event number is increased by one at the end. - * The function returns the event number; this event number can be used to configure actions to be - * done when this event is triggered. - * - * @param base SCTimer peripheral base address - * @param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t - * @param matchValue The match value that will be programmed to a match register - * @param whichIO The input or output that will be involved in event triggering. This field - * is ignored if the event type is "match only" - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Pointer to a variable where the new event number is stored - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of events created or - if we have reached the limit in terms of number of match registers - */ -status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, - sctimer_event_t howToMonitor, - uint32_t matchValue, - uint32_t whichIO, - sctimer_counter_t whichCounter, - uint32_t *event); - -/*! - * @brief Enable an event in the current state. - * - * This function will allow the event passed in to trigger in the current state. The event must - * be created earlier by either calling the function SCTIMER_SetupPwm() or function - * SCTIMER_CreateAndScheduleEvent() . - * - * @param base SCTimer peripheral base address - * @param event Event number to enable in the current state - * - */ -void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event); - -/*! - * @brief Increase the state by 1 - * - * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new - * state. - * - * @param base SCTimer peripheral base address - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of states used - - */ -status_t SCTIMER_IncreaseState(SCT_Type *base); - -/*! - * @brief Provides the current state - * - * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). - * - * @param base SCTimer peripheral base address - * - * @return The current state - */ -uint32_t SCTIMER_GetCurrentState(SCT_Type *base); - -/*! - * @brief Set the counter current state. - * - * The function is to set the state variable bit field of STATE register. Writing to the STATE_L, STATE_H, or unified - * register is only allowed when the corresponding counter is halted (HALT bits are set to 1 in the CTRL register). - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param state The counter current state number (only support range from 0~31). - */ -static inline void SCTIMER_SetCounterState(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t state) -{ - /* SCT only support 0 ~ FSL_FEATURE_SCT_NUMBER_OF_STATES state value. */ - assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); - - SCTIMER_StopTimer(base, (uint32_t)whichCounter); - - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_L bits when user wants to setup the Low counter */ - base->STATE_ACCESS16BIT.STATEL = SCT_STATEL_STATEL(state); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_H bits when user wants to start the High counter */ - base->STATE_ACCESS16BIT.STATEH = SCT_STATEH_STATEH(state); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_L bits when counter is operating in 32-bit mode (unify counter). */ - base->STATE = SCT_STATE_STATE_L(state); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } - - SCTIMER_StartTimer(base, (uint32_t)whichCounter); -} - -/*! - * @brief Get the counter current state value. - * - * The function is to get the state variable bit field of STATE register. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @return The the counter current state value. - */ -static inline uint16_t SCTIMER_GetCounterState(SCT_Type *base, sctimer_counter_t whichCounter) -{ - uint16_t regs; - - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_L bits when user wants to setup the Low counter */ - regs = base->STATE_ACCESS16BIT.STATEL & SCT_STATEL_STATEL_MASK; - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_H bits when user wants to start the High counter */ - regs = base->STATE_ACCESS16BIT.STATEH & SCT_STATEH_STATEH_MASK; - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_L bits when counter is operating in 32-bit mode (unify counter). */ - regs = (uint16_t)(base->STATE & SCT_STATE_STATE_L_MASK); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } - - return regs; -} - -/*! @}*/ - -/*! - * @name Actions to take in response to an event - * @{ - */ - -/*! - * @brief Setup capture of the counter value on trigger of a selected event - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param captureRegister Pointer to a variable where the capture register number will be returned. User - * can read the captured value from this register when the specified event is triggered. - * @param event Event number that will trigger the capture - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of match/capture registers available - */ -status_t SCTIMER_SetupCaptureAction(SCT_Type *base, - sctimer_counter_t whichCounter, - uint32_t *captureRegister, - uint32_t event); - -/*! - * @brief Receive noticification when the event trigger an interrupt. - * - * If the interrupt for the event is enabled by the user, then a callback can be registered - * which will be invoked when the event is triggered - * - * @param base SCTimer peripheral base address - * @param event Event number that will trigger the interrupt - * @param callback Function to invoke when the event is triggered - */ - -void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event); - -/*! - * @brief Change the load method of transition to the specified state. - * - * Change the load method of transition, it will be triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param event Event number that will change the method to trigger the state transition - * @param fgLoad The method to load highest-numbered event occurring for that state to the STATE register. - * - true: Load the STATEV value to STATE when the event occurs to be the next state. - * - false: Add the STATEV value to STATE when the event occurs to be the next state. - */ -static inline void SCTIMER_SetupStateLdMethodAction(SCT_Type *base, uint32_t event, bool fgLoad) -{ - uint32_t reg = base->EV[event].CTRL; - - if (fgLoad) - { - /* Load the STATEV value to STATE when the event occurs to be the next state */ - reg |= SCT_EV_CTRL_STATELD_MASK; - } - else - { - /* Add the STATEV value to STATE when the event occurs to be the next state */ - reg &= ~SCT_EV_CTRL_STATELD_MASK; - } - - base->EV[event].CTRL = reg; -} - -/*! - * @brief Transition to the specified state with Load method. - * - * This transition will be triggered by the event number that is passed in by the user, the method decide how to load - * the highest-numbered event occurring for that state to the STATE register. - * - * @param base SCTimer peripheral base address - * @param nextState The next state SCTimer will transition to - * @param event Event number that will trigger the state transition - * @param fgLoad The method to load the highest-numbered event occurring for that state to the STATE register. - * - true: Load the STATEV value to STATE when the event occurs to be the next state. - * - false: Add the STATEV value to STATE when the event occurs to be the next state. - */ -static inline void SCTIMER_SetupNextStateActionwithLdMethod(SCT_Type *base, - uint32_t nextState, - uint32_t event, - bool fgLoad) -{ - uint32_t reg = base->EV[event].CTRL; - - reg &= ~(SCT_EV_CTRL_STATEV_MASK | SCT_EV_CTRL_STATELD_MASK); - - reg |= SCT_EV_CTRL_STATEV(nextState); - - if (fgLoad) - { - /* Load the STATEV value when the event occurs to be the next state */ - reg |= SCT_EV_CTRL_STATELD_MASK; - } - - base->EV[event].CTRL = reg; -} - -/*! - * @brief Transition to the specified state. - * @deprecated Do not use this function. It has been superceded by @ref SCTIMER_SetupNextStateActionwithLdMethod - * - * This transition will be triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param nextState The next state SCTimer will transition to - * @param event Event number that will trigger the state transition - */ -static inline void SCTIMER_SetupNextStateAction(SCT_Type *base, uint32_t nextState, uint32_t event) -{ - uint32_t reg = base->EV[event].CTRL; - - reg &= ~(SCT_EV_CTRL_STATEV_MASK); - /* Load the STATEV value when the event occurs to be the next state */ - reg |= SCT_EV_CTRL_STATEV(nextState) | SCT_EV_CTRL_STATELD_MASK; - - base->EV[event].CTRL = reg; -} - -/*! - * @brief Setup event active direction when the counters are operating in BIDIR mode. - * - * @param base SCTimer peripheral base address - * @param activeDirection Event generation active direction, see @ref sctimer_event_active_direction_t. - * @param event Event number that need setup the active direction. - */ -static inline void SCTIMER_SetupEventActiveDirection(SCT_Type *base, - sctimer_event_active_direction_t activeDirection, - uint32_t event) -{ - uint32_t reg = base->EV[event].CTRL; - - reg &= ~(SCT_EV_CTRL_DIRECTION_MASK); - - reg |= SCT_EV_CTRL_DIRECTION(activeDirection); - - base->EV[event].CTRL = reg; -} - -/*! - * @brief Set the Output. - * - * This output will be set when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to set - * @param event Event number that will trigger the output change - */ -static inline void SCTIMER_SetupOutputSetAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - base->OUT[whichIO].SET |= (1UL << event); -} - -/*! - * @brief Clear the Output. - * - * This output will be cleared when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to clear - * @param event Event number that will trigger the output change - */ -static inline void SCTIMER_SetupOutputClearAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - base->OUT[whichIO].CLR |= (1UL << event); -} - -/*! - * @brief Toggle the output level. - * - * This change in the output level is triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to toggle - * @param event Event number that will trigger the output change - */ -void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event); - -/*! - * @brief Limit the running counter. - * - * The counter is limited when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Event number that will trigger the counter to be limited - */ -static inline void SCTIMER_SetupCounterLimitAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->LIMIT_ACCESS16BIT.LIMITL |= SCT_LIMITL_LIMITL(1UL << event); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->LIMIT_ACCESS16BIT.LIMITH |= SCT_LIMITH_LIMITH(1UL << event); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->LIMIT |= SCT_LIMIT_LIMMSK_L(1UL << event); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } -} - -/*! - * @brief Stop the running counter. - * - * The counter is stopped when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Event number that will trigger the counter to be stopped - */ -static inline void SCTIMER_SetupCounterStopAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->STOP_ACCESS16BIT.STOPL |= SCT_STOPL_STOPL(1UL << event); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->STOP_ACCESS16BIT.STOPH |= SCT_STOPH_STOPH(1UL << event); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->STOP |= SCT_STOP_STOPMSK_L(1UL << event); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } -} - -/*! - * @brief Re-start the stopped counter. - * - * The counter will re-start when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Event number that will trigger the counter to re-start - */ -static inline void SCTIMER_SetupCounterStartAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->START_ACCESS16BIT.STARTL |= SCT_STARTL_STARTL(1UL << event); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->START_ACCESS16BIT.STARTH |= SCT_STARTH_STARTH(1UL << event); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->START |= SCT_START_STARTMSK_L(1UL << event); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } -} - -/*! - * @brief Halt the running counter. - * - * The counter is disabled (halted) when the event number that is passed in by the user is - * triggered. When the counter is halted, all further events are disabled. The HALT condition - * can only be removed by calling the SCTIMER_StartTimer() function. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Event number that will trigger the counter to be halted - */ -static inline void SCTIMER_SetupCounterHaltAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->HALT_ACCESS16BIT.HALTL |= SCT_HALTL_HALTL(1UL << event); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->HALT_ACCESS16BIT.HALTH |= SCT_HALTH_HALTH(1UL << event); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->HALT |= SCT_HALT_HALTMSK_L(1UL << event); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } -} - -#if !(defined(FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) && FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) -/*! - * @brief Generate a DMA request. - * - * DMA request will be triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param dmaNumber The DMA request to generate - * @param event Event number that will trigger the DMA request - */ -static inline void SCTIMER_SetupDmaTriggerAction(SCT_Type *base, uint32_t dmaNumber, uint32_t event) -{ - if (dmaNumber == 0U) - { - base->DMAREQ0 |= (1UL << event); - } - else - { - base->DMAREQ1 |= (1UL << event); - } -} -#endif /* FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST */ - -/*! - * @brief Set the value of counter. - * - * The function is to set the value of Count register, Writing to the COUNT_L, COUNT_H, or unified register - * is only allowed when the corresponding counter is halted (HALT bits are set to 1 in the CTRL register). - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param value the counter value update to the COUNT register. - */ -static inline void SCTIMER_SetCOUNTValue(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t value) -{ - SCTIMER_StopTimer(base, (uint32_t)whichCounter); - - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(value <= 0xFFFFU); - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->COUNT_ACCESS16BIT.COUNTL = (uint16_t)value; - break; - - case kSCTIMER_Counter_H: - assert(value <= 0xFFFFU); - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->COUNT_ACCESS16BIT.COUNTH = (uint16_t)value; - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->COUNT &= ~SCT_COUNT_CTR_L_MASK; - base->COUNT |= SCT_COUNT_CTR_L(value); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } - - SCTIMER_StartTimer(base, (uint32_t)whichCounter); -} - -/*! - * @brief Get the value of counter. - * - * The function is to read the value of Count register, software can read the counter registers at any time.. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @return The value of counter selected. - */ -static inline uint32_t SCTIMER_GetCOUNTValue(SCT_Type *base, sctimer_counter_t whichCounter) -{ - uint32_t value; - - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - value = base->COUNT_ACCESS16BIT.COUNTL; - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - value = base->COUNT_ACCESS16BIT.COUNTH; - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - value = base->COUNT; - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } - - return value; -} - -/*! - * @brief Set the state mask bit field of EV_STATE register. - * - * @param base SCTimer peripheral base address - * @param event The EV_STATE register be set. - * @param state The state value in which the event is enabled to occur. - */ -static inline void SCTIMER_SetEventInState(SCT_Type *base, uint32_t event, uint32_t state) -{ - assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); - assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); - - base->EV[event].STATE |= SCT_EV_STATE_STATEMSKn((uint32_t)1U << state); -} - -/*! - * @brief Clear the state mask bit field of EV_STATE register. - * - * @param base SCTimer peripheral base address - * @param event The EV_STATE register be clear. - * @param state The state value in which the event is disabled to occur. - */ -static inline void SCTIMER_ClearEventInState(SCT_Type *base, uint32_t event, uint32_t state) -{ - assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); - assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); - - base->EV[event].STATE &= ~SCT_EV_STATE_STATEMSKn((uint32_t)1U << state); -} - -/*! - * @brief Get the state mask bit field of EV_STATE register. - * - * @note This function is to check whether the event is enabled in a specific state. - * - * @param base SCTimer peripheral base address - * @param event The EV_STATE register be read. - * @param state The state value. - * - * @return The the state mask bit field of EV_STATE register. - * - true: The event is enable in state. - * - false: The event is disable in state. - */ -static inline bool SCTIMER_GetEventInState(SCT_Type *base, uint32_t event, uint32_t state) -{ - assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); - assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); - - return (0U != (base->EV[event].STATE & SCT_EV_STATE_STATEMSKn((uint32_t)1U << state))); -} - -/*! - * @brief SCTimer interrupt handler. - * - * @param base SCTimer peripheral base address. - */ -void SCTIMER_EventHandleIRQ(SCT_Type *base); - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_SCTIMER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_spi.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_spi.c deleted file mode 100644 index 456361e6204..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_spi.c +++ /dev/null @@ -1,1072 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_spi.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi" -#endif - -/* Note: FIFOCFG[SIZE] has always value 1 = 8 items depth */ - -#if defined(FSL_FEATURE_SPI_FIFOSIZE_CFG) && (FSL_FEATURE_SPI_FIFOSIZE_CFG) -#define SPI_FIFO_DEPTH(base) 4 -#else -#define SPI_FIFO_DEPTH(base) ((((base)->FIFOCFG & SPI_FIFOCFG_SIZE_MASK) >> SPI_FIFOCFG_SIZE_SHIFT) << 3) -#endif /*FSL_FEATURE_SPI_FIFOSIZE_CFG*/ - -/* Convert transfer count to transfer bytes. dataWidth is a - * range <0,15>. Range <8,15> represents 2B transfer */ -#define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U)) -#define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U)) -#if defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) && (FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) -#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK)) -#else -#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK) | (SPI_CFG_SPOL3_MASK)) -#endif /*FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE*/ - -/*! - * @brief Used for conversion from `flexcomm_irq_handler_t` to `flexcomm_spi_master_irq_handler_t` and - * `flexcomm_spi_slave_irq_handler_t`. - */ -typedef union spi_to_flexcomm -{ - flexcomm_spi_master_irq_handler_t spi_master_handler; - flexcomm_spi_slave_irq_handler_t spi_slave_handler; - flexcomm_irq_handler_t flexcomm_handler; -} spi_to_flexcomm_t; - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief internal SPI config array */ -static spi_config_t g_configs[FSL_FEATURE_SOC_SPI_COUNT] = {(spi_data_width_t)0}; - -/*! @brief Array to map SPI instance number to base address. */ -static const uint32_t s_spiBaseAddrs[FSL_FEATURE_SOC_SPI_COUNT] = SPI_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_spiIRQ[] = SPI_IRQS; - -/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ -volatile uint8_t s_dummyData[FSL_FEATURE_SOC_SPI_COUNT] = {0}; -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Get the index corresponding to the FLEXCOMM */ -/*! brief Returns instance number for SPI peripheral base address. */ -uint32_t SPI_GetInstance(SPI_Type *base) -{ - uint32_t i; - - for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_SPI_COUNT; i++) - { - if ((uint32_t)base == s_spiBaseAddrs[i]) - { - break; - } - } - - assert(i < (uint32_t)FSL_FEATURE_SOC_SPI_COUNT); - return i; -} - -/*! - * brief Set up the dummy data. - * - * param base SPI peripheral address. - * param dummyData Data to be transferred when tx buffer is NULL. - */ -void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData) -{ - uint32_t instance = SPI_GetInstance(base); - s_dummyData[instance] = dummyData; -} - -/*! - * brief Returns the configurations. - * - * param base SPI peripheral address. - * return return configurations which contain datawidth and SSEL numbers. - * return data type is a pointer of spi_config_t. - */ -void *SPI_GetConfig(SPI_Type *base) -{ - uint32_t instance; - instance = SPI_GetInstance(base); - return &g_configs[instance]; -} - -/*! - * brief Sets the SPI master configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). - * User may use the initialized structure unchanged in SPI_MasterInit(), or modify - * some fields of the structure before calling SPI_MasterInit(). After calling this API, - * the master is ready to transfer. - * Example: - code - spi_master_config_t config; - SPI_MasterGetDefaultConfig(&config); - endcode - * - * param config pointer to master config structure - */ -void SPI_MasterGetDefaultConfig(spi_master_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enableLoopback = false; - config->enableMaster = true; - config->polarity = kSPI_ClockPolarityActiveHigh; - config->phase = kSPI_ClockPhaseFirstEdge; - config->direction = kSPI_MsbFirst; - config->baudRate_Bps = 500000U; - config->dataWidth = kSPI_Data8Bits; - config->sselNum = kSPI_Ssel0; - config->txWatermark = (uint8_t)kSPI_TxFifo0; - config->rxWatermark = (uint8_t)kSPI_RxFifo1; - config->sselPol = kSPI_SpolActiveAllLow; - config->delayConfig.preDelay = 0U; - config->delayConfig.postDelay = 0U; - config->delayConfig.frameDelay = 0U; - config->delayConfig.transferDelay = 0U; -} - -/*! - * brief Initializes the SPI with master configuration. - * - * The configuration structure can be filled by user from scratch, or be set with default - * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. - * Example - code - spi_master_config_t config = { - .baudRate_Bps = 400000, - ... - }; - SPI_MasterInit(SPI0, &config); - endcode - * - * param base SPI base pointer - * param config pointer to master configuration structure - * param srcClock_Hz Source clock frequency. - */ -status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz) -{ - status_t result = kStatus_Success; - uint32_t instance; - uint32_t tmpConfig; - - /* assert params */ - assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); - if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* initialize flexcomm to SPI mode */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); - if (kStatus_Success != result) - { - return result; - } - - /* set divider */ - result = SPI_MasterSetBaud(base, config->baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - - /* get instance number */ - instance = SPI_GetInstance(base); - - /* configure SPI mode */ - tmpConfig = base->CFG; - tmpConfig &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | - SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); - /* phase */ - tmpConfig |= SPI_CFG_CPHA(config->phase); - /* polarity */ - tmpConfig |= SPI_CFG_CPOL(config->polarity); - /* direction */ - tmpConfig |= SPI_CFG_LSBF(config->direction); - /* master mode */ - tmpConfig |= SPI_CFG_MASTER(1); - /* loopback */ - tmpConfig |= SPI_CFG_LOOP(config->enableLoopback); - /* configure active level for all CS */ - tmpConfig |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); - base->CFG = tmpConfig; - - /* store configuration */ - g_configs[instance].dataWidth = config->dataWidth; - g_configs[instance].sselNum = config->sselNum; - /* enable FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; - /* trigger level - empty txFIFO, one item in rxFIFO */ - tmpConfig = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); - tmpConfig |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable generating interrupts for FIFOTRIG levels */ - tmpConfig |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; - /* set FIFOTRIG */ - base->FIFOTRIG = tmpConfig; - - /* Set the delay configuration. */ - SPI_SetTransferDelay(base, &config->delayConfig); - /* Set the dummy data. */ - SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); - - SPI_Enable(base, config->enableMaster); - return kStatus_Success; -} - -/*! - * brief Sets the SPI slave configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). - * Modify some fields of the structure before calling SPI_SlaveInit(). - * Example: - code - spi_slave_config_t config; - SPI_SlaveGetDefaultConfig(&config); - endcode - * - * param config pointer to slave configuration structure - */ -void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enableSlave = true; - config->polarity = kSPI_ClockPolarityActiveHigh; - config->phase = kSPI_ClockPhaseFirstEdge; - config->direction = kSPI_MsbFirst; - config->dataWidth = kSPI_Data8Bits; - config->txWatermark = (uint8_t)kSPI_TxFifo0; - config->rxWatermark = (uint8_t)kSPI_RxFifo1; - config->sselPol = kSPI_SpolActiveAllLow; -} - -/*! - * brief Initializes the SPI with slave configuration. - * - * The configuration structure can be filled by user from scratch or be set with - * default values by SPI_SlaveGetDefaultConfig(). - * After calling this API, the slave is ready to transfer. - * Example - code - spi_slave_config_t config = { - .polarity = flexSPIClockPolarity_ActiveHigh; - .phase = flexSPIClockPhase_FirstEdge; - .direction = flexSPIMsbFirst; - ... - }; - SPI_SlaveInit(SPI0, &config); - endcode - * - * param base SPI base pointer - * param config pointer to slave configuration structure - */ -status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) -{ - status_t result = kStatus_Success; - uint32_t instance; - uint32_t tmpConfig; - - /* assert params */ - assert(!((NULL == base) || (NULL == config))); - if ((NULL == base) || (NULL == config)) - { - return kStatus_InvalidArgument; - } - /* configure flexcomm to SPI, enable clock gate */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); - if (kStatus_Success != result) - { - return result; - } - - instance = SPI_GetInstance(base); - - /* configure SPI mode */ - tmpConfig = base->CFG; - tmpConfig &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | - SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); - /* phase */ - tmpConfig |= SPI_CFG_CPHA(config->phase); - /* polarity */ - tmpConfig |= SPI_CFG_CPOL(config->polarity); - /* direction */ - tmpConfig |= SPI_CFG_LSBF(config->direction); - /* configure active level for all CS */ - tmpConfig |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); - base->CFG = tmpConfig; - - /* store configuration */ - g_configs[instance].dataWidth = config->dataWidth; - /* empty and enable FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; - /* trigger level - empty txFIFO, one item in rxFIFO */ - tmpConfig = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); - tmpConfig |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable generating interrupts for FIFOTRIG levels */ - tmpConfig |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; - /* set FIFOTRIG */ - base->FIFOTRIG = tmpConfig; - - SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); - - SPI_Enable(base, config->enableSlave); - return kStatus_Success; -} - -/*! - * brief De-initializes the SPI. - * - * Calling this API resets the SPI module, gates the SPI clock. - * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. - * - * param base SPI base pointer - */ -void SPI_Deinit(SPI_Type *base) -{ - /* Assert arguments */ - assert(NULL != base); - /* Disable interrupts, disable dma requests, disable peripheral */ - base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXERR_MASK | SPI_FIFOINTENCLR_RXERR_MASK | SPI_FIFOINTENCLR_TXLVL_MASK | - SPI_FIFOINTENCLR_RXLVL_MASK; - base->FIFOCFG &= ~(SPI_FIFOCFG_DMATX_MASK | SPI_FIFOCFG_DMARX_MASK); - base->CFG &= ~(SPI_CFG_ENABLE_MASK); -} - -/*! - * brief Enables the DMA request from SPI txFIFO. - * - * param base SPI base pointer - * param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableTxDMA(SPI_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= SPI_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= ~SPI_FIFOCFG_DMATX_MASK; - } -} - -/*! - * brief Enables the DMA request from SPI rxFIFO. - * - * param base SPI base pointer - * param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableRxDMA(SPI_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= SPI_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= ~SPI_FIFOCFG_DMARX_MASK; - } -} - -/*! - * brief Sets the baud rate for SPI transfer. This is only used in master. - * - * param base SPI base pointer - * param baudrate_Bps baud rate needed in Hz. - * param srcClock_Hz SPI source clock frequency in Hz. - */ -status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) -{ - uint32_t tmpDiv; - - /* assert params */ - assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))); - if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* calculate baudrate, round up the result */ - tmpDiv = ((srcClock_Hz * 10U) / baudrate_Bps + 5U) / 10U - 1U; - if (tmpDiv > 0xFFFFU) - { - return kStatus_SPI_BaudrateNotSupport; - } - base->DIV &= ~SPI_DIV_DIVVAL_MASK; - base->DIV |= SPI_DIV_DIVVAL(tmpDiv); - return kStatus_Success; -} - -/*! - * brief Writes a data into the SPI data register. - * - * param base SPI base pointer - * param data needs to be write. - * param configFlags transfer configuration options ref spi_xfer_option_t - */ -void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags) -{ - uint32_t control = 0U; - uint32_t instance; - - /* check params */ - assert(NULL != base); - /* get and check instance */ - instance = SPI_GetInstance(base); - - /* set data width */ - control |= (uint32_t)SPI_FIFOWR_LEN((g_configs[instance].dataWidth)); - /* set sssel */ - control |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL((uint32_t)(g_configs[instance].sselNum)))); - /* mask configFlags */ - control |= (configFlags & (uint32_t)SPI_FIFOWR_FLAGS_MASK); - /* control should not affect lower 16 bits */ - assert(0U == (control & 0xFFFFU)); - base->FIFOWR = data | control; -} - -/*! - * brief Initializes the SPI master handle. - * - * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * param base SPI peripheral base address. - * param handle SPI handle pointer. - * param callback Callback function. - * param userData User data. - */ -status_t SPI_MasterTransferCreateHandle(SPI_Type *base, - spi_master_handle_t *handle, - spi_master_callback_t callback, - void *userData) -{ - /* check 'base' */ - assert(NULL != base); - /* check 'handle' */ - assert(NULL != handle); - - uint32_t instance; - spi_to_flexcomm_t handler; - - /* get flexcomm instance by 'base' param */ - instance = SPI_GetInstance(base); - - (void)memset(handle, 0, sizeof(*handle)); - /* Initialize the handle */ - if ((base->CFG & SPI_CFG_MASTER_MASK) != 0U) - { - handler.spi_master_handler = SPI_MasterTransferHandleIRQ; - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - } - else - { - handler.spi_slave_handler = SPI_SlaveTransferHandleIRQ; - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - } - - handle->dataWidth = (uint8_t)(g_configs[instance].dataWidth); - /* in slave mode, the sselNum is not important */ - handle->sselNum = (uint8_t)(g_configs[instance].sselNum); - handle->txWatermark = (uint8_t)SPI_FIFOTRIG_TXLVL_GET(base); - handle->rxWatermark = (uint8_t)SPI_FIFOTRIG_RXLVL_GET(base); - handle->callback = callback; - handle->userData = userData; - - /* Enable SPI NVIC */ - (void)EnableIRQ(s_spiIRQ[instance]); - - return kStatus_Success; -} - -/*! - * brief Transfers a block of data using a polling method. - * - * param base SPI base pointer - * param xfer pointer to spi_xfer_config_t structure - * retval kStatus_Success Successfully start a transfer. - * retval kStatus_InvalidArgument Input argument is invalid. - * retval kStatus_SPI_Timeout The transfer timed out and was aborted. - */ -status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) -{ - uint32_t instance; - uint32_t tx_ctrl = 0U, last_ctrl = 0U; - uint32_t tmp32, rxRemainingBytes, txRemainingBytes, dataWidth; - uint32_t toReceiveCount = 0; - uint8_t *txData, *rxData; - uint32_t fifoDepth; -#if SPI_RETRY_TIMES - uint32_t waitTimes = SPI_RETRY_TIMES; -#endif - - /* check params */ - assert(!((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); - if ((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) - { - return kStatus_InvalidArgument; - } - - fifoDepth = SPI_FIFO_DEPTH(base); - txData = xfer->txData; - rxData = xfer->rxData; - txRemainingBytes = (txData != NULL) ? xfer->dataSize : 0U; - rxRemainingBytes = (rxData != NULL) ? xfer->dataSize : 0U; - - instance = SPI_GetInstance(base); - dataWidth = (uint32_t)(g_configs[instance].dataWidth); - - /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ - if ((dataWidth > (uint32_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U)) - { - return kStatus_InvalidArgument; - } - - /* clear tx/rx errors and empty FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - /* select slave to talk with */ - tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL((uint32_t)(g_configs[instance].sselNum)))); - /* set width of data - range asserted at entry */ - tx_ctrl |= SPI_FIFOWR_LEN(dataWidth); - /* delay for frames */ - tx_ctrl |= ((xfer->configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; - /* end of transfer */ - last_ctrl |= ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; - /* last index of loop */ - while ((txRemainingBytes != 0U) || (rxRemainingBytes != 0U) || (toReceiveCount != 0U)) - { -#if SPI_RETRY_TIMES - if (--waitTimes == 0U) - { - return kStatus_SPI_Timeout; - } -#endif - /* if rxFIFO is not empty */ - if ((base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) != 0U) - { - tmp32 = base->FIFORD; - /* rxBuffer is not empty */ - if (rxRemainingBytes != 0U) - { - *(rxData++) = (uint8_t)tmp32; - rxRemainingBytes--; - /* read 16 bits at once */ - if (dataWidth > 8U) - { - *(rxData++) = (uint8_t)(tmp32 >> 8); - rxRemainingBytes--; - } - } - /* decrease number of data expected to receive */ - toReceiveCount -= 1U; - } - /* transmit if txFIFO is not full and data to receive does not exceed FIFO depth */ - if (((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) != 0U) && (toReceiveCount < fifoDepth) && - ((txRemainingBytes != 0U) || (rxRemainingBytes >= SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1U)))) - { - /* txBuffer is not empty */ - if (txRemainingBytes != 0U) - { - tmp32 = *(txData++); - txRemainingBytes--; - /* write 16 bit at once */ - if (dataWidth > 8U) - { - tmp32 |= ((uint32_t)(*(txData++))) << 8U; - txRemainingBytes--; - } - if (txRemainingBytes == 0U) - { - tx_ctrl |= last_ctrl; - } - } - else - { - tmp32 = (uint32_t)s_dummyData[instance]; - tmp32 |= (uint32_t)s_dummyData[instance] << 8U; - /* last transfer */ - if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1U)) - { - tx_ctrl |= last_ctrl; - } - } - /* send data */ - tmp32 = tx_ctrl | tmp32; - base->FIFOWR = tmp32; - toReceiveCount += 1U; - } - } - /* wait if TX FIFO of previous transfer is not empty */ -#if SPI_RETRY_TIMES - waitTimes = SPI_RETRY_TIMES; - while ((0U == (base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) && (0U != --waitTimes)) -#else - while (0U == (base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) -#endif - { - } -#if SPI_RETRY_TIMES - if (waitTimes == 0U) - { - return kStatus_SPI_Timeout; - } -#endif - return kStatus_Success; -} - -/*! - * brief Performs a non-blocking SPI interrupt transfer. - * - * param base SPI peripheral base address. - * param handle pointer to spi_master_handle_t structure which stores the transfer state - * param xfer pointer to spi_xfer_config_t structure - * retval kStatus_Success Successfully start a transfer. - * retval kStatus_InvalidArgument Input argument is invalid. - * retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer) -{ - /* check params */ - assert( - !((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) - { - return kStatus_InvalidArgument; - } - - /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ - assert(!((handle->dataWidth > (uint8_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U))); - if ((handle->dataWidth > (uint8_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U)) - { - return kStatus_InvalidArgument; - } - - /* Check if SPI is busy */ - if (handle->state == (uint32_t)kStatus_SPI_Busy) - { - return kStatus_SPI_Busy; - } - - /* Set the handle information */ - handle->txData = xfer->txData; - handle->rxData = xfer->rxData; - /* set count */ - handle->txRemainingBytes = (xfer->txData != NULL) ? xfer->dataSize : 0U; - handle->rxRemainingBytes = (xfer->rxData != NULL) ? xfer->dataSize : 0U; - handle->totalByteCount = xfer->dataSize; - /* other options */ - handle->toReceiveCount = 0; - handle->configFlags = xfer->configFlags; - /* Set the SPI state to busy */ - handle->state = (uint32_t)kStatus_SPI_Busy; - /* clear FIFOs when transfer starts */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - /* enable generating txIRQ and rxIRQ, first transfer is fired by empty txFIFO */ - base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK; - return kStatus_Success; -} - -/*! - * brief Transfers a block of data using a polling method. - * - * This function will do a half-duplex transfer for SPI master, This is a blocking function, - * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, - * users can set transmit first or receive first. - * - * param base SPI base pointer - * param xfer pointer to spi_half_duplex_transfer_t structure - * return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer) -{ - assert(xfer != NULL); - - spi_transfer_t tempXfer = {0}; - status_t status; - - if (xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the pcs pin keep assert between transmit and receive. */ - if (xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); - } - else - { - tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; - } - - status = SPI_MasterTransferBlocking(base, &tempXfer); - - if (status != kStatus_Success) - { - return status; - } - - if (xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - /* SPI transfer blocking. */ - status = SPI_MasterTransferBlocking(base, &tempXfer); - - return status; -} - -/*! - * brief Performs a non-blocking SPI interrupt transfer. - * - * This function using polling way to do the first half transimission and using interrupts to - * do the second half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * param base SPI peripheral base address. - * param handle pointer to spi_master_handle_t structure which stores the transfer state - * param xfer pointer to spi_half_duplex_transfer_t structure - * return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, - spi_master_handle_t *handle, - spi_half_duplex_transfer_t *xfer) -{ - assert(xfer != NULL); - assert(handle != NULL); - spi_transfer_t tempXfer = {0}; - status_t status; - - if (xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the PCS pin keep assert between transmit and receive. */ - if (xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); - } - else - { - tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; - } - - status = SPI_MasterTransferBlocking(base, &tempXfer); - if (status != kStatus_Success) - { - return status; - } - - if (xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - status = SPI_MasterTransferNonBlocking(base, handle, &tempXfer); - - return status; -} - -/*! - * brief Gets the master transfer count. - * - * This function gets the master transfer count. - * - * param base SPI peripheral base address. - * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * param count The number of bytes transferred by using the non-blocking transaction. - * return status of status_t. - */ -status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count) -{ - assert(NULL != handle); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != (uint32_t)kStatus_SPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - *count = handle->totalByteCount - handle->rxRemainingBytes; - return kStatus_Success; -} - -/*! - * brief SPI master aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * param base SPI peripheral base address. - * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle) -{ - assert(NULL != handle); - - /* Disable interrupt requests*/ - base->FIFOINTENSET &= ~(SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK); - /* Empty FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - - handle->state = (uint32_t)kStatus_SPI_Idle; - handle->txRemainingBytes = 0U; - handle->rxRemainingBytes = 0U; -} - -static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *handle) -{ - uint32_t tx_ctrl = 0U, last_ctrl = 0U, tmp32; - bool loopContinue; - uint32_t fifoDepth; - /* Get flexcomm instance by 'base' param */ - uint32_t instance = SPI_GetInstance(base); - size_t txRemainingBytes; - size_t rxRemainingBytes; - uint8_t toReceiveCount; - - /* check params */ - assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData))); - - fifoDepth = SPI_FIFO_DEPTH(base); - /* select slave to talk with */ - tx_ctrl |= ((uint32_t)SPI_DEASSERT_ALL & (uint32_t)SPI_ASSERTNUM_SSEL(handle->sselNum)); - /* set width of data */ - tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth); - /* delay for frames */ - tx_ctrl |= ((handle->configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; - /* end of transfer */ - last_ctrl |= ((handle->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; - do - { - loopContinue = false; - - /* rxFIFO is not empty */ - if ((base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) != 0U) - { - tmp32 = base->FIFORD; - /* rxBuffer is not empty */ - if (handle->rxRemainingBytes != 0U) - { - /* low byte must go first */ - *(handle->rxData++) = (uint8_t)tmp32; - handle->rxRemainingBytes--; - /* read 16 bits at once */ - if (handle->dataWidth > (uint8_t)kSPI_Data8Bits) - { - *(handle->rxData++) = (uint8_t)(tmp32 >> 8); - handle->rxRemainingBytes--; - } - } - - /* decrease number of data expected to receive */ - handle->toReceiveCount -= 1; - loopContinue = true; - } - - /* - txFIFO is not full - * - we cannot cause rxFIFO overflow by sending more data than is the depth of FIFO - * - txBuffer is not empty or the next 'toReceiveCount' data can fit into rxBuffer - */ - txRemainingBytes = handle->txRemainingBytes; - rxRemainingBytes = handle->rxRemainingBytes; - toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; - if (((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) != 0U) && ((uint32_t)toReceiveCount < fifoDepth) && - ((txRemainingBytes != 0U) || - (rxRemainingBytes >= SPI_COUNT_TO_BYTES(handle->dataWidth, (uint32_t)toReceiveCount + 1U)))) - { - /* txBuffer is not empty */ - if ((txRemainingBytes != 0U) && (handle->txData != NULL)) - { - /* low byte must go first */ - tmp32 = *(handle->txData++); - handle->txRemainingBytes--; - txRemainingBytes = handle->txRemainingBytes; - /* write 16 bit at once */ - if (handle->dataWidth > (uint8_t)kSPI_Data8Bits) - { - tmp32 |= ((uint32_t)(*(handle->txData++))) << 8U; - handle->txRemainingBytes--; - txRemainingBytes = handle->txRemainingBytes; - } - /* last transfer */ - if (handle->txRemainingBytes == 0U) - { - tx_ctrl |= last_ctrl; - } - } - else - { - tmp32 = (uint32_t)s_dummyData[instance]; - tmp32 |= (uint32_t)s_dummyData[instance] << 8U; - /* last transfer */ - if (rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, (uint32_t)toReceiveCount + 1U)) - { - tx_ctrl |= last_ctrl; - } - } - /* send data */ - tmp32 = tx_ctrl | tmp32; - base->FIFOWR = tmp32; - /* increase number of expected data to receive */ - handle->toReceiveCount += 1; - toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; - loopContinue = true; - } - } while (loopContinue); -} - -/*! - * brief Interrupts the handler for the SPI. - * - * param base SPI peripheral base address. - * param handle pointer to spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle) -{ - assert((NULL != base) && (NULL != handle)); - size_t txRemainingBytes; - uint8_t toReceiveCount; - - /* IRQ behaviour: - * - first interrupt is triggered by empty txFIFO. The transfer function - * then tries empty rxFIFO and fill txFIFO interleaved that results to - * strategy to process as many items as possible. - * - the next IRQs can be: - * rxIRQ from nonempty rxFIFO which requires to empty rxFIFO. - * txIRQ from empty txFIFO which requires to refill txFIFO. - * - last interrupt is triggered by empty txFIFO. The last state is - * known by empty rxBuffer and txBuffer. If there is nothing to receive - * or send - both operations have been finished and interrupts can be - * disabled. - */ - - /* Data to send or read or expected to receive */ - if ((handle->txRemainingBytes != 0U) || (handle->rxRemainingBytes != 0U) || (handle->toReceiveCount != 0)) - { - /* Transmit or receive data */ - SPI_TransferHandleIRQInternal(base, handle); - /* No data to send or read or receive. Transfer ends. Set txTrigger to 0 level and - * enable txIRQ to confirm when txFIFO becomes empty */ - if ((0U == handle->txRemainingBytes) && (0U == handle->rxRemainingBytes) && (0 == handle->toReceiveCount)) - { - base->FIFOTRIG = base->FIFOTRIG & (~SPI_FIFOTRIG_TXLVL_MASK); - base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK; - } - else - { - uint32_t rxRemainingCount = SPI_BYTES_TO_COUNT(handle->dataWidth, handle->rxRemainingBytes); - /* If, there are no data to send or rxFIFO is already filled with necessary number of dummy data, - * disable txIRQ. From this point only rxIRQ is used to receive data without any transmission */ - toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; - if ((0U == handle->txRemainingBytes) && (rxRemainingCount <= toReceiveCount)) - { - base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXLVL_MASK; - } - /* Nothing to receive or transmit, but we still have pending data which are bellow rxLevel. - * Cannot clear rxFIFO, txFIFO might be still active */ - if (rxRemainingCount == 0U) - { - txRemainingBytes = handle->txRemainingBytes; - if ((txRemainingBytes == 0U) && (toReceiveCount != 0U) && - (toReceiveCount < SPI_FIFOTRIG_RXLVL_GET(base) + 1U)) - { - base->FIFOTRIG = (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | - SPI_FIFOTRIG_RXLVL((uint32_t)toReceiveCount - 1U); - } - } - else - { - /* Expected to receive less data than rxLevel value, we have to update rxLevel */ - if (rxRemainingCount < (SPI_FIFOTRIG_RXLVL_GET(base) + 1U)) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(rxRemainingCount - 1U); - } - } - } - } - else - { - /* Empty txFIFO is confirmed. Disable IRQs and restore triggers values */ - base->FIFOINTENCLR = SPI_FIFOINTENCLR_RXLVL_MASK | SPI_FIFOINTENCLR_TXLVL_MASK; - base->FIFOTRIG = (base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_RXLVL_MASK))) | - SPI_FIFOTRIG_RXLVL(handle->rxWatermark) | SPI_FIFOTRIG_TXLVL(handle->txWatermark); - /* set idle state and call user callback */ - handle->state = (uint32_t)kStatus_SPI_Idle; - if (handle->callback != NULL) - { - (handle->callback)(base, handle, handle->state, handle->userData); - } - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_spi.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_spi.h deleted file mode 100644 index 2320e574cc9..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_spi.h +++ /dev/null @@ -1,746 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SPI_H_ -#define _FSL_SPI_H_ - -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/*! - * @addtogroup spi_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SPI driver version. */ -#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) -/*@}*/ - -/*! @brief Global variable for dummy data value setting. */ -extern volatile uint8_t s_dummyData[]; - -#ifndef SPI_DUMMYDATA -/*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */ -#define SPI_DUMMYDATA (0xFFU) -#endif - -/*! @brief Retry times for waiting flag. */ -#ifndef SPI_RETRY_TIMES -#define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ -#endif - -#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFFUL) -#define SPI_CTRLMASK (0xFFFF0000U) - -#define SPI_ASSERTNUM_SSEL(n) ((~(1UL << ((n) + 16UL))) & 0xF0000UL) -#define SPI_DEASSERTNUM_SSEL(n) (1UL << ((n) + 16UL)) -#define SPI_DEASSERT_ALL (0xF0000UL) - -#define SPI_FIFOWR_FLAGS_MASK (~(SPI_DEASSERT_ALL | SPI_FIFOWR_TXDATA_MASK | SPI_FIFOWR_LEN_MASK)) - -#define SPI_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_TXLVL_MASK) >> SPI_FIFOTRIG_TXLVL_SHIFT) -#define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT) - -/*! @brief SPI transfer option.*/ -typedef enum _spi_xfer_option -{ - kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), /*!< A delay may be inserted, defined in the DLY register.*/ - kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< SSEL will be deasserted at the end of a transfer */ -} spi_xfer_option_t; - -/*! @brief SPI data shifter direction options.*/ -typedef enum _spi_shift_direction -{ - kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */ - kSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. */ -} spi_shift_direction_t; - -/*! @brief SPI clock polarity configuration.*/ -typedef enum _spi_clock_polarity -{ - kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */ - kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */ -} spi_clock_polarity_t; - -/*! @brief SPI clock phase configuration.*/ -typedef enum _spi_clock_phase -{ - kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first - * cycle of a data transfer. */ - kSPI_ClockPhaseSecondEdge /*!< First edge on SCK occurs at the start of the - * first cycle of a data transfer. */ -} spi_clock_phase_t; - -/*! @brief txFIFO watermark values */ -typedef enum _spi_txfifo_watermark -{ - kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */ - kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */ - kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */ - kSPI_TxFifo3 = 3, /*!< SPI tx watermark at 3 items */ - kSPI_TxFifo4 = 4, /*!< SPI tx watermark at 4 items */ - kSPI_TxFifo5 = 5, /*!< SPI tx watermark at 5 items */ - kSPI_TxFifo6 = 6, /*!< SPI tx watermark at 6 items */ - kSPI_TxFifo7 = 7, /*!< SPI tx watermark at 7 items */ -} spi_txfifo_watermark_t; - -/*! @brief rxFIFO watermark values */ -typedef enum _spi_rxfifo_watermark -{ - kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */ - kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */ - kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */ - kSPI_RxFifo4 = 3, /*!< SPI rx watermark at 4 items */ - kSPI_RxFifo5 = 4, /*!< SPI rx watermark at 5 items */ - kSPI_RxFifo6 = 5, /*!< SPI rx watermark at 6 items */ - kSPI_RxFifo7 = 6, /*!< SPI rx watermark at 7 items */ - kSPI_RxFifo8 = 7, /*!< SPI rx watermark at 8 items */ -} spi_rxfifo_watermark_t; - -/*! @brief Transfer data width */ -typedef enum _spi_data_width -{ - kSPI_Data4Bits = 3, /*!< 4 bits data width */ - kSPI_Data5Bits = 4, /*!< 5 bits data width */ - kSPI_Data6Bits = 5, /*!< 6 bits data width */ - kSPI_Data7Bits = 6, /*!< 7 bits data width */ - kSPI_Data8Bits = 7, /*!< 8 bits data width */ - kSPI_Data9Bits = 8, /*!< 9 bits data width */ - kSPI_Data10Bits = 9, /*!< 10 bits data width */ - kSPI_Data11Bits = 10, /*!< 11 bits data width */ - kSPI_Data12Bits = 11, /*!< 12 bits data width */ - kSPI_Data13Bits = 12, /*!< 13 bits data width */ - kSPI_Data14Bits = 13, /*!< 14 bits data width */ - kSPI_Data15Bits = 14, /*!< 15 bits data width */ - kSPI_Data16Bits = 15, /*!< 16 bits data width */ -} spi_data_width_t; - -/*! @brief Slave select */ -typedef enum _spi_ssel -{ - kSPI_Ssel0 = 0, /*!< Slave select 0 */ - kSPI_Ssel1 = 1, /*!< Slave select 1 */ - kSPI_Ssel2 = 2, /*!< Slave select 2 */ - kSPI_Ssel3 = 3, /*!< Slave select 3 */ -} spi_ssel_t; - -/*! @brief ssel polarity */ -typedef enum _spi_spol -{ - kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0(1), - kSPI_Spol1ActiveHigh = SPI_CFG_SPOL1(1), - kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2(1), -#if defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) && (FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) - kSPI_SpolActiveAllHigh = (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh), -#else - kSPI_Spol3ActiveHigh = SPI_CFG_SPOL3(1), - kSPI_SpolActiveAllHigh = - (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh | kSPI_Spol3ActiveHigh), -#endif - kSPI_SpolActiveAllLow = 0, -} spi_spol_t; - -/*! - * @brief SPI delay time configure structure. - * Note: - * The DLY register controls several programmable delays related to SPI signalling, - * it stands for how many SPI clock time will be inserted. - * The maxinun value of these delay time is 15. - */ -typedef struct _spi_delay_config -{ - uint8_t preDelay; /*!< Delay between SSEL assertion and the beginning of transfer. */ - uint8_t postDelay; /*!< Delay between the end of transfer and SSEL deassertion. */ - uint8_t frameDelay; /*!< Delay between frame to frame. */ - uint8_t transferDelay; /*!< Delay between transfer to transfer. */ -} spi_delay_config_t; - -/*! @brief SPI master user configure structure.*/ -typedef struct _spi_master_config -{ - bool enableLoopback; /*!< Enable loopback for test purpose */ - bool enableMaster; /*!< Enable SPI at initialization time */ - spi_clock_polarity_t polarity; /*!< Clock polarity */ - spi_clock_phase_t phase; /*!< Clock phase */ - spi_shift_direction_t direction; /*!< MSB or LSB */ - uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */ - spi_data_width_t dataWidth; /*!< Width of the data */ - spi_ssel_t sselNum; /*!< Slave select number */ - spi_spol_t sselPol; /*!< Configure active CS polarity */ - uint8_t txWatermark; /*!< txFIFO watermark */ - uint8_t rxWatermark; /*!< rxFIFO watermark */ - spi_delay_config_t delayConfig; /*!< Delay configuration. */ -} spi_master_config_t; - -/*! @brief SPI slave user configure structure.*/ -typedef struct _spi_slave_config -{ - bool enableSlave; /*!< Enable SPI at initialization time */ - spi_clock_polarity_t polarity; /*!< Clock polarity */ - spi_clock_phase_t phase; /*!< Clock phase */ - spi_shift_direction_t direction; /*!< MSB or LSB */ - spi_data_width_t dataWidth; /*!< Width of the data */ - spi_spol_t sselPol; /*!< Configure active CS polarity */ - uint8_t txWatermark; /*!< txFIFO watermark */ - uint8_t rxWatermark; /*!< rxFIFO watermark */ -} spi_slave_config_t; - -/*! @brief SPI transfer status.*/ -enum -{ - kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0), /*!< SPI bus is busy */ - kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1), /*!< SPI is idle */ - kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI error */ - kStatus_SPI_BaudrateNotSupport = - MAKE_STATUS(kStatusGroup_LPC_SPI, 3), /*!< Baudrate is not support in current clock source */ - kStatus_SPI_Timeout = MAKE_STATUS(kStatusGroup_LPC_SPI, 4) /*!< SPI timeout polling status flags. */ -}; - -/*! @brief SPI interrupt sources.*/ -enum _spi_interrupt_enable -{ - kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, /*!< Rx level interrupt */ - kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, /*!< Tx level interrupt */ -}; - -/*! @brief SPI status flags.*/ -enum _spi_statusflags -{ - kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK, /*!< txFifo is empty */ - kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK, /*!< txFifo is not full */ - kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, /*!< rxFIFO is not empty */ - kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK, /*!< rxFIFO is full */ -}; - -/*! @brief SPI transfer structure */ -typedef struct _spi_transfer -{ - uint8_t *txData; /*!< Send buffer */ - uint8_t *rxData; /*!< Receive buffer */ - uint32_t configFlags; /*!< Additional option to control transfer, @ref spi_xfer_option_t. */ - size_t dataSize; /*!< Transfer bytes */ -} spi_transfer_t; - -/*! @brief SPI half-duplex(master only) transfer structure */ -typedef struct _spi_half_duplex_transfer -{ - uint8_t *txData; /*!< Send buffer */ - uint8_t *rxData; /*!< Receive buffer */ - size_t txDataSize; /*!< Transfer bytes for transmit */ - size_t rxDataSize; /*!< Transfer bytes */ - uint32_t configFlags; /*!< Transfer configuration flags, @ref spi_xfer_option_t. */ - bool isPcsAssertInTransfer; /*!< If PCS pin keep assert between transmit and receive. true for assert and false for - deassert. */ - bool isTransmitFirst; /*!< True for transmit first and false for receive first. */ -} spi_half_duplex_transfer_t; - -/*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */ -typedef struct _spi_config -{ - spi_data_width_t dataWidth; - spi_ssel_t sselNum; -} spi_config_t; - -/*! @brief Master handle type */ -typedef struct _spi_master_handle spi_master_handle_t; - -/*! @brief Slave handle type */ -typedef spi_master_handle_t spi_slave_handle_t; - -/*! @brief SPI master callback for finished transmit */ -typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI slave callback for finished transmit */ -typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI transfer handle structure */ -struct _spi_master_handle -{ - uint8_t *volatile txData; /*!< Transfer buffer */ - uint8_t *volatile rxData; /*!< Receive buffer */ - volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */ - volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */ - volatile int8_t toReceiveCount; /*!< The number of data expected to receive in data width. Since the received count - and sent count should be the same to complete the transfer, if the sent count is - x and the received count is y, toReceiveCount is x-y. */ - size_t totalByteCount; /*!< A number of transfer bytes */ - volatile uint32_t state; /*!< SPI internal state */ - spi_master_callback_t callback; /*!< SPI callback */ - void *userData; /*!< Callback parameter */ - uint8_t dataWidth; /*!< Width of the data [Valid values: 1 to 16] */ - uint8_t sselNum; /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */ - uint32_t configFlags; /*!< Additional option to control transfer */ - uint8_t txWatermark; /*!< txFIFO watermark */ - uint8_t rxWatermark; /*!< rxFIFO watermark */ -}; - -/*! @brief Typedef for master interrupt handler. */ -typedef void (*flexcomm_spi_master_irq_handler_t)(SPI_Type *base, spi_master_handle_t *handle); - -/*! @brief Typedef for slave interrupt handler. */ -typedef void (*flexcomm_spi_slave_irq_handler_t)(SPI_Type *base, spi_slave_handle_t *handle); -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @brief Returns instance number for SPI peripheral base address. */ -uint32_t SPI_GetInstance(SPI_Type *base); - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Sets the SPI master configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). - * User may use the initialized structure unchanged in SPI_MasterInit(), or modify - * some fields of the structure before calling SPI_MasterInit(). After calling this API, - * the master is ready to transfer. - * Example: - @code - spi_master_config_t config; - SPI_MasterGetDefaultConfig(&config); - @endcode - * - * @param config pointer to master config structure - */ -void SPI_MasterGetDefaultConfig(spi_master_config_t *config); - -/*! - * @brief Initializes the SPI with master configuration. - * - * The configuration structure can be filled by user from scratch, or be set with default - * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. - * Example - @code - spi_master_config_t config = { - .baudRate_Bps = 400000, - ... - }; - SPI_MasterInit(SPI0, &config); - @endcode - * - * @param base SPI base pointer - * @param config pointer to master configuration structure - * @param srcClock_Hz Source clock frequency. - */ -status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Sets the SPI slave configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). - * Modify some fields of the structure before calling SPI_SlaveInit(). - * Example: - @code - spi_slave_config_t config; - SPI_SlaveGetDefaultConfig(&config); - @endcode - * - * @param config pointer to slave configuration structure - */ -void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config); - -/*! - * @brief Initializes the SPI with slave configuration. - * - * The configuration structure can be filled by user from scratch or be set with - * default values by SPI_SlaveGetDefaultConfig(). - * After calling this API, the slave is ready to transfer. - * Example - @code - spi_slave_config_t config = { - .polarity = flexSPIClockPolarity_ActiveHigh; - .phase = flexSPIClockPhase_FirstEdge; - .direction = flexSPIMsbFirst; - ... - }; - SPI_SlaveInit(SPI0, &config); - @endcode - * - * @param base SPI base pointer - * @param config pointer to slave configuration structure - */ -status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config); - -/*! - * @brief De-initializes the SPI. - * - * Calling this API resets the SPI module, gates the SPI clock. - * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. - * - * @param base SPI base pointer - */ -void SPI_Deinit(SPI_Type *base); - -/*! - * @brief Enable or disable the SPI Master or Slave - * @param base SPI base pointer - * @param enable or disable ( true = enable, false = disable) - */ -static inline void SPI_Enable(SPI_Type *base, bool enable) -{ - if (enable) - { - base->CFG |= SPI_CFG_ENABLE_MASK; - } - else - { - base->CFG &= ~SPI_CFG_ENABLE_MASK; - } -} - -/*! @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the status flag. - * - * @param base SPI base pointer - * @return SPI Status, use status flag to AND @ref _spi_statusflags could get the related status. - */ -static inline uint32_t SPI_GetStatusFlags(SPI_Type *base) -{ - assert(NULL != base); - return base->FIFOSTAT; -} - -/*! @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the interrupt for the SPI. - * - * @param base SPI base pointer - * @param irqs SPI interrupt source. The parameter can be any combination of the following values: - * @arg kSPI_RxLvlIrq - * @arg kSPI_TxLvlIrq - */ -static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs) -{ - assert(NULL != base); - base->FIFOINTENSET = irqs; -} - -/*! - * @brief Disables the interrupt for the SPI. - * - * @param base SPI base pointer - * @param irqs SPI interrupt source. The parameter can be any combination of the following values: - * @arg kSPI_RxLvlIrq - * @arg kSPI_TxLvlIrq - */ -static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs) -{ - assert(NULL != base); - base->FIFOINTENCLR = irqs; -} - -/*! @} */ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Enables the DMA request from SPI txFIFO. - * - * @param base SPI base pointer - * @param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableTxDMA(SPI_Type *base, bool enable); - -/*! - * @brief Enables the DMA request from SPI rxFIFO. - * - * @param base SPI base pointer - * @param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableRxDMA(SPI_Type *base, bool enable); - -/*! @} */ - -/*! - * @name Bus Operations - * @{ - */ -/*! - * @brief Returns the configurations. - * - * @param base SPI peripheral address. - * @return return configurations which contain datawidth and SSEL numbers. - * return data type is a pointer of spi_config_t. - */ -void *SPI_GetConfig(SPI_Type *base); - -/*! - * @brief Sets the baud rate for SPI transfer. This is only used in master. - * - * @param base SPI base pointer - * @param baudrate_Bps baud rate needed in Hz. - * @param srcClock_Hz SPI source clock frequency in Hz. - */ -status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Writes a data into the SPI data register. - * - * @param base SPI base pointer - * @param data needs to be write. - * @param configFlags transfer configuration options @ref spi_xfer_option_t - */ -void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags); - -/*! - * @brief Gets a data from the SPI data register. - * - * @param base SPI base pointer - * @return Data in the register. - */ -static inline uint32_t SPI_ReadData(SPI_Type *base) -{ - assert(NULL != base); - return base->FIFORD; -} - -/*! - * @brief Set delay time for transfer. - * the delay uint is SPI clock time, maximum value is 0xF. - * @param base SPI base pointer - * @param config configuration for delay option @ref spi_delay_config_t. - */ -static inline void SPI_SetTransferDelay(SPI_Type *base, const spi_delay_config_t *config) -{ - assert(NULL != base); - assert(NULL != config); - base->DLY = (SPI_DLY_PRE_DELAY(config->preDelay) | SPI_DLY_POST_DELAY(config->postDelay) | - SPI_DLY_FRAME_DELAY(config->frameDelay) | SPI_DLY_TRANSFER_DELAY(config->transferDelay)); -} - -/*! - * @brief Set up the dummy data. - * - * @param base SPI peripheral address. - * @param dummyData Data to be transferred when tx buffer is NULL. - */ -void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData); - -/*! @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the SPI master handle. - * - * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback Callback function. - * @param userData User data. - */ -status_t SPI_MasterTransferCreateHandle(SPI_Type *base, - spi_master_handle_t *handle, - spi_master_callback_t callback, - void *userData); - -/*! - * @brief Transfers a block of data using a polling method. - * - * @param base SPI base pointer - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Timeout The transfer timed out and was aborted. - */ -status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer); - -/*! - * @brief Performs a non-blocking SPI interrupt transfer. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer); - -/*! - * @brief Transfers a block of data using a polling method. - * - * This function will do a half-duplex transfer for SPI master, This is a blocking function, - * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, - * users can set transmit first or receive first. - * - * @param base SPI base pointer - * @param xfer pointer to spi_half_duplex_transfer_t structure - * @return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer); - -/*! - * @brief Performs a non-blocking SPI interrupt transfer. - * - * This function using polling way to do the first half transimission and using interrupts to - * do the second half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_half_duplex_transfer_t structure - * @return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, - spi_master_handle_t *handle, - spi_half_duplex_transfer_t *xfer); - -/*! - * @brief Gets the master transfer count. - * - * This function gets the master transfer count. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * @param count The number of bytes transferred by using the non-blocking transaction. - * @return status of status_t. - */ -status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count); - -/*! - * @brief SPI master aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle); - -/*! - * @brief Interrupts the handler for the SPI. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle); - -/*! - * @brief Initializes the SPI slave handle. - * - * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback Callback function. - * @param userData User data. - */ -static inline status_t SPI_SlaveTransferCreateHandle(SPI_Type *base, - spi_slave_handle_t *handle, - spi_slave_callback_t callback, - void *userData) -{ - return SPI_MasterTransferCreateHandle(base, handle, callback, userData); -} - -/*! - * @brief Performs a non-blocking SPI slave interrupt transfer. - * - * @note The API returns immediately after the transfer initialization is finished. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer) -{ - return SPI_MasterTransferNonBlocking(base, handle, xfer); -} - -/*! - * @brief Gets the slave transfer count. - * - * This function gets the slave transfer count. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * @param count The number of bytes transferred by using the non-blocking transaction. - * @return status of status_t. - */ -static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count) -{ - return SPI_MasterTransferGetCount(base, (spi_master_handle_t *)handle, count); -} - -/*! - * @brief SPI slave aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state. - */ -static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle) -{ - SPI_MasterTransferAbort(base, (spi_master_handle_t *)handle); -} - -/*! - * @brief Interrupts a handler for the SPI slave. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_slave_handle_t structure which stores the transfer state - */ -static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle) -{ - SPI_MasterTransferHandleIRQ(base, handle); -} - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_SPI_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_spi_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_spi_dma.c deleted file mode 100644 index ed0aaa6a9fa..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_spi_dma.c +++ /dev/null @@ -1,568 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_spi_dma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi_dma" -#endif - -/*configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; - *fifowr |= ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; -} - -static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr) -{ - *fifowr |= ((uint32_t)SPI_DEASSERT_ALL & (~(uint32_t)SPI_DEASSERTNUM_SSEL((uint32_t)config->sselNum))); - /* set width of data - range asserted at entry */ - *fifowr |= SPI_FIFOWR_LEN(config->dataWidth); -} - -static void PrepareTxLastWord(spi_transfer_t *xfer, uint32_t *txLastWord, spi_config_t *config) -{ - if (config->dataWidth > kSPI_Data8Bits) - { - *txLastWord = (((uint32_t)xfer->txData[xfer->dataSize - 1U] << 8U) | (xfer->txData[xfer->dataSize - 2U])); - } - else - { - *txLastWord = xfer->txData[xfer->dataSize - 1U]; - } - XferToFifoWR(xfer, txLastWord); - SpiConfigToFifoWR(config, txLastWord); -} - -static void SPI_SetupDummy(SPI_Type *base, spi_dma_txdummy_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p) -{ - uint32_t instance = SPI_GetInstance(base); - uint32_t dummydata = (uint32_t)s_dummyData[instance]; - dummydata |= (uint32_t)s_dummyData[instance] << 8U; - - dummy->word = dummydata; - dummy->lastWord = dummydata; - - XferToFifoWR(xfer, &dummy->word); - XferToFifoWR(xfer, &dummy->lastWord); - SpiConfigToFifoWR(spi_config_p, &dummy->word); - SpiConfigToFifoWR(spi_config_p, &dummy->lastWord); - /* Clear the end of transfer bit for continue word transfer. */ - dummy->word &= (~(uint32_t)kSPI_FrameAssert); -} - -/*! - * brief Initialize the SPI master DMA handle. - * - * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * param base SPI peripheral base address. - * param handle SPI handle pointer. - * param callback User callback function called at the end of a transfer. - * param userData User data for callback. - * param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle) -{ - uint32_t instance; - - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } - /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - instance = SPI_GetInstance(base); - - (void)memset(handle, 0, sizeof(*handle)); - /* Set spi base to handle */ - handle->txHandle = txHandle; - handle->rxHandle = rxHandle; - handle->callback = callback; - handle->userData = userData; - - /* Set SPI state to idle */ - handle->state = (uint8_t)kSPI_Idle; - - /* Set handle to global state */ - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - /* Install callback for Tx dma channel */ - DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]); - DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]); - - return kStatus_Success; -} - -/*! - * brief Perform a non-blocking SPI transfer using DMA. - * - * note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * param base SPI peripheral base address. - * param handle SPI DMA handle pointer. - * param xfer Pointer to dma transfer structure. - * retval kStatus_Success Successfully start a transfer. - * retval kStatus_InvalidArgument Input argument is invalid. - * retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) -{ - assert(!((NULL == handle) || (NULL == xfer))); - - uint32_t instance; - status_t result = kStatus_Success; - spi_config_t *spi_config_p; - uint32_t address; - - if ((NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - - /* Byte size is zero. */ - if (xfer->dataSize == 0U) - { - return kStatus_InvalidArgument; - } - /* cannot get instance from base address */ - instance = SPI_GetInstance(base); - - /* Check if the device is busy */ - if (handle->state == (uint8_t)kSPI_Busy) - { - return kStatus_SPI_Busy; - } - else - { - /* Clear FIFOs before transfer. */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - - dma_transfer_config_t xferConfig = {0}; - spi_config_p = (spi_config_t *)SPI_GetConfig(base); - - handle->state = (uint8_t)kSPI_Busy; - handle->transferSize = xfer->dataSize; - - /* receive */ - SPI_EnableRxDMA(base, true); - address = (uint32_t)&base->FIFORD; - if (xfer->rxData != NULL) - { - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, xfer->rxData, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_PeripheralToMemory, NULL); - } - else - { - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, &s_rxDummy, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_StaticToStatic, NULL); - } - (void)DMA_SubmitTransfer(handle->rxHandle, &xferConfig); - handle->rxInProgress = true; - DMA_StartTransfer(handle->rxHandle); - - /* transmit */ - SPI_EnableTxDMA(base, true); - address = (uint32_t)&base->FIFOWR; - if (xfer->txData != NULL) - { - if ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) - { - PrepareTxLastWord(xfer, &s_txLastWord[instance], spi_config_p); - } - /* If end of tranfer function is enabled and data transfer frame is bigger then 1, use dma - * descriptor to send the last data. - */ - if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2U) : (xfer->dataSize > 1U))) - { - dma_xfercfg_t tmp_xfercfg; - tmp_xfercfg.valid = true; - tmp_xfercfg.swtrig = true; - tmp_xfercfg.intA = true; - tmp_xfercfg.byteWidth = 4U; - tmp_xfercfg.srcInc = 0; - tmp_xfercfg.dstInc = 0; - tmp_xfercfg.transferCount = 1; - tmp_xfercfg.reload = false; - tmp_xfercfg.clrtrig = false; - tmp_xfercfg.intB = false; - /* Create chained descriptor to transmit last word */ - DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txLastWord[instance], - (uint32_t *)address, NULL); - - DMA_PrepareTransfer( - &xferConfig, xfer->txData, (uint32_t *)address, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2U) : (xfer->dataSize - 1U)), - kDMA_MemoryToPeripheral, &s_spi_descriptor_table[instance]); - /* Disable interrupts for first descriptor to avoid calling callback twice. */ - xferConfig.xfercfg.intA = false; - xferConfig.xfercfg.intB = false; - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - else - { - DMA_PrepareTransfer( - &xferConfig, xfer->txData, (uint32_t *)address, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_MemoryToPeripheral, NULL); - (void)DMA_SubmitTransfer(handle->txHandle, &xferConfig); - } - } - else - { - /* Setup tx dummy data. */ - SPI_SetupDummy(base, &s_txDummy[instance], xfer, spi_config_p); - if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2U) : (xfer->dataSize > 1U))) - { - dma_xfercfg_t tmp_xfercfg; - tmp_xfercfg.valid = true; - tmp_xfercfg.swtrig = true; - tmp_xfercfg.intA = true; - tmp_xfercfg.byteWidth = (uint8_t)sizeof(uint32_t); - tmp_xfercfg.srcInc = 0; - tmp_xfercfg.dstInc = 0; - tmp_xfercfg.transferCount = 1; - tmp_xfercfg.reload = false; - tmp_xfercfg.clrtrig = false; - tmp_xfercfg.intB = false; - /* Create chained descriptor to transmit last word */ - DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord, - (uint32_t *)address, NULL); - /* Use common API to setup first descriptor */ - DMA_PrepareTransfer( - &xferConfig, &s_txDummy[instance].word, (uint32_t *)address, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2U) : (xfer->dataSize - 1U)), - kDMA_StaticToStatic, &s_spi_descriptor_table[instance]); - /* Disable interrupts for first descriptor to avoid calling callback twice */ - xferConfig.xfercfg.intA = false; - xferConfig.xfercfg.intB = false; - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - else - { - DMA_PrepareTransfer( - &xferConfig, &s_txDummy[instance].word, (uint32_t *)address, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_StaticToStatic, NULL); - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - } - - handle->txInProgress = true; - uint32_t tmpData = 0U; - uint32_t writeAddress = (uint32_t) & (base->FIFOWR) + 2UL; - XferToFifoWR(xfer, &tmpData); - SpiConfigToFifoWR(spi_config_p, &tmpData); - - /* Setup the control info. - * Halfword writes to just the control bits (offset 0xE22) doesn't push anything into the FIFO. - * And the data access type of control bits must be uint16_t, byte writes or halfword writes to FIFOWR - * will push the data and the current control bits into the FIFO. - */ - if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize == 2U) : (xfer->dataSize == 1U))) - { - *(uint16_t *)writeAddress = (uint16_t)(tmpData >> 16U); - } - else - { - /* Clear the SPI_FIFOWR_EOT_MASK bit when data is not the last. */ - tmpData &= (~(uint32_t)kSPI_FrameAssert); - *(uint16_t *)writeAddress = (uint16_t)(tmpData >> 16U); - } - - DMA_StartTransfer(handle->txHandle); - } - - return result; -} - -/*! - * brief Transfers a block of data using a DMA method. - * - * This function using polling way to do the first half transimission and using DMA way to - * do the srcond half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * param base SPI base pointer - * param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. - * param transfer A pointer to the spi_half_duplex_transfer_t structure. - * return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer) -{ - assert((xfer != NULL) && (handle != NULL)); - spi_transfer_t tempXfer = {0}; - status_t status; - - if (xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the pcs pin keep assert between transmit and receive. */ - if (xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); - } - else - { - tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; - } - - status = SPI_MasterTransferBlocking(base, &tempXfer); - if (status != kStatus_Success) - { - return status; - } - - if (xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - status = SPI_MasterTransferDMA(base, handle, &tempXfer); - - return status; -} - -static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) -{ - spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; - spi_dma_handle_t *spiHandle = privHandle->handle; - SPI_Type *base = privHandle->base; - - /* change the state */ - spiHandle->rxInProgress = false; - - /* All finished, call the callback */ - if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) - { - spiHandle->state = (uint8_t)kSPI_Idle; - if (spiHandle->callback != NULL) - { - (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); - } - } -} - -static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) -{ - spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; - spi_dma_handle_t *spiHandle = privHandle->handle; - SPI_Type *base = privHandle->base; - - /* change the state */ - spiHandle->txInProgress = false; - - /* All finished, call the callback */ - if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) - { - spiHandle->state = (uint8_t)kSPI_Idle; - if (spiHandle->callback != NULL) - { - (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); - } - } -} - -/*! - * brief Abort a SPI transfer using DMA. - * - * param base SPI peripheral base address. - * param handle SPI DMA handle pointer. - */ -void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) -{ - assert(NULL != handle); - - /* Stop tx transfer first */ - DMA_AbortTransfer(handle->txHandle); - /* Then rx transfer */ - DMA_AbortTransfer(handle->rxHandle); - - /* Set the handle state */ - handle->txInProgress = false; - handle->rxInProgress = false; - handle->state = (uint8_t)kSPI_Idle; -} - -/*! - * brief Gets the master DMA transfer remaining bytes. - * - * This function gets the master DMA transfer remaining bytes. - * - * param base SPI peripheral base address. - * param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * param count A number of bytes transferred by the non-blocking transaction. - * return status of status_t. - */ -status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != (uint8_t)kSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - size_t bytes; - - bytes = DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel); - - *count = handle->transferSize - bytes; - - return kStatus_Success; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_spi_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_spi_dma.h deleted file mode 100644 index 614c37d791a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_spi_dma.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SPI_DMA_H_ -#define _FSL_SPI_DMA_H_ - -#include "fsl_dma.h" -#include "fsl_spi.h" - -/*! - * @addtogroup spi_dma_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SPI DMA driver version 2.1.1. */ -#define FSL_SPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) -/*@}*/ - -typedef struct _spi_dma_handle spi_dma_handle_t; - -/*! @brief SPI DMA callback called at the end of transfer. */ -typedef void (*spi_dma_callback_t)(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI DMA transfer handle, users should not touch the content of the handle.*/ -struct _spi_dma_handle -{ - volatile bool txInProgress; /*!< Send transfer finished */ - volatile bool rxInProgress; /*!< Receive transfer finished */ - dma_handle_t *txHandle; /*!< DMA handler for SPI send */ - dma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ - uint8_t bytesPerFrame; /*!< Bytes in a frame for SPI transfer */ - spi_dma_callback_t callback; /*!< Callback for SPI DMA transfer */ - void *userData; /*!< User Data for SPI DMA callback */ - uint32_t state; /*!< Internal state of SPI DMA transfer */ - size_t transferSize; /*!< Bytes need to be transfer */ -}; - -/******************************************************************************* - * APIs - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name DMA Transactional - * @{ - */ - -/*! - * @brief Initialize the SPI master DMA handle. - * - * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback User callback function called at the end of a transfer. - * @param userData User data for callback. - * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle); - -/*! - * @brief Perform a non-blocking SPI transfer using DMA. - * - * @note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - * @param xfer Pointer to dma transfer structure. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer); - -/*! - * @brief Transfers a block of data using a DMA method. - * - * This function using polling way to do the first half transimission and using DMA way to - * do the srcond half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * @param base SPI base pointer - * @param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. - * @param xfer A pointer to the spi_half_duplex_transfer_t structure. - * @return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer); - -/*! - * @brief Initialize the SPI slave DMA handle. - * - * This function initializes the SPI slave DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback User callback function called at the end of a transfer. - * @param userData User data for callback. - * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -static inline status_t SPI_SlaveTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle) -{ - return SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle); -} - -/*! - * @brief Perform a non-blocking SPI transfer using DMA. - * - * @note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - * @param xfer Pointer to dma transfer structure. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -static inline status_t SPI_SlaveTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) -{ - return SPI_MasterTransferDMA(base, handle, xfer); -} - -/*! - * @brief Abort a SPI transfer using DMA. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - */ -void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle); - -/*! - * @brief Gets the master DMA transfer remaining bytes. - * - * This function gets the master DMA transfer remaining bytes. - * - * @param base SPI peripheral base address. - * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * @param count A number of bytes transferred by the non-blocking transaction. - * @return status of status_t. - */ -status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count); - -/*! - * @brief Abort a SPI transfer using DMA. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - */ -static inline void SPI_SlaveTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) -{ - SPI_MasterTransferAbortDMA(base, handle); -} - -/*! - * @brief Gets the slave DMA transfer remaining bytes. - * - * This function gets the slave DMA transfer remaining bytes. - * - * @param base SPI peripheral base address. - * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * @param count A number of bytes transferred by the non-blocking transaction. - * @return status of status_t. - */ -static inline status_t SPI_SlaveTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) -{ - return SPI_MasterTransferGetCountDMA(base, handle, count); -} - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_SPI_DMA_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_sysctl.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_sysctl.c deleted file mode 100644 index 1d0dd9ccf64..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_sysctl.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sysctl.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.sysctl" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get the instance. - * - * @param base SYSCTL peripheral base address. - * @return Instance number. - */ -static uint32_t SYSCTL_GetInstance(SYSCTL_Type *base); - -/*! - * @brief Enable SYSCTL write protect - * - * @param base SYSCTL peripheral base address. - * @param regAddr register address - * @param value value to write. - */ -static void SYSCTL_UpdateRegister(SYSCTL_Type *base, volatile uint32_t *regAddr, uint32_t value); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief SYSCTL base address array name */ -static SYSCTL_Type *const s_sysctlBase[] = SYSCTL_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief SYSCTL clock array name */ -static const clock_ip_name_t s_sysctlClock[] = SYSCTL_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static void SYSCTL_UpdateRegister(SYSCTL_Type *base, volatile uint32_t *regAddr, uint32_t value) -{ - base->UPDATELCKOUT &= ~SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK; - *regAddr = value; - base->UPDATELCKOUT |= SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK; -} - -static uint32_t SYSCTL_GetInstance(SYSCTL_Type *base) -{ - uint8_t instance = 0; - - while ((instance < ARRAY_SIZE(s_sysctlBase)) && (s_sysctlBase[instance] != base)) - { - instance++; - } - - assert(instance < ARRAY_SIZE(s_sysctlBase)); - - return instance; -} - -/*! - * @brief SYSCTL initial - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Init(SYSCTL_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable SYSCTL clock. */ - CLOCK_EnableClock(s_sysctlClock[SYSCTL_GetInstance(base)]); -#endif -} - -/*! - * @brief SYSCTL deinit - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Deinit(SYSCTL_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable SYSCTL clock. */ - CLOCK_DisableClock(s_sysctlClock[SYSCTL_GetInstance(base)]); -#endif -} - -/*! - * @brief SYSCTL share set configure for separate signal - * - * @param base Base address of the SYSCTL peripheral - * @param flexCommIndex index of flexcomm,reference _sysctl_share_src - * @param setIndex share set for sck, reference _sysctl_share_set_index - * - */ -void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set) -{ - uint32_t tempReg = base->FCCTRLSEL[flexCommIndex]; - - tempReg &= ~((uint32_t)SYSCTL_FCCTRLSEL_SCKINSEL_MASK << (uint32_t)signal); - tempReg |= (set + 1U) << (uint32_t)signal; - - SYSCTL_UpdateRegister(base, &base->FCCTRLSEL[flexCommIndex], tempReg); -} - -/*! - * @brief SYSCTL share set configure for flexcomm - * - * @param base Base address of the SYSCTL peripheral. - * @param flexCommIndex index of flexcomm, reference _sysctl_share_src - * @param sckSet share set for sck,reference _sysctl_share_set_index - * @param wsSet share set for ws, reference _sysctl_share_set_index - * @param dataInSet share set for data in, reference _sysctl_share_set_index - * @param dataOutSet share set for data out, reference _sysctl_share_set_index - * - */ -void SYSCTL_SetFlexcommShareSet( - SYSCTL_Type *base, uint32_t flexCommIndex, uint32_t sckSet, uint32_t wsSet, uint32_t dataInSet, uint32_t dataOutSet) -{ - uint32_t tempReg = base->FCCTRLSEL[flexCommIndex]; - - tempReg &= ~(SYSCTL_FCCTRLSEL_SCKINSEL_MASK | SYSCTL_FCCTRLSEL_WSINSEL_MASK | SYSCTL_FCCTRLSEL_DATAINSEL_MASK | - SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK); - tempReg |= SYSCTL_FCCTRLSEL_SCKINSEL(sckSet + 1U) | SYSCTL_FCCTRLSEL_WSINSEL(wsSet + 1U) | - SYSCTL_FCCTRLSEL_DATAINSEL(dataInSet + 1U) | SYSCTL_FCCTRLSEL_DATAOUTSEL(dataOutSet + 1U); - - SYSCTL_UpdateRegister(base, &base->FCCTRLSEL[flexCommIndex], tempReg); -} - -/*! - * @brief SYSCTL share set source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param sckShareSrc sck source for this share set,reference _sysctl_share_src - * @param wsShareSrc ws source for this share set,reference _sysctl_share_src - * @param dataInShareSrc data in source for this share set,reference _sysctl_share_src - * @param dataOutShareSrc data out source for this share set,reference _sysctl_dataout_mask - * - */ -void SYSCTL_SetShareSetSrc(SYSCTL_Type *base, - uint32_t setIndex, - uint32_t sckShareSrc, - uint32_t wsShareSrc, - uint32_t dataInShareSrc, - uint32_t dataOutShareSrc) -{ - uint32_t tempReg = base->SHAREDCTRLSET[setIndex]; - - /* WS,SCK,DATA IN */ - tempReg &= ~(SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK | SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK | - SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK); - tempReg |= SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(sckShareSrc) | SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(wsShareSrc) | - SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(dataInShareSrc); - - /* data out */ - tempReg &= ~(SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK | SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK | - SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK | SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK | - SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK); - tempReg |= dataOutShareSrc; - - SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg); -} - -/*! - * @brief SYSCTL sck source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param sckShareSrc sck source fro this share set,reference _sysctl_share_src - * - */ -void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base, - uint32_t setIndex, - sysctl_sharedctrlset_signal_t signal, - uint32_t shareSrc) -{ - uint32_t tempReg = base->SHAREDCTRLSET[setIndex]; - - if (signal == kSYSCTL_SharedCtrlSignalDataOut) - { - tempReg |= 1UL << ((uint32_t)signal + shareSrc); - } - else - { - tempReg &= ~((uint32_t)SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK << (uint32_t)signal); - tempReg |= shareSrc << (uint32_t)signal; - } - - SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg); -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_sysctl.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_sysctl.h deleted file mode 100644 index 0a1be88469c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_sysctl.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_SYSCTL_H_ -#define _FSL_SYSCTL_H_ - -#include "fsl_common.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup sysctl - * @{ - */ - -/*! @file */ -/*! @file fsl_sysctl.h */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Group sysctl driver version for SDK */ -#define FSL_SYSCTL_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) /*!< Version 2.0.5. */ -/*@}*/ - -/*! @brief SYSCTL share set*/ -enum _sysctl_share_set_index -{ - kSYSCTL_ShareSet0 = 0, /*!< share set 0 */ - kSYSCTL_ShareSet1 = 1, /*!< share set 1 */ -}; - -/*! @brief SYSCTL flexcomm signal */ -typedef enum _sysctl_fcctrlsel_signal -{ - kSYSCTL_FlexcommSignalSCK = SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT, /*!< SCK signal */ - kSYSCTL_FlexcommSignalWS = SYSCTL_FCCTRLSEL_WSINSEL_SHIFT, /*!< WS signal */ - kSYSCTL_FlexcommSignalDataIn = SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT, /*!< Data in signal */ - kSYSCTL_FlexcommSignalDataOut = SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT, /*!< Data out signal */ -} sysctl_fcctrlsel_signal_t; - -/*! @brief SYSCTL flexcomm index*/ -enum _sysctl_share_src -{ - kSYSCTL_Flexcomm0 = 0, /*!< share set 0 */ - kSYSCTL_Flexcomm1 = 1, /*!< share set 1 */ - kSYSCTL_Flexcomm2 = 2, /*!< share set 2 */ - kSYSCTL_Flexcomm4 = 4, /*!< share set 4 */ - kSYSCTL_Flexcomm5 = 5, /*!< share set 5 */ - kSYSCTL_Flexcomm6 = 6, /*!< share set 6 */ - kSYSCTL_Flexcomm7 = 7, /*!< share set 7 */ -}; - -/*! @brief SYSCTL shared data out mask */ -enum _sysctl_dataout_mask -{ - kSYSCTL_Flexcomm0DataOut = SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK, /*!< share set 0 */ - kSYSCTL_Flexcomm1DataOut = SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK, /*!< share set 1 */ - kSYSCTL_Flexcomm2DataOut = SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK, /*!< share set 2 */ - kSYSCTL_Flexcomm4DataOut = SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK, /*!< share set 4 */ - kSYSCTL_Flexcomm5DataOut = SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK, /*!< share set 5 */ - kSYSCTL_Flexcomm6DataOut = SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK, /*!< share set 6 */ - kSYSCTL_Flexcomm7DataOut = SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK, /*!< share set 7 */ -}; - -/*! @brief SYSCTL flexcomm signal */ -typedef enum _sysctl_sharedctrlset_signal -{ - kSYSCTL_SharedCtrlSignalSCK = SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT, /*!< SCK signal */ - kSYSCTL_SharedCtrlSignalWS = SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT, /*!< WS signal */ - kSYSCTL_SharedCtrlSignalDataIn = SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT, /*!< Data in signal */ - kSYSCTL_SharedCtrlSignalDataOut = SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT, /*!< Data out signal */ -} sysctl_sharedctrlset_signal_t; -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief SYSCTL initial - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Init(SYSCTL_Type *base); - -/*! - * @brief SYSCTL deinit - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Deinit(SYSCTL_Type *base); - -/* @} */ - -/*! - * @name SYSCTL share signal configure - * @{ - */ - -/*! - * @brief SYSCTL share set configure for flexcomm - * - * @param base Base address of the SYSCTL peripheral. - * @param flexCommIndex index of flexcomm, reference _sysctl_share_src - * @param sckSet share set for sck,reference _sysctl_share_set_index - * @param wsSet share set for ws, reference _sysctl_share_set_index - * @param dataInSet share set for data in, reference _sysctl_share_set_index - * @param dataOutSet share set for data out, reference _sysctl_dataout_mask - * - */ -void SYSCTL_SetFlexcommShareSet(SYSCTL_Type *base, - uint32_t flexCommIndex, - uint32_t sckSet, - uint32_t wsSet, - uint32_t dataInSet, - uint32_t dataOutSet); - -/*! - * @brief SYSCTL share set configure for separate signal - * - * @param base Base address of the SYSCTL peripheral - * @param flexCommIndex index of flexcomm,reference _sysctl_share_src - * @param signal FCCTRLSEL signal shift - * @param set share set for sck, reference _sysctl_share_set_index - * - */ -void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set); - -/*! - * @brief SYSCTL share set source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param sckShareSrc sck source for this share set,reference _sysctl_share_src - * @param wsShareSrc ws source for this share set,reference _sysctl_share_src - * @param dataInShareSrc data in source for this share set,reference _sysctl_share_src - * @param dataOutShareSrc data out source for this share set,reference _sysctl_dataout_mask - * - */ -void SYSCTL_SetShareSetSrc(SYSCTL_Type *base, - uint32_t setIndex, - uint32_t sckShareSrc, - uint32_t wsShareSrc, - uint32_t dataInShareSrc, - uint32_t dataOutShareSrc); - -/*! - * @brief SYSCTL sck source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param signal FCCTRLSEL signal shift - * @param shareSrc sck source fro this share set,reference _sysctl_share_src - * - */ -void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base, - uint32_t setIndex, - sysctl_sharedctrlset_signal_t signal, - uint32_t shareSrc); - -/* @} */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_SYSCTL_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_usart.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_usart.c deleted file mode 100644 index 3286174f27b..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_usart.c +++ /dev/null @@ -1,1206 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_usart.h" -#include "fsl_device_registers.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart" -#endif - -/*! - * @brief Used for conversion from `flexcomm_usart_irq_handler_t` to `flexcomm_irq_handler_t` - */ -typedef union usart_to_flexcomm -{ - flexcomm_usart_irq_handler_t usart_master_handler; - flexcomm_irq_handler_t flexcomm_handler; -} usart_to_flexcomm_t; - -enum -{ - kUSART_TxIdle, /* TX idle. */ - kUSART_TxBusy, /* TX busy. */ - kUSART_RxIdle, /* RX idle. */ - kUSART_RxBusy /* RX busy. */ -}; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief IRQ name array */ -static const IRQn_Type s_usartIRQ[] = USART_IRQS; - -/*! @brief Array to map USART instance number to base address. */ -static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Get the index corresponding to the USART */ -/*! brief Returns instance number for USART peripheral base address. */ -uint32_t USART_GetInstance(USART_Type *base) -{ - uint32_t i; - - for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT; i++) - { - if ((uint32_t)base == s_usartBaseAddrs[i]) - { - break; - } - } - - assert(i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT); - return i; -} - -/*! - * brief Get the length of received data in RX ring buffer. - * - * param handle USART handle pointer. - * return Length of received data in RX ring buffer. - */ -size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) -{ - size_t size; - - /* Check arguments */ - assert(NULL != handle); - uint16_t rxRingBufferHead = handle->rxRingBufferHead; - uint16_t rxRingBufferTail = handle->rxRingBufferTail; - - if (rxRingBufferTail > rxRingBufferHead) - { - size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail; - } - else - { - size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail; - } - return size; -} - -static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle) -{ - bool full; - - /* Check arguments */ - assert(NULL != handle); - - if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) - { - full = true; - } - else - { - full = false; - } - return full; -} - -/*! - * brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific USART handle. - * - * When the RX ring buffer is used, data received are stored into the ring buffer even when the - * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * - * note When using the RX ring buffer, one byte is reserved for internal use. In other - * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. - * param ringBufferSize size of the ring buffer. - */ -void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) -{ - /* Check arguments */ - assert(NULL != base); - assert(NULL != handle); - assert(NULL != ringBuffer); - - /* Setup the ringbuffer address */ - handle->rxRingBuffer = ringBuffer; - handle->rxRingBufferSize = ringBufferSize; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; - /* ring buffer is ready we can start receiving data */ - base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -} - -/*! - * brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) -{ - /* Check arguments */ - assert(NULL != base); - assert(NULL != handle); - - if (handle->rxState == (uint8_t)kUSART_RxIdle) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK; - } - handle->rxRingBuffer = NULL; - handle->rxRingBufferSize = 0U; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; -} - -/*! - * brief Initializes a USART instance with user configuration structure and peripheral clock. - * - * This function configures the USART module with the user-defined settings. The user can configure the configuration - * structure and also get the default configuration by using the USART_GetDefaultConfig() function. - * Example below shows how to use this API to configure USART. - * code - * usart_config_t usartConfig; - * usartConfig.baudRate_Bps = 115200U; - * usartConfig.parityMode = kUSART_ParityDisabled; - * usartConfig.stopBitCount = kUSART_OneStopBit; - * USART_Init(USART1, &usartConfig, 20000000U); - * endcode - * - * param base USART peripheral base address. - * param config Pointer to user-defined configuration structure. - * param srcClock_Hz USART clock source frequency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_InvalidArgument USART base address is not valid - * retval kStatus_Success Status USART initialize succeed - */ -status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz) -{ - int result; - - /* check arguments */ - assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); - if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* initialize flexcomm to USART mode */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART); - if (kStatus_Success != result) - { - return result; - } - - if (config->enableTx) - { - /* empty and enable txFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK; - /* setup trigger level */ - base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK); - base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark); - /* enable trigger interrupt */ - base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK; - } - - /* empty and enable rxFIFO */ - if (config->enableRx) - { - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK; - /* setup trigger level */ - base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK); - base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable trigger interrupt */ - base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK; - } - /* setup configuration and enable USART */ - base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | - USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | - USART_CFG_SYNCEN((uint32_t)config->syncMode >> 1) | USART_CFG_SYNCMST((uint8_t)config->syncMode) | - USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_MODE32K(config->enableMode32k) | - USART_CFG_CTSEN(config->enableHardwareFlowControl) | USART_CFG_ENABLE_MASK; - - /* Setup baudrate */ - if (config->enableMode32k) - { - if ((9600U % config->baudRate_Bps) == 0U) - { - base->BRG = 9600U / config->baudRate_Bps; - } - else - { - return kStatus_USART_BaudrateNotSupport; - } - } - else - { - result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - } - /* Setting continuous Clock configuration. used for synchronous mode. */ - USART_EnableContinuousSCLK(base, config->enableContinuousSCLK); - - return kStatus_Success; -} - -/*! - * brief Deinitializes a USART instance. - * - * This function waits for TX complete, disables TX and RX, and disables the USART clock. - * - * param base USART peripheral base address. - */ -void USART_Deinit(USART_Type *base) -{ - /* Check arguments */ - assert(NULL != base); - while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) - { - } - /* Disable interrupts, disable dma requests, disable peripheral */ - base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK | - USART_FIFOINTENCLR_RXLVL_MASK; - base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK); - base->CFG &= ~(USART_CFG_ENABLE_MASK); -} - -/*! - * brief Gets the default configuration structure. - * - * This function initializes the USART configuration structure to a default value. The default - * values are: - * usartConfig->baudRate_Bps = 115200U; - * usartConfig->parityMode = kUSART_ParityDisabled; - * usartConfig->stopBitCount = kUSART_OneStopBit; - * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; - * usartConfig->loopback = false; - * usartConfig->enableTx = false; - * usartConfig->enableRx = false; - * - * param config Pointer to configuration structure. - */ -void USART_GetDefaultConfig(usart_config_t *config) -{ - /* Check arguments */ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* Set always all members ! */ - config->baudRate_Bps = 115200U; - config->parityMode = kUSART_ParityDisabled; - config->stopBitCount = kUSART_OneStopBit; - config->bitCountPerChar = kUSART_8BitsPerChar; - config->loopback = false; - config->enableRx = false; - config->enableTx = false; - config->enableMode32k = false; - config->txWatermark = kUSART_TxFifo0; - config->rxWatermark = kUSART_RxFifo1; - config->syncMode = kUSART_SyncModeDisabled; - config->enableContinuousSCLK = false; - config->clockPolarity = kUSART_RxSampleOnFallingEdge; - config->enableHardwareFlowControl = false; -} - -/*! - * brief Sets the USART instance baud rate. - * - * This function configures the USART module baud rate. This function is used to update - * the USART module baud rate after the USART module is initialized by the USART_Init. - * code - * USART_SetBaudRate(USART1, 115200U, 20000000U); - * endcode - * - * param base USART peripheral base address. - * param baudrate_Bps USART baudrate to be set. - * param srcClock_Hz USART clock source frequency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_Success Set baudrate succeed. - * retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) -{ - uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1; - uint32_t osrval, brgval, diff, baudrate; - - /* check arguments */ - assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))); - if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* If synchronous master mode is enabled, only configure the BRG value. */ - if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U) - { - if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U) - { - brgval = srcClock_Hz / baudrate_Bps; - base->BRG = brgval - 1U; - } - } - else - { - /* - * Smaller values of OSR can make the sampling position within a data bit less accurate and may - * potentially cause more noise errors or incorrect data. - */ - for (osrval = best_osrval; osrval >= 8U; osrval--) - { - brgval = (((srcClock_Hz * 10U) / ((osrval + 1U) * baudrate_Bps)) - 5U) / 10U; - if (brgval > 0xFFFFU) - { - continue; - } - baudrate = srcClock_Hz / ((osrval + 1U) * (brgval + 1U)); - diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); - if (diff < best_diff) - { - best_diff = diff; - best_osrval = osrval; - best_brgval = brgval; - } - } - - /* Check to see if actual baud rate is within 3% of desired baud rate - * based on the best calculated OSR and BRG value */ - baudrate = srcClock_Hz / ((best_osrval + 1U) * (best_brgval + 1U)); - diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); - if (diff > ((baudrate_Bps / 100U) * 3U)) - { - return kStatus_USART_BaudrateNotSupport; - } - - /* value over range */ - if (best_brgval > 0xFFFFU) - { - return kStatus_USART_BaudrateNotSupport; - } - - base->OSR = best_osrval; - base->BRG = best_brgval; - } - - return kStatus_Success; -} - -/*! - * brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source. - * - * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator - * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting - * SYSCON_RTCOSCCTRL_EN bit to 1. - * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that - * 9600 can evenly divide, eg: 4800, 3200. - * - * param base USART peripheral base address. - * param baudRate_Bps USART baudrate to be set.. - * param enableMode32k true is 32k mode, false is normal mode. - * param srcClock_Hz USART clock source frequency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_Success Set baudrate succeed. - * retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz) -{ - status_t result = kStatus_Success; - base->CFG &= ~(USART_CFG_ENABLE_MASK); - if (enableMode32k) - { - base->CFG |= USART_CFG_MODE32K_MASK; - if ((9600U % baudRate_Bps) == 0U) - { - base->BRG = 9600U / baudRate_Bps - 1U; - } - else - { - return kStatus_USART_BaudrateNotSupport; - } - } - else - { - base->CFG &= ~(USART_CFG_MODE32K_MASK); - result = USART_SetBaudRate(base, baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - } - base->CFG |= USART_CFG_ENABLE_MASK; - return result; -} - -/*! - * brief Enable 9-bit data mode for USART. - * - * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user. - * - * param base USART peripheral base address. - * param enable true to enable, false to disable. - */ -void USART_Enable9bitMode(USART_Type *base, bool enable) -{ - assert(base != NULL); - - uint32_t temp = 0U; - - if (enable) - { - /* Set USART 9-bit mode, disable parity. */ - temp = base->CFG & ~((uint32_t)USART_CFG_DATALEN_MASK | (uint32_t)USART_CFG_PARITYSEL_MASK); - temp |= (uint32_t)USART_CFG_DATALEN(0x2U); - base->CFG = temp; - } - else - { - /* Set USART to 8-bit mode. */ - base->CFG &= ~((uint32_t)USART_CFG_DATALEN_MASK); - base->CFG |= (uint32_t)USART_CFG_DATALEN(0x1U); - } -} - -/*! - * brief Transmit an address frame in 9-bit data mode. - * - * param base USART peripheral base address. - * param address USART slave address. - */ -void USART_SendAddress(USART_Type *base, uint8_t address) -{ - assert(base != NULL); - base->FIFOWR = ((uint32_t)address | 0x100UL); -} - -/*! - * brief Writes to the TX register using a blocking method. - * - * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO - * to have room and writes data to the TX buffer. - * - * param base USART peripheral base address. - * param data Start address of the data to write. - * param length Size of the data to write. - * retval kStatus_USART_Timeout Transmission timed out and was aborted. - * retval kStatus_InvalidArgument Invalid argument. - * retval kStatus_Success Successfully wrote all data. - */ -status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) -{ - /* Check arguments */ - assert(!((NULL == base) || (NULL == data))); -#if UART_RETRY_TIMES - uint32_t waitTimes; -#endif - if ((NULL == base) || (NULL == data)) - { - return kStatus_InvalidArgument; - } - /* Check whether txFIFO is enabled */ - if (0U == (base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK)) - { - return kStatus_InvalidArgument; - } - for (; length > 0U; length--) - { - /* Loop until txFIFO get some space for new data */ -#if UART_RETRY_TIMES - waitTimes = UART_RETRY_TIMES; - while ((0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) && (--waitTimes != 0U)) -#else - while (0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) -#endif - { - } -#if UART_RETRY_TIMES - if (0U == waitTimes) - { - return kStatus_USART_Timeout; - } -#endif - base->FIFOWR = *data; - data++; - } - /* Wait to finish transfer */ -#if UART_RETRY_TIMES - waitTimes = UART_RETRY_TIMES; - while ((0U == (base->STAT & USART_STAT_TXIDLE_MASK)) && (--waitTimes != 0U)) -#else - while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) -#endif - { - } -#if UART_RETRY_TIMES - if (0U == waitTimes) - { - return kStatus_USART_Timeout; - } -#endif - return kStatus_Success; -} - -/*! - * brief Read RX data register using a blocking method. - * - * This function polls the RX register, waits for the RX register to be full or for RX FIFO to - * have data and read data from the TX register. - * - * param base USART peripheral base address. - * param data Start address of the buffer to store the received data. - * param length Size of the buffer. - * retval kStatus_USART_FramingError Receiver overrun happened while receiving data. - * retval kStatus_USART_ParityError Noise error happened while receiving data. - * retval kStatus_USART_NoiseError Framing error happened while receiving data. - * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. - * retval kStatus_USART_Timeout Transmission timed out and was aborted. - * retval kStatus_Success Successfully received all data. - */ -status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) -{ - uint32_t statusFlag; - status_t status = kStatus_Success; -#if UART_RETRY_TIMES - uint32_t waitTimes; -#endif - - /* check arguments */ - assert(!((NULL == base) || (NULL == data))); - if ((NULL == base) || (NULL == data)) - { - return kStatus_InvalidArgument; - } - - /* Check whether rxFIFO is enabled */ - if ((base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK) == 0U) - { - return kStatus_Fail; - } - for (; length > 0U; length--) - { - /* loop until rxFIFO have some data to read */ -#if UART_RETRY_TIMES - waitTimes = UART_RETRY_TIMES; - while (((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) && (--waitTimes != 0U)) -#else - while ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) -#endif - { - } -#if UART_RETRY_TIMES - if (waitTimes == 0U) - { - status = kStatus_USART_Timeout; - break; - } -#endif - /* check rxFIFO statusFlag */ - if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) - { - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; - status = kStatus_USART_RxError; - break; - } - /* check receive statusFlag */ - statusFlag = base->STAT; - /* Clear all status flags */ - base->STAT |= statusFlag; - if ((statusFlag & USART_STAT_PARITYERRINT_MASK) != 0U) - { - status = kStatus_USART_ParityError; - } - if ((statusFlag & USART_STAT_FRAMERRINT_MASK) != 0U) - { - status = kStatus_USART_FramingError; - } - if ((statusFlag & USART_STAT_RXNOISEINT_MASK) != 0U) - { - status = kStatus_USART_NoiseError; - } - - if (kStatus_Success == status) - { - *data = (uint8_t)base->FIFORD; - data++; - } - else - { - break; - } - } - return status; -} - -/*! - * brief Initializes the USART handle. - * - * This function initializes the USART handle which can be used for other USART - * transactional APIs. Usually, for a specified USART instance, - * call this API once to get the initialized handle. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param callback The callback function. - * param userData The parameter of the callback function. - */ -status_t USART_TransferCreateHandle(USART_Type *base, - usart_handle_t *handle, - usart_transfer_callback_t callback, - void *userData) -{ - /* Check 'base' */ - assert(!((NULL == base) || (NULL == handle))); - - uint32_t instance = 0; - usart_to_flexcomm_t handler; - handler.usart_master_handler = USART_TransferHandleIRQ; - - if ((NULL == base) || (NULL == handle)) - { - return kStatus_InvalidArgument; - } - - instance = USART_GetInstance(base); - - (void)memset(handle, 0, sizeof(*handle)); - /* Set the TX/RX state. */ - handle->rxState = (uint8_t)kUSART_RxIdle; - handle->txState = (uint8_t)kUSART_TxIdle; - /* Set the callback and user data. */ - handle->callback = callback; - handle->userData = userData; - handle->rxWatermark = (uint8_t)USART_FIFOTRIG_RXLVL_GET(base); - handle->txWatermark = (uint8_t)USART_FIFOTRIG_TXLVL_GET(base); - - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - - /* Enable interrupt in NVIC. */ - (void)EnableIRQ(s_usartIRQ[instance]); - - return kStatus_Success; -} - -/*! - * brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in the IRQ handler, the USART driver calls the callback - * function and passes the ref kStatus_USART_TxIdle as status parameter. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART transfer structure. See #usart_transfer_t. - * retval kStatus_Success Successfully start the data transmission. - * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer) -{ - /* Check arguments */ - assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - /* Check xfer members */ - assert(!((0U == xfer->dataSize) || (NULL == xfer->txData))); - if ((0U == xfer->dataSize) || (NULL == xfer->txData)) - { - return kStatus_InvalidArgument; - } - - /* Return error if current TX busy. */ - if ((uint8_t)kUSART_TxBusy == handle->txState) - { - return kStatus_USART_TxBusy; - } - else - { - /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up the - * handle value. */ - uint32_t interruptMask = USART_GetEnabledInterrupts(base); - USART_DisableInterrupts(base, interruptMask); - handle->txData = xfer->txData; - handle->txDataSize = xfer->dataSize; - handle->txDataSizeAll = xfer->dataSize; - handle->txState = (uint8_t)kUSART_TxBusy; - /* Enable transmiter interrupt and the previously disabled interrupt. */ - USART_EnableInterrupts(base, interruptMask | (uint32_t)kUSART_TxLevelInterruptEnable); - } - return kStatus_Success; -} - -/*! - * brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out - * how many bytes are still not sent out. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) -{ - assert(NULL != handle); - - /* Disable interrupts */ - USART_DisableInterrupts(base, (uint32_t)kUSART_TxLevelInterruptEnable); - /* Empty txFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK; - - handle->txDataSize = 0U; - handle->txState = (uint8_t)kUSART_TxIdle; -} - -/*! - * brief Get the number of bytes that have been sent out to bus. - * - * This function gets the number of bytes that have been sent out to bus by interrupt method. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Send bytes count. - * retval kStatus_NoTransferInProgress No send in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != count); - - if ((uint8_t)kUSART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - handle->txDataSize - - ((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); - - return kStatus_Success; -} - -/*! - * brief Receives a buffer of data using an interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function, which - * returns without waiting for all data to be received. - * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and - * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in the ring buffer is not enough to read, the receive - * request is saved by the USART driver. When the new data arrives, the receive request - * is serviced first. When all data is received, the USART driver notifies the upper layer - * through a callback function and passes the status parameter ref kStatus_USART_RxIdle. - * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. - * The 5 bytes are copied to the xfer->data and this function returns with the - * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is - * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to the xfer->data. When all data is received, the upper layer is notified. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART transfer structure, see #usart_transfer_t. - * param receivedBytes Bytes received from the ring buffer directly. - * retval kStatus_Success Successfully queue the transfer into transmit queue. - * retval kStatus_USART_RxBusy Previous receive request is not finished. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveNonBlocking(USART_Type *base, - usart_handle_t *handle, - usart_transfer_t *xfer, - size_t *receivedBytes) -{ - uint32_t i; - /* How many bytes to copy from ring buffer to user memory. */ - size_t bytesToCopy = 0U; - /* How many bytes to receive. */ - size_t bytesToReceive; - /* How many bytes currently have received. */ - size_t bytesCurrentReceived; - uint32_t interruptMask = 0U; - - /* Check arguments */ - assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - /* Check xfer members */ - assert(!((0U == xfer->dataSize) || (NULL == xfer->rxData))); - if ((0U == xfer->dataSize) || (NULL == xfer->rxData)) - { - return kStatus_InvalidArgument; - } - - /* Enable address detect when address match is enabled. */ - if ((base->CFG & (uint32_t)USART_CFG_AUTOADDR_MASK) != 0U) - { - base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK; - } - - /* How to get data: - 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize - to uart handle, enable interrupt to store received data to xfer->data. When - all data received, trigger callback. - 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. - If there are enough data in ring buffer, copy them to xfer->data and return. - If there are not enough data in ring buffer, copy all of them to xfer->data, - save the xfer->data remained empty space to uart handle, receive data - to this empty space and trigger callback when finished. */ - if ((uint8_t)kUSART_RxBusy == handle->rxState) - { - return kStatus_USART_RxBusy; - } - else - { - bytesToReceive = xfer->dataSize; - bytesCurrentReceived = 0U; - /* If RX ring buffer is used. */ - if (handle->rxRingBuffer != NULL) - { - /* Disable IRQ, protect ring buffer. */ - interruptMask = USART_GetEnabledInterrupts(base); - USART_DisableInterrupts(base, interruptMask); - - /* How many bytes in RX ring buffer currently. */ - bytesToCopy = USART_TransferGetRxRingBufferLength(handle); - if (bytesToCopy != 0U) - { - bytesToCopy = MIN(bytesToReceive, bytesToCopy); - bytesToReceive -= bytesToCopy; - /* Copy data from ring buffer to user memory. */ - for (i = 0U; i < bytesToCopy; i++) - { - xfer->rxData[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; - /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ - if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - } - /* If ring buffer does not have enough data, still need to read more data. */ - if (bytesToReceive != 0U) - { - /* No data in ring buffer, save the request to UART handle. */ - handle->rxData = xfer->rxData + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = xfer->dataSize; - handle->rxState = (uint8_t)kUSART_RxBusy; - } - /* Re-enable IRQ. */ - USART_EnableInterrupts(base, interruptMask); - /* Call user callback since all data are received. */ - if (0U == bytesToReceive) - { - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); - } - } - } - /* Ring buffer not used. */ - else - { - /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up - * the handle value. */ - interruptMask = USART_GetEnabledInterrupts(base); - USART_DisableInterrupts(base, interruptMask); - handle->rxData = xfer->rxData + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = (uint8_t)kUSART_RxBusy; - - /* Enable RX interrupt. */ - base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK; - /* Re-enable IRQ. */ - USART_EnableInterrupts(base, interruptMask); - } - /* Return the how many bytes have read. */ - if (receivedBytes != NULL) - { - *receivedBytes = bytesCurrentReceived; - } - } - return kStatus_Success; -} - -/*! - * brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out - * how many bytes not received yet. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) -{ - assert(NULL != handle); - - /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ - if (NULL == handle->rxRingBuffer) - { - /* Disable interrupts */ - USART_DisableInterrupts(base, (uint32_t)kUSART_RxLevelInterruptEnable); - /* Empty rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - } - - handle->rxDataSize = 0U; - handle->rxState = (uint8_t)kUSART_RxIdle; -} - -/*! - * brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Receive bytes count. - * retval kStatus_NoTransferInProgress No receive in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != count); - - if ((uint8_t)kUSART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - handle->rxDataSize; - - return kStatus_Success; -} - -/*! - * brief USART IRQ handle function. - * - * This function handles the USART transmit and receive IRQ request. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) -{ - /* Check arguments */ - assert((NULL != base) && (NULL != handle)); - - bool receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); - bool sendEnabled = (handle->txDataSize != 0U); - uint8_t rxdata; - size_t tmpsize; - - /* If RX overrun. */ - if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) - { - /* Clear rx error state. */ - base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxError, handle->userData); - } - } - /* TX under run, happens when slave is in synchronous mode and the data is not written in tx register in time. */ - if ((base->FIFOSTAT & USART_FIFOSTAT_TXERR_MASK) != 0U) - { - /* Clear tx error state. */ - base->FIFOSTAT |= USART_FIFOSTAT_TXERR_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_TxError, handle->userData); - } - } - /* If noise error. */ - if ((base->STAT & USART_STAT_RXNOISEINT_MASK) != 0U) - { - /* Clear rx error state. */ - base->STAT |= USART_STAT_RXNOISEINT_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_NoiseError, handle->userData); - } - } - /* If framing error. */ - if ((base->STAT & USART_STAT_FRAMERRINT_MASK) != 0U) - { - /* Clear rx error state. */ - base->STAT |= USART_STAT_FRAMERRINT_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_FramingError, handle->userData); - } - } - /* If parity error. */ - if ((base->STAT & USART_STAT_PARITYERRINT_MASK) != 0U) - { - /* Clear rx error state. */ - base->STAT |= USART_STAT_PARITYERRINT_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_ParityError, handle->userData); - } - } - while ((receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) || - (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U))) - { - /* Receive data */ - if (receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) - { - /* Clear address detect when RXFIFO has data. */ - base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK; - /* Receive to app bufffer if app buffer is present */ - if (handle->rxDataSize != 0U) - { - rxdata = (uint8_t)base->FIFORD; - *handle->rxData = rxdata; - handle->rxDataSize--; - handle->rxData++; - receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); - if (0U == handle->rxDataSize) - { - if (NULL == handle->rxRingBuffer) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; - } - handle->rxState = (uint8_t)kUSART_RxIdle; - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); - } - } - } - /* Otherwise receive to ring buffer if ring buffer is present */ - else - { - if (handle->rxRingBuffer != NULL) - { - /* If RX ring buffer is full, trigger callback to notify over run. */ - if (USART_TransferIsRxRingBufferFull(handle)) - { - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData); - } - } - /* If ring buffer is still full after callback function, the oldest data is overridden. */ - if (USART_TransferIsRxRingBufferFull(handle)) - { - /* Increase handle->rxRingBufferTail to make room for new data. */ - if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - /* Read data. */ - rxdata = (uint8_t)base->FIFORD; - handle->rxRingBuffer[handle->rxRingBufferHead] = rxdata; - /* Increase handle->rxRingBufferHead. */ - if ((size_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferHead = 0U; - } - else - { - handle->rxRingBufferHead++; - } - } - } - } - /* Send data */ - if (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U)) - { - base->FIFOWR = *handle->txData; - handle->txDataSize--; - handle->txData++; - sendEnabled = handle->txDataSize != 0U; - if (!sendEnabled) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK; - - base->INTENSET = USART_INTENSET_TXIDLEEN_MASK; - } - } - } - - /* Tx idle and the interrupt is enabled. */ - if ((0U != (base->INTENSET & USART_INTENSET_TXIDLEEN_MASK)) && (0U != (base->INTSTAT & USART_INTSTAT_TXIDLE_MASK))) - { - /* Set txState to idle only when all data has been sent out to bus. */ - handle->txState = (uint8_t)kUSART_TxIdle; - /* Disable tx idle interrupt */ - base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK; - - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); - } - } - - /* ring buffer is not used */ - if (NULL == handle->rxRingBuffer) - { - tmpsize = handle->rxDataSize; - - /* restore if rx transfer ends and rxLevel is different from default value */ - if ((tmpsize == 0U) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark)) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark); - } - /* decrease level if rx transfer is bellow */ - if ((tmpsize != 0U) && (tmpsize < (USART_FIFOTRIG_RXLVL_GET(base) + 1U))) - { - base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(tmpsize - 1U)); - } - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_usart.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_usart.h deleted file mode 100644 index ef4715c4c5c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_usart.h +++ /dev/null @@ -1,903 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_USART_H_ -#define _FSL_USART_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup usart_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief USART driver version. */ -#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 7, 0)) -/*@}*/ - -#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT) -#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT) - -/*! @brief Retry times for waiting flag. */ -#ifndef UART_RETRY_TIMES -#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */ -#endif - -/*! @brief Error codes for the USART driver. */ -enum -{ - kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */ - kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */ - kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */ - kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */ - kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */ - kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */ - kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */ - kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */ - kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */ - kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */ - kStatus_USART_BaudrateNotSupport = - MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */ -#if UART_RETRY_TIMES - kStatus_USART_Timeout = MAKE_STATUS(kStatusGroup_LPC_USART, 14), /*!< USART time out. */ -#endif -}; - -/*! @brief USART synchronous mode. */ -typedef enum _usart_sync_mode -{ - kUSART_SyncModeDisabled = 0x0U, /*!< Asynchronous mode. */ - kUSART_SyncModeSlave = 0x2U, /*!< Synchronous slave mode. */ - kUSART_SyncModeMaster = 0x3U, /*!< Synchronous master mode. */ -} usart_sync_mode_t; - -/*! @brief USART parity mode. */ -typedef enum _usart_parity_mode -{ - kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */ - kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ - kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ -} usart_parity_mode_t; - -/*! @brief USART stop bit count. */ -typedef enum _usart_stop_bit_count -{ - kUSART_OneStopBit = 0U, /*!< One stop bit */ - kUSART_TwoStopBit = 1U, /*!< Two stop bits */ -} usart_stop_bit_count_t; - -/*! @brief USART data size. */ -typedef enum _usart_data_len -{ - kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */ - kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */ -} usart_data_len_t; - -/*! @brief USART clock polarity configuration, used in sync mode.*/ -typedef enum _usart_clock_polarity -{ - kUSART_RxSampleOnFallingEdge = 0x0U, /*!< Un_RXD is sampled on the falling edge of SCLK. */ - kUSART_RxSampleOnRisingEdge = 0x1U, /*!< Un_RXD is sampled on the rising edge of SCLK. */ -} usart_clock_polarity_t; - -/*! @brief txFIFO watermark values */ -typedef enum _usart_txfifo_watermark -{ - kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */ - kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */ - kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */ - kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */ - kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */ - kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */ - kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */ - kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */ -} usart_txfifo_watermark_t; - -/*! @brief rxFIFO watermark values */ -typedef enum _usart_rxfifo_watermark -{ - kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */ - kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */ - kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */ - kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */ - kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */ - kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */ - kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */ - kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */ -} usart_rxfifo_watermark_t; - -/*! - * @brief USART interrupt configuration structure, default settings all disabled. - */ -enum _usart_interrupt_enable -{ - kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK), - kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK), - kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK), - kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK), - kUSART_TxIdleInterruptEnable = (USART_INTENSET_TXIDLEEN_MASK << 16U), /*!< Transmitter idle. */ - kUSART_CtsChangeInterruptEnable = - (USART_INTENSET_DELTACTSEN_MASK << 16U), /*!< Change in the state of the CTS input. */ - kUSART_RxBreakChangeInterruptEnable = - (USART_INTENSET_DELTARXBRKEN_MASK), /*!< Break condition asserted or deasserted. */ - kUSART_RxStartInterruptEnable = (USART_INTENSET_STARTEN_MASK), /*!< Rx start bit detected. */ - kUSART_FramingErrorInterruptEnable = (USART_INTENSET_FRAMERREN_MASK), /*!< Framing error detected. */ - kUSART_ParityErrorInterruptEnable = (USART_INTENSET_PARITYERREN_MASK), /*!< Parity error detected. */ - kUSART_NoiseErrorInterruptEnable = (USART_INTENSET_RXNOISEEN_MASK), /*!< Noise error detected. */ - kUSART_AutoBaudErrorInterruptEnable = (USART_INTENSET_ABERREN_MASK), /*!< Auto baudrate error detected. */ - - kUSART_AllInterruptEnables = - kUSART_TxErrorInterruptEnable | kUSART_RxErrorInterruptEnable | kUSART_TxLevelInterruptEnable | - kUSART_RxLevelInterruptEnable | kUSART_TxIdleInterruptEnable | kUSART_CtsChangeInterruptEnable | - kUSART_RxBreakChangeInterruptEnable | kUSART_RxStartInterruptEnable | kUSART_FramingErrorInterruptEnable | - kUSART_ParityErrorInterruptEnable | kUSART_NoiseErrorInterruptEnable | kUSART_AutoBaudErrorInterruptEnable, -}; - -/*! - * @brief USART status flags. - * - * This provides constants for the USART status flags for use in the USART functions. - */ -enum _usart_flags -{ - kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */ - kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */ - kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */ - kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */ - kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */ - kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */ - kUSART_RxIdleFlag = (USART_STAT_RXIDLE_MASK << 16U), /*!< Receiver idle. */ - kUSART_TxIdleFlag = (USART_STAT_TXIDLE_MASK << 16U), /*!< Transmitter idle. */ - kUSART_CtsAssertFlag = (USART_STAT_CTS_MASK << 16U), /*!< CTS signal high. */ - kUSART_CtsChangeFlag = (USART_STAT_DELTACTS_MASK << 16U), /*!< CTS signal changed interrupt status. */ - kUSART_BreakDetectFlag = (USART_STAT_RXBRK_MASK), /*!< Break detected. Self cleared when rx pin goes high again. */ - kUSART_BreakDetectChangeFlag = (USART_STAT_DELTARXBRK_MASK), /*!< Break detect change interrupt flag. A change in - the state of receiver break detection. */ - kUSART_RxStartFlag = (USART_STAT_START_MASK), /*!< Rx start bit detected interrupt flag. */ - kUSART_FramingErrorFlag = (USART_STAT_FRAMERRINT_MASK), /*!< Framing error interrupt flag. */ - kUSART_ParityErrorFlag = (USART_STAT_PARITYERRINT_MASK), /*!< parity error interrupt flag. */ - kUSART_NoiseErrorFlag = (USART_STAT_RXNOISEINT_MASK), /*!< Noise error interrupt flag. */ - kUSART_AutobaudErrorFlag = (USART_STAT_ABERR_MASK), /*!< Auto baudrate error interrupt flag, caused by the baudrate - counter timeout before the end of start bit. */ - - kUSART_AllClearFlags = kUSART_TxError | kUSART_RxError | kUSART_CtsChangeFlag | kUSART_BreakDetectChangeFlag | - kUSART_RxStartFlag | kUSART_FramingErrorFlag | kUSART_ParityErrorFlag | - kUSART_NoiseErrorFlag | kUSART_AutobaudErrorFlag, -}; - -/*! @brief USART configuration structure. */ -typedef struct _usart_config -{ - uint32_t baudRate_Bps; /*!< USART baud rate */ - usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ - usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ - usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */ - bool loopback; /*!< Enable peripheral loopback */ - bool enableRx; /*!< Enable RX */ - bool enableTx; /*!< Enable TX */ - bool enableContinuousSCLK; /*!< USART continuous Clock generation enable in synchronous master mode. */ - bool enableMode32k; /*!< USART uses 32 kHz clock from the RTC oscillator as the clock source. */ - bool enableHardwareFlowControl; /*!< Enable hardware control RTS/CTS */ - usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ - usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */ - usart_clock_polarity_t clockPolarity; /*!< Selects the clock polarity and sampling edge in synchronous mode. */ -} usart_config_t; - -/*! @brief USART transfer structure. */ -typedef struct _usart_transfer -{ - /* - * Use separate TX and RX data pointer, because TX data is const data. - * The member data is kept for backward compatibility. - */ - union - { - uint8_t *data; /*!< The buffer of data to be transfer.*/ - uint8_t *rxData; /*!< The buffer to receive data. */ - const uint8_t *txData; /*!< The buffer of data to be sent. */ - }; - size_t dataSize; /*!< The byte count to be transfer. */ -} usart_transfer_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _usart_handle usart_handle_t; - -/*! @brief USART transfer callback function. */ -typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData); - -/*! @brief USART handle structure. */ -struct _usart_handle -{ - const uint8_t *volatile txData; /*!< Address of remaining data to send. */ - volatile size_t txDataSize; /*!< Size of the remaining data to send. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ - volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - - uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ - size_t rxRingBufferSize; /*!< Size of the ring buffer. */ - volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ - volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ - - usart_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< USART callback function parameter.*/ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ - - uint8_t txWatermark; /*!< txFIFO watermark */ - uint8_t rxWatermark; /*!< rxFIFO watermark */ -}; - -/*! @brief Typedef for usart interrupt handler. */ -typedef void (*flexcomm_usart_irq_handler_t)(USART_Type *base, usart_handle_t *handle); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! @brief Returns instance number for USART peripheral base address. */ -uint32_t USART_GetInstance(USART_Type *base); - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes a USART instance with user configuration structure and peripheral clock. - * - * This function configures the USART module with the user-defined settings. The user can configure the configuration - * structure and also get the default configuration by using the USART_GetDefaultConfig() function. - * Example below shows how to use this API to configure USART. - * @code - * usart_config_t usartConfig; - * usartConfig.baudRate_Bps = 115200U; - * usartConfig.parityMode = kUSART_ParityDisabled; - * usartConfig.stopBitCount = kUSART_OneStopBit; - * USART_Init(USART1, &usartConfig, 20000000U); - * @endcode - * - * @param base USART peripheral base address. - * @param config Pointer to user-defined configuration structure. - * @param srcClock_Hz USART clock source frequency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_InvalidArgument USART base address is not valid - * @retval kStatus_Success Status USART initialize succeed - */ -status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes a USART instance. - * - * This function waits for TX complete, disables TX and RX, and disables the USART clock. - * - * @param base USART peripheral base address. - */ -void USART_Deinit(USART_Type *base); - -/*! - * @brief Gets the default configuration structure. - * - * This function initializes the USART configuration structure to a default value. The default - * values are: - * usartConfig->baudRate_Bps = 115200U; - * usartConfig->parityMode = kUSART_ParityDisabled; - * usartConfig->stopBitCount = kUSART_OneStopBit; - * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; - * usartConfig->loopback = false; - * usartConfig->enableTx = false; - * usartConfig->enableRx = false; - * - * @param config Pointer to configuration structure. - */ -void USART_GetDefaultConfig(usart_config_t *config); - -/*! - * @brief Sets the USART instance baud rate. - * - * This function configures the USART module baud rate. This function is used to update - * the USART module baud rate after the USART module is initialized by the USART_Init. - * @code - * USART_SetBaudRate(USART1, 115200U, 20000000U); - * @endcode - * - * @param base USART peripheral base address. - * @param baudrate_Bps USART baudrate to be set. - * @param srcClock_Hz USART clock source frequency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_Success Set baudrate succeed. - * @retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source - * - * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator - * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting - * SYSCON_RTCOSCCTRL_EN bit to 1. - * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that - * 9600 can evenly divide, eg: 4800, 3200. - * - * @param base USART peripheral base address. - * @param baudRate_Bps USART baudrate to be set.. - * @param enableMode32k true is 32k mode, false is normal mode. - * @param srcClock_Hz USART clock source frequency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_Success Set baudrate succeed. - * @retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz); - -/*! - * @brief Enable 9-bit data mode for USART. - * - * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user. - * - * @param base USART peripheral base address. - * @param enable true to enable, false to disable. - */ -void USART_Enable9bitMode(USART_Type *base, bool enable); - -/*! - * @brief Set the USART slave address. - * - * This function configures the address for USART module that works as slave in 9-bit data mode. When the address - * detection is enabled, the frame it receices with MSB being 1 is considered as an address frame, otherwise it is - * considered as data frame. Once the address frame matches slave's own addresses, this slave is addressed. This - * address frame and its following data frames are stored in the receive buffer, otherwise the frames will be discarded. - * To un-address a slave, just send an address frame with unmatched address. - * - * @note Any USART instance joined in the multi-slave system can work as slave. The position of the address mark is the - * same as the parity bit when parity is enabled for 8 bit and 9 bit data formats. - * - * @param base USART peripheral base address. - * @param address USART slave address. - */ -static inline void USART_SetMatchAddress(USART_Type *base, uint8_t address) -{ - /* Configure match address. */ - base->ADDR = (uint32_t)address; -} - -/*! - * @brief Enable the USART match address feature. - * - * @param base USART peripheral base address. - * @param match true to enable match address, false to disable. - */ -static inline void USART_EnableMatchAddress(USART_Type *base, bool match) -{ - /* Configure match address enable bit. */ - if (match) - { - base->CFG |= (uint32_t)USART_CFG_AUTOADDR_MASK; - base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK; - } - else - { - base->CFG &= ~(uint32_t)USART_CFG_AUTOADDR_MASK; - base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK; - } -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Get USART status flags. - * - * This function get all USART status flags, the flags are returned as the logical - * OR value of the enumerators @ref _usart_flags. To check a specific status, - * compare the return value with enumerators in @ref _usart_flags. - * For example, to check whether the TX is empty: - * @code - * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1)) - * { - * ... - * } - * @endcode - * - * @param base USART peripheral base address. - * @return USART status flags which are ORed by the enumerators in the _usart_flags. - */ -static inline uint32_t USART_GetStatusFlags(USART_Type *base) -{ - return (base->FIFOSTAT & 0xFFUL) | (base->STAT & 0xFFUL) << 16U | (base->STAT & 0xFFFF00UL); -} - -/*! - * @brief Clear USART status flags. - * - * This function clear supported USART status flags - * Flags that can be cleared or set are: - * kUSART_TxError - * kUSART_RxError - * For example: - * @code - * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError) - * @endcode - * - * @param base USART peripheral base address. - * @param mask status flags to be cleared. - */ -static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask) -{ - mask &= (uint32_t)kUSART_AllClearFlags; - /* Clear the clearable status in STAT register. */ - base->STAT = (mask & 0xFFFF00UL) | ((mask & 0xFF0000UL) >> 16U); - /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */ - base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK); -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ -/*! - * @brief Enables USART interrupts according to the provided mask. - * - * This function enables the USART interrupts according to the provided mask. The mask - * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. - * For example, to enable TX empty interrupt and RX full interrupt: - * @code - * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); - * @endcode - * - * @param base USART peripheral base address. - * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable. - */ -static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) -{ - mask &= (uint32_t)kUSART_AllInterruptEnables; - base->INTENSET = (mask & 0x1FF00UL) | ((mask & 0xFF0000UL) >> 16U); - base->FIFOINTENSET = mask & 0xFUL; -} - -/*! - * @brief Disables USART interrupts according to a provided mask. - * - * This function disables the USART interrupts according to a provided mask. The mask - * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. - * This example shows how to disable the TX empty interrupt and RX full interrupt: - * @code - * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); - * @endcode - * - * @param base USART peripheral base address. - * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable. - */ -static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) -{ - mask &= (uint32_t)kUSART_AllInterruptEnables; - base->INTENCLR = (mask & 0x1FF00UL) | ((mask & 0xFF0000UL) >> 16U); - base->FIFOINTENCLR = mask & 0xFUL; -} - -/*! - * @brief Returns enabled USART interrupts. - * - * This function returns the enabled USART interrupts. - * - * @param base USART peripheral base address. - */ -static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base) -{ - return (base->INTENSET & 0x1FF00UL) | ((base->INTENSET & 0xFFUL) << 16UL) | (base->FIFOINTENSET & 0xFUL); -} - -/*! - * @brief Enable DMA for Tx - */ -static inline void USART_EnableTxDMA(USART_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK); - } -} - -/*! - * @brief Enable DMA for Rx - */ -static inline void USART_EnableRxDMA(USART_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK); - } -} - -/*! - * @brief Enable CTS. - * This function will determine whether CTS is used for flow control. - * - * @param base USART peripheral base address. - * @param enable Enable CTS or not, true for enable and false for disable. - */ -static inline void USART_EnableCTS(USART_Type *base, bool enable) -{ - if (enable) - { - base->CFG |= USART_CFG_CTSEN_MASK; - } - else - { - base->CFG &= ~USART_CFG_CTSEN_MASK; - } -} - -/*! - * @brief Continuous Clock generation. - * By default, SCLK is only output while data is being transmitted in synchronous mode. - * Enable this funciton, SCLK will run continuously in synchronous mode, allowing - * characters to be received on Un_RxD independently from transmission on Un_TXD). - * - * @param base USART peripheral base address. - * @param enable Enable Continuous Clock generation mode or not, true for enable and false for disable. - */ -static inline void USART_EnableContinuousSCLK(USART_Type *base, bool enable) -{ - if (enable) - { - base->CTL |= USART_CTL_CC_MASK; - } - else - { - base->CTL &= ~USART_CTL_CC_MASK; - } -} - -/*! - * @brief Enable Continuous Clock generation bit auto clear. - * While enable this cuntion, the Continuous Clock bit is automatically cleared when a complete - * character has been received. This bit is cleared at the same time. - * - * @param base USART peripheral base address. - * @param enable Enable auto clear or not, true for enable and false for disable. - */ -static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable) -{ - if (enable) - { - base->CTL |= USART_CTL_CLRCCONRX_MASK; - } - else - { - base->CTL &= ~USART_CTL_CLRCCONRX_MASK; - } -} - -/*! - * @brief Sets the rx FIFO watermark. - * - * @param base USART peripheral base address. - * @param water Rx FIFO watermark. - */ -static inline void USART_SetRxFifoWatermark(USART_Type *base, uint8_t water) -{ - assert(water <= (USART_FIFOTRIG_RXLVL_MASK >> USART_FIFOTRIG_RXLVL_SHIFT)); - base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_RXLVL_MASK) | USART_FIFOTRIG_RXLVL(water); -} - -/*! - * @brief Sets the tx FIFO watermark. - * - * @param base USART peripheral base address. - * @param water Tx FIFO watermark. - */ -static inline void USART_SetTxFifoWatermark(USART_Type *base, uint8_t water) -{ - assert(water <= (USART_FIFOTRIG_TXLVL_MASK >> USART_FIFOTRIG_TXLVL_SHIFT)); - base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_TXLVL_MASK) | USART_FIFOTRIG_TXLVL(water); -} -/* @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Writes to the FIFOWR register. - * - * This function writes data to the txFIFO directly. The upper layer must ensure - * that txFIFO has space for data to write before calling this function. - * - * @param base USART peripheral base address. - * @param data The byte to write. - */ -static inline void USART_WriteByte(USART_Type *base, uint8_t data) -{ - base->FIFOWR = data; -} - -/*! - * @brief Reads the FIFORD register directly. - * - * This function reads data from the rxFIFO directly. The upper layer must - * ensure that the rxFIFO is not empty before calling this function. - * - * @param base USART peripheral base address. - * @return The byte read from USART data register. - */ -static inline uint8_t USART_ReadByte(USART_Type *base) -{ - return (uint8_t)base->FIFORD; -} - -/*! - * @brief Gets the rx FIFO data count. - * - * @param base USART peripheral base address. - * @return rx FIFO data count. - */ -static inline uint8_t USART_GetRxFifoCount(USART_Type *base) -{ - return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_RXLVL_MASK) >> USART_FIFOSTAT_RXLVL_SHIFT); -} - -/*! - * @brief Gets the tx FIFO data count. - * - * @param base USART peripheral base address. - * @return tx FIFO data count. - */ -static inline uint8_t USART_GetTxFifoCount(USART_Type *base) -{ - return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); -} - -/*! - * @brief Transmit an address frame in 9-bit data mode. - * - * @param base USART peripheral base address. - * @param address USART slave address. - */ -void USART_SendAddress(USART_Type *base, uint8_t address); - -/*! - * @brief Writes to the TX register using a blocking method. - * - * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO - * to have room and writes data to the TX buffer. - * - * @param base USART peripheral base address. - * @param data Start address of the data to write. - * @param length Size of the data to write. - * @retval kStatus_USART_Timeout Transmission timed out and was aborted. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_Success Successfully wrote all data. - */ -status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length); - -/*! - * @brief Read RX data register using a blocking method. - * - * This function polls the RX register, waits for the RX register to be full or for RX FIFO to - * have data and read data from the TX register. - * - * @param base USART peripheral base address. - * @param data Start address of the buffer to store the received data. - * @param length Size of the buffer. - * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data. - * @retval kStatus_USART_ParityError Noise error happened while receiving data. - * @retval kStatus_USART_NoiseError Framing error happened while receiving data. - * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. - * @retval kStatus_USART_Timeout Transmission timed out and was aborted. - * @retval kStatus_Success Successfully received all data. - */ -status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the USART handle. - * - * This function initializes the USART handle which can be used for other USART - * transactional APIs. Usually, for a specified USART instance, - * call this API once to get the initialized handle. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param callback The callback function. - * @param userData The parameter of the callback function. - */ -status_t USART_TransferCreateHandle(USART_Type *base, - usart_handle_t *handle, - usart_transfer_callback_t callback, - void *userData); - -/*! - * @brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in the IRQ handler, the USART driver calls the callback - * function and passes the @ref kStatus_USART_TxIdle as status parameter. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART transfer structure. See #usart_transfer_t. - * @retval kStatus_Success Successfully start the data transmission. - * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific USART handle. - * - * When the RX ring buffer is used, data received are stored into the ring buffer even when the - * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * - * @note When using the RX ring buffer, one byte is reserved for internal use. In other - * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. - * @param ringBufferSize size of the ring buffer. - */ -void USART_TransferStartRingBuffer(USART_Type *base, - usart_handle_t *handle, - uint8_t *ringBuffer, - size_t ringBufferSize); - -/*! - * @brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the length of received data in RX ring buffer. - * - * @param handle USART handle pointer. - * @return Length of received data in RX ring buffer. - */ -size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle); - -/*! - * @brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out - * how many bytes are still not sent out. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been sent out to bus. - * - * This function gets the number of bytes that have been sent out to bus by interrupt method. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Send bytes count. - * @retval kStatus_NoTransferInProgress No send in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); - -/*! - * @brief Receives a buffer of data using an interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function, which - * returns without waiting for all data to be received. - * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and - * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in the ring buffer is not enough to read, the receive - * request is saved by the USART driver. When the new data arrives, the receive request - * is serviced first. When all data is received, the USART driver notifies the upper layer - * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle. - * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. - * The 5 bytes are copied to the xfer->data and this function returns with the - * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is - * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to the xfer->data. When all data is received, the upper layer is notified. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART transfer structure, see #usart_transfer_t. - * @param receivedBytes Bytes received from the ring buffer directly. - * @retval kStatus_Success Successfully queue the transfer into transmit queue. - * @retval kStatus_USART_RxBusy Previous receive request is not finished. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveNonBlocking(USART_Type *base, - usart_handle_t *handle, - usart_transfer_t *xfer, - size_t *receivedBytes); - -/*! - * @brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out - * how many bytes not received yet. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); - -/*! - * @brief USART IRQ handle function. - * - * This function handles the USART transmit and receive IRQ request. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_USART_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_usart_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_usart_dma.c deleted file mode 100644 index 60c2d5284c5..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_usart_dma.c +++ /dev/null @@ -1,392 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_usart.h" -#include "fsl_device_registers.h" -#include "fsl_dma.h" -#include "fsl_flexcomm.h" -#include "fsl_usart_dma.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_dma" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ -enum -{ - kUSART_TxIdle, /* TX idle. */ - kUSART_TxBusy, /* TX busy. */ - kUSART_RxIdle, /* RX idle. */ - kUSART_RxBusy /* RX busy. */ -}; - -/*! @brief Typedef for usart DMA interrupt handler. */ -typedef void (*flexcomm_usart_dma_irq_handler_t)(USART_Type *base, usart_dma_handle_t *handle); - -/*base, false); - - /* Enable tx idle interrupt */ - usartPrivateHandle->base->INTENSET = USART_INTENSET_TXIDLEEN_MASK; -} - -static void USART_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode) -{ - assert(handle != NULL); - assert(param != NULL); - - usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param; - - /* Disable UART RX DMA. */ - USART_EnableRxDMA(usartPrivateHandle->base, false); - - usartPrivateHandle->handle->rxState = (uint8_t)kUSART_RxIdle; - - if (usartPrivateHandle->handle->callback != NULL) - { - usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_RxIdle, - usartPrivateHandle->handle->userData); - } -} - -/*! - * brief Initializes the USART handle which is used in transactional functions. - * param base USART peripheral base address. - * param handle Pointer to usart_dma_handle_t structure. - * param callback Callback function. - * param userData User data. - * param txDmaHandle User-requested DMA handle for TX DMA transfer. - * param rxDmaHandle User-requested DMA handle for RX DMA transfer. - */ -status_t USART_TransferCreateHandleDMA(USART_Type *base, - usart_dma_handle_t *handle, - usart_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *txDmaHandle, - dma_handle_t *rxDmaHandle) -{ - uint32_t instance = 0; - - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } - /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - instance = USART_GetInstance(base); - - (void)memset(handle, 0, sizeof(*handle)); - /* assign 'base' and 'handle' */ - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - /* set tx/rx 'idle' state */ - handle->rxState = (uint8_t)kUSART_RxIdle; - handle->txState = (uint8_t)kUSART_TxIdle; - - handle->callback = callback; - handle->userData = userData; - - handle->rxDmaHandle = rxDmaHandle; - handle->txDmaHandle = txDmaHandle; - - /* Set USART_TransferDMAHandleIRQ as DMA IRQ handler */ - usart_dma_to_flexcomm_t handler; - handler.usart_dma_handler = USART_TransferDMAHandleIRQ; - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - /* Enable NVIC IRQ. */ - (void)EnableIRQ(s_usartIRQ[instance]); - - /* Configure TX. */ - if (txDmaHandle != NULL) - { - DMA_SetCallback(txDmaHandle, USART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]); - } - - /* Configure RX. */ - if (rxDmaHandle != NULL) - { - DMA_SetCallback(rxDmaHandle, USART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]); - } - - return kStatus_Success; -} - -/*! - * brief Sends data using DMA. - * - * This function sends data using DMA. This is a non-blocking function, which returns - * right away. When all data is sent, the send callback function is called. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART DMA transfer structure. See #usart_transfer_t. - * retval kStatus_Success if succeed, others failed. - * retval kStatus_USART_TxBusy Previous transfer on going. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) -{ - assert(handle != NULL); - assert(handle->txDmaHandle != NULL); - assert(xfer != NULL); - assert(xfer->data != NULL); - assert(xfer->dataSize != 0U); - - dma_transfer_config_t xferConfig; - status_t status; - uint32_t address = (uint32_t)&base->FIFOWR; - - /* If previous TX not finished. */ - if ((uint8_t)kUSART_TxBusy == handle->txState) - { - status = kStatus_USART_TxBusy; - } - else - { - handle->txState = (uint8_t)kUSART_TxBusy; - handle->txDataSizeAll = xfer->dataSize; - - /* Enable DMA request from txFIFO */ - USART_EnableTxDMA(base, true); - - /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, xfer->data, (uint32_t *)address, sizeof(uint8_t), xfer->dataSize, - kDMA_MemoryToPeripheral, NULL); - - /* Submit transfer. */ - (void)DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); - DMA_StartTransfer(handle->txDmaHandle); - - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Receives data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * param base USART peripheral base address. - * param handle Pointer to usart_dma_handle_t structure. - * param xfer USART DMA transfer structure. See #usart_transfer_t. - * retval kStatus_Success if succeed, others failed. - * retval kStatus_USART_RxBusy Previous transfer on going. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) -{ - assert(handle != NULL); - assert(handle->rxDmaHandle != NULL); - assert(xfer != NULL); - assert(xfer->data != NULL); - assert(xfer->dataSize != 0U); - - dma_transfer_config_t xferConfig; - status_t status; - uint32_t address = (uint32_t)&base->FIFORD; - - /* If previous RX not finished. */ - if ((uint8_t)kUSART_RxBusy == handle->rxState) - { - status = kStatus_USART_RxBusy; - } - else - { - handle->rxState = (uint8_t)kUSART_RxBusy; - handle->rxDataSizeAll = xfer->dataSize; - - /* Enable DMA request from rxFIFO */ - USART_EnableRxDMA(base, true); - - /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, xfer->data, sizeof(uint8_t), xfer->dataSize, - kDMA_PeripheralToMemory, NULL); - - /* Submit transfer. */ - (void)DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); - DMA_StartTransfer(handle->rxDmaHandle); - - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Aborts the sent data using DMA. - * - * This function aborts send data using DMA. - * - * param base USART peripheral base address - * param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle) -{ - assert(NULL != handle); - assert(NULL != handle->txDmaHandle); - - /* Stop transfer. */ - DMA_AbortTransfer(handle->txDmaHandle); - handle->txState = (uint8_t)kUSART_TxIdle; -} - -/*! - * brief Aborts the received data using DMA. - * - * This function aborts the received data using DMA. - * - * param base USART peripheral base address - * param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle) -{ - assert(NULL != handle); - assert(NULL != handle->rxDmaHandle); - - /* Stop transfer. */ - DMA_AbortTransfer(handle->rxDmaHandle); - handle->rxState = (uint8_t)kUSART_RxIdle; -} - -/*! - * brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Receive bytes count. - * retval kStatus_NoTransferInProgress No receive in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != handle->rxDmaHandle); - assert(NULL != count); - - if ((uint8_t)kUSART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); - - return kStatus_Success; -} - -/*! - * brief Get the number of bytes that have been sent. - * - * This function gets the number of bytes that have been sent. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Sent bytes count. - * retval kStatus_NoTransferInProgress No receive in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != handle->txDmaHandle); - assert(NULL != count); - - if ((uint8_t)kUSART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel); - - return kStatus_Success; -} - -void USART_TransferDMAHandleIRQ(USART_Type *base, usart_dma_handle_t *handle) -{ - /* Check arguments */ - assert((NULL != base) && (NULL != handle)); - - /* Tx idle interrupt happens means that all the tx data have been sent out to bus, set the tx state to idle */ - handle->txState = (uint8_t)kUSART_TxIdle; - - /* Disable tx idle interrupt */ - base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK; - - /* Invoke callback */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_usart_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_usart_dma.h deleted file mode 100644 index 2166803b5f2..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_usart_dma.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_USART_DMA_H_ -#define _FSL_USART_DMA_H_ - -#include "fsl_common.h" -#include "fsl_dma.h" -#include "fsl_usart.h" - -/*! - * @addtogroup usart_dma_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief USART dma driver version. */ -#define FSL_USART_DMA_DRIVER_VERSION (MAKE_VERSION(2, 6, 0)) -/*@}*/ - -/* Forward declaration of the handle typedef. */ -typedef struct _usart_dma_handle usart_dma_handle_t; - -/*! @brief UART transfer callback function. */ -typedef void (*usart_dma_transfer_callback_t)(USART_Type *base, - usart_dma_handle_t *handle, - status_t status, - void *userData); - -/*! - * @brief UART DMA handle - */ -struct _usart_dma_handle -{ - USART_Type *base; /*!< UART peripheral base address. */ - - usart_dma_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< UART callback function parameter.*/ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - - dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */ - dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name DMA transactional - * @{ - */ - -/*! - * @brief Initializes the USART handle which is used in transactional functions. - * @param base USART peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param callback Callback function. - * @param userData User data. - * @param txDmaHandle User-requested DMA handle for TX DMA transfer. - * @param rxDmaHandle User-requested DMA handle for RX DMA transfer. - */ -status_t USART_TransferCreateHandleDMA(USART_Type *base, - usart_dma_handle_t *handle, - usart_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *txDmaHandle, - dma_handle_t *rxDmaHandle); - -/*! - * @brief Sends data using DMA. - * - * This function sends data using DMA. This is a non-blocking function, which returns - * right away. When all data is sent, the send callback function is called. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART DMA transfer structure. See #usart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_USART_TxBusy Previous transfer on going. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Receives data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * @param base USART peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param xfer USART DMA transfer structure. See #usart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_USART_RxBusy Previous transfer on going. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Aborts the sent data using DMA. - * - * This function aborts send data using DMA. - * - * @param base USART peripheral base address - * @param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle); - -/*! - * @brief Aborts the received data using DMA. - * - * This function aborts the received data using DMA. - * - * @param base USART peripheral base address - * @param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); - -/*! - * @brief Get the number of bytes that have been sent. - * - * This function gets the number of bytes that have been sent. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Sent bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_USART_DMA_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_utick.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_utick.c deleted file mode 100644 index 0eea419cd34..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_utick.c +++ /dev/null @@ -1,230 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019, 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_utick.h" -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG) -#include "fsl_power.h" -#endif -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.utick" -#endif - -/* Typedef for interrupt handler. */ -typedef void (*utick_isr_t)(UTICK_Type *base, utick_callback_t cb); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base UTICK peripheral base address - * - * @return The UTICK instance - */ -static uint32_t UTICK_GetInstance(UTICK_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of UTICK handle. */ -static utick_callback_t s_utickHandle[FSL_FEATURE_SOC_UTICK_COUNT]; -/* Array of UTICK peripheral base address. */ -static UTICK_Type *const s_utickBases[] = UTICK_BASE_PTRS; -/* Array of UTICK IRQ number. */ -static const IRQn_Type s_utickIRQ[] = UTICK_IRQS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of UTICK clock name. */ -static const clock_ip_name_t s_utickClock[] = UTICK_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) -/*! @brief Pointers to UTICK resets for each instance. */ -static const reset_ip_name_t s_utickResets[] = UTICK_RSTS; -#endif - -/* UTICK ISR for transactional APIs. */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -static utick_isr_t s_utickIsr = (utick_isr_t)DefaultISR; -#else -static utick_isr_t s_utickIsr; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t UTICK_GetInstance(UTICK_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_utickBases); instance++) - { - if (s_utickBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_utickBases)); - - return instance; -} - -/*! - * brief Starts UTICK. - * - * This function starts a repeat/onetime countdown with an optional callback - * - * param base UTICK peripheral base address. - * param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) - * return none - */ -void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb) -{ - uint32_t instance; - - /* Get instance from peripheral base address. */ - instance = UTICK_GetInstance(base); - - /* Save the handle in global variables to support the double weak mechanism. */ - s_utickHandle[instance] = cb; -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) && \ - !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)) - EnableDeepSleepIRQ(s_utickIRQ[instance]); -#else - (void)EnableIRQ(s_utickIRQ[instance]); -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT && !FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ - base->CTRL = count | UTICK_CTRL_REPEAT(mode); -} - -/*! - * brief Initializes an UTICK by turning its bus clock on - * - */ -void UTICK_Init(UTICK_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable utick clock */ - CLOCK_EnableClock(s_utickClock[UTICK_GetInstance(base)]); -#endif - -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) - RESET_PeripheralReset(s_utickResets[UTICK_GetInstance(base)]); -#endif - -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG) - /* Power up Watchdog oscillator*/ - POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC); -#endif - - s_utickIsr = UTICK_HandleIRQ; -} - -/*! - * brief Deinitializes a UTICK instance. - * - * This function shuts down Utick bus clock - * - * param base UTICK peripheral base address. - */ -void UTICK_Deinit(UTICK_Type *base) -{ - /* Turn off utick */ - base->CTRL = 0; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable utick clock */ - CLOCK_DisableClock(s_utickClock[UTICK_GetInstance(base)]); -#endif -} - -/*! - * brief Get Status Flags. - * - * This returns the status flag - * - * param base UTICK peripheral base address. - * return status register value - */ -uint32_t UTICK_GetStatusFlags(UTICK_Type *base) -{ - return (base->STAT); -} - -/*! - * brief Clear Status Interrupt Flags. - * - * This clears intr status flag - * - * param base UTICK peripheral base address. - * return none - */ -void UTICK_ClearStatusFlags(UTICK_Type *base) -{ - base->STAT = UTICK_STAT_INTR_MASK; -} - -/*! - * brief UTICK Interrupt Service Handler. - * - * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request - * in UTICK_SetTick()). - * if no user callback is scheduled, the interrupt will simply be cleared. - * - * param base UTICK peripheral base address. - * param cb callback scheduled for this instance of UTICK - * return none - */ -void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb) -{ - UTICK_ClearStatusFlags(base); - if (cb != NULL) - { - cb(); - } -} - -#if defined(UTICK0) -void UTICK0_DriverIRQHandler(void); -void UTICK0_DriverIRQHandler(void) -{ - s_utickIsr(UTICK0, s_utickHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif -#if defined(UTICK1) -void UTICK1_DriverIRQHandler(void); -void UTICK1_DriverIRQHandler(void) -{ - s_utickIsr(UTICK1, s_utickHandle[1]); - SDK_ISR_EXIT_BARRIER; -} -#endif -#if defined(UTICK2) -void UTICK2_DriverIRQHandler(void); -void UTICK2_DriverIRQHandler(void) -{ - s_utickIsr(UTICK2, s_utickHandle[2]); - SDK_ISR_EXIT_BARRIER; -} -#endif -#if defined(UTICK) -void UTICK_DriverIRQHandler(void); -void UTICK_DriverIRQHandler(void) -{ - s_utickIsr(UTICK, s_utickHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_utick.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_utick.h deleted file mode 100644 index 48c7d6b86de..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_utick.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019, 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_UTICK_H_ -#define _FSL_UTICK_H_ - -#include "fsl_common.h" -/*! - * @addtogroup utick - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief UTICK driver version 2.0.5. */ -#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) -/*@}*/ - -/*! @brief UTICK timer operational mode. */ -typedef enum _utick_mode -{ - kUTICK_Onetime = 0x0U, /*!< Trigger once*/ - kUTICK_Repeat = 0x1U, /*!< Trigger repeatedly */ -} utick_mode_t; - -/*! @brief UTICK callback function. */ -typedef void (*utick_callback_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes an UTICK by turning its bus clock on - * - */ -void UTICK_Init(UTICK_Type *base); - -/*! - * @brief Deinitializes a UTICK instance. - * - * This function shuts down Utick bus clock - * - * @param base UTICK peripheral base address. - */ -void UTICK_Deinit(UTICK_Type *base); -/*! - * @brief Get Status Flags. - * - * This returns the status flag - * - * @param base UTICK peripheral base address. - * @return status register value - */ -uint32_t UTICK_GetStatusFlags(UTICK_Type *base); -/*! - * @brief Clear Status Interrupt Flags. - * - * This clears intr status flag - * - * @param base UTICK peripheral base address. - * @return none - */ -void UTICK_ClearStatusFlags(UTICK_Type *base); - -/*! - * @brief Starts UTICK. - * - * This function starts a repeat/onetime countdown with an optional callback - * - * @param base UTICK peripheral base address. - * @param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * @param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * @param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) - * @return none - */ -void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb); -/*! - * @brief UTICK Interrupt Service Handler. - * - * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request - * in UTICK_SetTick()). - * if no user callback is scheduled, the interrupt will simply be cleared. - * - * @param base UTICK peripheral base address. - * @param cb callback scheduled for this instance of UTICK - * @return none - */ -void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_UTICK_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_wwdt.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_wwdt.c deleted file mode 100644 index 6680148acf7..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_wwdt.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_wwdt.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.wwdt" -#endif - -#define FREQUENCY_3MHZ (3000000U) -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Gets the instance from the base address - * - * @param base WWDT peripheral base address - * - * @return The WWDT instance - */ -static uint32_t WWDT_GetInstance(WWDT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to WWDT bases for each instance. */ -static WWDT_Type *const s_wwdtBases[] = WWDT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to WWDT clocks for each instance. */ -static const clock_ip_name_t s_wwdtClocks[] = WWDT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) -/*! @brief Pointers to WWDT resets for each instance. */ -static const reset_ip_name_t s_wwdtResets[] = WWDT_RSTS; -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t WWDT_GetInstance(WWDT_Type *base) -{ - uint32_t instance; - uint32_t wwdtArrayCount = (sizeof(s_wwdtBases) / sizeof(s_wwdtBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < wwdtArrayCount; instance++) - { - if (s_wwdtBases[instance] == base) - { - break; - } - } - - assert(instance < wwdtArrayCount); - - return instance; -} - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Initializes WWDT configure structure. - * - * This function initializes the WWDT configure structure to default value. The default - * value are: - * code - * config->enableWwdt = true; - * config->enableWatchdogReset = false; - * config->enableWatchdogProtect = false; - * config->enableLockOscillator = false; - * config->windowValue = 0xFFFFFFU; - * config->timeoutValue = 0xFFFFFFU; - * config->warningValue = 0; - * endcode - * - * param config Pointer to WWDT config structure. - * see wwdt_config_t - */ -void WWDT_GetDefaultConfig(wwdt_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* Enable the watch dog */ - config->enableWwdt = true; - /* Disable the watchdog timeout reset */ - config->enableWatchdogReset = false; - /* Disable the watchdog protection for updating the timeout value */ - config->enableWatchdogProtect = false; -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) - /* Do not lock the watchdog oscillator */ - config->enableLockOscillator = false; -#endif - /* Windowing is not in effect */ - config->windowValue = 0xFFFFFFU; - /* Set the timeout value to the max */ - config->timeoutValue = 0xFFFFFFU; - /* No warning is provided */ - config->warningValue = 0; - /* Set clock frequency. */ - config->clockFreq_Hz = 0U; -} - -/*! - * brief Initializes the WWDT. - * - * This function initializes the WWDT. When called, the WWDT runs according to the configuration. - * - * Example: - * code - * wwdt_config_t config; - * WWDT_GetDefaultConfig(&config); - * config.timeoutValue = 0x7ffU; - * WWDT_Init(wwdt_base,&config); - * endcode - * - * param base WWDT peripheral base address - * param config The configuration of WWDT - */ -void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config) -{ - assert(NULL != config); - - uint32_t value = 0U; - uint32_t DelayUs = 0U; - uint32_t primaskValue = 0U; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the WWDT clock */ - CLOCK_EnableClock(s_wwdtClocks[WWDT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) - /* Reset the module. */ - RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]); -#endif - -#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) - /* PMC RESETCAUSE: set bit to clear it by write 1. */ - PMC->RESETCAUSE = PMC_RESETCAUSE_WDTRESET_MASK; - /* Enable the watchdog reset event to affect the system in the Power Management Controller */ - PMC->CTRL |= PMC_CTRL_WDTRESETENABLE_MASK; -#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ - -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) - value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) | - WWDT_MOD_LOCK(config->enableLockOscillator); -#else - value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset); -#endif - /* Clear legacy flag in the MOD register by software writing a "1" to this bit field.. */ - if (0U != (base->MOD & WWDT_MOD_WDINT_MASK)) - { - value |= WWDT_MOD_WDINT_MASK; - } - /* Set configuration */ - primaskValue = DisableGlobalIRQ(); - base->TC = WWDT_TC_COUNT(config->timeoutValue); - base->MOD = value; - base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue); - base->WARNINT = WWDT_WARNINT_WARNINT(config->warningValue); - /* Refreshes the WWDT timer. */ - base->FEED = WWDT_FIRST_WORD_OF_REFRESH; - base->FEED = WWDT_SECOND_WORD_OF_REFRESH; - EnableGlobalIRQ(primaskValue); - /* Read counter value to wait wwdt timer start*/ - if (config->enableWwdt) - { - while (base->TV == 0xFFUL) - { - } - } - - /* This WDPROTECT bit can be set once by software and is only cleared by a reset */ - if (config->enableWatchdogProtect && (0U == (base->MOD & WWDT_MOD_WDPROTECT_MASK))) - { - /* The config->clockFreq_Hz must be set in order to config the delay time. */ - assert(0U != config->clockFreq_Hz); - - /* Set the WDPROTECT bit after the Feed Sequence (0xAA, 0x55) with 3 WDCLK delay */ - DelayUs = FREQUENCY_3MHZ / config->clockFreq_Hz + 1U; - SDK_DelayAtLeastUs(DelayUs, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - - base->MOD |= WWDT_MOD_WDPROTECT(1U); - } -} - -/*! - * brief Shuts down the WWDT. - * - * This function shuts down the WWDT. - * - * param base WWDT peripheral base address - */ -void WWDT_Deinit(WWDT_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the WWDT clock */ - CLOCK_DisableClock(s_wwdtClocks[WWDT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Refreshes the WWDT timer. - * - * This function feeds the WWDT. - * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. - * - * param base WWDT peripheral base address - */ -void WWDT_Refresh(WWDT_Type *base) -{ - uint32_t primaskValue = 0U; - - /* Disable the global interrupt to protect refresh sequence */ - primaskValue = DisableGlobalIRQ(); - base->FEED = WWDT_FIRST_WORD_OF_REFRESH; - base->FEED = WWDT_SECOND_WORD_OF_REFRESH; - EnableGlobalIRQ(primaskValue); -} - -/*! - * brief Clear WWDT flag. - * - * This function clears WWDT status flag. - * - * Example for clearing warning flag: - * code - * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); - * endcode - * param base WWDT peripheral base address - * param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask) -{ - /* Clear the WDINT bit so that we don't accidentally clear it */ - uint32_t reg = (base->MOD & (~WWDT_MOD_WDINT_MASK)); - - /* Clear timeout by writing a zero */ - if (0U != (mask & (uint32_t)kWWDT_TimeoutFlag)) - { - reg &= ~WWDT_MOD_WDTOF_MASK; -#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) - /* PMC RESETCAUSE: set bit to clear it */ - PMC->RESETCAUSE = PMC_RESETCAUSE_WDTRESET_MASK; -#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ - } - - /* Clear warning interrupt flag by writing a one */ - if (0U != (mask & (uint32_t)kWWDT_WarningFlag)) - { - reg |= WWDT_MOD_WDINT_MASK; - } - - base->MOD = reg; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_wwdt.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_wwdt.h deleted file mode 100644 index 25462534966..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_wwdt.h +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_WWDT_H_ -#define _FSL_WWDT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup wwdt - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Defines WWDT driver version. */ -#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 1, 9)) -/*@}*/ - -/*! @name Refresh sequence */ -/*@{*/ -#define WWDT_FIRST_WORD_OF_REFRESH (0xAAU) /*!< First word of refresh sequence */ -#define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */ -/*@}*/ - -/*! @brief Describes WWDT configuration structure. */ -typedef struct _wwdt_config -{ - bool enableWwdt; /*!< Enables or disables WWDT */ - bool enableWatchdogReset; /*!< true: Watchdog timeout will cause a chip reset - false: Watchdog timeout will not cause a chip reset */ - bool enableWatchdogProtect; /*!< true: Enable watchdog protect i.e timeout value can only be - changed after counter is below warning & window values - false: Disable watchdog protect; timeout value can be changed - at any time */ -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) - bool enableLockOscillator; /*!< true: Disabling or powering down the watchdog oscillator is prevented - Once set, this bit can only be cleared by a reset - false: Do not lock oscillator */ -#endif - uint32_t windowValue; /*!< Window value, set this to 0xFFFFFF if windowing is not in effect */ - uint32_t timeoutValue; /*!< Timeout value */ - uint32_t warningValue; /*!< Watchdog time counter value that will generate a - warning interrupt. Set this to 0 for no warning */ - uint32_t clockFreq_Hz; /*!< Watchdog clock source frequency. */ -} wwdt_config_t; - -/*! - * @brief WWDT status flags. - * - * This structure contains the WWDT status flags for use in the WWDT functions. - */ -enum _wwdt_status_flags_t -{ - kWWDT_TimeoutFlag = WWDT_MOD_WDTOF_MASK, /*!< Time-out flag, set when the timer times out */ - kWWDT_WarningFlag = WWDT_MOD_WDINT_MASK /*!< Warning interrupt flag, set when timer is below the value WDWARNINT */ -}; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name WWDT Initialization and De-initialization - * @{ - */ - -/*! - * @brief Initializes WWDT configure structure. - * - * This function initializes the WWDT configure structure to default value. The default - * value are: - * @code - * config->enableWwdt = true; - * config->enableWatchdogReset = false; - * config->enableWatchdogProtect = false; - * config->enableLockOscillator = false; - * config->windowValue = 0xFFFFFFU; - * config->timeoutValue = 0xFFFFFFU; - * config->warningValue = 0; - * @endcode - * - * @param config Pointer to WWDT config structure. - * @see wwdt_config_t - */ -void WWDT_GetDefaultConfig(wwdt_config_t *config); - -/*! - * @brief Initializes the WWDT. - * - * This function initializes the WWDT. When called, the WWDT runs according to the configuration. - * - * Example: - * @code - * wwdt_config_t config; - * WWDT_GetDefaultConfig(&config); - * config.timeoutValue = 0x7ffU; - * WWDT_Init(wwdt_base,&config); - * @endcode - * - * @param base WWDT peripheral base address - * @param config The configuration of WWDT - */ -void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config); - -/*! - * @brief Shuts down the WWDT. - * - * This function shuts down the WWDT. - * - * @param base WWDT peripheral base address - */ -void WWDT_Deinit(WWDT_Type *base); - -/* @} */ - -/*! - * @name WWDT Functional Operation - * @{ - */ - -/*! - * @brief Enables the WWDT module. - * - * This function write value into WWDT_MOD register to enable the WWDT, it is a write-once bit; - * once this bit is set to one and a watchdog feed is performed, the watchdog timer will run - * permanently. - * - * @param base WWDT peripheral base address - */ -static inline void WWDT_Enable(WWDT_Type *base) -{ - base->MOD |= WWDT_MOD_WDEN_MASK; -} - -/*! - * @brief Disables the WWDT module. - * @deprecated Do not use this function. It will be deleted in next release version, for - * once the bit field of WDEN written with a 1, it can not be re-written with a 0. - * - * This function write value into WWDT_MOD register to disable the WWDT. - * - * @param base WWDT peripheral base address - */ -static inline void WWDT_Disable(WWDT_Type *base) -{ - base->MOD &= ~WWDT_MOD_WDEN_MASK; -} - -/*! - * @brief Gets all WWDT status flags. - * - * This function gets all status flags. - * - * Example for getting Timeout Flag: - * @code - * uint32_t status; - * status = WWDT_GetStatusFlags(wwdt_base) & kWWDT_TimeoutFlag; - * @endcode - * @param base WWDT peripheral base address - * @return The status flags. This is the logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -static inline uint32_t WWDT_GetStatusFlags(WWDT_Type *base) -{ -#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) - uint32_t status; - /* WDTOF is not set in case of WD reset - get info from PMC instead */ - status = (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); - if (PMC->RESETCAUSE & PMC_RESETCAUSE_WDTRESET_MASK) - { - status |= kWWDT_TimeoutFlag; - } - return status; -#else - return (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); -#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ -} - -/*! - * @brief Clear WWDT flag. - * - * This function clears WWDT status flag. - * - * Example for clearing warning flag: - * @code - * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); - * @endcode - * @param base WWDT peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask); - -/*! - * @brief Set the WWDT warning value. - * - * The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog - * interrupt. When the watchdog timer counter is no longer greater than the value defined by - * WARNINT, an interrupt will be generated after the subsequent WDCLK. - * - * @param base WWDT peripheral base address - * @param warningValue WWDT warning value. - */ -static inline void WWDT_SetWarningValue(WWDT_Type *base, uint32_t warningValue) -{ - base->WARNINT = WWDT_WARNINT_WARNINT(warningValue); -} - -/*! - * @brief Set the WWDT timeout value. - * - * This function sets the timeout value. Every time a feed sequence occurs the value in the TC - * register is loaded into the Watchdog timer. Writing a value below 0xFF will cause 0xFF to be - * loaded into the TC register. Thus the minimum time-out interval is TWDCLK*256*4. - * If enableWatchdogProtect flag is true in wwdt_config_t config structure, any attempt to change - * the timeout value before the watchdog counter is below the warning and window values - * will cause a watchdog reset and set the WDTOF flag. - * - * @param base WWDT peripheral base address - * @param timeoutCount WWDT timeout value, count of WWDT clock tick. - */ -static inline void WWDT_SetTimeoutValue(WWDT_Type *base, uint32_t timeoutCount) -{ - base->TC = WWDT_TC_COUNT(timeoutCount); -} - -/*! - * @brief Sets the WWDT window value. - * - * The WINDOW register determines the highest TV value allowed when a watchdog feed is performed. - * If a feed sequence occurs when timer value is greater than the value in WINDOW, a watchdog - * event will occur. To disable windowing, set windowValue to 0xFFFFFF (maximum possible timer - * value) so windowing is not in effect. - * - * @param base WWDT peripheral base address - * @param windowValue WWDT window value. - */ -static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue) -{ - base->WINDOW = WWDT_WINDOW_WINDOW(windowValue); -} - -/*! - * @brief Refreshes the WWDT timer. - * - * This function feeds the WWDT. - * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. - * - * @param base WWDT peripheral base address - */ -void WWDT_Refresh(WWDT_Type *base); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_WWDT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/fsl_device_registers.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/fsl_device_registers.h deleted file mode 100644 index 75cc6fb8b66..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/fsl_device_registers.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __FSL_DEVICE_REGISTERS_H__ -#define __FSL_DEVICE_REGISTERS_H__ - -/* - * Include the cpu specific register header files. - * - * The CPU macro should be declared in the project or makefile. - */ -#if (defined(CPU_LPC55S06JBD64) || defined(CPU_LPC55S06JHI48)) - -#define LPC55S06_SERIES - -/* CMSIS-style register definitions */ -#include "LPC55S06.h" -/* CPU specific feature definitions */ -#include "LPC55S06_features.h" - -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_DEVICE_REGISTERS_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/gcc/LPC55S06_flash.ld b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/gcc/LPC55S06_flash.ld deleted file mode 100644 index 6e686170df4..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/gcc/LPC55S06_flash.ld +++ /dev/null @@ -1,203 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S06JBD64 -** LPC55S06JHI48 -** -** Compiler: GNU C Compiler -** Reference manual: LPC55S0x/LPC550x User manual Rev.0.3 14 August 2020 -** Version: rev. 1.0, 2020-04-09 -** Build: b220622 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000200 - m_text (RX) : ORIGIN = 0x00000200, LENGTH = 0x0003CE00 - m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00010000 - m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00004000 - m_sram3 (RW) : ORIGIN = 0x20010000, LENGTH = 0x00004000 -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into internal flash */ - .interrupts : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.ramfunc*) /* for functions in ram */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/gcc/LPC55S06_ram.ld b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/gcc/LPC55S06_ram.ld deleted file mode 100644 index f2ad392c279..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/gcc/LPC55S06_ram.ld +++ /dev/null @@ -1,202 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S06JBD64 -** LPC55S06JHI48 -** -** Compiler: GNU C Compiler -** Reference manual: LPC55S0x/LPC550x User manual Rev.0.3 14 August 2020 -** Version: rev. 1.0, 2020-04-09 -** Build: b220622 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x20000000, LENGTH = 0x00000200 - m_text (RX) : ORIGIN = 0x20000200, LENGTH = 0x0000FE00 - m_data (RW) : ORIGIN = 0x04000000, LENGTH = 0x00004000 - m_sram3 (RW) : ORIGIN = 0x20010000, LENGTH = 0x00004000 -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into internal flash */ - .interrupts : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.ramfunc*) /* for functions in ram */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/gcc/startup_LPC55S06.S b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/gcc/startup_LPC55S06.S deleted file mode 100644 index 86789fe83ed..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/gcc/startup_LPC55S06.S +++ /dev/null @@ -1,895 +0,0 @@ -/* --------------------------------------------------------------------------*/ -/* @file: startup_LPC55S06.s */ -/* @purpose: CMSIS Cortex-M33 Core Device Startup File */ -/* LPC55S06 */ -/* @version: 1.0 */ -/* @date: 2020-4-9 */ -/* --------------------------------------------------------------------------*/ -/* */ -/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2021 NXP */ -/* All rights reserved. */ -/* */ -/* SPDX-License-Identifier: BSD-3-Clause */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - - - .syntax unified - .arch armv8-m.main - - .section .isr_vector, "a" - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long MemManage_Handler /* MPU Fault Handler*/ - .long BusFault_Handler /* Bus Fault Handler*/ - .long UsageFault_Handler /* Usage Fault Handler*/ - .long SecureFault_Handler /* Secure Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long DebugMon_Handler /* Debug Monitor Handler*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts */ - .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ - .long DMA0_IRQHandler /* DMA0 controller */ - .long GINT0_IRQHandler /* GPIO group 0 */ - .long GINT1_IRQHandler /* GPIO group 1 */ - .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - .long UTICK0_IRQHandler /* Micro-tick Timer */ - .long MRT0_IRQHandler /* Multi-rate timer */ - .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ - .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ - .long SCT0_IRQHandler /* SCTimer/PWM */ - .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ - .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long ADC0_IRQHandler /* ADC0 */ - .long Reserved39_IRQHandler /* Reserved interrupt */ - .long ACMP_IRQHandler /* ACMP interrupts */ - .long Reserved41_IRQHandler /* Reserved interrupt */ - .long Reserved42_IRQHandler /* Reserved interrupt */ - .long Reserved43_IRQHandler /* Reserved interrupt */ - .long Reserved44_IRQHandler /* Reserved interrupt */ - .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ - .long Reserved46_IRQHandler /* Reserved interrupt */ - .long Reserved47_IRQHandler /* Reserved interrupt */ - .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ - .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ - .long OS_EVENT_IRQHandler /* OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ - .long Reserved55_IRQHandler /* Reserved interrupt */ - .long Reserved56_IRQHandler /* Reserved interrupt */ - .long Reserved57_IRQHandler /* Reserved interrupt */ - .long Reserved58_IRQHandler /* Reserved interrupt */ - .long CAN0_IRQ0_IRQHandler /* CAN0 interrupt0 */ - .long CAN0_IRQ1_IRQHandler /* CAN0 interrupt1 */ - .long Reserved61_IRQHandler /* Reserved interrupt */ - .long Reserved62_IRQHandler /* Reserved interrupt */ - .long Reserved63_IRQHandler /* Reserved interrupt */ - .long Reserved64_IRQHandler /* Reserved interrupt */ - .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ - .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ - .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ - .long PLU_IRQHandler /* PLU interrupt */ - .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ - .long HASHCRYPT_IRQHandler /* SHA interrupt */ - .long CASER_IRQHandler /* CASPER interrupt */ - .long PUF_IRQHandler /* PUF interrupt */ - .long Reserved73_IRQHandler /* Reserved interrupt */ - .long DMA1_IRQHandler /* DMA1 interrupt */ - .long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ - .long CDOG_IRQHandler /* CDOG interrupt */ - - .size __Vectors, . - __Vectors - - .text - .thumb - -/* Reset Handler */ - .thumb_func - .align 2 - .globl Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - cpsid i /* Mask interrupts */ - .equ VTOR, 0xE000ED08 - ldr r0, =VTOR - ldr r1, =__Vectors - str r1, [r0] - ldr r2, [r1] - msr msp, r2 - ldr R0, =__StackLimit - msr msplim, R0 -#ifndef __NO_SYSTEM_INIT - ldr r0,=SystemInit - blx r0 -#endif -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -#if 1 -/* Here are two copies of loop implemenations. First one favors code size - * and the second one favors performance. Default uses the first one. - * Change to "#if 0" to use the second one */ -.LC0: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .LC0 -#else - subs r3, r2 - ble .LC1 -.LC0: - subs r3, #4 - ldr r0, [r1, r3] - str r0, [r2, r3] - bgt .LC0 -.LC1: -#endif - -#ifdef __STARTUP_CLEAR_BSS -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * Loop to zero out BSS section, which uses following symbols - * in linker script: - * __bss_start__: start of BSS section. Must align to 4 - * __bss_end__: end of BSS section. Must align to 4 - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.LC2: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC2 -#endif /* __STARTUP_CLEAR_BSS */ - -/* Add stack / heap initializaiton */ - movs r0, 0 - ldr r1, =__HeapBase - ldr r2, =__HeapLimit -.LC3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC3 - - ldr r1, =__StackLimit - ldr r2, =__StackTop -.LC4: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC4 -/*End of stack / heap initializaiton */ - cpsie i /* Unmask interrupts */ - -#ifndef __START -#define __START _start -#endif -#ifndef __ATOLLIC__ - ldr r0,=__START - blx r0 -#else - ldr r0,=__libc_init_array - blx r0 - ldr r0,=main - bx r0 -#endif - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - - .align 1 - .thumb_func - .weak WDT_BOD_IRQHandler - .type WDT_BOD_IRQHandler, %function -WDT_BOD_IRQHandler: - ldr r0,=WDT_BOD_DriverIRQHandler - bx r0 - .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler - - .align 1 - .thumb_func - .weak DMA0_IRQHandler - .type DMA0_IRQHandler, %function -DMA0_IRQHandler: - ldr r0,=DMA0_DriverIRQHandler - bx r0 - .size DMA0_IRQHandler, . - DMA0_IRQHandler - - .align 1 - .thumb_func - .weak GINT0_IRQHandler - .type GINT0_IRQHandler, %function -GINT0_IRQHandler: - ldr r0,=GINT0_DriverIRQHandler - bx r0 - .size GINT0_IRQHandler, . - GINT0_IRQHandler - - .align 1 - .thumb_func - .weak GINT1_IRQHandler - .type GINT1_IRQHandler, %function -GINT1_IRQHandler: - ldr r0,=GINT1_DriverIRQHandler - bx r0 - .size GINT1_IRQHandler, . - GINT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT0_IRQHandler - .type PIN_INT0_IRQHandler, %function -PIN_INT0_IRQHandler: - ldr r0,=PIN_INT0_DriverIRQHandler - bx r0 - .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT1_IRQHandler - .type PIN_INT1_IRQHandler, %function -PIN_INT1_IRQHandler: - ldr r0,=PIN_INT1_DriverIRQHandler - bx r0 - .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT2_IRQHandler - .type PIN_INT2_IRQHandler, %function -PIN_INT2_IRQHandler: - ldr r0,=PIN_INT2_DriverIRQHandler - bx r0 - .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT3_IRQHandler - .type PIN_INT3_IRQHandler, %function -PIN_INT3_IRQHandler: - ldr r0,=PIN_INT3_DriverIRQHandler - bx r0 - .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler - - .align 1 - .thumb_func - .weak UTICK0_IRQHandler - .type UTICK0_IRQHandler, %function -UTICK0_IRQHandler: - ldr r0,=UTICK0_DriverIRQHandler - bx r0 - .size UTICK0_IRQHandler, . - UTICK0_IRQHandler - - .align 1 - .thumb_func - .weak MRT0_IRQHandler - .type MRT0_IRQHandler, %function -MRT0_IRQHandler: - ldr r0,=MRT0_DriverIRQHandler - bx r0 - .size MRT0_IRQHandler, . - MRT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER0_IRQHandler - .type CTIMER0_IRQHandler, %function -CTIMER0_IRQHandler: - ldr r0,=CTIMER0_DriverIRQHandler - bx r0 - .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER1_IRQHandler - .type CTIMER1_IRQHandler, %function -CTIMER1_IRQHandler: - ldr r0,=CTIMER1_DriverIRQHandler - bx r0 - .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler - - .align 1 - .thumb_func - .weak SCT0_IRQHandler - .type SCT0_IRQHandler, %function -SCT0_IRQHandler: - ldr r0,=SCT0_DriverIRQHandler - bx r0 - .size SCT0_IRQHandler, . - SCT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER3_IRQHandler - .type CTIMER3_IRQHandler, %function -CTIMER3_IRQHandler: - ldr r0,=CTIMER3_DriverIRQHandler - bx r0 - .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM0_IRQHandler - .type FLEXCOMM0_IRQHandler, %function -FLEXCOMM0_IRQHandler: - ldr r0,=FLEXCOMM0_DriverIRQHandler - bx r0 - .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM1_IRQHandler - .type FLEXCOMM1_IRQHandler, %function -FLEXCOMM1_IRQHandler: - ldr r0,=FLEXCOMM1_DriverIRQHandler - bx r0 - .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM2_IRQHandler - .type FLEXCOMM2_IRQHandler, %function -FLEXCOMM2_IRQHandler: - ldr r0,=FLEXCOMM2_DriverIRQHandler - bx r0 - .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM3_IRQHandler - .type FLEXCOMM3_IRQHandler, %function -FLEXCOMM3_IRQHandler: - ldr r0,=FLEXCOMM3_DriverIRQHandler - bx r0 - .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM4_IRQHandler - .type FLEXCOMM4_IRQHandler, %function -FLEXCOMM4_IRQHandler: - ldr r0,=FLEXCOMM4_DriverIRQHandler - bx r0 - .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM5_IRQHandler - .type FLEXCOMM5_IRQHandler, %function -FLEXCOMM5_IRQHandler: - ldr r0,=FLEXCOMM5_DriverIRQHandler - bx r0 - .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM6_IRQHandler - .type FLEXCOMM6_IRQHandler, %function -FLEXCOMM6_IRQHandler: - ldr r0,=FLEXCOMM6_DriverIRQHandler - bx r0 - .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM7_IRQHandler - .type FLEXCOMM7_IRQHandler, %function -FLEXCOMM7_IRQHandler: - ldr r0,=FLEXCOMM7_DriverIRQHandler - bx r0 - .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_IRQHandler - .type ADC0_IRQHandler, %function -ADC0_IRQHandler: - ldr r0,=ADC0_DriverIRQHandler - bx r0 - .size ADC0_IRQHandler, . - ADC0_IRQHandler - - .align 1 - .thumb_func - .weak Reserved39_IRQHandler - .type Reserved39_IRQHandler, %function -Reserved39_IRQHandler: - ldr r0,=Reserved39_DriverIRQHandler - bx r0 - .size Reserved39_IRQHandler, . - Reserved39_IRQHandler - - .align 1 - .thumb_func - .weak ACMP_IRQHandler - .type ACMP_IRQHandler, %function -ACMP_IRQHandler: - ldr r0,=ACMP_DriverIRQHandler - bx r0 - .size ACMP_IRQHandler, . - ACMP_IRQHandler - - .align 1 - .thumb_func - .weak Reserved41_IRQHandler - .type Reserved41_IRQHandler, %function -Reserved41_IRQHandler: - ldr r0,=Reserved41_DriverIRQHandler - bx r0 - .size Reserved41_IRQHandler, . - Reserved41_IRQHandler - - .align 1 - .thumb_func - .weak Reserved42_IRQHandler - .type Reserved42_IRQHandler, %function -Reserved42_IRQHandler: - ldr r0,=Reserved42_DriverIRQHandler - bx r0 - .size Reserved42_IRQHandler, . - Reserved42_IRQHandler - - .align 1 - .thumb_func - .weak Reserved43_IRQHandler - .type Reserved43_IRQHandler, %function -Reserved43_IRQHandler: - ldr r0,=Reserved43_DriverIRQHandler - bx r0 - .size Reserved43_IRQHandler, . - Reserved43_IRQHandler - - .align 1 - .thumb_func - .weak Reserved44_IRQHandler - .type Reserved44_IRQHandler, %function -Reserved44_IRQHandler: - ldr r0,=Reserved44_DriverIRQHandler - bx r0 - .size Reserved44_IRQHandler, . - Reserved44_IRQHandler - - .align 1 - .thumb_func - .weak RTC_IRQHandler - .type RTC_IRQHandler, %function -RTC_IRQHandler: - ldr r0,=RTC_DriverIRQHandler - bx r0 - .size RTC_IRQHandler, . - RTC_IRQHandler - - .align 1 - .thumb_func - .weak Reserved46_IRQHandler - .type Reserved46_IRQHandler, %function -Reserved46_IRQHandler: - ldr r0,=Reserved46_DriverIRQHandler - bx r0 - .size Reserved46_IRQHandler, . - Reserved46_IRQHandler - - .align 1 - .thumb_func - .weak Reserved47_IRQHandler - .type Reserved47_IRQHandler, %function -Reserved47_IRQHandler: - ldr r0,=Reserved47_DriverIRQHandler - bx r0 - .size Reserved47_IRQHandler, . - Reserved47_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT4_IRQHandler - .type PIN_INT4_IRQHandler, %function -PIN_INT4_IRQHandler: - ldr r0,=PIN_INT4_DriverIRQHandler - bx r0 - .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT5_IRQHandler - .type PIN_INT5_IRQHandler, %function -PIN_INT5_IRQHandler: - ldr r0,=PIN_INT5_DriverIRQHandler - bx r0 - .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT6_IRQHandler - .type PIN_INT6_IRQHandler, %function -PIN_INT6_IRQHandler: - ldr r0,=PIN_INT6_DriverIRQHandler - bx r0 - .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT7_IRQHandler - .type PIN_INT7_IRQHandler, %function -PIN_INT7_IRQHandler: - ldr r0,=PIN_INT7_DriverIRQHandler - bx r0 - .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER2_IRQHandler - .type CTIMER2_IRQHandler, %function -CTIMER2_IRQHandler: - ldr r0,=CTIMER2_DriverIRQHandler - bx r0 - .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER4_IRQHandler - .type CTIMER4_IRQHandler, %function -CTIMER4_IRQHandler: - ldr r0,=CTIMER4_DriverIRQHandler - bx r0 - .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler - - .align 1 - .thumb_func - .weak OS_EVENT_IRQHandler - .type OS_EVENT_IRQHandler, %function -OS_EVENT_IRQHandler: - ldr r0,=OS_EVENT_DriverIRQHandler - bx r0 - .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler - - .align 1 - .thumb_func - .weak Reserved55_IRQHandler - .type Reserved55_IRQHandler, %function -Reserved55_IRQHandler: - ldr r0,=Reserved55_DriverIRQHandler - bx r0 - .size Reserved55_IRQHandler, . - Reserved55_IRQHandler - - .align 1 - .thumb_func - .weak Reserved56_IRQHandler - .type Reserved56_IRQHandler, %function -Reserved56_IRQHandler: - ldr r0,=Reserved56_DriverIRQHandler - bx r0 - .size Reserved56_IRQHandler, . - Reserved56_IRQHandler - - .align 1 - .thumb_func - .weak Reserved57_IRQHandler - .type Reserved57_IRQHandler, %function -Reserved57_IRQHandler: - ldr r0,=Reserved57_DriverIRQHandler - bx r0 - .size Reserved57_IRQHandler, . - Reserved57_IRQHandler - - .align 1 - .thumb_func - .weak Reserved58_IRQHandler - .type Reserved58_IRQHandler, %function -Reserved58_IRQHandler: - ldr r0,=Reserved58_DriverIRQHandler - bx r0 - .size Reserved58_IRQHandler, . - Reserved58_IRQHandler - - .align 1 - .thumb_func - .weak CAN0_IRQ0_IRQHandler - .type CAN0_IRQ0_IRQHandler, %function -CAN0_IRQ0_IRQHandler: - ldr r0,=CAN0_IRQ0_DriverIRQHandler - bx r0 - .size CAN0_IRQ0_IRQHandler, . - CAN0_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak CAN0_IRQ1_IRQHandler - .type CAN0_IRQ1_IRQHandler, %function -CAN0_IRQ1_IRQHandler: - ldr r0,=CAN0_IRQ1_DriverIRQHandler - bx r0 - .size CAN0_IRQ1_IRQHandler, . - CAN0_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak Reserved61_IRQHandler - .type Reserved61_IRQHandler, %function -Reserved61_IRQHandler: - ldr r0,=Reserved61_DriverIRQHandler - bx r0 - .size Reserved61_IRQHandler, . - Reserved61_IRQHandler - - .align 1 - .thumb_func - .weak Reserved62_IRQHandler - .type Reserved62_IRQHandler, %function -Reserved62_IRQHandler: - ldr r0,=Reserved62_DriverIRQHandler - bx r0 - .size Reserved62_IRQHandler, . - Reserved62_IRQHandler - - .align 1 - .thumb_func - .weak Reserved63_IRQHandler - .type Reserved63_IRQHandler, %function -Reserved63_IRQHandler: - ldr r0,=Reserved63_DriverIRQHandler - bx r0 - .size Reserved63_IRQHandler, . - Reserved63_IRQHandler - - .align 1 - .thumb_func - .weak Reserved64_IRQHandler - .type Reserved64_IRQHandler, %function -Reserved64_IRQHandler: - ldr r0,=Reserved64_DriverIRQHandler - bx r0 - .size Reserved64_IRQHandler, . - Reserved64_IRQHandler - - .align 1 - .thumb_func - .weak SEC_HYPERVISOR_CALL_IRQHandler - .type SEC_HYPERVISOR_CALL_IRQHandler, %function -SEC_HYPERVISOR_CALL_IRQHandler: - ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler - bx r0 - .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ0_IRQHandler - .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function -SEC_GPIO_INT0_IRQ0_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ1_IRQHandler - .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function -SEC_GPIO_INT0_IRQ1_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak PLU_IRQHandler - .type PLU_IRQHandler, %function -PLU_IRQHandler: - ldr r0,=PLU_DriverIRQHandler - bx r0 - .size PLU_IRQHandler, . - PLU_IRQHandler - - .align 1 - .thumb_func - .weak SEC_VIO_IRQHandler - .type SEC_VIO_IRQHandler, %function -SEC_VIO_IRQHandler: - ldr r0,=SEC_VIO_DriverIRQHandler - bx r0 - .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler - - .align 1 - .thumb_func - .weak HASHCRYPT_IRQHandler - .type HASHCRYPT_IRQHandler, %function -HASHCRYPT_IRQHandler: - ldr r0,=HASHCRYPT_DriverIRQHandler - bx r0 - .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler - - .align 1 - .thumb_func - .weak CASER_IRQHandler - .type CASER_IRQHandler, %function -CASER_IRQHandler: - ldr r0,=CASER_DriverIRQHandler - bx r0 - .size CASER_IRQHandler, . - CASER_IRQHandler - - .align 1 - .thumb_func - .weak PUF_IRQHandler - .type PUF_IRQHandler, %function -PUF_IRQHandler: - ldr r0,=PUF_DriverIRQHandler - bx r0 - .size PUF_IRQHandler, . - PUF_IRQHandler - - .align 1 - .thumb_func - .weak Reserved73_IRQHandler - .type Reserved73_IRQHandler, %function -Reserved73_IRQHandler: - ldr r0,=Reserved73_DriverIRQHandler - bx r0 - .size Reserved73_IRQHandler, . - Reserved73_IRQHandler - - .align 1 - .thumb_func - .weak DMA1_IRQHandler - .type DMA1_IRQHandler, %function -DMA1_IRQHandler: - ldr r0,=DMA1_DriverIRQHandler - bx r0 - .size DMA1_IRQHandler, . - DMA1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM8_IRQHandler - .type FLEXCOMM8_IRQHandler, %function -FLEXCOMM8_IRQHandler: - ldr r0,=FLEXCOMM8_DriverIRQHandler - bx r0 - .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler - - .align 1 - .thumb_func - .weak CDOG_IRQHandler - .type CDOG_IRQHandler, %function -CDOG_IRQHandler: - ldr r0,=CDOG_DriverIRQHandler - bx r0 - .size CDOG_IRQHandler, . - CDOG_IRQHandler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm -/* Exception Handlers */ - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SecureFault_Handler - def_irq_handler DebugMon_Handler - def_irq_handler WDT_BOD_DriverIRQHandler - def_irq_handler DMA0_DriverIRQHandler - def_irq_handler GINT0_DriverIRQHandler - def_irq_handler GINT1_DriverIRQHandler - def_irq_handler PIN_INT0_DriverIRQHandler - def_irq_handler PIN_INT1_DriverIRQHandler - def_irq_handler PIN_INT2_DriverIRQHandler - def_irq_handler PIN_INT3_DriverIRQHandler - def_irq_handler UTICK0_DriverIRQHandler - def_irq_handler MRT0_DriverIRQHandler - def_irq_handler CTIMER0_DriverIRQHandler - def_irq_handler CTIMER1_DriverIRQHandler - def_irq_handler SCT0_DriverIRQHandler - def_irq_handler CTIMER3_DriverIRQHandler - def_irq_handler FLEXCOMM0_DriverIRQHandler - def_irq_handler FLEXCOMM1_DriverIRQHandler - def_irq_handler FLEXCOMM2_DriverIRQHandler - def_irq_handler FLEXCOMM3_DriverIRQHandler - def_irq_handler FLEXCOMM4_DriverIRQHandler - def_irq_handler FLEXCOMM5_DriverIRQHandler - def_irq_handler FLEXCOMM6_DriverIRQHandler - def_irq_handler FLEXCOMM7_DriverIRQHandler - def_irq_handler ADC0_DriverIRQHandler - def_irq_handler Reserved39_DriverIRQHandler - def_irq_handler ACMP_DriverIRQHandler - def_irq_handler Reserved41_DriverIRQHandler - def_irq_handler Reserved42_DriverIRQHandler - def_irq_handler Reserved43_DriverIRQHandler - def_irq_handler Reserved44_DriverIRQHandler - def_irq_handler RTC_DriverIRQHandler - def_irq_handler Reserved46_DriverIRQHandler - def_irq_handler Reserved47_DriverIRQHandler - def_irq_handler PIN_INT4_DriverIRQHandler - def_irq_handler PIN_INT5_DriverIRQHandler - def_irq_handler PIN_INT6_DriverIRQHandler - def_irq_handler PIN_INT7_DriverIRQHandler - def_irq_handler CTIMER2_DriverIRQHandler - def_irq_handler CTIMER4_DriverIRQHandler - def_irq_handler OS_EVENT_DriverIRQHandler - def_irq_handler Reserved55_DriverIRQHandler - def_irq_handler Reserved56_DriverIRQHandler - def_irq_handler Reserved57_DriverIRQHandler - def_irq_handler Reserved58_DriverIRQHandler - def_irq_handler CAN0_IRQ0_DriverIRQHandler - def_irq_handler CAN0_IRQ1_DriverIRQHandler - def_irq_handler Reserved61_DriverIRQHandler - def_irq_handler Reserved62_DriverIRQHandler - def_irq_handler Reserved63_DriverIRQHandler - def_irq_handler Reserved64_DriverIRQHandler - def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler - def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler - def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler - def_irq_handler PLU_DriverIRQHandler - def_irq_handler SEC_VIO_DriverIRQHandler - def_irq_handler HASHCRYPT_DriverIRQHandler - def_irq_handler CASER_DriverIRQHandler - def_irq_handler PUF_DriverIRQHandler - def_irq_handler Reserved73_DriverIRQHandler - def_irq_handler DMA1_DriverIRQHandler - def_irq_handler FLEXCOMM8_DriverIRQHandler - def_irq_handler CDOG_DriverIRQHandler - - .end diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/iar/LPC55S06_flash.icf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/iar/LPC55S06_flash.icf deleted file mode 100644 index 6bf44a580b2..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/iar/LPC55S06_flash.icf +++ /dev/null @@ -1,93 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S06JBD64 -** LPC55S06JHI48 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55S0x/LPC550x User manual Rev.0.3 14 August 2020 -** Version: rev. 1.0, 2020-04-09 -** Build: b220622 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -define symbol usb_bdt_size = 0x0; -/* Stack and Heap Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define symbol m_interrupts_start = 0x00000000; -define symbol m_interrupts_end = 0x000001FF; - -define symbol m_text_start = 0x00000200; -define symbol m_text_end = 0x0003CFFF; - -define symbol m_data_start = 0x20000000; -define symbol m_data_end = 0x2000FFFF; - -define symbol m_sramx_start = 0x04000000; -define symbol m_sramx_end = 0x04003FFF; - -define symbol m_sram3_start = 0x20010000; -define symbol m_sram3_end = 0x20013FFF; - -define memory mem with size = 4G; - -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -if (isdefinedsymbol(__use_shmem__)) { - define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; -} - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - - -initialize by copy { readwrite, section .textrw }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - /* Required in a multi-threaded application */ - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -if (isdefinedsymbol(__use_shmem__)) { - do not initialize { section rpmsg_sh_mem_section }; -} - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; - - - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/iar/LPC55S06_ram.icf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/iar/LPC55S06_ram.icf deleted file mode 100644 index 2e425b46b20..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/iar/LPC55S06_ram.icf +++ /dev/null @@ -1,90 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S06JBD64 -** LPC55S06JHI48 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55S0x/LPC550x User manual Rev.0.3 14 August 2020 -** Version: rev. 1.0, 2020-04-09 -** Build: b220622 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -define symbol usb_bdt_size = 0x0; -/* Stack and Heap Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define symbol m_interrupts_start = 0x20000000; -define symbol m_interrupts_end = 0x200001FF; - -define symbol m_text_start = 0x20000200; -define symbol m_text_end = 0x2000FFFF; - -define symbol m_data_start = 0x04000000; -define symbol m_data_end = 0x04003FFF; - -define symbol m_sram3_start = 0x20010000; -define symbol m_sram3_end = 0x20013FFF; - -define memory mem with size = 4G; - -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -if (isdefinedsymbol(__use_shmem__)) { - define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; -} - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - - -initialize by copy { readwrite, section .textrw }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - /* Required in a multi-threaded application */ - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -if (isdefinedsymbol(__use_shmem__)) { - do not initialize { section rpmsg_sh_mem_section }; -} - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; - - - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/iar/startup_LPC55S06.s b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/iar/startup_LPC55S06.s deleted file mode 100644 index 53cc554bd62..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/iar/startup_LPC55S06.s +++ /dev/null @@ -1,643 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC55S06.s -; * @purpose: CMSIS Cortex-M33 Core Device Startup File -; * LPC55S06 -; * @version: 1.0 -; * @date: 2020-4-9 -; *---------------------------------------------------------------------------- -; * -; Copyright 1997-2016 Freescale Semiconductor, Inc. -; Copyright 2016-2021 NXP -; All rights reserved. -; -; SPDX-License-Identifier: BSD-3-Clause -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__iar_init$$done: ; The vector table is not needed - ; until after copy initialization is done - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD SecureFault_Handler - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt - DCD DMA0_IRQHandler ; DMA0 controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD ADC0_IRQHandler ; ADC0 - DCD Reserved39_IRQHandler ; Reserved interrupt - DCD ACMP_IRQHandler ; ACMP interrupts - DCD Reserved41_IRQHandler ; Reserved interrupt - DCD Reserved42_IRQHandler ; Reserved interrupt - DCD Reserved43_IRQHandler ; Reserved interrupt - DCD Reserved44_IRQHandler ; Reserved interrupt - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD Reserved46_IRQHandler ; Reserved interrupt - DCD Reserved47_IRQHandler ; Reserved interrupt - DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int - DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int - DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int - DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int - DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 - DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 - DCD OS_EVENT_IRQHandler ; OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts - DCD Reserved55_IRQHandler ; Reserved interrupt - DCD Reserved56_IRQHandler ; Reserved interrupt - DCD Reserved57_IRQHandler ; Reserved interrupt - DCD Reserved58_IRQHandler ; Reserved interrupt - DCD CAN0_IRQ0_IRQHandler ; CAN0 interrupt0 - DCD CAN0_IRQ1_IRQHandler ; CAN0 interrupt1 - DCD Reserved61_IRQHandler ; Reserved interrupt - DCD Reserved62_IRQHandler ; Reserved interrupt - DCD Reserved63_IRQHandler ; Reserved interrupt - DCD Reserved64_IRQHandler ; Reserved interrupt - DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt - DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT0_IRQ0 interrupt - DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT0_IRQ1 interrupt - DCD PLU_IRQHandler ; PLU interrupt - DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt - DCD HASHCRYPT_IRQHandler ; SHA interrupt - DCD CASER_IRQHandler ; CASPER interrupt - DCD PUF_IRQHandler ; PUF interrupt - DCD Reserved73_IRQHandler ; Reserved interrupt - DCD DMA1_IRQHandler ; DMA1 interrupt - DCD FLEXCOMM8_IRQHandler ; Flexcomm Interface 8 (SPI, , FLEXCOMM) - DCD CDOG_IRQHandler ; CDOG interrupt -__Vectors_End - - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__vector_table - STR R1, [R0] - LDR R2, [R1] - MSR MSP, R2 - LDR R0, =sfb(CSTACK) - MSR MSPLIM, R0 - CPSIE I ; Unmask interrupts - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SecureFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SecureFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK WDT_BOD_IRQHandler - PUBWEAK WDT_BOD_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -WDT_BOD_IRQHandler - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler - LDR R0, =DMA0_DriverIRQHandler - BX R0 - PUBWEAK GINT0_IRQHandler - PUBWEAK GINT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT0_IRQHandler - LDR R0, =GINT0_DriverIRQHandler - BX R0 - PUBWEAK GINT1_IRQHandler - PUBWEAK GINT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT1_IRQHandler - LDR R0, =GINT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT0_IRQHandler - PUBWEAK PIN_INT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT0_IRQHandler - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT1_IRQHandler - PUBWEAK PIN_INT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT1_IRQHandler - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT2_IRQHandler - PUBWEAK PIN_INT2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT2_IRQHandler - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT3_IRQHandler - PUBWEAK PIN_INT3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT3_IRQHandler - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - PUBWEAK UTICK0_IRQHandler - PUBWEAK UTICK0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UTICK0_IRQHandler - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - PUBWEAK MRT0_IRQHandler - PUBWEAK MRT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -MRT0_IRQHandler - LDR R0, =MRT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER0_IRQHandler - PUBWEAK CTIMER0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER0_IRQHandler - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER1_IRQHandler - PUBWEAK CTIMER1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER1_IRQHandler - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - PUBWEAK SCT0_IRQHandler - PUBWEAK SCT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SCT0_IRQHandler - LDR R0, =SCT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER3_IRQHandler - PUBWEAK CTIMER3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER3_IRQHandler - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM0_IRQHandler - PUBWEAK FLEXCOMM0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM0_IRQHandler - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM1_IRQHandler - PUBWEAK FLEXCOMM1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM1_IRQHandler - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM2_IRQHandler - PUBWEAK FLEXCOMM2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM2_IRQHandler - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM3_IRQHandler - PUBWEAK FLEXCOMM3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM3_IRQHandler - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM4_IRQHandler - PUBWEAK FLEXCOMM4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM4_IRQHandler - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM5_IRQHandler - PUBWEAK FLEXCOMM5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM5_IRQHandler - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM6_IRQHandler - PUBWEAK FLEXCOMM6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM6_IRQHandler - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM7_IRQHandler - PUBWEAK FLEXCOMM7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM7_IRQHandler - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - PUBWEAK ADC0_IRQHandler - PUBWEAK ADC0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_IRQHandler - LDR R0, =ADC0_DriverIRQHandler - BX R0 - PUBWEAK Reserved39_IRQHandler - PUBWEAK Reserved39_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved39_IRQHandler - LDR R0, =Reserved39_DriverIRQHandler - BX R0 - PUBWEAK ACMP_IRQHandler - PUBWEAK ACMP_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ACMP_IRQHandler - LDR R0, =ACMP_DriverIRQHandler - BX R0 - PUBWEAK Reserved41_IRQHandler - PUBWEAK Reserved41_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved41_IRQHandler - LDR R0, =Reserved41_DriverIRQHandler - BX R0 - PUBWEAK Reserved42_IRQHandler - PUBWEAK Reserved42_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved42_IRQHandler - LDR R0, =Reserved42_DriverIRQHandler - BX R0 - PUBWEAK Reserved43_IRQHandler - PUBWEAK Reserved43_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved43_IRQHandler - LDR R0, =Reserved43_DriverIRQHandler - BX R0 - PUBWEAK Reserved44_IRQHandler - PUBWEAK Reserved44_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved44_IRQHandler - LDR R0, =Reserved44_DriverIRQHandler - BX R0 - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -RTC_IRQHandler - LDR R0, =RTC_DriverIRQHandler - BX R0 - PUBWEAK Reserved46_IRQHandler - PUBWEAK Reserved46_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved46_IRQHandler - LDR R0, =Reserved46_DriverIRQHandler - BX R0 - PUBWEAK Reserved47_IRQHandler - PUBWEAK Reserved47_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved47_IRQHandler - LDR R0, =Reserved47_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT4_IRQHandler - PUBWEAK PIN_INT4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT4_IRQHandler - LDR R0, =PIN_INT4_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT5_IRQHandler - PUBWEAK PIN_INT5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT5_IRQHandler - LDR R0, =PIN_INT5_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT6_IRQHandler - PUBWEAK PIN_INT6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT6_IRQHandler - LDR R0, =PIN_INT6_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT7_IRQHandler - PUBWEAK PIN_INT7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT7_IRQHandler - LDR R0, =PIN_INT7_DriverIRQHandler - BX R0 - PUBWEAK CTIMER2_IRQHandler - PUBWEAK CTIMER2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER2_IRQHandler - LDR R0, =CTIMER2_DriverIRQHandler - BX R0 - PUBWEAK CTIMER4_IRQHandler - PUBWEAK CTIMER4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER4_IRQHandler - LDR R0, =CTIMER4_DriverIRQHandler - BX R0 - PUBWEAK OS_EVENT_IRQHandler - PUBWEAK OS_EVENT_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -OS_EVENT_IRQHandler - LDR R0, =OS_EVENT_DriverIRQHandler - BX R0 - PUBWEAK Reserved55_IRQHandler - PUBWEAK Reserved55_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved55_IRQHandler - LDR R0, =Reserved55_DriverIRQHandler - BX R0 - PUBWEAK Reserved56_IRQHandler - PUBWEAK Reserved56_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved56_IRQHandler - LDR R0, =Reserved56_DriverIRQHandler - BX R0 - PUBWEAK Reserved57_IRQHandler - PUBWEAK Reserved57_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved57_IRQHandler - LDR R0, =Reserved57_DriverIRQHandler - BX R0 - PUBWEAK Reserved58_IRQHandler - PUBWEAK Reserved58_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved58_IRQHandler - LDR R0, =Reserved58_DriverIRQHandler - BX R0 - PUBWEAK CAN0_IRQ0_IRQHandler - PUBWEAK CAN0_IRQ0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CAN0_IRQ0_IRQHandler - LDR R0, =CAN0_IRQ0_DriverIRQHandler - BX R0 - PUBWEAK CAN0_IRQ1_IRQHandler - PUBWEAK CAN0_IRQ1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CAN0_IRQ1_IRQHandler - LDR R0, =CAN0_IRQ1_DriverIRQHandler - BX R0 - PUBWEAK Reserved61_IRQHandler - PUBWEAK Reserved61_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved61_IRQHandler - LDR R0, =Reserved61_DriverIRQHandler - BX R0 - PUBWEAK Reserved62_IRQHandler - PUBWEAK Reserved62_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved62_IRQHandler - LDR R0, =Reserved62_DriverIRQHandler - BX R0 - PUBWEAK Reserved63_IRQHandler - PUBWEAK Reserved63_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved63_IRQHandler - LDR R0, =Reserved63_DriverIRQHandler - BX R0 - PUBWEAK Reserved64_IRQHandler - PUBWEAK Reserved64_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved64_IRQHandler - LDR R0, =Reserved64_DriverIRQHandler - BX R0 - PUBWEAK SEC_HYPERVISOR_CALL_IRQHandler - PUBWEAK SEC_HYPERVISOR_CALL_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_HYPERVISOR_CALL_IRQHandler - LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler - BX R0 - PUBWEAK SEC_GPIO_INT0_IRQ0_IRQHandler - PUBWEAK SEC_GPIO_INT0_IRQ0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_GPIO_INT0_IRQ0_IRQHandler - LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler - BX R0 - PUBWEAK SEC_GPIO_INT0_IRQ1_IRQHandler - PUBWEAK SEC_GPIO_INT0_IRQ1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_GPIO_INT0_IRQ1_IRQHandler - LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler - BX R0 - PUBWEAK PLU_IRQHandler - PUBWEAK PLU_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PLU_IRQHandler - LDR R0, =PLU_DriverIRQHandler - BX R0 - PUBWEAK SEC_VIO_IRQHandler - PUBWEAK SEC_VIO_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_VIO_IRQHandler - LDR R0, =SEC_VIO_DriverIRQHandler - BX R0 - PUBWEAK HASHCRYPT_IRQHandler - PUBWEAK HASHCRYPT_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -HASHCRYPT_IRQHandler - LDR R0, =HASHCRYPT_DriverIRQHandler - BX R0 - PUBWEAK CASER_IRQHandler - PUBWEAK CASER_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CASER_IRQHandler - LDR R0, =CASER_DriverIRQHandler - BX R0 - PUBWEAK PUF_IRQHandler - PUBWEAK PUF_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PUF_IRQHandler - LDR R0, =PUF_DriverIRQHandler - BX R0 - PUBWEAK Reserved73_IRQHandler - PUBWEAK Reserved73_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved73_IRQHandler - LDR R0, =Reserved73_DriverIRQHandler - BX R0 - PUBWEAK DMA1_IRQHandler - PUBWEAK DMA1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA1_IRQHandler - LDR R0, =DMA1_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM8_IRQHandler - PUBWEAK FLEXCOMM8_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM8_IRQHandler - LDR R0, =FLEXCOMM8_DriverIRQHandler - BX R0 - PUBWEAK CDOG_IRQHandler - PUBWEAK CDOG_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CDOG_IRQHandler - LDR R0, =CDOG_DriverIRQHandler - BX R0 -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_DriverIRQHandler -Reserved39_DriverIRQHandler -ACMP_DriverIRQHandler -Reserved41_DriverIRQHandler -Reserved42_DriverIRQHandler -Reserved43_DriverIRQHandler -Reserved44_DriverIRQHandler -RTC_DriverIRQHandler -Reserved46_DriverIRQHandler -Reserved47_DriverIRQHandler -PIN_INT4_DriverIRQHandler -PIN_INT5_DriverIRQHandler -PIN_INT6_DriverIRQHandler -PIN_INT7_DriverIRQHandler -CTIMER2_DriverIRQHandler -CTIMER4_DriverIRQHandler -OS_EVENT_DriverIRQHandler -Reserved55_DriverIRQHandler -Reserved56_DriverIRQHandler -Reserved57_DriverIRQHandler -Reserved58_DriverIRQHandler -CAN0_IRQ0_DriverIRQHandler -CAN0_IRQ1_DriverIRQHandler -Reserved61_DriverIRQHandler -Reserved62_DriverIRQHandler -Reserved63_DriverIRQHandler -Reserved64_DriverIRQHandler -SEC_HYPERVISOR_CALL_DriverIRQHandler -SEC_GPIO_INT0_IRQ0_DriverIRQHandler -SEC_GPIO_INT0_IRQ1_DriverIRQHandler -PLU_DriverIRQHandler -SEC_VIO_DriverIRQHandler -HASHCRYPT_DriverIRQHandler -CASER_DriverIRQHandler -PUF_DriverIRQHandler -Reserved73_DriverIRQHandler -DMA1_DriverIRQHandler -FLEXCOMM8_DriverIRQHandler -CDOG_DriverIRQHandler -DefaultISR - B . - - END diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/system_LPC55S06.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/system_LPC55S06.c deleted file mode 100644 index c6ee2cdba9d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/system_LPC55S06.c +++ /dev/null @@ -1,389 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S06JBD64 -** LPC55S06JHI48 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55S0x/LPC550x User manual Rev.0.3 14 August 2020 -** Version: rev. 1.0, 2020-04-09 -** Build: b220117 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2020-04-09) -** Initial version based on Niobe4mini -** -** ################################################################### -*/ - -/*! - * @file LPC55S06 - * @version 1.0 - * @date 2020-04-09 - * @brief Device specific configuration file for LPC55S06 (implementation file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include -#include "fsl_device_registers.h" - -/* PLL0 SSCG control1 */ -#define PLL_SSCG_MD_FRACT_P 0U -#define PLL_SSCG_MD_INT_P 25U -#define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P) -#define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P) - -/* Get predivider (N) from PLL0 NDEC setting */ -static uint32_t findPll0PreDiv(void) -{ - uint32_t preDiv = 1UL; - - /* Direct input is not used? */ - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) - { - preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; - if (preDiv == 0UL) - { - preDiv = 1UL; - } - } - return preDiv; -} - -/* Get postdivider (P) from PLL0 PDEC setting */ -static uint32_t findPll0PostDiv(void) -{ - uint32_t postDiv = 1; - - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) - { - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) - { - postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; - } - else - { - postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); - } - if (postDiv == 0UL) - { - postDiv = 2UL; - } - } - return postDiv; -} - -/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ -static float findPll0MMult(void) -{ - float mMult = 1.0F; - float mMult_fract; - uint32_t mMult_int; - - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) - { - mMult = (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); - } - else - { - mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); - mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P); - mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M) / - (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); - mMult = (float)mMult_int + mMult_fract; - } - if (0ULL == ((uint64_t)mMult)) - { - mMult = 1.0F; - } - return mMult; -} - -/* Get predivider (N) from PLL1 NDEC setting */ -static uint32_t findPll1PreDiv(void) -{ - uint32_t preDiv = 1UL; - - /* Direct input is not used? */ - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) - { - preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; - if (preDiv == 0UL) - { - preDiv = 1UL; - } - } - return preDiv; -} - -/* Get postdivider (P) from PLL1 PDEC setting */ -static uint32_t findPll1PostDiv(void) -{ - uint32_t postDiv = 1UL; - - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0UL) - { - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) != 0UL) - { - postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK; - } - else - { - postDiv = 2UL * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK); - } - if (postDiv == 0UL) - { - postDiv = 2UL; - } - } - return postDiv; -} - -/* Get multiplier (M) from PLL1 MDEC settings */ -static uint32_t findPll1MMult(void) -{ - uint32_t mMult = 1UL; - - mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK; - - if (mMult == 0UL) - { - mMult = 1UL; - } - return mMult; -} - -/* Get FRO 12M Clk */ -/*! brief Return Frequency of FRO 12MHz - * return Frequency of FRO 12MHz - */ -static uint32_t GetFro12MFreq(void) -{ - return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; -} - -/* Get FRO 1M Clk */ -/*! brief Return Frequency of FRO 1MHz - * return Frequency of FRO 1MHz - */ -static uint32_t GetFro1MFreq(void) -{ - return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; -} - -/* Get EXT OSC Clk */ -/*! brief Return Frequency of External Clock - * return Frequency of External Clock. If no external clock is used returns 0. - */ -static uint32_t GetExtClkFreq(void) -{ - return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? CLK_CLK_IN : 0U; -} - -/* Get HF FRO Clk */ -/*! brief Return Frequency of High-Freq output of FRO - * return Frequency of High-Freq output of FRO - */ -static uint32_t GetFroHfFreq(void) -{ - return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; -} - -/* Get RTC OSC Clk */ -/*! brief Return Frequency of 32kHz osc - * return Frequency of 32kHz osc - */ -static uint32_t GetOsc32KFreq(void) -{ - return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? - CLK_RTC_32K_CLK : - ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && ((PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK) != 0UL)) ? - CLK_RTC_32K_CLK : - 0U; -} - - - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ - -__attribute__ ((weak)) void SystemInit (void) { -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ - #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ - - SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ - -#if defined(__MCUXPRESSO) - extern void(*const g_pfnVectors[]) (void); - SCB->VTOR = (uint32_t) &g_pfnVectors; -#else - extern void *__Vectors; - SCB->VTOR = (uint32_t) &__Vectors; -#endif - SYSCON->TRACECLKDIV = 0; -/* Optionally enable RAM banks that may be off by default at reset */ -#if !defined(DONT_ENABLE_DISABLED_RAMBANKS) - SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK; - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_SRAM_CTRL3_MASK; -#endif - /* Following code is to reset PUF to remove over consumption */ - /* Enable PUF register clock to access register */ - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_PUF_MASK; - /* Release PUF reset */ - SYSCON->PRESETCTRLCLR[2] = SYSCON_PRESETCTRL2_PUF_RST_MASK; - /* Enable PUF SRAM */ - PUF_SRAM_CTRL->CFG |= PUF_SRAM_CTRL_CFG_ENABLE_MASK | PUF_SRAM_CTRL_CFG_CKGATING_MASK; - /* Disable PUF register clock. */ - // Delaying the line of code below until the PUF State Machine execution is completed: - // Shutting down the clock to early will prevent the state machine from reaching the end. - // => Wait for status bit in PUF Controller Registers before stop PUF clock. - while (!(PUF_SRAM_CTRL->INT_STATUS & PUF_SRAM_CTRL_INT_STATUS_READY_MASK)) - ; - SYSCON->AHBCLKCTRLCLR[2] = SYSCON_AHBCLKCTRL2_PUF_MASK; - SystemInitHook(); -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate (void) { - uint32_t clkRate = 0; - uint32_t prediv, postdiv; - uint64_t workRate; - uint64_t workRate1; - - switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) - { - case 0x00: /* MAINCLKSELA clock (main_clk_a)*/ - switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = GetFro12MFreq(); - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = GetExtClkFreq(); - break; - case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = GetFro1MFreq(); - break; - default: /* = 0x03 = FRO 96 MHz (fro_hf) */ - clkRate = GetFroHfFreq(); - break; - } - break; - case 0x01: /* PLL0 clock (pll0_clk)*/ - switch (SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = GetFro12MFreq(); - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = GetExtClkFreq(); - break; - case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = GetFro1MFreq(); - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = GetOsc32KFreq(); - break; - default: - clkRate = 0UL; - break; - } - if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) - { - prediv = findPll0PreDiv(); - postdiv = findPll0PostDiv(); - /* Adjust input clock */ - clkRate = clkRate / prediv; - /* MDEC used for rate */ - workRate = (uint64_t)clkRate * (uint64_t)findPll0MMult(); - clkRate = (uint32_t)(workRate / ((uint64_t)postdiv)); - } - break; - case 0x02: /* PLL1 clock (pll1_clk)*/ - switch (SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = GetFro12MFreq(); - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = GetExtClkFreq(); - break; - case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = GetFro1MFreq(); - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = GetOsc32KFreq(); - break; - default: - clkRate = 0UL; - break; - } - if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0UL)) - { - /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ - prediv = findPll1PreDiv(); - postdiv = findPll1PostDiv(); - /* Adjust input clock */ - clkRate = clkRate / prediv; - - /* MDEC used for rate */ - workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult(); - clkRate = (uint32_t)(workRate1 / ((uint64_t)postdiv)); - } - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = GetOsc32KFreq(); - break; - default: - clkRate = 0UL; - break; - } - SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL); -} - -/* ---------------------------------------------------------------------------- - -- SystemInitHook() - ---------------------------------------------------------------------------- */ - -__attribute__ ((weak)) void SystemInitHook (void) { - /* Void implementation of the weak function. */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/system_LPC55S06.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/system_LPC55S06.h deleted file mode 100644 index fd51ebed3b0..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/LPC55S06/system_LPC55S06.h +++ /dev/null @@ -1,109 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S06JBD64 -** LPC55S06JHI48 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55S0x/LPC550x User manual Rev.0.3 14 August 2020 -** Version: rev. 1.0, 2020-04-09 -** Build: b220117 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2020-04-09) -** Initial version based on Niobe4mini -** -** ################################################################### -*/ - -/*! - * @file LPC55S06 - * @version 1.0 - * @date 2020-04-09 - * @brief Device specific configuration file for LPC55S06 (header file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef _SYSTEM_LPC55S06_H_ -#define _SYSTEM_LPC55S06_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ -#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ -#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ -#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ -#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ -#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ - - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -/** - * @brief SystemInit function hook. - * - * This weak function allows to call specific initialization code during the - * SystemInit() execution.This can be used when an application specific code needs - * to be called as close to the reset entry as possible (for example the Multicore - * Manager MCMGR_EarlyInit() function call). - * NOTE: No global r/w variables can be used in this hook function because the - * initialization of these variables happens after this function. - */ -void SystemInitHook (void); - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_LPC55S06_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/SConscript b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/SConscript deleted file mode 100644 index 0f93927580f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S06/SConscript +++ /dev/null @@ -1,58 +0,0 @@ -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -path = [cwd + '/../CMSIS/Core/Include',cwd + '/components/codec', cwd + '/LPC55S06', cwd + '/LPC55S06/drivers', cwd + '/middleware/sdmmc/port'] -src = Split(''' - LPC55S06/system_LPC55S06.c - ''') - -if rtconfig.PLATFORM in ['gcc']: - src += ['LPC55S06/gcc/startup_LPC55S06.S'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - src += ['LPC55S06/arm/startup_LPC55S06.s'] -elif rtconfig.PLATFORM in ['iccarm']: - src += ['LPC55S06/iar/startup_LPC55S06.s'] - -src += ['LPC55S06/drivers/fsl_anactrl.c'] -src += ['LPC55S06/drivers/fsl_casper.c'] -src += ['LPC55S06/drivers/fsl_clock.c'] -src += ['LPC55S06/drivers/fsl_cmp.c'] -src += ['LPC55S06/drivers/fsl_common.c'] -src += ['LPC55S06/drivers/fsl_common_arm.c'] -src += ['LPC55S06/drivers/fsl_crc.c'] -src += ['LPC55S06/drivers/fsl_ctimer.c'] -src += ['LPC55S06/drivers/fsl_flexcomm.c'] -src += ['LPC55S06/drivers/fsl_dma.c'] -src += ['LPC55S06/drivers/fsl_gint.c'] -src += ['LPC55S06/drivers/fsl_gpio.c'] -src += ['LPC55S06/drivers/fsl_hashcrypt.c'] -src += ['LPC55S06/drivers/fsl_i2c.c'] -src += ['LPC55S06/drivers/fsl_i2c_dma.c'] -src += ['LPC55S06/drivers/fsl_i2s.c'] -src += ['LPC55S06/drivers/fsl_i2s_dma.c'] -src += ['LPC55S06/drivers/fsl_iap.c'] -src += ['LPC55S06/drivers/fsl_inputmux.c'] -src += ['LPC55S06/drivers/fsl_lpadc.c'] -src += ['LPC55S06/drivers/fsl_mrt.c'] -src += ['LPC55S06/drivers/fsl_ostimer.c'] -src += ['LPC55S06/drivers/fsl_pint.c'] -src += ['LPC55S06/drivers/fsl_plu.c'] -src += ['LPC55S06/drivers/fsl_power.c'] -src += ['LPC55S06/drivers/fsl_puf.c'] -src += ['LPC55S06/drivers/fsl_reset.c'] -src += ['LPC55S06/drivers/fsl_rng.c'] -src += ['LPC55S06/drivers/fsl_rtc.c'] -src += ['LPC55S06/drivers/fsl_sctimer.c'] -src += ['LPC55S06/drivers/fsl_spi.c'] -src += ['LPC55S06/drivers/fsl_spi_dma.c'] -src += ['LPC55S06/drivers/fsl_sysctl.c'] -src += ['LPC55S06/drivers/fsl_usart.c'] -src += ['LPC55S06/drivers/fsl_usart_dma.c'] -src += ['LPC55S06/drivers/fsl_utick.c'] -src += ['LPC55S06/drivers/fsl_wwdt.c'] - - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) - -Return('group') diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/LPC55S16.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/LPC55S16.h deleted file mode 100644 index 99470354a87..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/LPC55S16.h +++ /dev/null @@ -1,33285 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S16JBD100 -** LPC55S16JBD64 -** LPC55S16JEV59 -** LPC55S16JEV98 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 -** Version: rev. 1.1, 2019-12-03 -** Build: b220301 -** -** Abstract: -** CMSIS Peripheral Access Layer for LPC55S16 -** -** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** - rev. 1.1 (2019-12-03) -** Initial version based on v0.6UM -** -** ################################################################### -*/ - -/*! - * @file LPC55S16.h - * @version 1.1 - * @date 2019-12-03 - * @brief CMSIS Peripheral Access Layer for LPC55S16 - * - * CMSIS Peripheral Access Layer for LPC55S16 - */ - -#ifndef _LPC55S16_H_ -#define _LPC55S16_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0001U - - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 77 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Auxiliary constants */ - NotAvail_IRQn = -128, /**< Not available device specific interrupt */ - - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ - - /* Device specific interrupts */ - WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */ - DMA0_IRQn = 1, /**< DMA0 controller */ - GINT0_IRQn = 2, /**< GPIO group 0 */ - GINT1_IRQn = 3, /**< GPIO group 1 */ - PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ - PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ - PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ - PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ - UTICK0_IRQn = 8, /**< Micro-tick Timer */ - MRT0_IRQn = 9, /**< Multi-rate timer */ - CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ - CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ - SCT0_IRQn = 12, /**< SCTimer/PWM */ - CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ - FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - ADC0_IRQn = 22, /**< ADC0 */ - Reserved39_IRQn = 23, /**< Reserved interrupt */ - ACMP_IRQn = 24, /**< ACMP interrupts */ - Reserved41_IRQn = 25, /**< Reserved interrupt */ - Reserved42_IRQn = 26, /**< Reserved interrupt */ - USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ - USB0_IRQn = 28, /**< USB device */ - RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ - Reserved46_IRQn = 30, /**< Reserved interrupt */ - Reserved47_IRQn = 31, /**< Reserved interrupt */ - PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ - PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ - PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ - PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ - CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ - CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ - OS_EVENT_IRQn = 38, /**< OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ - Reserved55_IRQn = 39, /**< Reserved interrupt */ - Reserved56_IRQn = 40, /**< Reserved interrupt */ - Reserved57_IRQn = 41, /**< Reserved interrupt */ - Reserved58_IRQn = 42, /**< Reserved interrupt */ - CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */ - CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */ - Reserved61_IRQn = 45, /**< Reserved interrupt */ - USB1_PHY_IRQn = 46, /**< USB1_PHY */ - USB1_IRQn = 47, /**< USB1 interrupt */ - USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ - SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */ - SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */ - SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */ - PLU_IRQn = 52, /**< PLU interrupt */ - SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */ - HASHCRYPT_IRQn = 54, /**< SHA interrupt */ - CASER_IRQn = 55, /**< CASPER interrupt */ - PUF_IRQn = 56, /**< PUF interrupt */ - Reserved73_IRQn = 57, /**< Reserved interrupt */ - DMA1_IRQn = 58, /**< DMA1 interrupt */ - FLEXCOMM8_IRQn = 59, /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */ - CDOG_IRQn = 60 /**< CDOG interrupt */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M33 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration - * @{ - */ - -#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ -#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ -#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ -#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ - -#include "core_cm33.h" /* Core Peripheral Access Layer */ -#include "system_LPC55S16.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Mapping Information - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Mapping_Information Mapping Information - * @{ - */ - -/** Mapping Information */ -/*! - * @addtogroup dma_request - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief Structure for the DMA hardware request - * - * Defines the structure for the DMA hardware request collections. The user can configure the - * hardware request to trigger the DMA transfer accordingly. The index - * of the hardware request varies according to the to SoC. - */ -typedef enum _dma_request_source -{ - kDma0RequestHashCrypt = 0U, /**< HashCrypt */ - kDma1RequestHashCrypt = 0U, /**< HashCrypt */ - kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ - kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ - kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ - kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ - kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ - kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ - kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ - kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ - kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ - kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ - kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ - kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ - kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ - kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ - kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ - kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ - kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ - kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ - kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */ - kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */ - kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */ - kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */ - kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */ - kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */ - kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */ - kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */ - kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */ - kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */ - kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */ - kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */ - kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */ -} dma_request_source_t; - -/* @} */ - - -/*! - * @} - */ /* end of group Mapping_Information */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #else - #pragma push - #pragma anon_unions - #endif -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ - __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ - __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ - __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ - __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ - __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ - uint8_t RESERVED_1[12]; - __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ - __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ - uint8_t RESERVED_2[4]; - __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ - uint8_t RESERVED_3[92]; - __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ - __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ - uint8_t RESERVED_4[8]; - __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ - __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ - struct { /* offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ - } CMD[15]; - uint8_t RESERVED_5[136]; - __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_6[240]; - __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ - uint8_t RESERVED_7[248]; - __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ - uint8_t RESERVED_8[124]; - __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ - -#define ADC_VERID_RES_MASK (0x1U) -#define ADC_VERID_RES_SHIFT (0U) -/*! RES - Resolution - * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. - * 0b1..Up to 16-bit differential/16-bit single ended resolution supported. - */ -#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) - -#define ADC_VERID_DIFFEN_MASK (0x2U) -#define ADC_VERID_DIFFEN_SHIFT (1U) -/*! DIFFEN - Differential Supported - * 0b0..Differential operation not supported. - * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented. - */ -#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) - -#define ADC_VERID_MVI_MASK (0x8U) -#define ADC_VERID_MVI_SHIFT (3U) -/*! MVI - Multi Vref Implemented - * 0b0..Single voltage reference high (VREFH) input supported. - * 0b1..Multiple voltage reference high (VREFH) inputs supported. - */ -#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) - -#define ADC_VERID_CSW_MASK (0x70U) -#define ADC_VERID_CSW_SHIFT (4U) -/*! CSW - Channel Scale Width - * 0b000..Channel scaling not supported. - * 0b001..Channel scaling supported. 1-bit CSCALE control field. - * 0b110..Channel scaling supported. 6-bit CSCALE control field. - */ -#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) - -#define ADC_VERID_VR1RNGI_MASK (0x100U) -#define ADC_VERID_VR1RNGI_SHIFT (8U) -/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented - * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. - * 0b1..Range control required. CFG[VREF1RNG] is implemented. - */ -#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) - -#define ADC_VERID_IADCKI_MASK (0x200U) -#define ADC_VERID_IADCKI_SHIFT (9U) -/*! IADCKI - Internal ADC Clock implemented - * 0b0..Internal clock source not implemented. - * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. - */ -#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) - -#define ADC_VERID_CALOFSI_MASK (0x400U) -#define ADC_VERID_CALOFSI_SHIFT (10U) -/*! CALOFSI - Calibration Function Implemented - * 0b0..Calibration Not Implemented. - * 0b1..Calibration Implemented. - */ -#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) - -#define ADC_VERID_NUM_SEC_MASK (0x800U) -#define ADC_VERID_NUM_SEC_SHIFT (11U) -/*! NUM_SEC - Number of Single Ended Outputs Supported - * 0b0..This design supports one single ended conversion at a time. - * 0b1..This design supports two simultanious single ended conversions. - */ -#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) - -#define ADC_VERID_NUM_FIFO_MASK (0x7000U) -#define ADC_VERID_NUM_FIFO_SHIFT (12U) -/*! NUM_FIFO - Number of FIFOs - * 0b000..N/A - * 0b001..This design supports one result FIFO. - * 0b010..This design supports two result FIFOs. - * 0b011..This design supports three result FIFOs. - * 0b100..This design supports four result FIFOs. - */ -#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) - -#define ADC_VERID_MINOR_MASK (0xFF0000U) -#define ADC_VERID_MINOR_SHIFT (16U) -/*! MINOR - Minor Version Number - */ -#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) - -#define ADC_VERID_MAJOR_MASK (0xFF000000U) -#define ADC_VERID_MAJOR_SHIFT (24U) -/*! MAJOR - Major Version Number - */ -#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ - -#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) -#define ADC_PARAM_TRIG_NUM_SHIFT (0U) -/*! TRIG_NUM - Trigger Number - */ -#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) - -#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) -#define ADC_PARAM_FIFOSIZE_SHIFT (8U) -/*! FIFOSIZE - Result FIFO Depth - * 0b00000001..Result FIFO depth = 1 dataword. - * 0b00000100..Result FIFO depth = 4 datawords. - * 0b00001000..Result FIFO depth = 8 datawords. - * 0b00010000..Result FIFO depth = 16 datawords. - * 0b00100000..Result FIFO depth = 32 datawords. - * 0b01000000..Result FIFO depth = 64 datawords. - */ -#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) - -#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) -#define ADC_PARAM_CV_NUM_SHIFT (16U) -/*! CV_NUM - Compare Value Number - */ -#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) - -#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) -#define ADC_PARAM_CMD_NUM_SHIFT (24U) -/*! CMD_NUM - Command Buffer Number - */ -#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) -/*! @} */ - -/*! @name CTRL - ADC Control Register */ -/*! @{ */ - -#define ADC_CTRL_ADCEN_MASK (0x1U) -#define ADC_CTRL_ADCEN_SHIFT (0U) -/*! ADCEN - ADC Enable - * 0b0..ADC is disabled. - * 0b1..ADC is enabled. - */ -#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) - -#define ADC_CTRL_RST_MASK (0x2U) -#define ADC_CTRL_RST_SHIFT (1U) -/*! RST - Software Reset - * 0b0..ADC logic is not reset. - * 0b1..ADC logic is reset. - */ -#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) - -#define ADC_CTRL_DOZEN_MASK (0x4U) -#define ADC_CTRL_DOZEN_SHIFT (2U) -/*! DOZEN - Doze Enable - * 0b0..ADC is enabled in Doze mode. - * 0b1..ADC is disabled in Doze mode. - */ -#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) - -#define ADC_CTRL_CAL_REQ_MASK (0x8U) -#define ADC_CTRL_CAL_REQ_SHIFT (3U) -/*! CAL_REQ - Auto-Calibration Request - * 0b0..No request for auto-calibration has been made. - * 0b1..A request for auto-calibration has been made - */ -#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) - -#define ADC_CTRL_CALOFS_MASK (0x10U) -#define ADC_CTRL_CALOFS_SHIFT (4U) -/*! CALOFS - Configure for offset calibration function - * 0b0..Calibration function disabled - * 0b1..Request for offset calibration function - */ -#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) - -#define ADC_CTRL_RSTFIFO0_MASK (0x100U) -#define ADC_CTRL_RSTFIFO0_SHIFT (8U) -/*! RSTFIFO0 - Reset FIFO 0 - * 0b0..No effect. - * 0b1..FIFO 0 is reset. - */ -#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) - -#define ADC_CTRL_RSTFIFO1_MASK (0x200U) -#define ADC_CTRL_RSTFIFO1_SHIFT (9U) -/*! RSTFIFO1 - Reset FIFO 1 - * 0b0..No effect. - * 0b1..FIFO 1 is reset. - */ -#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) - -#define ADC_CTRL_CAL_AVGS_MASK (0x70000U) -#define ADC_CTRL_CAL_AVGS_SHIFT (16U) -/*! CAL_AVGS - Auto-Calibration Averages - * 0b000..Single conversion. - * 0b001..2 conversions averaged. - * 0b010..4 conversions averaged. - * 0b011..8 conversions averaged. - * 0b100..16 conversions averaged. - * 0b101..32 conversions averaged. - * 0b110..64 conversions averaged. - * 0b111..128 conversions averaged. - */ -#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) -/*! @} */ - -/*! @name STAT - ADC Status Register */ -/*! @{ */ - -#define ADC_STAT_RDY0_MASK (0x1U) -#define ADC_STAT_RDY0_SHIFT (0U) -/*! RDY0 - Result FIFO 0 Ready Flag - * 0b0..Result FIFO 0 data level not above watermark level. - * 0b1..Result FIFO 0 holding data above watermark level. - */ -#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) - -#define ADC_STAT_FOF0_MASK (0x2U) -#define ADC_STAT_FOF0_SHIFT (1U) -/*! FOF0 - Result FIFO 0 Overflow Flag - * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) - -#define ADC_STAT_RDY1_MASK (0x4U) -#define ADC_STAT_RDY1_SHIFT (2U) -/*! RDY1 - Result FIFO1 Ready Flag - * 0b0..Result FIFO1 data level not above watermark level. - * 0b1..Result FIFO1 holding data above watermark level. - */ -#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) - -#define ADC_STAT_FOF1_MASK (0x8U) -#define ADC_STAT_FOF1_SHIFT (3U) -/*! FOF1 - Result FIFO1 Overflow Flag - * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) - -#define ADC_STAT_TEXC_INT_MASK (0x100U) -#define ADC_STAT_TEXC_INT_SHIFT (8U) -/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception - * 0b0..No trigger exceptions have occurred. - * 0b1..A trigger exception has occurred and is pending acknowledgement. - */ -#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) - -#define ADC_STAT_TCOMP_INT_MASK (0x200U) -#define ADC_STAT_TCOMP_INT_SHIFT (9U) -/*! TCOMP_INT - Interrupt Flag For Trigger Completion - * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. - * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. - */ -#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) - -#define ADC_STAT_CAL_RDY_MASK (0x400U) -#define ADC_STAT_CAL_RDY_SHIFT (10U) -/*! CAL_RDY - Calibration Ready - * 0b0..Calibration is incomplete or hasn't been ran. - * 0b1..The ADC is calibrated. - */ -#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) - -#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) -#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) -/*! ADC_ACTIVE - ADC Active - * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. - * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. - */ -#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) - -#define ADC_STAT_TRGACT_MASK (0xF0000U) -#define ADC_STAT_TRGACT_SHIFT (16U) -/*! TRGACT - Trigger Active - * 0b0000..Command (sequence) associated with Trigger 0 currently being executed. - * 0b0001..Command (sequence) associated with Trigger 1 currently being executed. - * 0b0010..Command (sequence) associated with Trigger 2 currently being executed. - * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed. - */ -#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) - -#define ADC_STAT_CMDACT_MASK (0xF000000U) -#define ADC_STAT_CMDACT_SHIFT (24U) -/*! CMDACT - Command Active - * 0b0000..No command is currently in progress. - * 0b0001..Command 1 currently being executed. - * 0b0010..Command 2 currently being executed. - * 0b0011-0b1111..Associated command number is currently being executed. - */ -#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) -/*! @} */ - -/*! @name IE - Interrupt Enable Register */ -/*! @{ */ - -#define ADC_IE_FWMIE0_MASK (0x1U) -#define ADC_IE_FWMIE0_SHIFT (0U) -/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable - * 0b0..FIFO 0 watermark interrupts are not enabled. - * 0b1..FIFO 0 watermark interrupts are enabled. - */ -#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) - -#define ADC_IE_FOFIE0_MASK (0x2U) -#define ADC_IE_FOFIE0_SHIFT (1U) -/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable - * 0b0..FIFO 0 overflow interrupts are not enabled. - * 0b1..FIFO 0 overflow interrupts are enabled. - */ -#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) - -#define ADC_IE_FWMIE1_MASK (0x4U) -#define ADC_IE_FWMIE1_SHIFT (2U) -/*! FWMIE1 - FIFO1 Watermark Interrupt Enable - * 0b0..FIFO1 watermark interrupts are not enabled. - * 0b1..FIFO1 watermark interrupts are enabled. - */ -#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) - -#define ADC_IE_FOFIE1_MASK (0x8U) -#define ADC_IE_FOFIE1_SHIFT (3U) -/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable - * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) - -#define ADC_IE_TEXC_IE_MASK (0x100U) -#define ADC_IE_TEXC_IE_SHIFT (8U) -/*! TEXC_IE - Trigger Exception Interrupt Enable - * 0b0..Trigger exception interrupts are disabled. - * 0b1..Trigger exception interrupts are enabled. - */ -#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) - -#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U) -#define ADC_IE_TCOMP_IE_SHIFT (16U) -/*! TCOMP_IE - Trigger Completion Interrupt Enable - * 0b0000000000000000..Trigger completion interrupts are disabled. - * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only. - * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only. - * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled. - * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source. - */ -#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) -/*! @} */ - -/*! @name DE - DMA Enable Register */ -/*! @{ */ - -#define ADC_DE_FWMDE0_MASK (0x1U) -#define ADC_DE_FWMDE0_SHIFT (0U) -/*! FWMDE0 - FIFO 0 Watermark DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) - -#define ADC_DE_FWMDE1_MASK (0x2U) -#define ADC_DE_FWMDE1_SHIFT (1U) -/*! FWMDE1 - FIFO1 Watermark DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) -/*! @} */ - -/*! @name CFG - ADC Configuration Register */ -/*! @{ */ - -#define ADC_CFG_TPRICTRL_MASK (0x3U) -#define ADC_CFG_TPRICTRL_SHIFT (0U) -/*! TPRICTRL - ADC trigger priority control - * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted - * and the new command specified by the trigger is started. - * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after - * after completing the current conversion. If averaging is enabled, the averaging loop will be completed. - * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. - * 0b10..If a higher priority trigger is received during command processing, the current command will be - * completed (averaging, looping, compare) before servicing the higher priority trigger. - * 0b11..RESERVED - */ -#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) - -#define ADC_CFG_PWRSEL_MASK (0x30U) -#define ADC_CFG_PWRSEL_SHIFT (4U) -/*! PWRSEL - Power Configuration Select - * 0b00..Lowest power setting. - * 0b01..Higher power setting than 0b0. - * 0b10..Higher power setting than 0b1. - * 0b11..Highest power setting. - */ -#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) - -#define ADC_CFG_REFSEL_MASK (0xC0U) -#define ADC_CFG_REFSEL_SHIFT (6U) -/*! REFSEL - Voltage Reference Selection - * 0b00..(Default) Option 1 setting. - * 0b01..Option 2 setting. - * 0b10..Option 3 setting. - * 0b11..Reserved - */ -#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) - -#define ADC_CFG_TRES_MASK (0x100U) -#define ADC_CFG_TRES_SHIFT (8U) -/*! TRES - Trigger Resume Enable - * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. - * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. - */ -#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) - -#define ADC_CFG_TCMDRES_MASK (0x200U) -#define ADC_CFG_TCMDRES_SHIFT (9U) -/*! TCMDRES - Trigger Command Resume - * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. - * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. - */ -#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) - -#define ADC_CFG_HPT_EXDI_MASK (0x400U) -#define ADC_CFG_HPT_EXDI_SHIFT (10U) -/*! HPT_EXDI - High Priority Trigger Exception Disable - * 0b0..High priority trigger exceptions are enabled. - * 0b1..High priority trigger exceptions are disabled. - */ -#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) - -#define ADC_CFG_PUDLY_MASK (0xFF0000U) -#define ADC_CFG_PUDLY_SHIFT (16U) -/*! PUDLY - Power Up Delay - */ -#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) - -#define ADC_CFG_PWREN_MASK (0x10000000U) -#define ADC_CFG_PWREN_SHIFT (28U) -/*! PWREN - ADC Analog Pre-Enable - * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. - * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost - * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN - * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. - * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be - * executed. - */ -#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) -/*! @} */ - -/*! @name PAUSE - ADC Pause Register */ -/*! @{ */ - -#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) -#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) -/*! PAUSEDLY - Pause Delay - */ -#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) - -#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) -#define ADC_PAUSE_PAUSEEN_SHIFT (31U) -/*! PAUSEEN - PAUSE Option Enable - * 0b0..Pause operation disabled - * 0b1..Pause operation enabled - */ -#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) -/*! @} */ - -/*! @name SWTRIG - Software Trigger Register */ -/*! @{ */ - -#define ADC_SWTRIG_SWT0_MASK (0x1U) -#define ADC_SWTRIG_SWT0_SHIFT (0U) -/*! SWT0 - Software trigger 0 event - * 0b0..No trigger 0 event generated. - * 0b1..Trigger 0 event generated. - */ -#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) - -#define ADC_SWTRIG_SWT1_MASK (0x2U) -#define ADC_SWTRIG_SWT1_SHIFT (1U) -/*! SWT1 - Software trigger 1 event - * 0b0..No trigger 1 event generated. - * 0b1..Trigger 1 event generated. - */ -#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) - -#define ADC_SWTRIG_SWT2_MASK (0x4U) -#define ADC_SWTRIG_SWT2_SHIFT (2U) -/*! SWT2 - Software trigger 2 event - * 0b0..No trigger 2 event generated. - * 0b1..Trigger 2 event generated. - */ -#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) - -#define ADC_SWTRIG_SWT3_MASK (0x8U) -#define ADC_SWTRIG_SWT3_SHIFT (3U) -/*! SWT3 - Software trigger 3 event - * 0b0..No trigger 3 event generated. - * 0b1..Trigger 3 event generated. - */ -#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) - -#define ADC_SWTRIG_SWT4_MASK (0x10U) -#define ADC_SWTRIG_SWT4_SHIFT (4U) -/*! SWT4 - Software trigger 4 event - * 0b0..No trigger 4 event generated. - * 0b1..Trigger 4 event generated. - */ -#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) - -#define ADC_SWTRIG_SWT5_MASK (0x20U) -#define ADC_SWTRIG_SWT5_SHIFT (5U) -/*! SWT5 - Software trigger 5 event - * 0b0..No trigger 5 event generated. - * 0b1..Trigger 5 event generated. - */ -#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) - -#define ADC_SWTRIG_SWT6_MASK (0x40U) -#define ADC_SWTRIG_SWT6_SHIFT (6U) -/*! SWT6 - Software trigger 6 event - * 0b0..No trigger 6 event generated. - * 0b1..Trigger 6 event generated. - */ -#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) - -#define ADC_SWTRIG_SWT7_MASK (0x80U) -#define ADC_SWTRIG_SWT7_SHIFT (7U) -/*! SWT7 - Software trigger 7 event - * 0b0..No trigger 7 event generated. - * 0b1..Trigger 7 event generated. - */ -#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) - -#define ADC_SWTRIG_SWT8_MASK (0x100U) -#define ADC_SWTRIG_SWT8_SHIFT (8U) -/*! SWT8 - Software trigger 8 event - * 0b0..No trigger 8 event generated. - * 0b1..Trigger 8 event generated. - */ -#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK) - -#define ADC_SWTRIG_SWT9_MASK (0x200U) -#define ADC_SWTRIG_SWT9_SHIFT (9U) -/*! SWT9 - Software trigger 9 event - * 0b0..No trigger 9 event generated. - * 0b1..Trigger 9 event generated. - */ -#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK) - -#define ADC_SWTRIG_SWT10_MASK (0x400U) -#define ADC_SWTRIG_SWT10_SHIFT (10U) -/*! SWT10 - Software trigger 10 event - * 0b0..No trigger 10 event generated. - * 0b1..Trigger 10 event generated. - */ -#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK) - -#define ADC_SWTRIG_SWT11_MASK (0x800U) -#define ADC_SWTRIG_SWT11_SHIFT (11U) -/*! SWT11 - Software trigger 11 event - * 0b0..No trigger 11 event generated. - * 0b1..Trigger 11 event generated. - */ -#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK) - -#define ADC_SWTRIG_SWT12_MASK (0x1000U) -#define ADC_SWTRIG_SWT12_SHIFT (12U) -/*! SWT12 - Software trigger 12 event - * 0b0..No trigger 12 event generated. - * 0b1..Trigger 12 event generated. - */ -#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK) - -#define ADC_SWTRIG_SWT13_MASK (0x2000U) -#define ADC_SWTRIG_SWT13_SHIFT (13U) -/*! SWT13 - Software trigger 13 event - * 0b0..No trigger 13 event generated. - * 0b1..Trigger 13 event generated. - */ -#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK) - -#define ADC_SWTRIG_SWT14_MASK (0x4000U) -#define ADC_SWTRIG_SWT14_SHIFT (14U) -/*! SWT14 - Software trigger 14 event - * 0b0..No trigger 14 event generated. - * 0b1..Trigger 14 event generated. - */ -#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK) - -#define ADC_SWTRIG_SWT15_MASK (0x8000U) -#define ADC_SWTRIG_SWT15_SHIFT (15U) -/*! SWT15 - Software trigger 15 event - * 0b0..No trigger 15 event generated. - * 0b1..Trigger 15 event generated. - */ -#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK) -/*! @} */ - -/*! @name TSTAT - Trigger Status Register */ -/*! @{ */ - -#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU) -#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) -/*! TEXC_NUM - Trigger Exception Number - * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. - * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception. - * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception. - * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception. - * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception. - */ -#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) - -#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U) -#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) -/*! TCOMP_FLAG - Trigger Completion Flag - * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled. - * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts. - * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts. - * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts. - * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. - */ -#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) -/*! @} */ - -/*! @name OFSTRIM - ADC Offset Trim Register */ -/*! @{ */ - -#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) -#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) -/*! OFSTRIM_A - Trim for offset - */ -#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) - -#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) -#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) -/*! OFSTRIM_B - Trim for offset - */ -#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) -/*! @} */ - -/*! @name TCTRL - Trigger Control Register */ -/*! @{ */ - -#define ADC_TCTRL_HTEN_MASK (0x1U) -#define ADC_TCTRL_HTEN_SHIFT (0U) -/*! HTEN - Trigger enable - * 0b0..Hardware trigger source disabled - * 0b1..Hardware trigger source enabled - */ -#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) - -#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) -#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) -/*! FIFO_SEL_A - SAR Result Destination For Channel A - * 0b0..Result written to FIFO 0 - * 0b1..Result written to FIFO 1 - */ -#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) - -#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) -#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) -/*! FIFO_SEL_B - SAR Result Destination For Channel B - * 0b0..Result written to FIFO 0 - * 0b1..Result written to FIFO 1 - */ -#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) - -#define ADC_TCTRL_TPRI_MASK (0xF00U) -#define ADC_TCTRL_TPRI_SHIFT (8U) -/*! TPRI - Trigger priority setting - * 0b0000..Set to highest priority, Level 1 - * 0b0001-0b1110..Set to corresponding priority level - * 0b1111..Set to lowest priority, Level 16 - */ -#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) - -#define ADC_TCTRL_RSYNC_MASK (0x8000U) -#define ADC_TCTRL_RSYNC_SHIFT (15U) -/*! RSYNC - Trigger Resync - */ -#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) - -#define ADC_TCTRL_TDLY_MASK (0xF0000U) -#define ADC_TCTRL_TDLY_SHIFT (16U) -/*! TDLY - Trigger delay select - */ -#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) - -#define ADC_TCTRL_TCMD_MASK (0xF000000U) -#define ADC_TCTRL_TCMD_SHIFT (24U) -/*! TCMD - Trigger command select - * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. - * 0b0001..CMD1 is executed - * 0b0010-0b1110..Corresponding CMD is executed - * 0b1111..CMD15 is executed - */ -#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) -/*! @} */ - -/* The count of ADC_TCTRL */ -#define ADC_TCTRL_COUNT (16U) - -/*! @name FCTRL - FIFO Control Register */ -/*! @{ */ - -#define ADC_FCTRL_FCOUNT_MASK (0x1FU) -#define ADC_FCTRL_FCOUNT_SHIFT (0U) -/*! FCOUNT - Result FIFO counter - */ -#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) - -#define ADC_FCTRL_FWMARK_MASK (0xF0000U) -#define ADC_FCTRL_FWMARK_SHIFT (16U) -/*! FWMARK - Watermark level selection - */ -#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) -/*! @} */ - -/* The count of ADC_FCTRL */ -#define ADC_FCTRL_COUNT (2U) - -/*! @name GCC - Gain Calibration Control */ -/*! @{ */ - -#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) -#define ADC_GCC_GAIN_CAL_SHIFT (0U) -/*! GAIN_CAL - Gain Calibration Value - */ -#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) - -#define ADC_GCC_RDY_MASK (0x1000000U) -#define ADC_GCC_RDY_SHIFT (24U) -/*! RDY - Gain Calibration Value Valid - * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. - * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. - */ -#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) -/*! @} */ - -/* The count of ADC_GCC */ -#define ADC_GCC_COUNT (2U) - -/*! @name GCR - Gain Calculation Result */ -/*! @{ */ - -#define ADC_GCR_GCALR_MASK (0xFFFFU) -#define ADC_GCR_GCALR_SHIFT (0U) -/*! GCALR - Gain Calculation Result - */ -#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) - -#define ADC_GCR_RDY_MASK (0x1000000U) -#define ADC_GCR_RDY_SHIFT (24U) -/*! RDY - Gain Calculation Ready - * 0b0..The gain offset calculation value is invalid. - * 0b1..The gain calibration value is valid. - */ -#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) -/*! @} */ - -/* The count of ADC_GCR */ -#define ADC_GCR_COUNT (2U) - -/*! @name CMDL - ADC Command Low Buffer Register */ -/*! @{ */ - -#define ADC_CMDL_ADCH_MASK (0x1FU) -#define ADC_CMDL_ADCH_SHIFT (0U) -/*! ADCH - Input channel select - * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. - * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. - * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. - * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. - * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. - * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. - */ -#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) - -#define ADC_CMDL_CTYPE_MASK (0x60U) -#define ADC_CMDL_CTYPE_SHIFT (5U) -/*! CTYPE - Conversion Type - * 0b00..Single-Ended Mode. Only A side channel is converted. - * 0b01..Single-Ended Mode. Only B side channel is converted. - * 0b10..Differential Mode. A-B. - * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - */ -#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) - -#define ADC_CMDL_MODE_MASK (0x80U) -#define ADC_CMDL_MODE_SHIFT (7U) -/*! MODE - Select resolution of conversions - * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - */ -#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) -/*! @} */ - -/* The count of ADC_CMDL */ -#define ADC_CMDL_COUNT (15U) - -/*! @name CMDH - ADC Command High Buffer Register */ -/*! @{ */ - -#define ADC_CMDH_CMPEN_MASK (0x3U) -#define ADC_CMDH_CMPEN_SHIFT (0U) -/*! CMPEN - Compare Function Enable - * 0b00..Compare disabled. - * 0b01..Reserved - * 0b10..Compare enabled. Store on true. - * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - */ -#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) - -#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) -#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) -/*! WAIT_TRIG - Wait for trigger assertion before execution. - * 0b0..This command will be automatically executed. - * 0b1..The active trigger must be asserted again before executing this command. - */ -#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) - -#define ADC_CMDH_LWI_MASK (0x80U) -#define ADC_CMDH_LWI_SHIFT (7U) -/*! LWI - Loop with Increment - * 0b0..Auto channel increment disabled - * 0b1..Auto channel increment enabled - */ -#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) - -#define ADC_CMDH_STS_MASK (0x700U) -#define ADC_CMDH_STS_SHIFT (8U) -/*! STS - Sample Time Select - * 0b000..Minimum sample time of 3 ADCK cycles. - * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - */ -#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) - -#define ADC_CMDH_AVGS_MASK (0x7000U) -#define ADC_CMDH_AVGS_SHIFT (12U) -/*! AVGS - Hardware Average Select - * 0b000..Single conversion. - * 0b001..2 conversions averaged. - * 0b010..4 conversions averaged. - * 0b011..8 conversions averaged. - * 0b100..16 conversions averaged. - * 0b101..32 conversions averaged. - * 0b110..64 conversions averaged. - * 0b111..128 conversions averaged. - */ -#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) - -#define ADC_CMDH_LOOP_MASK (0xF0000U) -#define ADC_CMDH_LOOP_SHIFT (16U) -/*! LOOP - Loop Count Select - * 0b0000..Looping not enabled. Command executes 1 time. - * 0b0001..Loop 1 time. Command executes 2 times. - * 0b0010..Loop 2 times. Command executes 3 times. - * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. - * 0b1111..Loop 15 times. Command executes 16 times. - */ -#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) - -#define ADC_CMDH_NEXT_MASK (0xF000000U) -#define ADC_CMDH_NEXT_SHIFT (24U) -/*! NEXT - Next Command Select - * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority - * trigger pending, begin command associated with lower priority trigger. - * 0b0001..Select CMD1 command buffer register as next command. - * 0b0010-0b1110..Select corresponding CMD command buffer register as next command - * 0b1111..Select CMD15 command buffer register as next command. - */ -#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) -/*! @} */ - -/* The count of ADC_CMDH */ -#define ADC_CMDH_COUNT (15U) - -/*! @name CV - Compare Value Register */ -/*! @{ */ - -#define ADC_CV_CVL_MASK (0xFFFFU) -#define ADC_CV_CVL_SHIFT (0U) -/*! CVL - Compare Value Low. - */ -#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) - -#define ADC_CV_CVH_MASK (0xFFFF0000U) -#define ADC_CV_CVH_SHIFT (16U) -/*! CVH - Compare Value High. - */ -#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) -/*! @} */ - -/* The count of ADC_CV */ -#define ADC_CV_COUNT (4U) - -/*! @name RESFIFO - ADC Data Result FIFO Register */ -/*! @{ */ - -#define ADC_RESFIFO_D_MASK (0xFFFFU) -#define ADC_RESFIFO_D_SHIFT (0U) -/*! D - Data result - */ -#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) - -#define ADC_RESFIFO_TSRC_MASK (0xF0000U) -#define ADC_RESFIFO_TSRC_SHIFT (16U) -/*! TSRC - Trigger Source - * 0b0000..Trigger source 0 initiated this conversion. - * 0b0001..Trigger source 1 initiated this conversion. - * 0b0010-0b1110..Corresponding trigger source initiated this conversion. - * 0b1111..Trigger source 15 initiated this conversion. - */ -#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) - -#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) -#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) -/*! LOOPCNT - Loop count value - * 0b0000..Result is from initial conversion in command. - * 0b0001..Result is from second conversion in command. - * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. - * 0b1111..Result is from 16th conversion in command. - */ -#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) - -#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) -#define ADC_RESFIFO_CMDSRC_SHIFT (24U) -/*! CMDSRC - Command Buffer Source - * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state - * prior to an ADC conversion result dataword being stored to a RESFIFO buffer. - * 0b0001..CMD1 buffer used as control settings for this conversion. - * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. - * 0b1111..CMD15 buffer used as control settings for this conversion. - */ -#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) - -#define ADC_RESFIFO_VALID_MASK (0x80000000U) -#define ADC_RESFIFO_VALID_SHIFT (31U) -/*! VALID - FIFO entry is valid - * 0b0..FIFO is empty. Discard any read from RESFIFO. - * 0b1..FIFO record read from RESFIFO is valid. - */ -#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) -/*! @} */ - -/* The count of ADC_RESFIFO */ -#define ADC_RESFIFO_COUNT (2U) - -/*! @name CAL_GAR - Calibration General A-Side Registers */ -/*! @{ */ - -#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) -#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) -/*! CAL_GAR_VAL - Calibration General A Side Register Element - */ -#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) -/*! @} */ - -/* The count of ADC_CAL_GAR */ -#define ADC_CAL_GAR_COUNT (33U) - -/*! @name CAL_GBR - Calibration General B-Side Registers */ -/*! @{ */ - -#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) -#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) -/*! CAL_GBR_VAL - Calibration General B Side Register Element - */ -#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) -/*! @} */ - -/* The count of ADC_CAL_GBR */ -#define ADC_CAL_GBR_COUNT (33U) - - -/*! - * @} - */ /* end of group ADC_Register_Masks */ - - -/* ADC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral ADC0 base address */ - #define ADC0_BASE (0x500A0000u) - /** Peripheral ADC0 base address */ - #define ADC0_BASE_NS (0x400A0000u) - /** Peripheral ADC0 base pointer */ - #define ADC0 ((ADC_Type *)ADC0_BASE) - /** Peripheral ADC0 base pointer */ - #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS { ADC0_BASE } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS { ADC0 } - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS_NS { ADC0_NS } -#else - /** Peripheral ADC0 base address */ - #define ADC0_BASE (0x400A0000u) - /** Peripheral ADC0 base pointer */ - #define ADC0 ((ADC_Type *)ADC0_BASE) - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS { ADC0_BASE } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS { ADC0 } -#endif -/** Interrupt vectors for the ADC peripheral type */ -#define ADC_IRQS { ADC0_IRQn } - -/*! - * @} - */ /* end of group ADC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- AHB_SECURE_CTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer - * @{ - */ - -/** AHB_SECURE_CTRL - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x30 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */ - uint8_t RESERVED_0[12]; - __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[1]; /**< Security access rules for FLASH sector 0 to sector 7. Each Flash sector is 32 Kbytes. There are 8 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */ - uint8_t RESERVED_1[12]; - __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */ - } SEC_CTRL_FLASH_ROM[1]; - struct { /* offset: 0x30, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAMX slaves., array offset: 0x40, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_RAMX[1]; - uint8_t RESERVED_0[12]; - struct { /* offset: 0x50, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM0 slaves., array offset: 0x60, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_RAM0[1]; - uint8_t RESERVED_1[12]; - struct { /* offset: 0x70, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM1 slaves., array offset: 0x80, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_RAM1[1]; - uint8_t RESERVED_2[12]; - struct { /* offset: 0x90, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_RAM2[1]; - uint8_t RESERVED_3[12]; - struct { /* offset: 0xB0, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0xB0, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM_USB_HS., array offset: 0xC0, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_USB_HS[1]; - uint8_t RESERVED_4[12]; - struct { /* offset: 0xD0, array step: 0x30 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for both APB Bridges slaves., array offset: 0xD0, array step: 0x30 */ - uint8_t RESERVED_0[12]; - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0xE0, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0xE4, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0xE8, array step: 0x30 */ - uint8_t RESERVED_1[4]; - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xF0, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xF4, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xF8, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xFC, array step: 0x30 */ - } SEC_CTRL_APB_BRIDGE[1]; - __IO uint32_t SEC_CTRL_AHB_PORT7_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x100 */ - __IO uint32_t SEC_CTRL_AHB_PORT7_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x104 */ - uint8_t RESERVED_5[8]; - __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x110 */ - __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x114 */ - uint8_t RESERVED_6[8]; - struct { /* offset: 0x120, array step: 0x14 */ - __IO uint32_t SLAVE0_RULE; /**< Security access rules for AHB peripherals., array offset: 0x120, array step: 0x14 */ - __IO uint32_t SLAVE1_RULE; /**< Security access rules for AHB peripherals., array offset: 0x124, array step: 0x14 */ - uint8_t RESERVED_0[8]; - __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x130, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_AHB_PORT9[1]; - uint8_t RESERVED_7[3276]; - __I uint32_t SEC_VIO_ADDR[10]; /**< most recent security violation address for AHB layer n, array offset: 0xE00, array step: 0x4 */ - uint8_t RESERVED_8[88]; - __I uint32_t SEC_VIO_MISC_INFO[10]; /**< most recent security violation miscellaneous information for AHB layer n, array offset: 0xE80, array step: 0x4 */ - uint8_t RESERVED_9[88]; - __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */ - uint8_t RESERVED_10[124]; - __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */ - __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */ - uint8_t RESERVED_11[52]; - __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */ - uint8_t RESERVED_12[16]; - __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */ - __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */ - uint8_t RESERVED_13[20]; - __IO uint32_t CPU0_LOCK_REG; /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */ - uint8_t RESERVED_14[8]; - __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */ - __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */ -} AHB_SECURE_CTRL_Type; - -/* ---------------------------------------------------------------------------- - -- AHB_SECURE_CTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks - * @{ - */ - -/*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U) -/*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0003_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U) -/*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 7. Each Flash sector is 32 Kbytes. There are 8 FLASH sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U) - -/*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U) -/*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAMX_MEM_RULE - Security access rules for RAMX slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U) -/*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_7FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM0_MEM_RULE - Security access rules for RAM0 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT (0U) -/*! RAM1_RULE - Security access rules for the whole RAM1 : 0x2000_8000 - 0x2000_BFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM1_MEM_RULE - Security access rules for RAM1 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U) -/*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2000_C000 - 0x2000_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM2_MEM_RULE - Security access rules for RAM2 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U) -/*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x2001_0000 - 0x2001_3FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U) -/*! SRAM_SECT_0_RULE - Address space: 0x2001_0000 - 0x2001_0FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U) -/*! SRAM_SECT_1_RULE - Address space: 0x2001_1000 - 0x2001_1FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U) -/*! SRAM_SECT_2_RULE - Address space: 0x2001_2000 - 0x2001_2FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U) -/*! SRAM_SECT_3_RULE - Address space: 0x2001_3000 - 0x2001_3FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U) -/*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U) -/*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U) -/*! SYSCON_RULE - System Configuration - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U) -/*! IOCON_RULE - I/O Configuration - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U) -/*! GINT0_RULE - GPIO input Interrupt 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U) -/*! GINT1_RULE - GPIO input Interrupt 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U) -/*! PINT_RULE - Pin Interrupt and Pattern match - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U) -/*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT (24U) -/*! INPUTMUX_RULE - Peripheral input multiplexing - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U) -/*! CTIMER0_RULE - Standard counter/Timer 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U) -/*! CTIMER1_RULE - Standard counter/Timer 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U) -/*! WWDT_RULE - Windiwed wtachdog Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U) -/*! MRT_RULE - Multi-rate Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U) -/*! UTICK_RULE - Micro-Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U) -/*! ANACTRL_RULE - Analog Modules controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U) -/*! PMC_RULE - Power Management Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U) -/*! SYSCTRL_RULE - System Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_SHIFT (16U) -/*! SPI_FILTER_RULE - SPI FILTER control - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U) -/*! CTIMER2_RULE - Standard counter/Timer 2 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U) -/*! CTIMER3_RULE - Standard counter/Timer 3 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U) -/*! CTIMER4_RULE - Standard counter/Timer 4 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U) -/*! RTC_RULE - Real Time Counter - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U) -/*! OSEVENT_RULE - OS Event Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U) -/*! FLASH_CTRL_RULE - Flash Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U) -/*! PRINCE_RULE - Prince - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U) -/*! USBHPHY_RULE - USB High Speed Phy controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U) -/*! RNG_RULE - True Random Number Generator - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT (12U) -/*! PUF_RULE - PUF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U) -/*! PLU_RULE - Programmable Look-Up logic - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U) - -/*! @name SEC_CTRL_AHB_PORT7_SLAVE0_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_SHIFT (8U) -/*! DMA0_RULE - DMA Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT (16U) -/*! FS_USB_DEV_RULE - USB Full-speed device - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_SHIFT (20U) -/*! SCT_RULE - SCTimer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT (24U) -/*! FLEXCOMM0_RULE - Flexcomm interface 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT (28U) -/*! FLEXCOMM1_RULE - Flexcomm interface 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB_PORT7_SLAVE1_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT (0U) -/*! FLEXCOMM2_RULE - Flexcomm interface 2 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT (4U) -/*! FLEXCOMM3_RULE - Flexcomm interface 3 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT (8U) -/*! FLEXCOMM4_RULE - Flexcomm interface 4 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_SHIFT (16U) -/*! GPIO0_RULE - High Speed GPIO - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT (16U) -/*! USB_HS_DEV_RULE - USB high Speed device registers - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_SHIFT (20U) -/*! CRC_RULE - CRC engine - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT (24U) -/*! FLEXCOMM5_RULE - Flexcomm interface 5 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT (28U) -/*! FLEXCOMM6_RULE - Flexcomm interface 6 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT (0U) -/*! FLEXCOMM7_RULE - Flexcomm interface 7 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT (16U) -/*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_SHIFT (20U) -/*! CAN0_RULE - CAN-FD - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_SHIFT (28U) -/*! HS_LSPI_RULE - High Speed SPI - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_SHIFT (0U) -/*! ADC_RULE - ADC - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT (8U) -/*! USB_FS_HOST_RULE - USB Full Speed Host registers. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT (12U) -/*! USB_HS_HOST_RULE - USB High speed host registers - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_SHIFT (16U) -/*! HASH_RULE - SHA-2 crypto registers - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_SHIFT (20U) -/*! CASPER_RULE - RSA/ECC crypto accelerator - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_SHIFT (28U) -/*! DMA1_RULE - DMA Controller (Secure) - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_COUNT (1U) - -/*! @name SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_SHIFT (0U) -/*! GPIO1_RULE - Secure High Speed GPIO - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U) -/*! AHB_SEC_CTRL_RULE - AHB Secure Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_COUNT (1U) - -/*! @name SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U) -/*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U) -/*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U) -/*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U) -/*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_VIO_ADDR - most recent security violation address for AHB layer n */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) -/*! SEC_VIO_ADDR - security violation address for AHB layer - */ -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */ -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (10U) - -/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB layer n */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) -/*! SEC_VIO_INFO_WRITE - security violation access read/write indicator. - * 0b0..Read access. - * 0b1..Write access. - */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) -/*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator. - * 0b0..Code access. - * 0b1..Data access. - */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) -/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level - */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) -/*! SEC_VIO_INFO_MASTER - security violation master number - * 0b0000..CPU0 Code. - * 0b0001..CPU0 System. - * 0b0100..USB-HS Device. - * 0b0101..SDMA0. - * 0b1010..HASH. - * 0b1011..USB-FS Host. - * 0b1100..SDMA1. - * 0b1101..CAN-FD. - */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (10U) - -/*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) -/*! VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) -/*! VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) -/*! VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) -/*! VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) -/*! VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) -/*! VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) -/*! VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) -/*! VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) -/*! VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) -/*! VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) -/*! @} */ - -/*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U) -/*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U) -/*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U) -/*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U) -/*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U) -/*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U) -/*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U) -/*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U) -/*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U) -/*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U) -/*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U) -/*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U) -/*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U) -/*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U) -/*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U) -/*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U) -/*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U) -/*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U) -/*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U) -/*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U) -/*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U) -/*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U) -/*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U) -/*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U) -/*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U) -/*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U) -/*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U) -/*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U) -/*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U) -/*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U) -/*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U) -/*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U) -/*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK) -/*! @} */ - -/*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U) -/*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U) -/*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U) -/*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U) -/*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U) -/*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U) -/*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U) -/*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U) -/*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U) -/*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U) -/*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U) -/*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U) -/*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U) -/*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U) -/*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U) -/*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U) -/*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U) -/*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U) -/*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U) -/*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U) -/*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U) -/*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U) -/*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U) -/*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U) -/*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U) -/*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U) -/*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U) -/*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U) -/*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U) -/*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U) -/*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U) -/*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U) -/*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK) -/*! @} */ - -/*! @name SEC_MASK_LOCK - Security General Purpose register access control. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) -/*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK) - -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) -/*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK) -/*! @} */ - -/*! @name MASTER_SEC_LEVEL - master secure level register */ -/*! @{ */ - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U) -/*! USBFSD - USB Full Speed Device. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U) -/*! SDMA0 - System DMA 0. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U) -/*! HASH - Hash. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U) -/*! USBFSH - USB Full speed Host. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U) -/*! SDMA1 - System DMA 1 security level. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_MASK (0xC000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_SHIFT (26U) -/*! CANFD - CAN FD. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) -/*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) -/*! @} */ - -/*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */ -/*! @{ */ - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U) -/*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U) -/*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U) -/*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U) -/*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U) -/*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_MASK (0xC000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_SHIFT (26U) -/*! CANFD - CAN FD. Must be equal to NOT(MASTER_SEC_LEVEL.CANFD) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) -/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) -/*! @} */ - -/*! @name CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) */ -/*! @{ */ - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) -/*! LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) -/*! LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) -/*! LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U) -/*! LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U) -/*! LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT (30U) -/*! CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK) -/*! @} */ - -/*! @name MISC_CTRL_DP_REG - secure control duplicate register */ -/*! @{ */ - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) -/*! WRITE_LOCK - Write lock. - * 0b10..Secure control registers can be written. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) -/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. - * 0b10..Disable check. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) -/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. - * 0b10..Disable check. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) -/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. - * 0b10..Disable check. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) -/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. - * 0b10..Enable abort fort secure checker. - * 0b01..Disable abort fort secure checker. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) -/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. - * 0b10..Simple master in strict mode. - * 0b01..Simple master in tier mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) -/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. - * 0b10..Smart master in strict mode. - * 0b01..Smart master in tier mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) -/*! IDAU_ALL_NS - Disable IDAU. - * 0b10..IDAU is enabled. - * 0b01..IDAU is disable. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) -/*! @} */ - -/*! @name MISC_CTRL_REG - secure control register */ -/*! @{ */ - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) -/*! WRITE_LOCK - Write lock. - * 0b10..Secure control registers can be written. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) -/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. - * 0b10..Disable check. - * 0b01..Enabled (restricted mode) - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) -/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. - * 0b10..Disable check. - * 0b01..Enabled (restricted mode) - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) -/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. - * 0b10..Disable check. - * 0b01..Enabled (restricted mode) - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) -/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. - * 0b10..Enable abort fort secure checker. - * 0b01..Disable abort fort secure checker. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) -/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. - * 0b10..Simple master in strict mode. - * 0b01..Simple master in tier mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) -/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. - * 0b10..Smart master in strict mode. - * 0b01..Smart master in tier mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) -/*! IDAU_ALL_NS - Disable IDAU. - * 0b10..IDAU is enabled. - * 0b01..IDAU is disable. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group AHB_SECURE_CTRL_Register_Masks */ - - -/* AHB_SECURE_CTRL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral AHB_SECURE_CTRL base address */ - #define AHB_SECURE_CTRL_BASE (0x500AC000u) - /** Peripheral AHB_SECURE_CTRL base address */ - #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u) - /** Peripheral AHB_SECURE_CTRL base pointer */ - #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) - /** Peripheral AHB_SECURE_CTRL base pointer */ - #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS) - /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ - #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } - /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ - #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } - /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ - #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS } - /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ - #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS } -#else - /** Peripheral AHB_SECURE_CTRL base address */ - #define AHB_SECURE_CTRL_BASE (0x400AC000u) - /** Peripheral AHB_SECURE_CTRL base pointer */ - #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) - /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ - #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } - /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ - #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } -#endif - -/*! - * @} - */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ANACTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer - * @{ - */ - -/** ANACTRL - Register Layout Typedef */ -typedef struct { - __IO uint32_t ANALOG_CTRL_CFG; /**< Various Analog blocks configuration (like FRO 192MHz trimmings source ...), offset: 0x0 */ - __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */ - __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */ - __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */ - __IO uint32_t ADC_CTRL; /**< General Purpose ADC VBAT Divider branch control, offset: 0x18 */ - uint8_t RESERVED_1[4]; - __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */ - __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status register, offset: 0x24 */ - uint8_t RESERVED_2[8]; - __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */ - __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */ - uint8_t RESERVED_3[8]; - __IO uint32_t RINGO0_CTRL; /**< First Ring Oscillator module control register., offset: 0x40 */ - __IO uint32_t RINGO1_CTRL; /**< Second Ring Oscillator module control register., offset: 0x44 */ - __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */ - uint8_t RESERVED_4[100]; - __IO uint32_t LDO_XO32M; /**< High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register, offset: 0xB0 */ - __IO uint32_t AUX_BIAS; /**< AUX_BIAS, offset: 0xB4 */ - uint8_t RESERVED_5[64]; - __IO uint32_t DUMMY_CTRL; /**< Dummy Control bus to analog modules, offset: 0xF8 */ - uint8_t RESERVED_6[4]; - __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */ - __IO uint32_t USBHS_PHY_TRIM; /**< USB High Speed Phy Trim values, offset: 0x104 */ -} ANACTRL_Type; - -/* ---------------------------------------------------------------------------- - -- ANACTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks - * @{ - */ - -/*! @name ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) */ -/*! @{ */ - -#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK (0x1U) -#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT (0U) -/*! FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source. - * 0b0..FRO192M trimming and 'Enable' comes from eFUSE. - * 0b1..FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers. - */ -#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT)) & ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK) -/*! @} */ - -/*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */ -/*! @{ */ - -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U) -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U) -/*! FLASH_PWRDWN - Flash Power Down status. - * 0b0..Flash is not in power down mode. - * 0b1..Flash is in power down mode. - */ -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK) - -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U) -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U) -/*! FLASH_INIT_ERROR - Flash initialization error status. - * 0b0..No error. - * 0b1..At least one error occured during flash initialization.. - */ -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK) -/*! @} */ - -/*! @name FREQ_ME_CTRL - Frequency Measure function control register */ -/*! @{ */ - -#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU) -#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U) -/*! CAPVAL_SCALE - Frequency measure result /Frequency measur scale - */ -#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK) - -#define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U) -#define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U) -/*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit - * when the measurement cycle has completed and there is valid capture data in the CAPVAL field - * (bits 30:0). - */ -#define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK) -/*! @} */ - -/*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */ -/*! @{ */ - -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U) -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U) -/*! ENA_12MHZCLK - 12 MHz clock control. - * 0b0..12 MHz clock is disabled. - * 0b1..12 MHz clock is enabled. - */ -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) - -#define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U) -#define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U) -/*! DAC_TRIM - Frequency trim. - */ -#define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK) - -#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U) -#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U) -/*! USBCLKADJ - If this bit is set and the USB peripheral is enabled into full speed device mode, - * the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF - * packets. - */ -#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK) - -#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U) -#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U) -/*! USBMODCHG - If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0. - */ -#define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK) - -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U) -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U) -/*! ENA_96MHZCLK - 96 MHz clock control. - * 0b0..96 MHz clock is disabled. - * 0b1..96 MHz clock is enabled. - */ -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) - -#define ANACTRL_FRO192M_CTRL_WRTRIM_MASK (0x80000000U) -#define ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT (31U) -/*! WRTRIM - This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields. - */ -#define ANACTRL_FRO192M_CTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_WRTRIM_MASK) -/*! @} */ - -/*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */ -/*! @{ */ - -#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U) -#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U) -/*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. - * 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). - * 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by - * FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). - */ -#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK) - -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U) -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U) -/*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses - * the threshold voltage of a SLVT transistor, this output signal will go high. It is also - * possible to observe the clk_valid signal. - */ -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK) -/*! @} */ - -/*! @name ADC_CTRL - General Purpose ADC VBAT Divider branch control */ -/*! @{ */ - -#define ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK (0x1U) -#define ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT (0U) -/*! VBATDIVENABLE - Switch On/Off VBAT divider branch. - * 0b0..VBAT divider branch is disabled. - * 0b1..VBAT divider branch is enabled. - */ -#define ANACTRL_ADC_CTRL_VBATDIVENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT)) & ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK) -/*! @} */ - -/*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */ -/*! @{ */ - -#define ANACTRL_XO32M_CTRL_SLAVE_MASK (0x10U) -#define ANACTRL_XO32M_CTRL_SLAVE_SHIFT (4U) -/*! SLAVE - Xo in slave mode. - */ -#define ANACTRL_XO32M_CTRL_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_SLAVE_SHIFT)) & ANACTRL_XO32M_CTRL_SLAVE_MASK) - -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK (0x7F00U) -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT (8U) -/*! OSC_CAP_IN - Tune capa banks of High speed Crystal Oscillator input pin - */ -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK) - -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK (0x3F8000U) -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT (15U) -/*! OSC_CAP_OUT - Tune capa banks of High speed Crystal Oscillator output pin - */ -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK) - -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U) -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U) -/*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. - * 0b0..XO AC buffer bypass is disabled. - * 0b1..XO AC buffer bypass is enabled. - */ -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK) - -#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U) -#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U) -/*! ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL. - * 0b0..High speed Crystal oscillator output to USB HS PLL is disabled. - * 0b1..High speed Crystal oscillator output to USB HS PLL is enabled. - */ -#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) - -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U) -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U) -/*! ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system. - * 0b0..High speed Crystal oscillator output to CPU system is disabled. - * 0b1..High speed Crystal oscillator output to CPU system is enabled. - */ -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) -/*! @} */ - -/*! @name XO32M_STATUS - High speed Crystal Oscillator Status register */ -/*! @{ */ - -#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U) -#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U) -/*! XO_READY - Indicates XO out frequency statibilty. - * 0b0..XO output frequency is not yet stable. - * 0b1..XO output frequency is stable. - */ -#define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK) -/*! @} */ - -/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */ -/*! @{ */ - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U) -/*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control. - * 0b0..BOD VBAT interrupt is disabled. - * 0b1..BOD VBAT interrupt is enabled. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U) -/*! BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U) -/*! BODCORE_INT_ENABLE - BOD CORE interrupt control. - * 0b0..BOD CORE interrupt is disabled. - * 0b1..BOD CORE interrupt is enabled. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U) -/*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U) -/*! DCDC_INT_ENABLE - DCDC interrupt control. - * 0b0..DCDC interrupt is disabled. - * 0b1..DCDC interrupt is enabled. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U) -/*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK) -/*! @} */ - -/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */ -/*! @{ */ - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U) -/*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U) -/*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U) -/*! BODVBAT_VAL - Current value of BOD VBAT power status output. - * 0b0..VBAT voltage level is below the threshold. - * 0b1..VBAT voltage level is above the threshold. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U) -/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U) -/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U) -/*! BODCORE_VAL - Current value of BOD CORE power status output. - * 0b0..CORE voltage level is below the threshold. - * 0b1..CORE voltage level is above the threshold. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U) -/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U) -/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U) -/*! DCDC_VAL - Current value of DCDC power status output. - * 0b0..DCDC output Voltage is below the targeted regulation level. - * 0b1..DCDC output Voltage is above the targeted regulation level. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK) -/*! @} */ - -/*! @name RINGO0_CTRL - First Ring Oscillator module control register. */ -/*! @{ */ - -#define ANACTRL_RINGO0_CTRL_SL_MASK (0x1U) -#define ANACTRL_RINGO0_CTRL_SL_SHIFT (0U) -/*! SL - Select short or long ringo (for all ringos types). - * 0b0..Select short ringo (few elements). - * 0b1..Select long ringo (many elements). - */ -#define ANACTRL_RINGO0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK) - -#define ANACTRL_RINGO0_CTRL_FS_MASK (0x2U) -#define ANACTRL_RINGO0_CTRL_FS_SHIFT (1U) -/*! FS - Ringo frequency output divider. - * 0b0..High frequency output (frequency lower than 100 MHz). - * 0b1..Low frequency output (frequency lower than 10 MHz). - */ -#define ANACTRL_RINGO0_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK) - -#define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK (0xCU) -#define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT (2U) -/*! SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control. - * 0b00..Normal mode. - * 0b01..P-Monitor mode. Measure with weak P transistor. - * 0b10..P-Monitor mode. Measure with weak N transistor. - * 0b11..Don't use. - */ -#define ANACTRL_RINGO0_CTRL_SWN_SWP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK) - -#define ANACTRL_RINGO0_CTRL_PD_MASK (0x10U) -#define ANACTRL_RINGO0_CTRL_PD_SHIFT (4U) -/*! PD - Ringo module Power control. - * 0b0..The Ringo module is enabled. - * 0b1..The Ringo module is disabled. - */ -#define ANACTRL_RINGO0_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK) - -#define ANACTRL_RINGO0_CTRL_E_ND0_MASK (0x20U) -#define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT (5U) -/*! E_ND0 - First NAND2-based ringo control. - * 0b0..First NAND2-based ringo is disabled. - * 0b1..First NAND2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_ND0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK) - -#define ANACTRL_RINGO0_CTRL_E_ND1_MASK (0x40U) -#define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT (6U) -/*! E_ND1 - Second NAND2-based ringo control. - * 0b0..Second NAND2-based ringo is disabled. - * 0b1..Second NAND2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_ND1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK) - -#define ANACTRL_RINGO0_CTRL_E_NR0_MASK (0x80U) -#define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT (7U) -/*! E_NR0 - First NOR2-based ringo control. - * 0b0..First NOR2-based ringo is disabled. - * 0b1..First NOR2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_NR0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK) - -#define ANACTRL_RINGO0_CTRL_E_NR1_MASK (0x100U) -#define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT (8U) -/*! E_NR1 - Second NOR2-based ringo control. - * 0b0..Second NORD2-based ringo is disabled. - * 0b1..Second NORD2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_NR1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK) - -#define ANACTRL_RINGO0_CTRL_E_IV0_MASK (0x200U) -#define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT (9U) -/*! E_IV0 - First Inverter-based ringo control. - * 0b0..First INV-based ringo is disabled. - * 0b1..First INV-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_IV0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK) - -#define ANACTRL_RINGO0_CTRL_E_IV1_MASK (0x400U) -#define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT (10U) -/*! E_IV1 - Second Inverter-based ringo control. - * 0b0..Second INV-based ringo is disabled. - * 0b1..Second INV-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_IV1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK) - -#define ANACTRL_RINGO0_CTRL_E_PN0_MASK (0x800U) -#define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT (11U) -/*! E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control. - * 0b0..First PN-based ringo is disabled. - * 0b1..First PN-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_PN0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK) - -#define ANACTRL_RINGO0_CTRL_E_PN1_MASK (0x1000U) -#define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT (12U) -/*! E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control. - * 0b0..Second PN-based ringo is disabled. - * 0b1..Second PN-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_PN1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK) - -#define ANACTRL_RINGO0_CTRL_DIVISOR_MASK (0xF0000U) -#define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT (16U) -/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) - */ -#define ANACTRL_RINGO0_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK) - -#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) -#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT (31U) -/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider - * value, cleared when the change is complete. - */ -#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK) -/*! @} */ - -/*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */ -/*! @{ */ - -#define ANACTRL_RINGO1_CTRL_S_MASK (0x1U) -#define ANACTRL_RINGO1_CTRL_S_SHIFT (0U) -/*! S - Select short or long ringo (for all ringos types). - * 0b0..Select short ringo (few elements). - * 0b1..Select long ringo (many elements). - */ -#define ANACTRL_RINGO1_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK) - -#define ANACTRL_RINGO1_CTRL_FS_MASK (0x2U) -#define ANACTRL_RINGO1_CTRL_FS_SHIFT (1U) -/*! FS - Ringo frequency output divider. - * 0b0..High frequency output (frequency lower than 100 MHz). - * 0b1..Low frequency output (frequency lower than 10 MHz). - */ -#define ANACTRL_RINGO1_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK) - -#define ANACTRL_RINGO1_CTRL_PD_MASK (0x4U) -#define ANACTRL_RINGO1_CTRL_PD_SHIFT (2U) -/*! PD - Ringo module Power control. - * 0b0..The Ringo module is enabled. - * 0b1..The Ringo module is disabled. - */ -#define ANACTRL_RINGO1_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK) - -#define ANACTRL_RINGO1_CTRL_E_R24_MASK (0x8U) -#define ANACTRL_RINGO1_CTRL_E_R24_SHIFT (3U) -/*! E_R24 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK) - -#define ANACTRL_RINGO1_CTRL_E_R35_MASK (0x10U) -#define ANACTRL_RINGO1_CTRL_E_R35_SHIFT (4U) -/*! E_R35 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK) - -#define ANACTRL_RINGO1_CTRL_E_M2_MASK (0x20U) -#define ANACTRL_RINGO1_CTRL_E_M2_SHIFT (5U) -/*! E_M2 - Metal 2 (M2) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK) - -#define ANACTRL_RINGO1_CTRL_E_M3_MASK (0x40U) -#define ANACTRL_RINGO1_CTRL_E_M3_SHIFT (6U) -/*! E_M3 - Metal 3 (M3) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK) - -#define ANACTRL_RINGO1_CTRL_E_M4_MASK (0x80U) -#define ANACTRL_RINGO1_CTRL_E_M4_SHIFT (7U) -/*! E_M4 - Metal 4 (M4) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK) - -#define ANACTRL_RINGO1_CTRL_E_M5_MASK (0x100U) -#define ANACTRL_RINGO1_CTRL_E_M5_SHIFT (8U) -/*! E_M5 - Metal 5 (M5) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK) - -#define ANACTRL_RINGO1_CTRL_DIVISOR_MASK (0xF0000U) -#define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT (16U) -/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) - */ -#define ANACTRL_RINGO1_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK) - -#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) -#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT (31U) -/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider - * value, cleared when the change is complete. - */ -#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK) -/*! @} */ - -/*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */ -/*! @{ */ - -#define ANACTRL_RINGO2_CTRL_S_MASK (0x1U) -#define ANACTRL_RINGO2_CTRL_S_SHIFT (0U) -/*! S - Select short or long ringo (for all ringos types). - * 0b0..Select short ringo (few elements). - * 0b1..Select long ringo (many elements). - */ -#define ANACTRL_RINGO2_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK) - -#define ANACTRL_RINGO2_CTRL_FS_MASK (0x2U) -#define ANACTRL_RINGO2_CTRL_FS_SHIFT (1U) -/*! FS - Ringo frequency output divider. - * 0b0..High frequency output (frequency lower than 100 MHz). - * 0b1..Low frequency output (frequency lower than 10 MHz). - */ -#define ANACTRL_RINGO2_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK) - -#define ANACTRL_RINGO2_CTRL_PD_MASK (0x4U) -#define ANACTRL_RINGO2_CTRL_PD_SHIFT (2U) -/*! PD - Ringo module Power control. - * 0b0..The Ringo module is enabled. - * 0b1..The Ringo module is disabled. - */ -#define ANACTRL_RINGO2_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK) - -#define ANACTRL_RINGO2_CTRL_E_R24_MASK (0x8U) -#define ANACTRL_RINGO2_CTRL_E_R24_SHIFT (3U) -/*! E_R24 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK) - -#define ANACTRL_RINGO2_CTRL_E_R35_MASK (0x10U) -#define ANACTRL_RINGO2_CTRL_E_R35_SHIFT (4U) -/*! E_R35 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK) - -#define ANACTRL_RINGO2_CTRL_E_M2_MASK (0x20U) -#define ANACTRL_RINGO2_CTRL_E_M2_SHIFT (5U) -/*! E_M2 - Metal 2 (M2) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK) - -#define ANACTRL_RINGO2_CTRL_E_M3_MASK (0x40U) -#define ANACTRL_RINGO2_CTRL_E_M3_SHIFT (6U) -/*! E_M3 - Metal 3 (M3) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK) - -#define ANACTRL_RINGO2_CTRL_E_M4_MASK (0x80U) -#define ANACTRL_RINGO2_CTRL_E_M4_SHIFT (7U) -/*! E_M4 - Metal 4 (M4) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK) - -#define ANACTRL_RINGO2_CTRL_E_M5_MASK (0x100U) -#define ANACTRL_RINGO2_CTRL_E_M5_SHIFT (8U) -/*! E_M5 - Metal 5 (M5) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK) - -#define ANACTRL_RINGO2_CTRL_DIVISOR_MASK (0xF0000U) -#define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT (16U) -/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) - */ -#define ANACTRL_RINGO2_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK) - -#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) -#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT (31U) -/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider - * value, cleared when the change is complete. - */ -#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK) -/*! @} */ - -/*! @name LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register */ -/*! @{ */ - -#define ANACTRL_LDO_XO32M_BYPASS_MASK (0x2U) -#define ANACTRL_LDO_XO32M_BYPASS_SHIFT (1U) -/*! BYPASS - Activate LDO bypass. - * 0b0..Disable bypass mode (for normal operations). - * 0b1..Activate LDO bypass. - */ -#define ANACTRL_LDO_XO32M_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_BYPASS_SHIFT)) & ANACTRL_LDO_XO32M_BYPASS_MASK) - -#define ANACTRL_LDO_XO32M_HIGHZ_MASK (0x4U) -#define ANACTRL_LDO_XO32M_HIGHZ_SHIFT (2U) -/*! HIGHZ - . - * 0b0..Output in High normal state. - * 0b1..Output in High Impedance state. - */ -#define ANACTRL_LDO_XO32M_HIGHZ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_HIGHZ_SHIFT)) & ANACTRL_LDO_XO32M_HIGHZ_MASK) - -#define ANACTRL_LDO_XO32M_VOUT_MASK (0x38U) -#define ANACTRL_LDO_XO32M_VOUT_SHIFT (3U) -/*! VOUT - Sets the LDO output level. - * 0b000..0.750 V. - * 0b001..0.775 V. - * 0b010..0.800 V. - * 0b011..0.825 V. - * 0b100..0.850 V. - * 0b101..0.875 V. - * 0b110..0.900 V. - * 0b111..0.925 V. - */ -#define ANACTRL_LDO_XO32M_VOUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_VOUT_SHIFT)) & ANACTRL_LDO_XO32M_VOUT_MASK) - -#define ANACTRL_LDO_XO32M_IBIAS_MASK (0xC0U) -#define ANACTRL_LDO_XO32M_IBIAS_SHIFT (6U) -/*! IBIAS - Adjust the biasing current. - */ -#define ANACTRL_LDO_XO32M_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_IBIAS_SHIFT)) & ANACTRL_LDO_XO32M_IBIAS_MASK) - -#define ANACTRL_LDO_XO32M_STABMODE_MASK (0x300U) -#define ANACTRL_LDO_XO32M_STABMODE_SHIFT (8U) -/*! STABMODE - Stability configuration. - */ -#define ANACTRL_LDO_XO32M_STABMODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_STABMODE_SHIFT)) & ANACTRL_LDO_XO32M_STABMODE_MASK) -/*! @} */ - -/*! @name AUX_BIAS - AUX_BIAS */ -/*! @{ */ - -#define ANACTRL_AUX_BIAS_VREF1VENABLE_MASK (0x2U) -#define ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT (1U) -/*! VREF1VENABLE - Control output of 1V reference voltage. - * 0b0..Output of 1V reference voltage buffer is bypassed. - * 0b1..Output of 1V reference voltage is enabled. - */ -#define ANACTRL_AUX_BIAS_VREF1VENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VENABLE_MASK) - -#define ANACTRL_AUX_BIAS_ITRIM_MASK (0x7CU) -#define ANACTRL_AUX_BIAS_ITRIM_SHIFT (2U) -/*! ITRIM - current trimming control word. - */ -#define ANACTRL_AUX_BIAS_ITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIM_SHIFT)) & ANACTRL_AUX_BIAS_ITRIM_MASK) - -#define ANACTRL_AUX_BIAS_PTATITRIM_MASK (0xF80U) -#define ANACTRL_AUX_BIAS_PTATITRIM_SHIFT (7U) -/*! PTATITRIM - current trimming control word for ptat current. - */ -#define ANACTRL_AUX_BIAS_PTATITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_PTATITRIM_SHIFT)) & ANACTRL_AUX_BIAS_PTATITRIM_MASK) - -#define ANACTRL_AUX_BIAS_VREF1VTRIM_MASK (0x1F000U) -#define ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT (12U) -/*! VREF1VTRIM - voltage trimming control word. - */ -#define ANACTRL_AUX_BIAS_VREF1VTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VTRIM_MASK) - -#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK (0xE0000U) -#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT (17U) -/*! VREF1VCURVETRIM - Control bit to configure trimming state of mirror. - */ -#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK) - -#define ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK (0x100000U) -#define ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT (20U) -/*! ITRIMCTRL0 - Control bit to configure trimming state of mirror. - */ -#define ANACTRL_AUX_BIAS_ITRIMCTRL0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK) - -#define ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK (0x200000U) -#define ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT (21U) -/*! ITRIMCTRL1 - Control bit to configure trimming state of mirror. - */ -#define ANACTRL_AUX_BIAS_ITRIMCTRL1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK) -/*! @} */ - -/*! @name DUMMY_CTRL - Dummy Control bus to analog modules */ -/*! @{ */ - -#define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK (0xC00U) -#define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_SHIFT (10U) -/*! XO32M_ADC_CLK_MODE - Control High speed Crystal oscillator mode of the ADC clock. - * 0b00..High speed Crystal oscillator output to ADC is disabled. - * 0b01..High speed Crystal oscillator output to ADC is enable. - */ -#define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_SHIFT)) & ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK) -/*! @} */ - -/*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */ -/*! @{ */ - -#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK (0x1U) -#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT (0U) -/*! usb_vbusvalid_ext - Override value for Vbus if using external detectors. - */ -#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK) - -#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK (0x2U) -#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT (1U) -/*! usb_id_ext - Override value for ID if using external detectors. - */ -#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK) - -#define ANACTRL_USBHS_PHY_CTRL_iso_atx_MASK (0x8U) -#define ANACTRL_USBHS_PHY_CTRL_iso_atx_SHIFT (3U) -/*! iso_atx - . - */ -#define ANACTRL_USBHS_PHY_CTRL_iso_atx(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_iso_atx_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_iso_atx_MASK) -/*! @} */ - -/*! @name USBHS_PHY_TRIM - USB High Speed Phy Trim values */ -/*! @{ */ - -#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK (0x3U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT (0U) -/*! trim_usb_reg_env_tail_adj_vd - Adjusts time constant of HS RX squelch (envelope) comparator. - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK (0x3CU) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT (2U) -/*! trim_usbphy_tx_d_cal - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK (0x7C0U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT (6U) -/*! trim_usbphy_tx_cal45dp - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK (0xF800U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT (11U) -/*! trim_usbphy_tx_cal45dm - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK (0x30000U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT (16U) -/*! trim_usb2_refbias_tst - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK (0x1C0000U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT (18U) -/*! trim_usb2_refbias_vbgadj - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK (0xE00000U) -#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT (21U) -/*! trim_pll_ctrl0_div_sel - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ANACTRL_Register_Masks */ - - -/* ANACTRL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE (0x50013000u) - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE_NS (0x40013000u) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS) - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS { ANACTRL } - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS } -#else - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE (0x40013000u) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS { ANACTRL } -#endif - -/*! - * @} - */ /* end of group ANACTRL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CAN Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer - * @{ - */ - -/** CAN - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[12]; - __IO uint32_t DBTP; /**< Data Bit Timing Prescaler Register, offset: 0xC */ - __IO uint32_t TEST; /**< Test Register, offset: 0x10 */ - uint8_t RESERVED_1[4]; - __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */ - __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */ - __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */ - __I uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */ - __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */ - __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */ - uint8_t RESERVED_2[16]; - __I uint32_t ECR; /**< Error Counter Register, offset: 0x40 */ - __I uint32_t PSR; /**< Protocol Status Register, offset: 0x44 */ - __IO uint32_t TDCR; /**< Transmitter Delay Compensator Register, offset: 0x48 */ - uint8_t RESERVED_3[4]; - __IO uint32_t IR; /**< Interrupt Register, offset: 0x50 */ - __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */ - __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */ - __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */ - uint8_t RESERVED_4[32]; - __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */ - __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */ - __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */ - uint8_t RESERVED_5[4]; - __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */ - __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */ - __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */ - __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */ - __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */ - __I uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */ - __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */ - __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */ - __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */ - __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */ - __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */ - __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */ - __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */ - __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */ - __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */ - __I uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */ - __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */ - __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */ - __I uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */ - __I uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */ - __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */ - __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */ - uint8_t RESERVED_6[8]; - __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */ - __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */ - __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */ - uint8_t RESERVED_7[260]; - __IO uint32_t MRBA; /**< CAN Message RAM Base Address, offset: 0x200 */ - uint8_t RESERVED_8[508]; - __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */ - uint8_t RESERVED_9[508]; - __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */ -} CAN_Type; - -/* ---------------------------------------------------------------------------- - -- CAN Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CAN_Register_Masks CAN Register Masks - * @{ - */ - -/*! @name DBTP - Data Bit Timing Prescaler Register */ -/*! @{ */ - -#define CAN_DBTP_DSJW_MASK (0xFU) -#define CAN_DBTP_DSJW_SHIFT (0U) -/*! DSJW - Data (re)synchronization jump width. - */ -#define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK) - -#define CAN_DBTP_DTSEG2_MASK (0xF0U) -#define CAN_DBTP_DTSEG2_SHIFT (4U) -/*! DTSEG2 - Data time segment after sample point. - */ -#define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK) - -#define CAN_DBTP_DTSEG1_MASK (0x1F00U) -#define CAN_DBTP_DTSEG1_SHIFT (8U) -/*! DTSEG1 - Data time segment before sample point. - */ -#define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK) - -#define CAN_DBTP_DBRP_MASK (0x1F0000U) -#define CAN_DBTP_DBRP_SHIFT (16U) -/*! DBRP - Data bit rate prescaler. - */ -#define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK) - -#define CAN_DBTP_TDC_MASK (0x800000U) -#define CAN_DBTP_TDC_SHIFT (23U) -/*! TDC - Transmitter delay compensation. - */ -#define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK) -/*! @} */ - -/*! @name TEST - Test Register */ -/*! @{ */ - -#define CAN_TEST_LBCK_MASK (0x10U) -#define CAN_TEST_LBCK_SHIFT (4U) -/*! LBCK - Loop back mode. - */ -#define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK) - -#define CAN_TEST_TX_MASK (0x60U) -#define CAN_TEST_TX_SHIFT (5U) -/*! TX - Control of transmit pin. - */ -#define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK) - -#define CAN_TEST_RX_MASK (0x80U) -#define CAN_TEST_RX_SHIFT (7U) -/*! RX - Monitors the actual value of the CAN_RXD. - */ -#define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK) -/*! @} */ - -/*! @name CCCR - CC Control Register */ -/*! @{ */ - -#define CAN_CCCR_INIT_MASK (0x1U) -#define CAN_CCCR_INIT_SHIFT (0U) -/*! INIT - Initialization. - */ -#define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK) - -#define CAN_CCCR_CCE_MASK (0x2U) -#define CAN_CCCR_CCE_SHIFT (1U) -/*! CCE - Configuration change enable. - */ -#define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK) - -#define CAN_CCCR_ASM_MASK (0x4U) -#define CAN_CCCR_ASM_SHIFT (2U) -/*! ASM - Restricted operational mode. - */ -#define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK) - -#define CAN_CCCR_CSA_MASK (0x8U) -#define CAN_CCCR_CSA_SHIFT (3U) -/*! CSA - Clock Stop Acknowledge. - */ -#define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK) - -#define CAN_CCCR_CSR_MASK (0x10U) -#define CAN_CCCR_CSR_SHIFT (4U) -/*! CSR - Clock Stop Request. - */ -#define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK) - -#define CAN_CCCR_MON_MASK (0x20U) -#define CAN_CCCR_MON_SHIFT (5U) -/*! MON - Bus monitoring mode. - */ -#define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK) - -#define CAN_CCCR_DAR_MASK (0x40U) -#define CAN_CCCR_DAR_SHIFT (6U) -/*! DAR - Disable automatic retransmission. - */ -#define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK) - -#define CAN_CCCR_TEST_MASK (0x80U) -#define CAN_CCCR_TEST_SHIFT (7U) -/*! TEST - Test mode enable. - */ -#define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK) - -#define CAN_CCCR_FDOE_MASK (0x100U) -#define CAN_CCCR_FDOE_SHIFT (8U) -/*! FDOE - CAN FD operation enable. - */ -#define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK) - -#define CAN_CCCR_BRSE_MASK (0x200U) -#define CAN_CCCR_BRSE_SHIFT (9U) -/*! BRSE - When CAN FD operation is disabled, this bit is not evaluated. - */ -#define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK) - -#define CAN_CCCR_PXHD_MASK (0x1000U) -#define CAN_CCCR_PXHD_SHIFT (12U) -/*! PXHD - Protocol exception handling disable. - */ -#define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK) - -#define CAN_CCCR_EFBI_MASK (0x2000U) -#define CAN_CCCR_EFBI_SHIFT (13U) -/*! EFBI - Edge filtering during bus integration. - */ -#define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK) - -#define CAN_CCCR_TXP_MASK (0x4000U) -#define CAN_CCCR_TXP_SHIFT (14U) -/*! TXP - Transmit pause. - */ -#define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK) - -#define CAN_CCCR_NISO_MASK (0x8000U) -#define CAN_CCCR_NISO_SHIFT (15U) -/*! NISO - Non ISO operation. - */ -#define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK) -/*! @} */ - -/*! @name NBTP - Nominal Bit Timing and Prescaler Register */ -/*! @{ */ - -#define CAN_NBTP_NTSEG2_MASK (0x7FU) -#define CAN_NBTP_NTSEG2_SHIFT (0U) -/*! NTSEG2 - Nominal time segment after sample point. - */ -#define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK) - -#define CAN_NBTP_NTSEG1_MASK (0xFF00U) -#define CAN_NBTP_NTSEG1_SHIFT (8U) -/*! NTSEG1 - Nominal time segment before sample point. - */ -#define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK) - -#define CAN_NBTP_NBRP_MASK (0x1FF0000U) -#define CAN_NBTP_NBRP_SHIFT (16U) -/*! NBRP - Nominal bit rate prescaler. - */ -#define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK) - -#define CAN_NBTP_NSJW_MASK (0xFE000000U) -#define CAN_NBTP_NSJW_SHIFT (25U) -/*! NSJW - Nominal (re)synchronization jump width. - */ -#define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK) -/*! @} */ - -/*! @name TSCC - Timestamp Counter Configuration */ -/*! @{ */ - -#define CAN_TSCC_TSS_MASK (0x3U) -#define CAN_TSCC_TSS_SHIFT (0U) -/*! TSS - Timestamp select. - */ -#define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK) - -#define CAN_TSCC_TCP_MASK (0xF0000U) -#define CAN_TSCC_TCP_SHIFT (16U) -/*! TCP - Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times. - */ -#define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK) -/*! @} */ - -/*! @name TSCV - Timestamp Counter Value */ -/*! @{ */ - -#define CAN_TSCV_TSC_MASK (0xFFFFU) -#define CAN_TSCV_TSC_SHIFT (0U) -/*! TSC - Timestamp counter. - */ -#define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK) -/*! @} */ - -/*! @name TOCC - Timeout Counter Configuration */ -/*! @{ */ - -#define CAN_TOCC_ETOC_MASK (0x1U) -#define CAN_TOCC_ETOC_SHIFT (0U) -/*! ETOC - Enable timeout counter. - */ -#define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK) - -#define CAN_TOCC_TOS_MASK (0x6U) -#define CAN_TOCC_TOS_SHIFT (1U) -/*! TOS - Timeout select. - */ -#define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK) - -#define CAN_TOCC_TOP_MASK (0xFFFF0000U) -#define CAN_TOCC_TOP_SHIFT (16U) -/*! TOP - Timeout period. - */ -#define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK) -/*! @} */ - -/*! @name TOCV - Timeout Counter Value */ -/*! @{ */ - -#define CAN_TOCV_TOC_MASK (0xFFFFU) -#define CAN_TOCV_TOC_SHIFT (0U) -/*! TOC - Timeout counter. - */ -#define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK) -/*! @} */ - -/*! @name ECR - Error Counter Register */ -/*! @{ */ - -#define CAN_ECR_TEC_MASK (0xFFU) -#define CAN_ECR_TEC_SHIFT (0U) -/*! TEC - Transmit error counter. - */ -#define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK) - -#define CAN_ECR_REC_MASK (0x7F00U) -#define CAN_ECR_REC_SHIFT (8U) -/*! REC - Receive error counter. - */ -#define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK) - -#define CAN_ECR_RP_MASK (0x8000U) -#define CAN_ECR_RP_SHIFT (15U) -/*! RP - Receive error passive. - */ -#define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK) - -#define CAN_ECR_CEL_MASK (0xFF0000U) -#define CAN_ECR_CEL_SHIFT (16U) -/*! CEL - CAN error logging. - */ -#define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK) -/*! @} */ - -/*! @name PSR - Protocol Status Register */ -/*! @{ */ - -#define CAN_PSR_LEC_MASK (0x7U) -#define CAN_PSR_LEC_SHIFT (0U) -/*! LEC - Last error code. - */ -#define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK) - -#define CAN_PSR_ACT_MASK (0x18U) -#define CAN_PSR_ACT_SHIFT (3U) -/*! ACT - Activity. - */ -#define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK) - -#define CAN_PSR_EP_MASK (0x20U) -#define CAN_PSR_EP_SHIFT (5U) -/*! EP - Error Passive. - */ -#define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK) - -#define CAN_PSR_EW_MASK (0x40U) -#define CAN_PSR_EW_SHIFT (6U) -/*! EW - Warning status. - */ -#define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK) - -#define CAN_PSR_BO_MASK (0x80U) -#define CAN_PSR_BO_SHIFT (7U) -/*! BO - Bus Off Status. - */ -#define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK) - -#define CAN_PSR_DLEC_MASK (0x700U) -#define CAN_PSR_DLEC_SHIFT (8U) -/*! DLEC - Data phase last error code. - */ -#define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK) - -#define CAN_PSR_RESI_MASK (0x800U) -#define CAN_PSR_RESI_SHIFT (11U) -/*! RESI - ESI flag of the last received CAN FD message. - */ -#define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK) - -#define CAN_PSR_RBRS_MASK (0x1000U) -#define CAN_PSR_RBRS_SHIFT (12U) -/*! RBRS - BRS flag of last received CAN FD message. - */ -#define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK) - -#define CAN_PSR_RFDF_MASK (0x2000U) -#define CAN_PSR_RFDF_SHIFT (13U) -/*! RFDF - Received a CAN FD message. - */ -#define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK) - -#define CAN_PSR_PXE_MASK (0x4000U) -#define CAN_PSR_PXE_SHIFT (14U) -/*! PXE - Protocol exception event. - */ -#define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK) - -#define CAN_PSR_TDCV_MASK (0x7F0000U) -#define CAN_PSR_TDCV_SHIFT (16U) -/*! TDCV - Transmitter delay compensation value. - */ -#define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK) -/*! @} */ - -/*! @name TDCR - Transmitter Delay Compensator Register */ -/*! @{ */ - -#define CAN_TDCR_TDCF_MASK (0x7FU) -#define CAN_TDCR_TDCF_SHIFT (0U) -/*! TDCF - Transmitter delay compensation filter window length. - */ -#define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK) - -#define CAN_TDCR_TDCO_MASK (0x7F00U) -#define CAN_TDCR_TDCO_SHIFT (8U) -/*! TDCO - Transmitter delay compensation offset. - */ -#define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK) -/*! @} */ - -/*! @name IR - Interrupt Register */ -/*! @{ */ - -#define CAN_IR_RF0N_MASK (0x1U) -#define CAN_IR_RF0N_SHIFT (0U) -/*! RF0N - Rx FIFO 0 new message. - */ -#define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK) - -#define CAN_IR_RF0W_MASK (0x2U) -#define CAN_IR_RF0W_SHIFT (1U) -/*! RF0W - Rx FIFO 0 watermark reached. - */ -#define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK) - -#define CAN_IR_RF0F_MASK (0x4U) -#define CAN_IR_RF0F_SHIFT (2U) -/*! RF0F - Rx FIFO 0 full. - */ -#define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK) - -#define CAN_IR_RF0L_MASK (0x8U) -#define CAN_IR_RF0L_SHIFT (3U) -/*! RF0L - Rx FIFO 0 message lost. - */ -#define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK) - -#define CAN_IR_RF1N_MASK (0x10U) -#define CAN_IR_RF1N_SHIFT (4U) -/*! RF1N - Rx FIFO 1 new message. - */ -#define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK) - -#define CAN_IR_RF1W_MASK (0x20U) -#define CAN_IR_RF1W_SHIFT (5U) -/*! RF1W - Rx FIFO 1 watermark reached. - */ -#define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK) - -#define CAN_IR_RF1F_MASK (0x40U) -#define CAN_IR_RF1F_SHIFT (6U) -/*! RF1F - Rx FIFO 1 full. - */ -#define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK) - -#define CAN_IR_RF1L_MASK (0x80U) -#define CAN_IR_RF1L_SHIFT (7U) -/*! RF1L - Rx FIFO 1 message lost. - */ -#define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK) - -#define CAN_IR_HPM_MASK (0x100U) -#define CAN_IR_HPM_SHIFT (8U) -/*! HPM - High priority message. - */ -#define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK) - -#define CAN_IR_TC_MASK (0x200U) -#define CAN_IR_TC_SHIFT (9U) -/*! TC - Transmission completed. - */ -#define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK) - -#define CAN_IR_TCF_MASK (0x400U) -#define CAN_IR_TCF_SHIFT (10U) -/*! TCF - Transmission cancellation finished. - */ -#define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK) - -#define CAN_IR_TFE_MASK (0x800U) -#define CAN_IR_TFE_SHIFT (11U) -/*! TFE - Tx FIFO empty. - */ -#define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK) - -#define CAN_IR_TEFN_MASK (0x1000U) -#define CAN_IR_TEFN_SHIFT (12U) -/*! TEFN - Tx event FIFO new entry. - */ -#define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK) - -#define CAN_IR_TEFW_MASK (0x2000U) -#define CAN_IR_TEFW_SHIFT (13U) -/*! TEFW - Tx event FIFO watermark reached. - */ -#define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK) - -#define CAN_IR_TEFF_MASK (0x4000U) -#define CAN_IR_TEFF_SHIFT (14U) -/*! TEFF - Tx event FIFO full. - */ -#define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK) - -#define CAN_IR_TEFL_MASK (0x8000U) -#define CAN_IR_TEFL_SHIFT (15U) -/*! TEFL - Tx event FIFO element lost. - */ -#define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK) - -#define CAN_IR_TSW_MASK (0x10000U) -#define CAN_IR_TSW_SHIFT (16U) -/*! TSW - Timestamp wraparound. - */ -#define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK) - -#define CAN_IR_MRAF_MASK (0x20000U) -#define CAN_IR_MRAF_SHIFT (17U) -/*! MRAF - Message RAM access failure. - */ -#define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK) - -#define CAN_IR_TOO_MASK (0x40000U) -#define CAN_IR_TOO_SHIFT (18U) -/*! TOO - Timeout occurred. - */ -#define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK) - -#define CAN_IR_DRX_MASK (0x80000U) -#define CAN_IR_DRX_SHIFT (19U) -/*! DRX - Message stored in dedicated Rx buffer. - */ -#define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK) - -#define CAN_IR_BEC_MASK (0x100000U) -#define CAN_IR_BEC_SHIFT (20U) -/*! BEC - Bit error corrected. - */ -#define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK) - -#define CAN_IR_BEU_MASK (0x200000U) -#define CAN_IR_BEU_SHIFT (21U) -/*! BEU - Bit error uncorrected. - */ -#define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK) - -#define CAN_IR_ELO_MASK (0x400000U) -#define CAN_IR_ELO_SHIFT (22U) -/*! ELO - Error logging overflow. - */ -#define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK) - -#define CAN_IR_EP_MASK (0x800000U) -#define CAN_IR_EP_SHIFT (23U) -/*! EP - Error passive. - */ -#define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK) - -#define CAN_IR_EW_MASK (0x1000000U) -#define CAN_IR_EW_SHIFT (24U) -/*! EW - Warning status. - */ -#define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK) - -#define CAN_IR_BO_MASK (0x2000000U) -#define CAN_IR_BO_SHIFT (25U) -/*! BO - Bus_Off Status. - */ -#define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK) - -#define CAN_IR_WDI_MASK (0x4000000U) -#define CAN_IR_WDI_SHIFT (26U) -/*! WDI - Watchdog interrupt. - */ -#define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK) - -#define CAN_IR_PEA_MASK (0x8000000U) -#define CAN_IR_PEA_SHIFT (27U) -/*! PEA - Protocol error in arbitration phase. - */ -#define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK) - -#define CAN_IR_PED_MASK (0x10000000U) -#define CAN_IR_PED_SHIFT (28U) -/*! PED - Protocol error in data phase. - */ -#define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK) - -#define CAN_IR_ARA_MASK (0x20000000U) -#define CAN_IR_ARA_SHIFT (29U) -/*! ARA - Access to reserved address. - */ -#define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK) -/*! @} */ - -/*! @name IE - Interrupt Enable */ -/*! @{ */ - -#define CAN_IE_RF0NE_MASK (0x1U) -#define CAN_IE_RF0NE_SHIFT (0U) -/*! RF0NE - Rx FIFO 0 new message interrupt enable. - */ -#define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK) - -#define CAN_IE_RF0WE_MASK (0x2U) -#define CAN_IE_RF0WE_SHIFT (1U) -/*! RF0WE - Rx FIFO 0 watermark reached interrupt enable. - */ -#define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK) - -#define CAN_IE_RF0FE_MASK (0x4U) -#define CAN_IE_RF0FE_SHIFT (2U) -/*! RF0FE - Rx FIFO 0 full interrupt enable. - */ -#define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK) - -#define CAN_IE_RF0LE_MASK (0x8U) -#define CAN_IE_RF0LE_SHIFT (3U) -/*! RF0LE - Rx FIFO 0 message lost interrupt enable. - */ -#define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK) - -#define CAN_IE_RF1NE_MASK (0x10U) -#define CAN_IE_RF1NE_SHIFT (4U) -/*! RF1NE - Rx FIFO 1 new message interrupt enable. - */ -#define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK) - -#define CAN_IE_RF1WE_MASK (0x20U) -#define CAN_IE_RF1WE_SHIFT (5U) -/*! RF1WE - Rx FIFO 1 watermark reached interrupt enable. - */ -#define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK) - -#define CAN_IE_RF1FE_MASK (0x40U) -#define CAN_IE_RF1FE_SHIFT (6U) -/*! RF1FE - Rx FIFO 1 full interrupt enable. - */ -#define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK) - -#define CAN_IE_RF1LE_MASK (0x80U) -#define CAN_IE_RF1LE_SHIFT (7U) -/*! RF1LE - Rx FIFO 1 message lost interrupt enable. - */ -#define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK) - -#define CAN_IE_HPME_MASK (0x100U) -#define CAN_IE_HPME_SHIFT (8U) -/*! HPME - High priority message interrupt enable. - */ -#define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK) - -#define CAN_IE_TCE_MASK (0x200U) -#define CAN_IE_TCE_SHIFT (9U) -/*! TCE - Transmission completed interrupt enable. - */ -#define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK) - -#define CAN_IE_TCFE_MASK (0x400U) -#define CAN_IE_TCFE_SHIFT (10U) -/*! TCFE - Transmission cancellation finished interrupt enable. - */ -#define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK) - -#define CAN_IE_TFEE_MASK (0x800U) -#define CAN_IE_TFEE_SHIFT (11U) -/*! TFEE - Tx FIFO empty interrupt enable. - */ -#define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK) - -#define CAN_IE_TEFNE_MASK (0x1000U) -#define CAN_IE_TEFNE_SHIFT (12U) -/*! TEFNE - Tx event FIFO new entry interrupt enable. - */ -#define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK) - -#define CAN_IE_TEFWE_MASK (0x2000U) -#define CAN_IE_TEFWE_SHIFT (13U) -/*! TEFWE - Tx event FIFO watermark reached interrupt enable. - */ -#define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK) - -#define CAN_IE_TEFFE_MASK (0x4000U) -#define CAN_IE_TEFFE_SHIFT (14U) -/*! TEFFE - Tx event FIFO full interrupt enable. - */ -#define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK) - -#define CAN_IE_TEFLE_MASK (0x8000U) -#define CAN_IE_TEFLE_SHIFT (15U) -/*! TEFLE - Tx event FIFO element lost interrupt enable. - */ -#define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK) - -#define CAN_IE_TSWE_MASK (0x10000U) -#define CAN_IE_TSWE_SHIFT (16U) -/*! TSWE - Timestamp wraparound interrupt enable. - */ -#define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK) - -#define CAN_IE_MRAFE_MASK (0x20000U) -#define CAN_IE_MRAFE_SHIFT (17U) -/*! MRAFE - Message RAM access failure interrupt enable. - */ -#define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK) - -#define CAN_IE_TOOE_MASK (0x40000U) -#define CAN_IE_TOOE_SHIFT (18U) -/*! TOOE - Timeout occurred interrupt enable. - */ -#define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK) - -#define CAN_IE_DRXE_MASK (0x80000U) -#define CAN_IE_DRXE_SHIFT (19U) -/*! DRXE - Message stored in dedicated Rx buffer interrupt enable. - */ -#define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK) - -#define CAN_IE_BECE_MASK (0x100000U) -#define CAN_IE_BECE_SHIFT (20U) -/*! BECE - Bit error corrected interrupt enable. - */ -#define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK) - -#define CAN_IE_BEUE_MASK (0x200000U) -#define CAN_IE_BEUE_SHIFT (21U) -/*! BEUE - Bit error uncorrected interrupt enable. - */ -#define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK) - -#define CAN_IE_ELOE_MASK (0x400000U) -#define CAN_IE_ELOE_SHIFT (22U) -/*! ELOE - Error logging overflow interrupt enable. - */ -#define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK) - -#define CAN_IE_EPE_MASK (0x800000U) -#define CAN_IE_EPE_SHIFT (23U) -/*! EPE - Error passive interrupt enable. - */ -#define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK) - -#define CAN_IE_EWE_MASK (0x1000000U) -#define CAN_IE_EWE_SHIFT (24U) -/*! EWE - Warning status interrupt enable. - */ -#define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK) - -#define CAN_IE_BOE_MASK (0x2000000U) -#define CAN_IE_BOE_SHIFT (25U) -/*! BOE - Bus_Off Status interrupt enable. - */ -#define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK) - -#define CAN_IE_WDIE_MASK (0x4000000U) -#define CAN_IE_WDIE_SHIFT (26U) -/*! WDIE - Watchdog interrupt enable. - */ -#define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK) - -#define CAN_IE_PEAE_MASK (0x8000000U) -#define CAN_IE_PEAE_SHIFT (27U) -/*! PEAE - Protocol error in arbitration phase interrupt enable. - */ -#define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK) - -#define CAN_IE_PEDE_MASK (0x10000000U) -#define CAN_IE_PEDE_SHIFT (28U) -/*! PEDE - Protocol error in data phase interrupt enable. - */ -#define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK) - -#define CAN_IE_ARAE_MASK (0x20000000U) -#define CAN_IE_ARAE_SHIFT (29U) -/*! ARAE - Access to reserved address interrupt enable. - */ -#define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK) -/*! @} */ - -/*! @name ILS - Interrupt Line Select */ -/*! @{ */ - -#define CAN_ILS_RF0NL_MASK (0x1U) -#define CAN_ILS_RF0NL_SHIFT (0U) -/*! RF0NL - Rx FIFO 0 new message interrupt line. - */ -#define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK) - -#define CAN_ILS_RF0WL_MASK (0x2U) -#define CAN_ILS_RF0WL_SHIFT (1U) -/*! RF0WL - Rx FIFO 0 watermark reached interrupt line. - */ -#define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK) - -#define CAN_ILS_RF0FL_MASK (0x4U) -#define CAN_ILS_RF0FL_SHIFT (2U) -/*! RF0FL - Rx FIFO 0 full interrupt line. - */ -#define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK) - -#define CAN_ILS_RF0LL_MASK (0x8U) -#define CAN_ILS_RF0LL_SHIFT (3U) -/*! RF0LL - Rx FIFO 0 message lost interrupt line. - */ -#define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK) - -#define CAN_ILS_RF1NL_MASK (0x10U) -#define CAN_ILS_RF1NL_SHIFT (4U) -/*! RF1NL - Rx FIFO 1 new message interrupt line. - */ -#define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK) - -#define CAN_ILS_RF1WL_MASK (0x20U) -#define CAN_ILS_RF1WL_SHIFT (5U) -/*! RF1WL - Rx FIFO 1 watermark reached interrupt line. - */ -#define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK) - -#define CAN_ILS_RF1FL_MASK (0x40U) -#define CAN_ILS_RF1FL_SHIFT (6U) -/*! RF1FL - Rx FIFO 1 full interrupt line. - */ -#define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK) - -#define CAN_ILS_RF1LL_MASK (0x80U) -#define CAN_ILS_RF1LL_SHIFT (7U) -/*! RF1LL - Rx FIFO 1 message lost interrupt line. - */ -#define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK) - -#define CAN_ILS_HPML_MASK (0x100U) -#define CAN_ILS_HPML_SHIFT (8U) -/*! HPML - High priority message interrupt line. - */ -#define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK) - -#define CAN_ILS_TCL_MASK (0x200U) -#define CAN_ILS_TCL_SHIFT (9U) -/*! TCL - Transmission completed interrupt line. - */ -#define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK) - -#define CAN_ILS_TCFL_MASK (0x400U) -#define CAN_ILS_TCFL_SHIFT (10U) -/*! TCFL - Transmission cancellation finished interrupt line. - */ -#define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK) - -#define CAN_ILS_TFEL_MASK (0x800U) -#define CAN_ILS_TFEL_SHIFT (11U) -/*! TFEL - Tx FIFO empty interrupt line. - */ -#define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK) - -#define CAN_ILS_TEFNL_MASK (0x1000U) -#define CAN_ILS_TEFNL_SHIFT (12U) -/*! TEFNL - Tx event FIFO new entry interrupt line. - */ -#define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK) - -#define CAN_ILS_TEFWL_MASK (0x2000U) -#define CAN_ILS_TEFWL_SHIFT (13U) -/*! TEFWL - Tx event FIFO watermark reached interrupt line. - */ -#define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK) - -#define CAN_ILS_TEFFL_MASK (0x4000U) -#define CAN_ILS_TEFFL_SHIFT (14U) -/*! TEFFL - Tx event FIFO full interrupt line. - */ -#define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK) - -#define CAN_ILS_TEFLL_MASK (0x8000U) -#define CAN_ILS_TEFLL_SHIFT (15U) -/*! TEFLL - Tx event FIFO element lost interrupt line. - */ -#define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK) - -#define CAN_ILS_TSWL_MASK (0x10000U) -#define CAN_ILS_TSWL_SHIFT (16U) -/*! TSWL - Timestamp wraparound interrupt line. - */ -#define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK) - -#define CAN_ILS_MRAFL_MASK (0x20000U) -#define CAN_ILS_MRAFL_SHIFT (17U) -/*! MRAFL - Message RAM access failure interrupt line. - */ -#define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK) - -#define CAN_ILS_TOOL_MASK (0x40000U) -#define CAN_ILS_TOOL_SHIFT (18U) -/*! TOOL - Timeout occurred interrupt line. - */ -#define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK) - -#define CAN_ILS_DRXL_MASK (0x80000U) -#define CAN_ILS_DRXL_SHIFT (19U) -/*! DRXL - Message stored in dedicated Rx buffer interrupt line. - */ -#define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK) - -#define CAN_ILS_BECL_MASK (0x100000U) -#define CAN_ILS_BECL_SHIFT (20U) -/*! BECL - Bit error corrected interrupt line. - */ -#define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK) - -#define CAN_ILS_BEUL_MASK (0x200000U) -#define CAN_ILS_BEUL_SHIFT (21U) -/*! BEUL - Bit error uncorrected interrupt line. - */ -#define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK) - -#define CAN_ILS_ELOL_MASK (0x400000U) -#define CAN_ILS_ELOL_SHIFT (22U) -/*! ELOL - Error logging overflow interrupt line. - */ -#define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK) - -#define CAN_ILS_EPL_MASK (0x800000U) -#define CAN_ILS_EPL_SHIFT (23U) -/*! EPL - Error passive interrupt line. - */ -#define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK) - -#define CAN_ILS_EWL_MASK (0x1000000U) -#define CAN_ILS_EWL_SHIFT (24U) -/*! EWL - Warning status interrupt line. - */ -#define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK) - -#define CAN_ILS_BOL_MASK (0x2000000U) -#define CAN_ILS_BOL_SHIFT (25U) -/*! BOL - Bus_Off Status interrupt line. - */ -#define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK) - -#define CAN_ILS_WDIL_MASK (0x4000000U) -#define CAN_ILS_WDIL_SHIFT (26U) -/*! WDIL - Watchdog interrupt line. - */ -#define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK) - -#define CAN_ILS_PEAL_MASK (0x8000000U) -#define CAN_ILS_PEAL_SHIFT (27U) -/*! PEAL - Protocol error in arbitration phase interrupt line. - */ -#define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK) - -#define CAN_ILS_PEDL_MASK (0x10000000U) -#define CAN_ILS_PEDL_SHIFT (28U) -/*! PEDL - Protocol error in data phase interrupt line. - */ -#define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK) - -#define CAN_ILS_ARAL_MASK (0x20000000U) -#define CAN_ILS_ARAL_SHIFT (29U) -/*! ARAL - Access to reserved address interrupt line. - */ -#define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK) -/*! @} */ - -/*! @name ILE - Interrupt Line Enable */ -/*! @{ */ - -#define CAN_ILE_EINT0_MASK (0x1U) -#define CAN_ILE_EINT0_SHIFT (0U) -/*! EINT0 - Enable interrupt line 0. - */ -#define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK) - -#define CAN_ILE_EINT1_MASK (0x2U) -#define CAN_ILE_EINT1_SHIFT (1U) -/*! EINT1 - Enable interrupt line 1. - */ -#define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK) -/*! @} */ - -/*! @name GFC - Global Filter Configuration */ -/*! @{ */ - -#define CAN_GFC_RRFE_MASK (0x1U) -#define CAN_GFC_RRFE_SHIFT (0U) -/*! RRFE - Reject remote frames extended. - */ -#define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK) - -#define CAN_GFC_RRFS_MASK (0x2U) -#define CAN_GFC_RRFS_SHIFT (1U) -/*! RRFS - Reject remote frames standard. - */ -#define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK) - -#define CAN_GFC_ANFE_MASK (0xCU) -#define CAN_GFC_ANFE_SHIFT (2U) -/*! ANFE - Accept non-matching frames extended. - */ -#define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK) - -#define CAN_GFC_ANFS_MASK (0x30U) -#define CAN_GFC_ANFS_SHIFT (4U) -/*! ANFS - Accept non-matching frames standard. - */ -#define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK) -/*! @} */ - -/*! @name SIDFC - Standard ID Filter Configuration */ -/*! @{ */ - -#define CAN_SIDFC_FLSSA_MASK (0xFFFCU) -#define CAN_SIDFC_FLSSA_SHIFT (2U) -/*! FLSSA - Filter list standard start address. - */ -#define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK) - -#define CAN_SIDFC_LSS_MASK (0xFF0000U) -#define CAN_SIDFC_LSS_SHIFT (16U) -/*! LSS - List size standard 0 = No standard message ID filter. - */ -#define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK) -/*! @} */ - -/*! @name XIDFC - Extended ID Filter Configuration */ -/*! @{ */ - -#define CAN_XIDFC_FLESA_MASK (0xFFFCU) -#define CAN_XIDFC_FLESA_SHIFT (2U) -/*! FLESA - Filter list extended start address. - */ -#define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK) - -#define CAN_XIDFC_LSE_MASK (0xFF0000U) -#define CAN_XIDFC_LSE_SHIFT (16U) -/*! LSE - List size extended 0 = No extended message ID filter. - */ -#define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK) -/*! @} */ - -/*! @name XIDAM - Extended ID AND Mask */ -/*! @{ */ - -#define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU) -#define CAN_XIDAM_EIDM_SHIFT (0U) -/*! EIDM - Extended ID mask. - */ -#define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK) -/*! @} */ - -/*! @name HPMS - High Priority Message Status */ -/*! @{ */ - -#define CAN_HPMS_BIDX_MASK (0x3FU) -#define CAN_HPMS_BIDX_SHIFT (0U) -/*! BIDX - Buffer index. - */ -#define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK) - -#define CAN_HPMS_MSI_MASK (0xC0U) -#define CAN_HPMS_MSI_SHIFT (6U) -/*! MSI - Message storage indicator. - */ -#define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK) - -#define CAN_HPMS_FIDX_MASK (0x7F00U) -#define CAN_HPMS_FIDX_SHIFT (8U) -/*! FIDX - Filter index. - */ -#define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK) - -#define CAN_HPMS_FLST_MASK (0x8000U) -#define CAN_HPMS_FLST_SHIFT (15U) -/*! FLST - Filter list. - */ -#define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK) -/*! @} */ - -/*! @name NDAT1 - New Data 1 */ -/*! @{ */ - -#define CAN_NDAT1_ND_MASK (0xFFFFFFFFU) -#define CAN_NDAT1_ND_SHIFT (0U) -/*! ND - New Data. - */ -#define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK) -/*! @} */ - -/*! @name NDAT2 - New Data 2 */ -/*! @{ */ - -#define CAN_NDAT2_ND_MASK (0xFFFFFFFFU) -#define CAN_NDAT2_ND_SHIFT (0U) -/*! ND - New Data. - */ -#define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK) -/*! @} */ - -/*! @name RXF0C - Rx FIFO 0 Configuration */ -/*! @{ */ - -#define CAN_RXF0C_F0SA_MASK (0xFFFCU) -#define CAN_RXF0C_F0SA_SHIFT (2U) -/*! F0SA - Rx FIFO 0 start address. - */ -#define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK) - -#define CAN_RXF0C_F0S_MASK (0x7F0000U) -#define CAN_RXF0C_F0S_SHIFT (16U) -/*! F0S - Rx FIFO 0 size. - */ -#define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK) - -#define CAN_RXF0C_F0WM_MASK (0x7F000000U) -#define CAN_RXF0C_F0WM_SHIFT (24U) -/*! F0WM - Rx FIFO 0 watermark 0 = Watermark interrupt disabled. - */ -#define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK) - -#define CAN_RXF0C_F0OM_MASK (0x80000000U) -#define CAN_RXF0C_F0OM_SHIFT (31U) -/*! F0OM - FIFO 0 operation mode. - */ -#define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK) -/*! @} */ - -/*! @name RXF0S - Rx FIFO 0 Status */ -/*! @{ */ - -#define CAN_RXF0S_F0FL_MASK (0x7FU) -#define CAN_RXF0S_F0FL_SHIFT (0U) -/*! F0FL - Rx FIFO 0 fill level. - */ -#define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK) - -#define CAN_RXF0S_F0GI_MASK (0x3F00U) -#define CAN_RXF0S_F0GI_SHIFT (8U) -/*! F0GI - Rx FIFO 0 get index. - */ -#define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK) - -#define CAN_RXF0S_F0PI_MASK (0x3F0000U) -#define CAN_RXF0S_F0PI_SHIFT (16U) -/*! F0PI - Rx FIFO 0 put index. - */ -#define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK) - -#define CAN_RXF0S_F0F_MASK (0x1000000U) -#define CAN_RXF0S_F0F_SHIFT (24U) -/*! F0F - Rx FIFO 0 full. - */ -#define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK) - -#define CAN_RXF0S_RF0L_MASK (0x2000000U) -#define CAN_RXF0S_RF0L_SHIFT (25U) -/*! RF0L - Rx FIFO 0 message lost. - */ -#define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK) -/*! @} */ - -/*! @name RXF0A - Rx FIFO 0 Acknowledge */ -/*! @{ */ - -#define CAN_RXF0A_F0AI_MASK (0x3FU) -#define CAN_RXF0A_F0AI_SHIFT (0U) -/*! F0AI - Rx FIFO 0 acknowledge index. - */ -#define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK) -/*! @} */ - -/*! @name RXBC - Rx Buffer Configuration */ -/*! @{ */ - -#define CAN_RXBC_RBSA_MASK (0xFFFCU) -#define CAN_RXBC_RBSA_SHIFT (2U) -/*! RBSA - Rx buffer start address. - */ -#define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK) -/*! @} */ - -/*! @name RXF1C - Rx FIFO 1 Configuration */ -/*! @{ */ - -#define CAN_RXF1C_F1SA_MASK (0xFFFCU) -#define CAN_RXF1C_F1SA_SHIFT (2U) -/*! F1SA - Rx FIFO 1 start address. - */ -#define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK) - -#define CAN_RXF1C_F1S_MASK (0x7F0000U) -#define CAN_RXF1C_F1S_SHIFT (16U) -/*! F1S - Rx FIFO 1 size 0 = No Rx FIFO 1. - */ -#define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK) - -#define CAN_RXF1C_F1WM_MASK (0x7F000000U) -#define CAN_RXF1C_F1WM_SHIFT (24U) -/*! F1WM - Rx FIFO 1 watermark 0 = Watermark interrupt disabled. - */ -#define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK) - -#define CAN_RXF1C_F1OM_MASK (0x80000000U) -#define CAN_RXF1C_F1OM_SHIFT (31U) -/*! F1OM - FIFO 1 operation mode. - */ -#define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK) -/*! @} */ - -/*! @name RXF1S - Rx FIFO 1 Status */ -/*! @{ */ - -#define CAN_RXF1S_F1FL_MASK (0x7FU) -#define CAN_RXF1S_F1FL_SHIFT (0U) -/*! F1FL - Rx FIFO 1 fill level. - */ -#define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK) - -#define CAN_RXF1S_F1GI_MASK (0x3F00U) -#define CAN_RXF1S_F1GI_SHIFT (8U) -/*! F1GI - Rx FIFO 1 get index. - */ -#define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK) - -#define CAN_RXF1S_F1PI_MASK (0x3F0000U) -#define CAN_RXF1S_F1PI_SHIFT (16U) -/*! F1PI - Rx FIFO 1 put index. - */ -#define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK) - -#define CAN_RXF1S_F1F_MASK (0x1000000U) -#define CAN_RXF1S_F1F_SHIFT (24U) -/*! F1F - Rx FIFO 1 full. - */ -#define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK) - -#define CAN_RXF1S_RF1L_MASK (0x2000000U) -#define CAN_RXF1S_RF1L_SHIFT (25U) -/*! RF1L - Rx FIFO 1 message lost. - */ -#define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK) -/*! @} */ - -/*! @name RXF1A - Rx FIFO 1 Acknowledge */ -/*! @{ */ - -#define CAN_RXF1A_F1AI_MASK (0x3FU) -#define CAN_RXF1A_F1AI_SHIFT (0U) -/*! F1AI - Rx FIFO 1 acknowledge index. - */ -#define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK) -/*! @} */ - -/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */ -/*! @{ */ - -#define CAN_RXESC_F0DS_MASK (0x7U) -#define CAN_RXESC_F0DS_SHIFT (0U) -/*! F0DS - Rx FIFO 0 data field size. - */ -#define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK) - -#define CAN_RXESC_F1DS_MASK (0x70U) -#define CAN_RXESC_F1DS_SHIFT (4U) -/*! F1DS - Rx FIFO 1 data field size. - */ -#define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK) - -#define CAN_RXESC_RBDS_MASK (0x700U) -#define CAN_RXESC_RBDS_SHIFT (8U) -/*! RBDS - . - */ -#define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK) -/*! @} */ - -/*! @name TXBC - Tx Buffer Configuration */ -/*! @{ */ - -#define CAN_TXBC_TBSA_MASK (0xFFFCU) -#define CAN_TXBC_TBSA_SHIFT (2U) -/*! TBSA - Tx buffers start address. - */ -#define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK) - -#define CAN_TXBC_NDTB_MASK (0x3F0000U) -#define CAN_TXBC_NDTB_SHIFT (16U) -/*! NDTB - Number of dedicated transmit buffers 0 = No dedicated Tx buffers. - */ -#define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK) - -#define CAN_TXBC_TFQS_MASK (0x3F000000U) -#define CAN_TXBC_TFQS_SHIFT (24U) -/*! TFQS - Transmit FIFO/queue size 0 = No tx FIFO/Queue. - */ -#define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK) - -#define CAN_TXBC_TFQM_MASK (0x40000000U) -#define CAN_TXBC_TFQM_SHIFT (30U) -/*! TFQM - Tx FIFO/queue mode. - */ -#define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK) -/*! @} */ - -/*! @name TXFQS - Tx FIFO/Queue Status */ -/*! @{ */ - -#define CAN_TXFQS_TFGI_MASK (0x1F00U) -#define CAN_TXFQS_TFGI_SHIFT (8U) -/*! TFGI - Tx FIFO get index. - */ -#define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK) - -#define CAN_TXFQS_TFQPI_MASK (0x1F0000U) -#define CAN_TXFQS_TFQPI_SHIFT (16U) -/*! TFQPI - Tx FIFO/queue put index. - */ -#define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK) - -#define CAN_TXFQS_TFQF_MASK (0x200000U) -#define CAN_TXFQS_TFQF_SHIFT (21U) -/*! TFQF - Tx FIFO/queue full. - */ -#define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK) -/*! @} */ - -/*! @name TXESC - Tx Buffer Element Size Configuration */ -/*! @{ */ - -#define CAN_TXESC_TBDS_MASK (0x7U) -#define CAN_TXESC_TBDS_SHIFT (0U) -/*! TBDS - Tx buffer data field size. - */ -#define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK) -/*! @} */ - -/*! @name TXBRP - Tx Buffer Request Pending */ -/*! @{ */ - -#define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU) -#define CAN_TXBRP_TRP_SHIFT (0U) -/*! TRP - Transmission request pending. - */ -#define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK) -/*! @} */ - -/*! @name TXBAR - Tx Buffer Add Request */ -/*! @{ */ - -#define CAN_TXBAR_AR_MASK (0xFFFFFFFFU) -#define CAN_TXBAR_AR_SHIFT (0U) -/*! AR - Add request. - */ -#define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK) -/*! @} */ - -/*! @name TXBCR - Tx Buffer Cancellation Request */ -/*! @{ */ - -#define CAN_TXBCR_CR_MASK (0xFFFFFFFFU) -#define CAN_TXBCR_CR_SHIFT (0U) -/*! CR - Cancellation request. - */ -#define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK) -/*! @} */ - -/*! @name TXBTO - Tx Buffer Transmission Occurred */ -/*! @{ */ - -#define CAN_TXBTO_TO_MASK (0xFFFFFFFFU) -#define CAN_TXBTO_TO_SHIFT (0U) -/*! TO - Transmission occurred. - */ -#define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK) -/*! @} */ - -/*! @name TXBCF - Tx Buffer Cancellation Finished */ -/*! @{ */ - -#define CAN_TXBCF_TO_MASK (0xFFFFFFFFU) -#define CAN_TXBCF_TO_SHIFT (0U) -/*! TO - Cancellation finished. - */ -#define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK) -/*! @} */ - -/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */ -/*! @{ */ - -#define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU) -#define CAN_TXBTIE_TIE_SHIFT (0U) -/*! TIE - Transmission interrupt enable. - */ -#define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK) -/*! @} */ - -/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */ -/*! @{ */ - -#define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU) -#define CAN_TXBCIE_CFIE_SHIFT (0U) -/*! CFIE - Cancellation finished interrupt enable. - */ -#define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK) -/*! @} */ - -/*! @name TXEFC - Tx Event FIFO Configuration */ -/*! @{ */ - -#define CAN_TXEFC_EFSA_MASK (0xFFFCU) -#define CAN_TXEFC_EFSA_SHIFT (2U) -/*! EFSA - Event FIFO start address. - */ -#define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK) - -#define CAN_TXEFC_EFS_MASK (0x3F0000U) -#define CAN_TXEFC_EFS_SHIFT (16U) -/*! EFS - Event FIFO size 0 = Tx event FIFO disabled. - */ -#define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK) - -#define CAN_TXEFC_EFWM_MASK (0x3F000000U) -#define CAN_TXEFC_EFWM_SHIFT (24U) -/*! EFWM - Event FIFO watermark 0 = Watermark interrupt disabled. - */ -#define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK) -/*! @} */ - -/*! @name TXEFS - Tx Event FIFO Status */ -/*! @{ */ - -#define CAN_TXEFS_EFFL_MASK (0x3FU) -#define CAN_TXEFS_EFFL_SHIFT (0U) -/*! EFFL - Event FIFO fill level. - */ -#define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK) - -#define CAN_TXEFS_EFGI_MASK (0x1F00U) -#define CAN_TXEFS_EFGI_SHIFT (8U) -/*! EFGI - Event FIFO get index. - */ -#define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK) - -#define CAN_TXEFS_EFPI_MASK (0x3F0000U) -#define CAN_TXEFS_EFPI_SHIFT (16U) -/*! EFPI - Event FIFO put index. - */ -#define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK) - -#define CAN_TXEFS_EFF_MASK (0x1000000U) -#define CAN_TXEFS_EFF_SHIFT (24U) -/*! EFF - Event FIFO full. - */ -#define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK) - -#define CAN_TXEFS_TEFL_MASK (0x2000000U) -#define CAN_TXEFS_TEFL_SHIFT (25U) -/*! TEFL - Tx event FIFO element lost. - */ -#define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK) -/*! @} */ - -/*! @name TXEFA - Tx Event FIFO Acknowledge */ -/*! @{ */ - -#define CAN_TXEFA_EFAI_MASK (0x1FU) -#define CAN_TXEFA_EFAI_SHIFT (0U) -/*! EFAI - Event FIFO acknowledge index. - */ -#define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK) -/*! @} */ - -/*! @name MRBA - CAN Message RAM Base Address */ -/*! @{ */ - -#define CAN_MRBA_BA_MASK (0xFFFF0000U) -#define CAN_MRBA_BA_SHIFT (16U) -/*! BA - Base address for the message RAM in the chip memory map. - */ -#define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK) -/*! @} */ - -/*! @name ETSCC - External Timestamp Counter Configuration */ -/*! @{ */ - -#define CAN_ETSCC_ETCP_MASK (0x7FFU) -#define CAN_ETSCC_ETCP_SHIFT (0U) -/*! ETCP - External timestamp prescaler value. - */ -#define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK) - -#define CAN_ETSCC_ETCE_MASK (0x80000000U) -#define CAN_ETSCC_ETCE_SHIFT (31U) -/*! ETCE - External timestamp counter enable. - */ -#define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK) -/*! @} */ - -/*! @name ETSCV - External Timestamp Counter Value */ -/*! @{ */ - -#define CAN_ETSCV_ETSC_MASK (0xFFFFU) -#define CAN_ETSCV_ETSC_SHIFT (0U) -/*! ETSC - External timestamp counter. - */ -#define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CAN_Register_Masks */ - - -/* CAN - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CAN0 base address */ - #define CAN0_BASE (0x5009D000u) - /** Peripheral CAN0 base address */ - #define CAN0_BASE_NS (0x4009D000u) - /** Peripheral CAN0 base pointer */ - #define CAN0 ((CAN_Type *)CAN0_BASE) - /** Peripheral CAN0 base pointer */ - #define CAN0_NS ((CAN_Type *)CAN0_BASE_NS) - /** Array initializer of CAN peripheral base addresses */ - #define CAN_BASE_ADDRS { CAN0_BASE } - /** Array initializer of CAN peripheral base pointers */ - #define CAN_BASE_PTRS { CAN0 } - /** Array initializer of CAN peripheral base addresses */ - #define CAN_BASE_ADDRS_NS { CAN0_BASE_NS } - /** Array initializer of CAN peripheral base pointers */ - #define CAN_BASE_PTRS_NS { CAN0_NS } -#else - /** Peripheral CAN0 base address */ - #define CAN0_BASE (0x4009D000u) - /** Peripheral CAN0 base pointer */ - #define CAN0 ((CAN_Type *)CAN0_BASE) - /** Array initializer of CAN peripheral base addresses */ - #define CAN_BASE_ADDRS { CAN0_BASE } - /** Array initializer of CAN peripheral base pointers */ - #define CAN_BASE_PTRS { CAN0 } -#endif -/** Interrupt vectors for the CAN peripheral type */ -#define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn } } - -/*! - * @} - */ /* end of group CAN_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CASPER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CASPER_Peripheral_Access_Layer CASPER Peripheral Access Layer - * @{ - */ - -/** CASPER - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL0; /**< Contains the offsets of AB and CD in the RAM., offset: 0x0 */ - __IO uint32_t CTRL1; /**< Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR., offset: 0x4 */ - __IO uint32_t LOADER; /**< Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations., offset: 0x8 */ - __IO uint32_t STATUS; /**< Indicates operational status and would contain the carry bit if used., offset: 0xC */ - __IO uint32_t INTENSET; /**< Sets interrupts, offset: 0x10 */ - __IO uint32_t INTENCLR; /**< Clears interrupts, offset: 0x14 */ - __I uint32_t INTSTAT; /**< Interrupt status bits (mask of INTENSET and STATUS), offset: 0x18 */ - uint8_t RESERVED_0[4]; - __IO uint32_t AREG; /**< A register, offset: 0x20 */ - __IO uint32_t BREG; /**< B register, offset: 0x24 */ - __IO uint32_t CREG; /**< C register, offset: 0x28 */ - __IO uint32_t DREG; /**< D register, offset: 0x2C */ - __IO uint32_t RES0; /**< Result register 0, offset: 0x30 */ - __IO uint32_t RES1; /**< Result register 1, offset: 0x34 */ - __IO uint32_t RES2; /**< Result register 2, offset: 0x38 */ - __IO uint32_t RES3; /**< Result register 3, offset: 0x3C */ - uint8_t RESERVED_1[32]; - __IO uint32_t MASK; /**< Optional mask register, offset: 0x60 */ - __IO uint32_t REMASK; /**< Optional re-mask register, offset: 0x64 */ - uint8_t RESERVED_2[24]; - __IO uint32_t LOCK; /**< Security lock register, offset: 0x80 */ -} CASPER_Type; - -/* ---------------------------------------------------------------------------- - -- CASPER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CASPER_Register_Masks CASPER Register Masks - * @{ - */ - -/*! @name CTRL0 - Contains the offsets of AB and CD in the RAM. */ -/*! @{ */ - -#define CASPER_CTRL0_ABBPAIR_MASK (0x1U) -#define CASPER_CTRL0_ABBPAIR_SHIFT (0U) -/*! ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_CTRL0_ABBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK) - -#define CASPER_CTRL0_ABOFF_MASK (0x1FFCU) -#define CASPER_CTRL0_ABOFF_SHIFT (2U) -/*! ABOFF - Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code - * sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed - * if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up - */ -#define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK) - -#define CASPER_CTRL0_CDBPAIR_MASK (0x10000U) -#define CASPER_CTRL0_CDBPAIR_SHIFT (16U) -/*! CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_CTRL0_CDBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK) - -#define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U) -#define CASPER_CTRL0_CDOFF_SHIFT (18U) -/*! CDOFF - Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees - * (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 - * bit operation. Ideally not in the same RAM as the AB values - */ -#define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK) -/*! @} */ - -/*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */ -/*! @{ */ - -#define CASPER_CTRL1_ITER_MASK (0xFFU) -#define CASPER_CTRL1_ITER_SHIFT (0U) -/*! ITER - Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate. - */ -#define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK) - -#define CASPER_CTRL1_MODE_MASK (0xFF00U) -#define CASPER_CTRL1_MODE_SHIFT (8U) -/*! MODE - Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active. - */ -#define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK) - -#define CASPER_CTRL1_RESBPAIR_MASK (0x10000U) -#define CASPER_CTRL1_RESBPAIR_SHIFT (16U) -/*! RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally - * this is not the same bank as ABBPAIR (when 4-up supported) - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_CTRL1_RESBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK) - -#define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U) -#define CASPER_CTRL1_RESOFF_SHIFT (18U) -/*! RESOFF - Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally - * not in the same RAM as the AB and CD values - */ -#define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK) - -#define CASPER_CTRL1_CSKIP_MASK (0xC0000000U) -#define CASPER_CTRL1_CSKIP_SHIFT (30U) -/*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: - * 0b00..No Skip - * 0b01..Skip if Carry is 1 - * 0b10..Skip if Carry is 0 - * 0b11..Set CTRLOFF to CDOFF and Skip - */ -#define CASPER_CTRL1_CSKIP(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK) -/*! @} */ - -/*! @name LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. */ -/*! @{ */ - -#define CASPER_LOADER_COUNT_MASK (0xFFU) -#define CASPER_LOADER_COUNT_SHIFT (0U) -/*! COUNT - Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one - * op - does not iterate, write N means N control pairs to load - */ -#define CASPER_LOADER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK) - -#define CASPER_LOADER_CTRLBPAIR_MASK (0x10000U) -#define CASPER_LOADER_CTRLBPAIR_SHIFT (16U) -/*! CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not - * matter which bank is used as this is loaded when not performing an operation. - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_LOADER_CTRLBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK) - -#define CASPER_LOADER_CTRLOFF_MASK (0x1FFC0000U) -#define CASPER_LOADER_CTRLOFF_SHIFT (18U) -/*! CTRLOFF - DWord Offset of CTRL pair to load next. - */ -#define CASPER_LOADER_CTRLOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK) -/*! @} */ - -/*! @name STATUS - Indicates operational status and would contain the carry bit if used. */ -/*! @{ */ - -#define CASPER_STATUS_DONE_MASK (0x1U) -#define CASPER_STATUS_DONE_SHIFT (0U) -/*! DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. - * 0b0..Busy or just cleared - * 0b1..Completed last operation - */ -#define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK) - -#define CASPER_STATUS_CARRY_MASK (0x10U) -#define CASPER_STATUS_CARRY_SHIFT (4U) -/*! CARRY - Last carry value if operation produced a carry bit - * 0b0..Carry was 0 or no carry - * 0b1..Carry was 1 - */ -#define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK) - -#define CASPER_STATUS_BUSY_MASK (0x20U) -#define CASPER_STATUS_BUSY_SHIFT (5U) -/*! BUSY - Indicates if the accelerator is busy performing an operation - * 0b0..Not busy - is idle - * 0b1..Is busy - */ -#define CASPER_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK) -/*! @} */ - -/*! @name INTENSET - Sets interrupts */ -/*! @{ */ - -#define CASPER_INTENSET_DONE_MASK (0x1U) -#define CASPER_INTENSET_DONE_SHIFT (0U) -/*! DONE - Set if the accelerator should interrupt when done. - * 0b0..Do not interrupt when done - * 0b1..Interrupt when done - */ -#define CASPER_INTENSET_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK) -/*! @} */ - -/*! @name INTENCLR - Clears interrupts */ -/*! @{ */ - -#define CASPER_INTENCLR_DONE_MASK (0x1U) -#define CASPER_INTENCLR_DONE_SHIFT (0U) -/*! DONE - Written to clear an interrupt set with INTENSET. - * 0b0..If written 0, ignored - * 0b1..If written 1, do not Interrupt when done - */ -#define CASPER_INTENCLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) */ -/*! @{ */ - -#define CASPER_INTSTAT_DONE_MASK (0x1U) -#define CASPER_INTSTAT_DONE_SHIFT (0U) -/*! DONE - If set, interrupt is caused by accelerator being done. - * 0b0..Not caused by accelerator being done - * 0b1..Caused by accelerator being done - */ -#define CASPER_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK) -/*! @} */ - -/*! @name AREG - A register */ -/*! @{ */ - -#define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_AREG_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, - * but is available when accelerator not busy. - */ -#define CASPER_AREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name BREG - B register */ -/*! @{ */ - -#define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_BREG_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, - * but is available when accelerator not busy. - */ -#define CASPER_BREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name CREG - C register */ -/*! @{ */ - -#define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_CREG_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, - * but is available when accelerator not busy. - */ -#define CASPER_CREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name DREG - D register */ -/*! @{ */ - -#define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_DREG_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, - * but is available when accelerator not busy. - */ -#define CASPER_DREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES0 - Result register 0 */ -/*! @{ */ - -#define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES0_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally - * written or read by application, but is available when accelerator not busy. - */ -#define CASPER_RES0_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES1 - Result register 1 */ -/*! @{ */ - -#define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES1_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally - * written or read by application, but is available when accelerator not busy. - */ -#define CASPER_RES1_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES2 - Result register 2 */ -/*! @{ */ - -#define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES2_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally - * written or read by application, but is available when accelerator not busy. - */ -#define CASPER_RES2_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES3 - Result register 3 */ -/*! @{ */ - -#define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES3_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally - * written or read by application, but is available when accelerator not busy. - */ -#define CASPER_RES3_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK) -/*! @} */ - -/*! @name MASK - Optional mask register */ -/*! @{ */ - -#define CASPER_MASK_MASK_MASK (0xFFFFFFFFU) -#define CASPER_MASK_MASK_SHIFT (0U) -/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values - */ -#define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK) -/*! @} */ - -/*! @name REMASK - Optional re-mask register */ -/*! @{ */ - -#define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU) -#define CASPER_REMASK_MASK_SHIFT (0U) -/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values - */ -#define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK) -/*! @} */ - -/*! @name LOCK - Security lock register */ -/*! @{ */ - -#define CASPER_LOCK_LOCK_MASK (0x1U) -#define CASPER_LOCK_LOCK_SHIFT (0U) -/*! LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. - * 0b0..unlock - * 0b1..Lock to current security level - */ -#define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK) - -#define CASPER_LOCK_KEY_MASK (0x1FFF0U) -#define CASPER_LOCK_KEY_SHIFT (4U) -/*! KEY - Must be written as 0x73D to change the register. - * 0b0011100111101..If set during write, will allow lock or unlock - */ -#define CASPER_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CASPER_Register_Masks */ - - -/* CASPER - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CASPER base address */ - #define CASPER_BASE (0x500A5000u) - /** Peripheral CASPER base address */ - #define CASPER_BASE_NS (0x400A5000u) - /** Peripheral CASPER base pointer */ - #define CASPER ((CASPER_Type *)CASPER_BASE) - /** Peripheral CASPER base pointer */ - #define CASPER_NS ((CASPER_Type *)CASPER_BASE_NS) - /** Array initializer of CASPER peripheral base addresses */ - #define CASPER_BASE_ADDRS { CASPER_BASE } - /** Array initializer of CASPER peripheral base pointers */ - #define CASPER_BASE_PTRS { CASPER } - /** Array initializer of CASPER peripheral base addresses */ - #define CASPER_BASE_ADDRS_NS { CASPER_BASE_NS } - /** Array initializer of CASPER peripheral base pointers */ - #define CASPER_BASE_PTRS_NS { CASPER_NS } -#else - /** Peripheral CASPER base address */ - #define CASPER_BASE (0x400A5000u) - /** Peripheral CASPER base pointer */ - #define CASPER ((CASPER_Type *)CASPER_BASE) - /** Array initializer of CASPER peripheral base addresses */ - #define CASPER_BASE_ADDRS { CASPER_BASE } - /** Array initializer of CASPER peripheral base pointers */ - #define CASPER_BASE_PTRS { CASPER } -#endif -/** Interrupt vectors for the CASPER peripheral type */ -#define CASPER_IRQS { CASER_IRQn } - -/*! - * @} - */ /* end of group CASPER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CDOG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer - * @{ - */ - -/** CDOG - Register Layout Typedef */ -typedef struct { - __IO uint32_t CONTROL; /**< The control fields, which constitute CONTROL, control all controllable attributes of the module, including those of CONTROL itself., offset: 0x0 */ - __IO uint32_t RELOAD; /**< Instruction timer reload, offset: 0x4 */ - __IO uint32_t INSTRUCTION_TIMER; /**< The INSTRUCTION TIMER itself, offset: 0x8 */ - __IO uint32_t SECURE_COUNTER; /**< Also known as SEC_CNT, offset: 0xC */ - __I uint32_t STATUS; /**< Status register (1 of 2), offset: 0x10 */ - __I uint32_t STATUS2; /**< STATUS register (2 of 2), offset: 0x14 */ - __IO uint32_t FLAGS; /**< Hardware flags, offset: 0x18 */ - __IO uint32_t PERSISTENT; /**< Persistent (Ad. Hoc., quasi-NV) data storage, offset: 0x1C */ - __O uint32_t START; /**< Write address for issuing the START command., offset: 0x20 */ - __O uint32_t STOP; /**< Write address for issuing the STOP command., offset: 0x24 */ - __O uint32_t RESTART; /**< Write address for issuing the RESTART command., offset: 0x28 */ - __O uint32_t ADD; /**< Write address for issuing the ADD command., offset: 0x2C */ - __O uint32_t ADD1; /**< Write address for issuing the ADD1 command., offset: 0x30 */ - __O uint32_t ADD16; /**< Write address for issuing the ADD16 command., offset: 0x34 */ - __O uint32_t ADD256; /**< Write address for issuing the ADD16 command., offset: 0x38 */ - __O uint32_t SUB; /**< Write address for issuing the SUB command., offset: 0x3C */ - __O uint32_t SUB1; /**< Write address for issuing the SUB1 command., offset: 0x40 */ - __O uint32_t SUB16; /**< Write address for issuing the SUB16 command., offset: 0x44 */ - __O uint32_t SUB256; /**< Write address for issuing the SUB256 command., offset: 0x48 */ -} CDOG_Type; - -/* ---------------------------------------------------------------------------- - -- CDOG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CDOG_Register_Masks CDOG Register Masks - * @{ - */ - -/*! @name CONTROL - The control fields, which constitute CONTROL, control all controllable attributes of the module, including those of CONTROL itself. */ -/*! @{ */ - -#define CDOG_CONTROL_LOCK_CTRL_MASK (0x3U) -#define CDOG_CONTROL_LOCK_CTRL_SHIFT (0U) -/*! LOCK_CTRL - Lock control field - */ -#define CDOG_CONTROL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK) - -#define CDOG_CONTROL_TIMEOUT_CTRL_MASK (0x1CU) -#define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT (2U) -/*! TIMEOUT_CTRL - TIMEOUT control - */ -#define CDOG_CONTROL_TIMEOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK) - -#define CDOG_CONTROL_MISCOMPARE_CTRL_MASK (0xE0U) -#define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT (5U) -/*! MISCOMPARE_CTRL - MISCOMPARE control field - */ -#define CDOG_CONTROL_MISCOMPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK) - -#define CDOG_CONTROL_SEQUENCE_CTRL_MASK (0x700U) -#define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT (8U) -/*! SEQUENCE_CTRL - SEQUENCE control field - */ -#define CDOG_CONTROL_SEQUENCE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK) - -#define CDOG_CONTROL_CONTROL_CTRL_MASK (0x3800U) -#define CDOG_CONTROL_CONTROL_CTRL_SHIFT (11U) -/*! CONTROL_CTRL - CONTROL control field - */ -#define CDOG_CONTROL_CONTROL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_CONTROL_CTRL_SHIFT)) & CDOG_CONTROL_CONTROL_CTRL_MASK) - -#define CDOG_CONTROL_STATE_CTRL_MASK (0x1C000U) -#define CDOG_CONTROL_STATE_CTRL_SHIFT (14U) -/*! STATE_CTRL - STATE control field - */ -#define CDOG_CONTROL_STATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK) - -#define CDOG_CONTROL_ADDRESS_CTRL_MASK (0xE0000U) -#define CDOG_CONTROL_ADDRESS_CTRL_SHIFT (17U) -/*! ADDRESS_CTRL - ADDRESS control field - */ -#define CDOG_CONTROL_ADDRESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK) - -#define CDOG_CONTROL_Un_Imps_MASK (0xFF00000U) -#define CDOG_CONTROL_Un_Imps_SHIFT (20U) -/*! Un_Imps - The un-imps are un-IMPs! - */ -#define CDOG_CONTROL_Un_Imps(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_Un_Imps_SHIFT)) & CDOG_CONTROL_Un_Imps_MASK) - -#define CDOG_CONTROL_IRQ_PAUSE_MASK (0x30000000U) -#define CDOG_CONTROL_IRQ_PAUSE_SHIFT (28U) -/*! IRQ_PAUSE - IRQ pause control field - */ -#define CDOG_CONTROL_IRQ_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK) - -#define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK (0xC0000000U) -#define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT (30U) -/*! DEBUG_HALT_CTRL - DEBUG_HALT control field - */ -#define CDOG_CONTROL_DEBUG_HALT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK) -/*! @} */ - -/*! @name RELOAD - Instruction timer reload */ -/*! @{ */ - -#define CDOG_RELOAD_RLOAD_MASK (0xFFFFFFFFU) -#define CDOG_RELOAD_RLOAD_SHIFT (0U) -/*! RLOAD - Inst. Timer reload value - */ -#define CDOG_RELOAD_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK) -/*! @} */ - -/*! @name INSTRUCTION_TIMER - The INSTRUCTION TIMER itself */ -/*! @{ */ - -#define CDOG_INSTRUCTION_TIMER_INSTIM_MASK (0xFFFFFFFFU) -#define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT (0U) -/*! INSTIM - INSTRUCTION TIMER 32-bit value - */ -#define CDOG_INSTRUCTION_TIMER_INSTIM(x) (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK) -/*! @} */ - -/*! @name SECURE_COUNTER - Also known as SEC_CNT */ -/*! @{ */ - -#define CDOG_SECURE_COUNTER_SECCNT_MASK (0xFFFFFFFFU) -#define CDOG_SECURE_COUNTER_SECCNT_SHIFT (0U) -/*! SECCNT - Secure Counter - */ -#define CDOG_SECURE_COUNTER_SECCNT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SECURE_COUNTER_SECCNT_SHIFT)) & CDOG_SECURE_COUNTER_SECCNT_MASK) -/*! @} */ - -/*! @name STATUS - Status register (1 of 2) */ -/*! @{ */ - -#define CDOG_STATUS_NUMTOF_MASK (0xFFU) -#define CDOG_STATUS_NUMTOF_SHIFT (0U) -/*! NUMTOF - Number of Timeout Faults - */ -#define CDOG_STATUS_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK) - -#define CDOG_STATUS_NUMMISCOMPF_MASK (0xFF00U) -#define CDOG_STATUS_NUMMISCOMPF_SHIFT (8U) -/*! NUMMISCOMPF - Number of Miscompare Faults - */ -#define CDOG_STATUS_NUMMISCOMPF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK) - -#define CDOG_STATUS_NUMILSEQF_MASK (0xFF0000U) -#define CDOG_STATUS_NUMILSEQF_SHIFT (16U) -/*! NUMILSEQF - Number of illegal sequence faults - */ -#define CDOG_STATUS_NUMILSEQF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK) - -#define CDOG_STATUS_CURST_MASK (0xF000000U) -#define CDOG_STATUS_CURST_SHIFT (24U) -/*! CURST - Current State - */ -#define CDOG_STATUS_CURST(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK) - -#define CDOG_STATUS_uN_iMps_MASK (0xF0000000U) -#define CDOG_STATUS_uN_iMps_SHIFT (28U) -/*! uN_iMps - Un implemented - */ -#define CDOG_STATUS_uN_iMps(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_uN_iMps_SHIFT)) & CDOG_STATUS_uN_iMps_MASK) -/*! @} */ - -/*! @name STATUS2 - STATUS register (2 of 2) */ -/*! @{ */ - -#define CDOG_STATUS2_NUMCNTF_MASK (0xFFU) -#define CDOG_STATUS2_NUMCNTF_SHIFT (0U) -/*! NUMCNTF - Number (of) control faults - */ -#define CDOG_STATUS2_NUMCNTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK) - -#define CDOG_STATUS2_NUMILLSTF_MASK (0xFF00U) -#define CDOG_STATUS2_NUMILLSTF_SHIFT (8U) -/*! NUMILLSTF - Number (of) state faults - */ -#define CDOG_STATUS2_NUMILLSTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK) - -#define CDOG_STATUS2_NUMILLA_MASK (0xFF0000U) -#define CDOG_STATUS2_NUMILLA_SHIFT (16U) -/*! NUMILLA - Number of (illegal) address faults - */ -#define CDOG_STATUS2_NUMILLA(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK) - -#define CDOG_STATUS2_un_imPs_MASK (0xFF000000U) -#define CDOG_STATUS2_un_imPs_SHIFT (24U) -/*! un_imPs - Unimplemented bits, such as these here, aren't there. - */ -#define CDOG_STATUS2_un_imPs(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_un_imPs_SHIFT)) & CDOG_STATUS2_un_imPs_MASK) -/*! @} */ - -/*! @name FLAGS - Hardware flags */ -/*! @{ */ - -#define CDOG_FLAGS_TO_FLAG_MASK (0x1U) -#define CDOG_FLAGS_TO_FLAG_SHIFT (0U) -/*! TO_FLAG - Timeout flag - */ -#define CDOG_FLAGS_TO_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK) - -#define CDOG_FLAGS_MISCOM_FLAG_MASK (0x2U) -#define CDOG_FLAGS_MISCOM_FLAG_SHIFT (1U) -/*! MISCOM_FLAG - Miscompare flag - */ -#define CDOG_FLAGS_MISCOM_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK) - -#define CDOG_FLAGS_SEQ_FLAG_MASK (0x4U) -#define CDOG_FLAGS_SEQ_FLAG_SHIFT (2U) -/*! SEQ_FLAG - Sequence flag - */ -#define CDOG_FLAGS_SEQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK) - -#define CDOG_FLAGS_CNT_FLAG_MASK (0x8U) -#define CDOG_FLAGS_CNT_FLAG_SHIFT (3U) -/*! CNT_FLAG - Control (fault) flag - */ -#define CDOG_FLAGS_CNT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK) - -#define CDOG_FLAGS_STATE_FLAG_MASK (0x10U) -#define CDOG_FLAGS_STATE_FLAG_SHIFT (4U) -/*! STATE_FLAG - State flag - */ -#define CDOG_FLAGS_STATE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK) - -#define CDOG_FLAGS_ADDR_FLAG_MASK (0x20U) -#define CDOG_FLAGS_ADDR_FLAG_SHIFT (5U) -/*! ADDR_FLAG - Address flag - */ -#define CDOG_FLAGS_ADDR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK) - -#define CDOG_FLAGS_POR_FLAG_MASK (0x10000U) -#define CDOG_FLAGS_POR_FLAG_SHIFT (16U) -/*! POR_FLAG - Power-on reset flag - */ -#define CDOG_FLAGS_POR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK) -/*! @} */ - -/*! @name PERSISTENT - Persistent (Ad. Hoc., quasi-NV) data storage */ -/*! @{ */ - -#define CDOG_PERSISTENT_PERSIS_MASK (0xFFFFFFFFU) -#define CDOG_PERSISTENT_PERSIS_SHIFT (0U) -/*! PERSIS - 32 regs free for user SW to enjoy - */ -#define CDOG_PERSISTENT_PERSIS(x) (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK) -/*! @} */ - -/*! @name START - Write address for issuing the START command. */ -/*! @{ */ - -#define CDOG_START_STRT_MASK (0xFFFFFFFFU) -#define CDOG_START_STRT_SHIFT (0U) -/*! STRT - Address of start command access - */ -#define CDOG_START_STRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK) -/*! @} */ - -/*! @name STOP - Write address for issuing the STOP command. */ -/*! @{ */ - -#define CDOG_STOP_STP_MASK (0xFFFFFFFFU) -#define CDOG_STOP_STP_SHIFT (0U) -/*! STP - Address of stop command access - */ -#define CDOG_STOP_STP(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK) -/*! @} */ - -/*! @name RESTART - Write address for issuing the RESTART command. */ -/*! @{ */ - -#define CDOG_RESTART_RSTRT_MASK (0xFFFFFFFFU) -#define CDOG_RESTART_RSTRT_SHIFT (0U) -/*! RSTRT - Write address for issuing the RESTART command. - */ -#define CDOG_RESTART_RSTRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK) -/*! @} */ - -/*! @name ADD - Write address for issuing the ADD command. */ -/*! @{ */ - -#define CDOG_ADD_AD_MASK (0xFFFFFFFFU) -#define CDOG_ADD_AD_SHIFT (0U) -/*! AD - Address of ADD command - */ -#define CDOG_ADD_AD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK) -/*! @} */ - -/*! @name ADD1 - Write address for issuing the ADD1 command. */ -/*! @{ */ - -#define CDOG_ADD1_AD1_MASK (0xFFFFFFFFU) -#define CDOG_ADD1_AD1_SHIFT (0U) -/*! AD1 - Address of ADD1 command. - */ -#define CDOG_ADD1_AD1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK) -/*! @} */ - -/*! @name ADD16 - Write address for issuing the ADD16 command. */ -/*! @{ */ - -#define CDOG_ADD16_AD16_MASK (0xFFFFFFFFU) -#define CDOG_ADD16_AD16_SHIFT (0U) -/*! AD16 - Address of ADD16 - */ -#define CDOG_ADD16_AD16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK) -/*! @} */ - -/*! @name ADD256 - Write address for issuing the ADD16 command. */ -/*! @{ */ - -#define CDOG_ADD256_AD256_MASK (0xFFFFFFFFU) -#define CDOG_ADD256_AD256_SHIFT (0U) -/*! AD256 - Address of ADD256 command - */ -#define CDOG_ADD256_AD256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK) -/*! @} */ - -/*! @name SUB - Write address for issuing the SUB command. */ -/*! @{ */ - -#define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) -#define CDOG_SUB_S0B_SHIFT (0U) -/*! S0B - Address of SUB command. - */ -#define CDOG_SUB_S0B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK) -/*! @} */ - -/*! @name SUB1 - Write address for issuing the SUB1 command. */ -/*! @{ */ - -#define CDOG_SUB1_S1B_MASK (0xFFFFFFFFU) -#define CDOG_SUB1_S1B_SHIFT (0U) -/*! S1B - Address of SUB1 command. - */ -#define CDOG_SUB1_S1B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_S1B_SHIFT)) & CDOG_SUB1_S1B_MASK) -/*! @} */ - -/*! @name SUB16 - Write address for issuing the SUB16 command. */ -/*! @{ */ - -#define CDOG_SUB16_SB16_MASK (0xFFFFFFFFU) -#define CDOG_SUB16_SB16_SHIFT (0U) -/*! SB16 - Address of SUB16 command. - */ -#define CDOG_SUB16_SB16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK) -/*! @} */ - -/*! @name SUB256 - Write address for issuing the SUB256 command. */ -/*! @{ */ - -#define CDOG_SUB256_SB256_MASK (0xFFFFFFFFU) -#define CDOG_SUB256_SB256_SHIFT (0U) -/*! SB256 - Address of (you guessed it) SUB256 command. - */ -#define CDOG_SUB256_SB256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CDOG_Register_Masks */ - - -/* CDOG - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CDOG base address */ - #define CDOG_BASE (0x500A1000u) - /** Peripheral CDOG base address */ - #define CDOG_BASE_NS (0x400A1000u) - /** Peripheral CDOG base pointer */ - #define CDOG ((CDOG_Type *)CDOG_BASE) - /** Peripheral CDOG base pointer */ - #define CDOG_NS ((CDOG_Type *)CDOG_BASE_NS) - /** Array initializer of CDOG peripheral base addresses */ - #define CDOG_BASE_ADDRS { CDOG_BASE } - /** Array initializer of CDOG peripheral base pointers */ - #define CDOG_BASE_PTRS { CDOG } - /** Array initializer of CDOG peripheral base addresses */ - #define CDOG_BASE_ADDRS_NS { CDOG_BASE_NS } - /** Array initializer of CDOG peripheral base pointers */ - #define CDOG_BASE_PTRS_NS { CDOG_NS } -#else - /** Peripheral CDOG base address */ - #define CDOG_BASE (0x400A1000u) - /** Peripheral CDOG base pointer */ - #define CDOG ((CDOG_Type *)CDOG_BASE) - /** Array initializer of CDOG peripheral base addresses */ - #define CDOG_BASE_ADDRS { CDOG_BASE } - /** Array initializer of CDOG peripheral base pointers */ - #define CDOG_BASE_PTRS { CDOG } -#endif -/** Interrupt vectors for the CDOG peripheral type */ -#define CDOG_IRQS { CDOG_IRQn } - -/*! - * @} - */ /* end of group CDOG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CRC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer - * @{ - */ - -/** CRC - Register Layout Typedef */ -typedef struct { - __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ - __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ - union { /* offset: 0x8 */ - __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ - __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ - }; -} CRC_Type; - -/* ---------------------------------------------------------------------------- - -- CRC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Register_Masks CRC Register Masks - * @{ - */ - -/*! @name MODE - CRC mode register */ -/*! @{ */ - -#define CRC_MODE_CRC_POLY_MASK (0x3U) -#define CRC_MODE_CRC_POLY_SHIFT (0U) -/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial - */ -#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) - -#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) -#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) -/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) - */ -#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) - -#define CRC_MODE_CMPL_WR_MASK (0x8U) -#define CRC_MODE_CMPL_WR_SHIFT (3U) -/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA - */ -#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) - -#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) -#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) -/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM - */ -#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) - -#define CRC_MODE_CMPL_SUM_MASK (0x20U) -#define CRC_MODE_CMPL_SUM_SHIFT (5U) -/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM - */ -#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) -/*! @} */ - -/*! @name SEED - CRC seed register */ -/*! @{ */ - -#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) -#define CRC_SEED_CRC_SEED_SHIFT (0U) -/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with - * selected bit order and 1's complement pre-processes. A write access to this register will - * overrule the CRC calculation in progresses. - */ -#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) -/*! @} */ - -/*! @name SUM - CRC checksum register */ -/*! @{ */ - -#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) -#define CRC_SUM_CRC_SUM_SHIFT (0U) -/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. - */ -#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) -/*! @} */ - -/*! @name WR_DATA - CRC data register */ -/*! @{ */ - -#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) -#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) -/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with - * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and - * accept back-to-back transactions. - */ -#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CRC_Register_Masks */ - - -/* CRC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CRC_ENGINE base address */ - #define CRC_ENGINE_BASE (0x50095000u) - /** Peripheral CRC_ENGINE base address */ - #define CRC_ENGINE_BASE_NS (0x40095000u) - /** Peripheral CRC_ENGINE base pointer */ - #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) - /** Peripheral CRC_ENGINE base pointer */ - #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS) - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS { CRC_ENGINE } - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS } -#else - /** Peripheral CRC_ENGINE base address */ - #define CRC_ENGINE_BASE (0x40095000u) - /** Peripheral CRC_ENGINE base pointer */ - #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS { CRC_ENGINE } -#endif - -/*! - * @} - */ /* end of group CRC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CTIMER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer - * @{ - */ - -/** CTIMER - Register Layout Typedef */ -typedef struct { - __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ - __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ - __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ - __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ - __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ - __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ - __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ - __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ - __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ - __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ - uint8_t RESERVED_0[48]; - __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ - __IO uint32_t PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */ - __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ -} CTIMER_Type; - -/* ---------------------------------------------------------------------------- - -- CTIMER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Register_Masks CTIMER Register Masks - * @{ - */ - -/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ -/*! @{ */ - -#define CTIMER_IR_MR0INT_MASK (0x1U) -#define CTIMER_IR_MR0INT_SHIFT (0U) -/*! MR0INT - Interrupt flag for match channel 0. - */ -#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) - -#define CTIMER_IR_MR1INT_MASK (0x2U) -#define CTIMER_IR_MR1INT_SHIFT (1U) -/*! MR1INT - Interrupt flag for match channel 1. - */ -#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) - -#define CTIMER_IR_MR2INT_MASK (0x4U) -#define CTIMER_IR_MR2INT_SHIFT (2U) -/*! MR2INT - Interrupt flag for match channel 2. - */ -#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) - -#define CTIMER_IR_MR3INT_MASK (0x8U) -#define CTIMER_IR_MR3INT_SHIFT (3U) -/*! MR3INT - Interrupt flag for match channel 3. - */ -#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) - -#define CTIMER_IR_CR0INT_MASK (0x10U) -#define CTIMER_IR_CR0INT_SHIFT (4U) -/*! CR0INT - Interrupt flag for capture channel 0 event. - */ -#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) - -#define CTIMER_IR_CR1INT_MASK (0x20U) -#define CTIMER_IR_CR1INT_SHIFT (5U) -/*! CR1INT - Interrupt flag for capture channel 1 event. - */ -#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) - -#define CTIMER_IR_CR2INT_MASK (0x40U) -#define CTIMER_IR_CR2INT_SHIFT (6U) -/*! CR2INT - Interrupt flag for capture channel 2 event. - */ -#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) - -#define CTIMER_IR_CR3INT_MASK (0x80U) -#define CTIMER_IR_CR3INT_SHIFT (7U) -/*! CR3INT - Interrupt flag for capture channel 3 event. - */ -#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) -/*! @} */ - -/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ -/*! @{ */ - -#define CTIMER_TCR_CEN_MASK (0x1U) -#define CTIMER_TCR_CEN_SHIFT (0U) -/*! CEN - Counter enable. - * 0b0..Disabled.The counters are disabled. - * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. - */ -#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) - -#define CTIMER_TCR_CRST_MASK (0x2U) -#define CTIMER_TCR_CRST_SHIFT (1U) -/*! CRST - Counter reset. - * 0b0..Disabled. Do nothing. - * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of - * the APB bus clock. The counters remain reset until TCR[1] is returned to zero. - */ -#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) -/*! @} */ - -/*! @name TC - Timer Counter */ -/*! @{ */ - -#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_TC_TCVAL_SHIFT (0U) -/*! TCVAL - Timer counter value. - */ -#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) -/*! @} */ - -/*! @name PR - Prescale Register */ -/*! @{ */ - -#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PR_PRVAL_SHIFT (0U) -/*! PRVAL - Prescale counter value. - */ -#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) -/*! @} */ - -/*! @name PC - Prescale Counter */ -/*! @{ */ - -#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PC_PCVAL_SHIFT (0U) -/*! PCVAL - Prescale counter value. - */ -#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) -/*! @} */ - -/*! @name MCR - Match Control Register */ -/*! @{ */ - -#define CTIMER_MCR_MR0I_MASK (0x1U) -#define CTIMER_MCR_MR0I_SHIFT (0U) -/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. - */ -#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) - -#define CTIMER_MCR_MR0R_MASK (0x2U) -#define CTIMER_MCR_MR0R_SHIFT (1U) -/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. - */ -#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) - -#define CTIMER_MCR_MR0S_MASK (0x4U) -#define CTIMER_MCR_MR0S_SHIFT (2U) -/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. - */ -#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) - -#define CTIMER_MCR_MR1I_MASK (0x8U) -#define CTIMER_MCR_MR1I_SHIFT (3U) -/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. - */ -#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) - -#define CTIMER_MCR_MR1R_MASK (0x10U) -#define CTIMER_MCR_MR1R_SHIFT (4U) -/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. - */ -#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) - -#define CTIMER_MCR_MR1S_MASK (0x20U) -#define CTIMER_MCR_MR1S_SHIFT (5U) -/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. - */ -#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) - -#define CTIMER_MCR_MR2I_MASK (0x40U) -#define CTIMER_MCR_MR2I_SHIFT (6U) -/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. - */ -#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) - -#define CTIMER_MCR_MR2R_MASK (0x80U) -#define CTIMER_MCR_MR2R_SHIFT (7U) -/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. - */ -#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) - -#define CTIMER_MCR_MR2S_MASK (0x100U) -#define CTIMER_MCR_MR2S_SHIFT (8U) -/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. - */ -#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) - -#define CTIMER_MCR_MR3I_MASK (0x200U) -#define CTIMER_MCR_MR3I_SHIFT (9U) -/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. - */ -#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) - -#define CTIMER_MCR_MR3R_MASK (0x400U) -#define CTIMER_MCR_MR3R_SHIFT (10U) -/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it. - */ -#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) - -#define CTIMER_MCR_MR3S_MASK (0x800U) -#define CTIMER_MCR_MR3S_SHIFT (11U) -/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. - */ -#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) - -#define CTIMER_MCR_MR0RL_MASK (0x1000000U) -#define CTIMER_MCR_MR0RL_SHIFT (24U) -/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero - * (either via a match event or a write to bit 1 of the TCR). - */ -#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) - -#define CTIMER_MCR_MR1RL_MASK (0x2000000U) -#define CTIMER_MCR_MR1RL_SHIFT (25U) -/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero - * (either via a match event or a write to bit 1 of the TCR). - */ -#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) - -#define CTIMER_MCR_MR2RL_MASK (0x4000000U) -#define CTIMER_MCR_MR2RL_SHIFT (26U) -/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero - * (either via a match event or a write to bit 1 of the TCR). - */ -#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) - -#define CTIMER_MCR_MR3RL_MASK (0x8000000U) -#define CTIMER_MCR_MR3RL_SHIFT (27U) -/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero - * (either via a match event or a write to bit 1 of the TCR). - */ -#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) -/*! @} */ - -/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ -/*! @{ */ - -#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) -#define CTIMER_MR_MATCH_SHIFT (0U) -/*! MATCH - Timer counter match value. - */ -#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) -/*! @} */ - -/* The count of CTIMER_MR */ -#define CTIMER_MR_COUNT (4U) - -/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ -/*! @{ */ - -#define CTIMER_CCR_CAP0RE_MASK (0x1U) -#define CTIMER_CCR_CAP0RE_SHIFT (0U) -/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) - -#define CTIMER_CCR_CAP0FE_MASK (0x2U) -#define CTIMER_CCR_CAP0FE_SHIFT (1U) -/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) - -#define CTIMER_CCR_CAP0I_MASK (0x4U) -#define CTIMER_CCR_CAP0I_SHIFT (2U) -/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. - */ -#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) - -#define CTIMER_CCR_CAP1RE_MASK (0x8U) -#define CTIMER_CCR_CAP1RE_SHIFT (3U) -/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) - -#define CTIMER_CCR_CAP1FE_MASK (0x10U) -#define CTIMER_CCR_CAP1FE_SHIFT (4U) -/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) - -#define CTIMER_CCR_CAP1I_MASK (0x20U) -#define CTIMER_CCR_CAP1I_SHIFT (5U) -/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. - */ -#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) - -#define CTIMER_CCR_CAP2RE_MASK (0x40U) -#define CTIMER_CCR_CAP2RE_SHIFT (6U) -/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) - -#define CTIMER_CCR_CAP2FE_MASK (0x80U) -#define CTIMER_CCR_CAP2FE_SHIFT (7U) -/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) - -#define CTIMER_CCR_CAP2I_MASK (0x100U) -#define CTIMER_CCR_CAP2I_SHIFT (8U) -/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. - */ -#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) - -#define CTIMER_CCR_CAP3RE_MASK (0x200U) -#define CTIMER_CCR_CAP3RE_SHIFT (9U) -/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) - -#define CTIMER_CCR_CAP3FE_MASK (0x400U) -#define CTIMER_CCR_CAP3FE_SHIFT (10U) -/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) - -#define CTIMER_CCR_CAP3I_MASK (0x800U) -#define CTIMER_CCR_CAP3I_SHIFT (11U) -/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. - */ -#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) -/*! @} */ - -/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ -/*! @{ */ - -#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) -#define CTIMER_CR_CAP_SHIFT (0U) -/*! CAP - Timer counter capture value. - */ -#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) -/*! @} */ - -/* The count of CTIMER_CR */ -#define CTIMER_CR_COUNT (4U) - -/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ -/*! @{ */ - -#define CTIMER_EMR_EM0_MASK (0x1U) -#define CTIMER_EMR_EM0_SHIFT (0U) -/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output - * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, - * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if - * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - */ -#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) - -#define CTIMER_EMR_EM1_MASK (0x2U) -#define CTIMER_EMR_EM1_SHIFT (1U) -/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output - * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, - * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if - * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - */ -#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) - -#define CTIMER_EMR_EM2_MASK (0x4U) -#define CTIMER_EMR_EM2_SHIFT (2U) -/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output - * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, - * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if - * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - */ -#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) - -#define CTIMER_EMR_EM3_MASK (0x8U) -#define CTIMER_EMR_EM3_SHIFT (3U) -/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output - * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, - * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins - * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - */ -#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) - -#define CTIMER_EMR_EMC0_MASK (0x30U) -#define CTIMER_EMR_EMC0_SHIFT (4U) -/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) - -#define CTIMER_EMR_EMC1_MASK (0xC0U) -#define CTIMER_EMR_EMC1_SHIFT (6U) -/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) - -#define CTIMER_EMR_EMC2_MASK (0x300U) -#define CTIMER_EMR_EMC2_SHIFT (8U) -/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) - -#define CTIMER_EMR_EMC3_MASK (0xC00U) -#define CTIMER_EMR_EMC3_SHIFT (10U) -/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) -/*! @} */ - -/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ -/*! @{ */ - -#define CTIMER_CTCR_CTMODE_MASK (0x3U) -#define CTIMER_CTCR_CTMODE_SHIFT (0U) -/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment - * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC - * is incremented when the Prescale Counter matches the Prescale Register. - * 0b00..Timer Mode. Incremented every rising APB bus clock edge. - * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. - * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. - * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. - */ -#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) - -#define CTIMER_CTCR_CINSEL_MASK (0xCU) -#define CTIMER_CTCR_CINSEL_SHIFT (2U) -/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which - * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input - * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be - * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the - * same timer. - * 0b00..Channel 0. CAPn.0 for CTIMERn - * 0b01..Channel 1. CAPn.1 for CTIMERn - * 0b10..Channel 2. CAPn.2 for CTIMERn - * 0b11..Channel 3. CAPn.3 for CTIMERn - */ -#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) - -#define CTIMER_CTCR_ENCC_MASK (0x10U) -#define CTIMER_CTCR_ENCC_SHIFT (4U) -/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the - * capture-edge event specified in bits 7:5 occurs. - */ -#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) - -#define CTIMER_CTCR_SELCC_MASK (0xE0U) -#define CTIMER_CTCR_SELCC_SHIFT (5U) -/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the - * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to - * 0x3 and 0x6 to 0x7 are reserved. - * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - */ -#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) -/*! @} */ - -/*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */ -/*! @{ */ - -#define CTIMER_PWMC_PWMEN0_MASK (0x1U) -#define CTIMER_PWMC_PWMEN0_SHIFT (0U) -/*! PWMEN0 - PWM mode enable for channel0. - * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. - */ -#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) - -#define CTIMER_PWMC_PWMEN1_MASK (0x2U) -#define CTIMER_PWMC_PWMEN1_SHIFT (1U) -/*! PWMEN1 - PWM mode enable for channel1. - * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. - */ -#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) - -#define CTIMER_PWMC_PWMEN2_MASK (0x4U) -#define CTIMER_PWMC_PWMEN2_SHIFT (2U) -/*! PWMEN2 - PWM mode enable for channel2. - * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. - */ -#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) - -#define CTIMER_PWMC_PWMEN3_MASK (0x8U) -#define CTIMER_PWMC_PWMEN3_SHIFT (3U) -/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. - * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. - * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. - */ -#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) -/*! @} */ - -/*! @name MSR - Match Shadow Register */ -/*! @{ */ - -#define CTIMER_MSR_SHADOW_MASK (0xFFFFFFFFU) -#define CTIMER_MSR_SHADOW_SHIFT (0U) -/*! SHADOW - Timer counter match shadow value. - */ -#define CTIMER_MSR_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOW_SHIFT)) & CTIMER_MSR_SHADOW_MASK) -/*! @} */ - -/* The count of CTIMER_MSR */ -#define CTIMER_MSR_COUNT (4U) - - -/*! - * @} - */ /* end of group CTIMER_Register_Masks */ - - -/* CTIMER - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE (0x50008000u) - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE_NS (0x40008000u) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE (0x50009000u) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE_NS (0x40009000u) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE (0x50028000u) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE_NS (0x40028000u) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE (0x50029000u) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE_NS (0x40029000u) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE (0x5002A000u) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE_NS (0x4002A000u) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } -#else - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE (0x40008000u) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE (0x40009000u) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE (0x40028000u) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE (0x40029000u) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE (0x4002A000u) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } -#endif -/** Interrupt vectors for the CTIMER peripheral type */ -#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } - -/*! - * @} - */ /* end of group CTIMER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DBGMAILBOX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DBGMAILBOX_Peripheral_Access_Layer DBGMAILBOX Peripheral Access Layer - * @{ - */ - -/** DBGMAILBOX - Register Layout Typedef */ -typedef struct { - __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */ - __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */ - __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */ - uint8_t RESERVED_0[240]; - __I uint32_t ID; /**< Identification register, offset: 0xFC */ -} DBGMAILBOX_Type; - -/* ---------------------------------------------------------------------------- - -- DBGMAILBOX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DBGMAILBOX_Register_Masks DBGMAILBOX Register Masks - * @{ - */ - -/*! @name CSW - CRC mode register */ -/*! @{ */ - -#define DBGMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) -#define DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) -/*! RESYNCH_REQ - Debugger will set this bit to 1 to request a resynchronrisation - */ -#define DBGMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DBGMAILBOX_CSW_RESYNCH_REQ_MASK) - -#define DBGMAILBOX_CSW_REQ_PENDING_MASK (0x2U) -#define DBGMAILBOX_CSW_REQ_PENDING_SHIFT (1U) -/*! REQ_PENDING - Request is pending from debugger (i.e unread value in REQUEST) - */ -#define DBGMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DBGMAILBOX_CSW_REQ_PENDING_MASK) - -#define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) -#define DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) -/*! DBG_OR_ERR - Debugger overrun error (previous REQUEST overwritten before being picked up by ROM) - */ -#define DBGMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK) - -#define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) -#define DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) -/*! AHB_OR_ERR - AHB overrun Error (Return value overwritten by ROM) - */ -#define DBGMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK) - -#define DBGMAILBOX_CSW_SOFT_RESET_MASK (0x10U) -#define DBGMAILBOX_CSW_SOFT_RESET_SHIFT (4U) -/*! SOFT_RESET - Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to - * this bit will cause a soft reset for DM. - */ -#define DBGMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DBGMAILBOX_CSW_SOFT_RESET_MASK) - -#define DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) -#define DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) -/*! CHIP_RESET_REQ - Write only bit. Once written will cause the chip to reset (note that the DM is - * not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event) - */ -#define DBGMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK) -/*! @} */ - -/*! @name REQUEST - CRC seed register */ -/*! @{ */ - -#define DBGMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU) -#define DBGMAILBOX_REQUEST_REQ_SHIFT (0U) -/*! REQ - Request Value - */ -#define DBGMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_REQUEST_REQ_SHIFT)) & DBGMAILBOX_REQUEST_REQ_MASK) -/*! @} */ - -/*! @name RETURN - Return value from ROM. */ -/*! @{ */ - -#define DBGMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) -#define DBGMAILBOX_RETURN_RET_SHIFT (0U) -/*! RET - The Return value from ROM. - */ -#define DBGMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_RETURN_RET_SHIFT)) & DBGMAILBOX_RETURN_RET_MASK) -/*! @} */ - -/*! @name ID - Identification register */ -/*! @{ */ - -#define DBGMAILBOX_ID_ID_MASK (0xFFFFFFFFU) -#define DBGMAILBOX_ID_ID_SHIFT (0U) -/*! ID - Identification value. - */ -#define DBGMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_ID_ID_SHIFT)) & DBGMAILBOX_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group DBGMAILBOX_Register_Masks */ - - -/* DBGMAILBOX - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral DBGMAILBOX base address */ - #define DBGMAILBOX_BASE (0x5009C000u) - /** Peripheral DBGMAILBOX base address */ - #define DBGMAILBOX_BASE_NS (0x4009C000u) - /** Peripheral DBGMAILBOX base pointer */ - #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) - /** Peripheral DBGMAILBOX base pointer */ - #define DBGMAILBOX_NS ((DBGMAILBOX_Type *)DBGMAILBOX_BASE_NS) - /** Array initializer of DBGMAILBOX peripheral base addresses */ - #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } - /** Array initializer of DBGMAILBOX peripheral base pointers */ - #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } - /** Array initializer of DBGMAILBOX peripheral base addresses */ - #define DBGMAILBOX_BASE_ADDRS_NS { DBGMAILBOX_BASE_NS } - /** Array initializer of DBGMAILBOX peripheral base pointers */ - #define DBGMAILBOX_BASE_PTRS_NS { DBGMAILBOX_NS } -#else - /** Peripheral DBGMAILBOX base address */ - #define DBGMAILBOX_BASE (0x4009C000u) - /** Peripheral DBGMAILBOX base pointer */ - #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) - /** Array initializer of DBGMAILBOX peripheral base addresses */ - #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } - /** Array initializer of DBGMAILBOX peripheral base pointers */ - #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } -#endif - -/*! - * @} - */ /* end of group DBGMAILBOX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer - * @{ - */ - -/** DMA - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ - __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ - __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ - uint8_t RESERVED_0[20]; - struct { /* offset: 0x20, array step: 0x5C */ - __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ - uint8_t RESERVED_0[4]; - __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ - uint8_t RESERVED_1[4]; - __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ - uint8_t RESERVED_2[4]; - __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ - uint8_t RESERVED_3[4]; - __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ - uint8_t RESERVED_4[4]; - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ - uint8_t RESERVED_5[4]; - __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ - uint8_t RESERVED_6[4]; - __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ - uint8_t RESERVED_7[4]; - __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ - uint8_t RESERVED_8[4]; - __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ - uint8_t RESERVED_9[4]; - __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ - uint8_t RESERVED_10[4]; - __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ - } COMMON[1]; - uint8_t RESERVED_1[900]; - struct { /* offset: 0x400, array step: 0x10 */ - __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ - __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ - __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } CHANNEL[23]; -} DMA_Type; - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/*! @name CTRL - DMA control. */ -/*! @{ */ - -#define DMA_CTRL_ENABLE_MASK (0x1U) -#define DMA_CTRL_ENABLE_SHIFT (0U) -/*! ENABLE - DMA controller master enable. - * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when - * disabled, but does not prevent re-triggering when the DMA controller is re-enabled. - * 0b1..Enabled. The DMA controller is enabled. - */ -#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status. */ -/*! @{ */ - -#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) -#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) -/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. - * 0b0..Not pending. No enabled interrupts are pending. - * 0b1..Pending. At least one enabled interrupt is pending. - */ -#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) - -#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) -#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) -/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. - * 0b0..Not pending. No error interrupts are pending. - * 0b1..Pending. At least one error interrupt is pending. - */ -#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) -/*! @} */ - -/*! @name SRAMBASE - SRAM address of the channel configuration table. */ -/*! @{ */ - -#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) -#define DMA_SRAMBASE_OFFSET_SHIFT (9U) -/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the - * table must begin on a 512 byte boundary. - */ -#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) -/*! @} */ - -/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) -/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = - * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. - */ -#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLESET */ -#define DMA_COMMON_ENABLESET_COUNT (1U) - -/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) -/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears - * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits - * are reserved. - */ -#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLECLR */ -#define DMA_COMMON_ENABLECLR_COUNT (1U) - -/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) -/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = - * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. - */ -#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ACTIVE */ -#define DMA_COMMON_ACTIVE_COUNT (1U) - -/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) -#define DMA_COMMON_BUSY_BSY_SHIFT (0U) -/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = - * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. - */ -#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) -/*! @} */ - -/* The count of DMA_COMMON_BUSY */ -#define DMA_COMMON_BUSY_COUNT (1U) - -/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) -/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of - * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is - * not active. 1 = error interrupt is active. - */ -#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ERRINT */ -#define DMA_COMMON_ERRINT_COUNT (1U) - -/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) -/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The - * number of bits = number of DMA channels in this device. Other bits are reserved. 0 = - * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENSET */ -#define DMA_COMMON_INTENSET_COUNT (1U) - -/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) -/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n - * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are - * reserved. - */ -#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENCLR */ -#define DMA_COMMON_INTENCLR_COUNT (1U) - -/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTA_IA_SHIFT (0U) -/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of - * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel - * interrupt A is not active. 1 = the DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTA */ -#define DMA_COMMON_INTA_COUNT (1U) - -/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTB_IB_SHIFT (0U) -/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of - * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel - * interrupt B is not active. 1 = the DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTB */ -#define DMA_COMMON_INTB_COUNT (1U) - -/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETVALID_SV_SHIFT (0U) -/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits - * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the - * VALIDPENDING control bit for DMA channel n - */ -#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETVALID */ -#define DMA_COMMON_SETVALID_COUNT (1U) - -/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) -/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number - * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = - * sets the TRIG bit for DMA channel n. - */ -#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETTRIG */ -#define DMA_COMMON_SETTRIG_COUNT (1U) - -/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) -/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. - * 1 = aborts DMA operations on channel n. - */ -#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ABORT */ -#define DMA_COMMON_ABORT_COUNT (1U) - -/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ -/*! @{ */ - -#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) -#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) -/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory - * move, any peripheral DMA request associated with that channel can be disabled to prevent any - * interaction between the peripheral and the DMA controller. - * 0b0..Disabled. Peripheral DMA requests are disabled. - * 0b1..Enabled. Peripheral DMA requests are enabled. - */ -#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) - -#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) -#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) -/*! HWTRIGEN - Hardware Triggering Enable for this channel. - * 0b0..Disabled. Hardware triggering is not used. - * 0b1..Enabled. Use hardware triggering. - */ -#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) - -#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) -#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) -/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. - * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. - * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. - */ -#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) - -#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) -#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) -/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. - * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. - * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = - * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the - * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger - * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the - * current BURSTPOWER length are completed. - */ -#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) - -#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) -#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) -/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. - * 0b0..Single transfer. Hardware trigger causes a single transfer. - * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a - * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a - * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is - * complete. - */ -#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) - -#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) -#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) -/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when - * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). - * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many - * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that - * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: - * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = - * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The - * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even - * multiple of the burst size. - */ -#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) - -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) -/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is - * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this - * could be used to read several sequential registers from a peripheral for each DMA burst, - * reading the same registers again for each burst. - * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. - * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. - */ -#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) - -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) -/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is - * 'wrapped', meaning that the destination address range for each burst will be the same. As an - * example, this could be used to write several sequential registers to a peripheral for each DMA - * burst, writing the same registers again for each burst. - * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. - * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. - */ -#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) - -#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) -#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) -/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority - * levels are supported: 0x0 = highest priority. 0x7 = lowest priority. - */ -#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CFG */ -#define DMA_CHANNEL_CFG_COUNT (23U) - -/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ -/*! @{ */ - -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) -/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the - * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. - * 0b0..No effect. No effect on DMA operation. - * 0b1..Valid pending. - */ -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) - -#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) -#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) -/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is - * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. - * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. - * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. - */ -#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CTLSTAT */ -#define DMA_CHANNEL_CTLSTAT_COUNT (23U) - -/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ -/*! @{ */ - -#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) -#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) -/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor - * is valid and can potentially be acted upon, if all other activation criteria are fulfilled. - * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. - * 0b1..Valid. The current channel descriptor is considered valid. - */ -#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) - -#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) -#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) -/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current - * descriptor is exhausted. Reloading allows ping-pong and linked transfers. - * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. - * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) - -#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) -#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) -/*! SWTRIG - Software Trigger. - * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by - * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. - * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not - * be used with level triggering when TRIGBURST = 0. - */ -#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) - -#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) -#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) -/*! CLRTRIG - Clear Trigger. - * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. - * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted - */ -#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) - -#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) -#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) -/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between - * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By - * convention, interrupt A may be used when only one interrupt flag is needed. - * 0b0..No effect. - * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) - -#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) -#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) -/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between - * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By - * convention, interrupt A may be used when only one interrupt flag is needed. - * 0b0..No effect. - * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) - -#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) -#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) -/*! WIDTH - Transfer width used for this DMA channel. - * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). - * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). - * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). - * 0b11..Reserved. Reserved setting, do not use. - */ -#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) - -#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) -#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) -/*! SRCINC - Determines whether the source address is incremented for each DMA transfer. - * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. - * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is - * the usual case when the source is memory. - * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. - * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. - */ -#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) - -#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) -#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) -/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. - * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when - * the destination is a peripheral device. - * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. - * This is the usual case when the destination is memory. - * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. - * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. - */ -#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) - -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) -/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes - * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller - * uses this bit field during transfer to count down. Hence, it cannot be used by software to read - * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 - * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of - * 1,024 transfers will be performed. - */ -#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_XFERCFG */ -#define DMA_CHANNEL_XFERCFG_COUNT (23U) - - -/*! - * @} - */ /* end of group DMA_Register_Masks */ - - -/* DMA - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral DMA0 base address */ - #define DMA0_BASE (0x50082000u) - /** Peripheral DMA0 base address */ - #define DMA0_BASE_NS (0x40082000u) - /** Peripheral DMA0 base pointer */ - #define DMA0 ((DMA_Type *)DMA0_BASE) - /** Peripheral DMA0 base pointer */ - #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) - /** Peripheral DMA1 base address */ - #define DMA1_BASE (0x500A7000u) - /** Peripheral DMA1 base address */ - #define DMA1_BASE_NS (0x400A7000u) - /** Peripheral DMA1 base pointer */ - #define DMA1 ((DMA_Type *)DMA1_BASE) - /** Peripheral DMA1 base pointer */ - #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS { DMA0, DMA1 } - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } -#else - /** Peripheral DMA0 base address */ - #define DMA0_BASE (0x40082000u) - /** Peripheral DMA0 base pointer */ - #define DMA0 ((DMA_Type *)DMA0_BASE) - /** Peripheral DMA1 base address */ - #define DMA1_BASE (0x400A7000u) - /** Peripheral DMA1 base pointer */ - #define DMA1 ((DMA_Type *)DMA1_BASE) - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS { DMA0, DMA1 } -#endif -/** Interrupt vectors for the DMA peripheral type */ -#define DMA_IRQS { DMA0_IRQn, DMA1_IRQn } - -/*! - * @} - */ /* end of group DMA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer - * @{ - */ - -/** FLASH - Register Layout Typedef */ -typedef struct { - __O uint32_t CMD; /**< command register, offset: 0x0 */ - __O uint32_t EVENT; /**< event register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */ - __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */ - uint8_t RESERVED_1[104]; - __IO uint32_t DATAW[4]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_2[3912]; - __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */ - __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */ - __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ - __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ - __O uint32_t INT_CLR_STATUS; /**< Clear interrupt status bits, offset: 0xFE8 */ - __O uint32_t INT_SET_STATUS; /**< Set interrupt status bits, offset: 0xFEC */ - uint8_t RESERVED_3[12]; - __I uint32_t MODULE_ID; /**< Controller+Memory module identification, offset: 0xFFC */ -} FLASH_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_Register_Masks FLASH Register Masks - * @{ - */ - -/*! @name CMD - command register */ -/*! @{ */ - -#define FLASH_CMD_CMD_MASK (0xFFFFFFFFU) -#define FLASH_CMD_CMD_SHIFT (0U) -/*! CMD - command register. - */ -#define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK) -/*! @} */ - -/*! @name EVENT - event register */ -/*! @{ */ - -#define FLASH_EVENT_RST_MASK (0x1U) -#define FLASH_EVENT_RST_SHIFT (0U) -/*! RST - When bit is set, the controller and flash are reset. - */ -#define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK) - -#define FLASH_EVENT_WAKEUP_MASK (0x2U) -#define FLASH_EVENT_WAKEUP_SHIFT (1U) -/*! WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active. - */ -#define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK) - -#define FLASH_EVENT_ABORT_MASK (0x4U) -#define FLASH_EVENT_ABORT_SHIFT (2U) -/*! ABORT - When bit is set, a running program/erase command is aborted. - */ -#define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK) -/*! @} */ - -/*! @name STARTA - start (or only) address for next flash command */ -/*! @{ */ - -#define FLASH_STARTA_STARTA_MASK (0x3FFFFU) -#define FLASH_STARTA_STARTA_SHIFT (0U) -/*! STARTA - Address / Start address for commands that take an address (range) as a parameter. - */ -#define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK) -/*! @} */ - -/*! @name STOPA - end address for next flash command, if command operates on address ranges */ -/*! @{ */ - -#define FLASH_STOPA_STOPA_MASK (0x3FFFFU) -#define FLASH_STOPA_STOPA_SHIFT (0U) -/*! STOPA - Stop address for commands that take an address range as a parameter (the word specified - * by STOPA is included in the address range). - */ -#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK) -/*! @} */ - -/*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */ -/*! @{ */ - -#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU) -#define FLASH_DATAW_DATAW_SHIFT (0U) -#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK) -/*! @} */ - -/* The count of FLASH_DATAW */ -#define FLASH_DATAW_COUNT (4U) - -/*! @name INT_CLR_ENABLE - Clear interrupt enable bits */ -/*! @{ */ - -#define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U) -#define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U) -/*! FAIL - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - */ -#define FLASH_INT_CLR_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK) - -#define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U) -#define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U) -/*! ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - */ -#define FLASH_INT_CLR_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK) - -#define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U) -#define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U) -/*! DONE - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - */ -#define FLASH_INT_CLR_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK) - -#define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U) -#define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - */ -#define FLASH_INT_CLR_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_SET_ENABLE - Set interrupt enable bits */ -/*! @{ */ - -#define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U) -#define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U) -/*! FAIL - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - */ -#define FLASH_INT_SET_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK) - -#define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U) -#define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U) -/*! ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - */ -#define FLASH_INT_SET_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK) - -#define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U) -#define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U) -/*! DONE - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - */ -#define FLASH_INT_SET_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK) - -#define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U) -#define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - */ -#define FLASH_INT_SET_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_STATUS - Interrupt status bits */ -/*! @{ */ - -#define FLASH_INT_STATUS_FAIL_MASK (0x1U) -#define FLASH_INT_STATUS_FAIL_SHIFT (0U) -/*! FAIL - This status bit is set if execution of a (legal) command failed. - */ -#define FLASH_INT_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK) - -#define FLASH_INT_STATUS_ERR_MASK (0x2U) -#define FLASH_INT_STATUS_ERR_SHIFT (1U) -/*! ERR - This status bit is set if execution of an illegal command is detected. - */ -#define FLASH_INT_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK) - -#define FLASH_INT_STATUS_DONE_MASK (0x4U) -#define FLASH_INT_STATUS_DONE_SHIFT (2U) -/*! DONE - This status bit is set at the end of command execution. - */ -#define FLASH_INT_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK) - -#define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U) -#define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested - * read, or a speculative read, or reads performed by a controller command), a correctable or - * uncorrectable error is detected by ECC decoding logic. - */ -#define FLASH_INT_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_ENABLE - Interrupt enable bits */ -/*! @{ */ - -#define FLASH_INT_ENABLE_FAIL_MASK (0x1U) -#define FLASH_INT_ENABLE_FAIL_SHIFT (0U) -/*! FAIL - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - */ -#define FLASH_INT_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK) - -#define FLASH_INT_ENABLE_ERR_MASK (0x2U) -#define FLASH_INT_ENABLE_ERR_SHIFT (1U) -/*! ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - */ -#define FLASH_INT_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK) - -#define FLASH_INT_ENABLE_DONE_MASK (0x4U) -#define FLASH_INT_ENABLE_DONE_SHIFT (2U) -/*! DONE - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - */ -#define FLASH_INT_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK) - -#define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U) -#define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - */ -#define FLASH_INT_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_CLR_STATUS - Clear interrupt status bits */ -/*! @{ */ - -#define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U) -#define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U) -/*! FAIL - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - */ -#define FLASH_INT_CLR_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK) - -#define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U) -#define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U) -/*! ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - */ -#define FLASH_INT_CLR_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK) - -#define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U) -#define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U) -/*! DONE - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - */ -#define FLASH_INT_CLR_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK) - -#define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U) -#define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - */ -#define FLASH_INT_CLR_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_SET_STATUS - Set interrupt status bits */ -/*! @{ */ - -#define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U) -#define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U) -/*! FAIL - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - */ -#define FLASH_INT_SET_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK) - -#define FLASH_INT_SET_STATUS_ERR_MASK (0x2U) -#define FLASH_INT_SET_STATUS_ERR_SHIFT (1U) -/*! ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - */ -#define FLASH_INT_SET_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK) - -#define FLASH_INT_SET_STATUS_DONE_MASK (0x4U) -#define FLASH_INT_SET_STATUS_DONE_SHIFT (2U) -/*! DONE - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - */ -#define FLASH_INT_SET_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK) - -#define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U) -#define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - */ -#define FLASH_INT_SET_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK) -/*! @} */ - -/*! @name MODULE_ID - Controller+Memory module identification */ -/*! @{ */ - -#define FLASH_MODULE_ID_APERTURE_MASK (0xFFU) -#define FLASH_MODULE_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture i. - */ -#define FLASH_MODULE_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK) - -#define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U) -#define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision i. - */ -#define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK) - -#define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U) -#define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision i. - */ -#define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK) - -#define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U) -#define FLASH_MODULE_ID_ID_SHIFT (16U) -/*! ID - Identifier. - */ -#define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLASH_Register_Masks */ - - -/* FLASH - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH base address */ - #define FLASH_BASE (0x50034000u) - /** Peripheral FLASH base address */ - #define FLASH_BASE_NS (0x40034000u) - /** Peripheral FLASH base pointer */ - #define FLASH ((FLASH_Type *)FLASH_BASE) - /** Peripheral FLASH base pointer */ - #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS) - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS { FLASH_BASE } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS { FLASH } - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS_NS { FLASH_NS } -#else - /** Peripheral FLASH base address */ - #define FLASH_BASE (0x40034000u) - /** Peripheral FLASH base pointer */ - #define FLASH ((FLASH_Type *)FLASH_BASE) - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS { FLASH_BASE } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS { FLASH } -#endif - -/*! - * @} - */ /* end of group FLASH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_CFPA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CFPA_Peripheral_Access_Layer FLASH_CFPA Peripheral Access Layer - * @{ - */ - -/** FLASH_CFPA - Register Layout Typedef */ -typedef struct { - __IO uint32_t HEADER; /**< , offset: 0x0 */ - __IO uint32_t VERSION; /**< , offset: 0x4 */ - __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */ - __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */ - __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */ - uint8_t RESERVED_0[4]; - __IO uint32_t ROTKH_REVOKE; /**< , offset: 0x18 */ - __IO uint32_t VENDOR_USAGE; /**< , offset: 0x1C */ - __IO uint32_t DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */ - __IO uint32_t DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */ - __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */ - __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */ - union { /* offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< , array offset: 0x30, array step: 0x4 */ - struct { /* offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< , offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< , offset: 0x34 */ - __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< , array offset: 0x38, array step: 0x4 */ - } PRINCE_REGION0_IV_CODE_CORE; - }; - union { /* offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< , array offset: 0x68, array step: 0x4 */ - struct { /* offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< , offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< , offset: 0x6C */ - __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< , array offset: 0x70, array step: 0x4 */ - } PRINCE_REGION1_IV_CODE_CORE; - }; - union { /* offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< , array offset: 0xA0, array step: 0x4 */ - struct { /* offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< , offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< , offset: 0xA4 */ - __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< , array offset: 0xA8, array step: 0x4 */ - } PRINCE_REGION2_IV_CODE_CORE; - }; - uint8_t RESERVED_1[40]; - __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ - __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ -} FLASH_CFPA_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_CFPA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CFPA_Register_Masks FLASH_CFPA Register Masks - * @{ - */ - -/*! @name HEADER - */ -/*! @{ */ - -#define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_HEADER_FIELD_SHIFT (0U) -#define FLASH_CFPA_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK) -/*! @} */ - -/*! @name VERSION - */ -/*! @{ */ - -#define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_VERSION_FIELD_SHIFT (0U) -#define FLASH_CFPA_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK) -/*! @} */ - -/*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */ -/*! @{ */ - -#define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U) -#define FLASH_CFPA_S_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK) -/*! @} */ - -/*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */ -/*! @{ */ - -#define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U) -#define FLASH_CFPA_NS_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK) -/*! @} */ - -/*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */ -/*! @{ */ - -#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U) -#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK) -/*! @} */ - -/*! @name ROTKH_REVOKE - */ -/*! @{ */ - -#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U) -/*! RoTK0_EN - RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK) - -#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U) -/*! RoTK1_EN - RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK) - -#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U) -/*! RoTK2_EN - RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK) - -#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK (0xC0U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT (6U) -/*! RoTK3_EN - RoT Key 3 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK) -/*! @} */ - -/*! @name VENDOR_USAGE - */ -/*! @{ */ - -#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU) -#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U) -/*! DBG_VENDOR_USAGE - DBG_VENDOR_USAGE. - */ -#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK) - -#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ -/*! @{ */ - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_ME_CMD_EN_MASK (0x80U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_ME_CMD_EN_SHIFT (7U) -/*! FA_ME_CMD_EN - FA Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_ME_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) -/*! UUID_CHECK - Enforce UUID match during Debug authentication. - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ -/*! @{ */ - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_ME_CMD_EN_MASK (0x80U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_ME_CMD_EN_SHIFT (7U) -/*! FA_ME_CMD_EN - FA Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_ME_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */ -/*! @{ */ - -#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK) -/*! @} */ - -/*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */ -/*! @{ */ - -#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U) -#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_IV_CODE - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */ -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U) - -/*! @name PRINCE_REGION0_IV_HEADER0 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_IV_HEADER1 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK) - -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK) - -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_IV_BODY - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */ -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U) - -/*! @name PRINCE_REGION1_IV_CODE - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */ -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U) - -/*! @name PRINCE_REGION1_IV_HEADER0 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_IV_HEADER1 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK) - -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK) - -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_IV_BODY - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */ -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U) - -/*! @name PRINCE_REGION2_IV_CODE - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */ -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U) - -/*! @name PRINCE_REGION2_IV_HEADER0 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_IV_HEADER1 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK) - -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK) - -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_IV_BODY - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION2_IV_BODY */ -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_COUNT (12U) - -/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ -/*! @{ */ - -#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) -#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_CUSTOMER_DEFINED */ -#define FLASH_CFPA_CUSTOMER_DEFINED_COUNT (56U) - -/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ -/*! @{ */ - -#define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U) -#define FLASH_CFPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_SHA256_DIGEST */ -#define FLASH_CFPA_SHA256_DIGEST_COUNT (8U) - - -/*! - * @} - */ /* end of group FLASH_CFPA_Register_Masks */ - - -/* FLASH_CFPA - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH_CFPA0 base address */ - #define FLASH_CFPA0_BASE (0x1003E000u) - /** Peripheral FLASH_CFPA0 base address */ - #define FLASH_CFPA0_BASE_NS (0x3E000u) - /** Peripheral FLASH_CFPA0 base pointer */ - #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) - /** Peripheral FLASH_CFPA0 base pointer */ - #define FLASH_CFPA0_NS ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS) - /** Peripheral FLASH_CFPA1 base address */ - #define FLASH_CFPA1_BASE (0x1003E200u) - /** Peripheral FLASH_CFPA1 base address */ - #define FLASH_CFPA1_BASE_NS (0x3E200u) - /** Peripheral FLASH_CFPA1 base pointer */ - #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) - /** Peripheral FLASH_CFPA1 base pointer */ - #define FLASH_CFPA1_NS ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS) - /** Peripheral FLASH_CFPA_SCRATCH base address */ - #define FLASH_CFPA_SCRATCH_BASE (0x1003DE00u) - /** Peripheral FLASH_CFPA_SCRATCH base address */ - #define FLASH_CFPA_SCRATCH_BASE_NS (0x3DE00u) - /** Peripheral FLASH_CFPA_SCRATCH base pointer */ - #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) - /** Peripheral FLASH_CFPA_SCRATCH base pointer */ - #define FLASH_CFPA_SCRATCH_NS ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS) - /** Array initializer of FLASH_CFPA peripheral base addresses */ - #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } - /** Array initializer of FLASH_CFPA peripheral base pointers */ - #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } - /** Array initializer of FLASH_CFPA peripheral base addresses */ - #define FLASH_CFPA_BASE_ADDRS_NS { FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS } - /** Array initializer of FLASH_CFPA peripheral base pointers */ - #define FLASH_CFPA_BASE_PTRS_NS { FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS } -#else - /** Peripheral FLASH_CFPA0 base address */ - #define FLASH_CFPA0_BASE (0x3E000u) - /** Peripheral FLASH_CFPA0 base pointer */ - #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) - /** Peripheral FLASH_CFPA1 base address */ - #define FLASH_CFPA1_BASE (0x3E200u) - /** Peripheral FLASH_CFPA1 base pointer */ - #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) - /** Peripheral FLASH_CFPA_SCRATCH base address */ - #define FLASH_CFPA_SCRATCH_BASE (0x3DE00u) - /** Peripheral FLASH_CFPA_SCRATCH base pointer */ - #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) - /** Array initializer of FLASH_CFPA peripheral base addresses */ - #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } - /** Array initializer of FLASH_CFPA peripheral base pointers */ - #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } -#endif - -/*! - * @} - */ /* end of group FLASH_CFPA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_CMPA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CMPA_Peripheral_Access_Layer FLASH_CMPA Peripheral Access Layer - * @{ - */ - -/** FLASH_CMPA - Register Layout Typedef */ -typedef struct { - __IO uint32_t BOOT_CFG; /**< , offset: 0x0 */ - __IO uint32_t SPI_FLASH_CFG; /**< , offset: 0x4 */ - __IO uint32_t USB_ID; /**< , offset: 0x8 */ - __IO uint32_t SDIO_CFG; /**< , offset: 0xC */ - __IO uint32_t CC_SOCU_PIN; /**< , offset: 0x10 */ - __IO uint32_t CC_SOCU_DFLT; /**< , offset: 0x14 */ - __IO uint32_t VENDOR_USAGE; /**< , offset: 0x18 */ - __IO uint32_t SECURE_BOOT_CFG; /**< Secure boot configuration flags., offset: 0x1C */ - __IO uint32_t PRINCE_BASE_ADDR; /**< , offset: 0x20 */ - __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */ - __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */ - __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */ - __IO uint32_t XTAL_32KHZ_CAPABANK_TRIM; /**< Xtal 32kHz capabank triming., offset: 0x30 */ - __IO uint32_t XTAL_16MHZ_CAPABANK_TRIM; /**< Xtal 16MHz capabank triming., offset: 0x34 */ - __IO uint32_t FLASH_REMAP_SIZE; /**< This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB., offset: 0x38 */ - __IO uint32_t FLASH_REMAP_OFFSET; /**< This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB., offset: 0x3C */ - uint8_t RESERVED_0[16]; - __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */ - uint8_t RESERVED_1[144]; - __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ - __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ -} FLASH_CMPA_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_CMPA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CMPA_Register_Masks FLASH_CMPA Register Masks - * @{ - */ - -/*! @name BOOT_CFG - */ -/*! @{ */ - -#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U) -#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U) -/*! DEFAULT_ISP_MODE - Default ISP mode: - * 0b000..Auto ISP - * 0b001..USB_HID_ISP - * 0b010..UART ISP - * 0b011..SPI Slave ISP - * 0b100..I2C Slave ISP - * 0b111..Disable ISP fall through - */ -#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK) - -#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U) -#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U) -/*! BOOT_SPEED - Core clock: - * 0b00..Defined by NMPA.SYSTEM_SPEED_CODE - * 0b10..48MHz FRO - */ -#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK) - -#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U) -#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U) -/*! BOOT_FAILURE_PIN - GPIO port and pin number to use for indicating failure reason. The toggle - * rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO - * pin - */ -#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK) -/*! @} */ - -/*! @name SPI_FLASH_CFG - */ -/*! @{ */ - -#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK (0x1FU) -#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT (0U) -/*! SPI_RECOVERY_BOOT_EN - SPI flash recovery boot is enabled, if non-zero value is written to this field. - */ -#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK) -/*! @} */ - -/*! @name USB_ID - */ -/*! @{ */ - -#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU) -#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U) -#define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK) - -#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U) -#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U) -#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK) -/*! @} */ - -/*! @name SDIO_CFG - */ -/*! @{ */ - -#define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U) -#define FLASH_CMPA_SDIO_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK) -/*! @} */ - -/*! @name CC_SOCU_PIN - */ -/*! @{ */ - -#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK (0x1U) -#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK (0x2U) -#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) -#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK (0x8U) -#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK (0x10U) -#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_FA_ME_CMD_EN_MASK (0x80U) -#define FLASH_CMPA_CC_SOCU_PIN_FA_ME_CMD_EN_SHIFT (7U) -/*! FA_ME_CMD_EN - FA Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_FA_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_FA_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_FA_ME_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) -#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) -/*! UUID_CHECK - Enforce UUID match during Debug authentication. - */ -#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name CC_SOCU_DFLT - */ -/*! @{ */ - -#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK (0x1U) -#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK (0x2U) -#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) -#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) -#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK (0x10U) -#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_FA_ME_CMD_EN_MASK (0x80U) -#define FLASH_CMPA_CC_SOCU_DFLT_FA_ME_CMD_EN_SHIFT (7U) -/*! FA_ME_CMD_EN - FA Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_FA_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_FA_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_FA_ME_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name VENDOR_USAGE - */ -/*! @{ */ - -#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK (0xFFFF0000U) -#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT (16U) -/*! VENDOR_USAGE - Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area. - */ -#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK) -/*! @} */ - -/*! @name SECURE_BOOT_CFG - Secure boot configuration flags. */ -/*! @{ */ - -#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U) -#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U) -/*! RSA4K - Use RSA4096 keys only. - * 0b00..Allow RSA2048 and higher - * 0b01..RSA4096 only - * 0b10..RSA4096 only - * 0b11..RSA4096 only - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK (0xCU) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT (2U) -/*! DICE_INC_NXP_CFG - Include NXP area in DICE computation. - * 0b00..not included - * 0b01..included - * 0b10..included - * 0b11..included - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U) -/*! DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. - * 0b00..not included - * 0b01..included - * 0b10..included - * 0b11..included - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U) -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U) -/*! SKIP_DICE - Skip DICE computation - * 0b00..Enable DICE - * 0b01..Disable DICE - * 0b10..Disable DICE - * 0b11..Disable DICE - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U) -#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U) -/*! TZM_IMAGE_TYPE - TrustZone-M mode - * 0b00..TZ-M image mode is taken from application image header - * 0b01..TZ-M disabled image, boots to non-secure mode - * 0b10..TZ-M enabled image, boots to secure mode - * 0b11..TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U) -/*! BLOCK_SET_KEY - Block PUF key code generation - * 0b00..Allow PUF Key Code generation - * 0b01..Disable PUF Key Code generation - * 0b10..Disable PUF Key Code generation - * 0b11..Disable PUF Key Code generation - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U) -/*! BLOCK_ENROLL - Block PUF enrollement - * 0b00..Allow PUF enroll operation - * 0b01..Disable PUF enroll operation - * 0b10..Disable PUF enroll operation - * 0b11..Disable PUF enroll operation - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK (0xC000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT (14U) -/*! DICE_INC_SEC_EPOCH - Include security EPOCH in DICE - * 0b00..not included - * 0b01..included - * 0b10..included - * 0b11..included - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_BOOT_SEED_MASK (0x30000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_BOOT_SEED_SHIFT (16U) -/*! SKIP_BOOT_SEED - Skip boot seed computation - * 0b00..Enable BOOT_SEED - * 0b01..Disable BOOT_SEED - * 0b10..Disable BOOT_SEED - * 0b11..Disable BOOT_SEED - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_BOOT_SEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_BOOT_SEED_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_BOOT_SEED_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_NXP_CFG_MASK (0xC0000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_NXP_CFG_SHIFT (18U) -/*! BOOT_SEED_INC_NXP_CFG - Include NXP area in BOOT SEED computation - * 0b00..not included - * 0b01..included - * 0b10..included - * 0b11..included - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_NXP_CFG_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_CUST_CFG_MASK (0x300000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_CUST_CFG_SHIFT (20U) -/*! BOOT_SEED_CUST_CFG - Include CMPA area in BOOT SEED computation - * 0b00..not included - * 0b01..included - * 0b10..included - * 0b11..included - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_CUST_CFG_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_EPOCH_MASK (0xC00000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_EPOCH_SHIFT (22U) -/*! BOOT_SEED_INC_EPOCH - Include security epoch area in BOOT_SEED computation. - * 0b00..not included - * 0b01..included - * 0b10..included - * 0b11..included - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_EPOCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_EPOCH_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_EPOCH_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U) -/*! SEC_BOOT_EN - Secure boot enable - * 0b00..Plain image (internal flash with or without CRC) - * 0b01..Boot signed images. (internal flash, RSA signed) - * 0b10..Boot signed images. (internal flash, RSA signed) - * 0b11..Boot signed images. (internal flash, RSA signed) - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK) -/*! @} */ - -/*! @name PRINCE_BASE_ADDR - */ -/*! @{ */ - -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U) -/*! ADDR0_PRG - Programmable portion of the base address of region 0 - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U) -/*! ADDR1_PRG - Programmable portion of the base address of region 1 - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U) -/*! ADDR2_PRG - Programmable portion of the base address of region 2 - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0xC0000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (18U) -/*! LOCK_REG0 - Lock PRINCE region0 settings - * 0b00..Region is not locked - * 0b01..Region is locked - * 0b10..Region is locked - * 0b11..Region is locked - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0x300000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (20U) -/*! LOCK_REG1 - Lock PRINCE region1 settings - * 0b00..Region is not locked - * 0b01..Region is locked - * 0b10..Region is locked - * 0b11..Region is locked - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U) -/*! REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased together - * 0b00..Region is disabled - * 0b01..Region is enabled - * 0b10..Region is enabled - * 0b11..Region is enabled - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U) -/*! REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased together - * 0b00..Region is disabled - * 0b01..Region is enabled - * 0b10..Region is enabled - * 0b11..Region is enabled - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U) -/*! REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased together - * 0b00..Region is disabled - * 0b01..Region is enabled - * 0b10..Region is enabled - * 0b11..Region is enabled - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK) -/*! @} */ - -/*! @name PRINCE_SR_0 - Region 0, sub-region enable */ -/*! @{ */ - -#define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U) -#define FLASH_CMPA_PRINCE_SR_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_SR_1 - Region 1, sub-region enable */ -/*! @{ */ - -#define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U) -#define FLASH_CMPA_PRINCE_SR_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_SR_2 - Region 2, sub-region enable */ -/*! @{ */ - -#define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U) -#define FLASH_CMPA_PRINCE_SR_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK) -/*! @} */ - -/*! @name XTAL_32KHZ_CAPABANK_TRIM - Xtal 32kHz capabank triming. */ -/*! @{ */ - -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) -/*! TRIM_VALID - XTAL 32kHz capa bank trimmings - * 0b0..Capa Bank trimmings not valid. Default trimmings value are used - * 0b1..Capa Bank trimmings valid - */ -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK) - -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) -/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) - -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) -/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) - -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) -/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) -/*! @} */ - -/*! @name XTAL_16MHZ_CAPABANK_TRIM - Xtal 16MHz capabank triming. */ -/*! @{ */ - -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) -/*! TRIM_VALID - XTAL 16MHz capa bank trimmings - * 0b0..Capa Bank trimmings not valid. Default trimmings value are used - * 0b1..Capa Bank trimmings valid - */ -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK) - -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) -/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) - -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) -/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) - -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) -/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) -/*! @} */ - -/*! @name FLASH_REMAP_SIZE - This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB. */ -/*! @{ */ - -#define FLASH_CMPA_FLASH_REMAP_SIZE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_FLASH_REMAP_SIZE_FIELD_SHIFT (0U) -#define FLASH_CMPA_FLASH_REMAP_SIZE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_FLASH_REMAP_SIZE_FIELD_SHIFT)) & FLASH_CMPA_FLASH_REMAP_SIZE_FIELD_MASK) -/*! @} */ - -/*! @name FLASH_REMAP_OFFSET - This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB. */ -/*! @{ */ - -#define FLASH_CMPA_FLASH_REMAP_OFFSET_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_FLASH_REMAP_OFFSET_FIELD_SHIFT (0U) -#define FLASH_CMPA_FLASH_REMAP_OFFSET_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_FLASH_REMAP_OFFSET_FIELD_SHIFT)) & FLASH_CMPA_FLASH_REMAP_OFFSET_FIELD_MASK) -/*! @} */ - -/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0] */ -/*! @{ */ - -#define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U) -#define FLASH_CMPA_ROTKH_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CMPA_ROTKH */ -#define FLASH_CMPA_ROTKH_COUNT (8U) - -/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ -/*! @{ */ - -#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) -#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CMPA_CUSTOMER_DEFINED */ -#define FLASH_CMPA_CUSTOMER_DEFINED_COUNT (56U) - -/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ -/*! @{ */ - -#define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U) -#define FLASH_CMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CMPA_SHA256_DIGEST */ -#define FLASH_CMPA_SHA256_DIGEST_COUNT (8U) - - -/*! - * @} - */ /* end of group FLASH_CMPA_Register_Masks */ - - -/* FLASH_CMPA - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH_CMPA base address */ - #define FLASH_CMPA_BASE (0x1003E400u) - /** Peripheral FLASH_CMPA base address */ - #define FLASH_CMPA_BASE_NS (0x3E400u) - /** Peripheral FLASH_CMPA base pointer */ - #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) - /** Peripheral FLASH_CMPA base pointer */ - #define FLASH_CMPA_NS ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS) - /** Array initializer of FLASH_CMPA peripheral base addresses */ - #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } - /** Array initializer of FLASH_CMPA peripheral base pointers */ - #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } - /** Array initializer of FLASH_CMPA peripheral base addresses */ - #define FLASH_CMPA_BASE_ADDRS_NS { FLASH_CMPA_BASE_NS } - /** Array initializer of FLASH_CMPA peripheral base pointers */ - #define FLASH_CMPA_BASE_PTRS_NS { FLASH_CMPA_NS } -#else - /** Peripheral FLASH_CMPA base address */ - #define FLASH_CMPA_BASE (0x3E400u) - /** Peripheral FLASH_CMPA base pointer */ - #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) - /** Array initializer of FLASH_CMPA peripheral base addresses */ - #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } - /** Array initializer of FLASH_CMPA peripheral base pointers */ - #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } -#endif - -/*! - * @} - */ /* end of group FLASH_CMPA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_KEY_STORE Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_KEY_STORE_Peripheral_Access_Layer FLASH_KEY_STORE Peripheral Access Layer - * @{ - */ - -/** FLASH_KEY_STORE - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0 */ - __IO uint32_t HEADER; /**< Valid Key Sore Header : 0x95959595, offset: 0x0 */ - __IO uint32_t PUF_DISCHARGE_TIME_IN_MS; /**< puf discharge time in ms., offset: 0x4 */ - } KEY_STORE_HEADER; - __IO uint32_t ACTIVATION_CODE[298]; /**< ., array offset: 0x8, array step: 0x4 */ - union { /* offset: 0x4B0 */ - __IO uint32_t SBKEY_KEY_CODE[14]; /**< ., array offset: 0x4B0, array step: 0x4 */ - struct { /* offset: 0x4B0 */ - __IO uint32_t SBKEY_HEADER0; /**< ., offset: 0x4B0 */ - __IO uint32_t SBKEY_HEADER1; /**< ., offset: 0x4B4 */ - __IO uint32_t SBKEY_BODY[12]; /**< ., array offset: 0x4B8, array step: 0x4 */ - } SBKEY_KEY_CODE_CORE; - }; - union { /* offset: 0x4E8 */ - __IO uint32_t USER_KEK_KEY_CODE[14]; /**< ., array offset: 0x4E8, array step: 0x4 */ - struct { /* offset: 0x4E8 */ - __IO uint32_t USER_KEK_HEADER0; /**< ., offset: 0x4E8 */ - __IO uint32_t USER_KEK_HEADER1; /**< ., offset: 0x4EC */ - __IO uint32_t USER_KEK_BODY[12]; /**< ., array offset: 0x4F0, array step: 0x4 */ - } USER_KEK_KEY_CODE_CORE; - }; - union { /* offset: 0x520 */ - __IO uint32_t UDS_KEY_CODE[14]; /**< ., array offset: 0x520, array step: 0x4 */ - struct { /* offset: 0x520 */ - __IO uint32_t UDS_HEADER0; /**< ., offset: 0x520 */ - __IO uint32_t UDS_HEADER1; /**< ., offset: 0x524 */ - __IO uint32_t UDS_BODY[12]; /**< ., array offset: 0x528, array step: 0x4 */ - } UDS_KEY_CODE_CORE; - }; - union { /* offset: 0x558 */ - __IO uint32_t PRINCE_REGION0_KEY_CODE[14]; /**< ., array offset: 0x558, array step: 0x4 */ - struct { /* offset: 0x558 */ - __IO uint32_t PRINCE_REGION0_HEADER0; /**< ., offset: 0x558 */ - __IO uint32_t PRINCE_REGION0_HEADER1; /**< ., offset: 0x55C */ - __IO uint32_t PRINCE_REGION0_BODY[12]; /**< ., array offset: 0x560, array step: 0x4 */ - } PRINCE_REGION0_KEY_CODE_CORE; - }; - union { /* offset: 0x590 */ - __IO uint32_t PRINCE_REGION1_KEY_CODE[14]; /**< ., array offset: 0x590, array step: 0x4 */ - struct { /* offset: 0x590 */ - __IO uint32_t PRINCE_REGION1_HEADER0; /**< ., offset: 0x590 */ - __IO uint32_t PRINCE_REGION1_HEADER1; /**< ., offset: 0x594 */ - __IO uint32_t PRINCE_REGION1_BODY[12]; /**< ., array offset: 0x598, array step: 0x4 */ - } PRINCE_REGION1_KEY_CODE_CORE; - }; - union { /* offset: 0x5C8 */ - __IO uint32_t PRINCE_REGION2_KEY_CODE[14]; /**< ., array offset: 0x5C8, array step: 0x4 */ - struct { /* offset: 0x5C8 */ - __IO uint32_t PRINCE_REGION2_HEADER0; /**< ., offset: 0x5C8 */ - __IO uint32_t PRINCE_REGION2_HEADER1; /**< ., offset: 0x5CC */ - __IO uint32_t PRINCE_REGION2_BODY[12]; /**< ., array offset: 0x5D0, array step: 0x4 */ - } PRINCE_REGION2_KEY_CODE_CORE; - }; -} FLASH_KEY_STORE_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_KEY_STORE Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_KEY_STORE_Register_Masks FLASH_KEY_STORE Register Masks - * @{ - */ - -/*! @name HEADER - Valid Key Sore Header : 0x95959595 */ -/*! @{ */ - -#define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK) -/*! @} */ - -/*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */ -/*! @{ */ - -#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK) -/*! @} */ - -/*! @name ACTIVATION_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_ACTIVATION_CODE */ -#define FLASH_KEY_STORE_ACTIVATION_CODE_COUNT (298U) - -/*! @name SBKEY_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_SBKEY_KEY_CODE */ -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_COUNT (14U) - -/*! @name SBKEY_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name SBKEY_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name SBKEY_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_SBKEY_BODY */ -#define FLASH_KEY_STORE_SBKEY_BODY_COUNT (12U) - -/*! @name USER_KEK_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_USER_KEK_KEY_CODE */ -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_COUNT (14U) - -/*! @name USER_KEK_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name USER_KEK_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name USER_KEK_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_USER_KEK_BODY */ -#define FLASH_KEY_STORE_USER_KEK_BODY_COUNT (12U) - -/*! @name UDS_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_UDS_KEY_CODE */ -#define FLASH_KEY_STORE_UDS_KEY_CODE_COUNT (14U) - -/*! @name UDS_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name UDS_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name UDS_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_UDS_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_UDS_BODY */ -#define FLASH_KEY_STORE_UDS_BODY_COUNT (12U) - -/*! @name PRINCE_REGION0_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE */ -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_COUNT (14U) - -/*! @name PRINCE_REGION0_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION0_BODY */ -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_COUNT (12U) - -/*! @name PRINCE_REGION1_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE */ -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_COUNT (14U) - -/*! @name PRINCE_REGION1_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION1_BODY */ -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_COUNT (12U) - -/*! @name PRINCE_REGION2_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE */ -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_COUNT (14U) - -/*! @name PRINCE_REGION2_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION2_BODY */ -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_COUNT (12U) - - -/*! - * @} - */ /* end of group FLASH_KEY_STORE_Register_Masks */ - - -/* FLASH_KEY_STORE - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH_KEY_STORE base address */ - #define FLASH_KEY_STORE_BASE (0x1003E600u) - /** Peripheral FLASH_KEY_STORE base address */ - #define FLASH_KEY_STORE_BASE_NS (0x3E600u) - /** Peripheral FLASH_KEY_STORE base pointer */ - #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) - /** Peripheral FLASH_KEY_STORE base pointer */ - #define FLASH_KEY_STORE_NS ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS) - /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ - #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } - /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ - #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } - /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ - #define FLASH_KEY_STORE_BASE_ADDRS_NS { FLASH_KEY_STORE_BASE_NS } - /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ - #define FLASH_KEY_STORE_BASE_PTRS_NS { FLASH_KEY_STORE_NS } -#else - /** Peripheral FLASH_KEY_STORE base address */ - #define FLASH_KEY_STORE_BASE (0x3E600u) - /** Peripheral FLASH_KEY_STORE base pointer */ - #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) - /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ - #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } - /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ - #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } -#endif - -/*! - * @} - */ /* end of group FLASH_KEY_STORE_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_NMPA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_NMPA_Peripheral_Access_Layer FLASH_NMPA Peripheral Access Layer - * @{ - */ - -/** FLASH_NMPA - Register Layout Typedef */ -typedef struct { - union { /* offset: 0x0 */ - struct { /* offset: 0x0 */ - __IO uint32_t GPO0_0; /**< GPO0 register 0 description, offset: 0x0 */ - __IO uint32_t GPO0_1; /**< GPO0 register 1 description, offset: 0x4 */ - __IO uint32_t GPO0_2; /**< GPO0 register 2 description, offset: 0x8 */ - __IO uint32_t GPO0_3; /**< GPO0 register 3 description, offset: 0xC */ - } GPO0; - __IO uint32_t GPO0_ARRAY[4]; /**< GPO0 array description, array offset: 0x0, array step: 0x4 */ - }; - union { /* offset: 0x10 */ - struct { /* offset: 0x10 */ - __IO uint32_t GPO1_0; /**< GPO1 register 0 description, offset: 0x10 */ - __IO uint32_t GPO1_1; /**< GPO1 register 1 description, offset: 0x14 */ - __IO uint32_t GPO1_2; /**< GPO1 register 2 description, offset: 0x18 */ - __IO uint32_t GPO1_3; /**< GPO1 register 3 description, offset: 0x1C */ - } GPO1; - __IO uint32_t GPO1_ARRAY[4]; /**< GPO1 array description, array offset: 0x10, array step: 0x4 */ - }; - union { /* offset: 0x20 */ - struct { /* offset: 0x20 */ - __IO uint32_t GPO2_0; /**< GPO2 register 0 description, offset: 0x20 */ - __IO uint32_t GPO2_1; /**< GPO2 register 1 description, offset: 0x24 */ - __IO uint32_t GPO2_2; /**< GPO2 register 2 description, offset: 0x28 */ - __IO uint32_t GPO2_3; /**< GPO2 register 3 description, offset: 0x2C */ - } GPO2; - __IO uint32_t GPO2_ARRAY[4]; /**< GPO2 array description, array offset: 0x20, array step: 0x4 */ - }; - union { /* offset: 0x30 */ - struct { /* offset: 0x30 */ - __IO uint32_t GPO3_0; /**< GPO3 register 0 description, offset: 0x30 */ - __IO uint32_t GPO3_1; /**< GPO3 register 1 description, offset: 0x34 */ - __IO uint32_t GPO3_2; /**< GPO3 register 2 description, offset: 0x38 */ - __IO uint32_t GPO3_3; /**< GPO3 register 3 description, offset: 0x3C */ - } GPO3; - __IO uint32_t GPO3_ARRAY[4]; /**< GPO3 array description, array offset: 0x30, array step: 0x4 */ - }; - union { /* offset: 0x40 */ - struct { /* offset: 0x40 */ - __IO uint32_t GPO_CHECKSUM_0; /**< checksum of the GPO data in words 0, offset: 0x40 */ - __IO uint32_t GPO_CHECKSUM_1; /**< checksum of the GPO data in words 1, offset: 0x44 */ - __IO uint32_t GPO_CHECKSUM_2; /**< checksum of the GPO data in words 2, offset: 0x48 */ - __IO uint32_t GPO_CHECKSUM_3; /**< checksum of the GPO data in words 3, offset: 0x4C */ - } GPO_CHECKSUM; - __IO uint32_t GPO_CHECKSUM_ARRAY[4]; /**< checksum of the GPO data in words [3:0], array offset: 0x40, array step: 0x4 */ - }; - union { /* offset: 0x50 */ - struct { /* offset: 0x50 */ - __IO uint32_t FINAL_TEST_BATCH_ID_0; /**< , offset: 0x50 */ - __IO uint32_t FINAL_TEST_BATCH_ID_1; /**< , offset: 0x54 */ - __IO uint32_t FINAL_TEST_BATCH_ID_2; /**< , offset: 0x58 */ - __IO uint32_t FINAL_TEST_BATCH_ID_3; /**< , offset: 0x5C */ - } FINAL_TEST_BATCH_ID; - __IO uint32_t FINAL_TEST_BATCH_ID_ARRAY[4]; /**< , array offset: 0x50, array step: 0x4 */ - }; - __IO uint32_t DEVICE_TYPE; /**< , offset: 0x60 */ - __IO uint32_t FINAL_TEST_PROGRAM_VERSION; /**< , offset: 0x64 */ - __IO uint32_t FINAL_TEST_DATE; /**< , offset: 0x68 */ - __IO uint32_t FINAL_TEST_TIME; /**< , offset: 0x6C */ - union { /* offset: 0x70 */ - struct { /* offset: 0x70 */ - __IO uint32_t UUID_0; /**< , offset: 0x70 */ - __IO uint32_t UUID_1; /**< , offset: 0x74 */ - __IO uint32_t UUID_2; /**< , offset: 0x78 */ - __IO uint32_t UUID_3; /**< , offset: 0x7C */ - } UUID; - __IO uint32_t UUID_ARRAY[4]; /**< , array offset: 0x70, array step: 0x4 */ - }; - __IO uint32_t WAFER_TEST1_PROGRAM_VERSION; /**< , offset: 0x80 */ - __IO uint32_t WAFER_TEST1_DATE; /**< , offset: 0x84 */ - __IO uint32_t WAFER_TEST1_TIME; /**< , offset: 0x88 */ - uint8_t RESERVED_0[4]; - __IO uint32_t WAFER_TEST2_PROGRAM_VERSION; /**< , offset: 0x90 */ - __IO uint32_t WAFER_TEST2_DATE; /**< , offset: 0x94 */ - __IO uint32_t WAFER_TEST2_TIME; /**< , offset: 0x98 */ - __IO uint32_t USBCFG; /**< , offset: 0x9C */ - __IO uint32_t PERIPHENCFG; /**< , offset: 0xA0 */ - __IO uint32_t RAMSIZECFG; /**< , offset: 0xA4 */ - __IO uint32_t FLASHSIZECFG; /**< , offset: 0xA8 */ - uint8_t RESERVED_1[4]; - __IO uint32_t RINGO_0; /**< , offset: 0xB0 */ - __IO uint32_t RINGO_1; /**< , offset: 0xB4 */ - __IO uint32_t RINGO_2; /**< , offset: 0xB8 */ - uint8_t RESERVED_2[4]; - __IO uint32_t FRO_192MHZ; /**< , offset: 0xC0 */ - uint8_t RESERVED_3[4]; - __IO uint32_t XO_32MHZ; /**< , offset: 0xC8 */ - __IO uint32_t XO_32KHZ; /**< , offset: 0xCC */ - __IO uint32_t FRO_1MHZ; /**< , offset: 0xD0 */ - uint8_t RESERVED_4[4]; - union { /* offset: 0xD8 */ - struct { /* offset: 0xD8 */ - __IO uint32_t DCDC_POWER_PROFILE_HIGH_0; /**< , offset: 0xD8 */ - __IO uint32_t DCDC_POWER_PROFILE_HIGH_1; /**< , offset: 0xDC */ - } DCDC_POWER_PROFILE_HIGH; - __IO uint32_t DCDC_POWER_PROFILE_HIGH_ARRAY[2]; /**< , array offset: 0xD8, array step: 0x4 */ - }; - union { /* offset: 0xE0 */ - struct { /* offset: 0xE0 */ - __IO uint32_t DCDC_POWER_PROFILE_LOW_0; /**< , offset: 0xE0 */ - __IO uint32_t DCDC_POWER_PROFILE_LOW_1; /**< , offset: 0xE4 */ - } DCDC_POWER_PROFILE_LOW; - __IO uint32_t DCDC_POWER_PROFILE_LOW_ARRAY[2]; /**< , array offset: 0xE0, array step: 0x4 */ - }; - union { /* offset: 0xE8 */ - struct { /* offset: 0xE8 */ - __IO uint32_t DCDC_POWER_PROFILE_MEDIUM_0; /**< , offset: 0xE8 */ - __IO uint32_t DCDC_POWER_PROFILE_MEDIUM_1; /**< , offset: 0xEC */ - } DCDC_POWER_PROFILE_MEDIUM; - __IO uint32_t DCDC_POWER_PROFILE_MEDIUM_ARRAY[2]; /**< , array offset: 0xE8, array step: 0x4 */ - }; - __IO uint32_t BOD; /**< , offset: 0xF0 */ - __IO uint32_t LDO_AO; /**< , offset: 0xF4 */ - __IO uint32_t SDIO_DELAY; /**< , offset: 0xF8 */ - uint8_t RESERVED_5[4]; - union { /* offset: 0x100 */ - struct { /* offset: 0x100 */ - __IO uint32_t AUX_BIAS_CURVE_AMBIENT_0; /**< , offset: 0x100 */ - __IO uint32_t AUX_BIAS_CURVE_AMBIENT_1; /**< , offset: 0x104 */ - __IO uint32_t AUX_BIAS_CURVE_AMBIENT_2; /**< , offset: 0x108 */ - __IO uint32_t AUX_BIAS_CURVE_AMBIENT_3; /**< , offset: 0x10C */ - } AUX_BIAS_CURVE_AMBIENT; - __IO uint32_t AUX_BIAS_CURVE_AMBIENT_ARRAY[4]; /**< Aux Bias Curve Ambient (30degC), array offset: 0x100, array step: 0x4 */ - }; - union { /* offset: 0x110 */ - struct { /* offset: 0x110 */ - __IO uint32_t AUX_BIAS_CURVE_TEMP_0; /**< , offset: 0x110 */ - __IO uint32_t AUX_BIAS_CURVE_TEMP_1; /**< , offset: 0x114 */ - __IO uint32_t AUX_BIAS_CURVE_TEMP_2; /**< , offset: 0x118 */ - __IO uint32_t AUX_BIAS_CURVE_TEMP_3; /**< , offset: 0x11C */ - } AUX_BIAS_CURVE_TEMP; - __IO uint32_t AUX_BIAS_CURVE_TEMP_ARRAY[4]; /**< Aux Bias Curve TEMP (105degC), array offset: 0x110, array step: 0x4 */ - }; - __IO uint32_t TEMP_SENS_VBE1VBE8_REF_1; /**< , offset: 0x120 */ - __IO uint32_t TEMP_SENS_VBE1VBE8_REF_2; /**< , offset: 0x124 */ - __IO uint32_t TEMP_SENS_SLOPE; /**< , offset: 0x128 */ - __IO uint32_t TEMP_SENS_OFFSET; /**< , offset: 0x12C */ - union { /* offset: 0x130 */ - struct { /* offset: 0x130 */ - __IO uint32_t PVT_MONITOR_0_RINGO; /**< , offset: 0x130 */ - __IO uint32_t PVT_MONITOR_0_DELAYS_LSB; /**< , offset: 0x134 */ - __IO uint32_t PVT_MONITOR_0_DELAYS_MSB; /**< , offset: 0x138 */ - } PVT_MONITOR_0; - __IO uint32_t PVT_MONITOR_0_ARRAY[3]; /**< , array offset: 0x130, array step: 0x4 */ - }; - uint8_t RESERVED_6[4]; - union { /* offset: 0x140 */ - struct { /* offset: 0x140 */ - __IO uint32_t PVT_MONITOR_1_RINGO; /**< , offset: 0x140 */ - __IO uint32_t PVT_MONITOR_1_DELAYS_LSB; /**< , offset: 0x144 */ - __IO uint32_t PVT_MONITOR_1_DELAYS_MSB; /**< , offset: 0x148 */ - } PVT_MONITOR_1; - __IO uint32_t PVT_MONITOR_1_ARRAY[3]; /**< , array offset: 0x140, array step: 0x4 */ - }; - __IO uint32_t NXP_DEVICE_PRIVATE_KEY[13]; /**< , array offset: 0x14C, array step: 0x4 */ - __IO uint32_t NXP_DEVICE_CERTIFICATE_0[4]; /**< NXP Device Certificate (ECDSA_sign - r[255:128]), array offset: 0x180, array step: 0x4 */ - __IO uint32_t NXP_DEVICE_CERTIFICATE_1[4]; /**< NXP Device Certificate (ECDSA_sign - r[127:0]), array offset: 0x190, array step: 0x4 */ - __IO uint32_t NXP_DEVICE_CERTIFICATE_2[4]; /**< NXP Device Certificate (ECDSA_sign - s[255:128]), array offset: 0x1A0, array step: 0x4 */ - __IO uint32_t NXP_DEVICE_CERTIFICATE_3[4]; /**< NXP Device Certificate (ECDSA_sign - s[127:0]), array offset: 0x1B0, array step: 0x4 */ - __IO uint32_t SHA256_DIGEST[8]; /**< SHA-256 DIGEST (9EC00 - 9FDBC) ROM Patch Area + NXP Area (IMPORTANT NOTE: Pages used for Repair (N-8 to N-3) are excluded from the computation) SHA256_DIGEST0 for DIGEST[31:0]..SHA-256 DIGEST (9EC00 - 9FDBC) ROM Patch Area + NXP Area (IMPORTANT NOTE: Pages used for Repair (N-8 to N-3) are excluded from the computation) SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1C0, array step: 0x4 */ - union { /* offset: 0x1E0 */ - struct { /* offset: 0x1E0 */ - __IO uint32_t ECID_BACKUP_0; /**< , offset: 0x1E0 */ - __IO uint32_t ECID_BACKUP_1; /**< , offset: 0x1E4 */ - __IO uint32_t ECID_BACKUP_2; /**< , offset: 0x1E8 */ - __IO uint32_t ECID_BACKUP_3; /**< , offset: 0x1EC */ - } ECID_BACKUP; - __IO uint32_t ECID_BACKUP_ARRAY[4]; /**< ECID backup (the original is in page n-1), array offset: 0x1E0, array step: 0x4 */ - }; - uint32_t CHECKSUM[4]; /**< Checksum of the whole page, array offset: 0x1F0, array step: 0x4 */ - uint8_t RESERVED_7[2732]; - __IO uint32_t DIS_ROM_HIDING; /**< , offset: 0xCAC */ - uint8_t RESERVED_8[12]; - __IO uint32_t PUF_SRAM; /**< , offset: 0xCBC */ -} FLASH_NMPA_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_NMPA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_NMPA_Register_Masks FLASH_NMPA Register Masks - * @{ - */ - -/*! @name GPO0_0 - GPO0 register 0 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO0_0_FRO_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_GPO0_0_FRO_TRIM_VALID_SHIFT (0U) -#define FLASH_NMPA_GPO0_0_FRO_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_0_FRO_TRIM_VALID_SHIFT)) & FLASH_NMPA_GPO0_0_FRO_TRIM_VALID_MASK) - -#define FLASH_NMPA_GPO0_0_FRO32K_NTAT_MASK (0xEU) -#define FLASH_NMPA_GPO0_0_FRO32K_NTAT_SHIFT (1U) -#define FLASH_NMPA_GPO0_0_FRO32K_NTAT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_0_FRO32K_NTAT_SHIFT)) & FLASH_NMPA_GPO0_0_FRO32K_NTAT_MASK) - -#define FLASH_NMPA_GPO0_0_FRO32K_PTAT_MASK (0x70U) -#define FLASH_NMPA_GPO0_0_FRO32K_PTAT_SHIFT (4U) -#define FLASH_NMPA_GPO0_0_FRO32K_PTAT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_0_FRO32K_PTAT_SHIFT)) & FLASH_NMPA_GPO0_0_FRO32K_PTAT_MASK) - -#define FLASH_NMPA_GPO0_0_FRO32K_CAPCAL_MASK (0xFF80U) -#define FLASH_NMPA_GPO0_0_FRO32K_CAPCAL_SHIFT (7U) -#define FLASH_NMPA_GPO0_0_FRO32K_CAPCAL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_0_FRO32K_CAPCAL_SHIFT)) & FLASH_NMPA_GPO0_0_FRO32K_CAPCAL_MASK) - -#define FLASH_NMPA_GPO0_0_FIELD_MASK (0xFFFF0000U) -#define FLASH_NMPA_GPO0_0_FIELD_SHIFT (16U) -#define FLASH_NMPA_GPO0_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_0_FIELD_SHIFT)) & FLASH_NMPA_GPO0_0_FIELD_MASK) -/*! @} */ - -/*! @name GPO0_1 - GPO0 register 1 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO0_1_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO0_1_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO0_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_1_FIELD_SHIFT)) & FLASH_NMPA_GPO0_1_FIELD_MASK) -/*! @} */ - -/*! @name GPO0_2 - GPO0 register 2 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO0_2_SYSTEM_SPEED_CODE_MASK (0x3U) -#define FLASH_NMPA_GPO0_2_SYSTEM_SPEED_CODE_SHIFT (0U) -/*! SYSTEM_SPEED_CODE - 00 : FRO12MHz 01 : FRO24MHz 10 : FRO48MHz 11 : FRO96MHz - */ -#define FLASH_NMPA_GPO0_2_SYSTEM_SPEED_CODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_2_SYSTEM_SPEED_CODE_SHIFT)) & FLASH_NMPA_GPO0_2_SYSTEM_SPEED_CODE_MASK) - -#define FLASH_NMPA_GPO0_2_FLASH_CTRL_OPMODE_MASK (0xCU) -#define FLASH_NMPA_GPO0_2_FLASH_CTRL_OPMODE_SHIFT (2U) -/*! FLASH_CTRL_OPMODE - 00 : Delay Line 01 : RCLK (back up clock) 10 : PCLK (back up clock) - */ -#define FLASH_NMPA_GPO0_2_FLASH_CTRL_OPMODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_2_FLASH_CTRL_OPMODE_SHIFT)) & FLASH_NMPA_GPO0_2_FLASH_CTRL_OPMODE_MASK) - -#define FLASH_NMPA_GPO0_2_FIELD_MASK (0xFFFFFFF0U) -#define FLASH_NMPA_GPO0_2_FIELD_SHIFT (4U) -#define FLASH_NMPA_GPO0_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_2_FIELD_SHIFT)) & FLASH_NMPA_GPO0_2_FIELD_MASK) -/*! @} */ - -/*! @name GPO0_3 - GPO0 register 3 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO0_3_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO0_3_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO0_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_3_FIELD_SHIFT)) & FLASH_NMPA_GPO0_3_FIELD_MASK) -/*! @} */ - -/*! @name GPO0_ARRAY - GPO0 array description */ -/*! @{ */ - -#define FLASH_NMPA_GPO0_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO0_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO0_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_GPO0_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_GPO0_ARRAY */ -#define FLASH_NMPA_GPO0_ARRAY_COUNT (4U) - -/*! @name GPO1_0 - GPO1 register 0 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO1_0_FINAL_TEST_NOT_DONE_MASK (0xFU) -#define FLASH_NMPA_GPO1_0_FINAL_TEST_NOT_DONE_SHIFT (0U) -/*! FINAL_TEST_NOT_DONE - FINAL_TEST_NOT_DONE[3:0]: 1010 : Final Test Not Done. All Other values: Final Test Done. - */ -#define FLASH_NMPA_GPO1_0_FINAL_TEST_NOT_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_FINAL_TEST_NOT_DONE_SHIFT)) & FLASH_NMPA_GPO1_0_FINAL_TEST_NOT_DONE_MASK) - -#define FLASH_NMPA_GPO1_0_PARTCONFIG_MASK (0x7F0U) -#define FLASH_NMPA_GPO1_0_PARTCONFIG_SHIFT (4U) -/*! PARTCONFIG - Device type number. (E.g : LPC5569 stored as 69 decimal) - */ -#define FLASH_NMPA_GPO1_0_PARTCONFIG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_PARTCONFIG_SHIFT)) & FLASH_NMPA_GPO1_0_PARTCONFIG_MASK) - -#define FLASH_NMPA_GPO1_0_DEVICE_TYPE_SEC_MASK (0x800U) -#define FLASH_NMPA_GPO1_0_DEVICE_TYPE_SEC_SHIFT (11U) -/*! DEVICE_TYPE_SEC - Security device type: 0: LPC55xxx (Non Secure Familly) 1: LPC55Sxxx (Secure Familly) - */ -#define FLASH_NMPA_GPO1_0_DEVICE_TYPE_SEC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_DEVICE_TYPE_SEC_SHIFT)) & FLASH_NMPA_GPO1_0_DEVICE_TYPE_SEC_MASK) - -#define FLASH_NMPA_GPO1_0_SRAM_SIZE_MASK (0xF000U) -#define FLASH_NMPA_GPO1_0_SRAM_SIZE_SHIFT (12U) -/*! SRAM_SIZE - SRAM_SIZE[3:0]: (For Niobe4) 0000 : 320 KB 0001 : 256 KB 0010 : 144 KB 0011 : 80 KB - * (For Niobe4 Mini) 0100 : 96 KB 0101 : 80 KB 0110 : 64 KB 0111 : 48 KB All others : RESERVED - */ -#define FLASH_NMPA_GPO1_0_SRAM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_SRAM_SIZE_SHIFT)) & FLASH_NMPA_GPO1_0_SRAM_SIZE_MASK) - -#define FLASH_NMPA_GPO1_0_CPU0_SECURITY_EXTENSION_DISABLE_MASK (0xF0000U) -#define FLASH_NMPA_GPO1_0_CPU0_SECURITY_EXTENSION_DISABLE_SHIFT (16U) -/*! CPU0_SECURITY_EXTENSION_DISABLE - CPU0_SECURITY_EXTENSION_DISABLE[3:0]: 1010 : CPU0 Security - * Extension is disabled. All Other values: CPU0 Security Extension is enabled. - */ -#define FLASH_NMPA_GPO1_0_CPU0_SECURITY_EXTENSION_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_CPU0_SECURITY_EXTENSION_DISABLE_SHIFT)) & FLASH_NMPA_GPO1_0_CPU0_SECURITY_EXTENSION_DISABLE_MASK) - -#define FLASH_NMPA_GPO1_0_FIELD_MASK (0xF00000U) -#define FLASH_NMPA_GPO1_0_FIELD_SHIFT (20U) -#define FLASH_NMPA_GPO1_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_FIELD_SHIFT)) & FLASH_NMPA_GPO1_0_FIELD_MASK) - -#define FLASH_NMPA_GPO1_0_ROM_REVISION_MINOR_MASK (0xF000000U) -#define FLASH_NMPA_GPO1_0_ROM_REVISION_MINOR_SHIFT (24U) -/*! ROM_REVISION_MINOR - ROM Revision-Minor [3:0] - */ -#define FLASH_NMPA_GPO1_0_ROM_REVISION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_ROM_REVISION_MINOR_SHIFT)) & FLASH_NMPA_GPO1_0_ROM_REVISION_MINOR_MASK) - -#define FLASH_NMPA_GPO1_0_METAL_REVISION_ID_MASK (0xF0000000U) -#define FLASH_NMPA_GPO1_0_METAL_REVISION_ID_SHIFT (28U) -/*! METAL_REVISION_ID - METAL REVISION ID[3:0] - */ -#define FLASH_NMPA_GPO1_0_METAL_REVISION_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_METAL_REVISION_ID_SHIFT)) & FLASH_NMPA_GPO1_0_METAL_REVISION_ID_MASK) -/*! @} */ - -/*! @name GPO1_1 - GPO1 register 1 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO1_1_ROM_PATCH_VERSION_MASK (0xFU) -#define FLASH_NMPA_GPO1_1_ROM_PATCH_VERSION_SHIFT (0U) -/*! ROM_PATCH_VERSION - ROM Patch Version [3:0] - */ -#define FLASH_NMPA_GPO1_1_ROM_PATCH_VERSION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_1_ROM_PATCH_VERSION_SHIFT)) & FLASH_NMPA_GPO1_1_ROM_PATCH_VERSION_MASK) - -#define FLASH_NMPA_GPO1_1_CUSTOMER_REVISION_ID_MASK (0xF0U) -#define FLASH_NMPA_GPO1_1_CUSTOMER_REVISION_ID_SHIFT (4U) -/*! CUSTOMER_REVISION_ID - CUSTOMER REVISION ID[3:0] - */ -#define FLASH_NMPA_GPO1_1_CUSTOMER_REVISION_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_1_CUSTOMER_REVISION_ID_SHIFT)) & FLASH_NMPA_GPO1_1_CUSTOMER_REVISION_ID_MASK) - -#define FLASH_NMPA_GPO1_1_FIELD_MASK (0xFFFFFF00U) -#define FLASH_NMPA_GPO1_1_FIELD_SHIFT (8U) -#define FLASH_NMPA_GPO1_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_1_FIELD_SHIFT)) & FLASH_NMPA_GPO1_1_FIELD_MASK) -/*! @} */ - -/*! @name GPO1_2 - GPO1 register 2 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO1_2_HVST_MASK (0x1U) -#define FLASH_NMPA_GPO1_2_HVST_SHIFT (0U) -/*! HVST - High Voltage Stress: 0=not done; 1=done. - */ -#define FLASH_NMPA_GPO1_2_HVST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_2_HVST_SHIFT)) & FLASH_NMPA_GPO1_2_HVST_MASK) - -#define FLASH_NMPA_GPO1_2_FIELD_MASK (0xFFFFFFFEU) -#define FLASH_NMPA_GPO1_2_FIELD_SHIFT (1U) -#define FLASH_NMPA_GPO1_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_2_FIELD_SHIFT)) & FLASH_NMPA_GPO1_2_FIELD_MASK) -/*! @} */ - -/*! @name GPO1_3 - GPO1 register 3 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO1_3_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO1_3_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO1_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_3_FIELD_SHIFT)) & FLASH_NMPA_GPO1_3_FIELD_MASK) -/*! @} */ - -/*! @name GPO1_ARRAY - GPO1 array description */ -/*! @{ */ - -#define FLASH_NMPA_GPO1_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO1_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO1_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_GPO1_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_GPO1_ARRAY */ -#define FLASH_NMPA_GPO1_ARRAY_COUNT (4U) - -/*! @name GPO2_0 - GPO2 register 0 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO2_0_USBHS_PHY_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_GPO2_0_USBHS_PHY_TRIM_VALID_SHIFT (0U) -#define FLASH_NMPA_GPO2_0_USBHS_PHY_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_USBHS_PHY_TRIM_VALID_SHIFT)) & FLASH_NMPA_GPO2_0_USBHS_PHY_TRIM_VALID_MASK) - -#define FLASH_NMPA_GPO2_0_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0x6U) -#define FLASH_NMPA_GPO2_0_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (1U) -#define FLASH_NMPA_GPO2_0_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & FLASH_NMPA_GPO2_0_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK) - -#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_D_CAL_MASK (0x78U) -#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_D_CAL_SHIFT (3U) -#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_D_CAL_SHIFT)) & FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_D_CAL_MASK) - -#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DP_MASK (0xF80U) -#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DP_SHIFT (7U) -#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DP_MASK) - -#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DN_MASK (0x1F000U) -#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DN_SHIFT (12U) -#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DN_MASK) - -#define FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_TST_MASK (0x60000U) -#define FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_TST_SHIFT (17U) -#define FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_TST_SHIFT)) & FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_TST_MASK) - -#define FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x380000U) -#define FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (19U) -#define FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_VBGADJ_MASK) - -#define FLASH_NMPA_GPO2_0_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x1C00000U) -#define FLASH_NMPA_GPO2_0_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (22U) -#define FLASH_NMPA_GPO2_0_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & FLASH_NMPA_GPO2_0_TRIM_PLL_CTRL0_DIV_SEL_MASK) - -#define FLASH_NMPA_GPO2_0_FLASH_SIZE_MASK (0xE000000U) -#define FLASH_NMPA_GPO2_0_FLASH_SIZE_SHIFT (25U) -/*! FLASH_SIZE - (For Niobe4) 000 : 640 KB 001 : 512 KB 010 : 256 KB 011 : 128 KB 100 : 0 KB All - * others : RESERVED (For Niobe4 Mini) FLASH_SIZE[2:0] 000 : 256 KB 001 : 128 KB 010 : 80 KB - * (reserved) 011 : 64 KB 100 : 0 kB (reserved) All others : RESERVED - */ -#define FLASH_NMPA_GPO2_0_FLASH_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_FLASH_SIZE_SHIFT)) & FLASH_NMPA_GPO2_0_FLASH_SIZE_MASK) - -#define FLASH_NMPA_GPO2_0_CPU0_SECURITY_EXTENSION_DISABLE_MASK (0xF0000000U) -#define FLASH_NMPA_GPO2_0_CPU0_SECURITY_EXTENSION_DISABLE_SHIFT (28U) -/*! CPU0_SECURITY_EXTENSION_DISABLE - CPU0_SECURITY_EXTENSION_DISABLE[3:0]: 1010 : CPU0 Security - * Extension is disabled. All Other values: CPU0 Security Extension is enabled. - */ -#define FLASH_NMPA_GPO2_0_CPU0_SECURITY_EXTENSION_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_CPU0_SECURITY_EXTENSION_DISABLE_SHIFT)) & FLASH_NMPA_GPO2_0_CPU0_SECURITY_EXTENSION_DISABLE_MASK) -/*! @} */ - -/*! @name GPO2_1 - GPO2 register 1 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO2_1_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO2_1_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO2_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_1_FIELD_SHIFT)) & FLASH_NMPA_GPO2_1_FIELD_MASK) -/*! @} */ - -/*! @name GPO2_2 - GPO2 register 2 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO2_2_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO2_2_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO2_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_2_FIELD_SHIFT)) & FLASH_NMPA_GPO2_2_FIELD_MASK) -/*! @} */ - -/*! @name GPO2_3 - GPO2 register 3 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO2_3_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO2_3_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO2_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_3_FIELD_SHIFT)) & FLASH_NMPA_GPO2_3_FIELD_MASK) -/*! @} */ - -/*! @name GPO2_ARRAY - GPO2 array description */ -/*! @{ */ - -#define FLASH_NMPA_GPO2_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO2_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO2_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_GPO2_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_GPO2_ARRAY */ -#define FLASH_NMPA_GPO2_ARRAY_COUNT (4U) - -/*! @name GPO3_0 - GPO3 register 0 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO3_0_AUX_BIAS_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_GPO3_0_AUX_BIAS_TRIM_VALID_SHIFT (0U) -#define FLASH_NMPA_GPO3_0_AUX_BIAS_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_AUX_BIAS_TRIM_VALID_SHIFT)) & FLASH_NMPA_GPO3_0_AUX_BIAS_TRIM_VALID_MASK) - -#define FLASH_NMPA_GPO3_0_AUX_BIAS_ITRIM_MASK (0x3EU) -#define FLASH_NMPA_GPO3_0_AUX_BIAS_ITRIM_SHIFT (1U) -#define FLASH_NMPA_GPO3_0_AUX_BIAS_ITRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_AUX_BIAS_ITRIM_SHIFT)) & FLASH_NMPA_GPO3_0_AUX_BIAS_ITRIM_MASK) - -#define FLASH_NMPA_GPO3_0_AUX_BIAS_PTAT_ITRIM_MASK (0x7C0U) -#define FLASH_NMPA_GPO3_0_AUX_BIAS_PTAT_ITRIM_SHIFT (6U) -#define FLASH_NMPA_GPO3_0_AUX_BIAS_PTAT_ITRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_AUX_BIAS_PTAT_ITRIM_SHIFT)) & FLASH_NMPA_GPO3_0_AUX_BIAS_PTAT_ITRIM_MASK) - -#define FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VTRIM_MASK (0xF800U) -#define FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VTRIM_SHIFT (11U) -#define FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VTRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VTRIM_SHIFT)) & FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VTRIM_MASK) - -#define FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VCURVE_TRIM_MASK (0x70000U) -#define FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VCURVE_TRIM_SHIFT (16U) -#define FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VCURVE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VCURVE_TRIM_SHIFT)) & FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VCURVE_TRIM_MASK) - -#define FLASH_NMPA_GPO3_0_FIELD_MASK (0x1F80000U) -#define FLASH_NMPA_GPO3_0_FIELD_SHIFT (19U) -#define FLASH_NMPA_GPO3_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_FIELD_SHIFT)) & FLASH_NMPA_GPO3_0_FIELD_MASK) - -#define FLASH_NMPA_GPO3_0_MODELNUM_EXTENSION_MASK (0xE000000U) -#define FLASH_NMPA_GPO3_0_MODELNUM_EXTENSION_SHIFT (25U) -/*! MODELNUM_EXTENSION - ModelNumber extension[2:0] - */ -#define FLASH_NMPA_GPO3_0_MODELNUM_EXTENSION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_MODELNUM_EXTENSION_SHIFT)) & FLASH_NMPA_GPO3_0_MODELNUM_EXTENSION_MASK) - -#define FLASH_NMPA_GPO3_0_FINAL_TEST_NOT_DONE_MASK (0xF0000000U) -#define FLASH_NMPA_GPO3_0_FINAL_TEST_NOT_DONE_SHIFT (28U) -/*! FINAL_TEST_NOT_DONE - FINAL_TEST_NOT_DONE[3:0]: 1010 : Final Test Not Done. All Other values: Final Test Done. - */ -#define FLASH_NMPA_GPO3_0_FINAL_TEST_NOT_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_FINAL_TEST_NOT_DONE_SHIFT)) & FLASH_NMPA_GPO3_0_FINAL_TEST_NOT_DONE_MASK) -/*! @} */ - -/*! @name GPO3_1 - GPO3 register 1 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO3_1_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO3_1_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO3_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_1_FIELD_SHIFT)) & FLASH_NMPA_GPO3_1_FIELD_MASK) -/*! @} */ - -/*! @name GPO3_2 - GPO3 register 2 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO3_2_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO3_2_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO3_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_2_FIELD_SHIFT)) & FLASH_NMPA_GPO3_2_FIELD_MASK) -/*! @} */ - -/*! @name GPO3_3 - GPO3 register 3 description */ -/*! @{ */ - -#define FLASH_NMPA_GPO3_3_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO3_3_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO3_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_3_FIELD_SHIFT)) & FLASH_NMPA_GPO3_3_FIELD_MASK) -/*! @} */ - -/*! @name GPO3_ARRAY - GPO3 array description */ -/*! @{ */ - -#define FLASH_NMPA_GPO3_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO3_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO3_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_GPO3_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_GPO3_ARRAY */ -#define FLASH_NMPA_GPO3_ARRAY_COUNT (4U) - -/*! @name GPO_CHECKSUM_0 - checksum of the GPO data in words 0 */ -/*! @{ */ - -#define FLASH_NMPA_GPO_CHECKSUM_0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO_CHECKSUM_0_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO_CHECKSUM_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO_CHECKSUM_0_FIELD_SHIFT)) & FLASH_NMPA_GPO_CHECKSUM_0_FIELD_MASK) -/*! @} */ - -/*! @name GPO_CHECKSUM_1 - checksum of the GPO data in words 1 */ -/*! @{ */ - -#define FLASH_NMPA_GPO_CHECKSUM_1_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO_CHECKSUM_1_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO_CHECKSUM_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO_CHECKSUM_1_FIELD_SHIFT)) & FLASH_NMPA_GPO_CHECKSUM_1_FIELD_MASK) -/*! @} */ - -/*! @name GPO_CHECKSUM_2 - checksum of the GPO data in words 2 */ -/*! @{ */ - -#define FLASH_NMPA_GPO_CHECKSUM_2_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO_CHECKSUM_2_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO_CHECKSUM_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO_CHECKSUM_2_FIELD_SHIFT)) & FLASH_NMPA_GPO_CHECKSUM_2_FIELD_MASK) -/*! @} */ - -/*! @name GPO_CHECKSUM_3 - checksum of the GPO data in words 3 */ -/*! @{ */ - -#define FLASH_NMPA_GPO_CHECKSUM_3_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO_CHECKSUM_3_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO_CHECKSUM_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO_CHECKSUM_3_FIELD_SHIFT)) & FLASH_NMPA_GPO_CHECKSUM_3_FIELD_MASK) -/*! @} */ - -/*! @name GPO_CHECKSUM_ARRAY - checksum of the GPO data in words [3:0] */ -/*! @{ */ - -#define FLASH_NMPA_GPO_CHECKSUM_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_GPO_CHECKSUM_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_GPO_CHECKSUM_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO_CHECKSUM_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_GPO_CHECKSUM_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_GPO_CHECKSUM_ARRAY */ -#define FLASH_NMPA_GPO_CHECKSUM_ARRAY_COUNT (4U) - -/*! @name FINAL_TEST_BATCH_ID_0 - */ -/*! @{ */ - -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_0_FIELD_SHIFT (0U) -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_BATCH_ID_0_FIELD_SHIFT)) & FLASH_NMPA_FINAL_TEST_BATCH_ID_0_FIELD_MASK) -/*! @} */ - -/*! @name FINAL_TEST_BATCH_ID_1 - */ -/*! @{ */ - -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_1_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_1_FIELD_SHIFT (0U) -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_BATCH_ID_1_FIELD_SHIFT)) & FLASH_NMPA_FINAL_TEST_BATCH_ID_1_FIELD_MASK) -/*! @} */ - -/*! @name FINAL_TEST_BATCH_ID_2 - */ -/*! @{ */ - -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_2_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_2_FIELD_SHIFT (0U) -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_BATCH_ID_2_FIELD_SHIFT)) & FLASH_NMPA_FINAL_TEST_BATCH_ID_2_FIELD_MASK) -/*! @} */ - -/*! @name FINAL_TEST_BATCH_ID_3 - */ -/*! @{ */ - -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_3_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_3_FIELD_SHIFT (0U) -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_BATCH_ID_3_FIELD_SHIFT)) & FLASH_NMPA_FINAL_TEST_BATCH_ID_3_FIELD_MASK) -/*! @} */ - -/*! @name FINAL_TEST_BATCH_ID_ARRAY - */ -/*! @{ */ - -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_BATCH_ID_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_FINAL_TEST_BATCH_ID_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_FINAL_TEST_BATCH_ID_ARRAY */ -#define FLASH_NMPA_FINAL_TEST_BATCH_ID_ARRAY_COUNT (4U) - -/*! @name DEVICE_TYPE - */ -/*! @{ */ - -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_NUM_MASK (0xFFFFU) -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_NUM_SHIFT (0U) -/*! DEVICE_TYPE_NUM - Device type number. (E.g : LPC5569 stored as 5569 decimal) - */ -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_NUM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_NUM_SHIFT)) & FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_NUM_MASK) - -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_SEC_MASK (0x10000U) -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_SEC_SHIFT (16U) -/*! DEVICE_TYPE_SEC - Security device type: 0: LPC55xxx (Non Secure Familly) 1: LPC55Sxxx (Secure Familly) - */ -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_SEC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_SEC_SHIFT)) & FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_SEC_MASK) - -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PKG_MASK (0xF00000U) -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PKG_SHIFT (20U) -/*! DEVICE_TYPE_PKG - Device package type: 0000 : HLQFP 0001 : HTQFP 0010 : HVQFN 0100 : VFBGA 1000 : WLCSP - */ -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PKG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PKG_SHIFT)) & FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PKG_MASK) - -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PIN_MASK (0xFF000000U) -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PIN_SHIFT (24U) -/*! DEVICE_TYPE_PIN - Number of pins on the package. - */ -#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PIN_SHIFT)) & FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PIN_MASK) -/*! @} */ - -/*! @name FINAL_TEST_PROGRAM_VERSION - */ -/*! @{ */ - -#define FLASH_NMPA_FINAL_TEST_PROGRAM_VERSION_PROGRAM_VERSION_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_FINAL_TEST_PROGRAM_VERSION_PROGRAM_VERSION_SHIFT (0U) -/*! PROGRAM_VERSION - PROGRAM_VERSION [xx.yy stored as : 100*x+y] - */ -#define FLASH_NMPA_FINAL_TEST_PROGRAM_VERSION_PROGRAM_VERSION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_PROGRAM_VERSION_PROGRAM_VERSION_SHIFT)) & FLASH_NMPA_FINAL_TEST_PROGRAM_VERSION_PROGRAM_VERSION_MASK) -/*! @} */ - -/*! @name FINAL_TEST_DATE - */ -/*! @{ */ - -#define FLASH_NMPA_FINAL_TEST_DATE_DATE_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_FINAL_TEST_DATE_DATE_SHIFT (0U) -/*! DATE - DATE [stored as : year*10000+month*100+day] - */ -#define FLASH_NMPA_FINAL_TEST_DATE_DATE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_DATE_DATE_SHIFT)) & FLASH_NMPA_FINAL_TEST_DATE_DATE_MASK) -/*! @} */ - -/*! @name FINAL_TEST_TIME - */ -/*! @{ */ - -#define FLASH_NMPA_FINAL_TEST_TIME_TIME_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_FINAL_TEST_TIME_TIME_SHIFT (0U) -/*! TIME - TIME [stored as : hour*10000+minute*100+seconde] - */ -#define FLASH_NMPA_FINAL_TEST_TIME_TIME(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_TIME_TIME_SHIFT)) & FLASH_NMPA_FINAL_TEST_TIME_TIME_MASK) -/*! @} */ - -/*! @name UUID_0 - */ -/*! @{ */ - -#define FLASH_NMPA_UUID_0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_UUID_0_FIELD_SHIFT (0U) -#define FLASH_NMPA_UUID_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_UUID_0_FIELD_SHIFT)) & FLASH_NMPA_UUID_0_FIELD_MASK) -/*! @} */ - -/*! @name UUID_1 - */ -/*! @{ */ - -#define FLASH_NMPA_UUID_1_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_UUID_1_FIELD_SHIFT (0U) -#define FLASH_NMPA_UUID_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_UUID_1_FIELD_SHIFT)) & FLASH_NMPA_UUID_1_FIELD_MASK) -/*! @} */ - -/*! @name UUID_2 - */ -/*! @{ */ - -#define FLASH_NMPA_UUID_2_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_UUID_2_FIELD_SHIFT (0U) -#define FLASH_NMPA_UUID_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_UUID_2_FIELD_SHIFT)) & FLASH_NMPA_UUID_2_FIELD_MASK) -/*! @} */ - -/*! @name UUID_3 - */ -/*! @{ */ - -#define FLASH_NMPA_UUID_3_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_UUID_3_FIELD_SHIFT (0U) -#define FLASH_NMPA_UUID_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_UUID_3_FIELD_SHIFT)) & FLASH_NMPA_UUID_3_FIELD_MASK) -/*! @} */ - -/*! @name UUID_ARRAY - */ -/*! @{ */ - -#define FLASH_NMPA_UUID_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_UUID_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_UUID_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_UUID_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_UUID_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_UUID_ARRAY */ -#define FLASH_NMPA_UUID_ARRAY_COUNT (4U) - -/*! @name WAFER_TEST1_PROGRAM_VERSION - */ -/*! @{ */ - -#define FLASH_NMPA_WAFER_TEST1_PROGRAM_VERSION_WT1_PROGRAM_VERSION_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_WAFER_TEST1_PROGRAM_VERSION_WT1_PROGRAM_VERSION_SHIFT (0U) -/*! WT1_PROGRAM_VERSION - WT1_PROGRAM_VERSION [xx.yy stored as : 100*x+y] - */ -#define FLASH_NMPA_WAFER_TEST1_PROGRAM_VERSION_WT1_PROGRAM_VERSION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_WAFER_TEST1_PROGRAM_VERSION_WT1_PROGRAM_VERSION_SHIFT)) & FLASH_NMPA_WAFER_TEST1_PROGRAM_VERSION_WT1_PROGRAM_VERSION_MASK) -/*! @} */ - -/*! @name WAFER_TEST1_DATE - */ -/*! @{ */ - -#define FLASH_NMPA_WAFER_TEST1_DATE_WT1_DATE_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_WAFER_TEST1_DATE_WT1_DATE_SHIFT (0U) -/*! WT1_DATE - WT1_DATE [stored as : year*10000+month*100+day] - */ -#define FLASH_NMPA_WAFER_TEST1_DATE_WT1_DATE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_WAFER_TEST1_DATE_WT1_DATE_SHIFT)) & FLASH_NMPA_WAFER_TEST1_DATE_WT1_DATE_MASK) -/*! @} */ - -/*! @name WAFER_TEST1_TIME - */ -/*! @{ */ - -#define FLASH_NMPA_WAFER_TEST1_TIME_WT1_TIME_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_WAFER_TEST1_TIME_WT1_TIME_SHIFT (0U) -/*! WT1_TIME - WT1_TIME [stored as : hour*10000+minute*100+seconde] - */ -#define FLASH_NMPA_WAFER_TEST1_TIME_WT1_TIME(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_WAFER_TEST1_TIME_WT1_TIME_SHIFT)) & FLASH_NMPA_WAFER_TEST1_TIME_WT1_TIME_MASK) -/*! @} */ - -/*! @name WAFER_TEST2_PROGRAM_VERSION - */ -/*! @{ */ - -#define FLASH_NMPA_WAFER_TEST2_PROGRAM_VERSION_WT2_PROGRAM_VERSION_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_WAFER_TEST2_PROGRAM_VERSION_WT2_PROGRAM_VERSION_SHIFT (0U) -/*! WT2_PROGRAM_VERSION - WT2_PROGRAM_VERSION [xx.yy stored as : 100*x+y] - */ -#define FLASH_NMPA_WAFER_TEST2_PROGRAM_VERSION_WT2_PROGRAM_VERSION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_WAFER_TEST2_PROGRAM_VERSION_WT2_PROGRAM_VERSION_SHIFT)) & FLASH_NMPA_WAFER_TEST2_PROGRAM_VERSION_WT2_PROGRAM_VERSION_MASK) -/*! @} */ - -/*! @name WAFER_TEST2_DATE - */ -/*! @{ */ - -#define FLASH_NMPA_WAFER_TEST2_DATE_WT2_DATE_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_WAFER_TEST2_DATE_WT2_DATE_SHIFT (0U) -/*! WT2_DATE - WT2_DATE [stored as : year*10000+month*100+day] - */ -#define FLASH_NMPA_WAFER_TEST2_DATE_WT2_DATE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_WAFER_TEST2_DATE_WT2_DATE_SHIFT)) & FLASH_NMPA_WAFER_TEST2_DATE_WT2_DATE_MASK) -/*! @} */ - -/*! @name WAFER_TEST2_TIME - */ -/*! @{ */ - -#define FLASH_NMPA_WAFER_TEST2_TIME_WT2_TIME_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_WAFER_TEST2_TIME_WT2_TIME_SHIFT (0U) -/*! WT2_TIME - WT2_TIME [stored as : hour*10000+minute*100+seconde] - */ -#define FLASH_NMPA_WAFER_TEST2_TIME_WT2_TIME(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_WAFER_TEST2_TIME_WT2_TIME_SHIFT)) & FLASH_NMPA_WAFER_TEST2_TIME_WT2_TIME_MASK) -/*! @} */ - -/*! @name USBCFG - */ -/*! @{ */ - -#define FLASH_NMPA_USBCFG_XO32M_READY_TIME_OUT_MS_MASK (0xFFU) -#define FLASH_NMPA_USBCFG_XO32M_READY_TIME_OUT_MS_SHIFT (0U) -#define FLASH_NMPA_USBCFG_XO32M_READY_TIME_OUT_MS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_USBCFG_XO32M_READY_TIME_OUT_MS_SHIFT)) & FLASH_NMPA_USBCFG_XO32M_READY_TIME_OUT_MS_MASK) - -#define FLASH_NMPA_USBCFG_USB_SPEED_MASK (0xFF00U) -#define FLASH_NMPA_USBCFG_USB_SPEED_SHIFT (8U) -/*! USB_SPEED - USB_SPEED[7:0]= 0x00 : USB High Speed Module used for ISP 0x01 : USB Full SPeed - * Module used for ISP 0x02 : Neither USB High Speed module nor USB Full Speed module used for ISP - * 0x03 - 0xFF : RESERVED - */ -#define FLASH_NMPA_USBCFG_USB_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_USBCFG_USB_SPEED_SHIFT)) & FLASH_NMPA_USBCFG_USB_SPEED_MASK) - -#define FLASH_NMPA_USBCFG_USB_USE_XO32M_CAPA_BANKS_MASK (0x10000U) -#define FLASH_NMPA_USBCFG_USB_USE_XO32M_CAPA_BANKS_SHIFT (16U) -/*! USB_USE_XO32M_CAPA_BANKS - Enable the use of Crystal 32 MHz internal Capa Banks during the - * configuration of the High Speed USB for ISP: 0: Disable Crystal 32 MHz CapaBanks. 1: Enable Crystal - * 32 MHz CapaBanks. - */ -#define FLASH_NMPA_USBCFG_USB_USE_XO32M_CAPA_BANKS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_USBCFG_USB_USE_XO32M_CAPA_BANKS_SHIFT)) & FLASH_NMPA_USBCFG_USB_USE_XO32M_CAPA_BANKS_MASK) -/*! @} */ - -/*! @name PERIPHENCFG - */ -/*! @{ */ - -#define FLASH_NMPA_PERIPHENCFG_PERIPHERAL_CONFIGURATION_MASK (0xFFFFU) -#define FLASH_NMPA_PERIPHENCFG_PERIPHERAL_CONFIGURATION_SHIFT (0U) -#define FLASH_NMPA_PERIPHENCFG_PERIPHERAL_CONFIGURATION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PERIPHENCFG_PERIPHERAL_CONFIGURATION_SHIFT)) & FLASH_NMPA_PERIPHENCFG_PERIPHERAL_CONFIGURATION_MASK) - -#define FLASH_NMPA_PERIPHENCFG_CPU1_ENABLE_MASK (0x80000000U) -#define FLASH_NMPA_PERIPHENCFG_CPU1_ENABLE_SHIFT (31U) -#define FLASH_NMPA_PERIPHENCFG_CPU1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PERIPHENCFG_CPU1_ENABLE_SHIFT)) & FLASH_NMPA_PERIPHENCFG_CPU1_ENABLE_MASK) -/*! @} */ - -/*! @name RAMSIZECFG - */ -/*! @{ */ - -#define FLASH_NMPA_RAMSIZECFG_SRAM_CONFIGURATION_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_RAMSIZECFG_SRAM_CONFIGURATION_SHIFT (0U) -#define FLASH_NMPA_RAMSIZECFG_SRAM_CONFIGURATION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_RAMSIZECFG_SRAM_CONFIGURATION_SHIFT)) & FLASH_NMPA_RAMSIZECFG_SRAM_CONFIGURATION_MASK) -/*! @} */ - -/*! @name FLASHSIZECFG - */ -/*! @{ */ - -#define FLASH_NMPA_FLASHSIZECFG_FLASH_CONFIGURATION_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_FLASHSIZECFG_FLASH_CONFIGURATION_SHIFT (0U) -#define FLASH_NMPA_FLASHSIZECFG_FLASH_CONFIGURATION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FLASHSIZECFG_FLASH_CONFIGURATION_SHIFT)) & FLASH_NMPA_FLASHSIZECFG_FLASH_CONFIGURATION_MASK) -/*! @} */ - -/*! @name RINGO_0 - */ -/*! @{ */ - -#define FLASH_NMPA_RINGO_0_RINGO_0_CTRL_VALID_MASK (0x1U) -#define FLASH_NMPA_RINGO_0_RINGO_0_CTRL_VALID_SHIFT (0U) -/*! RINGO_0_CTRL_VALID - 1: RINGO_0_CTRL is valid. - */ -#define FLASH_NMPA_RINGO_0_RINGO_0_CTRL_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_RINGO_0_RINGO_0_CTRL_VALID_SHIFT)) & FLASH_NMPA_RINGO_0_RINGO_0_CTRL_VALID_MASK) - -#define FLASH_NMPA_RINGO_0_RINGO_0_CTRL_MASK (0xFFFFFFFEU) -#define FLASH_NMPA_RINGO_0_RINGO_0_CTRL_SHIFT (1U) -/*! RINGO_0_CTRL - To copy RINGO_0_CTRL = ANACTRL->RINGO0_CTRL[30:0] - */ -#define FLASH_NMPA_RINGO_0_RINGO_0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_RINGO_0_RINGO_0_CTRL_SHIFT)) & FLASH_NMPA_RINGO_0_RINGO_0_CTRL_MASK) -/*! @} */ - -/*! @name RINGO_1 - */ -/*! @{ */ - -#define FLASH_NMPA_RINGO_1_RINGO_1_CTRL_VALID_MASK (0x1U) -#define FLASH_NMPA_RINGO_1_RINGO_1_CTRL_VALID_SHIFT (0U) -/*! RINGO_1_CTRL_VALID - 1: RINGO_1_CTRL is valid. - */ -#define FLASH_NMPA_RINGO_1_RINGO_1_CTRL_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_RINGO_1_RINGO_1_CTRL_VALID_SHIFT)) & FLASH_NMPA_RINGO_1_RINGO_1_CTRL_VALID_MASK) - -#define FLASH_NMPA_RINGO_1_RINGO_1_CTRL_MASK (0xFFFFFFFEU) -#define FLASH_NMPA_RINGO_1_RINGO_1_CTRL_SHIFT (1U) -/*! RINGO_1_CTRL - To copy RINGO_1_CTRL = ANACTRL->RINGO1_CTRL[30:0] - */ -#define FLASH_NMPA_RINGO_1_RINGO_1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_RINGO_1_RINGO_1_CTRL_SHIFT)) & FLASH_NMPA_RINGO_1_RINGO_1_CTRL_MASK) -/*! @} */ - -/*! @name RINGO_2 - */ -/*! @{ */ - -#define FLASH_NMPA_RINGO_2_RINGO_2_CTRL_VALID_MASK (0x1U) -#define FLASH_NMPA_RINGO_2_RINGO_2_CTRL_VALID_SHIFT (0U) -/*! RINGO_2_CTRL_VALID - 1: RINGO_2_CTRL is valid. - */ -#define FLASH_NMPA_RINGO_2_RINGO_2_CTRL_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_RINGO_2_RINGO_2_CTRL_VALID_SHIFT)) & FLASH_NMPA_RINGO_2_RINGO_2_CTRL_VALID_MASK) - -#define FLASH_NMPA_RINGO_2_RINGO_2_CTRL_MASK (0xFFFFFFFEU) -#define FLASH_NMPA_RINGO_2_RINGO_2_CTRL_SHIFT (1U) -/*! RINGO_2_CTRL - To copy RINGO_2_CTRL = ANACTRL->RINGO2_CTRL[30:0] - */ -#define FLASH_NMPA_RINGO_2_RINGO_2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_RINGO_2_RINGO_2_CTRL_SHIFT)) & FLASH_NMPA_RINGO_2_RINGO_2_CTRL_MASK) -/*! @} */ - -/*! @name FRO_192MHZ - */ -/*! @{ */ - -#define FLASH_NMPA_FRO_192MHZ_FRO192M_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_FRO_192MHZ_FRO192M_TRIM_VALID_SHIFT (0U) -#define FLASH_NMPA_FRO_192MHZ_FRO192M_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FRO_192MHZ_FRO192M_TRIM_VALID_SHIFT)) & FLASH_NMPA_FRO_192MHZ_FRO192M_TRIM_VALID_MASK) - -#define FLASH_NMPA_FRO_192MHZ_FRO192M_BIASTRIM_MASK (0x7EU) -#define FLASH_NMPA_FRO_192MHZ_FRO192M_BIASTRIM_SHIFT (1U) -/*! FRO192M_BIASTRIM - FRO192M_BIASTRIM[5:0]. - */ -#define FLASH_NMPA_FRO_192MHZ_FRO192M_BIASTRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FRO_192MHZ_FRO192M_BIASTRIM_SHIFT)) & FLASH_NMPA_FRO_192MHZ_FRO192M_BIASTRIM_MASK) - -#define FLASH_NMPA_FRO_192MHZ_FRO192M_TEMPTRIM_MASK (0x7F00U) -#define FLASH_NMPA_FRO_192MHZ_FRO192M_TEMPTRIM_SHIFT (8U) -/*! FRO192M_TEMPTRIM - FRO192M_TEMPTRIM[6:0]. - */ -#define FLASH_NMPA_FRO_192MHZ_FRO192M_TEMPTRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FRO_192MHZ_FRO192M_TEMPTRIM_SHIFT)) & FLASH_NMPA_FRO_192MHZ_FRO192M_TEMPTRIM_MASK) - -#define FLASH_NMPA_FRO_192MHZ_FRO192M_DACTRIM_MASK (0x1FE0000U) -#define FLASH_NMPA_FRO_192MHZ_FRO192M_DACTRIM_SHIFT (17U) -/*! FRO192M_DACTRIM - FRO192M_DACTRIM[7:0]. - */ -#define FLASH_NMPA_FRO_192MHZ_FRO192M_DACTRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FRO_192MHZ_FRO192M_DACTRIM_SHIFT)) & FLASH_NMPA_FRO_192MHZ_FRO192M_DACTRIM_MASK) -/*! @} */ - -/*! @name XO_32MHZ - */ -/*! @{ */ - -#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_TRIM_VALID_SHIFT (0U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XIN_TRIM_VALID_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XIN_TRIM_VALID_MASK) - -#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_6PF_MASK (0xFEU) -#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_6PF_SHIFT (1U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_6PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_6PF_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_6PF_MASK) - -#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_8PF_MASK (0x7F00U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_8PF_SHIFT (8U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_8PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_8PF_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_8PF_MASK) - -#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_TRIM_VALID_MASK (0x8000U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_TRIM_VALID_SHIFT (15U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XOUT_TRIM_VALID_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XOUT_TRIM_VALID_MASK) - -#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_6PF_MASK (0x7F0000U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_6PF_SHIFT (16U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_6PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_6PF_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_6PF_MASK) - -#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_8PF_MASK (0x3F800000U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_8PF_SHIFT (23U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_8PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_8PF_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_8PF_MASK) - -#define FLASH_NMPA_XO_32MHZ_XO32M_XO_SLAVE_STATUS_MASK (0x40000000U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XO_SLAVE_STATUS_SHIFT (30U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XO_SLAVE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XO_SLAVE_STATUS_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XO_SLAVE_STATUS_MASK) - -#define FLASH_NMPA_XO_32MHZ_XO32M_XO_AC_BUF_STATUS_MASK (0x80000000U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XO_AC_BUF_STATUS_SHIFT (31U) -#define FLASH_NMPA_XO_32MHZ_XO32M_XO_AC_BUF_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XO_AC_BUF_STATUS_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XO_AC_BUF_STATUS_MASK) -/*! @} */ - -/*! @name XO_32KHZ - */ -/*! @{ */ - -#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_TRIM_VALID_SHIFT (0U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32KHZ_XO32K_XIN_TRIM_VALID_SHIFT)) & FLASH_NMPA_XO_32KHZ_XO32K_XIN_TRIM_VALID_MASK) - -#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_6PF_MASK (0xFEU) -#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_6PF_SHIFT (1U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_6PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_6PF_SHIFT)) & FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_6PF_MASK) - -#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_8PF_MASK (0x7F00U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_8PF_SHIFT (8U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_8PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_8PF_SHIFT)) & FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_8PF_MASK) - -#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_TRIM_VALID_MASK (0x8000U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_TRIM_VALID_SHIFT (15U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32KHZ_XO32K_XOUT_TRIM_VALID_SHIFT)) & FLASH_NMPA_XO_32KHZ_XO32K_XOUT_TRIM_VALID_MASK) - -#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_6PF_MASK (0x7F0000U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_6PF_SHIFT (16U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_6PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_6PF_SHIFT)) & FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_6PF_MASK) - -#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_8PF_MASK (0x3F800000U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_8PF_SHIFT (23U) -#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_8PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_8PF_SHIFT)) & FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_8PF_MASK) -/*! @} */ - -/*! @name FRO_1MHZ - */ -/*! @{ */ - -#define FLASH_NMPA_FRO_1MHZ_FRO1M_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_FRO_1MHZ_FRO1M_TRIM_VALID_SHIFT (0U) -#define FLASH_NMPA_FRO_1MHZ_FRO1M_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FRO_1MHZ_FRO1M_TRIM_VALID_SHIFT)) & FLASH_NMPA_FRO_1MHZ_FRO1M_TRIM_VALID_MASK) - -#define FLASH_NMPA_FRO_1MHZ_FRO1M_FREQSEL_MASK (0xFEU) -#define FLASH_NMPA_FRO_1MHZ_FRO1M_FREQSEL_SHIFT (1U) -/*! FRO1M_FREQSEL - Frequency trimming bits. - */ -#define FLASH_NMPA_FRO_1MHZ_FRO1M_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FRO_1MHZ_FRO1M_FREQSEL_SHIFT)) & FLASH_NMPA_FRO_1MHZ_FRO1M_FREQSEL_MASK) -/*! @} */ - -/*! @name DCDC_POWER_PROFILE_HIGH_0 - */ -/*! @{ */ - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DCDC_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DCDC_TRIM_VALID_SHIFT (0U) -/*! DCDC_TRIM_VALID - DCDC is trimed. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DCDC_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DCDC_TRIM_VALID_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DCDC_TRIM_VALID_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_RC_MASK (0x7EU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_RC_SHIFT (1U) -/*! RC - Constant On-Time calibration. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_RC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_RC_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_RC_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICOMP_MASK (0x180U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICOMP_SHIFT (7U) -/*! ICOMP - Select the type of ZCD comparator. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICOMP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICOMP_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICOMP_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ISEL_MASK (0x600U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ISEL_SHIFT (9U) -/*! ISEL - Alter Internal biasing currents. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ISEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ISEL_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ISEL_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICENABLE_MASK (0x800U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICENABLE_SHIFT (11U) -/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_TMOS_MASK (0x1F000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_TMOS_SHIFT (12U) -/*! TMOS - One-shot generator reference current trimming signal. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_TMOS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_TMOS_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_TMOS_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DISABLEISENSE_MASK (0x20000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DISABLEISENSE_SHIFT (17U) -/*! DISABLEISENSE - Disable Current sensing. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DISABLEISENSE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DISABLEISENSE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DISABLEISENSE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_MASK (0x3C0000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_SHIFT (18U) -/*! VOUT - Set output regulation voltage. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_SLICINGENABLE_MASK (0x400000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_SLICINGENABLE_SHIFT (22U) -/*! SLICINGENABLE - Enable staggered switching of power switches. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_SLICINGENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_SLICINGENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_SLICINGENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_INDUCTORCLAMPENABLE_MASK (0x800000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_INDUCTORCLAMPENABLE_SHIFT (23U) -/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_INDUCTORCLAMPENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_INDUCTORCLAMPENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_INDUCTORCLAMPENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_PWD_MASK (0xF000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_PWD_SHIFT (24U) -/*! VOUT_PWD - Set output regulation voltage during Deep Sleep. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_PWD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_PWD_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_PWD_MASK) -/*! @} */ - -/*! @name DCDC_POWER_PROFILE_HIGH_1 - */ -/*! @{ */ - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RTRIMOFFET_MASK (0xFU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RTRIMOFFET_SHIFT (0U) -/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RTRIMOFFET(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RTRIMOFFET_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RTRIMOFFET_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RSENSETRIM_MASK (0xF0U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RSENSETRIM_SHIFT (4U) -/*! RSENSETRIM - Adjust Max inductor peak current limiting. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RSENSETRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RSENSETRIM_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RSENSETRIM_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTENABLE_MASK (0x100U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTENABLE_SHIFT (8U) -/*! DTESTENABLE - Enable Digital test signals. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETCURVE_MASK (0x600U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETCURVE_SHIFT (9U) -/*! SETCURVE - Bandgap calibration parameter. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETCURVE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETCURVE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETCURVE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETDC_MASK (0x7800U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETDC_SHIFT (11U) -/*! SETDC - Bandgap calibration parameter. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETDC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETDC_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETDC_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTSEL_MASK (0x38000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTSEL_SHIFT (15U) -/*! DTESTSEL - Select the output signal for test. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTSEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTSEL_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTSEL_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ISCALEENABLE_MASK (0x40000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ISCALEENABLE_SHIFT (18U) -/*! ISCALEENABLE - Modify COT behavior. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ISCALEENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ISCALEENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ISCALEENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEBYPASS_MASK (0x80000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEBYPASS_SHIFT (19U) -/*! FORCEBYPASS - Force bypass mode. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEBYPASS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEBYPASS_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEBYPASS_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TRIMAUTOCOT_MASK (0xF00000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TRIMAUTOCOT_SHIFT (20U) -/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TRIMAUTOCOT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TRIMAUTOCOT_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TRIMAUTOCOT_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEFULLCYCLE_MASK (0x1000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEFULLCYCLE_SHIFT (24U) -/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEFULLCYCLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEFULLCYCLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEFULLCYCLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_LCENABLE_MASK (0x2000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_LCENABLE_SHIFT (25U) -/*! LCENABLE - Change the range of the peak detector of current inside the inductor. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_LCENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_LCENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_LCENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFF_MASK (0x7C000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFF_SHIFT (26U) -/*! TOFF - Constant Off-Time calibration input. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFF_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFF_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFFENABLE_MASK (0x80000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFFENABLE_SHIFT (31U) -/*! TOFFENABLE - Enable Constant Off-Time feature. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFFENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFFENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFFENABLE_MASK) -/*! @} */ - -/*! @name DCDC_POWER_PROFILE_HIGH_ARRAY - */ -/*! @{ */ - -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY_COUNT (2U) - -/*! @name DCDC_POWER_PROFILE_LOW_0 - */ -/*! @{ */ - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DCDC_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DCDC_TRIM_VALID_SHIFT (0U) -/*! DCDC_TRIM_VALID - DCDC is trimed. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DCDC_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DCDC_TRIM_VALID_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DCDC_TRIM_VALID_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_RC_MASK (0x7EU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_RC_SHIFT (1U) -/*! RC - Constant On-Time calibration. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_RC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_RC_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_RC_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICOMP_MASK (0x180U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICOMP_SHIFT (7U) -/*! ICOMP - Select the type of ZCD comparator. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICOMP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICOMP_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICOMP_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ISEL_MASK (0x600U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ISEL_SHIFT (9U) -/*! ISEL - Alter Internal biasing currents. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ISEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ISEL_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ISEL_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICENABLE_MASK (0x800U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICENABLE_SHIFT (11U) -/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_TMOS_MASK (0x1F000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_TMOS_SHIFT (12U) -/*! TMOS - One-shot generator reference current trimming signal. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_TMOS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_TMOS_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_TMOS_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DISABLEISENSE_MASK (0x20000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DISABLEISENSE_SHIFT (17U) -/*! DISABLEISENSE - Disable Current sensing. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DISABLEISENSE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DISABLEISENSE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DISABLEISENSE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_MASK (0x3C0000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_SHIFT (18U) -/*! VOUT - Set output regulation voltage. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_SLICINGENABLE_MASK (0x400000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_SLICINGENABLE_SHIFT (22U) -/*! SLICINGENABLE - Enable staggered switching of power switches. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_SLICINGENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_SLICINGENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_SLICINGENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_INDUCTORCLAMPENABLE_MASK (0x800000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_INDUCTORCLAMPENABLE_SHIFT (23U) -/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_INDUCTORCLAMPENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_INDUCTORCLAMPENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_INDUCTORCLAMPENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_PWD_MASK (0xF000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_PWD_SHIFT (24U) -/*! VOUT_PWD - Set output regulation voltage during Deep Sleep. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_PWD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_PWD_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_PWD_MASK) -/*! @} */ - -/*! @name DCDC_POWER_PROFILE_LOW_1 - */ -/*! @{ */ - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RTRIMOFFET_MASK (0xFU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RTRIMOFFET_SHIFT (0U) -/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RTRIMOFFET(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RTRIMOFFET_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RTRIMOFFET_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RSENSETRIM_MASK (0xF0U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RSENSETRIM_SHIFT (4U) -/*! RSENSETRIM - Adjust Max inductor peak current limiting. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RSENSETRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RSENSETRIM_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RSENSETRIM_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTENABLE_MASK (0x100U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTENABLE_SHIFT (8U) -/*! DTESTENABLE - Enable Digital test signals. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETCURVE_MASK (0x600U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETCURVE_SHIFT (9U) -/*! SETCURVE - Bandgap calibration parameter. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETCURVE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETCURVE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETCURVE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETDC_MASK (0x7800U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETDC_SHIFT (11U) -/*! SETDC - Bandgap calibration parameter. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETDC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETDC_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETDC_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTSEL_MASK (0x38000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTSEL_SHIFT (15U) -/*! DTESTSEL - Select the output signal for test. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTSEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTSEL_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTSEL_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ISCALEENABLE_MASK (0x40000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ISCALEENABLE_SHIFT (18U) -/*! ISCALEENABLE - Modify COT behavior. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ISCALEENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ISCALEENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ISCALEENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEBYPASS_MASK (0x80000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEBYPASS_SHIFT (19U) -/*! FORCEBYPASS - Force bypass mode. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEBYPASS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEBYPASS_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEBYPASS_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TRIMAUTOCOT_MASK (0xF00000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TRIMAUTOCOT_SHIFT (20U) -/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TRIMAUTOCOT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TRIMAUTOCOT_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TRIMAUTOCOT_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEFULLCYCLE_MASK (0x1000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEFULLCYCLE_SHIFT (24U) -/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEFULLCYCLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEFULLCYCLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEFULLCYCLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_LCENABLE_MASK (0x2000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_LCENABLE_SHIFT (25U) -/*! LCENABLE - Change the range of the peak detector of current inside the inductor. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_LCENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_LCENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_LCENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFF_MASK (0x7C000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFF_SHIFT (26U) -/*! TOFF - Constant Off-Time calibration input. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFF_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFF_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFFENABLE_MASK (0x80000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFFENABLE_SHIFT (31U) -/*! TOFFENABLE - Enable Constant Off-Time feature. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFFENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFFENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFFENABLE_MASK) -/*! @} */ - -/*! @name DCDC_POWER_PROFILE_LOW_ARRAY - */ -/*! @{ */ - -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY_COUNT (2U) - -/*! @name DCDC_POWER_PROFILE_MEDIUM_0 - */ -/*! @{ */ - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DCDC_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DCDC_TRIM_VALID_SHIFT (0U) -/*! DCDC_TRIM_VALID - DCDC is trimed. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DCDC_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DCDC_TRIM_VALID_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DCDC_TRIM_VALID_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_RC_MASK (0x7EU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_RC_SHIFT (1U) -/*! RC - Constant On-Time calibration. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_RC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_RC_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_RC_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICOMP_MASK (0x180U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICOMP_SHIFT (7U) -/*! ICOMP - Select the type of ZCD comparator. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICOMP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICOMP_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICOMP_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ISEL_MASK (0x600U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ISEL_SHIFT (9U) -/*! ISEL - Alter Internal biasing currents. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ISEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ISEL_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ISEL_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICENABLE_MASK (0x800U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICENABLE_SHIFT (11U) -/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_TMOS_MASK (0x1F000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_TMOS_SHIFT (12U) -/*! TMOS - One-shot generator reference current trimming signal. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_TMOS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_TMOS_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_TMOS_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DISABLEISENSE_MASK (0x20000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DISABLEISENSE_SHIFT (17U) -/*! DISABLEISENSE - Disable Current sensing. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DISABLEISENSE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DISABLEISENSE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DISABLEISENSE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_MASK (0x3C0000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_SHIFT (18U) -/*! VOUT - Set output regulation voltage. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_SLICINGENABLE_MASK (0x400000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_SLICINGENABLE_SHIFT (22U) -/*! SLICINGENABLE - Enable staggered switching of power switches. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_SLICINGENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_SLICINGENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_SLICINGENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_INDUCTORCLAMPENABLE_MASK (0x800000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_INDUCTORCLAMPENABLE_SHIFT (23U) -/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_INDUCTORCLAMPENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_INDUCTORCLAMPENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_INDUCTORCLAMPENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_PWD_MASK (0xF000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_PWD_SHIFT (24U) -/*! VOUT_PWD - Set output regulation voltage during Deep Sleep. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_PWD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_PWD_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_PWD_MASK) -/*! @} */ - -/*! @name DCDC_POWER_PROFILE_MEDIUM_1 - */ -/*! @{ */ - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RTRIMOFFET_MASK (0xFU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RTRIMOFFET_SHIFT (0U) -/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RTRIMOFFET(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RTRIMOFFET_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RTRIMOFFET_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RSENSETRIM_MASK (0xF0U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RSENSETRIM_SHIFT (4U) -/*! RSENSETRIM - Adjust Max inductor peak current limiting. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RSENSETRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RSENSETRIM_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RSENSETRIM_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTENABLE_MASK (0x100U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTENABLE_SHIFT (8U) -/*! DTESTENABLE - Enable Digital test signals. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETCURVE_MASK (0x600U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETCURVE_SHIFT (9U) -/*! SETCURVE - Bandgap calibration parameter. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETCURVE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETCURVE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETCURVE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETDC_MASK (0x7800U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETDC_SHIFT (11U) -/*! SETDC - Bandgap calibration parameter. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETDC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETDC_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETDC_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTSEL_MASK (0x38000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTSEL_SHIFT (15U) -/*! DTESTSEL - Select the output signal for test. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTSEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTSEL_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTSEL_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ISCALEENABLE_MASK (0x40000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ISCALEENABLE_SHIFT (18U) -/*! ISCALEENABLE - Modify COT behavior. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ISCALEENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ISCALEENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ISCALEENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEBYPASS_MASK (0x80000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEBYPASS_SHIFT (19U) -/*! FORCEBYPASS - Force bypass mode. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEBYPASS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEBYPASS_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEBYPASS_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TRIMAUTOCOT_MASK (0xF00000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TRIMAUTOCOT_SHIFT (20U) -/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TRIMAUTOCOT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TRIMAUTOCOT_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TRIMAUTOCOT_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEFULLCYCLE_MASK (0x1000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEFULLCYCLE_SHIFT (24U) -/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEFULLCYCLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEFULLCYCLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEFULLCYCLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_LCENABLE_MASK (0x2000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_LCENABLE_SHIFT (25U) -/*! LCENABLE - Change the range of the peak detector of current inside the inductor. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_LCENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_LCENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_LCENABLE_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFF_MASK (0x7C000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFF_SHIFT (26U) -/*! TOFF - Constant Off-Time calibration input. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFF_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFF_MASK) - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFFENABLE_MASK (0x80000000U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFFENABLE_SHIFT (31U) -/*! TOFFENABLE - Enable Constant Off-Time feature. - */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFFENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFFENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFFENABLE_MASK) -/*! @} */ - -/*! @name DCDC_POWER_PROFILE_MEDIUM_ARRAY - */ -/*! @{ */ - -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY */ -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY_COUNT (2U) - -/*! @name BOD - */ -/*! @{ */ - -#define FLASH_NMPA_BOD_BOD_VBAT_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_BOD_BOD_VBAT_TRIM_VALID_SHIFT (0U) -#define FLASH_NMPA_BOD_BOD_VBAT_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_BOD_BOD_VBAT_TRIM_VALID_SHIFT)) & FLASH_NMPA_BOD_BOD_VBAT_TRIM_VALID_MASK) - -#define FLASH_NMPA_BOD_BOD_VBAT_TRIGLVL_MASK (0x3EU) -#define FLASH_NMPA_BOD_BOD_VBAT_TRIGLVL_SHIFT (1U) -#define FLASH_NMPA_BOD_BOD_VBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_BOD_BOD_VBAT_TRIGLVL_SHIFT)) & FLASH_NMPA_BOD_BOD_VBAT_TRIGLVL_MASK) - -#define FLASH_NMPA_BOD_BOD_VBAT_HYST_MASK (0xC0U) -#define FLASH_NMPA_BOD_BOD_VBAT_HYST_SHIFT (6U) -#define FLASH_NMPA_BOD_BOD_VBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_BOD_BOD_VBAT_HYST_SHIFT)) & FLASH_NMPA_BOD_BOD_VBAT_HYST_MASK) - -#define FLASH_NMPA_BOD_BOD_CORE_TRIM_VALID_MASK (0x10000U) -#define FLASH_NMPA_BOD_BOD_CORE_TRIM_VALID_SHIFT (16U) -#define FLASH_NMPA_BOD_BOD_CORE_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_BOD_BOD_CORE_TRIM_VALID_SHIFT)) & FLASH_NMPA_BOD_BOD_CORE_TRIM_VALID_MASK) - -#define FLASH_NMPA_BOD_BOD_CORE_TRIGLVL_MASK (0xE0000U) -#define FLASH_NMPA_BOD_BOD_CORE_TRIGLVL_SHIFT (17U) -#define FLASH_NMPA_BOD_BOD_CORE_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_BOD_BOD_CORE_TRIGLVL_SHIFT)) & FLASH_NMPA_BOD_BOD_CORE_TRIGLVL_MASK) - -#define FLASH_NMPA_BOD_BOD_CORE_HYST_MASK (0x600000U) -#define FLASH_NMPA_BOD_BOD_CORE_HYST_SHIFT (21U) -#define FLASH_NMPA_BOD_BOD_CORE_HYST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_BOD_BOD_CORE_HYST_SHIFT)) & FLASH_NMPA_BOD_BOD_CORE_HYST_MASK) -/*! @} */ - -/*! @name LDO_AO - */ -/*! @{ */ - -#define FLASH_NMPA_LDO_AO_ACTIVE_TRIM_VALID_MASK (0x1U) -#define FLASH_NMPA_LDO_AO_ACTIVE_TRIM_VALID_SHIFT (0U) -#define FLASH_NMPA_LDO_AO_ACTIVE_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_ACTIVE_TRIM_VALID_SHIFT)) & FLASH_NMPA_LDO_AO_ACTIVE_TRIM_VALID_MASK) - -#define FLASH_NMPA_LDO_AO_ACTIVE_TRIM_MASK (0x3EU) -#define FLASH_NMPA_LDO_AO_ACTIVE_TRIM_SHIFT (1U) -#define FLASH_NMPA_LDO_AO_ACTIVE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_ACTIVE_TRIM_SHIFT)) & FLASH_NMPA_LDO_AO_ACTIVE_TRIM_MASK) - -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK (0x100U) -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_SHIFT (8U) -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_SHIFT)) & FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK) - -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK (0x3E00U) -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT (9U) -#define FLASH_NMPA_LDO_AO_DSLP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT)) & FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK) - -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK (0x10000U) -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_SHIFT (16U) -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_SHIFT)) & FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK) - -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK (0x3E0000U) -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT (17U) -#define FLASH_NMPA_LDO_AO_PDWN_TRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT)) & FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK) - -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK (0x1000000U) -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_SHIFT (24U) -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_SHIFT)) & FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK) - -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK (0x3E000000U) -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT (25U) -#define FLASH_NMPA_LDO_AO_DPDW_TRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT)) & FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK) -/*! @} */ - -/*! @name SDIO_DELAY - */ -/*! @{ */ - -#define FLASH_NMPA_SDIO_DELAY_SDIO_0_VALID_MASK (0x1U) -#define FLASH_NMPA_SDIO_DELAY_SDIO_0_VALID_SHIFT (0U) -#define FLASH_NMPA_SDIO_DELAY_SDIO_0_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_SDIO_DELAY_SDIO_0_VALID_SHIFT)) & FLASH_NMPA_SDIO_DELAY_SDIO_0_VALID_MASK) - -#define FLASH_NMPA_SDIO_DELAY_SDIO_0_DELAY_MASK (0x7FEU) -#define FLASH_NMPA_SDIO_DELAY_SDIO_0_DELAY_SHIFT (1U) -/*! SDIO_0_DELAY - SDIO_0_DELAY (unit: 100 ps). - */ -#define FLASH_NMPA_SDIO_DELAY_SDIO_0_DELAY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_SDIO_DELAY_SDIO_0_DELAY_SHIFT)) & FLASH_NMPA_SDIO_DELAY_SDIO_0_DELAY_MASK) -/*! @} */ - -/*! @name AUX_BIAS_CURVE_AMBIENT_0 - */ -/*! @{ */ - -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_0_MASK (0xFFFFU) -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_0_SHIFT (0U) -/*! VREF1VCURVETRIM_0 - VREF1VCURVETRIM_0 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_0_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_0_MASK) - -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_1_MASK (0xFFFF0000U) -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_1_SHIFT (16U) -/*! VREF1VCURVETRIM_1 - VREF1VCURVETRIM_1 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_1_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_1_MASK) -/*! @} */ - -/*! @name AUX_BIAS_CURVE_AMBIENT_1 - */ -/*! @{ */ - -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_2_MASK (0xFFFFU) -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_2_SHIFT (0U) -/*! VREF1VCURVETRIM_2 - VREF1VCURVETRIM_2 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_2_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_2_MASK) - -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_3_MASK (0xFFFF0000U) -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_3_SHIFT (16U) -/*! VREF1VCURVETRIM_3 - VREF1VCURVETRIM_3 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_3_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_3_MASK) -/*! @} */ - -/*! @name AUX_BIAS_CURVE_AMBIENT_2 - */ -/*! @{ */ - -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_4_MASK (0xFFFFU) -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_4_SHIFT (0U) -/*! VREF1VCURVETRIM_4 - VREF1VCURVETRIM_4 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_4(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_4_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_4_MASK) - -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_5_MASK (0xFFFF0000U) -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_5_SHIFT (16U) -/*! VREF1VCURVETRIM_5 - VREF1VCURVETRIM_5 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_5(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_5_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_5_MASK) -/*! @} */ - -/*! @name AUX_BIAS_CURVE_AMBIENT_3 - */ -/*! @{ */ - -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_6_MASK (0xFFFFU) -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_6_SHIFT (0U) -/*! VREF1VCURVETRIM_6 - VREF1VCURVETRIM_6 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_6(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_6_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_6_MASK) - -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_7_MASK (0xFFFF0000U) -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_7_SHIFT (16U) -/*! VREF1VCURVETRIM_7 - VREF1VCURVETRIM_7 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_7(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_7_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_7_MASK) -/*! @} */ - -/*! @name AUX_BIAS_CURVE_AMBIENT_ARRAY - Aux Bias Curve Ambient (30degC) */ -/*! @{ */ - -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_ARRAY */ -#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_ARRAY_COUNT (4U) - -/*! @name AUX_BIAS_CURVE_TEMP_0 - */ -/*! @{ */ - -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_0_MASK (0xFFFFU) -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_0_SHIFT (0U) -/*! VREF1VCURVETRIM_0 - VREF1VCURVETRIM_0 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_0_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_0_MASK) - -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_1_MASK (0xFFFF0000U) -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_1_SHIFT (16U) -/*! VREF1VCURVETRIM_1 - VREF1VCURVETRIM_1 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_1_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_1_MASK) -/*! @} */ - -/*! @name AUX_BIAS_CURVE_TEMP_1 - */ -/*! @{ */ - -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_2_MASK (0xFFFFU) -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_2_SHIFT (0U) -/*! VREF1VCURVETRIM_2 - VREF1VCURVETRIM_2 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_2_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_2_MASK) - -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_3_MASK (0xFFFF0000U) -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_3_SHIFT (16U) -/*! VREF1VCURVETRIM_3 - VREF1VCURVETRIM_3 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_3_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_3_MASK) -/*! @} */ - -/*! @name AUX_BIAS_CURVE_TEMP_2 - */ -/*! @{ */ - -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_4_MASK (0xFFFFU) -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_4_SHIFT (0U) -/*! VREF1VCURVETRIM_4 - VREF1VCURVETRIM_4 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_4(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_4_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_4_MASK) - -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_5_MASK (0xFFFF0000U) -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_5_SHIFT (16U) -/*! VREF1VCURVETRIM_5 - VREF1VCURVETRIM_5 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_5(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_5_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_5_MASK) -/*! @} */ - -/*! @name AUX_BIAS_CURVE_TEMP_3 - */ -/*! @{ */ - -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_6_MASK (0xFFFFU) -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_6_SHIFT (0U) -/*! VREF1VCURVETRIM_6 - VREF1VCURVETRIM_6 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_6(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_6_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_6_MASK) - -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_7_MASK (0xFFFF0000U) -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_7_SHIFT (16U) -/*! VREF1VCURVETRIM_7 - VREF1VCURVETRIM_7 (unit: 100uV) - */ -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_7(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_7_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_7_MASK) -/*! @} */ - -/*! @name AUX_BIAS_CURVE_TEMP_ARRAY - Aux Bias Curve TEMP (105degC) */ -/*! @{ */ - -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_AUX_BIAS_CURVE_TEMP_ARRAY */ -#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_ARRAY_COUNT (4U) - -/*! @name TEMP_SENS_VBE1VBE8_REF_1 - */ -/*! @{ */ - -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE1_MASK (0xFFFFU) -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE1_SHIFT (0U) -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE1_SHIFT)) & FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE1_MASK) - -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE8_MASK (0xFFFF0000U) -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE8_SHIFT (16U) -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE8(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE8_SHIFT)) & FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE8_MASK) -/*! @} */ - -/*! @name TEMP_SENS_VBE1VBE8_REF_2 - */ -/*! @{ */ - -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE1_MASK (0xFFFFU) -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE1_SHIFT (0U) -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE1_SHIFT)) & FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE1_MASK) - -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE8_MASK (0xFFFF0000U) -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE8_SHIFT (16U) -#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE8(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE8_SHIFT)) & FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE8_MASK) -/*! @} */ - -/*! @name TEMP_SENS_SLOPE - */ -/*! @{ */ - -#define FLASH_NMPA_TEMP_SENS_SLOPE_VALID_MASK (0x1U) -#define FLASH_NMPA_TEMP_SENS_SLOPE_VALID_SHIFT (0U) -#define FLASH_NMPA_TEMP_SENS_SLOPE_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_SLOPE_VALID_SHIFT)) & FLASH_NMPA_TEMP_SENS_SLOPE_VALID_MASK) - -#define FLASH_NMPA_TEMP_SENS_SLOPE_SLOPE_x1024_MASK (0xFFFFFFFEU) -#define FLASH_NMPA_TEMP_SENS_SLOPE_SLOPE_x1024_SHIFT (1U) -/*! SLOPE_x1024 - SLOPE_x1024[30:0] - */ -#define FLASH_NMPA_TEMP_SENS_SLOPE_SLOPE_x1024(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_SLOPE_SLOPE_x1024_SHIFT)) & FLASH_NMPA_TEMP_SENS_SLOPE_SLOPE_x1024_MASK) -/*! @} */ - -/*! @name TEMP_SENS_OFFSET - */ -/*! @{ */ - -#define FLASH_NMPA_TEMP_SENS_OFFSET_VALID_MASK (0x1U) -#define FLASH_NMPA_TEMP_SENS_OFFSET_VALID_SHIFT (0U) -#define FLASH_NMPA_TEMP_SENS_OFFSET_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_OFFSET_VALID_SHIFT)) & FLASH_NMPA_TEMP_SENS_OFFSET_VALID_MASK) - -#define FLASH_NMPA_TEMP_SENS_OFFSET_OFFSET_x1024_MASK (0xFFFFFFFEU) -#define FLASH_NMPA_TEMP_SENS_OFFSET_OFFSET_x1024_SHIFT (1U) -/*! OFFSET_x1024 - OFFSET_x1024[30:0] - */ -#define FLASH_NMPA_TEMP_SENS_OFFSET_OFFSET_x1024(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_OFFSET_OFFSET_x1024_SHIFT)) & FLASH_NMPA_TEMP_SENS_OFFSET_OFFSET_x1024_MASK) -/*! @} */ - -/*! @name PVT_MONITOR_0_RINGO - */ -/*! @{ */ - -#define FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_VALID_MASK (0x1U) -#define FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_VALID_SHIFT (0U) -#define FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_VALID_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_VALID_MASK) - -#define FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_FREQ_HZ_MASK (0xFFFFFFFEU) -#define FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_FREQ_HZ_SHIFT (1U) -#define FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_FREQ_HZ(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_FREQ_HZ_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_FREQ_HZ_MASK) -/*! @} */ - -/*! @name PVT_MONITOR_0_DELAYS_LSB - */ -/*! @{ */ - -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_VALID_MASK (0x1U) -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_VALID_SHIFT (0U) -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_VALID_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_VALID_MASK) - -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_0_MASK (0x7FEU) -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_0_SHIFT (1U) -/*! DELAY_0 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_0_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_0_MASK) - -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_1_MASK (0x1FF800U) -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_1_SHIFT (11U) -/*! DELAY_1 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_1_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_1_MASK) - -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_2_MASK (0x7FE00000U) -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_2_SHIFT (21U) -/*! DELAY_2 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_2_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_2_MASK) -/*! @} */ - -/*! @name PVT_MONITOR_0_DELAYS_MSB - */ -/*! @{ */ - -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_3_MASK (0x3FFU) -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_3_SHIFT (0U) -/*! DELAY_3 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_3_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_3_MASK) - -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_4_MASK (0xFFC00U) -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_4_SHIFT (10U) -/*! DELAY_4 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_4(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_4_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_4_MASK) - -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_5_MASK (0x3FF00000U) -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_5_SHIFT (20U) -/*! DELAY_5 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_5(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_5_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_5_MASK) -/*! @} */ - -/*! @name PVT_MONITOR_0_ARRAY - */ -/*! @{ */ - -#define FLASH_NMPA_PVT_MONITOR_0_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_PVT_MONITOR_0_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_PVT_MONITOR_0_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_PVT_MONITOR_0_ARRAY */ -#define FLASH_NMPA_PVT_MONITOR_0_ARRAY_COUNT (3U) - -/*! @name PVT_MONITOR_1_RINGO - */ -/*! @{ */ - -#define FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_VALID_MASK (0x1U) -#define FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_VALID_SHIFT (0U) -#define FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_VALID_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_VALID_MASK) - -#define FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_FREQ_HZ_MASK (0xFFFFFFFEU) -#define FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_FREQ_HZ_SHIFT (1U) -#define FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_FREQ_HZ(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_FREQ_HZ_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_FREQ_HZ_MASK) -/*! @} */ - -/*! @name PVT_MONITOR_1_DELAYS_LSB - */ -/*! @{ */ - -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_VALID_MASK (0x1U) -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_VALID_SHIFT (0U) -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_VALID_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_VALID_MASK) - -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_0_MASK (0x7FEU) -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_0_SHIFT (1U) -/*! DELAY_0 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_0_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_0_MASK) - -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_1_MASK (0x1FF800U) -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_1_SHIFT (11U) -/*! DELAY_1 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_1_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_1_MASK) - -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_2_MASK (0x7FE00000U) -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_2_SHIFT (21U) -/*! DELAY_2 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_2_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_2_MASK) -/*! @} */ - -/*! @name PVT_MONITOR_1_DELAYS_MSB - */ -/*! @{ */ - -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_3_MASK (0x3FFU) -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_3_SHIFT (0U) -/*! DELAY_3 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_3_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_3_MASK) - -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_4_MASK (0xFFC00U) -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_4_SHIFT (10U) -/*! DELAY_4 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_4(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_4_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_4_MASK) - -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_5_MASK (0x3FF00000U) -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_5_SHIFT (20U) -/*! DELAY_5 - Delay in us. - */ -#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_5(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_5_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_5_MASK) -/*! @} */ - -/*! @name PVT_MONITOR_1_ARRAY - */ -/*! @{ */ - -#define FLASH_NMPA_PVT_MONITOR_1_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_PVT_MONITOR_1_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_PVT_MONITOR_1_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_PVT_MONITOR_1_ARRAY */ -#define FLASH_NMPA_PVT_MONITOR_1_ARRAY_COUNT (3U) - -/*! @name NXP_DEVICE_PRIVATE_KEY - */ -/*! @{ */ - -#define FLASH_NMPA_NXP_DEVICE_PRIVATE_KEY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_NXP_DEVICE_PRIVATE_KEY_FIELD_SHIFT (0U) -#define FLASH_NMPA_NXP_DEVICE_PRIVATE_KEY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_NXP_DEVICE_PRIVATE_KEY_FIELD_SHIFT)) & FLASH_NMPA_NXP_DEVICE_PRIVATE_KEY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_NXP_DEVICE_PRIVATE_KEY */ -#define FLASH_NMPA_NXP_DEVICE_PRIVATE_KEY_COUNT (13U) - -/*! @name NXP_DEVICE_CERTIFICATE_0 - NXP Device Certificate (ECDSA_sign - r[255:128]) */ -/*! @{ */ - -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_0_FIELD_SHIFT (0U) -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_NXP_DEVICE_CERTIFICATE_0_FIELD_SHIFT)) & FLASH_NMPA_NXP_DEVICE_CERTIFICATE_0_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_NXP_DEVICE_CERTIFICATE_0 */ -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_0_COUNT (4U) - -/*! @name NXP_DEVICE_CERTIFICATE_1 - NXP Device Certificate (ECDSA_sign - r[127:0]) */ -/*! @{ */ - -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_1_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_1_FIELD_SHIFT (0U) -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_NXP_DEVICE_CERTIFICATE_1_FIELD_SHIFT)) & FLASH_NMPA_NXP_DEVICE_CERTIFICATE_1_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_NXP_DEVICE_CERTIFICATE_1 */ -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_1_COUNT (4U) - -/*! @name NXP_DEVICE_CERTIFICATE_2 - NXP Device Certificate (ECDSA_sign - s[255:128]) */ -/*! @{ */ - -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_2_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_2_FIELD_SHIFT (0U) -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_NXP_DEVICE_CERTIFICATE_2_FIELD_SHIFT)) & FLASH_NMPA_NXP_DEVICE_CERTIFICATE_2_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_NXP_DEVICE_CERTIFICATE_2 */ -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_2_COUNT (4U) - -/*! @name NXP_DEVICE_CERTIFICATE_3 - NXP Device Certificate (ECDSA_sign - s[127:0]) */ -/*! @{ */ - -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_3_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_3_FIELD_SHIFT (0U) -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_NXP_DEVICE_CERTIFICATE_3_FIELD_SHIFT)) & FLASH_NMPA_NXP_DEVICE_CERTIFICATE_3_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_NXP_DEVICE_CERTIFICATE_3 */ -#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_3_COUNT (4U) - -/*! @name SHA256_DIGEST - SHA-256 DIGEST (9EC00 - 9FDBC) ROM Patch Area + NXP Area (IMPORTANT NOTE: Pages used for Repair (N-8 to N-3) are excluded from the computation) SHA256_DIGEST0 for DIGEST[31:0]..SHA-256 DIGEST (9EC00 - 9FDBC) ROM Patch Area + NXP Area (IMPORTANT NOTE: Pages used for Repair (N-8 to N-3) are excluded from the computation) SHA256_DIGEST7 for DIGEST[255:224] */ -/*! @{ */ - -#define FLASH_NMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_SHA256_DIGEST_FIELD_SHIFT (0U) -#define FLASH_NMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_NMPA_SHA256_DIGEST_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_SHA256_DIGEST */ -#define FLASH_NMPA_SHA256_DIGEST_COUNT (8U) - -/*! @name ECID_BACKUP_0 - */ -/*! @{ */ - -#define FLASH_NMPA_ECID_BACKUP_0_COORD_Y_MASK (0xFFFFU) -#define FLASH_NMPA_ECID_BACKUP_0_COORD_Y_SHIFT (0U) -#define FLASH_NMPA_ECID_BACKUP_0_COORD_Y(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_ECID_BACKUP_0_COORD_Y_SHIFT)) & FLASH_NMPA_ECID_BACKUP_0_COORD_Y_MASK) - -#define FLASH_NMPA_ECID_BACKUP_0_COORD_X_MASK (0xFFFF0000U) -#define FLASH_NMPA_ECID_BACKUP_0_COORD_X_SHIFT (16U) -#define FLASH_NMPA_ECID_BACKUP_0_COORD_X(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_ECID_BACKUP_0_COORD_X_SHIFT)) & FLASH_NMPA_ECID_BACKUP_0_COORD_X_MASK) -/*! @} */ - -/*! @name ECID_BACKUP_1 - */ -/*! @{ */ - -#define FLASH_NMPA_ECID_BACKUP_1_WAFER_MASK (0xFFU) -#define FLASH_NMPA_ECID_BACKUP_1_WAFER_SHIFT (0U) -#define FLASH_NMPA_ECID_BACKUP_1_WAFER(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_ECID_BACKUP_1_WAFER_SHIFT)) & FLASH_NMPA_ECID_BACKUP_1_WAFER_MASK) -/*! @} */ - -/*! @name ECID_BACKUP_2 - */ -/*! @{ */ - -#define FLASH_NMPA_ECID_BACKUP_2_LOTID_LSB_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_ECID_BACKUP_2_LOTID_LSB_SHIFT (0U) -#define FLASH_NMPA_ECID_BACKUP_2_LOTID_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_ECID_BACKUP_2_LOTID_LSB_SHIFT)) & FLASH_NMPA_ECID_BACKUP_2_LOTID_LSB_MASK) -/*! @} */ - -/*! @name ECID_BACKUP_3 - */ -/*! @{ */ - -#define FLASH_NMPA_ECID_BACKUP_3_LOTID_MSB_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_ECID_BACKUP_3_LOTID_MSB_SHIFT (0U) -#define FLASH_NMPA_ECID_BACKUP_3_LOTID_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_ECID_BACKUP_3_LOTID_MSB_SHIFT)) & FLASH_NMPA_ECID_BACKUP_3_LOTID_MSB_MASK) -/*! @} */ - -/*! @name ECID_BACKUP_ARRAY - ECID backup (the original is in page n-1) */ -/*! @{ */ - -#define FLASH_NMPA_ECID_BACKUP_ARRAY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_ECID_BACKUP_ARRAY_FIELD_SHIFT (0U) -#define FLASH_NMPA_ECID_BACKUP_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_ECID_BACKUP_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_ECID_BACKUP_ARRAY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_NMPA_ECID_BACKUP_ARRAY */ -#define FLASH_NMPA_ECID_BACKUP_ARRAY_COUNT (4U) - -/* The count of FLASH_NMPA_CHECKSUM */ -#define FLASH_NMPA_CHECKSUM_COUNT (4U) - -/*! @name DIS_ROM_HIDING - */ -/*! @{ */ - -#define FLASH_NMPA_DIS_ROM_HIDING_DIS_ROM_HIDING_MASK (0xFFFFFFFFU) -#define FLASH_NMPA_DIS_ROM_HIDING_DIS_ROM_HIDING_SHIFT (0U) -/*! DIS_ROM_HIDING - When 0x3CC35AA5 ROM hiding feture is disabled. All other values critical ROM is hidden. - */ -#define FLASH_NMPA_DIS_ROM_HIDING_DIS_ROM_HIDING(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DIS_ROM_HIDING_DIS_ROM_HIDING_SHIFT)) & FLASH_NMPA_DIS_ROM_HIDING_DIS_ROM_HIDING_MASK) -/*! @} */ - -/*! @name PUF_SRAM - */ -/*! @{ */ - -#define FLASH_NMPA_PUF_SRAM_PUF_SRAM_VALID_MASK (0x1U) -#define FLASH_NMPA_PUF_SRAM_PUF_SRAM_VALID_SHIFT (0U) -/*! PUF_SRAM_VALID - 1: PUF_SRAM is valid. - */ -#define FLASH_NMPA_PUF_SRAM_PUF_SRAM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_PUF_SRAM_VALID_SHIFT)) & FLASH_NMPA_PUF_SRAM_PUF_SRAM_VALID_MASK) - -#define FLASH_NMPA_PUF_SRAM_mode_MASK (0x2U) -#define FLASH_NMPA_PUF_SRAM_mode_SHIFT (1U) -/*! mode - PUF SRAM Controller operating mode - */ -#define FLASH_NMPA_PUF_SRAM_mode(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_mode_SHIFT)) & FLASH_NMPA_PUF_SRAM_mode_MASK) - -#define FLASH_NMPA_PUF_SRAM_ckgating_MASK (0x4U) -#define FLASH_NMPA_PUF_SRAM_ckgating_SHIFT (2U) -/*! ckgating - PUF SRAM Clock Gating control - */ -#define FLASH_NMPA_PUF_SRAM_ckgating(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_ckgating_SHIFT)) & FLASH_NMPA_PUF_SRAM_ckgating_MASK) - -#define FLASH_NMPA_PUF_SRAM_SMB_MASK (0x300U) -#define FLASH_NMPA_PUF_SRAM_SMB_SHIFT (8U) -/*! SMB - Source Biasing voltage. - * 0b00..Low leakage. - * 0b01..Medium leakage. - * 0b10..Highest leakage. - * 0b11..Disable. - */ -#define FLASH_NMPA_PUF_SRAM_SMB(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_SMB_SHIFT)) & FLASH_NMPA_PUF_SRAM_SMB_MASK) - -#define FLASH_NMPA_PUF_SRAM_RM_MASK (0x1C00U) -#define FLASH_NMPA_PUF_SRAM_RM_SHIFT (10U) -/*! RM - Read Margin control settings. - */ -#define FLASH_NMPA_PUF_SRAM_RM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_RM_SHIFT)) & FLASH_NMPA_PUF_SRAM_RM_MASK) - -#define FLASH_NMPA_PUF_SRAM_WM_MASK (0xE000U) -#define FLASH_NMPA_PUF_SRAM_WM_SHIFT (13U) -/*! WM - Write Margin control settings. - */ -#define FLASH_NMPA_PUF_SRAM_WM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_WM_SHIFT)) & FLASH_NMPA_PUF_SRAM_WM_MASK) - -#define FLASH_NMPA_PUF_SRAM_WRME_MASK (0x10000U) -#define FLASH_NMPA_PUF_SRAM_WRME_SHIFT (16U) -/*! WRME - Write read margin enable. - */ -#define FLASH_NMPA_PUF_SRAM_WRME(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_WRME_SHIFT)) & FLASH_NMPA_PUF_SRAM_WRME_MASK) - -#define FLASH_NMPA_PUF_SRAM_RAEN_MASK (0x20000U) -#define FLASH_NMPA_PUF_SRAM_RAEN_SHIFT (17U) -/*! RAEN - SRAM Read Assist Enable - */ -#define FLASH_NMPA_PUF_SRAM_RAEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_RAEN_SHIFT)) & FLASH_NMPA_PUF_SRAM_RAEN_MASK) - -#define FLASH_NMPA_PUF_SRAM_RAM_MASK (0x3C0000U) -#define FLASH_NMPA_PUF_SRAM_RAM_SHIFT (18U) -/*! RAM - SRAM Read Assist settings - */ -#define FLASH_NMPA_PUF_SRAM_RAM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_RAM_SHIFT)) & FLASH_NMPA_PUF_SRAM_RAM_MASK) - -#define FLASH_NMPA_PUF_SRAM_WAEN_MASK (0x400000U) -#define FLASH_NMPA_PUF_SRAM_WAEN_SHIFT (22U) -/*! WAEN - SRAM Write Assist Enable - */ -#define FLASH_NMPA_PUF_SRAM_WAEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_WAEN_SHIFT)) & FLASH_NMPA_PUF_SRAM_WAEN_MASK) - -#define FLASH_NMPA_PUF_SRAM_WAM_MASK (0x1800000U) -#define FLASH_NMPA_PUF_SRAM_WAM_SHIFT (23U) -/*! WAM - SRAM Write Assist settings - */ -#define FLASH_NMPA_PUF_SRAM_WAM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_WAM_SHIFT)) & FLASH_NMPA_PUF_SRAM_WAM_MASK) - -#define FLASH_NMPA_PUF_SRAM_STBP_MASK (0x2000000U) -#define FLASH_NMPA_PUF_SRAM_STBP_SHIFT (25U) -/*! STBP - STBP - */ -#define FLASH_NMPA_PUF_SRAM_STBP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_STBP_SHIFT)) & FLASH_NMPA_PUF_SRAM_STBP_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLASH_NMPA_Register_Masks */ - - -/* FLASH_NMPA - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH_NMPA base address */ - #define FLASH_NMPA_BASE (0x1003FC00u) - /** Peripheral FLASH_NMPA base address */ - #define FLASH_NMPA_BASE_NS (0x3FC00u) - /** Peripheral FLASH_NMPA base pointer */ - #define FLASH_NMPA ((FLASH_NMPA_Type *)FLASH_NMPA_BASE) - /** Peripheral FLASH_NMPA base pointer */ - #define FLASH_NMPA_NS ((FLASH_NMPA_Type *)FLASH_NMPA_BASE_NS) - /** Array initializer of FLASH_NMPA peripheral base addresses */ - #define FLASH_NMPA_BASE_ADDRS { FLASH_NMPA_BASE } - /** Array initializer of FLASH_NMPA peripheral base pointers */ - #define FLASH_NMPA_BASE_PTRS { FLASH_NMPA } - /** Array initializer of FLASH_NMPA peripheral base addresses */ - #define FLASH_NMPA_BASE_ADDRS_NS { FLASH_NMPA_BASE_NS } - /** Array initializer of FLASH_NMPA peripheral base pointers */ - #define FLASH_NMPA_BASE_PTRS_NS { FLASH_NMPA_NS } -#else - /** Peripheral FLASH_NMPA base address */ - #define FLASH_NMPA_BASE (0x3FC00u) - /** Peripheral FLASH_NMPA base pointer */ - #define FLASH_NMPA ((FLASH_NMPA_Type *)FLASH_NMPA_BASE) - /** Array initializer of FLASH_NMPA peripheral base addresses */ - #define FLASH_NMPA_BASE_ADDRS { FLASH_NMPA_BASE } - /** Array initializer of FLASH_NMPA peripheral base pointers */ - #define FLASH_NMPA_BASE_PTRS { FLASH_NMPA } -#endif - -/*! - * @} - */ /* end of group FLASH_NMPA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_ROMPATCH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_ROMPATCH_Peripheral_Access_Layer FLASH_ROMPATCH Peripheral Access Layer - * @{ - */ - -/** FLASH_ROMPATCH - Register Layout Typedef */ -typedef struct { - __IO uint32_t HEADER; /**< ., offset: 0x0 */ - __IO uint32_t PATCH[255]; /**< ., array offset: 0x4, array step: 0x4 */ -} FLASH_ROMPATCH_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_ROMPATCH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_ROMPATCH_Register_Masks FLASH_ROMPATCH Register Masks - * @{ - */ - -/*! @name HEADER - . */ -/*! @{ */ - -#define FLASH_ROMPATCH_HEADER_ENTRIES_MASK (0xFFU) -#define FLASH_ROMPATCH_HEADER_ENTRIES_SHIFT (0U) -/*! ENTRIES - . - */ -#define FLASH_ROMPATCH_HEADER_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ROMPATCH_HEADER_ENTRIES_SHIFT)) & FLASH_ROMPATCH_HEADER_ENTRIES_MASK) - -#define FLASH_ROMPATCH_HEADER_SUB_TYPE_MASK (0xFF00U) -#define FLASH_ROMPATCH_HEADER_SUB_TYPE_SHIFT (8U) -/*! SUB_TYPE - . - */ -#define FLASH_ROMPATCH_HEADER_SUB_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ROMPATCH_HEADER_SUB_TYPE_SHIFT)) & FLASH_ROMPATCH_HEADER_SUB_TYPE_MASK) - -#define FLASH_ROMPATCH_HEADER_TYPE_MASK (0xFF0000U) -#define FLASH_ROMPATCH_HEADER_TYPE_SHIFT (16U) -/*! TYPE - . - */ -#define FLASH_ROMPATCH_HEADER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ROMPATCH_HEADER_TYPE_SHIFT)) & FLASH_ROMPATCH_HEADER_TYPE_MASK) - -#define FLASH_ROMPATCH_HEADER_IDENTIFIER_MASK (0xFF000000U) -#define FLASH_ROMPATCH_HEADER_IDENTIFIER_SHIFT (24U) -/*! IDENTIFIER - . - */ -#define FLASH_ROMPATCH_HEADER_IDENTIFIER(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ROMPATCH_HEADER_IDENTIFIER_SHIFT)) & FLASH_ROMPATCH_HEADER_IDENTIFIER_MASK) -/*! @} */ - -/*! @name PATCH - . */ -/*! @{ */ - -#define FLASH_ROMPATCH_PATCH_PATCH_MASK (0xFFFFFFFFU) -#define FLASH_ROMPATCH_PATCH_PATCH_SHIFT (0U) -/*! PATCH - . - */ -#define FLASH_ROMPATCH_PATCH_PATCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ROMPATCH_PATCH_PATCH_SHIFT)) & FLASH_ROMPATCH_PATCH_PATCH_MASK) -/*! @} */ - -/* The count of FLASH_ROMPATCH_PATCH */ -#define FLASH_ROMPATCH_PATCH_COUNT (255U) - - -/*! - * @} - */ /* end of group FLASH_ROMPATCH_Register_Masks */ - - -/* FLASH_ROMPATCH - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH_ROMPATCH base address */ - #define FLASH_ROMPATCH_BASE (0x1003EC00u) - /** Peripheral FLASH_ROMPATCH base address */ - #define FLASH_ROMPATCH_BASE_NS (0x3EC00u) - /** Peripheral FLASH_ROMPATCH base pointer */ - #define FLASH_ROMPATCH ((FLASH_ROMPATCH_Type *)FLASH_ROMPATCH_BASE) - /** Peripheral FLASH_ROMPATCH base pointer */ - #define FLASH_ROMPATCH_NS ((FLASH_ROMPATCH_Type *)FLASH_ROMPATCH_BASE_NS) - /** Array initializer of FLASH_ROMPATCH peripheral base addresses */ - #define FLASH_ROMPATCH_BASE_ADDRS { FLASH_ROMPATCH_BASE } - /** Array initializer of FLASH_ROMPATCH peripheral base pointers */ - #define FLASH_ROMPATCH_BASE_PTRS { FLASH_ROMPATCH } - /** Array initializer of FLASH_ROMPATCH peripheral base addresses */ - #define FLASH_ROMPATCH_BASE_ADDRS_NS { FLASH_ROMPATCH_BASE_NS } - /** Array initializer of FLASH_ROMPATCH peripheral base pointers */ - #define FLASH_ROMPATCH_BASE_PTRS_NS { FLASH_ROMPATCH_NS } -#else - /** Peripheral FLASH_ROMPATCH base address */ - #define FLASH_ROMPATCH_BASE (0x3EC00u) - /** Peripheral FLASH_ROMPATCH base pointer */ - #define FLASH_ROMPATCH ((FLASH_ROMPATCH_Type *)FLASH_ROMPATCH_BASE) - /** Array initializer of FLASH_ROMPATCH peripheral base addresses */ - #define FLASH_ROMPATCH_BASE_ADDRS { FLASH_ROMPATCH_BASE } - /** Array initializer of FLASH_ROMPATCH peripheral base pointers */ - #define FLASH_ROMPATCH_BASE_PTRS { FLASH_ROMPATCH } -#endif - -/*! - * @} - */ /* end of group FLASH_ROMPATCH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer - * @{ - */ - -/** FLEXCOMM - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4088]; - __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ - __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ -} FLEXCOMM_Type; - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks - * @{ - */ - -/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ -/*! @{ */ - -#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) -#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) -/*! PERSEL - Peripheral Select. This field is writable by software. - * 0b000..No peripheral selected. - * 0b001..USART function selected. - * 0b010..SPI function selected. - * 0b011..I2C function selected. - * 0b100..I2S transmit function selected. - * 0b101..I2S receive function selected. - * 0b110..Reserved - * 0b111..Reserved - */ -#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) - -#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) -#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) -/*! LOCK - Lock the peripheral select. This field is writable by software. - * 0b0..Peripheral select can be changed by software. - * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. - */ -#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) - -#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) -#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) -/*! USARTPRESENT - USART present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the USART function. - * 0b1..This Flexcomm includes the USART function. - */ -#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) - -#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) -#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) -/*! SPIPRESENT - SPI present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the SPI function. - * 0b1..This Flexcomm includes the SPI function. - */ -#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) - -#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) -#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) -/*! I2CPRESENT - I2C present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the I2C function. - * 0b1..This Flexcomm includes the I2C function. - */ -#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) - -#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) -#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) -/*! I2SPRESENT - I 2S present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the I2S function. - * 0b1..This Flexcomm includes the I2S function. - */ -#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) - -#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) -#define FLEXCOMM_PSELID_ID_SHIFT (12U) -/*! ID - Flexcomm ID. - */ -#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) -/*! @} */ - -/*! @name PID - Peripheral identification register. */ -/*! @{ */ - -#define FLEXCOMM_PID_APERTURE_MASK (0xFFU) -#define FLEXCOMM_PID_APERTURE_SHIFT (0U) -/*! APERTURE - size aperture for the register port on the bus (APB or AHB). - */ -#define FLEXCOMM_PID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_APERTURE_SHIFT)) & FLEXCOMM_PID_APERTURE_MASK) - -#define FLEXCOMM_PID_MINOR_REV_MASK (0xF00U) -#define FLEXCOMM_PID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation. - */ -#define FLEXCOMM_PID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MINOR_REV_SHIFT)) & FLEXCOMM_PID_MINOR_REV_MASK) - -#define FLEXCOMM_PID_MAJOR_REV_MASK (0xF000U) -#define FLEXCOMM_PID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation. - */ -#define FLEXCOMM_PID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MAJOR_REV_SHIFT)) & FLEXCOMM_PID_MAJOR_REV_MASK) - -#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) -#define FLEXCOMM_PID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function. - */ -#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLEXCOMM_Register_Masks */ - - -/* FLEXCOMM - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE (0x50086000u) - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE_NS (0x40086000u) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE (0x50087000u) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE_NS (0x40087000u) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE (0x50088000u) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE_NS (0x40088000u) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE (0x50089000u) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE_NS (0x40089000u) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE (0x5008A000u) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE_NS (0x4008A000u) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE (0x50096000u) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE_NS (0x40096000u) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE (0x50097000u) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE_NS (0x40097000u) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE (0x50098000u) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE_NS (0x40098000u) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE (0x5009F000u) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE_NS (0x4009F000u) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS) - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS_NS { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS_NS { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS } -#else - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE (0x40086000u) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE (0x40087000u) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE (0x40088000u) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE (0x40089000u) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE (0x4008A000u) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE (0x40096000u) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE (0x40097000u) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE (0x40098000u) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE (0x4009F000u) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } -#endif -/** Interrupt vectors for the FLEXCOMM peripheral type */ -#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } - -/*! - * @} - */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer - * @{ - */ - -/** GINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ - uint8_t RESERVED_0[28]; - __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[24]; - __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ -} GINT_Type; - -/* ---------------------------------------------------------------------------- - -- GINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Register_Masks GINT Register Masks - * @{ - */ - -/*! @name CTRL - GPIO grouped interrupt control register */ -/*! @{ */ - -#define GINT_CTRL_INT_MASK (0x1U) -#define GINT_CTRL_INT_SHIFT (0U) -/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. - * 0b0..No request. No interrupt request is pending. - * 0b1..Request active. Interrupt request is active. - */ -#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) - -#define GINT_CTRL_COMB_MASK (0x2U) -#define GINT_CTRL_COMB_SHIFT (1U) -/*! COMB - Combine enabled inputs for group interrupt - * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). - * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). - */ -#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) - -#define GINT_CTRL_TRIG_MASK (0x4U) -#define GINT_CTRL_TRIG_SHIFT (2U) -/*! TRIG - Group interrupt trigger - * 0b0..Edge-triggered. - * 0b1..Level-triggered. - */ -#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) -/*! @} */ - -/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ -/*! @{ */ - -#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) -#define GINT_PORT_POL_POL_SHIFT (0U) -/*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n - * of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to - * the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin - * contributes to the group interrupt. - */ -#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) -/*! @} */ - -/* The count of GINT_PORT_POL */ -#define GINT_PORT_POL_COUNT (2U) - -/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ -/*! @{ */ - -#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) -#define GINT_PORT_ENA_ENA_SHIFT (0U) -/*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the - * port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is - * enabled and contributes to the grouped interrupt. - */ -#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) -/*! @} */ - -/* The count of GINT_PORT_ENA */ -#define GINT_PORT_ENA_COUNT (2U) - - -/*! - * @} - */ /* end of group GINT_Register_Masks */ - - -/* GINT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral GINT0 base address */ - #define GINT0_BASE (0x50002000u) - /** Peripheral GINT0 base address */ - #define GINT0_BASE_NS (0x40002000u) - /** Peripheral GINT0 base pointer */ - #define GINT0 ((GINT_Type *)GINT0_BASE) - /** Peripheral GINT0 base pointer */ - #define GINT0_NS ((GINT_Type *)GINT0_BASE_NS) - /** Peripheral GINT1 base address */ - #define GINT1_BASE (0x50003000u) - /** Peripheral GINT1 base address */ - #define GINT1_BASE_NS (0x40003000u) - /** Peripheral GINT1 base pointer */ - #define GINT1 ((GINT_Type *)GINT1_BASE) - /** Peripheral GINT1 base pointer */ - #define GINT1_NS ((GINT_Type *)GINT1_BASE_NS) - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS { GINT0, GINT1 } - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS_NS { GINT0_BASE_NS, GINT1_BASE_NS } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS_NS { GINT0_NS, GINT1_NS } -#else - /** Peripheral GINT0 base address */ - #define GINT0_BASE (0x40002000u) - /** Peripheral GINT0 base pointer */ - #define GINT0 ((GINT_Type *)GINT0_BASE) - /** Peripheral GINT1 base address */ - #define GINT1_BASE (0x40003000u) - /** Peripheral GINT1 base pointer */ - #define GINT1 ((GINT_Type *)GINT1_BASE) - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS { GINT0, GINT1 } -#endif -/** Interrupt vectors for the GINT peripheral type */ -#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } - -/*! - * @} - */ /* end of group GINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer - * @{ - */ - -/** GPIO - Register Layout Typedef */ -typedef struct { - __IO uint8_t B[2][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ - uint8_t RESERVED_0[4032]; - __IO uint32_t W[2][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ - uint8_t RESERVED_1[3840]; - __IO uint32_t DIR[2]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */ - uint8_t RESERVED_2[120]; - __IO uint32_t MASK[2]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */ - uint8_t RESERVED_3[120]; - __IO uint32_t PIN[2]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */ - uint8_t RESERVED_4[120]; - __IO uint32_t MPIN[2]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */ - uint8_t RESERVED_5[120]; - __IO uint32_t SET[2]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */ - uint8_t RESERVED_6[120]; - __O uint32_t CLR[2]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */ - uint8_t RESERVED_7[120]; - __O uint32_t NOT[2]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */ - uint8_t RESERVED_8[120]; - __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ - uint8_t RESERVED_9[120]; - __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ - uint8_t RESERVED_10[120]; - __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ -} GPIO_Type; - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/*! @name B - Byte pin registers for all port GPIO pins */ -/*! @{ */ - -#define GPIO_B_PBYTE_MASK (0x1U) -#define GPIO_B_PBYTE_SHIFT (0U) -/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, - * except that pins configured as analog I/O always read as 0. One register for each port pin. - * Supported pins depends on the specific device and package. Write: loads the pin's output bit. - * One register for each port pin. Supported pins depends on the specific device and package. - */ -#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) -/*! @} */ - -/* The count of GPIO_B */ -#define GPIO_B_COUNT (2U) - -/* The count of GPIO_B */ -#define GPIO_B_COUNT2 (32U) - -/*! @name W - Word pin registers for all port GPIO pins */ -/*! @{ */ - -#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) -#define GPIO_W_PWORD_SHIFT (0U) -/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is - * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be - * read. Writing any value other than 0 will set the output bit. One register for each port pin. - * Supported pins depends on the specific device and package. - */ -#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) -/*! @} */ - -/* The count of GPIO_W */ -#define GPIO_W_COUNT (2U) - -/* The count of GPIO_W */ -#define GPIO_W_COUNT2 (32U) - -/*! @name DIR - Direction registers for all port GPIO pins */ -/*! @{ */ - -#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) -#define GPIO_DIR_DIRP_SHIFT (0U) -/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported - * pins depends on the specific device and package. 0 = input. 1 = output. - */ -#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) -/*! @} */ - -/* The count of GPIO_DIR */ -#define GPIO_DIR_COUNT (2U) - -/*! @name MASK - Mask register for all port GPIO pins */ -/*! @{ */ - -#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) -#define GPIO_MASK_MASKP_SHIFT (0U) -/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = - * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = - * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit - * not affected. - */ -#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) -/*! @} */ - -/* The count of GPIO_MASK */ -#define GPIO_MASK_COUNT (2U) - -/*! @name PIN - Port pin register for all port GPIO pins */ -/*! @{ */ - -#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) -#define GPIO_PIN_PORT_SHIFT (0U) -/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported - * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. - * 1 = Read: pin is high; write: set output bit. - */ -#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) -/*! @} */ - -/* The count of GPIO_PIN */ -#define GPIO_PIN_COUNT (2U) - -/*! @name MPIN - Masked port register for all port GPIO pins */ -/*! @{ */ - -#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) -#define GPIO_MPIN_MPORTP_SHIFT (0U) -/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on - * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK - * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 - * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit - * if the corresponding bit in the MASK register is 0. - */ -#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) -/*! @} */ - -/* The count of GPIO_MPIN */ -#define GPIO_MPIN_COUNT (2U) - -/*! @name SET - Write: Set register for port. Read: output bits for port */ -/*! @{ */ - -#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) -#define GPIO_SET_SETP_SHIFT (0U) -/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on - * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output - * bit; write: set output bit. - */ -#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) -/*! @} */ - -/* The count of GPIO_SET */ -#define GPIO_SET_COUNT (2U) - -/*! @name CLR - Clear port for all port GPIO pins */ -/*! @{ */ - -#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) -#define GPIO_CLR_CLRP_SHIFT (0U) -/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the - * specific device and package. 0 = No operation. 1 = Clear output bit. - */ -#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) -/*! @} */ - -/* The count of GPIO_CLR */ -#define GPIO_CLR_COUNT (2U) - -/*! @name NOT - Toggle port for all port GPIO pins */ -/*! @{ */ - -#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) -#define GPIO_NOT_NOTP_SHIFT (0U) -/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the - * specific device and package. 0 = no operation. 1 = Toggle output bit. - */ -#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) -/*! @} */ - -/* The count of GPIO_NOT */ -#define GPIO_NOT_COUNT (2U) - -/*! @name DIRSET - Set pin direction bits for port */ -/*! @{ */ - -#define GPIO_DIRSET_DIRSETP_MASK (0xFFFFFFFFU) -#define GPIO_DIRSET_DIRSETP_SHIFT (0U) -/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on - * the specific device and package. 0 = No operation. 1 = Set direction bit. - */ -#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) -/*! @} */ - -/* The count of GPIO_DIRSET */ -#define GPIO_DIRSET_COUNT (2U) - -/*! @name DIRCLR - Clear pin direction bits for port */ -/*! @{ */ - -#define GPIO_DIRCLR_DIRCLRP_MASK (0xFFFFFFFFU) -#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) -/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on - * the specific device and package. 0 = No operation. 1 = Clear direction bit. - */ -#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) -/*! @} */ - -/* The count of GPIO_DIRCLR */ -#define GPIO_DIRCLR_COUNT (2U) - -/*! @name DIRNOT - Toggle pin direction bits for port */ -/*! @{ */ - -#define GPIO_DIRNOT_DIRNOTP_MASK (0xFFFFFFFFU) -#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) -/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends - * on the specific device and package. 0 = no operation. 1 = Toggle direction bit. - */ -#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) -/*! @} */ - -/* The count of GPIO_DIRNOT */ -#define GPIO_DIRNOT_COUNT (2U) - - -/*! - * @} - */ /* end of group GPIO_Register_Masks */ - - -/* GPIO - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral GPIO base address */ - #define GPIO_BASE (0x5008C000u) - /** Peripheral GPIO base address */ - #define GPIO_BASE_NS (0x4008C000u) - /** Peripheral GPIO base pointer */ - #define GPIO ((GPIO_Type *)GPIO_BASE) - /** Peripheral GPIO base pointer */ - #define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE (0x500A8000u) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE_NS (0x400A8000u) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS) - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO, SECGPIO } - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS_NS { GPIO_BASE_NS, SECGPIO_BASE_NS } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS_NS { GPIO_NS, SECGPIO_NS } -#else - /** Peripheral GPIO base address */ - #define GPIO_BASE (0x4008C000u) - /** Peripheral GPIO base pointer */ - #define GPIO ((GPIO_Type *)GPIO_BASE) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE (0x400A8000u) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO, SECGPIO } -#endif - -/*! - * @} - */ /* end of group GPIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- HASHCRYPT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup HASHCRYPT_Peripheral_Access_Layer HASHCRYPT Peripheral Access Layer - * @{ - */ - -/** HASHCRYPT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register to enable and operate Hash and Crypto, offset: 0x0 */ - __IO uint32_t STATUS; /**< Indicates status of Hash peripheral., offset: 0x4 */ - __IO uint32_t INTENSET; /**< Write 1 to enable interrupts; reads back with which are set., offset: 0x8 */ - __IO uint32_t INTENCLR; /**< Write 1 to clear interrupts., offset: 0xC */ - __IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available), offset: 0x10 */ - __IO uint32_t MEMADDR; /**< Address to start memory access from (if available)., offset: 0x14 */ - uint8_t RESERVED_0[8]; - __O uint32_t INDATA; /**< Input of 16 words at a time to load up buffer., offset: 0x20 */ - __O uint32_t ALIAS[7]; /**< Aliases to allow writing words in a burst., array offset: 0x24, array step: 0x4 */ - __I uint32_t DIGEST0[8]; /**< Result digest (when status says so): • Is 1st 5 words if SHA1 used • Is all 8 words if SHA2 used • Is all 8 words if crypto or SHA512, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_1[32]; - __IO uint32_t CRYPTCFG; /**< Crypto settings for AES and Salsa and ChaCha, offset: 0x80 */ - __I uint32_t CONFIG; /**< Returns the configuration of this block in this chip - indicates what services are available., offset: 0x84 */ - uint8_t RESERVED_2[4]; - __IO uint32_t LOCK; /**< Lock register allows locking to the current security level or unlocking by the lock holding level., offset: 0x8C */ - __O uint32_t MASK[4]; /**< Allows Application to write a random mask for ICB use. Normally only a new one on each system reset (including power up)., array offset: 0x90, array step: 0x4 */ - __O uint32_t RELOAD[8]; /**< The WO digest-reload registers may be written with a saved Hash digest, to allow continuation from where left off. These registers may only be written if the Reload field in CTRL is 1. If SHA1, only the 1st 5 are used., array offset: 0xA0, array step: 0x4 */ - uint8_t RESERVED_3[16]; - __O uint32_t PRNG_SEED; /**< PRNG random input value used as an entropy source, offset: 0xD0 */ - uint8_t RESERVED_4[4]; - __I uint32_t PRNG_OUT; /**< Provide random number., offset: 0xD8 */ -} HASHCRYPT_Type; - -/* ---------------------------------------------------------------------------- - -- HASHCRYPT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup HASHCRYPT_Register_Masks HASHCRYPT Register Masks - * @{ - */ - -/*! @name CTRL - Control register to enable and operate Hash and Crypto */ -/*! @{ */ - -#define HASHCRYPT_CTRL_MODE_MASK (0x7U) -#define HASHCRYPT_CTRL_MODE_SHIFT (0U) -/*! Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if - * specific modes beyond SHA1 and SHA2-256 are available. - * 0b000..Disabled - * 0b001..SHA1 is enabled - * 0b010..SHA2-256 is enabled - * 0b100..AES if available (see also CRYPTCFG register for more controls) - * 0b101..Reserved - */ -#define HASHCRYPT_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK) - -#define HASHCRYPT_CTRL_NEW_HASH_MASK (0x10U) -#define HASHCRYPT_CTRL_NEW_HASH_SHIFT (4U) -/*! New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING - * Status bit will clear for a cycle during the initialization from New=1. - * 0b1..Starts a new Hash/Crypto and initializes the Digest/Result. - */ -#define HASHCRYPT_CTRL_NEW_HASH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK) - -#define HASHCRYPT_CTRL_RELOAD_MASK (0x20U) -#define HASHCRYPT_CTRL_RELOAD_SHIFT (5U) -/*! Reload - If 1, allows the SHA RELOAD registers to be used. This is used to save a partial Hash - * Digest (e.g. when need to run AES) and then reload it later for continuation. - * 0b1..Allow RELOAD registers to be used. - */ -#define HASHCRYPT_CTRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_RELOAD_SHIFT)) & HASHCRYPT_CTRL_RELOAD_MASK) - -#define HASHCRYPT_CTRL_DMA_I_MASK (0x100U) -#define HASHCRYPT_CTRL_DMA_I_SHIFT (8U) -/*! DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words - * and then will process the Hash. If Cryptographic, it will load as many words as needed, - * including key if not already loaded. It will then request again. Normal model is that the DMA - * interrupts the processor when its length expires. Note that if the processor will write the key and - * optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be - * expected to load those for the 1st block (when needed). - * 0b0..DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used. - * 0b1..DMA will push in the data. - */ -#define HASHCRYPT_CTRL_DMA_I(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK) - -#define HASHCRYPT_CTRL_DMA_O_MASK (0x200U) -#define HASHCRYPT_CTRL_DMA_O_SHIFT (9U) -/*! DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the - * DMA has to know to switch direction and the locations. This can be used for crypto uses. - * 0b0..DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. - */ -#define HASHCRYPT_CTRL_DMA_O(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK) - -#define HASHCRYPT_CTRL_HASHSWPB_MASK (0x1000U) -#define HASHCRYPT_CTRL_HASHSWPB_SHIFT (12U) -/*! HASHSWPB - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB - * is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For - * cryptographic swapping, see the CRYPTCFG register. - */ -#define HASHCRYPT_CTRL_HASHSWPB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK) - -#define HASHCRYPT_CTRL_AESFLUSH_MASK (0x2000U) -#define HASHCRYPT_CTRL_AESFLUSH_SHIFT (13U) -/*! AESFLUSH - Flushes the AES engine registers. This bit self clears. - * 0b1..Flush the AES engine registers. - * 0b0..Do not flush the AES engine registers. - */ -#define HASHCRYPT_CTRL_AESFLUSH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_AESFLUSH_SHIFT)) & HASHCRYPT_CTRL_AESFLUSH_MASK) -/*! @} */ - -/*! @name STATUS - Indicates status of Hash peripheral. */ -/*! @{ */ - -#define HASHCRYPT_STATUS_WAITING_MASK (0x1U) -#define HASHCRYPT_STATUS_WAITING_SHIFT (0U) -/*! WAITING - If 1, the block is waiting for more data to process. - * 0b0..Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set - * if IsLast is set nor will it set until at least 1 word is read of the output. - * 0b1..Waiting for data to be written in (16 words) - */ -#define HASHCRYPT_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK) - -#define HASHCRYPT_STATUS_DIGEST_MASK (0x2U) -#define HASHCRYPT_STATUS_DIGEST_SHIFT (1U) -/*! DIGEST - For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block - * already started. For Cryptographic uses, this will be set for each block processed, indicating - * OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared - * when any data is written, when New is written, for Cryptographic uses when the last word is read - * out, or when the block is disabled. - * 0b0..No Digest is ready - * 0b1..Digest is ready. Application may read it or may write more data - */ -#define HASHCRYPT_STATUS_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_SHIFT)) & HASHCRYPT_STATUS_DIGEST_MASK) - -#define HASHCRYPT_STATUS_ERROR_MASK (0x4U) -#define HASHCRYPT_STATUS_ERROR_SHIFT (2U) -/*! ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA - * was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT - * field will indicate which block it was on. - * 0b0..No error. - * 0b1..An error occurred since last cleared (written 1 to clear). - */ -#define HASHCRYPT_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK) - -#define HASHCRYPT_STATUS_FAULT_MASK (0x8U) -#define HASHCRYPT_STATUS_FAULT_SHIFT (3U) -/*! FAULT - Indicates if an AES or PRNG fault has occurred - * 0b0..No AES or PRNG fault has occurred. - * 0b1..An AES or PRNG fault has occurred. - */ -#define HASHCRYPT_STATUS_FAULT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_FAULT_SHIFT)) & HASHCRYPT_STATUS_FAULT_MASK) - -#define HASHCRYPT_STATUS_NEEDKEY_MASK (0x10U) -#define HASHCRYPT_STATUS_NEEDKEY_SHIFT (4U) -/*! NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING) - * 0b0..No Key is needed and writes will not be treated as Key - * 0b1..Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. - */ -#define HASHCRYPT_STATUS_NEEDKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK) - -#define HASHCRYPT_STATUS_NEEDIV_MASK (0x20U) -#define HASHCRYPT_STATUS_NEEDIV_SHIFT (5U) -/*! NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING) - * 0b0..No IV/Nonce is needed, either because written already or because not needed. - * 0b1..IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. - */ -#define HASHCRYPT_STATUS_NEEDIV(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK) - -#define HASHCRYPT_STATUS_AESFAULT_MASK (0x100U) -#define HASHCRYPT_STATUS_AESFAULT_SHIFT (8U) -/*! AESFAULT - AES fault status - * 0b0..No AES fault has occurred. - * 0b1..An AES fault has occurred. - */ -#define HASHCRYPT_STATUS_AESFAULT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_AESFAULT_SHIFT)) & HASHCRYPT_STATUS_AESFAULT_MASK) - -#define HASHCRYPT_STATUS_PRNGFAULT_MASK (0x200U) -#define HASHCRYPT_STATUS_PRNGFAULT_SHIFT (9U) -/*! PRNGFAULT - PRNG fault status - * 0b0..No PRNG fault has occurred. - * 0b1..A PRNG fault has occurred. - */ -#define HASHCRYPT_STATUS_PRNGFAULT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_PRNGFAULT_SHIFT)) & HASHCRYPT_STATUS_PRNGFAULT_MASK) -/*! @} */ - -/*! @name INTENSET - Write 1 to enable interrupts; reads back with which are set. */ -/*! @{ */ - -#define HASHCRYPT_INTENSET_WAITING_MASK (0x1U) -#define HASHCRYPT_INTENSET_WAITING_SHIFT (0U) -/*! WAITING - Indicates if should interrupt when waiting for data input. - * 0b0..Will not interrupt when waiting. - * 0b1..Will interrupt when waiting - */ -#define HASHCRYPT_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK) - -#define HASHCRYPT_INTENSET_DIGEST_MASK (0x2U) -#define HASHCRYPT_INTENSET_DIGEST_SHIFT (1U) -/*! DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). - * 0b0..Will not interrupt when Digest is ready - * 0b1..Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). - */ -#define HASHCRYPT_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK) - -#define HASHCRYPT_INTENSET_ERROR_MASK (0x4U) -#define HASHCRYPT_INTENSET_ERROR_SHIFT (2U) -/*! ERROR - Indicates if should interrupt on an ERROR (as defined in Status) - * 0b0..Will not interrupt on Error. - * 0b1..Will interrupt on Error (until cleared). - */ -#define HASHCRYPT_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_ERROR_SHIFT)) & HASHCRYPT_INTENSET_ERROR_MASK) - -#define HASHCRYPT_INTENSET_FAULT_MASK (0x8U) -#define HASHCRYPT_INTENSET_FAULT_SHIFT (3U) -/*! FAULT - Indicates if should interrupt on an AES or PRNG fault as indicated in the STATUS register - * 0b0..No interrupt on an AES or PRNG fault - * 0b1..Interrupt on an AES or PRNG fault - */ -#define HASHCRYPT_INTENSET_FAULT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_FAULT_SHIFT)) & HASHCRYPT_INTENSET_FAULT_MASK) -/*! @} */ - -/*! @name INTENCLR - Write 1 to clear interrupts. */ -/*! @{ */ - -#define HASHCRYPT_INTENCLR_WAITING_MASK (0x1U) -#define HASHCRYPT_INTENCLR_WAITING_SHIFT (0U) -/*! WAITING - Write 1 to clear mask. - */ -#define HASHCRYPT_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK) - -#define HASHCRYPT_INTENCLR_DIGEST_MASK (0x2U) -#define HASHCRYPT_INTENCLR_DIGEST_SHIFT (1U) -/*! DIGEST - Write 1 to clear mask. - */ -#define HASHCRYPT_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK) - -#define HASHCRYPT_INTENCLR_ERROR_MASK (0x4U) -#define HASHCRYPT_INTENCLR_ERROR_SHIFT (2U) -/*! ERROR - Write 1 to clear mask. - */ -#define HASHCRYPT_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK) - -#define HASHCRYPT_INTENCLR_FAULT_MASK (0x8U) -#define HASHCRYPT_INTENCLR_FAULT_SHIFT (3U) -/*! FAULT - Write 1 to clear mask. - */ -#define HASHCRYPT_INTENCLR_FAULT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_FAULT_SHIFT)) & HASHCRYPT_INTENCLR_FAULT_MASK) -/*! @} */ - -/*! @name MEMCTRL - Setup Master to access memory (if available) */ -/*! @{ */ - -#define HASHCRYPT_MEMCTRL_MASTER_MASK (0x1U) -#define HASHCRYPT_MEMCTRL_MASTER_SHIFT (0U) -/*! MASTER - Enables mastering. - * 0b0..Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. - * 0b1..Mastering is enabled and DMA and INDATA should not be used. - */ -#define HASHCRYPT_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK) - -#define HASHCRYPT_MEMCTRL_COUNT_MASK (0x7FF0000U) -#define HASHCRYPT_MEMCTRL_COUNT_SHIFT (16U) -/*! COUNT - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks - * to copy starting at MEMADDR. This register will decrement after each block is copied, ending - * in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA - * interrupt will occur on ever block. If a bus error occurs, it will stop with this field set - * to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) - * blocks to hash. - */ -#define HASHCRYPT_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK) -/*! @} */ - -/*! @name MEMADDR - Address to start memory access from (if available). */ -/*! @{ */ - -#define HASHCRYPT_MEMADDR_BASE_MASK (0xFFFFFFFFU) -#define HASHCRYPT_MEMADDR_BASE_SHIFT (0U) -/*! BASE - Address base to start copying from, word aligned (so bits 1:0 must be 0). This field will - * advance as it processes the words. If it fails with a bus error, the register will contain - * the failing word. N:Address in Flash or RAM space; RAM only as mapped in this part. May also be - * able to address SPIFI. - */ -#define HASHCRYPT_MEMADDR_BASE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK) -/*! @} */ - -/*! @name INDATA - Input of 16 words at a time to load up buffer. */ -/*! @{ */ - -#define HASHCRYPT_INDATA_DATA_MASK (0xFFFFFFFFU) -#define HASHCRYPT_INDATA_DATA_SHIFT (0U) -/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this - * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as - * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block - * will swap the word to restore into big endian. - */ -#define HASHCRYPT_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK) -/*! @} */ - -/*! @name ALIAS - Aliases to allow writing words in a burst. */ -/*! @{ */ - -#define HASHCRYPT_ALIAS_DATA_MASK (0xFFFFFFFFU) -#define HASHCRYPT_ALIAS_DATA_SHIFT (0U) -/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this - * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as - * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block - * will swap the word to restore into big endian. - */ -#define HASHCRYPT_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK) -/*! @} */ - -/* The count of HASHCRYPT_ALIAS */ -#define HASHCRYPT_ALIAS_COUNT (7U) - -/*! @name DIGEST0 - Result digest (when status says so): • Is 1st 5 words if SHA1 used • Is all 8 words if SHA2 used • Is all 8 words if crypto or SHA512 */ -/*! @{ */ - -#define HASHCRYPT_DIGEST0_DIGEST_MASK (0xFFFFFFFFU) -#define HASHCRYPT_DIGEST0_DIGEST_SHIFT (0U) -/*! DIGEST - One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1. - */ -#define HASHCRYPT_DIGEST0_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_DIGEST0_DIGEST_SHIFT)) & HASHCRYPT_DIGEST0_DIGEST_MASK) -/*! @} */ - -/* The count of HASHCRYPT_DIGEST0 */ -#define HASHCRYPT_DIGEST0_COUNT (8U) - -/*! @name CRYPTCFG - Crypto settings for AES and Salsa and ChaCha */ -/*! @{ */ - -#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK (0x1U) -#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT (0U) -/*! MSW1ST_OUT - If 1, OUTDATA0 will be read Most significant word 1st for AES. Else it will be read - * in normal little endian - Least significant word 1st. Note: only if allowed by configuration. - */ -#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK) - -#define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK (0x2U) -#define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT (1U) -/*! SWAPKEY - If 1, will Swap the key input (bytes in each word). - */ -#define HASHCRYPT_CRYPTCFG_SWAPKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK) - -#define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK (0x4U) -#define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT (2U) -/*! SWAPDAT - If 1, will SWAP the data and IV inputs (bytes in each word). - */ -#define HASHCRYPT_CRYPTCFG_SWAPDAT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK) - -#define HASHCRYPT_CRYPTCFG_MSW1ST_MASK (0x8U) -#define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT (3U) -/*! MSW1ST - If 1, load of key, IV, and data is MSW 1st for AES. Else, the words are little endian. - * Note: only if allowed by configuration. - */ -#define HASHCRYPT_CRYPTCFG_MSW1ST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK) - -#define HASHCRYPT_CRYPTCFG_AESMODE_MASK (0x30U) -#define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT (4U) -/*! AESMODE - AES Cipher mode to use if plain AES - * 0b00..ECB - used as is - * 0b01..CBC mode (see details on IV/nonce) - * 0b10..CTR mode (see details on IV/nonce). See also AESCTRPOS. - * 0b11..reserved - */ -#define HASHCRYPT_CRYPTCFG_AESMODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK) - -#define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK (0x40U) -#define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT (6U) -/*! AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB - * 0b0..Encrypt - * 0b1..Decrypt - */ -#define HASHCRYPT_CRYPTCFG_AESDECRYPT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK) - -#define HASHCRYPT_CRYPTCFG_AESSECRET_MASK (0x80U) -#define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT (7U) -/*! AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are - * used, only the highest level is permitted to select this. - * 0b0..User key provided in normal way - * 0b1..Secret key provided in hidden way by HW - */ -#define HASHCRYPT_CRYPTCFG_AESSECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK) - -#define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK (0x300U) -#define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT (8U) -/*! AESKEYSZ - Sets the AES key size - * 0b00..128 bit key - * 0b01..192 bit key - * 0b10..256 bit key - * 0b11..reserved - */ -#define HASHCRYPT_CRYPTCFG_AESKEYSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK) - -#define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK (0x1C00U) -#define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT (10U) -/*! AESCTRPOS - Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for - * Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if - * using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other - * use CTR should use ECB directly and do its own XOR and so on. - */ -#define HASHCRYPT_CRYPTCFG_AESCTRPOS(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK) - -#define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK (0x10000U) -#define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT (16U) -/*! STREAMLAST - Is 1 if last stream block. If not 1, then the engine will compute the next "hash". - */ -#define HASHCRYPT_CRYPTCFG_STREAMLAST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK) -/*! @} */ - -/*! @name CONFIG - Returns the configuration of this block in this chip - indicates what services are available. */ -/*! @{ */ - -#define HASHCRYPT_CONFIG_DUAL_MASK (0x1U) -#define HASHCRYPT_CONFIG_DUAL_SHIFT (0U) -/*! DUAL - 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit - */ -#define HASHCRYPT_CONFIG_DUAL(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK) - -#define HASHCRYPT_CONFIG_DMA_MASK (0x2U) -#define HASHCRYPT_CONFIG_DMA_SHIFT (1U) -/*! DMA - 1 if DMA is connected - */ -#define HASHCRYPT_CONFIG_DMA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK) - -#define HASHCRYPT_CONFIG_AHB_MASK (0x8U) -#define HASHCRYPT_CONFIG_AHB_SHIFT (3U) -/*! AHB - 1 if AHB Master is enabled - */ -#define HASHCRYPT_CONFIG_AHB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK) - -#define HASHCRYPT_CONFIG_AES_MASK (0x40U) -#define HASHCRYPT_CONFIG_AES_SHIFT (6U) -/*! AES - 1 if AES 128 included - */ -#define HASHCRYPT_CONFIG_AES(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK) - -#define HASHCRYPT_CONFIG_AESKEY_MASK (0x80U) -#define HASHCRYPT_CONFIG_AESKEY_SHIFT (7U) -/*! AESKEY - 1 if AES 192 and 256 also included - */ -#define HASHCRYPT_CONFIG_AESKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK) - -#define HASHCRYPT_CONFIG_SECRET_MASK (0x100U) -#define HASHCRYPT_CONFIG_SECRET_SHIFT (8U) -/*! SECRET - 1 if AES Secret key available - */ -#define HASHCRYPT_CONFIG_SECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK) -/*! @} */ - -/*! @name LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. */ -/*! @{ */ - -#define HASHCRYPT_LOCK_SECLOCK_MASK (0x3U) -#define HASHCRYPT_LOCK_SECLOCK_SHIFT (0U) -/*! SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. - * If locked already, may only write if at same or higher security level as lock. Reads as: 0 if - * unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the - * only readable registers if locked and current state is lower than lock level. - * 0b00..Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests. - * 0b01..Locks to the current security level. AHB Master will issue requests at this level. - */ -#define HASHCRYPT_LOCK_SECLOCK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK) - -#define HASHCRYPT_LOCK_PATTERN_MASK (0xFFF0U) -#define HASHCRYPT_LOCK_PATTERN_SHIFT (4U) -/*! PATTERN - Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0 - */ -#define HASHCRYPT_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK) -/*! @} */ - -/*! @name MASK - Allows Application to write a random mask for ICB use. Normally only a new one on each system reset (including power up). */ -/*! @{ */ - -#define HASHCRYPT_MASK_MASK_MASK (0xFFFFFFFFU) -#define HASHCRYPT_MASK_MASK_SHIFT (0U) -/*! MASK - A random word. - */ -#define HASHCRYPT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK) -/*! @} */ - -/* The count of HASHCRYPT_MASK */ -#define HASHCRYPT_MASK_COUNT (4U) - -/*! @name RELOAD - The WO digest-reload registers may be written with a saved Hash digest, to allow continuation from where left off. These registers may only be written if the Reload field in CTRL is 1. If SHA1, only the 1st 5 are used. */ -/*! @{ */ - -#define HASHCRYPT_RELOAD_DIGEST_MASK (0xFFFFFFFFU) -#define HASHCRYPT_RELOAD_DIGEST_SHIFT (0U) -/*! DIGEST - SHA Digest word to reload. - */ -#define HASHCRYPT_RELOAD_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_RELOAD_DIGEST_SHIFT)) & HASHCRYPT_RELOAD_DIGEST_MASK) -/*! @} */ - -/* The count of HASHCRYPT_RELOAD */ -#define HASHCRYPT_RELOAD_COUNT (8U) - -/*! @name PRNG_SEED - PRNG random input value used as an entropy source */ -/*! @{ */ - -#define HASHCRYPT_PRNG_SEED_PRNG_SEED_MASK (0xFFFFFFFFU) -#define HASHCRYPT_PRNG_SEED_PRNG_SEED_SHIFT (0U) -/*! PRNG_SEED - Random input value used as an entropy source - */ -#define HASHCRYPT_PRNG_SEED_PRNG_SEED(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_PRNG_SEED_PRNG_SEED_SHIFT)) & HASHCRYPT_PRNG_SEED_PRNG_SEED_MASK) -/*! @} */ - -/*! @name PRNG_OUT - Provide random number. */ -/*! @{ */ - -#define HASHCRYPT_PRNG_OUT_PRNG_OUT_MASK (0xFFFFFFFFU) -#define HASHCRYPT_PRNG_OUT_PRNG_OUT_SHIFT (0U) -/*! PRNG_OUT - Provide random number. - */ -#define HASHCRYPT_PRNG_OUT_PRNG_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_PRNG_OUT_PRNG_OUT_SHIFT)) & HASHCRYPT_PRNG_OUT_PRNG_OUT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group HASHCRYPT_Register_Masks */ - - -/* HASHCRYPT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral HASHCRYPT base address */ - #define HASHCRYPT_BASE (0x500A4000u) - /** Peripheral HASHCRYPT base address */ - #define HASHCRYPT_BASE_NS (0x400A4000u) - /** Peripheral HASHCRYPT base pointer */ - #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) - /** Peripheral HASHCRYPT base pointer */ - #define HASHCRYPT_NS ((HASHCRYPT_Type *)HASHCRYPT_BASE_NS) - /** Array initializer of HASHCRYPT peripheral base addresses */ - #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } - /** Array initializer of HASHCRYPT peripheral base pointers */ - #define HASHCRYPT_BASE_PTRS { HASHCRYPT } - /** Array initializer of HASHCRYPT peripheral base addresses */ - #define HASHCRYPT_BASE_ADDRS_NS { HASHCRYPT_BASE_NS } - /** Array initializer of HASHCRYPT peripheral base pointers */ - #define HASHCRYPT_BASE_PTRS_NS { HASHCRYPT_NS } -#else - /** Peripheral HASHCRYPT base address */ - #define HASHCRYPT_BASE (0x400A4000u) - /** Peripheral HASHCRYPT base pointer */ - #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) - /** Array initializer of HASHCRYPT peripheral base addresses */ - #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } - /** Array initializer of HASHCRYPT peripheral base pointers */ - #define HASHCRYPT_BASE_PTRS { HASHCRYPT } -#endif - -/*! - * @} - */ /* end of group HASHCRYPT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2C Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer - * @{ - */ - -/** I2C - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[2048]; - __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ - __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ - __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ - __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ - __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ - __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ - uint8_t RESERVED_1[4]; - __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ - __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ - __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ - uint8_t RESERVED_2[20]; - __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ - __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ - __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ - __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ - uint8_t RESERVED_3[36]; - __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ - uint8_t RESERVED_4[1912]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} I2C_Type; - -/* ---------------------------------------------------------------------------- - -- I2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Register_Masks I2C Register Masks - * @{ - */ - -/*! @name CFG - Configuration for shared functions. */ -/*! @{ */ - -#define I2C_CFG_MSTEN_MASK (0x1U) -#define I2C_CFG_MSTEN_SHIFT (0U) -/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not - * changed, but the Master function is internally reset. - * 0b0..Disabled. The I2C Master function is disabled. - * 0b1..Enabled. The I2C Master function is enabled. - */ -#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) - -#define I2C_CFG_SLVEN_MASK (0x2U) -#define I2C_CFG_SLVEN_SHIFT (1U) -/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not - * changed, but the Slave function is internally reset. - * 0b0..Disabled. The I2C slave function is disabled. - * 0b1..Enabled. The I2C slave function is enabled. - */ -#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) - -#define I2C_CFG_MONEN_MASK (0x4U) -#define I2C_CFG_MONEN_SHIFT (2U) -/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not - * changed, but the Monitor function is internally reset. - * 0b0..Disabled. The I2C Monitor function is disabled. - * 0b1..Enabled. The I2C Monitor function is enabled. - */ -#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) - -#define I2C_CFG_TIMEOUTEN_MASK (0x8U) -#define I2C_CFG_TIMEOUTEN_SHIFT (3U) -/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. - * 0b0..Disabled. Time-out function is disabled. - * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause - * interrupts if they are enabled. Typically, only one time-out will be used in a system. - */ -#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) - -#define I2C_CFG_MONCLKSTR_MASK (0x10U) -#define I2C_CFG_MONCLKSTR_SHIFT (4U) -/*! MONCLKSTR - Monitor function Clock Stretching. - * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able - * to read data provided by the Monitor function before it is overwritten. This mode may be used when - * non-invasive monitoring is critical. - * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can - * read all incoming data supplied by the Monitor function. - */ -#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) - -#define I2C_CFG_HSCAPABLE_MASK (0x20U) -#define I2C_CFG_HSCAPABLE_SHIFT (5U) -/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive - * and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies - * to all functions: Master, Slave, and Monitor. - * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the - * extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, - * such as changing the drive strength or filtering, must be made by software via the IOCON register associated - * with each I2C pin, - * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support - * High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more - * information. - */ -#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) -/*! @} */ - -/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ -/*! @{ */ - -#define I2C_STAT_MSTPENDING_MASK (0x1U) -#define I2C_STAT_MSTPENDING_SHIFT (0U) -/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on - * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what - * type of software service if any the master expects. This flag will cause an interrupt when set - * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling - * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle - * state, and no communication is needed, mask this interrupt. - * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. - * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the - * idle state, it is waiting to receive or transmit data or the NACK bit. - */ -#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) - -#define I2C_STAT_MSTSTATE_MASK (0xEU) -#define I2C_STAT_MSTSTATE_SHIFT (1U) -/*! MSTSTATE - Master State code. The master state code reflects the master state when the - * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field - * indicates a specific required service for the Master function. All other values are reserved. See - * Table 400 for details of state values and appropriate responses. - * 0b000..Idle. The Master function is available to be used for a new transaction. - * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. - * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. - * 0b011..NACK Address. Slave NACKed address. - * 0b100..NACK Data. Slave NACKed transmitted data. - */ -#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) - -#define I2C_STAT_MSTARBLOSS_MASK (0x10U) -#define I2C_STAT_MSTARBLOSS_SHIFT (4U) -/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to - * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - * 0b0..No Arbitration Loss has occurred. - * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master - * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, - * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. - */ -#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) - -#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) -/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to - * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - * 0b0..No Start/Stop Error has occurred. - * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is - * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an - * idle state, no action is required. A request for a Start could be made, or software could attempt to insure - * that the bus has not stalled. - */ -#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) - -#define I2C_STAT_SLVPENDING_MASK (0x100U) -#define I2C_STAT_SLVPENDING_SHIFT (8U) -/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue - * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if - * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the - * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is - * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time - * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section - * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are - * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must - * also be detected automatically, since the address must be acknowledged before the clock can be - * stretched. - * 0b0..In progress. The Slave function does not currently need service. - * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. - */ -#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) - -#define I2C_STAT_SLVSTATE_MASK (0x600U) -#define I2C_STAT_SLVSTATE_SHIFT (9U) -/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for - * the Slave function. All other values are reserved. See Table 401 for state values and actions. - * note that the occurrence of some states and how they are handled are affected by DMA mode and - * Automatic Operation modes. - * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. - * 0b01..Slave receive. Received data is available (Slave Receiver mode). - * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). - */ -#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) - -#define I2C_STAT_SLVNOTSTR_MASK (0x800U) -#define I2C_STAT_SLVNOTSTR_SHIFT (11U) -/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. - * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave - * operation. This read-only flag reflects the slave function status in real time. - * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. - * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or - * Power-down mode could be entered at this time. - */ -#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) - -#define I2C_STAT_SLVIDX_MASK (0x3000U) -#define I2C_STAT_SLVIDX_SHIFT (12U) -/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been - * selected by receiving an address that matches one of the slave addresses defined by any enabled - * slave address registers, and provides an identification of the address that was matched. It is - * possible that more than one address could be matched, but only one match can be reported here. - * 0b00..Address 0. Slave address 0 was matched. - * 0b01..Address 1. Slave address 1 was matched. - * 0b10..Address 2. Slave address 2 was matched. - * 0b11..Address 3. Slave address 3 was matched. - */ -#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) - -#define I2C_STAT_SLVSEL_MASK (0x4000U) -#define I2C_STAT_SLVSEL_SHIFT (14U) -/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave - * function to acknowledge the address, or when the address has been automatically acknowledged. - * It is cleared when another address cycle presents an address that does not match an enabled - * address on the Slave function, when slave software decides to NACK a matched address, when - * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of - * Automatic Operation. SLVSEL is not cleared if software NACKs data. - * 0b0..Not selected. The Slave function is not currently selected. - * 0b1..Selected. The Slave function is currently selected. - */ -#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) - -#define I2C_STAT_SLVDESEL_MASK (0x8000U) -#define I2C_STAT_SLVDESEL_SHIFT (15U) -/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via - * INTENSET. This flag can be cleared by writing a 1 to this bit. - * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently - * selected. That information can be found in the SLVSEL flag. - * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag - * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. - */ -#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) - -#define I2C_STAT_MONRDY_MASK (0x10000U) -#define I2C_STAT_MONRDY_SHIFT (16U) -/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. - * 0b0..No data. The Monitor function does not currently have data available. - * 0b1..Data waiting. The Monitor function has data waiting to be read. - */ -#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) - -#define I2C_STAT_MONOV_MASK (0x20000U) -#define I2C_STAT_MONOV_SHIFT (17U) -/*! MONOV - Monitor Overflow flag. - * 0b0..No overrun. Monitor data has not overrun. - * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not - * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. - */ -#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) - -#define I2C_STAT_MONACTIVE_MASK (0x40000U) -#define I2C_STAT_MONACTIVE_SHIFT (18U) -/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to - * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred - * more recently than a bus Stop. - * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. - * 0b1..Active. The Monitor function considers the I2C bus to be active. - */ -#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) - -#define I2C_STAT_MONIDLE_MASK (0x80000U) -#define I2C_STAT_MONIDLE_SHIFT (19U) -/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change - * from active to inactive. This can be used by software to decide when to process data - * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the - * INTENSET register. The flag can be cleared by writing a 1 to this bit. - * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. - * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. - */ -#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) - -#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) -/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been - * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock - * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus - * is idle. - * 0b0..No time-out. I2C bus events have not caused a time-out. - * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. - */ -#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) - -#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) -/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the - * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. - * 0b0..No time-out. SCL low time has not caused a time-out. - * 0b1..Time-out. SCL low time has caused a time-out. - */ -#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable Set and read register. */ -/*! @{ */ - -#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) -#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) -/*! MSTPENDINGEN - Master Pending interrupt Enable. - * 0b0..Disabled. The MstPending interrupt is disabled. - * 0b1..Enabled. The MstPending interrupt is enabled. - */ -#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) - -#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) -#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) -/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. - * 0b0..Disabled. The MstArbLoss interrupt is disabled. - * 0b1..Enabled. The MstArbLoss interrupt is enabled. - */ -#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) - -#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) -#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) -/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. - * 0b0..Disabled. The MstStStpErr interrupt is disabled. - * 0b1..Enabled. The MstStStpErr interrupt is enabled. - */ -#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) - -#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) -#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) -/*! SLVPENDINGEN - Slave Pending interrupt Enable. - * 0b0..Disabled. The SlvPending interrupt is disabled. - * 0b1..Enabled. The SlvPending interrupt is enabled. - */ -#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) - -#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) -#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) -/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. - * 0b0..Disabled. The SlvNotStr interrupt is disabled. - * 0b1..Enabled. The SlvNotStr interrupt is enabled. - */ -#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) - -#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) -#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) -/*! SLVDESELEN - Slave Deselect interrupt Enable. - * 0b0..Disabled. The SlvDeSel interrupt is disabled. - * 0b1..Enabled. The SlvDeSel interrupt is enabled. - */ -#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) - -#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) -#define I2C_INTENSET_MONRDYEN_SHIFT (16U) -/*! MONRDYEN - Monitor data Ready interrupt Enable. - * 0b0..Disabled. The MonRdy interrupt is disabled. - * 0b1..Enabled. The MonRdy interrupt is enabled. - */ -#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) - -#define I2C_INTENSET_MONOVEN_MASK (0x20000U) -#define I2C_INTENSET_MONOVEN_SHIFT (17U) -/*! MONOVEN - Monitor Overrun interrupt Enable. - * 0b0..Disabled. The MonOv interrupt is disabled. - * 0b1..Enabled. The MonOv interrupt is enabled. - */ -#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) - -#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) -#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) -/*! MONIDLEEN - Monitor Idle interrupt Enable. - * 0b0..Disabled. The MonIdle interrupt is disabled. - * 0b1..Enabled. The MonIdle interrupt is enabled. - */ -#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) - -#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) -#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) -/*! EVENTTIMEOUTEN - Event time-out interrupt Enable. - * 0b0..Disabled. The Event time-out interrupt is disabled. - * 0b1..Enabled. The Event time-out interrupt is enabled. - */ -#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) - -#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) -#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) -/*! SCLTIMEOUTEN - SCL time-out interrupt Enable. - * 0b0..Disabled. The SCL time-out interrupt is disabled. - * 0b1..Enabled. The SCL time-out interrupt is enabled. - */ -#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear register. */ -/*! @{ */ - -#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) -#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) -/*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding - * bit in the INTENSET register if implemented. - */ -#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) - -#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) -#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) -/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear. - */ -#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) - -#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) -#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) -/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear. - */ -#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) - -#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) -#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) -/*! SLVPENDINGCLR - Slave Pending interrupt clear. - */ -#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) - -#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) -#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) -/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear. - */ -#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) - -#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) -#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) -/*! SLVDESELCLR - Slave Deselect interrupt clear. - */ -#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) - -#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) -#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) -/*! MONRDYCLR - Monitor data Ready interrupt clear. - */ -#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) - -#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) -#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) -/*! MONOVCLR - Monitor Overrun interrupt clear. - */ -#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) - -#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) -#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) -/*! MONIDLECLR - Monitor Idle interrupt clear. - */ -#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) - -#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) -#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) -/*! EVENTTIMEOUTCLR - Event time-out interrupt clear. - */ -#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) - -#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) -#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) -/*! SCLTIMEOUTCLR - SCL time-out interrupt clear. - */ -#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) -/*! @} */ - -/*! @name TIMEOUT - Time-out value register. */ -/*! @{ */ - -#define I2C_TIMEOUT_TOMIN_MASK (0xFU) -#define I2C_TIMEOUT_TOMIN_SHIFT (0U) -/*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum - * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. - */ -#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) - -#define I2C_TIMEOUT_TO_MASK (0xFFF0U) -#define I2C_TIMEOUT_TO_SHIFT (4U) -/*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C - * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, - * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A - * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after - * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the - * I2C function clock. - */ -#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) -/*! @} */ - -/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ -/*! @{ */ - -#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) -#define I2C_CLKDIV_DIVVAL_SHIFT (0U) -/*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that - * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = - * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is - * divided by 65,536 before use. - */ -#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ -/*! @{ */ - -#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) -#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) -/*! MSTPENDING - Master Pending. - */ -#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) - -#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) -#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) -/*! MSTARBLOSS - Master Arbitration Loss flag. - */ -#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) - -#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) -/*! MSTSTSTPERR - Master Start/Stop Error flag. - */ -#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) - -#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) -#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) -/*! SLVPENDING - Slave Pending. - */ -#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) - -#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) -#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) -/*! SLVNOTSTR - Slave Not Stretching status. - */ -#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) - -#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) -#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) -/*! SLVDESEL - Slave Deselected flag. - */ -#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) - -#define I2C_INTSTAT_MONRDY_MASK (0x10000U) -#define I2C_INTSTAT_MONRDY_SHIFT (16U) -/*! MONRDY - Monitor Ready. - */ -#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) - -#define I2C_INTSTAT_MONOV_MASK (0x20000U) -#define I2C_INTSTAT_MONOV_SHIFT (17U) -/*! MONOV - Monitor Overflow flag. - */ -#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) - -#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) -#define I2C_INTSTAT_MONIDLE_SHIFT (19U) -/*! MONIDLE - Monitor Idle flag. - */ -#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) - -#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) -/*! EVENTTIMEOUT - Event time-out Interrupt flag. - */ -#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) - -#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) -/*! SCLTIMEOUT - SCL time-out Interrupt flag. - */ -#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name MSTCTL - Master control register. */ -/*! @{ */ - -#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) -#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) -/*! MSTCONTINUE - Master Continue. This bit is write-only. - * 0b0..No effect. - * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing - * transmit data, reading received data, or any other housekeeping related to the next bus operation. - */ -#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) - -#define I2C_MSTCTL_MSTSTART_MASK (0x2U) -#define I2C_MSTCTL_MSTSTART_SHIFT (1U) -/*! MSTSTART - Master Start control. This bit is write-only. - * 0b0..No effect. - * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. - */ -#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) - -#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) -#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) -/*! MSTSTOP - Master Stop control. This bit is write-only. - * 0b0..No effect. - * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave - * if the master is receiving data from the slave (Master Receiver mode). - */ -#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) - -#define I2C_MSTCTL_MSTDMA_MASK (0x8U) -#define I2C_MSTCTL_MSTDMA_SHIFT (3U) -/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type - * operations such as Start, address, Stop, and address match must always be done with software, - * typically via an interrupt. Address acknowledgement must also be done by software except when - * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by - * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA - * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is - * read/write. - * 0b0..Disable. No DMA requests are generated for master operation. - * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating - * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. - */ -#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) -/*! @} */ - -/*! @name MSTTIME - Master timing configuration. */ -/*! @{ */ - -#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) -#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) -/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this - * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This - * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters - * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. - * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. - * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. - * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. - * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. - * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. - * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. - * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. - * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. - */ -#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) - -#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) -#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) -/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this - * master on SCL. Other masters in a multi-master system could shorten this time. This - * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters - * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. - * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. - * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . - * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. - * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. - * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. - * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. - * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. - * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. - */ -#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) -/*! @} */ - -/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ -/*! @{ */ - -#define I2C_MSTDAT_DATA_MASK (0xFFU) -#define I2C_MSTDAT_DATA_SHIFT (0U) -/*! DATA - Master function data register. Read: read the most recently received data for the Master - * function. Write: transmit data using the Master function. - */ -#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVCTL - Slave control register. */ -/*! @{ */ - -#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) -#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) -/*! SLVCONTINUE - Slave Continue. - * 0b0..No effect. - * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag - * in the STAT register. This must be done after writing transmit data, reading received data, or any other - * housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE - * should not be set unless SLVPENDING = 1. - */ -#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) - -#define I2C_SLVCTL_SLVNACK_MASK (0x2U) -#define I2C_SLVCTL_SLVNACK_SHIFT (1U) -/*! SLVNACK - Slave NACK. - * 0b0..No effect. - * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). - */ -#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) - -#define I2C_SLVCTL_SLVDMA_MASK (0x8U) -#define I2C_SLVCTL_SLVDMA_SHIFT (3U) -/*! SLVDMA - Slave DMA enable. - * 0b0..Disabled. No DMA requests are issued for Slave mode operation. - * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. - */ -#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) - -#define I2C_SLVCTL_AUTOACK_MASK (0x100U) -#define I2C_SLVCTL_AUTOACK_SHIFT (8U) -/*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches - * SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA - * to allow processing of the data without intervention. If this bit is clear and a header - * matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or - * interrupt. - * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching - * address is received. If AUTONACK = 1, received addresses are NACKed (ignored). - * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, - * allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does - * not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK - * is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. - */ -#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) - -#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) -#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) -/*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write - * request on the next header with an address matching SLVADR0. Since DMA needs to be configured to - * match the transfer direction, the direction needs to be specified. This bit allows a direction to - * be chosen for the next operation. - * 0b0..The expected next operation in Automatic Mode is an I2C write. - * 0b1..The expected next operation in Automatic Mode is an I2C read. - */ -#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) -/*! @} */ - -/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ -/*! @{ */ - -#define I2C_SLVDAT_DATA_MASK (0xFFU) -#define I2C_SLVDAT_DATA_SHIFT (0U) -/*! DATA - Slave function data register. Read: read the most recently received data for the Slave - * function. Write: transmit data using the Slave function. - */ -#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVADR - Slave address register. */ -/*! @{ */ - -#define I2C_SLVADR_SADISABLE_MASK (0x1U) -#define I2C_SLVADR_SADISABLE_SHIFT (0U) -/*! SADISABLE - Slave Address n Disable. - * 0b0..Enabled. Slave Address n is enabled. - * 0b1..Ignored Slave Address n is ignored. - */ -#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) - -#define I2C_SLVADR_SLVADR_MASK (0xFEU) -#define I2C_SLVADR_SLVADR_SHIFT (1U) -/*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. - */ -#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) - -#define I2C_SLVADR_AUTONACK_MASK (0x8000U) -#define I2C_SLVADR_AUTONACK_SHIFT (15U) -/*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows - * software to ignore I2C traffic while handling previous I2C data or other operations. - * 0b0..Normal operation, matching I2C addresses are not ignored. - * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches - * SLVADRn, and AUTOMATCHREAD matches the direction. - */ -#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) -/*! @} */ - -/* The count of I2C_SLVADR */ -#define I2C_SLVADR_COUNT (4U) - -/*! @name SLVQUAL0 - Slave Qualification for address 0. */ -/*! @{ */ - -#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) -#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) -/*! QUALMODE0 - Qualify mode for slave address 0. - * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. - * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. - */ -#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) - -#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) -#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) -/*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to - * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is - * set to 1 will cause an automatic match of the corresponding bit of the received address when it - * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for - * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 - * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). - */ -#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) -/*! @} */ - -/*! @name MONRXDAT - Monitor receiver data register. */ -/*! @{ */ - -#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) -#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) -/*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. - */ -#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) - -#define I2C_MONRXDAT_MONSTART_MASK (0x100U) -#define I2C_MONRXDAT_MONSTART_SHIFT (8U) -/*! MONSTART - Monitor Received Start. - * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. - * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. - */ -#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) - -#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) -#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) -/*! MONRESTART - Monitor Received Repeated Start. - * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. - * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. - */ -#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) - -#define I2C_MONRXDAT_MONNACK_MASK (0x400U) -#define I2C_MONRXDAT_MONNACK_SHIFT (10U) -/*! MONNACK - Monitor Received NACK. - * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. - * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. - */ -#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ - -#define I2C_ID_APERTURE_MASK (0xFFU) -#define I2C_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - */ -#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) - -#define I2C_ID_MINOR_REV_MASK (0xF00U) -#define I2C_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation. - */ -#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) - -#define I2C_ID_MAJOR_REV_MASK (0xF000U) -#define I2C_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation. - */ -#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) - -#define I2C_ID_ID_MASK (0xFFFF0000U) -#define I2C_ID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function. - */ -#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2C_Register_Masks */ - - -/* I2C - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral I2C0 base address */ - #define I2C0_BASE (0x50086000u) - /** Peripheral I2C0 base address */ - #define I2C0_BASE_NS (0x40086000u) - /** Peripheral I2C0 base pointer */ - #define I2C0 ((I2C_Type *)I2C0_BASE) - /** Peripheral I2C0 base pointer */ - #define I2C0_NS ((I2C_Type *)I2C0_BASE_NS) - /** Peripheral I2C1 base address */ - #define I2C1_BASE (0x50087000u) - /** Peripheral I2C1 base address */ - #define I2C1_BASE_NS (0x40087000u) - /** Peripheral I2C1 base pointer */ - #define I2C1 ((I2C_Type *)I2C1_BASE) - /** Peripheral I2C1 base pointer */ - #define I2C1_NS ((I2C_Type *)I2C1_BASE_NS) - /** Peripheral I2C2 base address */ - #define I2C2_BASE (0x50088000u) - /** Peripheral I2C2 base address */ - #define I2C2_BASE_NS (0x40088000u) - /** Peripheral I2C2 base pointer */ - #define I2C2 ((I2C_Type *)I2C2_BASE) - /** Peripheral I2C2 base pointer */ - #define I2C2_NS ((I2C_Type *)I2C2_BASE_NS) - /** Peripheral I2C3 base address */ - #define I2C3_BASE (0x50089000u) - /** Peripheral I2C3 base address */ - #define I2C3_BASE_NS (0x40089000u) - /** Peripheral I2C3 base pointer */ - #define I2C3 ((I2C_Type *)I2C3_BASE) - /** Peripheral I2C3 base pointer */ - #define I2C3_NS ((I2C_Type *)I2C3_BASE_NS) - /** Peripheral I2C4 base address */ - #define I2C4_BASE (0x5008A000u) - /** Peripheral I2C4 base address */ - #define I2C4_BASE_NS (0x4008A000u) - /** Peripheral I2C4 base pointer */ - #define I2C4 ((I2C_Type *)I2C4_BASE) - /** Peripheral I2C4 base pointer */ - #define I2C4_NS ((I2C_Type *)I2C4_BASE_NS) - /** Peripheral I2C5 base address */ - #define I2C5_BASE (0x50096000u) - /** Peripheral I2C5 base address */ - #define I2C5_BASE_NS (0x40096000u) - /** Peripheral I2C5 base pointer */ - #define I2C5 ((I2C_Type *)I2C5_BASE) - /** Peripheral I2C5 base pointer */ - #define I2C5_NS ((I2C_Type *)I2C5_BASE_NS) - /** Peripheral I2C6 base address */ - #define I2C6_BASE (0x50097000u) - /** Peripheral I2C6 base address */ - #define I2C6_BASE_NS (0x40097000u) - /** Peripheral I2C6 base pointer */ - #define I2C6 ((I2C_Type *)I2C6_BASE) - /** Peripheral I2C6 base pointer */ - #define I2C6_NS ((I2C_Type *)I2C6_BASE_NS) - /** Peripheral I2C7 base address */ - #define I2C7_BASE (0x50098000u) - /** Peripheral I2C7 base address */ - #define I2C7_BASE_NS (0x40098000u) - /** Peripheral I2C7 base pointer */ - #define I2C7 ((I2C_Type *)I2C7_BASE) - /** Peripheral I2C7 base pointer */ - #define I2C7_NS ((I2C_Type *)I2C7_BASE_NS) - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS_NS { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS_NS { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS } -#else - /** Peripheral I2C0 base address */ - #define I2C0_BASE (0x40086000u) - /** Peripheral I2C0 base pointer */ - #define I2C0 ((I2C_Type *)I2C0_BASE) - /** Peripheral I2C1 base address */ - #define I2C1_BASE (0x40087000u) - /** Peripheral I2C1 base pointer */ - #define I2C1 ((I2C_Type *)I2C1_BASE) - /** Peripheral I2C2 base address */ - #define I2C2_BASE (0x40088000u) - /** Peripheral I2C2 base pointer */ - #define I2C2 ((I2C_Type *)I2C2_BASE) - /** Peripheral I2C3 base address */ - #define I2C3_BASE (0x40089000u) - /** Peripheral I2C3 base pointer */ - #define I2C3 ((I2C_Type *)I2C3_BASE) - /** Peripheral I2C4 base address */ - #define I2C4_BASE (0x4008A000u) - /** Peripheral I2C4 base pointer */ - #define I2C4 ((I2C_Type *)I2C4_BASE) - /** Peripheral I2C5 base address */ - #define I2C5_BASE (0x40096000u) - /** Peripheral I2C5 base pointer */ - #define I2C5 ((I2C_Type *)I2C5_BASE) - /** Peripheral I2C6 base address */ - #define I2C6_BASE (0x40097000u) - /** Peripheral I2C6 base pointer */ - #define I2C6 ((I2C_Type *)I2C6_BASE) - /** Peripheral I2C7 base address */ - #define I2C7_BASE (0x40098000u) - /** Peripheral I2C7 base pointer */ - #define I2C7 ((I2C_Type *)I2C7_BASE) - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } -#endif -/** Interrupt vectors for the I2C peripheral type */ -#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2C_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2S Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer - * @{ - */ - -/** I2S - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[3072]; - __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ - __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ - __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ - struct { /* offset: 0xC20, array step: 0x20 */ - __IO uint32_t PCFG1; /**< Configuration register 1 for channel pair, array offset: 0xC20, array step: 0x20 */ - __IO uint32_t PCFG2; /**< Configuration register 2 for channel pair, array offset: 0xC24, array step: 0x20 */ - __IO uint32_t PSTAT; /**< Status register for channel pair, array offset: 0xC28, array step: 0x20 */ - uint8_t RESERVED_0[20]; - } SECCHANNEL[3]; - uint8_t RESERVED_2[384]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ - uint8_t RESERVED_5[8]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ - uint8_t RESERVED_6[8]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ - __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ - uint8_t RESERVED_7[432]; - __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */ -} I2S_Type; - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ -/*! @{ */ - -#define I2S_CFG1_MAINENABLE_MASK (0x1U) -#define I2S_CFG1_MAINENABLE_SHIFT (0U) -/*! MAINENABLE - Main enable for I 2S function in this Flexcomm - * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags - * are reset. No other channel pairs can be enabled. - * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. - */ -#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) - -#define I2S_CFG1_DATAPAUSE_MASK (0x2U) -#define I2S_CFG1_DATAPAUSE_SHIFT (1U) -/*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer - * and the FIFO. This could be done in order to change streams, or while restarting after a data - * underflow or overflow. When paused, FIFO operations can be done without corrupting data that is - * in the process of being sent or received. Once a data pause has been requested, the interface - * may need to complete sending data that was in progress before interrupting the flow of data. - * Software must check that the pause is actually in effect before taking action. This is done by - * monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer - * will resume at the beginning of the next frame. - * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. - * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. - */ -#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) - -#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) -#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) -/*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field - * whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this - * Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs - * in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. - * 0b00..1 I2S channel pairs in this flexcomm - * 0b01..2 I2S channel pairs in this flexcomm - * 0b10..3 I2S channel pairs in this flexcomm - * 0b11..4 I2S channel pairs in this flexcomm - */ -#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) - -#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) -#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) -/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. - * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. - * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of - * SCK, when divided from the Flexcomm function clock. - * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. - * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. - */ -#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) - -#define I2S_CFG1_MODE_MASK (0xC0U) -#define I2S_CFG1_MODE_SHIFT (6U) -/*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all - * supported cases. See Formats and modes for examples. - * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece - * of left channel data occurring during the first phase, and one pieces of right channel data occurring - * during the second phase. In this mode, the data region begins one clock after the leading WS edge for the - * frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If - * FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. - * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0. - * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame. - * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame. - */ -#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) - -#define I2S_CFG1_RIGHTLOW_MASK (0x100U) -#define I2S_CFG1_RIGHTLOW_SHIFT (8U) -/*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left - * and right channel data as it is transferred to or from the FIFO. This bit is not used if the - * data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 - * of this register) = 1, the one channel to be used is the nominally the left channel. POSITION - * can still place that data in the frame where right channel data is normally located. if all - * enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. - * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO - * bits 31:16 are used for the right channel. - * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO - * bits 15:0 are used for the right channel. - */ -#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) - -#define I2S_CFG1_LEFTJUST_MASK (0x200U) -#define I2S_CFG1_LEFTJUST_SHIFT (9U) -/*! LEFTJUST - Left Justify data. - * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting - * from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data - * in the stream on the data bus. - * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting - * from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would - * correspond to left justified data in the stream on the data bus. - */ -#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) - -#define I2S_CFG1_ONECHANNEL_MASK (0x400U) -#define I2S_CFG1_ONECHANNEL_SHIFT (10U) -/*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit - * applies only to the first I2S channel pair. Other channel pairs may select this mode - * independently in their separate CFG1 registers. - * 0b0..I2S data for this channel pair is treated as left and right channels. - * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this - * pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a - * clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel - * of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side - * (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data - * for the single channel of data is placed at the clock defined by POSITION. - */ -#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) - -#define I2S_CFG1_SCK_POL_MASK (0x1000U) -#define I2S_CFG1_SCK_POL_SHIFT (12U) -/*! SCK_POL - SCK polarity. - * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). - * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges. - */ -#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) - -#define I2S_CFG1_WS_POL_MASK (0x2000U) -#define I2S_CFG1_WS_POL_SHIFT (13U) -/*! WS_POL - WS polarity. - * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S). - * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). - */ -#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) - -#define I2S_CFG1_DATALEN_MASK (0x1F0000U) -#define I2S_CFG1_DATALEN_SHIFT (16U) -/*! DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or - * received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received - * from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the - * I2S: Determines the size of data transfers between the FIFO and the I2S - * serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of - * right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse - * at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to - * 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = - * data is 32 bits in length - */ -#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) -/*! @} */ - -/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ -/*! @{ */ - -#define I2S_CFG2_FRAMELEN_MASK (0x7FFU) -#define I2S_CFG2_FRAMELEN_SHIFT (0U) -/*! FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the - * frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported - * 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x7FF = frame is - * 2048 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in - * mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger - * than DATALEN in order for the WS pulse to be generated correctly. - */ -#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) - -#define I2S_CFG2_POSITION_MASK (0x1FF0000U) -#define I2S_CFG2_POSITION_SHIFT (16U) -/*! POSITION - Data Position. Defines the location within the frame of the data for this channel - * pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION - * defines the location of data in both the left phase and right phase, starting one clock after - * the WS edge. In other modes, POSITION defines the location of data within the entire frame. - * ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The - * combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels - * do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit - * position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS - * phase. 0x002 = data begins at bit position 2 within the frame or WS phase. - */ -#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) -/*! @} */ - -/*! @name STAT - Status register for the primary channel pair. */ -/*! @{ */ - -#define I2S_STAT_BUSY_MASK (0x1U) -#define I2S_STAT_BUSY_SHIFT (0U) -/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. - * 0b0..The transmitter/receiver for channel pair is currently idle. - * 0b1..The transmitter/receiver for channel pair is currently processing data. - */ -#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) - -#define I2S_STAT_SLVFRMERR_MASK (0x2U) -#define I2S_STAT_SLVFRMERR_SHIFT (1U) -/*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as - * a slave. An error indicates that the incoming WS signal did not transition as expected due to - * a mismatch between FRAMELEN and the actual incoming I2S stream. - * 0b0..No error has been recorded. - * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. - */ -#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) - -#define I2S_STAT_LR_MASK (0x4U) -#define I2S_STAT_LR_SHIFT (2U) -/*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to - * be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data - * being processed for the currently busy channel pair. - * 0b0..Left channel. - * 0b1..Right channel. - */ -#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) - -#define I2S_STAT_DATAPAUSED_MASK (0x8U) -#define I2S_STAT_DATAPAUSED_SHIFT (3U) -/*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels - * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for - * an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. - * 0b1..A data pause has been requested and is now in force. - */ -#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) -/*! @} */ - -/*! @name DIV - Clock divider, used by all channel pairs. */ -/*! @{ */ - -#define I2S_DIV_DIV_MASK (0xFFFU) -#define I2S_DIV_DIV_SHIFT (0U) -/*! DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The - * Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. - * 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is - * divided by 4,096. - */ -#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) -/*! @} */ - -/*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */ -/*! @{ */ - -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U) -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U) -/*! PAIRENABLE - Enable for this channel pair. - * 0b0..This I2S channel pair is disabled. - * 0b1..This I2S channel pair is enabled. - */ -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK) - -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U) -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U) -/*! ONECHANNEL - Single channel mode. - * 0b0..I2S data for this channel pair is treated as left and right channels. - * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. - */ -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK) -/*! @} */ - -/* The count of I2S_SECCHANNEL_PCFG1 */ -#define I2S_SECCHANNEL_PCFG1_COUNT (3U) - -/*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */ -/*! @{ */ - -#define I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U) -#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U) -/*! POSITION - Data Position. - */ -#define I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK) -/*! @} */ - -/* The count of I2S_SECCHANNEL_PCFG2 */ -#define I2S_SECCHANNEL_PCFG2_COUNT (3U) - -/*! @name SECCHANNEL_PSTAT - Status register for channel pair */ -/*! @{ */ - -#define I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U) -#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U) -/*! BUSY - Busy status for this channel pair. - * 0b0..The transmitter/receiver for this channel pair is currently idle. - * 0b1..The transmitter/receiver for this channel pair is currently processing data. - */ -#define I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK) - -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U) -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U) -/*! SLVFRMERR - Save Frame Error flag. - */ -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK) - -#define I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U) -#define I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U) -/*! LR - Left/Right indication. - */ -#define I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK) - -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U) -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U) -/*! DATAPAUSED - Data Paused status flag. - * 0b0..Data is not currently paused. - * 0b1..A data pause has been requested and is now in force. - */ -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK) -/*! @} */ - -/* The count of I2S_SECCHANNEL_PSTAT */ -#define I2S_SECCHANNEL_PSTAT_COUNT (3U) - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ - -#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) -#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) - -#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) -#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) - -#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) -#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) -/*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX - * FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is - * cleared, new data is provided, and the I2S is un-paused. - * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 - * bits or less, or when MONO = 1 for this channel pair. - * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. - */ -#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) - -#define I2S_FIFOCFG_PACK48_MASK (0x8U) -#define I2S_FIFOCFG_PACK48_SHIFT (3U) -/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. - * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values. - * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. - */ -#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) - -#define I2S_FIFOCFG_SIZE_MASK (0x30U) -#define I2S_FIFOCFG_SIZE_SHIFT (4U) -/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 - * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - */ -#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) - -#define I2S_FIFOCFG_DMATX_MASK (0x1000U) -#define I2S_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) - -#define I2S_FIFOCFG_DMARX_MASK (0x2000U) -#define I2S_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) - -#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) -#define I2S_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in - * FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) - -#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) -#define I2S_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in - * FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) - -#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) -/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - */ -#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) - -#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) -/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - */ -#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ - -#define I2S_FIFOSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow - * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is - * needed. Cleared by writing a 1 to this bit. - */ -#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) - -#define I2S_FIFOSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA - * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - */ -#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) - -#define I2S_FIFOSTAT_PERINT_MASK (0x8U) -#define I2S_FIFOSTAT_PERINT_SHIFT (3U) -/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted - * an interrupt. The details can be found by reading the peripheral's STAT register. - */ -#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) - -#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) -/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - */ -#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) - -#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) -/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be - * written. When 0, the transmit FIFO is full and another write would cause it to overflow. - */ -#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) - -#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - */ -#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) - -#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) -#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) -/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to - * prevent the peripheral from causing an overflow. - */ -#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) - -#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY - * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at - * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be - * 0. - */ -#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) - -#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and - * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the - * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be - * 1. - */ -#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ - -#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) - -#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) - -#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) -#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled - * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to - * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO - * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX - * FIFO level decreases to 15 entries (is no longer full). - */ -#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) - -#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data - * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level - * can wake up the device just enough to perform DMA, then return to the reduced power mode. See - * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no - * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX - * FIFO has received 16 entries (has become full). - */ -#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ - -#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) -#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) - -#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) -#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) - -#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases - * to the level specified by TXLVL in the FIFOTRIG register. - */ -#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) - -#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level - * increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ - -#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) -#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) -/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) - -#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) -#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) -/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) - -#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) -/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) - -#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) -/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ - -#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. - */ -#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) - -#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. - */ -#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) - -#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO level interrupt. - */ -#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) - -#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO level interrupt. - */ -#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) - -#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) -#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) -/*! PERINT - Peripheral interrupt. - */ -#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ - -#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFOWR_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details. - */ -#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ - -#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) -#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. - */ -#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ - -#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORD_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. The number of bits used depends on configuration details. - */ -#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ - -#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48H_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. - */ -#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ - -#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. - */ -#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ - -#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. - */ -#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) -/*! @} */ - -/*! @name FIFOSIZE - FIFO size register */ -/*! @{ */ - -#define I2S_FIFOSIZE_FIFOSIZE_MASK (0x1FU) -#define I2S_FIFOSIZE_FIFOSIZE_SHIFT (0U) -/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - */ -#define I2S_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSIZE_FIFOSIZE_SHIFT)) & I2S_FIFOSIZE_FIFOSIZE_MASK) -/*! @} */ - -/*! @name ID - I2S Module identification */ -/*! @{ */ - -#define I2S_ID_APERTURE_MASK (0xFFU) -#define I2S_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - */ -#define I2S_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_APERTURE_SHIFT)) & I2S_ID_APERTURE_MASK) - -#define I2S_ID_MINOR_REV_MASK (0xF00U) -#define I2S_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation, starting at 0. - */ -#define I2S_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK) - -#define I2S_ID_MAJOR_REV_MASK (0xF000U) -#define I2S_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation, starting at 0. - */ -#define I2S_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK) - -#define I2S_ID_ID_MASK (0xFFFF0000U) -#define I2S_ID_ID_SHIFT (16U) -/*! ID - Unique module identifier for this IP block. - */ -#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2S_Register_Masks */ - - -/* I2S - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral I2S0 base address */ - #define I2S0_BASE (0x50086000u) - /** Peripheral I2S0 base address */ - #define I2S0_BASE_NS (0x40086000u) - /** Peripheral I2S0 base pointer */ - #define I2S0 ((I2S_Type *)I2S0_BASE) - /** Peripheral I2S0 base pointer */ - #define I2S0_NS ((I2S_Type *)I2S0_BASE_NS) - /** Peripheral I2S1 base address */ - #define I2S1_BASE (0x50087000u) - /** Peripheral I2S1 base address */ - #define I2S1_BASE_NS (0x40087000u) - /** Peripheral I2S1 base pointer */ - #define I2S1 ((I2S_Type *)I2S1_BASE) - /** Peripheral I2S1 base pointer */ - #define I2S1_NS ((I2S_Type *)I2S1_BASE_NS) - /** Peripheral I2S2 base address */ - #define I2S2_BASE (0x50088000u) - /** Peripheral I2S2 base address */ - #define I2S2_BASE_NS (0x40088000u) - /** Peripheral I2S2 base pointer */ - #define I2S2 ((I2S_Type *)I2S2_BASE) - /** Peripheral I2S2 base pointer */ - #define I2S2_NS ((I2S_Type *)I2S2_BASE_NS) - /** Peripheral I2S3 base address */ - #define I2S3_BASE (0x50089000u) - /** Peripheral I2S3 base address */ - #define I2S3_BASE_NS (0x40089000u) - /** Peripheral I2S3 base pointer */ - #define I2S3 ((I2S_Type *)I2S3_BASE) - /** Peripheral I2S3 base pointer */ - #define I2S3_NS ((I2S_Type *)I2S3_BASE_NS) - /** Peripheral I2S4 base address */ - #define I2S4_BASE (0x5008A000u) - /** Peripheral I2S4 base address */ - #define I2S4_BASE_NS (0x4008A000u) - /** Peripheral I2S4 base pointer */ - #define I2S4 ((I2S_Type *)I2S4_BASE) - /** Peripheral I2S4 base pointer */ - #define I2S4_NS ((I2S_Type *)I2S4_BASE_NS) - /** Peripheral I2S5 base address */ - #define I2S5_BASE (0x50096000u) - /** Peripheral I2S5 base address */ - #define I2S5_BASE_NS (0x40096000u) - /** Peripheral I2S5 base pointer */ - #define I2S5 ((I2S_Type *)I2S5_BASE) - /** Peripheral I2S5 base pointer */ - #define I2S5_NS ((I2S_Type *)I2S5_BASE_NS) - /** Peripheral I2S6 base address */ - #define I2S6_BASE (0x50097000u) - /** Peripheral I2S6 base address */ - #define I2S6_BASE_NS (0x40097000u) - /** Peripheral I2S6 base pointer */ - #define I2S6 ((I2S_Type *)I2S6_BASE) - /** Peripheral I2S6 base pointer */ - #define I2S6_NS ((I2S_Type *)I2S6_BASE_NS) - /** Peripheral I2S7 base address */ - #define I2S7_BASE (0x50098000u) - /** Peripheral I2S7 base address */ - #define I2S7_BASE_NS (0x40098000u) - /** Peripheral I2S7 base pointer */ - #define I2S7 ((I2S_Type *)I2S7_BASE) - /** Peripheral I2S7 base pointer */ - #define I2S7_NS ((I2S_Type *)I2S7_BASE_NS) - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS_NS { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS_NS { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS } -#else - /** Peripheral I2S0 base address */ - #define I2S0_BASE (0x40086000u) - /** Peripheral I2S0 base pointer */ - #define I2S0 ((I2S_Type *)I2S0_BASE) - /** Peripheral I2S1 base address */ - #define I2S1_BASE (0x40087000u) - /** Peripheral I2S1 base pointer */ - #define I2S1 ((I2S_Type *)I2S1_BASE) - /** Peripheral I2S2 base address */ - #define I2S2_BASE (0x40088000u) - /** Peripheral I2S2 base pointer */ - #define I2S2 ((I2S_Type *)I2S2_BASE) - /** Peripheral I2S3 base address */ - #define I2S3_BASE (0x40089000u) - /** Peripheral I2S3 base pointer */ - #define I2S3 ((I2S_Type *)I2S3_BASE) - /** Peripheral I2S4 base address */ - #define I2S4_BASE (0x4008A000u) - /** Peripheral I2S4 base pointer */ - #define I2S4 ((I2S_Type *)I2S4_BASE) - /** Peripheral I2S5 base address */ - #define I2S5_BASE (0x40096000u) - /** Peripheral I2S5 base pointer */ - #define I2S5 ((I2S_Type *)I2S5_BASE) - /** Peripheral I2S6 base address */ - #define I2S6_BASE (0x40097000u) - /** Peripheral I2S6 base pointer */ - #define I2S6 ((I2S_Type *)I2S6_BASE) - /** Peripheral I2S7 base address */ - #define I2S7_BASE (0x40098000u) - /** Peripheral I2S7 base pointer */ - #define I2S7 ((I2S_Type *)I2S7_BASE) - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } -#endif -/** Interrupt vectors for the I2S peripheral type */ -#define I2S_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2S_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer - * @{ - */ - -/** INPUTMUX - Register Layout Typedef */ -typedef struct { - __IO uint32_t SCT0_INMUX[7]; /**< Input mux register for SCT0 input, array offset: 0x0, array step: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t TIMER0CAPTSEL[4]; /**< Capture select registers for TIMER0 inputs, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[16]; - __IO uint32_t TIMER1CAPTSEL[4]; /**< Capture select registers for TIMER1 inputs, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_2[16]; - __IO uint32_t TIMER2CAPTSEL[4]; /**< Capture select registers for TIMER2 inputs, array offset: 0x60, array step: 0x4 */ - uint8_t RESERVED_3[80]; - __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ - __IO uint32_t DMA0_ITRIG_INMUX[23]; /**< Trigger select register for DMA0 channel, array offset: 0xE0, array step: 0x4 */ - uint8_t RESERVED_4[36]; - __IO uint32_t DMA0_OTRIG_INMUX[4]; /**< DMA0 output trigger selection to become DMA0 trigger, array offset: 0x160, array step: 0x4 */ - uint8_t RESERVED_5[16]; - __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ - __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ - uint8_t RESERVED_6[24]; - __IO uint32_t TIMER3CAPTSEL[4]; /**< Capture select registers for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */ - uint8_t RESERVED_7[16]; - __IO uint32_t TIMER4CAPTSEL[4]; /**< Capture select registers for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */ - uint8_t RESERVED_8[16]; - __IO uint32_t PINTSECSEL[2]; /**< Pin interrupt secure select register, array offset: 0x1E0, array step: 0x4 */ - uint8_t RESERVED_9[24]; - __IO uint32_t DMA1_ITRIG_INMUX[10]; /**< Trigger select register for DMA1 channel, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_10[24]; - __IO uint32_t DMA1_OTRIG_INMUX[4]; /**< DMA1 output trigger selection to become DMA1 trigger, array offset: 0x240, array step: 0x4 */ - uint8_t RESERVED_11[1264]; - __IO uint32_t DMA0_REQ_ENA; /**< Enable DMA0 requests, offset: 0x740 */ - uint8_t RESERVED_12[4]; - __O uint32_t DMA0_REQ_ENA_SET; /**< Set one or several bits in DMA0_REQ_ENA register, offset: 0x748 */ - uint8_t RESERVED_13[4]; - __O uint32_t DMA0_REQ_ENA_CLR; /**< Clear one or several bits in DMA0_REQ_ENA register, offset: 0x750 */ - uint8_t RESERVED_14[12]; - __IO uint32_t DMA1_REQ_ENA; /**< Enable DMA1 requests, offset: 0x760 */ - uint8_t RESERVED_15[4]; - __O uint32_t DMA1_REQ_ENA_SET; /**< Set one or several bits in DMA1_REQ_ENA register, offset: 0x768 */ - uint8_t RESERVED_16[4]; - __O uint32_t DMA1_REQ_ENA_CLR; /**< Clear one or several bits in DMA1_REQ_ENA register, offset: 0x770 */ - uint8_t RESERVED_17[12]; - __IO uint32_t DMA0_ITRIG_ENA; /**< Enable DMA0 triggers, offset: 0x780 */ - uint8_t RESERVED_18[4]; - __O uint32_t DMA0_ITRIG_ENA_SET; /**< Set one or several bits in DMA0_ITRIG_ENA register, offset: 0x788 */ - uint8_t RESERVED_19[4]; - __O uint32_t DMA0_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA0_ITRIG_ENA register, offset: 0x790 */ - uint8_t RESERVED_20[12]; - __IO uint32_t DMA1_ITRIG_ENA; /**< Enable DMA1 triggers, offset: 0x7A0 */ - uint8_t RESERVED_21[4]; - __O uint32_t DMA1_ITRIG_ENA_SET; /**< Set one or several bits in DMA1_ITRIG_ENA register, offset: 0x7A8 */ - uint8_t RESERVED_22[4]; - __O uint32_t DMA1_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA1_ITRIG_ENA register, offset: 0x7B0 */ -} INPUTMUX_Type; - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks - * @{ - */ - -/*! @name SCT0_INMUX - Input mux register for SCT0 input */ -/*! @{ */ - -#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU) -#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) -/*! INP_N - Input number to SCT0 inputs 0 to 6.. - * 0b00000..SCT_GPI0 function selected from IOCON register - * 0b00001..SCT_GPI1 function selected from IOCON register - * 0b00010..SCT_GPI2 function selected from IOCON register - * 0b00011..SCT_GPI3 function selected from IOCON register - * 0b00100..SCT_GPI4 function selected from IOCON register - * 0b00101..SCT_GPI5 function selected from IOCON register - * 0b00110..SCT_GPI6 function selected from IOCON register - * 0b00111..SCT_GPI7 function selected from IOCON register - * 0b01000..T0_OUT0 ctimer 0 match[0] output - * 0b01001..T1_OUT0 ctimer 1 match[0] output - * 0b01010..T2_OUT0 ctimer 2 match[0] output - * 0b01011..T3_OUT0 ctimer 3 match[0] output - * 0b01100..T4_OUT0 ctimer 4 match[0] output - * 0b01101..ADC_IRQ interrupt request from ADC - * 0b01110..GPIOINT_BMATCH - * 0b01111..USB0_FRAME_TOGGLE - * 0b10000..USB1_FRAME_TOGGLE - * 0b10001..COMP_OUTPUT output from analog comparator - * 0b10010..I2S_SHARED_SCK[0] output from I2S pin sharing - * 0b10011..I2S_SHARED_SCK[1] output from I2S pin sharing - * 0b10100..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b10101..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b10110..ARM_TXEV interrupt event from cpu0 or cpu1 - * 0b10111..DEBUG_HALTED from cpu0 or cpu1 - * 0b11000-0b11111..None - */ -#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK) -/*! @} */ - -/* The count of INPUTMUX_SCT0_INMUX */ -#define INPUTMUX_SCT0_INMUX_COUNT (7U) - -/*! @name TIMER0CAPTSEL - Capture select registers for TIMER0 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..None - * 0b10010..None - * 0b10011..None - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER0CAPTSEL */ -#define INPUTMUX_TIMER0CAPTSEL_COUNT (4U) - -/*! @name TIMER1CAPTSEL - Capture select registers for TIMER1 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..None - * 0b10010..None - * 0b10011..None - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER1CAPTSEL */ -#define INPUTMUX_TIMER1CAPTSEL_COUNT (4U) - -/*! @name TIMER2CAPTSEL - Capture select registers for TIMER2 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..None - * 0b10010..None - * 0b10011..None - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER2CAPTSEL */ -#define INPUTMUX_TIMER2CAPTSEL_COUNT (4U) - -/*! @name PINTSEL - Pin interrupt select register */ -/*! @{ */ - -#define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU) -#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) -/*! INTPIN - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = - * (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. - */ -#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PINTSEL */ -#define INPUTMUX_PINTSEL_COUNT (8U) - -/*! @name DMA0_ITRIG_INMUX - Trigger select register for DMA0 channel */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U) -/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22). - * 0b00000..Pin interrupt 0 - * 0b00001..Pin interrupt 1 - * 0b00010..Pin interrupt 2 - * 0b00011..Pin interrupt 3 - * 0b00100..Timer CTIMER0 Match 0 - * 0b00101..Timer CTIMER0 Match 1 - * 0b00110..Timer CTIMER1 Match 0 - * 0b00111..Timer CTIMER1 Match 1 - * 0b01000..Timer CTIMER2 Match 0 - * 0b01001..Timer CTIMER2 Match 1 - * 0b01010..Timer CTIMER3 Match 0 - * 0b01011..Timer CTIMER3 Match 1 - * 0b01100..Timer CTIMER4 Match 0 - * 0b01101..Timer CTIMER4 Match 1 - * 0b01110..COMP_OUTPUT - * 0b01111..DMA0 output trigger mux 0 - * 0b10000..DMA0 output trigger mux 1 - * 0b10001..DMA0 output trigger mux 1 - * 0b10010..DMA0 output trigger mux 3 - * 0b10011..SCT0 DMA request 0 - * 0b10100..SCT0 DMA request 1 - * 0b10101..HASH DMA RX trigger - * 0b10110-0b11111..None - */ -#define INPUTMUX_DMA0_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA0_ITRIG_INMUX */ -#define INPUTMUX_DMA0_ITRIG_INMUX_COUNT (23U) - -/*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection to become DMA0 trigger */ -/*! @{ */ - -#define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U) -/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22). - */ -#define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA0_OTRIG_INMUX */ -#define INPUTMUX_DMA0_OTRIG_INMUX_COUNT (4U) - -/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ -/*! @{ */ - -#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) -/*! CLKIN - Clock source number (decimal value) for frequency measure function reference clock: - * 0b00000..External main crystal oscilator (Clock_in). - * 0b00001..FRO 12MHz clock. - * 0b00010..FRO 96MHz clock. - * 0b00011..Watchdog oscillator / FRO1MHz clock. - * 0b00100..32 kHz oscillator (32k_clk) clock. - * 0b00101..main clock (main_clock). - * 0b00110..FREQME_GPIO_CLK_A. - * 0b00111..FREQME_GPIO_CLK_B. - */ -#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) -/*! @} */ - -/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ -/*! @{ */ - -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) -/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: - * 0b00000..External main crystal oscilator (Clock_in). - * 0b00001..FRO 12MHz clock. - * 0b00010..FRO 96MHz clock. - * 0b00011..Watchdog oscillator / FRO1MHz clock. - * 0b00100..32 kHz oscillator (32k_clk) clock. - * 0b00101..main clock (main_clock). - * 0b00110..FREQME_GPIO_CLK_A. - * 0b00111..FREQME_GPIO_CLK_B. - */ -#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) -/*! @} */ - -/*! @name TIMER3CAPTSEL - Capture select registers for TIMER3 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..None - * 0b10010..None - * 0b10011..None - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER3CAPTSEL */ -#define INPUTMUX_TIMER3CAPTSEL_COUNT (4U) - -/*! @name TIMER4CAPTSEL - Capture select registers for TIMER4 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..None - * 0b10010..None - * 0b10011..None - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER4CAPTSEL */ -#define INPUTMUX_TIMER4CAPTSEL_COUNT (4U) - -/*! @name PINTSECSEL - Pin interrupt secure select register */ -/*! @{ */ - -#define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU) -#define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U) -/*! INTPIN - Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: - * INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31. - */ -#define INPUTMUX_PINTSECSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PINTSECSEL */ -#define INPUTMUX_PINTSECSEL_COUNT (2U) - -/*! @name DMA1_ITRIG_INMUX - Trigger select register for DMA1 channel */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0xFU) -#define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U) -/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9). - * 0b0000..Pin interrupt 0 - * 0b0001..Pin interrupt 1 - * 0b0010..Pin interrupt 2 - * 0b0011..Pin interrupt 3 - * 0b0100..Timer CTIMER0 Match 0 - * 0b0101..Timer CTIMER0 Match 1 - * 0b0110..Timer CTIMER2 Match 0 - * 0b0111..Timer CTIMER4 Match 0 - * 0b1000..DMA1 output trigger mux 0 - * 0b1001..DMA1 output trigger mux 1 - * 0b1010..DMA1 output trigger mux 2 - * 0b1011..DMA1 output trigger mux 3 - * 0b1100..SCT0 DMA request 0 - * 0b1101..SCT0 DMA request 1 - * 0b1110..HASH DMA RX trigger - * 0b1111..None - */ -#define INPUTMUX_DMA1_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA1_ITRIG_INMUX */ -#define INPUTMUX_DMA1_ITRIG_INMUX_COUNT (10U) - -/*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection to become DMA1 trigger */ -/*! @{ */ - -#define INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK (0xFU) -#define INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT (0U) -/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9). - */ -#define INPUTMUX_DMA1_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA1_OTRIG_INMUX */ -#define INPUTMUX_DMA1_OTRIG_INMUX_COUNT (4U) - -/*! @name DMA0_REQ_ENA - Enable DMA0 requests */ -/*! @{ */ - -#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK (0x7FFFFFU) -#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT (0U) -/*! REQ_ENA - Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK) -/*! @} */ - -/*! @name DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK (0x7FFFFFU) -#define INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT (0U) -/*! SET - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register - */ -#define INPUTMUX_DMA0_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK (0x7FFFFFU) -#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT (0U) -/*! CLR - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register - */ -#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK) -/*! @} */ - -/*! @name DMA1_REQ_ENA - Enable DMA1 requests */ -/*! @{ */ - -#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK (0x3FFU) -#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT (0U) -/*! REQ_ENA - Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK) -/*! @} */ - -/*! @name DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK (0x3FFU) -#define INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT (0U) -/*! SET - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register - */ -#define INPUTMUX_DMA1_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK (0x3FFU) -#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT (0U) -/*! CLR - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register - */ -#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_ENA - Enable DMA0 triggers */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK (0x3FFFFFU) -#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) -/*! ITRIG_ENA - Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK (0x3FFFFFU) -#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT (0U) -/*! SET - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIG_ENA register - */ -#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK (0x3FFFFFU) -#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT (0U) -/*! CLR - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIG_ENA register - */ -#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK) -/*! @} */ - -/*! @name DMA1_ITRIG_ENA - Enable DMA1 triggers */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK (0x7FFFU) -#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) -/*! ITRIG_ENA - Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK) -/*! @} */ - -/*! @name DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK (0x7FFFU) -#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT (0U) -/*! SET - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no - * change in DMA1_ITRIG_ENA register - */ -#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK (0x7FFFU) -#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT (0U) -/*! CLR - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no - * change in DMA1_ITRIG_ENA register - */ -#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group INPUTMUX_Register_Masks */ - - -/* INPUTMUX - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE (0x50006000u) - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE_NS (0x40006000u) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS) - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS { INPUTMUX } - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX_BASE_NS } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS_NS { INPUTMUX_NS } -#else - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE (0x40006000u) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS { INPUTMUX } -#endif - -/*! - * @} - */ /* end of group INPUTMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- IOCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer - * @{ - */ - -/** IOCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ -} IOCON_Type; - -/* ---------------------------------------------------------------------------- - -- IOCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Register_Masks IOCON Register Masks - * @{ - */ - -/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ -/*! @{ */ - -#define IOCON_PIO_FUNC_MASK (0xFU) -#define IOCON_PIO_FUNC_SHIFT (0U) -/*! FUNC - Selects pin function. - * 0b0000..Alternative connection 0. - * 0b0001..Alternative connection 1. - * 0b0010..Alternative connection 2. - * 0b0011..Alternative connection 3. - * 0b0100..Alternative connection 4. - * 0b0101..Alternative connection 5. - * 0b0110..Alternative connection 6. - * 0b0111..Alternative connection 7. - */ -#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) - -#define IOCON_PIO_MODE_MASK (0x30U) -#define IOCON_PIO_MODE_SHIFT (4U) -/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) - -#define IOCON_PIO_SLEW_MASK (0x40U) -#define IOCON_PIO_SLEW_SHIFT (6U) -/*! SLEW - Driver slew rate. - * 0b0..Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - * 0b1..Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - */ -#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) - -#define IOCON_PIO_INVERT_MASK (0x80U) -#define IOCON_PIO_INVERT_SHIFT (7U) -/*! INVERT - Input polarity. - * 0b0..Disabled. Input function is not inverted. - * 0b1..Enabled. Input is function inverted. - */ -#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) - -#define IOCON_PIO_DIGIMODE_MASK (0x100U) -#define IOCON_PIO_DIGIMODE_SHIFT (8U) -/*! DIGIMODE - Select Digital mode. - * 0b0..Disable digital mode. Digital input set to 0. - * 0b1..Enable Digital mode. Digital input is enabled. - */ -#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) - -#define IOCON_PIO_OD_MASK (0x200U) -#define IOCON_PIO_OD_SHIFT (9U) -/*! OD - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). - * 0b0..Normal. Normal push-pull output - * 0b1..Open-drain. Simulated open-drain output (high drive disabled). - */ -#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) - -#define IOCON_PIO_ASW_MASK (0x400U) -#define IOCON_PIO_ASW_SHIFT (10U) -/*! ASW - Analog switch input control. - * 0b0..Analog switch is open. (disable) - * 0b1..Analog switch is closed. (enable) - */ -#define IOCON_PIO_ASW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW_SHIFT)) & IOCON_PIO_ASW_MASK) - -#define IOCON_PIO_SSEL_MASK (0x800U) -#define IOCON_PIO_SSEL_SHIFT (11U) -/*! SSEL - Supply Selection bit. - * 0b0..3V3 Signaling in I2C Mode. - * 0b1..1V8 Signaling in I2C Mode. - */ -#define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK) - -#define IOCON_PIO_FILTEROFF_MASK (0x1000U) -#define IOCON_PIO_FILTEROFF_SHIFT (12U) -/*! FILTEROFF - Controls input glitch filter. - * 0b0..Filter enabled. - * 0b1..Filter disabled. - */ -#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) - -#define IOCON_PIO_ECS_MASK (0x2000U) -#define IOCON_PIO_ECS_SHIFT (13U) -/*! ECS - Pull-up current source enable in I2C mode. - * 0b1..Enabled. Pull resistor is conencted. - * 0b0..Disabled. IO is in open drain cell. - */ -#define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK) - -#define IOCON_PIO_EGP_MASK (0x4000U) -#define IOCON_PIO_EGP_SHIFT (14U) -/*! EGP - Switch between GPIO mode and I2C mode. - * 0b0..I2C mode. - * 0b1..GPIO mode. - */ -#define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK) - -#define IOCON_PIO_I2CFILTER_MASK (0x8000U) -#define IOCON_PIO_I2CFILTER_SHIFT (15U) -/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. - * 0b0..I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. - * 0b1..I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. - */ -#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) -/*! @} */ - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT (2U) - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT2 (32U) - - -/*! - * @} - */ /* end of group IOCON_Register_Masks */ - - -/* IOCON - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral IOCON base address */ - #define IOCON_BASE (0x50001000u) - /** Peripheral IOCON base address */ - #define IOCON_BASE_NS (0x40001000u) - /** Peripheral IOCON base pointer */ - #define IOCON ((IOCON_Type *)IOCON_BASE) - /** Peripheral IOCON base pointer */ - #define IOCON_NS ((IOCON_Type *)IOCON_BASE_NS) - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS { IOCON_BASE } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS { IOCON } - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS_NS { IOCON_BASE_NS } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS_NS { IOCON_NS } -#else - /** Peripheral IOCON base address */ - #define IOCON_BASE (0x40001000u) - /** Peripheral IOCON base pointer */ - #define IOCON ((IOCON_Type *)IOCON_BASE) - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS { IOCON_BASE } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS { IOCON } -#endif - -/*! - * @} - */ /* end of group IOCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MRT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer - * @{ - */ - -/** MRT - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x10 */ - __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ - __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ - __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ - __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ - } CHANNEL[4]; - uint8_t RESERVED_0[176]; - __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ - __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ - __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ -} MRT_Type; - -/* ---------------------------------------------------------------------------- - -- MRT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Register_Masks MRT Register Masks - * @{ - */ - -/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ -/*! @{ */ - -#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) -/*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT - * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to - * this bit field starts the timer immediately. If the timer is running, writing a zero to this - * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer - * stops at the end of the time interval. - */ -#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) - -#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) -#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) -/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. - * This bit is write-only. Reading this bit always returns 0. - * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the - * time interval if the repeat mode is selected. - * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. - */ -#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_INTVAL */ -#define MRT_CHANNEL_INTVAL_COUNT (4U) - -/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ -/*! @{ */ - -#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) -/*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn - * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval - * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn - * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields - * returns -1 (0x00FF FFFF). - */ -#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_TIMER */ -#define MRT_CHANNEL_TIMER_COUNT (4U) - -/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ -/*! @{ */ - -#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) -#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) -/*! INTEN - Enable the TIMERn interrupt. - * 0b0..Disabled. TIMERn interrupt is disabled. - * 0b1..Enabled. TIMERn interrupt is enabled. - */ -#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) - -#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) -#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) -/*! MODE - Selects timer mode. - * 0b00..Repeat interrupt mode. - * 0b01..One-shot interrupt mode. - * 0b10..One-shot stall mode. - * 0b11..Reserved. - */ -#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_CTRL */ -#define MRT_CHANNEL_CTRL_COUNT (4U) - -/*! @name CHANNEL_STAT - MRT Status register. */ -/*! @{ */ - -#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) -#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) -/*! INTFLAG - Monitors the interrupt flag. - * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. - * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If - * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt - * are raised. Writing a 1 to this bit clears the interrupt request. - */ -#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) - -#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) -#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) -/*! RUN - Indicates the state of TIMERn. This bit is read-only. - * 0b0..Idle state. TIMERn is stopped. - * 0b1..Running. TIMERn is running. - */ -#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) - -#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) -#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) -/*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG - * register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating - * modes. - * 0b0..This channel is not in use. - * 0b1..This channel is in use. - */ -#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_STAT */ -#define MRT_CHANNEL_STAT_COUNT (4U) - -/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ -/*! @{ */ - -#define MRT_MODCFG_NOC_MASK (0xFU) -#define MRT_MODCFG_NOC_SHIFT (0U) -/*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.) - */ -#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) - -#define MRT_MODCFG_NOB_MASK (0x1F0U) -#define MRT_MODCFG_NOB_SHIFT (4U) -/*! NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.) - */ -#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) - -#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) -#define MRT_MODCFG_MULTITASK_SHIFT (31U) -/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. - * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. - * 0b1..Multi-task mode. - */ -#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) -/*! @} */ - -/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ -/*! @{ */ - -#define MRT_IDLE_CH_CHAN_MASK (0xF0U) -#define MRT_IDLE_CH_CHAN_SHIFT (4U) -/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is - * positioned such that it can be used as an offset from the MRT base address in order to access - * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See - * text above for more details. - */ -#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) -/*! @} */ - -/*! @name IRQ_FLAG - Global interrupt flag register */ -/*! @{ */ - -#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) -#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) -/*! GFLAG0 - Monitors the interrupt flag of TIMER0. - * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. - * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If - * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global - * interrupt are raised. Writing a 1 to this bit clears the interrupt request. - */ -#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) - -#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) -#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) -/*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0. - */ -#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) - -#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) -#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) -/*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0. - */ -#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) - -#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) -#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) -/*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0. - */ -#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MRT_Register_Masks */ - - -/* MRT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral MRT0 base address */ - #define MRT0_BASE (0x5000D000u) - /** Peripheral MRT0 base address */ - #define MRT0_BASE_NS (0x4000D000u) - /** Peripheral MRT0 base pointer */ - #define MRT0 ((MRT_Type *)MRT0_BASE) - /** Peripheral MRT0 base pointer */ - #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS { MRT0_BASE } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS { MRT0 } - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS_NS { MRT0_NS } -#else - /** Peripheral MRT0 base address */ - #define MRT0_BASE (0x4000D000u) - /** Peripheral MRT0 base pointer */ - #define MRT0 ((MRT_Type *)MRT0_BASE) - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS { MRT0_BASE } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS { MRT0 } -#endif -/** Interrupt vectors for the MRT peripheral type */ -#define MRT_IRQS { MRT0_IRQn } - -/*! - * @} - */ /* end of group MRT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- OSTIMER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer - * @{ - */ - -/** OSTIMER - Register Layout Typedef */ -typedef struct { - __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */ - __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */ - __I uint32_t CAPTURE_L; /**< Capture Low Register, offset: 0x8 */ - __I uint32_t CAPTURE_H; /**< Capture High Register, offset: 0xC */ - __IO uint32_t MATCH_L; /**< Match Low Register, offset: 0x10 */ - __IO uint32_t MATCH_H; /**< Match High Register, offset: 0x14 */ - uint8_t RESERVED_0[4]; - __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register, offset: 0x1C */ -} OSTIMER_Type; - -/* ---------------------------------------------------------------------------- - -- OSTIMER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks - * @{ - */ - -/*! @name EVTIMERL - EVTIMER Low Register */ -/*! @{ */ - -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) -/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the lower 32 bits of the 42-bits - * EVTIMER. Note there is only one EVTIMER, readable from all domains. - */ -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) -/*! @} */ - -/*! @name EVTIMERH - EVTIMER High Register */ -/*! @{ */ - -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU) -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) -/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the upper 10 bits of the 42-bits - * EVTIMER. Note there is only one EVTIMER, readable from all domains. - */ -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) -/*! @} */ - -/*! @name CAPTURE_L - Capture Low Register */ -/*! @{ */ - -#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U) -/*! CAPTURE_VALUE - A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at - * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). - */ -#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK) -/*! @} */ - -/*! @name CAPTURE_H - Capture High Register */ -/*! @{ */ - -#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0x3FFU) -#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U) -/*! CAPTURE_VALUE - A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at - * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). - */ -#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK) -/*! @} */ - -/*! @name MATCH_L - Match Low Register */ -/*! @{ */ - -#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U) -/*! MATCH_VALUE - The value written to the MATCH (L/H) register pair is compared against the central - * EVTIMER. When a match occurs, an interrupt request is generated if enabled. - */ -#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK) -/*! @} */ - -/*! @name MATCH_H - Match High Register */ -/*! @{ */ - -#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0x3FFU) -#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U) -/*! MATCH_VALUE - The value written (upper 10 bits) to the MATCH (L/H) register pair is compared - * against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. - */ -#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK) -/*! @} */ - -/*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register */ -/*! @{ */ - -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) -/*! OSTIMER_INTRFLAG - This bit is set when a match occurs between the central 42-bits EVTIMER and - * the value programmed in the match-register pair. This bit is cleared by writing a '1'. Writes - * to clear this bit are asynchronous. It should be done before a new match value is written into - * the MATCH_L/H registers. - */ -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) - -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) -/*! OSTIMER_INTENA - When this bit is '1' an interrupt/wakeup request to the domain processor will - * be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests - * due to the OSTIMER_INTR flag are blocked. - */ -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) - -#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U) -#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U) -/*! MATCH_WR_RDY - This bit will be low when it is safe to write to reload the Match Registers. In - * typical applications it should not be necessary to test this bit. [1] - */ -#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group OSTIMER_Register_Masks */ - - -/* OSTIMER - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral OSTIMER base address */ - #define OSTIMER_BASE (0x5002D000u) - /** Peripheral OSTIMER base address */ - #define OSTIMER_BASE_NS (0x4002D000u) - /** Peripheral OSTIMER base pointer */ - #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) - /** Peripheral OSTIMER base pointer */ - #define OSTIMER_NS ((OSTIMER_Type *)OSTIMER_BASE_NS) - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS { OSTIMER } - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS_NS { OSTIMER_BASE_NS } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS_NS { OSTIMER_NS } -#else - /** Peripheral OSTIMER base address */ - #define OSTIMER_BASE (0x4002D000u) - /** Peripheral OSTIMER base pointer */ - #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS { OSTIMER } -#endif -/** Interrupt vectors for the OSTIMER peripheral type */ -#define OSTIMER_IRQS { OS_EVENT_IRQn } - -/*! - * @} - */ /* end of group OSTIMER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer - * @{ - */ - -/** PINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ - __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ - __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ - __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ - __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ - __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ - __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ - __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ - __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ - __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ - __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ - __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ - __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ -} PINT_Type; - -/* ---------------------------------------------------------------------------- - -- PINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Register_Masks PINT Register Masks - * @{ - */ - -/*! @name ISEL - Pin Interrupt Mode register */ -/*! @{ */ - -#define PINT_ISEL_PMODE_MASK (0xFFU) -#define PINT_ISEL_PMODE_SHIFT (0U) -/*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt - * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive - */ -#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) -/*! @} */ - -/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ -/*! @{ */ - -#define PINT_IENR_ENRL_MASK (0xFFU) -#define PINT_IENR_ENRL_SHIFT (0U) -/*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the - * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable - * rising edge or level interrupt. - */ -#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) -/*! @} */ - -/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ -/*! @{ */ - -#define PINT_SIENR_SETENRL_MASK (0xFFU) -#define PINT_SIENR_SETENRL_SHIFT (0U) -/*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n - * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. - */ -#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) -/*! @} */ - -/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ -/*! @{ */ - -#define PINT_CIENR_CENRL_MASK (0xFFU) -#define PINT_CIENR_CENRL_SHIFT (0U) -/*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit - * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level - * interrupt. - */ -#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) -/*! @} */ - -/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ -/*! @{ */ - -#define PINT_IENF_ENAF_MASK (0xFFU) -#define PINT_IENF_ENAF_SHIFT (0U) -/*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt. - * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt - * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active - * interrupt level HIGH. - */ -#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) -/*! @} */ - -/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ -/*! @{ */ - -#define PINT_SIENF_SETENAF_MASK (0xFFU) -#define PINT_SIENF_SETENAF_SHIFT (0U) -/*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n - * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable - * falling edge interrupt. - */ -#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) -/*! @} */ - -/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ -/*! @{ */ - -#define PINT_CIENF_CENAF_MASK (0xFFU) -#define PINT_CIENF_CENAF_SHIFT (0U) -/*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n - * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or - * falling edge interrupt disabled. - */ -#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) -/*! @} */ - -/*! @name RISE - Pin interrupt rising edge register */ -/*! @{ */ - -#define PINT_RISE_RDET_MASK (0xFFU) -#define PINT_RISE_RDET_SHIFT (0U) -/*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read - * 0: No rising edge has been detected on this pin since Reset or the last time a one was written - * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the - * last time a one was written to this bit. Write 1: clear rising edge detection for this pin. - */ -#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) -/*! @} */ - -/*! @name FALL - Pin interrupt falling edge register */ -/*! @{ */ - -#define PINT_FALL_FDET_MASK (0xFFU) -#define PINT_FALL_FDET_SHIFT (0U) -/*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read - * 0: No falling edge has been detected on this pin since Reset or the last time a one was - * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or - * the last time a one was written to this bit. Write 1: clear falling edge detection for this - * pin. - */ -#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) -/*! @} */ - -/*! @name IST - Pin interrupt status register */ -/*! @{ */ - -#define PINT_IST_PSTAT_MASK (0xFFU) -#define PINT_IST_PSTAT_SHIFT (0U) -/*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts - * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for - * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this - * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. - * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). - */ -#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) -/*! @} */ - -/*! @name PMCTRL - Pattern match interrupt control register */ -/*! @{ */ - -#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) -#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) -/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. - * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. - * 0b1..Pattern match. Interrupts are driven in response to pattern matches. - */ -#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) - -#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) -#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) -/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. - * 0b0..Disabled. RXEV output to the CPU is disabled. - * 0b1..Enabled. RXEV output to the CPU is enabled. - */ -#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) - -#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) -#define PINT_PMCTRL_PMAT_SHIFT (24U) -/*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field - * indicates that the corresponding product term is matched by the current state of the appropriate - * inputs. - */ -#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) -/*! @} */ - -/*! @name PMSRC - Pattern match interrupt bit-slice source register */ -/*! @{ */ - -#define PINT_PMSRC_SRC0_MASK (0x700U) -#define PINT_PMSRC_SRC0_SHIFT (8U) -/*! SRC0 - Selects the input source for bit slice 0 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. - */ -#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) - -#define PINT_PMSRC_SRC1_MASK (0x3800U) -#define PINT_PMSRC_SRC1_SHIFT (11U) -/*! SRC1 - Selects the input source for bit slice 1 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. - */ -#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) - -#define PINT_PMSRC_SRC2_MASK (0x1C000U) -#define PINT_PMSRC_SRC2_SHIFT (14U) -/*! SRC2 - Selects the input source for bit slice 2 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. - */ -#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) - -#define PINT_PMSRC_SRC3_MASK (0xE0000U) -#define PINT_PMSRC_SRC3_SHIFT (17U) -/*! SRC3 - Selects the input source for bit slice 3 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. - */ -#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) - -#define PINT_PMSRC_SRC4_MASK (0x700000U) -#define PINT_PMSRC_SRC4_SHIFT (20U) -/*! SRC4 - Selects the input source for bit slice 4 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. - */ -#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) - -#define PINT_PMSRC_SRC5_MASK (0x3800000U) -#define PINT_PMSRC_SRC5_SHIFT (23U) -/*! SRC5 - Selects the input source for bit slice 5 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. - */ -#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) - -#define PINT_PMSRC_SRC6_MASK (0x1C000000U) -#define PINT_PMSRC_SRC6_SHIFT (26U) -/*! SRC6 - Selects the input source for bit slice 6 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. - */ -#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) - -#define PINT_PMSRC_SRC7_MASK (0xE0000000U) -#define PINT_PMSRC_SRC7_SHIFT (29U) -/*! SRC7 - Selects the input source for bit slice 7 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. - */ -#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) -/*! @} */ - -/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ -/*! @{ */ - -#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) -#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) -/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. - * 0b0..No effect. Slice 0 is not an endpoint. - * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) - -#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) -#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) -/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. - * 0b0..No effect. Slice 1 is not an endpoint. - * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) - -#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) -#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) -/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. - * 0b0..No effect. Slice 2 is not an endpoint. - * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) - -#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) -#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) -/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. - * 0b0..No effect. Slice 3 is not an endpoint. - * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) - -#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) -#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) -/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. - * 0b0..No effect. Slice 4 is not an endpoint. - * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) - -#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) -#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) -/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. - * 0b0..No effect. Slice 5 is not an endpoint. - * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) - -#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) -#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) -/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. - * 0b0..No effect. Slice 6 is not an endpoint. - * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) - -#define PINT_PMCFG_CFG0_MASK (0x700U) -#define PINT_PMCFG_CFG0_SHIFT (8U) -/*! CFG0 - Specifies the match contribution condition for bit slice 0. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) - -#define PINT_PMCFG_CFG1_MASK (0x3800U) -#define PINT_PMCFG_CFG1_SHIFT (11U) -/*! CFG1 - Specifies the match contribution condition for bit slice 1. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) - -#define PINT_PMCFG_CFG2_MASK (0x1C000U) -#define PINT_PMCFG_CFG2_SHIFT (14U) -/*! CFG2 - Specifies the match contribution condition for bit slice 2. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) - -#define PINT_PMCFG_CFG3_MASK (0xE0000U) -#define PINT_PMCFG_CFG3_SHIFT (17U) -/*! CFG3 - Specifies the match contribution condition for bit slice 3. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) - -#define PINT_PMCFG_CFG4_MASK (0x700000U) -#define PINT_PMCFG_CFG4_SHIFT (20U) -/*! CFG4 - Specifies the match contribution condition for bit slice 4. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) - -#define PINT_PMCFG_CFG5_MASK (0x3800000U) -#define PINT_PMCFG_CFG5_SHIFT (23U) -/*! CFG5 - Specifies the match contribution condition for bit slice 5. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) - -#define PINT_PMCFG_CFG6_MASK (0x1C000000U) -#define PINT_PMCFG_CFG6_SHIFT (26U) -/*! CFG6 - Specifies the match contribution condition for bit slice 6. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) - -#define PINT_PMCFG_CFG7_MASK (0xE0000000U) -#define PINT_PMCFG_CFG7_SHIFT (29U) -/*! CFG7 - Specifies the match contribution condition for bit slice 7. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PINT_Register_Masks */ - - -/* PINT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PINT base address */ - #define PINT_BASE (0x50004000u) - /** Peripheral PINT base address */ - #define PINT_BASE_NS (0x40004000u) - /** Peripheral PINT base pointer */ - #define PINT ((PINT_Type *)PINT_BASE) - /** Peripheral PINT base pointer */ - #define PINT_NS ((PINT_Type *)PINT_BASE_NS) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE (0x50005000u) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE_NS (0x40005000u) - /** Peripheral SECPINT base pointer */ - #define SECPINT ((PINT_Type *)SECPINT_BASE) - /** Peripheral SECPINT base pointer */ - #define SECPINT_NS ((PINT_Type *)SECPINT_BASE_NS) - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS { PINT, SECPINT } - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS_NS { PINT_BASE_NS, SECPINT_BASE_NS } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS_NS { PINT_NS, SECPINT_NS } -#else - /** Peripheral PINT base address */ - #define PINT_BASE (0x40004000u) - /** Peripheral PINT base pointer */ - #define PINT ((PINT_Type *)PINT_BASE) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE (0x40005000u) - /** Peripheral SECPINT base pointer */ - #define SECPINT ((PINT_Type *)SECPINT_BASE) - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS { PINT, SECPINT } -#endif -/** Interrupt vectors for the PINT peripheral type */ -#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn } - -/*! - * @} - */ /* end of group PINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PLU Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PLU_Peripheral_Access_Layer PLU Peripheral Access Layer - * @{ - */ - -/** PLU - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x20 */ - __IO uint32_t INP_MUX[5]; /**< LUTn input x MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */ - uint8_t RESERVED_0[12]; - } LUT[26]; - uint8_t RESERVED_0[1216]; - __IO uint32_t LUT_TRUTH[26]; /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25, array offset: 0x800, array step: 0x4 */ - uint8_t RESERVED_1[152]; - __I uint32_t OUTPUTS; /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */ - __IO uint32_t WAKEINT_CTRL; /**< Wakeup interrupt control for PLU, offset: 0x904 */ - uint8_t RESERVED_2[760]; - __IO uint32_t OUTPUT_MUX[8]; /**< Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */ -} PLU_Type; - -/* ---------------------------------------------------------------------------- - -- PLU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PLU_Register_Masks PLU Register Masks - * @{ - */ - -/*! @name LUT_INP_MUX - LUTn input x MUX */ -/*! @{ */ - -#define PLU_LUT_INP_MUX_LUTn_INPx_MASK (0x3FU) -#define PLU_LUT_INP_MUX_LUTn_INPx_SHIFT (0U) -/*! LUTn_INPx - Selects the input source to be connected to LUT25 input4. For each LUT, the slot - * associated with the output from LUTn itself is tied low. - * 0b000000..The PLU primary inputs 0. - * 0b000001..The PLU primary inputs 1. - * 0b000010..The PLU primary inputs 2. - * 0b000011..The PLU primary inputs 3. - * 0b000100..The PLU primary inputs 4. - * 0b000101..The PLU primary inputs 5. - * 0b000110..The output of LUT0. - * 0b000111..The output of LUT1. - * 0b001000..The output of LUT2. - * 0b001001..The output of LUT3. - * 0b001010..The output of LUT4. - * 0b001011..The output of LUT5. - * 0b001100..The output of LUT6. - * 0b001101..The output of LUT7. - * 0b001110..The output of LUT8. - * 0b001111..The output of LUT9. - * 0b010000..The output of LUT10. - * 0b010001..The output of LUT11. - * 0b010010..The output of LUT12. - * 0b010011..The output of LUT13. - * 0b010100..The output of LUT14. - * 0b010101..The output of LUT15. - * 0b010110..The output of LUT16. - * 0b010111..The output of LUT17. - * 0b011000..The output of LUT18. - * 0b011001..The output of LUT19. - * 0b011010..The output of LUT20. - * 0b011011..The output of LUT21. - * 0b011100..The output of LUT22. - * 0b011101..The output of LUT23. - * 0b011110..The output of LUT24. - * 0b011111..The output of LUT25. - * 0b100000..state(0). - * 0b100001..state(1). - * 0b100010..state(2). - * 0b100011..state(3). - */ -#define PLU_LUT_INP_MUX_LUTn_INPx(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_MUX_LUTn_INPx_SHIFT)) & PLU_LUT_INP_MUX_LUTn_INPx_MASK) -/*! @} */ - -/* The count of PLU_LUT_INP_MUX */ -#define PLU_LUT_INP_MUX_COUNT (26U) - -/* The count of PLU_LUT_INP_MUX */ -#define PLU_LUT_INP_MUX_COUNT2 (5U) - -/*! @name LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */ -/*! @{ */ - -#define PLU_LUT_TRUTH_LUTn_TRUTH_MASK (0xFFFFFFFFU) -#define PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT (0U) -/*! LUTn_TRUTH - Specifies the Truth Table contents for LUT25.. - */ -#define PLU_LUT_TRUTH_LUTn_TRUTH(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT)) & PLU_LUT_TRUTH_LUTn_TRUTH_MASK) -/*! @} */ - -/* The count of PLU_LUT_TRUTH */ -#define PLU_LUT_TRUTH_COUNT (26U) - -/*! @name OUTPUTS - Provides the current state of the 8 designated PLU Outputs. */ -/*! @{ */ - -#define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU) -#define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U) -/*! OUTPUT_STATE - Provides the current state of the 8 designated PLU Outputs.. - */ -#define PLU_OUTPUTS_OUTPUT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK) -/*! @} */ - -/*! @name WAKEINT_CTRL - Wakeup interrupt control for PLU */ -/*! @{ */ - -#define PLU_WAKEINT_CTRL_MASK_MASK (0xFFU) -#define PLU_WAKEINT_CTRL_MASK_SHIFT (0U) -/*! MASK - Interrupt mask (which of the 8 PLU Outputs contribute to interrupt) - */ -#define PLU_WAKEINT_CTRL_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_MASK_SHIFT)) & PLU_WAKEINT_CTRL_MASK_MASK) - -#define PLU_WAKEINT_CTRL_FILTER_MODE_MASK (0x300U) -#define PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT (8U) -/*! FILTER_MODE - control input of the PLU, add filtering for glitch. - * 0b00..Bypass mode. - * 0b01..Filter 1 clock period. - * 0b10..Filter 2 clock period. - * 0b11..Filter 3 clock period. - */ -#define PLU_WAKEINT_CTRL_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_MODE_MASK) - -#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK (0xC00U) -#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT (10U) -/*! FILTER_CLKSEL - hclk is divided by 2**filter_clksel. - * 0b00..Selects the 1 MHz low-power oscillator as the filter clock. - * 0b01..Selects the 12 Mhz FRO as the filter clock. - * 0b10..Selects a third filter clock source, if provided. - * 0b11..Reserved. - */ -#define PLU_WAKEINT_CTRL_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK) - -#define PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK (0x1000U) -#define PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT (12U) -/*! LATCH_ENABLE - latch the interrupt , then can be cleared with next bit INTR_CLEAR - */ -#define PLU_WAKEINT_CTRL_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK) - -#define PLU_WAKEINT_CTRL_INTR_CLEAR_MASK (0x2000U) -#define PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT (13U) -/*! INTR_CLEAR - Write to clear wakeint_latched - */ -#define PLU_WAKEINT_CTRL_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK) -/*! @} */ - -/*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7 */ -/*! @{ */ - -#define PLU_OUTPUT_MUX_OUTPUTn_MASK (0x1FU) -#define PLU_OUTPUT_MUX_OUTPUTn_SHIFT (0U) -/*! OUTPUTn - Selects the source to be connected to PLU Output 7. - * 0b00000..The PLU output 0. - * 0b00001..The PLU output 1. - * 0b00010..The PLU output 2. - * 0b00011..The PLU output 3. - * 0b00100..The PLU output 4. - * 0b00101..The PLU output 5. - * 0b00110..The PLU output 6. - * 0b00111..The PLU output 7. - * 0b01000..The PLU output 8. - * 0b01001..The PLU output 9. - * 0b01010..The PLU output 10. - * 0b01011..The PLU output 11. - * 0b01100..The PLU output 12. - * 0b01101..The PLU output 13. - * 0b01110..The PLU output 14. - * 0b01111..The PLU output 15. - * 0b10000..The PLU output 16. - * 0b10001..The PLU output 17. - * 0b10010..The PLU output 18. - * 0b10011..The PLU output 19. - * 0b10100..The PLU output 20. - * 0b10101..The PLU output 21. - * 0b10110..The PLU output 22. - * 0b10111..The PLU output 23. - * 0b11000..The PLU output 24. - * 0b11001..The PLU output 25. - * 0b11010..state(0). - * 0b11011..state(1). - * 0b11100..state(2). - * 0b11101..state(3). - */ -#define PLU_OUTPUT_MUX_OUTPUTn(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUTn_SHIFT)) & PLU_OUTPUT_MUX_OUTPUTn_MASK) -/*! @} */ - -/* The count of PLU_OUTPUT_MUX */ -#define PLU_OUTPUT_MUX_COUNT (8U) - - -/*! - * @} - */ /* end of group PLU_Register_Masks */ - - -/* PLU - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PLU base address */ - #define PLU_BASE (0x5003D000u) - /** Peripheral PLU base address */ - #define PLU_BASE_NS (0x4003D000u) - /** Peripheral PLU base pointer */ - #define PLU ((PLU_Type *)PLU_BASE) - /** Peripheral PLU base pointer */ - #define PLU_NS ((PLU_Type *)PLU_BASE_NS) - /** Array initializer of PLU peripheral base addresses */ - #define PLU_BASE_ADDRS { PLU_BASE } - /** Array initializer of PLU peripheral base pointers */ - #define PLU_BASE_PTRS { PLU } - /** Array initializer of PLU peripheral base addresses */ - #define PLU_BASE_ADDRS_NS { PLU_BASE_NS } - /** Array initializer of PLU peripheral base pointers */ - #define PLU_BASE_PTRS_NS { PLU_NS } -#else - /** Peripheral PLU base address */ - #define PLU_BASE (0x4003D000u) - /** Peripheral PLU base pointer */ - #define PLU ((PLU_Type *)PLU_BASE) - /** Array initializer of PLU peripheral base addresses */ - #define PLU_BASE_ADDRS { PLU_BASE } - /** Array initializer of PLU peripheral base pointers */ - #define PLU_BASE_PTRS { PLU } -#endif - -/*! - * @} - */ /* end of group PLU_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer - * @{ - */ - -/** PMC - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4]; - __I uint32_t STATUS; /**< Power Management Controller FSM (Finite State Machines) status, offset: 0x4 */ - __IO uint32_t RESETCTRL; /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x8 */ - uint8_t RESERVED_1[4]; - __IO uint32_t DCDC0; /**< DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x10 */ - __IO uint32_t DCDC1; /**< DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x14 */ - uint8_t RESERVED_2[4]; - __IO uint32_t LDOPMU; /**< Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x1C */ - uint8_t RESERVED_3[16]; - __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */ - uint8_t RESERVED_4[12]; - __IO uint32_t REFFASTWKUP; /**< Analog References fast wake-up Control register [Reset by: PoR], offset: 0x40 */ - uint8_t RESERVED_5[8]; - __IO uint32_t XTAL32K; /**< 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x4C */ - __IO uint32_t COMP; /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x50 */ - uint8_t RESERVED_6[16]; - __IO uint32_t WAKEUPIOCTRL; /**< Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset], offset: 0x64 */ - __IO uint32_t WAKEIOCAUSE; /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */ - uint8_t RESERVED_7[8]; - __IO uint32_t STATUSCLK; /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */ - uint8_t RESERVED_8[12]; - __IO uint32_t AOREG1; /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset], offset: 0x84 */ - uint8_t RESERVED_9[8]; - __IO uint32_t MISCCTRL; /**< Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x90 */ - uint8_t RESERVED_10[4]; - __IO uint32_t RTCOSC32K; /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x98 */ - __IO uint32_t OSTIMERr; /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C */ - uint8_t RESERVED_11[24]; - __IO uint32_t PDRUNCFG0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */ - uint8_t RESERVED_12[4]; - __O uint32_t PDRUNCFGSET0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */ - uint8_t RESERVED_13[4]; - __O uint32_t PDRUNCFGCLR0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */ - uint8_t RESERVED_14[8]; - __IO uint32_t SRAMCTRL; /**< All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xD4 */ -} PMC_Type; - -/* ---------------------------------------------------------------------------- - -- PMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Register_Masks PMC Register Masks - * @{ - */ - -/*! @name STATUS - Power Management Controller FSM (Finite State Machines) status */ -/*! @{ */ - -#define PMC_STATUS_FSMMAIN_MASK (0x7U) -#define PMC_STATUS_FSMMAIN_SHIFT (0U) -/*! FSMMAIN - Power Management Controller Main Finite State Machine (FSM) status. - * 0b000..POWER UP : The IC is powering up. - * 0b001..ACTIVE : Power up is completed. The IC is in normal functional operation mode. - * 0b010..POWER DOWN : the IC has entered POWER DOWN mode. - * 0b011..DEEP SLEEP: The IC has entered DEEP SLEEP mode. - * 0b110..DEEP POWER DOWN : The IC entred DEEP POWER DOWN mode. - * 0b111..IC Structural TEST Mode : The IC has entered in IC Test mode. - */ -#define PMC_STATUS_FSMMAIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMMAIN_SHIFT)) & PMC_STATUS_FSMMAIN_MASK) - -#define PMC_STATUS_FSMPWUP_MASK (0x78U) -#define PMC_STATUS_FSMPWUP_SHIFT (3U) -/*! FSMPWUP - POWER UP Finite State Machine (FSM) status. - */ -#define PMC_STATUS_FSMPWUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMPWUP_SHIFT)) & PMC_STATUS_FSMPWUP_MASK) - -#define PMC_STATUS_FSMDSLP_MASK (0x780U) -#define PMC_STATUS_FSMDSLP_SHIFT (7U) -/*! FSMDSLP - DEEP SLEEP Finite State Machine (FSM) status. - */ -#define PMC_STATUS_FSMDSLP(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMDSLP_SHIFT)) & PMC_STATUS_FSMDSLP_MASK) - -#define PMC_STATUS_FSMPWDN_MASK (0x7800U) -#define PMC_STATUS_FSMPWDN_SHIFT (11U) -/*! FSMPWDN - POWER DOWN Finite State Machine (FSM) status. - */ -#define PMC_STATUS_FSMPWDN(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMPWDN_SHIFT)) & PMC_STATUS_FSMPWDN_MASK) - -#define PMC_STATUS_FSMDPWD_MASK (0x38000U) -#define PMC_STATUS_FSMDPWD_SHIFT (15U) -/*! FSMDPWD - DEEP POWER DOWN Finite State Machine (FSM) status. - */ -#define PMC_STATUS_FSMDPWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMDPWD_SHIFT)) & PMC_STATUS_FSMDPWD_MASK) - -#define PMC_STATUS_BOOTMODE_MASK (0xC0000U) -#define PMC_STATUS_BOOTMODE_SHIFT (18U) -/*! BOOTMODE - Latest IC Boot cause:. - * 0b00..Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset). - * 0b01..Latest IC boot was from DEEP SLEEP low power mode.. - * 0b10..Latest IC boot was from POWER DOWN low power mode.. - * 0b11..Latest IC boot was from DEEP POWER DOWN low power mode.. - */ -#define PMC_STATUS_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_BOOTMODE_SHIFT)) & PMC_STATUS_BOOTMODE_MASK) - -#define PMC_STATUS_WAFERTESTDONEVECT_MASK (0xF0000000U) -#define PMC_STATUS_WAFERTESTDONEVECT_SHIFT (28U) -/*! WAFERTESTDONEVECT - Indicates cuurent status of wafer test level. - */ -#define PMC_STATUS_WAFERTESTDONEVECT(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_WAFERTESTDONEVECT_SHIFT)) & PMC_STATUS_WAFERTESTDONEVECT_MASK) -/*! @} */ - -/*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U) -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U) -/*! DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). - * 0b0..Reset event from DEEP POWER DOWN mode is disable. - * 0b1..Reset event from DEEP POWER DOWN mode is enable. - */ -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK) - -#define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U) -#define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U) -/*! SWRRESETENABLE - Software reset enable. - * 0b0..Software reset is disable. - * 0b1..Software reset is enable. - */ -#define PMC_RESETCTRL_SWRRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK) - -#define PMC_RESETCTRL_BODVBATRESETENA_SECURE_MASK (0x30U) -#define PMC_RESETCTRL_BODVBATRESETENA_SECURE_SHIFT (4U) -/*! BODVBATRESETENA_SECURE - BOD VBAT reset enable. - * 0b10..BOD VBAT reset is disable. - * 0b01..Any other value than b10, BOD VBAT reset is enable. - */ -#define PMC_RESETCTRL_BODVBATRESETENA_SECURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENA_SECURE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENA_SECURE_MASK) - -#define PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK (0xC0U) -#define PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT (6U) -/*! BODCORERESETENA_SECURE - BOD Core reset enable. - * 0b10..BOD Core reset is disable. - * 0b01..Any other value than b10, BOD Core reset is enable. - */ -#define PMC_RESETCTRL_BODCORERESETENA_SECURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT)) & PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK) - -#define PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_MASK (0x30000000U) -#define PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_SHIFT (28U) -/*! BODVBATRESETENA_SECURE_DP - BOD VBAT reset enable. - * 0b10..BOD VBAT reset is disable. - * 0b01..Any other value than b10, BOD VBAT reset is enable. - */ -#define PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_MASK) - -#define PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK (0xC0000000U) -#define PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT (30U) -/*! BODCORERESETENA_SECURE_DP - BOD Core reset enable. - * 0b10..BOD Core reset is disable. - * 0b01..Any other value than b10, BOD Core reset is enable. - */ -#define PMC_RESETCTRL_BODCORERESETENA_SECURE_DP(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT)) & PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK) -/*! @} */ - -/*! @name DCDC0 - DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_DCDC0_RC_MASK (0x3FU) -#define PMC_DCDC0_RC_SHIFT (0U) -/*! RC - Constant On-Time calibration. - */ -#define PMC_DCDC0_RC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_RC_SHIFT)) & PMC_DCDC0_RC_MASK) - -#define PMC_DCDC0_ICOMP_MASK (0xC0U) -#define PMC_DCDC0_ICOMP_SHIFT (6U) -/*! ICOMP - Select the type of ZCD comparator. - */ -#define PMC_DCDC0_ICOMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICOMP_SHIFT)) & PMC_DCDC0_ICOMP_MASK) - -#define PMC_DCDC0_ISEL_MASK (0x300U) -#define PMC_DCDC0_ISEL_SHIFT (8U) -/*! ISEL - Alter Internal biasing currents. - */ -#define PMC_DCDC0_ISEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ISEL_SHIFT)) & PMC_DCDC0_ISEL_MASK) - -#define PMC_DCDC0_ICENABLE_MASK (0x400U) -#define PMC_DCDC0_ICENABLE_SHIFT (10U) -/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD. - */ -#define PMC_DCDC0_ICENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICENABLE_SHIFT)) & PMC_DCDC0_ICENABLE_MASK) - -#define PMC_DCDC0_TMOS_MASK (0xF800U) -#define PMC_DCDC0_TMOS_SHIFT (11U) -/*! TMOS - One-shot generator reference current trimming signal. - */ -#define PMC_DCDC0_TMOS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_TMOS_SHIFT)) & PMC_DCDC0_TMOS_MASK) - -#define PMC_DCDC0_DISABLEISENSE_MASK (0x10000U) -#define PMC_DCDC0_DISABLEISENSE_SHIFT (16U) -/*! DISABLEISENSE - Disable Current sensing. - */ -#define PMC_DCDC0_DISABLEISENSE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_DISABLEISENSE_SHIFT)) & PMC_DCDC0_DISABLEISENSE_MASK) - -#define PMC_DCDC0_VOUT_MASK (0x1E0000U) -#define PMC_DCDC0_VOUT_SHIFT (17U) -/*! VOUT - Set output regulation voltage. - * 0b0000..0.95 V. - * 0b0001..0.975 V. - * 0b0010..1 V. - * 0b0011..1.025 V. - * 0b0100..1.05 V. - * 0b0101..1.075 V. - * 0b0110..1.1 V. - * 0b0111..1.125 V. - * 0b1000..1.15 V. - * 0b1001..1.175 V. - * 0b1010..1.2 V. - */ -#define PMC_DCDC0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_SHIFT)) & PMC_DCDC0_VOUT_MASK) - -#define PMC_DCDC0_SLICINGENABLE_MASK (0x200000U) -#define PMC_DCDC0_SLICINGENABLE_SHIFT (21U) -/*! SLICINGENABLE - Enable staggered switching of power switches. - */ -#define PMC_DCDC0_SLICINGENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_SLICINGENABLE_SHIFT)) & PMC_DCDC0_SLICINGENABLE_MASK) - -#define PMC_DCDC0_INDUCTORCLAMPENABLE_MASK (0x400000U) -#define PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT (22U) -/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. - */ -#define PMC_DCDC0_INDUCTORCLAMPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT)) & PMC_DCDC0_INDUCTORCLAMPENABLE_MASK) - -#define PMC_DCDC0_VOUT_PWD_MASK (0x7800000U) -#define PMC_DCDC0_VOUT_PWD_SHIFT (23U) -/*! VOUT_PWD - Set output regulation voltage during Deep Sleep. - */ -#define PMC_DCDC0_VOUT_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_PWD_SHIFT)) & PMC_DCDC0_VOUT_PWD_MASK) -/*! @} */ - -/*! @name DCDC1 - DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_DCDC1_RTRIMOFFET_MASK (0xFU) -#define PMC_DCDC1_RTRIMOFFET_SHIFT (0U) -/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator. - */ -#define PMC_DCDC1_RTRIMOFFET(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RTRIMOFFET_SHIFT)) & PMC_DCDC1_RTRIMOFFET_MASK) - -#define PMC_DCDC1_RSENSETRIM_MASK (0xF0U) -#define PMC_DCDC1_RSENSETRIM_SHIFT (4U) -/*! RSENSETRIM - Adjust Max inductor peak current limiting. - */ -#define PMC_DCDC1_RSENSETRIM(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RSENSETRIM_SHIFT)) & PMC_DCDC1_RSENSETRIM_MASK) - -#define PMC_DCDC1_DTESTENABLE_MASK (0x100U) -#define PMC_DCDC1_DTESTENABLE_SHIFT (8U) -/*! DTESTENABLE - Enable Digital test signals. - */ -#define PMC_DCDC1_DTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTENABLE_SHIFT)) & PMC_DCDC1_DTESTENABLE_MASK) - -#define PMC_DCDC1_SETCURVE_MASK (0x600U) -#define PMC_DCDC1_SETCURVE_SHIFT (9U) -/*! SETCURVE - Bandgap calibration parameter. - */ -#define PMC_DCDC1_SETCURVE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETCURVE_SHIFT)) & PMC_DCDC1_SETCURVE_MASK) - -#define PMC_DCDC1_SETDC_MASK (0x7800U) -#define PMC_DCDC1_SETDC_SHIFT (11U) -/*! SETDC - Bandgap calibration parameter. - */ -#define PMC_DCDC1_SETDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETDC_SHIFT)) & PMC_DCDC1_SETDC_MASK) - -#define PMC_DCDC1_DTESTSEL_MASK (0x38000U) -#define PMC_DCDC1_DTESTSEL_SHIFT (15U) -/*! DTESTSEL - Select the output signal for test. - */ -#define PMC_DCDC1_DTESTSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTSEL_SHIFT)) & PMC_DCDC1_DTESTSEL_MASK) - -#define PMC_DCDC1_ISCALEENABLE_MASK (0x40000U) -#define PMC_DCDC1_ISCALEENABLE_SHIFT (18U) -/*! ISCALEENABLE - Modify COT behavior. - */ -#define PMC_DCDC1_ISCALEENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_ISCALEENABLE_SHIFT)) & PMC_DCDC1_ISCALEENABLE_MASK) - -#define PMC_DCDC1_FORCEBYPASS_MASK (0x80000U) -#define PMC_DCDC1_FORCEBYPASS_SHIFT (19U) -/*! FORCEBYPASS - Force bypass mode. - */ -#define PMC_DCDC1_FORCEBYPASS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEBYPASS_SHIFT)) & PMC_DCDC1_FORCEBYPASS_MASK) - -#define PMC_DCDC1_TRIMAUTOCOT_MASK (0xF00000U) -#define PMC_DCDC1_TRIMAUTOCOT_SHIFT (20U) -/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. - */ -#define PMC_DCDC1_TRIMAUTOCOT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TRIMAUTOCOT_SHIFT)) & PMC_DCDC1_TRIMAUTOCOT_MASK) - -#define PMC_DCDC1_FORCEFULLCYCLE_MASK (0x1000000U) -#define PMC_DCDC1_FORCEFULLCYCLE_SHIFT (24U) -/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. - */ -#define PMC_DCDC1_FORCEFULLCYCLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEFULLCYCLE_SHIFT)) & PMC_DCDC1_FORCEFULLCYCLE_MASK) - -#define PMC_DCDC1_LCENABLE_MASK (0x2000000U) -#define PMC_DCDC1_LCENABLE_SHIFT (25U) -/*! LCENABLE - Change the range of the peak detector of current inside the inductor. - */ -#define PMC_DCDC1_LCENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_LCENABLE_SHIFT)) & PMC_DCDC1_LCENABLE_MASK) - -#define PMC_DCDC1_TOFF_MASK (0x7C000000U) -#define PMC_DCDC1_TOFF_SHIFT (26U) -/*! TOFF - Constant Off-Time calibration input. - */ -#define PMC_DCDC1_TOFF(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFF_SHIFT)) & PMC_DCDC1_TOFF_MASK) - -#define PMC_DCDC1_TOFFENABLE_MASK (0x80000000U) -#define PMC_DCDC1_TOFFENABLE_SHIFT (31U) -/*! TOFFENABLE - Enable Constant Off-Time feature. - */ -#define PMC_DCDC1_TOFFENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFFENABLE_SHIFT)) & PMC_DCDC1_TOFFENABLE_MASK) -/*! @} */ - -/*! @name LDOPMU - Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_LDOPMU_VADJ_MASK (0x1FU) -#define PMC_LDOPMU_VADJ_SHIFT (0U) -/*! VADJ - Sets the Always-On domain LDO output level. - * 0b00000..1.22 V. - * 0b00001..0.7 V. - * 0b00010..0.725 V. - * 0b00011..0.75 V. - * 0b00100..0.775 V. - * 0b00101..0.8 V. - * 0b00110..0.825 V. - * 0b00111..0.85 V. - * 0b01000..0.875 V. - * 0b01001..0.9 V. - * 0b01010..0.96 V. - * 0b01011..0.97 V. - * 0b01100..0.98 V. - * 0b01101..0.99 V. - * 0b01110..1 V. - * 0b01111..1.01 V. - * 0b10000..1.02 V. - * 0b10001..1.03 V. - * 0b10010..1.04 V. - * 0b10011..1.05 V. - * 0b10100..1.06 V. - * 0b10101..1.07 V. - * 0b10110..1.08 V. - * 0b10111..1.09 V. - * 0b11000..1.1 V. - * 0b11001..1.11 V. - * 0b11010..1.12 V. - * 0b11011..1.13 V. - * 0b11100..1.14 V. - * 0b11101..1.15 V. - * 0b11110..1.16 V. - * 0b11111..1.22 V. - */ -#define PMC_LDOPMU_VADJ(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_SHIFT)) & PMC_LDOPMU_VADJ_MASK) - -#define PMC_LDOPMU_VADJ_PWD_MASK (0x3E0U) -#define PMC_LDOPMU_VADJ_PWD_SHIFT (5U) -/*! VADJ_PWD - Sets the Always-On domain LDO output level in all power down modes. - */ -#define PMC_LDOPMU_VADJ_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_PWD_SHIFT)) & PMC_LDOPMU_VADJ_PWD_MASK) - -#define PMC_LDOPMU_VADJ_BOOST_MASK (0x7C00U) -#define PMC_LDOPMU_VADJ_BOOST_SHIFT (10U) -/*! VADJ_BOOST - Sets the Always-On domain LDO Boost output level. - */ -#define PMC_LDOPMU_VADJ_BOOST(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_MASK) - -#define PMC_LDOPMU_VADJ_BOOST_PWD_MASK (0xF8000U) -#define PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT (15U) -/*! VADJ_BOOST_PWD - Sets the Always-On domain LDO Boost output level in all power down modes. - */ -#define PMC_LDOPMU_VADJ_BOOST_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_PWD_MASK) - -#define PMC_LDOPMU_BLEED_MASK (0x100000U) -#define PMC_LDOPMU_BLEED_SHIFT (20U) -/*! BLEED - Controls LDOMEM bleed current. - * 0b0..Bleed current is disable. - * 0b1..Bleed current is enable. - */ -#define PMC_LDOPMU_BLEED(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BLEED_SHIFT)) & PMC_LDOPMU_BLEED_MASK) - -#define PMC_LDOPMU_BOOST_ENA_MASK (0x1000000U) -#define PMC_LDOPMU_BOOST_ENA_SHIFT (24U) -/*! BOOST_ENA - Control the LDO AO boost mode in ACTIVE mode. - * 0b0..LDO AO Boost Mode is disable. - * 0b1..LDO AO Boost Mode is enable. - */ -#define PMC_LDOPMU_BOOST_ENA(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_SHIFT)) & PMC_LDOPMU_BOOST_ENA_MASK) - -#define PMC_LDOPMU_BOOST_ENA_PWD_MASK (0x2000000U) -#define PMC_LDOPMU_BOOST_ENA_PWD_SHIFT (25U) -/*! BOOST_ENA_PWD - Control the LDO AO boost mode in the different low power modes (DEEP SLEEP, POWERDOWN, and DEEP POWER DOWN). - * 0b0..LDO AO Boost Mode is disable. - * 0b1..LDO AO Boost Mode is enable. - */ -#define PMC_LDOPMU_BOOST_ENA_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_PWD_SHIFT)) & PMC_LDOPMU_BOOST_ENA_PWD_MASK) -/*! @} */ - -/*! @name BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] */ -/*! @{ */ - -#define PMC_BODVBAT_TRIGLVL_MASK (0x1FU) -#define PMC_BODVBAT_TRIGLVL_SHIFT (0U) -/*! TRIGLVL - BoD trigger level. - * 0b00000..1.00 V. - * 0b00001..1.10 V. - * 0b00010..1.20 V. - * 0b00011..1.30 V. - * 0b00100..1.40 V. - * 0b00101..1.50 V. - * 0b00110..1.60 V. - * 0b00111..1.65 V. - * 0b01000..1.70 V. - * 0b01001..1.75 V. - * 0b01010..1.80 V. - * 0b01011..1.90 V. - * 0b01100..2.00 V. - * 0b01101..2.10 V. - * 0b01110..2.20 V. - * 0b01111..2.30 V. - * 0b10000..2.40 V. - * 0b10001..2.50 V. - * 0b10010..2.60 V. - * 0b10011..2.70 V. - * 0b10100..2.806 V. - * 0b10101..2.90 V. - * 0b10110..3.00 V. - * 0b10111..3.10 V. - * 0b11000..3.20 V. - * 0b11001..3.30 V. - * 0b11010..3.30 V. - * 0b11011..3.30 V. - * 0b11100..3.30 V. - * 0b11101..3.30 V. - * 0b11110..3.30 V. - * 0b11111..3.30 V. - */ -#define PMC_BODVBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_TRIGLVL_SHIFT)) & PMC_BODVBAT_TRIGLVL_MASK) - -#define PMC_BODVBAT_HYST_MASK (0x60U) -#define PMC_BODVBAT_HYST_SHIFT (5U) -/*! HYST - BoD Hysteresis control. - * 0b00..25 mV. - * 0b01..50 mV. - * 0b10..75 mV. - * 0b11..100 mV. - */ -#define PMC_BODVBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK) -/*! @} */ - -/*! @name REFFASTWKUP - Analog References fast wake-up Control register [Reset by: PoR] */ -/*! @{ */ - -#define PMC_REFFASTWKUP_LPWKUP_MASK (0x1U) -#define PMC_REFFASTWKUP_LPWKUP_SHIFT (0U) -/*! LPWKUP - Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP POWER DOWN): . - * 0b0..Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode. - * 0b1..Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode. - */ -#define PMC_REFFASTWKUP_LPWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_LPWKUP_SHIFT)) & PMC_REFFASTWKUP_LPWKUP_MASK) - -#define PMC_REFFASTWKUP_HWWKUP_MASK (0x2U) -#define PMC_REFFASTWKUP_HWWKUP_SHIFT (1U) -/*! HWWKUP - Analog References fast wake-up in case of Hardware Pin reset: . - * 0b0..Analog References fast wake-up feature is disabled in case of Hardware Pin reset. - * 0b1..Analog References fast wake-up feature is enabled in case of Hardware Pin reset. - */ -#define PMC_REFFASTWKUP_HWWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_HWWKUP_SHIFT)) & PMC_REFFASTWKUP_HWWKUP_MASK) -/*! @} */ - -/*! @name XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_XTAL32K_IREF_MASK (0x6U) -#define PMC_XTAL32K_IREF_SHIFT (1U) -/*! IREF - reference output current selection inputs. - */ -#define PMC_XTAL32K_IREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IREF_SHIFT)) & PMC_XTAL32K_IREF_MASK) - -#define PMC_XTAL32K_TEST_MASK (0x8U) -#define PMC_XTAL32K_TEST_SHIFT (3U) -/*! TEST - Oscillator Test Mode. - */ -#define PMC_XTAL32K_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK) - -#define PMC_XTAL32K_IBIAS_MASK (0x30U) -#define PMC_XTAL32K_IBIAS_SHIFT (4U) -/*! IBIAS - bias current selection inputs. - */ -#define PMC_XTAL32K_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IBIAS_SHIFT)) & PMC_XTAL32K_IBIAS_MASK) - -#define PMC_XTAL32K_AMPL_MASK (0xC0U) -#define PMC_XTAL32K_AMPL_SHIFT (6U) -/*! AMPL - oscillator amplitude selection inputs. - */ -#define PMC_XTAL32K_AMPL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_AMPL_SHIFT)) & PMC_XTAL32K_AMPL_MASK) - -#define PMC_XTAL32K_CAPBANKIN_MASK (0x7F00U) -#define PMC_XTAL32K_CAPBANKIN_SHIFT (8U) -/*! CAPBANKIN - Capa bank setting input. - */ -#define PMC_XTAL32K_CAPBANKIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKIN_SHIFT)) & PMC_XTAL32K_CAPBANKIN_MASK) - -#define PMC_XTAL32K_CAPBANKOUT_MASK (0x3F8000U) -#define PMC_XTAL32K_CAPBANKOUT_SHIFT (15U) -/*! CAPBANKOUT - Capa bank setting output. - */ -#define PMC_XTAL32K_CAPBANKOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKOUT_SHIFT)) & PMC_XTAL32K_CAPBANKOUT_MASK) - -#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK (0x400000U) -#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT (22U) -/*! CAPTESTSTARTSRCSEL - Source selection for xo32k_captest_start_ao_set. - * 0b0..Sourced from CAPTESTSTART. - * 0b1..Sourced from calibration. - */ -#define PMC_XTAL32K_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT)) & PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK) - -#define PMC_XTAL32K_CAPTESTSTART_MASK (0x800000U) -#define PMC_XTAL32K_CAPTESTSTART_SHIFT (23U) -/*! CAPTESTSTART - Start test. - */ -#define PMC_XTAL32K_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTART_SHIFT)) & PMC_XTAL32K_CAPTESTSTART_MASK) - -#define PMC_XTAL32K_CAPTESTENABLE_MASK (0x1000000U) -#define PMC_XTAL32K_CAPTESTENABLE_SHIFT (24U) -/*! CAPTESTENABLE - Enable signal for cap test. - */ -#define PMC_XTAL32K_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTENABLE_SHIFT)) & PMC_XTAL32K_CAPTESTENABLE_MASK) - -#define PMC_XTAL32K_CAPTESTOSCINSEL_MASK (0x2000000U) -#define PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT (25U) -/*! CAPTESTOSCINSEL - Select the input for test. - * 0b0..Oscillator output pin (osc_out). - * 0b1..Oscillator input pin (osc_in). - */ -#define PMC_XTAL32K_CAPTESTOSCINSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT)) & PMC_XTAL32K_CAPTESTOSCINSEL_MASK) -/*! @} */ - -/*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_COMP_HYST_MASK (0x2U) -#define PMC_COMP_HYST_SHIFT (1U) -/*! HYST - Hysteris when hyst = '1'. - * 0b0..Hysteresis is disable. - * 0b1..Hysteresis is enable. - */ -#define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK) - -#define PMC_COMP_VREFINPUT_MASK (0x4U) -#define PMC_COMP_VREFINPUT_SHIFT (2U) -/*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). - * 0b0..Select internal VREF. - * 0b1..Select VDDA. - */ -#define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK) - -#define PMC_COMP_LOWPOWER_MASK (0x8U) -#define PMC_COMP_LOWPOWER_SHIFT (3U) -/*! LOWPOWER - Low power mode. - * 0b0..High speed mode. - * 0b1..Low power mode (Low speed). - */ -#define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK) - -#define PMC_COMP_PMUX_MASK (0x70U) -#define PMC_COMP_PMUX_SHIFT (4U) -/*! PMUX - Control word for P multiplexer:. - * 0b000..VREF (See fiedl VREFINPUT). - * 0b001..Pin P0_0. - * 0b010..Pin P0_9. - * 0b011..Pin P0_18. - * 0b100..Pin P1_14. - * 0b101..Pin P2_23. - */ -#define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK) - -#define PMC_COMP_NMUX_MASK (0x380U) -#define PMC_COMP_NMUX_SHIFT (7U) -/*! NMUX - Control word for N multiplexer:. - * 0b000..VREF (See field VREFINPUT). - * 0b001..Pin P0_0. - * 0b010..Pin P0_9. - * 0b011..Pin P0_18. - * 0b100..Pin P1_14. - * 0b101..Pin P2_23. - */ -#define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK) - -#define PMC_COMP_VREF_MASK (0x7C00U) -#define PMC_COMP_VREF_SHIFT (10U) -/*! VREF - Control reference voltage step, per steps of (VREFINPUT/31). - */ -#define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK) - -#define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U) -#define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U) -/*! FILTERCGF_SAMPLEMODE - Control the filtering of the Analog Comparator output. - * 0b00..Bypass mode. - * 0b01..Filter 1 clock period. - * 0b10..Filter 2 clock period. - * 0b11..Filter 3 clock period. - */ -#define PMC_COMP_FILTERCGF_SAMPLEMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK) - -#define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U) -#define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U) -/*! FILTERCGF_CLKDIV - Filter Clock divider. - * 0b000..Filter clock period duration equals 1 Analog Comparator clock period. - * 0b001..Filter clock period duration equals 2 Analog Comparator clock period. - * 0b010..Filter clock period duration equals 4 Analog Comparator clock period. - * 0b011..Filter clock period duration equals 8 Analog Comparator clock period. - * 0b100..Filter clock period duration equals 16 Analog Comparator clock period. - * 0b101..Filter clock period duration equals 32 Analog Comparator clock period. - * 0b110..Filter clock period duration equals 64 Analog Comparator clock period. - * 0b111..Filter clock period duration equals 128 Analog Comparator clock period. - */ -#define PMC_COMP_FILTERCGF_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK) -/*! @} */ - -/*! @name WAKEUPIOCTRL - Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] */ -/*! @{ */ - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK (0x1U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT (0U) -/*! RISINGEDGEWAKEUP0 - Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disable. - * 0b1..Rising edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK (0x2U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT (1U) -/*! FALLINGEDGEWAKEUP0 - Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disable. - * 0b1..Falling edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK) - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK (0x4U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT (2U) -/*! RISINGEDGEWAKEUP1 - Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disable. - * 0b1..Rising edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK (0x8U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT (3U) -/*! FALLINGEDGEWAKEUP1 - Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disable. - * 0b1..Falling edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK) - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK (0x10U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT (4U) -/*! RISINGEDGEWAKEUP2 - Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disable. - * 0b1..Rising edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK (0x20U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT (5U) -/*! FALLINGEDGEWAKEUP2 - Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disable. - * 0b1..Falling edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK) - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK (0x40U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT (6U) -/*! RISINGEDGEWAKEUP3 - Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disable. - * 0b1..Rising edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK (0x80U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT (7U) -/*! FALLINGEDGEWAKEUP3 - Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disable. - * 0b1..Falling edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_MASK (0x3000U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_SHIFT (12U) -/*! MODEWAKEUPIOPAD0 - Selects function mode (on-chip pull-up/pull-down resistor control). - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_MASK (0xC000U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_SHIFT (14U) -/*! MODEWAKEUPIOPAD1 - Selects function mode (on-chip pull-up/pull-down resistor control). - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_MASK (0x30000U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_SHIFT (16U) -/*! MODEWAKEUPIOPAD2 - Selects function mode (on-chip pull-up/pull-down resistor control). - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_MASK (0xC0000U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_SHIFT (18U) -/*! MODEWAKEUPIOPAD3 - Selects function mode (on-chip pull-up/pull-down resistor control). - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_MASK) - -#define PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK (0x100000U) -#define PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_SHIFT (20U) -/*! WAKEUPIO_ENABLE_CTRL - Enable WAKEUP IO PAD control from MODEWAKEUPIOPAD (bits 12 to 19). - * 0b0..WAKEUP IO PAD mode control comes from IOCON. - * 0b1..WAKEUP IO PAD mode control comes from MODEWAKEUPIOPAD (bits 12 to 19). - */ -#define PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_SHIFT)) & PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK) - -#define PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_MASK (0x200000U) -#define PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_SHIFT (21U) -/*! WAKEUPIO_RSTN - WAKEUP IO event detector reset control. - * 0b0..Bloc is reset. - * 0b1..Bloc is not reset. - */ -#define PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_SHIFT)) & PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_MASK) -/*! @} */ - -/*! @name WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode */ -/*! @{ */ - -#define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U) -#define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U) -/*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0. - */ -#define PMC_WAKEIOCAUSE_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK) - -#define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U) -#define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U) -/*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1. - */ -#define PMC_WAKEIOCAUSE_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK) - -#define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U) -#define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U) -/*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2. - */ -#define PMC_WAKEIOCAUSE_WAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK) - -#define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U) -#define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U) -/*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 3. - */ -#define PMC_WAKEIOCAUSE_WAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK) -/*! @} */ - -/*! @name STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U) -#define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U) -/*! XTAL32KOK - XTAL oscillator 32 K OK signal. - */ -#define PMC_STATUSCLK_XTAL32KOK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK) - -#define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U) -#define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U) -/*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. - * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared. - * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared. - */ -#define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK) -/*! @} */ - -/*! @name AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_AOREG1_POR_MASK (0x10U) -#define PMC_AOREG1_POR_SHIFT (4U) -/*! POR - The last chip reset was caused by a Power On Reset. - */ -#define PMC_AOREG1_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_POR_SHIFT)) & PMC_AOREG1_POR_MASK) - -#define PMC_AOREG1_PADRESET_MASK (0x20U) -#define PMC_AOREG1_PADRESET_SHIFT (5U) -/*! PADRESET - The last chip reset was caused by a Pin Reset. - */ -#define PMC_AOREG1_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_PADRESET_SHIFT)) & PMC_AOREG1_PADRESET_MASK) - -#define PMC_AOREG1_BODRESET_MASK (0x40U) -#define PMC_AOREG1_BODRESET_SHIFT (6U) -/*! BODRESET - The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. - */ -#define PMC_AOREG1_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BODRESET_SHIFT)) & PMC_AOREG1_BODRESET_MASK) - -#define PMC_AOREG1_SYSTEMRESET_MASK (0x80U) -#define PMC_AOREG1_SYSTEMRESET_SHIFT (7U) -/*! SYSTEMRESET - The last chip reset was caused by a System Reset requested by the ARM CPU. - */ -#define PMC_AOREG1_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SYSTEMRESET_SHIFT)) & PMC_AOREG1_SYSTEMRESET_MASK) - -#define PMC_AOREG1_WDTRESET_MASK (0x100U) -#define PMC_AOREG1_WDTRESET_SHIFT (8U) -/*! WDTRESET - The last chip reset was caused by the Watchdog Timer. - */ -#define PMC_AOREG1_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_WDTRESET_SHIFT)) & PMC_AOREG1_WDTRESET_MASK) - -#define PMC_AOREG1_SWRRESET_MASK (0x200U) -#define PMC_AOREG1_SWRRESET_SHIFT (9U) -/*! SWRRESET - The last chip reset was caused by a Software event. - */ -#define PMC_AOREG1_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SWRRESET_SHIFT)) & PMC_AOREG1_SWRRESET_MASK) - -#define PMC_AOREG1_DPDRESET_WAKEUPIO_MASK (0x400U) -#define PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT (10U) -/*! DPDRESET_WAKEUPIO - The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode. - */ -#define PMC_AOREG1_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT)) & PMC_AOREG1_DPDRESET_WAKEUPIO_MASK) - -#define PMC_AOREG1_DPDRESET_RTC_MASK (0x800U) -#define PMC_AOREG1_DPDRESET_RTC_SHIFT (11U) -/*! DPDRESET_RTC - The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode. - */ -#define PMC_AOREG1_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_RTC_SHIFT)) & PMC_AOREG1_DPDRESET_RTC_MASK) - -#define PMC_AOREG1_DPDRESET_OSTIMER_MASK (0x1000U) -#define PMC_AOREG1_DPDRESET_OSTIMER_SHIFT (12U) -/*! DPDRESET_OSTIMER - The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode. - */ -#define PMC_AOREG1_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_OSTIMER_SHIFT)) & PMC_AOREG1_DPDRESET_OSTIMER_MASK) - -#define PMC_AOREG1_CDOGRESET_MASK (0x2000U) -#define PMC_AOREG1_CDOGRESET_SHIFT (13U) -/*! CDOGRESET - The last chip reset was caused by the code Watchdog. - */ -#define PMC_AOREG1_CDOGRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_CDOGRESET_SHIFT)) & PMC_AOREG1_CDOGRESET_MASK) - -#define PMC_AOREG1_BOOTERRORCOUNTER_MASK (0xF0000U) -#define PMC_AOREG1_BOOTERRORCOUNTER_SHIFT (16U) -/*! BOOTERRORCOUNTER - ROM Boot Fatal Error Counter. - */ -#define PMC_AOREG1_BOOTERRORCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BOOTERRORCOUNTER_SHIFT)) & PMC_AOREG1_BOOTERRORCOUNTER_MASK) -/*! @} */ - -/*! @name MISCCTRL - Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_MISCCTRL_LDODEEPSLEEPREF_MASK (0x1U) -#define PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT (0U) -/*! LDODEEPSLEEPREF - Select LDO Deep Sleep reference source. - * 0b0..LDO DEEP Sleep uses Flash buffer biasing as reference. - * 0b1..LDO DEEP Sleep uses Band Gap 0.8V as reference. - */ -#define PMC_MISCCTRL_LDODEEPSLEEPREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT)) & PMC_MISCCTRL_LDODEEPSLEEPREF_MASK) - -#define PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK (0x2U) -#define PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT (1U) -/*! LDOMEMHIGHZMODE - Control the activation of LDO MEM High Z mode. - * 0b0..LDO MEM High Z mode is disabled. - * 0b1..LDO MEM High Z mode is enabled. - */ -#define PMC_MISCCTRL_LDOMEMHIGHZMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT)) & PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK) - -#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK (0x4U) -#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT (2U) -#define PMC_MISCCTRL_LOWPWR_FLASH_BUF(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT)) & PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK) - -#define PMC_MISCCTRL_MISCCTRL_3_11_MASK (0xFF8U) -#define PMC_MISCCTRL_MISCCTRL_3_11_SHIFT (3U) -/*! MISCCTRL_3_11 - Reserved. - */ -#define PMC_MISCCTRL_MISCCTRL_3_11(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_3_11_SHIFT)) & PMC_MISCCTRL_MISCCTRL_3_11_MASK) - -#define PMC_MISCCTRL_DISABLE_BLEED_MASK (0x1000U) -#define PMC_MISCCTRL_DISABLE_BLEED_SHIFT (12U) -/*! DISABLE_BLEED - Controls LDO MEM bleed current. This field is expected to be controlled by the - * Low Power Software only in DEEP SLEEP low power mode. - * 0b0..LDO_MEM bleed current is enabled. - * 0b1..LDO_MEM bleed current is disabled. Should be set before entering in Deep Sleep low power mode and cleared - * after wake up from Deep SLeep low power mode. - */ -#define PMC_MISCCTRL_DISABLE_BLEED(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_DISABLE_BLEED_SHIFT)) & PMC_MISCCTRL_DISABLE_BLEED_MASK) - -#define PMC_MISCCTRL_MISCCTRL_13_15_MASK (0xE000U) -#define PMC_MISCCTRL_MISCCTRL_13_15_SHIFT (13U) -/*! MISCCTRL_13_15 - Reserved. - */ -#define PMC_MISCCTRL_MISCCTRL_13_15(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_13_15_SHIFT)) & PMC_MISCCTRL_MISCCTRL_13_15_MASK) -/*! @} */ - -/*! @name RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_RTCOSC32K_SEL_MASK (0x1U) -#define PMC_RTCOSC32K_SEL_SHIFT (0U) -/*! SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . - * 0b0..FRO 32 KHz. - * 0b1..XTAL 32KHz. - */ -#define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK) - -#define PMC_RTCOSC32K_CLK1KHZDIV_MASK (0xEU) -#define PMC_RTCOSC32K_CLK1KHZDIV_SHIFT (1U) -/*! CLK1KHZDIV - Actual division ratio is : 28 + CLK1KHZDIV. - */ -#define PMC_RTCOSC32K_CLK1KHZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIV_MASK) - -#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK (0x8000U) -#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT (15U) -/*! CLK1KHZDIVUPDATEREQ - RTC 1KHz clock Divider status flag. - */ -#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK) - -#define PMC_RTCOSC32K_CLK1HZDIV_MASK (0x7FF0000U) -#define PMC_RTCOSC32K_CLK1HZDIV_SHIFT (16U) -/*! CLK1HZDIV - Actual division ratio is : 31744 + CLK1HZDIV. - */ -#define PMC_RTCOSC32K_CLK1HZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIV_MASK) - -#define PMC_RTCOSC32K_CLK1HZDIVHALT_MASK (0x40000000U) -#define PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT (30U) -/*! CLK1HZDIVHALT - Halts the divider counter. - */ -#define PMC_RTCOSC32K_CLK1HZDIVHALT(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVHALT_MASK) - -#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK (0x80000000U) -#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT (31U) -/*! CLK1HZDIVUPDATEREQ - RTC 1Hz Divider status flag. - */ -#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK) -/*! @} */ - -/*! @name OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_OSTIMER_SOFTRESET_MASK (0x1U) -#define PMC_OSTIMER_SOFTRESET_SHIFT (0U) -/*! SOFTRESET - Active high reset. - */ -#define PMC_OSTIMER_SOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_SOFTRESET_SHIFT)) & PMC_OSTIMER_SOFTRESET_MASK) - -#define PMC_OSTIMER_CLOCKENABLE_MASK (0x2U) -#define PMC_OSTIMER_CLOCKENABLE_SHIFT (1U) -/*! CLOCKENABLE - Enable OS event timer clock. - */ -#define PMC_OSTIMER_CLOCKENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_CLOCKENABLE_SHIFT)) & PMC_OSTIMER_CLOCKENABLE_MASK) - -#define PMC_OSTIMER_DPDWAKEUPENABLE_MASK (0x4U) -#define PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT (2U) -/*! DPDWAKEUPENABLE - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode). - */ -#define PMC_OSTIMER_DPDWAKEUPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSTIMER_DPDWAKEUPENABLE_MASK) - -#define PMC_OSTIMER_OSC32KPD_MASK (0x8U) -#define PMC_OSTIMER_OSC32KPD_SHIFT (3U) -/*! OSC32KPD - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K. - */ -#define PMC_OSTIMER_OSC32KPD(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSC32KPD_SHIFT)) & PMC_OSTIMER_OSC32KPD_MASK) - -#define PMC_OSTIMER_OSTIMERCLKSEL_MASK (0x30U) -#define PMC_OSTIMER_OSTIMERCLKSEL_SHIFT (4U) -/*! OSTIMERCLKSEL - OS event timer clock select. - * 0b00..Oscillator 32 kHz clock. - * 0b01..FRO 1MHz clock. - * 0b10..Main clock for OS timer. - * 0b11..No clock. - */ -#define PMC_OSTIMER_OSTIMERCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSTIMERCLKSEL_SHIFT)) & PMC_OSTIMER_OSTIMERCLKSEL_MASK) -/*! @} */ - -/*! @name PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_PDRUNCFG0_PDEN_BODVBAT_MASK (0x8U) -#define PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT (3U) -/*! PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD). - * 0b0..BOD VBAT is powered. - * 0b1..BOD VBAT is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVBAT_MASK) - -#define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U) -#define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U) -/*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. - * 0b0..FRO32KHz is powered. - * 0b1..FRO32KHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK) - -#define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U) -#define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U) -/*! PDEN_XTAL32K - Controls power to crystal 32 KHz. - * 0b0..Crystal 32KHz is powered. - * 0b1..Crystal 32KHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK) - -#define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK (0x100U) -#define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT (8U) -/*! PDEN_XTAL32M - Controls power to high speed crystal. - * 0b0..High speed crystal is powered. - * 0b1..High speed crystal is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK) - -#define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U) -#define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U) -/*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). - * 0b0..PLL0 is powered. - * 0b1..PLL0 is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK) - -#define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U) -#define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U) -/*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1). - * 0b0..PLL1 is powered. - * 0b1..PLL1 is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK) - -#define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK (0x800U) -#define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT (11U) -/*! PDEN_USBFSPHY - Controls power to USB Full Speed phy. - * 0b0..USB Full Speed phy is powered. - * 0b1..USB Full Speed phy is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK) - -#define PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK (0x1000U) -#define PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT (12U) -/*! PDEN_USBHSPHY - Controls power to USB High Speed Phy. - * 0b0..USB HS phy is powered. - * 0b1..USB HS phy is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK) - -#define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U) -#define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U) -/*! PDEN_COMP - Controls power to Analog Comparator. - * 0b0..Analog Comparator is powered. - * 0b1..Analog Comparator is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK) - -#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK (0x40000U) -#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT (18U) -/*! PDEN_LDOUSBHS - Controls power to USB high speed LDO. - * 0b0..USB high speed LDO is powered. - * 0b1..USB high speed LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK) - -#define PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK (0x80000U) -#define PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT (19U) -/*! PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS) - * 0b0..auxiliary biasing is powered. - * 0b1..auxiliary biasing is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK) - -#define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK (0x100000U) -#define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT (20U) -/*! PDEN_LDOXO32M - Controls power to high speed crystal LDO. - * 0b0..High speed crystal LDO is powered. - * 0b1..High speed crystal LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK) - -#define PMC_PDRUNCFG0_PDEN_RNG_MASK (0x400000U) -#define PMC_PDRUNCFG0_PDEN_RNG_SHIFT (22U) -/*! PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources. - * 0b0..TRNG clocks are powered. - * 0b1..TRNG clocks are powered down. - */ -#define PMC_PDRUNCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_RNG_SHIFT)) & PMC_PDRUNCFG0_PDEN_RNG_MASK) - -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U) -/*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. - * 0b0..PLL0 Sread spectrum module is powered. - * 0b1..PLL0 Sread spectrum module is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) -/*! @} */ - -/*! @name PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU) -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U) -/*! PDRUNCFGSET0 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. - */ -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK) -/*! @} */ - -/*! @name PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU) -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U) -/*! PDRUNCFGCLR0 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. - */ -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK) -/*! @} */ - -/*! @name SRAMCTRL - All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ -/*! @{ */ - -#define PMC_SRAMCTRL_SMB_MASK (0x3U) -#define PMC_SRAMCTRL_SMB_SHIFT (0U) -/*! SMB - Source Biasing voltage. - * 0b00..Low leakage. - * 0b01..Medium leakage. - * 0b10..Highest leakage. - * 0b11..Disable. - */ -#define PMC_SRAMCTRL_SMB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_SMB_SHIFT)) & PMC_SRAMCTRL_SMB_MASK) - -#define PMC_SRAMCTRL_RM_MASK (0x1CU) -#define PMC_SRAMCTRL_RM_SHIFT (2U) -/*! RM - Read Margin control settings. - */ -#define PMC_SRAMCTRL_RM(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_RM_SHIFT)) & PMC_SRAMCTRL_RM_MASK) - -#define PMC_SRAMCTRL_WM_MASK (0xE0U) -#define PMC_SRAMCTRL_WM_SHIFT (5U) -/*! WM - Write Margin control settings. - */ -#define PMC_SRAMCTRL_WM(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WM_SHIFT)) & PMC_SRAMCTRL_WM_MASK) - -#define PMC_SRAMCTRL_WRME_MASK (0x100U) -#define PMC_SRAMCTRL_WRME_SHIFT (8U) -/*! WRME - Write read margin enable. - */ -#define PMC_SRAMCTRL_WRME(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WRME_SHIFT)) & PMC_SRAMCTRL_WRME_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PMC_Register_Masks */ - - -/* PMC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PMC base address */ - #define PMC_BASE (0x50020000u) - /** Peripheral PMC base address */ - #define PMC_BASE_NS (0x40020000u) - /** Peripheral PMC base pointer */ - #define PMC ((PMC_Type *)PMC_BASE) - /** Peripheral PMC base pointer */ - #define PMC_NS ((PMC_Type *)PMC_BASE_NS) - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS { PMC_BASE } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS { PMC } - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS_NS { PMC_BASE_NS } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS_NS { PMC_NS } -#else - /** Peripheral PMC base address */ - #define PMC_BASE (0x40020000u) - /** Peripheral PMC base pointer */ - #define PMC ((PMC_Type *)PMC_BASE) - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS { PMC_BASE } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS { PMC } -#endif - -/*! - * @} - */ /* end of group PMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PRINCE Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PRINCE_Peripheral_Access_Layer PRINCE Peripheral Access Layer - * @{ - */ - -/** PRINCE - Register Layout Typedef */ -typedef struct { - __IO uint32_t ENC_ENABLE; /**< Encryption Enable register, offset: 0x0 */ - __O uint32_t MASK_LSB; /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */ - __O uint32_t MASK_MSB; /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */ - __IO uint32_t LOCK; /**< Lock register, offset: 0xC */ - __O uint32_t IV_LSB0; /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */ - __O uint32_t IV_MSB0; /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */ - __IO uint32_t BASE_ADDR0; /**< Base Address for region 0 register, offset: 0x18 */ - __IO uint32_t SR_ENABLE0; /**< Sub-Region Enable register for region 0, offset: 0x1C */ - __O uint32_t IV_LSB1; /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */ - __O uint32_t IV_MSB1; /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */ - __IO uint32_t BASE_ADDR1; /**< Base Address for region 1 register, offset: 0x28 */ - __IO uint32_t SR_ENABLE1; /**< Sub-Region Enable register for region 1, offset: 0x2C */ - __O uint32_t IV_LSB2; /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */ - __O uint32_t IV_MSB2; /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */ - __IO uint32_t BASE_ADDR2; /**< Base Address for region 2 register, offset: 0x38 */ - __IO uint32_t SR_ENABLE2; /**< Sub-Region Enable register for region 2, offset: 0x3C */ - uint8_t RESERVED_0[80]; - __IO uint32_t ERR; /**< Error status register, offset: 0x90 */ -} PRINCE_Type; - -/* ---------------------------------------------------------------------------- - -- PRINCE Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PRINCE_Register_Masks PRINCE Register Masks - * @{ - */ - -/*! @name ENC_ENABLE - Encryption Enable register */ -/*! @{ */ - -#define PRINCE_ENC_ENABLE_EN_MASK (0x1U) -#define PRINCE_ENC_ENABLE_EN_SHIFT (0U) -/*! EN - Enables PRINCE encryption for flash programming. - * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled. - * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled. Reading of PRINCE-encrypted flash regions is disabled. - */ -#define PRINCE_ENC_ENABLE_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK) -/*! @} */ - -/*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */ -/*! @{ */ - -#define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU) -#define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U) -/*! MASKVAL - Value of the 32 Least Significant Bits of the 64-bit data mask. - */ -#define PRINCE_MASK_LSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK) -/*! @} */ - -/*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */ -/*! @{ */ - -#define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU) -#define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U) -/*! MASKVAL - Value of the 32 Most Significant Bits of the 64-bit data mask. - */ -#define PRINCE_MASK_MSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK) -/*! @} */ - -/*! @name LOCK - Lock register */ -/*! @{ */ - -#define PRINCE_LOCK_LOCKREG0_MASK (0x1U) -#define PRINCE_LOCK_LOCKREG0_SHIFT (0U) -/*! LOCKREG0 - Lock Region 0 registers. - * 0b0..Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. - * 0b1..Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. - */ -#define PRINCE_LOCK_LOCKREG0(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK) - -#define PRINCE_LOCK_LOCKREG1_MASK (0x2U) -#define PRINCE_LOCK_LOCKREG1_SHIFT (1U) -/*! LOCKREG1 - Lock Region 1 registers. - * 0b0..Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. - * 0b1..Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. - */ -#define PRINCE_LOCK_LOCKREG1(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK) - -#define PRINCE_LOCK_LOCKREG2_MASK (0x4U) -#define PRINCE_LOCK_LOCKREG2_SHIFT (2U) -/*! LOCKREG2 - Lock Region 2 registers. - * 0b0..Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. - * 0b1..Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. - */ -#define PRINCE_LOCK_LOCKREG2(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK) - -#define PRINCE_LOCK_LOCKMASK_MASK (0x100U) -#define PRINCE_LOCK_LOCKMASK_SHIFT (8U) -/*! LOCKMASK - Lock the Mask registers. - * 0b0..Disabled. MASK_LSB, and MASK_MSB are writable.. - * 0b1..Enabled. MASK_LSB, and MASK_MSB are not writable.. - */ -#define PRINCE_LOCK_LOCKMASK(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK) -/*! @} */ - -/*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB0_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_LSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB0_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_MSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR0 - Base Address for region 0 register */ -/*! @{ */ - -#define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U) -/*! ADDR_FIXED - Fixed portion of the base address of region 0. - */ -#define PRINCE_BASE_ADDR0_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK) - -#define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U) -/*! ADDR_PRG - Programmable portion of the base address of region 0. - */ -#define PRINCE_BASE_ADDR0_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */ -/*! @{ */ - -#define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE0_EN_SHIFT (0U) -/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0. - */ -#define PRINCE_SR_ENABLE0_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK) -/*! @} */ - -/*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB1_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_LSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB1_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_MSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR1 - Base Address for region 1 register */ -/*! @{ */ - -#define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U) -/*! ADDR_FIXED - Fixed portion of the base address of region 1. - */ -#define PRINCE_BASE_ADDR1_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK) - -#define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U) -/*! ADDR_PRG - Programmable portion of the base address of region 1. - */ -#define PRINCE_BASE_ADDR1_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */ -/*! @{ */ - -#define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE1_EN_SHIFT (0U) -/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1. - */ -#define PRINCE_SR_ENABLE1_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK) -/*! @} */ - -/*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB2_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_LSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB2_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_MSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR2 - Base Address for region 2 register */ -/*! @{ */ - -#define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U) -/*! ADDR_FIXED - Fixed portion of the base address of region 2. - */ -#define PRINCE_BASE_ADDR2_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK) - -#define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U) -/*! ADDR_PRG - Programmable portion of the base address of region 2. - */ -#define PRINCE_BASE_ADDR2_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */ -/*! @{ */ - -#define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE2_EN_SHIFT (0U) -/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2. - */ -#define PRINCE_SR_ENABLE2_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK) -/*! @} */ - -/*! @name ERR - Error status register */ -/*! @{ */ - -#define PRINCE_ERR_ERRSTAT_MASK (0x1U) -#define PRINCE_ERR_ERRSTAT_SHIFT (0U) -/*! ERRSTAT - PRINCE Error Status. This bit is write-1 to clear. - * 0b0..No PRINCE error. - * 0b1..Error. A read of a PRINCE-encrypted region was attempted while ENC_ENABLE.EN=1. - */ -#define PRINCE_ERR_ERRSTAT(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ERR_ERRSTAT_SHIFT)) & PRINCE_ERR_ERRSTAT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PRINCE_Register_Masks */ - - -/* PRINCE - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PRINCE base address */ - #define PRINCE_BASE (0x50035000u) - /** Peripheral PRINCE base address */ - #define PRINCE_BASE_NS (0x40035000u) - /** Peripheral PRINCE base pointer */ - #define PRINCE ((PRINCE_Type *)PRINCE_BASE) - /** Peripheral PRINCE base pointer */ - #define PRINCE_NS ((PRINCE_Type *)PRINCE_BASE_NS) - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS { PRINCE_BASE } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS { PRINCE } - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS_NS { PRINCE_BASE_NS } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS_NS { PRINCE_NS } -#else - /** Peripheral PRINCE base address */ - #define PRINCE_BASE (0x40035000u) - /** Peripheral PRINCE base pointer */ - #define PRINCE ((PRINCE_Type *)PRINCE_BASE) - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS { PRINCE_BASE } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS { PRINCE } -#endif - -/*! - * @} - */ /* end of group PRINCE_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PUF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer - * @{ - */ - -/** PUF - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< PUF Control register, offset: 0x0 */ - __IO uint32_t KEYINDEX; /**< PUF Key Index register, offset: 0x4 */ - __IO uint32_t KEYSIZE; /**< PUF Key Size register, offset: 0x8 */ - uint8_t RESERVED_0[20]; - __I uint32_t STAT; /**< PUF Status register, offset: 0x20 */ - uint8_t RESERVED_1[4]; - __I uint32_t ALLOW; /**< PUF Allow register, offset: 0x28 */ - uint8_t RESERVED_2[20]; - __O uint32_t KEYINPUT; /**< PUF Key Input register, offset: 0x40 */ - __O uint32_t CODEINPUT; /**< PUF Code Input register, offset: 0x44 */ - __I uint32_t CODEOUTPUT; /**< PUF Code Output register, offset: 0x48 */ - uint8_t RESERVED_3[20]; - __I uint32_t KEYOUTINDEX; /**< PUF Key Output Index register, offset: 0x60 */ - __I uint32_t KEYOUTPUT; /**< PUF Key Output register, offset: 0x64 */ - uint8_t RESERVED_4[116]; - __IO uint32_t IFSTAT; /**< PUF Interface Status and clear register, offset: 0xDC */ - uint8_t RESERVED_5[32]; - __IO uint32_t INTEN; /**< PUF Interrupt Enable, offset: 0x100 */ - __IO uint32_t INTSTAT; /**< PUF interrupt status, offset: 0x104 */ - uint8_t RESERVED_6[4]; - __IO uint32_t CFG; /**< PUF config register for block bits, offset: 0x10C */ - uint8_t RESERVED_7[240]; - __IO uint32_t KEYLOCK; /**< Only reset in case of full IC reset, offset: 0x200 */ - __IO uint32_t KEYENABLE; /**< , offset: 0x204 */ - __O uint32_t KEYRESET; /**< Reinitialize Keys shift registers counters, offset: 0x208 */ - __O uint32_t IDXBLK; /**< , offset: 0x20C */ - __O uint32_t IDXBLK_DP; /**< , offset: 0x210 */ - __O uint32_t KEYMASK[4]; /**< Only reset in case of full IC reset, array offset: 0x214, array step: 0x4 */ - uint8_t RESERVED_8[48]; - __I uint32_t IDXBLK_STATUS; /**< Index block status, offset: 0x254 */ - __I uint32_t SHIFT_STATUS; /**< , offset: 0x258 */ -} PUF_Type; - -/* ---------------------------------------------------------------------------- - -- PUF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_Register_Masks PUF Register Masks - * @{ - */ - -/*! @name CTRL - PUF Control register */ -/*! @{ */ - -#define PUF_CTRL_ZEROIZE_MASK (0x1U) -#define PUF_CTRL_ZEROIZE_SHIFT (0U) -/*! zeroize - Begin Zeroize operation for PUF and go to Error state - */ -#define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK) - -#define PUF_CTRL_ENROLL_MASK (0x2U) -#define PUF_CTRL_ENROLL_SHIFT (1U) -/*! enroll - Begin Enroll operation - */ -#define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK) - -#define PUF_CTRL_START_MASK (0x4U) -#define PUF_CTRL_START_SHIFT (2U) -/*! start - Begin Start operation - */ -#define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK) - -#define PUF_CTRL_GENERATEKEY_MASK (0x8U) -#define PUF_CTRL_GENERATEKEY_SHIFT (3U) -/*! GENERATEKEY - Begin Set Intrinsic Key operation - */ -#define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK) - -#define PUF_CTRL_SETKEY_MASK (0x10U) -#define PUF_CTRL_SETKEY_SHIFT (4U) -/*! SETKEY - Begin Set User Key operation - */ -#define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK) - -#define PUF_CTRL_GETKEY_MASK (0x40U) -#define PUF_CTRL_GETKEY_SHIFT (6U) -/*! GETKEY - Begin Get Key operation - */ -#define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK) -/*! @} */ - -/*! @name KEYINDEX - PUF Key Index register */ -/*! @{ */ - -#define PUF_KEYINDEX_KEYIDX_MASK (0xFU) -#define PUF_KEYINDEX_KEYIDX_SHIFT (0U) -/*! KEYIDX - Key index for Set Key operations - */ -#define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK) -/*! @} */ - -/*! @name KEYSIZE - PUF Key Size register */ -/*! @{ */ - -#define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU) -#define PUF_KEYSIZE_KEYSIZE_SHIFT (0U) -/*! KEYSIZE - Key size for Set Key operations - */ -#define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK) -/*! @} */ - -/*! @name STAT - PUF Status register */ -/*! @{ */ - -#define PUF_STAT_BUSY_MASK (0x1U) -#define PUF_STAT_BUSY_SHIFT (0U) -/*! busy - Indicates that operation is in progress - */ -#define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK) - -#define PUF_STAT_SUCCESS_MASK (0x2U) -#define PUF_STAT_SUCCESS_SHIFT (1U) -/*! SUCCESS - Last operation was successful - */ -#define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK) - -#define PUF_STAT_ERROR_MASK (0x4U) -#define PUF_STAT_ERROR_SHIFT (2U) -/*! error - PUF is in the Error state and no operations can be performed - */ -#define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK) - -#define PUF_STAT_KEYINREQ_MASK (0x10U) -#define PUF_STAT_KEYINREQ_SHIFT (4U) -/*! KEYINREQ - Request for next part of key - */ -#define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK) - -#define PUF_STAT_KEYOUTAVAIL_MASK (0x20U) -#define PUF_STAT_KEYOUTAVAIL_SHIFT (5U) -/*! KEYOUTAVAIL - Next part of key is available - */ -#define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK) - -#define PUF_STAT_CODEINREQ_MASK (0x40U) -#define PUF_STAT_CODEINREQ_SHIFT (6U) -/*! CODEINREQ - Request for next part of AC/KC - */ -#define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK) - -#define PUF_STAT_CODEOUTAVAIL_MASK (0x80U) -#define PUF_STAT_CODEOUTAVAIL_SHIFT (7U) -/*! CODEOUTAVAIL - Next part of AC/KC is available - */ -#define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK) -/*! @} */ - -/*! @name ALLOW - PUF Allow register */ -/*! @{ */ - -#define PUF_ALLOW_ALLOWENROLL_MASK (0x1U) -#define PUF_ALLOW_ALLOWENROLL_SHIFT (0U) -/*! ALLOWENROLL - Enroll operation is allowed - */ -#define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK) - -#define PUF_ALLOW_ALLOWSTART_MASK (0x2U) -#define PUF_ALLOW_ALLOWSTART_SHIFT (1U) -/*! ALLOWSTART - Start operation is allowed - */ -#define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK) - -#define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U) -#define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U) -/*! ALLOWSETKEY - Set Key operations are allowed - */ -#define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK) - -#define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U) -#define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U) -/*! ALLOWGETKEY - Get Key operation is allowed - */ -#define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK) -/*! @} */ - -/*! @name KEYINPUT - PUF Key Input register */ -/*! @{ */ - -#define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU) -#define PUF_KEYINPUT_KEYIN_SHIFT (0U) -/*! KEYIN - Key input data - */ -#define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK) -/*! @} */ - -/*! @name CODEINPUT - PUF Code Input register */ -/*! @{ */ - -#define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU) -#define PUF_CODEINPUT_CODEIN_SHIFT (0U) -/*! CODEIN - AC/KC input data - */ -#define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK) -/*! @} */ - -/*! @name CODEOUTPUT - PUF Code Output register */ -/*! @{ */ - -#define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU) -#define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U) -/*! CODEOUT - AC/KC output data - */ -#define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK) -/*! @} */ - -/*! @name KEYOUTINDEX - PUF Key Output Index register */ -/*! @{ */ - -#define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFU) -#define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U) -/*! KEYOUTIDX - Key index for the key that is currently output via the Key Output register - */ -#define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK) -/*! @} */ - -/*! @name KEYOUTPUT - PUF Key Output register */ -/*! @{ */ - -#define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU) -#define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U) -/*! KEYOUT - Key output data - */ -#define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK) -/*! @} */ - -/*! @name IFSTAT - PUF Interface Status and clear register */ -/*! @{ */ - -#define PUF_IFSTAT_ERROR_MASK (0x1U) -#define PUF_IFSTAT_ERROR_SHIFT (0U) -/*! ERROR - Indicates that an APB error has occurred,Writing logic1 clears the if_error bit - */ -#define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK) -/*! @} */ - -/*! @name INTEN - PUF Interrupt Enable */ -/*! @{ */ - -#define PUF_INTEN_READYEN_MASK (0x1U) -#define PUF_INTEN_READYEN_SHIFT (0U) -/*! READYEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK) - -#define PUF_INTEN_SUCCESEN_MASK (0x2U) -#define PUF_INTEN_SUCCESEN_SHIFT (1U) -/*! SUCCESEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_SUCCESEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK) - -#define PUF_INTEN_ERROREN_MASK (0x4U) -#define PUF_INTEN_ERROREN_SHIFT (2U) -/*! ERROREN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK) - -#define PUF_INTEN_KEYINREQEN_MASK (0x10U) -#define PUF_INTEN_KEYINREQEN_SHIFT (4U) -/*! KEYINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK) - -#define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U) -#define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U) -/*! KEYOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK) - -#define PUF_INTEN_CODEINREQEN_MASK (0x40U) -#define PUF_INTEN_CODEINREQEN_SHIFT (6U) -/*! CODEINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK) - -#define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U) -#define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U) -/*! CODEOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK) -/*! @} */ - -/*! @name INTSTAT - PUF interrupt status */ -/*! @{ */ - -#define PUF_INTSTAT_READY_MASK (0x1U) -#define PUF_INTSTAT_READY_SHIFT (0U) -/*! READY - Triggers on falling edge of busy, write 1 to clear - */ -#define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK) - -#define PUF_INTSTAT_SUCCESS_MASK (0x2U) -#define PUF_INTSTAT_SUCCESS_SHIFT (1U) -/*! SUCCESS - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK) - -#define PUF_INTSTAT_ERROR_MASK (0x4U) -#define PUF_INTSTAT_ERROR_SHIFT (2U) -/*! ERROR - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK) - -#define PUF_INTSTAT_KEYINREQ_MASK (0x10U) -#define PUF_INTSTAT_KEYINREQ_SHIFT (4U) -/*! KEYINREQ - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK) - -#define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U) -#define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U) -/*! KEYOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK) - -#define PUF_INTSTAT_CODEINREQ_MASK (0x40U) -#define PUF_INTSTAT_CODEINREQ_SHIFT (6U) -/*! CODEINREQ - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK) - -#define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U) -#define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U) -/*! CODEOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK) -/*! @} */ - -/*! @name CFG - PUF config register for block bits */ -/*! @{ */ - -#define PUF_CFG_BLOCKENROLL_SETKEY_MASK (0x1U) -#define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT (0U) -/*! BLOCKENROLL_SETKEY - Block enroll operation. Write 1 to set, cleared on reset. - */ -#define PUF_CFG_BLOCKENROLL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK) - -#define PUF_CFG_BLOCKKEYOUTPUT_MASK (0x2U) -#define PUF_CFG_BLOCKKEYOUTPUT_SHIFT (1U) -/*! BLOCKKEYOUTPUT - Block set key operation. Write 1 to set, cleared on reset. - */ -#define PUF_CFG_BLOCKKEYOUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK) -/*! @} */ - -/*! @name KEYLOCK - Only reset in case of full IC reset */ -/*! @{ */ - -#define PUF_KEYLOCK_KEY0_MASK (0x3U) -#define PUF_KEYLOCK_KEY0_SHIFT (0U) -/*! KEY0 - "10:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is allowed. 00, 01, - * 11:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is NOT allowed. Important Note : Once - * this field is written with a value different from '10', its value can no longer be modified - * until un Power On Reset occurs." - */ -#define PUF_KEYLOCK_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK) - -#define PUF_KEYLOCK_KEY1_MASK (0xCU) -#define PUF_KEYLOCK_KEY1_SHIFT (2U) -/*! KEY1 - "10:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is allowed. 00, 01, - * 11:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is NOT allowed. Important Note : Once - * this field is written with a value different from '10', its value can no longer be modified - * until un Power On Reset occurs." - */ -#define PUF_KEYLOCK_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK) - -#define PUF_KEYLOCK_KEY2_MASK (0x30U) -#define PUF_KEYLOCK_KEY2_SHIFT (4U) -/*! KEY2 - "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, - * 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once - * this field is written with a value different from '10', its value can no longer be modified - * until un Power On Reset occurs." - */ -#define PUF_KEYLOCK_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK) - -#define PUF_KEYLOCK_KEY3_MASK (0xC0U) -#define PUF_KEYLOCK_KEY3_SHIFT (6U) -/*! KEY3 - "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, - * 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once - * this field is written with a value different from '10', its value can no longer be modified - * until un Power On Reset occurs." - */ -#define PUF_KEYLOCK_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK) -/*! @} */ - -/*! @name KEYENABLE - */ -/*! @{ */ - -#define PUF_KEYENABLE_KEY0_MASK (0x3U) -#define PUF_KEYENABLE_KEY0_SHIFT (0U) -/*! KEY0 - "10: Data coming out from PUF Index 0 interface are shifted in KEY0 register. 00, 01, 11 - * : Data coming out from PUF Index 0 interface are NOT shifted in KEY0 register." - */ -#define PUF_KEYENABLE_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK) - -#define PUF_KEYENABLE_KEY1_MASK (0xCU) -#define PUF_KEYENABLE_KEY1_SHIFT (2U) -/*! KEY1 - "10: Data coming out from PUF Index 0 interface are shifted in KEY1 register. 00, 01, 11 - * : Data coming out from PUF Index 0 interface are NOT shifted in KEY1 register." - */ -#define PUF_KEYENABLE_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK) - -#define PUF_KEYENABLE_KEY2_MASK (0x30U) -#define PUF_KEYENABLE_KEY2_SHIFT (4U) -/*! KEY2 - "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 - * : Data coming out from PUF Index 0 interface are NOT shifted in KEY2 register." - */ -#define PUF_KEYENABLE_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK) - -#define PUF_KEYENABLE_KEY3_MASK (0xC0U) -#define PUF_KEYENABLE_KEY3_SHIFT (6U) -/*! KEY3 - "10: Data coming out from PUF Index 0 interface are shifted in KEY3 register. 00, 01, 11 - * : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." - */ -#define PUF_KEYENABLE_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK) -/*! @} */ - -/*! @name KEYRESET - Reinitialize Keys shift registers counters */ -/*! @{ */ - -#define PUF_KEYRESET_KEY0_MASK (0x3U) -#define PUF_KEYRESET_KEY0_SHIFT (0U) -/*! KEY0 - 10: Reset KEY0 shift register. Self clearing. Must be done before loading any new key. - */ -#define PUF_KEYRESET_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK) - -#define PUF_KEYRESET_KEY1_MASK (0xCU) -#define PUF_KEYRESET_KEY1_SHIFT (2U) -/*! KEY1 - 10: Reset KEY1 shift register. Self clearing. Must be done before loading any new key. - */ -#define PUF_KEYRESET_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK) - -#define PUF_KEYRESET_KEY2_MASK (0x30U) -#define PUF_KEYRESET_KEY2_SHIFT (4U) -/*! KEY2 - 10: Reset KEY2 shift register. Self clearing. Must be done before loading any new key. - */ -#define PUF_KEYRESET_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK) - -#define PUF_KEYRESET_KEY3_MASK (0xC0U) -#define PUF_KEYRESET_KEY3_SHIFT (6U) -/*! KEY3 - 10: Reset KEY3 shift register. Self clearing. Must be done before loading any new key. - */ -#define PUF_KEYRESET_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK) -/*! @} */ - -/*! @name IDXBLK - */ -/*! @{ */ - -#define PUF_IDXBLK_IDX0_MASK (0x3U) -#define PUF_IDXBLK_IDX0_SHIFT (0U) -/*! IDX0 - Use to block PUF index 0 - */ -#define PUF_IDXBLK_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX0_SHIFT)) & PUF_IDXBLK_IDX0_MASK) - -#define PUF_IDXBLK_IDX1_MASK (0xCU) -#define PUF_IDXBLK_IDX1_SHIFT (2U) -/*! IDX1 - Use to block PUF index 1 - */ -#define PUF_IDXBLK_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX1_SHIFT)) & PUF_IDXBLK_IDX1_MASK) - -#define PUF_IDXBLK_IDX2_MASK (0x30U) -#define PUF_IDXBLK_IDX2_SHIFT (4U) -/*! IDX2 - Use to block PUF index 2 - */ -#define PUF_IDXBLK_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX2_SHIFT)) & PUF_IDXBLK_IDX2_MASK) - -#define PUF_IDXBLK_IDX3_MASK (0xC0U) -#define PUF_IDXBLK_IDX3_SHIFT (6U) -/*! IDX3 - Use to block PUF index 3 - */ -#define PUF_IDXBLK_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX3_SHIFT)) & PUF_IDXBLK_IDX3_MASK) - -#define PUF_IDXBLK_IDX4_MASK (0x300U) -#define PUF_IDXBLK_IDX4_SHIFT (8U) -/*! IDX4 - Use to block PUF index 4 - */ -#define PUF_IDXBLK_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX4_SHIFT)) & PUF_IDXBLK_IDX4_MASK) - -#define PUF_IDXBLK_IDX5_MASK (0xC00U) -#define PUF_IDXBLK_IDX5_SHIFT (10U) -/*! IDX5 - Use to block PUF index 5 - */ -#define PUF_IDXBLK_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX5_SHIFT)) & PUF_IDXBLK_IDX5_MASK) - -#define PUF_IDXBLK_IDX6_MASK (0x3000U) -#define PUF_IDXBLK_IDX6_SHIFT (12U) -/*! IDX6 - Use to block PUF index 6 - */ -#define PUF_IDXBLK_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX6_SHIFT)) & PUF_IDXBLK_IDX6_MASK) - -#define PUF_IDXBLK_IDX7_MASK (0xC000U) -#define PUF_IDXBLK_IDX7_SHIFT (14U) -/*! IDX7 - Use to block PUF index 7 - */ -#define PUF_IDXBLK_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX7_SHIFT)) & PUF_IDXBLK_IDX7_MASK) - -#define PUF_IDXBLK_IDX8_MASK (0x30000U) -#define PUF_IDXBLK_IDX8_SHIFT (16U) -/*! IDX8 - Use to block PUF index 8 - */ -#define PUF_IDXBLK_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX8_SHIFT)) & PUF_IDXBLK_IDX8_MASK) - -#define PUF_IDXBLK_IDX9_MASK (0xC0000U) -#define PUF_IDXBLK_IDX9_SHIFT (18U) -/*! IDX9 - Use to block PUF index 9 - */ -#define PUF_IDXBLK_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX9_SHIFT)) & PUF_IDXBLK_IDX9_MASK) - -#define PUF_IDXBLK_IDX10_MASK (0x300000U) -#define PUF_IDXBLK_IDX10_SHIFT (20U) -/*! IDX10 - Use to block PUF index 10 - */ -#define PUF_IDXBLK_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX10_SHIFT)) & PUF_IDXBLK_IDX10_MASK) - -#define PUF_IDXBLK_IDX11_MASK (0xC00000U) -#define PUF_IDXBLK_IDX11_SHIFT (22U) -/*! IDX11 - Use to block PUF index 11 - */ -#define PUF_IDXBLK_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX11_SHIFT)) & PUF_IDXBLK_IDX11_MASK) - -#define PUF_IDXBLK_IDX12_MASK (0x3000000U) -#define PUF_IDXBLK_IDX12_SHIFT (24U) -/*! IDX12 - Use to block PUF index 12 - */ -#define PUF_IDXBLK_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX12_SHIFT)) & PUF_IDXBLK_IDX12_MASK) - -#define PUF_IDXBLK_IDX13_MASK (0xC000000U) -#define PUF_IDXBLK_IDX13_SHIFT (26U) -/*! IDX13 - Use to block PUF index 13 - */ -#define PUF_IDXBLK_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX13_SHIFT)) & PUF_IDXBLK_IDX13_MASK) - -#define PUF_IDXBLK_IDX14_MASK (0x30000000U) -#define PUF_IDXBLK_IDX14_SHIFT (28U) -/*! IDX14 - Use to block PUF index 14 - */ -#define PUF_IDXBLK_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX14_SHIFT)) & PUF_IDXBLK_IDX14_MASK) - -#define PUF_IDXBLK_IDX15_MASK (0xC0000000U) -#define PUF_IDXBLK_IDX15_SHIFT (30U) -/*! IDX15 - Use to block PUF index 15 - */ -#define PUF_IDXBLK_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX15_SHIFT)) & PUF_IDXBLK_IDX15_MASK) -/*! @} */ - -/*! @name IDXBLK_DP - */ -/*! @{ */ - -#define PUF_IDXBLK_DP_IDX0_MASK (0x3U) -#define PUF_IDXBLK_DP_IDX0_SHIFT (0U) -/*! IDX0 - Use to block PUF index 0 - */ -#define PUF_IDXBLK_DP_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX0_SHIFT)) & PUF_IDXBLK_DP_IDX0_MASK) - -#define PUF_IDXBLK_DP_IDX1_MASK (0xCU) -#define PUF_IDXBLK_DP_IDX1_SHIFT (2U) -/*! IDX1 - Use to block PUF index 1 - */ -#define PUF_IDXBLK_DP_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX1_SHIFT)) & PUF_IDXBLK_DP_IDX1_MASK) - -#define PUF_IDXBLK_DP_IDX2_MASK (0x30U) -#define PUF_IDXBLK_DP_IDX2_SHIFT (4U) -/*! IDX2 - Use to block PUF index 2 - */ -#define PUF_IDXBLK_DP_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX2_SHIFT)) & PUF_IDXBLK_DP_IDX2_MASK) - -#define PUF_IDXBLK_DP_IDX3_MASK (0xC0U) -#define PUF_IDXBLK_DP_IDX3_SHIFT (6U) -/*! IDX3 - Use to block PUF index 3 - */ -#define PUF_IDXBLK_DP_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX3_SHIFT)) & PUF_IDXBLK_DP_IDX3_MASK) - -#define PUF_IDXBLK_DP_IDX4_MASK (0x300U) -#define PUF_IDXBLK_DP_IDX4_SHIFT (8U) -/*! IDX4 - Use to block PUF index 4 - */ -#define PUF_IDXBLK_DP_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX4_SHIFT)) & PUF_IDXBLK_DP_IDX4_MASK) - -#define PUF_IDXBLK_DP_IDX5_MASK (0xC00U) -#define PUF_IDXBLK_DP_IDX5_SHIFT (10U) -/*! IDX5 - Use to block PUF index 5 - */ -#define PUF_IDXBLK_DP_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX5_SHIFT)) & PUF_IDXBLK_DP_IDX5_MASK) - -#define PUF_IDXBLK_DP_IDX6_MASK (0x3000U) -#define PUF_IDXBLK_DP_IDX6_SHIFT (12U) -/*! IDX6 - Use to block PUF index 6 - */ -#define PUF_IDXBLK_DP_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX6_SHIFT)) & PUF_IDXBLK_DP_IDX6_MASK) - -#define PUF_IDXBLK_DP_IDX7_MASK (0xC000U) -#define PUF_IDXBLK_DP_IDX7_SHIFT (14U) -/*! IDX7 - Use to block PUF index 7 - */ -#define PUF_IDXBLK_DP_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX7_SHIFT)) & PUF_IDXBLK_DP_IDX7_MASK) - -#define PUF_IDXBLK_DP_IDX8_MASK (0x30000U) -#define PUF_IDXBLK_DP_IDX8_SHIFT (16U) -/*! IDX8 - Use to block PUF index 8 - */ -#define PUF_IDXBLK_DP_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX8_SHIFT)) & PUF_IDXBLK_DP_IDX8_MASK) - -#define PUF_IDXBLK_DP_IDX9_MASK (0xC0000U) -#define PUF_IDXBLK_DP_IDX9_SHIFT (18U) -/*! IDX9 - Use to block PUF index 9 - */ -#define PUF_IDXBLK_DP_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX9_SHIFT)) & PUF_IDXBLK_DP_IDX9_MASK) - -#define PUF_IDXBLK_DP_IDX10_MASK (0x300000U) -#define PUF_IDXBLK_DP_IDX10_SHIFT (20U) -/*! IDX10 - Use to block PUF index 10 - */ -#define PUF_IDXBLK_DP_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX10_SHIFT)) & PUF_IDXBLK_DP_IDX10_MASK) - -#define PUF_IDXBLK_DP_IDX11_MASK (0xC00000U) -#define PUF_IDXBLK_DP_IDX11_SHIFT (22U) -/*! IDX11 - Use to block PUF index 11 - */ -#define PUF_IDXBLK_DP_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX11_SHIFT)) & PUF_IDXBLK_DP_IDX11_MASK) - -#define PUF_IDXBLK_DP_IDX12_MASK (0x3000000U) -#define PUF_IDXBLK_DP_IDX12_SHIFT (24U) -/*! IDX12 - Use to block PUF index 12 - */ -#define PUF_IDXBLK_DP_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX12_SHIFT)) & PUF_IDXBLK_DP_IDX12_MASK) - -#define PUF_IDXBLK_DP_IDX13_MASK (0xC000000U) -#define PUF_IDXBLK_DP_IDX13_SHIFT (26U) -/*! IDX13 - Use to block PUF index 13 - */ -#define PUF_IDXBLK_DP_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX13_SHIFT)) & PUF_IDXBLK_DP_IDX13_MASK) - -#define PUF_IDXBLK_DP_IDX14_MASK (0x30000000U) -#define PUF_IDXBLK_DP_IDX14_SHIFT (28U) -/*! IDX14 - Use to block PUF index 14 - */ -#define PUF_IDXBLK_DP_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX14_SHIFT)) & PUF_IDXBLK_DP_IDX14_MASK) - -#define PUF_IDXBLK_DP_IDX15_MASK (0xC0000000U) -#define PUF_IDXBLK_DP_IDX15_SHIFT (30U) -/*! IDX15 - Use to block PUF index 15 - */ -#define PUF_IDXBLK_DP_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX15_SHIFT)) & PUF_IDXBLK_DP_IDX15_MASK) -/*! @} */ - -/*! @name KEYMASK - Only reset in case of full IC reset */ -/*! @{ */ - -#define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU) -#define PUF_KEYMASK_KEYMASK_SHIFT (0U) -#define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK) -/*! @} */ - -/* The count of PUF_KEYMASK */ -#define PUF_KEYMASK_COUNT (4U) - -/*! @name IDXBLK_STATUS - Index block status */ -/*! @{ */ - -#define PUF_IDXBLK_STATUS_IDX0_MASK (0x3U) -#define PUF_IDXBLK_STATUS_IDX0_SHIFT (0U) -/*! IDX0 - Status block index 0 - */ -#define PUF_IDXBLK_STATUS_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX0_SHIFT)) & PUF_IDXBLK_STATUS_IDX0_MASK) - -#define PUF_IDXBLK_STATUS_IDX1_MASK (0xCU) -#define PUF_IDXBLK_STATUS_IDX1_SHIFT (2U) -/*! IDX1 - Status block index 1 - */ -#define PUF_IDXBLK_STATUS_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX1_SHIFT)) & PUF_IDXBLK_STATUS_IDX1_MASK) - -#define PUF_IDXBLK_STATUS_IDX2_MASK (0x30U) -#define PUF_IDXBLK_STATUS_IDX2_SHIFT (4U) -/*! IDX2 - Status block index 2 - */ -#define PUF_IDXBLK_STATUS_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX2_SHIFT)) & PUF_IDXBLK_STATUS_IDX2_MASK) - -#define PUF_IDXBLK_STATUS_IDX3_MASK (0xC0U) -#define PUF_IDXBLK_STATUS_IDX3_SHIFT (6U) -/*! IDX3 - Status block index 3 - */ -#define PUF_IDXBLK_STATUS_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX3_SHIFT)) & PUF_IDXBLK_STATUS_IDX3_MASK) - -#define PUF_IDXBLK_STATUS_IDX4_MASK (0x300U) -#define PUF_IDXBLK_STATUS_IDX4_SHIFT (8U) -/*! IDX4 - Status block index 4 - */ -#define PUF_IDXBLK_STATUS_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX4_SHIFT)) & PUF_IDXBLK_STATUS_IDX4_MASK) - -#define PUF_IDXBLK_STATUS_IDX5_MASK (0xC00U) -#define PUF_IDXBLK_STATUS_IDX5_SHIFT (10U) -/*! IDX5 - Status block index 5 - */ -#define PUF_IDXBLK_STATUS_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX5_SHIFT)) & PUF_IDXBLK_STATUS_IDX5_MASK) - -#define PUF_IDXBLK_STATUS_IDX6_MASK (0x3000U) -#define PUF_IDXBLK_STATUS_IDX6_SHIFT (12U) -/*! IDX6 - Status block index 6 - */ -#define PUF_IDXBLK_STATUS_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX6_SHIFT)) & PUF_IDXBLK_STATUS_IDX6_MASK) - -#define PUF_IDXBLK_STATUS_IDX7_MASK (0xC000U) -#define PUF_IDXBLK_STATUS_IDX7_SHIFT (14U) -/*! IDX7 - Status block index 7 - */ -#define PUF_IDXBLK_STATUS_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX7_SHIFT)) & PUF_IDXBLK_STATUS_IDX7_MASK) - -#define PUF_IDXBLK_STATUS_IDX8_MASK (0x30000U) -#define PUF_IDXBLK_STATUS_IDX8_SHIFT (16U) -/*! IDX8 - Status block index 8 - */ -#define PUF_IDXBLK_STATUS_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX8_SHIFT)) & PUF_IDXBLK_STATUS_IDX8_MASK) - -#define PUF_IDXBLK_STATUS_IDX9_MASK (0xC0000U) -#define PUF_IDXBLK_STATUS_IDX9_SHIFT (18U) -/*! IDX9 - Status block index 9 - */ -#define PUF_IDXBLK_STATUS_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX9_SHIFT)) & PUF_IDXBLK_STATUS_IDX9_MASK) - -#define PUF_IDXBLK_STATUS_IDX10_MASK (0x300000U) -#define PUF_IDXBLK_STATUS_IDX10_SHIFT (20U) -/*! IDX10 - Status block index 10 - */ -#define PUF_IDXBLK_STATUS_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX10_SHIFT)) & PUF_IDXBLK_STATUS_IDX10_MASK) - -#define PUF_IDXBLK_STATUS_IDX11_MASK (0xC00000U) -#define PUF_IDXBLK_STATUS_IDX11_SHIFT (22U) -/*! IDX11 - Status block index 11 - */ -#define PUF_IDXBLK_STATUS_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX11_SHIFT)) & PUF_IDXBLK_STATUS_IDX11_MASK) - -#define PUF_IDXBLK_STATUS_IDX12_MASK (0x3000000U) -#define PUF_IDXBLK_STATUS_IDX12_SHIFT (24U) -/*! IDX12 - Status block index 12 - */ -#define PUF_IDXBLK_STATUS_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX12_SHIFT)) & PUF_IDXBLK_STATUS_IDX12_MASK) - -#define PUF_IDXBLK_STATUS_IDX13_MASK (0xC000000U) -#define PUF_IDXBLK_STATUS_IDX13_SHIFT (26U) -/*! IDX13 - Status block index 13 - */ -#define PUF_IDXBLK_STATUS_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX13_SHIFT)) & PUF_IDXBLK_STATUS_IDX13_MASK) - -#define PUF_IDXBLK_STATUS_IDX14_MASK (0x30000000U) -#define PUF_IDXBLK_STATUS_IDX14_SHIFT (28U) -/*! IDX14 - Status block index 14 - */ -#define PUF_IDXBLK_STATUS_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX14_SHIFT)) & PUF_IDXBLK_STATUS_IDX14_MASK) - -#define PUF_IDXBLK_STATUS_IDX15_MASK (0xC0000000U) -#define PUF_IDXBLK_STATUS_IDX15_SHIFT (30U) -/*! IDX15 - Status block index 15 - */ -#define PUF_IDXBLK_STATUS_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX15_SHIFT)) & PUF_IDXBLK_STATUS_IDX15_MASK) -/*! @} */ - -/*! @name SHIFT_STATUS - */ -/*! @{ */ - -#define PUF_SHIFT_STATUS_KEY0_MASK (0xFU) -#define PUF_SHIFT_STATUS_KEY0_SHIFT (0U) -/*! KEY0 - Index counter from key 0 shift register - */ -#define PUF_SHIFT_STATUS_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY0_SHIFT)) & PUF_SHIFT_STATUS_KEY0_MASK) - -#define PUF_SHIFT_STATUS_KEY1_MASK (0xF0U) -#define PUF_SHIFT_STATUS_KEY1_SHIFT (4U) -/*! KEY1 - Index counter from key 1 shift register - */ -#define PUF_SHIFT_STATUS_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY1_SHIFT)) & PUF_SHIFT_STATUS_KEY1_MASK) - -#define PUF_SHIFT_STATUS_KEY2_MASK (0xF00U) -#define PUF_SHIFT_STATUS_KEY2_SHIFT (8U) -/*! KEY2 - Index counter from key 2 shift register - */ -#define PUF_SHIFT_STATUS_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY2_SHIFT)) & PUF_SHIFT_STATUS_KEY2_MASK) - -#define PUF_SHIFT_STATUS_KEY3_MASK (0xF000U) -#define PUF_SHIFT_STATUS_KEY3_SHIFT (12U) -/*! KEY3 - Index counter from key 3 shift register - */ -#define PUF_SHIFT_STATUS_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY3_SHIFT)) & PUF_SHIFT_STATUS_KEY3_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PUF_Register_Masks */ - - -/* PUF - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PUF base address */ - #define PUF_BASE (0x5003B000u) - /** Peripheral PUF base address */ - #define PUF_BASE_NS (0x4003B000u) - /** Peripheral PUF base pointer */ - #define PUF ((PUF_Type *)PUF_BASE) - /** Peripheral PUF base pointer */ - #define PUF_NS ((PUF_Type *)PUF_BASE_NS) - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS { PUF_BASE } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS { PUF } - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS_NS { PUF_BASE_NS } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS_NS { PUF_NS } -#else - /** Peripheral PUF base address */ - #define PUF_BASE (0x4003B000u) - /** Peripheral PUF base pointer */ - #define PUF ((PUF_Type *)PUF_BASE) - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS { PUF_BASE } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS { PUF } -#endif -/** Interrupt vectors for the PUF peripheral type */ -#define PUF_IRQS { PUF_IRQn } - -/*! - * @} - */ /* end of group PUF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PUF_SRAM_CTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_SRAM_CTRL_Peripheral_Access_Layer PUF_SRAM_CTRL Peripheral Access Layer - * @{ - */ - -/** PUF_SRAM_CTRL - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[768]; - __IO uint32_t CFG; /**< Configuration Register, offset: 0x300 */ - __I uint32_t STATUS; /**< Status Register, offset: 0x304 */ - uint8_t RESERVED_1[208]; - __O uint32_t INT_CLR_ENABLE; /**< Interrupt Enable Clear Register, offset: 0x3D8 */ - __O uint32_t INT_SET_ENABLE; /**< Interrupt Enable Set Register, offset: 0x3DC */ - __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x3E0 */ - __I uint32_t INT_ENABLE; /**< Interrupt Enable Register, offset: 0x3E4 */ - __O uint32_t INT_CLR_STATUS; /**< Interrupt Status Clear Register, offset: 0x3E8 */ - __O uint32_t INT_SET_STATUS; /**< Interrupt Status set, offset: 0x3EC */ -} PUF_SRAM_CTRL_Type; - -/* ---------------------------------------------------------------------------- - -- PUF_SRAM_CTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_SRAM_CTRL_Register_Masks PUF_SRAM_CTRL Register Masks - * @{ - */ - -/*! @name CFG - Configuration Register */ -/*! @{ */ - -#define PUF_SRAM_CTRL_CFG_ENABLE_MASK (0x1U) -#define PUF_SRAM_CTRL_CFG_ENABLE_SHIFT (0U) -/*! enable - PUF SRAM Controller activation - */ -#define PUF_SRAM_CTRL_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_CFG_ENABLE_SHIFT)) & PUF_SRAM_CTRL_CFG_ENABLE_MASK) - -#define PUF_SRAM_CTRL_CFG_CKGATING_MASK (0x4U) -#define PUF_SRAM_CTRL_CFG_CKGATING_SHIFT (2U) -/*! ckgating - PUF SRAM Clock Gating control - */ -#define PUF_SRAM_CTRL_CFG_CKGATING(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_CFG_CKGATING_SHIFT)) & PUF_SRAM_CTRL_CFG_CKGATING_MASK) -/*! @} */ - -/*! @name STATUS - Status Register */ -/*! @{ */ - -#define PUF_SRAM_CTRL_STATUS_READY_MASK (0x1U) -#define PUF_SRAM_CTRL_STATUS_READY_SHIFT (0U) -/*! READY - PUF SRAM Controller State - */ -#define PUF_SRAM_CTRL_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_STATUS_READY_SHIFT)) & PUF_SRAM_CTRL_STATUS_READY_MASK) -/*! @} */ - -/*! @name INT_CLR_ENABLE - Interrupt Enable Clear Register */ -/*! @{ */ - -#define PUF_SRAM_CTRL_INT_CLR_ENABLE_READY_MASK (0x1U) -#define PUF_SRAM_CTRL_INT_CLR_ENABLE_READY_SHIFT (0U) -/*! READY - READY Interrupt Enable clear - */ -#define PUF_SRAM_CTRL_INT_CLR_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_CLR_ENABLE_READY_SHIFT)) & PUF_SRAM_CTRL_INT_CLR_ENABLE_READY_MASK) - -#define PUF_SRAM_CTRL_INT_CLR_ENABLE_APB_ERR_MASK (0x2U) -#define PUF_SRAM_CTRL_INT_CLR_ENABLE_APB_ERR_SHIFT (1U) -/*! APB_ERR - APB_ERR Interrupt Enable clear - */ -#define PUF_SRAM_CTRL_INT_CLR_ENABLE_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_CLR_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_CTRL_INT_CLR_ENABLE_APB_ERR_MASK) -/*! @} */ - -/*! @name INT_SET_ENABLE - Interrupt Enable Set Register */ -/*! @{ */ - -#define PUF_SRAM_CTRL_INT_SET_ENABLE_READY_MASK (0x1U) -#define PUF_SRAM_CTRL_INT_SET_ENABLE_READY_SHIFT (0U) -/*! READY - READY Interrupt Enable set - */ -#define PUF_SRAM_CTRL_INT_SET_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_CTRL_INT_SET_ENABLE_READY_MASK) - -#define PUF_SRAM_CTRL_INT_SET_ENABLE_APB_ERR_MASK (0x2U) -#define PUF_SRAM_CTRL_INT_SET_ENABLE_APB_ERR_SHIFT (1U) -/*! APB_ERR - APB_ERR Interrupt Enable set - */ -#define PUF_SRAM_CTRL_INT_SET_ENABLE_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_SET_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_CTRL_INT_SET_ENABLE_APB_ERR_MASK) -/*! @} */ - -/*! @name INT_STATUS - Interrupt Status Register */ -/*! @{ */ - -#define PUF_SRAM_CTRL_INT_STATUS_READY_MASK (0x1U) -#define PUF_SRAM_CTRL_INT_STATUS_READY_SHIFT (0U) -/*! READY - READY Interrupt Status - */ -#define PUF_SRAM_CTRL_INT_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_STATUS_READY_SHIFT)) & PUF_SRAM_CTRL_INT_STATUS_READY_MASK) - -#define PUF_SRAM_CTRL_INT_STATUS_APB_ERR_MASK (0x2U) -#define PUF_SRAM_CTRL_INT_STATUS_APB_ERR_SHIFT (1U) -/*! APB_ERR - APB_ERR Interrupt Status - */ -#define PUF_SRAM_CTRL_INT_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_CTRL_INT_STATUS_APB_ERR_MASK) -/*! @} */ - -/*! @name INT_ENABLE - Interrupt Enable Register */ -/*! @{ */ - -#define PUF_SRAM_CTRL_INT_ENABLE_READY_MASK (0x1U) -#define PUF_SRAM_CTRL_INT_ENABLE_READY_SHIFT (0U) -/*! READY - READY Interrupt Enable - */ -#define PUF_SRAM_CTRL_INT_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_ENABLE_READY_SHIFT)) & PUF_SRAM_CTRL_INT_ENABLE_READY_MASK) - -#define PUF_SRAM_CTRL_INT_ENABLE_APB_ERR_MASK (0x2U) -#define PUF_SRAM_CTRL_INT_ENABLE_APB_ERR_SHIFT (1U) -/*! APB_ERR - APB_ERR Interrupt Enable - */ -#define PUF_SRAM_CTRL_INT_ENABLE_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_CTRL_INT_ENABLE_APB_ERR_MASK) -/*! @} */ - -/*! @name INT_CLR_STATUS - Interrupt Status Clear Register */ -/*! @{ */ - -#define PUF_SRAM_CTRL_INT_CLR_STATUS_READY_MASK (0x1U) -#define PUF_SRAM_CTRL_INT_CLR_STATUS_READY_SHIFT (0U) -/*! READY - READY Interrupt Status clear - */ -#define PUF_SRAM_CTRL_INT_CLR_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_CLR_STATUS_READY_SHIFT)) & PUF_SRAM_CTRL_INT_CLR_STATUS_READY_MASK) - -#define PUF_SRAM_CTRL_INT_CLR_STATUS_APB_ERR_MASK (0x2U) -#define PUF_SRAM_CTRL_INT_CLR_STATUS_APB_ERR_SHIFT (1U) -/*! APB_ERR - APB_ERR Interrupt Status Clear - */ -#define PUF_SRAM_CTRL_INT_CLR_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_CLR_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_CTRL_INT_CLR_STATUS_APB_ERR_MASK) -/*! @} */ - -/*! @name INT_SET_STATUS - Interrupt Status set */ -/*! @{ */ - -#define PUF_SRAM_CTRL_INT_SET_STATUS_READY_MASK (0x1U) -#define PUF_SRAM_CTRL_INT_SET_STATUS_READY_SHIFT (0U) -/*! READY - READY Interrupt Status set - */ -#define PUF_SRAM_CTRL_INT_SET_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_SET_STATUS_READY_SHIFT)) & PUF_SRAM_CTRL_INT_SET_STATUS_READY_MASK) - -#define PUF_SRAM_CTRL_INT_SET_STATUS_APB_ERR_MASK (0x2U) -#define PUF_SRAM_CTRL_INT_SET_STATUS_APB_ERR_SHIFT (1U) -/*! APB_ERR - APB_ERR Interrupt Status Set - */ -#define PUF_SRAM_CTRL_INT_SET_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_SET_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_CTRL_INT_SET_STATUS_APB_ERR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PUF_SRAM_CTRL_Register_Masks */ - - -/* PUF_SRAM_CTRL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PUF_SRAM_CTRL base address */ - #define PUF_SRAM_CTRL_BASE (0x5003B000u) - /** Peripheral PUF_SRAM_CTRL base address */ - #define PUF_SRAM_CTRL_BASE_NS (0x4003B000u) - /** Peripheral PUF_SRAM_CTRL base pointer */ - #define PUF_SRAM_CTRL ((PUF_SRAM_CTRL_Type *)PUF_SRAM_CTRL_BASE) - /** Peripheral PUF_SRAM_CTRL base pointer */ - #define PUF_SRAM_CTRL_NS ((PUF_SRAM_CTRL_Type *)PUF_SRAM_CTRL_BASE_NS) - /** Array initializer of PUF_SRAM_CTRL peripheral base addresses */ - #define PUF_SRAM_CTRL_BASE_ADDRS { PUF_SRAM_CTRL_BASE } - /** Array initializer of PUF_SRAM_CTRL peripheral base pointers */ - #define PUF_SRAM_CTRL_BASE_PTRS { PUF_SRAM_CTRL } - /** Array initializer of PUF_SRAM_CTRL peripheral base addresses */ - #define PUF_SRAM_CTRL_BASE_ADDRS_NS { PUF_SRAM_CTRL_BASE_NS } - /** Array initializer of PUF_SRAM_CTRL peripheral base pointers */ - #define PUF_SRAM_CTRL_BASE_PTRS_NS { PUF_SRAM_CTRL_NS } -#else - /** Peripheral PUF_SRAM_CTRL base address */ - #define PUF_SRAM_CTRL_BASE (0x4003B000u) - /** Peripheral PUF_SRAM_CTRL base pointer */ - #define PUF_SRAM_CTRL ((PUF_SRAM_CTRL_Type *)PUF_SRAM_CTRL_BASE) - /** Array initializer of PUF_SRAM_CTRL peripheral base addresses */ - #define PUF_SRAM_CTRL_BASE_ADDRS { PUF_SRAM_CTRL_BASE } - /** Array initializer of PUF_SRAM_CTRL peripheral base pointers */ - #define PUF_SRAM_CTRL_BASE_PTRS { PUF_SRAM_CTRL } -#endif - -/*! - * @} - */ /* end of group PUF_SRAM_CTRL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RNG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer - * @{ - */ - -/** RNG - Register Layout Typedef */ -typedef struct { - __I uint32_t RANDOM_NUMBER; /**< This register contains a random 32 bit number which is computed on demand, at each time it is read, offset: 0x0 */ - __IO uint32_t ENCRYPTED_NUMBER; /**< This register contains a random 32 bit number which is pre-computed, offset: 0x4 */ - __I uint32_t COUNTER_VAL; /**< , offset: 0x8 */ - __IO uint32_t COUNTER_CFG; /**< , offset: 0xC */ - __IO uint32_t ONLINE_TEST_CFG; /**< , offset: 0x10 */ - __I uint32_t ONLINE_TEST_VAL; /**< , offset: 0x14 */ - __IO uint32_t ENTROPY_INJECT; /**< , offset: 0x18 */ - __IO uint32_t MISC_CFG; /**< , offset: 0x1C */ - uint8_t RESERVED_0[4052]; - __IO uint32_t POWERDOWN; /**< Powerdown mode (standard but certainly useless here), offset: 0xFF4 */ - uint8_t RESERVED_1[4]; - __I uint32_t MODULEID; /**< IP identifier, offset: 0xFFC */ -} RNG_Type; - -/* ---------------------------------------------------------------------------- - -- RNG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RNG_Register_Masks RNG Register Masks - * @{ - */ - -/*! @name RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read */ -/*! @{ */ - -#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK (0xFFFFFFFFU) -#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT (0U) -/*! RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read. - */ -#define RNG_RANDOM_NUMBER_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT)) & RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK) -/*! @} */ - -/*! @name ENCRYPTED_NUMBER - This register contains a random 32 bit number which is pre-computed */ -/*! @{ */ - -#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_MASK (0xFFFFFFFFU) -#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_SHIFT (0U) -/*! ENCRYPTED_NUMBER - This register contains a random 32 bit number which is pre-computed. - */ -#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_SHIFT)) & RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_MASK) -/*! @} */ - -/*! @name COUNTER_VAL - */ -/*! @{ */ - -#define RNG_COUNTER_VAL_CLK_RATIO_MASK (0xFFU) -#define RNG_COUNTER_VAL_CLK_RATIO_SHIFT (0U) -/*! CLK_RATIO - Gives the ratio between the internal clocks frequencies and the register clock - * frequency for evaluation and certification purposes. - */ -#define RNG_COUNTER_VAL_CLK_RATIO(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_CLK_RATIO_SHIFT)) & RNG_COUNTER_VAL_CLK_RATIO_MASK) - -#define RNG_COUNTER_VAL_REFRESH_CNT_MASK (0x3FFF00U) -#define RNG_COUNTER_VAL_REFRESH_CNT_SHIFT (8U) -/*! REFRESH_CNT - Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER. - */ -#define RNG_COUNTER_VAL_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_REFRESH_CNT_SHIFT)) & RNG_COUNTER_VAL_REFRESH_CNT_MASK) -/*! @} */ - -/*! @name COUNTER_CFG - */ -/*! @{ */ - -#define RNG_COUNTER_CFG_MODE_MASK (0x3U) -#define RNG_COUNTER_CFG_MODE_SHIFT (0U) -/*! MODE - 00: disabled 01: update once. - */ -#define RNG_COUNTER_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_MODE_SHIFT)) & RNG_COUNTER_CFG_MODE_MASK) - -#define RNG_COUNTER_CFG_CLOCK_SEL_MASK (0x1CU) -#define RNG_COUNTER_CFG_CLOCK_SEL_SHIFT (2U) -/*! CLOCK_SEL - Selects the internal clock on which to compute statistics. - */ -#define RNG_COUNTER_CFG_CLOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_CLOCK_SEL_SHIFT)) & RNG_COUNTER_CFG_CLOCK_SEL_MASK) - -#define RNG_COUNTER_CFG_SHIFT4X_MASK (0xE0U) -#define RNG_COUNTER_CFG_SHIFT4X_SHIFT (5U) -/*! SHIFT4X - To be used to add precision to clock_ratio and determine 'entropy refill'. - */ -#define RNG_COUNTER_CFG_SHIFT4X(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_SHIFT4X_SHIFT)) & RNG_COUNTER_CFG_SHIFT4X_MASK) -/*! @} */ - -/*! @name ONLINE_TEST_CFG - */ -/*! @{ */ - -#define RNG_ONLINE_TEST_CFG_ACTIVATE_MASK (0x1U) -#define RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT (0U) -/*! ACTIVATE - 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER. - */ -#define RNG_ONLINE_TEST_CFG_ACTIVATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT)) & RNG_ONLINE_TEST_CFG_ACTIVATE_MASK) - -#define RNG_ONLINE_TEST_CFG_DATA_SEL_MASK (0x6U) -#define RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT (1U) -/*! DATA_SEL - Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one - * or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10: - * RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this - * field. - */ -#define RNG_ONLINE_TEST_CFG_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT)) & RNG_ONLINE_TEST_CFG_DATA_SEL_MASK) -/*! @} */ - -/*! @name ONLINE_TEST_VAL - */ -/*! @{ */ - -#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK (0xFU) -#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT (0U) -/*! LIVE_CHI_SQUARED - This value is updated as described in field 'activate'. - */ -#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK) - -#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK (0xF0U) -#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT (4U) -/*! MIN_CHI_SQUARED - This field is reset when 'activate'==0. - */ -#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) - -#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK (0xF00U) -#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT (8U) -/*! MAX_CHI_SQUARED - This field is reset when 'activate'==0. - */ -#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) -/*! @} */ - -/*! @name ENTROPY_INJECT - */ -/*! @{ */ - -#define RNG_ENTROPY_INJECT_ENTROPY_MASK (0xFFFFFFFFU) -#define RNG_ENTROPY_INJECT_ENTROPY_SHIFT (0U) -/*! ENTROPY - Use this register to inject or restore entropy 32 bits at a time. Writing is blocking - * thus see to it to have analog clocks activated. Injection can be usefull to add contribution - * from an external source of entropy, like for example LSBs of an ADC or of a temperature sensor. - * Restore can be usefull to store N random numbers in central memory before going powerdown - * then restore this entropy to RNG IP after power-up. It is useless to inject or restore more than - * 1*(number of RNGs) 32b words consecutively. Recommendation is to inject 1*(number of RNGs) - * words, and possibly later (2*32 clock cycles of slowest analog clock) inject again 1*(number of - * RNGs) words. Then maximum capacity of restoration is reached: about 44 bits per RNG (not to be - * mistaken with maximum capacity of entropy accumulation which is about 100 bits per RNG). You - * can inject less than 32 bits words (let unused bits to 0). Injection cannot degrade overall - * performance due to the fact that some internal PRNGs are excluded on purpose from this external - * action. - */ -#define RNG_ENTROPY_INJECT_ENTROPY(x) (((uint32_t)(((uint32_t)(x)) << RNG_ENTROPY_INJECT_ENTROPY_SHIFT)) & RNG_ENTROPY_INJECT_ENTROPY_MASK) -/*! @} */ - -/*! @name MISC_CFG - */ -/*! @{ */ - -#define RNG_MISC_CFG_AES_RESEED_MASK (0x1U) -#define RNG_MISC_CFG_AES_RESEED_SHIFT (0U) -/*! AES_RESEED - If set, ENCRYPTED_NUMBER generation becomes predictable, provided all secrets and - * current internal state are known: independant from entropy source. - */ -#define RNG_MISC_CFG_AES_RESEED(x) (((uint32_t)(((uint32_t)(x)) << RNG_MISC_CFG_AES_RESEED_SHIFT)) & RNG_MISC_CFG_AES_RESEED_MASK) - -#define RNG_MISC_CFG_AES_DT_CFG_MASK (0x2U) -#define RNG_MISC_CFG_AES_DT_CFG_SHIFT (1U) -/*! AES_DT_CFG - Set this bit to re-seed AES. - */ -#define RNG_MISC_CFG_AES_DT_CFG(x) (((uint32_t)(((uint32_t)(x)) << RNG_MISC_CFG_AES_DT_CFG_SHIFT)) & RNG_MISC_CFG_AES_DT_CFG_MASK) -/*! @} */ - -/*! @name POWERDOWN - Powerdown mode (standard but certainly useless here) */ -/*! @{ */ - -#define RNG_POWERDOWN_SOFT_RESET_MASK (0x1U) -#define RNG_POWERDOWN_SOFT_RESET_SHIFT (0U) -/*! SOFT_RESET - Request softreset that will go low automaticaly after acknowledge from CORE. - */ -#define RNG_POWERDOWN_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_SOFT_RESET_SHIFT)) & RNG_POWERDOWN_SOFT_RESET_MASK) - -#define RNG_POWERDOWN_FORCE_SOFT_RESET_MASK (0x2U) -#define RNG_POWERDOWN_FORCE_SOFT_RESET_SHIFT (1U) -/*! FORCE_SOFT_RESET - When used with softreset it forces CORE_RESETN to low on acknowledge from CORE. - */ -#define RNG_POWERDOWN_FORCE_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_FORCE_SOFT_RESET_SHIFT)) & RNG_POWERDOWN_FORCE_SOFT_RESET_MASK) - -#define RNG_POWERDOWN_POWERDOWN_MASK (0x80000000U) -#define RNG_POWERDOWN_POWERDOWN_SHIFT (31U) -/*! POWERDOWN - When set all accesses to standard registers are blocked. - */ -#define RNG_POWERDOWN_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_POWERDOWN_SHIFT)) & RNG_POWERDOWN_POWERDOWN_MASK) -/*! @} */ - -/*! @name MODULEID - IP identifier */ -/*! @{ */ - -#define RNG_MODULEID_APERTURE_MASK (0xFFU) -#define RNG_MODULEID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture i. - */ -#define RNG_MODULEID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_APERTURE_SHIFT)) & RNG_MODULEID_APERTURE_MASK) - -#define RNG_MODULEID_MIN_REV_MASK (0xF00U) -#define RNG_MODULEID_MIN_REV_SHIFT (8U) -/*! MIN_REV - Minor revision i. - */ -#define RNG_MODULEID_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MIN_REV_SHIFT)) & RNG_MODULEID_MIN_REV_MASK) - -#define RNG_MODULEID_MAJ_REV_MASK (0xF000U) -#define RNG_MODULEID_MAJ_REV_SHIFT (12U) -/*! MAJ_REV - Major revision i. - */ -#define RNG_MODULEID_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MAJ_REV_SHIFT)) & RNG_MODULEID_MAJ_REV_MASK) - -#define RNG_MODULEID_ID_MASK (0xFFFF0000U) -#define RNG_MODULEID_ID_SHIFT (16U) -/*! ID - Identifier. - */ -#define RNG_MODULEID_ID(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_ID_SHIFT)) & RNG_MODULEID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group RNG_Register_Masks */ - - -/* RNG - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral RNG base address */ - #define RNG_BASE (0x5003A000u) - /** Peripheral RNG base address */ - #define RNG_BASE_NS (0x4003A000u) - /** Peripheral RNG base pointer */ - #define RNG ((RNG_Type *)RNG_BASE) - /** Peripheral RNG base pointer */ - #define RNG_NS ((RNG_Type *)RNG_BASE_NS) - /** Array initializer of RNG peripheral base addresses */ - #define RNG_BASE_ADDRS { RNG_BASE } - /** Array initializer of RNG peripheral base pointers */ - #define RNG_BASE_PTRS { RNG } - /** Array initializer of RNG peripheral base addresses */ - #define RNG_BASE_ADDRS_NS { RNG_BASE_NS } - /** Array initializer of RNG peripheral base pointers */ - #define RNG_BASE_PTRS_NS { RNG_NS } -#else - /** Peripheral RNG base address */ - #define RNG_BASE (0x4003A000u) - /** Peripheral RNG base pointer */ - #define RNG ((RNG_Type *)RNG_BASE) - /** Array initializer of RNG peripheral base addresses */ - #define RNG_BASE_ADDRS { RNG_BASE } - /** Array initializer of RNG peripheral base pointers */ - #define RNG_BASE_PTRS { RNG } -#endif - -/*! - * @} - */ /* end of group RNG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RTC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer - * @{ - */ - -/** RTC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ - __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ - __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ - __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ - __I uint32_t SUBSEC; /**< Sub-second counter register, offset: 0x10 */ - uint8_t RESERVED_0[44]; - __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */ -} RTC_Type; - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/*! @name CTRL - RTC control register */ -/*! @{ */ - -#define RTC_CTRL_SWRESET_MASK (0x1U) -#define RTC_CTRL_SWRESET_SHIFT (0U) -/*! SWRESET - Software reset control - * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. - * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value - * except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes - * to set any of the other bits within this register. Do not attempt to write to any bits of this register at - * the same time that the reset bit is being cleared. - */ -#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) - -#define RTC_CTRL_ALARM1HZ_MASK (0x4U) -#define RTC_CTRL_ALARM1HZ_SHIFT (2U) -/*! ALARM1HZ - RTC 1 Hz timer alarm flag status. - * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. - * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt - * request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. - */ -#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) - -#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) -#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) -/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status. - * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. - * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up - * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. - */ -#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) - -#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) -#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) -/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. - * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. - */ -#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) - -#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) -#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) -/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. - * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. - */ -#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) - -#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) -#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) -/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz - * timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). - * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. The 1 kHz RTC timer is enabled. - */ -#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) - -#define RTC_CTRL_RTC_EN_MASK (0x80U) -#define RTC_CTRL_RTC_EN_SHIFT (7U) -/*! RTC_EN - RTC enable. - * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should - * be 0 when writing to load a value in the RTC counter register. - * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate - * operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the - * high-resolution, 1 kHz clock, set bit 6 in this register. - */ -#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) - -#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) -#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) -/*! RTC_OSC_PD - RTC oscillator power-down control. - * 0b0..See RTC_OSC_BYPASS - * 0b1..RTC oscillator is powered-down. - */ -#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) - -#define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) -#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) -/*! RTC_OSC_BYPASS - RTC oscillator bypass control. - * 0b0..The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. - * 0b1..The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. - */ -#define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) - -#define RTC_CTRL_RTC_SUBSEC_ENA_MASK (0x400U) -#define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT (10U) -/*! RTC_SUBSEC_ENA - RTC Sub-second counter control. - * 0b0..The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD - * reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second - * counter, this bit will always read-back as a '0'. - * 0b1..The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first - * one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is - * set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip - * exits deep power-down mode. - */ -#define RTC_CTRL_RTC_SUBSEC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK) -/*! @} */ - -/*! @name MATCH - RTC match register */ -/*! @{ */ - -#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) -#define RTC_MATCH_MATVAL_SHIFT (0U) -/*! MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the - * alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. - */ -#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) -/*! @} */ - -/*! @name COUNT - RTC counter register */ -/*! @{ */ - -#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) -#define RTC_COUNT_VAL_SHIFT (0U) -/*! VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial - * value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC - * Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this - * register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after - * the RTC_EN bit is set. - */ -#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) -/*! @} */ - -/*! @name WAKE - High-resolution/wake-up timer control register */ -/*! @{ */ - -#define RTC_WAKE_VAL_MASK (0xFFFFU) -#define RTC_WAKE_VAL_SHIFT (0U) -/*! VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads - * a start count value into the wake-up timer and initializes a count-down sequence. Do not write - * to this register while counting is in progress. - */ -#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) -/*! @} */ - -/*! @name SUBSEC - Sub-second counter register */ -/*! @{ */ - -#define RTC_SUBSEC_SUBSEC_MASK (0x7FFFU) -#define RTC_SUBSEC_SUBSEC_SHIFT (0U) -/*! SUBSEC - A read reflects the current value of the 32KHz sub-second counter. This counter is - * cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz - * rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This - * counter must be re-enabled after exiting deep power-down mode or after the main RTC module is - * disabled and re-enabled. On modules not equipped with a sub-second counter, this register - * will read-back as all zeroes. - */ -#define RTC_SUBSEC_SUBSEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_SUBSEC_SHIFT)) & RTC_SUBSEC_SUBSEC_MASK) -/*! @} */ - -/*! @name GPREG - General Purpose register */ -/*! @{ */ - -#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU) -#define RTC_GPREG_GPDATA_SHIFT (0U) -/*! GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied. - */ -#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK) -/*! @} */ - -/* The count of RTC_GPREG */ -#define RTC_GPREG_COUNT (8U) - - -/*! - * @} - */ /* end of group RTC_Register_Masks */ - - -/* RTC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral RTC base address */ - #define RTC_BASE (0x5002C000u) - /** Peripheral RTC base address */ - #define RTC_BASE_NS (0x4002C000u) - /** Peripheral RTC base pointer */ - #define RTC ((RTC_Type *)RTC_BASE) - /** Peripheral RTC base pointer */ - #define RTC_NS ((RTC_Type *)RTC_BASE_NS) - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS { RTC_BASE } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS { RTC } - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS_NS { RTC_BASE_NS } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS_NS { RTC_NS } -#else - /** Peripheral RTC base address */ - #define RTC_BASE (0x4002C000u) - /** Peripheral RTC base pointer */ - #define RTC ((RTC_Type *)RTC_BASE) - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS { RTC_BASE } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS { RTC } -#endif -/** Interrupt vectors for the RTC peripheral type */ -#define RTC_IRQS { RTC_IRQn } - -/*! - * @} - */ /* end of group RTC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SCT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer - * @{ - */ - -/** SCT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ - union { /* offset: 0x4 */ - struct { /* offset: 0x4 */ - __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */ - __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */ - } CTRL_ACCESS16BIT; - __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ - }; - union { /* offset: 0x8 */ - struct { /* offset: 0x8 */ - __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */ - __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */ - } LIMIT_ACCESS16BIT; - __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ - }; - union { /* offset: 0xC */ - struct { /* offset: 0xC */ - __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */ - __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */ - } HALT_ACCESS16BIT; - __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ - }; - union { /* offset: 0x10 */ - struct { /* offset: 0x10 */ - __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */ - __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */ - } STOP_ACCESS16BIT; - __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ - }; - union { /* offset: 0x14 */ - struct { /* offset: 0x14 */ - __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */ - __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */ - } START_ACCESS16BIT; - __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ - }; - uint8_t RESERVED_0[40]; - union { /* offset: 0x40 */ - struct { /* offset: 0x40 */ - __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */ - __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */ - } COUNT_ACCESS16BIT; - __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ - }; - union { /* offset: 0x44 */ - struct { /* offset: 0x44 */ - __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */ - __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */ - } STATE_ACCESS16BIT; - __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ - }; - __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ - union { /* offset: 0x4C */ - struct { /* offset: 0x4C */ - __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */ - __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */ - } REGMODE_ACCESS16BIT; - __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ - }; - __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ - __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ - __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ - __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */ - __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */ - uint8_t RESERVED_1[140]; - __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ - __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ - __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ - __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ - union { /* offset: 0x100 */ - union { /* offset: 0x100, array step: 0x4 */ - struct { /* offset: 0x100, array step: 0x4 */ - __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */ - __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */ - } CAP_ACCESS16BIT[16]; - __IO uint32_t CAP[16]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ - }; - union { /* offset: 0x100, array step: 0x4 */ - struct { /* offset: 0x100, array step: 0x4 */ - __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */ - __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */ - } MATCH_ACCESS16BIT[16]; - __IO uint32_t MATCH[16]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ - }; - }; - uint8_t RESERVED_2[192]; - union { /* offset: 0x200 */ - union { /* offset: 0x200, array step: 0x4 */ - struct { /* offset: 0x200, array step: 0x4 */ - __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */ - __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */ - } CAPCTRL_ACCESS16BIT[16]; - __IO uint32_t CAPCTRL[16]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ - }; - union { /* offset: 0x200, array step: 0x4 */ - struct { /* offset: 0x200, array step: 0x4 */ - __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */ - __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */ - } MATCHREL_ACCESS16BIT[16]; - __IO uint32_t MATCHREL[16]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ - }; - }; - uint8_t RESERVED_3[192]; - struct { /* offset: 0x300, array step: 0x8 */ - __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ - __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ - } EV[16]; - uint8_t RESERVED_4[384]; - struct { /* offset: 0x500, array step: 0x8 */ - __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ - __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ - } OUT[10]; -} SCT_Type; - -/* ---------------------------------------------------------------------------- - -- SCT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Register_Masks SCT Register Masks - * @{ - */ - -/*! @name CONFIG - SCT configuration register */ -/*! @{ */ - -#define SCT_CONFIG_UNIFY_MASK (0x1U) -#define SCT_CONFIG_UNIFY_SHIFT (0U) -/*! UNIFY - SCT operation - * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. - * 0b1..The SCT operates as a unified 32-bit counter. - */ -#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) - -#define SCT_CONFIG_CLKMODE_MASK (0x6U) -#define SCT_CONFIG_CLKMODE_SHIFT (1U) -/*! CLKMODE - SCT clock mode - * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. - * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are - * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The - * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the - * high-performance, sampled-clock mode. - * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the - * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the - * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. - * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL - * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system - * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than - * the system clock. - */ -#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) - -#define SCT_CONFIG_CKSEL_MASK (0x78U) -#define SCT_CONFIG_CKSEL_SHIFT (3U) -/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent - * on the CLKMODE bit selection in this register. - * 0b0000..Rising edges on input 0. - * 0b0001..Falling edges on input 0. - * 0b0010..Rising edges on input 1. - * 0b0011..Falling edges on input 1. - * 0b0100..Rising edges on input 2. - * 0b0101..Falling edges on input 2. - * 0b0110..Rising edges on input 3. - * 0b0111..Falling edges on input 3. - * 0b1000..Rising edges on input 4. - * 0b1001..Falling edges on input 4. - * 0b1010..Rising edges on input 5. - * 0b1011..Falling edges on input 5. - * 0b1100..Rising edges on input 6. - * 0b1101..Falling edges on input 6. - * 0b1110..Rising edges on input 7. - * 0b1111..Falling edges on input 7. - */ -#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) - -#define SCT_CONFIG_NORELOAD_L_MASK (0x80U) -#define SCT_CONFIG_NORELOAD_L_SHIFT (7U) -/*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their - * respective reload registers. Setting this bit eliminates the need to write to the reload - * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any - * time. This bit applies to both the higher and lower registers when the UNIFY bit is set. - */ -#define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK) - -#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) -#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) -/*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their - * respective reload registers. Setting this bit eliminates the need to write to the reload - * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at - * any time. This bit is not used when the UNIFY bit is set. - */ -#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) - -#define SCT_CONFIG_INSYNC_MASK (0x1E00U) -#define SCT_CONFIG_INSYNC_SHIFT (9U) -/*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all - * other bits are reserved. A 1 in one of these bits subjects the corresponding input to - * synchronization to the SCT clock, before it is used to create an event. If an input is known to - * already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: - * The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input - * clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. - * It does not apply to the clock input specified in the CKSEL field. - */ -#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) - -#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) -#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) -/*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto - * LIMIT condition without the need to define an associated event. As with any LIMIT event, this - * automatic limit causes the counter to be cleared to zero in unidirectional mode or to change - * the direction of count in bi-directional mode. Software can write to set or clear this bit at - * any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. - */ -#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) - -#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) -#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) -/*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a - * de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, - * this automatic limit causes the counter to be cleared to zero in unidirectional mode or to - * change the direction of count in bi-directional mode. Software can write to set or clear this bit - * at any time. This bit is not used when the UNIFY bit is set. - */ -#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) -/*! @} */ - -/*! @name CTRLL - SCT_CTRLL register */ -/*! @{ */ - -#define SCT_CTRLL_DOWN_L_MASK (0x1U) -#define SCT_CTRLL_DOWN_L_SHIFT (0U) -/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit - * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit - * when the counter is counting down and a limit condition occurs or when the counter reaches 0. - */ -#define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK) - -#define SCT_CTRLL_STOP_L_MASK (0x2U) -#define SCT_CTRLL_STOP_L_SHIFT (1U) -/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events - * related to the counter can occur. If a designated start event occurs, this bit is cleared and - * counting resumes. - */ -#define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK) - -#define SCT_CTRLL_HALT_L_MASK (0x4U) -#define SCT_CTRLL_HALT_L_SHIFT (2U) -/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A - * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to - * remove the halt condition while keeping the SCT in the stop condition (not running) with a - * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, - * only software can clear this bit to restore counter operation. This bit is set on reset. - */ -#define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK) - -#define SCT_CTRLL_CLRCTR_L_MASK (0x8U) -#define SCT_CTRLL_CLRCTR_L_SHIFT (3U) -/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. - */ -#define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK) - -#define SCT_CTRLL_BIDIR_L_MASK (0x10U) -#define SCT_CTRLL_BIDIR_L_SHIFT (4U) -/*! BIDIR_L - L or unified counter direction select - * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. - * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK) - -#define SCT_CTRLL_PRE_L_MASK (0x1FE0U) -#define SCT_CTRLL_PRE_L_SHIFT (5U) -/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified - * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. - * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - */ -#define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK) -/*! @} */ - -/*! @name CTRLH - SCT_CTRLH register */ -/*! @{ */ - -#define SCT_CTRLH_DOWN_H_MASK (0x1U) -#define SCT_CTRLH_DOWN_H_SHIFT (0U) -/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the - * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit - * when the counter is counting down and a limit condition occurs or when the counter reaches 0. - */ -#define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK) - -#define SCT_CTRLH_STOP_H_MASK (0x2U) -#define SCT_CTRLH_STOP_H_SHIFT (1U) -/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to - * the counter can occur. If such an event matches the mask in the Start register, this bit is - * cleared and counting resumes. - */ -#define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK) - -#define SCT_CTRLH_HALT_H_MASK (0x4U) -#define SCT_CTRLH_HALT_H_SHIFT (2U) -/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets - * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the - * halt condition while keeping the SCT in the stop condition (not running) with a single write to - * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit - * can only be cleared by software to restore counter operation. This bit is set on reset. - */ -#define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK) - -#define SCT_CTRLH_CLRCTR_H_MASK (0x8U) -#define SCT_CTRLH_CLRCTR_H_SHIFT (3U) -/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. - */ -#define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK) - -#define SCT_CTRLH_BIDIR_H_MASK (0x10U) -#define SCT_CTRLH_BIDIR_H_SHIFT (4U) -/*! BIDIR_H - Direction select - * 0b0..The H counter counts up to its limit condition, then is cleared to zero. - * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK) - -#define SCT_CTRLH_PRE_H_MASK (0x1FE0U) -#define SCT_CTRLH_PRE_H_SHIFT (5U) -/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. - * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the - * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - */ -#define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK) -/*! @} */ - -/*! @name CTRL - SCT control register */ -/*! @{ */ - -#define SCT_CTRL_DOWN_L_MASK (0x1U) -#define SCT_CTRL_DOWN_L_SHIFT (0U) -/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit - * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit - * when the counter is counting down and a limit condition occurs or when the counter reaches 0. - */ -#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) - -#define SCT_CTRL_STOP_L_MASK (0x2U) -#define SCT_CTRL_STOP_L_SHIFT (1U) -/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events - * related to the counter can occur. If a designated start event occurs, this bit is cleared and - * counting resumes. - */ -#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) - -#define SCT_CTRL_HALT_L_MASK (0x4U) -#define SCT_CTRL_HALT_L_SHIFT (2U) -/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A - * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to - * remove the halt condition while keeping the SCT in the stop condition (not running) with a - * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, - * only software can clear this bit to restore counter operation. This bit is set on reset. - */ -#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) - -#define SCT_CTRL_CLRCTR_L_MASK (0x8U) -#define SCT_CTRL_CLRCTR_L_SHIFT (3U) -/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. - */ -#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) - -#define SCT_CTRL_BIDIR_L_MASK (0x10U) -#define SCT_CTRL_BIDIR_L_SHIFT (4U) -/*! BIDIR_L - L or unified counter direction select - * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. - * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) - -#define SCT_CTRL_PRE_L_MASK (0x1FE0U) -#define SCT_CTRL_PRE_L_SHIFT (5U) -/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified - * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. - * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - */ -#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) - -#define SCT_CTRL_DOWN_H_MASK (0x10000U) -#define SCT_CTRL_DOWN_H_SHIFT (16U) -/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the - * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit - * when the counter is counting down and a limit condition occurs or when the counter reaches 0. - */ -#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) - -#define SCT_CTRL_STOP_H_MASK (0x20000U) -#define SCT_CTRL_STOP_H_SHIFT (17U) -/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to - * the counter can occur. If such an event matches the mask in the Start register, this bit is - * cleared and counting resumes. - */ -#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) - -#define SCT_CTRL_HALT_H_MASK (0x40000U) -#define SCT_CTRL_HALT_H_SHIFT (18U) -/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets - * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the - * halt condition while keeping the SCT in the stop condition (not running) with a single write to - * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit - * can only be cleared by software to restore counter operation. This bit is set on reset. - */ -#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) - -#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) -#define SCT_CTRL_CLRCTR_H_SHIFT (19U) -/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. - */ -#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) - -#define SCT_CTRL_BIDIR_H_MASK (0x100000U) -#define SCT_CTRL_BIDIR_H_SHIFT (20U) -/*! BIDIR_H - Direction select - * 0b0..The H counter counts up to its limit condition, then is cleared to zero. - * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) - -#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) -#define SCT_CTRL_PRE_H_SHIFT (21U) -/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. - * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the - * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - */ -#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) -/*! @} */ - -/*! @name LIMITL - SCT_LIMITL register */ -/*! @{ */ - -#define SCT_LIMITL_LIMITL_MASK (0xFFFFU) -#define SCT_LIMITL_LIMITL_SHIFT (0U) -#define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK) -/*! @} */ - -/*! @name LIMITH - SCT_LIMITH register */ -/*! @{ */ - -#define SCT_LIMITH_LIMITH_MASK (0xFFFFU) -#define SCT_LIMITH_LIMITH_SHIFT (0U) -#define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK) -/*! @} */ - -/*! @name LIMIT - SCT limit event select register */ -/*! @{ */ - -#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) -#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) -/*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter - * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) - -#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) -#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) -/*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit - * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) -/*! @} */ - -/*! @name HALTL - SCT_HALTL register */ -/*! @{ */ - -#define SCT_HALTL_HALTL_MASK (0xFFFFU) -#define SCT_HALTL_HALTL_SHIFT (0U) -#define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK) -/*! @} */ - -/*! @name HALTH - SCT_HALTH register */ -/*! @{ */ - -#define SCT_HALTH_HALTH_MASK (0xFFFFU) -#define SCT_HALTH_HALTH_SHIFT (0U) -#define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK) -/*! @} */ - -/*! @name HALT - SCT halt event select register */ -/*! @{ */ - -#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) -#define SCT_HALT_HALTMSK_L_SHIFT (0U) -/*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, - * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) - -#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) -#define SCT_HALT_HALTMSK_H_SHIFT (16U) -/*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, - * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) -/*! @} */ - -/*! @name STOPL - SCT_STOPL register */ -/*! @{ */ - -#define SCT_STOPL_STOPL_MASK (0xFFFFU) -#define SCT_STOPL_STOPL_SHIFT (0U) -#define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK) -/*! @} */ - -/*! @name STOPH - SCT_STOPH register */ -/*! @{ */ - -#define SCT_STOPH_STOPH_MASK (0xFFFFU) -#define SCT_STOPH_STOPH_SHIFT (0U) -#define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK) -/*! @} */ - -/*! @name STOP - SCT stop event select register */ -/*! @{ */ - -#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) -#define SCT_STOP_STOPMSK_L_SHIFT (0U) -/*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, - * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) - -#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) -#define SCT_STOP_STOPMSK_H_SHIFT (16U) -/*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, - * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) -/*! @} */ - -/*! @name STARTL - SCT_STARTL register */ -/*! @{ */ - -#define SCT_STARTL_STARTL_MASK (0xFFFFU) -#define SCT_STARTL_STARTL_SHIFT (0U) -#define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK) -/*! @} */ - -/*! @name STARTH - SCT_STARTH register */ -/*! @{ */ - -#define SCT_STARTH_STARTH_MASK (0xFFFFU) -#define SCT_STARTH_STARTH_SHIFT (0U) -#define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK) -/*! @} */ - -/*! @name START - SCT start event select register */ -/*! @{ */ - -#define SCT_START_STARTMSK_L_MASK (0xFFFFU) -#define SCT_START_STARTMSK_L_SHIFT (0U) -/*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit - * 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) - -#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) -#define SCT_START_STARTMSK_H_SHIFT (16U) -/*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit - * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) -/*! @} */ - -/*! @name COUNTL - SCT_COUNTL register */ -/*! @{ */ - -#define SCT_COUNTL_COUNTL_MASK (0xFFFFU) -#define SCT_COUNTL_COUNTL_SHIFT (0U) -#define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK) -/*! @} */ - -/*! @name COUNTH - SCT_COUNTH register */ -/*! @{ */ - -#define SCT_COUNTH_COUNTH_MASK (0xFFFFU) -#define SCT_COUNTH_COUNTH_SHIFT (0U) -#define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK) -/*! @} */ - -/*! @name COUNT - SCT counter register */ -/*! @{ */ - -#define SCT_COUNT_CTR_L_MASK (0xFFFFU) -#define SCT_COUNT_CTR_L_SHIFT (0U) -/*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write - * the lower 16 bits of the 32-bit unified counter. - */ -#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) - -#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) -#define SCT_COUNT_CTR_H_SHIFT (16U) -/*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write - * the upper 16 bits of the 32-bit unified counter. - */ -#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) -/*! @} */ - -/*! @name STATEL - SCT_STATEL register */ -/*! @{ */ - -#define SCT_STATEL_STATEL_MASK (0xFFFFU) -#define SCT_STATEL_STATEL_SHIFT (0U) -#define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK) -/*! @} */ - -/*! @name STATEH - SCT_STATEH register */ -/*! @{ */ - -#define SCT_STATEH_STATEH_MASK (0xFFFFU) -#define SCT_STATEH_STATEH_SHIFT (0U) -#define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK) -/*! @} */ - -/*! @name STATE - SCT state register */ -/*! @{ */ - -#define SCT_STATE_STATE_L_MASK (0x1FU) -#define SCT_STATE_STATE_L_SHIFT (0U) -/*! STATE_L - State variable. - */ -#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) - -#define SCT_STATE_STATE_H_MASK (0x1F0000U) -#define SCT_STATE_STATE_H_SHIFT (16U) -/*! STATE_H - State variable. - */ -#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) -/*! @} */ - -/*! @name INPUT - SCT input register */ -/*! @{ */ - -#define SCT_INPUT_AIN0_MASK (0x1U) -#define SCT_INPUT_AIN0_SHIFT (0U) -/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) - -#define SCT_INPUT_AIN1_MASK (0x2U) -#define SCT_INPUT_AIN1_SHIFT (1U) -/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) - -#define SCT_INPUT_AIN2_MASK (0x4U) -#define SCT_INPUT_AIN2_SHIFT (2U) -/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) - -#define SCT_INPUT_AIN3_MASK (0x8U) -#define SCT_INPUT_AIN3_SHIFT (3U) -/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) - -#define SCT_INPUT_AIN4_MASK (0x10U) -#define SCT_INPUT_AIN4_SHIFT (4U) -/*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) - -#define SCT_INPUT_AIN5_MASK (0x20U) -#define SCT_INPUT_AIN5_SHIFT (5U) -/*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) - -#define SCT_INPUT_AIN6_MASK (0x40U) -#define SCT_INPUT_AIN6_SHIFT (6U) -/*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) - -#define SCT_INPUT_AIN7_MASK (0x80U) -#define SCT_INPUT_AIN7_SHIFT (7U) -/*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) - -#define SCT_INPUT_AIN8_MASK (0x100U) -#define SCT_INPUT_AIN8_SHIFT (8U) -/*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) - -#define SCT_INPUT_AIN9_MASK (0x200U) -#define SCT_INPUT_AIN9_SHIFT (9U) -/*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) - -#define SCT_INPUT_AIN10_MASK (0x400U) -#define SCT_INPUT_AIN10_SHIFT (10U) -/*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) - -#define SCT_INPUT_AIN11_MASK (0x800U) -#define SCT_INPUT_AIN11_SHIFT (11U) -/*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) - -#define SCT_INPUT_AIN12_MASK (0x1000U) -#define SCT_INPUT_AIN12_SHIFT (12U) -/*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) - -#define SCT_INPUT_AIN13_MASK (0x2000U) -#define SCT_INPUT_AIN13_SHIFT (13U) -/*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) - -#define SCT_INPUT_AIN14_MASK (0x4000U) -#define SCT_INPUT_AIN14_SHIFT (14U) -/*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) - -#define SCT_INPUT_AIN15_MASK (0x8000U) -#define SCT_INPUT_AIN15_SHIFT (15U) -/*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) - -#define SCT_INPUT_SIN0_MASK (0x10000U) -#define SCT_INPUT_SIN0_SHIFT (16U) -/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) - -#define SCT_INPUT_SIN1_MASK (0x20000U) -#define SCT_INPUT_SIN1_SHIFT (17U) -/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) - -#define SCT_INPUT_SIN2_MASK (0x40000U) -#define SCT_INPUT_SIN2_SHIFT (18U) -/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) - -#define SCT_INPUT_SIN3_MASK (0x80000U) -#define SCT_INPUT_SIN3_SHIFT (19U) -/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) - -#define SCT_INPUT_SIN4_MASK (0x100000U) -#define SCT_INPUT_SIN4_SHIFT (20U) -/*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) - -#define SCT_INPUT_SIN5_MASK (0x200000U) -#define SCT_INPUT_SIN5_SHIFT (21U) -/*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) - -#define SCT_INPUT_SIN6_MASK (0x400000U) -#define SCT_INPUT_SIN6_SHIFT (22U) -/*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) - -#define SCT_INPUT_SIN7_MASK (0x800000U) -#define SCT_INPUT_SIN7_SHIFT (23U) -/*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) - -#define SCT_INPUT_SIN8_MASK (0x1000000U) -#define SCT_INPUT_SIN8_SHIFT (24U) -/*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) - -#define SCT_INPUT_SIN9_MASK (0x2000000U) -#define SCT_INPUT_SIN9_SHIFT (25U) -/*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) - -#define SCT_INPUT_SIN10_MASK (0x4000000U) -#define SCT_INPUT_SIN10_SHIFT (26U) -/*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) - -#define SCT_INPUT_SIN11_MASK (0x8000000U) -#define SCT_INPUT_SIN11_SHIFT (27U) -/*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) - -#define SCT_INPUT_SIN12_MASK (0x10000000U) -#define SCT_INPUT_SIN12_SHIFT (28U) -/*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) - -#define SCT_INPUT_SIN13_MASK (0x20000000U) -#define SCT_INPUT_SIN13_SHIFT (29U) -/*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) - -#define SCT_INPUT_SIN14_MASK (0x40000000U) -#define SCT_INPUT_SIN14_SHIFT (30U) -/*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) - -#define SCT_INPUT_SIN15_MASK (0x80000000U) -#define SCT_INPUT_SIN15_SHIFT (31U) -/*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) -/*! @} */ - -/*! @name REGMODEL - SCT_REGMODEL register */ -/*! @{ */ - -#define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU) -#define SCT_REGMODEL_REGMODEL_SHIFT (0U) -#define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK) -/*! @} */ - -/*! @name REGMODEH - SCT_REGMODEH register */ -/*! @{ */ - -#define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU) -#define SCT_REGMODEH_REGMODEH_SHIFT (0U) -#define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK) -/*! @} */ - -/*! @name REGMODE - SCT match/capture mode register */ -/*! @{ */ - -#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) -#define SCT_REGMODE_REGMOD_L_SHIFT (0U) -/*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, - * etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as - * match register. 1 = register operates as capture register. - */ -#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) - -#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) -#define SCT_REGMODE_REGMOD_H_SHIFT (16U) -/*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit - * 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as - * match registers. 1 = register operates as capture registers. - */ -#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) -/*! @} */ - -/*! @name OUTPUT - SCT output register */ -/*! @{ */ - -#define SCT_OUTPUT_OUT_MASK (0xFFFFU) -#define SCT_OUTPUT_OUT_SHIFT (0U) -/*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the - * corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of - * outputs in this SCT. - */ -#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) -/*! @} */ - -/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ -/*! @{ */ - -#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) -#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) -/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) -#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) -/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) -#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) -/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) -#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) -/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) -#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) -/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) -#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) -/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) -#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) -/*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) -#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) -/*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) -#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) -/*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) -#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) -/*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) -#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) -/*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) -#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) -/*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) -/*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) -/*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) -/*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) -/*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) -/*! @} */ - -/*! @name RES - SCT conflict resolution register */ -/*! @{ */ - -#define SCT_RES_O0RES_MASK (0x3U) -#define SCT_RES_O0RES_SHIFT (0U) -/*! O0RES - Effect of simultaneous set and clear on output 0. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR0 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) - -#define SCT_RES_O1RES_MASK (0xCU) -#define SCT_RES_O1RES_SHIFT (2U) -/*! O1RES - Effect of simultaneous set and clear on output 1. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR1 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) - -#define SCT_RES_O2RES_MASK (0x30U) -#define SCT_RES_O2RES_SHIFT (4U) -/*! O2RES - Effect of simultaneous set and clear on output 2. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output n (or set based on the SETCLR2 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) - -#define SCT_RES_O3RES_MASK (0xC0U) -#define SCT_RES_O3RES_SHIFT (6U) -/*! O3RES - Effect of simultaneous set and clear on output 3. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR3 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) - -#define SCT_RES_O4RES_MASK (0x300U) -#define SCT_RES_O4RES_SHIFT (8U) -/*! O4RES - Effect of simultaneous set and clear on output 4. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR4 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) - -#define SCT_RES_O5RES_MASK (0xC00U) -#define SCT_RES_O5RES_SHIFT (10U) -/*! O5RES - Effect of simultaneous set and clear on output 5. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR5 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) - -#define SCT_RES_O6RES_MASK (0x3000U) -#define SCT_RES_O6RES_SHIFT (12U) -/*! O6RES - Effect of simultaneous set and clear on output 6. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR6 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) - -#define SCT_RES_O7RES_MASK (0xC000U) -#define SCT_RES_O7RES_SHIFT (14U) -/*! O7RES - Effect of simultaneous set and clear on output 7. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output n (or set based on the SETCLR7 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) - -#define SCT_RES_O8RES_MASK (0x30000U) -#define SCT_RES_O8RES_SHIFT (16U) -/*! O8RES - Effect of simultaneous set and clear on output 8. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR8 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) - -#define SCT_RES_O9RES_MASK (0xC0000U) -#define SCT_RES_O9RES_SHIFT (18U) -/*! O9RES - Effect of simultaneous set and clear on output 9. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR9 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) - -#define SCT_RES_O10RES_MASK (0x300000U) -#define SCT_RES_O10RES_SHIFT (20U) -/*! O10RES - Effect of simultaneous set and clear on output 10. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR10 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) - -#define SCT_RES_O11RES_MASK (0xC00000U) -#define SCT_RES_O11RES_SHIFT (22U) -/*! O11RES - Effect of simultaneous set and clear on output 11. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR11 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) - -#define SCT_RES_O12RES_MASK (0x3000000U) -#define SCT_RES_O12RES_SHIFT (24U) -/*! O12RES - Effect of simultaneous set and clear on output 12. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR12 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) - -#define SCT_RES_O13RES_MASK (0xC000000U) -#define SCT_RES_O13RES_SHIFT (26U) -/*! O13RES - Effect of simultaneous set and clear on output 13. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR13 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) - -#define SCT_RES_O14RES_MASK (0x30000000U) -#define SCT_RES_O14RES_SHIFT (28U) -/*! O14RES - Effect of simultaneous set and clear on output 14. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR14 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) - -#define SCT_RES_O15RES_MASK (0xC0000000U) -#define SCT_RES_O15RES_SHIFT (30U) -/*! O15RES - Effect of simultaneous set and clear on output 15. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR15 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) -/*! @} */ - -/*! @name DMAREQ0 - SCT DMA request 0 register */ -/*! @{ */ - -#define SCT_DMAREQ0_DEV_0_MASK (0xFFFFU) -#define SCT_DMAREQ0_DEV_0_SHIFT (0U) -/*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, - * etc.). The number of bits = number of events in this SCT. - */ -#define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK) - -#define SCT_DMAREQ0_DRL0_MASK (0x40000000U) -#define SCT_DMAREQ0_DRL0_SHIFT (30U) -/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. - */ -#define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK) - -#define SCT_DMAREQ0_DRQ0_MASK (0x80000000U) -#define SCT_DMAREQ0_DRQ0_SHIFT (31U) -/*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA - * channel is enabled and properly set up, it is unlikely that software will see this flag, it will - * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA - * setup. - */ -#define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK) -/*! @} */ - -/*! @name DMAREQ1 - SCT DMA request 1 register */ -/*! @{ */ - -#define SCT_DMAREQ1_DEV_1_MASK (0xFFFFU) -#define SCT_DMAREQ1_DEV_1_SHIFT (0U) -/*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, - * etc.). The number of bits = number of events in this SCT. - */ -#define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK) - -#define SCT_DMAREQ1_DRL1_MASK (0x40000000U) -#define SCT_DMAREQ1_DRL1_SHIFT (30U) -/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. - */ -#define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK) - -#define SCT_DMAREQ1_DRQ1_MASK (0x80000000U) -#define SCT_DMAREQ1_DRQ1_SHIFT (31U) -/*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA - * channel is enabled and properly set up, it is unlikely that software will see this flag, it will - * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA - * setup. - */ -#define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK) -/*! @} */ - -/*! @name EVEN - SCT event interrupt enable register */ -/*! @{ */ - -#define SCT_EVEN_IEN_MASK (0xFFFFU) -#define SCT_EVEN_IEN_SHIFT (0U) -/*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are - * both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in - * this SCT. - */ -#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) -/*! @} */ - -/*! @name EVFLAG - SCT event flag register */ -/*! @{ */ - -#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) -#define SCT_EVFLAG_FLAG_SHIFT (0U) -/*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit - * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) -/*! @} */ - -/*! @name CONEN - SCT conflict interrupt enable register */ -/*! @{ */ - -#define SCT_CONEN_NCEN_MASK (0xFFFFU) -#define SCT_CONEN_NCEN_SHIFT (0U) -/*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag - * register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of - * outputs in this SCT. - */ -#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) -/*! @} */ - -/*! @name CONFLAG - SCT conflict flag register */ -/*! @{ */ - -#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) -#define SCT_CONFLAG_NCFLAG_SHIFT (0U) -/*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was - * last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = - * number of outputs in this SCT. - */ -#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) - -#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) -#define SCT_CONFLAG_BUSERRL_SHIFT (30U) -/*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE - * L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write - * to certain L and H registers can be half successful and half unsuccessful. - */ -#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) - -#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) -#define SCT_CONFLAG_BUSERRH_SHIFT (31U) -/*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or - * the Output register when the H counter was not halted. - */ -#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) -/*! @} */ - -/*! @name CAPL - SCT_CAPL register */ -/*! @{ */ - -#define SCT_CAPL_CAPL_MASK (0xFFFFU) -#define SCT_CAPL_CAPL_SHIFT (0U) -#define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK) -/*! @} */ - -/* The count of SCT_CAPL */ -#define SCT_CAPL_COUNT (16U) - -/*! @name CAPH - SCT_CAPH register */ -/*! @{ */ - -#define SCT_CAPH_CAPH_MASK (0xFFFFU) -#define SCT_CAPH_CAPH_SHIFT (0U) -#define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK) -/*! @} */ - -/* The count of SCT_CAPH */ -#define SCT_CAPH_COUNT (16U) - -/*! @name CAP - SCT capture register of capture channel */ -/*! @{ */ - -#define SCT_CAP_CAPn_L_MASK (0xFFFFU) -#define SCT_CAP_CAPn_L_SHIFT (0U) -/*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. - * When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last - * captured. - */ -#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK) - -#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U) -#define SCT_CAP_CAPn_H_SHIFT (16U) -/*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. - * When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last - * captured. - */ -#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK) -/*! @} */ - -/* The count of SCT_CAP */ -#define SCT_CAP_COUNT (16U) - -/*! @name MATCHL - SCT_MATCHL register */ -/*! @{ */ - -#define SCT_MATCHL_MATCHL_MASK (0xFFFFU) -#define SCT_MATCHL_MATCHL_SHIFT (0U) -#define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK) -/*! @} */ - -/* The count of SCT_MATCHL */ -#define SCT_MATCHL_COUNT (16U) - -/*! @name MATCHH - SCT_MATCHH register */ -/*! @{ */ - -#define SCT_MATCHH_MATCHH_MASK (0xFFFFU) -#define SCT_MATCHH_MATCHH_SHIFT (0U) -#define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK) -/*! @} */ - -/* The count of SCT_MATCHH */ -#define SCT_MATCHH_COUNT (16U) - -/*! @name MATCH - SCT match value register of match channels */ -/*! @{ */ - -#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU) -#define SCT_MATCH_MATCHn_L_SHIFT (0U) -/*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When - * UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified - * counter. - */ -#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK) - -#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U) -#define SCT_MATCH_MATCHn_H_SHIFT (16U) -/*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When - * UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified - * counter. - */ -#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK) -/*! @} */ - -/* The count of SCT_MATCH */ -#define SCT_MATCH_COUNT (16U) - -/*! @name CAPCTRLL - SCT_CAPCTRLL register */ -/*! @{ */ - -#define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU) -#define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U) -#define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK) -/*! @} */ - -/* The count of SCT_CAPCTRLL */ -#define SCT_CAPCTRLL_COUNT (16U) - -/*! @name CAPCTRLH - SCT_CAPCTRLH register */ -/*! @{ */ - -#define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU) -#define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U) -#define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK) -/*! @} */ - -/* The count of SCT_CAPCTRLH */ -#define SCT_CAPCTRLH_COUNT (16U) - -/*! @name CAPCTRL - SCT capture control register */ -/*! @{ */ - -#define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU) -#define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U) -/*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) - * register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of - * match/captures in this SCT. - */ -#define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK) - -#define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) -#define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U) -/*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event - * 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - */ -#define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK) -/*! @} */ - -/* The count of SCT_CAPCTRL */ -#define SCT_CAPCTRL_COUNT (16U) - -/*! @name MATCHRELL - SCT_MATCHRELL register */ -/*! @{ */ - -#define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU) -#define SCT_MATCHRELL_MATCHRELL_SHIFT (0U) -#define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK) -/*! @} */ - -/* The count of SCT_MATCHRELL */ -#define SCT_MATCHRELL_COUNT (16U) - -/*! @name MATCHRELH - SCT_MATCHRELH register */ -/*! @{ */ - -#define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU) -#define SCT_MATCHRELH_MATCHRELH_SHIFT (0U) -#define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK) -/*! @} */ - -/* The count of SCT_MATCHRELH */ -#define SCT_MATCHRELH_COUNT (16U) - -/*! @name MATCHREL - SCT match reload value register */ -/*! @{ */ - -#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU) -#define SCT_MATCHREL_RELOADn_L_SHIFT (0U) -/*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. - * When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn - * register. - */ -#define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK) - -#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U) -#define SCT_MATCHREL_RELOADn_H_SHIFT (16U) -/*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When - * UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn - * register. - */ -#define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK) -/*! @} */ - -/* The count of SCT_MATCHREL */ -#define SCT_MATCHREL_COUNT (16U) - -/*! @name EV_STATE - SCT event state register 0 */ -/*! @{ */ - -#define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFU) -#define SCT_EV_STATE_STATEMSKn_SHIFT (0U) -/*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT - * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of - * bits = number of states in this SCT. - */ -#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK) -/*! @} */ - -/* The count of SCT_EV_STATE */ -#define SCT_EV_STATE_COUNT (16U) - -/*! @name EV_CTRL - SCT event control register 0 */ -/*! @{ */ - -#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU) -#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U) -/*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur - * only when the counter selected by the HEVENT bit is running. - */ -#define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK) - -#define SCT_EV_CTRL_HEVENT_MASK (0x10U) -#define SCT_EV_CTRL_HEVENT_SHIFT (4U) -/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. - * 0b0..Selects the L state and the L match register selected by MATCHSEL. - * 0b1..Selects the H state and the H match register selected by MATCHSEL. - */ -#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK) - -#define SCT_EV_CTRL_OUTSEL_MASK (0x20U) -#define SCT_EV_CTRL_OUTSEL_SHIFT (5U) -/*! OUTSEL - Input/output select - * 0b0..Selects the inputs selected by IOSEL. - * 0b1..Selects the outputs selected by IOSEL. - */ -#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK) - -#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U) -#define SCT_EV_CTRL_IOSEL_SHIFT (6U) -/*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not - * select an input in this register if CKMODE is 1x. In this case the clock input is an implicit - * ingredient of every event. - */ -#define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK) - -#define SCT_EV_CTRL_IOCOND_MASK (0xC00U) -#define SCT_EV_CTRL_IOCOND_SHIFT (10U) -/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the - * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state - * detection, an input must have a minimum pulse width of at least one SCT clock period . - * 0b00..LOW - * 0b01..Rise - * 0b10..Fall - * 0b11..HIGH - */ -#define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK) - -#define SCT_EV_CTRL_COMBMODE_MASK (0x3000U) -#define SCT_EV_CTRL_COMBMODE_SHIFT (12U) -/*! COMBMODE - Selects how the specified match and I/O condition are used and combined. - * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. - * 0b01..MATCH. Uses the specified match only. - * 0b10..IO. Uses the specified I/O condition only. - * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. - */ -#define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK) - -#define SCT_EV_CTRL_STATELD_MASK (0x4000U) -#define SCT_EV_CTRL_STATELD_SHIFT (14U) -/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this - * event is the highest-numbered event occurring for that state. - * 0b0..STATEV value is added into STATE (the carry-out is ignored). - * 0b1..STATEV value is loaded into STATE. - */ -#define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK) - -#define SCT_EV_CTRL_STATEV_MASK (0xF8000U) -#define SCT_EV_CTRL_STATEV_SHIFT (15U) -/*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on - * STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and - * STATEV are both zero, there is no change to the STATE value. - */ -#define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK) - -#define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U) -#define SCT_EV_CTRL_MATCHMEM_SHIFT (20U) -/*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the - * triggering of this event, then a match is considered to be active whenever the counter value is - * GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR - * EQUAL TO the match value when counting down. If this bit is zero, a match is only be active - * during the cycle when the counter is equal to the match value. - */ -#define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK) - -#define SCT_EV_CTRL_DIRECTION_MASK (0x600000U) -#define SCT_EV_CTRL_DIRECTION_SHIFT (21U) -/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters - * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. - * 0b00..Direction independent. This event is triggered regardless of the count direction. - * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. - * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. - */ -#define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK) -/*! @} */ - -/* The count of SCT_EV_CTRL */ -#define SCT_EV_CTRL_COUNT (16U) - -/*! @name OUT_SET - SCT output 0 set register */ -/*! @{ */ - -#define SCT_OUT_SET_SET_MASK (0xFFFFU) -#define SCT_OUT_SET_SET_SHIFT (0U) -/*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output - * 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the - * counter is used in bi-directional mode, it is possible to reverse the action specified by the - * output set and clear registers when counting down, See the OUTPUTCTRL register. - */ -#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) -/*! @} */ - -/* The count of SCT_OUT_SET */ -#define SCT_OUT_SET_COUNT (10U) - -/*! @name OUT_CLR - SCT output 0 clear register */ -/*! @{ */ - -#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) -#define SCT_OUT_CLR_CLR_SHIFT (0U) -/*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 - * = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the - * counter is used in bi-directional mode, it is possible to reverse the action specified by the - * output set and clear registers when counting down, See the OUTPUTCTRL register. - */ -#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) -/*! @} */ - -/* The count of SCT_OUT_CLR */ -#define SCT_OUT_CLR_COUNT (10U) - - -/*! - * @} - */ /* end of group SCT_Register_Masks */ - - -/* SCT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SCT0 base address */ - #define SCT0_BASE (0x50085000u) - /** Peripheral SCT0 base address */ - #define SCT0_BASE_NS (0x40085000u) - /** Peripheral SCT0 base pointer */ - #define SCT0 ((SCT_Type *)SCT0_BASE) - /** Peripheral SCT0 base pointer */ - #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS { SCT0_BASE } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS { SCT0 } - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS_NS { SCT0_NS } -#else - /** Peripheral SCT0 base address */ - #define SCT0_BASE (0x40085000u) - /** Peripheral SCT0 base pointer */ - #define SCT0 ((SCT_Type *)SCT0_BASE) - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS { SCT0_BASE } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS { SCT0 } -#endif -/** Interrupt vectors for the SCT peripheral type */ -#define SCT_IRQS { SCT0_IRQn } - -/*! - * @} - */ /* end of group SCT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer - * @{ - */ - -/** SPI - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[1024]; - __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ - __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ - __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ - __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ - __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ - __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ - uint8_t RESERVED_2[2516]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_6[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_7[4]; - __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ - uint8_t RESERVED_8[432]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} SPI_Type; - -/* ---------------------------------------------------------------------------- - -- SPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Register_Masks SPI Register Masks - * @{ - */ - -/*! @name CFG - SPI Configuration register */ -/*! @{ */ - -#define SPI_CFG_ENABLE_MASK (0x1U) -#define SPI_CFG_ENABLE_SHIFT (0U) -/*! ENABLE - SPI enable. - * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. - * 0b1..Enabled. The SPI is enabled for operation. - */ -#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) - -#define SPI_CFG_MASTER_MASK (0x4U) -#define SPI_CFG_MASTER_SHIFT (2U) -/*! MASTER - Master mode select. - * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. - * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. - */ -#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) - -#define SPI_CFG_LSBF_MASK (0x8U) -#define SPI_CFG_LSBF_SHIFT (3U) -/*! LSBF - LSB First mode enable. - * 0b0..Standard. Data is transmitted and received in standard MSB first order. - * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). - */ -#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) - -#define SPI_CFG_CPHA_MASK (0x10U) -#define SPI_CFG_CPHA_SHIFT (4U) -/*! CPHA - Clock Phase select. - * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock - * changes away from the rest state). Data is changed on the following edge. - * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock - * changes away from the rest state). Data is captured on the following edge. - */ -#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) - -#define SPI_CFG_CPOL_MASK (0x20U) -#define SPI_CFG_CPOL_SHIFT (5U) -/*! CPOL - Clock Polarity select. - * 0b0..Low. The rest state of the clock (between transfers) is low. - * 0b1..High. The rest state of the clock (between transfers) is high. - */ -#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) - -#define SPI_CFG_LOOP_MASK (0x80U) -#define SPI_CFG_LOOP_SHIFT (7U) -/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit - * and receive data connected together to allow simple software testing. - * 0b0..Disabled. - * 0b1..Enabled. - */ -#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) - -#define SPI_CFG_SPOL0_MASK (0x100U) -#define SPI_CFG_SPOL0_SHIFT (8U) -/*! SPOL0 - SSEL0 Polarity select. - * 0b0..Low. The SSEL0 pin is active low. - * 0b1..High. The SSEL0 pin is active high. - */ -#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) - -#define SPI_CFG_SPOL1_MASK (0x200U) -#define SPI_CFG_SPOL1_SHIFT (9U) -/*! SPOL1 - SSEL1 Polarity select. - * 0b0..Low. The SSEL1 pin is active low. - * 0b1..High. The SSEL1 pin is active high. - */ -#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) - -#define SPI_CFG_SPOL2_MASK (0x400U) -#define SPI_CFG_SPOL2_SHIFT (10U) -/*! SPOL2 - SSEL2 Polarity select. - * 0b0..Low. The SSEL2 pin is active low. - * 0b1..High. The SSEL2 pin is active high. - */ -#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) - -#define SPI_CFG_SPOL3_MASK (0x800U) -#define SPI_CFG_SPOL3_SHIFT (11U) -/*! SPOL3 - SSEL3 Polarity select. - * 0b0..Low. The SSEL3 pin is active low. - * 0b1..High. The SSEL3 pin is active high. - */ -#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) -/*! @} */ - -/*! @name DLY - SPI Delay register */ -/*! @{ */ - -#define SPI_DLY_PRE_DELAY_MASK (0xFU) -#define SPI_DLY_PRE_DELAY_SHIFT (0U) -/*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data - * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This - * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI - * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are - * inserted. - */ -#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) - -#define SPI_DLY_POST_DELAY_MASK (0xF0U) -#define SPI_DLY_POST_DELAY_SHIFT (4U) -/*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL - * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock - * times are inserted. 0xF = 15 SPI clock times are inserted. - */ -#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) - -#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) -#define SPI_DLY_FRAME_DELAY_SHIFT (8U) -/*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current - * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 - * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock - * times are inserted. - */ -#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) - -#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) -#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) -/*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between - * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 - * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that - * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 - * SPI clock times. - */ -#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) -/*! @} */ - -/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ -/*! @{ */ - -#define SPI_STAT_SSA_MASK (0x10U) -#define SPI_STAT_SSA_SHIFT (4U) -/*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from - * deasserted to asserted, in both master and slave modes. This allows determining when the SPI - * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a - * slave mode access begins. This flag is cleared by software. - */ -#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) - -#define SPI_STAT_SSD_MASK (0x20U) -#define SPI_STAT_SSD_SHIFT (5U) -/*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to - * deasserted, in both master and slave modes. This allows determining when the SPI - * transmit/receive functions become idle. This flag is cleared by software. - */ -#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) - -#define SPI_STAT_STALLED_MASK (0x40U) -#define SPI_STAT_STALLED_SHIFT (6U) -/*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition. - */ -#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) - -#define SPI_STAT_ENDTRANSFER_MASK (0x80U) -#define SPI_STAT_ENDTRANSFER_SHIFT (7U) -/*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current - * transfer when the transmitter finishes any activity already in progress, as if the EOT flag - * had been set prior to the last transmission. This capability is included to support cases where - * it is not known when transmit data is written that it will be the end of a transfer. The bit - * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end - * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. - */ -#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) - -#define SPI_STAT_MSTIDLE_MASK (0x100U) -#define SPI_STAT_MSTIDLE_SHIFT (8U) -/*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. - * This means that the transmit holding register is empty and the transmitter is not in the - * process of sending data. - */ -#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -/*! @{ */ - -#define SPI_INTENSET_SSAEN_MASK (0x10U) -#define SPI_INTENSET_SSAEN_SHIFT (4U) -/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. - * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. - * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. - */ -#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) - -#define SPI_INTENSET_SSDEN_MASK (0x20U) -#define SPI_INTENSET_SSDEN_SHIFT (5U) -/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. - * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. - * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. - */ -#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) - -#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) -#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) -/*! MSTIDLEEN - Master idle interrupt enable. - * 0b0..No interrupt will be generated when the SPI master function is idle. - * 0b1..An interrupt will be generated when the SPI master function is fully idle. - */ -#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) -/*! @} */ - -/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ -/*! @{ */ - -#define SPI_INTENCLR_SSAEN_MASK (0x10U) -#define SPI_INTENCLR_SSAEN_SHIFT (4U) -/*! SSAEN - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) - -#define SPI_INTENCLR_SSDEN_MASK (0x20U) -#define SPI_INTENCLR_SSDEN_SHIFT (5U) -/*! SSDEN - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) - -#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) -#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) -/*! MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) -/*! @} */ - -/*! @name DIV - SPI clock Divider */ -/*! @{ */ - -#define SPI_DIV_DIVVAL_MASK (0xFFFFU) -#define SPI_DIV_DIVVAL_SHIFT (0U) -/*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the - * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, - * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results - * in FCLK/65536. - */ -#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - SPI Interrupt Status */ -/*! @{ */ - -#define SPI_INTSTAT_SSA_MASK (0x10U) -#define SPI_INTSTAT_SSA_SHIFT (4U) -/*! SSA - Slave Select Assert. - */ -#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) - -#define SPI_INTSTAT_SSD_MASK (0x20U) -#define SPI_INTSTAT_SSD_SHIFT (5U) -/*! SSD - Slave Select Deassert. - */ -#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) - -#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) -#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) -/*! MSTIDLE - Master Idle status flag. - */ -#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ - -#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) -#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) - -#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) -#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) - -#define SPI_FIFOCFG_SIZE_MASK (0x30U) -#define SPI_FIFOCFG_SIZE_SHIFT (4U) -/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 - * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - */ -#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) - -#define SPI_FIFOCFG_DMATX_MASK (0x1000U) -#define SPI_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) - -#define SPI_FIFOCFG_DMARX_MASK (0x2000U) -#define SPI_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) - -#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) -#define SPI_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in - * FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) - -#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) -#define SPI_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in - * FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) - -#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) -/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - */ -#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) - -#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) -/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - */ -#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ - -#define SPI_FIFOSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow - * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is - * needed. Cleared by writing a 1 to this bit. - */ -#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) - -#define SPI_FIFOSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA - * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - */ -#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) - -#define SPI_FIFOSTAT_PERINT_MASK (0x8U) -#define SPI_FIFOSTAT_PERINT_SHIFT (3U) -/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted - * an interrupt. The details can be found by reading the peripheral's STAT register. - */ -#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) - -#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) -/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - */ -#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) - -#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) -/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be - * written. When 0, the transmit FIFO is full and another write would cause it to overflow. - */ -#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) - -#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - */ -#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) - -#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) -#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) -/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to - * prevent the peripheral from causing an overflow. - */ -#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) - -#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY - * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at - * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be - * 0. - */ -#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) - -#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and - * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the - * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be - * 1. - */ -#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ - -#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) - -#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) - -#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) -#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled - * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to - * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO - * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX - * FIFO level decreases to 15 entries (is no longer full). - */ -#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) - -#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data - * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level - * can wake up the device just enough to perform DMA, then return to the reduced power mode. See - * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no - * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX - * FIFO has received 16 entries (has become full). - */ -#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ - -#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) -#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) - -#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) -#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) - -#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases - * to the level specified by TXLVL in the FIFOTRIG register. - */ -#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) - -#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level - * increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ - -#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) -#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) -/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) - -#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) -#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) -/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) - -#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) -/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) - -#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) -/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ - -#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. - */ -#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) - -#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. - */ -#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) - -#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO level interrupt. - */ -#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) - -#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO level interrupt. - */ -#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) - -#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) -#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) -/*! PERINT - Peripheral interrupt. - */ -#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ - -#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) -#define SPI_FIFOWR_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit data to the FIFO. - */ -#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) - -#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) -#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) -/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL0 asserted. - * 0b1..SSEL0 not asserted. - */ -#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) - -#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) -#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) -/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL1 asserted. - * 0b1..SSEL1 not asserted. - */ -#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) - -#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) -#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) -/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL2 asserted. - * 0b1..SSEL2 not asserted. - */ -#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) - -#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) -#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) -/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL3 asserted. - * 0b1..SSEL3 not asserted. - */ -#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) - -#define SPI_FIFOWR_EOT_MASK (0x100000U) -#define SPI_FIFOWR_EOT_SHIFT (20U) -/*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain - * so far at least the time specified by the Transfer_delay value in the DLY register. - * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. - * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. - */ -#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) - -#define SPI_FIFOWR_EOF_MASK (0x200000U) -#define SPI_FIFOWR_EOF_SHIFT (21U) -/*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value - * in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay - * value = 0. This control can be used as part of the support for frame lengths greater than 16 - * bits. - * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame. - * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be - * inserted before subsequent data is transmitted. - */ -#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) - -#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) -#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) -/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to - * read unneeded data from the receiver. Setting this bit simplifies the transmit process and can - * be used with the DMA. - * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit - * will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data - * is not read before new data is received. - * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received - * data. No receiver flags are generated. - */ -#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) - -#define SPI_FIFOWR_TXIGNORE_MASK (0x800000U) -#define SPI_FIFOWR_TXIGNORE_SHIFT (23U) -/*! TXIGNORE - Transmit Ignore. This allows data to be received using the SPI without the need to - * read unneeded data from the receiver. Setting this bit simplifies the transmit process and can - * be used with the DMA.This bit can only be set by writing to the upper 16 bits only of FIFOWR, - * i.e., a half-word write to offset 0xE22. - * 0b0..Write transmit data. Transmit data must be written for each data exchange between master and slave. In - * slave mode, an underrun error occurs if transmit data is not provided before needed in a data frame. - * 0b1..Ignore transmit data. Data can be received without transmitting data (after FIFOWR has been initialized - * to set TXIGNORE). No transmitter flags are generated. When configured with TXIGNORE =1, the slave will set - * the data to always 0. - */ -#define SPI_FIFOWR_TXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXIGNORE_SHIFT)) & SPI_FIFOWR_TXIGNORE_MASK) - -#define SPI_FIFOWR_LEN_MASK (0xF000000U) -#define SPI_FIFOWR_LEN_SHIFT (24U) -/*! LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths - * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. - * 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data - * transfer is 16 bits in length. - */ -#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ - -#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORD_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. - */ -#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) - -#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) -/*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved - * along with received data. The value will reflect the SSEL0 pin for both master and slave - * operation. A zero indicates that a slave select is active. The actual polarity of each slave select - * pin is configured by the related SPOL bit in CFG. - */ -#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) - -#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) -/*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved - * along with received data. The value will reflect the SSEL1 pin for both master and slave - * operation. A zero indicates that a slave select is active. The actual polarity of each slave select - * pin is configured by the related SPOL bit in CFG. - */ -#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) - -#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) -/*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved - * along with received data. The value will reflect the SSEL2 pin for both master and slave - * operation. A zero indicates that a slave select is active. The actual polarity of each slave select - * pin is configured by the related SPOL bit in CFG. - */ -#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) - -#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) -/*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved - * along with received data. The value will reflect the SSEL3 pin for both master and slave - * operation. A zero indicates that a slave select is active. The actual polarity of each slave select - * pin is configured by the related SPOL bit in CFG. - */ -#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) - -#define SPI_FIFORD_SOT_MASK (0x100000U) -#define SPI_FIFORD_SOT_SHIFT (20U) -/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went - * from deasserted to asserted (i.e., any previous transfer has ended). This information can be - * used to identify the first piece of data in cases where the transfer length is greater than 16 - * bits. - */ -#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ - -#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. - */ -#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) -/*! RXSSEL0_N - Slave Select for receive. - */ -#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) -/*! RXSSEL1_N - Slave Select for receive. - */ -#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) -/*! RXSSEL2_N - Slave Select for receive. - */ -#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) -/*! RXSSEL3_N - Slave Select for receive. - */ -#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) - -#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) -#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) -/*! SOT - Start of transfer flag. - */ -#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) -/*! @} */ - -/*! @name FIFOSIZE - FIFO size register */ -/*! @{ */ - -#define SPI_FIFOSIZE_FIFOSIZE_MASK (0x1FU) -#define SPI_FIFOSIZE_FIFOSIZE_SHIFT (0U) -/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - */ -#define SPI_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSIZE_FIFOSIZE_SHIFT)) & SPI_FIFOSIZE_FIFOSIZE_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ - -#define SPI_ID_APERTURE_MASK (0xFFU) -#define SPI_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - */ -#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) - -#define SPI_ID_MINOR_REV_MASK (0xF00U) -#define SPI_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation. - */ -#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) - -#define SPI_ID_MAJOR_REV_MASK (0xF000U) -#define SPI_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation. - */ -#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) - -#define SPI_ID_ID_MASK (0xFFFF0000U) -#define SPI_ID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function. - */ -#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SPI_Register_Masks */ - - -/* SPI - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SPI0 base address */ - #define SPI0_BASE (0x50086000u) - /** Peripheral SPI0 base address */ - #define SPI0_BASE_NS (0x40086000u) - /** Peripheral SPI0 base pointer */ - #define SPI0 ((SPI_Type *)SPI0_BASE) - /** Peripheral SPI0 base pointer */ - #define SPI0_NS ((SPI_Type *)SPI0_BASE_NS) - /** Peripheral SPI1 base address */ - #define SPI1_BASE (0x50087000u) - /** Peripheral SPI1 base address */ - #define SPI1_BASE_NS (0x40087000u) - /** Peripheral SPI1 base pointer */ - #define SPI1 ((SPI_Type *)SPI1_BASE) - /** Peripheral SPI1 base pointer */ - #define SPI1_NS ((SPI_Type *)SPI1_BASE_NS) - /** Peripheral SPI2 base address */ - #define SPI2_BASE (0x50088000u) - /** Peripheral SPI2 base address */ - #define SPI2_BASE_NS (0x40088000u) - /** Peripheral SPI2 base pointer */ - #define SPI2 ((SPI_Type *)SPI2_BASE) - /** Peripheral SPI2 base pointer */ - #define SPI2_NS ((SPI_Type *)SPI2_BASE_NS) - /** Peripheral SPI3 base address */ - #define SPI3_BASE (0x50089000u) - /** Peripheral SPI3 base address */ - #define SPI3_BASE_NS (0x40089000u) - /** Peripheral SPI3 base pointer */ - #define SPI3 ((SPI_Type *)SPI3_BASE) - /** Peripheral SPI3 base pointer */ - #define SPI3_NS ((SPI_Type *)SPI3_BASE_NS) - /** Peripheral SPI4 base address */ - #define SPI4_BASE (0x5008A000u) - /** Peripheral SPI4 base address */ - #define SPI4_BASE_NS (0x4008A000u) - /** Peripheral SPI4 base pointer */ - #define SPI4 ((SPI_Type *)SPI4_BASE) - /** Peripheral SPI4 base pointer */ - #define SPI4_NS ((SPI_Type *)SPI4_BASE_NS) - /** Peripheral SPI5 base address */ - #define SPI5_BASE (0x50096000u) - /** Peripheral SPI5 base address */ - #define SPI5_BASE_NS (0x40096000u) - /** Peripheral SPI5 base pointer */ - #define SPI5 ((SPI_Type *)SPI5_BASE) - /** Peripheral SPI5 base pointer */ - #define SPI5_NS ((SPI_Type *)SPI5_BASE_NS) - /** Peripheral SPI6 base address */ - #define SPI6_BASE (0x50097000u) - /** Peripheral SPI6 base address */ - #define SPI6_BASE_NS (0x40097000u) - /** Peripheral SPI6 base pointer */ - #define SPI6 ((SPI_Type *)SPI6_BASE) - /** Peripheral SPI6 base pointer */ - #define SPI6_NS ((SPI_Type *)SPI6_BASE_NS) - /** Peripheral SPI7 base address */ - #define SPI7_BASE (0x50098000u) - /** Peripheral SPI7 base address */ - #define SPI7_BASE_NS (0x40098000u) - /** Peripheral SPI7 base pointer */ - #define SPI7 ((SPI_Type *)SPI7_BASE) - /** Peripheral SPI7 base pointer */ - #define SPI7_NS ((SPI_Type *)SPI7_BASE_NS) - /** Peripheral SPI8 base address */ - #define SPI8_BASE (0x5009F000u) - /** Peripheral SPI8 base address */ - #define SPI8_BASE_NS (0x4009F000u) - /** Peripheral SPI8 base pointer */ - #define SPI8 ((SPI_Type *)SPI8_BASE) - /** Peripheral SPI8 base pointer */ - #define SPI8_NS ((SPI_Type *)SPI8_BASE_NS) - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS_NS { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS_NS { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS } -#else - /** Peripheral SPI0 base address */ - #define SPI0_BASE (0x40086000u) - /** Peripheral SPI0 base pointer */ - #define SPI0 ((SPI_Type *)SPI0_BASE) - /** Peripheral SPI1 base address */ - #define SPI1_BASE (0x40087000u) - /** Peripheral SPI1 base pointer */ - #define SPI1 ((SPI_Type *)SPI1_BASE) - /** Peripheral SPI2 base address */ - #define SPI2_BASE (0x40088000u) - /** Peripheral SPI2 base pointer */ - #define SPI2 ((SPI_Type *)SPI2_BASE) - /** Peripheral SPI3 base address */ - #define SPI3_BASE (0x40089000u) - /** Peripheral SPI3 base pointer */ - #define SPI3 ((SPI_Type *)SPI3_BASE) - /** Peripheral SPI4 base address */ - #define SPI4_BASE (0x4008A000u) - /** Peripheral SPI4 base pointer */ - #define SPI4 ((SPI_Type *)SPI4_BASE) - /** Peripheral SPI5 base address */ - #define SPI5_BASE (0x40096000u) - /** Peripheral SPI5 base pointer */ - #define SPI5 ((SPI_Type *)SPI5_BASE) - /** Peripheral SPI6 base address */ - #define SPI6_BASE (0x40097000u) - /** Peripheral SPI6 base pointer */ - #define SPI6 ((SPI_Type *)SPI6_BASE) - /** Peripheral SPI7 base address */ - #define SPI7_BASE (0x40098000u) - /** Peripheral SPI7 base pointer */ - #define SPI7 ((SPI_Type *)SPI7_BASE) - /** Peripheral SPI8 base address */ - #define SPI8_BASE (0x4009F000u) - /** Peripheral SPI8 base pointer */ - #define SPI8 ((SPI_Type *)SPI8_BASE) - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } -#endif -/** Interrupt vectors for the SPI peripheral type */ -#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } - -/*! - * @} - */ /* end of group SPI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SYSCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer - * @{ - */ - -/** SYSCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t MEMORYREMAP; /**< Memory Remap control register, offset: 0x0 */ - uint8_t RESERVED_0[12]; - __IO uint32_t AHBMATPRIO; /**< AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest, offset: 0x10 */ - uint8_t RESERVED_1[36]; - __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */ - __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */ - uint8_t RESERVED_2[8]; - __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ - uint8_t RESERVED_3[180]; - union { /* offset: 0x100 */ - struct { /* offset: 0x100 */ - __IO uint32_t PRESETCTRL0; /**< Peripheral reset control 0, offset: 0x100 */ - __IO uint32_t PRESETCTRL1; /**< Peripheral reset control 1, offset: 0x104 */ - __IO uint32_t PRESETCTRL2; /**< Peripheral reset control 2, offset: 0x108 */ - } PRESETCTRL; - __IO uint32_t PRESETCTRLX[3]; /**< Peripheral reset control register, array offset: 0x100, array step: 0x4 */ - }; - uint8_t RESERVED_4[20]; - __IO uint32_t PRESETCTRLSET[3]; /**< Peripheral reset control set register, array offset: 0x120, array step: 0x4 */ - uint8_t RESERVED_5[20]; - __IO uint32_t PRESETCTRLCLR[3]; /**< Peripheral reset control clear register, array offset: 0x140, array step: 0x4 */ - uint8_t RESERVED_6[20]; - __O uint32_t SWR_RESET; /**< generate a software_reset, offset: 0x160 */ - uint8_t RESERVED_7[156]; - union { /* offset: 0x200 */ - struct { /* offset: 0x200 */ - __IO uint32_t AHBCLKCTRL0; /**< AHB Clock control 0, offset: 0x200 */ - __IO uint32_t AHBCLKCTRL1; /**< AHB Clock control 1, offset: 0x204 */ - __IO uint32_t AHBCLKCTRL2; /**< AHB Clock control 2, offset: 0x208 */ - } AHBCLKCTRL; - __IO uint32_t AHBCLKCTRLX[3]; /**< Peripheral reset control register, array offset: 0x200, array step: 0x4 */ - }; - uint8_t RESERVED_8[20]; - __IO uint32_t AHBCLKCTRLSET[3]; /**< Peripheral reset control register, array offset: 0x220, array step: 0x4 */ - uint8_t RESERVED_9[20]; - __IO uint32_t AHBCLKCTRLCLR[3]; /**< Peripheral reset control register, array offset: 0x240, array step: 0x4 */ - uint8_t RESERVED_10[20]; - union { /* offset: 0x260 */ - __IO uint32_t SYSTICKCLKSEL0; /**< System Tick Timer for CPU0 source select, offset: 0x260 */ - __IO uint32_t SYSTICKCLKSELX[1]; /**< Peripheral reset control register, array offset: 0x260, array step: 0x4 */ - }; - uint8_t RESERVED_11[4]; - __IO uint32_t TRACECLKSEL; /**< Trace clock source select, offset: 0x268 */ - union { /* offset: 0x26C */ - struct { /* offset: 0x26C */ - __IO uint32_t CTIMERCLKSEL0; /**< CTimer 0 clock source select, offset: 0x26C */ - __IO uint32_t CTIMERCLKSEL1; /**< CTimer 1 clock source select, offset: 0x270 */ - __IO uint32_t CTIMERCLKSEL2; /**< CTimer 2 clock source select, offset: 0x274 */ - __IO uint32_t CTIMERCLKSEL3; /**< CTimer 3 clock source select, offset: 0x278 */ - __IO uint32_t CTIMERCLKSEL4; /**< CTimer 4 clock source select, offset: 0x27C */ - } CTIMERCLKSEL; - __IO uint32_t CTIMERCLKSELX[5]; /**< Peripheral reset control register, array offset: 0x26C, array step: 0x4 */ - }; - __IO uint32_t MAINCLKSELA; /**< Main clock A source select, offset: 0x280 */ - __IO uint32_t MAINCLKSELB; /**< Main clock source select, offset: 0x284 */ - __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0x288 */ - uint8_t RESERVED_12[4]; - __IO uint32_t PLL0CLKSEL; /**< PLL0 clock source select, offset: 0x290 */ - __IO uint32_t PLL1CLKSEL; /**< PLL1 clock source select, offset: 0x294 */ - uint8_t RESERVED_13[8]; - __IO uint32_t CANCLKSEL; /**< CAN clock source select, offset: 0x2A0 */ - __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ - __IO uint32_t USB0CLKSEL; /**< FS USB clock source select, offset: 0x2A8 */ - __IO uint32_t CLK32KCLKSEL; /**< clock low speed source select for HS USB., offset: 0x2AC */ - union { /* offset: 0x2B0 */ - struct { /* offset: 0x2B0 */ - __IO uint32_t FCCLKSEL0; /**< Flexcomm Interface 0 clock source select for Fractional Rate Divider, offset: 0x2B0 */ - __IO uint32_t FCCLKSEL1; /**< Flexcomm Interface 1 clock source select for Fractional Rate Divider, offset: 0x2B4 */ - __IO uint32_t FCCLKSEL2; /**< Flexcomm Interface 2 clock source select for Fractional Rate Divider, offset: 0x2B8 */ - __IO uint32_t FCCLKSEL3; /**< Flexcomm Interface 3 clock source select for Fractional Rate Divider, offset: 0x2BC */ - __IO uint32_t FCCLKSEL4; /**< Flexcomm Interface 4 clock source select for Fractional Rate Divider, offset: 0x2C0 */ - __IO uint32_t FCCLKSEL5; /**< Flexcomm Interface 5 clock source select for Fractional Rate Divider, offset: 0x2C4 */ - __IO uint32_t FCCLKSEL6; /**< Flexcomm Interface 6 clock source select for Fractional Rate Divider, offset: 0x2C8 */ - __IO uint32_t FCCLKSEL7; /**< Flexcomm Interface 7 clock source select for Fractional Rate Divider, offset: 0x2CC */ - } FCCLKSEL; - __IO uint32_t FCCLKSELX[8]; /**< Peripheral reset control register, array offset: 0x2B0, array step: 0x4 */ - }; - __IO uint32_t HSLSPICLKSEL; /**< HS LSPI clock source select, offset: 0x2D0 */ - uint8_t RESERVED_14[12]; - __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ - uint8_t RESERVED_15[12]; - __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ - uint8_t RESERVED_16[12]; - __IO uint32_t SYSTICKCLKDIV0; /**< System Tick Timer divider for CPU0, offset: 0x300 */ - uint8_t RESERVED_17[4]; - __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */ - __IO uint32_t CANCLKDIV; /**< CAN clock divider, offset: 0x30C */ - uint8_t RESERVED_18[16]; - union { /* offset: 0x320 */ - struct { /* offset: 0x320 */ - __IO uint32_t FLEXFRG0CTRL; /**< Fractional rate divider for flexcomm 0, offset: 0x320 */ - __IO uint32_t FLEXFRG1CTRL; /**< Fractional rate divider for flexcomm 1, offset: 0x324 */ - __IO uint32_t FLEXFRG2CTRL; /**< Fractional rate divider for flexcomm 2, offset: 0x328 */ - __IO uint32_t FLEXFRG3CTRL; /**< Fractional rate divider for flexcomm 3, offset: 0x32C */ - __IO uint32_t FLEXFRG4CTRL; /**< Fractional rate divider for flexcomm 4, offset: 0x330 */ - __IO uint32_t FLEXFRG5CTRL; /**< Fractional rate divider for flexcomm 5, offset: 0x334 */ - __IO uint32_t FLEXFRG6CTRL; /**< Fractional rate divider for flexcomm 6, offset: 0x338 */ - __IO uint32_t FLEXFRG7CTRL; /**< Fractional rate divider for flexcomm 7, offset: 0x33C */ - } FLEXFRGCTRL; - __IO uint32_t FLEXFRGXCTRL[8]; /**< Peripheral reset control register, array offset: 0x320, array step: 0x4 */ - }; - uint8_t RESERVED_19[64]; - __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */ - __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ - __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */ - __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */ - uint8_t RESERVED_20[4]; - __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ - __IO uint32_t USB0CLKDIV; /**< USB0-FS Clock divider, offset: 0x398 */ - uint8_t RESERVED_21[4]; - __IO uint32_t FRO1MCLKDIV; /**< FRO1MHz Clock divider (FRO1M_divided), offset: 0x3A0 */ - uint8_t RESERVED_22[8]; - __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ - uint8_t RESERVED_23[4]; - __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ - uint8_t RESERVED_24[12]; - __IO uint32_t PLL0CLKDIV; /**< PLL0 clock divider, offset: 0x3C4 */ - uint8_t RESERVED_25[52]; - __IO uint32_t CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */ - __IO uint32_t FMCCR; /**< FMC configuration register, offset: 0x400 */ - uint8_t RESERVED_26[8]; - __IO uint32_t USB0NEEDCLKCTRL; /**< USB0-FS need clock control, offset: 0x40C */ - __I uint32_t USB0NEEDCLKSTAT; /**< USB0-FS need clock status, offset: 0x410 */ - uint8_t RESERVED_27[8]; - __O uint32_t FMCFLUSH; /**< FMCflush control, offset: 0x41C */ - __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */ - __IO uint32_t USB1NEEDCLKCTRL; /**< USB1-HS need clock control, offset: 0x424 */ - __I uint32_t USB1NEEDCLKSTAT; /**< USB1-HS need clock status, offset: 0x428 */ - uint8_t RESERVED_28[20]; - __IO uint32_t FLASHREMAP_SIZE; /**< This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB., offset: 0x440 */ - __IO uint32_t FLASHREMAP_SIZE_DP; /**< This 32-bit register is a duplicate of FLASHREMAPSIZE for increased security., offset: 0x444 */ - __IO uint32_t FLASHREMAP_OFFSET; /**< This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB., offset: 0x448 */ - __IO uint32_t FLASHREMAP_OFFSET_DP; /**< This 32-bit register is a duplicate of FLASHREMAPOFFSET for increased security., offset: 0x44C */ - uint8_t RESERVED_29[12]; - __IO uint32_t FLASHREMAP_LOCK; /**< Control write access to FLASHREMAP_SIZE and FLASHREMAP_OFFSET registers., offset: 0x45C */ - uint8_t RESERVED_30[16]; - __IO uint32_t CASPER_CTRL; /**< Control CASPER integration., offset: 0x470 */ - uint8_t RESERVED_31[236]; - __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */ - __I uint32_t PLL1STAT; /**< PLL1 550m status, offset: 0x564 */ - __IO uint32_t PLL1NDEC; /**< PLL1 550m N divider, offset: 0x568 */ - __IO uint32_t PLL1MDEC; /**< PLL1 550m M divider, offset: 0x56C */ - __IO uint32_t PLL1PDEC; /**< PLL1 550m P divider, offset: 0x570 */ - uint8_t RESERVED_32[12]; - __IO uint32_t PLL0CTRL; /**< PLL0 550m control, offset: 0x580 */ - __I uint32_t PLL0STAT; /**< PLL0 550m status, offset: 0x584 */ - __IO uint32_t PLL0NDEC; /**< PLL0 550m N divider, offset: 0x588 */ - __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */ - __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */ - __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */ - uint8_t RESERVED_33[364]; - __IO uint32_t FUNCRETENTIONCTRL; /**< Functional retention control register, offset: 0x704 */ - uint8_t RESERVED_34[260]; - __I uint32_t CPSTAT; /**< CPU Status, offset: 0x80C */ - uint8_t RESERVED_35[272]; - __IO uint32_t BOOT_SEED_REG0; /**< boot seed (256-bit random value), offset: 0x920 */ - __IO uint32_t BOOT_SEED_REG1; /**< boot seed (256-bit random value), offset: 0x924 */ - __IO uint32_t BOOT_SEED_REG2; /**< boot seed (256-bit random value), offset: 0x928 */ - __IO uint32_t BOOT_SEED_REG3; /**< boot seed (256-bit random value), offset: 0x92C */ - __IO uint32_t BOOT_SEED_REG4; /**< boot seed (256-bit random value), offset: 0x930 */ - __IO uint32_t BOOT_SEED_REG5; /**< boot seed (256-bit random value), offset: 0x934 */ - __IO uint32_t BOOT_SEED_REG6; /**< boot seed (256-bit random value), offset: 0x938 */ - __IO uint32_t BOOT_SEED_REG7; /**< boot seed (256-bit random value), offset: 0x93C */ - __IO uint32_t HMAC_REG0; /**< HMAC, offset: 0x940 */ - __IO uint32_t HMAC_REG1; /**< HMAC, offset: 0x944 */ - __IO uint32_t HMAC_REG2; /**< HMAC, offset: 0x948 */ - __IO uint32_t HMAC_REG3; /**< HMAC, offset: 0x94C */ - __IO uint32_t HMAC_REG4; /**< HMAC, offset: 0x950 */ - __IO uint32_t HMAC_REG5; /**< HMAC, offset: 0x954 */ - __IO uint32_t HMAC_REG6; /**< HMAC, offset: 0x958 */ - __IO uint32_t HMAC_REG7; /**< HMAC, offset: 0x95C */ - __IO uint32_t BOOT_LOCK; /**< Control write access to boot seed security registers., offset: 0x960 */ - uint8_t RESERVED_36[180]; - __IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures, offset: 0xA18 */ - uint8_t RESERVED_37[244]; - __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */ - __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */ - uint8_t RESERVED_38[748]; - __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */ - __IO uint32_t GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */ - uint8_t RESERVED_39[380]; - __IO uint32_t HASHRESTHWKEY; /**< Controls whether the HASH AES hardware secret key is restricted to use by secure code, offset: 0xF88 */ - uint8_t RESERVED_40[20]; - __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers., offset: 0xFA0 */ - __IO uint32_t DEBUG_FEATURES; /**< Cortex debug features control., offset: 0xFA4 */ - __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex debug features control. (duplicate), offset: 0xFA8 */ - uint8_t RESERVED_41[8]; - __IO uint32_t SWD_ACCESS_CPU0; /**< This register is used by ROM during DEBUG authentication mechanism to enable debug access port for CPU0., offset: 0xFB4 */ - uint8_t RESERVED_42[4]; - __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index., offset: 0xFBC */ - __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug authentication BEACON register, offset: 0xFC0 */ - uint8_t RESERVED_43[52]; - __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ - __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */ -} SYSCON_Type; - -/* ---------------------------------------------------------------------------- - -- SYSCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Register_Masks SYSCON Register Masks - * @{ - */ - -/*! @name MEMORYREMAP - Memory Remap control register */ -/*! @{ */ - -#define SYSCON_MEMORYREMAP_MAP_MASK (0x3U) -#define SYSCON_MEMORYREMAP_MAP_SHIFT (0U) -/*! MAP - Select the location of the vector table :. - * 0b00..Vector Table in ROM. - * 0b01..Vector Table in RAM. - * 0b10..Vector Table in Flash. - * 0b11..Vector Table in Flash. - */ -#define SYSCON_MEMORYREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK) -/*! @} */ - -/*! @name AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest */ -/*! @{ */ - -#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK (0x3U) -#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT (0U) -/*! PRI_CPU0_CBUS - CPU0 C-AHB bus. - */ -#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK (0xCU) -#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT (2U) -/*! PRI_CPU0_SBUS - CPU0 S-AHB bus. - */ -#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0x30U) -#define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (4U) -/*! PRI_SDMA0 - DMA0 controller priority. - */ -#define SYSCON_AHBMATPRIO_PRI_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK) - -#define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0xC0U) -#define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (6U) -/*! PRI_SDMA1 - DMA1 controller priority. - */ -#define SYSCON_AHBMATPRIO_PRI_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK) - -#define SYSCON_AHBMATPRIO_PRI_USB_FSD_MASK (0x300U) -#define SYSCON_AHBMATPRIO_PRI_USB_FSD_SHIFT (8U) -/*! PRI_USB_FSD - USB0-FS Device.(USB0) - */ -#define SYSCON_AHBMATPRIO_PRI_USB_FSD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FSD_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FSD_MASK) - -#define SYSCON_AHBMATPRIO_PRI_USB_FSH_MASK (0xC00U) -#define SYSCON_AHBMATPRIO_PRI_USB_FSH_SHIFT (10U) -/*! PRI_USB_FSH - USB0-FS host.(USB0) - */ -#define SYSCON_AHBMATPRIO_PRI_USB_FSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FSH_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FSH_MASK) - -#define SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK (0x30000U) -#define SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT (16U) -/*! PRI_HASH_AES - HASH_AES. - */ -#define SYSCON_AHBMATPRIO_PRI_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT)) & SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK) - -#define SYSCON_AHBMATPRIO_PRI_CANFD_MASK (0xC0000U) -#define SYSCON_AHBMATPRIO_PRI_CANFD_SHIFT (18U) -/*! PRI_CANFD - CANFD. - */ -#define SYSCON_AHBMATPRIO_PRI_CANFD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CANFD_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CANFD_MASK) -/*! @} */ - -/*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */ -/*! @{ */ - -#define SYSCON_CPU0STCKCAL_TENMS_MASK (0xFFFFFFU) -#define SYSCON_CPU0STCKCAL_TENMS_SHIFT (0U) -/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value - * reads as zero, the calibration value is not known. - */ -#define SYSCON_CPU0STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK) - -#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) -/*! SKEW - Initial value for the Systick timer. - */ -#define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) - -#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) -/*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference - * clock provided; 1 = no reference clock provided. - */ -#define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */ -/*! @{ */ - -#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) -#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) -/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the - * value reads as zero, the calibration value is not known. - */ -#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) - -#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) -/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. - */ -#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) - -#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) -/*! NOREF - Initial value for the Systick timer. - */ -#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name NMISRC - NMI Source Select */ -/*! @{ */ - -#define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU) -#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) -/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0. - */ -#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) - -#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) -#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) -/*! NMIENCPU0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. - */ -#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) -/*! @} */ - -/*! @name PRESETCTRL0 - Peripheral reset control 0 */ -/*! @{ */ - -#define SYSCON_PRESETCTRL0_ROM_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL0_ROM_RST_SHIFT (1U) -/*! ROM_RST - ROM reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_ROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ROM_RST_SHIFT)) & SYSCON_PRESETCTRL0_ROM_RST_MASK) - -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U) -/*! SRAM_CTRL1_RST - SRAM Controller 1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK) - -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U) -/*! SRAM_CTRL2_RST - SRAM Controller 2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK) - -#define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U) -/*! FLASH_RST - Flash controller reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK) - -#define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U) -/*! FMC_RST - FMC controller reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK) - -#define SYSCON_PRESETCTRL0_MUX_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL0_MUX_RST_SHIFT (11U) -/*! MUX_RST - Input Mux reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK) - -#define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U) -/*! IOCON_RST - I/O controller reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK) - -#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U) -/*! GPIO0_RST - GPIO0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) - -#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U) -/*! GPIO1_RST - GPIO1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) - -#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U) -/*! PINT_RST - Pin interrupt (PINT) reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) - -#define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U) -/*! GINT_RST - Group interrupt (GINT) reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK) - -#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U) -#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U) -/*! DMA0_RST - DMA0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) - -#define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U) -#define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U) -/*! CRCGEN_RST - CRCGEN reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_CRCGEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK) - -#define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U) -/*! WWDT_RST - Watchdog Timer reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK) - -#define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U) -#define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U) -/*! RTC_RST - Real Time Clock (RTC) reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK) - -#define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U) -#define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U) -/*! MAILBOX_RST - Inter CPU communication Mailbox reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK) - -#define SYSCON_PRESETCTRL0_ADC_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL0_ADC_RST_SHIFT (27U) -/*! ADC_RST - ADC reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_ADC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRL1 - Peripheral reset control 1 */ -/*! @{ */ - -#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) -#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) -/*! MRT_RST - MRT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) - -#define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT (1U) -/*! OSTIMER_RST - OS Event Timer reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_OSTIMER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK) - -#define SYSCON_PRESETCTRL1_SCT_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL1_SCT_RST_SHIFT (2U) -/*! SCT_RST - SCT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_SCT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT_RST_MASK) - -#define SYSCON_PRESETCTRL1_CAN_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL1_CAN_RST_SHIFT (7U) -/*! CAN_RST - CAN reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_CAN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_CAN_RST_SHIFT)) & SYSCON_PRESETCTRL1_CAN_RST_MASK) - -#define SYSCON_PRESETCTRL1_UTICK_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT (10U) -/*! UTICK_RST - UTICK reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) -/*! FC0_RST - FC0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) -#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) -/*! FC1_RST - FC1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) -/*! FC2_RST - FC2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) -/*! FC3_RST - FC3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) -/*! FC4_RST - FC4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) -/*! FC5_RST - FC5 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) -/*! FC6_RST - FC6 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) -/*! FC7_RST - FC7 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) - -#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) -/*! TIMER2_RST - Timer 2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) - -#define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK (0x2000000U) -#define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT (25U) -/*! USB0_DEV_RST - USB0-FS DEV reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_USB0_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK) - -#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) -#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) -/*! TIMER0_RST - Timer 0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) - -#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) -/*! TIMER1_RST - Timer 1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRL2 - Peripheral reset control 2 */ -/*! @{ */ - -#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) -/*! DMA1_RST - DMA1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) - -#define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U) -/*! COMP_RST - Comparator reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_COMP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK (0x10U) -#define SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT (4U) -/*! USB1_HOST_RST - USB1-HS Host reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_HOST_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK (0x20U) -#define SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT (5U) -/*! USB1_DEV_RST - USB1-HS dev reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK (0x40U) -#define SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT (6U) -/*! USB1_RAM_RST - USB1-HS RAM reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT (7U) -/*! USB1_PHY_RST - USB1-HS PHY reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK) - -#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) -/*! FREQME_RST - Frequency meter reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) - -#define SYSCON_PRESETCTRL2_CDOG_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL2_CDOG_RST_SHIFT (11U) -/*! CDOG_RST - Code Watchdog reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_CDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CDOG_RST_SHIFT)) & SYSCON_PRESETCTRL2_CDOG_RST_MASK) - -#define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U) -/*! RNG_RST - RNG reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK) - -#define SYSCON_PRESETCTRL2_SYSCTL_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT (15U) -/*! SYSCTL_RST - SYSCTL Block reset. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_SYSCTL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT)) & SYSCON_PRESETCTRL2_SYSCTL_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT (16U) -/*! USB0_HOSTM_RST - USB0-FS Host Master reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT (17U) -/*! USB0_HOSTS_RST - USB0-FS Host Slave reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK) - -#define SYSCON_PRESETCTRL2_HASH_AES_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT (18U) -/*! HASH_AES_RST - HASH_AES reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_HASH_AES_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH_AES_RST_MASK) - -#define SYSCON_PRESETCTRL2_PLULUT_RST_MASK (0x100000U) -#define SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT (20U) -/*! PLULUT_RST - PLU LUT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_PLULUT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLULUT_RST_MASK) - -#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) -#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) -/*! TIMER3_RST - Timer 3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) - -#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) -/*! TIMER4_RST - Timer 4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) - -#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) -#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) -/*! PUF_RST - PUF reset control reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) - -#define SYSCON_PRESETCTRL2_CASPER_RST_MASK (0x1000000U) -#define SYSCON_PRESETCTRL2_CASPER_RST_SHIFT (24U) -/*! CASPER_RST - Casper reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_CASPER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CASPER_RST_SHIFT)) & SYSCON_PRESETCTRL2_CASPER_RST_MASK) - -#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT (27U) -/*! ANALOG_CTRL_RST - analog control reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK) - -#define SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK (0x10000000U) -#define SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT (28U) -/*! HS_LSPI_RST - HS LSPI reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_HS_LSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK) - -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U) -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U) -/*! GPIO_SEC_RST - GPIO secure reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK) - -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U) -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U) -/*! GPIO_SEC_INT_RST - GPIO secure int reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRLX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_PRESETCTRLX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_PRESETCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLX_DATA_SHIFT)) & SYSCON_PRESETCTRLX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLX */ -#define SYSCON_PRESETCTRLX_COUNT (3U) - -/*! @name PRESETCTRLSET - Peripheral reset control set register */ -/*! @{ */ - -#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLSET */ -#define SYSCON_PRESETCTRLSET_COUNT (3U) - -/*! @name PRESETCTRLCLR - Peripheral reset control clear register */ -/*! @{ */ - -#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLCLR */ -#define SYSCON_PRESETCTRLCLR_COUNT (3U) - -/*! @name SWR_RESET - generate a software_reset */ -/*! @{ */ - -#define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU) -#define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U) -/*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset. - * 0b01011010000000000000000000000001..Generate a software reset. - * 0b00000000000000000000000000000000..Bloc is not reset. - */ -#define SYSCON_SWR_RESET_SWR_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL0 - AHB Clock control 0 */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) -#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) -/*! ROM - Enables the clock for the ROM. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) - -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U) -/*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK) - -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U) -/*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK) - -#define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U) -#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U) -/*! FLASH - Enables the clock for the Flash controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK) - -#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U) -#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U) -/*! FMC - Enables the clock for the FMC controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) - -#define SYSCON_AHBCLKCTRL0_MUX_MASK (0x800U) -#define SYSCON_AHBCLKCTRL0_MUX_SHIFT (11U) -/*! MUX - Enables the clock for the Input Mux. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_MUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK) - -#define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U) -/*! IOCON - Enables the clock for the I/O controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK) - -#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U) -/*! GPIO0 - Enables the clock for the GPIO0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) - -#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U) -/*! GPIO1 - Enables the clock for the GPIO1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) - -#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U) -/*! PINT - Enables the clock for the Pin interrupt (PINT). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) - -#define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U) -/*! GINT - Enables the clock for the Group interrupt (GINT). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK) - -#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U) -#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U) -/*! DMA0 - Enables the clock for the DMA0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) - -#define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U) -#define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U) -/*! CRCGEN - Enables the clock for the CRCGEN. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK) - -#define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U) -/*! WWDT - Enables the clock for the Watchdog Timer. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK) - -#define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U) -#define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U) -/*! RTC - Enables the clock for the Real Time Clock (RTC). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK) - -#define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U) -/*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK) - -#define SYSCON_AHBCLKCTRL0_ADC_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL0_ADC_SHIFT (27U) -/*! ADC - Enables the clock for the ADC. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL1 - AHB Clock control 1 */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) -#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) -/*! MRT - Enables the clock for the MRT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) - -#define SYSCON_AHBCLKCTRL1_OSTIMER_MASK (0x2U) -#define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT (1U) -/*! OSTIMER - Enables the clock for the OS Event Timer. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK) - -#define SYSCON_AHBCLKCTRL1_SCT_MASK (0x4U) -#define SYSCON_AHBCLKCTRL1_SCT_SHIFT (2U) -/*! SCT - Enables the clock for the SCT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_SCT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT_MASK) - -#define SYSCON_AHBCLKCTRL1_CAN_MASK (0x80U) -#define SYSCON_AHBCLKCTRL1_CAN_SHIFT (7U) -/*! CAN - Enables the clock for the CAN. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_CAN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_CAN_SHIFT)) & SYSCON_AHBCLKCTRL1_CAN_MASK) - -#define SYSCON_AHBCLKCTRL1_UTICK_MASK (0x400U) -#define SYSCON_AHBCLKCTRL1_UTICK_SHIFT (10U) -/*! UTICK - Enables the clock for the UTICK. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK) - -#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) -#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) -/*! FC0 - Enables the clock for the FC0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) - -#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) -#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) -/*! FC1 - Enables the clock for the FC1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) - -#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) -/*! FC2 - Enables the clock for the FC2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) - -#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) -/*! FC3 - Enables the clock for the FC3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) - -#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) -/*! FC4 - Enables the clock for the FC4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) - -#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) -/*! FC5 - Enables the clock for the FC5. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) - -#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) -/*! FC6 - Enables the clock for the FC6. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) - -#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) -/*! FC7 - Enables the clock for the FC7. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) - -#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) -/*! TIMER2 - Enables the clock for the Timer 2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) - -#define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK (0x2000000U) -#define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT (25U) -/*! USB0_DEV - Enables the clock for the USB0-FS device. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_USB0_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK) - -#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) -/*! TIMER0 - Enables the clock for the Timer 0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) - -#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) -/*! TIMER1 - Enables the clock for the Timer 1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL2 - AHB Clock control 2 */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) -#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) -/*! DMA1 - Enables the clock for the DMA1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) - -#define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U) -#define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U) -/*! COMP - Enables the clock for the Comparator. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK) - -#define SYSCON_AHBCLKCTRL2_USB1_HOST_MASK (0x10U) -#define SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT (4U) -/*! USB1_HOST - Enables the clock for the USB1-HS Host. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_HOST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_HOST_MASK) - -#define SYSCON_AHBCLKCTRL2_USB1_DEV_MASK (0x20U) -#define SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT (5U) -/*! USB1_DEV - Enables the clock for the USB1-HS device. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_DEV_MASK) - -#define SYSCON_AHBCLKCTRL2_USB1_RAM_MASK (0x40U) -#define SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT (6U) -/*! USB1_RAM - Enables the clock for the USB1-HS RAM. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_RAM_MASK) - -#define SYSCON_AHBCLKCTRL2_USB1_PHY_MASK (0x80U) -#define SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT (7U) -/*! USB1_PHY - Enables the clock for the USB1-HS PHY. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_PHY_MASK) - -#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) -#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) -/*! FREQME - Enables the clock for the Frequency meter. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) - -#define SYSCON_AHBCLKCTRL2_CDOG_MASK (0x800U) -#define SYSCON_AHBCLKCTRL2_CDOG_SHIFT (11U) -/*! CDOG - Enables the clock for the code watchdog. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_CDOG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CDOG_SHIFT)) & SYSCON_AHBCLKCTRL2_CDOG_MASK) - -#define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U) -/*! RNG - Enables the clock for the RNG. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK) - -#define SYSCON_AHBCLKCTRL2_SYSCTL_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT (15U) -/*! SYSCTL - SYSCTL block clock. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_SYSCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT)) & SYSCON_AHBCLKCTRL2_SYSCTL_MASK) - -#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT (16U) -/*! USB0_HOSTM - Enables the clock for the USB0-FS Host Master. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK) - -#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT (17U) -/*! USB0_HOSTS - Enables the clock for the USB0-FS Host Slave. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK) - -#define SYSCON_AHBCLKCTRL2_HASH_AES_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT (18U) -/*! HASH_AES - Enables the clock for the HASH_AES. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH_AES_MASK) - -#define SYSCON_AHBCLKCTRL2_PLULUT_MASK (0x100000U) -#define SYSCON_AHBCLKCTRL2_PLULUT_SHIFT (20U) -/*! PLULUT - Enables the clock for the PLU LUT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PLULUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLULUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLULUT_MASK) - -#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) -#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) -/*! TIMER3 - Enables the clock for the Timer 3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) - -#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) -/*! TIMER4 - Enables the clock for the Timer 4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) - -#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) -#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) -/*! PUF - Enables the clock for the PUF reset control. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) - -#define SYSCON_AHBCLKCTRL2_CASPER_MASK (0x1000000U) -#define SYSCON_AHBCLKCTRL2_CASPER_SHIFT (24U) -/*! CASPER - Enables the clock for the Casper. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CASPER_SHIFT)) & SYSCON_AHBCLKCTRL2_CASPER_MASK) - -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U) -/*! ANALOG_CTRL - Enables the clock for the analog control. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK) - -#define SYSCON_AHBCLKCTRL2_HS_LSPI_MASK (0x10000000U) -#define SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT (28U) -/*! HS_LSPI - Enables the clock for the HS LSPI. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_LSPI_MASK) - -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U) -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U) -/*! GPIO_SEC - Enables the clock for the GPIO secure. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK) - -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U) -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U) -/*! GPIO_SEC_INT - Enables the clock for the GPIO secure int. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK) -/*! @} */ - -/*! @name AHBCLKCTRLX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRLX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_AHBCLKCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLX_DATA_SHIFT)) & SYSCON_AHBCLKCTRLX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLX */ -#define SYSCON_AHBCLKCTRLX_COUNT (3U) - -/*! @name AHBCLKCTRLSET - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLSET */ -#define SYSCON_AHBCLKCTRLSET_COUNT (3U) - -/*! @name AHBCLKCTRLCLR - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLCLR */ -#define SYSCON_AHBCLKCTRLCLR_COUNT (3U) - -/*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) -/*! SEL - System Tick Timer for CPU0 source select. - * 0b000..System Tick 0 divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKSELX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKSELX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_SYSTICKCLKSELX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_SYSTICKCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSELX_DATA_SHIFT)) & SYSCON_SYSTICKCLKSELX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_SYSTICKCLKSELX */ -#define SYSCON_SYSTICKCLKSELX_COUNT (1U) - -/*! @name TRACECLKSEL - Trace clock source select */ -/*! @{ */ - -#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) -#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) -/*! SEL - Trace clock source select. - * 0b000..Trace divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL0 - CTimer 0 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL0_SEL_SHIFT (0U) -/*! SEL - CTimer 0 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL0_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL1 - CTimer 1 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL1_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL1_SEL_SHIFT (0U) -/*! SEL - CTimer 1 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL1_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL1_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL2 - CTimer 2 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL2_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL2_SEL_SHIFT (0U) -/*! SEL - CTimer 2 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL2_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL2_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL3 - CTimer 3 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL3_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL3_SEL_SHIFT (0U) -/*! SEL - CTimer 3 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL3_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL3_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL4 - CTimer 4 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL4_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL4_SEL_SHIFT (0U) -/*! SEL - CTimer 4 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL4_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL4_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSELX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSELX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_CTIMERCLKSELX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_CTIMERCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSELX_DATA_SHIFT)) & SYSCON_CTIMERCLKSELX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_CTIMERCLKSELX */ -#define SYSCON_CTIMERCLKSELX_COUNT (5U) - -/*! @name MAINCLKSELA - Main clock A source select */ -/*! @{ */ - -#define SYSCON_MAINCLKSELA_SEL_MASK (0x7U) -#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) -/*! SEL - Main clock A source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..Reserved. - * 0b101..Reserved. - * 0b110..Reserved. - * 0b111..Reserved. - */ -#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) -/*! @} */ - -/*! @name MAINCLKSELB - Main clock source select */ -/*! @{ */ - -#define SYSCON_MAINCLKSELB_SEL_MASK (0x7U) -#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) -/*! SEL - Main clock source select. - * 0b000..Main Clock A. - * 0b001..PLL0 clock. - * 0b010..PLL1 clock. - * 0b011..Oscillator 32 kHz clock. - * 0b100..Reserved. - * 0b101..Reserved. - * 0b110..Reserved. - * 0b111..Reserved. - */ -#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) -/*! @} */ - -/*! @name CLKOUTSEL - CLKOUT clock source select */ -/*! @{ */ - -#define SYSCON_CLKOUTSEL_SEL_MASK (0xFU) -#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) -/*! SEL - CLKOUT clock source select. - * 0b0000..Main clock. - * 0b0001..PLL0 clock. - * 0b0010..CLKIN clock. - * 0b0011..FRO 96 MHz clock. - * 0b0100..FRO 1MHz clock. - * 0b0101..PLL1 clock. - * 0b0110..Oscillator 32kHz clock. - * 0b0111..No clock. - * 0b1000..Reserved. - * 0b1001..Reserved. - * 0b1010..Reserved. - * 0b1011..Reserved. - * 0b1100..No clock. - * 0b1101..No clock. - * 0b1110..No clock. - * 0b1111..No clock. - */ -#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) -/*! @} */ - -/*! @name PLL0CLKSEL - PLL0 clock source select */ -/*! @{ */ - -#define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U) -#define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U) -/*! SEL - PLL0 clock source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..Oscillator 32kHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_PLL0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name PLL1CLKSEL - PLL1 clock source select */ -/*! @{ */ - -#define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U) -#define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U) -/*! SEL - PLL1 clock source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..Oscillator 32kHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_PLL1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name CANCLKSEL - CAN clock source select */ -/*! @{ */ - -#define SYSCON_CANCLKSEL_SEL_MASK (0x7U) -#define SYSCON_CANCLKSEL_SEL_SHIFT (0U) -/*! SEL - CAN clock source select. - * 0b000..CAN divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_CANCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKSEL_SEL_SHIFT)) & SYSCON_CANCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name ADCCLKSEL - ADC clock source select */ -/*! @{ */ - -#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) -#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) -/*! SEL - ADC clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..FRO 96 MHz clock. - * 0b011..Reserved. - * 0b100..Xtal clock coming directly. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name USB0CLKSEL - FS USB clock source select */ -/*! @{ */ - -#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) -#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) -/*! SEL - FS USB clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..PLL1 clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name CLK32KCLKSEL - clock low speed source select for HS USB. */ -/*! @{ */ - -#define SYSCON_CLK32KCLKSEL_SEL_MASK (0x8U) -#define SYSCON_CLK32KCLKSEL_SEL_SHIFT (3U) -/*! SEL - clock low speed source select for HS USB. - * 0b0..Oscillator 32 kHz clock. - * 0b1..FRO1MHz_divided clock. - */ -#define SYSCON_CLK32KCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLK32KCLKSEL_SEL_SHIFT)) & SYSCON_CLK32KCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL0_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL0_SEL_SHIFT)) & SYSCON_FCCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL1_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL1_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL1_SEL_SHIFT)) & SYSCON_FCCLKSEL1_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL2_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL2_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL2_SEL_SHIFT)) & SYSCON_FCCLKSEL2_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL3_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL3_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL3_SEL_SHIFT)) & SYSCON_FCCLKSEL3_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL4_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL4_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL4_SEL_SHIFT)) & SYSCON_FCCLKSEL4_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL5_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL5_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL5_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL5_SEL_SHIFT)) & SYSCON_FCCLKSEL5_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL6_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL6_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL6_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL6_SEL_SHIFT)) & SYSCON_FCCLKSEL6_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL7_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL7_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL7_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL7_SEL_SHIFT)) & SYSCON_FCCLKSEL7_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSELX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_FCCLKSELX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_FCCLKSELX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_FCCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSELX_DATA_SHIFT)) & SYSCON_FCCLKSELX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_FCCLKSELX */ -#define SYSCON_FCCLKSELX_COUNT (8U) - -/*! @name HSLSPICLKSEL - HS LSPI clock source select */ -/*! @{ */ - -#define SYSCON_HSLSPICLKSEL_SEL_MASK (0x7U) -#define SYSCON_HSLSPICLKSEL_SEL_SHIFT (0U) -/*! SEL - HS LSPI clock source select. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..No clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_HSLSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HSLSPICLKSEL_SEL_SHIFT)) & SYSCON_HSLSPICLKSEL_SEL_MASK) -/*! @} */ - -/*! @name MCLKCLKSEL - MCLK clock source select */ -/*! @{ */ - -#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) -#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) -/*! SEL - MCLK clock source select. - * 0b000..FRO 96 MHz clock. - * 0b001..PLL0 clock. - * 0b010..Reserved. - * 0b011..Reserved. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SCTCLKSEL - SCTimer/PWM clock source select */ -/*! @{ */ - -#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) -#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) -/*! SEL - SCTimer/PWM clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..CLKIN clock. - * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..MCLK clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKDIV0_DIV_MASK (0xFFU) -#define SYSCON_SYSTICKCLKDIV0_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_SYSTICKCLKDIV0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV0_DIV_MASK) - -#define SYSCON_SYSTICKCLKDIV0_RESET_MASK (0x20000000U) -#define SYSCON_SYSTICKCLKDIV0_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SYSTICKCLKDIV0_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV0_RESET_MASK) - -#define SYSCON_SYSTICKCLKDIV0_HALT_MASK (0x40000000U) -#define SYSCON_SYSTICKCLKDIV0_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SYSTICKCLKDIV0_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV0_HALT_MASK) - -#define SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK (0x80000000U) -#define SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SYSTICKCLKDIV0_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK) -/*! @} */ - -/*! @name TRACECLKDIV - TRACE clock divider */ -/*! @{ */ - -#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) -#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) - -#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) - -#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) - -#define SYSCON_TRACECLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_TRACECLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_TRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_TRACECLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name CANCLKDIV - CAN clock divider */ -/*! @{ */ - -#define SYSCON_CANCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_CANCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_CANCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_DIV_SHIFT)) & SYSCON_CANCLKDIV_DIV_MASK) - -#define SYSCON_CANCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_CANCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_CANCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_RESET_SHIFT)) & SYSCON_CANCLKDIV_RESET_MASK) - -#define SYSCON_CANCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_CANCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_CANCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_HALT_SHIFT)) & SYSCON_CANCLKDIV_HALT_MASK) - -#define SYSCON_CANCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_CANCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_CANCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_REQFLAG_SHIFT)) & SYSCON_CANCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 */ -/*! @{ */ - -#define SYSCON_FLEXFRG0CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG0CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG0CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG0CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG0CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG0CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG0CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG0CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 */ -/*! @{ */ - -#define SYSCON_FLEXFRG1CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG1CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG1CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG1CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG1CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG1CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG1CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG1CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 */ -/*! @{ */ - -#define SYSCON_FLEXFRG2CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG2CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG2CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG2CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG2CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG2CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG2CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG2CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 */ -/*! @{ */ - -#define SYSCON_FLEXFRG3CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG3CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG3CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG3CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG3CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG3CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG3CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG3CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 */ -/*! @{ */ - -#define SYSCON_FLEXFRG4CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG4CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG4CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG4CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG4CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG4CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG4CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG4CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 */ -/*! @{ */ - -#define SYSCON_FLEXFRG5CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG5CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG5CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG5CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG5CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG5CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG5CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG5CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 */ -/*! @{ */ - -#define SYSCON_FLEXFRG6CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG6CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG6CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG6CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG6CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG6CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG6CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG6CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 */ -/*! @{ */ - -#define SYSCON_FLEXFRG7CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG7CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG7CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG7CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG7CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG7CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG7CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG7CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRGXCTRL - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_FLEXFRGXCTRL_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_FLEXFRGXCTRL_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_FLEXFRGXCTRL_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRGXCTRL_DATA_SHIFT)) & SYSCON_FLEXFRGXCTRL_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_FLEXFRGXCTRL */ -#define SYSCON_FLEXFRGXCTRL_COUNT (8U) - -/*! @name AHBCLKDIV - System clock divider */ -/*! @{ */ - -#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) - -#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) - -#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) - -#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name CLKOUTDIV - CLKOUT clock divider */ -/*! @{ */ - -#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) -#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) - -#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) -#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) - -#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) -#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) - -#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name FROHFDIV - FRO_HF (96MHz) clock divider */ -/*! @{ */ - -#define SYSCON_FROHFDIV_DIV_MASK (0xFFU) -#define SYSCON_FROHFDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) - -#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U) -#define SYSCON_FROHFDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK) - -#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) -#define SYSCON_FROHFDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) - -#define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_FROHFDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name WDTCLKDIV - WDT clock divider */ -/*! @{ */ - -#define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU) -#define SYSCON_WDTCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_WDTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK) - -#define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_WDTCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_WDTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK) - -#define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_WDTCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_WDTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK) - -#define SYSCON_WDTCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_WDTCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_WDTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_REQFLAG_SHIFT)) & SYSCON_WDTCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name ADCCLKDIV - ADC clock divider */ -/*! @{ */ - -#define SYSCON_ADCCLKDIV_DIV_MASK (0x7U) -#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) - -#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) - -#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) - -#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name USB0CLKDIV - USB0-FS Clock divider */ -/*! @{ */ - -#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) -#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) - -#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) - -#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) - -#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name FRO1MCLKDIV - FRO1MHz Clock divider (FRO1M_divided) */ -/*! @{ */ - -#define SYSCON_FRO1MCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_FRO1MCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_FRO1MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRO1MCLKDIV_DIV_SHIFT)) & SYSCON_FRO1MCLKDIV_DIV_MASK) - -#define SYSCON_FRO1MCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_FRO1MCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_FRO1MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRO1MCLKDIV_RESET_SHIFT)) & SYSCON_FRO1MCLKDIV_RESET_MASK) - -#define SYSCON_FRO1MCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_FRO1MCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_FRO1MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRO1MCLKDIV_HALT_SHIFT)) & SYSCON_FRO1MCLKDIV_HALT_MASK) - -#define SYSCON_FRO1MCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_FRO1MCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_FRO1MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRO1MCLKDIV_REQFLAG_SHIFT)) & SYSCON_FRO1MCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name MCLKDIV - I2S MCLK clock divider */ -/*! @{ */ - -#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_MCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) - -#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_MCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) - -#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_MCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) - -#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name SCTCLKDIV - SCT/PWM clock divider */ -/*! @{ */ - -#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) - -#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) - -#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) - -#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name PLL0CLKDIV - PLL0 clock divider */ -/*! @{ */ - -#define SYSCON_PLL0CLKDIV_DIV_MASK (0xFFU) -#define SYSCON_PLL0CLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_PLL0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_DIV_SHIFT)) & SYSCON_PLL0CLKDIV_DIV_MASK) - -#define SYSCON_PLL0CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_PLL0CLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_PLL0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_RESET_SHIFT)) & SYSCON_PLL0CLKDIV_RESET_MASK) - -#define SYSCON_PLL0CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_PLL0CLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_PLL0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_HALT_SHIFT)) & SYSCON_PLL0CLKDIV_HALT_MASK) - -#define SYSCON_PLL0CLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_PLL0CLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_PLL0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_REQFLAG_SHIFT)) & SYSCON_PLL0CLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) */ -/*! @{ */ - -#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK (0xFFFFFFFFU) -#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT (0U) -/*! CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (for example, xxxDIV, xxxSEL). - * 0b00000000000000000000000000000001..update all clock configuration. - * 0b00000000000000000000000000000000..all hardware clock configruration are freeze. - */ -#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK) -/*! @} */ - -/*! @name FMCCR - FMC configuration register */ -/*! @{ */ - -#define SYSCON_FMCCR_FETCHCFG_MASK (0x3U) -#define SYSCON_FMCCR_FETCHCFG_SHIFT (0U) -/*! FETCHCFG - Instruction fetch configuration. - * 0b00..Instruction fetches from flash are not buffered. - * 0b01..One buffer is used for all instruction fetches. - * 0b10..All buffers may be used for instruction fetches. - */ -#define SYSCON_FMCCR_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCFG_SHIFT)) & SYSCON_FMCCR_FETCHCFG_MASK) - -#define SYSCON_FMCCR_DATACFG_MASK (0xCU) -#define SYSCON_FMCCR_DATACFG_SHIFT (2U) -/*! DATACFG - Data read configuration. - * 0b00..Data accesses from flash are not buffered. - * 0b01..One buffer is used for all data accesses. - * 0b10..All buffers can be used for data accesses. - */ -#define SYSCON_FMCCR_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACFG_SHIFT)) & SYSCON_FMCCR_DATACFG_MASK) - -#define SYSCON_FMCCR_ACCEL_MASK (0x10U) -#define SYSCON_FMCCR_ACCEL_SHIFT (4U) -/*! ACCEL - Acceleration enable. - * 0b0..Flash acceleration is disabled. - * 0b1..Flash acceleration is enabled. - */ -#define SYSCON_FMCCR_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK) - -#define SYSCON_FMCCR_PREFEN_MASK (0x20U) -#define SYSCON_FMCCR_PREFEN_SHIFT (5U) -/*! PREFEN - Prefetch enable. - * 0b0..No instruction prefetch is performed. - * 0b1..Instruction prefetch is enabled. - */ -#define SYSCON_FMCCR_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK) - -#define SYSCON_FMCCR_PREFOVR_MASK (0x40U) -#define SYSCON_FMCCR_PREFOVR_SHIFT (6U) -/*! PREFOVR - Prefetch override. - * 0b0..Any previously initiated prefetch will be completed. - * 0b1..Any previously initiated prefetch will be aborted, and the next flash line following the current - * execution address will be prefetched if not already buffered. - */ -#define SYSCON_FMCCR_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK) - -#define SYSCON_FMCCR_FLASHTIM_MASK (0xF000U) -#define SYSCON_FMCCR_FLASHTIM_SHIFT (12U) -/*! FLASHTIM - Flash memory access time. - * 0b0000..1 system clock flash access time (for system clock rates up to 11 MHz). - * 0b0001..2 system clocks flash access time (for system clock rates up to 22 MHz). - * 0b0010..3 system clocks flash access time (for system clock rates up to 33 MHz). - * 0b0011..4 system clocks flash access time (for system clock rates up to 44 MHz). - * 0b0100..5 system clocks flash access time (for system clock rates up to 55 MHz). - * 0b0101..6 system clocks flash access time (for system clock rates up to 66 MHz). - * 0b0110..7 system clocks flash access time (for system clock rates up to 84 MHz). - * 0b0111..8 system clocks flash access time (for system clock rates up to 104 MHz). - * 0b1000..9 system clocks flash access time (for system clock rates up to 119 MHz). - * 0b1001..10 system clocks flash access time (for system clock rates up to 129 MHz). - * 0b1010..11 system clocks flash access time (for system clock rates up to 144 MHz). - * 0b1011..12 system clocks flash access time (for system clock rates up to 150 MHz). - */ -#define SYSCON_FMCCR_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FLASHTIM_SHIFT)) & SYSCON_FMCCR_FLASHTIM_MASK) -/*! @} */ - -/*! @name USB0NEEDCLKCTRL - USB0-FS need clock control */ -/*! @{ */ - -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK (0x1U) -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT (0U) -/*! AP_FS_DEV_NEEDCLK - USB0-FS Device USB0_NEEDCLK signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. - */ -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK) - -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK (0x2U) -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT (1U) -/*! POL_FS_DEV_NEEDCLK - USB0-FS Device USB0_NEEDCLK polarity for triggering the USB0-FS wake-up interrupt:. - * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. - * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK) - -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK (0x4U) -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT (2U) -/*! AP_FS_HOST_NEEDCLK - USB0-FS Host USB0_NEEDCLK signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. - */ -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK) - -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK (0x8U) -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT (3U) -/*! POL_FS_HOST_NEEDCLK - USB0-FS Host USB0_NEEDCLK polarity for triggering the USB0-FS wake-up interrupt:. - * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. - * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK) -/*! @} */ - -/*! @name USB0NEEDCLKSTAT - USB0-FS need clock status */ -/*! @{ */ - -#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) -#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) -/*! DEV_NEEDCLK - USB0-FS Device USB0_NEEDCLK signal status:. - * 0b1..USB0-FS Device clock is high. - * 0b0..USB0-FS Device clock is low. - */ -#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK) - -#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) -#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) -/*! HOST_NEEDCLK - USB0-FS Host USB0_NEEDCLK signal status:. - * 0b1..USB0-FS Host clock is high. - * 0b0..USB0-FS Host clock is low. - */ -#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK) -/*! @} */ - -/*! @name FMCFLUSH - FMCflush control */ -/*! @{ */ - -#define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U) -#define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U) -/*! FLUSH - Flush control - * 0b1..Flush the FMC buffer contents. - * 0b0..No action is performed. - */ -#define SYSCON_FMCFLUSH_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK) -/*! @} */ - -/*! @name MCLKIO - MCLK control */ -/*! @{ */ - -#define SYSCON_MCLKIO_MCLKIO_MASK (0x1U) -#define SYSCON_MCLKIO_MCLKIO_SHIFT (0U) -/*! MCLKIO - MCLK control. - * 0b0..input mode. - * 0b1..output mode. - */ -#define SYSCON_MCLKIO_MCLKIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK) -/*! @} */ - -/*! @name USB1NEEDCLKCTRL - USB1-HS need clock control */ -/*! @{ */ - -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK (0x1U) -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT (0U) -/*! AP_HS_DEV_NEEDCLK - USB1-HS Device need_clock signal control: - * 0b0..HOST_NEEDCLK is under hardware control. - * 0b1..HOST_NEEDCLK is forced high. - */ -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK) - -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK (0x2U) -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT (1U) -/*! POL_HS_DEV_NEEDCLK - USB1-HS device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt: - * 0b0..Falling edge of DEV_NEEDCLK triggers wake-up. - * 0b1..Rising edge of DEV_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK) - -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK (0x4U) -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT (2U) -/*! AP_HS_HOST_NEEDCLK - USB1-HS Host need clock signal control: - * 0b0..HOST_NEEDCLK is under hardware control. - * 0b1..HOST_NEEDCLK is forced high. - */ -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK) - -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK (0x8U) -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT (3U) -/*! POL_HS_HOST_NEEDCLK - USB1-HS host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. - * 0b0..Falling edge of HOST_NEEDCLK triggers wake-up. - * 0b1..Rising edge of HOST_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK) - -#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U) -#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U) -/*! HS_DEV_WAKEUP_N - Software override of device controller PHY wake up logic. - * 0b0..Forces USB1_PHY to wake-up. - * 0b1..Normal USB1_PHY behavior. - */ -#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK) -/*! @} */ - -/*! @name USB1NEEDCLKSTAT - USB1-HS need clock status */ -/*! @{ */ - -#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) -#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) -/*! DEV_NEEDCLK - USB1-HS Device need_clock signal status:. - * 0b1..DEV_NEEDCLK is high. - * 0b0..DEV_NEEDCLK is low. - */ -#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK) - -#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) -#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) -/*! HOST_NEEDCLK - USB1-HS Host need_clock signal status:. - * 0b1..HOST_NEEDCLK is high. - * 0b0..HOST_NEEDCLK is low. - */ -#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK) -/*! @} */ - -/*! @name FLASHREMAP_SIZE - This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB. */ -/*! @{ */ - -#define SYSCON_FLASHREMAP_SIZE_FLASHREMAP_SIZE_MASK (0xFFFFFFFFU) -#define SYSCON_FLASHREMAP_SIZE_FLASHREMAP_SIZE_SHIFT (0U) -#define SYSCON_FLASHREMAP_SIZE_FLASHREMAP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHREMAP_SIZE_FLASHREMAP_SIZE_SHIFT)) & SYSCON_FLASHREMAP_SIZE_FLASHREMAP_SIZE_MASK) -/*! @} */ - -/*! @name FLASHREMAP_SIZE_DP - This 32-bit register is a duplicate of FLASHREMAPSIZE for increased security. */ -/*! @{ */ - -#define SYSCON_FLASHREMAP_SIZE_DP_FLASHREMAP_SIZE_MASK (0xFFFFFFFFU) -#define SYSCON_FLASHREMAP_SIZE_DP_FLASHREMAP_SIZE_SHIFT (0U) -#define SYSCON_FLASHREMAP_SIZE_DP_FLASHREMAP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHREMAP_SIZE_DP_FLASHREMAP_SIZE_SHIFT)) & SYSCON_FLASHREMAP_SIZE_DP_FLASHREMAP_SIZE_MASK) -/*! @} */ - -/*! @name FLASHREMAP_OFFSET - This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB. */ -/*! @{ */ - -#define SYSCON_FLASHREMAP_OFFSET_FLASHREMAP_OFFSET_MASK (0xFFFFFFFFU) -#define SYSCON_FLASHREMAP_OFFSET_FLASHREMAP_OFFSET_SHIFT (0U) -#define SYSCON_FLASHREMAP_OFFSET_FLASHREMAP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHREMAP_OFFSET_FLASHREMAP_OFFSET_SHIFT)) & SYSCON_FLASHREMAP_OFFSET_FLASHREMAP_OFFSET_MASK) -/*! @} */ - -/*! @name FLASHREMAP_OFFSET_DP - This 32-bit register is a duplicate of FLASHREMAPOFFSET for increased security. */ -/*! @{ */ - -#define SYSCON_FLASHREMAP_OFFSET_DP_FLASHREMAP_OFFSET_MASK (0xFFFFFFFFU) -#define SYSCON_FLASHREMAP_OFFSET_DP_FLASHREMAP_OFFSET_SHIFT (0U) -#define SYSCON_FLASHREMAP_OFFSET_DP_FLASHREMAP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHREMAP_OFFSET_DP_FLASHREMAP_OFFSET_SHIFT)) & SYSCON_FLASHREMAP_OFFSET_DP_FLASHREMAP_OFFSET_MASK) -/*! @} */ - -/*! @name FLASHREMAP_LOCK - Control write access to FLASHREMAP_SIZE and FLASHREMAP_OFFSET registers. */ -/*! @{ */ - -#define SYSCON_FLASHREMAP_LOCK_LOCK_MASK (0xFFFFFFFFU) -#define SYSCON_FLASHREMAP_LOCK_LOCK_SHIFT (0U) -/*! LOCK - Control write access to FLASHREMAP_SIZE and FLASHREMAP_OFFSET registers. Any value other - * than 0xC33CA55A and 0x3CC35AA5 does not modify the state. - * 0b00111100110000110101101010100101..Write access to 4 registers FLASHREMAP_SIZE* and FLASHREMAP_OFFSET* is unlocked. - * 0b11000011001111001010010101011010..Write access to 4 registers FLASHREMAP_SIZE* and FLASHREMAP_OFFSET* is locked. - */ -#define SYSCON_FLASHREMAP_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHREMAP_LOCK_LOCK_SHIFT)) & SYSCON_FLASHREMAP_LOCK_LOCK_MASK) -/*! @} */ - -/*! @name CASPER_CTRL - Control CASPER integration. */ -/*! @{ */ - -#define SYSCON_CASPER_CTRL_INTERLEAVE_MASK (0x1U) -#define SYSCON_CASPER_CTRL_INTERLEAVE_SHIFT (0U) -/*! INTERLEAVE - Control RAM access for RAMX0 and RAMX1. - * 0b1..RAM access to RAMX0 and RAMX1 is interleaved. - * 0b0..RAM access to RAMX0 and RAMX1 is consecutive. - */ -#define SYSCON_CASPER_CTRL_INTERLEAVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CASPER_CTRL_INTERLEAVE_SHIFT)) & SYSCON_CASPER_CTRL_INTERLEAVE_MASK) -/*! @} */ - -/*! @name PLL1CTRL - PLL1 550m control */ -/*! @{ */ - -#define SYSCON_PLL1CTRL_SELR_MASK (0xFU) -#define SYSCON_PLL1CTRL_SELR_SHIFT (0U) -/*! SELR - Bandwidth select R value. - */ -#define SYSCON_PLL1CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK) - -#define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U) -#define SYSCON_PLL1CTRL_SELI_SHIFT (4U) -/*! SELI - Bandwidth select I value. - */ -#define SYSCON_PLL1CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK) - -#define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U) -#define SYSCON_PLL1CTRL_SELP_SHIFT (10U) -/*! SELP - Bandwidth select P value. - */ -#define SYSCON_PLL1CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U) -#define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U) -/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - * 0b1..PLL input clock is sent directly to the PLL output. - * 0b0..use PLL. - */ -#define SYSCON_PLL1CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U) -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U) -/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - * 0b1..bypass of the divide-by-2 divider in the post-divider. - * 0b0..use the divide-by-2 divider in the post-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) - -#define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U) -#define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U) -/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. - */ -#define SYSCON_PLL1CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK) - -#define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U) -#define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U) -/*! BWDIRECT - control of the bandwidth of the PLL. - * 0b1..modify the bandwidth of the PLL directly. - * 0b0..the bandwidth is changed synchronously with the feedback-divider. - */ -#define SYSCON_PLL1CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U) -#define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U) -/*! BYPASSPREDIV - bypass of the pre-divider. - * 0b1..bypass of the pre-divider. - * 0b0..use the pre-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U) -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U) -/*! BYPASSPOSTDIV - bypass of the post-divider. - * 0b1..bypass of the post-divider. - * 0b0..use the post-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) - -#define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U) -#define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U) -/*! CLKEN - enable the output clock. - * 0b1..Enable the output clock. - * 0b0..Disable the output clock. - */ -#define SYSCON_PLL1CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK) - -#define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U) -#define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U) -/*! FRMEN - 1: free running mode. - */ -#define SYSCON_PLL1CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK) - -#define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U) -#define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U) -/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable. - */ -#define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK) - -#define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U) -#define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U) -/*! SKEWEN - Skew mode. - * 0b1..skewmode is enable. - * 0b0..skewmode is disable. - */ -#define SYSCON_PLL1CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK) -/*! @} */ - -/*! @name PLL1STAT - PLL1 550m status */ -/*! @{ */ - -#define SYSCON_PLL1STAT_LOCK_MASK (0x1U) -#define SYSCON_PLL1STAT_LOCK_SHIFT (0U) -/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. - */ -#define SYSCON_PLL1STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK) - -#define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U) -#define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U) -/*! PREDIVACK - pre-divider ratio change acknowledge. - */ -#define SYSCON_PLL1STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK) - -#define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U) -#define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U) -/*! FEEDDIVACK - feedback divider ratio change acknowledge. - */ -#define SYSCON_PLL1STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK) - -#define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U) -#define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U) -/*! POSTDIVACK - post-divider ratio change acknowledge. - */ -#define SYSCON_PLL1STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK) - -#define SYSCON_PLL1STAT_FRMDET_MASK (0x10U) -#define SYSCON_PLL1STAT_FRMDET_SHIFT (4U) -/*! FRMDET - free running detector output (active high). - */ -#define SYSCON_PLL1STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK) -/*! @} */ - -/*! @name PLL1NDEC - PLL1 550m N divider */ -/*! @{ */ - -#define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU) -#define SYSCON_PLL1NDEC_NDIV_SHIFT (0U) -/*! NDIV - pre-divider divider ratio (N-divider). - */ -#define SYSCON_PLL1NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK) - -#define SYSCON_PLL1NDEC_NREQ_MASK (0x100U) -#define SYSCON_PLL1NDEC_NREQ_SHIFT (8U) -/*! NREQ - pre-divider ratio change request. - */ -#define SYSCON_PLL1NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK) -/*! @} */ - -/*! @name PLL1MDEC - PLL1 550m M divider */ -/*! @{ */ - -#define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU) -#define SYSCON_PLL1MDEC_MDIV_SHIFT (0U) -/*! MDIV - feedback divider divider ratio (M-divider). - */ -#define SYSCON_PLL1MDEC_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK) - -#define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U) -#define SYSCON_PLL1MDEC_MREQ_SHIFT (16U) -/*! MREQ - feedback ratio change request. - */ -#define SYSCON_PLL1MDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK) -/*! @} */ - -/*! @name PLL1PDEC - PLL1 550m P divider */ -/*! @{ */ - -#define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU) -#define SYSCON_PLL1PDEC_PDIV_SHIFT (0U) -/*! PDIV - post-divider divider ratio (P-divider) - */ -#define SYSCON_PLL1PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK) - -#define SYSCON_PLL1PDEC_PREQ_MASK (0x20U) -#define SYSCON_PLL1PDEC_PREQ_SHIFT (5U) -/*! PREQ - feedback ratio change request. - */ -#define SYSCON_PLL1PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK) -/*! @} */ - -/*! @name PLL0CTRL - PLL0 550m control */ -/*! @{ */ - -#define SYSCON_PLL0CTRL_SELR_MASK (0xFU) -#define SYSCON_PLL0CTRL_SELR_SHIFT (0U) -/*! SELR - Bandwidth select R value. - */ -#define SYSCON_PLL0CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK) - -#define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U) -#define SYSCON_PLL0CTRL_SELI_SHIFT (4U) -/*! SELI - Bandwidth select I value. - */ -#define SYSCON_PLL0CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK) - -#define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U) -#define SYSCON_PLL0CTRL_SELP_SHIFT (10U) -/*! SELP - Bandwidth select P value. - */ -#define SYSCON_PLL0CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U) -#define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U) -/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - * 0b1..Bypass PLL input clock is sent directly to the PLL output. - * 0b0..use PLL. - */ -#define SYSCON_PLL0CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U) -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U) -/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - * 0b1..bypass of the divide-by-2 divider in the post-divider. - * 0b0..use the divide-by-2 divider in the post-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) - -#define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U) -#define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U) -/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. - */ -#define SYSCON_PLL0CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK) - -#define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U) -#define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U) -/*! BWDIRECT - Control of the bandwidth of the PLL. - * 0b1..modify the bandwidth of the PLL directly. - * 0b0..the bandwidth is changed synchronously with the feedback-divider. - */ -#define SYSCON_PLL0CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U) -#define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U) -/*! BYPASSPREDIV - bypass of the pre-divider. - * 0b1..bypass of the pre-divider. - * 0b0..use the pre-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U) -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U) -/*! BYPASSPOSTDIV - bypass of the post-divider. - * 0b1..bypass of the post-divider. - * 0b0..use the post-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) - -#define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U) -#define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U) -/*! CLKEN - enable the output clock. - * 0b1..enable the output clock. - * 0b0..disable the output clock. - */ -#define SYSCON_PLL0CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK) - -#define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U) -#define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U) -/*! FRMEN - free running mode. - * 0b1..free running mode is enable. - * 0b0..free running mode is disable. - */ -#define SYSCON_PLL0CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK) - -#define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U) -#define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U) -/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable. - */ -#define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK) - -#define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U) -#define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U) -/*! SKEWEN - skew mode. - * 0b1..skew mode is enable. - * 0b0..skew mode is disable. - */ -#define SYSCON_PLL0CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK) -/*! @} */ - -/*! @name PLL0STAT - PLL0 550m status */ -/*! @{ */ - -#define SYSCON_PLL0STAT_LOCK_MASK (0x1U) -#define SYSCON_PLL0STAT_LOCK_SHIFT (0U) -/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. - */ -#define SYSCON_PLL0STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK) - -#define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U) -#define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U) -/*! PREDIVACK - pre-divider ratio change acknowledge. - */ -#define SYSCON_PLL0STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK) - -#define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U) -#define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U) -/*! FEEDDIVACK - feedback divider ratio change acknowledge. - */ -#define SYSCON_PLL0STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK) - -#define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U) -#define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U) -/*! POSTDIVACK - post-divider ratio change acknowledge. - */ -#define SYSCON_PLL0STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK) - -#define SYSCON_PLL0STAT_FRMDET_MASK (0x10U) -#define SYSCON_PLL0STAT_FRMDET_SHIFT (4U) -/*! FRMDET - free running detector output (active high). - */ -#define SYSCON_PLL0STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK) -/*! @} */ - -/*! @name PLL0NDEC - PLL0 550m N divider */ -/*! @{ */ - -#define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU) -#define SYSCON_PLL0NDEC_NDIV_SHIFT (0U) -/*! NDIV - pre-divider divider ratio (N-divider). - */ -#define SYSCON_PLL0NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK) - -#define SYSCON_PLL0NDEC_NREQ_MASK (0x100U) -#define SYSCON_PLL0NDEC_NREQ_SHIFT (8U) -/*! NREQ - pre-divider ratio change request. - */ -#define SYSCON_PLL0NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK) -/*! @} */ - -/*! @name PLL0PDEC - PLL0 550m P divider */ -/*! @{ */ - -#define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU) -#define SYSCON_PLL0PDEC_PDIV_SHIFT (0U) -/*! PDIV - post-divider divider ratio (P-divider) - */ -#define SYSCON_PLL0PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK) - -#define SYSCON_PLL0PDEC_PREQ_MASK (0x20U) -#define SYSCON_PLL0PDEC_PREQ_SHIFT (5U) -/*! PREQ - feedback ratio change request. - */ -#define SYSCON_PLL0PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK) -/*! @} */ - -/*! @name PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 */ -/*! @{ */ - -#define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU) -#define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U) -/*! MD_LBS - input word of the wrapper bit 31 to 0. - */ -#define SYSCON_PLL0SSCG0_MD_LBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK) -/*! @} */ - -/*! @name PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 */ -/*! @{ */ - -#define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U) -#define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U) -/*! MD_MBS - input word of the wrapper bit 32. - */ -#define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK) - -#define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U) -#define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U) -/*! MD_REQ - md change request. - */ -#define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK) - -#define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) -#define SYSCON_PLL0SSCG1_MF_SHIFT (2U) -/*! MF - programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3. - */ -#define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK) - -#define SYSCON_PLL0SSCG1_MR_MASK (0xE0U) -#define SYSCON_PLL0SSCG1_MR_SHIFT (5U) -/*! MR - programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) - * mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1. - */ -#define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK) - -#define SYSCON_PLL0SSCG1_MC_MASK (0x300U) -#define SYSCON_PLL0SSCG1_MC_SHIFT (8U) -/*! MC - modulation waveform control Compensation for low pass filtering of the PLL to get a - * triangular modulation at the output of the PLL, giving a flat frequency spectrum. - */ -#define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK) - -#define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U) -#define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U) -/*! MDIV_EXT - to select an external mdiv value. - */ -#define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) - -#define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U) -#define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U) -/*! MREQ - to select an external mreq value. - */ -#define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK) - -#define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U) -#define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U) -/*! DITHER - dithering between two modulation frequencies in a random way or in a pseudo random way - * (white noise), in order to decrease the probability that the modulated waveform will occur - * with the same phase on a particular point on the screen. - */ -#define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK) - -#define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U) -#define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U) -/*! SEL_EXT - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext. - */ -#define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK) -/*! @} */ - -/*! @name FUNCRETENTIONCTRL - Functional retention control register */ -/*! @{ */ - -#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK (0x1U) -#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT (0U) -/*! FUNCRETENA - functional retention in power down only. - * 0b1..enable functional retention. - * 0b0..disable functional retention. - */ -#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK) - -#define SYSCON_FUNCRETENTIONCTRL_RET_START_MASK (0x3FFEU) -#define SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT (1U) -/*! RET_START - Start address divided by 4 inside SRAMX bank. - */ -#define SYSCON_FUNCRETENTIONCTRL_RET_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_START_MASK) - -#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK (0xFFC000U) -#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT (14U) -/*! RET_LENTH - lenth of Scan chains to save. - */ -#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) -/*! @} */ - -/*! @name CPSTAT - CPU Status */ -/*! @{ */ - -#define SYSCON_CPSTAT_CPU0SLEEPING_MASK (0x1U) -#define SYSCON_CPSTAT_CPU0SLEEPING_SHIFT (0U) -/*! CPU0SLEEPING - The CPU0 sleeping state. - * 0b1..the CPU is sleeping. - * 0b0..the CPU is not sleeping. - */ -#define SYSCON_CPSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU0SLEEPING_MASK) - -#define SYSCON_CPSTAT_CPU0LOCKUP_MASK (0x4U) -#define SYSCON_CPSTAT_CPU0LOCKUP_SHIFT (2U) -/*! CPU0LOCKUP - The CPU0 lockup state. - * 0b1..the CPU is in lockup. - * 0b0..the CPU is not in lockup. - */ -#define SYSCON_CPSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU0LOCKUP_MASK) -/*! @} */ - -/*! @name BOOT_SEED_REG0 - boot seed (256-bit random value) */ -/*! @{ */ - -#define SYSCON_BOOT_SEED_REG0_BOOT_SEED_REG0_MASK (0xFFFFFFFFU) -#define SYSCON_BOOT_SEED_REG0_BOOT_SEED_REG0_SHIFT (0U) -#define SYSCON_BOOT_SEED_REG0_BOOT_SEED_REG0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG0_BOOT_SEED_REG0_SHIFT)) & SYSCON_BOOT_SEED_REG0_BOOT_SEED_REG0_MASK) -/*! @} */ - -/*! @name BOOT_SEED_REG1 - boot seed (256-bit random value) */ -/*! @{ */ - -#define SYSCON_BOOT_SEED_REG1_BOOT_SEED_REG1_MASK (0xFFFFFFFFU) -#define SYSCON_BOOT_SEED_REG1_BOOT_SEED_REG1_SHIFT (0U) -#define SYSCON_BOOT_SEED_REG1_BOOT_SEED_REG1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG1_BOOT_SEED_REG1_SHIFT)) & SYSCON_BOOT_SEED_REG1_BOOT_SEED_REG1_MASK) -/*! @} */ - -/*! @name BOOT_SEED_REG2 - boot seed (256-bit random value) */ -/*! @{ */ - -#define SYSCON_BOOT_SEED_REG2_BOOT_SEED_REG2_MASK (0xFFFFFFFFU) -#define SYSCON_BOOT_SEED_REG2_BOOT_SEED_REG2_SHIFT (0U) -#define SYSCON_BOOT_SEED_REG2_BOOT_SEED_REG2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG2_BOOT_SEED_REG2_SHIFT)) & SYSCON_BOOT_SEED_REG2_BOOT_SEED_REG2_MASK) -/*! @} */ - -/*! @name BOOT_SEED_REG3 - boot seed (256-bit random value) */ -/*! @{ */ - -#define SYSCON_BOOT_SEED_REG3_BOOT_SEED_REG3_MASK (0xFFFFFFFFU) -#define SYSCON_BOOT_SEED_REG3_BOOT_SEED_REG3_SHIFT (0U) -#define SYSCON_BOOT_SEED_REG3_BOOT_SEED_REG3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG3_BOOT_SEED_REG3_SHIFT)) & SYSCON_BOOT_SEED_REG3_BOOT_SEED_REG3_MASK) -/*! @} */ - -/*! @name BOOT_SEED_REG4 - boot seed (256-bit random value) */ -/*! @{ */ - -#define SYSCON_BOOT_SEED_REG4_BOOT_SEED_REG4_MASK (0xFFFFFFFFU) -#define SYSCON_BOOT_SEED_REG4_BOOT_SEED_REG4_SHIFT (0U) -#define SYSCON_BOOT_SEED_REG4_BOOT_SEED_REG4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG4_BOOT_SEED_REG4_SHIFT)) & SYSCON_BOOT_SEED_REG4_BOOT_SEED_REG4_MASK) -/*! @} */ - -/*! @name BOOT_SEED_REG5 - boot seed (256-bit random value) */ -/*! @{ */ - -#define SYSCON_BOOT_SEED_REG5_BOOT_SEED_REG5_MASK (0xFFFFFFFFU) -#define SYSCON_BOOT_SEED_REG5_BOOT_SEED_REG5_SHIFT (0U) -#define SYSCON_BOOT_SEED_REG5_BOOT_SEED_REG5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG5_BOOT_SEED_REG5_SHIFT)) & SYSCON_BOOT_SEED_REG5_BOOT_SEED_REG5_MASK) -/*! @} */ - -/*! @name BOOT_SEED_REG6 - boot seed (256-bit random value) */ -/*! @{ */ - -#define SYSCON_BOOT_SEED_REG6_BOOT_SEED_REG6_MASK (0xFFFFFFFFU) -#define SYSCON_BOOT_SEED_REG6_BOOT_SEED_REG6_SHIFT (0U) -#define SYSCON_BOOT_SEED_REG6_BOOT_SEED_REG6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG6_BOOT_SEED_REG6_SHIFT)) & SYSCON_BOOT_SEED_REG6_BOOT_SEED_REG6_MASK) -/*! @} */ - -/*! @name BOOT_SEED_REG7 - boot seed (256-bit random value) */ -/*! @{ */ - -#define SYSCON_BOOT_SEED_REG7_BOOT_SEED_REG7_MASK (0xFFFFFFFFU) -#define SYSCON_BOOT_SEED_REG7_BOOT_SEED_REG7_SHIFT (0U) -#define SYSCON_BOOT_SEED_REG7_BOOT_SEED_REG7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG7_BOOT_SEED_REG7_SHIFT)) & SYSCON_BOOT_SEED_REG7_BOOT_SEED_REG7_MASK) -/*! @} */ - -/*! @name HMAC_REG0 - HMAC */ -/*! @{ */ - -#define SYSCON_HMAC_REG0_HMAC_REG0_MASK (0xFFFFFFFFU) -#define SYSCON_HMAC_REG0_HMAC_REG0_SHIFT (0U) -#define SYSCON_HMAC_REG0_HMAC_REG0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG0_HMAC_REG0_SHIFT)) & SYSCON_HMAC_REG0_HMAC_REG0_MASK) -/*! @} */ - -/*! @name HMAC_REG1 - HMAC */ -/*! @{ */ - -#define SYSCON_HMAC_REG1_HMAC_REG1_MASK (0xFFFFFFFFU) -#define SYSCON_HMAC_REG1_HMAC_REG1_SHIFT (0U) -#define SYSCON_HMAC_REG1_HMAC_REG1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG1_HMAC_REG1_SHIFT)) & SYSCON_HMAC_REG1_HMAC_REG1_MASK) -/*! @} */ - -/*! @name HMAC_REG2 - HMAC */ -/*! @{ */ - -#define SYSCON_HMAC_REG2_HMAC_REG2_MASK (0xFFFFFFFFU) -#define SYSCON_HMAC_REG2_HMAC_REG2_SHIFT (0U) -#define SYSCON_HMAC_REG2_HMAC_REG2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG2_HMAC_REG2_SHIFT)) & SYSCON_HMAC_REG2_HMAC_REG2_MASK) -/*! @} */ - -/*! @name HMAC_REG3 - HMAC */ -/*! @{ */ - -#define SYSCON_HMAC_REG3_HMAC_REG3_MASK (0xFFFFFFFFU) -#define SYSCON_HMAC_REG3_HMAC_REG3_SHIFT (0U) -#define SYSCON_HMAC_REG3_HMAC_REG3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG3_HMAC_REG3_SHIFT)) & SYSCON_HMAC_REG3_HMAC_REG3_MASK) -/*! @} */ - -/*! @name HMAC_REG4 - HMAC */ -/*! @{ */ - -#define SYSCON_HMAC_REG4_HMAC_REG4_MASK (0xFFFFFFFFU) -#define SYSCON_HMAC_REG4_HMAC_REG4_SHIFT (0U) -#define SYSCON_HMAC_REG4_HMAC_REG4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG4_HMAC_REG4_SHIFT)) & SYSCON_HMAC_REG4_HMAC_REG4_MASK) -/*! @} */ - -/*! @name HMAC_REG5 - HMAC */ -/*! @{ */ - -#define SYSCON_HMAC_REG5_HMAC_REG5_MASK (0xFFFFFFFFU) -#define SYSCON_HMAC_REG5_HMAC_REG5_SHIFT (0U) -#define SYSCON_HMAC_REG5_HMAC_REG5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG5_HMAC_REG5_SHIFT)) & SYSCON_HMAC_REG5_HMAC_REG5_MASK) -/*! @} */ - -/*! @name HMAC_REG6 - HMAC */ -/*! @{ */ - -#define SYSCON_HMAC_REG6_HMAC_REG6_MASK (0xFFFFFFFFU) -#define SYSCON_HMAC_REG6_HMAC_REG6_SHIFT (0U) -#define SYSCON_HMAC_REG6_HMAC_REG6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG6_HMAC_REG6_SHIFT)) & SYSCON_HMAC_REG6_HMAC_REG6_MASK) -/*! @} */ - -/*! @name HMAC_REG7 - HMAC */ -/*! @{ */ - -#define SYSCON_HMAC_REG7_HMAC_REG7_MASK (0xFFFFFFFFU) -#define SYSCON_HMAC_REG7_HMAC_REG7_SHIFT (0U) -#define SYSCON_HMAC_REG7_HMAC_REG7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG7_HMAC_REG7_SHIFT)) & SYSCON_HMAC_REG7_HMAC_REG7_MASK) -/*! @} */ - -/*! @name BOOT_LOCK - Control write access to boot seed security registers. */ -/*! @{ */ - -#define SYSCON_BOOT_LOCK_LOCK_BOOT_SEED_MASK (0x1U) -#define SYSCON_BOOT_LOCK_LOCK_BOOT_SEED_SHIFT (0U) -/*! LOCK_BOOT_SEED - Control write access to BOOT_SEED_REG registers. - * 0b1..write access to all 8 registers BOOT_SEED_REG is locked. This register is write once. - */ -#define SYSCON_BOOT_LOCK_LOCK_BOOT_SEED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_LOCK_LOCK_BOOT_SEED_SHIFT)) & SYSCON_BOOT_LOCK_LOCK_BOOT_SEED_MASK) - -#define SYSCON_BOOT_LOCK_LOCK_HMAC_MASK (0x2U) -#define SYSCON_BOOT_LOCK_LOCK_HMAC_SHIFT (1U) -/*! LOCK_HMAC - Control write access to HMAC_REG registers. - * 0b1..write access to all 8 registers HMAC_REG is locked. This register is write once. - */ -#define SYSCON_BOOT_LOCK_LOCK_HMAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_LOCK_LOCK_HMAC_SHIFT)) & SYSCON_BOOT_LOCK_LOCK_HMAC_MASK) -/*! @} */ - -/*! @name CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures */ -/*! @{ */ - -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U) -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U) -/*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U) -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U) -/*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U) -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U) -/*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U) -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U) -/*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) -#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) -/*! CLKIN_ENA - Enable clock_in clock for clock module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) -/*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U) -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U) -/*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U) -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U) -/*! XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U) -#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U) -/*! PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK) -/*! @} */ - -/*! @name COMP_INT_CTRL - Comparator Interrupt control */ -/*! @{ */ - -#define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U) -#define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U) -/*! INT_ENABLE - Analog Comparator interrupt enable control:. - * 0b1..interrupt enable. - * 0b0..interrupt disable. - */ -#define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK) - -#define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U) -#define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U) -/*! INT_CLEAR - Analog Comparator interrupt clear. - * 0b0..No effect. - * 0b1..Clear the interrupt. Self-cleared bit. - */ -#define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK) - -#define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU) -#define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U) -/*! INT_CTRL - Comparator interrupt type selector:. - * 0b000..The analog comparator interrupt edge sensitive is disabled. - * 0b010..analog comparator interrupt is rising edge sensitive. - * 0b100..analog comparator interrupt is falling edge sensitive. - * 0b110..analog comparator interrupt is rising and falling edge sensitive. - * 0b001..The analog comparator interrupt level sensitive is disabled. - * 0b011..Analog Comparator interrupt is high level sensitive. - * 0b101..Analog Comparator interrupt is low level sensitive. - * 0b111..The analog comparator interrupt level sensitive is disabled. - */ -#define SYSCON_COMP_INT_CTRL_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK) - -#define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U) -#define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U) -/*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. - * 0b0..Select Analog Comparator filtered output as input for interrupt detection. - * 0b1..Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when - * Analog comparator is used as wake up source in Power down mode. - */ -#define SYSCON_COMP_INT_CTRL_INT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK) -/*! @} */ - -/*! @name COMP_INT_STATUS - Comparator Interrupt status */ -/*! @{ */ - -#define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U) -#define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U) -/*! STATUS - Interrupt status BEFORE Interrupt Enable. - * 0b0..no interrupt pending. - * 0b1..interrupt pending. - */ -#define SYSCON_COMP_INT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK) - -#define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U) -#define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U) -/*! INT_STATUS - Interrupt status AFTER Interrupt Enable. - * 0b0..no interrupt pending. - * 0b1..interrupt pending. - */ -#define SYSCON_COMP_INT_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) - -#define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U) -#define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U) -/*! VAL - comparator analog output. - * 0b1..P+ is greater than P-. - * 0b0..P+ is smaller than P-. - */ -#define SYSCON_COMP_INT_STATUS_VAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK) -/*! @} */ - -/*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */ -/*! @{ */ - -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U) -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U) -/*! ROM - Control automatic clock gating of ROM controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK (0x2U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT (1U) -/*! RAMX_CTRL - Control automatic clock gating of RAMX controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK (0x4U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT (2U) -/*! RAM0_CTRL - Control automatic clock gating of RAM0 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK (0x8U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT (3U) -/*! RAM1_CTRL - Control automatic clock gating of RAM1 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK (0x10U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT (4U) -/*! RAM2_CTRL - Control automatic clock gating of RAM2 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U) -/*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U) -/*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U) -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U) -/*! CRCGEN - Control automatic clock gating of CRCGEN controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U) -/*! SDMA0 - Control automatic clock gating of DMA0 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U) -/*! SDMA1 - Control automatic clock gating of DMA1 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK (0x4000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT (14U) -/*! USB0 - Control automatic clock gating of USB controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U) -/*! SYSCON - Control automatic clock gating of synchronous system controller registers bank. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U) -/*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. - * 0b1100000011011110..Bit Fields 0 - 15 of this register are updated - * 0b0000000000000000..Bit Fields 0 - 15 of this register are not updated - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK) -/*! @} */ - -/*! @name GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module */ -/*! @{ */ - -#define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U) -#define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U) -/*! PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module. - * 0b1..bypass of the first stage of synchonization inside GPIO_INT module. - * 0b0..use the first stage of synchonization inside GPIO_INT module. - */ -#define SYSCON_GPIOPSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK) -/*! @} */ - -/*! @name HASHRESTHWKEY - Controls whether the HASH AES hardware secret key is restricted to use by secure code */ -/*! @{ */ - -#define SYSCON_HASHRESTHWKEY_UNLOCKCODE_MASK (0xFFFFFFFFU) -#define SYSCON_HASHRESTHWKEY_UNLOCKCODE_SHIFT (0U) -/*! UNLOCKCODE - Code value that controls whether HASH AES hardware secret key is unlocked - * 0b11000011001111001010010101011010..HASH AES hardware secret key is unlocked for use by non-secure code. Any - * other value means that the hardware secret key is restricted to use by - * secure code only. - */ -#define SYSCON_HASHRESTHWKEY_UNLOCKCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HASHRESTHWKEY_UNLOCKCODE_SHIFT)) & SYSCON_HASHRESTHWKEY_UNLOCKCODE_MASK) -/*! @} */ - -/*! @name DEBUG_LOCK_EN - Control write access to security registers. */ -/*! @{ */ - -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) -/*! LOCK_ALL - Control write access to security registers. - * 0b1010..1010: Enable write access to all registers. - * 0b0000..Any other value than b1010: disable write access to all registers. - */ -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) -/*! @} */ - -/*! @name DEBUG_FEATURES - Cortex debug features control. */ -/*! @{ */ - -#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) -#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) -/*! CPU0_DBGEN - CPU0 Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) -#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) -/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK (0x30U) -#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (4U) -/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0xC0U) -#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U) -/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK) -/*! @} */ - -/*! @name DEBUG_FEATURES_DP - Cortex debug features control. (duplicate) */ -/*! @{ */ - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) -/*! CPU0_DBGEN - CPU0 (CPU0) Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) -/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U) -/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U) -/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK) -/*! @} */ - -/*! @name SWD_ACCESS_CPU0 - This register is used by ROM during DEBUG authentication mechanism to enable debug access port for CPU0. */ -/*! @{ */ - -#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE_MASK (0xFFFFFFFFU) -#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE_SHIFT (0U) -/*! SEC_CODE - CPU0 SWD-AP: 0x12345678. - * 0b00010010001101000101011001111000..Value to write to enable CPU0 SWD access. Reading back register will be read as 0xA. - * 0b00000000000000000000000000000000..CPU0 DAP is not allowed. Reading back register will be read as 0x5. - */ -#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU0_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU0_SEC_CODE_MASK) -/*! @} */ - -/*! @name KEY_BLOCK - block quiddikey/PUF all index. */ -/*! @{ */ - -#define SYSCON_KEY_BLOCK_KEY_BLOCK_MASK (0xFFFFFFFFU) -#define SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT (0U) -/*! KEY_BLOCK - Write a value to block quiddikey/PUF all index. - */ -#define SYSCON_KEY_BLOCK_KEY_BLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCON_KEY_BLOCK_KEY_BLOCK_MASK) -/*! @} */ - -/*! @name DEBUG_AUTH_BEACON - Debug authentication BEACON register */ -/*! @{ */ - -#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) -#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) -/*! BEACON - Set by the debug authentication code in ROM to pass the debug beacons (Credential - * Beacon and Authentication Beacon) to application code. - */ -#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) -/*! @} */ - -/*! @name DEVICE_ID0 - Device ID */ -/*! @{ */ - -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) -/*! ROM_REV_MINOR - ROM revision. - */ -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) -/*! @} */ - -/*! @name DIEID - Chip revision ID and Number */ -/*! @{ */ - -#define SYSCON_DIEID_REV_ID_MASK (0xFU) -#define SYSCON_DIEID_REV_ID_SHIFT (0U) -/*! REV_ID - Chip Metal Revision ID. - */ -#define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK) - -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U) -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U) -/*! MCO_NUM_IN_DIE_ID - Chip Number 0x426B. - */ -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SYSCON_Register_Masks */ - - -/* SYSCON - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SYSCON base address */ - #define SYSCON_BASE (0x50000000u) - /** Peripheral SYSCON base address */ - #define SYSCON_BASE_NS (0x40000000u) - /** Peripheral SYSCON base pointer */ - #define SYSCON ((SYSCON_Type *)SYSCON_BASE) - /** Peripheral SYSCON base pointer */ - #define SYSCON_NS ((SYSCON_Type *)SYSCON_BASE_NS) - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS { SYSCON_BASE } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS { SYSCON } - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS_NS { SYSCON_BASE_NS } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS_NS { SYSCON_NS } -#else - /** Peripheral SYSCON base address */ - #define SYSCON_BASE (0x40000000u) - /** Peripheral SYSCON base pointer */ - #define SYSCON ((SYSCON_Type *)SYSCON_BASE) - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS { SYSCON_BASE } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS { SYSCON } -#endif - -/*! - * @} - */ /* end of group SYSCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SYSCTL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCTL_Peripheral_Access_Layer SYSCTL Peripheral Access Layer - * @{ - */ - -/** SYSCTL - Register Layout Typedef */ -typedef struct { - __IO uint32_t UPDATELCKOUT; /**< update lock out control, offset: 0x0 */ - uint8_t RESERVED_0[60]; - __IO uint32_t FCCTRLSEL[8]; /**< Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_1[32]; - __IO uint32_t SHAREDCTRLSET[2]; /**< Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1., array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_2[120]; - __I uint32_t USB_HS_STATUS; /**< Status register for USB HS, offset: 0x100 */ - uint8_t RESERVED_3[124]; - __IO uint32_t CODE_GRAY_LSB; /**< CODE_GRAY LSB input Register, offset: 0x180 */ - __IO uint32_t CODE_GRAY_MSB; /**< CODE_GRAY MSB input Register, offset: 0x184 */ - __I uint32_t CODE_BIN_LSB; /**< CODE_BIN LSB output Register, offset: 0x188 */ - __I uint32_t CODE_BIN_MSB; /**< CODE_BIN MSB output Register, offset: 0x18C */ -} SYSCTL_Type; - -/* ---------------------------------------------------------------------------- - -- SYSCTL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCTL_Register_Masks SYSCTL Register Masks - * @{ - */ - -/*! @name UPDATELCKOUT - update lock out control */ -/*! @{ */ - -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U) -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U) -/*! UPDATELCKOUT - All Registers - * 0b0..Normal Mode. Can be written to. - * 0b1..Protected Mode. Cannot be written to. - */ -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK) -/*! @} */ - -/*! @name FCCTRLSEL - Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7 */ -/*! @{ */ - -#define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U) -#define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U) -/*! SCKINSEL - Selects the source for SCK going into this Flexcomm. - * 0b00..Selects the dedicated FCn_SCK function for this Flexcomm. - * 0b01..SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK) - -#define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U) -#define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U) -/*! WSINSEL - Selects the source for WS going into this Flexcomm. - * 0b00..Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. - * 0b01..WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK) - -#define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U) -#define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U) -/*! DATAINSEL - Selects the source for DATA input to this Flexcomm. - * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. - * 0b01..Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK) - -#define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U) -#define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U) -/*! DATAOUTSEL - Selects the source for DATA output from this Flexcomm. - * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. - * 0b01..Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_DATAOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK) -/*! @} */ - -/* The count of SYSCTL_FCCTRLSEL */ -#define SYSCTL_FCCTRLSEL_COUNT (8U) - -/*! @name SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */ -/*! @{ */ - -#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U) -#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U) -/*! SHAREDSCKSEL - Selects the source for SCK of this shared signal set. - * 0b000..SCK for this shared signal set comes from Flexcomm 0. - * 0b001..SCK for this shared signal set comes from Flexcomm 1. - * 0b010..SCK for this shared signal set comes from Flexcomm 2. - * 0b011..SCK for this shared signal set comes from Flexcomm 3. - * 0b100..SCK for this shared signal set comes from Flexcomm 4. - * 0b101..SCK for this shared signal set comes from Flexcomm 5. - * 0b110..SCK for this shared signal set comes from Flexcomm 6. - * 0b111..SCK for this shared signal set comes from Flexcomm 7. - */ -#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK) - -#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U) -#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U) -/*! SHAREDWSSEL - Selects the source for WS of this shared signal set. - * 0b000..WS for this shared signal set comes from Flexcomm 0. - * 0b001..WS for this shared signal set comes from Flexcomm 1. - * 0b010..WS for this shared signal set comes from Flexcomm 2. - * 0b011..WS for this shared signal set comes from Flexcomm 3. - * 0b100..WS for this shared signal set comes from Flexcomm 4. - * 0b101..WS for this shared signal set comes from Flexcomm 5. - * 0b110..WS for this shared signal set comes from Flexcomm 6. - * 0b111..WS for this shared signal set comes from Flexcomm 7. - */ -#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK) - -#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U) -#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U) -/*! SHAREDDATASEL - Selects the source for DATA input for this shared signal set. - * 0b000..DATA input for this shared signal set comes from Flexcomm 0. - * 0b001..DATA input for this shared signal set comes from Flexcomm 1. - * 0b010..DATA input for this shared signal set comes from Flexcomm 2. - * 0b011..DATA input for this shared signal set comes from Flexcomm 3. - * 0b100..DATA input for this shared signal set comes from Flexcomm 4. - * 0b101..DATA input for this shared signal set comes from Flexcomm 5. - * 0b110..DATA input for this shared signal set comes from Flexcomm 6. - * 0b111..DATA input for this shared signal set comes from Flexcomm 7. - */ -#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U) -#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U) -/*! FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC0 does not contribute to this shared set. - * 0b1..Data output from FC0 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U) -#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U) -/*! FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC1 does not contribute to this shared set. - * 0b1..Data output from FC1 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK (0x40000U) -#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT (18U) -/*! FC2DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC2 does not contribute to this shared set. - * 0b1..Data output from FC2 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U) -#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U) -/*! FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC4 does not contribute to this shared set. - * 0b1..Data output from FC4 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U) -#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U) -/*! FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC5 does not contribute to this shared set. - * 0b1..Data output from FC5 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U) -#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U) -/*! FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC6 does not contribute to this shared set. - * 0b1..Data output from FC6 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U) -#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U) -/*! FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC7 does not contribute to this shared set. - * 0b1..Data output from FC7 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK) -/*! @} */ - -/* The count of SYSCTL_SHAREDCTRLSET */ -#define SYSCTL_SHAREDCTRLSET_COUNT (2U) - -/*! @name USB_HS_STATUS - Status register for USB HS */ -/*! @{ */ - -#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK (0x1U) -#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT (0U) -/*! USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply. - * 0b0..3v3 supply is good. - * 0b1..3v3 supply is too low. - */ -#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT)) & SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK) -/*! @} */ - -/*! @name CODE_GRAY_LSB - CODE_GRAY LSB input Register */ -/*! @{ */ - -#define SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_MASK (0xFFFFFFFFU) -#define SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_SHIFT (0U) -/*! CODE_GRAY_LSB - Gray code (42bits) to be converted back to binary - */ -#define SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_SHIFT)) & SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_MASK) -/*! @} */ - -/*! @name CODE_GRAY_MSB - CODE_GRAY MSB input Register */ -/*! @{ */ - -#define SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_MASK (0x3FFU) -#define SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_SHIFT (0U) -/*! CODE_GRAY_MSB - Gray code (42bits) to be converted back to binary - */ -#define SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_SHIFT)) & SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_MASK) -/*! @} */ - -/*! @name CODE_BIN_LSB - CODE_BIN LSB output Register */ -/*! @{ */ - -#define SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_MASK (0xFFFFFFFFU) -#define SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_SHIFT (0U) -/*! CODE_BIN_LSB - Binary converted code (42bits) - */ -#define SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_SHIFT)) & SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_MASK) -/*! @} */ - -/*! @name CODE_BIN_MSB - CODE_BIN MSB output Register */ -/*! @{ */ - -#define SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_MASK (0x3FFU) -#define SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_SHIFT (0U) -/*! CODE_BIN_MSB - Binary converted code (42bits) - */ -#define SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_SHIFT)) & SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SYSCTL_Register_Masks */ - - -/* SYSCTL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE (0x50023000u) - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE_NS (0x40023000u) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL_NS ((SYSCTL_Type *)SYSCTL_BASE_NS) - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS { SYSCTL } - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS_NS { SYSCTL_BASE_NS } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS_NS { SYSCTL_NS } -#else - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE (0x40023000u) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS { SYSCTL } -#endif - -/*! - * @} - */ /* end of group SYSCTL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USART Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer - * @{ - */ - -/** USART - Register Layout Typedef */ -typedef struct { - __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ - __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ - __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ - uint8_t RESERVED_0[12]; - __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ - __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ - __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ - __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ - uint8_t RESERVED_1[3536]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_2[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_3[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_4[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_6[4]; - __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ - uint8_t RESERVED_7[432]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} USART_Type; - -/* ---------------------------------------------------------------------------- - -- USART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Register_Masks USART Register Masks - * @{ - */ - -/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ -/*! @{ */ - -#define USART_CFG_ENABLE_MASK (0x1U) -#define USART_CFG_ENABLE_SHIFT (0U) -/*! ENABLE - USART Enable. - * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, - * all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control - * bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the - * transmitter has been reset and is therefore available. - * 0b1..Enabled. The USART is enabled for operation. - */ -#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) - -#define USART_CFG_DATALEN_MASK (0xCU) -#define USART_CFG_DATALEN_SHIFT (2U) -/*! DATALEN - Selects the data size for the USART. - * 0b00..7 bit Data length. - * 0b01..8 bit Data length. - * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. - * 0b11..Reserved. - */ -#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) - -#define USART_CFG_PARITYSEL_MASK (0x30U) -#define USART_CFG_PARITYSEL_SHIFT (4U) -/*! PARITYSEL - Selects what type of parity is used by the USART. - * 0b00..No parity. - * 0b01..Reserved. - * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, - * and the number of 1s in a received character is expected to be even. - * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, - * and the number of 1s in a received character is expected to be odd. - */ -#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) - -#define USART_CFG_STOPLEN_MASK (0x40U) -#define USART_CFG_STOPLEN_SHIFT (6U) -/*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. - * 0b0..1 stop bit. - * 0b1..2 stop bits. This setting should only be used for asynchronous communication. - */ -#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) - -#define USART_CFG_MODE32K_MASK (0x80U) -#define USART_CFG_MODE32K_SHIFT (7U) -/*! MODE32K - Selects standard or 32 kHz clocking mode. - * 0b0..Disabled. USART uses standard clocking. - * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. - */ -#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) - -#define USART_CFG_LINMODE_MASK (0x100U) -#define USART_CFG_LINMODE_SHIFT (8U) -/*! LINMODE - LIN break mode enable. - * 0b0..Disabled. Break detect and generate is configured for normal operation. - * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. - */ -#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) - -#define USART_CFG_CTSEN_MASK (0x200U) -#define USART_CFG_CTSEN_SHIFT (9U) -/*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input - * pin, or from the USART's own RTS if loopback mode is enabled. - * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. - * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. - */ -#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) - -#define USART_CFG_SYNCEN_MASK (0x800U) -#define USART_CFG_SYNCEN_SHIFT (11U) -/*! SYNCEN - Selects synchronous or asynchronous operation. - * 0b0..Asynchronous mode. - * 0b1..Synchronous mode. - */ -#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) - -#define USART_CFG_CLKPOL_MASK (0x1000U) -#define USART_CFG_CLKPOL_SHIFT (12U) -/*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. - * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK. - * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. - */ -#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) - -#define USART_CFG_SYNCMST_MASK (0x4000U) -#define USART_CFG_SYNCMST_SHIFT (14U) -/*! SYNCMST - Synchronous mode Master select. - * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. - * 0b1..Master. When synchronous mode is enabled, the USART is a master. - */ -#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) - -#define USART_CFG_LOOP_MASK (0x8000U) -#define USART_CFG_LOOP_SHIFT (15U) -/*! LOOP - Selects data loopback mode. - * 0b0..Normal operation. - * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial - * data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD - * and Un_RTS activity will also appear on external pins if these functions are configured to appear on device - * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. - */ -#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) - -#define USART_CFG_OETA_MASK (0x40000U) -#define USART_CFG_OETA_SHIFT (18U) -/*! OETA - Output Enable Turnaround time enable for RS-485 operation. - * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. - * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the - * end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins - * before it is deasserted. - */ -#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) - -#define USART_CFG_AUTOADDR_MASK (0x80000U) -#define USART_CFG_AUTOADDR_SHIFT (19U) -/*! AUTOADDR - Automatic Address matching enable. - * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the - * possibility of versatile addressing (e.g. respond to more than one address). - * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in - * the ADDR register as the address to match. - */ -#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) - -#define USART_CFG_OESEL_MASK (0x100000U) -#define USART_CFG_OESEL_SHIFT (20U) -/*! OESEL - Output Enable Select. - * 0b0..Standard. The RTS signal is used as the standard flow control function. - * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. - */ -#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) - -#define USART_CFG_OEPOL_MASK (0x200000U) -#define USART_CFG_OEPOL_SHIFT (21U) -/*! OEPOL - Output Enable Polarity. - * 0b0..Low. If selected by OESEL, the output enable is active low. - * 0b1..High. If selected by OESEL, the output enable is active high. - */ -#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) - -#define USART_CFG_RXPOL_MASK (0x400000U) -#define USART_CFG_RXPOL_SHIFT (22U) -/*! RXPOL - Receive data polarity. - * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start - * bit is 0, data is not inverted, and the stop bit is 1. - * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is - * 0, start bit is 1, data is inverted, and the stop bit is 0. - */ -#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) - -#define USART_CFG_TXPOL_MASK (0x800000U) -#define USART_CFG_TXPOL_SHIFT (23U) -/*! TXPOL - Transmit data polarity. - * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is - * 0, data is not inverted, and the stop bit is 1. - * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value - * is 0, start bit is 1, data is inverted, and the stop bit is 0. - */ -#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) -/*! @} */ - -/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ -/*! @{ */ - -#define USART_CTL_TXBRKEN_MASK (0x2U) -#define USART_CTL_TXBRKEN_SHIFT (1U) -/*! TXBRKEN - Break Enable. - * 0b0..Normal operation. - * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit - * is cleared. A break may be sent without danger of corrupting any currently transmitting character if the - * transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled - * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. - */ -#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) - -#define USART_CTL_ADDRDET_MASK (0x4U) -#define USART_CTL_ADDRDET_SHIFT (2U) -/*! ADDRDET - Enable address detect mode. - * 0b0..Disabled. The USART presents all incoming data. - * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data - * (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, - * generating a received data interrupt. Software can then check the data to see if this is an address that - * should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled - * normally. - */ -#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) - -#define USART_CTL_TXDIS_MASK (0x40U) -#define USART_CTL_TXDIS_SHIFT (6U) -/*! TXDIS - Transmit Disable. - * 0b0..Not disabled. USART transmitter is not disabled. - * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This - * feature can be used to facilitate software flow control. - */ -#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) - -#define USART_CTL_CC_MASK (0x100U) -#define USART_CTL_CC_SHIFT (8U) -/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. - * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to - * complete a character that is being received. - * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on - * Un_RxD independently from transmission on Un_TXD). - */ -#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) - -#define USART_CTL_CLRCCONRX_MASK (0x200U) -#define USART_CTL_CLRCCONRX_SHIFT (9U) -/*! CLRCCONRX - Clear Continuous Clock. - * 0b0..No effect. No effect on the CC bit. - * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. - */ -#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) - -#define USART_CTL_AUTOBAUD_MASK (0x10000U) -#define USART_CTL_AUTOBAUD_SHIFT (16U) -/*! AUTOBAUD - Autobaud enable. - * 0b0..Disabled. USART is in normal operating mode. - * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The - * first start bit of RX is measured and used the update the BRG register to match the received data rate. - * AUTOBAUD is cleared once this process is complete, or if there is an AERR. - */ -#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) -/*! @} */ - -/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ -/*! @{ */ - -#define USART_STAT_RXIDLE_MASK (0x2U) -#define USART_STAT_RXIDLE_SHIFT (1U) -/*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of - * receiving data. When 1, indicates that the receiver is not currently in the process of receiving - * data. - */ -#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) - -#define USART_STAT_TXIDLE_MASK (0x8U) -#define USART_STAT_TXIDLE_SHIFT (3U) -/*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of - * sending data.When 1, indicate that the transmitter is not currently in the process of sending - * data. - */ -#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) - -#define USART_STAT_CTS_MASK (0x10U) -#define USART_STAT_CTS_SHIFT (4U) -/*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the - * CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode - * is enabled. - */ -#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) - -#define USART_STAT_DELTACTS_MASK (0x20U) -#define USART_STAT_DELTACTS_SHIFT (5U) -/*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. - */ -#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) - -#define USART_STAT_TXDISSTAT_MASK (0x40U) -#define USART_STAT_TXDISSTAT_SHIFT (6U) -/*! TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART - * transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). - */ -#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) - -#define USART_STAT_RXBRK_MASK (0x400U) -#define USART_STAT_RXBRK_SHIFT (10U) -/*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection - * logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also - * be set when this condition occurs because the stop bit(s) for the character would be missing. - * RXBRK is cleared when the Un_RXD pin goes high. - */ -#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) - -#define USART_STAT_DELTARXBRK_MASK (0x800U) -#define USART_STAT_DELTARXBRK_SHIFT (11U) -/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software. - */ -#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) - -#define USART_STAT_START_MASK (0x1000U) -#define USART_STAT_START_SHIFT (12U) -/*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily - * to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. - * Cleared by software. - */ -#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) - -#define USART_STAT_FRAMERRINT_MASK (0x2000U) -#define USART_STAT_FRAMERRINT_SHIFT (13U) -/*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a - * missing stop bit at the expected location. This could be an indication of a baud rate or - * configuration mismatch with the transmitting source. - */ -#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) - -#define USART_STAT_PARITYERRINT_MASK (0x4000U) -#define USART_STAT_PARITYERRINT_SHIFT (14U) -/*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. - */ -#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) - -#define USART_STAT_RXNOISEINT_MASK (0x8000U) -#define USART_STAT_RXNOISEINT_SHIFT (15U) -/*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to - * determine the value of each received data bit, except in synchronous mode. This acts as a - * noise filter if one sample disagrees. This flag is set when a received data bit contains one - * disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or - * loss of synchronization during data reception. - */ -#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) - -#define USART_STAT_ABERR_MASK (0x10000U) -#define USART_STAT_ABERR_SHIFT (16U) -/*! ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the - * end of the start bit that is being measured, essentially an auto baud time-out. - */ -#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -/*! @{ */ - -#define USART_INTENSET_TXIDLEEN_MASK (0x8U) -#define USART_INTENSET_TXIDLEEN_SHIFT (3U) -/*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). - */ -#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) - -#define USART_INTENSET_DELTACTSEN_MASK (0x20U) -#define USART_INTENSET_DELTACTSEN_SHIFT (5U) -/*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input. - */ -#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) - -#define USART_INTENSET_TXDISEN_MASK (0x40U) -#define USART_INTENSET_TXDISEN_SHIFT (6U) -/*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by - * the TXDISINT flag in STAT. See description of the TXDISINT bit for details. - */ -#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) - -#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) -#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) -/*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection - * of a received break condition (break condition asserted or deasserted). - */ -#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) - -#define USART_INTENSET_STARTEN_MASK (0x1000U) -#define USART_INTENSET_STARTEN_SHIFT (12U) -/*! STARTEN - When 1, enables an interrupt when a received start bit has been detected. - */ -#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) - -#define USART_INTENSET_FRAMERREN_MASK (0x2000U) -#define USART_INTENSET_FRAMERREN_SHIFT (13U) -/*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected. - */ -#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) - -#define USART_INTENSET_PARITYERREN_MASK (0x4000U) -#define USART_INTENSET_PARITYERREN_SHIFT (14U) -/*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected. - */ -#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) - -#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) -#define USART_INTENSET_RXNOISEEN_SHIFT (15U) -/*! RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. - */ -#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) - -#define USART_INTENSET_ABERREN_MASK (0x10000U) -#define USART_INTENSET_ABERREN_SHIFT (16U) -/*! ABERREN - When 1, enables an interrupt when an auto baud error occurs. - */ -#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ -/*! @{ */ - -#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) -#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) -/*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) - -#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) -#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) -/*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) - -#define USART_INTENCLR_TXDISCLR_MASK (0x40U) -#define USART_INTENCLR_TXDISCLR_SHIFT (6U) -/*! TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) - -#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) -#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) -/*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) - -#define USART_INTENCLR_STARTCLR_MASK (0x1000U) -#define USART_INTENCLR_STARTCLR_SHIFT (12U) -/*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) - -#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) -#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) -/*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) - -#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) -#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) -/*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) - -#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) -#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) -/*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) - -#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) -#define USART_INTENCLR_ABERRCLR_SHIFT (16U) -/*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) -/*! @} */ - -/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ -/*! @{ */ - -#define USART_BRG_BRGVAL_MASK (0xFFFFU) -#define USART_BRG_BRGVAL_SHIFT (0U) -/*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on - * the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is - * divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART - * function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. - */ -#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ -/*! @{ */ - -#define USART_INTSTAT_TXIDLE_MASK (0x8U) -#define USART_INTSTAT_TXIDLE_SHIFT (3U) -/*! TXIDLE - Transmitter Idle status. - */ -#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) - -#define USART_INTSTAT_DELTACTS_MASK (0x20U) -#define USART_INTSTAT_DELTACTS_SHIFT (5U) -/*! DELTACTS - This bit is set when a change in the state of the CTS input is detected. - */ -#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) - -#define USART_INTSTAT_TXDISINT_MASK (0x40U) -#define USART_INTSTAT_TXDISINT_SHIFT (6U) -/*! TXDISINT - Transmitter Disabled Interrupt flag. - */ -#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) - -#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) -#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) -/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. - */ -#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) - -#define USART_INTSTAT_START_MASK (0x1000U) -#define USART_INTSTAT_START_SHIFT (12U) -/*! START - This bit is set when a start is detected on the receiver input. - */ -#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) - -#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) -#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) -/*! FRAMERRINT - Framing Error interrupt flag. - */ -#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) - -#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) -#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) -/*! PARITYERRINT - Parity Error interrupt flag. - */ -#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) - -#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) -#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) -/*! RXNOISEINT - Received Noise interrupt flag. - */ -#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) - -#define USART_INTSTAT_ABERRINT_MASK (0x10000U) -#define USART_INTSTAT_ABERRINT_SHIFT (16U) -/*! ABERRINT - Auto baud Error Interrupt flag. - */ -#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) -/*! @} */ - -/*! @name OSR - Oversample selection register for asynchronous communication. */ -/*! @{ */ - -#define USART_OSR_OSRVAL_MASK (0xFU) -#define USART_OSR_OSRVAL_SHIFT (0U) -/*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to - * transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive - * each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. - */ -#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) -/*! @} */ - -/*! @name ADDR - Address register for automatic address matching. */ -/*! @{ */ - -#define USART_ADDR_ADDRESS_MASK (0xFFU) -#define USART_ADDR_ADDRESS_SHIFT (0U) -/*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is - * enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). - */ -#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ - -#define USART_FIFOCFG_ENABLETX_MASK (0x1U) -#define USART_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) - -#define USART_FIFOCFG_ENABLERX_MASK (0x2U) -#define USART_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) - -#define USART_FIFOCFG_SIZE_MASK (0x30U) -#define USART_FIFOCFG_SIZE_SHIFT (4U) -/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 - * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - */ -#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) - -#define USART_FIFOCFG_DMATX_MASK (0x1000U) -#define USART_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) - -#define USART_FIFOCFG_DMARX_MASK (0x2000U) -#define USART_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) - -#define USART_FIFOCFG_WAKETX_MASK (0x4000U) -#define USART_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in - * FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) - -#define USART_FIFOCFG_WAKERX_MASK (0x8000U) -#define USART_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in - * FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) - -#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) -/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - */ -#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) - -#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) -/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - */ -#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ - -#define USART_FIFOSTAT_TXERR_MASK (0x1U) -#define USART_FIFOSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow - * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is - * needed. Cleared by writing a 1 to this bit. - */ -#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) - -#define USART_FIFOSTAT_RXERR_MASK (0x2U) -#define USART_FIFOSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA - * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - */ -#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) - -#define USART_FIFOSTAT_PERINT_MASK (0x8U) -#define USART_FIFOSTAT_PERINT_SHIFT (3U) -/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted - * an interrupt. The details can be found by reading the peripheral's STAT register. - */ -#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) - -#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) -/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - */ -#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) - -#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) -/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be - * written. When 0, the transmit FIFO is full and another write would cause it to overflow. - */ -#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) - -#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - */ -#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) - -#define USART_FIFOSTAT_RXFULL_MASK (0x80U) -#define USART_FIFOSTAT_RXFULL_SHIFT (7U) -/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to - * prevent the peripheral from causing an overflow. - */ -#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) - -#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define USART_FIFOSTAT_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY - * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at - * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be - * 0. - */ -#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) - -#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define USART_FIFOSTAT_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and - * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the - * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be - * 1. - */ -#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ - -#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) - -#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) - -#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) -#define USART_FIFOTRIG_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled - * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to - * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO - * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX - * FIFO level decreases to 15 entries (is no longer full). - */ -#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) - -#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define USART_FIFOTRIG_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data - * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level - * can wake up the device just enough to perform DMA, then return to the reduced power mode. See - * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no - * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX - * FIFO has received 16 entries (has become full). - */ -#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ - -#define USART_FIFOINTENSET_TXERR_MASK (0x1U) -#define USART_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) - -#define USART_FIFOINTENSET_RXERR_MASK (0x2U) -#define USART_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) - -#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) -#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases - * to the level specified by TXLVL in the FIFOTRIG register. - */ -#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) - -#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) -#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level - * increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ - -#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) -#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) -/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) - -#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) -#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) -/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) - -#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) -/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) - -#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) -/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ - -#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) -#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. - */ -#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) - -#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) -#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. - */ -#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) - -#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO level interrupt. - */ -#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) - -#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO level interrupt. - */ -#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) - -#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) -#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) -/*! PERINT - Peripheral interrupt. - */ -#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ - -#define USART_FIFOWR_TXDATA_MASK (0x1FFU) -#define USART_FIFOWR_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit data to the FIFO. - */ -#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ - -#define USART_FIFORD_RXDATA_MASK (0x1FFU) -#define USART_FIFORD_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. - */ -#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) - -#define USART_FIFORD_FRAMERR_MASK (0x2000U) -#define USART_FIFORD_FRAMERR_SHIFT (13U) -/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along - * with from the FIFO, and indicates that the character was received with a missing stop bit at - * the expected location. This could be an indication of a baud rate or configuration mismatch - * with the transmitting source. - */ -#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) - -#define USART_FIFORD_PARITYERR_MASK (0x4000U) -#define USART_FIFORD_PARITYERR_SHIFT (14U) -/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along - * with from the FIFO. This bit will be set when a parity error is detected in a received - * character. - */ -#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) - -#define USART_FIFORD_RXNOISE_MASK (0x8000U) -#define USART_FIFORD_RXNOISE_SHIFT (15U) -/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. - */ -#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ - -#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) -#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. - */ -#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) - -#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) -#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) -/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along - * with from the FIFO, and indicates that the character was received with a missing stop bit at - * the expected location. This could be an indication of a baud rate or configuration mismatch - * with the transmitting source. - */ -#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) - -#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) -#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) -/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along - * with from the FIFO. This bit will be set when a parity error is detected in a received - * character. - */ -#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) - -#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) -#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) -/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. - */ -#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) -/*! @} */ - -/*! @name FIFOSIZE - FIFO size register */ -/*! @{ */ - -#define USART_FIFOSIZE_FIFOSIZE_MASK (0x1FU) -#define USART_FIFOSIZE_FIFOSIZE_SHIFT (0U) -/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - */ -#define USART_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSIZE_FIFOSIZE_SHIFT)) & USART_FIFOSIZE_FIFOSIZE_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ - -#define USART_ID_APERTURE_MASK (0xFFU) -#define USART_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - */ -#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) - -#define USART_ID_MINOR_REV_MASK (0xF00U) -#define USART_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation. - */ -#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) - -#define USART_ID_MAJOR_REV_MASK (0xF000U) -#define USART_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation. - */ -#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) - -#define USART_ID_ID_MASK (0xFFFF0000U) -#define USART_ID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function. - */ -#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USART_Register_Masks */ - - -/* USART - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USART0 base address */ - #define USART0_BASE (0x50086000u) - /** Peripheral USART0 base address */ - #define USART0_BASE_NS (0x40086000u) - /** Peripheral USART0 base pointer */ - #define USART0 ((USART_Type *)USART0_BASE) - /** Peripheral USART0 base pointer */ - #define USART0_NS ((USART_Type *)USART0_BASE_NS) - /** Peripheral USART1 base address */ - #define USART1_BASE (0x50087000u) - /** Peripheral USART1 base address */ - #define USART1_BASE_NS (0x40087000u) - /** Peripheral USART1 base pointer */ - #define USART1 ((USART_Type *)USART1_BASE) - /** Peripheral USART1 base pointer */ - #define USART1_NS ((USART_Type *)USART1_BASE_NS) - /** Peripheral USART2 base address */ - #define USART2_BASE (0x50088000u) - /** Peripheral USART2 base address */ - #define USART2_BASE_NS (0x40088000u) - /** Peripheral USART2 base pointer */ - #define USART2 ((USART_Type *)USART2_BASE) - /** Peripheral USART2 base pointer */ - #define USART2_NS ((USART_Type *)USART2_BASE_NS) - /** Peripheral USART3 base address */ - #define USART3_BASE (0x50089000u) - /** Peripheral USART3 base address */ - #define USART3_BASE_NS (0x40089000u) - /** Peripheral USART3 base pointer */ - #define USART3 ((USART_Type *)USART3_BASE) - /** Peripheral USART3 base pointer */ - #define USART3_NS ((USART_Type *)USART3_BASE_NS) - /** Peripheral USART4 base address */ - #define USART4_BASE (0x5008A000u) - /** Peripheral USART4 base address */ - #define USART4_BASE_NS (0x4008A000u) - /** Peripheral USART4 base pointer */ - #define USART4 ((USART_Type *)USART4_BASE) - /** Peripheral USART4 base pointer */ - #define USART4_NS ((USART_Type *)USART4_BASE_NS) - /** Peripheral USART5 base address */ - #define USART5_BASE (0x50096000u) - /** Peripheral USART5 base address */ - #define USART5_BASE_NS (0x40096000u) - /** Peripheral USART5 base pointer */ - #define USART5 ((USART_Type *)USART5_BASE) - /** Peripheral USART5 base pointer */ - #define USART5_NS ((USART_Type *)USART5_BASE_NS) - /** Peripheral USART6 base address */ - #define USART6_BASE (0x50097000u) - /** Peripheral USART6 base address */ - #define USART6_BASE_NS (0x40097000u) - /** Peripheral USART6 base pointer */ - #define USART6 ((USART_Type *)USART6_BASE) - /** Peripheral USART6 base pointer */ - #define USART6_NS ((USART_Type *)USART6_BASE_NS) - /** Peripheral USART7 base address */ - #define USART7_BASE (0x50098000u) - /** Peripheral USART7 base address */ - #define USART7_BASE_NS (0x40098000u) - /** Peripheral USART7 base pointer */ - #define USART7 ((USART_Type *)USART7_BASE) - /** Peripheral USART7 base pointer */ - #define USART7_NS ((USART_Type *)USART7_BASE_NS) - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS_NS { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS_NS { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS } -#else - /** Peripheral USART0 base address */ - #define USART0_BASE (0x40086000u) - /** Peripheral USART0 base pointer */ - #define USART0 ((USART_Type *)USART0_BASE) - /** Peripheral USART1 base address */ - #define USART1_BASE (0x40087000u) - /** Peripheral USART1 base pointer */ - #define USART1 ((USART_Type *)USART1_BASE) - /** Peripheral USART2 base address */ - #define USART2_BASE (0x40088000u) - /** Peripheral USART2 base pointer */ - #define USART2 ((USART_Type *)USART2_BASE) - /** Peripheral USART3 base address */ - #define USART3_BASE (0x40089000u) - /** Peripheral USART3 base pointer */ - #define USART3 ((USART_Type *)USART3_BASE) - /** Peripheral USART4 base address */ - #define USART4_BASE (0x4008A000u) - /** Peripheral USART4 base pointer */ - #define USART4 ((USART_Type *)USART4_BASE) - /** Peripheral USART5 base address */ - #define USART5_BASE (0x40096000u) - /** Peripheral USART5 base pointer */ - #define USART5 ((USART_Type *)USART5_BASE) - /** Peripheral USART6 base address */ - #define USART6_BASE (0x40097000u) - /** Peripheral USART6 base pointer */ - #define USART6 ((USART_Type *)USART6_BASE) - /** Peripheral USART7 base address */ - #define USART7_BASE (0x40098000u) - /** Peripheral USART7 base pointer */ - #define USART7 ((USART_Type *)USART7_BASE) - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } -#endif -/** Interrupt vectors for the USART peripheral type */ -#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group USART_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer - * @{ - */ - -/** USB - Register Layout Typedef */ -typedef struct { - __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ - __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ - __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ - __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ - __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ - __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ - __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ - __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ - __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ - __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ - __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ - uint8_t RESERVED_0[8]; - __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ -} USB_Type; - -/* ---------------------------------------------------------------------------- - -- USB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Register_Masks USB Register Masks - * @{ - */ - -/*! @name DEVCMDSTAT - USB Device Command/Status register */ -/*! @{ */ - -#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) -#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) -/*! DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit - * is set, the device will respond on packets for function address DEV_ADDR. When receiving a - * SetAddress Control Request from the USB host, software must program the new address before - * completing the status phase of the SetAddress Control Request. - */ -#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) - -#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) -#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) -/*! DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. - */ -#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) - -#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) -#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) -/*! SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this - * bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW - * must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the - * CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. - */ -#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) - -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) -/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: - * 0b0..USB_NEEDCLK has normal function. - * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. - */ -#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) - -#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) -#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) -/*! LPM_SUP - LPM Supported: - * 0b0..LPM not supported. - * 0b1..LPM supported. - */ -#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) - -#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) -#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) -/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) - -#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) -#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) -/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) - -#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) -#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) -/*! INTONNAK_CO - Interrupt on NAK for control OUT EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) - -#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) -#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) -/*! INTONNAK_CI - Interrupt on NAK for control IN EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) - -#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) -#define USB_DEVCMDSTAT_DCON_SHIFT (16U) -/*! DCON - Device status - connect. The connect bit must be set by SW to indicate that the device - * must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and - * the VBUSDEBOUNCED bit is one. - */ -#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) - -#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) -#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) -/*! DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set - * to 1 when the device hasn't seen any activity on its upstream port for more than 3 - * milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and - * the software writes a 0 to it, the device will generate a remote wake-up. This will only happen - * when the device is connected (Connect bit = 1). When the device is not connected or not - * suspended, a writing a 0 has no effect. Writing a 1 never has an effect. - */ -#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) - -#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) -#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) -/*! LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is - * set to 1 by HW when the device has acknowledged the LPM request from the USB host and the - * Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend - * bit = 1) and the software writes a zero to this bit, the device will generate a remote - * walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this - * bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the - * LPM_SUPP bit is equal to one. - */ -#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) - -#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) -#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) -/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake - * bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the - * host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset - * is received. Software can use this bit to check if the remote wake-up feature is enabled by the - * host for the LPM transaction. - */ -#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) - -#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) -#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) -/*! DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up - * resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. - */ -#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) - -#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) -#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) -/*! DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit - * toggles. The suspend bit can toggle because: - The device goes in the suspended state - The - * device is disconnected - The device receives resume signaling on its upstream port. The bit is - * reset by writing a one to it. - */ -#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) - -#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) -#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) -/*! DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On - * a bus reset the device will automatically go to the default state (unconfigured and responding - * to address 0). The bit is reset by writing a one to it. - */ -#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) - -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) -/*! VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when - * Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and - * the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. - */ -#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) -/*! @} */ - -/*! @name INFO - USB Info register */ -/*! @{ */ - -#define USB_INFO_FRAME_NR_MASK (0x7FFU) -#define USB_INFO_FRAME_NR_SHIFT (0U) -/*! FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF. - * In case no SOF was received by the device at the beginning of a frame, the frame number - * returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC - * error, the frame number returned will be the corrupted frame number as received by the device. - */ -#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) - -#define USB_INFO_ERR_CODE_MASK (0x7800U) -#define USB_INFO_ERR_CODE_SHIFT (11U) -/*! ERR_CODE - The error code which last occurred: - * 0b0000..No error - * 0b0001..PID encoding error - * 0b0010..PID unknown - * 0b0011..Packet unexpected - * 0b0100..Token CRC error - * 0b0101..Data CRC error - * 0b0110..Time out - * 0b0111..Babble - * 0b1000..Truncated EOP - * 0b1001..Sent/Received NAK - * 0b1010..Sent Stall - * 0b1011..Overrun - * 0b1100..Sent empty packet - * 0b1101..Bitstuff error - * 0b1110..Sync error - * 0b1111..Wrong data toggle - */ -#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) - -#define USB_INFO_MINREV_MASK (0xFF0000U) -#define USB_INFO_MINREV_SHIFT (16U) -/*! MINREV - Minor Revision. - */ -#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK) - -#define USB_INFO_MAJREV_MASK (0xFF000000U) -#define USB_INFO_MAJREV_SHIFT (24U) -/*! MAJREV - Major Revision. - */ -#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK) -/*! @} */ - -/*! @name EPLISTSTART - USB EP Command/Status List start address */ -/*! @{ */ - -#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) -#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) -/*! EP_LIST - Start address of the USB EP Command/Status List. - */ -#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) -/*! @} */ - -/*! @name DATABUFSTART - USB Data buffer start address */ -/*! @{ */ - -#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) -#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) -/*! DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located. - */ -#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) -/*! @} */ - -/*! @name LPM - USB Link Power Management register */ -/*! @{ */ - -#define USB_LPM_HIRD_HW_MASK (0xFU) -#define USB_LPM_HIRD_HW_SHIFT (0U) -/*! HIRD_HW - Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token - */ -#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) - -#define USB_LPM_HIRD_SW_MASK (0xF0U) -#define USB_LPM_HIRD_SW_SHIFT (4U) -/*! HIRD_SW - Host Initiated Resume Duration - SW. This is the time duration required by the USB - * device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. - */ -#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) - -#define USB_LPM_DATA_PENDING_MASK (0x100U) -#define USB_LPM_DATA_PENDING_SHIFT (8U) -/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will - * return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and - * this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has - * still data pending and LPM is supported, it must set this bit to 1. - */ -#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) -/*! @} */ - -/*! @name EPSKIP - USB Endpoint skip */ -/*! @{ */ - -#define USB_EPSKIP_SKIP_MASK (0x3FFU) -#define USB_EPSKIP_SKIP_SHIFT (0U) -/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must - * deactivate the buffer assigned to this endpoint and return control back to software. When HW has - * deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An - * interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, - * HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. - */ -#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) -/*! @} */ - -/*! @name EPINUSE - USB Endpoint Buffer in use */ -/*! @{ */ - -#define USB_EPINUSE_BUF_MASK (0x3FCU) -#define USB_EPINUSE_BUF_SHIFT (2U) -/*! BUF - Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer - * 0. 1: HW is accessing buffer 1. - */ -#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) -/*! @} */ - -/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ -/*! @{ */ - -#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) -#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) -/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: - * Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding - * EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle - * the EPINUSE bit when it clears the Active bit for the buffer. - */ -#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) -/*! @} */ - -/*! @name INTSTAT - USB interrupt status register */ -/*! @{ */ - -#define USB_INTSTAT_EP0OUT_MASK (0x1U) -#define USB_INTSTAT_EP0OUT_SHIFT (0U) -/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set - * if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is - * successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a - * NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a - * one to it. - */ -#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) - -#define USB_INTSTAT_EP0IN_MASK (0x2U) -#define USB_INTSTAT_EP0IN_SHIFT (1U) -/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if - * NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this - * bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can - * clear this bit by writing a one to it. - */ -#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) - -#define USB_INTSTAT_EP1OUT_MASK (0x4U) -#define USB_INTSTAT_EP1OUT_SHIFT (2U) -/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes - * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be - * set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by - * writing a one to it. - */ -#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) - -#define USB_INTSTAT_EP1IN_MASK (0x8U) -#define USB_INTSTAT_EP1IN_SHIFT (3U) -/*! EP1IN - Interrupt status register bit for the EP1 IN direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions - * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be - * set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing - * a one to it. - */ -#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) - -#define USB_INTSTAT_EP2OUT_MASK (0x10U) -#define USB_INTSTAT_EP2OUT_SHIFT (4U) -/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes - * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be - * set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by - * writing a one to it. - */ -#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) - -#define USB_INTSTAT_EP2IN_MASK (0x20U) -#define USB_INTSTAT_EP2IN_SHIFT (5U) -/*! EP2IN - Interrupt status register bit for the EP2 IN direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions - * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be - * set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing - * a one to it. - */ -#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) - -#define USB_INTSTAT_EP3OUT_MASK (0x40U) -#define USB_INTSTAT_EP3OUT_SHIFT (6U) -/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes - * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be - * set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by - * writing a one to it. - */ -#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) - -#define USB_INTSTAT_EP3IN_MASK (0x80U) -#define USB_INTSTAT_EP3IN_SHIFT (7U) -/*! EP3IN - Interrupt status register bit for the EP3 IN direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions - * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be - * set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing - * a one to it. - */ -#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) - -#define USB_INTSTAT_EP4OUT_MASK (0x100U) -#define USB_INTSTAT_EP4OUT_SHIFT (8U) -/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes - * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be - * set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by - * writing a one to it. - */ -#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) - -#define USB_INTSTAT_EP4IN_MASK (0x200U) -#define USB_INTSTAT_EP4IN_SHIFT (9U) -/*! EP4IN - Interrupt status register bit for the EP4 IN direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions - * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be - * set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing - * a one to it. - */ -#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) - -#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) -#define USB_INTSTAT_FRAME_INT_SHIFT (30U) -/*! FRAME_INT - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit - * and the DCON bit are set. This bit can be used by software when handling isochronous - * endpoints. Software can clear this bit by writing a one to it. - */ -#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) - -#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) -#define USB_INTSTAT_DEV_INT_SHIFT (31U) -/*! DEV_INT - Device status interrupt. This bit is set by HW when one of the bits in the Device - * Status Change register are set. Software can clear this bit by writing a one to it. - */ -#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) -/*! @} */ - -/*! @name INTEN - USB interrupt enable register */ -/*! @{ */ - -#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) -#define USB_INTEN_EP_INT_EN_SHIFT (0U) -/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing - * bit. - */ -#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) - -#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) -#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) -/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt - * routing bit. - */ -#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) - -#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) -#define USB_INTEN_DEV_INT_EN_SHIFT (31U) -/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing - * bit. - */ -#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) -/*! @} */ - -/*! @name INTSETSTAT - USB set interrupt status register */ -/*! @{ */ - -#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) -#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) -/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt - * status bit is set. When this register is read, the same value as the USB interrupt status register - * is returned. - */ -#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) - -#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) -#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) -/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt - * status bit is set. When this register is read, the same value as the USB interrupt status - * register is returned. - */ -#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) - -#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) -#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) -/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt - * status bit is set. When this register is read, the same value as the USB interrupt status - * register is returned. - */ -#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) -/*! @} */ - -/*! @name EPTOGGLE - USB Endpoint toggle register */ -/*! @{ */ - -#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) -#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) -/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. - */ -#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USB_Register_Masks */ - - -/* USB - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USB0 base address */ - #define USB0_BASE (0x50084000u) - /** Peripheral USB0 base address */ - #define USB0_BASE_NS (0x40084000u) - /** Peripheral USB0 base pointer */ - #define USB0 ((USB_Type *)USB0_BASE) - /** Peripheral USB0 base pointer */ - #define USB0_NS ((USB_Type *)USB0_BASE_NS) - /** Array initializer of USB peripheral base addresses */ - #define USB_BASE_ADDRS { USB0_BASE } - /** Array initializer of USB peripheral base pointers */ - #define USB_BASE_PTRS { USB0 } - /** Array initializer of USB peripheral base addresses */ - #define USB_BASE_ADDRS_NS { USB0_BASE_NS } - /** Array initializer of USB peripheral base pointers */ - #define USB_BASE_PTRS_NS { USB0_NS } -#else - /** Peripheral USB0 base address */ - #define USB0_BASE (0x40084000u) - /** Peripheral USB0 base pointer */ - #define USB0 ((USB_Type *)USB0_BASE) - /** Array initializer of USB peripheral base addresses */ - #define USB_BASE_ADDRS { USB0_BASE } - /** Array initializer of USB peripheral base pointers */ - #define USB_BASE_PTRS { USB0 } -#endif -/** Interrupt vectors for the USB peripheral type */ -#define USB_IRQS { USB0_IRQn } -#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBFSH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer - * @{ - */ - -/** USBFSH - Register Layout Typedef */ -typedef struct { - __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */ - __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */ - __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */ - __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */ - __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */ - __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */ - __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */ - __I uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */ - __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */ - __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */ - __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */ - __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */ - __I uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */ - __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */ - __I uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */ - __I uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */ - __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */ - __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */ - __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */ - __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */ - __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */ - __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */ - uint8_t RESERVED_0[4]; - __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */ -} USBFSH_Type; - -/* ---------------------------------------------------------------------------- - -- USBFSH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBFSH_Register_Masks USBFSH Register Masks - * @{ - */ - -/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */ -/*! @{ */ - -#define USBFSH_HCREVISION_REV_MASK (0xFFU) -#define USBFSH_HCREVISION_REV_SHIFT (0U) -/*! REV - Revision. - */ -#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK) -/*! @} */ - -/*! @name HCCONTROL - Defines the operating modes of the HC */ -/*! @{ */ - -#define USBFSH_HCCONTROL_CBSR_MASK (0x3U) -#define USBFSH_HCCONTROL_CBSR_SHIFT (0U) -/*! CBSR - ControlBulkServiceRatio. - */ -#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK) - -#define USBFSH_HCCONTROL_PLE_MASK (0x4U) -#define USBFSH_HCCONTROL_PLE_SHIFT (2U) -/*! PLE - PeriodicListEnable. - */ -#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK) - -#define USBFSH_HCCONTROL_IE_MASK (0x8U) -#define USBFSH_HCCONTROL_IE_SHIFT (3U) -/*! IE - IsochronousEnable. - */ -#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK) - -#define USBFSH_HCCONTROL_CLE_MASK (0x10U) -#define USBFSH_HCCONTROL_CLE_SHIFT (4U) -/*! CLE - ControlListEnable. - */ -#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK) - -#define USBFSH_HCCONTROL_BLE_MASK (0x20U) -#define USBFSH_HCCONTROL_BLE_SHIFT (5U) -/*! BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. - */ -#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK) - -#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U) -#define USBFSH_HCCONTROL_HCFS_SHIFT (6U) -/*! HCFS - HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL - * 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin - * 1 ms later. - */ -#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK) - -#define USBFSH_HCCONTROL_IR_MASK (0x100U) -#define USBFSH_HCCONTROL_IR_SHIFT (8U) -/*! IR - InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. - */ -#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK) - -#define USBFSH_HCCONTROL_RWC_MASK (0x200U) -#define USBFSH_HCCONTROL_RWC_SHIFT (9U) -/*! RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling. - */ -#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK) - -#define USBFSH_HCCONTROL_RWE_MASK (0x400U) -#define USBFSH_HCCONTROL_RWE_SHIFT (10U) -/*! RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature - * upon the detection of upstream resume signaling. - */ -#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK) -/*! @} */ - -/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */ -/*! @{ */ - -#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U) -#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U) -/*! HCR - HostControllerReset This bit is set by HCD to initiate a software reset of HC. - */ -#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK) - -#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U) -#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U) -/*! CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. - */ -#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK) - -#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U) -#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U) -/*! BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. - */ -#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK) - -#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U) -#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U) -/*! OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC. - */ -#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK) - -#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U) -#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U) -/*! SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error. - */ -#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK) -/*! @} */ - -/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */ -/*! @{ */ - -#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U) -/*! SO - SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and - * after the update of HccaFrameNumber. - */ -#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U) -/*! WDH - WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead. - */ -#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U) -/*! SF - StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. - */ -#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U) -/*! RD - ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling. - */ -#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U) -/*! UE - UnrecoverableError This bit is set when HC detects a system error not related to USB. - */ -#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U) -/*! FNO - FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value, - * from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated. - */ -#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U) -/*! RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any - * of HcRhPortStatus[NumberofDownstreamPort] has changed. - */ -#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U) -#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U) -/*! OC - OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus. - */ -#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK) -/*! @} */ - -/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */ -/*! @{ */ - -#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U) -/*! SO - Scheduling Overrun interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK) - -#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U) -/*! WDH - HcDoneHead Writeback interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK) - -#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U) -/*! SF - Start of Frame interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK) - -#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U) -/*! RD - Resume Detect interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK) - -#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U) -/*! UE - Unrecoverable Error interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK) - -#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U) -/*! FNO - Frame Number Overflow interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK) - -#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U) -/*! RHSC - Root Hub Status Change interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK) - -#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U) -#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U) -/*! OC - Ownership Change interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK) - -#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U) -#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U) -/*! MIE - Master Interrupt Enable. - */ -#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK) -/*! @} */ - -/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */ -/*! @{ */ - -#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U) -/*! SO - Scheduling Overrun interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U) -/*! WDH - HcDoneHead Writeback interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U) -/*! SF - Start of Frame interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U) -/*! RD - Resume Detect interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U) -/*! UE - Unrecoverable Error interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U) -/*! FNO - Frame Number Overflow interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U) -/*! RHSC - Root Hub Status Change interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U) -#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U) -/*! OC - Ownership Change interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U) -#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U) -/*! MIE - A 0 written to this field is ignored by HC. - */ -#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK) -/*! @} */ - -/*! @name HCHCCA - Contains the physical address of the host controller communication area */ -/*! @{ */ - -#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U) -#define USBFSH_HCHCCA_HCCA_SHIFT (8U) -/*! HCCA - Base address of the Host Controller Communication Area. - */ -#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK) -/*! @} */ - -/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */ -/*! @{ */ - -#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U) -/*! PCED - The content of this register is updated by HC after a periodic ED is processed. - */ -#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK) -/*! @} */ - -/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */ -/*! @{ */ - -#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U) -#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U) -/*! CHED - HC traverses the Control list starting with the HcControlHeadED pointer. - */ -#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK) -/*! @} */ - -/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */ -/*! @{ */ - -#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U) -/*! CCED - ControlCurrentED. - */ -#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK) -/*! @} */ - -/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */ -/*! @{ */ - -#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U) -#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U) -/*! BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer. - */ -#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK) -/*! @} */ - -/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */ -/*! @{ */ - -#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U) -/*! BCED - BulkCurrentED This is advanced to the next ED after the HC has served the current one. - */ -#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK) -/*! @} */ - -/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */ -/*! @{ */ - -#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U) -#define USBFSH_HCDONEHEAD_DH_SHIFT (4U) -/*! DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. - */ -#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK) -/*! @} */ - -/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */ -/*! @{ */ - -#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU) -#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U) -/*! FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times. - */ -#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK) - -#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U) -#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U) -/*! FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data - * Packet Counter at the beginning of each frame. - */ -#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK) - -#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U) -#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U) -/*! FIT - FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval. - */ -#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK) -/*! @} */ - -/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */ -/*! @{ */ - -#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU) -#define USBFSH_HCFMREMAINING_FR_SHIFT (0U) -/*! FR - FrameRemaining This counter is decremented at each bit time. - */ -#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK) - -#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U) -#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U) -/*! FRT - FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval - * whenever FrameRemaining reaches 0. - */ -#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK) -/*! @} */ - -/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */ -/*! @{ */ - -#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU) -#define USBFSH_HCFMNUMBER_FN_SHIFT (0U) -/*! FN - FrameNumber This is incremented when HcFmRemaining is re-loaded. - */ -#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK) -/*! @} */ - -/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */ -/*! @{ */ - -#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU) -#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U) -/*! PS - PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization. - */ -#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK) -/*! @} */ - -/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */ -/*! @{ */ - -#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU) -#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U) -/*! LST - LSThreshold This field contains a value which is compared to the FrameRemaining field - * prior to initiating a Low Speed transaction. - */ -#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK) -/*! @} */ - -/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */ -/*! @{ */ - -#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU) -#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U) -/*! NDP - NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub. - */ -#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK) - -#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U) -#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U) -/*! PSM - PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled. - */ -#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK) - -#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U) -#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U) -/*! NPS - NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered. - */ -#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK) - -#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U) -#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U) -/*! DT - DeviceType This bit specifies that the root hub is not a compound device. - */ -#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK) - -#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U) -#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U) -/*! OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported. - */ -#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK) - -#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U) -#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U) -/*! NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported. - */ -#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK) - -#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U) -#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U) -/*! POTPGT - PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before - * accessing a powered-on port of the root hub. - */ -#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK) -/*! @} */ - -/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */ -/*! @{ */ - -#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU) -#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U) -/*! DR - DeviceRemovable Each bit is dedicated to a port of the Root Hub. - */ -#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK) - -#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U) -#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U) -/*! PPCM - PortPowerControlMask Each bit indicates if a port is affected by a global power control - * command when PowerSwitchingMode is set. - */ -#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK) -/*! @} */ - -/*! @name HCRHSTATUS - This register is divided into two parts */ -/*! @{ */ - -#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U) -#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U) -/*! LPS - (read) LocalPowerStatus The Root Hub does not support the local power status feature; - * thus, this bit is always read as 0. - */ -#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK) - -#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U) -#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U) -/*! OCI - OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented. - */ -#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK) - -#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U) -#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U) -/*! DRWE - (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume - * event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected - * interrupt. - */ -#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK) - -#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U) -#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U) -/*! LPSC - (read) LocalPowerStatusChange The root hub does not support the local power status feature. - */ -#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK) - -#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U) -#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U) -/*! OCIC - OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register. - */ -#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK) - -#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U) -#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U) -/*! CRWE - (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable. - */ -#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK) -/*! @} */ - -/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */ -/*! @{ */ - -#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U) -#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U) -/*! CCS - (read) CurrentConnectStatus This bit reflects the current state of the downstream port. - */ -#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK) - -#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U) -#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U) -/*! PES - (read) PortEnableStatus This bit indicates whether the port is enabled or disabled. - */ -#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK) - -#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U) -#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U) -/*! PSS - (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence. - */ -#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK) - -#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U) -#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U) -/*! POCI - (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in - * such a way that overcurrent conditions are reported on a per-port basis. - */ -#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK) - -#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U) -#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U) -/*! PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. - */ -#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK) - -#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U) -#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U) -/*! PPS - (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type - * of power switching implemented. - */ -#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK) - -#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U) -#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U) -/*! LSDA - (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. - */ -#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK) - -#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U) -#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U) -/*! CSC - ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. - */ -#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK) - -#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U) -#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U) -/*! PESC - PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared. - */ -#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK) - -#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U) -#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U) -/*! PSSC - PortSuspendStatusChange This bit is set when the full resume sequence is completed. - */ -#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK) - -#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U) -#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U) -/*! OCIC - PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis. - */ -#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK) - -#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U) -#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U) -/*! PRSC - PortResetStatusChange This bit is set at the end of the 10 ms port reset signal. - */ -#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK) -/*! @} */ - -/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ -/*! @{ */ - -#define USBFSH_PORTMODE_ID_MASK (0x1U) -#define USBFSH_PORTMODE_ID_SHIFT (0U) -/*! ID - Port ID pin value. - */ -#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK) - -#define USBFSH_PORTMODE_ID_EN_MASK (0x100U) -#define USBFSH_PORTMODE_ID_EN_SHIFT (8U) -/*! ID_EN - Port ID pin pull-up enable. - */ -#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK) - -#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) -#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U) -/*! DEV_ENABLE - 1: device 0: host. - */ -#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBFSH_Register_Masks */ - - -/* USBFSH - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USBFSH base address */ - #define USBFSH_BASE (0x500A2000u) - /** Peripheral USBFSH base address */ - #define USBFSH_BASE_NS (0x400A2000u) - /** Peripheral USBFSH base pointer */ - #define USBFSH ((USBFSH_Type *)USBFSH_BASE) - /** Peripheral USBFSH base pointer */ - #define USBFSH_NS ((USBFSH_Type *)USBFSH_BASE_NS) - /** Array initializer of USBFSH peripheral base addresses */ - #define USBFSH_BASE_ADDRS { USBFSH_BASE } - /** Array initializer of USBFSH peripheral base pointers */ - #define USBFSH_BASE_PTRS { USBFSH } - /** Array initializer of USBFSH peripheral base addresses */ - #define USBFSH_BASE_ADDRS_NS { USBFSH_BASE_NS } - /** Array initializer of USBFSH peripheral base pointers */ - #define USBFSH_BASE_PTRS_NS { USBFSH_NS } -#else - /** Peripheral USBFSH base address */ - #define USBFSH_BASE (0x400A2000u) - /** Peripheral USBFSH base pointer */ - #define USBFSH ((USBFSH_Type *)USBFSH_BASE) - /** Array initializer of USBFSH peripheral base addresses */ - #define USBFSH_BASE_ADDRS { USBFSH_BASE } - /** Array initializer of USBFSH peripheral base pointers */ - #define USBFSH_BASE_PTRS { USBFSH } -#endif -/** Interrupt vectors for the USBFSH peripheral type */ -#define USBFSH_IRQS { USB0_IRQn } -#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBFSH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBHSD Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer - * @{ - */ - -/** USBHSD - Register Layout Typedef */ -typedef struct { - __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ - __I uint32_t INFO; /**< USB Info register, offset: 0x4 */ - __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ - __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ - __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ - __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ - __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ - __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ - __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ - __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ - __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ - uint8_t RESERVED_0[8]; - __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ -} USBHSD_Type; - -/* ---------------------------------------------------------------------------- - -- USBHSD Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSD_Register_Masks USBHSD Register Masks - * @{ - */ - -/*! @name DEVCMDSTAT - USB Device Command/Status register */ -/*! @{ */ - -#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) -#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) -/*! DEV_ADDR - USB device address. - */ -#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK) - -#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U) -#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U) -/*! DEV_EN - USB device enable. - */ -#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK) - -#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U) -#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U) -/*! SETUP - SETUP token received. - */ -#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK) - -#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) -#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) -/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:. - */ -#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK) - -#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U) -#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U) -/*! LPM_SUP - LPM Supported:. - */ -#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK) - -#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) -/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP:. - */ -#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK) - -#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) -/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP:. - */ -#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK) - -#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) -/*! INTONNAK_CO - Interrupt on NAK for control OUT EP:. - */ -#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK) - -#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) -/*! INTONNAK_CI - Interrupt on NAK for control IN EP:. - */ -#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK) - -#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U) -#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U) -/*! DCON - Device status - connect. - */ -#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK) - -#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U) -#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U) -/*! DSUS - Device status - suspend. - */ -#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK) - -#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) -#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U) -/*! LPM_SUS - Device status - LPM Suspend. - */ -#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK) - -#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) -#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U) -/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. - */ -#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK) - -#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U) -#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U) -/*! Speed - This field indicates the speed at which the device operates: 00b: reserved 01b: - * full-speed 10b: high-speed 11b: super-speed (reserved for future use). - */ -#define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK) - -#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U) -#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U) -/*! DCON_C - Device status - connect change. - */ -#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK) - -#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) -#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U) -/*! DSUS_C - Device status - suspend change. - */ -#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK) - -#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U) -#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U) -/*! DRES_C - Device status - reset change. - */ -#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK) - -#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U) -#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U) -/*! VBUS_DEBOUNCED - This bit indicates if VBUS is detected or not. - */ -#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK) - -#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U) -#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U) -/*! PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification. - * 0b000..Test mode disabled. - * 0b001..Test_J. - * 0b010..Test_K. - * 0b011..Test_SE0_NAK. - * 0b100..Test_Packet. - * 0b101..Test_Force_Enable. - */ -#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK) -/*! @} */ - -/*! @name INFO - USB Info register */ -/*! @{ */ - -#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU) -#define USBHSD_INFO_FRAME_NR_SHIFT (0U) -/*! FRAME_NR - Frame number. - */ -#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK) - -#define USBHSD_INFO_ERR_CODE_MASK (0x7800U) -#define USBHSD_INFO_ERR_CODE_SHIFT (11U) -/*! ERR_CODE - The error code which last occurred:. - */ -#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK) - -#define USBHSD_INFO_MINREV_MASK (0xFF0000U) -#define USBHSD_INFO_MINREV_SHIFT (16U) -/*! MINREV - Minor revision. - */ -#define USBHSD_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MINREV_SHIFT)) & USBHSD_INFO_MINREV_MASK) - -#define USBHSD_INFO_MAJREV_MASK (0xFF000000U) -#define USBHSD_INFO_MAJREV_SHIFT (24U) -/*! MAJREV - Major revision. - */ -#define USBHSD_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MAJREV_SHIFT)) & USBHSD_INFO_MAJREV_MASK) -/*! @} */ - -/*! @name EPLISTSTART - USB EP Command/Status List start address */ -/*! @{ */ - -#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U) -#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U) -/*! EP_LIST_PRG - Programmable portion of the USB EP Command/Status List address. - */ -#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK) - -#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U) -#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U) -/*! EP_LIST_FIXED - Fixed portion of USB EP Command/Status List address. - */ -#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK) -/*! @} */ - -/*! @name DATABUFSTART - USB Data buffer start address */ -/*! @{ */ - -#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU) -#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U) -/*! DA_BUF - Start address of the memory page where all endpoint data buffers are located. - */ -#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK) -/*! @} */ - -/*! @name LPM - USB Link Power Management register */ -/*! @{ */ - -#define USBHSD_LPM_HIRD_HW_MASK (0xFU) -#define USBHSD_LPM_HIRD_HW_SHIFT (0U) -/*! HIRD_HW - Host Initiated Resume Duration - HW. - */ -#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK) - -#define USBHSD_LPM_HIRD_SW_MASK (0xF0U) -#define USBHSD_LPM_HIRD_SW_SHIFT (4U) -/*! HIRD_SW - Host Initiated Resume Duration - SW. - */ -#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK) - -#define USBHSD_LPM_DATA_PENDING_MASK (0x100U) -#define USBHSD_LPM_DATA_PENDING_SHIFT (8U) -/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will - * return a NYET handshake on every LPM token it receives. - */ -#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK) -/*! @} */ - -/*! @name EPSKIP - USB Endpoint skip */ -/*! @{ */ - -#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU) -#define USBHSD_EPSKIP_SKIP_SHIFT (0U) -/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must - * deactivate the buffer assigned to this endpoint and return control back to software. - */ -#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK) -/*! @} */ - -/*! @name EPINUSE - USB Endpoint Buffer in use */ -/*! @{ */ - -#define USBHSD_EPINUSE_BUF_MASK (0xFFCU) -#define USBHSD_EPINUSE_BUF_SHIFT (2U) -/*! BUF - Buffer in use: This register has one bit per physical endpoint. - */ -#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK) -/*! @} */ - -/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ -/*! @{ */ - -#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU) -#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U) -/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. - */ -#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK) -/*! @} */ - -/*! @name INTSTAT - USB interrupt status register */ -/*! @{ */ - -#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U) -#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U) -/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. - */ -#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK) - -#define USBHSD_INTSTAT_EP0IN_MASK (0x2U) -#define USBHSD_INTSTAT_EP0IN_SHIFT (1U) -/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. - */ -#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK) - -#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U) -#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U) -/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. - */ -#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK) - -#define USBHSD_INTSTAT_EP1IN_MASK (0x8U) -#define USBHSD_INTSTAT_EP1IN_SHIFT (3U) -/*! EP1IN - Interrupt status register bit for the EP1 IN direction. - */ -#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK) - -#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U) -#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U) -/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. - */ -#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK) - -#define USBHSD_INTSTAT_EP2IN_MASK (0x20U) -#define USBHSD_INTSTAT_EP2IN_SHIFT (5U) -/*! EP2IN - Interrupt status register bit for the EP2 IN direction. - */ -#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK) - -#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U) -#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U) -/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. - */ -#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK) - -#define USBHSD_INTSTAT_EP3IN_MASK (0x80U) -#define USBHSD_INTSTAT_EP3IN_SHIFT (7U) -/*! EP3IN - Interrupt status register bit for the EP3 IN direction. - */ -#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK) - -#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U) -#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U) -/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. - */ -#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK) - -#define USBHSD_INTSTAT_EP4IN_MASK (0x200U) -#define USBHSD_INTSTAT_EP4IN_SHIFT (9U) -/*! EP4IN - Interrupt status register bit for the EP4 IN direction. - */ -#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK) - -#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U) -#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U) -/*! EP5OUT - Interrupt status register bit for the EP5 OUT direction. - */ -#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK) - -#define USBHSD_INTSTAT_EP5IN_MASK (0x800U) -#define USBHSD_INTSTAT_EP5IN_SHIFT (11U) -/*! EP5IN - Interrupt status register bit for the EP5 IN direction. - */ -#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK) - -#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U) -#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U) -/*! FRAME_INT - Frame interrupt. - */ -#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK) - -#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U) -#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U) -/*! DEV_INT - Device status interrupt. - */ -#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK) -/*! @} */ - -/*! @name INTEN - USB interrupt enable register */ -/*! @{ */ - -#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU) -#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U) -/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line. - */ -#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK) - -#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U) -#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U) -/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line. - */ -#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK) - -#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U) -#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U) -/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line. - */ -#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK) -/*! @} */ - -/*! @name INTSETSTAT - USB set interrupt status register */ -/*! @{ */ - -#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU) -#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U) -/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. - */ -#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK) - -#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) -#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) -/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. - */ -#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK) - -#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) -#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U) -/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. - */ -#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK) -/*! @} */ - -/*! @name EPTOGGLE - USB Endpoint toggle register */ -/*! @{ */ - -#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU) -#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U) -/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. - */ -#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBHSD_Register_Masks */ - - -/* USBHSD - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USBHSD base address */ - #define USBHSD_BASE (0x50094000u) - /** Peripheral USBHSD base address */ - #define USBHSD_BASE_NS (0x40094000u) - /** Peripheral USBHSD base pointer */ - #define USBHSD ((USBHSD_Type *)USBHSD_BASE) - /** Peripheral USBHSD base pointer */ - #define USBHSD_NS ((USBHSD_Type *)USBHSD_BASE_NS) - /** Array initializer of USBHSD peripheral base addresses */ - #define USBHSD_BASE_ADDRS { USBHSD_BASE } - /** Array initializer of USBHSD peripheral base pointers */ - #define USBHSD_BASE_PTRS { USBHSD } - /** Array initializer of USBHSD peripheral base addresses */ - #define USBHSD_BASE_ADDRS_NS { USBHSD_BASE_NS } - /** Array initializer of USBHSD peripheral base pointers */ - #define USBHSD_BASE_PTRS_NS { USBHSD_NS } -#else - /** Peripheral USBHSD base address */ - #define USBHSD_BASE (0x40094000u) - /** Peripheral USBHSD base pointer */ - #define USBHSD ((USBHSD_Type *)USBHSD_BASE) - /** Array initializer of USBHSD peripheral base addresses */ - #define USBHSD_BASE_ADDRS { USBHSD_BASE } - /** Array initializer of USBHSD peripheral base pointers */ - #define USBHSD_BASE_PTRS { USBHSD } -#endif -/** Interrupt vectors for the USBHSD peripheral type */ -#define USBHSD_IRQS { USB1_IRQn } -#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBHSD_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBHSH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer - * @{ - */ - -/** USBHSH - Register Layout Typedef */ -typedef struct { - __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */ - __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */ - __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x8 */ - __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */ - __IO uint32_t ATLPTD; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */ - __IO uint32_t ISOPTD; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */ - __IO uint32_t INTPTD; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */ - __IO uint32_t DATAPAYLOAD; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */ - __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */ - __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */ - __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */ - __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */ - __IO uint32_t ATLPTDD; /**< Done map for each ATL PTD, offset: 0x30 */ - __IO uint32_t ATLPTDS; /**< Skip map for each ATL PTD, offset: 0x34 */ - __IO uint32_t ISOPTDD; /**< Done map for each ISO PTD, offset: 0x38 */ - __IO uint32_t ISOPTDS; /**< Skip map for each ISO PTD, offset: 0x3C */ - __IO uint32_t INTPTDD; /**< Done map for each INT PTD, offset: 0x40 */ - __IO uint32_t INTPTDS; /**< Skip map for each INT PTD, offset: 0x44 */ - __IO uint32_t LASTPTD; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */ - uint8_t RESERVED_0[4]; - __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */ -} USBHSH_Type; - -/* ---------------------------------------------------------------------------- - -- USBHSH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSH_Register_Masks USBHSH Register Masks - * @{ - */ - -/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */ -/*! @{ */ - -#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU) -#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U) -/*! CAPLENGTH - Capability Length: This is used as an offset. - */ -#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK) - -#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U) -#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U) -/*! CHIPID - Chip identification: indicates major and minor revision of the IP: [31:24] = Major - * revision [23:16] = Minor revision Major revisions used: 0x01: USB2. - */ -#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK) -/*! @} */ - -/*! @name HCSPARAMS - Host Controller Structural Parameters */ -/*! @{ */ - -#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU) -#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U) -/*! N_PORTS - This register specifies the number of physical downstream ports implemented on this host controller. - */ -#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK) - -#define USBHSH_HCSPARAMS_PPC_MASK (0x10U) -#define USBHSH_HCSPARAMS_PPC_SHIFT (4U) -/*! PPC - This field indicates whether the host controller implementation includes port power control. - */ -#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK) - -#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U) -#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U) -/*! P_INDICATOR - This bit indicates whether the ports support port indicator control. - */ -#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK) -/*! @} */ - -/*! @name HCCPARAMS - Host Controller Capability Parameters */ -/*! @{ */ - -#define USBHSH_HCCPARAMS_LPMC_MASK (0x20000U) -#define USBHSH_HCCPARAMS_LPMC_SHIFT (17U) -/*! LPMC - Link Power Management Capability. - */ -#define USBHSH_HCCPARAMS_LPMC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK) -/*! @} */ - -/*! @name FLADJ_FRINDEX - Frame Length Adjustment */ -/*! @{ */ - -#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU) -#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U) -/*! FLADJ - Frame Length Timing Value. - */ -#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK) - -#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U) -#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U) -/*! FRINDEX - Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet. - */ -#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) -/*! @} */ - -/*! @name ATLPTD - Memory base address where ATL PTD0 is stored */ -/*! @{ */ - -#define USBHSH_ATLPTD_ATL_CUR_MASK (0x1F0U) -#define USBHSH_ATLPTD_ATL_CUR_SHIFT (4U) -/*! ATL_CUR - This indicates the current PTD that is used by the hardware when it is processing the ATL list. - */ -#define USBHSH_ATLPTD_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_CUR_SHIFT)) & USBHSH_ATLPTD_ATL_CUR_MASK) - -#define USBHSH_ATLPTD_ATL_BASE_MASK (0xFFFFFE00U) -#define USBHSH_ATLPTD_ATL_BASE_SHIFT (9U) -/*! ATL_BASE - Base address to be used by the hardware to find the start of the ATL list. - */ -#define USBHSH_ATLPTD_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_BASE_SHIFT)) & USBHSH_ATLPTD_ATL_BASE_MASK) -/*! @} */ - -/*! @name ISOPTD - Memory base address where ISO PTD0 is stored */ -/*! @{ */ - -#define USBHSH_ISOPTD_ISO_FIRST_MASK (0x3E0U) -#define USBHSH_ISOPTD_ISO_FIRST_SHIFT (5U) -/*! ISO_FIRST - This indicates the first PTD that is used by the hardware when it is processing the ISO list. - */ -#define USBHSH_ISOPTD_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_FIRST_SHIFT)) & USBHSH_ISOPTD_ISO_FIRST_MASK) - -#define USBHSH_ISOPTD_ISO_BASE_MASK (0xFFFFFC00U) -#define USBHSH_ISOPTD_ISO_BASE_SHIFT (10U) -/*! ISO_BASE - Base address to be used by the hardware to find the start of the ISO list. - */ -#define USBHSH_ISOPTD_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_BASE_SHIFT)) & USBHSH_ISOPTD_ISO_BASE_MASK) -/*! @} */ - -/*! @name INTPTD - Memory base address where INT PTD0 is stored */ -/*! @{ */ - -#define USBHSH_INTPTD_INT_FIRST_MASK (0x3E0U) -#define USBHSH_INTPTD_INT_FIRST_SHIFT (5U) -/*! INT_FIRST - This indicates the first PTD that is used by the hardware when it is processing the INT list. - */ -#define USBHSH_INTPTD_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_FIRST_SHIFT)) & USBHSH_INTPTD_INT_FIRST_MASK) - -#define USBHSH_INTPTD_INT_BASE_MASK (0xFFFFFC00U) -#define USBHSH_INTPTD_INT_BASE_SHIFT (10U) -/*! INT_BASE - Base address to be used by the hardware to find the start of the INT list. - */ -#define USBHSH_INTPTD_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_BASE_SHIFT)) & USBHSH_INTPTD_INT_BASE_MASK) -/*! @} */ - -/*! @name DATAPAYLOAD - Memory base address that indicates the start of the data payload buffers */ -/*! @{ */ - -#define USBHSH_DATAPAYLOAD_DAT_BASE_MASK (0xFFFF0000U) -#define USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT (16U) -/*! DAT_BASE - Base address to be used by the hardware to find the start of the data payload section. - */ -#define USBHSH_DATAPAYLOAD_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT)) & USBHSH_DATAPAYLOAD_DAT_BASE_MASK) -/*! @} */ - -/*! @name USBCMD - USB Command register */ -/*! @{ */ - -#define USBHSH_USBCMD_RS_MASK (0x1U) -#define USBHSH_USBCMD_RS_SHIFT (0U) -/*! RS - Run/Stop: 1b = Run. - */ -#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK) - -#define USBHSH_USBCMD_HCRESET_MASK (0x2U) -#define USBHSH_USBCMD_HCRESET_SHIFT (1U) -/*! HCRESET - Host Controller Reset: This control bit is used by the software to reset the host controller. - */ -#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK) - -#define USBHSH_USBCMD_FLS_MASK (0xCU) -#define USBHSH_USBCMD_FLS_SHIFT (2U) -/*! FLS - Frame List Size: This field specifies the size of the frame list. - */ -#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK) - -#define USBHSH_USBCMD_LHCR_MASK (0x80U) -#define USBHSH_USBCMD_LHCR_SHIFT (7U) -/*! LHCR - Light Host Controller Reset: This bit allows the driver software to reset the host - * controller without affecting the state of the ports. - */ -#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK) - -#define USBHSH_USBCMD_ATL_EN_MASK (0x100U) -#define USBHSH_USBCMD_ATL_EN_SHIFT (8U) -/*! ATL_EN - ATL List enabled. - */ -#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK) - -#define USBHSH_USBCMD_ISO_EN_MASK (0x200U) -#define USBHSH_USBCMD_ISO_EN_SHIFT (9U) -/*! ISO_EN - ISO List enabled. - */ -#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK) - -#define USBHSH_USBCMD_INT_EN_MASK (0x400U) -#define USBHSH_USBCMD_INT_EN_SHIFT (10U) -/*! INT_EN - INT List enabled. - */ -#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK) - -#define USBHSH_USBCMD_HIRD_MASK (0xF000000U) -#define USBHSH_USBCMD_HIRD_SHIFT (24U) -/*! HIRD - Host-Initiated Resume Duration. - */ -#define USBHSH_USBCMD_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK) - -#define USBHSH_USBCMD_LPM_RWU_MASK (0x10000000U) -#define USBHSH_USBCMD_LPM_RWU_SHIFT (28U) -/*! LPM_RWU - bRemoteWake field. - */ -#define USBHSH_USBCMD_LPM_RWU(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LPM_RWU_SHIFT)) & USBHSH_USBCMD_LPM_RWU_MASK) -/*! @} */ - -/*! @name USBSTS - USB Interrupt Status register */ -/*! @{ */ - -#define USBHSH_USBSTS_PCD_MASK (0x4U) -#define USBHSH_USBSTS_PCD_SHIFT (2U) -/*! PCD - Port Change Detect: The host controller sets this bit to logic 1 when any port has a - * change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a - * result of a J-K transition detected on a suspended port. - */ -#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK) - -#define USBHSH_USBSTS_FLR_MASK (0x8U) -#define USBHSH_USBSTS_FLR_SHIFT (3U) -/*! FLR - Frame List Rollover: The host controller sets this bit to logic 1 when the frame list - * index rolls over its maximum value to 0. - */ -#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK) - -#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U) -#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U) -/*! ATL_IRQ - ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed. - */ -#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK) - -#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U) -#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U) -/*! ISO_IRQ - ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed. - */ -#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK) - -#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U) -#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U) -/*! INT_IRQ - INT IRQ: Indicates that an INT PTD (with I-bit set) was completed. - */ -#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK) - -#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U) -#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U) -/*! SOF_IRQ - SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set. - */ -#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK) -/*! @} */ - -/*! @name USBINTR - USB Interrupt Enable register */ -/*! @{ */ - -#define USBHSH_USBINTR_PCDE_MASK (0x4U) -#define USBHSH_USBINTR_PCDE_SHIFT (2U) -/*! PCDE - Port Change Detect Interrupt Enable: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK) - -#define USBHSH_USBINTR_FLRE_MASK (0x8U) -#define USBHSH_USBINTR_FLRE_SHIFT (3U) -/*! FLRE - Frame List Rollover Interrupt Enable: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK) - -#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U) -#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U) -/*! ATL_IRQ_E - ATL IRQ Enable bit: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK) - -#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U) -#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U) -/*! ISO_IRQ_E - ISO IRQ Enable bit: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK) - -#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U) -#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U) -/*! INT_IRQ_E - INT IRQ Enable bit: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK) - -#define USBHSH_USBINTR_SOF_E_MASK (0x80000U) -#define USBHSH_USBINTR_SOF_E_SHIFT (19U) -/*! SOF_E - SOF Interrupt Enable bit: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK) -/*! @} */ - -/*! @name PORTSC1 - Port Status and Control register */ -/*! @{ */ - -#define USBHSH_PORTSC1_CCS_MASK (0x1U) -#define USBHSH_PORTSC1_CCS_SHIFT (0U) -/*! CCS - Current Connect Status: Logic 1 indicates a device is present on the port. - */ -#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK) - -#define USBHSH_PORTSC1_CSC_MASK (0x2U) -#define USBHSH_PORTSC1_CSC_SHIFT (1U) -/*! CSC - Connect Status Change: Logic 1 means that the value of CCS has changed. - */ -#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK) - -#define USBHSH_PORTSC1_PED_MASK (0x4U) -#define USBHSH_PORTSC1_PED_SHIFT (2U) -/*! PED - Port Enabled/Disabled. - */ -#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK) - -#define USBHSH_PORTSC1_PEDC_MASK (0x8U) -#define USBHSH_PORTSC1_PEDC_SHIFT (3U) -/*! PEDC - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed. - */ -#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK) - -#define USBHSH_PORTSC1_OCA_MASK (0x10U) -#define USBHSH_PORTSC1_OCA_SHIFT (4U) -/*! OCA - Over-current active: Logic 1 means that this port has an over-current condition. - */ -#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK) - -#define USBHSH_PORTSC1_OCC_MASK (0x20U) -#define USBHSH_PORTSC1_OCC_SHIFT (5U) -/*! OCC - Over-current change: Logic 1 means that the value of OCA has changed. - */ -#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK) - -#define USBHSH_PORTSC1_FPR_MASK (0x40U) -#define USBHSH_PORTSC1_FPR_SHIFT (6U) -/*! FPR - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port. - */ -#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK) - -#define USBHSH_PORTSC1_SUSP_MASK (0x80U) -#define USBHSH_PORTSC1_SUSP_SHIFT (7U) -/*! SUSP - Suspend: Logic 1 means port is in the suspend state. - */ -#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK) - -#define USBHSH_PORTSC1_PR_MASK (0x100U) -#define USBHSH_PORTSC1_PR_SHIFT (8U) -/*! PR - Port Reset: Logic 1 means the port is in the reset state. - */ -#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK) - -#define USBHSH_PORTSC1_SUS_L1_MASK (0x200U) -#define USBHSH_PORTSC1_SUS_L1_SHIFT (9U) -/*! SUS_L1 - Suspend using L1 0b = Suspend using L2 1b = Suspend using L1 When this bit is set to a - * 1 and a non-zero value is specified in the Device Address field, the host controller will - * generate an LPM Token to enter the L1 state whenever software writes a one to the Suspend bit, as - * well as L1 exit timing during any device or host-initiated resume. - */ -#define USBHSH_PORTSC1_SUS_L1(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK) - -#define USBHSH_PORTSC1_LS_MASK (0xC00U) -#define USBHSH_PORTSC1_LS_SHIFT (10U) -/*! LS - Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. - */ -#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK) - -#define USBHSH_PORTSC1_PP_MASK (0x1000U) -#define USBHSH_PORTSC1_PP_SHIFT (12U) -/*! PP - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register. - */ -#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK) - -#define USBHSH_PORTSC1_PIC_MASK (0xC000U) -#define USBHSH_PORTSC1_PIC_SHIFT (14U) -/*! PIC - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the - * HCSPARAMS register is logic 0. - */ -#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK) - -#define USBHSH_PORTSC1_PTC_MASK (0xF0000U) -#define USBHSH_PORTSC1_PTC_SHIFT (16U) -/*! PTC - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value. - */ -#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK) - -#define USBHSH_PORTSC1_PSPD_MASK (0x300000U) -#define USBHSH_PORTSC1_PSPD_SHIFT (20U) -/*! PSPD - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved. - */ -#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK) - -#define USBHSH_PORTSC1_WOO_MASK (0x400000U) -#define USBHSH_PORTSC1_WOO_SHIFT (22U) -/*! WOO - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to - * overcurrent conditions as wake-up events. - */ -#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK) - -#define USBHSH_PORTSC1_SUS_STAT_MASK (0x1800000U) -#define USBHSH_PORTSC1_SUS_STAT_SHIFT (23U) -/*! SUS_STAT - These two bits are used by software to determine whether the most recent L1 suspend - * request was successful: 00b: Success-state transition was successful (ACK) 01b: Not Yet - - * Device was unable to enter the L1 state at this time (NYET) 10b: Not supported - Device does not - * support the L1 state (STALL) 11b: Timeout/Error - Device failed to respond or an error occurred. - */ -#define USBHSH_PORTSC1_SUS_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK) - -#define USBHSH_PORTSC1_DEV_ADD_MASK (0xFE000000U) -#define USBHSH_PORTSC1_DEV_ADD_SHIFT (25U) -/*! DEV_ADD - Device Address for LPM tokens. - */ -#define USBHSH_PORTSC1_DEV_ADD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK) -/*! @} */ - -/*! @name ATLPTDD - Done map for each ATL PTD */ -/*! @{ */ - -#define USBHSH_ATLPTDD_ATL_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_ATLPTDD_ATL_DONE_SHIFT (0U) -/*! ATL_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - */ -#define USBHSH_ATLPTDD_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDD_ATL_DONE_SHIFT)) & USBHSH_ATLPTDD_ATL_DONE_MASK) -/*! @} */ - -/*! @name ATLPTDS - Skip map for each ATL PTD */ -/*! @{ */ - -#define USBHSH_ATLPTDS_ATL_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_ATLPTDS_ATL_SKIP_SHIFT (0U) -/*! ATL_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be - * skipped, independent of the V bit setting. - */ -#define USBHSH_ATLPTDS_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDS_ATL_SKIP_SHIFT)) & USBHSH_ATLPTDS_ATL_SKIP_MASK) -/*! @} */ - -/*! @name ISOPTDD - Done map for each ISO PTD */ -/*! @{ */ - -#define USBHSH_ISOPTDD_ISO_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_ISOPTDD_ISO_DONE_SHIFT (0U) -/*! ISO_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - */ -#define USBHSH_ISOPTDD_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDD_ISO_DONE_SHIFT)) & USBHSH_ISOPTDD_ISO_DONE_MASK) -/*! @} */ - -/*! @name ISOPTDS - Skip map for each ISO PTD */ -/*! @{ */ - -#define USBHSH_ISOPTDS_ISO_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_ISOPTDS_ISO_SKIP_SHIFT (0U) -/*! ISO_SKIP - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - */ -#define USBHSH_ISOPTDS_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDS_ISO_SKIP_SHIFT)) & USBHSH_ISOPTDS_ISO_SKIP_MASK) -/*! @} */ - -/*! @name INTPTDD - Done map for each INT PTD */ -/*! @{ */ - -#define USBHSH_INTPTDD_INT_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_INTPTDD_INT_DONE_SHIFT (0U) -/*! INT_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - */ -#define USBHSH_INTPTDD_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDD_INT_DONE_SHIFT)) & USBHSH_INTPTDD_INT_DONE_MASK) -/*! @} */ - -/*! @name INTPTDS - Skip map for each INT PTD */ -/*! @{ */ - -#define USBHSH_INTPTDS_INT_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_INTPTDS_INT_SKIP_SHIFT (0U) -/*! INT_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be - * skipped, independent of the V bit setting. - */ -#define USBHSH_INTPTDS_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDS_INT_SKIP_SHIFT)) & USBHSH_INTPTDS_INT_SKIP_MASK) -/*! @} */ - -/*! @name LASTPTD - Marks the last PTD in the list for ISO, INT and ATL */ -/*! @{ */ - -#define USBHSH_LASTPTD_ATL_LAST_MASK (0x1FU) -#define USBHSH_LASTPTD_ATL_LAST_SHIFT (0U) -/*! ATL_LAST - If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed. - */ -#define USBHSH_LASTPTD_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ATL_LAST_SHIFT)) & USBHSH_LASTPTD_ATL_LAST_MASK) - -#define USBHSH_LASTPTD_ISO_LAST_MASK (0x1F00U) -#define USBHSH_LASTPTD_ISO_LAST_SHIFT (8U) -/*! ISO_LAST - This indicates the last PTD in the ISO list. - */ -#define USBHSH_LASTPTD_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ISO_LAST_SHIFT)) & USBHSH_LASTPTD_ISO_LAST_MASK) - -#define USBHSH_LASTPTD_INT_LAST_MASK (0x1F0000U) -#define USBHSH_LASTPTD_INT_LAST_SHIFT (16U) -/*! INT_LAST - This indicates the last PTD in the INT list. - */ -#define USBHSH_LASTPTD_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_INT_LAST_SHIFT)) & USBHSH_LASTPTD_INT_LAST_MASK) -/*! @} */ - -/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ -/*! @{ */ - -#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) -#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U) -/*! DEV_ENABLE - If this bit is set to one, one of the ports will behave as a USB device. - */ -#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK) - -#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U) -#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U) -/*! SW_CTRL_PDCOM - This bit indicates if the PHY power-down input is controlled by software or by hardware. - */ -#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK) - -#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U) -#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U) -/*! SW_PDCOM - This bit is only used when SW_CTRL_PDCOM is set to 1b. - */ -#define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBHSH_Register_Masks */ - - -/* USBHSH - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USBHSH base address */ - #define USBHSH_BASE (0x500A3000u) - /** Peripheral USBHSH base address */ - #define USBHSH_BASE_NS (0x400A3000u) - /** Peripheral USBHSH base pointer */ - #define USBHSH ((USBHSH_Type *)USBHSH_BASE) - /** Peripheral USBHSH base pointer */ - #define USBHSH_NS ((USBHSH_Type *)USBHSH_BASE_NS) - /** Array initializer of USBHSH peripheral base addresses */ - #define USBHSH_BASE_ADDRS { USBHSH_BASE } - /** Array initializer of USBHSH peripheral base pointers */ - #define USBHSH_BASE_PTRS { USBHSH } - /** Array initializer of USBHSH peripheral base addresses */ - #define USBHSH_BASE_ADDRS_NS { USBHSH_BASE_NS } - /** Array initializer of USBHSH peripheral base pointers */ - #define USBHSH_BASE_PTRS_NS { USBHSH_NS } -#else - /** Peripheral USBHSH base address */ - #define USBHSH_BASE (0x400A3000u) - /** Peripheral USBHSH base pointer */ - #define USBHSH ((USBHSH_Type *)USBHSH_BASE) - /** Array initializer of USBHSH peripheral base addresses */ - #define USBHSH_BASE_ADDRS { USBHSH_BASE } - /** Array initializer of USBHSH peripheral base pointers */ - #define USBHSH_BASE_PTRS { USBHSH } -#endif -/** Interrupt vectors for the USBHSH peripheral type */ -#define USBHSH_IRQS { USB1_IRQn } -#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBHSH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBPHY Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer - * @{ - */ - -/** USBPHY - Register Layout Typedef */ -typedef struct { - __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ - __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ - __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ - __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ - __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ - __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ - __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ - __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ - __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ - __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ - __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ - __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ - __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ - __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ - __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ - __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ - __I uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ - uint8_t RESERVED_0[92]; - __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */ - __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */ - __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */ - __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */ - uint8_t RESERVED_1[16]; - __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */ - __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */ - __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */ - __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */ - __I uint32_t USB1_VBUS_DET_STAT; /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */ - uint8_t RESERVED_2[44]; - __IO uint32_t ANACTRLr; /**< USB PHY Analog Control Register, offset: 0x100 */ - __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */ - __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */ - __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */ -} USBPHY_Type; - -/* ---------------------------------------------------------------------------- - -- USBPHY Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBPHY_Register_Masks USBPHY Register Masks - * @{ - */ - -/*! @name PWD - USB PHY Power-Down Register */ -/*! @{ */ - -#define USBPHY_PWD_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) - -#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) - -#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) - -#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) - -#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) - -#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) - -#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) -/*! @} */ - -/*! @name PWD_SET - USB PHY Power-Down Register */ -/*! @{ */ - -#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) - -#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) - -#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) - -#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) - -#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) - -#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) - -#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) -/*! @} */ - -/*! @name PWD_CLR - USB PHY Power-Down Register */ -/*! @{ */ - -#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) - -#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) - -#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) - -#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) - -#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) - -#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) - -#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) -/*! @} */ - -/*! @name PWD_TOG - USB PHY Power-Down Register */ -/*! @{ */ - -#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) - -#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) - -#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) - -#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) - -#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) - -#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) - -#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) -/*! @} */ - -/*! @name TX - USB PHY Transmitter Control Register */ -/*! @{ */ - -#define USBPHY_TX_D_CAL_MASK (0xFU) -#define USBPHY_TX_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) - -#define USBPHY_TX_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK) - -#define USBPHY_TX_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DN_SHIFT)) & USBPHY_TX_TXENCAL45DN_MASK) - -#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) - -#define USBPHY_TX_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name TX_SET - USB PHY Transmitter Control Register */ -/*! @{ */ - -#define USBPHY_TX_SET_D_CAL_MASK (0xFU) -#define USBPHY_TX_SET_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) - -#define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK) - -#define USBPHY_TX_SET_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_SET_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_SET_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DN_SHIFT)) & USBPHY_TX_SET_TXENCAL45DN_MASK) - -#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) - -#define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_SET_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name TX_CLR - USB PHY Transmitter Control Register */ -/*! @{ */ - -#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) -#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) - -#define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK) - -#define USBPHY_TX_CLR_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_CLR_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_CLR_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DN_MASK) - -#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) - -#define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_CLR_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name TX_TOG - USB PHY Transmitter Control Register */ -/*! @{ */ - -#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) -#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) - -#define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK) - -#define USBPHY_TX_TOG_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_TOG_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_TOG_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DN_MASK) - -#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) - -#define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_TOG_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name RX - USB PHY Receiver Control Register */ -/*! @{ */ - -#define USBPHY_RX_ENVADJ_MASK (0x7U) -#define USBPHY_RX_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) - -#define USBPHY_RX_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) - -#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) -/*! @} */ - -/*! @name RX_SET - USB PHY Receiver Control Register */ -/*! @{ */ - -#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) -#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) - -#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) - -#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) -/*! @} */ - -/*! @name RX_CLR - USB PHY Receiver Control Register */ -/*! @{ */ - -#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) -#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) - -#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) - -#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) -/*! @} */ - -/*! @name RX_TOG - USB PHY Receiver Control Register */ -/*! @{ */ - -#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) -#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) - -#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) - -#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) -/*! @} */ - -/*! @name CTRL - USB PHY General Control Register */ -/*! @{ */ - -#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) - -#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) -#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) -#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) - -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) - -#define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK) - -#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) -#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) -#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) - -#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) -#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) -#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) - -#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) -#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) -#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) - -#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) -#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) -#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) - -#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) - -#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) - -#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) - -#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) -#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) -#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) - -#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) -#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) -#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) - -#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) - -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) - -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) - -#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) -#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) -#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) - -#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) -#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) -#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) - -#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) -#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT (25U) -#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK) - -#define USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK (0x4000000U) -#define USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT (26U) -#define USBPHY_CTRL_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK) - -#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) - -#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) - -#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) - -#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_SET - USB PHY General Control Register */ -/*! @{ */ - -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) - -#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) -#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) -#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) - -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) - -#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK) - -#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) -#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) -#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) - -#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) -#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) -#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) - -#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) -#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) -#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) - -#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) -#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) -#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) - -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) - -#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) - -#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) - -#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) -#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) -#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) - -#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) -#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) -#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) - -#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) - -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) - -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) - -#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) -#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) -#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) - -#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) -#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) -#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) - -#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) -#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT (25U) -#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK) - -#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK (0x4000000U) -#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT (26U) -#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK) - -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) - -#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) - -#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) - -#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_CLR - USB PHY General Control Register */ -/*! @{ */ - -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) - -#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) -#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) -#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) - -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) - -#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK) - -#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) - -#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) -#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) -#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) - -#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) -#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) -#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) - -#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) -#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) -#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) - -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) - -#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) - -#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) - -#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) -#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) -#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) - -#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) -#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) -#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) - -#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) - -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) - -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) - -#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) -#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) -#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) - -#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) -#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) -#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) - -#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT (25U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK) - -#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK (0x4000000U) -#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT (26U) -#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK) - -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) - -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) - -#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) - -#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_TOG - USB PHY General Control Register */ -/*! @{ */ - -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) - -#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) -#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) -#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) - -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) - -#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK) - -#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) - -#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) -#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) -#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) - -#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) -#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) -#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) - -#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) -#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) -#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) - -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) - -#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) - -#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) - -#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) -#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) -#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) - -#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) -#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) -#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) - -#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) - -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) - -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) - -#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) -#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) -#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) - -#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) -#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) -#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) - -#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT (25U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK) - -#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK (0x4000000U) -#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT (26U) -#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK) - -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) - -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) - -#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) - -#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) -/*! @} */ - -/*! @name STATUS - USB PHY Status Register */ -/*! @{ */ - -#define USBPHY_STATUS_OK_STATUS_3V_MASK (0x1U) -#define USBPHY_STATUS_OK_STATUS_3V_SHIFT (0U) -#define USBPHY_STATUS_OK_STATUS_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OK_STATUS_3V_SHIFT)) & USBPHY_STATUS_OK_STATUS_3V_MASK) - -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) -/*! HOSTDISCONDETECT_STATUS - * 0b0..USB cable disconnect has not been detected at the local host - * 0b1..USB cable disconnect has been detected at the local host - */ -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) - -#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) -#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) -/*! DEVPLUGIN_STATUS - * 0b0..No attachment to a USB host is detected - * 0b1..Cable attachment to a USB host is detected - */ -#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) - -#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) -#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) -#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) -/*! @} */ - -/*! @name PLL_SIC - USB PHY PLL Control/Status Register */ -/*! @{ */ - -#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) - -#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) - -#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) - -#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) - -#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) - -#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) - -#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) - -#define USBPHY_PLL_SIC_PLL_PREDIV_MASK (0x40000000U) -#define USBPHY_PLL_SIC_PLL_PREDIV_SHIFT (30U) -#define USBPHY_PLL_SIC_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_PREDIV_MASK) - -#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */ -/*! @{ */ - -#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) - -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) - -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK (0x40000000U) -#define USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT (30U) -#define USBPHY_PLL_SIC_SET_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */ -/*! @{ */ - -#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) - -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) - -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK (0x40000000U) -#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT (30U) -#define USBPHY_PLL_SIC_CLR_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */ -/*! @{ */ - -#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) - -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) - -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK (0x40000000U) -#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT (30U) -#define USBPHY_PLL_SIC_TOG_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */ -/*! @{ */ - -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U) -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U) -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U) -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U) -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK (0x2000U) -#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. - * 0b1..Select the external ID value. - */ -#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) -#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. - * 0b1..Select the external VBUS VALID value. - */ -#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK) - -#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x700000U) -#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b000..Powers down the VBUS_VALID comparator - * 0b111..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK) - -#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */ -/*! @{ */ - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U) -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U) -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U) -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U) -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK (0x2000U) -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. - * 0b1..Select the external ID value. - */ -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. - * 0b1..Select the external VBUS VALID value. - */ -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U) -#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b000..Powers down the VBUS_VALID comparator - * 0b111..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */ -/*! @{ */ - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U) -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U) -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U) -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK (0x2000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. - * 0b1..Select the external ID value. - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - * 0b0..Select the muxed value chosen using VBUS_OVERRIDE_EN. - * 0b1..Select the external VBUS VALID value. - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b000..Powers down the VBUS_VALID comparator - * 0b111..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */ -/*! @{ */ - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U) -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U) -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U) -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK (0x2000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - * 0b0..Select the muxed value chosen using ID_OVERRIDE_EN. - * 0b1..Select the external ID value. - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. - * 0b1..Select the external VBUS VALID value. - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b000..Powers down the VBUS_VALID comparator - * 0b111..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */ -/*! @{ */ - -#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U) -#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U) -/*! SESSEND - * 0b0..The VBUS voltage is above the Session Valid threshold - * 0b1..The VBUS voltage is below the Session Valid threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK) - -#define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U) -#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U) -/*! BVALID - * 0b0..The VBUS voltage is below the Session Valid threshold - * 0b1..The VBUS voltage is above the Session Valid threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK) - -#define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U) -#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U) -/*! AVALID - * 0b0..The VBUS voltage is below the Session Valid threshold - * 0b1..The VBUS voltage is above the Session Valid threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK) - -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U) -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U) -/*! VBUS_VALID - * 0b0..VBUS is below the comparator threshold - * 0b1..VBUS is above the comparator threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK) - -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U) -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U) -/*! VBUS_VALID_3V - * 0b0..VBUS voltage is below VBUS_VALID_3V threshold - * 0b1..VBUS voltage is above VBUS_VALID_3V threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK) -/*! @} */ - -/*! @name ANACTRL - USB PHY Analog Control Register */ -/*! @{ */ - -#define USBPHY_ANACTRL_LVI_EN_MASK (0x2U) -#define USBPHY_ANACTRL_LVI_EN_SHIFT (1U) -#define USBPHY_ANACTRL_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_LVI_EN_SHIFT)) & USBPHY_ANACTRL_LVI_EN_MASK) - -#define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU) -#define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U) -#define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) - -#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) -/*! @} */ - -/*! @name ANACTRL_SET - USB PHY Analog Control Register */ -/*! @{ */ - -#define USBPHY_ANACTRL_SET_LVI_EN_MASK (0x2U) -#define USBPHY_ANACTRL_SET_LVI_EN_SHIFT (1U) -#define USBPHY_ANACTRL_SET_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_LVI_EN_SHIFT)) & USBPHY_ANACTRL_SET_LVI_EN_MASK) - -#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU) -#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U) -#define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK) - -#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) -/*! @} */ - -/*! @name ANACTRL_CLR - USB PHY Analog Control Register */ -/*! @{ */ - -#define USBPHY_ANACTRL_CLR_LVI_EN_MASK (0x2U) -#define USBPHY_ANACTRL_CLR_LVI_EN_SHIFT (1U) -#define USBPHY_ANACTRL_CLR_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_LVI_EN_SHIFT)) & USBPHY_ANACTRL_CLR_LVI_EN_MASK) - -#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU) -#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U) -#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK) - -#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) -/*! @} */ - -/*! @name ANACTRL_TOG - USB PHY Analog Control Register */ -/*! @{ */ - -#define USBPHY_ANACTRL_TOG_LVI_EN_MASK (0x2U) -#define USBPHY_ANACTRL_TOG_LVI_EN_SHIFT (1U) -#define USBPHY_ANACTRL_TOG_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_LVI_EN_SHIFT)) & USBPHY_ANACTRL_TOG_LVI_EN_MASK) - -#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU) -#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U) -#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK) - -#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBPHY_Register_Masks */ - - -/* USBPHY - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USBPHY base address */ - #define USBPHY_BASE (0x50038000u) - /** Peripheral USBPHY base address */ - #define USBPHY_BASE_NS (0x40038000u) - /** Peripheral USBPHY base pointer */ - #define USBPHY ((USBPHY_Type *)USBPHY_BASE) - /** Peripheral USBPHY base pointer */ - #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) - /** Array initializer of USBPHY peripheral base addresses */ - #define USBPHY_BASE_ADDRS { USBPHY_BASE } - /** Array initializer of USBPHY peripheral base pointers */ - #define USBPHY_BASE_PTRS { USBPHY } - /** Array initializer of USBPHY peripheral base addresses */ - #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } - /** Array initializer of USBPHY peripheral base pointers */ - #define USBPHY_BASE_PTRS_NS { USBPHY_NS } -#else - /** Peripheral USBPHY base address */ - #define USBPHY_BASE (0x40038000u) - /** Peripheral USBPHY base pointer */ - #define USBPHY ((USBPHY_Type *)USBPHY_BASE) - /** Array initializer of USBPHY peripheral base addresses */ - #define USBPHY_BASE_ADDRS { USBPHY_BASE } - /** Array initializer of USBPHY peripheral base pointers */ - #define USBPHY_BASE_PTRS { USBPHY } -#endif -/** Interrupt vectors for the USBPHY peripheral type */ -#define USBPHY_IRQS { USB1_PHY_IRQn } - -/*! - * @} - */ /* end of group USBPHY_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- UTICK Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer - * @{ - */ - -/** UTICK - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ - __IO uint32_t STAT; /**< Status register., offset: 0x4 */ - __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ - __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ - __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ -} UTICK_Type; - -/* ---------------------------------------------------------------------------- - -- UTICK Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Register_Masks UTICK Register Masks - * @{ - */ - -/*! @name CTRL - Control register. */ -/*! @{ */ - -#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) -#define UTICK_CTRL_DELAYVAL_SHIFT (0U) -/*! DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer - * clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer. - */ -#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) - -#define UTICK_CTRL_REPEAT_MASK (0x80000000U) -#define UTICK_CTRL_REPEAT_SHIFT (31U) -/*! REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. - */ -#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) -/*! @} */ - -/*! @name STAT - Status register. */ -/*! @{ */ - -#define UTICK_STAT_INTR_MASK (0x1U) -#define UTICK_STAT_INTR_SHIFT (0U) -/*! INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any - * value to this register clears this flag. - */ -#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) - -#define UTICK_STAT_ACTIVE_MASK (0x2U) -#define UTICK_STAT_ACTIVE_SHIFT (1U) -/*! ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. - */ -#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) -/*! @} */ - -/*! @name CFG - Capture configuration register. */ -/*! @{ */ - -#define UTICK_CFG_CAPEN0_MASK (0x1U) -#define UTICK_CFG_CAPEN0_SHIFT (0U) -/*! CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled. - */ -#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) - -#define UTICK_CFG_CAPEN1_MASK (0x2U) -#define UTICK_CFG_CAPEN1_SHIFT (1U) -/*! CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled. - */ -#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) - -#define UTICK_CFG_CAPEN2_MASK (0x4U) -#define UTICK_CFG_CAPEN2_SHIFT (2U) -/*! CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled. - */ -#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) - -#define UTICK_CFG_CAPEN3_MASK (0x8U) -#define UTICK_CFG_CAPEN3_SHIFT (3U) -/*! CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled. - */ -#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) - -#define UTICK_CFG_CAPPOL0_MASK (0x100U) -#define UTICK_CFG_CAPPOL0_SHIFT (8U) -/*! CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. - */ -#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) - -#define UTICK_CFG_CAPPOL1_MASK (0x200U) -#define UTICK_CFG_CAPPOL1_SHIFT (9U) -/*! CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. - */ -#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) - -#define UTICK_CFG_CAPPOL2_MASK (0x400U) -#define UTICK_CFG_CAPPOL2_SHIFT (10U) -/*! CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. - */ -#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) - -#define UTICK_CFG_CAPPOL3_MASK (0x800U) -#define UTICK_CFG_CAPPOL3_SHIFT (11U) -/*! CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. - */ -#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) -/*! @} */ - -/*! @name CAPCLR - Capture clear register. */ -/*! @{ */ - -#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) -#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) -/*! CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value. - */ -#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) - -#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) -#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) -/*! CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value. - */ -#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) - -#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) -#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) -/*! CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value. - */ -#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) - -#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) -#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) -/*! CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value. - */ -#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) -/*! @} */ - -/*! @name CAP - Capture register . */ -/*! @{ */ - -#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) -#define UTICK_CAP_CAP_VALUE_SHIFT (0U) -/*! CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower - * than the actual value of the Micro-tick Timer at the moment of the capture event. - */ -#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) - -#define UTICK_CAP_VALID_MASK (0x80000000U) -#define UTICK_CAP_VALID_SHIFT (31U) -/*! VALID - Capture Valid. When 1, a value has been captured based on a transition of the related - * UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. - */ -#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) -/*! @} */ - -/* The count of UTICK_CAP */ -#define UTICK_CAP_COUNT (4U) - - -/*! - * @} - */ /* end of group UTICK_Register_Masks */ - - -/* UTICK - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE (0x5000E000u) - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE_NS (0x4000E000u) - /** Peripheral UTICK0 base pointer */ - #define UTICK0 ((UTICK_Type *)UTICK0_BASE) - /** Peripheral UTICK0 base pointer */ - #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS { UTICK0_BASE } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS { UTICK0 } - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS_NS { UTICK0_NS } -#else - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE (0x4000E000u) - /** Peripheral UTICK0 base pointer */ - #define UTICK0 ((UTICK_Type *)UTICK0_BASE) - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS { UTICK0_BASE } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS { UTICK0 } -#endif -/** Interrupt vectors for the UTICK peripheral type */ -#define UTICK_IRQS { UTICK0_IRQn } - -/*! - * @} - */ /* end of group UTICK_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- WWDT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer - * @{ - */ - -/** WWDT - Register Layout Typedef */ -typedef struct { - __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ - __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ - __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ - __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ - uint8_t RESERVED_0[4]; - __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ - __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ -} WWDT_Type; - -/* ---------------------------------------------------------------------------- - -- WWDT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Register_Masks WWDT Register Masks - * @{ - */ - -/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ -/*! @{ */ - -#define WWDT_MOD_WDEN_MASK (0x1U) -#define WWDT_MOD_WDEN_SHIFT (0U) -/*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the - * watchdog timer will run permanently. - * 0b0..Stop. The watchdog timer is stopped. - * 0b1..Run. The watchdog timer is running. - */ -#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) - -#define WWDT_MOD_WDRESET_MASK (0x2U) -#define WWDT_MOD_WDRESET_SHIFT (1U) -/*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. - * 0b0..Interrupt. A watchdog time-out will not cause a chip reset. - * 0b1..Reset. A watchdog time-out will cause a chip reset. - */ -#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) - -#define WWDT_MOD_WDTOF_MASK (0x4U) -#define WWDT_MOD_WDTOF_SHIFT (2U) -/*! WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by - * events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a - * chip reset if WDRESET = 1. - */ -#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) - -#define WWDT_MOD_WDINT_MASK (0x8U) -#define WWDT_MOD_WDINT_SHIFT (3U) -/*! WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. - * Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the - * WARNINT value is equal to the value of the TV register. This can occur if the value of - * WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. - */ -#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) - -#define WWDT_MOD_WDPROTECT_MASK (0x10U) -#define WWDT_MOD_WDPROTECT_SHIFT (4U) -/*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. - * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time. - * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. - */ -#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) -/*! @} */ - -/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ -/*! @{ */ - -#define WWDT_TC_COUNT_MASK (0xFFFFFFU) -#define WWDT_TC_COUNT_SHIFT (0U) -/*! COUNT - Watchdog time-out value. - */ -#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) -/*! @} */ - -/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ -/*! @{ */ - -#define WWDT_FEED_FEED_MASK (0xFFU) -#define WWDT_FEED_FEED_SHIFT (0U) -/*! FEED - Feed value should be 0xAA followed by 0x55. - */ -#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) -/*! @} */ - -/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ -/*! @{ */ - -#define WWDT_TV_COUNT_MASK (0xFFFFFFU) -#define WWDT_TV_COUNT_SHIFT (0U) -/*! COUNT - Counter timer value. - */ -#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) -/*! @} */ - -/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ -/*! @{ */ - -#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) -#define WWDT_WARNINT_WARNINT_SHIFT (0U) -/*! WARNINT - Watchdog warning interrupt compare value. - */ -#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) -/*! @} */ - -/*! @name WINDOW - Watchdog Window compare value. */ -/*! @{ */ - -#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) -#define WWDT_WINDOW_WINDOW_SHIFT (0U) -/*! WINDOW - Watchdog window value. - */ -#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group WWDT_Register_Masks */ - - -/* WWDT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral WWDT base address */ - #define WWDT_BASE (0x5000C000u) - /** Peripheral WWDT base address */ - #define WWDT_BASE_NS (0x4000C000u) - /** Peripheral WWDT base pointer */ - #define WWDT ((WWDT_Type *)WWDT_BASE) - /** Peripheral WWDT base pointer */ - #define WWDT_NS ((WWDT_Type *)WWDT_BASE_NS) - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS { WWDT_BASE } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS { WWDT } - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS_NS { WWDT_BASE_NS } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS_NS { WWDT_NS } -#else - /** Peripheral WWDT base address */ - #define WWDT_BASE (0x4000C000u) - /** Peripheral WWDT base pointer */ - #define WWDT ((WWDT_Type *)WWDT_BASE) - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS { WWDT_BASE } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS { WWDT } -#endif -/** Interrupt vectors for the WWDT peripheral type */ -#define WWDT_IRQS { WDT_BOD_IRQn } - -/*! - * @} - */ /* end of group WWDT_Peripheral_Access_Layer */ - - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop - #else - #pragma pop - #endif -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -/*! - * @} - */ /* end of group Peripheral_access_layer */ - - -/* ---------------------------------------------------------------------------- - -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - * @{ - */ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang system_header - #endif -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma system_include -#endif - -/** - * @brief Mask and left-shift a bit field value for use in a register bit range. - * @param field Name of the register bit field. - * @param value Value of the bit field. - * @return Masked and shifted value. - */ -#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) -/** - * @brief Mask and right-shift a register value to extract a bit field value. - * @param field Name of the register bit field. - * @param value Value of the register. - * @return Masked and shifted bit field value. - */ -#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) - -/*! - * @} - */ /* end of group Bit_Field_Generic_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SDK Compatibility - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDK_Compatibility_Symbols SDK Compatibility - * @{ - */ - -/** High Speed SPI (Flexcomm 8) interrupt name */ -#define LSPI_HS_IRQn FLEXCOMM8_IRQn - - -/*! - * @} - */ /* end of group SDK_Compatibility_Symbols */ - - -#endif /* _LPC55S16_H_ */ - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/LPC55S16_features.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/LPC55S16_features.h deleted file mode 100644 index 34d3df6c55e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/LPC55S16_features.h +++ /dev/null @@ -1,451 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.1, 2019-12-03 -** Build: b220303 -** -** Abstract: -** Chip specific module features. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** - rev. 1.1 (2019-12-03) -** Initial version based on v0.6UM -** -** ################################################################### -*/ - -#ifndef _LPC55S16_FEATURES_H_ -#define _LPC55S16_FEATURES_H_ - -/* SOC module features */ - -/* @brief LPC_CAN availability on the SoC. */ -#define FSL_FEATURE_SOC_LPC_CAN_COUNT (1) -/* @brief CASPER availability on the SoC. */ -#define FSL_FEATURE_SOC_CASPER_COUNT (1) -/* @brief CRC availability on the SoC. */ -#define FSL_FEATURE_SOC_CRC_COUNT (1) -/* @brief CTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_CTIMER_COUNT (5) -/* @brief CDOG availability on the SoC. */ -#define FSL_FEATURE_SOC_CDOG_COUNT (1) -/* @brief DMA availability on the SoC. */ -#define FSL_FEATURE_SOC_DMA_COUNT (2) -/* @brief FLASH availability on the SoC. */ -#define FSL_FEATURE_SOC_FLASH_COUNT (1) -/* @brief FLEXCOMM availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) -/* @brief GINT availability on the SoC. */ -#define FSL_FEATURE_SOC_GINT_COUNT (2) -/* @brief GPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_GPIO_COUNT (1) -/* @brief SECGPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_SECGPIO_COUNT (1) -/* @brief HASHCRYPT availability on the SoC. */ -#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) -/* @brief I2C availability on the SoC. */ -#define FSL_FEATURE_SOC_I2C_COUNT (8) -/* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (8) -/* @brief INPUTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) -/* @brief IOCON availability on the SoC. */ -#define FSL_FEATURE_SOC_IOCON_COUNT (1) -/* @brief LPADC availability on the SoC. */ -#define FSL_FEATURE_SOC_LPADC_COUNT (1) -/* @brief MRT availability on the SoC. */ -#define FSL_FEATURE_SOC_MRT_COUNT (1) -/* @brief OSTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) -/* @brief PINT availability on the SoC. */ -#define FSL_FEATURE_SOC_PINT_COUNT (1) -/* @brief SECPINT availability on the SoC. */ -#define FSL_FEATURE_SOC_SECPINT_COUNT (1) -/* @brief PMC availability on the SoC. */ -#define FSL_FEATURE_SOC_PMC_COUNT (1) -/* @brief PUF availability on the SoC. */ -#define FSL_FEATURE_SOC_PUF_COUNT (1) -/* @brief PUF_SRAM_CTRL availability on the SoC. */ -#define FSL_FEATURE_SOC_PUF_SRAM_CTRL_COUNT (1) -/* @brief LPC_RNG1 availability on the SoC. */ -#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) -/* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (1) -/* @brief SCT availability on the SoC. */ -#define FSL_FEATURE_SOC_SCT_COUNT (1) -/* @brief SPI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPI_COUNT (9) -/* @brief SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCON_COUNT (1) -/* @brief SYSCTL1 availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) -/* @brief USART availability on the SoC. */ -#define FSL_FEATURE_SOC_USART_COUNT (8) -/* @brief USB availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_COUNT (1) -/* @brief USBFSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBFSH_COUNT (1) -/* @brief USBHSD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSD_COUNT (1) -/* @brief USBHSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSH_COUNT (1) -/* @brief USBPHY availability on the SoC. */ -#define FSL_FEATURE_SOC_USBPHY_COUNT (1) -/* @brief UTICK availability on the SoC. */ -#define FSL_FEATURE_SOC_UTICK_COUNT (1) -/* @brief WWDT availability on the SoC. */ -#define FSL_FEATURE_SOC_WWDT_COUNT (1) - -/* LPADC module features */ - -/* @brief FIFO availability on the SoC. */ -#define FSL_FEATURE_LPADC_FIFO_COUNT (2) -/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) -/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) -/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) -/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) -/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) -/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) -/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) -/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) -/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) -/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) -/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) -/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) -/* @brief Has calibration (bitfield CFG[CALOFS]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) -/* @brief Has offset trim (register OFSTRIM). */ -#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) -/* @brief Has Trigger status register. */ -#define FSL_FEATURE_LPADC_HAS_TSTAT (1) -/* @brief Has power select (bitfield CFG[PWRSEL]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) -/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) -/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) -/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) -/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) -/* @brief Conversion averaged bitfiled width. */ -#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) -/* @brief Has internal temperature sensor. */ -#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) -/* @brief Temperature sensor parameter A (slope). */ -#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (799.0f) -/* @brief Temperature sensor parameter B (offset). */ -#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (280.0f) -/* @brief Temperature sensor parameter Alpha. */ -#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (8.5f) -/* @brief Temperature sensor need calibration. */ -#define FSL_FEATURE_LPADC_TEMP_NEED_CALIBRATION (1) -/* @brief the address of temperature sensor parameter A (slope) in Flash. */ -#define FSL_FEATURE_FLASH_NMPA_TEMP_SLOPE_ADDRS (0x3FD28U) -/* @brief the address of temperature sensor parameter B (offset) in Flash. */ -#define FSL_FEATURE_FLASH_NMPA_TEMP_OFFSET_ADDRS (0x3FD2CU) -/* @brief the buffer size of temperature sensor. */ -#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) - -/* ANALOGCTRL module features */ - -/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ -#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) -/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ -#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (1) -/* @brief Has auxiliary bias(register AUX_BIAS). */ -#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1) - -/* CAN module features */ - -/* @brief Support CANFD or not */ -#define FSL_FEATURE_CAN_SUPPORT_CANFD (1) - -/* CASPER module features */ - -/* @brief Base address of the CASPER dedicated RAM */ -#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) -/* @brief HW interleaving of the CASPER dedicated RAM */ -#define FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE (1) - -/* CTIMER module features */ - -/* @brief CTIMER has no capture channel. */ -#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) -/* @brief CTIMER has no capture 2 interrupt. */ -#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) -/* @brief CTIMER capture 3 interrupt. */ -#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) -/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ -#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) -/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ -#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) - -/* DMA module features */ - -/* @brief Number of channels */ -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23) -/* @brief Align size of DMA descriptor */ -#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) -/* @brief DMA head link descriptor table align size */ -#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) - -/* FLEXCOMM module features */ - -/* @brief FLEXCOMM0 USART INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) -/* @brief FLEXCOMM0 SPI INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) -/* @brief FLEXCOMM0 I2C INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) -/* @brief FLEXCOMM0 I2S INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) -/* @brief FLEXCOMM1 USART INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) -/* @brief FLEXCOMM1 SPI INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) -/* @brief FLEXCOMM1 I2C INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) -/* @brief FLEXCOMM1 I2S INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) -/* @brief FLEXCOMM2 USART INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) -/* @brief FLEXCOMM2 SPI INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) -/* @brief FLEXCOMM2 I2C INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) -/* @brief FLEXCOMM2 I2S INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) -/* @brief FLEXCOMM3 USART INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) -/* @brief FLEXCOMM3 SPI INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) -/* @brief FLEXCOMM3 I2C INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) -/* @brief FLEXCOMM3 I2S INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) -/* @brief FLEXCOMM4 USART INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) -/* @brief FLEXCOMM4 SPI INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) -/* @brief FLEXCOMM4 I2C INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) -/* @brief FLEXCOMM4 I2S INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) -/* @brief FLEXCOMM5 USART INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) -/* @brief FLEXCOMM5 SPI INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) -/* @brief FLEXCOMM5 I2C INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) -/* @brief FLEXCOMM5 I2S INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) -/* @brief FLEXCOMM6 USART INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) -/* @brief FLEXCOMM6 SPI INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) -/* @brief FLEXCOMM6 I2C INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) -/* @brief FLEXCOMM6 I2S INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) -/* @brief FLEXCOMM7 USART INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) -/* @brief FLEXCOMM7 SPI INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) -/* @brief FLEXCOMM7 I2C INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) -/* @brief FLEXCOMM7 I2S INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) -/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ -#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) -/* @brief I2S has DMIC interconnection */ -#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) -/* @brief I2S support dual channel transfer */ -#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn(x) \ - (((x) == FLEXCOMM0) ? (0) : \ - (((x) == FLEXCOMM1) ? (0) : \ - (((x) == FLEXCOMM2) ? (0) : \ - (((x) == FLEXCOMM3) ? (0) : \ - (((x) == FLEXCOMM4) ? (0) : \ - (((x) == FLEXCOMM5) ? (0) : \ - (((x) == FLEXCOMM6) ? (1) : \ - (((x) == FLEXCOMM7) ? (1) : \ - (((x) == FLEXCOMM8) ? (0) : (-1)))))))))) - -/* HASHCRYPT module features */ - -/* @brief the address of alias offset */ -#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000) -/* @brief hashcrypt has reload feature */ -#define FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE (1) - -/* I2S module features */ - -/* @brief I2S6 and I2S7 support dual channel transfer. */ -#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) -/* @brief I2S has DMIC interconnection */ -#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) - -/* IOCON module features */ - -/* @brief Func bit field width */ -#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) - -/* MRT module features */ - -/* @brief number of channels. */ -#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) - -/* PINT module features */ - -/* @brief Number of connected outputs */ -#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) - -/* PLU module features */ - -/* @brief Has WAKEINT_CTRL register. */ -#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) - -/* PMC module features */ - -/* @brief UTICK does not support PD configure. */ -#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) -/* @brief WDT OSC does not support PD configure. */ -#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) - -/* POWERLIB module features */ - -/* @brief Powerlib API is different with other LPC series devices. */ -#define FSL_FEATURE_POWERLIB_EXTEND (1) - -/* PUF module features */ - -/* @brief Number of PUF key slots available on device. */ -#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4) -/* @brief the shift status value */ -#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) -/* @brief PUF has dedicated SRAM control */ -#define FSL_FEATURE_PUF_HAS_SRAM_CTRL (1) - -/* RTC module features */ - -/* No feature definitions */ - -/* SCT module features */ - -/* @brief Number of events */ -#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) -/* @brief Number of states */ -#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) -/* @brief Number of match capture */ -#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) -/* @brief Number of outputs */ -#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) - -/* SECPINT module features */ - -/* @brief Number of connected outputs */ -#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) - -/* SYSCON module features */ - -/* @brief Flash page size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) -/* @brief Flash sector size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) -/* @brief Flash size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (251904) -/* @brief Has Power Down mode */ -#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) -/* @brief CCM_ANALOG availability on the SoC. */ -#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) -/* @brief Starter register discontinuous. */ -#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) - -/* SYSCTL1 module features */ - -/* @brief SYSCTRL has Code Gray feature. */ -#define FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY (1) - -/* USB module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USB_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x20010000) -/* @brief USB version */ -#define FSL_FEATURE_USB_VERSION (200) -/* @brief Number of the endpoint in USB FS */ -#define FSL_FEATURE_USB_EP_NUM (5) - -/* USBFSH module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x20010000) -/* @brief USBFSH version */ -#define FSL_FEATURE_USBFSH_VERSION (200) - -/* USBHSD module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x20010000) -/* @brief USBHSD version */ -#define FSL_FEATURE_USBHSD_VERSION (300) -/* @brief Number of the endpoint in USB HS */ -#define FSL_FEATURE_USBHSD_EP_NUM (6) - -/* USBHSH module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x20010000) -/* @brief USBHSH version */ -#define FSL_FEATURE_USBHSH_VERSION (300) - -/* USBPHY module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBPHY_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x20010000) -/* @brief USBHSD version */ -#define FSL_FEATURE_USBPHY_VERSION (300) -/* @brief Number of the endpoint in USB HS */ -#define FSL_FEATURE_USBPHY_EP_NUM (6) - -/* WWDT module features */ - -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) -/* @brief WWDT does not support oscillator lock. */ -#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) - -#endif /* _LPC55S16_FEATURES_H_ */ - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC551XX_256.FLM b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC551XX_256.FLM deleted file mode 100644 index 4440cef8784..00000000000 Binary files a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC551XX_256.FLM and /dev/null differ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC551XX_S_256.FLM b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC551XX_S_256.FLM deleted file mode 100644 index 659c35c994c..00000000000 Binary files a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC551XX_S_256.FLM and /dev/null differ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC55S16_flash.scf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC55S16_flash.scf deleted file mode 100644 index 99d6a233a27..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC55S16_flash.scf +++ /dev/null @@ -1,86 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c -/* -** ################################################################### -** Processors: LPC55S16JBD100 -** LPC55S16JBD64 -** LPC55S16JEV59 -** LPC55S16JEV98 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 -** Version: rev. 1.1, 2019-12-03 -** Build: b220622 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#define m_interrupts_start 0x00000000 -#define m_interrupts_size 0x00000200 - -#define m_text_start 0x00000200 -#define m_text_size 0x0003CE00 - -#define m_data_start 0x20000000 -#define m_data_size 0x00010000 - -#define m_sramx_start 0x04000000 -#define m_sramx_size 0x00004000 - -#define m_usb_sram_start 0x20010000 -#define m_usb_sram_size 0x00004000 - -LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region - - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - - RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (*m_usb_bdt) - } - - RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (*m_usb_global) - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC55S16_ram.scf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC55S16_ram.scf deleted file mode 100644 index 1986299df78..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC55S16_ram.scf +++ /dev/null @@ -1,83 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c -/* -** ################################################################### -** Processors: LPC55S16JBD100 -** LPC55S16JBD64 -** LPC55S16JEV59 -** LPC55S16JEV98 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 -** Version: rev. 1.1, 2019-12-03 -** Build: b220622 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#define m_interrupts_start 0x20000000 -#define m_interrupts_size 0x00000200 - -#define m_text_start 0x20000200 -#define m_text_size 0x0000FE00 - -#define m_data_start 0x04000000 -#define m_data_size 0x00004000 - -#define m_usb_sram_start 0x20010000 -#define m_usb_sram_size 0x00004000 - -LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region - - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - - RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (*m_usb_bdt) - } - - RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (*m_usb_global) - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC55S1xx.dbgconf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC55S1xx.dbgconf deleted file mode 100644 index 1cc3a2af84a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC55S1xx.dbgconf +++ /dev/null @@ -1,18 +0,0 @@ -// <<< Use Configuration Wizard in Context Menu >>> - -// SWO pin -// The SWO (Serial Wire Output) pin optionally provides data from the ITM -// for an external debug tool to evaluate. -// <0=> PIO0_10 -// <1=> PIO0_8 -SWO_Pin = 0; -// - -// Debug Configuration -// StopAfterBootloader Stop after Bootloader -// -Dbg_CR = 0x00000001; -// - - -// <<< end of configuration section >>> \ No newline at end of file diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/startup_LPC55S16.S b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/startup_LPC55S16.S deleted file mode 100644 index 134148bf5ee..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/startup_LPC55S16.S +++ /dev/null @@ -1,812 +0,0 @@ -/* --------------------------------------------------------------------------------------- - * @file: startup_LPC55S16.s - * @purpose: CMSIS Cortex-M33 Core Device Startup File for the LPC55S16 - * @version: 1.1 - * @date: 2019-12-3 - * ---------------------------------------------------------------------------------------*/ -/* - * Copyright 1997-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - - .syntax unified - .arch armv8-m.main - .eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */ - - .section .isr_vector, "a" - .align 2 - .globl __Vectors - -__Vectors: - .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long MemManage_Handler /* MPU Fault Handler*/ - .long BusFault_Handler /* Bus Fault Handler*/ - .long UsageFault_Handler /* Usage Fault Handler*/ - .long SecureFault_Handler /* Secure Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long DebugMon_Handler /* Debug Monitor Handler*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts*/ - .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ - .long DMA0_IRQHandler /* DMA0 controller */ - .long GINT0_IRQHandler /* GPIO group 0 */ - .long GINT1_IRQHandler /* GPIO group 1 */ - .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - .long UTICK0_IRQHandler /* Micro-tick Timer */ - .long MRT0_IRQHandler /* Multi-rate timer */ - .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ - .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ - .long SCT0_IRQHandler /* SCTimer/PWM */ - .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ - .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long ADC0_IRQHandler /* ADC0 */ - .long Reserved39_IRQHandler /* Reserved interrupt */ - .long ACMP_IRQHandler /* ACMP interrupts */ - .long Reserved41_IRQHandler /* Reserved interrupt */ - .long Reserved42_IRQHandler /* Reserved interrupt */ - .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ - .long USB0_IRQHandler /* USB device */ - .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ - .long Reserved46_IRQHandler /* Reserved interrupt */ - .long Reserved47_IRQHandler /* Reserved interrupt */ - .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ - .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ - .long OS_EVENT_IRQHandler /* OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ - .long Reserved55_IRQHandler /* Reserved interrupt */ - .long Reserved56_IRQHandler /* Reserved interrupt */ - .long Reserved57_IRQHandler /* Reserved interrupt */ - .long Reserved58_IRQHandler /* Reserved interrupt */ - .long CAN0_IRQ0_IRQHandler /* CAN0 interrupt0 */ - .long CAN0_IRQ1_IRQHandler /* CAN0 interrupt1 */ - .long Reserved61_IRQHandler /* Reserved interrupt */ - .long USB1_PHY_IRQHandler /* USB1_PHY */ - .long USB1_IRQHandler /* USB1 interrupt */ - .long USB1_NEEDCLK_IRQHandler /* USB1 activity */ - .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ - .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ - .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ - .long PLU_IRQHandler /* PLU interrupt */ - .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ - .long HASHCRYPT_IRQHandler /* SHA interrupt */ - .long CASER_IRQHandler /* CASPER interrupt */ - .long PUF_IRQHandler /* PUF interrupt */ - .long Reserved73_IRQHandler /* Reserved interrupt */ - .long DMA1_IRQHandler /* DMA1 interrupt */ - .long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ - .long CDOG_IRQHandler /* CDOG interrupt */ - .size __Vectors, . - __Vectors - - .text - .thumb - -/* Reset Handler */ - .thumb_func - .align 2 - .weak Reset_Handler - .type Reset_Handler, %function - -Reset_Handler: - cpsid i /* Mask interrupts */ - .equ VTOR, 0xE000ED08 - ldr r0, =VTOR - ldr r1, =__Vectors - str r1, [r0] - ldr r2, [r1] - msr msp, r2 - ldr R0, =Image$$ARM_LIB_STACK$$ZI$$Base - msr msplim, R0 - ldr r0,=SystemInit - blx r0 - cpsie i /* Unmask interrupts */ - ldr r0,=__main - bx r0 - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - .align 1 - .thumb_func - .weak WDT_BOD_IRQHandler - .type WDT_BOD_IRQHandler, %function -WDT_BOD_IRQHandler: - ldr r0,=WDT_BOD_DriverIRQHandler - bx r0 - .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler - - .align 1 - .thumb_func - .weak DMA0_IRQHandler - .type DMA0_IRQHandler, %function -DMA0_IRQHandler: - ldr r0,=DMA0_DriverIRQHandler - bx r0 - .size DMA0_IRQHandler, . - DMA0_IRQHandler - - .align 1 - .thumb_func - .weak GINT0_IRQHandler - .type GINT0_IRQHandler, %function -GINT0_IRQHandler: - ldr r0,=GINT0_DriverIRQHandler - bx r0 - .size GINT0_IRQHandler, . - GINT0_IRQHandler - - .align 1 - .thumb_func - .weak GINT1_IRQHandler - .type GINT1_IRQHandler, %function -GINT1_IRQHandler: - ldr r0,=GINT1_DriverIRQHandler - bx r0 - .size GINT1_IRQHandler, . - GINT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT0_IRQHandler - .type PIN_INT0_IRQHandler, %function -PIN_INT0_IRQHandler: - ldr r0,=PIN_INT0_DriverIRQHandler - bx r0 - .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT1_IRQHandler - .type PIN_INT1_IRQHandler, %function -PIN_INT1_IRQHandler: - ldr r0,=PIN_INT1_DriverIRQHandler - bx r0 - .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT2_IRQHandler - .type PIN_INT2_IRQHandler, %function -PIN_INT2_IRQHandler: - ldr r0,=PIN_INT2_DriverIRQHandler - bx r0 - .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT3_IRQHandler - .type PIN_INT3_IRQHandler, %function -PIN_INT3_IRQHandler: - ldr r0,=PIN_INT3_DriverIRQHandler - bx r0 - .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler - - .align 1 - .thumb_func - .weak UTICK0_IRQHandler - .type UTICK0_IRQHandler, %function -UTICK0_IRQHandler: - ldr r0,=UTICK0_DriverIRQHandler - bx r0 - .size UTICK0_IRQHandler, . - UTICK0_IRQHandler - - .align 1 - .thumb_func - .weak MRT0_IRQHandler - .type MRT0_IRQHandler, %function -MRT0_IRQHandler: - ldr r0,=MRT0_DriverIRQHandler - bx r0 - .size MRT0_IRQHandler, . - MRT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER0_IRQHandler - .type CTIMER0_IRQHandler, %function -CTIMER0_IRQHandler: - ldr r0,=CTIMER0_DriverIRQHandler - bx r0 - .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER1_IRQHandler - .type CTIMER1_IRQHandler, %function -CTIMER1_IRQHandler: - ldr r0,=CTIMER1_DriverIRQHandler - bx r0 - .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler - - .align 1 - .thumb_func - .weak SCT0_IRQHandler - .type SCT0_IRQHandler, %function -SCT0_IRQHandler: - ldr r0,=SCT0_DriverIRQHandler - bx r0 - .size SCT0_IRQHandler, . - SCT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER3_IRQHandler - .type CTIMER3_IRQHandler, %function -CTIMER3_IRQHandler: - ldr r0,=CTIMER3_DriverIRQHandler - bx r0 - .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM0_IRQHandler - .type FLEXCOMM0_IRQHandler, %function -FLEXCOMM0_IRQHandler: - ldr r0,=FLEXCOMM0_DriverIRQHandler - bx r0 - .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM1_IRQHandler - .type FLEXCOMM1_IRQHandler, %function -FLEXCOMM1_IRQHandler: - ldr r0,=FLEXCOMM1_DriverIRQHandler - bx r0 - .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM2_IRQHandler - .type FLEXCOMM2_IRQHandler, %function -FLEXCOMM2_IRQHandler: - ldr r0,=FLEXCOMM2_DriverIRQHandler - bx r0 - .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM3_IRQHandler - .type FLEXCOMM3_IRQHandler, %function -FLEXCOMM3_IRQHandler: - ldr r0,=FLEXCOMM3_DriverIRQHandler - bx r0 - .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM4_IRQHandler - .type FLEXCOMM4_IRQHandler, %function -FLEXCOMM4_IRQHandler: - ldr r0,=FLEXCOMM4_DriverIRQHandler - bx r0 - .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM5_IRQHandler - .type FLEXCOMM5_IRQHandler, %function -FLEXCOMM5_IRQHandler: - ldr r0,=FLEXCOMM5_DriverIRQHandler - bx r0 - .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM6_IRQHandler - .type FLEXCOMM6_IRQHandler, %function -FLEXCOMM6_IRQHandler: - ldr r0,=FLEXCOMM6_DriverIRQHandler - bx r0 - .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM7_IRQHandler - .type FLEXCOMM7_IRQHandler, %function -FLEXCOMM7_IRQHandler: - ldr r0,=FLEXCOMM7_DriverIRQHandler - bx r0 - .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_IRQHandler - .type ADC0_IRQHandler, %function -ADC0_IRQHandler: - ldr r0,=ADC0_DriverIRQHandler - bx r0 - .size ADC0_IRQHandler, . - ADC0_IRQHandler - - .align 1 - .thumb_func - .weak Reserved39_IRQHandler - .type Reserved39_IRQHandler, %function -Reserved39_IRQHandler: - ldr r0,=Reserved39_DriverIRQHandler - bx r0 - .size Reserved39_IRQHandler, . - Reserved39_IRQHandler - - .align 1 - .thumb_func - .weak ACMP_IRQHandler - .type ACMP_IRQHandler, %function -ACMP_IRQHandler: - ldr r0,=ACMP_DriverIRQHandler - bx r0 - .size ACMP_IRQHandler, . - ACMP_IRQHandler - - .align 1 - .thumb_func - .weak Reserved41_IRQHandler - .type Reserved41_IRQHandler, %function -Reserved41_IRQHandler: - ldr r0,=Reserved41_DriverIRQHandler - bx r0 - .size Reserved41_IRQHandler, . - Reserved41_IRQHandler - - .align 1 - .thumb_func - .weak Reserved42_IRQHandler - .type Reserved42_IRQHandler, %function -Reserved42_IRQHandler: - ldr r0,=Reserved42_DriverIRQHandler - bx r0 - .size Reserved42_IRQHandler, . - Reserved42_IRQHandler - - .align 1 - .thumb_func - .weak USB0_NEEDCLK_IRQHandler - .type USB0_NEEDCLK_IRQHandler, %function -USB0_NEEDCLK_IRQHandler: - ldr r0,=USB0_NEEDCLK_DriverIRQHandler - bx r0 - .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak USB0_IRQHandler - .type USB0_IRQHandler, %function -USB0_IRQHandler: - ldr r0,=USB0_DriverIRQHandler - bx r0 - .size USB0_IRQHandler, . - USB0_IRQHandler - - .align 1 - .thumb_func - .weak RTC_IRQHandler - .type RTC_IRQHandler, %function -RTC_IRQHandler: - ldr r0,=RTC_DriverIRQHandler - bx r0 - .size RTC_IRQHandler, . - RTC_IRQHandler - - .align 1 - .thumb_func - .weak Reserved46_IRQHandler - .type Reserved46_IRQHandler, %function -Reserved46_IRQHandler: - ldr r0,=Reserved46_DriverIRQHandler - bx r0 - .size Reserved46_IRQHandler, . - Reserved46_IRQHandler - - .align 1 - .thumb_func - .weak Reserved47_IRQHandler - .type Reserved47_IRQHandler, %function -Reserved47_IRQHandler: - ldr r0,=Reserved47_DriverIRQHandler - bx r0 - .size Reserved47_IRQHandler, . - Reserved47_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT4_IRQHandler - .type PIN_INT4_IRQHandler, %function -PIN_INT4_IRQHandler: - ldr r0,=PIN_INT4_DriverIRQHandler - bx r0 - .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT5_IRQHandler - .type PIN_INT5_IRQHandler, %function -PIN_INT5_IRQHandler: - ldr r0,=PIN_INT5_DriverIRQHandler - bx r0 - .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT6_IRQHandler - .type PIN_INT6_IRQHandler, %function -PIN_INT6_IRQHandler: - ldr r0,=PIN_INT6_DriverIRQHandler - bx r0 - .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT7_IRQHandler - .type PIN_INT7_IRQHandler, %function -PIN_INT7_IRQHandler: - ldr r0,=PIN_INT7_DriverIRQHandler - bx r0 - .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER2_IRQHandler - .type CTIMER2_IRQHandler, %function -CTIMER2_IRQHandler: - ldr r0,=CTIMER2_DriverIRQHandler - bx r0 - .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER4_IRQHandler - .type CTIMER4_IRQHandler, %function -CTIMER4_IRQHandler: - ldr r0,=CTIMER4_DriverIRQHandler - bx r0 - .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler - - .align 1 - .thumb_func - .weak OS_EVENT_IRQHandler - .type OS_EVENT_IRQHandler, %function -OS_EVENT_IRQHandler: - ldr r0,=OS_EVENT_DriverIRQHandler - bx r0 - .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler - - .align 1 - .thumb_func - .weak Reserved55_IRQHandler - .type Reserved55_IRQHandler, %function -Reserved55_IRQHandler: - ldr r0,=Reserved55_DriverIRQHandler - bx r0 - .size Reserved55_IRQHandler, . - Reserved55_IRQHandler - - .align 1 - .thumb_func - .weak Reserved56_IRQHandler - .type Reserved56_IRQHandler, %function -Reserved56_IRQHandler: - ldr r0,=Reserved56_DriverIRQHandler - bx r0 - .size Reserved56_IRQHandler, . - Reserved56_IRQHandler - - .align 1 - .thumb_func - .weak Reserved57_IRQHandler - .type Reserved57_IRQHandler, %function -Reserved57_IRQHandler: - ldr r0,=Reserved57_DriverIRQHandler - bx r0 - .size Reserved57_IRQHandler, . - Reserved57_IRQHandler - - .align 1 - .thumb_func - .weak Reserved58_IRQHandler - .type Reserved58_IRQHandler, %function -Reserved58_IRQHandler: - ldr r0,=Reserved58_DriverIRQHandler - bx r0 - .size Reserved58_IRQHandler, . - Reserved58_IRQHandler - - .align 1 - .thumb_func - .weak CAN0_IRQ0_IRQHandler - .type CAN0_IRQ0_IRQHandler, %function -CAN0_IRQ0_IRQHandler: - ldr r0,=CAN0_IRQ0_DriverIRQHandler - bx r0 - .size CAN0_IRQ0_IRQHandler, . - CAN0_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak CAN0_IRQ1_IRQHandler - .type CAN0_IRQ1_IRQHandler, %function -CAN0_IRQ1_IRQHandler: - ldr r0,=CAN0_IRQ1_DriverIRQHandler - bx r0 - .size CAN0_IRQ1_IRQHandler, . - CAN0_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak Reserved61_IRQHandler - .type Reserved61_IRQHandler, %function -Reserved61_IRQHandler: - ldr r0,=Reserved61_DriverIRQHandler - bx r0 - .size Reserved61_IRQHandler, . - Reserved61_IRQHandler - - .align 1 - .thumb_func - .weak USB1_PHY_IRQHandler - .type USB1_PHY_IRQHandler, %function -USB1_PHY_IRQHandler: - ldr r0,=USB1_PHY_DriverIRQHandler - bx r0 - .size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler - - .align 1 - .thumb_func - .weak USB1_IRQHandler - .type USB1_IRQHandler, %function -USB1_IRQHandler: - ldr r0,=USB1_DriverIRQHandler - bx r0 - .size USB1_IRQHandler, . - USB1_IRQHandler - - .align 1 - .thumb_func - .weak USB1_NEEDCLK_IRQHandler - .type USB1_NEEDCLK_IRQHandler, %function -USB1_NEEDCLK_IRQHandler: - ldr r0,=USB1_NEEDCLK_DriverIRQHandler - bx r0 - .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak SEC_HYPERVISOR_CALL_IRQHandler - .type SEC_HYPERVISOR_CALL_IRQHandler, %function -SEC_HYPERVISOR_CALL_IRQHandler: - ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler - bx r0 - .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ0_IRQHandler - .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function -SEC_GPIO_INT0_IRQ0_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ1_IRQHandler - .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function -SEC_GPIO_INT0_IRQ1_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak PLU_IRQHandler - .type PLU_IRQHandler, %function -PLU_IRQHandler: - ldr r0,=PLU_DriverIRQHandler - bx r0 - .size PLU_IRQHandler, . - PLU_IRQHandler - - .align 1 - .thumb_func - .weak SEC_VIO_IRQHandler - .type SEC_VIO_IRQHandler, %function -SEC_VIO_IRQHandler: - ldr r0,=SEC_VIO_DriverIRQHandler - bx r0 - .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler - - .align 1 - .thumb_func - .weak HASHCRYPT_IRQHandler - .type HASHCRYPT_IRQHandler, %function -HASHCRYPT_IRQHandler: - ldr r0,=HASHCRYPT_DriverIRQHandler - bx r0 - .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler - - .align 1 - .thumb_func - .weak CASER_IRQHandler - .type CASER_IRQHandler, %function -CASER_IRQHandler: - ldr r0,=CASER_DriverIRQHandler - bx r0 - .size CASER_IRQHandler, . - CASER_IRQHandler - - .align 1 - .thumb_func - .weak PUF_IRQHandler - .type PUF_IRQHandler, %function -PUF_IRQHandler: - ldr r0,=PUF_DriverIRQHandler - bx r0 - .size PUF_IRQHandler, . - PUF_IRQHandler - - .align 1 - .thumb_func - .weak Reserved73_IRQHandler - .type Reserved73_IRQHandler, %function -Reserved73_IRQHandler: - ldr r0,=Reserved73_DriverIRQHandler - bx r0 - .size Reserved73_IRQHandler, . - Reserved73_IRQHandler - - .align 1 - .thumb_func - .weak DMA1_IRQHandler - .type DMA1_IRQHandler, %function -DMA1_IRQHandler: - ldr r0,=DMA1_DriverIRQHandler - bx r0 - .size DMA1_IRQHandler, . - DMA1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM8_IRQHandler - .type FLEXCOMM8_IRQHandler, %function -FLEXCOMM8_IRQHandler: - ldr r0,=FLEXCOMM8_DriverIRQHandler - bx r0 - .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler - - .align 1 - .thumb_func - .weak CDOG_IRQHandler - .type CDOG_IRQHandler, %function -CDOG_IRQHandler: - ldr r0,=CDOG_DriverIRQHandler - bx r0 - .size CDOG_IRQHandler, . - CDOG_IRQHandler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm -/* Exception Handlers */ - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SecureFault_Handler - def_irq_handler DebugMon_Handler - def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ - def_irq_handler DMA0_DriverIRQHandler /* DMA0 controller */ - def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */ - def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */ - def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */ - def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */ - def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */ - def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */ - def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */ - def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */ - def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler ADC0_DriverIRQHandler /* ADC0 */ - def_irq_handler Reserved39_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler ACMP_DriverIRQHandler /* ACMP interrupts */ - def_irq_handler Reserved41_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved42_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */ - def_irq_handler USB0_DriverIRQHandler /* USB device */ - def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */ - def_irq_handler Reserved46_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved47_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler PIN_INT4_DriverIRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - def_irq_handler PIN_INT5_DriverIRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - def_irq_handler PIN_INT6_DriverIRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - def_irq_handler PIN_INT7_DriverIRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - def_irq_handler CTIMER2_DriverIRQHandler /* Standard counter/timer CTIMER2 */ - def_irq_handler CTIMER4_DriverIRQHandler /* Standard counter/timer CTIMER4 */ - def_irq_handler OS_EVENT_DriverIRQHandler /* OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ - def_irq_handler Reserved55_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved56_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved57_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved58_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler CAN0_IRQ0_DriverIRQHandler /* CAN0 interrupt0 */ - def_irq_handler CAN0_IRQ1_DriverIRQHandler /* CAN0 interrupt1 */ - def_irq_handler Reserved61_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler USB1_PHY_DriverIRQHandler /* USB1_PHY */ - def_irq_handler USB1_DriverIRQHandler /* USB1 interrupt */ - def_irq_handler USB1_NEEDCLK_DriverIRQHandler /* USB1 activity */ - def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler /* SEC_HYPERVISOR_CALL interrupt */ - def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ - def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ - def_irq_handler PLU_DriverIRQHandler /* PLU interrupt */ - def_irq_handler SEC_VIO_DriverIRQHandler /* SEC_VIO interrupt */ - def_irq_handler HASHCRYPT_DriverIRQHandler /* SHA interrupt */ - def_irq_handler CASER_DriverIRQHandler /* CASPER interrupt */ - def_irq_handler PUF_DriverIRQHandler /* PUF interrupt */ - def_irq_handler Reserved73_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler DMA1_DriverIRQHandler /* DMA1 interrupt */ - def_irq_handler FLEXCOMM8_DriverIRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ - def_irq_handler CDOG_DriverIRQHandler /* CDOG interrupt */ - - .end diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_anactrl.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_anactrl.c deleted file mode 100644 index 68175b880a3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_anactrl.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright 2018-2021, NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_anactrl.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.anactrl" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for ANACTRL module. - * - * @param base ANACTRL peripheral base address - */ -static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to ANACTRL bases for each instance. */ -static ANACTRL_Type *const s_anactrlBases[] = ANACTRL_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to ANACTRL clocks for each instance. */ -static const clock_ip_name_t s_anactrlClocks[] = ANALOGCTRL_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! - * brief Get the ANACTRL instance from peripheral base address. - * - * param base ANACTRL peripheral base address. - * return ANACTRL instance. - */ -static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_anactrlBases); instance++) - { - if (s_anactrlBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_anactrlBases)); - - return instance; -} - -/*! - * brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function. - * - * param base ANACTRL peripheral base address. - */ -void ANACTRL_Init(ANACTRL_Type *base) -{ - assert(NULL != base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock for ANACTRL instance. */ - CLOCK_EnableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function. - * - * param base ANACTRL peripheral base address. - */ -void ANACTRL_Deinit(ANACTRL_Type *base) -{ - assert(NULL != base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock for ANACTRL instance. */ - CLOCK_DisableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock output - * and enable/disable 96MHZ clock output. - * - * param base ANACTRL peripheral base address. - * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure. - */ -void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32 = base->FRO192M_CTRL; - - tmp32 &= ~(ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK); - - if (config->enable12MHzClk) - { - tmp32 |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK; - } - if (config->enable96MHzClk) - { - tmp32 |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; - } - - base->FRO192M_CTRL |= tmp32; -} - -/*! - * brief Gets the default configuration of FRO192M. - * The default values are: - * code - config->enable12MHzClk = true; - config->enable96MHzClk = false; - endcode - * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure. - */ -void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enable12MHzClk = true; - config->enable96MHzClk = false; -} - -/*! - * brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU - * system, and so on. - * - * param base ANACTRL peripheral base address. - * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure. - */ -void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32 = base->XO32M_CTRL; - - tmp32 &= ~(ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK | ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK); - - /* Set XO32M CTRL. */ -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) - tmp32 &= ~ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; - if (config->enablePllUsbOutput) - { - tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; - } -#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ - - if (config->enableACBufferBypass) - { - tmp32 |= ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; - } - - if (config->enableSysCLkOutput) - { - tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; - } - base->XO32M_CTRL = tmp32; - -#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) - if (config->enableADCOutput) - { - base->DUMMY_CTRL |= ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK; - } - else - { - base->DUMMY_CTRL &= ~ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK; - } -#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ -} - -/*! - * brief Gets the default configuration of XO32M. - * The default values are: - * code - config->enableSysCLkOutput = false; - config->enableACBufferBypass = false; - endcode - * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure. - */ -void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) - config->enablePllUsbOutput = false; -#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ - config->enableSysCLkOutput = false; - config->enableACBufferBypass = false; -#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) - config->enableADCOutput = true; -#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ -} - -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) -/*! - * brief Measures the frequency of the target clock source. - * - * This function measures target frequency according to a accurate reference frequency.The formula is: - * Ftarget = (CAPVAL * Freference) / ((1<= 2U); - - uint32_t targetClkFreq = 0U; - uint32_t capval = 0U; - - /* Init a measurement cycle. */ - base->FREQ_ME_CTRL = ANACTRL_FREQ_ME_CTRL_PROG_MASK + ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(scale); - while (ANACTRL_FREQ_ME_CTRL_PROG_MASK == (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_PROG_MASK)) - { - } - - /* Calculate the target clock frequency. */ - capval = (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK); - targetClkFreq = (capval * refClkFreq) / ((1UL << scale) - 1UL); - - return targetClkFreq; -} -#endif /* FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_anactrl.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_anactrl.h deleted file mode 100644 index 4ca845b5a9a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_anactrl.h +++ /dev/null @@ -1,377 +0,0 @@ -/* - * Copyright 2018-2021, NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __FSL_ANACTRL_H__ -#define __FSL_ANACTRL_H__ - -#include "fsl_common.h" - -/*! - * @addtogroup anactrl - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief ANACTRL driver version. */ -#define FSL_ANACTRL_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*!< Version 2.3.0. */` - -/*! - * @brief ANACTRL interrupt flags - */ -enum _anactrl_interrupt_flags -{ -#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) - kANACTRL_BodVDDMainFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_MASK, /*!< BOD VDDMAIN Interrupt status - before Interrupt Enable. */ - kANACTRL_BodVDDMainInterruptFlag = - ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_MASK, /*!< BOD VDDMAIN Interrupt status - after Interrupt Enable. */ - kANACTRL_BodVDDMainPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_MASK, /*!< Current value of BOD VDDMAIN - power status output. */ -#else - kANACTRL_BodVbatFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK, /*!< BOD VBAT Interrupt status before - Interrupt Enable. */ - kANACTRL_BodVbatInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK, /*!< BOD VBAT Interrupt status - after Interrupt Enable. */ - kANACTRL_BodVbatPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK, /*!< Current value of BOD VBAT power - status output. */ -#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */ - kANACTRL_BodCoreFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK, /*!< BOD CORE Interrupt status before - Interrupt Enable. */ - kANACTRL_BodCoreInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK, /*!< BOD CORE Interrupt status - after Interrupt Enable. */ - kANACTRL_BodCorePowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK, /*!< Current value of BOD CORE power - status output. */ - kANACTRL_DcdcFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK, /*!< DCDC Interrupt status before - Interrupt Enable. */ - kANACTRL_DcdcInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK, /*!< DCDC Interrupt status after - Interrupt Enable. */ - kANACTRL_DcdcPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK, /*!< Current value of DCDC power - status output. */ -}; - -/*! - * @brief ANACTRL interrupt control - */ -enum _anactrl_interrupt -{ -#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) - kANACTRL_BodVDDMainInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_MASK, /*!< BOD VDDMAIN - interrupt control. */ -#else - kANACTRL_BodVbatInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK, /*!< BOD VBAT interrupt - control. */ -#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */ - kANACTRL_BodCoreInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK, /*!< BOD CORE interrupt - control. */ - kANACTRL_DcdcInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK, /*!< DCDC interrupt control. */ -}; - -/*! - * @brief ANACTRL status flags - */ -enum _anactrl_flags -{ - kANACTRL_FlashPowerDownFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK, /*!< Flash power-down status. */ - kANACTRL_FlashInitErrorFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK, /*!< Flash initialization - error status. */ -}; - -/*! - * @brief ANACTRL FRO192M and XO32M status flags - */ -enum _anactrl_osc_flags -{ - kANACTRL_OutputClkValidFlag = ANACTRL_FRO192M_STATUS_CLK_VALID_MASK, /*!< Output clock valid signal. */ - kANACTRL_CCOThresholdVoltageFlag = ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK, /*!< CCO threshold voltage detector - output (signal vcco_ok). */ - kANACTRL_XO32MOutputReadyFlag = ANACTRL_XO32M_STATUS_XO_READY_MASK << 16U, /*!< Indicates XO out - frequency statibilty. */ -}; - -/*! - * @brief Configuration for FRO192M - * - * This structure holds the configuration settings for the on-chip high-speed Free Running Oscillator. To initialize - * this structure to reasonable defaults, call the ANACTRL_GetDefaultFro192MConfig() function and pass a - * pointer to your config structure instance. - */ -typedef struct _anactrl_fro192M_config -{ - bool enable12MHzClk; /*!< Enable 12MHz clock. */ - bool enable96MHzClk; /*!< Enable 96MHz clock. */ -} anactrl_fro192M_config_t; - -/*! - * @brief Configuration for XO32M - * - * This structure holds the configuration settings for the 32 MHz crystal oscillator. To initialize this - * structure to reasonable defaults, call the ANACTRL_GetDefaultXo32MConfig() function and pass a - * pointer to your config structure instance. - */ -typedef struct _anactrl_xo32M_config -{ - bool enableACBufferBypass; /*!< Enable XO AC buffer bypass in pll and top level. */ -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) - bool enablePllUsbOutput; /*!< Enable XO 32 MHz output to USB HS PLL. */ -#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ - bool enableSysCLkOutput; /*!< Enable XO 32 MHz output to CPU system, SCT, and CLKOUT */ -#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) - bool enableADCOutput; /*!< Enable High speed crystal oscillator output to ADC. */ -#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ -} anactrl_xo32M_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function. - * - * @param base ANACTRL peripheral base address. - */ -void ANACTRL_Init(ANACTRL_Type *base); - -/*! - * @brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function. - * - * @param base ANACTRL peripheral base address. - */ -void ANACTRL_Deinit(ANACTRL_Type *base); -/* @} */ - -/*! - * @name Set oscillators - * @{ - */ - -/*! - * @brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock - * output and enable/disable 96MHZ clock output. - * - * @param base ANACTRL peripheral base address. - * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure. - */ -void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config); - -/*! - * @brief Gets the default configuration of FRO192M. - * The default values are: - * @code - config->enable12MHzClk = true; - config->enable96MHzClk = false; - @endcode - * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure. - */ -void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config); - -/*! - * @brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU - * system, and so on. - * - * @param base ANACTRL peripheral base address. - * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure. - */ -void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config); - -/*! - * @brief Gets the default configuration of XO32M. - * The default values are: - * @code - config->enableSysCLkOutput = false; - config->enableACBufferBypass = false; - @endcode - * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure. - */ -void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config); - -/* @} */ - -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) -/*! - * @name Measure Frequency - * @{ - */ - -/*! - * @brief Measures the frequency of the target clock source. - * - * This function measures target frequency according to a accurate reference frequency.The formula is: - * Ftarget = (CAPVAL * Freference) / ((1<BOD_DCDC_INT_CTRL |= (0x15U & mask); -} - -/*! - * @brief Disables the ANACTRL interrupts. - * - * @param base ANACTRL peripheral base address. - * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration. - */ -static inline void ANACTRL_DisableInterrupts(ANACTRL_Type *base, uint32_t mask) -{ - base->BOD_DCDC_INT_CTRL &= ~(0x15U & mask); -} - -/*! - * @brief Clears the ANACTRL interrupts. - * - * @param base ANACTRL peripheral base address. - * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration. - */ -static inline void ANACTRL_ClearInterrupts(ANACTRL_Type *base, uint32_t mask) -{ - base->BOD_DCDC_INT_CTRL |= (uint32_t)(mask << 1UL); -} -/* @} */ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets ANACTRL status flags. - * - * This function gets Analog control status flags. The flags are returned as the logical - * OR value of the enumerators @ref _anactrl_flags. To check for a specific status, - * compare the return value with enumerators in the @ref _anactrl_flags. - * For example, to check whether the flash is in power down mode: - * @code - * if (kANACTRL_FlashPowerDownFlag & ANACTRL_ANACTRL_GetStatusFlags(ANACTRL)) - * { - * ... - * } - * @endcode - * - * @param base ANACTRL peripheral base address. - * @return ANACTRL status flags which are given in the enumerators in the @ref _anactrl_flags. - */ -static inline uint32_t ANACTRL_GetStatusFlags(ANACTRL_Type *base) -{ - return base->ANALOG_CTRL_STATUS; -} - -/*! - * @brief Gets ANACTRL oscillators status flags. - * - * This function gets Anactrl oscillators status flags. The flags are returned as the logical - * OR value of the enumerators @ref _anactrl_osc_flags. To check for a specific status, - * compare the return value with enumerators in the @ref _anactrl_osc_flags. - * For example, to check whether the FRO192M clock output is valid: - * @code - * if (kANACTRL_OutputClkValidFlag & ANACTRL_ANACTRL_GetOscStatusFlags(ANACTRL)) - * { - * ... - * } - * @endcode - * - * @param base ANACTRL peripheral base address. - * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags. - */ -static inline uint32_t ANACTRL_GetOscStatusFlags(ANACTRL_Type *base) -{ - return (base->FRO192M_STATUS & 0xFFU) | ((base->XO32M_STATUS & 0xFFU) << 16U); -} - -/*! - * @brief Gets ANACTRL interrupt status flags. - * - * This function gets Anactrl interrupt status flags. The flags are returned as the logical - * OR value of the enumerators @ref _anactrl_interrupt_flags. To check for a specific status, - * compare the return value with enumerators in the @ref _anactrl_interrupt_flags. - * For example, to check whether the VBAT voltage level is above the threshold: - * @code - * if (kANACTRL_BodVbatPowerFlag & ANACTRL_ANACTRL_GetInterruptStatusFlags(ANACTRL)) - * { - * ... - * } - * @endcode - * - * @param base ANACTRL peripheral base address. - * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags. - */ -static inline uint32_t ANACTRL_GetInterruptStatusFlags(ANACTRL_Type *base) -{ - return base->BOD_DCDC_INT_STATUS & 0x1FFU; -} -/* @} */ - -#if (defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) && (FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG == 1U)) -/*! - * @brief Aux_Bias Control Interfaces - * @{ - */ - -/*! - * @brief Enables/disabless 1V reference voltage buffer. - * - * @param base ANACTRL peripheral base address. - * @param enable Used to enable or disable 1V reference voltage buffer. - */ -static inline void ANACTRL_EnableVref1V(ANACTRL_Type *base, bool enable) -{ - if (enable) - { - base->AUX_BIAS |= ANACTRL_AUX_BIAS_VREF1VENABLE_MASK; - } - else - { - base->AUX_BIAS &= ~ANACTRL_AUX_BIAS_VREF1VENABLE_MASK; - } -} - -/* @} */ -#endif /* defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) */ - -#if defined(__cplusplus) -} -#endif - -/* @}*/ - -#endif /* __FSL_ANACTRL_H__ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_casper.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_casper.c deleted file mode 100644 index 97c2613fd16..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_casper.c +++ /dev/null @@ -1,3433 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_casper.h" -#include /* ceil TODO check if really need it */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.casper" -#endif - -/* Recoding length for the secure scalar multiplication: - * Use n=256 and w=4 --> compute ciel(384/3) = 86 + 1 digits - * Use n=384 and w=4 --> compute ciel(384/3) = 128 + 1 digits - * Use n=521 and w=4 --> compute ciel(521/3) = 174 + 1 digits - */ - -/*!< Recoding length for the secure scalar multiplication */ -enum _casper_ecc_recode_len -{ - kCASPER_ECC_P256_recode_len = 87u, - kCASPER_ECC_P384_recode_len = 129u, - kCASPER_ECC_P521_recode_len = 175u, -}; - -enum _casper_ecc_N_bitlen -{ - kCASPER_ECC_P256_N_bitlen = 256u, - kCASPER_ECC_P384_N_bitlen = 384u, - kCASPER_ECC_P521_N_bitlen = 576u, -}; - -enum _casper_ecc_N_wordlen -{ - kCASPER_ECC_P256_wordlen = 256U / 32U, - kCASPER_ECC_P384_wordlen = 384u / 32U, - kCASPER_ECC_P521_wordlen = 576u / 32U, -}; - -#if defined(__GNUC__) -/* Enforce O1 optimize level, specifically to remove strict-aliasing option. - (-fno-strict-aliasing is required for this driver). */ -#pragma GCC push_options -#pragma GCC optimize("-O1") -#endif - -#if (defined(__CC_ARM) || defined(__ARMCC_VERSION)) -/* Enforce optimization off for clang, specifically to remove strict-aliasing option. -(-fno-strict-aliasing is required for this driver). */ -#pragma clang optimize off -#endif - -/* CASPER driver allows usage of 256, 384 and 521 ECC */ -#define CASPER_MAX_ECC_SIZE_WORDLEN (576u / 32U) -#define CASPER_RECODE_LENGTH_MAX 175 - -#define CASPER_RAM_BASE_NS (FSL_FEATURE_CASPER_RAM_BASE_ADDRESS) - -#if defined(FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED) && FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED -#define CASPER_RAM_OFFSET (FSL_FEATURE_CASPER_RAM_OFFSET) -#define INTERLEAVE(addr) \ - (((((((addr) >> 2U) & 0x00000001U) << CASPER_RAM_OFFSET) + (((addr) >> 3U) << 2U) + ((addr)&0x00000003U)) & \ - 0xFFFFU) | \ - s_casperRamBase) -#define DEINTERLEAVE(addr) INTERLEAVE(addr) -#define GET_WORD(addr) (*((uint32_t *)DEINTERLEAVE((uint32_t)(addr)))) -#define GET_DWORD(addr) (((uint64_t)GET_WORD(addr)) | (((uint64_t)GET_WORD(((uint32_t)(addr)) + 4U)) << 32U)) -#define SET_WORD(addr, value) *((uint32_t *)INTERLEAVE((uint32_t)(addr))) = ((uint32_t)(value)) -#define SET_DWORD(addr, value) \ - do \ - { \ - SET_WORD(addr, (uint32_t)(value & 0xFFFFFFFFU)); \ - SET_WORD(((uint32_t)(addr)) + 4U, (uint32_t)((value & 0xFFFFFFFF00000000U) >> 32U)); \ - } while (false) - -/* memcopy is always word aligned */ -/* interleaved to interleaved - static void CASPER_MEMCPY_I2I(void *dst, const void *src, size_t siz) - */ -#define CASPER_MEMCPY_I2I(dst, src, siz) \ - \ - { \ - uint32_t *dst32 = (uint32_t *)(dst); \ - const uint32_t *src32 = (const uint32_t *)(const uint32_t *)(src); \ - uint32_t i; \ - for (i = 0U; i < (siz) / 4U; i++) \ - { \ - SET_WORD(&dst32[i], GET_WORD(&src32[i])); \ - } \ - } - -/* interleaved to non-interleaved - static void CASPER_MEMCPY_I2N(void *dst, const void *src, size_t siz) - */ -#define CASPER_MEMCPY_I2N(dst, src, siz) \ - \ - { \ - uint32_t *dst32 = (uint32_t *)(dst); \ - const uint32_t *src32 = (const uint32_t *)(const uint32_t *)(src); \ - uint32_t i; \ - for (i = 0U; i < (siz) / 4U; i++) \ - { \ - dst32[i] = GET_WORD(&src32[i]); \ - } \ - } - -/* non-interleaved to interleaved - static void CASPER_MEMCPY_N2I(void *dst, const void *src, size_t siz) - */ -#define CASPER_MEMCPY_N2I(dst, src, siz) \ - \ - { \ - volatile uint32_t *dst32 = (uint32_t *)(dst); \ - const uint32_t *src32 = (const uint32_t *)(const uint32_t *)(src); \ - uint32_t i; \ - for (i = 0U; i < (siz) / 4U; i++) \ - { \ - SET_WORD(&dst32[i], src32[i]); \ - } \ - } -#else -#define GET_WORD(addr) (*((uint32_t *)(uint32_t)(addr))) -#define GET_DWORD(addr) (*((uint64_t *)(addr))) -#define SET_WORD(addr, value) *((uint32_t *)(uint32_t)(addr)) = ((uint32_t)(value)) -#define SET_DWORD(addr, value) *((uint64_t *)(addr)) = ((uint64_t)(value)) - -#define CASPER_MEMCPY_I2I(dst, src, siz) (void)memcpy(dst, src, siz) -#define CASPER_MEMCPY_I2N(dst, src, siz) (void)memcpy(dst, src, siz) -#define CASPER_MEMCPY_N2I(dst, src, siz) (void)memcpy(dst, src, siz) -#endif - -#define WORK_BUFF_MUL4 (N_wordlen_max * 4 + 2) /* ! working buffer is 4xN_wordlen to allow in place math */ -#define N_bytelen (N_wordlen * 4U) /* for memory copy and the like */ -#define N_dwordlen (unsigned)(N_wordlen / 2U) - -#define PreZeroW(i, w_out) \ - for ((i) = 0U; (i) < N_wordlen; (i) += 4U) \ - { \ - SET_WORD(&(w_out)[(i) + 0U], 0U); \ - SET_WORD(&(w_out)[(i) + 1U], 0U); \ - SET_WORD(&(w_out)[(i) + 2U], 0U); \ - SET_WORD(&(w_out)[(i) + 3U], 0U); \ - } /* unrolled partly */ -#define PreZeroW2up(i, w_out) \ - for (i = N_wordlen; i <= N_wordlen * 2U; i += 4U) \ - { \ - SET_WORD(&w_out[i + 0U], 0U); \ - SET_WORD(&w_out[i + 1U], 0U); \ - SET_WORD(&w_out[i + 2U], 0U); \ - SET_WORD(&w_out[i + 3U], 0U); \ - } /* unrolled partly */ - -/* Macros for the ECC component in Casper */ - -/* CASPER memory layout for ECC */ - -#define CASPER_MEM ((uint32_t *)msg_ret) - -/* Currently these macros work on 32-bit platforms */ - -#define add(c1, c0, a, b) \ - \ - do \ - { \ - uint32_t _t; \ - _t = a + b; \ - c1 = (uint32_t)(_t < a); \ - c0 = _t; \ - \ - } while (false) - -#define add_cout(carry, c, a, b) add((carry), (c), (a), (b)) - -#define add_cout_cin(carryout, c, a, b, carryin) \ - do \ - { \ - uint64_t _t = (uint64_t)(a) + (b) + (carryin); \ - (c) = (uint32_t)_t; \ - (carryout) = (uint32_t)(_t >> 32); \ - } while (false) - -#define sub_borrowout(borrow, c, a, b) \ - do \ - { \ - uint32_t _b = (uint32_t)((b) > (a)); \ - (c) = (a) - (b); \ - (borrow) = _b; \ - } while (false) - -#define sub_borrowin_borrowout(borrowout, c, a, b, borrowin) \ - do \ - { \ - uint32_t _t, _borrow1, _borrow2; \ - sub_borrowout(_borrow1, _t, (a), (b)); \ - sub_borrowout(_borrow2, (c), _t, (borrowin)); \ - (borrowout) = _borrow1 + _borrow2; \ - } while (false) - -#define sub_borrowout_1(borrow, c, a) \ - do \ - { \ - uint32_t _b = 0; \ - c = a - b; \ - borrow = _b; \ - } while (false) - -#define sub_borrowin_borrowout_1(borrowout, c, a, borrowin) \ - do \ - { \ - uint32_t _t, _borrow1, _borrow2; \ - sub_borrowout_1(_borrow1, _t, a); \ - sub_borrowout(_borrow2, c, _t, borrowin); \ - borrowout = _borrow1 + _borrow2; \ - } while (false) - -/* 32 x 32 --> 64-bit multiplication - * (c1,c0) = a * b - */ -#define mul(c1, c0, a, b) \ - \ - do \ - { \ - uint64_t __m; \ - __m = (uint64_t)a * (uint64_t)b; \ - c0 = (uint32_t)__m; \ - c1 = (uint32_t)(__m >> (uint64_t)32); \ - \ - } while (false) - -/* Multiply-and-accumulate - * (c1,c0) = a*b+c0 - */ -#define muladd(c1, c0, a, b) \ - \ - do \ - { \ - uint32_t __ma = c0; \ - mul(c1, c0, a, b); \ - c0 = c0 + __ma; \ - c1 = c1 + (c0 < __ma); \ - \ - } while (0) - -/* Multiply-and-accumulate-accumulate - * (c1,c0) = a*b+c0+c1 - */ -#define muladdadd(c1, c0, a, b) \ - \ - do \ - { \ - uint32_t __maa0 = c0, __maa1 = c1; \ - mul(c1, c0, a, b); \ - c0 = c0 + __maa0; \ - c1 = c1 + (c0 < __maa0); \ - c0 = c0 + __maa1; \ - c1 = c1 + (c0 < __maa1); \ - \ - } while (0) - -#define square_casper(c, a) multiply_casper(c, a, a) -#define sub_casper(c, a, b) CASPER_montsub(c, a, b, &CASPER_MEM[(N_wordlen + 4U)]) -#define add_casper(c, a, b) CASPER_montadd(c, a, b, &CASPER_MEM[(N_wordlen + 4U)]) -#define mul2_casper(c, a) add_casper(c, a, a) -#define half(c, a, b) CASPER_half(c, a, b) -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* The model for this algo is that it can be implemented for a fixed size RSA key */ -/* for max speed. If this is made into a variable (to allow varying size), then */ -/* it will be slower by a bit. */ -/* The file is compiled with N_bitlen passed in as number of bits of the RSA key */ -/* #define N_bitlen 2048 */ -static size_t N_wordlen = 0U; /* ! number of words (e.g. 4096/32 is 128 words) */ - -static uint32_t s_casperRamBase = CASPER_RAM_BASE_NS; -static uint32_t *msg_ret = (uint32_t *)CASPER_RAM_BASE_NS; - -/* NISTp-256 = 2^256-2^224+2^192+2^96-1 */ -static uint32_t NISTp256[256 / 32u] = {0xffffffffU, 0xffffffffU, 0xffffffffU, 0x00000000, - 0x00000000, 0x00000000, 0x00000001, 0xffffffffU}; - -/* The cardinality of the curve E(F_p) */ -static uint32_t NISTp256_q[256 / 32u] = {0xfc632551U, 0xf3b9cac2U, 0xa7179e84U, 0xbce6faadU, - 0xffffffffU, 0xffffffffU, 0x00000000, 0xffffffffU}; - -/* R = 2^256 mod p, the value "1" in Montgomery form. */ -static uint32_t NISTr256[256 / 32u] = {0x00000001, 0x00000000, 0x00000000, 0xffffffffU, - 0xffffffffU, 0xffffffffU, 0xfffffffeU, 0x00000000}; - -static uint32_t Np256[2] = {1, 0}; - -/* NISTp-384 = 2^384 - 2^128 - 2^96 + 2^32 - 1 */ -static uint32_t NISTp384[384 / 32u] = {0xffffffffU, 0x00000000, 0x00000000, 0xffffffffU, 0xfffffffeU, 0xffffffffU, - 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU}; - -/* The cardinality of the curve E(F_p) */ -static uint32_t NISTp384_q[384 / 32u] = {0xccc52973U, 0xecec196aU, 0x48b0a77aU, 0x581a0db2U, 0xf4372ddfU, 0xc7634d81U, - 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU}; - -/* R = 2^256 mod p, the value "1" in Montgomery form. */ -static uint32_t NISTr384[384 / 32u] = {0x00000001, 0xffffffffU, 0xffffffffU, 0x00000000, 0x1, 0, 0, 0, 0, 0, 0, 0}; - -// -p^-1 mod 2^64 = 0x100000001 -static uint32_t Np384[2] = {1, 1}; - -/* NISTp-521 = 2^521 - 1 */ -static uint32_t NISTp521[576 / 32U] = {0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, - 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, - 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0x1ffU, 0}; - -/* The cardinality of the curve E(F_p) */ -static uint32_t NISTp521_q[576 / 32U] = {0x91386409U, 0xbb6fb71eU, 0x899c47aeU, 0x3bb5c9b8U, 0xf709a5d0U, 0x7fcc0148U, - 0xbf2f966bU, 0x51868783U, 0xfffffffaU, 0xffffffffU, 0xffffffffU, 0xffffffffU, - 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0x1ffU, 0}; - -/* R = 2^576 mod p, the value "1" in Montgomery form. */ -static uint32_t NISTr521[576 / 32U] = {0, 0x800000, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - -/* -p^-1 mod 2^64 = 1 */ -static uint32_t Np521[2] = {1, 0}; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/* Convert a projective point (X1 : Y1 : Z1) - * to the affine point (X3, Y3) = (X1/Z1^2,Y1/Z1^3) - * The memory of (X3, Y3) and (X1 : Y1 : Z1) should not overlap - */ -void Jac_toAffine(uint32_t *X3, uint32_t *Y3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1); - -/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2 : Y2 : Z2) - * where (X1: Y1: Z1) != (X2 : Y2 : Z2) - * (X3 : Y3: Z3) may be the same as one of the inputs. - */ -void Jac_addition(uint32_t *X3, - uint32_t *Y3, - uint32_t *Z3, - uint32_t *X1, - uint32_t *Y1, - uint32_t *Z1, - uint32_t *X2, - uint32_t *Y2, - uint32_t *Z2); - -/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2, Y2) - * where (X1: Y1: Z1) != (X2, Y2) - * (X3 : Y3: Z3) may not overlap with (X1: Y1: Z1). - * Source: 2004 Hankerson?Menezes?Vanstone, page 91. - */ -void Jac_add_affine( - uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *X2, uint32_t *Y2); - -/* Point doubling from: 2004 Hankerson?Menezes?Vanstone, page 91. - * Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X1 : Y1 : Z1) - * (X3 : Y3: Z3) may be the same as the input. - */ -void Jac_double(uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1); - -/* Constant time elliptic curve scalar multiplication. - * Source: https://eprint.iacr.org/2014/130.pdf - * when using w = 4. - * Computes (X3 : Y3 : Z3) = k * (X1, Y1) \in E(F_p) - * p is the prime used to define the finite field F_p - * q is the (prime) order of the curve - */ -void Jac_scalar_multiplication( - uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *k, uint32_t *p, uint32_t *q); - -/* Compute the double scalar multiplication - * (X3 : Y3 : Z3) = k1 * (X1, Y1) + k2 * (X2, Y2) - * Using Shamir's trick and precomputing 16 points. - * This code is *not* constant time since this is used - * for verification only. - */ -void double_scalar_multiplication(uint32_t *X3, - uint32_t *Y3, - uint32_t *Z3, - uint32_t *X1, - uint32_t *Y1, - uint32_t *k1, - uint32_t *X2, - uint32_t *Y2, - uint32_t *k2); - -/* Compute inversion modulo NIST-p384 using Fermats little theorem. - * Using c = a^(p-2) = a^(-1) mod p. - * This computes the modular inversion if all arithmetic is "regular" - * modular arithmetic or computes automatically the Montgomery inverse - * if all arithmetic is Montgomery arithmetic. - */ -static void invert_mod_p384(uint32_t *c, uint32_t *a); - -/* Modular inversion for NIST-P256 */ -static void invert_mod_p256(uint32_t *c, uint32_t *a); - -/* Modular inversion for NIST-P521 */ -static void invert_mod_p521(uint32_t *c, uint32_t *a); - -// A and C do not need to be in Casper memory -static void toMontgomery_ECC_P256(uint32_t *C, uint32_t *A); -static void toMontgomery_ECC_P384(uint32_t *C, uint32_t *A); -static void toMontgomery_ECC_P521(uint32_t *C, uint32_t *A); - -static void CASPER_montsub(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod); -static void CASPER_montadd(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod); - -/* Compute c = a/2 mod p where b is scratch space. */ -static void CASPER_half(uint32_t *c, uint32_t *a, uint32_t *b); - -void CASPER_MEMCPY(void *dst, const void *src, size_t siz); - -static void multiply_casper(uint32_t w_out[], const uint32_t a[], const uint32_t b[]); - -static uint8_t int8abs(int8_t v); - -/* Constant time select c = a if m = 0 or - * c = b if m = 1 - * a, b, c are n words - */ -static void casper_select(uint32_t *c, uint32_t *a, uint32_t *b, int m, int n); - -/* Dumb n-limb addition of c=a+b, return carry. */ -static uint32_t add_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n); - -#if 0 -/* Dumb n-limb addition of c=a+b, return carry. */ -static uint32_t add_n(uint32_t *c, uint32_t *a, uint32_t *b, int n); - -/* Dumb n-limb subtraction of c=a-b, return borrow. */ -static uint32_t sub_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n); -#endif - -/* Dumb n-limb subtraction of c=a-b, return borrow. */ -static uint32_t sub_n(uint32_t *c, uint32_t *a, uint32_t *b, int n); - -int RSA_SignatureToPlaintextFast(const unsigned signature[N_wordlen_max], - const unsigned exp_pubkey, - const unsigned pubkey[N_wordlen_max], - unsigned MsgRet[WORK_BUFF_MUL4]); - -int RSA_MontSignatureToPlaintextFast(const unsigned mont_signature[N_wordlen_max], - const unsigned exp_pubkey, - const unsigned pubkey[N_wordlen_max], - unsigned MsgRet[WORK_BUFF_MUL4]); - -void MultprecMultiply(unsigned w_out[], const unsigned u[], const unsigned v[]); - -void MultprecGenNp64(const unsigned *Nmod, unsigned *np64_ret); -void MultprecMontPrepareX(unsigned Xmont_out[], const unsigned x[], const unsigned Rp[], const unsigned Nmod[]); -void MultprecModulo(unsigned r_out[], const unsigned v[], int top); -void MultprecCiosMul( - unsigned w_out[], const unsigned a[], const unsigned b[], const unsigned Nmod[], const unsigned *Np); -void MultprecMontCalcRp(unsigned Rp[], const unsigned exp_pubkey, const unsigned Nmod[]); - -static void MultprecCiosMul_ct( - uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np); - -static void MultprecCiosMul521_ct( - uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np); - -static void shiftrightSysram(uint32_t *z, uint32_t *x, uint32_t c); -static void shiftright(uint32_t *z, uint32_t *x, uint32_t c); -static void shiftleft(uint32_t *z, uint32_t *x, uint32_t c); - -/******************************************************************************* - * Code - ******************************************************************************/ - -__STATIC_FORCEINLINE uint32_t CA_MK_OFF(const void *addr) -{ - return ((uint32_t)(const uint32_t *)addr - s_casperRamBase); -} - -#if 1 -__STATIC_FORCEINLINE void Accel_done(void) -{ - register uint32_t status; - do - { - status = CASPER->STATUS; - } while (0U == (status & CASPER_STATUS_DONE_MASK)); -} - -__STATIC_FORCEINLINE void Accel_SetABCD_Addr(uint32_t ab, uint32_t cd) -{ - CASPER->CTRL0 = ab | (cd << 16); /* CDoffset << 16 | ABoffset */ -} - -__STATIC_FORCEINLINE void Accel_crypto_mul(uint32_t ctrl1) -{ - CASPER->CTRL1 = ctrl1; -} -#else -#include "intrinsics.h" -#define Accel_done() \ - { \ - register uint32_t status; \ - do \ - { \ - status = CASPER_Rd32b(CASPER_CP_STATUS); \ - } while (0 == (status & CASPER_STATUS_DONE_MASK)); \ - } -#if 0 -__STATIC_FORCEINLINE void Accel_done(void) -{ - register uint32_t status; - do - { - status = CASPER->STATUS; - } while (0 == (status & CASPER_STATUS_DONE_MASK)); -} -#endif -#define Accel_SetABCD_Addr(ab, cd) CASPER_Wr32b((uint32_t)ab | ((uint32_t)cd << 16), CASPER_CP_CTRL0); -#define Accel_crypto_mul(ctrl1) CASPER_Wr32b((uint32_t)ctrl1, CASPER_CP_CTRL1); -#endif - -__STATIC_FORCEINLINE uint32_t Accel_IterOpcodeResaddr(uint32_t iter, uint32_t opcode, uint32_t resAddr) -{ - return CASPER_CTRL1_ITER(iter) | CASPER_CTRL1_MODE(opcode) | (resAddr << 16); -} - -void CASPER_MEMCPY(void *dst, const void *src, size_t siz) -{ - bool bdst = - ((((uint32_t)(uint32_t *)dst) | 0x10000000u) >= ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) && - (((uint32_t)(uint32_t *)dst) | 0x10000000u) < - ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) + 8u * 1024u); - - bool bsrc = ((((uint32_t)(const uint32_t *)src) | 0x10000000u) >= - ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) && - (((uint32_t)(const uint32_t *)src) | 0x10000000u) < - ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) + 8u * 1024u); - - if (bdst && bsrc) - { - CASPER_MEMCPY_I2I(dst, src, siz); - } - else if (bdst && !bsrc) - { - CASPER_MEMCPY_N2I(dst, src, siz); - } - else if (!bdst && bsrc) - { - CASPER_MEMCPY_I2N(dst, src, siz); - } - else - { - (void)memcpy(dst, src, siz); - } -} - -/* Constant time select c = a if m = 0 or - * c = b if m = 1 - * a, b, c are n words - */ -static void casper_select(uint32_t *c, uint32_t *a, uint32_t *b, int m, int n) -{ - uint32_t m1 = 0U - (uint32_t)m, m2 = ~m1; - int i; - - for (i = 0; i < n; i++) - { - SET_WORD(&c[i], (GET_WORD(&a[i]) & m2) | (GET_WORD(&b[i]) & m1)); - } -} - -/* Compute R`, which is R mod N. This is done using subtraction */ -/* R has 1 in N_wordlen, but we do not fill it in since borrowed. */ -/* Exp-pubkey only used to optimize for exp=3 */ -void MultprecMontCalcRp(unsigned Rp[], const unsigned exp_pubkey, const unsigned Nmod[]) -{ - uint32_t i; - - /* R is 2^n where n is 1 bit longer than Nmod, so 1 followed by 32 or 64 0 words for example */ - /* Note that Nmod's upper most bit has to be 1 by definition, so one subtract is enough. We */ - /* do not set the 1 since it is "borrowed" so no point */ - PreZeroW(i, Rp); - Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(Rp))); - Accel_done(); - /* final borrow cannot happen since we know we started with a larger number */ -} - -/* MultprecMultiply - multiple w=u*v (per Knuth) */ -/* w_out is 2x the size of u and v */ -void MultprecMultiply(unsigned w_out[], const unsigned u[], const unsigned v[]) -{ - uint32_t i, j; - - /* Knuth 4.3.1 - Algorithm M */ - /* Compute w = u * v */ - /* u and v are N bits long in 32 bit word form */ - /* w is 2*N bits long in 32 bit word form */ - /* Note: We just multiply in place */ - - /* Step 1. Fill w[t-1:0] with 0s, the upper half will be written as we go */ - PreZeroW(i, w_out); - - /* We do 1st pass NOSUM so we do not have to 0 output */ - Accel_SetABCD_Addr(CA_MK_OFF(&v[0]), CA_MK_OFF(u)); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpMul6464NoSum, CA_MK_OFF(&w_out[0]))); - Accel_done(); - /* Step 2. iterate over N words of v using j */ - for (j = 2U; j < N_wordlen; j += 2U) - { - /* Step 2b. Check for 0 on v word - skip if so since we 0ed already */ - /* Step 3. Iterate over N words of u using i - perform Multiply-accumulate */ - if (0U != (GET_WORD(&v[j])) || 0U != (GET_WORD(&v[j + 1U]))) - { - Accel_SetABCD_Addr(CA_MK_OFF(&v[j]), CA_MK_OFF(u)); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpMul6464Sum, CA_MK_OFF(&w_out[j]))); - Accel_done(); - } - } -} - -/* MultprecModulo performs divide to get remainer as needed for RSA */ -/* This performs (q,r) = u/v, but we do not keep q */ -/* r_out is module (remainder) and is 2*N */ -/* u is in r_out (1st N) at start (passed in) */ -/* v is N long */ -void MultprecModulo(unsigned r_out[], const unsigned v[], int top) -{ - uint64_t u64; /* use 64 bit math mixed with 32 bit */ - unsigned u32; /* allows us to work on U in 32 bit */ - unsigned u_n, ul16, uh16, *u_shft; /* u_shft is because r_out is u initially */ - unsigned vl16, vh16, v_Nm1; - unsigned q_hat, r_hat, q_over; - unsigned borrow, carry; - uint32_t i; - int j, tmp; - - /* Knuth 4.3.1 - Algorithm D */ - /* Compute q = u / v giving remainder r = u mod v */ - /* -- we only want r, so we build qhat but do not store the Qs */ - /* v is N long, with u,q,r 2N long because u is slowly replavced by r. */ - /* We normalize/unnormlize per Knuth in the buffer (not copied) */ - - /* Step 1. Normalize value so MSb is in v[n-1]. Remember that v is */ - /* the public key - to call it a 2048 bit number, they cannot have 0 */ - /* in the MSb (or it would be less than 2048 bits) and so we know we */ - /* are normalized already. Therefore, u is effectively shifted already. */ - /* For u, we have it in r_out. u[n] holds any overflow */ - /* Since divide on CM3/4 is 32/32=32, we break into 16 bit halves, but */ - /* multiply can be 32x32=64. */ - u_n = 0; - u_shft = r_out; /* u (shifted) is in r_out */ - - v_Nm1 = GET_WORD(&v[N_wordlen - 1U]); /* MSw of public key */ - vl16 = v_Nm1 & 0xFFFFU; /* lower 16 */ - vh16 = v_Nm1 >> 16; /* upper 16 */ - /* Step 2. Iterate j from m-n down to 0 (M selected per Knuth as 2*N) */ - for (j = top; j >= 0; j--) - { - /* Step 3. estimate q_hat as (U[j+n]*B + U[j+n-1]) / V[n-1] */ - /* Note: using subset of Knuth algo since v is 1/2 len of u (which is */ - /* from multiply or x^2 leading into this). */ - u32 = u_n; /* pickup u4u3u2, knowing u4 is 0 */ - u64 = ((uint64_t)u_n << 32) | GET_WORD(&u_shft[(uint32_t)j + N_wordlen - 1U]); - ul16 = (unsigned int)(u64 & 0xFFFFU); /* lower 16 */ - uh16 = (unsigned int)((u64 >> 16) & 0xFFFFU); /* upper 16 */ - - /* we see if even possible (u large enough relative to v) */ - if ((u32 - v_Nm1) <= u32) - { - u32 -= v_Nm1; - q_over = 1; /* overflow from the sub */ - } - else - { - q_over = 0; - } - /* q_hat = u32 / vh16 -- is the upper partial value */ - /* estimate; if too much, then back down by 1 or 2 */ - q_hat = u32 / vh16; - r_hat = u32 - (q_hat * vh16); - /* see if Q is more than 16 bits or remainder is too large (over div) */ - if ((q_hat == 0x10000U) || ((q_hat * vl16) > ((r_hat << 16) | uh16))) - { - /* too much - undo a division */ - q_hat--; - r_hat += vh16; - /* check if still too much */ - if ((r_hat < 0x10000U) && ((q_hat * vl16) > ((r_hat << 16) | uh16))) - { - q_hat--; /* yes, so undo a 2nd */ - } - } - - /* compose u3u2uh16, then sub q_hat*v if OK */ - u64 = (((uint64_t)u32 << 16) | uh16) - ((uint64_t)q_hat * v_Nm1); - if (0U != (u64 >> 48)) - { - /* no, so add v back */ - u32 = (unsigned)(u64 + v_Nm1); - q_hat--; - } - else - { - u32 = (unsigned)u64; - } - tmp = (int32_t)(uint32_t)(q_hat << 16); /* quotient upper part */ - - /* divide lower part: q = u2uh16ul16 / v. */ - /* estimate and add back if over divdied */ - q_hat = u32 / vh16; - r_hat = u32 - (q_hat * vh16); - if ((q_hat == 0x10000U) || ((q_hat * vl16) > ((r_hat << 16) | ul16))) - { - /* too much - undo a division */ - q_hat--; - r_hat += vh16; - /* check if still too much */ - if ((r_hat < 0x10000U) && ((q_hat * vl16) > ((r_hat << 16) | ul16))) - { - q_hat--; /* yes, so undo a 2nd */ - } - } - - /* compose u2uh16ul16, then sub q_hat*v if OK */ - u64 = (((uint64_t)u32 << 16) | ul16) - ((uint64_t)q_hat * v_Nm1); - if (0U != (u64 >> 48)) - { - /* no, so add v back */ - r_hat = (unsigned)(u64 + v_Nm1); - q_hat--; - } - else - { - r_hat = (unsigned)u64; - } - q_hat |= (unsigned)tmp; /* other half of the quotient */ - while ((q_over != 0U) || ((uint64_t)q_hat * GET_WORD(&v[N_wordlen - 2U])) > - ((1ULL << 32) * r_hat) + (uint64_t)GET_WORD(&u_shft[(uint32_t)j + N_wordlen - 2U])) - { /* if Qhat>b, then reduce to b-1, then adjust up Rhat */ - q_hat--; - r_hat += v_Nm1; - if (r_hat < v_Nm1) - { - break; /* no overflow */ - /* else repeat since Rhat >= b */ - } - } - - /* Step 4. Multiply and subtract. We know the amount, */ - /* so we do the schoolboy math. Have to do on */ - /* the large value. */ - if (q_hat != 0U) - { - borrow = 0; - for (i = 0; i < N_wordlen; i++) - { - u64 = (uint64_t)q_hat * GET_WORD(&v[i]) + borrow; - borrow = (unsigned)(u64 >> 32); - if (GET_WORD(&u_shft[i + (unsigned)j]) < (unsigned)u64) - { - borrow++; /* carry the overflow */ - } - SET_WORD(&u_shft[i + (unsigned)j], GET_WORD(&u_shft[i + (unsigned)j]) - (unsigned)u64); - } - u_n -= borrow; /* overflow from shift left does not fit otherwise */ - } - - /* Store 5. (update Q - we don't), and add back V to remainder if we over-subtracted */ - /* That restores remainder to correct (we could only be off by 1) */ - /* This should happen very rarely. */ - if (u_n != 0U) - { - carry = 0; - for (i = 0; i < N_wordlen; i++) - { - SET_WORD(&u_shft[i + (unsigned)j], GET_WORD(&u_shft[i + (unsigned)j]) + carry); - carry = (GET_WORD(&u_shft[i + (unsigned)j]) < carry) ? 1U : 0U; - SET_WORD(&u_shft[i + (unsigned)j], GET_WORD(&u_shft[i + (unsigned)j]) + GET_WORD(&v[i])); - if (GET_WORD(&u_shft[i + (unsigned)j]) < GET_WORD(&v[i])) - { - carry++; - } - } - } - u_n = GET_WORD( - &u_shft[(uint32_t)j + N_wordlen - 1U]); /* hold upper part of u to catch overflow (to borrow from) */ - } - /* low N bits of r are valid as remainder */ -} - -/* We convert X into a Mont form number. Note length of arrays: */ -/* x is N_wordlen, Nmod is N_wordlen */ -/* Rp is N_wordlen (it is R` which is R mod N) */ -/* Xmont_out is N_wordlen*2+1 */ -void MultprecMontPrepareX(unsigned Xmont_out[], const unsigned x[], const unsigned Rp[], const unsigned Nmod[]) -{ - MultprecMultiply(Xmont_out, x, Rp); - MultprecModulo(Xmont_out, Nmod, (int32_t)N_wordlen); -} - -void MultprecGenNp64(const unsigned *Nmod, unsigned *np64_ret) /* only pass the low order double word */ -{ - uint64_t nprime, Nmod_0; - Nmod_0 = GET_WORD(&Nmod[0]) | ((uint64_t)GET_WORD(&Nmod[1]) << 32); - -#define COMP_NPN_1 ((2U - Nmod_0 * nprime) * nprime) /* computes N`*N0=1 mod 2^P where P is the partial built up */ - nprime = (((2U + Nmod_0) & 4U) << 1) + Nmod_0; /* mod 2^4 */ - nprime = COMP_NPN_1; - nprime = COMP_NPN_1; - nprime = COMP_NPN_1; - nprime = COMP_NPN_1; - /* 8 multiplies of uint64_t */ - *((uint64_t *)(uintptr_t)np64_ret) = (~0ULL - nprime) + 1ULL; -} - -/* CIOS Multiply. This is the Coarse Integrated form where the values are */ -/* multiplied and reduced for each step of "i". This uses less memory and */ -/* is faster as a result. Note that this is used to square as well as mul, */ -/* so not as fast as pure squaring could be. */ -void MultprecCiosMul( - unsigned w_out[], const unsigned a[], const unsigned b[], const unsigned Nmod[], const unsigned *Np) -{ - int j; - uint32_t i; - uint64_t *m64 = (uint64_t *)(uintptr_t)&msg_ret[kCASPER_RamOffset_M64]; - uint64_t Np64; - uint64_t carry; - uint64_t *a64, *b64, *w64, *N64; - - Np64 = *(uint64_t *)(uintptr_t)Np; - - a64 = (uint64_t *)(uintptr_t)a; - b64 = (uint64_t *)(uintptr_t)b; - w64 = (uint64_t *)(uintptr_t)w_out; - N64 = (uint64_t *)(uintptr_t)Nmod; - - if (a != NULL) - { /* if !a, we are reducing only */ - PreZeroW(i, w_out); - } - SET_DWORD(&w64[N_dwordlen], 0ULL); - SET_DWORD(&w64[N_dwordlen + 1U], 0ULL); - /* with accelerator */ - - /* loop i and then reduce after each j round */ - for (i = 0; i < N_dwordlen; i++) - { - /* Step 3. Iterate over N words of u using i - perform Multiply-accumulate */ - /* push-pull: we do a*b and then separately m*n (reduce) */ - if (a != NULL) - { /* if mul&reduce vs. reduce only */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(&b64[i]), CA_MK_OFF(a64)); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); - Accel_done(); - /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ - /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ - /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ - /* w64[N_dwordlen+1] = g_carry; */ - carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); - SET_DWORD(&w64[N_dwordlen + 1U], carry); - } - SET_DWORD(&m64[0], GET_DWORD(&w64[0]) * Np64); /* prime for 1st; modulo a double-word */ - - /* we are reducing, so the 1st [0th] 64 bit value product is tossed, but we */ - /* need its carry. We let the accel do this separately - really need a mode to */ - /* do this "reduce" since it is natural */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(m64), CA_MK_OFF(&N64[0])); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(&w64[0]))); - Accel_done(); - carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); - - Accel_SetABCD_Addr(CA_MK_OFF(&w64[1]), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpCopy, CA_MK_OFF(&w64[0]))); - - Accel_done(); - SET_DWORD(&w64[N_dwordlen], (GET_DWORD(&w64[N_dwordlen + 1U]) + carry)); - } - - /* now check if need to subtract Nmod */ - if (0U != (GET_WORD(&w_out[N_wordlen]))) - { - j = 1; /* we have to subtract for sure if carry up */ - } - else - { - j = 0; - for (i = N_wordlen - 1U; i > 0U; i--) - { - if (GET_WORD(&w_out[i]) != GET_WORD(&Nmod[i])) - { - j = (int32_t)(GET_WORD(&w_out[i]) > GET_WORD(&Nmod[i])); /* if larger sub */ - break; /* we would remove the break if worrying about side channel */ - } - } - } - if (0 == j) - { - return; /* Is smaller than Nmod, so done. */ - } - Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(w_out))); - Accel_done(); - /* last borrow is OK since we know it could only be <2N and */ -} - -/* RSA_MontSignatureToPlaintextFast: */ -/* MsgRet[] = Message return buffer - must be large enough to hold input and output (4*N+2) */ -/* exp_pubkey = the "e" that the value is raised to. Usually 3 or 0x10001. */ -/* signature = N bitpos len long "message" to process in Montgomery form - so saving conversion (divide) */ -/* pubkey = N bitpos len long public key to process signature with */ -/* returns: 0 */ -/* */ -/* Algo: compute M = signaturen^e mod public_key */ -/* where M is original plaintext, signature is signed value */ -/* note: e is usually either 0x3 or 0x10001 */ -int RSA_MontSignatureToPlaintextFast(const unsigned mont_signature[N_wordlen_max], - const unsigned exp_pubkey, - const unsigned pubkey[N_wordlen_max], - unsigned MsgRet[WORK_BUFF_MUL4]) -{ - int bidx = 0; - int bitpos; - unsigned np64[2]; - - /* MsgRet working area: */ - /* 0..N = RESULT, starting with S` */ - /* N..N*2 = S` and then working BASE during math. */ - /* N*2..N*4+2 = temp working area for Mont mul */ - - /* 1. Copy sig into MsgRet so we have one working result buffer */ - CASPER_MEMCPY_I2I((uint32_t *)(uintptr_t)&MsgRet[kCASPER_RamOffset_Result], - (const uint32_t *)(uintptr_t)mont_signature, N_bytelen); - MultprecGenNp64(pubkey, np64); /* Generate N` from LSW of N (LSW being lowest 64b word) */ - bitpos = (int8_t)(uint8_t)(31U - __CLZ(exp_pubkey)); /* count of bits after the left most 1 */ - while (--bitpos >= 0) - { - /* This operates on: */ - /* result = 1; */ - /* base = signature */ - /* loop while exponent bits from MSb to LSb */ - /* if (exp bit is 1) */ - /* result = result * base */ - /* base = base^2 */ - /* Because the MSb of exp is always 1 by definition, we can invert this a bit: */ - /* base = signature` */ - /* result = base; equivalent to result = 1*base from 1st pass, but now square is needed 1st */ - /* loop while exponent bits from MSb-1 to LSb */ - /* base = base^2 */ - /* if (exp bit is 1) */ - /* result = result * base */ - /* This ends up doing the same thing but skips two wasteful steps of multiplying by 1 and */ - /* a final squaring never used. */ - /* */ - /* Next we have the problem that CIOS mul needs a separate dest buffer. So, we bounce */ - /* base between base and temp, and likewise for result. */ - MultprecCiosMul(&MsgRet[(bidx != 0) ? kCASPER_RamOffset_Base : kCASPER_RamOffset_TempBase], - &MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], - &MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], pubkey, np64); - if (0U != (exp_pubkey & (uint32_t)(uint8_t)(1U << (uint8_t)bitpos))) /* where e is 1 */ - { - /* result has result, so we need to work into other temp area */ - MultprecCiosMul(&MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], - &MsgRet[kCASPER_RamOffset_Result], - &MsgRet[(bidx != 0) ? kCASPER_RamOffset_Base : kCASPER_RamOffset_TempBase], pubkey, np64); - /* we have to copy back to result */ - - // CASPER_MEMCPY_I2I(&MsgRet[kCASPER_RamOffset_Result], - // &MsgRet[bidx ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], N_bytelen); - } - else - { - bidx = (int32_t)(uint32_t) ~(unsigned)bidx; - } - } - - CASPER_MEMCPY_I2I((uint32_t *)(uintptr_t)&MsgRet[kCASPER_RamOffset_Result], - (uint32_t *)(uintptr_t)&MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], - N_bytelen); - - /* final step is one more reduction to get back to normal form (ie. divide R out) */ - MultprecCiosMul(&MsgRet[kCASPER_RamOffset_Result], NULL, NULL, pubkey, np64); - return (0); /* always 0 */ -} - -/* RSA_SignatureToPlaintextFast: */ -/* MsgRet[] = Message return buffer - must be large enough to hold input and output (4*N+2) */ -/* exp_pubkey = the "e" that the value is raised to. Usually 3 or 0x10001. */ -/* signature = N bitpos len long "message" to process in normal form - so converted to Mont form */ -/* pubkey = N bitpos len long public key to process signature with */ -/* returns: 0 */ -/* */ -/* Algo: compute M = signaturen^e mod public_key */ -/* where M is original plaintext, signature is signed value */ -/* note: e is usually either 0x3 or 0x10001 */ -int RSA_SignatureToPlaintextFast(const unsigned signature[N_wordlen_max], - const unsigned exp_pubkey, - const unsigned pubkey[N_wordlen_max], - unsigned MsgRet[WORK_BUFF_MUL4]) -{ - /* MsgRet working area: */ - /* 0..N = RESULT, starting with S`; it is used for R` just during creation of S` */ - /* N..N*2 = S` and then working BASE during math. Note overflow beyond N*2 when making S` */ - /* N*2..N*4+2 = temp working area for Mont mul */ - - MultprecMontCalcRp(&MsgRet[kCASPER_RamOffset_Result], exp_pubkey, pubkey); /* calculate R` (=R mod N) */ - MultprecMontPrepareX(&MsgRet[kCASPER_RamOffset_Base], signature, &MsgRet[kCASPER_RamOffset_Result], - pubkey); /* X*R1` mod N */ - return (RSA_MontSignatureToPlaintextFast(&MsgRet[kCASPER_RamOffset_Base], exp_pubkey, pubkey, MsgRet)); -} - -/*! - * brief Performs modular exponentiation - (A^E) mod N. - * - * This function performs modular exponentiation. - * - * param base CASPER base address - * param signature first addend (in little endian format) - * param pubN modulus (in little endian format) - * param wordLen Size of pubN in bytes - * param pubE exponent - * param[out] plaintext Output array to store result of operation (in little endian format) - */ -void CASPER_ModExp( - CASPER_Type *base, const uint8_t *signature, const uint8_t *pubN, size_t wordLen, uint32_t pubE, uint8_t *plaintext) -{ -#define PK_LOC &msg_ret[kCASPER_RamOffset_Modulus] -#define SIG_LOC &msg_ret[(unsigned)kCASPER_RamOffset_Modulus + N_wordlen_max] - - N_wordlen = wordLen; /* set global variable for key length - used by RSA_SignatureToPlaintextFast() */ - CASPER_MEMCPY_N2I(PK_LOC, (const uint32_t *)(uintptr_t)pubN, N_bytelen); - CASPER_MEMCPY_N2I(SIG_LOC, (const uint32_t *)(uintptr_t)signature, N_bytelen); - (void)RSA_SignatureToPlaintextFast((const unsigned *)(uintptr_t)(SIG_LOC), pubE, - (const unsigned *)(uintptr_t)(PK_LOC), (unsigned int *)(uintptr_t)msg_ret); - - CASPER_MEMCPY_I2N((uint32_t *)(uintptr_t)plaintext, msg_ret, N_bytelen); -} - -/*! - * brief Enables clock and disables reset for CASPER peripheral. - * - * Enable clock and disable reset for CASPER. - * - * param base CASPER base address - */ -void CASPER_Init(CASPER_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(CASPER_CLOCKS) - CLOCK_EnableClock(kCLOCK_Casper); -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if defined(CASPER_RSTS) - RESET_PeripheralReset(kCASPER_RST_SHIFT_RSTn); -#endif -#if defined(FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE) && (FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE > 0) - /* Enable hardware interleaving to RAMX0 and RAMX1 for CASPER */ - SYSCON->CASPER_CTRL = SYSCON_CASPER_CTRL_INTERLEAVE(1); -#endif /* FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE */ - /* If Casper init is called with secure address, use secure addres also for accessing Casper RAM. */ - s_casperRamBase = (unsigned)CASPER_RAM_BASE_NS | ((uint32_t)base & 0x10000000u); - msg_ret = (uint32_t *)s_casperRamBase; -} - -/*! - * brief Disables clock for CASPER peripheral. - * - * Disable clock and enable reset. - * - * param base CASPER base address - */ -void CASPER_Deinit(CASPER_Type *base) -{ -#if defined(CASPER_RSTS) - RESET_SetPeripheralReset(kCASPER_RST_SHIFT_RSTn); -#endif -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(CASPER_CLOCKS) - CLOCK_DisableClock(kCLOCK_Casper); -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/* New ECC code which uses Casper. */ - -/* Set the prime modulus mod in Casper memory. - */ -void CASPER_ecc_init(casper_algo_t curve) -{ - uint32_t *mod; - - if (curve == kCASPER_ECC_P256) - { - N_wordlen = 256U / 32U; - mod = NISTp256; - } - - if (curve == kCASPER_ECC_P384) - { - N_wordlen = 384U / 32U; - mod = NISTp384; - } - - if (curve == kCASPER_ECC_P521) - { - N_wordlen = 576U / 32U; - mod = NISTp521; - } - - CASPER_MEMCPY(&CASPER_MEM[(N_wordlen + 4U)], mod, N_wordlen * sizeof(uint32_t)); - uint8_t a[((CASPER_MAX_ECC_SIZE_WORDLEN + 4U) - CASPER_MAX_ECC_SIZE_WORDLEN) * sizeof(uint32_t)] = {0}; - CASPER_MEMCPY(&CASPER_MEM[(N_wordlen + 4U) + N_wordlen], a, ((N_wordlen + 4U) - N_wordlen) * sizeof(uint32_t)); -} - -void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2) -{ - uint32_t a[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; - uint32_t b[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; - uint32_t c = 0; - CASPER_MEMCPY(a, op1, N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(b, op2, N_wordlen * sizeof(uint32_t)); - - do - { - uint32_t _i; - c = (a[0] ^ b[0]); - for (_i = 1; _i < N_wordlen; _i++) - { - c |= (a[_i] ^ b[_i]); - } - } while (false); - - *res = (int32_t)c; -} - -void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1) -{ - uint32_t a[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; - uint32_t c = 0; - CASPER_MEMCPY(a, op1, N_wordlen * sizeof(uint32_t)); - - do - { - uint32_t _i; - c = a[0]; - for (_i = 1; _i < N_wordlen; _i++) - { - c |= a[_i]; - } - } while (false); - - *res = (int32_t)c; -} - -void CASPER_ECC_SECP256R1_Mul( - CASPER_Type *base, uint32_t resX[8], uint32_t resY[8], uint32_t X[8], uint32_t Y[8], uint32_t scalar[8]) -{ - uint32_t X1[8] = {0}; - uint32_t Y1[8] = {0}; - toMontgomery_ECC_P256(X1, X); - toMontgomery_ECC_P256(Y1, Y); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - - Jac_scalar_multiplication( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - scalar, NISTp256, NISTp256_q); - - Jac_toAffine( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - - /* Montgomery to Normal */ - /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ - uint32_t one[(kCASPER_ECC_P256_wordlen + 4U)] = {0x0}; - one[0] = 0x1u; - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - one, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - - /* copy out to result */ - CASPER_MEMCPY( - resX, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - resY, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP256R1_MulAdd(CASPER_Type *base, - uint32_t resX[8], - uint32_t resY[8], - uint32_t X1[8], - uint32_t Y1[8], - uint32_t scalar1[8], - uint32_t X2[8], - uint32_t Y2[8], - uint32_t scalar2[8]) -{ - uint32_t zeroes[(kCASPER_ECC_P256_wordlen + 4U)] = {0}; - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - X2, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - Y2, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - - toMontgomery_ECC_P256( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - toMontgomery_ECC_P256( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - toMontgomery_ECC_P256( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - toMontgomery_ECC_P256( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); - double_scalar_multiplication( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - scalar1, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - scalar2); - - Jac_toAffine( - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - - uint32_t one[(kCASPER_ECC_P256_wordlen + 4U)] = {0x0}; - one[0] = 0x1u; - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - one, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - - CASPER_MEMCPY(resX, - (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(resY, - (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP384R1_Mul( - CASPER_Type *base, uint32_t resX[12], uint32_t resY[12], uint32_t X[12], uint32_t Y[12], uint32_t scalar[12]) -{ - uint32_t X1[12] = {0}; - uint32_t Y1[12] = {0}; - toMontgomery_ECC_P384(X1, X); - toMontgomery_ECC_P384(Y1, Y); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - - Jac_scalar_multiplication( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - scalar, NISTp384, NISTp384_q); - - Jac_toAffine( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - - /* Montgomery to Normal */ - /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ - uint32_t one[12] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - one, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - - /* copy out to result */ - CASPER_MEMCPY( - resX, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - resY, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base, - uint32_t resX[12], - uint32_t resY[12], - uint32_t X1[12], - uint32_t Y1[12], - uint32_t scalar1[12], - uint32_t X2[12], - uint32_t Y2[12], - uint32_t scalar2[12]) -{ - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - X2, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - Y2, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - - toMontgomery_ECC_P384( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - toMontgomery_ECC_P384( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - toMontgomery_ECC_P384( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - toMontgomery_ECC_P384( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - - double_scalar_multiplication( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - scalar1, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - scalar2); - - Jac_toAffine( - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - - uint32_t one[12] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - one, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - - CASPER_MEMCPY(resX, - (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + - 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(resY, - (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + - 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP521R1_Mul( - CASPER_Type *base, uint32_t resX[18], uint32_t resY[18], uint32_t X[18], uint32_t Y[18], uint32_t scalar[18]) -{ - uint32_t X1[18] = {0}; - uint32_t Y1[18] = {0}; - toMontgomery_ECC_P521(X1, X); - toMontgomery_ECC_P521(Y1, Y); - - CASPER_MEMCPY( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - - Jac_scalar_multiplication( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 7U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 8U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - scalar, NISTp521, NISTp521_q); - - Jac_toAffine( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 7U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 8U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - - /* Montgomery to Normal */ - /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ - uint32_t one[18] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; - CASPER_MEMCPY( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - one, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - - /* copy out to result */ - CASPER_MEMCPY( - resX, - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - resY, - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP521R1_MulAdd(CASPER_Type *base, - uint32_t resX[18], - uint32_t resY[18], - uint32_t X1[18], - uint32_t Y1[18], - uint32_t scalar1[18], - uint32_t X2[18], - uint32_t Y2[18], - uint32_t scalar2[18]) -{ - uint32_t zeroes[(kCASPER_ECC_P521_wordlen + 4U)] = {0}; - - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - X2, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - Y2, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - - toMontgomery_ECC_P521( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - toMontgomery_ECC_P521( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - toMontgomery_ECC_P521( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - toMontgomery_ECC_P521( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); - double_scalar_multiplication( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - scalar1, - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - scalar2); - - Jac_toAffine( - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - - uint32_t one[(kCASPER_ECC_P521_wordlen + 4U)] = {0x0}; - one[0] = 0x1u; - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - one, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + - 2U * ((uint32_t)(uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - - CASPER_MEMCPY( - resX, - (&CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - resY, - (&CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); -} - -// CIOS Multiply. This is the Coarse Integrated form where the values are -// multiplied and reduced for each step of "i". This uses less memory and -// is faster as a result. Note that this is used to square as well as mul, -// so not as fast as pure squaring could be. -static void MultprecCiosMul_ct( - uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np) -{ - uint32_t j; - uint64_t *m64 = (uint64_t *)(uintptr_t)&msg_ret[kCASPER_RamOffset_M64]; - uint64_t Np64; - uint64_t carry; - uint64_t *a64, *b64, *w64, *N64; - uint32_t *T1 = &CASPER_MEM[0], borrow; - - Np64 = *(uint64_t *)(uintptr_t)Np; - - a64 = (uint64_t *)(uintptr_t)a; - b64 = (uint64_t *)(uintptr_t)b; - w64 = (uint64_t *)(uintptr_t)w_out; - N64 = (uint64_t *)(uintptr_t)Nmod; - - if (a != NULL) - { /* if !a, we are reducing only */ - PreZeroW(j, w_out); - } - SET_DWORD(&w64[N_dwordlen], 0ULL); - SET_DWORD(&w64[N_dwordlen + 1U], 0ULL); - /* with accelerator */ - - /* loop j and then reduce after each j round */ - for (j = 0; j < N_dwordlen; j++) - { - /* Step 3. Iterate over N words of u using j - perform Multiply-accumulate */ - /* push-pull: we do a*b and then separately m*n (reduce) */ - if (a != NULL) - { /* if mul&reduce vs. reduce only */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(&b64[j]), CA_MK_OFF(a64)); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); - Accel_done(); - /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ - /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ - /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ - /* w64[N_dwordlen+1] = g_carry; */ - carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); - SET_DWORD(&w64[N_dwordlen + 1U], carry); - } - SET_DWORD(&m64[0], GET_DWORD(&w64[0]) * Np64); /* prime for 1st; modulo a double-word */ - - /* we are reducing, so the 1st [0th] 64 bit value product is tossed, but we */ - /* need its carry. We let the accel do this separately - really need a mode to */ - /* do this "reduce" since it is natural */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(m64), CA_MK_OFF(&N64[0])); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(&w64[0]))); - Accel_done(); - carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); - - Accel_SetABCD_Addr(CA_MK_OFF(&w64[1]), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpCopy, CA_MK_OFF(&w64[0]))); - - Accel_done(); - SET_DWORD(&w64[N_dwordlen], (GET_DWORD(&w64[N_dwordlen + 1U]) + carry)); - } - - /* now check if need to subtract Nmod */ - CASPER_MEMCPY_I2I(T1, w_out, (N_wordlen + 1U) * sizeof(uint32_t)); - - /* Compute w = w - N */ - Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(w_out))); - Accel_done(); - - // if w_out > T1 then there was a borrow - borrow = (uint32_t)(GET_WORD(&((uint32_t *)w_out)[N_wordlen]) > GET_WORD(&T1[N_wordlen])); - - SET_WORD(&w_out[N_wordlen + 1U], 0); - SET_WORD(&w_out[N_wordlen], 0); - casper_select(w_out, w_out, T1, (int32_t)borrow, (int16_t)(uint16_t)N_wordlen); -} - -/* Compute C = A - B % mod - * Assumes all operand have two extra limbs to store carry. - */ -static void CASPER_montsub(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod) -{ - uint64_t *b64, *c64, *m64, *tmp; - int borrow; - - b64 = (uint64_t *)(uintptr_t)B; - c64 = (uint64_t *)(uintptr_t)C; - m64 = (uint64_t *)(uintptr_t)mod; - - tmp = (uint64_t *)(uintptr_t)&CASPER_MEM[0]; - - CASPER_MEMCPY(tmp, A, N_wordlen * sizeof(uint32_t)); - - /* Compute tmp = A - B. */ - Accel_SetABCD_Addr(CA_MK_OFF(b64), 0); - - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(tmp))); - Accel_done(); - - borrow = (int32_t)((GET_WORD(&((uint32_t *)(uintptr_t)tmp)[N_wordlen - 1U])) > GET_WORD(&A[N_wordlen - 1U])); - CASPER_MEMCPY(c64, tmp, N_wordlen * sizeof(uint32_t)); - - /* Compute C = Mod + tmp */ - Accel_SetABCD_Addr(CA_MK_OFF(m64), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpAdd64, CA_MK_OFF(c64))); - Accel_done(); - - casper_select(C, (uint32_t *)(uintptr_t)tmp, C, borrow, (int16_t)(uint16_t)N_wordlen); -} - -/* Compute C = A + B % mod - * Assumes all operand have two extra limbs to store carry. - */ -static void CASPER_montadd(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod) -{ - uint64_t *b64, *c64, *m64, *tmp; - int borrow; - - b64 = (uint64_t *)(uintptr_t)B; - c64 = (uint64_t *)(uintptr_t)C; - m64 = (uint64_t *)(uintptr_t)mod; - - tmp = (uint64_t *)(uintptr_t)&CASPER_MEM[0]; - - CASPER_MEMCPY(tmp, A, N_wordlen * sizeof(uint32_t)); - SET_DWORD(&tmp[N_wordlen / 2U], 0ULL); - SET_DWORD(&b64[N_wordlen / 2U], 0ULL); - SET_DWORD(&m64[N_wordlen / 2U], 0ULL); - - /* Compute tmp = A + B using one additonal double-length limb. */ - Accel_SetABCD_Addr(CA_MK_OFF(b64), 0); - - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U, (uint32_t)kCASPER_OpAdd64, CA_MK_OFF(tmp))); - Accel_done(); - - CASPER_MEMCPY(c64, tmp, (N_wordlen + 2U) * sizeof(uint32_t)); - - /* Compute C = Mod - tmp */ - Accel_SetABCD_Addr(CA_MK_OFF(m64), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(c64))); - Accel_done(); - - // borrow = g_carry; - borrow = (int32_t)(GET_WORD(&C[N_wordlen]) > GET_WORD(&(((uint32_t *)(uintptr_t)tmp)[N_wordlen]))); - casper_select(C, C, (uint32_t *)(uintptr_t)tmp, borrow, (int16_t)(uint16_t)N_wordlen); -} - -/* Compute c = a/2 mod p where b is scratch space. */ -static void CASPER_half(uint32_t *c, uint32_t *a, uint32_t *b) -{ - shiftright(b, a, 1U); /* Compute a/2 and (a+p)/2 */ - - /* Compute tmp = a + p using one additonal double-length limb. */ - CASPER_MEMCPY(c, a, N_wordlen * sizeof(uint32_t)); - SET_WORD(&c[N_wordlen], 0); - SET_WORD(&c[N_wordlen + 1U], 0U); - - Accel_SetABCD_Addr(CA_MK_OFF(((uint64_t *)(uintptr_t)&CASPER_MEM[(N_wordlen + 4U)])), 0); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_wordlen / 2U, (uint32_t)kCASPER_OpAdd64, CA_MK_OFF(((uint64_t *)(uintptr_t)c)))); - Accel_done(); - - shiftright(c, c, 1U); - SET_WORD(&c[N_wordlen - 1U], GET_WORD(&c[N_wordlen - 1U]) | (GET_WORD(&c[N_wordlen]) << 31)); - SET_WORD(&c[N_wordlen], 0U); - casper_select(c, b, c, (int32_t)(uint32_t)(GET_WORD(&a[0]) & 1U), (int16_t)(uint16_t)(N_wordlen)); -} - -static uint32_t casper_get_word(uint32_t *addr) -{ - return GET_WORD(addr); -} - -/* Shift right by 1 <= c <= 31. z[] and x[] in system RAM, no interleaving macros used. */ -static void shiftrightSysram(uint32_t *z, uint32_t *x, uint32_t c) -{ - z[0] = (x[1] << (32U - (c))) | (x[0] >> (c)); - z[1] = (x[2] << (32U - (c))) | (x[1] >> (c)); - z[2] = (x[3] << (32U - (c))) | (x[2] >> (c)); - z[3] = (x[4] << (32U - (c))) | (x[3] >> (c)); - z[4] = (x[5] << (32U - (c))) | (x[4] >> (c)); - z[5] = (x[6] << (32U - (c))) | (x[5] >> (c)); - z[6] = (x[7] << (32U - (c))) | (x[6] >> (c)); - - if (N_wordlen == 18U) - { - z[7] = (x[8] << (32U - (c))) | (x[7] >> (c)); - z[8] = (x[9] << (32U - (c))) | (x[8] >> (c)); - z[9] = (x[10] << (32U - (c))) | (x[9] >> (c)); - z[10] = (x[11] << (32U - (c))) | (x[10] >> (c)); - z[11] = (x[12] << (32U - (c))) | (x[11] >> (c)); - z[12] = (x[13] << (32U - (c))) | (x[12] >> (c)); - z[13] = (x[14] << (32U - (c))) | (x[13] >> (c)); - z[14] = (x[15] << (32U - (c))) | (x[14] >> (c)); - z[15] = (x[16] << (32U - (c))) | (x[15] >> (c)); - z[16] = (x[17] << (32U - (c))) | (x[16] >> (c)); - z[17] = (x[17] >> (c)); - } - - if (N_wordlen == 12U) - { - z[7] = (x[8] << (32U - (c))) | (x[7] >> (c)); - z[8] = (x[9] << (32U - (c))) | (x[8] >> (c)); - z[9] = (x[10] << (32U - (c))) | (x[9] >> (c)); - z[10] = (x[11] << (32U - (c))) | (x[10] >> (c)); - z[11] = (x[11] >> (c)); - } - if (N_wordlen == 8U) - { - z[7] = (x[7] >> (c)); - } -} -/* Shift right by 1 <= c <= 31. */ -static void shiftright(uint32_t *z, uint32_t *x, uint32_t c) -{ - SET_WORD(&z[0], (GET_WORD(&x[1]) << (32U - (c))) | (GET_WORD(&x[0]) >> (c))); - SET_WORD(&z[1], (GET_WORD(&x[2]) << (32U - (c))) | (GET_WORD(&x[1]) >> (c))); - SET_WORD(&z[2], (GET_WORD(&x[3]) << (32U - (c))) | (GET_WORD(&x[2]) >> (c))); - SET_WORD(&z[3], (GET_WORD(&x[4]) << (32U - (c))) | (GET_WORD(&x[3]) >> (c))); - SET_WORD(&z[4], (GET_WORD(&x[5]) << (32U - (c))) | (GET_WORD(&x[4]) >> (c))); - SET_WORD(&z[5], (GET_WORD(&x[6]) << (32U - (c))) | (GET_WORD(&x[5]) >> (c))); - SET_WORD(&z[6], (GET_WORD(&x[7]) << (32U - (c))) | (GET_WORD(&x[6]) >> (c))); - - if (N_wordlen == 18U) - { - SET_WORD(&z[7], (GET_WORD(&x[8]) << (32U - (c))) | (GET_WORD(&x[7]) >> (c))); - SET_WORD(&z[8], (GET_WORD(&x[9]) << (32U - (c))) | (GET_WORD(&x[8]) >> (c))); - SET_WORD(&z[9], (GET_WORD(&x[10]) << (32U - (c))) | (GET_WORD(&x[9]) >> (c))); - SET_WORD(&z[10], (GET_WORD(&x[11]) << (32U - (c))) | (GET_WORD(&x[10]) >> (c))); - SET_WORD(&z[11], (GET_WORD(&x[12]) << (32U - (c))) | (GET_WORD(&x[11]) >> (c))); - SET_WORD(&z[12], (GET_WORD(&x[13]) << (32U - (c))) | (GET_WORD(&x[12]) >> (c))); - SET_WORD(&z[13], (GET_WORD(&x[14]) << (32U - (c))) | (GET_WORD(&x[13]) >> (c))); - SET_WORD(&z[14], (GET_WORD(&x[15]) << (32U - (c))) | (GET_WORD(&x[14]) >> (c))); - SET_WORD(&z[15], (GET_WORD(&x[16]) << (32U - (c))) | (GET_WORD(&x[15]) >> (c))); - SET_WORD(&z[16], (GET_WORD(&x[17]) << (32U - (c))) | (GET_WORD(&x[16]) >> (c))); - SET_WORD(&z[17], (GET_WORD(&x[17]) >> (c))); - } - if (N_wordlen == 12U) - { - SET_WORD(&z[7], (GET_WORD(&x[8]) << (32U - (c))) | (GET_WORD(&x[7]) >> (c))); - SET_WORD(&z[8], (GET_WORD(&x[9]) << (32U - (c))) | (GET_WORD(&x[8]) >> (c))); - SET_WORD(&z[9], (GET_WORD(&x[10]) << (32U - (c))) | (GET_WORD(&x[9]) >> (c))); - SET_WORD(&z[10], (GET_WORD(&x[11]) << (32U - (c))) | (GET_WORD(&x[10]) >> (c))); - SET_WORD(&z[11], (GET_WORD(&x[11]) >> (c))); - } - if (N_wordlen == 8U) - { - SET_WORD((&z[7]), (GET_WORD(&x[7]) >> (c))); - } -} -/* Shift left by 1 <= c <= 31. */ -static void shiftleft(uint32_t *z, uint32_t *x, uint32_t c) -{ - if (N_wordlen == 18U) - { - SET_WORD(&z[17], (GET_WORD(&x[17]) << (c)) | GET_WORD(&z[16]) >> (32U - (c))); - SET_WORD(&z[16], (GET_WORD(&x[16]) << (c)) | GET_WORD(&z[15]) >> (32U - (c))); - SET_WORD(&z[15], (GET_WORD(&x[15]) << (c)) | GET_WORD(&z[14]) >> (32U - (c))); - SET_WORD(&z[14], (GET_WORD(&x[14]) << (c)) | GET_WORD(&z[13]) >> (32U - (c))); - SET_WORD(&z[13], (GET_WORD(&x[13]) << (c)) | GET_WORD(&z[12]) >> (32U - (c))); - SET_WORD(&z[12], (GET_WORD(&x[12]) << (c)) | GET_WORD(&z[11]) >> (32U - (c))); - SET_WORD(&z[11], (GET_WORD(&x[11]) << (c)) | GET_WORD(&z[10]) >> (32U - (c))); - SET_WORD(&z[10], (GET_WORD(&x[10]) << (c)) | GET_WORD(&z[9]) >> (32U - (c))); - SET_WORD(&z[9], (GET_WORD(&x[9]) << (c)) | GET_WORD(&z[8]) >> (32U - (c))); - SET_WORD(&z[8], (GET_WORD(&x[8]) << (c)) | GET_WORD(&z[7]) >> (32U - (c))); - } - if (N_wordlen == 12U) - { - SET_WORD(&z[11], (GET_WORD(&x[11]) << (c)) | GET_WORD(&z[10]) >> (32U - (c))); - SET_WORD(&z[10], (GET_WORD(&x[10]) << (c)) | GET_WORD(&z[9]) >> (32U - (c))); - SET_WORD(&z[9], (GET_WORD(&x[9]) << (c)) | GET_WORD(&z[8]) >> (32U - (c))); - SET_WORD(&z[8], (GET_WORD(&x[8]) << (c)) | GET_WORD(&z[7]) >> (32U - (c))); - } - SET_WORD(&z[7], (GET_WORD(&x[7]) << (c)) | GET_WORD(&z[6]) >> (32U - (c))); - SET_WORD(&z[6], (GET_WORD(&x[6]) << (c)) | GET_WORD(&z[5]) >> (32U - (c))); - SET_WORD(&z[5], (GET_WORD(&x[5]) << (c)) | GET_WORD(&z[4]) >> (32U - (c))); - SET_WORD(&z[4], (GET_WORD(&x[4]) << (c)) | GET_WORD(&z[3]) >> (32U - (c))); - SET_WORD(&z[3], (GET_WORD(&x[3]) << (c)) | GET_WORD(&z[2]) >> (32U - (c))); - SET_WORD(&z[2], (GET_WORD(&x[2]) << (c)) | GET_WORD(&z[1]) >> (32U - (c))); - SET_WORD(&z[1], (GET_WORD(&x[1]) << (c)) | GET_WORD(&z[0]) >> (32U - (c))); - SET_WORD(&z[0], (GET_WORD(&x[0]) << (c))); -} - -static void multiply_casper(uint32_t w_out[], const uint32_t a[], const uint32_t b[]) -{ - uint32_t *Np; - - if (N_wordlen == 8U) - { - Np = Np256; - MultprecCiosMul_ct(w_out, a, b, &CASPER_MEM[(N_wordlen + 4U)], Np); - } - if (N_wordlen == 12U) - { - Np = Np384; - MultprecCiosMul_ct(w_out, a, b, &CASPER_MEM[(N_wordlen + 4U)], Np); - } - - if (N_wordlen == 18U) - { - Np = Np521; - MultprecCiosMul521_ct(w_out, a, b, &CASPER_MEM[(N_wordlen + 4U)], Np); - } -} -/* Convert a projective point (X1 : Y1 : Z1) - * to the affine point (X3, Y3) = (X1/Z1^2,Y1/Z1^3) - * The memory of (X3, Y3) and (X1 : Y1 : Z1) should not overlap - */ -void Jac_toAffine(uint32_t *X3, uint32_t *Y3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1) -{ - uint32_t *T1, *T2; - - T1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; - T2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; - - square_casper(T1, Z1); // Z^2 - multiply_casper(T2, T1, Z1); // Z^3 - - // Montgomery inverse - if (N_wordlen == 8U) - { - invert_mod_p256(T1, T2); - } - - if (N_wordlen == 12U) - { - invert_mod_p384(T1, T2); - } - - if (N_wordlen == 18U) - { - invert_mod_p521(T1, T2); - } - - multiply_casper(Y3, Y1, T1); // Y3 = Y/Z^3 - multiply_casper(T2, T1, Z1); // Z^-2 - multiply_casper(X3, X1, T2); // X3 = X/Z^2 -} - -/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2 : Y2 : Z2) - * where (X1: Y1: Z1) != (X2 : Y2 : Z2) - * (X3 : Y3: Z3) may be the same as one of the inputs. - */ -void Jac_addition(uint32_t *X3, - uint32_t *Y3, - uint32_t *Z3, - uint32_t *X1, - uint32_t *Y1, - uint32_t *Z1, - uint32_t *X2, - uint32_t *Y2, - uint32_t *Z2) -{ - uint32_t *Z1Z1, *Z2Z2, *U1, *S1, *J, *H, *V, *t0, *t1; - int m1, m2; - - Z1Z1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; - Z2Z2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; - U1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 2U * (N_wordlen + 4U)]; - S1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 3U * (N_wordlen + 4U)]; - J = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 4U * (N_wordlen + 4U)]; - H = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 5U * (N_wordlen + 4U)]; - V = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 6U * (N_wordlen + 4U)]; - t0 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 7U * (N_wordlen + 4U)]; - t1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 8U * (N_wordlen + 4U)]; - - CASPER_ECC_equal_to_zero(&m1, Z1); - CASPER_ECC_equal_to_zero(&m2, Z2); - if (m1 == 0) - { - CASPER_MEMCPY(X3, X2, N_wordlen * 4U); - CASPER_MEMCPY(Y3, Y2, N_wordlen * 4U); - CASPER_MEMCPY(Z3, Z2, N_wordlen * 4U); - return; - } - if (m2 == 0) - { - CASPER_MEMCPY(X3, X1, N_wordlen * 4U); - CASPER_MEMCPY(Y3, Y1, N_wordlen * 4U); - CASPER_MEMCPY(Z3, Z1, N_wordlen * 4U); - return; - } - - square_casper(Z1Z1, Z1); - square_casper(Z2Z2, Z2); - multiply_casper(U1, X1, Z2Z2); - multiply_casper(H, X2, Z1Z1); /* if H equals U1 then X's are the same */ - multiply_casper(t0, Z2, Z2Z2); - multiply_casper(S1, Y1, t0); - multiply_casper(t0, Z1, Z1Z1); - multiply_casper(J, Y2, t0); /* if (S1 == J) then Y's are the same */ - - CASPER_ECC_equal(&m1, H, U1); /* If H and U1 match then the X-coordinates are the same. */ - CASPER_ECC_equal(&m2, S1, J); /* If S1 and J match then the Y-coordinates are the same. */ - if (m1 == 0) - { - if (m2 == 0) - { - Jac_double(X3, Y3, Z3, X1, Y1, Z1); - return; - } - /* else { - We work with the point at infinity. - The Z-coordinate will be set to zero in this function. - } */ - } - - sub_casper(H, H, U1); - mul2_casper(t0, H); - square_casper(t1, t0); - sub_casper(t0, J, S1); - multiply_casper(J, H, t1); - multiply_casper(V, U1, t1); - mul2_casper(U1, t0); - square_casper(t0, U1); - mul2_casper(t1, V); - sub_casper(t0, t0, J); - sub_casper(X3, t0, t1); - sub_casper(t0, V, X3); - multiply_casper(t1, S1, J); - mul2_casper(t1, t1); - multiply_casper(V, U1, t0); - sub_casper(Y3, V, t1); - add_casper(V, Z1, Z2); - square_casper(t1, V); - sub_casper(t1, t1, Z1Z1); - sub_casper(t1, t1, Z2Z2); - multiply_casper(Z3, t1, H); -} - -/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2, Y2) - * where (X1: Y1: Z1) != (X2, Y2) - * (X3 : Y3: Z3) may not overlap with (X1: Y1: Z1). - * Source: 2004 Hankerson?Menezes?Vanstone, page 91. - */ -void Jac_add_affine( - uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *X2, uint32_t *Y2) -{ - uint32_t *T1, *T2, *T3, *T4, *T5; - uint32_t *ONE = NULL; - int m1, m2; - - if (N_wordlen == 8U) - { - ONE = NISTr256; - } - if (N_wordlen == 12U) - { - ONE = NISTr384; - } - if (N_wordlen == 18U) - { - ONE = NISTr521; - } - - T1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; - T2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; - T3 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 2U * (N_wordlen + 4U)]; - T4 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 3U * (N_wordlen + 4U)]; - T5 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 4U * (N_wordlen + 4U)]; - - CASPER_ECC_equal_to_zero(&m1, Z1); - if (m1 == 0) - { - CASPER_MEMCPY(X3, X2, N_wordlen * 4U); - CASPER_MEMCPY(Y3, Y2, N_wordlen * 4U); - CASPER_MEMCPY(Z3, ONE, N_wordlen * 4U); - return; - } - - CASPER_MEMCPY(T5, Z1, N_wordlen * sizeof(uint32_t)); - square_casper(T3, Z1); - multiply_casper(T2, T3, Z1); - multiply_casper(T4, T3, X2); - multiply_casper(T3, T2, Y2); - - CASPER_ECC_equal(&m1, T4, X1); - CASPER_ECC_equal(&m2, T3, Y1); - if (m1 == 0) - { - if (m2 == 0) - { - Jac_double(X3, Y3, Z3, X1, Y1, Z1); - return; - } - /* else { - We work with the point at infinity. - The Z-coordinate will be set to zero in this function. - } */ - } - - sub_casper(T1, T4, X1); - sub_casper(T2, T3, Y1); - multiply_casper(Z3, T5, T1); - square_casper(T3, T1); - multiply_casper(T4, T3, T1); - multiply_casper(T5, T3, X1); - mul2_casper(T1, T5); - square_casper(X3, T2); - sub_casper(X3, X3, T1); - sub_casper(X3, X3, T4); - sub_casper(T3, T5, X3); - multiply_casper(T1, T3, T2); - multiply_casper(T2, T4, Y1); - sub_casper(Y3, T1, T2); -} - -static uint32_t casper_get_word(uint32_t *addr); - -/* Point doubling from: 2004 Hankerson?Menezes?Vanstone, page 91. - * Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X1 : Y1 : Z1) - * (X3 : Y3: Z3) may be the same as the input. - */ -void Jac_double(uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1) -{ - uint32_t *T1, *T2, *T3, *T4, *T5; - - T1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; - T2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; - T3 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 2U * (N_wordlen + 4U)]; - T4 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 3U * (N_wordlen + 4U)]; - T5 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 4U * (N_wordlen + 4U)]; - - square_casper(T1, Z1); - sub_casper(T3, X1, T1); - add_casper(T1, X1, T1); - multiply_casper(T4, T3, T1); - - mul2_casper(T3, T4); - - add_casper(T2, T3, T4); - - mul2_casper(Y3, Y1); - - CASPER_MEMCPY(T5, Z1, N_wordlen * sizeof(uint32_t)); - multiply_casper(Z3, Y3, T5); - - square_casper(T5, Y3); - - multiply_casper(T3, T5, X1); - - square_casper(Y3, T5); - - half(T5, Y3, T4); - - square_casper(X3, T2); - - mul2_casper(T1, T3); - - sub_casper(X3, X3, T1); - - sub_casper(T1, T3, X3); - - multiply_casper(T3, T1, T2); - - sub_casper(Y3, T3, T5); -} - -/* Recoding for a signed fixed window. - * Source: https://eprint.iacr.org/2014/130.pdf, Algorithm 6 - * Recode the n-bit integer k into ciel(log2(n)/(w-1)) digits - * where each digit is in - * { +/- 1, +/- 3, ..., +/- 2^(w-1)-1 } - * and put the result in c. - */ -static void recode(int8_t *c, uint32_t *k, int n, int w) -{ - int i, t; - uint32_t K[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; - (void)memcpy(K, k, (size_t)ceil(((double)n / 8.))); - t = (n + (w - 2)) / (w - 1); - for (i = 0; i < t; i++) - { - c[i] = (int8_t)(uint8_t)((K[0] & ((uint32_t)(uint32_t)(1UL << (uint32_t)w) - 1UL)) - - (uint32_t)(uint32_t)(1UL << ((uint32_t)w - 1UL))); - shiftrightSysram(K, K, (unsigned)w - 1U); - (void)add_n_1(K, K, (uint32_t)c[i] >> 31, (int16_t)(uint16_t)N_wordlen); - } - c[t] = (int8_t)K[0]; -} - -static uint32_t sub_n(uint32_t *c, uint32_t *a, uint32_t *b, int n) -{ - int i; - uint32_t borrow; - sub_borrowout(borrow, GET_WORD(&c[0]), a[0], GET_WORD(&b[0])); - for (i = 1; i < n; i++) - { - sub_borrowin_borrowout(borrow, GET_WORD(&c[i]), a[i], GET_WORD(&b[i]), borrow); - } - return borrow; -} - -#if 0 -/* Dumb n-limb subtraction of c=a-b, return borrow. */ -static uint32_t sub_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n) { - int i; - uint32_t borrow; - sub_borrowout(borrow, c[0], a[0], b); - for (i = 1; i < n; i++) { - sub_borrowin_borrowout_1(borrow, c[i], a[i], borrow); - } - return borrow; -} - -/* Dumb n-limb addition of c=a+b, return carry. */ -static uint32_t add_n(uint32_t *c, uint32_t *a, uint32_t *b, int n) { - int i; - uint32_t carry; - add_cout(carry, c[0], a[0], b[0]); - for (i = 1; i < n; i++) { - add_cout_cin(carry, c[i], a[i], b[i], carry); - } - return carry; -} -#endif - -/* Dumb n-limb addition of c=a+b, return carry. */ -static uint32_t add_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n) -{ - int i; - uint32_t carry; - add_cout(carry, c[0], a[0], b); - for (i = 1; i < n; i++) - { - add_cout_cin(carry, c[i], a[i], 0U, carry); - } - return carry; -} - -static uint8_t int8abs(int8_t v) -{ - return ((v < 0) ? ((uint8_t)-v) : ((uint8_t)v)); -} - -/* Constant time elliptic curve scalar multiplication. - * Source: https://eprint.iacr.org/2014/130.pdf - * when using w = 4. - * Computes (X3 : Y3 : Z3) = k * (X1, Y1) \in E(F_p) - * p is the prime used to define the finite field F_p - * q is the (prime) order of the curve - */ -void Jac_scalar_multiplication( - uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *k, uint32_t *p, uint32_t *q) -{ - uint32_t *scalar, *M, *X, *Y, *Z, *mem; - uint32_t *ONE = NULL; - int i, sign, odd; - uint8_t index; - size_t recodeLength = 175u; - size_t bitlen = 0u; - int8_t rec[CASPER_RECODE_LENGTH_MAX] = {0}; - - if (N_wordlen == 8U) - { - recodeLength = (size_t)kCASPER_ECC_P256_recode_len; - bitlen = (size_t)kCASPER_ECC_P256_N_bitlen; - ONE = NISTr256; - } - - if (N_wordlen == 12U) - { - recodeLength = (size_t)kCASPER_ECC_P384_recode_len; - bitlen = (size_t)kCASPER_ECC_P384_N_bitlen; - ONE = NISTr384; - } - - if (N_wordlen == 18U) - { - recodeLength = (size_t)kCASPER_ECC_P521_recode_len; - bitlen = (size_t)521U; - ONE = NISTr521; - } - - /* Point to the start of the LUT table space. */ - mem = &CASPER_MEM[(20U * N_wordlen + 80U)]; - - scalar = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * (N_wordlen + 4U)]; - X = &CASPER_MEM[(20U * N_wordlen + 80U) + 13U * (N_wordlen + 4U)]; - Y = &CASPER_MEM[(20U * N_wordlen + 80U) + 14U * (N_wordlen + 4U)]; - Z = &CASPER_MEM[(20U * N_wordlen + 80U) + 15U * (N_wordlen + 4U)]; - M = &CASPER_MEM[(20U * N_wordlen + 80U) + 16U * (N_wordlen + 4U)]; - - /* Point to memory the recoded scalar. - */ - CASPER_MEMCPY(scalar, k, sizeof(uint32_t) * N_wordlen); - -/* Precomputation: compute 1*P, 3*P, 5*P, and 7*P */ -#define FSL_CASPER_LUT(P, x) (mem + (3U * ((P)-1U) / 2U + (x)) * (N_wordlen + 4U)) - - /* Set 1*P */ - CASPER_MEMCPY(Z3, ONE, N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(FSL_CASPER_LUT(1U, 0U), X1, N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(FSL_CASPER_LUT(1U, 1U), Y1, N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(FSL_CASPER_LUT(1U, 2U), Z3, N_wordlen * sizeof(uint32_t)); - - /* Compute 2*P */ - Jac_double(X3, Y3, Z3, X1, Y1, Z3); - - /* Compute 3*P = 2P + P */ - Jac_add_affine(FSL_CASPER_LUT(3U, 0U), FSL_CASPER_LUT(3U, 1U), FSL_CASPER_LUT(3U, 2U), X3, Y3, Z3, X1, Y1); - - /* Compute 5*P = 3P + 2P */ - Jac_addition(FSL_CASPER_LUT(5U, 0U), FSL_CASPER_LUT(5U, 1U), FSL_CASPER_LUT(5U, 2U), FSL_CASPER_LUT(3U, 0U), - FSL_CASPER_LUT(3U, 1U), FSL_CASPER_LUT(3U, 2U), X3, Y3, Z3); - - /* Compute 7*P = 5P + 2P */ - Jac_addition(FSL_CASPER_LUT(7U, 0U), FSL_CASPER_LUT(7U, 1U), FSL_CASPER_LUT(7U, 2U), FSL_CASPER_LUT(5U, 0U), - FSL_CASPER_LUT(5U, 1U), FSL_CASPER_LUT(5U, 2U), X3, Y3, Z3); - - /* Recode the scalar */ - odd = (int32_t)((uint32_t)(casper_get_word(&scalar[0]) & 1U)); - (void)sub_n(M, q, scalar, (int16_t)(uint16_t)N_wordlen); // todo!!! - casper_select(scalar, M, scalar, odd, (int16_t)(uint16_t)N_wordlen); - - /* Use n=384 and w=4 --> compute ciel(384/3) = 128 + 1 digits */ - uint32_t scalarSysram[CASPER_MAX_ECC_SIZE_WORDLEN]; - CASPER_MEMCPY(scalarSysram, scalar, /*CASPER_*/ N_wordlen * sizeof(uint32_t)); - recode(rec, scalarSysram, (int32_t)bitlen, 4); - - /* Set the first value. */ - index = int8abs(rec[recodeLength - 1U]); - sign = (int32_t)(uint32_t)(uint8_t)(((uint8_t)rec[recodeLength - 1U]) >> 7); - - CASPER_MEMCPY(X3, FSL_CASPER_LUT((uint32_t)index, 0U), N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Y3, FSL_CASPER_LUT((uint32_t)index, 1U), N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Z3, FSL_CASPER_LUT((uint32_t)index, 2U), N_wordlen * sizeof(uint32_t)); - - /* Get the correct LUT element in constant time by touching - * all elements and masking out the correct one. - */ - -#define GET_LUT(x, y, z, index) \ - do \ - { \ - int m; \ - CASPER_MEMCPY((x), FSL_CASPER_LUT(1U, 0U), N_wordlen * sizeof(uint32_t)); \ - CASPER_MEMCPY((y), FSL_CASPER_LUT(1U, 1U), N_wordlen * sizeof(uint32_t)); \ - CASPER_MEMCPY((z), FSL_CASPER_LUT(1U, 2U), N_wordlen * sizeof(uint32_t)); \ - m = (int32_t)((index) == 3U); \ - casper_select((x), (x), FSL_CASPER_LUT(3U, 0U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((y), (y), FSL_CASPER_LUT(3U, 1U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((z), (z), FSL_CASPER_LUT(3U, 2U), m, (int16_t)(uint16_t)N_wordlen); \ - m = (int32_t)((index) == 5U); \ - casper_select((x), (x), FSL_CASPER_LUT(5U, 0U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((y), (y), FSL_CASPER_LUT(5U, 1U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((z), (z), FSL_CASPER_LUT(5U, 2U), m, (int16_t)(uint16_t)N_wordlen); \ - m = (int32_t)((index) == 7U); \ - casper_select((x), (x), FSL_CASPER_LUT(7U, 0U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((y), (y), FSL_CASPER_LUT(7U, 1U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((z), (z), FSL_CASPER_LUT(7U, 2U), m, (int16_t)(uint16_t)N_wordlen); \ - } while (false) - - GET_LUT(X3, Y3, Z3, index); - - /* Compute -y and select the positive or negative point. */ - (void)sub_n(M, p, Y3, (int16_t)(uint16_t)N_wordlen); // todo!!! - casper_select(Y3, Y3, M, sign, (int16_t)(uint16_t)N_wordlen); - - for (i = (int)(uint32_t)(recodeLength - 2U); i >= 0; i--) - { - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - - index = int8abs(rec[i]); - sign = (int32_t)(uint32_t)(uint8_t)(((uint8_t)rec[i]) >> 7); - - GET_LUT(X, Y, Z, index); - - /* Compute -y and select the positive or negative point. */ - (void)sub_n(scalar, p, Y, (int16_t)(uint16_t)N_wordlen); // todo!!! - casper_select(scalar, Y, scalar, sign, (int16_t)(uint16_t)N_wordlen); - - Jac_addition(X3, Y3, Z3, X3, Y3, Z3, X, scalar, Z); - } - - (void)sub_n(M, p, Y3, (int16_t)(uint16_t)N_wordlen); // todo!!! - - casper_select(Y3, M, Y3, odd, (int16_t)(uint16_t)N_wordlen); -} - -#undef FSL_CASPER_LUT -#undef GET_LUT - -/* - * Pre-compute the following 16 points: - * 00 00 = 0*P + 0*Q <-- Not needed when using sliding windows - * 00 01 = 0*P + 1*Q <-- Not needed when using sliding windows - * 00 10 = 0*P + 2*Q - * 00 11 = 0*P + 3*Q - * - * 01 00 = 1*P + 0*Q <-- Not needed when using sliding windows - * 01 01 = 1*P + 1*Q <-- Not needed when using sliding windows - * 01 10 = 1*P + 2*Q - * 01 11 = 1*P + 3*Q - * - * 10 00 = 2*P + 0*Q - * 10 01 = 2*P + 1*Q - * 10 10 = 2*P + 2*Q - * 10 11 = 2*P + 3*Q - * - * 11 00 = 3*P + 0*Q - * 11 01 = 3*P + 1*Q - * 11 10 = 3*P + 2*Q - * 11 11 = 3*P + 3*Q - * - * index = (bitsi||bitsj)-2 - (biti != 0)*2 - * - * Input: P = (X1 : Y1 : Z1) and - * Q = (X2 : Y2 : Z2) - * Output: mem, memory location for the LUT. - */ - -static void precompute_double_scalar_LUT16(uint32_t *Px, uint32_t *Py, uint32_t *Qx, uint32_t *Qy) -{ - uint32_t *Q2x, *Q2y, *Q2z, *P2x, *P2y, *P2z, *Z, *mem; - uint32_t *ONE = NULL; - uint32_t index = 0; - - if (N_wordlen == 8U) - { - ONE = NISTr256; - } - - if (N_wordlen == 12U) - { - ONE = NISTr384; - } - - Q2x = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 0U * (N_wordlen + 4U)]; - Q2y = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 1U * (N_wordlen + 4U)]; - Q2z = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 2U * (N_wordlen + 4U)]; - - /* Re-use memory from different scratch space since no - * projective point addition is used below. */ - P2x = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 5U * (N_wordlen + 4U)]; - P2z = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 6U * (N_wordlen + 4U)]; - P2y = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 7U * (N_wordlen + 4U)]; - Z = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 8U * (N_wordlen + 4U)]; - - mem = &CASPER_MEM[(20U * N_wordlen + 80U)]; - - CASPER_MEMCPY(Z, ONE, N_wordlen * sizeof(uint32_t)); - - // 00 10 = 0*P + 2*Q - Jac_double(Q2x, Q2y, Q2z, Qx, Qy, Z); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 00 11 = 0*P + 3*Q - Jac_add_affine(P2x, P2y, P2z, Q2x, Q2y, Q2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 01 10 = 1*P + 2*Q - Jac_add_affine(P2x, P2y, P2z, Q2x, Q2y, Q2z, Px, Py); - CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 01 11 = 1*P + 3*Q - Jac_add_affine(P2x, P2y, P2z, P2x, P2y, P2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 10 00 = 2*P + 0*Q - Jac_double(P2x, P2y, P2z, Px, Py, Z); - CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 10 01 = 2*P + 1*Q - Jac_add_affine(Q2x, Q2y, Q2z, P2x, P2y, P2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 10 10 = 2*P + 2*Q - Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 10 11 = 2*P + 3*Q - Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 11 00 = 3*P + 0*Q - Jac_add_affine(P2x, P2y, P2z, P2x, P2y, P2z, Px, Py); - CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 11 01 = 3*P + 1*Q - Jac_add_affine(Q2x, Q2y, Q2z, P2x, P2y, P2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 11 10 = 3*P + 2*Q - Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 11 11 = 3*P + 3*Q - Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; -} - -/* - * Pre-compute the following 4 points: - * 0 0 = 0*P + 0*Q <-- Not needed when using sliding windows - * 0 1 = 0*P + 1*Q - * - * 1 0 = 1*P + 0*Q - * 1 1 = 1*P + 1*Q - * - * index = (bitsj+1) & (0-bitsi) - * - * Input: P = (X1 : Y1 : Z1) and - * Q = (X2 : Y2 : Z2) - * Output: mem, memory location for the LUT. - */ - -static void precompute_double_scalar_LUT4(uint32_t *Px, uint32_t *Py, uint32_t *Qx, uint32_t *Qy) -{ - uint32_t *Z, *mem, *ONE; - uint32_t index = 0; - - ONE = NISTr521; - - /* Re-use memory from different scratch space since no - * projective point addition is used below. */ - Z = &CASPER_MEM[(11U * N_wordlen + 4U) + 5U * (N_wordlen + 4U)]; - mem = &CASPER_MEM[(20U * N_wordlen + 80U)]; - - CASPER_MEMCPY(Z, ONE, N_wordlen * sizeof(uint32_t)); - - // 0*P + 1*Q - CASPER_MEMCPY(&mem[index], Qx, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Qy, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 1*P + 0*Q - CASPER_MEMCPY(&mem[index], Px, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Py, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 1*P + 1*Q - Jac_add_affine(&mem[index], &mem[index + N_wordlen], &mem[index + 2U * N_wordlen], Px, Py, Z, Qx, Qy); -} - -#define GETLUTX(x) (3U * (x)*N_wordlen) -#define GETLUTY(x) (3U * (x)*N_wordlen + 1U * N_wordlen) -#define GETLUTZ(x) (3U * (x)*N_wordlen + 2U * N_wordlen) - -/* Compute the double scalar multiplication - * (X3 : Y3 : Z3) = k1 * (X1, Y1) + k2 * (X2, Y2) - * Using Shamir's trick and precomputing 16 points. - * This code is *not* constant time since this is used - * for verification only. - */ -void double_scalar_multiplication(uint32_t *X3, - uint32_t *Y3, - uint32_t *Z3, - uint32_t *X1, - uint32_t *Y1, - uint32_t *k1, - uint32_t *X2, - uint32_t *Y2, - uint32_t *k2) -{ - uint32_t index = 0, c = 0; - uint32_t *p1 = NULL, *p2 = NULL, x1, x2, *lut, *Tx = NULL, *Ty = NULL, *Tz = NULL; - size_t bitlen, shiftr, shiftl = 0u; - - if (N_wordlen == 8U) - { - bitlen = (size_t)kCASPER_ECC_P256_N_bitlen; - precompute_double_scalar_LUT16(X1, Y1, X2, Y2); - shiftr = 30U; - shiftl = 2U; - } - - if (N_wordlen == 12U) - { - bitlen = (size_t)kCASPER_ECC_P384_N_bitlen; - precompute_double_scalar_LUT16(X1, Y1, X2, Y2); - shiftr = 30U; - shiftl = 2U; - } - - if (N_wordlen == 18U) - { - bitlen = (size_t)kCASPER_ECC_P521_N_bitlen; - precompute_double_scalar_LUT4(X1, Y1, X2, Y2); - shiftr = 31U; - shiftl = 1U; - } - - lut = &CASPER_MEM[(20U * N_wordlen + 80U)]; - - if (N_wordlen == 8U || N_wordlen == 12U) - { - p1 = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen]; - p2 = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 1U * (N_wordlen + 4U)]; - - Tx = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 2U * (N_wordlen + 4U)]; - Ty = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 3U * (N_wordlen + 4U)]; - Tz = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 4U * (N_wordlen + 4U)]; - } - - if (N_wordlen == 18U) - { - p1 = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen]; - p2 = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 1U * (N_wordlen + 4U)]; - - Tx = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 2U * (N_wordlen + 4U)]; - Ty = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 3U * (N_wordlen + 4U)]; - Tz = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 4U * (N_wordlen + 4U)]; - } - - CASPER_MEMCPY(p1, k1, sizeof(uint32_t) * N_wordlen); - CASPER_MEMCPY(p2, k2, sizeof(uint32_t) * N_wordlen); - - /* Check if we can slide. */ - while (((casper_get_word(&p1[N_wordlen - 1U]) | casper_get_word(&p2[N_wordlen - 1U])) >> 31) == 0U && c < bitlen) - { - shiftleft(p1, p1, 1U); - shiftleft(p2, p2, 1U); - c++; - /* No doubling needed. */ - } - - /* Set the first value. */ - x1 = casper_get_word(&p1[N_wordlen - 1U]) >> shiftr; - x2 = casper_get_word(&p2[N_wordlen - 1U]) >> shiftr; - if (N_wordlen == 8U || N_wordlen == 12U) - { - index = (x2 | (x1 << 2)) - 2U - (uint32_t)(x1 != 0U) * 2U; - } - - if (N_wordlen == 18U) - { - index = (((x2) + 1U) & (0U - (x1))); - } - shiftleft(p1, p1, shiftl); - shiftleft(p2, p2, shiftl); - - CASPER_MEMCPY(X3, &lut[GETLUTX(index)], N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Y3, &lut[GETLUTY(index)], N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Z3, &lut[GETLUTZ(index)], N_wordlen * sizeof(uint32_t)); - c += shiftl; - - // todo: create an is_zero function - - while ((casper_get_word(&p1[0]) | casper_get_word(&p1[1]) | casper_get_word(&p1[2]) | casper_get_word(&p1[3]) | - casper_get_word(&p1[4]) | casper_get_word(&p1[5]) | casper_get_word(&p1[6]) | casper_get_word(&p1[7]) | - casper_get_word(&p1[8]) | casper_get_word(&p1[9]) | casper_get_word(&p1[10]) | casper_get_word(&p1[11]) | - casper_get_word(&p1[12]) | casper_get_word(&p1[13]) | casper_get_word(&p1[14]) | casper_get_word(&p1[15]) | - casper_get_word(&p1[16]) | casper_get_word(&p1[17]) | casper_get_word(&p2[0]) | casper_get_word(&p2[1]) | - casper_get_word(&p2[2]) | casper_get_word(&p2[3]) | casper_get_word(&p2[4]) | casper_get_word(&p2[5]) | - casper_get_word(&p2[6]) | casper_get_word(&p2[7]) | casper_get_word(&p2[8]) | casper_get_word(&p2[9]) | - casper_get_word(&p2[10]) | casper_get_word(&p2[11]) | casper_get_word(&p2[12]) | casper_get_word(&p2[13]) | - casper_get_word(&p2[14]) | casper_get_word(&p2[15]) | casper_get_word(&p2[16]) | - casper_get_word(&p2[17])) != 0U) - { - /* Check if we can slide. */ - while (((casper_get_word(&p1[N_wordlen - 1U]) | casper_get_word(&p2[N_wordlen - 1U])) >> 31) == 0U && - c < bitlen) - { - shiftleft(p1, p1, 1U); - shiftleft(p2, p2, 1U); - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - c++; - } - - if (c >= (bitlen - 1U)) - { - break; - } - - for (uint32_t i = 0; i < shiftl; i++) - { - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - } - - x1 = casper_get_word(&p1[N_wordlen - 1U]) >> shiftr; - x2 = casper_get_word(&p2[N_wordlen - 1U]) >> shiftr; - - if (N_wordlen == 8U || N_wordlen == 12U) - { - index = (x2 | (x1 << 2)) - 2U - (uint32_t)(x1 != 0U) * 2U; - } - - if (N_wordlen == 18U) - { - index = (((x2) + 1U) & (0U - (x1))); - } - - shiftleft(p1, p1, shiftl); - shiftleft(p2, p2, shiftl); - - CASPER_MEMCPY(Tx, &lut[GETLUTX(index)], N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Ty, &lut[GETLUTY(index)], N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Tz, &lut[GETLUTZ(index)], N_wordlen * sizeof(uint32_t)); - - Jac_addition(X3, Y3, Z3, X3, Y3, Z3, Tx, Ty, - Tz); //&lut[GETLUTX(index)], &lut[GETLUTY(index)], &lut[GETLUTZ(index)]); - c += shiftl; - } - - /* Special case in the end. */ - if (c == (bitlen - 1U)) - { - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - x1 = casper_get_word(&p1[N_wordlen - 1U]) >> 31; - x2 = casper_get_word(&p2[N_wordlen - 1U]) >> 31; - if (0U != x1) - { - Jac_add_affine(X3, Y3, Z3, X3, Y3, Z3, X1, Y1); - } - if (x2 != 0U) - { - Jac_add_affine(X3, Y3, Z3, X3, Y3, Z3, X2, Y2); - } - c++; - } - - while (c < bitlen) - { - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - c++; - } -} - -static void invert_mod_p256(uint32_t *c, uint32_t *a) -{ - int i; - uint32_t *t, *t2, *s1, *s2, *s4, *s8, *tmp; - - /* Assuming it is safe to use the ECC scratch size. */ - t = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - t2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - s1 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - s2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - s4 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - s8 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 7U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - tmp = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 8U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - - // t2 = n^(2^1)*n # 11 - square_casper(tmp, a); - multiply_casper(t2, tmp, a); - - // s1 = t2^(2^2)*t2 # F - square_casper(s1, t2); - square_casper(tmp, s1); - multiply_casper(s1, tmp, t2); - - // s2 = s1^(2^4)*s1 # FF - square_casper(s2, s1); - // for (i = 1; i < 4; i++) square(s2, s2); - square_casper(tmp, s2); - square_casper(s2, tmp); - square_casper(tmp, s2); - multiply_casper(s2, tmp, s1); - - // s4 = s2^(2^8)*s2 # FFFF - square_casper(s4, s2); - for (i = 1; i < 7; i += 2) - { - square_casper(tmp, s4); - square_casper(s4, tmp); - } - square_casper(tmp, s4); - multiply_casper(s4, tmp, s2); - - // s8 = s4^(2^16)*s4 # FFFFFFFF - square_casper(s8, s4); - for (i = 1; i < 15; i += 2) - { - square_casper(tmp, s8); - square_casper(s8, tmp); - } - square_casper(tmp, s8); - multiply_casper(s8, tmp, s4); - - // t = s8^(2^32)*n # ffffffff00000001 - square_casper(tmp, s8); - for (i = 1; i < 31; i += 2) - { - square_casper(t, tmp); - square_casper(tmp, t); - } - square_casper(t, tmp); - multiply_casper(tmp, t, a); - - // t = t^(2^128)*s8 # ffffffff00000001000000000000000000000000ffffffff - for (i = 0; i < 128; i += 2) - { - square_casper(t, tmp); - square_casper(tmp, t); - } - multiply_casper(t, tmp, s8); - - // t = t^(2^32)*s8 # ffffffff00000001000000000000000000000000ffffffffffffffff - for (i = 0; i < 32; i += 2) - { - square_casper(tmp, t); - square_casper(t, tmp); - } - multiply_casper(tmp, t, s8); - - // t = t^(2^16)*s4 # ffffffff00000001000000000000000000000000ffffffffffffffffffff - for (i = 0; i < 16; i += 2) - { - square_casper(t, tmp); - square_casper(tmp, t); - } - multiply_casper(t, tmp, s4); - - // t = t^(2^8)*s2 # ffffffff00000001000000000000000000000000ffffffffffffffffffffff - for (i = 0; i < 8; i += 2) - { - square_casper(tmp, t); - square_casper(t, tmp); - } - multiply_casper(tmp, t, s2); - - // t = t^(2^4)*s1 # ffffffff00000001000000000000000000000000fffffffffffffffffffffff - for (i = 0; i < 4; i += 2) - { - square_casper(t, tmp); - square_casper(tmp, t); - } - multiply_casper(t, tmp, s1); - - // t = t^(2^2)*t2 - square_casper(tmp, t); - square_casper(t, tmp); - multiply_casper(tmp, t, t2); - - // t = t^(2^2)*n # ffffffff00000001000000000000000000000000fffffffffffffffffffffffd - square_casper(t, tmp); - square_casper(tmp, t); - multiply_casper(c, tmp, a); -} - -// A and C do not need to be in Casper memory -static void toMontgomery_ECC_P256(uint32_t *C, uint32_t *A) -{ - /* R^2 = 2^512 mod p, used to convert values to Montgomery form. */ - uint32_t R2[kCASPER_ECC_P256_wordlen] = {0x00000003, 0x00000000, 0xffffffffU, 0xfffffffbU, - 0xfffffffeU, 0xffffffffU, 0xfffffffdU, 0x4}; - uint32_t *T1, *T2, *T3; - T1 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - T2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - T3 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - - CASPER_MEMCPY(T1, R2, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(T2, A, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - - multiply_casper(T3, T2, T1); - CASPER_MEMCPY(C, T3, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); -} - -/* Compute inversion modulo NIST-p384 using Fermats little theorem. - * Using c = a^(p-2) = a^(-1) mod p. - * This computes the modular inversion if all arithmetic is "regular" - * modular arithmetic or computes automatically the Montgomery inverse - * if all arithmetic is Montgomery arithmetic. - */ - -static void invert_mod_p384(uint32_t *c, uint32_t *a) -{ - int i; - uint32_t *e, *d, *tmp, *t0, *t1, *t2, *t3, *t4, *t5, *t6; // 10 residues needed - - /* Assuming it is safe to use the LUT scratch size. - * Hence, do not invert while elements in the LUT are needed. - */ - e = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - d = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - tmp = - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t0 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t1 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t4 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 7U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t5 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 8U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t6 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - - square_casper(tmp, a); // 2 - square_casper(t1, tmp); // 4 - square_casper(tmp, t1); // 8 - multiply_casper(t2, tmp, t1); // 12 - multiply_casper(d, a, t2); // 13 - multiply_casper(e, d, a); // 14 - multiply_casper(t0, e, a); // 15 - - // t1 = t0^(2^4)*t0 # ff - square_casper(tmp, t0); - square_casper(t1, tmp); - square_casper(tmp, t1); - square_casper(t2, tmp); - multiply_casper(t1, t2, t0); - - // t2 = t1^(2^8)*t1 # 4f - square_casper(tmp, t1); - for (i = 0; i < 3; i++) - { - square_casper(t3, tmp); - square_casper(tmp, t3); - } - square_casper(t3, tmp); - multiply_casper(t2, t3, t1); - - // t3 = t2^(2^16)*t2 # 8f - square_casper(tmp, t2); - for (i = 0; i < 7; i++) - { - square_casper(t4, tmp); - square_casper(tmp, t4); - } - square_casper(t4, tmp); - multiply_casper(t3, t4, t2); - - // t4 = t3^(2^32)*t3 # 16f - square_casper(tmp, t3); - for (i = 0; i < 15; i++) - { - square_casper(t5, tmp); - square_casper(tmp, t5); - } - square_casper(t5, tmp); - multiply_casper(t4, t5, t3); - - // t5 = t4^(2^64)*t4 # 32f - square_casper(tmp, t4); - for (i = 0; i < 31; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t4); - - // t5 = t5^(2^64)*t4 # 48f - square_casper(tmp, t5); - for (i = 0; i < 31; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t4); - - // t5 = t5^(2^32)*t3 # 56f - square_casper(tmp, t5); - for (i = 0; i < 15; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t3); - - // t5 = t5^(2^16)*t2 # 60f - square_casper(tmp, t5); - for (i = 0; i < 7; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t2); - - // t5 = t5^(2^8)*t1 # 62f - square_casper(tmp, t5); - for (i = 0; i < 3; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t1); - - // n = t5^(2^4)*t0 # 63f - square_casper(tmp, t5); - for (i = 0; i < 1; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t0); - - // n = n^(2^4)*e - square_casper(tmp, t5); - for (i = 0; i < 1; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, e); - - // n = n^(2^32)*t3 - square_casper(tmp, t5); - for (i = 0; i < 15; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t3); - - // n = n^(2^64) - square_casper(tmp, t5); - for (i = 0; i < 31; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t5, tmp); - - // n = n^(2^16)*t2 - square_casper(tmp, t5); - for (i = 0; i < 7; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t2); - - // n = n^(2^8)*t1 - square_casper(tmp, t5); - for (i = 0; i < 3; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t1); - - // n = n^(2^4)*t0 - square_casper(tmp, t5); - for (i = 0; i < 1; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t0); - - // n = n^(2^4)*d - square_casper(tmp, t5); - for (i = 0; i < 1; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(c, t6, d); -} - -// A and C do not need to be in Casper memory -static void toMontgomery_ECC_P384(uint32_t *C, uint32_t *A) -{ - /* R^2 = 2^768 mod p, used to convert values to Montgomery form. */ - uint32_t R2[kCASPER_ECC_P384_wordlen] = {0x00000001, 0xfffffffeU, 0x00000000, 0x00000002, 0x00000000, 0xfffffffeU, - 0x00000000, 0x00000002, 0x1, 0x0, 0x0, 0x0}; - uint32_t *T1, *T2, *T3; - T1 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - T2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U))) + - 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - T3 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U))) + - 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - - CASPER_MEMCPY(T1, R2, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(T2, A, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - - multiply_casper(T3, T2, T1); - CASPER_MEMCPY(C, T3, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); -} - -static void invert_mod_p521(uint32_t *c, uint32_t *a) -{ - int i; - uint32_t *e3, *d2, *d3, *d4, *T2, *T4; // 6 residues needed - - /* Assuming it is safe to use the LUT scratch size. - * Hence, do not invert while elements in the LUT are needed. - */ - e3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - d2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - d3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - d4 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - T2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - T4 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - - square_casper(d2, a); - multiply_casper(T2, d2, a); - - // d3 = 2^2 * T2 - square_casper(d3, T2); - square_casper(e3, d3); - multiply_casper(T4, e3, T2); - - // d3 = 2^4 * T4 - square_casper(d3, T4); - square_casper(e3, d3); - square_casper(d3, e3); - square_casper(e3, d3); - multiply_casper(d2, e3, T4); - - // d3 = 2^8 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - for (i = 0; i < 3; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d4, e3, d2); - - // d3 = 2^16 * d2 - square_casper(d3, d4); - square_casper(e3, d3); - for (i = 0; i < 7; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d2, e3, d4); - - // d3 = 2^32 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - for (i = 0; i < 15; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d4, e3, d2); - - // d3 = 2^64 * d2 - square_casper(d3, d4); - square_casper(e3, d3); - for (i = 0; i < 31; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d2, e3, d4); - - // d3 = 2^128 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - for (i = 0; i < 63; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d4, e3, d2); - - // d3 = 2^256 * d2 - square_casper(d3, d4); - square_casper(e3, d3); - for (i = 0; i < 127; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d2, e3, d4); - - // d3 = 2^2 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - multiply_casper(d2, e3, T2); - - // d3 = 2^4 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - square_casper(d3, e3); - square_casper(e3, d3); - multiply_casper(d2, e3, T4); - - square_casper(d3, d2); - multiply_casper(d2, d3, a); - - // d3 = 2 ^ 2 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - multiply_casper(c, e3, a); -} - -static void toMontgomery_ECC_P521(uint32_t *C, uint32_t *A) -{ - /* R^2 = 2^1088 mod p, used to convert values to Montgomery form. */ - // uint32_t R2[NUM_LIMBS] = { 0x00000000, 0x4000, 0, 0, - // 0, 0, 0, 0, - // 0, 0, 0, 0, - // 0 }; - /* R^2 = 2^1152 mod p, used to convert values to Montgomery form. */ - uint32_t R2[kCASPER_ECC_P521_wordlen] = {0, 0, 0, 0x4000, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - - uint32_t *T1, *T2, *T3; - T1 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - T2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - T3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - - CASPER_MEMCPY(T1, R2, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(T2, A, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - - multiply_casper(T3, T2, T1); - CASPER_MEMCPY(C, T3, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); -} - -static void MultprecCiosMul521_ct( - uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np) -{ - uint32_t j; - uint64_t carry; - uint64_t *a64, *b64, *w64; - - uint32_t *T1 = &CASPER_MEM[0], borrow; - - a64 = (uint64_t *)(uintptr_t)a; - b64 = (uint64_t *)(uintptr_t)b; - w64 = (uint64_t *)(uintptr_t)w_out; - - if (a != NULL) - { /* if !a, we are reducing only */ - PreZeroW(j, w_out); - } - SET_DWORD(&w64[N_dwordlen], 0ULL); - SET_DWORD(&w64[N_dwordlen + 1U], 0ULL); - /* with accelerator */ - - /* loop j and then reduce after each j round */ - for (j = 0; j < N_dwordlen; j++) - { - /* Step 3. Iterate over N words of u using j - perform Multiply-accumulate */ - /* push-pull: we do a*b and then separately m*n (reduce) */ - if (a != NULL) - { /* if mul&reduce vs. reduce only */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(&b64[j]), CA_MK_OFF(a64)); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); - Accel_done(); - /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ - /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ - /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ - /* w64[N_dwordlen+1] = g_carry; */ - carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); - SET_DWORD(&w64[N_dwordlen + 1U], carry); - } - - /* Fast reduction using only shifts for this special shape: - * (c - (-p^-1*c mod 2^64) * p)/2^64 = - * (c - c_0 * p)/2^64 = - * (\sum_{j=0}^9 c_i*2^64 - c_0 * p)/2^64 = - * (\sum_{j=0}^9 c_i*2^64 - c_0 * (2^521-1))/2^64 = - * (\sum_{j=0}^9 c_i*2^64 - c_0 * 2^521 - c_0)/2^64 = - * c_1 + c_2*2^64 + c_3*2^128 + c_4*2^192 + c_5*2^256 + c_6*2^320 + c_7*2^384 + c_8*2^448 + c_9*2^512 + c_0 * - * 2^{448 + 9} so one only needs to compute this 128-bit addition: [c_8, c_9] + c_0 * 2^9 - */ - - uint64_t *p64 = (uint64_t *)(uintptr_t)T1; - - /* p64[0] = w64[0] << 9;*/ - SET_DWORD(&p64[0], GET_DWORD(&w64[0]) << 9U); - /* p64[1] = w64[0] >> (64 - 9); */ - SET_DWORD(&p64[1], GET_DWORD(&w64[0]) >> (64 - 9)); - /* w64[0] = w64[1]; */ - SET_DWORD(&w64[0], GET_DWORD(&w64[1])); - /* w64[1] = w64[2]; */ - SET_DWORD(&w64[1], GET_DWORD(&w64[2])); - /* w64[2] = w64[3]; */ - SET_DWORD(&w64[2], GET_DWORD(&w64[3])); - /* w64[3] = w64[4]; */ - SET_DWORD(&w64[3], GET_DWORD(&w64[4])); - /* w64[4] = w64[5]; */ - SET_DWORD(&w64[4], GET_DWORD(&w64[5])); - /* w64[5] = w64[6]; */ - SET_DWORD(&w64[5], GET_DWORD(&w64[6])); - /* w64[6] = w64[7]; */ - SET_DWORD(&w64[6], GET_DWORD(&w64[7])); - - /* Compute p64 = p64 + {w64[8], w64[9]} using one additonal double-length limb, - * where p64 = w64[0] * 2^9. - */ - Accel_SetABCD_Addr(CA_MK_OFF(&w64[8]), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(2, (uint32_t)kCASPER_OpAdd64, /* kCASPER_OpAdd64, */ - CA_MK_OFF(p64))); - Accel_done(); - - /* w64[7] = p64[0]; */ - SET_DWORD(&w64[7], GET_DWORD(&p64[0])); - /* w64[8] = p64[1]; */ - SET_DWORD(&w64[8], GET_DWORD(&p64[1])); - /* w64[9] = 0; */ - SET_DWORD(&w64[9], (uint64_t)0U); - } - - /* memcpy(T1, w_out, (NUM_LIMBS + 1) * sizeof(uint32_t)); */ - /* now check if need to subtract Nmod */ - CASPER_MEMCPY_I2I(T1, w_out, (N_wordlen + 1U) * sizeof(uint32_t)); - - /* Compute w = w - N */ - Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(w_out))); - Accel_done(); - - /* if w_out > T1 then there was a borrow */ - /* borrow = (((uint32_t*)w_out)[NUM_LIMBS] > T1[NUM_LIMBS]); */ - borrow = (uint32_t)(GET_WORD(&((uint32_t *)w_out)[N_wordlen]) > GET_WORD(&T1[N_wordlen])); - SET_WORD(&w_out[N_wordlen + 1U], 0); - SET_WORD(&w_out[N_wordlen], 0); - /* w_out[NUM_LIMBS + 1] = 0; */ - /* w_out[NUM_LIMBS] = 0; */ - casper_select(w_out, w_out, T1, (int32_t)borrow, (int32_t)N_wordlen); -} - -#if defined(__GNUC__) -/* End of enforcing O1 optimize level for gcc*/ -#pragma GCC pop_options -#endif - -#if (defined(__CC_ARM) || defined(__ARMCC_VERSION)) -// End of enforcing optimize off for clang -#pragma clang optimize on -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_casper.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_casper.h deleted file mode 100644 index 328dc101116..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_casper.h +++ /dev/null @@ -1,386 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CASPER_H_ -#define _FSL_CASPER_H_ - -#include "fsl_common.h" - -/*! @file */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! - * @addtogroup casper_driver - * @{ - */ -/*! @name Driver version */ -/*@{*/ -/*! @brief CASPER driver version. Version 2.2.3. - * - * Current version: 2.2.3 - * - * Change log: - * - Version 2.0.0 - * - Initial version - * - Version 2.0.1 - * - Bug fix KPSDK-24531 double_scalar_multiplication() result may be all zeroes for some specific input - * - Version 2.0.2 - * - Bug fix KPSDK-25015 CASPER_MEMCPY hard-fault on LPC55xx when both source and destination buffers are outside of - * CASPER_RAM - * - Version 2.0.3 - * - Bug fix KPSDK-28107 RSUB, FILL and ZERO operations not implemented in enum _casper_operation. - * - Version 2.0.4 - * - For GCC compiler, enforce O1 optimize level, specifically to remove strict-aliasing option. - * This driver is very specific and requires -fno-strict-aliasing. - * - Version 2.0.5 - * - Fix sign-compare warning. - * - Version 2.0.6 - * - Fix IAR Pa082 warning. - * - Version 2.0.7 - * - Fix MISRA-C 2012 issue. - * - Version 2.0.8 - * - Add feature macro for CASPER_RAM_OFFSET. - * - Version 2.0.9 - * - Remove unused function Jac_oncurve(). - * - Fix ECC384 build. - * - Version 2.0.10 - * - Fix MISRA-C 2012 issue. - * - Version 2.1.0 - * - Add ECC NIST P-521 elliptic curve. - * - Version 2.2.0 - * - Rework driver to support multiple curves at once. - * - Version 2.2.1 - * - Fix MISRA-C 2012 issue. - * - Version 2.2.2 - * - Enable hardware interleaving to RAMX0 and RAMX1 for CASPER by feature macro FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE - * - Version 2.2.3 - * - Added macro into CASPER_Init and CASPER_Deinit to support devices without clock and reset control. - */ -#define FSL_CASPER_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) -/*@}*/ - -/*! @brief CASPER operation - * - */ -typedef enum _casper_operation -{ - kCASPER_OpMul6464NoSum = 0x01, /*! Walking 1 or more of J loop, doing r=a*b using 64x64=128*/ - kCASPER_OpMul6464Sum = - 0x02, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but assume inner j loop*/ - kCASPER_OpMul6464FullSum = - 0x03, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but sum all of w. */ - kCASPER_OpMul6464Reduce = - 0x04, /*! Walking 1 or more of J loop, doing c,r[-1]=r+a*b using 64x64=128, but skip 1st write*/ - kCASPER_OpAdd64 = 0x08, /*! Walking add with off_AB, and in/out off_RES doing c,r=r+a+c using 64+64=65*/ - kCASPER_OpSub64 = 0x09, /*! Walking subtract with off_AB, and in/out off_RES doing r=r-a using 64-64=64, with last - borrow implicit if any*/ - kCASPER_OpDouble64 = 0x0A, /*! Walking add to self with off_RES doing c,r=r+r+c using 64+64=65*/ - kCASPER_OpXor64 = 0x0B, /*! Walking XOR with off_AB, and in/out off_RES doing r=r^a using 64^64=64*/ - kCASPER_OpRSub64 = 0x0C, /*! Walking subtract with off_AB, and in/out off_RES using r=a-r */ - kCASPER_OpShiftLeft32 = - 0x10, /*! Walking shift left doing r1,r=(b*D)|r1, where D is 2^amt and is loaded by app (off_CD not used)*/ - kCASPER_OpShiftRight32 = 0x11, /*! Walking shift right doing r,r1=(b*D)|r1, where D is 2^(32-amt) and is loaded by - app (off_CD not used) and off_RES starts at MSW*/ - kCASPER_OpCopy = 0x14, /*! Copy from ABoff to resoff, 64b at a time*/ - kCASPER_OpRemask = 0x15, /*! Copy and mask from ABoff to resoff, 64b at a time*/ - kCASPER_OpFill = 0x16, /*! Fill RESOFF using 64 bits at a time with value in A and B */ - kCASPER_OpZero = 0x17, /*! Fill RESOFF using 64 bits at a time of 0s */ - kCASPER_OpCompare = 0x18, /*! Compare two arrays, running all the way to the end*/ - kCASPER_OpCompareFast = 0x19, /*! Compare two arrays, stopping on 1st !=*/ -} casper_operation_t; - -/*! @brief Algorithm used for CASPER operation */ -typedef enum _casper_algo_t -{ - kCASPER_ECC_P256 = 0x01, /*!< ECC_P256*/ - kCASPER_ECC_P384 = 0x02, /*!< ECC_P384 */ - kCASPER_ECC_P521 = 0x03, /*!< ECC_P521 */ -} casper_algo_t; - -#define CASPER_CP 1 -#define CASPER_CP_CTRL0 (0x0 >> 2) -#define CASPER_CP_CTRL1 (0x4 >> 2) -#define CASPER_CP_LOADER (0x8 >> 2) -#define CASPER_CP_STATUS (0xC >> 2) -#define CASPER_CP_INTENSET (0x10 >> 2) -#define CASPER_CP_INTENCLR (0x14 >> 2) -#define CASPER_CP_INTSTAT (0x18 >> 2) -#define CASPER_CP_AREG (0x20 >> 2) -#define CASPER_CP_BREG (0x24 >> 2) -#define CASPER_CP_CREG (0x28 >> 2) -#define CASPER_CP_DREG (0x2C >> 2) -#define CASPER_CP_RES0 (0x30 >> 2) -#define CASPER_CP_RES1 (0x34 >> 2) -#define CASPER_CP_RES2 (0x38 >> 2) -#define CASPER_CP_RES3 (0x3C >> 2) -#define CASPER_CP_MASK (0x60 >> 2) -#define CASPER_CP_REMASK (0x64 >> 2) -#define CASPER_CP_LOCK (0x80 >> 2) -#define CASPER_CP_ID (0xFFC >> 2) -/* mcr (cp, opc1, value, CRn, CRm, opc2) */ -#define CASPER_Wr32b(value, off) __arm_mcr(CASPER_CP, 0, value, ((off >> 4)), (off), 0) -/* mcrr(coproc, opc1, value, CRm) */ -#define CASPER_Wr64b(value, off) __arm_mcrr(CASPER_CP, 0, value, off) -/* mrc(coproc, opc1, CRn, CRm, opc2) */ -#define CASPER_Rd32b(off) __arm_mrc(CASPER_CP, 0, ((off >> 4)), (off), 0) - -/* The model for this algo is that it can be implemented for a fixed size RSA key */ -/* for max speed. If this is made into a variable (to allow varying size), then */ -/* it will be slower by a bit. */ -/* The file is compiled with N_bitlen passed in as number of bits of the RSA key */ -/* #define N_bitlen 2048 */ -#define N_wordlen_max (4096U / 32U) - -enum -{ - kCASPER_RamOffset_Result = 0x0u, - kCASPER_RamOffset_Base = (N_wordlen_max + 8u), - kCASPER_RamOffset_TempBase = (2u * N_wordlen_max + 16u), - kCASPER_RamOffset_Modulus = (kCASPER_RamOffset_TempBase + N_wordlen_max + 4u), - kCASPER_RamOffset_M64 = 1022U, -}; - -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup casper_driver - * @{ - */ - -/*! - * @brief Enables clock and disables reset for CASPER peripheral. - * - * Enable clock and disable reset for CASPER. - * - * @param base CASPER base address - */ -void CASPER_Init(CASPER_Type *base); - -/*! - * @brief Disables clock for CASPER peripheral. - * - * Disable clock and enable reset. - * - * @param base CASPER base address - */ -void CASPER_Deinit(CASPER_Type *base); - -/*! - *@} - */ /* end of casper_driver */ - -/******************************************************************************* - * PKHA API - ******************************************************************************/ - -/*! - * @addtogroup casper_driver_pkha - * @{ - */ - -/*! - * @brief Performs modular exponentiation - (A^E) mod N. - * - * This function performs modular exponentiation. - * - * @param base CASPER base address - * @param signature first addend (in little endian format) - * @param pubN modulus (in little endian format) - * @param wordLen Size of pubN in bytes - * @param pubE exponent - * @param[out] plaintext Output array to store result of operation (in little endian format) - */ -void CASPER_ModExp(CASPER_Type *base, - const uint8_t *signature, - const uint8_t *pubN, - size_t wordLen, - uint32_t pubE, - uint8_t *plaintext); - -/*! - * @brief Initialize prime modulus mod in Casper memory . - * - * Set the prime modulus mod in Casper memory and set N_wordlen - * according to selected algorithm. - * - * @param curve elliptic curve algoritm - */ -void CASPER_ecc_init(casper_algo_t curve); - -/*! - * @brief Performs ECC secp256r1 point single scalar multiplication - * - * This function performs ECC secp256r1 point single scalar multiplication - * [resX; resY] = scalar * [X; Y] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate in normal form, little endian. - * @param[out] resY Output Y affine coordinate in normal form, little endian. - * @param X Input X affine coordinate in normal form, little endian. - * @param Y Input Y affine coordinate in normal form, little endian. - * @param scalar Input scalar integer, in normal form, little endian. - */ -void CASPER_ECC_SECP256R1_Mul( - CASPER_Type *base, uint32_t resX[8], uint32_t resY[8], uint32_t X[8], uint32_t Y[8], uint32_t scalar[8]); - -/*! - * @brief Performs ECC secp256r1 point double scalar multiplication - * - * This function performs ECC secp256r1 point double scalar multiplication - * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate. - * @param[out] resY Output Y affine coordinate. - * @param X1 Input X1 affine coordinate. - * @param Y1 Input Y1 affine coordinate. - * @param scalar1 Input scalar1 integer. - * @param X2 Input X2 affine coordinate. - * @param Y2 Input Y2 affine coordinate. - * @param scalar2 Input scalar2 integer. - */ -void CASPER_ECC_SECP256R1_MulAdd(CASPER_Type *base, - uint32_t resX[8], - uint32_t resY[8], - uint32_t X1[8], - uint32_t Y1[8], - uint32_t scalar1[8], - uint32_t X2[8], - uint32_t Y2[8], - uint32_t scalar2[8]); - -/*! - * @brief Performs ECC secp384r1 point single scalar multiplication - * - * This function performs ECC secp384r1 point single scalar multiplication - * [resX; resY] = scalar * [X; Y] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate in normal form, little endian. - * @param[out] resY Output Y affine coordinate in normal form, little endian. - * @param X Input X affine coordinate in normal form, little endian. - * @param Y Input Y affine coordinate in normal form, little endian. - * @param scalar Input scalar integer, in normal form, little endian. - */ -void CASPER_ECC_SECP384R1_Mul( - CASPER_Type *base, uint32_t resX[12], uint32_t resY[12], uint32_t X[12], uint32_t Y[12], uint32_t scalar[12]); - -/*! - * @brief Performs ECC secp384r1 point double scalar multiplication - * - * This function performs ECC secp384r1 point double scalar multiplication - * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate. - * @param[out] resY Output Y affine coordinate. - * @param X1 Input X1 affine coordinate. - * @param Y1 Input Y1 affine coordinate. - * @param scalar1 Input scalar1 integer. - * @param X2 Input X2 affine coordinate. - * @param Y2 Input Y2 affine coordinate. - * @param scalar2 Input scalar2 integer. - */ -void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base, - uint32_t resX[12], - uint32_t resY[12], - uint32_t X1[12], - uint32_t Y1[12], - uint32_t scalar1[12], - uint32_t X2[12], - uint32_t Y2[12], - uint32_t scalar2[12]); - -/*! - * @brief Performs ECC secp521r1 point single scalar multiplication - * - * This function performs ECC secp521r1 point single scalar multiplication - * [resX; resY] = scalar * [X; Y] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate in normal form, little endian. - * @param[out] resY Output Y affine coordinate in normal form, little endian. - * @param X Input X affine coordinate in normal form, little endian. - * @param Y Input Y affine coordinate in normal form, little endian. - * @param scalar Input scalar integer, in normal form, little endian. - */ -void CASPER_ECC_SECP521R1_Mul( - CASPER_Type *base, uint32_t resX[18], uint32_t resY[18], uint32_t X[18], uint32_t Y[18], uint32_t scalar[18]); - -/*! - * @brief Performs ECC secp521r1 point double scalar multiplication - * - * This function performs ECC secp521r1 point double scalar multiplication - * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate. - * @param[out] resY Output Y affine coordinate. - * @param X1 Input X1 affine coordinate. - * @param Y1 Input Y1 affine coordinate. - * @param scalar1 Input scalar1 integer. - * @param X2 Input X2 affine coordinate. - * @param Y2 Input Y2 affine coordinate. - * @param scalar2 Input scalar2 integer. - */ -void CASPER_ECC_SECP521R1_MulAdd(CASPER_Type *base, - uint32_t resX[18], - uint32_t resY[18], - uint32_t X1[18], - uint32_t Y1[18], - uint32_t scalar1[18], - uint32_t X2[18], - uint32_t Y2[18], - uint32_t scalar2[18]); - -void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2); -void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1); - -/*! - *@} - */ /* end of casper_driver_pkha */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_CASPER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cdog.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cdog.c deleted file mode 100644 index 9b985e1cbd2..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cdog.c +++ /dev/null @@ -1,314 +0,0 @@ -/* - * Copyright 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_cdog.h" - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.cdog" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Sets the default configuration of CDOG - * - * This function initialize CDOG config structure to default values. - * - * param conf CDOG configuration structure - */ -void CDOG_GetDefaultConfig(cdog_config_t *conf) -{ - /* Default configuration after reset */ - conf->lock = (uint8_t)kCDOG_LockCtrl_Unlock; /* Lock control */ - conf->timeout = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Timeout control */ - conf->miscompare = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Miscompare control */ - conf->sequence = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Sequence control */ - conf->state = (uint8_t)kCDOG_FaultCtrl_NoAction; /* State control */ - conf->address = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Address control */ - conf->irq_pause = (uint8_t)kCDOG_IrqPauseCtrl_Run; /* IRQ pause control */ - conf->debug_halt = (uint8_t)kCDOG_DebugHaltCtrl_Run; /* Debug halt control */ - return; -} - -/*! - * brief Sets secure counter and instruction timer values - * - * This function sets value in RELOAD and START registers for instruction timer. - * - * param base CDOG peripheral base address - * param reload reload value - * param start start value - */ -void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start) -{ - base->RELOAD = reload; - base->START = start; -} - -/*! - * brief Stops secure counter and instruction timer - * - * This function stops instruction timer and secure counter. - * This also change state of CDOG to IDLE. - * - * param base CDOG peripheral base address - * param stop expected value which will be compared with value of secure counter - */ -void CDOG_Stop(CDOG_Type *base, uint32_t stop) -{ - base->STOP = stop; -} - -/*! - * brief Sets secure counter and instruction timer values - * - * This function sets value in STOP, RELOAD and START registers - * for instruction timer and secure counter. - * - * param base CDOG peripheral base address - * param stop expected value which will be compared with value of secure counter - * param reload reload value for instruction timer - * param start start value for secure timer - */ -void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start) -{ - base->STOP = stop; - base->RELOAD = reload; - base->START = start; -} - -/*! - * brief Add value to secure counter - * - * This function add specified value to secure counter. - * - * param base CDOG peripheral base address. - * param add Value to be added. - */ -void CDOG_Add(CDOG_Type *base, uint32_t add) -{ - base->ADD = (secure_counter_t)add; -} - -/*! - * brief Add 1 to secure counter - * - * This function add 1 to secure counter. - * - * param base CDOG peripheral base address. - * param add Value to be added. - */ -void CDOG_Add1(CDOG_Type *base) -{ - base->ADD1 = (secure_counter_t)0x1U; -} - -/*! - * brief Add 16 to secure counter - * - * This function add 16 to secure counter. - * - * param base CDOG peripheral base address. - * param add Value to be added. - */ -void CDOG_Add16(CDOG_Type *base) -{ - base->ADD16 = (secure_counter_t)0x1U; -} - -/*! - * brief Add 256 to secure counter - * - * This function add 256 to secure counter. - * - * param base CDOG peripheral base address. - * param add Value to be added. - */ -void CDOG_Add256(CDOG_Type *base) -{ - base->ADD256 = (secure_counter_t)0x1U; -} - -/*! - * brief Substract value to secure counter - * - * This function substract specified value to secure counter. - * - * param base CDOG peripheral base address. - * param sub Value to be substracted. - */ -void CDOG_Sub(CDOG_Type *base, uint32_t sub) -{ - base->SUB = (secure_counter_t)sub; -} - -/*! - * brief Substract 1 from secure counter - * - * This function substract specified 1 from secure counter. - * - * param base CDOG peripheral base address. - */ -void CDOG_Sub1(CDOG_Type *base) -{ - base->SUB1 = (secure_counter_t)0x1U; -} - -/*! - * brief Substract 16 from secure counter - * - * This function substract specified 16 from secure counter. - * - * param base CDOG peripheral base address. - */ -void CDOG_Sub16(CDOG_Type *base) -{ - base->SUB16 = (secure_counter_t)0x1U; -} - -/*! - * brief Substract 256 from secure counter - * - * This function substract specified 256 from secure counter. - * - * param base CDOG peripheral base address. - */ -void CDOG_Sub256(CDOG_Type *base) -{ - base->SUB256 = (secure_counter_t)0x1U; -} - -/*! - * brief Checks secure counter. - * - * This function compares stop value with secure counter value - * by writting to RELOAD refister. - * - * param base CDOG peripheral base address - * param check expected (stop) value. - */ -void CDOG_Check(CDOG_Type *base, uint32_t check) -{ - base->RESTART = check; -} - -/*! - * brief Set the CDOG persistent word. - * - * param base CDOG peripheral base address. - * param value The value to be written. - */ -void CDOG_WritePersistent(CDOG_Type *base, uint32_t value) -{ - base->PERSISTENT = value; -} - -/*! - * brief Get the CDOG persistent word. - * - * param base CDOG peripheral base address. - * return The persistent word. - */ -uint32_t CDOG_ReadPersistent(CDOG_Type *base) -{ - return base->PERSISTENT; -} - -/*! - * brief Initialize CDOG - * - * This function initializes CDOG block and setting. - * - * param base CDOG peripheral base address - * param conf CDOG configuration structure - * return Status of the init operation - */ -status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf) -{ - /* Ungate clock to CDOG engine and reset it */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#ifdef CDOG_CLOCKS - CLOCK_EnableClock(kCLOCK_Cdog); -#endif /* CDOG_CLOCKS */ -#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET) - RESET_PeripheralReset(kCDOG_RST_SHIFT_RSTn); -#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */ - - if (base->CONTROL == 0x0U) - { - /* CDOG is not in IDLE mode, which may be cause after SW reset. */ - /* Writing to CONTROL register will trigger fault. */ - return kStatus_Fail; - } - - /* Clear pending errors, otherwise the device will reset */ - /* itself immediately after enable Code Watchdog */ - if ((uint32_t)kCDOG_LockCtrl_Lock == - ((base->CONTROL & CDOG_CONTROL_LOCK_CTRL_MASK) >> CDOG_CONTROL_LOCK_CTRL_SHIFT)) - - { - CDOG->FLAGS = CDOG_FLAGS_TO_FLAG(1U) | CDOG_FLAGS_MISCOM_FLAG(1U) | CDOG_FLAGS_SEQ_FLAG(1U) | - CDOG_FLAGS_CNT_FLAG(1U) | CDOG_FLAGS_STATE_FLAG(1U) | CDOG_FLAGS_ADDR_FLAG(1U) | - CDOG_FLAGS_POR_FLAG(1U); - } - else - { - CDOG->FLAGS = CDOG_FLAGS_TO_FLAG(0U) | CDOG_FLAGS_MISCOM_FLAG(0U) | CDOG_FLAGS_SEQ_FLAG(0U) | - CDOG_FLAGS_CNT_FLAG(0U) | CDOG_FLAGS_STATE_FLAG(0U) | CDOG_FLAGS_ADDR_FLAG(0U) | - CDOG_FLAGS_POR_FLAG(0U); - } - - base->CONTROL = - CDOG_CONTROL_TIMEOUT_CTRL(conf->timeout) | /* Action if the timeout event is triggered */ - CDOG_CONTROL_MISCOMPARE_CTRL(conf->miscompare) | /* Action if the miscompare error event is triggered */ - CDOG_CONTROL_SEQUENCE_CTRL(conf->sequence) | /* Action if the sequence error event is triggered */ - CDOG_CONTROL_STATE_CTRL(conf->state) | /* Action if the state error event is triggered */ - CDOG_CONTROL_ADDRESS_CTRL(conf->address) | /* Action if the address error event is triggered */ - CDOG_CONTROL_IRQ_PAUSE(conf->irq_pause) | /* Pause running during interrupts setup */ - CDOG_CONTROL_DEBUG_HALT_CTRL( - conf->debug_halt) | /* Halt CDOG timer during debug so we have chance to debug code */ - CDOG_CONTROL_LOCK_CTRL(conf->lock); /* Lock control register */ - - NVIC_EnableIRQ(CDOG_IRQn); - - return kStatus_Success; -} - -/*! - * brief Deinitialize CDOG - * - * This function stops CDOG secure counter. - * - * param base CDOG peripheral base address - */ -void CDOG_Deinit(CDOG_Type *base) -{ - NVIC_DisableIRQ(CDOG_IRQn); - -#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET) - RESET_SetPeripheralReset(kCDOG_RST_SHIFT_RSTn); -#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#ifdef CDOG_CLOCKS - CLOCK_DisableClock(kCLOCK_Cdog); -#endif /* CDOG_CLOCKS */ -#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cdog.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cdog.h deleted file mode 100644 index b93c8dbdfe7..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cdog.h +++ /dev/null @@ -1,325 +0,0 @@ -/* - * Copyright 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_CDOG_H_ -#define _FSL_CDOG_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup CDOG - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Defines CDOG driver version 2.1.1. - * - * Change log: - * - Version 2.1.1 - * - Remove bit CONTROL[CONTROL_CTRL] - * - Version 2.1.0 - * - Rename CWT to CDOG - * - Version 2.0.2 - * - Fix MISRA-2012 issues - * - Version 2.0.1 - * - Fix doxygen issues - * - Version 2.0.0 - * - initial version - */ -#define FSL_CDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) -/*@}*/ - -typedef struct -{ - uint8_t lock : 2; - uint8_t timeout : 3; - uint8_t miscompare : 3; - uint8_t sequence : 3; - uint8_t state : 3; - uint8_t address : 3; - uint8_t reserved : 8; - uint8_t irq_pause : 2; - uint8_t debug_halt : 2; -} cdog_config_t; - -enum __cdog_debug_Action_ctrl_enum -{ - kCDOG_DebugHaltCtrl_Run = 0x1, - kCDOG_DebugHaltCtrl_Pause = 0x2, -}; - -enum __cdog_irq_pause_ctrl_enum -{ - kCDOG_IrqPauseCtrl_Run = 0x1, - kCDOG_IrqPauseCtrl_Pause = 0x2, -}; - -enum __cdog_fault_ctrl_enum -{ - kCDOG_FaultCtrl_EnableReset = 0x1U, - kCDOG_FaultCtrl_EnableInterrupt = 0x2U, - kCDOG_FaultCtrl_NoAction = 0x4U, -}; - -enum __code_lock_ctrl_enum -{ - kCDOG_LockCtrl_Lock = 0x1, - kCDOG_LockCtrl_Unlock = 0x2, -}; - -typedef uint32_t secure_counter_t; - -#define SC_ADD(add) \ - do \ - { \ - CDOG->ADD = (secure_counter_t)(add); \ - } while (0) - -#define SC_ADD1 \ - do \ - { \ - CDOG->ADD1 = (secure_counter_t)0x1U; \ - } while (0) - -#define SC_ADD16 \ - do \ - { \ - CDOG->ADD16 = (secure_counter_t)0x1U; \ - } while (0) - -#define SC_ADD256 \ - do \ - { \ - CDOG->ADD256 = (secure_counter_t)0x1U; \ - } while (0) - -#define SC_SUB(sub) \ - do \ - { \ - CDOG->SUB = (secure_counter_t)(sub); \ - } while (0) - -#define SC_SUB1 \ - do \ - { \ - CDOG->SUB1 = (secure_counter_t)0x1U; \ - } while (0) - -#define SC_SUB16 \ - do \ - { \ - CDOG->SUB16 = (secure_counter_t)0x1U; \ - } while (0) - -#define SC_SUB256 \ - do \ - { \ - CDOG->SUB256 = (secure_counter_t)0x1U; \ - } while (0) - -#define SC_CHECK(val) \ - do \ - { \ - CDOG->RESTART = (secure_counter_t)val; \ - } while (0) - -/******************************************************************************* - * API - *******************************************************************************/ - -extern void CDOG_DriverIRQHandler(void); - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name CDOG Functional Operation - * @{ - */ - -/*! - * @brief Initialize CDOG - * - * This function initializes CDOG block and setting. - * - * @param base CDOG peripheral base address - * @param conf CDOG configuration structure - * @return Status of the init operation - */ -status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf); - -/*! - * @brief Deinitialize CDOG - * - * This function deinitializes CDOG secure counter. - * - * @param base CDOG peripheral base address - */ -void CDOG_Deinit(CDOG_Type *base); - -/*! - * @brief Sets the default configuration of CDOG - * - * This function initialize CDOG config structure to default values. - * - * @param conf CDOG configuration structure - */ -void CDOG_GetDefaultConfig(cdog_config_t *conf); - -/*! - * @brief Stops secure counter and instruction timer - * - * This function stops instruction timer and secure counter. - * This also change state od CDOG to IDLE. - * - * @param base CDOG peripheral base address - * @param stop expected value which will be compared with value of secure counter - */ -void CDOG_Stop(CDOG_Type *base, uint32_t stop); - -/*! - * @brief Sets secure counter and instruction timer values - * - * This function sets value in RELOAD and START registers - * for instruction timer and secure counter - * - * @param base CDOG peripheral base address - * @param reload reload value - * @param start start value - */ -void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start); - -/*! - * @brief Checks secure counter. - * - * This function compares stop value in handler with secure counter value - * by writting to RELOAD refister. - * - * @param base CDOG peripheral base address - * @param check expected (stop) value - */ -void CDOG_Check(CDOG_Type *base, uint32_t check); - -/*! - * @brief Sets secure counter and instruction timer values - * - * This function sets value in STOP, RELOAD and START registers - * for instruction timer and secure counter. - * - * @param base CDOG peripheral base address - * @param stop expected value which will be compared with value of secure counter - * @param reload reload value for instruction timer - * @param start start value for secure timer - */ -void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start); - -/*! - * @brief Add value to secure counter - * - * This function add specified value to secure counter. - * - * @param base CDOG peripheral base address. - * @param add Value to be added. - */ -void CDOG_Add(CDOG_Type *base, uint32_t add); - -/*! - * @brief Add 1 to secure counter - * - * This function add 1 to secure counter. - * - * @param base CDOG peripheral base address. - */ -void CDOG_Add1(CDOG_Type *base); - -/*! - * @brief Add 16 to secure counter - * - * This function add 16 to secure counter. - * - * @param base CDOG peripheral base address. - */ -void CDOG_Add16(CDOG_Type *base); - -/*! - * @brief Add 256 to secure counter - * - * This function add 256 to secure counter. - * - * @param base CDOG peripheral base address. - */ -void CDOG_Add256(CDOG_Type *base); - -/*! - * brief Substract value to secure counter - * - * This function substract specified value to secure counter. - * - * param base CDOG peripheral base address. - * param sub Value to be substracted. - */ -void CDOG_Sub(CDOG_Type *base, uint32_t sub); - -/*! - * @brief Substract 1 from secure counter - * - * This function substract specified 1 from secure counter. - * - * @param base CDOG peripheral base address. - */ -void CDOG_Sub1(CDOG_Type *base); - -/*! - * @brief Substract 16 from secure counter - * - * This function substract specified 16 from secure counter. - * - * @param base CDOG peripheral base address. - */ -void CDOG_Sub16(CDOG_Type *base); - -/*! - * @brief Substract 256 from secure counter - * - * This function substract specified 256 from secure counter. - * - * @param base CDOG peripheral base address. - */ -void CDOG_Sub256(CDOG_Type *base); - -/*! - * @brief Set the CDOG persistent word. - * - * @param base CDOG peripheral base address. - * @param value The value to be written. - */ -void CDOG_WritePersistent(CDOG_Type *base, uint32_t value); - -/*! - * @brief Get the CDOG persistent word. - * - * @param base CDOG peripheral base address. - * @return The persistent word. - */ -uint32_t CDOG_ReadPersistent(CDOG_Type *base); - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ /* end of group cdog */ - -#endif /* _FSL_CDOG_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_clock.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_clock.c deleted file mode 100644 index 8a3be03261b..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_clock.c +++ /dev/null @@ -1,2179 +0,0 @@ -/* - * Copyright 2017 - 2021 , NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_clock.h" -#include "fsl_power.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.clock" -#endif -#define NVALMAX (0x100U) -#define PVALMAX (0x20U) -#define MVALMAX (0x10000U) - -#define PLL_MAX_N_DIV 0x100U - -/*-------------------------------------------------------------------------- -!!! If required these #defines can be moved to chip library file -----------------------------------------------------------------------------*/ - -#define PLL_SSCG1_MDEC_VAL_P (10U) /* MDEC is in bits 25 downto 10 */ -#define PLL_SSCG1_MDEC_VAL_M (0xFFFFULL << PLL_SSCG1_MDEC_VAL_P) -#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */ -#define PLL_NDEC_VAL_M (0xFFUL << PLL_NDEC_VAL_P) -#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */ -#define PLL_PDEC_VAL_M (0x1FUL << PLL_PDEC_VAL_P) - -#define PLL_MIN_CCO_FREQ_MHZ (275000000U) -#define PLL_MAX_CCO_FREQ_MHZ (550000000U) -#define PLL_LOWER_IN_LIMIT (2000U) /*!< Minimum PLL input rate */ -#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */ -#define PLL_MIN_IN_SSMODE (3000000U) -#define PLL_MAX_IN_SSMODE \ - (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */ - -/* PLL NDEC reg */ -#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) -/* PLL PDEC reg */ -#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M) -/* SSCG control1 */ -#define PLL_SSCG1_MDEC_VAL_SET(value) (((uint64_t)(value) << PLL_SSCG1_MDEC_VAL_P) & PLL_SSCG1_MDEC_VAL_M) - -/* PLL0 SSCG control1 */ -#define PLL0_SSCG_MD_FRACT_P 0U -#define PLL0_SSCG_MD_INT_P 25U -#define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) -#define PLL0_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL0_SSCG_MD_INT_P) - -#define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_FRACT_M) -#define PLL0_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_INT_P) & PLL0_SSCG_MD_INT_M) - -/* Saved value of PLL output rate, computed whenever needed to save run-time - computation on each call to retrive the PLL rate. */ -static uint32_t s_Pll0_Freq; -static uint32_t s_Pll1_Freq; - -/** External clock rate on the CLKIN pin in Hz. If not used, - set this to 0. Otherwise, set it to the exact rate in Hz this pin is - being driven at. */ -static uint32_t s_Ext_Clk_Freq = 16000000U; -static uint32_t s_I2S_Mclk_Freq = 0U; -static uint32_t s_PLU_ClkIn_Freq = 0U; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ -static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); -/* Get predivider (N) from PLL0 NDEC setting */ -static uint32_t findPll0PreDiv(void); -/* Get predivider (N) from PLL1 NDEC setting */ -static uint32_t findPll1PreDiv(void); -/* Get postdivider (P) from PLL0 PDEC setting */ -static uint32_t findPll0PostDiv(void); -/* Get postdivider (P) from PLL1 PDEC setting. */ -static uint32_t findPll1PostDiv(void); -/* Get multiplier (M) from PLL0 MDEC and SSCG settings */ -static float findPll0MMult(void); -/* Get multiplier (M) from PLL1 MDEC. */ -static uint32_t findPll1MMult(void); -/* Get the greatest common divisor */ -static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); -/* Set PLL output based on desired output rate */ -static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS); -/* Update local PLL rate variable */ -static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup); -/* Update local PLL1 rate variable */ -static void CLOCK_GetPLL1OutFromSetupUpdate(pll_setup_t *pSetup); - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Clock Selection for IP */ -/** - * brief Configure the clock selection muxes. - * param connection : Clock to be configured. - * return Nothing - */ -void CLOCK_AttachClk(clock_attach_id_t connection) -{ - uint8_t mux; - uint8_t sel; - uint16_t item; - uint32_t tmp32 = (uint32_t)connection; - uint32_t i; - volatile uint32_t *pClkSel; - - pClkSel = &(SYSCON->SYSTICKCLKSELX[0]); - - if (kNONE_to_NONE != connection) - { - for (i = 0U; i < 2U; i++) - { - if (tmp32 == 0U) - { - break; - } - item = (uint16_t)GET_ID_ITEM(tmp32); - if (item != 0U) - { - mux = (uint8_t)GET_ID_ITEM_MUX(item); - sel = (uint8_t)GET_ID_ITEM_SEL(item); - if (mux == CM_RTCOSC32KCLKSEL) - { - PMC->RTCOSC32K = (PMC->RTCOSC32K & ~PMC_RTCOSC32K_SEL_MASK) | PMC_RTCOSC32K_SEL(sel); - } - else if (mux == CM_OSTIMERCLKSEL) - { - PMC->OSTIMERr = (PMC->OSTIMERr & ~PMC_OSTIMER_OSTIMERCLKSEL_MASK) | PMC_OSTIMER_OSTIMERCLKSEL(sel); - } - else - { - pClkSel[mux] = sel; - } - } - tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */ - } - } -} - -/* Return the actual clock attach id */ -/** - * brief Get the actual clock attach id. - * This fuction uses the offset in input attach id, then it reads the actual source value in - * the register and combine the offset to obtain an actual attach id. - * param attachId : Clock attach id to get. - * return Clock source value. - */ -clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId) -{ - uint8_t mux; - uint32_t actualSel; - uint32_t tmp32 = (uint32_t)attachId; - uint32_t i; - uint32_t actualAttachId = 0U; - uint32_t selector = GET_ID_SELECTOR(tmp32); - volatile uint32_t *pClkSel; - - pClkSel = &(SYSCON->SYSTICKCLKSELX[0]); - - if (kNONE_to_NONE == attachId) - { - return kNONE_to_NONE; - } - - for (i = 0U; i < 2U; i++) - { - mux = (uint8_t)GET_ID_ITEM_MUX(tmp32); - if (tmp32 != 0UL) - { - if (mux == CM_RTCOSC32KCLKSEL) - { - actualSel = ((PMC->RTCOSC32K) & PMC_RTCOSC32K_SEL_MASK) >> PMC_RTCOSC32K_SEL_SHIFT; - } - else if (mux == CM_OSTIMERCLKSEL) - { - actualSel = ((PMC->OSTIMERr) & PMC_OSTIMER_OSTIMERCLKSEL_MASK) >> PMC_OSTIMER_OSTIMERCLKSEL_SHIFT; - } - else - { - actualSel = pClkSel[mux]; - } - - /* Consider the combination of two registers */ - actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i); - } - tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */ - } - - actualAttachId |= selector; - - return (clock_attach_id_t)actualAttachId; -} - -/* Set IP Clock Divider */ -/** - * brief Setup peripheral clock dividers. - * param div_name : Clock divider name - * param divided_by_value: Value to be divided - * param reset : Whether to reset the divider counter. - * return Nothing - */ -void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) -{ - volatile uint32_t *pClkDiv; - - pClkDiv = &(SYSCON->SYSTICKCLKDIV0); - if ((div_name >= kCLOCK_DivFlexFrg0) && (div_name <= kCLOCK_DivFlexFrg7)) - { - /*!< Flexcomm Interface function clock = (clock selected via FCCLKSEL) / (1+ MULT /DIV), DIV = 0xFF */ - ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = - SYSCON_FLEXFRG0CTRL_DIV_MASK | SYSCON_FLEXFRG0CTRL_MULT(divided_by_value); - } - else - { - if (reset) - { - ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = 1UL << 29U; - } - if (divided_by_value == 0U) /*!< halt */ - { - ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = 1UL << 30U; - } - else - { - ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = (divided_by_value - 1U); - } - } -} - -/* Set RTC 1KHz Clock Divider */ -/** - * brief Setup rtc 1khz clock divider. - * param divided_by_value: Value to be divided - * return Nothing - */ -void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value) -{ - PMC->RTCOSC32K = - (PMC->RTCOSC32K & ~PMC_RTCOSC32K_CLK1KHZDIV_MASK) | PMC_RTCOSC32K_CLK1KHZDIV(divided_by_value - 28U); -} - -/* Set RTC 1KHz Clock Divider */ -/** - * brief Setup rtc 1hz clock divider. - * param divided_by_value: Value to be divided - * return Nothing - */ -void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value) -{ - if (divided_by_value == 0U) /*!< halt */ - { - PMC->RTCOSC32K |= (1UL << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT); - } - else - { - PMC->RTCOSC32K = - (PMC->RTCOSC32K & ~PMC_RTCOSC32K_CLK1HZDIV_MASK) | PMC_RTCOSC32K_CLK1HZDIV(divided_by_value - 31744U); - } -} - -/* Set FRO Clocking */ -/** - * brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). - * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is - * enabled. - * param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ) - * return returns success or fail status. - */ -status_t CLOCK_SetupFROClocking(uint32_t iFreq) -{ - if ((iFreq != 12000000U) && (iFreq != 96000000U)) - { - return kStatus_Fail; - } - /* Enable Analog Control module */ - SYSCON->PRESETCTRLCLR[2] = (1UL << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT); - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK; - /* Power up the FRO192M */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); - - if (iFreq == 96000000U) - { - ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(1); - } - /* always enable - else if (iFreq == 48000000U) - { - ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(1); - }*/ - else - { - ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(1); - } - return kStatus_Success; -} - -/* Set the FLASH wait states for the passed frequency */ -/** - * brief Set the flash wait states for the input freuqency. - * param iFreq: Input frequency - * return Nothing - */ -typedef struct -{ - uint32_t waitstate; - uint32_t freqMax; -} WaitStateInterval_t; - -/* clang-format off */ -/* Wait state if frequency is inferior to the one specified */ -static const WaitStateInterval_t IntervalList[] = { - {0, 11000000}, - {1, 22000000}, - {2, 33000000}, - {3, 44000000}, - {4, 55000000}, - {5, 66000000}, - {6, 84000000}, - {7, 104000000}, - {8, 119000000}, - {9, 129000000}, - {10, 144000000}, - {11, 150000000} /* Maximum allowed frequency (150 MHz) */ -}; -/* clang-format on */ - -void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz) -{ - /* Flash Controller & FMC internal number of Wait States (minus 1) */ - uint32_t num_wait_states = 15UL; /* Default to the maximum number of wait states */ - - for (size_t cnt = 0; cnt < (sizeof(IntervalList) / sizeof(WaitStateInterval_t)); cnt++) - { - if (system_freq_hz <= IntervalList[cnt].freqMax) - { - num_wait_states = IntervalList[cnt].waitstate; - break; - } - } - - FLASH->INT_CLR_STATUS = 0x1F; /* Clear all status flags */ - - FLASH->DATAW[0] = (FLASH->DATAW[0] & 0xFFFFFFF0UL) | - (num_wait_states & (SYSCON_FMCCR_FLASHTIM_MASK >> SYSCON_FMCCR_FLASHTIM_SHIFT)); - - FLASH->CMD = 0x2; /* CMD_SET_READ_MODE */ - - /* Wait until the cmd is completed (without error) */ - while ((FLASH->INT_STATUS & FLASH_INT_STATUS_DONE_MASK) == 0UL) - { - } - - /* Adjust FMC waiting time cycles (num_wait_states) */ - SYSCON->FMCCR = (SYSCON->FMCCR & ~SYSCON_FMCCR_FLASHTIM_MASK) | - ((num_wait_states << SYSCON_FMCCR_FLASHTIM_SHIFT) & SYSCON_FMCCR_FLASHTIM_MASK); -} - -/* Set EXT OSC Clk */ -/** - * brief Initialize the external osc clock to given frequency. - * Crystal oscillator with an operating frequency of 12 MHz to 32 MHz. - * Option for external clock input (bypass mode) for clock frequencies of up to 25 MHz. - * param iFreq : Desired frequency (must be equal to exact rate in Hz) - * return returns success or fail status. - */ -status_t CLOCK_SetupExtClocking(uint32_t iFreq) -{ - if (iFreq > 32000000U) - { - return kStatus_Fail; - } - /* Turn on power for crystal 32 MHz */ - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); - /* Enable clock_in clock for clock module. */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; - - s_Ext_Clk_Freq = iFreq; - return kStatus_Success; -} - -/* Set I2S MCLK Clk */ -/** - * brief Initialize the I2S MCLK clock to given frequency. - * param iFreq : Desired frequency (must be equal to exact rate in Hz) - * return returns success or fail status. - */ -status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq) -{ - s_I2S_Mclk_Freq = iFreq; - return kStatus_Success; -} - -/* Set PLU CLKIN Clk */ -/** - * brief Initialize the PLU CLKIN clock to given frequency. - * param iFreq : Desired frequency (must be equal to exact rate in Hz) - * return returns success or fail status. - */ -status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq) -{ - s_PLU_ClkIn_Freq = iFreq; - return kStatus_Success; -} - -/* Get CLOCK OUT Clk */ -/*! brief Return Frequency of ClockOut - * return Frequency of ClockOut - */ -uint32_t CLOCK_GetClockOutClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->CLKOUTSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - - case 2U: - freq = CLOCK_GetExtClkFreq(); - break; - - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - - case 5U: - freq = CLOCK_GetPll1OutFreq(); - break; - - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U); -} - -/* Get CAN Clk */ -/*! brief Return Frequency of Can Clock - * return Frequency of Can. - */ -uint32_t CLOCK_GetMCanClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->CANCLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CANCLKDIV & SYSCON_CANCLKDIV_DIV_MASK) + 1U); - break; - case 1U: - freq = CLOCK_GetFro1MFreq(); - break; - case 2U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq; -} - -/* Get ADC Clk */ -/*! brief Return Frequency of Adc Clock - * return Frequency of Adc. - */ -uint32_t CLOCK_GetAdcClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->ADCCLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 2U: - freq = CLOCK_GetFroHfFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq / ((SYSCON->ADCCLKDIV & SYSCON_ADCCLKDIV_DIV_MASK) + 1U); -} - -/* Get USB0 Clk */ -/*! brief Return Frequency of Usb0 Clock - * return Frequency of Usb0 Clock. - */ -uint32_t CLOCK_GetUsb0ClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->USB0CLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 5U: - freq = CLOCK_GetPll1OutFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq / ((SYSCON->USB0CLKDIV & 0xffU) + 1U); -} - -/* Get USB1 Clk */ -/*! brief Return Frequency of Usb1 Clock - * return Frequency of Usb1 Clock. - */ -uint32_t CLOCK_GetUsb1ClkFreq(void) -{ - return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; -} - -/* Get MCLK Clk */ -/*! brief Return Frequency of MClk Clock - * return Frequency of MClk Clock. - */ -uint32_t CLOCK_GetMclkClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->MCLKCLKSEL) - { - case 0U: - freq = CLOCK_GetFroHfFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq / ((SYSCON->MCLKDIV & 0xffU) + 1U); -} - -/* Get SCTIMER Clk */ -/*! brief Return Frequency of SCTimer Clock - * return Frequency of SCTimer Clock. - */ -uint32_t CLOCK_GetSctClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->SCTCLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 2U: - freq = CLOCK_GetExtClkFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 5U: - freq = CLOCK_GetI2SMClkFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq / ((SYSCON->SCTCLKDIV & 0xffU) + 1U); -} - -/* Get FRO 12M Clk */ -/*! brief Return Frequency of FRO 12MHz - * return Frequency of FRO 12MHz - */ -uint32_t CLOCK_GetFro12MFreq(void) -{ - return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; -} - -/* Get FRO 1M Clk */ -/*! brief Return Frequency of FRO 1MHz - * return Frequency of FRO 1MHz - */ -uint32_t CLOCK_GetFro1MFreq(void) -{ - return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; -} - -/* Get EXT OSC Clk */ -/*! brief Return Frequency of External Clock - * return Frequency of External Clock. If no external clock is used returns 0. - */ -uint32_t CLOCK_GetExtClkFreq(void) -{ - return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; -} - -/* Get WATCH DOG Clk */ -/*! brief Return Frequency of Watchdog - * return Frequency of Watchdog - */ -uint32_t CLOCK_GetWdtClkFreq(void) -{ - return CLOCK_GetFro1MFreq() / ((SYSCON->WDTCLKDIV & SYSCON_WDTCLKDIV_DIV_MASK) + 1U); -} - -/* Get HF FRO Clk */ -/*! brief Return Frequency of High-Freq output of FRO - * return Frequency of High-Freq output of FRO - */ -uint32_t CLOCK_GetFroHfFreq(void) -{ - return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; -} - -/* Get SYSTEM PLL Clk */ -/*! brief Return Frequency of PLL - * return Frequency of PLL - */ -uint32_t CLOCK_GetPll0OutFreq(void) -{ - return s_Pll0_Freq; -} - -/* Get USB PLL Clk */ -/*! brief Return Frequency of USB PLL - * return Frequency of PLL - */ -uint32_t CLOCK_GetPll1OutFreq(void) -{ - return s_Pll1_Freq; -} - -/* Get RTC OSC Clk */ -/*! brief Return Frequency of 32kHz osc - * return Frequency of 32kHz osc - */ -uint32_t CLOCK_GetOsc32KFreq(void) -{ - return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && - (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? - CLK_RTC_32K_CLK : - ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && - ((PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK) != 0UL)) ? - CLK_RTC_32K_CLK : - 0UL; -} - -/* Get MAIN Clk */ -/*! brief Return Frequency of Core System - * return Frequency of Core System - */ -uint32_t CLOCK_GetCoreSysClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->MAINCLKSELB) - { - case 0U: - if (SYSCON->MAINCLKSELA == 0U) - { - freq = CLOCK_GetFro12MFreq(); - } - else if (SYSCON->MAINCLKSELA == 1U) - { - freq = CLOCK_GetExtClkFreq(); - } - else if (SYSCON->MAINCLKSELA == 2U) - { - freq = CLOCK_GetFro1MFreq(); - } - else if (SYSCON->MAINCLKSELA == 3U) - { - freq = CLOCK_GetFroHfFreq(); - } - else - { - /* Added comments to avoid the violation of MISRA C-2012 rule 15.7 */ - } - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 2U: - freq = CLOCK_GetPll1OutFreq(); - break; - - case 3U: - freq = CLOCK_GetOsc32KFreq(); - break; - - default: - freq = 0U; - break; - } - - return freq; -} - -/* Get I2S MCLK Clk */ -/*! brief Return Frequency of I2S MCLK Clock - * return Frequency of I2S MCLK Clock - */ -uint32_t CLOCK_GetI2SMClkFreq(void) -{ - return s_I2S_Mclk_Freq; -} - -/* Get PLU CLKIN Clk */ -/*! brief Return Frequency of PLU CLKIN Clock - * return Frequency of PLU CLKIN Clock - */ -uint32_t CLOCK_GetPLUClkInFreq(void) -{ - return s_PLU_ClkIn_Freq; -} - -/* Get FLEXCOMM input clock */ -/*! brief Return Frequency of flexcomm input clock - * param id : flexcomm instance id - * return Frequency value - */ -uint32_t CLOCK_GetFlexCommInputClock(uint32_t id) -{ - uint32_t freq = 0U; - - switch (SYSCON->FCCLKSELX[id]) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U); - break; - case 2U: - freq = CLOCK_GetFro12MFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); - break; - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - case 5U: - freq = CLOCK_GetI2SMClkFreq(); - break; - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq; -} - -/* Get FLEXCOMM Clk */ -uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) -{ - uint32_t freq = 0U; - uint32_t frgMul = 0U; - uint32_t frgDiv = 0U; - - freq = CLOCK_GetFlexCommInputClock(id); - frgMul = (SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_MULT_MASK) >> 8U; - frgDiv = SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_DIV_MASK; - return (uint32_t)(((uint64_t)freq * ((uint64_t)frgDiv + 1ULL)) / (frgMul + frgDiv + 1UL)); -} - -/* Get HS_LPSI Clk */ -uint32_t CLOCK_GetHsLspiClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->HSLSPICLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U); - break; - case 2U: - freq = CLOCK_GetFro12MFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); - break; - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq; -} - -/* Get CTimer Clk */ -/*! brief Return Frequency of CTimer functional Clock - * return Frequency of CTimer functional Clock - */ -uint32_t CLOCK_GetCTimerClkFreq(uint32_t id) -{ - uint32_t freq = 0U; - - switch (SYSCON->CTIMERCLKSELX[id]) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - case 5U: - freq = CLOCK_GetI2SMClkFreq(); - break; - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq; -} - -/* Get Systick Clk */ -/*! brief Return Frequency of SystickClock - * return Frequency of Systick Clock - */ -uint32_t CLOCK_GetSystickClkFreq(uint32_t id) -{ - uint32_t freq = 0U; - - switch (SYSCON->SYSTICKCLKSELX[id]) - { - case 0U: - /*Niobe4mini just has one SYSTICKSEL and SYSTICKDIV register, Fix coverity problem in this way temporarily - */ - freq = CLOCK_GetCoreSysClkFreq() / (((SYSCON->SYSTICKCLKDIV0) & 0xffU) + 1U); - break; - case 1U: - freq = CLOCK_GetFro1MFreq(); - break; - case 2U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq; -} - -/* Set FlexComm Clock */ -/** - * brief Set the flexcomm output frequency. - * param id : flexcomm instance id - * freq : output frequency - * return 0 : the frequency range is out of range. - * 1 : switch successfully. - */ -uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq) -{ - uint32_t input = CLOCK_GetFlexCommClkFreq(id); - uint32_t mul; - - if ((freq > 48000000UL) || (freq > input) || (input / freq >= 2UL)) - { - /* FRG output frequency should be less than equal to 48MHz */ - return 0UL; - } - else - { - mul = (uint32_t)((((uint64_t)input - freq) * 256ULL) / ((uint64_t)freq)); - SYSCON->FLEXFRGXCTRL[id] = (mul << 8U) | 0xFFU; - return 1UL; - } -} - -/* Get IP Clk */ -/*! brief Return Frequency of selected clock - * return Frequency of selected clock - */ -uint32_t CLOCK_GetFreq(clock_name_t clockName) -{ - uint32_t freq; - switch (clockName) - { - case kCLOCK_CoreSysClk: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case kCLOCK_BusClk: - freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); - break; - case kCLOCK_ClockOut: - freq = CLOCK_GetClockOutClkFreq(); - break; - case kCLOCK_Pll1Out: - freq = CLOCK_GetPll1OutFreq(); - break; - case kCLOCK_Mclk: - freq = CLOCK_GetMclkClkFreq(); - break; - case kCLOCK_FroHf: - freq = CLOCK_GetFroHfFreq(); - break; - case kCLOCK_Fro12M: - freq = CLOCK_GetFro12MFreq(); - break; - case kCLOCK_Fro1M: - freq = CLOCK_GetFro1MFreq(); - break; - case kCLOCK_ExtClk: - freq = CLOCK_GetExtClkFreq(); - break; - case kCLOCK_Pll0Out: - freq = CLOCK_GetPll0OutFreq(); - break; - case kCLOCK_FlexI2S: - freq = CLOCK_GetI2SMClkFreq(); - break; - default: - freq = 0U; - break; - } - return freq; -} - -/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ -static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) -{ - uint32_t seli, selp; - /* bandwidth: compute selP from Multiplier */ - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ - { - selp = (M >> 2U) + 1U; - if (selp >= 31U) - { - selp = 31U; - } - *pSelP = selp; - - if (M >= 8000UL) - { - seli = 1UL; - } - else if (M >= 122UL) - { - seli = (uint32_t)(8000UL / M); /*floor(8000/M) */ - } - else - { - seli = 2UL * ((uint32_t)(M / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ - } - - if (seli >= 63UL) - { - seli = 63UL; - } - *pSelI = seli; - - *pSelR = 0UL; - } - else - { - /* Note: If the spread spectrum mode, choose N to ensure 3 MHz < Fin/N < 5 MHz */ - *pSelP = 3U; - *pSelI = 4U; - *pSelR = 4U; - } -} - -/* Get predivider (N) from PLL0 NDEC setting */ -static uint32_t findPll0PreDiv(void) -{ - uint32_t preDiv = 1UL; - - /* Direct input is not used? */ - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) - { - preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; - if (preDiv == 0UL) - { - preDiv = 1UL; - } - } - return preDiv; -} - -/* Get predivider (N) from PLL1 NDEC setting */ -static uint32_t findPll1PreDiv(void) -{ - uint32_t preDiv = 1UL; - - /* Direct input is not used? */ - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) - { - preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; - if (preDiv == 0UL) - { - preDiv = 1UL; - } - } - return preDiv; -} - -/* Get postdivider (P) from PLL0 PDEC setting */ -static uint32_t findPll0PostDiv(void) -{ - uint32_t postDiv = 1UL; - - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) - { - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) - { - postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; - } - else - { - postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); - } - if (postDiv == 0UL) - { - postDiv = 2UL; - } - } - return postDiv; -} - -/* Get postdivider (P) from PLL1 PDEC setting. */ -static uint32_t findPll1PostDiv(void) -{ - uint32_t postDiv = 1UL; - - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0UL) - { - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) != 0UL) - { - postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK; - } - else - { - postDiv = 2UL * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK); - } - if (postDiv == 0UL) - { - postDiv = 2UL; - } - } - - return postDiv; -} - -/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ -static float findPll0MMult(void) -{ - float mMult = 1.0F; - float mMult_fract; - uint32_t mMult_int; - - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) - { - mMult = - (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); - } - else - { - mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); - mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL0_SSCG_MD_INT_P); - mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL0_SSCG_MD_FRACT_M) / - (float)(uint32_t)(1UL << PLL0_SSCG_MD_INT_P)); - mMult = (float)mMult_int + mMult_fract; - } - if(0ULL == ((uint64_t)mMult)) - { - mMult = 1.0F; - } - return mMult; -} - -/* Get multiplier (M) from PLL1 MDEC. */ -static uint32_t findPll1MMult(void) -{ - uint32_t mMult = 1UL; - - mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK; - - if (mMult == 0UL) - { - mMult = 1UL; - } - - return mMult; -} - -/* Find greatest common divisor between m and n */ -static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) -{ - uint32_t tmp; - - while (n != 0U) - { - tmp = n; - n = m % n; - m = tmp; - } - - return m; -} - -/* - * Set PLL0 output based on desired output rate. - * In this function, the it calculates the PLL0 setting for output frequency from input clock - * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. - * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. - */ -static pll_error_t CLOCK_GetPll0ConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) -{ - uint32_t nDivOutHz, fccoHz; - uint32_t pllPreDivider, pllMultiplier, pllPostDivider; - uint32_t pllDirectInput, pllDirectOutput; - uint32_t pllSelP, pllSelI, pllSelR, uplimoff; - - /* Baseline parameters (no input or output dividers) */ - pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ - pllPostDivider = 1U; /* 1 implies post-divider will be disabled */ - pllDirectOutput = 1U; - - /* Verify output rate parameter */ - if (foutHz > PLL_MAX_CCO_FREQ_MHZ) - { - /* Maximum PLL output with post divider=1 cannot go above this frequency */ - return kStatus_PLL_OutputTooHigh; - } - if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) - { - /* Minmum PLL output with maximum post divider cannot go below this frequency */ - return kStatus_PLL_OutputTooLow; - } - - /* If using SS mode, input clock needs to be between 3MHz and 20MHz */ - if (useSS) - { - /* Verify input rate parameter */ - if (finHz < PLL_MIN_IN_SSMODE) - { - /* Input clock into the PLL cannot be lower than this */ - return kStatus_PLL_InputTooLow; - } - /* PLL input in SS mode must be under 20MHz */ - if (finHz > (PLL_MAX_IN_SSMODE * NVALMAX)) - { - return kStatus_PLL_InputTooHigh; - } - } - else - { - /* Verify input rate parameter */ - if (finHz < PLL_LOWER_IN_LIMIT) - { - /* Input clock into the PLL cannot be lower than this */ - return kStatus_PLL_InputTooLow; - } - if (finHz > PLL_HIGHER_IN_LIMIT) - { - /* Input clock into the PLL cannot be higher than this */ - return kStatus_PLL_InputTooHigh; - } - } - - /* Find the optimal CCO frequency for the output and input that - will keep it inside the PLL CCO range. This may require - tweaking the post-divider for the PLL. */ - fccoHz = foutHz; - while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) - { - /* CCO output is less than minimum CCO range, so the CCO output - needs to be bumped up and the post-divider is used to bring - the PLL output back down. */ - pllPostDivider++; - if (pllPostDivider > PVALMAX) - { - return kStatus_PLL_OutsideIntLimit; - } - - /* Target CCO goes up, PLL output goes down */ - /* divide-by-2 divider in the post-divider is always work*/ - fccoHz = foutHz * (pllPostDivider * 2U); - pllDirectOutput = 0U; - } - - /* Determine if a pre-divider is needed to get the best frequency */ - if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) - { - uint32_t a = FindGreatestCommonDivisor(fccoHz, finHz); - - if (a > PLL_LOWER_IN_LIMIT) - { - a = finHz / a; - if ((a != 0U) && (a < PLL_MAX_N_DIV)) - { - pllPreDivider = a; - } - } - } - - /* Bypass pre-divider hardware if pre-divider is 1 */ - if (pllPreDivider > 1U) - { - pllDirectInput = 0U; - } - else - { - pllDirectInput = 1U; - } - - /* Determine PLL multipler */ - nDivOutHz = (finHz / pllPreDivider); - pllMultiplier = (fccoHz / nDivOutHz); - - /* Find optimal values for filter */ - if (useSS == false) - { - /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ - if ((nDivOutHz * ((pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) - { - pllMultiplier++; - } - - /* Setup filtering */ - pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR); - uplimoff = 0U; - - /* Get encoded value for M (mult) and use manual filter, disable SS mode */ - pSetup->pllsscg[1] = - (uint32_t)((PLL_SSCG1_MDEC_VAL_SET(pllMultiplier)) | (1UL << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)); - } - else - { - uint64_t fc; - - /* Filtering will be handled by SSC */ - pllSelR = 0UL; - pllSelI = 0UL; - pllSelP = 0UL; - uplimoff = 1U; - - /* The PLL multiplier will get very close and slightly under the - desired target frequency. A small fractional component can be - added to fine tune the frequency upwards to the target. */ - fc = ((uint64_t)(uint32_t)(fccoHz % nDivOutHz) << 25UL) / nDivOutHz; - - /* Set multiplier */ - pSetup->pllsscg[0] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) | PLL0_SSCG_MD_FRACT_SET((uint32_t)fc)); - pSetup->pllsscg[1] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) >> 32U); - } - - /* Get encoded values for N (prediv) and P (postdiv) */ - pSetup->pllndec = PLL_NDEC_VAL_SET(pllPreDivider); - pSetup->pllpdec = PLL_PDEC_VAL_SET(pllPostDivider); - - /* PLL control */ - pSetup->pllctrl = (pllSelR << SYSCON_PLL0CTRL_SELR_SHIFT) | /* Filter coefficient */ - (pllSelI << SYSCON_PLL0CTRL_SELI_SHIFT) | /* Filter coefficient */ - (pllSelP << SYSCON_PLL0CTRL_SELP_SHIFT) | /* Filter coefficient */ - (0UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT) | /* PLL bypass mode disabled */ - (uplimoff << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */ - (pllDirectInput << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */ - (pllDirectOutput << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT) | /* Bypass post-divider? */ - (1UL << SYSCON_PLL0CTRL_CLKEN_SHIFT); /* Ensure the PLL clock output */ - - return kStatus_PLL_Success; -} - -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) -/* Alloct the static buffer for cache. */ -static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; -static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; -static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; -static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; -static uint32_t s_PllSetupCacheIdx = 0U; -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - -/* - * Calculate the PLL setting values from input clock freq to output freq. - */ -static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) -{ - pll_error_t retErr; -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - uint32_t i; - - for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) - { - if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && (useSS == s_UseSSCache[i])) - { - /* Hit the target in cache buffer. */ - pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl; - pSetup->pllndec = s_PllSetupCacheStruct[i].pllndec; - pSetup->pllpdec = s_PllSetupCacheStruct[i].pllpdec; - pSetup->pllsscg[0] = s_PllSetupCacheStruct[i].pllsscg[0]; - pSetup->pllsscg[1] = s_PllSetupCacheStruct[i].pllsscg[1]; - retErr = kStatus_PLL_Success; - break; - } - } - - if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - { - return retErr; - } -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - - retErr = CLOCK_GetPll0ConfigInternal(finHz, foutHz, pSetup, useSS); - -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - /* Cache the most recent calulation result into buffer. */ - s_FinHzCache[s_PllSetupCacheIdx] = finHz; - s_FoutHzCache[s_PllSetupCacheIdx] = foutHz; - s_UseSSCache[s_PllSetupCacheIdx] = useSS; - - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndec = pSetup->pllndec; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdec = pSetup->pllpdec; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[0] = pSetup->pllsscg[0]; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[1] = pSetup->pllsscg[1]; - /* Update the index for next available buffer. */ - s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - - return retErr; -} - -/* Update local PLL rate variable */ -static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup) -{ - s_Pll0_Freq = CLOCK_GetPLL0OutFromSetup(pSetup); -} - -/* Update local PLL1 rate variable */ -static void CLOCK_GetPLL1OutFromSetupUpdate(pll_setup_t *pSetup) -{ - s_Pll1_Freq = CLOCK_GetPLL1OutFromSetup(pSetup); -} - -/* Return System PLL input clock rate */ -/*! brief Return PLL0 input clock rate - * return PLL0 input clock rate - */ -uint32_t CLOCK_GetPLL0InClockRate(void) -{ - uint32_t clkRate = 0U; - - switch ((SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK)) - { - case 0x00U: - clkRate = CLK_FRO_12MHZ; - break; - - case 0x01U: - clkRate = CLOCK_GetExtClkFreq(); - break; - - case 0x02U: - clkRate = CLOCK_GetFro1MFreq(); - break; - - case 0x03U: - clkRate = CLOCK_GetOsc32KFreq(); - break; - - default: - clkRate = 0U; - break; - } - - return clkRate; -} - -/* Return PLL1 input clock rate */ -uint32_t CLOCK_GetPLL1InClockRate(void) -{ - uint32_t clkRate = 0U; - - switch ((SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK)) - { - case 0x00U: - clkRate = CLK_FRO_12MHZ; - break; - - case 0x01U: - clkRate = CLOCK_GetExtClkFreq(); - break; - - case 0x02U: - clkRate = CLOCK_GetFro1MFreq(); - break; - - case 0x03U: - clkRate = CLOCK_GetOsc32KFreq(); - break; - - default: - clkRate = 0U; - break; - } - - return clkRate; -} - -/* Return PLL0 output clock rate from setup structure */ -/*! brief Return PLL0 output clock rate from setup structure - * param pSetup : Pointer to a PLL setup structure - * return PLL0 output clock rate the setup structure will generate - */ -uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup) -{ - uint32_t clkRate = 0; - uint32_t prediv, postdiv; - float workRate = 0.0F; - - /* Get the input clock frequency of PLL. */ - clkRate = CLOCK_GetPLL0InClockRate(); - - if (((pSetup->pllctrl & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && - ((pSetup->pllctrl & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && - ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && - ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) - { - prediv = findPll0PreDiv(); - postdiv = findPll0PostDiv(); - /* Adjust input clock */ - clkRate = clkRate / prediv; - /* MDEC used for rate */ - workRate = (float)clkRate * (float)findPll0MMult(); - workRate /= (float)postdiv; - } - - return (uint32_t)workRate; -} - -/* Return PLL1 output clock rate from setup structure */ -/*! brief Return PLL1 output clock rate from setup structure - * param pSetup : Pointer to a PLL setup structure - * return PLL0 output clock rate the setup structure will generate - */ -uint32_t CLOCK_GetPLL1OutFromSetup(pll_setup_t *pSetup) -{ - uint32_t clkRate = 0; - uint32_t prediv, postdiv; - uint32_t workRate = 0UL; - - /* Get the input clock frequency of PLL. */ - clkRate = CLOCK_GetPLL1InClockRate(); - - if (((pSetup->pllctrl & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0UL) && - ((pSetup->pllctrl & SYSCON_PLL1CTRL_CLKEN_MASK) != 0UL) && - ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0UL)) - { - prediv = findPll1PreDiv(); - postdiv = findPll1PostDiv(); - /* Adjust input clock */ - clkRate = clkRate / prediv; - /* MDEC used for rate */ - workRate = clkRate * findPll1MMult(); - workRate /= postdiv; - } - - return workRate; -} - -/* Set the current PLL0 Rate */ -/*! brief Store the current PLL rate - * param rate: Current rate of the PLL - * return Nothing - **/ -void CLOCK_SetStoredPLL0ClockRate(uint32_t rate) -{ - s_Pll0_Freq = rate; -} - -/* Return PLL0 output clock rate */ -/*! brief Return PLL0 output clock rate - * param recompute : Forces a PLL rate recomputation if true - * return PLL0 output clock rate - * note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetPLL0OutClockRate(bool recompute) -{ - pll_setup_t Setup; - uint32_t rate; - - if ((recompute) || (s_Pll0_Freq == 0U)) - { - Setup.pllctrl = SYSCON->PLL0CTRL; - Setup.pllndec = SYSCON->PLL0NDEC; - Setup.pllpdec = SYSCON->PLL0PDEC; - Setup.pllsscg[0] = SYSCON->PLL0SSCG0; - Setup.pllsscg[1] = SYSCON->PLL0SSCG1; - - CLOCK_GetPLL0OutFromSetupUpdate(&Setup); - } - - rate = s_Pll0_Freq; - - return rate; -} - -/*! brief Return PLL1 output clock rate - * param recompute : Forces a PLL rate recomputation if true - * return PLL1 output clock rate - * note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetPLL1OutClockRate(bool recompute) -{ - pll_setup_t Setup; - uint32_t rate; - - if ((recompute) || (s_Pll1_Freq == 0U)) - { - Setup.pllctrl = SYSCON->PLL1CTRL; - Setup.pllndec = SYSCON->PLL1NDEC; - Setup.pllpdec = SYSCON->PLL1PDEC; - Setup.pllmdec = SYSCON->PLL1MDEC; - CLOCK_GetPLL1OutFromSetupUpdate(&Setup); - } - - rate = s_Pll1_Freq; - - return rate; -} - -/* Set PLL0 output based on the passed PLL setup data */ -/*! brief Set PLL output based on the passed PLL setup data - * param pControl : Pointer to populated PLL control structure to generate setup with - * param pSetup : Pointer to PLL setup structure to be filled - * return PLL_ERROR_SUCCESS on success, or PLL setup error code - * note Actual frequency for setup may vary from the desired frequency based on the - * accuracy of input clocks, rounding, non-fractional PLL mode, etc. - */ -pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup) -{ - uint32_t inRate; - bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0UL); - - pll_error_t pllError; - - /* Determine input rate for the PLL */ - if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0UL) - { - inRate = pControl->inputRate; - } - else - { - inRate = CLOCK_GetPLL0InClockRate(); - } - - /* PLL flag options */ - pllError = CLOCK_GetPll0Config(inRate, pControl->desiredRate, pSetup, useSS); - if ((useSS) && (pllError == kStatus_PLL_Success)) - { - /* If using SS mode, then some tweaks are made to the generated setup */ - pSetup->pllsscg[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc; - if (pControl->mfDither) - { - pSetup->pllsscg[1] |= (1UL << SYSCON_PLL0SSCG1_DITHER_SHIFT); - } - } - - return pllError; -} - -/* Set PLL0 output from PLL setup structure */ -/*! brief Set PLL output from PLL setup structure (precise frequency) - * param pSetup : Pointer to populated PLL setup structure - * param flagcfg : Flag configuration for PLL config structure - * return PLL_ERROR_SUCCESS on success, or PLL setup error code - * note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg) -{ - uint32_t inRate, clkRate, prediv; - - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_PLL0); - POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); - - pSetup->flags = flagcfg; - - /* Write PLL setup data */ - SYSCON->PLL0CTRL = pSetup->pllctrl; - SYSCON->PLL0NDEC = pSetup->pllndec; - SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ - SYSCON->PLL0PDEC = pSetup->pllpdec; - SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ - SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; - SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; - SYSCON->PLL0SSCG1 = - pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT); /* latch */ - - POWER_DisablePD(kPDRUNCFG_PD_PLL0); - POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); - - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0UL) - { - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ - { - inRate = CLOCK_GetPLL0InClockRate(); - prediv = findPll0PreDiv(); - /* Adjust input clock */ - clkRate = inRate / prediv; - /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ - if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) - { - while (CLOCK_IsPLL0Locked() == false) - { - } - } - else - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval - to insure the PLL will be stable */ - } - } - else /* spread spectrum mode */ - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to - insure the PLL will be stable */ - } - } - - /* Update current programmed PLL rate var */ - CLOCK_GetPLL0OutFromSetupUpdate(pSetup); - - /* System voltage adjustment, occurs prior to setting main system clock */ - if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0UL) - { - POWER_SetVoltageForFreq(s_Pll0_Freq); - } - - return kStatus_PLL_Success; -} - -/* Setup PLL Frequency from pre-calculated value */ -/** - * brief Set PLL0 output from PLL setup structure (precise frequency) - * param pSetup : Pointer to populated PLL setup structure - * return kStatus_PLL_Success on success, or PLL setup error code - * note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup) -{ - uint32_t inRate, clkRate, prediv; - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_PLL0); - POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); - - /* Write PLL setup data */ - SYSCON->PLL0CTRL = pSetup->pllctrl; - SYSCON->PLL0NDEC = pSetup->pllndec; - SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ - SYSCON->PLL0PDEC = pSetup->pllpdec; - SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ - SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; - SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; - SYSCON->PLL0SSCG1 = - pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* latch */ - - POWER_DisablePD(kPDRUNCFG_PD_PLL0); - POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); - - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0UL) - { - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ - { - inRate = CLOCK_GetPLL0InClockRate(); - prediv = findPll0PreDiv(); - /* Adjust input clock */ - clkRate = inRate / prediv; - /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ - if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) - { - while (CLOCK_IsPLL0Locked() == false) - { - } - } - else - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval - to insure the PLL will be stable */ - } - } - else /* spread spectrum mode */ - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to - insure the PLL will be stable */ - } - } - - /* Update current programmed PLL rate var */ - s_Pll0_Freq = pSetup->pllRate; - - return kStatus_PLL_Success; -} - -/* Setup PLL1 Frequency from pre-calculated value */ -/** - * brief Set PLL1 output from PLL setup structure (precise frequency) - * param pSetup : Pointer to populated PLL setup structure - * return kStatus_PLL_Success on success, or PLL setup error code - * note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup) -{ - uint32_t inRate, clkRate, prediv; - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_PLL1); - - /* Write PLL setup data */ - SYSCON->PLL1CTRL = pSetup->pllctrl; - SYSCON->PLL1NDEC = pSetup->pllndec; - SYSCON->PLL1NDEC = pSetup->pllndec | (1UL << SYSCON_PLL1NDEC_NREQ_SHIFT); /* latch */ - SYSCON->PLL1PDEC = pSetup->pllpdec; - SYSCON->PLL1PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL1PDEC_PREQ_SHIFT); /* latch */ - SYSCON->PLL1MDEC = pSetup->pllmdec; - SYSCON->PLL1MDEC = pSetup->pllmdec | (1UL << SYSCON_PLL1MDEC_MREQ_SHIFT); /* latch */ - - POWER_DisablePD(kPDRUNCFG_PD_PLL1); - - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0UL) - { - inRate = CLOCK_GetPLL1InClockRate(); - prediv = findPll1PreDiv(); - /* Adjust input clock */ - clkRate = inRate / prediv; - /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ - if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) - { - while (CLOCK_IsPLL1Locked() == false) - { - } - } - else - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to - insure the PLL will be stable */ - } - } - - /* Update current programmed PLL rate var */ - s_Pll1_Freq = pSetup->pllRate; - - return kStatus_PLL_Success; -} - -/* Set PLL0 clock based on the input frequency and multiplier */ -/*! brief Set PLL0 output based on the multiplier and input frequency - * param multiply_by : multiplier - * param input_freq : Clock input frequency of the PLL - * return Nothing - * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this - * function does not disable or enable PLL power, wait for PLL lock, - * or adjust system voltages. These must be done in the application. - * The function will not alter any source clocks (ie, main systen clock) - * that may use the PLL, so these should be setup prior to and after - * exiting the function. - */ -void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq) -{ - uint32_t cco_freq = input_freq * multiply_by; - uint32_t pdec = 1U; - uint32_t selr; - uint32_t seli; - uint32_t selp; - uint32_t mdec, ndec; - - while (cco_freq < 275000000U) - { - multiply_by <<= 1U; /* double value in each iteration */ - pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */ - cco_freq = input_freq * multiply_by; - } - - selr = 0U; - - if (multiply_by >= 8000UL) - { - seli = 1UL; - } - else if (multiply_by >= 122UL) - { - seli = (uint32_t)(8000UL / multiply_by); /*floor(8000/M) */ - } - else - { - seli = 2UL * ((uint32_t)(multiply_by / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ - } - - if (seli >= 63U) - { - seli = 63U; - } - - { - selp = 31U; - } - - if (pdec > 1U) - { - pdec = pdec / 2U; /* Account for minus 1 encoding */ - /* Translate P value */ - } - - mdec = (uint32_t)PLL_SSCG1_MDEC_VAL_SET(multiply_by); - ndec = 0x1U; /* pre divide by 1 (hardcoded) */ - - SYSCON->PLL0CTRL = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_BYPASSPOSTDIV(0) | - SYSCON_PLL0CTRL_BYPASSPOSTDIV2(0) | (selr << SYSCON_PLL0CTRL_SELR_SHIFT) | - (seli << SYSCON_PLL0CTRL_SELI_SHIFT) | (selp << SYSCON_PLL0CTRL_SELP_SHIFT); - SYSCON->PLL0PDEC = pdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* set Pdec value and assert preq */ - SYSCON->PLL0NDEC = ndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* set Pdec value and assert preq */ - SYSCON->PLL0SSCG1 = - mdec | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* select non sscg MDEC value, assert mreq and select mdec value */ -} - -/* Enable USB DEVICE FULL SPEED clock */ -/*! brief Enable USB Device FS clock. - * param src : clock source - * param freq: clock frequency - * Enable USB Device Full Speed clock. - */ -bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq) -{ - bool ret = true; - - CLOCK_DisableClock(kCLOCK_Usbd0); - - if (kCLOCK_UsbfsSrcFro == src) - { - switch (freq) - { - case 96000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ - break; - - default: - ret = false; - break; - } - /* Turn ON FRO HF */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); - /* Enable FRO 96MHz output */ - ANACTRL->FRO192M_CTRL = - ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK | ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK; - /* Select FRO 96 or 48 MHz */ - CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); - } - else - { - /*!< Configure XTAL32M */ - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ - (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ - - /*!< Set up PLL1 */ - POWER_DisablePD(kPDRUNCFG_PD_PLL1); - CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ - const pll_setup_t pll1Setup = { - .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U), - .pllndec = SYSCON_PLL1NDEC_NDIV(1U), - .pllpdec = SYSCON_PLL1PDEC_PDIV(5U), - .pllmdec = SYSCON_PLL1MDEC_MDIV(30U), - .pllRate = 48000000U, - .flags = PLL_SETUPFLAG_WAITLOCK}; - (void)CLOCK_SetPLL1Freq(&pll1Setup); - - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); - CLOCK_AttachClk(kPLL1_to_USB0_CLK); - SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - } - CLOCK_EnableClock(kCLOCK_Usbd0); - CLOCK_EnableClock(kCLOCK_UsbRam1); - - return ret; -} - -/* Enable USB HOST FULL SPEED clock */ -/*! brief Enable USB HOST FS clock. - * param src : clock source - * param freq: clock frequency - * Enable USB HOST Full Speed clock. - */ -bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq) -{ - bool ret = true; - - CLOCK_DisableClock(kCLOCK_Usbhmr0); - CLOCK_DisableClock(kCLOCK_Usbhsl0); - - if (kCLOCK_UsbfsSrcFro == src) - { - switch (freq) - { - case 96000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ - break; - - default: - ret = false; - break; - } - /* Turn ON FRO HF */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); - /* Enable FRO 96MHz output */ - ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; - /* Select FRO 96 MHz */ - CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); - } - else - { - /*!< Configure XTAL32M */ - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ - (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ - - /*!< Set up PLL1 */ - POWER_DisablePD(kPDRUNCFG_PD_PLL1); - CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ - const pll_setup_t pll1Setup = { - .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U), - .pllndec = SYSCON_PLL1NDEC_NDIV(1U), - .pllpdec = SYSCON_PLL1PDEC_PDIV(5U), - .pllmdec = SYSCON_PLL1MDEC_MDIV(30U), - .pllRate = 48000000U, - .flags = PLL_SETUPFLAG_WAITLOCK}; - (void)CLOCK_SetPLL1Freq(&pll1Setup); - - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); - CLOCK_AttachClk(kPLL1_to_USB0_CLK); - SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - } - CLOCK_EnableClock(kCLOCK_Usbhmr0); - CLOCK_EnableClock(kCLOCK_Usbhsl0); - CLOCK_EnableClock(kCLOCK_UsbRam1); - - return ret; -} - -/* Enable USB PHY clock */ -bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) -{ - volatile uint32_t i; - uint32_t phyPllDiv = 0U; - uint16_t multiplier = 0U; - - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); - POWER_DisablePD(kPDRUNCFG_PD_FRO32K); /*!< Ensure FRO32k is on */ - POWER_DisablePD(kPDRUNCFG_PD_XTAL32K); /*!< Ensure xtal32k is on */ - POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /*!< Ensure xtal32k is on */ - POWER_DisablePD(kPDRUNCFG_PD_LDOUSBHS); /*!< Ensure xtal32k is on */ - - /* wait to make sure PHY power is fully up */ - i = 100000U; - while ((i--) != 0U) - { - __ASM("nop"); - } - - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL(1); - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_PHY(1); - - USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; - - multiplier = 480000000 / freq; - - switch (multiplier) - { - case 15: - { - phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(0U); - break; - } - case 16: - { - phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(1U); - break; - } - case 20: - { - phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(2U); - break; - } - case 24: - { - phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(4U); - break; - } - case 25: - { - phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(5U); - break; - } - case 30: - { - phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(6U); - break; - } - default: - { - return false; - } - } - USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | phyPllDiv; - USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK; - USBPHY->PLL_SIC_CLR = (1UL << 16U); // Reserved. User must set this bit to 0x0 - USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_POWER_MASK; - USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK; - - USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; - USBPHY->PWD_SET = 0x0; - - return true; -} - -/* Enable USB DEVICE HIGH SPEED clock */ -bool CLOCK_EnableUsbhs0DeviceClock(clock_usbhs_src_t src, uint32_t freq) -{ - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1); - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_DEV(1); - - /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1); - return true; -} - -/* Enable USB HOST HIGH SPEED clock */ -bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq) -{ - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1); - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_HOST(1); - - /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1); - - return true; -} - -/*! @brief Enable the OSTIMER 32k clock. - * @return Nothing - */ -void CLOCK_EnableOstimer32kClock(void) -{ - PMC->OSTIMERr |= PMC_OSTIMER_CLOCKENABLE_MASK; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_clock.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_clock.h deleted file mode 100644 index d28d8b21a3d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_clock.h +++ /dev/null @@ -1,1525 +0,0 @@ -/* - * Copyright 2017 - 2021 , NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CLOCK_H_ -#define _FSL_CLOCK_H_ - -#include "fsl_common.h" - -/*! @addtogroup clock */ -/*! @{ */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CLOCK driver version 2.3.7. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 7)) -/*@}*/ - -/*! @brief Configure whether driver controls clock - * - * When set to 0, peripheral drivers will enable clock in initialize function - * and disable clock in de-initialize function. When set to 1, peripheral - * driver will not control the clock, application could control the clock out of - * the driver. - * - * @note All drivers share this feature switcher. If it is set to 1, application - * should handle clock enable and disable for all drivers. - */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) -#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 -#endif - -/*! - * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. - * - * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function - * would cache the recent calulation and accelerate the execution to get the - * right settings. - */ -#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT -#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U -#endif - -/* Definition for delay API in clock driver, users can redefine it to the real application. */ -#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY -#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (100000000UL) -#endif - -/*! @brief Clock ip name array for ROM. */ -#define ROM_CLOCKS \ - { \ - kCLOCK_Rom \ - } -/*! @brief Clock ip name array for SRAM. */ -#define SRAM_CLOCKS \ - { \ - kCLOCK_Sram1, kCLOCK_Sram2 \ - } -/*! @brief Clock ip name array for FLASH. */ -#define FLASH_CLOCKS \ - { \ - kCLOCK_Flash \ - } -/*! @brief Clock ip name array for FMC. */ -#define FMC_CLOCKS \ - { \ - kCLOCK_Fmc \ - } -/*! @brief Clock ip name array for INPUTMUX. */ -#define INPUTMUX_CLOCKS \ - { \ - kCLOCK_InputMux0 \ - } -/*! @brief Clock ip name array for IOCON. */ -#define IOCON_CLOCKS \ - { \ - kCLOCK_Iocon \ - } -/*! @brief Clock ip name array for GPIO. */ -#define GPIO_CLOCKS \ - { \ - kCLOCK_Gpio0, kCLOCK_Gpio1 \ - } -/*! @brief Clock ip name array for PINT. */ -#define PINT_CLOCKS \ - { \ - kCLOCK_Pint \ - } -/*! @brief Clock ip name array for GINT. */ -#define GINT_CLOCKS \ - { \ - kCLOCK_Gint, kCLOCK_Gint \ - } -/*! @brief Clock ip name array for DMA. */ -#define DMA_CLOCKS \ - { \ - kCLOCK_Dma0, kCLOCK_Dma1 \ - } -/*! @brief Clock ip name array for CRC. */ -#define CRC_CLOCKS \ - { \ - kCLOCK_Crc \ - } -/*! @brief Clock ip name array for WWDT. */ -#define WWDT_CLOCKS \ - { \ - kCLOCK_Wwdt \ - } -/*! @brief Clock ip name array for RTC. */ -#define RTC_CLOCKS \ - { \ - kCLOCK_Rtc \ - } -/*! @brief Clock ip name array for Mailbox. */ -#define MAILBOX_CLOCKS \ - { \ - kCLOCK_Mailbox \ - } -/*! @brief Clock ip name array for LPADC. */ -#define LPADC_CLOCKS \ - { \ - kCLOCK_Adc0 \ - } -/*! @brief Clock ip name array for MRT. */ -#define MRT_CLOCKS \ - { \ - kCLOCK_Mrt \ - } -/*! @brief Clock ip name array for OSTIMER. */ -#define OSTIMER_CLOCKS \ - { \ - kCLOCK_OsTimer0 \ - } -/*! @brief Clock ip name array for SCT0. */ -#define SCT_CLOCKS \ - { \ - kCLOCK_Sct0 \ - } -/*! @brief Clock ip name array for MCAN. */ -#define MCAN_CLOCKS \ - { \ - kCLOCK_Mcan \ - } -/*! @brief Clock ip name array for UTICK. */ -#define UTICK_CLOCKS \ - { \ - kCLOCK_Utick0 \ - } -/*! @brief Clock ip name array for FLEXCOMM. */ -#define FLEXCOMM_CLOCKS \ - { \ - kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \ - kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi \ - } -/*! @brief Clock ip name array for LPUART. */ -#define LPUART_CLOCKS \ - { \ - kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \ - kCLOCK_MinUart6, kCLOCK_MinUart7 \ - } - -/*! @brief Clock ip name array for BI2C. */ -#define BI2C_CLOCKS \ - { \ - kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \ - } -/*! @brief Clock ip name array for LSPI. */ -#define LPSPI_CLOCKS \ - { \ - kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \ - } -/*! @brief Clock ip name array for FLEXI2S. */ -#define FLEXI2S_CLOCKS \ - { \ - kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \ - kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \ - } -/*! @brief Clock ip name array for CTIMER. */ -#define CTIMER_CLOCKS \ - { \ - kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ - } -/*! @brief Clock ip name array for EZHA */ -#define EZHA_CLOCKS \ - { \ - kCLOCK_Ezha \ - } -/*! @brief Clock ip name array for EZHB */ -#define EZHB_CLOCKS \ - { \ - kCLOCK_Ezhb \ - } -/*! @brief Clock ip name array for COMP */ -#define COMP_CLOCKS \ - { \ - kCLOCK_Comp \ - } -/*! @brief Clock ip name array for USB1CLK. */ -#define USB1CLK_CLOCKS \ - { \ - kCLOCK_Usb1Clk \ - } -/*! @brief Clock ip name array for FREQME. */ -#define FREQME_CLOCKS \ - { \ - kCLOCK_Freqme \ - } -/*! @brief Clock ip name array for USBRAM. */ -#define USBRAM_CLOCKS \ - { \ - kCLOCK_UsbRam1 \ - } -/*! @brief Clock ip name array for CDOG. */ -#define CDOG_CLOCKS \ - { \ - kCLOCK_Cdog \ - } -/*! @brief Clock ip name array for RNG. */ -#define RNG_CLOCKS \ - { \ - kCLOCK_Rng \ - } -/*! @brief Clock ip name array for USBHMR0. */ -#define USBHMR0_CLOCKS \ - { \ - kCLOCK_Usbhmr0 \ - } -/*! @brief Clock ip name array for USBHSL0. */ -#define USBHSL0_CLOCKS \ - { \ - kCLOCK_Usbhsl0 \ - } -/*! @brief Clock ip name array for HashCrypt. */ -#define HASHCRYPT_CLOCKS \ - { \ - kCLOCK_HashCrypt \ - } -/*! @brief Clock ip name array for PLULUT. */ -#define PLULUT_CLOCKS \ - { \ - kCLOCK_PluLut \ - } -/*! @brief Clock ip name array for PUF. */ -#define PUF_CLOCKS \ - { \ - kCLOCK_Puf \ - } -/*! @brief Clock ip name array for CASPER. */ -#define CASPER_CLOCKS \ - { \ - kCLOCK_Casper \ - } -/*! @brief Clock ip name array for ANALOGCTRL. */ -#define ANALOGCTRL_CLOCKS \ - { \ - kCLOCK_AnalogCtrl \ - } -/*! @brief Clock ip name array for HS_LSPI. */ -#define HS_LSPI_CLOCKS \ - { \ - kCLOCK_Hs_Lspi \ - } -/*! @brief Clock ip name array for GPIO_SEC. */ -#define GPIO_SEC_CLOCKS \ - { \ - kCLOCK_Gpio_Sec \ - } -/*! @brief Clock ip name array for GPIO_SEC_INT. */ -#define GPIO_SEC_INT_CLOCKS \ - { \ - kCLOCK_Gpio_Sec_Int \ - } -/*! @brief Clock ip name array for USBD. */ -#define USBD_CLOCKS \ - { \ - kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \ - } -/*! @brief Clock ip name array for USBH. */ -#define USBH_CLOCKS \ - { \ - kCLOCK_Usbh1 \ - } -#define PLU_CLOCKS \ - { \ - kCLOCK_PluLut \ - } -#define SYSCTL_CLOCKS \ - { \ - kCLOCK_Sysctl \ - } -/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ -/*------------------------------------------------------------------------------ - clock_ip_name_t definition: -------------------------------------------------------------------------------*/ - -#define CLK_GATE_REG_OFFSET_SHIFT 8U -#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U -#define CLK_GATE_BIT_SHIFT_SHIFT 0U -#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU - -#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ - ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ - (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) - -#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) -#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) - -#define AHB_CLK_CTRL0 0 -#define AHB_CLK_CTRL1 1 -#define AHB_CLK_CTRL2 2 - -/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ -typedef enum _clock_ip_name -{ - kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */ - kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /*!< Clock gate name: Rom. */ - - kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /*!< Clock gate name: Sram1. */ - - kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /*!< Clock gate name: Sram2. */ - - kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /*!< Clock gate name: Flash. */ - - kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /*!< Clock gate name: Fmc. */ - - kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /*!< Clock gate name: InputMux. */ - - kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Iocon. */ - - kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Gpio0. */ - - kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Gpio1. */ - - kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), /*!< Clock gate name: Pint. */ - - kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gint. */ - - kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Dma0. */ - - kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Crc. */ - - kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Wwdt. */ - - kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Rtc. */ - - kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), /*!< Clock gate name: Mailbox. */ - - kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), /*!< Clock gate name: Adc0. */ - - kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), /*!< Clock gate name: Mrt. */ - - kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), /*!< Clock gate name: OsTimer0. */ - - kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), /*!< Clock gate name: Sct0. */ - - kCLOCK_Mcan = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7), /*!< Clock gate name: Mcan. */ - - kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), /*!< Clock gate name: Utick0. */ - - kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexComm0. */ - - kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexComm1. */ - - kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexComm2. */ - - kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexComm3. */ - - kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexComm4. */ - - kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexComm5. */ - - kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexComm6. */ - - kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexComm7. */ - - kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: MinUart0. */ - - kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: MinUart1. */ - - kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: MinUart2. */ - - kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: MinUart3. */ - - kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: MinUart4. */ - - kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: MinUart5. */ - - kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: MinUart6. */ - - kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: MinUart7. */ - - kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LSpi0. */ - - kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LSpi1. */ - - kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LSpi2. */ - - kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LSpi3. */ - - kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LSpi4. */ - - kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LSpi5. */ - - kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LSpi6. */ - - kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LSpi7. */ - - kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: BI2c0. */ - - kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: BI2c1. */ - - kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: BI2c2. */ - - kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: BI2c3. */ - - kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: BI2c4. */ - - kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: BI2c5. */ - - kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: BI2c6. */ - - kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: BI2c7. */ - - kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexI2s0. */ - - kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexI2s1. */ - - kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexI2s2. */ - - kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexI2s3. */ - - kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexI2s4. */ - - kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexI2s5. */ - - kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexI2s6. */ - - kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexI2s7. */ - - kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), /*!< Clock gate name: Timer2. */ - - kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), /*!< Clock gate name: Usbd0. */ - - kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), /*!< Clock gate name: Timer0. */ - - kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), /*!< Clock gate name: Timer1. */ - - kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30), /*!< Clock gate name: Ezha. */ - - kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), /*!< Clock gate name: Ezhb. */ - - kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), /*!< Clock gate name: Dma1. */ - - kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), /*!< Clock gate name: Comp. */ - - kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), /*!< Clock gate name: Usbh1. */ - - kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), /*!< Clock gate name: Usbd1. */ - - kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), /*!< Clock gate name: UsbRam1. */ - - kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), /*!< Clock gate name: Usb1Clk. */ - - kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), /*!< Clock gate name: Freqme. */ - - kCLOCK_Cdog = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11), /*!< Clock gate name: Cdog. */ - - kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), /*!< Clock gate name: Rng. */ - - kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: Sysctl. */ - - kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), /*!< Clock gate name: Usbhmr0. */ - - kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), /*!< Clock gate name: Usbhsl0. */ - - kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), /*!< Clock gate name: HashCrypt. */ - - kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), /*!< Clock gate name: PluLut. */ - - kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), /*!< Clock gate name: Timer3. */ - - kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), /*!< Clock gate name: Timer4. */ - - kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), /*!< Clock gate name: Puf. */ - - kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), /*!< Clock gate name: Casper. */ - - kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27), /*!< Clock gate name: AnalogCtrl. */ - - kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28), /*!< Clock gate name: Lspi. */ - - kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), /*!< Clock gate name: GPIO Sec. */ - - kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30) /*!< Clock gate name: GPIO SEC Int. */ -} clock_ip_name_t; - -/*! @brief Peripherals clock source definition. */ -#define BUS_CLK kCLOCK_BusClk - -#define I2C0_CLK_SRC BUS_CLK - -/*! @brief Clock name used to get clock frequency. */ -typedef enum _clock_name -{ - kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ - kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ - kCLOCK_ClockOut, /*!< CLOCKOUT */ - kCLOCK_FroHf, /*!< FRO48/96 */ - kCLOCK_Pll1Out, /*!< PLL1 Output */ - kCLOCK_Mclk, /*!< MCLK */ - kCLOCK_Fro12M, /*!< FRO12M */ - kCLOCK_Fro1M, /*!< FRO1M */ - kCLOCK_ExtClk, /*!< External Clock */ - kCLOCK_Pll0Out, /*!< PLL0 Output */ - kCLOCK_FlexI2S, /*!< FlexI2S clock */ - -} clock_name_t; - -/*! @brief Clock Mux Switches - * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable - * starting from LSB upwards - * - * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* - * - */ - -#define CLK_ATTACH_ID(mux, sel, pos) \ - ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((uint32_t)(pos)*12U)) -#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U) -#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U)) - -#define GET_ID_ITEM(connection) ((connection)&0xFFFU) -#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U) -#define GET_ID_ITEM_MUX(connection) (((uint8_t)connection) & 0xFFU) -#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF00U) >> 8U) - 1U)) -#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) - -#define CM_SYSTICKCLKSEL0 0 -#define CM_TRACECLKSEL 2 -#define CM_CTIMERCLKSEL0 3 -#define CM_CTIMERCLKSEL1 4 -#define CM_CTIMERCLKSEL2 5 -#define CM_CTIMERCLKSEL3 6 -#define CM_CTIMERCLKSEL4 7 -#define CM_MAINCLKSELA 8 -#define CM_MAINCLKSELB 9 -#define CM_CLKOUTCLKSEL 10 -#define CM_PLL0CLKSEL 12 -#define CM_PLL1CLKSEL 13 -#define CM_MCANCLKSEL 16 -#define CM_ADCASYNCCLKSEL 17 -#define CM_USB0CLKSEL 18 -#define CM_CLK32KCLKSEL 19 -#define CM_FXCOMCLKSEL0 20 -#define CM_FXCOMCLKSEL1 21 -#define CM_FXCOMCLKSEL2 22 -#define CM_FXCOMCLKSEL3 23 -#define CM_FXCOMCLKSEL4 24 -#define CM_FXCOMCLKSEL5 25 -#define CM_FXCOMCLKSEL6 26 -#define CM_FXCOMCLKSEL7 27 -#define CM_HSLSPICLKSEL 28 -#define CM_MCLKCLKSEL 32 -#define CM_SCTCLKSEL 36 - -#define CM_OSTIMERCLKSEL (62U) -#define CM_RTCOSC32KCLKSEL 63U - -/*! - * @brief The enumerator of clock attach Id. - */ -typedef enum _clock_attach_id -{ - - kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO12M to MAIN_CLK. */ - - kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach EXT_CLK to MAIN_CLK. */ - - kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO1M to MAIN_CLK. */ - - kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO_HF to MAIN_CLK. */ - - kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0), /*!< Attach PLL0 to MAIN_CLK. */ - - kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), /*!< Attach PLL1 to MAIN_CLK. */ - - kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), /*!< Attach OSC32K to MAIN_CLK. */ - - kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Attach MAIN_CLK to CLKOUT. */ - - kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Attach PLL0 to CLKOUT. */ - - kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Attach EXT_CLK to CLKOUT. */ - - kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Attach FRO_HF to CLKOUT. */ - - kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Attach FRO1M to CLKOUT. */ - - kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Attach PLL1 to CLKOUT. */ - - kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Attach OSC32K to CLKOUT. */ - - kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< Attach NONE to SYS_CLKOUT. */ - - kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0), /*!< Attach FRO12M to PLL0. */ - - kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1), /*!< Attach EXT_CLK to PLL0. */ - - kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2), /*!< Attach FRO1M to PLL0. */ - - kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3), /*!< Attach OSC32K to PLL0. */ - - kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7), /*!< Attach NONE to PLL0. */ - - kMCAN_DIV_to_MCAN = MUX_A(CM_MCANCLKSEL, 0), /*!< Attach MCAN_DIV to MCAN. */ - - kFRO1M_to_MCAN = MUX_A(CM_MCANCLKSEL, 1), /*!< Attach FRO1M to MCAN. */ - - kOSC32K_to_MCAN = MUX_A(CM_MCANCLKSEL, 2), /*!< Attach OSC32K to MCAN. */ - - kNONE_to_MCAN = MUX_A(CM_MCANCLKSEL, 7), /*!< Attach NONE to MCAN. */ - - kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), /*!< Attach MAIN_CLK to ADC_CLK. */ - - kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), /*!< Attach PLL0 to ADC_CLK. */ - - kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), /*!< Attach FRO_HF to ADC_CLK. */ - - kEXT_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 4), /*!< Attach EXT_CLK to ADC_CLK. */ - - kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), /*!< Attach NONE to ADC_CLK. */ - - kMAIN_CLK_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0), /*!< Attach MAIN_CLK to USB0_CLK. */ - - kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1), /*!< Attach PLL0 to USB0_CLK. */ - - kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3), /*!< Attach FRO_HF to USB0_CLK. */ - - kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5), /*!< Attach PLL1 to USB0_CLK. */ - - kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7), /*!< Attach NONE to USB0_CLK. */ - - kOSC32K_to_CLK32K = MUX_A(CM_CLK32KCLKSEL, 0), /*!< Attach OSC32K to CLK32K. */ - - kFRO1MDIV_to_CLK32K = MUX_A(CM_CLK32KCLKSEL, 1), /*!< Attach FRO1MDIV to CLK32K. */ - - kNONE_to_CLK32K = MUX_A(CM_CLK32KCLKSEL, 7), /*!< Attach NONE to CLK32K. */ - - kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), /*!< Attach MAIN_CLK to FLEXCOMM0. */ - - kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), /*!< Attach PLL0_DIV to FLEXCOMM0. */ - - kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), /*!< Attach FRO12M to FLEXCOMM0. */ - - kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM0. */ - - kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), /*!< Attach FRO1M to FLEXCOMM0. */ - - kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5), /*!< Attach MCLK to FLEXCOMM0. */ - - kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6), /*!< Attach OSC32K to FLEXCOMM0. */ - - kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */ - - kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), /*!< Attach MAIN_CLK to FLEXCOMM1. */ - - kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), /*!< Attach PLL0_DIV to FLEXCOMM1. */ - - kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), /*!< Attach FRO12M to FLEXCOMM1. */ - - kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM1. */ - - kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), /*!< Attach FRO1M to FLEXCOMM1. */ - - kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5), /*!< Attach MCLK to FLEXCOMM1. */ - - kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6), /*!< Attach OSC32K to FLEXCOMM1. */ - - kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */ - - kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), /*!< Attach MAIN_CLK to FLEXCOMM2. */ - - kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), /*!< Attach PLL0_DIV to FLEXCOMM2. */ - - kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), /*!< Attach FRO12M to FLEXCOMM2. */ - - kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM2. */ - - kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), /*!< Attach FRO1M to FLEXCOMM2. */ - - kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5), /*!< Attach MCLK to FLEXCOMM2. */ - - kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6), /*!< Attach OSC32K to FLEXCOMM2. */ - - kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */ - - kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), /*!< Attach MAIN_CLK to FLEXCOMM3. */ - - kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), /*!< Attach PLL0_DIV to FLEXCOMM3. */ - - kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), /*!< Attach FRO12M to FLEXCOMM3. */ - - kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM3. */ - - kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), /*!< Attach FRO1M to FLEXCOMM3. */ - - kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5), /*!< Attach MCLK to FLEXCOMM3. */ - - kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6), /*!< Attach OSC32K to FLEXCOMM3. */ - - kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */ - - kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), /*!< Attach MAIN_CLK to FLEXCOMM4. */ - - kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), /*!< Attach PLL0_DIV to FLEXCOMM4. */ - - kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), /*!< Attach FRO12M to FLEXCOMM4. */ - - kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM4. */ - - kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), /*!< Attach FRO1M to FLEXCOMM4. */ - - kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5), /*!< Attach MCLK to FLEXCOMM4. */ - - kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6), /*!< Attach OSC32K to FLEXCOMM4. */ - - kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */ - - kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), /*!< Attach MAIN_CLK to FLEXCOMM5. */ - - kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), /*!< Attach PLL0_DIV to FLEXCOMM5. */ - - kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), /*!< Attach FRO12M to FLEXCOMM5. */ - - kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM5. */ - - kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), /*!< Attach FRO1M to FLEXCOMM5. */ - - kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5), /*!< Attach MCLK to FLEXCOMM5. */ - - kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6), /*!< Attach OSC32K to FLEXCOMM5. */ - - kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */ - - kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), /*!< Attach MAIN_CLK to FLEXCOMM6. */ - - kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), /*!< Attach PLL0_DIV to FLEXCOMM6. */ - - kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), /*!< Attach FRO12M to FLEXCOMM6. */ - - kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM6. */ - - kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), /*!< Attach FRO1M to FLEXCOMM6. */ - - kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5), /*!< Attach MCLK to FLEXCOMM6. */ - - kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6), /*!< Attach OSC32K to FLEXCOMM6. */ - - kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */ - - kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), /*!< Attach MAIN_CLK to FLEXCOMM7. */ - - kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), /*!< Attach PLL0_DIV to FLEXCOMM7. */ - - kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), /*!< Attach FRO12M to FLEXCOMM7. */ - - kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM7. */ - - kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), /*!< Attach FRO1M to FLEXCOMM7. */ - - kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5), /*!< Attach MCLK to FLEXCOMM7. */ - - kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6), /*!< Attach OSC32K to FLEXCOMM7. */ - - kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */ - - kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0), /*!< Attach MAIN_CLK to HSLSPI. */ - - kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1), /*!< Attach PLL0_DIV to HSLSPI. */ - - kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2), /*!< Attach FRO12M to HSLSPI. */ - - kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3), /*!< Attach FRO_HF_DIV to HSLSPI. */ - - kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4), /*!< Attach FRO1M to HSLSPI. */ - - kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6), /*!< Attach OSC32K to HSLSPI. */ - - kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7), /*!< Attach NONE to HSLSPI. */ - - kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), /*!< Attach FRO_HF to MCLK. */ - - kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), /*!< Attach PLL0 to MCLK. */ - - kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), /*!< Attach NONE to MCLK. */ - - kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), /*!< Attach MAIN_CLK to SCT_CLK. */ - - kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), /*!< Attach PLL0 to SCT_CLK. */ - - kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), /*!< Attach EXT_CLK to SCT_CLK. */ - - kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), /*!< Attach FRO_HF to SCT_CLK. */ - - kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5), /*!< Attach MCLK to SCT_CLK. */ - - kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), /*!< Attach NONE to SCT_CLK. */ - - kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0), /*!< Attach FRO32K to OSC32K. */ - - kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1), /*!< Attach XTAL32K to OSC32K. */ - - kOSC32K_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 0), /*!< Attach OSC32K to OSTIMER. */ - - kFRO1M_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 1), /*!< Attach FRO1M to OSTIMER. */ - - kMAIN_CLK_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 2), /*!< Attach MAIN_CLK to OSTIMER. */ - - kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), /*!< Attach TRACE_DIV to TRACE. */ - - kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), /*!< Attach FRO1M to TRACE. */ - - kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), /*!< Attach OSC32K to TRACE. */ - - kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), /*!< Attach NONE to TRACE. */ - - kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), /*!< Attach SYSTICK_DIV0 to SYSTICK0. */ - - kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), /*!< Attach FRO1M to SYSTICK0. */ - - kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), /*!< Attach OSC32K to SYSTICK0. */ - - kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), /*!< Attach NONE to SYSTICK0. */ - - kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0), /*!< Attach FRO12M to PLL1. */ - - kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1), /*!< Attach EXT_CLK to PLL1. */ - - kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2), /*!< Attach FRO1M to PLL1. */ - - kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3), /*!< Attach OSC32K to PLL1. */ - - kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7), /*!< Attach NONE to PLL1. */ - - kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), /*!< Attach MAIN_CLK to CTIMER0. */ - - kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), /*!< Attach PLL0 to CTIMER0. */ - - kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), /*!< Attach FRO_HF to CTIMER0. */ - - kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), /*!< Attach FRO1M to CTIMER0. */ - - kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), /*!< Attach MCLK to CTIMER0. */ - - kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), /*!< Attach OSC32K to CTIMER0. */ - - kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7), /*!< Attach NONE to CTIMER0. */ - - kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), /*!< Attach MAIN_CLK to CTIMER1. */ - - kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), /*!< Attach PLL0 to CTIMER1. */ - - kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), /*!< Attach FRO_HF to CTIMER1. */ - - kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), /*!< Attach FRO1M to CTIMER1. */ - - kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), /*!< Attach MCLK to CTIMER1. */ - - kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), /*!< Attach OSC32K to CTIMER1. */ - - kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7), /*!< Attach NONE to CTIMER1. */ - - kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), /*!< Attach MAIN_CLK to CTIMER2. */ - - kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), /*!< Attach PLL0 to CTIMER2. */ - - kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), /*!< Attach FRO_HF to CTIMER2. */ - - kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), /*!< Attach FRO1M to CTIMER2. */ - - kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), /*!< Attach MCLK to CTIMER2. */ - - kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), /*!< Attach OSC32K to CTIMER2. */ - - kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7), /*!< Attach NONE to CTIMER2. */ - - kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), /*!< Attach MAIN_CLK to CTIMER3. */ - - kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), /*!< Attach PLL0 to CTIMER3. */ - - kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), /*!< Attach FRO_HF to CTIMER3. */ - - kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), /*!< Attach FRO1M to CTIMER3. */ - - kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), /*!< Attach MCLK to CTIMER3. */ - - kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), /*!< Attach OSC32K to CTIMER3. */ - - kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7), /*!< Attach NONE to CTIMER3. */ - - kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), /*!< Attach MAIN_CLK to CTIMER4. */ - - kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), /*!< Attach PLL0 to CTIMER4. */ - - kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), /*!< Attach FRO_HF to CTIMER4. */ - - kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), /*!< Attach FRO1M to CTIMER4. */ - - kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), /*!< Attach MCLK to CTIMER4. */ - - kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), /*!< Attach OSC32K to CTIMER4. */ - - kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7), /*!< Attach NONE to CTIMER4. */ - - kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */ - -} clock_attach_id_t; - -/*! @brief Clock dividers */ -typedef enum _clock_div_name -{ - kCLOCK_DivSystickClk0 = 0, /*!< Systick Clk0 Divider. */ - - kCLOCK_DivArmTrClkDiv = 2, /*!< Arm Tr Clk Div Divider. */ - - kCLOCK_DivCanClk = 3, /*!< Can Clock Divider. */ - - kCLOCK_DivFlexFrg0 = 8, /*!< Flex Frg0 Divider. */ - - kCLOCK_DivFlexFrg1 = 9, /*!< Flex Frg1 Divider. */ - - kCLOCK_DivFlexFrg2 = 10, /*!< Flex Frg2 Divider. */ - - kCLOCK_DivFlexFrg3 = 11, /*!< Flex Frg3 Divider. */ - - kCLOCK_DivFlexFrg4 = 12, /*!< Flex Frg4 Divider. */ - - kCLOCK_DivFlexFrg5 = 13, /*!< Flex Frg5 Divider. */ - - kCLOCK_DivFlexFrg6 = 14, /*!< Flex Frg6 Divider. */ - - kCLOCK_DivFlexFrg7 = 15, /*!< Flex Frg7 Divider. */ - - kCLOCK_DivAhbClk = 32, /*!< Ahb Clock Divider. */ - - kCLOCK_DivClkOut = 33, /*!< Clk Out Divider. */ - - kCLOCK_DivFrohfClk = 34, /*!< Frohf Clock Divider. */ - - kCLOCK_DivWdtClk = 35, /*!< Wdt Clock Divider. */ - - kCLOCK_DivAdcAsyncClk = 37, /*!< Adc Async Clock Divider. */ - - kCLOCK_DivUsb0Clk = 38, /*!< Usb0 Clock Divider. */ - - kCLOCK_DivFro1mClk = 40, /*!< Fro1m Clock Divider. */ - - kCLOCK_DivMClk = 43, /*!< I2S MCLK Clock Divider. */ - - kCLOCK_DivSctClk = 45, /*!< Sct Clock Divider. */ - - kCLOCK_DivPll0Clk = 49 /*!< PLL clock divider. */ -} clock_div_name_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief Enable the clock for specific IP. - * @param clk : Clock to be enabled. - * @return Nothing - */ -static inline void CLOCK_EnableClock(clock_ip_name_t clk) -{ - uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); -} -/** - * @brief Disable the clock for specific IP. - * @param clk : Clock to be Disabled. - * @return Nothing - */ -static inline void CLOCK_DisableClock(clock_ip_name_t clk) -{ - uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); -} -/** - * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). - * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is - * enabled. - * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ) - * @return returns success or fail status. - */ -status_t CLOCK_SetupFROClocking(uint32_t iFreq); -/** - * @brief Set the flash wait states for the input freuqency. - * @param system_freq_hz : Input frequency - * @return Nothing - */ -void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz); -/** - * @brief Initialize the external osc clock to given frequency. - * @param iFreq : Desired frequency (must be equal to exact rate in Hz) - * @return returns success or fail status. - */ -status_t CLOCK_SetupExtClocking(uint32_t iFreq); -/** - * @brief Initialize the I2S MCLK clock to given frequency. - * @param iFreq : Desired frequency (must be equal to exact rate in Hz) - * @return returns success or fail status. - */ -status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq); -/** - * @brief Initialize the PLU CLKIN clock to given frequency. - * @param iFreq : Desired frequency (must be equal to exact rate in Hz) - * @return returns success or fail status. - */ -status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq); -/** - * @brief Configure the clock selection muxes. - * @param connection : Clock to be configured. - * @return Nothing - */ -void CLOCK_AttachClk(clock_attach_id_t connection); -/** - * @brief Get the actual clock attach id. - * This fuction uses the offset in input attach id, then it reads the actual source value in - * the register and combine the offset to obtain an actual attach id. - * @param attachId : Clock attach id to get. - * @return Clock source value. - */ -clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId); -/** - * @brief Setup peripheral clock dividers. - * @param div_name : Clock divider name - * @param divided_by_value: Value to be divided - * @param reset : Whether to reset the divider counter. - * @return Nothing - */ -void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset); -/** - * @brief Setup rtc 1khz clock divider. - * @param divided_by_value: Value to be divided - * @return Nothing - */ -void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value); -/** - * @brief Setup rtc 1hz clock divider. - * @param divided_by_value: Value to be divided - * @return Nothing - */ -void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value); - -/** - * @brief Set the flexcomm output frequency. - * @param id : flexcomm instance id - * @param freq : output frequency - * @return 0 : the frequency range is out of range. - * 1 : switch successfully. - */ -uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq); - -/*! @brief Return Frequency of flexcomm input clock - * @param id : flexcomm instance id - * @return Frequency value - */ -uint32_t CLOCK_GetFlexCommInputClock(uint32_t id); - -/*! @brief Return Frequency of selected clock - * @return Frequency of selected clock - */ -uint32_t CLOCK_GetFreq(clock_name_t clockName); -/*! @brief Return Frequency of FRO 12MHz - * @return Frequency of FRO 12MHz - */ -uint32_t CLOCK_GetFro12MFreq(void); -/*! @brief Return Frequency of FRO 1MHz - * @return Frequency of FRO 1MHz - */ -uint32_t CLOCK_GetFro1MFreq(void); -/*! @brief Return Frequency of ClockOut - * @return Frequency of ClockOut - */ -uint32_t CLOCK_GetClockOutClkFreq(void); -/*! @brief Return Frequency of Can Clock - * @return Frequency of Can. - */ -uint32_t CLOCK_GetMCanClkFreq(void); -/*! @brief Return Frequency of Adc Clock - * @return Frequency of Adc. - */ -uint32_t CLOCK_GetAdcClkFreq(void); -/*! @brief Return Frequency of Usb0 Clock - * @return Frequency of Usb0 Clock. - */ -uint32_t CLOCK_GetUsb0ClkFreq(void); -/*! @brief Return Frequency of Usb1 Clock - * @return Frequency of Usb1 Clock. - */ -uint32_t CLOCK_GetUsb1ClkFreq(void); -/*! @brief Return Frequency of MClk Clock - * @return Frequency of MClk Clock. - */ -uint32_t CLOCK_GetMclkClkFreq(void); -/*! @brief Return Frequency of SCTimer Clock - * @return Frequency of SCTimer Clock. - */ -uint32_t CLOCK_GetSctClkFreq(void); -/*! @brief Return Frequency of External Clock - * @return Frequency of External Clock. If no external clock is used returns 0. - */ -uint32_t CLOCK_GetExtClkFreq(void); -/*! @brief Return Frequency of Watchdog - * @return Frequency of Watchdog - */ -uint32_t CLOCK_GetWdtClkFreq(void); -/*! @brief Return Frequency of High-Freq output of FRO - * @return Frequency of High-Freq output of FRO - */ -uint32_t CLOCK_GetFroHfFreq(void); -/*! @brief Return Frequency of PLL - * @return Frequency of PLL - */ -uint32_t CLOCK_GetPll0OutFreq(void); -/*! @brief Return Frequency of USB PLL - * @return Frequency of PLL - */ -uint32_t CLOCK_GetPll1OutFreq(void); -/*! @brief Return Frequency of 32kHz osc - * @return Frequency of 32kHz osc - */ -uint32_t CLOCK_GetOsc32KFreq(void); -/*! @brief Return Frequency of Core System - * @return Frequency of Core System - */ -uint32_t CLOCK_GetCoreSysClkFreq(void); -/*! @brief Return Frequency of I2S MCLK Clock - * @return Frequency of I2S MCLK Clock - */ -uint32_t CLOCK_GetI2SMClkFreq(void); -/*! @brief Return Frequency of PLU CLKIN Clock - * @return Frequency of PLU CLKIN Clock - */ -uint32_t CLOCK_GetPLUClkInFreq(void); -/*! @brief Return Frequency of FlexComm Clock - * @return Frequency of FlexComm Clock - */ -uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id); -/*! @brief Return Frequency of High speed SPI Clock - * @return Frequency of High speed SPI Clock - */ -uint32_t CLOCK_GetHsLspiClkFreq(void); -/*! @brief Return Frequency of CTimer functional Clock - * @return Frequency of CTimer functional Clock - */ -uint32_t CLOCK_GetCTimerClkFreq(uint32_t id); -/*! @brief Return Frequency of SystickClock - * @return Frequency of Systick Clock - */ -uint32_t CLOCK_GetSystickClkFreq(uint32_t id); - -/*! @brief Return PLL0 input clock rate - * @return PLL0 input clock rate - */ -uint32_t CLOCK_GetPLL0InClockRate(void); - -/*! @brief Return PLL1 input clock rate - * @return PLL1 input clock rate - */ -uint32_t CLOCK_GetPLL1InClockRate(void); - -/*! @brief Return PLL0 output clock rate - * @param recompute : Forces a PLL rate recomputation if true - * @return PLL0 output clock rate - * @note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetPLL0OutClockRate(bool recompute); - -/*! @brief Return PLL1 output clock rate - * @param recompute : Forces a PLL rate recomputation if true - * @return PLL1 output clock rate - * @note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetPLL1OutClockRate(bool recompute); - -/*! @brief Enables and disables PLL0 bypass mode - * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass - * @return PLL0 output clock rate - */ -__STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass) -{ - if (bypass) - { - SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); - } - else - { - SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); - } -} - -/*! @brief Enables and disables PLL1 bypass mode - * @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass - * @return PLL1 output clock rate - */ -__STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass) -{ - if (bypass) - { - SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); - } - else - { - SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); - } -} - -/*! @brief Check if PLL is locked or not - * @return true if the PLL is locked, false if not locked - */ -__STATIC_INLINE bool CLOCK_IsPLL0Locked(void) -{ - return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0UL); -} - -/*! @brief Check if PLL1 is locked or not - * @return true if the PLL1 is locked, false if not locked - */ -__STATIC_INLINE bool CLOCK_IsPLL1Locked(void) -{ - return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0UL); -} - -/*! @brief Store the current PLL0 rate - * @param rate: Current rate of the PLL0 - * @return Nothing - **/ -void CLOCK_SetStoredPLL0ClockRate(uint32_t rate); - -/*! @brief PLL configuration structure flags for 'flags' field - * These flags control how the PLL configuration function sets up the PLL setup structure.
- * - * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the - * configuration structure must be assigned with the expected PLL frequency. If the - * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration - * function and the driver will determine the PLL rate from the currently selected - * PLL source. This flag might be used to configure the PLL input clock more accurately - * when using the WDT oscillator or a more dyanmic CLKIN source.
- * - * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the - * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider - * are not used.
- */ -#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */ -#define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U) -/*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */ - -/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency - * See (MF) field in the PLL0SSCG1 register in the UM. - */ -typedef enum _ss_progmodfm -{ - kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */ - kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */ - kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */ - kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */ - kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */ - kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */ - kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */ - kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */ -} ss_progmodfm_t; - -/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth - * See (MR) field in the PLL0SSCG1 register in the UM. - */ -typedef enum _ss_progmoddp -{ - kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */ - kSS_MR_K1 = (1 << 23), /*!< k = 1 */ - kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */ - kSS_MR_K2 = (3 << 23), /*!< k = 2 */ - kSS_MR_K3 = (4 << 23), /*!< k = 3 */ - kSS_MR_K4 = (5 << 23), /*!< k = 4 */ - kSS_MR_K6 = (6 << 23), /*!< k = 6 */ - kSS_MR_K8 = (7 << 23) /*!< k = 8 */ -} ss_progmoddp_t; - -/*! @brief PLL Spread Spectrum (SS) Modulation waveform control - * See (MC) field in the PLL0SSCG1 register in the UM.
- * Compensation for low pass filtering of the PLL to get a triangular - * modulation at the output of the PLL, giving a flat frequency spectrum. - */ -typedef enum _ss_modwvctrl -{ - kSS_MC_NOC = (0 << 26), /*!< no compensation */ - kSS_MC_RECC = (2 << 26), /*!< recommended setting */ - kSS_MC_MAXC = (3 << 26), /*!< max. compensation */ -} ss_modwvctrl_t; - -/*! @brief PLL configuration structure - * - * This structure can be used to configure the settings for a PLL - * setup structure. Fill in the desired configuration for the PLL - * and call the PLL setup function to fill in a PLL setup structure. - */ -typedef struct _pll_config -{ - uint32_t desiredRate; /*!< Desired PLL rate in Hz */ - uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */ - uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ - ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - ss_modwvctrl_t - ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ - bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - -} pll_config_t; - -/*! @brief PLL setup structure flags for 'flags' field - * These flags control how the PLL setup function sets up the PLL - */ -#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */ -#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ -#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */ -#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */ - -/*! @brief PLL0 setup structure - * This structure can be used to pre-build a PLL setup configuration - * at run-time and quickly set the PLL to the configuration. It can be - * populated with the PLL setup function. If powering up or waiting - * for PLL lock, the PLL input clock source should be configured prior - * to PLL setup. - */ -typedef struct _pll_setup -{ - uint32_t pllctrl; /*!< PLL control register PLL0CTRL */ - uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */ - uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */ - uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */ - uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/ - uint32_t pllRate; /*!< Acutal PLL rate */ - uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ -} pll_setup_t; - -/*! @brief PLL status definitions - */ -typedef enum _pll_error -{ - kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ - kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ - kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ - kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ - kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ - kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */ - kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */ - kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */ -} pll_error_t; - -/*! @brief USB FS clock source definition. */ -typedef enum _clock_usbfs_src -{ - kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 MHz. */ - kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, /*!< Use PLL0 output. */ - kCLOCK_UsbfsSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */ - kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, /*!< Use PLL1 clock. */ - - kCLOCK_UsbfsSrcNone = - SYSCON_USB0CLKSEL_SEL(7) /*!COMP & ~(PMC_COMP_LOWPOWER_MASK | PMC_COMP_HYST_MASK | PMC_COMP_FILTERCGF_CLKDIV_MASK | - PMC_COMP_FILTERCGF_SAMPLEMODE_MASK)); - - if (true == config->enableLowPower) - { - tmpReg |= PMC_COMP_LOWPOWER_MASK; - } - else - { - tmpReg &= ~PMC_COMP_LOWPOWER_MASK; - } - - if (true == config->enableHysteresis) - { - tmpReg |= PMC_COMP_HYST_MASK; - } - else - { - tmpReg &= ~PMC_COMP_HYST_MASK; - } - - tmpReg |= (PMC_COMP_FILTERCGF_CLKDIV(config->filterClockDivider) | - PMC_COMP_FILTERCGF_SAMPLEMODE(config->filterSampleMode)); - - PMC->COMP = tmpReg; -} - -/*! - * @brief CMP deinitialization. - * - * This function gates the clock for CMP module. - */ -void CMP_Deinit(void) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(kCLOCK_Comp); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Initializes the CMP user configuration structure. - * - * This function initializes the user configuration structure to these default values. - * @code - * config->enableHysteresis = true; - * config->enableLowPower = true; - * config->filterClockDivider = kCMP_FilterClockDivide1; - * config->filterSampleMode = kCMP_FilterSampleMode0; - * @endcode - * @param config Pointer to the configuration structure. - */ -void CMP_GetDefaultConfig(cmp_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enableHysteresis = true; - config->enableLowPower = true; - config->filterClockDivider = kCMP_FilterClockDivide1; - config->filterSampleMode = kCMP_FilterSampleMode0; -} - -/*! - * @brief Configures the VREFINPUT. - * - * @param config Pointer to the configuration structure. - */ -void CMP_SetVREF(const cmp_vref_config_t *config) -{ - assert(NULL != config); - assert(config->vrefValue < 32U); - - uint32_t tmpReg = PMC->COMP & ~(PMC_COMP_VREF_MASK | PMC_COMP_VREFINPUT_MASK); - - tmpReg |= PMC_COMP_VREFINPUT(config->vrefSource) | PMC_COMP_VREF(config->vrefValue); - - PMC->COMP = tmpReg; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cmp.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cmp.h deleted file mode 100644 index 1afdc972808..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cmp.h +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Copyright 2018-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __FSL_CMP_H_ -#define __FSL_CMP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup cmp_1 - * @{ - */ - -/****************************************************************************** - * Definitions. - *****************************************************************************/ -/*! @name Driver version */ -/*@{*/ -/*! @brief Driver version 2.2.1. */ -#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 1U)) -/*@}*/ - -/*! @brief CMP input mux for positive and negative sides. */ -enum _cmp_input_mux -{ - kCMP_InputVREF = 0U, /*!< Cmp input from VREF. */ - kCMP_Input1 = 1U, /*!< Cmp input source 1. */ - kCMP_Input2 = 2U, /*!< Cmp input source 2. */ - kCMP_Input3 = 3U, /*!< Cmp input source 3. */ - kCMP_Input4 = 4U, /*!< Cmp input source 4. */ - kCMP_Input5 = 5U, /*!< Cmp input source 5. */ -}; - -/*! @brief CMP interrupt type. */ -enum _cmp_interrupt_type -{ - kCMP_EdgeDisable = 0U, /*!< Disable edge interupt. */ - kCMP_EdgeRising = 2U, /*!< Interrupt on falling edge. */ - kCMP_EdgeFalling = 4U, /*!< Interrupt on rising edge. */ - kCMP_EdgeRisingFalling = 6U, /*!< Interrupt on both rising and falling edges. */ - - kCMP_LevelDisable = 1U, /*!< Disable level interupt. */ - kCMP_LevelHigh = 3U, /*!< Interrupt on high level. */ - kCMP_LevelLow = 5U, /*!< Interrupt on low level. */ -}; - -/*! @brief CMP Voltage Reference source. */ -typedef enum _cmp_vref_source -{ - KCMP_VREFSourceVDDA = 1U, /*!< Select VDDA as VREF. */ - KCMP_VREFSourceInternalVREF = 0U, /*!< Select internal VREF as VREF. */ -} cmp_vref_source_t; - -typedef struct _cmp_vref_config -{ - cmp_vref_source_t vrefSource; /*!< Reference voltage source. */ - uint8_t vrefValue; /*!< Reference voltage step. Available range is 0-31. Per step equals to VREFINPUT/31. */ -} cmp_vref_config_t; - -/*! @brief CMP Filter sample mode. */ -typedef enum _cmp_filtercgf_samplemode -{ - kCMP_FilterSampleMode0 = 0U, /*!< Bypass mode. Filtering is disabled. */ - kCMP_FilterSampleMode1 = 1U, /*!< Filter 1 clock period. */ - kCMP_FilterSampleMode2 = 2U, /*!< Filter 2 clock period. */ - kCMP_FilterSampleMode3 = 3U /*!< Filter 3 clock period. */ -} cmp_filtercgf_samplemode_t; - -/*! @brief CMP Filter clock divider. */ -typedef enum _cmp_filtercgf_clkdiv -{ - kCMP_FilterClockDivide1 = 0U, /*!< Filter clock period duration equals 1 analog comparator clock period. */ - kCMP_FilterClockDivide2 = 1U, /*!< Filter clock period duration equals 2 analog comparator clock period. */ - kCMP_FilterClockDivide4 = 2U, /*!< Filter clock period duration equals 4 analog comparator clock period. */ - kCMP_FilterClockDivide8 = 3U, /*!< Filter clock period duration equals 8 analog comparator clock period. */ - kCMP_FilterClockDivide16 = 4U, /*!< Filter clock period duration equals 16 analog comparator clock period. */ - kCMP_FilterClockDivide32 = 5U, /*!< Filter clock period duration equals 32 analog comparator clock period. */ - kCMP_FilterClockDivide64 = 6U /*!< Filter clock period duration equals 64 analog comparator clock period. */ -} cmp_filtercgf_clkdiv_t; - -/*! @brief CMP configuration structure. */ -typedef struct _cmp_config -{ - bool enableHysteresis; /*!< Enable hysteresis. */ - bool enableLowPower; /*!< Enable low power mode. */ - cmp_filtercgf_clkdiv_t filterClockDivider; /* Filter clock divider. Filter clock equals the Analog Comparator clock - divided by 2^FILTERCGF_CLKDIV. */ - cmp_filtercgf_samplemode_t - filterSampleMode; /* Filter sample mode. Control the filtering of the Analog Comparator output. */ -} cmp_config_t; - -/************************************************************************************************* - * API - ************************************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief CMP initialization. - * - * This function enables the CMP module and do necessary settings. - * - * @param config Pointer to the configuration structure. - */ -void CMP_Init(const cmp_config_t *config); - -/*! - * @brief CMP deinitialization. - * - * This function gates the clock for CMP module. - */ -void CMP_Deinit(void); - -/*! - * @brief Initializes the CMP user configuration structure. - * - * This function initializes the user configuration structure to these default values. - * @code - * config->enableHysteresis = true; - * config->enableLowPower = true; - * config->filterClockDivider = kCMP_FilterClockDivide1; - * config->filterSampleMode = kCMP_FilterSampleMode0; - * @endcode - * @param config Pointer to the configuration structure. - */ -void CMP_GetDefaultConfig(cmp_config_t *config); - -/* @} */ - -/*! - * @name Compare Interface - * @{ - */ - -/* - * @brief Set the input channels for the comparator. - * - * @param positiveChannel Positive side input channel number. See "_cmp_input_mux". - * @param negativeChannel Negative side input channel number. See "_cmp_input_mux". - */ -static inline void CMP_SetInputChannels(uint8_t positiveChannel, uint8_t negativeChannel) -{ - PMC->COMP &= ~(PMC_COMP_PMUX_MASK | PMC_COMP_NMUX_MASK); - PMC->COMP |= (PMC_COMP_PMUX(positiveChannel) | PMC_COMP_NMUX(negativeChannel)); -} - -/*! - * @brief Configures the VREFINPUT. - * - * @param config Pointer to the configuration structure. - */ -void CMP_SetVREF(const cmp_vref_config_t *config); - -/*! - * @brief Get CMP compare output. - * - * @return The output result. true: voltage on positive side is greater than negative side. - * false: voltage on positive side is lower than negative side. - */ -static inline bool CMP_GetOutput(void) -{ - return SYSCON_COMP_INT_STATUS_VAL_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_VAL_MASK); -} - -/* @} */ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief CMP enable interrupt. - * - * @param type CMP interrupt type. See "_cmp_interrupt_type". - */ -static inline void CMP_EnableInterrupt(uint32_t type) -{ - SYSCON->COMP_INT_CTRL |= (SYSCON_COMP_INT_CTRL_INT_CTRL(type) | SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK); -} - -/*! - * @brief CMP disable interrupt. - * - */ -static inline void CMP_DisableInterrupt(void) -{ - SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK; -} - -/*! - * @brief CMP clear interrupt. - * - */ -static inline void CMP_ClearInterrupt(void) -{ - SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK; -} - -/*! - * @brief Select which Analog comparator output (filtered or un-filtered) is used for interrupt detection. - * - * @param enable false: Select Analog Comparator raw output (unfiltered) as input for interrupt detection. - * true: Select Analog Comparator filtered output as input for interrupt detection. - * - * @note: When CMP is configured as the wakeup source in power down mode, this function must use the raw output as the - * interupt source, that is, call this function and set parameter enable to false. - */ -static inline void CMP_EnableFilteredInterruptSource(bool enable) -{ - if (enable) - { - SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; - } - else - { - SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; - } -} -/* @} */ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Get CMP interrupt status before interupt enable. - * - * @return Interrupt status. true: interrupt pending, - * false: no interrupt pending. - */ -static inline bool CMP_GetPreviousInterruptStatus(void) -{ - return SYSCON_COMP_INT_STATUS_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_STATUS_MASK); -} - -/*! - * @brief Get CMP interrupt status after interupt enable. - * - * @return Interrupt status. true: interrupt pending, - * false: no interrupt pending. - */ -static inline bool CMP_GetInterruptStatus(void) -{ - return SYSCON_COMP_INT_STATUS_INT_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK); -} -/* @} */ - -/*! - * @name Filter Interface - * @{ - */ - -/*! - * @brief CMP Filter Sample Config. - * - * This function allows the users to configure the sampling mode and clock divider of the CMP Filter. - * - * @param filterSampleMode CMP Select filter sample mode - * @param filterClockDivider CMP Set fileter clock divider - */ -static inline void CMP_FilterSampleConfig(cmp_filtercgf_samplemode_t filterSampleMode, - cmp_filtercgf_clkdiv_t filterClockDivider) -{ - uint32_t comp = PMC->COMP; - - comp &= ~(PMC_COMP_FILTERCGF_CLKDIV_MASK | PMC_COMP_FILTERCGF_SAMPLEMODE_MASK); - comp |= (((uint32_t)filterClockDivider << PMC_COMP_FILTERCGF_CLKDIV_SHIFT) | - ((uint32_t)filterSampleMode << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)); - - PMC->COMP = comp; -} -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ -#endif /* __FSL_CMP_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common.c deleted file mode 100644 index d3af9fdfc67..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" - -#define SDK_MEM_MAGIC_NUMBER 12345U - -typedef struct _mem_align_control_block -{ - uint16_t identifier; /*!< Identifier for the memory control block. */ - uint16_t offset; /*!< offset from aligned address to real address */ -} mem_align_cb_t; - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.common" -#endif - -#if !((defined(__DSC__) && defined(__CW__))) -void *SDK_Malloc(size_t size, size_t alignbytes) -{ - mem_align_cb_t *p_cb = NULL; - uint32_t alignedsize; - - /* Check overflow. */ - alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes); - if (alignedsize < size) - { - return NULL; - } - - if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t)) - { - return NULL; - } - - alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t); - - union - { - void *pointer_value; - uintptr_t unsigned_value; - } p_align_addr, p_addr; - - p_addr.pointer_value = malloc((size_t)alignedsize); - - if (p_addr.pointer_value == NULL) - { - return NULL; - } - - p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes); - - p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U); - p_cb->identifier = SDK_MEM_MAGIC_NUMBER; - p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value); - - return p_align_addr.pointer_value; -} - -void SDK_Free(void *ptr) -{ - union - { - void *pointer_value; - uintptr_t unsigned_value; - } p_free; - p_free.pointer_value = ptr; - mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U); - - if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) - { - return; - } - - p_free.unsigned_value = p_free.unsigned_value - p_cb->offset; - - free(p_free.pointer_value); -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common.h deleted file mode 100644 index d9cb304f2f8..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common.h +++ /dev/null @@ -1,316 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_COMMON_H_ -#define _FSL_COMMON_H_ - -#include -#include -#include -#include -#include - -#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__) -#include -#endif - -#include "fsl_device_registers.h" - -/*! - * @addtogroup ksdk_common - * @{ - */ - -/******************************************************************************* - * Configurations - ******************************************************************************/ - -/*! @brief Macro to use the default weak IRQ handler in drivers. */ -#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ -#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Construct a status code value from a group and code number. */ -#define MAKE_STATUS(group, code) ((((group)*100L) + (code))) - -/*! @brief Construct the version number for drivers. - * - * The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M) - * and 16-bit platforms(such as DSC). - * - * @verbatim - - | Unused || Major Version || Minor Version || Bug Fix | - 31 25 24 17 16 9 8 0 - - @endverbatim - */ -#define MAKE_VERSION(major, minor, bugfix) (((major) * 65536L) + ((minor) * 256L) + (bugfix)) - -/*! @name Driver version */ -/*@{*/ -/*! @brief common driver version. */ -#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 2)) -/*@}*/ - -/* Debug console type definition. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */ - -/*! @brief Status group numbers. */ -enum _status_groups -{ - kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ - kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ - kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ - kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ - kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ - kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ - kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ - kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ - kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ - kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ - kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ - kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ - kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ - kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ - kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ - kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ - kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ - kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ - kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ - kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ - kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ - kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ - kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ - kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ - kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ - kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ - kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ - kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ - kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ - kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ - kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ - kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ - kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ - kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ - kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ - kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ - kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ - kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ - kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ - kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ - kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ - kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ - kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ - kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ - kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ - kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ - kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ - kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ - kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ - kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ - kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ - kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ - kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ - kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ - kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ - kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ - kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ - kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ - kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ - kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ - kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ - kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ - kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ - kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ - kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ - kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ - kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ - kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ - kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ - kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ - kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ - kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ - kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ - kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/ - kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */ - kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */ - kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */ - - kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ - kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ - kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ - kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ - kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ - kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ - kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ - kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ - kStatusGroup_HAL_I2S = 129, /*!< Group number for HAL I2S status codes. */ - kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ - kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ - kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ - kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ - kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ - kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ - kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ - kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ - kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ - kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ - kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ - kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ - kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ - kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ - kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */ - kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */ - kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */ - kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */ - kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */ - kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */ - kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */ - kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */ - kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */ - kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */ - kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */ - kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */ - kStatusGroup_CSS_PKC = 161, /*!< Group number for CSS PKC status codes. */ - kStatusGroup_HOSTIF = 162, /*!< Group number for HOSTIF status codes. */ - kStatusGroup_CLIF = 163, /*!< Group number for CLIF status codes. */ - kStatusGroup_BMA = 164, /*!< Group number for BMA status codes. */ -}; - -/*! \public - * @brief Generic status return codes. - */ -enum -{ - kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */ - kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */ - kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */ - kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */ - kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */ - kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */ - kStatus_NoTransferInProgress = - MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */ - kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */ - kStatus_NoData = - MAKE_STATUS(kStatusGroup_Generic, 8), /*!< Generic status for no data is found for the operation. */ -}; - -/*! @brief Type used for all status and error return values. */ -typedef int32_t status_t; - -/*! - * @name Min/max macros - * @{ - */ -#if !defined(MIN) -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) -#endif - -#if !defined(MAX) -#define MAX(a, b) (((a) > (b)) ? (a) : (b)) -#endif -/* @} */ - -/*! @brief Computes the number of elements in an array. */ -#if !defined(ARRAY_SIZE) -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) -#endif - -/*! @name UINT16_MAX/UINT32_MAX value */ -/* @{ */ -#if !defined(UINT16_MAX) -#define UINT16_MAX ((uint16_t)-1) -#endif - -#if !defined(UINT32_MAX) -#define UINT32_MAX ((uint32_t)-1) -#endif -/* @} */ - -/*! @name Suppress fallthrough warning macro */ -/* For switch case code block, if case section ends without "break;" statement, there wil be - fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. - To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each - case section which misses "break;"statement. - */ -/* @{ */ -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) -#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough)) -#else -#define SUPPRESS_FALL_THROUGH_WARNING() -#endif -/* @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -#if !((defined(__DSC__) && defined(__CW__))) -/*! - * @brief Allocate memory with given alignment and aligned size. - * - * This is provided to support the dynamically allocated memory - * used in cache-able region. - * @param size The length required to malloc. - * @param alignbytes The alignment size. - * @retval The allocated memory. - */ -void *SDK_Malloc(size_t size, size_t alignbytes); - -/*! - * @brief Free memory. - * - * @param ptr The memory to be release. - */ -void SDK_Free(void *ptr); -#endif - -/*! - * @brief Delay at least for some time. - * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, - * if precise delay count was needed, please implement a new delay function with hardware timer. - * - * @param delayTime_us Delay time in unit of microsecond. - * @param coreClock_Hz Core clock frequency with Hz. - */ -void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#if (defined(__DSC__) && defined(__CW__)) -#include "fsl_common_dsc.h" -#elif defined(__XCC__) -#include "fsl_common_dsp.h" -#else -#include "fsl_common_arm.h" -#endif - -#endif /* _FSL_COMMON_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common_arm.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common_arm.c deleted file mode 100644 index e77a265ce43..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common_arm.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.common_arm" -#endif - -#ifndef __GIC_PRIO_BITS -#if defined(ENABLE_RAM_VECTOR_TABLE) -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) -{ -#ifdef __VECTOR_TABLE -#undef __VECTOR_TABLE -#endif - -/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) - extern uint32_t Image$$VECTOR_ROM$$Base[]; - extern uint32_t Image$$VECTOR_RAM$$Base[]; - extern uint32_t Image$$RW_m_data$$Base[]; - -#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base -#define __VECTOR_RAM Image$$VECTOR_RAM$$Base -#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) -#elif defined(__ICCARM__) - extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; -#elif defined(__GNUC__) - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; - extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; - uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); -#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ - uint32_t n; - uint32_t ret; - uint32_t irqMaskValue; - - irqMaskValue = DisableGlobalIRQ(); - if (SCB->VTOR != (uint32_t)__VECTOR_RAM) - { - /* Copy the vector table from ROM to RAM */ - for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) - { - __VECTOR_RAM[n] = __VECTOR_TABLE[n]; - } - /* Point the VTOR to the position of vector table */ - SCB->VTOR = (uint32_t)__VECTOR_RAM; - } - - ret = __VECTOR_RAM[(int32_t)irq + 16]; - /* make sure the __VECTOR_RAM is noncachable */ - __VECTOR_RAM[(int32_t)irq + 16] = irqHandler; - - EnableGlobalIRQ(irqMaskValue); - - return ret; -} -#endif /* ENABLE_RAM_VECTOR_TABLE. */ -#endif /* __GIC_PRIO_BITS. */ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - -/* - * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, - * powerlib should be used instead of these functions. - */ -#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) - -/* - * When the SYSCON STARTER registers are discontinuous, these functions are - * implemented in fsl_power.c. - */ -#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) - -void EnableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t intNumber = (uint32_t)interrupt; - - uint32_t index = 0; - - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERSET[index] = 1UL << intNumber; - (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */ -} - -void DisableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t intNumber = (uint32_t)interrupt; - - (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */ - uint32_t index = 0; - - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERCLR[index] = 1UL << intNumber; -} -#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ -#endif /* FSL_FEATURE_POWERLIB_EXTEND */ -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - -#if defined(SDK_DELAY_USE_DWT) && defined(DWT) -/* Use WDT. */ -static void enableCpuCycleCounter(void) -{ - /* Make sure the DWT trace fucntion is enabled. */ - if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) - { - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - } - - /* CYCCNT not supported on this device. */ - assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); - - /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */ - if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) - { - DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; - } -} - -static uint32_t getCpuCycleCount(void) -{ - return DWT->CYCCNT; -} -#else /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ -/* Use software loop. */ -#if defined(__CC_ARM) /* This macro is arm v5 specific */ -/* clang-format off */ -__ASM static void DelayLoop(uint32_t count) -{ -loop - SUBS R0, R0, #1 - CMP R0, #0 - BNE loop - BX LR -} -/* clang-format on */ -#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__) -/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler, - * use SUB and CMP here for compatibility */ -static void DelayLoop(uint32_t count) -{ - __ASM volatile(" MOV R0, %0" : : "r"(count)); - __ASM volatile( - "loop: \n" -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) - " SUB R0, R0, #1 \n" -#else - " SUBS R0, R0, #1 \n" -#endif - " CMP R0, #0 \n" - - " BNE loop \n" - : - : - : "r0"); -} -#endif /* defined(__CC_ARM) */ -#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ - -/*! - * @brief Delay at least for some time. - * Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have - * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and - * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports - * up to 4294967 in current code. If long time delay is needed, please implement a new delay function. - * - * @param delayTime_us Delay time in unit of microsecond. - * @param coreClock_Hz Core clock frequency with Hz. - */ -void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) -{ - uint64_t count; - - if (delayTime_us > 0U) - { - count = USEC_TO_COUNT(delayTime_us, coreClock_Hz); - - assert(count <= UINT32_MAX); - -#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */ - - enableCpuCycleCounter(); - /* Calculate the count ticks. */ - count += getCpuCycleCount(); - - if (count > UINT32_MAX) - { - count -= UINT32_MAX; - /* Wait for cyccnt overflow. */ - while (count < getCpuCycleCount()) - { - } - } - - /* Wait for cyccnt reach count value. */ - while (count > getCpuCycleCount()) - { - } -#else - /* Divide value may be different in various environment to ensure delay is precise. - * Every loop count includes three instructions, due to Cortex-M7 sometimes executes - * two instructions in one period, through test here set divide 1.5. Other M cores use - * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does - * not matter because other instructions outside while loop is enough to fill the time. - */ -#if (__CORTEX_M == 7) - count = count / 3U * 2U; -#else - count = count / 4U; -#endif - DelayLoop((uint32_t)count); -#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common_arm.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common_arm.h deleted file mode 100644 index 2678ff625c7..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common_arm.h +++ /dev/null @@ -1,671 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_COMMON_ARM_H_ -#define _FSL_COMMON_ARM_H_ - -/* - * For CMSIS pack RTE. - * CMSIS pack RTE generates "RTC_Components.h" which contains the statements - * of the related element for all selected software components. - */ -#ifdef _RTE_ -#include "RTE_Components.h" -#endif - -/*! - * @addtogroup ksdk_common - * @{ - */ - -/*! @name Atomic modification - * - * These macros are used for atomic access, such as read-modify-write - * to the peripheral registers. - * - * - SDK_ATOMIC_LOCAL_ADD - * - SDK_ATOMIC_LOCAL_SET - * - SDK_ATOMIC_LOCAL_CLEAR - * - SDK_ATOMIC_LOCAL_TOGGLE - * - SDK_ATOMIC_LOCAL_CLEAR_AND_SET - * - * Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr - * means the address of the peripheral register or variable you want to modify - * atomically, the parameter @c clearBits is the bits to clear, the parameter - * @c setBits it the bits to set. - * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this: - * - * @code - volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR; - - SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02); - @endcode - * - * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result, - * register bit1:bit0 = 0b10. - * - * @note For the platforms don't support exclusive load and store, these macros - * disable the global interrupt to pretect the modification. - * - * @note These macros only guarantee the local processor atomic operations. For - * the multi-processor devices, use hardware semaphore such as SEMA42 to - * guarantee exclusive access if necessary. - * - * @{ - */ - -/* clang-format off */ -#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) -/* clang-format on */ - -/* If the LDREX and STREX are supported, use them. */ -#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \ - do \ - { \ - (val) = __LDREXB(addr); \ - (ops); \ - } while (0UL != __STREXB((val), (addr))) - -#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \ - do \ - { \ - (val) = __LDREXH(addr); \ - (ops); \ - } while (0UL != __STREXH((val), (addr))) - -#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \ - do \ - { \ - (val) = __LDREXW(addr); \ - (ops); \ - } while (0UL != __STREXW((val), (addr))) - -static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val); -} - -static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val); -} - -static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val); -} - -static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val); -} - -static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val); -} - -static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val); -} - -static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits); -} - -static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits); -} - -static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits); -} - -static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits); -} - -static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits); -} - -static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits); -} - -static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits); -} - -static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits); -} - -static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits); -} - -static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); -} - -static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); -} - -static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); -} - -#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ - ((1UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalAdd1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \ - ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \ - _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val)))) - -#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ - ((1UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ - ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ - _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) - -#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ - ((1UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalClear1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ - ((2UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalClear2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ - _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) - -#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ - ((1UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalToggle1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ - ((2UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalToggle2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ - _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) - -#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ - ((1UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(clearBits), (uint8_t)(setBits)) : \ - ((2UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(clearBits), (uint16_t)(setBits)) : \ - _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(clearBits), (uint32_t)(setBits)))) -#else - -#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ - do \ - { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) += (val); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ - do \ - { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) |= (bits); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ - do \ - { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) &= ~(bits); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ - do \ - { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) ^= (bits); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ - do \ - { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) = (*(addr) & ~(clearBits)) | (setBits); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#endif -/* @} */ - -/*! @name Timer utilities */ -/* @{ */ -/*! Macro to convert a microsecond period to raw count value */ -#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) -/*! Macro to convert a raw count value to microsecond */ -#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000000U / (clockFreqInHz)) - -/*! Macro to convert a millisecond period to raw count value */ -#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) -/*! Macro to convert a raw count value to millisecond */ -#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz)) -/* @} */ - -/*! @name ISR exit barrier - * @{ - * - * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - * exception return operation might vector to incorrect interrupt. - * For Cortex-M7, if core speed much faster than peripheral register write speed, - * the peripheral interrupt flags may be still set after exiting ISR, this results to - * the same error similar with errata 83869. - */ -#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U)) -#define SDK_ISR_EXIT_BARRIER __DSB() -#else -#define SDK_ISR_EXIT_BARRIER -#endif - -/* @} */ - -/*! @name Alignment variable definition macros */ -/* @{ */ -#if (defined(__ICCARM__)) -/* - * Workaround to disable MISRA C message suppress warnings for IAR compiler. - * http:/ /supp.iar.com/Support/?note=24725 - */ -_Pragma("diag_suppress=Pm120") -#define SDK_PRAGMA(x) _Pragma(#x) - _Pragma("diag_error=Pm120") -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var -#elif defined(__GNUC__) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) -#else -#error Toolchain not supported -#endif - -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#endif - -/*! Macro to change a value to a given size aligned value */ -#define SDK_SIZEALIGN(var, alignbytes) \ - ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) -/* @} */ - -/*! @name Non-cacheable region definition macros */ -/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or - * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable - * variables, please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, - * these zero-inited variables will be initialized to zero in system startup. - */ -/* @{ */ - -#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \ - defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) - -#if (defined(__ICCARM__)) -#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" -#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" - -#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var -#if (defined(__CC_ARM)) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var -#else -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var -#endif - -#elif (defined(__GNUC__)) -/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" - * in your projects to make sure the non-cacheable section variables will be initialized in system startup. - */ -#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) -#else -#error Toolchain not supported. -#endif - -#else - -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes) -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes) - -#endif - -/* @} */ - -/*! - * @name Time sensitive region - * @{ - */ -#if (defined(__ICCARM__)) -#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" -#define AT_QUICKACCESS_SECTION_DATA(var) var @"DataQuickAccess" -#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ - SDK_PRAGMA(data_alignment = alignbytes) var @"DataQuickAccess" -#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func -#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var -#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ - __attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var -#elif (defined(__GNUC__)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func -#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var -#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ - __attribute__((section("DataQuickAccess"))) var __attribute__((aligned(alignbytes))) -#else -#error Toolchain not supported. -#endif /* defined(__ICCARM__) */ - -/*! @name Ram Function */ -#if (defined(__ICCARM__)) -#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" -#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func -#elif (defined(__GNUC__)) -#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func -#else -#error Toolchain not supported. -#endif /* defined(__ICCARM__) */ -/* @} */ - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - void DefaultISR(void); -#endif - -/* - * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t - * defined in previous of this file. - */ -#include "fsl_clock.h" - -/* - * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral - */ -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) -#include "fsl_reset.h" -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief Enable specific interrupt. - * - * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt enabled successfully - * @retval kStatus_Fail Failed to enable the interrupt - */ -static inline status_t EnableIRQ(IRQn_Type interrupt) -{ - status_t status = kStatus_Success; - - if (NotAvail_IRQn == interrupt) - { - status = kStatus_Fail; - } - -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - status = kStatus_Fail; - } -#endif - - else - { -#if defined(__GIC_PRIO_BITS) - GIC_EnableIRQ(interrupt); -#else - NVIC_EnableIRQ(interrupt); -#endif - } - - return status; -} - -/*! - * @brief Disable specific interrupt. - * - * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt disabled successfully - * @retval kStatus_Fail Failed to disable the interrupt - */ -static inline status_t DisableIRQ(IRQn_Type interrupt) -{ - status_t status = kStatus_Success; - - if (NotAvail_IRQn == interrupt) - { - status = kStatus_Fail; - } - -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - status = kStatus_Fail; - } -#endif - - else - { -#if defined(__GIC_PRIO_BITS) - GIC_DisableIRQ(interrupt); -#else - NVIC_DisableIRQ(interrupt); -#endif - } - - return status; -} - -/*! - * @brief Disable the global IRQ - * - * Disable the global interrupt and return the current primask register. User is required to provided the primask - * register for the EnableGlobalIRQ(). - * - * @return Current primask value. - */ -static inline uint32_t DisableGlobalIRQ(void) -{ -#if defined(CPSR_I_Msk) - uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; - - __disable_irq(); - - return cpsr; -#else - uint32_t regPrimask = __get_PRIMASK(); - - __disable_irq(); - - return regPrimask; -#endif -} - -/*! - * @brief Enable the global IRQ - * - * Set the primask register with the provided primask value but not just enable the primask. The idea is for the - * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to - * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. - * - * @param primask value of primask register to be restored. The primask value is supposed to be provided by the - * DisableGlobalIRQ(). - */ -static inline void EnableGlobalIRQ(uint32_t primask) -{ -#if defined(CPSR_I_Msk) - __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); -#else - __set_PRIMASK(primask); -#endif -} - -#if defined(ENABLE_RAM_VECTOR_TABLE) -/*! - * @brief install IRQ handler - * - * @param irq IRQ number - * @param irqHandler IRQ handler address - * @return The old IRQ handler address - */ -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); -#endif /* ENABLE_RAM_VECTOR_TABLE. */ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - -/* - * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, - * powerlib should be used instead of these functions. - */ -#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) -/*! - * @brief Enable specific interrupt for wake-up from deep-sleep mode. - * - * Enable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). - * - * @param interrupt The IRQ number. - */ -void EnableDeepSleepIRQ(IRQn_Type interrupt); - -/*! - * @brief Disable specific interrupt for wake-up from deep-sleep mode. - * - * Disable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). - * - * @param interrupt The IRQ number. - */ -void DisableDeepSleepIRQ(IRQn_Type interrupt); -#endif /* FSL_FEATURE_POWERLIB_EXTEND */ -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @} */ - -#endif /* _FSL_COMMON_ARM_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_crc.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_crc.c deleted file mode 100644 index c73f84997af..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_crc.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2019-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_crc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_crc" -#endif - -#if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT -/* @brief Default user configuration structure for CRC-CCITT */ -#define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT -/*< CRC-CCIT polynomial x^16 + x^12 + x^5 + x^0 */ -#define CRC_DRIVER_DEFAULT_REVERSE_IN false -/*< Default is no bit reverse */ -#define CRC_DRIVER_DEFAULT_COMPLEMENT_IN false -/*< Default is without complement of written data */ -#define CRC_DRIVER_DEFAULT_REVERSE_OUT false -/*< Default is no bit reverse */ -#define CRC_DRIVER_DEFAULT_COMPLEMENT_OUT false -/*< Default is without complement of CRC data register read data */ -#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU -/*< Default initial checksum */ -#endif /* CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Enables and configures the CRC peripheral module. - * - * This functions enables the CRC peripheral clock in the LPC SYSCON block. - * It also configures the CRC engine and starts checksum computation by writing the seed. - * - * param base CRC peripheral address. - * param config CRC module configuration structure. - */ -void CRC_Init(CRC_Type *base, const crc_config_t *config) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* enable clock to CRC */ - CLOCK_EnableClock(kCLOCK_Crc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_CRC_HAS_NO_RESET) && FSL_FEATURE_CRC_HAS_NO_RESET) - RESET_PeripheralReset(kCRC_RST_SHIFT_RSTn); -#endif - - /* configure CRC module and write the seed */ - base->MODE = CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) | - CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) | - CRC_MODE_CMPL_SUM(config->complementOut); - base->SEED = config->seed; -} - -/*! - * brief Loads default values to CRC protocol configuration structure. - * - * Loads default values to CRC protocol configuration structure. The default values are: - * code - * config->polynomial = kCRC_Polynomial_CRC_CCITT; - * config->reverseIn = false; - * config->complementIn = false; - * config->reverseOut = false; - * config->complementOut = false; - * config->seed = 0xFFFFU; - * endcode - * - * param config CRC protocol configuration structure - */ -void CRC_GetDefaultConfig(crc_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_REVERSE_IN, - CRC_DRIVER_DEFAULT_COMPLEMENT_IN, CRC_DRIVER_DEFAULT_REVERSE_OUT, - CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED}; - - *config = default_config; -} - -/*! - * brief resets CRC peripheral module. - * - * param base CRC peripheral address. - */ -void CRC_Reset(CRC_Type *base) -{ - crc_config_t config; - CRC_GetDefaultConfig(&config); - CRC_Init(base, &config); -} - -/*! - * brief Write seed (initial checksum) to CRC peripheral module. - * - * param base CRC peripheral address. - * param seed CRC Seed value. - */ -void CRC_WriteSeed(CRC_Type *base, uint32_t seed) -{ - /* write the seed (initial checksum) */ - base->SEED = seed; -} - -/*! - * brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure. - * - * The values, including seed, can be used to resume CRC calculation later. - - * param base CRC peripheral address. - * param config CRC protocol configuration structure - */ -void CRC_GetConfig(CRC_Type *base, crc_config_t *config) -{ - /* extract CRC mode settings */ - uint32_t mode = base->MODE; - config->polynomial = - (crc_polynomial_t)(uint32_t)(((uint32_t)(mode & CRC_MODE_CRC_POLY_MASK)) >> CRC_MODE_CRC_POLY_SHIFT); - config->reverseIn = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK); - config->complementIn = (bool)(mode & CRC_MODE_CMPL_WR_MASK); - config->reverseOut = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK); - config->complementOut = (bool)(mode & CRC_MODE_CMPL_SUM_MASK); - - /* reset CRC sum bit reverse and 1's complement setting, so its value can be used as a seed */ - base->MODE = mode & ~((1U << CRC_MODE_BIT_RVS_SUM_SHIFT) | (1U << CRC_MODE_CMPL_SUM_SHIFT)); - - /* now we can obtain intermediate raw CRC sum value */ - config->seed = base->SUM; - - /* restore original CRC sum bit reverse and 1's complement setting */ - base->MODE = mode; -} - -/*! - * brief Writes data to the CRC module. - * - * Writes input data buffer bytes to CRC data register. - * - * param base CRC peripheral address. - * param data Input data stream, MSByte in data[0]. - * param dataSize Size of the input data buffer in bytes. - */ -void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) -{ - const uint32_t *data32; - - /* 8-bit reads and writes till source address is aligned 4 bytes */ - while ((0U != dataSize) && (0U != ((uint32_t)data & 3U))) - { - *((__O uint8_t *)&(base->WR_DATA)) = *data; - data++; - dataSize--; - } - - /* use 32-bit reads and writes as long as possible */ - data32 = (const uint32_t *)(uint32_t)data; - while (dataSize >= sizeof(uint32_t)) - { - *((__O uint32_t *)&(base->WR_DATA)) = *data32; - data32++; - dataSize -= sizeof(uint32_t); - } - - data = (const uint8_t *)data32; - - /* 8-bit reads and writes till end of data buffer */ - while (0U != dataSize) - { - *((__O uint8_t *)&(base->WR_DATA)) = *data; - data++; - dataSize--; - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_crc.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_crc.h deleted file mode 100644 index 08e08bd57d3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_crc.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2019-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CRC_H_ -#define _FSL_CRC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup crc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CRC driver version. Version 2.1.1. - * - * Current version: 2.1.1 - * - * Change log: - * - Version 2.0.0 - * - initial version - * - Version 2.0.1 - * - add explicit type cast when writing to WR_DATA - * - Version 2.0.2 - * - Fix MISRA issue - * - Version 2.1.0 - * - Add CRC_WriteSeed function - * - Version 2.1.1 - * - Fix MISRA issue - */ -#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) -/*@}*/ - -#ifndef CRC_DRIVER_CUSTOM_DEFAULTS -/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Uses CRC-16/CCITT-FALSE as default. */ -#define CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT 1 -#endif - -/*! @brief CRC polynomials to use. */ -typedef enum _crc_polynomial -{ - kCRC_Polynomial_CRC_CCITT = 0U, /*!< x^16+x^12+x^5+1 */ - kCRC_Polynomial_CRC_16 = 1U, /*!< x^16+x^15+x^2+1 */ - kCRC_Polynomial_CRC_32 = 2U /*!< x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */ -} crc_polynomial_t; - -/*! - * @brief CRC protocol configuration. - * - * This structure holds the configuration for the CRC protocol. - * - */ -typedef struct _crc_config -{ - crc_polynomial_t polynomial; /*!< CRC polynomial. */ - bool reverseIn; /*!< Reverse bits on input. */ - bool complementIn; /*!< Perform 1's complement on input. */ - bool reverseOut; /*!< Reverse bits on output. */ - bool complementOut; /*!< Perform 1's complement on output. */ - uint32_t seed; /*!< Starting checksum value. */ -} crc_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Enables and configures the CRC peripheral module. - * - * This functions enables the CRC peripheral clock in the LPC SYSCON block. - * It also configures the CRC engine and starts checksum computation by writing the seed. - * - * @param base CRC peripheral address. - * @param config CRC module configuration structure. - */ -void CRC_Init(CRC_Type *base, const crc_config_t *config); - -/*! - * @brief Disables the CRC peripheral module. - * - * This functions disables the CRC peripheral clock in the LPC SYSCON block. - * - * @param base CRC peripheral address. - */ -static inline void CRC_Deinit(CRC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* disable clock to CRC */ - CLOCK_DisableClock(kCLOCK_Crc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief resets CRC peripheral module. - * - * @param base CRC peripheral address. - */ -void CRC_Reset(CRC_Type *base); - -/*! - * @brief Write seed to CRC peripheral module. - * - * @param base CRC peripheral address. - * @param seed CRC Seed value. - */ -void CRC_WriteSeed(CRC_Type *base, uint32_t seed); - -/*! - * @brief Loads default values to CRC protocol configuration structure. - * - * Loads default values to CRC protocol configuration structure. The default values are: - * @code - * config->polynomial = kCRC_Polynomial_CRC_CCITT; - * config->reverseIn = false; - * config->complementIn = false; - * config->reverseOut = false; - * config->complementOut = false; - * config->seed = 0xFFFFU; - * @endcode - * - * @param config CRC protocol configuration structure - */ -void CRC_GetDefaultConfig(crc_config_t *config); - -/*! - * @brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure. - * - * The values, including seed, can be used to resume CRC calculation later. - - * @param base CRC peripheral address. - * @param config CRC protocol configuration structure - */ -void CRC_GetConfig(CRC_Type *base, crc_config_t *config); - -/*! - * @brief Writes data to the CRC module. - * - * Writes input data buffer bytes to CRC data register. - * - * @param base CRC peripheral address. - * @param data Input data stream, MSByte in data[0]. - * @param dataSize Size of the input data buffer in bytes. - */ -void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize); - -/*! - * @brief Reads 32-bit checksum from the CRC module. - * - * Reads CRC data register. - * - * @param base CRC peripheral address. - * @return final 32-bit checksum, after configured bit reverse and complement operations. - */ -static inline uint32_t CRC_Get32bitResult(CRC_Type *base) -{ - return base->SUM; -} - -/*! - * @brief Reads 16-bit checksum from the CRC module. - * - * Reads CRC data register. - * - * @param base CRC peripheral address. - * @return final 16-bit checksum, after configured bit reverse and complement operations. - */ -static inline uint16_t CRC_Get16bitResult(CRC_Type *base) -{ - return (uint16_t)base->SUM; -} - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_CRC_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ctimer.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ctimer.c deleted file mode 100644 index e53bebdd013..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ctimer.c +++ /dev/null @@ -1,577 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_ctimer.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.ctimer" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base Ctimer peripheral base address - * - * @return The Timer instance - */ -static uint32_t CTIMER_GetInstance(CTIMER_Type *base); - -/*! - * @brief CTIMER generic IRQ handle function. - * - * @param index FlexCAN peripheral instance index. - */ -static void CTIMER_GenericIRQHandler(uint32_t index); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to Timer bases for each instance. */ -static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to Timer clocks for each instance. */ -static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET -/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N; -#else -/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; -#endif -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/*! @brief Pointers real ISRs installed by drivers for each instance. */ -static ctimer_callback_t *s_ctimerCallback[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = {0}; - -/*! @brief Callback type installed by drivers for each instance. */ -static ctimer_callback_type_t ctimerCallbackType[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = { - kCTIMER_SingleCallback}; - -/*! @brief Array to map timer instance to IRQ number. */ -static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t CTIMER_GetInstance(CTIMER_Type *base) -{ - uint32_t instance; - uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ctimerArrayCount; instance++) - { - if (s_ctimerBases[instance] == base) - { - break; - } - } - - assert(instance < ctimerArrayCount); - - return instance; -} - -/*! - * brief Ungates the clock and configures the peripheral for basic operation. - * - * note This API should be called at the beginning of the application before using the driver. - * - * param base Ctimer peripheral base address - * param config Pointer to the user configuration structure. - */ -void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) -{ - assert(config != NULL); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the timer clock*/ - CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -/* Reset the module. */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) - RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]); -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/* Setup the cimer mode and count select */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input); -#endif - /* Setup the timer prescale value */ - base->PR = CTIMER_PR_PRVAL(config->prescale); -} - -/*! - * brief Gates the timer clock. - * - * param base Ctimer peripheral base address - */ -void CTIMER_Deinit(CTIMER_Type *base) -{ - uint32_t index = CTIMER_GetInstance(base); - /* Stop the timer */ - base->TCR &= ~CTIMER_TCR_CEN_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the timer clock*/ - CLOCK_DisableClock(s_ctimerClocks[index]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Disable IRQ at NVIC Level */ - (void)DisableIRQ(s_ctimerIRQ[index]); -} - -/*! - * brief Fills in the timers configuration structure with the default settings. - * - * The default values are: - * code - * config->mode = kCTIMER_TimerMode; - * config->input = kCTIMER_Capture_0; - * config->prescale = 0; - * endcode - * param config Pointer to the user configuration structure. - */ -void CTIMER_GetDefaultConfig(ctimer_config_t *config) -{ - assert(config != NULL); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* Run as a timer */ - config->mode = kCTIMER_TimerMode; - /* This field is ignored when mode is timer */ - config->input = kCTIMER_Capture_0; - /* Timer counter is incremented on every APB bus clock */ - config->prescale = 0; -} - -/*! - * brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function can manually assign the specified channel to set the PWM cycle. - * - * note When setting PWM output from multiple output pins, all should use the same PWM - * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. - * - * param base Ctimer peripheral base address - * param pwmPeriodChannel Specify the channel to control the PWM period - * param matchChannel Match pin to be used to output the PWM signal - * param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 - * param pwmFreq_Hz PWM signal frequency in Hz - * param srcClock_Hz Timer counter clock in Hz - * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt will be generated. - * - * return kStatus_Success on success - * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM cycle - */ -status_t CTIMER_SetupPwm(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - bool enableInt) -{ - assert(pwmFreq_Hz > 0U); - - uint32_t reg; - uint32_t period, pulsePeriod = 0; - uint32_t timerClock = srcClock_Hz / (base->PR + 1U); - uint32_t index = CTIMER_GetInstance(base); - - if (matchChannel == pwmPeriodChannel) - { - return kStatus_Fail; - } - - /* Enable PWM mode on the match channel */ - base->PWMC |= (1UL << (uint32_t)matchChannel); - - /* Clear the stop, reset and interrupt bits for this channel */ - reg = base->MCR; - reg &= - ~(((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK)) - << ((uint32_t)matchChannel * 3U)); - - /* If call back function is valid then enable match interrupt for the channel */ - if (enableInt) - { - reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); - } - - /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ - reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); - - base->MCR = reg; - - /* Calculate PWM period match value */ - period = (timerClock / pwmFreq_Hz) - 1U; - - /* Calculate pulse width match value */ - if (dutyCyclePercent == 0U) - { - pulsePeriod = period + 1U; - } - else - { - pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; - } - - /* Specified channel pwmPeriodChannel will define the PWM period */ - base->MR[pwmPeriodChannel] = period; - - /* This will define the PWM pulse period */ - base->MR[matchChannel] = pulsePeriod; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); - /* If call back function is valid then enable interrupt and update the call back function */ - if (enableInt) - { - (void)EnableIRQ(s_ctimerIRQ[index]); - } - - return kStatus_Success; -} - -/*! - * brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function can manually assign the specified channel to set the PWM cycle. - * - * note When setting PWM output from multiple output pins, all should use the same PWM - * period - * - * param base Ctimer peripheral base address - * param pwmPeriodChannel Specify the channel to control the PWM period - * param matchChannel Match pin to be used to output the PWM signal - * param pwmPeriod PWM period match value - * param pulsePeriod Pulse width match value - * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt will be generated. - * - * return kStatus_Success on success - * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM period - */ -status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint32_t pwmPeriod, - uint32_t pulsePeriod, - bool enableInt) -{ -/* Some CTimers only have 16bits , so the value is limited*/ -#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B - assert(!((FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32) && (pulsePeriod > 0xFFFFU))); -#endif - - uint32_t reg; - uint32_t index = CTIMER_GetInstance(base); - - if (matchChannel == pwmPeriodChannel) - { - return kStatus_Fail; - } - - /* Enable PWM mode on PWM pulse channel */ - base->PWMC |= (1UL << (uint32_t)matchChannel); - - /* Clear the stop, reset and interrupt bits for PWM pulse channel */ - reg = base->MCR; - reg &= - ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) - << ((uint32_t)matchChannel * 3U)); - - /* If call back function is valid then enable match interrupt for PWM pulse channel */ - if (enableInt) - { - reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); - } - - /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ - reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); - - base->MCR = reg; - - /* Specified channel pwmPeriodChannel will define the PWM period */ - base->MR[pwmPeriodChannel] = pwmPeriod; - - /* This will define the PWM pulse period */ - base->MR[matchChannel] = pulsePeriod; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); - /* If call back function is valid then enable interrupt and update the call back function */ - if (enableInt) - { - (void)EnableIRQ(s_ctimerIRQ[index]); - } - - return kStatus_Success; -} - -/*! - * brief Updates the duty cycle of an active PWM signal. - * - * note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. - * This function can manually assign the specified channel to set the PWM cycle. - * - * param base Ctimer peripheral base address - * param pwmPeriodChannel Specify the channel to control the PWM period - * param matchChannel Match pin to be used to output the PWM signal - * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 - */ -void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent) -{ - uint32_t pulsePeriod = 0, period; - - /* Specified channel pwmPeriodChannel defines the PWM period */ - period = base->MR[pwmPeriodChannel]; - - /* For 0% dutycyle, make pulse period greater than period so the event will never occur */ - if (dutyCyclePercent == 0U) - { - pulsePeriod = period + 1U; - } - else - { - pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; - } - - /* Update dutycycle */ - base->MR[matchChannel] = pulsePeriod; -} - -/*! - * brief Setup the match register. - * - * User configuration is used to setup the match value and action to be taken when a match occurs. - * - * param base Ctimer peripheral base address - * param matchChannel Match register to configure - * param config Pointer to the match configuration structure - */ -void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config) -{ -/* Some CTimers only have 16bits , so the value is limited*/ -#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B - assert(!(FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32 && config->matchValue > 0xFFFFU)); -#endif - uint32_t reg; - uint32_t index = CTIMER_GetInstance(base); - - /* Set the counter operation when a match on this channel occurs */ - reg = base->MCR; - reg &= - ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) - << ((uint32_t)matchChannel * 3U)); - reg |= ((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)matchChannel * 3U))); - reg |= ((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)matchChannel * 3U))); - reg |= ((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); - base->MCR = reg; - - reg = base->EMR; - /* Set the match output operation when a match on this channel occurs */ - reg &= ~(((uint32_t)CTIMER_EMR_EMC0_MASK) << ((uint32_t)matchChannel * 2U)); - reg |= ((uint32_t)config->outControl) << (CTIMER_EMR_EMC0_SHIFT + ((uint32_t)matchChannel * 2U)); - - /* Set the initial state of the EM bit/output */ - reg &= ~(((uint32_t)CTIMER_EMR_EM0_MASK) << (uint32_t)matchChannel); - reg |= ((uint32_t)config->outPinInitState) << (uint32_t)matchChannel; - base->EMR = reg; - - /* Set the match value */ - base->MR[matchChannel] = config->matchValue; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); - /* If interrupt is enabled then enable interrupt and update the call back function */ - if (config->enableInterrupt) - { - (void)EnableIRQ(s_ctimerIRQ[index]); - } -} - -/*! - * brief Get the status of output match. - * - * This function gets the status of output MAT, whether or not this output is connected to a pin. - * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - * - * param base Ctimer peripheral base address - * param matchChannel External match channel, user can obtain the status of multiple match channels - * at the same time by using the logic of "|" - * enumeration ::ctimer_external_match_t - * return The mask of external match channel status flags. Users need to use the - * _ctimer_external_match type to decode the return variables. - */ -uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel) -{ - return (base->EMR & matchChannel); -} - -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) -/*! - * brief Setup the capture. - * - * param base Ctimer peripheral base address - * param capture Capture channel to configure - * param edge Edge on the channel that will trigger a capture - * param enableInt Flag to enable channel interrupts, if enabled then the registered call back - * is called upon capture - */ -void CTIMER_SetupCapture(CTIMER_Type *base, - ctimer_capture_channel_t capture, - ctimer_capture_edge_t edge, - bool enableInt) -{ - uint32_t reg = base->CCR; - uint32_t index = CTIMER_GetInstance(base); - - /* Set the capture edge */ - reg &= ~((uint32_t)((uint32_t)CTIMER_CCR_CAP0RE_MASK | (uint32_t)CTIMER_CCR_CAP0FE_MASK | - (uint32_t)CTIMER_CCR_CAP0I_MASK) - << ((uint32_t)capture * 3U)); - reg |= ((uint32_t)edge) << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U)); - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, (((uint32_t)kCTIMER_Capture0Flag) << (uint32_t)capture)); - /* If call back function is valid then enable capture interrupt for the channel and update the call back function */ - if (enableInt) - { - reg |= ((uint32_t)CTIMER_CCR_CAP0I_MASK) << ((uint32_t)capture * 3U); - (void)EnableIRQ(s_ctimerIRQ[index]); - } - base->CCR = reg; -} -#endif - -/*! - * brief Register callback. - * - * param base Ctimer peripheral base address - * param cb_func callback function - * param cb_type callback function type, singular or multiple - */ -void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type) -{ - uint32_t index = CTIMER_GetInstance(base); - s_ctimerCallback[index] = cb_func; - ctimerCallbackType[index] = cb_type; -} - -/*! - * brief CTIMER generic IRQ handle function. - * - * param index FlexCAN peripheral instance index. - */ -static void CTIMER_GenericIRQHandler(uint32_t index) -{ - uint32_t int_stat, i, mask; - /* Get Interrupt status flags */ - int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]); - /* Clear the status flags that were set */ - CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat); - if (ctimerCallbackType[index] == kCTIMER_SingleCallback) - { - if (s_ctimerCallback[index][0] != NULL) - { - s_ctimerCallback[index][0](int_stat); - } - } - else - { -#if defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE - for (i = 0; i <= CTIMER_IR_MR3INT_SHIFT; i++) -#else -#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT - for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) -#else -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) - for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) -#else - for (i = 0; i <= CTIMER_IR_CR1INT_SHIFT; i++) -#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ -#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ -#endif - { - mask = 0x01UL << i; - /* For each status flag bit that was set call the callback function if it is valid */ - if (((int_stat & mask) != 0U) && (s_ctimerCallback[index][i] != NULL)) - { - s_ctimerCallback[index][i](int_stat); - } - } - } - SDK_ISR_EXIT_BARRIER; -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(CTIMER0) -void CTIMER0_DriverIRQHandler(void); -void CTIMER0_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(0); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CTIMER1) -void CTIMER1_DriverIRQHandler(void); -void CTIMER1_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(1); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CTIMER2) -void CTIMER2_DriverIRQHandler(void); -void CTIMER2_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(2); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CTIMER3) -void CTIMER3_DriverIRQHandler(void); -void CTIMER3_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(3); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CTIMER4) -void CTIMER4_DriverIRQHandler(void); -void CTIMER4_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(4); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ctimer.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ctimer.h deleted file mode 100644 index ca39c95d30e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ctimer.h +++ /dev/null @@ -1,533 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_CTIMER_H_ -#define _FSL_CTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup ctimer - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) /*!< Version 2.2.2 */ -/*@}*/ - -/*! @brief List of Timer capture channels */ -typedef enum _ctimer_capture_channel -{ - kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ - kCTIMER_Capture_1, /*!< Timer capture channel 1 */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - kCTIMER_Capture_2, /*!< Timer capture channel 2 */ -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - kCTIMER_Capture_3 /*!< Timer capture channel 3 */ -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ -} ctimer_capture_channel_t; - -/*! @brief List of capture edge options */ -typedef enum _ctimer_capture_edge -{ - kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */ - kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */ - kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */ -} ctimer_capture_edge_t; - -/*! @brief List of Timer match registers */ -typedef enum _ctimer_match -{ - kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */ - kCTIMER_Match_1, /*!< Timer match register 1 */ - kCTIMER_Match_2, /*!< Timer match register 2 */ - kCTIMER_Match_3 /*!< Timer match register 3 */ -} ctimer_match_t; - -/*! @brief List of external match */ -typedef enum _ctimer_external_match -{ - kCTIMER_External_Match_0 = (1U << 0), /*!< External match 0 */ - kCTIMER_External_Match_1 = (1U << 1), /*!< External match 1 */ - kCTIMER_External_Match_2 = (1U << 2), /*!< External match 2 */ - kCTIMER_External_Match_3 = (1U << 3) /*!< External match 3 */ -} ctimer_external_match_t; - -/*! @brief List of output control options */ -typedef enum _ctimer_match_output_control -{ - kCTIMER_Output_NoAction = 0U, /*!< No action is taken */ - kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */ - kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */ - kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */ -} ctimer_match_output_control_t; - -/*! @brief List of Timer modes */ -typedef enum _ctimer_timer_mode -{ - kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */ - kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */ - kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */ - kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */ -} ctimer_timer_mode_t; - -/*! @brief List of Timer interrupts */ -typedef enum _ctimer_interrupt_enable -{ - kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ - kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ - kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ - kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ - kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ -#endif -} ctimer_interrupt_enable_t; - -/*! @brief List of Timer flags */ -typedef enum _ctimer_status_flags -{ - kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ - kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ - kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ - kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ - kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) - kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ -#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ -#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT - kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ -#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ -#endif -} ctimer_status_flags_t; - -typedef void (*ctimer_callback_t)(uint32_t flags); - -/*! @brief Callback type when registering for a callback. When registering a callback - * an array of function pointers is passed the size could be 1 or 8, the callback - * type will tell that. - */ -typedef enum -{ - kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. - based on the status flags different channels needs to be handled differently */ - kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. - for both match/capture */ -} ctimer_callback_type_t; - -/*! - * @brief Match configuration - * - * This structure holds the configuration settings for each match register. - */ -typedef struct _ctimer_match_config -{ - uint32_t matchValue; /*!< This is stored in the match register */ - bool enableCounterReset; /*!< true: Match will reset the counter - false: Match will not reser the counter */ - bool enableCounterStop; /*!< true: Match will stop the counter - false: Match will not stop the counter */ - ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */ - bool outPinInitState; /*!< Initial value of the EM bit/output */ - bool enableInterrupt; /*!< true: Generate interrupt upon match - false: Do not generate interrupt on match */ - -} ctimer_match_config_t; - -/*! - * @brief Timer configuration structure - * - * This structure holds the configuration settings for the Timer peripheral. To initialize this - * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a - * pointer to the configuration structure instance. - * - * The configuration structure can be made constant so as to reside in flash. - */ -typedef struct _ctimer_config -{ - ctimer_timer_mode_t mode; /*!< Timer mode */ - ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer - modes that rely on this input signal to increment TC */ - uint32_t prescale; /*!< Prescale value */ -} ctimer_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application before using the driver. - * - * @param base Ctimer peripheral base address - * @param config Pointer to the user configuration structure. - */ -void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config); - -/*! - * @brief Gates the timer clock. - * - * @param base Ctimer peripheral base address - */ -void CTIMER_Deinit(CTIMER_Type *base); - -/*! - * @brief Fills in the timers configuration structure with the default settings. - * - * The default values are: - * @code - * config->mode = kCTIMER_TimerMode; - * config->input = kCTIMER_Capture_0; - * config->prescale = 0; - * @endcode - * @param config Pointer to the user configuration structure. - */ -void CTIMER_GetDefaultConfig(ctimer_config_t *config); - -/*! @}*/ - -/*! - * @name PWM setup operations - * @{ - */ - -/*! - * @brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function can manually assign the specified channel to set the PWM cycle. - * - * @note When setting PWM output from multiple output pins, all should use the same PWM - * period - * - * @param base Ctimer peripheral base address - * @param pwmPeriodChannel Specify the channel to control the PWM period - * @param matchChannel Match pin to be used to output the PWM signal - * @param pwmPeriod PWM period match value - * @param pulsePeriod Pulse width match value - * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt will be generated. - */ -status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint32_t pwmPeriod, - uint32_t pulsePeriod, - bool enableInt); - -/*! - * @brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function can manually assign the specified channel to set the PWM cycle. - * - * @note When setting PWM output from multiple output pins, all should use the same PWM - * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. - * - * @param base Ctimer peripheral base address - * @param pwmPeriodChannel Specify the channel to control the PWM period - * @param matchChannel Match pin to be used to output the PWM signal - * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz Timer counter clock in Hz - * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt will be generated. - */ -status_t CTIMER_SetupPwm(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - bool enableInt); - -/*! - * @brief Updates the pulse period of an active PWM signal. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match pin to be used to output the PWM signal - * @param pulsePeriod New PWM pulse width match value - */ -static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod) -{ - /* Update PWM pulse period match value */ - base->MR[matchChannel] = pulsePeriod; -} - -/*! - * @brief Updates the duty cycle of an active PWM signal. - * - * @note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. - * This function can manually assign the specified channel to set the PWM cycle. - * - * @param base Ctimer peripheral base address - * @param pwmPeriodChannel Specify the channel to control the PWM period - * @param matchChannel Match pin to be used to output the PWM signal - * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 - */ -void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent); - -/*! @}*/ - -/*! - * @brief Setup the match register. - * - * User configuration is used to setup the match value and action to be taken when a match occurs. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match register to configure - * @param config Pointer to the match configuration structure - */ -void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config); - -/*! - * @brief Get the status of output match. - * - * This function gets the status of output MAT, whether or not this output is connected to a pin. - * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - * - * @param base Ctimer peripheral base address - * @param matchChannel External match channel, user can obtain the status of multiple match channels - * at the same time by using the logic of "|" - * enumeration ::ctimer_external_match_t - * @return The mask of external match channel status flags. Users need to use the - * _ctimer_external_match type to decode the return variables. - */ -uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel); - -/*! - * @brief Setup the capture. - * - * @param base Ctimer peripheral base address - * @param capture Capture channel to configure - * @param edge Edge on the channel that will trigger a capture - * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back - * is called upon capture - */ -void CTIMER_SetupCapture(CTIMER_Type *base, - ctimer_capture_channel_t capture, - ctimer_capture_edge_t edge, - bool enableInt); - -/*! - * @brief Get the timer count value from TC register. - * - * @param base Ctimer peripheral base address. - * @return return the timer count value. - */ -static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base) -{ - return (base->TC); -} - -/*! - * @brief Register callback. - * - * @param base Ctimer peripheral base address - * @param cb_func callback function - * @param cb_type callback function type, singular or multiple - */ -void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type); - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected Timer interrupts. - * - * @param base Ctimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) -{ - /* Enable match interrupts */ - base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); - -/* Enable capture interrupts */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - | CTIMER_CCR_CAP2I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - ); -#endif -} - -/*! - * @brief Disables the selected Timer interrupts. - * - * @param base Ctimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) -{ - /* Disable match interrupts */ - base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK)); - -/* Disable capture interrupts */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - | CTIMER_CCR_CAP2I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - )); -#endif -} - -/*! - * @brief Gets the enabled Timer interrupts. - * - * @param base Ctimer peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) -{ - uint32_t enabledIntrs = 0; - - /* Get all the match interrupts enabled */ - enabledIntrs = - base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); - -/* Get all the capture interrupts enabled */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - | CTIMER_CCR_CAP2I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - ); -#endif - - return enabledIntrs; -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the Timer status flags. - * - * @param base Ctimer peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::ctimer_status_flags_t - */ -static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base) -{ - return base->IR; -} - -/*! - * @brief Clears the Timer status flags. - * - * @param base Ctimer peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::ctimer_status_flags_t - */ -static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask) -{ - base->IR = mask; -} - -/*! @}*/ - -/*! - * @name Counter Start and Stop - * @{ - */ - -/*! - * @brief Starts the Timer counter. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_StartTimer(CTIMER_Type *base) -{ - base->TCR |= CTIMER_TCR_CEN_MASK; -} - -/*! - * @brief Stops the Timer counter. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_StopTimer(CTIMER_Type *base) -{ - base->TCR &= ~CTIMER_TCR_CEN_MASK; -} - -/*! @}*/ - -/*! - * @brief Reset the counter. - * - * The timer counter and prescale counter are reset on the next positive edge of the APB clock. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_Reset(CTIMER_Type *base) -{ - base->TCR |= CTIMER_TCR_CRST_MASK; - base->TCR &= ~CTIMER_TCR_CRST_MASK; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_CTIMER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_dma.c deleted file mode 100644 index 6b7bc594ad0..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_dma.c +++ /dev/null @@ -1,1079 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_dma.h" -#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) -#include "fsl_memory.h" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_dma" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for DMA. - * - * @param base DMA peripheral base address. - */ -static uint32_t DMA_GetInstance(DMA_Type *base); - -/*! - * @brief Get virtual channel number. - * - * @param base DMA peripheral base address. - */ -static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map DMA instance number to base pointer. */ -static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map DMA instance number to clock name. */ -static const clock_ip_name_t s_dmaClockName[] = DMA_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET) -/*! @brief Pointers to DMA resets for each instance. */ -static const reset_ip_name_t s_dmaResets[] = DMA_RSTS_N; -#endif /*! @brief Array to map DMA instance number to IRQ number. */ -static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS; - -/*! @brief Pointers to transfer handle for each DMA channel. */ -static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_ALL_CHANNELS]; - -/*! @brief DMA driver internal descriptor table */ -#ifdef FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE -SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE); -#else -#if (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) -AT_NONCACHEABLE_SECTION_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -#else -SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -#endif /* (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) */ -#endif /* FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE */ - -#if defined(DMA1) -#ifdef FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE -SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE); -#else -#if (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) -AT_NONCACHEABLE_SECTION_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -#else -SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -#endif /* (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) */ -#endif /* FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE */ -static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0, s_dma_descriptor_table1}; -#else -static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0}; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t DMA_GetInstance(DMA_Type *base) -{ - uint32_t instance; - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++) - { - if (s_dmaBases[instance] == base) - { - break; - } - } - assert(instance < ARRAY_SIZE(s_dmaBases)); - - return instance; -} - -static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base) -{ - uint32_t startChannel = 0, instance = 0; - uint32_t i = 0; - - instance = DMA_GetInstance(base); - - /* Compute start channel */ - for (i = 0; i < instance; i++) - { - startChannel += (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(s_dmaBases[i]); - } - - return startChannel; -} - -/*! - * brief Initializes DMA peripheral. - * - * This function enable the DMA clock, set descriptor table and - * enable DMA peripheral. - * - * param base DMA peripheral base address. - */ -void DMA_Init(DMA_Type *base) -{ - uint32_t instance = DMA_GetInstance(base); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* enable dma clock gate */ - CLOCK_EnableClock(s_dmaClockName[DMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET) - /* Reset the DMA module */ - RESET_PeripheralReset(s_dmaResets[DMA_GetInstance(base)]); -#endif - /* set descriptor table */ -#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) - base->SRAMBASE = MEMORY_ConvertMemoryMapAddress((uint32_t)s_dma_descriptor_table[instance], kMEMORY_Local2DMA); -#else - base->SRAMBASE = (uint32_t)s_dma_descriptor_table[instance]; -#endif - /* enable dma peripheral */ - base->CTRL |= DMA_CTRL_ENABLE_MASK; -} - -/*! - * brief Deinitializes DMA peripheral. - * - * This function gates the DMA clock. - * - * param base DMA peripheral base address. - */ -void DMA_Deinit(DMA_Type *base) -{ - /* Disable DMA peripheral */ - base->CTRL &= ~(DMA_CTRL_ENABLE_MASK); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(s_dmaClockName[DMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Set trigger settings of DMA channel. - * deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig. - * - * param base DMA peripheral base address. - * param channel DMA channel number. - * param trigger trigger configuration. - */ -void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger) -{ - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); - assert((channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)) && (NULL != trigger)); - - uint32_t tmpReg = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | - DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | - DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK); - tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); - tmpReg |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); - base->CHANNEL[channel].CFG = tmpReg; -} - -/*! - * brief Gets the remaining bytes of the current DMA descriptor transfer. - * - * param base DMA peripheral base address. - * param channel DMA channel number. - * return The number of bytes which have not been transferred yet. - */ -uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) -{ - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); - assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - - /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes - * impossible to distinguish between: - * - transfer finishes (represented by value '0x3FF') - * - and remaining 1024 bytes to transfer (value 0x3FF) - * for all descriptor in chain, except the last one. - * If you decide to use this function, please use 1023 transfers as maximal value */ - - /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */ - if ((!DMA_ChannelIsActive(base, channel)) && - (0x3FFUL == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> - DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))) - { - return 0UL; - } - - return ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> - DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + - 1UL; -} - -/* Verify and convert dma_xfercfg_t to XFERCFG register */ -static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr) -{ - assert(xfercfg != NULL); - /* check source increment */ - assert((xfercfg->srcInc <= (uint8_t)kDMA_AddressInterleave4xWidth) && - (xfercfg->dstInc <= (uint8_t)kDMA_AddressInterleave4xWidth)); - /* check data width */ - assert(xfercfg->byteWidth <= (uint8_t)kDMA_Transfer32BitWidth); - /* check transfer count */ - assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT); - - uint32_t xfer = 0; - - /* set valid flag - descriptor is ready now */ - xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid); - /* set reload - allow link to next descriptor */ - xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload); - /* set swtrig flag - start transfer */ - xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig); - /* set transfer count */ - xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig); - /* set INTA */ - xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA); - /* set INTB */ - xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB); - /* set data width */ - xfer |= DMA_CHANNEL_XFERCFG_WIDTH(xfercfg->byteWidth == 4U ? 2U : xfercfg->byteWidth - 1UL); - /* set source increment value */ - xfer |= DMA_CHANNEL_XFERCFG_SRCINC( - (xfercfg->srcInc == (uint8_t)kDMA_AddressInterleave4xWidth) ? (xfercfg->srcInc - 1UL) : xfercfg->srcInc); - /* set destination increment value */ - xfer |= DMA_CHANNEL_XFERCFG_DSTINC( - (xfercfg->dstInc == (uint8_t)kDMA_AddressInterleave4xWidth) ? (xfercfg->dstInc - 1UL) : xfercfg->dstInc); - /* set transfer count */ - xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1UL); - - /* store xferCFG */ - *xfercfg_addr = xfer; -} - -/*! - * brief setup dma descriptor - * Note: This function do not support configure wrap descriptor. - * param desc DMA descriptor address. - * param xfercfg Transfer configuration for DMA descriptor. - * param srcStartAddr Start address of source address. - * param dstStartAddr Start address of destination address. - * param nextDesc Address of next descriptor in chain. - */ -void DMA_SetupDescriptor( - dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) -{ - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - -#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) - srcStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)srcStartAddr, kMEMORY_Local2DMA); - dstStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)dstStartAddr, kMEMORY_Local2DMA); - nextDesc = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)nextDesc, kMEMORY_Local2DMA); -#endif - - uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; - - width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT; - srcInc = (xfercfg & DMA_CHANNEL_XFERCFG_SRCINC_MASK) >> DMA_CHANNEL_XFERCFG_SRCINC_SHIFT; - dstInc = (xfercfg & DMA_CHANNEL_XFERCFG_DSTINC_MASK) >> DMA_CHANNEL_XFERCFG_DSTINC_SHIFT; - transferCount = ((xfercfg & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1U; - - /* covert register value to actual value */ - if (width == 2U) - { - width = kDMA_Transfer32BitWidth; - } - else - { - width += 1U; - } - - /* - * Transfers of 16 bit width require an address alignment to a multiple of 2 bytes. - * Transfers of 32 bit width require an address alignment to a multiple of 4 bytes. - * Transfers of 8 bit width can be at any address - */ - if (((NULL != srcStartAddr) && (0UL == ((uint32_t)(uint32_t *)srcStartAddr) % width)) && - ((NULL != dstStartAddr) && (0UL == ((uint32_t)(uint32_t *)dstStartAddr) % width))) - { - if (srcInc == 3U) - { - srcInc = kDMA_AddressInterleave4xWidth; - } - - if (dstInc == 3U) - { - dstInc = kDMA_AddressInterleave4xWidth; - } - - desc->xfercfg = xfercfg; - desc->srcEndAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); - desc->dstEndAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); - desc->linkToNextDesc = nextDesc; - } - else - { - /* if address alignment not satisfy the requirement, reset the descriptor to make sure DMA generate error */ - desc->xfercfg = 0U; - desc->srcEndAddr = NULL; - desc->dstEndAddr = NULL; - } -} - -/*! - * brief setup dma channel descriptor - * Note: This function support configure wrap descriptor. - * param desc DMA descriptor address. - * param xfercfg Transfer configuration for DMA descriptor. - * param srcStartAddr Start address of source address. - * param dstStartAddr Start address of destination address. - * param nextDesc Address of next descriptor in chain. - * param wrapType burst wrap type. - * param burstSize burst size, reference _dma_burst_size. - */ -void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, - uint32_t xfercfg, - void *srcStartAddr, - void *dstStartAddr, - void *nextDesc, - dma_burst_wrap_t wrapType, - uint32_t burstSize) -{ - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - -#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) - srcStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)srcStartAddr, kMEMORY_Local2DMA); - dstStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)dstStartAddr, kMEMORY_Local2DMA); - nextDesc = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)nextDesc, kMEMORY_Local2DMA); -#endif - - uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; - - width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT; - srcInc = (xfercfg & DMA_CHANNEL_XFERCFG_SRCINC_MASK) >> DMA_CHANNEL_XFERCFG_SRCINC_SHIFT; - dstInc = (xfercfg & DMA_CHANNEL_XFERCFG_DSTINC_MASK) >> DMA_CHANNEL_XFERCFG_DSTINC_SHIFT; - transferCount = ((xfercfg & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1U; - - /* covert register value to actual value */ - if (width == 2U) - { - width = kDMA_Transfer32BitWidth; - } - else - { - width += 1U; - } - - /* - * Transfers of 16 bit width require an address alignment to a multiple of 2 bytes. - * Transfers of 32 bit width require an address alignment to a multiple of 4 bytes. - * Transfers of 8 bit width can be at any address - */ - if (((NULL != srcStartAddr) && (0UL == ((uint32_t)(uint32_t *)srcStartAddr) % width)) && - ((NULL != dstStartAddr) && (0UL == ((uint32_t)(uint32_t *)dstStartAddr) % width))) - { - if (srcInc == 3U) - { - srcInc = kDMA_AddressInterleave4xWidth; - } - - if (dstInc == 3U) - { - dstInc = kDMA_AddressInterleave4xWidth; - } - - desc->xfercfg = xfercfg; - - if (wrapType == kDMA_NoWrap) - { - desc->srcEndAddr = - DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); - desc->dstEndAddr = - DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); - } - /* for the wrap transfer, the destination address should be determined by the burstSize/width/interleave size */ - if (wrapType == kDMA_SrcWrap) - { - desc->srcEndAddr = - (uint32_t *)((uint32_t)(uint32_t *)srcStartAddr + ((1UL << burstSize) - 1UL) * width * srcInc); - desc->dstEndAddr = - DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); - } - if (wrapType == kDMA_DstWrap) - { - desc->srcEndAddr = - DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); - desc->dstEndAddr = - (uint32_t *)((uint32_t)(uint32_t *)dstStartAddr + ((1UL << burstSize) - 1UL) * width * dstInc); - } - if (wrapType == kDMA_SrcAndDstWrap) - { - desc->srcEndAddr = - (uint32_t *)(((uint32_t)(uint32_t *)srcStartAddr) + ((1UL << burstSize) - 1UL) * width * srcInc); - desc->dstEndAddr = - (uint32_t *)(((uint32_t)(uint32_t *)dstStartAddr) + ((1UL << burstSize) - 1UL) * width * dstInc); - } - - desc->linkToNextDesc = nextDesc; - } - else - { - /* if address alignment not satisfy the requirement, reset the descriptor to make sure DMA generate error */ - desc->xfercfg = 0U; - desc->srcEndAddr = NULL; - desc->dstEndAddr = NULL; - } -} - -/*! - * brief Create application specific DMA descriptor - * to be used in a chain in transfer - * deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor - * param desc DMA descriptor address. - * param xfercfg Transfer configuration for DMA descriptor. - * param srcAddr Address of last item to transmit - * param dstAddr Address of last item to receive. - * param nextDesc Address of next descriptor in chain. - */ -void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc) -{ - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - assert((NULL != srcAddr) && (0UL == ((uint32_t)(uint32_t *)srcAddr) % xfercfg->byteWidth)); - assert((NULL != dstAddr) && (0UL == ((uint32_t)(uint32_t *)dstAddr) % xfercfg->byteWidth)); - - uint32_t xfercfg_reg = 0; - - DMA_SetupXferCFG(xfercfg, &xfercfg_reg); - - /* Set descriptor structure */ - DMA_SetupDescriptor(desc, xfercfg_reg, srcAddr, dstAddr, nextDesc); -} - -/*! - * brief Abort running transfer by handle. - * - * This function aborts DMA transfer specified by handle. - * - * param handle DMA handle pointer. - */ -void DMA_AbortTransfer(dma_handle_t *handle) -{ - assert(NULL != handle); - - DMA_DisableChannel(handle->base, handle->channel); - while ((DMA_COMMON_CONST_REG_GET(handle->base, handle->channel, BUSY) & - (1UL << DMA_CHANNEL_INDEX(handle->base, handle->channel))) != 0UL) - { - } - DMA_COMMON_REG_GET(handle->base, handle->channel, ABORT) |= 1UL << DMA_CHANNEL_INDEX(handle->base, handle->channel); - DMA_EnableChannel(handle->base, handle->channel); -} - -/*! - * brief Creates the DMA handle. - * - * This function is called if using transaction API for DMA. This function - * initializes the internal state of DMA handle. - * - * param handle DMA handle pointer. The DMA handle stores callback function and - * parameters. - * param base DMA peripheral base address. - * param channel DMA channel number. - */ -void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel) -{ - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); - assert((NULL != handle) && (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - - uint32_t dmaInstance; - uint32_t startChannel = 0; - /* base address is invalid DMA instance */ - dmaInstance = DMA_GetInstance(base); - startChannel = DMA_GetVirtualStartChannel(base); - - (void)memset(handle, 0, sizeof(*handle)); - handle->base = base; - handle->channel = (uint8_t)channel; - s_DMAHandle[startChannel + channel] = handle; - /* Enable NVIC interrupt */ - (void)EnableIRQ(s_dmaIRQNumber[dmaInstance]); - /* Enable channel interrupt */ - DMA_EnableChannelInterrupts(handle->base, channel); -} - -/*! - * brief Installs a callback function for the DMA transfer. - * - * This callback is called in DMA IRQ handler. Use the callback to do something after - * the current major loop transfer completes. - * - * param handle DMA handle pointer. - * param callback DMA callback function pointer. - * param userData Parameter for callback function. - */ -void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData) -{ - assert(handle != NULL); - - handle->callback = callback; - handle->userData = userData; -} - -/*! - * brief Prepares the DMA transfer structure. - * deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer and - * DMA_PrepareChannelXfer. - * This function prepares the transfer configuration structure according to the user input. - * - * param config The user configuration structure of type dma_transfer_t. - * param srcAddr DMA transfer source address. - * param dstAddr DMA transfer destination address. - * param byteWidth DMA transfer destination address width(bytes). - * param transferBytes DMA transfer bytes to be transferred. - * param type DMA transfer type. - * param nextDesc Chain custom descriptor to transfer. - * note The data address and the data width must be consistent. For example, if the SRC - * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in - * source address error(SAE). - */ -void DMA_PrepareTransfer(dma_transfer_config_t *config, - void *srcAddr, - void *dstAddr, - uint32_t byteWidth, - uint32_t transferBytes, - dma_transfer_type_t type, - void *nextDesc) -{ - uint32_t xfer_count; - assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr)); - assert((byteWidth == 1UL) || (byteWidth == 2UL) || (byteWidth == 4UL)); - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - - /* check max */ - xfer_count = transferBytes / byteWidth; - assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0UL == transferBytes % byteWidth)); - - (void)memset(config, 0, sizeof(*config)); - - if (type == kDMA_MemoryToMemory) - { - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 1; - config->isPeriph = false; - } - - else if (type == kDMA_PeripheralToMemory) - { - /* Peripheral register - source doesn't increment */ - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 1; - config->isPeriph = true; - } - else if (type == kDMA_MemoryToPeripheral) - { - /* Peripheral register - destination doesn't increment */ - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - } - /* kDMA_StaticToStatic */ - else - { - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - } - - config->dstAddr = (uint8_t *)dstAddr; - config->srcAddr = (uint8_t *)srcAddr; - config->nextDesc = (uint8_t *)nextDesc; - config->xfercfg.transferCount = (uint16_t)xfer_count; - config->xfercfg.byteWidth = (uint8_t)byteWidth; - config->xfercfg.intA = true; - config->xfercfg.reload = nextDesc != NULL; - config->xfercfg.valid = true; -} - -/*! - * brief set channel config. - * - * This function provide a interface to configure channel configuration reisters. - * - * param base DMA base address. - * param channel DMA channel number. - * param config channel configurations structure. - */ -void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph) -{ - assert(channel < (uint32_t)FSL_FEATURE_DMA_MAX_CHANNELS); - - uint32_t tmpReg = DMA_CHANNEL_CFG_PERIPHREQEN_MASK; - - if (trigger != NULL) - { - tmpReg |= DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | - DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | - DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK; - } - - tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); - - if (trigger != NULL) - { - tmpReg |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); - } - - tmpReg |= DMA_CHANNEL_CFG_PERIPHREQEN(isPeriph); - - base->CHANNEL[channel].CFG = tmpReg; -} - -/*! - * brief Prepare channel transfer configurations. - * - * This function used to prepare channel transfer configurations. - * - * param config Pointer to DMA channel transfer configuration structure. - * param srcStartAddr source start address. - * param dstStartAddr destination start address. - * param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * param type transfer type. - * param trigger DMA channel trigger configurations. - * param nextDesc address of next descriptor. - */ -void DMA_PrepareChannelTransfer(dma_channel_config_t *config, - void *srcStartAddr, - void *dstStartAddr, - uint32_t xferCfg, - dma_transfer_type_t type, - dma_channel_trigger_t *trigger, - void *nextDesc) -{ - assert((NULL != config) && (NULL != srcStartAddr) && (NULL != dstStartAddr)); - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - - /* check max */ - (void)memset(config, 0, sizeof(*config)); - - if (type == kDMA_MemoryToMemory) - { - config->isPeriph = false; - } - else if (type == kDMA_PeripheralToMemory) - { - config->isPeriph = true; - } - else if (type == kDMA_MemoryToPeripheral) - { - config->isPeriph = true; - } - /* kDMA_StaticToStatic */ - else - { - config->isPeriph = true; - } - - config->dstStartAddr = (uint8_t *)dstStartAddr; - config->srcStartAddr = (uint8_t *)srcStartAddr; - config->nextDesc = (uint8_t *)nextDesc; - config->trigger = trigger; - config->xferCfg = xferCfg; -} - -/*! - * brief load channel transfer decriptor. - * - * This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA - * transfer, the head descriptor table is defined in DMA driver, it is useful for the case: - * 1. for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly - * and then call this api to load the configured descriptor to driver descriptor table. code DMA_Init(DMA0); - * DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL); - * DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL); - * DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc); - * DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL); - * while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL)) - * {} - * endcode - * - * param base DMA base address. - * param channel DMA channel. - * param descriptor configured DMA descriptor. - */ -void DMA_LoadChannelDescriptor(DMA_Type *base, uint32_t channel, dma_descriptor_t *descriptor) -{ - assert(NULL != descriptor); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); - assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - - uint32_t instance = DMA_GetInstance(base); - dma_descriptor_t *channelDescriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][channel]); - - channelDescriptor->xfercfg = descriptor->xfercfg; - channelDescriptor->srcEndAddr = descriptor->srcEndAddr; - channelDescriptor->dstEndAddr = descriptor->dstEndAddr; - channelDescriptor->linkToNextDesc = descriptor->linkToNextDesc; - - /* Set channel XFERCFG register according first channel descriptor. */ - base->CHANNEL[channel].XFERCFG = descriptor->xfercfg; -} - -/*! - * brief Install DMA descriptor memory. - * - * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong - * transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has - * a default DMA descriptor buffer, but it support one DMA descriptor for one channel only. - * User should be take care about the address of DMA descriptor pool which required align with 512BYTE. - * - * param handle Pointer to DMA channel transfer handle. - * param addr DMA descriptor address - * param num DMA descriptor number. - */ -void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr) -{ - assert(addr != NULL); - -#if defined FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn - assert((((uint32_t)(uint32_t *)addr) & ((uint32_t)FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn(base) - 1UL)) == 0U); -#else - assert((((uint32_t)(uint32_t *)addr) & ((uint32_t)FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0U); -#endif - /* reconfigure the DMA descriptor base address */ - base->SRAMBASE = (uint32_t)(uint32_t *)addr; -} - -/*! - * brief Submit channel transfer paramter directly. - * - * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table - * is defined in DMA driver, it is useful for the case: - * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used - for it. - * code - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, - bytes), srcStartAddr, dstStartAddr, NULL); - DMA_StartTransfer(handle) - * endcode - * - * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is - required, then application should prepare - * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc2); - DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, NULL); - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, - bytes), srcStartAddr, dstStartAddr, nextDesc0); - DMA_StartTransfer(handle); - * endcode - * - * param handle Pointer to DMA handle. - * param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * param srcStartAddr source start address. - * param dstStartAddr destination start address. - * param nextDesc address of next descriptor. - */ -void DMA_SubmitChannelTransferParameter( - dma_handle_t *handle, uint32_t xferCfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) -{ - assert((NULL != srcStartAddr) && (NULL != dstStartAddr)); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); - assert(handle->channel < (uint8_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - - uint32_t instance = DMA_GetInstance(handle->base); - dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); - - DMA_SetupDescriptor(descriptor, xferCfg, srcStartAddr, dstStartAddr, nextDesc); - - /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = xferCfg; -} - -/*! - * brief Submit channel descriptor. - * - * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table - is defined in - * DMA driver, this functiono is typical for the ping pong case: - * - * 1. for the ping pong case, application should responsible for the descriptor, for example, application should - * prepare two descriptor table with macro. - * code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc0); - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelDescriptor(handle, nextDesc0); - DMA_StartTransfer(handle); - * endcode - * - * param handle Pointer to DMA handle. - * param descriptor descriptor to submit. - */ -void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descriptor) -{ - assert((NULL != handle) && (NULL != descriptor)); - - DMA_LoadChannelDescriptor(handle->base, handle->channel, descriptor); -} - -/*! - * brief Submits the DMA channel transfer request. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * It is used for the case: - * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used - for it. - * code - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,NULL); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * endcode - * - * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is - required, then application should prepare - * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc2); - DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, NULL); - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * endcode - * - * 3. for the ping pong case, application should responsible for link descriptor, for example, application should - prepare - * two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc0); - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * endcode - * param handle DMA handle pointer. - * param config Pointer to DMA transfer configuration structure. - * retval kStatus_DMA_Success It means submit transfer request succeed. - * retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config) -{ - assert((NULL != handle) && (NULL != config)); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); - assert(handle->channel < (uint8_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - uint32_t instance = DMA_GetInstance(handle->base); - dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); - - /* Previous transfer has not finished */ - if (DMA_ChannelIsActive(handle->base, handle->channel)) - { - return kStatus_DMA_Busy; - } - - /* setup channgel trigger configurations */ - DMA_SetChannelConfig(handle->base, handle->channel, config->trigger, config->isPeriph); - - DMA_SetupChannelDescriptor( - descriptor, config->xferCfg, config->srcStartAddr, config->dstStartAddr, config->nextDesc, - config->trigger == NULL ? kDMA_NoWrap : config->trigger->wrap, - (config->trigger == NULL ? (uint32_t)kDMA_BurstSize1 : - ((uint32_t)config->trigger->burst & (DMA_CHANNEL_CFG_BURSTPOWER_MASK)) >> - DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)); - - /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = config->xferCfg; - - return kStatus_Success; -} - -/*! - * brief Submits the DMA transfer request. - * deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * - * param handle DMA handle pointer. - * param config Pointer to DMA transfer configuration structure. - * retval kStatus_DMA_Success It means submit transfer request succeed. - * retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) -{ - assert((NULL != handle) && (NULL != config)); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); - assert(handle->channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - - uint32_t instance = DMA_GetInstance(handle->base); - dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); - - /* Previous transfer has not finished */ - if (DMA_ChannelIsActive(handle->base, handle->channel)) - { - return kStatus_DMA_Busy; - } - - /* enable/disable peripheral request */ - if (config->isPeriph) - { - DMA_EnableChannelPeriphRq(handle->base, handle->channel); - } - else - { - DMA_DisableChannelPeriphRq(handle->base, handle->channel); - } - - DMA_CreateDescriptor(descriptor, &config->xfercfg, config->srcAddr, config->dstAddr, config->nextDesc); - /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = descriptor->xfercfg; - - return kStatus_Success; -} - -/*! - * brief DMA start transfer. - * - * This function enables the channel request. User can call this function after submitting the transfer request - * It will trigger transfer start with software trigger only when hardware trigger is not used. - * - * param handle DMA handle pointer. - */ -void DMA_StartTransfer(dma_handle_t *handle) -{ - assert(NULL != handle); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); - - uint32_t channel = handle->channel; - assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - - /* enable channel */ - DMA_EnableChannel(handle->base, channel); - - /* Do software trigger only when HW trigger is not enabled. */ - if ((handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK) == 0U) - { - handle->base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; - } -} - -void DMA_IRQHandle(DMA_Type *base) -{ - dma_handle_t *handle; - uint8_t channel_index; - uint32_t startChannel = DMA_GetVirtualStartChannel(base); - uint32_t i = 0; - bool intEnabled = false, intA = false, intB = false; - - /* Find channels that have completed transfer */ - for (i = 0; i < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base); i++) - { - handle = s_DMAHandle[i + startChannel]; - /* Handle is not present */ - if (NULL == handle) - { - continue; - } - channel_index = DMA_CHANNEL_INDEX(base, handle->channel); - /* Channel uses INTA flag */ - intEnabled = ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTENSET) & (1UL << channel_index)) != 0UL); - intA = ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTA) & (1UL << channel_index)) != 0UL); - if (intEnabled && intA) - { - /* Clear INTA flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, INTA, (1UL << channel_index)); - if (handle->callback != NULL) - { - (handle->callback)(handle, handle->userData, true, kDMA_IntA); - } - } - - intB = ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTB) & (1UL << channel_index)) != 0UL); - /* Channel uses INTB flag */ - if (intEnabled && intB) - { - /* Clear INTB flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, INTB, (1UL << channel_index)); - if (handle->callback != NULL) - { - (handle->callback)(handle, handle->userData, true, kDMA_IntB); - } - } - /* Error flag */ - if ((DMA_COMMON_REG_GET(handle->base, handle->channel, ERRINT) & (1UL << channel_index)) != 0UL) - { - /* Clear error flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, ERRINT, (1UL << channel_index)); - if (handle->callback != NULL) - { - (handle->callback)(handle, handle->userData, false, kDMA_IntError); - } - } - } -} - -void DMA0_DriverIRQHandler(void); -void DMA0_DriverIRQHandler(void) -{ - DMA_IRQHandle(DMA0); - SDK_ISR_EXIT_BARRIER; -} - -#if defined(DMA1) -void DMA1_DriverIRQHandler(void); -void DMA1_DriverIRQHandler(void) -{ - DMA_IRQHandle(DMA1); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_dma.h deleted file mode 100644 index 0e857752e58..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_dma.h +++ /dev/null @@ -1,892 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_DMA_H_ -#define _FSL_DMA_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup dma - * @{ - */ - -/*! @file */ -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief DMA driver version */ -#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 4)) /*!< Version 2.4.4. */ -/*@}*/ - -/*! @brief DMA max transfer size */ -#define DMA_MAX_TRANSFER_COUNT 0x400U -/*! @brief DMA channel numbers */ -#if defined FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_MAX_CHANNELS FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_ALL_CHANNELS (FSL_FEATURE_DMA_NUMBER_OF_CHANNELS * FSL_FEATURE_SOC_DMA_COUNT) -#endif -/*! @brief DMA head link descriptor table align size */ -#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) -/*! @brief DMA head descriptor table allocate macro - * To simplify user interface, this macro will help allocate descriptor memory, - * user just need to provide the name and the number for the allocate descriptor. - * - * @param name Allocate decriptor name. - * @param number Number of descriptor to be allocated. - */ -#define DMA_ALLOCATE_HEAD_DESCRIPTORS(name, number) \ - SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE) -/*! @brief DMA head descriptor table allocate macro at noncacheable section - * To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, - * user just need to provide the name and the number for the allocate descriptor. - * - * @param name Allocate decriptor name. - * @param number Number of descriptor to be allocated. - */ -#define DMA_ALLOCATE_HEAD_DESCRIPTORS_AT_NONCACHEABLE(name, number) \ - AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE) -/*! @brief DMA link descriptor table allocate macro - * To simplify user interface, this macro will help allocate descriptor memory, - * user just need to provide the name and the number for the allocate descriptor. - * - * @param name Allocate decriptor name. - * @param number Number of descriptor to be allocated. - */ -#define DMA_ALLOCATE_LINK_DESCRIPTORS(name, number) \ - SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE) -/*! @brief DMA link descriptor table allocate macro at noncacheable section - * To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, - * user just need to provide the name and the number for the allocate descriptor. - * - * @param name Allocate decriptor name. - * @param number Number of descriptor to be allocated. - */ -#define DMA_ALLOCATE_LINK_DESCRIPTORS_AT_NONCACHEABLE(name, number) \ - AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE) -/*! @brief DMA transfer buffer address need to align with the transfer width */ -#define DMA_ALLOCATE_DATA_TRANSFER_BUFFER(name, width) SDK_ALIGN(name, width) -/* Channel group consists of 32 channels. channel_group = 0 */ -#define DMA_CHANNEL_GROUP(channel) (((uint8_t)(channel)) >> 5U) -/* Channel index in channel group. channel_index = (channel % (channel number per instance)) */ -#define DMA_CHANNEL_INDEX(base, channel) (((uint8_t)(channel)) & 0x1FU) -/*! @brief DMA linked descriptor address algin size */ -#define DMA_COMMON_REG_GET(base, channel, reg) \ - (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) -#define DMA_COMMON_CONST_REG_GET(base, channel, reg) \ - (((volatile const uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) -#define DMA_COMMON_REG_SET(base, channel, reg, value) \ - (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)] = (value)) - -/*! @brief DMA descriptor end address calculate - * @param start start address - * @param inc address interleave size - * @param bytes transfer bytes - * @param width transfer width - */ -#define DMA_DESCRIPTOR_END_ADDRESS(start, inc, bytes, width) \ - ((uint32_t *)((uint32_t)(start) + (inc) * (bytes) - (inc) * (width))) - -/*! @brief DMA channel transfer configurations macro - * @param reload true is reload link descriptor after current exhaust, false is not - * @param clrTrig true is clear trigger status, wait software trigger, false is not - * @param intA enable interruptA - * @param intB enable interruptB - * @param width transfer width - * @param srcInc source address interleave size - * @param dstInc destination address interleave size - * @param bytes transfer bytes - */ -#define DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes) \ - DMA_CHANNEL_XFERCFG_CFGVALID_MASK | DMA_CHANNEL_XFERCFG_RELOAD(reload) | DMA_CHANNEL_XFERCFG_CLRTRIG(clrTrig) | \ - DMA_CHANNEL_XFERCFG_SETINTA(intA) | DMA_CHANNEL_XFERCFG_SETINTB(intB) | \ - DMA_CHANNEL_XFERCFG_WIDTH(width == 4UL ? 2UL : (width - 1UL)) | \ - DMA_CHANNEL_XFERCFG_SRCINC(srcInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (srcInc - 1UL) : srcInc) | \ - DMA_CHANNEL_XFERCFG_DSTINC(dstInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (dstInc - 1UL) : dstInc) | \ - DMA_CHANNEL_XFERCFG_XFERCOUNT(bytes / width - 1UL) - -/*! @brief _dma_transfer_status DMA transfer status */ -enum -{ - kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the - transfer request. */ -}; - -/*! @brief _dma_addr_interleave_size dma address interleave size */ -enum -{ - kDMA_AddressInterleave0xWidth = 0U, /*!< dma source/destination address no interleave */ - kDMA_AddressInterleave1xWidth = 1U, /*!< dma source/destination address interleave 1xwidth */ - kDMA_AddressInterleave2xWidth = 2U, /*!< dma source/destination address interleave 2xwidth */ - kDMA_AddressInterleave4xWidth = 4U, /*!< dma source/destination address interleave 3xwidth */ -}; - -/*! @brief _dma_transfer_width dma transfer width */ -enum -{ - kDMA_Transfer8BitWidth = 1U, /*!< dma channel transfer bit width is 8 bit */ - kDMA_Transfer16BitWidth = 2U, /*!< dma channel transfer bit width is 16 bit */ - kDMA_Transfer32BitWidth = 4U, /*!< dma channel transfer bit width is 32 bit */ -}; - -/*! @brief DMA descriptor structure */ -typedef struct _dma_descriptor -{ - volatile uint32_t xfercfg; /*!< Transfer configuration */ - void *srcEndAddr; /*!< Last source address of DMA transfer */ - void *dstEndAddr; /*!< Last destination address of DMA transfer */ - void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */ -} dma_descriptor_t; - -/*! @brief DMA transfer configuration */ -typedef struct _dma_xfercfg -{ - bool valid; /*!< Descriptor is ready to transfer */ - bool reload; /*!< Reload channel configuration register after - current descriptor is exhausted */ - bool swtrig; /*!< Perform software trigger. Transfer if fired - when 'valid' is set */ - bool clrtrig; /*!< Clear trigger */ - bool intA; /*!< Raises IRQ when transfer is done and set IRQA status register flag */ - bool intB; /*!< Raises IRQ when transfer is done and set IRQB status register flag */ - uint8_t byteWidth; /*!< Byte width of data to transfer */ - uint8_t srcInc; /*!< Increment source address by 'srcInc' x 'byteWidth' */ - uint8_t dstInc; /*!< Increment destination address by 'dstInc' x 'byteWidth' */ - uint16_t transferCount; /*!< Number of transfers */ -} dma_xfercfg_t; - -/*! @brief DMA channel priority */ -typedef enum _dma_priority -{ - kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */ - kDMA_ChannelPriority1, /*!< Channel priority 1 */ - kDMA_ChannelPriority2, /*!< Channel priority 2 */ - kDMA_ChannelPriority3, /*!< Channel priority 3 */ - kDMA_ChannelPriority4, /*!< Channel priority 4 */ - kDMA_ChannelPriority5, /*!< Channel priority 5 */ - kDMA_ChannelPriority6, /*!< Channel priority 6 */ - kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */ -} dma_priority_t; - -/*! @brief DMA interrupt flags */ -typedef enum _dma_int -{ - kDMA_IntA, /*!< DMA interrupt flag A */ - kDMA_IntB, /*!< DMA interrupt flag B */ - kDMA_IntError, /*!< DMA interrupt flag error */ -} dma_irq_t; - -/*! @brief DMA trigger type*/ -typedef enum _dma_trigger_type -{ - kDMA_NoTrigger = 0, /*!< Trigger is disabled */ - kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */ - kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | - DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */ - kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */ - kDMA_RisingEdgeTrigger = - DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */ -} dma_trigger_type_t; - -/*! @brief _dma_burst_size DMA burst size*/ -enum -{ - kDMA_BurstSize1 = 0U, /*!< burst size 1 transfer */ - kDMA_BurstSize2 = 1U, /*!< burst size 2 transfer */ - kDMA_BurstSize4 = 2U, /*!< burst size 4 transfer */ - kDMA_BurstSize8 = 3U, /*!< burst size 8 transfer */ - kDMA_BurstSize16 = 4U, /*!< burst size 16 transfer */ - kDMA_BurstSize32 = 5U, /*!< burst size 32 transfer */ - kDMA_BurstSize64 = 6U, /*!< burst size 64 transfer */ - kDMA_BurstSize128 = 7U, /*!< burst size 128 transfer */ - kDMA_BurstSize256 = 8U, /*!< burst size 256 transfer */ - kDMA_BurstSize512 = 9U, /*!< burst size 512 transfer */ - kDMA_BurstSize1024 = 10U, /*!< burst size 1024 transfer */ -}; - -/*! @brief DMA trigger burst */ -typedef enum _dma_trigger_burst -{ - kDMA_SingleTransfer = 0, /*!< Single transfer */ - kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */ - kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */ - kDMA_EdgeBurstTransfer2 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */ - kDMA_EdgeBurstTransfer4 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */ - kDMA_EdgeBurstTransfer8 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */ - kDMA_EdgeBurstTransfer16 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */ - kDMA_EdgeBurstTransfer32 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */ - kDMA_EdgeBurstTransfer64 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */ - kDMA_EdgeBurstTransfer128 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */ - kDMA_EdgeBurstTransfer256 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */ - kDMA_EdgeBurstTransfer512 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */ - kDMA_EdgeBurstTransfer1024 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */ -} dma_trigger_burst_t; - -/*! @brief DMA burst wrapping */ -typedef enum _dma_burst_wrap -{ - kDMA_NoWrap = 0, /*!< Wrapping is disabled */ - kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */ - kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */ - kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | - DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */ -} dma_burst_wrap_t; - -/*! @brief DMA transfer type */ -typedef enum _dma_transfer_type -{ - kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */ - kDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory (increment only destination) */ - kDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral (increment only source)*/ - kDMA_StaticToStatic, /*!< Peripheral to static memory (do not increment source or destination) */ -} dma_transfer_type_t; - -/*! @brief DMA channel trigger */ -typedef struct _dma_channel_trigger -{ - dma_trigger_type_t type; /*!< Select hardware trigger as edge triggered or level triggered. */ - dma_trigger_burst_t burst; /*!< Select whether hardware triggers cause a single or burst transfer. */ - dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */ -} dma_channel_trigger_t; - -/*! @brief DMA channel trigger */ -typedef struct _dma_channel_config -{ - void *srcStartAddr; /*!< Source data address */ - void *dstStartAddr; /*!< Destination data address */ - void *nextDesc; /*!< Chain custom descriptor */ - uint32_t xferCfg; /*!< channel transfer configurations */ - dma_channel_trigger_t *trigger; /*!< DMA trigger type */ - bool isPeriph; /*!< select the request type */ -} dma_channel_config_t; - -/*! @brief DMA transfer configuration */ -typedef struct _dma_transfer_config -{ - uint8_t *srcAddr; /*!< Source data address */ - uint8_t *dstAddr; /*!< Destination data address */ - uint8_t *nextDesc; /*!< Chain custom descriptor */ - dma_xfercfg_t xfercfg; /*!< Transfer options */ - bool isPeriph; /*!< DMA transfer is driven by peripheral */ -} dma_transfer_config_t; - -/*! @brief Callback for DMA */ -struct _dma_handle; - -/*! @brief Define Callback function for DMA. */ -typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode); - -/*! @brief DMA transfer handle structure */ -typedef struct _dma_handle -{ - dma_callback callback; /*!< Callback function. Invoked when transfer - of descriptor with interrupt flag finishes */ - void *userData; /*!< Callback function parameter */ - DMA_Type *base; /*!< DMA peripheral base address */ - uint8_t channel; /*!< DMA channel number */ -} dma_handle_t; - -/******************************************************************************* - * APIs - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name DMA initialization and De-initialization - * @{ - */ - -/*! - * @brief Initializes DMA peripheral. - * - * This function enable the DMA clock, set descriptor table and - * enable DMA peripheral. - * - * @param base DMA peripheral base address. - */ -void DMA_Init(DMA_Type *base); - -/*! - * @brief Deinitializes DMA peripheral. - * - * This function gates the DMA clock. - * - * @param base DMA peripheral base address. - */ -void DMA_Deinit(DMA_Type *base); - -/*! - * @brief Install DMA descriptor memory. - * - * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong - * transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has - * a default DMA descriptor buffer, but it support one DMA descriptor for one channel only. - * - * @param base DMA base address. - * @param addr DMA descriptor address - */ -void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr); - -/* @} */ - -/*! - * @name DMA Channel Operation - * @{ - */ - -/*! - * @brief Return whether DMA channel is processing transfer - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return True for active state, false otherwise. - */ -static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - - return (DMA_COMMON_CONST_REG_GET(base, channel, ACTIVE) & (1UL << DMA_CHANNEL_INDEX(base, channel))) != 0UL; -} - -/*! - * @brief Return whether DMA channel is busy - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return True for busy state, false otherwise. - */ -static inline bool DMA_ChannelIsBusy(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - - return (DMA_COMMON_CONST_REG_GET(base, channel, BUSY) & (1UL << DMA_CHANNEL_INDEX(base, channel))) != 0UL; -} - -/*! - * @brief Enables the interrupt source for the DMA transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - DMA_COMMON_REG_GET(base, channel, INTENSET) |= 1UL << DMA_CHANNEL_INDEX(base, channel); -} - -/*! - * @brief Disables the interrupt source for the DMA transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - DMA_COMMON_REG_GET(base, channel, INTENCLR) |= 1UL << DMA_CHANNEL_INDEX(base, channel); -} - -/*! - * @brief Enable DMA channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - DMA_COMMON_REG_GET(base, channel, ENABLESET) |= 1UL << DMA_CHANNEL_INDEX(base, channel); -} - -/*! - * @brief Disable DMA channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - DMA_COMMON_REG_GET(base, channel, ENABLECLR) |= 1UL << DMA_CHANNEL_INDEX(base, channel); -} - -/*! - * @brief Set PERIPHREQEN of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK; -} - -/*! - * @brief Get PERIPHREQEN value of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return True for enabled PeriphRq, false for disabled. - */ -static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK; -} - -/*! - * @brief Set trigger settings of DMA channel. - * @deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param trigger trigger configuration. - */ -void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger); - -/*! - * @brief set channel config. - * - * This function provide a interface to configure channel configuration reisters. - * - * @param base DMA base address. - * @param channel DMA channel number. - * @param trigger channel configurations structure. - * @param isPeriph true is periph request, false is not. - */ -void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph); - -/*! - * @brief Gets the remaining bytes of the current DMA descriptor transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return The number of bytes which have not been transferred yet. - */ -uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel); - -/*! - * @brief Set priority of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param priority Channel priority value. - */ -static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - base->CHANNEL[channel].CFG = - (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority); -} - -/*! - * @brief Get priority of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return Channel priority value. - */ -static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - return (dma_priority_t)(uint8_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> - DMA_CHANNEL_CFG_CHPRIORITY_SHIFT); -} - -/*! - * @brief Set channel configuration valid. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_SetChannelConfigValid(DMA_Type *base, uint32_t channel) -{ - base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_CFGVALID_MASK; -} - -/*! - * @brief Do software trigger for the channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DoChannelSoftwareTrigger(DMA_Type *base, uint32_t channel) -{ - base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; -} - -/*! - * @brief Load channel transfer configurations. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param xfer transfer configurations. - */ -static inline void DMA_LoadChannelTransferConfig(DMA_Type *base, uint32_t channel, uint32_t xfer) -{ - base->CHANNEL[channel].XFERCFG = xfer; -} - -/*! - * @brief Create application specific DMA descriptor - * to be used in a chain in transfer - * @deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor. - * @param desc DMA descriptor address. - * @param xfercfg Transfer configuration for DMA descriptor. - * @param srcAddr Address of last item to transmit - * @param dstAddr Address of last item to receive. - * @param nextDesc Address of next descriptor in chain. - */ -void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc); - -/*! - * @brief setup dma descriptor - * - * Note: This function do not support configure wrap descriptor. - * - * @param desc DMA descriptor address. - * @param xfercfg Transfer configuration for DMA descriptor. - * @param srcStartAddr Start address of source address. - * @param dstStartAddr Start address of destination address. - * @param nextDesc Address of next descriptor in chain. - */ -void DMA_SetupDescriptor( - dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc); - -/*! - * @brief setup dma channel descriptor - * - * Note: This function support configure wrap descriptor. - * - * @param desc DMA descriptor address. - * @param xfercfg Transfer configuration for DMA descriptor. - * @param srcStartAddr Start address of source address. - * @param dstStartAddr Start address of destination address. - * @param nextDesc Address of next descriptor in chain. - * @param wrapType burst wrap type. - * @param burstSize burst size, reference _dma_burst_size. - */ -void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, - uint32_t xfercfg, - void *srcStartAddr, - void *dstStartAddr, - void *nextDesc, - dma_burst_wrap_t wrapType, - uint32_t burstSize); - -/*! - * @brief load channel transfer decriptor. - * - * This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA - * transfer, the head descriptor table is defined in DMA driver, it is useful for the case: - * 1. for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly - * and then call this api to load the configured descriptor to driver descriptor table. - * @code - * DMA_Init(DMA0); - * DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL); - * DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL); - * DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc); - * DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL); - * while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL)) - * {} - * @endcode - * - * @param base DMA base address. - * @param channel DMA channel. - * @param descriptor configured DMA descriptor. - */ -void DMA_LoadChannelDescriptor(DMA_Type *base, uint32_t channel, dma_descriptor_t *descriptor); - -/* @} */ - -/*! - * @name DMA Transactional Operation - * @{ - */ - -/*! - * @brief Abort running transfer by handle. - * - * This function aborts DMA transfer specified by handle. - * - * @param handle DMA handle pointer. - */ -void DMA_AbortTransfer(dma_handle_t *handle); - -/*! - * @brief Creates the DMA handle. - * - * This function is called if using transaction API for DMA. This function - * initializes the internal state of DMA handle. - * - * @param handle DMA handle pointer. The DMA handle stores callback function and - * parameters. - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel); - -/*! - * @brief Installs a callback function for the DMA transfer. - * - * This callback is called in DMA IRQ handler. Use the callback to do something after - * the current major loop transfer completes. - * - * @param handle DMA handle pointer. - * @param callback DMA callback function pointer. - * @param userData Parameter for callback function. - */ -void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData); - -/*! - * @brief Prepares the DMA transfer structure. - * @deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer. - * This function prepares the transfer configuration structure according to the user input. - * - * @param config The user configuration structure of type dma_transfer_t. - * @param srcAddr DMA transfer source address. - * @param dstAddr DMA transfer destination address. - * @param byteWidth DMA transfer destination address width(bytes). - * @param transferBytes DMA transfer bytes to be transferred. - * @param type DMA transfer type. - * @param nextDesc Chain custom descriptor to transfer. - * @note The data address and the data width must be consistent. For example, if the SRC - * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in - * source address error(SAE). - */ -void DMA_PrepareTransfer(dma_transfer_config_t *config, - void *srcAddr, - void *dstAddr, - uint32_t byteWidth, - uint32_t transferBytes, - dma_transfer_type_t type, - void *nextDesc); - -/*! - * @brief Prepare channel transfer configurations. - * - * This function used to prepare channel transfer configurations. - * - * @param config Pointer to DMA channel transfer configuration structure. - * @param srcStartAddr source start address. - * @param dstStartAddr destination start address. - * @param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * @param type transfer type. - * @param trigger DMA channel trigger configurations. - * @param nextDesc address of next descriptor. - */ -void DMA_PrepareChannelTransfer(dma_channel_config_t *config, - void *srcStartAddr, - void *dstStartAddr, - uint32_t xferCfg, - dma_transfer_type_t type, - dma_channel_trigger_t *trigger, - void *nextDesc); - -/*! - * @brief Submits the DMA transfer request. - * @deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * - * @param handle DMA handle pointer. - * @param config Pointer to DMA transfer configuration structure. - * @retval kStatus_DMA_Success It means submit transfer request succeed. - * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config); - -/*! - * @brief Submit channel transfer paramter directly. - * - * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table - * is defined in DMA driver, it is useful for the case: - * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used - for it. - * @code - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, - bytes), srcStartAddr, dstStartAddr, NULL); - DMA_StartTransfer(handle) - * @endcode - * - * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is - required, then application should prepare - * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * @code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc2); - DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, NULL); - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, - bytes), srcStartAddr, dstStartAddr, nextDesc0); - DMA_StartTransfer(handle); - * @endcode - * - * @param handle Pointer to DMA handle. - * @param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * @param srcStartAddr source start address. - * @param dstStartAddr destination start address. - * @param nextDesc address of next descriptor. - */ -void DMA_SubmitChannelTransferParameter( - dma_handle_t *handle, uint32_t xferCfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc); - -/*! - * @brief Submit channel descriptor. - * - * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table - is defined in - * DMA driver, this functiono is typical for the ping pong case: - * - * 1. for the ping pong case, application should responsible for the descriptor, for example, application should - * prepare two descriptor table with macro. - * @code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc0); - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelDescriptor(handle, nextDesc0); - DMA_StartTransfer(handle); - * @endcode - * - * @param handle Pointer to DMA handle. - * @param descriptor descriptor to submit. - */ -void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descriptor); - -/*! - * @brief Submits the DMA channel transfer request. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * It is used for the case: - * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used - for it. - * @code - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,NULL); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * @endcode - * - * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is - required, then application should prepare - * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * @code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc2); - DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, NULL); - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * @endcode - * - * 3. for the ping pong case, application should responsible for link descriptor, for example, application should - prepare - * two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * @code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc0); - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * @endcode - * @param handle DMA handle pointer. - * @param config Pointer to DMA transfer configuration structure. - * @retval kStatus_DMA_Success It means submit transfer request succeed. - * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config); - -/*! - * @brief DMA start transfer. - * - * This function enables the channel request. User can call this function after submitting the transfer request - * It will trigger transfer start with software trigger only when hardware trigger is not used. - * - * @param handle DMA handle pointer. - */ -void DMA_StartTransfer(dma_handle_t *handle); - -/*! - * @brief DMA IRQ handler for descriptor transfer complete. - * - * This function clears the channel major interrupt flag and call - * the callback function if it is not NULL. - * - * @param base DMA base address. - */ -void DMA_IRQHandle(DMA_Type *base); - -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/* @} */ - -#endif /*_FSL_DMA_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_flexcomm.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_flexcomm.c deleted file mode 100644 index 7a21a1ce0ea..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_flexcomm.c +++ /dev/null @@ -1,412 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm" -#endif - -/*! - * @brief Used for conversion between `void*` and `uint32_t`. - */ -typedef union pvoid_to_u32 -{ - void *pvoid; - uint32_t u32; -} pvoid_to_u32_t; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! @brief Set the FLEXCOMM mode . */ -static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock); - -/*! @brief check whether flexcomm supports peripheral type */ -static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map FLEXCOMM instance number to base address. */ -static const uint32_t s_flexcommBaseAddrs[] = FLEXCOMM_BASE_ADDRS; - -/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ -static flexcomm_irq_handler_t s_flexcommIrqHandler[ARRAY_SIZE(s_flexcommBaseAddrs)]; - -/*! @brief Pointers to handles for each instance to provide context to interrupt routines */ -static void *s_flexcommHandle[ARRAY_SIZE(s_flexcommBaseAddrs)]; - -/*! @brief Array to map FLEXCOMM instance number to IRQ number. */ -IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief IDs of clock for each FLEXCOMM module */ -static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) -/*! @brief Pointers to FLEXCOMM resets for each instance. */ -static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* check whether flexcomm supports peripheral type */ -static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph) -{ - if (periph == FLEXCOMM_PERIPH_NONE) - { - return true; - } - else if (periph <= FLEXCOMM_PERIPH_I2S_TX) - { - return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false; - } - else if (periph == FLEXCOMM_PERIPH_I2S_RX) - { - return (base->PSELID & (1U << 7U)) > (uint32_t)0U ? true : false; - } - else - { - return false; - } -} - -/* Get the index corresponding to the FLEXCOMM */ -/*! brief Returns instance number for FLEXCOMM module with given base address. */ -uint32_t FLEXCOMM_GetInstance(void *base) -{ - uint32_t i; - pvoid_to_u32_t BaseAddr; - BaseAddr.pvoid = base; - - for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++) - { - if (BaseAddr.u32 == s_flexcommBaseAddrs[i]) - { - break; - } - } - - assert(i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT); - return i; -} - -/* Changes FLEXCOMM mode */ -static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock) -{ - /* Check whether peripheral type is present */ - if (!FLEXCOMM_PeripheralIsPresent(base, periph)) - { - return kStatus_OutOfRange; - } - - /* Flexcomm is locked to different peripheral type than expected */ - if (((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) != 0U) && - ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph)) - { - return kStatus_Fail; - } - - /* Check if we are asked to lock */ - if (lock != 0) - { - base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK; - } - else - { - base->PSELID = (uint32_t)periph; - } - - return kStatus_Success; -} - -/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ -status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) -{ - uint32_t idx = FLEXCOMM_GetInstance(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the peripheral clock */ - CLOCK_EnableClock(s_flexcommClocks[idx]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) - /* Reset the FLEXCOMM module */ - RESET_PeripheralReset(s_flexcommResets[idx]); -#endif - - /* Set the FLEXCOMM to given peripheral */ - return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0); -} - -/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM - * mode */ -void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(base); - - /* Clear handler first to avoid execution of the handler with wrong handle */ - s_flexcommIrqHandler[instance] = NULL; - s_flexcommHandle[instance] = flexcommHandle; - s_flexcommIrqHandler[instance] = handler; - SDK_ISR_EXIT_BARRIER; -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(FLEXCOMM0) -void FLEXCOMM0_DriverIRQHandler(void); -void FLEXCOMM0_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM0); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM1) -void FLEXCOMM1_DriverIRQHandler(void); -void FLEXCOMM1_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM1); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM2) -void FLEXCOMM2_DriverIRQHandler(void); -void FLEXCOMM2_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM2); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM3) -void FLEXCOMM3_DriverIRQHandler(void); -void FLEXCOMM3_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM3); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM4) -void FLEXCOMM4_DriverIRQHandler(void); -void FLEXCOMM4_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM4); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} - -#endif - -#if defined(FLEXCOMM5) -void FLEXCOMM5_DriverIRQHandler(void); -void FLEXCOMM5_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM5); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM6) -void FLEXCOMM6_DriverIRQHandler(void); -void FLEXCOMM6_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM6); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM7) -void FLEXCOMM7_DriverIRQHandler(void); -void FLEXCOMM7_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM7); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM8) -void FLEXCOMM8_DriverIRQHandler(void); -void FLEXCOMM8_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM8); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM9) -void FLEXCOMM9_DriverIRQHandler(void); -void FLEXCOMM9_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM9); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM10) -void FLEXCOMM10_DriverIRQHandler(void); -void FLEXCOMM10_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM10); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM11) -void FLEXCOMM11_DriverIRQHandler(void); -void FLEXCOMM11_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM11); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM12) -void FLEXCOMM12_DriverIRQHandler(void); -void FLEXCOMM12_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM12); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM13) -void FLEXCOMM13_DriverIRQHandler(void); -void FLEXCOMM13_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM13); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM14) -void FLEXCOMM14_DriverIRQHandler(void); -void FLEXCOMM14_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM14); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM15) -void FLEXCOMM15_DriverIRQHandler(void); -void FLEXCOMM15_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM15); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM16) -void FLEXCOMM16_DriverIRQHandler(void); -void FLEXCOMM16_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM16); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_flexcomm.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_flexcomm.h deleted file mode 100644 index f96086fdecc..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_flexcomm.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_FLEXCOMM_H_ -#define _FSL_FLEXCOMM_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup flexcomm_driver - * @{ - */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FlexCOMM driver version 2.0.2. */ -#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -/*! @brief FLEXCOMM peripheral modes. */ -typedef enum -{ - FLEXCOMM_PERIPH_NONE, /*!< No peripheral */ - FLEXCOMM_PERIPH_USART, /*!< USART peripheral */ - FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */ - FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */ - FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */ - FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */ -} FLEXCOMM_PERIPH_T; - -/*! @brief Typedef for interrupt handler. */ -typedef void (*flexcomm_irq_handler_t)(void *base, void *handle); - -/*! @brief Array with IRQ number for each FLEXCOMM module. */ -extern IRQn_Type const kFlexcommIrqs[]; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @brief Returns instance number for FLEXCOMM module with given base address. */ -uint32_t FLEXCOMM_GetInstance(void *base); - -/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ -status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph); - -/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM - * mode */ -void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle); - -#if defined(__cplusplus) -} -#endif - -/*@}*/ - -#endif /* _FSL_FLEXCOMM_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_fro_calib.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_fro_calib.h deleted file mode 100644 index 9662444a526..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_fro_calib.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2017, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_FRO_CALIB_H_ -#define _FSL_FRO_CALIB_H_ - -#include "fsl_common.h" -#include "fsl_device_registers.h" -#include - -/*! - * @addtogroup power - * @{ - */ -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FRO_CALIB driver version 1.0.0. */ -#define FSL_FRO_CALIB_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) -/*@}*/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.fro_calib" -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Returns the version of the FRO Calibration library */ -unsigned int fro_calib_Get_Lib_Ver(void); - -/* ctimer instance */ -/* ctimer clock frquency in KHz */ -void Chip_TIMER_Instance_Freq(CTIMER_Type *base, unsigned int ctimerFreq); - -/* USB_SOF_Event */ -/* Application software should be written to make sure the USB_SOF_EVENT() is */ -/* being called with lower interrupt latency for calibration to work properly */ -void USB_SOF_Event(void); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* _FSL_FRO_CALIB_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gint.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gint.c deleted file mode 100644 index 408844c3d15..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gint.c +++ /dev/null @@ -1,372 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_gint.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.gint" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to GINT bases for each instance. */ -static GINT_Type *const s_gintBases[FSL_FEATURE_SOC_GINT_COUNT] = GINT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Clocks for each instance. */ -static const clock_ip_name_t s_gintClocks[FSL_FEATURE_SOC_GINT_COUNT] = GINT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -/*! @brief Resets for each instance. */ -static const reset_ip_name_t s_gintResets[FSL_FEATURE_SOC_GINT_COUNT] = GINT_RSTS; -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/* @brief Irq number for each instance */ -static const IRQn_Type s_gintIRQ[FSL_FEATURE_SOC_GINT_COUNT] = GINT_IRQS; - -/*! @brief Callback function array for GINT(s). */ -static gint_cb_t s_gintCallback[FSL_FEATURE_SOC_GINT_COUNT]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t GINT_GetInstance(GINT_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_gintBases); instance++) - { - if (s_gintBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_gintBases)); - - return instance; -} - -/*! - * brief Initialize GINT peripheral. - - * This function initializes the GINT peripheral and enables the clock. - * - * param base Base address of the GINT peripheral. - * - * retval None. - */ -void GINT_Init(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - s_gintCallback[instance] = NULL; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the peripheral clock */ - CLOCK_EnableClock(s_gintClocks[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_gintResets[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -} - -/*! - * brief Setup GINT peripheral control parameters. - - * This function sets the control parameters of GINT peripheral. - * - * param base Base address of the GINT peripheral. - * param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. - * param trig Controls if the enabled inputs are level or edge sensitive based on polarity. - * param callback This function is called when configured group interrupt is generated. - * - * retval None. - */ -void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - base->CTRL = (GINT_CTRL_COMB(comb) | GINT_CTRL_TRIG(trig)); - - /* Save callback pointer */ - s_gintCallback[instance] = callback; -} - -/*! - * brief Get GINT peripheral control parameters. - - * This function returns the control parameters of GINT peripheral. - * - * param base Base address of the GINT peripheral. - * param comb Pointer to store combine input value. - * param trig Pointer to store trigger value. - * param callback Pointer to store callback function. - * - * retval None. - */ -void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback) -{ - uint32_t instance; - uint32_t combValue; - uint32_t trigValue; - - instance = GINT_GetInstance(base); - - combValue = (base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT; - *comb = (gint_comb_t)combValue; - trigValue = (base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT; - *trig = (gint_trig_t)trigValue; - *callback = s_gintCallback[instance]; -} - -/*! - * brief Configure GINT peripheral pins. - - * This function enables and controls the polarity of enabled pin(s) of a given port. - * - * param base Base address of the GINT peripheral. - * param port Port number. - * param polarityMask Each bit position selects the polarity of the corresponding enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * param enableMask Each bit position selects if the corresponding pin is enabled or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * retval None. - */ -void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask) -{ - base->PORT_POL[port] = polarityMask; - base->PORT_ENA[port] = enableMask; -} - -/*! - * brief Get GINT peripheral pin configuration. - - * This function returns the pin configuration of a given port. - * - * param base Base address of the GINT peripheral. - * param port Port number. - * param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding - enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled - or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * retval None. - */ -void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask) -{ - *polarityMask = base->PORT_POL[port]; - *enableMask = base->PORT_ENA[port]; -} - -/*! - * brief Enable callback. - - * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * param base Base address of the GINT peripheral. - * - * retval None. - */ -void GINT_EnableCallback(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - /* If GINT is configured in "AND" mode a spurious interrupt is generated. - Clear status and pending interrupt before enabling the irq in NVIC. */ - GINT_ClrStatus(base); - NVIC_ClearPendingIRQ(s_gintIRQ[instance]); - (void)EnableIRQ(s_gintIRQ[instance]); -} - -/*! - * brief Disable callback. - - * This function disables the interrupt for the selected GINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * param base Base address of the peripheral. - * - * retval None. - */ -void GINT_DisableCallback(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - (void)DisableIRQ(s_gintIRQ[instance]); - GINT_ClrStatus(base); - NVIC_ClearPendingIRQ(s_gintIRQ[instance]); -} - -/*! - * brief Deinitialize GINT peripheral. - - * This function disables the GINT clock. - * - * param base Base address of the GINT peripheral. - * - * retval None. - */ -void GINT_Deinit(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - /* Cleanup */ - GINT_DisableCallback(base); - s_gintCallback[instance] = NULL; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_gintResets[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the peripheral clock */ - CLOCK_DisableClock(s_gintClocks[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(GINT0) -void GINT0_DriverIRQHandler(void); -void GINT0_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[0]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[0] != NULL) - { - s_gintCallback[0](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT1) -void GINT1_DriverIRQHandler(void); -void GINT1_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[1]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[1] != NULL) - { - s_gintCallback[1](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT2) -void GINT2_DriverIRQHandler(void); -void GINT2_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[2]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[2] != NULL) - { - s_gintCallback[2](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT3) -void GINT3_DriverIRQHandler(void); -void GINT3_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[3]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[3] != NULL) - { - s_gintCallback[3](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT4) -void GINT4_DriverIRQHandler(void); -void GINT4_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[4]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[4] != NULL) - { - s_gintCallback[4](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT5) -void GINT5_DriverIRQHandler(void); -void GINT5_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[5]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[5] != NULL) - { - s_gintCallback[5](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT6) -void GINT6_DriverIRQHandler(void); -void GINT6_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[6]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[6] != NULL) - { - s_gintCallback[6](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT7) -void GINT7_DriverIRQHandler(void); -void GINT7_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[7]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[7] != NULL) - { - s_gintCallback[7](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gint.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gint.h deleted file mode 100644 index 081be7a57cb..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gint.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_GINT_H_ -#define _FSL_GINT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup gint_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3. */ -/*@}*/ - -/*! @brief GINT combine inputs type */ -typedef enum _gint_comb -{ - kGINT_CombineOr = 0U, /*!< A grouped interrupt is generated when any one of the enabled inputs is active */ - kGINT_CombineAnd = 1U /*!< A grouped interrupt is generated when all enabled inputs are active */ -} gint_comb_t; - -/*! @brief GINT trigger type */ -typedef enum _gint_trig -{ - kGINT_TrigEdge = 0U, /*!< Edge triggered based on polarity */ - kGINT_TrigLevel = 1U /*!< Level triggered based on polarity */ -} gint_trig_t; - -/* @brief GINT port type */ -typedef enum _gint_port -{ - kGINT_Port0 = 0U, - kGINT_Port1 = 1U, -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 2U) - kGINT_Port2 = 2U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 3U) - kGINT_Port3 = 3U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 4U) - kGINT_Port4 = 4U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 5U) - kGINT_Port5 = 5U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 6U) - kGINT_Port6 = 6U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 7U) - kGINT_Port7 = 7U, -#endif -} gint_port_t; - -/*! @brief GINT Callback function. */ -typedef void (*gint_cb_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize GINT peripheral. - - * This function initializes the GINT peripheral and enables the clock. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_Init(GINT_Type *base); - -/*! - * @brief Setup GINT peripheral control parameters. - - * This function sets the control parameters of GINT peripheral. - * - * @param base Base address of the GINT peripheral. - * @param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. - * @param trig Controls if the enabled inputs are level or edge sensitive based on polarity. - * @param callback This function is called when configured group interrupt is generated. - * - * @retval None. - */ -void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback); - -/*! - * @brief Get GINT peripheral control parameters. - - * This function returns the control parameters of GINT peripheral. - * - * @param base Base address of the GINT peripheral. - * @param comb Pointer to store combine input value. - * @param trig Pointer to store trigger value. - * @param callback Pointer to store callback function. - * - * @retval None. - */ -void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback); - -/*! - * @brief Configure GINT peripheral pins. - - * This function enables and controls the polarity of enabled pin(s) of a given port. - * - * @param base Base address of the GINT peripheral. - * @param port Port number. - * @param polarityMask Each bit position selects the polarity of the corresponding enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * @param enableMask Each bit position selects if the corresponding pin is enabled or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * @retval None. - */ -void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask); - -/*! - * @brief Get GINT peripheral pin configuration. - - * This function returns the pin configuration of a given port. - * - * @param base Base address of the GINT peripheral. - * @param port Port number. - * @param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding - enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * @param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled - or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * @retval None. - */ -void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask); - -/*! - * @brief Enable callback. - - * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_EnableCallback(GINT_Type *base); - -/*! - * @brief Disable callback. - - * This function disables the interrupt for the selected GINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * @param base Base address of the peripheral. - * - * @retval None. - */ -void GINT_DisableCallback(GINT_Type *base); - -/*! - * @brief Clear GINT status. - - * This function clears the GINT status bit. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -static inline void GINT_ClrStatus(GINT_Type *base) -{ - base->CTRL |= GINT_CTRL_INT_MASK; -} - -/*! - * @brief Get GINT status. - - * This function returns the GINT status. - * - * @param base Base address of the GINT peripheral. - * - * @retval status = 0 No group interrupt request. = 1 Group interrupt request active. - */ -static inline uint32_t GINT_GetStatus(GINT_Type *base) -{ - return (base->CTRL & GINT_CTRL_INT_MASK); -} - -/*! - * @brief Deinitialize GINT peripheral. - - * This function disables the GINT clock. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_Deinit(GINT_Type *base); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_GINT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gpio.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gpio.c deleted file mode 100644 index be100d5e9e3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gpio.c +++ /dev/null @@ -1,317 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_gpio.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map FGPIO instance number to clock name. */ -static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) -/*! @brief Pointers to GPIO resets for each instance. */ -static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N; -#endif -/******************************************************************************* - * Prototypes - ************ ******************************************************************/ -/*! - * @brief Enable GPIO port clock. - * - * @param base GPIO peripheral base pointer. - * @param port GPIO port number. - */ -static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port); - -/******************************************************************************* - * Code - ******************************************************************************/ -static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - assert(port < ARRAY_SIZE(s_gpioClockName)); - - /* Upgate the GPIO clock */ - CLOCK_EnableClock(s_gpioClockName[port]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Initializes the GPIO peripheral. - * - * This function ungates the GPIO clock. - * - * param base GPIO peripheral base pointer. - * param port GPIO port number. - */ -void GPIO_PortInit(GPIO_Type *base, uint32_t port) -{ - GPIO_EnablePortClock(base, port); - -#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) - /* Reset the GPIO module */ - RESET_PeripheralReset(s_gpioResets[port]); -#endif -} - -/*! - * brief Initializes a GPIO pin used by the board. - * - * To initialize the GPIO, define a pin configuration, either input or output, in the user file. - * Then, call the GPIO_PinInit() function. - * - * This is an example to define an input pin or output pin configuration: - * code - * Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * endcode - * - * param base GPIO peripheral base pointer(Typically GPIO) - * param port GPIO port number - * param pin GPIO pin number - * param config GPIO pin configuration pointer - */ -void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) -{ - GPIO_EnablePortClock(base, port); - - if (config->pinDirection == kGPIO_DigitalInput) - { -#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) - base->DIRCLR[port] = 1UL << pin; -#else - base->DIR[port] &= ~(1UL << pin); -#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ - } - else - { - /* Set default output value */ - if (config->outputLogic == 0U) - { - base->CLR[port] = (1UL << pin); - } - else - { - base->SET[port] = (1UL << pin); - } -/* Set pin direction */ -#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) - base->DIRSET[port] = 1UL << pin; -#else - base->DIR[port] |= 1UL << pin; -#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ - } -} - -#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT -/*! - * @brief Set the configuration of pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param pin GPIO pin number. - * @param config GPIO pin interrupt configuration.. - */ -void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config) -{ - base->INTEDG[port] = (base->INTEDG[port] & ~(1UL << pin)) | ((uint32_t)config->mode << pin); - - base->INTPOL[port] = (base->INTPOL[port] & ~(1UL << pin)) | ((uint32_t)config->polarity << pin); -} - -/*! - * @brief Enables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] | mask; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] | mask; - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Disables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] & ~mask; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] & ~mask; - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Clears multiple pins interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTSTATA[port] = mask; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTSTATB[port] = mask; - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @ Read port interrupt status. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param index GPIO interrupt number. - * @retval masked GPIO status value - */ -uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index) -{ - uint32_t status = 0U; - - if ((uint32_t)kGPIO_InterruptA == index) - { - status = base->INTSTATA[port]; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - status = base->INTSTATB[port]; - } - else - { - /*Should not enter here*/ - } - return status; -} - -/*! - * @brief Enables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] | (1UL << pin); - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] | (1UL << pin); - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Disables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] & ~(1UL << pin); - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] & ~(1UL << pin); - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Clears the specific pin interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTSTATA[port] = 1UL << pin; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTSTATB[port] = 1UL << pin; - } - else - { - /*Should not enter here*/ - } -} -#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gpio.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gpio.h deleted file mode 100644 index 50a33f89208..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gpio.h +++ /dev/null @@ -1,364 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _LPC_GPIO_H_ -#define _LPC_GPIO_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_gpio - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPC GPIO driver version. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 7)) -/*@}*/ - -/*! @brief LPC GPIO direction definition */ -typedef enum _gpio_pin_direction -{ - kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ - kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ -} gpio_pin_direction_t; - -/*! - * @brief The GPIO pin configuration structure. - * - * Every pin can only be configured as either output pin or input pin at a time. - * If configured as a input pin, then leave the outputConfig unused. - */ -typedef struct _gpio_pin_config -{ - gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ - /* Output configurations, please ignore if configured as a input one */ - uint8_t outputLogic; /*!< Set default output logic, no use in input */ -} gpio_pin_config_t; - -#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT) -#define GPIO_PIN_INT_LEVEL 0x00U -#define GPIO_PIN_INT_EDGE 0x01U - -#define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U -#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U - -/*! @brief GPIO Pin Interrupt enable mode */ -typedef enum _gpio_pin_enable_mode -{ - kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */ - kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE /*!< Generate Pin Interrupt on edge mode */ -} gpio_pin_enable_mode_t; - -/*! @brief GPIO Pin Interrupt enable polarity */ -typedef enum _gpio_pin_enable_polarity -{ - kGPIO_PinIntEnableHighOrRise = - PINT_PIN_INT_HIGH_OR_RISE_TRIGGER, /*!< Generate Pin Interrupt on high level or rising edge */ - kGPIO_PinIntEnableLowOrFall = - PINT_PIN_INT_LOW_OR_FALL_TRIGGER /*!< Generate Pin Interrupt on low level or falling edge */ -} gpio_pin_enable_polarity_t; - -/*! @brief LPC GPIO interrupt index definition */ -typedef enum _gpio_interrupt_index -{ - kGPIO_InterruptA = 0U, /*!< Set current pin as interrupt A*/ - kGPIO_InterruptB = 1U, /*!< Set current pin as interrupt B*/ -} gpio_interrupt_index_t; - -/*! @brief Configures the interrupt generation condition. */ -typedef struct _gpio_interrupt_config -{ - uint8_t mode; /* The trigger mode of GPIO interrupts */ - uint8_t polarity; /* The polarity of GPIO interrupts */ -} gpio_interrupt_config_t; -#endif - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @name GPIO Configuration */ -/*@{*/ - -/*! - * @brief Initializes the GPIO peripheral. - * - * This function ungates the GPIO clock. - * - * @param base GPIO peripheral base pointer. - * @param port GPIO port number. - */ -void GPIO_PortInit(GPIO_Type *base, uint32_t port); - -/*! - * @brief Initializes a GPIO pin used by the board. - * - * To initialize the GPIO, define a pin configuration, either input or output, in the user file. - * Then, call the GPIO_PinInit() function. - * - * This is an example to define an input pin or output pin configuration: - * @code - * Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * @endcode - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @param config GPIO pin configuration pointer - */ -void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config); - -/*@}*/ - -/*! @name GPIO Output Operations */ -/*@{*/ - -/*! - * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @param output GPIO pin output logic level. - * - 0: corresponding pin output low-logic level. - * - 1: corresponding pin output high-logic level. - */ -static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) -{ - base->B[port][pin] = output; -} - -/*@}*/ -/*! @name GPIO Input Operations */ -/*@{*/ - -/*! - * @brief Reads the current input value of the GPIO PIN. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @retval GPIO port input value - * - 0: corresponding pin input low-logic level. - * - 1: corresponding pin input high-logic level. - */ -static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) -{ - return (uint32_t)base->B[port][pin]; -} - -/*@}*/ - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 1. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->SET[port] = mask; -} - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 0. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->CLR[port] = mask; -} - -/*! - * @brief Reverses current output logic of the multiple GPIO pins. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->NOT[port] = mask; -} - -/*@}*/ - -/*! - * @brief Reads the current input value of the whole GPIO port. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - */ -static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port) -{ - return (uint32_t)base->PIN[port]; -} - -/*@}*/ -/*! @name GPIO Mask Operations */ -/*@{*/ - -/*! - * @brief Sets port mask, 0 - enable pin, 1 - disable pin. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->MASK[port] = mask; -} - -/*! - * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param output GPIO port output value. - */ -static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output) -{ - base->MPIN[port] = output; -} - -/*! - * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be - * affected. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @retval masked GPIO port value - */ -static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) -{ - return (uint32_t)base->MPIN[port]; -} - -#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT -/*! - * @brief Set the configuration of pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param pin GPIO pin number. - * @param config GPIO pin interrupt configuration.. - */ -void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config); - -/*! - * @brief Enables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); - -/*! - * @brief Disables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); - -/*! - * @brief Clears pin interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); - -/*! - * @ Read port interrupt status. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param index GPIO interrupt number. - * @retval masked GPIO status value - */ -uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index); - -/*! - * @brief Enables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); - -/*! - * @brief Disables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); - -/*! - * @brief Clears the specific pin interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); - -#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* _LPC_GPIO_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_hashcrypt.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_hashcrypt.c deleted file mode 100644 index 85943dcfdd3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_hashcrypt.c +++ /dev/null @@ -1,1726 +0,0 @@ -/* - * Copyright 2017-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_hashcrypt.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.hashcrypt" -#endif - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*!< SHA-1 and SHA-256 block size */ -#define SHA_BLOCK_SIZE 64U -/*!< max number of blocks that can be proccessed in one run (master mode) */ -#define SHA_MASTER_MAX_BLOCKS 2048U - -/*!< Use standard C library memcpy */ -#define hashcrypt_memcpy memcpy - -/*! Internal states of the HASH creation process */ -typedef enum _hashcrypt_sha_algo_state -{ - kHASHCRYPT_HashInit = 1u, /*!< Init state, the NEW bit in SHA Control register has not been written yet. */ - kHASHCRYPT_HashUpdate, /*!< Update state, DIGEST registers contain running hash, NEW bit in SHA control register has - been written. */ -} hashcrypt_sha_algo_state_t; - -/*! 64-byte block represented as byte array of 16 32-bit words */ -typedef union _sha_hash_block -{ - uint32_t w[SHA_BLOCK_SIZE / 4]; /*!< array of 32-bit words */ - uint8_t b[SHA_BLOCK_SIZE]; /*!< byte array */ -} hashcrypt_sha_block_t; - -/*! internal sha context structure */ -typedef struct _hashcrypt_sha_ctx_internal -{ - hashcrypt_sha_block_t blk; /*!< memory buffer. only full 64-byte blocks are written to SHA during hash updates */ - size_t blksz; /*!< number of valid bytes in memory buffer */ - hashcrypt_algo_t algo; /*!< selected algorithm from the set of supported algorithms */ - hashcrypt_sha_algo_state_t state; /*!< finite machine state of the hash software process */ - size_t fullMessageSize; /*!< track message size during SHA_Update(). The value is used for padding. */ - uint32_t remainingBlcks; /*!< number of remaining blocks to process in AHB master mode */ - hashcrypt_callback_t hashCallback; /*!< pointer to HASH callback function */ - void - *userData; /*!< user data to be passed as an argument to callback function, once callback is invoked from isr */ -#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) - uint32_t runningHash[8]; /*!< running hash. up to SHA-256, that is 32 bytes. */ -#endif -} hashcrypt_sha_ctx_internal_t; - -#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) -#define SHA1_LEN 5u -#define SHA256_LEN 8u -#endif - -/*!< SHA-1 and SHA-256 digest length in bytes */ -enum _hashcrypt_sha_digest_len -{ - kHASHCRYPT_OutLenSha1 = 20u, - kHASHCRYPT_OutLenSha256 = 32u, -}; - -/*!< pointer to hash context structure used by isr */ -static hashcrypt_hash_ctx_t *s_ctx; - -/*!< macro for checking build time condition. It is used to assure the hashcrypt_sha_ctx_internal_t can fit into - * hashcrypt_hash_ctx_t */ -#define BUILD_ASSERT(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused)) - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * @brief Swap bytes withing 32-bit word. - * - * This function changes endianess of a 32-bit word. - * - * @param in 32-bit unsigned integer - * @return 32-bit unsigned integer with different endianess (big endian to little endian and vice versa). - */ - -#define swap_bytes(in) __REV(in) - -/*! - * @brief Increment a 16 byte integer. - * - * This function increments by one a 16 byte integer. - * - * @param input Pointer to a 16 byte integer to be incremented by one. - */ -static void ctrIncrement(uint8_t *input) -{ - int i = 15; - while (input[i] == (uint8_t)0xFFu) - { - input[i] = (uint8_t)0x00u; - i--; - if (i < 0) - { - return; - } - } - - if (i >= 0) - { - input[i] += (uint8_t)1u; - } -} - -/*! - * @brief Reads an unaligned word. - * - * This function creates a 32-bit word from an input array of four bytes. - * - * @param src Input array of four bytes. The array can start at any address in memory. - * @return 32-bit unsigned int created from the input byte array. - */ - -/* Force lower optimization for Keil, otherwise it replaces inline LDR with LDM */ -#if defined(__CC_ARM) -#pragma push -#pragma O0 -#endif - -static inline uint32_t hashcrypt_get_word_from_unaligned(const uint8_t *srcAddr) -{ -#if (!(defined(__CORTEX_M)) || (defined(__CORTEX_M) && (__CORTEX_M == 0))) - register const uint8_t *src = srcAddr; - /* Cortex M0 does not support misaligned loads */ - if (0U != ((uint32_t)src & 0x3u)) - { - union _align_bytes_t - { - uint32_t word; - uint8_t byte[sizeof(uint32_t)]; - } my_bytes; - - my_bytes.byte[0] = *src; - my_bytes.byte[1] = src[1]; - my_bytes.byte[2] = src[2]; - my_bytes.byte[3] = src[3]; - return my_bytes.word; - } - else - { - /* addr aligned to 0-modulo-4 so it is safe to type cast */ - return *((const uint32_t *)(uint32_t)src); - } -#elif defined(__CC_ARM) - /* -O3 optimization in Keil 5.15 and 5.16a uses LDM instruction here (LDM r4!, {r0}) - * which is wrong, because srcAddr might be unaligned. - * LDM on unaligned address causes hard-fault. in contrary, - * LDR supports unaligned address on Cortex M4 */ - - register uint32_t retVal; - __asm - { - LDR retVal, [srcAddr] - } - return retVal; -#else - return *((const uint32_t *)(uintptr_t)srcAddr); -#endif -} - -/* End lower optimization */ -#if defined(__CC_ARM) -#pragma pop -#endif - -static status_t hashcrypt_get_key_from_unaligned_src(uint8_t *dest, const uint8_t *src, size_t size) -{ - status_t retVal = kStatus_InvalidArgument; - uint32_t i; - - /* destination is SDK driver internal workspace and it must be aligned */ - assert(0x0u == ((uint32_t)dest & 0x1u)); - if (0U != ((uint32_t)dest & 0x1u)) - { - return retVal; - } - - for (i = 0; i < ((uint32_t)size / 4u); i++) - { - ((uint32_t *)(uintptr_t)dest)[i] = hashcrypt_get_word_from_unaligned(&src[i * sizeof(uint32_t)]); - } - - return kStatus_Success; -} - -/*! - * @brief LDM to SHA engine INDATA and ALIAS registers. - * - * This function writes 16 words starting from the src address (must be word aligned) - * to the dst address. Dst address does not increment (destination is peripheral module register INDATA). - * Src address increments to load 16 consecutive words. - * - * @param dst peripheral register address (word aligned) - * @param src address of the input 512-bit block (16 words) (word aligned) - * - */ -__STATIC_FORCEINLINE void hashcrypt_sha_ldm_stm_16_words(HASHCRYPT_Type *base, const uint32_t *src) -{ - /* Data Synchronization Barrier */ - __DSB(); - /* - typedef struct _one_block - { - uint32_t a[8]; - } one_block_t; - - volatile one_block_t *ldst = (void *)(uintptr_t)(&base->INDATA); - one_block_t *lsrc = (void *)(uintptr_t)src; - *ldst = lsrc[0]; - *ldst = lsrc[1]; - */ - - /* Data Synchronization Barrier prevent compiler from reordering memory write when -O2 or higher is used. */ - /* The address is passed to the crypto engine for hashing below, therefore out */ - /* of order memory write due to compiler optimization must be prevented. */ - __DSB(); - - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(src); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(1); - - __DSB(); -} - -/*! - * @brief Loads data to Hashcrypt engine INDATA register. - * - * This function writes desired number of bytes starting from the src address - * to the dst address. Dst address does not increment (destination is peripheral module register INDATA). - * Src address increments to load consecutive words. - * - * @param src address of the input block - * @param size number of bytes to write - * - */ -__STATIC_INLINE void hashcrypt_load_data(HASHCRYPT_Type *base, uint32_t *src, size_t size) -{ - /* 16 bytes aligned input block */ - uint32_t __attribute__((aligned(4))) inAlign[HASHCRYPT_AES_BLOCK_SIZE / sizeof(uint32_t)]; - uint32_t *in; - uint8_t i; - - in = src; - /* Check if address of src data is aligned */ - if ((0U != ((uint32_t)in & 3U))) - { - for (i = 0; i < ((uint32_t)size / 4U); i++) - { - inAlign[i] = hashcrypt_get_word_from_unaligned((uint8_t *)&src[i]); - } - in = &inAlign[0]; - } - - if (size >= sizeof(uint32_t)) - { - base->INDATA = in[0]; - size -= sizeof(uint32_t); - } - - for (uint32_t j = 0; j < size / 4U; j++) - { - base->ALIAS[j] = in[j + 1U]; - } -} - -/*! - * @brief Checks availability of HW AES key. - * - * This function checks if the AES key is present at dedicated hardware bus - * and can be used at actual security level. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @return kStatus_Success if available, kStatus_Fail otherwise. - * - */ -static status_t hashcrypt_check_need_key(HASHCRYPT_Type *base, hashcrypt_handle_t *handle) -{ - if (handle->keyType == kHASHCRYPT_SecretKey) - { - volatile uint32_t wait = 50u; - /* wait until STATUS register is non-zero */ - while ((wait > 0U) && (base->STATUS == 0U)) - { - wait--; - } - /* if NEEDKEY bit is not set, HW key is available */ - if (0U == (base->STATUS & HASHCRYPT_STATUS_NEEDKEY_MASK)) - { - return kStatus_Success; - } - /* NEEDKEY is set, HW key is not available */ - return kStatus_Fail; - } - else - { - /* in case user key is used, return success */ - return kStatus_Success; - } -} - -/*! - * @brief Read OUTDATA registers. - * - * This function copies OUTDATA to output buffer. - * - * @param base Hachcrypt peripheral base address. - * @param[out] output Output buffer. - * @param Number of bytes to copy. - */ -static void hashcrypt_get_data(HASHCRYPT_Type *base, uint32_t *output, size_t outputSize) -{ - uint32_t digest[8]; - - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - - /* Data Synchronization Barrier */ - __DSB(); - - for (int i = 0; i < 8; i++) - { - digest[i] = swap_bytes(base->DIGEST0[i]); - } - - if (outputSize > sizeof(digest)) - { - outputSize = sizeof(digest); - } - (void)hashcrypt_memcpy(output, digest, outputSize); -} - -/*! - * @brief Initialize the Hashcrypt engine for new operation. - * - * This function sets NEW and MODE fields in Hashcrypt Control register to start new operation. - * - * @param base Hashcrypt peripheral base address. - * @param hashcrypt_algo_t Internal context. - */ -static void hashcrypt_engine_init(HASHCRYPT_Type *base, hashcrypt_algo_t algo) -{ - /* NEW bit must be set before we switch from previous mode otherwise new mode will not work correctly */ - base->CTRL = HASHCRYPT_CTRL_NEW_HASH(1); - base->CTRL = HASHCRYPT_CTRL_MODE(algo) | HASHCRYPT_CTRL_NEW_HASH(1); -} - -/*! - * @brief Deinitialization of the Hashcrypt engine. - * - * This function sets MODE field in Hashcrypt Control register to zero - disabled. - * This reduces power consumption of HASHCRYPT. - * - * @param base Hashcrypt peripheral base address. - */ -static inline void hashcrypt_engine_deinit(HASHCRYPT_Type *base) -{ - base->CTRL &= ~(HASHCRYPT_CTRL_MODE_MASK); -} - -/*! - * @brief Loads user key to INDATA register. - * - * This function writes user key stored in handle into HashCrypt INDATA register. - * - * @param base Hashcrypt peripheral base address. - * @param handle Handle used for this request. - */ -static void hashcrypt_aes_load_userKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle) -{ - size_t keySize = 0; - - switch (handle->keySize) - { - case kHASHCRYPT_Aes128: - keySize = 16; - break; - case kHASHCRYPT_Aes192: - keySize = 24; - break; - case kHASHCRYPT_Aes256: - keySize = 32; - break; - default: - /* All the cases have been listed above, the default clause should not be reached. */ - break; - } - if (keySize == 0U) - { - return; - } - hashcrypt_load_data(base, &handle->keyWord[0], keySize); -} - -/*! - * @brief Performs AES encryption/decryption of one data block. - * - * This function encrypts/decrypts one block of data with specified size. - * - * @param base Hashcrypt peripheral base address. - * @param input input data - * @param output output data - * @param size size of data block to process in bytes (must be 16bytes multiple). - */ -static status_t hashcrypt_aes_one_block_aligned(HASHCRYPT_Type *base, - const uint8_t *input, - uint8_t *output, - size_t size) -{ - status_t status = kStatus_Fail; - uint32_t idx = 0; - - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(input); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(size / 16U); - while (size >= HASHCRYPT_AES_BLOCK_SIZE) - { - /* Get result */ - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - - for (int i = 0; i < 4; i++) - { - ((uint32_t *)(uintptr_t)output + idx)[i] = swap_bytes(base->DIGEST0[i]); - } - - idx += HASHCRYPT_AES_BLOCK_SIZE / 4U; - size -= HASHCRYPT_AES_BLOCK_SIZE; - } - - if (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * @brief Performs AES encryption/decryption of one data block. - * - * This function encrypts/decrypts one block of data with specified size. - * - * @param base Hashcrypt peripheral base address. - * @param input input data - * @param output output data - * @param size size of data block to process in bytes (must be 16bytes multiple). - */ -static status_t hashcrypt_aes_one_block_unaligned(HASHCRYPT_Type *base, - const uint8_t *input, - uint8_t *output, - size_t size) -{ - status_t status = kStatus_Fail; - - /* we use AHB master mode as much as possible */ - /* however, it can work only with aligned input data */ - /* so, if unaligned, we do memcpy to temp buffer on stack, which is aligned, and use AHB mode to read data in */ - /* then we read data back to it and do memcpy to the output buffer */ - uint32_t temp[256 / sizeof(uint32_t)]; - int cnt = 0; - while (size != 0U) - { - size_t actSz = size >= 256u ? 256u : size; - size_t actSzOrig = actSz; - (void)memcpy(temp, (const uint32_t *)(uintptr_t)(input + 256 * cnt), actSz); - size -= actSz; - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(temp); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(actSz / 16U); - uint32_t outidx = 0; - while (actSz != 0U) - { - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - for (int i = 0; i < 4; i++) - { - (temp + outidx)[i] = swap_bytes(base->DIGEST0[i]); - } - outidx += HASHCRYPT_AES_BLOCK_SIZE / 4U; - actSz -= HASHCRYPT_AES_BLOCK_SIZE; - } - (void)memcpy(output + 256 * cnt, (const uint8_t *)(uintptr_t)temp, actSzOrig); - cnt++; - } - - if (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * @brief Performs AES encryption/decryption of one data block. - * - * This function encrypts/decrypts one block of data with specified size. - * - * @param base Hashcrypt peripheral base address. - * @param input input data - * @param output output data - * @param size size of data block to process in bytes (must be 16bytes multiple). - */ -static status_t hashcrypt_aes_one_block(HASHCRYPT_Type *base, const uint8_t *input, uint8_t *output, size_t size) -{ - status_t status = kStatus_Fail; - - /*MEMCTRL bitfield for COUNT is 11 bits, and this limits the number of blocks to process in one Master run to 2047 - (2^11 -1) blocks . Each block is 16bytes long, so biggest data size which can we do in one Master run is (2047 - blocks *16 bytes) = 32752 So, when size is overflowing HASHCRYPT_MEMCTRL_COUNT field of MEMCTRL register, we split - our data into more smaller chunks */ - - if (size > 32752U) - - { - size_t numBlock = size / 32752U; /* number of blocks, each block is processed in one run*/ - size_t remainingSize = size - (numBlock * 32752U); /* size of last block */ - - if ((0U != ((uint32_t)input & 0x3u)) || (0U != ((uint32_t)output & 0x3u))) /* If data is unaligned*/ - { - for (uint32_t i = 0; i < numBlock; i++) - { - status = hashcrypt_aes_one_block_unaligned(base, input, output, 32752U); - input += 32752U; - output += 32752U; - } - status = hashcrypt_aes_one_block_unaligned(base, input, output, remainingSize); - } - else /* If data is aligned*/ - { - for (uint32_t i = 0; i < numBlock; i++) - { - status = hashcrypt_aes_one_block_aligned(base, input, output, 32752U); - input += 32752U; - output += 32752U; - } - status = hashcrypt_aes_one_block_aligned(base, input, output, remainingSize); - } - } - - else /* size is less than COUNT field of MEMCTRL register so we can process all data at once */ - { - /* we use AHB master mode as much as possible */ - /* however, it can work only with aligned input data */ - /* so, if unaligned, we do memcpy to temp buffer on stack, which is aligned, and use AHB mode to read data in */ - /* then we read data back to it and do memcpy to the output buffer */ - if ((0U != ((uint32_t)input & 0x3u)) || (0U != ((uint32_t)output & 0x3u))) - { - status = hashcrypt_aes_one_block_unaligned(base, input, output, size); - } - else - { - status = hashcrypt_aes_one_block_aligned(base, input, output, size); - } - } - return status; -} - -/*! - * @brief Check validity of algoritm. - * - * This function checks the validity of input argument. - * - * @param algo Tested algorithm value. - * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. - */ -static status_t hashcrypt_sha_check_input_alg(HASHCRYPT_Type *base, hashcrypt_algo_t algo) -{ - if ((algo == kHASHCRYPT_Sha1) || (algo == kHASHCRYPT_Sha256)) - { - return kStatus_Success; - } - - return kStatus_InvalidArgument; -} - -/*! - * @brief Check validity of input arguments. - * - * This function checks the validity of input arguments. - * - * @param base SHA peripheral base address. - * @param ctx Memory buffer given by user application where the SHA_Init/SHA_Update/SHA_Finish store context. - * @param algo Tested algorithm value. - * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. - */ -static status_t hashcrypt_sha_check_input_args(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo) -{ - /* Check validity of input algorithm */ - if (kStatus_Success != hashcrypt_sha_check_input_alg(base, algo)) - { - return kStatus_InvalidArgument; - } - - if ((NULL == ctx) || (NULL == base)) - { - return kStatus_InvalidArgument; - } - - return kStatus_Success; -} - -/*! - * @brief Check validity of internal software context. - * - * This function checks if the internal context structure looks correct. - * - * @param ctxInternal Internal context. - * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. - */ -static status_t hashcrypt_sha_check_context(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) -{ - if ((NULL == ctxInternal) || (kStatus_Success != hashcrypt_sha_check_input_alg(base, ctxInternal->algo))) - { - return kStatus_InvalidArgument; - } - return kStatus_Success; -} - -/*! - * @brief Load 512-bit block (16 words) into SHA engine. - * - * This function aligns the input block and moves it into SHA engine INDATA. - * CPU polls the WAITING bit and then moves data by using LDM and STM instructions. - * - * @param base SHA peripheral base address. - * @param blk 512-bit block - */ -static void hashcrypt_sha_one_block(HASHCRYPT_Type *base, const uint8_t *blk) -{ - uint32_t temp[SHA_BLOCK_SIZE / sizeof(uint32_t)]; - const uint32_t *actBlk; - - /* make sure the 512-bit block is word aligned */ - if (0U != ((uintptr_t)blk & 0x3u)) - { - (void)hashcrypt_memcpy(temp, (const uint32_t *)(uintptr_t)blk, SHA_BLOCK_SIZE); - actBlk = (const uint32_t *)(uintptr_t)temp; - } - else - { - actBlk = (const uint32_t *)(uintptr_t)blk; - } - - /* poll waiting. */ - while (0U == (base->STATUS & HASHCRYPT_STATUS_WAITING_MASK)) - { - } - /* feed INDATA (and ALIASes). use STM instruction. */ - hashcrypt_sha_ldm_stm_16_words(base, actBlk); -} - -/*! - * @brief Adds message to current hash. - * - * This function merges the message to fill the internal buffer, empties the internal buffer if - * it becomes full, then process all remaining message data. - * - * - * @param base SHA peripheral base address. - * @param ctxInternal Internal context. - * @param message Input message. - * @param messageSize Size of input message in bytes. - * @return kStatus_Success. - */ -static status_t hashcrypt_sha_process_message_data(HASHCRYPT_Type *base, - hashcrypt_sha_ctx_internal_t *ctxInternal, - const uint8_t *message, - size_t messageSize) -{ - /* first fill the internal buffer to full block */ - if (ctxInternal->blksz != 0U) - { - size_t toCopy = SHA_BLOCK_SIZE - ctxInternal->blksz; - (void)hashcrypt_memcpy(&ctxInternal->blk.b[ctxInternal->blksz], message, toCopy); - message += toCopy; - messageSize -= toCopy; - - /* process full internal block */ - hashcrypt_sha_one_block(base, &ctxInternal->blk.b[0]); - } - - /* process all full blocks in message[] */ - if (messageSize >= SHA_BLOCK_SIZE) - { - if (0U != ((uintptr_t)message & 0x3u)) - { - while (messageSize >= SHA_BLOCK_SIZE) - { - hashcrypt_sha_one_block(base, message); - message += SHA_BLOCK_SIZE; - messageSize -= SHA_BLOCK_SIZE; - } - } - else - { - /* poll waiting. */ - while (0U == (base->STATUS & HASHCRYPT_STATUS_WAITING_MASK)) - { - } - uint32_t blkNum = (messageSize >> 6); /* div by 64 bytes */ - uint32_t blkBytes = blkNum * 64u; /* number of bytes in 64 bytes blocks */ - __DSB(); - __ISB(); - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(message); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(blkNum); - message += blkBytes; - messageSize -= blkBytes; - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - } - } - - /* copy last incomplete message bytes into internal block */ - (void)hashcrypt_memcpy(&ctxInternal->blk.b[0], message, messageSize); - ctxInternal->blksz = messageSize; - return kStatus_Success; -} - -/*! - * @brief Finalize the running hash to make digest. - * - * This function empties the internal buffer, adds padding bits, and generates final digest. - * - * @param base SHA peripheral base address. - * @param ctxInternal Internal context. - * @return kStatus_Success. - */ -static status_t hashcrypt_sha_finalize(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) -{ - hashcrypt_sha_block_t lastBlock; - - (void)memset(&lastBlock, 0, sizeof(hashcrypt_sha_block_t)); - - /* this is last call, so need to flush buffered message bytes along with padding */ - if (ctxInternal->blksz <= 55u) - { - /* last data is 440 bits or less. */ - (void)hashcrypt_memcpy(&lastBlock.b[0], &ctxInternal->blk.b[0], ctxInternal->blksz); - lastBlock.b[ctxInternal->blksz] = (uint8_t)0x80U; - lastBlock.w[SHA_BLOCK_SIZE / 4U - 1U] = swap_bytes(8u * ctxInternal->fullMessageSize); - hashcrypt_sha_one_block(base, &lastBlock.b[0]); - } - else - { - if (ctxInternal->blksz < SHA_BLOCK_SIZE) - { - ctxInternal->blk.b[ctxInternal->blksz] = (uint8_t)0x80U; - for (uint32_t i = ctxInternal->blksz + 1u; i < SHA_BLOCK_SIZE; i++) - { - ctxInternal->blk.b[i] = 0; - } - } - else - { - lastBlock.b[0] = (uint8_t)0x80U; - } - - hashcrypt_sha_one_block(base, &ctxInternal->blk.b[0]); - lastBlock.w[SHA_BLOCK_SIZE / 4U - 1U] = swap_bytes(8u * ctxInternal->fullMessageSize); - hashcrypt_sha_one_block(base, &lastBlock.b[0]); - } - /* poll wait for final digest */ - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - return kStatus_Success; -} - -static void hashcrypt_save_running_hash(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) -{ -#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) - size_t len = (ctxInternal->algo == kHASHCRYPT_Sha1) ? SHA1_LEN : SHA256_LEN; - - /* Wait until digest is ready */ - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - - /* Store partial digest to context */ - for (uint32_t i = 0; i < len; i++) - { - ctxInternal->runningHash[i] = base->DIGEST0[i]; - } -#endif -} - -static void hashcrypt_restore_running_hash(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) -{ -#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) - size_t len = (ctxInternal->algo == kHASHCRYPT_Sha1) ? SHA1_LEN : SHA256_LEN; - - /* When switching from different mode, need to set NEW bit to work properly */ - if ((base->CTRL & HASHCRYPT_CTRL_MODE_MASK) != HASHCRYPT_CTRL_MODE(ctxInternal->algo)) - { - base->CTRL = HASHCRYPT_CTRL_NEW_HASH(1); - base->CTRL = HASHCRYPT_CTRL_MODE(ctxInternal->algo) | HASHCRYPT_CTRL_NEW_HASH(1); - } - /* Set RELOAD bit to allow registers to be used */ - base->CTRL |= HASHCRYPT_CTRL_RELOAD_MASK; - - /* Reload partial hash digest */ - for (uint32_t i = 0; i < len; i++) - { - base->RELOAD[i] = ctxInternal->runningHash[i]; - } - /* Clear RELOAD register before continuing */ - base->CTRL &= ~HASHCRYPT_CTRL_RELOAD_MASK; -#endif -} - -status_t HASHCRYPT_SHA(HASHCRYPT_Type *base, - hashcrypt_algo_t algo, - const uint8_t *input, - size_t inputSize, - uint8_t *output, - size_t *outputSize) -{ - hashcrypt_hash_ctx_t hashCtx; - status_t status; - - status = HASHCRYPT_SHA_Init(base, &hashCtx, algo); - if (status != kStatus_Success) - { - return status; - } - - status = HASHCRYPT_SHA_Update(base, &hashCtx, input, inputSize); - if (status != kStatus_Success) - { - return status; - } - - status = HASHCRYPT_SHA_Finish(base, &hashCtx, output, outputSize); - - return status; -} - -status_t HASHCRYPT_SHA_Init(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo) -{ - status_t status; - - hashcrypt_sha_ctx_internal_t *ctxInternal; - /* compile time check for the correct structure size */ - BUILD_ASSERT(sizeof(hashcrypt_hash_ctx_t) >= sizeof(hashcrypt_sha_ctx_internal_t), hashcrypt_hash_ctx_t_size); - - status = hashcrypt_sha_check_input_args(base, ctx, algo); - if (status != kStatus_Success) - { - return status; - } - - /* set algorithm in context struct for later use */ - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; - ctxInternal->algo = algo; - ctxInternal->blksz = 0u; -#ifdef HASHCRYPT_SHA_DO_WIPE_CONTEXT - for (int i = 0; i < sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]); i++) - { - ctxInternal->blk.w[i] = 0u; - } -#endif /* HASHCRYPT_SHA_DO_WIPE_CONTEXT */ - ctxInternal->state = kHASHCRYPT_HashInit; - ctxInternal->fullMessageSize = 0; - return kStatus_Success; -} - -status_t HASHCRYPT_SHA_Update(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize) -{ - bool isUpdateState; - status_t status; - hashcrypt_sha_ctx_internal_t *ctxInternal; - size_t blockSize; - - if (inputSize == 0U) - { - return kStatus_Success; - } - - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; -#ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT - status = hashcrypt_sha_check_context(base, ctxInternal); - if (kStatus_Success != status) - { - return status; - } -#endif /* HASHCRYPT_SHA_DO_CHECK_CONTEXT */ - - ctxInternal->fullMessageSize += inputSize; - blockSize = SHA_BLOCK_SIZE; - /* if we are still less than 64 bytes, keep only in context */ - if ((ctxInternal->blksz + inputSize) <= blockSize) - { - (void)hashcrypt_memcpy((&ctxInternal->blk.b[0]) + ctxInternal->blksz, input, inputSize); - ctxInternal->blksz += inputSize; - return kStatus_Success; - } - else - { - isUpdateState = ctxInternal->state == kHASHCRYPT_HashUpdate; - if (!isUpdateState) - { - /* start NEW hash */ - hashcrypt_engine_init(base, ctxInternal->algo); - ctxInternal->state = kHASHCRYPT_HashUpdate; - } - else - { - hashcrypt_restore_running_hash(base, ctxInternal); - } - } - - /* process message data */ - /* Data Synchronization Barrier */ - __DSB(); - status = hashcrypt_sha_process_message_data(base, ctxInternal, input, inputSize); - hashcrypt_save_running_hash(base, ctxInternal); - return status; -} - -status_t HASHCRYPT_SHA_Finish(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize) -{ - size_t algOutSize = 0; - status_t status; - hashcrypt_sha_ctx_internal_t *ctxInternal; -#ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT - uint32_t *ctxW; - uint32_t i; -#endif /* HASHCRYPT_SHA_DO_CHECK_CONTEXT */ - - if (output == NULL) - { - return kStatus_InvalidArgument; - } - - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; -#ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT - status = hashcrypt_sha_check_context(base, ctxInternal); - if (kStatus_Success != status) - { - return status; - } -#endif /* HASHCRYPT_SHA_DO_CHECK_CONTEXT */ - - if (ctxInternal->state == kHASHCRYPT_HashInit) - { - hashcrypt_engine_init(base, ctxInternal->algo); - } - else - { - hashcrypt_restore_running_hash(base, ctxInternal); - } - - size_t outSize = 0u; - - /* compute algorithm output length */ - switch (ctxInternal->algo) - { - case kHASHCRYPT_Sha1: - outSize = (size_t)kHASHCRYPT_OutLenSha1; - break; - case kHASHCRYPT_Sha256: - outSize = (size_t)kHASHCRYPT_OutLenSha256; - break; - default: - /* All the cases have been listed above, the default clause should not be reached. */ - break; - } - algOutSize = outSize; - - /* flush message last incomplete block, if there is any, and add padding bits */ - status = hashcrypt_sha_finalize(base, ctxInternal); - - if (outputSize != NULL) - { - if (algOutSize < *outputSize) - { - *outputSize = algOutSize; - } - else - { - algOutSize = *outputSize; - } - } - - hashcrypt_get_data(base, (uint32_t *)(uintptr_t)output, algOutSize); - -#ifdef HASHCRYPT_SHA_DO_WIPE_CONTEXT - ctxW = (uint32_t *)ctx; - for (i = 0; i < HASHCRYPT_HASH_CTX_SIZE; i++) - { - ctxW[i] = 0u; - } -#endif /* HASHCRYPT_SHA_DO_WIPE_CONTEXT */ - return status; -} - -void HASHCRYPT_SHA_SetCallback(HASHCRYPT_Type *base, - hashcrypt_hash_ctx_t *ctx, - hashcrypt_callback_t callback, - void *userData) -{ - hashcrypt_sha_ctx_internal_t *ctxInternal; - - s_ctx = ctx; - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; - ctxInternal->hashCallback = callback; - ctxInternal->userData = userData; - - (void)EnableIRQ(HASHCRYPT_IRQn); -} - -status_t HASHCRYPT_SHA_UpdateNonBlocking(HASHCRYPT_Type *base, - hashcrypt_hash_ctx_t *ctx, - const uint8_t *input, - size_t inputSize) -{ - hashcrypt_sha_ctx_internal_t *ctxInternal; - uint32_t numBlocks; - status_t status; - - if (inputSize == 0U) - { - return kStatus_Success; - } - - if (0U != ((uintptr_t)input & 0x3U)) - { - return kStatus_Fail; - } - - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; - status = hashcrypt_sha_check_context(base, ctxInternal); - if (kStatus_Success != status) - { - return status; - } - - ctxInternal->fullMessageSize = inputSize; - ctxInternal->remainingBlcks = inputSize / SHA_BLOCK_SIZE; - ctxInternal->blksz = inputSize % SHA_BLOCK_SIZE; - - /* copy last incomplete block to context */ - if ((ctxInternal->blksz > 0U) && (ctxInternal->blksz <= SHA_BLOCK_SIZE)) - { - (void)hashcrypt_memcpy((&ctxInternal->blk.b[0]), input + SHA_BLOCK_SIZE * ctxInternal->remainingBlcks, - ctxInternal->blksz); - } - - if (ctxInternal->remainingBlcks >= SHA_MASTER_MAX_BLOCKS) - { - numBlocks = SHA_MASTER_MAX_BLOCKS - 1U; - } - else - { - numBlocks = ctxInternal->remainingBlcks; - } - /* update remainingBlks so that ISR can run another hash if necessary */ - ctxInternal->remainingBlcks -= numBlocks; - - /* compute hash using AHB Master mode for full blocks */ - if (numBlocks > 0U) - { - ctxInternal->state = kHASHCRYPT_HashUpdate; - hashcrypt_engine_init(base, ctxInternal->algo); - - /* Enable digest and error interrupts and start hash */ - base->INTENSET = HASHCRYPT_INTENCLR_DIGEST_MASK | HASHCRYPT_INTENCLR_ERROR_MASK; - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(input); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(numBlocks); - } - /* no full blocks, invoke callback directly */ - else - { - ctxInternal->hashCallback(HASHCRYPT, ctx, status, ctxInternal->userData); - } - - return status; -} - -status_t HASHCRYPT_AES_SetKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *key, size_t keySize) -{ - status_t retVal = kStatus_InvalidArgument; - - switch (keySize) - { - case 16: - handle->keySize = kHASHCRYPT_Aes128; - break; - case 24: - handle->keySize = kHASHCRYPT_Aes192; - break; - case 32: - handle->keySize = kHASHCRYPT_Aes256; - break; - default: - handle->keySize = kHASHCRYPT_InvalidKey; - break; - } - - if (handle->keySize == kHASHCRYPT_InvalidKey) - { - return retVal; - } - - if (handle->keyType == kHASHCRYPT_SecretKey) - { - /* for kHASHCRYPT_SecretKey just return Success */ - retVal = kStatus_Success; - } - else if (handle->keyType == kHASHCRYPT_UserKey) - { - retVal = hashcrypt_get_key_from_unaligned_src((uint8_t *)&handle->keyWord[0], key, keySize); - } - else - { - retVal = kStatus_InvalidArgument; - } - - return retVal; -} - -status_t HASHCRYPT_AES_EncryptEcb( - HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size) -{ - status_t status = kStatus_Fail; - - if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesEcb) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load message and get result */ - status = hashcrypt_aes_one_block(base, plaintext, ciphertext, size); - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - - return status; -} - -status_t HASHCRYPT_AES_DecryptEcb( - HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size) -{ - status_t status = kStatus_Fail; - - if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesEcb) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_DECRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load message and get result */ - status = hashcrypt_aes_one_block(base, ciphertext, plaintext, size); - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -status_t HASHCRYPT_AES_EncryptCbc(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t iv[16]) -{ - status_t status = kStatus_Fail; - - if (0U != ((size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load 16b iv */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, 16); - - /* load message and get result */ - status = hashcrypt_aes_one_block(base, plaintext, ciphertext, size); - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -status_t HASHCRYPT_AES_DecryptCbc(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t iv[16]) -{ - status_t status = kStatus_Fail; - - if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_DECRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load iv */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, 16); - - /* load message and get result */ - status = hashcrypt_aes_one_block(base, ciphertext, plaintext, size); - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *input, - uint8_t *output, - size_t size, - uint8_t counter[HASHCRYPT_AES_BLOCK_SIZE], - uint8_t counterlast[HASHCRYPT_AES_BLOCK_SIZE], - size_t *szLeft) -{ - uint32_t lastSize; - uint8_t lastBlock[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - uint8_t *lastEncryptedCounter; - status_t status = kStatus_Fail; - - if (handle->keySize == kHASHCRYPT_InvalidKey) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCtr) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load nonce */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)counter, 16); - - lastSize = size % HASHCRYPT_AES_BLOCK_SIZE; - size -= lastSize; - - /* encrypt full 16byte blocks */ - status = hashcrypt_aes_one_block(base, input, output, size); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - - while (size != 0U) - { - ctrIncrement(counter); - size -= 16u; - input += 16; - output += 16; - } - - if (lastSize != 0U) - { - if (counterlast != NULL) - { - lastEncryptedCounter = counterlast; - } - else - { - lastEncryptedCounter = lastBlock; - } - - /* Perform encryption with all zeros to get last counter. XOR with zeros doesn't change. */ - status = hashcrypt_aes_one_block(base, lastBlock, lastEncryptedCounter, HASHCRYPT_AES_BLOCK_SIZE); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* remain output = input XOR counterlast */ - for (uint32_t i = 0; i < lastSize; i++) - { - output[i] = input[i] ^ lastEncryptedCounter[i]; - } - /* Increment counter parameter */ - ctrIncrement(counter); - } - else - { - lastSize = HASHCRYPT_AES_BLOCK_SIZE; - /* no remaining bytes in couterlast so clearing it */ - if (counterlast != NULL) - { - (void)memset(counterlast, 0, HASHCRYPT_AES_BLOCK_SIZE); - } - } - - if (szLeft != NULL) - { - *szLeft = HASHCRYPT_AES_BLOCK_SIZE - lastSize; - } - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return kStatus_Success; -} - -status_t HASHCRYPT_AES_CryptOfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *input, - uint8_t *output, - size_t size, - const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]) -{ - status_t status = kStatus_Fail; - uint8_t zeroes[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - uint8_t blockOutput[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - - if (handle->keySize == kHASHCRYPT_InvalidKey) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load iv */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, HASHCRYPT_AES_BLOCK_SIZE); - - /*Use AES CBC mode and feed input with zeroes as input*/ - /*Output block is then XORed with input*/ - - while (size >= 16u) - { - status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* XOR input with output block to get output*/ - for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) - { - output[i] = input[i] ^ blockOutput[i]; - } - size -= 16u; - output += 16; - input += 16; - } - - /* OFB can have non-block multiple size.*/ - if (size != 0U) - { - status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - - /* XOR input with output block to get output*/ - for (uint32_t i = 0; i < size; i++) - { - output[i] = input[i] ^ blockOutput[i]; - } - } - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -status_t HASHCRYPT_AES_EncryptCfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]) -{ - status_t status = kStatus_Fail; - uint8_t zeroes[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - uint8_t blockOutput[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - - /* For CFB mode size must be 16-byte multiple */ - if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load iv */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, HASHCRYPT_AES_BLOCK_SIZE); - - /*Use AES CBC mode and feed input with zeroes for first block */ - /*Output block is then XORed with plaintext to get ciphertext*/ - - status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* XOR plaintext with output block to get ciphertext*/ - for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) - { - ciphertext[i] = plaintext[i] ^ blockOutput[i]; - } - size -= 16u; - - /*Remaining blocks use previous plaintext as input for aes block function */ - while (size >= 16u) - { - status = hashcrypt_aes_one_block(base, plaintext, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - ciphertext += 16; - plaintext += 16; - - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* XOR plaintext with output block to get ciphertext*/ - for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) - { - ciphertext[i] = plaintext[i] ^ blockOutput[i]; - } - size -= 16u; - } - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -status_t HASHCRYPT_AES_DecryptCfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]) -{ - status_t status = kStatus_Fail; - uint8_t zeroes[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - uint8_t blockOutput[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - - /* For CFB mode size must be 16-byte multiple */ - if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load iv */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, HASHCRYPT_AES_BLOCK_SIZE); - - /*Use AES CBC mode and feed input with zeroes for first block */ - /*Output block is then XORed with ciphertext to get plaintext*/ - - status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* XOR ciphertext with output block to get plaintext*/ - for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) - { - plaintext[i] = ciphertext[i] ^ blockOutput[i]; - } - size -= 16u; - - /*Remaining blocks use previous plaintext as input for aes block function */ - while (size >= 16u) - { - status = hashcrypt_aes_one_block(base, plaintext, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - ciphertext += 16; - plaintext += 16; - - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* XOR plaintext with ciphertext block to get plaintext*/ - for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) - { - plaintext[i] = ciphertext[i] ^ blockOutput[i]; - } - size -= 16u; - } - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -void HASHCRYPT_DriverIRQHandler(void); -void HASHCRYPT_DriverIRQHandler(void) -{ - hashcrypt_sha_ctx_internal_t *ctxInternal; - HASHCRYPT_Type *base = HASHCRYPT; - uint32_t numBlocks; - status_t status; - - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)s_ctx; - - if (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) - { - if (ctxInternal->remainingBlcks > 0U) - { - if (ctxInternal->remainingBlcks >= SHA_MASTER_MAX_BLOCKS) - { - numBlocks = SHA_MASTER_MAX_BLOCKS - 1U; - } - else - { - numBlocks = ctxInternal->remainingBlcks; - } - /* some blocks still remaining, update remainingBlcks for next ISR and start another hash */ - ctxInternal->remainingBlcks -= numBlocks; - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(numBlocks); - return; - } - /* no full blocks left, disable interrupts and AHB master mode */ - base->INTENCLR = HASHCRYPT_INTENCLR_DIGEST_MASK | HASHCRYPT_INTENCLR_ERROR_MASK; - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(0); - hashcrypt_save_running_hash(base, ctxInternal); - status = kStatus_Success; - } - else - { - status = kStatus_Fail; - } - - /* Invoke callback if there is one */ - if (NULL != ctxInternal->hashCallback) - { - ctxInternal->hashCallback(HASHCRYPT, s_ctx, status, ctxInternal->userData); - } -} - -void HASHCRYPT_Init(HASHCRYPT_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_HashCrypt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - RESET_PeripheralReset(kHASHCRYPT_RST_SHIFT_RSTn); -} - -void HASHCRYPT_Deinit(HASHCRYPT_Type *base) -{ - RESET_SetPeripheralReset(kHASHCRYPT_RST_SHIFT_RSTn); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_HashCrypt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_hashcrypt.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_hashcrypt.h deleted file mode 100644 index fa15b8cf710..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_hashcrypt.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - * Copyright 2017-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_HASHCRYPT_H_ -#define _FSL_HASHCRYPT_H_ - -#include "fsl_common.h" - -/*! @brief HASHCRYPT status return codes. */ -enum _hashcrypt_status -{ - kStatus_HASHCRYPT_Again = - MAKE_STATUS(kStatusGroup_HASHCRYPT, 0), /*!< Non-blocking function shall be called again. */ -}; - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! - * @addtogroup hashcrypt_driver - * @{ - */ -/*! @name Driver version */ -/*@{*/ -/*! @brief HASHCRYPT driver version. Version 2.2.6. - * - * Current version: 2.2.6 - * - * Change log: - * - Version 2.0.0 - * - Initial version - * - Version 2.0.1 - * - Support loading AES key from unaligned address - * - Version 2.0.2 - * - Support loading AES key from unaligned address for different compiler and core variants - * - Version 2.0.3 - * - Remove SHA512 and AES ICB algorithm definitions - * - Version 2.0.4 - * - Add SHA context switch support - * - Version 2.1.0 - * - Update the register name and macro to align with new header. - * - Version 2.1.1 - * - Fix MISRA C-2012. - * - Version 2.1.2 - * - Support loading AES input data from unaligned address. - * - Version 2.1.3 - * - Fix MISRA C-2012. - * - Version 2.1.4 - * - Fix context switch cannot work when switching from AES. - * - Version 2.1.5 - * - Add data synchronization barrier inside hashcrypt_sha_ldm_stm_16_words() - * to prevent possible optimization issue. - * - Version 2.2.0 - * - Add AES-OFB and AES-CFB mixed IP/SW modes. - * - Version 2.2.1 - * - Add data synchronization barrier inside hashcrypt_sha_ldm_stm_16_words() - * prevent compiler from reordering memory write when -O2 or higher is used. - * - Version 2.2.2 - * - Add data synchronization barrier inside hashcrypt_sha_ldm_stm_16_words() - * to fix optimization issue - * - Version 2.2.3 - * - Added check for size in hashcrypt_aes_one_block to prevent overflowing COUNT field in MEMCTRL register, if its - * bigger than COUNT field do a multiple runs. - * - Version 2.2.4 - * - In all HASHCRYPT_AES_xx functions have been added setting CTRL_MODE bitfield to 0 after processing data, which - * decreases power consumption. - * - Version 2.2.5 - * - Add data synchronization barrier and instruction synchronization barrier inside - * hashcrypt_sha_process_message_data() to fix optimization issue - * - Version 2.2.6 - * - Add data synchronization barrier inside HASHCRYPT_SHA_Update() and hashcrypt_get_data() function to fix - * optimization issue on MDK and ARMGCC release targets - */ -#define FSL_HASHCRYPT_DRIVER_VERSION (MAKE_VERSION(2, 2, 6)) -/*@}*/ - -/*! @brief Algorithm definitions correspond with the values for Mode field in Control register !*/ -#define HASHCRYPT_MODE_SHA1 0x1 -#define HASHCRYPT_MODE_SHA256 0x2 -#define HASHCRYPT_MODE_AES 0x4 - -/*! @brief Algorithm used for Hashcrypt operation */ -typedef enum _hashcrypt_algo_t -{ - kHASHCRYPT_Sha1 = HASHCRYPT_MODE_SHA1, /*!< SHA_1 */ - kHASHCRYPT_Sha256 = HASHCRYPT_MODE_SHA256, /*!< SHA_256 */ - kHASHCRYPT_Aes = HASHCRYPT_MODE_AES, /*!< AES */ -} hashcrypt_algo_t; - -/*! @} */ - -/******************************************************************************* - * AES Definitions - *******************************************************************************/ - -/*! - * @addtogroup hashcrypt_driver_aes - * @{ - */ - -/*! AES block size in bytes */ -#define HASHCRYPT_AES_BLOCK_SIZE 16U -#define AES_ENCRYPT 0 -#define AES_DECRYPT 1 - -/*! @brief AES mode */ -typedef enum _hashcrypt_aes_mode_t -{ - kHASHCRYPT_AesEcb = 0U, /*!< AES ECB mode */ - kHASHCRYPT_AesCbc = 1U, /*!< AES CBC mode */ - kHASHCRYPT_AesCtr = 2U, /*!< AES CTR mode */ -} hashcrypt_aes_mode_t; - -/*! @brief Size of AES key */ -typedef enum _hashcrypt_aes_keysize_t -{ - kHASHCRYPT_Aes128 = 0U, /*!< AES 128 bit key */ - kHASHCRYPT_Aes192 = 1U, /*!< AES 192 bit key */ - kHASHCRYPT_Aes256 = 2U, /*!< AES 256 bit key */ - kHASHCRYPT_InvalidKey = 3U, /*!< AES invalid key */ -} hashcrypt_aes_keysize_t; - -/*! @brief HASHCRYPT key source selection. - * - */ -typedef enum _hashcrypt_key -{ - kHASHCRYPT_UserKey = 0xc3c3U, /*!< HASHCRYPT user key */ - kHASHCRYPT_SecretKey = 0x3c3cU, /*!< HASHCRYPT secret key (dedicated hw bus from PUF) */ -} hashcrypt_key_t; - -/*! @brief Specify HASHCRYPT's key resource. */ -struct _hashcrypt_handle -{ - uint32_t keyWord[8]; /*!< Copy of user key (set by HASHCRYPT_AES_SetKey(). */ - hashcrypt_aes_keysize_t keySize; - hashcrypt_key_t keyType; /*!< For operations with key (such as AES encryption/decryption), specify key type. */ -} __attribute__((aligned)); - -typedef struct _hashcrypt_handle hashcrypt_handle_t; - -/*! - *@} - */ /* end of hashcrypt_driver_aes */ - -/******************************************************************************* - * HASH Definitions - ******************************************************************************/ -/*! - * @addtogroup hashcrypt_driver_hash - * @{ - */ - -/*! @brief HASHCRYPT HASH Context size. */ -#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) -#define HASHCRYPT_HASH_CTX_SIZE 30 -#else -#define HASHCRYPT_HASH_CTX_SIZE 22 -#endif - -/*! @brief Storage type used to save hash context. */ -typedef struct _hashcrypt_hash_ctx_t -{ - uint32_t x[HASHCRYPT_HASH_CTX_SIZE]; /*!< storage */ -} hashcrypt_hash_ctx_t; - -/*! @brief HASHCRYPT background hash callback function. */ -typedef void (*hashcrypt_callback_t)(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, status_t status, void *userData); - -/*! - *@} - */ /* end of hashcrypt_driver_hash */ - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup hashcrypt_driver - * @{ - */ - -/*! - * @brief Enables clock and disables reset for HASHCRYPT peripheral. - * - * Enable clock and disable reset for HASHCRYPT. - * - * @param base HASHCRYPT base address - */ -void HASHCRYPT_Init(HASHCRYPT_Type *base); - -/*! - * @brief Disables clock for HASHCRYPT peripheral. - * - * Disable clock and enable reset. - * - * @param base HASHCRYPT base address - */ -void HASHCRYPT_Deinit(HASHCRYPT_Type *base); - -/*! - *@} - */ /* end of hashcrypt_driver */ - -/******************************************************************************* - * AES API - ******************************************************************************/ - -/*! - * @addtogroup hashcrypt_driver_aes - * @{ - */ - -/*! - * @brief Set AES key to hashcrypt_handle_t struct and optionally to HASHCRYPT. - * - * Sets the AES key for encryption/decryption with the hashcrypt_handle_t structure. - * The hashcrypt_handle_t input argument specifies key source. - * - * @param base HASHCRYPT peripheral base address. - * @param handle Handle used for the request. - * @param key 0-mod-4 aligned pointer to AES key. - * @param keySize AES key size in bytes. Shall equal 16, 24 or 32. - * @return status from set key operation - */ -status_t HASHCRYPT_AES_SetKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *key, size_t keySize); - -/*! - * @brief Encrypts AES on one or multiple 128-bit block(s). - * - * Encrypts AES. - * The source plaintext and destination ciphertext can overlap in system memory. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @return Status from encrypt operation - */ -status_t HASHCRYPT_AES_EncryptEcb( - HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size); - -/*! - * @brief Decrypts AES on one or multiple 128-bit block(s). - * - * Decrypts AES. - * The source ciphertext and destination plaintext can overlap in system memory. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param ciphertext Input plain text to encrypt - * @param[out] plaintext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @return Status from decrypt operation - */ -status_t HASHCRYPT_AES_DecryptEcb( - HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size); - -/*! - * @brief Encrypts AES using CBC block mode. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return Status from encrypt operation - */ -status_t HASHCRYPT_AES_EncryptCbc(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t iv[16]); - -/*! - * @brief Decrypts AES using CBC block mode. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param ciphertext Input cipher text to decrypt - * @param[out] plaintext Output plain text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return Status from decrypt operation - */ -status_t HASHCRYPT_AES_DecryptCbc(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t iv[16]); - -/*! - * @brief Encrypts or decrypts AES using CTR block mode. - * - * Encrypts or decrypts AES using CTR block mode. - * AES CTR mode uses only forward AES cipher and same algorithm for encryption and decryption. - * The only difference between encryption and decryption is that, for encryption, the input argument - * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text - * and the output argument is plain text. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param input Input data for CTR block mode - * @param[out] output Output data for CTR block mode - * @param size Size of input and output data in bytes - * @param[in,out] counter Input counter (updates on return) - * @param[out] counterlast Output cipher of last counter, for chained CTR calls (statefull encryption). NULL can be - * passed if chained calls are - * not used. - * @param[out] szLeft Output number of bytes in left unused in counterlast block. NULL can be passed if chained calls - * are not used. - * @return Status from encrypt operation - */ -status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *input, - uint8_t *output, - size_t size, - uint8_t counter[HASHCRYPT_AES_BLOCK_SIZE], - uint8_t counterlast[HASHCRYPT_AES_BLOCK_SIZE], - size_t *szLeft); - -/*! - * @brief Encrypts or decrypts AES using OFB block mode. - * - * Encrypts or decrypts AES using OFB block mode. - * AES OFB mode uses only forward AES cipher and same algorithm for encryption and decryption. - * The only difference between encryption and decryption is that, for encryption, the input argument - * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text - * and the output argument is plain text. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param input Input data for OFB block mode - * @param[out] output Output data for OFB block mode - * @param size Size of input and output data in bytes - * @param iv Input initial vector to combine with the first input block. - * @return Status from encrypt operation - */ - -status_t HASHCRYPT_AES_CryptOfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *input, - uint8_t *output, - size_t size, - const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]); - -/*! - * @brief Encrypts AES using CFB block mode. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return Status from encrypt operation - */ - -status_t HASHCRYPT_AES_EncryptCfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t iv[16]); - -/*! - * @brief Decrypts AES using CFB block mode. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param ciphertext Input cipher text to decrypt - * @param[out] plaintext Output plaintext text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return Status from encrypt operation - */ - -status_t HASHCRYPT_AES_DecryptCfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t iv[16]); -/*! - *@} - */ /* end of hashcrypt_driver_aes */ - -/******************************************************************************* - * HASH API - ******************************************************************************/ - -/*! - * @addtogroup hashcrypt_driver_hash - * @{ - */ - -/*! - * @brief Create HASH on given data - * - * Perform the full SHA in one function call. The function is blocking. - * - * @param base HASHCRYPT peripheral base address - * @param algo Underlaying algorithm to use for hash computation. - * @param input Input data - * @param inputSize Size of input data in bytes - * @param[out] output Output hash data - * @param[out] outputSize Output parameter storing the size of the output hash in bytes - * @return Status of the one call hash operation. - */ -status_t HASHCRYPT_SHA(HASHCRYPT_Type *base, - hashcrypt_algo_t algo, - const uint8_t *input, - size_t inputSize, - uint8_t *output, - size_t *outputSize); - -/*! - * @brief Initialize HASH context - * - * This function initializes the HASH. - * - * @param base HASHCRYPT peripheral base address - * @param[out] ctx Output hash context - * @param algo Underlaying algorithm to use for hash computation. - * @return Status of initialization - */ -status_t HASHCRYPT_SHA_Init(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo); - -/*! - * @brief Add data to current HASH - * - * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be - * hashed. The functions blocks. If it returns kStatus_Success, the running hash - * has been updated (HASHCRYPT has processed the input data), so the memory at \p input pointer - * can be released back to system. The HASHCRYPT context buffer is updated with the running hash - * and with all necessary information to support possible context switch. - * - * @param base HASHCRYPT peripheral base address - * @param[in,out] ctx HASH context - * @param input Input data - * @param inputSize Size of input data in bytes - * @return Status of the hash update operation - */ -status_t HASHCRYPT_SHA_Update(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize); - -/*! - * @brief Finalize hashing - * - * Outputs the final hash (computed by HASHCRYPT_HASH_Update()) and erases the context. - * - * @param base HASHCRYPT peripheral base address - * @param[in,out] ctx Input hash context - * @param[out] output Output hash data - * @param[in,out] outputSize Optional parameter (can be passed as NULL). On function entry, it specifies the size of - * output[] buffer. On function return, it stores the number of updated output bytes. - * @return Status of the hash finish operation - */ -status_t HASHCRYPT_SHA_Finish(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize); - -/*! - *@} - */ /* end of hashcrypt_driver_hash */ - -/*! - * @addtogroup hashcrypt_background_driver_hash - * @{ - */ - -/*! - * @brief Initializes the HASHCRYPT handle for background hashing. - * - * This function initializes the hash context for background hashing - * (Non-blocking) APIs. This is less typical interface to hash function, but can be used - * for parallel processing, when main CPU has something else to do. - * Example is digital signature RSASSA-PKCS1-V1_5-VERIFY((n,e),M,S) algorithm, where - * background hashing of M can be started, then CPU can compute S^e mod n - * (in parallel with background hashing) and once the digest becomes available, - * CPU can proceed to comparison of EM with EM'. - * - * @param base HASHCRYPT peripheral base address. - * @param[out] ctx Hash context. - * @param callback Callback function. - * @param userData User data (to be passed as an argument to callback function, once callback is invoked from isr). - */ -void HASHCRYPT_SHA_SetCallback(HASHCRYPT_Type *base, - hashcrypt_hash_ctx_t *ctx, - hashcrypt_callback_t callback, - void *userData); - -/*! - * @brief Create running hash on given data. - * - * Configures the HASHCRYPT to compute new running hash as AHB master - * and returns immediately. HASHCRYPT AHB Master mode supports only aligned \p input - * address and can be called only once per continuous block of data. Every call to this function - * must be preceded with HASHCRYPT_SHA_Init() and finished with HASHCRYPT_SHA_Finish(). - * Once callback function is invoked by HASHCRYPT isr, it should set a flag - * for the main application to finalize the hashing (padding) and to read out the final digest - * by calling HASHCRYPT_SHA_Finish(). - * - * @param base HASHCRYPT peripheral base address - * @param ctx Specifies callback. Last incomplete 512-bit block of the input is copied into clear buffer for padding. - * @param input 32-bit word aligned pointer to Input data. - * @param inputSize Size of input data in bytes (must be word aligned) - * @return Status of the hash update operation. - */ -status_t HASHCRYPT_SHA_UpdateNonBlocking(HASHCRYPT_Type *base, - hashcrypt_hash_ctx_t *ctx, - const uint8_t *input, - size_t inputSize); -/*! - *@} - */ /* end of hashcrypt_background_driver_hash */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_HASHCRYPT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c.c deleted file mode 100644 index 9ecde80c90a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c.c +++ /dev/null @@ -1,2085 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_i2c.h" -#include "fsl_flexcomm.h" -#include -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c" -#endif - -/*! @brief Common sets of flags used by the driver's transactional layer internally. */ -enum _i2c_flag_constants -{ - kI2C_MasterIrqFlags = I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | - I2C_INTSTAT_EVENTTIMEOUT_MASK | I2C_INTSTAT_SCLTIMEOUT_MASK, - kI2C_SlaveIrqFlags = I2C_INTSTAT_SLVPENDING_MASK | I2C_INTSTAT_SLVDESEL_MASK, -}; - -/*! - * @brief Used for conversion from `flexcomm_irq_handler_t` to `flexcomm_i2c_master_irq_handler_t` and - * `flexcomm_i2c_slave_irq_handler_t`. - */ -typedef union i2c_to_flexcomm -{ - flexcomm_i2c_master_irq_handler_t i2c_master_handler; - flexcomm_i2c_slave_irq_handler_t i2c_slave_handler; - flexcomm_irq_handler_t flexcomm_handler; -} i2c_to_flexcomm_t; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Waits for Master Pending status bit to set and check for bus error status. - * - * @param base The I2C peripheral base address. - * @return Bus status. - */ -static status_t I2C_PendingStatusWait(I2C_Type *base); - -/*! - * @brief Prepares the transfer state machine and fills in the command buffer. - * @param base The I2C peripheral base address. - * @param handle Master nonblocking driver handle. - * @param xfer The I2C transfer configuration structure. - */ -static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Resets the slave hardware state machine. - * According to documentation, after disabling slave to rest the slave hardware state machine, the register - * configuration remains unchanged. - * @param base The I2C peripheral base address. - */ -static void I2C_SlaveInternalStateMachineReset(I2C_Type *base); - -/*! - * @brief Compute CLKDIV - * - * This function computes CLKDIV value according to the given bus speed and Flexcomm source clock frequency. - * This setting is used by hardware during slave clock stretching. - * - * @param base The I2C peripheral base address. - * @return status of the operation - */ -static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal); - -/*! - * @brief Poll wait for the SLVPENDING flag. - * - * Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register. - * - * @param base The I2C peripheral base address. - * @return status register at time the SLVPENDING bit is read as set - */ -static uint32_t I2C_SlavePollPending(I2C_Type *base); - -/*! - * @brief Invoke event from I2C_SlaveTransferHandleIRQ(). - * - * Sets the event type to transfer structure and invokes the event callback, if it has been - * enabled by eventMask. - * - * @param base The I2C peripheral base address. - * @param handle The I2C slave handle for non-blocking APIs. - * @param event The I2C slave event to invoke. - */ -static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event); - -/*! - * @brief Handle slave address match event. - * - * Called by Slave interrupt routine to ACK or NACK the matched address. - * It also determines master direction (read or write). - * - * @param base The I2C peripheral base address. - * @return true if the matched address is ACK'ed - * @return false if the matched address is NACK'ed - */ -static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle); - -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. - * @param txData Data to be transmitted to master in response to master read from slave requests. NULL if slave RX only. - * @param txSize Size of txData buffer in bytes. - * @param rxData Data where received data from master will be stored in response to master write to slave requests. NULL - * if slave TX only. - * @param rxSize Size of rxData buffer in bytes. - * @retval #kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, - i2c_slave_handle_t *handle, - const void *txData, - size_t txSize, - void *rxData, - size_t rxSize, - uint32_t eventMask); - -/*! - * @brief Execute master transfer software state machine until FIFOs are exhausted. - * - * For master transmit, the states would be kStartState->kTransmitSubaddrState->kTransmitDataState->kStopState - * For master receive, the states would be kStartState->kTransmitSubaddrState->kStartState->kReceiveDataState-> - * kWaitForCompletionState - * - * @param handle Master nonblocking driver handle. - * @param[out] isDone Set to true if the transfer has completed. - * @retval #kStatus_Success - * @retval #kStatus_I2C_ArbitrationLost - * @retval #kStatus_I2C_Nak - */ -static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone); - -/*! - * @brief Checks the slave response to master's start signal. - * - * @param base I2C peripheral base address. - * @retval kStatus_Success Successfully complete the data transmission. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStataus_I2C_Nak Transfer error, receive NAK during addressing. - */ -static status_t I2C_MasterCheckStartResponse(I2C_Type *base); -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map i2c instance number to base address. */ -static const uint32_t s_i2cBaseAddrs[FSL_FEATURE_SOC_I2C_COUNT] = I2C_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_i2cIRQ[] = I2C_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * param base The I2C peripheral base address. - * return I2C instance number starting from 0. - */ -uint32_t I2C_GetInstance(I2C_Type *base) -{ - uint32_t i; - for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_I2C_COUNT; i++) - { - if ((uint32_t)base == s_i2cBaseAddrs[i]) - { - break; - } - } - assert(i < (uint32_t)FSL_FEATURE_SOC_I2C_COUNT); - return i; -} - -/*! - * brief Provides a default configuration for the I2C master peripheral. - * - * This function provides the following default configuration for the I2C master peripheral: - * code - * masterConfig->enableMaster = true; - * masterConfig->baudRate_Bps = 100000U; - * masterConfig->enableTimeout = false; - * endcode - * - * After calling this function, you can override any settings in order to customize the configuration, - * prior to initializing the master driver with I2C_MasterInit(). - * - * param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. - */ -void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) -{ - /* Initializes the configure structure to zero. */ - (void)memset(masterConfig, 0, sizeof(*masterConfig)); - - masterConfig->enableMaster = true; - masterConfig->baudRate_Bps = 100000U; - masterConfig->enableTimeout = false; - masterConfig->timeout_Ms = 35; -} - -/*! - * brief Initializes the I2C master peripheral. - * - * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user - * provided configuration. A software reset is performed prior to configuration. - * - * param base The I2C peripheral base address. - * param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of - * defaults - * that you can override. - * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, - * filter widths, and timeout periods. - */ -void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) -{ - (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); - I2C_MasterEnable(base, masterConfig->enableMaster); - I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); - I2C_MasterSetTimeoutValue(base, masterConfig->timeout_Ms, srcClock_Hz); -} - -/*! - * brief Deinitializes the I2C master peripheral. - * - * This function disables the I2C master peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * param base The I2C peripheral base address. - */ -void I2C_MasterDeinit(I2C_Type *base) -{ - I2C_MasterEnable(base, false); -} - -/*! - * brief Gets the I2C status flags. - * - * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit - * in the return value is set if the flag is asserted. - * - * param base The I2C peripheral base address. - * return State of the status flags: - * - 1: related status flag is set. - * - 0: related status flag is not set. - * see ref _i2c_status_flags, ref _i2c_master_status_flags and ref _i2c_slave_status_flags. - */ -uint32_t I2C_GetStatusFlags(I2C_Type *base) -{ - uint32_t statusMask = base->STAT; - if ((statusMask & (uint32_t)I2C_STAT_MSTSTATE_MASK) == 0UL) - { - statusMask |= (uint32_t)kI2C_MasterIdleFlag; - } - if (((statusMask & (uint32_t)I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == 3UL) - { - statusMask = (statusMask & ~(uint32_t)I2C_STAT_MSTSTATE_MASK) | (uint32_t)kI2C_MasterAddrNackFlag; - } - if ((statusMask & (uint32_t)I2C_STAT_SLVSTATE_MASK) == 0UL) - { - statusMask |= (uint32_t)kI2C_SlaveAddressedFlag; - } - if ((statusMask & (uint32_t)I2C_STAT_SLVIDX_MASK) == 0UL) - { - statusMask |= (uint32_t)kI2C_SlaveAddress0MatchFlag; - } - if (((statusMask & (uint32_t)I2C_STAT_SLVIDX_MASK) >> I2C_STAT_SLVIDX_SHIFT) == 3UL) - { - statusMask = (statusMask & ~(uint32_t)I2C_STAT_SLVIDX_MASK) | (uint32_t)kI2C_SlaveAddress3MatchFlag; - } - return statusMask; -} - -/*! - * brief Sets the I2C bus frequency for master transactions. - * - * The I2C master is automatically disabled and re-enabled as necessary to configure the baud - * rate. Do not call this function during a transfer, or the transfer is aborted. - * - * param base The I2C peripheral base address. - * param srcClock_Hz I2C functional clock frequency in Hertz. - * param baudRate_Bps Requested bus frequency in bits per second. - */ -void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) -{ - uint32_t scl, divider; - uint32_t mindivider; - uint32_t err, best_err; - uint32_t best_scl = 0U; - uint32_t best_div = 0U; - -#if defined(FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) && (FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) - /* - * RFT1717/RFT1437: workaround for hardware bug when using DMA - * I2C peripheral clock frequency has to be fixed at 8MHz - * source clock is 32MHz or 48MHz so divider is a round integer value - */ - best_div = srcClock_Hz / 8000000U; - best_scl = 8000000U / baudRate_Bps; - - if ((8000000U / best_scl - baudRate_Bps) > (baudRate_Bps - (8000000U / (best_scl + 1U)))) - { - best_scl = best_scl + 1U; - } - - /* - * Fallback to usual baudrate computation method, when: - * 1.Master SCL frequency does not fit in workaround range, - * 2.User's setting of baudRate_Bps is 400kHz while the clock frequency after divval is larger than 2MHz - */ - if ((best_scl > 18U) || ((best_scl < 4U)) || ((baudRate_Bps == 400000U) && (srcClock_Hz / best_div > 2000000U))) - { -#endif /*FSL_FEATURE_I2C_PREPCLKFRG_8MHZ*/ - - /* Calculate the minimal divider value to make sure the clock frequency after divval is not larger than 2MHz */ - /* This is required in RM in order to generate 400kHz baudrate */ - mindivider = ((srcClock_Hz * 10U) / 2000000U + 5U) / 10U; - /* If the scl value with current mindivider is smaller than 4, which is the minimal value register can achieve, - update mindivider */ - if ((srcClock_Hz / mindivider / baudRate_Bps) < 4U) - { - mindivider = srcClock_Hz / 4U / baudRate_Bps; - } - /* Calculate the ideal div and scl value*/ - best_err = 0U; - for (divider = mindivider; divider <= 0x10000U; divider++) - { - /* Calculte ideal scl value, round up the value */ - scl = ((srcClock_Hz * 10U) / (divider * baudRate_Bps) + 5U) / 10U; - - /* adjust it if it is out of range */ - scl = (scl > 18U) ? 18U : scl; - - /* calculate error */ - err = srcClock_Hz - (baudRate_Bps * scl * divider); - if ((err < best_err) || (best_err == 0U)) - { - best_div = divider; - best_scl = scl; - best_err = err; - } - - if ((err == 0U) || (scl <= 4U)) - { - /* either exact value was found - or scl is at its min (it would be even smaller in the next iteration for sure) */ - break; - } - } -#if defined(FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) && (FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) - } -#endif /*FSL_FEATURE_I2C_PREPCLKFRG_8MHZ*/ - base->CLKDIV = I2C_CLKDIV_DIVVAL(best_div - 1U); - if (best_scl % 2U == 0U) - { - base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl / 2U - 2U) | I2C_MSTTIME_MSTSCLHIGH(best_scl / 2U - 2U); - } - else - { - base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl / 2U - 1U) | I2C_MSTTIME_MSTSCLHIGH(best_scl / 2U - 2U); - } -} - -/*! - * brief Sets the I2C bus timeout value. - * - * If the SCL signal remains low or bus does not have event longer than the timeout value, kI2C_SclTimeoutFlag or - * kI2C_EventTimeoutFlag is set. This can indicete the bus is held by slave or any fault occurs to the I2C module. - * - * param base The I2C peripheral base address. - * param timeout_Ms Timeout value in millisecond. - * param srcClock_Hz I2C functional clock frequency in Hertz. - */ -void I2C_MasterSetTimeoutValue(I2C_Type *base, uint8_t timeout_Ms, uint32_t srcClock_Hz) -{ - assert((timeout_Ms != 0U) && (srcClock_Hz != 0U)); - - /* The low 4 bits of the timout reister TIMEOUT is hard-wired to be 1, so the the time out value is always 16 times - the I2C functional clock, we only need to calculate the high bits. */ - uint32_t timeoutValue = ((uint32_t)timeout_Ms * srcClock_Hz / 16UL / 100UL + 5UL) / 10UL; - if (timeoutValue > 0x1000UL) - { - timeoutValue = 0x1000UL; - } - timeoutValue = ((timeoutValue - 1UL) << 4UL) | 0xFUL; - base->TIMEOUT = timeoutValue; -} - -static status_t I2C_PendingStatusWait(I2C_Type *base) -{ - status_t result = kStatus_Success; - uint32_t status; - -#if I2C_RETRY_TIMES != 0U - uint32_t waitTimes = I2C_RETRY_TIMES; -#endif - - do - { - status = I2C_GetStatusFlags(base); - if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) - { - result = kStatus_I2C_EventTimeout; - } - if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) - { - result = kStatus_I2C_SclLowTimeout; - } -#if defined(FSL_FEATURE_I2C_TIMEOUT_RECOVERY) && FSL_FEATURE_I2C_TIMEOUT_RECOVERY - if (result != kStatus_Success) - { - I2C_MasterEnable(base, false); - I2C_MasterEnable(base, true); - break; - } -#endif -#if I2C_RETRY_TIMES != 0U - waitTimes--; - } while (((status & (uint32_t)kI2C_MasterPendingFlag) == 0U) && (waitTimes != 0U)); - - if (waitTimes == 0U) - { -#if defined(FSL_FEATURE_I2C_TIMEOUT_RECOVERY) && FSL_FEATURE_I2C_TIMEOUT_RECOVERY - I2C_MasterEnable(base, false); - I2C_MasterEnable(base, true); -#endif - return kStatus_I2C_Timeout; - } -#else - } while ((status & (uint32_t)kI2C_MasterPendingFlag) == 0U); -#endif - - if ((status & (uint32_t)kI2C_MasterArbitrationLostFlag) != 0U) - { - result = kStatus_I2C_ArbitrationLost; - } - - if ((status & (uint32_t)kI2C_MasterStartStopErrorFlag) != 0U) - { - result = kStatus_I2C_StartStopError; - } - - /* Clear controller state. */ - I2C_ClearStatusFlags( - base, (uint32_t)kI2C_MasterAllClearFlags | (uint32_t)kI2C_EventTimeoutFlag | (uint32_t)kI2C_SclTimeoutFlag); - - return result; -} - -/*! - * brief Sends a START on the I2C bus. - * - * This function is used to initiate a new master mode transfer by sending the START signal. - * The slave address is sent following the I2C START signal. - * - * param base I2C peripheral base pointer - * param address 7-bit slave device address. - * param direction Master transfer directions(transmit/receive). - * retval kStatus_Success Successfully send the start signal. - * retval kStatus_I2C_Busy Current bus is busy. - */ -status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) -{ - status_t result; - result = I2C_PendingStatusWait(base); - if (result != kStatus_Success) - { - return result; - } - - /* Write Address and RW bit to data register */ - base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1U); - /* Start the transfer */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - - return kStatus_Success; -} - -/*! - * brief Sends a STOP signal on the I2C bus. - * - * retval kStatus_Success Successfully send the stop signal. - * retval kStatus_I2C_Timeout Send stop signal failed, timeout. - */ -status_t I2C_MasterStop(I2C_Type *base) -{ - status_t result = I2C_PendingStatusWait(base); - if (result != kStatus_Success) - { - return result; - } - - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - return kStatus_Success; -} - -/*! - * brief Performs a polling send transfer on the I2C bus. - * - * Sends up to a txSize number of bytes to the previously addressed slave device. The slave may - * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this - * function returns #kStatus_I2C_Nak. - * - * param base The I2C peripheral base address. - * param txBuff The pointer to the data to be transferred. - * param txSize The length in bytes of the data to be transferred. - * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * retval kStatus_Success Data was sent successfully. - * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags) -{ - uint32_t master_state; - status_t err; - - const uint8_t *buf = (const uint8_t *)txBuff; - - assert(txBuff != NULL); - - err = kStatus_Success; - while (txSize != 0U) - { - err = I2C_PendingStatusWait(base); - - if (err != kStatus_Success) - { - return err; - } - - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - switch (master_state) - { - case I2C_STAT_MSTCODE_TXREADY: - /* ready to send next byte */ - base->MSTDAT = *buf++; - txSize--; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - break; - - case I2C_STAT_MSTCODE_NACKADR: - case I2C_STAT_MSTCODE_NACKDAT: - err = kStatus_I2C_Nak; - /* Issue nack signal when nacked by slave. */ - (void)I2C_MasterStop(base); - break; - - default: - /* unexpected state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - if (err != kStatus_Success) - { - return err; - } - } - - err = I2C_PendingStatusWait(base); - - if (err != kStatus_Success) - { - return err; - } - -#if !I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK - /* Check nack signal. If master is nacked by slave of the last byte, return kStatus_I2C_Nak. */ - if (((base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == (uint32_t)I2C_STAT_MSTCODE_NACKDAT) - { - (void)I2C_MasterStop(base); - return kStatus_I2C_Nak; - } -#endif - - if (0U == (flags & (uint32_t)kI2C_TransferNoStopFlag)) - { - /* Initiate stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - err = I2C_PendingStatusWait(base); - if (err != kStatus_Success) - { - return err; - } - } - - return kStatus_Success; -} - -/*! - * brief Performs a polling receive transfer on the I2C bus. - * - * param base The I2C peripheral base address. - * param rxBuff The pointer to the data to be transferred. - * param rxSize The length in bytes of the data to be transferred. - * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * retval kStatus_Success Data was received successfully. - * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags) -{ - uint32_t master_state; - status_t err; - - uint8_t *buf = (uint8_t *)(rxBuff); - - assert(rxBuff != NULL); - - err = kStatus_Success; - while (rxSize != 0U) - { - err = I2C_PendingStatusWait(base); - - if (err != kStatus_Success) - { - return err; - } - - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - switch (master_state) - { - case I2C_STAT_MSTCODE_RXREADY: - /* ready to send next byte */ - *(buf++) = (uint8_t)base->MSTDAT; - if (--rxSize != 0U) - { - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - } - else - { - if ((flags & (uint32_t)kI2C_TransferNoStopFlag) == 0U) - { - /* initiate NAK and stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - err = I2C_PendingStatusWait(base); - } - } - break; - - case I2C_STAT_MSTCODE_NACKADR: - case I2C_STAT_MSTCODE_NACKDAT: - /* slave nacked the last byte */ - err = kStatus_I2C_Nak; - break; - - default: - /* unexpected state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - if (err != kStatus_Success) - { - return err; - } - } - - return kStatus_Success; -} - -static status_t I2C_MasterCheckStartResponse(I2C_Type *base) -{ - /* Wait for start signal to be transmitted. */ - status_t result = I2C_PendingStatusWait(base); - - if (result != kStatus_Success) - { - return result; - } - - if (((base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == I2C_STAT_MSTCODE_NACKADR) - { - (void)I2C_MasterStop(base); - return kStatus_I2C_Addr_Nak; - } - return kStatus_Success; -} - -/*! - * brief Performs a master polling transfer on the I2C bus. - * - * note The API does not return until the transfer succeeds or fails due - * to arbitration lost or receiving a NAK. - * - * param base I2C peripheral base address. - * param xfer Pointer to the transfer structure. - * retval kStatus_Success Successfully complete the data transmission. - * retval kStatus_I2C_Busy Previous transmission still not finished. - * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - * retval kStataus_I2C_Addr_Nak Transfer error, receive NAK during addressing. - */ -status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) -{ - status_t result = kStatus_Success; - uint32_t subaddress; - uint8_t subaddrBuf[4]; - i2c_direction_t direction; - int i; - - assert(xfer != NULL); - - /* If start signal is requested, send start signal. */ - if (0U == (xfer->flags & (uint32_t)kI2C_TransferNoStartFlag)) - { - direction = (xfer->subaddressSize != 0U) ? kI2C_Write : xfer->direction; - result = I2C_MasterStart(base, xfer->slaveAddress, direction); - if (result == kStatus_Success) - { - result = I2C_MasterCheckStartResponse(base); - if (result != kStatus_Success) - { - return result; - } - if ((xfer->subaddressSize) != 0U) - { - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) - { - subaddrBuf[i] = (uint8_t)subaddress & 0xffU; - subaddress >>= 8; - } - /* Send subaddress. */ - result = - I2C_MasterWriteBlocking(base, subaddrBuf, xfer->subaddressSize, (uint32_t)kI2C_TransferNoStopFlag); - if (result != kStatus_Success) - { - if (result == kStatus_I2C_Nak) - { - (void)I2C_MasterStop(base); - return kStatus_I2C_Addr_Nak; - } - } - else if (xfer->direction == kI2C_Read) - { - result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction); - if (result == kStatus_Success) - { - result = I2C_MasterCheckStartResponse(base); - if (result != kStatus_Success) - { - return result; - } - } - } - else - { - /* Empty else block to avoid MISRA 14.1 violation. */ - } - } - } - } - - if (result == kStatus_Success) - { - if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0U)) - { - /* Transmit data. */ - result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); - } - else - { - if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0U)) - { - /* Receive Data. */ - result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags); - } - } - } - - if (result == kStatus_I2C_Nak) - { - (void)I2C_MasterStop(base); - } - - return result; -} - -/*! - * brief Creates a new handle for the I2C master non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. - * - * param base The I2C peripheral base address. - * param[out] handle Pointer to the I2C master driver handle. - * param callback User provided pointer to the asynchronous callback function. - * param userData User provided pointer to the application callback data. - */ -void I2C_MasterTransferCreateHandle(I2C_Type *base, - i2c_master_handle_t *handle, - i2c_master_transfer_callback_t callback, - void *userData) -{ - assert(handle != NULL); - - uint32_t instance; - i2c_to_flexcomm_t handler; - handler.i2c_master_handler = I2C_MasterTransferHandleIRQ; - - /* Clear out the handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Save base and instance. */ - handle->completionCallback = callback; - handle->userData = userData; - - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - (void)EnableIRQ(s_i2cIRQ[instance]); -} - -/*! - * brief Performs a non-blocking transaction on the I2C bus. - * - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - * param xfer The pointer to the transfer descriptor. - * retval kStatus_Success The transaction was started successfully. - * retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking - * transaction is already in progress. - */ -status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) -{ - status_t result; - - assert(handle != NULL); - assert(xfer != NULL); - assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); - - /* Return busy if another transaction is in progress. */ - if (handle->state != (uint8_t)kIdleState) - { - return kStatus_I2C_Busy; - } - - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - - /* Prepare transfer state machine. */ - result = I2C_InitTransferStateMachine(base, handle, xfer); - - /* Clear error flags. */ - I2C_ClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Enable I2C internal IRQ sources. */ - I2C_EnableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - - return result; -} - -/*! - * brief Returns number of bytes transferred so far. - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - * param[out] count Number of bytes transferred so far by the non-blocking transaction. - * retval kStatus_Success - * retval #kStatus_I2C_Busy - */ -status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state == (uint8_t)kIdleState) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* There is no necessity to disable interrupts as we read a single integer value */ - *count = handle->transferCount; - return kStatus_Success; -} - -/*! - * brief Terminates a non-blocking I2C master transmission early. - * - * note It is not safe to call this function from an IRQ handler that has a higher priority than the - * I2C peripheral's IRQ priority. - * - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - * retval kStatus_Success A transaction was successfully aborted. - * retval #kStatus_I2C_Timeout Timeout during polling for flags. - */ -status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) -{ - status_t result = kStatus_Success; - uint32_t master_state; - - if (handle->state != (uint8_t)kIdleState) - { - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - - /* Wait until module is ready */ - result = I2C_PendingStatusWait(base); - - if (result != kStatus_Success) - { - handle->state = (uint8_t)kIdleState; - return result; - } - - /* Get the state of the I2C module */ - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if (master_state != (uint32_t)I2C_STAT_MSTCODE_IDLE) - { - /* Send a stop command to finalize the transfer. */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - - /* Wait until the STOP is completed */ - result = I2C_PendingStatusWait(base); - - if (result != kStatus_Success) - { - handle->state = (uint8_t)kIdleState; - return result; - } - } - - /* Reset handle. */ - handle->state = (uint8_t)kIdleState; - handle->checkAddrNack = false; - } - return kStatus_Success; -} - -static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) -{ - struct _i2c_master_transfer *transfer; - - handle->transfer = *xfer; - transfer = &(handle->transfer); - - handle->transferCount = 0; - handle->remainingBytes = transfer->dataSize; - handle->buf = (uint8_t *)transfer->data; - handle->remainingSubaddr = 0; - handle->checkAddrNack = false; - - if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) - { - /* Start condition shall be ommited, switch directly to next phase */ - if (transfer->dataSize == 0U) - { - handle->state = (uint8_t)kStopState; - } - else if (handle->transfer.direction == kI2C_Write) - { - handle->state = (uint8_t)kTransmitDataState; - } - else if (handle->transfer.direction == kI2C_Read) - { - handle->state = (uint8_t)kReceiveDataBeginState; - } - else - { - return kStatus_I2C_InvalidParameter; - } - } - else - { - if (transfer->subaddressSize != 0U) - { - int i; - uint32_t subaddress; - - if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) - { - return kStatus_I2C_InvalidParameter; - } - - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) - { - handle->subaddrBuf[i] = (uint8_t)subaddress & 0xffU; - subaddress >>= 8; - } - handle->remainingSubaddr = transfer->subaddressSize; - } - handle->state = (uint8_t)kStartState; - handle->checkAddrNack = true; - } - - return kStatus_Success; -} - -static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) -{ - uint32_t status; - uint32_t master_state; - struct _i2c_master_transfer *transfer; - status_t err; - - transfer = &(handle->transfer); - bool ignoreNak = ((handle->state == (uint8_t)kWaitForCompletionState) && (handle->remainingBytes == 0U)) -#if I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK - /* If master is nacked by slave after the last byte during transmit, ignore the nack. */ - || ((handle->state == (uint8_t)kStopState) && (handle->remainingBytes == 0U)) -#endif - ; - - *isDone = false; - - status = I2C_GetStatusFlags(base); - - if ((status & I2C_STAT_MSTARBLOSS_MASK) != 0U) - { - I2C_ClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); - return kStatus_I2C_ArbitrationLost; - } - - if ((status & I2C_STAT_MSTSTSTPERR_MASK) != 0U) - { - I2C_ClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); - return kStatus_I2C_StartStopError; - } - - /* Event timeout happens when the time since last bus event has been longer than the time specified by TIMEOUT - register. eg: Start signal fails to generate, no error status is set and transfer hangs if glitch on bus happens - before, the timeout status can be used to avoid the transfer hangs indefinitely. */ - if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) - { - I2C_ClearStatusFlags(base, (uint32_t)kI2C_EventTimeoutFlag); - return kStatus_I2C_EventTimeout; - } - - /* SCL timeout happens when the slave is holding the SCL line low and the time has been longer than the time - specified by TIMEOUT register. */ - if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) - { - I2C_ClearStatusFlags(base, (uint32_t)kI2C_SclTimeoutFlag); - return kStatus_I2C_SclLowTimeout; - } - - if ((status & I2C_STAT_MSTPENDING_MASK) == 0U) - { - return kStatus_I2C_Busy; - } - - /* Get the hardware state of the I2C module */ - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - if (((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || - (master_state == (uint32_t)I2C_STAT_MSTCODE_NACKDAT)) && - (ignoreNak != true)) - { - /* Slave NACKed last byte, issue stop and return error */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = (uint8_t)kWaitForCompletionState; - /* If master is nacked during slave probe or during sending subaddress, return kStatus_I2C_ADDR_Nak. */ - if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (handle->checkAddrNack)) - { - return kStatus_I2C_Addr_Nak; - } - else /* Otherwise just return kStatus_I2C_Nak */ - { - return kStatus_I2C_Nak; - } - } - - err = kStatus_Success; - switch (handle->state) - { - case (uint8_t)kStartState: - if (handle->remainingSubaddr != 0U) - { - /* Subaddress takes precedence over the data transfer, direction is always "write" in this case */ - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1U; - handle->state = (uint8_t)kTransmitSubaddrState; - } - else if (transfer->direction == kI2C_Write) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = (handle->remainingBytes != 0U) ? (uint8_t)kTransmitDataState : (uint8_t)kStopState; - } - else - { - base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; - handle->state = (handle->remainingBytes != 0U) ? (uint8_t)kReceiveDataState : (uint8_t)kStopState; - } - /* Send start condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - break; - - case (uint8_t)kTransmitSubaddrState: - if (master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) - { - return kStatus_I2C_UnexpectedState; - } - /* Most significant subaddress byte comes first */ - base->MSTDAT = handle->subaddrBuf[handle->transfer.subaddressSize - handle->remainingSubaddr]; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - if (--(handle->remainingSubaddr) != 0U) - { - /* There are still subaddress bytes to be transmitted */ - break; - } - if (handle->remainingBytes != 0U) - { - /* There is data to be transferred, if there is write to read turnaround it is necessary to perform - * repeated start */ - handle->state = (transfer->direction == kI2C_Read) ? (uint8_t)kStartState : (uint8_t)kTransmitDataState; - } - else - { - /* No more data, schedule stop condition */ - handle->state = (uint8_t)kStopState; - } - break; - - case (uint8_t)kTransmitDataState: - handle->checkAddrNack = false; - if (master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) - { - return kStatus_I2C_UnexpectedState; - } - base->MSTDAT = *(handle->buf)++; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - if (--handle->remainingBytes == 0U) - { - /* No more data, schedule stop condition */ - handle->state = (uint8_t)kStopState; - } - handle->transferCount++; - break; - - case (uint8_t)kReceiveDataBeginState: - handle->checkAddrNack = false; - if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) - { - return kStatus_I2C_UnexpectedState; - } - (void)base->MSTDAT; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - handle->state = (uint8_t)kReceiveDataState; - break; - - case (uint8_t)kReceiveDataState: - handle->checkAddrNack = false; - if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) - { - return kStatus_I2C_UnexpectedState; - } - *(handle->buf)++ = (uint8_t)base->MSTDAT; - if (--handle->remainingBytes != 0U) - { - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - } - else - { - /* No more data expected, issue NACK and STOP right away */ - if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStopFlag)) - { - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - } - handle->state = (uint8_t)kWaitForCompletionState; - } - handle->transferCount++; - break; - - case (uint8_t)kStopState: - handle->checkAddrNack = false; - if ((transfer->flags & (uint32_t)kI2C_TransferNoStopFlag) != 0U) - { - /* Stop condition is omitted, we are done */ - *isDone = true; - handle->state = (uint8_t)kIdleState; - break; - } - /* Send stop condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = (uint8_t)kWaitForCompletionState; - break; - - case (uint8_t)kWaitForCompletionState: - *isDone = true; - handle->state = (uint8_t)kIdleState; - break; - - case (uint8_t)kIdleState: - default: - /* State machine shall not be invoked again once it enters the idle state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - return err; -} - -/*! - * brief Reusable routine to handle master interrupts. - * note This function does not need to be called unless you are reimplementing the - * nonblocking API's interrupt handler routines to add special functionality. - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - */ -void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle) -{ - bool isDone; - status_t result; - - /* Don't do anything if we don't have a valid handle. */ - if (NULL == handle) - { - return; - } - - result = I2C_RunTransferStateMachine(base, handle, &isDone); - - if ((result != kStatus_Success) || isDone) - { - /* Restore handle to idle state. */ - handle->state = (uint8_t)kIdleState; - - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - - /* Invoke callback. */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } -} - -static void I2C_SlaveInternalStateMachineReset(I2C_Type *base) -{ - I2C_SlaveEnable(base, false); /* clear SLVEN Slave enable bit */ -} - -static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal) -{ - uint32_t dataSetupTime_ns; - - switch ((uint8_t)(busSpeed)) - { - case (uint8_t)kI2C_SlaveStandardMode: - dataSetupTime_ns = 250U; - break; - - case (uint8_t)kI2C_SlaveFastMode: - dataSetupTime_ns = 100U; - break; - - case (uint8_t)kI2C_SlaveFastModePlus: - dataSetupTime_ns = 50U; - break; - - case (uint8_t)kI2C_SlaveHsMode: - dataSetupTime_ns = 10U; - break; - - default: - dataSetupTime_ns = 0U; - break; - } - - if (0U == dataSetupTime_ns) - { - return kStatus_InvalidArgument; - } - - /* divVal = (sourceClock_Hz / 1000000) * (dataSetupTime_ns / 1000) */ - *divVal = srcClock_Hz / 1000U; - *divVal = (*divVal) * dataSetupTime_ns; - *divVal = (*divVal) / 1000000U; - - if ((*divVal) > I2C_CLKDIV_DIVVAL_MASK) - { - *divVal = I2C_CLKDIV_DIVVAL_MASK; - } - - return kStatus_Success; -} - -static uint32_t I2C_SlavePollPending(I2C_Type *base) -{ - uint32_t stat; - -#if I2C_RETRY_TIMES != 0U - uint32_t waitTimes = I2C_RETRY_TIMES; -#endif - do - { - stat = base->STAT; -#if I2C_RETRY_TIMES != 0U - waitTimes--; - } while ((0U == (stat & I2C_STAT_SLVPENDING_MASK)) && (waitTimes != 0U)); - - if (waitTimes == 0U) - { - return (uint32_t)kStatus_I2C_Timeout; - } -#else - } while (0U == (stat & I2C_STAT_SLVPENDING_MASK)); -#endif - - return stat; -} - -static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event) -{ - uint32_t eventMask = handle->transfer.eventMask; - handle->transfer.event = event; - if (((handle->callback) != NULL) && ((eventMask & (uint32_t)event) != 0U)) - { - handle->callback(base, &handle->transfer, handle->userData); - - size_t txSize = handle->transfer.txSize; - size_t rxSize = handle->transfer.rxSize; - /* if after event callback we have data buffer (callback func has added new data), keep transfer busy */ - if (false == handle->isBusy) - { - if (((handle->transfer.txData != NULL) && (txSize != 0U)) || - ((handle->transfer.rxData != NULL) && (rxSize != 0U))) - { - handle->isBusy = true; - } - } - - /* Clear the transferred count now that we have a new buffer. */ - if ((event == kI2C_SlaveReceiveEvent) || (event == kI2C_SlaveTransmitEvent)) - { - handle->transfer.transferredCount = 0; - } - } -} - -static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle) -{ - uint8_t addressByte0; - size_t txSize; - size_t rxSize; - - addressByte0 = (uint8_t)base->SLVDAT; - - /* store the matched address */ - handle->transfer.receivedAddress = addressByte0; - - /* R/nW */ - if ((addressByte0 & 1U) != 0U) - { - txSize = handle->transfer.txSize; - /* if we have no data in this transfer, call callback to get new */ - if ((handle->transfer.txData == NULL) || (txSize == 0U)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); - } - - txSize = handle->transfer.txSize; - /* NACK if we have no data in this transfer. */ - if ((handle->transfer.txData == NULL) || (txSize == 0U)) - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - return false; - } - - /* master wants to read, so slave transmit is next state */ - handle->slaveFsm = kI2C_SlaveFsmTransmit; - } - else - { - rxSize = handle->transfer.rxSize; - /* if we have no receive buffer in this transfer, call callback to get new */ - if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); - } - - rxSize = handle->transfer.rxSize; - /* NACK if we have no data in this transfer */ - if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - return false; - } - - /* master wants write, so slave receive is next state */ - handle->slaveFsm = kI2C_SlaveFsmReceive; - } - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - return true; -} - -static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, - i2c_slave_handle_t *handle, - const void *txData, - size_t txSize, - void *rxData, - size_t rxSize, - uint32_t eventMask) -{ - assert(handle != NULL); - - status_t status; - status = kStatus_Success; - - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); - - /* Return busy if another transaction is in progress. */ - if (handle->isBusy) - { - status = kStatus_I2C_Busy; - } - - /* Save transfer into handle. */ - handle->transfer.txData = (const uint8_t *)txData; - handle->transfer.txSize = txSize; - handle->transfer.rxData = (uint8_t *)rxData; - handle->transfer.rxSize = rxSize; - handle->transfer.transferredCount = 0; - handle->transfer.eventMask = eventMask | (uint32_t)kI2C_SlaveTransmitEvent | (uint32_t)kI2C_SlaveReceiveEvent; - handle->isBusy = true; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* Clear w1c flags. */ - base->STAT |= 0u; - - /* Enable I2C internal IRQ sources. */ - I2C_EnableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); - - return status; -} - -/*! - * brief Starts accepting master read from slave requests. - * - * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * param base The I2C peripheral base address. - * param transfer Pointer to #i2c_slave_transfer_t structure. - * param txData Pointer to data to send to master. - * param txSize Size of txData in bytes. - * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * retval kStatus_Success Slave transfers were successfully started. - * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetSendBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, txData, txSize, NULL, 0u, eventMask); -} - -/*! - * brief Starts accepting master write to slave requests. - * - * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * param base The I2C peripheral base address. - * param transfer Pointer to #i2c_slave_transfer_t structure. - * param rxData Pointer to data to store data from master. - * param rxSize Size of rxData in bytes. - * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * retval kStatus_Success Slave transfers were successfully started. - * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetReceiveBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, NULL, 0u, rxData, rxSize, eventMask); -} - -/*! - * brief Configures Slave Address n register. - * - * This function writes new value to Slave Address register. - * - * param base The I2C peripheral base address. - * param addressRegister The module supports multiple address registers. The parameter determines which one shall be - * changed. - * param address The slave address to be stored to the address register for matching. - * param addressDisable Disable matching of the specified address register. - */ -void I2C_SlaveSetAddress(I2C_Type *base, - i2c_slave_address_register_t addressRegister, - uint8_t address, - bool addressDisable) -{ - base->SLVADR[addressRegister] = I2C_SLVADR_SLVADR(address) | I2C_SLVADR_SADISABLE(addressDisable); -} - -/*! - * brief Provides a default configuration for the I2C slave peripheral. - * - * This function provides the following default configuration for the I2C slave peripheral: - * code - * slaveConfig->enableSlave = true; - * slaveConfig->address0.disable = false; - * slaveConfig->address0.address = 0u; - * slaveConfig->address1.disable = true; - * slaveConfig->address2.disable = true; - * slaveConfig->address3.disable = true; - * slaveConfig->busSpeed = kI2C_SlaveStandardMode; - * endcode - * - * After calling this function, override any settings to customize the configuration, - * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the a - * address0.address member of the configuration structure with the desired slave address. - * - * param[out] slaveConfig User provided configuration structure that is set to default values. Refer to - * #i2c_slave_config_t. - */ -void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) -{ - assert(slaveConfig != NULL); - - i2c_slave_config_t mySlaveConfig = {0}; - - /* default config enables slave address 0 match to general I2C call address zero */ - mySlaveConfig.enableSlave = true; - mySlaveConfig.address1.addressDisable = true; - mySlaveConfig.address2.addressDisable = true; - mySlaveConfig.address3.addressDisable = true; - - *slaveConfig = mySlaveConfig; -} - -/*! - * brief Initializes the I2C slave peripheral. - * - * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user - * provided configuration. - * - * param base The I2C peripheral base address. - * param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults - * that you can override. - * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide - * enough - * data setup time for master when slave stretches the clock. - */ -status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz) -{ - status_t status; - uint32_t divVal = 0; - - /* configure data setup time used when slave stretches clock */ - status = I2C_SlaveDivVal(srcClock_Hz, slaveConfig->busSpeed, &divVal); - if (kStatus_Success != status) - { - return status; - } - - (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); - - /* I2C Clock Divider register */ - base->CLKDIV = divVal; - - /* set Slave address */ - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister0, slaveConfig->address0.address, - slaveConfig->address0.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister1, slaveConfig->address1.address, - slaveConfig->address1.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister2, slaveConfig->address2.address, - slaveConfig->address2.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister3, slaveConfig->address3.address, - slaveConfig->address3.addressDisable); - - /* set Slave address 0 qual */ - base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(slaveConfig->qualMode) | I2C_SLVQUAL0_SLVQUAL0(slaveConfig->qualAddress); - - /* set Slave enable */ - base->CFG = I2C_CFG_SLVEN(slaveConfig->enableSlave); - - return status; -} - -/*! - * brief Deinitializes the I2C slave peripheral. - * - * This function disables the I2C slave peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * param base The I2C peripheral base address. - */ -void I2C_SlaveDeinit(I2C_Type *base) -{ - I2C_SlaveEnable(base, false); -} - -/*! - * brief Performs a polling send transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * param base The I2C peripheral base address. - * param txBuff The pointer to the data to be transferred. - * param txSize The length in bytes of the data to be transferred. - * return kStatus_Success Data has been sent. - * return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). - */ -status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) -{ - const uint8_t *buf = txBuff; - uint32_t stat; - bool slaveAddress; - bool slaveTransmit; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - - /* Get slave machine state */ - slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); - slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_TX); - - /* in I2C_SlaveSend() it shall be either slaveAddress or slaveTransmit */ - if (!(slaveAddress || slaveTransmit)) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - if (slaveAddress) - { - /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - - /* send bytes up to txSize */ - while (txSize != 0U) - { - slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_TX); - - if (!slaveTransmit) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - /* Write 8 bits of data to the SLVDAT register */ - base->SLVDAT = I2C_SLVDAT_DATA(*buf); - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* advance counters and pointers for next data */ - buf++; - txSize--; - - if (txSize != 0U) - { - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - } - - return kStatus_Success; -} - -/*! - * brief Performs a polling receive transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * param base The I2C peripheral base address. - * param rxBuff The pointer to the data to be transferred. - * param rxSize The length in bytes of the data to be transferred. - * return kStatus_Success Data has been received. - * return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). - */ -status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) -{ - uint8_t *buf = rxBuff; - uint32_t stat; - bool slaveAddress; - bool slaveReceive; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - - /* Get slave machine state */ - slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); - slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_RX); - - /* in I2C_SlaveReceive() it shall be either slaveAddress or slaveReceive */ - if (!(slaveAddress || slaveReceive)) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - if (slaveAddress) - { - /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - - /* receive bytes up to rxSize */ - while (rxSize != 0U) - { - slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_RX); - - if (!slaveReceive) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - /* Read 8 bits of data from the SLVDAT register */ - *buf = (uint8_t)base->SLVDAT; - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* advance counters and pointers for next data */ - buf++; - rxSize--; - - if (rxSize != 0U) - { - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - } - - return kStatus_Success; -} - -/*! - * brief Creates a new handle for the I2C slave non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. - * - * param base The I2C peripheral base address. - * param[out] handle Pointer to the I2C slave driver handle. - * param callback User provided pointer to the asynchronous callback function. - * param userData User provided pointer to the application callback data. - */ -void I2C_SlaveTransferCreateHandle(I2C_Type *base, - i2c_slave_handle_t *handle, - i2c_slave_transfer_callback_t callback, - void *userData) -{ - assert(handle != NULL); - - uint32_t instance; - i2c_to_flexcomm_t handler; - handler.i2c_slave_handler = I2C_SlaveTransferHandleIRQ; - - /* Clear out the handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Save base and instance. */ - handle->callback = callback; - handle->userData = userData; - - /* initialize fsm */ - handle->slaveFsm = kI2C_SlaveFsmAddressMatch; - - /* store pointer to handle into transfer struct */ - handle->transfer.handle = handle; - - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); - (void)EnableIRQ(s_i2cIRQ[instance]); -} - -/*! - * brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. - * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. - * - * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * param base The I2C peripheral base address. - * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * retval kStatus_Success Slave transfers were successfully started. - * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, handle, NULL, 0u, NULL, 0u, eventMask); -} - -/*! - * brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. - * - * param base I2C base pointer. - * param handle pointer to i2c_slave_handle_t structure. - * param count Number of bytes transferred so far by the non-blocking transaction. - * retval kStatus_InvalidArgument count is Invalid. - * retval kStatus_Success Successfully return the count. - */ -status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (!handle->isBusy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* For an active transfer, just return the count from the handle. */ - *count = handle->transfer.transferredCount; - - return kStatus_Success; -} - -/*! - * brief Aborts the slave non-blocking transfers. - * note This API could be called at any time to stop slave for handling the bus events. - * param base The I2C peripheral base address. - * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * retval kStatus_Success - * retval #kStatus_I2C_Idle - */ -void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) -{ - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); - - /* Set the SLVEN bit to 0 in the CFG register. */ - I2C_SlaveEnable(base, false); - - handle->isBusy = false; - handle->transfer.txSize = 0U; - handle->transfer.rxSize = 0U; -} - -/*! - * brief Reusable routine to handle slave interrupts. - * note This function does not need to be called unless you are reimplementing the - * non blocking API's interrupt handler routines to add special functionality. - * param base The I2C peripheral base address. - * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - */ -void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle) -{ - uint32_t i2cStatus = base->STAT; - uint8_t tmpdata; - size_t txSize; - size_t rxSize; - - if ((i2cStatus & I2C_STAT_SLVDESEL_MASK) != 0U) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveDeselectedEvent); - I2C_SlaveClearStatusFlags(base, I2C_STAT_SLVDESEL_MASK); - } - - /* SLVPENDING flag is cleared by writing I2C_SLVCTL_SLVCONTINUE_MASK to SLVCTL register */ - if ((i2cStatus & I2C_STAT_SLVPENDING_MASK) != 0U) - { - bool slaveAddress = - (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); - - if (slaveAddress) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveAddressMatchEvent); - (void)I2C_SlaveAddressIRQ(base, handle); - } - else - { - switch (handle->slaveFsm) - { - case kI2C_SlaveFsmReceive: - { - bool slaveReceive = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == - (uint32_t)I2C_STAT_SLVST_RX); - - if (slaveReceive) - { - rxSize = handle->transfer.rxSize; - /* if we have no receive buffer in this transfer, call callback to get new */ - if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); - } - - rxSize = handle->transfer.rxSize; - /* receive a byte */ - if ((handle->transfer.rxData != NULL) && (rxSize != 0U)) - { - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - tmpdata = (uint8_t)base->SLVDAT; - *(handle->transfer.rxData) = tmpdata; - (handle->transfer.rxSize)--; - (handle->transfer.rxData)++; - (handle->transfer.transferredCount)++; - } - - rxSize = handle->transfer.rxSize; - txSize = handle->transfer.txSize; - /* is this last transaction for this transfer? allow next transaction */ - if ((0U == rxSize) && (0U == txSize)) - { - handle->isBusy = false; - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); - } - } - else - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - } - } - break; - - case kI2C_SlaveFsmTransmit: - { - bool slaveTransmit = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == - (uint32_t)I2C_STAT_SLVST_TX); - - if (slaveTransmit) - { - txSize = handle->transfer.txSize; - /* if we have no data in this transfer, call callback to get new */ - if ((handle->transfer.txData == NULL) || (txSize == 0U)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); - } - - txSize = handle->transfer.txSize; - /* transmit a byte */ - if ((handle->transfer.txData != NULL) && (txSize != 0U)) - { - base->SLVDAT = *(handle->transfer.txData); - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - (handle->transfer.txSize)--; - (handle->transfer.txData)++; - (handle->transfer.transferredCount)++; - } - - rxSize = handle->transfer.rxSize; - txSize = handle->transfer.txSize; - /* is this last transaction for this transfer? allow next transaction */ - if ((0U == rxSize) && (0U == txSize)) - { - handle->isBusy = false; - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); - } - } - else - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - } - } - break; - - default: - /* incorrect state, slv_abort()? */ - break; - } - } - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c.h deleted file mode 100644 index b521a1ad756..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c.h +++ /dev/null @@ -1,1148 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2C_H_ -#define _FSL_I2C_H_ - -#include -#include "fsl_device_registers.h" -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define I2C_CFG_MASK 0x1f - -/*! - * @addtogroup i2c_driver - * @{ - */ - -/*! @file */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2C driver version. */ -#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) -/*@}*/ - -/*! @brief Retry times for waiting flag. */ -#ifndef I2C_RETRY_TIMES -#define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ -#endif - -/*! @brief Whether to ignore the nack signal of the last byte during master transmit. */ -#ifndef I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK -#define I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK \ - 1U /* Define to one means master ignores the last byte's nack and considers the transfer successful. */ -#endif - -/* definitions for MSTCODE bits in I2C Status register STAT */ -#define I2C_STAT_MSTCODE_IDLE (0U) /*!< Master Idle State Code */ -#define I2C_STAT_MSTCODE_RXREADY (1U) /*!< Master Receive Ready State Code */ -#define I2C_STAT_MSTCODE_TXREADY (2U) /*!< Master Transmit Ready State Code */ -#define I2C_STAT_MSTCODE_NACKADR (3U) /*!< Master NACK by slave on address State Code */ -#define I2C_STAT_MSTCODE_NACKDAT (4U) /*!< Master NACK by slave on data State Code */ - -/* definitions for SLVSTATE bits in I2C Status register STAT */ -#define I2C_STAT_SLVST_ADDR (0) -#define I2C_STAT_SLVST_RX (1) -#define I2C_STAT_SLVST_TX (2) - -/*! @brief I2C status return codes. */ -enum -{ - kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 0), /*!< The master is already performing a transfer. */ - kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 1), /*!< The slave driver is idle. */ - kStatus_I2C_Nak = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 2), /*!< The slave device sent a NAK in response to a byte. */ - kStatus_I2C_InvalidParameter = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 3), /*!< Unable to proceed due to invalid parameter. */ - kStatus_I2C_BitError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 4), /*!< Transferred bit was not seen on the bus. */ - kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 5), /*!< Arbitration lost error. */ - kStatus_I2C_NoTransferInProgress = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 6), /*!< Attempt to abort a transfer when one is not in progress. */ - kStatus_I2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */ - kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8), /*!< Start and stop error. */ - kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9), /*!< Unexpected state. */ - kStatus_I2C_Timeout = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, - 10), /*!< Timeout when waiting for I2C master/slave pending status to set to continue transfer. */ - kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 11), /*!< NAK received for Address */ - kStatus_I2C_EventTimeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 12), /*!< Timeout waiting for bus event. */ - kStatus_I2C_SclLowTimeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 13), /*!< Timeout SCL signal remains low. */ -}; - -/*! @} */ - -/*! - * @addtogroup i2c_driver - * @{ - */ - -/*! - * @brief I2C status flags. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -enum _i2c_status_flags -{ - kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. bit 0 */ - kI2C_MasterArbitrationLostFlag = - I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus. bit 4*/ - kI2C_MasterStartStopErrorFlag = - I2C_STAT_MSTSTSTPERR_MASK, /*!< There was an error during start or stop phase of the transaction. bit 6 */ - kI2C_MasterIdleFlag = 1UL << 5U, /*!< The I2C master idle status. bit 5 */ - kI2C_MasterRxReadyFlag = 1UL << I2C_STAT_MSTSTATE_SHIFT, /*!< The I2C master rx ready status. bit 1 */ - kI2C_MasterTxReadyFlag = 1UL << (I2C_STAT_MSTSTATE_SHIFT + 1U), /*!< The I2C master tx ready status. bit 2 */ - kI2C_MasterAddrNackFlag = 1UL << 7U, /*!< The I2C master address nack status. bit 7 */ - kI2C_MasterDataNackFlag = 1UL << (I2C_STAT_MSTSTATE_SHIFT + 2U), /*!< The I2C master data nack status. bit 3 */ - kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. bit 8 */ - kI2C_SlaveNotStretching = I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 - = yes, 1 = no). bit 11 */ - kI2C_SlaveSelected = - I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. bit 14 */ - kI2C_SaveDeselected = I2C_STAT_SLVDESEL_MASK, /*!< Indicates that slave was previously deselected (deselect event - took place, w1c). bit 15 */ - kI2C_SlaveAddressedFlag = 1UL << 22U, /*!< One of the I2C slave's 4 addresses is matched. bit 22 */ - kI2C_SlaveReceiveFlag = 1UL << I2C_STAT_SLVSTATE_SHIFT, /*!< Slave receive data available. bit 9 */ - kI2C_SlaveTransmitFlag = 1UL << (I2C_STAT_SLVSTATE_SHIFT + 1U), /*!< Slave data can be transmitted. bit 10 */ - kI2C_SlaveAddress0MatchFlag = 1UL << 20U, /*!< Slave address0 match. bit 20 */ - kI2C_SlaveAddress1MatchFlag = 1UL << I2C_STAT_SLVIDX_SHIFT, /*!< Slave address1 match. bit 12 */ - kI2C_SlaveAddress2MatchFlag = 1UL << (I2C_STAT_SLVIDX_SHIFT + 1U), /*!< Slave address2 match. bit 13 */ - kI2C_SlaveAddress3MatchFlag = 1UL << 21U, /*!< Slave address3 match. bit 21 */ - kI2C_MonitorReadyFlag = I2C_STAT_MONRDY_MASK, /*!< The I2C monitor ready interrupt. bit 16 */ - kI2C_MonitorOverflowFlag = I2C_STAT_MONOV_MASK, /*!< The monitor data overrun interrupt. bit 17 */ - kI2C_MonitorActiveFlag = I2C_STAT_MONACTIVE_MASK, /*!< The monitor is active. bit 18 */ - kI2C_MonitorIdleFlag = I2C_STAT_MONIDLE_MASK, /*!< The monitor idle interrupt. bit 19 */ - kI2C_EventTimeoutFlag = I2C_STAT_EVENTTIMEOUT_MASK, /*!< The bus event timeout interrupt. bit 24 */ - kI2C_SclTimeoutFlag = I2C_STAT_SCLTIMEOUT_MASK, /*!< The SCL timeout interrupt. bit 25 */ - - /* All master flags that can be cleared by software */ - kI2C_MasterAllClearFlags = kI2C_MasterArbitrationLostFlag | kI2C_MasterStartStopErrorFlag, - /* All slave flags that can be cleared by software */ - kI2C_SlaveAllClearFlags = kI2C_SaveDeselected, - /* All common flags that can be cleared by software */ - kI2C_CommonAllClearFlags = - kI2C_MonitorOverflowFlag | kI2C_MonitorIdleFlag | kI2C_EventTimeoutFlag | kI2C_SclTimeoutFlag, -}; - -/*! - * @brief I2C interrupt enable. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -enum _i2c_interrupt_enable -{ - kI2C_MasterPendingInterruptEnable = - I2C_STAT_MSTPENDING_MASK, /*!< The I2C master communication pending interrupt. */ - kI2C_MasterArbitrationLostInterruptEnable = - I2C_STAT_MSTARBLOSS_MASK, /*!< The I2C master arbitration lost interrupt. */ - kI2C_MasterStartStopErrorInterruptEnable = - I2C_STAT_MSTSTSTPERR_MASK, /*!< The I2C master start/stop timing error interrupt. */ - kI2C_SlavePendingInterruptEnable = I2C_STAT_SLVPENDING_MASK, /*!< The I2C slave communication pending interrupt. */ - kI2C_SlaveNotStretchingInterruptEnable = - I2C_STAT_SLVNOTSTR_MASK, /*!< The I2C slave not streching interrupt, deep-sleep mode can be entered only when - this interrupt occurs. */ - kI2C_SlaveDeselectedInterruptEnable = I2C_STAT_SLVDESEL_MASK, /*!< The I2C slave deselection interrupt. */ - kI2C_MonitorReadyInterruptEnable = I2C_STAT_MONRDY_MASK, /*!< The I2C monitor ready interrupt. */ - kI2C_MonitorOverflowInterruptEnable = I2C_STAT_MONOV_MASK, /*!< The monitor data overrun interrupt. */ - kI2C_MonitorIdleInterruptEnable = I2C_STAT_MONIDLE_MASK, /*!< The monitor idle interrupt. */ - kI2C_EventTimeoutInterruptEnable = I2C_STAT_EVENTTIMEOUT_MASK, /*!< The bus event timeout interrupt. */ - kI2C_SclTimeoutInterruptEnable = I2C_STAT_SCLTIMEOUT_MASK, /*!< The SCL timeout interrupt. */ - - /* All master interrupt sources */ - kI2C_MasterAllInterruptEnable = kI2C_MasterPendingInterruptEnable | kI2C_MasterArbitrationLostInterruptEnable | - kI2C_MasterStartStopErrorInterruptEnable, - /* All slave interrupt sources */ - kI2C_SlaveAllInterruptEnable = - kI2C_SlavePendingInterruptEnable | kI2C_SlaveNotStretchingInterruptEnable | kI2C_SlaveDeselectedInterruptEnable, - /* All common interrupt sources */ - kI2C_CommonAllInterruptEnable = kI2C_MonitorReadyInterruptEnable | kI2C_MonitorOverflowInterruptEnable | - kI2C_MonitorIdleInterruptEnable | kI2C_EventTimeoutInterruptEnable | - kI2C_SclTimeoutInterruptEnable, -}; -/*! @} */ - -/*! - * @addtogroup i2c_master_driver - * @{ - */ - -/*! @brief Direction of master and slave transfers. */ -typedef enum _i2c_direction -{ - kI2C_Write = 0U, /*!< Master transmit. */ - kI2C_Read = 1U /*!< Master receive. */ -} i2c_direction_t; - -/*! - * @brief Structure with settings to initialize the I2C master module. - * - * This structure holds configuration settings for the I2C peripheral. To initialize this - * structure to reasonable defaults, call the I2C_MasterGetDefaultConfig() function and - * pass a pointer to your configuration structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _i2c_master_config -{ - bool enableMaster; /*!< Whether to enable master mode. */ - uint32_t baudRate_Bps; /*!< Desired baud rate in bits per second. */ - bool enableTimeout; /*!< Enable internal timeout function. */ - uint8_t timeout_Ms; /*!< Event timeout and SCL low timeout value. */ -} i2c_master_config_t; - -/* Forward declaration of the transfer descriptor and handle typedefs. */ -/*! @brief I2C master transfer typedef */ -typedef struct _i2c_master_transfer i2c_master_transfer_t; - -/*! @brief I2C master handle typedef */ -typedef struct _i2c_master_handle i2c_master_handle_t; - -/*! - * @brief Master completion callback function pointer type. - * - * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use - * in the call to I2C_MasterTransferCreateHandle(). - * - * @param base The I2C peripheral base address. - * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, - i2c_master_handle_t *handle, - status_t completionStatus, - void *userData); - -/*! - * @brief Transfer option flags. - * - * @note These enumerations are intended to be OR'd together to form a bit mask of options for - * the #_i2c_master_transfer::flags field. - */ -enum _i2c_master_transfer_flags -{ - kI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ - kI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ - kI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ - kI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ -}; - -/*! @brief States for the state machine used by transactional APIs. */ -enum _i2c_transfer_states -{ - kIdleState = 0, - kTransmitSubaddrState, - kTransmitDataState, - kReceiveDataBeginState, - kReceiveDataState, - kReceiveLastDataState, - kStartState, - kStopState, - kWaitForCompletionState -}; - -/*! - * @brief Non-blocking transfer descriptor structure. - * - * This structure is used to pass transaction parameters to the I2C_MasterTransferNonBlocking() API. - */ -struct _i2c_master_transfer -{ - uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i2c_master_transfer_flags for available - options. Set to 0 or #kI2C_TransferDefaultFlag for normal transfers. */ - uint8_t slaveAddress; /*!< The 7-bit slave address. */ - i2c_direction_t direction; /*!< Either #kI2C_Read or #kI2C_Write. */ - uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ - size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ - void *data; /*!< Pointer to data to transfer. */ - size_t dataSize; /*!< Number of bytes to transfer. */ -}; - -/*! - * @brief Driver handle for master non-blocking APIs. - * @note The contents of this structure are private and subject to change. - */ -struct _i2c_master_handle -{ - uint8_t state; /*!< Transfer state machine current state. */ - uint32_t transferCount; /*!< Indicates progress of the transfer */ - uint32_t remainingBytes; /*!< Remaining byte count in current state. */ - uint8_t *buf; /*!< Buffer pointer for current state. */ - uint32_t remainingSubaddr; - uint8_t subaddrBuf[4]; - bool checkAddrNack; /*!< Whether to check the nack signal is detected during addressing. */ - i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ - i2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ - void *userData; /*!< Application data passed to callback. */ -}; - -/*! @} */ - -/*! - * @addtogroup i2c_slave_driver - * @{ - */ -/*! @brief I2C slave address register. */ -typedef enum _i2c_slave_address_register -{ - kI2C_SlaveAddressRegister0 = 0U, /*!< Slave Address 0 register. */ - kI2C_SlaveAddressRegister1 = 1U, /*!< Slave Address 1 register. */ - kI2C_SlaveAddressRegister2 = 2U, /*!< Slave Address 2 register. */ - kI2C_SlaveAddressRegister3 = 3U, /*!< Slave Address 3 register. */ -} i2c_slave_address_register_t; - -/*! @brief Data structure with 7-bit Slave address and Slave address disable. */ -typedef struct _i2c_slave_address -{ - uint8_t address; /*!< 7-bit Slave address SLVADR. */ - bool addressDisable; /*!< Slave address disable SADISABLE. */ -} i2c_slave_address_t; - -/*! @brief I2C slave address match options. */ -typedef enum _i2c_slave_address_qual_mode -{ - kI2C_QualModeMask = 0U, /*!< The SLVQUAL0 field (qualAddress) is used as a logical mask for matching address0. */ - kI2C_QualModeExtend = - 1U, /*!< The SLVQUAL0 (qualAddress) field is used to extend address 0 matching in a range of addresses. */ -} i2c_slave_address_qual_mode_t; - -/*! @brief I2C slave bus speed options. */ -typedef enum _i2c_slave_bus_speed -{ - kI2C_SlaveStandardMode = 0U, - kI2C_SlaveFastMode = 1U, - kI2C_SlaveFastModePlus = 2U, - kI2C_SlaveHsMode = 3U, -} i2c_slave_bus_speed_t; - -/*! - * @brief Structure with settings to initialize the I2C slave module. - * - * This structure holds configuration settings for the I2C slave peripheral. To initialize this - * structure to reasonable defaults, call the I2C_SlaveGetDefaultConfig() function and - * pass a pointer to your configuration structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _i2c_slave_config -{ - i2c_slave_address_t address0; /*!< Slave's 7-bit address and disable. */ - i2c_slave_address_t address1; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_t address2; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_t address3; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_qual_mode_t qualMode; /*!< Qualify mode for slave address 0. */ - uint8_t qualAddress; /*!< Slave address qualifier for address 0. */ - i2c_slave_bus_speed_t - busSpeed; /*!< Slave bus speed mode. If the slave function stretches SCL to allow for software response, it must - provide sufficient data setup time to the master before releasing the stretched clock. - This is accomplished by inserting one clock time of CLKDIV at that point. - The #busSpeed value is used to configure CLKDIV - such that one clock time is greater than the tSU;DAT value noted - in the I2C bus specification for the I2C mode that is being used. - If the #busSpeed mode is unknown at compile time, use the longest data setup time - kI2C_SlaveStandardMode (250 ns) */ - bool enableSlave; /*!< Enable slave mode. */ -} i2c_slave_config_t; - -/*! - * @brief Set of events sent to the callback for non blocking slave transfers. - * - * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together - * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable. - * Then, when the slave callback is invoked, it is passed the current event through its @a transfer - * parameter. - * - * @note These enumerations are meant to be OR'd together to form a bit mask of events. - */ -typedef enum _i2c_slave_transfer_event -{ - kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ - kI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit - (slave-transmitter role). */ - kI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received - data (slave-receiver role). */ - kI2C_SlaveCompletionEvent = 0x20U, /*!< All data in the active transfer have been consumed. */ - kI2C_SlaveDeselectedEvent = - 0x40U, /*!< The slave function has become deselected (SLVSEL flag changing from 1 to 0. */ - - /*! Bit mask of all available events. */ - kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | - kI2C_SlaveCompletionEvent | kI2C_SlaveDeselectedEvent, -} i2c_slave_transfer_event_t; - -/*! @brief I2C slave handle typedef. */ -typedef struct _i2c_slave_handle i2c_slave_handle_t; - -/*! @brief I2C slave transfer structure */ -typedef struct _i2c_slave_transfer -{ - i2c_slave_handle_t *handle; /*!< Pointer to handle that contains this transfer. */ - i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ - uint8_t receivedAddress; /*!< Matching address send by master. 7-bits plus R/nW bit0 */ - uint32_t eventMask; /*!< Mask of enabled events. */ - uint8_t *rxData; /*!< Transfer buffer for receive data */ - const uint8_t *txData; /*!< Transfer buffer for transmit data */ - size_t txSize; /*!< Transfer size */ - size_t rxSize; /*!< Transfer size */ - size_t transferredCount; /*!< Number of bytes transferred during this transfer. */ - status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for - #kI2C_SlaveCompletionEvent. */ -} i2c_slave_transfer_t; - -/*! - * @brief Slave event callback function pointer type. - * - * This callback is used only for the slave non-blocking transfer API. To install a callback, - * use the I2C_SlaveSetCallback() function after you have created a handle. - * - * @param base Base address for the I2C instance on which the event occurred. - * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *userData); - -/*! - * @brief I2C slave software finite state machine states. - */ -typedef enum _i2c_slave_fsm -{ - kI2C_SlaveFsmAddressMatch = 0u, - kI2C_SlaveFsmReceive = 2u, - kI2C_SlaveFsmTransmit = 3u, -} i2c_slave_fsm_t; - -/*! - * @brief I2C slave handle structure. - * @note The contents of this structure are private and subject to change. - */ -struct _i2c_slave_handle -{ - volatile i2c_slave_transfer_t transfer; /*!< I2C slave transfer. */ - volatile bool isBusy; /*!< Whether transfer is busy. */ - volatile i2c_slave_fsm_t slaveFsm; /*!< slave transfer state machine. */ - i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ - void *userData; /*!< Callback parameter passed to callback. */ -}; - -/*! @brief Typedef for master interrupt handler. */ -typedef void (*flexcomm_i2c_master_irq_handler_t)(I2C_Type *base, i2c_master_handle_t *handle); - -/*! @brief Typedef for slave interrupt handler. */ -typedef void (*flexcomm_i2c_slave_irq_handler_t)(I2C_Type *base, i2c_slave_handle_t *handle); -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup i2c_master_driver - * @{ - */ - -/*! @name Initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the I2C master peripheral. - * - * This function provides the following default configuration for the I2C master peripheral: - * @code - * masterConfig->enableMaster = true; - * masterConfig->baudRate_Bps = 100000U; - * masterConfig->enableTimeout = false; - * @endcode - * - * After calling this function, you can override any settings in order to customize the configuration, - * prior to initializing the master driver with I2C_MasterInit(). - * - * @param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. - */ -void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); - -/*! - * @brief Initializes the I2C master peripheral. - * - * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user - * provided configuration. A software reset is performed prior to configuration. - * - * @param base The I2C peripheral base address. - * @param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of - * defaults - * that you can override. - * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, - * filter widths, and timeout periods. - */ -void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes the I2C master peripheral. - * - * This function disables the I2C master peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -void I2C_MasterDeinit(I2C_Type *base); - -/*! - * @brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * @param base The I2C peripheral base address. - * @return I2C instance number starting from 0. - */ -uint32_t I2C_GetInstance(I2C_Type *base); - -/*! - * @brief Performs a software reset. - * - * Restores the I2C master peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -static inline void I2C_MasterReset(I2C_Type *base) -{ -} - -/*! - * @brief Enables or disables the I2C module as master. - * - * @param base The I2C peripheral base address. - * @param enable Pass true to enable or false to disable the specified I2C as master. - */ -static inline void I2C_MasterEnable(I2C_Type *base, bool enable) -{ - if (enable) - { - base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK; - } - else - { - base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK; - } -} - -/*@}*/ - -/*! @name Status */ -/*@{*/ -/*! - * @brief Gets the I2C status flags. - * - * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit - * in the return value is set if the flag is asserted. - * - * @param base The I2C peripheral base address. - * @return State of the status flags: - * - 1: related status flag is set. - * - 0: related status flag is not set. - * @see @ref _i2c_status_flags. - */ -uint32_t I2C_GetStatusFlags(I2C_Type *base); - -/*! - * @brief Clears the I2C status flag state. - * - * Refer to kI2C_CommonAllClearStatusFlags, kI2C_MasterAllClearStatusFlags and kI2C_SlaveAllClearStatusFlags to see - * the clearable flags. Attempts to clear other flags has no effect. - * - * @param base The I2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of the members in - * kI2C_CommonAllClearStatusFlags, kI2C_MasterAllClearStatusFlags and kI2C_SlaveAllClearStatusFlags. You may pass - * the result of a previous call to I2C_GetStatusFlags(). - * @see #_i2c_status_flags, _i2c_master_status_flags and _i2c_slave_status_flags. - */ -static inline void I2C_ClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - /* Only deal with the clearable flags */ - statusMask &= - ((uint32_t)kI2C_CommonAllClearFlags | (uint32_t)kI2C_MasterAllClearFlags | (uint32_t)kI2C_SlaveAllClearFlags); - base->STAT = statusMask; -} - -/*! - * @brief Clears the I2C master status flag state. - * @deprecated Do not use this function. It has been superceded by @ref I2C_ClearStatusFlags - * The following status register flags can be cleared: - * - #kI2C_MasterArbitrationLostFlag - * - #kI2C_MasterStartStopErrorFlag - * - * Attempts to clear other flags has no effect. - * - * @param base The I2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * #_i2c_status_flags enumerators OR'd together. You may pass the result of a previous call to - * I2C_GetStatusFlags(). - * @see _i2c_status_flags. - */ -static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - /* Allow clearing just master status flags */ - base->STAT = statusMask & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); -} - -/*@}*/ - -/*! @name Interrupts */ -/*@{*/ - -/*! - * @brief Enables the I2C interrupt requests. - * - * @param base The I2C peripheral base address. - * @param interruptMask Bit mask of interrupts to enable. See #_i2c_interrupt_enable for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2C_EnableInterrupts(I2C_Type *base, uint32_t interruptMask) -{ - base->INTENSET = interruptMask; -} - -/*! - * @brief Disables the I2C interrupt requests. - * - * @param base The I2C peripheral base address. - * @param interruptMask Bit mask of interrupts to disable. See #_i2c_interrupt_enable for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2C_DisableInterrupts(I2C_Type *base, uint32_t interruptMask) -{ - base->INTENCLR = interruptMask; -} - -/*! - * @brief Returns the set of currently enabled I2C interrupt requests. - * - * @param base The I2C peripheral base address. - * @return A bitmask composed of #_i2c_interrupt_enable enumerators OR'd together to indicate the - * set of enabled interrupts. - */ -static inline uint32_t I2C_GetEnabledInterrupts(I2C_Type *base) -{ - return base->INTSTAT; -} - -/*@}*/ - -/*! @name Bus operations */ -/*@{*/ - -/*! - * @brief Sets the I2C bus frequency for master transactions. - * - * The I2C master is automatically disabled and re-enabled as necessary to configure the baud - * rate. Do not call this function during a transfer, or the transfer is aborted. - * - * @param base The I2C peripheral base address. - * @param srcClock_Hz I2C functional clock frequency in Hertz. - * @param baudRate_Bps Requested bus frequency in bits per second. - */ -void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Sets the I2C bus timeout value. - * - * If the SCL signal remains low or bus does not have event longer than the timeout value, kI2C_SclTimeoutFlag or - * kI2C_EventTimeoutFlag is set. This can indicete the bus is held by slave or any fault occurs to the I2C module. - * - * @param base The I2C peripheral base address. - * @param timeout_Ms Timeout value in millisecond. - * @param srcClock_Hz I2C functional clock frequency in Hertz. - */ -void I2C_MasterSetTimeoutValue(I2C_Type *base, uint8_t timeout_Ms, uint32_t srcClock_Hz); - -/*! - * @brief Returns whether the bus is idle. - * - * Requires the master mode to be enabled. - * - * @param base The I2C peripheral base address. - * @retval true Bus is busy. - * @retval false Bus is idle. - */ -static inline bool I2C_MasterGetBusIdleState(I2C_Type *base) -{ - /* True if MSTPENDING flag is set and MSTSTATE is zero == idle */ - return ((base->STAT & (I2C_STAT_MSTPENDING_MASK | I2C_STAT_MSTSTATE_MASK)) == I2C_STAT_MSTPENDING_MASK); -} - -/*! - * @brief Sends a START on the I2C bus. - * - * This function is used to initiate a new master mode transfer by sending the START signal. - * The slave address is sent following the I2C START signal. - * - * @param base I2C peripheral base pointer - * @param address 7-bit slave device address. - * @param direction Master transfer directions(transmit/receive). - * @retval kStatus_Success Successfully send the start signal. - * @retval kStatus_I2C_Busy Current bus is busy. - */ -status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); - -/*! - * @brief Sends a STOP signal on the I2C bus. - * - * @retval kStatus_Success Successfully send the stop signal. - * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. - */ -status_t I2C_MasterStop(I2C_Type *base); - -/*! - * @brief Sends a REPEATED START on the I2C bus. - * - * @param base I2C peripheral base pointer - * @param address 7-bit slave device address. - * @param direction Master transfer directions(transmit/receive). - * @retval kStatus_Success Successfully send the start signal. - * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. - */ -static inline status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) -{ - return I2C_MasterStart(base, address, direction); -} - -/*! - * @brief Performs a polling send transfer on the I2C bus. - * - * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may - * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this - * function returns #kStatus_I2C_Nak. - * - * @param base The I2C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * @retval kStatus_Success Data was sent successfully. - * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags); - -/*! - * @brief Performs a polling receive transfer on the I2C bus. - * - * @param base The I2C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * @retval kStatus_Success Data was received successfully. - * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags); - -/*! - * @brief Performs a master polling transfer on the I2C bus. - * - * @note The API does not return until the transfer succeeds or fails due - * to arbitration lost or receiving a NAK. - * - * @param base I2C peripheral base address. - * @param xfer Pointer to the transfer structure. - * @retval kStatus_Success Successfully complete the data transmission. - * @retval kStatus_I2C_Busy Previous transmission still not finished. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - * @retval kStataus_I2C_Addr_Nak Transfer error, receive NAK during addressing. - */ -status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); - -/*@}*/ - -/*! @name Non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the I2C master non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. - * - * @param base The I2C peripheral base address. - * @param[out] handle Pointer to the I2C master driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void I2C_MasterTransferCreateHandle(I2C_Type *base, - i2c_master_handle_t *handle, - i2c_master_transfer_callback_t callback, - void *userData); - -/*! - * @brief Performs a non-blocking transaction on the I2C bus. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @param xfer The pointer to the transfer descriptor. - * @retval kStatus_Success The transaction was started successfully. - * @retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking - * transaction is already in progress. - */ -status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Returns number of bytes transferred so far. - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @param[out] count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_Success - * @retval #kStatus_I2C_Busy - */ -status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); - -/*! - * @brief Terminates a non-blocking I2C master transmission early. - * - * @note It is not safe to call this function from an IRQ handler that has a higher priority than the - * I2C peripheral's IRQ priority. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @retval kStatus_Success A transaction was successfully aborted. - * @retval #kStatus_I2C_Timeout Timeout during polling for flags. - */ -status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); - -/*@}*/ - -/*! @name IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle master interrupts. - * @note This function does not need to be called unless you are reimplementing the - * nonblocking API's interrupt handler routines to add special functionality. - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - */ -void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle); - -/*@}*/ - -/*! @} */ /* end of i2c_master_driver */ - -/*! - * @addtogroup i2c_slave_driver - * @{ - */ - -/*! @name Slave initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the I2C slave peripheral. - * - * This function provides the following default configuration for the I2C slave peripheral: - * @code - * slaveConfig->enableSlave = true; - * slaveConfig->address0.disable = false; - * slaveConfig->address0.address = 0u; - * slaveConfig->address1.disable = true; - * slaveConfig->address2.disable = true; - * slaveConfig->address3.disable = true; - * slaveConfig->busSpeed = kI2C_SlaveStandardMode; - * @endcode - * - * After calling this function, override any settings to customize the configuration, - * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the @a - * address0.address member of the configuration structure with the desired slave address. - * - * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to - * #i2c_slave_config_t. - */ -void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); - -/*! - * @brief Initializes the I2C slave peripheral. - * - * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user - * provided configuration. - * - * @param base The I2C peripheral base address. - * @param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults - * that you can override. - * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide - * enough - * data setup time for master when slave stretches the clock. - */ -status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz); - -/*! - * @brief Configures Slave Address n register. - * - * This function writes new value to Slave Address register. - * - * @param base The I2C peripheral base address. - * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be - * changed. - * @param address The slave address to be stored to the address register for matching. - * @param addressDisable Disable matching of the specified address register. - */ -void I2C_SlaveSetAddress(I2C_Type *base, - i2c_slave_address_register_t addressRegister, - uint8_t address, - bool addressDisable); - -/*! - * @brief Deinitializes the I2C slave peripheral. - * - * This function disables the I2C slave peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -void I2C_SlaveDeinit(I2C_Type *base); - -/*! - * @brief Enables or disables the I2C module as slave. - * - * @param base The I2C peripheral base address. - * @param enable True to enable or flase to disable. - */ -static inline void I2C_SlaveEnable(I2C_Type *base, bool enable) -{ - /* Set or clear the SLVEN bit in the CFG register. */ - base->CFG = I2C_CFG_SLVEN(enable); -} - -/*@}*/ /* end of Slave initialization and deinitialization */ - -/*! @name Slave status */ -/*@{*/ - -/*! - * @brief Clears the I2C status flag state. - * - * The following status register flags can be cleared: - * - slave deselected flag - * - * Attempts to clear other flags has no effect. - * - * @param base The I2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * _i2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to - * I2C_SlaveGetStatusFlags(). - * @see _i2c_slave_flags. - */ -static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - /* Allow clearing just slave status flags */ - base->STAT = statusMask & I2C_STAT_SLVDESEL_MASK; -} - -/*@}*/ /* end of Slave status */ - -/*! @name Slave bus operations */ -/*@{*/ - -/*! - * @brief Performs a polling send transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * @param base The I2C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @return kStatus_Success Data has been sent. - * @return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). - */ -status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); - -/*! - * @brief Performs a polling receive transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * @param base The I2C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @return kStatus_Success Data has been received. - * @return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). - */ -status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); - -/*@}*/ /* end of Slave bus operations */ - -/*! @name Slave non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the I2C slave non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. - * - * @param base The I2C peripheral base address. - * @param[out] handle Pointer to the I2C slave driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void I2C_SlaveTransferCreateHandle(I2C_Type *base, - i2c_slave_handle_t *handle, - i2c_slave_transfer_callback_t callback, - void *userData); - -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. - * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); - -/*! - * @brief Starts accepting master read from slave requests. - * - * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param transfer Pointer to #i2c_slave_transfer_t structure. - * @param txData Pointer to data to send to master. - * @param txSize Size of txData in bytes. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetSendBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask); - -/*! - * @brief Starts accepting master write to slave requests. - * - * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param transfer Pointer to #i2c_slave_transfer_t structure. - * @param rxData Pointer to data to store data from master. - * @param rxSize Size of rxData in bytes. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetReceiveBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask); - -/*! - * @brief Returns the slave address sent by the I2C master. - * - * This function should only be called from the address match event callback #kI2C_SlaveAddressMatchEvent. - * - * @param base The I2C peripheral base address. - * @param transfer The I2C slave transfer. - * @return The 8-bit address matched by the I2C slave. Bit 0 contains the R/w direction bit, and - * the 7-bit slave address is in the upper 7 bits. - */ -static inline uint32_t I2C_SlaveGetReceivedAddress(I2C_Type *base, volatile i2c_slave_transfer_t *transfer) -{ - return transfer->receivedAddress; -} - -/*! - * @brief Aborts the slave non-blocking transfers. - * @note This API could be called at any time to stop slave for handling the bus events. - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * @retval kStatus_Success - * @retval #kStatus_I2C_Idle - */ -void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); - -/*! - * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_slave_handle_t structure. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_InvalidArgument count is Invalid. - * @retval kStatus_Success Successfully return the count. - */ -status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); - -/*@}*/ /* end of Slave non-blocking */ - -/*! @name Slave IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle slave interrupts. - * @note This function does not need to be called unless you are reimplementing the - * non blocking API's interrupt handler routines to add special functionality. - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - */ -void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle); - -/*@}*/ /* end of Slave IRQ handler */ - -/*! @} */ /* end of i2c_slave_driver */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2C_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c_dma.c deleted file mode 100644 index 45d47e59073..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c_dma.c +++ /dev/null @@ -1,652 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_i2c_dma.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c_dma" -#endif - -/*transfer = *xfer; - transfer = &(handle->transfer); - - handle->transferCount = 0U; - handle->remainingBytesDMA = 0U; - handle->buf = (uint8_t *)transfer->data; - handle->remainingSubaddr = 0U; - - if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) - { - handle->checkAddrNack = false; - /* Start condition shall not be ommited, switch directly to next phase */ - if (transfer->dataSize == 0U) - { - handle->state = (uint8_t)kStopState; - } - else if (handle->transfer.direction == kI2C_Write) - { - handle->state = (uint8_t)kTransmitDataState; - } - else if (handle->transfer.direction == kI2C_Read) - { - handle->state = (xfer->dataSize == 1U) ? (uint8_t)kReceiveLastDataState : (uint8_t)kReceiveDataState; - } - else - { - return kStatus_I2C_InvalidParameter; - } - } - else - { - if (transfer->subaddressSize != 0U) - { - int i; - uint32_t subaddress; - - if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) - { - return kStatus_I2C_InvalidParameter; - } - - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) - { - handle->subaddrBuf[i] = (uint8_t)subaddress & 0xffU; - subaddress >>= 8; - } - handle->remainingSubaddr = transfer->subaddressSize; - } - - handle->state = (uint8_t)kStartState; - handle->checkAddrNack = true; - } - - return kStatus_Success; -} - -static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - uint32_t transfer_size; - dma_transfer_config_t xferConfig; - uint32_t address; - address = (uint32_t)&base->MSTDAT; - - /* Update transfer count */ - int32_t count = handle->buf - (uint8_t *)handle->transfer.data; - assert(count >= 0); - handle->transferCount = (uint32_t)count; - - /* Check if there is anything to be transferred at all */ - if (handle->remainingBytesDMA == 0U) - { - /* No data to be transferrred, disable DMA */ - base->MSTCTL = 0; - return; - } - - /* Calculate transfer size */ - transfer_size = handle->remainingBytesDMA; - if (transfer_size > (uint32_t)I2C_MAX_DMA_TRANSFER_COUNT) - { - transfer_size = (uint32_t)I2C_MAX_DMA_TRANSFER_COUNT; - } - - switch (handle->transfer.direction) - { - case kI2C_Write: - DMA_PrepareTransfer(&xferConfig, handle->buf, (uint32_t *)address, sizeof(uint8_t), transfer_size, - kDMA_MemoryToPeripheral, NULL); - break; - - case kI2C_Read: - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, handle->buf, sizeof(uint8_t), transfer_size, - kDMA_PeripheralToMemory, NULL); - break; - - default: - /* This should never happen */ - assert(0); - break; - } - - (void)DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - DMA_StartTransfer(handle->dmaHandle); - - handle->remainingBytesDMA -= transfer_size; - handle->buf += transfer_size; - handle->checkAddrNack = false; -} - -static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone) -{ - uint32_t status; - uint32_t master_state; - struct _i2c_master_transfer *transfer; - dma_transfer_config_t xferConfig; - status_t err; - uint32_t start_flag = 0U; - uint32_t address; - address = (uint32_t)&base->MSTDAT; - - transfer = &(handle->transfer); - - *isDone = false; - - status = I2C_GetStatusFlags(base); - - if ((status & (uint32_t)I2C_STAT_MSTARBLOSS_MASK) != 0U) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_ArbitrationLost; - } - - if ((status & (uint32_t)I2C_STAT_MSTSTSTPERR_MASK) != 0U) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_StartStopError; - } - - /* Event timeout happens when the time since last bus event has been longer than the time specified by TIMEOUT - register. eg: Start signal fails to generate, no error status is set and transfer hangs if glitch on bus happens - before, the timeout status can be used to avoid the transfer hangs indefinitely. */ - if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) - { - I2C_ClearStatusFlags(base, (uint32_t)kI2C_EventTimeoutFlag); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_EventTimeout; - } - - /* SCL timeout happens when the slave is holding the SCL line low and the time has been longer than the time - specified by TIMEOUT register. */ - if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) - { - I2C_ClearStatusFlags(base, (uint32_t)kI2C_SclTimeoutFlag); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_SclLowTimeout; - } - - if ((status & (uint32_t)I2C_STAT_MSTPENDING_MASK) == 0U) - { - return kStatus_I2C_Busy; - } - - /* Get the state of the I2C module */ - master_state = (base->STAT & (uint32_t)I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (master_state == (uint32_t)I2C_STAT_MSTCODE_NACKDAT)) - { - /* Slave NACKed last byte, issue stop and return error */ - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = (uint8_t)kWaitForCompletionState; - if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (handle->checkAddrNack == true)) - { - return kStatus_I2C_Addr_Nak; - } - else - { - return kStatus_I2C_Nak; - } - } - - err = kStatus_Success; - - if (handle->state == (uint8_t)kStartState) - { - /* set start flag for later use */ - start_flag = I2C_MSTCTL_MSTSTART_MASK; - - if (handle->remainingSubaddr != 0U) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = (uint8_t)kTransmitSubaddrState; - } - else if (transfer->direction == kI2C_Write) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - if (transfer->dataSize == 0U) - { - /* No data to be transferred, initiate start and schedule stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - handle->state = (uint8_t)kStopState; - return err; - } - handle->state = (uint8_t)kTransmitDataState; - } - else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0U)) - { - base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; - if (transfer->dataSize == 1U) - { - /* The very last byte is always received by means of SW */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - handle->state = (uint8_t)kReceiveLastDataState; - return err; - } - handle->state = (uint8_t)kReceiveDataState; - } - else - { - handle->state = (uint8_t)kIdleState; - err = kStatus_I2C_UnexpectedState; - return err; - } - } - - switch (handle->state) - { - case (uint8_t)kTransmitSubaddrState: - if ((master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) && (0U == start_flag)) - { - return kStatus_I2C_UnexpectedState; - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - - /* Prepare and submit DMA transfer. */ - DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (uint32_t *)address, sizeof(uint8_t), - handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL); - (void)DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - DMA_StartTransfer(handle->dmaHandle); - handle->remainingSubaddr = 0; - if (transfer->dataSize != 0U) - { - /* There is data to be transferred, if there is write to read turnaround it is necessary to perform - * repeated start */ - handle->state = (transfer->direction == kI2C_Read) ? (uint8_t)kStartState : (uint8_t)kTransmitDataState; - } - else - { - /* No more data, schedule stop condition */ - handle->state = (uint8_t)kStopState; - } - break; - - case (uint8_t)kTransmitDataState: - if ((master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) && (0U == start_flag)) - { - return kStatus_I2C_UnexpectedState; - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - handle->remainingBytesDMA = handle->transfer.dataSize; - - I2C_RunDMATransfer(base, handle); - - /* Schedule stop condition */ - handle->state = (uint8_t)kStopState; - handle->checkAddrNack = false; - break; - - case (uint8_t)kReceiveDataState: - if ((master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) && (0U == start_flag)) - { - if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStartFlag)) - { - return kStatus_I2C_UnexpectedState; - } - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - handle->remainingBytesDMA = handle->transfer.dataSize - 1U; - - if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) - { - /* Read the master data register to avoid the data be read again */ - (void)base->MSTDAT; - } - I2C_RunDMATransfer(base, handle); - - /* Schedule reception of last data byte */ - handle->state = (uint8_t)kReceiveLastDataState; - handle->checkAddrNack = false; - break; - - case (uint8_t)kReceiveLastDataState: - if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) - { - return kStatus_I2C_UnexpectedState; - } - - ((uint8_t *)transfer->data)[transfer->dataSize - 1U] = (uint8_t)base->MSTDAT; - handle->transferCount++; - - /* No more data expected, issue NACK and STOP right away */ - if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStopFlag)) - { - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - } - handle->state = (uint8_t)kWaitForCompletionState; - break; - - case (uint8_t)kStopState: - if ((transfer->flags & (uint32_t)kI2C_TransferNoStopFlag) != 0U) - { - /* Stop condition is omitted, we are done */ - *isDone = true; - handle->state = (uint8_t)kIdleState; - break; - } - /* Send stop condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = (uint8_t)kWaitForCompletionState; - break; - - case (uint8_t)kWaitForCompletionState: - *isDone = true; - handle->state = (uint8_t)kIdleState; - break; - - case (uint8_t)kStartState: - case (uint8_t)kIdleState: - default: - /* State machine shall not be invoked again once it enters the idle state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - return err; -} - -static void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - bool isDone; - status_t result; - - /* Don't do anything if we don't have a valid handle. */ - if (NULL == handle) - { - return; - } - - result = I2C_RunTransferStateMachineDMA(base, handle, &isDone); - - if ((result != kStatus_Success) || isDone) - { - /* Restore handle to idle state. */ - handle->state = (uint8_t)kIdleState; - - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | - I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); - - /* Invoke callback. */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } -} - -static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) -{ - i2c_master_dma_private_handle_t *dmaPrivateHandle; - - /* Don't do anything if we don't have a valid handle. */ - if (NULL == handle) - { - return; - } - - dmaPrivateHandle = (i2c_master_dma_private_handle_t *)userData; - I2C_RunDMATransfer(dmaPrivateHandle->base, dmaPrivateHandle->handle); -} - -/*! - * brief Init the I2C handle which is used in transactional functions - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - * param callback pointer to user callback function - * param userData user param passed to the callback function - * param dmaHandle DMA handle pointer - */ -void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, - i2c_master_dma_handle_t *handle, - i2c_master_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *dmaHandle) -{ - assert(handle != NULL); - assert(dmaHandle != NULL); - - uint32_t instance; - i2c_dma_to_flexcomm_t handler; - handler.i2c_dma_master_handler = I2C_MasterTransferDMAHandleIRQ; - - /* Zero handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Set the user callback and userData. */ - handle->completionCallback = callback; - handle->userData = userData; - - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | - I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); - (void)EnableIRQ(s_i2cIRQ[instance]); - - /* Set the handle for DMA. */ - handle->dmaHandle = dmaHandle; - - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - DMA_SetCallback(dmaHandle, I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]); -} - -/*! - * brief Performs a master dma non-blocking transfer on the I2C bus - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - * param xfer pointer to transfer structure of i2c_master_transfer_t - * retval kStatus_Success Sucessully complete the data transmission. - * retval kStatus_I2C_Busy Previous transmission still not finished. - * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. - */ -status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer) -{ - status_t result; - - assert(handle != NULL); - assert(xfer != NULL); - assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); - - /* Return busy if another transaction is in progress. */ - if (handle->state != (uint8_t)kIdleState) - { - return kStatus_I2C_Busy; - } - - /* Prepare transfer state machine. */ - result = I2C_InitTransferStateMachineDMA(base, handle, xfer); - - /* Clear error flags. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Enable I2C internal IRQ sources */ - /* Enable arbitration lost interrupt, start/stop error interrupt and master pending interrupt. - The master pending flag is not set during dma transfer. */ - I2C_EnableInterrupts(base, I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | - I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); - - return result; -} - -/*! - * brief Get master transfer status during a dma non-blocking transfer - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - * param count Number of bytes transferred so far by the non-blocking transaction. - */ -status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state == (uint8_t)kIdleState) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* There is no necessity to disable interrupts as we read a single integer value */ - *count = handle->transferCount; - return kStatus_Success; -} - -/*! - * brief Abort a master dma non-blocking transfer in a early time - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - */ -void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - uint32_t status; - uint32_t master_state; - - if (handle->state != (uint8_t)kIdleState) - { - DMA_AbortTransfer(handle->dmaHandle); - - /* Disable DMA */ - base->MSTCTL = 0; - - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | - I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); - - /* Wait until module is ready */ - do - { - status = I2C_GetStatusFlags(base); - } while ((status & (uint8_t)I2C_STAT_MSTPENDING_MASK) == 0U); - - /* Clear controller state. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Get the state of the I2C module */ - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if (master_state != (uint32_t)I2C_STAT_MSTCODE_IDLE) - { - /* Send a stop command to finalize the transfer. */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - - /* Wait until module is ready */ - do - { - status = I2C_GetStatusFlags(base); - } while ((status & (uint32_t)I2C_STAT_MSTPENDING_MASK) == 0U); - - /* Clear controller state. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - } - - /* Reset the state to idle. */ - handle->state = (uint8_t)kIdleState; - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c_dma.h deleted file mode 100644 index 07899f9c7c9..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c_dma.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2C_DMA_H_ -#define _FSL_I2C_DMA_H_ - -#include "fsl_i2c.h" -#include "fsl_dma.h" - -/*! - * @addtogroup i2c_dma_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2C DMA driver version. */ -#define FSL_I2C_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) -/*@}*/ - -/*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */ -#define I2C_MAX_DMA_TRANSFER_COUNT 1024 - -/*! @brief I2C master dma handle typedef. */ -typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t; - -/*! @brief I2C master dma transfer callback typedef. */ -typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base, - i2c_master_dma_handle_t *handle, - status_t status, - void *userData); - -/*! @brief Typedef for master dma handler. */ -typedef void (*flexcomm_i2c_dma_master_irq_handler_t)(I2C_Type *base, i2c_master_dma_handle_t *handle); - -/*! @brief I2C master dma transfer structure. */ -struct _i2c_master_dma_handle -{ - uint8_t state; /*!< Transfer state machine current state. */ - uint32_t transferCount; /*!< Indicates progress of the transfer */ - uint32_t remainingBytesDMA; /*!< Remaining byte count to be transferred using DMA. */ - uint8_t *buf; /*!< Buffer pointer for current state. */ - uint32_t remainingSubaddr; - uint8_t subaddrBuf[4]; - bool checkAddrNack; /*!< Whether to check the nack signal is detected during addressing. */ - dma_handle_t *dmaHandle; /*!< The DMA handler used. */ - i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ - i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */ - void *userData; /*!< Callback parameter passed to callback function. */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus. */ - -/*! - * @name I2C Block DMA Transfer Operation - * @{ - */ - -/*! - * @brief Init the I2C handle which is used in transactional functions - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param callback pointer to user callback function - * @param userData user param passed to the callback function - * @param dmaHandle DMA handle pointer - */ -void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, - i2c_master_dma_handle_t *handle, - i2c_master_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *dmaHandle); - -/*! - * @brief Performs a master dma non-blocking transfer on the I2C bus - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param xfer pointer to transfer structure of i2c_master_transfer_t - * @retval kStatus_Success Sucessully complete the data transmission. - * @retval kStatus_I2C_Busy Previous transmission still not finished. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. - */ -status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Get master transfer status during a dma non-blocking transfer - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param count Number of bytes transferred so far by the non-blocking transaction. - */ -status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count); - -/*! - * @brief Abort a master dma non-blocking transfer in a early time - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - */ -void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle); - -/* @} */ -#if defined(__cplusplus) -} -#endif /*_cplusplus. */ -/*@}*/ -#endif /*_FSL_I2C_DMA_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s.c deleted file mode 100644 index c13f2f4bcd4..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s.c +++ /dev/null @@ -1,1198 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_i2s.h" -#include "fsl_flexcomm.h" -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s" -#endif - -/* TODO - absent in device header files, should be there */ -#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) -#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) -#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) -#define I2S_FIFOCFG_PACK48_MASK (0x8U) -#define I2S_FIFOCFG_PACK48_SHIFT (3U) -#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) -/*! @brief i2s empty tx fifo timeout value */ -#define I2S_FIFO_DEPTH (8U) -#define I2S_TX_ONE_SAMPLE_MAX_TIMEOUT (125U) /* 8K/8bit one sample need 125us*/ -#define I2S_TX_FIFO_EMPTY_TIMEOUT(count) (count) * I2S_TX_ONE_SAMPLE_MAX_TIMEOUT -/*! @brief _i2s_state I2S states. */ -enum -{ - kI2S_StateIdle = 0x0, /*!< Not performing transfer */ - kI2S_StateTx, /*!< Performing transmit */ - kI2S_StateTxWaitToWriteDummyData, /*!< Wait on FIFO in order to write final dummy data there */ - kI2S_StateTxWaitForEmptyFifo, /*!< Wait for FIFO to be flushed */ - kI2S_StateRx, /*!< Performing receive */ -}; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -static void I2S_Config(I2S_Type *base, const i2s_config_t *config); -static void I2S_TxEnable(I2S_Type *base, bool enable); -static void I2S_RxEnable(I2S_Type *base, bool enable); -static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map i2c instance number to base address. */ -static const uint32_t s_i2sBaseAddrs[] = I2S_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_i2sIRQ[] = I2S_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! - * @brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * @param base The I2S peripheral base address. - * @return I2S instance number starting from 0. - */ -static uint32_t I2S_GetInstance(I2S_Type *base) -{ - uint32_t i; - for (i = 0; i < (uint32_t)ARRAY_SIZE(s_i2sBaseAddrs); i++) - { - if ((uint32_t)base == s_i2sBaseAddrs[i]) - { - return i; - } - } - assert(false); - return 0; -} - -/*! - * brief Transmitter bit clock rate configurations. - * - * param base SAI base pointer. - * param sourceClockHz, bit clock source frequency. - * param sampleRate audio data sample rate. - * param bitWidth, audio data bitWidth. - * param channelNumbers, audio channel numbers. - */ -void I2S_SetBitClockRate( - I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers) -{ - uint32_t bitClockDivider = sourceClockHz / sampleRate / bitWidth / channelNumbers; - - assert(bitClockDivider >= 1U); - base->DIV = I2S_DIV_DIV(bitClockDivider - 1U); -} - -/*! - * brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S transmission using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_TxGetDefaultConfig(). - * - * note This API should be called at the beginning of the application to use - * the I2S driver. - * - * param base I2S base pointer. - * param config pointer to I2S configuration structure. - */ -void I2S_TxInit(I2S_Type *base, const i2s_config_t *config) -{ - uint32_t cfg = 0U; - uint32_t trig = 0U; - - (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_TX); - I2S_Config(base, config); - - /* Configure FIFO */ - - cfg |= I2S_FIFOCFG_ENABLETX(1U); /* enable TX FIFO */ - cfg |= I2S_FIFOCFG_EMPTYTX(1U); /* empty TX FIFO */ - cfg |= I2S_FIFOCFG_TXI2SE0(config->txEmptyZero); /* transmit zero when buffer becomes empty or last item */ - cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ - trig |= I2S_FIFOTRIG_TXLVLENA(1U); /* enable TX FIFO trigger */ - trig |= I2S_FIFOTRIG_TXLVL(config->watermark); /* set TX FIFO trigger level */ - - base->FIFOCFG = cfg; - base->FIFOTRIG = trig; -} - -/*! - * brief Initializes the FLEXCOMM peripheral for I2S receive functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S receive using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_RxGetDefaultConfig(). - * - * note This API should be called at the beginning of the application to use - * the I2S driver. - * - * param base I2S base pointer. - * param config pointer to I2S configuration structure. - */ -void I2S_RxInit(I2S_Type *base, const i2s_config_t *config) -{ - uint32_t cfg = 0U; - uint32_t trig = 0U; - - (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_RX); - I2S_Config(base, config); - - /* Configure FIFO */ - - cfg |= I2S_FIFOCFG_ENABLERX(1U); /* enable RX FIFO */ - cfg |= I2S_FIFOCFG_EMPTYRX(1U); /* empty RX FIFO */ - cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ - trig |= I2S_FIFOTRIG_RXLVLENA(1U); /* enable RX FIFO trigger */ - trig |= I2S_FIFOTRIG_RXLVL(config->watermark); /* set RX FIFO trigger level */ - - base->FIFOCFG = cfg; - base->FIFOTRIG = trig; -} - -/*! - * brief Flush the valid data in TX fifo. - * - * param base I2S base pointer. - * return kStatus_Fail empty TX fifo failed, kStatus_Success empty tx fifo success. - */ -status_t I2S_EmptyTxFifo(I2S_Type *base) -{ - uint32_t timeout = I2S_TX_FIFO_EMPTY_TIMEOUT(I2S_FIFO_DEPTH); - - while (((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) && (timeout != 0U)) - { - timeout -= I2S_TX_ONE_SAMPLE_MAX_TIMEOUT; - SDK_DelayAtLeastUs(I2S_TX_ONE_SAMPLE_MAX_TIMEOUT, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - } - - /* The last piece of valid data can be still being transmitted from I2S at this moment */ - timeout = I2S_TX_ONE_SAMPLE_MAX_TIMEOUT; - /* Write additional data to FIFO */ - base->FIFOWR = 0U; - while (((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) && (timeout != 0U)) - { - timeout -= I2S_TX_ONE_SAMPLE_MAX_TIMEOUT; - SDK_DelayAtLeastUs(I2S_TX_ONE_SAMPLE_MAX_TIMEOUT, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - } - - return ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) ? kStatus_Fail : kStatus_Success; -} - -/*! - * brief Sets the I2S Tx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_TxInit(). - * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified - * before calling I2S_TxInit(). - * Example: - code - i2s_config_t config; - I2S_TxGetDefaultConfig(&config); - endcode - * - * Default values: - * code - * config->masterSlave = kI2S_MasterSlaveNormalMaster; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = true; - * config->pack48 = false; - * endcode - * - * param config pointer to I2S configuration structure. - */ -void I2S_TxGetDefaultConfig(i2s_config_t *config) -{ - config->masterSlave = kI2S_MasterSlaveNormalMaster; - config->mode = kI2S_ModeI2sClassic; - config->rightLow = false; - config->leftJust = false; -#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) - config->pdmData = false; -#endif - config->sckPol = false; - config->wsPol = false; - config->divider = 1U; - config->oneChannel = false; - config->dataLength = 16U; - config->frameLength = 32U; - config->position = 0U; - config->watermark = 4U; - config->txEmptyZero = true; - config->pack48 = false; -} - -/*! - * brief Sets the I2S Rx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_RxInit(). - * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified - * before calling I2S_RxInit(). - * Example: - code - i2s_config_t config; - I2S_RxGetDefaultConfig(&config); - endcode - * - * Default values: - * code - * config->masterSlave = kI2S_MasterSlaveNormalSlave; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = false; - * config->pack48 = false; - * endcode - * - * param config pointer to I2S configuration structure. - */ -void I2S_RxGetDefaultConfig(i2s_config_t *config) -{ - config->masterSlave = kI2S_MasterSlaveNormalSlave; - config->mode = kI2S_ModeI2sClassic; - config->rightLow = false; - config->leftJust = false; -#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) - config->pdmData = false; -#endif - config->sckPol = false; - config->wsPol = false; - config->divider = 1U; - config->oneChannel = false; - config->dataLength = 16U; - config->frameLength = 32U; - config->position = 0U; - config->watermark = 4U; - config->txEmptyZero = false; - config->pack48 = false; -} - -static void I2S_Config(I2S_Type *base, const i2s_config_t *config) -{ - assert(config != NULL); - - uint32_t cfg1 = 0U; - uint32_t cfg2 = 0U; - - /* set master/slave configuration */ - cfg1 |= I2S_CFG1_MSTSLVCFG(config->masterSlave); - - /* set I2S mode */ - cfg1 |= I2S_CFG1_MODE(config->mode); - - /* set right low (channel swap) */ - cfg1 |= I2S_CFG1_RIGHTLOW(config->rightLow); - - /* set data justification */ - cfg1 |= I2S_CFG1_LEFTJUST(config->leftJust); - -#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) - if (FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn((FLEXCOMM_Type *)(uint32_t)base) > 0) - { - /* set source to PDM dmic */ - cfg1 |= I2S_CFG1_PDMDATA(config->pdmData); - } -#endif - - /* set SCLK polarity */ - cfg1 |= I2S_CFG1_SCK_POL(config->sckPol); - - /* set WS polarity */ - cfg1 |= I2S_CFG1_WS_POL(config->wsPol); - - /* set mono mode */ - cfg1 |= I2S_CFG1_ONECHANNEL(config->oneChannel); - - /* set data length */ - cfg1 |= I2S_CFG1_DATALEN(config->dataLength - 1UL); - - /* set frame length */ - cfg2 |= I2S_CFG2_FRAMELEN(config->frameLength - 1UL); - - /* set data position of this channel pair within the frame */ - cfg2 |= I2S_CFG2_POSITION(config->position); - - /* write to registers */ - base->CFG1 = cfg1; - base->CFG2 = cfg2; - - /* set the clock divider */ - base->DIV = I2S_DIV_DIV(config->divider - 1UL); -} - -/*! - * brief De-initializes the I2S peripheral. - * - * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit - * or I2S_RxInit is called to enable the clock. - * - * param base I2S base pointer. - */ -void I2S_Deinit(I2S_Type *base) -{ - /* TODO gate FLEXCOMM clock via FLEXCOMM driver */ -} - -static void I2S_TxEnable(I2S_Type *base, bool enable) -{ - if (enable) - { - I2S_Enable(base); - I2S_EnableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); - } - else - { - I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); - I2S_Disable(base); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - } -} - -static void I2S_RxEnable(I2S_Type *base, bool enable) -{ - if (enable) - { - I2S_Enable(base); - I2S_EnableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); - } - else - { - I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); - I2S_Disable(base); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - } -} - -static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer) -{ - assert(transfer->data != NULL); - - if (transfer->data == NULL) - { - return kStatus_InvalidArgument; - } - - assert(transfer->dataSize > 0U); - if (transfer->dataSize <= 0U) - { - return kStatus_InvalidArgument; - } - - if (handle->dataLength == 4U) - { - /* No alignment and data length requirements */ - } - else if ((handle->dataLength >= 5U) && (handle->dataLength <= 8U)) - { - assert((((uint32_t)transfer->data) % 2U) == 0U); - if ((((uint32_t)transfer->data) % 2U) != 0U) - { - /* Data not 2-bytes aligned */ - return kStatus_InvalidArgument; - } - - assert((transfer->dataSize % 2U) == 0U); - if ((transfer->dataSize % 2U) != 0U) - { - /* Data not in pairs of left/right channel bytes */ - return kStatus_InvalidArgument; - } - } - else if ((handle->dataLength >= 9U) && (handle->dataLength <= 16U)) - { - assert((((uint32_t)transfer->data) % 4U) == 0U); - if ((((uint32_t)transfer->data) % 4U) != 0U) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - - assert((transfer->dataSize % 4U) == 0U); - if ((transfer->dataSize % 4U) != 0U) - { - /* Data lenght not multiply of 4 */ - return kStatus_InvalidArgument; - } - } - else if ((handle->dataLength >= 17U) && (handle->dataLength <= 24U)) - { - assert((transfer->dataSize % 6U) == 0U); - if ((transfer->dataSize % 6U) != 0U) - { - /* Data lenght not multiply of 6 */ - return kStatus_InvalidArgument; - } - - assert(!((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U))); - if ((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U)) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - } - else /* if (handle->dataLength >= 25U) */ - { - assert((((uint32_t)transfer->data) % 4U) == 0U); - if ((((uint32_t)transfer->data) % 4U) != 0U) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - - if (handle->oneChannel) - { - assert((transfer->dataSize % 4U) == 0U); - if ((transfer->dataSize % 4U) != 0U) - { - /* Data lenght not multiply of 4 */ - return kStatus_InvalidArgument; - } - } - else - { - assert((transfer->dataSize % 8U) == 0U); - if ((transfer->dataSize % 8U) != 0U) - { - /* Data lenght not multiply of 8 */ - return kStatus_InvalidArgument; - } - } - } - - return kStatus_Success; -} - -#if (defined(FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) && FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) -/*! - * brief Enables I2S secondary channel. - * - * param base I2S base pointer. - * param channel seondary channel channel number, reference _i2s_secondary_channel. - * param oneChannel true is treated as single channel, functionality left channel for this pair. - * param position define the location within the frame of the data, should not bigger than 0x1FFU. - */ -void I2S_EnableSecondaryChannel(I2S_Type *base, uint32_t channel, bool oneChannel, uint32_t position) -{ - assert(channel <= (uint32_t)kI2S_SecondaryChannel3); -#if defined FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn - assert(FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn((FLEXCOMM_Type *)(uint32_t)base) == 1); -#endif - - uint32_t pcfg1 = base->SECCHANNEL[channel].PCFG1; - uint32_t pcfg2 = base->SECCHANNEL[channel].PCFG2; - - pcfg1 &= ~I2S_CFG1_ONECHANNEL_MASK; - pcfg1 |= I2S_CFG1_MAINENABLE_MASK | I2S_CFG1_ONECHANNEL(oneChannel); - - pcfg2 &= ~I2S_CFG2_POSITION_MASK; - pcfg2 |= I2S_CFG2_POSITION(position); - - base->SECCHANNEL[channel].PCFG1 = pcfg1; - base->SECCHANNEL[channel].PCFG2 = pcfg2; -} -#endif - -/*! - * brief Initializes handle for transfer of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) -{ - assert(handle != NULL); - - uint32_t instance; - - /* Clear out the handle */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2S_GetInstance(base); - - /* Save callback and user data */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Remember some items set previously by configuration */ - handle->watermark = (uint8_t)((base->FIFOTRIG & I2S_FIFOTRIG_TXLVL_MASK) >> I2S_FIFOTRIG_TXLVL_SHIFT); - handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT) != 0U ? true : false; - handle->dataLength = (uint8_t)((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; - handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT) != 0u ? true : false; - - handle->useFifo48H = false; - - /* Register IRQ handling */ - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_TxHandleIRQ, handle); - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); - (void)EnableIRQ(s_i2sIRQ[instance]); -} - -/*! - * brief Begins or queue sending of the given data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) -{ - assert(handle != NULL); - - status_t result; - - if (handle == NULL) - { - return kStatus_InvalidArgument; - } - - result = I2S_ValidateBuffer(handle, &transfer); - if (result != kStatus_Success) - { - return result; - } - - if (handle->i2sQueue[handle->queueUser].dataSize != 0UL) - { - /* Previously prepared buffers not processed yet */ - return kStatus_I2S_Busy; - } - - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_TXLVL_MASK)) | I2S_FIFOTRIG_TXLVL(handle->watermark); - I2S_TxEnable(base, true); - - return kStatus_Success; -} - -/*! - * brief Aborts sending of data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle) -{ - assert(handle != NULL); - - /* Disable I2S operation and interrupts */ - I2S_TxEnable(base, false); - - /* Reset state */ - handle->state = (uint32_t)kI2S_StateIdle; - - /* Clear transfer queue */ - (void)memset((void *)&handle->i2sQueue, 0, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); - handle->queueDriver = 0U; - handle->queueUser = 0U; -} - -/*! - * brief Initializes handle for reception of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) -{ - assert(handle != NULL); - - uint32_t instance; - - /* Clear out the handle */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2S_GetInstance(base); - - /* Save callback and user data */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Remember some items set previously by configuration */ - handle->watermark = (uint8_t)((base->FIFOTRIG & I2S_FIFOTRIG_RXLVL_MASK) >> I2S_FIFOTRIG_RXLVL_SHIFT); - handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT) != 0UL ? true : false; - handle->dataLength = (uint8_t)((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; - handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT) != 0UL ? true : false; - - handle->useFifo48H = false; - - /* Register IRQ handling */ - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_RxHandleIRQ, handle); - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); - - (void)EnableIRQ(s_i2sIRQ[instance]); -} - -/*! - * brief Begins or queue reception of data into given buffer. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. - */ -status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) -{ - assert(handle != NULL); - - status_t result; - - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - result = I2S_ValidateBuffer(handle, &transfer); - if (result != kStatus_Success) - { - return result; - } - - if (handle->i2sQueue[handle->queueUser].dataSize != 0UL) - { - /* Previously prepared buffers not processed yet */ - return kStatus_I2S_Busy; - } - - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_RXLVL_MASK)) | I2S_FIFOTRIG_RXLVL(handle->watermark); - I2S_RxEnable(base, true); - - return kStatus_Success; -} - -/*! - * brief Aborts receiving of data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle) -{ - assert(handle != NULL); - - /* Disable I2S operation and interrupts */ - I2S_RxEnable(base, false); - - /* Reset state */ - handle->state = (uint32_t)kI2S_StateIdle; - - /* Clear transfer queue */ - (void)memset((void *)&handle->i2sQueue, 0, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); - handle->queueDriver = 0U; - handle->queueUser = 0U; -} - -/*! - * brief Returns number of bytes transferred so far. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param[out] count number of bytes transferred so far by the non-blocking transaction. - * - * retval kStatus_Success - * retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - assert(count != NULL); - - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - if (handle->state == (uint32_t)kI2S_StateIdle) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->transferCount; - - return kStatus_Success; -} - -/*! - * brief Returns number of buffer underruns or overruns. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param[out] count number of transmit errors encountered so far by the non-blocking transaction. - * - * retval kStatus_Success - * retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - assert(count != NULL); - - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - if (handle->state == (uint32_t)kI2S_StateIdle) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->errorCount; - - return kStatus_Success; -} - -/*! - * brief Invoked from interrupt handler when transmit FIFO level decreases. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) -{ - uint32_t intstat = base->FIFOINTSTAT; - uint32_t data; - uint8_t queueDriverIndex = handle->queueDriver; - uint32_t dataAddr = (uint32_t)handle->i2sQueue[queueDriverIndex].data; - uint32_t dataSize = handle->i2sQueue[queueDriverIndex].dataSize; - - if ((intstat & I2S_FIFOINTSTAT_TXERR_MASK) != 0UL) - { - handle->errorCount++; - - /* Clear TX error interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_TXERR(1U); - } - - if ((intstat & I2S_FIFOINTSTAT_TXLVL_MASK) != 0UL) - { - if ((handle->state != (uint32_t)kI2S_StateTx) && (dataSize != 0U) && (dataAddr != 0U)) - { - handle->state = (uint32_t)kI2S_StateTx; - } - - if (handle->state == (uint32_t)kI2S_StateTx) - { - /* Send data */ - - while (((base->FIFOSTAT & I2S_FIFOSTAT_TXNOTFULL_MASK) != 0UL) && (dataSize > 0U)) - { - /* Write output data */ - if (handle->dataLength == 4U) - { - data = *((uint8_t *)dataAddr); - base->FIFOWR = ((data & 0xF0U) << 12U) | (data & 0xFU); - dataAddr++; - handle->transferCount++; - dataSize--; - } - else if (handle->dataLength <= 8U) - { - data = *((volatile uint16_t *)dataAddr); - if (handle->oneChannel) - { - base->FIFOWR = (data & 0xFFU); - dataAddr += sizeof(uint8_t); - handle->transferCount += sizeof(uint8_t); - dataSize -= sizeof(uint8_t); - } - else - { - base->FIFOWR = ((data & 0xFF00U) << 8U) | (data & 0xFFU); - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - } - else if (handle->dataLength <= 16U) - { - data = *((volatile uint32_t *)(dataAddr)); - if (handle->oneChannel) - { - base->FIFOWR = data & 0xFFFFU; - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - else - { - base->FIFOWR = data; - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - } - else if (handle->dataLength <= 24U) - { - if (handle->pack48) - { - if (handle->useFifo48H) - { - base->FIFOWR48H = *((volatile uint16_t *)(dataAddr)); - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - handle->useFifo48H = false; - } - else - { - base->FIFOWR = *((volatile uint32_t *)(dataAddr)); - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - handle->useFifo48H = true; - } - } - else - { - data = (uint32_t)(*(uint8_t *)(dataAddr++)); - data |= ((uint32_t)(*(uint8_t *)(dataAddr++))) << 8U; - data |= ((uint32_t)(*(uint8_t *)(dataAddr++))) << 16U; - if ((handle->useFifo48H) && (handle->oneChannel == false)) - { - base->FIFOWR48H = data; - handle->useFifo48H = false; - } - else - { - base->FIFOWR = data; - handle->useFifo48H = true; - } - handle->transferCount += 3U; - dataSize -= 3U; - } - } - else /* if (handle->dataLength <= 32U) */ - { - base->FIFOWR = *((volatile uint32_t *)(dataAddr)); - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - - if (dataSize == 0U) - { - handle->i2sQueue[queueDriverIndex].dataSize = 0U; - /* Actual data buffer sent out, switch to a next one */ - handle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; - - /* Notify user */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); - } - - /* Check if the next buffer contains anything to send */ - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* Everything has been written to FIFO */ - handle->state = kI2S_StateTxWaitToWriteDummyData; - break; - } - } - else - { - handle->i2sQueue[queueDriverIndex].dataSize = dataSize; - handle->i2sQueue[queueDriverIndex].data = (uint8_t *)dataAddr; - } - } - } - else if (handle->state == (uint32_t)kI2S_StateTxWaitToWriteDummyData) - { - /* Write dummy data */ - if ((handle->dataLength > 16U) && (handle->dataLength < 25U)) - { - if (handle->useFifo48H) - { - base->FIFOWR48H = 0U; - handle->useFifo48H = false; - } - else - { - base->FIFOWR = 0U; - base->FIFOWR48H = 0U; - } - } - else - { - base->FIFOWR = 0U; - } - - /* Next time invoke this handler when FIFO becomes empty (TX level 0) */ - base->FIFOTRIG &= ~I2S_FIFOTRIG_TXLVL_MASK; - handle->state = (uint32_t)kI2S_StateTxWaitForEmptyFifo; - } - else if (handle->state == (uint32_t)kI2S_StateTxWaitForEmptyFifo) - { - /* FIFO, including additional dummy data, has been emptied now, - * all relevant data should have been output from peripheral */ - - /* Stop transfer */ - I2S_Disable(base); - I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - - /* Reset state */ - handle->state = (uint32_t)kI2S_StateIdle; - - /* Notify user */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); - } - } - else - { - /* Do nothing */ - } - - /* Clear TX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_TXLVL(1U); - } -} - -/*! - * brief Invoked from interrupt handler when receive FIFO level decreases. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) -{ - uint32_t intstat = base->FIFOINTSTAT; - uint32_t data; - uint8_t queueDriverIndex = handle->queueDriver; - uint32_t dataAddr = (uint32_t)handle->i2sQueue[queueDriverIndex].data; - uint32_t dataSize = handle->i2sQueue[queueDriverIndex].dataSize; - - if ((intstat & I2S_FIFOINTSTAT_RXERR_MASK) != 0UL) - { - handle->errorCount++; - - /* Clear RX error interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXERR(1U); - } - - if ((intstat & I2S_FIFOINTSTAT_RXLVL_MASK) != 0UL) - { - while (((base->FIFOSTAT & I2S_FIFOSTAT_RXNOTEMPTY_MASK) != 0UL) && (dataSize > 0U)) - { - /* Read input data */ - if (handle->dataLength == 4U) - { - data = base->FIFORD; - *((uint8_t *)dataAddr) = (uint8_t)(((data & 0x000F0000U) >> 12U) | (data & 0x0000000FU)); - dataAddr++; - handle->transferCount++; - dataSize--; - } - else if (handle->dataLength <= 8U) - { - data = base->FIFORD; - - if (handle->oneChannel) - { - *((volatile uint8_t *)dataAddr) = (uint8_t)(data & 0xFFU); - dataAddr += sizeof(uint8_t); - handle->transferCount += sizeof(uint8_t); - dataSize -= sizeof(uint8_t); - } - else - { - *((volatile uint16_t *)dataAddr) = (uint16_t)(((data >> 8U) & 0xFF00U) | (data & 0xFFU)); - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - } - else if (handle->dataLength <= 16U) - { - data = base->FIFORD; - - if (handle->oneChannel) - { - *((volatile uint16_t *)dataAddr) = (uint16_t)(data & 0xFFFFU); - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - else - { - *((volatile uint32_t *)dataAddr) = data; - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - } - else if (handle->dataLength <= 24U) - { - if (handle->pack48) - { - if (handle->useFifo48H) - { - data = base->FIFORD48H; - handle->useFifo48H = false; - - *((volatile uint16_t *)dataAddr) = (uint16_t)data; - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - else - { - data = base->FIFORD; - handle->useFifo48H = true; - - *((volatile uint32_t *)dataAddr) = data; - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - } - else - { - if (handle->useFifo48H) - { - data = base->FIFORD48H; - handle->useFifo48H = false; - } - else - { - data = base->FIFORD; - handle->useFifo48H = true; - } - - *(uint8_t *)(dataAddr++) = (uint8_t)(data & 0xFFU); - *(uint8_t *)(dataAddr++) = (uint8_t)((data >> 8U) & 0xFFU); - *(uint8_t *)(dataAddr++) = (uint8_t)((data >> 16U) & 0xFFU); - handle->transferCount += 3U; - dataSize -= 3U; - } - } - else /* if (handle->dataLength <= 32U) */ - { - data = base->FIFORD; - *((volatile uint32_t *)dataAddr) = data; - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - - if (dataSize == 0U) - { - handle->i2sQueue[queueDriverIndex].dataSize = 0U; - /* Actual data buffer filled with input data, switch to a next one */ - handle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; - - /* Notify user */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); - } - - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* No other buffer prepared to receive data into */ - - /* Disable I2S operation and interrupts */ - I2S_Disable(base); - I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - - /* Reset state */ - handle->state = (uint32_t)kI2S_StateIdle; - - /* Notify user */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); - } - - /* Clear RX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); - - return; - } - } - else - { - handle->i2sQueue[queueDriverIndex].dataSize = dataSize; - handle->i2sQueue[queueDriverIndex].data = (uint8_t *)dataAddr; - } - } - - /* Clear RX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s.h deleted file mode 100644 index e0787d6b145..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s.h +++ /dev/null @@ -1,513 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2S_H_ -#define _FSL_I2S_H_ - -#include "fsl_device_registers.h" -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup i2s_driver - * @{ - */ - -/*! @file */ - -/*! @name Driver version */ -/*@{*/ - -/*! @brief I2S driver version 2.3.1. */ -#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) -/*@}*/ - -#ifndef I2S_NUM_BUFFERS - -/*! @brief Number of buffers . */ -#define I2S_NUM_BUFFERS (4U) - -#endif - -/*! @brief _i2s_status I2S status codes. */ -enum -{ - kStatus_I2S_BufferComplete = - MAKE_STATUS(kStatusGroup_I2S, 0), /*!< Transfer from/into a single buffer has completed */ - kStatus_I2S_Done = MAKE_STATUS(kStatusGroup_I2S, 1), /*!< All buffers transfers have completed */ - kStatus_I2S_Busy = - MAKE_STATUS(kStatusGroup_I2S, 2), /*!< Already performing a transfer and cannot queue another buffer */ -}; - -/*! - * @brief I2S flags. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -typedef enum _i2s_flags -{ - kI2S_TxErrorFlag = I2S_FIFOINTENSET_TXERR_MASK, /*!< TX error interrupt */ - kI2S_TxLevelFlag = I2S_FIFOINTENSET_TXLVL_MASK, /*!< TX level interrupt */ - kI2S_RxErrorFlag = I2S_FIFOINTENSET_RXERR_MASK, /*!< RX error interrupt */ - kI2S_RxLevelFlag = I2S_FIFOINTENSET_RXLVL_MASK /*!< RX level interrupt */ -} i2s_flags_t; - -/*! @brief Master / slave mode. */ -typedef enum _i2s_master_slave -{ - kI2S_MasterSlaveNormalSlave = 0x0, /*!< Normal slave */ - kI2S_MasterSlaveWsSyncMaster = 0x1, /*!< WS synchronized master */ - kI2S_MasterSlaveExtSckMaster = 0x2, /*!< Master using existing SCK */ - kI2S_MasterSlaveNormalMaster = 0x3 /*!< Normal master */ -} i2s_master_slave_t; - -/*! @brief I2S mode. */ -typedef enum _i2s_mode -{ - kI2S_ModeI2sClassic = 0x0, /*!< I2S classic mode */ - kI2S_ModeDspWs50 = 0x1, /*!< DSP mode, WS having 50% duty cycle */ - kI2S_ModeDspWsShort = 0x2, /*!< DSP mode, WS having one clock long pulse */ - kI2S_ModeDspWsLong = 0x3 /*!< DSP mode, WS having one data slot long pulse */ -} i2s_mode_t; - -/*! @brief _i2s_secondary_channel I2S secondary channel. */ -enum -{ - kI2S_SecondaryChannel1 = 0U, /*!< secondary channel 1 */ - kI2S_SecondaryChannel2 = 1U, /*!< secondary channel 2 */ - kI2S_SecondaryChannel3 = 2U, /*!< secondary channel 3 */ -}; - -/*! @brief I2S configuration structure. */ -typedef struct _i2s_config -{ - i2s_master_slave_t masterSlave; /*!< Master / slave configuration */ - i2s_mode_t mode; /*!< I2S mode */ - bool rightLow; /*!< Right channel data in low portion of FIFO */ - bool leftJust; /*!< Left justify data in FIFO */ -#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) - bool pdmData; /*!< Data source is the D-Mic subsystem */ -#endif - bool sckPol; /*!< SCK polarity */ - bool wsPol; /*!< WS polarity */ - uint16_t divider; /*!< Flexcomm function clock divider (1 - 4096) */ - bool oneChannel; /*!< true mono, false stereo */ - uint8_t dataLength; /*!< Data length (4 - 32) */ - uint16_t frameLength; /*!< Frame width (4 - 512) */ - uint16_t position; /*!< Data position in the frame */ - uint8_t watermark; /*!< FIFO trigger level */ - bool txEmptyZero; /*!< Transmit zero when buffer becomes empty or last item */ - bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit - values) */ -} i2s_config_t; - -/*! @brief Buffer to transfer from or receive audio data into. */ -typedef struct _i2s_transfer -{ - uint8_t *data; /*!< Pointer to data buffer. */ - size_t dataSize; /*!< Buffer size in bytes. */ -} i2s_transfer_t; - -/*! @brief Transactional state of the intialized transfer or receive I2S operation. */ -typedef struct _i2s_handle i2s_handle_t; - -/*! - * @brief Callback function invoked from transactional API - * on completion of a single buffer transfer. - * - * @param base I2S base pointer. - * @param handle pointer to I2S transaction. - * @param completionStatus status of the transaction. - * @param userData optional pointer to user arguments data. - */ -typedef void (*i2s_transfer_callback_t)(I2S_Type *base, - i2s_handle_t *handle, - status_t completionStatus, - void *userData); - -/*! @brief Members not to be accessed / modified outside of the driver. */ -struct _i2s_handle -{ - volatile uint32_t state; /*!< State of transfer */ - i2s_transfer_callback_t completionCallback; /*!< Callback function pointer */ - void *userData; /*!< Application data passed to callback */ - bool oneChannel; /*!< true mono, false stereo */ - uint8_t dataLength; /*!< Data length (4 - 32) */ - bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit - values) */ - uint8_t watermark; /*!< FIFO trigger level */ - bool useFifo48H; /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */ - - volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ - volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ - volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ - volatile uint32_t errorCount; /*!< Number of buffer underruns/overruns */ - volatile uint32_t transferCount; /*!< Number of bytes transferred */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S transmission using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_TxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the I2S driver. - * - * @param base I2S base pointer. - * @param config pointer to I2S configuration structure. - */ -void I2S_TxInit(I2S_Type *base, const i2s_config_t *config); - -/*! - * @brief Initializes the FLEXCOMM peripheral for I2S receive functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S receive using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_RxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the I2S driver. - * - * @param base I2S base pointer. - * @param config pointer to I2S configuration structure. - */ -void I2S_RxInit(I2S_Type *base, const i2s_config_t *config); - -/*! - * @brief Sets the I2S Tx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_TxInit(). - * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified - * before calling I2S_TxInit(). - * Example: - @code - i2s_config_t config; - I2S_TxGetDefaultConfig(&config); - @endcode - * - * Default values: - * @code - * config->masterSlave = kI2S_MasterSlaveNormalMaster; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = true; - * config->pack48 = false; - * @endcode - * - * @param config pointer to I2S configuration structure. - */ -void I2S_TxGetDefaultConfig(i2s_config_t *config); - -/*! - * @brief Sets the I2S Rx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_RxInit(). - * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified - * before calling I2S_RxInit(). - * Example: - @code - i2s_config_t config; - I2S_RxGetDefaultConfig(&config); - @endcode - * - * Default values: - * @code - * config->masterSlave = kI2S_MasterSlaveNormalSlave; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = false; - * config->pack48 = false; - * @endcode - * - * @param config pointer to I2S configuration structure. - */ -void I2S_RxGetDefaultConfig(i2s_config_t *config); - -/*! - * @brief De-initializes the I2S peripheral. - * - * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit - * or I2S_RxInit is called to enable the clock. - * - * @param base I2S base pointer. - */ -void I2S_Deinit(I2S_Type *base); - -/*! - * @brief Transmitter/Receiver bit clock rate configurations. - * - * @param base SAI base pointer. - * @param sourceClockHz bit clock source frequency. - * @param sampleRate audio data sample rate. - * @param bitWidth audio data bitWidth. - * @param channelNumbers audio channel numbers. - */ -void I2S_SetBitClockRate( - I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers); - -/*! @} */ - -/*! - * @name Non-blocking API - * @{ - */ - -/*! - * @brief Initializes handle for transfer of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); - -/*! - * @brief Begins or queue sending of the given data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts sending of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Initializes handle for reception of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); - -/*! - * @brief Begins or queue reception of data into given buffer. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. - */ -status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts receiving of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Returns number of bytes transferred so far. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param[out] count number of bytes transferred so far by the non-blocking transaction. - * - * @retval kStatus_Success - * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); - -/*! - * @brief Returns number of buffer underruns or overruns. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param[out] count number of transmit errors encountered so far by the non-blocking transaction. - * - * @retval kStatus_Success - * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); - -/*! @} */ - -/*! - * @name Enable / disable - * @{ - */ - -/*! - * @brief Enables I2S operation. - * - * @param base I2S base pointer. - */ -static inline void I2S_Enable(I2S_Type *base) -{ - base->CFG1 |= I2S_CFG1_MAINENABLE(1U); -} - -#if (defined(FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) && FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) -/*! - * @brief Enables I2S secondary channel. - * - * @param base I2S base pointer. - * @param channel seondary channel channel number, reference _i2s_secondary_channel. - * @param oneChannel true is treated as single channel, functionality left channel for this pair. - * @param position define the location within the frame of the data, should not bigger than 0x1FFU. - */ -void I2S_EnableSecondaryChannel(I2S_Type *base, uint32_t channel, bool oneChannel, uint32_t position); - -/*! - * @brief Disables I2S secondary channel. - * - * @param base I2S base pointer. - * @param channel seondary channel channel number, reference _i2s_secondary_channel. - */ -static inline void I2S_DisableSecondaryChannel(I2S_Type *base, uint32_t channel) -{ -#if defined FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn - assert(FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn((FLEXCOMM_Type *)(uint32_t)base) == 1); -#endif - - base->SECCHANNEL[channel].PCFG1 &= ~I2S_CFG1_MAINENABLE_MASK; -} -#endif -/*! - * @brief Disables I2S operation. - * - * @param base I2S base pointer. - */ -static inline void I2S_Disable(I2S_Type *base) -{ - base->CFG1 &= (~I2S_CFG1_MAINENABLE(1U)); -} - -/*! @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables I2S FIFO interrupts. - * - * @param base I2S base pointer. - * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2S_EnableInterrupts(I2S_Type *base, uint32_t interruptMask) -{ - base->FIFOINTENSET = interruptMask; -} - -/*! - * @brief Disables I2S FIFO interrupts. - * - * @param base I2S base pointer. - * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2S_DisableInterrupts(I2S_Type *base, uint32_t interruptMask) -{ - base->FIFOINTENCLR = interruptMask; -} - -/*! - * @brief Returns the set of currently enabled I2S FIFO interrupts. - * - * @param base I2S base pointer. - * - * @return A bitmask composed of #i2s_flags_t enumerators OR'd together - * to indicate the set of enabled interrupts. - */ -static inline uint32_t I2S_GetEnabledInterrupts(I2S_Type *base) -{ - return base->FIFOINTENSET; -} - -/*! - * @brief Flush the valid data in TX fifo. - * - * @param base I2S base pointer. - * @return kStatus_Fail empty TX fifo failed, kStatus_Success empty tx fifo success. - */ -status_t I2S_EmptyTxFifo(I2S_Type *base); - -/*! - * @brief Invoked from interrupt handler when transmit FIFO level decreases. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Invoked from interrupt handler when receive FIFO level decreases. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); - -/*! @} */ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2S_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s_dma.c deleted file mode 100644 index 84f25b30e91..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s_dma.c +++ /dev/null @@ -1,848 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_dma.h" -#include "fsl_i2s_dma.h" -#include "fsl_flexcomm.h" -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s_dma" -#endif - -#define DMA_MAX_TRANSFER_BYTES (DMA_MAX_TRANSFER_COUNT * sizeof(uint32_t)) -#define DMA_DESCRIPTORS (2U) - -/*i2sQueue[handle->queueUser].dataSize != 0UL) - { - /* Previously prepared buffers not processed yet, reject request */ - return kStatus_I2S_Busy; - } - - /* Enqueue data */ - privateHandle->descriptorQueue[handle->queueUser].data = transfer.data; - privateHandle->descriptorQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - return kStatus_Success; -} - -static uint32_t I2S_GetInstance(I2S_Type *base) -{ - uint32_t i; - - for (i = 0U; i < ARRAY_SIZE(s_I2sBaseAddrs); i++) - { - if ((uint32_t)base == s_I2sBaseAddrs[i]) - { - return i; - } - } - - assert(false); - return 0U; -} - -static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle) -{ - DMA_DisableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); -} - -static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle) -{ - if (handle->state != (uint32_t)kI2S_DmaStateIdle) - { - DMA_EnableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); - } -} - -/*! - * brief Initializes handle for transfer of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param dmaHandle pointer to dma handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData) -{ - assert(handle != NULL); - assert(dmaHandle != NULL); - - uint32_t instance = I2S_GetInstance(base); - i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - - (void)memset(handle, 0, sizeof(*handle)); - handle->state = (uint32_t)kI2S_DmaStateIdle; - handle->dmaHandle = dmaHandle; - handle->completionCallback = callback; - handle->userData = userData; - - handle->bytesPerFrame = (uint8_t)((((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U) / 8U); - /* if one channel is disabled, bytesPerFrame should be 4U, user should pay attention that when data length is - * shorter than 16, the data format: left data put in 0-15 bit and right data should put in 16-31 - */ - if (((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) == 0U)) - { - handle->bytesPerFrame = 4U; - } - /* since DMA do not support 24bit transfer width, use 32bit instead */ - if (handle->bytesPerFrame == 3U) - { - handle->bytesPerFrame = 4U; - } - - (void)memset(privateHandle, 0, sizeof(*privateHandle)); - privateHandle->base = base; - privateHandle->handle = handle; - - DMA_SetCallback(dmaHandle, I2S_DMACallback, privateHandle); -} - -/*! - * brief Begins or queue sending of the given data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) -{ - status_t status; - - I2S_DisableDMAInterrupts(handle); - - /* Enqueue transfer buffer */ - status = I2S_EnqueueUserBuffer(base, handle, transfer); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - - /* Initialize DMA transfer */ - if (handle->state == (uint32_t)kI2S_DmaStateIdle) - { - handle->state = (uint32_t)kI2S_DmaStateTx; - status = I2S_StartTransferDMA(base, handle); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - } - - I2S_AddTransferDMA(base, handle); - I2S_EnableDMAInterrupts(handle); - - return kStatus_Success; -} - -/*! - * brief Aborts transfer of data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - assert(handle != NULL); - assert(handle->dmaHandle != NULL); - - uint32_t instance = I2S_GetInstance(base); - i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - - I2S_DisableDMAInterrupts(handle); - - /* Abort operation */ - DMA_AbortTransfer(handle->dmaHandle); - - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - /* Disable TX */ - I2S_TxEnableDMA(base, false); - } - else - { - /* Disable RX */ - I2S_RxEnableDMA(base, false); - } - - I2S_Disable(base); - - /* Reset state */ - handle->state = (uint32_t)kI2S_DmaStateIdle; - - /* Clear transfer queue */ - (void)memset((void *)&(handle->i2sQueue), 0, sizeof(handle->i2sQueue)); - handle->queueDriver = 0U; - handle->queueUser = 0U; - - /* Clear internal state */ - (void)memset((void *)&(privateHandle->descriptorQueue), 0, sizeof(privateHandle->descriptorQueue)); - (void)memset((void *)&(privateHandle->enqueuedBytes), 0, sizeof(privateHandle->enqueuedBytes)); - privateHandle->enqueuedBytesStart = 0U; - privateHandle->enqueuedBytesEnd = 0U; - privateHandle->dmaDescriptorsUsed = 0U; - privateHandle->descriptor = 0U; - privateHandle->queueDescriptor = 0U; - privateHandle->intA = false; -} - -/*! - * brief Initializes handle for reception of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param dmaHandle pointer to dma handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData) -{ - I2S_TxTransferCreateHandleDMA(base, handle, dmaHandle, callback, userData); -} - -/*! - * brief Begins or queue reception of data into given buffer. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with buffers - * which are not full. - */ -status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) -{ - status_t status; - - I2S_DisableDMAInterrupts(handle); - - /* Enqueue transfer buffer */ - status = I2S_EnqueueUserBuffer(base, handle, transfer); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - - /* Initialize DMA transfer */ - if (handle->state == (uint32_t)kI2S_DmaStateIdle) - { - handle->state = (uint32_t)kI2S_DmaStateRx; - status = I2S_StartTransferDMA(base, handle); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - } - - I2S_AddTransferDMA(base, handle); - I2S_EnableDMAInterrupts(handle); - - return kStatus_Success; -} - -static void I2S_TxEnableDMA(I2S_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= I2S_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= (~I2S_FIFOCFG_DMATX_MASK); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - } -} - -static void I2S_RxEnableDMA(I2S_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= I2S_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= (~I2S_FIFOCFG_DMARX_MASK); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - } -} - -static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer) -{ - assert(transfer != NULL); - - uint16_t transferBytes; - - if (transfer->dataSize >= (2UL * DMA_MAX_TRANSFER_BYTES)) - { - transferBytes = DMA_MAX_TRANSFER_BYTES; - } - else if (transfer->dataSize > DMA_MAX_TRANSFER_BYTES) - { - transferBytes = (uint16_t)(transfer->dataSize / 2U); - if ((transferBytes % 4U) != 0U) - { - transferBytes -= (transferBytes % 4U); - } - } - else - { - transferBytes = (uint16_t)transfer->dataSize; - } - - return transferBytes; -} - -/*! - * brief Install DMA descriptor memory for loop transfer only. - * - * This function used to register DMA descriptor memory for the i2s loop dma transfer. - * - * It must be callbed before I2S_TransferSendLoopDMA/I2S_TransferReceiveLoopDMA and after - * I2S_RxTransferCreateHandleDMA/I2S_TxTransferCreateHandleDMA. - * - * User should be take care about the address of DMA descriptor pool which required align with 16BYTE at least. - * - * param handle Pointer to i2s DMA transfer handle. - * param dmaDescriptorAddr DMA descriptor start address. - * param dmaDescriptorNum DMA descriptor number. - */ -void I2S_TransferInstallLoopDMADescriptorMemory(i2s_dma_handle_t *handle, - void *dmaDescriptorAddr, - size_t dmaDescriptorNum) -{ - assert(handle != NULL); - assert((((uint32_t)(uint32_t *)dmaDescriptorAddr) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == - 0UL); - - handle->i2sLoopDMADescriptor = (dma_descriptor_t *)dmaDescriptorAddr; - handle->i2sLoopDMADescriptorNum = dmaDescriptorNum; -} - -static status_t I2S_TransferLoopDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - i2s_transfer_t *xfer, - uint32_t loopTransferCount) -{ - assert(handle != NULL); - assert(handle->dmaHandle != NULL); - assert(xfer != NULL); - - uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; - i2s_transfer_t *currentTransfer = xfer; - bool intA = true; - - if (handle->i2sLoopDMADescriptor == NULL) - { - return kStatus_InvalidArgument; - } - - if (handle->state == (uint32_t)kI2S_DmaStateBusyLoopTransfer) - { - return kStatus_I2S_Busy; - } - - for (uint32_t i = 0U; i < loopTransferCount; i++) - { - currentTransfer = &xfer[i]; - - if ((currentTransfer->data == NULL) || (currentTransfer->dataSize == 0U) || - (i >= handle->i2sLoopDMADescriptorNum) || - (currentTransfer->dataSize / handle->bytesPerFrame > DMA_MAX_TRANSFER_COUNT)) - { - return kStatus_InvalidArgument; - } - - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - srcAddr = (uint32_t *)(uint32_t)currentTransfer->data; - destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); - srcInc = 1U; - destInc = 0UL; - } - else - { - srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); - destAddr = (uint32_t *)(uint32_t)currentTransfer->data; - srcInc = 0U; - destInc = 1UL; - } - - intA = intA == true ? false : true; - - if (i == (loopTransferCount - 1U)) - { - /* set up linked descriptor */ - DMA_SetupDescriptor(&handle->i2sLoopDMADescriptor[i], - DMA_CHANNEL_XFER(1UL, 0UL, intA, !intA, handle->bytesPerFrame, srcInc, destInc, - currentTransfer->dataSize), - srcAddr, destAddr, &handle->i2sLoopDMADescriptor[0U]); - } - else - { - /* set up linked descriptor */ - DMA_SetupDescriptor(&handle->i2sLoopDMADescriptor[i], - DMA_CHANNEL_XFER(1UL, 0UL, intA, !intA, handle->bytesPerFrame, srcInc, destInc, - currentTransfer->dataSize), - srcAddr, destAddr, &handle->i2sLoopDMADescriptor[i + 1U]); - } - } - - /* transferSize make sense to non link transfer only */ - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - srcAddr = (uint32_t *)(uint32_t)xfer->data; - destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); - srcInc = 1U; - destInc = 0UL; - } - else - { - srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); - destAddr = (uint32_t *)(uint32_t)xfer->data; - srcInc = 0U; - destInc = 1UL; - } - - DMA_SubmitChannelTransferParameter( - handle->dmaHandle, - DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 1UL, handle->bytesPerFrame, srcInc, destInc, (uint32_t)xfer->dataSize), srcAddr, - destAddr, (void *)&handle->i2sLoopDMADescriptor[1U]); - - /* Submit and start initial DMA transfer */ - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - I2S_TxEnableDMA(base, true); - } - else - { - I2S_RxEnableDMA(base, true); - } - DMA_EnableChannelPeriphRq(handle->dmaHandle->base, handle->dmaHandle->channel); - /* start transfer */ - DMA_StartTransfer(handle->dmaHandle); - I2S_Enable(base); - - handle->state = (uint32_t)kI2S_DmaStateBusyLoopTransfer; - - return kStatus_Success; -} - -/*! - * brief Send loop transfer data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * This function support loop transfer, such as A->B->...->A, the loop transfer chain - * will be converted into a chain of descriptor and submit to dma. - * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, - * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. - * - * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support - * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop - * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. - * - * param base I2S peripheral base address. - * param handle Pointer to usart_dma_handle_t structure. - * param xfer I2S DMA transfer structure. See #i2s_transfer_t. - * param i2s_channel I2S start channel number - * retval kStatus_Success - */ -status_t I2S_TransferSendLoopDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - i2s_transfer_t *xfer, - uint32_t loopTransferCount) -{ - assert(handle != NULL); - assert(handle->i2sLoopDMADescriptor != NULL); - - handle->state = (uint32_t)kI2S_DmaStateTx; - - return I2S_TransferLoopDMA(base, handle, xfer, loopTransferCount); -} - -/*! - * brief Receive loop transfer data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * This function support loop transfer, such as A->B->...->A, the loop transfer chain - * will be converted into a chain of descriptor and submit to dma. - * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, - * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. - * - * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support - * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop - * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. - * - * param base I2S peripheral base address. - * param handle Pointer to usart_dma_handle_t structure. - * param xfer I2S DMA transfer structure. See #i2s_transfer_t. - * param i2s_channel I2S start channel number - * retval kStatus_Success - */ -status_t I2S_TransferReceiveLoopDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - i2s_transfer_t *xfer, - uint32_t loopTransferCount) -{ - assert(handle != NULL); - assert(handle->i2sLoopDMADescriptor != NULL); - - handle->state = (uint32_t)kI2S_DmaStateRx; - - return I2S_TransferLoopDMA(base, handle, xfer, loopTransferCount); -} - -static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - uint32_t instance = I2S_GetInstance(base); - i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - volatile i2s_transfer_t *transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); - uint16_t transferBytes = I2S_GetTransferBytes(transfer); - uint32_t i = 0U; - uint32_t xferConfig = 0U; - uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; - - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - srcAddr = (uint32_t *)(uint32_t)transfer->data; - destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); - srcInc = 1U; - destInc = 0UL; - } - else - { - srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); - destAddr = (uint32_t *)(uint32_t)transfer->data; - srcInc = 0U; - destInc = 1UL; - } - /* Initial descriptor is stored in another place in memory, but treat it as another descriptor for simplicity */ - privateHandle->dmaDescriptorsUsed = 1U; - privateHandle->intA = false; - - /* submit transfer parameter directly */ - xferConfig = DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 1UL, handle->bytesPerFrame, srcInc, destInc, (uint32_t)transferBytes); - - DMA_SubmitChannelTransferParameter(handle->dmaHandle, xferConfig, srcAddr, destAddr, - (void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U])); - - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; - privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; - - transfer->dataSize -= transferBytes; - transfer->data = (uint8_t *)((uint32_t)transfer->data + transferBytes); - - if (transfer->dataSize == 0U) - { - transfer->data = NULL; - privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; - } - - /* Link the DMA descriptors for the case when no additional transfer is queued before the initial one finishes - * The configuration for the DMA dummy descriptor make no sense to tx or rx transfer, since it will be overwritten - * when another transfer request comes before the previous finished. - * To make sure the audio data transfer continuously, application must request another transfer by call - * I2S_RxTransferReceiveDMA or I2S_TxTransferSendDMA before previous transfer finished. - */ - for (i = 0; i < DMA_DESCRIPTORS; i++) - { - /* DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 0UL, sizeof(uint32_t), 0U, 0U, 8U) = 0x10203UL */ - DMA_SetupDescriptor( - &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + i]), 0x10203UL, - ((handle->state == (uint32_t)kI2S_DmaStateTx) ? &s_DummyBufferTx : (uint32_t *)(uint32_t)(&(base->FIFORD))), - ((handle->state == (uint32_t)kI2S_DmaStateTx) ? (uint32_t *)(uint32_t)(&(base->FIFOWR)) : &s_DummyBufferRx), - &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + ((i + 1U) % DMA_DESCRIPTORS)])); - } - - /* Submit and start initial DMA transfer */ - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - I2S_TxEnableDMA(base, true); - } - else - { - I2S_RxEnableDMA(base, true); - } - /* enable I2S peripheral request and put the channel into triggered status */ - DMA_EnableChannelPeriphRq(handle->dmaHandle->base, handle->dmaHandle->channel); - DMA_StartTransfer(handle->dmaHandle); - - I2S_Enable(base); - - return kStatus_Success; -} - -static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - volatile i2s_transfer_t *transfer; - uint16_t transferBytes; - uint32_t instance; - i2s_dma_private_handle_t *privateHandle; - dma_descriptor_t *descriptor; - dma_descriptor_t *nextDescriptor; - uint32_t xferConfig = 0U; - bool intA = false; - uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; - - instance = I2S_GetInstance(base); - privateHandle = &(s_DmaPrivateHandle[instance]); - - while (privateHandle->dmaDescriptorsUsed < DMA_DESCRIPTORS) - { - transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); - intA = privateHandle->intA; - if (transfer->dataSize == 0U) - { - /* Nothing to be added */ - return; - } - - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - srcAddr = (uint32_t *)(uint32_t)transfer->data; - destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); - srcInc = 1U; - destInc = 0UL; - } - else - { - srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); - destAddr = (uint32_t *)(uint32_t)transfer->data; - srcInc = 0U; - destInc = 1UL; - } - - /* Determine currently configured descriptor and the other which it will link to */ - descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); - privateHandle->descriptor = (privateHandle->descriptor + 1U) % DMA_DESCRIPTORS; - nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); - - transferBytes = I2S_GetTransferBytes(transfer); - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; - privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; - - xferConfig = - DMA_CHANNEL_XFER(1UL, 0UL, !intA, intA, handle->bytesPerFrame, srcInc, destInc, (uint32_t)transferBytes); - - DMA_SetupDescriptor(descriptor, xferConfig, srcAddr, destAddr, nextDescriptor); - - /* Advance internal state */ - privateHandle->dmaDescriptorsUsed++; - privateHandle->intA = !privateHandle->intA; - - transfer->dataSize -= transferBytes; - transfer->data += transferBytes; - if (transfer->dataSize == 0U) - { - transfer->data = NULL; - privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; - } - } -} - -/*! - * brief Invoked from DMA interrupt handler. - * - * param handle pointer to DMA handle structure. - * param userData argument for user callback. - * param transferDone if transfer was done. - * param tcds - */ -void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds) -{ - i2s_dma_private_handle_t *privateHandle = (i2s_dma_private_handle_t *)userData; - i2s_dma_handle_t *i2sHandle = privateHandle->handle; - I2S_Type *base = privateHandle->base; - uint8_t queueDriverIndex = i2sHandle->queueDriver; - uint32_t enqueueBytes = privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart]; - uint32_t queueDataAddr = (uint32_t)i2sHandle->i2sQueue[queueDriverIndex].data; - - if ((!transferDone) || (i2sHandle->state == (uint32_t)kI2S_DmaStateIdle)) - { - return; - } - - if (privateHandle->dmaDescriptorsUsed > 0U) - { - /* Finished descriptor, decrease amount of data to be processed */ - - i2sHandle->i2sQueue[queueDriverIndex].dataSize -= enqueueBytes; - i2sHandle->i2sQueue[queueDriverIndex].data = (uint8_t *)(queueDataAddr + enqueueBytes); - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] = 0U; - privateHandle->enqueuedBytesStart = (privateHandle->enqueuedBytesStart + 1U) % DMA_DESCRIPTORS; - privateHandle->dmaDescriptorsUsed--; - } - - if (i2sHandle->i2sQueue[queueDriverIndex].dataSize == 0U) - { - /* Entire user buffer sent or received - advance to next one */ - i2sHandle->i2sQueue[queueDriverIndex].data = NULL; - i2sHandle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; - /* Notify user about buffer completion */ - if (i2sHandle->completionCallback != NULL) - { - (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_BufferComplete, i2sHandle->userData); - } - } - - if (i2sHandle->state != (uint32_t)kI2S_DmaStateBusyLoopTransfer) - { - /* check next buffer queue is avaliable or not */ - if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U) - { - if (i2sHandle->state == (uint32_t)kI2S_DmaStateTx) - { - (void)I2S_EmptyTxFifo(base); - } - /* All user buffers processed */ - I2S_TransferAbortDMA(base, i2sHandle); - } - else - { - /* Enqueue another user buffer to DMA if it could not be done when in I2S_Rx/TxTransferSendDMA */ - I2S_AddTransferDMA(base, i2sHandle); - } - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s_dma.h deleted file mode 100644 index ec63472653a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s_dma.h +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2S_DMA_H_ -#define _FSL_I2S_DMA_H_ - -#include "fsl_device_registers.h" -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -#include "fsl_dma.h" -#include "fsl_i2s.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup i2s_dma_driver - * @{ - */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2S DMA driver version 2.3.1. */ -#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) -/*@}*/ - -/*! @brief Members not to be accessed / modified outside of the driver. */ -typedef struct _i2s_dma_handle i2s_dma_handle_t; - -/*! - * @brief Callback function invoked from DMA API on completion. - * - * @param base I2S base pointer. - * @param handle pointer to I2S transaction. - * @param completionStatus status of the transaction. - * @param userData optional pointer to user arguments data. - */ -typedef void (*i2s_dma_transfer_callback_t)(I2S_Type *base, - i2s_dma_handle_t *handle, - status_t completionStatus, - void *userData); -/*! @brief i2s dma handle */ -struct _i2s_dma_handle -{ - uint32_t state; /*!< Internal state of I2S DMA transfer */ - uint8_t bytesPerFrame; /*!< bytes per frame */ - i2s_dma_transfer_callback_t completionCallback; /*!< Callback function pointer */ - void *userData; /*!< Application data passed to callback */ - dma_handle_t *dmaHandle; /*!< DMA handle */ - volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ - volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ - volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ - - dma_descriptor_t *i2sLoopDMADescriptor; /*!< descriptor pool pointer */ - size_t i2sLoopDMADescriptorNum; /*!< number of descriptor in descriptors pool */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! @} */ - -/*! - * @name DMA API - * @{ - */ - -/*! - * @brief Initializes handle for transfer of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param dmaHandle pointer to dma handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData); - -/*! - * @brief Begins or queue sending of the given data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts transfer of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle); - -/*! - * @brief Initializes handle for reception of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param dmaHandle pointer to dma handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData); - -/*! - * @brief Begins or queue reception of data into given buffer. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers - * which are not full. - */ -status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Invoked from DMA interrupt handler. - * - * @param handle pointer to DMA handle structure. - * @param userData argument for user callback. - * @param transferDone if transfer was done. - * @param tcds - */ -void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds); - -/*! - * @brief Install DMA descriptor memory for loop transfer only. - * - * This function used to register DMA descriptor memory for the i2s loop dma transfer. - * - * It must be callbed before I2S_TransferSendLoopDMA/I2S_TransferReceiveLoopDMA and after - * I2S_RxTransferCreateHandleDMA/I2S_TxTransferCreateHandleDMA. - * - * User should be take care about the address of DMA descriptor pool which required align with 16BYTE at least. - * - * @param handle Pointer to i2s DMA transfer handle. - * @param dmaDescriptorAddr DMA descriptor start address. - * @param dmaDescriptorNum DMA descriptor number. - */ -void I2S_TransferInstallLoopDMADescriptorMemory(i2s_dma_handle_t *handle, - void *dmaDescriptorAddr, - size_t dmaDescriptorNum); - -/*! - * @brief Send link transfer data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * This function support loop transfer, such as A->B->...->A, the loop transfer chain - * will be converted into a chain of descriptor and submit to dma. - * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, - * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. - * - * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support - * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop - * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. - * - * @param base I2S peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param xfer I2S DMA transfer structure. See #i2s_transfer_t. - * @param loopTransferCount loop count - * @retval kStatus_Success - */ -status_t I2S_TransferSendLoopDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - i2s_transfer_t *xfer, - uint32_t loopTransferCount); - -/*! - * @brief Receive link transfer data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * This function support loop transfer, such as A->B->...->A, the loop transfer chain - * will be converted into a chain of descriptor and submit to dma. - * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, - * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. - * - * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support - * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop - * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. - * - * @param base I2S peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param xfer I2S DMA transfer structure. See #i2s_transfer_t. - * @param loopTransferCount loop count - * @retval kStatus_Success - */ -status_t I2S_TransferReceiveLoopDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - i2s_transfer_t *xfer, - uint32_t loopTransferCount); - -/*! @} */ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2S_DMA_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap.c deleted file mode 100644 index 712b0faef71..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap.c +++ /dev/null @@ -1,666 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "fsl_iap.h" -#include "fsl_iap_ffr.h" -#include "fsl_iap_kbp.h" -#include "fsl_iap_skboot_authenticate.h" -#include "fsl_device_registers.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.iap1" -#endif - -#if (defined(LPC5512_SERIES) || defined(LPC5514_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ - defined(LPC55S16_SERIES) || defined(LPC5524_SERIES) || defined(LPC5502_SERIES) || defined(LPC5504_SERIES) || \ - defined(LPC5506_SERIES) || defined(LPC55S04_SERIES) || defined(LPC55S06_SERIES)) - -#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1301fe00U) - -#elif (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || defined(LPC5526_SERIES) || \ - defined(LPC55S26_SERIES) || defined(LPC5528_SERIES) || defined(LPC55S28_SERIES) || \ - defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES)) - -#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x130010f0U) - -#else -#error "No valid CPU defined!" - -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -static status_t get_cfpa_higher_version(flash_config_t *config); - -/*! - * @name flash and ffr Structure - * @{ - */ - -typedef union functionCommandOption -{ - uint32_t commandAddr; - status_t (*eraseCommand)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - status_t (*programCommand)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); - status_t (*verifyProgramCommand)(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - status_t (*flashReadCommand)(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); -} function_command_option_t; - -/* - *!@brief Structure of version property. - * - *!@ingroup bl_core - */ -typedef union StandardVersion -{ - struct - { - uint32_t bugfix : 8; /*!< bugfix version [7:0] */ - uint32_t minor : 8; /*!< minor version [15:8] */ - uint32_t major : 8; /*!< major version [23:16] */ - uint32_t name : 8; /*!< name [31:24] */ - }; - uint32_t version; /*!< combined version numbers. */ -#if defined(__cplusplus) - StandardVersion() : version(0) - { - } - StandardVersion(uint32_t version) : version(version) - { - } -#endif -} standard_version_t; - -/*! @brief Interface for the flash driver.*/ -typedef struct version1FlashDriverInterface -{ - standard_version_t version; /*!< flash driver API version number.*/ - - /*!< Flash driver.*/ - status_t (*flash_init)(flash_config_t *config); - status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); - status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); - status_t (*flash_verify_program)(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); - uint32_t reserved[3]; /*! Reserved for future use */ - /*!< Flash FFR driver*/ - status_t (*ffr_init)(flash_config_t *config); - status_t (*ffr_lock_all)(flash_config_t *config); - status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); - status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); - status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); - status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode); - status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); - status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); - status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); -} version1_flash_driver_interface_t; - -/*! @brief Interface for the flash driver.*/ -typedef struct version0FlashDriverInterface -{ - standard_version_t version; /*!< flash driver API version number.*/ - - /*!< Flash driver.*/ - status_t (*flash_init)(flash_config_t *config); - status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); - status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); - status_t (*flash_verify_program)(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); - - /*!< Flash FFR driver*/ - status_t (*ffr_init)(flash_config_t *config); - status_t (*ffr_lock_all)(flash_config_t *config); - status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); - status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); - status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); - status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode); - status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); - status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); - status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); -} version0_flash_driver_interface_t; - -typedef union flashDriverInterface -{ - const version1_flash_driver_interface_t *version1FlashDriver; - const version0_flash_driver_interface_t *version0FlashDriver; -} flash_driver_interface_t; - -/*! @}*/ - -/*! - * @name Bootloader API and image authentication Structure - * @{ - */ - -/*! @brief Interface for Bootloader API functions. */ -typedef struct _kb_interface -{ - /*!< Initialize the API. */ - status_t (*kb_init_function)(kb_session_ref_t **session, const kb_options_t *options); - status_t (*kb_deinit_function)(kb_session_ref_t *session); - status_t (*kb_execute_function)(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength); -} kb_interface_t; - -//! @brief Interface for image authentication API -typedef struct _skboot_authenticate_interface -{ - skboot_status_t (*skboot_authenticate_function)(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified); - void (*skboot_hashcrypt_irq_handler)(void); -} skboot_authenticate_interface_t; -/*! @}*/ - -/*! - * @brief Root of the bootloader API tree. - * - * An instance of this struct resides in read-only memory in the bootloader. It - * provides a user application access to APIs exported by the bootloader. - * - * @note The order of existing fields must not be changed. - */ -typedef struct BootloaderTree -{ - void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing. */ - standard_version_t bootloader_version; /*!< Bootloader version number. */ - const char *copyright; /*!< Copyright string. */ - const uint32_t reserved0; /*!< Do NOT use. */ - flash_driver_interface_t flashDriver; - const kb_interface_t *kbApi; /*!< Bootloader API. */ - const uint32_t reserved1[4]; /*!< Do NOT use. */ - const skboot_authenticate_interface_t *skbootAuthenticate; /*!< Image authentication API. */ -} bootloader_tree_t; - -/******************************************************************************* - * Prototype - ******************************************************************************/ -static uint32_t get_rom_api_version(void); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! Get pointer to flash driver API table in ROM. */ -#define VERSION1_FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver.version1FlashDriver -#define VERSION0_FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver.version0FlashDriver -#define LPC55S69_REV0_FLASH_READ_ADDR (0x130043a3U) -#define LPC55S69_REV1_FLASH_READ_ADDR (0x13007539U) -#define LPC55S16_REV0_FLASH_READ_ADDR (0x1300ade5U) - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t get_rom_api_version(void) -{ - if (BOOTLOADER_API_TREE_POINTER->bootloader_version.major == 3u) - { - return 1u; - } - else - { - return 0u; - } -} - -/*! - * @brief Initializes the global flash properties structure members. - * - * This function checks and initializes the Flash module for the other Flash APIs. - */ -status_t FLASH_Init(flash_config_t *config) -{ - status_t status; - /* Initialize the clock to 96MHz */ - config->modeConfig.sysFreqInMHz = (uint32_t)kSysToFlashFreq_defaultInMHz; - if (get_rom_api_version() == 1u) - { - status = VERSION1_FLASH_API_TREE->flash_init(config); - } - else - { - status = VERSION0_FLASH_API_TREE->flash_init(config); - } - - if (config->PFlashTotalSize == 0xA0000U) - { - config->PFlashTotalSize -= 17U * config->PFlashPageSize; - } - - return status; -} - -/*! - * @brief Erases the flash sectors encompassed by parameters passed into function. - * - * This function erases the appropriate number of flash sectors based on the - * desired start address and length. - */ -status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) -{ - if (get_rom_api_version() == 0u) - { - function_command_option_t runCmdFuncOption; - runCmdFuncOption.commandAddr = 0x1300413bU; /*!< get the flash erase api location adress in rom */ - return runCmdFuncOption.eraseCommand(config, start, lengthInBytes, key); - } - else - { - return VERSION1_FLASH_API_TREE->flash_erase(config, start, lengthInBytes, key); - } -} - -/*! See fsl_iap.h for documentation of this function. */ -status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) -{ - if (get_rom_api_version() == 0u) - { - function_command_option_t runCmdFuncOption; - runCmdFuncOption.commandAddr = 0x1300419dU; /*!< get the flash program api location adress in rom*/ - return runCmdFuncOption.programCommand(config, start, src, lengthInBytes); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->flash_program(config, start, src, lengthInBytes); - } -} - -/*! See fsl_iap.h for documentation of this function. */ -status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes) -{ - if (get_rom_api_version() == 0u) - { - /*!< get the flash read api location adress in rom*/ - function_command_option_t runCmdFuncOption; - runCmdFuncOption.commandAddr = LPC55S69_REV0_FLASH_READ_ADDR; - return runCmdFuncOption.flashReadCommand(config, start, dest, lengthInBytes); - } - else - { - /*!< get the flash read api location adress in rom*/ - function_command_option_t runCmdFuncOption; - if ((SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK) != 0u) - { - runCmdFuncOption.commandAddr = LPC55S69_REV1_FLASH_READ_ADDR; - } - else - { - runCmdFuncOption.commandAddr = LPC55S16_REV0_FLASH_READ_ADDR; - } - return runCmdFuncOption.flashReadCommand(config, start, dest, lengthInBytes); - } -} - -/*! See fsl_iap.h for documentation of this function. */ -status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) -{ - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->flash_verify_erase(config, start, lengthInBytes); -} - -/*! - * @brief Verifies programming of the desired flash area at a specified margin level. - * - * This function verifies the data programed in the flash memory using the - * Flash Program Check Command and compares it to the expected data for a given - * flash area as determined by the start address and length. - */ -status_t FLASH_VerifyProgram(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData) -{ - if (get_rom_api_version() == 0u) - { - function_command_option_t runCmdFuncOption; - runCmdFuncOption.commandAddr = 0x1300427dU; /*!< get the flash verify program api location adress in rom*/ - return runCmdFuncOption.verifyProgramCommand(config, start, lengthInBytes, expectedData, failedAddress, - failedData); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->flash_verify_program(config, start, lengthInBytes, expectedData, failedAddress, - failedData); - } -} - -/*! - * @brief Returns the desired flash property. - */ -status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) -{ - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->flash_get_property(config, whichProperty, value); -} -/******************************************************************************** - * fsl iap ffr CODE - *******************************************************************************/ - -static status_t get_cfpa_higher_version(flash_config_t *config) -{ - uint32_t pageData[FLASH_FFR_MAX_PAGE_SIZE / sizeof(uint32_t)]; - uint32_t versionPing = 0U; - uint32_t versionPong = 0U; - - /* Get the CFPA ping page data and the corresponding version */ - config->ffrConfig.cfpaPageOffset = 1U; - status_t status = FFR_GetCustomerInfieldData(config, (uint8_t *)pageData, 0U, FLASH_FFR_MAX_PAGE_SIZE); - if (status != (int32_t)kStatus_FLASH_Success) - { - return status; - } - versionPing = pageData[1]; - - /* Get the CFPA pong page data and the corresponding version */ - config->ffrConfig.cfpaPageOffset = 2U; - status = FFR_GetCustomerInfieldData(config, (uint8_t *)pageData, 0U, FLASH_FFR_MAX_PAGE_SIZE); - if (status != (int32_t)kStatus_FLASH_Success) - { - return status; - } - versionPong = pageData[1]; - - /* Compare the CFPA ping version and pong version and set it correctly in flash_config structure */ - if (versionPing > versionPong) - { - config->ffrConfig.cfpaPageVersion = versionPing; - config->ffrConfig.cfpaPageOffset = 1U; - } - else - { - config->ffrConfig.cfpaPageVersion = versionPong; - config->ffrConfig.cfpaPageOffset = 2U; - } - return (int32_t)kStatus_FLASH_Success; -} - -/*! - * Initializes the global FFR properties structure members. - */ -status_t FFR_Init(flash_config_t *config) -{ - status_t status; - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - status = VERSION0_FLASH_API_TREE->ffr_init(config); - if (status != (status_t)kStatus_FLASH_Success) - { - return status; - } - return get_cfpa_higher_version(config); - } - else - { - assert(VERSION1_FLASH_API_TREE); - status = VERSION1_FLASH_API_TREE->ffr_init(config); - if (status != (status_t)kStatus_FLASH_Success) - { - return status; - } - return get_cfpa_higher_version(config); - } -} - -/*! - * Enable firewall for all flash banks. - */ -status_t FFR_Lock_All(flash_config_t *config) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_lock_all(config); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_lock_all(config); - } -} - -/*! - * APIs to access CMPA pages; - * This routine will erase "customer factory page" and program the page with passed data. - */ -status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part); - } -} - -/*! - * See fsl_iap_ffr.h for documentation of this function. - */ -status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_get_uuid(config, uuid); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_get_uuid(config, uuid); - } -} - -/*! - * APIs to access CMPA pages - * Read data stored in 'Customer Factory CFG Page'. - */ -status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len); - } -} - -/*! - * This routine writes the 3 pages allocated for Key store data, - * Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state. - */ -status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_keystore_write(config, pKeyStore); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_keystore_write(config, pKeyStore); - } -} - -/*! See fsl_iap_ffr.h for documentation of this function. */ -status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode); - } -} - -/*! See fsl_iap_ffr.h for documentation of this function. */ -status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex); - } -} - -/*! - * APIs to access CFPA pages - * This routine will erase CFPA and program the CFPA page with passed data. - */ -status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len); - } -} - -/*! - * APIs to access CFPA pages - * Generic read function, used by customer to read data stored in 'Customer In-field Page'. - */ -status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len); - } -} - -/******************************************************************************** - * Bootloader API - *******************************************************************************/ -/*! - * @brief Initialize ROM API for a given operation. - * - * Inits the ROM API based on the options provided by the application in the second - * argument. Every call to rom_init() should be paired with a call to rom_deinit(). - */ -status_t kb_init(kb_session_ref_t **session, const kb_options_t *options) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->kbApi->kb_init_function(session, options); -} - -/*! - * @brief Cleans up the ROM API context. - * - * After this call, the @a context parameter can be reused for another operation - * by calling rom_init() again. - */ -status_t kb_deinit(kb_session_ref_t *session) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->kbApi->kb_deinit_function(session); -} - -/*! - * Perform the operation configured during init. - * - * This application must call this API repeatedly, passing in sequential chunks of - * data from the boot image (SB file) that is to be processed. The ROM will perform - * the selected operation on this data and return. The application may call this - * function with as much or as little data as it wishes, which can be used to select - * the granularity of time given to the application in between executing the operation. - * - * @param context Current ROM context pointer. - * @param data Buffer of boot image data provided to the ROM by the application. - * @param dataLength Length in bytes of the data in the buffer provided to the ROM. - * - * @retval #kStatus_Success The operation has completed successfully. - * @retval #kStatus_Fail An error occurred while executing the operation. - * @retval #kStatus_RomApiNeedMoreData No error occurred, but the ROM needs more data to - * continue processing the boot image. - */ -status_t kb_execute(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->kbApi->kb_execute_function(session, data, dataLength); -} - -/******************************************************************************** - * Image authentication API - *******************************************************************************/ - -/*! - * @brief Authenticate entry function with ARENA allocator init - * - * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface - */ -skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->skbootAuthenticate->skboot_authenticate_function(imageStartAddr, - isSignVerified); -} - -/*! - * @brief Interface for image authentication API - */ -void HASH_IRQHandler(void) -{ - assert(BOOTLOADER_API_TREE_POINTER); - BOOTLOADER_API_TREE_POINTER->skbootAuthenticate->skboot_hashcrypt_irq_handler(); -} -/******************************************************************************** - * EOF - *******************************************************************************/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap.h deleted file mode 100644 index f7b318b66bd..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap.h +++ /dev/null @@ -1,528 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __FSL_IAP_H_ -#define __FSL_IAP_H_ - -#include "fsl_common.h" -/*! - * @addtogroup flash_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! - * @name Flash version - * @{ - */ -/*! @brief Constructs the version number for drivers. */ -#if !defined(MAKE_VERSION) -#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) -#endif - -/*! @brief Flash driver version for SDK*/ -#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4. */ - -/*! @brief Flash driver version for ROM*/ -enum _flash_driver_version_constants -{ - kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ - kFLASH_DriverVersionMajor = 2, /*!< Major flash driver version.*/ - kFLASH_DriverVersionMinor = 1, /*!< Minor flash driver version.*/ - kFLASH_DriverVersionBugfix = 3 /*!< Bugfix for flash driver version.*/ -}; - -/*@}*/ - -/*! - * @name Flash configuration - * @{ - */ -/*! @brief Flash IP Type. */ -#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC) -#define FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC (1) -#endif -#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_FC) -#define FSL_FEATURE_FLASH_IP_IS_C040HD_FC (0) -#endif - -/*! - * @name Flash status - * @{ - */ -/*! @brief Flash driver status group. */ -#if defined(kStatusGroup_FlashDriver) -#define kStatusGroupGeneric kStatusGroup_Generic -#define kStatusGroupFlashDriver kStatusGroup_FlashDriver -#elif defined(kStatusGroup_FLASHIAP) -#define kStatusGroupGeneric kStatusGroup_Generic -#define kStatusGroupFlashDriver kStatusGroup_FLASH -#else -#define kStatusGroupGeneric 0 -#define kStatusGroupFlashDriver 1 -#endif - -/*! @brief Constructs a status code value from a group and a code number. */ -#if !defined(MAKE_STATUS) -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) -#endif - -/*! - * @brief Flash driver status codes. - */ -enum _flash_status -{ - kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ - kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ - kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ - kStatus_FLASH_AlignmentError = - MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ - kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ - kStatus_FLASH_AccessError = - MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ - kStatus_FLASH_ProtectionViolation = MAKE_STATUS( - kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ - kStatus_FLASH_CommandFailure = - MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ - kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ - kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/ - kStatus_FLASH_RegionExecuteOnly = - MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/ - kStatus_FLASH_ExecuteInRamFunctionNotReady = - MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/ - - kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Flash API is not supported.*/ - kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< The flash property is read-only.*/ - kStatus_FLASH_InvalidPropertyValue = - MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< The flash property value is out of range.*/ - kStatus_FLASH_InvalidSpeculationOption = - MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< The option of flash prefetch speculation is invalid.*/ - kStatus_FLASH_EccError = MAKE_STATUS(kStatusGroupFlashDriver, - 0x10), /*!< A correctable or uncorrectable error during command execution. */ - kStatus_FLASH_CompareError = - MAKE_STATUS(kStatusGroupFlashDriver, 0x11), /*!< Destination and source memory contents do not match. */ - kStatus_FLASH_RegulationLoss = MAKE_STATUS(kStatusGroupFlashDriver, 0x12), /*!< A loss of regulation during read. */ - kStatus_FLASH_InvalidWaitStateCycles = - MAKE_STATUS(kStatusGroupFlashDriver, 0x13), /*!< The wait state cycle set to r/w mode is invalid. */ - - kStatus_FLASH_OutOfDateCfpaPage = - MAKE_STATUS(kStatusGroupFlashDriver, 0x20), /*!< CFPA page version is out of date. */ - kStatus_FLASH_BlankIfrPageData = MAKE_STATUS(kStatusGroupFlashDriver, 0x21), /*!< Blank page cannnot be read. */ - kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce = - MAKE_STATUS(kStatusGroupFlashDriver, 0x22), /*!< Encrypted flash subregions are not erased at once. */ - kStatus_FLASH_ProgramVerificationNotAllowed = MAKE_STATUS( - kStatusGroupFlashDriver, 0x23), /*!< Program verification is not allowed when the encryption is enabled. */ - kStatus_FLASH_HashCheckError = - MAKE_STATUS(kStatusGroupFlashDriver, 0x24), /*!< Hash check of page data is failed. */ - kStatus_FLASH_SealedFfrRegion = MAKE_STATUS(kStatusGroupFlashDriver, 0x25), /*!< The FFR region is sealed. */ - kStatus_FLASH_FfrRegionWriteBroken = MAKE_STATUS( - kStatusGroupFlashDriver, 0x26), /*!< The FFR Spec region is not allowed to be written discontinuously. */ - kStatus_FLASH_NmpaAccessNotAllowed = - MAKE_STATUS(kStatusGroupFlashDriver, 0x27), /*!< The NMPA region is not allowed to be read/written/erased. */ - kStatus_FLASH_CmpaCfgDirectEraseNotAllowed = - MAKE_STATUS(kStatusGroupFlashDriver, 0x28), /*!< The CMPA Cfg region is not allowed to be erased directly. */ - kStatus_FLASH_FfrBankIsLocked = MAKE_STATUS(kStatusGroupFlashDriver, 0x29), /*!< The FFR bank region is locked. */ -}; -/*@}*/ - -/*! - * @name Flash API key - * @{ - */ -/*! @brief Constructs the four character code for the Flash driver API key. */ -#if !defined(FOUR_CHAR_CODE) -#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) -#endif - -/*! - * @brief Enumeration for Flash driver API keys. - * - * @note The resulting value is built with a byte order such that the string - * being readable in expected order when viewed in a hex editor, if the value - * is treated as a 32-bit little endian value. - */ -enum _flash_driver_api_keys -{ - kFLASH_ApiEraseKey = FOUR_CHAR_CODE('l', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ -}; -/*@}*/ - -/*! - * @brief Enumeration for various flash properties. - */ -typedef enum _flash_property_tag -{ - kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ - kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ - kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ - kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ - kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ - - kFLASH_PropertyPflashPageSize = 0x30U, /*!< Pflash page size property.*/ - kFLASH_PropertyPflashSystemFreq = 0x31U, /*!< System Frequency System Frequency.*/ - - kFLASH_PropertyFfrSectorSize = 0x40U, /*!< FFR sector size property.*/ - kFLASH_PropertyFfrTotalSize = 0x41U, /*!< FFR total size property.*/ - kFLASH_PropertyFfrBlockBaseAddr = 0x42U, /*!< FFR block base address property.*/ - kFLASH_PropertyFfrPageSize = 0x43U, /*!< FFR page size property.*/ -} flash_property_tag_t; - -/*! - * @brief Enumeration for flash max pages to erase. - */ -enum _flash_max_erase_page_value -{ - kFLASH_MaxPagesToErase = 100U /*!< The max value in pages to erase. */ -}; - -/*! - * @brief Enumeration for flash alignment property. - */ -enum _flash_alignment_property -{ - kFLASH_AlignementUnitVerifyErase = 4, /*!< The alignment unit in bytes used for verify erase operation.*/ - kFLASH_AlignementUnitProgram = 512, /*!< The alignment unit in bytes used for program operation.*/ - /*kFLASH_AlignementUnitVerifyProgram = 4,*/ /*!< The alignment unit in bytes used for verify program operation.*/ - kFLASH_AlignementUnitSingleWordRead = 16 /*!< The alignment unit in bytes used for SingleWordRead command.*/ -}; - -/*! - * @brief Enumeration for flash read ecc option - */ -enum _flash_read_ecc_option -{ - kFLASH_ReadWithEccOn = 0, /*! ECC is on */ - kFLASH_ReadWithEccOff = 1, /*! ECC is off */ -}; - -/* set flash Controller timing before flash init */ -enum _flash_freq_tag -{ - kSysToFlashFreq_lowInMHz = 12u, - kSysToFlashFreq_defaultInMHz = 96u, -}; - -/*! - * @brief Enumeration for flash read margin option - */ -enum _flash_read_margin_option -{ - kFLASH_ReadMarginNormal = 0, /*!< Normal read */ - kFLASH_ReadMarginVsProgram = 1, /*!< Margin vs. program */ - kFLASH_ReadMarginVsErase = 2, /*!< Margin vs. erase */ - kFLASH_ReadMarginIllegalBitCombination = 3 /*!< Illegal bit combination */ -}; - -/*! - * @brief Enumeration for flash read dmacc option - */ -enum _flash_read_dmacc_option -{ - kFLASH_ReadDmaccDisabled = 0, /*!< Memory word */ - kFLASH_ReadDmaccEnabled = 1, /*!< DMACC word */ -}; - -/*! - * @brief Enumeration for flash ramp control option - */ -enum _flash_ramp_control_option -{ - kFLASH_RampControlDivisionFactorReserved = 0, /*!< Reserved */ - kFLASH_RampControlDivisionFactor256 = 1, /*!< clk48mhz / 256 = 187.5KHz */ - kFLASH_RampControlDivisionFactor128 = 2, /*!< clk48mhz / 128 = 375KHz */ - kFLASH_RampControlDivisionFactor64 = 3 /*!< clk48mhz / 64 = 750KHz */ -}; - -/*! @brief Flash ECC log info. */ -typedef struct _flash_ecc_log -{ - uint32_t firstEccEventAddress; - uint32_t eccErrorCount; - uint32_t eccCorrectionCount; - uint32_t reserved; -} flash_ecc_log_t; - -/*! @brief Flash controller paramter config. */ -typedef struct _flash_mode_config -{ - uint32_t sysFreqInMHz; - /* ReadSingleWord parameter. */ - struct - { - uint8_t readWithEccOff : 1; - uint8_t readMarginLevel : 2; - uint8_t readDmaccWord : 1; - uint8_t reserved0 : 4; - uint8_t reserved1[3]; - } readSingleWord; - /* SetWriteMode parameter. */ - struct - { - uint8_t programRampControl; - uint8_t eraseRampControl; - uint8_t reserved[2]; - } setWriteMode; - /* SetReadMode parameter. */ - struct - { - uint16_t readInterfaceTimingTrim; - uint16_t readControllerTimingTrim; - uint8_t readWaitStates; - uint8_t reserved[3]; - } setReadMode; -} flash_mode_config_t; - -/*! @brief Flash controller paramter config. */ -typedef struct _flash_ffr_config -{ - uint32_t ffrBlockBase; - uint32_t ffrTotalSize; - uint32_t ffrPageSize; - uint32_t cfpaPageVersion; - uint32_t cfpaPageOffset; -} flash_ffr_config_t; - -/*! @brief Flash driver state information. - * - * An instance of this structure is allocated by the user of the flash driver and - * passed into each of the driver APIs. - */ -typedef struct _flash_config -{ - uint32_t PFlashBlockBase; /*!< A base address of the first PFlash block */ - uint32_t PFlashTotalSize; /*!< The size of the combined PFlash block. */ - uint32_t PFlashBlockCount; /*!< A number of PFlash blocks. */ - uint32_t PFlashPageSize; /*!< The size in bytes of a page of PFlash. */ - uint32_t PFlashSectorSize; /*!< The size in bytes of a sector of PFlash. */ - flash_ffr_config_t ffrConfig; - flash_mode_config_t modeConfig; -} flash_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization - * @{ - */ - -/*! - * @brief Initializes the global flash properties structure members. - * - * This function checks and initializes the Flash module for the other Flash APIs. - * - * @param config Pointer to the storage for the driver runtime state. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_Init(flash_config_t *config); - -/*@}*/ - -/*! - * @name Erasing - * @{ - */ - -/*! - * @brief Erases the flash sectors encompassed by parameters passed into function. - * - * This function erases the appropriate number of flash sectors based on the - * desired start address and length. - * - * @param config The pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be erased. - * The start address need to be 512bytes-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words) - * to be erased. Must be 512bytes-aligned. - * @param key The value used to validate all flash erase APIs. - * - * @retval #kStatus_FLASH_Success API was executed successfully; - * the appropriate number of flash sectors based on the desired - * start address and length were erased successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_AddressError The address is out of range. - * @retval #kStatus_FLASH_EraseKeyError The API erase key is invalid. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - -/*@}*/ - -/*! - * @name Programming - * @{ - */ - -/*! - * @brief Programs flash with data at locations passed in through parameters. - * - * This function programs the flash memory with the desired data for a given - * flash area as determined by the start address and the length. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be programmed. Must be - * 512bytes-aligned. - * @param src A pointer to the source buffer of data that is to be programmed - * into the flash. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be programmed. Must be 512bytes-aligned. - * - * @retval #kStatus_FLASH_Success API was executed successfully; the desired data were programed successfully - * into flash based on desired start address and length. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); - -/*@}*/ - -/*! - * @brief Reads flash at locations passed in through parameters. - * - * This function read the flash memory from a given flash area as determined - * by the start address and the length. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be read. - * @param dest A pointer to the dest buffer of data that is to be read - * from the flash. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be read. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); - -/*! - * @name Verification - * @{ - */ - -/*! - * @brief Verifies an erasure of the desired flash area at a specified margin level. - * - * This function checks the appropriate number of flash sectors based on - * the desired start address and length to check whether the flash is erased - * to the specified read margin level. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be verified. - * The start address need to be 512bytes-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be verified. Must be 512bytes-aligned. - * - * @retval #kStatus_FLASH_Success API was executed successfully; the specified FLASH region has been erased. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); - -/*! - * @brief Verifies programming of the desired flash area at a specified margin level. - * - * This function verifies the data programed in the flash memory using the - * Flash Program Check Command and compares it to the expected data for a given - * flash area as determined by the start address and length. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be verified. need be 512bytes-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be verified. need be 512bytes-aligned. - * @param expectedData A pointer to the expected data that is to be - * verified against. - * @param failedAddress A pointer to the returned failing address. - * @param failedData A pointer to the returned failing data. Some derivatives do - * not include failed data as part of the FCCOBx registers. In this - * case, zeros are returned upon failure. - * - * @retval #kStatus_FLASH_Success API was executed successfully; - * the desired data have been successfully programed into specified FLASH region. - * - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_VerifyProgram(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - -/*@}*/ - -/*! - * @name Properties - * @{ - */ - -/*! - * @brief Returns the desired flash property. - * - * @param config A pointer to the storage for the driver runtime state. - * @param whichProperty The desired property from the list of properties in - * enum flash_property_tag_t - * @param value A pointer to the value returned for the desired flash property. - * - * @retval #kStatus_FLASH_Success API was executed successfully; the flash property was stored to value. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_UnknownProperty An unknown property tag. - */ -status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); - -/*@}*/ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* __FLASH_FLASH_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap_ffr.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap_ffr.h deleted file mode 100644 index 9481e07af14..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap_ffr.h +++ /dev/null @@ -1,388 +0,0 @@ -/* - * Copyright 2018-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __FSL_IAP_FFR_H_ -#define __FSL_IAP_FFR_H_ - -#include "fsl_iap.h" - -/*! - * @addtogroup flash_ifr_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! - * @name Flash IFR version - * @{ - */ -/*! @brief Flash IFR driver version for SDK*/ -#define FSL_FLASH_IFR_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ -/*@}*/ - -/*! @brief Alignment(down) utility. */ -#if !defined(ALIGN_DOWN) -#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) -#endif - -/*! @brief Alignment(up) utility. */ -#if !defined(ALIGN_UP) -#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) -#endif - -#define FLASH_FFR_MAX_PAGE_SIZE (512u) -#define FLASH_FFR_HASH_DIGEST_SIZE (32u) -#define FLASH_FFR_IV_CODE_SIZE (52u) - -/*! @brief flash ffr page offset. */ -enum _flash_ffr_page_offset -{ - kFfrPageOffset_CFPA = 0, /*!< Customer In-Field programmed area*/ - kFfrPageOffset_CFPA_Scratch = 0, /*!< CFPA Scratch page */ - kFfrPageOffset_CFPA_Cfg = 1, /*!< CFPA Configuration area (Ping page)*/ - kFfrPageOffset_CFPA_CfgPong = 2, /*!< Same as CFPA page (Pong page)*/ - - kFfrPageOffset_CMPA = 3, /*!< Customer Manufacturing programmed area*/ - kFfrPageOffset_CMPA_Cfg = 3, /*!< CMPA Configuration area (Part of CMPA)*/ - kFfrPageOffset_CMPA_Key = 4, /*!< Key Store area (Part of CMPA)*/ - - kFfrPageOffset_NMPA = 7, /*!< NXP Manufacturing programmed area*/ - kFfrPageOffset_NMPA_Romcp = 7, /*!< ROM patch area (Part of NMPA)*/ - kFfrPageOffset_NMPA_Repair = 9, /*!< Repair area (Part of NMPA)*/ - kFfrPageOffset_NMPA_Cfg = 15, /*!< NMPA configuration area (Part of NMPA)*/ - kFfrPageOffset_NMPA_End = 16, /*!< Reserved (Part of NMPA)*/ -}; - -/*! @brief flash ffr page number. */ -enum _flash_ffr_page_num -{ - kFfrPageNum_CFPA = 3, /*!< Customer In-Field programmed area*/ - kFfrPageNum_CMPA = 4, /*!< Customer Manufacturing programmed area*/ - kFfrPageNum_NMPA = 10, /*!< NXP Manufacturing programmed area*/ - - kFfrPageNum_CMPA_Cfg = 1, - kFfrPageNum_CMPA_Key = 3, - kFfrPageNum_NMPA_Romcp = 2, - - kFfrPageNum_SpecArea = kFfrPageNum_CFPA + kFfrPageNum_CMPA, - kFfrPageNum_Total = (kFfrPageNum_CFPA + kFfrPageNum_CMPA + kFfrPageNum_NMPA), -}; - -enum _flash_ffr_block_size -{ - kFfrBlockSize_Key = 52u, - kFfrBlockSize_ActivationCode = 1192u, -}; - -typedef enum _cfpa_cfg_cmpa_prog_process -{ - kFfrCmpaProgProcess_Pre = 0x0u, - kFfrCmpaProgProcess_Post = 0xFFFFFFFFu, -} cmpa_prog_process_t; - -typedef struct _cfpa_cfg_iv_code -{ - uint32_t keycodeHeader; - uint8_t reserved[FLASH_FFR_IV_CODE_SIZE]; -} cfpa_cfg_iv_code_t; - -typedef struct _cfpa_cfg_info -{ - uint32_t header; /*!< [0x000-0x003] */ - uint32_t version; /*!< [0x004-0x007 */ - uint32_t secureFwVersion; /*!< [0x008-0x00b */ - uint32_t nsFwVersion; /*!< [0x00c-0x00f] */ - uint32_t imageKeyRevoke; /*!< [0x010-0x013] */ - uint8_t reserved0[4]; /*!< [0x014-0x017] */ - uint32_t rotkhRevoke; /*!< [0x018-0x01b] */ - uint32_t vendorUsage; /*!< [0x01c-0x01f] */ - uint32_t dcfgNsPin; /*!< [0x020-0x013] */ - uint32_t dcfgNsDflt; /*!< [0x024-0x017] */ - uint32_t enableFaMode; /*!< [0x028-0x02b] */ - uint8_t reserved1[4]; /*!< [0x02c-0x02f] */ - cfpa_cfg_iv_code_t ivCodePrinceRegion[3]; /*!< [0x030-0x0d7] */ - uint8_t reserved2[264]; /*!< [0x0d8-0x1df] */ - uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */ -} cfpa_cfg_info_t; - -#define FFR_BOOTCFG_BOOTSPEED_MASK (0x18U) -#define FFR_BOOTCFG_BOOTSPEED_SHIFT (7U) -#define FFR_BOOTCFG_BOOTSPEED_48MHZ (0x0U) -#define FFR_BOOTCFG_BOOTSPEED_96MHZ (0x1U) - -#define FFR_USBID_VENDORID_MASK (0xFFFFU) -#define FFR_USBID_VENDORID_SHIFT (0U) -#define FFR_USBID_PRODUCTID_MASK (0xFFFF0000U) -#define FFR_USBID_PRODUCTID_SHIFT (16U) - -typedef struct _cmpa_cfg_info -{ - uint32_t bootCfg; /*!< [0x000-0x003] */ - uint32_t spiFlashCfg; /*!< [0x004-0x007] */ - struct - { - uint16_t vid; - uint16_t pid; - } usbId; /*!< [0x008-0x00b] */ - uint32_t sdioCfg; /*!< [0x00c-0x00f] */ - uint32_t dcfgPin; /*!< [0x010-0x013] */ - uint32_t dcfgDflt; /*!< [0x014-0x017] */ - uint32_t dapVendorUsage; /*!< [0x018-0x01b] */ - uint32_t secureBootCfg; /*!< [0x01c-0x01f] */ - uint32_t princeBaseAddr; /*!< [0x020-0x023] */ - uint32_t princeSr[3]; /*!< [0x024-0x02f] */ - uint8_t reserved0[32]; /*!< [0x030-0x04f] */ - uint32_t rotkh[8]; /*!< [0x050-0x06f] */ - uint8_t reserved1[368]; /*!< [0x070-0x1df] */ - uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */ -} cmpa_cfg_info_t; - -typedef struct _cmpa_key_store_header -{ - uint32_t header; - uint8_t reserved[4]; -} cmpa_key_store_header_t; - -#define FFR_SYSTEM_SPEED_CODE_MASK (0x3U) -#define FFR_SYSTEM_SPEED_CODE_SHIFT (0U) -#define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ (0x0U) -#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_24MHZ (0x1U) -#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_48MHZ (0x2U) -#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_96MHZ (0x3U) - -#define FFR_PERIPHERALCFG_PERI_MASK (0x7FFFFFFFU) -#define FFR_PERIPHERALCFG_PERI_SHIFT (0U) -#define FFR_PERIPHERALCFG_COREEN_MASK (0x10000000U) -#define FFR_PERIPHERALCFG_COREEN_SHIFT (31U) - -typedef struct _nmpa_cfg_info -{ - uint16_t fro32kCfg; /*!< [0x000-0x001] */ - uint8_t reserved0[6]; /*!< [0x002-0x007] */ - uint8_t sysCfg; /*!< [0x008-0x008] */ - uint8_t reserved1[7]; /*!< [0x009-0x00f] */ - struct - { - uint32_t data; - uint32_t reserved[3]; - } GpoInitData[3]; /*!< [0x010-0x03f] */ - uint32_t GpoDataChecksum[4]; /*!< [0x040-0x04f] */ - uint32_t finalTestBatchId[4]; /*!< [0x050-0x05f] */ - uint32_t deviceType; /*!< [0x060-0x063] */ - uint32_t finalTestProgVersion; /*!< [0x064-0x067] */ - uint32_t finalTestDate; /*!< [0x068-0x06b] */ - uint32_t finalTestTime; /*!< [0x06c-0x06f] */ - uint32_t uuid[4]; /*!< [0x070-0x07f] */ - uint8_t reserved2[32]; /*!< [0x080-0x09f] */ - uint32_t peripheralCfg; /*!< [0x0a0-0x0a3] */ - uint32_t ramSizeCfg; /*!< [0x0a4-0x0a7] */ - uint32_t flashSizeCfg; /*!< [0x0a8-0x0ab] */ - uint8_t reserved3[36]; /*!< [0x0ac-0x0cf] */ - uint8_t fro1mCfg; /*!< [0x0d0-0x0d0] */ - uint8_t reserved4[15]; /*!< [0x0d1-0x0df] */ - uint32_t dcdc[4]; /*!< [0x0e0-0x0ef] */ - uint32_t bod; /*!< [0x0f0-0x0f3] */ - uint8_t reserved5[12]; /*!< [0x0f4-0x0ff] */ - uint8_t calcHashReserved[192]; /*!< [0x100-0x1bf] */ - uint8_t sha256[32]; /*!< [0x1c0-0x1df] */ - uint32_t ecidBackup[4]; /*!< [0x1e0-0x1ef] */ - uint32_t pageChecksum[4]; /*!< [0x1f0-0x1ff] */ -} nmpa_cfg_info_t; - -typedef struct _ffr_key_store -{ - uint8_t reserved[3][FLASH_FFR_MAX_PAGE_SIZE]; -} ffr_key_store_t; - -typedef enum _ffr_key_type -{ - kFFR_KeyTypeSbkek = 0x00U, - kFFR_KeyTypeUser = 0x01U, - kFFR_KeyTypeUds = 0x02U, - kFFR_KeyTypePrinceRegion0 = 0x03U, - kFFR_KeyTypePrinceRegion1 = 0x04U, - kFFR_KeyTypePrinceRegion2 = 0x05U, -} ffr_key_type_t; - -typedef enum _ffr_bank_type -{ - kFFR_BankTypeBank0_NMPA = 0x00U, - kFFR_BankTypeBank1_CMPA = 0x01U, - kFFR_BankTypeBank2_CFPA = 0x02U -} ffr_bank_type_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name FFR APIs - * @{ - */ - -/*! - * @brief Initializes the global FFR properties structure members. - * - * @param config A pointer to the storage for the driver runtime state. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - */ -status_t FFR_Init(flash_config_t *config); - -/*! - * @brief Enable firewall for all flash banks. - * - * CFPA, CMPA, and NMPA flash areas region will be locked, After this function executed; - * Unless the board is reset again. - * - * @param config A pointer to the storage for the driver runtime state. - * - * @retval #kStatus_FLASH_Success An invalid argument is provided. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - */ -status_t FFR_Lock_All(flash_config_t *config); - -/*! - * @brief APIs to access CFPA pages - * - * This routine will erase CFPA and program the CFPA page with passed data. - * - * @param config A pointer to the storage for the driver runtime state. - * @param page_data A pointer to the source buffer of data that is to be programmed - * into the CFPA. - * @param valid_len The length, given in bytes, to be programmed. - * - * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CFPA. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_FfrBankIsLocked The CFPA was locked. - * @retval #kStatus_FLASH_OutOfDateCfpaPage It is not newest CFPA page. - */ -status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); - -/*! - * @brief APIs to access CFPA pages - * - * Generic read function, used by customer to read data stored in 'Customer In-field Page'. - * - * @param config A pointer to the storage for the driver runtime state. - * @param pData A pointer to the dest buffer of data that is to be read from 'Customer In-field Page'. - * @param offset An offset from the 'Customer In-field Page' start address. - * @param len The length, given in bytes, to be read. - * - * @retval #kStatus_FLASH_Success Get data from 'Customer In-field Page'. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_CommandFailure access error. - */ -status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - -/*! - * @brief APIs to access CMPA pages - * - * This routine will erase "customer factory page" and program the page with passed data. - * If 'seal_part' parameter is TRUE then the routine will compute SHA256 hash of - * the page contents and then programs the pages. - * 1.During development customer code uses this API with 'seal_part' set to FALSE. - * 2.During manufacturing this parameter should be set to TRUE to seal the part - * from further modifications - * 3.This routine checks if the page is sealed or not. A page is said to be sealed if - * the SHA256 value in the page has non-zero value. On boot ROM locks the firewall for - * the region if hash is programmed anyways. So, write/erase commands will fail eventually. - * - * @param config A pointer to the storage for the driver runtime state. - * @param page_data A pointer to the source buffer of data that is to be programmed - * into the "customer factory page". - * @param seal_part Set fasle for During development customer code. - * - * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CMPA. - * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. - * @retval kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_CommandFailure access error. - */ -status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part); - -/*! - * @brief APIs to access CMPA page - * - * Read data stored in 'Customer Factory CFG Page'. - * - * @param config A pointer to the storage for the driver runtime state. - * @param pData A pointer to the dest buffer of data that is to be read - * from the Customer Factory CFG Page. - * @param offset Address offset relative to the CMPA area. - * @param len The length, given in bytes to be read. - * - * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. - * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. - * @retval kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_CommandFailure access error. - */ -status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - -/*! - * @brief APIs to access CMPA page - * - * 1.SW should use this API routine to get the UUID of the chip. - * 2.Calling routine should pass a pointer to buffer which can hold 128-bit value. - */ -status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid); - -/*! - * @brief This routine writes the 3 pages allocated for Key store data, - * - * 1.Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state. - * 2.Optional routines to set individual data members (activation code, key codes etc) to construct - * the key store structure in RAM before committing it to IFR/FFR. - * - * @param config A pointer to the storage for the driver runtime state. - * @param pKeyStore A Pointer to the 3 pages allocated for Key store data. - * that will be written to 'customer factory page'. - * - * @retval #kStatus_FLASH_Success The key were programed successfully into FFR. - * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. - * @retval kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_CommandFailure access error. - */ -status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore); - -/*! - * @brief Get/Read Key store code routines - * - * 1. Calling code should pass buffer pointer which can hold activation code 1192 bytes. - * 2. Check if flash aperture is small or regular and read the data appropriately. - */ -status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode); - -/*! - * @brief Get/Read Key store code routines - * - * 1. Calling code should pass buffer pointer which can hold key code 52 bytes. - * 2. Check if flash aperture is small or regular and read the data appropriately. - * 3. keyIndex specifies which key code is read. - */ -status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); - -/*@}*/ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /*! __FSL_FLASH_FFR_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap_kbp.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap_kbp.h deleted file mode 100644 index 453a89a8fde..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap_kbp.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * Copyright (c) 2020-2021, Freescale Semiconductor, Inc. - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_IAP_KBP_H_ -#define _FSL_IAP_KBP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup kb_driver - * @{ - */ -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @brief ROM API status group number */ -#define kStatusGroup_RomApi (108U) - -/*! @brief ROM API status codes. */ -enum -{ - kStatus_RomApiExecuteCompleted = kStatus_Success, /*!< ROM successfully process the whole sb file/boot image.*/ - kStatus_RomApiNeedMoreData = - MAKE_STATUS(kStatusGroup_RomApi, 1), /*!< ROM needs more data to continue processing the boot image.*/ - kStatus_RomApiBufferSizeNotEnough = - MAKE_STATUS(kStatusGroup_RomApi, - 2), /*!< The user buffer is not enough for use by Kboot during execution of the operation.*/ - kStatus_RomApiInvalidBuffer = - MAKE_STATUS(kStatusGroup_RomApi, 3), /*!< The user buffer is not ok for sbloader or authentication.*/ -}; - -/*! - * @brief Details of the operation to be performed by the ROM. - * - * The #kRomAuthenticateImage operation requires the entire signed image to be - * available to the application. - */ -typedef enum _kb_operation -{ - kRomAuthenticateImage = 1, /*!< Authenticate a signed image.*/ - kRomLoadImage = 2, /*!< Load SB file.*/ - kRomOperationCount = 3, -} kb_operation_t; - -/*! - * @brief Security constraint flags, Security profile flags. - */ -enum _kb_security_profile -{ - kKbootMinRSA4096 = (1 << 16), -}; - -/*! - * @brief Memory region definition. - */ -typedef struct _kb_region -{ - uint32_t address; - uint32_t length; -} kb_region_t; - -/*! - * @brief User-provided options passed into kb_init(). - * - * The buffer field is a pointer to memory provided by the caller for use by - * Kboot during execution of the operation. Minimum size is the size of each - * certificate in the chain plus 432 bytes additional per certificate. - * - * The profile field is a mask that specifies which features are required in - * the SB file or image being processed. This includes the minimum AES and RSA - * key sizes. See the _kb_security_profile enum for profile mask constants. - * The image being loaded or authenticated must match the profile or an error will - * be returned. - * - * minBuildNumber is an optional field that can be used to prevent version - * rollback. The API will check the build number of the image, and if it is less - * than minBuildNumber will fail with an error. - * - * maxImageLength is used to verify the offsetToCertificateBlockHeaderInBytes - * value at the beginning of a signed image. It should be set to the length of - * the SB file. If verifying an image in flash, it can be set to the internal - * flash size or a large number like 0x10000000. - * - * userRHK can optionally be used by the user to override the RHK in IFR. If - * userRHK is not NULL, it points to a 32-byte array containing the SHA-256 of - * the root certificate's RSA public key. - * - * The regions field points to an array of memory regions that the SB file being - * loaded is allowed to access. If regions is NULL, then all memory is - * accessible by the SB file. This feature is required to prevent a malicious - * image from erasing good code or RAM contents while it is being loaded, only - * for us to find that the image is inauthentic when we hit the end of the - * section. - * - * overrideSBBootSectionID lets the caller override the default section of the - * SB file that is processed during a kKbootLoadSB operation. By default, - * the section specified in the firstBootableSectionID field of the SB header - * is loaded. If overrideSBBootSectionID is non-zero, then the section with - * the given ID will be loaded instead. - * - * The userSBKEK field lets a user provide their own AES-256 key for unwrapping - * keys in an SB file during the kKbootLoadSB operation. userSBKEK should point - * to a 32-byte AES-256 key. If userSBKEK is NULL then the IFR SBKEK will be used. - * After kb_init() returns, the caller should zero out the data pointed to by - * userSBKEK, as the API will have installed the key in the CAU3. - */ - -typedef struct _kb_load_sb -{ - uint32_t profile; - uint32_t minBuildNumber; - uint32_t overrideSBBootSectionID; - uint32_t *userSBKEK; - uint32_t regionCount; - const kb_region_t *regions; -} kb_load_sb_t; - -typedef struct _kb_authenticate -{ - uint32_t profile; - uint32_t minBuildNumber; - uint32_t maxImageLength; - uint32_t *userRHK; -} kb_authenticate_t; - -typedef struct _kb_options -{ - uint32_t version; /*!< Should be set to kKbootApiVersion.*/ - uint8_t *buffer; /*!< Caller-provided buffer used by Kboot.*/ - uint32_t bufferLength; - kb_operation_t op; - union - { - kb_authenticate_t authenticate; /*! Settings for kKbootAuthenticate operation.*/ - kb_load_sb_t loadSB; /*! Settings for kKbootLoadSB operation.*/ - }; -} kb_options_t; - -/*! - * @brief Interface to memory operations for one region of memory. - */ -typedef struct _memory_region_interface -{ - status_t (*init)(void); - status_t (*read)(uint32_t address, uint32_t length, uint8_t *buffer); - status_t (*write)(uint32_t address, uint32_t length, const uint8_t *buffer); - status_t (*fill)(uint32_t address, uint32_t length, uint32_t pattern); - status_t (*flush)(void); - status_t (*erase)(uint32_t address, uint32_t length); - status_t (*config)(uint32_t *buffer); - status_t (*erase_all)(void); -} memory_region_interface_t; - -/*! - * @brief Structure of a memory map entry. - */ -typedef struct _memory_map_entry -{ - uint32_t startAddress; - uint32_t endAddress; - uint32_t memoryProperty; - uint32_t memoryId; - const memory_region_interface_t *memoryInterface; -} memory_map_entry_t; - -typedef struct _kb_opaque_session_ref -{ - kb_options_t context; - bool cau3Initialized; - memory_map_entry_t *memoryMap; -} kb_session_ref_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize ROM API for a given operation. - * - * Inits the ROM API based on the options provided by the application in the second - * argument. Every call to rom_init() should be paired with a call to rom_deinit(). - * - * @retval #kStatus_Success API was executed successfully. - * @retval #kStatus_InvalidArgument An invalid argument is provided. - * @retval #kStatus_RomApiBufferSizeNotEnough The user buffer is not enough for use by Kboot during execution of the - * operation. - * @retval #kStatus_RomApiInvalidBuffer The user buffer is not ok for sbloader or authentication. - * @retval #kStatus_SKBOOT_Fail Return the failed status of secure boot. - * @retval #kStatus_SKBOOT_KeyStoreMarkerInvalid The key code for the particular PRINCE region is not present in the - * keystore - * @retval #kStatus_SKBOOT_Success Return the successful status of secure boot. - */ -status_t kb_init(kb_session_ref_t **session, const kb_options_t *options); - -/*! - * @brief Cleans up the ROM API context. - * - * After this call, the context parameter can be reused for another operation - * by calling rom_init() again. - * - * @retval #kStatus_Success API was executed successfully - */ -status_t kb_deinit(kb_session_ref_t *session); - -/*! - * Perform the operation configured during init. - * - * This application must call this API repeatedly, passing in sequential chunks of - * data from the boot image (SB file) that is to be processed. The ROM will perform - * the selected operation on this data and return. The application may call this - * function with as much or as little data as it wishes, which can be used to select - * the granularity of time given to the application in between executing the operation. - * - * @param session Current ROM context pointer. - * @param data Buffer of boot image data provided to the ROM by the application. - * @param dataLength Length in bytes of the data in the buffer provided to the ROM. - * - * @retval #kStatus_Success ROM successfully process the part of sb file/boot image. - * @retval #kStatus_RomApiExecuteCompleted ROM successfully process the whole sb file/boot image. - * @retval #kStatus_Fail An error occurred while executing the operation. - * @retval #kStatus_RomApiNeedMoreData No error occurred, but the ROM needs more data to - * continue processing the boot image. - * @retval #kStatus_RomApiBufferSizeNotEnough user buffer is not enough for - * use by Kboot during execution of the operation. - */ -status_t kb_execute(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength); - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_IAP_KBP_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap_skboot_authenticate.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap_skboot_authenticate.h deleted file mode 100644 index 67a513bc3cf..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap_skboot_authenticate.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _FSL_IAP_SKBOOT_AUTHENTICATE_H_ -#define _FSL_IAP_SKBOOT_AUTHENTICATE_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup skboot_authenticate - * @{ - */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @brief SKBOOT return status*/ -typedef enum _skboot_status -{ - kStatus_SKBOOT_Success = 0x5ac3c35au, /*!< SKBOOT return success status.*/ - kStatus_SKBOOT_Fail = 0xc35ac35au, /*!< SKBOOT return fail status.*/ - kStatus_SKBOOT_InvalidArgument = 0xc35a5ac3u, /*!< SKBOOT return invalid argument status.*/ - kStatus_SKBOOT_KeyStoreMarkerInvalid = 0xc3c35a5au, /*!< SKBOOT return Keystore invalid Marker status.*/ - kStatus_SKBOOT_HashcryptFinishedWithStatusSuccess = - 0xc15a5ac3, /*!< SKBOOT return Hashcrypt finished with the success status.*/ - kStatus_SKBOOT_HashcryptFinishedWithStatusFail = - 0xc15a5acb, /*!< SKBOOT return Hashcrypt finished with the fail status.*/ -} skboot_status_t; - -/*! @brief Secure bool flag*/ -typedef enum _secure_bool -{ - kSECURE_TRUE = 0xc33cc33cU, /*!< Secure true flag.*/ - kSECURE_FALSE = 0x5aa55aa5U, /*!< Secure false flag.*/ - kSECURE_CALLPROTECT_SECURITY_FLAGS = 0xc33c5aa5U, /*!< Secure call protect the security flag.*/ - kSECURE_CALLPROTECT_IS_APP_READY = 0x5aa5c33cU, /*!< Secure call protect the app is ready flag.*/ - kSECURE_TRACKER_VERIFIED = 0x55aacc33U, /*!< Secure tracker verified flag.*/ -} secure_bool_t; - -/******************************************************************************* - * Externs - ******************************************************************************/ - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Authenticate entry function with ARENA allocator init - * - * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface - */ -skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified); - -/*! - * @brief Interface for image authentication API - */ -void HASH_IRQHandler(void); - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_IAP_SKBOOT_AUTHENTICATE_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_inputmux.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_inputmux.c deleted file mode 100644 index ab208b78a4e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_inputmux.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_inputmux.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.inputmux" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Initialize INPUTMUX peripheral. - - * This function enables the INPUTMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * - * retval None. - */ -void INPUTMUX_Init(INPUTMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE - CLOCK_EnableClock(kCLOCK_Sct); - CLOCK_EnableClock(kCLOCK_Dma); -#else - CLOCK_EnableClock(kCLOCK_InputMux); -#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Attaches a signal - * - * This function gates the INPUTPMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * param index Destination peripheral to attach the signal to. - * param connection Selects connection. - * - * retval None. - */ -void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection) -{ - uint32_t pmux_id; - uint32_t output_id; - - /* extract pmux to be used */ - pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT; - /* extract function number */ - output_id = ((uint32_t)(connection)) & ((1UL << PMUX_SHIFT) - 1U); - /* programm signal */ - *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4U)) = output_id; -} - -#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) -/*! - * brief Enable/disable a signal - * - * This function gates the INPUTPMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * param signal Enable signal register id and bit offset. - * param enable Selects enable or disable. - * - * retval None. - */ -void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable) -{ - uint32_t ena_id; - uint32_t ena_id_mask = (1UL << (32U - ENA_SHIFT)) - 1U; - uint32_t bit_offset; - -#if defined(FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX) && FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX - uint32_t chmux_offset; - uint32_t chmux_value; - - /* Only enable need to update channel mux */ - if (enable && ((((uint32_t)signal) & (1UL << CHMUX_AVL_SHIFT)) != 0U)) - { - chmux_offset = (((uint32_t)signal) >> CHMUX_OFF_SHIFT) & ((1UL << (CHMUX_AVL_SHIFT - CHMUX_OFF_SHIFT)) - 1UL); - chmux_value = (((uint32_t)signal) >> CHMUX_VAL_SHIFT) & ((1UL << (CHMUX_OFF_SHIFT - CHMUX_VAL_SHIFT)) - 1UL); - *(volatile uint32_t *)(((uint32_t)base) + chmux_offset) = chmux_value; - } - ena_id_mask = (1UL << (CHMUX_VAL_SHIFT - ENA_SHIFT)) - 1U; -#endif - /* extract enable register to be used */ - ena_id = (((uint32_t)signal) >> ENA_SHIFT) & ena_id_mask; - /* extract enable bit offset */ - bit_offset = ((uint32_t)signal) & ((1UL << ENA_SHIFT) - 1U); - /* set signal */ - if (enable) - { - *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1UL << bit_offset); - } - else - { - *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1UL << bit_offset); - } -} -#endif - -/*! - * brief Deinitialize INPUTMUX peripheral. - - * This function disables the INPUTMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * - * retval None. - */ -void INPUTMUX_Deinit(INPUTMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE - CLOCK_DisableClock(kCLOCK_Sct); - CLOCK_DisableClock(kCLOCK_Dma); -#else - CLOCK_DisableClock(kCLOCK_InputMux); -#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_inputmux.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_inputmux.h deleted file mode 100644 index 90dd905fcfa..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_inputmux.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_INPUTMUX_H_ -#define _FSL_INPUTMUX_H_ - -#include "fsl_inputmux_connections.h" -#include "fsl_common.h" - -/*! - * @addtogroup inputmux_driver - * @{ - */ - -/*! @file */ -/*! @file fsl_inputmux_connections.h */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Group interrupt driver version for SDK */ -#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) -/*@}*/ - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @brief Initialize INPUTMUX peripheral. - - * This function enables the INPUTMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * - * @retval None. - */ -void INPUTMUX_Init(INPUTMUX_Type *base); - -/*! - * @brief Attaches a signal - * - * This function gates the INPUTPMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * @param index Destination peripheral to attach the signal to. - * @param connection Selects connection. - * - * @retval None. - */ -void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection); - -#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) -/*! - * @brief Enable/disable a signal - * - * This function gates the INPUTPMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * @param signal Enable signal register id and bit offset. - * @param enable Selects enable or disable. - * - * @retval None. - */ -void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable); -#endif - -/*! - * @brief Deinitialize INPUTMUX peripheral. - - * This function disables the INPUTMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * - * @retval None. - */ -void INPUTMUX_Deinit(INPUTMUX_Type *base); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_INPUTMUX_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_inputmux_connections.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_inputmux_connections.h deleted file mode 100644 index 3c142c7eba2..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_inputmux_connections.h +++ /dev/null @@ -1,481 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_INPUTMUX_CONNECTIONS_ -#define _FSL_INPUTMUX_CONNECTIONS_ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" -#endif - -/*! - * @addtogroup inputmux_driver - * @{ - */ - -/*! - * @name Input multiplexing connections - * @{ - */ - -/*! @brief Periphinmux IDs */ -#define SCT0_INMUX0 0x00U -#define TIMER0CAPTSEL0 0x20U -#define TIMER1CAPTSEL0 0x40U -#define TIMER2CAPTSEL0 0x60U -#define PINTSEL_PMUX_ID 0xC0U -#define PINTSEL0 0xC0U -#define DMA0_ITRIG_INMUX0 0xE0U -#define DMA0_OTRIG_INMUX0 0x160U -#define FREQMEAS_REF_REG 0x180U -#define FREQMEAS_TARGET_REG 0x184U -#define TIMER3CAPTSEL0 0x1A0U -#define TIMER4CAPTSEL0 0x1C0U -#define PINTSECSEL0 0x1E0U -#define DMA1_ITRIG_INMUX0 0x200U -#define DMA1_OTRIG_INMUX0 0x240U -#define DMA0_REQ_ENA_ID 0x740U -#define DMA1_REQ_ENA_ID 0x760U -#define DMA0_ITRIG_ENA_ID 0x780U -#define DMA1_ITRIG_ENA_ID 0x7A0U -#define ENA_SHIFT 8U -#define PMUX_SHIFT 20U - -/*! @brief INPUTMUX connections type */ -typedef enum _inputmux_connection_t -{ - /*!< SCT0 INMUX. */ - kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToSct0 = 8U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToSct0 = 9U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToSct0 = 10U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToSct0 = 11U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToSct0 = 12U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_AdcIrqToSct0 = 13U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToSct0 = 14U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToSct0 = 16U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_CompOutToSct0 = 17U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedSck0ToSct0 = 18U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedSck1ToSct0 = 19U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToSct0 = 20U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToSct0 = 21U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_ArmTxevToSct0 = 22U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_DebugHaltedToSct0 = 23U + (SCT0_INMUX0 << PMUX_SHIFT), - - /*!< TIMER0 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer0Captsel = 0U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToTimer0Captsel = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - - /*!< TIMER1 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer1Captsel = 0U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToTimer1Captsel = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - - /*!< TIMER2 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer2Captsel = 0U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToTimer2Captsel = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - - /*!< Pin interrupt select. */ - kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL0 << PMUX_SHIFT), - - /*!< DMA0 Input trigger. */ - kINPUTMUX_PinInt0ToDma0 = 0U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt1ToDma0 = 1U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt2ToDma0 = 2U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt3ToDma0 = 3U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToDma0 = 4U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M1ToDma0 = 5U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToDma0 = 6U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M1ToDma0 = 7U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToDma0 = 8U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M1ToDma0 = 9U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToDma0 = 10U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M1ToDma0 = 11U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToDma0 = 12U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M1ToDma0 = 13U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_CompOutToDma0 = 14U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig0ToDma0 = 15U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig1ToDma0 = 16U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig2ToDma0 = 17U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig3ToDma0 = 18U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq0ToDma0 = 19U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq1ToDma0 = 20U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_HashDmaRxToDma0 = 21U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - - /*!< DMA0 output trigger. */ - kINPUTMUX_Dma0Hash0TxTrigoutToTriginChannels = 0U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0HsLspiRxTrigoutToTriginChannels = 2U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0HsLspiTxTrigoutToTriginChannels = 3U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm3RxTrigoutToTriginChannels = 8U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm3TxTrigoutToTriginChannels = 9U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm2RxTrigoutToTriginChannels = 10U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm2TxTrigoutToTriginChannels = 11U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm4RxTrigoutToTriginChannels = 12U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm4TxTrigoutToTriginChannels = 13U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm5RxTrigoutToTriginChannels = 14U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm5TxTrigoutToTriginChannels = 15U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm6RxTrigoutToTriginChannels = 16U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm6TxTrigoutToTriginChannels = 17U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm7RxTrigoutToTriginChannels = 18U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm7TxTrigoutToTriginChannels = 19U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Adc0Ch0TrigoutToTriginChannels = 21U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Adc0Ch1TrigoutToTriginChannels = 22U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - - /*!< Selection for frequency measurement reference clock. */ - kINPUTMUX_ExternOscToFreqmeasRef = 0U + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_Fro12MhzToFreqmeasRef = 1u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_Fro96MhzToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_WdtOscToFreqmeasRef = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_32KhzOscToFreqmeasRef = 4u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_MainClkToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_aRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_bRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT), - - /*!< Selection for frequency measurement target clock. */ - kINPUTMUX_ExternOscToFreqmeasTarget = 0U + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_Fro12MhzToFreqmeasTarget = 1u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_Fro96MhzToFreqmeasTarget = 2u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_WdtOscToFreqmeasTarget = 3u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_32KhzOscToFreqmeasTarget = 4u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_MainClkToFreqmeasTarget = 5u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_aTarget = 6u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_bTarget = 7u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - - /*!< TIMER3 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer3Captsel = 0U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToTimer3Captsel = 21U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - - /*!< Timer4 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer4Captsel = 0U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToTimer4Captsel = 21U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - - /*Pin interrupt secure select */ - kINPUTMUX_GpioPort0Pin0ToPintSecsel = 0U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin1ToPintSecsel = 1U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin2ToPintSecsel = 2U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin3ToPintSecsel = 3U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin4ToPintSecsel = 4U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin5ToPintSecsel = 5U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin6ToPintSecsel = 6U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin7ToPintSecsel = 7U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin8ToPintSecsel = 8U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin9ToPintSecsel = 9U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin10ToPintSecsel = 10U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin11ToPintSecsel = 11U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin12ToPintSecsel = 12U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin13ToPintSecsel = 13U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin14ToPintSecsel = 14U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin15ToPintSecsel = 15U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin16ToPintSecsel = 16U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin17ToPintSecsel = 17U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin18ToPintSecsel = 18U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin19ToPintSecsel = 19U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin20ToPintSecsel = 20U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin21ToPintSecsel = 21U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin22ToPintSecsel = 22U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin23ToPintSecsel = 23U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin24ToPintSecsel = 24U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin25ToPintSecsel = 25U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin26ToPintSecsel = 26U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin27ToPintSecsel = 27U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin28ToPintSecsel = 28U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin29ToPintSecsel = 29U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin30ToPintSecsel = 30U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin31ToPintSecsel = 31U + (PINTSECSEL0 << PMUX_SHIFT), - - /*!< DMA1 Input trigger. */ - kINPUTMUX_PinInt0ToDma1 = 0U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt1ToDma1 = 1U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt2ToDma1 = 2U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt3ToDma1 = 3U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToDma1 = 4U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M1ToDma1 = 5U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToDma1 = 6U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToDma1 = 7U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig0ToDma1 = 8U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig1ToDma1 = 9U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig2ToDma1 = 10U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig3ToDma1 = 11U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq0ToDma1 = 12U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq1ToDma1 = 13U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_HashDmaRxToDma1 = 14U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - - /*!< DMA1 output trigger. */ - kINPUTMUX_Dma1Hash0TxTrigoutToTriginChannels = 0U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1HsLspiRxTrigoutToTriginChannels = 2U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1HsLspiTxTrigoutToTriginChannels = 3U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm3RxTrigoutToTriginChannels = 8U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm3TxTrigoutToTriginChannels = 9U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), -} inputmux_connection_t; - -/*! @brief INPUTMUX signal enable/disable type */ -typedef enum _inputmux_signal_t -{ - /*!< DMA0 REQ signal. */ - kINPUTMUX_HashCryptToDmac0Ch0RequestEna = 0U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm8RxToDmac0Ch2RequestEna = 2U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm8TxToDmac0Ch3RequestEna = 3U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm0RxToDmac0Ch4RequestEna = 4U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm0TxToDmac0Ch5RequestEna = 5U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm1RxToDmac0Ch6RequestEna = 6U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm1TxToDmac0Ch7RequestEna = 7U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm3RxToDmac0Ch8RequestEna = 8U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm3TxToDmac0Ch9RequestEna = 9U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm2RxToDmac0Ch10RequestEna = 10U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm2TxToDmac0Ch11RequestEna = 11U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm4RxToDmac0Ch12RequestEna = 12U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm4TxToDmac0Ch13RequestEna = 13U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm5RxToDmac0Ch14RequestEna = 14U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm5TxToDmac0Ch15RequestEna = 15U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm6RxToDmac0Ch16RequestEna = 16U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm6TxToDmac0Ch17RequestEna = 17U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm7RxToDmac0Ch18RequestEna = 18U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm7TxToDmac0Ch19RequestEna = 19U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Adc0FIFO0ToDmac0Ch21RequestEna = 21U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Adc0FIFO1ToDmac0Ch22RequestEna = 22U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - - /*!< DMA1 REQ signal. */ - kINPUTMUX_HashCryptToDmac1Ch0RequestEna = 0U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm8RxToDmac1Ch2RequestEna = 2U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm8TxToDmac1Ch3RequestEna = 3U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm0RxToDmac1Ch4RequestEna = 4U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm0TxToDmac1Ch5RequestEna = 5U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm1RxToDmac1Ch6RequestEna = 6U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm1TxToDmac1Ch7RequestEna = 7U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm3RxToDmac1Ch8RequestEna = 8U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm3TxToDmac1Ch9RequestEna = 9U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - - /*!< DMA0 input trigger source enable. */ - kINPUTMUX_Dmac0InputTriggerPint0Ena = 0U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerPint1Ena = 1U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerPint2Ena = 2U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerPint3Ena = 3U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer0M0Ena = 4U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer0M1Ena = 5U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer1M0Ena = 6U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer1M1Ena = 7U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer2M0Ena = 8U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer2M1Ena = 9U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer3M0Ena = 10U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer3M1Ena = 11U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer4M0Ena = 12U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer4M1Ena = 13U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCompOutEna = 14U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerDma0Out0Ena = 15U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerDma0Out1Ena = 16U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerDma0Out2Ena = 17U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerDma0Out3Ena = 18U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerSctDmac0Ena = 19U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerSctDmac1Ena = 20U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerHashOutEna = 21U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - - /*!< DMA1 input trigger source enable. */ - kINPUTMUX_Dmac1InputTriggerPint0Ena = 0U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerPint1Ena = 1U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerPint2Ena = 2U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerPint3Ena = 3U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerCtimer0M0Ena = 4U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerCtimer0M1Ena = 5U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerCtimer2M0Ena = 6U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerCtimer4M0Ena = 7U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerDma1Out0Ena = 8U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerDma1Out1Ena = 9U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerDma1Out2Ena = 10U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerDma1Out3Ena = 11U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerSctDmac0Ena = 12U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerSctDmac1Ena = 13U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerHashOutEna = 14U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), -} inputmux_signal_t; - -/*@}*/ - -/*@}*/ - -#endif /* _FSL_INPUTMUX_CONNECTIONS_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iocon.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iocon.h deleted file mode 100644 index e705e91f66c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iocon.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_IOCON_H_ -#define _FSL_IOCON_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_iocon - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon" -#endif - -/*! @name Driver version */ -/*@{*/ -/*! @brief IOCON driver version. */ -#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) -/*@}*/ - -/** - * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format - */ -typedef struct _iocon_group -{ - uint8_t port; /* Pin port */ - uint8_t pin; /* Pin number */ - uint8_t ionumber; /* IO number */ - uint16_t modefunc; /* Function and mode */ -} iocon_group_t; - -/** - * @brief IOCON function and mode selection definitions - * @note See the User Manual for specific modes and functions supported by the various pins. - */ -#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ -#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ -#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ -#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ -#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ -#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ -#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ -#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ -#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) -#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ -#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ -#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ -#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ -#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ -#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ -#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ -#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ -#endif /* FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH */ - -#if defined(IOCON_PIO_MODE_SHIFT) -#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ -#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ -#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ -#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ -#endif - -#if defined(IOCON_PIO_I2CSLEW_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_MODE (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ -#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */ -#endif - -#if defined(IOCON_PIO_EGP_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_MODE (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ -#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */ -#endif - -#if defined(IOCON_PIO_SLEW_SHIFT) -#define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ -#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ -#endif - -#if defined(IOCON_PIO_INVERT_SHIFT) -#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */ -#endif - -#if defined(IOCON_PIO_DIGIMODE_SHIFT) -#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */ -#define IOCON_DIGITAL_EN \ - (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */ -#endif - -#if defined(IOCON_PIO_FILTEROFF_SHIFT) -#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ -#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ -#endif - -#if defined(IOCON_PIO_I2CDRIVE_SHIFT) -#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ -#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ -#endif - -#if defined(IOCON_PIO_OD_SHIFT) -#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */ -#endif - -#if defined(IOCON_PIO_I2CFILTER_SHIFT) -#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ -#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */ -#endif - -#if defined(IOCON_PIO_ASW_SHIFT) -#define IOCON_AWS_EN (0x1 << IOCON_PIO_ASW_SHIFT) /*!< Enables analog switch function */ -#endif - -#if defined(IOCON_PIO_SSEL_SHIFT) -#define IOCON_SSEL_3V3 (0x0 << IOCON_PIO_SSEL_SHIFT) /*!< 3V3 signaling in I2C mode */ -#define IOCON_SSEL_1V8 (0x1 << IOCON_PIO_SSEL_SHIFT) /*!< 1V8 signaling in I2C mode */ -#endif - -#if defined(IOCON_PIO_ECS_SHIFT) -#define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */ -#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */ -#endif - -#if defined(IOCON_PIO_S_MODE_SHIFT) -#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ -#define IOCON_S_MODE_1CLK \ - (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_2CLK \ - (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_3CLK \ - (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ -#endif - -#if defined(IOCON_PIO_CLK_DIV_SHIFT) -#define IOCON_CLKDIV(div) \ - ((div) \ - << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ -#endif - -#if defined(__cplusplus) -extern "C" { -#endif - -#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) -/** - * @brief Sets I/O Control pin mux - * @param base : The base of IOCON peripheral on the chip - * @param ionumber : GPIO number to mux - * @param modefunc : OR'ed values of type IOCON_* - * @return Nothing - */ -__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc) -{ - base->PIO[ionumber] = modefunc; -} -#else -/** - * @brief Sets I/O Control pin mux - * @param base : The base of IOCON peripheral on the chip - * @param port : GPIO port to mux - * @param pin : GPIO pin to mux - * @param modefunc : OR'ed values of type IOCON_* - * @return Nothing - */ -__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc) -{ - base->PIO[port][pin] = modefunc; -} -#endif - -/** - * @brief Set all I/O Control pin muxing - * @param base : The base of IOCON peripheral on the chip - * @param pinArray : Pointer to array of pin mux selections - * @param arrayLength : Number of entries in pinArray - * @return Nothing - */ -__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength) -{ - uint32_t i; - - for (i = 0; i < arrayLength; i++) - { -#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) - IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc); -#else - IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc); -#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */ - } -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_IOCON_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_lpadc.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_lpadc.c deleted file mode 100644 index 7835e6fc454..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_lpadc.c +++ /dev/null @@ -1,612 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_lpadc.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpadc" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for LPADC module. - * - * @param base LPADC peripheral base address - */ -static uint32_t LPADC_GetInstance(ADC_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to LPADC bases for each instance. */ -static ADC_Type *const s_lpadcBases[] = ADC_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to LPADC clocks for each instance. */ -static const clock_ip_name_t s_lpadcClocks[] = LPADC_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t LPADC_GetInstance(ADC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_lpadcBases); instance++) - { - if (s_lpadcBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_lpadcBases)); - - return instance; -} - -/*! - * brief Initializes the LPADC module. - * - * param base LPADC peripheral base address. - * param config Pointer to configuration structure. See "lpadc_config_t". - */ -void LPADC_Init(ADC_Type *base, const lpadc_config_t *config) -{ - /* Check if the pointer is available. */ - assert(config != NULL); - - uint32_t tmp32 = 0U; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock for LPADC instance. */ - (void)CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the module. */ - LPADC_DoResetConfig(base); -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - LPADC_DoResetFIFO0(base); - LPADC_DoResetFIFO1(base); -#else - LPADC_DoResetFIFO(base); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - - /* Disable the module before setting configuration. */ - LPADC_Enable(base, false); - - /* Configure the module generally. */ - if (config->enableInDozeMode) - { - base->CTRL &= ~ADC_CTRL_DOZEN_MASK; - } - else - { - base->CTRL |= ADC_CTRL_DOZEN_MASK; - } - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS - /* Set calibration average mode. */ - base->CTRL |= ADC_CTRL_CAL_AVGS(config->conversionAverageMode); -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - -/* ADCx_CFG. */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - if (config->enableInternalClock) - { - tmp32 |= ADC_CFG_ADCKEN_MASK; - } -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - if (config->enableVref1LowVoltage) - { - tmp32 |= ADC_CFG_VREF1RNG_MASK; - } -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - if (config->enableAnalogPreliminary) - { - tmp32 |= ADC_CFG_PWREN_MASK; - } - tmp32 |= ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */ - | ADC_CFG_REFSEL(config->referenceVoltageSource) /* Reference voltage. */ - | ADC_CFG_PWRSEL(config->powerLevelMode) /* Power configuration. */ - | ADC_CFG_TPRICTRL(config->triggerPriorityPolicy); /* Trigger priority policy. */ - base->CFG = tmp32; - - /* ADCx_PAUSE. */ - if (config->enableConvPause) - { - base->PAUSE = ADC_PAUSE_PAUSEEN_MASK | ADC_PAUSE_PAUSEDLY(config->convPauseDelay); - } - else - { - base->PAUSE = 0U; - } - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - /* ADCx_FCTRL0. */ - base->FCTRL[0] = ADC_FCTRL_FWMARK(config->FIFO0Watermark); - /* ADCx_FCTRL1. */ - base->FCTRL[1] = ADC_FCTRL_FWMARK(config->FIFO1Watermark); -#else - /* ADCx_FCTRL. */ - base->FCTRL = ADC_FCTRL_FWMARK(config->FIFOWatermark); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - - /* Enable the module after setting configuration. */ - LPADC_Enable(base, true); -} - -/*! - * brief Gets an available pre-defined settings for initial configuration. - * - * This function initializes the converter configuration structure with an available settings. The default values are: - * code - * config->enableInDozeMode = true; - * config->conversionAverageMode = kLPADC_ConversionAverage1; - * config->enableAnalogPreliminary = false; - * config->powerUpDelay = 0x80; - * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - * config->powerLevelMode = kLPADC_PowerLevelAlt1; - * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; - * config->enableConvPause = false; - * config->convPauseDelay = 0U; - * config->FIFO0Watermark = 0U; - * config->FIFO1Watermark = 0U; - * config->FIFOWatermark = 0U; - * endcode - * param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConfig(lpadc_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - config->enableInternalClock = false; -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - config->enableVref1LowVoltage = false; -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - config->enableInDozeMode = true; -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS - /* Set calibration average mode. */ - config->conversionAverageMode = kLPADC_ConversionAverage1; -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - config->enableAnalogPreliminary = false; - config->powerUpDelay = 0x80; - config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - config->powerLevelMode = kLPADC_PowerLevelAlt1; - config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; - config->enableConvPause = false; - config->convPauseDelay = 0U; -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - config->FIFO0Watermark = 0U; - config->FIFO1Watermark = 0U; -#else - config->FIFOWatermark = 0U; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ -} - -/*! - * brief De-initializes the LPADC module. - * - * param base LPADC peripheral base address. - */ -void LPADC_Deinit(ADC_Type *base) -{ - /* Disable the module. */ - LPADC_Enable(base, false); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the clock. */ - (void)CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * brief Get the result in conversion FIFOn. - * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. - * param index Result FIFO index. - * - * return Status whether FIFOn entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index) -{ - assert(result != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - tmp32 = base->RESFIFO[index]; - - if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) - { - return false; /* FIFO is empty. Discard any read from RESFIFO. */ - } - - result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; - result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; - result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; - result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); - - return true; -} -#else -/*! - * brief Get the result in conversion FIFO. - * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFO. - * - * return Status whether FIFO entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result) -{ - assert(result != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - tmp32 = base->RESFIFO; - - if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) - { - return false; /* FIFO is empty. Discard any read from RESFIFO. */ - } - - result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; - result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; - result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; - result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); - - return true; -} -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * brief Configure the conversion trigger source. - * - * Each programmable trigger can launch the conversion command in command buffer. - * - * param base LPADC peripheral base address. - * param triggerId ID for each trigger. Typically, the available value range is from 0. - * param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. - */ -void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config) -{ - assert(triggerId < ADC_TCTRL_COUNT); /* Check if the triggerId is available in this device. */ - assert(config != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - tmp32 = ADC_TCTRL_TCMD(config->targetCommandId) /* Trigger command select. */ - | ADC_TCTRL_TDLY(config->delayPower) /* Trigger delay select. */ - | ADC_TCTRL_TPRI(config->priority) /* Trigger priority setting. */ -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - | ADC_TCTRL_FIFO_SEL_A(config->channelAFIFOSelect) -#if !(defined(FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) && FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) - | ADC_TCTRL_FIFO_SEL_B(config->channelBFIFOSelect) -#endif /* FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - ; - if (config->enableHardwareTrigger) - { - tmp32 |= ADC_TCTRL_HTEN_MASK; - } - - base->TCTRL[triggerId] = tmp32; -} - -/*! - * brief Gets an available pre-defined settings for trigger's configuration. - * - * This function initializes the trigger's configuration structure with an available settings. The default values are: - * code - * config->commandIdSource = 0U; - * config->loopCountIndex = 0U; - * config->triggerIdSource = 0U; - * config->enableHardwareTrigger = false; - * config->channelAFIFOSelect = 0U; - * config->channelBFIFOSelect = 0U; - * endcode - * param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config) -{ - assert(config != NULL); /* Check if the input pointer is available. */ - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->targetCommandId = 0U; - config->delayPower = 0U; - config->priority = 0U; -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - config->channelAFIFOSelect = 0U; - config->channelBFIFOSelect = 0U; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - config->enableHardwareTrigger = false; -} - -/*! - * brief Configure conversion command. - * - * param base LPADC peripheral base address. - * param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. - * param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. - */ -void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config) -{ - assert(commandId < (ADC_CMDL_COUNT + 1U)); /* Check if the commandId is available on this device. */ - assert(config != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32 = 0; - - commandId--; /* The available command number are 1-15, while the index of register group are 0-14. */ - - /* ADCx_CMDL. */ - tmp32 = ADC_CMDL_ADCH(config->channelNumber); /* Channel number. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - tmp32 |= ADC_CMDL_CSCALE(config->sampleScaleMode); /* Full/Part scale input voltage. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE - tmp32 |= ADC_CMDL_CTYPE(config->sampleChannelMode); -#else - switch (config->sampleChannelMode) /* Sample input. */ - { - case kLPADC_SampleChannelSingleEndSideB: - tmp32 |= ADC_CMDL_ABSEL_MASK; - break; -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF - case kLPADC_SampleChannelDiffBothSideAB: - tmp32 |= ADC_CMDL_DIFF_MASK; - break; - case kLPADC_SampleChannelDiffBothSideBA: - tmp32 |= ADC_CMDL_ABSEL_MASK | ADC_CMDL_DIFF_MASK; - break; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_DIFF */ - default: /* kLPADC_SampleChannelSingleEndSideA. */ - break; - } -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - tmp32 |= ADC_CMDL_MODE(config->conversionResolutionMode); -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ - base->CMD[commandId].CMDL = tmp32; - - /* ADCx_CMDH. */ - tmp32 = ADC_CMDH_NEXT(config->chainedNextCommandNumber) /* Next Command Select. */ - | ADC_CMDH_LOOP(config->loopCount) /* Loop Count Select. */ - | ADC_CMDH_AVGS(config->hardwareAverageMode) /* Hardware Average Select. */ - | ADC_CMDH_STS(config->sampleTimeMode) /* Sample Time Select. */ - | ADC_CMDH_CMPEN(config->hardwareCompareMode); /* Hardware compare enable. */ -#if (defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) - if (config->enableWaitTrigger) - { - tmp32 |= ADC_CMDH_WAIT_TRIG_MASK; /* Wait trigger enable. */ - } -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ - - if (config->enableAutoChannelIncrement) - { - tmp32 |= ADC_CMDH_LWI_MASK; - } - base->CMD[commandId].CMDH = tmp32; - - /* Hardware compare settings. - * Not all Command Buffers have an associated Compare Value register. The compare function is only available on - * Command Buffers that have a corresponding Compare Value register. - */ - if (kLPADC_HardwareCompareDisabled != config->hardwareCompareMode) - { - /* Check if the hardware compare feature is available for indicated command buffer. */ - assert(commandId < ADC_CV_COUNT); - - /* Set CV register. */ - base->CV[commandId] = ADC_CV_CVH(config->hardwareCompareValueHigh) /* Compare value high. */ - | ADC_CV_CVL(config->hardwareCompareValueLow); /* Compare value low. */ - } -} - -/*! - * brief Gets an available pre-defined settings for conversion command's configuration. - * - * This function initializes the conversion command's configuration structure with an available settings. The default - * values are: - * code - * config->sampleScaleMode = kLPADC_SampleFullScale; - * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; - * config->channelNumber = 0U; - * config->chainedNextCmdNumber = 0U; - * config->enableAutoChannelIncrement = false; - * config->loopCount = 0U; - * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - * config->sampleTimeMode = kLPADC_SampleTimeADCK3; - * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - * config->hardwareCompareValueHigh = 0U; - * config->hardwareCompareValueLow = 0U; - * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; - * config->enableWaitTrigger = false; - * endcode - * param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config) -{ - assert(config != NULL); /* Check if the input pointer is available. */ - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - config->sampleScaleMode = kLPADC_SampleFullScale; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ - config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; - config->channelNumber = 0U; - config->chainedNextCommandNumber = 0U; /* No next command defined. */ - config->enableAutoChannelIncrement = false; - config->loopCount = 0U; - config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - config->sampleTimeMode = kLPADC_SampleTimeADCK3; - config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - config->hardwareCompareValueHigh = 0U; /* No used. */ - config->hardwareCompareValueLow = 0U; /* No used. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG - config->enableWaitTrigger = false; -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ -} - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS -/*! - * brief Enable the calibration function. - * - * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes - * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value - * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- - * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the - * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. - * - * param base LPADC peripheral base address. - * param enable switcher to the calibration function. - */ -void LPADC_EnableCalibration(ADC_Type *base, bool enable) -{ - LPADC_Enable(base, false); - if (enable) - { - base->CFG |= ADC_CFG_CALOFS_MASK; - } - else - { - base->CFG &= ~ADC_CFG_CALOFS_MASK; - } - LPADC_Enable(base, true); -} - -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! - * brief Do auto calibration. - * - * Calibration function should be executed before using converter in application. It used the software trigger and a - * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API - * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) - * -LPADC_SetConvTriggerConfig(...) - * - * param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base) -{ - assert(0u == LPADC_GetConvResultCount(base)); - - uint32_t mLpadcCMDL; - uint32_t mLpadcCMDH; - uint32_t mLpadcTrigger; - lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct; - lpadc_conv_command_config_t mLpadcCommandConfigStruct; - lpadc_conv_result_t mLpadcResultConfigStruct; - - /* Enable the calibration function. */ - LPADC_EnableCalibration(base, true); - - /* Keep the CMD and TRG state here and restore it later if the calibration completes.*/ - mLpadcCMDL = base->CMD[0].CMDL; /* CMD1L. */ - mLpadcCMDH = base->CMD[0].CMDH; /* CMD1H. */ - mLpadcTrigger = base->TCTRL[0]; /* Trigger0. */ - - /* Set trigger0 configuration - for software trigger. */ - LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct); - mLpadcTriggerConfigStruct.targetCommandId = 1U; /* CMD1 is executed. */ - LPADC_SetConvTriggerConfig(base, 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */ - - /* Set conversion CMD configuration. */ - LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct); - mLpadcCommandConfigStruct.hardwareAverageMode = kLPADC_HardwareAverageCount128; - LPADC_SetConvCommandConfig(base, 1U, &mLpadcCommandConfigStruct); /* Set CMD1 configuration. */ - - /* Do calibration. */ - LPADC_DoSoftwareTrigger(base, 1U); /* 1U is trigger0 mask. */ - while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct)) - { - } - /* The valid bits of data are bits 14:3 in the RESFIFO register. */ - LPADC_SetOffsetValue(base, (uint32_t)(mLpadcResultConfigStruct.convValue) >> 3UL); - /* Disable the calibration function. */ - LPADC_EnableCalibration(base, false); - - /* restore CMD and TRG registers. */ - base->CMD[0].CMDL = mLpadcCMDL; /* CMD1L. */ - base->CMD[0].CMDH = mLpadcCMDH; /* CMD1H. */ - base->TCTRL[0] = mLpadcTrigger; /* Trigger0. */ -} -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS -/*! - * brief Do offset calibration. - * - * param base LPADC peripheral base address. - */ -void LPADC_DoOffsetCalibration(ADC_Type *base) -{ - LPADC_EnableOffsetCalibration(base, true); - while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) - { - } -} - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ -/*! - * brief Do auto calibration. - * - * param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base) -{ - assert((0u == LPADC_GetConvResultCount(base, 0)) && (0u == LPADC_GetConvResultCount(base, 1))); - - uint32_t GCCa; - uint32_t GCCb; - uint32_t GCRa; - uint32_t GCRb; - - /* Request gain calibration. */ - base->CTRL |= ADC_CTRL_CAL_REQ_MASK; - while ((ADC_GCC_RDY_MASK != (base->GCC[0] & ADC_GCC_RDY_MASK)) || - (ADC_GCC_RDY_MASK != (base->GCC[1] & ADC_GCC_RDY_MASK))) - { - } - - /* Calculate gain offset. */ - GCCa = (base->GCC[0] & ADC_GCC_GAIN_CAL_MASK); - GCCb = (base->GCC[1] & ADC_GCC_GAIN_CAL_MASK); - GCRa = (uint16_t)((GCCa << 16U) / - (0x1FFFFU - GCCa)); /* Gain_CalA = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[0])) - 1. */ - GCRb = (uint16_t)((GCCb << 16U) / - (0x1FFFFU - GCCb)); /* Gain_CalB = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[1])) - 1. */ - base->GCR[0] = ADC_GCR_GCALR(GCRa); - base->GCR[1] = ADC_GCR_GCALR(GCRb); - - /* Indicate the values are valid. */ - base->GCR[0] |= ADC_GCR_RDY_MASK; - base->GCR[1] |= ADC_GCR_RDY_MASK; - - while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) - { - } -} -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_lpadc.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_lpadc.h deleted file mode 100644 index d3e5a9ec30a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_lpadc.h +++ /dev/null @@ -1,964 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_LPADC_H_ -#define _FSL_LPADC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpadc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPADC driver version 2.5.1. */ -#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 5, 1)) -/*@}*/ - -/*! - * @brief Define the MACRO function to get command status from status value. - * - * The statusVal is the return value from LPADC_GetStatusFlags(). - */ -#define LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal) ((statusVal & ADC_STAT_CMDACT_MASK) >> ADC_STAT_CMDACT_SHIFT) - -/*! - * @brief Define the MACRO function to get trigger status from status value. - * - * The statusVal is the return value from LPADC_GetStatusFlags(). - */ -#define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT) - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Define hardware flags of the module. - */ -enum _lpadc_status_flags -{ - kLPADC_ResultFIFO0OverflowFlag = ADC_STAT_FOF0_MASK, /*!< Indicates that more data has been written to the Result - FIFO 0 than it can hold. */ - kLPADC_ResultFIFO0ReadyFlag = ADC_STAT_RDY0_MASK, /*!< Indicates when the number of valid datawords in the result - FIFO 0 is greater than the setting watermark level. */ - kLPADC_ResultFIFO1OverflowFlag = ADC_STAT_FOF1_MASK, /*!< Indicates that more data has been written to the Result - FIFO 1 than it can hold. */ - kLPADC_ResultFIFO1ReadyFlag = ADC_STAT_RDY1_MASK, /*!< Indicates when the number of valid datawords in the result - FIFO 1 is greater than the setting watermark level. */ -}; - -/*! - * @brief Define interrupt switchers of the module. - */ -enum _lpadc_interrupt_enable -{ - kLPADC_ResultFIFO0OverflowInterruptEnable = ADC_IE_FOFIE0_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF0 flag is asserted. */ - kLPADC_FIFO0WatermarkInterruptEnable = ADC_IE_FWMIE0_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY0 flag is asserted. */ - kLPADC_ResultFIFO1OverflowInterruptEnable = ADC_IE_FOFIE1_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF1 flag is asserted. */ - kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY1 flag is asserted. */ -#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) - kLPADC_TriggerExceptionInterruptEnable = ADC_IE_TEXC_IE_MASK, /*!< Configures ADC to generate trigger exception - interrupt. */ - kLPADC_Trigger0CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 0UL), /*!< Configures ADC to generate interrupt - when trigger 0 completion. */ - kLPADC_Trigger1CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 1UL), /*!< Configures ADC to generate interrupt - when trigger 1 completion. */ - kLPADC_Trigger2CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 2UL), /*!< Configures ADC to generate interrupt - when trigger 2 completion. */ - kLPADC_Trigger3CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 3UL), /*!< Configures ADC to generate interrupt - when trigger 3 completion. */ - kLPADC_Trigger4CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 4UL), /*!< Configures ADC to generate interrupt - when trigger 4 completion. */ - kLPADC_Trigger5CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 5UL), /*!< Configures ADC to generate interrupt - when trigger 5 completion. */ - kLPADC_Trigger6CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 6UL), /*!< Configures ADC to generate interrupt - when trigger 6 completion. */ - kLPADC_Trigger7CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 7UL), /*!< Configures ADC to generate interrupt - when trigger 7 completion. */ - kLPADC_Trigger8CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 8UL), /*!< Configures ADC to generate interrupt - when trigger 8 completion. */ - kLPADC_Trigger9CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 9UL), /*!< Configures ADC to generate interrupt - when trigger 9 completion. */ - kLPADC_Trigger10CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 10UL), /*!< Configures ADC to generate interrupt - when trigger 10 completion. */ - kLPADC_Trigger11CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 11UL), /*!< Configures ADC to generate interrupt - when trigger 11 completion. */ - kLPADC_Trigger12CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 12UL), /*!< Configures ADC to generate interrupt - when trigger 12 completion. */ - kLPADC_Trigger13CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 13UL), /*!< Configures ADC to generate interrupt - when trigger 13 completion. */ - kLPADC_Trigger14CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 14UL), /*!< Configures ADC to generate interrupt - when trigger 14 completion. */ - kLPADC_Trigger15CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 15UL), /*!< Configures ADC to generate interrupt - when trigger 15 completion. */ -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ -}; -#else -/*! - * @brief Define hardware flags of the module. - */ -enum _lpadc_status_flags -{ - kLPADC_ResultFIFOOverflowFlag = ADC_STAT_FOF_MASK, /*!< Indicates that more data has been written to the Result FIFO - than it can hold. */ - kLPADC_ResultFIFOReadyFlag = ADC_STAT_RDY_MASK, /*!< Indicates when the number of valid datawords in the result FIFO - is greater than the setting watermark level. */ -}; - -/*! - * @brief Define interrupt switchers of the module. - */ -enum _lpadc_interrupt_enable -{ - kLPADC_ResultFIFOOverflowInterruptEnable = ADC_IE_FOFIE_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF flag is asserted. */ - kLPADC_FIFOWatermarkInterruptEnable = ADC_IE_FWMIE_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY flag is asserted. */ -}; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) -/*! - * @brief The enumerator of lpadc trigger status flags, including interrupted flags and completed flags. - */ -enum _lpadc_trigger_status_flags -{ - kLPADC_Trigger0InterruptedFlag = 1UL << 0UL, /*!< Trigger 0 is interrupted by a high priority exception. */ - kLPADC_Trigger1InterruptedFlag = 1UL << 1UL, /*!< Trigger 1 is interrupted by a high priority exception. */ - kLPADC_Trigger2InterruptedFlag = 1UL << 2UL, /*!< Trigger 2 is interrupted by a high priority exception. */ - kLPADC_Trigger3InterruptedFlag = 1UL << 3UL, /*!< Trigger 3 is interrupted by a high priority exception. */ - kLPADC_Trigger4InterruptedFlag = 1UL << 4UL, /*!< Trigger 4 is interrupted by a high priority exception. */ - kLPADC_Trigger5InterruptedFlag = 1UL << 5UL, /*!< Trigger 5 is interrupted by a high priority exception. */ - kLPADC_Trigger6InterruptedFlag = 1UL << 6UL, /*!< Trigger 6 is interrupted by a high priority exception. */ - kLPADC_Trigger7InterruptedFlag = 1UL << 7UL, /*!< Trigger 7 is interrupted by a high priority exception. */ - kLPADC_Trigger8InterruptedFlag = 1UL << 8UL, /*!< Trigger 8 is interrupted by a high priority exception. */ - kLPADC_Trigger9InterruptedFlag = 1UL << 9UL, /*!< Trigger 9 is interrupted by a high priority exception. */ - kLPADC_Trigger10InterruptedFlag = 1UL << 10UL, /*!< Trigger 10 is interrupted by a high priority exception. */ - kLPADC_Trigger11InterruptedFlag = 1UL << 11UL, /*!< Trigger 11 is interrupted by a high priority exception. */ - kLPADC_Trigger12InterruptedFlag = 1UL << 12UL, /*!< Trigger 12 is interrupted by a high priority exception. */ - kLPADC_Trigger13InterruptedFlag = 1UL << 13UL, /*!< Trigger 13 is interrupted by a high priority exception. */ - kLPADC_Trigger14InterruptedFlag = 1UL << 14UL, /*!< Trigger 14 is interrupted by a high priority exception. */ - kLPADC_Trigger15InterruptedFlag = 1UL << 15UL, /*!< Trigger 15 is interrupted by a high priority exception. */ - - kLPADC_Trigger0CompletedFlag = 1UL << 16UL, /*!< Trigger 0 is completed and - trigger 0 has enabled completion interrupts. */ - kLPADC_Trigger1CompletedFlag = 1UL << 17UL, /*!< Trigger 1 is completed and - trigger 1 has enabled completion interrupts. */ - kLPADC_Trigger2CompletedFlag = 1UL << 18UL, /*!< Trigger 2 is completed and - trigger 2 has enabled completion interrupts. */ - kLPADC_Trigger3CompletedFlag = 1UL << 19UL, /*!< Trigger 3 is completed and - trigger 3 has enabled completion interrupts. */ - kLPADC_Trigger4CompletedFlag = 1UL << 20UL, /*!< Trigger 4 is completed and - trigger 4 has enabled completion interrupts. */ - kLPADC_Trigger5CompletedFlag = 1UL << 21UL, /*!< Trigger 5 is completed and - trigger 5 has enabled completion interrupts. */ - kLPADC_Trigger6CompletedFlag = 1UL << 22UL, /*!< Trigger 6 is completed and - trigger 6 has enabled completion interrupts. */ - kLPADC_Trigger7CompletedFlag = 1UL << 23UL, /*!< Trigger 7 is completed and - trigger 7 has enabled completion interrupts. */ - kLPADC_Trigger8CompletedFlag = 1UL << 24UL, /*!< Trigger 8 is completed and - trigger 8 has enabled completion interrupts. */ - kLPADC_Trigger9CompletedFlag = 1UL << 25UL, /*!< Trigger 9 is completed and - trigger 9 has enabled completion interrupts. */ - kLPADC_Trigger10CompletedFlag = 1UL << 26UL, /*!< Trigger 10 is completed and - trigger 10 has enabled completion interrupts. */ - kLPADC_Trigger11CompletedFlag = 1UL << 27UL, /*!< Trigger 11 is completed and - trigger 11 has enabled completion interrupts. */ - kLPADC_Trigger12CompletedFlag = 1UL << 28UL, /*!< Trigger 12 is completed and - trigger 12 has enabled completion interrupts. */ - kLPADC_Trigger13CompletedFlag = 1UL << 29UL, /*!< Trigger 13 is completed and - trigger 13 has enabled completion interrupts. */ - kLPADC_Trigger14CompletedFlag = 1UL << 30UL, /*!< Trigger 14 is completed and - trigger 14 has enabled completion interrupts. */ - kLPADC_Trigger15CompletedFlag = 1UL << 31UL, /*!< Trigger 15 is completed and - trigger 15 has enabled completion interrupts. */ -}; -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ - -/*! - * @brief Define enumeration of sample scale mode. - * - * The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum - * possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the - * reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows - * conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode. - */ -typedef enum _lpadc_sample_scale_mode -{ - kLPADC_SamplePartScale = 0U, /*!< Use divided input voltage signal. (Factor of 30/64). */ - kLPADC_SampleFullScale = 1U, /*!< Full scale (Factor of 1). */ -} lpadc_sample_scale_mode_t; - -/*! - * @brief Define enumeration of channel sample mode. - * - * The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B. - */ -typedef enum _lpadc_sample_channel_mode -{ - kLPADC_SampleChannelSingleEndSideA = 0U, /*!< Single end mode, using side A. */ - kLPADC_SampleChannelSingleEndSideB = 1U, /*!< Single end mode, using side B. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF - kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minus side. */ - kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minus side. */ -#elif defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE - kLPADC_SampleChannelDiffBothSide = 2U, /*!< Differential mode, using A and B. */ - kLPADC_SampleChannelDualSingleEndBothSide = - 3U, /*!< Dual-Single-Ended Mode. Both A side and B side channels are converted independently. */ -#endif -} lpadc_sample_channel_mode_t; - -/*! - * @brief Define enumeration of hardware average selection. - * - * It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to - * capture temporary results while the averaging iterations are executed. - */ -typedef enum _lpadc_hardware_average_mode -{ - kLPADC_HardwareAverageCount1 = 0U, /*!< Single conversion. */ - kLPADC_HardwareAverageCount2 = 1U, /*!< 2 conversions averaged. */ - kLPADC_HardwareAverageCount4 = 2U, /*!< 4 conversions averaged. */ - kLPADC_HardwareAverageCount8 = 3U, /*!< 8 conversions averaged. */ - kLPADC_HardwareAverageCount16 = 4U, /*!< 16 conversions averaged. */ - kLPADC_HardwareAverageCount32 = 5U, /*!< 32 conversions averaged. */ - kLPADC_HardwareAverageCount64 = 6U, /*!< 64 conversions averaged. */ - kLPADC_HardwareAverageCount128 = 7U, /*!< 128 conversions averaged. */ -} lpadc_hardware_average_mode_t; - -/*! - * @brief Define enumeration of sample time selection. - * - * The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher - * impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption - * when command looping and sequencing is configured and high conversion rates are not required. - */ -typedef enum _lpadc_sample_time_mode -{ - kLPADC_SampleTimeADCK3 = 0U, /*!< 3 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK5 = 1U, /*!< 5 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK7 = 2U, /*!< 7 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK11 = 3U, /*!< 11 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK19 = 4U, /*!< 19 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK35 = 5U, /*!< 35 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK67 = 6U, /*!< 69 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK131 = 7U, /*!< 131 ADCK cycles total sample time. */ -} lpadc_sample_time_mode_t; - -/*! - * @brief Define enumeration of hardware compare mode. - * - * After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting - * guides operation of the automatic compare function to optionally only store when the compare operation is true. - * When compare is enabled, the conversion result is compared to the compare values. - */ -typedef enum _lpadc_hardware_compare_mode -{ - kLPADC_HardwareCompareDisabled = 0U, /*!< Compare disabled. */ - kLPADC_HardwareCompareStoreOnTrue = 2U, /*!< Compare enabled. Store on true. */ - kLPADC_HardwareCompareRepeatUntilTrue = 3U, /*!< Compare enabled. Repeat channel acquisition until true. */ -} lpadc_hardware_compare_mode_t; - -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE -/*! - * @brief Define enumeration of conversion resolution mode. - * - * Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to - * #lpadc_sample_channel_mode_t - */ -typedef enum _lpadc_conversion_resolution_mode -{ - kLPADC_ConversionResolutionStandard = 0U, /*!< Standard resolution. Single-ended 12-bit conversion, Differential - 13-bit conversion with 2’s complement output. */ - kLPADC_ConversionResolutionHigh = 1U, /*!< High resolution. Single-ended 16-bit conversion; Differential 16-bit - conversion with 2’s complement output. */ -} lpadc_conversion_resolution_mode_t; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS -/*! - * @brief Define enumeration of conversion averages mode. - * - * Configure the converion average number for auto-calibration. - */ -typedef enum _lpadc_conversion_average_mode -{ - kLPADC_ConversionAverage1 = 0U, /*!< Single conversion. */ - kLPADC_ConversionAverage2 = 1U, /*!< 2 conversions averaged. */ - kLPADC_ConversionAverage4 = 2U, /*!< 4 conversions averaged. */ - kLPADC_ConversionAverage8 = 3U, /*!< 8 conversions averaged. */ - kLPADC_ConversionAverage16 = 4U, /*!< 16 conversions averaged. */ - kLPADC_ConversionAverage32 = 5U, /*!< 32 conversions averaged. */ - kLPADC_ConversionAverage64 = 6U, /*!< 64 conversions averaged. */ - kLPADC_ConversionAverage128 = 7U, /*!< 128 conversions averaged. */ -} lpadc_conversion_average_mode_t; -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - -/*! - * @brief Define enumeration of reference voltage source. - * - * For detail information, need to check the SoC's specification. - */ -typedef enum _lpadc_reference_voltage_mode -{ - kLPADC_ReferenceVoltageAlt1 = 0U, /*!< Option 1 setting. */ - kLPADC_ReferenceVoltageAlt2 = 1U, /*!< Option 2 setting. */ - kLPADC_ReferenceVoltageAlt3 = 2U, /*!< Option 3 setting. */ -} lpadc_reference_voltage_source_t; - -/*! - * @brief Define enumeration of power configuration. - * - * Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be - * possible. Refer to the device data sheet for power and performance capabilities for each setting. - */ -typedef enum _lpadc_power_level_mode -{ - kLPADC_PowerLevelAlt1 = 0U, /*!< Lowest power setting. */ - kLPADC_PowerLevelAlt2 = 1U, /*!< Next lowest power setting. */ - kLPADC_PowerLevelAlt3 = 2U, /*!< ... */ - kLPADC_PowerLevelAlt4 = 3U, /*!< Highest power setting. */ -} lpadc_power_level_mode_t; - -/*! - * @brief Define enumeration of trigger priority policy. - * - * This selection controls how higher priority triggers are handled. - */ -typedef enum _lpadc_trigger_priority_policy -{ - kLPADC_TriggerPriorityPreemptImmediately = 0U, /*!< If a higher priority trigger is detected during command - processing, the current conversion is aborted and the new - command specified by the trigger is started. */ - kLPADC_TriggerPriorityPreemptSoftly = 1U, /*!< If a higher priority trigger is received during command processing, - the current conversion is completed (including averaging iterations - and compare function if enabled) and stored to the result FIFO - before the higher priority trigger/command is initiated. */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY) && FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY - kLPADC_TriggerPriorityPreemptSubsequently = 2U, /*!< If a higher priority trigger is received during command - processing, the current command will be completed (averaging, - looping, compare) before servicing the higher priority trigger. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY */ -} lpadc_trigger_priority_policy_t; - -/*! - * @brief LPADC global configuration. - * - * This structure would used to keep the settings for initialization. - */ -typedef struct -{ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock - selection logic at the chip level and is optionally used for the ADC clock source. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - bool enableVref1LowVoltage; /*!< If voltage reference option1 input is below 1.8V, it should be "true". - If voltage reference option1 input is above 1.8V, it should be "false". */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - bool enableInDozeMode; /*!< Control system transition to Stop and Wait power modes while ADC is converting. When - enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the - ADC will wait for the current averaging iteration/FIFO storage to complete before - acknowledging stop or wait mode entry. */ -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS - lpadc_conversion_average_mode_t conversionAverageMode; /*!< Auto-Calibration Averages. */ -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - bool enableAnalogPreliminary; /*!< ADC analog circuits are pre-enabled and ready to execute conversions without - startup delays(at the cost of higher DC current consumption). */ - uint32_t powerUpDelay; /*!< When the analog circuits are not pre-enabled, the ADC analog circuits are only powered - while the ADC is active and there is a counted delay defined by this field after an - initial trigger transitions the ADC from its Idle state to allow time for the analog - circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must - result in a longer delay than the analog startup time. */ - lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for - conversions.*/ - lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */ - lpadc_trigger_priority_policy_t triggerPriorityPolicy; /*!< Control how higher priority triggers are handled, see to - lpadc_trigger_priority_policy_t. */ - bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during - command execution sequencing between LOOP iterations, between commands in a sequence, and - between conversions when command is executing in "Compare Until True" configuration. */ - uint32_t convPauseDelay; /*!< Controls the duration of pausing during command execution sequencing. The pause delay - is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing - function is enabled. The available value range is in 9-bit. */ -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - /* for FIFO0. */ - uint32_t FIFO0Watermark; /*!< FIFO0Watermark is a programmable threshold setting. When the number of datawords - stored in the ADC Result FIFO0 is greater than the value in this field, the ready flag - would be asserted to indicate stored data has reached the programmable threshold. */ - /* for FIFO1. */ - uint32_t FIFO1Watermark; /*!< FIFO1Watermark is a programmable threshold setting. When the number of datawords - stored in the ADC Result FIFO1 is greater than the value in this field, the ready flag - would be asserted to indicate stored data has reached the programmable threshold. */ -#else - /* for FIFO. */ - uint32_t FIFOWatermark; /*!< FIFOWatermark is a programmable threshold setting. When the number of datawords stored - in the ADC Result FIFO is greater than the value in this field, the ready flag would be - asserted to indicate stored data has reached the programmable threshold. */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ -} lpadc_config_t; - -/*! - * @brief Define structure to keep the configuration for conversion command. - */ -typedef struct -{ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ - lpadc_sample_channel_mode_t sampleChannelMode; /*!< Channel sample mode. */ - uint32_t channelNumber; /*!< Channel number, select the channel or channel pair. */ - uint32_t chainedNextCommandNumber; /*!< Selects the next command to be executed after this command completes. - 1-15 is available, 0 is to terminate the chain after this command. */ - bool enableAutoChannelIncrement; /*!< Loop with increment: when disabled, the "loopCount" field selects the number - of times the selected channel is converted consecutively; when enabled, the - "loopCount" field defines how many consecutive channels are converted as part - of the command execution. */ - uint32_t loopCount; /*!< Selects how many times this command executes before finish and transition to the next - command or Idle state. Command executes LOOP+1 times. 0-15 is available. */ - lpadc_hardware_average_mode_t hardwareAverageMode; /*!< Hardware average selection. */ - lpadc_sample_time_mode_t sampleTimeMode; /*!< Sample time selection. */ - - lpadc_hardware_compare_mode_t hardwareCompareMode; /*!< Hardware compare selection. */ - uint32_t hardwareCompareValueHigh; /*!< Compare Value High. The available value range is in 16-bit. */ - uint32_t hardwareCompareValueLow; /*!< Compare Value Low. The available value range is in 16-bit. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - lpadc_conversion_resolution_mode_t conversionResolutionMode; /*!< Conversion resolution mode. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG - bool enableWaitTrigger; /*!< Wait for trigger assertion before execution: when disabled, this command will be - automatically executed; when enabled, the active trigger must be asserted again before - executing this command. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ -} lpadc_conv_command_config_t; - -/*! - * @brief Define structure to keep the configuration for conversion trigger. - */ -typedef struct -{ - uint32_t targetCommandId; /*!< Select the command from command buffer to execute upon detect of the associated - trigger event. */ - uint32_t delayPower; /*!< Select the trigger delay duration to wait at the start of servicing a trigger event. - When this field is clear, then no delay is incurred. When this field is set to a non-zero - value, the duration for the delay is 2^delayPower ADCK cycles. The available value range - is 4-bit. */ - uint32_t priority; /*!< Sets the priority of the associated trigger source. If two or more triggers have the same - priority level setting, the lower order trigger event has the higher priority. The lower - value for this field is for the higher priority, the available value range is 1-bit. */ -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - uint8_t channelAFIFOSelect; /* SAR Result Destination For Channel A. */ - uint8_t channelBFIFOSelect; /* SAR Result Destination For Channel B. */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - bool enableHardwareTrigger; /*!< Enable hardware trigger source to initiate conversion on the rising edge of the - input trigger source or not. THe software trigger is always available. */ -} lpadc_conv_trigger_config_t; - -/*! - * @brief Define the structure to keep the conversion result. - */ -typedef struct -{ - uint32_t commandIdSource; /*!< Indicate the command buffer being executed that generated this result. */ - uint32_t loopCountIndex; /*!< Indicate the loop count value during command execution that generated this result. */ - uint32_t triggerIdSource; /*!< Indicate the trigger source that initiated a conversion and generated this result. */ - uint16_t convValue; /*!< Data result. */ -} lpadc_conv_result_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ -/*! - * @name Initialization & de-initialization. - * @{ - */ - -/*! - * @brief Initializes the LPADC module. - * - * @param base LPADC peripheral base address. - * @param config Pointer to configuration structure. See "lpadc_config_t". - */ -void LPADC_Init(ADC_Type *base, const lpadc_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for initial configuration. - * - * This function initializes the converter configuration structure with an available settings. The default values are: - * @code - * config->enableInDozeMode = true; - * config->enableAnalogPreliminary = false; - * config->powerUpDelay = 0x80; - * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - * config->powerLevelMode = kLPADC_PowerLevelAlt1; - * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; - * config->enableConvPause = false; - * config->convPauseDelay = 0U; - * config->FIFOWatermark = 0U; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConfig(lpadc_config_t *config); - -/*! - * @brief De-initializes the LPADC module. - * - * @param base LPADC peripheral base address. - */ -void LPADC_Deinit(ADC_Type *base); - -/*! - * @brief Switch on/off the LPADC module. - * - * @param base LPADC peripheral base address. - * @param enable switcher to the module. - */ -static inline void LPADC_Enable(ADC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= ADC_CTRL_ADCEN_MASK; - } - else - { - base->CTRL &= ~ADC_CTRL_ADCEN_MASK; - } -} - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Do reset the conversion FIFO0. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO0(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO0_MASK; -} - -/*! - * @brief Do reset the conversion FIFO1. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO1(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO1_MASK; -} -#else -/*! - * @brief Do reset the conversion FIFO. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO_MASK; -} -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * @brief Do reset the module's configuration. - * - * Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL). - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetConfig(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RST_MASK; - base->CTRL &= ~ADC_CTRL_RST_MASK; -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Get status flags. - * - * @param base LPADC peripheral base address. - * @return status flags' mask. See to #_lpadc_status_flags. - */ -static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base) -{ - return base->STAT; -} - -/*! - * @brief Clear status flags. - * - * Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for flags to be cleared. See to #_lpadc_status_flags. - */ -static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) -{ - base->STAT = mask; -} - -#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) -/*! - * @brief Get trigger status flags to indicate which trigger sequences have been completed or interrupted by a high - * priority trigger exception. - * - * @param base LPADC peripheral base address. - * @return The OR'ed value of @ref _lpadc_trigger_status_flags. - */ -static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base) -{ - return base->TSTAT; -} - -/*! - * @brief Clear trigger status flags. - * - * @param base LPADC peripheral base address. - * @param mask The mask of trigger status flags to be cleared, should be the - * OR'ed value of @ref _lpadc_trigger_status_flags. - */ -static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask) -{ - base->TSTAT = mask; -} -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enable interrupts. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. - */ -static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask) -{ - base->IE |= mask; -} - -/*! - * @brief Disable interrupts. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. - */ -static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask) -{ - base->IE &= ~mask; -} - -/*! - * @name DMA Control - * @{ - */ - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Switch on/off the DMA trigger for FIFO0 watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFO0WatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE0_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE0_MASK; - } -} - -/*! - * @brief Switch on/off the DMA trigger for FIFO1 watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFO1WatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE1_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE1_MASK; - } -} -#else -/*! - * @brief Switch on/off the DMA trigger for FIFO watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE_MASK; - } -} -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - /* @} */ - -/*! - * @name Trigger and conversion with FIFO. - * @{ - */ - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Get the count of result kept in conversion FIFOn. - * - * @param base LPADC peripheral base address. - * @param index Result FIFO index. - * @return The count of result kept in conversion FIFOn. - */ -static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index) -{ - return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL[index]) >> ADC_FCTRL_FCOUNT_SHIFT; -} - -/*! - * brief Get the result in conversion FIFOn. - * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. - * param index Result FIFO index. - * - * return Status whether FIFOn entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index); -#else -/*! - * @brief Get the count of result kept in conversion FIFO. - * - * @param base LPADC peripheral base address. - * @return The count of result kept in conversion FIFO. - */ -static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base) -{ - return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL) >> ADC_FCTRL_FCOUNT_SHIFT; -} - -/*! - * @brief Get the result in conversion FIFO. - * - * @param base LPADC peripheral base address. - * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. - * - * @return Status whether FIFO entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * @brief Configure the conversion trigger source. - * - * Each programmable trigger can launch the conversion command in command buffer. - * - * @param base LPADC peripheral base address. - * @param triggerId ID for each trigger. Typically, the available value range is from 0. - * @param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. - */ -void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for trigger's configuration. - * - * This function initializes the trigger's configuration structure with an available settings. The default values are: - * @code - * config->commandIdSource = 0U; - * config->loopCountIndex = 0U; - * config->triggerIdSource = 0U; - * config->enableHardwareTrigger = false; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config); - -/*! - * @brief Do software trigger to conversion command. - * - * @param base LPADC peripheral base address. - * @param triggerIdMask Mask value for software trigger indexes, which count from zero. - */ -static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask) -{ - /* Writes to ADCx_SWTRIG register are ignored while ADCx_CTRL[ADCEN] is clear. */ - base->SWTRIG = triggerIdMask; -} - -/*! - * @brief Configure conversion command. - * - * @param base LPADC peripheral base address. - * @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. - * @param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. - */ -void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for conversion command's configuration. - * - * This function initializes the conversion command's configuration structure with an available settings. The default - * values are: - * @code - * config->sampleScaleMode = kLPADC_SampleFullScale; - * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; - * config->channelNumber = 0U; - * config->chainedNextCmdNumber = 0U; - * config->enableAutoChannelIncrement = false; - * config->loopCount = 0U; - * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - * config->sampleTimeMode = kLPADC_SampleTimeADCK3; - * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - * config->hardwareCompareValueHigh = 0U; - * config->hardwareCompareValueLow = 0U; - * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; - * config->enableWaitTrigger = false; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config); - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS -/*! - * @brief Enable the calibration function. - * - * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes - * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value - * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- - * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the - * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. - * - * @param base LPADC peripheral base address. - * @param enable switcher to the calibration function. - */ -void LPADC_EnableCalibration(ADC_Type *base, bool enable); -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! - * @brief Set proper offset value to trim ADC. - * - * To minimize the offset during normal operation, software should read the conversion result from - * the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register. - * - * @param base LPADC peripheral base address. - * @param value Setting offset value. - */ -static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value) -{ - base->OFSTRIM = (value & ADC_OFSTRIM_OFSTRIM_MASK) >> ADC_OFSTRIM_OFSTRIM_SHIFT; -} - -/*! - * @brief Do auto calibration. - * - * Calibration function should be executed before using converter in application. It used the software trigger and a - * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API - * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) - * -LPADC_SetConvTriggerConfig(...) - * - * @param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base); -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! - * @brief Set proper offset value to trim ADC. - * - * Set the offset trim value for offset calibration manually. - * - * @param base LPADC peripheral base address. - * @param valueA Setting offset value A. - * @param valueB Setting offset value B. - * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. - */ -static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t valueA, uint32_t valueB) -{ - base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB); -} -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ - -/*! - * @brief Enable the offset calibration function. - * - * @param base LPADC peripheral base address. - * @param enable switcher to the calibration function. - */ -static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= ADC_CTRL_CALOFS_MASK; - } - else - { - base->CTRL &= ~ADC_CTRL_CALOFS_MASK; - } -} - -/*! - * @brief Do offset calibration. - * - * @param base LPADC peripheral base address. - */ -void LPADC_DoOffsetCalibration(ADC_Type *base); - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ -/*! - * brief Do auto calibration. - * - * param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base); -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ - -/* @} */ - -#if defined(__cplusplus) -} -#endif -/*! - * @} - */ -#endif /* _FSL_LPADC_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mcan.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mcan.c deleted file mode 100644 index 9de92174731..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mcan.c +++ /dev/null @@ -1,1744 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_mcan.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.mcan" -#endif - -/* According to CiA doc 1301 v1.0.0, specified data/nominal phase sample point postion for CAN FD at 80 MHz. */ -#define IDEAL_DATA_SP_1 (800U) -#define IDEAL_DATA_SP_2 (750U) -#define IDEAL_DATA_SP_3 (700U) -#define IDEAL_DATA_SP_4 (625U) -#define IDEAL_NOMINAL_SP (800U) - -/* According to CiA doc 301 v4.2.0 and previous version, specified sample point postion for classic CAN. */ -#define IDEAL_SP_LOW (750U) -#define IDEAL_SP_MID (800U) -#define IDEAL_SP_HIGH (875U) -#define IDEAL_SP_FACTOR (1000U) - -#define MAX_DSJW (CAN_DBTP_DSJW_MASK >> CAN_DBTP_DSJW_SHIFT) -#define MAX_DTSEG2 (CAN_DBTP_DTSEG2_MASK >> CAN_DBTP_DTSEG2_SHIFT) -#define MAX_DTSEG1 (CAN_DBTP_DTSEG1_MASK >> CAN_DBTP_DTSEG1_SHIFT) -#define MAX_DBRP (CAN_DBTP_DBRP_MASK >> CAN_DBTP_DBRP_SHIFT) - -#define MAX_NSJW (CAN_NBTP_NSJW_MASK >> CAN_NBTP_NSJW_SHIFT) -#define MAX_NTSEG2 (CAN_NBTP_NTSEG2_MASK >> CAN_NBTP_NTSEG2_SHIFT) -#define MAX_NTSEG1 (CAN_NBTP_NTSEG1_MASK >> CAN_NBTP_NTSEG1_SHIFT) -#define MAX_NBRP (CAN_NBTP_NBRP_MASK >> CAN_NBTP_NBRP_SHIFT) - -#define DBTP_MAX_TIME_QUANTA (1U + MAX_DTSEG2 + 1U + MAX_DTSEG1 + 1U) -#define DBTP_MIN_TIME_QUANTA (3U) -#define NBTP_MAX_TIME_QUANTA (1U + MAX_NTSEG2 + 1U + MAX_NTSEG1 + 1U) -#define NBTP_MIN_TIME_QUANTA (3U) - -#define MAX_TDCOFF ((uint32_t)CAN_TDCR_TDCO_MASK >> CAN_TDCR_TDCO_SHIFT) - -#define MAX_CANFD_BAUDRATE (8000000U) -#define MAX_CAN_BAUDRATE (1000000U) - -/*! @brief MCAN Internal State. */ -enum _mcan_state -{ - kMCAN_StateIdle = 0x0, /*!< MB/RxFIFO idle.*/ - kMCAN_StateRxData = 0x1, /*!< MB receiving.*/ - kMCAN_StateRxRemote = 0x2, /*!< MB receiving remote reply.*/ - kMCAN_StateTxData = 0x3, /*!< MB transmitting.*/ - kMCAN_StateTxRemote = 0x4, /*!< MB transmitting remote request.*/ - kMCAN_StateRxFifo = 0x5, /*!< RxFIFO receiving.*/ -}; - -/* Typedef for interrupt handler. */ -typedef void (*mcan_isr_t)(CAN_Type *base, mcan_handle_t *handle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get the MCAN instance from peripheral base address. - * - * @param base MCAN peripheral base address. - * @return MCAN instance. - */ -static uint32_t MCAN_GetInstance(CAN_Type *base); - -/*! - * @brief Reset the MCAN instance. - * - * @param base MCAN peripheral base address. - */ -static void MCAN_Reset(CAN_Type *base); - -/*! - * @brief Calculates the segment values for a single bit time for classical CAN - * - * @param baudRate The data speed in bps - * @param tqNum Number of time quantas per bit, range in 4~385 - * @param pconfig Pointer to the MCAN timing configuration structure. - */ -static void MCAN_GetSegments(uint32_t baudRate, uint32_t tqNum, mcan_timing_config_t *pconfig); - -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) -/*! - * @brief Calculates the segment values for a single bit time for CANFD bus data baud Rate - * - * @param baudRate The canfd bus data speed in bps - * @param tqNum Number of time quanta per bit, range in 3 ~ 33 - * @param pconfig Pointer to the MCAN timing configuration structure. - */ -static void MCAN_FDGetSegments(uint32_t baudRateFD, uint32_t tqNum, mcan_timing_config_t *pconfig); - -#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */ - -/*! - * @brief Get the element's address when read receive fifo 0. - * - * @param base MCAN peripheral base address. - * @return Address of the element in receive fifo 0. - */ -static uint32_t MCAN_GetRxFifo0ElementAddress(CAN_Type *base); - -/*! - * @brief Get the element's address when read receive fifo 1. - * - * @param base MCAN peripheral base address. - * @return Address of the element in receive fifo 1. - */ -static uint32_t MCAN_GetRxFifo1ElementAddress(CAN_Type *base); - -/*! - * @brief Get the element's address when read receive buffer. - * - * @param base MCAN peripheral base address. - * @param idx Number of the erceive buffer element. - * @return Address of the element in receive buffer. - */ -static uint32_t MCAN_GetRxBufferElementAddress(CAN_Type *base, uint8_t idx); - -/*! - * @brief Get the element's address when read transmit buffer. - * - * @param base MCAN peripheral base address. - * @param idx Number of the transmit buffer element. - * @return Address of the element in transmit buffer. - */ -static uint32_t MCAN_GetTxBufferElementAddress(CAN_Type *base, uint8_t idx); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of MCAN handle. */ -static mcan_handle_t *s_mcanHandle[FSL_FEATURE_SOC_LPC_CAN_COUNT]; - -/* Array of MCAN peripheral base address. */ -static CAN_Type *const s_mcanBases[] = CAN_BASE_PTRS; - -/* Array of MCAN IRQ number. */ -static const IRQn_Type s_mcanIRQ[][2] = CAN_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of MCAN clock name. */ -static const clock_ip_name_t s_mcanClock[] = MCAN_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_MCAN_HAS_NO_RESET) && FSL_FEATURE_MCAN_HAS_NO_RESET) -/*! @brief Pointers to MCAN resets for each instance. */ -static const reset_ip_name_t s_mcanResets[] = MCAN_RSTS; -#endif - -/* MCAN ISR for transactional APIs. */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -static mcan_isr_t s_mcanIsr = (mcan_isr_t)DefaultISR; -#else -static mcan_isr_t s_mcanIsr; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t MCAN_GetInstance(CAN_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_mcanBases); instance++) - { - if (s_mcanBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_mcanBases)); - - return instance; -} - -static void MCAN_Reset(CAN_Type *base) -{ - /* Set INIT bit. */ - base->CCCR |= CAN_CCCR_INIT_MASK; - /* Confirm the value has been accepted. */ - while (0U == (base->CCCR & CAN_CCCR_INIT_MASK)) - { - } - - /* Set CCE bit to have access to the protected configuration registers, - and clear some status registers. */ - base->CCCR |= CAN_CCCR_CCE_MASK; -} - -/*! - * brief Initializes an MCAN instance. - * - * This function initializes the MCAN module with user-defined settings. - * This example shows how to set up the mcan_config_t parameters and how - * to call the MCAN_Init function by passing in these parameters. - * code - * mcan_config_t config; - * config->baudRateA = 500000U; - * config->baudRateD = 1000000U; - * config->enableCanfdNormal = false; - * config->enableCanfdSwitch = false; - * config->enableLoopBackInt = false; - * config->enableLoopBackExt = false; - * config->enableBusMon = false; - * MCAN_Init(CANFD0, &config, 8000000UL); - * endcode - * - * param base MCAN peripheral base address. - * param config Pointer to the user-defined configuration structure. - * param sourceClock_Hz MCAN Protocol Engine clock source frequency in Hz. - */ -void MCAN_Init(CAN_Type *base, const mcan_config_t *config, uint32_t sourceClock_Hz) -{ - mcan_timing_config_t timingCfg = config->timingConfig; - uint32_t quantum = 0U; - uint32_t tqFre = 0U; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable MCAN clock. */ - CLOCK_EnableClock(s_mcanClock[MCAN_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_MCAN_HAS_NO_RESET) && FSL_FEATURE_MCAN_HAS_NO_RESET) - /* Reset the MCAN module */ - RESET_PeripheralReset(s_mcanResets[MCAN_GetInstance(base)]); -#endif - - MCAN_Reset(base); - - if (config->enableLoopBackInt) - { - base->CCCR |= CAN_CCCR_TEST_MASK | CAN_CCCR_MON_MASK; - base->TEST |= CAN_TEST_LBCK_MASK; - } - if (config->enableLoopBackExt) - { - base->CCCR |= CAN_CCCR_TEST_MASK; - base->TEST |= CAN_TEST_LBCK_MASK; - } - if (config->enableBusMon) - { - base->CCCR |= CAN_CCCR_MON_MASK; - } - - /* Nominal quantum = 1 + (NTSEG1 + 1) + (NTSEG2 + 1) */ - quantum = (1U + ((uint32_t)timingCfg.seg1 + 1U) + ((uint32_t)timingCfg.seg2 + 1U)); - tqFre = config->baudRateA * quantum; - - /* Assertion: Source clock should greater than baud rate * quantum. */ - assert((tqFre != 0U) && (tqFre <= sourceClock_Hz)); - - /* Check whether Nominal Bit Rate Prescaler is overflow. */ - if ((sourceClock_Hz / tqFre - 1U) > 0x1FFU) - { - timingCfg.preDivider = 0x1FFU; - } - else - { - timingCfg.preDivider = (uint16_t)(sourceClock_Hz / tqFre) - 1U; - } - /* Update actual timing characteristic to set baud rate of arbitration phase. */ - MCAN_SetArbitrationTimingConfig(base, &timingCfg); - -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) - if (config->enableCanfdNormal) - { - base->CCCR |= CAN_CCCR_FDOE_MASK; - } - if (config->enableCanfdSwitch) - { - /* Enable the CAN FD mode and Bit Rate Switch feature. */ - base->CCCR |= CAN_CCCR_FDOE_MASK | CAN_CCCR_BRSE_MASK; - - /* Data quantum = 1 + (NTSEG1 + 1) + (NTSEG2 + 1) */ - quantum = (1U + ((uint32_t)timingCfg.dataseg1 + 1U) + ((uint32_t)timingCfg.dataseg2 + 1U)); - tqFre = config->baudRateD * quantum; - assert((tqFre != 0U) && (tqFre <= sourceClock_Hz)); - - /* Check whether Data Bit Rate Prescaler is overflow. */ - if ((sourceClock_Hz / tqFre - 1U) > 0x1FU) - { - timingCfg.datapreDivider = 0x1FU; - } - else - { - timingCfg.datapreDivider = (uint16_t)(sourceClock_Hz / tqFre) - 1U; - } - - /* Update actual timing characteristic to set baud rate of data phase. */ - MCAN_SetDataTimingConfig(base, &timingCfg); - if (!config->enableLoopBackInt && !config->enableLoopBackExt) - { - /* Enable the Transceiver Delay Compensation. */ - base->DBTP |= CAN_DBTP_TDC_MASK; - /* Cleaning previous TDCO Setting. */ - base->TDCR &= ~CAN_TDCR_TDCO_MASK; - /* The TDC offset should be configured as shown in this equation : offset = (DTSEG1 + 2) * (DBRP + 1) */ - if (((uint32_t)timingCfg.dataseg1 + 2U) * (timingCfg.datapreDivider + 1U) < MAX_TDCOFF) - { - base->TDCR |= CAN_TDCR_TDCO(((uint32_t)timingCfg.dataseg1 + 2U) * (timingCfg.datapreDivider + 1U)); - } - else - { - /* Set the Transceiver Delay Compensation offset to max value. */ - base->TDCR |= CAN_TDCR_TDCO(MAX_TDCOFF); - } - } - } -#endif -} - -/*! - * brief Deinitializes an MCAN instance. - * - * This function deinitializes the MCAN module. - * - * param base MCAN peripheral base address. - */ -void MCAN_Deinit(CAN_Type *base) -{ - /* Reset all Register Contents. */ - MCAN_Reset(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable MCAN clock. */ - CLOCK_DisableClock(s_mcanClock[MCAN_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief MCAN enters normal mode. - * - * After initialization, INIT bit in CCCR register must be cleared to enter - * normal mode thus synchronizes to the CAN bus and ready for communication. - * - * param base MCAN peripheral base address. - */ -void MCAN_EnterNormalMode(CAN_Type *base) -{ - /* Reset INIT bit to enter normal mode. */ - base->CCCR &= ~CAN_CCCR_INIT_MASK; - while (0U != (base->CCCR & CAN_CCCR_INIT_MASK)) - { - } -} - -/*! - * brief Gets the default configuration structure. - * - * This function initializes the MCAN configuration structure to default values. The default - * values are as follows. - * config->baudRateA = 500000U; - * config->baudRateD = 1000000U; - * config->enableCanfdNormal = false; - * config->enableCanfdSwitch = false; - * config->enableLoopBackInt = false; - * config->enableLoopBackExt = false; - * config->enableBusMon = false; - * - * param config Pointer to the MCAN configuration structure. - */ -void MCAN_GetDefaultConfig(mcan_config_t *config) -{ - /* Assertion. */ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* Initialize MCAN Module config struct with default value. */ - config->baudRateA = 500000U; - config->baudRateD = 2000000U; - config->enableCanfdNormal = false; - config->enableCanfdSwitch = false; - config->enableLoopBackInt = false; - config->enableLoopBackExt = false; - config->enableBusMon = false; - /* Default protocol timing configuration, time quantum is 16. */ - config->timingConfig.seg1 = 0xAU; - config->timingConfig.seg2 = 0x3U; - config->timingConfig.rJumpwidth = 0x3U; -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) - config->timingConfig.dataseg1 = 0xAU; - config->timingConfig.dataseg2 = 0x3U; - config->timingConfig.datarJumpwidth = 0x3U; -#endif -} - -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) -/*! - * @brief Calculates the segment values for a single bit time for CANFD bus data baud Rate - * - * @param baudRate The canfd bus data speed in bps - * @param tqNum Number of time quanta per bit, range in 3 ~ 33 - * @param pconfig Pointer to the MCAN timing configuration structure. - */ -static void MCAN_FDGetSegments(uint32_t baudRateFD, uint32_t tqNum, mcan_timing_config_t *pconfig) -{ - uint32_t ideal_sp, seg1Temp; - - /* get ideal sample point. */ - if (baudRateFD <= 1000000U) - { - ideal_sp = IDEAL_DATA_SP_1; - } - else if (baudRateFD <= 2000000U) - { - ideal_sp = IDEAL_DATA_SP_2; - } - else if (baudRateFD <= 4000000U) - { - ideal_sp = IDEAL_DATA_SP_3; - } - else - { - ideal_sp = IDEAL_DATA_SP_4; - } - /* distribute time quanta. */ - pconfig->dataseg2 = (uint8_t)(tqNum - (tqNum * ideal_sp) / (uint32_t)IDEAL_SP_FACTOR - 1U); - - if (pconfig->dataseg2 > MAX_DTSEG2) - { - pconfig->dataseg2 = MAX_DTSEG2; - } - - seg1Temp = tqNum - pconfig->dataseg2 - 3U; - - if (seg1Temp > MAX_DTSEG1) - { - pconfig->dataseg2 = (uint8_t)(tqNum - MAX_DTSEG1 - 3U); - pconfig->dataseg1 = MAX_DTSEG1; - } - else - { - pconfig->dataseg1 = (uint8_t)seg1Temp; - } - - /* sjw is the minimum value of phaseSeg1 and phaseSeg2. */ - pconfig->datarJumpwidth = (pconfig->dataseg1 > pconfig->dataseg2) ? pconfig->dataseg2 : pconfig->dataseg1; - if (pconfig->datarJumpwidth > (uint8_t)MAX_DSJW) - { - pconfig->datarJumpwidth = (uint8_t)MAX_DSJW; - } -} - -/*! - * brief Calculates the improved timing values by specific bit rate for CAN FD nominal phase. - * - * This function use to calculates the CAN FD nominal phase timing values according to the given nominal phase bit rate. - * The calculation is based on the recommendation of the CiA 1301 v1.0.0 document. - * - * param baudRate The CAN FD nominal phase speed in bps defined by user, should be less than or equal to 1Mbps. - * param sourceClock_Hz The Source clock frequency in Hz. - * param pconfig Pointer to the MCAN timing configuration structure. - * - * return TRUE if timing configuration found, FALSE if failed to find configuration. - */ -static bool MCAN_CalculateImprovedNominalTimingValues(uint32_t baudRate, - uint32_t sourceClock_Hz, - mcan_timing_config_t *pconfig) -{ - uint32_t clk; /* the clock is tqNumb x baudRate. */ - uint32_t tqNum; /* Numbers of TQ. */ - uint32_t seg1Temp; - bool fgRet = false; - uint32_t spTemp = 1000U; - mcan_timing_config_t configTemp; - - /* Auto Improved Protocal timing for NBTP. */ - for (tqNum = NBTP_MAX_TIME_QUANTA; tqNum >= NBTP_MIN_TIME_QUANTA; tqNum--) - { - clk = baudRate * tqNum; - if (clk > sourceClock_Hz) - { - continue; /* tqNum too large, clk has been exceed sourceClock_Hz. */ - } - - if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) - { - continue; /* Non-supporting: the frequency of clock source is not divisible by target baud rate, the user - should change a divisible baud rate. */ - } - - configTemp.preDivider = (uint16_t)(sourceClock_Hz / clk - 1U); - if (configTemp.preDivider > MAX_NBRP) - { - break; /* The frequency of source clock is too large or the baud rate is too small, the pre-divider could - not handle it. */ - } - /* Calculates the best timing configuration under current tqNum. */ - configTemp.seg2 = (uint8_t)(tqNum - (tqNum * IDEAL_NOMINAL_SP) / (uint32_t)IDEAL_SP_FACTOR - 1U); - - if (configTemp.seg2 > MAX_NTSEG2) - { - configTemp.seg2 = MAX_NTSEG2; - } - - seg1Temp = tqNum - configTemp.seg2 - 3U; - - if (seg1Temp > MAX_NTSEG1) - { - configTemp.seg2 = (uint8_t)(tqNum - MAX_NTSEG1 - 3U); - configTemp.seg1 = MAX_NTSEG1; - } - else - { - configTemp.seg1 = (uint8_t)seg1Temp; - } - - /* sjw is the minimum value of phaseSeg1 and phaseSeg2. */ - configTemp.rJumpwidth = (configTemp.seg1 > configTemp.seg2) ? configTemp.seg2 : configTemp.seg1; - if (configTemp.rJumpwidth > (uint8_t)MAX_NSJW) - { - configTemp.rJumpwidth = (uint8_t)MAX_NSJW; - } - /* Determine whether the calculated timing configuration can get the optimal sampling point. */ - if (((((uint32_t)configTemp.seg2 + 1U) * 1000U) / tqNum) < spTemp) - { - spTemp = (((uint32_t)configTemp.seg2 + 1U) * 1000U) / tqNum; - pconfig->preDivider = configTemp.preDivider; - pconfig->rJumpwidth = configTemp.rJumpwidth; - pconfig->seg1 = configTemp.seg1; - pconfig->seg2 = configTemp.seg2; - } - fgRet = true; - } - return fgRet; -} -/*! - * brief Calculates the improved timing values by specific baudrates for CANFD - * - * param baudRate The CANFD bus control speed in bps defined by user - * param baudRateFD The CANFD bus data speed in bps defined by user - * param sourceClock_Hz The Source clock data speed in bps. - * param pconfig Pointer to the MCAN timing configuration structure. - * - * return TRUE if timing configuration found, FALSE if failed to find configuration - */ -bool MCAN_FDCalculateImprovedTimingValues(uint32_t baudRate, - uint32_t baudRateFD, - uint32_t sourceClock_Hz, - mcan_timing_config_t *pconfig) -{ - uint32_t clk; - uint32_t tqNum; /* Numbers of TQ. */ - bool fgRet = false; - uint16_t preDividerTemp = 1U; - /* observe baud rate maximums */ - assert(baudRate <= MAX_CAN_BAUDRATE); - assert(baudRateFD <= MAX_CANFD_BAUDRATE); - /* Data phase bit rate need greater or equal to nominal phase bit rate. */ - assert(baudRate <= baudRateFD); - - if (baudRate < baudRateFD) - { - /* To minimize errors when processing FD frames, try to get the same bit rate prescaler value for nominal phase - and data phase. */ - while (MCAN_CalculateImprovedNominalTimingValues(baudRate, sourceClock_Hz / preDividerTemp, pconfig)) - { - pconfig->datapreDivider = 0U; - for (tqNum = DBTP_MAX_TIME_QUANTA; tqNum >= DBTP_MIN_TIME_QUANTA; tqNum--) - { - clk = baudRateFD * tqNum; - if (clk > sourceClock_Hz) - { - continue; /* tqNumbrs too large, clk x tqNumbrs has been exceed sourceClock_Hz. */ - } - - if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) - { - continue; /* Non-supporting: the frequency of clock source is not divisible by target bit rate. */ - } - - pconfig->datapreDivider = (uint16_t)(sourceClock_Hz / clk - 1U); - - if (pconfig->datapreDivider > MAX_DBRP) - { - break; /* The frequency of source clock is too large or the bit rate is too small, the pre-divider - could not handle it. */ - } - - if (pconfig->datapreDivider < ((pconfig->preDivider + 1U) * preDividerTemp - 1U)) - { - continue; /* try to get the same bit rate prescaler value for nominal phase and data phase. */ - } - else if (pconfig->datapreDivider == ((pconfig->preDivider + 1U) * preDividerTemp - 1U)) - { - /* Calculates the best data phase timing configuration under current tqNum. */ - MCAN_FDGetSegments(baudRateFD, tqNum, pconfig); - fgRet = true; - break; - } - else - { - break; - } - } - - if (fgRet) - { - /* Find same bit rate prescaler (BRP) configuration in both nominal and data bit timing configurations. - */ - pconfig->preDivider = (pconfig->preDivider + 1U) * preDividerTemp - 1U; - break; - } - else - { - if ((pconfig->datapreDivider <= MAX_DBRP) && (pconfig->datapreDivider != 0U)) - { - /* Can't find same data bit rate prescaler (BRP) configuration under current nominal phase bit rate - prescaler, double the nominal phase bit rate prescaler and recalculate. */ - preDividerTemp++; - } - else - { - break; - } - } - } - } - else - { - if (MCAN_CalculateImprovedTimingValues(baudRate, sourceClock_Hz, pconfig)) - { - /* No need data phase timing configuration, data phase rate equal to nominal phase rate, user don't use Brs - feature. */ - pconfig->datapreDivider = 0U; - pconfig->datarJumpwidth = 0U; - pconfig->dataseg1 = 0U; - pconfig->dataseg2 = 0U; - fgRet = true; - } - } - - return fgRet; -} - -/*! - * brief Sets the MCAN protocol data phase timing characteristic. - * - * This function gives user settings to CAN bus timing characteristic. - * The function is for an experienced user. For less experienced users, call - * the MCAN_Init() and fill the baud rate field with a desired value. - * This provides the default data phase timing characteristics. - * - * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate - * set in MCAN_Init(). - * - * param base MCAN peripheral base address. - * param config Pointer to the timing configuration structure. - */ -void MCAN_SetDataTimingConfig(CAN_Type *base, const mcan_timing_config_t *config) -{ - /* Assertion. */ - assert(NULL != config); - - /* Cleaning previous Timing Setting. */ - base->DBTP &= ~(CAN_DBTP_DSJW_MASK | CAN_DBTP_DTSEG2_MASK | CAN_DBTP_DTSEG1_MASK | CAN_DBTP_DBRP_MASK); - - /* Updating Timing Setting according to configuration structure. */ - base->DBTP |= (CAN_DBTP_DBRP(config->datapreDivider) | CAN_DBTP_DSJW(config->datarJumpwidth) | - CAN_DBTP_DTSEG1(config->dataseg1) | CAN_DBTP_DTSEG2(config->dataseg2)); -} - -/*! - * brief Set Baud Rate of MCAN FD mode. - * - * This function set the baud rate of MCAN FD base on MCAN_FDCalculateImprovedTimingValues API calculated timing values. - * - * param base MCAN peripheral base address. - * param sourceClock_Hz Source Clock in Hz. - * param baudRateN_Bps Nominal Baud Rate in Bps. - * param baudRateD_Bps Data Baud Rate in Bps. - * return kStatus_Success - Set CAN FD baud rate (include Nominal and Data phase) successfully. - */ -status_t MCAN_SetBaudRateFD(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateN_Bps, uint32_t baudRateD_Bps) -{ - mcan_timing_config_t timingCfg; - - if (MCAN_FDCalculateImprovedTimingValues(baudRateN_Bps, baudRateD_Bps, sourceClock_Hz, &timingCfg)) - { - /* Enable write access to the protected conï¬guration registers */ - base->CCCR |= CAN_CCCR_INIT_MASK; - while (0U == (base->CCCR & CAN_CCCR_INIT_MASK)) - { - } - base->CCCR |= CAN_CCCR_CCE_MASK; - /* Update actual timing characteristic. */ - MCAN_SetArbitrationTimingConfig(base, &timingCfg); - MCAN_SetDataTimingConfig(base, &timingCfg); - /* Update TDCO value when not enable loopback mode */ - if (0U == (base->TEST & CAN_TEST_LBCK_MASK)) - { - /* Cleaning previous TDCO Setting. */ - base->TDCR &= ~CAN_TDCR_TDCO_MASK; - /* The TDC offset should be configured as shown in this equation : offset = (DTSEG1 + 2) * (DBRP + 1) */ - if (((uint32_t)timingCfg.dataseg1 + 2U) * (timingCfg.datapreDivider + 1U) < MAX_TDCOFF) - { - base->TDCR |= CAN_TDCR_TDCO(((uint32_t)timingCfg.dataseg1 + 2U) * (timingCfg.datapreDivider + 1U)); - } - else - { - /* Set the Transceiver Delay Compensation offset to max value. */ - base->TDCR |= CAN_TDCR_TDCO(MAX_TDCOFF); - } - } - MCAN_EnterNormalMode(base); - return kStatus_Success; - } - else - { - return kStatus_Fail; - } -} -#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */ - -/*! - * @brief Calculates the segment values for a single bit time for classical CAN - * - * @param baudRate The data speed in bps - * @param tqNum Number of time quantas per bit, range in 4~385 - * @param pconfig Pointer to the MCAN timing configuration structure. - */ -static void MCAN_GetSegments(uint32_t baudRate, uint32_t tqNum, mcan_timing_config_t *pconfig) -{ - uint32_t ideal_sp, seg1Temp; - - /* get ideal sample point. */ - if (baudRate >= 1000000U) - { - ideal_sp = IDEAL_SP_LOW; - } - else if (baudRate >= 800000U) - { - ideal_sp = IDEAL_SP_MID; - } - else - { - ideal_sp = IDEAL_SP_HIGH; - } - - /* distribute time quanta. */ - pconfig->seg2 = (uint8_t)(tqNum - (tqNum * ideal_sp) / (uint32_t)IDEAL_SP_FACTOR - 1U); - - if (pconfig->seg2 > MAX_NTSEG2) - { - pconfig->seg2 = MAX_NTSEG2; - } - - seg1Temp = tqNum - pconfig->seg2 - 3U; - - if (seg1Temp > MAX_NTSEG1) - { - pconfig->seg2 = (uint8_t)(tqNum - MAX_NTSEG1 - 3U); - pconfig->seg1 = MAX_NTSEG1; - } - else - { - pconfig->seg1 = (uint8_t)seg1Temp; - } - - /* sjw is the minimum value of phaseSeg1 and phaseSeg2. */ - pconfig->rJumpwidth = (pconfig->seg1 > pconfig->seg2) ? pconfig->seg2 : pconfig->seg1; - if (pconfig->rJumpwidth > (uint8_t)MAX_NSJW) - { - pconfig->rJumpwidth = (uint8_t)MAX_NSJW; - } -} - -/*! - * brief Calculates the improved timing values by specific baudrates for classical CAN - * - * param baudRate The classical CAN speed in bps defined by user - * param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching - * param pconfig Pointer to the MCAN timing configuration structure. - * - * return TRUE if timing configuration found, FALSE if failed to find configuration - */ -bool MCAN_CalculateImprovedTimingValues(uint32_t baudRate, uint32_t sourceClock_Hz, mcan_timing_config_t *pconfig) -{ - uint32_t clk; /* the clock is tqNumb x baudRate. */ - uint32_t tqNum; /* Numbers of TQ. */ - bool fgRet = false; - uint32_t spTemp = 1000U; - mcan_timing_config_t configTemp = {0}; - /* observe baud rate maximums. */ - assert(baudRate <= MAX_CAN_BAUDRATE); - - /* Auto Improved Protocal timing for NBTP. */ - for (tqNum = NBTP_MAX_TIME_QUANTA; tqNum >= NBTP_MIN_TIME_QUANTA; tqNum--) - { - clk = baudRate * tqNum; - if (clk > sourceClock_Hz) - { - continue; /* tqNum too large, clk has been exceed sourceClock_Hz. */ - } - - if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) - { - continue; /* Non-supporting: the frequency of clock source is not divisible by target baud rate, the user - should change a divisible baud rate. */ - } - - configTemp.preDivider = (uint16_t)(sourceClock_Hz / clk - 1U); - if (configTemp.preDivider > MAX_NBRP) - { - break; /* The frequency of source clock is too large or the baud rate is too small, the pre-divider could - not handle it. */ - } - /* Calculates the best timing configuration under current tqNum. */ - MCAN_GetSegments(baudRate, tqNum, &configTemp); - /* Determine whether the calculated timing configuration can get the optimal sampling point. */ - if (((((uint32_t)configTemp.seg2 + 1U) * 1000U) / tqNum) < spTemp) - { - spTemp = (((uint32_t)configTemp.seg2 + 1U) * 1000U) / tqNum; - pconfig->preDivider = configTemp.preDivider; - pconfig->rJumpwidth = configTemp.rJumpwidth; - pconfig->seg1 = configTemp.seg1; - pconfig->seg2 = configTemp.seg2; - } - fgRet = true; - } - return fgRet; -} -/*! - * brief Set Baud Rate of MCAN classic mode. - * - * This function set the baud rate of MCAN base on MCAN_CalculateImprovedTimingValues() API calculated timing values. - * - * param base MCAN peripheral base address. - * param sourceClock_Hz Source Clock in Hz. - * param baudRate_Bps Baud Rate in Bps. - * return kStatus_Success - Set CAN baud rate (only has Nominal phase) successfully. - */ -status_t MCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Bps) -{ - mcan_timing_config_t timingCfg; - - if (MCAN_CalculateImprovedTimingValues(baudRate_Bps, sourceClock_Hz, &timingCfg)) - { - /* Enable write access to the protected conï¬guration registers */ - base->CCCR |= CAN_CCCR_INIT_MASK; - while (0U == (base->CCCR & CAN_CCCR_INIT_MASK)) - { - } - base->CCCR |= CAN_CCCR_CCE_MASK; - /* Update actual timing characteristic. */ - MCAN_SetArbitrationTimingConfig(base, &timingCfg); - MCAN_EnterNormalMode(base); - return kStatus_Success; - } - else - { - return kStatus_Fail; - } -} - -/*! - * brief Sets the MCAN protocol arbitration phase timing characteristic. - * - * This function gives user settings to CAN bus timing characteristic. - * The function is for an experienced user. For less experienced users, call - * the MCAN_Init() and fill the baud rate field with a desired value. - * This provides the default arbitration phase timing characteristics. - * - * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate - * set in MCAN_Init(). - * - * param base MCAN peripheral base address. - * param config Pointer to the timing configuration structure. - */ -void MCAN_SetArbitrationTimingConfig(CAN_Type *base, const mcan_timing_config_t *config) -{ - /* Assertion. */ - assert(NULL != config); - - /* Cleaning previous Timing Setting. */ - base->NBTP &= ~(CAN_NBTP_NSJW_MASK | CAN_NBTP_NTSEG2_MASK | CAN_NBTP_NTSEG1_MASK | CAN_NBTP_NBRP_MASK); - - /* Updating Timing Setting according to configuration structure. */ - base->NBTP |= (CAN_NBTP_NBRP(config->preDivider) | CAN_NBTP_NSJW(config->rJumpwidth) | - CAN_NBTP_NTSEG1(config->seg1) | CAN_NBTP_NTSEG2(config->seg2)); -} - -/*! - * brief Set filter configuration. - * - * This function sets remote and non masking frames in global filter configuration, - * also the start address, list size in standard/extended ID filter configuration. - * - * param base MCAN peripheral base address. - * param config The MCAN filter configuration. - */ -void MCAN_SetFilterConfig(CAN_Type *base, const mcan_frame_filter_config_t *config) -{ - /* Set global configuration of remote/nonmasking frames, set filter address and list size. */ - if (config->idFormat == kMCAN_FrameIDStandard) - { - base->GFC |= CAN_GFC_RRFS(config->remFrame) | CAN_GFC_ANFS(config->nmFrame); - base->SIDFC |= CAN_SIDFC_FLSSA(config->address >> CAN_SIDFC_FLSSA_SHIFT) | CAN_SIDFC_LSS(config->listSize); - } - else - { - base->GFC |= CAN_GFC_RRFE(config->remFrame) | CAN_GFC_ANFE(config->nmFrame); - base->XIDFC |= CAN_XIDFC_FLESA(config->address >> CAN_XIDFC_FLESA_SHIFT) | CAN_XIDFC_LSE(config->listSize); - } -} - -/*! - * brief Configures an MCAN receive fifo 0 buffer. - * - * This function sets start address, element size, watermark, operation mode - * and datafield size of the recieve fifo 0. - * - * param base MCAN peripheral base address. - * param config The receive fifo 0 configuration structure. - */ -void MCAN_SetRxFifo0Config(CAN_Type *base, const mcan_rx_fifo_config_t *config) -{ - /* Set Rx FIFO 0 start address, element size, watermark, operation mode. */ - base->RXF0C |= CAN_RXF0C_F0SA(config->address >> CAN_RXF0C_F0SA_SHIFT) | CAN_RXF0C_F0S(config->elementSize) | - CAN_RXF0C_F0WM(config->watermark) | CAN_RXF0C_F0OM(config->opmode); - /* Set Rx FIFO 0 data field size */ - base->RXESC |= CAN_RXESC_F0DS(config->datafieldSize); -} - -/*! - * brief Configures an MCAN receive fifo 1 buffer. - * - * This function sets start address, element size, watermark, operation mode - * and datafield size of the recieve fifo 1. - * - * param base MCAN peripheral base address. - * param config The receive fifo 1 configuration structure. - */ -void MCAN_SetRxFifo1Config(CAN_Type *base, const mcan_rx_fifo_config_t *config) -{ - /* Set Rx FIFO 1 start address, element size, watermark, operation mode. */ - base->RXF1C |= CAN_RXF1C_F1SA(config->address >> CAN_RXF1C_F1SA_SHIFT) | CAN_RXF1C_F1S(config->elementSize) | - CAN_RXF1C_F1WM(config->watermark) | CAN_RXF1C_F1OM(config->opmode); - /* Set Rx FIFO 1 data field size */ - base->RXESC |= CAN_RXESC_F1DS(config->datafieldSize); -} - -/*! - * brief Configures an MCAN receive buffer. - * - * This function sets start address and datafield size of the recieve buffer. - * - * param base MCAN peripheral base address. - * param config The receive buffer configuration structure. - */ -void MCAN_SetRxBufferConfig(CAN_Type *base, const mcan_rx_buffer_config_t *config) -{ - /* Set Rx Buffer start address. */ - base->RXBC |= CAN_RXBC_RBSA(config->address >> CAN_RXBC_RBSA_SHIFT); - /* Set Rx Buffer data field size */ - base->RXESC |= CAN_RXESC_RBDS(config->datafieldSize); -} - -/*! - * brief Configures an MCAN transmit event fifo. - * - * This function sets start address, element size, watermark of the transmit event fifo. - * - * param base MCAN peripheral base address. - * param config The transmit event fifo configuration structure. - */ -void MCAN_SetTxEventFifoConfig(CAN_Type *base, const mcan_tx_fifo_config_t *config) -{ - /* Set TX Event FIFO start address, element size, watermark. */ - base->TXEFC |= CAN_TXEFC_EFSA(config->address >> CAN_TXEFC_EFSA_SHIFT) | CAN_TXEFC_EFS(config->elementSize) | - CAN_TXEFC_EFWM(config->watermark); -} - -/*! - * brief Configures an MCAN transmit buffer. - * - * This function sets start address, element size, fifo/queue mode and datafield - * size of the transmit buffer. - * - * param base MCAN peripheral base address. - * param config The transmit buffer configuration structure. - */ -void MCAN_SetTxBufferConfig(CAN_Type *base, const mcan_tx_buffer_config_t *config) -{ - assert((config->dedicatedSize + config->fqSize) <= 32U); - - /* Set Tx Buffer start address, size, fifo/queue mode. */ - base->TXBC |= CAN_TXBC_TBSA(config->address >> CAN_TXBC_TBSA_SHIFT) | CAN_TXBC_NDTB(config->dedicatedSize) | - CAN_TXBC_TFQS(config->fqSize) | CAN_TXBC_TFQM(config->mode); - /* Set Tx Buffer data field size */ - base->TXESC |= CAN_TXESC_TBDS(config->datafieldSize); -} - -/*! - * brief Set standard message ID filter element configuration. - * - * param base MCAN peripheral base address. - * param config The MCAN filter configuration. - * param filter The MCAN standard message ID filter element configuration. - * param idx The standard message ID filter element index. - */ -void MCAN_SetSTDFilterElement(CAN_Type *base, - const mcan_frame_filter_config_t *config, - const mcan_std_filter_element_config_t *filter, - uint8_t idx) -{ - uint32_t *elementAddress = NULL; - elementAddress = (uint32_t *)(MCAN_GetMsgRAMBase(base) + config->address + idx * 4U); - (void)memcpy((void *)elementAddress, (const void *)filter, sizeof(mcan_std_filter_element_config_t)); -} - -/*! - * brief Set extended message ID filter element configuration. - * - * param base MCAN peripheral base address. - * param config The MCAN filter configuration. - * param filter The MCAN extended message ID filter element configuration. - * param idx The extended message ID filter element index. - */ -void MCAN_SetEXTFilterElement(CAN_Type *base, - const mcan_frame_filter_config_t *config, - const mcan_ext_filter_element_config_t *filter, - uint8_t idx) -{ - uint32_t *elementAddress = NULL; - elementAddress = (uint32_t *)(MCAN_GetMsgRAMBase(base) + config->address + idx * 8U); - (void)memcpy((void *)elementAddress, (const void *)filter, sizeof(mcan_ext_filter_element_config_t)); -} - -static uint32_t MCAN_GetRxFifo0ElementAddress(CAN_Type *base) -{ - uint32_t eSize; - uint32_t eAddress; - eSize = (base->RXESC & CAN_RXESC_F0DS_MASK) >> CAN_RXESC_F0DS_SHIFT; - if (eSize < 5U) - { - eSize += 4U; - } - else - { - eSize = eSize * 4U - 10U; - } - eAddress = base->RXF0C & CAN_RXF0C_F0SA_MASK; - eAddress += ((base->RXF0S & CAN_RXF0S_F0GI_MASK) >> CAN_RXF0S_F0GI_SHIFT) * eSize * 4U; - return eAddress; -} - -static uint32_t MCAN_GetRxFifo1ElementAddress(CAN_Type *base) -{ - uint32_t eSize; - uint32_t eAddress; - eSize = (base->RXESC & CAN_RXESC_F1DS_MASK) >> CAN_RXESC_F1DS_SHIFT; - if (eSize < 5U) - { - eSize += 4U; - } - else - { - eSize = eSize * 4U - 10U; - } - eAddress = base->RXF1C & CAN_RXF1C_F1SA_MASK; - eAddress += ((base->RXF1S & CAN_RXF1S_F1GI_MASK) >> CAN_RXF1S_F1GI_SHIFT) * eSize * 4U; - return eAddress; -} - -static uint32_t MCAN_GetRxBufferElementAddress(CAN_Type *base, uint8_t idx) -{ - assert(idx <= 63U); - uint32_t eSize; - eSize = (base->RXESC & CAN_RXESC_RBDS_MASK) >> CAN_RXESC_RBDS_SHIFT; - if (eSize < 5U) - { - eSize += 4U; - } - else - { - eSize = eSize * 4U - 10U; - } - return (base->RXBC & CAN_RXBC_RBSA_MASK) + idx * eSize * 4U; -} - -static uint32_t MCAN_GetTxBufferElementAddress(CAN_Type *base, uint8_t idx) -{ - assert(idx <= 31U); - uint32_t eSize; - eSize = (base->TXESC & CAN_TXESC_TBDS_MASK) >> CAN_TXESC_TBDS_SHIFT; - if (eSize < 5U) - { - eSize += 4U; - } - else - { - eSize = eSize * 4U - 10U; - } - return (base->TXBC & CAN_TXBC_TBSA_MASK) + idx * eSize * 4U; -} - -/*! - * brief Gets the Tx buffer request pending status. - * - * This function returns Tx Message Buffer transmission request pending status. - * - * param base MCAN peripheral base address. - * param idx The MCAN Tx Buffer index. - */ -uint32_t MCAN_IsTransmitRequestPending(CAN_Type *base, uint8_t idx) -{ - return (base->TXBRP & ((uint32_t)1U << idx)) >> (uint32_t)idx; -} - -/*! - * brief Gets the Tx buffer transmission occurred status. - * - * This function returns Tx Message Buffer transmission occurred status. - * - * param base MCAN peripheral base address. - * param idx The MCAN Tx Buffer index. - */ -uint32_t MCAN_IsTransmitOccurred(CAN_Type *base, uint8_t idx) -{ - return (base->TXBTO & ((uint32_t)1U << idx)) >> (uint32_t)idx; -} - -/*! - * brief Writes an MCAN Message to the Transmit Buffer. - * - * This function writes a CAN Message to the specified Transmit Message Buffer - * and changes the Message Buffer state to start CAN Message transmit. After - * that the function returns immediately. - * - * param base MCAN peripheral base address. - * param idx The MCAN Tx Buffer index. - * param pTxFrame Pointer to CAN message frame to be sent. - */ -status_t MCAN_WriteTxBuffer(CAN_Type *base, uint8_t idx, const mcan_tx_buffer_frame_t *pTxFrame) -{ - /* Assertion. */ - assert(NULL != pTxFrame); - - status_t status; - uint8_t *elementAddress = NULL; - uint8_t *elementPayloadAddress = NULL; - - if (0U == MCAN_IsTransmitRequestPending(base, idx)) - { - elementAddress = (uint8_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetTxBufferElementAddress(base, idx)); - elementPayloadAddress = (uint8_t *)((uint32_t)elementAddress + 8U); - - /* Write 2 words configuration field. */ - (void)memcpy(elementAddress, (const uint8_t *)pTxFrame, 8U); - /* Write data field. */ - (void)memcpy(elementPayloadAddress, pTxFrame->data, pTxFrame->size); - status = kStatus_Success; - } - else - { - status = kStatus_Fail; - } - - return status; -} - -/*! - * brief Reads an MCAN Message from Rx Buffer. - * - * This function reads a CAN message from the Rx Buffer in the Message RAM. - * - * param base MCAN peripheral base address. - * param idx The MCAN Rx Buffer index. - * param pRxFrame Pointer to CAN message frame structure for reception. - * retval kStatus_Success - Read Message from Rx Buffer successfully. - */ -status_t MCAN_ReadRxBuffer(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *pRxFrame) -{ - /* Assertion. */ - assert(NULL != pRxFrame); - - mcan_rx_buffer_frame_t *elementAddress = NULL; - uint32_t u4PayloadLength = (uint32_t)(pRxFrame->size) + 8U; - - elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxBufferElementAddress(base, idx)); - (void)memcpy((void *)pRxFrame, (void *)elementAddress, u4PayloadLength); - - return kStatus_Success; -} - -/*! - * brief Reads an MCAN Message from Rx FIFO. - * - * This function reads a CAN message from the Rx FIFO in the Message RAM. - * - * param base MCAN peripheral base address. - * param fifoBlock Rx FIFO block 0 or 1. - * param pRxFrame Pointer to CAN message frame structure for reception. - * retval kStatus_Success - Read Message from Rx FIFO successfully. - */ -status_t MCAN_ReadRxFifo(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *pRxFrame) -{ - /* Assertion. */ - assert((0U == fifoBlock) || (1U == fifoBlock)); - assert(NULL != pRxFrame); - - mcan_rx_buffer_frame_t *elementAddress = NULL; - - if (0U == fifoBlock) - { - if ((base->RXF0S & CAN_RXF0S_F0FL_MASK) != 0U) - { - elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxFifo0ElementAddress(base)); - } - else - { - return kStatus_Fail; - } - } - else - { - if ((base->RXF1S & CAN_RXF1S_F1FL_MASK) != 0U) - { - elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxFifo1ElementAddress(base)); - } - else - { - return kStatus_Fail; - } - } - (void)memcpy(pRxFrame, elementAddress, 8U); - pRxFrame->data = (uint8_t *)((uint32_t)elementAddress + 8U); - /* Acknowledge the read. */ - if (0U == fifoBlock) - { - base->RXF0A = (base->RXF0S & CAN_RXF0S_F0GI_MASK) >> CAN_RXF0S_F0GI_SHIFT; - } - else - { - base->RXF1A = (base->RXF1S & CAN_RXF1S_F1GI_MASK) >> CAN_RXF1S_F1GI_SHIFT; - } - return kStatus_Success; -} - -/*! - * brief Performs a polling send transaction on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * param base MCAN peripheral base pointer. - * param idx The MCAN buffer index. - * param pTxFrame Pointer to CAN message frame to be sent. - * retval kStatus_Success - Write Tx Message Buffer Successfully. - * retval kStatus_Fail - Tx Message Buffer is currently in use. - */ -status_t MCAN_TransferSendBlocking(CAN_Type *base, uint8_t idx, mcan_tx_buffer_frame_t *pTxFrame) -{ - status_t status; - - if (kStatus_Success == MCAN_WriteTxBuffer(base, idx, pTxFrame)) - { - MCAN_TransmitAddRequest(base, idx); - - /* Wait until message sent out. */ - while (0U == MCAN_IsTransmitOccurred(base, idx)) - { - } - status = kStatus_Success; - } - else - { - status = kStatus_Fail; - } - - return status; -} - -/*! - * brief Performs a polling receive transaction on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * param base MCAN peripheral base pointer. - * param idx The MCAN buffer index. - * param pRxFrame Pointer to CAN message frame structure for reception. - * retval kStatus_Success - Read Rx Message Buffer Successfully. - * retval kStatus_Fail - No new message. - */ -status_t MCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *pRxFrame) -{ - assert(idx <= 63U); - - status_t status = kStatus_Success; - -#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) - uint32_t u4Retry = MCAN_RETRY_TIMES; -#endif - - while (!MCAN_GetRxBufferStatusFlag(base, idx)) - { -#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) - if (0U == u4Retry--) - { - status = kStatus_Fail; - } -#endif - } -#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) - if (kStatus_Success == status) -#endif - { - MCAN_ClearRxBufferStatusFlag(base, idx); - status = MCAN_ReadRxBuffer(base, idx, pRxFrame); - } - - return status; -} - -/*! - * brief Performs a polling receive transaction from Rx FIFO on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * param base MCAN peripheral base pointer. - * param fifoBlock Rx FIFO block, 0 or 1. - * param pRxFrame Pointer to CAN message frame structure for reception. - * retval kStatus_Success - Read Message from Rx FIFO successfully. - * retval kStatus_Fail - No new message in Rx FIFO. - */ -status_t MCAN_TransferReceiveFifoBlocking(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *pRxFrame) -{ - assert((0U == fifoBlock) || (1U == fifoBlock)); - - status_t status = kStatus_Success; - uint32_t maskCanIR; -#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) - uint32_t u4Retry = MCAN_RETRY_TIMES; -#endif - - maskCanIR = (0U == fifoBlock) ? CAN_IR_RF0N_MASK : CAN_IR_RF1N_MASK; - - while (0U == MCAN_GetStatusFlag(base, maskCanIR)) - { -#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) - if (0U == u4Retry--) - { - status = kStatus_Fail; - } -#endif - } - -#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) - if (kStatus_Success == status) -#endif - { - MCAN_ClearStatusFlag(base, maskCanIR); - status = MCAN_ReadRxFifo(base, fifoBlock, pRxFrame); - } - - return status; -} - -/*! - * brief Initializes the MCAN handle. - * - * This function initializes the MCAN handle, which can be used for other MCAN - * transactional APIs. Usually, for a specified MCAN instance, - * call this API once to get the initialized handle. - * - * param base MCAN peripheral base address. - * param handle MCAN handle pointer. - * param callback The callback function. - * param userData The parameter of the callback function. - */ -void MCAN_TransferCreateHandle(CAN_Type *base, mcan_handle_t *handle, mcan_transfer_callback_t callback, void *userData) -{ - assert(NULL != handle); - - uint8_t instance; - - /* Clean MCAN transfer handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Get instance from peripheral base address. */ - instance = (uint8_t)MCAN_GetInstance(base); - - /* Save the context in global variables to support the double weak mechanism. */ - s_mcanHandle[instance] = handle; - - /* Register Callback function. */ - handle->callback = callback; - handle->userData = userData; - - s_mcanIsr = MCAN_TransferHandleIRQ; - - /* We Enable Error & Status interrupt here, because this interrupt just - * report current status of MCAN module through Callback function. - * It is insignificance without a available callback function. - */ - if (handle->callback != NULL) - { - MCAN_EnableInterrupts(base, 0U, - (uint32_t)kMCAN_BusOffInterruptEnable | (uint32_t)kMCAN_ErrorInterruptEnable | - (uint32_t)kMCAN_WarningInterruptEnable); - } - else - { - MCAN_DisableInterrupts(base, (uint32_t)kMCAN_BusOffInterruptEnable | (uint32_t)kMCAN_ErrorInterruptEnable | - (uint32_t)kMCAN_WarningInterruptEnable); - } - - /* Enable interrupts in NVIC. */ - (void)EnableIRQ((IRQn_Type)(s_mcanIRQ[instance][0])); - (void)EnableIRQ((IRQn_Type)(s_mcanIRQ[instance][1])); -} - -/*! - * brief Sends a message using IRQ. - * - * This function sends a message using IRQ. This is a non-blocking function, which returns - * right away. When messages have been sent out, the send callback function is called. - * - * param base MCAN peripheral base address. - * param handle MCAN handle pointer. - * param xfer MCAN Buffer transfer structure. See the #mcan_buffer_transfer_t. - * retval kStatus_Success Start Tx Buffer sending process successfully. - * retval kStatus_Fail Write Tx Buffer failed. - * retval kStatus_MCAN_TxBusy Tx Buffer is in use. - */ -status_t MCAN_TransferSendNonBlocking(CAN_Type *base, mcan_handle_t *handle, mcan_buffer_transfer_t *xfer) -{ - /* Assertion. */ - assert(NULL != handle); - assert(NULL != xfer); - assert(xfer->bufferIdx <= 63U); - - status_t status; - - /* Check if Tx Buffer is idle. */ - if ((uint8_t)kMCAN_StateIdle == handle->bufferState[xfer->bufferIdx]) - { - /* Distinguish transmit type. */ - if ((uint8_t)kMCAN_FrameTypeRemote == xfer->frame->xtd) - { - handle->bufferState[xfer->bufferIdx] = (uint8_t)kMCAN_StateTxRemote; - - /* Register user Frame buffer to receive remote Frame. */ - handle->bufferFrameBuf[xfer->bufferIdx] = xfer->frame; - } - else - { - handle->bufferState[xfer->bufferIdx] = (uint8_t)kMCAN_StateTxData; - } - - if (kStatus_Success == MCAN_WriteTxBuffer(base, xfer->bufferIdx, xfer->frame)) - { - /* Enable Buffer Interrupt. */ - MCAN_EnableTransmitBufferInterrupts(base, xfer->bufferIdx); - MCAN_EnableInterrupts(base, 0U, CAN_IE_TCE_MASK); - - MCAN_TransmitAddRequest(base, xfer->bufferIdx); - - status = kStatus_Success; - } - else - { - handle->bufferState[xfer->bufferIdx] = (uint8_t)kMCAN_StateIdle; - status = kStatus_Fail; - } - } - else - { - status = kStatus_MCAN_TxBusy; - } - - return status; -} - -/*! - * brief Receives a message from Rx FIFO using IRQ. - * - * This function receives a message using IRQ. This is a non-blocking function, which returns - * right away. When all messages have been received, the receive callback function is called. - * - * param base MCAN peripheral base address. - * param handle MCAN handle pointer. - * param fifoBlock Rx FIFO block, 0 or 1. - * param xfer MCAN Rx FIFO transfer structure. See the ref mcan_fifo_transfer_t. - * retval kStatus_Success - Start Rx FIFO receiving process successfully. - * retval kStatus_MCAN_RxFifo0Busy - Rx FIFO 0 is currently in use. - * retval kStatus_MCAN_RxFifo1Busy - Rx FIFO 1 is currently in use. - */ -status_t MCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, - uint8_t fifoBlock, - mcan_handle_t *handle, - mcan_fifo_transfer_t *xfer) -{ - /* Assertion. */ - assert((0U == fifoBlock) || (1U == fifoBlock)); - assert(NULL != handle); - assert(NULL != xfer); - - status_t status; - - /* Check if Message Buffer is idle. */ - if ((uint8_t)kMCAN_StateIdle == handle->rxFifoState) - { - handle->rxFifoState = (uint8_t)kMCAN_StateRxFifo; - - /* Register Message Buffer. */ - handle->rxFifoFrameBuf = xfer->frame; - - /* Enable FIFO Interrupt. */ - if (1U == fifoBlock) - { - MCAN_EnableInterrupts(base, 0U, CAN_IE_RF1NE_MASK); - } - else - { - MCAN_EnableInterrupts(base, 0U, CAN_IE_RF0NE_MASK); - } - status = kStatus_Success; - } - else - { - status = (1U == fifoBlock) ? kStatus_MCAN_RxFifo1Busy : kStatus_MCAN_RxFifo0Busy; - } - - return status; -} - -/*! - * brief Aborts the interrupt driven message send process. - * - * This function aborts the interrupt driven message send process. - * - * param base MCAN peripheral base address. - * param handle MCAN handle pointer. - * param bufferIdx The MCAN Buffer index. - */ -void MCAN_TransferAbortSend(CAN_Type *base, mcan_handle_t *handle, uint8_t bufferIdx) -{ - /* Assertion. */ - assert(NULL != handle); - assert(bufferIdx <= 63U); - - /* Disable Message Buffer Interrupt. */ - MCAN_DisableTransmitBufferInterrupts(base, bufferIdx); - - /* Cancel send request. */ - MCAN_TransmitCancelRequest(base, bufferIdx); - - /* Un-register handle. */ - handle->bufferFrameBuf[bufferIdx] = NULL; - - handle->bufferState[bufferIdx] = (uint8_t)kMCAN_StateIdle; -} - -/*! - * brief Aborts the interrupt driven message receive from Rx FIFO process. - * - * This function aborts the interrupt driven message receive from Rx FIFO process. - * - * param base MCAN peripheral base address. - * param fifoBlock MCAN Fifo block, 0 or 1. - * param handle MCAN handle pointer. - */ -void MCAN_TransferAbortReceiveFifo(CAN_Type *base, uint8_t fifoBlock, mcan_handle_t *handle) -{ - /* Assertion. */ - assert(NULL != handle); - assert((0U == fifoBlock) || (1U == fifoBlock)); - - /* Check if Rx FIFO is enabled. */ - if (1U == fifoBlock) - { - /* Disable Rx Message FIFO Interrupts. */ - MCAN_DisableInterrupts(base, CAN_IE_RF1NE_MASK); - } - else - { - MCAN_DisableInterrupts(base, CAN_IE_RF0NE_MASK); - } - /* Un-register handle. */ - handle->rxFifoFrameBuf = NULL; - - handle->rxFifoState = (uint8_t)kMCAN_StateIdle; -} - -/*! - * brief MCAN IRQ handle function. - * - * This function handles the MCAN Error, the Buffer, and the Rx FIFO IRQ request. - * - * param base MCAN peripheral base address. - * param handle MCAN handle pointer. - */ -void MCAN_TransferHandleIRQ(CAN_Type *base, mcan_handle_t *handle) -{ - /* Assertion. */ - assert(NULL != handle); - - status_t status = kStatus_MCAN_UnHandled; - uint32_t valueIR; - uint32_t result; - - /* Store Current MCAN Module Error and Status. */ - valueIR = base->IR; - - do - { - if (0U != (valueIR & ((uint32_t)kMCAN_ErrorWarningIntFlag | (uint32_t)kMCAN_ErrorPassiveIntFlag | - (uint32_t)kMCAN_BusOffIntFlag))) - { - /* Solve error. */ - result = (valueIR & ((uint32_t)kMCAN_ErrorWarningIntFlag | (uint32_t)kMCAN_ErrorPassiveIntFlag | - (uint32_t)kMCAN_BusOffIntFlag)); - status = kStatus_MCAN_ErrorStatus; - } - else if (0U != (valueIR & (uint32_t)kMCAN_TxTransmitCompleteFlag)) - { - /* Solve Tx interrupt. */ - uint8_t idx = 0U; - for (; idx < (uint8_t)((base->TXBC & CAN_TXBC_NDTB_MASK) >> CAN_TXBC_NDTB_SHIFT); idx++) - { - /* Get the lowest unhandled Tx Message Buffer */ - if (0U != MCAN_IsTransmitOccurred(base, idx)) - { - if ((base->TXBTIE & ((uint32_t)1U << idx)) != 0U) - { - MCAN_TransferAbortSend(base, handle, idx); - } - } - } - result = (uint32_t)kMCAN_TxTransmitCompleteFlag; - status = kStatus_MCAN_TxIdle; - } - else if (0U != (valueIR & (uint32_t)kMCAN_RxFifo0NewFlag)) - { - (void)MCAN_ReadRxFifo(base, 0U, handle->rxFifoFrameBuf); - result = (uint32_t)kMCAN_RxFifo0NewFlag; - status = kStatus_MCAN_RxFifo0Idle; - MCAN_TransferAbortReceiveFifo(base, 0U, handle); - } - else if (0U != (valueIR & (uint32_t)kMCAN_RxFifo0LostFlag)) - { - result = (uint32_t)kMCAN_RxFifo0LostFlag; - status = kStatus_MCAN_RxFifo0Lost; - } - else if (0U != (valueIR & (uint32_t)kMCAN_RxFifo1NewFlag)) - { - (void)MCAN_ReadRxFifo(base, 1U, handle->rxFifoFrameBuf); - result = (uint32_t)kMCAN_RxFifo1NewFlag; - status = kStatus_MCAN_RxFifo1Idle; - MCAN_TransferAbortReceiveFifo(base, 1U, handle); - } - else if (0U != (valueIR & (uint32_t)kMCAN_RxFifo1LostFlag)) - { - result = (uint32_t)kMCAN_RxFifo1LostFlag; - status = kStatus_MCAN_RxFifo0Lost; - } - else - { - /* Handle the interrupt flag unsupported in current version of MCAN driver. - * User can get these unsupported interrupt flags by callback function, - * we can clear directly in the handler to prevent endless loop. - */ - result = valueIR; - result &= ~((uint32_t)kMCAN_ErrorWarningIntFlag | (uint32_t)kMCAN_ErrorPassiveIntFlag | - (uint32_t)kMCAN_BusOffIntFlag | (uint32_t)kMCAN_TxTransmitCompleteFlag | - (uint32_t)kMCAN_RxFifo0NewFlag | (uint32_t)kMCAN_RxFifo0LostFlag | - (uint32_t)kMCAN_RxFifo1NewFlag | (uint32_t)kMCAN_RxFifo1LostFlag); - } - - /* Clear Error interrupt, resolved Rx FIFO, Tx Buffer IRQ and other unsupported interrupt flags. */ - MCAN_ClearStatusFlag(base, result); - - /* Calling Callback Function if has one. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, status, result, handle->userData); - } - - /* Reset return status */ - status = kStatus_MCAN_UnHandled; - - /* Store Current MCAN Module Error and Status. */ - valueIR = base->IR; - } while (0U != valueIR); -} - -#if defined(CAN0) -void CAN0_IRQ0_DriverIRQHandler(void); -void CAN0_IRQ0_DriverIRQHandler(void) -{ - assert(NULL != s_mcanHandle[0]); - - s_mcanIsr(CAN0, s_mcanHandle[0]); - SDK_ISR_EXIT_BARRIER; -} - -void CAN0_IRQ1_DriverIRQHandler(void); -void CAN0_IRQ1_DriverIRQHandler(void) -{ - assert(NULL != s_mcanHandle[0]); - - s_mcanIsr(CAN0, s_mcanHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CAN1) -void CAN1_IRQ0_DriverIRQHandler(void); -void CAN1_IRQ0_DriverIRQHandler(void) -{ - assert(NULL != s_mcanHandle[1]); - - s_mcanIsr(CAN1, s_mcanHandle[1]); - SDK_ISR_EXIT_BARRIER; -} - -void CAN1_IRQ1_DriverIRQHandler(void); -void CAN1_IRQ1_DriverIRQHandler(void) -{ - assert(NULL != s_mcanHandle[1]); - - s_mcanIsr(CAN1, s_mcanHandle[1]); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mcan.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mcan.h deleted file mode 100644 index 7b0ee3e1c36..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mcan.h +++ /dev/null @@ -1,1056 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_MCAN_H_ -#define _FSL_MCAN_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup mcan - * @{ - */ - -/****************************************************************************** - * Definitions - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief MCAN driver version. */ -#define FSL_MCAN_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) -/*@}*/ - -#ifndef MCAN_RETRY_TIMES -/* Define to 0 by default means to retry infinitely until the flag is assert/de-assert. - * User can change the macro with their requirement by defined the MACRO. - */ -#define MCAN_RETRY_TIMES (0U) -#endif - -/*! @brief MCAN transfer status. */ -enum -{ - kStatus_MCAN_TxBusy = MAKE_STATUS(kStatusGroup_MCAN, 0), /*!< Tx Buffer is Busy. */ - kStatus_MCAN_TxIdle = MAKE_STATUS(kStatusGroup_MCAN, 1), /*!< Tx Buffer is Idle. */ - kStatus_MCAN_RxBusy = MAKE_STATUS(kStatusGroup_MCAN, 2), /*!< Rx Buffer is Busy. */ - kStatus_MCAN_RxIdle = MAKE_STATUS(kStatusGroup_MCAN, 3), /*!< Rx Buffer is Idle. */ - kStatus_MCAN_RxFifo0New = MAKE_STATUS(kStatusGroup_MCAN, 4), /*!< New message written to Rx FIFO 0. */ - kStatus_MCAN_RxFifo0Idle = MAKE_STATUS(kStatusGroup_MCAN, 5), /*!< Rx FIFO 0 is Idle. */ - kStatus_MCAN_RxFifo0Watermark = MAKE_STATUS(kStatusGroup_MCAN, 6), /*!< Rx FIFO 0 fill level reached watermark. */ - kStatus_MCAN_RxFifo0Full = MAKE_STATUS(kStatusGroup_MCAN, 7), /*!< Rx FIFO 0 full. */ - kStatus_MCAN_RxFifo0Lost = MAKE_STATUS(kStatusGroup_MCAN, 8), /*!< Rx FIFO 0 message lost. */ - kStatus_MCAN_RxFifo1New = MAKE_STATUS(kStatusGroup_MCAN, 9), /*!< New message written to Rx FIFO 1. */ - kStatus_MCAN_RxFifo1Idle = MAKE_STATUS(kStatusGroup_MCAN, 10), /*!< Rx FIFO 1 is Idle. */ - kStatus_MCAN_RxFifo1Watermark = MAKE_STATUS(kStatusGroup_MCAN, 11), /*!< Rx FIFO 1 fill level reached watermark. */ - kStatus_MCAN_RxFifo1Full = MAKE_STATUS(kStatusGroup_MCAN, 12), /*!< Rx FIFO 1 full. */ - kStatus_MCAN_RxFifo1Lost = MAKE_STATUS(kStatusGroup_MCAN, 13), /*!< Rx FIFO 1 message lost. */ - kStatus_MCAN_RxFifo0Busy = MAKE_STATUS(kStatusGroup_MCAN, 14), /*!< Rx FIFO 0 is busy. */ - kStatus_MCAN_RxFifo1Busy = MAKE_STATUS(kStatusGroup_MCAN, 15), /*!< Rx FIFO 1 is busy. */ - kStatus_MCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_MCAN, 16), /*!< MCAN Module Error and Status. */ - kStatus_MCAN_UnHandled = MAKE_STATUS(kStatusGroup_MCAN, 17), /*!< UnHadled Interrupt asserted. */ -}; - -/*! - * @brief MCAN status flags. - * - * This provides constants for the MCAN status flags for use in the MCAN functions. - * Note: The CPU read action clears MCAN_ErrorFlag, therefore user need to - * read MCAN_ErrorFlag and distinguish which error is occur using - * _mcan_error_flags enumerations. - */ -enum _mcan_flags -{ - kMCAN_AccesstoRsvdFlag = CAN_IR_ARA_MASK, /*!< CAN Synchronization Status. */ - kMCAN_ProtocolErrDIntFlag = CAN_IR_PED_MASK, /*!< Tx Warning Interrupt Flag. */ - kMCAN_ProtocolErrAIntFlag = CAN_IR_PEA_MASK, /*!< Rx Warning Interrupt Flag. */ - kMCAN_BusOffIntFlag = CAN_IR_BO_MASK, /*!< Tx Error Warning Status. */ - kMCAN_ErrorWarningIntFlag = CAN_IR_EW_MASK, /*!< Rx Error Warning Status. */ - kMCAN_ErrorPassiveIntFlag = CAN_IR_EP_MASK, /*!< Rx Error Warning Status. */ -}; - -/*! - * @brief MCAN Rx FIFO status flags. - * - * The MCAN Rx FIFO Status enumerations are used to determine the status of the - * Rx FIFO. - */ -enum _mcan_rx_fifo_flags -{ - kMCAN_RxFifo0NewFlag = CAN_IR_RF0N_MASK, /*!< Rx FIFO 0 new message flag. */ - kMCAN_RxFifo0WatermarkFlag = CAN_IR_RF0W_MASK, /*!< Rx FIFO 0 watermark reached flag. */ - kMCAN_RxFifo0FullFlag = CAN_IR_RF0F_MASK, /*!< Rx FIFO 0 full flag. */ - kMCAN_RxFifo0LostFlag = CAN_IR_RF0L_MASK, /*!< Rx FIFO 0 message lost flag. */ - kMCAN_RxFifo1NewFlag = CAN_IR_RF1N_MASK, /*!< Rx FIFO 0 new message flag. */ - kMCAN_RxFifo1WatermarkFlag = CAN_IR_RF1W_MASK, /*!< Rx FIFO 0 watermark reached flag. */ - kMCAN_RxFifo1FullFlag = CAN_IR_RF1F_MASK, /*!< Rx FIFO 0 full flag. */ - kMCAN_RxFifo1LostFlag = CAN_IR_RF1L_MASK, /*!< Rx FIFO 0 message lost flag. */ -}; - -/*! - * @brief MCAN Tx status flags. - * - * The MCAN Tx Status enumerations are used to determine the status of the - * Tx Buffer/Event FIFO. - */ -enum _mcan_tx_flags -{ - kMCAN_TxTransmitCompleteFlag = CAN_IR_TC_MASK, /*!< Transmission completed flag. */ - kMCAN_TxTransmitCancelFinishFlag = CAN_IR_TCF_MASK, /*!< Transmission cancellation finished flag. */ - kMCAN_TxEventFifoLostFlag = CAN_IR_TEFL_MASK, /*!< Tx Event FIFO element lost. */ - kMCAN_TxEventFifoFullFlag = CAN_IR_TEFF_MASK, /*!< Tx Event FIFO full. */ - kMCAN_TxEventFifoWatermarkFlag = CAN_IR_TEFW_MASK, /*!< Tx Event FIFO fill level reached watermark. */ - kMCAN_TxEventFifoNewFlag = CAN_IR_TEFN_MASK, /*!< Tx Handler wrote Tx Event FIFO element flag. */ - kMCAN_TxEventFifoEmptyFlag = CAN_IR_TFE_MASK, /*!< Tx FIFO empty flag. */ -}; - -/*! - * @brief MCAN interrupt configuration structure, default settings all disabled. - * - * This structure contains the settings for all of the MCAN Module interrupt configurations. - */ -enum _mcan_interrupt_enable -{ - kMCAN_BusOffInterruptEnable = CAN_IE_BOE_MASK, /*!< Bus Off interrupt. */ - kMCAN_ErrorInterruptEnable = CAN_IE_EPE_MASK, /*!< Error interrupt. */ - kMCAN_WarningInterruptEnable = CAN_IE_EWE_MASK, /*!< Rx Warning interrupt. */ -}; - -/*! @brief MCAN frame format. */ -typedef enum _mcan_frame_idformat -{ - kMCAN_FrameIDStandard = 0x0U, /*!< Standard frame format attribute. */ - kMCAN_FrameIDExtend = 0x1U, /*!< Extend frame format attribute. */ -} mcan_frame_idformat_t; - -/*! @brief MCAN frame type. */ -typedef enum _mcan_frame_type -{ - kMCAN_FrameTypeData = 0x0U, /*!< Data frame type attribute. */ - kMCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */ -} mcan_frame_type_t; - -/*! @brief MCAN frame datafield size. */ -typedef enum _mcan_bytes_in_datafield -{ - kMCAN_8ByteDatafield = 0x0U, /*!< 8 byte data field. */ - kMCAN_12ByteDatafield = 0x1U, /*!< 12 byte data field. */ - kMCAN_16ByteDatafield = 0x2U, /*!< 16 byte data field. */ - kMCAN_20ByteDatafield = 0x3U, /*!< 20 byte data field. */ - kMCAN_24ByteDatafield = 0x4U, /*!< 24 byte data field. */ - kMCAN_32ByteDatafield = 0x5U, /*!< 32 byte data field. */ - kMCAN_48ByteDatafield = 0x6U, /*!< 48 byte data field. */ - kMCAN_64ByteDatafield = 0x7U, /*!< 64 byte data field. */ -} mcan_bytes_in_datafield_t; - -#if defined(__CC_ARM) -#pragma anon_unions -#endif -/*! @brief MCAN Tx Buffer structure. */ -typedef struct _mcan_tx_buffer_frame -{ - struct - { - uint32_t id : 29; /*!< CAN Frame Identifier. */ - uint32_t rtr : 1; /*!< CAN Frame Type(DATA or REMOTE). */ - uint32_t xtd : 1; /*!< CAN Frame Type(STD or EXT). */ - uint32_t esi : 1; /*!< CAN Frame Error State Indicator. */ - }; - struct - { - uint32_t : 16; - uint32_t dlc : 4; /*!< Data Length Code 9 10 11 12 13 14 15 - Number of data bytes 12 16 20 24 32 48 64 */ - uint32_t brs : 1; /*!< Bit Rate Switch. */ - uint32_t fdf : 1; /*!< CAN FD format. */ - uint32_t : 1; /*!< Reserved. */ - uint32_t efc : 1; /*!< Event FIFO control. */ - uint32_t mm : 8; /*!< Message Marker. */ - }; - uint8_t *data; - uint8_t size; /*!< classical CAN is 8(bytes), FD is 12/64 such. */ -} mcan_tx_buffer_frame_t; - -/*! @brief MCAN Rx FIFO/Buffer structure. */ -typedef struct _mcan_rx_buffer_frame -{ - struct - { - uint32_t id : 29; /*!< CAN Frame Identifier. */ - uint32_t rtr : 1; /*!< CAN Frame Type(DATA or REMOTE). */ - uint32_t xtd : 1; /*!< CAN Frame Type(STD or EXT). */ - uint32_t esi : 1; /*!< CAN Frame Error State Indicator. */ - }; - struct - { - uint32_t rxts : 16; /*!< Rx Timestamp. */ - uint32_t dlc : 4; /*!< Data Length Code 9 10 11 12 13 14 15 - Number of data bytes 12 16 20 24 32 48 64 */ - uint32_t brs : 1; /*!< Bit Rate Switch. */ - uint32_t fdf : 1; /*!< CAN FD format. */ - uint32_t : 2; /*!< Reserved. */ - uint32_t fidx : 7; /*!< Filter Index. */ - uint32_t anmf : 1; /*!< Accepted Non-matching Frame. */ - }; - uint8_t *data; - uint8_t size; /*!< classical CAN is 8(bytes), FD is 12/64 such. */ -} mcan_rx_buffer_frame_t; - -/*! @brief MCAN Rx FIFO block number. */ -typedef enum _mcan_fifo_type -{ - kMCAN_Fifo0 = 0x0U, /*!< CAN Rx FIFO 0. */ - kMCAN_Fifo1 = 0x1U, /*!< CAN Rx FIFO 1. */ -} mcan_fifo_type_t; - -/*! @brief MCAN FIFO Operation Mode. */ -typedef enum _mcan_fifo_opmode_config -{ - kMCAN_FifoBlocking = 0x0U, /*!< FIFO blocking mode. */ - kMCAN_FifoOverwrite = 0x1U, /*!< FIFO overwrite mode. */ -} mcan_fifo_opmode_config_t; - -/*! @brief MCAN Tx FIFO/Queue Mode. */ -typedef enum _mcan_txmode_config -{ - kMCAN_txFifo = 0x0U, /*!< Tx FIFO operation. */ - kMCAN_txQueue = 0x1U, /*!< Tx Queue operation. */ -} mcan_txmode_config_t; - -/*! @brief MCAN remote frames treatment. */ -typedef enum _mcan_remote_frame_config -{ - kMCAN_filterFrame = 0x0U, /*!< Filter remote frames. */ - kMCAN_rejectFrame = 0x1U, /*!< Reject all remote frames. */ -} mcan_remote_frame_config_t; - -/*! @brief MCAN non-masking frames treatment. */ -typedef enum _mcan_nonmasking_frame_config -{ - kMCAN_acceptinFifo0 = 0x0U, /*!< Accept non-masking frames in Rx FIFO 0. */ - kMCAN_acceptinFifo1 = 0x1U, /*!< Accept non-masking frames in Rx FIFO 1. */ - kMCAN_reject0 = 0x2U, /*!< Reject non-masking frames. */ - kMCAN_reject1 = 0x3U, /*!< Reject non-masking frames. */ -} mcan_nonmasking_frame_config_t; - -/*! @brief MCAN Filter Element Configuration. */ -typedef enum _mcan_fec_config -{ - kMCAN_disable = 0x0U, /*!< Disable filter element. */ - kMCAN_storeinFifo0 = 0x1U, /*!< Store in Rx FIFO 0 if filter matches. */ - kMCAN_storeinFifo1 = 0x2U, /*!< Store in Rx FIFO 1 if filter matches. */ - kMCAN_reject = 0x3U, /*!< Reject ID if filter matches. */ - kMCAN_setprio = 0x4U, /*!< Set priority if filter matches. */ - kMCAN_setpriofifo0 = 0x5U, /*!< Set priority and store in FIFO 0 if filter matches. */ - kMCAN_setpriofifo1 = 0x6U, /*!< Set priority and store in FIFO 1 if filter matches. */ - kMCAN_storeinbuffer = 0x7U, /*!< Store into Rx Buffer or as debug message. */ -} mcan_fec_config_t; - -/*! @brief MCAN Rx FIFO configuration. */ -typedef struct _mcan_rx_fifo_config -{ - uint32_t address; /*!< FIFOn start address. */ - uint32_t elementSize; /*!< FIFOn element number. */ - uint32_t watermark; /*!< FIFOn watermark level. */ - mcan_fifo_opmode_config_t opmode; /*!< FIFOn blocking/overwrite mode. */ - mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */ -} mcan_rx_fifo_config_t; - -/*! @brief MCAN Rx Buffer configuration. */ -typedef struct _mcan_rx_buffer_config -{ - uint32_t address; /*!< Rx Buffer start address. */ - mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */ -} mcan_rx_buffer_config_t; - -/*! @brief MCAN Tx Event FIFO configuration. */ -typedef struct _mcan_tx_fifo_config -{ - uint32_t address; /*!< Event fifo start address. */ - uint32_t elementSize; /*!< FIFOn element number. */ - uint32_t watermark; /*!< FIFOn watermark level. */ -} mcan_tx_fifo_config_t; - -/*! @brief MCAN Tx Buffer configuration. */ -typedef struct _mcan_tx_buffer_config -{ - uint32_t address; /*!< Tx Buffers Start Address. */ - uint32_t dedicatedSize; /*!< Number of Dedicated Transmit Buffers. */ - uint32_t fqSize; /*!< Transmit FIFO/Queue Size. */ - mcan_txmode_config_t mode; /*!< Tx FIFO/Queue Mode.*/ - mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */ -} mcan_tx_buffer_config_t; - -/*! @brief MCAN Filter Type. */ -typedef enum _mcan_std_filter_type -{ - kMCAN_range = 0x0U, /*!< Range filter from SFID1 to SFID2. */ - kMCAN_dual = 0x1U, /*!< Dual ID filter for SFID1 or SFID2. */ - kMCAN_classic = 0x2U, /*!< Classic filter: SFID1 = filter, SFID2 = mask. */ - kMCAN_disableORrange2 = 0x3U, /*!< Filter element disabled for standard filter - or Range filter, XIDAM mask not applied for extended filter. */ -} mcan_filter_type_t; - -/*! @brief MCAN Standard Message ID Filter Element. */ -typedef struct _mcan_std_filter_element_config -{ - uint32_t sfid2 : 11; /*!< Standard Filter ID 2. */ - uint32_t : 5; /*!< Reserved. */ - uint32_t sfid1 : 11; /*!< Standard Filter ID 1. */ - uint32_t sfec : 3; /*!< Standard Filter Element Configuration. */ - uint32_t sft : 2; /*!< Standard Filter Type. */ -} mcan_std_filter_element_config_t; - -/*! @brief MCAN Extended Message ID Filter Element. */ -typedef struct _mcan_ext_filter_element_config -{ - uint32_t efid1 : 29; /*!< Extended Filter ID 1. */ - uint32_t efec : 3; /*!< Extended Filter Element Configuration. */ - uint32_t efid2 : 29; /*!< Extended Filter ID 2. */ - uint32_t : 1; /*!< Reserved. */ - uint32_t eft : 2; /*!< Extended Filter Type. */ -} mcan_ext_filter_element_config_t; - -/*! @brief MCAN Rx filter configuration. */ -typedef struct _mcan_frame_filter_config -{ - uint32_t address; /*!< Filter start address. */ - uint32_t listSize; /*!< Filter list size. */ - mcan_frame_idformat_t idFormat; /*!< Frame format. */ - mcan_remote_frame_config_t remFrame; /*!< Remote frame treatment. */ - mcan_nonmasking_frame_config_t nmFrame; /*!< Non-masking frame treatment. */ -} mcan_frame_filter_config_t; - -/*! @brief MCAN protocol timing characteristic configuration structure. */ -typedef struct _mcan_timing_config -{ - uint16_t preDivider; /*!< Nominal Clock Pre-scaler Division Factor. */ - uint8_t rJumpwidth; /*!< Nominal Re-sync Jump Width. */ - uint8_t seg1; /*!< Nominal Time Segment 1. */ - uint8_t seg2; /*!< Nominal Time Segment 2. */ -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) - uint16_t datapreDivider; /*!< Data Clock Pre-scaler Division Factor. */ - uint8_t datarJumpwidth; /*!< Data Re-sync Jump Width. */ - uint8_t dataseg1; /*!< Data Time Segment 1. */ - uint8_t dataseg2; /*!< Data Time Segment 2. */ -#endif -} mcan_timing_config_t; - -/*! @brief MCAN module configuration structure. */ -typedef struct _mcan_config -{ - uint32_t baudRateA; /*!< Baud rate of Arbitration phase in bps. */ - uint32_t baudRateD; /*!< Baud rate of Data phase in bps. */ - bool enableCanfdNormal; /*!< Enable or Disable CANFD normal. */ - bool enableCanfdSwitch; /*!< Enable or Disable CANFD with baudrate switch. */ - bool enableLoopBackInt; /*!< Enable or Disable Internal Back. */ - bool enableLoopBackExt; /*!< Enable or Disable External Loop Back. */ - bool enableBusMon; /*!< Enable or Disable Bus Monitoring Mode. */ - mcan_timing_config_t timingConfig; /*!< Protocol timing . */ -} mcan_config_t; - -/*! @brief MCAN Buffer transfer. */ -typedef struct _mcan_buffer_transfer -{ - mcan_tx_buffer_frame_t *frame; /*!< The buffer of CAN Message to be transfer. */ - uint8_t bufferIdx; /*!< The index of Message buffer used to transfer Message. */ -} mcan_buffer_transfer_t; - -/*! @brief MCAN Rx FIFO transfer. */ -typedef struct _mcan_fifo_transfer -{ - mcan_rx_buffer_frame_t *frame; /*!< The buffer of CAN Message to be received from Rx FIFO. */ -} mcan_fifo_transfer_t; - -/*! @brief MCAN handle structure definition. */ -typedef struct _mcan_handle mcan_handle_t; - -/*! @brief MCAN transfer callback function. - * - * The MCAN transfer callback returns a value from the underlying layer. - * If the status equals to kStatus_MCAN_ErrorStatus, the result parameter is the Content of - * MCAN status register which can be used to get the working status(or error status) of MCAN module. - * If the status equals to other MCAN Message Buffer transfer status, the result is the index of - * Message Buffer that generate transfer event. - * If the status equals to other MCAN Message Buffer transfer status, the result is meaningless and should be - * Ignored. - */ -typedef void (*mcan_transfer_callback_t)( - CAN_Type *base, mcan_handle_t *handle, status_t status, uint32_t result, void *userData); - -/*! @brief MCAN handle structure. */ -struct _mcan_handle -{ - mcan_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< MCAN callback function parameter.*/ - mcan_tx_buffer_frame_t *volatile bufferFrameBuf[64]; /*!< The buffer for received data from Buffers. */ - mcan_rx_buffer_frame_t *volatile rxFifoFrameBuf; /*!< The buffer for received data from Rx FIFO. */ - volatile uint8_t bufferState[64]; /*!< Message Buffer transfer state. */ - volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */ -}; - -/****************************************************************************** - * API - *****************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes an MCAN instance. - * - * This function initializes the MCAN module with user-defined settings. - * This example shows how to set up the mcan_config_t parameters and how - * to call the MCAN_Init function by passing in these parameters. - * @code - * mcan_config_t config; - * config->baudRateA = 500000U; - * config->baudRateD = 1000000U; - * config->enableCanfdNormal = false; - * config->enableCanfdSwitch = false; - * config->enableLoopBackInt = false; - * config->enableLoopBackExt = false; - * config->enableBusMon = false; - * MCAN_Init(CANFD0, &config, 8000000UL); - * @endcode - * - * @param base MCAN peripheral base address. - * @param config Pointer to the user-defined configuration structure. - * @param sourceClock_Hz MCAN Protocol Engine clock source frequency in Hz. - */ -void MCAN_Init(CAN_Type *base, const mcan_config_t *config, uint32_t sourceClock_Hz); - -/*! - * @brief Deinitializes an MCAN instance. - * - * This function deinitializes the MCAN module. - * - * @param base MCAN peripheral base address. - */ -void MCAN_Deinit(CAN_Type *base); - -/*! - * @brief Gets the default configuration structure. - * - * This function initializes the MCAN configuration structure to default values. The default - * values are as follows. - * config->baudRateA = 500000U; - * config->baudRateD = 1000000U; - * config->enableCanfdNormal = false; - * config->enableCanfdSwitch = false; - * config->enableLoopBackInt = false; - * config->enableLoopBackExt = false; - * config->enableBusMon = false; - * - * @param config Pointer to the MCAN configuration structure. - */ -void MCAN_GetDefaultConfig(mcan_config_t *config); - -/*! - * @brief MCAN enters normal mode. - * - * After initialization, INIT bit in CCCR register must be cleared to enter - * normal mode thus synchronizes to the CAN bus and ready for communication. - * - * @param base MCAN peripheral base address. - */ -void MCAN_EnterNormalMode(CAN_Type *base); - -/*! - * @name Configuration. - * @{ - */ - -/*! - * @brief Sets the MCAN Message RAM base address. - * - * This function sets the Message RAM base address. - * - * @param base MCAN peripheral base address. - * @param value Desired Message RAM base. - */ -static inline void MCAN_SetMsgRAMBase(CAN_Type *base, uint32_t value) -{ - assert(((value >= 0x20000000U) && (value <= 0x20027FFFU)) || ((value >= 0x04000000U) && (value <= 0x04007FFFU))); - - base->MRBA = CAN_MRBA_BA(value >> 16U); -} - -/*! - * @brief Gets the MCAN Message RAM base address. - * - * This function gets the Message RAM base address. - * - * @param base MCAN peripheral base address. - * @return Message RAM base address. - */ -static inline uint32_t MCAN_GetMsgRAMBase(CAN_Type *base) -{ - return base->MRBA; -} - -/*! - * @brief Calculates the improved timing values by specific baudrates for classical CAN - * - * @param baudRate The classical CAN speed in bps defined by user - * @param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching - * @param pconfig Pointer to the MCAN timing configuration structure. - * - * @return TRUE if timing configuration found, FALSE if failed to find configuration - */ -bool MCAN_CalculateImprovedTimingValues(uint32_t baudRate, uint32_t sourceClock_Hz, mcan_timing_config_t *pconfig); - -/*! - * @brief Sets the MCAN protocol arbitration phase timing characteristic. - * - * This function gives user settings to CAN bus timing characteristic. - * The function is for an experienced user. For less experienced users, call - * the MCAN_Init() and fill the baud rate field with a desired value. - * This provides the default arbitration phase timing characteristics. - * - * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate - * set in MCAN_Init(). - * - * @param base MCAN peripheral base address. - * @param config Pointer to the timing configuration structure. - */ -void MCAN_SetArbitrationTimingConfig(CAN_Type *base, const mcan_timing_config_t *config); - -/*! - * @brief Set Baud Rate of MCAN classic mode. - * - * This function set the baud rate of MCAN base on MCAN_CalculateImprovedTimingValues() API calculated timing values. - * - * @param base MCAN peripheral base address. - * @param sourceClock_Hz Source Clock in Hz. - * @param baudRate_Bps Baud Rate in Bps. - * @return kStatus_Success - Set CAN baud rate (only has Nominal phase) successfully. - */ -status_t MCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Bps); - -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) -/*! - * @brief Calculates the improved timing values by specific baudrates for CANFD - * - * @param baudRate The CANFD bus control speed in bps defined by user - * @param baudRateFD The CANFD bus data speed in bps defined by user - * @param sourceClock_Hz The Source clock data speed in bps. - * @param pconfig Pointer to the MCAN timing configuration structure. - * - * @return TRUE if timing configuration found, FALSE if failed to find configuration - */ -bool MCAN_FDCalculateImprovedTimingValues(uint32_t baudRate, - uint32_t baudRateFD, - uint32_t sourceClock_Hz, - mcan_timing_config_t *pconfig); - -/*! - * @brief Set Baud Rate of MCAN FD mode. - * - * This function set the baud rate of MCAN FD base on MCAN_FDCalculateImprovedTimingValues API calculated timing values. - * - * @param base MCAN peripheral base address. - * @param sourceClock_Hz Source Clock in Hz. - * @param baudRateN_Bps Nominal Baud Rate in Bps. - * @param baudRateD_Bps Data Baud Rate in Bps. - * @return kStatus_Success - Set CAN FD baud rate (include Nominal and Data phase) successfully. - */ -status_t MCAN_SetBaudRateFD(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateN_Bps, uint32_t baudRateD_Bps); -/*! - * @brief Sets the MCAN protocol data phase timing characteristic. - * - * This function gives user settings to CAN bus timing characteristic. - * The function is for an experienced user. For less experienced users, call - * the MCAN_Init() and fill the baud rate field with a desired value. - * This provides the default data phase timing characteristics. - * - * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate - * set in MCAN_Init(). - * - * @param base MCAN peripheral base address. - * @param config Pointer to the timing configuration structure. - */ -void MCAN_SetDataTimingConfig(CAN_Type *base, const mcan_timing_config_t *config); -#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */ - -/*! - * @brief Configures an MCAN receive fifo 0 buffer. - * - * This function sets start address, element size, watermark, operation mode - * and datafield size of the recieve fifo 0. - * - * @param base MCAN peripheral base address. - * @param config The receive fifo 0 configuration structure. - */ -void MCAN_SetRxFifo0Config(CAN_Type *base, const mcan_rx_fifo_config_t *config); - -/*! - * @brief Configures an MCAN receive fifo 1 buffer. - * - * This function sets start address, element size, watermark, operation mode - * and datafield size of the recieve fifo 1. - * - * @param base MCAN peripheral base address. - * @param config The receive fifo 1 configuration structure. - */ -void MCAN_SetRxFifo1Config(CAN_Type *base, const mcan_rx_fifo_config_t *config); - -/*! - * @brief Configures an MCAN receive buffer. - * - * This function sets start address and datafield size of the recieve buffer. - * - * @param base MCAN peripheral base address. - * @param config The receive buffer configuration structure. - */ -void MCAN_SetRxBufferConfig(CAN_Type *base, const mcan_rx_buffer_config_t *config); - -/*! - * @brief Configures an MCAN transmit event fifo. - * - * This function sets start address, element size, watermark of the transmit event fifo. - * - * @param base MCAN peripheral base address. - * @param config The transmit event fifo configuration structure. - */ -void MCAN_SetTxEventFifoConfig(CAN_Type *base, const mcan_tx_fifo_config_t *config); - -/*! - * @brief Configures an MCAN transmit buffer. - * - * This function sets start address, element size, fifo/queue mode and datafield - * size of the transmit buffer. - * - * @param base MCAN peripheral base address. - * @param config The transmit buffer configuration structure. - */ -void MCAN_SetTxBufferConfig(CAN_Type *base, const mcan_tx_buffer_config_t *config); - -/*! - * @brief Set filter configuration. - * - * This function sets remote and non masking frames in global filter configuration, - * also the start address, list size in standard/extended ID filter configuration. - * - * @param base MCAN peripheral base address. - * @param config The MCAN filter configuration. - */ -void MCAN_SetFilterConfig(CAN_Type *base, const mcan_frame_filter_config_t *config); - -/*! - * @brief Set standard message ID filter element configuration. - * - * @param base MCAN peripheral base address. - * @param config The MCAN filter configuration. - * @param filter The MCAN standard message ID filter element configuration. - * @param idx The standard message ID filter element index. - */ -void MCAN_SetSTDFilterElement(CAN_Type *base, - const mcan_frame_filter_config_t *config, - const mcan_std_filter_element_config_t *filter, - uint8_t idx); - -/*! - * @brief Set extended message ID filter element configuration. - * - * @param base MCAN peripheral base address. - * @param config The MCAN filter configuration. - * @param filter The MCAN extended message ID filter element configuration. - * @param idx The extended message ID filter element index. - */ -void MCAN_SetEXTFilterElement(CAN_Type *base, - const mcan_frame_filter_config_t *config, - const mcan_ext_filter_element_config_t *filter, - uint8_t idx); - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the MCAN module interrupt flags. - * - * This function gets all MCAN interrupt status flags. - * - * @param base MCAN peripheral base address. - * @param mask The ORed MCAN interrupt mask. - * @return MCAN status flags which are ORed. - */ -static inline uint32_t MCAN_GetStatusFlag(CAN_Type *base, uint32_t mask) -{ - return (base->IR & mask); -} - -/*! - * @brief Clears the MCAN module interrupt flags. - * - * This function clears MCAN interrupt status flags. - * - * @param base MCAN peripheral base address. - * @param mask The ORed MCAN interrupt mask. - */ -static inline void MCAN_ClearStatusFlag(CAN_Type *base, uint32_t mask) -{ - /* Write 1 to clear status flag, write 0 has no effect. */ - base->IR = mask; -} - -/*! - * @brief Gets the new data flag of specific Rx Buffer. - * - * This function gets new data flag of specific Rx Buffer. - * - * @param base MCAN peripheral base address. - * @param idx Rx Buffer index. - * @return Rx Buffer new data status flag. - */ -static inline bool MCAN_GetRxBufferStatusFlag(CAN_Type *base, uint8_t idx) -{ - assert(idx <= 63U); - - bool fgRet; - - if (idx <= 31U) - { - fgRet = (0U != (base->NDAT1 & ((uint32_t)1U << idx))); - } - else - { - fgRet = (0U != (base->NDAT2 & ((uint32_t)1U << (idx - 32U)))); - } - - return fgRet; -} - -/*! - * @brief Clears the new data flag of specific Rx Buffer. - * - * This function clears new data flag of specific Rx Buffer. - * - * @param base MCAN peripheral base address. - * @param idx Rx Buffer index. - */ -static inline void MCAN_ClearRxBufferStatusFlag(CAN_Type *base, uint8_t idx) -{ - assert(idx <= 63U); - - if (idx <= 31U) - { - base->NDAT1 = ((uint32_t)1U << idx); - } - else - { - base->NDAT2 = ((uint32_t)1U << (idx - 32U)); - } -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables MCAN interrupts according to the provided interrupt line and mask. - * - * This function enables the MCAN interrupts according to the provided interrupt line and mask. - * The mask is a logical OR of enumeration members. - * - * @param base MCAN peripheral base address. - * @param line Interrupt line number, 0 or 1. - * @param mask The interrupts to enable. - */ -static inline void MCAN_EnableInterrupts(CAN_Type *base, uint32_t line, uint32_t mask) -{ - base->ILE |= ((uint32_t)1U << line); - if (0U == line) - { - base->ILS &= ~mask; - } - else - { - base->ILS |= mask; - } - base->IE |= mask; -} - -/*! - * @brief Enables MCAN Tx Buffer interrupts according to the provided index. - * - * This function enables the MCAN Tx Buffer interrupts. - * - * @param base MCAN peripheral base address. - * @param idx Tx Buffer index. - */ -static inline void MCAN_EnableTransmitBufferInterrupts(CAN_Type *base, uint8_t idx) -{ - base->TXBTIE |= ((uint32_t)1U << idx); -} - -/*! - * @brief Disables MCAN Tx Buffer interrupts according to the provided index. - * - * This function disables the MCAN Tx Buffer interrupts. - * - * @param base MCAN peripheral base address. - * @param idx Tx Buffer index. - */ -static inline void MCAN_DisableTransmitBufferInterrupts(CAN_Type *base, uint8_t idx) -{ - base->TXBTIE &= (~((uint32_t)1U << idx)); -} - -/*! - * @brief Disables MCAN interrupts according to the provided mask. - * - * This function disables the MCAN interrupts according to the provided mask. - * The mask is a logical OR of enumeration members. - * - * @param base MCAN peripheral base address. - * @param mask The interrupts to disable. - */ -static inline void MCAN_DisableInterrupts(CAN_Type *base, uint32_t mask) -{ - base->IE &= ~mask; -} - -/* @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Gets the Tx buffer request pending status. - * - * This function returns Tx Message Buffer transmission request pending status. - * - * @param base MCAN peripheral base address. - * @param idx The MCAN Tx Buffer index. - */ -uint32_t MCAN_IsTransmitRequestPending(CAN_Type *base, uint8_t idx); - -/*! - * @brief Gets the Tx buffer transmission occurred status. - * - * This function returns Tx Message Buffer transmission occurred status. - * - * @param base MCAN peripheral base address. - * @param idx The MCAN Tx Buffer index. - */ -uint32_t MCAN_IsTransmitOccurred(CAN_Type *base, uint8_t idx); - -/*! - * @brief Writes an MCAN Message to the Transmit Buffer. - * - * This function writes a CAN Message to the specified Transmit Message Buffer - * and changes the Message Buffer state to start CAN Message transmit. After - * that the function returns immediately. - * - * @param base MCAN peripheral base address. - * @param idx The MCAN Tx Buffer index. - * @param pTxFrame Pointer to CAN message frame to be sent. - */ -status_t MCAN_WriteTxBuffer(CAN_Type *base, uint8_t idx, const mcan_tx_buffer_frame_t *pTxFrame); - -/*! - * @brief Reads an MCAN Message from Rx Buffer. - * - * This function reads a CAN message from the Rx Buffer in the Message RAM. - * - * @param base MCAN peripheral base address. - * @param idx The MCAN Rx Buffer index. - * @param pRxFrame Pointer to CAN message frame structure for reception. - * @retval kStatus_Success - Read Message from Rx Buffer successfully. - */ -status_t MCAN_ReadRxBuffer(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *pRxFrame); - -/*! - * @brief Reads an MCAN Message from Rx FIFO. - * - * This function reads a CAN message from the Rx FIFO in the Message RAM. - * - * @param base MCAN peripheral base address. - * @param fifoBlock Rx FIFO block 0 or 1. - * @param pRxFrame Pointer to CAN message frame structure for reception. - * @retval kStatus_Success - Read Message from Rx FIFO successfully. - */ -status_t MCAN_ReadRxFifo(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *pRxFrame); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Tx Buffer add request to send message out. - * - * This function add sending request to corresponding Tx Buffer. - * - * @param base MCAN peripheral base address. - * @param idx Tx Buffer index. - */ -static inline void MCAN_TransmitAddRequest(CAN_Type *base, uint8_t idx) -{ - base->TXBAR = ((uint32_t)1U << idx); -} - -/*! - * @brief Tx Buffer cancel sending request. - * - * This function clears Tx buffer request pending bit. - * - * @param base MCAN peripheral base address. - * @param idx Tx Buffer index. - */ -static inline void MCAN_TransmitCancelRequest(CAN_Type *base, uint8_t idx) -{ - base->TXBCR = ((uint32_t)1U << idx); -} - -/*! - * @brief Performs a polling send transaction on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * @param base MCAN peripheral base pointer. - * @param idx The MCAN buffer index. - * @param pTxFrame Pointer to CAN message frame to be sent. - * @retval kStatus_Success - Write Tx Message Buffer Successfully. - * @retval kStatus_Fail - Tx Message Buffer is currently in use. - */ -status_t MCAN_TransferSendBlocking(CAN_Type *base, uint8_t idx, mcan_tx_buffer_frame_t *pTxFrame); - -/*! - * @brief Performs a polling receive transaction on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * @param base MCAN peripheral base pointer. - * @param idx The MCAN buffer index. - * @param pRxFrame Pointer to CAN message frame structure for reception. - * @retval kStatus_Success - Read Rx Message Buffer Successfully. - * @retval kStatus_Fail - No new message. - */ -status_t MCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *pRxFrame); - -/*! - * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * @param base MCAN peripheral base pointer. - * @param fifoBlock Rx FIFO block, 0 or 1. - * @param pRxFrame Pointer to CAN message frame structure for reception. - * @retval kStatus_Success - Read Message from Rx FIFO successfully. - * @retval kStatus_Fail - No new message in Rx FIFO. - */ -status_t MCAN_TransferReceiveFifoBlocking(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *pRxFrame); - -/*! - * @brief Initializes the MCAN handle. - * - * This function initializes the MCAN handle, which can be used for other MCAN - * transactional APIs. Usually, for a specified MCAN instance, - * call this API once to get the initialized handle. - * - * @param base MCAN peripheral base address. - * @param handle MCAN handle pointer. - * @param callback The callback function. - * @param userData The parameter of the callback function. - */ -void MCAN_TransferCreateHandle(CAN_Type *base, - mcan_handle_t *handle, - mcan_transfer_callback_t callback, - void *userData); - -/*! - * @brief Sends a message using IRQ. - * - * This function sends a message using IRQ. This is a non-blocking function, which returns - * right away. When messages have been sent out, the send callback function is called. - * - * @param base MCAN peripheral base address. - * @param handle MCAN handle pointer. - * @param xfer MCAN Buffer transfer structure. See the #mcan_buffer_transfer_t. - * @retval kStatus_Success Start Tx Buffer sending process successfully. - * @retval kStatus_Fail Write Tx Buffer failed. - * @retval kStatus_MCAN_TxBusy Tx Buffer is in use. - */ -status_t MCAN_TransferSendNonBlocking(CAN_Type *base, mcan_handle_t *handle, mcan_buffer_transfer_t *xfer); - -/*! - * @brief Receives a message from Rx FIFO using IRQ. - * - * This function receives a message using IRQ. This is a non-blocking function, which returns - * right away. When all messages have been received, the receive callback function is called. - * - * @param base MCAN peripheral base address. - * @param handle MCAN handle pointer. - * @param fifoBlock Rx FIFO block, 0 or 1. - * @param xfer MCAN Rx FIFO transfer structure. See the @ref mcan_fifo_transfer_t. - * @retval kStatus_Success - Start Rx FIFO receiving process successfully. - * @retval kStatus_MCAN_RxFifo0Busy - Rx FIFO 0 is currently in use. - * @retval kStatus_MCAN_RxFifo1Busy - Rx FIFO 1 is currently in use. - */ -status_t MCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, - uint8_t fifoBlock, - mcan_handle_t *handle, - mcan_fifo_transfer_t *xfer); - -/*! - * @brief Aborts the interrupt driven message send process. - * - * This function aborts the interrupt driven message send process. - * - * @param base MCAN peripheral base address. - * @param handle MCAN handle pointer. - * @param bufferIdx The MCAN Buffer index. - */ -void MCAN_TransferAbortSend(CAN_Type *base, mcan_handle_t *handle, uint8_t bufferIdx); - -/*! - * @brief Aborts the interrupt driven message receive from Rx FIFO process. - * - * This function aborts the interrupt driven message receive from Rx FIFO process. - * - * @param base MCAN peripheral base address. - * @param fifoBlock MCAN Fifo block, 0 or 1. - * @param handle MCAN handle pointer. - */ -void MCAN_TransferAbortReceiveFifo(CAN_Type *base, uint8_t fifoBlock, mcan_handle_t *handle); - -/*! - * @brief MCAN IRQ handle function. - * - * This function handles the MCAN Error, the Buffer, and the Rx FIFO IRQ request. - * - * @param base MCAN peripheral base address. - * @param handle MCAN handle pointer. - */ -void MCAN_TransferHandleIRQ(CAN_Type *base, mcan_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_MCAN_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mrt.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mrt.c deleted file mode 100644 index 69697a21b5c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mrt.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_mrt.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.mrt" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base Multi-Rate timer peripheral base address - * - * @return The MRT instance - */ -static uint32_t MRT_GetInstance(MRT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to MRT bases for each instance. */ -static MRT_Type *const s_mrtBases[] = MRT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to MRT clocks for each instance. */ -static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(MRT_RSTS_N) -/*! @brief Pointers to MRT resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_mrtResets[] = MRT_RSTS_N; -#elif defined(MRT_RSTS) -/*! @brief Pointers to MRT resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_mrtResets[] = MRT_RSTS; -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t MRT_GetInstance(MRT_Type *base) -{ - uint32_t instance; - uint32_t mrtArrayCount = (sizeof(s_mrtBases) / sizeof(s_mrtBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < mrtArrayCount; instance++) - { - if (s_mrtBases[instance] == base) - { - break; - } - } - - assert(instance < mrtArrayCount); - - return instance; -} - -/*! - * brief Ungates the MRT clock and configures the peripheral for basic operation. - * - * note This API should be called at the beginning of the application using the MRT driver. - * - * param base Multi-Rate timer peripheral base address - * param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in - * MODCFG reigster, param config is useless. - */ -void MRT_Init(MRT_Type *base, const mrt_config_t *config) -{ - assert(config != NULL); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate the MRT clock */ - CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(MRT_RSTS_N) || defined(MRT_RSTS) - /* Reset the module. */ - RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]); -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) - /* Set timer operating mode */ - base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask); -#endif -} - -/*! - * brief Gate the MRT clock - * - * param base Multi-Rate timer peripheral base address - */ -void MRT_Deinit(MRT_Type *base) -{ - /* Stop all the timers */ - MRT_StopTimer(base, kMRT_Channel_0); - MRT_StopTimer(base, kMRT_Channel_1); -#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 2U) - MRT_StopTimer(base, kMRT_Channel_2); -#endif -#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 3U) - MRT_StopTimer(base, kMRT_Channel_3); -#endif - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the MRT clock*/ - CLOCK_DisableClock(s_mrtClocks[MRT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Used to update the timer period in units of count. - * - * The new value will be immediately loaded or will be loaded at the end of the current time - * interval. For one-shot interrupt mode the new value will be immediately loaded. - * - * note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * param base Multi-Rate timer peripheral base address - * param channel Timer channel number - * param count Timer period in units of ticks - * param immediateLoad true: Load the new value immediately into the TIMER register; - * false: Load the new value at the end of current timer interval - */ -void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - - uint32_t newValue = count; - if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == (uint8_t)kMRT_OneShotMode) || (immediateLoad)) - { - /* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */ - newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK; - } - - /* Update the timer interval value */ - base->CHANNEL[channel].INTVAL = newValue; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mrt.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mrt.h deleted file mode 100644 index 7829d984e20..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mrt.h +++ /dev/null @@ -1,366 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_MRT_H_ -#define _FSL_MRT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup mrt - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3 */ -/*@}*/ - -/*! @brief List of MRT channels */ -typedef enum _mrt_chnl -{ - kMRT_Channel_0 = 0U, /*!< MRT channel number 0*/ - kMRT_Channel_1, /*!< MRT channel number 1 */ - kMRT_Channel_2, /*!< MRT channel number 2 */ - kMRT_Channel_3 /*!< MRT channel number 3 */ -} mrt_chnl_t; - -/*! @brief List of MRT timer modes */ -typedef enum _mrt_timer_mode -{ - kMRT_RepeatMode = (0 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< Repeat Interrupt mode */ - kMRT_OneShotMode = (1 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< One-shot Interrupt mode */ - kMRT_OneShotStallMode = (2 << MRT_CHANNEL_CTRL_MODE_SHIFT) /*!< One-shot stall mode */ -} mrt_timer_mode_t; - -/*! @brief List of MRT interrupts */ -typedef enum _mrt_interrupt_enable -{ - kMRT_TimerInterruptEnable = MRT_CHANNEL_CTRL_INTEN_MASK /*!< Timer interrupt enable*/ -} mrt_interrupt_enable_t; - -/*! @brief List of MRT status flags */ -typedef enum _mrt_status_flags -{ - kMRT_TimerInterruptFlag = MRT_CHANNEL_STAT_INTFLAG_MASK, /*!< Timer interrupt flag */ - kMRT_TimerRunFlag = MRT_CHANNEL_STAT_RUN_MASK, /*!< Indicates state of the timer */ -} mrt_status_flags_t; - -/*! - * @brief MRT configuration structure - * - * This structure holds the configuration settings for the MRT peripheral. To initialize this - * structure to reasonable defaults, call the MRT_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _mrt_config -{ - bool enableMultiTask; /*!< true: Timers run in multi-task mode; false: Timers run in hardware status mode */ -} mrt_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the MRT clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the MRT driver. - * - * @param base Multi-Rate timer peripheral base address - * @param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in - * MODCFG reigster, param config is useless. - */ -void MRT_Init(MRT_Type *base, const mrt_config_t *config); - -/*! - * @brief Gate the MRT clock - * - * @param base Multi-Rate timer peripheral base address - */ -void MRT_Deinit(MRT_Type *base); - -/*! - * @brief Fill in the MRT config struct with the default settings - * - * The default values are: - * @code - * config->enableMultiTask = false; - * @endcode - * @param config Pointer to user's MRT config structure. - */ -static inline void MRT_GetDefaultConfig(mrt_config_t *config) -{ - assert(config != NULL); -#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) - /* Use hardware status operating mode */ - config->enableMultiTask = false; -#endif -} - -/*! - * @brief Sets up an MRT channel mode. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Channel that is being configured. - * @param mode Timer mode to use for the channel. - */ -static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - - uint32_t reg = base->CHANNEL[channel].CTRL; - - /* Clear old value */ - reg &= ~MRT_CHANNEL_CTRL_MODE_MASK; - /* Add the new mode */ - reg |= (uint32_t)mode; - - base->CHANNEL[channel].CTRL = reg; -} - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the MRT interrupt. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].CTRL |= mask; -} - -/*! - * @brief Disables the selected MRT interrupt. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to disable. This is a logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].CTRL &= ~mask; -} - -/*! - * @brief Gets the enabled MRT interrupts. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the MRT status flags - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::mrt_status_flags_t - */ -static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK)); -} - -/*! - * @brief Clears the MRT status flags. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::mrt_status_flags_t - */ -static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK); -} - -/*! @}*/ - -/*! - * @name Read and Write the timer period - * @{ - */ - -/*! - * @brief Used to update the timer period in units of count. - * - * The new value will be immediately loaded or will be loaded at the end of the current time - * interval. For one-shot interrupt mode the new value will be immediately loaded. - * - * @note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param count Timer period in units of ticks - * @param immediateLoad true: Load the new value immediately into the TIMER register; - * false: Load the new value at the end of current timer interval - */ -void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad); - -/*! - * @brief Reads the current timer counting value. - * - * This function returns the real-time timer counting value, in a range from 0 to a - * timer period. - * - * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return Current timer counting value in ticks - */ -static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - return base->CHANNEL[channel].TIMER; -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the timer counting. - * - * After calling this function, timers load period value, counts down to 0 and - * depending on the timer mode it will either load the respective start value again or stop. - * - * @note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - * @param count Timer period in units of ticks. Count can contain the LOAD bit, which control the force load feature. - */ -static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - assert((uint32_t)(count & ~MRT_CHANNEL_INTVAL_LOAD_MASK) <= (uint32_t)MRT_CHANNEL_INTVAL_IVALUE_MASK); - /* Write the timer interval value */ - base->CHANNEL[channel].INTVAL = count; -} - -/*! - * @brief Stops the timer counting. - * - * This function stops the timer from counting. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - */ -static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - /* Stop the timer immediately */ - base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK; -} - -/*! @}*/ - -/*! - * @name Get & release channel - * @{ - */ - -/*! - * @brief Find the available channel. - * - * This function returns the lowest available channel number. - * - * @param base Multi-Rate timer peripheral base address - */ -static inline uint32_t MRT_GetIdleChannel(MRT_Type *base) -{ - return base->IDLE_CH; -} - -#if !(defined(FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) && FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) -/*! - * @brief Release the channel when the timer is using the multi-task mode. - * - * In multi-task mode, the INUSE flags allow more control over when MRT channels are released for - * further use. The user can hold on to a channel acquired by calling MRT_GetIdleChannel() for as - * long as it is needed and release it by calling this function. This removes the need to ask for - * an available channel for every use. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - */ -static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - - uint32_t reg = base->CHANNEL[channel].STAT; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg = ~MRT_CHANNEL_STAT_INTFLAG_MASK; - reg |= MRT_CHANNEL_STAT_INUSE_MASK; - - base->CHANNEL[channel].STAT = reg; -} -#endif - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_MRT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ostimer.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ostimer.c deleted file mode 100644 index c3acfb0e48f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ostimer.c +++ /dev/null @@ -1,381 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_ostimer.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.ostimer" -#endif - -/* Typedef for interrupt handler. */ -typedef void (*ostimer_isr_t)(OSTIMER_Type *base, ostimer_callback_t cb); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base OSTIMER peripheral base address - * - * @return The OSTIMER instance - */ -static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base); - -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) -/* @brief Translate the value from gray-code to decimal by the Code Gray in SYSCTL. - * - * @param gray The gray value input. - * - * @return the decimal value. - */ -static uint64_t OSTIMER_GrayToDecimalbyCodeGray(uint64_t gray); -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of OSTIMER handle. */ -static ostimer_callback_t s_ostimerHandle[FSL_FEATURE_SOC_OSTIMER_COUNT]; -/* Array of OSTIMER peripheral base address. */ -static OSTIMER_Type *const s_ostimerBases[] = OSTIMER_BASE_PTRS; -/* Array of OSTIMER IRQ number. */ -static const IRQn_Type s_ostimerIRQ[] = OSTIMER_IRQS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of OSTIMER clock name. */ -static const clock_ip_name_t s_ostimerClock[] = OSTIMER_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/* OSTIMER ISR for transactional APIs. */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -static ostimer_isr_t s_ostimerIsr = (ostimer_isr_t)DefaultISR; -#else -static ostimer_isr_t s_ostimerIsr; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* @brief Function for getting the instance number of OS timer. */ -static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_ostimerBases); instance++) - { - if (s_ostimerBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_ostimerBases)); - - return instance; -} - -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) -/* @brief Translate the value from gray-code to decimal by the Code Gray in SYSCTL. - * - * @param gray The gray value input. - * - * @return the decimal value. - */ -static uint64_t OSTIMER_GrayToDecimalbyCodeGray(uint64_t gray) -{ - uint64_t decOut; - - SYSCTL->CODE_GRAY_LSB = (uint32_t)(gray & 0xFFFFFFFFU); - SYSCTL->CODE_GRAY_MSB = (uint32_t)((gray >> 32U) & 0x3FFU); // limit to 42bits as OSevent timer - __NOP(); - decOut = ((uint64_t)(SYSCTL->CODE_BIN_MSB) & 0x3FFU) << 32U; - decOut |= (uint64_t)(SYSCTL->CODE_BIN_LSB); - - return decOut; -} -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ - -/* @brief Translate the value from gray-code to decimal. */ -/* - * @param gray The gray value input. - * - * @return the decimal value. - */ -uint64_t OSTIMER_GrayToDecimal(uint64_t gray) -{ -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) - return OSTIMER_GrayToDecimalbyCodeGray(gray); -#else - uint64_t temp = gray; - while (temp != 0U) - { - temp >>= 1U; - gray ^= temp; - } - - return gray; -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ -} - -/* @brief Enable the OSTIMER interrupt. - * - * After calling this function, the OSTIMER driver will enable/disable the IRQ and module interrupt enablement. - * - * @param base OSTIMER peripheral base address. - * @param enable enable/disable the IRQ and module interrupt enablement. - * - true: Disable the IRQ and module interrupt enablement. - * - false: Disable the IRQ and module interrupt enablement. - * @return none - */ -static void OSTIMER_EnableInterrupt(OSTIMER_Type *base, bool enable) -{ - assert(NULL != base); - - if (enable) - { - /* Enable the IRQ and module interrupt enablement. */ - (void)EnableIRQ(s_ostimerIRQ[OSTIMER_GetInstance(base)]); - base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; - } - else - { - /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ - (void)DisableIRQ(s_ostimerIRQ[OSTIMER_GetInstance(base)]); - base->OSEVENT_CTRL &= ~OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; /* Clear interrupt flag by writing 1. */ - } -} - -/*! - * @brief Initializes an OSTIMER by turning it's clock on. - * - */ -void OSTIMER_Init(OSTIMER_Type *base) -{ - assert(NULL != base); - - uint32_t instance = OSTIMER_GetInstance(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if !(defined(FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) && FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) - /* Enable the OSTIMER 32k clock in PMC module. */ - CLOCK_EnableOstimer32kClock(); -#endif - /* Enable clock for OSTIMER. */ - CLOCK_EnableClock(s_ostimerClock[instance]); -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) - CLOCK_EnableClock(kCLOCK_Sysctl); -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Deinitializes a OSTIMER instance. - * - * This function shuts down OSTIMER clock - * - * @param base OSTIMER peripheral base address. - */ -void OSTIMER_Deinit(OSTIMER_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable clock for OSTIMER. */ - CLOCK_DisableClock(s_ostimerClock[OSTIMER_GetInstance(base)]); -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) - CLOCK_DisableClock(kCLOCK_Sysctl); -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Get OSTIMER status Flags. - * - * This returns the status flag. - * Currently, only match interrupt flag can be got. - * - * @param base OSTIMER peripheral base address. - * @return status register value - */ -uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base) -{ - return base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK; -} - -/*! - * @brief Clear Status Interrupt Flags. - * - * This clears intr status flag. - * Currently, only match interrupt flag can be cleared. - * - * @param base OSTIMER peripheral base address. - * @param mask Clear bit mask. - * @return none - */ -void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask) -{ - base->OSEVENT_CTRL |= mask; -} - -/*! - * @brief Set the match raw value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. - * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is gray-code format) - * - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. - * @retval kStatus_Fail - Set match raw value fail. - */ -status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) -{ -#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK - uint64_t decValueTimer; -#endif - status_t status; - uint64_t tmp = count; - uint32_t instance = OSTIMER_GetInstance(base); - - /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ - OSTIMER_EnableInterrupt(base, false); - - s_ostimerIsr = OSTIMER_HandleIRQ; - s_ostimerHandle[instance] = cb; - - /* Set the match value. */ - base->MATCH_L = (uint32_t)tmp; - base->MATCH_H = (uint32_t)(tmp >> 32U); - -#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK - /* Workaround-2019-12-30: - * Since OSTimer's counter register is Gray-encoded, it would cost more time to write register. When EVTimer Match - * Write Ready bit is low, which means the previous match value has been updated successfully by that time, it is - * safe to reload (write) the Match Registers. Even if there is the RM comment that "In typical applications, it - * should not be necessary to test this bit", but we found the interruption would not be reported when the delta - * timer user added is smaller(IE: RT595 11us in 1MHz typical application) in release version." To prevent such - * issue from happening, we'd better wait for the match value to update successfully before enabling IRQ. - */ - while (0U != (base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)) - { - } - - /* After the WR_RDY bit became low, we need to check whether current time goes ahead of the match value we set. - * (1) If current timer value has gone ahead of the match value, the interrupt will not be reported before 64-bit - * timer value over flow. We need to check whether the interrupt flag has been set or not: if yes, we will enable - * interrupt and return success; if not, we will return fail directly. - * (2) If current timer value has not gone ahead of match value, we will enable interrupt and return success. - */ - decValueTimer = OSTIMER_GetCurrentTimerValue(base); - if ((decValueTimer >= OSTIMER_GrayToDecimal(tmp)) && - (0U == (base->OSEVENT_CTRL & (uint32_t)kOSTIMER_MatchInterruptFlag))) - { - status = kStatus_Fail; - } - else -#endif /* #ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK */ - { - /* Enable the module interrupt enablement. */ - OSTIMER_EnableInterrupt(base, true); - status = kStatus_Success; - } - - return status; -} - -/*! - * @brief Set the match value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code in - * API. ) - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @retval kStatus_Success - Set match value and enable interrupt Successfully. - * @retval kStatus_Fail - Set match value fail. - */ -status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) -{ - uint64_t tmp = OSTIMER_DecimalToGray(count); - - return OSTIMER_SetMatchRawValue(base, tmp, cb); -} - -/*! - * @brief Get current timer count value from OSTIMER. - * - * This function will get a decimal timer count value. - * The RAW value of timer count is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of OSTIMER which will formated to decimal value. - */ -uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = OSTIMER_GetCurrentTimerRawValue(base); - - return OSTIMER_GrayToDecimal(tmp); -} - -/*! - * @brief Get the capture value from OSTIMER. - * - * This function will get a capture decimal-value from OSTIMER. - * The RAW value of timer capture is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of capture register, data format is decimal. - */ -uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = OSTIMER_GetCaptureRawValue(base); - - return OSTIMER_GrayToDecimal(tmp); -} - -void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb) -{ - /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ - OSTIMER_EnableInterrupt(base, false); - - if (cb != NULL) - { - cb(); - } -} - -#if defined(OSTIMER0) -void OS_EVENT_DriverIRQHandler(void); -void OS_EVENT_DriverIRQHandler(void) -{ - s_ostimerIsr(OSTIMER0, s_ostimerHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(OSTIMER) -void OS_EVENT_DriverIRQHandler(void); -void OS_EVENT_DriverIRQHandler(void) -{ - s_ostimerIsr(OSTIMER, s_ostimerHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ostimer.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ostimer.h deleted file mode 100644 index c74a7931362..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ostimer.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_OSTIMER_H_ -#define _FSL_OSTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup ostimer - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief OSTIMER driver version. */ -#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) -/*@}*/ - -/*! - * @brief OSTIMER status flags. - */ -enum _ostimer_flags -{ - kOSTIMER_MatchInterruptFlag = (OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK), /*!< Match interrupt flag bit, sets if - the match value was reached. */ -}; - -/*! @brief ostimer callback function. */ -typedef void (*ostimer_callback_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes an OSTIMER by turning its bus clock on - * - */ -void OSTIMER_Init(OSTIMER_Type *base); - -/*! - * @brief Deinitializes a OSTIMER instance. - * - * This function shuts down OSTIMER bus clock - * - * @param base OSTIMER peripheral base address. - */ -void OSTIMER_Deinit(OSTIMER_Type *base); - -/*! - * @brief Translate the value from gray-code to decimal. - * - * @param gray The gray value input. - * @return The decimal value. - */ -uint64_t OSTIMER_GrayToDecimal(uint64_t gray); - -/*! - * @brief Translate the value from decimal to gray-code. - * - * @param dec The decimal value. - * @return The gray code of the input value. - */ -static inline uint64_t OSTIMER_DecimalToGray(uint64_t dec) -{ - return (dec ^ (dec >> 1U)); -} - -/*! - * @brief Get OSTIMER status Flags. - * - * This returns the status flag. - * Currently, only match interrupt flag can be got. - * - * @param base OSTIMER peripheral base address. - * @return status register value - */ -uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base); - -/*! - * @brief Clear Status Interrupt Flags. - * - * This clears intrrupt status flag. - * Currently, only match interrupt flag can be cleared. - * - * @param base OSTIMER peripheral base address. - * @param mask Clear bit mask. - * @return none - */ -void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask); - -/*! - * @brief Set the match raw value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. - * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is gray-code format) - * - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. - * @retval kStatus_Fail - Set match raw value fail. - */ -status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); - -/*! - * @brief Set the match value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central OS TIMER. - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code - * internally.) - * - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @retval kStatus_Success - Set match value and enable interrupt Successfully. - * @retval kStatus_Fail - Set match value fail. - */ -status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); - -/*! - * @brief Set value to OSTIMER MATCH register directly. - * - * This function writes the input value to OSTIMER MATCH register directly, - * it does not touch any other registers. Note that, the data format is - * gray-code. The function @ref OSTIMER_DecimalToGray could convert decimal - * value to gray code. - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value (Value is gray-code format). - */ -static inline void OSTIMER_SetMatchRegister(OSTIMER_Type *base, uint64_t value) -{ -#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK - /* Wait for MATCH register ready for write. */ - while (0U != (base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)) - { - } -#endif - - base->MATCH_L = (uint32_t)value; - base->MATCH_H = (uint32_t)(value >> 32U); -} - -/*! - * @brief Enable the OSTIMER counter match interrupt. - * - * Enable the timer counter match interrupt. The interrupt happens when OSTIMER - * counter matches the value in MATCH registers. - * - * @param base OSTIMER peripheral base address. - */ -static inline void OSTIMER_EnableMatchInterrupt(OSTIMER_Type *base) -{ - base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; -} - -/*! - * @brief Disable the OSTIMER counter match interrupt. - * - * Disable the timer counter match interrupt. The interrupt happens when OSTIMER - * counter matches the value in MATCH registers. - * - * @param base OSTIMER peripheral base address. - */ -static inline void OSTIMER_DisableMatchInterrupt(OSTIMER_Type *base) -{ - base->OSEVENT_CTRL &= ~OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; -} - -/*! - * @brief Get current timer raw count value from OSTIMER. - * - * This function will get a gray code type timer count value from OS timer register. - * The raw value of timer count is gray code format. - * - * @param base OSTIMER peripheral base address. - * @return Raw value of OSTIMER, gray code format. - */ -static inline uint64_t OSTIMER_GetCurrentTimerRawValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = base->EVTIMERL; - tmp |= (uint64_t)(base->EVTIMERH) << 32U; - - return tmp; -} - -/*! - * @brief Get current timer count value from OSTIMER. - * - * This function will get a decimal timer count value. - * The RAW value of timer count is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of OSTIMER which will be formated to decimal value. - */ -uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base); - -/*! - * @brief Get the capture value from OSTIMER. - * - * This function will get a captured gray-code value from OSTIMER. - * The Raw value of timer capture is gray code format. - * - * @param base OSTIMER peripheral base address. - * @return Raw value of capture register, data format is gray code. - */ -static inline uint64_t OSTIMER_GetCaptureRawValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = base->CAPTURE_L; - tmp |= (uint64_t)(base->CAPTURE_H) << 32U; - - return tmp; -} - -/*! - * @brief Get the capture value from OSTIMER. - * - * This function will get a capture decimal-value from OSTIMER. - * The RAW value of timer capture is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of capture register, data format is decimal. - */ -uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base); - -/*! - * @brief OS timer interrupt Service Handler. - * - * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request - * in OSTIMER_SetMatchValue()). - * if no user callback is scheduled, the interrupt will simply be cleared. - * - * @param base OS timer peripheral base address. - * @param cb callback scheduled for this instance of OS timer - * @return none - */ -void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb); -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_OSTIMER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_pint.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_pint.c deleted file mode 100644 index 74b44ea7ad5..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_pint.c +++ /dev/null @@ -1,971 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_pint.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.pint" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -/*! @brief Irq number array */ -static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS + - FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; - -/*! @brief Callback function array for SECPINT(s). */ -static pint_cb_t s_secpintCallback[FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS]; -#else -/*! @brief Irq number array */ -static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - -/*! @brief Callback function array for PINT(s). */ -static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Initialize PINT peripheral. - - * This function initializes the PINT peripheral and enables the clock. - * - * param base Base address of the PINT peripheral. - * - * retval None. - */ -void PINT_Init(PINT_Type *base) -{ - uint32_t i; - uint32_t pmcfg = 0; - uint8_t pintcount = 0; - assert(base != NULL); - - if (base == PINT) - { - pintcount = FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; - /* clear PINT callback array*/ - for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_pintCallback[i] = NULL; - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - pintcount = FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; - /* clear SECPINT callback array*/ - for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_secpintCallback[i] = NULL; - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - - /* Disable all bit slices for pint*/ - for (i = 0; i < pintcount; i++) - { - pmcfg = pmcfg | ((uint32_t)kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U))); - } - -#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_GpioInt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) - - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio_Sec); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - -#else - - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Pint); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } - else - { - /* if need config SECURE PINT device,then enable secure pint interrupt clock */ -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio_Sec_Int); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } -#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ - - /* Disable all pattern match bit slices */ - base->PMCFG = pmcfg; -} - -/*! - * brief Configure PINT peripheral pin interrupt. - - * This function configures a given pin interrupt. - * - * param base Base address of the PINT peripheral. - * param intr Pin interrupt. - * param enable Selects detection logic. - * param callback Callback. - * - * retval None. - */ -void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback) -{ - assert(base != NULL); - - /* Clear Rise and Fall flags first */ - PINT_PinInterruptClrRiseFlag(base, intr); - PINT_PinInterruptClrFallFlag(base, intr); - - /* Security PINT uses additional callback array */ - if (base == PINT) - { - s_pintCallback[intr] = callback; - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - s_secpintCallback[intr] = callback; -#endif - } - - /* select level or edge sensitive */ - base->ISEL = (base->ISEL & ~(1UL << (uint32_t)intr)) | - ((((uint32_t)enable & PINT_PIN_INT_LEVEL) != 0U) ? (1UL << (uint32_t)intr) : 0U); - - /* enable rising or level interrupt */ - if (((unsigned)enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE)) != 0U) - { - base->SIENR = 1UL << (uint32_t)intr; - } - else - { - base->CIENR = 1UL << (uint32_t)intr; - } - - /* Enable falling or select high level */ - if (((unsigned)enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL) != 0U) - { - base->SIENF = 1UL << (uint32_t)intr; - } - else - { - base->CIENF = 1UL << (uint32_t)intr; - } -} - -/*! - * brief Get PINT peripheral pin interrupt configuration. - - * This function returns the configuration of a given pin interrupt. - * - * param base Base address of the PINT peripheral. - * param pintr Pin interrupt. - * param enable Pointer to store the detection logic. - * param callback Callback. - * - * retval None. - */ -void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback) -{ - uint32_t mask; - bool level; - - assert(base != NULL); - - *enable = kPINT_PinIntEnableNone; - level = false; - - mask = 1UL << (uint32_t)pintr; - if ((base->ISEL & mask) != 0U) - { - /* Pin interrupt is level sensitive */ - level = true; - } - - if ((base->IENR & mask) != 0U) - { - if (level) - { - /* Level interrupt is enabled */ - *enable = kPINT_PinIntEnableLowLevel; - } - else - { - /* Rising edge interrupt */ - *enable = kPINT_PinIntEnableRiseEdge; - } - } - - if ((base->IENF & mask) != 0U) - { - if (level) - { - /* Level interrupt is active high */ - *enable = kPINT_PinIntEnableHighLevel; - } - else - { - /* Either falling or both edge */ - if (*enable == kPINT_PinIntEnableRiseEdge) - { - /* Rising and faling edge */ - *enable = kPINT_PinIntEnableBothEdges; - } - else - { - /* Falling edge */ - *enable = kPINT_PinIntEnableFallEdge; - } - } - } - - /* Security PINT uses additional callback array */ - if (base == PINT) - { - *callback = s_pintCallback[pintr]; - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - *callback = s_secpintCallback[pintr]; -#endif - } -} - -/*! - * brief Configure PINT pattern match. - - * This function configures a given pattern match bit slice. - * - * param base Base address of the PINT peripheral. - * param bslice Pattern match bit slice number. - * param cfg Pointer to bit slice configuration. - * - * retval None. - */ -void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) -{ - uint32_t src_shift; - uint32_t cfg_shift; - uint32_t pmcfg; - uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; - uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; - - assert(base != NULL); - - src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); - cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); - - /* Input source selection for selected bit slice */ - base->PMSRC = (base->PMSRC & ~(tmp_src_shift << src_shift)) | ((uint32_t)(cfg->bs_src) << src_shift); - - /* Bit slice configuration */ - pmcfg = base->PMCFG; - pmcfg = (pmcfg & ~(tmp_cfg_shift << cfg_shift)) | ((uint32_t)(cfg->bs_cfg) << cfg_shift); - - /* If end point is true, enable the bits */ - if ((uint32_t)bslice != 7UL) - { - if (cfg->end_point) - { - pmcfg |= (1UL << (uint32_t)bslice); - } - else - { - pmcfg &= ~(1UL << (uint32_t)bslice); - } - } - - base->PMCFG = pmcfg; - - /* Save callback pointer */ - if (base == PINT) - { - if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) - { - s_pintCallback[bslice] = cfg->callback; - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - { - s_secpintCallback[bslice] = cfg->callback; - } -#endif - } -} - -/*! - * brief Get PINT pattern match configuration. - - * This function returns the configuration of a given pattern match bit slice. - * - * param base Base address of the PINT peripheral. - * param bslice Pattern match bit slice number. - * param cfg Pointer to bit slice configuration. - * - * retval None. - */ -void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) -{ - uint32_t src_shift; - uint32_t cfg_shift; - uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; - uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; - - assert(base != NULL); - - src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); - cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); - - cfg->bs_src = (pint_pmatch_input_src_t)(uint32_t)((base->PMSRC & (tmp_src_shift << src_shift)) >> src_shift); - cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)(uint32_t)((base->PMCFG & (tmp_cfg_shift << cfg_shift)) >> cfg_shift); - - if ((uint32_t)bslice == 7U) - { - cfg->end_point = true; - } - else - { - cfg->end_point = (((base->PMCFG & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice) != 0U) ? true : false; - } - - if (base == PINT) - { - if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) - { - cfg->callback = s_pintCallback[bslice]; - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - { - cfg->callback = s_secpintCallback[bslice]; - } -#endif - } -} - -/*! - * brief Reset pattern match detection logic. - - * This function resets the pattern match detection logic if any of the product term is matching. - * - * param base Base address of the PINT peripheral. - * - * retval pmstatus Each bit position indicates the match status of corresponding bit slice. - * = 0 Match was detected. = 1 Match was not detected. - */ -uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base) -{ - uint32_t pmctrl; - uint32_t pmstatus; - uint32_t pmsrc; - - pmctrl = base->PMCTRL; - pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT; - if (pmstatus != 0UL) - { - /* Reset Pattern match engine detection logic */ - pmsrc = base->PMSRC; - base->PMSRC = pmsrc; - } - return (pmstatus); -} - -/*! - * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. - - * This function clears the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr) -{ - uint32_t pinIntMode = base->ISEL & (1UL << (uint32_t)pintr); - uint32_t pinIntStatus = base->IST & (1UL << (uint32_t)pintr); - - /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ - if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) - { - base->IST = (1UL << (uint32_t)pintr); - } -} - -/*! - * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. - - * This function clears the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_PinInterruptClrStatusAll(PINT_Type *base) -{ - uint32_t pinIntMode = 0; - uint32_t pinIntStatus = 0; - uint32_t pinIntCount = 0; - uint32_t mask = 0; - uint32_t i; - - if (base == PINT) - { - pinIntCount = (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - pinIntCount = (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - - for (i = 0; i < pinIntCount; i++) - { - pinIntMode = base->ISEL & (1UL << i); - pinIntStatus = base->IST & (1UL << i); - - /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ - if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) - { - mask |= 1UL << i; - } - } - - base->IST = mask; -} - -/*! - * brief Enable callback. - - * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * param base Base address of the PINT peripheral. - * - * retval None. - */ -void PINT_EnableCallback(PINT_Type *base) -{ - uint32_t i; - - assert(base != NULL); - - if (base == PINT) - { - for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i]); - (void)EnableIRQ(s_pintIRQ[i]); - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - (void)EnableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } -} - -/*! - * brief enable callback by pin index. - - * This function enables callback by pin index instead of enabling all pins. - * - * param base Base address of the peripheral. - * param pinIdx pin index. - * - * retval None. - */ -void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) -{ - assert(base != NULL); - - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); - -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - /* Get the right security pint irq index in array */ - if (base == SECPINT) - { - pintIdx = - (pint_pin_int_t)(uint32_t)((uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS); - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - - NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); - (void)EnableIRQ(s_pintIRQ[pintIdx]); -} - -/*! - * brief Disable callback. - - * This function disables the interrupt for the selected PINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * param base Base address of the peripheral. - * - * retval None. - */ -void PINT_DisableCallback(PINT_Type *base) -{ - uint32_t i; - - assert(base != NULL); - - if (base == PINT) - { - for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - (void)DisableIRQ(s_pintIRQ[i]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i]); - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - (void)DisableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } -} - -/*! - * brief disable callback by pin index. - - * This function disables callback by pin index instead of disabling all pins. - * - * param base Base address of the peripheral. - * param pinIdx pin index. - * - * retval None. - */ -void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) -{ - assert(base != NULL); - - if (base == PINT) - { - (void)DisableIRQ(s_pintIRQ[pintIdx]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); - NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - (void)DisableIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); - NVIC_ClearPendingIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); -#endif - } -} - -/*! - * brief Deinitialize PINT peripheral. - - * This function disables the PINT clock. - * - * param base Base address of the PINT peripheral. - * - * retval None. - */ -void PINT_Deinit(PINT_Type *base) -{ - uint32_t i; - - assert(base != NULL); - - /* Cleanup */ - PINT_DisableCallback(base); - if (base == PINT) - { - /* clear PINT callback array*/ - for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_pintCallback[i] = NULL; - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - /* clear SECPINT callback array */ - for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_secpintCallback[i] = NULL; - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - -#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_GpioInt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) - - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio_Sec); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - -#else - - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Pint); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } - else - { - /* if need config SECURE PINT device,then enable secure pint interrupt clock */ -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio_Sec_Int); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } -#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ -} -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -/* IRQ handler functions overloading weak symbols in the startup */ -void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void); -void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void) -{ - uint32_t pmstatus = 0; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); - /* Call user function */ - if (s_secpintCallback[kPINT_SecPinInt0] != NULL) - { - s_secpintCallback[kPINT_SecPinInt0](kPINT_SecPinInt0, pmstatus); - } - if ((SECPINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt0); - } - SDK_ISR_EXIT_BARRIER; -} - -#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) -/* IRQ handler functions overloading weak symbols in the startup */ -void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void); -void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); - /* Call user function */ - if (s_secpintCallback[kPINT_SecPinInt1] != NULL) - { - s_secpintCallback[kPINT_SecPinInt1](kPINT_SecPinInt1, pmstatus); - } - if ((SECPINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt1); - } - SDK_ISR_EXIT_BARRIER; -} -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - -/* IRQ handler functions overloading weak symbols in the startup */ -void PIN_INT0_DriverIRQHandler(void); -void PIN_INT0_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt0] != NULL) - { - s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus); - } - if ((PINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); - } - SDK_ISR_EXIT_BARRIER; -} - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) -void PIN_INT1_DriverIRQHandler(void); -void PIN_INT1_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt1] != NULL) - { - s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus); - } - if ((PINT->ISEL & 0x2U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) -void PIN_INT2_DriverIRQHandler(void); -void PIN_INT2_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt2] != NULL) - { - s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus); - } - if ((PINT->ISEL & 0x4U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) -void PIN_INT3_DriverIRQHandler(void); -void PIN_INT3_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt3] != NULL) - { - s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus); - } - if ((PINT->ISEL & 0x8U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) -void PIN_INT4_DriverIRQHandler(void); -void PIN_INT4_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt4] != NULL) - { - s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus); - } - if ((PINT->ISEL & 0x10U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT5_DAC1_IRQHandler(void); -void PIN_INT5_DAC1_IRQHandler(void) -#else -void PIN_INT5_DriverIRQHandler(void); -void PIN_INT5_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt5] != NULL) - { - s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus); - } - if ((PINT->ISEL & 0x20U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT6_USART3_IRQHandler(void); -void PIN_INT6_USART3_IRQHandler(void) -#else -void PIN_INT6_DriverIRQHandler(void); -void PIN_INT6_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt6] != NULL) - { - s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus); - } - if ((PINT->ISEL & 0x40U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT7_USART4_IRQHandler(void); -void PIN_INT7_USART4_IRQHandler(void) -#else -void PIN_INT7_DriverIRQHandler(void); -void PIN_INT7_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt7] != NULL) - { - s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus); - } - if ((PINT->ISEL & 0x80U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7); - } - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_pint.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_pint.h deleted file mode 100644 index 85be865571b..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_pint.h +++ /dev/null @@ -1,581 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_PINT_H_ -#define _FSL_PINT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup pint_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 1, 9)) /*!< Version 2.1.9 */ -/*@}*/ - -/* Number of interrupt line supported by PINT */ -#define PINT_PIN_INT_COUNT 8U - -/* Number of interrupt line supported by SECURE PINT */ -#define SEC_PINT_PIN_INT_COUNT 2U - -/* Number of input sources supported by PINT */ -#define PINT_INPUT_COUNT 8U - -/* PININT Bit slice source register bits */ -#define PININT_BITSLICE_SRC_START 8U -#define PININT_BITSLICE_SRC_MASK 7U - -/* PININT Bit slice configuration register bits */ -#define PININT_BITSLICE_CFG_START 8U -#define PININT_BITSLICE_CFG_MASK 7U -#define PININT_BITSLICE_ENDP_MASK 7U - -#define PINT_PIN_INT_LEVEL 0x10U -#define PINT_PIN_INT_EDGE 0x00U -#define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U -#define PINT_PIN_INT_RISE 0x01U -#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE) -#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) -#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) -#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL) -#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) - -/*! @brief PINT Pin Interrupt enable type */ -typedef enum _pint_pin_enable -{ - kPINT_PinIntEnableNone = 0U, /*!< Do not generate Pin Interrupt */ - kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE, /*!< Generate Pin Interrupt on rising edge */ - kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE, /*!< Generate Pin Interrupt on falling edge */ - kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */ - kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL, /*!< Generate Pin Interrupt on low level */ - kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */ -} pint_pin_enable_t; - -/*! @brief PINT Pin Interrupt type */ -typedef enum _pint_int -{ - kPINT_PinInt0 = 0U, /*!< Pin Interrupt 0 */ -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_PinInt1 = 1U, /*!< Pin Interrupt 1 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) - kPINT_PinInt2 = 2U, /*!< Pin Interrupt 2 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) - kPINT_PinInt3 = 3U, /*!< Pin Interrupt 3 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) - kPINT_PinInt4 = 4U, /*!< Pin Interrupt 4 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) - kPINT_PinInt5 = 5U, /*!< Pin Interrupt 5 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) - kPINT_PinInt6 = 6U, /*!< Pin Interrupt 6 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) - kPINT_PinInt7 = 7U, /*!< Pin Interrupt 7 */ -#endif -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) - kPINT_SecPinInt0 = 0U, /*!< Secure Pin Interrupt 0 */ -#endif -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_SecPinInt1 = 1U, /*!< Secure Pin Interrupt 1 */ -#endif -} pint_pin_int_t; - -/*! @brief PINT Pattern Match bit slice input source type */ -typedef enum _pint_pmatch_input_src -{ - kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */ - kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */ - kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */ - kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */ - kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */ - kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */ - kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */ - kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */ - kPINT_SecPatternMatchInp0Src = 0U, /*!< Input source 0 */ - kPINT_SecPatternMatchInp1Src = 1U, /*!< Input source 1 */ -} pint_pmatch_input_src_t; - -/*! @brief PINT Pattern Match bit slice type */ -typedef enum _pint_pmatch_bslice -{ - kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) - kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) - kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) - kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) - kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) - kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) - kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */ -#endif -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) - kPINT_SecPatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ -#endif -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_SecPatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ -#endif -} pint_pmatch_bslice_t; - -/*! @brief PINT Pattern Match configuration type */ -typedef enum _pint_pmatch_bslice_cfg -{ - kPINT_PatternMatchAlways = 0U, /*!< Always Contributes to product term match */ - kPINT_PatternMatchStickyRise = 1U, /*!< Sticky Rising edge */ - kPINT_PatternMatchStickyFall = 2U, /*!< Sticky Falling edge */ - kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */ - kPINT_PatternMatchHigh = 4U, /*!< High level */ - kPINT_PatternMatchLow = 5U, /*!< Low level */ - kPINT_PatternMatchNever = 6U, /*!< Never contributes to product term match */ - kPINT_PatternMatchBothEdges = 7U, /*!< Either rising or falling edge */ -} pint_pmatch_bslice_cfg_t; - -/*! @brief PINT Callback function. */ -typedef void (*pint_cb_t)(pint_pin_int_t pintr, uint32_t pmatch_status); - -typedef struct _pint_pmatch_cfg -{ - pint_pmatch_input_src_t bs_src; - pint_pmatch_bslice_cfg_t bs_cfg; - bool end_point; - pint_cb_t callback; -} pint_pmatch_cfg_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize PINT peripheral. - - * This function initializes the PINT peripheral and enables the clock. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_Init(PINT_Type *base); - -/*! - * @brief Configure PINT peripheral pin interrupt. - - * This function configures a given pin interrupt. - * - * @param base Base address of the PINT peripheral. - * @param intr Pin interrupt. - * @param enable Selects detection logic. - * @param callback Callback. - * - * @retval None. - */ -void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback); - -/*! - * @brief Get PINT peripheral pin interrupt configuration. - - * This function returns the configuration of a given pin interrupt. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * @param enable Pointer to store the detection logic. - * @param callback Callback. - * - * @retval None. - */ -void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback); - -/*! - * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. - - * This function clears the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr); - -/*! - * @brief Get Selected pin interrupt status. - - * This function returns the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval status = 0 No pin interrupt request. = 1 Selected Pin interrupt request active. - */ -static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->IST & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. - - * This function clears the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_PinInterruptClrStatusAll(PINT_Type *base); - -/*! - * @brief Get all pin interrupts status. - - * This function returns the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval status Each bit position indicates the status of corresponding pin interrupt. - * = 0 No pin interrupt request. = 1 Pin interrupt request active. - */ -static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base) -{ - return (base->IST); -} - -/*! - * @brief Clear Selected pin interrupt fall flag. - - * This function clears the selected pin interrupt fall flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - base->FALL = (1UL << (uint32_t)pintr); -} - -/*! - * @brief Get selected pin interrupt fall flag. - - * This function returns the selected pin interrupt fall flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval flag = 0 Falling edge has not been detected. = 1 Falling edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->FALL & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupt fall flags. - - * This function clears the fall flag for all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base) -{ - base->FALL = PINT_FALL_FDET_MASK; -} - -/*! - * @brief Get all pin interrupt fall flags. - - * This function returns the fall flag of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval flags Each bit position indicates the falling edge detection of the corresponding pin interrupt. - * 0 Falling edge has not been detected. = 1 Falling edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base) -{ - return (base->FALL); -} - -/*! - * @brief Clear Selected pin interrupt rise flag. - - * This function clears the selected pin interrupt rise flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - base->RISE = (1UL << (uint32_t)pintr); -} - -/*! - * @brief Get selected pin interrupt rise flag. - - * This function returns the selected pin interrupt rise flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval flag = 0 Rising edge has not been detected. = 1 Rising edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->RISE & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupt rise flags. - - * This function clears the rise flag for all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base) -{ - base->RISE = PINT_RISE_RDET_MASK; -} - -/*! - * @brief Get all pin interrupt rise flags. - - * This function returns the rise flag of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval flags Each bit position indicates the rising edge detection of the corresponding pin interrupt. - * 0 Rising edge has not been detected. = 1 Rising edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base) -{ - return (base->RISE); -} - -/*! - * @brief Configure PINT pattern match. - - * This function configures a given pattern match bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * @param cfg Pointer to bit slice configuration. - * - * @retval None. - */ -void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); - -/*! - * @brief Get PINT pattern match configuration. - - * This function returns the configuration of a given pattern match bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * @param cfg Pointer to bit slice configuration. - * - * @retval None. - */ -void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); - -/*! - * @brief Get pattern match bit slice status. - - * This function returns the status of selected bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * - * @retval status = 0 Match has not been detected. = 1 Match has been detected. - */ -static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_bslice_t bslice) -{ - return ((base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT) & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice; -} - -/*! - * @brief Get status of all pattern match bit slices. - - * This function returns the status of all bit slices. - * - * @param base Base address of the PINT peripheral. - * - * @retval status Each bit position indicates the match status of corresponding bit slice. - * = 0 Match has not been detected. = 1 Match has been detected. - */ -static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base) -{ - return base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT; -} - -/*! - * @brief Reset pattern match detection logic. - - * This function resets the pattern match detection logic if any of the product term is matching. - * - * @param base Base address of the PINT peripheral. - * - * @retval pmstatus Each bit position indicates the match status of corresponding bit slice. - * = 0 Match was detected. = 1 Match was not detected. - */ -uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base); - -/*! - * @brief Enable pattern match function. - - * This function enables the pattern match function. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchEnable(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) | PINT_PMCTRL_SEL_PMATCH_MASK; -} - -/*! - * @brief Disable pattern match function. - - * This function disables the pattern match function. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchDisable(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) & ~PINT_PMCTRL_SEL_PMATCH_MASK; -} - -/*! - * @brief Enable RXEV output. - - * This function enables the pattern match RXEV output. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) | PINT_PMCTRL_ENA_RXEV_MASK; -} - -/*! - * @brief Disable RXEV output. - - * This function disables the pattern match RXEV output. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) & ~PINT_PMCTRL_ENA_RXEV_MASK; -} - -/*! - * @brief Enable callback. - - * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_EnableCallback(PINT_Type *base); - -/*! - * @brief Disable callback. - - * This function disables the interrupt for the selected PINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * @param base Base address of the peripheral. - * - * @retval None. - */ -void PINT_DisableCallback(PINT_Type *base); - -/*! - * @brief Deinitialize PINT peripheral. - - * This function disables the PINT clock. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_Deinit(PINT_Type *base); - -/*! - * @brief enable callback by pin index. - - * This function enables callback by pin index instead of enabling all pins. - * - * @param base Base address of the peripheral. - * @param pintIdx pin index. - * - * @retval None. - */ -void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); - -/*! - * @brief disable callback by pin index. - - * This function disables callback by pin index instead of disabling all pins. - * - * @param base Base address of the peripheral. - * @param pintIdx pin index. - * - * @retval None. - */ -void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_PINT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_plu.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_plu.c deleted file mode 100644 index b50f472675e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_plu.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_plu.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.plu" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Gets the instance from the base address - * - * @param base PLU peripheral base address - * - * @return The PLU instance - */ -static uint32_t PLU_GetInstance(PLU_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to PLU bases for each instance. */ -static PLU_Type *const s_pluBases[] = PLU_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to PLU clocks for each instance. */ -static const clock_ip_name_t s_pluClocks[] = PLU_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -/*! @brief Pointers to PLU resets for each instance. */ -static const reset_ip_name_t s_lpuResets[] = PLU_RSTS_N; -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t PLU_GetInstance(PLU_Type *base) -{ - uint32_t instance; - uint32_t pluArrayCount = (sizeof(s_pluBases) / sizeof(s_pluBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < pluArrayCount; instance++) - { - if (s_pluBases[instance] == base) - { - break; - } - } - - assert(instance < pluArrayCount); - - return instance; -} - -/*! - * brief Ungates the PLU clock and reset the module. - * - * note This API should be called at the beginning of the application using the PLU driver. - * - * param base PLU peripheral base address - */ -void PLU_Init(PLU_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the PLU peripheral clock */ - CLOCK_EnableClock(s_pluClocks[PLU_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_lpuResets[PLU_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -} - -/*! - * brief Gate the PLU clock - * - * param base PLU peripheral base address - */ -void PLU_Deinit(PLU_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the module clock */ - CLOCK_DisableClock((s_pluClocks[PLU_GetInstance(base)])); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -#if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG -/*! - * @brief Gets an available pre-defined settings for wakeup/interrupt control. - * - * This function initializes the initial configuration structure with an available settings. The default values are: - * @code - * config->filterMode = kPLU_WAKEINT_FILTER_MODE_BYPASS; - * config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC; - * @endcode - * @param config Pointer to configuration structure. - */ -void PLU_GetDefaultWakeIntConfig(plu_wakeint_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->filterMode = kPLU_WAKEINT_FILTER_MODE_BYPASS; - config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC; -} - -/*! - * @brief Enable PLU outputs wakeup/interrupt request. - * - * This function enables Any of the eight selected PLU outputs to contribute to an asynchronous wake-up or an interrupt - * request. - * - * Note: If a PLU_CLKIN is provided, the raw wake-up/interrupt request will be set on the rising-edge of the PLU_CLKIN - * whenever the raw request signal is high. This registered signal will be glitch-free and just use the default wakeint - * config by PLU_GetDefaultWakeIntConfig(). If not, have to specify the filter mode and clock source to eliminate the - * glitches caused by long and widely disparate delays through the network of LUTs making up the PLU. This way may - * increase power consumption in low-power operating modes and inject delay before the wake-up/interrupt request is - * generated. - * - * @param base PLU peripheral base address. - * @param interruptMask PLU interrupt mask (see @ref _plu_interrupt_mask enumeration). - * @param config Pointer to configuration structure (see @ref plu_wakeint_config_t typedef enumeration) - */ -void PLU_EnableWakeIntRequest(PLU_Type *base, uint32_t interruptMask, const plu_wakeint_config_t *config) -{ - uint32_t tmp32 = 0U; - - tmp32 = PLU_WAKEINT_CTRL_FILTER_MODE(config->filterMode) | PLU_WAKEINT_CTRL_FILTER_CLKSEL(config->clockSource) | - PLU_WAKEINT_CTRL_MASK(interruptMask); - - base->WAKEINT_CTRL = tmp32; -} - -/*! - * @brief Clear the latched interrupt - * - * This function clears the wake-up/interrupt request flag latched by PLU_LatchInterrupt() - * - * Note: It is not necessary for the PLU bus clock to be enabled in order to write-to or read-back this bit. - * - * @param base PLU peripheral base address. - */ -void PLU_ClearLatchedInterrupt(PLU_Type *base) -{ - base->WAKEINT_CTRL |= PLU_WAKEINT_CTRL_INTR_CLEAR_MASK; - /* It will take a delay of up to 1.5 PLU_CLKIN clock cycles before this write-to-clear takes effect. */ - while (PLU_WAKEINT_CTRL_INTR_CLEAR_MASK == (base->WAKEINT_CTRL & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK)) - { - } -} -#endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_plu.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_plu.h deleted file mode 100644 index 0c94d49091d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_plu.h +++ /dev/null @@ -1,374 +0,0 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_PLU_H_ -#define _FSL_PLU_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup plu - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_PLU_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1 */ - /*@}*/ - -/*! @brief Index of LUT */ -typedef enum _plu_lut_index -{ - kPLU_LUT_0 = 0U, /*!< 5-input Look-up Table 0 */ - kPLU_LUT_1 = 1U, /*!< 5-input Look-up Table 1 */ - kPLU_LUT_2 = 2U, /*!< 5-input Look-up Table 2 */ - kPLU_LUT_3 = 3U, /*!< 5-input Look-up Table 3 */ - kPLU_LUT_4 = 4U, /*!< 5-input Look-up Table 4 */ - kPLU_LUT_5 = 5U, /*!< 5-input Look-up Table 5 */ - kPLU_LUT_6 = 6U, /*!< 5-input Look-up Table 6 */ - kPLU_LUT_7 = 7U, /*!< 5-input Look-up Table 7 */ - kPLU_LUT_8 = 8U, /*!< 5-input Look-up Table 8 */ - kPLU_LUT_9 = 9U, /*!< 5-input Look-up Table 9 */ - kPLU_LUT_10 = 10U, /*!< 5-input Look-up Table 10 */ - kPLU_LUT_11 = 11U, /*!< 5-input Look-up Table 11 */ - kPLU_LUT_12 = 12U, /*!< 5-input Look-up Table 12 */ - kPLU_LUT_13 = 13U, /*!< 5-input Look-up Table 13 */ - kPLU_LUT_14 = 14U, /*!< 5-input Look-up Table 14 */ - kPLU_LUT_15 = 15U, /*!< 5-input Look-up Table 15 */ - kPLU_LUT_16 = 16U, /*!< 5-input Look-up Table 16 */ - kPLU_LUT_17 = 17U, /*!< 5-input Look-up Table 17 */ - kPLU_LUT_18 = 18U, /*!< 5-input Look-up Table 18 */ - kPLU_LUT_19 = 19U, /*!< 5-input Look-up Table 19 */ - kPLU_LUT_20 = 20U, /*!< 5-input Look-up Table 20 */ - kPLU_LUT_21 = 21U, /*!< 5-input Look-up Table 21 */ - kPLU_LUT_22 = 22U, /*!< 5-input Look-up Table 22 */ - kPLU_LUT_23 = 23U, /*!< 5-input Look-up Table 23 */ - kPLU_LUT_24 = 24U, /*!< 5-input Look-up Table 24 */ - kPLU_LUT_25 = 25U /*!< 5-input Look-up Table 25 */ -} plu_lut_index_t; - -/*! @brief Inputs of LUT. 5 input present for each LUT. */ -typedef enum _plu_lut_in_index -{ - kPLU_LUT_IN_0 = 0U, /*!< LUT input 0 */ - kPLU_LUT_IN_1 = 1U, /*!< LUT input 1 */ - kPLU_LUT_IN_2 = 2U, /*!< LUT input 2 */ - kPLU_LUT_IN_3 = 3U, /*!< LUT input 3 */ - kPLU_LUT_IN_4 = 4U /*!< LUT input 4 */ -} plu_lut_in_index_t; - -/*! @brief Available sources of LUT input */ -typedef enum _plu_lut_input_source -{ - kPLU_LUT_IN_SRC_PLU_IN_0 = 0U, /*!< Select PLU input 0 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_1 = 1U, /*!< Select PLU input 1 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_2 = 2U, /*!< Select PLU input 2 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_3 = 3U, /*!< Select PLU input 3 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_4 = 4U, /*!< Select PLU input 4 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_5 = 5U, /*!< Select PLU input 5 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_0 = 6U, /*!< Select LUT output 0 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_1 = 7U, /*!< Select LUT output 1 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_2 = 8U, /*!< Select LUT output 2 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_3 = 9U, /*!< Select LUT output 3 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_4 = 10U, /*!< Select LUT output 4 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_5 = 11U, /*!< Select LUT output 5 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_6 = 12U, /*!< Select LUT output 6 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_7 = 13U, /*!< Select LUT output 7 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_8 = 14U, /*!< Select LUT output 8 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_9 = 15U, /*!< Select LUT output 9 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_10 = 16U, /*!< Select LUT output 10 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_11 = 17U, /*!< Select LUT output 11 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_12 = 18U, /*!< Select LUT output 12 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_13 = 19U, /*!< Select LUT output 13 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_14 = 20U, /*!< Select LUT output 14 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_15 = 21U, /*!< Select LUT output 15 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_16 = 22U, /*!< Select LUT output 16 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_17 = 23U, /*!< Select LUT output 17 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_18 = 24U, /*!< Select LUT output 18 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_19 = 25U, /*!< Select LUT output 19 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_20 = 26U, /*!< Select LUT output 20 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_21 = 27U, /*!< Select LUT output 21 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_22 = 28U, /*!< Select LUT output 22 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_23 = 29U, /*!< Select LUT output 23 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_24 = 30U, /*!< Select LUT output 24 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_25 = 31U, /*!< Select LUT output 25 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_FLIPFLOP_0 = 32U, /*!< Select Flip-Flops state 0 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_FLIPFLOP_1 = 33U, /*!< Select Flip-Flops state 1 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_FLIPFLOP_2 = 34U, /*!< Select Flip-Flops state 2 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_FLIPFLOP_3 = 35U /*!< Select Flip-Flops state 3 to be connected to LUTn Input x */ -} plu_lut_input_source_t; - -/*! @brief PLU output multiplexer registers */ -typedef enum _plu_output_index -{ - kPLU_OUTPUT_0 = 0U, /*!< PLU OUTPUT 0 */ - kPLU_OUTPUT_1 = 1U, /*!< PLU OUTPUT 1 */ - kPLU_OUTPUT_2 = 2U, /*!< PLU OUTPUT 2 */ - kPLU_OUTPUT_3 = 3U, /*!< PLU OUTPUT 3 */ - kPLU_OUTPUT_4 = 4U, /*!< PLU OUTPUT 4 */ - kPLU_OUTPUT_5 = 5U, /*!< PLU OUTPUT 5 */ - kPLU_OUTPUT_6 = 6U, /*!< PLU OUTPUT 6 */ - kPLU_OUTPUT_7 = 7U /*!< PLU OUTPUT 7 */ -} plu_output_index_t; - -/*! @brief Available sources of PLU output */ -typedef enum _plu_output_source -{ - kPLU_OUT_SRC_LUT_0 = 0U, /*!< Select LUT0 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_1 = 1U, /*!< Select LUT1 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_2 = 2U, /*!< Select LUT2 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_3 = 3U, /*!< Select LUT3 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_4 = 4U, /*!< Select LUT4 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_5 = 5U, /*!< Select LUT5 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_6 = 6U, /*!< Select LUT6 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_7 = 7U, /*!< Select LUT7 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_8 = 8U, /*!< Select LUT8 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_9 = 9U, /*!< Select LUT9 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_10 = 10U, /*!< Select LUT10 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_11 = 11U, /*!< Select LUT11 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_12 = 12U, /*!< Select LUT12 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_13 = 13U, /*!< Select LUT13 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_14 = 14U, /*!< Select LUT14 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_15 = 15U, /*!< Select LUT15 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_16 = 16U, /*!< Select LUT16 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_17 = 17U, /*!< Select LUT17 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_18 = 18U, /*!< Select LUT18 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_19 = 19U, /*!< Select LUT19 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_20 = 20U, /*!< Select LUT20 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_21 = 21U, /*!< Select LUT21 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_22 = 22U, /*!< Select LUT22 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_23 = 23U, /*!< Select LUT23 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_24 = 24U, /*!< Select LUT24 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_25 = 25U, /*!< Select LUT25 output to be connected to PLU output */ - kPLU_OUT_SRC_FLIPFLOP_0 = 26U, /*!< Select Flip-Flops state(0) to be connected to PLU output */ - kPLU_OUT_SRC_FLIPFLOP_1 = 27U, /*!< Select Flip-Flops state(1) to be connected to PLU output */ - kPLU_OUT_SRC_FLIPFLOP_2 = 28U, /*!< Select Flip-Flops state(2) to be connected to PLU output */ - kPLU_OUT_SRC_FLIPFLOP_3 = 29U /*!< Select Flip-Flops state(3) to be connected to PLU output */ -} plu_output_source_t; - -#if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG - -/*! @brief The enumerator of PLU Interrupt. */ -enum _plu_interrupt_mask -{ - kPLU_OUTPUT_0_INTERRUPT_MASK = 1 << 0, /*!< Select PLU output 0 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_1_INTERRUPT_MASK = 1 << 1, /*!< Select PLU output 1 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_2_INTERRUPT_MASK = 1 << 2, /*!< Select PLU output 2 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_3_INTERRUPT_MASK = 1 << 3, /*!< Select PLU output 3 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_4_INTERRUPT_MASK = 1 << 4, /*!< Select PLU output 4 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_5_INTERRUPT_MASK = 1 << 5, /*!< Select PLU output 5 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_6_INTERRUPT_MASK = 1 << 6, /*!< Select PLU output 6 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_7_INTERRUPT_MASK = 1 << 7 /*!< Select PLU output 7 contribute to interrupt/wake-up generation */ -}; - -/*! @brief Control input of the PLU, add filtering for glitch. */ -typedef enum _plu_wakeint_filter_mode -{ - kPLU_WAKEINT_FILTER_MODE_BYPASS = 0U, /*!< Select Bypass mode */ - kPLU_WAKEINT_FILTER_MODE_1_CLK_PERIOD = 1U, /*!< Filter 1 clock period */ - kPLU_WAKEINT_FILTER_MODE_2_CLK_PERIOD = 2U, /*!< Filter 2 clock period */ - kPLU_WAKEINT_FILTER_MODE_3_CLK_PERIOD = 3U /*!< Filter 3 clock period */ -} plu_wakeint_filter_mode_t; - -/*! @brief Clock source for filter mode. */ -typedef enum _plu_wakeint_filter_clock_source -{ - kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC = 0U, /*!< Select the 1MHz low-power oscillator as the filter clock */ - kPLU_WAKEINT_FILTER_CLK_SRC_12MHZ_FRO = 1U, /*!< Select the 12MHz FRO as the filer clock */ - kPLU_WAKEINT_FILTER_CLK_SRC_ALT = 2U /*!< Select a third clock source */ -} plu_wakeint_filter_clock_source_t; - -/*! @brief Wake configuration. */ -typedef struct _plu_wakeint_config -{ - plu_wakeint_filter_mode_t filterMode; /*!< Filter Mode. */ - plu_wakeint_filter_clock_source_t clockSource; /*!< The clock source for filter mode. */ -} plu_wakeint_config_t; -#endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Enable the PLU clock and reset the module. - * - * @note This API should be called at the beginning of the application using the PLU driver. - * - * @param base PLU peripheral base address - */ -void PLU_Init(PLU_Type *base); - -/*! - * @brief Gate the PLU clock - * - * @param base PLU peripheral base address - */ -void PLU_Deinit(PLU_Type *base); - -/*! @}*/ - -/*! - * @name Set input/output source and Truth Table - * @{ - */ - -/*! - * @brief Set Input source of LUT. - * - * Note: An external clock must be applied to the PLU_CLKIN input when using FFs. - * For each LUT, the slot associated with the output from LUTn itself is tied low. - * - * @param base PLU peripheral base address. - * @param lutIndex LUT index (see @ref plu_lut_index_t typedef enumeration). - * @param lutInIndex LUT input index (see @ref plu_lut_in_index_t typedef enumeration). - * @param inputSrc LUT input source (see @ref plu_lut_input_source_t typedef enumeration). - */ -static inline void PLU_SetLutInputSource(PLU_Type *base, - plu_lut_index_t lutIndex, - plu_lut_in_index_t lutInIndex, - plu_lut_input_source_t inputSrc) -{ - PLU->LUT[lutIndex].INP_MUX[lutInIndex] = (uint32_t)inputSrc; -} - -/*! - * @brief Set Output source of PLU. - * - * Note: An external clock must be applied to the PLU_CLKIN input when using FFs. - * - * @param base PLU peripheral base address. - * @param outputIndex PLU output index (see @ref plu_output_index_t typedef enumeration). - * @param outputSrc PLU output source (see @ref plu_output_source_t typedef enumeration). - */ -static inline void PLU_SetOutputSource(PLU_Type *base, plu_output_index_t outputIndex, plu_output_source_t outputSrc) -{ - base->OUTPUT_MUX[outputIndex] = (uint32_t)outputSrc; -} - -/*! - * @brief Set Truth Table of LUT. - * - * @param base PLU peripheral base address. - * @param lutIndex LUT index (see @ref plu_lut_index_t typedef enumeration). - * @param truthTable Truth Table value. - */ -static inline void PLU_SetLutTruthTable(PLU_Type *base, plu_lut_index_t lutIndex, uint32_t truthTable) -{ - base->LUT_TRUTH[lutIndex] = truthTable; -} - -/*! @}*/ - -/*! - * @name Read current Output State - * @{ - */ - -/*! - * @brief Read the current state of the 8 designated PLU Outputs. - * - * Note: The PLU bus clock must be re-enabled prior to reading the Outpus Register if PLU bus clock is - * shut-off. - * - * @param base PLU peripheral base address. - * @return Current PLU output state value. - */ -static inline uint32_t PLU_ReadOutputState(PLU_Type *base) -{ - return (base->OUTPUTS & PLU_OUTPUTS_OUTPUT_STATE_MASK); -} - -/*! @}*/ - -#if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG -/*! - * @name Wake-up/Interrupt Control - * @{ - */ - -/*! - * @brief Gets an available pre-defined settings for wakeup/interrupt control. - * - * This function initializes the initial configuration structure with an available settings. The default values are: - * @code - * config->filterMode = kPLU_WAKEINT_FILTER_MODE_BYPASS; - * config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC; - * @endcode - * @param config Pointer to configuration structure. - */ -void PLU_GetDefaultWakeIntConfig(plu_wakeint_config_t *config); - -/*! - * @brief Enable PLU outputs wakeup/interrupt request. - * - * This function enables Any of the eight selected PLU outputs to contribute to an asynchronous wake-up or an interrupt - * request. - * - * Note: If a PLU_CLKIN is provided, the raw wake-up/interrupt request will be set on the rising-edge of the PLU_CLKIN - * whenever the raw request signal is high. This registered signal will be glitch-free and just use the default wakeint - * config by PLU_GetDefaultWakeIntConfig(). If not, have to specify the filter mode and clock source to eliminate the - * glitches caused by long and widely disparate delays through the network of LUTs making up the PLU. This way may - * increase power consumption in low-power operating modes and inject delay before the wake-up/interrupt request is - * generated. - * - * @param base PLU peripheral base address. - * @param interruptMask PLU interrupt mask (see @ref _plu_interrupt_mask enumeration). - * @param config Pointer to configuration structure (see @ref plu_wakeint_config_t typedef enumeration) - */ -void PLU_EnableWakeIntRequest(PLU_Type *base, uint32_t interruptMask, const plu_wakeint_config_t *config); - -/*! - * @brief Latch an interrupt - * - * This function latches the interrupt and then it can be cleared with PLU_ClearLatchedInterrupt(). - * - * Note: This mode is not compatible with use of the glitch filter. If this bit is set, the FILTER MODE should be set - * to kPLU_WAKEINT_FILTER_MODE_BYPASS (Bypass Mode) and PLU_CLKIN should be provided. If this bit is set, the - * wake-up/interrupt request will be set on the rising-edge of PLU_CLKIN whenever the raw wake-up/interrupt signal is - * high. The request must be cleared by software. - * - * @param base PLU peripheral base address. - */ -static inline void PLU_LatchInterrupt(PLU_Type *base) -{ - base->WAKEINT_CTRL |= PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK; -} - -/*! - * @brief Clear the latched interrupt - * - * This function clears the wake-up/interrupt request flag latched by PLU_LatchInterrupt() - * - * Note: It is not necessary for the PLU bus clock to be enabled in order to write-to or read-back this bit. - * - * @param base PLU peripheral base address. - */ -void PLU_ClearLatchedInterrupt(PLU_Type *base); - -/*! @}*/ -#endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_PLU_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_power.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_power.c deleted file mode 100644 index b4c02794371..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_power.c +++ /dev/null @@ -1,1985 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_common.h" -#include "fsl_power.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.power" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/** @brief Low Power main structure */ -typedef enum -{ - VD_AON = 0x0, /*!< Digital Always On power domain */ - VD_MEM = 0x1, /*!< Memories (SRAM) power domain */ - VD_DCDC = 0x2, /*!< Core logic power domain */ - VD_DEEPSLEEP = 0x3 /*!< Core logic power domain */ -} LPC_POWER_DOMAIN_T; - -/** - * @brief LDO_FLASH_NV & LDO_USB voltage settings - */ -typedef enum _v_flashnv -{ - V_LDOFLASHNV_1P650 = 0, /*!< 0.95 V */ - V_LDOFLASHNV_1P700 = 1, /*!< 0.975 V */ - V_LDOFLASHNV_1P750 = 2, /*!< 1 V */ - V_LDOFLASHNV_0P800 = 3, /*!< 1.025 V */ - V_LDOFLASHNV_1P850 = 4, /*!< 1.050 V */ - V_LDOFLASHNV_1P900 = 5, /*!< 1.075 V */ - V_LDOFLASHNV_1P950 = 6, /*!< 1.1 V */ - V_LDOFLASHNV_2P000 = 7 /*!< 1.125 V */ -} v_flashnv_t; - -/** @brief Low Power main structure */ -typedef struct -{ /* */ - __IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */ - __IO uint32_t PDCTRL0; /*!< Power Down control : controls power of various modules - in the different Low power modes, including ROM */ - __IO uint32_t SRAMRETCTRL; /*!< Power Down control : controls power SRAM instances - in the different Low power modes */ - __IO uint32_t CPURETCTRL; /*!< CPU0 retention control : controls CPU retention parameters in POWER DOWN modes */ - __IO uint64_t VOLTAGE; /*!< Voltage control in Low Power Modes */ - __IO uint64_t WAKEUPSRC; /*!< Wake up sources control for sleepcon */ - __IO uint64_t WAKEUPINT; /*!< Wake up sources control for ARM */ - __IO uint32_t HWWAKE; /*!< Interrupt that can postpone power down modes - in case an interrupt is pending when the processor request deepsleep */ - __IO uint32_t WAKEUPIOSRC; /*!< Wake up I/O sources in DEEP POWER DOWN mode */ - __IO uint32_t TIMERCFG; /*!< Wake up timers configuration */ - __IO uint32_t TIMERCOUNT; /*!< Wake up Timer count*/ - __IO uint32_t POWERCYCLE; /*!< Cancels entry in Low Power mode if set with 0xDEADABBA (might be used by some - interrupt handlers)*/ -} LPC_LOWPOWER_T; - -/* */ -#define LOWPOWER_POWERCYCLE_CANCELLED 0xDEADABBAUL /*!< */ - -/** - * @brief SRAM Low Power Modes - */ -#define LOWPOWER_SRAM_LPMODE_MASK (0xFUL) -#define LOWPOWER_SRAM_LPMODE_ACTIVE (0x6UL) /*!< SRAM functional mode */ -#define LOWPOWER_SRAM_LPMODE_SLEEP (0xFUL) /*!< SRAM Sleep mode (Data retention, fast wake up) */ -#define LOWPOWER_SRAM_LPMODE_DEEPSLEEP (0x8UL) /*!< SRAM Deep Sleep mode (Data retention, slow wake up) */ -#define LOWPOWER_SRAM_LPMODE_SHUTDOWN (0x9UL) /*!< SRAM Shut Down mode (no data retention) */ -#define LOWPOWER_SRAM_LPMODE_POWERUP (0xAUL) /*!< SRAM is powering up */ - -/** - * @brief Wake up timers configuration in Low Power Modes - */ -#define LOWPOWER_TIMERCFG_CTRL_INDEX 0 -#define LOWPOWER_TIMERCFG_CTRL_MASK (0x1UL << LOWPOWER_TIMERCFG_CTRL_INDEX) -#define LOWPOWER_TIMERCFG_TIMER_INDEX 1 -#define LOWPOWER_TIMERCFG_TIMER_MASK (0x7UL << LOWPOWER_TIMERCFG_TIMER_INDEX) -#define LOWPOWER_TIMERCFG_OSC32K_INDEX 4 -#define LOWPOWER_TIMERCFG_OSC32K_MASK (0x1UL << LOWPOWER_TIMERCFG_OSC32K_INDEX) - -#define LOWPOWER_TIMERCFG_CTRL_DISABLE 0 /*!< Wake Timer Disable */ -#define LOWPOWER_TIMERCFG_CTRL_ENABLE 1 /*!< Wake Timer Enable */ - -/** - * @brief Primary Wake up timers configuration in Low Power Modes - */ -#define LOWPOWER_TIMERCFG_TIMER_RTC1KHZ 0 /*!< 1 KHz Real Time Counter (RTC) used as wake up source */ -#define LOWPOWER_TIMERCFG_TIMER_RTC1HZ 1 /*!< 1 Hz Real Time Counter (RTC) used as wake up source */ -#define LOWPOWER_TIMERCFG_TIMER_OSTIMER 2 /*!< OS Event Timer used as wake up source */ - -#define LOWPOWER_TIMERCFG_OSC32K_FRO32KHZ 0 /*!< Wake up Timers uses FRO 32 KHz as clock source */ -#define LOWPOWER_TIMERCFG_OSC32K_XTAL32KHZ 1 /*!< Wake up Timers uses Chrystal 32 KHz as clock source */ - -//! @brief Interface for lowpower functions -typedef struct LowpowerDriverInterface -{ - void (*power_cycle_cpu_and_flash)(void); - void (*set_lowpower_mode)(LPC_LOWPOWER_T *p_lowpower_cfg); -} lowpower_driver_interface_t; - -/**< DCDC Power Profiles */ -typedef enum -{ - DCDC_POWER_PROFILE_LOW, /**< LOW (for CPU frequencies below DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ) */ - DCDC_POWER_PROFILE_MEDIUM, /**< MEDIUM (for CPU frequencies between DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ and - DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ) */ - DCDC_POWER_PROFILE_HIGH, /**< HIGH (for CPU frequencies between DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ and - DCDC_POWER_PROFILE_HIGH_MAX_FREQ_HZ) */ -} lowpower_dcdc_power_profile_enum; - -/**< Manufacturing Process Corners */ -typedef enum -{ - PROCESS_CORNER_SSS, /**< Slow Corner Process */ - PROCESS_CORNER_NNN, /**< Nominal Corner Process */ - PROCESS_CORNER_FFF, /**< Fast Corner Process */ - PROCESS_CORNER_OTHERS, /**< SFN, SNF, NFS, Poly Res ... Corner Process */ -} lowpower_process_corner_enum; - -/** - * @brief DCDC voltage settings - */ -typedef enum _v_dcdc -{ - V_DCDC_0P950 = 0, /*!< 0.95 V */ - V_DCDC_0P975 = 1, /*!< 0.975 V */ - V_DCDC_1P000 = 2, /*!< 1 V */ - V_DCDC_1P025 = 3, /*!< 1.025 V */ - V_DCDC_1P050 = 4, /*!< 1.050 V */ - V_DCDC_1P075 = 5, /*!< 1.075 V */ - V_DCDC_1P100 = 6, /*!< 1.1 V */ - V_DCDC_1P125 = 7, /*!< 1.125 V */ - V_DCDC_1P150 = 8, /*!< 1.150 V */ - V_DCDC_1P175 = 9, /*!< 1.175 V */ - V_DCDC_1P200 = 10 /*!< 1.2 V */ -} v_dcdc_t; - -/** - * @brief Deep Sleep LDO voltage settings - */ -typedef enum _v_deepsleep -{ - V_DEEPSLEEP_0P900 = 0, /*!< 0.9 V */ - V_DEEPSLEEP_0P925 = 1, /*!< 0.925 V */ - V_DEEPSLEEP_0P950 = 2, /*!< 0.95 V */ - V_DEEPSLEEP_0P975 = 3, /*!< 0.975 V */ - V_DEEPSLEEP_1P000 = 4, /*!< 1.000 V */ - V_DEEPSLEEP_1P025 = 5, /*!< 1.025 V */ - V_DEEPSLEEP_1P050 = 6, /*!< 1.050 V */ - V_DEEPSLEEP_1P075 = 7 /*!< 1.075 V */ -} v_deepsleep_t; - -/** - * @brief Always On and Memories LDO voltage settings - */ -typedef enum _v_ao -{ - V_AO_0P700 = 1, /*!< 0.7 V */ - V_AO_0P725 = 2, /*!< 0.725 V */ - V_AO_0P750 = 3, /*!< 0.75 V */ - V_AO_0P775 = 4, /*!< 0.775 V */ - V_AO_0P800 = 5, /*!< 0.8 V */ - V_AO_0P825 = 6, /*!< 0.825 V */ - V_AO_0P850 = 7, /*!< 0.85 V */ - V_AO_0P875 = 8, /*!< 0.875 V */ - V_AO_0P900 = 9, /*!< 0.9 V */ - V_AO_0P960 = 10, /*!< 0.96 V */ - V_AO_0P970 = 11, /*!< 0.97 V */ - V_AO_0P980 = 12, /*!< 0.98 V */ - V_AO_0P990 = 13, /*!< 0.99 V */ - V_AO_1P000 = 14, /*!< 1 V */ - V_AO_1P010 = 15, /*!< 1.01 V */ - V_AO_1P020 = 16, /*!< 1.02 V */ - V_AO_1P030 = 17, /*!< 1.03 V */ - V_AO_1P040 = 18, /*!< 1.04 V */ - V_AO_1P050 = 19, /*!< 1.05 V */ - V_AO_1P060 = 20, /*!< 1.06 V */ - V_AO_1P070 = 21, /*!< 1.07 V */ - V_AO_1P080 = 22, /*!< 1.08 V */ - V_AO_1P090 = 23, /*!< 1.09 V */ - V_AO_1P100 = 24, /*!< 1.1 V */ - V_AO_1P110 = 25, /*!< 1.11 V */ - V_AO_1P120 = 26, /*!< 1.12 V */ - V_AO_1P130 = 27, /*!< 1.13 V */ - V_AO_1P140 = 28, /*!< 1.14 V */ - V_AO_1P150 = 29, /*!< 1.15 V */ - V_AO_1P160 = 30, /*!< 1.16 V */ - V_AO_1P220 = 31 /*!< 1.22 V */ -} v_ao_t; - -/* Low Power modes */ -#define LOWPOWER_CFG_LPMODE_INDEX 0 -#define LOWPOWER_CFG_LPMODE_MASK (0x3UL << LOWPOWER_CFG_LPMODE_INDEX) -#define LOWPOWER_CFG_SELCLOCK_INDEX 2 -#define LOWPOWER_CFG_SELCLOCK_MASK (0x1UL << LOWPOWER_CFG_SELCLOCK_INDEX) -#define LOWPOWER_CFG_SELMEMSUPPLY_INDEX 3 -#define LOWPOWER_CFG_SELMEMSUPPLY_MASK (0x1UL << LOWPOWER_CFG_SELMEMSUPPLY_INDEX) -#define LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX 4 -#define LOWPOWER_CFG_MEMLOWPOWERMODE_MASK (0x1UL << LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX) -#define LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX 5 -#define LOWPOWER_CFG_LDODEEPSLEEPREF_MASK (0x1UL << LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX) - -#define LOWPOWER_CFG_LPMODE_ACTIVE 0 /*!< ACTIVE mode */ -#define LOWPOWER_CFG_LPMODE_DEEPSLEEP 1 /*!< DEEP SLEEP mode */ -#define LOWPOWER_CFG_LPMODE_POWERDOWN 2 /*!< POWER DOWN mode */ -#define LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN 3 /*!< DEEP POWER DOWN mode */ -#define LOWPOWER_CFG_LPMODE_SLEEP 4 /*!< SLEEP mode */ - -#define LOWPOWER_CFG_SELCLOCK_1MHZ 0 /*!< The 1 MHz clock is used during the configuration of the PMC */ -#define LOWPOWER_CFG_SELCLOCK_12MHZ \ - 1 /*!< The 12 MHz clock is used during the configuration of the PMC (to speed up PMC configuration process)*/ - -#define LOWPOWER_CFG_SELMEMSUPPLY_LDOMEM 0 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_MEM */ -#define LOWPOWER_CFG_SELMEMSUPPLY_LDODEEPSLEEP \ - 1 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_DEEP_SLEEP (or DCDC) */ - -#define LOWPOWER_CFG_MEMLOWPOWERMODE_SOURCEBIASING \ - 0 /*!< All SRAM instances use "Source Biasing" as low power mode technic (it is recommended to set LDO_MEM as high \ - as possible -- 1.1V typical -- during low power mode) */ -#define LOWPOWER_CFG_MEMLOWPOWERMODE_VOLTAGESCALING \ - 1 /*!< All SRAM instances use "Voltage Scaling" as low power mode technic (it is recommended to set LDO_MEM as low \ - as possible -- down to 0.7V -- during low power mode) */ - -/* CPU Retention Control*/ -#define LOWPOWER_CPURETCTRL_ENA_INDEX 0 -#define LOWPOWER_CPURETCTRL_ENA_MASK (0x1UL << LOWPOWER_CPURETCTRL_ENA_INDEX) -#define LOWPOWER_CPURETCTRL_MEMBASE_INDEX 1 -#define LOWPOWER_CPURETCTRL_MEMBASE_MASK (0x1FFFUL << LOWPOWER_CPURETCTRL_MEMBASE_INDEX) -#define LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX 14 -#define LOWPOWER_CPURETCTRL_RETDATALENGTH_MASK (0x3FFUL << LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX) - -/* Voltgae setting*/ -#define DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ \ - (72000000U) /* Maximum System Frequency allowed with DCDC Power Profile LOW */ -#define DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ \ - (100000000U) /* Maximum System Frequency allowed with DCDC Power Profile MEDIUM */ -#define DCDC_POWER_PROFILE_HIGH_MAX_FREQ_HZ \ - (150000000U) /* Maximum System Frequency allowed with DCDC Power Profile HIGH */ -#define PROCESS_NNN_AVG_HZ (19300000U) /* Average Ring OScillator value for Nominal (NNN) Manufacturing Process */ -#define PROCESS_NNN_STD_HZ \ - (400000U) /* Standard Deviation Ring OScillator value for Nominal (NNN) Manufacturing Process */ -#define PROCESS_NNN_LIMITS \ - (6U) /* Nominal (NNN) Manufacturing Process Ring Oscillator values limit (with respect to the Average value) */ -#define PROCESS_NNN_MIN_HZ \ - (PROCESS_NNN_AVG_HZ - \ - (PROCESS_NNN_LIMITS * \ - PROCESS_NNN_STD_HZ)) /* Minimum Ring OScillator value for Nominal (NNN) Manufacturing Process */ -#define PROCESS_NNN_MAX_HZ \ - (PROCESS_NNN_AVG_HZ + \ - (PROCESS_NNN_LIMITS * \ - PROCESS_NNN_STD_HZ)) /* Maximum Ring OScillator value for Nominal (NNN) Manufacturing Process */ -#define VOLTAGE_SSS_LOW_MV (1100U) /* Voltage Settings for : Process=SSS, DCDC Power Profile=LOW */ -#define VOLTAGE_SSS_MED_MV (1150U) /* Voltage Settings for : Process=SSS, DCDC Power Profile=MEDIUM */ -#define VOLTAGE_SSS_HIG_MV (1200U) /* Voltage Settings for : Process=SSS, DCDC Power Profile=HIGH */ -#define VOLTAGE_NNN_LOW_MV (1050U) /* Voltage Settings for : Process=NNN, DCDC Power Profile=LOW */ -#define VOLTAGE_NNN_MED_MV (1075U) /* Voltage Settings for : Process=NNN, DCDC Power Profile=MEDIUM */ -#define VOLTAGE_NNN_HIG_MV (1150U) /* Voltage Settings for : Process=NNN, DCDC Power Profile=HIGH */ -#define VOLTAGE_FFF_LOW_MV (1000U) /* Voltage Settings for : Process=FFF, DCDC Power Profile=LOW */ -#define VOLTAGE_FFF_MED_MV (1025U) /* Voltage Settings for : Process=FFF, DCDC Power Profile=MEDIUM */ -#define VOLTAGE_FFF_HIG_MV (1050U) /* Voltage Settings for : Process=FFF, DCDC Power Profile=HIGH */ - -/** - * @brief LDO Voltage control in Low Power Modes - */ -#define LOWPOWER_VOLTAGE_LDO_PMU_INDEX 0 -#define LOWPOWER_VOLTAGE_LDO_PMU_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) -#define LOWPOWER_VOLTAGE_LDO_MEM_INDEX 5 -#define LOWPOWER_VOLTAGE_LDO_MEM_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) -#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX 10 -#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_MASK (0x7ULL << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX) -#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX 19 -#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) -#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX 24 -#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) -#define LOWPOWER_VOLTAGE_DCDC_INDEX 29 -#define LOWPOWER_VOLTAGE_DCDC_MASK (0xFULL << LOWPOWER_VOLTAGE_DCDC_INDEX) - -/*! @brief set and clear bit MACRO's. */ -#define U32_SET_BITS(P, B) ((*(uint32_t *)P) |= (B)) -#define U32_CLR_BITS(P, B) ((*(uint32_t *)P) &= ~(B)) -/* Return values from Config (N-2) page of flash */ -#define GET_16MXO_TRIM() (*(uint32_t *)(FLASH_NMPA_BASE + 0xC8U)) // (0x3FCC8) -#define GET_32KXO_TRIM() (*(uint32_t *)(FLASH_NMPA_BASE + 0xCCU)) // (0x3FCCC) - -#define CPU_RETENTION_RAMX_STORAGE_START_ADDR (0x04002000) - -#define XO_SLAVE_EN (1) -/******************************************************************************* - * Codes - ******************************************************************************/ - -/******************************************************************************* - * LOCAL FUNCTIONS PROTOTYPES - ******************************************************************************/ -static void lf_get_deepsleep_core_supply_cfg(uint32_t exclude_from_pd, uint32_t *dcdc_voltage); -static uint32_t lf_set_ldo_ao_ldo_mem_voltage(uint32_t p_lp_mode, uint32_t p_dcdc_voltage); -static uint32_t lf_wakeup_io_ctrl(uint32_t p_wakeup_io_ctrl); -static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity); - -static void lowpower_set_dcdc_power_profile(lowpower_dcdc_power_profile_enum dcdc_power_profile); -static lowpower_process_corner_enum lowpower_get_part_process_corner(void); -static void lowpower_set_voltage_for_process(lowpower_dcdc_power_profile_enum dcdc_power_profile); -static lowpower_driver_interface_t *s_lowpowerDriver = (lowpower_driver_interface_t *)(0x130050e4); - -/** - * @brief Configures and enters in low power mode - * @param p_lowpower_cfg: pointer to a structure that contains all low power mode parameters - * @return Nothing - * - * !!! IMPORTANT NOTES : - * 1 - CPU Interrupt Enable registers are updated with p_lowpower_cfg->WAKEUPINT. They are NOT restored by the - * API. - * 2 - The Non Maskable Interrupt (NMI) should be disable before calling this API (otherwise, there is a risk - * of Dead Lock). - * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip - * reset) - */ -static void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg); - -/** - * @brief - * @param - * @return - */ -static void lf_set_dcdc_power_profile_low(void) -{ -#define DCDC_POWER_PROFILE_LOW_0_ADDRS (FLASH_NMPA_BASE + 0xE0U) // N4M (0x3FCE0U) / N4S (0x9FCE0U) -#define DCDC_POWER_PROFILE_LOW_1_ADDRS (FLASH_NMPA_BASE + 0xE4U) // N4M (0x3FCE4U) / N4S (0x9FCE4U) - - uint32_t dcdcTrimValue0 = (*((volatile unsigned int *)(DCDC_POWER_PROFILE_LOW_0_ADDRS))); - uint32_t dcdcTrimValue1 = (*((volatile unsigned int *)(DCDC_POWER_PROFILE_LOW_1_ADDRS))); - - if (0UL != (dcdcTrimValue0 & 0x1UL)) - { - PMC->DCDC0 = dcdcTrimValue0 >> 1; - PMC->DCDC1 = dcdcTrimValue1; - } -} - -/** - * @brief Configures and enters in low power mode - * @param : p_lowpower_cfg - * @return Nothing - */ -static void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg) -{ - /* PMC clk set to 12 MHZ */ - p_lowpower_cfg->CFG |= (uint32_t)LOWPOWER_CFG_SELCLOCK_12MHZ << LOWPOWER_CFG_SELCLOCK_INDEX; - - /* Enable Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP - * POWER DOWN) and Hardware Pin reset */ - PMC->REFFASTWKUP = (PMC->REFFASTWKUP & (~PMC_REFFASTWKUP_LPWKUP_MASK) & (~PMC_REFFASTWKUP_HWWKUP_MASK)) | - PMC_REFFASTWKUP_LPWKUP(1) | PMC_REFFASTWKUP_HWWKUP(1); - - /* SRAM uses Voltage Scaling in all Low Power modes */ - PMC->SRAMCTRL = (PMC->SRAMCTRL & (~PMC_SRAMCTRL_SMB_MASK)) | PMC_SRAMCTRL_SMB(3); - - /* CPU Retention configuration : preserve the value of FUNCRETENTIONCTRL.RET_LENTH which is a Hardware defined - * parameter. */ - p_lowpower_cfg->CPURETCTRL = (SYSCON->FUNCRETENTIONCTRL & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) | - (p_lowpower_cfg->CPURETCTRL & (~SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK)); - - /* Switch System Clock to FRO12Mhz (the configuration before calling this function will not be restored back) */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* Switch main clock to FRO12MHz */ - CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /* Main clock divided by 1 */ - SYSCON->FMCCR = (SYSCON->FMCCR & 0xFFFF0000UL) | 0x201AUL; /* Adjust FMC waiting time cycles */ - lf_set_dcdc_power_profile_low(); /* Align DCDC Power profile with the 12 MHz clock (DCDC Power Profile LOW) */ - - (*(s_lowpowerDriver->set_lowpower_mode))(p_lowpower_cfg); - - /* Restore the configuration of the MISCCTRL Register : LOWPWR_FLASH_BUF = 0, LDOMEMBLEEDDSLP = 0, LDOMEMHIGHZMODE = - * 0 */ - PMC->MISCCTRL &= (~PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK) & (~PMC_MISCCTRL_DISABLE_BLEED_MASK) & - (~PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK); -} - -/** - * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event - * @param None - * @return Nothing - */ -void POWER_CycleCpuAndFlash(void) -{ - (*(s_lowpowerDriver->power_cycle_cpu_and_flash))(); -}; - -/** - * brief PMC Deep Sleep function call - * return nothing - */ -void POWER_EnterDeepSleep(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t hardware_wake_ctrl) -{ - LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ - uint32_t cpu0_nmi_enable; - uint32_t cpu0_int_enable_0; - uint32_t cpu0_int_enable_1; - uint32_t dcdc_voltage; - uint32_t pmc_reset_ctrl; - /* Clear Low Power Mode configuration variable */ - (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); - - /* Configure Low Power Mode configuration variable */ - lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPSLEEP - << LOWPOWER_CFG_LPMODE_INDEX; /* DEEPSLEEP mode */ - - lf_get_deepsleep_core_supply_cfg(exclude_from_pd, &dcdc_voltage); - - if (((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_USB1_PHY) != 0UL) && - ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_LDOUSBHS) != 0UL)) - { - /* USB High Speed is required as wake-up source in Deep Sleep mode: make sure LDO FLASH NV stays powered during - * deep-sleep */ - exclude_from_pd = exclude_from_pd | (uint32_t)kPDRUNCFG_PD_LDOFLASHNV; - } - - /* DCDC will be always used during Deep Sleep (instead of LDO Deep Sleep); Make sure LDO MEM & Analog references - * will stay powered, Shut down ROM */ - lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd & ~(uint32_t)kPDRUNCFG_PD_DCDC & ~(uint32_t)kPDRUNCFG_PD_LDOMEM & - ~(uint32_t)kPDRUNCFG_PD_BIAS) | - (uint32_t)kPDRUNCFG_PD_LDODEEPSLEEP | (uint32_t)kPDRUNCFG_PD_ROM; - - /* Voltage control in DeepSleep Low Power Modes */ - /* The Memories Voltage settings below are for voltage scaling */ - lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_POWERDOWN, dcdc_voltage); - - /* SRAM retention control during POWERDOWN */ - lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; - - /* CPU Wake up & Interrupt sources control */ - lv_low_power_mode_cfg.WAKEUPINT = wakeup_interrupts; - lv_low_power_mode_cfg.WAKEUPSRC = wakeup_interrupts; - - /* Interrupts that allow DMA transfers with Flexcomm without waking up the Processor */ - if (0UL != (hardware_wake_ctrl & (LOWPOWER_HWWAKE_PERIPHERALS | LOWPOWER_HWWAKE_SDMA0 | LOWPOWER_HWWAKE_SDMA1))) - { - lv_low_power_mode_cfg.HWWAKE = (hardware_wake_ctrl & ~LOWPOWER_HWWAKE_FORCED) | LOWPOWER_HWWAKE_ENABLE_FRO192M; - } - - cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ - SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ - - /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power - * API */ - cpu0_int_enable_0 = NVIC->ISER[0]; - cpu0_int_enable_1 = NVIC->ISER[1]; - - pmc_reset_ctrl = PMC->RESETCTRL; - - if ((pmc_reset_ctrl & (PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK | PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK)) == - ((0x1UL << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT) | - (0x1UL << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT))) - { - /* BoD CORE reset is activated, so make sure BoD Core and Biasing won't be shutdown */ - lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_BODCORE & ~(uint32_t)kPDRUNCFG_PD_BIAS; - } - if ((pmc_reset_ctrl & (PMC_RESETCTRL_BODVBATRESETENA_SECURE_MASK | PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_MASK)) == - ((0x1UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_SHIFT) | - (0x1UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_SHIFT))) - { - /* BoD VBAT reset is activated, so make sure BoD VBAT and Biasing won't be shutdown */ - lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_BODVBAT & ~(uint32_t)kPDRUNCFG_PD_BIAS; - } - - /* Enter low power mode */ - POWER_EnterLowPower(&lv_low_power_mode_cfg); - - /* Restore the configuration of the NMI Register */ - SYSCON->NMISRC |= cpu0_nmi_enable; - - /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the - * low power API */ - NVIC->ISER[0] = cpu0_int_enable_0; - NVIC->ISER[1] = cpu0_int_enable_1; -} - -/** - * brief PMC power Down function call - * return nothing - */ -void POWER_EnterPowerDown(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t cpu_retention_ctrl) -{ - LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ - uint32_t cpu0_nmi_enable; - uint32_t cpu0_int_enable_0; - uint32_t cpu0_int_enable_1; - uint64_t wakeup_src_int; - uint32_t pmc_reset_ctrl; - uint32_t rng_entropy_save[6]; - - uint32_t analog_ctrl_regs[12]; /* To store Analog Controller Regristers */ - - /* Clear Low Power Mode configuration variable */ - (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); - - /* Configure Low Power Mode configuration variable */ - lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_POWERDOWN - << LOWPOWER_CFG_LPMODE_INDEX; /* POWER DOWN mode */ - - /* Only FRO32K, XTAL32K, COMP, BIAS and LDO_MEM can be stay powered during POWERDOWN (valid from application point - * of view; Hardware allows BODVBAT, LDODEEPSLEEP and FRO1M to stay powered, that's why they are excluded below) */ - lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd) | (uint32_t)kPDRUNCFG_PD_BODVBAT | (uint32_t)kPDRUNCFG_PD_FRO1M | - (uint32_t)kPDRUNCFG_PD_LDODEEPSLEEP; - - /* @TODO Guillaume: add save/restore entropy during PowerDown */ - /* Entropy for RNG need to saved */ - if ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_RNG) != 0UL) - { - CLOCK_EnableClock(kCLOCK_Rng); - RESET_ClearPeripheralReset(kRNG_RST_SHIFT_RSTn); - for (int i = 0; i < 6; i++) - { - rng_entropy_save[i] = RNG->RANDOM_NUMBER; - } - } - - /* CPU0 retention Ctrl. - * For the time being, we do not allow customer to relocate the CPU retention area in SRAMX, meaning that the - * retention area range is [0x0400_6000 - 0x0400_6600] (beginning of RAMX2 for N4S) If required by customer, - * retention area range is [0x0400_2000 - 0x0400_2600] (beginning of RAMX2 for N4M) If required by customer, - * cpu_retention_ctrl[13:1] will be used for that to modify the default retention area - */ - lv_low_power_mode_cfg.CPURETCTRL = - (cpu_retention_ctrl & LOWPOWER_CPURETCTRL_ENA_MASK) | - ((((uint32_t)CPU_RETENTION_RAMX_STORAGE_START_ADDR >> 2UL) << LOWPOWER_CPURETCTRL_MEMBASE_INDEX) & - LOWPOWER_CPURETCTRL_MEMBASE_MASK); - if (0UL != (cpu_retention_ctrl & 0x1UL)) - { - /* Add RAMX2 for retention */ - sram_retention_ctrl |= LOWPOWER_SRAMRETCTRL_RETEN_RAMX2; - /* CPU retention is required: store Analog Controller Registers */ - analog_ctrl_regs[0] = ANACTRL->FRO192M_CTRL; - analog_ctrl_regs[1] = ANACTRL->ANALOG_CTRL_CFG; - analog_ctrl_regs[2] = ANACTRL->ADC_CTRL; - analog_ctrl_regs[3] = ANACTRL->XO32M_CTRL; - analog_ctrl_regs[4] = ANACTRL->BOD_DCDC_INT_CTRL; - analog_ctrl_regs[5] = ANACTRL->RINGO0_CTRL; - analog_ctrl_regs[6] = ANACTRL->RINGO1_CTRL; - analog_ctrl_regs[7] = ANACTRL->RINGO2_CTRL; - analog_ctrl_regs[8] = ANACTRL->LDO_XO32M; - analog_ctrl_regs[9] = ANACTRL->AUX_BIAS; - analog_ctrl_regs[10] = ANACTRL->USBHS_PHY_CTRL; - analog_ctrl_regs[11] = ANACTRL->USBHS_PHY_TRIM; - } - - /* SRAM retention control during POWERDOWN */ - lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; - - /* Sanity check: If retention is required for any of SRAM instances, make sure LDO MEM will stay powered */ - if ((sram_retention_ctrl & 0x7FFFUL) != 0UL) - { - lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_LDOMEM; - } - - /* Voltage control in Low Power Modes */ - /* The Memories Voltage settings below are for voltage scaling */ - lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_POWERDOWN, 0); - - /* CPU Wake up & Interrupt sources control : only WAKEUP_GPIO_GLOBALINT0, WAKEUP_GPIO_GLOBALINT1, WAKEUP_FLEXCOMM3, - * WAKEUP_ACMP_CAPT, WAKEUP_RTC_LITE_ALARM_WAKEUP, WAKEUP_OS_EVENT_TIMER, WAKEUP_ALLWAKEUPIOS */ - wakeup_src_int = (uint64_t)(WAKEUP_GPIO_GLOBALINT0 | WAKEUP_GPIO_GLOBALINT1 | WAKEUP_FLEXCOMM3 | WAKEUP_ACMP | - WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER | WAKEUP_ALLWAKEUPIOS); - lv_low_power_mode_cfg.WAKEUPINT = wakeup_interrupts & wakeup_src_int; - lv_low_power_mode_cfg.WAKEUPSRC = wakeup_interrupts & wakeup_src_int; - - cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ - SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ - - /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power - * API */ - cpu0_int_enable_0 = NVIC->ISER[0]; - cpu0_int_enable_1 = NVIC->ISER[1]; - - /* Disable BoD VBAT and BoD Core resets */ - /* BOD VBAT disable reset */ - pmc_reset_ctrl = - PMC->RESETCTRL & (~(PMC_RESETCTRL_BODVBATRESETENA_SECURE_MASK | PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_MASK)); - pmc_reset_ctrl |= (0x2UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_SHIFT) | - (0x2UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_SHIFT); - - /* BOD CORE disable reset */ - pmc_reset_ctrl &= (~(PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK | PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK)); - pmc_reset_ctrl |= (0x2UL << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT) | - (0x2UL << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT); - - PMC->RESETCTRL = pmc_reset_ctrl; - - /* Enter low power mode */ - POWER_EnterLowPower(&lv_low_power_mode_cfg); - - /*** We'll reach this point in case of POWERDOWN with CPU retention or if the POWERDOWN has not been taken (for - instance because an interrupt is pending). In case of CPU retention, assumption is that the SRAM containing the - stack used to call this function shall be preserved during low power ***/ - -#if defined(PUF_SRAM_CTRL_CFG_ENABLE_MASK) - /* Following code is to reset PUF to remove over consumption */ - /* Enable PUF register clock to access register */ - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_PUF_MASK; - /* Release PUF reset */ - SYSCON->PRESETCTRLCLR[2] = SYSCON_PRESETCTRL2_PUF_RST_MASK; - /* Enable PUF SRAM */ - PUF_SRAM_CTRL->CFG |= PUF_SRAM_CTRL_CFG_ENABLE_MASK | PUF_SRAM_CTRL_CFG_CKGATING_MASK; - - /* Disable PUF register clock. */ - // Delaying the line of code below until the PUF State Machine execution is completed: - // Shuting down the clock to early will prevent the state machine from reaching the end. - // => Wait for status bit in PUF Controller Registers before stop PUF clock. - while (0UL == (PUF_SRAM_CTRL->INT_STATUS & PUF_SRAM_CTRL_INT_STATUS_READY_MASK)) - { - } - - SYSCON->AHBCLKCTRLCLR[2] = SYSCON_AHBCLKCTRL2_PUF_MASK; -#endif - /* Restore the configuration of the NMI Register */ - SYSCON->NMISRC |= cpu0_nmi_enable; - - /* Restore PMC RESETCTRL register */ - PMC->RESETCTRL = pmc_reset_ctrl; - - /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the - * low power API */ - NVIC->ISER[0] = cpu0_int_enable_0; - NVIC->ISER[1] = cpu0_int_enable_1; - - if ((cpu_retention_ctrl & 0x1UL) != 0UL) - { - /* Restore Analog Controller Registers */ - ANACTRL->FRO192M_CTRL = analog_ctrl_regs[0] | ANACTRL_FRO192M_CTRL_WRTRIM_MASK; - ANACTRL->ANALOG_CTRL_CFG = analog_ctrl_regs[1]; - ANACTRL->ADC_CTRL = analog_ctrl_regs[2]; - ANACTRL->XO32M_CTRL = analog_ctrl_regs[3]; - ANACTRL->BOD_DCDC_INT_CTRL = analog_ctrl_regs[4]; - ANACTRL->RINGO0_CTRL = analog_ctrl_regs[5]; - ANACTRL->RINGO1_CTRL = analog_ctrl_regs[6]; - ANACTRL->RINGO2_CTRL = analog_ctrl_regs[7]; - ANACTRL->LDO_XO32M = analog_ctrl_regs[8]; - ANACTRL->AUX_BIAS = analog_ctrl_regs[9]; - ANACTRL->USBHS_PHY_CTRL = analog_ctrl_regs[10]; - ANACTRL->USBHS_PHY_TRIM = analog_ctrl_regs[11]; - } - - /* @TODO Guillaume: add save/restore entropy during PowerDown */ - /* Restore Entropy for RNG */ - if ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_RNG) != 0UL) - { - RNG->POWERDOWN &= ~RNG_POWERDOWN_POWERDOWN_MASK; - for (int i = 0; i < 6; i++) - { - RNG->ENTROPY_INJECT = rng_entropy_save[i]; - } - } -} - -/** - * brief PMC Deep Sleep Power Down function call - * return nothing - */ -void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t wakeup_io_ctrl) -{ - LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ - uint32_t cpu0_nmi_enable; - uint32_t cpu0_int_enable_0; - uint32_t cpu0_int_enable_1; - uint32_t pmc_reset_ctrl; - - /* Clear Low Power Mode configuration variable */ - (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); - - /* Configure Low Power Mode configuration variable */ - lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN - << LOWPOWER_CFG_LPMODE_INDEX; /* DEEP POWER DOWN mode */ - - /* Only FRO32K, XTAL32K and LDO_MEM can be stay powered during DEEPPOWERDOWN (valid from application point of view; - * Hardware allows BODVBAT, BIAS FRO1M and COMP to stay powered, that's why they are excluded below) */ - lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd) | (uint32_t)kPDRUNCFG_PD_BIAS | (uint32_t)kPDRUNCFG_PD_BODVBAT | - (uint32_t)kPDRUNCFG_PD_FRO1M | (uint32_t)kPDRUNCFG_PD_COMP; - - /* SRAM retention control during DEEPPOWERDOWN */ - /* RAM00 used by ROM code to restart. */ - sram_retention_ctrl = sram_retention_ctrl & (~(LOWPOWER_SRAMRETCTRL_RETEN_RAM00)); - - /* SRAM retention control during DEEPPOWERDOWN */ - lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; - - /* Sanity check: If retention is required for any of SRAM instances, make sure LDO MEM will stay powered */ - if ((sram_retention_ctrl & 0x7FFFUL) != 0UL) - { - lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_LDOMEM; - } - - /* Voltage control in Low Power Modes */ - /* The Memories Voltage settings below are for voltage scaling */ - lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN, 0); - - lv_low_power_mode_cfg.WAKEUPINT = - wakeup_interrupts & (WAKEUP_RTC_LITE_ALARM_WAKEUP | - WAKEUP_OS_EVENT_TIMER); /* CPU Wake up sources control : only WAKEUP_RTC_LITE_ALARM_WAKEUP, - WAKEUP_OS_EVENT_TIMER */ - lv_low_power_mode_cfg.WAKEUPSRC = - wakeup_interrupts & - (WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER | - WAKEUP_ALLWAKEUPIOS); /*!< Hardware Wake up sources control: : only WAKEUP_RTC_LITE_ALARM_WAKEUP, - WAKEUP_OS_EVENT_TIMER and WAKEUP_ALLWAKEUPIOS */ - - /* Wake up I/O sources */ - lv_low_power_mode_cfg.WAKEUPIOSRC = lf_wakeup_io_ctrl(wakeup_io_ctrl); - - cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ - SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ - - /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power - * API */ - cpu0_int_enable_0 = NVIC->ISER[0]; - cpu0_int_enable_1 = NVIC->ISER[1]; - - /* Save the configuration of the PMC RESETCTRL register */ - /* BOD VBAT disable reset */ - pmc_reset_ctrl = - PMC->RESETCTRL & (~(PMC_RESETCTRL_BODVBATRESETENA_SECURE_MASK | PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_MASK)); - pmc_reset_ctrl |= (0x2UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_SHIFT) | - (0x2UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_SHIFT); - - /* BOD CORE disable reset */ - pmc_reset_ctrl &= (~(PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK | PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK)); - pmc_reset_ctrl |= (0x2UL << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT) | - (0x2UL << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT); - - PMC->RESETCTRL = pmc_reset_ctrl; - - /* Enter low power mode */ - POWER_EnterLowPower(&lv_low_power_mode_cfg); - - /*** We'll reach this point ONLY and ONLY if the DEEPPOWERDOWN has not been taken (for instance because an RTC or - * OSTIMER interrupt is pending) ***/ - - /* Restore the configuration of the NMI Register */ - SYSCON->NMISRC |= cpu0_nmi_enable; - - /* Restore PMC RESETCTRL register */ - PMC->RESETCTRL = pmc_reset_ctrl; - - /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the - * low power API */ - NVIC->ISER[0] = cpu0_int_enable_0; - NVIC->ISER[1] = cpu0_int_enable_1; -} - -/** - * brief PMC Sleep function call - * return nothing - */ -void POWER_EnterSleep(void) -{ - uint32_t pmsk; - pmsk = __get_PRIMASK(); - __disable_irq(); - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - __WFI(); - __set_PRIMASK(pmsk); -} - -/** - * @brief Get Digital Core logic supply source to be used during Deep Sleep. - * @param [in] exclude_from_pd: COmpoenents NOT to be powered down during Deep Sleep - * @param [out] core_supply: 0 = LDO DEEPSLEEP will be used / 1 = DCDC will be used - * @param [out] dcdc_voltage: as defined by V_DCDC_* in fsl_power.h - - * @return Nothing - */ -static void lf_get_deepsleep_core_supply_cfg(uint32_t exclude_from_pd, uint32_t *dcdc_voltage) -{ - *dcdc_voltage = V_DCDC_0P950; /* Default value */ - - if (((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_USB1_PHY) != 0) && - ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_LDOUSBHS) != 0)) - { - /* USB High Speed is required as wake-up source in Deep Sleep mode */ - PMC->MISCCTRL |= PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK; /* Force flash buffer in low power mode */ - *dcdc_voltage = V_DCDC_1P000; /* Set DCDC voltage to be 1.000 V (USB HS IP cannot work below 0.990 V) */ - } -} - -/** - * @brief - * @param - * @return - */ -static uint32_t lf_set_ldo_ao_ldo_mem_voltage(uint32_t p_lp_mode, uint32_t p_dcdc_voltage) -{ -#define FLASH_NMPA_LDO_AO_ADDRS (FLASH_NMPA_BASE + 0x0F4U) // N4M (0x3FCF4U) / N4S (0x9FCF4U) -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK (0x100U) -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK (0x3E00U) -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT (9U) -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK (0x10000U) -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK (0x3E0000U) -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT (17U) -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK (0x1000000U) -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK (0x3E000000U) -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT (25U) - - uint32_t ldo_ao_trim, voltage; - uint32_t lv_v_ldo_pmu, lv_v_ldo_pmu_boost; - - ldo_ao_trim = (*((volatile unsigned int *)(FLASH_NMPA_LDO_AO_ADDRS))); - - switch (p_lp_mode) - { - case LOWPOWER_CFG_LPMODE_DEEPSLEEP: - { - if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK) != 0UL) - { - /* Apply settings coming from Flash */ - lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK) >> FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT; - lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ - } - else - { - /* Apply default settings */ - lv_v_ldo_pmu = (uint32_t)V_AO_0P900; - lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P850; - } - } - break; - - case LOWPOWER_CFG_LPMODE_POWERDOWN: - { - if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK) != 0UL) - { - /* Apply settings coming from Flash */ - lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK) >> FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT; - lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ - } - else - { - /* Apply default settings */ - lv_v_ldo_pmu = (uint32_t)V_AO_0P800; - lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P750; - } - } - break; - - case LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN: - { - if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK) != 0UL) - { - /* Apply settings coming from Flash */ - lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK) >> FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT; - lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ - } - else - { - /* Apply default settings */ - lv_v_ldo_pmu = (uint32_t)V_AO_0P800; - lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P750; - } - } - break; - - default: - /* Should never reach this point */ - lv_v_ldo_pmu = (uint32_t)V_AO_1P100; - lv_v_ldo_pmu_boost = (uint32_t)V_AO_1P050; - break; - } - - /* The Memories Voltage settings below are for voltage scaling */ - voltage = - (lv_v_ldo_pmu << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) | /* */ - (lv_v_ldo_pmu_boost << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) | /* */ - ((uint32_t)V_AO_0P750 << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) | /* Set to 0.75V (voltage Scaling) */ - ((uint32_t)V_AO_0P700 << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) | /* Set to 0.7V (voltage Scaling) */ - ((uint32_t)V_DEEPSLEEP_0P900 - << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX) | /* Set to 0.90 V (Not used because LDO_DEEP_SLEEP is disabled)*/ - (p_dcdc_voltage << LOWPOWER_VOLTAGE_DCDC_INDEX) /* */ - ; - - return (voltage); -} - -/** - * @brief - * @param - * @return - */ -static uint32_t lf_wakeup_io_ctrl(uint32_t p_wakeup_io_ctrl) -{ - uint32_t wake_up_type; - uint32_t wakeup_io_ctrl_reg; - uint8_t use_external_pullupdown = 0; - - /* Configure Pull up & Pull down based on the required wake-up edge */ - CLOCK_EnableClock(kCLOCK_Iocon); - - wakeup_io_ctrl_reg = 0UL; - - /* Wake-up I/O 0 */ - wake_up_type = (p_wakeup_io_ctrl & 0x3UL) >> LOWPOWER_WAKEUPIOSRC_PIO0_INDEX; - wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO0_INDEX); - use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK) >> - LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX); - - if (use_external_pullupdown == 0UL) - { - if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) - { - /* Rising edge and both rising and falling edges */ - IOCON->PIO[1][1] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); - } - else - { - if (wake_up_type == 2UL) - { - /* Falling edge only */ - IOCON->PIO[1][1] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); - } - else - { - /* Wake-up I/O is disabled : set it as required by the user */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as Plain Input */ - // @TODO not used p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-up or pull-down */ - // @TODO update for mask name - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as pull-up */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-down */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); - } - } - } - } - } - else - { - wakeup_io_ctrl_reg |= ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); - } - - /* Wake-up I/O 1 */ - wake_up_type = (p_wakeup_io_ctrl & 0xCUL) >> LOWPOWER_WAKEUPIOSRC_PIO1_INDEX; - wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO1_INDEX); - use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK) >> - LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX); - - if (use_external_pullupdown == 0UL) - { - if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) - { - /* Rising edge and both rising and falling edges */ - IOCON->PIO[0][28] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); - } - else - { - if (wake_up_type == 2UL) - { - /* Falling edge only */ - IOCON->PIO[0][28] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); - } - else - { - /* Wake-up I/O is disabled : set it as required by the user */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as Plain Input */ - // @TODO not used p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-up or pull-down */ - // @TODO update for mask name - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as pull-up */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-down */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); - } - } - } - } - } - else - { - wakeup_io_ctrl_reg |= ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); - } - - /* Wake-up I/O 2 */ - wake_up_type = (p_wakeup_io_ctrl & 0x30UL) >> LOWPOWER_WAKEUPIOSRC_PIO2_INDEX; - wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO2_INDEX); - use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK) >> - LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX); - - if (use_external_pullupdown == 0UL) - { - if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) - { - /* Rising edge and both rising and falling edges */ - IOCON->PIO[1][18] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); - } - else - { - if (wake_up_type == 2UL) - { - /* Falling edge only */ - IOCON->PIO[1][18] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); - } - else - { - /* Wake-up I/O is disabled : set it as required by the user */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as Plain Input */ - // @TODO not used p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-up or pull-down */ - // @TODO update for mask name - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as pull-up */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-down */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); - } - } - } - } - } - else - { - wakeup_io_ctrl_reg |= ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); - } - - /* Wake-up I/O 3 */ - wake_up_type = (p_wakeup_io_ctrl & 0xC0UL) >> LOWPOWER_WAKEUPIOSRC_PIO3_INDEX; - wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO3_INDEX); - use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK) >> - LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX); - - if (use_external_pullupdown == 0UL) - { - if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) - { - /* Rising edge and both rising and falling edges */ - IOCON->PIO[1][30] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); - } - else - { - if (wake_up_type == 2UL) - { - /* Falling edge only */ - IOCON->PIO[1][30] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); - } - else - { - /* Wake-up I/O is disabled : set it as required by the user */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as Plain Input */ - // @TODO not used p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-up or pull-down */ - // @TODO update for mask name - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as pull-up */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-down */ - wakeup_io_ctrl_reg |= - ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); - } - } - } - } - } - else - { - wakeup_io_ctrl_reg |= ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); - } - - return (wakeup_io_ctrl_reg); -} - -/** - * @brief - * @param - * @return - */ -static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity) -{ - /* Compensate for discontinuity in the capacitor banks */ - if (u8OscCap < 64U) - { - if (u8OscCap >= u8CapBankDiscontinuity) - { - u8OscCap -= u8CapBankDiscontinuity; - } - else - { - u8OscCap = 0U; - } - } - else - { - if (u8OscCap <= (127U - u8CapBankDiscontinuity)) - { - u8OscCap += u8CapBankDiscontinuity; - } - else - { - u8OscCap = 127U; - } - } - return u8OscCap; -} - -/** - * @brief Described in fsl_common.h - * @param - * @return - */ -static void lowpower_set_system_voltage(uint32_t system_voltage_mv) -{ - /* - * Set system voltage - */ - uint32_t lv_ldo_ao = (uint32_t)V_AO_1P100; /* */ - uint32_t lv_ldo_ao_boost = (uint32_t)V_AO_1P150; /* */ - uint32_t lv_dcdc = (uint32_t)V_DCDC_1P100; /* */ - - if (system_voltage_mv <= 950UL) - { - lv_dcdc = (uint32_t)V_DCDC_0P950; - lv_ldo_ao = (uint32_t)V_AO_0P960; - lv_ldo_ao_boost = (uint32_t)V_AO_1P010; - } - else if (system_voltage_mv <= 975UL) - { - lv_dcdc = (uint32_t)V_DCDC_0P975; - lv_ldo_ao = (uint32_t)V_AO_0P980; - lv_ldo_ao_boost = (uint32_t)V_AO_1P030; - } - else if (system_voltage_mv <= 1000UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P000; - lv_ldo_ao = (uint32_t)V_AO_1P000; - lv_ldo_ao_boost = (uint32_t)V_AO_1P050; - } - else if (system_voltage_mv <= 1025UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P025; - lv_ldo_ao = (uint32_t)V_AO_1P030; - lv_ldo_ao_boost = (uint32_t)V_AO_1P080; - } - else if (system_voltage_mv <= 1050UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P050; - lv_ldo_ao = (uint32_t)V_AO_1P060; - lv_ldo_ao_boost = (uint32_t)V_AO_1P110; - } - else if (system_voltage_mv <= 1075UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P075; - lv_ldo_ao = (uint32_t)V_AO_1P080; - lv_ldo_ao_boost = (uint32_t)V_AO_1P130; - } - else if (system_voltage_mv <= 1100UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P100; - lv_ldo_ao = (uint32_t)V_AO_1P100; - lv_ldo_ao_boost = (uint32_t)V_AO_1P150; - } - else if (system_voltage_mv <= 1125UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P125; - lv_ldo_ao = (uint32_t)V_AO_1P130; - lv_ldo_ao_boost = (uint32_t)V_AO_1P160; - } - else if (system_voltage_mv <= 1150UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P150; - lv_ldo_ao = (uint32_t)V_AO_1P160; - lv_ldo_ao_boost = (uint32_t)V_AO_1P220; - } - else if (system_voltage_mv <= 1175UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P175; - lv_ldo_ao = (uint32_t)V_AO_1P160; - lv_ldo_ao_boost = (uint32_t)V_AO_1P220; - } - else - { - lv_dcdc = (uint32_t)V_DCDC_1P200; - lv_ldo_ao = (uint32_t)V_AO_1P160; - lv_ldo_ao_boost = (uint32_t)V_AO_1P220; - } - - /* Set up LDO Always-On voltages */ - PMC->LDOPMU = (PMC->LDOPMU & (~PMC_LDOPMU_VADJ_MASK) & (~PMC_LDOPMU_VADJ_BOOST_MASK)) | PMC_LDOPMU_VADJ(lv_ldo_ao) | - PMC_LDOPMU_VADJ_BOOST(lv_ldo_ao_boost); - - /* Set up DCDC voltage */ - PMC->DCDC0 = (PMC->DCDC0 & (~PMC_DCDC0_VOUT_MASK)) | PMC_DCDC0_VOUT(lv_dcdc); -} - -/** - * @brief Described in fsl_common.h - * @param - * @return - */ -static void lowpower_set_dcdc_power_profile(lowpower_dcdc_power_profile_enum dcdc_power_profile) -{ -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ADDRS (FLASH_NMPA_BASE + 0xE0U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ADDRS (FLASH_NMPA_BASE + 0xE4U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ADDRS (FLASH_NMPA_BASE + 0xE8U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ADDRS (FLASH_NMPA_BASE + 0xECU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ADDRS (FLASH_NMPA_BASE + 0xD8U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ADDRS (FLASH_NMPA_BASE + 0xDCU) - - const uint32_t PMC_DCDC0_DEFAULT = 0x010C4E68; - const uint32_t PMC_DCDC1_DEFAULT = 0x01803A98; - - uint32_t dcdcTrimValue0; - uint32_t dcdcTrimValue1; - - switch (dcdc_power_profile) - { - case DCDC_POWER_PROFILE_LOW: - /* Low */ - dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ADDRS))); - dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ADDRS))); - - if (0UL != (dcdcTrimValue0 & 0x1UL)) - { - dcdcTrimValue0 = dcdcTrimValue0 >> 1; - - PMC->DCDC0 = dcdcTrimValue0; - PMC->DCDC1 = dcdcTrimValue1; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : DCDC Power Profile set to " - "LOW" - "\n"); -#endif - } - break; - - case DCDC_POWER_PROFILE_MEDIUM: - /* Medium */ - dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ADDRS))); - dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ADDRS))); - - if (0UL != (dcdcTrimValue0 & 0x1UL)) - { - dcdcTrimValue0 = dcdcTrimValue0 >> 1; - - PMC->DCDC0 = dcdcTrimValue0; - PMC->DCDC1 = dcdcTrimValue1; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : DCDC Power Profile set to " - "MEDIUM" - "\n"); -#endif - } - break; - - case DCDC_POWER_PROFILE_HIGH: - /* High */ - dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ADDRS))); - dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ADDRS))); - - if (0UL != (dcdcTrimValue0 & 0x1UL)) - { - dcdcTrimValue0 = dcdcTrimValue0 >> 1; - - PMC->DCDC0 = dcdcTrimValue0; - PMC->DCDC1 = dcdcTrimValue1; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : DCDC Power Profile set to " - "HIGH" - "\n"); -#endif - } - break; - - default: - /* Low */ - PMC->DCDC0 = PMC_DCDC0_DEFAULT; - PMC->DCDC1 = PMC_DCDC1_DEFAULT; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : DCDC Power Profile set to " - "LOW" - "\n"); -#endif - break; - } -} - -/** - * @brief - * @param - * @return - */ -static lowpower_process_corner_enum lowpower_get_part_process_corner(void) -{ -#define FLASH_NMPA_PVT_MONITOR_0_RINGO_ADDRS (FLASH_NMPA_BASE + 0x130U) -#define FLASH_NMPA_PVT_MONITOR_1_RINGO_ADDRS (FLASH_NMPA_BASE + 0x140U) - - lowpower_process_corner_enum part_process_corner; - uint32_t pvt_ringo_hz; - uint32_t pvt_ringo_0 = (*((volatile unsigned int *)(FLASH_NMPA_PVT_MONITOR_0_RINGO_ADDRS))); - uint32_t pvt_ringo_1 = (*((volatile unsigned int *)(FLASH_NMPA_PVT_MONITOR_1_RINGO_ADDRS))); - - /* - * Check that the PVT Monitors Trimmings in flash are valid. - */ - if (0UL != (pvt_ringo_0 & 0x1UL)) - { - /* PVT Trimmings in Flash are valid */ - pvt_ringo_0 = pvt_ringo_0 >> 1; - } - else - { - /* PVT Trimmings in Flash are NOT valid (average value assumed) */ - pvt_ringo_0 = PROCESS_NNN_AVG_HZ; - } - - if (0UL != (pvt_ringo_1 & 0x1UL)) - { - /* PVT Trimmings in Flash are valid */ - pvt_ringo_1 = pvt_ringo_1 >> 1; - } - else - { - /* PVT Trimmings in Flash are NOT valid (average value assumed) */ - pvt_ringo_1 = PROCESS_NNN_AVG_HZ; - } - - if (pvt_ringo_1 <= pvt_ringo_0) - { - pvt_ringo_hz = pvt_ringo_1; - } - else - { - pvt_ringo_hz = pvt_ringo_0; - } - - /* - * Determine the process corner based on the value of the Ring Oscillator frequency - */ - if (pvt_ringo_hz <= PROCESS_NNN_MIN_HZ) - { - /* SSS Process Corner */ - part_process_corner = PROCESS_CORNER_SSS; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : Process Corner : " - "SSS" - "\n"); -#endif - } - else - { - if (pvt_ringo_hz <= PROCESS_NNN_MAX_HZ) - { - /* NNN Process Corner */ - part_process_corner = PROCESS_CORNER_NNN; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : Process Corner : " - "NNN" - "\n"); -#endif - } - else - { - /* FFF Process Corner */ - part_process_corner = PROCESS_CORNER_FFF; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : Process Corner : " - "FFF" - "\n"); -#endif - } - } - - return (part_process_corner); -} - -/** - * @brief Described in fsl_common.h - * @param - * @return - */ -static void lowpower_set_voltage_for_process(lowpower_dcdc_power_profile_enum dcdc_power_profile) -{ - /* Get Sample Process Corner */ - lowpower_process_corner_enum part_process_corner = lowpower_get_part_process_corner(); - - switch (part_process_corner) - { - case PROCESS_CORNER_SSS: - /* Slow Corner */ - { - switch (dcdc_power_profile) - { - case DCDC_POWER_PROFILE_MEDIUM: - /* Medium */ - lowpower_set_system_voltage(VOLTAGE_SSS_MED_MV); - break; - - case DCDC_POWER_PROFILE_HIGH: - /* High */ - lowpower_set_system_voltage(VOLTAGE_SSS_HIG_MV); - break; - - default: - /* DCDC_POWER_PROFILE_LOW */ - lowpower_set_system_voltage(VOLTAGE_SSS_LOW_MV); - break; - } // switch(dcdc_power_profile) - } - break; - - case PROCESS_CORNER_FFF: - /* Fast Corner */ - { - switch (dcdc_power_profile) - { - case DCDC_POWER_PROFILE_MEDIUM: - /* Medium */ - lowpower_set_system_voltage(VOLTAGE_FFF_MED_MV); - break; - - case DCDC_POWER_PROFILE_HIGH: - /* High */ - lowpower_set_system_voltage(VOLTAGE_FFF_HIG_MV); - break; - - default: - /* DCDC_POWER_PROFILE_LOW */ - lowpower_set_system_voltage(VOLTAGE_FFF_LOW_MV); - break; - } // switch(dcdc_power_profile) - } - break; - - default: - /* Nominal (NNN) and all others Process Corners : assume Nominal Corner */ - { - switch (dcdc_power_profile) - { - case DCDC_POWER_PROFILE_MEDIUM: - /* Medium */ - lowpower_set_system_voltage(VOLTAGE_NNN_MED_MV); - break; - - case DCDC_POWER_PROFILE_HIGH: - /* High */ - lowpower_set_system_voltage(VOLTAGE_NNN_HIG_MV); - break; - - default: - /* DCDC_POWER_PROFILE_LOW */ - lowpower_set_system_voltage(VOLTAGE_NNN_LOW_MV); - break; - } // switch(dcdc_power_profile) - break; - } - } // switch(part_process_corner) -} - -/** - * @brief Described in fsl_common.h - * @param - * @return - */ -void POWER_SetVoltageForFreq(uint32_t system_freq_hz) -{ - if (system_freq_hz <= DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ) - { - /* [0 Hz - DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz] */ - lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_LOW); /* DCDC VOUT = 1.05 V by default */ - lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_LOW); - } - else - { - if (system_freq_hz <= DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ) - { - /* ]DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz - DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz] */ - lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_MEDIUM); /* DCDC VOUT = 1.15 V by default */ - lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_MEDIUM); - } - else - { - /* > DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz */ - lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_HIGH); /* DCDC VOUT = 1.2 V by default */ - lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_HIGH); - } - } -} - -void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, - int32_t pi32_16MfXtalPPcbParCappF_x100, - int32_t pi32_16MfXtalNPcbParCappF_x100) -{ - uint32_t u32XOTrimValue; - uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF, u8XOSlave; - int32_t iaXin_x4, ibXin, iaXout_x4, ibXout; - int32_t iXOCapInpF_x100, iXOCapOutpF_x100; - uint8_t u8XOCapInCtrl, u8XOCapOutCtrl; - uint32_t u32RegVal; - int32_t i32Tmp; - - /* Enable and set LDO, if not already done */ - POWER_SetXtal16mhzLdo(); - /* Get Cal values from Flash */ - u32XOTrimValue = GET_16MXO_TRIM(); - /* Check validity and apply */ - if ((0UL != (u32XOTrimValue & 1UL)) && (0UL != ((u32XOTrimValue >> 15UL) & 1UL))) - { - /* These fields are 7 bits, unsigned */ - u8IECXinCapCal6pF = (uint8_t)((u32XOTrimValue >> 1UL) & 0x7fUL); - u8IECXinCapCal8pF = (uint8_t)((u32XOTrimValue >> 8UL) & 0x7fUL); - u8IECXoutCapCal6pF = (uint8_t)((u32XOTrimValue >> 16UL) & 0x7fUL); - u8IECXoutCapCal8pF = (uint8_t)((u32XOTrimValue >> 23UL) & 0x7fUL); - /* This field is 1 bit */ - u8XOSlave = (uint8_t)((u32XOTrimValue >> 30UL) & 0x1UL); - /* Linear fit coefficients calculation */ - iaXin_x4 = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF; - ibXin = (int)u8IECXinCapCal6pF - iaXin_x4 * 3; - iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF; - ibXout = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3; - } - else - { - iaXin_x4 = 20; // gain in LSB/pF - ibXin = -9; // offset in LSB - iaXout_x4 = 20; // gain in LSB/pF - ibXout = -13; // offset in LSB - u8XOSlave = 0; - } - /* In & out load cap calculation with derating */ - iXOCapInpF_x100 = 2 * pi32_16MfXtalIecLoadpF_x100 - pi32_16MfXtalNPcbParCappF_x100 + - 39 * ((int32_t)XO_SLAVE_EN - (int32_t)u8XOSlave) - 15; - iXOCapOutpF_x100 = 2 * pi32_16MfXtalIecLoadpF_x100 - pi32_16MfXtalPPcbParCappF_x100 - 21; - /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */ - i32Tmp = ((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400; - u8XOCapInCtrl = (uint8_t)i32Tmp; - i32Tmp = ((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400; - u8XOCapOutCtrl = (uint8_t)i32Tmp; - /* Read register and clear fields to be written */ - u32RegVal = ANACTRL->XO32M_CTRL; - u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); - /* Configuration of 32 MHz XO output buffers */ -#if (XO_SLAVE_EN == 0) - u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); -#else - u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; -#endif - /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */ - u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT; - u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT; - /* Write back to register */ - ANACTRL->XO32M_CTRL = u32RegVal; -} - -void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, - int32_t pi32_32kfXtalPPcbParCappF_x100, - int32_t pi32_32kfXtalNPcbParCappF_x100) -{ - uint32_t u32XOTrimValue; - uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF; - int32_t iaXin_x4, ibXin, iaXout_x4, ibXout; - int32_t iXOCapInpF_x100, iXOCapOutpF_x100; - uint8_t u8XOCapInCtrl, u8XOCapOutCtrl; - uint32_t u32RegVal; - int32_t i32Tmp; - /* Get Cal values from Flash */ - u32XOTrimValue = GET_32KXO_TRIM(); - /* check validity and apply */ - if ((0UL != (u32XOTrimValue & 1UL)) && (0UL != ((u32XOTrimValue >> 15UL) & 1UL))) - { - /* These fields are 7 bits, unsigned */ - u8IECXinCapCal6pF = (uint8_t)((u32XOTrimValue >> 1UL) & 0x7fUL); - u8IECXinCapCal8pF = (uint8_t)((u32XOTrimValue >> 8UL) & 0x7fUL); - u8IECXoutCapCal6pF = (uint8_t)((u32XOTrimValue >> 16UL) & 0x7fUL); - u8IECXoutCapCal8pF = (uint8_t)((u32XOTrimValue >> 23UL) & 0x7fUL); - /* Linear fit coefficients calculation */ - iaXin_x4 = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF; - ibXin = (int)u8IECXinCapCal6pF - iaXin_x4 * 3; - iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF; - ibXout = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3; - } - else - { - iaXin_x4 = 16; // gain in LSB/pF - ibXin = 12; // offset in LSB - iaXout_x4 = 16; // gain in LSB/pF - ibXout = 11; // offset in LSB - } - - /* In & out load cap calculation with derating */ - iXOCapInpF_x100 = 2 * pi32_32kfXtalIecLoadpF_x100 - pi32_32kfXtalNPcbParCappF_x100 - 130; - iXOCapOutpF_x100 = 2 * pi32_32kfXtalIecLoadpF_x100 - pi32_32kfXtalPPcbParCappF_x100 - 41; - - /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */ - i32Tmp = ((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400; - u8XOCapInCtrl = (uint8_t)i32Tmp; - i32Tmp = ((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400; - u8XOCapOutCtrl = (uint8_t)i32Tmp; - - /* Read register and clear fields to be written */ - u32RegVal = PMC->XTAL32K; - u32RegVal &= ~(PMC_XTAL32K_CAPBANKIN_MASK | PMC_XTAL32K_CAPBANKOUT_MASK); - - /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */ - u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 23) << PMC_XTAL32K_CAPBANKIN_SHIFT; - u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 23) << PMC_XTAL32K_CAPBANKOUT_SHIFT; - - /* Write back to register */ - PMC->XTAL32K = u32RegVal; -} - -void POWER_SetXtal16mhzLdo(void) -{ - uint32_t temp; - const uint32_t u32Mask = - (ANACTRL_LDO_XO32M_VOUT_MASK | ANACTRL_LDO_XO32M_IBIAS_MASK | ANACTRL_LDO_XO32M_STABMODE_MASK); - - const uint32_t u32Value = - (ANACTRL_LDO_XO32M_VOUT(0x5) | ANACTRL_LDO_XO32M_IBIAS(0x2) | ANACTRL_LDO_XO32M_STABMODE(0x1)); - - /* Enable & set-up XTAL 32 MHz clock LDO */ - temp = ANACTRL->LDO_XO32M; - - if ((temp & u32Mask) != u32Value) - { - temp &= ~u32Mask; - - /* - * Enable the XTAL32M LDO - * Adjust the output voltage level, 0x5 for 1.1V - * Adjust the biasing current, 0x2 value - * Stability configuration, 0x1 default mode - */ - temp |= u32Value; - - ANACTRL->LDO_XO32M = temp; - - /* Delay for LDO to be up */ - // CLOCK_uDelay(20); - } - - /* Enable LDO XO32M */ - PMC->PDRUNCFGCLR0 = PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK; -} - -/*! - * @brief set BOD VBAT level. - * - * @param level BOD detect level - * @param hyst BoD Hysteresis control - * @param enBodVbatReset VBAT brown out detect reset - */ -void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset) -{ - uint32_t pmc_reset_ctrl; - /* BOD VBAT disable reset */ - pmc_reset_ctrl = - PMC->RESETCTRL & (~(PMC_RESETCTRL_BODVBATRESETENA_SECURE_MASK | PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_MASK)); - pmc_reset_ctrl |= (0x2UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_SHIFT) | - (0x2UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_SHIFT); - - PMC->RESETCTRL = pmc_reset_ctrl; - - PMC->BODVBAT = (PMC->BODVBAT & (~(PMC_BODVBAT_TRIGLVL_MASK | PMC_BODVBAT_HYST_MASK))) | PMC_BODVBAT_TRIGLVL(level) | - PMC_BODVBAT_HYST(hyst); - - /* BOD VBAT enable reset */ - if ((uint32_t)enBodVbatReset == 1UL) - { - pmc_reset_ctrl &= (~(PMC_RESETCTRL_BODVBATRESETENA_SECURE_MASK | PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_MASK)); - pmc_reset_ctrl |= (0x1UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_SHIFT) | - (0x1UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_SHIFT); - PMC->RESETCTRL = pmc_reset_ctrl; - } -} - -#if defined(PMC_BODCORE_TRIGLVL_MASK) -/*! - * @brief set BOD core level. - * - * @param level BOD detect level - * @param hyst BoD Hysteresis control - * @param enBodCoreReset core brown out detect reset - */ -void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset) -{ - uint32_t pmc_reset_ctrl; - /* BOD CORE disable reset */ - pmc_reset_ctrl = - PMC->RESETCTRL & (~(PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK | PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK)); - pmc_reset_ctrl |= - (0x2 << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT) | (0x2 << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT); - - PMC->RESETCTRL = pmc_reset_ctrl; - - PMC->BODCORE = (PMC->BODCORE & (~(PMC_BODCORE_TRIGLVL_MASK | PMC_BODCORE_HYST_MASK))) | PMC_BODCORE_TRIGLVL(level) | - PMC_BODCORE_HYST(hyst); - - /* BOD CORE enable reset */ - if (enBodCoreReset == 1) - { - pmc_reset_ctrl &= (~(PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK | PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK)); - pmc_reset_ctrl |= (0x1 << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT) | - (0x1 << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT); - PMC->RESETCTRL = pmc_reset_ctrl; - } -} -#endif - -/** - * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes. - * @param p_reset_cause : the device reset cause, according to the definition of power_device_reset_cause_t type. - * @param p_boot_mode : the device boot mode, according to the definition of power_device_boot_mode_t type. - * @param p_wakeupio_cause: the wake-up pin sources, according to the definition of register PMC->WAKEIOCAUSE[3:0]. - - * @return Nothing - * - * !!! IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA !!! - * !!! valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06) !!! - * !!! when FALLING EDGE DETECTION is enabled on wake-up pins: !!! - * - 1. p_wakeupio_cause is NOT ACCURATE - * - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when - * several wake-up sources are enabled during DEEP-POWER-DOWN - * (like enabling wake-up on RTC and Falling edge wake-up pins) - * - */ -void POWER_GetWakeUpCause(power_device_reset_cause_t *p_reset_cause, - power_device_boot_mode_t *p_boot_mode, - uint32_t *p_wakeupio_cause) -{ - uint32_t reset_cause_reg; - uint32_t boot_mode_reg; - -#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ - defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ - defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) - reset_cause_reg = (PMC->AOREG1) & 0x3FF0UL; -#else /* LPC55S69/28 */ - reset_cause_reg = (PMC->AOREG1) & 0x1FF0UL; -#endif - - /* - * Prioritize interrupts source with respect to their critical level - */ -#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ - defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ - defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) - if (0UL != (reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK)) - { /* Code Watchdog Reset */ - *p_reset_cause = kRESET_CAUSE_CDOGRESET; - *p_boot_mode = kBOOT_MODE_POWER_UP; - *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ - } - else -#endif - { - if (0UL != (reset_cause_reg & PMC_AOREG1_WDTRESET_MASK)) - { /* Watchdog Timer Reset */ - *p_reset_cause = kRESET_CAUSE_WDTRESET; - *p_boot_mode = kBOOT_MODE_POWER_UP; - *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ - } - else - { - if (0UL != (reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK)) - { /* ARM System Reset */ - *p_reset_cause = kRESET_CAUSE_ARMSYSTEMRESET; - *p_boot_mode = kBOOT_MODE_POWER_UP; - *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ - } - else - { - boot_mode_reg = (PMC->STATUS & PMC_STATUS_BOOTMODE_MASK) >> PMC_STATUS_BOOTMODE_SHIFT; - - if (boot_mode_reg == 0UL) /* POWER-UP: Power On Reset, Pin reset, Brown Out Detectors, Software Reset */ - { - *p_boot_mode = kBOOT_MODE_POWER_UP; /* All non wake-up from a Low Power mode */ - *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ - - /* - * Prioritise Reset causes, starting from the strongest (Power On Reset) - */ - if (0UL != (reset_cause_reg & PMC_AOREG1_POR_MASK)) - { /* Power On Reset */ - *p_reset_cause = kRESET_CAUSE_POR; - } - else - { - if (0UL != (reset_cause_reg & PMC_AOREG1_BODRESET_MASK)) - { /* Brown-out Detector reset (either BODVBAT or BODCORE) */ - *p_reset_cause = kRESET_CAUSE_BODRESET; - } - else - { - if (0UL != (reset_cause_reg & PMC_AOREG1_PADRESET_MASK)) - { /* Hardware Pin Reset */ - *p_reset_cause = kRESET_CAUSE_PADRESET; - } - else - { - if (0UL != (reset_cause_reg & PMC_AOREG1_SWRRESET_MASK)) - { /* Software triggered Reset */ - *p_reset_cause = kRESET_CAUSE_SWRRESET; - } - else - { /* Unknown Reset Cause */ - *p_reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC; - } - } - } - } - -#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ - defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ - defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) - /* Transfer the control of the 4 wake-up pins to IOCON (instead of the Power Management Controller - */ - PMC->WAKEUPIOCTRL = PMC->WAKEUPIOCTRL & (~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK); -#endif - } - else /* DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN */ - { - /* - * 1- First, save wakeup_io_cause register ... - */ - *p_wakeupio_cause = PMC->WAKEIOCAUSE; - - if (boot_mode_reg == 3UL) /* DEEP-POWER-DOWN */ - { - *p_boot_mode = kBOOT_MODE_LP_DEEP_POWER_DOWN; - - switch (((reset_cause_reg >> PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT) & 0x7UL)) - { - case 1: - *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO; - break; - case 2: - *p_reset_cause = kRESET_CAUSE_DPDRESET_RTC; - break; - case 3: - *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC; - break; - case 4: - *p_reset_cause = kRESET_CAUSE_DPDRESET_OSTIMER; - break; - case 5: - *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER; - break; - case 6: - *p_reset_cause = kRESET_CAUSE_DPDRESET_RTC_OSTIMER; - break; - case 7: - *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER; - break; - default: - /* Unknown Reset Cause */ - *p_reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC; - break; - } - -#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ - defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ - defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) - /* - * 2- Next, transfer the control of the 4 wake-up pins - * to IOCON (instead of the Power Management Controller) - */ - PMC->WAKEUPIOCTRL = PMC->WAKEUPIOCTRL & (~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK); -#endif - } - else /* DEEP-SLEEP and POWER-DOWN */ - { - *p_reset_cause = kRESET_CAUSE_NOT_RELEVANT; - - /* - * The control of the 4 wake-up pins is already in IOCON, - * so there is nothing special to do. - */ - - if (boot_mode_reg == 1UL) /* DEEP-SLEEP */ - { - *p_boot_mode = kBOOT_MODE_LP_DEEP_SLEEP; - } - else /* POWER-DOWN */ - { - *p_boot_mode = kBOOT_MODE_LP_POWER_DOWN; - - } /* if ( boot_mode_reg == 1 ) DEEP-SLEEP */ - - } /* if ( boot_mode == 3 ) DEEP-POWER-DOWN */ - - } /* if ( boot_mode == 0 ) POWER-UP */ - - } /* if ( reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK ) */ - - } /* if ( reset_cause_reg & PMC_AOREG1_WDTRESET_MASK ) */ - - } /* if ( reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK ) */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_power.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_power.h deleted file mode 100644 index 6b1c0f1fb42..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_power.h +++ /dev/null @@ -1,598 +0,0 @@ -/* - * Copyright 2017, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_POWER_H_ -#define _FSL_POWER_H_ - -#include "fsl_common.h" -#include "fsl_device_registers.h" -#include - -/*! - * @addtogroup power - * @{ - */ -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief power driver version 1.0.0. */ -#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) -/*@}*/ - -/* Power mode configuration API parameter */ -typedef enum _power_mode_config -{ - kPmu_Sleep = 0U, - kPmu_Deep_Sleep = 1U, - kPmu_PowerDown = 2U, - kPmu_Deep_PowerDown = 3U, -} power_mode_cfg_t; - -/** - * @brief Analog components power modes control during low power modes - */ -typedef enum pd_bits -{ - kPDRUNCFG_PD_DCDC = (1UL << 0), - kPDRUNCFG_PD_BIAS = (1UL << 1), - kPDRUNCFG_PD_BODCORE = (1UL << 2), - kPDRUNCFG_PD_BODVBAT = (1UL << 3), - kPDRUNCFG_PD_FRO1M = (1UL << 4), - kPDRUNCFG_PD_FRO192M = (1UL << 5), - kPDRUNCFG_PD_FRO32K = (1UL << 6), - kPDRUNCFG_PD_XTAL32K = (1UL << 7), - kPDRUNCFG_PD_XTAL32M = (1UL << 8), - kPDRUNCFG_PD_PLL0 = (1UL << 9), - kPDRUNCFG_PD_PLL1 = (1UL << 10), - kPDRUNCFG_PD_USB0_PHY = (1UL << 11), - kPDRUNCFG_PD_USB1_PHY = (1UL << 12), - kPDRUNCFG_PD_COMP = (1UL << 13), - kPDRUNCFG_PD_TEMPSENS = (1UL << 14), - kPDRUNCFG_PD_GPADC = (1UL << 15), - kPDRUNCFG_PD_LDOMEM = (1UL << 16), - kPDRUNCFG_PD_LDODEEPSLEEP = (1UL << 17), - kPDRUNCFG_PD_LDOUSBHS = (1UL << 18), - kPDRUNCFG_PD_LDOGPADC = (1UL << 19), - kPDRUNCFG_PD_LDOXO32M = (1UL << 20), - kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21), - kPDRUNCFG_PD_RNG = (1UL << 22), - kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23), - kPDRUNCFG_PD_ROM = (1UL << 24), - /* - This enum member has no practical meaning,it is used to avoid MISRA issue, - user should not trying to use it. - */ - kPDRUNCFG_ForceUnsigned = 0x80000000U, -} pd_bit_t; - -/** - * @brief BOD VBAT level - */ -typedef enum _power_bod_vbat_level -{ - kPOWER_BodVbatLevel1000mv = 0, /*!< Brown out detector VBAT level 1V */ - kPOWER_BodVbatLevel1100mv = 1, /*!< Brown out detector VBAT level 1.1V */ - kPOWER_BodVbatLevel1200mv = 2, /*!< Brown out detector VBAT level 1.2V */ - kPOWER_BodVbatLevel1300mv = 3, /*!< Brown out detector VBAT level 1.3V */ - kPOWER_BodVbatLevel1400mv = 4, /*!< Brown out detector VBAT level 1.4V */ - kPOWER_BodVbatLevel1500mv = 5, /*!< Brown out detector VBAT level 1.5V */ - kPOWER_BodVbatLevel1600mv = 6, /*!< Brown out detector VBAT level 1.6V */ - kPOWER_BodVbatLevel1650mv = 7, /*!< Brown out detector VBAT level 1.65V */ - kPOWER_BodVbatLevel1700mv = 8, /*!< Brown out detector VBAT level 1.7V */ - kPOWER_BodVbatLevel1750mv = 9, /*!< Brown out detector VBAT level 1.75V */ - kPOWER_BodVbatLevel1800mv = 10, /*!< Brown out detector VBAT level 1.8V */ - kPOWER_BodVbatLevel1900mv = 11, /*!< Brown out detector VBAT level 1.9V */ - kPOWER_BodVbatLevel2000mv = 12, /*!< Brown out detector VBAT level 2V */ - kPOWER_BodVbatLevel2100mv = 13, /*!< Brown out detector VBAT level 2.1V */ - kPOWER_BodVbatLevel2200mv = 14, /*!< Brown out detector VBAT level 2.2V */ - kPOWER_BodVbatLevel2300mv = 15, /*!< Brown out detector VBAT level 2.3V */ - kPOWER_BodVbatLevel2400mv = 16, /*!< Brown out detector VBAT level 2.4V */ - kPOWER_BodVbatLevel2500mv = 17, /*!< Brown out detector VBAT level 2.5V */ - kPOWER_BodVbatLevel2600mv = 18, /*!< Brown out detector VBAT level 2.6V */ - kPOWER_BodVbatLevel2700mv = 19, /*!< Brown out detector VBAT level 2.7V */ - kPOWER_BodVbatLevel2806mv = 20, /*!< Brown out detector VBAT level 2.806V */ - kPOWER_BodVbatLevel2900mv = 21, /*!< Brown out detector VBAT level 2.9V */ - kPOWER_BodVbatLevel3000mv = 22, /*!< Brown out detector VBAT level 3.0V */ - kPOWER_BodVbatLevel3100mv = 23, /*!< Brown out detector VBAT level 3.1V */ - kPOWER_BodVbatLevel3200mv = 24, /*!< Brown out detector VBAT level 3.2V */ - kPOWER_BodVbatLevel3300mv = 25, /*!< Brown out detector VBAT level 3.3V */ -} power_bod_vbat_level_t; - -/** - * @brief BOD Hysteresis control - */ -typedef enum _power_bod_hyst -{ - kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */ - kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */ - kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */ - kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */ -} power_bod_hyst_t; -/** - * @brief BOD core level - */ -typedef enum _power_bod_core_level -{ - kPOWER_BodCoreLevel600mv = 0, /*!< Brown out detector core level 600mV */ - kPOWER_BodCoreLevel650mv = 1, /*!< Brown out detector core level 650mV */ - kPOWER_BodCoreLevel700mv = 2, /*!< Brown out detector core level 700mV */ - kPOWER_BodCoreLevel750mv = 3, /*!< Brown out detector core level 750mV */ - kPOWER_BodCoreLevel800mv = 4, /*!< Brown out detector core level 800mV */ - kPOWER_BodCoreLevel850mv = 5, /*!< Brown out detector core level 850mV */ - kPOWER_BodCoreLevel900mv = 6, /*!< Brown out detector core level 900mV */ - kPOWER_BodCoreLevel950mv = 7, /*!< Brown out detector core level 950mV */ -} power_bod_core_level_t; - -/** - * @brief Device Reset Causes - */ -typedef enum _power_device_reset_cause -{ - kRESET_CAUSE_POR = 0UL, /*!< Power On Reset */ - kRESET_CAUSE_PADRESET = 1UL, /*!< Hardware Pin Reset */ - kRESET_CAUSE_BODRESET = 2UL, /*!< Brown-out Detector reset (either BODVBAT or BODCORE) */ - kRESET_CAUSE_ARMSYSTEMRESET = 3UL, /*!< ARM System Reset */ - kRESET_CAUSE_WDTRESET = 4UL, /*!< Watchdog Timer Reset */ - kRESET_CAUSE_SWRRESET = 5UL, /*!< Software Reset */ - kRESET_CAUSE_CDOGRESET = 6UL, /*!< Code Watchdog Reset */ - /* Reset causes in DEEP-POWER-DOWN low power mode */ - kRESET_CAUSE_DPDRESET_WAKEUPIO = 7UL, /*!< Any of the 4 wake-up pins */ - kRESET_CAUSE_DPDRESET_RTC = 8UL, /*!< Real Time Counter (RTC) */ - kRESET_CAUSE_DPDRESET_OSTIMER = 9UL, /*!< OS Event Timer (OSTIMER) */ - kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC = 10UL, /*!< Any of the 4 wake-up pins and RTC (it is not possible to distinguish - which of these 2 events occured first) */ - kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER = 11UL, /*!< Any of the 4 wake-up pins and OSTIMER (it is not possible to - distinguish which of these 2 events occured first) */ - kRESET_CAUSE_DPDRESET_RTC_OSTIMER = 12UL, /*!< Real Time Counter or OS Event Timer (it is not possible to - distinguish which of these 2 events occured first) */ - kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER = 13UL, /*!< Any of the 4 wake-up pins (it is not possible to distinguish - which of these 3 events occured first) */ - /* Miscallenous */ - kRESET_CAUSE_NOT_RELEVANT = - 14UL, /*!< No reset cause (for example, this code is used when waking up from DEEP-SLEEP low power mode) */ - kRESET_CAUSE_NOT_DETERMINISTIC = 15UL, /*!< Unknown Reset Cause. Should be treated like "Hardware Pin Reset" from an - application point of view. */ -} power_device_reset_cause_t; - -/** - * @brief Device Boot Modes - */ -typedef enum _power_device_boot_mode -{ - kBOOT_MODE_POWER_UP = - 0UL, /*!< All non Low Power Mode wake up (Power On Reset, Pin Reset, BoD Reset, ARM System Reset ... ) */ - kBOOT_MODE_LP_DEEP_SLEEP = 1UL, /*!< Wake up from DEEP-SLEEP Low Power mode */ - kBOOT_MODE_LP_POWER_DOWN = 2UL, /*!< Wake up from POWER-DOWN Low Power mode */ - kBOOT_MODE_LP_DEEP_POWER_DOWN = 4UL, /*!< Wake up from DEEP-POWER-DOWN Low Power mode */ -} power_device_boot_mode_t; - -/** - * @brief SRAM instances retention control during low power modes - */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 \ - (1UL << 0) /*!< Enable SRAMX_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 \ - (1UL << 1) /*!< Enable SRAMX_1 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 \ - (1UL << 2) /*!< Enable SRAMX_2 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 \ - (1UL << 3) /*!< Enable SRAMX_3 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM00 \ - (1UL << 4) /*!< Enable SRAM0_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM10 \ - (1UL << 6) /*!< Enable SRAM1_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM20 \ - (1UL << 7) /*!< Enable SRAM2_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_USB_HS \ - (1UL << 14) /*!< Enable SRAM USB HS retention when entering in Low power modes */ - -/** - * @brief Low Power Modes Wake up sources - */ -#define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/ -#define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */ -#define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */ -#define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */ -#define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */ -// reserved (1ULL << 23) -#define WAKEUP_ACMP (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -// reserved (1ULL << 25) -// reserved (1ULL << 26) -#define WAKEUP_USB0_NEEDCLK (1ULL << 27) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_USB0 (1ULL << 28) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ -// reserved (1ULL << 30) -// reserved (1ULL << 31) -#define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ -// reserved (1ULL << 39) -// reserved (1ULL << 40) -// reserved (1ULL << 41) -// reserved (1ULL << 42) -#define CAN0_INT0 (1ULL << 43) /*!< [SLEEP, ] */ -#define CAN1_INT0 (1ULL << 44) /*!< [SLEEP, ] */ -// reserved (1ULL << 45) -// reserved (1ULL << 46) -#define WAKEUP_USB1 (1ULL << 47) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_USB1_NEEDCLK (1ULL << 48) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */ -#define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SEC_VIO (1ULL << 53) -#define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */ -#define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */ -#define WAKEUP_PUF (1ULL << 56) /*!< [SLEEP, ] */ -// reserved (1ULL << 57) -#define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */ -//#define CDOG (1ULL << 60) !< [SLEEP, ] -// reserved (1ULL << 61) -// reserved (1ULL << 62) -#define WAKEUP_ALLWAKEUPIOS (1ULL << 63) /*!< [ , DEEP POWER DOWN] */ - -/** - * @brief Sleep Postpone - */ -#define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */ -#define LOWPOWER_HWWAKE_PERIPHERALS \ - (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause \ - peripheral clocking to wake up temporarily while the related status is asserted */ -#define LOWPOWER_HWWAKE_SDMA0 \ - (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA \ - completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ -#define LOWPOWER_HWWAKE_SDMA1 \ - (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA \ - completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ -#define LOWPOWER_HWWAKE_ENABLE_FRO192M \ - (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of \ - LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set */ - -#define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */ -#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */ -/** - * @brief Wake up I/O sources - */ -#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */ -#define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */ -#define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */ -#define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */ - -#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */ -#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */ -#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */ -#define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */ - -#define LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX 12 /*!< Pin P1( 1) */ -#define LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX 14 /*!< Pin P0(28) */ -#define LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX 16 /*!< Pin P1(18) */ -#define LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX 18 /*!< Pin P1(30) */ - -#define LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN 0 /*!< Wake up Pad is plain input */ -#define LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN 1 /*!< Wake up Pad is pull-down */ -#define LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP 2 /*!< Wake up Pad is pull-up */ -#define LOWPOWER_WAKEUPIOSRC_IO_MODE_REPEATER 3 /*!< Wake up Pad is in repeater */ - -#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX 8 /*!< Wake-up I/O 0 pull-up/down configuration index */ -#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX 9 /*!< Wake-up I/O 1 pull-up/down configuration index */ -#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX 10 /*!< Wake-up I/O 2 pull-up/down configuration index */ -#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX 11 /*!< Wake-up I/O 3 pull-up/down configuration index */ - -#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down mask */ -#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down mask */ -#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down mask */ -#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down mask */ - -#define LOWPOWER_WAKEUPIO_PULLDOWN 0 /*!< Select pull-down */ -#define LOWPOWER_WAKEUPIO_PULLUP 1 /*!< Select pull-up */ - -#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX \ - 12 /*!< Wake-up I/O 0 pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX \ - 13 /*!< Wake-up I/O 1 pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX \ - 14 /*!< Wake-up I/O 2 pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX \ - 15 /*!< Wake-up I/O 3 pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down disable/enable mask */ -#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down disable/enable mask */ -#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down disable/enable mask */ -#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down disable/enable mask */ - -#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX \ - (16) /*!< Wake-up I/O 0 use external pull-up/down disable/enable control index*/ -#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX \ - (17) /*!< Wake-up I/O 1 use external pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX \ - (18) /*!< Wake-up I/O 2 use external pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX \ - (19) /*!< Wake-up I/O 3 use external pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 use external pull-up/down \ - disable/enable mask, 0: disable, 1: enable */ -#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 use external pull-up/down \ - disable/enable mask, 0: disable, 1: enable */ -#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 use external pull-up/down \ - disable/enable mask, 0: disable, 1: enable */ -#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 use external pull-up/down \ - disable/enable mask, 0: disable, 1: enable */ - -#ifdef __cplusplus -extern "C" { -#endif -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral - * - * @param en peripheral for which to enable the PDRUNCFG bit - * @return none - */ -static inline void POWER_EnablePD(pd_bit_t en) -{ - /* PDRUNCFGSET */ - PMC->PDRUNCFGSET0 = (uint32_t)en; -} - -/*! - * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral - * - * @param en peripheral for which to disable the PDRUNCFG bit - * @return none - */ -static inline void POWER_DisablePD(pd_bit_t en) -{ - /* PDRUNCFGCLR */ - PMC->PDRUNCFGCLR0 = (uint32_t)en; -} - -/*! - * @brief set BOD VBAT level. - * - * @param level BOD detect level - * @param hyst BoD Hysteresis control - * @param enBodVbatReset VBAT brown out detect reset - */ -void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset); - -#if defined(PMC_BODCORE_TRIGLVL_MASK) -/*! - * @brief set BOD core level. - * - * @param level BOD detect level - * @param hyst BoD Hysteresis control - * @param enBodCoreReset core brown out detect reset - */ -void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset); -#endif - -/*! - * @brief API to enable deep sleep bit in the ARM Core. - * - * @return none - */ -static inline void POWER_EnableDeepSleep(void) -{ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; -} - -/*! - * @brief API to disable deep sleep bit in the ARM Core. - * - * @return none - */ -static inline void POWER_DisableDeepSleep(void) -{ - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; -} - -/** - * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event - * This MUST BE EXECUTED outside the Flash: - * either from ROM or from SRAM. The rest could stay in Flash. But, for consistency, it is - * preferable to have all functions defined in this file implemented in ROM. - * - * @return Nothing - */ -void POWER_CycleCpuAndFlash(void); - -/** - * @brief Configures and enters in DEEP-SLEEP low power mode - * @param exclude_from_pd: - * @param sram_retention_ctrl: - * @param wakeup_interrupts: - * @param hardware_wake_ctrl: - - * @return Nothing - * - * !!! IMPORTANT NOTES : - 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. - * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in - case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). - * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be - restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip - reset) reset) - */ -void POWER_EnterDeepSleep(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t hardware_wake_ctrl); - -/** - * @brief Configures and enters in POWERDOWN low power mode - * @param exclude_from_pd: - * @param sram_retention_ctrl: - * @param wakeup_interrupts: - * @param cpu_retention_ctrl: 0 = CPU retention is disable / 1 = CPU retention is enabled, all other values are - RESERVED. - - * @return Nothing - * - * !!! IMPORTANT NOTES : - 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. - * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in - case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). - * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be - restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance - containing the stack used to call this function WILL BE preserved during low power (via parameter - "sram_retention_ctrl") - * 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip - reset) reset) - */ - -void POWER_EnterPowerDown(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t cpu_retention_ctrl); - -/** - * @brief Configures and enters in DEEPPOWERDOWN low power mode - * @param exclude_from_pd: - * @param sram_retention_ctrl: - * @param wakeup_interrupts: - * @param wakeup_io_ctrl: - - * @return Nothing - * - * !!! IMPORTANT NOTES : - 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. - * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back if - DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be - restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip - reset) - */ -void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t wakeup_io_ctrl); - -/** - * @brief Configures and enters in SLEEP low power mode - * - * @return Nothing - */ -void POWER_EnterSleep(void); - -/*! - * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency. - * - * @param system_freq_hz - The desired frequency (in Hertz) at which the part would like to operate, - * note that the voltage and flash wait states should be set before changing frequency - * @return none - */ -void POWER_SetVoltageForFreq(uint32_t system_freq_hz); - -/** - * @brief Sets board-specific trim values for 16MHz XTAL - * @param pi32_16MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 - * @param pi32_16MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF - * becomes 120 - * @param pi32_16MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF - * becomes 120 - * @return none - * @note Following default Values can be used: - * pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 - * pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20 - * pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 - */ -extern void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, - int32_t pi32_16MfXtalPPcbParCappF_x100, - int32_t pi32_16MfXtalNPcbParCappF_x100); -/** - * @brief Sets board-specific trim values for 32kHz XTAL - * @param pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 - * @param pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF - becomes 120 - * @param pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF - becomes 120 - - * @return none - * @note Following default Values can be used: - * pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 - * pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40 - * pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 - */ -extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, - int32_t pi32_32kfXtalPPcbParCappF_x100, - int32_t pi32_32kfXtalNPcbParCappF_x100); -/** - * @brief Enables and sets LDO for 16MHz XTAL - * @return none - */ -extern void POWER_SetXtal16mhzLdo(void); - -/** - * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes. - * @param p_reset_cause : the device reset cause, according to the definition of power_device_reset_cause_t type. - * @param p_boot_mode : the device boot mode, according to the definition of power_device_boot_mode_t type. - * @param p_wakeupio_cause: the wake-up pin sources, according to the definition of register PMC->WAKEIOCAUSE[3:0]. - - * @return Nothing - * - * !!! IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA !!! - * !!! valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06) !!! - * !!! when FALLING EDGE DETECTION is enabled on wake-up pins: !!! - * - 1. p_wakeupio_cause is NOT ACCURATE - * - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when - * several wake-up sources are enabled during DEEP-POWER-DOWN - * (like enabling wake-up on RTC and Falling edge wake-up pins) - * - */ -void POWER_GetWakeUpCause(power_device_reset_cause_t *p_reset_cause, - power_device_boot_mode_t *p_boot_mode, - uint32_t *p_wakeupio_cause); -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* _FSL_POWER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_prince.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_prince.c deleted file mode 100644 index 63e4c278528..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_prince.c +++ /dev/null @@ -1,1096 +0,0 @@ -/* - * Copyright 2018 - 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_prince.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ - -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.prince" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -static secure_bool_t PRINCE_CheckerAlgorithm(uint32_t address, - uint32_t length, - prince_flags_t flag, - flash_config_t *flash_context) -{ - uint32_t temp_base = 0, temp_sr = 0, region_index = 0, contiguous_start_index = 0, contiguous_end_index = 32; - secure_bool_t is_prince_region_contiguous = kSECURE_TRUE; - uint8_t prince_iv_code[FLASH_FFR_IV_CODE_SIZE] = {0}; - - if (address >= flash_context->ffrConfig.ffrBlockBase) - { - /* If it is not in flash region, return true to allow erase/write operation. */ - return kSECURE_TRUE; - } - - /* Iterate for all PRINCE regions */ - for (region_index = (uint32_t)kPRINCE_Region0; region_index <= (uint32_t)kPRINCE_Region2; region_index++) - { - contiguous_start_index = 0; - contiguous_end_index = 32; - switch (region_index) - { - case (uint32_t)kPRINCE_Region0: - temp_base = PRINCE->BASE_ADDR0; - temp_sr = PRINCE->SR_ENABLE0; - break; - - case (uint32_t)kPRINCE_Region1: - temp_base = PRINCE->BASE_ADDR1; - temp_sr = PRINCE->SR_ENABLE1; - break; - - case (uint32_t)kPRINCE_Region2: - temp_base = PRINCE->BASE_ADDR2; - temp_sr = PRINCE->SR_ENABLE2; - break; - - default: - /* All the cases have been listed above, the default clause should not be reached. */ - break; - } - - if (((address >= temp_base) && - ((address + length) < (temp_base + (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 32U * 1024U)))) && - (temp_sr != 0U)) - { - /* Check if the mask is contiguous */ - secure_bool_t first_set_bit_found = kSECURE_FALSE; - secure_bool_t contiguous_end_found = kSECURE_FALSE; - for (uint32_t i = 0; i < 32U; i++) - { - if (0U != (temp_sr & (1UL << i))) - { - if (kSECURE_FALSE == first_set_bit_found) - { - first_set_bit_found = kSECURE_TRUE; - contiguous_start_index = i; - } - if (kSECURE_TRUE == contiguous_end_found) - { - is_prince_region_contiguous = kSECURE_FALSE; - break; - } - } - else - { - if ((kSECURE_TRUE == first_set_bit_found) && (kSECURE_FALSE == contiguous_end_found)) - { - contiguous_end_found = kSECURE_TRUE; - contiguous_end_index = i; - } - } - } - } - else - { - continue; /* No encryption enabled, continue with the next region checking. */ - } - - /* Check if the provided memory range covers all addresses defined in the SR mask */ - if ((kSECURE_TRUE == is_prince_region_contiguous) && - ((address <= (temp_base + (contiguous_start_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U)))) && - (((address + length) >= - (temp_base + (contiguous_end_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U))))) - { - /* In case of erase operation, invalidate the old PRINCE IV by regenerating the new one */ - if (kPRINCE_Flag_EraseCheck == flag) - { - /* Re-generate the PRINCE IV in case of erase operation */ - - /* Generate new IV code for the PRINCE region and store the new IV into the respective FFRs */ - if (kStatus_Success == - PRINCE_GenNewIV((prince_region_t)region_index, &prince_iv_code[0], true, flash_context)) - { - /* Store the new IV for the PRINCE region into PRINCE registers. */ - if (kStatus_Success == PRINCE_LoadIV((prince_region_t)region_index, &prince_iv_code[0])) - { - /* Encryption is enabled, all subregions are to be erased/written at once, IV successfully - * regenerated, return true to allow erase operation. */ - return kSECURE_TRUE; - } - } - /* Encryption is enabled, all subregions are to be erased/written at once but IV has not been correctly - * regenerated, return false to disable erase operation. */ - return kSECURE_FALSE; - } - - /* Encryption is enabled and all subregions are to be erased/written at once, return true to allow - * erase/write operation. */ - return kSECURE_TRUE; - } - /* The provided memory range does not cover all addresses defined in the SR mask. */ - else - { - /* Is the provided memory range outside the addresses defined by the SR mask? */ - if ((kSECURE_TRUE == is_prince_region_contiguous) && - ((((address + length) <= - (temp_base + (contiguous_start_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U)))) || - ((address >= (temp_base + (contiguous_end_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U)))))) - { - /* No encryption enabled for the provided memory range, true could be returned to allow erase/write - operation, but due to the same base address for all three prince regions on Niobe4Mini we should - continue with other regions (SR mask) checking. */ - continue; - } - else - { - /* Encryption is enabled but not all subregions are to be erased/written at once, return false to - * disable erase/write operation. */ - return kSECURE_FALSE; - } - } - } - return kSECURE_TRUE; -} -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Generate new IV code. - * - * This function generates new IV code and stores it into the persistent memory. - * Ensure about 800 bytes free space on the stack when calling this routine with the store parameter set to true! - * - * @param region PRINCE region index. - * @param iv_code IV code pointer used for storing the newly generated 52 bytes long IV code. - * @param store flag to allow storing the newly generated IV code into the persistent memory (FFR). - * @param flash_context pointer to the flash driver context structure. - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise, kStatus_Fail is also returned if the key code for the particular - * PRINCE region is not present in the keystore (though new IV code has been provided) - */ -status_t PRINCE_GenNewIV(prince_region_t region, uint8_t *iv_code, bool store, flash_config_t *flash_context) -{ - status_t status = kStatus_Fail; - uint8_t prince_iv_code[FLASH_FFR_IV_CODE_SIZE] = {0}; - uint8_t tempBuffer[FLASH_FFR_MAX_PAGE_SIZE] = {0}; - - /* Make sure PUF is started to allow key and IV code decryption and generation */ - if (true != PUF_IsGetKeyAllowed(PUF)) - { - return status; - } - - /* Generate new IV code for the PRINCE region */ - status = - PUF_SetIntrinsicKey(PUF, (puf_key_index_register_t)(uint32_t)((uint32_t)kPUF_KeyIndex_02 + (uint32_t)region), 8, - &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); - if ((kStatus_Success == status) && (true == store)) - { - /* Store the new IV code for the PRINCE region into the respective FFRs. */ - /* Create a new version of "Customer Field Programmable" (CFP) page. */ - if ((int32_t)kStatus_FLASH_Success == - FFR_GetCustomerInfieldData(flash_context, (uint8_t *)tempBuffer, 0, FLASH_FFR_MAX_PAGE_SIZE)) - { - /* Set the IV code in the page */ - (void)memcpy(&tempBuffer[offsetof(cfpa_cfg_info_t, ivCodePrinceRegion) + - (((uint32_t)region * sizeof(cfpa_cfg_iv_code_t))) + 4U], - &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); - - uint32_t *p32 = (uint32_t *)(uint32_t)tempBuffer; - uint32_t version = p32[1]; - if (version == 0xFFFFFFFFu) - { - return kStatus_Fail; - } - version++; - p32[1] = version; - - /* Program the page and enable firewall for "Customer field area" */ - if ((int32_t)kStatus_FLASH_Success == - FFR_InfieldPageWrite(flash_context, (uint8_t *)tempBuffer, FLASH_FFR_MAX_PAGE_SIZE)) - { - status = kStatus_Success; - } - else - { - status = kStatus_Fail; - } - } - } - if (status == kStatus_Success) - { - /* Pass the new IV code */ - (void)memcpy(iv_code, &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); - } - - return status; -} -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Load IV code. - * - * This function enables IV code loading into the PRINCE bus encryption engine. - * - * @param region PRINCE region index. - * @param iv_code IV code pointer used for passing the IV code. - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise - */ -status_t PRINCE_LoadIV(prince_region_t region, uint8_t *iv_code) -{ - status_t status = kStatus_Fail; - uint32_t keyIndex = (0x0Fu & (uint32_t)iv_code[1]); - uint8_t prince_iv[8] = {0}; - - /* Make sure PUF is started to allow key and IV code decryption and generation */ - if (true != PUF_IsGetKeyAllowed(PUF)) - { - return kStatus_Fail; - } - - /* Check if region number matches the PUF index value */ - if (((uint32_t)kPUF_KeyIndex_02 + (uint32_t)region) == (uint32_t)keyIndex) - { - /* Decrypt the IV */ - if (kStatus_Success == PUF_GetKey(PUF, iv_code, FLASH_FFR_IV_CODE_SIZE, &prince_iv[0], 8)) - { - /* Store the new IV for the PRINCE region into PRINCE registers. */ - (void)PRINCE_SetRegionIV(PRINCE, (prince_region_t)region, prince_iv); - status = kStatus_Success; - } - } - - return status; -} -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Allow encryption/decryption for specified address range. - * - * This function sets the encryption/decryption for specified address range. - * The SR mask value for the selected Prince region is calculated from provided - * start_address and length parameters. This calculated value is OR'ed with the - * actual SR mask value and stored into the PRINCE SR_ENABLE register and also - * into the persistent memory (FFR) to be used after the device reset. It is - * possible to define several nonadjacent encrypted areas within one Prince - * region when calling this function repeatedly. If the length parameter is set - * to 0, the SR mask value is set to 0 and thus the encryption/decryption for - * the whole selected Prince region is disabled. - * Ensure about 800 bytes free space on the stack when calling this routine! - * - * @param region PRINCE region index. - * @param start_address start address of the area to be encrypted/decrypted. - * @param length length of the area to be encrypted/decrypted. - * @param flash_context pointer to the flash driver context structure. - * @param regenerate_iv flag to allow IV code regenerating, storing into - * the persistent memory (FFR) and loading into the PRINCE engine - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise - */ -status_t PRINCE_SetEncryptForAddressRange( - prince_region_t region, uint32_t start_address, uint32_t length, flash_config_t *flash_context, bool regenerate_iv) -{ - status_t status = kStatus_Fail; - uint32_t srEnableRegister = 0; - uint32_t alignedStartAddress; - uint32_t prince_base_addr_ffr_word = 0; - uint32_t end_address = start_address + length; - uint32_t prince_region_base_address = 0; - uint8_t tempBuffer[FLASH_FFR_MAX_PAGE_SIZE] = {0}; - - /* Check input parameters. */ - if (NULL == flash_context) - { - return kStatus_Fail; - } - - /* Check the address range, region borders crossing. */ -#if (defined(FSL_PRINCE_DRIVER_LPC55S0x)) || (defined(FSL_PRINCE_DRIVER_LPC55S1x)) || \ - (defined(FSL_PRINCE_DRIVER_LPC55S2x)) || (defined(FSL_PRINCE_DRIVER_LPC55S3x)) - if ((start_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) || - ((start_address < FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) && (end_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR))) - { - return kStatus_Fail; - } -#endif -#if (defined(FSL_PRINCE_DRIVER_LPC55S6x)) - if ((start_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) || - ((start_address < 0x40000U) && (end_address > 0x40000U)) || - ((start_address < 0x80000U) && (end_address > 0x80000U)) || - ((start_address < FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) && (end_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR))) - { - return kStatus_Fail; - } -#endif - - if (true == regenerate_iv) - { - uint8_t prince_iv_code[FLASH_FFR_IV_CODE_SIZE] = {0}; - - /* Generate new IV code for the PRINCE region and store the new IV into the respective FFRs */ - status = PRINCE_GenNewIV((prince_region_t)region, &prince_iv_code[0], true, flash_context); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - /* Store the new IV for the PRINCE region into PRINCE registers. */ - status = PRINCE_LoadIV((prince_region_t)region, &prince_iv_code[0]); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - } - - alignedStartAddress = ALIGN_DOWN(start_address, (int32_t)FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024); - - uint32_t subregion = alignedStartAddress / (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U); - if (subregion < (32U)) - { - /* PRINCE_Region0 */ - prince_region_base_address = 0; - } - else if (subregion < (64U)) - { - /* PRINCE_Region1 */ - subregion = subregion - 32U; - prince_region_base_address = 0x40000; - } - else - { - /* PRINCE_Region2 */ - subregion = subregion - 64U; - prince_region_base_address = 0x80000; - } - - /* If length > 0 then srEnableRegister mask is set based on the alignedStartAddress and the length. - If the length is 0, srEnableRegister should be kept 0 (no subregion enabled). */ - if (length != 0U) - { - srEnableRegister = (1UL << subregion); - alignedStartAddress += (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U); - - while (alignedStartAddress < (start_address + length)) - { - subregion++; - srEnableRegister |= (1UL << subregion); - alignedStartAddress += (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U); - } - - uint32_t srEnableRegisterActual = 0; - (void)PRINCE_GetRegionSREnable(PRINCE, (prince_region_t)region, &srEnableRegisterActual); - srEnableRegister |= srEnableRegisterActual; - } - - /* Store BASE_ADDR into PRINCE register before storing the SR to avoid en/decryption triggering - from addresses being defined by current BASE_ADDR register content (could be 0 and the decryption - of actually executed code can be started causing the hardfault then). */ - status = PRINCE_SetRegionBaseAddress(PRINCE, (prince_region_t)region, prince_region_base_address); - if (kStatus_Success != status) - { - return status; - } - - /* Store SR into PRINCE register */ - status = PRINCE_SetRegionSREnable(PRINCE, (prince_region_t)region, srEnableRegister); - if (kStatus_Success != status) - { - return status; - } - - /* Store SR and BASE_ADDR into CMPA FFR */ - if (kStatus_Success == FFR_GetCustomerData(flash_context, (uint8_t *)&tempBuffer, 0, FLASH_FFR_MAX_PAGE_SIZE)) - { - /* Set the PRINCE_SR_X in the page */ - (void)memcpy((uint32_t *)(uintptr_t)&tempBuffer[offsetof(cmpa_cfg_info_t, princeSr) + - ((uint32_t)region * sizeof(uint32_t))], - &srEnableRegister, sizeof(uint32_t)); - /* Set the ADDRX_PRG in the page */ - (void)memcpy(&prince_base_addr_ffr_word, - (const uint32_t *)(uintptr_t)&tempBuffer[offsetof(cmpa_cfg_info_t, princeBaseAddr)], - sizeof(uint32_t)); - prince_base_addr_ffr_word &= - ~(((uint32_t)FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) << ((uint32_t)region * 4U)); - prince_base_addr_ffr_word |= (((prince_region_base_address >> PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT) & - FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) - << ((uint32_t)region * 4U)); - (void)memcpy((uint32_t *)(uintptr_t)&tempBuffer[offsetof(cmpa_cfg_info_t, princeBaseAddr)], - &prince_base_addr_ffr_word, sizeof(uint32_t)); - - /* Program the CMPA page, set seal_part parameter to false (used during development to avoid sealing the - * part) - */ - status = FFR_CustFactoryPageWrite(flash_context, (uint8_t *)tempBuffer, false); - } - - return status; -} -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -/*! - * @brief Gets the PRINCE Sub-Region Enable register. - * - * This function gets PRINCE SR_ENABLE register. - * - * @param base PRINCE peripheral address. - * @param region PRINCE region index. - * @param sr_enable Sub-Region Enable register pointer. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_GetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t *sr_enable) -{ - status_t status = kStatus_Success; - - switch (region) - { - case kPRINCE_Region0: - *sr_enable = base->SR_ENABLE0; - break; - - case kPRINCE_Region1: - *sr_enable = base->SR_ENABLE1; - break; - - case kPRINCE_Region2: - *sr_enable = base->SR_ENABLE2; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - return status; -} - -/*! - * @brief Gets the PRINCE region base address register. - * - * This function gets PRINCE BASE_ADDR register. - * - * @param base PRINCE peripheral address. - * @param region PRINCE region index. - * @param region_base_addr Region base address pointer. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_GetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t *region_base_addr) -{ - status_t status = kStatus_Success; - - switch (region) - { - case kPRINCE_Region0: - *region_base_addr = base->BASE_ADDR0; - break; - - case kPRINCE_Region1: - *region_base_addr = base->BASE_ADDR1; - break; - - case kPRINCE_Region2: - *region_base_addr = base->BASE_ADDR2; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - return status; -} - -/*! - * @brief Sets the PRINCE region IV. - * - * This function sets specified AES IV for the given region. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param iv 64-bit AES IV in little-endian byte order. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_SetRegionIV(PRINCE_Type *base, prince_region_t region, const uint8_t iv[8]) -{ - status_t status = kStatus_Fail; - volatile uint32_t *IVMsb_reg = NULL; - volatile uint32_t *IVLsb_reg = NULL; - - switch (region) - { - case kPRINCE_Region0: - IVLsb_reg = &base->IV_LSB0; - IVMsb_reg = &base->IV_MSB0; - break; - - case kPRINCE_Region1: - IVLsb_reg = &base->IV_LSB1; - IVMsb_reg = &base->IV_MSB1; - break; - - case kPRINCE_Region2: - IVLsb_reg = &base->IV_LSB2; - IVMsb_reg = &base->IV_MSB2; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - if (status != kStatus_InvalidArgument) - { - *IVLsb_reg = ((uint32_t *)(uintptr_t)iv)[0]; - *IVMsb_reg = ((uint32_t *)(uintptr_t)iv)[1]; - status = kStatus_Success; - } - - return status; -} - -/*! - * @brief Sets the PRINCE region base address. - * - * This function configures PRINCE region base address. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param region_base_addr Base Address for region. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_SetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t region_base_addr) -{ - status_t status = kStatus_Success; - - /* Check input parameters. */ -#if (defined(FSL_PRINCE_DRIVER_LPC55S0x)) || (defined(FSL_PRINCE_DRIVER_LPC55S1x)) || \ - (defined(FSL_PRINCE_DRIVER_LPC55S2x)) || (defined(FSL_PRINCE_DRIVER_LPC55S3x)) - if (region_base_addr > 0U) - { - return kStatus_InvalidArgument; - } -#endif -#if (defined(FSL_PRINCE_DRIVER_LPC55S6x)) - if (region_base_addr > 0x80000U) - { - return kStatus_InvalidArgument; - } -#endif - - switch (region) - { - case kPRINCE_Region0: - base->BASE_ADDR0 = region_base_addr; - break; - - case kPRINCE_Region1: - base->BASE_ADDR1 = region_base_addr; - break; - - case kPRINCE_Region2: - base->BASE_ADDR2 = region_base_addr; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - return status; -} - -/*! - * @brief Sets the PRINCE Sub-Region Enable register. - * - * This function configures PRINCE SR_ENABLE register. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param sr_enable Sub-Region Enable register value. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_SetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t sr_enable) -{ - status_t status = kStatus_Success; - - switch (region) - { - case kPRINCE_Region0: - base->SR_ENABLE0 = sr_enable; - break; - - case kPRINCE_Region1: - base->SR_ENABLE1 = sr_enable; - break; - - case kPRINCE_Region2: - base->SR_ENABLE2 = sr_enable; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - return status; -} - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Erases the flash sectors encompassed by parameters passed into function. - * - * This function erases the appropriate number of flash sectors based on the - * desired start address and length. It deals with the flash erase function - * complenentary to the standard erase API of the IAP1 driver. This implementation - * additionally checks if the whole encrypted PRINCE subregions are erased at once - * to avoid secrets revealing. The checker implementation is limited to one contiguous - * PRINCE-controlled memory area. - * - * @param config The pointer to the flash driver context structure. - * @param start The start address of the desired flash memory to be erased. - * The start address needs to be prince-sburegion-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words) - * to be erased. Must be prince-sburegion-size-aligned. - * @param key The value used to validate all flash erase APIs. - * - * @return #kStatus_FLASH_Success API was executed successfully. - * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @return #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. - * @return #kStatus_FLASH_AddressError The address is out of range. - * @return #kStatus_FLASH_EraseKeyError The API erase key is invalid. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @return #kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce Encrypted flash subregions are not erased at once. - */ -status_t PRINCE_FlashEraseWithChecker(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) -{ - /* Check input parameters. */ - if (NULL == config) - { - return kStatus_Fail; - } - /* Check that the whole encrypted region is erased at once. */ - if (kSECURE_TRUE != PRINCE_CheckerAlgorithm(start, lengthInBytes, kPRINCE_Flag_EraseCheck, config)) - { - return (int32_t)kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce; - } - return FLASH_Erase(config, start, lengthInBytes, key); -} - -/*! - * @brief Programs flash with data at locations passed in through parameters. - * - * This function programs the flash memory with the desired data for a given - * flash area as determined by the start address and the length. It deals with the - * flash program function complenentary to the standard program API of the IAP1 driver. - * This implementation additionally checks if the whole PRINCE subregions are - * programmed at once to avoid secrets revealing. The checker implementation is limited - * to one contiguous PRINCE-controlled memory area. - * - * @param config The pointer to the flash driver context structure. - * @param start The start address of the desired flash memory to be programmed. Must be - * prince-sburegion-aligned. - * @param src A pointer to the source buffer of data that is to be programmed - * into the flash. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be programmed. Must be prince-sburegion-size-aligned. - * - * @return #kStatus_FLASH_Success API was executed successfully. - * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @return #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @return #kStatus_FLASH_AddressError Address is out of range. - * @return #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @return #kStatus_FLASH_SizeError Encrypted flash subregions are not programmed at once. - */ -status_t PRINCE_FlashProgramWithChecker(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) -{ - /* Check input parameters. */ - if (NULL == config) - { - return kStatus_Fail; - } - /* Check that the whole encrypted subregions will be writen at once. */ - if (kSECURE_TRUE != PRINCE_CheckerAlgorithm(start, lengthInBytes, kPRINCE_Flag_WriteCheck, config)) - { - return (int32_t)kStatus_FLASH_SizeError; - } - return FLASH_Program(config, start, src, lengthInBytes); -} -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if defined(FSL_PRINCE_DRIVER_LPC55S3x) -static status_t PRINCE_CSS_generate_random(uint8_t *output, size_t outputByteLen); -static status_t PRINCE_CSS_check_key(uint8_t keyIdx, mcuxClCss_KeyProp_t *pKeyProp); -static status_t PRINCE_CSS_gen_iv_key(void); -static status_t PRINCE_CSS_enable(void); -static status_t PRINCE_CSS_calculate_iv(uint32_t *IvReg); - -/*! - * @brief Configures PRINCE setting. - * - * This function does the initial PRINCE configuration via ROM IAP API call. - * PRINCE_SR_x configuration for each region configuration is stored into FFR (CMPA). - * PRINCE IV erase counters (MCTR_INT_IV_CTRx) in CFPA are updated accordingly. - * - * Note: This function is expected to be called once in the device lifetime, - * typically during the initial device provisioning, since it is programming the CMPA pages in PFR flash. - * - * @param coreCtx The pointer to the ROM API driver context structure. - * @param config The pointer to the PRINCE driver configuration structure. - * - * @retval #kStatus_Success - * @retval #kStatus_CommandUnsupported - * @retval #kStatus_InvalidArgument - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed - * @retval #kStatusMemoryRangeInvalid - * @retval #kStatus_Fail - * @retval #kStatus_OutOfRange - * @retval #kStatus_SPI_BaudrateNotSupport - */ -status_t PRINCE_Configure(api_core_context_t *coreCtx, prince_prot_region_arg_t *config) -{ - /* Enable CSS and check keys */ - if (kStatus_Success != PRINCE_CSS_enable()) - { - return kStatus_Fail; - } - - return MEM_Config(coreCtx, (uint32_t *)config, kMemoryInternal); -} - -/*! - * @brief Configures PRINCE setting. - * - * This function is used to re-configure PRINCE IP based on configuration stored in FFR. - * This function also needs to be called after wake up from power-down mode to regenerate IV - * encryption key in CSS key store whose presence is necessary for correct PRINCE operation - * during erase and write operations to encrypted regions of internal flash memory - * (dependency for correct operation of MEM_Erase() and MEM_Write() after wake up from power-down mode). - * - * @param coreCtx The pointer to the ROM API driver context structure. - * - * @retval #kStatus_Success - * @retval #kStatus_Fail - */ -status_t PRINCE_Reconfigure(api_core_context_t *coreCtx) -{ - status_t status = kStatus_Fail; - uint64_t princeMask; - uint32_t IvReg[4] = {0}; - uint32_t ivEraseCounter[3]; - uint32_t srEnable[3]; - uint32_t uuid[4]; - flash_config_t flash_config; - uint32_t lockWord; - uint8_t lock[3]; - - /* Enable CSS and check keys */ - status = PRINCE_CSS_enable(); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - /* Set PRINCE mask value. */ - status = PRINCE_CSS_generate_random((uint8_t *)&princeMask, sizeof(princeMask)); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - PRINCE_SetMask(PRINCE, princeMask); - - /* Clean up Flash driver structure and Init*/ - memset(&flash_config, 0, sizeof(flash_config_t)); - if (FLASH_Init(&flash_config) != kStatus_Success) - { - return kStatus_Fail; - } - - /* FFR Init */ - if (FFR_Init(&flash_config) != kStatus_Success) - { - return kStatus_Fail; - } - - /* Get UUID from FFR */ - status = FFR_GetUUID(&flash_config, (uint8_t *)uuid); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - /* Check version of CFPA scratch first */ - uint32_t cfpaScratchVer = 0u; - memcpy(&cfpaScratchVer, (void *)(CFPA_SCRATCH_VER), sizeof(uint32_t)); - - /* Get CFPA version using FFR ROM API */ - uint32_t cfpaVer = 0u; - if (kStatus_Success != - FFR_GetCustomerInfieldData(&flash_config, (uint8_t *)&cfpaVer, CFPA_VER_OFFSET, sizeof(uint32_t))) - { - status = kStatus_Fail; - return status; - } - - /* Compare the version of CFPA scratch and version of CFPA returned by ROM API */ - if (cfpaScratchVer > cfpaVer) - { - /* Get PRINCE_IV_CTRs from CFPA scratch */ - memcpy(&ivEraseCounter, (void *)CFPA_SCRATCH_IV, sizeof(uint32_t) * PRINCE_REGION_COUNT); - } - else - { - /* Get PRINCE_IV_CTRs IVs from CFPA ping/pong page */ - status = FFR_GetCustomerInfieldData(&flash_config, (uint8_t *)ivEraseCounter, CFPA_PRINCE_IV_OFFSET, - sizeof(uint32_t) * PRINCE_REGION_COUNT); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - } - - /* Get PRINCE sub-region enable word from FFR */ - status = FFR_GetCustomerData(&flash_config, (uint8_t *)srEnable, CMPA_PRINCE_SR_OFFSET, - sizeof(uint32_t) * PRINCE_REGION_COUNT); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - /* Get PRINCE lock setting from FFR */ - status = FFR_GetCustomerData(&flash_config, (uint8_t *)&lockWord, CMPA_PRINCE_LOCK_OFFSET, sizeof(uint32_t)); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - lock[0] = (lockWord & PRINCE_BASE_ADDR_LOCK_REG0_MASK) >> PRINCE_BASE_ADDR_LOCK_REG0_SHIFT; - lock[1] = (lockWord & PRINCE_BASE_ADDR_LOCK_REG1_MASK) >> PRINCE_BASE_ADDR_LOCK_REG1_SHIFT; - lock[2] = (lockWord & PRINCE_BASE_ADDR_LOCK_REG2_MASK) >> PRINCE_BASE_ADDR_LOCK_REG2_SHIFT; - - /* Iterate for all internal PRINCE regions */ - for (prince_region_t region = kPRINCE_Region0; region <= kPRINCE_Region2; region++) - { - /* Set region base address. Should be always 0x0 on LPC55S36 */ - status = PRINCE_SetRegionBaseAddress(PRINCE, (prince_region_t)region, 0x0u); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - status = PRINCE_SetRegionSREnable(PRINCE, region, srEnable[region]); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - /* Prepare ivSeed for current region */ - IvReg[0] = uuid[0]; - IvReg[1] = uuid[1]; - IvReg[2] = uuid[2] ^ region; - IvReg[3] = ivEraseCounter[region]; - - /* Calculate IV as IvReg = AES_ECB_ENC(DUK_derived_key, {ctx_erase_counter, ctx_id}) */ - status = PRINCE_CSS_calculate_iv(IvReg); - if (status != kStatus_Success) - { - return kStatus_Fail; - } - - /* Load IV into PRINCE registers */ - status = PRINCE_SetRegionIV(PRINCE, (prince_region_t)region, (uint8_t *)IvReg); - if (status != kStatus_Success) - { - return kStatus_Fail; - } - - /* Lock region if required */ - if ((lock[region] == 0x1u) || (lock[region] == 0x2u) || (lock[region] == 0x3u)) - { - PRINCE_SetLock(PRINCE, (kPRINCE_Region0Lock << region)); - } - } - - /* Break the main loop in case that error occured during PRINCE configuration */ - if (status != kStatus_Success) - { - return kStatus_Fail; - } - - /* When ENC_ENABLE is set, reading from PRINCE-encrypted regions is disabled. */ - /* For LPC55S36, the ENC_ENABLE is self-cleared after programming memory. */ - PRINCE_EncryptDisable(PRINCE); - return status; -} - -static status_t PRINCE_CSS_generate_random(uint8_t *output, size_t outputByteLen) -{ - status_t status = kStatus_Fail; - - // PRNG needs to be initialized; this can be done by calling mcuxClCss_KeyDelete_Async - // (delete any key slot, can be empty) - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_KeyDelete_Async(18)); - // mcuxClCss_KeyDelete_Async is a flow-protected function: Check the protection token and the return value - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_KeyDelete_Async) != token) || (MCUXCLCSS_STATUS_OK_WAIT != result)) - return kStatus_Fail; // Expect that no error occurred, meaning that the mcuxClCss_KeyDelete_Async operation was - // started. - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - // Wait for operation to finish - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_WaitForOperation(MCUXCLCSS_ERROR_FLAGS_CLEAR)); - // mcuxClCss_WaitForOperation is a flow-protected function: Check the protection token and the return value - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_WaitForOperation) != token) || (MCUXCLCSS_STATUS_OK != result)) - return kStatus_Fail; // Expect that no error occurred, meaning that the mcuxClCss_WaitForOperation operation was - // started. - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_Prng_GetRandom(output, outputByteLen)); - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_Prng_GetRandom) != token) || (MCUXCLCSS_STATUS_OK != result)) - return kStatus_Fail; - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - status = kStatus_Success; - return status; -} - -static status_t PRINCE_CSS_check_key(uint8_t keyIdx, mcuxClCss_KeyProp_t *pKeyProp) -{ - /* Check if CSS required keys are available in CSS keystore */ - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, - mcuxClCss_GetKeyProperties(keyIdx, pKeyProp)); // Get key propertis from the CSS. - // mcuxClCss_GetKeyProperties is a flow-protected function: Check the protection token and the return value - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_GetKeyProperties) != token) || (MCUXCLCSS_STATUS_OK != result)) - return kStatus_Fail; - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - return kStatus_Success; -} - -static status_t PRINCE_CSS_gen_iv_key(void) -{ - /* The NXP_DIE_MEM_IV_ENC_SK is not loaded and needs to be regenerated (power-down wakeup) */ - /* Set KDF mask and key properties for NXP_DIE_MEM_IV_ENC_SK */ - SYSCON->CSS_KDF_MASK = SYSCON_CSS_KDF_MASK; - static const uint32_t ddata2[3] = {0x62032504, 0x72f04280, 0x87a2bbae}; - mcuxClCss_KeyProp_t keyProp; - /* Set key properties in structure */ - keyProp.word.value = CSS_CSS_KS2_ks2_uaes_MASK | CSS_CSS_KS2_ks2_fgp_MASK | CSS_CSS_KS2_ks2_kact_MASK; - status_t status = kStatus_Fail; - - /* Generate the key using CKDF */ - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN( - result, token, - mcuxClCss_Ckdf_Sp800108_Async((mcuxClCss_KeyIndex_t)0, (mcuxClCss_KeyIndex_t)NXP_DIE_MEM_IV_ENC_SK, keyProp, - (uint8_t const *)ddata2)); - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_Ckdf_Sp800108_Async) != token) && (MCUXCLCSS_STATUS_OK != result)) - { - return kStatus_Fail; - } - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - /* Wait for CKDF to finish */ - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_WaitForOperation(MCUXCLCSS_ERROR_FLAGS_CLEAR)); - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_WaitForOperation) == token) && (MCUXCLCSS_STATUS_OK == result)) - { - status = kStatus_Success; - } - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - return status; -} - -static status_t PRINCE_CSS_enable(void) -{ - mcuxClCss_KeyProp_t key_properties; - status_t status = kStatus_Fail; - - /* Enable CSS and related clocks */ - status = CSS_PowerDownWakeupInit(CSS); - if (status != kStatus_Success) - { - return kStatus_Fail; - } - - /* Check if MEM_ENC_SK key is available in CSS keystore */ - status = PRINCE_CSS_check_key(NXP_DIE_MEM_ENC_SK, &key_properties); - if (status != kStatus_Success || key_properties.bits.kactv != 1u) - { - return kStatus_Fail; - } - - /* Check if MEM_IV_ENC_SK key is available in CSS keystore */ - status = PRINCE_CSS_check_key(NXP_DIE_MEM_IV_ENC_SK, &key_properties); - if (status != kStatus_Success || key_properties.bits.kactv != 1u) - { - return PRINCE_CSS_gen_iv_key(); - } - - return kStatus_Success; -} - -static status_t PRINCE_CSS_calculate_iv(uint32_t *IvReg) -{ - mcuxClCss_CipherOption_t cipherOptions = {0}; - status_t status = kStatus_Fail; - - /* Configure CSS for AES ECB-128, using NXP_DIE_MEM_IV_ENC_SK key */ - cipherOptions.bits.cphmde = MCUXCLCSS_CIPHERPARAM_ALGORITHM_AES_ECB; - cipherOptions.bits.dcrpt = MCUXCLCSS_CIPHER_ENCRYPT; - cipherOptions.bits.extkey = MCUXCLCSS_CIPHER_INTERNAL_KEY; - - do - { - /* Calculate IV as IvReg = AES_ECB_ENC(NXP_DIE_MEM_IV_ENC_SK, ivSeed[127:0]) */ - /* ivSeed[127:0] = {UUID[96:0] ^ regionNumber[1:0], ivEraseCounter[31:0]} */ - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN( - result, token, - mcuxClCss_Cipher_Async(cipherOptions, (mcuxClCss_KeyIndex_t)NXP_DIE_MEM_IV_ENC_SK, NULL, - MCUXCLCSS_CIPHER_KEY_SIZE_AES_128, (uint8_t *)IvReg, MCUXCLCSS_CIPHER_BLOCK_SIZE_AES, - NULL, (uint8_t *)IvReg)); - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_Cipher_Async) != token) || (MCUXCLCSS_STATUS_OK_WAIT != result)) - break; - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN( - result, token, - mcuxClCss_WaitForOperation( - MCUXCLCSS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClCss_Enable_Async operation to complete. - // mcuxClCss_WaitForOperation is a flow-protected function: Check the protection token and the return value - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_WaitForOperation) == token) && (MCUXCLCSS_STATUS_OK == result)) - { - status = kStatus_Success; - } - MCUX_CSSL_FP_FUNCTION_CALL_END(); - } while (0); - - return status; -} -#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_prince.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_prince.h deleted file mode 100644 index 1d702ae499b..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_prince.h +++ /dev/null @@ -1,522 +0,0 @@ -/* - * Copyright 2018 - 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_PRINCE_H_ -#define _FSL_PRINCE_H_ - -#include "fsl_common.h" - -#include FFR_INCLUDE - -/*! - * @addtogroup prince - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief PRINCE driver version 2.5.0. - * - * Current version: 2.5.0 - * - * Change log: - * - Version 2.0.0 - * - Initial version. - * - Version 2.1.0 - * - Update for the A1 rev. of LPC55Sxx serie. - * - Version 2.2.0 - * - Add runtime checking of the A0 and A1 rev. of LPC55Sxx serie to support - * both silicone revisions. - * - Version 2.3.0 - * - Add support for LPC55S1x and LPC55S2x series - * - Version 2.3.0 - * - Fix MISRA-2012 issues. - * - Version 2.3.1 - * - Add support for LPC55S0x series - * - Version 2.3.2 - * - Fix documentation of enumeration. Extend PRINCE example. - * - Version 2.4.0 - * - Add support for LPC55S3x series - * - Version 2.5.0 - * - Add PRINCE_Config() and PRINCE_Reconfig() features. - */ -#define FSL_PRINCE_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) -/*@}*/ - -#if (defined(LPC55S04_SERIES) || defined(LPC55S06_SERIES)) -/* LPC55S0x series*/ -#define FSL_PRINCE_DRIVER_LPC55S0x -#include "fsl_puf.h" - -#elif (defined(LPC55S14_SERIES) || defined(LPC55S16_SERIES)) -/* LPC55S1x series*/ -#define FSL_PRINCE_DRIVER_LPC55S1x -#include "fsl_puf.h" - -#elif (defined(LPC55S26_SERIES) || defined(LPC55S28_SERIES)) -/* LPC55S2x series*/ -#define FSL_PRINCE_DRIVER_LPC55S2x -#include "fsl_puf.h" - -#elif (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || \ - defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES)) -/* LPC55S6x series*/ -#define FSL_PRINCE_DRIVER_LPC55S6x -#include "fsl_puf.h" - -#elif (defined(LPC55S36_SERIES)) -/* LPC55S3x series*/ -#define FSL_PRINCE_DRIVER_LPC55S3x -#define PRINCE PRINCE0 -#include "fsl_mem_interface.h" -#include "fsl_css.h" // Power Down Wake-up Init -#include // Interface to the entire nxpClCss component -#include // Code flow protection -#else -#error "No valid CPU defined!" -#endif - -#define FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB (8U) -#define FSL_PRINCE_DRIVER_MAX_FLASH_ADDR \ - ((uint32_t)FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES - (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 2U * 1024U)) - -#if !defined(ALIGN_DOWN) -#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) -#endif - -/*! @brief Secure status enumeration. */ -typedef enum _skboot_status -{ - kStatus_SKBOOT_Success = 0x5ac3c35au, /*!< PRINCE Success */ - kStatus_SKBOOT_Fail = 0xc35ac35au, /*!< PRINCE Fail */ - kStatus_SKBOOT_InvalidArgument = 0xc35a5ac3u, /*!< PRINCE Invalid argument */ - kStatus_SKBOOT_KeyStoreMarkerInvalid = 0xc3c35a5au, /*!< PRINCE Invalid marker */ -} skboot_status_t; - -/*! @brief Secure boolean enumeration. */ -typedef enum _secure_bool -{ - kSECURE_TRUE = 0xc33cc33cU, /*!< PRINCE true */ - kSECURE_FALSE = 0x5aa55aa5U, /*!< PRINCE false */ -} secure_bool_t; - -/*! @brief Prince region. */ -typedef enum _prince_region -{ - kPRINCE_Region0 = 0U, /*!< PRINCE region 0 */ - kPRINCE_Region1 = 1U, /*!< PRINCE region 1 */ - kPRINCE_Region2 = 2U, /*!< PRINCE region 2 */ -} prince_region_t; - -/*! @brief Prince lock. */ -typedef enum _prince_lock -{ - kPRINCE_Region0Lock = 1U, /*!< PRINCE region 0 lock */ - kPRINCE_Region1Lock = 2U, /*!< PRINCE region 1 lock */ - kPRINCE_Region2Lock = 4U, /*!< PRINCE region 2 lock */ - kPRINCE_MaskLock = 256U, /*!< PRINCE mask register lock */ -} prince_lock_t; - -/*! @brief Prince flag. */ -typedef enum _prince_flags -{ - kPRINCE_Flag_None = 0U, /*!< PRINCE Flag None */ - kPRINCE_Flag_EraseCheck = 1U, /*!< PRINCE Flag Erase check */ - kPRINCE_Flag_WriteCheck = 2U, /*!< PRINCE Flag Write check */ -} prince_flags_t; - -#if defined(FSL_PRINCE_DRIVER_LPC55S3x) -typedef struct -{ - uint32_t target_prince_region : 2; // 0/1/2 - uint32_t reserved : 22; - uint32_t tag : 8; // Fixed to 0x50 ('P') -} prince_prot_region_option_t; -typedef struct -{ - prince_prot_region_option_t option; - uint32_t start; - uint32_t length; -} prince_prot_region_arg_t; - -/*! @brief Prince fixed tag in prince_prot_region_option_t structure */ -#define PRINCE_TAG 0x50u -#define PRINCE_TAG_SHIFT 24u -/*! @brief Prince region count */ -#define PRINCE_REGION_COUNT 3u -/*! @brief Define for CSS key store indexes */ -#define NXP_DIE_MEM_ENC_SK 2u -#define NXP_DIE_MEM_IV_ENC_SK 4u -/*! @brief KDF mask and key properties for NXP_DIE_MEM_IV_ENC_SK (see SYSCON documentation)*/ -#define SYSCON_CSS_KDF_MASK 0x07000FCF -/*! @brief CFPA version and IV indexes (see Protected Flash Region table) */ -#define CFPA_VER_OFFSET 0x04 -#define CFPA_PRINCE_IV_OFFSET 0x14u -/*! @brief CMPA SR and lock indexes (see Protected Flash Region table) */ -#define CMPA_PRINCE_SR_OFFSET 0x24u -#define CMPA_PRINCE_LOCK_OFFSET 0x20u -/*! @brief CFPA scrach version and IV addresses (see Protected Flash Region table) */ -#define CFPA_SCRATCH_VER 0x3dc04 -#define CFPA_SCRATCH_IV 0x3dc14 -/*! @brief CMPA lock bit-field defines (see Protected Flash Region table) */ -#define PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (16u) -#define PRINCE_BASE_ADDR_LOCK_REG0_MASK (0x3u << PRINCE_BASE_ADDR_LOCK_REG0_SHIFT) -#define PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (18u) -#define PRINCE_BASE_ADDR_LOCK_REG1_MASK (0x3u << PRINCE_BASE_ADDR_LOCK_REG1_SHIFT) -#define PRINCE_BASE_ADDR_LOCK_REG2_SHIFT (20u) -#define PRINCE_BASE_ADDR_LOCK_REG2_MASK (0x3u << PRINCE_BASE_ADDR_LOCK_REG2_SHIFT) - -#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Enable data encryption. - * - * This function enables PRINCE on-the-fly data encryption. - * - * @param base PRINCE peripheral address. - */ -static inline void PRINCE_EncryptEnable(PRINCE_Type *base) -{ - base->ENC_ENABLE = 1u; -} - -/*! - * @brief Disable data encryption. - * - * This function disables PRINCE on-the-fly data encryption. - * - * @param base PRINCE peripheral address. - */ -static inline void PRINCE_EncryptDisable(PRINCE_Type *base) -{ - base->ENC_ENABLE = 0u; -} - -/*! - * @brief Is Enable data encryption. - * - * This function test if PRINCE on-the-fly data encryption is enabled. - * - * @param base PRINCE peripheral address. - * @return true if enabled, false if not - */ -static inline bool PRINCE_IsEncryptEnable(PRINCE_Type *base) -{ - return (base->ENC_ENABLE == 1u) ? true : false; -} - -/*! - * @brief Sets PRINCE data mask. - * - * This function sets the PRINCE mask that is used to mask decrypted data. - * - * @param base PRINCE peripheral address. - * @param mask 64-bit data mask value. - */ -static inline void PRINCE_SetMask(PRINCE_Type *base, uint64_t mask) -{ - base->MASK_LSB = (uint32_t)(mask & 0xffffffffu); - base->MASK_MSB = (uint32_t)(mask >> 32u); -} - -/*! - * @brief Locks access for specified region registers or data mask register. - * - * This function sets lock on specified region registers or mask register. - * - * @param base PRINCE peripheral address. - * @param lock registers to lock. This is a logical OR of members of the - * enumeration ::prince_lock_t - */ -static inline void PRINCE_SetLock(PRINCE_Type *base, uint32_t lock) -{ - base->LOCK = lock & 0x1ffu; -} - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Generate new IV code. - * - * This function generates new IV code and stores it into the persistent memory. - * Ensure about 800 bytes free space on the stack when calling this routine with the store parameter set to true! - * - * @param region PRINCE region index. - * @param iv_code IV code pointer used for storing the newly generated 52 bytes long IV code. - * @param store flag to allow storing the newly generated IV code into the persistent memory (FFR). - * @param flash_context pointer to the flash driver context structure. - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise, kStatus_Fail is also returned if the key code for the particular - * PRINCE region is not present in the keystore (though new IV code has been provided) - */ -status_t PRINCE_GenNewIV(prince_region_t region, uint8_t *iv_code, bool store, flash_config_t *flash_context); -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Load IV code. - * - * This function enables IV code loading into the PRINCE bus encryption engine. - * - * @param region PRINCE region index. - * @param iv_code IV code pointer used for passing the IV code. - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise - */ -status_t PRINCE_LoadIV(prince_region_t region, uint8_t *iv_code); -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Allow encryption/decryption for specified address range. - * - * This function sets the encryption/decryption for specified address range. - * The SR mask value for the selected Prince region is calculated from provided - * start_address and length parameters. This calculated value is OR'ed with the - * actual SR mask value and stored into the PRINCE SR_ENABLE register and also - * into the persistent memory (FFR) to be used after the device reset. It is - * possible to define several nonadjacent encrypted areas within one Prince - * region when calling this function repeatedly. If the length parameter is set - * to 0, the SR mask value is set to 0 and thus the encryption/decryption for - * the whole selected Prince region is disabled. - * Ensure about 800 bytes free space on the stack when calling this routine! - * - * @param region PRINCE region index. - * @param start_address start address of the area to be encrypted/decrypted. - * @param length length of the area to be encrypted/decrypted. - * @param flash_context pointer to the flash driver context structure. - * @param regenerate_iv flag to allow IV code regenerating, storing into - * the persistent memory (FFR) and loading into the PRINCE engine - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise - */ -status_t PRINCE_SetEncryptForAddressRange( - prince_region_t region, uint32_t start_address, uint32_t length, flash_config_t *flash_context, bool regenerate_iv); -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -/*! - * @brief Gets the PRINCE Sub-Region Enable register. - * - * This function gets PRINCE SR_ENABLE register. - * - * @param base PRINCE peripheral address. - * @param region PRINCE region index. - * @param sr_enable Sub-Region Enable register pointer. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_GetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t *sr_enable); - -/*! - * @brief Gets the PRINCE region base address register. - * - * This function gets PRINCE BASE_ADDR register. - * - * @param base PRINCE peripheral address. - * @param region PRINCE region index. - * @param region_base_addr Region base address pointer. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_GetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t *region_base_addr); - -/*! - * @brief Sets the PRINCE region IV. - * - * This function sets specified AES IV for the given region. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param iv 64-bit AES IV in little-endian byte order. - */ -status_t PRINCE_SetRegionIV(PRINCE_Type *base, prince_region_t region, const uint8_t iv[8]); - -/*! - * @brief Sets the PRINCE region base address. - * - * This function configures PRINCE region base address. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param region_base_addr Base Address for region. - */ -status_t PRINCE_SetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t region_base_addr); - -/*! - * @brief Sets the PRINCE Sub-Region Enable register. - * - * This function configures PRINCE SR_ENABLE register. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param sr_enable Sub-Region Enable register value. - */ -status_t PRINCE_SetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t sr_enable); - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Erases the flash sectors encompassed by parameters passed into function. - * - * This function erases the appropriate number of flash sectors based on the - * desired start address and length. It deals with the flash erase function - * complenentary to the standard erase API of the IAP1 driver. This implementation - * additionally checks if the whole encrypted PRINCE subregions are erased at once - * to avoid secrets revealing. The checker implementation is limited to one contiguous - * PRINCE-controlled memory area. - * - * @param config The pointer to the flash driver context structure. - * @param start The start address of the desired flash memory to be erased. - * The start address needs to be prince-sburegion-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words) - * to be erased. Must be prince-sburegion-size-aligned. - * @param key The value used to validate all flash erase APIs. - * - * @return #kStatus_FLASH_Success API was executed successfully. - * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @return #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. - * @return #kStatus_FLASH_AddressError The address is out of range. - * @return #kStatus_FLASH_EraseKeyError The API erase key is invalid. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @return #kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce Encrypted flash subregions are not erased at once. - */ -status_t PRINCE_FlashEraseWithChecker(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Programs flash with data at locations passed in through parameters. - * - * This function programs the flash memory with the desired data for a given - * flash area as determined by the start address and the length. It deals with the - * flash program function complenentary to the standard program API of the IAP1 driver. - * This implementation additionally checks if the whole PRINCE subregions are - * programmed at once to avoid secrets revealing. The checker implementation is limited - * to one contiguous PRINCE-controlled memory area. - * - * @param config The pointer to the flash driver context structure. - * @param start The start address of the desired flash memory to be programmed. Must be - * prince-sburegion-aligned. - * @param src A pointer to the source buffer of data that is to be programmed - * into the flash. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be programmed. Must be prince-sburegion-size-aligned. - * - * @return #kStatus_FLASH_Success API was executed successfully. - * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @return #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @return #kStatus_FLASH_AddressError Address is out of range. - * @return #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @return #kStatus_FLASH_SizeError Encrypted flash subregions are not programmed at once. - */ -status_t PRINCE_FlashProgramWithChecker(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Configures PRINCE setting. - * - * This function does the initial PRINCE configuration via ROM IAP API call. - * PRINCE_SR_x configuration for each region configuration is stored into FFR (CMPA). - * PRINCE IV erase counters (MCTR_INT_IV_CTRx) in CFPA are updated accordingly. - * - * Note: This function is expected to be called once in the device lifetime, - * typically during the initial device provisioning, since it is programming the CMPA pages in PFR flash. - * - * @param coreCtx The pointer to the ROM API driver context structure. - * @param config The pointer to the PRINCE driver configuration structure. - * - * @retval #kStatus_Success - * @retval #kStatus_CommandUnsupported - * @retval #kStatus_InvalidArgument - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed - * @retval #kStatusMemoryRangeInvalid - * @retval #kStatus_Fail - * @retval #kStatus_OutOfRange - * @retval #kStatus_SPI_BaudrateNotSupport - */ -status_t PRINCE_Configure(api_core_context_t *coreCtx, prince_prot_region_arg_t *config); -#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Reconfigures PRINCE setting. - * - * This function is used to re-configure PRINCE IP based on configuration stored in FFR. - * This function also needs to be called after wake up from power-down mode to regenerate IV - * encryption key in CSS key store whose presence is necessary for correct PRINCE operation - * during erase and write operations to encrypted regions of internal flash memory - * (dependency for correct operation of MEM_Erase() and MEM_Write() after wake up from power-down mode). - * - * @param coreCtx The pointer to the ROM API driver context structure. - * - * @retval #kStatus_Success - * @retval #kStatus_CommandUnsupported - * @retval #kStatus_InvalidArgument - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed - * @retval #kStatusMemoryRangeInvalid - * @retval #kStatus_Fail - * @retval #kStatus_OutOfRange - * @retval #kStatus_SPI_BaudrateNotSupport - */ -status_t PRINCE_Reconfigure(api_core_context_t *coreCtx); -#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if (defined(FSL_PRINCE_DRIVER_LPC55S0x)) || defined(FSL_PRINCE_DRIVER_LPC55S1x) || defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Gets the PRINCE Error status register. - * - * @param base PRINCE peripheral address. - * - * @return PRINCE Error status register - */ -static inline uint32_t PRINCE_GetErrorStatus(PRINCE_Type *base) -{ - return base->ERR; -} - -/*! - * @brief Clears the PRINCE Error status register. - * - * @param base PRINCE peripheral address. - */ -static inline void PRINCE_ClearErrorStatus(PRINCE_Type *base) -{ - base->ERR = 0U; -} -#endif /* defined(FSL_PRINCE_DRIVER_LPC55S0x) || defined(FSL_PRINCE_DRIVER_LPC55S1x) || \ - defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_PRINCE_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_puf.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_puf.c deleted file mode 100644 index d82299ed243..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_puf.c +++ /dev/null @@ -1,949 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_puf.h" -#include "fsl_clock.h" -#include "fsl_common.h" - -#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) -#include "fsl_reset.h" -#endif /* FSL_FEATURE_PUF_HAS_NO_RESET */ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.puf" -#endif - -/* RT6xx POWER CONTROL bit masks */ -#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) -#define PUF_PWRCTRL_CKDIS_MASK (0x4U) -#define PUF_PWRCTRL_RAMINIT_MASK (0x8U) -#define PUF_PWRCTRL_RAMPSWLARGEMA_MASK (0x10U) -#define PUF_PWRCTRL_RAMPSWLARGEMP_MASK (0x20U) -#define PUF_PWRCTRL_RAMPSWSMALLMA_MASK (0x40U) -#define PUF_PWRCTRL_RAMPSWSMALLMP_MASK (0x80U) -#endif - -#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) -#define DEFAULT_CKGATING 0x0u -#define PUF_ENABLE_MASK 0xFFFFFFFEu -#define PUF_ENABLE_CTRL 0x1u - -#else -static void puf_wait_usec(volatile uint32_t usec, uint32_t coreClockFrequencyMHz) -{ - SDK_DelayAtLeastUs(usec, coreClockFrequencyMHz * 1000000U); - - /* Instead of calling SDK_DelayAtLeastUs() implement delay loop here */ - // while (usec > 0U) - // { - // usec--; - - // number of MHz is directly number of core clocks to wait 1 usec. - // the while loop below is actually 4 clocks so divide by 4 for ~1 usec - // volatile uint32_t ticksCount = coreClockFrequencyMHz / 4u + 1u; - // while (0U != ticksCount--) - // { - // } - // } -} -#endif /* defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) */ - -static status_t puf_waitForInit(PUF_Type *base) -{ - status_t status = kStatus_Fail; - - /* wait until status register reads non-zero. All zero is not valid. It should be BUSY or OK or ERROR */ - while (0U == base->STAT) - { - } - - /* wait if busy */ - while ((base->STAT & PUF_STAT_BUSY_MASK) != 0U) - { - } - - /* return status */ - if (0U != (base->STAT & (PUF_STAT_SUCCESS_MASK | PUF_STAT_ERROR_MASK))) - { - status = kStatus_Success; - } - - return status; -} - -static void puf_powerOn(PUF_Type *base, puf_config_t *conf) -{ -#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) - /* RT6xxs */ - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK); - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_RAMINIT_MASK); -#elif defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* LPCXpresso55s16 */ - conf->puf_sram_base->CFG |= PUF_ENABLE_CTRL; - while (0U == (PUF_SRAM_CTRL_STATUS_READY_MASK & conf->puf_sram_base->STATUS)) - { - } -#else /* !FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ - /* LPCXpresso55s69 & LPCXpresso54S018 */ - base->PWRCTRL = PUF_PWRCTRL_RAMON_MASK; - while (0U == (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL)) - { - } -#endif /* FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ -} -/*! - * brief Powercycle PUF - * - * This function make powercycle of PUF. - * - * param base PUF peripheral base address - * param conf PUF configuration structure - * return Status of the powercycle operation. - */ -status_t PUF_PowerCycle(PUF_Type *base, puf_config_t *conf) -{ -#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) - /* RT6xxs */ - uint32_t coreClockFrequencyMHz = conf->coreClockFrequencyHz / 1000000u; - - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* disable RAM CK */ - - /* enter ASPS mode */ - base->PWRCTRL = (PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* SLEEP = 1 */ - base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK); /* enable RAM CK */ - base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | PUF_PWRCTRL_RAMPSWLARGEMP_MASK | - PUF_PWRCTRL_RAMPSWSMALLMA_MASK | PUF_PWRCTRL_RAMPSWSMALLMP_MASK); /* SLEEP=1, PSW*=1 */ - - /* Wait enough time to discharge fully */ - puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); - - /* write PWRCTRL=0x38. wait time > 1 us */ - base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | - PUF_PWRCTRL_RAMPSWLARGEMP_MASK); /* SLEEP=1. PSWSMALL*=0. PSWLARGE*=1. */ - puf_wait_usec(1, coreClockFrequencyMHz); - - /* write PWRCTRL=0x8. wait time > 1 us */ - base->PWRCTRL = PUF_PWRCTRL_RAMINIT_MASK; /* SLEEP=1. PSWSMALL*=0. PSWLARGE*=0 */ - puf_wait_usec(1, coreClockFrequencyMHz); - - base->PWRCTRL = (PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_RAMINIT_MASK); - - /* Generate INITN low pulse */ - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK); - base->PWRCTRL = PUF_PWRCTRL_RAM_ON_MASK; -#elif defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* LPCXpresso55s16 */ - conf->puf_sram_base->CFG &= PUF_ENABLE_MASK; -#else - /* LPCXpresso55s69 & LPCXpresso54S018 */ - base->PWRCTRL = 0x0u; - while (0U != (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL)) - { - } - - /* Wait enough time to discharge fully */ - puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); -#endif - -#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) - /* Reset PUF and reenable power to PUF SRAM */ - RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); -#endif /* FSL_TEATURE_PUF_HAS_NO_RESET */ - puf_powerOn(base, conf); - - return kStatus_Success; -} - -/*! - * brief Sets the default configuration of PUF - * - * This function initialize PUF config structure to default values. - * - * param conf PUF configuration structure - */ -void PUF_GetDefaultConfig(puf_config_t *conf) -{ -#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* LPCXpresso55s16 */ - conf->puf_sram_base = PUF_SRAM_CTRL; - - /* Default configuration after reset */ - conf->CKGATING = DEFAULT_CKGATING; /* PUF SRAM Clock Gating */ -#endif /* FSL_FEATURE_PUF_HAS_SRAM_CTRL */ - - conf->dischargeTimeMsec = KEYSTORE_PUF_DISCHARGE_TIME_FIRST_TRY_MS; - conf->coreClockFrequencyHz = CLOCK_GetFreq(kCLOCK_CoreSysClk); - - return; -} - -/*! - * brief Initialize PUF - * - * This function enables power to PUF block and waits until the block initializes. - * - * param base PUF peripheral base address - * param conf PUF configuration structure - * return Status of the init operation - */ -status_t PUF_Init(PUF_Type *base, puf_config_t *conf) -{ - status_t status = kStatus_Fail; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Puf); -#endif -#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) - /* Reset PUF */ - RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); -#endif /* FSL_FEATURE_PUF_HAS_NO_RESET */ - -#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* Set configuration for SRAM */ - conf->puf_sram_base->CFG |= PUF_SRAM_CTRL_CFG_CKGATING(conf->CKGATING); - -#endif /* FSL_FEATURE_PUF_HAS_SRAM_CTRL */ - - /* Enable power to PUF SRAM */ - puf_powerOn(base, conf); - - /* Wait for peripheral to become ready */ - status = puf_waitForInit(base); - - /* In case of error or enroll or start not allowed, do power-cycle */ - /* First try with shorter discharge time, if then it also fails try with longer time */ - /* conf->dischargeTimeMsec = KEYSTORE_PUF_DISCHARGE_TIME_FIRST_TRY_MS; */ - if ((status != kStatus_Success) || (0U == (base->ALLOW & (PUF_ALLOW_ALLOWENROLL_MASK | PUF_ALLOW_ALLOWSTART_MASK)))) - { - (void)PUF_PowerCycle(base, conf); - status = puf_waitForInit(base); - } - - /* In case of error or enroll or start not allowed, do power-cycle with worst discharge timing */ - if ((status != kStatus_Success) || (0U == (base->ALLOW & (PUF_ALLOW_ALLOWENROLL_MASK | PUF_ALLOW_ALLOWSTART_MASK)))) - { - conf->dischargeTimeMsec = KEYSTORE_PUF_DISCHARGE_TIME_MAX_MS; - (void)PUF_PowerCycle(base, conf); - status = puf_waitForInit(base); - } - - return status; -} - -/*! - * brief Denitialize PUF - * - * This function disables power to PUF SRAM and peripheral clock. - * - * param base PUF peripheral base address - * param conf PUF configuration structure - */ -void PUF_Deinit(PUF_Type *base, puf_config_t *conf) -{ -#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) - /* RT6xxs */ - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* disable RAM CK */ - - /* enter ASPS mode */ - base->PWRCTRL = (PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* SLEEP = 1 */ - base->PWRCTRL = PUF_PWRCTRL_RAMINIT_MASK; /* enable RAM CK */ - base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | PUF_PWRCTRL_RAMPSWLARGEMP_MASK | - PUF_PWRCTRL_RAMPSWSMALLMA_MASK | PUF_PWRCTRL_RAMPSWSMALLMP_MASK); /* SLEEP=1, PSW*=1 */ - puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); -#elif defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* LPCXpresso55s16 */ - conf->puf_sram_base = PUF_SRAM_CTRL; - conf->puf_sram_base->CFG &= PUF_ENABLE_MASK; -#else /* !FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ - /* LPCXpresso55s69 & LPCXpresso54S018 */ - base->PWRCTRL = 0x00u; - puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); -#endif - -#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) - RESET_SetPeripheralReset(kPUF_RST_SHIFT_RSTn); -#endif /* FSL_FEATURE_PUF_HAS_NO_RESET */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Puf); -#endif -} - -/*! - * brief Enroll PUF - * - * This function derives a digital fingerprint, generates the corresponding Activation Code (AC) - * and returns it to be stored in an NVM or a file. This step needs to be - * performed only once for each device. This function may be permanently disallowed by a fuse. - * - * param base PUF peripheral base address - * param[out] activationCode Word aligned address of the resulting activation code. - * param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. - * return Status of enroll operation. - */ -status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize) -{ - status_t status = kStatus_Fail; - uint32_t *activationCodeAligned = NULL; - register uint32_t temp32 = 0; - - /* check that activation code buffer size is at least 1192 bytes */ - if (activationCodeSize < PUF_ACTIVATION_CODE_SIZE) - { - return kStatus_InvalidArgument; - } - - /* only work with aligned activationCode */ - if (0U != (0x3u & (uintptr_t)activationCode)) - { - return kStatus_InvalidArgument; - } - - activationCodeAligned = (uint32_t *)(uintptr_t)activationCode; - - /* check if ENROLL is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWENROLL_MASK)) - { - return kStatus_EnrollNotAllowed; - } - - /* begin */ - base->CTRL = PUF_CTRL_ENROLL_MASK; - - /* check status */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* read out AC */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) - { - temp32 = base->CODEOUTPUT; - if (activationCodeSize >= sizeof(uint32_t)) - { - *activationCodeAligned = temp32; - activationCodeAligned++; - activationCodeSize -= sizeof(uint32_t); - } - } - } - - if (((base->STAT & PUF_STAT_SUCCESS_MASK) != 0U) && (activationCodeSize == 0U)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Start PUF - * - * The Activation Code generated during the Enroll operation is used to - * reconstruct the digital fingerprint. This needs to be done after every power-up - * and reset. - * - * param base PUF peripheral base address - * param activationCode Word aligned address of the input activation code. - * param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. - * return Status of start operation. - */ -status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize) -{ - status_t status = kStatus_Fail; - const uint32_t *activationCodeAligned = NULL; - register uint32_t temp32 = 0; - - /* check that activation code size is at least 1192 bytes */ - if (activationCodeSize < 1192U) - { - return kStatus_InvalidArgument; - } - - /* only work with aligned activationCode */ - if (0U != (0x3u & (uintptr_t)activationCode)) - { - return kStatus_InvalidArgument; - } - - activationCodeAligned = (const uint32_t *)(uintptr_t)activationCode; - - /* check if START is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSTART_MASK)) - { - return kStatus_StartNotAllowed; - } - - /* begin */ - base->CTRL = PUF_CTRL_START_MASK; - - /* check status */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy send AC */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_CODEINREQ_MASK & base->STAT)) - { - if (activationCodeSize >= sizeof(uint32_t)) - { - temp32 = *activationCodeAligned; - activationCodeAligned++; - activationCodeSize -= sizeof(uint32_t); - } - base->CODEINPUT = temp32; - } - } - - /* get status */ - if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Set intrinsic key - * - * The digital fingerprint generated during the Enroll/Start - * operations is used to generate a Key Code (KC) that defines a unique intrinsic - * key. This KC is returned to be stored in an NVM or a file. This operation - * needs to be done only once for each intrinsic key. - * Each time a Set Intrinsic Key operation is executed a new unique key is - * generated. - * - * param base PUF peripheral base address - * param keyIndex PUF key index register - * param keySize Size of the intrinsic key to generate in bytes. - * param[out] keyCode Word aligned address of the resulting key code. - * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * return Status of set intrinsic key operation. - */ -status_t PUF_SetIntrinsicKey( - PUF_Type *base, puf_key_index_register_t keyIndex, size_t keySize, uint8_t *keyCode, size_t keyCodeSize) -{ - status_t status = kStatus_Fail; - uint32_t *keyCodeAligned = NULL; - register uint32_t temp32 = 0; - - /* check if SET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSETKEY_MASK)) - { - return kStatus_Fail; - } - - /* only work with aligned keyCode */ - if (0U != (0x3u & (uintptr_t)keyCode)) - { - return kStatus_InvalidArgument; - } - - /* Check that keySize is in the correct range and that it is multiple of 8 */ - if ((keySize < (uint32_t)kPUF_KeySizeMin) || (keySize > (uint32_t)kPUF_KeySizeMax) || (0U != (keySize & 0x7U))) - { - return kStatus_InvalidArgument; - } - - /* check that keyCodeSize is correct for given keySize */ - if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize)) - { - return kStatus_InvalidArgument; - } - - if ((uint32_t)keyIndex > (uint32_t)kPUF_KeyIndexMax) - { - return kStatus_InvalidArgument; - } - - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - - /* program the key size and index */ - base->KEYSIZE = keySize >> 3; - base->KEYINDEX = (uint32_t)keyIndex; - - /* begin */ - base->CTRL = PUF_CTRL_GENERATEKEY_MASK; - - /* wait till command is accepted */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy read KC */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) - { - temp32 = base->CODEOUTPUT; - if (keyCodeSize >= sizeof(uint32_t)) - { - *keyCodeAligned = temp32; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - } - } - - /* get status */ - if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Set user key - * - * The digital fingerprint generated during the Enroll/Start - * operations and a user key (UK) provided as input are used to - * generate a Key Code (KC). This KC is sent returned to be stored - * in an NVM or a file. This operation needs to be done only once for each user key. - * - * param base PUF peripheral base address - * param keyIndex PUF key index register - * param userKey Word aligned address of input user key. - * param userKeySize Size of the input user key in bytes. - * param[out] keyCode Word aligned address of the resulting key code. - * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize). - * return Status of set user key operation. - */ -status_t PUF_SetUserKey(PUF_Type *base, - puf_key_index_register_t keyIndex, - const uint8_t *userKey, - size_t userKeySize, - uint8_t *keyCode, - size_t keyCodeSize) -{ - status_t status = kStatus_Fail; - uint32_t *keyCodeAligned = NULL; - const uint32_t *userKeyAligned = NULL; - register uint32_t temp32 = 0; - - /* check if SET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSETKEY_MASK)) - { - return kStatus_Fail; - } - - /* only work with aligned keyCode */ - if (0U != (0x3u & (uintptr_t)keyCode)) - { - return kStatus_InvalidArgument; - } - - /* Check that userKeySize is in the correct range and that it is multiple of 8 */ - if ((userKeySize < (uint32_t)kPUF_KeySizeMin) || (userKeySize > (uint32_t)kPUF_KeySizeMax) || - (0U != (userKeySize & 0x7U))) - { - return kStatus_InvalidArgument; - } - - /* check that keyCodeSize is correct for given userKeySize */ - if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize)) - { - return kStatus_InvalidArgument; - } - - if ((uint32_t)keyIndex > (uint32_t)kPUF_KeyIndexMax) - { - return kStatus_InvalidArgument; - } - - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - userKeyAligned = (const uint32_t *)(uintptr_t)userKey; - - /* program the key size and index */ - base->KEYSIZE = userKeySize >> 3; /* convert to 64-bit blocks */ - base->KEYINDEX = (uint32_t)keyIndex; - - /* We have to store the user key on index 0 swaped for HW bus */ - if (keyIndex == kPUF_KeyIndex_00) - { - userKeyAligned = userKeyAligned + (userKeySize / sizeof(uint32_t)); - } - - /* begin */ - base->CTRL = PUF_CTRL_SETKEY_MASK; - - /* wait till command is accepted */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy write UK and read KC */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_KEYINREQ_MASK & base->STAT)) - { - if (userKeySize >= sizeof(uint32_t)) - { -#if defined(LPC54S018_SERIES) - if (keyIndex == kPUF_KeyIndex_00) - { - userKeyAligned--; - temp32 = *userKeyAligned; - userKeySize -= sizeof(uint32_t); - } -#else - if (keyIndex == kPUF_KeyIndex_00) - { - userKeyAligned--; - temp32 = __REV(*userKeyAligned); - userKeySize--; - } -#endif /* defined(LPC54S018_SERIES) */ - else if (keyIndex != kPUF_KeyIndex_00) - { - temp32 = *userKeyAligned; - userKeyAligned++; - userKeySize -= sizeof(uint32_t); - } - else - { - /* Intentional empty */ - } - } - base->KEYINPUT = temp32; - } - - if (0U != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) - { - temp32 = base->CODEOUTPUT; - if (keyCodeSize >= sizeof(uint32_t)) - { - *keyCodeAligned = temp32; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - } - } - - /* get status */ - if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -static status_t puf_getHwKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize) -{ - status_t status = kStatus_Fail; - uint32_t *keyCodeAligned = NULL; - register uint32_t temp32 = 0; - - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - - /* begin */ - base->CTRL = PUF_CTRL_GETKEY_MASK; - - /* wait till command is accepted */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy send KC, key is reconstructed to HW bus */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_CODEINREQ_MASK & base->STAT)) - { - if (keyCodeSize >= sizeof(uint32_t)) - { - temp32 = *keyCodeAligned; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - base->CODEINPUT = temp32; - } - } - - /* get status */ - if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Reconstruct hw bus key from a key code - * - * The digital fingerprint generated during the Start operation and the KC - * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This - * operation needs to be done every time a key is needed. - * This function accepts only Key Codes created for PUF index register kPUF_KeyIndex_00. - * Such a key is output directly to a dedicated hardware bus. The reconstructed key is not exposed to system memory. - * - * param base PUF peripheral base address - * param keyCode Word aligned address of the input key code. - * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * param keySlot key slot to output on hw bus. Parameter is ignored on devices with less than two key slots. - * param keyMask key masking value. Shall be random for each POR/reset. Value does not have to be cryptographicaly - * secure. - * return Status of get key operation. - */ -status_t PUF_GetHwKey( - PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, puf_key_slot_t keySlot, uint32_t keyMask) -{ - status_t status = kStatus_Fail; - uint32_t keyIndex; - - /* check if GET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK)) - { - return kStatus_Fail; - } - - /* only work with aligned keyCode */ - if (0U != (0x3u & (uintptr_t)keyCode)) - { - return kStatus_Fail; - } - - /* check that keyCodeSize is at least PUF_MIN_KEY_CODE_SIZE */ - if (keyCodeSize < PUF_MIN_KEY_CODE_SIZE) - { - return kStatus_InvalidArgument; - } - - keyIndex = (uint32_t)(0x0Fu & (uint32_t)keyCode[1]); - - /* check the Key Code header byte 1. index must be zero for the hw key. */ - if (kPUF_KeyIndex_00 != (puf_key_index_register_t)keyIndex) - { - return kStatus_Fail; - } - -#if defined(PUF_KEYMASK_COUNT) && (PUF_KEYMASK_COUNT > 0) - volatile uint32_t *keyMask_reg = NULL; - uint32_t regVal = ((uint32_t)2U << ((uint32_t)2U * (uint32_t)keySlot)); - - switch (keySlot) - { - case kPUF_KeySlot0: - keyMask_reg = &base->KEYMASK[0]; - break; - - case kPUF_KeySlot1: - keyMask_reg = &base->KEYMASK[1]; - break; -#if (PUF_KEYMASK_COUNT > 2) - case kPUF_KeySlot2: - keyMask_reg = &base->KEYMASK[2]; - break; - - case kPUF_KeySlot3: - keyMask_reg = &base->KEYMASK[3]; - break; -#endif /* PUF_KEYMASK_COUNT > 2 */ - default: - status = kStatus_InvalidArgument; - break; - } -#endif /* PUF_KEYMASK_COUNT */ - - if (status != kStatus_InvalidArgument) - { -#if defined(PUF_KEYMASK_COUNT) && (PUF_KEYMASK_COUNT > 0) - base->KEYRESET = regVal; - base->KEYENABLE = regVal; - *keyMask_reg = keyMask; -#endif /* FSL_FEATURE_PUF_HAS_KEYSLOTS */ - - status = puf_getHwKey(base, keyCode, keyCodeSize); - -#if defined(FSL_FEATURE_PUF_HAS_SHIFT_STATUS) && (FSL_FEATURE_PUF_HAS_SHIFT_STATUS > 0) - size_t keyWords = 0; - - if (status == kStatus_Success) - { - /* if the corresponding shift count does not match, return fail anyway */ - keyWords = ((((size_t)keyCode[3]) * 2U) - 1u) << ((size_t)keySlot << 2U); - if (keyWords != ((0x0FUL << ((uint32_t)keySlot << 2U)) & base->SHIFT_STATUS)) - { - status = kStatus_Fail; - } - } -#elif defined(PUF_IDXBLK_SHIFT_IND_KEY0_MASK) && PUF_IDXBLK_SHIFT_IND_KEY0_MASK - size_t keyWords = 0; - - if (status == kStatus_Success) - { - /* if the corresponding shift count does not match, return fail anyway */ - keyWords = ((((size_t)keyCode[3]) * 2U) - 1u) << ((size_t)keySlot << 2U); - if (keyWords != ((0x0FUL << ((uint32_t)keySlot << 2U)) & base->IDXBLK_SHIFT)) - { - status = kStatus_Fail; - } - } -#endif /* FSL_FEATURE_PUF_HAS_SHIFT_STATUS || PUF_IDXBLK_SHIFT_IND_KEY0_MASK */ - } - - return status; -} - -/*! - * brief Checks if Get Key operation is allowed. - * - * This function returns true if get key operation is allowed. - * - * param base PUF peripheral base address - * return true if get key operation is allowed - */ -bool PUF_IsGetKeyAllowed(PUF_Type *base) -{ - /* check if GET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK)) - { - return false; - } - - return true; -} - -/*! - * brief Reconstruct key from a key code - * - * The digital fingerprint generated during the Start operation and the KC - * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This - * operation needs to be done every time a key is needed. - * This function accepts only Key Codes created for PUF index registers kPUF_KeyIndex_01 to kPUF_KeyIndex_15. - * - * param base PUF peripheral base address - * param keyCode Word aligned address of the input key code. - * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * param[out] key Word aligned address of output key. - * param keySize Size of the output key in bytes. - * return Status of get key operation. - */ -status_t PUF_GetKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize) -{ - status_t status = kStatus_Fail; - uint32_t *keyCodeAligned = NULL; - uint32_t *keyAligned = NULL; - uint32_t keyIndex; - register uint32_t temp32 = 0; - - /* check if GET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK)) - { - return kStatus_Fail; - } - - /* only work with aligned keyCode */ - if (0U != (0x3u & (uintptr_t)keyCode)) - { - return kStatus_Fail; - } - - /* only work with aligned key */ - if (0U != (0x3u & (uintptr_t)key)) - { - return kStatus_Fail; - } - - /* check that keyCodeSize is correct for given keySize */ - if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize)) - { - return kStatus_InvalidArgument; - } - - keyIndex = (0x0Fu & (uint32_t)keyCode[1]); - - /* check the Key Code header byte 1. index must be non-zero for the register key. */ - if (kPUF_KeyIndex_00 == (puf_key_index_register_t)keyIndex) - { - return kStatus_Fail; - } - - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - keyAligned = (uint32_t *)(uintptr_t)key; - - /* begin */ - base->CTRL = PUF_CTRL_GETKEY_MASK; - - /* wait till command is accepted */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy send KC, read key */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_CODEINREQ_MASK & base->STAT)) - { - temp32 = 0; - if (keyCodeSize >= sizeof(uint32_t)) - { - temp32 = *keyCodeAligned; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - base->CODEINPUT = temp32; - } - - if (0U != (PUF_STAT_KEYOUTAVAIL_MASK & base->STAT)) - { - keyIndex = base->KEYOUTINDEX; - temp32 = base->KEYOUTPUT; - if (keySize >= sizeof(uint32_t)) - { - *keyAligned = temp32; - keyAligned++; - keySize -= sizeof(uint32_t); - } - } - } - - /* get status */ - if ((keyIndex != 0U) && (0U != (base->STAT & PUF_STAT_SUCCESS_MASK))) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Zeroize PUF - * - * This function clears all PUF internal logic and puts the PUF to error state. - * - * param base PUF peripheral base address - * return Status of the zeroize operation. - */ -status_t PUF_Zeroize(PUF_Type *base) -{ - status_t status = kStatus_Fail; - - /* zeroize command is always allowed */ - base->CTRL = PUF_CTRL_ZEROIZE_MASK; - - /* check that command is accepted */ - if ((0U != (base->STAT & PUF_STAT_ERROR_MASK)) && (0U == base->ALLOW)) - { - status = kStatus_Success; - } - - return status; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_puf.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_puf.h deleted file mode 100644 index b8a5c51c856..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_puf.h +++ /dev/null @@ -1,335 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PUF_H_ -#define _PUF_H_ - -#include -#include - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! - * @addtogroup puf_driver - * @{ - */ -/*! @name Driver version */ -/*@{*/ -/*! @brief PUF driver version. Version 2.1.6. - * - * Current version: 2.1.6 - * - * Change log: - * - 2.0.0 - * - Initial version. - * - 2.0.1 - * - Fixed puf_wait_usec function optimization issue. - * - 2.0.2 - * - Add PUF configuration structure and support for PUF SRAM controller. - * Remove magic constants. - * - 2.0.3 - * - Fix MISRA C-2012 issue. - * - 2.1.0 - * - Align driver with PUF SRAM controller registers on LPCXpresso55s16. - * - Update initizalition logic . - * - 2.1.1 - * - Fix ARMGCC build warning . - * - 2.1.2 - * - Update: Add automatic big to little endian swap for user - * (pre-shared) keys destinated to secret hardware bus (PUF key index 0). - * - 2.1.3 - * - Fix MISRA C-2012 issue. - * - 2.1.4 - * - Replace register uint32_t ticksCount with volatile uint32_t ticksCount in puf_wait_usec() to prevent optimization - * out delay loop. - * - 2.1.5 - * - Use common SDK delay in puf_wait_usec() - * - 2.1.6 - * - Changed wait time in PUF_Init(), when initialization fails it will try PUF_Powercycle() with shorter time. If - * this shorter time will also fail, initialization will be tried with worst case time as before. - */ -#define FSL_PUF_DRIVER_VERSION (MAKE_VERSION(2, 1, 6)) -/*@}*/ - -typedef enum _puf_key_index_register -{ - kPUF_KeyIndex_00 = 0x00U, - kPUF_KeyIndex_01 = 0x01U, - kPUF_KeyIndex_02 = 0x02U, - kPUF_KeyIndex_03 = 0x03U, - kPUF_KeyIndex_04 = 0x04U, - kPUF_KeyIndex_05 = 0x05U, - kPUF_KeyIndex_06 = 0x06U, - kPUF_KeyIndex_07 = 0x07U, - kPUF_KeyIndex_08 = 0x08U, - kPUF_KeyIndex_09 = 0x09U, - kPUF_KeyIndex_10 = 0x0AU, - kPUF_KeyIndex_11 = 0x0BU, - kPUF_KeyIndex_12 = 0x0CU, - kPUF_KeyIndex_13 = 0x0DU, - kPUF_KeyIndex_14 = 0x0EU, - kPUF_KeyIndex_15 = 0x0FU, -} puf_key_index_register_t; - -typedef enum _puf_min_max -{ - kPUF_KeySizeMin = 8u, - kPUF_KeySizeMax = 512u, - kPUF_KeyIndexMax = kPUF_KeyIndex_15, -} puf_min_max_t; - -/*! @brief PUF key slot. */ -typedef enum _puf_key_slot -{ - kPUF_KeySlot0 = 0U, /*!< PUF key slot 0 */ - kPUF_KeySlot1 = 1U, /*!< PUF key slot 1 */ -#if defined(PUF_KEYMASK_COUNT) && (PUF_KEYMASK_COUNT > 2) - kPUF_KeySlot2 = 2U, /*!< PUF key slot 2 */ - kPUF_KeySlot3 = 3U, /*!< PUF key slot 3 */ -#endif -} puf_key_slot_t; - -typedef struct -{ - uint32_t dischargeTimeMsec; - uint32_t coreClockFrequencyHz; -#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* LPCXpresso55s16 */ - PUF_SRAM_CTRL_Type *puf_sram_base; - uint8_t CKGATING; -#endif /* FSL_FEATURE_PUF_HAS_SRAM_CTRL */ -} puf_config_t; -/*! @brief Get Key Code size in bytes from key size in bytes at compile time. */ -#define PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(x) ((160u + (((((x) << 3) + 255u) >> 8) << 8)) >> 3) -#define PUF_MIN_KEY_CODE_SIZE PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(8UL) -#define PUF_ACTIVATION_CODE_SIZE 1192U -#define KEYSTORE_PUF_DISCHARGE_TIME_FIRST_TRY_MS 50 -#define KEYSTORE_PUF_DISCHARGE_TIME_MAX_MS 400 - -/*! PUF status return codes. */ -enum -{ - kStatus_EnrollNotAllowed = MAKE_STATUS(kStatusGroup_PUF, 1), - kStatus_StartNotAllowed = MAKE_STATUS(kStatusGroup_PUF, 2) -}; - -/*! @} */ -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @brief Sets the default configuration of PUF - * - * This function initialize PUF config structure to default values. - * - * @param conf PUF configuration structure - */ -void PUF_GetDefaultConfig(puf_config_t *conf); - -/*! - * @brief Initialize PUF - * - * This function enables power to PUF block and waits until the block initializes. - * - * @param base PUF peripheral base address - * @param conf PUF configuration structure - * @return Status of the init operation - */ -status_t PUF_Init(PUF_Type *base, puf_config_t *conf); - -/*! - * @brief Denitialize PUF - * - * This function disables power to PUF SRAM and peripheral clock. - * - * @param base PUF peripheral base address - * @param conf PUF configuration structure - */ -void PUF_Deinit(PUF_Type *base, puf_config_t *conf); - -/*! - * @brief Enroll PUF - * - * This function derives a digital fingerprint, generates the corresponding Activation Code (AC) - * and returns it to be stored in an NVM or a file. This step needs to be - * performed only once for each device. This function may be permanently disallowed by a fuse. - * - * @param base PUF peripheral base address - * @param[out] activationCode Word aligned address of the resulting activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. - * @return Status of enroll operation. - */ -status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize); - -/*! - * @brief Start PUF - * - * The Activation Code generated during the Enroll operation is used to - * reconstruct the digital fingerprint. This needs to be done after every power-up - * and reset. - * - * @param base PUF peripheral base address - * @param activationCode Word aligned address of the input activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. - * @return Status of start operation. - */ -status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize); - -/*! - * @brief Set intrinsic key - * - * The digital fingerprint generated during the Enroll/Start - * operations is used to generate a Key Code (KC) that defines a unique intrinsic - * key. This KC is returned to be stored in an NVM or a file. This operation - * needs to be done only once for each intrinsic key. - * Each time a Set Intrinsic Key operation is executed a new unique key is - * generated. - * - * @param base PUF peripheral base address - * @param keyIndex PUF key index register - * @param keySize Size of the intrinsic key to generate in bytes. - * @param[out] keyCode Word aligned address of the resulting key code. - * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * @return Status of set intrinsic key operation. - */ -status_t PUF_SetIntrinsicKey( - PUF_Type *base, puf_key_index_register_t keyIndex, size_t keySize, uint8_t *keyCode, size_t keyCodeSize); - -/*! - * @brief Set user key - * - * The digital fingerprint generated during the Enroll/Start - * operations and a user key (UK) provided as input are used to - * generate a Key Code (KC). This KC is sent returned to be stored - * in an NVM or a file. This operation needs to be done only once for each user key. - * - * @param base PUF peripheral base address - * @param keyIndex PUF key index register - * @param userKey Word aligned address of input user key. - * @param userKeySize Size of the input user key in bytes. - * @param[out] keyCode Word aligned address of the resulting key code. - * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize). - * @return Status of set user key operation. - */ -status_t PUF_SetUserKey(PUF_Type *base, - puf_key_index_register_t keyIndex, - const uint8_t *userKey, - size_t userKeySize, - uint8_t *keyCode, - size_t keyCodeSize); - -/*! - * @brief Reconstruct key from a key code - * - * The digital fingerprint generated during the Start operation and the KC - * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This - * operation needs to be done every time a key is needed. - * This function accepts only Key Codes created for PUF index registers kPUF_KeyIndex_01 to kPUF_KeyIndex_15. - * - * @param base PUF peripheral base address - * @param keyCode Word aligned address of the input key code. - * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * @param[out] key Word aligned address of output key. - * @param keySize Size of the output key in bytes. - * @return Status of get key operation. - */ -status_t PUF_GetKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize); - -/*! - * @brief Reconstruct hw bus key from a key code - * - * The digital fingerprint generated during the Start operation and the KC - * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This - * operation needs to be done every time a key is needed. - * This function accepts only Key Codes created for PUF index register kPUF_KeyIndex_00. - * Such a key is output directly to a dedicated hardware bus. The reconstructed key is not exposed to system memory. - * - * @param base PUF peripheral base address - * @param keyCode Word aligned address of the input key code. - * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * @param keySlot key slot to output on hw bus. Parameter is ignored on devices with less than two key slots. - * @param keyMask key masking value. Shall be random for each POR/reset. Value does not have to be cryptographicaly - * secure. - * @return Status of get key operation. - */ -status_t PUF_GetHwKey( - PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, puf_key_slot_t keySlot, uint32_t keyMask); - -/*! - * @brief Zeroize PUF - * - * This function clears all PUF internal logic and puts the PUF to error state. - * - * @param base PUF peripheral base address - * @return Status of the zeroize operation. - */ -status_t PUF_Zeroize(PUF_Type *base); - -/*! - * @brief Checks if Get Key operation is allowed. - * - * This function returns true if get key operation is allowed. - * - * @param base PUF peripheral base address - * @return true if get key operation is allowed - */ -bool PUF_IsGetKeyAllowed(PUF_Type *base); - -#if defined(PUF_CFG_BLOCKKEYOUTPUT_MASK) && PUF_CFG_BLOCKKEYOUTPUT_MASK -static inline void PUF_BlockSetKey(PUF_Type *base) -{ - base->CFG |= PUF_CFG_BLOCKKEYOUTPUT_MASK; /* block set key */ -} -#endif /* PUF_CFG_BLOCKKEYOUTPUT_MASK */ - -#if defined(PUF_CFG_PUF_BLOCK_SET_KEY_MASK) && PUF_CFG_PUF_BLOCK_SET_KEY_MASK -static inline void PUF_BlockSetKey(PUF_Type *base) -{ - base->CFG |= PUF_CFG_PUF_BLOCK_SET_KEY_MASK; /* block set key */ -} -#endif /* PUF_CFG_PUF_BLOCK_SET_KEY_MASK */ - -#if defined(PUF_CFG_BLOCKENROLL_SETKEY_MASK) && PUF_CFG_BLOCKENROLL_SETKEY_MASK -static inline void PUF_BlockEnroll(PUF_Type *base) -{ - base->CFG |= PUF_CFG_BLOCKENROLL_SETKEY_MASK; /* block enroll */ -} -#endif /* PUF_CFG_BLOCKENROLL_SETKEY_MASK */ - -#if defined(PUF_CFG_PUF_BLOCK_ENROLL_MASK) && PUF_CFG_PUF_BLOCK_ENROLL_MASK -static inline void PUF_BlockEnroll(PUF_Type *base) -{ - base->CFG |= PUF_CFG_PUF_BLOCK_ENROLL_MASK; /* block enroll */ -} -#endif /* PUF_CFG_PUF_BLOCK_ENROLL_MASK */ - -/*! - * @brief Powercycle PUF - * - * This function make powercycle. - * - * @param base PUF peripheral base address - * @param conf PUF configuration structure - * @return Status of the powercycle operation. - */ -status_t PUF_PowerCycle(PUF_Type *base, puf_config_t *conf); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -#endif /* _PUF_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_reset.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_reset.c deleted file mode 100644 index 4326e0dae24..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_reset.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#include "fsl_reset.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.reset" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - -/*! - * brief Assert reset to peripheral. - * - * Asserts reset signal to specified peripheral module. - * - * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_SetPeripheralReset(reset_ip_name_t peripheral) -{ - const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; - const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); - const uint32_t bitMask = 1UL << bitPos; - - assert(bitPos < 32u); - - /* reset register is in SYSCON */ - /* set bit */ - SYSCON->PRESETCTRLSET[regIndex] = bitMask; - /* wait until it reads 0b1 */ - while (0u == (SYSCON->PRESETCTRLX[regIndex] & bitMask)) - { - } -} - -/*! - * brief Clear reset to peripheral. - * - * Clears reset signal to specified peripheral module, allows it to operate. - * - * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) -{ - const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; - const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); - const uint32_t bitMask = 1UL << bitPos; - - assert(bitPos < 32u); - - /* reset register is in SYSCON */ - - /* clear bit */ - SYSCON->PRESETCTRLCLR[regIndex] = bitMask; - /* wait until it reads 0b0 */ - while (bitMask == (SYSCON->PRESETCTRLX[regIndex] & bitMask)) - { - } -} - -/*! - * brief Reset peripheral module. - * - * Reset peripheral module. - * - * param peripheral Peripheral to reset. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_PeripheralReset(reset_ip_name_t peripheral) -{ - RESET_SetPeripheralReset(peripheral); - RESET_ClearPeripheralReset(peripheral); -} - -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_reset.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_reset.h deleted file mode 100644 index 3766c890cda..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_reset.h +++ /dev/null @@ -1,267 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_RESET_H_ -#define _FSL_RESET_H_ - -#include -#include -#include -#include -#include "fsl_device_registers.h" - -/*! - * @addtogroup reset - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief reset driver version 2.0.2. */ -#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -/*! - * @brief Enumeration for peripheral reset control bits - * - * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers - */ -typedef enum _SYSCON_RSTn -{ - kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */ - kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */ - kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */ - kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ - kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ - kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */ - kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ - kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ - kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ - kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ - kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ - kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ - kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ - kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ - kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */ - kMAILBOX_RST_SHIFT_RSTn = 0 | 26U, /**< Mailbox reset control */ - kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ - - kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ - kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */ - kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ - kMCAN_RST_SHIFT_RSTn = 65536 | 7U, /**< MCAN reset control */ - kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ - kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ - kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ - kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ - kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ - kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ - kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ - kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ - kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ - kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */ - kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0 Device reset control */ - kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */ - kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */ - kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */ - kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */ - - kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */ - kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */ - kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USBHS Host reset control */ - kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USBHS Device reset control */ - kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB RAM reset control */ - kUSB1_RST_SHIFT_RSTn = 131072 | 7U, /**< USBHS reset control */ - kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */ - kCDOG_RST_SHIFT_RSTn = 131072 | 11U, /**< Code Watchdog reset control */ - kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */ - kSYSCTL_RST_SHIFT_RSTn = 131072 | 15U, /**< SYSCTL reset control */ - kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */ - kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */ - kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */ - kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */ - kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */ - kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */ - kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */ - kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */ - kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */ - kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */ - kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */ - kGPIOSECINT_RST_SHIFT_RSTn = 131072 | 30U, /**< GPIO Secure int reset control */ -} SYSCON_RSTn_t; - -/** Array initializers with peripheral reset bits **/ -#define ADC_RSTS \ - { \ - kADC0_RST_SHIFT_RSTn \ - } /* Reset bits for ADC peripheral */ -#define MCAN_RSTS \ - { \ - kMCAN_RST_SHIFT_RSTn \ - } /* Reset bits for CAN peripheral */ -#define CRC_RSTS \ - { \ - kCRC_RST_SHIFT_RSTn \ - } /* Reset bits for CRC peripheral */ -#define CTIMER_RSTS \ - { \ - kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \ - kCTIMER4_RST_SHIFT_RSTn \ - } /* Reset bits for CTIMER peripheral */ -#define DMA_RSTS_N \ - { \ - kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \ - } /* Reset bits for DMA peripheral */ - -#define FLEXCOMM_RSTS \ - { \ - kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ - kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kHSLSPI_RST_SHIFT_RSTn \ - } /* Reset bits for FLEXCOMM peripheral */ -#define GINT_RSTS \ - { \ - kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ - } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ -#define GPIO_RSTS_N \ - { \ - kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn \ - } /* Reset bits for GPIO peripheral */ -#define INPUTMUX_RSTS \ - { \ - kMUX0_RST_SHIFT_RSTn \ - } /* Reset bits for INPUTMUX peripheral */ -#define IOCON_RSTS \ - { \ - kIOCON_RST_SHIFT_RSTn \ - } /* Reset bits for IOCON peripheral */ -#define FLASH_RSTS \ - { \ - kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ - } /* Reset bits for Flash peripheral */ -#define MRT_RSTS \ - { \ - kMRT_RST_SHIFT_RSTn \ - } /* Reset bits for MRT peripheral */ -#define PINT_RSTS \ - { \ - kPINT_RST_SHIFT_RSTn \ - } /* Reset bits for PINT peripheral */ -#define CDOG_RSTS \ - { \ - kCDOG_RST_SHIFT_RSTn \ - } /* Reset bits for CDOG peripheral */ -#define RNG_RSTS \ - { \ - kRNG_RST_SHIFT_RSTn \ - } /* Reset bits for RNG peripheral */ -#define SCT_RSTS \ - { \ - kSCT0_RST_SHIFT_RSTn \ - } /* Reset bits for SCT peripheral */ -#define USB0D_RST \ - { \ - kUSB0D_RST_SHIFT_RSTn \ - } /* Reset bits for USB0D peripheral */ -#define USB0HMR_RST \ - { \ - kUSB0HMR_RST_SHIFT_RSTn \ - } /* Reset bits for USB0HMR peripheral */ -#define USB0HSL_RST \ - { \ - kUSB0HSL_RST_SHIFT_RSTn \ - } /* Reset bits for USB0HSL peripheral */ -#define USB1H_RST \ - { \ - kUSB1H_RST_SHIFT_RSTn \ - } /* Reset bits for USB1H peripheral */ -#define USB1D_RST \ - { \ - kUSB1D_RST_SHIFT_RSTn \ - } /* Reset bits for USB1D peripheral */ -#define USB1RAM_RST \ - { \ - kUSB1RAM_RST_SHIFT_RSTn \ - } /* Reset bits for USB1RAM peripheral */ -#define UTICK_RSTS \ - { \ - kUTICK_RST_SHIFT_RSTn \ - } /* Reset bits for UTICK peripheral */ -#define WWDT_RSTS \ - { \ - kWWDT_RST_SHIFT_RSTn \ - } /* Reset bits for WWDT peripheral */ -#define PLU_RSTS_N \ - { \ - kPLULUT_RST_SHIFT_RSTn \ - } /* Reset bits for PLU peripheral */ -#define OSTIMER_RSTS \ - { \ - kOSTIMER0_RST_SHIFT_RSTn \ - } /* Reset bits for OSTIMER peripheral */ -#define CASPER_RSTS \ - { \ - kCASPER_RST_SHIFT_RSTn \ - } /* Reset bits for Casper peripheral */ -#define HASHCRYPT_RSTS \ - { \ - kHASHCRYPT_RST_SHIFT_RSTn \ - } /* Reset bits for Hashcrypt peripheral */ -#define PUF_RSTS \ - { \ - kPUF_RST_SHIFT_RSTn \ - } /* Reset bits for PUF peripheral */ -typedef SYSCON_RSTn_t reset_ip_name_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Assert reset to peripheral. - * - * Asserts reset signal to specified peripheral module. - * - * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_SetPeripheralReset(reset_ip_name_t peripheral); - -/*! - * @brief Clear reset to peripheral. - * - * Clears reset signal to specified peripheral module, allows it to operate. - * - * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); - -/*! - * @brief Reset peripheral module. - * - * Reset peripheral module. - * - * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_PeripheralReset(reset_ip_name_t peripheral); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_RESET_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rng.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rng.c deleted file mode 100644 index 1b2e9d4d61e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rng.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright 2017, 2019, 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_rng.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.rng_1" -#endif - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/******************************************************************************* - * Prototypes - *******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -static void rng_accumulateEntropy(RNG_Type *base) -{ - uint32_t minChiSq; - uint32_t maxChiSq; - - /* Steps to accumulate entropy, more info can be found in LPC55SXX UM*/ - - /* Select fourth clock on which to compute CHI SQUARE statistics*/ - base->COUNTER_CFG = (base->COUNTER_CFG & ~RNG_COUNTER_CFG_CLOCK_SEL_MASK) | RNG_COUNTER_CFG_CLOCK_SEL(4U); - - /* Activate CHI computing */ - base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(1U); - - /* Read min chi squared value, on power on should be higher than max chi squared value */ - minChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT); - - /* Read max chi squared value */ - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - - /* Wait until minChiSq decreases and become smaller than maxChiSq*/ - while (minChiSq > (maxChiSq - 1U)) - { - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - minChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT); - } -} - -/*! - * @brief Gets a entry data from the RNG. - * - * This function gets an entropy data from RNG. - */ -static uint32_t rng_readEntropy(RNG_Type *base) -{ - uint32_t data; - uint32_t refreshCnt, maxChiSq, tmpShift4x; - - /* Activate CHI computing */ - base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(1); - - /* Wait for refresh count become 31 to refill fresh entropy since last read of random number*/ - do - { - refreshCnt = ((base->COUNTER_VAL & RNG_COUNTER_VAL_REFRESH_CNT_MASK) >> RNG_COUNTER_VAL_REFRESH_CNT_SHIFT); - } while (refreshCnt < 31U); - - /* reading RANDOM_NUMBER register will reset refCnt to 0 */ - data = base->RANDOM_NUMBER; - - /* Perform CHI computing by checking max chi squared value */ - /* Wait until maxChiSq become smaller or equal than 4, then next random number can be read*/ - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - - while (maxChiSq > 4U) - { - /* Deactivate CHI computing to reset*/ - base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(0); - - /* read Shift4x register, if is less than 7 increment it and then start accumulating entropy again */ - tmpShift4x = ((base->COUNTER_CFG & RNG_COUNTER_CFG_SHIFT4X_MASK) >> RNG_COUNTER_CFG_SHIFT4X_SHIFT); - if (tmpShift4x < 7U) - { - tmpShift4x++; - base->COUNTER_CFG = - (base->COUNTER_CFG & ~RNG_COUNTER_CFG_SHIFT4X_MASK) | RNG_COUNTER_CFG_SHIFT4X(tmpShift4x); - } - rng_accumulateEntropy(base); - - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - } - - return data; -} - -void RNG_Init(RNG_Type *base) -{ - uint32_t maxChiSq, tmpShift4x; - - /* Clear ring oscilator disable bit*/ - PMC->PDRUNCFGCLR0 = PMC_PDRUNCFG0_PDEN_RNG_MASK; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Rng); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kRNG_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - - /* Turn on CHI Squared test */ - /* Activate CHI computing and wait until min chi squared become smaller than max chi squared */ - rng_accumulateEntropy(base); - - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - - /* When maxChiSq is bigger than 4 its assumed there is not enough entropy and previous steps are repeated */ - /* When maxChiSq is 4 or less initialization is complete and random number can be read*/ - while (maxChiSq > 4U) - { - /* Deactivate CHI coputing to reset*/ - base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(0); - - /* read Shift4x register, if is less than 7 increment it and then start accumulating entropy again */ - tmpShift4x = ((base->COUNTER_CFG & RNG_COUNTER_CFG_SHIFT4X_MASK) >> RNG_COUNTER_CFG_SHIFT4X_SHIFT); - if (tmpShift4x < 7U) - { - tmpShift4x++; - base->COUNTER_CFG = - (base->COUNTER_CFG & ~RNG_COUNTER_CFG_SHIFT4X_MASK) | RNG_COUNTER_CFG_SHIFT4X(tmpShift4x); - } - rng_accumulateEntropy(base); - - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - } -} - -void RNG_Deinit(RNG_Type *base) -{ - /* Set ring oscilator disable bit*/ - PMC->PDRUNCFGSET0 = PMC_PDRUNCFG0_PDEN_RNG_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kRNG_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Rng); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -status_t RNG_GetRandomData(RNG_Type *base, void *data, size_t dataSize) -{ - status_t result = kStatus_Fail; - uint32_t random32; - uint32_t randomSize; - uint8_t *pRandom; - uint8_t *pData = (uint8_t *)data; - uint32_t i; - - /* Check input parameters.*/ - if (!((base != NULL) && (data != NULL) && (dataSize != 0U))) - { - result = kStatus_InvalidArgument; - } - else - { - /* Check that ring oscilator is enabled */ - if (0U == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_RNG_MASK)) - { - do - { - /* Read Entropy.*/ - random32 = rng_readEntropy(base); - pRandom = (uint8_t *)&random32; - - if (dataSize < sizeof(random32)) - { - randomSize = dataSize; - } - else - { - randomSize = sizeof(random32); - } - - for (i = 0; i < randomSize; i++) - { - *pData++ = *pRandom++; - } - - dataSize -= randomSize; - } while (dataSize > 0U); - - result = kStatus_Success; - } - } - - return result; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rng.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rng.h deleted file mode 100644 index 38279cad7fa..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rng.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2017, 2019, 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_RNG_DRIVER_H_ -#define _FSL_RNG_DRIVER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup rng - * @{ - */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief RNG driver version. Version 2.0.3. - * - * Current version: 2.0.3 - * - * Change log: - * - Version 2.0.0 - * - Initial version - * - * - Version 2.0.1 - * - Fix MISRA C-2012 issue. - * - * - Version 2.0.2 - * - Add RESET_PeripheralReset function inside RNG_Init and RNG_Deinit functions. - * - * - Version 2.0.3 - * - Modified RNG_Init and RNG_GetRandomData functions, added rng_accumulateEntropy and rng_readEntropy functions. - * - These changes are reflecting recommended usage of RNG according to device UM. - */ -#define FSL_RNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initializes the RNG. - * - * This function initializes the RNG. - * When called, the RNG module and ring oscillator is enabled. - * - * @param base RNG base address - * @return If successful, returns the kStatus_RNG_Success. Otherwise, it returns an error. - */ -void RNG_Init(RNG_Type *base); - -/*! - * @brief Shuts down the RNG. - * - * This function shuts down the RNG. - * - * @param base RNG base address. - */ -void RNG_Deinit(RNG_Type *base); - -/*! - * @brief Gets random data. - * - * This function gets random data from the RNG. - * - * @param base RNG base address. - * @param data Pointer address used to store random data. - * @param dataSize Size of the buffer pointed by the data parameter. - * @return random data - */ -status_t RNG_GetRandomData(RNG_Type *base, void *data, size_t dataSize); - -/*! - * @brief Returns random 32-bit number. - * - * This function gets random number from the RNG. - * - * @param base RNG base address. - * @return random number - */ -static inline uint32_t RNG_GetRandomWord(RNG_Type *base) -{ - return base->RANDOM_NUMBER; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /*_FSL_RNG_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rtc.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rtc.c deleted file mode 100644 index b39370b6830..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rtc.c +++ /dev/null @@ -1,322 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_rtc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_rtc" -#endif - -#define SECONDS_IN_A_DAY (86400U) -#define SECONDS_IN_A_HOUR (3600U) -#define SECONDS_IN_A_MINUTE (60U) -#define DAYS_IN_A_YEAR (365U) -#define YEAR_RANGE_START (1970U) -#define YEAR_RANGE_END (2099U) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Check whether the date and time passed in is valid - * - * @param datetime Pointer to structure where the date and time details are stored - * - * @return Returns false if the date & time details are out of range; true if in range - */ -static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime); - -/*! - * @brief Convert time data from datetime to seconds - * - * @param datetime Pointer to datetime structure where the date and time details are stored - * - * @return The result of the conversion in seconds - */ -static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime); - -/*! - * @brief Convert time data from seconds to a datetime structure - * - * @param seconds Seconds value that needs to be converted to datetime format - * @param datetime Pointer to the datetime structure where the result of the conversion is stored - */ -static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime); - -/******************************************************************************* - * Code - ******************************************************************************/ -static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Check year, month, hour, minute, seconds */ - if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || - (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) - { - /* If not correct then error*/ - return false; - } - - /* Adjust the days in February for a leap year */ - if ((((datetime->year & 3U) == 0U) && (datetime->year % 100U != 0U)) || (datetime->year % 400U == 0U)) - { - daysPerMonth[2] = 29U; - } - - /* Check the validity of the day */ - if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) - { - return false; - } - - return true; -} - -static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Number of days from begin of the non Leap-year*/ - /* Number of days from begin of the non Leap-year*/ - uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; - uint32_t seconds; - - /* Compute number of days from 1970 till given year*/ - seconds = ((uint32_t)datetime->year - 1970U) * DAYS_IN_A_YEAR; - /* Add leap year days */ - seconds += (((uint32_t)datetime->year / 4U) - (1970U / 4U)); - /* Add number of days till given month*/ - seconds += monthDays[datetime->month]; - /* Add days in given month. We subtract the current day as it is - * represented in the hours, minutes and seconds field*/ - seconds += ((uint32_t)datetime->day - 1U); - /* For leap year if month less than or equal to Febraury, decrement day counter*/ - if (((datetime->year & 3U) == 0x00U) && (datetime->month <= 2U)) - { - seconds--; - } - - seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + - (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; - - return seconds; -} - -static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint8_t i; - uint16_t daysInYear; - uint32_t secondsRemaining; - uint32_t days; - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Start with the seconds value that is passed in to be converted to date time format */ - secondsRemaining = seconds; - - /* Calcuate the number of days, we add 1 for the current day which is represented in the - * hours and seconds field - */ - days = secondsRemaining / SECONDS_IN_A_DAY + 1U; - - /* Update seconds left*/ - secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; - - /* Calculate the datetime hour, minute and second fields */ - datetime->hour = (uint8_t)(secondsRemaining / SECONDS_IN_A_HOUR); - secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; - datetime->minute = (uint8_t)(secondsRemaining / 60U); - datetime->second = (uint8_t)(secondsRemaining % SECONDS_IN_A_MINUTE); - - /* Calculate year */ - daysInYear = DAYS_IN_A_YEAR; - datetime->year = YEAR_RANGE_START; - while (days > daysInYear) - { - /* Decrease day count by a year and increment year by 1 */ - days -= daysInYear; - datetime->year++; - - /* Adjust the number of days for a leap year */ - if ((datetime->year & 3U) != 0x00U) - { - daysInYear = DAYS_IN_A_YEAR; - } - else - { - daysInYear = DAYS_IN_A_YEAR + 1U; - } - } - - /* Adjust the days in February for a leap year */ - if ((datetime->year & 3U) == 0x00U) - { - daysPerMonth[2] = 29U; - } - - for (i = 1U; i <= 12U; i++) - { - if (days <= daysPerMonth[i]) - { - datetime->month = i; - break; - } - else - { - days -= daysPerMonth[i]; - } - } - - datetime->day = (uint8_t)days; -} - -/*! - * brief Ungate the RTC clock and enables the RTC oscillator. - * - * note This API should be called at the beginning of the application using the RTC driver. - * - * param base RTC peripheral base address - */ -void RTC_Init(RTC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the RTC peripheral clock */ - CLOCK_EnableClock(kCLOCK_Rtc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_RTC_HAS_NO_RESET) && FSL_FEATURE_RTC_HAS_NO_RESET) - RESET_PeripheralReset(kRTC_RST_SHIFT_RSTn); -#endif - /* Make sure the reset bit is cleared */ - base->CTRL &= ~RTC_CTRL_SWRESET_MASK; - -#if !(defined(FSL_FEATURE_RTC_HAS_NO_OSC_PD) && FSL_FEATURE_RTC_HAS_NO_OSC_PD) - /* Make sure the RTC OSC is powered up */ - base->CTRL &= ~RTC_CTRL_RTC_OSC_PD_MASK; -#endif -} - -/*! - * brief Set the RTC date and time according to the given time structure. - * - * The RTC counter must be stopped prior to calling this function as writes to the RTC - * seconds register will fail if the RTC counter is running. - * - * param base RTC peripheral base address - * param datetime Pointer to structure where the date and time details to set are stored - * - * return kStatus_Success: Success in setting the time and starting the RTC - * kStatus_InvalidArgument: Error because the datetime format is incorrect - */ -status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Return error if the time provided is not valid */ - if (!(RTC_CheckDatetimeFormat(datetime))) - { - return kStatus_InvalidArgument; - } - - /* Set time in seconds */ - base->COUNT = RTC_ConvertDatetimeToSeconds(datetime); - - return kStatus_Success; -} - -/*! - * brief Gets the RTC time and stores it in the given time structure. - * - * param base RTC peripheral base address - * param datetime Pointer to structure where the date and time details are stored. - */ -void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t seconds = 0; - - seconds = RTC_GetSecondsTimerCount(base); - RTC_ConvertSecondsToDatetime(seconds, datetime); -} - -/*! - * brief Set the RTC alarm time - * - * The function checks whether the specified alarm time is greater than the present - * time. If not, the function does not set the alarm and returns an error. - * - * param base RTC peripheral base address - * param alarmTime Pointer to structure where the alarm time is stored. - * - * return kStatus_Success: success in setting the RTC alarm - * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect - * kStatus_Fail: Error because the alarm time has already passed - */ -status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) -{ - assert(alarmTime != NULL); - - uint32_t alarmSeconds = 0; - uint32_t currSeconds = 0; - - /* Return error if the alarm time provided is not valid */ - if (!(RTC_CheckDatetimeFormat(alarmTime))) - { - return kStatus_InvalidArgument; - } - - alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime); - - /* Get the current time */ - currSeconds = RTC_GetSecondsTimerCount(base); - - /* Return error if the alarm time has passed */ - if (alarmSeconds < currSeconds) - { - return kStatus_Fail; - } - - /* Set alarm in seconds*/ - base->MATCH = alarmSeconds; - - return kStatus_Success; -} - -/*! - * brief Return the RTC alarm time. - * - * param base RTC peripheral base address - * param datetime Pointer to structure where the alarm date and time details are stored. - */ -void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t alarmSeconds = 0; - - /* Get alarm in seconds */ - alarmSeconds = base->MATCH; - - RTC_ConvertSecondsToDatetime(alarmSeconds, datetime); -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rtc.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rtc.h deleted file mode 100644 index a960d8baf7c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rtc.h +++ /dev/null @@ -1,493 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_RTC_H_ -#define _FSL_RTC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup rtc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*!< Version 2.1.2 */ -/*@}*/ - -/*! @brief List of RTC interrupts */ -typedef enum _rtc_interrupt_enable -{ - kRTC_AlarmInterruptEnable = RTC_CTRL_ALARMDPD_EN_MASK, /*!< Alarm interrupt.*/ - kRTC_WakeupInterruptEnable = RTC_CTRL_WAKEDPD_EN_MASK /*!< Wake-up interrupt.*/ -} rtc_interrupt_enable_t; - -/*! @brief List of RTC flags */ -typedef enum _rtc_status_flags -{ - kRTC_AlarmFlag = RTC_CTRL_ALARM1HZ_MASK, /*!< Alarm flag*/ - kRTC_WakeupFlag = RTC_CTRL_WAKE1KHZ_MASK /*!< 1kHz wake-up timer flag*/ -} rtc_status_flags_t; - -/*! @brief Structure is used to hold the date and time */ -typedef struct _rtc_datetime -{ - uint16_t year; /*!< Range from 1970 to 2099.*/ - uint8_t month; /*!< Range from 1 to 12.*/ - uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ - uint8_t hour; /*!< Range from 0 to 23.*/ - uint8_t minute; /*!< Range from 0 to 59.*/ - uint8_t second; /*!< Range from 0 to 59.*/ -} rtc_datetime_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Un-gate the RTC clock and enable the RTC oscillator. - * - * @note This API should be called at the beginning of the application using the RTC driver. - * - * @param base RTC peripheral base address - */ -void RTC_Init(RTC_Type *base); - -/*! - * @brief Stop the timer and gate the RTC clock - * - * @param base RTC peripheral base address - */ -static inline void RTC_Deinit(RTC_Type *base) -{ - /* Stop the RTC timer */ - base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the module clock */ - CLOCK_DisableClock(kCLOCK_Rtc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! @}*/ - -/*! - * @name Current Time & Alarm - * @{ - */ - -/*! - * @brief Set the RTC date and time according to the given time structure. - * - * The RTC counter must be stopped prior to calling this function as writes to the RTC - * seconds register will fail if the RTC counter is running. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the date and time details to set are stored - * - * @return kStatus_Success: Success in setting the time and starting the RTC - * kStatus_InvalidArgument: Error because the datetime format is incorrect - */ -status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime); - -/*! - * @brief Get the RTC time and stores it in the given time structure. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the date and time details are stored. - */ -void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime); - -/*! - * @brief Set the RTC alarm time - * - * The function checks whether the specified alarm time is greater than the present - * time. If not, the function does not set the alarm and returns an error. - * - * @param base RTC peripheral base address - * @param alarmTime Pointer to structure where the alarm time is stored. - * - * @return kStatus_Success: success in setting the RTC alarm - * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect - * kStatus_Fail: Error because the alarm time has already passed - */ -status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime); - -/*! - * @brief Return the RTC alarm time. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the alarm date and time details are stored. - */ -void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime); - -/*! @}*/ - -/*! - * @name RTC wake-up timer (1KHZ) Enable - * @{ - */ - -/*! - * @brief Enable the RTC wake-up timer (1KHZ). - * - * After calling this function, the RTC driver will use/un-use the RTC wake-up (1KHZ) at the same time. - * - * @param base RTC peripheral base address - * @param enable Use/Un-use the RTC wake-up timer. - * - true: Use RTC wake-up timer at the same time. - * - false: Un-use RTC wake-up timer, RTC only use the normal seconds timer by default. - */ -static inline void RTC_EnableWakeupTimer(RTC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK; - } - else - { - base->CTRL &= ~RTC_CTRL_RTC1KHZ_EN_MASK; - } -} - -/*! - * @brief Get the enabled status of the RTC wake-up timer (1KHZ). - * - - * @param base RTC peripheral base address - * - * @return The enabled status of RTC wake-up timer (1KHZ). - */ -static inline uint32_t RTC_GetEnabledWakeupTimer(RTC_Type *base) -{ - return (base->CTRL & RTC_CTRL_RTC1KHZ_EN_MASK); -} - -/*! @}*/ - -/*! - * @brief Set the RTC seconds timer (1HZ) MATCH value. - * - * @param base RTC peripheral base address - * @param matchValue The value to be set into the RTC MATCH register - */ -static inline void RTC_SetSecondsTimerMatch(RTC_Type *base, uint32_t matchValue) -{ - /* Set the start match value into the default RTC seconds timer (1HZ). */ - base->MATCH = matchValue; -} - -/*! - * @brief Read actual RTC seconds timer (1HZ) MATCH value. - * - * @param base RTC peripheral base address - * - * @return The actual RTC seconds timer (1HZ) MATCH value. - */ -static inline uint32_t RTC_GetSecondsTimerMatch(RTC_Type *base) -{ - /* Read the RTC default seconds timer (1HZ) MATCH value. */ - return base->MATCH; -} - -/*! - * @brief Set the RTC seconds timer (1HZ) COUNT value. - * - * @param base RTC peripheral base address - * @param countValue The value to be loaded into the RTC COUNT register - */ -static inline void RTC_SetSecondsTimerCount(RTC_Type *base, uint32_t countValue) -{ - /* Set the start count value into the default RTC seconds timer (1HZ). */ - base->COUNT = countValue; -} - -/*! - * @brief Read the actual RTC seconds timer (1HZ) COUNT value. - * - * @param base RTC peripheral base address - * - * @return The actual RTC seconds timer (1HZ) COUNT value. - */ -static inline uint32_t RTC_GetSecondsTimerCount(RTC_Type *base) -{ - uint32_t a, b; - - /* Follow the RF document to read the RTC default seconds timer (1HZ) counter value. */ - do - { - a = base->COUNT; - b = base->COUNT; - } while (a != b); - - return b; -} - -/*! - * @brief Enable the RTC wake-up timer (1KHZ) and set countdown value to the RTC WAKE register. - * - * @param base RTC peripheral base address - * @param wakeupValue The value to be loaded into the WAKE register in RTC wake-up timer (1KHZ). - */ -static inline void RTC_SetWakeupCount(RTC_Type *base, uint16_t wakeupValue) -{ - /* Use the RTC wake-up timer (1KHZ) */ - base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK; - - /* Set the start countdown value into the RTC WAKE register */ - base->WAKE = RTC_WAKE_VAL((uint32_t)wakeupValue); -} - -/*! - * @brief Read the actual value from the WAKE register value in RTC wake-up timer (1KHZ). - * - * @param base RTC peripheral base address - * - * @return The actual value of the WAKE register value in RTC wake-up timer (1HZ). - */ -static inline uint16_t RTC_GetWakeupCount(RTC_Type *base) -{ - /* Read current wake-up countdown value */ - return (uint16_t)((base->WAKE & RTC_WAKE_VAL_MASK) >> RTC_WAKE_VAL_SHIFT); -} - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enable the wake-up timer interrupt from deep power down mode. - * - * @param base RTC peripheral base address - * @param enable Enable/Disable wake-up timer interrupt from deep power down mode. - * - true: Enable wake-up timer interrupt from deep power down mode. - * - false: Disable wake-up timer interrupt from deep power down mode. - */ -static inline void RTC_EnableWakeUpTimerInterruptFromDPD(RTC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= RTC_CTRL_WAKEDPD_EN_MASK; - } - else - { - base->CTRL &= ~RTC_CTRL_WAKEDPD_EN_MASK; - } -} - -/*! - * @brief Enable the alarm timer interrupt from deep power down mode. - * - * @param base RTC peripheral base address - * @param enable Enable/Disable alarm timer interrupt from deep power down mode. - * - true: Enable alarm timer interrupt from deep power down mode. - * - false: Disable alarm timer interrupt from deep power down mode. - */ -static inline void RTC_EnableAlarmTimerInterruptFromDPD(RTC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= RTC_CTRL_ALARMDPD_EN_MASK; - } - else - { - base->CTRL &= ~RTC_CTRL_ALARMDPD_EN_MASK; - } -} - -/*! - * @brief Enables the selected RTC interrupts. - * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableAlarmTimerInterruptFromDPD - * and RTC_EnableWakeUpTimerInterruptFromDPD - * - * @param base RTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) -{ - uint32_t reg = base->CTRL; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK); - reg |= mask; - - base->CTRL = reg; -} - -/*! - * @brief Disables the selected RTC interrupts. - * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableAlarmTimerInterruptFromDPD - * and RTC_EnableWakeUpTimerInterruptFromDPD - * - * @param base RTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) -{ - uint32_t reg = base->CTRL; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK | mask); - - base->CTRL = reg; -} - -/*! - * @brief Get the enabled RTC interrupts. - * @deprecated Do not use this function. It will be deleted in next release version. - * - * @param base RTC peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) -{ - return (base->CTRL & (RTC_CTRL_ALARMDPD_EN_MASK | RTC_CTRL_WAKEDPD_EN_MASK)); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Get the RTC status flags - * - * @param base RTC peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::rtc_status_flags_t - */ -static inline uint32_t RTC_GetStatusFlags(RTC_Type *base) -{ - return (base->CTRL & (RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK)); -} - -/*! - * @brief Clear the RTC status flags. - * - * @param base RTC peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::rtc_status_flags_t - */ -static inline void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) -{ - uint32_t reg = base->CTRL; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK); - - /* Write 1 to the flags we wish to clear */ - reg |= mask; - - base->CTRL = reg; -} - -/*! @}*/ - -/*! - * @name Timer Enable - * @{ - */ - -/*! - * @brief Enable the RTC timer counter. - * - * After calling this function, the RTC inner counter increments once a second when only using the RTC seconds timer - * (1hz), while the RTC inner wake-up timer countdown once a millisecond when using RTC wake-up timer (1KHZ) at the - * same time. RTC timer contain two timers, one is the RTC normal seconds timer, the other one is the RTC wake-up timer, - * the RTC enable bit is the master switch for the whole RTC timer, so user can use the RTC seconds (1HZ) timer - * independly, but they can't use the RTC wake-up timer (1KHZ) independently. - * - * @param base RTC peripheral base address - * @param enable Enable/Disable RTC Timer counter. - * - true: Enable RTC Timer counter. - * - false: Disable RTC Timer counter. - */ -static inline void RTC_EnableTimer(RTC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= RTC_CTRL_RTC_EN_MASK; - } - else - { - base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; - } -} - -/*! - * @brief Starts the RTC time counter. - * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableTimer - * - * After calling this function, the timer counter increments once a second provided SR[TOF] or - * SR[TIF] are not set. - * - * @param base RTC peripheral base address - */ -static inline void RTC_StartTimer(RTC_Type *base) -{ - base->CTRL |= RTC_CTRL_RTC_EN_MASK; -} - -/*! - * @brief Stops the RTC time counter. - * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableTimer - * - * RTC's seconds register can be written to only when the timer is stopped. - * - * @param base RTC peripheral base address - */ -static inline void RTC_StopTimer(RTC_Type *base) -{ - base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; -} - -/*! @}*/ - -/*! - * @brief Perform a software reset on the RTC module. - * - * This resets all RTC registers to their reset value. The bit is cleared by software explicitly clearing it. - * - * @param base RTC peripheral base address - */ -static inline void RTC_Reset(RTC_Type *base) -{ - base->CTRL |= RTC_CTRL_SWRESET_MASK; - base->CTRL &= ~RTC_CTRL_SWRESET_MASK; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_RTC_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sctimer.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sctimer.c deleted file mode 100644 index 4208097a8b9..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sctimer.c +++ /dev/null @@ -1,791 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sctimer.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.sctimer" -#endif - -/*! @brief Typedef for interrupt handler. */ -typedef void (*sctimer_isr_t)(SCT_Type *base); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base SCTimer peripheral base address - * - * @return The SCTimer instance - */ -static uint32_t SCTIMER_GetInstance(SCT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to SCT bases for each instance. */ -static SCT_Type *const s_sctBases[] = SCT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to SCT clocks for each instance. */ -static const clock_ip_name_t s_sctClocks[] = SCT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET -/*! @brief Pointers to SCT resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_sctResets[] = SCT_RSTS_N; -#else -/*! @brief Pointers to SCT resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_sctResets[] = SCT_RSTS; -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/*!< @brief SCTimer event Callback function. */ -static sctimer_event_callback_t s_eventCallback[FSL_FEATURE_SCT_NUMBER_OF_EVENTS]; - -/*!< @brief Keep track of SCTimer event number */ -static uint32_t s_currentEvent; - -/*!< @brief Keep track of SCTimer state number */ -static uint32_t s_currentState; - -/*!< @brief Keep track of SCTimer unify 32-bit or low 16-bit match/capture register number. */ -static uint32_t s_currentMatch; -/*!< @brief Keep track of SCTimer high 16-bit match/capture register number. */ -static uint32_t s_currentMatchhigh; - -/*! @brief Pointer to SCTimer IRQ handler */ -static sctimer_isr_t s_sctimerIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t SCTIMER_GetInstance(SCT_Type *base) -{ - uint32_t instance; - uint32_t sctArrayCount = (sizeof(s_sctBases) / sizeof(s_sctBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < sctArrayCount; instance++) - { - if (s_sctBases[instance] == base) - { - break; - } - } - - assert(instance < sctArrayCount); - - return instance; -} - -/*! - * brief Ungates the SCTimer clock and configures the peripheral for basic operation. - * - * note This API should be called at the beginning of the application using the SCTimer driver. - * - * param base SCTimer peripheral base address - * param config Pointer to the user configuration structure. - * - * return kStatus_Success indicates success; Else indicates failure. - */ -status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config) -{ - assert(NULL != config); - - uint32_t i; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the SCTimer clock*/ - CLOCK_EnableClock(s_sctClocks[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_sctResets[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - - /* Setup the counter operation. For Current Driver interface SCTIMER_Init don't know detail - * frequency of input clock, but User know it. So the INSYNC have to set by user level. */ - base->CONFIG = SCT_CONFIG_CKSEL(config->clockSelect) | SCT_CONFIG_CLKMODE(config->clockMode) | - SCT_CONFIG_UNIFY(config->enableCounterUnify) | SCT_CONFIG_INSYNC(config->inputsync); - - /* Write to the control register, keep the counters halted. */ - base->CTRL = - SCT_CTRL_BIDIR_L(config->enableBidirection_l) | SCT_CTRL_PRE_L(config->prescale_l) | SCT_CTRL_HALT_L_MASK; - /* Clear the counter after changing the PRE value. */ - base->CTRL |= SCT_CTRL_CLRCTR_L_MASK; - - if (!(config->enableCounterUnify)) - { - base->CTRL |= - SCT_CTRL_BIDIR_H(config->enableBidirection_h) | SCT_CTRL_PRE_H(config->prescale_h) | SCT_CTRL_HALT_H_MASK; - base->CTRL |= SCT_CTRL_CLRCTR_H_MASK; - } - - /* Initial state of channel output */ - base->OUTPUT = config->outInitState; - - /* Clear the global variables */ - s_currentEvent = 0U; - s_currentState = 0U; - s_currentMatch = 0U; - s_currentMatchhigh = 0U; - - /* Clear the callback array */ - for (i = 0; i < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) - { - s_eventCallback[i] = NULL; - } - - /* Save interrupt handler */ - s_sctimerIsr = SCTIMER_EventHandleIRQ; - - return kStatus_Success; -} - -/*! - * brief Gates the SCTimer clock. - * - * param base SCTimer peripheral base address - */ -void SCTIMER_Deinit(SCT_Type *base) -{ - /* Halt the counters */ - base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the SCTimer clock*/ - CLOCK_DisableClock(s_sctClocks[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Fills in the SCTimer configuration structure with the default settings. - * - * The default values are: - * code - * config->enableCounterUnify = true; - * config->clockMode = kSCTIMER_System_ClockMode; - * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - * config->enableBidirection_l = false; - * config->enableBidirection_h = false; - * config->prescale_l = 0U; - * config->prescale_h = 0U; - * config->outInitState = 0U; - * config->inputsync = 0xFU; - * endcode - * param config Pointer to the user configuration structure. - */ -void SCTIMER_GetDefaultConfig(sctimer_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* SCT operates as a unified 32-bit counter */ - config->enableCounterUnify = true; - /* System clock clocks the entire SCT module */ - config->clockMode = kSCTIMER_System_ClockMode; - /* This is used only by certain clock modes */ - config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - /* Up count mode only for the unified counter */ - config->enableBidirection_l = false; - /* Up count mode only for Counte_H */ - config->enableBidirection_h = false; - /* Prescale factor of 1 */ - config->prescale_l = 0U; - /* Prescale factor of 1 for Counter_H*/ - config->prescale_h = 0U; - /* Clear outputs */ - config->outInitState = 0U; - /* Default value is 0xFU, it can be clear as 0 when speical conditions met. - * Condition can be clear as 0: (for all Clock Modes): - * (1) The corresponding input is already synchronous to the SCTimer/PWM clock. - * (2) The SCTimer/PWM clock frequency does not exceed 100 MHz. - * Note: The SCTimer/PWM clock is the bus/system clock for CKMODE 0-2 or asynchronous input - * clock for CKMODE3. - * Another condition can be clear as 0: (for CKMODE2 only) - * (1) The corresponding input is synchronous to the designated CKMODE2 input clock. - * (2) The CKMODE2 input clock frequency is less than one-third the frequency of the bus/system clock. - * Default value set as 0U, input0~input3 are set as bypasses. */ - config->inputsync = 0xFU; -} - -/*! - * brief Configures the PWM signal parameters. - * - * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This - * function will create 2 events; one of the events will trigger on match with the pulse value - * and the other will trigger when the counter matches the PWM period. The PWM period event is - * also used as a limit event to reset the counter or change direction. Both events are enabled - * for the same state. The state number can be retrieved by calling the function - * SCTIMER_GetCurrentStateNumber(). - * The counter is set to operate as one 32-bit counter (unify bit is set to 1). - * The counter operates in bi-directional mode when generating a center-aligned PWM. - * - * note When setting PWM output from multiple output pins, they all should use the same PWM mode - * i.e all PWM's should be either edge-aligned or center-aligned. - * When using this API, the PWM signal frequency of all the initialized channels must be the same. - * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the - * API's pwmFreq_Hz. - * - * param base SCTimer peripheral base address - * param pwmParams PWM parameters to configure the output - * param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t - * param pwmFreq_Hz PWM signal frequency in Hz - * param srcClock_Hz SCTimer counter clock in Hz - * param event Pointer to a variable where the PWM period event number is stored - * - * return kStatus_Success on success - * kStatus_Fail If we have hit the limit in terms of number of events created or if - * an incorrect PWM dutycylce is passed in. - */ -status_t SCTIMER_SetupPwm(SCT_Type *base, - const sctimer_pwm_signal_param_t *pwmParams, - sctimer_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - uint32_t *event) -{ - assert(NULL != pwmParams); - assert(0U != srcClock_Hz); - assert(0U != pwmFreq_Hz); - assert((uint32_t)pwmParams->output < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - - /* If we do not have enough events available (this function will create two events), - * the function will return fail. - */ - status_t status = kStatus_Fail; - status_t status2; - uint32_t period, pulsePeriod = 0; - uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1U); - uint32_t periodEvent = 0, pulseEvent = 0; - uint32_t reg; - - if ((s_currentEvent + 2U) <= (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS) - { - /* Use bi-directional mode for center-aligned PWM */ - if (mode == kSCTIMER_CenterAlignedPwm) - { - base->CTRL |= SCT_CTRL_BIDIR_L_MASK; - } - - /* Calculate PWM period match value */ - if (mode == kSCTIMER_EdgeAlignedPwm) - { - period = (sctClock / pwmFreq_Hz) - 1U; - } - else - { - period = sctClock / (pwmFreq_Hz * 2U); - } - - /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ - if (pwmParams->dutyCyclePercent >= 100U) - { - pulsePeriod = period + 2U; - } - else - { - pulsePeriod = (uint32_t)(((uint64_t)period * pwmParams->dutyCyclePercent) / 100U); - } - - /* Schedule an event when we reach the PWM period */ - status = - SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, period, 0, kSCTIMER_Counter_U, &periodEvent); - - /* Schedule an event when we reach the pulse width */ - status2 = SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, pulsePeriod, 0, kSCTIMER_Counter_U, - &pulseEvent); - - if ((kStatus_Success == status) && (kStatus_Success == status2)) - { - /* Reset the counter when we reach the PWM period */ - SCTIMER_SetupCounterLimitAction(base, kSCTIMER_Counter_U, periodEvent); - - /* Return the period event to the user */ - *event = periodEvent; - - /* For high-true level */ - if ((uint32_t)pwmParams->level == (uint32_t)kSCTIMER_HighTrue) - { - if (mode == kSCTIMER_EdgeAlignedPwm) - { - /* Set the initial output level to low which is the inactive state */ - base->OUTPUT &= ~(1UL << (uint32_t)pwmParams->output); - /* Set the output when we reach the PWM period */ - SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, periodEvent); - /* Clear the output when we reach the PWM pulse value */ - SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, pulseEvent); - } - else - { - /* Set the initial output level to high which is the inactive state */ - base->OUTPUT |= (1UL << (uint32_t)pwmParams->output); - /* Clear the output when we reach the PWM pulse event */ - SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, pulseEvent); - /* Reverse output when down counting */ - reg = base->OUTPUTDIRCTRL; - reg &= ~((uint32_t)SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2U * (uint32_t)pwmParams->output)); - reg |= (1UL << (2U * (uint32_t)pwmParams->output)); - base->OUTPUTDIRCTRL = reg; - } - } - /* For low-true level */ - else - { - if (mode == kSCTIMER_EdgeAlignedPwm) - { - /* Set the initial output level to high which is the inactive state */ - base->OUTPUT |= (1UL << (uint32_t)pwmParams->output); - /* Clear the output when we reach the PWM period */ - SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, periodEvent); - /* Set the output when we reach the PWM pulse value */ - SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, pulseEvent); - } - else - { - /* Set the initial output level to low which is the inactive state */ - base->OUTPUT &= ~(1UL << (uint32_t)pwmParams->output); - /* Set the output when we reach the PWM pulse event */ - SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, pulseEvent); - /* Reverse output when down counting */ - reg = base->OUTPUTDIRCTRL; - reg &= ~((uint32_t)SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2U * (uint32_t)pwmParams->output)); - reg |= (1UL << (2U * (uint32_t)pwmParams->output)); - base->OUTPUTDIRCTRL = reg; - } - } - } - else - { - status = kStatus_Fail; - } - } - - return status; -} - -/*! - * brief Updates the duty cycle of an active PWM signal. - * - * Before calling this function, the counter is set to operate as one 32-bit counter (unify bit is set to 1). - * - * param base SCTimer peripheral base address - * param output The output to configure - * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 - * param event Event number associated with this PWM signal. This was returned to the user by the - * function SCTIMER_SetupPwm(). - */ -void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event) - -{ - assert(dutyCyclePercent <= 100U); - assert((uint32_t)output < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - - uint32_t periodMatchReg, pulseMatchReg; - uint32_t pulsePeriod = 0, period; - - /* Retrieve the match register number for the PWM period */ - periodMatchReg = base->EV[event].CTRL & SCT_EV_CTRL_MATCHSEL_MASK; - - /* Retrieve the match register number for the PWM pulse period */ - pulseMatchReg = base->EV[event + 1U].CTRL & SCT_EV_CTRL_MATCHSEL_MASK; - - period = base->MATCH[periodMatchReg]; - - /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ - if (dutyCyclePercent >= 100U) - { - pulsePeriod = period + 2U; - } - else - { - pulsePeriod = (uint32_t)(((uint64_t)period * dutyCyclePercent) / 100U); - } - - /* Stop the counter before updating match register */ - SCTIMER_StopTimer(base, (uint32_t)kSCTIMER_Counter_U); - - /* Update dutycycle */ - base->MATCH[pulseMatchReg] = SCT_MATCH_MATCHn_L(pulsePeriod); - base->MATCHREL[pulseMatchReg] = SCT_MATCHREL_RELOADn_L(pulsePeriod); - - /* Restart the counter */ - SCTIMER_StartTimer(base, (uint32_t)kSCTIMER_Counter_U); -} - -/*! - * brief Create an event that is triggered on a match or IO and schedule in current state. - * - * This function will configure an event using the options provided by the user. If the event type uses - * the counter match, then the function will set the user provided match value into a match register - * and put this match register number into the event control register. - * The event is enabled for the current state and the event number is increased by one at the end. - * The function returns the event number; this event number can be used to configure actions to be - * done when this event is triggered. - * - * param base SCTimer peripheral base address - * param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t - * param matchValue The match value that will be programmed to a match register - * param whichIO The input or output that will be involved in event triggering. This field - * is ignored if the event type is "match only" - * param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * param event Pointer to a variable where the new event number is stored - * - * return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of events created or - if we have reached the limit in terms of number of match registers - */ -status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, - sctimer_event_t howToMonitor, - uint32_t matchValue, - uint32_t whichIO, - sctimer_counter_t whichCounter, - uint32_t *event) -{ - uint32_t combMode = (((uint32_t)howToMonitor & SCT_EV_CTRL_COMBMODE_MASK) >> SCT_EV_CTRL_COMBMODE_SHIFT); - uint32_t currentCtrlVal = (uint32_t)howToMonitor; - status_t status = kStatus_Success; - uint32_t temp = 0; - - if (s_currentEvent < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS) - { - if (2U == combMode) - { - base->EV[s_currentEvent].CTRL = currentCtrlVal | SCT_EV_CTRL_IOSEL(whichIO); - } - else - { - if ((0U == combMode) || (3U == combMode)) - { - currentCtrlVal |= SCT_EV_CTRL_IOSEL(whichIO); - } - - if ((kSCTIMER_Counter_L == whichCounter) && (0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) - { - if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatch); - - /* Use Counter_L bits if user wants to setup the Low counter */ - base->MATCH_ACCESS16BIT[s_currentMatch].MATCHL = (uint16_t)matchValue; - base->MATCHREL_ACCESS16BIT[s_currentMatch].MATCHRELL = (uint16_t)matchValue; - base->EV[s_currentEvent].CTRL = currentCtrlVal; - - /* Increment the match register number */ - s_currentMatch++; - } - else - { - /* An error would occur if we have hit the limit in terms of number of match registers */ - status = kStatus_Fail; - } - } - else if ((kSCTIMER_Counter_H == whichCounter) && (0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) - { - if (s_currentMatchhigh < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatchhigh); - - /* Use Counter_H bits if user wants to setup the High counter */ - currentCtrlVal |= SCT_EV_CTRL_HEVENT(1U); - temp = base->MATCH_ACCESS16BIT[s_currentMatchhigh].MATCHL; - base->MATCH[s_currentMatchhigh] = temp | (matchValue << 16U); - temp = base->MATCHREL_ACCESS16BIT[s_currentMatchhigh].MATCHRELL; - base->MATCHREL[s_currentMatchhigh] = temp | (matchValue << 16U); - - base->EV[s_currentEvent].CTRL = currentCtrlVal; - /* Increment the match register number */ - s_currentMatchhigh++; - } - else - { - /* An error would occur if we have hit the limit in terms of number of match registers */ - status = kStatus_Fail; - } - } - else if ((kSCTIMER_Counter_U == whichCounter) && (0U != (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) - { - if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - /* Use Counter_L bits if counter is operating in 32-bit mode */ - currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatch); - - base->MATCH[s_currentMatch] = matchValue; - base->MATCHREL[s_currentMatch] = matchValue; - base->EV[s_currentEvent].CTRL = currentCtrlVal; - - /* Increment the match register number */ - s_currentMatch++; - } - else - { - /* An error would occur if we have hit the limit in terms of number of match registers */ - status = kStatus_Fail; - } - } - else - { - /* The used counter must match the CONFIG[UNIFY] bit selection */ - status = kStatus_Fail; - } - } - - if (kStatus_Success == status) - { - /* Enable the event in the current state */ - base->EV[s_currentEvent].STATE = (1UL << s_currentState); - - /* Return the event number */ - *event = s_currentEvent; - - /* Increment the event number */ - s_currentEvent++; - } - } - else - { - /* An error would occur if we have hit the limit in terms of number of events created */ - status = kStatus_Fail; - } - - return status; -} - -/*! - * brief Enable an event in the current state. - * - * This function will allow the event passed in to trigger in the current state. The event must - * be created earlier by either calling the function SCTIMER_SetupPwm() or function - * SCTIMER_CreateAndScheduleEvent() . - * - * param base SCTimer peripheral base address - * param event Event number to enable in the current state - * - */ -void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event) -{ - /* Enable event in the current state */ - base->EV[event].STATE |= (1UL << s_currentState); -} - -/*! - * brief Increase the state by 1 - * - * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new - * state. - * - * param base SCTimer peripheral base address - * - * return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of states used - - */ -status_t SCTIMER_IncreaseState(SCT_Type *base) -{ - status_t status = kStatus_Success; - - /* Return an error if we have hit the limit in terms of states used */ - if (s_currentState >= (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES) - { - status = kStatus_Fail; - } - else - { - s_currentState++; - } - - return status; -} - -/*! - * brief Provides the current state - * - * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). - * - * param base SCTimer peripheral base address - * - * return The current state - */ -uint32_t SCTIMER_GetCurrentState(SCT_Type *base) -{ - return s_currentState; -} - -/*! - * brief Toggle the output level. - * - * This change in the output level is triggered by the event number that is passed in by the user. - * - * param base SCTimer peripheral base address - * param whichIO The output to toggle - * param event Event number that will trigger the output change - */ -void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - uint32_t reg; - - /* Set the same event to set and clear the output */ - base->OUT[whichIO].CLR |= (1UL << event); - base->OUT[whichIO].SET |= (1UL << event); - - /* Set the conflict resolution to toggle output */ - reg = base->RES; - reg &= ~(((uint32_t)SCT_RES_O0RES_MASK) << (2U * whichIO)); - reg |= ((uint32_t)(kSCTIMER_ResolveToggle)) << (2U * whichIO); - base->RES = reg; -} - -/*! - * brief Setup capture of the counter value on trigger of a selected event - * - * param base SCTimer peripheral base address - * param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * param captureRegister Pointer to a variable where the capture register number will be returned. User - * can read the captured value from this register when the specified event is triggered. - * param event Event number that will trigger the capture - * - * return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of match/capture registers available - */ -status_t SCTIMER_SetupCaptureAction(SCT_Type *base, - sctimer_counter_t whichCounter, - uint32_t *captureRegister, - uint32_t event) -{ - status_t status; - uint32_t temp = 0; - - if ((kSCTIMER_Counter_L == whichCounter) || (kSCTIMER_Counter_U == whichCounter)) - { - if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - /* Set the bit to enable event */ - base->CAPCTRL_ACCESS16BIT[s_currentMatch].CAPCTRLL |= SCT_CAPCTRLL_CAPCTRLL(1UL << event); - - /* Set this resource to be a capture rather than match */ - base->REGMODE_ACCESS16BIT.REGMODEL |= SCT_REGMODEL_REGMODEL(1UL << s_currentMatch); - - /* Return the match register number */ - *captureRegister = s_currentMatch; - - /* Increase the match register number */ - s_currentMatch++; - - status = kStatus_Success; - } - else - { - /* Return an error if we have hit the limit in terms of number of capture/match registers used */ - status = kStatus_Fail; - } - } - else - { - if (s_currentMatchhigh < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - /* Set bit to enable event */ - temp = base->CAPCTRL_ACCESS16BIT[s_currentMatchhigh].CAPCTRLL; - base->CAPCTRL[s_currentMatchhigh] = temp | ((uint32_t)((uint32_t)(1UL << event) << 16U) & 0xFFFF000U); - /* Set this resource to be a capture rather than match */ - temp = base->REGMODE_ACCESS16BIT.REGMODEL; - base->REGMODE = temp | ((uint32_t)((uint32_t)(1UL << s_currentMatchhigh) << 16U) & 0xFFFF000U); - - /* Return the match register number */ - *captureRegister = s_currentMatchhigh; - - /* Increase the match register number */ - s_currentMatchhigh++; - - status = kStatus_Success; - } - else - { - /* Return an error if we have hit the limit in terms of number of capture/match registers used */ - status = kStatus_Fail; - } - } - - return status; -} - -/*! - * brief Receive noticification when the event trigger an interrupt. - * - * If the interrupt for the event is enabled by the user, then a callback can be registered - * which will be invoked when the event is triggered - * - * param base SCTimer peripheral base address - * param event Event number that will trigger the interrupt - * param callback Function to invoke when the event is triggered - */ - -void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event) -{ - s_eventCallback[event] = callback; -} - -/*! - * brief SCTimer interrupt handler. - * - * param base SCTimer peripheral base address. - */ -void SCTIMER_EventHandleIRQ(SCT_Type *base) -{ - uint32_t eventFlag = SCT0->EVFLAG; - /* Only clear the flags whose interrupt field is enabled */ - uint32_t clearFlag = (eventFlag & SCT0->EVEN); - uint32_t mask = eventFlag; - uint32_t i; - - /* Invoke the callback for certain events */ - for (i = 0; i < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) - { - if ((mask & 0x1U) != 0U) - { - if (s_eventCallback[i] != NULL) - { - s_eventCallback[i](); - } - } - mask >>= 1UL; - - if (0U == mask) - { - /* All events have been handled. */ - break; - } - } - - /* Clear event interrupt flag */ - SCT0->EVFLAG = clearFlag; -} - -void SCT0_DriverIRQHandler(void); -void SCT0_DriverIRQHandler(void) -{ - s_sctimerIsr(SCT0); - SDK_ISR_EXIT_BARRIER; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sctimer.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sctimer.h deleted file mode 100644 index 283a5b7019f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sctimer.h +++ /dev/null @@ -1,1258 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SCTIMER_H_ -#define _FSL_SCTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup sctimer - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 4, 4)) /*!< Version */ -/*@}*/ - -#ifndef SCT_EV_STATE_STATEMSKn -#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(x) & (1UL << FSL_FEATURE_SCT_NUMBER_OF_STATES) - 1UL)) -#endif - -/*! @brief SCTimer PWM operation modes */ -typedef enum _sctimer_pwm_mode -{ - kSCTIMER_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */ - kSCTIMER_CenterAlignedPwm /*!< Center-aligned PWM */ -} sctimer_pwm_mode_t; - -/*! @brief SCTimer counters type. */ -typedef enum _sctimer_counter -{ - kSCTIMER_Counter_L = (1U << 0), /*!< 16-bit Low counter. */ - kSCTIMER_Counter_H = (1U << 1), /*!< 16-bit High counter. */ - kSCTIMER_Counter_U = (1U << 2), /*!< 32-bit Unified counter. */ -} sctimer_counter_t; - -/*! @brief List of SCTimer input pins */ -typedef enum _sctimer_input -{ - kSCTIMER_Input_0 = 0U, /*!< SCTIMER input 0 */ - kSCTIMER_Input_1, /*!< SCTIMER input 1 */ - kSCTIMER_Input_2, /*!< SCTIMER input 2 */ - kSCTIMER_Input_3, /*!< SCTIMER input 3 */ - kSCTIMER_Input_4, /*!< SCTIMER input 4 */ - kSCTIMER_Input_5, /*!< SCTIMER input 5 */ - kSCTIMER_Input_6, /*!< SCTIMER input 6 */ - kSCTIMER_Input_7 /*!< SCTIMER input 7 */ -} sctimer_input_t; - -/*! @brief List of SCTimer output pins */ -typedef enum _sctimer_out -{ - kSCTIMER_Out_0 = 0U, /*!< SCTIMER output 0*/ - kSCTIMER_Out_1, /*!< SCTIMER output 1 */ - kSCTIMER_Out_2, /*!< SCTIMER output 2 */ - kSCTIMER_Out_3, /*!< SCTIMER output 3 */ - kSCTIMER_Out_4, /*!< SCTIMER output 4 */ - kSCTIMER_Out_5, /*!< SCTIMER output 5 */ - kSCTIMER_Out_6, /*!< SCTIMER output 6 */ - kSCTIMER_Out_7, /*!< SCTIMER output 7 */ - kSCTIMER_Out_8, /*!< SCTIMER output 8 */ - kSCTIMER_Out_9 /*!< SCTIMER output 9 */ -} sctimer_out_t; - -/*! @brief SCTimer PWM output pulse mode: high-true, low-true or no output */ -typedef enum _sctimer_pwm_level_select -{ - kSCTIMER_LowTrue = 0U, /*!< Low true pulses */ - kSCTIMER_HighTrue /*!< High true pulses */ -} sctimer_pwm_level_select_t; - -/*! @brief Options to configure a SCTimer PWM signal */ -typedef struct _sctimer_pwm_signal_param -{ - sctimer_out_t output; /*!< The output pin to use to generate the PWM signal */ - sctimer_pwm_level_select_t level; /*!< PWM output active level select. */ - uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 - 0 = always inactive signal (0% duty cycle) - 100 = always active signal (100% duty cycle).*/ -} sctimer_pwm_signal_param_t; - -/*! @brief SCTimer clock mode options */ -typedef enum _sctimer_clock_mode -{ - kSCTIMER_System_ClockMode = 0U, /*!< System Clock Mode */ - kSCTIMER_Sampled_ClockMode, /*!< Sampled System Clock Mode */ - kSCTIMER_Input_ClockMode, /*!< SCT Input Clock Mode */ - kSCTIMER_Asynchronous_ClockMode /*!< Asynchronous Mode */ -} sctimer_clock_mode_t; - -/*! @brief SCTimer clock select options */ -typedef enum _sctimer_clock_select -{ - kSCTIMER_Clock_On_Rise_Input_0 = 0U, /*!< Rising edges on input 0 */ - kSCTIMER_Clock_On_Fall_Input_0, /*!< Falling edges on input 0 */ - kSCTIMER_Clock_On_Rise_Input_1, /*!< Rising edges on input 1 */ - kSCTIMER_Clock_On_Fall_Input_1, /*!< Falling edges on input 1 */ - kSCTIMER_Clock_On_Rise_Input_2, /*!< Rising edges on input 2 */ - kSCTIMER_Clock_On_Fall_Input_2, /*!< Falling edges on input 2 */ - kSCTIMER_Clock_On_Rise_Input_3, /*!< Rising edges on input 3 */ - kSCTIMER_Clock_On_Fall_Input_3, /*!< Falling edges on input 3 */ - kSCTIMER_Clock_On_Rise_Input_4, /*!< Rising edges on input 4 */ - kSCTIMER_Clock_On_Fall_Input_4, /*!< Falling edges on input 4 */ - kSCTIMER_Clock_On_Rise_Input_5, /*!< Rising edges on input 5 */ - kSCTIMER_Clock_On_Fall_Input_5, /*!< Falling edges on input 5 */ - kSCTIMER_Clock_On_Rise_Input_6, /*!< Rising edges on input 6 */ - kSCTIMER_Clock_On_Fall_Input_6, /*!< Falling edges on input 6 */ - kSCTIMER_Clock_On_Rise_Input_7, /*!< Rising edges on input 7 */ - kSCTIMER_Clock_On_Fall_Input_7 /*!< Falling edges on input 7 */ -} sctimer_clock_select_t; - -/*! - * @brief SCTimer output conflict resolution options. - * - * Specifies what action should be taken if multiple events dictate that a given output should be - * both set and cleared at the same time - */ -typedef enum _sctimer_conflict_resolution -{ - kSCTIMER_ResolveNone = 0U, /*!< No change */ - kSCTIMER_ResolveSet, /*!< Set output */ - kSCTIMER_ResolveClear, /*!< Clear output */ - kSCTIMER_ResolveToggle /*!< Toggle output */ -} sctimer_conflict_resolution_t; - -/*! @brief List of SCTimer event generation active direction when the counters are operating in BIDIR mode. */ -typedef enum _sctimer_event_active_direction -{ - kSCTIMER_ActiveIndependent = 0U, /*!< This event is triggered regardless of the count direction. */ - kSCTIMER_ActiveInCountUp, /*!< This event is triggered only during up-counting when BIDIR = 1. */ - kSCTIMER_ActiveInCountDown /*!< This event is triggered only during down-counting when BIDIR = 1. */ -} sctimer_event_active_direction_t; - -/*! @brief List of SCTimer event types */ -typedef enum _sctimer_event -{ - kSCTIMER_InputLowOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_MatchEventOnly = - (1 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_InputLowEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_InputLowAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT) -} sctimer_event_t; - -/*! @brief SCTimer callback typedef. */ -typedef void (*sctimer_event_callback_t)(void); - -/*! @brief List of SCTimer interrupts */ -typedef enum _sctimer_interrupt_enable -{ - kSCTIMER_Event0InterruptEnable = (1U << 0), /*!< Event 0 interrupt */ - kSCTIMER_Event1InterruptEnable = (1U << 1), /*!< Event 1 interrupt */ - kSCTIMER_Event2InterruptEnable = (1U << 2), /*!< Event 2 interrupt */ - kSCTIMER_Event3InterruptEnable = (1U << 3), /*!< Event 3 interrupt */ - kSCTIMER_Event4InterruptEnable = (1U << 4), /*!< Event 4 interrupt */ - kSCTIMER_Event5InterruptEnable = (1U << 5), /*!< Event 5 interrupt */ - kSCTIMER_Event6InterruptEnable = (1U << 6), /*!< Event 6 interrupt */ - kSCTIMER_Event7InterruptEnable = (1U << 7), /*!< Event 7 interrupt */ - kSCTIMER_Event8InterruptEnable = (1U << 8), /*!< Event 8 interrupt */ - kSCTIMER_Event9InterruptEnable = (1U << 9), /*!< Event 9 interrupt */ - kSCTIMER_Event10InterruptEnable = (1U << 10), /*!< Event 10 interrupt */ - kSCTIMER_Event11InterruptEnable = (1U << 11), /*!< Event 11 interrupt */ - kSCTIMER_Event12InterruptEnable = (1U << 12), /*!< Event 12 interrupt */ -} sctimer_interrupt_enable_t; - -/*! @brief List of SCTimer flags */ -typedef enum _sctimer_status_flags -{ - kSCTIMER_Event0Flag = (1U << 0), /*!< Event 0 Flag */ - kSCTIMER_Event1Flag = (1U << 1), /*!< Event 1 Flag */ - kSCTIMER_Event2Flag = (1U << 2), /*!< Event 2 Flag */ - kSCTIMER_Event3Flag = (1U << 3), /*!< Event 3 Flag */ - kSCTIMER_Event4Flag = (1U << 4), /*!< Event 4 Flag */ - kSCTIMER_Event5Flag = (1U << 5), /*!< Event 5 Flag */ - kSCTIMER_Event6Flag = (1U << 6), /*!< Event 6 Flag */ - kSCTIMER_Event7Flag = (1U << 7), /*!< Event 7 Flag */ - kSCTIMER_Event8Flag = (1U << 8), /*!< Event 8 Flag */ - kSCTIMER_Event9Flag = (1U << 9), /*!< Event 9 Flag */ - kSCTIMER_Event10Flag = (1U << 10), /*!< Event 10 Flag */ - kSCTIMER_Event11Flag = (1U << 11), /*!< Event 11 Flag */ - kSCTIMER_Event12Flag = (1U << 12), /*!< Event 12 Flag */ - kSCTIMER_BusErrorLFlag = - (1U << SCT_CONFLAG_BUSERRL_SHIFT), /*!< Bus error due to write when L counter was not halted */ - kSCTIMER_BusErrorHFlag = - (int)(1U << SCT_CONFLAG_BUSERRH_SHIFT) /*!< Bus error due to write when H counter was not halted */ -} sctimer_status_flags_t; - -/*! - * @brief SCTimer configuration structure - * - * This structure holds the configuration settings for the SCTimer peripheral. To initialize this - * structure to reasonable defaults, call the SCTMR_GetDefaultConfig() function and pass a - * pointer to the configuration structure instance. - * - * The configuration structure can be made constant so as to reside in flash. - */ -typedef struct _sctimer_config -{ - bool enableCounterUnify; /*!< true: SCT operates as a unified 32-bit counter; - false: SCT operates as two 16-bit counters. - User can use the 16-bit low counter and the 16-bit high counters at the - same time; for Hardware limit, user can not use unified 32-bit counter - and any 16-bit low/high counter at the same time. */ - sctimer_clock_mode_t clockMode; /*!< SCT clock mode value */ - sctimer_clock_select_t clockSelect; /*!< SCT clock select value */ - bool enableBidirection_l; /*!< true: Up-down count mode for the L or unified counter - false: Up count mode only for the L or unified counter */ - bool enableBidirection_h; /*!< true: Up-down count mode for the H or unified counter - false: Up count mode only for the H or unified counter. - This field is used only if the enableCounterUnify is set - to false */ - uint8_t prescale_l; /*!< Prescale value to produce the L or unified counter clock */ - uint8_t prescale_h; /*!< Prescale value to produce the H counter clock. - This field is used only if the enableCounterUnify is set - to false */ - uint8_t outInitState; /*!< Defines the initial output value */ - uint8_t inputsync; /*!< SCT INSYNC value, INSYNC field in the CONFIG register, from bit9 to bit 16. - it is used to define synchronization for input N: - bit 9 = input 0 - bit 10 = input 1 - bit 11 = input 2 - bit 12 = input 3 - All other bits are reserved (bit13 ~bit 16). - How User to set the the value for the member inputsync. - IE: delay for input0, and input 1, bypasses for input 2 and input 3 - MACRO definition in user level. - \#define INPUTSYNC0 (0U) - \#define INPUTSYNC1 (1U) - \#define INPUTSYNC2 (2U) - \#define INPUTSYNC3 (3U) - User Code. - sctimerInfo.inputsync = (1 << INPUTSYNC2) | (1 << INPUTSYNC3); */ -} sctimer_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the SCTimer clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the SCTimer driver. - * - * @param base SCTimer peripheral base address - * @param config Pointer to the user configuration structure. - * - * @return kStatus_Success indicates success; Else indicates failure. - */ -status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config); - -/*! - * @brief Gates the SCTimer clock. - * - * @param base SCTimer peripheral base address - */ -void SCTIMER_Deinit(SCT_Type *base); - -/*! - * @brief Fills in the SCTimer configuration structure with the default settings. - * - * The default values are: - * @code - * config->enableCounterUnify = true; - * config->clockMode = kSCTIMER_System_ClockMode; - * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - * config->enableBidirection_l = false; - * config->enableBidirection_h = false; - * config->prescale_l = 0U; - * config->prescale_h = 0U; - * config->outInitState = 0U; - * config->inputsync = 0xFU; - * @endcode - * @param config Pointer to the user configuration structure. - */ -void SCTIMER_GetDefaultConfig(sctimer_config_t *config); - -/*! @}*/ - -/*! - * @name PWM setup operations - * @{ - */ - -/*! - * @brief Configures the PWM signal parameters. - * - * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This - * function will create 2 events; one of the events will trigger on match with the pulse value - * and the other will trigger when the counter matches the PWM period. The PWM period event is - * also used as a limit event to reset the counter or change direction. Both events are enabled - * for the same state. The state number can be retrieved by calling the function - * SCTIMER_GetCurrentStateNumber(). - * The counter is set to operate as one 32-bit counter (unify bit is set to 1). - * The counter operates in bi-directional mode when generating a center-aligned PWM. - * - * @note When setting PWM output from multiple output pins, they all should use the same PWM mode - * i.e all PWM's should be either edge-aligned or center-aligned. - * When using this API, the PWM signal frequency of all the initialized channels must be the same. - * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the - * API's pwmFreq_Hz. - * - * @param base SCTimer peripheral base address - * @param pwmParams PWM parameters to configure the output - * @param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz SCTimer counter clock in Hz - * @param event Pointer to a variable where the PWM period event number is stored - * - * @return kStatus_Success on success - * kStatus_Fail If we have hit the limit in terms of number of events created or if - * an incorrect PWM dutycylce is passed in. - */ -status_t SCTIMER_SetupPwm(SCT_Type *base, - const sctimer_pwm_signal_param_t *pwmParams, - sctimer_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - uint32_t *event); - -/*! - * @brief Updates the duty cycle of an active PWM signal. - * - * Before calling this function, the counter is set to operate as one 32-bit counter (unify bit is set to 1). - * - * @param base SCTimer peripheral base address - * @param output The output to configure - * @param dutyCyclePercent New PWM pulse width; the value should be between 1 to 100 - * @param event Event number associated with this PWM signal. This was returned to the user by the - * function SCTIMER_SetupPwm(). - */ -void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event); - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline void SCTIMER_EnableInterrupts(SCT_Type *base, uint32_t mask) -{ - base->EVEN |= mask; -} - -/*! - * @brief Disables the selected SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline void SCTIMER_DisableInterrupts(SCT_Type *base, uint32_t mask) -{ - base->EVEN &= ~mask; -} - -/*! - * @brief Gets the enabled SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline uint32_t SCTIMER_GetEnabledInterrupts(SCT_Type *base) -{ - return (base->EVEN & 0xFFFFU); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the SCTimer status flags. - * - * @param base SCTimer peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::sctimer_status_flags_t - */ -static inline uint32_t SCTIMER_GetStatusFlags(SCT_Type *base) -{ - uint32_t statusFlags = 0; - - /* Add the recorded events */ - statusFlags = (base->EVFLAG & 0xFFFFU); - - /* Add bus error flags */ - statusFlags |= (base->CONFLAG & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); - - return statusFlags; -} - -/*! - * @brief Clears the SCTimer status flags. - * - * @param base SCTimer peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::sctimer_status_flags_t - */ -static inline void SCTIMER_ClearStatusFlags(SCT_Type *base, uint32_t mask) -{ - /* Write to the flag registers */ - base->EVFLAG = (mask & 0xFFFFU); - base->CONFLAG = (mask & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); -} - -/*! @}*/ - -/*! - * @name Counter Start and Stop - * @{ - */ - -/*! - * @brief Starts the SCTimer counter. - * - * @note In 16-bit mode, we can enable both Counter_L and Counter_H, In 32-bit mode, we only can select Counter_U. - * - * @param base SCTimer peripheral base address - * @param countertoStart The SCTimer counters to enable. This is a logical OR of members of the - * enumeration ::sctimer_counter_t. - */ -static inline void SCTIMER_StartTimer(SCT_Type *base, uint32_t countertoStart) -{ - switch (countertoStart) - { - case (uint32_t)kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_L bit when user wants to start the Low counter */ - base->CTRL_ACCESS16BIT.CTRLL &= ~((uint16_t)SCT_CTRLL_HALT_L_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_H bit when user wants to start the High counter */ - base->CTRL_ACCESS16BIT.CTRLH &= ~((uint16_t)SCT_CTRLH_HALT_H_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_L | (uint32_t)kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_L/HALT_H bit when user wants to H counter and L counter at same time */ - base->CTRL &= ~(SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_L bit when the counter is operating in 32-bit mode (unify counter). */ - base->CTRL &= ~(SCT_CTRL_HALT_L_MASK); - break; - - default: - /* Counter_L/Counter_H can't work together with Counter_U. */ - assert(false); - break; - } -} - -/*! - * @brief Halts the SCTimer counter. - * - * @param base SCTimer peripheral base address - * @param countertoStop The SCTimer counters to stop. This is a logical OR of members of the - * enumeration ::sctimer_counter_t. - */ -static inline void SCTIMER_StopTimer(SCT_Type *base, uint32_t countertoStop) -{ - switch (countertoStop) - { - case (uint32_t)kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Set HALT_L bit when user wants to start the Low counter */ - base->CTRL_ACCESS16BIT.CTRLL |= (SCT_CTRLL_HALT_L_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Set HALT_H bit when user wants to start the High counter */ - base->CTRL_ACCESS16BIT.CTRLH |= (SCT_CTRLH_HALT_H_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_L | (uint32_t)kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_L/HALT_H bit when user wants to H counter and L counter at same time */ - base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Set HALT_L bit when the counter is operating in 32-bit mode (unify counter). */ - base->CTRL |= (SCT_CTRL_HALT_L_MASK); - break; - - default: - /* Counter_L/Counter_H can't work together with Counter_U. */ - assert(false); - break; - } -} - -/*! @}*/ - -/*! - * @name Functions to create a new event and manage the state logic - * @{ - */ - -/*! - * @brief Create an event that is triggered on a match or IO and schedule in current state. - * - * This function will configure an event using the options provided by the user. If the event type uses - * the counter match, then the function will set the user provided match value into a match register - * and put this match register number into the event control register. - * The event is enabled for the current state and the event number is increased by one at the end. - * The function returns the event number; this event number can be used to configure actions to be - * done when this event is triggered. - * - * @param base SCTimer peripheral base address - * @param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t - * @param matchValue The match value that will be programmed to a match register - * @param whichIO The input or output that will be involved in event triggering. This field - * is ignored if the event type is "match only" - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Pointer to a variable where the new event number is stored - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of events created or - if we have reached the limit in terms of number of match registers - */ -status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, - sctimer_event_t howToMonitor, - uint32_t matchValue, - uint32_t whichIO, - sctimer_counter_t whichCounter, - uint32_t *event); - -/*! - * @brief Enable an event in the current state. - * - * This function will allow the event passed in to trigger in the current state. The event must - * be created earlier by either calling the function SCTIMER_SetupPwm() or function - * SCTIMER_CreateAndScheduleEvent() . - * - * @param base SCTimer peripheral base address - * @param event Event number to enable in the current state - * - */ -void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event); - -/*! - * @brief Increase the state by 1 - * - * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new - * state. - * - * @param base SCTimer peripheral base address - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of states used - - */ -status_t SCTIMER_IncreaseState(SCT_Type *base); - -/*! - * @brief Provides the current state - * - * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). - * - * @param base SCTimer peripheral base address - * - * @return The current state - */ -uint32_t SCTIMER_GetCurrentState(SCT_Type *base); - -/*! - * @brief Set the counter current state. - * - * The function is to set the state variable bit field of STATE register. Writing to the STATE_L, STATE_H, or unified - * register is only allowed when the corresponding counter is halted (HALT bits are set to 1 in the CTRL register). - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param state The counter current state number (only support range from 0~31). - */ -static inline void SCTIMER_SetCounterState(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t state) -{ - /* SCT only support 0 ~ FSL_FEATURE_SCT_NUMBER_OF_STATES state value. */ - assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); - - SCTIMER_StopTimer(base, (uint32_t)whichCounter); - - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_L bits when user wants to setup the Low counter */ - base->STATE_ACCESS16BIT.STATEL = SCT_STATEL_STATEL(state); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_H bits when user wants to start the High counter */ - base->STATE_ACCESS16BIT.STATEH = SCT_STATEH_STATEH(state); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_L bits when counter is operating in 32-bit mode (unify counter). */ - base->STATE = SCT_STATE_STATE_L(state); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } - - SCTIMER_StartTimer(base, (uint32_t)whichCounter); -} - -/*! - * @brief Get the counter current state value. - * - * The function is to get the state variable bit field of STATE register. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @return The the counter current state value. - */ -static inline uint16_t SCTIMER_GetCounterState(SCT_Type *base, sctimer_counter_t whichCounter) -{ - uint16_t regs; - - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_L bits when user wants to setup the Low counter */ - regs = base->STATE_ACCESS16BIT.STATEL & SCT_STATEL_STATEL_MASK; - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_H bits when user wants to start the High counter */ - regs = base->STATE_ACCESS16BIT.STATEH & SCT_STATEH_STATEH_MASK; - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_L bits when counter is operating in 32-bit mode (unify counter). */ - regs = (uint16_t)(base->STATE & SCT_STATE_STATE_L_MASK); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } - - return regs; -} - -/*! @}*/ - -/*! - * @name Actions to take in response to an event - * @{ - */ - -/*! - * @brief Setup capture of the counter value on trigger of a selected event - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param captureRegister Pointer to a variable where the capture register number will be returned. User - * can read the captured value from this register when the specified event is triggered. - * @param event Event number that will trigger the capture - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of match/capture registers available - */ -status_t SCTIMER_SetupCaptureAction(SCT_Type *base, - sctimer_counter_t whichCounter, - uint32_t *captureRegister, - uint32_t event); - -/*! - * @brief Receive noticification when the event trigger an interrupt. - * - * If the interrupt for the event is enabled by the user, then a callback can be registered - * which will be invoked when the event is triggered - * - * @param base SCTimer peripheral base address - * @param event Event number that will trigger the interrupt - * @param callback Function to invoke when the event is triggered - */ - -void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event); - -/*! - * @brief Change the load method of transition to the specified state. - * - * Change the load method of transition, it will be triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param event Event number that will change the method to trigger the state transition - * @param fgLoad The method to load highest-numbered event occurring for that state to the STATE register. - * - true: Load the STATEV value to STATE when the event occurs to be the next state. - * - false: Add the STATEV value to STATE when the event occurs to be the next state. - */ -static inline void SCTIMER_SetupStateLdMethodAction(SCT_Type *base, uint32_t event, bool fgLoad) -{ - uint32_t reg = base->EV[event].CTRL; - - if (fgLoad) - { - /* Load the STATEV value to STATE when the event occurs to be the next state */ - reg |= SCT_EV_CTRL_STATELD_MASK; - } - else - { - /* Add the STATEV value to STATE when the event occurs to be the next state */ - reg &= ~SCT_EV_CTRL_STATELD_MASK; - } - - base->EV[event].CTRL = reg; -} - -/*! - * @brief Transition to the specified state with Load method. - * - * This transition will be triggered by the event number that is passed in by the user, the method decide how to load - * the highest-numbered event occurring for that state to the STATE register. - * - * @param base SCTimer peripheral base address - * @param nextState The next state SCTimer will transition to - * @param event Event number that will trigger the state transition - * @param fgLoad The method to load the highest-numbered event occurring for that state to the STATE register. - * - true: Load the STATEV value to STATE when the event occurs to be the next state. - * - false: Add the STATEV value to STATE when the event occurs to be the next state. - */ -static inline void SCTIMER_SetupNextStateActionwithLdMethod(SCT_Type *base, - uint32_t nextState, - uint32_t event, - bool fgLoad) -{ - uint32_t reg = base->EV[event].CTRL; - - reg &= ~(SCT_EV_CTRL_STATEV_MASK | SCT_EV_CTRL_STATELD_MASK); - - reg |= SCT_EV_CTRL_STATEV(nextState); - - if (fgLoad) - { - /* Load the STATEV value when the event occurs to be the next state */ - reg |= SCT_EV_CTRL_STATELD_MASK; - } - - base->EV[event].CTRL = reg; -} - -/*! - * @brief Transition to the specified state. - * @deprecated Do not use this function. It has been superceded by @ref SCTIMER_SetupNextStateActionwithLdMethod - * - * This transition will be triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param nextState The next state SCTimer will transition to - * @param event Event number that will trigger the state transition - */ -static inline void SCTIMER_SetupNextStateAction(SCT_Type *base, uint32_t nextState, uint32_t event) -{ - uint32_t reg = base->EV[event].CTRL; - - reg &= ~(SCT_EV_CTRL_STATEV_MASK); - /* Load the STATEV value when the event occurs to be the next state */ - reg |= SCT_EV_CTRL_STATEV(nextState) | SCT_EV_CTRL_STATELD_MASK; - - base->EV[event].CTRL = reg; -} - -/*! - * @brief Setup event active direction when the counters are operating in BIDIR mode. - * - * @param base SCTimer peripheral base address - * @param activeDirection Event generation active direction, see @ref sctimer_event_active_direction_t. - * @param event Event number that need setup the active direction. - */ -static inline void SCTIMER_SetupEventActiveDirection(SCT_Type *base, - sctimer_event_active_direction_t activeDirection, - uint32_t event) -{ - uint32_t reg = base->EV[event].CTRL; - - reg &= ~(SCT_EV_CTRL_DIRECTION_MASK); - - reg |= SCT_EV_CTRL_DIRECTION(activeDirection); - - base->EV[event].CTRL = reg; -} - -/*! - * @brief Set the Output. - * - * This output will be set when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to set - * @param event Event number that will trigger the output change - */ -static inline void SCTIMER_SetupOutputSetAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - base->OUT[whichIO].SET |= (1UL << event); -} - -/*! - * @brief Clear the Output. - * - * This output will be cleared when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to clear - * @param event Event number that will trigger the output change - */ -static inline void SCTIMER_SetupOutputClearAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - base->OUT[whichIO].CLR |= (1UL << event); -} - -/*! - * @brief Toggle the output level. - * - * This change in the output level is triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to toggle - * @param event Event number that will trigger the output change - */ -void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event); - -/*! - * @brief Limit the running counter. - * - * The counter is limited when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Event number that will trigger the counter to be limited - */ -static inline void SCTIMER_SetupCounterLimitAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->LIMIT_ACCESS16BIT.LIMITL |= SCT_LIMITL_LIMITL(1UL << event); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->LIMIT_ACCESS16BIT.LIMITH |= SCT_LIMITH_LIMITH(1UL << event); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->LIMIT |= SCT_LIMIT_LIMMSK_L(1UL << event); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } -} - -/*! - * @brief Stop the running counter. - * - * The counter is stopped when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Event number that will trigger the counter to be stopped - */ -static inline void SCTIMER_SetupCounterStopAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->STOP_ACCESS16BIT.STOPL |= SCT_STOPL_STOPL(1UL << event); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->STOP_ACCESS16BIT.STOPH |= SCT_STOPH_STOPH(1UL << event); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->STOP |= SCT_STOP_STOPMSK_L(1UL << event); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } -} - -/*! - * @brief Re-start the stopped counter. - * - * The counter will re-start when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Event number that will trigger the counter to re-start - */ -static inline void SCTIMER_SetupCounterStartAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->START_ACCESS16BIT.STARTL |= SCT_STARTL_STARTL(1UL << event); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->START_ACCESS16BIT.STARTH |= SCT_STARTH_STARTH(1UL << event); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->START |= SCT_START_STARTMSK_L(1UL << event); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } -} - -/*! - * @brief Halt the running counter. - * - * The counter is disabled (halted) when the event number that is passed in by the user is - * triggered. When the counter is halted, all further events are disabled. The HALT condition - * can only be removed by calling the SCTIMER_StartTimer() function. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Event number that will trigger the counter to be halted - */ -static inline void SCTIMER_SetupCounterHaltAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->HALT_ACCESS16BIT.HALTL |= SCT_HALTL_HALTL(1UL << event); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->HALT_ACCESS16BIT.HALTH |= SCT_HALTH_HALTH(1UL << event); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->HALT |= SCT_HALT_HALTMSK_L(1UL << event); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } -} - -#if !(defined(FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) && FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) -/*! - * @brief Generate a DMA request. - * - * DMA request will be triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param dmaNumber The DMA request to generate - * @param event Event number that will trigger the DMA request - */ -static inline void SCTIMER_SetupDmaTriggerAction(SCT_Type *base, uint32_t dmaNumber, uint32_t event) -{ - if (dmaNumber == 0U) - { - base->DMAREQ0 |= (1UL << event); - } - else - { - base->DMAREQ1 |= (1UL << event); - } -} -#endif /* FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST */ - -/*! - * @brief Set the value of counter. - * - * The function is to set the value of Count register, Writing to the COUNT_L, COUNT_H, or unified register - * is only allowed when the corresponding counter is halted (HALT bits are set to 1 in the CTRL register). - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param value the counter value update to the COUNT register. - */ -static inline void SCTIMER_SetCOUNTValue(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t value) -{ - SCTIMER_StopTimer(base, (uint32_t)whichCounter); - - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(value <= 0xFFFFU); - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->COUNT_ACCESS16BIT.COUNTL = (uint16_t)value; - break; - - case kSCTIMER_Counter_H: - assert(value <= 0xFFFFU); - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->COUNT_ACCESS16BIT.COUNTH = (uint16_t)value; - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->COUNT &= ~SCT_COUNT_CTR_L_MASK; - base->COUNT |= SCT_COUNT_CTR_L(value); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } - - SCTIMER_StartTimer(base, (uint32_t)whichCounter); -} - -/*! - * @brief Get the value of counter. - * - * The function is to read the value of Count register, software can read the counter registers at any time.. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @return The value of counter selected. - */ -static inline uint32_t SCTIMER_GetCOUNTValue(SCT_Type *base, sctimer_counter_t whichCounter) -{ - uint32_t value; - - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - value = base->COUNT_ACCESS16BIT.COUNTL; - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - value = base->COUNT_ACCESS16BIT.COUNTH; - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - value = base->COUNT; - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } - - return value; -} - -/*! - * @brief Set the state mask bit field of EV_STATE register. - * - * @param base SCTimer peripheral base address - * @param event The EV_STATE register be set. - * @param state The state value in which the event is enabled to occur. - */ -static inline void SCTIMER_SetEventInState(SCT_Type *base, uint32_t event, uint32_t state) -{ - assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); - assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); - - base->EV[event].STATE |= SCT_EV_STATE_STATEMSKn((uint32_t)1U << state); -} - -/*! - * @brief Clear the state mask bit field of EV_STATE register. - * - * @param base SCTimer peripheral base address - * @param event The EV_STATE register be clear. - * @param state The state value in which the event is disabled to occur. - */ -static inline void SCTIMER_ClearEventInState(SCT_Type *base, uint32_t event, uint32_t state) -{ - assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); - assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); - - base->EV[event].STATE &= ~SCT_EV_STATE_STATEMSKn((uint32_t)1U << state); -} - -/*! - * @brief Get the state mask bit field of EV_STATE register. - * - * @note This function is to check whether the event is enabled in a specific state. - * - * @param base SCTimer peripheral base address - * @param event The EV_STATE register be read. - * @param state The state value. - * - * @return The the state mask bit field of EV_STATE register. - * - true: The event is enable in state. - * - false: The event is disable in state. - */ -static inline bool SCTIMER_GetEventInState(SCT_Type *base, uint32_t event, uint32_t state) -{ - assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); - assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); - - return (0U != (base->EV[event].STATE & SCT_EV_STATE_STATEMSKn((uint32_t)1U << state))); -} - -/*! - * @brief SCTimer interrupt handler. - * - * @param base SCTimer peripheral base address. - */ -void SCTIMER_EventHandleIRQ(SCT_Type *base); - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_SCTIMER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi.c deleted file mode 100644 index 456361e6204..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi.c +++ /dev/null @@ -1,1072 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_spi.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi" -#endif - -/* Note: FIFOCFG[SIZE] has always value 1 = 8 items depth */ - -#if defined(FSL_FEATURE_SPI_FIFOSIZE_CFG) && (FSL_FEATURE_SPI_FIFOSIZE_CFG) -#define SPI_FIFO_DEPTH(base) 4 -#else -#define SPI_FIFO_DEPTH(base) ((((base)->FIFOCFG & SPI_FIFOCFG_SIZE_MASK) >> SPI_FIFOCFG_SIZE_SHIFT) << 3) -#endif /*FSL_FEATURE_SPI_FIFOSIZE_CFG*/ - -/* Convert transfer count to transfer bytes. dataWidth is a - * range <0,15>. Range <8,15> represents 2B transfer */ -#define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U)) -#define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U)) -#if defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) && (FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) -#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK)) -#else -#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK) | (SPI_CFG_SPOL3_MASK)) -#endif /*FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE*/ - -/*! - * @brief Used for conversion from `flexcomm_irq_handler_t` to `flexcomm_spi_master_irq_handler_t` and - * `flexcomm_spi_slave_irq_handler_t`. - */ -typedef union spi_to_flexcomm -{ - flexcomm_spi_master_irq_handler_t spi_master_handler; - flexcomm_spi_slave_irq_handler_t spi_slave_handler; - flexcomm_irq_handler_t flexcomm_handler; -} spi_to_flexcomm_t; - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief internal SPI config array */ -static spi_config_t g_configs[FSL_FEATURE_SOC_SPI_COUNT] = {(spi_data_width_t)0}; - -/*! @brief Array to map SPI instance number to base address. */ -static const uint32_t s_spiBaseAddrs[FSL_FEATURE_SOC_SPI_COUNT] = SPI_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_spiIRQ[] = SPI_IRQS; - -/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ -volatile uint8_t s_dummyData[FSL_FEATURE_SOC_SPI_COUNT] = {0}; -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Get the index corresponding to the FLEXCOMM */ -/*! brief Returns instance number for SPI peripheral base address. */ -uint32_t SPI_GetInstance(SPI_Type *base) -{ - uint32_t i; - - for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_SPI_COUNT; i++) - { - if ((uint32_t)base == s_spiBaseAddrs[i]) - { - break; - } - } - - assert(i < (uint32_t)FSL_FEATURE_SOC_SPI_COUNT); - return i; -} - -/*! - * brief Set up the dummy data. - * - * param base SPI peripheral address. - * param dummyData Data to be transferred when tx buffer is NULL. - */ -void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData) -{ - uint32_t instance = SPI_GetInstance(base); - s_dummyData[instance] = dummyData; -} - -/*! - * brief Returns the configurations. - * - * param base SPI peripheral address. - * return return configurations which contain datawidth and SSEL numbers. - * return data type is a pointer of spi_config_t. - */ -void *SPI_GetConfig(SPI_Type *base) -{ - uint32_t instance; - instance = SPI_GetInstance(base); - return &g_configs[instance]; -} - -/*! - * brief Sets the SPI master configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). - * User may use the initialized structure unchanged in SPI_MasterInit(), or modify - * some fields of the structure before calling SPI_MasterInit(). After calling this API, - * the master is ready to transfer. - * Example: - code - spi_master_config_t config; - SPI_MasterGetDefaultConfig(&config); - endcode - * - * param config pointer to master config structure - */ -void SPI_MasterGetDefaultConfig(spi_master_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enableLoopback = false; - config->enableMaster = true; - config->polarity = kSPI_ClockPolarityActiveHigh; - config->phase = kSPI_ClockPhaseFirstEdge; - config->direction = kSPI_MsbFirst; - config->baudRate_Bps = 500000U; - config->dataWidth = kSPI_Data8Bits; - config->sselNum = kSPI_Ssel0; - config->txWatermark = (uint8_t)kSPI_TxFifo0; - config->rxWatermark = (uint8_t)kSPI_RxFifo1; - config->sselPol = kSPI_SpolActiveAllLow; - config->delayConfig.preDelay = 0U; - config->delayConfig.postDelay = 0U; - config->delayConfig.frameDelay = 0U; - config->delayConfig.transferDelay = 0U; -} - -/*! - * brief Initializes the SPI with master configuration. - * - * The configuration structure can be filled by user from scratch, or be set with default - * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. - * Example - code - spi_master_config_t config = { - .baudRate_Bps = 400000, - ... - }; - SPI_MasterInit(SPI0, &config); - endcode - * - * param base SPI base pointer - * param config pointer to master configuration structure - * param srcClock_Hz Source clock frequency. - */ -status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz) -{ - status_t result = kStatus_Success; - uint32_t instance; - uint32_t tmpConfig; - - /* assert params */ - assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); - if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* initialize flexcomm to SPI mode */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); - if (kStatus_Success != result) - { - return result; - } - - /* set divider */ - result = SPI_MasterSetBaud(base, config->baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - - /* get instance number */ - instance = SPI_GetInstance(base); - - /* configure SPI mode */ - tmpConfig = base->CFG; - tmpConfig &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | - SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); - /* phase */ - tmpConfig |= SPI_CFG_CPHA(config->phase); - /* polarity */ - tmpConfig |= SPI_CFG_CPOL(config->polarity); - /* direction */ - tmpConfig |= SPI_CFG_LSBF(config->direction); - /* master mode */ - tmpConfig |= SPI_CFG_MASTER(1); - /* loopback */ - tmpConfig |= SPI_CFG_LOOP(config->enableLoopback); - /* configure active level for all CS */ - tmpConfig |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); - base->CFG = tmpConfig; - - /* store configuration */ - g_configs[instance].dataWidth = config->dataWidth; - g_configs[instance].sselNum = config->sselNum; - /* enable FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; - /* trigger level - empty txFIFO, one item in rxFIFO */ - tmpConfig = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); - tmpConfig |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable generating interrupts for FIFOTRIG levels */ - tmpConfig |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; - /* set FIFOTRIG */ - base->FIFOTRIG = tmpConfig; - - /* Set the delay configuration. */ - SPI_SetTransferDelay(base, &config->delayConfig); - /* Set the dummy data. */ - SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); - - SPI_Enable(base, config->enableMaster); - return kStatus_Success; -} - -/*! - * brief Sets the SPI slave configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). - * Modify some fields of the structure before calling SPI_SlaveInit(). - * Example: - code - spi_slave_config_t config; - SPI_SlaveGetDefaultConfig(&config); - endcode - * - * param config pointer to slave configuration structure - */ -void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enableSlave = true; - config->polarity = kSPI_ClockPolarityActiveHigh; - config->phase = kSPI_ClockPhaseFirstEdge; - config->direction = kSPI_MsbFirst; - config->dataWidth = kSPI_Data8Bits; - config->txWatermark = (uint8_t)kSPI_TxFifo0; - config->rxWatermark = (uint8_t)kSPI_RxFifo1; - config->sselPol = kSPI_SpolActiveAllLow; -} - -/*! - * brief Initializes the SPI with slave configuration. - * - * The configuration structure can be filled by user from scratch or be set with - * default values by SPI_SlaveGetDefaultConfig(). - * After calling this API, the slave is ready to transfer. - * Example - code - spi_slave_config_t config = { - .polarity = flexSPIClockPolarity_ActiveHigh; - .phase = flexSPIClockPhase_FirstEdge; - .direction = flexSPIMsbFirst; - ... - }; - SPI_SlaveInit(SPI0, &config); - endcode - * - * param base SPI base pointer - * param config pointer to slave configuration structure - */ -status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) -{ - status_t result = kStatus_Success; - uint32_t instance; - uint32_t tmpConfig; - - /* assert params */ - assert(!((NULL == base) || (NULL == config))); - if ((NULL == base) || (NULL == config)) - { - return kStatus_InvalidArgument; - } - /* configure flexcomm to SPI, enable clock gate */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); - if (kStatus_Success != result) - { - return result; - } - - instance = SPI_GetInstance(base); - - /* configure SPI mode */ - tmpConfig = base->CFG; - tmpConfig &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | - SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); - /* phase */ - tmpConfig |= SPI_CFG_CPHA(config->phase); - /* polarity */ - tmpConfig |= SPI_CFG_CPOL(config->polarity); - /* direction */ - tmpConfig |= SPI_CFG_LSBF(config->direction); - /* configure active level for all CS */ - tmpConfig |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); - base->CFG = tmpConfig; - - /* store configuration */ - g_configs[instance].dataWidth = config->dataWidth; - /* empty and enable FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; - /* trigger level - empty txFIFO, one item in rxFIFO */ - tmpConfig = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); - tmpConfig |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable generating interrupts for FIFOTRIG levels */ - tmpConfig |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; - /* set FIFOTRIG */ - base->FIFOTRIG = tmpConfig; - - SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); - - SPI_Enable(base, config->enableSlave); - return kStatus_Success; -} - -/*! - * brief De-initializes the SPI. - * - * Calling this API resets the SPI module, gates the SPI clock. - * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. - * - * param base SPI base pointer - */ -void SPI_Deinit(SPI_Type *base) -{ - /* Assert arguments */ - assert(NULL != base); - /* Disable interrupts, disable dma requests, disable peripheral */ - base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXERR_MASK | SPI_FIFOINTENCLR_RXERR_MASK | SPI_FIFOINTENCLR_TXLVL_MASK | - SPI_FIFOINTENCLR_RXLVL_MASK; - base->FIFOCFG &= ~(SPI_FIFOCFG_DMATX_MASK | SPI_FIFOCFG_DMARX_MASK); - base->CFG &= ~(SPI_CFG_ENABLE_MASK); -} - -/*! - * brief Enables the DMA request from SPI txFIFO. - * - * param base SPI base pointer - * param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableTxDMA(SPI_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= SPI_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= ~SPI_FIFOCFG_DMATX_MASK; - } -} - -/*! - * brief Enables the DMA request from SPI rxFIFO. - * - * param base SPI base pointer - * param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableRxDMA(SPI_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= SPI_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= ~SPI_FIFOCFG_DMARX_MASK; - } -} - -/*! - * brief Sets the baud rate for SPI transfer. This is only used in master. - * - * param base SPI base pointer - * param baudrate_Bps baud rate needed in Hz. - * param srcClock_Hz SPI source clock frequency in Hz. - */ -status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) -{ - uint32_t tmpDiv; - - /* assert params */ - assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))); - if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* calculate baudrate, round up the result */ - tmpDiv = ((srcClock_Hz * 10U) / baudrate_Bps + 5U) / 10U - 1U; - if (tmpDiv > 0xFFFFU) - { - return kStatus_SPI_BaudrateNotSupport; - } - base->DIV &= ~SPI_DIV_DIVVAL_MASK; - base->DIV |= SPI_DIV_DIVVAL(tmpDiv); - return kStatus_Success; -} - -/*! - * brief Writes a data into the SPI data register. - * - * param base SPI base pointer - * param data needs to be write. - * param configFlags transfer configuration options ref spi_xfer_option_t - */ -void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags) -{ - uint32_t control = 0U; - uint32_t instance; - - /* check params */ - assert(NULL != base); - /* get and check instance */ - instance = SPI_GetInstance(base); - - /* set data width */ - control |= (uint32_t)SPI_FIFOWR_LEN((g_configs[instance].dataWidth)); - /* set sssel */ - control |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL((uint32_t)(g_configs[instance].sselNum)))); - /* mask configFlags */ - control |= (configFlags & (uint32_t)SPI_FIFOWR_FLAGS_MASK); - /* control should not affect lower 16 bits */ - assert(0U == (control & 0xFFFFU)); - base->FIFOWR = data | control; -} - -/*! - * brief Initializes the SPI master handle. - * - * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * param base SPI peripheral base address. - * param handle SPI handle pointer. - * param callback Callback function. - * param userData User data. - */ -status_t SPI_MasterTransferCreateHandle(SPI_Type *base, - spi_master_handle_t *handle, - spi_master_callback_t callback, - void *userData) -{ - /* check 'base' */ - assert(NULL != base); - /* check 'handle' */ - assert(NULL != handle); - - uint32_t instance; - spi_to_flexcomm_t handler; - - /* get flexcomm instance by 'base' param */ - instance = SPI_GetInstance(base); - - (void)memset(handle, 0, sizeof(*handle)); - /* Initialize the handle */ - if ((base->CFG & SPI_CFG_MASTER_MASK) != 0U) - { - handler.spi_master_handler = SPI_MasterTransferHandleIRQ; - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - } - else - { - handler.spi_slave_handler = SPI_SlaveTransferHandleIRQ; - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - } - - handle->dataWidth = (uint8_t)(g_configs[instance].dataWidth); - /* in slave mode, the sselNum is not important */ - handle->sselNum = (uint8_t)(g_configs[instance].sselNum); - handle->txWatermark = (uint8_t)SPI_FIFOTRIG_TXLVL_GET(base); - handle->rxWatermark = (uint8_t)SPI_FIFOTRIG_RXLVL_GET(base); - handle->callback = callback; - handle->userData = userData; - - /* Enable SPI NVIC */ - (void)EnableIRQ(s_spiIRQ[instance]); - - return kStatus_Success; -} - -/*! - * brief Transfers a block of data using a polling method. - * - * param base SPI base pointer - * param xfer pointer to spi_xfer_config_t structure - * retval kStatus_Success Successfully start a transfer. - * retval kStatus_InvalidArgument Input argument is invalid. - * retval kStatus_SPI_Timeout The transfer timed out and was aborted. - */ -status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) -{ - uint32_t instance; - uint32_t tx_ctrl = 0U, last_ctrl = 0U; - uint32_t tmp32, rxRemainingBytes, txRemainingBytes, dataWidth; - uint32_t toReceiveCount = 0; - uint8_t *txData, *rxData; - uint32_t fifoDepth; -#if SPI_RETRY_TIMES - uint32_t waitTimes = SPI_RETRY_TIMES; -#endif - - /* check params */ - assert(!((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); - if ((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) - { - return kStatus_InvalidArgument; - } - - fifoDepth = SPI_FIFO_DEPTH(base); - txData = xfer->txData; - rxData = xfer->rxData; - txRemainingBytes = (txData != NULL) ? xfer->dataSize : 0U; - rxRemainingBytes = (rxData != NULL) ? xfer->dataSize : 0U; - - instance = SPI_GetInstance(base); - dataWidth = (uint32_t)(g_configs[instance].dataWidth); - - /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ - if ((dataWidth > (uint32_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U)) - { - return kStatus_InvalidArgument; - } - - /* clear tx/rx errors and empty FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - /* select slave to talk with */ - tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL((uint32_t)(g_configs[instance].sselNum)))); - /* set width of data - range asserted at entry */ - tx_ctrl |= SPI_FIFOWR_LEN(dataWidth); - /* delay for frames */ - tx_ctrl |= ((xfer->configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; - /* end of transfer */ - last_ctrl |= ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; - /* last index of loop */ - while ((txRemainingBytes != 0U) || (rxRemainingBytes != 0U) || (toReceiveCount != 0U)) - { -#if SPI_RETRY_TIMES - if (--waitTimes == 0U) - { - return kStatus_SPI_Timeout; - } -#endif - /* if rxFIFO is not empty */ - if ((base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) != 0U) - { - tmp32 = base->FIFORD; - /* rxBuffer is not empty */ - if (rxRemainingBytes != 0U) - { - *(rxData++) = (uint8_t)tmp32; - rxRemainingBytes--; - /* read 16 bits at once */ - if (dataWidth > 8U) - { - *(rxData++) = (uint8_t)(tmp32 >> 8); - rxRemainingBytes--; - } - } - /* decrease number of data expected to receive */ - toReceiveCount -= 1U; - } - /* transmit if txFIFO is not full and data to receive does not exceed FIFO depth */ - if (((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) != 0U) && (toReceiveCount < fifoDepth) && - ((txRemainingBytes != 0U) || (rxRemainingBytes >= SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1U)))) - { - /* txBuffer is not empty */ - if (txRemainingBytes != 0U) - { - tmp32 = *(txData++); - txRemainingBytes--; - /* write 16 bit at once */ - if (dataWidth > 8U) - { - tmp32 |= ((uint32_t)(*(txData++))) << 8U; - txRemainingBytes--; - } - if (txRemainingBytes == 0U) - { - tx_ctrl |= last_ctrl; - } - } - else - { - tmp32 = (uint32_t)s_dummyData[instance]; - tmp32 |= (uint32_t)s_dummyData[instance] << 8U; - /* last transfer */ - if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1U)) - { - tx_ctrl |= last_ctrl; - } - } - /* send data */ - tmp32 = tx_ctrl | tmp32; - base->FIFOWR = tmp32; - toReceiveCount += 1U; - } - } - /* wait if TX FIFO of previous transfer is not empty */ -#if SPI_RETRY_TIMES - waitTimes = SPI_RETRY_TIMES; - while ((0U == (base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) && (0U != --waitTimes)) -#else - while (0U == (base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) -#endif - { - } -#if SPI_RETRY_TIMES - if (waitTimes == 0U) - { - return kStatus_SPI_Timeout; - } -#endif - return kStatus_Success; -} - -/*! - * brief Performs a non-blocking SPI interrupt transfer. - * - * param base SPI peripheral base address. - * param handle pointer to spi_master_handle_t structure which stores the transfer state - * param xfer pointer to spi_xfer_config_t structure - * retval kStatus_Success Successfully start a transfer. - * retval kStatus_InvalidArgument Input argument is invalid. - * retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer) -{ - /* check params */ - assert( - !((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) - { - return kStatus_InvalidArgument; - } - - /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ - assert(!((handle->dataWidth > (uint8_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U))); - if ((handle->dataWidth > (uint8_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U)) - { - return kStatus_InvalidArgument; - } - - /* Check if SPI is busy */ - if (handle->state == (uint32_t)kStatus_SPI_Busy) - { - return kStatus_SPI_Busy; - } - - /* Set the handle information */ - handle->txData = xfer->txData; - handle->rxData = xfer->rxData; - /* set count */ - handle->txRemainingBytes = (xfer->txData != NULL) ? xfer->dataSize : 0U; - handle->rxRemainingBytes = (xfer->rxData != NULL) ? xfer->dataSize : 0U; - handle->totalByteCount = xfer->dataSize; - /* other options */ - handle->toReceiveCount = 0; - handle->configFlags = xfer->configFlags; - /* Set the SPI state to busy */ - handle->state = (uint32_t)kStatus_SPI_Busy; - /* clear FIFOs when transfer starts */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - /* enable generating txIRQ and rxIRQ, first transfer is fired by empty txFIFO */ - base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK; - return kStatus_Success; -} - -/*! - * brief Transfers a block of data using a polling method. - * - * This function will do a half-duplex transfer for SPI master, This is a blocking function, - * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, - * users can set transmit first or receive first. - * - * param base SPI base pointer - * param xfer pointer to spi_half_duplex_transfer_t structure - * return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer) -{ - assert(xfer != NULL); - - spi_transfer_t tempXfer = {0}; - status_t status; - - if (xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the pcs pin keep assert between transmit and receive. */ - if (xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); - } - else - { - tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; - } - - status = SPI_MasterTransferBlocking(base, &tempXfer); - - if (status != kStatus_Success) - { - return status; - } - - if (xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - /* SPI transfer blocking. */ - status = SPI_MasterTransferBlocking(base, &tempXfer); - - return status; -} - -/*! - * brief Performs a non-blocking SPI interrupt transfer. - * - * This function using polling way to do the first half transimission and using interrupts to - * do the second half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * param base SPI peripheral base address. - * param handle pointer to spi_master_handle_t structure which stores the transfer state - * param xfer pointer to spi_half_duplex_transfer_t structure - * return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, - spi_master_handle_t *handle, - spi_half_duplex_transfer_t *xfer) -{ - assert(xfer != NULL); - assert(handle != NULL); - spi_transfer_t tempXfer = {0}; - status_t status; - - if (xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the PCS pin keep assert between transmit and receive. */ - if (xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); - } - else - { - tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; - } - - status = SPI_MasterTransferBlocking(base, &tempXfer); - if (status != kStatus_Success) - { - return status; - } - - if (xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - status = SPI_MasterTransferNonBlocking(base, handle, &tempXfer); - - return status; -} - -/*! - * brief Gets the master transfer count. - * - * This function gets the master transfer count. - * - * param base SPI peripheral base address. - * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * param count The number of bytes transferred by using the non-blocking transaction. - * return status of status_t. - */ -status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count) -{ - assert(NULL != handle); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != (uint32_t)kStatus_SPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - *count = handle->totalByteCount - handle->rxRemainingBytes; - return kStatus_Success; -} - -/*! - * brief SPI master aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * param base SPI peripheral base address. - * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle) -{ - assert(NULL != handle); - - /* Disable interrupt requests*/ - base->FIFOINTENSET &= ~(SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK); - /* Empty FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - - handle->state = (uint32_t)kStatus_SPI_Idle; - handle->txRemainingBytes = 0U; - handle->rxRemainingBytes = 0U; -} - -static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *handle) -{ - uint32_t tx_ctrl = 0U, last_ctrl = 0U, tmp32; - bool loopContinue; - uint32_t fifoDepth; - /* Get flexcomm instance by 'base' param */ - uint32_t instance = SPI_GetInstance(base); - size_t txRemainingBytes; - size_t rxRemainingBytes; - uint8_t toReceiveCount; - - /* check params */ - assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData))); - - fifoDepth = SPI_FIFO_DEPTH(base); - /* select slave to talk with */ - tx_ctrl |= ((uint32_t)SPI_DEASSERT_ALL & (uint32_t)SPI_ASSERTNUM_SSEL(handle->sselNum)); - /* set width of data */ - tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth); - /* delay for frames */ - tx_ctrl |= ((handle->configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; - /* end of transfer */ - last_ctrl |= ((handle->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; - do - { - loopContinue = false; - - /* rxFIFO is not empty */ - if ((base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) != 0U) - { - tmp32 = base->FIFORD; - /* rxBuffer is not empty */ - if (handle->rxRemainingBytes != 0U) - { - /* low byte must go first */ - *(handle->rxData++) = (uint8_t)tmp32; - handle->rxRemainingBytes--; - /* read 16 bits at once */ - if (handle->dataWidth > (uint8_t)kSPI_Data8Bits) - { - *(handle->rxData++) = (uint8_t)(tmp32 >> 8); - handle->rxRemainingBytes--; - } - } - - /* decrease number of data expected to receive */ - handle->toReceiveCount -= 1; - loopContinue = true; - } - - /* - txFIFO is not full - * - we cannot cause rxFIFO overflow by sending more data than is the depth of FIFO - * - txBuffer is not empty or the next 'toReceiveCount' data can fit into rxBuffer - */ - txRemainingBytes = handle->txRemainingBytes; - rxRemainingBytes = handle->rxRemainingBytes; - toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; - if (((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) != 0U) && ((uint32_t)toReceiveCount < fifoDepth) && - ((txRemainingBytes != 0U) || - (rxRemainingBytes >= SPI_COUNT_TO_BYTES(handle->dataWidth, (uint32_t)toReceiveCount + 1U)))) - { - /* txBuffer is not empty */ - if ((txRemainingBytes != 0U) && (handle->txData != NULL)) - { - /* low byte must go first */ - tmp32 = *(handle->txData++); - handle->txRemainingBytes--; - txRemainingBytes = handle->txRemainingBytes; - /* write 16 bit at once */ - if (handle->dataWidth > (uint8_t)kSPI_Data8Bits) - { - tmp32 |= ((uint32_t)(*(handle->txData++))) << 8U; - handle->txRemainingBytes--; - txRemainingBytes = handle->txRemainingBytes; - } - /* last transfer */ - if (handle->txRemainingBytes == 0U) - { - tx_ctrl |= last_ctrl; - } - } - else - { - tmp32 = (uint32_t)s_dummyData[instance]; - tmp32 |= (uint32_t)s_dummyData[instance] << 8U; - /* last transfer */ - if (rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, (uint32_t)toReceiveCount + 1U)) - { - tx_ctrl |= last_ctrl; - } - } - /* send data */ - tmp32 = tx_ctrl | tmp32; - base->FIFOWR = tmp32; - /* increase number of expected data to receive */ - handle->toReceiveCount += 1; - toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; - loopContinue = true; - } - } while (loopContinue); -} - -/*! - * brief Interrupts the handler for the SPI. - * - * param base SPI peripheral base address. - * param handle pointer to spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle) -{ - assert((NULL != base) && (NULL != handle)); - size_t txRemainingBytes; - uint8_t toReceiveCount; - - /* IRQ behaviour: - * - first interrupt is triggered by empty txFIFO. The transfer function - * then tries empty rxFIFO and fill txFIFO interleaved that results to - * strategy to process as many items as possible. - * - the next IRQs can be: - * rxIRQ from nonempty rxFIFO which requires to empty rxFIFO. - * txIRQ from empty txFIFO which requires to refill txFIFO. - * - last interrupt is triggered by empty txFIFO. The last state is - * known by empty rxBuffer and txBuffer. If there is nothing to receive - * or send - both operations have been finished and interrupts can be - * disabled. - */ - - /* Data to send or read or expected to receive */ - if ((handle->txRemainingBytes != 0U) || (handle->rxRemainingBytes != 0U) || (handle->toReceiveCount != 0)) - { - /* Transmit or receive data */ - SPI_TransferHandleIRQInternal(base, handle); - /* No data to send or read or receive. Transfer ends. Set txTrigger to 0 level and - * enable txIRQ to confirm when txFIFO becomes empty */ - if ((0U == handle->txRemainingBytes) && (0U == handle->rxRemainingBytes) && (0 == handle->toReceiveCount)) - { - base->FIFOTRIG = base->FIFOTRIG & (~SPI_FIFOTRIG_TXLVL_MASK); - base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK; - } - else - { - uint32_t rxRemainingCount = SPI_BYTES_TO_COUNT(handle->dataWidth, handle->rxRemainingBytes); - /* If, there are no data to send or rxFIFO is already filled with necessary number of dummy data, - * disable txIRQ. From this point only rxIRQ is used to receive data without any transmission */ - toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; - if ((0U == handle->txRemainingBytes) && (rxRemainingCount <= toReceiveCount)) - { - base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXLVL_MASK; - } - /* Nothing to receive or transmit, but we still have pending data which are bellow rxLevel. - * Cannot clear rxFIFO, txFIFO might be still active */ - if (rxRemainingCount == 0U) - { - txRemainingBytes = handle->txRemainingBytes; - if ((txRemainingBytes == 0U) && (toReceiveCount != 0U) && - (toReceiveCount < SPI_FIFOTRIG_RXLVL_GET(base) + 1U)) - { - base->FIFOTRIG = (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | - SPI_FIFOTRIG_RXLVL((uint32_t)toReceiveCount - 1U); - } - } - else - { - /* Expected to receive less data than rxLevel value, we have to update rxLevel */ - if (rxRemainingCount < (SPI_FIFOTRIG_RXLVL_GET(base) + 1U)) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(rxRemainingCount - 1U); - } - } - } - } - else - { - /* Empty txFIFO is confirmed. Disable IRQs and restore triggers values */ - base->FIFOINTENCLR = SPI_FIFOINTENCLR_RXLVL_MASK | SPI_FIFOINTENCLR_TXLVL_MASK; - base->FIFOTRIG = (base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_RXLVL_MASK))) | - SPI_FIFOTRIG_RXLVL(handle->rxWatermark) | SPI_FIFOTRIG_TXLVL(handle->txWatermark); - /* set idle state and call user callback */ - handle->state = (uint32_t)kStatus_SPI_Idle; - if (handle->callback != NULL) - { - (handle->callback)(base, handle, handle->state, handle->userData); - } - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi.h deleted file mode 100644 index 2320e574cc9..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi.h +++ /dev/null @@ -1,746 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SPI_H_ -#define _FSL_SPI_H_ - -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/*! - * @addtogroup spi_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SPI driver version. */ -#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) -/*@}*/ - -/*! @brief Global variable for dummy data value setting. */ -extern volatile uint8_t s_dummyData[]; - -#ifndef SPI_DUMMYDATA -/*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */ -#define SPI_DUMMYDATA (0xFFU) -#endif - -/*! @brief Retry times for waiting flag. */ -#ifndef SPI_RETRY_TIMES -#define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ -#endif - -#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFFUL) -#define SPI_CTRLMASK (0xFFFF0000U) - -#define SPI_ASSERTNUM_SSEL(n) ((~(1UL << ((n) + 16UL))) & 0xF0000UL) -#define SPI_DEASSERTNUM_SSEL(n) (1UL << ((n) + 16UL)) -#define SPI_DEASSERT_ALL (0xF0000UL) - -#define SPI_FIFOWR_FLAGS_MASK (~(SPI_DEASSERT_ALL | SPI_FIFOWR_TXDATA_MASK | SPI_FIFOWR_LEN_MASK)) - -#define SPI_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_TXLVL_MASK) >> SPI_FIFOTRIG_TXLVL_SHIFT) -#define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT) - -/*! @brief SPI transfer option.*/ -typedef enum _spi_xfer_option -{ - kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), /*!< A delay may be inserted, defined in the DLY register.*/ - kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< SSEL will be deasserted at the end of a transfer */ -} spi_xfer_option_t; - -/*! @brief SPI data shifter direction options.*/ -typedef enum _spi_shift_direction -{ - kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */ - kSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. */ -} spi_shift_direction_t; - -/*! @brief SPI clock polarity configuration.*/ -typedef enum _spi_clock_polarity -{ - kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */ - kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */ -} spi_clock_polarity_t; - -/*! @brief SPI clock phase configuration.*/ -typedef enum _spi_clock_phase -{ - kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first - * cycle of a data transfer. */ - kSPI_ClockPhaseSecondEdge /*!< First edge on SCK occurs at the start of the - * first cycle of a data transfer. */ -} spi_clock_phase_t; - -/*! @brief txFIFO watermark values */ -typedef enum _spi_txfifo_watermark -{ - kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */ - kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */ - kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */ - kSPI_TxFifo3 = 3, /*!< SPI tx watermark at 3 items */ - kSPI_TxFifo4 = 4, /*!< SPI tx watermark at 4 items */ - kSPI_TxFifo5 = 5, /*!< SPI tx watermark at 5 items */ - kSPI_TxFifo6 = 6, /*!< SPI tx watermark at 6 items */ - kSPI_TxFifo7 = 7, /*!< SPI tx watermark at 7 items */ -} spi_txfifo_watermark_t; - -/*! @brief rxFIFO watermark values */ -typedef enum _spi_rxfifo_watermark -{ - kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */ - kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */ - kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */ - kSPI_RxFifo4 = 3, /*!< SPI rx watermark at 4 items */ - kSPI_RxFifo5 = 4, /*!< SPI rx watermark at 5 items */ - kSPI_RxFifo6 = 5, /*!< SPI rx watermark at 6 items */ - kSPI_RxFifo7 = 6, /*!< SPI rx watermark at 7 items */ - kSPI_RxFifo8 = 7, /*!< SPI rx watermark at 8 items */ -} spi_rxfifo_watermark_t; - -/*! @brief Transfer data width */ -typedef enum _spi_data_width -{ - kSPI_Data4Bits = 3, /*!< 4 bits data width */ - kSPI_Data5Bits = 4, /*!< 5 bits data width */ - kSPI_Data6Bits = 5, /*!< 6 bits data width */ - kSPI_Data7Bits = 6, /*!< 7 bits data width */ - kSPI_Data8Bits = 7, /*!< 8 bits data width */ - kSPI_Data9Bits = 8, /*!< 9 bits data width */ - kSPI_Data10Bits = 9, /*!< 10 bits data width */ - kSPI_Data11Bits = 10, /*!< 11 bits data width */ - kSPI_Data12Bits = 11, /*!< 12 bits data width */ - kSPI_Data13Bits = 12, /*!< 13 bits data width */ - kSPI_Data14Bits = 13, /*!< 14 bits data width */ - kSPI_Data15Bits = 14, /*!< 15 bits data width */ - kSPI_Data16Bits = 15, /*!< 16 bits data width */ -} spi_data_width_t; - -/*! @brief Slave select */ -typedef enum _spi_ssel -{ - kSPI_Ssel0 = 0, /*!< Slave select 0 */ - kSPI_Ssel1 = 1, /*!< Slave select 1 */ - kSPI_Ssel2 = 2, /*!< Slave select 2 */ - kSPI_Ssel3 = 3, /*!< Slave select 3 */ -} spi_ssel_t; - -/*! @brief ssel polarity */ -typedef enum _spi_spol -{ - kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0(1), - kSPI_Spol1ActiveHigh = SPI_CFG_SPOL1(1), - kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2(1), -#if defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) && (FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) - kSPI_SpolActiveAllHigh = (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh), -#else - kSPI_Spol3ActiveHigh = SPI_CFG_SPOL3(1), - kSPI_SpolActiveAllHigh = - (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh | kSPI_Spol3ActiveHigh), -#endif - kSPI_SpolActiveAllLow = 0, -} spi_spol_t; - -/*! - * @brief SPI delay time configure structure. - * Note: - * The DLY register controls several programmable delays related to SPI signalling, - * it stands for how many SPI clock time will be inserted. - * The maxinun value of these delay time is 15. - */ -typedef struct _spi_delay_config -{ - uint8_t preDelay; /*!< Delay between SSEL assertion and the beginning of transfer. */ - uint8_t postDelay; /*!< Delay between the end of transfer and SSEL deassertion. */ - uint8_t frameDelay; /*!< Delay between frame to frame. */ - uint8_t transferDelay; /*!< Delay between transfer to transfer. */ -} spi_delay_config_t; - -/*! @brief SPI master user configure structure.*/ -typedef struct _spi_master_config -{ - bool enableLoopback; /*!< Enable loopback for test purpose */ - bool enableMaster; /*!< Enable SPI at initialization time */ - spi_clock_polarity_t polarity; /*!< Clock polarity */ - spi_clock_phase_t phase; /*!< Clock phase */ - spi_shift_direction_t direction; /*!< MSB or LSB */ - uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */ - spi_data_width_t dataWidth; /*!< Width of the data */ - spi_ssel_t sselNum; /*!< Slave select number */ - spi_spol_t sselPol; /*!< Configure active CS polarity */ - uint8_t txWatermark; /*!< txFIFO watermark */ - uint8_t rxWatermark; /*!< rxFIFO watermark */ - spi_delay_config_t delayConfig; /*!< Delay configuration. */ -} spi_master_config_t; - -/*! @brief SPI slave user configure structure.*/ -typedef struct _spi_slave_config -{ - bool enableSlave; /*!< Enable SPI at initialization time */ - spi_clock_polarity_t polarity; /*!< Clock polarity */ - spi_clock_phase_t phase; /*!< Clock phase */ - spi_shift_direction_t direction; /*!< MSB or LSB */ - spi_data_width_t dataWidth; /*!< Width of the data */ - spi_spol_t sselPol; /*!< Configure active CS polarity */ - uint8_t txWatermark; /*!< txFIFO watermark */ - uint8_t rxWatermark; /*!< rxFIFO watermark */ -} spi_slave_config_t; - -/*! @brief SPI transfer status.*/ -enum -{ - kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0), /*!< SPI bus is busy */ - kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1), /*!< SPI is idle */ - kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI error */ - kStatus_SPI_BaudrateNotSupport = - MAKE_STATUS(kStatusGroup_LPC_SPI, 3), /*!< Baudrate is not support in current clock source */ - kStatus_SPI_Timeout = MAKE_STATUS(kStatusGroup_LPC_SPI, 4) /*!< SPI timeout polling status flags. */ -}; - -/*! @brief SPI interrupt sources.*/ -enum _spi_interrupt_enable -{ - kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, /*!< Rx level interrupt */ - kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, /*!< Tx level interrupt */ -}; - -/*! @brief SPI status flags.*/ -enum _spi_statusflags -{ - kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK, /*!< txFifo is empty */ - kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK, /*!< txFifo is not full */ - kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, /*!< rxFIFO is not empty */ - kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK, /*!< rxFIFO is full */ -}; - -/*! @brief SPI transfer structure */ -typedef struct _spi_transfer -{ - uint8_t *txData; /*!< Send buffer */ - uint8_t *rxData; /*!< Receive buffer */ - uint32_t configFlags; /*!< Additional option to control transfer, @ref spi_xfer_option_t. */ - size_t dataSize; /*!< Transfer bytes */ -} spi_transfer_t; - -/*! @brief SPI half-duplex(master only) transfer structure */ -typedef struct _spi_half_duplex_transfer -{ - uint8_t *txData; /*!< Send buffer */ - uint8_t *rxData; /*!< Receive buffer */ - size_t txDataSize; /*!< Transfer bytes for transmit */ - size_t rxDataSize; /*!< Transfer bytes */ - uint32_t configFlags; /*!< Transfer configuration flags, @ref spi_xfer_option_t. */ - bool isPcsAssertInTransfer; /*!< If PCS pin keep assert between transmit and receive. true for assert and false for - deassert. */ - bool isTransmitFirst; /*!< True for transmit first and false for receive first. */ -} spi_half_duplex_transfer_t; - -/*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */ -typedef struct _spi_config -{ - spi_data_width_t dataWidth; - spi_ssel_t sselNum; -} spi_config_t; - -/*! @brief Master handle type */ -typedef struct _spi_master_handle spi_master_handle_t; - -/*! @brief Slave handle type */ -typedef spi_master_handle_t spi_slave_handle_t; - -/*! @brief SPI master callback for finished transmit */ -typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI slave callback for finished transmit */ -typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI transfer handle structure */ -struct _spi_master_handle -{ - uint8_t *volatile txData; /*!< Transfer buffer */ - uint8_t *volatile rxData; /*!< Receive buffer */ - volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */ - volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */ - volatile int8_t toReceiveCount; /*!< The number of data expected to receive in data width. Since the received count - and sent count should be the same to complete the transfer, if the sent count is - x and the received count is y, toReceiveCount is x-y. */ - size_t totalByteCount; /*!< A number of transfer bytes */ - volatile uint32_t state; /*!< SPI internal state */ - spi_master_callback_t callback; /*!< SPI callback */ - void *userData; /*!< Callback parameter */ - uint8_t dataWidth; /*!< Width of the data [Valid values: 1 to 16] */ - uint8_t sselNum; /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */ - uint32_t configFlags; /*!< Additional option to control transfer */ - uint8_t txWatermark; /*!< txFIFO watermark */ - uint8_t rxWatermark; /*!< rxFIFO watermark */ -}; - -/*! @brief Typedef for master interrupt handler. */ -typedef void (*flexcomm_spi_master_irq_handler_t)(SPI_Type *base, spi_master_handle_t *handle); - -/*! @brief Typedef for slave interrupt handler. */ -typedef void (*flexcomm_spi_slave_irq_handler_t)(SPI_Type *base, spi_slave_handle_t *handle); -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @brief Returns instance number for SPI peripheral base address. */ -uint32_t SPI_GetInstance(SPI_Type *base); - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Sets the SPI master configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). - * User may use the initialized structure unchanged in SPI_MasterInit(), or modify - * some fields of the structure before calling SPI_MasterInit(). After calling this API, - * the master is ready to transfer. - * Example: - @code - spi_master_config_t config; - SPI_MasterGetDefaultConfig(&config); - @endcode - * - * @param config pointer to master config structure - */ -void SPI_MasterGetDefaultConfig(spi_master_config_t *config); - -/*! - * @brief Initializes the SPI with master configuration. - * - * The configuration structure can be filled by user from scratch, or be set with default - * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. - * Example - @code - spi_master_config_t config = { - .baudRate_Bps = 400000, - ... - }; - SPI_MasterInit(SPI0, &config); - @endcode - * - * @param base SPI base pointer - * @param config pointer to master configuration structure - * @param srcClock_Hz Source clock frequency. - */ -status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Sets the SPI slave configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). - * Modify some fields of the structure before calling SPI_SlaveInit(). - * Example: - @code - spi_slave_config_t config; - SPI_SlaveGetDefaultConfig(&config); - @endcode - * - * @param config pointer to slave configuration structure - */ -void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config); - -/*! - * @brief Initializes the SPI with slave configuration. - * - * The configuration structure can be filled by user from scratch or be set with - * default values by SPI_SlaveGetDefaultConfig(). - * After calling this API, the slave is ready to transfer. - * Example - @code - spi_slave_config_t config = { - .polarity = flexSPIClockPolarity_ActiveHigh; - .phase = flexSPIClockPhase_FirstEdge; - .direction = flexSPIMsbFirst; - ... - }; - SPI_SlaveInit(SPI0, &config); - @endcode - * - * @param base SPI base pointer - * @param config pointer to slave configuration structure - */ -status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config); - -/*! - * @brief De-initializes the SPI. - * - * Calling this API resets the SPI module, gates the SPI clock. - * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. - * - * @param base SPI base pointer - */ -void SPI_Deinit(SPI_Type *base); - -/*! - * @brief Enable or disable the SPI Master or Slave - * @param base SPI base pointer - * @param enable or disable ( true = enable, false = disable) - */ -static inline void SPI_Enable(SPI_Type *base, bool enable) -{ - if (enable) - { - base->CFG |= SPI_CFG_ENABLE_MASK; - } - else - { - base->CFG &= ~SPI_CFG_ENABLE_MASK; - } -} - -/*! @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the status flag. - * - * @param base SPI base pointer - * @return SPI Status, use status flag to AND @ref _spi_statusflags could get the related status. - */ -static inline uint32_t SPI_GetStatusFlags(SPI_Type *base) -{ - assert(NULL != base); - return base->FIFOSTAT; -} - -/*! @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the interrupt for the SPI. - * - * @param base SPI base pointer - * @param irqs SPI interrupt source. The parameter can be any combination of the following values: - * @arg kSPI_RxLvlIrq - * @arg kSPI_TxLvlIrq - */ -static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs) -{ - assert(NULL != base); - base->FIFOINTENSET = irqs; -} - -/*! - * @brief Disables the interrupt for the SPI. - * - * @param base SPI base pointer - * @param irqs SPI interrupt source. The parameter can be any combination of the following values: - * @arg kSPI_RxLvlIrq - * @arg kSPI_TxLvlIrq - */ -static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs) -{ - assert(NULL != base); - base->FIFOINTENCLR = irqs; -} - -/*! @} */ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Enables the DMA request from SPI txFIFO. - * - * @param base SPI base pointer - * @param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableTxDMA(SPI_Type *base, bool enable); - -/*! - * @brief Enables the DMA request from SPI rxFIFO. - * - * @param base SPI base pointer - * @param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableRxDMA(SPI_Type *base, bool enable); - -/*! @} */ - -/*! - * @name Bus Operations - * @{ - */ -/*! - * @brief Returns the configurations. - * - * @param base SPI peripheral address. - * @return return configurations which contain datawidth and SSEL numbers. - * return data type is a pointer of spi_config_t. - */ -void *SPI_GetConfig(SPI_Type *base); - -/*! - * @brief Sets the baud rate for SPI transfer. This is only used in master. - * - * @param base SPI base pointer - * @param baudrate_Bps baud rate needed in Hz. - * @param srcClock_Hz SPI source clock frequency in Hz. - */ -status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Writes a data into the SPI data register. - * - * @param base SPI base pointer - * @param data needs to be write. - * @param configFlags transfer configuration options @ref spi_xfer_option_t - */ -void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags); - -/*! - * @brief Gets a data from the SPI data register. - * - * @param base SPI base pointer - * @return Data in the register. - */ -static inline uint32_t SPI_ReadData(SPI_Type *base) -{ - assert(NULL != base); - return base->FIFORD; -} - -/*! - * @brief Set delay time for transfer. - * the delay uint is SPI clock time, maximum value is 0xF. - * @param base SPI base pointer - * @param config configuration for delay option @ref spi_delay_config_t. - */ -static inline void SPI_SetTransferDelay(SPI_Type *base, const spi_delay_config_t *config) -{ - assert(NULL != base); - assert(NULL != config); - base->DLY = (SPI_DLY_PRE_DELAY(config->preDelay) | SPI_DLY_POST_DELAY(config->postDelay) | - SPI_DLY_FRAME_DELAY(config->frameDelay) | SPI_DLY_TRANSFER_DELAY(config->transferDelay)); -} - -/*! - * @brief Set up the dummy data. - * - * @param base SPI peripheral address. - * @param dummyData Data to be transferred when tx buffer is NULL. - */ -void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData); - -/*! @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the SPI master handle. - * - * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback Callback function. - * @param userData User data. - */ -status_t SPI_MasterTransferCreateHandle(SPI_Type *base, - spi_master_handle_t *handle, - spi_master_callback_t callback, - void *userData); - -/*! - * @brief Transfers a block of data using a polling method. - * - * @param base SPI base pointer - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Timeout The transfer timed out and was aborted. - */ -status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer); - -/*! - * @brief Performs a non-blocking SPI interrupt transfer. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer); - -/*! - * @brief Transfers a block of data using a polling method. - * - * This function will do a half-duplex transfer for SPI master, This is a blocking function, - * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, - * users can set transmit first or receive first. - * - * @param base SPI base pointer - * @param xfer pointer to spi_half_duplex_transfer_t structure - * @return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer); - -/*! - * @brief Performs a non-blocking SPI interrupt transfer. - * - * This function using polling way to do the first half transimission and using interrupts to - * do the second half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_half_duplex_transfer_t structure - * @return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, - spi_master_handle_t *handle, - spi_half_duplex_transfer_t *xfer); - -/*! - * @brief Gets the master transfer count. - * - * This function gets the master transfer count. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * @param count The number of bytes transferred by using the non-blocking transaction. - * @return status of status_t. - */ -status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count); - -/*! - * @brief SPI master aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle); - -/*! - * @brief Interrupts the handler for the SPI. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle); - -/*! - * @brief Initializes the SPI slave handle. - * - * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback Callback function. - * @param userData User data. - */ -static inline status_t SPI_SlaveTransferCreateHandle(SPI_Type *base, - spi_slave_handle_t *handle, - spi_slave_callback_t callback, - void *userData) -{ - return SPI_MasterTransferCreateHandle(base, handle, callback, userData); -} - -/*! - * @brief Performs a non-blocking SPI slave interrupt transfer. - * - * @note The API returns immediately after the transfer initialization is finished. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer) -{ - return SPI_MasterTransferNonBlocking(base, handle, xfer); -} - -/*! - * @brief Gets the slave transfer count. - * - * This function gets the slave transfer count. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * @param count The number of bytes transferred by using the non-blocking transaction. - * @return status of status_t. - */ -static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count) -{ - return SPI_MasterTransferGetCount(base, (spi_master_handle_t *)handle, count); -} - -/*! - * @brief SPI slave aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state. - */ -static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle) -{ - SPI_MasterTransferAbort(base, (spi_master_handle_t *)handle); -} - -/*! - * @brief Interrupts a handler for the SPI slave. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_slave_handle_t structure which stores the transfer state - */ -static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle) -{ - SPI_MasterTransferHandleIRQ(base, handle); -} - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_SPI_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi_dma.c deleted file mode 100644 index ed0aaa6a9fa..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi_dma.c +++ /dev/null @@ -1,568 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_spi_dma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi_dma" -#endif - -/*configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; - *fifowr |= ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; -} - -static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr) -{ - *fifowr |= ((uint32_t)SPI_DEASSERT_ALL & (~(uint32_t)SPI_DEASSERTNUM_SSEL((uint32_t)config->sselNum))); - /* set width of data - range asserted at entry */ - *fifowr |= SPI_FIFOWR_LEN(config->dataWidth); -} - -static void PrepareTxLastWord(spi_transfer_t *xfer, uint32_t *txLastWord, spi_config_t *config) -{ - if (config->dataWidth > kSPI_Data8Bits) - { - *txLastWord = (((uint32_t)xfer->txData[xfer->dataSize - 1U] << 8U) | (xfer->txData[xfer->dataSize - 2U])); - } - else - { - *txLastWord = xfer->txData[xfer->dataSize - 1U]; - } - XferToFifoWR(xfer, txLastWord); - SpiConfigToFifoWR(config, txLastWord); -} - -static void SPI_SetupDummy(SPI_Type *base, spi_dma_txdummy_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p) -{ - uint32_t instance = SPI_GetInstance(base); - uint32_t dummydata = (uint32_t)s_dummyData[instance]; - dummydata |= (uint32_t)s_dummyData[instance] << 8U; - - dummy->word = dummydata; - dummy->lastWord = dummydata; - - XferToFifoWR(xfer, &dummy->word); - XferToFifoWR(xfer, &dummy->lastWord); - SpiConfigToFifoWR(spi_config_p, &dummy->word); - SpiConfigToFifoWR(spi_config_p, &dummy->lastWord); - /* Clear the end of transfer bit for continue word transfer. */ - dummy->word &= (~(uint32_t)kSPI_FrameAssert); -} - -/*! - * brief Initialize the SPI master DMA handle. - * - * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * param base SPI peripheral base address. - * param handle SPI handle pointer. - * param callback User callback function called at the end of a transfer. - * param userData User data for callback. - * param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle) -{ - uint32_t instance; - - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } - /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - instance = SPI_GetInstance(base); - - (void)memset(handle, 0, sizeof(*handle)); - /* Set spi base to handle */ - handle->txHandle = txHandle; - handle->rxHandle = rxHandle; - handle->callback = callback; - handle->userData = userData; - - /* Set SPI state to idle */ - handle->state = (uint8_t)kSPI_Idle; - - /* Set handle to global state */ - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - /* Install callback for Tx dma channel */ - DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]); - DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]); - - return kStatus_Success; -} - -/*! - * brief Perform a non-blocking SPI transfer using DMA. - * - * note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * param base SPI peripheral base address. - * param handle SPI DMA handle pointer. - * param xfer Pointer to dma transfer structure. - * retval kStatus_Success Successfully start a transfer. - * retval kStatus_InvalidArgument Input argument is invalid. - * retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) -{ - assert(!((NULL == handle) || (NULL == xfer))); - - uint32_t instance; - status_t result = kStatus_Success; - spi_config_t *spi_config_p; - uint32_t address; - - if ((NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - - /* Byte size is zero. */ - if (xfer->dataSize == 0U) - { - return kStatus_InvalidArgument; - } - /* cannot get instance from base address */ - instance = SPI_GetInstance(base); - - /* Check if the device is busy */ - if (handle->state == (uint8_t)kSPI_Busy) - { - return kStatus_SPI_Busy; - } - else - { - /* Clear FIFOs before transfer. */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - - dma_transfer_config_t xferConfig = {0}; - spi_config_p = (spi_config_t *)SPI_GetConfig(base); - - handle->state = (uint8_t)kSPI_Busy; - handle->transferSize = xfer->dataSize; - - /* receive */ - SPI_EnableRxDMA(base, true); - address = (uint32_t)&base->FIFORD; - if (xfer->rxData != NULL) - { - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, xfer->rxData, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_PeripheralToMemory, NULL); - } - else - { - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, &s_rxDummy, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_StaticToStatic, NULL); - } - (void)DMA_SubmitTransfer(handle->rxHandle, &xferConfig); - handle->rxInProgress = true; - DMA_StartTransfer(handle->rxHandle); - - /* transmit */ - SPI_EnableTxDMA(base, true); - address = (uint32_t)&base->FIFOWR; - if (xfer->txData != NULL) - { - if ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) - { - PrepareTxLastWord(xfer, &s_txLastWord[instance], spi_config_p); - } - /* If end of tranfer function is enabled and data transfer frame is bigger then 1, use dma - * descriptor to send the last data. - */ - if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2U) : (xfer->dataSize > 1U))) - { - dma_xfercfg_t tmp_xfercfg; - tmp_xfercfg.valid = true; - tmp_xfercfg.swtrig = true; - tmp_xfercfg.intA = true; - tmp_xfercfg.byteWidth = 4U; - tmp_xfercfg.srcInc = 0; - tmp_xfercfg.dstInc = 0; - tmp_xfercfg.transferCount = 1; - tmp_xfercfg.reload = false; - tmp_xfercfg.clrtrig = false; - tmp_xfercfg.intB = false; - /* Create chained descriptor to transmit last word */ - DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txLastWord[instance], - (uint32_t *)address, NULL); - - DMA_PrepareTransfer( - &xferConfig, xfer->txData, (uint32_t *)address, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2U) : (xfer->dataSize - 1U)), - kDMA_MemoryToPeripheral, &s_spi_descriptor_table[instance]); - /* Disable interrupts for first descriptor to avoid calling callback twice. */ - xferConfig.xfercfg.intA = false; - xferConfig.xfercfg.intB = false; - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - else - { - DMA_PrepareTransfer( - &xferConfig, xfer->txData, (uint32_t *)address, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_MemoryToPeripheral, NULL); - (void)DMA_SubmitTransfer(handle->txHandle, &xferConfig); - } - } - else - { - /* Setup tx dummy data. */ - SPI_SetupDummy(base, &s_txDummy[instance], xfer, spi_config_p); - if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2U) : (xfer->dataSize > 1U))) - { - dma_xfercfg_t tmp_xfercfg; - tmp_xfercfg.valid = true; - tmp_xfercfg.swtrig = true; - tmp_xfercfg.intA = true; - tmp_xfercfg.byteWidth = (uint8_t)sizeof(uint32_t); - tmp_xfercfg.srcInc = 0; - tmp_xfercfg.dstInc = 0; - tmp_xfercfg.transferCount = 1; - tmp_xfercfg.reload = false; - tmp_xfercfg.clrtrig = false; - tmp_xfercfg.intB = false; - /* Create chained descriptor to transmit last word */ - DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord, - (uint32_t *)address, NULL); - /* Use common API to setup first descriptor */ - DMA_PrepareTransfer( - &xferConfig, &s_txDummy[instance].word, (uint32_t *)address, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2U) : (xfer->dataSize - 1U)), - kDMA_StaticToStatic, &s_spi_descriptor_table[instance]); - /* Disable interrupts for first descriptor to avoid calling callback twice */ - xferConfig.xfercfg.intA = false; - xferConfig.xfercfg.intB = false; - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - else - { - DMA_PrepareTransfer( - &xferConfig, &s_txDummy[instance].word, (uint32_t *)address, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_StaticToStatic, NULL); - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - } - - handle->txInProgress = true; - uint32_t tmpData = 0U; - uint32_t writeAddress = (uint32_t) & (base->FIFOWR) + 2UL; - XferToFifoWR(xfer, &tmpData); - SpiConfigToFifoWR(spi_config_p, &tmpData); - - /* Setup the control info. - * Halfword writes to just the control bits (offset 0xE22) doesn't push anything into the FIFO. - * And the data access type of control bits must be uint16_t, byte writes or halfword writes to FIFOWR - * will push the data and the current control bits into the FIFO. - */ - if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize == 2U) : (xfer->dataSize == 1U))) - { - *(uint16_t *)writeAddress = (uint16_t)(tmpData >> 16U); - } - else - { - /* Clear the SPI_FIFOWR_EOT_MASK bit when data is not the last. */ - tmpData &= (~(uint32_t)kSPI_FrameAssert); - *(uint16_t *)writeAddress = (uint16_t)(tmpData >> 16U); - } - - DMA_StartTransfer(handle->txHandle); - } - - return result; -} - -/*! - * brief Transfers a block of data using a DMA method. - * - * This function using polling way to do the first half transimission and using DMA way to - * do the srcond half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * param base SPI base pointer - * param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. - * param transfer A pointer to the spi_half_duplex_transfer_t structure. - * return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer) -{ - assert((xfer != NULL) && (handle != NULL)); - spi_transfer_t tempXfer = {0}; - status_t status; - - if (xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the pcs pin keep assert between transmit and receive. */ - if (xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); - } - else - { - tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; - } - - status = SPI_MasterTransferBlocking(base, &tempXfer); - if (status != kStatus_Success) - { - return status; - } - - if (xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - status = SPI_MasterTransferDMA(base, handle, &tempXfer); - - return status; -} - -static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) -{ - spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; - spi_dma_handle_t *spiHandle = privHandle->handle; - SPI_Type *base = privHandle->base; - - /* change the state */ - spiHandle->rxInProgress = false; - - /* All finished, call the callback */ - if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) - { - spiHandle->state = (uint8_t)kSPI_Idle; - if (spiHandle->callback != NULL) - { - (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); - } - } -} - -static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) -{ - spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; - spi_dma_handle_t *spiHandle = privHandle->handle; - SPI_Type *base = privHandle->base; - - /* change the state */ - spiHandle->txInProgress = false; - - /* All finished, call the callback */ - if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) - { - spiHandle->state = (uint8_t)kSPI_Idle; - if (spiHandle->callback != NULL) - { - (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); - } - } -} - -/*! - * brief Abort a SPI transfer using DMA. - * - * param base SPI peripheral base address. - * param handle SPI DMA handle pointer. - */ -void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) -{ - assert(NULL != handle); - - /* Stop tx transfer first */ - DMA_AbortTransfer(handle->txHandle); - /* Then rx transfer */ - DMA_AbortTransfer(handle->rxHandle); - - /* Set the handle state */ - handle->txInProgress = false; - handle->rxInProgress = false; - handle->state = (uint8_t)kSPI_Idle; -} - -/*! - * brief Gets the master DMA transfer remaining bytes. - * - * This function gets the master DMA transfer remaining bytes. - * - * param base SPI peripheral base address. - * param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * param count A number of bytes transferred by the non-blocking transaction. - * return status of status_t. - */ -status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != (uint8_t)kSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - size_t bytes; - - bytes = DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel); - - *count = handle->transferSize - bytes; - - return kStatus_Success; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi_dma.h deleted file mode 100644 index 614c37d791a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi_dma.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SPI_DMA_H_ -#define _FSL_SPI_DMA_H_ - -#include "fsl_dma.h" -#include "fsl_spi.h" - -/*! - * @addtogroup spi_dma_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SPI DMA driver version 2.1.1. */ -#define FSL_SPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) -/*@}*/ - -typedef struct _spi_dma_handle spi_dma_handle_t; - -/*! @brief SPI DMA callback called at the end of transfer. */ -typedef void (*spi_dma_callback_t)(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI DMA transfer handle, users should not touch the content of the handle.*/ -struct _spi_dma_handle -{ - volatile bool txInProgress; /*!< Send transfer finished */ - volatile bool rxInProgress; /*!< Receive transfer finished */ - dma_handle_t *txHandle; /*!< DMA handler for SPI send */ - dma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ - uint8_t bytesPerFrame; /*!< Bytes in a frame for SPI transfer */ - spi_dma_callback_t callback; /*!< Callback for SPI DMA transfer */ - void *userData; /*!< User Data for SPI DMA callback */ - uint32_t state; /*!< Internal state of SPI DMA transfer */ - size_t transferSize; /*!< Bytes need to be transfer */ -}; - -/******************************************************************************* - * APIs - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name DMA Transactional - * @{ - */ - -/*! - * @brief Initialize the SPI master DMA handle. - * - * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback User callback function called at the end of a transfer. - * @param userData User data for callback. - * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle); - -/*! - * @brief Perform a non-blocking SPI transfer using DMA. - * - * @note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - * @param xfer Pointer to dma transfer structure. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer); - -/*! - * @brief Transfers a block of data using a DMA method. - * - * This function using polling way to do the first half transimission and using DMA way to - * do the srcond half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * @param base SPI base pointer - * @param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. - * @param xfer A pointer to the spi_half_duplex_transfer_t structure. - * @return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer); - -/*! - * @brief Initialize the SPI slave DMA handle. - * - * This function initializes the SPI slave DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback User callback function called at the end of a transfer. - * @param userData User data for callback. - * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -static inline status_t SPI_SlaveTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle) -{ - return SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle); -} - -/*! - * @brief Perform a non-blocking SPI transfer using DMA. - * - * @note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - * @param xfer Pointer to dma transfer structure. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -static inline status_t SPI_SlaveTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) -{ - return SPI_MasterTransferDMA(base, handle, xfer); -} - -/*! - * @brief Abort a SPI transfer using DMA. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - */ -void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle); - -/*! - * @brief Gets the master DMA transfer remaining bytes. - * - * This function gets the master DMA transfer remaining bytes. - * - * @param base SPI peripheral base address. - * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * @param count A number of bytes transferred by the non-blocking transaction. - * @return status of status_t. - */ -status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count); - -/*! - * @brief Abort a SPI transfer using DMA. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - */ -static inline void SPI_SlaveTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) -{ - SPI_MasterTransferAbortDMA(base, handle); -} - -/*! - * @brief Gets the slave DMA transfer remaining bytes. - * - * This function gets the slave DMA transfer remaining bytes. - * - * @param base SPI peripheral base address. - * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * @param count A number of bytes transferred by the non-blocking transaction. - * @return status of status_t. - */ -static inline status_t SPI_SlaveTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) -{ - return SPI_MasterTransferGetCountDMA(base, handle, count); -} - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_SPI_DMA_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sysctl.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sysctl.c deleted file mode 100644 index 1d0dd9ccf64..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sysctl.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sysctl.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.sysctl" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get the instance. - * - * @param base SYSCTL peripheral base address. - * @return Instance number. - */ -static uint32_t SYSCTL_GetInstance(SYSCTL_Type *base); - -/*! - * @brief Enable SYSCTL write protect - * - * @param base SYSCTL peripheral base address. - * @param regAddr register address - * @param value value to write. - */ -static void SYSCTL_UpdateRegister(SYSCTL_Type *base, volatile uint32_t *regAddr, uint32_t value); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief SYSCTL base address array name */ -static SYSCTL_Type *const s_sysctlBase[] = SYSCTL_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief SYSCTL clock array name */ -static const clock_ip_name_t s_sysctlClock[] = SYSCTL_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static void SYSCTL_UpdateRegister(SYSCTL_Type *base, volatile uint32_t *regAddr, uint32_t value) -{ - base->UPDATELCKOUT &= ~SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK; - *regAddr = value; - base->UPDATELCKOUT |= SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK; -} - -static uint32_t SYSCTL_GetInstance(SYSCTL_Type *base) -{ - uint8_t instance = 0; - - while ((instance < ARRAY_SIZE(s_sysctlBase)) && (s_sysctlBase[instance] != base)) - { - instance++; - } - - assert(instance < ARRAY_SIZE(s_sysctlBase)); - - return instance; -} - -/*! - * @brief SYSCTL initial - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Init(SYSCTL_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable SYSCTL clock. */ - CLOCK_EnableClock(s_sysctlClock[SYSCTL_GetInstance(base)]); -#endif -} - -/*! - * @brief SYSCTL deinit - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Deinit(SYSCTL_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable SYSCTL clock. */ - CLOCK_DisableClock(s_sysctlClock[SYSCTL_GetInstance(base)]); -#endif -} - -/*! - * @brief SYSCTL share set configure for separate signal - * - * @param base Base address of the SYSCTL peripheral - * @param flexCommIndex index of flexcomm,reference _sysctl_share_src - * @param setIndex share set for sck, reference _sysctl_share_set_index - * - */ -void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set) -{ - uint32_t tempReg = base->FCCTRLSEL[flexCommIndex]; - - tempReg &= ~((uint32_t)SYSCTL_FCCTRLSEL_SCKINSEL_MASK << (uint32_t)signal); - tempReg |= (set + 1U) << (uint32_t)signal; - - SYSCTL_UpdateRegister(base, &base->FCCTRLSEL[flexCommIndex], tempReg); -} - -/*! - * @brief SYSCTL share set configure for flexcomm - * - * @param base Base address of the SYSCTL peripheral. - * @param flexCommIndex index of flexcomm, reference _sysctl_share_src - * @param sckSet share set for sck,reference _sysctl_share_set_index - * @param wsSet share set for ws, reference _sysctl_share_set_index - * @param dataInSet share set for data in, reference _sysctl_share_set_index - * @param dataOutSet share set for data out, reference _sysctl_share_set_index - * - */ -void SYSCTL_SetFlexcommShareSet( - SYSCTL_Type *base, uint32_t flexCommIndex, uint32_t sckSet, uint32_t wsSet, uint32_t dataInSet, uint32_t dataOutSet) -{ - uint32_t tempReg = base->FCCTRLSEL[flexCommIndex]; - - tempReg &= ~(SYSCTL_FCCTRLSEL_SCKINSEL_MASK | SYSCTL_FCCTRLSEL_WSINSEL_MASK | SYSCTL_FCCTRLSEL_DATAINSEL_MASK | - SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK); - tempReg |= SYSCTL_FCCTRLSEL_SCKINSEL(sckSet + 1U) | SYSCTL_FCCTRLSEL_WSINSEL(wsSet + 1U) | - SYSCTL_FCCTRLSEL_DATAINSEL(dataInSet + 1U) | SYSCTL_FCCTRLSEL_DATAOUTSEL(dataOutSet + 1U); - - SYSCTL_UpdateRegister(base, &base->FCCTRLSEL[flexCommIndex], tempReg); -} - -/*! - * @brief SYSCTL share set source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param sckShareSrc sck source for this share set,reference _sysctl_share_src - * @param wsShareSrc ws source for this share set,reference _sysctl_share_src - * @param dataInShareSrc data in source for this share set,reference _sysctl_share_src - * @param dataOutShareSrc data out source for this share set,reference _sysctl_dataout_mask - * - */ -void SYSCTL_SetShareSetSrc(SYSCTL_Type *base, - uint32_t setIndex, - uint32_t sckShareSrc, - uint32_t wsShareSrc, - uint32_t dataInShareSrc, - uint32_t dataOutShareSrc) -{ - uint32_t tempReg = base->SHAREDCTRLSET[setIndex]; - - /* WS,SCK,DATA IN */ - tempReg &= ~(SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK | SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK | - SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK); - tempReg |= SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(sckShareSrc) | SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(wsShareSrc) | - SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(dataInShareSrc); - - /* data out */ - tempReg &= ~(SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK | SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK | - SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK | SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK | - SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK); - tempReg |= dataOutShareSrc; - - SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg); -} - -/*! - * @brief SYSCTL sck source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param sckShareSrc sck source fro this share set,reference _sysctl_share_src - * - */ -void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base, - uint32_t setIndex, - sysctl_sharedctrlset_signal_t signal, - uint32_t shareSrc) -{ - uint32_t tempReg = base->SHAREDCTRLSET[setIndex]; - - if (signal == kSYSCTL_SharedCtrlSignalDataOut) - { - tempReg |= 1UL << ((uint32_t)signal + shareSrc); - } - else - { - tempReg &= ~((uint32_t)SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK << (uint32_t)signal); - tempReg |= shareSrc << (uint32_t)signal; - } - - SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg); -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sysctl.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sysctl.h deleted file mode 100644 index 0a1be88469c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sysctl.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_SYSCTL_H_ -#define _FSL_SYSCTL_H_ - -#include "fsl_common.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup sysctl - * @{ - */ - -/*! @file */ -/*! @file fsl_sysctl.h */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Group sysctl driver version for SDK */ -#define FSL_SYSCTL_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) /*!< Version 2.0.5. */ -/*@}*/ - -/*! @brief SYSCTL share set*/ -enum _sysctl_share_set_index -{ - kSYSCTL_ShareSet0 = 0, /*!< share set 0 */ - kSYSCTL_ShareSet1 = 1, /*!< share set 1 */ -}; - -/*! @brief SYSCTL flexcomm signal */ -typedef enum _sysctl_fcctrlsel_signal -{ - kSYSCTL_FlexcommSignalSCK = SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT, /*!< SCK signal */ - kSYSCTL_FlexcommSignalWS = SYSCTL_FCCTRLSEL_WSINSEL_SHIFT, /*!< WS signal */ - kSYSCTL_FlexcommSignalDataIn = SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT, /*!< Data in signal */ - kSYSCTL_FlexcommSignalDataOut = SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT, /*!< Data out signal */ -} sysctl_fcctrlsel_signal_t; - -/*! @brief SYSCTL flexcomm index*/ -enum _sysctl_share_src -{ - kSYSCTL_Flexcomm0 = 0, /*!< share set 0 */ - kSYSCTL_Flexcomm1 = 1, /*!< share set 1 */ - kSYSCTL_Flexcomm2 = 2, /*!< share set 2 */ - kSYSCTL_Flexcomm4 = 4, /*!< share set 4 */ - kSYSCTL_Flexcomm5 = 5, /*!< share set 5 */ - kSYSCTL_Flexcomm6 = 6, /*!< share set 6 */ - kSYSCTL_Flexcomm7 = 7, /*!< share set 7 */ -}; - -/*! @brief SYSCTL shared data out mask */ -enum _sysctl_dataout_mask -{ - kSYSCTL_Flexcomm0DataOut = SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK, /*!< share set 0 */ - kSYSCTL_Flexcomm1DataOut = SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK, /*!< share set 1 */ - kSYSCTL_Flexcomm2DataOut = SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK, /*!< share set 2 */ - kSYSCTL_Flexcomm4DataOut = SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK, /*!< share set 4 */ - kSYSCTL_Flexcomm5DataOut = SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK, /*!< share set 5 */ - kSYSCTL_Flexcomm6DataOut = SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK, /*!< share set 6 */ - kSYSCTL_Flexcomm7DataOut = SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK, /*!< share set 7 */ -}; - -/*! @brief SYSCTL flexcomm signal */ -typedef enum _sysctl_sharedctrlset_signal -{ - kSYSCTL_SharedCtrlSignalSCK = SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT, /*!< SCK signal */ - kSYSCTL_SharedCtrlSignalWS = SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT, /*!< WS signal */ - kSYSCTL_SharedCtrlSignalDataIn = SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT, /*!< Data in signal */ - kSYSCTL_SharedCtrlSignalDataOut = SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT, /*!< Data out signal */ -} sysctl_sharedctrlset_signal_t; -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief SYSCTL initial - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Init(SYSCTL_Type *base); - -/*! - * @brief SYSCTL deinit - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Deinit(SYSCTL_Type *base); - -/* @} */ - -/*! - * @name SYSCTL share signal configure - * @{ - */ - -/*! - * @brief SYSCTL share set configure for flexcomm - * - * @param base Base address of the SYSCTL peripheral. - * @param flexCommIndex index of flexcomm, reference _sysctl_share_src - * @param sckSet share set for sck,reference _sysctl_share_set_index - * @param wsSet share set for ws, reference _sysctl_share_set_index - * @param dataInSet share set for data in, reference _sysctl_share_set_index - * @param dataOutSet share set for data out, reference _sysctl_dataout_mask - * - */ -void SYSCTL_SetFlexcommShareSet(SYSCTL_Type *base, - uint32_t flexCommIndex, - uint32_t sckSet, - uint32_t wsSet, - uint32_t dataInSet, - uint32_t dataOutSet); - -/*! - * @brief SYSCTL share set configure for separate signal - * - * @param base Base address of the SYSCTL peripheral - * @param flexCommIndex index of flexcomm,reference _sysctl_share_src - * @param signal FCCTRLSEL signal shift - * @param set share set for sck, reference _sysctl_share_set_index - * - */ -void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set); - -/*! - * @brief SYSCTL share set source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param sckShareSrc sck source for this share set,reference _sysctl_share_src - * @param wsShareSrc ws source for this share set,reference _sysctl_share_src - * @param dataInShareSrc data in source for this share set,reference _sysctl_share_src - * @param dataOutShareSrc data out source for this share set,reference _sysctl_dataout_mask - * - */ -void SYSCTL_SetShareSetSrc(SYSCTL_Type *base, - uint32_t setIndex, - uint32_t sckShareSrc, - uint32_t wsShareSrc, - uint32_t dataInShareSrc, - uint32_t dataOutShareSrc); - -/*! - * @brief SYSCTL sck source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param signal FCCTRLSEL signal shift - * @param shareSrc sck source fro this share set,reference _sysctl_share_src - * - */ -void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base, - uint32_t setIndex, - sysctl_sharedctrlset_signal_t signal, - uint32_t shareSrc); - -/* @} */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_SYSCTL_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart.c deleted file mode 100644 index 3286174f27b..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart.c +++ /dev/null @@ -1,1206 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_usart.h" -#include "fsl_device_registers.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart" -#endif - -/*! - * @brief Used for conversion from `flexcomm_usart_irq_handler_t` to `flexcomm_irq_handler_t` - */ -typedef union usart_to_flexcomm -{ - flexcomm_usart_irq_handler_t usart_master_handler; - flexcomm_irq_handler_t flexcomm_handler; -} usart_to_flexcomm_t; - -enum -{ - kUSART_TxIdle, /* TX idle. */ - kUSART_TxBusy, /* TX busy. */ - kUSART_RxIdle, /* RX idle. */ - kUSART_RxBusy /* RX busy. */ -}; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief IRQ name array */ -static const IRQn_Type s_usartIRQ[] = USART_IRQS; - -/*! @brief Array to map USART instance number to base address. */ -static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Get the index corresponding to the USART */ -/*! brief Returns instance number for USART peripheral base address. */ -uint32_t USART_GetInstance(USART_Type *base) -{ - uint32_t i; - - for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT; i++) - { - if ((uint32_t)base == s_usartBaseAddrs[i]) - { - break; - } - } - - assert(i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT); - return i; -} - -/*! - * brief Get the length of received data in RX ring buffer. - * - * param handle USART handle pointer. - * return Length of received data in RX ring buffer. - */ -size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) -{ - size_t size; - - /* Check arguments */ - assert(NULL != handle); - uint16_t rxRingBufferHead = handle->rxRingBufferHead; - uint16_t rxRingBufferTail = handle->rxRingBufferTail; - - if (rxRingBufferTail > rxRingBufferHead) - { - size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail; - } - else - { - size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail; - } - return size; -} - -static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle) -{ - bool full; - - /* Check arguments */ - assert(NULL != handle); - - if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) - { - full = true; - } - else - { - full = false; - } - return full; -} - -/*! - * brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific USART handle. - * - * When the RX ring buffer is used, data received are stored into the ring buffer even when the - * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * - * note When using the RX ring buffer, one byte is reserved for internal use. In other - * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. - * param ringBufferSize size of the ring buffer. - */ -void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) -{ - /* Check arguments */ - assert(NULL != base); - assert(NULL != handle); - assert(NULL != ringBuffer); - - /* Setup the ringbuffer address */ - handle->rxRingBuffer = ringBuffer; - handle->rxRingBufferSize = ringBufferSize; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; - /* ring buffer is ready we can start receiving data */ - base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -} - -/*! - * brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) -{ - /* Check arguments */ - assert(NULL != base); - assert(NULL != handle); - - if (handle->rxState == (uint8_t)kUSART_RxIdle) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK; - } - handle->rxRingBuffer = NULL; - handle->rxRingBufferSize = 0U; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; -} - -/*! - * brief Initializes a USART instance with user configuration structure and peripheral clock. - * - * This function configures the USART module with the user-defined settings. The user can configure the configuration - * structure and also get the default configuration by using the USART_GetDefaultConfig() function. - * Example below shows how to use this API to configure USART. - * code - * usart_config_t usartConfig; - * usartConfig.baudRate_Bps = 115200U; - * usartConfig.parityMode = kUSART_ParityDisabled; - * usartConfig.stopBitCount = kUSART_OneStopBit; - * USART_Init(USART1, &usartConfig, 20000000U); - * endcode - * - * param base USART peripheral base address. - * param config Pointer to user-defined configuration structure. - * param srcClock_Hz USART clock source frequency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_InvalidArgument USART base address is not valid - * retval kStatus_Success Status USART initialize succeed - */ -status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz) -{ - int result; - - /* check arguments */ - assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); - if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* initialize flexcomm to USART mode */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART); - if (kStatus_Success != result) - { - return result; - } - - if (config->enableTx) - { - /* empty and enable txFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK; - /* setup trigger level */ - base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK); - base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark); - /* enable trigger interrupt */ - base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK; - } - - /* empty and enable rxFIFO */ - if (config->enableRx) - { - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK; - /* setup trigger level */ - base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK); - base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable trigger interrupt */ - base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK; - } - /* setup configuration and enable USART */ - base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | - USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | - USART_CFG_SYNCEN((uint32_t)config->syncMode >> 1) | USART_CFG_SYNCMST((uint8_t)config->syncMode) | - USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_MODE32K(config->enableMode32k) | - USART_CFG_CTSEN(config->enableHardwareFlowControl) | USART_CFG_ENABLE_MASK; - - /* Setup baudrate */ - if (config->enableMode32k) - { - if ((9600U % config->baudRate_Bps) == 0U) - { - base->BRG = 9600U / config->baudRate_Bps; - } - else - { - return kStatus_USART_BaudrateNotSupport; - } - } - else - { - result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - } - /* Setting continuous Clock configuration. used for synchronous mode. */ - USART_EnableContinuousSCLK(base, config->enableContinuousSCLK); - - return kStatus_Success; -} - -/*! - * brief Deinitializes a USART instance. - * - * This function waits for TX complete, disables TX and RX, and disables the USART clock. - * - * param base USART peripheral base address. - */ -void USART_Deinit(USART_Type *base) -{ - /* Check arguments */ - assert(NULL != base); - while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) - { - } - /* Disable interrupts, disable dma requests, disable peripheral */ - base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK | - USART_FIFOINTENCLR_RXLVL_MASK; - base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK); - base->CFG &= ~(USART_CFG_ENABLE_MASK); -} - -/*! - * brief Gets the default configuration structure. - * - * This function initializes the USART configuration structure to a default value. The default - * values are: - * usartConfig->baudRate_Bps = 115200U; - * usartConfig->parityMode = kUSART_ParityDisabled; - * usartConfig->stopBitCount = kUSART_OneStopBit; - * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; - * usartConfig->loopback = false; - * usartConfig->enableTx = false; - * usartConfig->enableRx = false; - * - * param config Pointer to configuration structure. - */ -void USART_GetDefaultConfig(usart_config_t *config) -{ - /* Check arguments */ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* Set always all members ! */ - config->baudRate_Bps = 115200U; - config->parityMode = kUSART_ParityDisabled; - config->stopBitCount = kUSART_OneStopBit; - config->bitCountPerChar = kUSART_8BitsPerChar; - config->loopback = false; - config->enableRx = false; - config->enableTx = false; - config->enableMode32k = false; - config->txWatermark = kUSART_TxFifo0; - config->rxWatermark = kUSART_RxFifo1; - config->syncMode = kUSART_SyncModeDisabled; - config->enableContinuousSCLK = false; - config->clockPolarity = kUSART_RxSampleOnFallingEdge; - config->enableHardwareFlowControl = false; -} - -/*! - * brief Sets the USART instance baud rate. - * - * This function configures the USART module baud rate. This function is used to update - * the USART module baud rate after the USART module is initialized by the USART_Init. - * code - * USART_SetBaudRate(USART1, 115200U, 20000000U); - * endcode - * - * param base USART peripheral base address. - * param baudrate_Bps USART baudrate to be set. - * param srcClock_Hz USART clock source frequency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_Success Set baudrate succeed. - * retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) -{ - uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1; - uint32_t osrval, brgval, diff, baudrate; - - /* check arguments */ - assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))); - if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* If synchronous master mode is enabled, only configure the BRG value. */ - if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U) - { - if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U) - { - brgval = srcClock_Hz / baudrate_Bps; - base->BRG = brgval - 1U; - } - } - else - { - /* - * Smaller values of OSR can make the sampling position within a data bit less accurate and may - * potentially cause more noise errors or incorrect data. - */ - for (osrval = best_osrval; osrval >= 8U; osrval--) - { - brgval = (((srcClock_Hz * 10U) / ((osrval + 1U) * baudrate_Bps)) - 5U) / 10U; - if (brgval > 0xFFFFU) - { - continue; - } - baudrate = srcClock_Hz / ((osrval + 1U) * (brgval + 1U)); - diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); - if (diff < best_diff) - { - best_diff = diff; - best_osrval = osrval; - best_brgval = brgval; - } - } - - /* Check to see if actual baud rate is within 3% of desired baud rate - * based on the best calculated OSR and BRG value */ - baudrate = srcClock_Hz / ((best_osrval + 1U) * (best_brgval + 1U)); - diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); - if (diff > ((baudrate_Bps / 100U) * 3U)) - { - return kStatus_USART_BaudrateNotSupport; - } - - /* value over range */ - if (best_brgval > 0xFFFFU) - { - return kStatus_USART_BaudrateNotSupport; - } - - base->OSR = best_osrval; - base->BRG = best_brgval; - } - - return kStatus_Success; -} - -/*! - * brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source. - * - * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator - * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting - * SYSCON_RTCOSCCTRL_EN bit to 1. - * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that - * 9600 can evenly divide, eg: 4800, 3200. - * - * param base USART peripheral base address. - * param baudRate_Bps USART baudrate to be set.. - * param enableMode32k true is 32k mode, false is normal mode. - * param srcClock_Hz USART clock source frequency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_Success Set baudrate succeed. - * retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz) -{ - status_t result = kStatus_Success; - base->CFG &= ~(USART_CFG_ENABLE_MASK); - if (enableMode32k) - { - base->CFG |= USART_CFG_MODE32K_MASK; - if ((9600U % baudRate_Bps) == 0U) - { - base->BRG = 9600U / baudRate_Bps - 1U; - } - else - { - return kStatus_USART_BaudrateNotSupport; - } - } - else - { - base->CFG &= ~(USART_CFG_MODE32K_MASK); - result = USART_SetBaudRate(base, baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - } - base->CFG |= USART_CFG_ENABLE_MASK; - return result; -} - -/*! - * brief Enable 9-bit data mode for USART. - * - * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user. - * - * param base USART peripheral base address. - * param enable true to enable, false to disable. - */ -void USART_Enable9bitMode(USART_Type *base, bool enable) -{ - assert(base != NULL); - - uint32_t temp = 0U; - - if (enable) - { - /* Set USART 9-bit mode, disable parity. */ - temp = base->CFG & ~((uint32_t)USART_CFG_DATALEN_MASK | (uint32_t)USART_CFG_PARITYSEL_MASK); - temp |= (uint32_t)USART_CFG_DATALEN(0x2U); - base->CFG = temp; - } - else - { - /* Set USART to 8-bit mode. */ - base->CFG &= ~((uint32_t)USART_CFG_DATALEN_MASK); - base->CFG |= (uint32_t)USART_CFG_DATALEN(0x1U); - } -} - -/*! - * brief Transmit an address frame in 9-bit data mode. - * - * param base USART peripheral base address. - * param address USART slave address. - */ -void USART_SendAddress(USART_Type *base, uint8_t address) -{ - assert(base != NULL); - base->FIFOWR = ((uint32_t)address | 0x100UL); -} - -/*! - * brief Writes to the TX register using a blocking method. - * - * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO - * to have room and writes data to the TX buffer. - * - * param base USART peripheral base address. - * param data Start address of the data to write. - * param length Size of the data to write. - * retval kStatus_USART_Timeout Transmission timed out and was aborted. - * retval kStatus_InvalidArgument Invalid argument. - * retval kStatus_Success Successfully wrote all data. - */ -status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) -{ - /* Check arguments */ - assert(!((NULL == base) || (NULL == data))); -#if UART_RETRY_TIMES - uint32_t waitTimes; -#endif - if ((NULL == base) || (NULL == data)) - { - return kStatus_InvalidArgument; - } - /* Check whether txFIFO is enabled */ - if (0U == (base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK)) - { - return kStatus_InvalidArgument; - } - for (; length > 0U; length--) - { - /* Loop until txFIFO get some space for new data */ -#if UART_RETRY_TIMES - waitTimes = UART_RETRY_TIMES; - while ((0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) && (--waitTimes != 0U)) -#else - while (0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) -#endif - { - } -#if UART_RETRY_TIMES - if (0U == waitTimes) - { - return kStatus_USART_Timeout; - } -#endif - base->FIFOWR = *data; - data++; - } - /* Wait to finish transfer */ -#if UART_RETRY_TIMES - waitTimes = UART_RETRY_TIMES; - while ((0U == (base->STAT & USART_STAT_TXIDLE_MASK)) && (--waitTimes != 0U)) -#else - while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) -#endif - { - } -#if UART_RETRY_TIMES - if (0U == waitTimes) - { - return kStatus_USART_Timeout; - } -#endif - return kStatus_Success; -} - -/*! - * brief Read RX data register using a blocking method. - * - * This function polls the RX register, waits for the RX register to be full or for RX FIFO to - * have data and read data from the TX register. - * - * param base USART peripheral base address. - * param data Start address of the buffer to store the received data. - * param length Size of the buffer. - * retval kStatus_USART_FramingError Receiver overrun happened while receiving data. - * retval kStatus_USART_ParityError Noise error happened while receiving data. - * retval kStatus_USART_NoiseError Framing error happened while receiving data. - * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. - * retval kStatus_USART_Timeout Transmission timed out and was aborted. - * retval kStatus_Success Successfully received all data. - */ -status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) -{ - uint32_t statusFlag; - status_t status = kStatus_Success; -#if UART_RETRY_TIMES - uint32_t waitTimes; -#endif - - /* check arguments */ - assert(!((NULL == base) || (NULL == data))); - if ((NULL == base) || (NULL == data)) - { - return kStatus_InvalidArgument; - } - - /* Check whether rxFIFO is enabled */ - if ((base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK) == 0U) - { - return kStatus_Fail; - } - for (; length > 0U; length--) - { - /* loop until rxFIFO have some data to read */ -#if UART_RETRY_TIMES - waitTimes = UART_RETRY_TIMES; - while (((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) && (--waitTimes != 0U)) -#else - while ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) -#endif - { - } -#if UART_RETRY_TIMES - if (waitTimes == 0U) - { - status = kStatus_USART_Timeout; - break; - } -#endif - /* check rxFIFO statusFlag */ - if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) - { - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; - status = kStatus_USART_RxError; - break; - } - /* check receive statusFlag */ - statusFlag = base->STAT; - /* Clear all status flags */ - base->STAT |= statusFlag; - if ((statusFlag & USART_STAT_PARITYERRINT_MASK) != 0U) - { - status = kStatus_USART_ParityError; - } - if ((statusFlag & USART_STAT_FRAMERRINT_MASK) != 0U) - { - status = kStatus_USART_FramingError; - } - if ((statusFlag & USART_STAT_RXNOISEINT_MASK) != 0U) - { - status = kStatus_USART_NoiseError; - } - - if (kStatus_Success == status) - { - *data = (uint8_t)base->FIFORD; - data++; - } - else - { - break; - } - } - return status; -} - -/*! - * brief Initializes the USART handle. - * - * This function initializes the USART handle which can be used for other USART - * transactional APIs. Usually, for a specified USART instance, - * call this API once to get the initialized handle. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param callback The callback function. - * param userData The parameter of the callback function. - */ -status_t USART_TransferCreateHandle(USART_Type *base, - usart_handle_t *handle, - usart_transfer_callback_t callback, - void *userData) -{ - /* Check 'base' */ - assert(!((NULL == base) || (NULL == handle))); - - uint32_t instance = 0; - usart_to_flexcomm_t handler; - handler.usart_master_handler = USART_TransferHandleIRQ; - - if ((NULL == base) || (NULL == handle)) - { - return kStatus_InvalidArgument; - } - - instance = USART_GetInstance(base); - - (void)memset(handle, 0, sizeof(*handle)); - /* Set the TX/RX state. */ - handle->rxState = (uint8_t)kUSART_RxIdle; - handle->txState = (uint8_t)kUSART_TxIdle; - /* Set the callback and user data. */ - handle->callback = callback; - handle->userData = userData; - handle->rxWatermark = (uint8_t)USART_FIFOTRIG_RXLVL_GET(base); - handle->txWatermark = (uint8_t)USART_FIFOTRIG_TXLVL_GET(base); - - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - - /* Enable interrupt in NVIC. */ - (void)EnableIRQ(s_usartIRQ[instance]); - - return kStatus_Success; -} - -/*! - * brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in the IRQ handler, the USART driver calls the callback - * function and passes the ref kStatus_USART_TxIdle as status parameter. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART transfer structure. See #usart_transfer_t. - * retval kStatus_Success Successfully start the data transmission. - * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer) -{ - /* Check arguments */ - assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - /* Check xfer members */ - assert(!((0U == xfer->dataSize) || (NULL == xfer->txData))); - if ((0U == xfer->dataSize) || (NULL == xfer->txData)) - { - return kStatus_InvalidArgument; - } - - /* Return error if current TX busy. */ - if ((uint8_t)kUSART_TxBusy == handle->txState) - { - return kStatus_USART_TxBusy; - } - else - { - /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up the - * handle value. */ - uint32_t interruptMask = USART_GetEnabledInterrupts(base); - USART_DisableInterrupts(base, interruptMask); - handle->txData = xfer->txData; - handle->txDataSize = xfer->dataSize; - handle->txDataSizeAll = xfer->dataSize; - handle->txState = (uint8_t)kUSART_TxBusy; - /* Enable transmiter interrupt and the previously disabled interrupt. */ - USART_EnableInterrupts(base, interruptMask | (uint32_t)kUSART_TxLevelInterruptEnable); - } - return kStatus_Success; -} - -/*! - * brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out - * how many bytes are still not sent out. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) -{ - assert(NULL != handle); - - /* Disable interrupts */ - USART_DisableInterrupts(base, (uint32_t)kUSART_TxLevelInterruptEnable); - /* Empty txFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK; - - handle->txDataSize = 0U; - handle->txState = (uint8_t)kUSART_TxIdle; -} - -/*! - * brief Get the number of bytes that have been sent out to bus. - * - * This function gets the number of bytes that have been sent out to bus by interrupt method. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Send bytes count. - * retval kStatus_NoTransferInProgress No send in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != count); - - if ((uint8_t)kUSART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - handle->txDataSize - - ((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); - - return kStatus_Success; -} - -/*! - * brief Receives a buffer of data using an interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function, which - * returns without waiting for all data to be received. - * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and - * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in the ring buffer is not enough to read, the receive - * request is saved by the USART driver. When the new data arrives, the receive request - * is serviced first. When all data is received, the USART driver notifies the upper layer - * through a callback function and passes the status parameter ref kStatus_USART_RxIdle. - * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. - * The 5 bytes are copied to the xfer->data and this function returns with the - * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is - * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to the xfer->data. When all data is received, the upper layer is notified. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART transfer structure, see #usart_transfer_t. - * param receivedBytes Bytes received from the ring buffer directly. - * retval kStatus_Success Successfully queue the transfer into transmit queue. - * retval kStatus_USART_RxBusy Previous receive request is not finished. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveNonBlocking(USART_Type *base, - usart_handle_t *handle, - usart_transfer_t *xfer, - size_t *receivedBytes) -{ - uint32_t i; - /* How many bytes to copy from ring buffer to user memory. */ - size_t bytesToCopy = 0U; - /* How many bytes to receive. */ - size_t bytesToReceive; - /* How many bytes currently have received. */ - size_t bytesCurrentReceived; - uint32_t interruptMask = 0U; - - /* Check arguments */ - assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - /* Check xfer members */ - assert(!((0U == xfer->dataSize) || (NULL == xfer->rxData))); - if ((0U == xfer->dataSize) || (NULL == xfer->rxData)) - { - return kStatus_InvalidArgument; - } - - /* Enable address detect when address match is enabled. */ - if ((base->CFG & (uint32_t)USART_CFG_AUTOADDR_MASK) != 0U) - { - base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK; - } - - /* How to get data: - 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize - to uart handle, enable interrupt to store received data to xfer->data. When - all data received, trigger callback. - 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. - If there are enough data in ring buffer, copy them to xfer->data and return. - If there are not enough data in ring buffer, copy all of them to xfer->data, - save the xfer->data remained empty space to uart handle, receive data - to this empty space and trigger callback when finished. */ - if ((uint8_t)kUSART_RxBusy == handle->rxState) - { - return kStatus_USART_RxBusy; - } - else - { - bytesToReceive = xfer->dataSize; - bytesCurrentReceived = 0U; - /* If RX ring buffer is used. */ - if (handle->rxRingBuffer != NULL) - { - /* Disable IRQ, protect ring buffer. */ - interruptMask = USART_GetEnabledInterrupts(base); - USART_DisableInterrupts(base, interruptMask); - - /* How many bytes in RX ring buffer currently. */ - bytesToCopy = USART_TransferGetRxRingBufferLength(handle); - if (bytesToCopy != 0U) - { - bytesToCopy = MIN(bytesToReceive, bytesToCopy); - bytesToReceive -= bytesToCopy; - /* Copy data from ring buffer to user memory. */ - for (i = 0U; i < bytesToCopy; i++) - { - xfer->rxData[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; - /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ - if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - } - /* If ring buffer does not have enough data, still need to read more data. */ - if (bytesToReceive != 0U) - { - /* No data in ring buffer, save the request to UART handle. */ - handle->rxData = xfer->rxData + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = xfer->dataSize; - handle->rxState = (uint8_t)kUSART_RxBusy; - } - /* Re-enable IRQ. */ - USART_EnableInterrupts(base, interruptMask); - /* Call user callback since all data are received. */ - if (0U == bytesToReceive) - { - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); - } - } - } - /* Ring buffer not used. */ - else - { - /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up - * the handle value. */ - interruptMask = USART_GetEnabledInterrupts(base); - USART_DisableInterrupts(base, interruptMask); - handle->rxData = xfer->rxData + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = (uint8_t)kUSART_RxBusy; - - /* Enable RX interrupt. */ - base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK; - /* Re-enable IRQ. */ - USART_EnableInterrupts(base, interruptMask); - } - /* Return the how many bytes have read. */ - if (receivedBytes != NULL) - { - *receivedBytes = bytesCurrentReceived; - } - } - return kStatus_Success; -} - -/*! - * brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out - * how many bytes not received yet. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) -{ - assert(NULL != handle); - - /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ - if (NULL == handle->rxRingBuffer) - { - /* Disable interrupts */ - USART_DisableInterrupts(base, (uint32_t)kUSART_RxLevelInterruptEnable); - /* Empty rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - } - - handle->rxDataSize = 0U; - handle->rxState = (uint8_t)kUSART_RxIdle; -} - -/*! - * brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Receive bytes count. - * retval kStatus_NoTransferInProgress No receive in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != count); - - if ((uint8_t)kUSART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - handle->rxDataSize; - - return kStatus_Success; -} - -/*! - * brief USART IRQ handle function. - * - * This function handles the USART transmit and receive IRQ request. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) -{ - /* Check arguments */ - assert((NULL != base) && (NULL != handle)); - - bool receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); - bool sendEnabled = (handle->txDataSize != 0U); - uint8_t rxdata; - size_t tmpsize; - - /* If RX overrun. */ - if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) - { - /* Clear rx error state. */ - base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxError, handle->userData); - } - } - /* TX under run, happens when slave is in synchronous mode and the data is not written in tx register in time. */ - if ((base->FIFOSTAT & USART_FIFOSTAT_TXERR_MASK) != 0U) - { - /* Clear tx error state. */ - base->FIFOSTAT |= USART_FIFOSTAT_TXERR_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_TxError, handle->userData); - } - } - /* If noise error. */ - if ((base->STAT & USART_STAT_RXNOISEINT_MASK) != 0U) - { - /* Clear rx error state. */ - base->STAT |= USART_STAT_RXNOISEINT_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_NoiseError, handle->userData); - } - } - /* If framing error. */ - if ((base->STAT & USART_STAT_FRAMERRINT_MASK) != 0U) - { - /* Clear rx error state. */ - base->STAT |= USART_STAT_FRAMERRINT_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_FramingError, handle->userData); - } - } - /* If parity error. */ - if ((base->STAT & USART_STAT_PARITYERRINT_MASK) != 0U) - { - /* Clear rx error state. */ - base->STAT |= USART_STAT_PARITYERRINT_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_ParityError, handle->userData); - } - } - while ((receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) || - (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U))) - { - /* Receive data */ - if (receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) - { - /* Clear address detect when RXFIFO has data. */ - base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK; - /* Receive to app bufffer if app buffer is present */ - if (handle->rxDataSize != 0U) - { - rxdata = (uint8_t)base->FIFORD; - *handle->rxData = rxdata; - handle->rxDataSize--; - handle->rxData++; - receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); - if (0U == handle->rxDataSize) - { - if (NULL == handle->rxRingBuffer) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; - } - handle->rxState = (uint8_t)kUSART_RxIdle; - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); - } - } - } - /* Otherwise receive to ring buffer if ring buffer is present */ - else - { - if (handle->rxRingBuffer != NULL) - { - /* If RX ring buffer is full, trigger callback to notify over run. */ - if (USART_TransferIsRxRingBufferFull(handle)) - { - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData); - } - } - /* If ring buffer is still full after callback function, the oldest data is overridden. */ - if (USART_TransferIsRxRingBufferFull(handle)) - { - /* Increase handle->rxRingBufferTail to make room for new data. */ - if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - /* Read data. */ - rxdata = (uint8_t)base->FIFORD; - handle->rxRingBuffer[handle->rxRingBufferHead] = rxdata; - /* Increase handle->rxRingBufferHead. */ - if ((size_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferHead = 0U; - } - else - { - handle->rxRingBufferHead++; - } - } - } - } - /* Send data */ - if (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U)) - { - base->FIFOWR = *handle->txData; - handle->txDataSize--; - handle->txData++; - sendEnabled = handle->txDataSize != 0U; - if (!sendEnabled) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK; - - base->INTENSET = USART_INTENSET_TXIDLEEN_MASK; - } - } - } - - /* Tx idle and the interrupt is enabled. */ - if ((0U != (base->INTENSET & USART_INTENSET_TXIDLEEN_MASK)) && (0U != (base->INTSTAT & USART_INTSTAT_TXIDLE_MASK))) - { - /* Set txState to idle only when all data has been sent out to bus. */ - handle->txState = (uint8_t)kUSART_TxIdle; - /* Disable tx idle interrupt */ - base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK; - - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); - } - } - - /* ring buffer is not used */ - if (NULL == handle->rxRingBuffer) - { - tmpsize = handle->rxDataSize; - - /* restore if rx transfer ends and rxLevel is different from default value */ - if ((tmpsize == 0U) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark)) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark); - } - /* decrease level if rx transfer is bellow */ - if ((tmpsize != 0U) && (tmpsize < (USART_FIFOTRIG_RXLVL_GET(base) + 1U))) - { - base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(tmpsize - 1U)); - } - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart.h deleted file mode 100644 index ef4715c4c5c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart.h +++ /dev/null @@ -1,903 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_USART_H_ -#define _FSL_USART_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup usart_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief USART driver version. */ -#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 7, 0)) -/*@}*/ - -#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT) -#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT) - -/*! @brief Retry times for waiting flag. */ -#ifndef UART_RETRY_TIMES -#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */ -#endif - -/*! @brief Error codes for the USART driver. */ -enum -{ - kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */ - kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */ - kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */ - kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */ - kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */ - kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */ - kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */ - kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */ - kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */ - kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */ - kStatus_USART_BaudrateNotSupport = - MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */ -#if UART_RETRY_TIMES - kStatus_USART_Timeout = MAKE_STATUS(kStatusGroup_LPC_USART, 14), /*!< USART time out. */ -#endif -}; - -/*! @brief USART synchronous mode. */ -typedef enum _usart_sync_mode -{ - kUSART_SyncModeDisabled = 0x0U, /*!< Asynchronous mode. */ - kUSART_SyncModeSlave = 0x2U, /*!< Synchronous slave mode. */ - kUSART_SyncModeMaster = 0x3U, /*!< Synchronous master mode. */ -} usart_sync_mode_t; - -/*! @brief USART parity mode. */ -typedef enum _usart_parity_mode -{ - kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */ - kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ - kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ -} usart_parity_mode_t; - -/*! @brief USART stop bit count. */ -typedef enum _usart_stop_bit_count -{ - kUSART_OneStopBit = 0U, /*!< One stop bit */ - kUSART_TwoStopBit = 1U, /*!< Two stop bits */ -} usart_stop_bit_count_t; - -/*! @brief USART data size. */ -typedef enum _usart_data_len -{ - kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */ - kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */ -} usart_data_len_t; - -/*! @brief USART clock polarity configuration, used in sync mode.*/ -typedef enum _usart_clock_polarity -{ - kUSART_RxSampleOnFallingEdge = 0x0U, /*!< Un_RXD is sampled on the falling edge of SCLK. */ - kUSART_RxSampleOnRisingEdge = 0x1U, /*!< Un_RXD is sampled on the rising edge of SCLK. */ -} usart_clock_polarity_t; - -/*! @brief txFIFO watermark values */ -typedef enum _usart_txfifo_watermark -{ - kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */ - kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */ - kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */ - kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */ - kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */ - kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */ - kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */ - kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */ -} usart_txfifo_watermark_t; - -/*! @brief rxFIFO watermark values */ -typedef enum _usart_rxfifo_watermark -{ - kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */ - kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */ - kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */ - kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */ - kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */ - kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */ - kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */ - kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */ -} usart_rxfifo_watermark_t; - -/*! - * @brief USART interrupt configuration structure, default settings all disabled. - */ -enum _usart_interrupt_enable -{ - kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK), - kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK), - kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK), - kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK), - kUSART_TxIdleInterruptEnable = (USART_INTENSET_TXIDLEEN_MASK << 16U), /*!< Transmitter idle. */ - kUSART_CtsChangeInterruptEnable = - (USART_INTENSET_DELTACTSEN_MASK << 16U), /*!< Change in the state of the CTS input. */ - kUSART_RxBreakChangeInterruptEnable = - (USART_INTENSET_DELTARXBRKEN_MASK), /*!< Break condition asserted or deasserted. */ - kUSART_RxStartInterruptEnable = (USART_INTENSET_STARTEN_MASK), /*!< Rx start bit detected. */ - kUSART_FramingErrorInterruptEnable = (USART_INTENSET_FRAMERREN_MASK), /*!< Framing error detected. */ - kUSART_ParityErrorInterruptEnable = (USART_INTENSET_PARITYERREN_MASK), /*!< Parity error detected. */ - kUSART_NoiseErrorInterruptEnable = (USART_INTENSET_RXNOISEEN_MASK), /*!< Noise error detected. */ - kUSART_AutoBaudErrorInterruptEnable = (USART_INTENSET_ABERREN_MASK), /*!< Auto baudrate error detected. */ - - kUSART_AllInterruptEnables = - kUSART_TxErrorInterruptEnable | kUSART_RxErrorInterruptEnable | kUSART_TxLevelInterruptEnable | - kUSART_RxLevelInterruptEnable | kUSART_TxIdleInterruptEnable | kUSART_CtsChangeInterruptEnable | - kUSART_RxBreakChangeInterruptEnable | kUSART_RxStartInterruptEnable | kUSART_FramingErrorInterruptEnable | - kUSART_ParityErrorInterruptEnable | kUSART_NoiseErrorInterruptEnable | kUSART_AutoBaudErrorInterruptEnable, -}; - -/*! - * @brief USART status flags. - * - * This provides constants for the USART status flags for use in the USART functions. - */ -enum _usart_flags -{ - kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */ - kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */ - kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */ - kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */ - kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */ - kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */ - kUSART_RxIdleFlag = (USART_STAT_RXIDLE_MASK << 16U), /*!< Receiver idle. */ - kUSART_TxIdleFlag = (USART_STAT_TXIDLE_MASK << 16U), /*!< Transmitter idle. */ - kUSART_CtsAssertFlag = (USART_STAT_CTS_MASK << 16U), /*!< CTS signal high. */ - kUSART_CtsChangeFlag = (USART_STAT_DELTACTS_MASK << 16U), /*!< CTS signal changed interrupt status. */ - kUSART_BreakDetectFlag = (USART_STAT_RXBRK_MASK), /*!< Break detected. Self cleared when rx pin goes high again. */ - kUSART_BreakDetectChangeFlag = (USART_STAT_DELTARXBRK_MASK), /*!< Break detect change interrupt flag. A change in - the state of receiver break detection. */ - kUSART_RxStartFlag = (USART_STAT_START_MASK), /*!< Rx start bit detected interrupt flag. */ - kUSART_FramingErrorFlag = (USART_STAT_FRAMERRINT_MASK), /*!< Framing error interrupt flag. */ - kUSART_ParityErrorFlag = (USART_STAT_PARITYERRINT_MASK), /*!< parity error interrupt flag. */ - kUSART_NoiseErrorFlag = (USART_STAT_RXNOISEINT_MASK), /*!< Noise error interrupt flag. */ - kUSART_AutobaudErrorFlag = (USART_STAT_ABERR_MASK), /*!< Auto baudrate error interrupt flag, caused by the baudrate - counter timeout before the end of start bit. */ - - kUSART_AllClearFlags = kUSART_TxError | kUSART_RxError | kUSART_CtsChangeFlag | kUSART_BreakDetectChangeFlag | - kUSART_RxStartFlag | kUSART_FramingErrorFlag | kUSART_ParityErrorFlag | - kUSART_NoiseErrorFlag | kUSART_AutobaudErrorFlag, -}; - -/*! @brief USART configuration structure. */ -typedef struct _usart_config -{ - uint32_t baudRate_Bps; /*!< USART baud rate */ - usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ - usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ - usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */ - bool loopback; /*!< Enable peripheral loopback */ - bool enableRx; /*!< Enable RX */ - bool enableTx; /*!< Enable TX */ - bool enableContinuousSCLK; /*!< USART continuous Clock generation enable in synchronous master mode. */ - bool enableMode32k; /*!< USART uses 32 kHz clock from the RTC oscillator as the clock source. */ - bool enableHardwareFlowControl; /*!< Enable hardware control RTS/CTS */ - usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ - usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */ - usart_clock_polarity_t clockPolarity; /*!< Selects the clock polarity and sampling edge in synchronous mode. */ -} usart_config_t; - -/*! @brief USART transfer structure. */ -typedef struct _usart_transfer -{ - /* - * Use separate TX and RX data pointer, because TX data is const data. - * The member data is kept for backward compatibility. - */ - union - { - uint8_t *data; /*!< The buffer of data to be transfer.*/ - uint8_t *rxData; /*!< The buffer to receive data. */ - const uint8_t *txData; /*!< The buffer of data to be sent. */ - }; - size_t dataSize; /*!< The byte count to be transfer. */ -} usart_transfer_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _usart_handle usart_handle_t; - -/*! @brief USART transfer callback function. */ -typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData); - -/*! @brief USART handle structure. */ -struct _usart_handle -{ - const uint8_t *volatile txData; /*!< Address of remaining data to send. */ - volatile size_t txDataSize; /*!< Size of the remaining data to send. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ - volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - - uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ - size_t rxRingBufferSize; /*!< Size of the ring buffer. */ - volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ - volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ - - usart_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< USART callback function parameter.*/ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ - - uint8_t txWatermark; /*!< txFIFO watermark */ - uint8_t rxWatermark; /*!< rxFIFO watermark */ -}; - -/*! @brief Typedef for usart interrupt handler. */ -typedef void (*flexcomm_usart_irq_handler_t)(USART_Type *base, usart_handle_t *handle); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! @brief Returns instance number for USART peripheral base address. */ -uint32_t USART_GetInstance(USART_Type *base); - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes a USART instance with user configuration structure and peripheral clock. - * - * This function configures the USART module with the user-defined settings. The user can configure the configuration - * structure and also get the default configuration by using the USART_GetDefaultConfig() function. - * Example below shows how to use this API to configure USART. - * @code - * usart_config_t usartConfig; - * usartConfig.baudRate_Bps = 115200U; - * usartConfig.parityMode = kUSART_ParityDisabled; - * usartConfig.stopBitCount = kUSART_OneStopBit; - * USART_Init(USART1, &usartConfig, 20000000U); - * @endcode - * - * @param base USART peripheral base address. - * @param config Pointer to user-defined configuration structure. - * @param srcClock_Hz USART clock source frequency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_InvalidArgument USART base address is not valid - * @retval kStatus_Success Status USART initialize succeed - */ -status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes a USART instance. - * - * This function waits for TX complete, disables TX and RX, and disables the USART clock. - * - * @param base USART peripheral base address. - */ -void USART_Deinit(USART_Type *base); - -/*! - * @brief Gets the default configuration structure. - * - * This function initializes the USART configuration structure to a default value. The default - * values are: - * usartConfig->baudRate_Bps = 115200U; - * usartConfig->parityMode = kUSART_ParityDisabled; - * usartConfig->stopBitCount = kUSART_OneStopBit; - * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; - * usartConfig->loopback = false; - * usartConfig->enableTx = false; - * usartConfig->enableRx = false; - * - * @param config Pointer to configuration structure. - */ -void USART_GetDefaultConfig(usart_config_t *config); - -/*! - * @brief Sets the USART instance baud rate. - * - * This function configures the USART module baud rate. This function is used to update - * the USART module baud rate after the USART module is initialized by the USART_Init. - * @code - * USART_SetBaudRate(USART1, 115200U, 20000000U); - * @endcode - * - * @param base USART peripheral base address. - * @param baudrate_Bps USART baudrate to be set. - * @param srcClock_Hz USART clock source frequency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_Success Set baudrate succeed. - * @retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source - * - * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator - * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting - * SYSCON_RTCOSCCTRL_EN bit to 1. - * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that - * 9600 can evenly divide, eg: 4800, 3200. - * - * @param base USART peripheral base address. - * @param baudRate_Bps USART baudrate to be set.. - * @param enableMode32k true is 32k mode, false is normal mode. - * @param srcClock_Hz USART clock source frequency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_Success Set baudrate succeed. - * @retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz); - -/*! - * @brief Enable 9-bit data mode for USART. - * - * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user. - * - * @param base USART peripheral base address. - * @param enable true to enable, false to disable. - */ -void USART_Enable9bitMode(USART_Type *base, bool enable); - -/*! - * @brief Set the USART slave address. - * - * This function configures the address for USART module that works as slave in 9-bit data mode. When the address - * detection is enabled, the frame it receices with MSB being 1 is considered as an address frame, otherwise it is - * considered as data frame. Once the address frame matches slave's own addresses, this slave is addressed. This - * address frame and its following data frames are stored in the receive buffer, otherwise the frames will be discarded. - * To un-address a slave, just send an address frame with unmatched address. - * - * @note Any USART instance joined in the multi-slave system can work as slave. The position of the address mark is the - * same as the parity bit when parity is enabled for 8 bit and 9 bit data formats. - * - * @param base USART peripheral base address. - * @param address USART slave address. - */ -static inline void USART_SetMatchAddress(USART_Type *base, uint8_t address) -{ - /* Configure match address. */ - base->ADDR = (uint32_t)address; -} - -/*! - * @brief Enable the USART match address feature. - * - * @param base USART peripheral base address. - * @param match true to enable match address, false to disable. - */ -static inline void USART_EnableMatchAddress(USART_Type *base, bool match) -{ - /* Configure match address enable bit. */ - if (match) - { - base->CFG |= (uint32_t)USART_CFG_AUTOADDR_MASK; - base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK; - } - else - { - base->CFG &= ~(uint32_t)USART_CFG_AUTOADDR_MASK; - base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK; - } -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Get USART status flags. - * - * This function get all USART status flags, the flags are returned as the logical - * OR value of the enumerators @ref _usart_flags. To check a specific status, - * compare the return value with enumerators in @ref _usart_flags. - * For example, to check whether the TX is empty: - * @code - * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1)) - * { - * ... - * } - * @endcode - * - * @param base USART peripheral base address. - * @return USART status flags which are ORed by the enumerators in the _usart_flags. - */ -static inline uint32_t USART_GetStatusFlags(USART_Type *base) -{ - return (base->FIFOSTAT & 0xFFUL) | (base->STAT & 0xFFUL) << 16U | (base->STAT & 0xFFFF00UL); -} - -/*! - * @brief Clear USART status flags. - * - * This function clear supported USART status flags - * Flags that can be cleared or set are: - * kUSART_TxError - * kUSART_RxError - * For example: - * @code - * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError) - * @endcode - * - * @param base USART peripheral base address. - * @param mask status flags to be cleared. - */ -static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask) -{ - mask &= (uint32_t)kUSART_AllClearFlags; - /* Clear the clearable status in STAT register. */ - base->STAT = (mask & 0xFFFF00UL) | ((mask & 0xFF0000UL) >> 16U); - /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */ - base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK); -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ -/*! - * @brief Enables USART interrupts according to the provided mask. - * - * This function enables the USART interrupts according to the provided mask. The mask - * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. - * For example, to enable TX empty interrupt and RX full interrupt: - * @code - * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); - * @endcode - * - * @param base USART peripheral base address. - * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable. - */ -static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) -{ - mask &= (uint32_t)kUSART_AllInterruptEnables; - base->INTENSET = (mask & 0x1FF00UL) | ((mask & 0xFF0000UL) >> 16U); - base->FIFOINTENSET = mask & 0xFUL; -} - -/*! - * @brief Disables USART interrupts according to a provided mask. - * - * This function disables the USART interrupts according to a provided mask. The mask - * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. - * This example shows how to disable the TX empty interrupt and RX full interrupt: - * @code - * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); - * @endcode - * - * @param base USART peripheral base address. - * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable. - */ -static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) -{ - mask &= (uint32_t)kUSART_AllInterruptEnables; - base->INTENCLR = (mask & 0x1FF00UL) | ((mask & 0xFF0000UL) >> 16U); - base->FIFOINTENCLR = mask & 0xFUL; -} - -/*! - * @brief Returns enabled USART interrupts. - * - * This function returns the enabled USART interrupts. - * - * @param base USART peripheral base address. - */ -static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base) -{ - return (base->INTENSET & 0x1FF00UL) | ((base->INTENSET & 0xFFUL) << 16UL) | (base->FIFOINTENSET & 0xFUL); -} - -/*! - * @brief Enable DMA for Tx - */ -static inline void USART_EnableTxDMA(USART_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK); - } -} - -/*! - * @brief Enable DMA for Rx - */ -static inline void USART_EnableRxDMA(USART_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK); - } -} - -/*! - * @brief Enable CTS. - * This function will determine whether CTS is used for flow control. - * - * @param base USART peripheral base address. - * @param enable Enable CTS or not, true for enable and false for disable. - */ -static inline void USART_EnableCTS(USART_Type *base, bool enable) -{ - if (enable) - { - base->CFG |= USART_CFG_CTSEN_MASK; - } - else - { - base->CFG &= ~USART_CFG_CTSEN_MASK; - } -} - -/*! - * @brief Continuous Clock generation. - * By default, SCLK is only output while data is being transmitted in synchronous mode. - * Enable this funciton, SCLK will run continuously in synchronous mode, allowing - * characters to be received on Un_RxD independently from transmission on Un_TXD). - * - * @param base USART peripheral base address. - * @param enable Enable Continuous Clock generation mode or not, true for enable and false for disable. - */ -static inline void USART_EnableContinuousSCLK(USART_Type *base, bool enable) -{ - if (enable) - { - base->CTL |= USART_CTL_CC_MASK; - } - else - { - base->CTL &= ~USART_CTL_CC_MASK; - } -} - -/*! - * @brief Enable Continuous Clock generation bit auto clear. - * While enable this cuntion, the Continuous Clock bit is automatically cleared when a complete - * character has been received. This bit is cleared at the same time. - * - * @param base USART peripheral base address. - * @param enable Enable auto clear or not, true for enable and false for disable. - */ -static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable) -{ - if (enable) - { - base->CTL |= USART_CTL_CLRCCONRX_MASK; - } - else - { - base->CTL &= ~USART_CTL_CLRCCONRX_MASK; - } -} - -/*! - * @brief Sets the rx FIFO watermark. - * - * @param base USART peripheral base address. - * @param water Rx FIFO watermark. - */ -static inline void USART_SetRxFifoWatermark(USART_Type *base, uint8_t water) -{ - assert(water <= (USART_FIFOTRIG_RXLVL_MASK >> USART_FIFOTRIG_RXLVL_SHIFT)); - base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_RXLVL_MASK) | USART_FIFOTRIG_RXLVL(water); -} - -/*! - * @brief Sets the tx FIFO watermark. - * - * @param base USART peripheral base address. - * @param water Tx FIFO watermark. - */ -static inline void USART_SetTxFifoWatermark(USART_Type *base, uint8_t water) -{ - assert(water <= (USART_FIFOTRIG_TXLVL_MASK >> USART_FIFOTRIG_TXLVL_SHIFT)); - base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_TXLVL_MASK) | USART_FIFOTRIG_TXLVL(water); -} -/* @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Writes to the FIFOWR register. - * - * This function writes data to the txFIFO directly. The upper layer must ensure - * that txFIFO has space for data to write before calling this function. - * - * @param base USART peripheral base address. - * @param data The byte to write. - */ -static inline void USART_WriteByte(USART_Type *base, uint8_t data) -{ - base->FIFOWR = data; -} - -/*! - * @brief Reads the FIFORD register directly. - * - * This function reads data from the rxFIFO directly. The upper layer must - * ensure that the rxFIFO is not empty before calling this function. - * - * @param base USART peripheral base address. - * @return The byte read from USART data register. - */ -static inline uint8_t USART_ReadByte(USART_Type *base) -{ - return (uint8_t)base->FIFORD; -} - -/*! - * @brief Gets the rx FIFO data count. - * - * @param base USART peripheral base address. - * @return rx FIFO data count. - */ -static inline uint8_t USART_GetRxFifoCount(USART_Type *base) -{ - return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_RXLVL_MASK) >> USART_FIFOSTAT_RXLVL_SHIFT); -} - -/*! - * @brief Gets the tx FIFO data count. - * - * @param base USART peripheral base address. - * @return tx FIFO data count. - */ -static inline uint8_t USART_GetTxFifoCount(USART_Type *base) -{ - return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); -} - -/*! - * @brief Transmit an address frame in 9-bit data mode. - * - * @param base USART peripheral base address. - * @param address USART slave address. - */ -void USART_SendAddress(USART_Type *base, uint8_t address); - -/*! - * @brief Writes to the TX register using a blocking method. - * - * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO - * to have room and writes data to the TX buffer. - * - * @param base USART peripheral base address. - * @param data Start address of the data to write. - * @param length Size of the data to write. - * @retval kStatus_USART_Timeout Transmission timed out and was aborted. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_Success Successfully wrote all data. - */ -status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length); - -/*! - * @brief Read RX data register using a blocking method. - * - * This function polls the RX register, waits for the RX register to be full or for RX FIFO to - * have data and read data from the TX register. - * - * @param base USART peripheral base address. - * @param data Start address of the buffer to store the received data. - * @param length Size of the buffer. - * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data. - * @retval kStatus_USART_ParityError Noise error happened while receiving data. - * @retval kStatus_USART_NoiseError Framing error happened while receiving data. - * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. - * @retval kStatus_USART_Timeout Transmission timed out and was aborted. - * @retval kStatus_Success Successfully received all data. - */ -status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the USART handle. - * - * This function initializes the USART handle which can be used for other USART - * transactional APIs. Usually, for a specified USART instance, - * call this API once to get the initialized handle. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param callback The callback function. - * @param userData The parameter of the callback function. - */ -status_t USART_TransferCreateHandle(USART_Type *base, - usart_handle_t *handle, - usart_transfer_callback_t callback, - void *userData); - -/*! - * @brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in the IRQ handler, the USART driver calls the callback - * function and passes the @ref kStatus_USART_TxIdle as status parameter. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART transfer structure. See #usart_transfer_t. - * @retval kStatus_Success Successfully start the data transmission. - * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific USART handle. - * - * When the RX ring buffer is used, data received are stored into the ring buffer even when the - * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * - * @note When using the RX ring buffer, one byte is reserved for internal use. In other - * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. - * @param ringBufferSize size of the ring buffer. - */ -void USART_TransferStartRingBuffer(USART_Type *base, - usart_handle_t *handle, - uint8_t *ringBuffer, - size_t ringBufferSize); - -/*! - * @brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the length of received data in RX ring buffer. - * - * @param handle USART handle pointer. - * @return Length of received data in RX ring buffer. - */ -size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle); - -/*! - * @brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out - * how many bytes are still not sent out. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been sent out to bus. - * - * This function gets the number of bytes that have been sent out to bus by interrupt method. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Send bytes count. - * @retval kStatus_NoTransferInProgress No send in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); - -/*! - * @brief Receives a buffer of data using an interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function, which - * returns without waiting for all data to be received. - * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and - * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in the ring buffer is not enough to read, the receive - * request is saved by the USART driver. When the new data arrives, the receive request - * is serviced first. When all data is received, the USART driver notifies the upper layer - * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle. - * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. - * The 5 bytes are copied to the xfer->data and this function returns with the - * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is - * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to the xfer->data. When all data is received, the upper layer is notified. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART transfer structure, see #usart_transfer_t. - * @param receivedBytes Bytes received from the ring buffer directly. - * @retval kStatus_Success Successfully queue the transfer into transmit queue. - * @retval kStatus_USART_RxBusy Previous receive request is not finished. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveNonBlocking(USART_Type *base, - usart_handle_t *handle, - usart_transfer_t *xfer, - size_t *receivedBytes); - -/*! - * @brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out - * how many bytes not received yet. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); - -/*! - * @brief USART IRQ handle function. - * - * This function handles the USART transmit and receive IRQ request. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_USART_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart_dma.c deleted file mode 100644 index 60c2d5284c5..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart_dma.c +++ /dev/null @@ -1,392 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_usart.h" -#include "fsl_device_registers.h" -#include "fsl_dma.h" -#include "fsl_flexcomm.h" -#include "fsl_usart_dma.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_dma" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ -enum -{ - kUSART_TxIdle, /* TX idle. */ - kUSART_TxBusy, /* TX busy. */ - kUSART_RxIdle, /* RX idle. */ - kUSART_RxBusy /* RX busy. */ -}; - -/*! @brief Typedef for usart DMA interrupt handler. */ -typedef void (*flexcomm_usart_dma_irq_handler_t)(USART_Type *base, usart_dma_handle_t *handle); - -/*base, false); - - /* Enable tx idle interrupt */ - usartPrivateHandle->base->INTENSET = USART_INTENSET_TXIDLEEN_MASK; -} - -static void USART_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode) -{ - assert(handle != NULL); - assert(param != NULL); - - usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param; - - /* Disable UART RX DMA. */ - USART_EnableRxDMA(usartPrivateHandle->base, false); - - usartPrivateHandle->handle->rxState = (uint8_t)kUSART_RxIdle; - - if (usartPrivateHandle->handle->callback != NULL) - { - usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_RxIdle, - usartPrivateHandle->handle->userData); - } -} - -/*! - * brief Initializes the USART handle which is used in transactional functions. - * param base USART peripheral base address. - * param handle Pointer to usart_dma_handle_t structure. - * param callback Callback function. - * param userData User data. - * param txDmaHandle User-requested DMA handle for TX DMA transfer. - * param rxDmaHandle User-requested DMA handle for RX DMA transfer. - */ -status_t USART_TransferCreateHandleDMA(USART_Type *base, - usart_dma_handle_t *handle, - usart_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *txDmaHandle, - dma_handle_t *rxDmaHandle) -{ - uint32_t instance = 0; - - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } - /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - instance = USART_GetInstance(base); - - (void)memset(handle, 0, sizeof(*handle)); - /* assign 'base' and 'handle' */ - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - /* set tx/rx 'idle' state */ - handle->rxState = (uint8_t)kUSART_RxIdle; - handle->txState = (uint8_t)kUSART_TxIdle; - - handle->callback = callback; - handle->userData = userData; - - handle->rxDmaHandle = rxDmaHandle; - handle->txDmaHandle = txDmaHandle; - - /* Set USART_TransferDMAHandleIRQ as DMA IRQ handler */ - usart_dma_to_flexcomm_t handler; - handler.usart_dma_handler = USART_TransferDMAHandleIRQ; - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - /* Enable NVIC IRQ. */ - (void)EnableIRQ(s_usartIRQ[instance]); - - /* Configure TX. */ - if (txDmaHandle != NULL) - { - DMA_SetCallback(txDmaHandle, USART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]); - } - - /* Configure RX. */ - if (rxDmaHandle != NULL) - { - DMA_SetCallback(rxDmaHandle, USART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]); - } - - return kStatus_Success; -} - -/*! - * brief Sends data using DMA. - * - * This function sends data using DMA. This is a non-blocking function, which returns - * right away. When all data is sent, the send callback function is called. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART DMA transfer structure. See #usart_transfer_t. - * retval kStatus_Success if succeed, others failed. - * retval kStatus_USART_TxBusy Previous transfer on going. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) -{ - assert(handle != NULL); - assert(handle->txDmaHandle != NULL); - assert(xfer != NULL); - assert(xfer->data != NULL); - assert(xfer->dataSize != 0U); - - dma_transfer_config_t xferConfig; - status_t status; - uint32_t address = (uint32_t)&base->FIFOWR; - - /* If previous TX not finished. */ - if ((uint8_t)kUSART_TxBusy == handle->txState) - { - status = kStatus_USART_TxBusy; - } - else - { - handle->txState = (uint8_t)kUSART_TxBusy; - handle->txDataSizeAll = xfer->dataSize; - - /* Enable DMA request from txFIFO */ - USART_EnableTxDMA(base, true); - - /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, xfer->data, (uint32_t *)address, sizeof(uint8_t), xfer->dataSize, - kDMA_MemoryToPeripheral, NULL); - - /* Submit transfer. */ - (void)DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); - DMA_StartTransfer(handle->txDmaHandle); - - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Receives data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * param base USART peripheral base address. - * param handle Pointer to usart_dma_handle_t structure. - * param xfer USART DMA transfer structure. See #usart_transfer_t. - * retval kStatus_Success if succeed, others failed. - * retval kStatus_USART_RxBusy Previous transfer on going. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) -{ - assert(handle != NULL); - assert(handle->rxDmaHandle != NULL); - assert(xfer != NULL); - assert(xfer->data != NULL); - assert(xfer->dataSize != 0U); - - dma_transfer_config_t xferConfig; - status_t status; - uint32_t address = (uint32_t)&base->FIFORD; - - /* If previous RX not finished. */ - if ((uint8_t)kUSART_RxBusy == handle->rxState) - { - status = kStatus_USART_RxBusy; - } - else - { - handle->rxState = (uint8_t)kUSART_RxBusy; - handle->rxDataSizeAll = xfer->dataSize; - - /* Enable DMA request from rxFIFO */ - USART_EnableRxDMA(base, true); - - /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, xfer->data, sizeof(uint8_t), xfer->dataSize, - kDMA_PeripheralToMemory, NULL); - - /* Submit transfer. */ - (void)DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); - DMA_StartTransfer(handle->rxDmaHandle); - - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Aborts the sent data using DMA. - * - * This function aborts send data using DMA. - * - * param base USART peripheral base address - * param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle) -{ - assert(NULL != handle); - assert(NULL != handle->txDmaHandle); - - /* Stop transfer. */ - DMA_AbortTransfer(handle->txDmaHandle); - handle->txState = (uint8_t)kUSART_TxIdle; -} - -/*! - * brief Aborts the received data using DMA. - * - * This function aborts the received data using DMA. - * - * param base USART peripheral base address - * param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle) -{ - assert(NULL != handle); - assert(NULL != handle->rxDmaHandle); - - /* Stop transfer. */ - DMA_AbortTransfer(handle->rxDmaHandle); - handle->rxState = (uint8_t)kUSART_RxIdle; -} - -/*! - * brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Receive bytes count. - * retval kStatus_NoTransferInProgress No receive in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != handle->rxDmaHandle); - assert(NULL != count); - - if ((uint8_t)kUSART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); - - return kStatus_Success; -} - -/*! - * brief Get the number of bytes that have been sent. - * - * This function gets the number of bytes that have been sent. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Sent bytes count. - * retval kStatus_NoTransferInProgress No receive in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != handle->txDmaHandle); - assert(NULL != count); - - if ((uint8_t)kUSART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel); - - return kStatus_Success; -} - -void USART_TransferDMAHandleIRQ(USART_Type *base, usart_dma_handle_t *handle) -{ - /* Check arguments */ - assert((NULL != base) && (NULL != handle)); - - /* Tx idle interrupt happens means that all the tx data have been sent out to bus, set the tx state to idle */ - handle->txState = (uint8_t)kUSART_TxIdle; - - /* Disable tx idle interrupt */ - base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK; - - /* Invoke callback */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart_dma.h deleted file mode 100644 index 2166803b5f2..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart_dma.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_USART_DMA_H_ -#define _FSL_USART_DMA_H_ - -#include "fsl_common.h" -#include "fsl_dma.h" -#include "fsl_usart.h" - -/*! - * @addtogroup usart_dma_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief USART dma driver version. */ -#define FSL_USART_DMA_DRIVER_VERSION (MAKE_VERSION(2, 6, 0)) -/*@}*/ - -/* Forward declaration of the handle typedef. */ -typedef struct _usart_dma_handle usart_dma_handle_t; - -/*! @brief UART transfer callback function. */ -typedef void (*usart_dma_transfer_callback_t)(USART_Type *base, - usart_dma_handle_t *handle, - status_t status, - void *userData); - -/*! - * @brief UART DMA handle - */ -struct _usart_dma_handle -{ - USART_Type *base; /*!< UART peripheral base address. */ - - usart_dma_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< UART callback function parameter.*/ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - - dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */ - dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name DMA transactional - * @{ - */ - -/*! - * @brief Initializes the USART handle which is used in transactional functions. - * @param base USART peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param callback Callback function. - * @param userData User data. - * @param txDmaHandle User-requested DMA handle for TX DMA transfer. - * @param rxDmaHandle User-requested DMA handle for RX DMA transfer. - */ -status_t USART_TransferCreateHandleDMA(USART_Type *base, - usart_dma_handle_t *handle, - usart_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *txDmaHandle, - dma_handle_t *rxDmaHandle); - -/*! - * @brief Sends data using DMA. - * - * This function sends data using DMA. This is a non-blocking function, which returns - * right away. When all data is sent, the send callback function is called. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART DMA transfer structure. See #usart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_USART_TxBusy Previous transfer on going. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Receives data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * @param base USART peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param xfer USART DMA transfer structure. See #usart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_USART_RxBusy Previous transfer on going. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Aborts the sent data using DMA. - * - * This function aborts send data using DMA. - * - * @param base USART peripheral base address - * @param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle); - -/*! - * @brief Aborts the received data using DMA. - * - * This function aborts the received data using DMA. - * - * @param base USART peripheral base address - * @param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); - -/*! - * @brief Get the number of bytes that have been sent. - * - * This function gets the number of bytes that have been sent. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Sent bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_USART_DMA_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_utick.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_utick.c deleted file mode 100644 index 0eea419cd34..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_utick.c +++ /dev/null @@ -1,230 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019, 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_utick.h" -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG) -#include "fsl_power.h" -#endif -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.utick" -#endif - -/* Typedef for interrupt handler. */ -typedef void (*utick_isr_t)(UTICK_Type *base, utick_callback_t cb); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base UTICK peripheral base address - * - * @return The UTICK instance - */ -static uint32_t UTICK_GetInstance(UTICK_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of UTICK handle. */ -static utick_callback_t s_utickHandle[FSL_FEATURE_SOC_UTICK_COUNT]; -/* Array of UTICK peripheral base address. */ -static UTICK_Type *const s_utickBases[] = UTICK_BASE_PTRS; -/* Array of UTICK IRQ number. */ -static const IRQn_Type s_utickIRQ[] = UTICK_IRQS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of UTICK clock name. */ -static const clock_ip_name_t s_utickClock[] = UTICK_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) -/*! @brief Pointers to UTICK resets for each instance. */ -static const reset_ip_name_t s_utickResets[] = UTICK_RSTS; -#endif - -/* UTICK ISR for transactional APIs. */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -static utick_isr_t s_utickIsr = (utick_isr_t)DefaultISR; -#else -static utick_isr_t s_utickIsr; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t UTICK_GetInstance(UTICK_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_utickBases); instance++) - { - if (s_utickBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_utickBases)); - - return instance; -} - -/*! - * brief Starts UTICK. - * - * This function starts a repeat/onetime countdown with an optional callback - * - * param base UTICK peripheral base address. - * param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) - * return none - */ -void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb) -{ - uint32_t instance; - - /* Get instance from peripheral base address. */ - instance = UTICK_GetInstance(base); - - /* Save the handle in global variables to support the double weak mechanism. */ - s_utickHandle[instance] = cb; -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) && \ - !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)) - EnableDeepSleepIRQ(s_utickIRQ[instance]); -#else - (void)EnableIRQ(s_utickIRQ[instance]); -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT && !FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ - base->CTRL = count | UTICK_CTRL_REPEAT(mode); -} - -/*! - * brief Initializes an UTICK by turning its bus clock on - * - */ -void UTICK_Init(UTICK_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable utick clock */ - CLOCK_EnableClock(s_utickClock[UTICK_GetInstance(base)]); -#endif - -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) - RESET_PeripheralReset(s_utickResets[UTICK_GetInstance(base)]); -#endif - -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG) - /* Power up Watchdog oscillator*/ - POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC); -#endif - - s_utickIsr = UTICK_HandleIRQ; -} - -/*! - * brief Deinitializes a UTICK instance. - * - * This function shuts down Utick bus clock - * - * param base UTICK peripheral base address. - */ -void UTICK_Deinit(UTICK_Type *base) -{ - /* Turn off utick */ - base->CTRL = 0; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable utick clock */ - CLOCK_DisableClock(s_utickClock[UTICK_GetInstance(base)]); -#endif -} - -/*! - * brief Get Status Flags. - * - * This returns the status flag - * - * param base UTICK peripheral base address. - * return status register value - */ -uint32_t UTICK_GetStatusFlags(UTICK_Type *base) -{ - return (base->STAT); -} - -/*! - * brief Clear Status Interrupt Flags. - * - * This clears intr status flag - * - * param base UTICK peripheral base address. - * return none - */ -void UTICK_ClearStatusFlags(UTICK_Type *base) -{ - base->STAT = UTICK_STAT_INTR_MASK; -} - -/*! - * brief UTICK Interrupt Service Handler. - * - * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request - * in UTICK_SetTick()). - * if no user callback is scheduled, the interrupt will simply be cleared. - * - * param base UTICK peripheral base address. - * param cb callback scheduled for this instance of UTICK - * return none - */ -void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb) -{ - UTICK_ClearStatusFlags(base); - if (cb != NULL) - { - cb(); - } -} - -#if defined(UTICK0) -void UTICK0_DriverIRQHandler(void); -void UTICK0_DriverIRQHandler(void) -{ - s_utickIsr(UTICK0, s_utickHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif -#if defined(UTICK1) -void UTICK1_DriverIRQHandler(void); -void UTICK1_DriverIRQHandler(void) -{ - s_utickIsr(UTICK1, s_utickHandle[1]); - SDK_ISR_EXIT_BARRIER; -} -#endif -#if defined(UTICK2) -void UTICK2_DriverIRQHandler(void); -void UTICK2_DriverIRQHandler(void) -{ - s_utickIsr(UTICK2, s_utickHandle[2]); - SDK_ISR_EXIT_BARRIER; -} -#endif -#if defined(UTICK) -void UTICK_DriverIRQHandler(void); -void UTICK_DriverIRQHandler(void) -{ - s_utickIsr(UTICK, s_utickHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_utick.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_utick.h deleted file mode 100644 index 48c7d6b86de..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_utick.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019, 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_UTICK_H_ -#define _FSL_UTICK_H_ - -#include "fsl_common.h" -/*! - * @addtogroup utick - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief UTICK driver version 2.0.5. */ -#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) -/*@}*/ - -/*! @brief UTICK timer operational mode. */ -typedef enum _utick_mode -{ - kUTICK_Onetime = 0x0U, /*!< Trigger once*/ - kUTICK_Repeat = 0x1U, /*!< Trigger repeatedly */ -} utick_mode_t; - -/*! @brief UTICK callback function. */ -typedef void (*utick_callback_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes an UTICK by turning its bus clock on - * - */ -void UTICK_Init(UTICK_Type *base); - -/*! - * @brief Deinitializes a UTICK instance. - * - * This function shuts down Utick bus clock - * - * @param base UTICK peripheral base address. - */ -void UTICK_Deinit(UTICK_Type *base); -/*! - * @brief Get Status Flags. - * - * This returns the status flag - * - * @param base UTICK peripheral base address. - * @return status register value - */ -uint32_t UTICK_GetStatusFlags(UTICK_Type *base); -/*! - * @brief Clear Status Interrupt Flags. - * - * This clears intr status flag - * - * @param base UTICK peripheral base address. - * @return none - */ -void UTICK_ClearStatusFlags(UTICK_Type *base); - -/*! - * @brief Starts UTICK. - * - * This function starts a repeat/onetime countdown with an optional callback - * - * @param base UTICK peripheral base address. - * @param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * @param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * @param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) - * @return none - */ -void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb); -/*! - * @brief UTICK Interrupt Service Handler. - * - * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request - * in UTICK_SetTick()). - * if no user callback is scheduled, the interrupt will simply be cleared. - * - * @param base UTICK peripheral base address. - * @param cb callback scheduled for this instance of UTICK - * @return none - */ -void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_UTICK_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_wwdt.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_wwdt.c deleted file mode 100644 index 6680148acf7..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_wwdt.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_wwdt.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.wwdt" -#endif - -#define FREQUENCY_3MHZ (3000000U) -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Gets the instance from the base address - * - * @param base WWDT peripheral base address - * - * @return The WWDT instance - */ -static uint32_t WWDT_GetInstance(WWDT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to WWDT bases for each instance. */ -static WWDT_Type *const s_wwdtBases[] = WWDT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to WWDT clocks for each instance. */ -static const clock_ip_name_t s_wwdtClocks[] = WWDT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) -/*! @brief Pointers to WWDT resets for each instance. */ -static const reset_ip_name_t s_wwdtResets[] = WWDT_RSTS; -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t WWDT_GetInstance(WWDT_Type *base) -{ - uint32_t instance; - uint32_t wwdtArrayCount = (sizeof(s_wwdtBases) / sizeof(s_wwdtBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < wwdtArrayCount; instance++) - { - if (s_wwdtBases[instance] == base) - { - break; - } - } - - assert(instance < wwdtArrayCount); - - return instance; -} - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Initializes WWDT configure structure. - * - * This function initializes the WWDT configure structure to default value. The default - * value are: - * code - * config->enableWwdt = true; - * config->enableWatchdogReset = false; - * config->enableWatchdogProtect = false; - * config->enableLockOscillator = false; - * config->windowValue = 0xFFFFFFU; - * config->timeoutValue = 0xFFFFFFU; - * config->warningValue = 0; - * endcode - * - * param config Pointer to WWDT config structure. - * see wwdt_config_t - */ -void WWDT_GetDefaultConfig(wwdt_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* Enable the watch dog */ - config->enableWwdt = true; - /* Disable the watchdog timeout reset */ - config->enableWatchdogReset = false; - /* Disable the watchdog protection for updating the timeout value */ - config->enableWatchdogProtect = false; -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) - /* Do not lock the watchdog oscillator */ - config->enableLockOscillator = false; -#endif - /* Windowing is not in effect */ - config->windowValue = 0xFFFFFFU; - /* Set the timeout value to the max */ - config->timeoutValue = 0xFFFFFFU; - /* No warning is provided */ - config->warningValue = 0; - /* Set clock frequency. */ - config->clockFreq_Hz = 0U; -} - -/*! - * brief Initializes the WWDT. - * - * This function initializes the WWDT. When called, the WWDT runs according to the configuration. - * - * Example: - * code - * wwdt_config_t config; - * WWDT_GetDefaultConfig(&config); - * config.timeoutValue = 0x7ffU; - * WWDT_Init(wwdt_base,&config); - * endcode - * - * param base WWDT peripheral base address - * param config The configuration of WWDT - */ -void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config) -{ - assert(NULL != config); - - uint32_t value = 0U; - uint32_t DelayUs = 0U; - uint32_t primaskValue = 0U; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the WWDT clock */ - CLOCK_EnableClock(s_wwdtClocks[WWDT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) - /* Reset the module. */ - RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]); -#endif - -#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) - /* PMC RESETCAUSE: set bit to clear it by write 1. */ - PMC->RESETCAUSE = PMC_RESETCAUSE_WDTRESET_MASK; - /* Enable the watchdog reset event to affect the system in the Power Management Controller */ - PMC->CTRL |= PMC_CTRL_WDTRESETENABLE_MASK; -#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ - -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) - value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) | - WWDT_MOD_LOCK(config->enableLockOscillator); -#else - value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset); -#endif - /* Clear legacy flag in the MOD register by software writing a "1" to this bit field.. */ - if (0U != (base->MOD & WWDT_MOD_WDINT_MASK)) - { - value |= WWDT_MOD_WDINT_MASK; - } - /* Set configuration */ - primaskValue = DisableGlobalIRQ(); - base->TC = WWDT_TC_COUNT(config->timeoutValue); - base->MOD = value; - base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue); - base->WARNINT = WWDT_WARNINT_WARNINT(config->warningValue); - /* Refreshes the WWDT timer. */ - base->FEED = WWDT_FIRST_WORD_OF_REFRESH; - base->FEED = WWDT_SECOND_WORD_OF_REFRESH; - EnableGlobalIRQ(primaskValue); - /* Read counter value to wait wwdt timer start*/ - if (config->enableWwdt) - { - while (base->TV == 0xFFUL) - { - } - } - - /* This WDPROTECT bit can be set once by software and is only cleared by a reset */ - if (config->enableWatchdogProtect && (0U == (base->MOD & WWDT_MOD_WDPROTECT_MASK))) - { - /* The config->clockFreq_Hz must be set in order to config the delay time. */ - assert(0U != config->clockFreq_Hz); - - /* Set the WDPROTECT bit after the Feed Sequence (0xAA, 0x55) with 3 WDCLK delay */ - DelayUs = FREQUENCY_3MHZ / config->clockFreq_Hz + 1U; - SDK_DelayAtLeastUs(DelayUs, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - - base->MOD |= WWDT_MOD_WDPROTECT(1U); - } -} - -/*! - * brief Shuts down the WWDT. - * - * This function shuts down the WWDT. - * - * param base WWDT peripheral base address - */ -void WWDT_Deinit(WWDT_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the WWDT clock */ - CLOCK_DisableClock(s_wwdtClocks[WWDT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Refreshes the WWDT timer. - * - * This function feeds the WWDT. - * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. - * - * param base WWDT peripheral base address - */ -void WWDT_Refresh(WWDT_Type *base) -{ - uint32_t primaskValue = 0U; - - /* Disable the global interrupt to protect refresh sequence */ - primaskValue = DisableGlobalIRQ(); - base->FEED = WWDT_FIRST_WORD_OF_REFRESH; - base->FEED = WWDT_SECOND_WORD_OF_REFRESH; - EnableGlobalIRQ(primaskValue); -} - -/*! - * brief Clear WWDT flag. - * - * This function clears WWDT status flag. - * - * Example for clearing warning flag: - * code - * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); - * endcode - * param base WWDT peripheral base address - * param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask) -{ - /* Clear the WDINT bit so that we don't accidentally clear it */ - uint32_t reg = (base->MOD & (~WWDT_MOD_WDINT_MASK)); - - /* Clear timeout by writing a zero */ - if (0U != (mask & (uint32_t)kWWDT_TimeoutFlag)) - { - reg &= ~WWDT_MOD_WDTOF_MASK; -#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) - /* PMC RESETCAUSE: set bit to clear it */ - PMC->RESETCAUSE = PMC_RESETCAUSE_WDTRESET_MASK; -#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ - } - - /* Clear warning interrupt flag by writing a one */ - if (0U != (mask & (uint32_t)kWWDT_WarningFlag)) - { - reg |= WWDT_MOD_WDINT_MASK; - } - - base->MOD = reg; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_wwdt.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_wwdt.h deleted file mode 100644 index 25462534966..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_wwdt.h +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_WWDT_H_ -#define _FSL_WWDT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup wwdt - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Defines WWDT driver version. */ -#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 1, 9)) -/*@}*/ - -/*! @name Refresh sequence */ -/*@{*/ -#define WWDT_FIRST_WORD_OF_REFRESH (0xAAU) /*!< First word of refresh sequence */ -#define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */ -/*@}*/ - -/*! @brief Describes WWDT configuration structure. */ -typedef struct _wwdt_config -{ - bool enableWwdt; /*!< Enables or disables WWDT */ - bool enableWatchdogReset; /*!< true: Watchdog timeout will cause a chip reset - false: Watchdog timeout will not cause a chip reset */ - bool enableWatchdogProtect; /*!< true: Enable watchdog protect i.e timeout value can only be - changed after counter is below warning & window values - false: Disable watchdog protect; timeout value can be changed - at any time */ -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) - bool enableLockOscillator; /*!< true: Disabling or powering down the watchdog oscillator is prevented - Once set, this bit can only be cleared by a reset - false: Do not lock oscillator */ -#endif - uint32_t windowValue; /*!< Window value, set this to 0xFFFFFF if windowing is not in effect */ - uint32_t timeoutValue; /*!< Timeout value */ - uint32_t warningValue; /*!< Watchdog time counter value that will generate a - warning interrupt. Set this to 0 for no warning */ - uint32_t clockFreq_Hz; /*!< Watchdog clock source frequency. */ -} wwdt_config_t; - -/*! - * @brief WWDT status flags. - * - * This structure contains the WWDT status flags for use in the WWDT functions. - */ -enum _wwdt_status_flags_t -{ - kWWDT_TimeoutFlag = WWDT_MOD_WDTOF_MASK, /*!< Time-out flag, set when the timer times out */ - kWWDT_WarningFlag = WWDT_MOD_WDINT_MASK /*!< Warning interrupt flag, set when timer is below the value WDWARNINT */ -}; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name WWDT Initialization and De-initialization - * @{ - */ - -/*! - * @brief Initializes WWDT configure structure. - * - * This function initializes the WWDT configure structure to default value. The default - * value are: - * @code - * config->enableWwdt = true; - * config->enableWatchdogReset = false; - * config->enableWatchdogProtect = false; - * config->enableLockOscillator = false; - * config->windowValue = 0xFFFFFFU; - * config->timeoutValue = 0xFFFFFFU; - * config->warningValue = 0; - * @endcode - * - * @param config Pointer to WWDT config structure. - * @see wwdt_config_t - */ -void WWDT_GetDefaultConfig(wwdt_config_t *config); - -/*! - * @brief Initializes the WWDT. - * - * This function initializes the WWDT. When called, the WWDT runs according to the configuration. - * - * Example: - * @code - * wwdt_config_t config; - * WWDT_GetDefaultConfig(&config); - * config.timeoutValue = 0x7ffU; - * WWDT_Init(wwdt_base,&config); - * @endcode - * - * @param base WWDT peripheral base address - * @param config The configuration of WWDT - */ -void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config); - -/*! - * @brief Shuts down the WWDT. - * - * This function shuts down the WWDT. - * - * @param base WWDT peripheral base address - */ -void WWDT_Deinit(WWDT_Type *base); - -/* @} */ - -/*! - * @name WWDT Functional Operation - * @{ - */ - -/*! - * @brief Enables the WWDT module. - * - * This function write value into WWDT_MOD register to enable the WWDT, it is a write-once bit; - * once this bit is set to one and a watchdog feed is performed, the watchdog timer will run - * permanently. - * - * @param base WWDT peripheral base address - */ -static inline void WWDT_Enable(WWDT_Type *base) -{ - base->MOD |= WWDT_MOD_WDEN_MASK; -} - -/*! - * @brief Disables the WWDT module. - * @deprecated Do not use this function. It will be deleted in next release version, for - * once the bit field of WDEN written with a 1, it can not be re-written with a 0. - * - * This function write value into WWDT_MOD register to disable the WWDT. - * - * @param base WWDT peripheral base address - */ -static inline void WWDT_Disable(WWDT_Type *base) -{ - base->MOD &= ~WWDT_MOD_WDEN_MASK; -} - -/*! - * @brief Gets all WWDT status flags. - * - * This function gets all status flags. - * - * Example for getting Timeout Flag: - * @code - * uint32_t status; - * status = WWDT_GetStatusFlags(wwdt_base) & kWWDT_TimeoutFlag; - * @endcode - * @param base WWDT peripheral base address - * @return The status flags. This is the logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -static inline uint32_t WWDT_GetStatusFlags(WWDT_Type *base) -{ -#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) - uint32_t status; - /* WDTOF is not set in case of WD reset - get info from PMC instead */ - status = (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); - if (PMC->RESETCAUSE & PMC_RESETCAUSE_WDTRESET_MASK) - { - status |= kWWDT_TimeoutFlag; - } - return status; -#else - return (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); -#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ -} - -/*! - * @brief Clear WWDT flag. - * - * This function clears WWDT status flag. - * - * Example for clearing warning flag: - * @code - * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); - * @endcode - * @param base WWDT peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask); - -/*! - * @brief Set the WWDT warning value. - * - * The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog - * interrupt. When the watchdog timer counter is no longer greater than the value defined by - * WARNINT, an interrupt will be generated after the subsequent WDCLK. - * - * @param base WWDT peripheral base address - * @param warningValue WWDT warning value. - */ -static inline void WWDT_SetWarningValue(WWDT_Type *base, uint32_t warningValue) -{ - base->WARNINT = WWDT_WARNINT_WARNINT(warningValue); -} - -/*! - * @brief Set the WWDT timeout value. - * - * This function sets the timeout value. Every time a feed sequence occurs the value in the TC - * register is loaded into the Watchdog timer. Writing a value below 0xFF will cause 0xFF to be - * loaded into the TC register. Thus the minimum time-out interval is TWDCLK*256*4. - * If enableWatchdogProtect flag is true in wwdt_config_t config structure, any attempt to change - * the timeout value before the watchdog counter is below the warning and window values - * will cause a watchdog reset and set the WDTOF flag. - * - * @param base WWDT peripheral base address - * @param timeoutCount WWDT timeout value, count of WWDT clock tick. - */ -static inline void WWDT_SetTimeoutValue(WWDT_Type *base, uint32_t timeoutCount) -{ - base->TC = WWDT_TC_COUNT(timeoutCount); -} - -/*! - * @brief Sets the WWDT window value. - * - * The WINDOW register determines the highest TV value allowed when a watchdog feed is performed. - * If a feed sequence occurs when timer value is greater than the value in WINDOW, a watchdog - * event will occur. To disable windowing, set windowValue to 0xFFFFFF (maximum possible timer - * value) so windowing is not in effect. - * - * @param base WWDT peripheral base address - * @param windowValue WWDT window value. - */ -static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue) -{ - base->WINDOW = WWDT_WINDOW_WINDOW(windowValue); -} - -/*! - * @brief Refreshes the WWDT timer. - * - * This function feeds the WWDT. - * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. - * - * @param base WWDT peripheral base address - */ -void WWDT_Refresh(WWDT_Type *base); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_WWDT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/fsl_device_registers.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/fsl_device_registers.h deleted file mode 100644 index 82442958234..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/fsl_device_registers.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __FSL_DEVICE_REGISTERS_H__ -#define __FSL_DEVICE_REGISTERS_H__ - -/* - * Include the cpu specific register header files. - * - * The CPU macro should be declared in the project or makefile. - */ -#if (defined(CPU_LPC55S16JBD100) || defined(CPU_LPC55S16JBD64) || defined(CPU_LPC55S16JEV59) || \ - defined(CPU_LPC55S16JEV98)) - -#define LPC55S16_SERIES - -/* CMSIS-style register definitions */ -#include "LPC55S16.h" -/* CPU specific feature definitions */ -#include "LPC55S16_features.h" - -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_DEVICE_REGISTERS_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/gcc/LPC55S16_flash.ld b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/gcc/LPC55S16_flash.ld deleted file mode 100644 index 1897ad11378..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/gcc/LPC55S16_flash.ld +++ /dev/null @@ -1,215 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S16JBD100 -** LPC55S16JBD64 -** LPC55S16JEV59 -** LPC55S16JEV98 -** -** Compiler: GNU C Compiler -** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 -** Version: rev. 1.1, 2019-12-03 -** Build: b220622 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000200 - m_text (RX) : ORIGIN = 0x00000200, LENGTH = 0x0003CE00 - m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00010000 - m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00004000 - m_usb_sram (RW) : ORIGIN = 0x20010000, LENGTH = 0x00004000 -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into internal flash */ - .interrupts : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.ramfunc*) /* for functions in ram */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - m_usb_bdt (NOLOAD) : - { - . = ALIGN(512); - *(m_usb_bdt) - } > m_usb_sram - - m_usb_global (NOLOAD) : - { - *(m_usb_global) - } > m_usb_sram - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/gcc/LPC55S16_ram.ld b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/gcc/LPC55S16_ram.ld deleted file mode 100644 index 02635a696bf..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/gcc/LPC55S16_ram.ld +++ /dev/null @@ -1,214 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S16JBD100 -** LPC55S16JBD64 -** LPC55S16JEV59 -** LPC55S16JEV98 -** -** Compiler: GNU C Compiler -** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 -** Version: rev. 1.1, 2019-12-03 -** Build: b220622 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x20000000, LENGTH = 0x00000200 - m_text (RX) : ORIGIN = 0x20000200, LENGTH = 0x0000FE00 - m_data (RW) : ORIGIN = 0x04000000, LENGTH = 0x00004000 - m_usb_sram (RW) : ORIGIN = 0x20010000, LENGTH = 0x00004000 -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into internal flash */ - .interrupts : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.ramfunc*) /* for functions in ram */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - m_usb_bdt (NOLOAD) : - { - . = ALIGN(512); - *(m_usb_bdt) - } > m_usb_sram - - m_usb_global (NOLOAD) : - { - *(m_usb_global) - } > m_usb_sram - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/gcc/startup_LPC55S16.S b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/gcc/startup_LPC55S16.S deleted file mode 100644 index 7b13cdccebc..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/gcc/startup_LPC55S16.S +++ /dev/null @@ -1,895 +0,0 @@ -/* --------------------------------------------------------------------------*/ -/* @file: startup_LPC55S16.s */ -/* @purpose: CMSIS Cortex-M33 Core Device Startup File */ -/* LPC55S16 */ -/* @version: 1.1 */ -/* @date: 2019-12-3 */ -/* --------------------------------------------------------------------------*/ -/* */ -/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2021 NXP */ -/* All rights reserved. */ -/* */ -/* SPDX-License-Identifier: BSD-3-Clause */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - - - .syntax unified - .arch armv8-m.main - - .section .isr_vector, "a" - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long MemManage_Handler /* MPU Fault Handler*/ - .long BusFault_Handler /* Bus Fault Handler*/ - .long UsageFault_Handler /* Usage Fault Handler*/ - .long SecureFault_Handler /* Secure Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long DebugMon_Handler /* Debug Monitor Handler*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts */ - .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ - .long DMA0_IRQHandler /* DMA0 controller */ - .long GINT0_IRQHandler /* GPIO group 0 */ - .long GINT1_IRQHandler /* GPIO group 1 */ - .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - .long UTICK0_IRQHandler /* Micro-tick Timer */ - .long MRT0_IRQHandler /* Multi-rate timer */ - .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ - .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ - .long SCT0_IRQHandler /* SCTimer/PWM */ - .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ - .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long ADC0_IRQHandler /* ADC0 */ - .long Reserved39_IRQHandler /* Reserved interrupt */ - .long ACMP_IRQHandler /* ACMP interrupts */ - .long Reserved41_IRQHandler /* Reserved interrupt */ - .long Reserved42_IRQHandler /* Reserved interrupt */ - .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ - .long USB0_IRQHandler /* USB device */ - .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ - .long Reserved46_IRQHandler /* Reserved interrupt */ - .long Reserved47_IRQHandler /* Reserved interrupt */ - .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ - .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ - .long OS_EVENT_IRQHandler /* OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ - .long Reserved55_IRQHandler /* Reserved interrupt */ - .long Reserved56_IRQHandler /* Reserved interrupt */ - .long Reserved57_IRQHandler /* Reserved interrupt */ - .long Reserved58_IRQHandler /* Reserved interrupt */ - .long CAN0_IRQ0_IRQHandler /* CAN0 interrupt0 */ - .long CAN0_IRQ1_IRQHandler /* CAN0 interrupt1 */ - .long Reserved61_IRQHandler /* Reserved interrupt */ - .long USB1_PHY_IRQHandler /* USB1_PHY */ - .long USB1_IRQHandler /* USB1 interrupt */ - .long USB1_NEEDCLK_IRQHandler /* USB1 activity */ - .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ - .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ - .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ - .long PLU_IRQHandler /* PLU interrupt */ - .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ - .long HASHCRYPT_IRQHandler /* SHA interrupt */ - .long CASER_IRQHandler /* CASPER interrupt */ - .long PUF_IRQHandler /* PUF interrupt */ - .long Reserved73_IRQHandler /* Reserved interrupt */ - .long DMA1_IRQHandler /* DMA1 interrupt */ - .long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ - .long CDOG_IRQHandler /* CDOG interrupt */ - - .size __Vectors, . - __Vectors - - .text - .thumb - -/* Reset Handler */ - .thumb_func - .align 2 - .globl Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - cpsid i /* Mask interrupts */ - .equ VTOR, 0xE000ED08 - ldr r0, =VTOR - ldr r1, =__Vectors - str r1, [r0] - ldr r2, [r1] - msr msp, r2 - ldr R0, =__StackLimit - msr msplim, R0 -#ifndef __NO_SYSTEM_INIT - ldr r0,=SystemInit - blx r0 -#endif -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -#if 1 -/* Here are two copies of loop implemenations. First one favors code size - * and the second one favors performance. Default uses the first one. - * Change to "#if 0" to use the second one */ -.LC0: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .LC0 -#else - subs r3, r2 - ble .LC1 -.LC0: - subs r3, #4 - ldr r0, [r1, r3] - str r0, [r2, r3] - bgt .LC0 -.LC1: -#endif - -#ifdef __STARTUP_CLEAR_BSS -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * Loop to zero out BSS section, which uses following symbols - * in linker script: - * __bss_start__: start of BSS section. Must align to 4 - * __bss_end__: end of BSS section. Must align to 4 - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.LC2: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC2 -#endif /* __STARTUP_CLEAR_BSS */ - -/* Add stack / heap initializaiton */ - movs r0, 0 - ldr r1, =__HeapBase - ldr r2, =__HeapLimit -.LC3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC3 - - ldr r1, =__StackLimit - ldr r2, =__StackTop -.LC4: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC4 -/*End of stack / heap initializaiton */ - cpsie i /* Unmask interrupts */ - -#ifndef __START -#define __START _start -#endif -#ifndef __ATOLLIC__ - ldr r0,=__START - blx r0 -#else - ldr r0,=__libc_init_array - blx r0 - ldr r0,=main - bx r0 -#endif - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - - .align 1 - .thumb_func - .weak WDT_BOD_IRQHandler - .type WDT_BOD_IRQHandler, %function -WDT_BOD_IRQHandler: - ldr r0,=WDT_BOD_DriverIRQHandler - bx r0 - .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler - - .align 1 - .thumb_func - .weak DMA0_IRQHandler - .type DMA0_IRQHandler, %function -DMA0_IRQHandler: - ldr r0,=DMA0_DriverIRQHandler - bx r0 - .size DMA0_IRQHandler, . - DMA0_IRQHandler - - .align 1 - .thumb_func - .weak GINT0_IRQHandler - .type GINT0_IRQHandler, %function -GINT0_IRQHandler: - ldr r0,=GINT0_DriverIRQHandler - bx r0 - .size GINT0_IRQHandler, . - GINT0_IRQHandler - - .align 1 - .thumb_func - .weak GINT1_IRQHandler - .type GINT1_IRQHandler, %function -GINT1_IRQHandler: - ldr r0,=GINT1_DriverIRQHandler - bx r0 - .size GINT1_IRQHandler, . - GINT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT0_IRQHandler - .type PIN_INT0_IRQHandler, %function -PIN_INT0_IRQHandler: - ldr r0,=PIN_INT0_DriverIRQHandler - bx r0 - .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT1_IRQHandler - .type PIN_INT1_IRQHandler, %function -PIN_INT1_IRQHandler: - ldr r0,=PIN_INT1_DriverIRQHandler - bx r0 - .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT2_IRQHandler - .type PIN_INT2_IRQHandler, %function -PIN_INT2_IRQHandler: - ldr r0,=PIN_INT2_DriverIRQHandler - bx r0 - .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT3_IRQHandler - .type PIN_INT3_IRQHandler, %function -PIN_INT3_IRQHandler: - ldr r0,=PIN_INT3_DriverIRQHandler - bx r0 - .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler - - .align 1 - .thumb_func - .weak UTICK0_IRQHandler - .type UTICK0_IRQHandler, %function -UTICK0_IRQHandler: - ldr r0,=UTICK0_DriverIRQHandler - bx r0 - .size UTICK0_IRQHandler, . - UTICK0_IRQHandler - - .align 1 - .thumb_func - .weak MRT0_IRQHandler - .type MRT0_IRQHandler, %function -MRT0_IRQHandler: - ldr r0,=MRT0_DriverIRQHandler - bx r0 - .size MRT0_IRQHandler, . - MRT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER0_IRQHandler - .type CTIMER0_IRQHandler, %function -CTIMER0_IRQHandler: - ldr r0,=CTIMER0_DriverIRQHandler - bx r0 - .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER1_IRQHandler - .type CTIMER1_IRQHandler, %function -CTIMER1_IRQHandler: - ldr r0,=CTIMER1_DriverIRQHandler - bx r0 - .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler - - .align 1 - .thumb_func - .weak SCT0_IRQHandler - .type SCT0_IRQHandler, %function -SCT0_IRQHandler: - ldr r0,=SCT0_DriverIRQHandler - bx r0 - .size SCT0_IRQHandler, . - SCT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER3_IRQHandler - .type CTIMER3_IRQHandler, %function -CTIMER3_IRQHandler: - ldr r0,=CTIMER3_DriverIRQHandler - bx r0 - .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM0_IRQHandler - .type FLEXCOMM0_IRQHandler, %function -FLEXCOMM0_IRQHandler: - ldr r0,=FLEXCOMM0_DriverIRQHandler - bx r0 - .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM1_IRQHandler - .type FLEXCOMM1_IRQHandler, %function -FLEXCOMM1_IRQHandler: - ldr r0,=FLEXCOMM1_DriverIRQHandler - bx r0 - .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM2_IRQHandler - .type FLEXCOMM2_IRQHandler, %function -FLEXCOMM2_IRQHandler: - ldr r0,=FLEXCOMM2_DriverIRQHandler - bx r0 - .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM3_IRQHandler - .type FLEXCOMM3_IRQHandler, %function -FLEXCOMM3_IRQHandler: - ldr r0,=FLEXCOMM3_DriverIRQHandler - bx r0 - .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM4_IRQHandler - .type FLEXCOMM4_IRQHandler, %function -FLEXCOMM4_IRQHandler: - ldr r0,=FLEXCOMM4_DriverIRQHandler - bx r0 - .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM5_IRQHandler - .type FLEXCOMM5_IRQHandler, %function -FLEXCOMM5_IRQHandler: - ldr r0,=FLEXCOMM5_DriverIRQHandler - bx r0 - .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM6_IRQHandler - .type FLEXCOMM6_IRQHandler, %function -FLEXCOMM6_IRQHandler: - ldr r0,=FLEXCOMM6_DriverIRQHandler - bx r0 - .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM7_IRQHandler - .type FLEXCOMM7_IRQHandler, %function -FLEXCOMM7_IRQHandler: - ldr r0,=FLEXCOMM7_DriverIRQHandler - bx r0 - .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_IRQHandler - .type ADC0_IRQHandler, %function -ADC0_IRQHandler: - ldr r0,=ADC0_DriverIRQHandler - bx r0 - .size ADC0_IRQHandler, . - ADC0_IRQHandler - - .align 1 - .thumb_func - .weak Reserved39_IRQHandler - .type Reserved39_IRQHandler, %function -Reserved39_IRQHandler: - ldr r0,=Reserved39_DriverIRQHandler - bx r0 - .size Reserved39_IRQHandler, . - Reserved39_IRQHandler - - .align 1 - .thumb_func - .weak ACMP_IRQHandler - .type ACMP_IRQHandler, %function -ACMP_IRQHandler: - ldr r0,=ACMP_DriverIRQHandler - bx r0 - .size ACMP_IRQHandler, . - ACMP_IRQHandler - - .align 1 - .thumb_func - .weak Reserved41_IRQHandler - .type Reserved41_IRQHandler, %function -Reserved41_IRQHandler: - ldr r0,=Reserved41_DriverIRQHandler - bx r0 - .size Reserved41_IRQHandler, . - Reserved41_IRQHandler - - .align 1 - .thumb_func - .weak Reserved42_IRQHandler - .type Reserved42_IRQHandler, %function -Reserved42_IRQHandler: - ldr r0,=Reserved42_DriverIRQHandler - bx r0 - .size Reserved42_IRQHandler, . - Reserved42_IRQHandler - - .align 1 - .thumb_func - .weak USB0_NEEDCLK_IRQHandler - .type USB0_NEEDCLK_IRQHandler, %function -USB0_NEEDCLK_IRQHandler: - ldr r0,=USB0_NEEDCLK_DriverIRQHandler - bx r0 - .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak USB0_IRQHandler - .type USB0_IRQHandler, %function -USB0_IRQHandler: - ldr r0,=USB0_DriverIRQHandler - bx r0 - .size USB0_IRQHandler, . - USB0_IRQHandler - - .align 1 - .thumb_func - .weak RTC_IRQHandler - .type RTC_IRQHandler, %function -RTC_IRQHandler: - ldr r0,=RTC_DriverIRQHandler - bx r0 - .size RTC_IRQHandler, . - RTC_IRQHandler - - .align 1 - .thumb_func - .weak Reserved46_IRQHandler - .type Reserved46_IRQHandler, %function -Reserved46_IRQHandler: - ldr r0,=Reserved46_DriverIRQHandler - bx r0 - .size Reserved46_IRQHandler, . - Reserved46_IRQHandler - - .align 1 - .thumb_func - .weak Reserved47_IRQHandler - .type Reserved47_IRQHandler, %function -Reserved47_IRQHandler: - ldr r0,=Reserved47_DriverIRQHandler - bx r0 - .size Reserved47_IRQHandler, . - Reserved47_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT4_IRQHandler - .type PIN_INT4_IRQHandler, %function -PIN_INT4_IRQHandler: - ldr r0,=PIN_INT4_DriverIRQHandler - bx r0 - .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT5_IRQHandler - .type PIN_INT5_IRQHandler, %function -PIN_INT5_IRQHandler: - ldr r0,=PIN_INT5_DriverIRQHandler - bx r0 - .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT6_IRQHandler - .type PIN_INT6_IRQHandler, %function -PIN_INT6_IRQHandler: - ldr r0,=PIN_INT6_DriverIRQHandler - bx r0 - .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT7_IRQHandler - .type PIN_INT7_IRQHandler, %function -PIN_INT7_IRQHandler: - ldr r0,=PIN_INT7_DriverIRQHandler - bx r0 - .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER2_IRQHandler - .type CTIMER2_IRQHandler, %function -CTIMER2_IRQHandler: - ldr r0,=CTIMER2_DriverIRQHandler - bx r0 - .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER4_IRQHandler - .type CTIMER4_IRQHandler, %function -CTIMER4_IRQHandler: - ldr r0,=CTIMER4_DriverIRQHandler - bx r0 - .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler - - .align 1 - .thumb_func - .weak OS_EVENT_IRQHandler - .type OS_EVENT_IRQHandler, %function -OS_EVENT_IRQHandler: - ldr r0,=OS_EVENT_DriverIRQHandler - bx r0 - .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler - - .align 1 - .thumb_func - .weak Reserved55_IRQHandler - .type Reserved55_IRQHandler, %function -Reserved55_IRQHandler: - ldr r0,=Reserved55_DriverIRQHandler - bx r0 - .size Reserved55_IRQHandler, . - Reserved55_IRQHandler - - .align 1 - .thumb_func - .weak Reserved56_IRQHandler - .type Reserved56_IRQHandler, %function -Reserved56_IRQHandler: - ldr r0,=Reserved56_DriverIRQHandler - bx r0 - .size Reserved56_IRQHandler, . - Reserved56_IRQHandler - - .align 1 - .thumb_func - .weak Reserved57_IRQHandler - .type Reserved57_IRQHandler, %function -Reserved57_IRQHandler: - ldr r0,=Reserved57_DriverIRQHandler - bx r0 - .size Reserved57_IRQHandler, . - Reserved57_IRQHandler - - .align 1 - .thumb_func - .weak Reserved58_IRQHandler - .type Reserved58_IRQHandler, %function -Reserved58_IRQHandler: - ldr r0,=Reserved58_DriverIRQHandler - bx r0 - .size Reserved58_IRQHandler, . - Reserved58_IRQHandler - - .align 1 - .thumb_func - .weak CAN0_IRQ0_IRQHandler - .type CAN0_IRQ0_IRQHandler, %function -CAN0_IRQ0_IRQHandler: - ldr r0,=CAN0_IRQ0_DriverIRQHandler - bx r0 - .size CAN0_IRQ0_IRQHandler, . - CAN0_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak CAN0_IRQ1_IRQHandler - .type CAN0_IRQ1_IRQHandler, %function -CAN0_IRQ1_IRQHandler: - ldr r0,=CAN0_IRQ1_DriverIRQHandler - bx r0 - .size CAN0_IRQ1_IRQHandler, . - CAN0_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak Reserved61_IRQHandler - .type Reserved61_IRQHandler, %function -Reserved61_IRQHandler: - ldr r0,=Reserved61_DriverIRQHandler - bx r0 - .size Reserved61_IRQHandler, . - Reserved61_IRQHandler - - .align 1 - .thumb_func - .weak USB1_PHY_IRQHandler - .type USB1_PHY_IRQHandler, %function -USB1_PHY_IRQHandler: - ldr r0,=USB1_PHY_DriverIRQHandler - bx r0 - .size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler - - .align 1 - .thumb_func - .weak USB1_IRQHandler - .type USB1_IRQHandler, %function -USB1_IRQHandler: - ldr r0,=USB1_DriverIRQHandler - bx r0 - .size USB1_IRQHandler, . - USB1_IRQHandler - - .align 1 - .thumb_func - .weak USB1_NEEDCLK_IRQHandler - .type USB1_NEEDCLK_IRQHandler, %function -USB1_NEEDCLK_IRQHandler: - ldr r0,=USB1_NEEDCLK_DriverIRQHandler - bx r0 - .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak SEC_HYPERVISOR_CALL_IRQHandler - .type SEC_HYPERVISOR_CALL_IRQHandler, %function -SEC_HYPERVISOR_CALL_IRQHandler: - ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler - bx r0 - .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ0_IRQHandler - .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function -SEC_GPIO_INT0_IRQ0_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ1_IRQHandler - .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function -SEC_GPIO_INT0_IRQ1_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak PLU_IRQHandler - .type PLU_IRQHandler, %function -PLU_IRQHandler: - ldr r0,=PLU_DriverIRQHandler - bx r0 - .size PLU_IRQHandler, . - PLU_IRQHandler - - .align 1 - .thumb_func - .weak SEC_VIO_IRQHandler - .type SEC_VIO_IRQHandler, %function -SEC_VIO_IRQHandler: - ldr r0,=SEC_VIO_DriverIRQHandler - bx r0 - .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler - - .align 1 - .thumb_func - .weak HASHCRYPT_IRQHandler - .type HASHCRYPT_IRQHandler, %function -HASHCRYPT_IRQHandler: - ldr r0,=HASHCRYPT_DriverIRQHandler - bx r0 - .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler - - .align 1 - .thumb_func - .weak CASER_IRQHandler - .type CASER_IRQHandler, %function -CASER_IRQHandler: - ldr r0,=CASER_DriverIRQHandler - bx r0 - .size CASER_IRQHandler, . - CASER_IRQHandler - - .align 1 - .thumb_func - .weak PUF_IRQHandler - .type PUF_IRQHandler, %function -PUF_IRQHandler: - ldr r0,=PUF_DriverIRQHandler - bx r0 - .size PUF_IRQHandler, . - PUF_IRQHandler - - .align 1 - .thumb_func - .weak Reserved73_IRQHandler - .type Reserved73_IRQHandler, %function -Reserved73_IRQHandler: - ldr r0,=Reserved73_DriverIRQHandler - bx r0 - .size Reserved73_IRQHandler, . - Reserved73_IRQHandler - - .align 1 - .thumb_func - .weak DMA1_IRQHandler - .type DMA1_IRQHandler, %function -DMA1_IRQHandler: - ldr r0,=DMA1_DriverIRQHandler - bx r0 - .size DMA1_IRQHandler, . - DMA1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM8_IRQHandler - .type FLEXCOMM8_IRQHandler, %function -FLEXCOMM8_IRQHandler: - ldr r0,=FLEXCOMM8_DriverIRQHandler - bx r0 - .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler - - .align 1 - .thumb_func - .weak CDOG_IRQHandler - .type CDOG_IRQHandler, %function -CDOG_IRQHandler: - ldr r0,=CDOG_DriverIRQHandler - bx r0 - .size CDOG_IRQHandler, . - CDOG_IRQHandler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm -/* Exception Handlers */ - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SecureFault_Handler - def_irq_handler DebugMon_Handler - def_irq_handler WDT_BOD_DriverIRQHandler - def_irq_handler DMA0_DriverIRQHandler - def_irq_handler GINT0_DriverIRQHandler - def_irq_handler GINT1_DriverIRQHandler - def_irq_handler PIN_INT0_DriverIRQHandler - def_irq_handler PIN_INT1_DriverIRQHandler - def_irq_handler PIN_INT2_DriverIRQHandler - def_irq_handler PIN_INT3_DriverIRQHandler - def_irq_handler UTICK0_DriverIRQHandler - def_irq_handler MRT0_DriverIRQHandler - def_irq_handler CTIMER0_DriverIRQHandler - def_irq_handler CTIMER1_DriverIRQHandler - def_irq_handler SCT0_DriverIRQHandler - def_irq_handler CTIMER3_DriverIRQHandler - def_irq_handler FLEXCOMM0_DriverIRQHandler - def_irq_handler FLEXCOMM1_DriverIRQHandler - def_irq_handler FLEXCOMM2_DriverIRQHandler - def_irq_handler FLEXCOMM3_DriverIRQHandler - def_irq_handler FLEXCOMM4_DriverIRQHandler - def_irq_handler FLEXCOMM5_DriverIRQHandler - def_irq_handler FLEXCOMM6_DriverIRQHandler - def_irq_handler FLEXCOMM7_DriverIRQHandler - def_irq_handler ADC0_DriverIRQHandler - def_irq_handler Reserved39_DriverIRQHandler - def_irq_handler ACMP_DriverIRQHandler - def_irq_handler Reserved41_DriverIRQHandler - def_irq_handler Reserved42_DriverIRQHandler - def_irq_handler USB0_NEEDCLK_DriverIRQHandler - def_irq_handler USB0_DriverIRQHandler - def_irq_handler RTC_DriverIRQHandler - def_irq_handler Reserved46_DriverIRQHandler - def_irq_handler Reserved47_DriverIRQHandler - def_irq_handler PIN_INT4_DriverIRQHandler - def_irq_handler PIN_INT5_DriverIRQHandler - def_irq_handler PIN_INT6_DriverIRQHandler - def_irq_handler PIN_INT7_DriverIRQHandler - def_irq_handler CTIMER2_DriverIRQHandler - def_irq_handler CTIMER4_DriverIRQHandler - def_irq_handler OS_EVENT_DriverIRQHandler - def_irq_handler Reserved55_DriverIRQHandler - def_irq_handler Reserved56_DriverIRQHandler - def_irq_handler Reserved57_DriverIRQHandler - def_irq_handler Reserved58_DriverIRQHandler - def_irq_handler CAN0_IRQ0_DriverIRQHandler - def_irq_handler CAN0_IRQ1_DriverIRQHandler - def_irq_handler Reserved61_DriverIRQHandler - def_irq_handler USB1_PHY_DriverIRQHandler - def_irq_handler USB1_DriverIRQHandler - def_irq_handler USB1_NEEDCLK_DriverIRQHandler - def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler - def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler - def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler - def_irq_handler PLU_DriverIRQHandler - def_irq_handler SEC_VIO_DriverIRQHandler - def_irq_handler HASHCRYPT_DriverIRQHandler - def_irq_handler CASER_DriverIRQHandler - def_irq_handler PUF_DriverIRQHandler - def_irq_handler Reserved73_DriverIRQHandler - def_irq_handler DMA1_DriverIRQHandler - def_irq_handler FLEXCOMM8_DriverIRQHandler - def_irq_handler CDOG_DriverIRQHandler - - .end diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/iar/LPC55S16_flash.icf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/iar/LPC55S16_flash.icf deleted file mode 100644 index 1fa04c399b6..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/iar/LPC55S16_flash.icf +++ /dev/null @@ -1,101 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S16JBD100 -** LPC55S16JBD64 -** LPC55S16JEV59 -** LPC55S16JEV98 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 -** Version: rev. 1.1, 2019-12-03 -** Build: b220622 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -define symbol usb_bdt_size = 0x0; -/* Stack and Heap Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define symbol m_interrupts_start = 0x00000000; -define symbol m_interrupts_end = 0x000001FF; - -define symbol m_text_start = 0x00000200; -define symbol m_text_end = 0x0003CFFF; - -define symbol m_data_start = 0x20000000; -define symbol m_data_end = 0x2000FFFF; - -define symbol m_sramx_start = 0x04000000; -define symbol m_sramx_end = 0x04003FFF; - -define symbol m_usb_sram_start = 0x20010000; -define symbol m_usb_sram_end = 0x20013FFF; - -define memory mem with size = 4G; - -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -if (isdefinedsymbol(__use_shmem__)) { - define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; -} - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - -/* regions for USB */ -define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; -define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; -place in USB_BDT_region { section m_usb_bdt }; -place in USB_SRAM_region { section m_usb_global }; - -initialize by copy { readwrite, section .textrw }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - /* Required in a multi-threaded application */ - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; -if (isdefinedsymbol(__use_shmem__)) { - do not initialize { section rpmsg_sh_mem_section }; -} - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; - - - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/iar/LPC55S16_ram.icf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/iar/LPC55S16_ram.icf deleted file mode 100644 index 2f7306acbc3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/iar/LPC55S16_ram.icf +++ /dev/null @@ -1,98 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S16JBD100 -** LPC55S16JBD64 -** LPC55S16JEV59 -** LPC55S16JEV98 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 -** Version: rev. 1.1, 2019-12-03 -** Build: b220622 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -define symbol usb_bdt_size = 0x0; -/* Stack and Heap Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define symbol m_interrupts_start = 0x20000000; -define symbol m_interrupts_end = 0x200001FF; - -define symbol m_text_start = 0x20000200; -define symbol m_text_end = 0x2000FFFF; - -define symbol m_data_start = 0x04000000; -define symbol m_data_end = 0x04003FFF; - -define symbol m_usb_sram_start = 0x20010000; -define symbol m_usb_sram_end = 0x20013FFF; - -define memory mem with size = 4G; - -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -if (isdefinedsymbol(__use_shmem__)) { - define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; -} - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - -/* regions for USB */ -define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; -define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; -place in USB_BDT_region { section m_usb_bdt }; -place in USB_SRAM_region { section m_usb_global }; - -initialize by copy { readwrite, section .textrw }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - /* Required in a multi-threaded application */ - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; -if (isdefinedsymbol(__use_shmem__)) { - do not initialize { section rpmsg_sh_mem_section }; -} - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; - - - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/iar/startup_LPC55S16.s b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/iar/startup_LPC55S16.s deleted file mode 100644 index 7a592dc667f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/iar/startup_LPC55S16.s +++ /dev/null @@ -1,643 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC55S16.s -; * @purpose: CMSIS Cortex-M33 Core Device Startup File -; * LPC55S16 -; * @version: 1.1 -; * @date: 2019-12-3 -; *---------------------------------------------------------------------------- -; * -; Copyright 1997-2016 Freescale Semiconductor, Inc. -; Copyright 2016-2021 NXP -; All rights reserved. -; -; SPDX-License-Identifier: BSD-3-Clause -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__iar_init$$done: ; The vector table is not needed - ; until after copy initialization is done - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD SecureFault_Handler - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt - DCD DMA0_IRQHandler ; DMA0 controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD ADC0_IRQHandler ; ADC0 - DCD Reserved39_IRQHandler ; Reserved interrupt - DCD ACMP_IRQHandler ; ACMP interrupts - DCD Reserved41_IRQHandler ; Reserved interrupt - DCD Reserved42_IRQHandler ; Reserved interrupt - DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt - DCD USB0_IRQHandler ; USB device - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD Reserved46_IRQHandler ; Reserved interrupt - DCD Reserved47_IRQHandler ; Reserved interrupt - DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int - DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int - DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int - DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int - DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 - DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 - DCD OS_EVENT_IRQHandler ; OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts - DCD Reserved55_IRQHandler ; Reserved interrupt - DCD Reserved56_IRQHandler ; Reserved interrupt - DCD Reserved57_IRQHandler ; Reserved interrupt - DCD Reserved58_IRQHandler ; Reserved interrupt - DCD CAN0_IRQ0_IRQHandler ; CAN0 interrupt0 - DCD CAN0_IRQ1_IRQHandler ; CAN0 interrupt1 - DCD Reserved61_IRQHandler ; Reserved interrupt - DCD USB1_PHY_IRQHandler ; USB1_PHY - DCD USB1_IRQHandler ; USB1 interrupt - DCD USB1_NEEDCLK_IRQHandler ; USB1 activity - DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt - DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT0_IRQ0 interrupt - DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT0_IRQ1 interrupt - DCD PLU_IRQHandler ; PLU interrupt - DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt - DCD HASHCRYPT_IRQHandler ; SHA interrupt - DCD CASER_IRQHandler ; CASPER interrupt - DCD PUF_IRQHandler ; PUF interrupt - DCD Reserved73_IRQHandler ; Reserved interrupt - DCD DMA1_IRQHandler ; DMA1 interrupt - DCD FLEXCOMM8_IRQHandler ; Flexcomm Interface 8 (SPI, , FLEXCOMM) - DCD CDOG_IRQHandler ; CDOG interrupt -__Vectors_End - - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__vector_table - STR R1, [R0] - LDR R2, [R1] - MSR MSP, R2 - LDR R0, =sfb(CSTACK) - MSR MSPLIM, R0 - CPSIE I ; Unmask interrupts - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SecureFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SecureFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK WDT_BOD_IRQHandler - PUBWEAK WDT_BOD_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -WDT_BOD_IRQHandler - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler - LDR R0, =DMA0_DriverIRQHandler - BX R0 - PUBWEAK GINT0_IRQHandler - PUBWEAK GINT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT0_IRQHandler - LDR R0, =GINT0_DriverIRQHandler - BX R0 - PUBWEAK GINT1_IRQHandler - PUBWEAK GINT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT1_IRQHandler - LDR R0, =GINT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT0_IRQHandler - PUBWEAK PIN_INT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT0_IRQHandler - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT1_IRQHandler - PUBWEAK PIN_INT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT1_IRQHandler - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT2_IRQHandler - PUBWEAK PIN_INT2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT2_IRQHandler - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT3_IRQHandler - PUBWEAK PIN_INT3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT3_IRQHandler - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - PUBWEAK UTICK0_IRQHandler - PUBWEAK UTICK0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UTICK0_IRQHandler - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - PUBWEAK MRT0_IRQHandler - PUBWEAK MRT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -MRT0_IRQHandler - LDR R0, =MRT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER0_IRQHandler - PUBWEAK CTIMER0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER0_IRQHandler - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER1_IRQHandler - PUBWEAK CTIMER1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER1_IRQHandler - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - PUBWEAK SCT0_IRQHandler - PUBWEAK SCT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SCT0_IRQHandler - LDR R0, =SCT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER3_IRQHandler - PUBWEAK CTIMER3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER3_IRQHandler - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM0_IRQHandler - PUBWEAK FLEXCOMM0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM0_IRQHandler - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM1_IRQHandler - PUBWEAK FLEXCOMM1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM1_IRQHandler - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM2_IRQHandler - PUBWEAK FLEXCOMM2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM2_IRQHandler - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM3_IRQHandler - PUBWEAK FLEXCOMM3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM3_IRQHandler - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM4_IRQHandler - PUBWEAK FLEXCOMM4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM4_IRQHandler - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM5_IRQHandler - PUBWEAK FLEXCOMM5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM5_IRQHandler - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM6_IRQHandler - PUBWEAK FLEXCOMM6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM6_IRQHandler - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM7_IRQHandler - PUBWEAK FLEXCOMM7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM7_IRQHandler - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - PUBWEAK ADC0_IRQHandler - PUBWEAK ADC0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_IRQHandler - LDR R0, =ADC0_DriverIRQHandler - BX R0 - PUBWEAK Reserved39_IRQHandler - PUBWEAK Reserved39_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved39_IRQHandler - LDR R0, =Reserved39_DriverIRQHandler - BX R0 - PUBWEAK ACMP_IRQHandler - PUBWEAK ACMP_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ACMP_IRQHandler - LDR R0, =ACMP_DriverIRQHandler - BX R0 - PUBWEAK Reserved41_IRQHandler - PUBWEAK Reserved41_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved41_IRQHandler - LDR R0, =Reserved41_DriverIRQHandler - BX R0 - PUBWEAK Reserved42_IRQHandler - PUBWEAK Reserved42_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved42_IRQHandler - LDR R0, =Reserved42_DriverIRQHandler - BX R0 - PUBWEAK USB0_NEEDCLK_IRQHandler - PUBWEAK USB0_NEEDCLK_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_NEEDCLK_IRQHandler - LDR R0, =USB0_NEEDCLK_DriverIRQHandler - BX R0 - PUBWEAK USB0_IRQHandler - PUBWEAK USB0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_IRQHandler - LDR R0, =USB0_DriverIRQHandler - BX R0 - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -RTC_IRQHandler - LDR R0, =RTC_DriverIRQHandler - BX R0 - PUBWEAK Reserved46_IRQHandler - PUBWEAK Reserved46_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved46_IRQHandler - LDR R0, =Reserved46_DriverIRQHandler - BX R0 - PUBWEAK Reserved47_IRQHandler - PUBWEAK Reserved47_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved47_IRQHandler - LDR R0, =Reserved47_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT4_IRQHandler - PUBWEAK PIN_INT4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT4_IRQHandler - LDR R0, =PIN_INT4_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT5_IRQHandler - PUBWEAK PIN_INT5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT5_IRQHandler - LDR R0, =PIN_INT5_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT6_IRQHandler - PUBWEAK PIN_INT6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT6_IRQHandler - LDR R0, =PIN_INT6_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT7_IRQHandler - PUBWEAK PIN_INT7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT7_IRQHandler - LDR R0, =PIN_INT7_DriverIRQHandler - BX R0 - PUBWEAK CTIMER2_IRQHandler - PUBWEAK CTIMER2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER2_IRQHandler - LDR R0, =CTIMER2_DriverIRQHandler - BX R0 - PUBWEAK CTIMER4_IRQHandler - PUBWEAK CTIMER4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER4_IRQHandler - LDR R0, =CTIMER4_DriverIRQHandler - BX R0 - PUBWEAK OS_EVENT_IRQHandler - PUBWEAK OS_EVENT_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -OS_EVENT_IRQHandler - LDR R0, =OS_EVENT_DriverIRQHandler - BX R0 - PUBWEAK Reserved55_IRQHandler - PUBWEAK Reserved55_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved55_IRQHandler - LDR R0, =Reserved55_DriverIRQHandler - BX R0 - PUBWEAK Reserved56_IRQHandler - PUBWEAK Reserved56_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved56_IRQHandler - LDR R0, =Reserved56_DriverIRQHandler - BX R0 - PUBWEAK Reserved57_IRQHandler - PUBWEAK Reserved57_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved57_IRQHandler - LDR R0, =Reserved57_DriverIRQHandler - BX R0 - PUBWEAK Reserved58_IRQHandler - PUBWEAK Reserved58_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved58_IRQHandler - LDR R0, =Reserved58_DriverIRQHandler - BX R0 - PUBWEAK CAN0_IRQ0_IRQHandler - PUBWEAK CAN0_IRQ0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CAN0_IRQ0_IRQHandler - LDR R0, =CAN0_IRQ0_DriverIRQHandler - BX R0 - PUBWEAK CAN0_IRQ1_IRQHandler - PUBWEAK CAN0_IRQ1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CAN0_IRQ1_IRQHandler - LDR R0, =CAN0_IRQ1_DriverIRQHandler - BX R0 - PUBWEAK Reserved61_IRQHandler - PUBWEAK Reserved61_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved61_IRQHandler - LDR R0, =Reserved61_DriverIRQHandler - BX R0 - PUBWEAK USB1_PHY_IRQHandler - PUBWEAK USB1_PHY_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB1_PHY_IRQHandler - LDR R0, =USB1_PHY_DriverIRQHandler - BX R0 - PUBWEAK USB1_IRQHandler - PUBWEAK USB1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB1_IRQHandler - LDR R0, =USB1_DriverIRQHandler - BX R0 - PUBWEAK USB1_NEEDCLK_IRQHandler - PUBWEAK USB1_NEEDCLK_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB1_NEEDCLK_IRQHandler - LDR R0, =USB1_NEEDCLK_DriverIRQHandler - BX R0 - PUBWEAK SEC_HYPERVISOR_CALL_IRQHandler - PUBWEAK SEC_HYPERVISOR_CALL_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_HYPERVISOR_CALL_IRQHandler - LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler - BX R0 - PUBWEAK SEC_GPIO_INT0_IRQ0_IRQHandler - PUBWEAK SEC_GPIO_INT0_IRQ0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_GPIO_INT0_IRQ0_IRQHandler - LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler - BX R0 - PUBWEAK SEC_GPIO_INT0_IRQ1_IRQHandler - PUBWEAK SEC_GPIO_INT0_IRQ1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_GPIO_INT0_IRQ1_IRQHandler - LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler - BX R0 - PUBWEAK PLU_IRQHandler - PUBWEAK PLU_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PLU_IRQHandler - LDR R0, =PLU_DriverIRQHandler - BX R0 - PUBWEAK SEC_VIO_IRQHandler - PUBWEAK SEC_VIO_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_VIO_IRQHandler - LDR R0, =SEC_VIO_DriverIRQHandler - BX R0 - PUBWEAK HASHCRYPT_IRQHandler - PUBWEAK HASHCRYPT_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -HASHCRYPT_IRQHandler - LDR R0, =HASHCRYPT_DriverIRQHandler - BX R0 - PUBWEAK CASER_IRQHandler - PUBWEAK CASER_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CASER_IRQHandler - LDR R0, =CASER_DriverIRQHandler - BX R0 - PUBWEAK PUF_IRQHandler - PUBWEAK PUF_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PUF_IRQHandler - LDR R0, =PUF_DriverIRQHandler - BX R0 - PUBWEAK Reserved73_IRQHandler - PUBWEAK Reserved73_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved73_IRQHandler - LDR R0, =Reserved73_DriverIRQHandler - BX R0 - PUBWEAK DMA1_IRQHandler - PUBWEAK DMA1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA1_IRQHandler - LDR R0, =DMA1_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM8_IRQHandler - PUBWEAK FLEXCOMM8_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM8_IRQHandler - LDR R0, =FLEXCOMM8_DriverIRQHandler - BX R0 - PUBWEAK CDOG_IRQHandler - PUBWEAK CDOG_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CDOG_IRQHandler - LDR R0, =CDOG_DriverIRQHandler - BX R0 -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_DriverIRQHandler -Reserved39_DriverIRQHandler -ACMP_DriverIRQHandler -Reserved41_DriverIRQHandler -Reserved42_DriverIRQHandler -USB0_NEEDCLK_DriverIRQHandler -USB0_DriverIRQHandler -RTC_DriverIRQHandler -Reserved46_DriverIRQHandler -Reserved47_DriverIRQHandler -PIN_INT4_DriverIRQHandler -PIN_INT5_DriverIRQHandler -PIN_INT6_DriverIRQHandler -PIN_INT7_DriverIRQHandler -CTIMER2_DriverIRQHandler -CTIMER4_DriverIRQHandler -OS_EVENT_DriverIRQHandler -Reserved55_DriverIRQHandler -Reserved56_DriverIRQHandler -Reserved57_DriverIRQHandler -Reserved58_DriverIRQHandler -CAN0_IRQ0_DriverIRQHandler -CAN0_IRQ1_DriverIRQHandler -Reserved61_DriverIRQHandler -USB1_PHY_DriverIRQHandler -USB1_DriverIRQHandler -USB1_NEEDCLK_DriverIRQHandler -SEC_HYPERVISOR_CALL_DriverIRQHandler -SEC_GPIO_INT0_IRQ0_DriverIRQHandler -SEC_GPIO_INT0_IRQ1_DriverIRQHandler -PLU_DriverIRQHandler -SEC_VIO_DriverIRQHandler -HASHCRYPT_DriverIRQHandler -CASER_DriverIRQHandler -PUF_DriverIRQHandler -Reserved73_DriverIRQHandler -DMA1_DriverIRQHandler -FLEXCOMM8_DriverIRQHandler -CDOG_DriverIRQHandler -DefaultISR - B . - - END diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/system_LPC55S16.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/system_LPC55S16.c deleted file mode 100644 index f9e725a1409..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/system_LPC55S16.c +++ /dev/null @@ -1,392 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S16JBD100 -** LPC55S16JBD64 -** LPC55S16JEV98 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 -** Version: rev. 1.1, 2019-12-03 -** Build: b220117 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** - rev. 1.1 (2019-12-03) -** Initial version based on v0.6UM -** -** ################################################################### -*/ - -/*! - * @file LPC55S16 - * @version 1.1 - * @date 2019-12-03 - * @brief Device specific configuration file for LPC55S16 (implementation file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include -#include "fsl_device_registers.h" - -/* PLL0 SSCG control1 */ -#define PLL_SSCG_MD_FRACT_P 0U -#define PLL_SSCG_MD_INT_P 25U -#define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P) -#define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P) - -/* Get predivider (N) from PLL0 NDEC setting */ -static uint32_t findPll0PreDiv(void) -{ - uint32_t preDiv = 1UL; - - /* Direct input is not used? */ - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) - { - preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; - if (preDiv == 0UL) - { - preDiv = 1UL; - } - } - return preDiv; -} - -/* Get postdivider (P) from PLL0 PDEC setting */ -static uint32_t findPll0PostDiv(void) -{ - uint32_t postDiv = 1; - - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) - { - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) - { - postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; - } - else - { - postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); - } - if (postDiv == 0UL) - { - postDiv = 2UL; - } - } - return postDiv; -} - -/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ -static float findPll0MMult(void) -{ - float mMult = 1.0F; - float mMult_fract; - uint32_t mMult_int; - - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) - { - mMult = (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); - } - else - { - mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); - mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P); - mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M) / - (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); - mMult = (float)mMult_int + mMult_fract; - } - if (0ULL == ((uint64_t)mMult)) - { - mMult = 1.0F; - } - return mMult; -} - -/* Get predivider (N) from PLL1 NDEC setting */ -static uint32_t findPll1PreDiv(void) -{ - uint32_t preDiv = 1UL; - - /* Direct input is not used? */ - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) - { - preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; - if (preDiv == 0UL) - { - preDiv = 1UL; - } - } - return preDiv; -} - -/* Get postdivider (P) from PLL1 PDEC setting */ -static uint32_t findPll1PostDiv(void) -{ - uint32_t postDiv = 1UL; - - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0UL) - { - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) != 0UL) - { - postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK; - } - else - { - postDiv = 2UL * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK); - } - if (postDiv == 0UL) - { - postDiv = 2UL; - } - } - return postDiv; -} - -/* Get multiplier (M) from PLL1 MDEC settings */ -static uint32_t findPll1MMult(void) -{ - uint32_t mMult = 1UL; - - mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK; - - if (mMult == 0UL) - { - mMult = 1UL; - } - return mMult; -} - -/* Get FRO 12M Clk */ -/*! brief Return Frequency of FRO 12MHz - * return Frequency of FRO 12MHz - */ -static uint32_t GetFro12MFreq(void) -{ - return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; -} - -/* Get FRO 1M Clk */ -/*! brief Return Frequency of FRO 1MHz - * return Frequency of FRO 1MHz - */ -static uint32_t GetFro1MFreq(void) -{ - return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; -} - -/* Get EXT OSC Clk */ -/*! brief Return Frequency of External Clock - * return Frequency of External Clock. If no external clock is used returns 0. - */ -static uint32_t GetExtClkFreq(void) -{ - return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? CLK_CLK_IN : 0U; -} - -/* Get HF FRO Clk */ -/*! brief Return Frequency of High-Freq output of FRO - * return Frequency of High-Freq output of FRO - */ -static uint32_t GetFroHfFreq(void) -{ - return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; -} - -/* Get RTC OSC Clk */ -/*! brief Return Frequency of 32kHz osc - * return Frequency of 32kHz osc - */ -static uint32_t GetOsc32KFreq(void) -{ - return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? - CLK_RTC_32K_CLK : - ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && ((PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK) != 0UL)) ? - CLK_RTC_32K_CLK : - 0U; -} - - - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ - -__attribute__ ((weak)) void SystemInit (void) { -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ - #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ - - SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ - -#if defined(__MCUXPRESSO) - extern void(*const g_pfnVectors[]) (void); - SCB->VTOR = (uint32_t) &g_pfnVectors; -#else - extern void *__Vectors; - SCB->VTOR = (uint32_t) &__Vectors; -#endif - SYSCON->TRACECLKDIV = 0; -/* Optionally enable RAM banks that may be off by default at reset */ -#if !defined(DONT_ENABLE_DISABLED_RAMBANKS) - SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK; -#endif - /* Following code is to reset PUF to remove over consumption */ - /* Enable PUF register clock to access register */ - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_PUF_MASK; - /* Release PUF reset */ - SYSCON->PRESETCTRLCLR[2] = SYSCON_PRESETCTRL2_PUF_RST_MASK; - /* Enable PUF SRAM */ - PUF_SRAM_CTRL->CFG |= PUF_SRAM_CTRL_CFG_ENABLE_MASK | PUF_SRAM_CTRL_CFG_CKGATING_MASK; - /* Disable PUF register clock. */ - // Delaying the line of code below until the PUF State Machine execution is completed: - // Shutting down the clock to early will prevent the state machine from reaching the end. - // => Wait for status bit in PUF Controller Registers before stop PUF clock. - while ((PUF_SRAM_CTRL->INT_STATUS & PUF_SRAM_CTRL_INT_STATUS_READY_MASK) == 0UL) - { - } - SYSCON->AHBCLKCTRLCLR[2] = SYSCON_AHBCLKCTRL2_PUF_MASK; - SystemInitHook(); -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate (void) { - uint32_t clkRate = 0; - uint32_t prediv, postdiv; - uint64_t workRate; - uint64_t workRate1; - - switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) - { - case 0x00: /* MAINCLKSELA clock (main_clk_a)*/ - switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = GetFro12MFreq(); - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = GetExtClkFreq(); - break; - case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = GetFro1MFreq(); - break; - default: /* = 0x03 = FRO 96 MHz (fro_hf) */ - clkRate = GetFroHfFreq(); - break; - } - break; - case 0x01: /* PLL0 clock (pll0_clk)*/ - switch (SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = GetFro12MFreq(); - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = GetExtClkFreq(); - break; - case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = GetFro1MFreq(); - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = GetOsc32KFreq(); - break; - default: - clkRate = 0UL; - break; - } - if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) - { - prediv = findPll0PreDiv(); - postdiv = findPll0PostDiv(); - /* Adjust input clock */ - clkRate = clkRate / prediv; - /* MDEC used for rate */ - workRate = (uint64_t)clkRate * (uint64_t)findPll0MMult(); - clkRate = (uint32_t)(workRate / ((uint64_t)postdiv)); - } - break; - case 0x02: /* PLL1 clock (pll1_clk)*/ - switch (SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = GetFro12MFreq(); - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = GetExtClkFreq(); - break; - case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = GetFro1MFreq(); - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = GetOsc32KFreq(); - break; - default: - clkRate = 0UL; - break; - } - if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0UL)) - { - /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ - prediv = findPll1PreDiv(); - postdiv = findPll1PostDiv(); - /* Adjust input clock */ - clkRate = clkRate / prediv; - - /* MDEC used for rate */ - workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult(); - clkRate = (uint32_t)(workRate1 / ((uint64_t)postdiv)); - } - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = GetOsc32KFreq(); - break; - default: - clkRate = 0UL; - break; - } - SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL); -} - -/* ---------------------------------------------------------------------------- - -- SystemInitHook() - ---------------------------------------------------------------------------- */ - -__attribute__ ((weak)) void SystemInitHook (void) { - /* Void implementation of the weak function. */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/system_LPC55S16.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/system_LPC55S16.h deleted file mode 100644 index ecfd4b244af..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/LPC55S16/system_LPC55S16.h +++ /dev/null @@ -1,112 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S16JBD100 -** LPC55S16JBD64 -** LPC55S16JEV98 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 -** Version: rev. 1.1, 2019-12-03 -** Build: b220117 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** - rev. 1.1 (2019-12-03) -** Initial version based on v0.6UM -** -** ################################################################### -*/ - -/*! - * @file LPC55S16 - * @version 1.1 - * @date 2019-12-03 - * @brief Device specific configuration file for LPC55S16 (header file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef _SYSTEM_LPC55S16_H_ -#define _SYSTEM_LPC55S16_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ -#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ -#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ -#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ -#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ -#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ - - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -/** - * @brief SystemInit function hook. - * - * This weak function allows to call specific initialization code during the - * SystemInit() execution.This can be used when an application specific code needs - * to be called as close to the reset entry as possible (for example the Multicore - * Manager MCMGR_EarlyInit() function call). - * NOTE: No global r/w variables can be used in this hook function because the - * initialization of these variables happens after this function. - */ -void SystemInitHook (void); - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_LPC55S16_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/SConscript b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/SConscript deleted file mode 100644 index 3ec55349f1a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S16/SConscript +++ /dev/null @@ -1,51 +0,0 @@ -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -path = [cwd + '/../CMSIS/Core/Include',cwd + '/components/codec', cwd + '/LPC55S16', cwd + '/LPC55S16/drivers', cwd + '/middleware/sdmmc/inc', cwd + '/middleware/sdmmc/port'] -src = Split(''' - LPC55S16/system_LPC55S16.c - ''') - -if rtconfig.PLATFORM in ['gcc']: - src += ['LPC55S16/gcc/startup_LPC55S16.S'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - src += ['LPC55S16/arm/startup_LPC55S16.s'] -elif rtconfig.PLATFORM in ['iccarm']: - src += ['LPC55S16/iar/startup_LPC55S16.s'] - -src += ['LPC55S16/drivers/fsl_anactrl.c'] -src += ['LPC55S16/drivers/fsl_clock.c'] -src += ['LPC55S16/drivers/fsl_cmp.c'] -src += ['LPC55S16/drivers/fsl_common.c'] -src += ['LPC55S16/drivers/fsl_common_arm.c'] -src += ['LPC55S16/drivers/fsl_crc.c'] -src += ['LPC55S16/drivers/fsl_ctimer.c'] -src += ['LPC55S16/drivers/fsl_flexcomm.c'] -src += ['LPC55S16/drivers/fsl_dma.c'] -src += ['LPC55S16/drivers/fsl_gint.c'] -src += ['LPC55S16/drivers/fsl_gpio.c'] -src += ['LPC55S16/drivers/fsl_i2c.c'] -src += ['LPC55S16/drivers/fsl_i2c_dma.c'] -src += ['LPC55S16/drivers/fsl_i2s.c'] -src += ['LPC55S16/drivers/fsl_i2s_dma.c'] -src += ['LPC55S16/drivers/fsl_inputmux.c'] -src += ['LPC55S16/drivers/fsl_lpadc.c'] -src += ['LPC55S16/drivers/fsl_mrt.c'] -src += ['LPC55S16/drivers/fsl_ostimer.c'] -src += ['LPC55S16/drivers/fsl_pint.c'] -src += ['LPC55S16/drivers/fsl_power.c'] -src += ['LPC55S16/drivers/fsl_reset.c'] -src += ['LPC55S16/drivers/fsl_sctimer.c'] -src += ['LPC55S16/drivers/fsl_spi.c'] -src += ['LPC55S16/drivers/fsl_spi_dma.c'] -src += ['LPC55S16/drivers/fsl_sysctl.c'] -src += ['LPC55S16/drivers/fsl_usart.c'] -src += ['LPC55S16/drivers/fsl_usart_dma.c'] -src += ['LPC55S16/drivers/fsl_utick.c'] -src += ['LPC55S16/drivers/fsl_wwdt.c'] - - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) - -Return('group') diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/LPC55S28.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/LPC55S28.h deleted file mode 100644 index 6087aaaa15d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/LPC55S28.h +++ /dev/null @@ -1,30607 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S28JBD100 -** LPC55S28JBD64 -** LPC55S28JEV98 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b211009 -** -** Abstract: -** CMSIS Peripheral Access Layer for LPC55S28 -** -** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** - rev. 1.1 (2019-05-16) -** Initial A1 version based on v1.3UM -** -** ################################################################### -*/ - -/*! - * @file LPC55S28.h - * @version 1.1 - * @date 2019-05-16 - * @brief CMSIS Peripheral Access Layer for LPC55S28 - * - * CMSIS Peripheral Access Layer for LPC55S28 - */ - -#ifndef _LPC55S28_H_ -#define _LPC55S28_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0001U - - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 76 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Auxiliary constants */ - NotAvail_IRQn = -128, /**< Not available device specific interrupt */ - - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ - - /* Device specific interrupts */ - WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */ - DMA0_IRQn = 1, /**< DMA0 controller */ - GINT0_IRQn = 2, /**< GPIO group 0 */ - GINT1_IRQn = 3, /**< GPIO group 1 */ - PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ - PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ - PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ - PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ - UTICK0_IRQn = 8, /**< Micro-tick Timer */ - MRT0_IRQn = 9, /**< Multi-rate timer */ - CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ - CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ - SCT0_IRQn = 12, /**< SCTimer/PWM */ - CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ - FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - ADC0_IRQn = 22, /**< ADC0 */ - Reserved39_IRQn = 23, /**< Reserved interrupt */ - ACMP_IRQn = 24, /**< ACMP interrupts */ - Reserved41_IRQn = 25, /**< Reserved interrupt */ - Reserved42_IRQn = 26, /**< Reserved interrupt */ - USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ - USB0_IRQn = 28, /**< USB device */ - RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ - Reserved46_IRQn = 30, /**< Reserved interrupt */ - Reserved47_IRQn = 31, /**< Reserved interrupt */ - PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ - PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ - PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ - PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ - CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ - CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ - OS_EVENT_IRQn = 38, /**< OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ - Reserved55_IRQn = 39, /**< Reserved interrupt */ - Reserved56_IRQn = 40, /**< Reserved interrupt */ - Reserved57_IRQn = 41, /**< Reserved interrupt */ - SDIO_IRQn = 42, /**< SD/MMC */ - Reserved59_IRQn = 43, /**< Reserved interrupt */ - Reserved60_IRQn = 44, /**< Reserved interrupt */ - Reserved61_IRQn = 45, /**< Reserved interrupt */ - USB1_PHY_IRQn = 46, /**< USB1_PHY */ - USB1_IRQn = 47, /**< USB1 interrupt */ - USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ - SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */ - SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */ - SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */ - PLU_IRQn = 52, /**< PLU interrupt */ - SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */ - HASHCRYPT_IRQn = 54, /**< HASHCRYPT interrupt */ - CASER_IRQn = 55, /**< CASPER interrupt */ - PUF_IRQn = 56, /**< PUF interrupt */ - PQ_IRQn = 57, /**< PQ interrupt */ - DMA1_IRQn = 58, /**< DMA1 interrupt */ - FLEXCOMM8_IRQn = 59 /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M33 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration - * @{ - */ - -#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ -#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ -#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ -#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ - -#include "core_cm33.h" /* Core Peripheral Access Layer */ -#include "system_LPC55S28.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Mapping Information - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Mapping_Information Mapping Information - * @{ - */ - -/** Mapping Information */ -/*! - * @addtogroup dma_request - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief Structure for the DMA hardware request - * - * Defines the structure for the DMA hardware request collections. The user can configure the - * hardware request to trigger the DMA transfer accordingly. The index - * of the hardware request varies according to the to SoC. - */ -typedef enum _dma_request_source -{ - kDma0RequestHashCrypt = 0U, /**< HashCrypt */ - kDma1RequestHashCrypt = 0U, /**< HashCrypt */ - kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ - kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ - kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ - kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ - kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ - kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ - kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ - kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ - kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ - kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ - kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ - kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ - kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ - kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ - kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ - kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ - kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ - kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ - kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */ - kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */ - kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */ - kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */ - kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */ - kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */ - kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */ - kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */ - kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */ - kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */ - kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */ - kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */ - kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */ -} dma_request_source_t; - -/* @} */ - - -/*! - * @} - */ /* end of group Mapping_Information */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #else - #pragma push - #pragma anon_unions - #endif -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ - __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ - __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ - __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ - __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ - __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ - uint8_t RESERVED_1[12]; - __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ - __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ - uint8_t RESERVED_2[4]; - __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ - uint8_t RESERVED_3[92]; - __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ - __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ - uint8_t RESERVED_4[8]; - __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ - __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ - struct { /* offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ - } CMD[15]; - uint8_t RESERVED_5[136]; - __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_6[240]; - __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ - uint8_t RESERVED_7[248]; - __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ - uint8_t RESERVED_8[124]; - __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */ - uint8_t RESERVED_9[2680]; - __IO uint32_t TST; /**< ADC Test Register, offset: 0xFFC */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ - -#define ADC_VERID_RES_MASK (0x1U) -#define ADC_VERID_RES_SHIFT (0U) -/*! RES - Resolution - * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. - * 0b1..Up to 16-bit differential/16-bit single ended resolution supported. - */ -#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) - -#define ADC_VERID_DIFFEN_MASK (0x2U) -#define ADC_VERID_DIFFEN_SHIFT (1U) -/*! DIFFEN - Differential Supported - * 0b0..Differential operation not supported. - * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented. - */ -#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) - -#define ADC_VERID_MVI_MASK (0x8U) -#define ADC_VERID_MVI_SHIFT (3U) -/*! MVI - Multi Vref Implemented - * 0b0..Single voltage reference high (VREFH) input supported. - * 0b1..Multiple voltage reference high (VREFH) inputs supported. - */ -#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) - -#define ADC_VERID_CSW_MASK (0x70U) -#define ADC_VERID_CSW_SHIFT (4U) -/*! CSW - Channel Scale Width - * 0b000..Channel scaling not supported. - * 0b001..Channel scaling supported. 1-bit CSCALE control field. - * 0b110..Channel scaling supported. 6-bit CSCALE control field. - */ -#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) - -#define ADC_VERID_VR1RNGI_MASK (0x100U) -#define ADC_VERID_VR1RNGI_SHIFT (8U) -/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented - * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. - * 0b1..Range control required. CFG[VREF1RNG] is implemented. - */ -#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) - -#define ADC_VERID_IADCKI_MASK (0x200U) -#define ADC_VERID_IADCKI_SHIFT (9U) -/*! IADCKI - Internal ADC Clock implemented - * 0b0..Internal clock source not implemented. - * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. - */ -#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) - -#define ADC_VERID_CALOFSI_MASK (0x400U) -#define ADC_VERID_CALOFSI_SHIFT (10U) -/*! CALOFSI - Calibration Function Implemented - * 0b0..Calibration Not Implemented. - * 0b1..Calibration Implemented. - */ -#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) - -#define ADC_VERID_NUM_SEC_MASK (0x800U) -#define ADC_VERID_NUM_SEC_SHIFT (11U) -/*! NUM_SEC - Number of Single Ended Outputs Supported - * 0b0..This design supports one single ended conversion at a time. - * 0b1..This design supports two simultanious single ended conversions. - */ -#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) - -#define ADC_VERID_NUM_FIFO_MASK (0x7000U) -#define ADC_VERID_NUM_FIFO_SHIFT (12U) -/*! NUM_FIFO - Number of FIFOs - * 0b000..N/A - * 0b001..This design supports one result FIFO. - * 0b010..This design supports two result FIFOs. - * 0b011..This design supports three result FIFOs. - * 0b100..This design supports four result FIFOs. - */ -#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) - -#define ADC_VERID_MINOR_MASK (0xFF0000U) -#define ADC_VERID_MINOR_SHIFT (16U) -/*! MINOR - Minor Version Number - */ -#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) - -#define ADC_VERID_MAJOR_MASK (0xFF000000U) -#define ADC_VERID_MAJOR_SHIFT (24U) -/*! MAJOR - Major Version Number - */ -#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ - -#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) -#define ADC_PARAM_TRIG_NUM_SHIFT (0U) -/*! TRIG_NUM - Trigger Number - */ -#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) - -#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) -#define ADC_PARAM_FIFOSIZE_SHIFT (8U) -/*! FIFOSIZE - Result FIFO Depth - * 0b00000001..Result FIFO depth = 1 dataword. - * 0b00000100..Result FIFO depth = 4 datawords. - * 0b00001000..Result FIFO depth = 8 datawords. - * 0b00010000..Result FIFO depth = 16 datawords. - * 0b00100000..Result FIFO depth = 32 datawords. - * 0b01000000..Result FIFO depth = 64 datawords. - */ -#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) - -#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) -#define ADC_PARAM_CV_NUM_SHIFT (16U) -/*! CV_NUM - Compare Value Number - */ -#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) - -#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) -#define ADC_PARAM_CMD_NUM_SHIFT (24U) -/*! CMD_NUM - Command Buffer Number - */ -#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) -/*! @} */ - -/*! @name CTRL - ADC Control Register */ -/*! @{ */ - -#define ADC_CTRL_ADCEN_MASK (0x1U) -#define ADC_CTRL_ADCEN_SHIFT (0U) -/*! ADCEN - ADC Enable - * 0b0..ADC is disabled. - * 0b1..ADC is enabled. - */ -#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) - -#define ADC_CTRL_RST_MASK (0x2U) -#define ADC_CTRL_RST_SHIFT (1U) -/*! RST - Software Reset - * 0b0..ADC logic is not reset. - * 0b1..ADC logic is reset. - */ -#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) - -#define ADC_CTRL_DOZEN_MASK (0x4U) -#define ADC_CTRL_DOZEN_SHIFT (2U) -/*! DOZEN - Doze Enable - * 0b0..ADC is enabled in Doze mode. - * 0b1..ADC is disabled in Doze mode. - */ -#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) - -#define ADC_CTRL_CAL_REQ_MASK (0x8U) -#define ADC_CTRL_CAL_REQ_SHIFT (3U) -/*! CAL_REQ - Auto-Calibration Request - * 0b0..No request for auto-calibration has been made. - * 0b1..A request for auto-calibration has been made - */ -#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) - -#define ADC_CTRL_CALOFS_MASK (0x10U) -#define ADC_CTRL_CALOFS_SHIFT (4U) -/*! CALOFS - Configure for offset calibration function - * 0b0..Calibration function disabled - * 0b1..Request for offset calibration function - */ -#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) - -#define ADC_CTRL_RSTFIFO0_MASK (0x100U) -#define ADC_CTRL_RSTFIFO0_SHIFT (8U) -/*! RSTFIFO0 - Reset FIFO 0 - * 0b0..No effect. - * 0b1..FIFO 0 is reset. - */ -#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) - -#define ADC_CTRL_RSTFIFO1_MASK (0x200U) -#define ADC_CTRL_RSTFIFO1_SHIFT (9U) -/*! RSTFIFO1 - Reset FIFO 1 - * 0b0..No effect. - * 0b1..FIFO 1 is reset. - */ -#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) - -#define ADC_CTRL_CAL_AVGS_MASK (0x70000U) -#define ADC_CTRL_CAL_AVGS_SHIFT (16U) -/*! CAL_AVGS - Auto-Calibration Averages - * 0b000..Single conversion. - * 0b001..2 conversions averaged. - * 0b010..4 conversions averaged. - * 0b011..8 conversions averaged. - * 0b100..16 conversions averaged. - * 0b101..32 conversions averaged. - * 0b110..64 conversions averaged. - * 0b111..128 conversions averaged. - */ -#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) -/*! @} */ - -/*! @name STAT - ADC Status Register */ -/*! @{ */ - -#define ADC_STAT_RDY0_MASK (0x1U) -#define ADC_STAT_RDY0_SHIFT (0U) -/*! RDY0 - Result FIFO 0 Ready Flag - * 0b0..Result FIFO 0 data level not above watermark level. - * 0b1..Result FIFO 0 holding data above watermark level. - */ -#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) - -#define ADC_STAT_FOF0_MASK (0x2U) -#define ADC_STAT_FOF0_SHIFT (1U) -/*! FOF0 - Result FIFO 0 Overflow Flag - * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) - -#define ADC_STAT_RDY1_MASK (0x4U) -#define ADC_STAT_RDY1_SHIFT (2U) -/*! RDY1 - Result FIFO1 Ready Flag - * 0b0..Result FIFO1 data level not above watermark level. - * 0b1..Result FIFO1 holding data above watermark level. - */ -#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) - -#define ADC_STAT_FOF1_MASK (0x8U) -#define ADC_STAT_FOF1_SHIFT (3U) -/*! FOF1 - Result FIFO1 Overflow Flag - * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) - -#define ADC_STAT_TEXC_INT_MASK (0x100U) -#define ADC_STAT_TEXC_INT_SHIFT (8U) -/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception - * 0b0..No trigger exceptions have occurred. - * 0b1..A trigger exception has occurred and is pending acknowledgement. - */ -#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) - -#define ADC_STAT_TCOMP_INT_MASK (0x200U) -#define ADC_STAT_TCOMP_INT_SHIFT (9U) -/*! TCOMP_INT - Interrupt Flag For Trigger Completion - * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. - * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. - */ -#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) - -#define ADC_STAT_CAL_RDY_MASK (0x400U) -#define ADC_STAT_CAL_RDY_SHIFT (10U) -/*! CAL_RDY - Calibration Ready - * 0b0..Calibration is incomplete or hasn't been ran. - * 0b1..The ADC is calibrated. - */ -#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) - -#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) -#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) -/*! ADC_ACTIVE - ADC Active - * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. - * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. - */ -#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) - -#define ADC_STAT_TRGACT_MASK (0xF0000U) -#define ADC_STAT_TRGACT_SHIFT (16U) -/*! TRGACT - Trigger Active - * 0b0000..Command (sequence) associated with Trigger 0 currently being executed. - * 0b0001..Command (sequence) associated with Trigger 1 currently being executed. - * 0b0010..Command (sequence) associated with Trigger 2 currently being executed. - * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed. - */ -#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) - -#define ADC_STAT_CMDACT_MASK (0xF000000U) -#define ADC_STAT_CMDACT_SHIFT (24U) -/*! CMDACT - Command Active - * 0b0000..No command is currently in progress. - * 0b0001..Command 1 currently being executed. - * 0b0010..Command 2 currently being executed. - * 0b0011-0b1111..Associated command number is currently being executed. - */ -#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) -/*! @} */ - -/*! @name IE - Interrupt Enable Register */ -/*! @{ */ - -#define ADC_IE_FWMIE0_MASK (0x1U) -#define ADC_IE_FWMIE0_SHIFT (0U) -/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable - * 0b0..FIFO 0 watermark interrupts are not enabled. - * 0b1..FIFO 0 watermark interrupts are enabled. - */ -#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) - -#define ADC_IE_FOFIE0_MASK (0x2U) -#define ADC_IE_FOFIE0_SHIFT (1U) -/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable - * 0b0..FIFO 0 overflow interrupts are not enabled. - * 0b1..FIFO 0 overflow interrupts are enabled. - */ -#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) - -#define ADC_IE_FWMIE1_MASK (0x4U) -#define ADC_IE_FWMIE1_SHIFT (2U) -/*! FWMIE1 - FIFO1 Watermark Interrupt Enable - * 0b0..FIFO1 watermark interrupts are not enabled. - * 0b1..FIFO1 watermark interrupts are enabled. - */ -#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) - -#define ADC_IE_FOFIE1_MASK (0x8U) -#define ADC_IE_FOFIE1_SHIFT (3U) -/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable - * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) - -#define ADC_IE_TEXC_IE_MASK (0x100U) -#define ADC_IE_TEXC_IE_SHIFT (8U) -/*! TEXC_IE - Trigger Exception Interrupt Enable - * 0b0..Trigger exception interrupts are disabled. - * 0b1..Trigger exception interrupts are enabled. - */ -#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) - -#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U) -#define ADC_IE_TCOMP_IE_SHIFT (16U) -/*! TCOMP_IE - Trigger Completion Interrupt Enable - * 0b0000000000000000..Trigger completion interrupts are disabled. - * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only. - * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only. - * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled. - * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source. - */ -#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) -/*! @} */ - -/*! @name DE - DMA Enable Register */ -/*! @{ */ - -#define ADC_DE_FWMDE0_MASK (0x1U) -#define ADC_DE_FWMDE0_SHIFT (0U) -/*! FWMDE0 - FIFO 0 Watermark DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) - -#define ADC_DE_FWMDE1_MASK (0x2U) -#define ADC_DE_FWMDE1_SHIFT (1U) -/*! FWMDE1 - FIFO1 Watermark DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) -/*! @} */ - -/*! @name CFG - ADC Configuration Register */ -/*! @{ */ - -#define ADC_CFG_TPRICTRL_MASK (0x3U) -#define ADC_CFG_TPRICTRL_SHIFT (0U) -/*! TPRICTRL - ADC trigger priority control - * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted - * and the new command specified by the trigger is started. - * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after - * after completing the current conversion. If averaging is enabled, the averaging loop will be completed. - * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. - * 0b10..If a higher priority trigger is received during command processing, the current command will be - * completed (averaging, looping, compare) before servicing the higher priority trigger. - * 0b11..RESERVED - */ -#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) - -#define ADC_CFG_PWRSEL_MASK (0x30U) -#define ADC_CFG_PWRSEL_SHIFT (4U) -/*! PWRSEL - Power Configuration Select - * 0b00..Lowest power setting. - * 0b01..Higher power setting than 0b0. - * 0b10..Higher power setting than 0b1. - * 0b11..Highest power setting. - */ -#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) - -#define ADC_CFG_REFSEL_MASK (0xC0U) -#define ADC_CFG_REFSEL_SHIFT (6U) -/*! REFSEL - Voltage Reference Selection - * 0b00..(Default) Option 1 setting. - * 0b01..Option 2 setting. - * 0b10..Option 3 setting. - * 0b11..Reserved - */ -#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) - -#define ADC_CFG_TRES_MASK (0x100U) -#define ADC_CFG_TRES_SHIFT (8U) -/*! TRES - Trigger Resume Enable - * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. - * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. - */ -#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) - -#define ADC_CFG_TCMDRES_MASK (0x200U) -#define ADC_CFG_TCMDRES_SHIFT (9U) -/*! TCMDRES - Trigger Command Resume - * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. - * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. - */ -#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) - -#define ADC_CFG_HPT_EXDI_MASK (0x400U) -#define ADC_CFG_HPT_EXDI_SHIFT (10U) -/*! HPT_EXDI - High Priority Trigger Exception Disable - * 0b0..High priority trigger exceptions are enabled. - * 0b1..High priority trigger exceptions are disabled. - */ -#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) - -#define ADC_CFG_PUDLY_MASK (0xFF0000U) -#define ADC_CFG_PUDLY_SHIFT (16U) -/*! PUDLY - Power Up Delay - */ -#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) - -#define ADC_CFG_PWREN_MASK (0x10000000U) -#define ADC_CFG_PWREN_SHIFT (28U) -/*! PWREN - ADC Analog Pre-Enable - * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. - * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost - * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN - * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. - * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be - * executed. - */ -#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) -/*! @} */ - -/*! @name PAUSE - ADC Pause Register */ -/*! @{ */ - -#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) -#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) -/*! PAUSEDLY - Pause Delay - */ -#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) - -#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) -#define ADC_PAUSE_PAUSEEN_SHIFT (31U) -/*! PAUSEEN - PAUSE Option Enable - * 0b0..Pause operation disabled - * 0b1..Pause operation enabled - */ -#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) -/*! @} */ - -/*! @name SWTRIG - Software Trigger Register */ -/*! @{ */ - -#define ADC_SWTRIG_SWT0_MASK (0x1U) -#define ADC_SWTRIG_SWT0_SHIFT (0U) -/*! SWT0 - Software trigger 0 event - * 0b0..No trigger 0 event generated. - * 0b1..Trigger 0 event generated. - */ -#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) - -#define ADC_SWTRIG_SWT1_MASK (0x2U) -#define ADC_SWTRIG_SWT1_SHIFT (1U) -/*! SWT1 - Software trigger 1 event - * 0b0..No trigger 1 event generated. - * 0b1..Trigger 1 event generated. - */ -#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) - -#define ADC_SWTRIG_SWT2_MASK (0x4U) -#define ADC_SWTRIG_SWT2_SHIFT (2U) -/*! SWT2 - Software trigger 2 event - * 0b0..No trigger 2 event generated. - * 0b1..Trigger 2 event generated. - */ -#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) - -#define ADC_SWTRIG_SWT3_MASK (0x8U) -#define ADC_SWTRIG_SWT3_SHIFT (3U) -/*! SWT3 - Software trigger 3 event - * 0b0..No trigger 3 event generated. - * 0b1..Trigger 3 event generated. - */ -#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) - -#define ADC_SWTRIG_SWT4_MASK (0x10U) -#define ADC_SWTRIG_SWT4_SHIFT (4U) -/*! SWT4 - Software trigger 4 event - * 0b0..No trigger 4 event generated. - * 0b1..Trigger 4 event generated. - */ -#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) - -#define ADC_SWTRIG_SWT5_MASK (0x20U) -#define ADC_SWTRIG_SWT5_SHIFT (5U) -/*! SWT5 - Software trigger 5 event - * 0b0..No trigger 5 event generated. - * 0b1..Trigger 5 event generated. - */ -#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) - -#define ADC_SWTRIG_SWT6_MASK (0x40U) -#define ADC_SWTRIG_SWT6_SHIFT (6U) -/*! SWT6 - Software trigger 6 event - * 0b0..No trigger 6 event generated. - * 0b1..Trigger 6 event generated. - */ -#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) - -#define ADC_SWTRIG_SWT7_MASK (0x80U) -#define ADC_SWTRIG_SWT7_SHIFT (7U) -/*! SWT7 - Software trigger 7 event - * 0b0..No trigger 7 event generated. - * 0b1..Trigger 7 event generated. - */ -#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) - -#define ADC_SWTRIG_SWT8_MASK (0x100U) -#define ADC_SWTRIG_SWT8_SHIFT (8U) -/*! SWT8 - Software trigger 8 event - * 0b0..No trigger 8 event generated. - * 0b1..Trigger 8 event generated. - */ -#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK) - -#define ADC_SWTRIG_SWT9_MASK (0x200U) -#define ADC_SWTRIG_SWT9_SHIFT (9U) -/*! SWT9 - Software trigger 9 event - * 0b0..No trigger 9 event generated. - * 0b1..Trigger 9 event generated. - */ -#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK) - -#define ADC_SWTRIG_SWT10_MASK (0x400U) -#define ADC_SWTRIG_SWT10_SHIFT (10U) -/*! SWT10 - Software trigger 10 event - * 0b0..No trigger 10 event generated. - * 0b1..Trigger 10 event generated. - */ -#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK) - -#define ADC_SWTRIG_SWT11_MASK (0x800U) -#define ADC_SWTRIG_SWT11_SHIFT (11U) -/*! SWT11 - Software trigger 11 event - * 0b0..No trigger 11 event generated. - * 0b1..Trigger 11 event generated. - */ -#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK) - -#define ADC_SWTRIG_SWT12_MASK (0x1000U) -#define ADC_SWTRIG_SWT12_SHIFT (12U) -/*! SWT12 - Software trigger 12 event - * 0b0..No trigger 12 event generated. - * 0b1..Trigger 12 event generated. - */ -#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK) - -#define ADC_SWTRIG_SWT13_MASK (0x2000U) -#define ADC_SWTRIG_SWT13_SHIFT (13U) -/*! SWT13 - Software trigger 13 event - * 0b0..No trigger 13 event generated. - * 0b1..Trigger 13 event generated. - */ -#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK) - -#define ADC_SWTRIG_SWT14_MASK (0x4000U) -#define ADC_SWTRIG_SWT14_SHIFT (14U) -/*! SWT14 - Software trigger 14 event - * 0b0..No trigger 14 event generated. - * 0b1..Trigger 14 event generated. - */ -#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK) - -#define ADC_SWTRIG_SWT15_MASK (0x8000U) -#define ADC_SWTRIG_SWT15_SHIFT (15U) -/*! SWT15 - Software trigger 15 event - * 0b0..No trigger 15 event generated. - * 0b1..Trigger 15 event generated. - */ -#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK) -/*! @} */ - -/*! @name TSTAT - Trigger Status Register */ -/*! @{ */ - -#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU) -#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) -/*! TEXC_NUM - Trigger Exception Number - * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. - * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception. - * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception. - * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception. - * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception. - */ -#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) - -#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U) -#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) -/*! TCOMP_FLAG - Trigger Completion Flag - * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled. - * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts. - * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts. - * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts. - * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. - */ -#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) -/*! @} */ - -/*! @name OFSTRIM - ADC Offset Trim Register */ -/*! @{ */ - -#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) -#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) -/*! OFSTRIM_A - Trim for offset - */ -#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) - -#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) -#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) -/*! OFSTRIM_B - Trim for offset - */ -#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) -/*! @} */ - -/*! @name TCTRL - Trigger Control Register */ -/*! @{ */ - -#define ADC_TCTRL_HTEN_MASK (0x1U) -#define ADC_TCTRL_HTEN_SHIFT (0U) -/*! HTEN - Trigger enable - * 0b0..Hardware trigger source disabled - * 0b1..Hardware trigger source enabled - */ -#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) - -#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) -#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) -/*! FIFO_SEL_A - SAR Result Destination For Channel A - * 0b0..Result written to FIFO 0 - * 0b1..Result written to FIFO 1 - */ -#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) - -#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) -#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) -/*! FIFO_SEL_B - SAR Result Destination For Channel B - * 0b0..Result written to FIFO 0 - * 0b1..Result written to FIFO 1 - */ -#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) - -#define ADC_TCTRL_TPRI_MASK (0xF00U) -#define ADC_TCTRL_TPRI_SHIFT (8U) -/*! TPRI - Trigger priority setting - * 0b0000..Set to highest priority, Level 1 - * 0b0001-0b1110..Set to corresponding priority level - * 0b1111..Set to lowest priority, Level 16 - */ -#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) - -#define ADC_TCTRL_RSYNC_MASK (0x8000U) -#define ADC_TCTRL_RSYNC_SHIFT (15U) -/*! RSYNC - Trigger Resync - */ -#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) - -#define ADC_TCTRL_TDLY_MASK (0xF0000U) -#define ADC_TCTRL_TDLY_SHIFT (16U) -/*! TDLY - Trigger delay select - */ -#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) - -#define ADC_TCTRL_TCMD_MASK (0xF000000U) -#define ADC_TCTRL_TCMD_SHIFT (24U) -/*! TCMD - Trigger command select - * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. - * 0b0001..CMD1 is executed - * 0b0010-0b1110..Corresponding CMD is executed - * 0b1111..CMD15 is executed - */ -#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) -/*! @} */ - -/* The count of ADC_TCTRL */ -#define ADC_TCTRL_COUNT (16U) - -/*! @name FCTRL - FIFO Control Register */ -/*! @{ */ - -#define ADC_FCTRL_FCOUNT_MASK (0x1FU) -#define ADC_FCTRL_FCOUNT_SHIFT (0U) -/*! FCOUNT - Result FIFO counter - */ -#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) - -#define ADC_FCTRL_FWMARK_MASK (0xF0000U) -#define ADC_FCTRL_FWMARK_SHIFT (16U) -/*! FWMARK - Watermark level selection - */ -#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) -/*! @} */ - -/* The count of ADC_FCTRL */ -#define ADC_FCTRL_COUNT (2U) - -/*! @name GCC - Gain Calibration Control */ -/*! @{ */ - -#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) -#define ADC_GCC_GAIN_CAL_SHIFT (0U) -/*! GAIN_CAL - Gain Calibration Value - */ -#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) - -#define ADC_GCC_RDY_MASK (0x1000000U) -#define ADC_GCC_RDY_SHIFT (24U) -/*! RDY - Gain Calibration Value Valid - * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. - * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. - */ -#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) -/*! @} */ - -/* The count of ADC_GCC */ -#define ADC_GCC_COUNT (2U) - -/*! @name GCR - Gain Calculation Result */ -/*! @{ */ - -#define ADC_GCR_GCALR_MASK (0xFFFFU) -#define ADC_GCR_GCALR_SHIFT (0U) -/*! GCALR - Gain Calculation Result - */ -#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) - -#define ADC_GCR_RDY_MASK (0x1000000U) -#define ADC_GCR_RDY_SHIFT (24U) -/*! RDY - Gain Calculation Ready - * 0b0..The gain offset calculation value is invalid. - * 0b1..The gain calibration value is valid. - */ -#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) -/*! @} */ - -/* The count of ADC_GCR */ -#define ADC_GCR_COUNT (2U) - -/*! @name CMDL - ADC Command Low Buffer Register */ -/*! @{ */ - -#define ADC_CMDL_ADCH_MASK (0x1FU) -#define ADC_CMDL_ADCH_SHIFT (0U) -/*! ADCH - Input channel select - * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. - * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. - * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. - * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. - * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. - * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. - */ -#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) - -#define ADC_CMDL_CTYPE_MASK (0x60U) -#define ADC_CMDL_CTYPE_SHIFT (5U) -/*! CTYPE - Conversion Type - * 0b00..Single-Ended Mode. Only A side channel is converted. - * 0b01..Single-Ended Mode. Only B side channel is converted. - * 0b10..Differential Mode. A-B. - * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - */ -#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) - -#define ADC_CMDL_MODE_MASK (0x80U) -#define ADC_CMDL_MODE_SHIFT (7U) -/*! MODE - Select resolution of conversions - * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - */ -#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) -/*! @} */ - -/* The count of ADC_CMDL */ -#define ADC_CMDL_COUNT (15U) - -/*! @name CMDH - ADC Command High Buffer Register */ -/*! @{ */ - -#define ADC_CMDH_CMPEN_MASK (0x3U) -#define ADC_CMDH_CMPEN_SHIFT (0U) -/*! CMPEN - Compare Function Enable - * 0b00..Compare disabled. - * 0b01..Reserved - * 0b10..Compare enabled. Store on true. - * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - */ -#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) - -#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) -#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) -/*! WAIT_TRIG - Wait for trigger assertion before execution. - * 0b0..This command will be automatically executed. - * 0b1..The active trigger must be asserted again before executing this command. - */ -#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) - -#define ADC_CMDH_LWI_MASK (0x80U) -#define ADC_CMDH_LWI_SHIFT (7U) -/*! LWI - Loop with Increment - * 0b0..Auto channel increment disabled - * 0b1..Auto channel increment enabled - */ -#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) - -#define ADC_CMDH_STS_MASK (0x700U) -#define ADC_CMDH_STS_SHIFT (8U) -/*! STS - Sample Time Select - * 0b000..Minimum sample time of 3 ADCK cycles. - * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - */ -#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) - -#define ADC_CMDH_AVGS_MASK (0x7000U) -#define ADC_CMDH_AVGS_SHIFT (12U) -/*! AVGS - Hardware Average Select - * 0b000..Single conversion. - * 0b001..2 conversions averaged. - * 0b010..4 conversions averaged. - * 0b011..8 conversions averaged. - * 0b100..16 conversions averaged. - * 0b101..32 conversions averaged. - * 0b110..64 conversions averaged. - * 0b111..128 conversions averaged. - */ -#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) - -#define ADC_CMDH_LOOP_MASK (0xF0000U) -#define ADC_CMDH_LOOP_SHIFT (16U) -/*! LOOP - Loop Count Select - * 0b0000..Looping not enabled. Command executes 1 time. - * 0b0001..Loop 1 time. Command executes 2 times. - * 0b0010..Loop 2 times. Command executes 3 times. - * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. - * 0b1111..Loop 15 times. Command executes 16 times. - */ -#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) - -#define ADC_CMDH_NEXT_MASK (0xF000000U) -#define ADC_CMDH_NEXT_SHIFT (24U) -/*! NEXT - Next Command Select - * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority - * trigger pending, begin command associated with lower priority trigger. - * 0b0001..Select CMD1 command buffer register as next command. - * 0b0010-0b1110..Select corresponding CMD command buffer register as next command - * 0b1111..Select CMD15 command buffer register as next command. - */ -#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) -/*! @} */ - -/* The count of ADC_CMDH */ -#define ADC_CMDH_COUNT (15U) - -/*! @name CV - Compare Value Register */ -/*! @{ */ - -#define ADC_CV_CVL_MASK (0xFFFFU) -#define ADC_CV_CVL_SHIFT (0U) -/*! CVL - Compare Value Low. - */ -#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) - -#define ADC_CV_CVH_MASK (0xFFFF0000U) -#define ADC_CV_CVH_SHIFT (16U) -/*! CVH - Compare Value High. - */ -#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) -/*! @} */ - -/* The count of ADC_CV */ -#define ADC_CV_COUNT (4U) - -/*! @name RESFIFO - ADC Data Result FIFO Register */ -/*! @{ */ - -#define ADC_RESFIFO_D_MASK (0xFFFFU) -#define ADC_RESFIFO_D_SHIFT (0U) -/*! D - Data result - */ -#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) - -#define ADC_RESFIFO_TSRC_MASK (0xF0000U) -#define ADC_RESFIFO_TSRC_SHIFT (16U) -/*! TSRC - Trigger Source - * 0b0000..Trigger source 0 initiated this conversion. - * 0b0001..Trigger source 1 initiated this conversion. - * 0b0010-0b1110..Corresponding trigger source initiated this conversion. - * 0b1111..Trigger source 15 initiated this conversion. - */ -#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) - -#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) -#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) -/*! LOOPCNT - Loop count value - * 0b0000..Result is from initial conversion in command. - * 0b0001..Result is from second conversion in command. - * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. - * 0b1111..Result is from 16th conversion in command. - */ -#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) - -#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) -#define ADC_RESFIFO_CMDSRC_SHIFT (24U) -/*! CMDSRC - Command Buffer Source - * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state - * prior to an ADC conversion result dataword being stored to a RESFIFO buffer. - * 0b0001..CMD1 buffer used as control settings for this conversion. - * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. - * 0b1111..CMD15 buffer used as control settings for this conversion. - */ -#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) - -#define ADC_RESFIFO_VALID_MASK (0x80000000U) -#define ADC_RESFIFO_VALID_SHIFT (31U) -/*! VALID - FIFO entry is valid - * 0b0..FIFO is empty. Discard any read from RESFIFO. - * 0b1..FIFO record read from RESFIFO is valid. - */ -#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) -/*! @} */ - -/* The count of ADC_RESFIFO */ -#define ADC_RESFIFO_COUNT (2U) - -/*! @name CAL_GAR - Calibration General A-Side Registers */ -/*! @{ */ - -#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) -#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) -/*! CAL_GAR_VAL - Calibration General A Side Register Element - */ -#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) -/*! @} */ - -/* The count of ADC_CAL_GAR */ -#define ADC_CAL_GAR_COUNT (33U) - -/*! @name CAL_GBR - Calibration General B-Side Registers */ -/*! @{ */ - -#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) -#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) -/*! CAL_GBR_VAL - Calibration General B Side Register Element - */ -#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) -/*! @} */ - -/* The count of ADC_CAL_GBR */ -#define ADC_CAL_GBR_COUNT (33U) - -/*! @name TST - ADC Test Register */ -/*! @{ */ - -#define ADC_TST_CST_LONG_MASK (0x1U) -#define ADC_TST_CST_LONG_SHIFT (0U) -/*! CST_LONG - Calibration Sample Time Long - * 0b0..Normal sample time. Minimum sample time of 3 ADCK cycles. - * 0b1..Increased sample time. 67 ADCK cycles total sample time. - */ -#define ADC_TST_CST_LONG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_CST_LONG_SHIFT)) & ADC_TST_CST_LONG_MASK) - -#define ADC_TST_FOFFM_MASK (0x100U) -#define ADC_TST_FOFFM_SHIFT (8U) -/*! FOFFM - Force M-side positive offset - * 0b0..Normal operation. No forced offset. - * 0b1..Test configuration. Forced positive offset on MDAC. - */ -#define ADC_TST_FOFFM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK) - -#define ADC_TST_FOFFP_MASK (0x200U) -#define ADC_TST_FOFFP_SHIFT (9U) -/*! FOFFP - Force P-side positive offset - * 0b0..Normal operation. No forced offset. - * 0b1..Test configuration. Forced positive offset on PDAC. - */ -#define ADC_TST_FOFFP(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK) - -#define ADC_TST_FOFFM2_MASK (0x400U) -#define ADC_TST_FOFFM2_SHIFT (10U) -/*! FOFFM2 - Force M-side negative offset - * 0b0..Normal operation. No forced offset. - * 0b1..Test configuration. Forced negative offset on MDAC. - */ -#define ADC_TST_FOFFM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM2_SHIFT)) & ADC_TST_FOFFM2_MASK) - -#define ADC_TST_FOFFP2_MASK (0x800U) -#define ADC_TST_FOFFP2_SHIFT (11U) -/*! FOFFP2 - Force P-side negative offset - * 0b0..Normal operation. No forced offset. - * 0b1..Test configuration. Forced negative offset on PDAC. - */ -#define ADC_TST_FOFFP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP2_SHIFT)) & ADC_TST_FOFFP2_MASK) - -#define ADC_TST_TESTEN_MASK (0x800000U) -#define ADC_TST_TESTEN_SHIFT (23U) -/*! TESTEN - Enable test configuration - * 0b0..Normal operation. Test configuration not enabled. - * 0b1..Hardware BIST Test in progress. - */ -#define ADC_TST_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_TESTEN_SHIFT)) & ADC_TST_TESTEN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ADC_Register_Masks */ - - -/* ADC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral ADC0 base address */ - #define ADC0_BASE (0x500A0000u) - /** Peripheral ADC0 base address */ - #define ADC0_BASE_NS (0x400A0000u) - /** Peripheral ADC0 base pointer */ - #define ADC0 ((ADC_Type *)ADC0_BASE) - /** Peripheral ADC0 base pointer */ - #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS { ADC0_BASE } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS { ADC0 } - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS_NS { ADC0_NS } -#else - /** Peripheral ADC0 base address */ - #define ADC0_BASE (0x400A0000u) - /** Peripheral ADC0 base pointer */ - #define ADC0 ((ADC_Type *)ADC0_BASE) - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS { ADC0_BASE } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS { ADC0 } -#endif -/** Interrupt vectors for the ADC peripheral type */ -#define ADC_IRQS { ADC0_IRQn } - -/*! - * @} - */ /* end of group ADC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- AHB_SECURE_CTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer - * @{ - */ - -/** AHB_SECURE_CTRL - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x30 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */ - uint8_t RESERVED_0[12]; - __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[3]; /**< Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */ - uint8_t RESERVED_1[4]; - __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */ - } SEC_CTRL_FLASH_ROM[1]; - struct { /* offset: 0x30, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAMX slaves., array offset: 0x40, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_RAMX[1]; - uint8_t RESERVED_0[12]; - struct { /* offset: 0x50, array step: 0x18 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x18 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM0 slaves., array offset: 0x60, array step: index*0x18, index2*0x4 */ - } SEC_CTRL_RAM0[1]; - uint8_t RESERVED_1[8]; - struct { /* offset: 0x70, array step: 0x18 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x18 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM1 slaves., array offset: 0x80, array step: index*0x18, index2*0x4 */ - } SEC_CTRL_RAM1[1]; - uint8_t RESERVED_2[8]; - struct { /* offset: 0x90, array step: 0x18 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x18 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step: index*0x18, index2*0x4 */ - } SEC_CTRL_RAM2[1]; - uint8_t RESERVED_3[8]; - struct { /* offset: 0xB0, array step: 0x18 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM3 slaves., array offset: 0xB0, array step: 0x18 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM3 slaves., array offset: 0xC0, array step: index*0x18, index2*0x4 */ - } SEC_CTRL_RAM3[1]; - uint8_t RESERVED_4[8]; - struct { /* offset: 0xD0, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM4 slaves., array offset: 0xD0, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM4 slaves., array offset: 0xE0, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_RAM4[1]; - uint8_t RESERVED_5[12]; - struct { /* offset: 0xF0, array step: 0x30 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for both APB Bridges slaves., array offset: 0xF0, array step: 0x30 */ - uint8_t RESERVED_0[12]; - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x100, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x104, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x108, array step: 0x30 */ - uint8_t RESERVED_1[4]; - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x110, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x114, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x118, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x11C, array step: 0x30 */ - } SEC_CTRL_APB_BRIDGE[1]; - __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */ - __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */ - uint8_t RESERVED_6[8]; - __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */ - __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */ - uint8_t RESERVED_7[8]; - struct { /* offset: 0x140, array step: 0x14 */ - __IO uint32_t SLAVE0_RULE; /**< Security access rules for AHB peripherals., array offset: 0x140, array step: 0x14 */ - __IO uint32_t SLAVE1_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */ - uint8_t RESERVED_0[8]; - __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x150, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_AHB_PORT10[1]; - uint8_t RESERVED_8[12]; - struct { /* offset: 0x160, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0x160, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM_USB_HS., array offset: 0x170, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_USB_HS[1]; - uint8_t RESERVED_9[3212]; - __I uint32_t SEC_VIO_ADDR[12]; /**< most recent security violation address for AHB port n, array offset: 0xE00, array step: 0x4 */ - uint8_t RESERVED_10[80]; - __I uint32_t SEC_VIO_MISC_INFO[12]; /**< most recent security violation miscellaneous information for AHB port n, array offset: 0xE80, array step: 0x4 */ - uint8_t RESERVED_11[80]; - __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */ - uint8_t RESERVED_12[124]; - __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */ - __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */ - uint8_t RESERVED_13[8]; - __IO uint32_t SEC_CPU_INT_MASK0; /**< Secure Interrupt mask for CPU1, offset: 0xF90 */ - __IO uint32_t SEC_CPU_INT_MASK1; /**< Secure Interrupt mask for CPU1, offset: 0xF94 */ - uint8_t RESERVED_14[36]; - __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */ - uint8_t RESERVED_15[16]; - __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */ - __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */ - uint8_t RESERVED_16[20]; - __IO uint32_t CPU0_LOCK_REG; /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */ - __IO uint32_t CPU1_LOCK_REG; /**< Miscalleneous control signals for in micro-Cortex M33 (CPU1), offset: 0xFF0 */ - uint8_t RESERVED_17[4]; - __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */ - __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */ -} AHB_SECURE_CTRL_Type; - -/* ---------------------------------------------------------------------------- - -- AHB_SECURE_CTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks - * @{ - */ - -/*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U) -/*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U) -/*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U) - -/*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U) - -/*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U) -/*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAMX_MEM_RULE - Security access rules for RAMX slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U) -/*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM0_MEM_RULE - Security access rules for RAM0 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT2 (2U) - -/*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT (0U) -/*! RAM1_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM1_MEM_RULE - Security access rules for RAM1 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT2 (2U) - -/*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U) -/*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM2_MEM_RULE - Security access rules for RAM2 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT2 (2U) - -/*! @name SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT (0U) -/*! RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM3_MEM_RULE - Security access rules for RAM3 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT2 (2U) - -/*! @name SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT (0U) -/*! RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM4_MEM_RULE - Security access rules for RAM4 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U) -/*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U) -/*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U) -/*! SYSCON_RULE - System Configuration - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U) -/*! IOCON_RULE - I/O Configuration - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U) -/*! GINT0_RULE - GPIO input Interrupt 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U) -/*! GINT1_RULE - GPIO input Interrupt 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U) -/*! PINT_RULE - Pin Interrupt and Pattern match - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U) -/*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT (24U) -/*! INPUTMUX_RULE - Peripheral input multiplexing - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U) -/*! CTIMER0_RULE - Standard counter/Timer 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U) -/*! CTIMER1_RULE - Standard counter/Timer 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U) -/*! WWDT_RULE - Windiwed wtachdog Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U) -/*! MRT_RULE - Multi-rate Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U) -/*! UTICK_RULE - Micro-Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U) -/*! ANACTRL_RULE - Analog Modules controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U) -/*! PMC_RULE - Power Management Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U) -/*! SYSCTRL_RULE - System Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U) -/*! CTIMER2_RULE - Standard counter/Timer 2 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U) -/*! CTIMER3_RULE - Standard counter/Timer 3 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U) -/*! CTIMER4_RULE - Standard counter/Timer 4 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U) -/*! RTC_RULE - Real Time Counter - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U) -/*! OSEVENT_RULE - OS Event Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U) -/*! FLASH_CTRL_RULE - Flash Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U) -/*! PRINCE_RULE - Prince - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U) -/*! USBHPHY_RULE - USB High Speed Phy controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U) -/*! RNG_RULE - True Random Number Generator - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT (12U) -/*! PUF_RULE - PUF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U) -/*! PLU_RULE - Programmable Look-Up logic - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U) - -/*! @name SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT (8U) -/*! DMA0_RULE - DMA Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT (16U) -/*! FS_USB_DEV_RULE - USB Full-speed device - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT (20U) -/*! SCT_RULE - SCTimer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT (24U) -/*! FLEXCOMM0_RULE - Flexcomm interface 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT (28U) -/*! FLEXCOMM1_RULE - Flexcomm interface 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT (0U) -/*! FLEXCOMM2_RULE - Flexcomm interface 2 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT (4U) -/*! FLEXCOMM3_RULE - Flexcomm interface 3 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT (8U) -/*! FLEXCOMM4_RULE - Flexcomm interface 4 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT (12U) -/*! MAILBOX_RULE - Inter CPU communication Mailbox - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT (16U) -/*! GPIO0_RULE - High Speed GPIO - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT (16U) -/*! USB_HS_DEV_RULE - USB high Speed device registers - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT (20U) -/*! CRC_RULE - CRC engine - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT (24U) -/*! FLEXCOMM5_RULE - Flexcomm interface 5 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT (28U) -/*! FLEXCOMM6_RULE - Flexcomm interface 6 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT (0U) -/*! FLEXCOMM7_RULE - Flexcomm interface 7 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT (12U) -/*! SDIO_RULE - SDMMC card interface - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT (16U) -/*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT (28U) -/*! HS_LSPI_RULE - High Speed SPI - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB_PORT10_SLAVE0_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT (0U) -/*! ADC_RULE - ADC - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT (8U) -/*! USB_FS_HOST_RULE - USB Full Speed Host registers. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT (12U) -/*! USB_HS_HOST_RULE - USB High speed host registers - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT (16U) -/*! HASH_RULE - SHA-2 crypto registers - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT (20U) -/*! CASPER_RULE - RSA/ECC crypto accelerator - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT (24U) -/*! PQ_RULE - Power Quad (CPU0 processor hardware accelerator) - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT (28U) -/*! DMA1_RULE - DMA Controller (Secure) - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_COUNT (1U) - -/*! @name SEC_CTRL_AHB_PORT10_SLAVE1_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT (0U) -/*! GPIO1_RULE - Secure High Speed GPIO - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U) -/*! AHB_SEC_CTRL_RULE - AHB Secure Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_COUNT (1U) - -/*! @name SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U) -/*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U) -/*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U) -/*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U) -/*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U) -/*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U) -/*! SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U) -/*! SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U) -/*! SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U) -/*! SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_VIO_ADDR - most recent security violation address for AHB port n */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) -/*! SEC_VIO_ADDR - security violation address for AHB port - */ -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */ -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (12U) - -/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB port n */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) -/*! SEC_VIO_INFO_WRITE - security violation access read/write indicator. - * 0b0..Read access. - * 0b1..Write access. - */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) -/*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator. - * 0b0..Code access. - * 0b1..Data access. - */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) -/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level - */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) -/*! SEC_VIO_INFO_MASTER - security violation master number - * 0b0000..CPU0 Code. - * 0b0001..CPU0 System. - * 0b0010..CPU1 Data. - * 0b0011..CPU1 System. - * 0b0100..USB-HS Device. - * 0b0101..SDMA0. - * 0b1000..SDIO. - * 0b1001..PowerQuad. - * 0b1010..HASH. - * 0b1011..USB-FS Host. - * 0b1100..SDMA1. - */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (12U) - -/*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) -/*! VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) -/*! VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) -/*! VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) -/*! VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) -/*! VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) -/*! VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) -/*! VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) -/*! VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) -/*! VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) -/*! VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U) -/*! VIO_INFO_VALID10 - violation information valid flag for AHB port 10. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U) -/*! VIO_INFO_VALID11 - violation information valid flag for AHB port 11. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK) -/*! @} */ - -/*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U) -/*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U) -/*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U) -/*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U) -/*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U) -/*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U) -/*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U) -/*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U) -/*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U) -/*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U) -/*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U) -/*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U) -/*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U) -/*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U) -/*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U) -/*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U) -/*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U) -/*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U) -/*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U) -/*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U) -/*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U) -/*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U) -/*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U) -/*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U) -/*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U) -/*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U) -/*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U) -/*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U) -/*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U) -/*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U) -/*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U) -/*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U) -/*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK) -/*! @} */ - -/*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U) -/*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U) -/*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U) -/*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U) -/*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U) -/*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U) -/*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U) -/*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U) -/*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U) -/*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U) -/*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U) -/*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U) -/*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U) -/*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U) -/*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U) -/*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U) -/*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U) -/*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U) -/*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U) -/*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U) -/*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U) -/*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U) -/*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U) -/*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U) -/*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U) -/*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U) -/*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U) -/*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U) -/*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U) -/*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U) -/*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U) -/*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U) -/*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK) -/*! @} */ - -/*! @name SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT (0U) -/*! SYS_IRQ - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT (1U) -/*! SDMA0_IRQ - System DMA 0 (non-secure) interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT (2U) -/*! GPIO_GLOBALINT0_IRQ - GPIO Group 0 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT (3U) -/*! GPIO_GLOBALINT1_IRQ - GPIO Group 1 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT (4U) -/*! GPIO_INT0_IRQ0 - Pin interrupt 0 or pattern match engine slice 0 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT (5U) -/*! GPIO_INT0_IRQ1 - Pin interrupt 1 or pattern match engine slice 1 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT (6U) -/*! GPIO_INT0_IRQ2 - Pin interrupt 2 or pattern match engine slice 2 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT (7U) -/*! GPIO_INT0_IRQ3 - Pin interrupt 3 or pattern match engine slice 3 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT (8U) -/*! UTICK_IRQ - Micro Tick Timer interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT (9U) -/*! MRT_IRQ - Multi-Rate Timer interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT (10U) -/*! CTIMER0_IRQ - Standard counter/timer 0 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT (11U) -/*! CTIMER1_IRQ - Standard counter/timer 1 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT (12U) -/*! SCT_IRQ - SCTimer/PWM interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT (13U) -/*! CTIMER3_IRQ - Standard counter/timer 3 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT (14U) -/*! FLEXCOMM0_IRQ - Flexcomm 0 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT (15U) -/*! FLEXCOMM1_IRQ - Flexcomm 1 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT (16U) -/*! FLEXCOMM2_IRQ - Flexcomm 2 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT (17U) -/*! FLEXCOMM3_IRQ - Flexcomm 3 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT (18U) -/*! FLEXCOMM4_IRQ - Flexcomm 4 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT (19U) -/*! FLEXCOMM5_IRQ - Flexcomm 5 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT (20U) -/*! FLEXCOMM6_IRQ - Flexcomm 6 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT (21U) -/*! FLEXCOMM7_IRQ - Flexcomm 7 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT (22U) -/*! ADC_IRQ - General Purpose ADC interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT (23U) -/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT (24U) -/*! ACMP_IRQ - Analog Comparator interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT (25U) -/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT (26U) -/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT (27U) -/*! USB0_NEEDCLK - USB Full Speed Controller Clock request interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT (28U) -/*! USB0_IRQ - USB Full Speed Controller interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT (29U) -/*! RTC_IRQ - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT (30U) -/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT (31U) -/*! MAILBOX_IRQ - Mailbox interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK) -/*! @} */ - -/*! @name SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT (0U) -/*! GPIO_INT0_IRQ4 - Pin interrupt 4 or pattern match engine slice 4 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT (1U) -/*! GPIO_INT0_IRQ5 - Pin interrupt 5 or pattern match engine slice 5 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT (2U) -/*! GPIO_INT0_IRQ6 - Pin interrupt 6 or pattern match engine slice 6 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT (3U) -/*! GPIO_INT0_IRQ7 - Pin interrupt 7 or pattern match engine slice 7 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT (4U) -/*! CTIMER2_IRQ - Standard counter/timer 2 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT (5U) -/*! CTIMER4_IRQ - Standard counter/timer 4 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT (6U) -/*! OS_EVENT_TIMER_IRQ - OS Event Timer and OS Event Timer Wakeup interrupts - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT (7U) -/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT (8U) -/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT (9U) -/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT (10U) -/*! SDIO_IRQ - SDIO Controller interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT (11U) -/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT (12U) -/*! RESERVED4 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT (13U) -/*! RESERVED5 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT (14U) -/*! USB1_PHY_IRQ - USB High Speed PHY Controller interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT (15U) -/*! USB1_IRQ - USB High Speed Controller interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT (16U) -/*! USB1_NEEDCLK - USB High Speed Controller Clock request interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT (17U) -/*! SEC_HYPERVISOR_CALL_IRQ - Secure fault Hyper Visor call interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT (18U) -/*! SEC_GPIO_INT0_IRQ0 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT (19U) -/*! SEC_GPIO_INT0_IRQ1 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT (20U) -/*! PLU_IRQ - Programmable Look-Up Controller interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT (21U) -/*! SEC_VIO_IRQ - Security Violation interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT (22U) -/*! SHA_IRQ - HASH-AES interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT (23U) -/*! CASPER_IRQ - CASPER interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT (24U) -/*! PUFKEY_IRQ - PUF interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT (25U) -/*! PQ_IRQ - Power Quad interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT (26U) -/*! SDMA1_IRQ - System DMA 1 (Secure) interrupt - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT (27U) -/*! LSPI_HS_IRQ - High Speed SPI interrupt - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK) -/*! @} */ - -/*! @name SEC_MASK_LOCK - Security General Purpose register access control. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) -/*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK) - -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) -/*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK) - -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (8U) -/*! SEC_CPU1_INT_MASK0_LOCK - SEC_CPU_INT_MASK0 register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK) - -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC00U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (10U) -/*! SEC_CPU1_INT_MASK1_LOCK - SEC_CPU_INT_MASK1 register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK) -/*! @} */ - -/*! @name MASTER_SEC_LEVEL - master secure level register */ -/*! @{ */ - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK (0x30U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT (4U) -/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK (0xC0U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT (6U) -/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U) -/*! USBFSD - USB Full Speed Device. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U) -/*! SDMA0 - System DMA 0. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK (0x30000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT (16U) -/*! SDIO - SDIO. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK (0xC0000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT (18U) -/*! PQ - Power Quad. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U) -/*! HASH - Hash. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U) -/*! USBFSH - USB Full speed Host. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U) -/*! SDMA1 - System DMA 1 security level. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) -/*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) -/*! @} */ - -/*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */ -/*! @{ */ - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK (0x30U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT (4U) -/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK (0xC0U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT (6U) -/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U) -/*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U) -/*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK (0x30000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT (16U) -/*! SDIO - SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0xC0000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (18U) -/*! PQ - Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U) -/*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U) -/*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U) -/*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) -/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) -/*! @} */ - -/*! @name CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) */ -/*! @{ */ - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) -/*! LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) -/*! LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) -/*! LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U) -/*! LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U) -/*! LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT (30U) -/*! CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK) -/*! @} */ - -/*! @name CPU1_LOCK_REG - Miscalleneous control signals for in micro-Cortex M33 (CPU1) */ -/*! @{ */ - -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) -/*! LOCK_NS_VTOR - micro-Cortex M33 (CPU1) VTOR_NS register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK) - -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) -/*! LOCK_NS_MPU - micro-Cortex M33 (CPU1) non-secure MPU register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK) - -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT (30U) -/*! CPU1_LOCK_REG_LOCK - CPU1_LOCK_REG write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK) -/*! @} */ - -/*! @name MISC_CTRL_DP_REG - secure control duplicate register */ -/*! @{ */ - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) -/*! WRITE_LOCK - Write lock. - * 0b10..Secure control registers can be written. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) -/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. - * 0b10..Disable check. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) -/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. - * 0b10..Disable check. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) -/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. - * 0b10..Disable check. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) -/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. - * 0b10..Enable abort fort secure checker. - * 0b01..Disable abort fort secure checker. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) -/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. - * 0b10..Simple master in strict mode. - * 0b01..Simple master in tier mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) -/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. - * 0b10..Smart master in strict mode. - * 0b01..Smart master in tier mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) -/*! IDAU_ALL_NS - Disable IDAU. - * 0b10..IDAU is enabled. - * 0b01..IDAU is disable. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) -/*! @} */ - -/*! @name MISC_CTRL_REG - secure control register */ -/*! @{ */ - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) -/*! WRITE_LOCK - Write lock. - * 0b10..Secure control registers can be written. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) -/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. - * 0b10..Disable check. - * 0b01..Enabled (restricted mode) - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) -/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. - * 0b10..Disable check. - * 0b01..Enabled (restricted mode) - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) -/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. - * 0b10..Disable check. - * 0b01..Enabled (restricted mode) - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) -/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. - * 0b10..Enable abort fort secure checker. - * 0b01..Disable abort fort secure checker. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) -/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. - * 0b10..Simple master in strict mode. - * 0b01..Simple master in tier mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) -/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. - * 0b10..Smart master in strict mode. - * 0b01..Smart master in tier mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) -/*! IDAU_ALL_NS - Disable IDAU. - * 0b10..IDAU is enabled. - * 0b01..IDAU is disable. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group AHB_SECURE_CTRL_Register_Masks */ - - -/* AHB_SECURE_CTRL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral AHB_SECURE_CTRL base address */ - #define AHB_SECURE_CTRL_BASE (0x500AC000u) - /** Peripheral AHB_SECURE_CTRL base address */ - #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u) - /** Peripheral AHB_SECURE_CTRL base pointer */ - #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) - /** Peripheral AHB_SECURE_CTRL base pointer */ - #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS) - /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ - #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } - /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ - #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } - /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ - #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS } - /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ - #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS } -#else - /** Peripheral AHB_SECURE_CTRL base address */ - #define AHB_SECURE_CTRL_BASE (0x400AC000u) - /** Peripheral AHB_SECURE_CTRL base pointer */ - #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) - /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ - #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } - /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ - #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } -#endif - -/*! - * @} - */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ANACTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer - * @{ - */ - -/** ANACTRL - Register Layout Typedef */ -typedef struct { - __IO uint32_t ANALOG_CTRL_CFG; /**< Various Analog blocks configuration (like FRO 192MHz trimmings source ...), offset: 0x0 */ - __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */ - __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */ - __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */ - __IO uint32_t ADC_CTRL; /**< General Purpose ADC VBAT Divider branch control, offset: 0x18 */ - uint8_t RESERVED_1[4]; - __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */ - __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status register, offset: 0x24 */ - uint8_t RESERVED_2[8]; - __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */ - __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */ - uint8_t RESERVED_3[8]; - __IO uint32_t RINGO0_CTRL; /**< First Ring Oscillator module control register., offset: 0x40 */ - __IO uint32_t RINGO1_CTRL; /**< Second Ring Oscillator module control register., offset: 0x44 */ - __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */ - uint8_t RESERVED_4[100]; - __IO uint32_t LDO_XO32M; /**< High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register, offset: 0xB0 */ - __IO uint32_t AUX_BIAS; /**< AUX_BIAS, offset: 0xB4 */ - uint8_t RESERVED_5[72]; - __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */ - __IO uint32_t USBHS_PHY_TRIM; /**< USB High Speed Phy Trim values, offset: 0x104 */ -} ANACTRL_Type; - -/* ---------------------------------------------------------------------------- - -- ANACTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks - * @{ - */ - -/*! @name ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) */ -/*! @{ */ - -#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK (0x1U) -#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT (0U) -/*! FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source. - * 0b0..FRO192M trimming and 'Enable' comes from eFUSE. - * 0b1..FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers. - */ -#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT)) & ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK) -/*! @} */ - -/*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */ -/*! @{ */ - -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U) -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U) -/*! FLASH_PWRDWN - Flash Power Down status. - * 0b0..Flash is not in power down mode. - * 0b1..Flash is in power down mode. - */ -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK) - -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U) -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U) -/*! FLASH_INIT_ERROR - Flash initialization error status. - * 0b0..No error. - * 0b1..At least one error occured during flash initialization.. - */ -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK) -/*! @} */ - -/*! @name FREQ_ME_CTRL - Frequency Measure function control register */ -/*! @{ */ - -#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU) -#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U) -/*! CAPVAL_SCALE - Frequency measure result /Frequency measur scale - */ -#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK) - -#define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U) -#define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U) -/*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit - * when the measurement cycle has completed and there is valid capture data in the CAPVAL field - * (bits 30:0). - */ -#define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK) -/*! @} */ - -/*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */ -/*! @{ */ - -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U) -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U) -/*! ENA_12MHZCLK - 12 MHz clock control. - * 0b0..12 MHz clock is disabled. - * 0b1..12 MHz clock is enabled. - */ -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) - -#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK (0x8000U) -#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT (15U) -/*! ENA_48MHZCLK - 48 MHz clock control. - * 0b0..Reserved. - * 0b1..48 MHz clock is enabled. - */ -#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK) - -#define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U) -#define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U) -/*! DAC_TRIM - Frequency trim. - */ -#define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK) - -#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U) -#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U) -/*! USBCLKADJ - If this bit is set and the USB peripheral is enabled into full speed device mode, - * the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF - * packets. - */ -#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK) - -#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U) -#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U) -/*! USBMODCHG - If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0. - */ -#define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK) - -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U) -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U) -/*! ENA_96MHZCLK - 96 MHz clock control. - * 0b0..96 MHz clock is disabled. - * 0b1..96 MHz clock is enabled. - */ -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) - -#define ANACTRL_FRO192M_CTRL_WRTRIM_MASK (0x80000000U) -#define ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT (31U) -/*! WRTRIM - This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields. - */ -#define ANACTRL_FRO192M_CTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_WRTRIM_MASK) -/*! @} */ - -/*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */ -/*! @{ */ - -#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U) -#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U) -/*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. - * 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). - * 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by - * FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). - */ -#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK) - -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U) -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U) -/*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses - * the threshold voltage of a SLVT transistor, this output signal will go high. It is also - * possible to observe the clk_valid signal. - */ -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK) -/*! @} */ - -/*! @name ADC_CTRL - General Purpose ADC VBAT Divider branch control */ -/*! @{ */ - -#define ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK (0x1U) -#define ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT (0U) -/*! VBATDIVENABLE - Switch On/Off VBAT divider branch. - * 0b0..VBAT divider branch is disabled. - * 0b1..VBAT divider branch is enabled. - */ -#define ANACTRL_ADC_CTRL_VBATDIVENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT)) & ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK) -/*! @} */ - -/*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */ -/*! @{ */ - -#define ANACTRL_XO32M_CTRL_SLAVE_MASK (0x10U) -#define ANACTRL_XO32M_CTRL_SLAVE_SHIFT (4U) -/*! SLAVE - Xo in slave mode. - */ -#define ANACTRL_XO32M_CTRL_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_SLAVE_SHIFT)) & ANACTRL_XO32M_CTRL_SLAVE_MASK) - -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK (0x7F00U) -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT (8U) -/*! OSC_CAP_IN - Tune capa banks of High speed Crystal Oscillator input pin - */ -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK) - -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK (0x3F8000U) -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT (15U) -/*! OSC_CAP_OUT - Tune capa banks of High speed Crystal Oscillator output pin - */ -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK) - -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U) -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U) -/*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. - * 0b0..XO AC buffer bypass is disabled. - * 0b1..XO AC buffer bypass is enabled. - */ -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK) - -#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U) -#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U) -/*! ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL. - * 0b0..High speed Crystal oscillator output to USB HS PLL is disabled. - * 0b1..High speed Crystal oscillator output to USB HS PLL is enabled. - */ -#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) - -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U) -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U) -/*! ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system. - * 0b0..High speed Crystal oscillator output to CPU system is disabled. - * 0b1..High speed Crystal oscillator output to CPU system is enabled. - */ -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) -/*! @} */ - -/*! @name XO32M_STATUS - High speed Crystal Oscillator Status register */ -/*! @{ */ - -#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U) -#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U) -/*! XO_READY - Indicates XO out frequency statibilty. - * 0b0..XO output frequency is not yet stable. - * 0b1..XO output frequency is stable. - */ -#define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK) -/*! @} */ - -/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */ -/*! @{ */ - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U) -/*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control. - * 0b0..BOD VBAT interrupt is disabled. - * 0b1..BOD VBAT interrupt is enabled. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U) -/*! BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U) -/*! BODCORE_INT_ENABLE - BOD CORE interrupt control. - * 0b0..BOD CORE interrupt is disabled. - * 0b1..BOD CORE interrupt is enabled. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U) -/*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U) -/*! DCDC_INT_ENABLE - DCDC interrupt control. - * 0b0..DCDC interrupt is disabled. - * 0b1..DCDC interrupt is enabled. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U) -/*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK) -/*! @} */ - -/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */ -/*! @{ */ - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U) -/*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U) -/*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U) -/*! BODVBAT_VAL - Current value of BOD VBAT power status output. - * 0b0..VBAT voltage level is below the threshold. - * 0b1..VBAT voltage level is above the threshold. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U) -/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U) -/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U) -/*! BODCORE_VAL - Current value of BOD CORE power status output. - * 0b0..CORE voltage level is below the threshold. - * 0b1..CORE voltage level is above the threshold. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U) -/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U) -/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U) -/*! DCDC_VAL - Current value of DCDC power status output. - * 0b0..DCDC output Voltage is below the targeted regulation level. - * 0b1..DCDC output Voltage is above the targeted regulation level. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK) -/*! @} */ - -/*! @name RINGO0_CTRL - First Ring Oscillator module control register. */ -/*! @{ */ - -#define ANACTRL_RINGO0_CTRL_SL_MASK (0x1U) -#define ANACTRL_RINGO0_CTRL_SL_SHIFT (0U) -/*! SL - Select short or long ringo (for all ringos types). - * 0b0..Select short ringo (few elements). - * 0b1..Select long ringo (many elements). - */ -#define ANACTRL_RINGO0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK) - -#define ANACTRL_RINGO0_CTRL_FS_MASK (0x2U) -#define ANACTRL_RINGO0_CTRL_FS_SHIFT (1U) -/*! FS - Ringo frequency output divider. - * 0b0..High frequency output (frequency lower than 100 MHz). - * 0b1..Low frequency output (frequency lower than 10 MHz). - */ -#define ANACTRL_RINGO0_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK) - -#define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK (0xCU) -#define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT (2U) -/*! SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control. - * 0b00..Normal mode. - * 0b01..P-Monitor mode. Measure with weak P transistor. - * 0b10..P-Monitor mode. Measure with weak N transistor. - * 0b11..Don't use. - */ -#define ANACTRL_RINGO0_CTRL_SWN_SWP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK) - -#define ANACTRL_RINGO0_CTRL_PD_MASK (0x10U) -#define ANACTRL_RINGO0_CTRL_PD_SHIFT (4U) -/*! PD - Ringo module Power control. - * 0b0..The Ringo module is enabled. - * 0b1..The Ringo module is disabled. - */ -#define ANACTRL_RINGO0_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK) - -#define ANACTRL_RINGO0_CTRL_E_ND0_MASK (0x20U) -#define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT (5U) -/*! E_ND0 - First NAND2-based ringo control. - * 0b0..First NAND2-based ringo is disabled. - * 0b1..First NAND2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_ND0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK) - -#define ANACTRL_RINGO0_CTRL_E_ND1_MASK (0x40U) -#define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT (6U) -/*! E_ND1 - Second NAND2-based ringo control. - * 0b0..Second NAND2-based ringo is disabled. - * 0b1..Second NAND2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_ND1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK) - -#define ANACTRL_RINGO0_CTRL_E_NR0_MASK (0x80U) -#define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT (7U) -/*! E_NR0 - First NOR2-based ringo control. - * 0b0..First NOR2-based ringo is disabled. - * 0b1..First NOR2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_NR0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK) - -#define ANACTRL_RINGO0_CTRL_E_NR1_MASK (0x100U) -#define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT (8U) -/*! E_NR1 - Second NOR2-based ringo control. - * 0b0..Second NORD2-based ringo is disabled. - * 0b1..Second NORD2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_NR1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK) - -#define ANACTRL_RINGO0_CTRL_E_IV0_MASK (0x200U) -#define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT (9U) -/*! E_IV0 - First Inverter-based ringo control. - * 0b0..First INV-based ringo is disabled. - * 0b1..First INV-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_IV0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK) - -#define ANACTRL_RINGO0_CTRL_E_IV1_MASK (0x400U) -#define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT (10U) -/*! E_IV1 - Second Inverter-based ringo control. - * 0b0..Second INV-based ringo is disabled. - * 0b1..Second INV-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_IV1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK) - -#define ANACTRL_RINGO0_CTRL_E_PN0_MASK (0x800U) -#define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT (11U) -/*! E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control. - * 0b0..First PN-based ringo is disabled. - * 0b1..First PN-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_PN0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK) - -#define ANACTRL_RINGO0_CTRL_E_PN1_MASK (0x1000U) -#define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT (12U) -/*! E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control. - * 0b0..Second PN-based ringo is disabled. - * 0b1..Second PN-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_PN1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK) - -#define ANACTRL_RINGO0_CTRL_DIVISOR_MASK (0xF0000U) -#define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT (16U) -/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) - */ -#define ANACTRL_RINGO0_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK) - -#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) -#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT (31U) -/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider - * value, cleared when the change is complete. - */ -#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK) -/*! @} */ - -/*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */ -/*! @{ */ - -#define ANACTRL_RINGO1_CTRL_S_MASK (0x1U) -#define ANACTRL_RINGO1_CTRL_S_SHIFT (0U) -/*! S - Select short or long ringo (for all ringos types). - * 0b0..Select short ringo (few elements). - * 0b1..Select long ringo (many elements). - */ -#define ANACTRL_RINGO1_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK) - -#define ANACTRL_RINGO1_CTRL_FS_MASK (0x2U) -#define ANACTRL_RINGO1_CTRL_FS_SHIFT (1U) -/*! FS - Ringo frequency output divider. - * 0b0..High frequency output (frequency lower than 100 MHz). - * 0b1..Low frequency output (frequency lower than 10 MHz). - */ -#define ANACTRL_RINGO1_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK) - -#define ANACTRL_RINGO1_CTRL_PD_MASK (0x4U) -#define ANACTRL_RINGO1_CTRL_PD_SHIFT (2U) -/*! PD - Ringo module Power control. - * 0b0..The Ringo module is enabled. - * 0b1..The Ringo module is disabled. - */ -#define ANACTRL_RINGO1_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK) - -#define ANACTRL_RINGO1_CTRL_E_R24_MASK (0x8U) -#define ANACTRL_RINGO1_CTRL_E_R24_SHIFT (3U) -/*! E_R24 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK) - -#define ANACTRL_RINGO1_CTRL_E_R35_MASK (0x10U) -#define ANACTRL_RINGO1_CTRL_E_R35_SHIFT (4U) -/*! E_R35 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK) - -#define ANACTRL_RINGO1_CTRL_E_M2_MASK (0x20U) -#define ANACTRL_RINGO1_CTRL_E_M2_SHIFT (5U) -/*! E_M2 - Metal 2 (M2) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK) - -#define ANACTRL_RINGO1_CTRL_E_M3_MASK (0x40U) -#define ANACTRL_RINGO1_CTRL_E_M3_SHIFT (6U) -/*! E_M3 - Metal 3 (M3) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK) - -#define ANACTRL_RINGO1_CTRL_E_M4_MASK (0x80U) -#define ANACTRL_RINGO1_CTRL_E_M4_SHIFT (7U) -/*! E_M4 - Metal 4 (M4) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK) - -#define ANACTRL_RINGO1_CTRL_E_M5_MASK (0x100U) -#define ANACTRL_RINGO1_CTRL_E_M5_SHIFT (8U) -/*! E_M5 - Metal 5 (M5) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK) - -#define ANACTRL_RINGO1_CTRL_DIVISOR_MASK (0xF0000U) -#define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT (16U) -/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) - */ -#define ANACTRL_RINGO1_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK) - -#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) -#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT (31U) -/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider - * value, cleared when the change is complete. - */ -#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK) -/*! @} */ - -/*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */ -/*! @{ */ - -#define ANACTRL_RINGO2_CTRL_S_MASK (0x1U) -#define ANACTRL_RINGO2_CTRL_S_SHIFT (0U) -/*! S - Select short or long ringo (for all ringos types). - * 0b0..Select short ringo (few elements). - * 0b1..Select long ringo (many elements). - */ -#define ANACTRL_RINGO2_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK) - -#define ANACTRL_RINGO2_CTRL_FS_MASK (0x2U) -#define ANACTRL_RINGO2_CTRL_FS_SHIFT (1U) -/*! FS - Ringo frequency output divider. - * 0b0..High frequency output (frequency lower than 100 MHz). - * 0b1..Low frequency output (frequency lower than 10 MHz). - */ -#define ANACTRL_RINGO2_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK) - -#define ANACTRL_RINGO2_CTRL_PD_MASK (0x4U) -#define ANACTRL_RINGO2_CTRL_PD_SHIFT (2U) -/*! PD - Ringo module Power control. - * 0b0..The Ringo module is enabled. - * 0b1..The Ringo module is disabled. - */ -#define ANACTRL_RINGO2_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK) - -#define ANACTRL_RINGO2_CTRL_E_R24_MASK (0x8U) -#define ANACTRL_RINGO2_CTRL_E_R24_SHIFT (3U) -/*! E_R24 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK) - -#define ANACTRL_RINGO2_CTRL_E_R35_MASK (0x10U) -#define ANACTRL_RINGO2_CTRL_E_R35_SHIFT (4U) -/*! E_R35 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK) - -#define ANACTRL_RINGO2_CTRL_E_M2_MASK (0x20U) -#define ANACTRL_RINGO2_CTRL_E_M2_SHIFT (5U) -/*! E_M2 - Metal 2 (M2) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK) - -#define ANACTRL_RINGO2_CTRL_E_M3_MASK (0x40U) -#define ANACTRL_RINGO2_CTRL_E_M3_SHIFT (6U) -/*! E_M3 - Metal 3 (M3) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK) - -#define ANACTRL_RINGO2_CTRL_E_M4_MASK (0x80U) -#define ANACTRL_RINGO2_CTRL_E_M4_SHIFT (7U) -/*! E_M4 - Metal 4 (M4) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK) - -#define ANACTRL_RINGO2_CTRL_E_M5_MASK (0x100U) -#define ANACTRL_RINGO2_CTRL_E_M5_SHIFT (8U) -/*! E_M5 - Metal 5 (M5) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK) - -#define ANACTRL_RINGO2_CTRL_DIVISOR_MASK (0xF0000U) -#define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT (16U) -/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) - */ -#define ANACTRL_RINGO2_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK) - -#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) -#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT (31U) -/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider - * value, cleared when the change is complete. - */ -#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK) -/*! @} */ - -/*! @name LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register */ -/*! @{ */ - -#define ANACTRL_LDO_XO32M_BYPASS_MASK (0x2U) -#define ANACTRL_LDO_XO32M_BYPASS_SHIFT (1U) -/*! BYPASS - Activate LDO bypass. - * 0b0..Disable bypass mode (for normal operations). - * 0b1..Activate LDO bypass. - */ -#define ANACTRL_LDO_XO32M_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_BYPASS_SHIFT)) & ANACTRL_LDO_XO32M_BYPASS_MASK) - -#define ANACTRL_LDO_XO32M_HIGHZ_MASK (0x4U) -#define ANACTRL_LDO_XO32M_HIGHZ_SHIFT (2U) -/*! HIGHZ - . - * 0b0..Output in High normal state. - * 0b1..Output in High Impedance state. - */ -#define ANACTRL_LDO_XO32M_HIGHZ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_HIGHZ_SHIFT)) & ANACTRL_LDO_XO32M_HIGHZ_MASK) - -#define ANACTRL_LDO_XO32M_VOUT_MASK (0x38U) -#define ANACTRL_LDO_XO32M_VOUT_SHIFT (3U) -/*! VOUT - Sets the LDO output level. - * 0b000..0.750 V. - * 0b001..0.775 V. - * 0b010..0.800 V. - * 0b011..0.825 V. - * 0b100..0.850 V. - * 0b101..0.875 V. - * 0b110..0.900 V. - * 0b111..0.925 V. - */ -#define ANACTRL_LDO_XO32M_VOUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_VOUT_SHIFT)) & ANACTRL_LDO_XO32M_VOUT_MASK) - -#define ANACTRL_LDO_XO32M_IBIAS_MASK (0xC0U) -#define ANACTRL_LDO_XO32M_IBIAS_SHIFT (6U) -/*! IBIAS - Adjust the biasing current. - */ -#define ANACTRL_LDO_XO32M_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_IBIAS_SHIFT)) & ANACTRL_LDO_XO32M_IBIAS_MASK) - -#define ANACTRL_LDO_XO32M_STABMODE_MASK (0x300U) -#define ANACTRL_LDO_XO32M_STABMODE_SHIFT (8U) -/*! STABMODE - Stability configuration. - */ -#define ANACTRL_LDO_XO32M_STABMODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_STABMODE_SHIFT)) & ANACTRL_LDO_XO32M_STABMODE_MASK) -/*! @} */ - -/*! @name AUX_BIAS - AUX_BIAS */ -/*! @{ */ - -#define ANACTRL_AUX_BIAS_VREF1VENABLE_MASK (0x2U) -#define ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT (1U) -/*! VREF1VENABLE - Control output of 1V reference voltage. - * 0b0..Output of 1V reference voltage buffer is bypassed. - * 0b1..Output of 1V reference voltage is enabled. - */ -#define ANACTRL_AUX_BIAS_VREF1VENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VENABLE_MASK) - -#define ANACTRL_AUX_BIAS_ITRIM_MASK (0x7CU) -#define ANACTRL_AUX_BIAS_ITRIM_SHIFT (2U) -/*! ITRIM - current trimming control word. - */ -#define ANACTRL_AUX_BIAS_ITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIM_SHIFT)) & ANACTRL_AUX_BIAS_ITRIM_MASK) - -#define ANACTRL_AUX_BIAS_PTATITRIM_MASK (0xF80U) -#define ANACTRL_AUX_BIAS_PTATITRIM_SHIFT (7U) -/*! PTATITRIM - current trimming control word for ptat current. - */ -#define ANACTRL_AUX_BIAS_PTATITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_PTATITRIM_SHIFT)) & ANACTRL_AUX_BIAS_PTATITRIM_MASK) - -#define ANACTRL_AUX_BIAS_VREF1VTRIM_MASK (0x1F000U) -#define ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT (12U) -/*! VREF1VTRIM - voltage trimming control word. - */ -#define ANACTRL_AUX_BIAS_VREF1VTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VTRIM_MASK) - -#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK (0xE0000U) -#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT (17U) -/*! VREF1VCURVETRIM - Control bit to configure trimming state of mirror. - */ -#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK) - -#define ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK (0x100000U) -#define ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT (20U) -/*! ITRIMCTRL0 - Control bit to configure trimming state of mirror. - */ -#define ANACTRL_AUX_BIAS_ITRIMCTRL0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK) - -#define ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK (0x200000U) -#define ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT (21U) -/*! ITRIMCTRL1 - Control bit to configure trimming state of mirror. - */ -#define ANACTRL_AUX_BIAS_ITRIMCTRL1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK) -/*! @} */ - -/*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */ -/*! @{ */ - -#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK (0x1U) -#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT (0U) -/*! usb_vbusvalid_ext - Override value for Vbus if using external detectors. - */ -#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK) - -#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK (0x2U) -#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT (1U) -/*! usb_id_ext - Override value for ID if using external detectors. - */ -#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK) -/*! @} */ - -/*! @name USBHS_PHY_TRIM - USB High Speed Phy Trim values */ -/*! @{ */ - -#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK (0x3U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT (0U) -/*! trim_usb_reg_env_tail_adj_vd - Adjusts time constant of HS RX squelch (envelope) comparator. - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK (0x3CU) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT (2U) -/*! trim_usbphy_tx_d_cal - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK (0x7C0U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT (6U) -/*! trim_usbphy_tx_cal45dp - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK (0xF800U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT (11U) -/*! trim_usbphy_tx_cal45dm - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK (0x30000U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT (16U) -/*! trim_usb2_refbias_tst - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK (0x1C0000U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT (18U) -/*! trim_usb2_refbias_vbgadj - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK (0xE00000U) -#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT (21U) -/*! trim_pll_ctrl0_div_sel - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ANACTRL_Register_Masks */ - - -/* ANACTRL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE (0x50013000u) - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE_NS (0x40013000u) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS) - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS { ANACTRL } - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS } -#else - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE (0x40013000u) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS { ANACTRL } -#endif - -/*! - * @} - */ /* end of group ANACTRL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CASPER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CASPER_Peripheral_Access_Layer CASPER Peripheral Access Layer - * @{ - */ - -/** CASPER - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL0; /**< Contains the offsets of AB and CD in the RAM., offset: 0x0 */ - __IO uint32_t CTRL1; /**< Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR., offset: 0x4 */ - __IO uint32_t LOADER; /**< Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations., offset: 0x8 */ - __IO uint32_t STATUS; /**< Indicates operational status and would contain the carry bit if used., offset: 0xC */ - __IO uint32_t INTENSET; /**< Sets interrupts, offset: 0x10 */ - __IO uint32_t INTENCLR; /**< Clears interrupts, offset: 0x14 */ - __I uint32_t INTSTAT; /**< Interrupt status bits (mask of INTENSET and STATUS), offset: 0x18 */ - uint8_t RESERVED_0[4]; - __IO uint32_t AREG; /**< A register, offset: 0x20 */ - __IO uint32_t BREG; /**< B register, offset: 0x24 */ - __IO uint32_t CREG; /**< C register, offset: 0x28 */ - __IO uint32_t DREG; /**< D register, offset: 0x2C */ - __IO uint32_t RES0; /**< Result register 0, offset: 0x30 */ - __IO uint32_t RES1; /**< Result register 1, offset: 0x34 */ - __IO uint32_t RES2; /**< Result register 2, offset: 0x38 */ - __IO uint32_t RES3; /**< Result register 3, offset: 0x3C */ - uint8_t RESERVED_1[32]; - __IO uint32_t MASK; /**< Optional mask register, offset: 0x60 */ - __IO uint32_t REMASK; /**< Optional re-mask register, offset: 0x64 */ - uint8_t RESERVED_2[24]; - __IO uint32_t LOCK; /**< Security lock register, offset: 0x80 */ -} CASPER_Type; - -/* ---------------------------------------------------------------------------- - -- CASPER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CASPER_Register_Masks CASPER Register Masks - * @{ - */ - -/*! @name CTRL0 - Contains the offsets of AB and CD in the RAM. */ -/*! @{ */ - -#define CASPER_CTRL0_ABBPAIR_MASK (0x1U) -#define CASPER_CTRL0_ABBPAIR_SHIFT (0U) -/*! ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_CTRL0_ABBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK) - -#define CASPER_CTRL0_ABOFF_MASK (0x1FFCU) -#define CASPER_CTRL0_ABOFF_SHIFT (2U) -/*! ABOFF - Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code - * sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed - * if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up - */ -#define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK) - -#define CASPER_CTRL0_CDBPAIR_MASK (0x10000U) -#define CASPER_CTRL0_CDBPAIR_SHIFT (16U) -/*! CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_CTRL0_CDBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK) - -#define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U) -#define CASPER_CTRL0_CDOFF_SHIFT (18U) -/*! CDOFF - Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees - * (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 - * bit operation. Ideally not in the same RAM as the AB values - */ -#define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK) -/*! @} */ - -/*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */ -/*! @{ */ - -#define CASPER_CTRL1_ITER_MASK (0xFFU) -#define CASPER_CTRL1_ITER_SHIFT (0U) -/*! ITER - Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate. - */ -#define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK) - -#define CASPER_CTRL1_MODE_MASK (0xFF00U) -#define CASPER_CTRL1_MODE_SHIFT (8U) -/*! MODE - Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active. - */ -#define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK) - -#define CASPER_CTRL1_RESBPAIR_MASK (0x10000U) -#define CASPER_CTRL1_RESBPAIR_SHIFT (16U) -/*! RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally - * this is not the same bank as ABBPAIR (when 4-up supported) - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_CTRL1_RESBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK) - -#define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U) -#define CASPER_CTRL1_RESOFF_SHIFT (18U) -/*! RESOFF - Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally - * not in the same RAM as the AB and CD values - */ -#define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK) - -#define CASPER_CTRL1_CSKIP_MASK (0xC0000000U) -#define CASPER_CTRL1_CSKIP_SHIFT (30U) -/*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: - * 0b00..No Skip - * 0b01..Skip if Carry is 1 - * 0b10..Skip if Carry is 0 - * 0b11..Set CTRLOFF to CDOFF and Skip - */ -#define CASPER_CTRL1_CSKIP(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK) -/*! @} */ - -/*! @name LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. */ -/*! @{ */ - -#define CASPER_LOADER_COUNT_MASK (0xFFU) -#define CASPER_LOADER_COUNT_SHIFT (0U) -/*! COUNT - Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one - * op - does not iterate, write N means N control pairs to load - */ -#define CASPER_LOADER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK) - -#define CASPER_LOADER_CTRLBPAIR_MASK (0x10000U) -#define CASPER_LOADER_CTRLBPAIR_SHIFT (16U) -/*! CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not - * matter which bank is used as this is loaded when not performing an operation. - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_LOADER_CTRLBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK) - -#define CASPER_LOADER_CTRLOFF_MASK (0x1FFC0000U) -#define CASPER_LOADER_CTRLOFF_SHIFT (18U) -/*! CTRLOFF - DWord Offset of CTRL pair to load next. - */ -#define CASPER_LOADER_CTRLOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK) -/*! @} */ - -/*! @name STATUS - Indicates operational status and would contain the carry bit if used. */ -/*! @{ */ - -#define CASPER_STATUS_DONE_MASK (0x1U) -#define CASPER_STATUS_DONE_SHIFT (0U) -/*! DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. - * 0b0..Busy or just cleared - * 0b1..Completed last operation - */ -#define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK) - -#define CASPER_STATUS_CARRY_MASK (0x10U) -#define CASPER_STATUS_CARRY_SHIFT (4U) -/*! CARRY - Last carry value if operation produced a carry bit - * 0b0..Carry was 0 or no carry - * 0b1..Carry was 1 - */ -#define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK) - -#define CASPER_STATUS_BUSY_MASK (0x20U) -#define CASPER_STATUS_BUSY_SHIFT (5U) -/*! BUSY - Indicates if the accelerator is busy performing an operation - * 0b0..Not busy - is idle - * 0b1..Is busy - */ -#define CASPER_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK) -/*! @} */ - -/*! @name INTENSET - Sets interrupts */ -/*! @{ */ - -#define CASPER_INTENSET_DONE_MASK (0x1U) -#define CASPER_INTENSET_DONE_SHIFT (0U) -/*! DONE - Set if the accelerator should interrupt when done. - * 0b0..Do not interrupt when done - * 0b1..Interrupt when done - */ -#define CASPER_INTENSET_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK) -/*! @} */ - -/*! @name INTENCLR - Clears interrupts */ -/*! @{ */ - -#define CASPER_INTENCLR_DONE_MASK (0x1U) -#define CASPER_INTENCLR_DONE_SHIFT (0U) -/*! DONE - Written to clear an interrupt set with INTENSET. - * 0b0..If written 0, ignored - * 0b1..If written 1, do not Interrupt when done - */ -#define CASPER_INTENCLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) */ -/*! @{ */ - -#define CASPER_INTSTAT_DONE_MASK (0x1U) -#define CASPER_INTSTAT_DONE_SHIFT (0U) -/*! DONE - If set, interrupt is caused by accelerator being done. - * 0b0..Not caused by accelerator being done - * 0b1..Caused by accelerator being done - */ -#define CASPER_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK) -/*! @} */ - -/*! @name AREG - A register */ -/*! @{ */ - -#define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_AREG_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, - * but is available when accelerator not busy. - */ -#define CASPER_AREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name BREG - B register */ -/*! @{ */ - -#define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_BREG_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, - * but is available when accelerator not busy. - */ -#define CASPER_BREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name CREG - C register */ -/*! @{ */ - -#define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_CREG_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, - * but is available when accelerator not busy. - */ -#define CASPER_CREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name DREG - D register */ -/*! @{ */ - -#define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_DREG_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, - * but is available when accelerator not busy. - */ -#define CASPER_DREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES0 - Result register 0 */ -/*! @{ */ - -#define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES0_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally - * written or read by application, but is available when accelerator not busy. - */ -#define CASPER_RES0_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES1 - Result register 1 */ -/*! @{ */ - -#define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES1_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally - * written or read by application, but is available when accelerator not busy. - */ -#define CASPER_RES1_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES2 - Result register 2 */ -/*! @{ */ - -#define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES2_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally - * written or read by application, but is available when accelerator not busy. - */ -#define CASPER_RES2_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES3 - Result register 3 */ -/*! @{ */ - -#define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES3_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally - * written or read by application, but is available when accelerator not busy. - */ -#define CASPER_RES3_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK) -/*! @} */ - -/*! @name MASK - Optional mask register */ -/*! @{ */ - -#define CASPER_MASK_MASK_MASK (0xFFFFFFFFU) -#define CASPER_MASK_MASK_SHIFT (0U) -/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values - */ -#define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK) -/*! @} */ - -/*! @name REMASK - Optional re-mask register */ -/*! @{ */ - -#define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU) -#define CASPER_REMASK_MASK_SHIFT (0U) -/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values - */ -#define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK) -/*! @} */ - -/*! @name LOCK - Security lock register */ -/*! @{ */ - -#define CASPER_LOCK_LOCK_MASK (0x1U) -#define CASPER_LOCK_LOCK_SHIFT (0U) -/*! LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. - * 0b0..unlock - * 0b1..Lock to current security level - */ -#define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK) - -#define CASPER_LOCK_KEY_MASK (0x1FFF0U) -#define CASPER_LOCK_KEY_SHIFT (4U) -/*! KEY - Must be written as 0x73D to change the register. - * 0b0011100111101..If set during write, will allow lock or unlock - */ -#define CASPER_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CASPER_Register_Masks */ - - -/* CASPER - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CASPER base address */ - #define CASPER_BASE (0x500A5000u) - /** Peripheral CASPER base address */ - #define CASPER_BASE_NS (0x400A5000u) - /** Peripheral CASPER base pointer */ - #define CASPER ((CASPER_Type *)CASPER_BASE) - /** Peripheral CASPER base pointer */ - #define CASPER_NS ((CASPER_Type *)CASPER_BASE_NS) - /** Array initializer of CASPER peripheral base addresses */ - #define CASPER_BASE_ADDRS { CASPER_BASE } - /** Array initializer of CASPER peripheral base pointers */ - #define CASPER_BASE_PTRS { CASPER } - /** Array initializer of CASPER peripheral base addresses */ - #define CASPER_BASE_ADDRS_NS { CASPER_BASE_NS } - /** Array initializer of CASPER peripheral base pointers */ - #define CASPER_BASE_PTRS_NS { CASPER_NS } -#else - /** Peripheral CASPER base address */ - #define CASPER_BASE (0x400A5000u) - /** Peripheral CASPER base pointer */ - #define CASPER ((CASPER_Type *)CASPER_BASE) - /** Array initializer of CASPER peripheral base addresses */ - #define CASPER_BASE_ADDRS { CASPER_BASE } - /** Array initializer of CASPER peripheral base pointers */ - #define CASPER_BASE_PTRS { CASPER } -#endif -/** Interrupt vectors for the CASPER peripheral type */ -#define CASPER_IRQS { CASER_IRQn } - -/*! - * @} - */ /* end of group CASPER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CRC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer - * @{ - */ - -/** CRC - Register Layout Typedef */ -typedef struct { - __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ - __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ - union { /* offset: 0x8 */ - __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ - __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ - }; -} CRC_Type; - -/* ---------------------------------------------------------------------------- - -- CRC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Register_Masks CRC Register Masks - * @{ - */ - -/*! @name MODE - CRC mode register */ -/*! @{ */ - -#define CRC_MODE_CRC_POLY_MASK (0x3U) -#define CRC_MODE_CRC_POLY_SHIFT (0U) -/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial - */ -#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) - -#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) -#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) -/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) - */ -#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) - -#define CRC_MODE_CMPL_WR_MASK (0x8U) -#define CRC_MODE_CMPL_WR_SHIFT (3U) -/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA - */ -#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) - -#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) -#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) -/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM - */ -#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) - -#define CRC_MODE_CMPL_SUM_MASK (0x20U) -#define CRC_MODE_CMPL_SUM_SHIFT (5U) -/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM - */ -#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) -/*! @} */ - -/*! @name SEED - CRC seed register */ -/*! @{ */ - -#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) -#define CRC_SEED_CRC_SEED_SHIFT (0U) -/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with - * selected bit order and 1's complement pre-processes. A write access to this register will - * overrule the CRC calculation in progresses. - */ -#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) -/*! @} */ - -/*! @name SUM - CRC checksum register */ -/*! @{ */ - -#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) -#define CRC_SUM_CRC_SUM_SHIFT (0U) -/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. - */ -#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) -/*! @} */ - -/*! @name WR_DATA - CRC data register */ -/*! @{ */ - -#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) -#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) -/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with - * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and - * accept back-to-back transactions. - */ -#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CRC_Register_Masks */ - - -/* CRC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CRC_ENGINE base address */ - #define CRC_ENGINE_BASE (0x50095000u) - /** Peripheral CRC_ENGINE base address */ - #define CRC_ENGINE_BASE_NS (0x40095000u) - /** Peripheral CRC_ENGINE base pointer */ - #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) - /** Peripheral CRC_ENGINE base pointer */ - #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS) - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS { CRC_ENGINE } - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS } -#else - /** Peripheral CRC_ENGINE base address */ - #define CRC_ENGINE_BASE (0x40095000u) - /** Peripheral CRC_ENGINE base pointer */ - #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS { CRC_ENGINE } -#endif - -/*! - * @} - */ /* end of group CRC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CTIMER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer - * @{ - */ - -/** CTIMER - Register Layout Typedef */ -typedef struct { - __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ - __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ - __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ - __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ - __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ - __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ - __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ - __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ - __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ - __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ - uint8_t RESERVED_0[48]; - __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ - __IO uint32_t PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */ - __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ -} CTIMER_Type; - -/* ---------------------------------------------------------------------------- - -- CTIMER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Register_Masks CTIMER Register Masks - * @{ - */ - -/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ -/*! @{ */ - -#define CTIMER_IR_MR0INT_MASK (0x1U) -#define CTIMER_IR_MR0INT_SHIFT (0U) -/*! MR0INT - Interrupt flag for match channel 0. - */ -#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) - -#define CTIMER_IR_MR1INT_MASK (0x2U) -#define CTIMER_IR_MR1INT_SHIFT (1U) -/*! MR1INT - Interrupt flag for match channel 1. - */ -#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) - -#define CTIMER_IR_MR2INT_MASK (0x4U) -#define CTIMER_IR_MR2INT_SHIFT (2U) -/*! MR2INT - Interrupt flag for match channel 2. - */ -#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) - -#define CTIMER_IR_MR3INT_MASK (0x8U) -#define CTIMER_IR_MR3INT_SHIFT (3U) -/*! MR3INT - Interrupt flag for match channel 3. - */ -#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) - -#define CTIMER_IR_CR0INT_MASK (0x10U) -#define CTIMER_IR_CR0INT_SHIFT (4U) -/*! CR0INT - Interrupt flag for capture channel 0 event. - */ -#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) - -#define CTIMER_IR_CR1INT_MASK (0x20U) -#define CTIMER_IR_CR1INT_SHIFT (5U) -/*! CR1INT - Interrupt flag for capture channel 1 event. - */ -#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) - -#define CTIMER_IR_CR2INT_MASK (0x40U) -#define CTIMER_IR_CR2INT_SHIFT (6U) -/*! CR2INT - Interrupt flag for capture channel 2 event. - */ -#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) - -#define CTIMER_IR_CR3INT_MASK (0x80U) -#define CTIMER_IR_CR3INT_SHIFT (7U) -/*! CR3INT - Interrupt flag for capture channel 3 event. - */ -#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) -/*! @} */ - -/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ -/*! @{ */ - -#define CTIMER_TCR_CEN_MASK (0x1U) -#define CTIMER_TCR_CEN_SHIFT (0U) -/*! CEN - Counter enable. - * 0b0..Disabled.The counters are disabled. - * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. - */ -#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) - -#define CTIMER_TCR_CRST_MASK (0x2U) -#define CTIMER_TCR_CRST_SHIFT (1U) -/*! CRST - Counter reset. - * 0b0..Disabled. Do nothing. - * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of - * the APB bus clock. The counters remain reset until TCR[1] is returned to zero. - */ -#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) -/*! @} */ - -/*! @name TC - Timer Counter */ -/*! @{ */ - -#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_TC_TCVAL_SHIFT (0U) -/*! TCVAL - Timer counter value. - */ -#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) -/*! @} */ - -/*! @name PR - Prescale Register */ -/*! @{ */ - -#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PR_PRVAL_SHIFT (0U) -/*! PRVAL - Prescale counter value. - */ -#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) -/*! @} */ - -/*! @name PC - Prescale Counter */ -/*! @{ */ - -#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PC_PCVAL_SHIFT (0U) -/*! PCVAL - Prescale counter value. - */ -#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) -/*! @} */ - -/*! @name MCR - Match Control Register */ -/*! @{ */ - -#define CTIMER_MCR_MR0I_MASK (0x1U) -#define CTIMER_MCR_MR0I_SHIFT (0U) -/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. - */ -#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) - -#define CTIMER_MCR_MR0R_MASK (0x2U) -#define CTIMER_MCR_MR0R_SHIFT (1U) -/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. - */ -#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) - -#define CTIMER_MCR_MR0S_MASK (0x4U) -#define CTIMER_MCR_MR0S_SHIFT (2U) -/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. - */ -#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) - -#define CTIMER_MCR_MR1I_MASK (0x8U) -#define CTIMER_MCR_MR1I_SHIFT (3U) -/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. - */ -#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) - -#define CTIMER_MCR_MR1R_MASK (0x10U) -#define CTIMER_MCR_MR1R_SHIFT (4U) -/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. - */ -#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) - -#define CTIMER_MCR_MR1S_MASK (0x20U) -#define CTIMER_MCR_MR1S_SHIFT (5U) -/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. - */ -#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) - -#define CTIMER_MCR_MR2I_MASK (0x40U) -#define CTIMER_MCR_MR2I_SHIFT (6U) -/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. - */ -#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) - -#define CTIMER_MCR_MR2R_MASK (0x80U) -#define CTIMER_MCR_MR2R_SHIFT (7U) -/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. - */ -#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) - -#define CTIMER_MCR_MR2S_MASK (0x100U) -#define CTIMER_MCR_MR2S_SHIFT (8U) -/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. - */ -#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) - -#define CTIMER_MCR_MR3I_MASK (0x200U) -#define CTIMER_MCR_MR3I_SHIFT (9U) -/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. - */ -#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) - -#define CTIMER_MCR_MR3R_MASK (0x400U) -#define CTIMER_MCR_MR3R_SHIFT (10U) -/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it. - */ -#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) - -#define CTIMER_MCR_MR3S_MASK (0x800U) -#define CTIMER_MCR_MR3S_SHIFT (11U) -/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. - */ -#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) - -#define CTIMER_MCR_MR0RL_MASK (0x1000000U) -#define CTIMER_MCR_MR0RL_SHIFT (24U) -/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero - * (either via a match event or a write to bit 1 of the TCR). - */ -#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) - -#define CTIMER_MCR_MR1RL_MASK (0x2000000U) -#define CTIMER_MCR_MR1RL_SHIFT (25U) -/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero - * (either via a match event or a write to bit 1 of the TCR). - */ -#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) - -#define CTIMER_MCR_MR2RL_MASK (0x4000000U) -#define CTIMER_MCR_MR2RL_SHIFT (26U) -/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero - * (either via a match event or a write to bit 1 of the TCR). - */ -#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) - -#define CTIMER_MCR_MR3RL_MASK (0x8000000U) -#define CTIMER_MCR_MR3RL_SHIFT (27U) -/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero - * (either via a match event or a write to bit 1 of the TCR). - */ -#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) -/*! @} */ - -/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ -/*! @{ */ - -#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) -#define CTIMER_MR_MATCH_SHIFT (0U) -/*! MATCH - Timer counter match value. - */ -#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) -/*! @} */ - -/* The count of CTIMER_MR */ -#define CTIMER_MR_COUNT (4U) - -/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ -/*! @{ */ - -#define CTIMER_CCR_CAP0RE_MASK (0x1U) -#define CTIMER_CCR_CAP0RE_SHIFT (0U) -/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) - -#define CTIMER_CCR_CAP0FE_MASK (0x2U) -#define CTIMER_CCR_CAP0FE_SHIFT (1U) -/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) - -#define CTIMER_CCR_CAP0I_MASK (0x4U) -#define CTIMER_CCR_CAP0I_SHIFT (2U) -/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. - */ -#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) - -#define CTIMER_CCR_CAP1RE_MASK (0x8U) -#define CTIMER_CCR_CAP1RE_SHIFT (3U) -/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) - -#define CTIMER_CCR_CAP1FE_MASK (0x10U) -#define CTIMER_CCR_CAP1FE_SHIFT (4U) -/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) - -#define CTIMER_CCR_CAP1I_MASK (0x20U) -#define CTIMER_CCR_CAP1I_SHIFT (5U) -/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. - */ -#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) - -#define CTIMER_CCR_CAP2RE_MASK (0x40U) -#define CTIMER_CCR_CAP2RE_SHIFT (6U) -/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) - -#define CTIMER_CCR_CAP2FE_MASK (0x80U) -#define CTIMER_CCR_CAP2FE_SHIFT (7U) -/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) - -#define CTIMER_CCR_CAP2I_MASK (0x100U) -#define CTIMER_CCR_CAP2I_SHIFT (8U) -/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. - */ -#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) - -#define CTIMER_CCR_CAP3RE_MASK (0x200U) -#define CTIMER_CCR_CAP3RE_SHIFT (9U) -/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) - -#define CTIMER_CCR_CAP3FE_MASK (0x400U) -#define CTIMER_CCR_CAP3FE_SHIFT (10U) -/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) - -#define CTIMER_CCR_CAP3I_MASK (0x800U) -#define CTIMER_CCR_CAP3I_SHIFT (11U) -/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. - */ -#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) -/*! @} */ - -/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ -/*! @{ */ - -#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) -#define CTIMER_CR_CAP_SHIFT (0U) -/*! CAP - Timer counter capture value. - */ -#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) -/*! @} */ - -/* The count of CTIMER_CR */ -#define CTIMER_CR_COUNT (4U) - -/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ -/*! @{ */ - -#define CTIMER_EMR_EM0_MASK (0x1U) -#define CTIMER_EMR_EM0_SHIFT (0U) -/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output - * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, - * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if - * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - */ -#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) - -#define CTIMER_EMR_EM1_MASK (0x2U) -#define CTIMER_EMR_EM1_SHIFT (1U) -/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output - * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, - * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if - * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - */ -#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) - -#define CTIMER_EMR_EM2_MASK (0x4U) -#define CTIMER_EMR_EM2_SHIFT (2U) -/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output - * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, - * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if - * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - */ -#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) - -#define CTIMER_EMR_EM3_MASK (0x8U) -#define CTIMER_EMR_EM3_SHIFT (3U) -/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output - * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, - * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins - * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - */ -#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) - -#define CTIMER_EMR_EMC0_MASK (0x30U) -#define CTIMER_EMR_EMC0_SHIFT (4U) -/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) - -#define CTIMER_EMR_EMC1_MASK (0xC0U) -#define CTIMER_EMR_EMC1_SHIFT (6U) -/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) - -#define CTIMER_EMR_EMC2_MASK (0x300U) -#define CTIMER_EMR_EMC2_SHIFT (8U) -/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) - -#define CTIMER_EMR_EMC3_MASK (0xC00U) -#define CTIMER_EMR_EMC3_SHIFT (10U) -/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) -/*! @} */ - -/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ -/*! @{ */ - -#define CTIMER_CTCR_CTMODE_MASK (0x3U) -#define CTIMER_CTCR_CTMODE_SHIFT (0U) -/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment - * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC - * is incremented when the Prescale Counter matches the Prescale Register. - * 0b00..Timer Mode. Incremented every rising APB bus clock edge. - * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. - * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. - * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. - */ -#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) - -#define CTIMER_CTCR_CINSEL_MASK (0xCU) -#define CTIMER_CTCR_CINSEL_SHIFT (2U) -/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which - * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input - * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be - * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the - * same timer. - * 0b00..Channel 0. CAPn.0 for CTIMERn - * 0b01..Channel 1. CAPn.1 for CTIMERn - * 0b10..Channel 2. CAPn.2 for CTIMERn - * 0b11..Channel 3. CAPn.3 for CTIMERn - */ -#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) - -#define CTIMER_CTCR_ENCC_MASK (0x10U) -#define CTIMER_CTCR_ENCC_SHIFT (4U) -/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the - * capture-edge event specified in bits 7:5 occurs. - */ -#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) - -#define CTIMER_CTCR_SELCC_MASK (0xE0U) -#define CTIMER_CTCR_SELCC_SHIFT (5U) -/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the - * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to - * 0x3 and 0x6 to 0x7 are reserved. - * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - */ -#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) -/*! @} */ - -/*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */ -/*! @{ */ - -#define CTIMER_PWMC_PWMEN0_MASK (0x1U) -#define CTIMER_PWMC_PWMEN0_SHIFT (0U) -/*! PWMEN0 - PWM mode enable for channel0. - * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. - */ -#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) - -#define CTIMER_PWMC_PWMEN1_MASK (0x2U) -#define CTIMER_PWMC_PWMEN1_SHIFT (1U) -/*! PWMEN1 - PWM mode enable for channel1. - * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. - */ -#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) - -#define CTIMER_PWMC_PWMEN2_MASK (0x4U) -#define CTIMER_PWMC_PWMEN2_SHIFT (2U) -/*! PWMEN2 - PWM mode enable for channel2. - * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. - */ -#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) - -#define CTIMER_PWMC_PWMEN3_MASK (0x8U) -#define CTIMER_PWMC_PWMEN3_SHIFT (3U) -/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. - * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. - * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. - */ -#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) -/*! @} */ - -/*! @name MSR - Match Shadow Register */ -/*! @{ */ - -#define CTIMER_MSR_SHADOW_MASK (0xFFFFFFFFU) -#define CTIMER_MSR_SHADOW_SHIFT (0U) -/*! SHADOW - Timer counter match shadow value. - */ -#define CTIMER_MSR_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOW_SHIFT)) & CTIMER_MSR_SHADOW_MASK) -/*! @} */ - -/* The count of CTIMER_MSR */ -#define CTIMER_MSR_COUNT (4U) - - -/*! - * @} - */ /* end of group CTIMER_Register_Masks */ - - -/* CTIMER - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE (0x50008000u) - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE_NS (0x40008000u) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE (0x50009000u) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE_NS (0x40009000u) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE (0x50028000u) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE_NS (0x40028000u) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE (0x50029000u) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE_NS (0x40029000u) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE (0x5002A000u) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE_NS (0x4002A000u) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } -#else - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE (0x40008000u) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE (0x40009000u) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE (0x40028000u) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE (0x40029000u) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE (0x4002A000u) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } -#endif -/** Interrupt vectors for the CTIMER peripheral type */ -#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } - -/*! - * @} - */ /* end of group CTIMER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DBGMAILBOX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DBGMAILBOX_Peripheral_Access_Layer DBGMAILBOX Peripheral Access Layer - * @{ - */ - -/** DBGMAILBOX - Register Layout Typedef */ -typedef struct { - __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */ - __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */ - __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */ - uint8_t RESERVED_0[240]; - __I uint32_t ID; /**< Identification register, offset: 0xFC */ -} DBGMAILBOX_Type; - -/* ---------------------------------------------------------------------------- - -- DBGMAILBOX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DBGMAILBOX_Register_Masks DBGMAILBOX Register Masks - * @{ - */ - -/*! @name CSW - CRC mode register */ -/*! @{ */ - -#define DBGMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) -#define DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) -/*! RESYNCH_REQ - Debugger will set this bit to 1 to request a resynchronrisation - */ -#define DBGMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DBGMAILBOX_CSW_RESYNCH_REQ_MASK) - -#define DBGMAILBOX_CSW_REQ_PENDING_MASK (0x2U) -#define DBGMAILBOX_CSW_REQ_PENDING_SHIFT (1U) -/*! REQ_PENDING - Request is pending from debugger (i.e unread value in REQUEST) - */ -#define DBGMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DBGMAILBOX_CSW_REQ_PENDING_MASK) - -#define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) -#define DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) -/*! DBG_OR_ERR - Debugger overrun error (previous REQUEST overwritten before being picked up by ROM) - */ -#define DBGMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK) - -#define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) -#define DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) -/*! AHB_OR_ERR - AHB overrun Error (Return value overwritten by ROM) - */ -#define DBGMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK) - -#define DBGMAILBOX_CSW_SOFT_RESET_MASK (0x10U) -#define DBGMAILBOX_CSW_SOFT_RESET_SHIFT (4U) -/*! SOFT_RESET - Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to - * this bit will cause a soft reset for DM. - */ -#define DBGMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DBGMAILBOX_CSW_SOFT_RESET_MASK) - -#define DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) -#define DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) -/*! CHIP_RESET_REQ - Write only bit. Once written will cause the chip to reset (note that the DM is - * not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event) - */ -#define DBGMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK) -/*! @} */ - -/*! @name REQUEST - CRC seed register */ -/*! @{ */ - -#define DBGMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU) -#define DBGMAILBOX_REQUEST_REQ_SHIFT (0U) -/*! REQ - Request Value - */ -#define DBGMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_REQUEST_REQ_SHIFT)) & DBGMAILBOX_REQUEST_REQ_MASK) -/*! @} */ - -/*! @name RETURN - Return value from ROM. */ -/*! @{ */ - -#define DBGMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) -#define DBGMAILBOX_RETURN_RET_SHIFT (0U) -/*! RET - The Return value from ROM. - */ -#define DBGMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_RETURN_RET_SHIFT)) & DBGMAILBOX_RETURN_RET_MASK) -/*! @} */ - -/*! @name ID - Identification register */ -/*! @{ */ - -#define DBGMAILBOX_ID_ID_MASK (0xFFFFFFFFU) -#define DBGMAILBOX_ID_ID_SHIFT (0U) -/*! ID - Identification value. - */ -#define DBGMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_ID_ID_SHIFT)) & DBGMAILBOX_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group DBGMAILBOX_Register_Masks */ - - -/* DBGMAILBOX - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral DBGMAILBOX base address */ - #define DBGMAILBOX_BASE (0x5009C000u) - /** Peripheral DBGMAILBOX base address */ - #define DBGMAILBOX_BASE_NS (0x4009C000u) - /** Peripheral DBGMAILBOX base pointer */ - #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) - /** Peripheral DBGMAILBOX base pointer */ - #define DBGMAILBOX_NS ((DBGMAILBOX_Type *)DBGMAILBOX_BASE_NS) - /** Array initializer of DBGMAILBOX peripheral base addresses */ - #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } - /** Array initializer of DBGMAILBOX peripheral base pointers */ - #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } - /** Array initializer of DBGMAILBOX peripheral base addresses */ - #define DBGMAILBOX_BASE_ADDRS_NS { DBGMAILBOX_BASE_NS } - /** Array initializer of DBGMAILBOX peripheral base pointers */ - #define DBGMAILBOX_BASE_PTRS_NS { DBGMAILBOX_NS } -#else - /** Peripheral DBGMAILBOX base address */ - #define DBGMAILBOX_BASE (0x4009C000u) - /** Peripheral DBGMAILBOX base pointer */ - #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) - /** Array initializer of DBGMAILBOX peripheral base addresses */ - #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } - /** Array initializer of DBGMAILBOX peripheral base pointers */ - #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } -#endif - -/*! - * @} - */ /* end of group DBGMAILBOX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer - * @{ - */ - -/** DMA - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ - __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ - __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ - uint8_t RESERVED_0[20]; - struct { /* offset: 0x20, array step: 0x5C */ - __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ - uint8_t RESERVED_0[4]; - __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ - uint8_t RESERVED_1[4]; - __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ - uint8_t RESERVED_2[4]; - __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ - uint8_t RESERVED_3[4]; - __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ - uint8_t RESERVED_4[4]; - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ - uint8_t RESERVED_5[4]; - __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ - uint8_t RESERVED_6[4]; - __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ - uint8_t RESERVED_7[4]; - __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ - uint8_t RESERVED_8[4]; - __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ - uint8_t RESERVED_9[4]; - __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ - uint8_t RESERVED_10[4]; - __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ - } COMMON[1]; - uint8_t RESERVED_1[900]; - struct { /* offset: 0x400, array step: 0x10 */ - __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ - __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ - __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } CHANNEL[23]; -} DMA_Type; - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/*! @name CTRL - DMA control. */ -/*! @{ */ - -#define DMA_CTRL_ENABLE_MASK (0x1U) -#define DMA_CTRL_ENABLE_SHIFT (0U) -/*! ENABLE - DMA controller master enable. - * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when - * disabled, but does not prevent re-triggering when the DMA controller is re-enabled. - * 0b1..Enabled. The DMA controller is enabled. - */ -#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status. */ -/*! @{ */ - -#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) -#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) -/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. - * 0b0..Not pending. No enabled interrupts are pending. - * 0b1..Pending. At least one enabled interrupt is pending. - */ -#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) - -#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) -#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) -/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. - * 0b0..Not pending. No error interrupts are pending. - * 0b1..Pending. At least one error interrupt is pending. - */ -#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) -/*! @} */ - -/*! @name SRAMBASE - SRAM address of the channel configuration table. */ -/*! @{ */ - -#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) -#define DMA_SRAMBASE_OFFSET_SHIFT (9U) -/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the - * table must begin on a 512 byte boundary. - */ -#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) -/*! @} */ - -/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) -/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = - * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. - */ -#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLESET */ -#define DMA_COMMON_ENABLESET_COUNT (1U) - -/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) -/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears - * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits - * are reserved. - */ -#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLECLR */ -#define DMA_COMMON_ENABLECLR_COUNT (1U) - -/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) -/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = - * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. - */ -#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ACTIVE */ -#define DMA_COMMON_ACTIVE_COUNT (1U) - -/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) -#define DMA_COMMON_BUSY_BSY_SHIFT (0U) -/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = - * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. - */ -#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) -/*! @} */ - -/* The count of DMA_COMMON_BUSY */ -#define DMA_COMMON_BUSY_COUNT (1U) - -/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) -/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of - * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is - * not active. 1 = error interrupt is active. - */ -#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ERRINT */ -#define DMA_COMMON_ERRINT_COUNT (1U) - -/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) -/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The - * number of bits = number of DMA channels in this device. Other bits are reserved. 0 = - * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENSET */ -#define DMA_COMMON_INTENSET_COUNT (1U) - -/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) -/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n - * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are - * reserved. - */ -#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENCLR */ -#define DMA_COMMON_INTENCLR_COUNT (1U) - -/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTA_IA_SHIFT (0U) -/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of - * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel - * interrupt A is not active. 1 = the DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTA */ -#define DMA_COMMON_INTA_COUNT (1U) - -/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTB_IB_SHIFT (0U) -/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of - * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel - * interrupt B is not active. 1 = the DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTB */ -#define DMA_COMMON_INTB_COUNT (1U) - -/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETVALID_SV_SHIFT (0U) -/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits - * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the - * VALIDPENDING control bit for DMA channel n - */ -#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETVALID */ -#define DMA_COMMON_SETVALID_COUNT (1U) - -/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) -/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number - * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = - * sets the TRIG bit for DMA channel n. - */ -#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETTRIG */ -#define DMA_COMMON_SETTRIG_COUNT (1U) - -/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) -/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. - * 1 = aborts DMA operations on channel n. - */ -#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ABORT */ -#define DMA_COMMON_ABORT_COUNT (1U) - -/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ -/*! @{ */ - -#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) -#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) -/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory - * move, any peripheral DMA request associated with that channel can be disabled to prevent any - * interaction between the peripheral and the DMA controller. - * 0b0..Disabled. Peripheral DMA requests are disabled. - * 0b1..Enabled. Peripheral DMA requests are enabled. - */ -#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) - -#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) -#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) -/*! HWTRIGEN - Hardware Triggering Enable for this channel. - * 0b0..Disabled. Hardware triggering is not used. - * 0b1..Enabled. Use hardware triggering. - */ -#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) - -#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) -#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) -/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. - * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. - * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. - */ -#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) - -#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) -#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) -/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. - * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. - * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = - * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the - * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger - * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the - * current BURSTPOWER length are completed. - */ -#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) - -#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) -#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) -/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. - * 0b0..Single transfer. Hardware trigger causes a single transfer. - * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a - * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a - * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is - * complete. - */ -#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) - -#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) -#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) -/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when - * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). - * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many - * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that - * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: - * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = - * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The - * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even - * multiple of the burst size. - */ -#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) - -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) -/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is - * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this - * could be used to read several sequential registers from a peripheral for each DMA burst, - * reading the same registers again for each burst. - * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. - * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. - */ -#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) - -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) -/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is - * 'wrapped', meaning that the destination address range for each burst will be the same. As an - * example, this could be used to write several sequential registers to a peripheral for each DMA - * burst, writing the same registers again for each burst. - * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. - * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. - */ -#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) - -#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) -#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) -/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority - * levels are supported: 0x0 = highest priority. 0x7 = lowest priority. - */ -#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CFG */ -#define DMA_CHANNEL_CFG_COUNT (23U) - -/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ -/*! @{ */ - -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) -/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the - * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. - * 0b0..No effect. No effect on DMA operation. - * 0b1..Valid pending. - */ -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) - -#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) -#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) -/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is - * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. - * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. - * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. - */ -#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CTLSTAT */ -#define DMA_CHANNEL_CTLSTAT_COUNT (23U) - -/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ -/*! @{ */ - -#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) -#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) -/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor - * is valid and can potentially be acted upon, if all other activation criteria are fulfilled. - * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. - * 0b1..Valid. The current channel descriptor is considered valid. - */ -#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) - -#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) -#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) -/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current - * descriptor is exhausted. Reloading allows ping-pong and linked transfers. - * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. - * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) - -#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) -#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) -/*! SWTRIG - Software Trigger. - * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by - * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. - * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not - * be used with level triggering when TRIGBURST = 0. - */ -#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) - -#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) -#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) -/*! CLRTRIG - Clear Trigger. - * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. - * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted - */ -#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) - -#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) -#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) -/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between - * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By - * convention, interrupt A may be used when only one interrupt flag is needed. - * 0b0..No effect. - * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) - -#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) -#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) -/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between - * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By - * convention, interrupt A may be used when only one interrupt flag is needed. - * 0b0..No effect. - * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) - -#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) -#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) -/*! WIDTH - Transfer width used for this DMA channel. - * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). - * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). - * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). - * 0b11..Reserved. Reserved setting, do not use. - */ -#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) - -#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) -#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) -/*! SRCINC - Determines whether the source address is incremented for each DMA transfer. - * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. - * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is - * the usual case when the source is memory. - * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. - * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. - */ -#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) - -#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) -#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) -/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. - * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when - * the destination is a peripheral device. - * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. - * This is the usual case when the destination is memory. - * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. - * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. - */ -#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) - -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) -/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes - * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller - * uses this bit field during transfer to count down. Hence, it cannot be used by software to read - * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 - * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of - * 1,024 transfers will be performed. - */ -#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_XFERCFG */ -#define DMA_CHANNEL_XFERCFG_COUNT (23U) - - -/*! - * @} - */ /* end of group DMA_Register_Masks */ - - -/* DMA - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral DMA0 base address */ - #define DMA0_BASE (0x50082000u) - /** Peripheral DMA0 base address */ - #define DMA0_BASE_NS (0x40082000u) - /** Peripheral DMA0 base pointer */ - #define DMA0 ((DMA_Type *)DMA0_BASE) - /** Peripheral DMA0 base pointer */ - #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) - /** Peripheral DMA1 base address */ - #define DMA1_BASE (0x500A7000u) - /** Peripheral DMA1 base address */ - #define DMA1_BASE_NS (0x400A7000u) - /** Peripheral DMA1 base pointer */ - #define DMA1 ((DMA_Type *)DMA1_BASE) - /** Peripheral DMA1 base pointer */ - #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS { DMA0, DMA1 } - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } -#else - /** Peripheral DMA0 base address */ - #define DMA0_BASE (0x40082000u) - /** Peripheral DMA0 base pointer */ - #define DMA0 ((DMA_Type *)DMA0_BASE) - /** Peripheral DMA1 base address */ - #define DMA1_BASE (0x400A7000u) - /** Peripheral DMA1 base pointer */ - #define DMA1 ((DMA_Type *)DMA1_BASE) - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS { DMA0, DMA1 } -#endif -/** Interrupt vectors for the DMA peripheral type */ -#define DMA_IRQS { DMA0_IRQn, DMA1_IRQn } - -/*! - * @} - */ /* end of group DMA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer - * @{ - */ - -/** FLASH - Register Layout Typedef */ -typedef struct { - __O uint32_t CMD; /**< command register, offset: 0x0 */ - __O uint32_t EVENT; /**< event register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */ - __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */ - uint8_t RESERVED_1[104]; - __IO uint32_t DATAW[4]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_2[3912]; - __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */ - __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */ - __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ - __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ - __O uint32_t INT_CLR_STATUS; /**< Clear interrupt status bits, offset: 0xFE8 */ - __O uint32_t INT_SET_STATUS; /**< Set interrupt status bits, offset: 0xFEC */ - uint8_t RESERVED_3[12]; - __I uint32_t MODULE_ID; /**< Controller+Memory module identification, offset: 0xFFC */ -} FLASH_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_Register_Masks FLASH Register Masks - * @{ - */ - -/*! @name CMD - command register */ -/*! @{ */ - -#define FLASH_CMD_CMD_MASK (0xFFFFFFFFU) -#define FLASH_CMD_CMD_SHIFT (0U) -/*! CMD - command register. - */ -#define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK) -/*! @} */ - -/*! @name EVENT - event register */ -/*! @{ */ - -#define FLASH_EVENT_RST_MASK (0x1U) -#define FLASH_EVENT_RST_SHIFT (0U) -/*! RST - When bit is set, the controller and flash are reset. - */ -#define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK) - -#define FLASH_EVENT_WAKEUP_MASK (0x2U) -#define FLASH_EVENT_WAKEUP_SHIFT (1U) -/*! WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active. - */ -#define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK) - -#define FLASH_EVENT_ABORT_MASK (0x4U) -#define FLASH_EVENT_ABORT_SHIFT (2U) -/*! ABORT - When bit is set, a running program/erase command is aborted. - */ -#define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK) -/*! @} */ - -/*! @name STARTA - start (or only) address for next flash command */ -/*! @{ */ - -#define FLASH_STARTA_STARTA_MASK (0x3FFFFU) -#define FLASH_STARTA_STARTA_SHIFT (0U) -/*! STARTA - Address / Start address for commands that take an address (range) as a parameter. - */ -#define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK) -/*! @} */ - -/*! @name STOPA - end address for next flash command, if command operates on address ranges */ -/*! @{ */ - -#define FLASH_STOPA_STOPA_MASK (0x3FFFFU) -#define FLASH_STOPA_STOPA_SHIFT (0U) -/*! STOPA - Stop address for commands that take an address range as a parameter (the word specified - * by STOPA is included in the address range). - */ -#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK) -/*! @} */ - -/*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */ -/*! @{ */ - -#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU) -#define FLASH_DATAW_DATAW_SHIFT (0U) -#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK) -/*! @} */ - -/* The count of FLASH_DATAW */ -#define FLASH_DATAW_COUNT (4U) - -/*! @name INT_CLR_ENABLE - Clear interrupt enable bits */ -/*! @{ */ - -#define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U) -#define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U) -/*! FAIL - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - */ -#define FLASH_INT_CLR_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK) - -#define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U) -#define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U) -/*! ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - */ -#define FLASH_INT_CLR_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK) - -#define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U) -#define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U) -/*! DONE - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - */ -#define FLASH_INT_CLR_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK) - -#define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U) -#define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - */ -#define FLASH_INT_CLR_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_SET_ENABLE - Set interrupt enable bits */ -/*! @{ */ - -#define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U) -#define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U) -/*! FAIL - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - */ -#define FLASH_INT_SET_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK) - -#define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U) -#define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U) -/*! ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - */ -#define FLASH_INT_SET_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK) - -#define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U) -#define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U) -/*! DONE - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - */ -#define FLASH_INT_SET_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK) - -#define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U) -#define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - */ -#define FLASH_INT_SET_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_STATUS - Interrupt status bits */ -/*! @{ */ - -#define FLASH_INT_STATUS_FAIL_MASK (0x1U) -#define FLASH_INT_STATUS_FAIL_SHIFT (0U) -/*! FAIL - This status bit is set if execution of a (legal) command failed. - */ -#define FLASH_INT_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK) - -#define FLASH_INT_STATUS_ERR_MASK (0x2U) -#define FLASH_INT_STATUS_ERR_SHIFT (1U) -/*! ERR - This status bit is set if execution of an illegal command is detected. - */ -#define FLASH_INT_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK) - -#define FLASH_INT_STATUS_DONE_MASK (0x4U) -#define FLASH_INT_STATUS_DONE_SHIFT (2U) -/*! DONE - This status bit is set at the end of command execution. - */ -#define FLASH_INT_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK) - -#define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U) -#define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested - * read, or a speculative read, or reads performed by a controller command), a correctable or - * uncorrectable error is detected by ECC decoding logic. - */ -#define FLASH_INT_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_ENABLE - Interrupt enable bits */ -/*! @{ */ - -#define FLASH_INT_ENABLE_FAIL_MASK (0x1U) -#define FLASH_INT_ENABLE_FAIL_SHIFT (0U) -/*! FAIL - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - */ -#define FLASH_INT_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK) - -#define FLASH_INT_ENABLE_ERR_MASK (0x2U) -#define FLASH_INT_ENABLE_ERR_SHIFT (1U) -/*! ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - */ -#define FLASH_INT_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK) - -#define FLASH_INT_ENABLE_DONE_MASK (0x4U) -#define FLASH_INT_ENABLE_DONE_SHIFT (2U) -/*! DONE - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - */ -#define FLASH_INT_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK) - -#define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U) -#define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - */ -#define FLASH_INT_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_CLR_STATUS - Clear interrupt status bits */ -/*! @{ */ - -#define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U) -#define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U) -/*! FAIL - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - */ -#define FLASH_INT_CLR_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK) - -#define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U) -#define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U) -/*! ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - */ -#define FLASH_INT_CLR_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK) - -#define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U) -#define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U) -/*! DONE - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - */ -#define FLASH_INT_CLR_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK) - -#define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U) -#define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - */ -#define FLASH_INT_CLR_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_SET_STATUS - Set interrupt status bits */ -/*! @{ */ - -#define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U) -#define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U) -/*! FAIL - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - */ -#define FLASH_INT_SET_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK) - -#define FLASH_INT_SET_STATUS_ERR_MASK (0x2U) -#define FLASH_INT_SET_STATUS_ERR_SHIFT (1U) -/*! ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - */ -#define FLASH_INT_SET_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK) - -#define FLASH_INT_SET_STATUS_DONE_MASK (0x4U) -#define FLASH_INT_SET_STATUS_DONE_SHIFT (2U) -/*! DONE - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - */ -#define FLASH_INT_SET_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK) - -#define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U) -#define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - */ -#define FLASH_INT_SET_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK) -/*! @} */ - -/*! @name MODULE_ID - Controller+Memory module identification */ -/*! @{ */ - -#define FLASH_MODULE_ID_APERTURE_MASK (0xFFU) -#define FLASH_MODULE_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture i. - */ -#define FLASH_MODULE_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK) - -#define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U) -#define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision i. - */ -#define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK) - -#define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U) -#define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision i. - */ -#define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK) - -#define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U) -#define FLASH_MODULE_ID_ID_SHIFT (16U) -/*! ID - Identifier. - */ -#define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLASH_Register_Masks */ - - -/* FLASH - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH base address */ - #define FLASH_BASE (0x50034000u) - /** Peripheral FLASH base address */ - #define FLASH_BASE_NS (0x40034000u) - /** Peripheral FLASH base pointer */ - #define FLASH ((FLASH_Type *)FLASH_BASE) - /** Peripheral FLASH base pointer */ - #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS) - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS { FLASH_BASE } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS { FLASH } - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS_NS { FLASH_NS } -#else - /** Peripheral FLASH base address */ - #define FLASH_BASE (0x40034000u) - /** Peripheral FLASH base pointer */ - #define FLASH ((FLASH_Type *)FLASH_BASE) - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS { FLASH_BASE } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS { FLASH } -#endif - -/*! - * @} - */ /* end of group FLASH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_CFPA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CFPA_Peripheral_Access_Layer FLASH_CFPA Peripheral Access Layer - * @{ - */ - -/** FLASH_CFPA - Register Layout Typedef */ -typedef struct { - __IO uint32_t HEADER; /**< , offset: 0x0 */ - __IO uint32_t VERSION; /**< , offset: 0x4 */ - __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */ - __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */ - __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */ - uint8_t RESERVED_0[4]; - __IO uint32_t ROTKH_REVOKE; /**< , offset: 0x18 */ - __IO uint32_t VENDOR_USAGE; /**< , offset: 0x1C */ - __IO uint32_t DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */ - __IO uint32_t DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */ - __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */ - __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */ - union { /* offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< , array offset: 0x30, array step: 0x4 */ - struct { /* offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< , offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< , offset: 0x34 */ - __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< , array offset: 0x38, array step: 0x4 */ - } PRINCE_REGION0_IV_CODE_CORE; - }; - union { /* offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< , array offset: 0x68, array step: 0x4 */ - struct { /* offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< , offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< , offset: 0x6C */ - __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< , array offset: 0x70, array step: 0x4 */ - } PRINCE_REGION1_IV_CODE_CORE; - }; - union { /* offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< , array offset: 0xA0, array step: 0x4 */ - struct { /* offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< , offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< , offset: 0xA4 */ - __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< , array offset: 0xA8, array step: 0x4 */ - } PRINCE_REGION2_IV_CODE_CORE; - }; - uint8_t RESERVED_1[40]; - __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ - __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ -} FLASH_CFPA_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_CFPA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CFPA_Register_Masks FLASH_CFPA Register Masks - * @{ - */ - -/*! @name HEADER - */ -/*! @{ */ - -#define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_HEADER_FIELD_SHIFT (0U) -#define FLASH_CFPA_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK) -/*! @} */ - -/*! @name VERSION - */ -/*! @{ */ - -#define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_VERSION_FIELD_SHIFT (0U) -#define FLASH_CFPA_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK) -/*! @} */ - -/*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */ -/*! @{ */ - -#define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U) -#define FLASH_CFPA_S_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK) -/*! @} */ - -/*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */ -/*! @{ */ - -#define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U) -#define FLASH_CFPA_NS_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK) -/*! @} */ - -/*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */ -/*! @{ */ - -#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U) -#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK) -/*! @} */ - -/*! @name ROTKH_REVOKE - */ -/*! @{ */ - -#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U) -/*! RoTK0_EN - RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK) - -#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U) -/*! RoTK1_EN - RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK) - -#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U) -/*! RoTK2_EN - RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK) - -#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK (0xC0U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT (6U) -/*! RoTK3_EN - RoT Key 3 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK) -/*! @} */ - -/*! @name VENDOR_USAGE - */ -/*! @{ */ - -#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU) -#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U) -/*! DBG_VENDOR_USAGE - DBG_VENDOR_USAGE. - */ -#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK) - -#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ -/*! @{ */ - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) -/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) -/*! FA_CMD_EN - FA Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) -/*! ME_CMD_EN - Flash Mass Erase Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) -/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) -/*! UUID_CHECK - Enforce UUID match during Debug authentication. - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ -/*! @{ */ - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) -/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) -/*! FA_CMD_EN - FA Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) -/*! ME_CMD_EN - Flash Mass Erase Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) -/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */ -/*! @{ */ - -#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK) -/*! @} */ - -/*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */ -/*! @{ */ - -#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U) -#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_IV_CODE - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */ -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U) - -/*! @name PRINCE_REGION0_IV_HEADER0 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_IV_HEADER1 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK) - -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK) - -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_IV_BODY - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */ -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U) - -/*! @name PRINCE_REGION1_IV_CODE - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */ -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U) - -/*! @name PRINCE_REGION1_IV_HEADER0 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_IV_HEADER1 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK) - -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK) - -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_IV_BODY - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */ -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U) - -/*! @name PRINCE_REGION2_IV_CODE - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */ -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U) - -/*! @name PRINCE_REGION2_IV_HEADER0 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_IV_HEADER1 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK) - -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK) - -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_IV_BODY - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION2_IV_BODY */ -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_COUNT (12U) - -/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ -/*! @{ */ - -#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) -#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_CUSTOMER_DEFINED */ -#define FLASH_CFPA_CUSTOMER_DEFINED_COUNT (56U) - -/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ -/*! @{ */ - -#define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U) -#define FLASH_CFPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_SHA256_DIGEST */ -#define FLASH_CFPA_SHA256_DIGEST_COUNT (8U) - - -/*! - * @} - */ /* end of group FLASH_CFPA_Register_Masks */ - - -/* FLASH_CFPA - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH_CFPA0 base address */ - #define FLASH_CFPA0_BASE (0x1009E000u) - /** Peripheral FLASH_CFPA0 base address */ - #define FLASH_CFPA0_BASE_NS (0x9E000u) - /** Peripheral FLASH_CFPA0 base pointer */ - #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) - /** Peripheral FLASH_CFPA0 base pointer */ - #define FLASH_CFPA0_NS ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS) - /** Peripheral FLASH_CFPA1 base address */ - #define FLASH_CFPA1_BASE (0x1009E200u) - /** Peripheral FLASH_CFPA1 base address */ - #define FLASH_CFPA1_BASE_NS (0x9E200u) - /** Peripheral FLASH_CFPA1 base pointer */ - #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) - /** Peripheral FLASH_CFPA1 base pointer */ - #define FLASH_CFPA1_NS ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS) - /** Peripheral FLASH_CFPA_SCRATCH base address */ - #define FLASH_CFPA_SCRATCH_BASE (0x1009DE00u) - /** Peripheral FLASH_CFPA_SCRATCH base address */ - #define FLASH_CFPA_SCRATCH_BASE_NS (0x9DE00u) - /** Peripheral FLASH_CFPA_SCRATCH base pointer */ - #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) - /** Peripheral FLASH_CFPA_SCRATCH base pointer */ - #define FLASH_CFPA_SCRATCH_NS ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS) - /** Array initializer of FLASH_CFPA peripheral base addresses */ - #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } - /** Array initializer of FLASH_CFPA peripheral base pointers */ - #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } - /** Array initializer of FLASH_CFPA peripheral base addresses */ - #define FLASH_CFPA_BASE_ADDRS_NS { FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS } - /** Array initializer of FLASH_CFPA peripheral base pointers */ - #define FLASH_CFPA_BASE_PTRS_NS { FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS } -#else - /** Peripheral FLASH_CFPA0 base address */ - #define FLASH_CFPA0_BASE (0x9E000u) - /** Peripheral FLASH_CFPA0 base pointer */ - #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) - /** Peripheral FLASH_CFPA1 base address */ - #define FLASH_CFPA1_BASE (0x9E200u) - /** Peripheral FLASH_CFPA1 base pointer */ - #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) - /** Peripheral FLASH_CFPA_SCRATCH base address */ - #define FLASH_CFPA_SCRATCH_BASE (0x9DE00u) - /** Peripheral FLASH_CFPA_SCRATCH base pointer */ - #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) - /** Array initializer of FLASH_CFPA peripheral base addresses */ - #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } - /** Array initializer of FLASH_CFPA peripheral base pointers */ - #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } -#endif - -/*! - * @} - */ /* end of group FLASH_CFPA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_CMPA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CMPA_Peripheral_Access_Layer FLASH_CMPA Peripheral Access Layer - * @{ - */ - -/** FLASH_CMPA - Register Layout Typedef */ -typedef struct { - __IO uint32_t BOOT_CFG; /**< , offset: 0x0 */ - __IO uint32_t SPI_FLASH_CFG; /**< , offset: 0x4 */ - __IO uint32_t USB_ID; /**< , offset: 0x8 */ - __IO uint32_t SDIO_CFG; /**< , offset: 0xC */ - __IO uint32_t CC_SOCU_PIN; /**< , offset: 0x10 */ - __IO uint32_t CC_SOCU_DFLT; /**< , offset: 0x14 */ - __IO uint32_t VENDOR_USAGE; /**< , offset: 0x18 */ - __IO uint32_t SECURE_BOOT_CFG; /**< Secure boot configuration flags., offset: 0x1C */ - __IO uint32_t PRINCE_BASE_ADDR; /**< , offset: 0x20 */ - __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */ - __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */ - __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */ - __IO uint32_t XTAL_32KHZ_CAPABANK_TRIM; /**< Xtal 32kHz capabank triming., offset: 0x30 */ - __IO uint32_t XTAL_16MHZ_CAPABANK_TRIM; /**< Xtal 16MHz capabank triming., offset: 0x34 */ - uint8_t RESERVED_0[24]; - __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */ - uint8_t RESERVED_1[144]; - __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ - __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ -} FLASH_CMPA_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_CMPA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CMPA_Register_Masks FLASH_CMPA Register Masks - * @{ - */ - -/*! @name BOOT_CFG - */ -/*! @{ */ - -#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U) -#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U) -/*! DEFAULT_ISP_MODE - Default ISP mode: - * 0b000..Auto ISP - * 0b001..USB_HID_ISP - * 0b010..UART ISP - * 0b011..SPI Slave ISP - * 0b100..I2C Slave ISP - * 0b111..Disable ISP fall through - */ -#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK) - -#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U) -#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U) -/*! BOOT_SPEED - Core clock: - * 0b00..Defined by NMPA.SYSTEM_SPEED_CODE - * 0b01..96MHz FRO - * 0b10..48MHz FRO - */ -#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK) - -#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U) -#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U) -/*! BOOT_FAILURE_PIN - GPIO port and pin number to use for indicating failure reason. The toggle - * rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO - * pin - */ -#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK) -/*! @} */ - -/*! @name SPI_FLASH_CFG - */ -/*! @{ */ - -#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK (0x1FU) -#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT (0U) -/*! SPI_RECOVERY_BOOT_EN - SPI flash recovery boot is enabled, if non-zero value is written to this field. - */ -#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK) -/*! @} */ - -/*! @name USB_ID - */ -/*! @{ */ - -#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU) -#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U) -#define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK) - -#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U) -#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U) -#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK) -/*! @} */ - -/*! @name SDIO_CFG - */ -/*! @{ */ - -#define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U) -#define FLASH_CMPA_SDIO_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK) -/*! @} */ - -/*! @name CC_SOCU_PIN - */ -/*! @{ */ - -#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK (0x1U) -#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK (0x2U) -#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) -#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK (0x8U) -#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK (0x10U) -#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) -#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) -/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) -#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) -/*! FA_CMD_EN - FA Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) -#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) -/*! ME_CMD_EN - Flash Mass Erase Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) -#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) -/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) -#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) -/*! UUID_CHECK - Enforce UUID match during Debug authentication. - */ -#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name CC_SOCU_DFLT - */ -/*! @{ */ - -#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK (0x1U) -#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK (0x2U) -#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) -#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) -#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK (0x10U) -#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) -#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) -/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) -#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) -/*! FA_CMD_EN - FA Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) -#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) -/*! ME_CMD_EN - Flash Mass Erase Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) -#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) -/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name VENDOR_USAGE - */ -/*! @{ */ - -#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK (0xFFFF0000U) -#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT (16U) -/*! VENDOR_USAGE - Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area. - */ -#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK) -/*! @} */ - -/*! @name SECURE_BOOT_CFG - Secure boot configuration flags. */ -/*! @{ */ - -#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U) -#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U) -/*! RSA4K - Use RSA4096 keys only. - * 0b00..Allow RSA2048 and higher - * 0b01..RSA4096 only - * 0b10..RSA4096 only - * 0b11..RSA4096 only - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK (0xCU) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT (2U) -/*! DICE_INC_NXP_CFG - Include NXP area in DICE computation. - * 0b00..not included - * 0b01..included - * 0b10..included - * 0b11..included - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U) -/*! DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. - * 0b00..not included - * 0b01..included - * 0b10..included - * 0b11..included - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U) -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U) -/*! SKIP_DICE - Skip DICE computation - * 0b00..Enable DICE - * 0b01..Disable DICE - * 0b10..Disable DICE - * 0b11..Disable DICE - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U) -#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U) -/*! TZM_IMAGE_TYPE - TrustZone-M mode - * 0b00..TZ-M image mode is taken from application image header - * 0b01..TZ-M disabled image, boots to non-secure mode - * 0b10..TZ-M enabled image, boots to secure mode - * 0b11..TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U) -/*! BLOCK_SET_KEY - Block PUF key code generation - * 0b00..Allow PUF Key Code generation - * 0b01..Disable PUF Key Code generation - * 0b10..Disable PUF Key Code generation - * 0b11..Disable PUF Key Code generation - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U) -/*! BLOCK_ENROLL - Block PUF enrollement - * 0b00..Allow PUF enroll operation - * 0b01..Disable PUF enroll operation - * 0b10..Disable PUF enroll operation - * 0b11..Disable PUF enroll operation - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK (0xC000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT (14U) -/*! DICE_INC_SEC_EPOCH - Include security EPOCH in DICE - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U) -/*! SEC_BOOT_EN - Secure boot enable - * 0b00..Plain image (internal flash with or without CRC) - * 0b01..Boot signed images. (internal flash, RSA signed) - * 0b10..Boot signed images. (internal flash, RSA signed) - * 0b11..Boot signed images. (internal flash, RSA signed) - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK) -/*! @} */ - -/*! @name PRINCE_BASE_ADDR - */ -/*! @{ */ - -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U) -/*! ADDR0_PRG - Programmable portion of the base address of region 0 - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U) -/*! ADDR1_PRG - Programmable portion of the base address of region 1 - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U) -/*! ADDR2_PRG - Programmable portion of the base address of region 2 - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0xC0000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (18U) -/*! LOCK_REG0 - Lock PRINCE region0 settings - * 0b00..Region is not locked - * 0b01..Region is locked - * 0b10..Region is locked - * 0b11..Region is locked - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0x300000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (20U) -/*! LOCK_REG1 - Lock PRINCE region1 settings - * 0b00..Region is not locked - * 0b01..Region is locked - * 0b10..Region is locked - * 0b11..Region is locked - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U) -/*! REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased together - * 0b00..Region is disabled - * 0b01..Region is enabled - * 0b10..Region is enabled - * 0b11..Region is enabled - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U) -/*! REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased together - * 0b00..Region is disabled - * 0b01..Region is enabled - * 0b10..Region is enabled - * 0b11..Region is enabled - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U) -/*! REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased together - * 0b00..Region is disabled - * 0b01..Region is enabled - * 0b10..Region is enabled - * 0b11..Region is enabled - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK) -/*! @} */ - -/*! @name PRINCE_SR_0 - Region 0, sub-region enable */ -/*! @{ */ - -#define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U) -#define FLASH_CMPA_PRINCE_SR_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_SR_1 - Region 1, sub-region enable */ -/*! @{ */ - -#define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U) -#define FLASH_CMPA_PRINCE_SR_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_SR_2 - Region 2, sub-region enable */ -/*! @{ */ - -#define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U) -#define FLASH_CMPA_PRINCE_SR_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK) -/*! @} */ - -/*! @name XTAL_32KHZ_CAPABANK_TRIM - Xtal 32kHz capabank triming. */ -/*! @{ */ - -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) -/*! TRIM_VALID - XTAL 32kHz capa bank trimmings - * 0b0..Capa Bank trimmings not valid. Default trimmings value are used - * 0b1..Capa Bank trimmings valid - */ -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK) - -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) -/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) - -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) -/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) - -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) -/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) -/*! @} */ - -/*! @name XTAL_16MHZ_CAPABANK_TRIM - Xtal 16MHz capabank triming. */ -/*! @{ */ - -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) -/*! TRIM_VALID - XTAL 16MHz capa bank trimmings - * 0b0..Capa Bank trimmings not valid. Default trimmings value are used - * 0b1..Capa Bank trimmings valid - */ -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK) - -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) -/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) - -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) -/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) - -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) -/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) -/*! @} */ - -/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0] */ -/*! @{ */ - -#define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U) -#define FLASH_CMPA_ROTKH_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CMPA_ROTKH */ -#define FLASH_CMPA_ROTKH_COUNT (8U) - -/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ -/*! @{ */ - -#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) -#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CMPA_CUSTOMER_DEFINED */ -#define FLASH_CMPA_CUSTOMER_DEFINED_COUNT (56U) - -/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ -/*! @{ */ - -#define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U) -#define FLASH_CMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CMPA_SHA256_DIGEST */ -#define FLASH_CMPA_SHA256_DIGEST_COUNT (8U) - - -/*! - * @} - */ /* end of group FLASH_CMPA_Register_Masks */ - - -/* FLASH_CMPA - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH_CMPA base address */ - #define FLASH_CMPA_BASE (0x1009E400u) - /** Peripheral FLASH_CMPA base address */ - #define FLASH_CMPA_BASE_NS (0x9E400u) - /** Peripheral FLASH_CMPA base pointer */ - #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) - /** Peripheral FLASH_CMPA base pointer */ - #define FLASH_CMPA_NS ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS) - /** Array initializer of FLASH_CMPA peripheral base addresses */ - #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } - /** Array initializer of FLASH_CMPA peripheral base pointers */ - #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } - /** Array initializer of FLASH_CMPA peripheral base addresses */ - #define FLASH_CMPA_BASE_ADDRS_NS { FLASH_CMPA_BASE_NS } - /** Array initializer of FLASH_CMPA peripheral base pointers */ - #define FLASH_CMPA_BASE_PTRS_NS { FLASH_CMPA_NS } -#else - /** Peripheral FLASH_CMPA base address */ - #define FLASH_CMPA_BASE (0x9E400u) - /** Peripheral FLASH_CMPA base pointer */ - #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) - /** Array initializer of FLASH_CMPA peripheral base addresses */ - #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } - /** Array initializer of FLASH_CMPA peripheral base pointers */ - #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } -#endif - -/*! - * @} - */ /* end of group FLASH_CMPA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_KEY_STORE Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_KEY_STORE_Peripheral_Access_Layer FLASH_KEY_STORE Peripheral Access Layer - * @{ - */ - -/** FLASH_KEY_STORE - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0 */ - __IO uint32_t HEADER; /**< Valid Key Sore Header : 0x95959595, offset: 0x0 */ - __IO uint32_t PUF_DISCHARGE_TIME_IN_MS; /**< puf discharge time in ms., offset: 0x4 */ - } KEY_STORE_HEADER; - __IO uint32_t ACTIVATION_CODE[298]; /**< ., array offset: 0x8, array step: 0x4 */ - union { /* offset: 0x4B0 */ - __IO uint32_t SBKEY_KEY_CODE[14]; /**< ., array offset: 0x4B0, array step: 0x4 */ - struct { /* offset: 0x4B0 */ - __IO uint32_t SBKEY_HEADER0; /**< ., offset: 0x4B0 */ - __IO uint32_t SBKEY_HEADER1; /**< ., offset: 0x4B4 */ - __IO uint32_t SBKEY_BODY[12]; /**< ., array offset: 0x4B8, array step: 0x4 */ - } SBKEY_KEY_CODE_CORE; - }; - union { /* offset: 0x4E8 */ - __IO uint32_t USER_KEK_KEY_CODE[14]; /**< ., array offset: 0x4E8, array step: 0x4 */ - struct { /* offset: 0x4E8 */ - __IO uint32_t USER_KEK_HEADER0; /**< ., offset: 0x4E8 */ - __IO uint32_t USER_KEK_HEADER1; /**< ., offset: 0x4EC */ - __IO uint32_t USER_KEK_BODY[12]; /**< ., array offset: 0x4F0, array step: 0x4 */ - } USER_KEK_KEY_CODE_CORE; - }; - union { /* offset: 0x520 */ - __IO uint32_t UDS_KEY_CODE[14]; /**< ., array offset: 0x520, array step: 0x4 */ - struct { /* offset: 0x520 */ - __IO uint32_t UDS_HEADER0; /**< ., offset: 0x520 */ - __IO uint32_t UDS_HEADER1; /**< ., offset: 0x524 */ - __IO uint32_t UDS_BODY[12]; /**< ., array offset: 0x528, array step: 0x4 */ - } UDS_KEY_CODE_CORE; - }; - union { /* offset: 0x558 */ - __IO uint32_t PRINCE_REGION0_KEY_CODE[14]; /**< ., array offset: 0x558, array step: 0x4 */ - struct { /* offset: 0x558 */ - __IO uint32_t PRINCE_REGION0_HEADER0; /**< ., offset: 0x558 */ - __IO uint32_t PRINCE_REGION0_HEADER1; /**< ., offset: 0x55C */ - __IO uint32_t PRINCE_REGION0_BODY[12]; /**< ., array offset: 0x560, array step: 0x4 */ - } PRINCE_REGION0_KEY_CODE_CORE; - }; - union { /* offset: 0x590 */ - __IO uint32_t PRINCE_REGION1_KEY_CODE[14]; /**< ., array offset: 0x590, array step: 0x4 */ - struct { /* offset: 0x590 */ - __IO uint32_t PRINCE_REGION1_HEADER0; /**< ., offset: 0x590 */ - __IO uint32_t PRINCE_REGION1_HEADER1; /**< ., offset: 0x594 */ - __IO uint32_t PRINCE_REGION1_BODY[12]; /**< ., array offset: 0x598, array step: 0x4 */ - } PRINCE_REGION1_KEY_CODE_CORE; - }; - union { /* offset: 0x5C8 */ - __IO uint32_t PRINCE_REGION2_KEY_CODE[14]; /**< ., array offset: 0x5C8, array step: 0x4 */ - struct { /* offset: 0x5C8 */ - __IO uint32_t PRINCE_REGION2_HEADER0; /**< ., offset: 0x5C8 */ - __IO uint32_t PRINCE_REGION2_HEADER1; /**< ., offset: 0x5CC */ - __IO uint32_t PRINCE_REGION2_BODY[12]; /**< ., array offset: 0x5D0, array step: 0x4 */ - } PRINCE_REGION2_KEY_CODE_CORE; - }; -} FLASH_KEY_STORE_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_KEY_STORE Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_KEY_STORE_Register_Masks FLASH_KEY_STORE Register Masks - * @{ - */ - -/*! @name HEADER - Valid Key Sore Header : 0x95959595 */ -/*! @{ */ - -#define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK) -/*! @} */ - -/*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */ -/*! @{ */ - -#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK) -/*! @} */ - -/*! @name ACTIVATION_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_ACTIVATION_CODE */ -#define FLASH_KEY_STORE_ACTIVATION_CODE_COUNT (298U) - -/*! @name SBKEY_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_SBKEY_KEY_CODE */ -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_COUNT (14U) - -/*! @name SBKEY_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name SBKEY_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name SBKEY_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_SBKEY_BODY */ -#define FLASH_KEY_STORE_SBKEY_BODY_COUNT (12U) - -/*! @name USER_KEK_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_USER_KEK_KEY_CODE */ -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_COUNT (14U) - -/*! @name USER_KEK_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name USER_KEK_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name USER_KEK_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_USER_KEK_BODY */ -#define FLASH_KEY_STORE_USER_KEK_BODY_COUNT (12U) - -/*! @name UDS_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_UDS_KEY_CODE */ -#define FLASH_KEY_STORE_UDS_KEY_CODE_COUNT (14U) - -/*! @name UDS_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name UDS_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name UDS_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_UDS_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_UDS_BODY */ -#define FLASH_KEY_STORE_UDS_BODY_COUNT (12U) - -/*! @name PRINCE_REGION0_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE */ -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_COUNT (14U) - -/*! @name PRINCE_REGION0_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION0_BODY */ -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_COUNT (12U) - -/*! @name PRINCE_REGION1_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE */ -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_COUNT (14U) - -/*! @name PRINCE_REGION1_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION1_BODY */ -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_COUNT (12U) - -/*! @name PRINCE_REGION2_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE */ -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_COUNT (14U) - -/*! @name PRINCE_REGION2_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION2_BODY */ -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_COUNT (12U) - - -/*! - * @} - */ /* end of group FLASH_KEY_STORE_Register_Masks */ - - -/* FLASH_KEY_STORE - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH_KEY_STORE base address */ - #define FLASH_KEY_STORE_BASE (0x1009E600u) - /** Peripheral FLASH_KEY_STORE base address */ - #define FLASH_KEY_STORE_BASE_NS (0x9E600u) - /** Peripheral FLASH_KEY_STORE base pointer */ - #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) - /** Peripheral FLASH_KEY_STORE base pointer */ - #define FLASH_KEY_STORE_NS ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS) - /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ - #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } - /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ - #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } - /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ - #define FLASH_KEY_STORE_BASE_ADDRS_NS { FLASH_KEY_STORE_BASE_NS } - /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ - #define FLASH_KEY_STORE_BASE_PTRS_NS { FLASH_KEY_STORE_NS } -#else - /** Peripheral FLASH_KEY_STORE base address */ - #define FLASH_KEY_STORE_BASE (0x9E600u) - /** Peripheral FLASH_KEY_STORE base pointer */ - #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) - /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ - #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } - /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ - #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } -#endif - -/*! - * @} - */ /* end of group FLASH_KEY_STORE_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer - * @{ - */ - -/** FLEXCOMM - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4088]; - __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ - __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ -} FLEXCOMM_Type; - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks - * @{ - */ - -/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ -/*! @{ */ - -#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) -#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) -/*! PERSEL - Peripheral Select. This field is writable by software. - * 0b000..No peripheral selected. - * 0b001..USART function selected. - * 0b010..SPI function selected. - * 0b011..I2C function selected. - * 0b100..I2S transmit function selected. - * 0b101..I2S receive function selected. - * 0b110..Reserved - * 0b111..Reserved - */ -#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) - -#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) -#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) -/*! LOCK - Lock the peripheral select. This field is writable by software. - * 0b0..Peripheral select can be changed by software. - * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. - */ -#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) - -#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) -#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) -/*! USARTPRESENT - USART present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the USART function. - * 0b1..This Flexcomm includes the USART function. - */ -#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) - -#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) -#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) -/*! SPIPRESENT - SPI present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the SPI function. - * 0b1..This Flexcomm includes the SPI function. - */ -#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) - -#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) -#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) -/*! I2CPRESENT - I2C present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the I2C function. - * 0b1..This Flexcomm includes the I2C function. - */ -#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) - -#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) -#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) -/*! I2SPRESENT - I 2S present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the I2S function. - * 0b1..This Flexcomm includes the I2S function. - */ -#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) - -#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) -#define FLEXCOMM_PSELID_ID_SHIFT (12U) -/*! ID - Flexcomm ID. - */ -#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) -/*! @} */ - -/*! @name PID - Peripheral identification register. */ -/*! @{ */ - -#define FLEXCOMM_PID_APERTURE_MASK (0xFFU) -#define FLEXCOMM_PID_APERTURE_SHIFT (0U) -/*! APERTURE - size aperture for the register port on the bus (APB or AHB). - */ -#define FLEXCOMM_PID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_APERTURE_SHIFT)) & FLEXCOMM_PID_APERTURE_MASK) - -#define FLEXCOMM_PID_MINOR_REV_MASK (0xF00U) -#define FLEXCOMM_PID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation. - */ -#define FLEXCOMM_PID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MINOR_REV_SHIFT)) & FLEXCOMM_PID_MINOR_REV_MASK) - -#define FLEXCOMM_PID_MAJOR_REV_MASK (0xF000U) -#define FLEXCOMM_PID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation. - */ -#define FLEXCOMM_PID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MAJOR_REV_SHIFT)) & FLEXCOMM_PID_MAJOR_REV_MASK) - -#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) -#define FLEXCOMM_PID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function. - */ -#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLEXCOMM_Register_Masks */ - - -/* FLEXCOMM - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE (0x50086000u) - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE_NS (0x40086000u) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE (0x50087000u) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE_NS (0x40087000u) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE (0x50088000u) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE_NS (0x40088000u) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE (0x50089000u) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE_NS (0x40089000u) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE (0x5008A000u) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE_NS (0x4008A000u) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE (0x50096000u) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE_NS (0x40096000u) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE (0x50097000u) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE_NS (0x40097000u) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE (0x50098000u) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE_NS (0x40098000u) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE (0x5009F000u) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE_NS (0x4009F000u) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS) - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS_NS { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS_NS { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS } -#else - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE (0x40086000u) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE (0x40087000u) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE (0x40088000u) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE (0x40089000u) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE (0x4008A000u) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE (0x40096000u) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE (0x40097000u) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE (0x40098000u) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE (0x4009F000u) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } -#endif -/** Interrupt vectors for the FLEXCOMM peripheral type */ -#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } - -/*! - * @} - */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer - * @{ - */ - -/** GINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ - uint8_t RESERVED_0[28]; - __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[24]; - __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ -} GINT_Type; - -/* ---------------------------------------------------------------------------- - -- GINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Register_Masks GINT Register Masks - * @{ - */ - -/*! @name CTRL - GPIO grouped interrupt control register */ -/*! @{ */ - -#define GINT_CTRL_INT_MASK (0x1U) -#define GINT_CTRL_INT_SHIFT (0U) -/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. - * 0b0..No request. No interrupt request is pending. - * 0b1..Request active. Interrupt request is active. - */ -#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) - -#define GINT_CTRL_COMB_MASK (0x2U) -#define GINT_CTRL_COMB_SHIFT (1U) -/*! COMB - Combine enabled inputs for group interrupt - * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). - * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). - */ -#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) - -#define GINT_CTRL_TRIG_MASK (0x4U) -#define GINT_CTRL_TRIG_SHIFT (2U) -/*! TRIG - Group interrupt trigger - * 0b0..Edge-triggered. - * 0b1..Level-triggered. - */ -#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) -/*! @} */ - -/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ -/*! @{ */ - -#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) -#define GINT_PORT_POL_POL_SHIFT (0U) -/*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n - * of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to - * the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin - * contributes to the group interrupt. - */ -#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) -/*! @} */ - -/* The count of GINT_PORT_POL */ -#define GINT_PORT_POL_COUNT (2U) - -/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ -/*! @{ */ - -#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) -#define GINT_PORT_ENA_ENA_SHIFT (0U) -/*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the - * port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is - * enabled and contributes to the grouped interrupt. - */ -#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) -/*! @} */ - -/* The count of GINT_PORT_ENA */ -#define GINT_PORT_ENA_COUNT (2U) - - -/*! - * @} - */ /* end of group GINT_Register_Masks */ - - -/* GINT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral GINT0 base address */ - #define GINT0_BASE (0x50002000u) - /** Peripheral GINT0 base address */ - #define GINT0_BASE_NS (0x40002000u) - /** Peripheral GINT0 base pointer */ - #define GINT0 ((GINT_Type *)GINT0_BASE) - /** Peripheral GINT0 base pointer */ - #define GINT0_NS ((GINT_Type *)GINT0_BASE_NS) - /** Peripheral GINT1 base address */ - #define GINT1_BASE (0x50003000u) - /** Peripheral GINT1 base address */ - #define GINT1_BASE_NS (0x40003000u) - /** Peripheral GINT1 base pointer */ - #define GINT1 ((GINT_Type *)GINT1_BASE) - /** Peripheral GINT1 base pointer */ - #define GINT1_NS ((GINT_Type *)GINT1_BASE_NS) - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS { GINT0, GINT1 } - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS_NS { GINT0_BASE_NS, GINT1_BASE_NS } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS_NS { GINT0_NS, GINT1_NS } -#else - /** Peripheral GINT0 base address */ - #define GINT0_BASE (0x40002000u) - /** Peripheral GINT0 base pointer */ - #define GINT0 ((GINT_Type *)GINT0_BASE) - /** Peripheral GINT1 base address */ - #define GINT1_BASE (0x40003000u) - /** Peripheral GINT1 base pointer */ - #define GINT1 ((GINT_Type *)GINT1_BASE) - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS { GINT0, GINT1 } -#endif -/** Interrupt vectors for the GINT peripheral type */ -#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } - -/*! - * @} - */ /* end of group GINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer - * @{ - */ - -/** GPIO - Register Layout Typedef */ -typedef struct { - __IO uint8_t B[2][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ - uint8_t RESERVED_0[4032]; - __IO uint32_t W[2][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ - uint8_t RESERVED_1[3840]; - __IO uint32_t DIR[2]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */ - uint8_t RESERVED_2[120]; - __IO uint32_t MASK[2]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */ - uint8_t RESERVED_3[120]; - __IO uint32_t PIN[2]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */ - uint8_t RESERVED_4[120]; - __IO uint32_t MPIN[2]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */ - uint8_t RESERVED_5[120]; - __IO uint32_t SET[2]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */ - uint8_t RESERVED_6[120]; - __O uint32_t CLR[2]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */ - uint8_t RESERVED_7[120]; - __O uint32_t NOT[2]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */ - uint8_t RESERVED_8[120]; - __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ - uint8_t RESERVED_9[120]; - __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ - uint8_t RESERVED_10[120]; - __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ -} GPIO_Type; - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/*! @name B - Byte pin registers for all port GPIO pins */ -/*! @{ */ - -#define GPIO_B_PBYTE_MASK (0x1U) -#define GPIO_B_PBYTE_SHIFT (0U) -/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, - * except that pins configured as analog I/O always read as 0. One register for each port pin. - * Supported pins depends on the specific device and package. Write: loads the pin's output bit. - * One register for each port pin. Supported pins depends on the specific device and package. - */ -#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) -/*! @} */ - -/* The count of GPIO_B */ -#define GPIO_B_COUNT (2U) - -/* The count of GPIO_B */ -#define GPIO_B_COUNT2 (32U) - -/*! @name W - Word pin registers for all port GPIO pins */ -/*! @{ */ - -#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) -#define GPIO_W_PWORD_SHIFT (0U) -/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is - * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be - * read. Writing any value other than 0 will set the output bit. One register for each port pin. - * Supported pins depends on the specific device and package. - */ -#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) -/*! @} */ - -/* The count of GPIO_W */ -#define GPIO_W_COUNT (2U) - -/* The count of GPIO_W */ -#define GPIO_W_COUNT2 (32U) - -/*! @name DIR - Direction registers for all port GPIO pins */ -/*! @{ */ - -#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) -#define GPIO_DIR_DIRP_SHIFT (0U) -/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported - * pins depends on the specific device and package. 0 = input. 1 = output. - */ -#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) -/*! @} */ - -/* The count of GPIO_DIR */ -#define GPIO_DIR_COUNT (2U) - -/*! @name MASK - Mask register for all port GPIO pins */ -/*! @{ */ - -#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) -#define GPIO_MASK_MASKP_SHIFT (0U) -/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = - * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = - * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit - * not affected. - */ -#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) -/*! @} */ - -/* The count of GPIO_MASK */ -#define GPIO_MASK_COUNT (2U) - -/*! @name PIN - Port pin register for all port GPIO pins */ -/*! @{ */ - -#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) -#define GPIO_PIN_PORT_SHIFT (0U) -/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported - * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. - * 1 = Read: pin is high; write: set output bit. - */ -#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) -/*! @} */ - -/* The count of GPIO_PIN */ -#define GPIO_PIN_COUNT (2U) - -/*! @name MPIN - Masked port register for all port GPIO pins */ -/*! @{ */ - -#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) -#define GPIO_MPIN_MPORTP_SHIFT (0U) -/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on - * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK - * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 - * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit - * if the corresponding bit in the MASK register is 0. - */ -#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) -/*! @} */ - -/* The count of GPIO_MPIN */ -#define GPIO_MPIN_COUNT (2U) - -/*! @name SET - Write: Set register for port. Read: output bits for port */ -/*! @{ */ - -#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) -#define GPIO_SET_SETP_SHIFT (0U) -/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on - * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output - * bit; write: set output bit. - */ -#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) -/*! @} */ - -/* The count of GPIO_SET */ -#define GPIO_SET_COUNT (2U) - -/*! @name CLR - Clear port for all port GPIO pins */ -/*! @{ */ - -#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) -#define GPIO_CLR_CLRP_SHIFT (0U) -/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the - * specific device and package. 0 = No operation. 1 = Clear output bit. - */ -#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) -/*! @} */ - -/* The count of GPIO_CLR */ -#define GPIO_CLR_COUNT (2U) - -/*! @name NOT - Toggle port for all port GPIO pins */ -/*! @{ */ - -#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) -#define GPIO_NOT_NOTP_SHIFT (0U) -/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the - * specific device and package. 0 = no operation. 1 = Toggle output bit. - */ -#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) -/*! @} */ - -/* The count of GPIO_NOT */ -#define GPIO_NOT_COUNT (2U) - -/*! @name DIRSET - Set pin direction bits for port */ -/*! @{ */ - -#define GPIO_DIRSET_DIRSETP_MASK (0xFFFFFFFFU) -#define GPIO_DIRSET_DIRSETP_SHIFT (0U) -/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on - * the specific device and package. 0 = No operation. 1 = Set direction bit. - */ -#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) -/*! @} */ - -/* The count of GPIO_DIRSET */ -#define GPIO_DIRSET_COUNT (2U) - -/*! @name DIRCLR - Clear pin direction bits for port */ -/*! @{ */ - -#define GPIO_DIRCLR_DIRCLRP_MASK (0xFFFFFFFFU) -#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) -/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on - * the specific device and package. 0 = No operation. 1 = Clear direction bit. - */ -#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) -/*! @} */ - -/* The count of GPIO_DIRCLR */ -#define GPIO_DIRCLR_COUNT (2U) - -/*! @name DIRNOT - Toggle pin direction bits for port */ -/*! @{ */ - -#define GPIO_DIRNOT_DIRNOTP_MASK (0xFFFFFFFFU) -#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) -/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends - * on the specific device and package. 0 = no operation. 1 = Toggle direction bit. - */ -#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) -/*! @} */ - -/* The count of GPIO_DIRNOT */ -#define GPIO_DIRNOT_COUNT (2U) - - -/*! - * @} - */ /* end of group GPIO_Register_Masks */ - - -/* GPIO - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral GPIO base address */ - #define GPIO_BASE (0x5008C000u) - /** Peripheral GPIO base address */ - #define GPIO_BASE_NS (0x4008C000u) - /** Peripheral GPIO base pointer */ - #define GPIO ((GPIO_Type *)GPIO_BASE) - /** Peripheral GPIO base pointer */ - #define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE (0x500A8000u) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE_NS (0x400A8000u) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS) - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO, SECGPIO } - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS_NS { GPIO_BASE_NS, SECGPIO_BASE_NS } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS_NS { GPIO_NS, SECGPIO_NS } -#else - /** Peripheral GPIO base address */ - #define GPIO_BASE (0x4008C000u) - /** Peripheral GPIO base pointer */ - #define GPIO ((GPIO_Type *)GPIO_BASE) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE (0x400A8000u) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO, SECGPIO } -#endif - -/*! - * @} - */ /* end of group GPIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- HASHCRYPT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup HASHCRYPT_Peripheral_Access_Layer HASHCRYPT Peripheral Access Layer - * @{ - */ - -/** HASHCRYPT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register to enable and operate Hash and Crypto, offset: 0x0 */ - __IO uint32_t STATUS; /**< Indicates status of Hash peripheral., offset: 0x4 */ - __IO uint32_t INTENSET; /**< Write 1 to enable interrupts; reads back with which are set., offset: 0x8 */ - __IO uint32_t INTENCLR; /**< Write 1 to clear interrupts., offset: 0xC */ - __IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available), offset: 0x10 */ - __IO uint32_t MEMADDR; /**< Address to start memory access from (if available)., offset: 0x14 */ - uint8_t RESERVED_0[8]; - __O uint32_t INDATA; /**< Input of 16 words at a time to load up buffer., offset: 0x20 */ - __O uint32_t ALIAS[7]; /**< , array offset: 0x24, array step: 0x4 */ - __I uint32_t DIGEST0[8]; /**< , array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_1[32]; - __IO uint32_t CRYPTCFG; /**< Crypto settings for AES and Salsa and ChaCha, offset: 0x80 */ - __I uint32_t CONFIG; /**< Returns the configuration of this block in this chip - indicates what services are available., offset: 0x84 */ - uint8_t RESERVED_2[4]; - __IO uint32_t LOCK; /**< Lock register allows locking to the current security level or unlocking by the lock holding level., offset: 0x8C */ - __O uint32_t MASK[4]; /**< , array offset: 0x90, array step: 0x4 */ -} HASHCRYPT_Type; - -/* ---------------------------------------------------------------------------- - -- HASHCRYPT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup HASHCRYPT_Register_Masks HASHCRYPT Register Masks - * @{ - */ - -/*! @name CTRL - Control register to enable and operate Hash and Crypto */ -/*! @{ */ - -#define HASHCRYPT_CTRL_MODE_MASK (0x7U) -#define HASHCRYPT_CTRL_MODE_SHIFT (0U) -/*! Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if - * specific modes beyond SHA1 and SHA2-256 are available. - * 0b000..Disabled - * 0b001..SHA1 is enabled - * 0b010..SHA2-256 is enabled - * 0b100..AES if available (see also CRYPTCFG register for more controls) - * 0b101..ICB-AES if available (see also CRYPTCFG register for more controls) - */ -#define HASHCRYPT_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK) - -#define HASHCRYPT_CTRL_NEW_HASH_MASK (0x10U) -#define HASHCRYPT_CTRL_NEW_HASH_SHIFT (4U) -/*! New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING - * Status bit will clear for a cycle during the initialization from New=1. - * 0b1..Starts a new Hash/Crypto and initializes the Digest/Result. - */ -#define HASHCRYPT_CTRL_NEW_HASH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK) - -#define HASHCRYPT_CTRL_DMA_I_MASK (0x100U) -#define HASHCRYPT_CTRL_DMA_I_SHIFT (8U) -/*! DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words - * and then will process the Hash. If Cryptographic, it will load as many words as needed, - * including key if not already loaded. It will then request again. Normal model is that the DMA - * interrupts the processor when its length expires. Note that if the processor will write the key and - * optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be - * expected to load those for the 1st block (when needed). - * 0b0..DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used. - * 0b1..DMA will push in the data. - */ -#define HASHCRYPT_CTRL_DMA_I(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK) - -#define HASHCRYPT_CTRL_DMA_O_MASK (0x200U) -#define HASHCRYPT_CTRL_DMA_O_SHIFT (9U) -/*! DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the - * DMA has to know to switch direction and the locations. This can be used for crypto uses. - * 0b0..DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. - */ -#define HASHCRYPT_CTRL_DMA_O(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK) - -#define HASHCRYPT_CTRL_HASHSWPB_MASK (0x1000U) -#define HASHCRYPT_CTRL_HASHSWPB_SHIFT (12U) -/*! HASHSWPB - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB - * is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For - * cryptographic swapping, see the CRYPTCFG register. - */ -#define HASHCRYPT_CTRL_HASHSWPB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK) -/*! @} */ - -/*! @name STATUS - Indicates status of Hash peripheral. */ -/*! @{ */ - -#define HASHCRYPT_STATUS_WAITING_MASK (0x1U) -#define HASHCRYPT_STATUS_WAITING_SHIFT (0U) -/*! WAITING - If 1, the block is waiting for more data to process. - * 0b0..Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set - * if IsLast is set nor will it set until at least 1 word is read of the output. - * 0b1..Waiting for data to be written in (16 words) - */ -#define HASHCRYPT_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK) - -#define HASHCRYPT_STATUS_DIGEST_MASK (0x2U) -#define HASHCRYPT_STATUS_DIGEST_SHIFT (1U) -/*! DIGEST - For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block - * already started. For Cryptographic uses, this will be set for each block processed, indicating - * OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared - * when any data is written, when New is written, for Cryptographic uses when the last word is read - * out, or when the block is disabled. - * 0b0..No Digest is ready - * 0b1..Digest is ready. Application may read it or may write more data - */ -#define HASHCRYPT_STATUS_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_SHIFT)) & HASHCRYPT_STATUS_DIGEST_MASK) - -#define HASHCRYPT_STATUS_ERROR_MASK (0x4U) -#define HASHCRYPT_STATUS_ERROR_SHIFT (2U) -/*! ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA - * was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT - * field will indicate which block it was on. - * 0b0..No error. - * 0b1..An error occurred since last cleared (written 1 to clear). - */ -#define HASHCRYPT_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK) - -#define HASHCRYPT_STATUS_NEEDKEY_MASK (0x10U) -#define HASHCRYPT_STATUS_NEEDKEY_SHIFT (4U) -/*! NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING) - * 0b0..No Key is needed and writes will not be treated as Key - * 0b1..Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. - */ -#define HASHCRYPT_STATUS_NEEDKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK) - -#define HASHCRYPT_STATUS_NEEDIV_MASK (0x20U) -#define HASHCRYPT_STATUS_NEEDIV_SHIFT (5U) -/*! NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING) - * 0b0..No IV/Nonce is needed, either because written already or because not needed. - * 0b1..IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. - */ -#define HASHCRYPT_STATUS_NEEDIV(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK) - -#define HASHCRYPT_STATUS_ICBIDX_MASK (0x3F0000U) -#define HASHCRYPT_STATUS_ICBIDX_SHIFT (16U) -/*! ICBIDX - If ICB-AES is selected, then reads as the ICB index count based on ICBSTRM (from - * CRYPTCFG). That is, if 3 bits of ICBSTRM, then this will count from 0 to 7 and then back to 0. On 0, - * it has to compute the full ICB, quicker when not 0. - */ -#define HASHCRYPT_STATUS_ICBIDX(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ICBIDX_SHIFT)) & HASHCRYPT_STATUS_ICBIDX_MASK) -/*! @} */ - -/*! @name INTENSET - Write 1 to enable interrupts; reads back with which are set. */ -/*! @{ */ - -#define HASHCRYPT_INTENSET_WAITING_MASK (0x1U) -#define HASHCRYPT_INTENSET_WAITING_SHIFT (0U) -/*! WAITING - Indicates if should interrupt when waiting for data input. - * 0b0..Will not interrupt when waiting. - * 0b1..Will interrupt when waiting - */ -#define HASHCRYPT_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK) - -#define HASHCRYPT_INTENSET_DIGEST_MASK (0x2U) -#define HASHCRYPT_INTENSET_DIGEST_SHIFT (1U) -/*! DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). - * 0b0..Will not interrupt when Digest is ready - * 0b1..Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). - */ -#define HASHCRYPT_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK) - -#define HASHCRYPT_INTENSET_ERROR_MASK (0x4U) -#define HASHCRYPT_INTENSET_ERROR_SHIFT (2U) -/*! ERROR - Indicates if should interrupt on an ERROR (as defined in Status) - * 0b0..Will not interrupt on Error. - * 0b1..Will interrupt on Error (until cleared). - */ -#define HASHCRYPT_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_ERROR_SHIFT)) & HASHCRYPT_INTENSET_ERROR_MASK) -/*! @} */ - -/*! @name INTENCLR - Write 1 to clear interrupts. */ -/*! @{ */ - -#define HASHCRYPT_INTENCLR_WAITING_MASK (0x1U) -#define HASHCRYPT_INTENCLR_WAITING_SHIFT (0U) -/*! WAITING - Write 1 to clear mask. - */ -#define HASHCRYPT_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK) - -#define HASHCRYPT_INTENCLR_DIGEST_MASK (0x2U) -#define HASHCRYPT_INTENCLR_DIGEST_SHIFT (1U) -/*! DIGEST - Write 1 to clear mask. - */ -#define HASHCRYPT_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK) - -#define HASHCRYPT_INTENCLR_ERROR_MASK (0x4U) -#define HASHCRYPT_INTENCLR_ERROR_SHIFT (2U) -/*! ERROR - Write 1 to clear mask. - */ -#define HASHCRYPT_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK) -/*! @} */ - -/*! @name MEMCTRL - Setup Master to access memory (if available) */ -/*! @{ */ - -#define HASHCRYPT_MEMCTRL_MASTER_MASK (0x1U) -#define HASHCRYPT_MEMCTRL_MASTER_SHIFT (0U) -/*! MASTER - Enables mastering. - * 0b0..Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. - * 0b1..Mastering is enabled and DMA and INDATA should not be used. - */ -#define HASHCRYPT_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK) - -#define HASHCRYPT_MEMCTRL_COUNT_MASK (0x7FF0000U) -#define HASHCRYPT_MEMCTRL_COUNT_SHIFT (16U) -/*! COUNT - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks - * to copy starting at MEMADDR. This register will decrement after each block is copied, ending - * in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA - * interrupt will occur on ever block. If a bus error occurs, it will stop with this field set - * to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) - * blocks to hash. - */ -#define HASHCRYPT_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK) -/*! @} */ - -/*! @name MEMADDR - Address to start memory access from (if available). */ -/*! @{ */ - -#define HASHCRYPT_MEMADDR_BASE_MASK (0xFFFFFFFFU) -#define HASHCRYPT_MEMADDR_BASE_SHIFT (0U) -/*! BASE - Address base to start copying from, word aligned (so bits 1:0 must be 0). This field will - * advance as it processes the words. If it fails with a bus error, the register will contain - * the failing word. N:Address in Flash or RAM space; RAM only as mapped in this part. May also be - * able to address SPIFI. - */ -#define HASHCRYPT_MEMADDR_BASE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK) -/*! @} */ - -/*! @name INDATA - Input of 16 words at a time to load up buffer. */ -/*! @{ */ - -#define HASHCRYPT_INDATA_DATA_MASK (0xFFFFFFFFU) -#define HASHCRYPT_INDATA_DATA_SHIFT (0U) -/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this - * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as - * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block - * will swap the word to restore into big endian. - */ -#define HASHCRYPT_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK) -/*! @} */ - -/*! @name ALIAS - */ -/*! @{ */ - -#define HASHCRYPT_ALIAS_DATA_MASK (0xFFFFFFFFU) -#define HASHCRYPT_ALIAS_DATA_SHIFT (0U) -/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this - * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as - * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block - * will swap the word to restore into big endian. - */ -#define HASHCRYPT_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK) -/*! @} */ - -/* The count of HASHCRYPT_ALIAS */ -#define HASHCRYPT_ALIAS_COUNT (7U) - -/*! @name DIGEST0 - */ -/*! @{ */ - -#define HASHCRYPT_DIGEST0_DIGEST_MASK (0xFFFFFFFFU) -#define HASHCRYPT_DIGEST0_DIGEST_SHIFT (0U) -/*! DIGEST - One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1. - */ -#define HASHCRYPT_DIGEST0_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_DIGEST0_DIGEST_SHIFT)) & HASHCRYPT_DIGEST0_DIGEST_MASK) -/*! @} */ - -/* The count of HASHCRYPT_DIGEST0 */ -#define HASHCRYPT_DIGEST0_COUNT (8U) - -/*! @name CRYPTCFG - Crypto settings for AES and Salsa and ChaCha */ -/*! @{ */ - -#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK (0x1U) -#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT (0U) -/*! MSW1ST_OUT - If 1, OUTDATA0 will be read Most significant word 1st for AES. Else it will be read - * in normal little endian - Least significant word 1st. Note: only if allowed by configuration. - */ -#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK) - -#define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK (0x2U) -#define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT (1U) -/*! SWAPKEY - If 1, will Swap the key input (bytes in each word). - */ -#define HASHCRYPT_CRYPTCFG_SWAPKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK) - -#define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK (0x4U) -#define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT (2U) -/*! SWAPDAT - If 1, will SWAP the data and IV inputs (bytes in each word). - */ -#define HASHCRYPT_CRYPTCFG_SWAPDAT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK) - -#define HASHCRYPT_CRYPTCFG_MSW1ST_MASK (0x8U) -#define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT (3U) -/*! MSW1ST - If 1, load of key, IV, and data is MSW 1st for AES. Else, the words are little endian. - * Note: only if allowed by configuration. - */ -#define HASHCRYPT_CRYPTCFG_MSW1ST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK) - -#define HASHCRYPT_CRYPTCFG_AESMODE_MASK (0x30U) -#define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT (4U) -/*! AESMODE - AES Cipher mode to use if plain AES - * 0b00..ECB - used as is - * 0b01..CBC mode (see details on IV/nonce) - * 0b10..CTR mode (see details on IV/nonce). See also AESCTRPOS. - * 0b11..reserved - */ -#define HASHCRYPT_CRYPTCFG_AESMODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK) - -#define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK (0x40U) -#define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT (6U) -/*! AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB - * 0b0..Encrypt - * 0b1..Decrypt - */ -#define HASHCRYPT_CRYPTCFG_AESDECRYPT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK) - -#define HASHCRYPT_CRYPTCFG_AESSECRET_MASK (0x80U) -#define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT (7U) -/*! AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are - * used, only the highest level is permitted to select this. - * 0b0..User key provided in normal way - * 0b1..Secret key provided in hidden way by HW - */ -#define HASHCRYPT_CRYPTCFG_AESSECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK) - -#define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK (0x300U) -#define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT (8U) -/*! AESKEYSZ - Sets the AES key size - * 0b00..128 bit key - * 0b01..192 bit key - * 0b10..256 bit key - * 0b11..reserved - */ -#define HASHCRYPT_CRYPTCFG_AESKEYSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK) - -#define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK (0x1C00U) -#define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT (10U) -/*! AESCTRPOS - Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for - * Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if - * using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other - * use CTR should use ECB directly and do its own XOR and so on. - */ -#define HASHCRYPT_CRYPTCFG_AESCTRPOS(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK) - -#define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK (0x10000U) -#define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT (16U) -/*! STREAMLAST - Is 1 if last stream block. If not 1, then the engine will compute the next "hash". - */ -#define HASHCRYPT_CRYPTCFG_STREAMLAST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK) - -#define HASHCRYPT_CRYPTCFG_ICBSZ_MASK (0x300000U) -#define HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT (20U) -/*! ICBSZ - This sets the ICB size between 32 and 128 bits, using the following rules. Note that the - * counter is assumed to occupy the low order bits of the IV. - * 0b00..32 bits of the IV/ctr are used (from 127:96) - * 0b01..64 bits of the IV/ctr are used (from 127:64) - * 0b10..96 bits of the IV/ctr are used (from 127:32) - * 0b11..All 128 bits of the IV/ctr are used - */ -#define HASHCRYPT_CRYPTCFG_ICBSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSZ_MASK) - -#define HASHCRYPT_CRYPTCFG_ICBSTRM_MASK (0xC00000U) -#define HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT (22U) -/*! ICBSTRM - The size of the ICB-AES stream that can be pushed before needing to compute a new - * IV/ctr (counter start). This optimizes the performance of the stream of blocks after the 1st. - * 0b00..8 blocks - * 0b01..16 blocks - * 0b10..32 blocks - * 0b11..64 blocks - */ -#define HASHCRYPT_CRYPTCFG_ICBSTRM(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSTRM_MASK) -/*! @} */ - -/*! @name CONFIG - Returns the configuration of this block in this chip - indicates what services are available. */ -/*! @{ */ - -#define HASHCRYPT_CONFIG_DUAL_MASK (0x1U) -#define HASHCRYPT_CONFIG_DUAL_SHIFT (0U) -/*! DUAL - 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit - */ -#define HASHCRYPT_CONFIG_DUAL(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK) - -#define HASHCRYPT_CONFIG_DMA_MASK (0x2U) -#define HASHCRYPT_CONFIG_DMA_SHIFT (1U) -/*! DMA - 1 if DMA is connected - */ -#define HASHCRYPT_CONFIG_DMA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK) - -#define HASHCRYPT_CONFIG_AHB_MASK (0x8U) -#define HASHCRYPT_CONFIG_AHB_SHIFT (3U) -/*! AHB - 1 if AHB Master is enabled - */ -#define HASHCRYPT_CONFIG_AHB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK) - -#define HASHCRYPT_CONFIG_AES_MASK (0x40U) -#define HASHCRYPT_CONFIG_AES_SHIFT (6U) -/*! AES - 1 if AES 128 included - */ -#define HASHCRYPT_CONFIG_AES(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK) - -#define HASHCRYPT_CONFIG_AESKEY_MASK (0x80U) -#define HASHCRYPT_CONFIG_AESKEY_SHIFT (7U) -/*! AESKEY - 1 if AES 192 and 256 also included - */ -#define HASHCRYPT_CONFIG_AESKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK) - -#define HASHCRYPT_CONFIG_SECRET_MASK (0x100U) -#define HASHCRYPT_CONFIG_SECRET_SHIFT (8U) -/*! SECRET - 1 if AES Secret key available - */ -#define HASHCRYPT_CONFIG_SECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK) - -#define HASHCRYPT_CONFIG_ICB_MASK (0x800U) -#define HASHCRYPT_CONFIG_ICB_SHIFT (11U) -/*! ICB - 1 if ICB over AES included - */ -#define HASHCRYPT_CONFIG_ICB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_ICB_SHIFT)) & HASHCRYPT_CONFIG_ICB_MASK) -/*! @} */ - -/*! @name LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. */ -/*! @{ */ - -#define HASHCRYPT_LOCK_SECLOCK_MASK (0x3U) -#define HASHCRYPT_LOCK_SECLOCK_SHIFT (0U) -/*! SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. - * If locked already, may only write if at same or higher security level as lock. Reads as: 0 if - * unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the - * only readable registers if locked and current state is lower than lock level. - * 0b00..Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests. - * 0b01..Locks to the current security level. AHB Master will issue requests at this level. - */ -#define HASHCRYPT_LOCK_SECLOCK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK) - -#define HASHCRYPT_LOCK_PATTERN_MASK (0xFFF0U) -#define HASHCRYPT_LOCK_PATTERN_SHIFT (4U) -/*! PATTERN - Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0 - */ -#define HASHCRYPT_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK) -/*! @} */ - -/*! @name MASK - */ -/*! @{ */ - -#define HASHCRYPT_MASK_MASK_MASK (0xFFFFFFFFU) -#define HASHCRYPT_MASK_MASK_SHIFT (0U) -/*! MASK - A random word. - */ -#define HASHCRYPT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK) -/*! @} */ - -/* The count of HASHCRYPT_MASK */ -#define HASHCRYPT_MASK_COUNT (4U) - - -/*! - * @} - */ /* end of group HASHCRYPT_Register_Masks */ - - -/* HASHCRYPT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral HASHCRYPT base address */ - #define HASHCRYPT_BASE (0x500A4000u) - /** Peripheral HASHCRYPT base address */ - #define HASHCRYPT_BASE_NS (0x400A4000u) - /** Peripheral HASHCRYPT base pointer */ - #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) - /** Peripheral HASHCRYPT base pointer */ - #define HASHCRYPT_NS ((HASHCRYPT_Type *)HASHCRYPT_BASE_NS) - /** Array initializer of HASHCRYPT peripheral base addresses */ - #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } - /** Array initializer of HASHCRYPT peripheral base pointers */ - #define HASHCRYPT_BASE_PTRS { HASHCRYPT } - /** Array initializer of HASHCRYPT peripheral base addresses */ - #define HASHCRYPT_BASE_ADDRS_NS { HASHCRYPT_BASE_NS } - /** Array initializer of HASHCRYPT peripheral base pointers */ - #define HASHCRYPT_BASE_PTRS_NS { HASHCRYPT_NS } -#else - /** Peripheral HASHCRYPT base address */ - #define HASHCRYPT_BASE (0x400A4000u) - /** Peripheral HASHCRYPT base pointer */ - #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) - /** Array initializer of HASHCRYPT peripheral base addresses */ - #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } - /** Array initializer of HASHCRYPT peripheral base pointers */ - #define HASHCRYPT_BASE_PTRS { HASHCRYPT } -#endif - -/*! - * @} - */ /* end of group HASHCRYPT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2C Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer - * @{ - */ - -/** I2C - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[2048]; - __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ - __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ - __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ - __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ - __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ - __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ - uint8_t RESERVED_1[4]; - __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ - __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ - __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ - uint8_t RESERVED_2[20]; - __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ - __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ - __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ - __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ - uint8_t RESERVED_3[36]; - __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ - uint8_t RESERVED_4[1912]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} I2C_Type; - -/* ---------------------------------------------------------------------------- - -- I2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Register_Masks I2C Register Masks - * @{ - */ - -/*! @name CFG - Configuration for shared functions. */ -/*! @{ */ - -#define I2C_CFG_MSTEN_MASK (0x1U) -#define I2C_CFG_MSTEN_SHIFT (0U) -/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not - * changed, but the Master function is internally reset. - * 0b0..Disabled. The I2C Master function is disabled. - * 0b1..Enabled. The I2C Master function is enabled. - */ -#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) - -#define I2C_CFG_SLVEN_MASK (0x2U) -#define I2C_CFG_SLVEN_SHIFT (1U) -/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not - * changed, but the Slave function is internally reset. - * 0b0..Disabled. The I2C slave function is disabled. - * 0b1..Enabled. The I2C slave function is enabled. - */ -#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) - -#define I2C_CFG_MONEN_MASK (0x4U) -#define I2C_CFG_MONEN_SHIFT (2U) -/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not - * changed, but the Monitor function is internally reset. - * 0b0..Disabled. The I2C Monitor function is disabled. - * 0b1..Enabled. The I2C Monitor function is enabled. - */ -#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) - -#define I2C_CFG_TIMEOUTEN_MASK (0x8U) -#define I2C_CFG_TIMEOUTEN_SHIFT (3U) -/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. - * 0b0..Disabled. Time-out function is disabled. - * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause - * interrupts if they are enabled. Typically, only one time-out will be used in a system. - */ -#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) - -#define I2C_CFG_MONCLKSTR_MASK (0x10U) -#define I2C_CFG_MONCLKSTR_SHIFT (4U) -/*! MONCLKSTR - Monitor function Clock Stretching. - * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able - * to read data provided by the Monitor function before it is overwritten. This mode may be used when - * non-invasive monitoring is critical. - * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can - * read all incoming data supplied by the Monitor function. - */ -#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) - -#define I2C_CFG_HSCAPABLE_MASK (0x20U) -#define I2C_CFG_HSCAPABLE_SHIFT (5U) -/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive - * and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies - * to all functions: Master, Slave, and Monitor. - * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the - * extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, - * such as changing the drive strength or filtering, must be made by software via the IOCON register associated - * with each I2C pin, - * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support - * High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more - * information. - */ -#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) -/*! @} */ - -/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ -/*! @{ */ - -#define I2C_STAT_MSTPENDING_MASK (0x1U) -#define I2C_STAT_MSTPENDING_SHIFT (0U) -/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on - * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what - * type of software service if any the master expects. This flag will cause an interrupt when set - * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling - * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle - * state, and no communication is needed, mask this interrupt. - * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. - * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the - * idle state, it is waiting to receive or transmit data or the NACK bit. - */ -#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) - -#define I2C_STAT_MSTSTATE_MASK (0xEU) -#define I2C_STAT_MSTSTATE_SHIFT (1U) -/*! MSTSTATE - Master State code. The master state code reflects the master state when the - * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field - * indicates a specific required service for the Master function. All other values are reserved. See - * Table 400 for details of state values and appropriate responses. - * 0b000..Idle. The Master function is available to be used for a new transaction. - * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. - * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. - * 0b011..NACK Address. Slave NACKed address. - * 0b100..NACK Data. Slave NACKed transmitted data. - */ -#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) - -#define I2C_STAT_MSTARBLOSS_MASK (0x10U) -#define I2C_STAT_MSTARBLOSS_SHIFT (4U) -/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to - * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - * 0b0..No Arbitration Loss has occurred. - * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master - * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, - * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. - */ -#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) - -#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) -/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to - * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - * 0b0..No Start/Stop Error has occurred. - * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is - * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an - * idle state, no action is required. A request for a Start could be made, or software could attempt to insure - * that the bus has not stalled. - */ -#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) - -#define I2C_STAT_SLVPENDING_MASK (0x100U) -#define I2C_STAT_SLVPENDING_SHIFT (8U) -/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue - * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if - * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the - * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is - * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time - * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section - * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are - * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must - * also be detected automatically, since the address must be acknowledged before the clock can be - * stretched. - * 0b0..In progress. The Slave function does not currently need service. - * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. - */ -#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) - -#define I2C_STAT_SLVSTATE_MASK (0x600U) -#define I2C_STAT_SLVSTATE_SHIFT (9U) -/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for - * the Slave function. All other values are reserved. See Table 401 for state values and actions. - * note that the occurrence of some states and how they are handled are affected by DMA mode and - * Automatic Operation modes. - * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. - * 0b01..Slave receive. Received data is available (Slave Receiver mode). - * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). - */ -#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) - -#define I2C_STAT_SLVNOTSTR_MASK (0x800U) -#define I2C_STAT_SLVNOTSTR_SHIFT (11U) -/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. - * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave - * operation. This read-only flag reflects the slave function status in real time. - * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. - * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or - * Power-down mode could be entered at this time. - */ -#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) - -#define I2C_STAT_SLVIDX_MASK (0x3000U) -#define I2C_STAT_SLVIDX_SHIFT (12U) -/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been - * selected by receiving an address that matches one of the slave addresses defined by any enabled - * slave address registers, and provides an identification of the address that was matched. It is - * possible that more than one address could be matched, but only one match can be reported here. - * 0b00..Address 0. Slave address 0 was matched. - * 0b01..Address 1. Slave address 1 was matched. - * 0b10..Address 2. Slave address 2 was matched. - * 0b11..Address 3. Slave address 3 was matched. - */ -#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) - -#define I2C_STAT_SLVSEL_MASK (0x4000U) -#define I2C_STAT_SLVSEL_SHIFT (14U) -/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave - * function to acknowledge the address, or when the address has been automatically acknowledged. - * It is cleared when another address cycle presents an address that does not match an enabled - * address on the Slave function, when slave software decides to NACK a matched address, when - * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of - * Automatic Operation. SLVSEL is not cleared if software NACKs data. - * 0b0..Not selected. The Slave function is not currently selected. - * 0b1..Selected. The Slave function is currently selected. - */ -#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) - -#define I2C_STAT_SLVDESEL_MASK (0x8000U) -#define I2C_STAT_SLVDESEL_SHIFT (15U) -/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via - * INTENSET. This flag can be cleared by writing a 1 to this bit. - * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently - * selected. That information can be found in the SLVSEL flag. - * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag - * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. - */ -#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) - -#define I2C_STAT_MONRDY_MASK (0x10000U) -#define I2C_STAT_MONRDY_SHIFT (16U) -/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. - * 0b0..No data. The Monitor function does not currently have data available. - * 0b1..Data waiting. The Monitor function has data waiting to be read. - */ -#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) - -#define I2C_STAT_MONOV_MASK (0x20000U) -#define I2C_STAT_MONOV_SHIFT (17U) -/*! MONOV - Monitor Overflow flag. - * 0b0..No overrun. Monitor data has not overrun. - * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not - * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. - */ -#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) - -#define I2C_STAT_MONACTIVE_MASK (0x40000U) -#define I2C_STAT_MONACTIVE_SHIFT (18U) -/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to - * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred - * more recently than a bus Stop. - * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. - * 0b1..Active. The Monitor function considers the I2C bus to be active. - */ -#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) - -#define I2C_STAT_MONIDLE_MASK (0x80000U) -#define I2C_STAT_MONIDLE_SHIFT (19U) -/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change - * from active to inactive. This can be used by software to decide when to process data - * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the - * INTENSET register. The flag can be cleared by writing a 1 to this bit. - * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. - * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. - */ -#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) - -#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) -/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been - * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock - * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus - * is idle. - * 0b0..No time-out. I2C bus events have not caused a time-out. - * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. - */ -#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) - -#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) -/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the - * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. - * 0b0..No time-out. SCL low time has not caused a time-out. - * 0b1..Time-out. SCL low time has caused a time-out. - */ -#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable Set and read register. */ -/*! @{ */ - -#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) -#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) -/*! MSTPENDINGEN - Master Pending interrupt Enable. - * 0b0..Disabled. The MstPending interrupt is disabled. - * 0b1..Enabled. The MstPending interrupt is enabled. - */ -#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) - -#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) -#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) -/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. - * 0b0..Disabled. The MstArbLoss interrupt is disabled. - * 0b1..Enabled. The MstArbLoss interrupt is enabled. - */ -#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) - -#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) -#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) -/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. - * 0b0..Disabled. The MstStStpErr interrupt is disabled. - * 0b1..Enabled. The MstStStpErr interrupt is enabled. - */ -#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) - -#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) -#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) -/*! SLVPENDINGEN - Slave Pending interrupt Enable. - * 0b0..Disabled. The SlvPending interrupt is disabled. - * 0b1..Enabled. The SlvPending interrupt is enabled. - */ -#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) - -#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) -#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) -/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. - * 0b0..Disabled. The SlvNotStr interrupt is disabled. - * 0b1..Enabled. The SlvNotStr interrupt is enabled. - */ -#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) - -#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) -#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) -/*! SLVDESELEN - Slave Deselect interrupt Enable. - * 0b0..Disabled. The SlvDeSel interrupt is disabled. - * 0b1..Enabled. The SlvDeSel interrupt is enabled. - */ -#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) - -#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) -#define I2C_INTENSET_MONRDYEN_SHIFT (16U) -/*! MONRDYEN - Monitor data Ready interrupt Enable. - * 0b0..Disabled. The MonRdy interrupt is disabled. - * 0b1..Enabled. The MonRdy interrupt is enabled. - */ -#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) - -#define I2C_INTENSET_MONOVEN_MASK (0x20000U) -#define I2C_INTENSET_MONOVEN_SHIFT (17U) -/*! MONOVEN - Monitor Overrun interrupt Enable. - * 0b0..Disabled. The MonOv interrupt is disabled. - * 0b1..Enabled. The MonOv interrupt is enabled. - */ -#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) - -#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) -#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) -/*! MONIDLEEN - Monitor Idle interrupt Enable. - * 0b0..Disabled. The MonIdle interrupt is disabled. - * 0b1..Enabled. The MonIdle interrupt is enabled. - */ -#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) - -#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) -#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) -/*! EVENTTIMEOUTEN - Event time-out interrupt Enable. - * 0b0..Disabled. The Event time-out interrupt is disabled. - * 0b1..Enabled. The Event time-out interrupt is enabled. - */ -#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) - -#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) -#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) -/*! SCLTIMEOUTEN - SCL time-out interrupt Enable. - * 0b0..Disabled. The SCL time-out interrupt is disabled. - * 0b1..Enabled. The SCL time-out interrupt is enabled. - */ -#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear register. */ -/*! @{ */ - -#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) -#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) -/*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding - * bit in the INTENSET register if implemented. - */ -#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) - -#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) -#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) -/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear. - */ -#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) - -#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) -#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) -/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear. - */ -#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) - -#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) -#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) -/*! SLVPENDINGCLR - Slave Pending interrupt clear. - */ -#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) - -#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) -#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) -/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear. - */ -#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) - -#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) -#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) -/*! SLVDESELCLR - Slave Deselect interrupt clear. - */ -#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) - -#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) -#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) -/*! MONRDYCLR - Monitor data Ready interrupt clear. - */ -#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) - -#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) -#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) -/*! MONOVCLR - Monitor Overrun interrupt clear. - */ -#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) - -#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) -#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) -/*! MONIDLECLR - Monitor Idle interrupt clear. - */ -#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) - -#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) -#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) -/*! EVENTTIMEOUTCLR - Event time-out interrupt clear. - */ -#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) - -#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) -#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) -/*! SCLTIMEOUTCLR - SCL time-out interrupt clear. - */ -#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) -/*! @} */ - -/*! @name TIMEOUT - Time-out value register. */ -/*! @{ */ - -#define I2C_TIMEOUT_TOMIN_MASK (0xFU) -#define I2C_TIMEOUT_TOMIN_SHIFT (0U) -/*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum - * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. - */ -#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) - -#define I2C_TIMEOUT_TO_MASK (0xFFF0U) -#define I2C_TIMEOUT_TO_SHIFT (4U) -/*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C - * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, - * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A - * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after - * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the - * I2C function clock. - */ -#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) -/*! @} */ - -/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ -/*! @{ */ - -#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) -#define I2C_CLKDIV_DIVVAL_SHIFT (0U) -/*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that - * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = - * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is - * divided by 65,536 before use. - */ -#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ -/*! @{ */ - -#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) -#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) -/*! MSTPENDING - Master Pending. - */ -#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) - -#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) -#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) -/*! MSTARBLOSS - Master Arbitration Loss flag. - */ -#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) - -#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) -/*! MSTSTSTPERR - Master Start/Stop Error flag. - */ -#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) - -#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) -#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) -/*! SLVPENDING - Slave Pending. - */ -#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) - -#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) -#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) -/*! SLVNOTSTR - Slave Not Stretching status. - */ -#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) - -#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) -#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) -/*! SLVDESEL - Slave Deselected flag. - */ -#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) - -#define I2C_INTSTAT_MONRDY_MASK (0x10000U) -#define I2C_INTSTAT_MONRDY_SHIFT (16U) -/*! MONRDY - Monitor Ready. - */ -#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) - -#define I2C_INTSTAT_MONOV_MASK (0x20000U) -#define I2C_INTSTAT_MONOV_SHIFT (17U) -/*! MONOV - Monitor Overflow flag. - */ -#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) - -#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) -#define I2C_INTSTAT_MONIDLE_SHIFT (19U) -/*! MONIDLE - Monitor Idle flag. - */ -#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) - -#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) -/*! EVENTTIMEOUT - Event time-out Interrupt flag. - */ -#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) - -#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) -/*! SCLTIMEOUT - SCL time-out Interrupt flag. - */ -#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name MSTCTL - Master control register. */ -/*! @{ */ - -#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) -#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) -/*! MSTCONTINUE - Master Continue. This bit is write-only. - * 0b0..No effect. - * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing - * transmit data, reading received data, or any other housekeeping related to the next bus operation. - */ -#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) - -#define I2C_MSTCTL_MSTSTART_MASK (0x2U) -#define I2C_MSTCTL_MSTSTART_SHIFT (1U) -/*! MSTSTART - Master Start control. This bit is write-only. - * 0b0..No effect. - * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. - */ -#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) - -#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) -#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) -/*! MSTSTOP - Master Stop control. This bit is write-only. - * 0b0..No effect. - * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave - * if the master is receiving data from the slave (Master Receiver mode). - */ -#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) - -#define I2C_MSTCTL_MSTDMA_MASK (0x8U) -#define I2C_MSTCTL_MSTDMA_SHIFT (3U) -/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type - * operations such as Start, address, Stop, and address match must always be done with software, - * typically via an interrupt. Address acknowledgement must also be done by software except when - * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by - * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA - * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is - * read/write. - * 0b0..Disable. No DMA requests are generated for master operation. - * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating - * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. - */ -#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) -/*! @} */ - -/*! @name MSTTIME - Master timing configuration. */ -/*! @{ */ - -#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) -#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) -/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this - * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This - * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters - * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. - * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. - * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. - * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. - * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. - * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. - * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. - * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. - * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. - */ -#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) - -#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) -#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) -/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this - * master on SCL. Other masters in a multi-master system could shorten this time. This - * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters - * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. - * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. - * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . - * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. - * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. - * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. - * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. - * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. - * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. - */ -#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) -/*! @} */ - -/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ -/*! @{ */ - -#define I2C_MSTDAT_DATA_MASK (0xFFU) -#define I2C_MSTDAT_DATA_SHIFT (0U) -/*! DATA - Master function data register. Read: read the most recently received data for the Master - * function. Write: transmit data using the Master function. - */ -#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVCTL - Slave control register. */ -/*! @{ */ - -#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) -#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) -/*! SLVCONTINUE - Slave Continue. - * 0b0..No effect. - * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag - * in the STAT register. This must be done after writing transmit data, reading received data, or any other - * housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE - * should not be set unless SLVPENDING = 1. - */ -#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) - -#define I2C_SLVCTL_SLVNACK_MASK (0x2U) -#define I2C_SLVCTL_SLVNACK_SHIFT (1U) -/*! SLVNACK - Slave NACK. - * 0b0..No effect. - * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). - */ -#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) - -#define I2C_SLVCTL_SLVDMA_MASK (0x8U) -#define I2C_SLVCTL_SLVDMA_SHIFT (3U) -/*! SLVDMA - Slave DMA enable. - * 0b0..Disabled. No DMA requests are issued for Slave mode operation. - * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. - */ -#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) - -#define I2C_SLVCTL_AUTOACK_MASK (0x100U) -#define I2C_SLVCTL_AUTOACK_SHIFT (8U) -/*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches - * SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA - * to allow processing of the data without intervention. If this bit is clear and a header - * matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or - * interrupt. - * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching - * address is received. If AUTONACK = 1, received addresses are NACKed (ignored). - * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, - * allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does - * not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK - * is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. - */ -#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) - -#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) -#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) -/*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write - * request on the next header with an address matching SLVADR0. Since DMA needs to be configured to - * match the transfer direction, the direction needs to be specified. This bit allows a direction to - * be chosen for the next operation. - * 0b0..The expected next operation in Automatic Mode is an I2C write. - * 0b1..The expected next operation in Automatic Mode is an I2C read. - */ -#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) -/*! @} */ - -/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ -/*! @{ */ - -#define I2C_SLVDAT_DATA_MASK (0xFFU) -#define I2C_SLVDAT_DATA_SHIFT (0U) -/*! DATA - Slave function data register. Read: read the most recently received data for the Slave - * function. Write: transmit data using the Slave function. - */ -#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVADR - Slave address register. */ -/*! @{ */ - -#define I2C_SLVADR_SADISABLE_MASK (0x1U) -#define I2C_SLVADR_SADISABLE_SHIFT (0U) -/*! SADISABLE - Slave Address n Disable. - * 0b0..Enabled. Slave Address n is enabled. - * 0b1..Ignored Slave Address n is ignored. - */ -#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) - -#define I2C_SLVADR_SLVADR_MASK (0xFEU) -#define I2C_SLVADR_SLVADR_SHIFT (1U) -/*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. - */ -#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) - -#define I2C_SLVADR_AUTONACK_MASK (0x8000U) -#define I2C_SLVADR_AUTONACK_SHIFT (15U) -/*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows - * software to ignore I2C traffic while handling previous I2C data or other operations. - * 0b0..Normal operation, matching I2C addresses are not ignored. - * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches - * SLVADRn, and AUTOMATCHREAD matches the direction. - */ -#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) -/*! @} */ - -/* The count of I2C_SLVADR */ -#define I2C_SLVADR_COUNT (4U) - -/*! @name SLVQUAL0 - Slave Qualification for address 0. */ -/*! @{ */ - -#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) -#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) -/*! QUALMODE0 - Qualify mode for slave address 0. - * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. - * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. - */ -#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) - -#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) -#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) -/*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to - * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is - * set to 1 will cause an automatic match of the corresponding bit of the received address when it - * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for - * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 - * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). - */ -#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) -/*! @} */ - -/*! @name MONRXDAT - Monitor receiver data register. */ -/*! @{ */ - -#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) -#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) -/*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. - */ -#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) - -#define I2C_MONRXDAT_MONSTART_MASK (0x100U) -#define I2C_MONRXDAT_MONSTART_SHIFT (8U) -/*! MONSTART - Monitor Received Start. - * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. - * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. - */ -#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) - -#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) -#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) -/*! MONRESTART - Monitor Received Repeated Start. - * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. - * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. - */ -#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) - -#define I2C_MONRXDAT_MONNACK_MASK (0x400U) -#define I2C_MONRXDAT_MONNACK_SHIFT (10U) -/*! MONNACK - Monitor Received NACK. - * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. - * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. - */ -#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ - -#define I2C_ID_APERTURE_MASK (0xFFU) -#define I2C_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - */ -#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) - -#define I2C_ID_MINOR_REV_MASK (0xF00U) -#define I2C_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation. - */ -#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) - -#define I2C_ID_MAJOR_REV_MASK (0xF000U) -#define I2C_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation. - */ -#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) - -#define I2C_ID_ID_MASK (0xFFFF0000U) -#define I2C_ID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function. - */ -#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2C_Register_Masks */ - - -/* I2C - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral I2C0 base address */ - #define I2C0_BASE (0x50086000u) - /** Peripheral I2C0 base address */ - #define I2C0_BASE_NS (0x40086000u) - /** Peripheral I2C0 base pointer */ - #define I2C0 ((I2C_Type *)I2C0_BASE) - /** Peripheral I2C0 base pointer */ - #define I2C0_NS ((I2C_Type *)I2C0_BASE_NS) - /** Peripheral I2C1 base address */ - #define I2C1_BASE (0x50087000u) - /** Peripheral I2C1 base address */ - #define I2C1_BASE_NS (0x40087000u) - /** Peripheral I2C1 base pointer */ - #define I2C1 ((I2C_Type *)I2C1_BASE) - /** Peripheral I2C1 base pointer */ - #define I2C1_NS ((I2C_Type *)I2C1_BASE_NS) - /** Peripheral I2C2 base address */ - #define I2C2_BASE (0x50088000u) - /** Peripheral I2C2 base address */ - #define I2C2_BASE_NS (0x40088000u) - /** Peripheral I2C2 base pointer */ - #define I2C2 ((I2C_Type *)I2C2_BASE) - /** Peripheral I2C2 base pointer */ - #define I2C2_NS ((I2C_Type *)I2C2_BASE_NS) - /** Peripheral I2C3 base address */ - #define I2C3_BASE (0x50089000u) - /** Peripheral I2C3 base address */ - #define I2C3_BASE_NS (0x40089000u) - /** Peripheral I2C3 base pointer */ - #define I2C3 ((I2C_Type *)I2C3_BASE) - /** Peripheral I2C3 base pointer */ - #define I2C3_NS ((I2C_Type *)I2C3_BASE_NS) - /** Peripheral I2C4 base address */ - #define I2C4_BASE (0x5008A000u) - /** Peripheral I2C4 base address */ - #define I2C4_BASE_NS (0x4008A000u) - /** Peripheral I2C4 base pointer */ - #define I2C4 ((I2C_Type *)I2C4_BASE) - /** Peripheral I2C4 base pointer */ - #define I2C4_NS ((I2C_Type *)I2C4_BASE_NS) - /** Peripheral I2C5 base address */ - #define I2C5_BASE (0x50096000u) - /** Peripheral I2C5 base address */ - #define I2C5_BASE_NS (0x40096000u) - /** Peripheral I2C5 base pointer */ - #define I2C5 ((I2C_Type *)I2C5_BASE) - /** Peripheral I2C5 base pointer */ - #define I2C5_NS ((I2C_Type *)I2C5_BASE_NS) - /** Peripheral I2C6 base address */ - #define I2C6_BASE (0x50097000u) - /** Peripheral I2C6 base address */ - #define I2C6_BASE_NS (0x40097000u) - /** Peripheral I2C6 base pointer */ - #define I2C6 ((I2C_Type *)I2C6_BASE) - /** Peripheral I2C6 base pointer */ - #define I2C6_NS ((I2C_Type *)I2C6_BASE_NS) - /** Peripheral I2C7 base address */ - #define I2C7_BASE (0x50098000u) - /** Peripheral I2C7 base address */ - #define I2C7_BASE_NS (0x40098000u) - /** Peripheral I2C7 base pointer */ - #define I2C7 ((I2C_Type *)I2C7_BASE) - /** Peripheral I2C7 base pointer */ - #define I2C7_NS ((I2C_Type *)I2C7_BASE_NS) - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS_NS { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS_NS { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS } -#else - /** Peripheral I2C0 base address */ - #define I2C0_BASE (0x40086000u) - /** Peripheral I2C0 base pointer */ - #define I2C0 ((I2C_Type *)I2C0_BASE) - /** Peripheral I2C1 base address */ - #define I2C1_BASE (0x40087000u) - /** Peripheral I2C1 base pointer */ - #define I2C1 ((I2C_Type *)I2C1_BASE) - /** Peripheral I2C2 base address */ - #define I2C2_BASE (0x40088000u) - /** Peripheral I2C2 base pointer */ - #define I2C2 ((I2C_Type *)I2C2_BASE) - /** Peripheral I2C3 base address */ - #define I2C3_BASE (0x40089000u) - /** Peripheral I2C3 base pointer */ - #define I2C3 ((I2C_Type *)I2C3_BASE) - /** Peripheral I2C4 base address */ - #define I2C4_BASE (0x4008A000u) - /** Peripheral I2C4 base pointer */ - #define I2C4 ((I2C_Type *)I2C4_BASE) - /** Peripheral I2C5 base address */ - #define I2C5_BASE (0x40096000u) - /** Peripheral I2C5 base pointer */ - #define I2C5 ((I2C_Type *)I2C5_BASE) - /** Peripheral I2C6 base address */ - #define I2C6_BASE (0x40097000u) - /** Peripheral I2C6 base pointer */ - #define I2C6 ((I2C_Type *)I2C6_BASE) - /** Peripheral I2C7 base address */ - #define I2C7_BASE (0x40098000u) - /** Peripheral I2C7 base pointer */ - #define I2C7 ((I2C_Type *)I2C7_BASE) - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } -#endif -/** Interrupt vectors for the I2C peripheral type */ -#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2C_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2S Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer - * @{ - */ - -/** I2S - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[3072]; - __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ - __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ - __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ - uint8_t RESERVED_2[480]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ - uint8_t RESERVED_5[8]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ - uint8_t RESERVED_6[8]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ - __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ - uint8_t RESERVED_7[432]; - __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */ -} I2S_Type; - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ -/*! @{ */ - -#define I2S_CFG1_MAINENABLE_MASK (0x1U) -#define I2S_CFG1_MAINENABLE_SHIFT (0U) -/*! MAINENABLE - Main enable for I 2S function in this Flexcomm - * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags - * are reset. No other channel pairs can be enabled. - * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. - */ -#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) - -#define I2S_CFG1_DATAPAUSE_MASK (0x2U) -#define I2S_CFG1_DATAPAUSE_SHIFT (1U) -/*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer - * and the FIFO. This could be done in order to change streams, or while restarting after a data - * underflow or overflow. When paused, FIFO operations can be done without corrupting data that is - * in the process of being sent or received. Once a data pause has been requested, the interface - * may need to complete sending data that was in progress before interrupting the flow of data. - * Software must check that the pause is actually in effect before taking action. This is done by - * monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer - * will resume at the beginning of the next frame. - * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. - * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. - */ -#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) - -#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) -#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) -/*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field - * whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this - * Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs - * in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. - * 0b00..1 I2S channel pairs in this flexcomm - * 0b01..2 I2S channel pairs in this flexcomm - * 0b10..3 I2S channel pairs in this flexcomm - * 0b11..4 I2S channel pairs in this flexcomm - */ -#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) - -#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) -#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) -/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. - * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. - * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of - * SCK, when divided from the Flexcomm function clock. - * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. - * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. - */ -#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) - -#define I2S_CFG1_MODE_MASK (0xC0U) -#define I2S_CFG1_MODE_SHIFT (6U) -/*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all - * supported cases. See Formats and modes for examples. - * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece - * of left channel data occurring during the first phase, and one pieces of right channel data occurring - * during the second phase. In this mode, the data region begins one clock after the leading WS edge for the - * frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If - * FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. - * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0. - * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame. - * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame. - */ -#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) - -#define I2S_CFG1_RIGHTLOW_MASK (0x100U) -#define I2S_CFG1_RIGHTLOW_SHIFT (8U) -/*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left - * and right channel data as it is transferred to or from the FIFO. This bit is not used if the - * data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 - * of this register) = 1, the one channel to be used is the nominally the left channel. POSITION - * can still place that data in the frame where right channel data is normally located. if all - * enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. - * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO - * bits 31:16 are used for the right channel. - * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO - * bits 15:0 are used for the right channel. - */ -#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) - -#define I2S_CFG1_LEFTJUST_MASK (0x200U) -#define I2S_CFG1_LEFTJUST_SHIFT (9U) -/*! LEFTJUST - Left Justify data. - * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting - * from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data - * in the stream on the data bus. - * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting - * from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would - * correspond to left justified data in the stream on the data bus. - */ -#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) - -#define I2S_CFG1_ONECHANNEL_MASK (0x400U) -#define I2S_CFG1_ONECHANNEL_SHIFT (10U) -/*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit - * applies only to the first I2S channel pair. Other channel pairs may select this mode - * independently in their separate CFG1 registers. - * 0b0..I2S data for this channel pair is treated as left and right channels. - * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this - * pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a - * clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel - * of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side - * (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data - * for the single channel of data is placed at the clock defined by POSITION. - */ -#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) - -#define I2S_CFG1_SCK_POL_MASK (0x1000U) -#define I2S_CFG1_SCK_POL_SHIFT (12U) -/*! SCK_POL - SCK polarity. - * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). - * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges. - */ -#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) - -#define I2S_CFG1_WS_POL_MASK (0x2000U) -#define I2S_CFG1_WS_POL_SHIFT (13U) -/*! WS_POL - WS polarity. - * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S). - * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). - */ -#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) - -#define I2S_CFG1_DATALEN_MASK (0x1F0000U) -#define I2S_CFG1_DATALEN_SHIFT (16U) -/*! DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or - * received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received - * from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the - * I2S: Determines the size of data transfers between the FIFO and the I2S - * serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of - * right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse - * at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to - * 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = - * data is 32 bits in length - */ -#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) -/*! @} */ - -/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ -/*! @{ */ - -#define I2S_CFG2_FRAMELEN_MASK (0x1FFU) -#define I2S_CFG2_FRAMELEN_SHIFT (0U) -/*! FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the - * frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported - * 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is - * 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in - * mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger - * than DATALEN in order for the WS pulse to be generated correctly. - */ -#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) - -#define I2S_CFG2_POSITION_MASK (0x1FF0000U) -#define I2S_CFG2_POSITION_SHIFT (16U) -/*! POSITION - Data Position. Defines the location within the frame of the data for this channel - * pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION - * defines the location of data in both the left phase and right phase, starting one clock after - * the WS edge. In other modes, POSITION defines the location of data within the entire frame. - * ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The - * combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels - * do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit - * position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS - * phase. 0x002 = data begins at bit position 2 within the frame or WS phase. - */ -#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) -/*! @} */ - -/*! @name STAT - Status register for the primary channel pair. */ -/*! @{ */ - -#define I2S_STAT_BUSY_MASK (0x1U) -#define I2S_STAT_BUSY_SHIFT (0U) -/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. - * 0b0..The transmitter/receiver for channel pair is currently idle. - * 0b1..The transmitter/receiver for channel pair is currently processing data. - */ -#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) - -#define I2S_STAT_SLVFRMERR_MASK (0x2U) -#define I2S_STAT_SLVFRMERR_SHIFT (1U) -/*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as - * a slave. An error indicates that the incoming WS signal did not transition as expected due to - * a mismatch between FRAMELEN and the actual incoming I2S stream. - * 0b0..No error has been recorded. - * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. - */ -#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) - -#define I2S_STAT_LR_MASK (0x4U) -#define I2S_STAT_LR_SHIFT (2U) -/*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to - * be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data - * being processed for the currently busy channel pair. - * 0b0..Left channel. - * 0b1..Right channel. - */ -#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) - -#define I2S_STAT_DATAPAUSED_MASK (0x8U) -#define I2S_STAT_DATAPAUSED_SHIFT (3U) -/*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels - * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for - * an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. - * 0b1..A data pause has been requested and is now in force. - */ -#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) -/*! @} */ - -/*! @name DIV - Clock divider, used by all channel pairs. */ -/*! @{ */ - -#define I2S_DIV_DIV_MASK (0xFFFU) -#define I2S_DIV_DIV_SHIFT (0U) -/*! DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The - * Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. - * 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is - * divided by 4,096. - */ -#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ - -#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) -#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) - -#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) -#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) - -#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) -#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) -/*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX - * FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is - * cleared, new data is provided, and the I2S is un-paused. - * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 - * bits or less, or when MONO = 1 for this channel pair. - * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. - */ -#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) - -#define I2S_FIFOCFG_PACK48_MASK (0x8U) -#define I2S_FIFOCFG_PACK48_SHIFT (3U) -/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. - * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values. - * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. - */ -#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) - -#define I2S_FIFOCFG_SIZE_MASK (0x30U) -#define I2S_FIFOCFG_SIZE_SHIFT (4U) -/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 - * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - */ -#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) - -#define I2S_FIFOCFG_DMATX_MASK (0x1000U) -#define I2S_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) - -#define I2S_FIFOCFG_DMARX_MASK (0x2000U) -#define I2S_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) - -#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) -#define I2S_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in - * FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) - -#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) -#define I2S_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in - * FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) - -#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) -/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - */ -#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) - -#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) -/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - */ -#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ - -#define I2S_FIFOSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow - * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is - * needed. Cleared by writing a 1 to this bit. - */ -#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) - -#define I2S_FIFOSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA - * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - */ -#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) - -#define I2S_FIFOSTAT_PERINT_MASK (0x8U) -#define I2S_FIFOSTAT_PERINT_SHIFT (3U) -/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted - * an interrupt. The details can be found by reading the peripheral's STAT register. - */ -#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) - -#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) -/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - */ -#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) - -#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) -/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be - * written. When 0, the transmit FIFO is full and another write would cause it to overflow. - */ -#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) - -#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - */ -#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) - -#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) -#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) -/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to - * prevent the peripheral from causing an overflow. - */ -#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) - -#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY - * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at - * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be - * 0. - */ -#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) - -#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and - * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the - * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be - * 1. - */ -#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ - -#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) - -#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) - -#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) -#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled - * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to - * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO - * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX - * FIFO level decreases to 15 entries (is no longer full). - */ -#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) - -#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data - * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level - * can wake up the device just enough to perform DMA, then return to the reduced power mode. See - * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no - * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX - * FIFO has received 16 entries (has become full). - */ -#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ - -#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) -#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) - -#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) -#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) - -#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases - * to the level specified by TXLVL in the FIFOTRIG register. - */ -#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) - -#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level - * increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ - -#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) -#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) -/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) - -#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) -#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) -/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) - -#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) -/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) - -#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) -/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ - -#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. - */ -#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) - -#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. - */ -#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) - -#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO level interrupt. - */ -#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) - -#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO level interrupt. - */ -#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) - -#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) -#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) -/*! PERINT - Peripheral interrupt. - */ -#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ - -#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFOWR_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details. - */ -#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ - -#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) -#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. - */ -#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ - -#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORD_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. The number of bits used depends on configuration details. - */ -#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ - -#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48H_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. - */ -#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ - -#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. - */ -#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ - -#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. - */ -#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) -/*! @} */ - -/*! @name FIFOSIZE - FIFO size register */ -/*! @{ */ - -#define I2S_FIFOSIZE_FIFOSIZE_MASK (0x1FU) -#define I2S_FIFOSIZE_FIFOSIZE_SHIFT (0U) -/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - */ -#define I2S_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSIZE_FIFOSIZE_SHIFT)) & I2S_FIFOSIZE_FIFOSIZE_MASK) -/*! @} */ - -/*! @name ID - I2S Module identification */ -/*! @{ */ - -#define I2S_ID_APERTURE_MASK (0xFFU) -#define I2S_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - */ -#define I2S_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_APERTURE_SHIFT)) & I2S_ID_APERTURE_MASK) - -#define I2S_ID_MINOR_REV_MASK (0xF00U) -#define I2S_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation, starting at 0. - */ -#define I2S_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK) - -#define I2S_ID_MAJOR_REV_MASK (0xF000U) -#define I2S_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation, starting at 0. - */ -#define I2S_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK) - -#define I2S_ID_ID_MASK (0xFFFF0000U) -#define I2S_ID_ID_SHIFT (16U) -/*! ID - Unique module identifier for this IP block. - */ -#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2S_Register_Masks */ - - -/* I2S - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral I2S0 base address */ - #define I2S0_BASE (0x50086000u) - /** Peripheral I2S0 base address */ - #define I2S0_BASE_NS (0x40086000u) - /** Peripheral I2S0 base pointer */ - #define I2S0 ((I2S_Type *)I2S0_BASE) - /** Peripheral I2S0 base pointer */ - #define I2S0_NS ((I2S_Type *)I2S0_BASE_NS) - /** Peripheral I2S1 base address */ - #define I2S1_BASE (0x50087000u) - /** Peripheral I2S1 base address */ - #define I2S1_BASE_NS (0x40087000u) - /** Peripheral I2S1 base pointer */ - #define I2S1 ((I2S_Type *)I2S1_BASE) - /** Peripheral I2S1 base pointer */ - #define I2S1_NS ((I2S_Type *)I2S1_BASE_NS) - /** Peripheral I2S2 base address */ - #define I2S2_BASE (0x50088000u) - /** Peripheral I2S2 base address */ - #define I2S2_BASE_NS (0x40088000u) - /** Peripheral I2S2 base pointer */ - #define I2S2 ((I2S_Type *)I2S2_BASE) - /** Peripheral I2S2 base pointer */ - #define I2S2_NS ((I2S_Type *)I2S2_BASE_NS) - /** Peripheral I2S3 base address */ - #define I2S3_BASE (0x50089000u) - /** Peripheral I2S3 base address */ - #define I2S3_BASE_NS (0x40089000u) - /** Peripheral I2S3 base pointer */ - #define I2S3 ((I2S_Type *)I2S3_BASE) - /** Peripheral I2S3 base pointer */ - #define I2S3_NS ((I2S_Type *)I2S3_BASE_NS) - /** Peripheral I2S4 base address */ - #define I2S4_BASE (0x5008A000u) - /** Peripheral I2S4 base address */ - #define I2S4_BASE_NS (0x4008A000u) - /** Peripheral I2S4 base pointer */ - #define I2S4 ((I2S_Type *)I2S4_BASE) - /** Peripheral I2S4 base pointer */ - #define I2S4_NS ((I2S_Type *)I2S4_BASE_NS) - /** Peripheral I2S5 base address */ - #define I2S5_BASE (0x50096000u) - /** Peripheral I2S5 base address */ - #define I2S5_BASE_NS (0x40096000u) - /** Peripheral I2S5 base pointer */ - #define I2S5 ((I2S_Type *)I2S5_BASE) - /** Peripheral I2S5 base pointer */ - #define I2S5_NS ((I2S_Type *)I2S5_BASE_NS) - /** Peripheral I2S6 base address */ - #define I2S6_BASE (0x50097000u) - /** Peripheral I2S6 base address */ - #define I2S6_BASE_NS (0x40097000u) - /** Peripheral I2S6 base pointer */ - #define I2S6 ((I2S_Type *)I2S6_BASE) - /** Peripheral I2S6 base pointer */ - #define I2S6_NS ((I2S_Type *)I2S6_BASE_NS) - /** Peripheral I2S7 base address */ - #define I2S7_BASE (0x50098000u) - /** Peripheral I2S7 base address */ - #define I2S7_BASE_NS (0x40098000u) - /** Peripheral I2S7 base pointer */ - #define I2S7 ((I2S_Type *)I2S7_BASE) - /** Peripheral I2S7 base pointer */ - #define I2S7_NS ((I2S_Type *)I2S7_BASE_NS) - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS_NS { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS_NS { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS } -#else - /** Peripheral I2S0 base address */ - #define I2S0_BASE (0x40086000u) - /** Peripheral I2S0 base pointer */ - #define I2S0 ((I2S_Type *)I2S0_BASE) - /** Peripheral I2S1 base address */ - #define I2S1_BASE (0x40087000u) - /** Peripheral I2S1 base pointer */ - #define I2S1 ((I2S_Type *)I2S1_BASE) - /** Peripheral I2S2 base address */ - #define I2S2_BASE (0x40088000u) - /** Peripheral I2S2 base pointer */ - #define I2S2 ((I2S_Type *)I2S2_BASE) - /** Peripheral I2S3 base address */ - #define I2S3_BASE (0x40089000u) - /** Peripheral I2S3 base pointer */ - #define I2S3 ((I2S_Type *)I2S3_BASE) - /** Peripheral I2S4 base address */ - #define I2S4_BASE (0x4008A000u) - /** Peripheral I2S4 base pointer */ - #define I2S4 ((I2S_Type *)I2S4_BASE) - /** Peripheral I2S5 base address */ - #define I2S5_BASE (0x40096000u) - /** Peripheral I2S5 base pointer */ - #define I2S5 ((I2S_Type *)I2S5_BASE) - /** Peripheral I2S6 base address */ - #define I2S6_BASE (0x40097000u) - /** Peripheral I2S6 base pointer */ - #define I2S6 ((I2S_Type *)I2S6_BASE) - /** Peripheral I2S7 base address */ - #define I2S7_BASE (0x40098000u) - /** Peripheral I2S7 base pointer */ - #define I2S7 ((I2S_Type *)I2S7_BASE) - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } -#endif -/** Interrupt vectors for the I2S peripheral type */ -#define I2S_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2S_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer - * @{ - */ - -/** INPUTMUX - Register Layout Typedef */ -typedef struct { - __IO uint32_t SCT0_INMUX[7]; /**< Input mux register for SCT0 input, array offset: 0x0, array step: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t TIMER0CAPTSEL[4]; /**< Capture select registers for TIMER0 inputs, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[16]; - __IO uint32_t TIMER1CAPTSEL[4]; /**< Capture select registers for TIMER1 inputs, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_2[16]; - __IO uint32_t TIMER2CAPTSEL[4]; /**< Capture select registers for TIMER2 inputs, array offset: 0x60, array step: 0x4 */ - uint8_t RESERVED_3[80]; - __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ - __IO uint32_t DMA0_ITRIG_INMUX[23]; /**< Trigger select register for DMA0 channel, array offset: 0xE0, array step: 0x4 */ - uint8_t RESERVED_4[36]; - __IO uint32_t DMA0_OTRIG_INMUX[4]; /**< DMA0 output trigger selection to become DMA0 trigger, array offset: 0x160, array step: 0x4 */ - uint8_t RESERVED_5[16]; - __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ - __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ - uint8_t RESERVED_6[24]; - __IO uint32_t TIMER3CAPTSEL[4]; /**< Capture select registers for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */ - uint8_t RESERVED_7[16]; - __IO uint32_t TIMER4CAPTSEL[4]; /**< Capture select registers for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */ - uint8_t RESERVED_8[16]; - __IO uint32_t PINTSECSEL[2]; /**< Pin interrupt secure select register, array offset: 0x1E0, array step: 0x4 */ - uint8_t RESERVED_9[24]; - __IO uint32_t DMA1_ITRIG_INMUX[10]; /**< Trigger select register for DMA1 channel, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_10[24]; - __IO uint32_t DMA1_OTRIG_INMUX[4]; /**< DMA1 output trigger selection to become DMA1 trigger, array offset: 0x240, array step: 0x4 */ - uint8_t RESERVED_11[1264]; - __IO uint32_t DMA0_REQ_ENA; /**< Enable DMA0 requests, offset: 0x740 */ - uint8_t RESERVED_12[4]; - __O uint32_t DMA0_REQ_ENA_SET; /**< Set one or several bits in DMA0_REQ_ENA register, offset: 0x748 */ - uint8_t RESERVED_13[4]; - __O uint32_t DMA0_REQ_ENA_CLR; /**< Clear one or several bits in DMA0_REQ_ENA register, offset: 0x750 */ - uint8_t RESERVED_14[12]; - __IO uint32_t DMA1_REQ_ENA; /**< Enable DMA1 requests, offset: 0x760 */ - uint8_t RESERVED_15[4]; - __O uint32_t DMA1_REQ_ENA_SET; /**< Set one or several bits in DMA1_REQ_ENA register, offset: 0x768 */ - uint8_t RESERVED_16[4]; - __O uint32_t DMA1_REQ_ENA_CLR; /**< Clear one or several bits in DMA1_REQ_ENA register, offset: 0x770 */ - uint8_t RESERVED_17[12]; - __IO uint32_t DMA0_ITRIG_ENA; /**< Enable DMA0 triggers, offset: 0x780 */ - uint8_t RESERVED_18[4]; - __O uint32_t DMA0_ITRIG_ENA_SET; /**< Set one or several bits in DMA0_ITRIG_ENA register, offset: 0x788 */ - uint8_t RESERVED_19[4]; - __O uint32_t DMA0_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA0_ITRIG_ENA register, offset: 0x790 */ - uint8_t RESERVED_20[12]; - __IO uint32_t DMA1_ITRIG_ENA; /**< Enable DMA1 triggers, offset: 0x7A0 */ - uint8_t RESERVED_21[4]; - __O uint32_t DMA1_ITRIG_ENA_SET; /**< Set one or several bits in DMA1_ITRIG_ENA register, offset: 0x7A8 */ - uint8_t RESERVED_22[4]; - __O uint32_t DMA1_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA1_ITRIG_ENA register, offset: 0x7B0 */ -} INPUTMUX_Type; - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks - * @{ - */ - -/*! @name SCT0_INMUX - Input mux register for SCT0 input */ -/*! @{ */ - -#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU) -#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) -/*! INP_N - Input number to SCT0 inputs 0 to 6.. - * 0b00000..SCT_GPI0 function selected from IOCON register - * 0b00001..SCT_GPI1 function selected from IOCON register - * 0b00010..SCT_GPI2 function selected from IOCON register - * 0b00011..SCT_GPI3 function selected from IOCON register - * 0b00100..SCT_GPI4 function selected from IOCON register - * 0b00101..SCT_GPI5 function selected from IOCON register - * 0b00110..SCT_GPI6 function selected from IOCON register - * 0b00111..SCT_GPI7 function selected from IOCON register - * 0b01000..T0_OUT0 ctimer 0 match[0] output - * 0b01001..T1_OUT0 ctimer 1 match[0] output - * 0b01010..T2_OUT0 ctimer 2 match[0] output - * 0b01011..T3_OUT0 ctimer 3 match[0] output - * 0b01100..T4_OUT0 ctimer 4 match[0] output - * 0b01101..ADC_IRQ interrupt request from ADC - * 0b01110..GPIOINT_BMATCH - * 0b01111..USB0_FRAME_TOGGLE - * 0b10000..USB1_FRAME_TOGGLE - * 0b10001..COMP_OUTPUT output from analog comparator - * 0b10010..I2S_SHARED_SCK[0] output from I2S pin sharing - * 0b10011..I2S_SHARED_SCK[1] output from I2S pin sharing - * 0b10100..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b10101..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b10110..ARM_TXEV interrupt event from cpu0 or cpu1 - * 0b10111..DEBUG_HALTED from cpu0 or cpu1 - * 0b11000-0b11111..None - */ -#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK) -/*! @} */ - -/* The count of INPUTMUX_SCT0_INMUX */ -#define INPUTMUX_SCT0_INMUX_COUNT (7U) - -/*! @name TIMER0CAPTSEL - Capture select registers for TIMER0 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..None - * 0b10010..None - * 0b10011..None - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER0CAPTSEL */ -#define INPUTMUX_TIMER0CAPTSEL_COUNT (4U) - -/*! @name TIMER1CAPTSEL - Capture select registers for TIMER1 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..None - * 0b10010..None - * 0b10011..None - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER1CAPTSEL */ -#define INPUTMUX_TIMER1CAPTSEL_COUNT (4U) - -/*! @name TIMER2CAPTSEL - Capture select registers for TIMER2 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..None - * 0b10010..None - * 0b10011..None - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER2CAPTSEL */ -#define INPUTMUX_TIMER2CAPTSEL_COUNT (4U) - -/*! @name PINTSEL - Pin interrupt select register */ -/*! @{ */ - -#define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU) -#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) -/*! INTPIN - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = - * (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. - */ -#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PINTSEL */ -#define INPUTMUX_PINTSEL_COUNT (8U) - -/*! @name DMA0_ITRIG_INMUX - Trigger select register for DMA0 channel */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U) -/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22). - * 0b00000..Pin interrupt 0 - * 0b00001..Pin interrupt 1 - * 0b00010..Pin interrupt 2 - * 0b00011..Pin interrupt 3 - * 0b00100..Timer CTIMER0 Match 0 - * 0b00101..Timer CTIMER0 Match 1 - * 0b00110..Timer CTIMER1 Match 0 - * 0b00111..Timer CTIMER1 Match 1 - * 0b01000..Timer CTIMER2 Match 0 - * 0b01001..Timer CTIMER2 Match 1 - * 0b01010..Timer CTIMER3 Match 0 - * 0b01011..Timer CTIMER3 Match 1 - * 0b01100..Timer CTIMER4 Match 0 - * 0b01101..Timer CTIMER4 Match 1 - * 0b01110..COMP_OUTPUT - * 0b01111..DMA0 output trigger mux 0 - * 0b10000..DMA0 output trigger mux 1 - * 0b10001..DMA0 output trigger mux 1 - * 0b10010..DMA0 output trigger mux 3 - * 0b10011..SCT0 DMA request 0 - * 0b10100..SCT0 DMA request 1 - * 0b10101..HASH DMA RX trigger - * 0b10110-0b11111..None - */ -#define INPUTMUX_DMA0_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA0_ITRIG_INMUX */ -#define INPUTMUX_DMA0_ITRIG_INMUX_COUNT (23U) - -/*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection to become DMA0 trigger */ -/*! @{ */ - -#define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U) -/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22). - */ -#define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA0_OTRIG_INMUX */ -#define INPUTMUX_DMA0_OTRIG_INMUX_COUNT (4U) - -/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ -/*! @{ */ - -#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) -/*! CLKIN - Clock source number (decimal value) for frequency measure function reference clock: - * 0b00000..External main crystal oscilator (Clock_in). - * 0b00001..FRO 12MHz clock. - * 0b00010..FRO 96MHz clock. - * 0b00011..Watchdog oscillator / FRO1MHz clock. - * 0b00100..32 kHz oscillator (32k_clk) clock. - * 0b00101..main clock (main_clock). - * 0b00110..FREQME_GPIO_CLK_A. - * 0b00111..FREQME_GPIO_CLK_B. - */ -#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) -/*! @} */ - -/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ -/*! @{ */ - -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) -/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: - * 0b00000..External main crystal oscilator (Clock_in). - * 0b00001..FRO 12MHz clock. - * 0b00010..FRO 96MHz clock. - * 0b00011..Watchdog oscillator / FRO1MHz clock. - * 0b00100..32 kHz oscillator (32k_clk) clock. - * 0b00101..main clock (main_clock). - * 0b00110..FREQME_GPIO_CLK_A. - * 0b00111..FREQME_GPIO_CLK_B. - */ -#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) -/*! @} */ - -/*! @name TIMER3CAPTSEL - Capture select registers for TIMER3 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER3CAPTSEL */ -#define INPUTMUX_TIMER3CAPTSEL_COUNT (4U) - -/*! @name TIMER4CAPTSEL - Capture select registers for TIMER4 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER4CAPTSEL */ -#define INPUTMUX_TIMER4CAPTSEL_COUNT (4U) - -/*! @name PINTSECSEL - Pin interrupt secure select register */ -/*! @{ */ - -#define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU) -#define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U) -/*! INTPIN - Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: - * INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31. - */ -#define INPUTMUX_PINTSECSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PINTSECSEL */ -#define INPUTMUX_PINTSECSEL_COUNT (2U) - -/*! @name DMA1_ITRIG_INMUX - Trigger select register for DMA1 channel */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0xFU) -#define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U) -/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9). - * 0b0000..Pin interrupt 0 - * 0b0001..Pin interrupt 1 - * 0b0010..Pin interrupt 2 - * 0b0011..Pin interrupt 3 - * 0b0100..Timer CTIMER0 Match 0 - * 0b0101..Timer CTIMER0 Match 1 - * 0b0110..Timer CTIMER2 Match 0 - * 0b0111..Timer CTIMER4 Match 0 - * 0b1000..DMA1 output trigger mux 0 - * 0b1001..DMA1 output trigger mux 1 - * 0b1010..DMA1 output trigger mux 2 - * 0b1011..DMA1 output trigger mux 3 - * 0b1100..SCT0 DMA request 0 - * 0b1101..SCT0 DMA request 1 - * 0b1110..HASH DMA RX trigger - * 0b1111..None - */ -#define INPUTMUX_DMA1_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA1_ITRIG_INMUX */ -#define INPUTMUX_DMA1_ITRIG_INMUX_COUNT (10U) - -/*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection to become DMA1 trigger */ -/*! @{ */ - -#define INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK (0xFU) -#define INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT (0U) -/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9). - */ -#define INPUTMUX_DMA1_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA1_OTRIG_INMUX */ -#define INPUTMUX_DMA1_OTRIG_INMUX_COUNT (4U) - -/*! @name DMA0_REQ_ENA - Enable DMA0 requests */ -/*! @{ */ - -#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK (0x7FFFFFU) -#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT (0U) -/*! REQ_ENA - Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK) -/*! @} */ - -/*! @name DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK (0x7FFFFFU) -#define INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT (0U) -/*! SET - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register - */ -#define INPUTMUX_DMA0_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK (0x7FFFFFU) -#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT (0U) -/*! CLR - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register - */ -#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK) -/*! @} */ - -/*! @name DMA1_REQ_ENA - Enable DMA1 requests */ -/*! @{ */ - -#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK (0x3FFU) -#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT (0U) -/*! REQ_ENA - Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK) -/*! @} */ - -/*! @name DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK (0x3FFU) -#define INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT (0U) -/*! SET - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register - */ -#define INPUTMUX_DMA1_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK (0x3FFU) -#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT (0U) -/*! CLR - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register - */ -#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_ENA - Enable DMA0 triggers */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK (0x3FFFFFU) -#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) -/*! ITRIG_ENA - Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK (0x3FFFFFU) -#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT (0U) -/*! SET - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIG_ENA register - */ -#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK (0x3FFFFFU) -#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT (0U) -/*! CLR - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIG_ENA register - */ -#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK) -/*! @} */ - -/*! @name DMA1_ITRIG_ENA - Enable DMA1 triggers */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK (0x7FFFU) -#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) -/*! ITRIG_ENA - Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK) -/*! @} */ - -/*! @name DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK (0x7FFFU) -#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT (0U) -/*! SET - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no - * change in DMA1_ITRIG_ENA register - */ -#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK (0x7FFFU) -#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT (0U) -/*! CLR - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no - * change in DMA1_ITRIG_ENA register - */ -#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group INPUTMUX_Register_Masks */ - - -/* INPUTMUX - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE (0x50006000u) - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE_NS (0x40006000u) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS) - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS { INPUTMUX } - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX_BASE_NS } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS_NS { INPUTMUX_NS } -#else - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE (0x40006000u) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS { INPUTMUX } -#endif - -/*! - * @} - */ /* end of group INPUTMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- IOCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer - * @{ - */ - -/** IOCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ -} IOCON_Type; - -/* ---------------------------------------------------------------------------- - -- IOCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Register_Masks IOCON Register Masks - * @{ - */ - -/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ -/*! @{ */ - -#define IOCON_PIO_FUNC_MASK (0xFU) -#define IOCON_PIO_FUNC_SHIFT (0U) -/*! FUNC - Selects pin function. - * 0b0000..Alternative connection 0. - * 0b0001..Alternative connection 1. - * 0b0010..Alternative connection 2. - * 0b0011..Alternative connection 3. - * 0b0100..Alternative connection 4. - * 0b0101..Alternative connection 5. - * 0b0110..Alternative connection 6. - * 0b0111..Alternative connection 7. - */ -#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) - -#define IOCON_PIO_MODE_MASK (0x30U) -#define IOCON_PIO_MODE_SHIFT (4U) -/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) - -#define IOCON_PIO_SLEW_MASK (0x40U) -#define IOCON_PIO_SLEW_SHIFT (6U) -/*! SLEW - Driver slew rate. - * 0b0..Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - * 0b1..Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - */ -#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) - -#define IOCON_PIO_INVERT_MASK (0x80U) -#define IOCON_PIO_INVERT_SHIFT (7U) -/*! INVERT - Input polarity. - * 0b0..Disabled. Input function is not inverted. - * 0b1..Enabled. Input is function inverted. - */ -#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) - -#define IOCON_PIO_DIGIMODE_MASK (0x100U) -#define IOCON_PIO_DIGIMODE_SHIFT (8U) -/*! DIGIMODE - Select Digital mode. - * 0b0..Disable digital mode. Digital input set to 0. - * 0b1..Enable Digital mode. Digital input is enabled. - */ -#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) - -#define IOCON_PIO_OD_MASK (0x200U) -#define IOCON_PIO_OD_SHIFT (9U) -/*! OD - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). - * 0b0..Normal. Normal push-pull output - * 0b1..Open-drain. Simulated open-drain output (high drive disabled). - */ -#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) - -#define IOCON_PIO_ASW_MASK (0x400U) -#define IOCON_PIO_ASW_SHIFT (10U) -/*! ASW - Analog switch input control. - * 0b0..For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed - * (enabled). For the other pins, analog switch is open (disabled). - * 0b1..For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - */ -#define IOCON_PIO_ASW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW_SHIFT)) & IOCON_PIO_ASW_MASK) - -#define IOCON_PIO_SSEL_MASK (0x800U) -#define IOCON_PIO_SSEL_SHIFT (11U) -/*! SSEL - Supply Selection bit. - * 0b0..3V3 Signaling in I2C Mode. - * 0b1..1V8 Signaling in I2C Mode. - */ -#define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK) - -#define IOCON_PIO_FILTEROFF_MASK (0x1000U) -#define IOCON_PIO_FILTEROFF_SHIFT (12U) -/*! FILTEROFF - Controls input glitch filter. - * 0b0..Filter enabled. - * 0b1..Filter disabled. - */ -#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) - -#define IOCON_PIO_ECS_MASK (0x2000U) -#define IOCON_PIO_ECS_SHIFT (13U) -/*! ECS - Pull-up current source enable in I2C mode. - * 0b1..Enabled. Pull resistor is conencted. - * 0b0..Disabled. IO is in open drain cell. - */ -#define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK) - -#define IOCON_PIO_EGP_MASK (0x4000U) -#define IOCON_PIO_EGP_SHIFT (14U) -/*! EGP - Switch between GPIO mode and I2C mode. - * 0b0..I2C mode. - * 0b1..GPIO mode. - */ -#define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK) - -#define IOCON_PIO_I2CFILTER_MASK (0x8000U) -#define IOCON_PIO_I2CFILTER_SHIFT (15U) -/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. - * 0b0..I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. - * 0b1..I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. - */ -#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) -/*! @} */ - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT (2U) - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT2 (32U) - - -/*! - * @} - */ /* end of group IOCON_Register_Masks */ - - -/* IOCON - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral IOCON base address */ - #define IOCON_BASE (0x50001000u) - /** Peripheral IOCON base address */ - #define IOCON_BASE_NS (0x40001000u) - /** Peripheral IOCON base pointer */ - #define IOCON ((IOCON_Type *)IOCON_BASE) - /** Peripheral IOCON base pointer */ - #define IOCON_NS ((IOCON_Type *)IOCON_BASE_NS) - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS { IOCON_BASE } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS { IOCON } - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS_NS { IOCON_BASE_NS } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS_NS { IOCON_NS } -#else - /** Peripheral IOCON base address */ - #define IOCON_BASE (0x40001000u) - /** Peripheral IOCON base pointer */ - #define IOCON ((IOCON_Type *)IOCON_BASE) - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS { IOCON_BASE } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS { IOCON } -#endif - -/*! - * @} - */ /* end of group IOCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MRT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer - * @{ - */ - -/** MRT - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x10 */ - __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ - __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ - __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ - __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ - } CHANNEL[4]; - uint8_t RESERVED_0[176]; - __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ - __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ - __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ -} MRT_Type; - -/* ---------------------------------------------------------------------------- - -- MRT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Register_Masks MRT Register Masks - * @{ - */ - -/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ -/*! @{ */ - -#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) -/*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT - * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to - * this bit field starts the timer immediately. If the timer is running, writing a zero to this - * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer - * stops at the end of the time interval. - */ -#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) - -#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) -#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) -/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. - * This bit is write-only. Reading this bit always returns 0. - * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the - * time interval if the repeat mode is selected. - * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. - */ -#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_INTVAL */ -#define MRT_CHANNEL_INTVAL_COUNT (4U) - -/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ -/*! @{ */ - -#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) -/*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn - * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval - * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn - * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields - * returns -1 (0x00FF FFFF). - */ -#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_TIMER */ -#define MRT_CHANNEL_TIMER_COUNT (4U) - -/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ -/*! @{ */ - -#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) -#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) -/*! INTEN - Enable the TIMERn interrupt. - * 0b0..Disabled. TIMERn interrupt is disabled. - * 0b1..Enabled. TIMERn interrupt is enabled. - */ -#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) - -#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) -#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) -/*! MODE - Selects timer mode. - * 0b00..Repeat interrupt mode. - * 0b01..One-shot interrupt mode. - * 0b10..One-shot stall mode. - * 0b11..Reserved. - */ -#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_CTRL */ -#define MRT_CHANNEL_CTRL_COUNT (4U) - -/*! @name CHANNEL_STAT - MRT Status register. */ -/*! @{ */ - -#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) -#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) -/*! INTFLAG - Monitors the interrupt flag. - * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. - * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If - * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt - * are raised. Writing a 1 to this bit clears the interrupt request. - */ -#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) - -#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) -#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) -/*! RUN - Indicates the state of TIMERn. This bit is read-only. - * 0b0..Idle state. TIMERn is stopped. - * 0b1..Running. TIMERn is running. - */ -#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) - -#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) -#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) -/*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG - * register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating - * modes. - * 0b0..This channel is not in use. - * 0b1..This channel is in use. - */ -#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_STAT */ -#define MRT_CHANNEL_STAT_COUNT (4U) - -/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ -/*! @{ */ - -#define MRT_MODCFG_NOC_MASK (0xFU) -#define MRT_MODCFG_NOC_SHIFT (0U) -/*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.) - */ -#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) - -#define MRT_MODCFG_NOB_MASK (0x1F0U) -#define MRT_MODCFG_NOB_SHIFT (4U) -/*! NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.) - */ -#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) - -#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) -#define MRT_MODCFG_MULTITASK_SHIFT (31U) -/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. - * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. - * 0b1..Multi-task mode. - */ -#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) -/*! @} */ - -/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ -/*! @{ */ - -#define MRT_IDLE_CH_CHAN_MASK (0xF0U) -#define MRT_IDLE_CH_CHAN_SHIFT (4U) -/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is - * positioned such that it can be used as an offset from the MRT base address in order to access - * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See - * text above for more details. - */ -#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) -/*! @} */ - -/*! @name IRQ_FLAG - Global interrupt flag register */ -/*! @{ */ - -#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) -#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) -/*! GFLAG0 - Monitors the interrupt flag of TIMER0. - * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. - * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If - * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global - * interrupt are raised. Writing a 1 to this bit clears the interrupt request. - */ -#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) - -#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) -#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) -/*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0. - */ -#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) - -#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) -#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) -/*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0. - */ -#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) - -#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) -#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) -/*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0. - */ -#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MRT_Register_Masks */ - - -/* MRT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral MRT0 base address */ - #define MRT0_BASE (0x5000D000u) - /** Peripheral MRT0 base address */ - #define MRT0_BASE_NS (0x4000D000u) - /** Peripheral MRT0 base pointer */ - #define MRT0 ((MRT_Type *)MRT0_BASE) - /** Peripheral MRT0 base pointer */ - #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS { MRT0_BASE } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS { MRT0 } - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS_NS { MRT0_NS } -#else - /** Peripheral MRT0 base address */ - #define MRT0_BASE (0x4000D000u) - /** Peripheral MRT0 base pointer */ - #define MRT0 ((MRT_Type *)MRT0_BASE) - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS { MRT0_BASE } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS { MRT0 } -#endif -/** Interrupt vectors for the MRT peripheral type */ -#define MRT_IRQS { MRT0_IRQn } - -/*! - * @} - */ /* end of group MRT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- OSTIMER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer - * @{ - */ - -/** OSTIMER - Register Layout Typedef */ -typedef struct { - __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */ - __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */ - __I uint32_t CAPTURE_L; /**< Capture Low Register, offset: 0x8 */ - __I uint32_t CAPTURE_H; /**< Capture High Register, offset: 0xC */ - __IO uint32_t MATCH_L; /**< Match Low Register, offset: 0x10 */ - __IO uint32_t MATCH_H; /**< Match High Register, offset: 0x14 */ - uint8_t RESERVED_0[4]; - __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register, offset: 0x1C */ -} OSTIMER_Type; - -/* ---------------------------------------------------------------------------- - -- OSTIMER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks - * @{ - */ - -/*! @name EVTIMERL - EVTIMER Low Register */ -/*! @{ */ - -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) -/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the lower 32 bits of the 42-bits - * EVTIMER. Note: There is only one EVTIMER, readable from all domains. - */ -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) -/*! @} */ - -/*! @name EVTIMERH - EVTIMER High Register */ -/*! @{ */ - -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU) -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) -/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the upper 10 bits of the 42-bits - * EVTIMER. Note there is only one EVTIMER, readable from all domains. - */ -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) -/*! @} */ - -/*! @name CAPTURE_L - Capture Low Register */ -/*! @{ */ - -#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U) -/*! CAPTURE_VALUE - A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at - * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). - */ -#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK) -/*! @} */ - -/*! @name CAPTURE_H - Capture High Register */ -/*! @{ */ - -#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0x3FFU) -#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U) -/*! CAPTURE_VALUE - A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at - * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). - */ -#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK) -/*! @} */ - -/*! @name MATCH_L - Match Low Register */ -/*! @{ */ - -#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U) -/*! MATCH_VALUE - The value written to the MATCH (L/H) register pair is compared against the central - * EVTIMER. When a match occurs, an interrupt request is generated if enabled. - */ -#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK) -/*! @} */ - -/*! @name MATCH_H - Match High Register */ -/*! @{ */ - -#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0x3FFU) -#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U) -/*! MATCH_VALUE - The value written (upper 10 bits) to the MATCH (L/H) register pair is compared - * against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. - */ -#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK) -/*! @} */ - -/*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register */ -/*! @{ */ - -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) -/*! OSTIMER_INTRFLAG - This bit is set when a match occurs between the central 42-bits EVTIMER and - * the value programmed in the match-register pair. This bit is cleared by writing a '1'. Writes - * to clear this bit are asynchronous. It should be done before a new match value is written into - * the MATCH_L/H registers. - */ -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) - -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) -/*! OSTIMER_INTENA - When this bit is '1' an interrupt/wakeup request to the domain processor will - * be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests - * due to the OSTIMER_INTR flag are blocked. - */ -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) - -#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U) -#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U) -/*! MATCH_WR_RDY - This bit will be low when it is safe to write to reload the Match Registers. In - * typical applications it should not be necessary to test this bit. [1] - */ -#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group OSTIMER_Register_Masks */ - - -/* OSTIMER - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral OSTIMER base address */ - #define OSTIMER_BASE (0x5002D000u) - /** Peripheral OSTIMER base address */ - #define OSTIMER_BASE_NS (0x4002D000u) - /** Peripheral OSTIMER base pointer */ - #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) - /** Peripheral OSTIMER base pointer */ - #define OSTIMER_NS ((OSTIMER_Type *)OSTIMER_BASE_NS) - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS { OSTIMER } - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS_NS { OSTIMER_BASE_NS } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS_NS { OSTIMER_NS } -#else - /** Peripheral OSTIMER base address */ - #define OSTIMER_BASE (0x4002D000u) - /** Peripheral OSTIMER base pointer */ - #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS { OSTIMER } -#endif -/** Interrupt vectors for the OSTIMER peripheral type */ -#define OSTIMER_IRQS { OS_EVENT_IRQn } - -/*! - * @} - */ /* end of group OSTIMER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer - * @{ - */ - -/** PINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ - __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ - __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ - __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ - __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ - __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ - __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ - __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ - __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ - __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ - __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ - __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ - __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ -} PINT_Type; - -/* ---------------------------------------------------------------------------- - -- PINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Register_Masks PINT Register Masks - * @{ - */ - -/*! @name ISEL - Pin Interrupt Mode register */ -/*! @{ */ - -#define PINT_ISEL_PMODE_MASK (0xFFU) -#define PINT_ISEL_PMODE_SHIFT (0U) -/*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt - * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive - */ -#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) -/*! @} */ - -/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ -/*! @{ */ - -#define PINT_IENR_ENRL_MASK (0xFFU) -#define PINT_IENR_ENRL_SHIFT (0U) -/*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the - * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable - * rising edge or level interrupt. - */ -#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) -/*! @} */ - -/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ -/*! @{ */ - -#define PINT_SIENR_SETENRL_MASK (0xFFU) -#define PINT_SIENR_SETENRL_SHIFT (0U) -/*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n - * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. - */ -#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) -/*! @} */ - -/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ -/*! @{ */ - -#define PINT_CIENR_CENRL_MASK (0xFFU) -#define PINT_CIENR_CENRL_SHIFT (0U) -/*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit - * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level - * interrupt. - */ -#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) -/*! @} */ - -/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ -/*! @{ */ - -#define PINT_IENF_ENAF_MASK (0xFFU) -#define PINT_IENF_ENAF_SHIFT (0U) -/*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt. - * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt - * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active - * interrupt level HIGH. - */ -#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) -/*! @} */ - -/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ -/*! @{ */ - -#define PINT_SIENF_SETENAF_MASK (0xFFU) -#define PINT_SIENF_SETENAF_SHIFT (0U) -/*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n - * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable - * falling edge interrupt. - */ -#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) -/*! @} */ - -/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ -/*! @{ */ - -#define PINT_CIENF_CENAF_MASK (0xFFU) -#define PINT_CIENF_CENAF_SHIFT (0U) -/*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n - * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or - * falling edge interrupt disabled. - */ -#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) -/*! @} */ - -/*! @name RISE - Pin interrupt rising edge register */ -/*! @{ */ - -#define PINT_RISE_RDET_MASK (0xFFU) -#define PINT_RISE_RDET_SHIFT (0U) -/*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read - * 0: No rising edge has been detected on this pin since Reset or the last time a one was written - * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the - * last time a one was written to this bit. Write 1: clear rising edge detection for this pin. - */ -#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) -/*! @} */ - -/*! @name FALL - Pin interrupt falling edge register */ -/*! @{ */ - -#define PINT_FALL_FDET_MASK (0xFFU) -#define PINT_FALL_FDET_SHIFT (0U) -/*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read - * 0: No falling edge has been detected on this pin since Reset or the last time a one was - * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or - * the last time a one was written to this bit. Write 1: clear falling edge detection for this - * pin. - */ -#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) -/*! @} */ - -/*! @name IST - Pin interrupt status register */ -/*! @{ */ - -#define PINT_IST_PSTAT_MASK (0xFFU) -#define PINT_IST_PSTAT_SHIFT (0U) -/*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts - * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for - * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this - * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. - * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). - */ -#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) -/*! @} */ - -/*! @name PMCTRL - Pattern match interrupt control register */ -/*! @{ */ - -#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) -#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) -/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. - * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. - * 0b1..Pattern match. Interrupts are driven in response to pattern matches. - */ -#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) - -#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) -#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) -/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. - * 0b0..Disabled. RXEV output to the CPU is disabled. - * 0b1..Enabled. RXEV output to the CPU is enabled. - */ -#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) - -#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) -#define PINT_PMCTRL_PMAT_SHIFT (24U) -/*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field - * indicates that the corresponding product term is matched by the current state of the appropriate - * inputs. - */ -#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) -/*! @} */ - -/*! @name PMSRC - Pattern match interrupt bit-slice source register */ -/*! @{ */ - -#define PINT_PMSRC_SRC0_MASK (0x700U) -#define PINT_PMSRC_SRC0_SHIFT (8U) -/*! SRC0 - Selects the input source for bit slice 0 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. - */ -#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) - -#define PINT_PMSRC_SRC1_MASK (0x3800U) -#define PINT_PMSRC_SRC1_SHIFT (11U) -/*! SRC1 - Selects the input source for bit slice 1 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. - */ -#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) - -#define PINT_PMSRC_SRC2_MASK (0x1C000U) -#define PINT_PMSRC_SRC2_SHIFT (14U) -/*! SRC2 - Selects the input source for bit slice 2 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. - */ -#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) - -#define PINT_PMSRC_SRC3_MASK (0xE0000U) -#define PINT_PMSRC_SRC3_SHIFT (17U) -/*! SRC3 - Selects the input source for bit slice 3 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. - */ -#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) - -#define PINT_PMSRC_SRC4_MASK (0x700000U) -#define PINT_PMSRC_SRC4_SHIFT (20U) -/*! SRC4 - Selects the input source for bit slice 4 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. - */ -#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) - -#define PINT_PMSRC_SRC5_MASK (0x3800000U) -#define PINT_PMSRC_SRC5_SHIFT (23U) -/*! SRC5 - Selects the input source for bit slice 5 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. - */ -#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) - -#define PINT_PMSRC_SRC6_MASK (0x1C000000U) -#define PINT_PMSRC_SRC6_SHIFT (26U) -/*! SRC6 - Selects the input source for bit slice 6 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. - */ -#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) - -#define PINT_PMSRC_SRC7_MASK (0xE0000000U) -#define PINT_PMSRC_SRC7_SHIFT (29U) -/*! SRC7 - Selects the input source for bit slice 7 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. - */ -#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) -/*! @} */ - -/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ -/*! @{ */ - -#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) -#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) -/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. - * 0b0..No effect. Slice 0 is not an endpoint. - * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) - -#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) -#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) -/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. - * 0b0..No effect. Slice 1 is not an endpoint. - * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) - -#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) -#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) -/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. - * 0b0..No effect. Slice 2 is not an endpoint. - * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) - -#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) -#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) -/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. - * 0b0..No effect. Slice 3 is not an endpoint. - * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) - -#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) -#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) -/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. - * 0b0..No effect. Slice 4 is not an endpoint. - * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) - -#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) -#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) -/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. - * 0b0..No effect. Slice 5 is not an endpoint. - * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) - -#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) -#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) -/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. - * 0b0..No effect. Slice 6 is not an endpoint. - * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) - -#define PINT_PMCFG_CFG0_MASK (0x700U) -#define PINT_PMCFG_CFG0_SHIFT (8U) -/*! CFG0 - Specifies the match contribution condition for bit slice 0. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) - -#define PINT_PMCFG_CFG1_MASK (0x3800U) -#define PINT_PMCFG_CFG1_SHIFT (11U) -/*! CFG1 - Specifies the match contribution condition for bit slice 1. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) - -#define PINT_PMCFG_CFG2_MASK (0x1C000U) -#define PINT_PMCFG_CFG2_SHIFT (14U) -/*! CFG2 - Specifies the match contribution condition for bit slice 2. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) - -#define PINT_PMCFG_CFG3_MASK (0xE0000U) -#define PINT_PMCFG_CFG3_SHIFT (17U) -/*! CFG3 - Specifies the match contribution condition for bit slice 3. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) - -#define PINT_PMCFG_CFG4_MASK (0x700000U) -#define PINT_PMCFG_CFG4_SHIFT (20U) -/*! CFG4 - Specifies the match contribution condition for bit slice 4. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) - -#define PINT_PMCFG_CFG5_MASK (0x3800000U) -#define PINT_PMCFG_CFG5_SHIFT (23U) -/*! CFG5 - Specifies the match contribution condition for bit slice 5. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) - -#define PINT_PMCFG_CFG6_MASK (0x1C000000U) -#define PINT_PMCFG_CFG6_SHIFT (26U) -/*! CFG6 - Specifies the match contribution condition for bit slice 6. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) - -#define PINT_PMCFG_CFG7_MASK (0xE0000000U) -#define PINT_PMCFG_CFG7_SHIFT (29U) -/*! CFG7 - Specifies the match contribution condition for bit slice 7. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PINT_Register_Masks */ - - -/* PINT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PINT base address */ - #define PINT_BASE (0x50004000u) - /** Peripheral PINT base address */ - #define PINT_BASE_NS (0x40004000u) - /** Peripheral PINT base pointer */ - #define PINT ((PINT_Type *)PINT_BASE) - /** Peripheral PINT base pointer */ - #define PINT_NS ((PINT_Type *)PINT_BASE_NS) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE (0x50005000u) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE_NS (0x40005000u) - /** Peripheral SECPINT base pointer */ - #define SECPINT ((PINT_Type *)SECPINT_BASE) - /** Peripheral SECPINT base pointer */ - #define SECPINT_NS ((PINT_Type *)SECPINT_BASE_NS) - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS { PINT, SECPINT } - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS_NS { PINT_BASE_NS, SECPINT_BASE_NS } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS_NS { PINT_NS, SECPINT_NS } -#else - /** Peripheral PINT base address */ - #define PINT_BASE (0x40004000u) - /** Peripheral PINT base pointer */ - #define PINT ((PINT_Type *)PINT_BASE) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE (0x40005000u) - /** Peripheral SECPINT base pointer */ - #define SECPINT ((PINT_Type *)SECPINT_BASE) - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS { PINT, SECPINT } -#endif -/** Interrupt vectors for the PINT peripheral type */ -#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn } - -/*! - * @} - */ /* end of group PINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PLU Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PLU_Peripheral_Access_Layer PLU Peripheral Access Layer - * @{ - */ - -/** PLU - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x20 */ - __IO uint32_t INP_MUX[5]; /**< LUTn input x MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */ - uint8_t RESERVED_0[12]; - } LUT[26]; - uint8_t RESERVED_0[1216]; - __IO uint32_t LUT_TRUTH[26]; /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25, array offset: 0x800, array step: 0x4 */ - uint8_t RESERVED_1[152]; - __I uint32_t OUTPUTS; /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */ - __IO uint32_t WAKEINT_CTRL; /**< Wakeup interrupt control for PLU, offset: 0x904 */ - uint8_t RESERVED_2[760]; - __IO uint32_t OUTPUT_MUX[8]; /**< Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */ -} PLU_Type; - -/* ---------------------------------------------------------------------------- - -- PLU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PLU_Register_Masks PLU Register Masks - * @{ - */ - -/*! @name LUT_INP_MUX - LUTn input x MUX */ -/*! @{ */ - -#define PLU_LUT_INP_MUX_LUTn_INPx_MASK (0x3FU) -#define PLU_LUT_INP_MUX_LUTn_INPx_SHIFT (0U) -/*! LUTn_INPx - Selects the input source to be connected to LUT25 input4. For each LUT, the slot - * associated with the output from LUTn itself is tied low. - * 0b000000..The PLU primary inputs 0. - * 0b000001..The PLU primary inputs 1. - * 0b000010..The PLU primary inputs 2. - * 0b000011..The PLU primary inputs 3. - * 0b000100..The PLU primary inputs 4. - * 0b000101..The PLU primary inputs 5. - * 0b000110..The output of LUT0. - * 0b000111..The output of LUT1. - * 0b001000..The output of LUT2. - * 0b001001..The output of LUT3. - * 0b001010..The output of LUT4. - * 0b001011..The output of LUT5. - * 0b001100..The output of LUT6. - * 0b001101..The output of LUT7. - * 0b001110..The output of LUT8. - * 0b001111..The output of LUT9. - * 0b010000..The output of LUT10. - * 0b010001..The output of LUT11. - * 0b010010..The output of LUT12. - * 0b010011..The output of LUT13. - * 0b010100..The output of LUT14. - * 0b010101..The output of LUT15. - * 0b010110..The output of LUT16. - * 0b010111..The output of LUT17. - * 0b011000..The output of LUT18. - * 0b011001..The output of LUT19. - * 0b011010..The output of LUT20. - * 0b011011..The output of LUT21. - * 0b011100..The output of LUT22. - * 0b011101..The output of LUT23. - * 0b011110..The output of LUT24. - * 0b011111..The output of LUT25. - * 0b100000..state(0). - * 0b100001..state(1). - * 0b100010..state(2). - * 0b100011..state(3). - */ -#define PLU_LUT_INP_MUX_LUTn_INPx(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_MUX_LUTn_INPx_SHIFT)) & PLU_LUT_INP_MUX_LUTn_INPx_MASK) -/*! @} */ - -/* The count of PLU_LUT_INP_MUX */ -#define PLU_LUT_INP_MUX_COUNT (26U) - -/* The count of PLU_LUT_INP_MUX */ -#define PLU_LUT_INP_MUX_COUNT2 (5U) - -/*! @name LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */ -/*! @{ */ - -#define PLU_LUT_TRUTH_LUTn_TRUTH_MASK (0xFFFFFFFFU) -#define PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT (0U) -/*! LUTn_TRUTH - Specifies the Truth Table contents for LUT25.. - */ -#define PLU_LUT_TRUTH_LUTn_TRUTH(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT)) & PLU_LUT_TRUTH_LUTn_TRUTH_MASK) -/*! @} */ - -/* The count of PLU_LUT_TRUTH */ -#define PLU_LUT_TRUTH_COUNT (26U) - -/*! @name OUTPUTS - Provides the current state of the 8 designated PLU Outputs. */ -/*! @{ */ - -#define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU) -#define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U) -/*! OUTPUT_STATE - Provides the current state of the 8 designated PLU Outputs.. - */ -#define PLU_OUTPUTS_OUTPUT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK) -/*! @} */ - -/*! @name WAKEINT_CTRL - Wakeup interrupt control for PLU */ -/*! @{ */ - -#define PLU_WAKEINT_CTRL_MASK_MASK (0xFFU) -#define PLU_WAKEINT_CTRL_MASK_SHIFT (0U) -/*! MASK - Interrupt mask (which of the 8 PLU Outputs contribute to interrupt) - */ -#define PLU_WAKEINT_CTRL_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_MASK_SHIFT)) & PLU_WAKEINT_CTRL_MASK_MASK) - -#define PLU_WAKEINT_CTRL_FILTER_MODE_MASK (0x300U) -#define PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT (8U) -/*! FILTER_MODE - control input of the PLU, add filtering for glitch. - * 0b00..Bypass mode. - * 0b01..Filter 1 clock period. - * 0b10..Filter 2 clock period. - * 0b11..Filter 3 clock period. - */ -#define PLU_WAKEINT_CTRL_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_MODE_MASK) - -#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK (0xC00U) -#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT (10U) -/*! FILTER_CLKSEL - hclk is divided by 2**filter_clksel. - * 0b00..Selects the 1 MHz low-power oscillator as the filter clock. - * 0b01..Selects the 12 Mhz FRO as the filter clock. - * 0b10..Selects a third filter clock source, if provided. - * 0b11..Reserved. - */ -#define PLU_WAKEINT_CTRL_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK) - -#define PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK (0x1000U) -#define PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT (12U) -/*! LATCH_ENABLE - latch the interrupt , then can be cleared with next bit INTR_CLEAR - */ -#define PLU_WAKEINT_CTRL_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK) - -#define PLU_WAKEINT_CTRL_INTR_CLEAR_MASK (0x2000U) -#define PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT (13U) -/*! INTR_CLEAR - Write to clear wakeint_latched - */ -#define PLU_WAKEINT_CTRL_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK) -/*! @} */ - -/*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7 */ -/*! @{ */ - -#define PLU_OUTPUT_MUX_OUTPUTn_MASK (0x1FU) -#define PLU_OUTPUT_MUX_OUTPUTn_SHIFT (0U) -/*! OUTPUTn - Selects the source to be connected to PLU Output 7. - * 0b00000..The PLU output 0. - * 0b00001..The PLU output 1. - * 0b00010..The PLU output 2. - * 0b00011..The PLU output 3. - * 0b00100..The PLU output 4. - * 0b00101..The PLU output 5. - * 0b00110..The PLU output 6. - * 0b00111..The PLU output 7. - * 0b01000..The PLU output 8. - * 0b01001..The PLU output 9. - * 0b01010..The PLU output 10. - * 0b01011..The PLU output 11. - * 0b01100..The PLU output 12. - * 0b01101..The PLU output 13. - * 0b01110..The PLU output 14. - * 0b01111..The PLU output 15. - * 0b10000..The PLU output 16. - * 0b10001..The PLU output 17. - * 0b10010..The PLU output 18. - * 0b10011..The PLU output 19. - * 0b10100..The PLU output 20. - * 0b10101..The PLU output 21. - * 0b10110..The PLU output 22. - * 0b10111..The PLU output 23. - * 0b11000..The PLU output 24. - * 0b11001..The PLU output 25. - * 0b11010..state(0). - * 0b11011..state(1). - * 0b11100..state(2). - * 0b11101..state(3). - */ -#define PLU_OUTPUT_MUX_OUTPUTn(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUTn_SHIFT)) & PLU_OUTPUT_MUX_OUTPUTn_MASK) -/*! @} */ - -/* The count of PLU_OUTPUT_MUX */ -#define PLU_OUTPUT_MUX_COUNT (8U) - - -/*! - * @} - */ /* end of group PLU_Register_Masks */ - - -/* PLU - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PLU base address */ - #define PLU_BASE (0x5003D000u) - /** Peripheral PLU base address */ - #define PLU_BASE_NS (0x4003D000u) - /** Peripheral PLU base pointer */ - #define PLU ((PLU_Type *)PLU_BASE) - /** Peripheral PLU base pointer */ - #define PLU_NS ((PLU_Type *)PLU_BASE_NS) - /** Array initializer of PLU peripheral base addresses */ - #define PLU_BASE_ADDRS { PLU_BASE } - /** Array initializer of PLU peripheral base pointers */ - #define PLU_BASE_PTRS { PLU } - /** Array initializer of PLU peripheral base addresses */ - #define PLU_BASE_ADDRS_NS { PLU_BASE_NS } - /** Array initializer of PLU peripheral base pointers */ - #define PLU_BASE_PTRS_NS { PLU_NS } -#else - /** Peripheral PLU base address */ - #define PLU_BASE (0x4003D000u) - /** Peripheral PLU base pointer */ - #define PLU ((PLU_Type *)PLU_BASE) - /** Array initializer of PLU peripheral base addresses */ - #define PLU_BASE_ADDRS { PLU_BASE } - /** Array initializer of PLU peripheral base pointers */ - #define PLU_BASE_PTRS { PLU } -#endif - -/*! - * @} - */ /* end of group PLU_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer - * @{ - */ - -/** PMC - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4]; - __I uint32_t STATUS; /**< Power Management Controller FSM (Finite State Machines) status, offset: 0x4 */ - __IO uint32_t RESETCTRL; /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x8 */ - uint8_t RESERVED_1[4]; - __IO uint32_t DCDC0; /**< DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x10 */ - __IO uint32_t DCDC1; /**< DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x14 */ - uint8_t RESERVED_2[4]; - __IO uint32_t LDOPMU; /**< Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x1C */ - uint8_t RESERVED_3[16]; - __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */ - uint8_t RESERVED_4[12]; - __IO uint32_t REFFASTWKUP; /**< Analog References fast wake-up Control register [Reset by: PoR], offset: 0x40 */ - uint8_t RESERVED_5[8]; - __IO uint32_t XTAL32K; /**< 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x4C */ - __IO uint32_t COMP; /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x50 */ - uint8_t RESERVED_6[16]; - __IO uint32_t WAKEUPIOCTRL; /**< Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset], offset: 0x64 */ - __IO uint32_t WAKEIOCAUSE; /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */ - uint8_t RESERVED_7[8]; - __IO uint32_t STATUSCLK; /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */ - uint8_t RESERVED_8[12]; - __IO uint32_t AOREG1; /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset], offset: 0x84 */ - uint8_t RESERVED_9[8]; - __IO uint32_t MISCCTRL; /**< Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x90 */ - uint8_t RESERVED_10[4]; - __IO uint32_t RTCOSC32K; /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x98 */ - __IO uint32_t OSTIMERr; /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C */ - uint8_t RESERVED_11[24]; - __IO uint32_t PDRUNCFG0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */ - uint8_t RESERVED_12[4]; - __O uint32_t PDRUNCFGSET0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */ - uint8_t RESERVED_13[4]; - __O uint32_t PDRUNCFGCLR0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */ - uint8_t RESERVED_14[8]; - __IO uint32_t SRAMCTRL; /**< All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xD4 */ -} PMC_Type; - -/* ---------------------------------------------------------------------------- - -- PMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Register_Masks PMC Register Masks - * @{ - */ - -/*! @name STATUS - Power Management Controller FSM (Finite State Machines) status */ -/*! @{ */ - -#define PMC_STATUS_BOOTMODE_MASK (0xC0000U) -#define PMC_STATUS_BOOTMODE_SHIFT (18U) -/*! BOOTMODE - Latest IC Boot cause:. - * 0b00..Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset). - * 0b01..Latest IC boot was from DEEP SLEEP low power mode. - * 0b10..Latest IC boot was from POWER DOWN low power mode. - * 0b11..Latest IC boot was from DEEP POWER DOWN low power mode. - */ -#define PMC_STATUS_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_BOOTMODE_SHIFT)) & PMC_STATUS_BOOTMODE_MASK) -/*! @} */ - -/*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U) -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U) -/*! DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). - * 0b0..Reset event from DEEP POWER DOWN mode is disable. - * 0b1..Reset event from DEEP POWER DOWN mode is enable. - */ -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK) - -#define PMC_RESETCTRL_BODVBATRESETENABLE_MASK (0x2U) -#define PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT (1U) -/*! BODVBATRESETENABLE - BOD VBAT reset enable. - * 0b0..BOD VBAT reset is disable. - * 0b1..BOD VBAT reset is enable. - */ -#define PMC_RESETCTRL_BODVBATRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENABLE_MASK) - -#define PMC_RESETCTRL_BODCORERESETENABLE_MASK (0x4U) -#define PMC_RESETCTRL_BODCORERESETENABLE_SHIFT (2U) -/*! BODCORERESETENABLE - BOD CORE reset enable. - * 0b0..BOD CORE reset is disable. - * 0b1..BOD CORE reset is enable. - */ -#define PMC_RESETCTRL_BODCORERESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENABLE_SHIFT)) & PMC_RESETCTRL_BODCORERESETENABLE_MASK) - -#define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U) -#define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U) -/*! SWRRESETENABLE - Software reset enable. - * 0b0..Software reset is disable. - * 0b1..Software reset is enable. - */ -#define PMC_RESETCTRL_SWRRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK) -/*! @} */ - -/*! @name DCDC0 - DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_DCDC0_RC_MASK (0x3FU) -#define PMC_DCDC0_RC_SHIFT (0U) -/*! RC - Constant On-Time calibration. - */ -#define PMC_DCDC0_RC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_RC_SHIFT)) & PMC_DCDC0_RC_MASK) - -#define PMC_DCDC0_ICOMP_MASK (0xC0U) -#define PMC_DCDC0_ICOMP_SHIFT (6U) -/*! ICOMP - Select the type of ZCD comparator. - */ -#define PMC_DCDC0_ICOMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICOMP_SHIFT)) & PMC_DCDC0_ICOMP_MASK) - -#define PMC_DCDC0_ISEL_MASK (0x300U) -#define PMC_DCDC0_ISEL_SHIFT (8U) -/*! ISEL - Alter Internal biasing currents. - */ -#define PMC_DCDC0_ISEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ISEL_SHIFT)) & PMC_DCDC0_ISEL_MASK) - -#define PMC_DCDC0_ICENABLE_MASK (0x400U) -#define PMC_DCDC0_ICENABLE_SHIFT (10U) -/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD. - */ -#define PMC_DCDC0_ICENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICENABLE_SHIFT)) & PMC_DCDC0_ICENABLE_MASK) - -#define PMC_DCDC0_TMOS_MASK (0xF800U) -#define PMC_DCDC0_TMOS_SHIFT (11U) -/*! TMOS - One-shot generator reference current trimming signal. - */ -#define PMC_DCDC0_TMOS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_TMOS_SHIFT)) & PMC_DCDC0_TMOS_MASK) - -#define PMC_DCDC0_DISABLEISENSE_MASK (0x10000U) -#define PMC_DCDC0_DISABLEISENSE_SHIFT (16U) -/*! DISABLEISENSE - Disable Current sensing. - */ -#define PMC_DCDC0_DISABLEISENSE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_DISABLEISENSE_SHIFT)) & PMC_DCDC0_DISABLEISENSE_MASK) - -#define PMC_DCDC0_VOUT_MASK (0x1E0000U) -#define PMC_DCDC0_VOUT_SHIFT (17U) -/*! VOUT - Set output regulation voltage. - * 0b0000..0.95 V. - * 0b0001..0.975 V. - * 0b0010..1 V. - * 0b0011..1.025 V. - * 0b0100..1.05 V. - * 0b0101..1.075 V. - * 0b0110..1.1 V. - * 0b0111..1.125 V. - * 0b1000..1.15 V. - * 0b1001..1.175 V. - * 0b1010..1.2 V. - */ -#define PMC_DCDC0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_SHIFT)) & PMC_DCDC0_VOUT_MASK) - -#define PMC_DCDC0_SLICINGENABLE_MASK (0x200000U) -#define PMC_DCDC0_SLICINGENABLE_SHIFT (21U) -/*! SLICINGENABLE - Enable staggered switching of power switches. - */ -#define PMC_DCDC0_SLICINGENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_SLICINGENABLE_SHIFT)) & PMC_DCDC0_SLICINGENABLE_MASK) - -#define PMC_DCDC0_INDUCTORCLAMPENABLE_MASK (0x400000U) -#define PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT (22U) -/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. - */ -#define PMC_DCDC0_INDUCTORCLAMPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT)) & PMC_DCDC0_INDUCTORCLAMPENABLE_MASK) - -#define PMC_DCDC0_VOUT_PWD_MASK (0x7800000U) -#define PMC_DCDC0_VOUT_PWD_SHIFT (23U) -/*! VOUT_PWD - Set output regulation voltage during Deep Sleep. - */ -#define PMC_DCDC0_VOUT_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_PWD_SHIFT)) & PMC_DCDC0_VOUT_PWD_MASK) -/*! @} */ - -/*! @name DCDC1 - DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_DCDC1_RTRIMOFFET_MASK (0xFU) -#define PMC_DCDC1_RTRIMOFFET_SHIFT (0U) -/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator. - */ -#define PMC_DCDC1_RTRIMOFFET(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RTRIMOFFET_SHIFT)) & PMC_DCDC1_RTRIMOFFET_MASK) - -#define PMC_DCDC1_RSENSETRIM_MASK (0xF0U) -#define PMC_DCDC1_RSENSETRIM_SHIFT (4U) -/*! RSENSETRIM - Adjust Max inductor peak current limiting. - */ -#define PMC_DCDC1_RSENSETRIM(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RSENSETRIM_SHIFT)) & PMC_DCDC1_RSENSETRIM_MASK) - -#define PMC_DCDC1_DTESTENABLE_MASK (0x100U) -#define PMC_DCDC1_DTESTENABLE_SHIFT (8U) -/*! DTESTENABLE - Enable Digital test signals. - */ -#define PMC_DCDC1_DTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTENABLE_SHIFT)) & PMC_DCDC1_DTESTENABLE_MASK) - -#define PMC_DCDC1_SETCURVE_MASK (0x600U) -#define PMC_DCDC1_SETCURVE_SHIFT (9U) -/*! SETCURVE - Bandgap calibration parameter. - */ -#define PMC_DCDC1_SETCURVE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETCURVE_SHIFT)) & PMC_DCDC1_SETCURVE_MASK) - -#define PMC_DCDC1_SETDC_MASK (0x7800U) -#define PMC_DCDC1_SETDC_SHIFT (11U) -/*! SETDC - Bandgap calibration parameter. - */ -#define PMC_DCDC1_SETDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETDC_SHIFT)) & PMC_DCDC1_SETDC_MASK) - -#define PMC_DCDC1_DTESTSEL_MASK (0x38000U) -#define PMC_DCDC1_DTESTSEL_SHIFT (15U) -/*! DTESTSEL - Select the output signal for test. - */ -#define PMC_DCDC1_DTESTSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTSEL_SHIFT)) & PMC_DCDC1_DTESTSEL_MASK) - -#define PMC_DCDC1_ISCALEENABLE_MASK (0x40000U) -#define PMC_DCDC1_ISCALEENABLE_SHIFT (18U) -/*! ISCALEENABLE - Modify COT behavior. - */ -#define PMC_DCDC1_ISCALEENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_ISCALEENABLE_SHIFT)) & PMC_DCDC1_ISCALEENABLE_MASK) - -#define PMC_DCDC1_FORCEBYPASS_MASK (0x80000U) -#define PMC_DCDC1_FORCEBYPASS_SHIFT (19U) -/*! FORCEBYPASS - Force bypass mode. - */ -#define PMC_DCDC1_FORCEBYPASS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEBYPASS_SHIFT)) & PMC_DCDC1_FORCEBYPASS_MASK) - -#define PMC_DCDC1_TRIMAUTOCOT_MASK (0xF00000U) -#define PMC_DCDC1_TRIMAUTOCOT_SHIFT (20U) -/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. - */ -#define PMC_DCDC1_TRIMAUTOCOT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TRIMAUTOCOT_SHIFT)) & PMC_DCDC1_TRIMAUTOCOT_MASK) - -#define PMC_DCDC1_FORCEFULLCYCLE_MASK (0x1000000U) -#define PMC_DCDC1_FORCEFULLCYCLE_SHIFT (24U) -/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. - */ -#define PMC_DCDC1_FORCEFULLCYCLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEFULLCYCLE_SHIFT)) & PMC_DCDC1_FORCEFULLCYCLE_MASK) - -#define PMC_DCDC1_LCENABLE_MASK (0x2000000U) -#define PMC_DCDC1_LCENABLE_SHIFT (25U) -/*! LCENABLE - Change the range of the peak detector of current inside the inductor. - */ -#define PMC_DCDC1_LCENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_LCENABLE_SHIFT)) & PMC_DCDC1_LCENABLE_MASK) - -#define PMC_DCDC1_TOFF_MASK (0x7C000000U) -#define PMC_DCDC1_TOFF_SHIFT (26U) -/*! TOFF - Constant Off-Time calibration input. - */ -#define PMC_DCDC1_TOFF(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFF_SHIFT)) & PMC_DCDC1_TOFF_MASK) - -#define PMC_DCDC1_TOFFENABLE_MASK (0x80000000U) -#define PMC_DCDC1_TOFFENABLE_SHIFT (31U) -/*! TOFFENABLE - Enable Constant Off-Time feature. - */ -#define PMC_DCDC1_TOFFENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFFENABLE_SHIFT)) & PMC_DCDC1_TOFFENABLE_MASK) -/*! @} */ - -/*! @name LDOPMU - Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_LDOPMU_VADJ_MASK (0x1FU) -#define PMC_LDOPMU_VADJ_SHIFT (0U) -/*! VADJ - Sets the Always-On domain LDO output level. - * 0b00000..1.22 V. - * 0b00001..0.7 V. - * 0b00010..0.725 V. - * 0b00011..0.75 V. - * 0b00100..0.775 V. - * 0b00101..0.8 V. - * 0b00110..0.825 V. - * 0b00111..0.85 V. - * 0b01000..0.875 V. - * 0b01001..0.9 V. - * 0b01010..0.96 V. - * 0b01011..0.97 V. - * 0b01100..0.98 V. - * 0b01101..0.99 V. - * 0b01110..1 V. - * 0b01111..1.01 V. - * 0b10000..1.02 V. - * 0b10001..1.03 V. - * 0b10010..1.04 V. - * 0b10011..1.05 V. - * 0b10100..1.06 V. - * 0b10101..1.07 V. - * 0b10110..1.08 V. - * 0b10111..1.09 V. - * 0b11000..1.1 V. - * 0b11001..1.11 V. - * 0b11010..1.12 V. - * 0b11011..1.13 V. - * 0b11100..1.14 V. - * 0b11101..1.15 V. - * 0b11110..1.16 V. - * 0b11111..1.22 V. - */ -#define PMC_LDOPMU_VADJ(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_SHIFT)) & PMC_LDOPMU_VADJ_MASK) - -#define PMC_LDOPMU_VADJ_PWD_MASK (0x3E0U) -#define PMC_LDOPMU_VADJ_PWD_SHIFT (5U) -/*! VADJ_PWD - Sets the Always-On domain LDO output level in all power down modes. - */ -#define PMC_LDOPMU_VADJ_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_PWD_SHIFT)) & PMC_LDOPMU_VADJ_PWD_MASK) - -#define PMC_LDOPMU_VADJ_BOOST_MASK (0x7C00U) -#define PMC_LDOPMU_VADJ_BOOST_SHIFT (10U) -/*! VADJ_BOOST - Sets the Always-On domain LDO Boost output level. - */ -#define PMC_LDOPMU_VADJ_BOOST(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_MASK) - -#define PMC_LDOPMU_VADJ_BOOST_PWD_MASK (0xF8000U) -#define PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT (15U) -/*! VADJ_BOOST_PWD - Sets the Always-On domain LDO Boost output level in all power down modes. - */ -#define PMC_LDOPMU_VADJ_BOOST_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_PWD_MASK) - -#define PMC_LDOPMU_BOOST_ENA_MASK (0x1000000U) -#define PMC_LDOPMU_BOOST_ENA_SHIFT (24U) -/*! BOOST_ENA - Control the LDO AO boost mode in ACTIVE mode. - * 0b0..LDO AO Boost Mode is disable. - * 0b1..LDO AO Boost Mode is enable. - */ -#define PMC_LDOPMU_BOOST_ENA(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_SHIFT)) & PMC_LDOPMU_BOOST_ENA_MASK) - -#define PMC_LDOPMU_BOOST_ENA_PWD_MASK (0x2000000U) -#define PMC_LDOPMU_BOOST_ENA_PWD_SHIFT (25U) -/*! BOOST_ENA_PWD - Control the LDO AO boost mode in the different low power modes (DEEP SLEEP, POWERDOWN, and DEEP POWER DOWN). - * 0b0..LDO AO Boost Mode is disable. - * 0b1..LDO AO Boost Mode is enable. - */ -#define PMC_LDOPMU_BOOST_ENA_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_PWD_SHIFT)) & PMC_LDOPMU_BOOST_ENA_PWD_MASK) -/*! @} */ - -/*! @name BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] */ -/*! @{ */ - -#define PMC_BODVBAT_TRIGLVL_MASK (0x1FU) -#define PMC_BODVBAT_TRIGLVL_SHIFT (0U) -/*! TRIGLVL - BoD trigger level. - * 0b00000..1.00 V. - * 0b00001..1.10 V. - * 0b00010..1.20 V. - * 0b00011..1.30 V. - * 0b00100..1.40 V. - * 0b00101..1.50 V. - * 0b00110..1.60 V. - * 0b00111..1.65 V. - * 0b01000..1.70 V. - * 0b01001..1.75 V. - * 0b01010..1.80 V. - * 0b01011..1.90 V. - * 0b01100..2.00 V. - * 0b01101..2.10 V. - * 0b01110..2.20 V. - * 0b01111..2.30 V. - * 0b10000..2.40 V. - * 0b10001..2.50 V. - * 0b10010..2.60 V. - * 0b10011..2.70 V. - * 0b10100..2.806 V. - * 0b10101..2.90 V. - * 0b10110..3.00 V. - * 0b10111..3.10 V. - * 0b11000..3.20 V. - * 0b11001..3.30 V. - * 0b11010..3.30 V. - * 0b11011..3.30 V. - * 0b11100..3.30 V. - * 0b11101..3.30 V. - * 0b11110..3.30 V. - * 0b11111..3.30 V. - */ -#define PMC_BODVBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_TRIGLVL_SHIFT)) & PMC_BODVBAT_TRIGLVL_MASK) - -#define PMC_BODVBAT_HYST_MASK (0x60U) -#define PMC_BODVBAT_HYST_SHIFT (5U) -/*! HYST - BoD Hysteresis control. - * 0b00..25 mV. - * 0b01..50 mV. - * 0b10..75 mV. - * 0b11..100 mV. - */ -#define PMC_BODVBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK) -/*! @} */ - -/*! @name REFFASTWKUP - Analog References fast wake-up Control register [Reset by: PoR] */ -/*! @{ */ - -#define PMC_REFFASTWKUP_LPWKUP_MASK (0x1U) -#define PMC_REFFASTWKUP_LPWKUP_SHIFT (0U) -/*! LPWKUP - Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP POWER DOWN): . - * 0b0..Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode. - * 0b1..Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode. - */ -#define PMC_REFFASTWKUP_LPWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_LPWKUP_SHIFT)) & PMC_REFFASTWKUP_LPWKUP_MASK) - -#define PMC_REFFASTWKUP_HWWKUP_MASK (0x2U) -#define PMC_REFFASTWKUP_HWWKUP_SHIFT (1U) -/*! HWWKUP - Analog References fast wake-up in case of Hardware Pin reset: . - * 0b0..Analog References fast wake-up feature is disabled in case of Hardware Pin reset. - * 0b1..Analog References fast wake-up feature is enabled in case of Hardware Pin reset. - */ -#define PMC_REFFASTWKUP_HWWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_HWWKUP_SHIFT)) & PMC_REFFASTWKUP_HWWKUP_MASK) -/*! @} */ - -/*! @name XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_XTAL32K_IREF_MASK (0x6U) -#define PMC_XTAL32K_IREF_SHIFT (1U) -/*! IREF - reference output current selection inputs. - */ -#define PMC_XTAL32K_IREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IREF_SHIFT)) & PMC_XTAL32K_IREF_MASK) - -#define PMC_XTAL32K_TEST_MASK (0x8U) -#define PMC_XTAL32K_TEST_SHIFT (3U) -/*! TEST - Oscillator Test Mode. - */ -#define PMC_XTAL32K_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK) - -#define PMC_XTAL32K_IBIAS_MASK (0x30U) -#define PMC_XTAL32K_IBIAS_SHIFT (4U) -/*! IBIAS - bias current selection inputs. - */ -#define PMC_XTAL32K_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IBIAS_SHIFT)) & PMC_XTAL32K_IBIAS_MASK) - -#define PMC_XTAL32K_AMPL_MASK (0xC0U) -#define PMC_XTAL32K_AMPL_SHIFT (6U) -/*! AMPL - oscillator amplitude selection inputs. - */ -#define PMC_XTAL32K_AMPL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_AMPL_SHIFT)) & PMC_XTAL32K_AMPL_MASK) - -#define PMC_XTAL32K_CAPBANKIN_MASK (0x7F00U) -#define PMC_XTAL32K_CAPBANKIN_SHIFT (8U) -/*! CAPBANKIN - Capa bank setting input. - */ -#define PMC_XTAL32K_CAPBANKIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKIN_SHIFT)) & PMC_XTAL32K_CAPBANKIN_MASK) - -#define PMC_XTAL32K_CAPBANKOUT_MASK (0x3F8000U) -#define PMC_XTAL32K_CAPBANKOUT_SHIFT (15U) -/*! CAPBANKOUT - Capa bank setting output. - */ -#define PMC_XTAL32K_CAPBANKOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKOUT_SHIFT)) & PMC_XTAL32K_CAPBANKOUT_MASK) - -#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK (0x400000U) -#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT (22U) -/*! CAPTESTSTARTSRCSEL - Source selection for xo32k_captest_start_ao_set. - * 0b0..Sourced from CAPTESTSTART. - * 0b1..Sourced from calibration. - */ -#define PMC_XTAL32K_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT)) & PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK) - -#define PMC_XTAL32K_CAPTESTSTART_MASK (0x800000U) -#define PMC_XTAL32K_CAPTESTSTART_SHIFT (23U) -/*! CAPTESTSTART - Start test. - */ -#define PMC_XTAL32K_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTART_SHIFT)) & PMC_XTAL32K_CAPTESTSTART_MASK) - -#define PMC_XTAL32K_CAPTESTENABLE_MASK (0x1000000U) -#define PMC_XTAL32K_CAPTESTENABLE_SHIFT (24U) -/*! CAPTESTENABLE - Enable signal for cap test. - */ -#define PMC_XTAL32K_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTENABLE_SHIFT)) & PMC_XTAL32K_CAPTESTENABLE_MASK) - -#define PMC_XTAL32K_CAPTESTOSCINSEL_MASK (0x2000000U) -#define PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT (25U) -/*! CAPTESTOSCINSEL - Select the input for test. - * 0b0..Oscillator output pin (osc_out). - * 0b1..Oscillator input pin (osc_in). - */ -#define PMC_XTAL32K_CAPTESTOSCINSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT)) & PMC_XTAL32K_CAPTESTOSCINSEL_MASK) -/*! @} */ - -/*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_COMP_HYST_MASK (0x2U) -#define PMC_COMP_HYST_SHIFT (1U) -/*! HYST - Hysteris when hyst = '1'. - * 0b0..Hysteresis is disable. - * 0b1..Hysteresis is enable. - */ -#define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK) - -#define PMC_COMP_VREFINPUT_MASK (0x4U) -#define PMC_COMP_VREFINPUT_SHIFT (2U) -/*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). - * 0b0..Select internal VREF. - * 0b1..Select VDDA. - */ -#define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK) - -#define PMC_COMP_LOWPOWER_MASK (0x8U) -#define PMC_COMP_LOWPOWER_SHIFT (3U) -/*! LOWPOWER - Low power mode. - * 0b0..High speed mode. - * 0b1..Low power mode (Low speed). - */ -#define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK) - -#define PMC_COMP_PMUX_MASK (0x70U) -#define PMC_COMP_PMUX_SHIFT (4U) -/*! PMUX - Control word for P multiplexer:. - * 0b000..VREF (See fiedl VREFINPUT). - * 0b001..Pin P0_0. - * 0b010..Pin P0_9. - * 0b011..Pin P0_18. - * 0b100..Pin P1_14. - * 0b101..Pin P2_23. - */ -#define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK) - -#define PMC_COMP_NMUX_MASK (0x380U) -#define PMC_COMP_NMUX_SHIFT (7U) -/*! NMUX - Control word for N multiplexer:. - * 0b000..VREF (See field VREFINPUT). - * 0b001..Pin P0_0. - * 0b010..Pin P0_9. - * 0b011..Pin P0_18. - * 0b100..Pin P1_14. - * 0b101..Pin P2_23. - */ -#define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK) - -#define PMC_COMP_VREF_MASK (0x7C00U) -#define PMC_COMP_VREF_SHIFT (10U) -/*! VREF - Control reference voltage step, per steps of (VREFINPUT/31). - */ -#define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK) - -#define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U) -#define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U) -/*! FILTERCGF_SAMPLEMODE - Control the filtering of the Analog Comparator output. - * 0b00..Bypass mode. - * 0b01..Filter 1 clock period. - * 0b10..Filter 2 clock period. - * 0b11..Filter 3 clock period. - */ -#define PMC_COMP_FILTERCGF_SAMPLEMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK) - -#define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U) -#define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U) -/*! FILTERCGF_CLKDIV - Filter Clock divider. - * 0b000..Filter clock period duration equals 1 Analog Comparator clock period. - * 0b001..Filter clock period duration equals 2 Analog Comparator clock period. - * 0b010..Filter clock period duration equals 4 Analog Comparator clock period. - * 0b011..Filter clock period duration equals 8 Analog Comparator clock period. - * 0b100..Filter clock period duration equals 16 Analog Comparator clock period. - * 0b101..Filter clock period duration equals 32 Analog Comparator clock period. - * 0b110..Filter clock period duration equals 64 Analog Comparator clock period. - * 0b111..Filter clock period duration equals 128 Analog Comparator clock period. - */ -#define PMC_COMP_FILTERCGF_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK) -/*! @} */ - -/*! @name WAKEUPIOCTRL - Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] */ -/*! @{ */ - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK (0x1U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT (0U) -/*! RISINGEDGEWAKEUP0 - Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disable. - * 0b1..Rising edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK (0x2U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT (1U) -/*! FALLINGEDGEWAKEUP0 - Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disable. - * 0b1..Falling edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK) - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK (0x4U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT (2U) -/*! RISINGEDGEWAKEUP1 - Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disable. - * 0b1..Rising edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK (0x8U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT (3U) -/*! FALLINGEDGEWAKEUP1 - Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disable. - * 0b1..Falling edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK) - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK (0x10U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT (4U) -/*! RISINGEDGEWAKEUP2 - Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disable. - * 0b1..Rising edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK (0x20U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT (5U) -/*! FALLINGEDGEWAKEUP2 - Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disable. - * 0b1..Falling edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK) - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK (0x40U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT (6U) -/*! RISINGEDGEWAKEUP3 - Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disable. - * 0b1..Rising edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK (0x80U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT (7U) -/*! FALLINGEDGEWAKEUP3 - Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disable. - * 0b1..Falling edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUP0_MASK (0x100U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUP0_SHIFT (8U) -/*! MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP0_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUP1_MASK (0x200U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUP1_SHIFT (9U) -/*! MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP1_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUP2_MASK (0x400U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUP2_SHIFT (10U) -/*! MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP2_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUP3_MASK (0x800U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUP3_SHIFT (11U) -/*! MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP3_MASK) -/*! @} */ - -/*! @name WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode */ -/*! @{ */ - -#define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U) -#define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U) -/*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0. - */ -#define PMC_WAKEIOCAUSE_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK) - -#define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U) -#define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U) -/*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1. - */ -#define PMC_WAKEIOCAUSE_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK) - -#define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U) -#define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U) -/*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2. - */ -#define PMC_WAKEIOCAUSE_WAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK) - -#define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U) -#define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U) -/*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 3. - */ -#define PMC_WAKEIOCAUSE_WAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK) -/*! @} */ - -/*! @name STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U) -#define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U) -/*! XTAL32KOK - XTAL oscillator 32 K OK signal. - */ -#define PMC_STATUSCLK_XTAL32KOK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK) - -#define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U) -#define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U) -/*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. - * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared. - * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared. - */ -#define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK) -/*! @} */ - -/*! @name AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_AOREG1_POR_MASK (0x10U) -#define PMC_AOREG1_POR_SHIFT (4U) -/*! POR - The last chip reset was caused by a Power On Reset. - */ -#define PMC_AOREG1_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_POR_SHIFT)) & PMC_AOREG1_POR_MASK) - -#define PMC_AOREG1_PADRESET_MASK (0x20U) -#define PMC_AOREG1_PADRESET_SHIFT (5U) -/*! PADRESET - The last chip reset was caused by a Pin Reset. - */ -#define PMC_AOREG1_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_PADRESET_SHIFT)) & PMC_AOREG1_PADRESET_MASK) - -#define PMC_AOREG1_BODRESET_MASK (0x40U) -#define PMC_AOREG1_BODRESET_SHIFT (6U) -/*! BODRESET - The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. - */ -#define PMC_AOREG1_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BODRESET_SHIFT)) & PMC_AOREG1_BODRESET_MASK) - -#define PMC_AOREG1_SYSTEMRESET_MASK (0x80U) -#define PMC_AOREG1_SYSTEMRESET_SHIFT (7U) -/*! SYSTEMRESET - The last chip reset was caused by a System Reset requested by the ARM CPU. - */ -#define PMC_AOREG1_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SYSTEMRESET_SHIFT)) & PMC_AOREG1_SYSTEMRESET_MASK) - -#define PMC_AOREG1_WDTRESET_MASK (0x100U) -#define PMC_AOREG1_WDTRESET_SHIFT (8U) -/*! WDTRESET - The last chip reset was caused by the Watchdog Timer. - */ -#define PMC_AOREG1_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_WDTRESET_SHIFT)) & PMC_AOREG1_WDTRESET_MASK) - -#define PMC_AOREG1_SWRRESET_MASK (0x200U) -#define PMC_AOREG1_SWRRESET_SHIFT (9U) -/*! SWRRESET - The last chip reset was caused by a Software event. - */ -#define PMC_AOREG1_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SWRRESET_SHIFT)) & PMC_AOREG1_SWRRESET_MASK) - -#define PMC_AOREG1_DPDRESET_WAKEUPIO_MASK (0x400U) -#define PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT (10U) -/*! DPDRESET_WAKEUPIO - The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode. - */ -#define PMC_AOREG1_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT)) & PMC_AOREG1_DPDRESET_WAKEUPIO_MASK) - -#define PMC_AOREG1_DPDRESET_RTC_MASK (0x800U) -#define PMC_AOREG1_DPDRESET_RTC_SHIFT (11U) -/*! DPDRESET_RTC - The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode. - */ -#define PMC_AOREG1_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_RTC_SHIFT)) & PMC_AOREG1_DPDRESET_RTC_MASK) - -#define PMC_AOREG1_DPDRESET_OSTIMER_MASK (0x1000U) -#define PMC_AOREG1_DPDRESET_OSTIMER_SHIFT (12U) -/*! DPDRESET_OSTIMER - The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode. - */ -#define PMC_AOREG1_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_OSTIMER_SHIFT)) & PMC_AOREG1_DPDRESET_OSTIMER_MASK) - -#define PMC_AOREG1_BOOTERRORCOUNTER_MASK (0xF0000U) -#define PMC_AOREG1_BOOTERRORCOUNTER_SHIFT (16U) -/*! BOOTERRORCOUNTER - ROM Boot Fatal Error Counter. - */ -#define PMC_AOREG1_BOOTERRORCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BOOTERRORCOUNTER_SHIFT)) & PMC_AOREG1_BOOTERRORCOUNTER_MASK) -/*! @} */ - -/*! @name MISCCTRL - Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_MISCCTRL_LDODEEPSLEEPREF_MASK (0x1U) -#define PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT (0U) -/*! LDODEEPSLEEPREF - Select LDO Deep Sleep reference source. - * 0b0..LDO DEEP Sleep uses Flash buffer biasing as reference. - * 0b1..LDO DEEP Sleep uses Band Gap 0.8V as reference. - */ -#define PMC_MISCCTRL_LDODEEPSLEEPREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT)) & PMC_MISCCTRL_LDODEEPSLEEPREF_MASK) - -#define PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK (0x2U) -#define PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT (1U) -/*! LDOMEMHIGHZMODE - Control the activation of LDO MEM High Z mode. - * 0b0..LDO MEM High Z mode is disabled. - * 0b1..LDO MEM High Z mode is enabled. - */ -#define PMC_MISCCTRL_LDOMEMHIGHZMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT)) & PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK) - -#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK (0x4U) -#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT (2U) -#define PMC_MISCCTRL_LOWPWR_FLASH_BUF(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT)) & PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK) - -#define PMC_MISCCTRL_MISCCTRL_3_8_MASK (0xF8U) -#define PMC_MISCCTRL_MISCCTRL_3_8_SHIFT (3U) -/*! MISCCTRL_3_8 - Reserved. - */ -#define PMC_MISCCTRL_MISCCTRL_3_8(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_3_8_SHIFT)) & PMC_MISCCTRL_MISCCTRL_3_8_MASK) - -#define PMC_MISCCTRL_MODEWAKEUP0_MASK (0x100U) -#define PMC_MISCCTRL_MODEWAKEUP0_SHIFT (8U) -/*! MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode - */ -#define PMC_MISCCTRL_MODEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP0_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP0_MASK) - -#define PMC_MISCCTRL_MODEWAKEUP1_MASK (0x200U) -#define PMC_MISCCTRL_MODEWAKEUP1_SHIFT (9U) -/*! MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode - */ -#define PMC_MISCCTRL_MODEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP1_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP1_MASK) - -#define PMC_MISCCTRL_MODEWAKEUP2_MASK (0x400U) -#define PMC_MISCCTRL_MODEWAKEUP2_SHIFT (10U) -/*! MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode - */ -#define PMC_MISCCTRL_MODEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP2_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP2_MASK) - -#define PMC_MISCCTRL_MODEWAKEUP3_MASK (0x800U) -#define PMC_MISCCTRL_MODEWAKEUP3_SHIFT (11U) -/*! MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode - */ -#define PMC_MISCCTRL_MODEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP3_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP3_MASK) - -#define PMC_MISCCTRL_DISABLE_BLEED_MASK (0x1000U) -#define PMC_MISCCTRL_DISABLE_BLEED_SHIFT (12U) -/*! DISABLE_BLEED - Controls LDO MEM bleed current. This field is expected to be controlled by the - * Low Power Software only in DEEP SLEEP low power mode. - * 0b0..LDO_MEM bleed current is enabled. - * 0b1..LDO_MEM bleed current is disabled. Should be set before entering in Deep Sleep low power mode and cleared - * after wake up from Deep SLeep low power mode. - */ -#define PMC_MISCCTRL_DISABLE_BLEED(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_DISABLE_BLEED_SHIFT)) & PMC_MISCCTRL_DISABLE_BLEED_MASK) - -#define PMC_MISCCTRL_MISCCTRL_13_14_MASK (0x6000U) -#define PMC_MISCCTRL_MISCCTRL_13_14_SHIFT (13U) -/*! MISCCTRL_13_14 - Reserved. - */ -#define PMC_MISCCTRL_MISCCTRL_13_14(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_13_14_SHIFT)) & PMC_MISCCTRL_MISCCTRL_13_14_MASK) - -#define PMC_MISCCTRL_WAKUPIO_RST_MASK (0x8000U) -#define PMC_MISCCTRL_WAKUPIO_RST_SHIFT (15U) -/*! WAKUPIO_RST - WAKEUP IO event detector reset control. - * 0b1..Wakeup IO is reset. - * 0b0..Wakeup IO is not reset. - */ -#define PMC_MISCCTRL_WAKUPIO_RST(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_WAKUPIO_RST_SHIFT)) & PMC_MISCCTRL_WAKUPIO_RST_MASK) -/*! @} */ - -/*! @name RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_RTCOSC32K_SEL_MASK (0x1U) -#define PMC_RTCOSC32K_SEL_SHIFT (0U) -/*! SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . - * 0b0..FRO 32 KHz. - * 0b1..XTAL 32KHz. - */ -#define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK) - -#define PMC_RTCOSC32K_CLK1KHZDIV_MASK (0xEU) -#define PMC_RTCOSC32K_CLK1KHZDIV_SHIFT (1U) -/*! CLK1KHZDIV - Actual division ratio is : 28 + CLK1KHZDIV. - */ -#define PMC_RTCOSC32K_CLK1KHZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIV_MASK) - -#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK (0x8000U) -#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT (15U) -/*! CLK1KHZDIVUPDATEREQ - RTC 1KHz clock Divider status flag. - */ -#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK) - -#define PMC_RTCOSC32K_CLK1HZDIV_MASK (0x7FF0000U) -#define PMC_RTCOSC32K_CLK1HZDIV_SHIFT (16U) -/*! CLK1HZDIV - Actual division ratio is : 31744 + CLK1HZDIV. - */ -#define PMC_RTCOSC32K_CLK1HZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIV_MASK) - -#define PMC_RTCOSC32K_CLK1HZDIVHALT_MASK (0x40000000U) -#define PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT (30U) -/*! CLK1HZDIVHALT - Halts the divider counter. - */ -#define PMC_RTCOSC32K_CLK1HZDIVHALT(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVHALT_MASK) - -#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK (0x80000000U) -#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT (31U) -/*! CLK1HZDIVUPDATEREQ - RTC 1Hz Divider status flag. - */ -#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK) -/*! @} */ - -/*! @name OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_OSTIMER_SOFTRESET_MASK (0x1U) -#define PMC_OSTIMER_SOFTRESET_SHIFT (0U) -/*! SOFTRESET - Active high reset. - */ -#define PMC_OSTIMER_SOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_SOFTRESET_SHIFT)) & PMC_OSTIMER_SOFTRESET_MASK) - -#define PMC_OSTIMER_CLOCKENABLE_MASK (0x2U) -#define PMC_OSTIMER_CLOCKENABLE_SHIFT (1U) -/*! CLOCKENABLE - Enable OSTIMER 32 KHz clock. - */ -#define PMC_OSTIMER_CLOCKENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_CLOCKENABLE_SHIFT)) & PMC_OSTIMER_CLOCKENABLE_MASK) - -#define PMC_OSTIMER_DPDWAKEUPENABLE_MASK (0x4U) -#define PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT (2U) -/*! DPDWAKEUPENABLE - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode). - */ -#define PMC_OSTIMER_DPDWAKEUPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSTIMER_DPDWAKEUPENABLE_MASK) - -#define PMC_OSTIMER_OSC32KPD_MASK (0x8U) -#define PMC_OSTIMER_OSC32KPD_SHIFT (3U) -/*! OSC32KPD - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K. - */ -#define PMC_OSTIMER_OSC32KPD(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSC32KPD_SHIFT)) & PMC_OSTIMER_OSC32KPD_MASK) -/*! @} */ - -/*! @name PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_PDRUNCFG0_PDEN_BODVBAT_MASK (0x8U) -#define PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT (3U) -/*! PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD). - * 0b0..BOD VBAT is powered. - * 0b1..BOD VBAT is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVBAT_MASK) - -#define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U) -#define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U) -/*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. - * 0b0..FRO32KHz is powered. - * 0b1..FRO32KHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK) - -#define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U) -#define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U) -/*! PDEN_XTAL32K - Controls power to crystal 32 KHz. - * 0b0..Crystal 32KHz is powered. - * 0b1..Crystal 32KHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK) - -#define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK (0x100U) -#define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT (8U) -/*! PDEN_XTAL32M - Controls power to high speed crystal. - * 0b0..High speed crystal is powered. - * 0b1..High speed crystal is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK) - -#define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U) -#define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U) -/*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). - * 0b0..PLL0 is powered. - * 0b1..PLL0 is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK) - -#define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U) -#define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U) -/*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1). - * 0b0..PLL1 is powered. - * 0b1..PLL1 is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK) - -#define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK (0x800U) -#define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT (11U) -/*! PDEN_USBFSPHY - Controls power to USB Full Speed phy. - * 0b0..USB Full Speed phy is powered. - * 0b1..USB Full Speed phy is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK) - -#define PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK (0x1000U) -#define PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT (12U) -/*! PDEN_USBHSPHY - Controls power to USB High Speed Phy. - * 0b0..USB HS phy is powered. - * 0b1..USB HS phy is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK) - -#define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U) -#define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U) -/*! PDEN_COMP - Controls power to Analog Comparator. - * 0b0..Analog Comparator is powered. - * 0b1..Analog Comparator is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK) - -#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK (0x40000U) -#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT (18U) -/*! PDEN_LDOUSBHS - Controls power to USB high speed LDO. - * 0b0..USB high speed LDO is powered. - * 0b1..USB high speed LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK) - -#define PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK (0x80000U) -#define PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT (19U) -/*! PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS) - * 0b0..auxiliary biasing is powered. - * 0b1..auxiliary biasing is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK) - -#define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK (0x100000U) -#define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT (20U) -/*! PDEN_LDOXO32M - Controls power to high speed crystal LDO. - * 0b0..High speed crystal LDO is powered. - * 0b1..High speed crystal LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK) - -#define PMC_PDRUNCFG0_PDEN_RNG_MASK (0x400000U) -#define PMC_PDRUNCFG0_PDEN_RNG_SHIFT (22U) -/*! PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources. - * 0b0..TRNG clocks are powered. - * 0b1..TRNG clocks are powered down. - */ -#define PMC_PDRUNCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_RNG_SHIFT)) & PMC_PDRUNCFG0_PDEN_RNG_MASK) - -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U) -/*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. - * 0b0..PLL0 Sread spectrum module is powered. - * 0b1..PLL0 Sread spectrum module is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) -/*! @} */ - -/*! @name PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU) -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U) -/*! PDRUNCFGSET0 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. - */ -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK) -/*! @} */ - -/*! @name PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU) -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U) -/*! PDRUNCFGCLR0 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. - */ -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK) -/*! @} */ - -/*! @name SRAMCTRL - All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ -/*! @{ */ - -#define PMC_SRAMCTRL_SMB_MASK (0x3U) -#define PMC_SRAMCTRL_SMB_SHIFT (0U) -/*! SMB - Source Biasing voltage. - * 0b00..Low leakage. - * 0b01..Medium leakage. - * 0b10..Highest leakage. - * 0b11..Disable. - */ -#define PMC_SRAMCTRL_SMB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_SMB_SHIFT)) & PMC_SRAMCTRL_SMB_MASK) - -#define PMC_SRAMCTRL_RM_MASK (0x1CU) -#define PMC_SRAMCTRL_RM_SHIFT (2U) -/*! RM - Read Margin control settings. - */ -#define PMC_SRAMCTRL_RM(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_RM_SHIFT)) & PMC_SRAMCTRL_RM_MASK) - -#define PMC_SRAMCTRL_WM_MASK (0xE0U) -#define PMC_SRAMCTRL_WM_SHIFT (5U) -/*! WM - Write Margin control settings. - */ -#define PMC_SRAMCTRL_WM(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WM_SHIFT)) & PMC_SRAMCTRL_WM_MASK) - -#define PMC_SRAMCTRL_WRME_MASK (0x100U) -#define PMC_SRAMCTRL_WRME_SHIFT (8U) -/*! WRME - Write read margin enable. - */ -#define PMC_SRAMCTRL_WRME(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WRME_SHIFT)) & PMC_SRAMCTRL_WRME_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PMC_Register_Masks */ - - -/* PMC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PMC base address */ - #define PMC_BASE (0x50020000u) - /** Peripheral PMC base address */ - #define PMC_BASE_NS (0x40020000u) - /** Peripheral PMC base pointer */ - #define PMC ((PMC_Type *)PMC_BASE) - /** Peripheral PMC base pointer */ - #define PMC_NS ((PMC_Type *)PMC_BASE_NS) - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS { PMC_BASE } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS { PMC } - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS_NS { PMC_BASE_NS } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS_NS { PMC_NS } -#else - /** Peripheral PMC base address */ - #define PMC_BASE (0x40020000u) - /** Peripheral PMC base pointer */ - #define PMC ((PMC_Type *)PMC_BASE) - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS { PMC_BASE } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS { PMC } -#endif - -/*! - * @} - */ /* end of group PMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PRINCE Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PRINCE_Peripheral_Access_Layer PRINCE Peripheral Access Layer - * @{ - */ - -/** PRINCE - Register Layout Typedef */ -typedef struct { - __IO uint32_t ENC_ENABLE; /**< Encryption Enable register, offset: 0x0 */ - __O uint32_t MASK_LSB; /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */ - __O uint32_t MASK_MSB; /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */ - __IO uint32_t LOCK; /**< Lock register, offset: 0xC */ - __O uint32_t IV_LSB0; /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */ - __O uint32_t IV_MSB0; /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */ - __IO uint32_t BASE_ADDR0; /**< Base Address for region 0 register, offset: 0x18 */ - __IO uint32_t SR_ENABLE0; /**< Sub-Region Enable register for region 0, offset: 0x1C */ - __O uint32_t IV_LSB1; /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */ - __O uint32_t IV_MSB1; /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */ - __IO uint32_t BASE_ADDR1; /**< Base Address for region 1 register, offset: 0x28 */ - __IO uint32_t SR_ENABLE1; /**< Sub-Region Enable register for region 1, offset: 0x2C */ - __O uint32_t IV_LSB2; /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */ - __O uint32_t IV_MSB2; /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */ - __IO uint32_t BASE_ADDR2; /**< Base Address for region 2 register, offset: 0x38 */ - __IO uint32_t SR_ENABLE2; /**< Sub-Region Enable register for region 2, offset: 0x3C */ -} PRINCE_Type; - -/* ---------------------------------------------------------------------------- - -- PRINCE Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PRINCE_Register_Masks PRINCE Register Masks - * @{ - */ - -/*! @name ENC_ENABLE - Encryption Enable register */ -/*! @{ */ - -#define PRINCE_ENC_ENABLE_EN_MASK (0x1U) -#define PRINCE_ENC_ENABLE_EN_SHIFT (0U) -/*! EN - Encryption Enable. - * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled. - * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled. - */ -#define PRINCE_ENC_ENABLE_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK) -/*! @} */ - -/*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */ -/*! @{ */ - -#define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU) -#define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U) -/*! MASKVAL - Value of the 32 Least Significant Bits of the 64-bit data mask. - */ -#define PRINCE_MASK_LSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK) -/*! @} */ - -/*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */ -/*! @{ */ - -#define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU) -#define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U) -/*! MASKVAL - Value of the 32 Most Significant Bits of the 64-bit data mask. - */ -#define PRINCE_MASK_MSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK) -/*! @} */ - -/*! @name LOCK - Lock register */ -/*! @{ */ - -#define PRINCE_LOCK_LOCKREG0_MASK (0x1U) -#define PRINCE_LOCK_LOCKREG0_SHIFT (0U) -/*! LOCKREG0 - Lock Region 0 registers. - * 0b0..Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. - * 0b1..Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. - */ -#define PRINCE_LOCK_LOCKREG0(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK) - -#define PRINCE_LOCK_LOCKREG1_MASK (0x2U) -#define PRINCE_LOCK_LOCKREG1_SHIFT (1U) -/*! LOCKREG1 - Lock Region 1 registers. - * 0b0..Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. - * 0b1..Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. - */ -#define PRINCE_LOCK_LOCKREG1(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK) - -#define PRINCE_LOCK_LOCKREG2_MASK (0x4U) -#define PRINCE_LOCK_LOCKREG2_SHIFT (2U) -/*! LOCKREG2 - Lock Region 2 registers. - * 0b0..Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. - * 0b1..Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. - */ -#define PRINCE_LOCK_LOCKREG2(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK) - -#define PRINCE_LOCK_LOCKMASK_MASK (0x100U) -#define PRINCE_LOCK_LOCKMASK_SHIFT (8U) -/*! LOCKMASK - Lock the Mask registers. - * 0b0..Disabled. MASK_LSB, and MASK_MSB are writable.. - * 0b1..Enabled. MASK_LSB, and MASK_MSB are not writable.. - */ -#define PRINCE_LOCK_LOCKMASK(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK) -/*! @} */ - -/*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB0_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_LSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB0_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_MSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR0 - Base Address for region 0 register */ -/*! @{ */ - -#define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U) -/*! ADDR_FIXED - Fixed portion of the base address of region 0. - */ -#define PRINCE_BASE_ADDR0_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK) - -#define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U) -/*! ADDR_PRG - Programmable portion of the base address of region 0. - */ -#define PRINCE_BASE_ADDR0_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */ -/*! @{ */ - -#define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE0_EN_SHIFT (0U) -/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0. - */ -#define PRINCE_SR_ENABLE0_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK) -/*! @} */ - -/*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB1_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_LSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB1_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_MSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR1 - Base Address for region 1 register */ -/*! @{ */ - -#define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U) -/*! ADDR_FIXED - Fixed portion of the base address of region 1. - */ -#define PRINCE_BASE_ADDR1_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK) - -#define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U) -/*! ADDR_PRG - Programmable portion of the base address of region 1. - */ -#define PRINCE_BASE_ADDR1_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */ -/*! @{ */ - -#define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE1_EN_SHIFT (0U) -/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1. - */ -#define PRINCE_SR_ENABLE1_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK) -/*! @} */ - -/*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB2_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_LSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB2_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_MSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR2 - Base Address for region 2 register */ -/*! @{ */ - -#define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U) -/*! ADDR_FIXED - Fixed portion of the base address of region 2. - */ -#define PRINCE_BASE_ADDR2_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK) - -#define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U) -/*! ADDR_PRG - Programmable portion of the base address of region 2. - */ -#define PRINCE_BASE_ADDR2_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */ -/*! @{ */ - -#define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE2_EN_SHIFT (0U) -/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2. - */ -#define PRINCE_SR_ENABLE2_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PRINCE_Register_Masks */ - - -/* PRINCE - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PRINCE base address */ - #define PRINCE_BASE (0x50035000u) - /** Peripheral PRINCE base address */ - #define PRINCE_BASE_NS (0x40035000u) - /** Peripheral PRINCE base pointer */ - #define PRINCE ((PRINCE_Type *)PRINCE_BASE) - /** Peripheral PRINCE base pointer */ - #define PRINCE_NS ((PRINCE_Type *)PRINCE_BASE_NS) - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS { PRINCE_BASE } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS { PRINCE } - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS_NS { PRINCE_BASE_NS } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS_NS { PRINCE_NS } -#else - /** Peripheral PRINCE base address */ - #define PRINCE_BASE (0x40035000u) - /** Peripheral PRINCE base pointer */ - #define PRINCE ((PRINCE_Type *)PRINCE_BASE) - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS { PRINCE_BASE } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS { PRINCE } -#endif - -/*! - * @} - */ /* end of group PRINCE_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PUF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer - * @{ - */ - -/** PUF - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< PUF Control register, offset: 0x0 */ - __IO uint32_t KEYINDEX; /**< PUF Key Index register, offset: 0x4 */ - __IO uint32_t KEYSIZE; /**< PUF Key Size register, offset: 0x8 */ - uint8_t RESERVED_0[20]; - __I uint32_t STAT; /**< PUF Status register, offset: 0x20 */ - uint8_t RESERVED_1[4]; - __I uint32_t ALLOW; /**< PUF Allow register, offset: 0x28 */ - uint8_t RESERVED_2[20]; - __O uint32_t KEYINPUT; /**< PUF Key Input register, offset: 0x40 */ - __O uint32_t CODEINPUT; /**< PUF Code Input register, offset: 0x44 */ - __I uint32_t CODEOUTPUT; /**< PUF Code Output register, offset: 0x48 */ - uint8_t RESERVED_3[20]; - __I uint32_t KEYOUTINDEX; /**< PUF Key Output Index register, offset: 0x60 */ - __I uint32_t KEYOUTPUT; /**< PUF Key Output register, offset: 0x64 */ - uint8_t RESERVED_4[116]; - __IO uint32_t IFSTAT; /**< PUF Interface Status and clear register, offset: 0xDC */ - uint8_t RESERVED_5[28]; - __I uint32_t VERSION; /**< PUF version register., offset: 0xFC */ - __IO uint32_t INTEN; /**< PUF Interrupt Enable, offset: 0x100 */ - __IO uint32_t INTSTAT; /**< PUF interrupt status, offset: 0x104 */ - __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */ - __IO uint32_t CFG; /**< PUF config register for block bits, offset: 0x10C */ - uint8_t RESERVED_6[240]; - __IO uint32_t KEYLOCK; /**< Only reset in case of full IC reset, offset: 0x200 */ - __IO uint32_t KEYENABLE; /**< , offset: 0x204 */ - __O uint32_t KEYRESET; /**< Reinitialize Keys shift registers counters, offset: 0x208 */ - __IO uint32_t IDXBLK_L; /**< , offset: 0x20C */ - __IO uint32_t IDXBLK_H_DP; /**< , offset: 0x210 */ - __O uint32_t KEYMASK[4]; /**< Only reset in case of full IC reset, array offset: 0x214, array step: 0x4 */ - uint8_t RESERVED_7[48]; - __IO uint32_t IDXBLK_H; /**< , offset: 0x254 */ - __IO uint32_t IDXBLK_L_DP; /**< , offset: 0x258 */ - __I uint32_t SHIFT_STATUS; /**< , offset: 0x25C */ -} PUF_Type; - -/* ---------------------------------------------------------------------------- - -- PUF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_Register_Masks PUF Register Masks - * @{ - */ - -/*! @name CTRL - PUF Control register */ -/*! @{ */ - -#define PUF_CTRL_ZEROIZE_MASK (0x1U) -#define PUF_CTRL_ZEROIZE_SHIFT (0U) -/*! zeroize - Begin Zeroize operation for PUF and go to Error state - */ -#define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK) - -#define PUF_CTRL_ENROLL_MASK (0x2U) -#define PUF_CTRL_ENROLL_SHIFT (1U) -/*! enroll - Begin Enroll operation - */ -#define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK) - -#define PUF_CTRL_START_MASK (0x4U) -#define PUF_CTRL_START_SHIFT (2U) -/*! start - Begin Start operation - */ -#define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK) - -#define PUF_CTRL_GENERATEKEY_MASK (0x8U) -#define PUF_CTRL_GENERATEKEY_SHIFT (3U) -/*! GENERATEKEY - Begin Set Intrinsic Key operation - */ -#define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK) - -#define PUF_CTRL_SETKEY_MASK (0x10U) -#define PUF_CTRL_SETKEY_SHIFT (4U) -/*! SETKEY - Begin Set User Key operation - */ -#define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK) - -#define PUF_CTRL_GETKEY_MASK (0x40U) -#define PUF_CTRL_GETKEY_SHIFT (6U) -/*! GETKEY - Begin Get Key operation - */ -#define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK) -/*! @} */ - -/*! @name KEYINDEX - PUF Key Index register */ -/*! @{ */ - -#define PUF_KEYINDEX_KEYIDX_MASK (0xFU) -#define PUF_KEYINDEX_KEYIDX_SHIFT (0U) -/*! KEYIDX - Key index for Set Key operations - */ -#define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK) -/*! @} */ - -/*! @name KEYSIZE - PUF Key Size register */ -/*! @{ */ - -#define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU) -#define PUF_KEYSIZE_KEYSIZE_SHIFT (0U) -/*! KEYSIZE - Key size for Set Key operations - */ -#define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK) -/*! @} */ - -/*! @name STAT - PUF Status register */ -/*! @{ */ - -#define PUF_STAT_BUSY_MASK (0x1U) -#define PUF_STAT_BUSY_SHIFT (0U) -/*! busy - Indicates that operation is in progress - */ -#define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK) - -#define PUF_STAT_SUCCESS_MASK (0x2U) -#define PUF_STAT_SUCCESS_SHIFT (1U) -/*! SUCCESS - Last operation was successful - */ -#define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK) - -#define PUF_STAT_ERROR_MASK (0x4U) -#define PUF_STAT_ERROR_SHIFT (2U) -/*! error - PUF is in the Error state and no operations can be performed - */ -#define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK) - -#define PUF_STAT_KEYINREQ_MASK (0x10U) -#define PUF_STAT_KEYINREQ_SHIFT (4U) -/*! KEYINREQ - Request for next part of key - */ -#define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK) - -#define PUF_STAT_KEYOUTAVAIL_MASK (0x20U) -#define PUF_STAT_KEYOUTAVAIL_SHIFT (5U) -/*! KEYOUTAVAIL - Next part of key is available - */ -#define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK) - -#define PUF_STAT_CODEINREQ_MASK (0x40U) -#define PUF_STAT_CODEINREQ_SHIFT (6U) -/*! CODEINREQ - Request for next part of AC/KC - */ -#define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK) - -#define PUF_STAT_CODEOUTAVAIL_MASK (0x80U) -#define PUF_STAT_CODEOUTAVAIL_SHIFT (7U) -/*! CODEOUTAVAIL - Next part of AC/KC is available - */ -#define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK) -/*! @} */ - -/*! @name ALLOW - PUF Allow register */ -/*! @{ */ - -#define PUF_ALLOW_ALLOWENROLL_MASK (0x1U) -#define PUF_ALLOW_ALLOWENROLL_SHIFT (0U) -/*! ALLOWENROLL - Enroll operation is allowed - */ -#define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK) - -#define PUF_ALLOW_ALLOWSTART_MASK (0x2U) -#define PUF_ALLOW_ALLOWSTART_SHIFT (1U) -/*! ALLOWSTART - Start operation is allowed - */ -#define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK) - -#define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U) -#define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U) -/*! ALLOWSETKEY - Set Key operations are allowed - */ -#define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK) - -#define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U) -#define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U) -/*! ALLOWGETKEY - Get Key operation is allowed - */ -#define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK) -/*! @} */ - -/*! @name KEYINPUT - PUF Key Input register */ -/*! @{ */ - -#define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU) -#define PUF_KEYINPUT_KEYIN_SHIFT (0U) -/*! KEYIN - Key input data - */ -#define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK) -/*! @} */ - -/*! @name CODEINPUT - PUF Code Input register */ -/*! @{ */ - -#define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU) -#define PUF_CODEINPUT_CODEIN_SHIFT (0U) -/*! CODEIN - AC/KC input data - */ -#define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK) -/*! @} */ - -/*! @name CODEOUTPUT - PUF Code Output register */ -/*! @{ */ - -#define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU) -#define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U) -/*! CODEOUT - AC/KC output data - */ -#define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK) -/*! @} */ - -/*! @name KEYOUTINDEX - PUF Key Output Index register */ -/*! @{ */ - -#define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFU) -#define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U) -/*! KEYOUTIDX - Key index for the key that is currently output via the Key Output register - */ -#define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK) -/*! @} */ - -/*! @name KEYOUTPUT - PUF Key Output register */ -/*! @{ */ - -#define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU) -#define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U) -/*! KEYOUT - Key output data - */ -#define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK) -/*! @} */ - -/*! @name IFSTAT - PUF Interface Status and clear register */ -/*! @{ */ - -#define PUF_IFSTAT_ERROR_MASK (0x1U) -#define PUF_IFSTAT_ERROR_SHIFT (0U) -/*! ERROR - Indicates that an APB error has occurred,Writing logic1 clears the if_error bit - */ -#define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK) -/*! @} */ - -/*! @name VERSION - PUF version register. */ -/*! @{ */ - -#define PUF_VERSION_VERSION_MASK (0xFFFFFFFFU) -#define PUF_VERSION_VERSION_SHIFT (0U) -/*! VERSION - Version of the PUF module. - */ -#define PUF_VERSION_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_VERSION_SHIFT)) & PUF_VERSION_VERSION_MASK) -/*! @} */ - -/*! @name INTEN - PUF Interrupt Enable */ -/*! @{ */ - -#define PUF_INTEN_READYEN_MASK (0x1U) -#define PUF_INTEN_READYEN_SHIFT (0U) -/*! READYEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK) - -#define PUF_INTEN_SUCCESEN_MASK (0x2U) -#define PUF_INTEN_SUCCESEN_SHIFT (1U) -/*! SUCCESEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_SUCCESEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK) - -#define PUF_INTEN_ERROREN_MASK (0x4U) -#define PUF_INTEN_ERROREN_SHIFT (2U) -/*! ERROREN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK) - -#define PUF_INTEN_KEYINREQEN_MASK (0x10U) -#define PUF_INTEN_KEYINREQEN_SHIFT (4U) -/*! KEYINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK) - -#define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U) -#define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U) -/*! KEYOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK) - -#define PUF_INTEN_CODEINREQEN_MASK (0x40U) -#define PUF_INTEN_CODEINREQEN_SHIFT (6U) -/*! CODEINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK) - -#define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U) -#define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U) -/*! CODEOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK) -/*! @} */ - -/*! @name INTSTAT - PUF interrupt status */ -/*! @{ */ - -#define PUF_INTSTAT_READY_MASK (0x1U) -#define PUF_INTSTAT_READY_SHIFT (0U) -/*! READY - Triggers on falling edge of busy, write 1 to clear - */ -#define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK) - -#define PUF_INTSTAT_SUCCESS_MASK (0x2U) -#define PUF_INTSTAT_SUCCESS_SHIFT (1U) -/*! SUCCESS - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK) - -#define PUF_INTSTAT_ERROR_MASK (0x4U) -#define PUF_INTSTAT_ERROR_SHIFT (2U) -/*! ERROR - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK) - -#define PUF_INTSTAT_KEYINREQ_MASK (0x10U) -#define PUF_INTSTAT_KEYINREQ_SHIFT (4U) -/*! KEYINREQ - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK) - -#define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U) -#define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U) -/*! KEYOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK) - -#define PUF_INTSTAT_CODEINREQ_MASK (0x40U) -#define PUF_INTSTAT_CODEINREQ_SHIFT (6U) -/*! CODEINREQ - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK) - -#define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U) -#define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U) -/*! CODEOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK) -/*! @} */ - -/*! @name PWRCTRL - PUF RAM Power Control */ -/*! @{ */ - -#define PUF_PWRCTRL_RAMON_MASK (0x1U) -#define PUF_PWRCTRL_RAMON_SHIFT (0U) -/*! RAMON - Power on the PUF RAM. - */ -#define PUF_PWRCTRL_RAMON(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMON_SHIFT)) & PUF_PWRCTRL_RAMON_MASK) - -#define PUF_PWRCTRL_RAMSTAT_MASK (0x2U) -#define PUF_PWRCTRL_RAMSTAT_SHIFT (1U) -/*! RAMSTAT - PUF RAM status. - */ -#define PUF_PWRCTRL_RAMSTAT(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMSTAT_SHIFT)) & PUF_PWRCTRL_RAMSTAT_MASK) -/*! @} */ - -/*! @name CFG - PUF config register for block bits */ -/*! @{ */ - -#define PUF_CFG_BLOCKENROLL_SETKEY_MASK (0x1U) -#define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT (0U) -/*! BLOCKENROLL_SETKEY - Block enroll operation. Write 1 to set, cleared on reset. - */ -#define PUF_CFG_BLOCKENROLL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK) - -#define PUF_CFG_BLOCKKEYOUTPUT_MASK (0x2U) -#define PUF_CFG_BLOCKKEYOUTPUT_SHIFT (1U) -/*! BLOCKKEYOUTPUT - Block set key operation. Write 1 to set, cleared on reset. - */ -#define PUF_CFG_BLOCKKEYOUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK) -/*! @} */ - -/*! @name KEYLOCK - Only reset in case of full IC reset */ -/*! @{ */ - -#define PUF_KEYLOCK_KEY0_MASK (0x3U) -#define PUF_KEYLOCK_KEY0_SHIFT (0U) -/*! KEY0 - "10:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is allowed. 00, 01, - * 11:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is NOT allowed. Important Note : Once - * this field is written with a value different from '10', its value can no longer be modified - * until un Power On Reset occurs." - */ -#define PUF_KEYLOCK_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK) - -#define PUF_KEYLOCK_KEY1_MASK (0xCU) -#define PUF_KEYLOCK_KEY1_SHIFT (2U) -/*! KEY1 - "10:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is allowed. 00, 01, - * 11:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is NOT allowed. Important Note : Once - * this field is written with a value different from '10', its value can no longer be modified - * until un Power On Reset occurs." - */ -#define PUF_KEYLOCK_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK) - -#define PUF_KEYLOCK_KEY2_MASK (0x30U) -#define PUF_KEYLOCK_KEY2_SHIFT (4U) -/*! KEY2 - "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, - * 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once - * this field is written with a value different from '10', its value can no longer be modified - * until un Power On Reset occurs." - */ -#define PUF_KEYLOCK_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK) - -#define PUF_KEYLOCK_KEY3_MASK (0xC0U) -#define PUF_KEYLOCK_KEY3_SHIFT (6U) -/*! KEY3 - "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, - * 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once - * this field is written with a value different from '10', its value can no longer be modified - * until un Power On Reset occurs." - */ -#define PUF_KEYLOCK_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK) -/*! @} */ - -/*! @name KEYENABLE - */ -/*! @{ */ - -#define PUF_KEYENABLE_KEY0_MASK (0x3U) -#define PUF_KEYENABLE_KEY0_SHIFT (0U) -/*! KEY0 - "10: Data coming out from PUF Index 0 interface are shifted in KEY0 register. 00, 01, 11 - * : Data coming out from PUF Index 0 interface are NOT shifted in KEY0 register." - */ -#define PUF_KEYENABLE_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK) - -#define PUF_KEYENABLE_KEY1_MASK (0xCU) -#define PUF_KEYENABLE_KEY1_SHIFT (2U) -/*! KEY1 - "10: Data coming out from PUF Index 0 interface are shifted in KEY1 register. 00, 01, 11 - * : Data coming out from PUF Index 0 interface are NOT shifted in KEY1 register." - */ -#define PUF_KEYENABLE_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK) - -#define PUF_KEYENABLE_KEY2_MASK (0x30U) -#define PUF_KEYENABLE_KEY2_SHIFT (4U) -/*! KEY2 - "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 - * : Data coming out from PUF Index 0 interface are NOT shifted in KEY2 register." - */ -#define PUF_KEYENABLE_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK) - -#define PUF_KEYENABLE_KEY3_MASK (0xC0U) -#define PUF_KEYENABLE_KEY3_SHIFT (6U) -/*! KEY3 - "10: Data coming out from PUF Index 0 interface are shifted in KEY3 register. 00, 01, 11 - * : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." - */ -#define PUF_KEYENABLE_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK) -/*! @} */ - -/*! @name KEYRESET - Reinitialize Keys shift registers counters */ -/*! @{ */ - -#define PUF_KEYRESET_KEY0_MASK (0x3U) -#define PUF_KEYRESET_KEY0_SHIFT (0U) -/*! KEY0 - 10: Reset KEY0 shift register. Self clearing. Must be done before loading any new key. - */ -#define PUF_KEYRESET_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK) - -#define PUF_KEYRESET_KEY1_MASK (0xCU) -#define PUF_KEYRESET_KEY1_SHIFT (2U) -/*! KEY1 - 10: Reset KEY1 shift register. Self clearing. Must be done before loading any new key. - */ -#define PUF_KEYRESET_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK) - -#define PUF_KEYRESET_KEY2_MASK (0x30U) -#define PUF_KEYRESET_KEY2_SHIFT (4U) -/*! KEY2 - 10: Reset KEY2 shift register. Self clearing. Must be done before loading any new key. - */ -#define PUF_KEYRESET_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK) - -#define PUF_KEYRESET_KEY3_MASK (0xC0U) -#define PUF_KEYRESET_KEY3_SHIFT (6U) -/*! KEY3 - 10: Reset KEY3 shift register. Self clearing. Must be done before loading any new key. - */ -#define PUF_KEYRESET_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK) -/*! @} */ - -/*! @name IDXBLK_L - */ -/*! @{ */ - -#define PUF_IDXBLK_L_IDX1_MASK (0xCU) -#define PUF_IDXBLK_L_IDX1_SHIFT (2U) -/*! IDX1 - Use to block PUF index 1 - */ -#define PUF_IDXBLK_L_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX1_SHIFT)) & PUF_IDXBLK_L_IDX1_MASK) - -#define PUF_IDXBLK_L_IDX2_MASK (0x30U) -#define PUF_IDXBLK_L_IDX2_SHIFT (4U) -/*! IDX2 - Use to block PUF index 2 - */ -#define PUF_IDXBLK_L_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX2_SHIFT)) & PUF_IDXBLK_L_IDX2_MASK) - -#define PUF_IDXBLK_L_IDX3_MASK (0xC0U) -#define PUF_IDXBLK_L_IDX3_SHIFT (6U) -/*! IDX3 - Use to block PUF index 3 - */ -#define PUF_IDXBLK_L_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX3_SHIFT)) & PUF_IDXBLK_L_IDX3_MASK) - -#define PUF_IDXBLK_L_IDX4_MASK (0x300U) -#define PUF_IDXBLK_L_IDX4_SHIFT (8U) -/*! IDX4 - Use to block PUF index 4 - */ -#define PUF_IDXBLK_L_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX4_SHIFT)) & PUF_IDXBLK_L_IDX4_MASK) - -#define PUF_IDXBLK_L_IDX5_MASK (0xC00U) -#define PUF_IDXBLK_L_IDX5_SHIFT (10U) -/*! IDX5 - Use to block PUF index 5 - */ -#define PUF_IDXBLK_L_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX5_SHIFT)) & PUF_IDXBLK_L_IDX5_MASK) - -#define PUF_IDXBLK_L_IDX6_MASK (0x3000U) -#define PUF_IDXBLK_L_IDX6_SHIFT (12U) -/*! IDX6 - Use to block PUF index 6 - */ -#define PUF_IDXBLK_L_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX6_SHIFT)) & PUF_IDXBLK_L_IDX6_MASK) - -#define PUF_IDXBLK_L_IDX7_MASK (0xC000U) -#define PUF_IDXBLK_L_IDX7_SHIFT (14U) -/*! IDX7 - Use to block PUF index 7 - */ -#define PUF_IDXBLK_L_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX7_SHIFT)) & PUF_IDXBLK_L_IDX7_MASK) - -#define PUF_IDXBLK_L_LOCK_IDX_MASK (0xC0000000U) -#define PUF_IDXBLK_L_LOCK_IDX_SHIFT (30U) -/*! LOCK_IDX - Lock 0 to 7 PUF key indexes - */ -#define PUF_IDXBLK_L_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_LOCK_IDX_SHIFT)) & PUF_IDXBLK_L_LOCK_IDX_MASK) -/*! @} */ - -/*! @name IDXBLK_H_DP - */ -/*! @{ */ - -#define PUF_IDXBLK_H_DP_IDX8_MASK (0x3U) -#define PUF_IDXBLK_H_DP_IDX8_SHIFT (0U) -/*! IDX8 - Use to block PUF index 8 - */ -#define PUF_IDXBLK_H_DP_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX8_SHIFT)) & PUF_IDXBLK_H_DP_IDX8_MASK) - -#define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) -#define PUF_IDXBLK_H_DP_IDX9_SHIFT (2U) -/*! IDX9 - Use to block PUF index 9 - */ -#define PUF_IDXBLK_H_DP_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK) - -#define PUF_IDXBLK_H_DP_IDX10_MASK (0x30U) -#define PUF_IDXBLK_H_DP_IDX10_SHIFT (4U) -/*! IDX10 - Use to block PUF index 10 - */ -#define PUF_IDXBLK_H_DP_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX10_SHIFT)) & PUF_IDXBLK_H_DP_IDX10_MASK) - -#define PUF_IDXBLK_H_DP_IDX11_MASK (0xC0U) -#define PUF_IDXBLK_H_DP_IDX11_SHIFT (6U) -/*! IDX11 - Use to block PUF index 11 - */ -#define PUF_IDXBLK_H_DP_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX11_SHIFT)) & PUF_IDXBLK_H_DP_IDX11_MASK) - -#define PUF_IDXBLK_H_DP_IDX12_MASK (0x300U) -#define PUF_IDXBLK_H_DP_IDX12_SHIFT (8U) -/*! IDX12 - Use to block PUF index 12 - */ -#define PUF_IDXBLK_H_DP_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX12_SHIFT)) & PUF_IDXBLK_H_DP_IDX12_MASK) - -#define PUF_IDXBLK_H_DP_IDX13_MASK (0xC00U) -#define PUF_IDXBLK_H_DP_IDX13_SHIFT (10U) -/*! IDX13 - Use to block PUF index 13 - */ -#define PUF_IDXBLK_H_DP_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX13_SHIFT)) & PUF_IDXBLK_H_DP_IDX13_MASK) - -#define PUF_IDXBLK_H_DP_IDX14_MASK (0x3000U) -#define PUF_IDXBLK_H_DP_IDX14_SHIFT (12U) -/*! IDX14 - Use to block PUF index 14 - */ -#define PUF_IDXBLK_H_DP_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX14_SHIFT)) & PUF_IDXBLK_H_DP_IDX14_MASK) - -#define PUF_IDXBLK_H_DP_IDX15_MASK (0xC000U) -#define PUF_IDXBLK_H_DP_IDX15_SHIFT (14U) -/*! IDX15 - Use to block PUF index 15 - */ -#define PUF_IDXBLK_H_DP_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX15_SHIFT)) & PUF_IDXBLK_H_DP_IDX15_MASK) -/*! @} */ - -/*! @name KEYMASK - Only reset in case of full IC reset */ -/*! @{ */ - -#define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU) -#define PUF_KEYMASK_KEYMASK_SHIFT (0U) -#define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK) -/*! @} */ - -/* The count of PUF_KEYMASK */ -#define PUF_KEYMASK_COUNT (4U) - -/*! @name IDXBLK_H - */ -/*! @{ */ - -#define PUF_IDXBLK_H_IDX8_MASK (0x3U) -#define PUF_IDXBLK_H_IDX8_SHIFT (0U) -/*! IDX8 - Use to block PUF index 8 - */ -#define PUF_IDXBLK_H_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX8_SHIFT)) & PUF_IDXBLK_H_IDX8_MASK) - -#define PUF_IDXBLK_H_IDX9_MASK (0xCU) -#define PUF_IDXBLK_H_IDX9_SHIFT (2U) -/*! IDX9 - Use to block PUF index 9 - */ -#define PUF_IDXBLK_H_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX9_SHIFT)) & PUF_IDXBLK_H_IDX9_MASK) - -#define PUF_IDXBLK_H_IDX10_MASK (0x30U) -#define PUF_IDXBLK_H_IDX10_SHIFT (4U) -/*! IDX10 - Use to block PUF index 10 - */ -#define PUF_IDXBLK_H_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX10_SHIFT)) & PUF_IDXBLK_H_IDX10_MASK) - -#define PUF_IDXBLK_H_IDX11_MASK (0xC0U) -#define PUF_IDXBLK_H_IDX11_SHIFT (6U) -/*! IDX11 - Use to block PUF index 11 - */ -#define PUF_IDXBLK_H_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX11_SHIFT)) & PUF_IDXBLK_H_IDX11_MASK) - -#define PUF_IDXBLK_H_IDX12_MASK (0x300U) -#define PUF_IDXBLK_H_IDX12_SHIFT (8U) -/*! IDX12 - Use to block PUF index 12 - */ -#define PUF_IDXBLK_H_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX12_SHIFT)) & PUF_IDXBLK_H_IDX12_MASK) - -#define PUF_IDXBLK_H_IDX13_MASK (0xC00U) -#define PUF_IDXBLK_H_IDX13_SHIFT (10U) -/*! IDX13 - Use to block PUF index 13 - */ -#define PUF_IDXBLK_H_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX13_SHIFT)) & PUF_IDXBLK_H_IDX13_MASK) - -#define PUF_IDXBLK_H_IDX14_MASK (0x3000U) -#define PUF_IDXBLK_H_IDX14_SHIFT (12U) -/*! IDX14 - Use to block PUF index 14 - */ -#define PUF_IDXBLK_H_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX14_SHIFT)) & PUF_IDXBLK_H_IDX14_MASK) - -#define PUF_IDXBLK_H_IDX15_MASK (0xC000U) -#define PUF_IDXBLK_H_IDX15_SHIFT (14U) -/*! IDX15 - Use to block PUF index 15 - */ -#define PUF_IDXBLK_H_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX15_SHIFT)) & PUF_IDXBLK_H_IDX15_MASK) - -#define PUF_IDXBLK_H_LOCK_IDX_MASK (0xC0000000U) -#define PUF_IDXBLK_H_LOCK_IDX_SHIFT (30U) -/*! LOCK_IDX - Lock 8 to 15 PUF key indexes - */ -#define PUF_IDXBLK_H_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_LOCK_IDX_SHIFT)) & PUF_IDXBLK_H_LOCK_IDX_MASK) -/*! @} */ - -/*! @name IDXBLK_L_DP - */ -/*! @{ */ - -#define PUF_IDXBLK_L_DP_IDX1_MASK (0xCU) -#define PUF_IDXBLK_L_DP_IDX1_SHIFT (2U) -/*! IDX1 - Use to block PUF index 1 - */ -#define PUF_IDXBLK_L_DP_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX1_SHIFT)) & PUF_IDXBLK_L_DP_IDX1_MASK) - -#define PUF_IDXBLK_L_DP_IDX2_MASK (0x30U) -#define PUF_IDXBLK_L_DP_IDX2_SHIFT (4U) -/*! IDX2 - Use to block PUF index 2 - */ -#define PUF_IDXBLK_L_DP_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX2_SHIFT)) & PUF_IDXBLK_L_DP_IDX2_MASK) - -#define PUF_IDXBLK_L_DP_IDX3_MASK (0xC0U) -#define PUF_IDXBLK_L_DP_IDX3_SHIFT (6U) -/*! IDX3 - Use to block PUF index 3 - */ -#define PUF_IDXBLK_L_DP_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX3_SHIFT)) & PUF_IDXBLK_L_DP_IDX3_MASK) - -#define PUF_IDXBLK_L_DP_IDX4_MASK (0x300U) -#define PUF_IDXBLK_L_DP_IDX4_SHIFT (8U) -/*! IDX4 - Use to block PUF index 4 - */ -#define PUF_IDXBLK_L_DP_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX4_SHIFT)) & PUF_IDXBLK_L_DP_IDX4_MASK) - -#define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) -#define PUF_IDXBLK_L_DP_IDX5_SHIFT (10U) -/*! IDX5 - Use to block PUF index 5 - */ -#define PUF_IDXBLK_L_DP_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK) - -#define PUF_IDXBLK_L_DP_IDX6_MASK (0x3000U) -#define PUF_IDXBLK_L_DP_IDX6_SHIFT (12U) -/*! IDX6 - Use to block PUF index 6 - */ -#define PUF_IDXBLK_L_DP_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX6_SHIFT)) & PUF_IDXBLK_L_DP_IDX6_MASK) - -#define PUF_IDXBLK_L_DP_IDX7_MASK (0xC000U) -#define PUF_IDXBLK_L_DP_IDX7_SHIFT (14U) -/*! IDX7 - Use to block PUF index 7 - */ -#define PUF_IDXBLK_L_DP_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX7_SHIFT)) & PUF_IDXBLK_L_DP_IDX7_MASK) -/*! @} */ - -/*! @name SHIFT_STATUS - */ -/*! @{ */ - -#define PUF_SHIFT_STATUS_KEY0_MASK (0xFU) -#define PUF_SHIFT_STATUS_KEY0_SHIFT (0U) -/*! KEY0 - Index counter from key 0 shift register - */ -#define PUF_SHIFT_STATUS_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY0_SHIFT)) & PUF_SHIFT_STATUS_KEY0_MASK) - -#define PUF_SHIFT_STATUS_KEY1_MASK (0xF0U) -#define PUF_SHIFT_STATUS_KEY1_SHIFT (4U) -/*! KEY1 - Index counter from key 1 shift register - */ -#define PUF_SHIFT_STATUS_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY1_SHIFT)) & PUF_SHIFT_STATUS_KEY1_MASK) - -#define PUF_SHIFT_STATUS_KEY2_MASK (0xF00U) -#define PUF_SHIFT_STATUS_KEY2_SHIFT (8U) -/*! KEY2 - Index counter from key 2 shift register - */ -#define PUF_SHIFT_STATUS_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY2_SHIFT)) & PUF_SHIFT_STATUS_KEY2_MASK) - -#define PUF_SHIFT_STATUS_KEY3_MASK (0xF000U) -#define PUF_SHIFT_STATUS_KEY3_SHIFT (12U) -/*! KEY3 - Index counter from key 3 shift register - */ -#define PUF_SHIFT_STATUS_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY3_SHIFT)) & PUF_SHIFT_STATUS_KEY3_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PUF_Register_Masks */ - - -/* PUF - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PUF base address */ - #define PUF_BASE (0x5003B000u) - /** Peripheral PUF base address */ - #define PUF_BASE_NS (0x4003B000u) - /** Peripheral PUF base pointer */ - #define PUF ((PUF_Type *)PUF_BASE) - /** Peripheral PUF base pointer */ - #define PUF_NS ((PUF_Type *)PUF_BASE_NS) - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS { PUF_BASE } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS { PUF } - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS_NS { PUF_BASE_NS } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS_NS { PUF_NS } -#else - /** Peripheral PUF base address */ - #define PUF_BASE (0x4003B000u) - /** Peripheral PUF base pointer */ - #define PUF ((PUF_Type *)PUF_BASE) - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS { PUF_BASE } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS { PUF } -#endif -/** Interrupt vectors for the PUF peripheral type */ -#define PUF_IRQS { PUF_IRQn } - -/*! - * @} - */ /* end of group PUF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RNG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer - * @{ - */ - -/** RNG - Register Layout Typedef */ -typedef struct { - __I uint32_t RANDOM_NUMBER; /**< This register contains a random 32 bit number which is computed on demand, at each time it is read, offset: 0x0 */ - uint8_t RESERVED_0[4]; - __I uint32_t COUNTER_VAL; /**< , offset: 0x8 */ - __IO uint32_t COUNTER_CFG; /**< , offset: 0xC */ - __IO uint32_t ONLINE_TEST_CFG; /**< , offset: 0x10 */ - __I uint32_t ONLINE_TEST_VAL; /**< , offset: 0x14 */ - uint8_t RESERVED_1[4068]; - __I uint32_t MODULEID; /**< IP identifier, offset: 0xFFC */ -} RNG_Type; - -/* ---------------------------------------------------------------------------- - -- RNG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RNG_Register_Masks RNG Register Masks - * @{ - */ - -/*! @name RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read */ -/*! @{ */ - -#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK (0xFFFFFFFFU) -#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT (0U) -/*! RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read. - */ -#define RNG_RANDOM_NUMBER_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT)) & RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK) -/*! @} */ - -/*! @name COUNTER_VAL - */ -/*! @{ */ - -#define RNG_COUNTER_VAL_CLK_RATIO_MASK (0xFFU) -#define RNG_COUNTER_VAL_CLK_RATIO_SHIFT (0U) -/*! CLK_RATIO - Gives the ratio between the internal clocks frequencies and the register clock - * frequency for evaluation and certification purposes. - */ -#define RNG_COUNTER_VAL_CLK_RATIO(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_CLK_RATIO_SHIFT)) & RNG_COUNTER_VAL_CLK_RATIO_MASK) - -#define RNG_COUNTER_VAL_REFRESH_CNT_MASK (0x1F00U) -#define RNG_COUNTER_VAL_REFRESH_CNT_SHIFT (8U) -/*! REFRESH_CNT - Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER. - */ -#define RNG_COUNTER_VAL_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_REFRESH_CNT_SHIFT)) & RNG_COUNTER_VAL_REFRESH_CNT_MASK) -/*! @} */ - -/*! @name COUNTER_CFG - */ -/*! @{ */ - -#define RNG_COUNTER_CFG_MODE_MASK (0x3U) -#define RNG_COUNTER_CFG_MODE_SHIFT (0U) -/*! MODE - 00: disabled 01: update once. - */ -#define RNG_COUNTER_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_MODE_SHIFT)) & RNG_COUNTER_CFG_MODE_MASK) - -#define RNG_COUNTER_CFG_CLOCK_SEL_MASK (0x1CU) -#define RNG_COUNTER_CFG_CLOCK_SEL_SHIFT (2U) -/*! CLOCK_SEL - Selects the internal clock on which to compute statistics. - */ -#define RNG_COUNTER_CFG_CLOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_CLOCK_SEL_SHIFT)) & RNG_COUNTER_CFG_CLOCK_SEL_MASK) - -#define RNG_COUNTER_CFG_SHIFT4X_MASK (0xE0U) -#define RNG_COUNTER_CFG_SHIFT4X_SHIFT (5U) -/*! SHIFT4X - To be used to add precision to clock_ratio and determine 'entropy refill'. - */ -#define RNG_COUNTER_CFG_SHIFT4X(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_SHIFT4X_SHIFT)) & RNG_COUNTER_CFG_SHIFT4X_MASK) -/*! @} */ - -/*! @name ONLINE_TEST_CFG - */ -/*! @{ */ - -#define RNG_ONLINE_TEST_CFG_ACTIVATE_MASK (0x1U) -#define RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT (0U) -/*! ACTIVATE - 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER. - */ -#define RNG_ONLINE_TEST_CFG_ACTIVATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT)) & RNG_ONLINE_TEST_CFG_ACTIVATE_MASK) - -#define RNG_ONLINE_TEST_CFG_DATA_SEL_MASK (0x6U) -#define RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT (1U) -/*! DATA_SEL - Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one - * or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10: - * RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this - * field. - */ -#define RNG_ONLINE_TEST_CFG_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT)) & RNG_ONLINE_TEST_CFG_DATA_SEL_MASK) -/*! @} */ - -/*! @name ONLINE_TEST_VAL - */ -/*! @{ */ - -#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK (0xFU) -#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT (0U) -/*! LIVE_CHI_SQUARED - This value is updated as described in field 'activate'. - */ -#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK) - -#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK (0xF0U) -#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT (4U) -/*! MIN_CHI_SQUARED - This field is reset when 'activate'==0. - */ -#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) - -#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK (0xF00U) -#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT (8U) -/*! MAX_CHI_SQUARED - This field is reset when 'activate'==0. - */ -#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) -/*! @} */ - -/*! @name MODULEID - IP identifier */ -/*! @{ */ - -#define RNG_MODULEID_APERTURE_MASK (0xFFU) -#define RNG_MODULEID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture i. - */ -#define RNG_MODULEID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_APERTURE_SHIFT)) & RNG_MODULEID_APERTURE_MASK) - -#define RNG_MODULEID_MIN_REV_MASK (0xF00U) -#define RNG_MODULEID_MIN_REV_SHIFT (8U) -/*! MIN_REV - Minor revision i. - */ -#define RNG_MODULEID_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MIN_REV_SHIFT)) & RNG_MODULEID_MIN_REV_MASK) - -#define RNG_MODULEID_MAJ_REV_MASK (0xF000U) -#define RNG_MODULEID_MAJ_REV_SHIFT (12U) -/*! MAJ_REV - Major revision i. - */ -#define RNG_MODULEID_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MAJ_REV_SHIFT)) & RNG_MODULEID_MAJ_REV_MASK) - -#define RNG_MODULEID_ID_MASK (0xFFFF0000U) -#define RNG_MODULEID_ID_SHIFT (16U) -/*! ID - Identifier. - */ -#define RNG_MODULEID_ID(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_ID_SHIFT)) & RNG_MODULEID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group RNG_Register_Masks */ - - -/* RNG - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral RNG base address */ - #define RNG_BASE (0x5003A000u) - /** Peripheral RNG base address */ - #define RNG_BASE_NS (0x4003A000u) - /** Peripheral RNG base pointer */ - #define RNG ((RNG_Type *)RNG_BASE) - /** Peripheral RNG base pointer */ - #define RNG_NS ((RNG_Type *)RNG_BASE_NS) - /** Array initializer of RNG peripheral base addresses */ - #define RNG_BASE_ADDRS { RNG_BASE } - /** Array initializer of RNG peripheral base pointers */ - #define RNG_BASE_PTRS { RNG } - /** Array initializer of RNG peripheral base addresses */ - #define RNG_BASE_ADDRS_NS { RNG_BASE_NS } - /** Array initializer of RNG peripheral base pointers */ - #define RNG_BASE_PTRS_NS { RNG_NS } -#else - /** Peripheral RNG base address */ - #define RNG_BASE (0x4003A000u) - /** Peripheral RNG base pointer */ - #define RNG ((RNG_Type *)RNG_BASE) - /** Array initializer of RNG peripheral base addresses */ - #define RNG_BASE_ADDRS { RNG_BASE } - /** Array initializer of RNG peripheral base pointers */ - #define RNG_BASE_PTRS { RNG } -#endif - -/*! - * @} - */ /* end of group RNG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RTC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer - * @{ - */ - -/** RTC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ - __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ - __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ - __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ - __I uint32_t SUBSEC; /**< Sub-second counter register, offset: 0x10 */ - uint8_t RESERVED_0[44]; - __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */ -} RTC_Type; - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/*! @name CTRL - RTC control register */ -/*! @{ */ - -#define RTC_CTRL_SWRESET_MASK (0x1U) -#define RTC_CTRL_SWRESET_SHIFT (0U) -/*! SWRESET - Software reset control - * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. - * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value - * except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes - * to set any of the other bits within this register. Do not attempt to write to any bits of this register at - * the same time that the reset bit is being cleared. - */ -#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) - -#define RTC_CTRL_ALARM1HZ_MASK (0x4U) -#define RTC_CTRL_ALARM1HZ_SHIFT (2U) -/*! ALARM1HZ - RTC 1 Hz timer alarm flag status. - * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. - * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt - * request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. - */ -#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) - -#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) -#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) -/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status. - * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. - * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up - * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. - */ -#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) - -#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) -#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) -/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. - * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. - */ -#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) - -#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) -#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) -/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. - * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. - */ -#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) - -#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) -#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) -/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz - * timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). - * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. The 1 kHz RTC timer is enabled. - */ -#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) - -#define RTC_CTRL_RTC_EN_MASK (0x80U) -#define RTC_CTRL_RTC_EN_SHIFT (7U) -/*! RTC_EN - RTC enable. - * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should - * be 0 when writing to load a value in the RTC counter register. - * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate - * operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the - * high-resolution, 1 kHz clock, set bit 6 in this register. - */ -#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) - -#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) -#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) -/*! RTC_OSC_PD - RTC oscillator power-down control. - * 0b0..See RTC_OSC_BYPASS - * 0b1..RTC oscillator is powered-down. - */ -#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) - -#define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) -#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) -/*! RTC_OSC_BYPASS - RTC oscillator bypass control. - * 0b0..The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. - * 0b1..The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. - */ -#define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) - -#define RTC_CTRL_RTC_SUBSEC_ENA_MASK (0x400U) -#define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT (10U) -/*! RTC_SUBSEC_ENA - RTC Sub-second counter control. - * 0b0..The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD - * reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second - * counter, this bit will always read-back as a '0'. - * 0b1..The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first - * one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is - * set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip - * exits deep power-down mode. - */ -#define RTC_CTRL_RTC_SUBSEC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK) -/*! @} */ - -/*! @name MATCH - RTC match register */ -/*! @{ */ - -#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) -#define RTC_MATCH_MATVAL_SHIFT (0U) -/*! MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the - * alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. - */ -#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) -/*! @} */ - -/*! @name COUNT - RTC counter register */ -/*! @{ */ - -#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) -#define RTC_COUNT_VAL_SHIFT (0U) -/*! VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial - * value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC - * Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this - * register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after - * the RTC_EN bit is set. - */ -#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) -/*! @} */ - -/*! @name WAKE - High-resolution/wake-up timer control register */ -/*! @{ */ - -#define RTC_WAKE_VAL_MASK (0xFFFFU) -#define RTC_WAKE_VAL_SHIFT (0U) -/*! VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads - * a start count value into the wake-up timer and initializes a count-down sequence. Do not write - * to this register while counting is in progress. - */ -#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) -/*! @} */ - -/*! @name SUBSEC - Sub-second counter register */ -/*! @{ */ - -#define RTC_SUBSEC_SUBSEC_MASK (0x7FFFU) -#define RTC_SUBSEC_SUBSEC_SHIFT (0U) -/*! SUBSEC - A read reflects the current value of the 32KHz sub-second counter. This counter is - * cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz - * rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This - * counter must be re-enabled after exiting deep power-down mode or after the main RTC module is - * disabled and re-enabled. On modules not equipped with a sub-second counter, this register - * will read-back as all zeroes. - */ -#define RTC_SUBSEC_SUBSEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_SUBSEC_SHIFT)) & RTC_SUBSEC_SUBSEC_MASK) -/*! @} */ - -/*! @name GPREG - General Purpose register */ -/*! @{ */ - -#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU) -#define RTC_GPREG_GPDATA_SHIFT (0U) -/*! GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied. - */ -#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK) -/*! @} */ - -/* The count of RTC_GPREG */ -#define RTC_GPREG_COUNT (8U) - - -/*! - * @} - */ /* end of group RTC_Register_Masks */ - - -/* RTC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral RTC base address */ - #define RTC_BASE (0x5002C000u) - /** Peripheral RTC base address */ - #define RTC_BASE_NS (0x4002C000u) - /** Peripheral RTC base pointer */ - #define RTC ((RTC_Type *)RTC_BASE) - /** Peripheral RTC base pointer */ - #define RTC_NS ((RTC_Type *)RTC_BASE_NS) - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS { RTC_BASE } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS { RTC } - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS_NS { RTC_BASE_NS } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS_NS { RTC_NS } -#else - /** Peripheral RTC base address */ - #define RTC_BASE (0x4002C000u) - /** Peripheral RTC base pointer */ - #define RTC ((RTC_Type *)RTC_BASE) - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS { RTC_BASE } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS { RTC } -#endif -/** Interrupt vectors for the RTC peripheral type */ -#define RTC_IRQS { RTC_IRQn } - -/*! - * @} - */ /* end of group RTC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SCT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer - * @{ - */ - -/** SCT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ - union { /* offset: 0x4 */ - struct { /* offset: 0x4 */ - __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */ - __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */ - } CTRL_ACCESS16BIT; - __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ - }; - union { /* offset: 0x8 */ - struct { /* offset: 0x8 */ - __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */ - __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */ - } LIMIT_ACCESS16BIT; - __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ - }; - union { /* offset: 0xC */ - struct { /* offset: 0xC */ - __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */ - __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */ - } HALT_ACCESS16BIT; - __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ - }; - union { /* offset: 0x10 */ - struct { /* offset: 0x10 */ - __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */ - __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */ - } STOP_ACCESS16BIT; - __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ - }; - union { /* offset: 0x14 */ - struct { /* offset: 0x14 */ - __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */ - __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */ - } START_ACCESS16BIT; - __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ - }; - uint8_t RESERVED_0[40]; - union { /* offset: 0x40 */ - struct { /* offset: 0x40 */ - __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */ - __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */ - } COUNT_ACCESS16BIT; - __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ - }; - union { /* offset: 0x44 */ - struct { /* offset: 0x44 */ - __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */ - __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */ - } STATE_ACCESS16BIT; - __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ - }; - __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ - union { /* offset: 0x4C */ - struct { /* offset: 0x4C */ - __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */ - __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */ - } REGMODE_ACCESS16BIT; - __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ - }; - __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ - __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ - __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ - __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */ - __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */ - uint8_t RESERVED_1[140]; - __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ - __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ - __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ - __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ - union { /* offset: 0x100 */ - union { /* offset: 0x100, array step: 0x4 */ - struct { /* offset: 0x100, array step: 0x4 */ - __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */ - __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */ - } CAP_ACCESS16BIT[16]; - __IO uint32_t CAP[16]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ - }; - union { /* offset: 0x100, array step: 0x4 */ - struct { /* offset: 0x100, array step: 0x4 */ - __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */ - __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */ - } MATCH_ACCESS16BIT[16]; - __IO uint32_t MATCH[16]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ - }; - }; - uint8_t RESERVED_2[192]; - union { /* offset: 0x200 */ - union { /* offset: 0x200, array step: 0x4 */ - struct { /* offset: 0x200, array step: 0x4 */ - __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */ - __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */ - } CAPCTRL_ACCESS16BIT[16]; - __IO uint32_t CAPCTRL[16]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ - }; - union { /* offset: 0x200, array step: 0x4 */ - struct { /* offset: 0x200, array step: 0x4 */ - __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */ - __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */ - } MATCHREL_ACCESS16BIT[16]; - __IO uint32_t MATCHREL[16]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ - }; - }; - uint8_t RESERVED_3[192]; - struct { /* offset: 0x300, array step: 0x8 */ - __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ - __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ - } EV[16]; - uint8_t RESERVED_4[384]; - struct { /* offset: 0x500, array step: 0x8 */ - __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ - __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ - } OUT[10]; -} SCT_Type; - -/* ---------------------------------------------------------------------------- - -- SCT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Register_Masks SCT Register Masks - * @{ - */ - -/*! @name CONFIG - SCT configuration register */ -/*! @{ */ - -#define SCT_CONFIG_UNIFY_MASK (0x1U) -#define SCT_CONFIG_UNIFY_SHIFT (0U) -/*! UNIFY - SCT operation - * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. - * 0b1..The SCT operates as a unified 32-bit counter. - */ -#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) - -#define SCT_CONFIG_CLKMODE_MASK (0x6U) -#define SCT_CONFIG_CLKMODE_SHIFT (1U) -/*! CLKMODE - SCT clock mode - * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. - * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are - * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The - * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the - * high-performance, sampled-clock mode. - * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the - * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the - * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. - * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL - * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system - * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than - * the system clock. - */ -#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) - -#define SCT_CONFIG_CKSEL_MASK (0x78U) -#define SCT_CONFIG_CKSEL_SHIFT (3U) -/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent - * on the CLKMODE bit selection in this register. - * 0b0000..Rising edges on input 0. - * 0b0001..Falling edges on input 0. - * 0b0010..Rising edges on input 1. - * 0b0011..Falling edges on input 1. - * 0b0100..Rising edges on input 2. - * 0b0101..Falling edges on input 2. - * 0b0110..Rising edges on input 3. - * 0b0111..Falling edges on input 3. - * 0b1000..Rising edges on input 4. - * 0b1001..Falling edges on input 4. - * 0b1010..Rising edges on input 5. - * 0b1011..Falling edges on input 5. - * 0b1100..Rising edges on input 6. - * 0b1101..Falling edges on input 6. - * 0b1110..Rising edges on input 7. - * 0b1111..Falling edges on input 7. - */ -#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) - -#define SCT_CONFIG_NORELOAD_L_MASK (0x80U) -#define SCT_CONFIG_NORELOAD_L_SHIFT (7U) -/*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their - * respective reload registers. Setting this bit eliminates the need to write to the reload - * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any - * time. This bit applies to both the higher and lower registers when the UNIFY bit is set. - */ -#define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK) - -#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) -#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) -/*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their - * respective reload registers. Setting this bit eliminates the need to write to the reload - * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at - * any time. This bit is not used when the UNIFY bit is set. - */ -#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) - -#define SCT_CONFIG_INSYNC_MASK (0x1E00U) -#define SCT_CONFIG_INSYNC_SHIFT (9U) -/*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all - * other bits are reserved. A 1 in one of these bits subjects the corresponding input to - * synchronization to the SCT clock, before it is used to create an event. If an input is known to - * already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: - * The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input - * clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. - * It does not apply to the clock input specified in the CKSEL field. - */ -#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) - -#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) -#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) -/*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto - * LIMIT condition without the need to define an associated event. As with any LIMIT event, this - * automatic limit causes the counter to be cleared to zero in unidirectional mode or to change - * the direction of count in bi-directional mode. Software can write to set or clear this bit at - * any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. - */ -#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) - -#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) -#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) -/*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a - * de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, - * this automatic limit causes the counter to be cleared to zero in unidirectional mode or to - * change the direction of count in bi-directional mode. Software can write to set or clear this bit - * at any time. This bit is not used when the UNIFY bit is set. - */ -#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) -/*! @} */ - -/*! @name CTRLL - SCT_CTRLL register */ -/*! @{ */ - -#define SCT_CTRLL_DOWN_L_MASK (0x1U) -#define SCT_CTRLL_DOWN_L_SHIFT (0U) -/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit - * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit - * when the counter is counting down and a limit condition occurs or when the counter reaches 0. - */ -#define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK) - -#define SCT_CTRLL_STOP_L_MASK (0x2U) -#define SCT_CTRLL_STOP_L_SHIFT (1U) -/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events - * related to the counter can occur. If a designated start event occurs, this bit is cleared and - * counting resumes. - */ -#define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK) - -#define SCT_CTRLL_HALT_L_MASK (0x4U) -#define SCT_CTRLL_HALT_L_SHIFT (2U) -/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A - * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to - * remove the halt condition while keeping the SCT in the stop condition (not running) with a - * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, - * only software can clear this bit to restore counter operation. This bit is set on reset. - */ -#define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK) - -#define SCT_CTRLL_CLRCTR_L_MASK (0x8U) -#define SCT_CTRLL_CLRCTR_L_SHIFT (3U) -/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. - */ -#define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK) - -#define SCT_CTRLL_BIDIR_L_MASK (0x10U) -#define SCT_CTRLL_BIDIR_L_SHIFT (4U) -/*! BIDIR_L - L or unified counter direction select - * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. - * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK) - -#define SCT_CTRLL_PRE_L_MASK (0x1FE0U) -#define SCT_CTRLL_PRE_L_SHIFT (5U) -/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified - * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. - * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - */ -#define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK) -/*! @} */ - -/*! @name CTRLH - SCT_CTRLH register */ -/*! @{ */ - -#define SCT_CTRLH_DOWN_H_MASK (0x1U) -#define SCT_CTRLH_DOWN_H_SHIFT (0U) -/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the - * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit - * when the counter is counting down and a limit condition occurs or when the counter reaches 0. - */ -#define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK) - -#define SCT_CTRLH_STOP_H_MASK (0x2U) -#define SCT_CTRLH_STOP_H_SHIFT (1U) -/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to - * the counter can occur. If such an event matches the mask in the Start register, this bit is - * cleared and counting resumes. - */ -#define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK) - -#define SCT_CTRLH_HALT_H_MASK (0x4U) -#define SCT_CTRLH_HALT_H_SHIFT (2U) -/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets - * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the - * halt condition while keeping the SCT in the stop condition (not running) with a single write to - * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit - * can only be cleared by software to restore counter operation. This bit is set on reset. - */ -#define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK) - -#define SCT_CTRLH_CLRCTR_H_MASK (0x8U) -#define SCT_CTRLH_CLRCTR_H_SHIFT (3U) -/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. - */ -#define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK) - -#define SCT_CTRLH_BIDIR_H_MASK (0x10U) -#define SCT_CTRLH_BIDIR_H_SHIFT (4U) -/*! BIDIR_H - Direction select - * 0b0..The H counter counts up to its limit condition, then is cleared to zero. - * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK) - -#define SCT_CTRLH_PRE_H_MASK (0x1FE0U) -#define SCT_CTRLH_PRE_H_SHIFT (5U) -/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. - * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the - * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - */ -#define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK) -/*! @} */ - -/*! @name CTRL - SCT control register */ -/*! @{ */ - -#define SCT_CTRL_DOWN_L_MASK (0x1U) -#define SCT_CTRL_DOWN_L_SHIFT (0U) -/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit - * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit - * when the counter is counting down and a limit condition occurs or when the counter reaches 0. - */ -#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) - -#define SCT_CTRL_STOP_L_MASK (0x2U) -#define SCT_CTRL_STOP_L_SHIFT (1U) -/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events - * related to the counter can occur. If a designated start event occurs, this bit is cleared and - * counting resumes. - */ -#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) - -#define SCT_CTRL_HALT_L_MASK (0x4U) -#define SCT_CTRL_HALT_L_SHIFT (2U) -/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A - * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to - * remove the halt condition while keeping the SCT in the stop condition (not running) with a - * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, - * only software can clear this bit to restore counter operation. This bit is set on reset. - */ -#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) - -#define SCT_CTRL_CLRCTR_L_MASK (0x8U) -#define SCT_CTRL_CLRCTR_L_SHIFT (3U) -/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. - */ -#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) - -#define SCT_CTRL_BIDIR_L_MASK (0x10U) -#define SCT_CTRL_BIDIR_L_SHIFT (4U) -/*! BIDIR_L - L or unified counter direction select - * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. - * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) - -#define SCT_CTRL_PRE_L_MASK (0x1FE0U) -#define SCT_CTRL_PRE_L_SHIFT (5U) -/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified - * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. - * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - */ -#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) - -#define SCT_CTRL_DOWN_H_MASK (0x10000U) -#define SCT_CTRL_DOWN_H_SHIFT (16U) -/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the - * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit - * when the counter is counting down and a limit condition occurs or when the counter reaches 0. - */ -#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) - -#define SCT_CTRL_STOP_H_MASK (0x20000U) -#define SCT_CTRL_STOP_H_SHIFT (17U) -/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to - * the counter can occur. If such an event matches the mask in the Start register, this bit is - * cleared and counting resumes. - */ -#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) - -#define SCT_CTRL_HALT_H_MASK (0x40000U) -#define SCT_CTRL_HALT_H_SHIFT (18U) -/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets - * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the - * halt condition while keeping the SCT in the stop condition (not running) with a single write to - * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit - * can only be cleared by software to restore counter operation. This bit is set on reset. - */ -#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) - -#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) -#define SCT_CTRL_CLRCTR_H_SHIFT (19U) -/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. - */ -#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) - -#define SCT_CTRL_BIDIR_H_MASK (0x100000U) -#define SCT_CTRL_BIDIR_H_SHIFT (20U) -/*! BIDIR_H - Direction select - * 0b0..The H counter counts up to its limit condition, then is cleared to zero. - * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) - -#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) -#define SCT_CTRL_PRE_H_SHIFT (21U) -/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. - * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the - * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - */ -#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) -/*! @} */ - -/*! @name LIMITL - SCT_LIMITL register */ -/*! @{ */ - -#define SCT_LIMITL_LIMITL_MASK (0xFFFFU) -#define SCT_LIMITL_LIMITL_SHIFT (0U) -#define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK) -/*! @} */ - -/*! @name LIMITH - SCT_LIMITH register */ -/*! @{ */ - -#define SCT_LIMITH_LIMITH_MASK (0xFFFFU) -#define SCT_LIMITH_LIMITH_SHIFT (0U) -#define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK) -/*! @} */ - -/*! @name LIMIT - SCT limit event select register */ -/*! @{ */ - -#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) -#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) -/*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter - * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) - -#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) -#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) -/*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit - * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) -/*! @} */ - -/*! @name HALTL - SCT_HALTL register */ -/*! @{ */ - -#define SCT_HALTL_HALTL_MASK (0xFFFFU) -#define SCT_HALTL_HALTL_SHIFT (0U) -#define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK) -/*! @} */ - -/*! @name HALTH - SCT_HALTH register */ -/*! @{ */ - -#define SCT_HALTH_HALTH_MASK (0xFFFFU) -#define SCT_HALTH_HALTH_SHIFT (0U) -#define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK) -/*! @} */ - -/*! @name HALT - SCT halt event select register */ -/*! @{ */ - -#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) -#define SCT_HALT_HALTMSK_L_SHIFT (0U) -/*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, - * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) - -#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) -#define SCT_HALT_HALTMSK_H_SHIFT (16U) -/*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, - * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) -/*! @} */ - -/*! @name STOPL - SCT_STOPL register */ -/*! @{ */ - -#define SCT_STOPL_STOPL_MASK (0xFFFFU) -#define SCT_STOPL_STOPL_SHIFT (0U) -#define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK) -/*! @} */ - -/*! @name STOPH - SCT_STOPH register */ -/*! @{ */ - -#define SCT_STOPH_STOPH_MASK (0xFFFFU) -#define SCT_STOPH_STOPH_SHIFT (0U) -#define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK) -/*! @} */ - -/*! @name STOP - SCT stop event select register */ -/*! @{ */ - -#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) -#define SCT_STOP_STOPMSK_L_SHIFT (0U) -/*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, - * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) - -#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) -#define SCT_STOP_STOPMSK_H_SHIFT (16U) -/*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, - * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) -/*! @} */ - -/*! @name STARTL - SCT_STARTL register */ -/*! @{ */ - -#define SCT_STARTL_STARTL_MASK (0xFFFFU) -#define SCT_STARTL_STARTL_SHIFT (0U) -#define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK) -/*! @} */ - -/*! @name STARTH - SCT_STARTH register */ -/*! @{ */ - -#define SCT_STARTH_STARTH_MASK (0xFFFFU) -#define SCT_STARTH_STARTH_SHIFT (0U) -#define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK) -/*! @} */ - -/*! @name START - SCT start event select register */ -/*! @{ */ - -#define SCT_START_STARTMSK_L_MASK (0xFFFFU) -#define SCT_START_STARTMSK_L_SHIFT (0U) -/*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit - * 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) - -#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) -#define SCT_START_STARTMSK_H_SHIFT (16U) -/*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit - * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) -/*! @} */ - -/*! @name COUNTL - SCT_COUNTL register */ -/*! @{ */ - -#define SCT_COUNTL_COUNTL_MASK (0xFFFFU) -#define SCT_COUNTL_COUNTL_SHIFT (0U) -#define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK) -/*! @} */ - -/*! @name COUNTH - SCT_COUNTH register */ -/*! @{ */ - -#define SCT_COUNTH_COUNTH_MASK (0xFFFFU) -#define SCT_COUNTH_COUNTH_SHIFT (0U) -#define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK) -/*! @} */ - -/*! @name COUNT - SCT counter register */ -/*! @{ */ - -#define SCT_COUNT_CTR_L_MASK (0xFFFFU) -#define SCT_COUNT_CTR_L_SHIFT (0U) -/*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write - * the lower 16 bits of the 32-bit unified counter. - */ -#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) - -#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) -#define SCT_COUNT_CTR_H_SHIFT (16U) -/*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write - * the upper 16 bits of the 32-bit unified counter. - */ -#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) -/*! @} */ - -/*! @name STATEL - SCT_STATEL register */ -/*! @{ */ - -#define SCT_STATEL_STATEL_MASK (0xFFFFU) -#define SCT_STATEL_STATEL_SHIFT (0U) -#define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK) -/*! @} */ - -/*! @name STATEH - SCT_STATEH register */ -/*! @{ */ - -#define SCT_STATEH_STATEH_MASK (0xFFFFU) -#define SCT_STATEH_STATEH_SHIFT (0U) -#define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK) -/*! @} */ - -/*! @name STATE - SCT state register */ -/*! @{ */ - -#define SCT_STATE_STATE_L_MASK (0x1FU) -#define SCT_STATE_STATE_L_SHIFT (0U) -/*! STATE_L - State variable. - */ -#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) - -#define SCT_STATE_STATE_H_MASK (0x1F0000U) -#define SCT_STATE_STATE_H_SHIFT (16U) -/*! STATE_H - State variable. - */ -#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) -/*! @} */ - -/*! @name INPUT - SCT input register */ -/*! @{ */ - -#define SCT_INPUT_AIN0_MASK (0x1U) -#define SCT_INPUT_AIN0_SHIFT (0U) -/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) - -#define SCT_INPUT_AIN1_MASK (0x2U) -#define SCT_INPUT_AIN1_SHIFT (1U) -/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) - -#define SCT_INPUT_AIN2_MASK (0x4U) -#define SCT_INPUT_AIN2_SHIFT (2U) -/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) - -#define SCT_INPUT_AIN3_MASK (0x8U) -#define SCT_INPUT_AIN3_SHIFT (3U) -/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) - -#define SCT_INPUT_AIN4_MASK (0x10U) -#define SCT_INPUT_AIN4_SHIFT (4U) -/*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) - -#define SCT_INPUT_AIN5_MASK (0x20U) -#define SCT_INPUT_AIN5_SHIFT (5U) -/*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) - -#define SCT_INPUT_AIN6_MASK (0x40U) -#define SCT_INPUT_AIN6_SHIFT (6U) -/*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) - -#define SCT_INPUT_AIN7_MASK (0x80U) -#define SCT_INPUT_AIN7_SHIFT (7U) -/*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) - -#define SCT_INPUT_AIN8_MASK (0x100U) -#define SCT_INPUT_AIN8_SHIFT (8U) -/*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) - -#define SCT_INPUT_AIN9_MASK (0x200U) -#define SCT_INPUT_AIN9_SHIFT (9U) -/*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) - -#define SCT_INPUT_AIN10_MASK (0x400U) -#define SCT_INPUT_AIN10_SHIFT (10U) -/*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) - -#define SCT_INPUT_AIN11_MASK (0x800U) -#define SCT_INPUT_AIN11_SHIFT (11U) -/*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) - -#define SCT_INPUT_AIN12_MASK (0x1000U) -#define SCT_INPUT_AIN12_SHIFT (12U) -/*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) - -#define SCT_INPUT_AIN13_MASK (0x2000U) -#define SCT_INPUT_AIN13_SHIFT (13U) -/*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) - -#define SCT_INPUT_AIN14_MASK (0x4000U) -#define SCT_INPUT_AIN14_SHIFT (14U) -/*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) - -#define SCT_INPUT_AIN15_MASK (0x8000U) -#define SCT_INPUT_AIN15_SHIFT (15U) -/*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) - -#define SCT_INPUT_SIN0_MASK (0x10000U) -#define SCT_INPUT_SIN0_SHIFT (16U) -/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) - -#define SCT_INPUT_SIN1_MASK (0x20000U) -#define SCT_INPUT_SIN1_SHIFT (17U) -/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) - -#define SCT_INPUT_SIN2_MASK (0x40000U) -#define SCT_INPUT_SIN2_SHIFT (18U) -/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) - -#define SCT_INPUT_SIN3_MASK (0x80000U) -#define SCT_INPUT_SIN3_SHIFT (19U) -/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) - -#define SCT_INPUT_SIN4_MASK (0x100000U) -#define SCT_INPUT_SIN4_SHIFT (20U) -/*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) - -#define SCT_INPUT_SIN5_MASK (0x200000U) -#define SCT_INPUT_SIN5_SHIFT (21U) -/*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) - -#define SCT_INPUT_SIN6_MASK (0x400000U) -#define SCT_INPUT_SIN6_SHIFT (22U) -/*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) - -#define SCT_INPUT_SIN7_MASK (0x800000U) -#define SCT_INPUT_SIN7_SHIFT (23U) -/*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) - -#define SCT_INPUT_SIN8_MASK (0x1000000U) -#define SCT_INPUT_SIN8_SHIFT (24U) -/*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) - -#define SCT_INPUT_SIN9_MASK (0x2000000U) -#define SCT_INPUT_SIN9_SHIFT (25U) -/*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) - -#define SCT_INPUT_SIN10_MASK (0x4000000U) -#define SCT_INPUT_SIN10_SHIFT (26U) -/*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) - -#define SCT_INPUT_SIN11_MASK (0x8000000U) -#define SCT_INPUT_SIN11_SHIFT (27U) -/*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) - -#define SCT_INPUT_SIN12_MASK (0x10000000U) -#define SCT_INPUT_SIN12_SHIFT (28U) -/*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) - -#define SCT_INPUT_SIN13_MASK (0x20000000U) -#define SCT_INPUT_SIN13_SHIFT (29U) -/*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) - -#define SCT_INPUT_SIN14_MASK (0x40000000U) -#define SCT_INPUT_SIN14_SHIFT (30U) -/*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) - -#define SCT_INPUT_SIN15_MASK (0x80000000U) -#define SCT_INPUT_SIN15_SHIFT (31U) -/*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) -/*! @} */ - -/*! @name REGMODEL - SCT_REGMODEL register */ -/*! @{ */ - -#define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU) -#define SCT_REGMODEL_REGMODEL_SHIFT (0U) -#define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK) -/*! @} */ - -/*! @name REGMODEH - SCT_REGMODEH register */ -/*! @{ */ - -#define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU) -#define SCT_REGMODEH_REGMODEH_SHIFT (0U) -#define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK) -/*! @} */ - -/*! @name REGMODE - SCT match/capture mode register */ -/*! @{ */ - -#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) -#define SCT_REGMODE_REGMOD_L_SHIFT (0U) -/*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, - * etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as - * match register. 1 = register operates as capture register. - */ -#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) - -#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) -#define SCT_REGMODE_REGMOD_H_SHIFT (16U) -/*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit - * 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as - * match registers. 1 = register operates as capture registers. - */ -#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) -/*! @} */ - -/*! @name OUTPUT - SCT output register */ -/*! @{ */ - -#define SCT_OUTPUT_OUT_MASK (0xFFFFU) -#define SCT_OUTPUT_OUT_SHIFT (0U) -/*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the - * corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of - * outputs in this SCT. - */ -#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) -/*! @} */ - -/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ -/*! @{ */ - -#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) -#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) -/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) -#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) -/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) -#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) -/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) -#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) -/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) -#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) -/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) -#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) -/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) -#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) -/*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) -#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) -/*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) -#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) -/*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) -#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) -/*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) -#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) -/*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) -#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) -/*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) -/*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) -/*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) -/*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) -/*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) -/*! @} */ - -/*! @name RES - SCT conflict resolution register */ -/*! @{ */ - -#define SCT_RES_O0RES_MASK (0x3U) -#define SCT_RES_O0RES_SHIFT (0U) -/*! O0RES - Effect of simultaneous set and clear on output 0. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR0 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) - -#define SCT_RES_O1RES_MASK (0xCU) -#define SCT_RES_O1RES_SHIFT (2U) -/*! O1RES - Effect of simultaneous set and clear on output 1. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR1 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) - -#define SCT_RES_O2RES_MASK (0x30U) -#define SCT_RES_O2RES_SHIFT (4U) -/*! O2RES - Effect of simultaneous set and clear on output 2. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output n (or set based on the SETCLR2 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) - -#define SCT_RES_O3RES_MASK (0xC0U) -#define SCT_RES_O3RES_SHIFT (6U) -/*! O3RES - Effect of simultaneous set and clear on output 3. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR3 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) - -#define SCT_RES_O4RES_MASK (0x300U) -#define SCT_RES_O4RES_SHIFT (8U) -/*! O4RES - Effect of simultaneous set and clear on output 4. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR4 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) - -#define SCT_RES_O5RES_MASK (0xC00U) -#define SCT_RES_O5RES_SHIFT (10U) -/*! O5RES - Effect of simultaneous set and clear on output 5. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR5 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) - -#define SCT_RES_O6RES_MASK (0x3000U) -#define SCT_RES_O6RES_SHIFT (12U) -/*! O6RES - Effect of simultaneous set and clear on output 6. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR6 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) - -#define SCT_RES_O7RES_MASK (0xC000U) -#define SCT_RES_O7RES_SHIFT (14U) -/*! O7RES - Effect of simultaneous set and clear on output 7. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output n (or set based on the SETCLR7 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) - -#define SCT_RES_O8RES_MASK (0x30000U) -#define SCT_RES_O8RES_SHIFT (16U) -/*! O8RES - Effect of simultaneous set and clear on output 8. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR8 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) - -#define SCT_RES_O9RES_MASK (0xC0000U) -#define SCT_RES_O9RES_SHIFT (18U) -/*! O9RES - Effect of simultaneous set and clear on output 9. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR9 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) - -#define SCT_RES_O10RES_MASK (0x300000U) -#define SCT_RES_O10RES_SHIFT (20U) -/*! O10RES - Effect of simultaneous set and clear on output 10. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR10 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) - -#define SCT_RES_O11RES_MASK (0xC00000U) -#define SCT_RES_O11RES_SHIFT (22U) -/*! O11RES - Effect of simultaneous set and clear on output 11. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR11 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) - -#define SCT_RES_O12RES_MASK (0x3000000U) -#define SCT_RES_O12RES_SHIFT (24U) -/*! O12RES - Effect of simultaneous set and clear on output 12. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR12 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) - -#define SCT_RES_O13RES_MASK (0xC000000U) -#define SCT_RES_O13RES_SHIFT (26U) -/*! O13RES - Effect of simultaneous set and clear on output 13. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR13 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) - -#define SCT_RES_O14RES_MASK (0x30000000U) -#define SCT_RES_O14RES_SHIFT (28U) -/*! O14RES - Effect of simultaneous set and clear on output 14. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR14 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) - -#define SCT_RES_O15RES_MASK (0xC0000000U) -#define SCT_RES_O15RES_SHIFT (30U) -/*! O15RES - Effect of simultaneous set and clear on output 15. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR15 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) -/*! @} */ - -/*! @name DMAREQ0 - SCT DMA request 0 register */ -/*! @{ */ - -#define SCT_DMAREQ0_DEV_0_MASK (0xFFFFU) -#define SCT_DMAREQ0_DEV_0_SHIFT (0U) -/*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, - * etc.). The number of bits = number of events in this SCT. - */ -#define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK) - -#define SCT_DMAREQ0_DRL0_MASK (0x40000000U) -#define SCT_DMAREQ0_DRL0_SHIFT (30U) -/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. - */ -#define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK) - -#define SCT_DMAREQ0_DRQ0_MASK (0x80000000U) -#define SCT_DMAREQ0_DRQ0_SHIFT (31U) -/*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA - * channel is enabled and properly set up, it is unlikely that software will see this flag, it will - * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA - * setup. - */ -#define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK) -/*! @} */ - -/*! @name DMAREQ1 - SCT DMA request 1 register */ -/*! @{ */ - -#define SCT_DMAREQ1_DEV_1_MASK (0xFFFFU) -#define SCT_DMAREQ1_DEV_1_SHIFT (0U) -/*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, - * etc.). The number of bits = number of events in this SCT. - */ -#define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK) - -#define SCT_DMAREQ1_DRL1_MASK (0x40000000U) -#define SCT_DMAREQ1_DRL1_SHIFT (30U) -/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. - */ -#define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK) - -#define SCT_DMAREQ1_DRQ1_MASK (0x80000000U) -#define SCT_DMAREQ1_DRQ1_SHIFT (31U) -/*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA - * channel is enabled and properly set up, it is unlikely that software will see this flag, it will - * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA - * setup. - */ -#define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK) -/*! @} */ - -/*! @name EVEN - SCT event interrupt enable register */ -/*! @{ */ - -#define SCT_EVEN_IEN_MASK (0xFFFFU) -#define SCT_EVEN_IEN_SHIFT (0U) -/*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are - * both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in - * this SCT. - */ -#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) -/*! @} */ - -/*! @name EVFLAG - SCT event flag register */ -/*! @{ */ - -#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) -#define SCT_EVFLAG_FLAG_SHIFT (0U) -/*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit - * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) -/*! @} */ - -/*! @name CONEN - SCT conflict interrupt enable register */ -/*! @{ */ - -#define SCT_CONEN_NCEN_MASK (0xFFFFU) -#define SCT_CONEN_NCEN_SHIFT (0U) -/*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag - * register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of - * outputs in this SCT. - */ -#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) -/*! @} */ - -/*! @name CONFLAG - SCT conflict flag register */ -/*! @{ */ - -#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) -#define SCT_CONFLAG_NCFLAG_SHIFT (0U) -/*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was - * last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = - * number of outputs in this SCT. - */ -#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) - -#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) -#define SCT_CONFLAG_BUSERRL_SHIFT (30U) -/*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE - * L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write - * to certain L and H registers can be half successful and half unsuccessful. - */ -#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) - -#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) -#define SCT_CONFLAG_BUSERRH_SHIFT (31U) -/*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or - * the Output register when the H counter was not halted. - */ -#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) -/*! @} */ - -/*! @name CAPL - SCT_CAPL register */ -/*! @{ */ - -#define SCT_CAPL_CAPL_MASK (0xFFFFU) -#define SCT_CAPL_CAPL_SHIFT (0U) -#define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK) -/*! @} */ - -/* The count of SCT_CAPL */ -#define SCT_CAPL_COUNT (16U) - -/*! @name CAPH - SCT_CAPH register */ -/*! @{ */ - -#define SCT_CAPH_CAPH_MASK (0xFFFFU) -#define SCT_CAPH_CAPH_SHIFT (0U) -#define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK) -/*! @} */ - -/* The count of SCT_CAPH */ -#define SCT_CAPH_COUNT (16U) - -/*! @name CAP - SCT capture register of capture channel */ -/*! @{ */ - -#define SCT_CAP_CAPn_L_MASK (0xFFFFU) -#define SCT_CAP_CAPn_L_SHIFT (0U) -/*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. - * When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last - * captured. - */ -#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK) - -#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U) -#define SCT_CAP_CAPn_H_SHIFT (16U) -/*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. - * When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last - * captured. - */ -#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK) -/*! @} */ - -/* The count of SCT_CAP */ -#define SCT_CAP_COUNT (16U) - -/*! @name MATCHL - SCT_MATCHL register */ -/*! @{ */ - -#define SCT_MATCHL_MATCHL_MASK (0xFFFFU) -#define SCT_MATCHL_MATCHL_SHIFT (0U) -#define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK) -/*! @} */ - -/* The count of SCT_MATCHL */ -#define SCT_MATCHL_COUNT (16U) - -/*! @name MATCHH - SCT_MATCHH register */ -/*! @{ */ - -#define SCT_MATCHH_MATCHH_MASK (0xFFFFU) -#define SCT_MATCHH_MATCHH_SHIFT (0U) -#define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK) -/*! @} */ - -/* The count of SCT_MATCHH */ -#define SCT_MATCHH_COUNT (16U) - -/*! @name MATCH - SCT match value register of match channels */ -/*! @{ */ - -#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU) -#define SCT_MATCH_MATCHn_L_SHIFT (0U) -/*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When - * UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified - * counter. - */ -#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK) - -#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U) -#define SCT_MATCH_MATCHn_H_SHIFT (16U) -/*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When - * UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified - * counter. - */ -#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK) -/*! @} */ - -/* The count of SCT_MATCH */ -#define SCT_MATCH_COUNT (16U) - -/*! @name CAPCTRLL - SCT_CAPCTRLL register */ -/*! @{ */ - -#define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU) -#define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U) -#define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK) -/*! @} */ - -/* The count of SCT_CAPCTRLL */ -#define SCT_CAPCTRLL_COUNT (16U) - -/*! @name CAPCTRLH - SCT_CAPCTRLH register */ -/*! @{ */ - -#define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU) -#define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U) -#define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK) -/*! @} */ - -/* The count of SCT_CAPCTRLH */ -#define SCT_CAPCTRLH_COUNT (16U) - -/*! @name CAPCTRL - SCT capture control register */ -/*! @{ */ - -#define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU) -#define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U) -/*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) - * register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of - * match/captures in this SCT. - */ -#define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK) - -#define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) -#define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U) -/*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event - * 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - */ -#define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK) -/*! @} */ - -/* The count of SCT_CAPCTRL */ -#define SCT_CAPCTRL_COUNT (16U) - -/*! @name MATCHRELL - SCT_MATCHRELL register */ -/*! @{ */ - -#define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU) -#define SCT_MATCHRELL_MATCHRELL_SHIFT (0U) -#define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK) -/*! @} */ - -/* The count of SCT_MATCHRELL */ -#define SCT_MATCHRELL_COUNT (16U) - -/*! @name MATCHRELH - SCT_MATCHRELH register */ -/*! @{ */ - -#define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU) -#define SCT_MATCHRELH_MATCHRELH_SHIFT (0U) -#define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK) -/*! @} */ - -/* The count of SCT_MATCHRELH */ -#define SCT_MATCHRELH_COUNT (16U) - -/*! @name MATCHREL - SCT match reload value register */ -/*! @{ */ - -#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU) -#define SCT_MATCHREL_RELOADn_L_SHIFT (0U) -/*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. - * When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn - * register. - */ -#define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK) - -#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U) -#define SCT_MATCHREL_RELOADn_H_SHIFT (16U) -/*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When - * UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn - * register. - */ -#define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK) -/*! @} */ - -/* The count of SCT_MATCHREL */ -#define SCT_MATCHREL_COUNT (16U) - -/*! @name EV_STATE - SCT event state register 0 */ -/*! @{ */ - -#define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFU) -#define SCT_EV_STATE_STATEMSKn_SHIFT (0U) -/*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT - * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of - * bits = number of states in this SCT. - */ -#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK) -/*! @} */ - -/* The count of SCT_EV_STATE */ -#define SCT_EV_STATE_COUNT (16U) - -/*! @name EV_CTRL - SCT event control register 0 */ -/*! @{ */ - -#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU) -#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U) -/*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur - * only when the counter selected by the HEVENT bit is running. - */ -#define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK) - -#define SCT_EV_CTRL_HEVENT_MASK (0x10U) -#define SCT_EV_CTRL_HEVENT_SHIFT (4U) -/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. - * 0b0..Selects the L state and the L match register selected by MATCHSEL. - * 0b1..Selects the H state and the H match register selected by MATCHSEL. - */ -#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK) - -#define SCT_EV_CTRL_OUTSEL_MASK (0x20U) -#define SCT_EV_CTRL_OUTSEL_SHIFT (5U) -/*! OUTSEL - Input/output select - * 0b0..Selects the inputs selected by IOSEL. - * 0b1..Selects the outputs selected by IOSEL. - */ -#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK) - -#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U) -#define SCT_EV_CTRL_IOSEL_SHIFT (6U) -/*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not - * select an input in this register if CKMODE is 1x. In this case the clock input is an implicit - * ingredient of every event. - */ -#define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK) - -#define SCT_EV_CTRL_IOCOND_MASK (0xC00U) -#define SCT_EV_CTRL_IOCOND_SHIFT (10U) -/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the - * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state - * detection, an input must have a minimum pulse width of at least one SCT clock period . - * 0b00..LOW - * 0b01..Rise - * 0b10..Fall - * 0b11..HIGH - */ -#define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK) - -#define SCT_EV_CTRL_COMBMODE_MASK (0x3000U) -#define SCT_EV_CTRL_COMBMODE_SHIFT (12U) -/*! COMBMODE - Selects how the specified match and I/O condition are used and combined. - * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. - * 0b01..MATCH. Uses the specified match only. - * 0b10..IO. Uses the specified I/O condition only. - * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. - */ -#define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK) - -#define SCT_EV_CTRL_STATELD_MASK (0x4000U) -#define SCT_EV_CTRL_STATELD_SHIFT (14U) -/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this - * event is the highest-numbered event occurring for that state. - * 0b0..STATEV value is added into STATE (the carry-out is ignored). - * 0b1..STATEV value is loaded into STATE. - */ -#define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK) - -#define SCT_EV_CTRL_STATEV_MASK (0xF8000U) -#define SCT_EV_CTRL_STATEV_SHIFT (15U) -/*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on - * STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and - * STATEV are both zero, there is no change to the STATE value. - */ -#define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK) - -#define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U) -#define SCT_EV_CTRL_MATCHMEM_SHIFT (20U) -/*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the - * triggering of this event, then a match is considered to be active whenever the counter value is - * GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR - * EQUAL TO the match value when counting down. If this bit is zero, a match is only be active - * during the cycle when the counter is equal to the match value. - */ -#define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK) - -#define SCT_EV_CTRL_DIRECTION_MASK (0x600000U) -#define SCT_EV_CTRL_DIRECTION_SHIFT (21U) -/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters - * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. - * 0b00..Direction independent. This event is triggered regardless of the count direction. - * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. - * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. - */ -#define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK) -/*! @} */ - -/* The count of SCT_EV_CTRL */ -#define SCT_EV_CTRL_COUNT (16U) - -/*! @name OUT_SET - SCT output 0 set register */ -/*! @{ */ - -#define SCT_OUT_SET_SET_MASK (0xFFFFU) -#define SCT_OUT_SET_SET_SHIFT (0U) -/*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output - * 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the - * counter is used in bi-directional mode, it is possible to reverse the action specified by the - * output set and clear registers when counting down, See the OUTPUTCTRL register. - */ -#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) -/*! @} */ - -/* The count of SCT_OUT_SET */ -#define SCT_OUT_SET_COUNT (10U) - -/*! @name OUT_CLR - SCT output 0 clear register */ -/*! @{ */ - -#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) -#define SCT_OUT_CLR_CLR_SHIFT (0U) -/*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 - * = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the - * counter is used in bi-directional mode, it is possible to reverse the action specified by the - * output set and clear registers when counting down, See the OUTPUTCTRL register. - */ -#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) -/*! @} */ - -/* The count of SCT_OUT_CLR */ -#define SCT_OUT_CLR_COUNT (10U) - - -/*! - * @} - */ /* end of group SCT_Register_Masks */ - - -/* SCT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SCT0 base address */ - #define SCT0_BASE (0x50085000u) - /** Peripheral SCT0 base address */ - #define SCT0_BASE_NS (0x40085000u) - /** Peripheral SCT0 base pointer */ - #define SCT0 ((SCT_Type *)SCT0_BASE) - /** Peripheral SCT0 base pointer */ - #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS { SCT0_BASE } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS { SCT0 } - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS_NS { SCT0_NS } -#else - /** Peripheral SCT0 base address */ - #define SCT0_BASE (0x40085000u) - /** Peripheral SCT0 base pointer */ - #define SCT0 ((SCT_Type *)SCT0_BASE) - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS { SCT0_BASE } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS { SCT0 } -#endif -/** Interrupt vectors for the SCT peripheral type */ -#define SCT_IRQS { SCT0_IRQn } - -/*! - * @} - */ /* end of group SCT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SDIF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer - * @{ - */ - -/** SDIF - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register, offset: 0x0 */ - __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */ - __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */ - __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */ - __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */ - __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */ - __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */ - __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */ - __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */ - __IO uint32_t CMD; /**< Command register, offset: 0x2C */ - __IO uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */ - __IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */ - __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */ - __IO uint32_t STATUS; /**< Status register, offset: 0x48 */ - __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */ - __IO uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */ - __IO uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */ - uint8_t RESERVED_1[4]; - __IO uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */ - __IO uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */ - __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */ - uint8_t RESERVED_2[16]; - __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */ - uint8_t RESERVED_3[4]; - __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */ - __IO uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */ - __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */ - __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */ - __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */ - __IO uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */ - __IO uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */ - uint8_t RESERVED_4[100]; - __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */ - __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */ - uint8_t RESERVED_5[248]; - __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */ -} SDIF_Type; - -/* ---------------------------------------------------------------------------- - -- SDIF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDIF_Register_Masks SDIF Register Masks - * @{ - */ - -/*! @name CTRL - Control register */ -/*! @{ */ - -#define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U) -#define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U) -/*! CONTROLLER_RESET - Controller reset. - */ -#define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK) - -#define SDIF_CTRL_FIFO_RESET_MASK (0x2U) -#define SDIF_CTRL_FIFO_RESET_SHIFT (1U) -/*! FIFO_RESET - Fifo reset. - */ -#define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK) - -#define SDIF_CTRL_DMA_RESET_MASK (0x4U) -#define SDIF_CTRL_DMA_RESET_SHIFT (2U) -/*! DMA_RESET - DMA reset. - */ -#define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK) - -#define SDIF_CTRL_INT_ENABLE_MASK (0x10U) -#define SDIF_CTRL_INT_ENABLE_SHIFT (4U) -/*! INT_ENABLE - Global interrupt enable/disable bit. - */ -#define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK) - -#define SDIF_CTRL_READ_WAIT_MASK (0x40U) -#define SDIF_CTRL_READ_WAIT_SHIFT (6U) -/*! READ_WAIT - Read/wait. - */ -#define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK) - -#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U) -#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U) -/*! SEND_IRQ_RESPONSE - Send irq response. - */ -#define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK) - -#define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U) -#define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U) -/*! ABORT_READ_DATA - Abort read data. - */ -#define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK) - -#define SDIF_CTRL_SEND_CCSD_MASK (0x200U) -#define SDIF_CTRL_SEND_CCSD_SHIFT (9U) -/*! SEND_CCSD - Send ccsd. - */ -#define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK) - -#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U) -#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U) -/*! SEND_AUTO_STOP_CCSD - Send auto stop ccsd. - */ -#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK) - -#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U) -#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U) -/*! CEATA_DEVICE_INTERRUPT_STATUS - CEATA device interrupt status. - */ -#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK) - -#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U) -#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U) -/*! CARD_VOLTAGE_A0 - Controls the state of the SD_VOLT0 pin. - */ -#define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK) - -#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U) -#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U) -/*! CARD_VOLTAGE_A1 - Controls the state of the SD_VOLT1 pin. - */ -#define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK) - -#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U) -#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U) -/*! CARD_VOLTAGE_A2 - Controls the state of the SD_VOLT2 pin. - */ -#define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK) - -#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U) -#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U) -/*! USE_INTERNAL_DMAC - SD/MMC DMA use. - */ -#define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) -/*! @} */ - -/*! @name PWREN - Power Enable register */ -/*! @{ */ - -#define SDIF_PWREN_POWER_ENABLE0_MASK (0x1U) -#define SDIF_PWREN_POWER_ENABLE0_SHIFT (0U) -/*! POWER_ENABLE0 - Power on/off switch for card 0; once power is turned on, software should wait - * for regulator/switch ramp-up time before trying to initialize card 0. - */ -#define SDIF_PWREN_POWER_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE0_SHIFT)) & SDIF_PWREN_POWER_ENABLE0_MASK) - -#define SDIF_PWREN_POWER_ENABLE1_MASK (0x2U) -#define SDIF_PWREN_POWER_ENABLE1_SHIFT (1U) -/*! POWER_ENABLE1 - Power on/off switch for card 1; once power is turned on, software should wait - * for regulator/switch ramp-up time before trying to initialize card 1. - */ -#define SDIF_PWREN_POWER_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE1_SHIFT)) & SDIF_PWREN_POWER_ENABLE1_MASK) -/*! @} */ - -/*! @name CLKDIV - Clock Divider register */ -/*! @{ */ - -#define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU) -#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U) -/*! CLK_DIVIDER0 - Clock divider-0 value. - */ -#define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK) -/*! @} */ - -/*! @name CLKENA - Clock Enable register */ -/*! @{ */ - -#define SDIF_CLKENA_CCLK0_ENABLE_MASK (0x1U) -#define SDIF_CLKENA_CCLK0_ENABLE_SHIFT (0U) -/*! CCLK0_ENABLE - Clock-enable control for SD card 0 clock. - */ -#define SDIF_CLKENA_CCLK0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK0_ENABLE_MASK) - -#define SDIF_CLKENA_CCLK1_ENABLE_MASK (0x2U) -#define SDIF_CLKENA_CCLK1_ENABLE_SHIFT (1U) -/*! CCLK1_ENABLE - Clock-enable control for SD card 1 clock. - */ -#define SDIF_CLKENA_CCLK1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK1_ENABLE_MASK) - -#define SDIF_CLKENA_CCLK0_LOW_POWER_MASK (0x10000U) -#define SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT (16U) -/*! CCLK0_LOW_POWER - Low-power control for SD card 0 clock. - */ -#define SDIF_CLKENA_CCLK0_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK0_LOW_POWER_MASK) - -#define SDIF_CLKENA_CCLK1_LOW_POWER_MASK (0x20000U) -#define SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT (17U) -/*! CCLK1_LOW_POWER - Low-power control for SD card 1 clock. - */ -#define SDIF_CLKENA_CCLK1_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK1_LOW_POWER_MASK) -/*! @} */ - -/*! @name TMOUT - Time-out register */ -/*! @{ */ - -#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU) -#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U) -/*! RESPONSE_TIMEOUT - Response time-out value. - */ -#define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK) - -#define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U) -#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U) -/*! DATA_TIMEOUT - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. - */ -#define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK) -/*! @} */ - -/*! @name CTYPE - Card Type register */ -/*! @{ */ - -#define SDIF_CTYPE_CARD0_WIDTH0_MASK (0x1U) -#define SDIF_CTYPE_CARD0_WIDTH0_SHIFT (0U) -/*! CARD0_WIDTH0 - Indicates if card 0 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit - * modes only work when 8-bit mode in CARD0_WIDTH1 is not enabled (bit 16 in this register is set - * to 0). - */ -#define SDIF_CTYPE_CARD0_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH0_MASK) - -#define SDIF_CTYPE_CARD1_WIDTH0_MASK (0x2U) -#define SDIF_CTYPE_CARD1_WIDTH0_SHIFT (1U) -/*! CARD1_WIDTH0 - Indicates if card 1 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit - * modes only work when 8-bit mode in CARD1_WIDTH1 is not enabled (bit 16 in this register is set - * to 0). - */ -#define SDIF_CTYPE_CARD1_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH0_MASK) - -#define SDIF_CTYPE_CARD0_WIDTH1_MASK (0x10000U) -#define SDIF_CTYPE_CARD0_WIDTH1_SHIFT (16U) -/*! CARD0_WIDTH1 - Indicates if card 0 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. - */ -#define SDIF_CTYPE_CARD0_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH1_MASK) - -#define SDIF_CTYPE_CARD1_WIDTH1_MASK (0x20000U) -#define SDIF_CTYPE_CARD1_WIDTH1_SHIFT (17U) -/*! CARD1_WIDTH1 - Indicates if card 1 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. - */ -#define SDIF_CTYPE_CARD1_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH1_MASK) -/*! @} */ - -/*! @name BLKSIZ - Block Size register */ -/*! @{ */ - -#define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU) -#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U) -/*! BLOCK_SIZE - Block size. - */ -#define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK) -/*! @} */ - -/*! @name BYTCNT - Byte Count register */ -/*! @{ */ - -#define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU) -#define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U) -/*! BYTE_COUNT - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. - */ -#define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK) -/*! @} */ - -/*! @name INTMASK - Interrupt Mask register */ -/*! @{ */ - -#define SDIF_INTMASK_CDET_MASK (0x1U) -#define SDIF_INTMASK_CDET_SHIFT (0U) -/*! CDET - Card detect. - */ -#define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK) - -#define SDIF_INTMASK_RE_MASK (0x2U) -#define SDIF_INTMASK_RE_SHIFT (1U) -/*! RE - Response error. - */ -#define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK) - -#define SDIF_INTMASK_CDONE_MASK (0x4U) -#define SDIF_INTMASK_CDONE_SHIFT (2U) -/*! CDONE - Command done. - */ -#define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK) - -#define SDIF_INTMASK_DTO_MASK (0x8U) -#define SDIF_INTMASK_DTO_SHIFT (3U) -/*! DTO - Data transfer over. - */ -#define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK) - -#define SDIF_INTMASK_TXDR_MASK (0x10U) -#define SDIF_INTMASK_TXDR_SHIFT (4U) -/*! TXDR - Transmit FIFO data request. - */ -#define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK) - -#define SDIF_INTMASK_RXDR_MASK (0x20U) -#define SDIF_INTMASK_RXDR_SHIFT (5U) -/*! RXDR - Receive FIFO data request. - */ -#define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK) - -#define SDIF_INTMASK_RCRC_MASK (0x40U) -#define SDIF_INTMASK_RCRC_SHIFT (6U) -/*! RCRC - Response CRC error. - */ -#define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK) - -#define SDIF_INTMASK_DCRC_MASK (0x80U) -#define SDIF_INTMASK_DCRC_SHIFT (7U) -/*! DCRC - Data CRC error. - */ -#define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK) - -#define SDIF_INTMASK_RTO_MASK (0x100U) -#define SDIF_INTMASK_RTO_SHIFT (8U) -/*! RTO - Response time-out. - */ -#define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK) - -#define SDIF_INTMASK_DRTO_MASK (0x200U) -#define SDIF_INTMASK_DRTO_SHIFT (9U) -/*! DRTO - Data read time-out. - */ -#define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK) - -#define SDIF_INTMASK_HTO_MASK (0x400U) -#define SDIF_INTMASK_HTO_SHIFT (10U) -/*! HTO - Data starvation-by-host time-out (HTO). - */ -#define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK) - -#define SDIF_INTMASK_FRUN_MASK (0x800U) -#define SDIF_INTMASK_FRUN_SHIFT (11U) -/*! FRUN - FIFO underrun/overrun error. - */ -#define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK) - -#define SDIF_INTMASK_HLE_MASK (0x1000U) -#define SDIF_INTMASK_HLE_SHIFT (12U) -/*! HLE - Hardware locked write error. - */ -#define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK) - -#define SDIF_INTMASK_SBE_MASK (0x2000U) -#define SDIF_INTMASK_SBE_SHIFT (13U) -/*! SBE - Start-bit error. - */ -#define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK) - -#define SDIF_INTMASK_ACD_MASK (0x4000U) -#define SDIF_INTMASK_ACD_SHIFT (14U) -/*! ACD - Auto command done. - */ -#define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK) - -#define SDIF_INTMASK_EBE_MASK (0x8000U) -#define SDIF_INTMASK_EBE_SHIFT (15U) -/*! EBE - End-bit error (read)/Write no CRC. - */ -#define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK) - -#define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U) -#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U) -/*! SDIO_INT_MASK - Mask SDIO interrupt. - */ -#define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK) -/*! @} */ - -/*! @name CMDARG - Command Argument register */ -/*! @{ */ - -#define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU) -#define SDIF_CMDARG_CMD_ARG_SHIFT (0U) -/*! CMD_ARG - Value indicates command argument to be passed to card. - */ -#define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK) -/*! @} */ - -/*! @name CMD - Command register */ -/*! @{ */ - -#define SDIF_CMD_CMD_INDEX_MASK (0x3FU) -#define SDIF_CMD_CMD_INDEX_SHIFT (0U) -/*! CMD_INDEX - Command index. - */ -#define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK) - -#define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U) -#define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U) -/*! RESPONSE_EXPECT - Response expect. - */ -#define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK) - -#define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U) -#define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U) -/*! RESPONSE_LENGTH - Response length. - */ -#define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK) - -#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U) -#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U) -/*! CHECK_RESPONSE_CRC - Check response CRC. - */ -#define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK) - -#define SDIF_CMD_DATA_EXPECTED_MASK (0x200U) -#define SDIF_CMD_DATA_EXPECTED_SHIFT (9U) -/*! DATA_EXPECTED - Data expected. - */ -#define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK) - -#define SDIF_CMD_READ_WRITE_MASK (0x400U) -#define SDIF_CMD_READ_WRITE_SHIFT (10U) -/*! READ_WRITE - read/write. - */ -#define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK) - -#define SDIF_CMD_TRANSFER_MODE_MASK (0x800U) -#define SDIF_CMD_TRANSFER_MODE_SHIFT (11U) -/*! TRANSFER_MODE - Transfer mode. - */ -#define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK) - -#define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U) -#define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U) -/*! SEND_AUTO_STOP - Send auto stop. - */ -#define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK) - -#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U) -#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U) -/*! WAIT_PRVDATA_COMPLETE - Wait prvdata complete. - */ -#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK) - -#define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U) -#define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U) -/*! STOP_ABORT_CMD - Stop abort command. - */ -#define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK) - -#define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U) -#define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U) -/*! SEND_INITIALIZATION - Send initialization. - */ -#define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK) - -#define SDIF_CMD_CARD_NUMBER_MASK (0x1F0000U) -#define SDIF_CMD_CARD_NUMBER_SHIFT (16U) -/*! CARD_NUMBER - Specifies the card number of SDCARD for which the current Command is being executed - * 0b00000..Command will be execute on SDCARD 0 - * 0b00001..Command will be execute on SDCARD 1 - */ -#define SDIF_CMD_CARD_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CARD_NUMBER_SHIFT)) & SDIF_CMD_CARD_NUMBER_MASK) - -#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U) -#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U) -/*! UPDATE_CLOCK_REGISTERS_ONLY - Update clock registers only. - */ -#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK) - -#define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U) -#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U) -/*! READ_CEATA_DEVICE - Read ceata device. - */ -#define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK) - -#define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U) -#define SDIF_CMD_CCS_EXPECTED_SHIFT (23U) -/*! CCS_EXPECTED - CCS expected. - */ -#define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK) - -#define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U) -#define SDIF_CMD_ENABLE_BOOT_SHIFT (24U) -/*! ENABLE_BOOT - Enable Boot - this bit should be set only for mandatory boot mode. - */ -#define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK) - -#define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U) -#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U) -/*! EXPECT_BOOT_ACK - Expect Boot Acknowledge. - */ -#define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK) - -#define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U) -#define SDIF_CMD_DISABLE_BOOT_SHIFT (26U) -/*! DISABLE_BOOT - Disable Boot. - */ -#define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK) - -#define SDIF_CMD_BOOT_MODE_MASK (0x8000000U) -#define SDIF_CMD_BOOT_MODE_SHIFT (27U) -/*! BOOT_MODE - Boot Mode. - */ -#define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK) - -#define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U) -#define SDIF_CMD_VOLT_SWITCH_SHIFT (28U) -/*! VOLT_SWITCH - Voltage switch bit. - */ -#define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK) - -#define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U) -#define SDIF_CMD_USE_HOLD_REG_SHIFT (29U) -/*! USE_HOLD_REG - Use Hold Register. - */ -#define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK) - -#define SDIF_CMD_START_CMD_MASK (0x80000000U) -#define SDIF_CMD_START_CMD_SHIFT (31U) -/*! START_CMD - Start command. - */ -#define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK) -/*! @} */ - -/*! @name RESP - Response register */ -/*! @{ */ - -#define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU) -#define SDIF_RESP_RESPONSE_SHIFT (0U) -/*! RESPONSE - Bits of response. - */ -#define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK) -/*! @} */ - -/* The count of SDIF_RESP */ -#define SDIF_RESP_COUNT (4U) - -/*! @name MINTSTS - Masked Interrupt Status register */ -/*! @{ */ - -#define SDIF_MINTSTS_CDET_MASK (0x1U) -#define SDIF_MINTSTS_CDET_SHIFT (0U) -/*! CDET - Card detect. - */ -#define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK) - -#define SDIF_MINTSTS_RE_MASK (0x2U) -#define SDIF_MINTSTS_RE_SHIFT (1U) -/*! RE - Response error. - */ -#define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK) - -#define SDIF_MINTSTS_CDONE_MASK (0x4U) -#define SDIF_MINTSTS_CDONE_SHIFT (2U) -/*! CDONE - Command done. - */ -#define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK) - -#define SDIF_MINTSTS_DTO_MASK (0x8U) -#define SDIF_MINTSTS_DTO_SHIFT (3U) -/*! DTO - Data transfer over. - */ -#define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK) - -#define SDIF_MINTSTS_TXDR_MASK (0x10U) -#define SDIF_MINTSTS_TXDR_SHIFT (4U) -/*! TXDR - Transmit FIFO data request. - */ -#define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK) - -#define SDIF_MINTSTS_RXDR_MASK (0x20U) -#define SDIF_MINTSTS_RXDR_SHIFT (5U) -/*! RXDR - Receive FIFO data request. - */ -#define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK) - -#define SDIF_MINTSTS_RCRC_MASK (0x40U) -#define SDIF_MINTSTS_RCRC_SHIFT (6U) -/*! RCRC - Response CRC error. - */ -#define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK) - -#define SDIF_MINTSTS_DCRC_MASK (0x80U) -#define SDIF_MINTSTS_DCRC_SHIFT (7U) -/*! DCRC - Data CRC error. - */ -#define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK) - -#define SDIF_MINTSTS_RTO_MASK (0x100U) -#define SDIF_MINTSTS_RTO_SHIFT (8U) -/*! RTO - Response time-out. - */ -#define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK) - -#define SDIF_MINTSTS_DRTO_MASK (0x200U) -#define SDIF_MINTSTS_DRTO_SHIFT (9U) -/*! DRTO - Data read time-out. - */ -#define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK) - -#define SDIF_MINTSTS_HTO_MASK (0x400U) -#define SDIF_MINTSTS_HTO_SHIFT (10U) -/*! HTO - Data starvation-by-host time-out (HTO). - */ -#define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK) - -#define SDIF_MINTSTS_FRUN_MASK (0x800U) -#define SDIF_MINTSTS_FRUN_SHIFT (11U) -/*! FRUN - FIFO underrun/overrun error. - */ -#define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK) - -#define SDIF_MINTSTS_HLE_MASK (0x1000U) -#define SDIF_MINTSTS_HLE_SHIFT (12U) -/*! HLE - Hardware locked write error. - */ -#define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK) - -#define SDIF_MINTSTS_SBE_MASK (0x2000U) -#define SDIF_MINTSTS_SBE_SHIFT (13U) -/*! SBE - Start-bit error. - */ -#define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK) - -#define SDIF_MINTSTS_ACD_MASK (0x4000U) -#define SDIF_MINTSTS_ACD_SHIFT (14U) -/*! ACD - Auto command done. - */ -#define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK) - -#define SDIF_MINTSTS_EBE_MASK (0x8000U) -#define SDIF_MINTSTS_EBE_SHIFT (15U) -/*! EBE - End-bit error (read)/write no CRC. - */ -#define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK) - -#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U) -#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U) -/*! SDIO_INTERRUPT - Interrupt from SDIO card. - */ -#define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK) -/*! @} */ - -/*! @name RINTSTS - Raw Interrupt Status register */ -/*! @{ */ - -#define SDIF_RINTSTS_CDET_MASK (0x1U) -#define SDIF_RINTSTS_CDET_SHIFT (0U) -/*! CDET - Card detect. - */ -#define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK) - -#define SDIF_RINTSTS_RE_MASK (0x2U) -#define SDIF_RINTSTS_RE_SHIFT (1U) -/*! RE - Response error. - */ -#define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK) - -#define SDIF_RINTSTS_CDONE_MASK (0x4U) -#define SDIF_RINTSTS_CDONE_SHIFT (2U) -/*! CDONE - Command done. - */ -#define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK) - -#define SDIF_RINTSTS_DTO_MASK (0x8U) -#define SDIF_RINTSTS_DTO_SHIFT (3U) -/*! DTO - Data transfer over. - */ -#define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK) - -#define SDIF_RINTSTS_TXDR_MASK (0x10U) -#define SDIF_RINTSTS_TXDR_SHIFT (4U) -/*! TXDR - Transmit FIFO data request. - */ -#define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK) - -#define SDIF_RINTSTS_RXDR_MASK (0x20U) -#define SDIF_RINTSTS_RXDR_SHIFT (5U) -/*! RXDR - Receive FIFO data request. - */ -#define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK) - -#define SDIF_RINTSTS_RCRC_MASK (0x40U) -#define SDIF_RINTSTS_RCRC_SHIFT (6U) -/*! RCRC - Response CRC error. - */ -#define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK) - -#define SDIF_RINTSTS_DCRC_MASK (0x80U) -#define SDIF_RINTSTS_DCRC_SHIFT (7U) -/*! DCRC - Data CRC error. - */ -#define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK) - -#define SDIF_RINTSTS_RTO_BAR_MASK (0x100U) -#define SDIF_RINTSTS_RTO_BAR_SHIFT (8U) -/*! RTO_BAR - Response time-out (RTO)/Boot Ack Received (BAR). - */ -#define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK) - -#define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U) -#define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U) -/*! DRTO_BDS - Data read time-out (DRTO)/Boot Data Start (BDS). - */ -#define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK) - -#define SDIF_RINTSTS_HTO_MASK (0x400U) -#define SDIF_RINTSTS_HTO_SHIFT (10U) -/*! HTO - Data starvation-by-host time-out (HTO). - */ -#define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK) - -#define SDIF_RINTSTS_FRUN_MASK (0x800U) -#define SDIF_RINTSTS_FRUN_SHIFT (11U) -/*! FRUN - FIFO underrun/overrun error. - */ -#define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK) - -#define SDIF_RINTSTS_HLE_MASK (0x1000U) -#define SDIF_RINTSTS_HLE_SHIFT (12U) -/*! HLE - Hardware locked write error. - */ -#define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK) - -#define SDIF_RINTSTS_SBE_MASK (0x2000U) -#define SDIF_RINTSTS_SBE_SHIFT (13U) -/*! SBE - Start-bit error. - */ -#define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK) - -#define SDIF_RINTSTS_ACD_MASK (0x4000U) -#define SDIF_RINTSTS_ACD_SHIFT (14U) -/*! ACD - Auto command done. - */ -#define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK) - -#define SDIF_RINTSTS_EBE_MASK (0x8000U) -#define SDIF_RINTSTS_EBE_SHIFT (15U) -/*! EBE - End-bit error (read)/write no CRC. - */ -#define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK) - -#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U) -#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U) -/*! SDIO_INTERRUPT - Interrupt from SDIO card. - */ -#define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK) -/*! @} */ - -/*! @name STATUS - Status register */ -/*! @{ */ - -#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U) -#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U) -/*! FIFO_RX_WATERMARK - FIFO reached Receive watermark level; not qualified with data transfer. - */ -#define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK) - -#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U) -#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U) -/*! FIFO_TX_WATERMARK - FIFO reached Transmit watermark level; not qualified with data transfer. - */ -#define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK) - -#define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U) -#define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U) -/*! FIFO_EMPTY - FIFO is empty status. - */ -#define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK) - -#define SDIF_STATUS_FIFO_FULL_MASK (0x8U) -#define SDIF_STATUS_FIFO_FULL_SHIFT (3U) -/*! FIFO_FULL - FIFO is full status. - */ -#define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK) - -#define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U) -#define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U) -/*! CMDFSMSTATES - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx - * cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - - * Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp - * crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The - * command FSM state is represented using 19 bits. - */ -#define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK) - -#define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U) -#define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U) -/*! DATA_3_STATUS - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present. - */ -#define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK) - -#define SDIF_STATUS_DATA_BUSY_MASK (0x200U) -#define SDIF_STATUS_DATA_BUSY_SHIFT (9U) -/*! DATA_BUSY - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy. - */ -#define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK) - -#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U) -#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U) -/*! DATA_STATE_MC_BUSY - Data transmit or receive state-machine is busy. - */ -#define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK) - -#define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) -#define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U) -/*! RESPONSE_INDEX - Index of previous response, including any auto-stop sent by core. - */ -#define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK) - -#define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U) -#define SDIF_STATUS_FIFO_COUNT_SHIFT (17U) -/*! FIFO_COUNT - FIFO count - Number of filled locations in FIFO. - */ -#define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK) - -#define SDIF_STATUS_DMA_ACK_MASK (0x40000000U) -#define SDIF_STATUS_DMA_ACK_SHIFT (30U) -/*! DMA_ACK - DMA acknowledge signal state. - */ -#define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK) - -#define SDIF_STATUS_DMA_REQ_MASK (0x80000000U) -#define SDIF_STATUS_DMA_REQ_SHIFT (31U) -/*! DMA_REQ - DMA request signal state. - */ -#define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK) -/*! @} */ - -/*! @name FIFOTH - FIFO Threshold Watermark register */ -/*! @{ */ - -#define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU) -#define SDIF_FIFOTH_TX_WMARK_SHIFT (0U) -/*! TX_WMARK - FIFO threshold watermark level when transmitting data to card. - */ -#define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK) - -#define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U) -#define SDIF_FIFOTH_RX_WMARK_SHIFT (16U) -/*! RX_WMARK - FIFO threshold watermark level when receiving data to card. - */ -#define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK) - -#define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U) -#define SDIF_FIFOTH_DMA_MTS_SHIFT (28U) -/*! DMA_MTS - Burst size of multiple transaction; should be programmed same as DW-DMA controller - * multiple-transaction-size SRC/DEST_MSIZE. - */ -#define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK) -/*! @} */ - -/*! @name CDETECT - Card Detect register */ -/*! @{ */ - -#define SDIF_CDETECT_CARD0_DETECT_MASK (0x1U) -#define SDIF_CDETECT_CARD0_DETECT_SHIFT (0U) -/*! CARD0_DETECT - Card 0 detect - */ -#define SDIF_CDETECT_CARD0_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD0_DETECT_SHIFT)) & SDIF_CDETECT_CARD0_DETECT_MASK) - -#define SDIF_CDETECT_CARD1_DETECT_MASK (0x2U) -#define SDIF_CDETECT_CARD1_DETECT_SHIFT (1U) -/*! CARD1_DETECT - Card 1 detect - */ -#define SDIF_CDETECT_CARD1_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD1_DETECT_SHIFT)) & SDIF_CDETECT_CARD1_DETECT_MASK) -/*! @} */ - -/*! @name WRTPRT - Write Protect register */ -/*! @{ */ - -#define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U) -#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U) -/*! WRITE_PROTECT - Write protect. - */ -#define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK) -/*! @} */ - -/*! @name TCBCNT - Transferred CIU Card Byte Count register */ -/*! @{ */ - -#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU) -#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U) -/*! TRANS_CARD_BYTE_COUNT - Number of bytes transferred by CIU unit to card. - */ -#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK) -/*! @} */ - -/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */ -/*! @{ */ - -#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU) -#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U) -/*! TRANS_FIFO_BYTE_COUNT - Number of bytes transferred between Host/DMA memory and BIU FIFO. - */ -#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK) -/*! @} */ - -/*! @name DEBNCE - Debounce Count register */ -/*! @{ */ - -#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU) -#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U) -/*! DEBOUNCE_COUNT - Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms. - */ -#define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK) -/*! @} */ - -/*! @name RST_N - Hardware Reset */ -/*! @{ */ - -#define SDIF_RST_N_CARD_RESET_MASK (0x1U) -#define SDIF_RST_N_CARD_RESET_SHIFT (0U) -/*! CARD_RESET - Hardware reset. - */ -#define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK) -/*! @} */ - -/*! @name BMOD - Bus Mode register */ -/*! @{ */ - -#define SDIF_BMOD_SWR_MASK (0x1U) -#define SDIF_BMOD_SWR_SHIFT (0U) -/*! SWR - Software Reset. - */ -#define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK) - -#define SDIF_BMOD_FB_MASK (0x2U) -#define SDIF_BMOD_FB_SHIFT (1U) -/*! FB - Fixed Burst. - */ -#define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK) - -#define SDIF_BMOD_DSL_MASK (0x7CU) -#define SDIF_BMOD_DSL_SHIFT (2U) -/*! DSL - Descriptor Skip Length. - */ -#define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK) - -#define SDIF_BMOD_DE_MASK (0x80U) -#define SDIF_BMOD_DE_SHIFT (7U) -/*! DE - SD/MMC DMA Enable. - */ -#define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK) - -#define SDIF_BMOD_PBL_MASK (0x700U) -#define SDIF_BMOD_PBL_SHIFT (8U) -/*! PBL - Programmable Burst Length. - */ -#define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK) -/*! @} */ - -/*! @name PLDMND - Poll Demand register */ -/*! @{ */ - -#define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU) -#define SDIF_PLDMND_PD_SHIFT (0U) -/*! PD - Poll Demand. - */ -#define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK) -/*! @} */ - -/*! @name DBADDR - Descriptor List Base Address register */ -/*! @{ */ - -#define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU) -#define SDIF_DBADDR_SDL_SHIFT (0U) -/*! SDL - Start of Descriptor List. - */ -#define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK) -/*! @} */ - -/*! @name IDSTS - Internal DMAC Status register */ -/*! @{ */ - -#define SDIF_IDSTS_TI_MASK (0x1U) -#define SDIF_IDSTS_TI_SHIFT (0U) -/*! TI - Transmit Interrupt. - */ -#define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK) - -#define SDIF_IDSTS_RI_MASK (0x2U) -#define SDIF_IDSTS_RI_SHIFT (1U) -/*! RI - Receive Interrupt. - */ -#define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK) - -#define SDIF_IDSTS_FBE_MASK (0x4U) -#define SDIF_IDSTS_FBE_SHIFT (2U) -/*! FBE - Fatal Bus Error Interrupt. - */ -#define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK) - -#define SDIF_IDSTS_DU_MASK (0x10U) -#define SDIF_IDSTS_DU_SHIFT (4U) -/*! DU - Descriptor Unavailable Interrupt. - */ -#define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK) - -#define SDIF_IDSTS_CES_MASK (0x20U) -#define SDIF_IDSTS_CES_SHIFT (5U) -/*! CES - Card Error Summary. - */ -#define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK) - -#define SDIF_IDSTS_NIS_MASK (0x100U) -#define SDIF_IDSTS_NIS_SHIFT (8U) -/*! NIS - Normal Interrupt Summary. - */ -#define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK) - -#define SDIF_IDSTS_AIS_MASK (0x200U) -#define SDIF_IDSTS_AIS_SHIFT (9U) -/*! AIS - Abnormal Interrupt Summary. - */ -#define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK) - -#define SDIF_IDSTS_EB_MASK (0x1C00U) -#define SDIF_IDSTS_EB_SHIFT (10U) -/*! EB - Error Bits. - */ -#define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK) - -#define SDIF_IDSTS_FSM_MASK (0x1E000U) -#define SDIF_IDSTS_FSM_SHIFT (13U) -/*! FSM - DMAC state machine present state. - */ -#define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK) -/*! @} */ - -/*! @name IDINTEN - Internal DMAC Interrupt Enable register */ -/*! @{ */ - -#define SDIF_IDINTEN_TI_MASK (0x1U) -#define SDIF_IDINTEN_TI_SHIFT (0U) -/*! TI - Transmit Interrupt Enable. - */ -#define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK) - -#define SDIF_IDINTEN_RI_MASK (0x2U) -#define SDIF_IDINTEN_RI_SHIFT (1U) -/*! RI - Receive Interrupt Enable. - */ -#define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK) - -#define SDIF_IDINTEN_FBE_MASK (0x4U) -#define SDIF_IDINTEN_FBE_SHIFT (2U) -/*! FBE - Fatal Bus Error Enable. - */ -#define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK) - -#define SDIF_IDINTEN_DU_MASK (0x10U) -#define SDIF_IDINTEN_DU_SHIFT (4U) -/*! DU - Descriptor Unavailable Interrupt. - */ -#define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK) - -#define SDIF_IDINTEN_CES_MASK (0x20U) -#define SDIF_IDINTEN_CES_SHIFT (5U) -/*! CES - Card Error summary Interrupt Enable. - */ -#define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK) - -#define SDIF_IDINTEN_NIS_MASK (0x100U) -#define SDIF_IDINTEN_NIS_SHIFT (8U) -/*! NIS - Normal Interrupt Summary Enable. - */ -#define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK) - -#define SDIF_IDINTEN_AIS_MASK (0x200U) -#define SDIF_IDINTEN_AIS_SHIFT (9U) -/*! AIS - Abnormal Interrupt Summary Enable. - */ -#define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK) -/*! @} */ - -/*! @name DSCADDR - Current Host Descriptor Address register */ -/*! @{ */ - -#define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU) -#define SDIF_DSCADDR_HDA_SHIFT (0U) -/*! HDA - Host Descriptor Address Pointer. - */ -#define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK) -/*! @} */ - -/*! @name BUFADDR - Current Buffer Descriptor Address register */ -/*! @{ */ - -#define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU) -#define SDIF_BUFADDR_HBA_SHIFT (0U) -/*! HBA - Host Buffer Address Pointer. - */ -#define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK) -/*! @} */ - -/*! @name CARDTHRCTL - Card Threshold Control */ -/*! @{ */ - -#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U) -#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U) -/*! CARDRDTHREN - Card Read Threshold Enable. - */ -#define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK) - -#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U) -#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U) -/*! BSYCLRINTEN - Busy Clear Interrupt Enable. - */ -#define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK) - -#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U) -#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U) -/*! CARDTHRESHOLD - Card Threshold size. - */ -#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK) -/*! @} */ - -/*! @name BACKENDPWR - Power control */ -/*! @{ */ - -#define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U) -#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U) -/*! BACKENDPWR - Back-end Power control for card application. - */ -#define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK) -/*! @} */ - -/*! @name FIFO - SDIF FIFO */ -/*! @{ */ - -#define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU) -#define SDIF_FIFO_DATA_SHIFT (0U) -/*! DATA - SDIF FIFO. - */ -#define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK) -/*! @} */ - -/* The count of SDIF_FIFO */ -#define SDIF_FIFO_COUNT (64U) - - -/*! - * @} - */ /* end of group SDIF_Register_Masks */ - - -/* SDIF - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SDIF base address */ - #define SDIF_BASE (0x5009B000u) - /** Peripheral SDIF base address */ - #define SDIF_BASE_NS (0x4009B000u) - /** Peripheral SDIF base pointer */ - #define SDIF ((SDIF_Type *)SDIF_BASE) - /** Peripheral SDIF base pointer */ - #define SDIF_NS ((SDIF_Type *)SDIF_BASE_NS) - /** Array initializer of SDIF peripheral base addresses */ - #define SDIF_BASE_ADDRS { SDIF_BASE } - /** Array initializer of SDIF peripheral base pointers */ - #define SDIF_BASE_PTRS { SDIF } - /** Array initializer of SDIF peripheral base addresses */ - #define SDIF_BASE_ADDRS_NS { SDIF_BASE_NS } - /** Array initializer of SDIF peripheral base pointers */ - #define SDIF_BASE_PTRS_NS { SDIF_NS } -#else - /** Peripheral SDIF base address */ - #define SDIF_BASE (0x4009B000u) - /** Peripheral SDIF base pointer */ - #define SDIF ((SDIF_Type *)SDIF_BASE) - /** Array initializer of SDIF peripheral base addresses */ - #define SDIF_BASE_ADDRS { SDIF_BASE } - /** Array initializer of SDIF peripheral base pointers */ - #define SDIF_BASE_PTRS { SDIF } -#endif -/** Interrupt vectors for the SDIF peripheral type */ -#define SDIF_IRQS { SDIO_IRQn } - -/*! - * @} - */ /* end of group SDIF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer - * @{ - */ - -/** SPI - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[1024]; - __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ - __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ - __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ - __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ - __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ - __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ - uint8_t RESERVED_2[2516]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_6[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_7[4]; - __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ - uint8_t RESERVED_8[432]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} SPI_Type; - -/* ---------------------------------------------------------------------------- - -- SPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Register_Masks SPI Register Masks - * @{ - */ - -/*! @name CFG - SPI Configuration register */ -/*! @{ */ - -#define SPI_CFG_ENABLE_MASK (0x1U) -#define SPI_CFG_ENABLE_SHIFT (0U) -/*! ENABLE - SPI enable. - * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. - * 0b1..Enabled. The SPI is enabled for operation. - */ -#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) - -#define SPI_CFG_MASTER_MASK (0x4U) -#define SPI_CFG_MASTER_SHIFT (2U) -/*! MASTER - Master mode select. - * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. - * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. - */ -#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) - -#define SPI_CFG_LSBF_MASK (0x8U) -#define SPI_CFG_LSBF_SHIFT (3U) -/*! LSBF - LSB First mode enable. - * 0b0..Standard. Data is transmitted and received in standard MSB first order. - * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). - */ -#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) - -#define SPI_CFG_CPHA_MASK (0x10U) -#define SPI_CFG_CPHA_SHIFT (4U) -/*! CPHA - Clock Phase select. - * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock - * changes away from the rest state). Data is changed on the following edge. - * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock - * changes away from the rest state). Data is captured on the following edge. - */ -#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) - -#define SPI_CFG_CPOL_MASK (0x20U) -#define SPI_CFG_CPOL_SHIFT (5U) -/*! CPOL - Clock Polarity select. - * 0b0..Low. The rest state of the clock (between transfers) is low. - * 0b1..High. The rest state of the clock (between transfers) is high. - */ -#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) - -#define SPI_CFG_LOOP_MASK (0x80U) -#define SPI_CFG_LOOP_SHIFT (7U) -/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit - * and receive data connected together to allow simple software testing. - * 0b0..Disabled. - * 0b1..Enabled. - */ -#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) - -#define SPI_CFG_SPOL0_MASK (0x100U) -#define SPI_CFG_SPOL0_SHIFT (8U) -/*! SPOL0 - SSEL0 Polarity select. - * 0b0..Low. The SSEL0 pin is active low. - * 0b1..High. The SSEL0 pin is active high. - */ -#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) - -#define SPI_CFG_SPOL1_MASK (0x200U) -#define SPI_CFG_SPOL1_SHIFT (9U) -/*! SPOL1 - SSEL1 Polarity select. - * 0b0..Low. The SSEL1 pin is active low. - * 0b1..High. The SSEL1 pin is active high. - */ -#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) - -#define SPI_CFG_SPOL2_MASK (0x400U) -#define SPI_CFG_SPOL2_SHIFT (10U) -/*! SPOL2 - SSEL2 Polarity select. - * 0b0..Low. The SSEL2 pin is active low. - * 0b1..High. The SSEL2 pin is active high. - */ -#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) - -#define SPI_CFG_SPOL3_MASK (0x800U) -#define SPI_CFG_SPOL3_SHIFT (11U) -/*! SPOL3 - SSEL3 Polarity select. - * 0b0..Low. The SSEL3 pin is active low. - * 0b1..High. The SSEL3 pin is active high. - */ -#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) -/*! @} */ - -/*! @name DLY - SPI Delay register */ -/*! @{ */ - -#define SPI_DLY_PRE_DELAY_MASK (0xFU) -#define SPI_DLY_PRE_DELAY_SHIFT (0U) -/*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data - * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This - * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI - * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are - * inserted. - */ -#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) - -#define SPI_DLY_POST_DELAY_MASK (0xF0U) -#define SPI_DLY_POST_DELAY_SHIFT (4U) -/*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL - * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock - * times are inserted. 0xF = 15 SPI clock times are inserted. - */ -#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) - -#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) -#define SPI_DLY_FRAME_DELAY_SHIFT (8U) -/*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current - * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 - * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock - * times are inserted. - */ -#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) - -#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) -#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) -/*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between - * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 - * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that - * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 - * SPI clock times. - */ -#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) -/*! @} */ - -/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ -/*! @{ */ - -#define SPI_STAT_SSA_MASK (0x10U) -#define SPI_STAT_SSA_SHIFT (4U) -/*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from - * deasserted to asserted, in both master and slave modes. This allows determining when the SPI - * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a - * slave mode access begins. This flag is cleared by software. - */ -#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) - -#define SPI_STAT_SSD_MASK (0x20U) -#define SPI_STAT_SSD_SHIFT (5U) -/*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to - * deasserted, in both master and slave modes. This allows determining when the SPI - * transmit/receive functions become idle. This flag is cleared by software. - */ -#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) - -#define SPI_STAT_STALLED_MASK (0x40U) -#define SPI_STAT_STALLED_SHIFT (6U) -/*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition. - */ -#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) - -#define SPI_STAT_ENDTRANSFER_MASK (0x80U) -#define SPI_STAT_ENDTRANSFER_SHIFT (7U) -/*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current - * transfer when the transmitter finishes any activity already in progress, as if the EOT flag - * had been set prior to the last transmission. This capability is included to support cases where - * it is not known when transmit data is written that it will be the end of a transfer. The bit - * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end - * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. - */ -#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) - -#define SPI_STAT_MSTIDLE_MASK (0x100U) -#define SPI_STAT_MSTIDLE_SHIFT (8U) -/*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. - * This means that the transmit holding register is empty and the transmitter is not in the - * process of sending data. - */ -#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -/*! @{ */ - -#define SPI_INTENSET_SSAEN_MASK (0x10U) -#define SPI_INTENSET_SSAEN_SHIFT (4U) -/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. - * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. - * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. - */ -#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) - -#define SPI_INTENSET_SSDEN_MASK (0x20U) -#define SPI_INTENSET_SSDEN_SHIFT (5U) -/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. - * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. - * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. - */ -#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) - -#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) -#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) -/*! MSTIDLEEN - Master idle interrupt enable. - * 0b0..No interrupt will be generated when the SPI master function is idle. - * 0b1..An interrupt will be generated when the SPI master function is fully idle. - */ -#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) -/*! @} */ - -/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ -/*! @{ */ - -#define SPI_INTENCLR_SSAEN_MASK (0x10U) -#define SPI_INTENCLR_SSAEN_SHIFT (4U) -/*! SSAEN - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) - -#define SPI_INTENCLR_SSDEN_MASK (0x20U) -#define SPI_INTENCLR_SSDEN_SHIFT (5U) -/*! SSDEN - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) - -#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) -#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) -/*! MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) -/*! @} */ - -/*! @name DIV - SPI clock Divider */ -/*! @{ */ - -#define SPI_DIV_DIVVAL_MASK (0xFFFFU) -#define SPI_DIV_DIVVAL_SHIFT (0U) -/*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the - * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, - * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results - * in FCLK/65536. - */ -#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - SPI Interrupt Status */ -/*! @{ */ - -#define SPI_INTSTAT_SSA_MASK (0x10U) -#define SPI_INTSTAT_SSA_SHIFT (4U) -/*! SSA - Slave Select Assert. - */ -#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) - -#define SPI_INTSTAT_SSD_MASK (0x20U) -#define SPI_INTSTAT_SSD_SHIFT (5U) -/*! SSD - Slave Select Deassert. - */ -#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) - -#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) -#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) -/*! MSTIDLE - Master Idle status flag. - */ -#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ - -#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) -#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) - -#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) -#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) - -#define SPI_FIFOCFG_SIZE_MASK (0x30U) -#define SPI_FIFOCFG_SIZE_SHIFT (4U) -/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 - * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - */ -#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) - -#define SPI_FIFOCFG_DMATX_MASK (0x1000U) -#define SPI_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) - -#define SPI_FIFOCFG_DMARX_MASK (0x2000U) -#define SPI_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) - -#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) -#define SPI_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in - * FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) - -#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) -#define SPI_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in - * FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) - -#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) -/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - */ -#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) - -#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) -/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - */ -#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ - -#define SPI_FIFOSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow - * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is - * needed. Cleared by writing a 1 to this bit. - */ -#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) - -#define SPI_FIFOSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA - * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - */ -#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) - -#define SPI_FIFOSTAT_PERINT_MASK (0x8U) -#define SPI_FIFOSTAT_PERINT_SHIFT (3U) -/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted - * an interrupt. The details can be found by reading the peripheral's STAT register. - */ -#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) - -#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) -/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - */ -#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) - -#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) -/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be - * written. When 0, the transmit FIFO is full and another write would cause it to overflow. - */ -#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) - -#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - */ -#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) - -#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) -#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) -/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to - * prevent the peripheral from causing an overflow. - */ -#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) - -#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY - * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at - * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be - * 0. - */ -#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) - -#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and - * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the - * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be - * 1. - */ -#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ - -#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) - -#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) - -#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) -#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled - * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to - * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO - * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX - * FIFO level decreases to 15 entries (is no longer full). - */ -#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) - -#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data - * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level - * can wake up the device just enough to perform DMA, then return to the reduced power mode. See - * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no - * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX - * FIFO has received 16 entries (has become full). - */ -#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ - -#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) -#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) - -#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) -#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) - -#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases - * to the level specified by TXLVL in the FIFOTRIG register. - */ -#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) - -#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level - * increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ - -#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) -#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) -/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) - -#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) -#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) -/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) - -#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) -/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) - -#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) -/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ - -#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. - */ -#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) - -#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. - */ -#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) - -#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO level interrupt. - */ -#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) - -#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO level interrupt. - */ -#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) - -#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) -#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) -/*! PERINT - Peripheral interrupt. - */ -#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ - -#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) -#define SPI_FIFOWR_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit data to the FIFO. - */ -#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) - -#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) -#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) -/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL0 asserted. - * 0b1..SSEL0 not asserted. - */ -#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) - -#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) -#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) -/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL1 asserted. - * 0b1..SSEL1 not asserted. - */ -#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) - -#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) -#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) -/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL2 asserted. - * 0b1..SSEL2 not asserted. - */ -#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) - -#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) -#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) -/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL3 asserted. - * 0b1..SSEL3 not asserted. - */ -#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) - -#define SPI_FIFOWR_EOT_MASK (0x100000U) -#define SPI_FIFOWR_EOT_SHIFT (20U) -/*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain - * so far at least the time specified by the Transfer_delay value in the DLY register. - * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. - * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. - */ -#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) - -#define SPI_FIFOWR_EOF_MASK (0x200000U) -#define SPI_FIFOWR_EOF_SHIFT (21U) -/*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value - * in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay - * value = 0. This control can be used as part of the support for frame lengths greater than 16 - * bits. - * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame. - * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be - * inserted before subsequent data is transmitted. - */ -#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) - -#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) -#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) -/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to - * read unneeded data from the receiver. Setting this bit simplifies the transmit process and can - * be used with the DMA. - * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit - * will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data - * is not read before new data is received. - * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received - * data. No receiver flags are generated. - */ -#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) - -#define SPI_FIFOWR_LEN_MASK (0xF000000U) -#define SPI_FIFOWR_LEN_SHIFT (24U) -/*! LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths - * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. - * 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data - * transfer is 16 bits in length. - */ -#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ - -#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORD_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. - */ -#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) - -#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) -/*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved - * along with received data. The value will reflect the SSEL0 pin for both master and slave - * operation. A zero indicates that a slave select is active. The actual polarity of each slave select - * pin is configured by the related SPOL bit in CFG. - */ -#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) - -#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) -/*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved - * along with received data. The value will reflect the SSEL1 pin for both master and slave - * operation. A zero indicates that a slave select is active. The actual polarity of each slave select - * pin is configured by the related SPOL bit in CFG. - */ -#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) - -#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) -/*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved - * along with received data. The value will reflect the SSEL2 pin for both master and slave - * operation. A zero indicates that a slave select is active. The actual polarity of each slave select - * pin is configured by the related SPOL bit in CFG. - */ -#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) - -#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) -/*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved - * along with received data. The value will reflect the SSEL3 pin for both master and slave - * operation. A zero indicates that a slave select is active. The actual polarity of each slave select - * pin is configured by the related SPOL bit in CFG. - */ -#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) - -#define SPI_FIFORD_SOT_MASK (0x100000U) -#define SPI_FIFORD_SOT_SHIFT (20U) -/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went - * from deasserted to asserted (i.e., any previous transfer has ended). This information can be - * used to identify the first piece of data in cases where the transfer length is greater than 16 - * bits. - */ -#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ - -#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. - */ -#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) -/*! RXSSEL0_N - Slave Select for receive. - */ -#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) -/*! RXSSEL1_N - Slave Select for receive. - */ -#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) -/*! RXSSEL2_N - Slave Select for receive. - */ -#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) -/*! RXSSEL3_N - Slave Select for receive. - */ -#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) - -#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) -#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) -/*! SOT - Start of transfer flag. - */ -#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) -/*! @} */ - -/*! @name FIFOSIZE - FIFO size register */ -/*! @{ */ - -#define SPI_FIFOSIZE_FIFOSIZE_MASK (0x1FU) -#define SPI_FIFOSIZE_FIFOSIZE_SHIFT (0U) -/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - */ -#define SPI_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSIZE_FIFOSIZE_SHIFT)) & SPI_FIFOSIZE_FIFOSIZE_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ - -#define SPI_ID_APERTURE_MASK (0xFFU) -#define SPI_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - */ -#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) - -#define SPI_ID_MINOR_REV_MASK (0xF00U) -#define SPI_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation. - */ -#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) - -#define SPI_ID_MAJOR_REV_MASK (0xF000U) -#define SPI_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation. - */ -#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) - -#define SPI_ID_ID_MASK (0xFFFF0000U) -#define SPI_ID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function. - */ -#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SPI_Register_Masks */ - - -/* SPI - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SPI0 base address */ - #define SPI0_BASE (0x50086000u) - /** Peripheral SPI0 base address */ - #define SPI0_BASE_NS (0x40086000u) - /** Peripheral SPI0 base pointer */ - #define SPI0 ((SPI_Type *)SPI0_BASE) - /** Peripheral SPI0 base pointer */ - #define SPI0_NS ((SPI_Type *)SPI0_BASE_NS) - /** Peripheral SPI1 base address */ - #define SPI1_BASE (0x50087000u) - /** Peripheral SPI1 base address */ - #define SPI1_BASE_NS (0x40087000u) - /** Peripheral SPI1 base pointer */ - #define SPI1 ((SPI_Type *)SPI1_BASE) - /** Peripheral SPI1 base pointer */ - #define SPI1_NS ((SPI_Type *)SPI1_BASE_NS) - /** Peripheral SPI2 base address */ - #define SPI2_BASE (0x50088000u) - /** Peripheral SPI2 base address */ - #define SPI2_BASE_NS (0x40088000u) - /** Peripheral SPI2 base pointer */ - #define SPI2 ((SPI_Type *)SPI2_BASE) - /** Peripheral SPI2 base pointer */ - #define SPI2_NS ((SPI_Type *)SPI2_BASE_NS) - /** Peripheral SPI3 base address */ - #define SPI3_BASE (0x50089000u) - /** Peripheral SPI3 base address */ - #define SPI3_BASE_NS (0x40089000u) - /** Peripheral SPI3 base pointer */ - #define SPI3 ((SPI_Type *)SPI3_BASE) - /** Peripheral SPI3 base pointer */ - #define SPI3_NS ((SPI_Type *)SPI3_BASE_NS) - /** Peripheral SPI4 base address */ - #define SPI4_BASE (0x5008A000u) - /** Peripheral SPI4 base address */ - #define SPI4_BASE_NS (0x4008A000u) - /** Peripheral SPI4 base pointer */ - #define SPI4 ((SPI_Type *)SPI4_BASE) - /** Peripheral SPI4 base pointer */ - #define SPI4_NS ((SPI_Type *)SPI4_BASE_NS) - /** Peripheral SPI5 base address */ - #define SPI5_BASE (0x50096000u) - /** Peripheral SPI5 base address */ - #define SPI5_BASE_NS (0x40096000u) - /** Peripheral SPI5 base pointer */ - #define SPI5 ((SPI_Type *)SPI5_BASE) - /** Peripheral SPI5 base pointer */ - #define SPI5_NS ((SPI_Type *)SPI5_BASE_NS) - /** Peripheral SPI6 base address */ - #define SPI6_BASE (0x50097000u) - /** Peripheral SPI6 base address */ - #define SPI6_BASE_NS (0x40097000u) - /** Peripheral SPI6 base pointer */ - #define SPI6 ((SPI_Type *)SPI6_BASE) - /** Peripheral SPI6 base pointer */ - #define SPI6_NS ((SPI_Type *)SPI6_BASE_NS) - /** Peripheral SPI7 base address */ - #define SPI7_BASE (0x50098000u) - /** Peripheral SPI7 base address */ - #define SPI7_BASE_NS (0x40098000u) - /** Peripheral SPI7 base pointer */ - #define SPI7 ((SPI_Type *)SPI7_BASE) - /** Peripheral SPI7 base pointer */ - #define SPI7_NS ((SPI_Type *)SPI7_BASE_NS) - /** Peripheral SPI8 base address */ - #define SPI8_BASE (0x5009F000u) - /** Peripheral SPI8 base address */ - #define SPI8_BASE_NS (0x4009F000u) - /** Peripheral SPI8 base pointer */ - #define SPI8 ((SPI_Type *)SPI8_BASE) - /** Peripheral SPI8 base pointer */ - #define SPI8_NS ((SPI_Type *)SPI8_BASE_NS) - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS_NS { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS_NS { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS } -#else - /** Peripheral SPI0 base address */ - #define SPI0_BASE (0x40086000u) - /** Peripheral SPI0 base pointer */ - #define SPI0 ((SPI_Type *)SPI0_BASE) - /** Peripheral SPI1 base address */ - #define SPI1_BASE (0x40087000u) - /** Peripheral SPI1 base pointer */ - #define SPI1 ((SPI_Type *)SPI1_BASE) - /** Peripheral SPI2 base address */ - #define SPI2_BASE (0x40088000u) - /** Peripheral SPI2 base pointer */ - #define SPI2 ((SPI_Type *)SPI2_BASE) - /** Peripheral SPI3 base address */ - #define SPI3_BASE (0x40089000u) - /** Peripheral SPI3 base pointer */ - #define SPI3 ((SPI_Type *)SPI3_BASE) - /** Peripheral SPI4 base address */ - #define SPI4_BASE (0x4008A000u) - /** Peripheral SPI4 base pointer */ - #define SPI4 ((SPI_Type *)SPI4_BASE) - /** Peripheral SPI5 base address */ - #define SPI5_BASE (0x40096000u) - /** Peripheral SPI5 base pointer */ - #define SPI5 ((SPI_Type *)SPI5_BASE) - /** Peripheral SPI6 base address */ - #define SPI6_BASE (0x40097000u) - /** Peripheral SPI6 base pointer */ - #define SPI6 ((SPI_Type *)SPI6_BASE) - /** Peripheral SPI7 base address */ - #define SPI7_BASE (0x40098000u) - /** Peripheral SPI7 base pointer */ - #define SPI7 ((SPI_Type *)SPI7_BASE) - /** Peripheral SPI8 base address */ - #define SPI8_BASE (0x4009F000u) - /** Peripheral SPI8 base pointer */ - #define SPI8 ((SPI_Type *)SPI8_BASE) - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } -#endif -/** Interrupt vectors for the SPI peripheral type */ -#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } - -/*! - * @} - */ /* end of group SPI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SYSCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer - * @{ - */ - -/** SYSCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t MEMORYREMAP; /**< Memory Remap control register, offset: 0x0 */ - uint8_t RESERVED_0[12]; - __IO uint32_t AHBMATPRIO; /**< AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest, offset: 0x10 */ - uint8_t RESERVED_1[36]; - __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */ - __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */ - __IO uint32_t CPU1STCKCAL; /**< System tick calibration for CPU1, offset: 0x40 */ - uint8_t RESERVED_2[4]; - __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ - uint8_t RESERVED_3[180]; - union { /* offset: 0x100 */ - struct { /* offset: 0x100 */ - __IO uint32_t PRESETCTRL0; /**< Peripheral reset control 0, offset: 0x100 */ - __IO uint32_t PRESETCTRL1; /**< Peripheral reset control 1, offset: 0x104 */ - __IO uint32_t PRESETCTRL2; /**< Peripheral reset control 2, offset: 0x108 */ - } PRESETCTRL; - __IO uint32_t PRESETCTRLX[3]; /**< Peripheral reset control register, array offset: 0x100, array step: 0x4 */ - }; - uint8_t RESERVED_4[20]; - __IO uint32_t PRESETCTRLSET[3]; /**< Peripheral reset control set register, array offset: 0x120, array step: 0x4 */ - uint8_t RESERVED_5[20]; - __IO uint32_t PRESETCTRLCLR[3]; /**< Peripheral reset control clear register, array offset: 0x140, array step: 0x4 */ - uint8_t RESERVED_6[20]; - __O uint32_t SWR_RESET; /**< generate a software_reset, offset: 0x160 */ - uint8_t RESERVED_7[156]; - union { /* offset: 0x200 */ - struct { /* offset: 0x200 */ - __IO uint32_t AHBCLKCTRL0; /**< AHB Clock control 0, offset: 0x200 */ - __IO uint32_t AHBCLKCTRL1; /**< AHB Clock control 1, offset: 0x204 */ - __IO uint32_t AHBCLKCTRL2; /**< AHB Clock control 2, offset: 0x208 */ - } AHBCLKCTRL; - __IO uint32_t AHBCLKCTRLX[3]; /**< Peripheral reset control register, array offset: 0x200, array step: 0x4 */ - }; - uint8_t RESERVED_8[20]; - __IO uint32_t AHBCLKCTRLSET[3]; /**< Peripheral reset control register, array offset: 0x220, array step: 0x4 */ - uint8_t RESERVED_9[20]; - __IO uint32_t AHBCLKCTRLCLR[3]; /**< Peripheral reset control register, array offset: 0x240, array step: 0x4 */ - uint8_t RESERVED_10[20]; - union { /* offset: 0x260 */ - __IO uint32_t SYSTICKCLKSEL0; /**< System Tick Timer for CPU0 source select, offset: 0x260 */ - __IO uint32_t SYSTICKCLKSELX[1]; /**< Peripheral reset control register, array offset: 0x260, array step: 0x4 */ - }; - uint8_t RESERVED_11[4]; - __IO uint32_t TRACECLKSEL; /**< Trace clock source select, offset: 0x268 */ - union { /* offset: 0x26C */ - struct { /* offset: 0x26C */ - __IO uint32_t CTIMERCLKSEL0; /**< CTimer 0 clock source select, offset: 0x26C */ - __IO uint32_t CTIMERCLKSEL1; /**< CTimer 1 clock source select, offset: 0x270 */ - __IO uint32_t CTIMERCLKSEL2; /**< CTimer 2 clock source select, offset: 0x274 */ - __IO uint32_t CTIMERCLKSEL3; /**< CTimer 3 clock source select, offset: 0x278 */ - __IO uint32_t CTIMERCLKSEL4; /**< CTimer 4 clock source select, offset: 0x27C */ - } CTIMERCLKSEL; - __IO uint32_t CTIMERCLKSELX[5]; /**< Peripheral reset control register, array offset: 0x26C, array step: 0x4 */ - }; - __IO uint32_t MAINCLKSELA; /**< Main clock A source select, offset: 0x280 */ - __IO uint32_t MAINCLKSELB; /**< Main clock source select, offset: 0x284 */ - __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0x288 */ - uint8_t RESERVED_12[4]; - __IO uint32_t PLL0CLKSEL; /**< PLL0 clock source select, offset: 0x290 */ - __IO uint32_t PLL1CLKSEL; /**< PLL1 clock source select, offset: 0x294 */ - uint8_t RESERVED_13[12]; - __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ - __IO uint32_t USB0CLKSEL; /**< FS USB clock source select, offset: 0x2A8 */ - uint8_t RESERVED_14[4]; - union { /* offset: 0x2B0 */ - struct { /* offset: 0x2B0 */ - __IO uint32_t FCCLKSEL0; /**< Flexcomm Interface 0 clock source select for Fractional Rate Divider, offset: 0x2B0 */ - __IO uint32_t FCCLKSEL1; /**< Flexcomm Interface 1 clock source select for Fractional Rate Divider, offset: 0x2B4 */ - __IO uint32_t FCCLKSEL2; /**< Flexcomm Interface 2 clock source select for Fractional Rate Divider, offset: 0x2B8 */ - __IO uint32_t FCCLKSEL3; /**< Flexcomm Interface 3 clock source select for Fractional Rate Divider, offset: 0x2BC */ - __IO uint32_t FCCLKSEL4; /**< Flexcomm Interface 4 clock source select for Fractional Rate Divider, offset: 0x2C0 */ - __IO uint32_t FCCLKSEL5; /**< Flexcomm Interface 5 clock source select for Fractional Rate Divider, offset: 0x2C4 */ - __IO uint32_t FCCLKSEL6; /**< Flexcomm Interface 6 clock source select for Fractional Rate Divider, offset: 0x2C8 */ - __IO uint32_t FCCLKSEL7; /**< Flexcomm Interface 7 clock source select for Fractional Rate Divider, offset: 0x2CC */ - } FCCLKSEL; - __IO uint32_t FCCLKSELX[8]; /**< Peripheral reset control register, array offset: 0x2B0, array step: 0x4 */ - }; - __IO uint32_t HSLSPICLKSEL; /**< HS LSPI clock source select, offset: 0x2D0 */ - uint8_t RESERVED_15[12]; - __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ - uint8_t RESERVED_16[12]; - __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ - uint8_t RESERVED_17[4]; - __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */ - uint8_t RESERVED_18[4]; - __IO uint32_t SYSTICKCLKDIV0; /**< System Tick Timer divider for CPU0, offset: 0x300 */ - __IO uint32_t SYSTICKCLKDIV1; /**< System Tick Timer divider for CPU1, offset: 0x304 */ - __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */ - uint8_t RESERVED_19[20]; - union { /* offset: 0x320 */ - struct { /* offset: 0x320 */ - __IO uint32_t FLEXFRG0CTRL; /**< Fractional rate divider for flexcomm 0, offset: 0x320 */ - __IO uint32_t FLEXFRG1CTRL; /**< Fractional rate divider for flexcomm 1, offset: 0x324 */ - __IO uint32_t FLEXFRG2CTRL; /**< Fractional rate divider for flexcomm 2, offset: 0x328 */ - __IO uint32_t FLEXFRG3CTRL; /**< Fractional rate divider for flexcomm 3, offset: 0x32C */ - __IO uint32_t FLEXFRG4CTRL; /**< Fractional rate divider for flexcomm 4, offset: 0x330 */ - __IO uint32_t FLEXFRG5CTRL; /**< Fractional rate divider for flexcomm 5, offset: 0x334 */ - __IO uint32_t FLEXFRG6CTRL; /**< Fractional rate divider for flexcomm 6, offset: 0x338 */ - __IO uint32_t FLEXFRG7CTRL; /**< Fractional rate divider for flexcomm 7, offset: 0x33C */ - } FLEXFRGCTRL; - __IO uint32_t FLEXFRGXCTRL[8]; /**< Peripheral reset control register, array offset: 0x320, array step: 0x4 */ - }; - uint8_t RESERVED_20[64]; - __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */ - __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ - __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */ - __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */ - uint8_t RESERVED_21[4]; - __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ - __IO uint32_t USB0CLKDIV; /**< USB0 Clock divider, offset: 0x398 */ - uint8_t RESERVED_22[16]; - __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ - uint8_t RESERVED_23[4]; - __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ - uint8_t RESERVED_24[4]; - __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */ - uint8_t RESERVED_25[4]; - __IO uint32_t PLL0CLKDIV; /**< PLL0 clock divider, offset: 0x3C4 */ - uint8_t RESERVED_26[52]; - __IO uint32_t CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */ - __IO uint32_t FMCCR; /**< FMC configuration register, offset: 0x400 */ - uint8_t RESERVED_27[8]; - __IO uint32_t USB0NEEDCLKCTRL; /**< USB0 need clock control, offset: 0x40C */ - __I uint32_t USB0NEEDCLKSTAT; /**< USB0 need clock status, offset: 0x410 */ - uint8_t RESERVED_28[8]; - __O uint32_t FMCFLUSH; /**< FMCflush control, offset: 0x41C */ - __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */ - __IO uint32_t USB1NEEDCLKCTRL; /**< USB1 need clock control, offset: 0x424 */ - __I uint32_t USB1NEEDCLKSTAT; /**< USB1 need clock status, offset: 0x428 */ - uint8_t RESERVED_29[52]; - __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */ - uint8_t RESERVED_30[252]; - __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */ - __I uint32_t PLL1STAT; /**< PLL1 550m status, offset: 0x564 */ - __IO uint32_t PLL1NDEC; /**< PLL1 550m N divider, offset: 0x568 */ - __IO uint32_t PLL1MDEC; /**< PLL1 550m M divider, offset: 0x56C */ - __IO uint32_t PLL1PDEC; /**< PLL1 550m P divider, offset: 0x570 */ - uint8_t RESERVED_31[12]; - __IO uint32_t PLL0CTRL; /**< PLL0 550m control, offset: 0x580 */ - __I uint32_t PLL0STAT; /**< PLL0 550m status, offset: 0x584 */ - __IO uint32_t PLL0NDEC; /**< PLL0 550m N divider, offset: 0x588 */ - __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */ - __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */ - __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */ - uint8_t RESERVED_32[364]; - __IO uint32_t FUNCRETENTIONCTRL; /**< Functional retention control register, offset: 0x704 */ - uint8_t RESERVED_33[248]; - __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ - __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ - uint8_t RESERVED_34[4]; - __I uint32_t CPSTAT; /**< CPU Status, offset: 0x80C */ - uint8_t RESERVED_35[520]; - __IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures, offset: 0xA18 */ - uint8_t RESERVED_36[244]; - __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */ - __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */ - uint8_t RESERVED_37[748]; - __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */ - __IO uint32_t GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */ - uint8_t RESERVED_38[404]; - __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers., offset: 0xFA0 */ - __IO uint32_t DEBUG_FEATURES; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control., offset: 0xFA4 */ - __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register., offset: 0xFA8 */ - uint8_t RESERVED_39[16]; - __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index., offset: 0xFBC */ - __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug authentication BEACON register, offset: 0xFC0 */ - uint8_t RESERVED_40[52]; - __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ - __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */ -} SYSCON_Type; - -/* ---------------------------------------------------------------------------- - -- SYSCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Register_Masks SYSCON Register Masks - * @{ - */ - -/*! @name MEMORYREMAP - Memory Remap control register */ -/*! @{ */ - -#define SYSCON_MEMORYREMAP_MAP_MASK (0x3U) -#define SYSCON_MEMORYREMAP_MAP_SHIFT (0U) -/*! MAP - Select the location of the vector table :. - * 0b00..Vector Table in ROM. - * 0b01..Vector Table in RAM. - * 0b10..Vector Table in Flash. - * 0b11..Vector Table in Flash. - */ -#define SYSCON_MEMORYREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK) -/*! @} */ - -/*! @name AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest */ -/*! @{ */ - -#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK (0x3U) -#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT (0U) -/*! PRI_CPU0_CBUS - CPU0 C-AHB bus. - */ -#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK (0xCU) -#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT (2U) -/*! PRI_CPU0_SBUS - CPU0 S-AHB bus. - */ -#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK (0x30U) -#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT (4U) -/*! PRI_CPU1_CBUS - CPU1 C-AHB bus. - */ -#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK (0xC0U) -#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT (6U) -/*! PRI_CPU1_SBUS - CPU1 S-AHB bus. - */ -#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_USB_FS_MASK (0x300U) -#define SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT (8U) -/*! PRI_USB_FS - USB-FS.(USB0) - */ -#define SYSCON_AHBMATPRIO_PRI_USB_FS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0xC00U) -#define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (10U) -/*! PRI_SDMA0 - DMA0 controller priority. - */ -#define SYSCON_AHBMATPRIO_PRI_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK) - -#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0x30000U) -#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (16U) -/*! PRI_SDIO - SDIO. - */ -#define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK) - -#define SYSCON_AHBMATPRIO_PRI_PQ_MASK (0xC0000U) -#define SYSCON_AHBMATPRIO_PRI_PQ_SHIFT (18U) -/*! PRI_PQ - PQ (HW Accelerator). - */ -#define SYSCON_AHBMATPRIO_PRI_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PQ_MASK) - -#define SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK (0x300000U) -#define SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT (20U) -/*! PRI_HASH_AES - HASH_AES. - */ -#define SYSCON_AHBMATPRIO_PRI_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT)) & SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK) - -#define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK (0xC00000U) -#define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT (22U) -/*! PRI_USB_HS - USB-HS.(USB1) - */ -#define SYSCON_AHBMATPRIO_PRI_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0x3000000U) -#define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (24U) -/*! PRI_SDMA1 - DMA1 controller priority. - */ -#define SYSCON_AHBMATPRIO_PRI_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK) -/*! @} */ - -/*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */ -/*! @{ */ - -#define SYSCON_CPU0STCKCAL_TENMS_MASK (0xFFFFFFU) -#define SYSCON_CPU0STCKCAL_TENMS_SHIFT (0U) -/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value - * reads as zero, the calibration value is not known. - */ -#define SYSCON_CPU0STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK) - -#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) -/*! SKEW - Initial value for the Systick timer. - */ -#define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) - -#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) -/*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference - * clock provided; 1 = no reference clock provided. - */ -#define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */ -/*! @{ */ - -#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) -#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) -/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the - * value reads as zero, the calibration value is not known. - */ -#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) - -#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) -/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. - */ -#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) - -#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) -/*! NOREF - Initial value for the Systick timer. - */ -#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name CPU1STCKCAL - System tick calibration for CPU1 */ -/*! @{ */ - -#define SYSCON_CPU1STCKCAL_TENMS_MASK (0xFFFFFFU) -#define SYSCON_CPU1STCKCAL_TENMS_SHIFT (0U) -/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value - * reads as zero, the calibration value is not known. - */ -#define SYSCON_CPU1STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_TENMS_SHIFT)) & SYSCON_CPU1STCKCAL_TENMS_MASK) - -#define SYSCON_CPU1STCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU1STCKCAL_SKEW_SHIFT (24U) -/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. - */ -#define SYSCON_CPU1STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_SKEW_SHIFT)) & SYSCON_CPU1STCKCAL_SKEW_MASK) - -#define SYSCON_CPU1STCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU1STCKCAL_NOREF_SHIFT (25U) -/*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference - * clock provided; 1 = no reference clock provided. - */ -#define SYSCON_CPU1STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_NOREF_SHIFT)) & SYSCON_CPU1STCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name NMISRC - NMI Source Select */ -/*! @{ */ - -#define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU) -#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) -/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0. - */ -#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) - -#define SYSCON_NMISRC_IRQCPU1_MASK (0x3F00U) -#define SYSCON_NMISRC_IRQCPU1_SHIFT (8U) -/*! IRQCPU1 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1, if enabled by NMIENCPU1. - */ -#define SYSCON_NMISRC_IRQCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU1_SHIFT)) & SYSCON_NMISRC_IRQCPU1_MASK) - -#define SYSCON_NMISRC_NMIENCPU1_MASK (0x40000000U) -#define SYSCON_NMISRC_NMIENCPU1_SHIFT (30U) -/*! NMIENCPU1 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU1. - */ -#define SYSCON_NMISRC_NMIENCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU1_SHIFT)) & SYSCON_NMISRC_NMIENCPU1_MASK) - -#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) -#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) -/*! NMIENCPU0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. - */ -#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) -/*! @} */ - -/*! @name PRESETCTRL0 - Peripheral reset control 0 */ -/*! @{ */ - -#define SYSCON_PRESETCTRL0_ROM_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL0_ROM_RST_SHIFT (1U) -/*! ROM_RST - ROM reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_ROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ROM_RST_SHIFT)) & SYSCON_PRESETCTRL0_ROM_RST_MASK) - -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U) -/*! SRAM_CTRL1_RST - SRAM Controller 1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK) - -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U) -/*! SRAM_CTRL2_RST - SRAM Controller 2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK) - -#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK (0x20U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT (5U) -/*! SRAM_CTRL3_RST - SRAM Controller 3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK) - -#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK (0x40U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT (6U) -/*! SRAM_CTRL4_RST - SRAM Controller 4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK) - -#define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U) -/*! FLASH_RST - Flash controller reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK) - -#define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U) -/*! FMC_RST - FMC controller reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK) - -#define SYSCON_PRESETCTRL0_MUX_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL0_MUX_RST_SHIFT (11U) -/*! MUX_RST - Input Mux reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK) - -#define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U) -/*! IOCON_RST - I/O controller reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK) - -#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U) -/*! GPIO0_RST - GPIO0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) - -#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U) -/*! GPIO1_RST - GPIO1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) - -#define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (16U) -/*! GPIO2_RST - GPIO2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK) - -#define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (17U) -/*! GPIO3_RST - GPIO3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK) - -#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U) -/*! PINT_RST - Pin interrupt (PINT) reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) - -#define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U) -/*! GINT_RST - Group interrupt (GINT) reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK) - -#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U) -#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U) -/*! DMA0_RST - DMA0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) - -#define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U) -#define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U) -/*! CRCGEN_RST - CRCGEN reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_CRCGEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK) - -#define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U) -/*! WWDT_RST - Watchdog Timer reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK) - -#define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U) -#define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U) -/*! RTC_RST - Real Time Clock (RTC) reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK) - -#define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U) -#define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U) -/*! MAILBOX_RST - Inter CPU communication Mailbox reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK) - -#define SYSCON_PRESETCTRL0_ADC_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL0_ADC_RST_SHIFT (27U) -/*! ADC_RST - ADC reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_ADC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRL1 - Peripheral reset control 1 */ -/*! @{ */ - -#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) -#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) -/*! MRT_RST - MRT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) - -#define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT (1U) -/*! OSTIMER_RST - OS Event Timer reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_OSTIMER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK) - -#define SYSCON_PRESETCTRL1_SCT_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL1_SCT_RST_SHIFT (2U) -/*! SCT_RST - SCT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_SCT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT_RST_MASK) - -#define SYSCON_PRESETCTRL1_SCTIPU_RST_MASK (0x40U) -#define SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT (6U) -/*! SCTIPU_RST - SCTIPU reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_SCTIPU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCTIPU_RST_MASK) - -#define SYSCON_PRESETCTRL1_UTICK_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT (10U) -/*! UTICK_RST - UTICK reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) -/*! FC0_RST - FC0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) -#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) -/*! FC1_RST - FC1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) -/*! FC2_RST - FC2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) -/*! FC3_RST - FC3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) -/*! FC4_RST - FC4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) -/*! FC5_RST - FC5 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) -/*! FC6_RST - FC6 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) -/*! FC7_RST - FC7 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) - -#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) -/*! TIMER2_RST - Timer 2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) - -#define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK (0x2000000U) -#define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT (25U) -/*! USB0_DEV_RST - USB0 DEV reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_USB0_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK) - -#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) -#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) -/*! TIMER0_RST - Timer 0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) - -#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) -/*! TIMER1_RST - Timer 1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRL2 - Peripheral reset control 2 */ -/*! @{ */ - -#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) -/*! DMA1_RST - DMA1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) - -#define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U) -/*! COMP_RST - Comparator reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_COMP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK) - -#define SYSCON_PRESETCTRL2_SDIO_RST_MASK (0x8U) -#define SYSCON_PRESETCTRL2_SDIO_RST_SHIFT (3U) -/*! SDIO_RST - SDIO reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_SDIO_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK (0x10U) -#define SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT (4U) -/*! USB1_HOST_RST - USB1 Host reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_HOST_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK (0x20U) -#define SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT (5U) -/*! USB1_DEV_RST - USB1 dev reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK (0x40U) -#define SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT (6U) -/*! USB1_RAM_RST - USB1 RAM reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT (7U) -/*! USB1_PHY_RST - USB1 PHY reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK) - -#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) -/*! FREQME_RST - Frequency meter reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) - -#define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U) -/*! RNG_RST - RNG reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK) - -#define SYSCON_PRESETCTRL2_SYSCTL_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT (15U) -/*! SYSCTL_RST - SYSCTL Block reset. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_SYSCTL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT)) & SYSCON_PRESETCTRL2_SYSCTL_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT (16U) -/*! USB0_HOSTM_RST - USB0 Host Master reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT (17U) -/*! USB0_HOSTS_RST - USB0 Host Slave reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK) - -#define SYSCON_PRESETCTRL2_HASH_AES_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT (18U) -/*! HASH_AES_RST - HASH_AES reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_HASH_AES_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH_AES_RST_MASK) - -#define SYSCON_PRESETCTRL2_PQ_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL2_PQ_RST_SHIFT (19U) -/*! PQ_RST - Power Quad reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_PQ_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK) - -#define SYSCON_PRESETCTRL2_PLULUT_RST_MASK (0x100000U) -#define SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT (20U) -/*! PLULUT_RST - PLU LUT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_PLULUT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLULUT_RST_MASK) - -#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) -#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) -/*! TIMER3_RST - Timer 3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) - -#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) -/*! TIMER4_RST - Timer 4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) - -#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) -#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) -/*! PUF_RST - PUF reset control reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) - -#define SYSCON_PRESETCTRL2_CASPER_RST_MASK (0x1000000U) -#define SYSCON_PRESETCTRL2_CASPER_RST_SHIFT (24U) -/*! CASPER_RST - Casper reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_CASPER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CASPER_RST_SHIFT)) & SYSCON_PRESETCTRL2_CASPER_RST_MASK) - -#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT (27U) -/*! ANALOG_CTRL_RST - analog control reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK) - -#define SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK (0x10000000U) -#define SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT (28U) -/*! HS_LSPI_RST - HS LSPI reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_HS_LSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK) - -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U) -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U) -/*! GPIO_SEC_RST - GPIO secure reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK) - -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U) -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U) -/*! GPIO_SEC_INT_RST - GPIO secure int reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRLX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_PRESETCTRLX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_PRESETCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLX_DATA_SHIFT)) & SYSCON_PRESETCTRLX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLX */ -#define SYSCON_PRESETCTRLX_COUNT (3U) - -/*! @name PRESETCTRLSET - Peripheral reset control set register */ -/*! @{ */ - -#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLSET */ -#define SYSCON_PRESETCTRLSET_COUNT (3U) - -/*! @name PRESETCTRLCLR - Peripheral reset control clear register */ -/*! @{ */ - -#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLCLR */ -#define SYSCON_PRESETCTRLCLR_COUNT (3U) - -/*! @name SWR_RESET - generate a software_reset */ -/*! @{ */ - -#define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU) -#define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U) -/*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset. - * 0b01011010000000000000000000000001..Generate a software reset. - * 0b00000000000000000000000000000000..Bloc is not reset. - */ -#define SYSCON_SWR_RESET_SWR_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL0 - AHB Clock control 0 */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) -#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) -/*! ROM - Enables the clock for the ROM. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) - -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U) -/*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK) - -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U) -/*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK) - -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK (0x20U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT (5U) -/*! SRAM_CTRL3 - Enables the clock for the SRAM Controller 3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK) - -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK (0x40U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT (6U) -/*! SRAM_CTRL4 - Enables the clock for the SRAM Controller 4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK) - -#define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U) -#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U) -/*! FLASH - Enables the clock for the Flash controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK) - -#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U) -#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U) -/*! FMC - Enables the clock for the FMC controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) - -#define SYSCON_AHBCLKCTRL0_MUX_MASK (0x800U) -#define SYSCON_AHBCLKCTRL0_MUX_SHIFT (11U) -/*! MUX - Enables the clock for the Input Mux. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_MUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK) - -#define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U) -/*! IOCON - Enables the clock for the I/O controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK) - -#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U) -/*! GPIO0 - Enables the clock for the GPIO0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) - -#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U) -/*! GPIO1 - Enables the clock for the GPIO1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) - -#define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (16U) -/*! GPIO2 - Enables the clock for the GPIO2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK) - -#define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (17U) -/*! GPIO3 - Enables the clock for the GPIO3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK) - -#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U) -/*! PINT - Enables the clock for the Pin interrupt (PINT). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) - -#define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U) -/*! GINT - Enables the clock for the Group interrupt (GINT). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK) - -#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U) -#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U) -/*! DMA0 - Enables the clock for the DMA0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) - -#define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U) -#define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U) -/*! CRCGEN - Enables the clock for the CRCGEN. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK) - -#define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U) -/*! WWDT - Enables the clock for the Watchdog Timer. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK) - -#define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U) -#define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U) -/*! RTC - Enables the clock for the Real Time Clock (RTC). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK) - -#define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U) -/*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK) - -#define SYSCON_AHBCLKCTRL0_ADC_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL0_ADC_SHIFT (27U) -/*! ADC - Enables the clock for the ADC. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL1 - AHB Clock control 1 */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) -#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) -/*! MRT - Enables the clock for the MRT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) - -#define SYSCON_AHBCLKCTRL1_OSTIMER_MASK (0x2U) -#define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT (1U) -/*! OSTIMER - Enables the clock for the OS Event Timer. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK) - -#define SYSCON_AHBCLKCTRL1_SCT_MASK (0x4U) -#define SYSCON_AHBCLKCTRL1_SCT_SHIFT (2U) -/*! SCT - Enables the clock for the SCT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_SCT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT_MASK) - -#define SYSCON_AHBCLKCTRL1_UTICK_MASK (0x400U) -#define SYSCON_AHBCLKCTRL1_UTICK_SHIFT (10U) -/*! UTICK - Enables the clock for the UTICK. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK) - -#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) -#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) -/*! FC0 - Enables the clock for the FC0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) - -#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) -#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) -/*! FC1 - Enables the clock for the FC1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) - -#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) -/*! FC2 - Enables the clock for the FC2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) - -#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) -/*! FC3 - Enables the clock for the FC3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) - -#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) -/*! FC4 - Enables the clock for the FC4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) - -#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) -/*! FC5 - Enables the clock for the FC5. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) - -#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) -/*! FC6 - Enables the clock for the FC6. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) - -#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) -/*! FC7 - Enables the clock for the FC7. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) - -#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) -/*! TIMER2 - Enables the clock for the Timer 2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) - -#define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK (0x2000000U) -#define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT (25U) -/*! USB0_DEV - Enables the clock for the USB0 DEV. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_USB0_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK) - -#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) -/*! TIMER0 - Enables the clock for the Timer 0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) - -#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) -/*! TIMER1 - Enables the clock for the Timer 1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL2 - AHB Clock control 2 */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) -#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) -/*! DMA1 - Enables the clock for the DMA1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) - -#define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U) -#define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U) -/*! COMP - Enables the clock for the Comparator. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK) - -#define SYSCON_AHBCLKCTRL2_SDIO_MASK (0x8U) -#define SYSCON_AHBCLKCTRL2_SDIO_SHIFT (3U) -/*! SDIO - Enables the clock for the SDIO. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL2_SDIO_MASK) - -#define SYSCON_AHBCLKCTRL2_USB1_HOST_MASK (0x10U) -#define SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT (4U) -/*! USB1_HOST - Enables the clock for the USB1 Host. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_HOST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_HOST_MASK) - -#define SYSCON_AHBCLKCTRL2_USB1_DEV_MASK (0x20U) -#define SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT (5U) -/*! USB1_DEV - Enables the clock for the USB1 dev. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_DEV_MASK) - -#define SYSCON_AHBCLKCTRL2_USB1_RAM_MASK (0x40U) -#define SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT (6U) -/*! USB1_RAM - Enables the clock for the USB1 RAM. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_RAM_MASK) - -#define SYSCON_AHBCLKCTRL2_USB1_PHY_MASK (0x80U) -#define SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT (7U) -/*! USB1_PHY - Enables the clock for the USB1 PHY. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_PHY_MASK) - -#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) -#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) -/*! FREQME - Enables the clock for the Frequency meter. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) - -#define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U) -/*! RNG - Enables the clock for the RNG. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK) - -#define SYSCON_AHBCLKCTRL2_SYSCTL_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT (15U) -/*! SYSCTL - SYSCTL block clock. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_SYSCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT)) & SYSCON_AHBCLKCTRL2_SYSCTL_MASK) - -#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT (16U) -/*! USB0_HOSTM - Enables the clock for the USB0 Host Master. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK) - -#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT (17U) -/*! USB0_HOSTS - Enables the clock for the USB0 Host Slave. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK) - -#define SYSCON_AHBCLKCTRL2_HASH_AES_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT (18U) -/*! HASH_AES - Enables the clock for the HASH_AES. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH_AES_MASK) - -#define SYSCON_AHBCLKCTRL2_PQ_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL2_PQ_SHIFT (19U) -/*! PQ - Enables the clock for the Power Quad. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK) - -#define SYSCON_AHBCLKCTRL2_PLULUT_MASK (0x100000U) -#define SYSCON_AHBCLKCTRL2_PLULUT_SHIFT (20U) -/*! PLULUT - Enables the clock for the PLU LUT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PLULUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLULUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLULUT_MASK) - -#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) -#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) -/*! TIMER3 - Enables the clock for the Timer 3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) - -#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) -/*! TIMER4 - Enables the clock for the Timer 4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) - -#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) -#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) -/*! PUF - Enables the clock for the PUF reset control. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) - -#define SYSCON_AHBCLKCTRL2_CASPER_MASK (0x1000000U) -#define SYSCON_AHBCLKCTRL2_CASPER_SHIFT (24U) -/*! CASPER - Enables the clock for the Casper. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CASPER_SHIFT)) & SYSCON_AHBCLKCTRL2_CASPER_MASK) - -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U) -/*! ANALOG_CTRL - Enables the clock for the analog control. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK) - -#define SYSCON_AHBCLKCTRL2_HS_LSPI_MASK (0x10000000U) -#define SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT (28U) -/*! HS_LSPI - Enables the clock for the HS LSPI. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_LSPI_MASK) - -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U) -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U) -/*! GPIO_SEC - Enables the clock for the GPIO secure. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK) - -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U) -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U) -/*! GPIO_SEC_INT - Enables the clock for the GPIO secure int. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK) -/*! @} */ - -/*! @name AHBCLKCTRLX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRLX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_AHBCLKCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLX_DATA_SHIFT)) & SYSCON_AHBCLKCTRLX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLX */ -#define SYSCON_AHBCLKCTRLX_COUNT (3U) - -/*! @name AHBCLKCTRLSET - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLSET */ -#define SYSCON_AHBCLKCTRLSET_COUNT (3U) - -/*! @name AHBCLKCTRLCLR - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLCLR */ -#define SYSCON_AHBCLKCTRLCLR_COUNT (3U) - -/*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) -/*! SEL - System Tick Timer for CPU0 source select. - * 0b000..System Tick 0 divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKSELX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKSELX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_SYSTICKCLKSELX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_SYSTICKCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSELX_DATA_SHIFT)) & SYSCON_SYSTICKCLKSELX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_SYSTICKCLKSELX */ -#define SYSCON_SYSTICKCLKSELX_COUNT (1U) - -/*! @name TRACECLKSEL - Trace clock source select */ -/*! @{ */ - -#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) -#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) -/*! SEL - Trace clock source select. - * 0b000..Trace divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL0 - CTimer 0 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL0_SEL_SHIFT (0U) -/*! SEL - CTimer 0 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL0_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL1 - CTimer 1 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL1_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL1_SEL_SHIFT (0U) -/*! SEL - CTimer 1 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL1_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL1_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL2 - CTimer 2 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL2_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL2_SEL_SHIFT (0U) -/*! SEL - CTimer 2 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL2_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL2_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL3 - CTimer 3 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL3_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL3_SEL_SHIFT (0U) -/*! SEL - CTimer 3 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL3_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL3_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL4 - CTimer 4 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL4_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL4_SEL_SHIFT (0U) -/*! SEL - CTimer 4 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL4_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL4_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSELX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSELX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_CTIMERCLKSELX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_CTIMERCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSELX_DATA_SHIFT)) & SYSCON_CTIMERCLKSELX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_CTIMERCLKSELX */ -#define SYSCON_CTIMERCLKSELX_COUNT (5U) - -/*! @name MAINCLKSELA - Main clock A source select */ -/*! @{ */ - -#define SYSCON_MAINCLKSELA_SEL_MASK (0x7U) -#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) -/*! SEL - Main clock A source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..Reserved. - * 0b101..Reserved. - * 0b110..Reserved. - * 0b111..Reserved. - */ -#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) -/*! @} */ - -/*! @name MAINCLKSELB - Main clock source select */ -/*! @{ */ - -#define SYSCON_MAINCLKSELB_SEL_MASK (0x7U) -#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) -/*! SEL - Main clock source select. - * 0b000..Main Clock A. - * 0b001..PLL0 clock. - * 0b010..PLL1 clock. - * 0b011..Oscillator 32 kHz clock. - * 0b100..Reserved. - * 0b101..Reserved. - * 0b110..Reserved. - * 0b111..Reserved. - */ -#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) -/*! @} */ - -/*! @name CLKOUTSEL - CLKOUT clock source select */ -/*! @{ */ - -#define SYSCON_CLKOUTSEL_SEL_MASK (0x7U) -#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) -/*! SEL - CLKOUT clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..CLKIN clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..PLL1 clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) -/*! @} */ - -/*! @name PLL0CLKSEL - PLL0 clock source select */ -/*! @{ */ - -#define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U) -#define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U) -/*! SEL - PLL0 clock source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..Oscillator 32kHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_PLL0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name PLL1CLKSEL - PLL1 clock source select */ -/*! @{ */ - -#define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U) -#define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U) -/*! SEL - PLL1 clock source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..Oscillator 32kHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_PLL1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name ADCCLKSEL - ADC clock source select */ -/*! @{ */ - -#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) -#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) -/*! SEL - ADC clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..FRO 96 MHz clock. - * 0b011..Reserved. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name USB0CLKSEL - FS USB clock source select */ -/*! @{ */ - -#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) -#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) -/*! SEL - FS USB clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..PLL1 clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL0_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL0_SEL_SHIFT)) & SYSCON_FCCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL1_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL1_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL1_SEL_SHIFT)) & SYSCON_FCCLKSEL1_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL2_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL2_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL2_SEL_SHIFT)) & SYSCON_FCCLKSEL2_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL3_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL3_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL3_SEL_SHIFT)) & SYSCON_FCCLKSEL3_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL4_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL4_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL4_SEL_SHIFT)) & SYSCON_FCCLKSEL4_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL5_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL5_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL5_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL5_SEL_SHIFT)) & SYSCON_FCCLKSEL5_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL6_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL6_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL6_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL6_SEL_SHIFT)) & SYSCON_FCCLKSEL6_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL7_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL7_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL7_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL7_SEL_SHIFT)) & SYSCON_FCCLKSEL7_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSELX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_FCCLKSELX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_FCCLKSELX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_FCCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSELX_DATA_SHIFT)) & SYSCON_FCCLKSELX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_FCCLKSELX */ -#define SYSCON_FCCLKSELX_COUNT (8U) - -/*! @name HSLSPICLKSEL - HS LSPI clock source select */ -/*! @{ */ - -#define SYSCON_HSLSPICLKSEL_SEL_MASK (0x7U) -#define SYSCON_HSLSPICLKSEL_SEL_SHIFT (0U) -/*! SEL - HS LSPI clock source select. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..No clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_HSLSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HSLSPICLKSEL_SEL_SHIFT)) & SYSCON_HSLSPICLKSEL_SEL_MASK) -/*! @} */ - -/*! @name MCLKCLKSEL - MCLK clock source select */ -/*! @{ */ - -#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) -#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) -/*! SEL - MCLK clock source select. - * 0b000..FRO 96 MHz clock. - * 0b001..PLL0 clock. - * 0b010..Reserved. - * 0b011..Reserved. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SCTCLKSEL - SCTimer/PWM clock source select */ -/*! @{ */ - -#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) -#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) -/*! SEL - SCTimer/PWM clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..CLKIN clock. - * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..MCLK clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SDIOCLKSEL - SDIO clock source select */ -/*! @{ */ - -#define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U) -#define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U) -/*! SEL - SDIO clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..PLL1 clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKDIV0_DIV_MASK (0xFFU) -#define SYSCON_SYSTICKCLKDIV0_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_SYSTICKCLKDIV0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV0_DIV_MASK) - -#define SYSCON_SYSTICKCLKDIV0_RESET_MASK (0x20000000U) -#define SYSCON_SYSTICKCLKDIV0_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SYSTICKCLKDIV0_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV0_RESET_MASK) - -#define SYSCON_SYSTICKCLKDIV0_HALT_MASK (0x40000000U) -#define SYSCON_SYSTICKCLKDIV0_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SYSTICKCLKDIV0_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV0_HALT_MASK) - -#define SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK (0x80000000U) -#define SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SYSTICKCLKDIV0_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK) -/*! @} */ - -/*! @name SYSTICKCLKDIV1 - System Tick Timer divider for CPU1 */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKDIV1_DIV_MASK (0xFFU) -#define SYSCON_SYSTICKCLKDIV1_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_SYSTICKCLKDIV1_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV1_DIV_MASK) - -#define SYSCON_SYSTICKCLKDIV1_RESET_MASK (0x20000000U) -#define SYSCON_SYSTICKCLKDIV1_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SYSTICKCLKDIV1_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV1_RESET_MASK) - -#define SYSCON_SYSTICKCLKDIV1_HALT_MASK (0x40000000U) -#define SYSCON_SYSTICKCLKDIV1_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SYSTICKCLKDIV1_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV1_HALT_MASK) - -#define SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK (0x80000000U) -#define SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SYSTICKCLKDIV1_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK) -/*! @} */ - -/*! @name TRACECLKDIV - TRACE clock divider */ -/*! @{ */ - -#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) -#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) - -#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) - -#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) - -#define SYSCON_TRACECLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_TRACECLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_TRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_TRACECLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 */ -/*! @{ */ - -#define SYSCON_FLEXFRG0CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG0CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG0CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG0CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG0CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG0CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG0CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG0CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 */ -/*! @{ */ - -#define SYSCON_FLEXFRG1CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG1CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG1CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG1CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG1CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG1CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG1CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG1CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 */ -/*! @{ */ - -#define SYSCON_FLEXFRG2CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG2CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG2CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG2CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG2CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG2CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG2CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG2CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 */ -/*! @{ */ - -#define SYSCON_FLEXFRG3CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG3CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG3CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG3CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG3CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG3CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG3CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG3CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 */ -/*! @{ */ - -#define SYSCON_FLEXFRG4CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG4CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG4CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG4CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG4CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG4CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG4CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG4CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 */ -/*! @{ */ - -#define SYSCON_FLEXFRG5CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG5CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG5CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG5CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG5CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG5CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG5CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG5CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 */ -/*! @{ */ - -#define SYSCON_FLEXFRG6CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG6CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG6CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG6CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG6CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG6CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG6CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG6CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 */ -/*! @{ */ - -#define SYSCON_FLEXFRG7CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG7CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG7CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG7CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG7CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG7CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG7CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG7CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRGXCTRL - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_FLEXFRGXCTRL_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_FLEXFRGXCTRL_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_FLEXFRGXCTRL_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRGXCTRL_DATA_SHIFT)) & SYSCON_FLEXFRGXCTRL_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_FLEXFRGXCTRL */ -#define SYSCON_FLEXFRGXCTRL_COUNT (8U) - -/*! @name AHBCLKDIV - System clock divider */ -/*! @{ */ - -#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) - -#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) - -#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) - -#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name CLKOUTDIV - CLKOUT clock divider */ -/*! @{ */ - -#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) -#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) - -#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) -#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) - -#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) -#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) - -#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name FROHFDIV - FRO_HF (96MHz) clock divider */ -/*! @{ */ - -#define SYSCON_FROHFDIV_DIV_MASK (0xFFU) -#define SYSCON_FROHFDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) - -#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U) -#define SYSCON_FROHFDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK) - -#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) -#define SYSCON_FROHFDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) - -#define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_FROHFDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name WDTCLKDIV - WDT clock divider */ -/*! @{ */ - -#define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU) -#define SYSCON_WDTCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_WDTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK) - -#define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_WDTCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_WDTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK) - -#define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_WDTCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_WDTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK) - -#define SYSCON_WDTCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_WDTCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_WDTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_REQFLAG_SHIFT)) & SYSCON_WDTCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name ADCCLKDIV - ADC clock divider */ -/*! @{ */ - -#define SYSCON_ADCCLKDIV_DIV_MASK (0x7U) -#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) - -#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) - -#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) - -#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name USB0CLKDIV - USB0 Clock divider */ -/*! @{ */ - -#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) -#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) - -#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) - -#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) - -#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name MCLKDIV - I2S MCLK clock divider */ -/*! @{ */ - -#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_MCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) - -#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_MCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) - -#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_MCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) - -#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name SCTCLKDIV - SCT/PWM clock divider */ -/*! @{ */ - -#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) - -#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) - -#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) - -#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name SDIOCLKDIV - SDIO clock divider */ -/*! @{ */ - -#define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK) - -#define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK) - -#define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK) - -#define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name PLL0CLKDIV - PLL0 clock divider */ -/*! @{ */ - -#define SYSCON_PLL0CLKDIV_DIV_MASK (0xFFU) -#define SYSCON_PLL0CLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_PLL0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_DIV_SHIFT)) & SYSCON_PLL0CLKDIV_DIV_MASK) - -#define SYSCON_PLL0CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_PLL0CLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_PLL0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_RESET_SHIFT)) & SYSCON_PLL0CLKDIV_RESET_MASK) - -#define SYSCON_PLL0CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_PLL0CLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_PLL0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_HALT_SHIFT)) & SYSCON_PLL0CLKDIV_HALT_MASK) - -#define SYSCON_PLL0CLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_PLL0CLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_PLL0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_REQFLAG_SHIFT)) & SYSCON_PLL0CLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) */ -/*! @{ */ - -#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK (0xFFFFFFFFU) -#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT (0U) -/*! CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL). - * 0b00000000000000000000000000000001..update all clock configuration. - * 0b00000000000000000000000000000000..all hardware clock configruration are freeze. - */ -#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK) -/*! @} */ - -/*! @name FMCCR - FMC configuration register */ -/*! @{ */ - -#define SYSCON_FMCCR_FETCHCFG_MASK (0x3U) -#define SYSCON_FMCCR_FETCHCFG_SHIFT (0U) -/*! FETCHCFG - Instruction fetch configuration. - * 0b00..Instruction fetches from flash are not buffered. - * 0b01..One buffer is used for all instruction fetches. - * 0b10..All buffers may be used for instruction fetches. - */ -#define SYSCON_FMCCR_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCFG_SHIFT)) & SYSCON_FMCCR_FETCHCFG_MASK) - -#define SYSCON_FMCCR_DATACFG_MASK (0xCU) -#define SYSCON_FMCCR_DATACFG_SHIFT (2U) -/*! DATACFG - Data read configuration. - * 0b00..Data accesses from flash are not buffered. - * 0b01..One buffer is used for all data accesses. - * 0b10..All buffers can be used for data accesses. - */ -#define SYSCON_FMCCR_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACFG_SHIFT)) & SYSCON_FMCCR_DATACFG_MASK) - -#define SYSCON_FMCCR_ACCEL_MASK (0x10U) -#define SYSCON_FMCCR_ACCEL_SHIFT (4U) -/*! ACCEL - Acceleration enable. - * 0b0..Flash acceleration is disabled. - * 0b1..Flash acceleration is enabled. - */ -#define SYSCON_FMCCR_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK) - -#define SYSCON_FMCCR_PREFEN_MASK (0x20U) -#define SYSCON_FMCCR_PREFEN_SHIFT (5U) -/*! PREFEN - Prefetch enable. - * 0b0..No instruction prefetch is performed. - * 0b1..Instruction prefetch is enabled. - */ -#define SYSCON_FMCCR_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK) - -#define SYSCON_FMCCR_PREFOVR_MASK (0x40U) -#define SYSCON_FMCCR_PREFOVR_SHIFT (6U) -/*! PREFOVR - Prefetch override. - * 0b0..Any previously initiated prefetch will be completed. - * 0b1..Any previously initiated prefetch will be aborted, and the next flash line following the current - * execution address will be prefetched if not already buffered. - */ -#define SYSCON_FMCCR_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK) - -#define SYSCON_FMCCR_FLASHTIM_MASK (0xF000U) -#define SYSCON_FMCCR_FLASHTIM_SHIFT (12U) -/*! FLASHTIM - Flash memory access time. - * 0b0000..1 system clock flash access time (for system clock rates up to 11 MHz). - * 0b0001..2 system clocks flash access time (for system clock rates up to 22 MHz). - * 0b0010..3 system clocks flash access time (for system clock rates up to 33 MHz). - * 0b0011..4 system clocks flash access time (for system clock rates up to 44 MHz). - * 0b0100..5 system clocks flash access time (for system clock rates up to 55 MHz). - * 0b0101..6 system clocks flash access time (for system clock rates up to 66 MHz). - * 0b0110..7 system clocks flash access time (for system clock rates up to 77 MHz). - * 0b0111..8 system clocks flash access time (for system clock rates up to 88 MHz). - * 0b1000..9 system clocks flash access time (for system clock rates up to 100 MHz). - * 0b1001..10 system clocks flash access time (for system clock rates up to 115 MHz). - * 0b1010..11 system clocks flash access time (for system clock rates up to 130 MHz). - * 0b1011..12 system clocks flash access time (for system clock rates up to 150 MHz). - */ -#define SYSCON_FMCCR_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FLASHTIM_SHIFT)) & SYSCON_FMCCR_FLASHTIM_MASK) -/*! @} */ - -/*! @name USB0NEEDCLKCTRL - USB0 need clock control */ -/*! @{ */ - -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK (0x1U) -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT (0U) -/*! AP_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. - */ -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK) - -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK (0x2U) -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT (1U) -/*! POL_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. - * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. - * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK) - -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK (0x4U) -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT (2U) -/*! AP_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. - */ -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK) - -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK (0x8U) -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT (3U) -/*! POL_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. - * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. - * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK) -/*! @} */ - -/*! @name USB0NEEDCLKSTAT - USB0 need clock status */ -/*! @{ */ - -#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) -#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) -/*! DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal status:. - * 0b1..USB0 Device clock is high. - * 0b0..USB0 Device clock is low. - */ -#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK) - -#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) -#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) -/*! HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal status:. - * 0b1..USB0 Host clock is high. - * 0b0..USB0 Host clock is low. - */ -#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK) -/*! @} */ - -/*! @name FMCFLUSH - FMCflush control */ -/*! @{ */ - -#define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U) -#define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U) -/*! FLUSH - Flush control - * 0b1..Flush the FMC buffer contents. - * 0b0..No action is performed. - */ -#define SYSCON_FMCFLUSH_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK) -/*! @} */ - -/*! @name MCLKIO - MCLK control */ -/*! @{ */ - -#define SYSCON_MCLKIO_MCLKIO_MASK (0x1U) -#define SYSCON_MCLKIO_MCLKIO_SHIFT (0U) -/*! MCLKIO - MCLK control. - * 0b0..input mode. - * 0b1..output mode. - */ -#define SYSCON_MCLKIO_MCLKIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK) -/*! @} */ - -/*! @name USB1NEEDCLKCTRL - USB1 need clock control */ -/*! @{ */ - -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK (0x1U) -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT (0U) -/*! AP_HS_DEV_NEEDCLK - USB1 Device need_clock signal control: - * 0b0..HOST_NEEDCLK is under hardware control. - * 0b1..HOST_NEEDCLK is forced high. - */ -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK) - -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK (0x2U) -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT (1U) -/*! POL_HS_DEV_NEEDCLK - USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt: - * 0b0..Falling edge of DEV_NEEDCLK triggers wake-up. - * 0b1..Rising edge of DEV_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK) - -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK (0x4U) -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT (2U) -/*! AP_HS_HOST_NEEDCLK - USB1 Host need clock signal control: - * 0b0..HOST_NEEDCLK is under hardware control. - * 0b1..HOST_NEEDCLK is forced high. - */ -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK) - -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK (0x8U) -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT (3U) -/*! POL_HS_HOST_NEEDCLK - USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. - * 0b0..Falling edge of HOST_NEEDCLK triggers wake-up. - * 0b1..Rising edge of HOST_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK) - -#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U) -#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U) -/*! HS_DEV_WAKEUP_N - Software override of device controller PHY wake up logic. - * 0b0..Forces USB1_PHY to wake-up. - * 0b1..Normal USB1_PHY behavior. - */ -#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK) -/*! @} */ - -/*! @name USB1NEEDCLKSTAT - USB1 need clock status */ -/*! @{ */ - -#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) -#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) -/*! DEV_NEEDCLK - USB1 Device need_clock signal status:. - * 0b1..DEV_NEEDCLK is high. - * 0b0..DEV_NEEDCLK is low. - */ -#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK) - -#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) -#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) -/*! HOST_NEEDCLK - USB1 Host need_clock signal status:. - * 0b1..HOST_NEEDCLK is high. - * 0b0..HOST_NEEDCLK is low. - */ -#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK) -/*! @} */ - -/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */ -/*! @{ */ - -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U) -/*! CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in. - * 0b00..0 degree shift. - * 0b01..90 degree shift. - * 0b10..180 degree shift. - * 0b11..270 degree shift. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK) - -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U) -/*! CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. - * 0b00..0 degree shift. - * 0b01..90 degree shift. - * 0b10..180 degree shift. - * 0b11..270 degree shift. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK) - -#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) -#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U) -/*! PHASE_ACTIVE - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE. - * 0b0..Bypassed. - * 0b1..Activates phase shift logic. When active, the clock divider is active and phase delays are enabled. - */ -#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK) - -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U) -/*! CCLK_DRV_DELAY - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK) - -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U) -/*! CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field. - * 0b1..Enable drive delay. - * 0b0..Disable drive delay. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK) - -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U) -/*! CCLK_SAMPLE_DELAY - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK) - -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U) -/*! CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. - * 0b1..Enables sample delay. - * 0b0..Disables sample delay. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK) -/*! @} */ - -/*! @name PLL1CTRL - PLL1 550m control */ -/*! @{ */ - -#define SYSCON_PLL1CTRL_SELR_MASK (0xFU) -#define SYSCON_PLL1CTRL_SELR_SHIFT (0U) -/*! SELR - Bandwidth select R value. - */ -#define SYSCON_PLL1CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK) - -#define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U) -#define SYSCON_PLL1CTRL_SELI_SHIFT (4U) -/*! SELI - Bandwidth select I value. - */ -#define SYSCON_PLL1CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK) - -#define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U) -#define SYSCON_PLL1CTRL_SELP_SHIFT (10U) -/*! SELP - Bandwidth select P value. - */ -#define SYSCON_PLL1CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U) -#define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U) -/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - * 0b1..PLL input clock is sent directly to the PLL output. - * 0b0..use PLL. - */ -#define SYSCON_PLL1CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U) -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U) -/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - * 0b1..bypass of the divide-by-2 divider in the post-divider. - * 0b0..use the divide-by-2 divider in the post-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) - -#define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U) -#define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U) -/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. - */ -#define SYSCON_PLL1CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK) - -#define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U) -#define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U) -/*! BWDIRECT - control of the bandwidth of the PLL. - * 0b1..modify the bandwidth of the PLL directly. - * 0b0..the bandwidth is changed synchronously with the feedback-divider. - */ -#define SYSCON_PLL1CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U) -#define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U) -/*! BYPASSPREDIV - bypass of the pre-divider. - * 0b1..bypass of the pre-divider. - * 0b0..use the pre-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U) -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U) -/*! BYPASSPOSTDIV - bypass of the post-divider. - * 0b1..bypass of the post-divider. - * 0b0..use the post-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) - -#define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U) -#define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U) -/*! CLKEN - enable the output clock. - * 0b1..Enable the output clock. - * 0b0..Disable the output clock. - */ -#define SYSCON_PLL1CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK) - -#define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U) -#define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U) -/*! FRMEN - 1: free running mode. - */ -#define SYSCON_PLL1CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK) - -#define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U) -#define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U) -/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable. - */ -#define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK) - -#define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U) -#define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U) -/*! SKEWEN - Skew mode. - * 0b1..skewmode is enable. - * 0b0..skewmode is disable. - */ -#define SYSCON_PLL1CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK) -/*! @} */ - -/*! @name PLL1STAT - PLL1 550m status */ -/*! @{ */ - -#define SYSCON_PLL1STAT_LOCK_MASK (0x1U) -#define SYSCON_PLL1STAT_LOCK_SHIFT (0U) -/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. - */ -#define SYSCON_PLL1STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK) - -#define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U) -#define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U) -/*! PREDIVACK - pre-divider ratio change acknowledge. - */ -#define SYSCON_PLL1STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK) - -#define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U) -#define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U) -/*! FEEDDIVACK - feedback divider ratio change acknowledge. - */ -#define SYSCON_PLL1STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK) - -#define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U) -#define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U) -/*! POSTDIVACK - post-divider ratio change acknowledge. - */ -#define SYSCON_PLL1STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK) - -#define SYSCON_PLL1STAT_FRMDET_MASK (0x10U) -#define SYSCON_PLL1STAT_FRMDET_SHIFT (4U) -/*! FRMDET - free running detector output (active high). - */ -#define SYSCON_PLL1STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK) -/*! @} */ - -/*! @name PLL1NDEC - PLL1 550m N divider */ -/*! @{ */ - -#define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU) -#define SYSCON_PLL1NDEC_NDIV_SHIFT (0U) -/*! NDIV - pre-divider divider ratio (N-divider). - */ -#define SYSCON_PLL1NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK) - -#define SYSCON_PLL1NDEC_NREQ_MASK (0x100U) -#define SYSCON_PLL1NDEC_NREQ_SHIFT (8U) -/*! NREQ - pre-divider ratio change request. - */ -#define SYSCON_PLL1NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK) -/*! @} */ - -/*! @name PLL1MDEC - PLL1 550m M divider */ -/*! @{ */ - -#define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU) -#define SYSCON_PLL1MDEC_MDIV_SHIFT (0U) -/*! MDIV - feedback divider divider ratio (M-divider). - */ -#define SYSCON_PLL1MDEC_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK) - -#define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U) -#define SYSCON_PLL1MDEC_MREQ_SHIFT (16U) -/*! MREQ - feedback ratio change request. - */ -#define SYSCON_PLL1MDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK) -/*! @} */ - -/*! @name PLL1PDEC - PLL1 550m P divider */ -/*! @{ */ - -#define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU) -#define SYSCON_PLL1PDEC_PDIV_SHIFT (0U) -/*! PDIV - post-divider divider ratio (P-divider) - */ -#define SYSCON_PLL1PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK) - -#define SYSCON_PLL1PDEC_PREQ_MASK (0x20U) -#define SYSCON_PLL1PDEC_PREQ_SHIFT (5U) -/*! PREQ - feedback ratio change request. - */ -#define SYSCON_PLL1PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK) -/*! @} */ - -/*! @name PLL0CTRL - PLL0 550m control */ -/*! @{ */ - -#define SYSCON_PLL0CTRL_SELR_MASK (0xFU) -#define SYSCON_PLL0CTRL_SELR_SHIFT (0U) -/*! SELR - Bandwidth select R value. - */ -#define SYSCON_PLL0CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK) - -#define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U) -#define SYSCON_PLL0CTRL_SELI_SHIFT (4U) -/*! SELI - Bandwidth select I value. - */ -#define SYSCON_PLL0CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK) - -#define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U) -#define SYSCON_PLL0CTRL_SELP_SHIFT (10U) -/*! SELP - Bandwidth select P value. - */ -#define SYSCON_PLL0CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U) -#define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U) -/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - * 0b1..Bypass PLL input clock is sent directly to the PLL output. - * 0b0..use PLL. - */ -#define SYSCON_PLL0CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U) -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U) -/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - * 0b1..bypass of the divide-by-2 divider in the post-divider. - * 0b0..use the divide-by-2 divider in the post-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) - -#define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U) -#define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U) -/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. - */ -#define SYSCON_PLL0CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK) - -#define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U) -#define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U) -/*! BWDIRECT - Control of the bandwidth of the PLL. - * 0b1..modify the bandwidth of the PLL directly. - * 0b0..the bandwidth is changed synchronously with the feedback-divider. - */ -#define SYSCON_PLL0CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U) -#define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U) -/*! BYPASSPREDIV - bypass of the pre-divider. - * 0b1..bypass of the pre-divider. - * 0b0..use the pre-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U) -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U) -/*! BYPASSPOSTDIV - bypass of the post-divider. - * 0b1..bypass of the post-divider. - * 0b0..use the post-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) - -#define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U) -#define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U) -/*! CLKEN - enable the output clock. - * 0b1..enable the output clock. - * 0b0..disable the output clock. - */ -#define SYSCON_PLL0CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK) - -#define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U) -#define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U) -/*! FRMEN - free running mode. - * 0b1..free running mode is enable. - * 0b0..free running mode is disable. - */ -#define SYSCON_PLL0CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK) - -#define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U) -#define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U) -/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable. - */ -#define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK) - -#define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U) -#define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U) -/*! SKEWEN - skew mode. - * 0b1..skew mode is enable. - * 0b0..skew mode is disable. - */ -#define SYSCON_PLL0CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK) -/*! @} */ - -/*! @name PLL0STAT - PLL0 550m status */ -/*! @{ */ - -#define SYSCON_PLL0STAT_LOCK_MASK (0x1U) -#define SYSCON_PLL0STAT_LOCK_SHIFT (0U) -/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. - */ -#define SYSCON_PLL0STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK) - -#define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U) -#define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U) -/*! PREDIVACK - pre-divider ratio change acknowledge. - */ -#define SYSCON_PLL0STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK) - -#define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U) -#define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U) -/*! FEEDDIVACK - feedback divider ratio change acknowledge. - */ -#define SYSCON_PLL0STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK) - -#define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U) -#define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U) -/*! POSTDIVACK - post-divider ratio change acknowledge. - */ -#define SYSCON_PLL0STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK) - -#define SYSCON_PLL0STAT_FRMDET_MASK (0x10U) -#define SYSCON_PLL0STAT_FRMDET_SHIFT (4U) -/*! FRMDET - free running detector output (active high). - */ -#define SYSCON_PLL0STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK) -/*! @} */ - -/*! @name PLL0NDEC - PLL0 550m N divider */ -/*! @{ */ - -#define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU) -#define SYSCON_PLL0NDEC_NDIV_SHIFT (0U) -/*! NDIV - pre-divider divider ratio (N-divider). - */ -#define SYSCON_PLL0NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK) - -#define SYSCON_PLL0NDEC_NREQ_MASK (0x100U) -#define SYSCON_PLL0NDEC_NREQ_SHIFT (8U) -/*! NREQ - pre-divider ratio change request. - */ -#define SYSCON_PLL0NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK) -/*! @} */ - -/*! @name PLL0PDEC - PLL0 550m P divider */ -/*! @{ */ - -#define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU) -#define SYSCON_PLL0PDEC_PDIV_SHIFT (0U) -/*! PDIV - post-divider divider ratio (P-divider) - */ -#define SYSCON_PLL0PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK) - -#define SYSCON_PLL0PDEC_PREQ_MASK (0x20U) -#define SYSCON_PLL0PDEC_PREQ_SHIFT (5U) -/*! PREQ - feedback ratio change request. - */ -#define SYSCON_PLL0PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK) -/*! @} */ - -/*! @name PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 */ -/*! @{ */ - -#define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU) -#define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U) -/*! MD_LBS - input word of the wrapper bit 31 to 0. - */ -#define SYSCON_PLL0SSCG0_MD_LBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK) -/*! @} */ - -/*! @name PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 */ -/*! @{ */ - -#define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U) -#define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U) -/*! MD_MBS - input word of the wrapper bit 32. - */ -#define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK) - -#define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U) -#define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U) -/*! MD_REQ - md change request. - */ -#define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK) - -#define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) -#define SYSCON_PLL0SSCG1_MF_SHIFT (2U) -/*! MF - programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3. - */ -#define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK) - -#define SYSCON_PLL0SSCG1_MR_MASK (0xE0U) -#define SYSCON_PLL0SSCG1_MR_SHIFT (5U) -/*! MR - programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) - * mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1. - */ -#define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK) - -#define SYSCON_PLL0SSCG1_MC_MASK (0x300U) -#define SYSCON_PLL0SSCG1_MC_SHIFT (8U) -/*! MC - modulation waveform control Compensation for low pass filtering of the PLL to get a - * triangular modulation at the output of the PLL, giving a flat frequency spectrum. - */ -#define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK) - -#define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U) -#define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U) -/*! MDIV_EXT - to select an external mdiv value. - */ -#define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) - -#define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U) -#define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U) -/*! MREQ - to select an external mreq value. - */ -#define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK) - -#define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U) -#define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U) -/*! DITHER - dithering between two modulation frequencies in a random way or in a pseudo random way - * (white noise), in order to decrease the probability that the modulated waveform will occur - * with the same phase on a particular point on the screen. - */ -#define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK) - -#define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U) -#define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U) -/*! SEL_EXT - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext. - */ -#define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK) -/*! @} */ - -/*! @name FUNCRETENTIONCTRL - Functional retention control register */ -/*! @{ */ - -#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK (0x1U) -#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT (0U) -/*! FUNCRETENA - functional retention in power down only. - * 0b1..enable functional retention. - * 0b0..disable functional retention. - */ -#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK) - -#define SYSCON_FUNCRETENTIONCTRL_RET_START_MASK (0x3FFEU) -#define SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT (1U) -/*! RET_START - Start address divided by 4 inside SRAMX bank. - */ -#define SYSCON_FUNCRETENTIONCTRL_RET_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_START_MASK) - -#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK (0xFFC000U) -#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT (14U) -/*! RET_LENTH - lenth of Scan chains to save. - */ -#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) -/*! @} */ - -/*! @name CPUCTRL - CPU Control for multiple processors */ -/*! @{ */ - -#define SYSCON_CPUCTRL_CPU1CLKEN_MASK (0x8U) -#define SYSCON_CPUCTRL_CPU1CLKEN_SHIFT (3U) -/*! CPU1CLKEN - CPU1 clock enable. - * 0b1..The CPU1 clock is enabled. - * 0b0..The CPU1 clock is not enabled. - */ -#define SYSCON_CPUCTRL_CPU1CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1CLKEN_SHIFT)) & SYSCON_CPUCTRL_CPU1CLKEN_MASK) - -#define SYSCON_CPUCTRL_CPU1RSTEN_MASK (0x20U) -#define SYSCON_CPUCTRL_CPU1RSTEN_SHIFT (5U) -/*! CPU1RSTEN - CPU1 reset. - * 0b1..The CPU1 is being reset. - * 0b0..The CPU1 is not being reset. - */ -#define SYSCON_CPUCTRL_CPU1RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1RSTEN_SHIFT)) & SYSCON_CPUCTRL_CPU1RSTEN_MASK) -/*! @} */ - -/*! @name CPBOOT - Coprocessor Boot Address */ -/*! @{ */ - -#define SYSCON_CPBOOT_CPBOOT_MASK (0xFFFFFFFFU) -#define SYSCON_CPBOOT_CPBOOT_SHIFT (0U) -/*! CPBOOT - Coprocessor Boot Address for CPU1. - */ -#define SYSCON_CPBOOT_CPBOOT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_CPBOOT_SHIFT)) & SYSCON_CPBOOT_CPBOOT_MASK) -/*! @} */ - -/*! @name CPSTAT - CPU Status */ -/*! @{ */ - -#define SYSCON_CPSTAT_CPU0SLEEPING_MASK (0x1U) -#define SYSCON_CPSTAT_CPU0SLEEPING_SHIFT (0U) -/*! CPU0SLEEPING - The CPU0 sleeping state. - * 0b1..the CPU is sleeping. - * 0b0..the CPU is not sleeping. - */ -#define SYSCON_CPSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU0SLEEPING_MASK) - -#define SYSCON_CPSTAT_CPU1SLEEPING_MASK (0x2U) -#define SYSCON_CPSTAT_CPU1SLEEPING_SHIFT (1U) -/*! CPU1SLEEPING - The CPU1 sleeping state. - * 0b1..the CPU is sleeping. - * 0b0..the CPU is not sleeping. - */ -#define SYSCON_CPSTAT_CPU1SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU1SLEEPING_MASK) - -#define SYSCON_CPSTAT_CPU0LOCKUP_MASK (0x4U) -#define SYSCON_CPSTAT_CPU0LOCKUP_SHIFT (2U) -/*! CPU0LOCKUP - The CPU0 lockup state. - * 0b1..the CPU is in lockup. - * 0b0..the CPU is not in lockup. - */ -#define SYSCON_CPSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU0LOCKUP_MASK) - -#define SYSCON_CPSTAT_CPU1LOCKUP_MASK (0x8U) -#define SYSCON_CPSTAT_CPU1LOCKUP_SHIFT (3U) -/*! CPU1LOCKUP - The CPU1 lockup state. - * 0b1..the CPU is in lockup. - * 0b0..the CPU is not in lockup. - */ -#define SYSCON_CPSTAT_CPU1LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU1LOCKUP_MASK) -/*! @} */ - -/*! @name CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures */ -/*! @{ */ - -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U) -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U) -/*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U) -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U) -/*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U) -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U) -/*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U) -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U) -/*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) -#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) -/*! CLKIN_ENA - Enable clock_in clock for clock module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) -/*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U) -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U) -/*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U) -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U) -/*! XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U) -#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U) -/*! PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK) -/*! @} */ - -/*! @name COMP_INT_CTRL - Comparator Interrupt control */ -/*! @{ */ - -#define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U) -#define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U) -/*! INT_ENABLE - Analog Comparator interrupt enable control:. - * 0b1..interrupt enable. - * 0b0..interrupt disable. - */ -#define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK) - -#define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U) -#define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U) -/*! INT_CLEAR - Analog Comparator interrupt clear. - * 0b0..No effect. - * 0b1..Clear the interrupt. Self-cleared bit. - */ -#define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK) - -#define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU) -#define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U) -/*! INT_CTRL - Comparator interrupt type selector:. - * 0b000..The analog comparator interrupt edge sensitive is disabled. - * 0b010..analog comparator interrupt is rising edge sensitive. - * 0b100..analog comparator interrupt is falling edge sensitive. - * 0b110..analog comparator interrupt is rising and falling edge sensitive. - * 0b001..The analog comparator interrupt level sensitive is disabled. - * 0b011..Analog Comparator interrupt is high level sensitive. - * 0b101..Analog Comparator interrupt is low level sensitive. - * 0b111..The analog comparator interrupt level sensitive is disabled. - */ -#define SYSCON_COMP_INT_CTRL_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK) - -#define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U) -#define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U) -/*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. - * 0b0..Select Analog Comparator filtered output as input for interrupt detection. - * 0b1..Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when - * Analog comparator is used as wake up source in Power down mode. - */ -#define SYSCON_COMP_INT_CTRL_INT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK) -/*! @} */ - -/*! @name COMP_INT_STATUS - Comparator Interrupt status */ -/*! @{ */ - -#define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U) -#define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U) -/*! STATUS - Interrupt status BEFORE Interrupt Enable. - * 0b0..no interrupt pending. - * 0b1..interrupt pending. - */ -#define SYSCON_COMP_INT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK) - -#define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U) -#define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U) -/*! INT_STATUS - Interrupt status AFTER Interrupt Enable. - * 0b0..no interrupt pending. - * 0b1..interrupt pending. - */ -#define SYSCON_COMP_INT_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) - -#define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U) -#define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U) -/*! VAL - comparator analog output. - * 0b1..P+ is greater than P-. - * 0b0..P+ is smaller than P-. - */ -#define SYSCON_COMP_INT_STATUS_VAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK) -/*! @} */ - -/*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */ -/*! @{ */ - -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U) -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U) -/*! ROM - Control automatic clock gating of ROM controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK (0x2U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT (1U) -/*! RAMX_CTRL - Control automatic clock gating of RAMX controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK (0x4U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT (2U) -/*! RAM0_CTRL - Control automatic clock gating of RAM0 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK (0x8U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT (3U) -/*! RAM1_CTRL - Control automatic clock gating of RAM1 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK (0x10U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT (4U) -/*! RAM2_CTRL - Control automatic clock gating of RAM2 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK (0x20U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT (5U) -/*! RAM3_CTRL - Control automatic clock gating of RAM3 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK (0x40U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT (6U) -/*! RAM4_CTRL - Control automatic clock gating of RAM4 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U) -/*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U) -/*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U) -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U) -/*! CRCGEN - Control automatic clock gating of CRCGEN controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U) -/*! SDMA0 - Control automatic clock gating of DMA0 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U) -/*! SDMA1 - Control automatic clock gating of DMA1 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK (0x4000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT (14U) -/*! USB0 - Control automatic clock gating of USB controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U) -/*! SYSCON - Control automatic clock gating of synchronous system controller registers bank. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U) -/*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. - * 0b1100000011011110..Bit Fields 0 - 15 of this register are updated - * 0b0000000000000000..Bit Fields 0 - 15 of this register are not updated - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK) -/*! @} */ - -/*! @name GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module */ -/*! @{ */ - -#define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U) -#define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U) -/*! PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module. - * 0b1..bypass of the first stage of synchonization inside GPIO_INT module. - * 0b0..use the first stage of synchonization inside GPIO_INT module. - */ -#define SYSCON_GPIOPSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK) -/*! @} */ - -/*! @name DEBUG_LOCK_EN - Control write access to security registers. */ -/*! @{ */ - -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) -/*! LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, - * CODESECURITYPROTCPU1, CPU0_DEBUG_FEATURES, CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. - * 0b1010..1010: Enable write access to all 6 registers. - * 0b0000..Any other value than b1010: disable write access to all 6 registers. - */ -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) -/*! @} */ - -/*! @name DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control. */ -/*! @{ */ - -#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) -#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) -/*! CPU0_DBGEN - CPU0 Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) -#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) -/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK (0x30U) -#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (4U) -/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0xC0U) -#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U) -/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK (0x300U) -#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT (8U) -/*! CPU1_DBGEN - CPU1 Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK (0xC00U) -#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT (10U) -/*! CPU1_NIDEN - CPU1 Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK) -/*! @} */ - -/*! @name DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register. */ -/*! @{ */ - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) -/*! CPU0_DBGEN - CPU0 (CPU0) Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) -/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U) -/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U) -/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK (0x300U) -#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT (8U) -/*! CPU1_DBGEN - CPU1 Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK (0xC00U) -#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT (10U) -/*! CPU1_NIDEN - CPU1 Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK) -/*! @} */ - -/*! @name KEY_BLOCK - block quiddikey/PUF all index. */ -/*! @{ */ - -#define SYSCON_KEY_BLOCK_KEY_BLOCK_MASK (0xFFFFFFFFU) -#define SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT (0U) -/*! KEY_BLOCK - Write a value to block quiddikey/PUF all index. - */ -#define SYSCON_KEY_BLOCK_KEY_BLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCON_KEY_BLOCK_KEY_BLOCK_MASK) -/*! @} */ - -/*! @name DEBUG_AUTH_BEACON - Debug authentication BEACON register */ -/*! @{ */ - -#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) -#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) -/*! BEACON - Set by the debug authentication code in ROM to pass the debug beacons (Credential - * Beacon and Authentication Beacon) to application code. - */ -#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) -/*! @} */ - -/*! @name DEVICE_ID0 - Device ID */ -/*! @{ */ - -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) -/*! ROM_REV_MINOR - ROM revision. - */ -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) -/*! @} */ - -/*! @name DIEID - Chip revision ID and Number */ -/*! @{ */ - -#define SYSCON_DIEID_REV_ID_MASK (0xFU) -#define SYSCON_DIEID_REV_ID_SHIFT (0U) -/*! REV_ID - Chip Metal Revision ID. - */ -#define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK) - -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U) -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U) -/*! MCO_NUM_IN_DIE_ID - Chip Number 0x426B. - */ -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SYSCON_Register_Masks */ - - -/* SYSCON - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SYSCON base address */ - #define SYSCON_BASE (0x50000000u) - /** Peripheral SYSCON base address */ - #define SYSCON_BASE_NS (0x40000000u) - /** Peripheral SYSCON base pointer */ - #define SYSCON ((SYSCON_Type *)SYSCON_BASE) - /** Peripheral SYSCON base pointer */ - #define SYSCON_NS ((SYSCON_Type *)SYSCON_BASE_NS) - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS { SYSCON_BASE } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS { SYSCON } - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS_NS { SYSCON_BASE_NS } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS_NS { SYSCON_NS } -#else - /** Peripheral SYSCON base address */ - #define SYSCON_BASE (0x40000000u) - /** Peripheral SYSCON base pointer */ - #define SYSCON ((SYSCON_Type *)SYSCON_BASE) - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS { SYSCON_BASE } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS { SYSCON } -#endif - -/*! - * @} - */ /* end of group SYSCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SYSCTL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCTL_Peripheral_Access_Layer SYSCTL Peripheral Access Layer - * @{ - */ - -/** SYSCTL - Register Layout Typedef */ -typedef struct { - __IO uint32_t UPDATELCKOUT; /**< update lock out control, offset: 0x0 */ - uint8_t RESERVED_0[60]; - __IO uint32_t FCCTRLSEL[8]; /**< Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_1[32]; - __IO uint32_t SHAREDCTRLSET[2]; /**< Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1., array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_2[120]; - __I uint32_t USB_HS_STATUS; /**< Status register for USB HS, offset: 0x100 */ -} SYSCTL_Type; - -/* ---------------------------------------------------------------------------- - -- SYSCTL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCTL_Register_Masks SYSCTL Register Masks - * @{ - */ - -/*! @name UPDATELCKOUT - update lock out control */ -/*! @{ */ - -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U) -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U) -/*! UPDATELCKOUT - All Registers - * 0b0..Normal Mode. Can be written to. - * 0b1..Protected Mode. Cannot be written to. - */ -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK) -/*! @} */ - -/*! @name FCCTRLSEL - Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7 */ -/*! @{ */ - -#define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U) -#define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U) -/*! SCKINSEL - Selects the source for SCK going into this Flexcomm. - * 0b00..Selects the dedicated FCn_SCK function for this Flexcomm. - * 0b01..SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK) - -#define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U) -#define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U) -/*! WSINSEL - Selects the source for WS going into this Flexcomm. - * 0b00..Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. - * 0b01..WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK) - -#define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U) -#define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U) -/*! DATAINSEL - Selects the source for DATA input to this Flexcomm. - * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. - * 0b01..Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK) - -#define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U) -#define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U) -/*! DATAOUTSEL - Selects the source for DATA output from this Flexcomm. - * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. - * 0b01..Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_DATAOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK) -/*! @} */ - -/* The count of SYSCTL_FCCTRLSEL */ -#define SYSCTL_FCCTRLSEL_COUNT (8U) - -/*! @name SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */ -/*! @{ */ - -#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U) -#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U) -/*! SHAREDSCKSEL - Selects the source for SCK of this shared signal set. - * 0b000..SCK for this shared signal set comes from Flexcomm 0. - * 0b001..SCK for this shared signal set comes from Flexcomm 1. - * 0b010..SCK for this shared signal set comes from Flexcomm 2. - * 0b011..SCK for this shared signal set comes from Flexcomm 3. - * 0b100..SCK for this shared signal set comes from Flexcomm 4. - * 0b101..SCK for this shared signal set comes from Flexcomm 5. - * 0b110..SCK for this shared signal set comes from Flexcomm 6. - * 0b111..SCK for this shared signal set comes from Flexcomm 7. - */ -#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK) - -#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U) -#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U) -/*! SHAREDWSSEL - Selects the source for WS of this shared signal set. - * 0b000..WS for this shared signal set comes from Flexcomm 0. - * 0b001..WS for this shared signal set comes from Flexcomm 1. - * 0b010..WS for this shared signal set comes from Flexcomm 2. - * 0b011..WS for this shared signal set comes from Flexcomm 3. - * 0b100..WS for this shared signal set comes from Flexcomm 4. - * 0b101..WS for this shared signal set comes from Flexcomm 5. - * 0b110..WS for this shared signal set comes from Flexcomm 6. - * 0b111..WS for this shared signal set comes from Flexcomm 7. - */ -#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK) - -#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U) -#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U) -/*! SHAREDDATASEL - Selects the source for DATA input for this shared signal set. - * 0b000..DATA input for this shared signal set comes from Flexcomm 0. - * 0b001..DATA input for this shared signal set comes from Flexcomm 1. - * 0b010..DATA input for this shared signal set comes from Flexcomm 2. - * 0b011..DATA input for this shared signal set comes from Flexcomm 3. - * 0b100..DATA input for this shared signal set comes from Flexcomm 4. - * 0b101..DATA input for this shared signal set comes from Flexcomm 5. - * 0b110..DATA input for this shared signal set comes from Flexcomm 6. - * 0b111..DATA input for this shared signal set comes from Flexcomm 7. - */ -#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U) -#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U) -/*! FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC0 does not contribute to this shared set. - * 0b1..Data output from FC0 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U) -#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U) -/*! FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC1 does not contribute to this shared set. - * 0b1..Data output from FC1 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK (0x40000U) -#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT (18U) -/*! FC2DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC2 does not contribute to this shared set. - * 0b1..Data output from FC2 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U) -#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U) -/*! FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC4 does not contribute to this shared set. - * 0b1..Data output from FC4 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U) -#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U) -/*! FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC5 does not contribute to this shared set. - * 0b1..Data output from FC5 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U) -#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U) -/*! FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC6 does not contribute to this shared set. - * 0b1..Data output from FC6 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U) -#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U) -/*! FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC7 does not contribute to this shared set. - * 0b1..Data output from FC7 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK) -/*! @} */ - -/* The count of SYSCTL_SHAREDCTRLSET */ -#define SYSCTL_SHAREDCTRLSET_COUNT (2U) - -/*! @name USB_HS_STATUS - Status register for USB HS */ -/*! @{ */ - -#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK (0x1U) -#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT (0U) -/*! USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply. - * 0b0..3v3 supply is good. - * 0b1..3v3 supply is too low. - */ -#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT)) & SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SYSCTL_Register_Masks */ - - -/* SYSCTL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE (0x50023000u) - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE_NS (0x40023000u) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL_NS ((SYSCTL_Type *)SYSCTL_BASE_NS) - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS { SYSCTL } - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS_NS { SYSCTL_BASE_NS } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS_NS { SYSCTL_NS } -#else - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE (0x40023000u) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS { SYSCTL } -#endif - -/*! - * @} - */ /* end of group SYSCTL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USART Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer - * @{ - */ - -/** USART - Register Layout Typedef */ -typedef struct { - __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ - __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ - __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ - uint8_t RESERVED_0[12]; - __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ - __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ - __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ - __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ - uint8_t RESERVED_1[3536]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_2[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_3[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_4[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_6[4]; - __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ - uint8_t RESERVED_7[432]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} USART_Type; - -/* ---------------------------------------------------------------------------- - -- USART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Register_Masks USART Register Masks - * @{ - */ - -/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ -/*! @{ */ - -#define USART_CFG_ENABLE_MASK (0x1U) -#define USART_CFG_ENABLE_SHIFT (0U) -/*! ENABLE - USART Enable. - * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, - * all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control - * bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the - * transmitter has been reset and is therefore available. - * 0b1..Enabled. The USART is enabled for operation. - */ -#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) - -#define USART_CFG_DATALEN_MASK (0xCU) -#define USART_CFG_DATALEN_SHIFT (2U) -/*! DATALEN - Selects the data size for the USART. - * 0b00..7 bit Data length. - * 0b01..8 bit Data length. - * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. - * 0b11..Reserved. - */ -#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) - -#define USART_CFG_PARITYSEL_MASK (0x30U) -#define USART_CFG_PARITYSEL_SHIFT (4U) -/*! PARITYSEL - Selects what type of parity is used by the USART. - * 0b00..No parity. - * 0b01..Reserved. - * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, - * and the number of 1s in a received character is expected to be even. - * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, - * and the number of 1s in a received character is expected to be odd. - */ -#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) - -#define USART_CFG_STOPLEN_MASK (0x40U) -#define USART_CFG_STOPLEN_SHIFT (6U) -/*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. - * 0b0..1 stop bit. - * 0b1..2 stop bits. This setting should only be used for asynchronous communication. - */ -#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) - -#define USART_CFG_MODE32K_MASK (0x80U) -#define USART_CFG_MODE32K_SHIFT (7U) -/*! MODE32K - Selects standard or 32 kHz clocking mode. - * 0b0..Disabled. USART uses standard clocking. - * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. - */ -#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) - -#define USART_CFG_LINMODE_MASK (0x100U) -#define USART_CFG_LINMODE_SHIFT (8U) -/*! LINMODE - LIN break mode enable. - * 0b0..Disabled. Break detect and generate is configured for normal operation. - * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. - */ -#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) - -#define USART_CFG_CTSEN_MASK (0x200U) -#define USART_CFG_CTSEN_SHIFT (9U) -/*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input - * pin, or from the USART's own RTS if loopback mode is enabled. - * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. - * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. - */ -#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) - -#define USART_CFG_SYNCEN_MASK (0x800U) -#define USART_CFG_SYNCEN_SHIFT (11U) -/*! SYNCEN - Selects synchronous or asynchronous operation. - * 0b0..Asynchronous mode. - * 0b1..Synchronous mode. - */ -#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) - -#define USART_CFG_CLKPOL_MASK (0x1000U) -#define USART_CFG_CLKPOL_SHIFT (12U) -/*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. - * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK. - * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. - */ -#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) - -#define USART_CFG_SYNCMST_MASK (0x4000U) -#define USART_CFG_SYNCMST_SHIFT (14U) -/*! SYNCMST - Synchronous mode Master select. - * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. - * 0b1..Master. When synchronous mode is enabled, the USART is a master. - */ -#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) - -#define USART_CFG_LOOP_MASK (0x8000U) -#define USART_CFG_LOOP_SHIFT (15U) -/*! LOOP - Selects data loopback mode. - * 0b0..Normal operation. - * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial - * data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD - * and Un_RTS activity will also appear on external pins if these functions are configured to appear on device - * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. - */ -#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) - -#define USART_CFG_OETA_MASK (0x40000U) -#define USART_CFG_OETA_SHIFT (18U) -/*! OETA - Output Enable Turnaround time enable for RS-485 operation. - * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. - * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the - * end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins - * before it is deasserted. - */ -#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) - -#define USART_CFG_AUTOADDR_MASK (0x80000U) -#define USART_CFG_AUTOADDR_SHIFT (19U) -/*! AUTOADDR - Automatic Address matching enable. - * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the - * possibility of versatile addressing (e.g. respond to more than one address). - * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in - * the ADDR register as the address to match. - */ -#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) - -#define USART_CFG_OESEL_MASK (0x100000U) -#define USART_CFG_OESEL_SHIFT (20U) -/*! OESEL - Output Enable Select. - * 0b0..Standard. The RTS signal is used as the standard flow control function. - * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. - */ -#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) - -#define USART_CFG_OEPOL_MASK (0x200000U) -#define USART_CFG_OEPOL_SHIFT (21U) -/*! OEPOL - Output Enable Polarity. - * 0b0..Low. If selected by OESEL, the output enable is active low. - * 0b1..High. If selected by OESEL, the output enable is active high. - */ -#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) - -#define USART_CFG_RXPOL_MASK (0x400000U) -#define USART_CFG_RXPOL_SHIFT (22U) -/*! RXPOL - Receive data polarity. - * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start - * bit is 0, data is not inverted, and the stop bit is 1. - * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is - * 0, start bit is 1, data is inverted, and the stop bit is 0. - */ -#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) - -#define USART_CFG_TXPOL_MASK (0x800000U) -#define USART_CFG_TXPOL_SHIFT (23U) -/*! TXPOL - Transmit data polarity. - * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is - * 0, data is not inverted, and the stop bit is 1. - * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value - * is 0, start bit is 1, data is inverted, and the stop bit is 0. - */ -#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) -/*! @} */ - -/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ -/*! @{ */ - -#define USART_CTL_TXBRKEN_MASK (0x2U) -#define USART_CTL_TXBRKEN_SHIFT (1U) -/*! TXBRKEN - Break Enable. - * 0b0..Normal operation. - * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit - * is cleared. A break may be sent without danger of corrupting any currently transmitting character if the - * transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled - * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. - */ -#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) - -#define USART_CTL_ADDRDET_MASK (0x4U) -#define USART_CTL_ADDRDET_SHIFT (2U) -/*! ADDRDET - Enable address detect mode. - * 0b0..Disabled. The USART presents all incoming data. - * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data - * (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, - * generating a received data interrupt. Software can then check the data to see if this is an address that - * should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled - * normally. - */ -#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) - -#define USART_CTL_TXDIS_MASK (0x40U) -#define USART_CTL_TXDIS_SHIFT (6U) -/*! TXDIS - Transmit Disable. - * 0b0..Not disabled. USART transmitter is not disabled. - * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This - * feature can be used to facilitate software flow control. - */ -#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) - -#define USART_CTL_CC_MASK (0x100U) -#define USART_CTL_CC_SHIFT (8U) -/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. - * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to - * complete a character that is being received. - * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on - * Un_RxD independently from transmission on Un_TXD). - */ -#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) - -#define USART_CTL_CLRCCONRX_MASK (0x200U) -#define USART_CTL_CLRCCONRX_SHIFT (9U) -/*! CLRCCONRX - Clear Continuous Clock. - * 0b0..No effect. No effect on the CC bit. - * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. - */ -#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) - -#define USART_CTL_AUTOBAUD_MASK (0x10000U) -#define USART_CTL_AUTOBAUD_SHIFT (16U) -/*! AUTOBAUD - Autobaud enable. - * 0b0..Disabled. USART is in normal operating mode. - * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The - * first start bit of RX is measured and used the update the BRG register to match the received data rate. - * AUTOBAUD is cleared once this process is complete, or if there is an AERR. - */ -#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) -/*! @} */ - -/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ -/*! @{ */ - -#define USART_STAT_RXIDLE_MASK (0x2U) -#define USART_STAT_RXIDLE_SHIFT (1U) -/*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of - * receiving data. When 1, indicates that the receiver is not currently in the process of receiving - * data. - */ -#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) - -#define USART_STAT_TXIDLE_MASK (0x8U) -#define USART_STAT_TXIDLE_SHIFT (3U) -/*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of - * sending data.When 1, indicate that the transmitter is not currently in the process of sending - * data. - */ -#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) - -#define USART_STAT_CTS_MASK (0x10U) -#define USART_STAT_CTS_SHIFT (4U) -/*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the - * CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode - * is enabled. - */ -#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) - -#define USART_STAT_DELTACTS_MASK (0x20U) -#define USART_STAT_DELTACTS_SHIFT (5U) -/*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. - */ -#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) - -#define USART_STAT_TXDISSTAT_MASK (0x40U) -#define USART_STAT_TXDISSTAT_SHIFT (6U) -/*! TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART - * transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). - */ -#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) - -#define USART_STAT_RXBRK_MASK (0x400U) -#define USART_STAT_RXBRK_SHIFT (10U) -/*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection - * logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also - * be set when this condition occurs because the stop bit(s) for the character would be missing. - * RXBRK is cleared when the Un_RXD pin goes high. - */ -#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) - -#define USART_STAT_DELTARXBRK_MASK (0x800U) -#define USART_STAT_DELTARXBRK_SHIFT (11U) -/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software. - */ -#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) - -#define USART_STAT_START_MASK (0x1000U) -#define USART_STAT_START_SHIFT (12U) -/*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily - * to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. - * Cleared by software. - */ -#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) - -#define USART_STAT_FRAMERRINT_MASK (0x2000U) -#define USART_STAT_FRAMERRINT_SHIFT (13U) -/*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a - * missing stop bit at the expected location. This could be an indication of a baud rate or - * configuration mismatch with the transmitting source. - */ -#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) - -#define USART_STAT_PARITYERRINT_MASK (0x4000U) -#define USART_STAT_PARITYERRINT_SHIFT (14U) -/*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. - */ -#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) - -#define USART_STAT_RXNOISEINT_MASK (0x8000U) -#define USART_STAT_RXNOISEINT_SHIFT (15U) -/*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to - * determine the value of each received data bit, except in synchronous mode. This acts as a - * noise filter if one sample disagrees. This flag is set when a received data bit contains one - * disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or - * loss of synchronization during data reception. - */ -#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) - -#define USART_STAT_ABERR_MASK (0x10000U) -#define USART_STAT_ABERR_SHIFT (16U) -/*! ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the - * end of the start bit that is being measured, essentially an auto baud time-out. - */ -#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -/*! @{ */ - -#define USART_INTENSET_TXIDLEEN_MASK (0x8U) -#define USART_INTENSET_TXIDLEEN_SHIFT (3U) -/*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). - */ -#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) - -#define USART_INTENSET_DELTACTSEN_MASK (0x20U) -#define USART_INTENSET_DELTACTSEN_SHIFT (5U) -/*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input. - */ -#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) - -#define USART_INTENSET_TXDISEN_MASK (0x40U) -#define USART_INTENSET_TXDISEN_SHIFT (6U) -/*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by - * the TXDISINT flag in STAT. See description of the TXDISINT bit for details. - */ -#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) - -#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) -#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) -/*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection - * of a received break condition (break condition asserted or deasserted). - */ -#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) - -#define USART_INTENSET_STARTEN_MASK (0x1000U) -#define USART_INTENSET_STARTEN_SHIFT (12U) -/*! STARTEN - When 1, enables an interrupt when a received start bit has been detected. - */ -#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) - -#define USART_INTENSET_FRAMERREN_MASK (0x2000U) -#define USART_INTENSET_FRAMERREN_SHIFT (13U) -/*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected. - */ -#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) - -#define USART_INTENSET_PARITYERREN_MASK (0x4000U) -#define USART_INTENSET_PARITYERREN_SHIFT (14U) -/*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected. - */ -#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) - -#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) -#define USART_INTENSET_RXNOISEEN_SHIFT (15U) -/*! RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. - */ -#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) - -#define USART_INTENSET_ABERREN_MASK (0x10000U) -#define USART_INTENSET_ABERREN_SHIFT (16U) -/*! ABERREN - When 1, enables an interrupt when an auto baud error occurs. - */ -#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ -/*! @{ */ - -#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) -#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) -/*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) - -#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) -#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) -/*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) - -#define USART_INTENCLR_TXDISCLR_MASK (0x40U) -#define USART_INTENCLR_TXDISCLR_SHIFT (6U) -/*! TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) - -#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) -#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) -/*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) - -#define USART_INTENCLR_STARTCLR_MASK (0x1000U) -#define USART_INTENCLR_STARTCLR_SHIFT (12U) -/*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) - -#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) -#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) -/*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) - -#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) -#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) -/*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) - -#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) -#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) -/*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) - -#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) -#define USART_INTENCLR_ABERRCLR_SHIFT (16U) -/*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) -/*! @} */ - -/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ -/*! @{ */ - -#define USART_BRG_BRGVAL_MASK (0xFFFFU) -#define USART_BRG_BRGVAL_SHIFT (0U) -/*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on - * the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is - * divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART - * function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. - */ -#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ -/*! @{ */ - -#define USART_INTSTAT_TXIDLE_MASK (0x8U) -#define USART_INTSTAT_TXIDLE_SHIFT (3U) -/*! TXIDLE - Transmitter Idle status. - */ -#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) - -#define USART_INTSTAT_DELTACTS_MASK (0x20U) -#define USART_INTSTAT_DELTACTS_SHIFT (5U) -/*! DELTACTS - This bit is set when a change in the state of the CTS input is detected. - */ -#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) - -#define USART_INTSTAT_TXDISINT_MASK (0x40U) -#define USART_INTSTAT_TXDISINT_SHIFT (6U) -/*! TXDISINT - Transmitter Disabled Interrupt flag. - */ -#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) - -#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) -#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) -/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. - */ -#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) - -#define USART_INTSTAT_START_MASK (0x1000U) -#define USART_INTSTAT_START_SHIFT (12U) -/*! START - This bit is set when a start is detected on the receiver input. - */ -#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) - -#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) -#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) -/*! FRAMERRINT - Framing Error interrupt flag. - */ -#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) - -#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) -#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) -/*! PARITYERRINT - Parity Error interrupt flag. - */ -#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) - -#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) -#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) -/*! RXNOISEINT - Received Noise interrupt flag. - */ -#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) - -#define USART_INTSTAT_ABERRINT_MASK (0x10000U) -#define USART_INTSTAT_ABERRINT_SHIFT (16U) -/*! ABERRINT - Auto baud Error Interrupt flag. - */ -#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) -/*! @} */ - -/*! @name OSR - Oversample selection register for asynchronous communication. */ -/*! @{ */ - -#define USART_OSR_OSRVAL_MASK (0xFU) -#define USART_OSR_OSRVAL_SHIFT (0U) -/*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to - * transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive - * each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. - */ -#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) -/*! @} */ - -/*! @name ADDR - Address register for automatic address matching. */ -/*! @{ */ - -#define USART_ADDR_ADDRESS_MASK (0xFFU) -#define USART_ADDR_ADDRESS_SHIFT (0U) -/*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is - * enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). - */ -#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ - -#define USART_FIFOCFG_ENABLETX_MASK (0x1U) -#define USART_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) - -#define USART_FIFOCFG_ENABLERX_MASK (0x2U) -#define USART_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) - -#define USART_FIFOCFG_SIZE_MASK (0x30U) -#define USART_FIFOCFG_SIZE_SHIFT (4U) -/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 - * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - */ -#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) - -#define USART_FIFOCFG_DMATX_MASK (0x1000U) -#define USART_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) - -#define USART_FIFOCFG_DMARX_MASK (0x2000U) -#define USART_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) - -#define USART_FIFOCFG_WAKETX_MASK (0x4000U) -#define USART_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in - * FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) - -#define USART_FIFOCFG_WAKERX_MASK (0x8000U) -#define USART_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in - * FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) - -#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) -/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - */ -#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) - -#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) -/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - */ -#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ - -#define USART_FIFOSTAT_TXERR_MASK (0x1U) -#define USART_FIFOSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow - * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is - * needed. Cleared by writing a 1 to this bit. - */ -#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) - -#define USART_FIFOSTAT_RXERR_MASK (0x2U) -#define USART_FIFOSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA - * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - */ -#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) - -#define USART_FIFOSTAT_PERINT_MASK (0x8U) -#define USART_FIFOSTAT_PERINT_SHIFT (3U) -/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted - * an interrupt. The details can be found by reading the peripheral's STAT register. - */ -#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) - -#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) -/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - */ -#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) - -#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) -/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be - * written. When 0, the transmit FIFO is full and another write would cause it to overflow. - */ -#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) - -#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - */ -#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) - -#define USART_FIFOSTAT_RXFULL_MASK (0x80U) -#define USART_FIFOSTAT_RXFULL_SHIFT (7U) -/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to - * prevent the peripheral from causing an overflow. - */ -#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) - -#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define USART_FIFOSTAT_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY - * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at - * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be - * 0. - */ -#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) - -#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define USART_FIFOSTAT_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and - * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the - * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be - * 1. - */ -#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ - -#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) - -#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) - -#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) -#define USART_FIFOTRIG_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled - * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to - * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO - * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX - * FIFO level decreases to 15 entries (is no longer full). - */ -#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) - -#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define USART_FIFOTRIG_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data - * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level - * can wake up the device just enough to perform DMA, then return to the reduced power mode. See - * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no - * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX - * FIFO has received 16 entries (has become full). - */ -#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ - -#define USART_FIFOINTENSET_TXERR_MASK (0x1U) -#define USART_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) - -#define USART_FIFOINTENSET_RXERR_MASK (0x2U) -#define USART_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) - -#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) -#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases - * to the level specified by TXLVL in the FIFOTRIG register. - */ -#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) - -#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) -#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level - * increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ - -#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) -#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) -/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) - -#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) -#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) -/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) - -#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) -/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) - -#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) -/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ - -#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) -#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. - */ -#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) - -#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) -#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. - */ -#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) - -#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO level interrupt. - */ -#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) - -#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO level interrupt. - */ -#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) - -#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) -#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) -/*! PERINT - Peripheral interrupt. - */ -#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ - -#define USART_FIFOWR_TXDATA_MASK (0x1FFU) -#define USART_FIFOWR_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit data to the FIFO. - */ -#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ - -#define USART_FIFORD_RXDATA_MASK (0x1FFU) -#define USART_FIFORD_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. - */ -#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) - -#define USART_FIFORD_FRAMERR_MASK (0x2000U) -#define USART_FIFORD_FRAMERR_SHIFT (13U) -/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along - * with from the FIFO, and indicates that the character was received with a missing stop bit at - * the expected location. This could be an indication of a baud rate or configuration mismatch - * with the transmitting source. - */ -#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) - -#define USART_FIFORD_PARITYERR_MASK (0x4000U) -#define USART_FIFORD_PARITYERR_SHIFT (14U) -/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along - * with from the FIFO. This bit will be set when a parity error is detected in a received - * character. - */ -#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) - -#define USART_FIFORD_RXNOISE_MASK (0x8000U) -#define USART_FIFORD_RXNOISE_SHIFT (15U) -/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. - */ -#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ - -#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) -#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. - */ -#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) - -#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) -#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) -/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along - * with from the FIFO, and indicates that the character was received with a missing stop bit at - * the expected location. This could be an indication of a baud rate or configuration mismatch - * with the transmitting source. - */ -#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) - -#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) -#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) -/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along - * with from the FIFO. This bit will be set when a parity error is detected in a received - * character. - */ -#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) - -#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) -#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) -/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. - */ -#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) -/*! @} */ - -/*! @name FIFOSIZE - FIFO size register */ -/*! @{ */ - -#define USART_FIFOSIZE_FIFOSIZE_MASK (0x1FU) -#define USART_FIFOSIZE_FIFOSIZE_SHIFT (0U) -/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - */ -#define USART_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSIZE_FIFOSIZE_SHIFT)) & USART_FIFOSIZE_FIFOSIZE_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ - -#define USART_ID_APERTURE_MASK (0xFFU) -#define USART_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - */ -#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) - -#define USART_ID_MINOR_REV_MASK (0xF00U) -#define USART_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation. - */ -#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) - -#define USART_ID_MAJOR_REV_MASK (0xF000U) -#define USART_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation. - */ -#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) - -#define USART_ID_ID_MASK (0xFFFF0000U) -#define USART_ID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function. - */ -#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USART_Register_Masks */ - - -/* USART - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USART0 base address */ - #define USART0_BASE (0x50086000u) - /** Peripheral USART0 base address */ - #define USART0_BASE_NS (0x40086000u) - /** Peripheral USART0 base pointer */ - #define USART0 ((USART_Type *)USART0_BASE) - /** Peripheral USART0 base pointer */ - #define USART0_NS ((USART_Type *)USART0_BASE_NS) - /** Peripheral USART1 base address */ - #define USART1_BASE (0x50087000u) - /** Peripheral USART1 base address */ - #define USART1_BASE_NS (0x40087000u) - /** Peripheral USART1 base pointer */ - #define USART1 ((USART_Type *)USART1_BASE) - /** Peripheral USART1 base pointer */ - #define USART1_NS ((USART_Type *)USART1_BASE_NS) - /** Peripheral USART2 base address */ - #define USART2_BASE (0x50088000u) - /** Peripheral USART2 base address */ - #define USART2_BASE_NS (0x40088000u) - /** Peripheral USART2 base pointer */ - #define USART2 ((USART_Type *)USART2_BASE) - /** Peripheral USART2 base pointer */ - #define USART2_NS ((USART_Type *)USART2_BASE_NS) - /** Peripheral USART3 base address */ - #define USART3_BASE (0x50089000u) - /** Peripheral USART3 base address */ - #define USART3_BASE_NS (0x40089000u) - /** Peripheral USART3 base pointer */ - #define USART3 ((USART_Type *)USART3_BASE) - /** Peripheral USART3 base pointer */ - #define USART3_NS ((USART_Type *)USART3_BASE_NS) - /** Peripheral USART4 base address */ - #define USART4_BASE (0x5008A000u) - /** Peripheral USART4 base address */ - #define USART4_BASE_NS (0x4008A000u) - /** Peripheral USART4 base pointer */ - #define USART4 ((USART_Type *)USART4_BASE) - /** Peripheral USART4 base pointer */ - #define USART4_NS ((USART_Type *)USART4_BASE_NS) - /** Peripheral USART5 base address */ - #define USART5_BASE (0x50096000u) - /** Peripheral USART5 base address */ - #define USART5_BASE_NS (0x40096000u) - /** Peripheral USART5 base pointer */ - #define USART5 ((USART_Type *)USART5_BASE) - /** Peripheral USART5 base pointer */ - #define USART5_NS ((USART_Type *)USART5_BASE_NS) - /** Peripheral USART6 base address */ - #define USART6_BASE (0x50097000u) - /** Peripheral USART6 base address */ - #define USART6_BASE_NS (0x40097000u) - /** Peripheral USART6 base pointer */ - #define USART6 ((USART_Type *)USART6_BASE) - /** Peripheral USART6 base pointer */ - #define USART6_NS ((USART_Type *)USART6_BASE_NS) - /** Peripheral USART7 base address */ - #define USART7_BASE (0x50098000u) - /** Peripheral USART7 base address */ - #define USART7_BASE_NS (0x40098000u) - /** Peripheral USART7 base pointer */ - #define USART7 ((USART_Type *)USART7_BASE) - /** Peripheral USART7 base pointer */ - #define USART7_NS ((USART_Type *)USART7_BASE_NS) - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS_NS { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS_NS { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS } -#else - /** Peripheral USART0 base address */ - #define USART0_BASE (0x40086000u) - /** Peripheral USART0 base pointer */ - #define USART0 ((USART_Type *)USART0_BASE) - /** Peripheral USART1 base address */ - #define USART1_BASE (0x40087000u) - /** Peripheral USART1 base pointer */ - #define USART1 ((USART_Type *)USART1_BASE) - /** Peripheral USART2 base address */ - #define USART2_BASE (0x40088000u) - /** Peripheral USART2 base pointer */ - #define USART2 ((USART_Type *)USART2_BASE) - /** Peripheral USART3 base address */ - #define USART3_BASE (0x40089000u) - /** Peripheral USART3 base pointer */ - #define USART3 ((USART_Type *)USART3_BASE) - /** Peripheral USART4 base address */ - #define USART4_BASE (0x4008A000u) - /** Peripheral USART4 base pointer */ - #define USART4 ((USART_Type *)USART4_BASE) - /** Peripheral USART5 base address */ - #define USART5_BASE (0x40096000u) - /** Peripheral USART5 base pointer */ - #define USART5 ((USART_Type *)USART5_BASE) - /** Peripheral USART6 base address */ - #define USART6_BASE (0x40097000u) - /** Peripheral USART6 base pointer */ - #define USART6 ((USART_Type *)USART6_BASE) - /** Peripheral USART7 base address */ - #define USART7_BASE (0x40098000u) - /** Peripheral USART7 base pointer */ - #define USART7 ((USART_Type *)USART7_BASE) - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } -#endif -/** Interrupt vectors for the USART peripheral type */ -#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group USART_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer - * @{ - */ - -/** USB - Register Layout Typedef */ -typedef struct { - __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ - __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ - __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ - __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ - __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ - __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ - __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ - __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ - __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ - __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ - __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ - uint8_t RESERVED_0[8]; - __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ -} USB_Type; - -/* ---------------------------------------------------------------------------- - -- USB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Register_Masks USB Register Masks - * @{ - */ - -/*! @name DEVCMDSTAT - USB Device Command/Status register */ -/*! @{ */ - -#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) -#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) -/*! DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit - * is set, the device will respond on packets for function address DEV_ADDR. When receiving a - * SetAddress Control Request from the USB host, software must program the new address before - * completing the status phase of the SetAddress Control Request. - */ -#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) - -#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) -#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) -/*! DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. - */ -#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) - -#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) -#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) -/*! SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this - * bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW - * must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the - * CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. - */ -#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) - -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) -/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: - * 0b0..USB_NEEDCLK has normal function. - * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. - */ -#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) - -#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) -#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) -/*! LPM_SUP - LPM Supported: - * 0b0..LPM not supported. - * 0b1..LPM supported. - */ -#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) - -#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) -#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) -/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) - -#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) -#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) -/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) - -#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) -#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) -/*! INTONNAK_CO - Interrupt on NAK for control OUT EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) - -#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) -#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) -/*! INTONNAK_CI - Interrupt on NAK for control IN EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) - -#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) -#define USB_DEVCMDSTAT_DCON_SHIFT (16U) -/*! DCON - Device status - connect. The connect bit must be set by SW to indicate that the device - * must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and - * the VBUSDEBOUNCED bit is one. - */ -#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) - -#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) -#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) -/*! DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set - * to 1 when the device hasn't seen any activity on its upstream port for more than 3 - * milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and - * the software writes a 0 to it, the device will generate a remote wake-up. This will only happen - * when the device is connected (Connect bit = 1). When the device is not connected or not - * suspended, a writing a 0 has no effect. Writing a 1 never has an effect. - */ -#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) - -#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) -#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) -/*! LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is - * set to 1 by HW when the device has acknowledged the LPM request from the USB host and the - * Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend - * bit = 1) and the software writes a zero to this bit, the device will generate a remote - * walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this - * bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the - * LPM_SUPP bit is equal to one. - */ -#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) - -#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) -#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) -/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake - * bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the - * host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset - * is received. Software can use this bit to check if the remote wake-up feature is enabled by the - * host for the LPM transaction. - */ -#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) - -#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) -#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) -/*! DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up - * resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. - */ -#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) - -#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) -#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) -/*! DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit - * toggles. The suspend bit can toggle because: - The device goes in the suspended state - The - * device is disconnected - The device receives resume signaling on its upstream port. The bit is - * reset by writing a one to it. - */ -#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) - -#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) -#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) -/*! DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On - * a bus reset the device will automatically go to the default state (unconfigured and responding - * to address 0). The bit is reset by writing a one to it. - */ -#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) - -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) -/*! VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when - * Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and - * the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. - */ -#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) -/*! @} */ - -/*! @name INFO - USB Info register */ -/*! @{ */ - -#define USB_INFO_FRAME_NR_MASK (0x7FFU) -#define USB_INFO_FRAME_NR_SHIFT (0U) -/*! FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF. - * In case no SOF was received by the device at the beginning of a frame, the frame number - * returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC - * error, the frame number returned will be the corrupted frame number as received by the device. - */ -#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) - -#define USB_INFO_ERR_CODE_MASK (0x7800U) -#define USB_INFO_ERR_CODE_SHIFT (11U) -/*! ERR_CODE - The error code which last occurred: - * 0b0000..No error - * 0b0001..PID encoding error - * 0b0010..PID unknown - * 0b0011..Packet unexpected - * 0b0100..Token CRC error - * 0b0101..Data CRC error - * 0b0110..Time out - * 0b0111..Babble - * 0b1000..Truncated EOP - * 0b1001..Sent/Received NAK - * 0b1010..Sent Stall - * 0b1011..Overrun - * 0b1100..Sent empty packet - * 0b1101..Bitstuff error - * 0b1110..Sync error - * 0b1111..Wrong data toggle - */ -#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) - -#define USB_INFO_MINREV_MASK (0xFF0000U) -#define USB_INFO_MINREV_SHIFT (16U) -/*! MINREV - Minor Revision. - */ -#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK) - -#define USB_INFO_MAJREV_MASK (0xFF000000U) -#define USB_INFO_MAJREV_SHIFT (24U) -/*! MAJREV - Major Revision. - */ -#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK) -/*! @} */ - -/*! @name EPLISTSTART - USB EP Command/Status List start address */ -/*! @{ */ - -#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) -#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) -/*! EP_LIST - Start address of the USB EP Command/Status List. - */ -#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) -/*! @} */ - -/*! @name DATABUFSTART - USB Data buffer start address */ -/*! @{ */ - -#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) -#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) -/*! DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located. - */ -#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) -/*! @} */ - -/*! @name LPM - USB Link Power Management register */ -/*! @{ */ - -#define USB_LPM_HIRD_HW_MASK (0xFU) -#define USB_LPM_HIRD_HW_SHIFT (0U) -/*! HIRD_HW - Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token - */ -#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) - -#define USB_LPM_HIRD_SW_MASK (0xF0U) -#define USB_LPM_HIRD_SW_SHIFT (4U) -/*! HIRD_SW - Host Initiated Resume Duration - SW. This is the time duration required by the USB - * device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. - */ -#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) - -#define USB_LPM_DATA_PENDING_MASK (0x100U) -#define USB_LPM_DATA_PENDING_SHIFT (8U) -/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will - * return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and - * this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has - * still data pending and LPM is supported, it must set this bit to 1. - */ -#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) -/*! @} */ - -/*! @name EPSKIP - USB Endpoint skip */ -/*! @{ */ - -#define USB_EPSKIP_SKIP_MASK (0x3FFU) -#define USB_EPSKIP_SKIP_SHIFT (0U) -/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must - * deactivate the buffer assigned to this endpoint and return control back to software. When HW has - * deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An - * interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, - * HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. - */ -#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) -/*! @} */ - -/*! @name EPINUSE - USB Endpoint Buffer in use */ -/*! @{ */ - -#define USB_EPINUSE_BUF_MASK (0x3FCU) -#define USB_EPINUSE_BUF_SHIFT (2U) -/*! BUF - Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer - * 0. 1: HW is accessing buffer 1. - */ -#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) -/*! @} */ - -/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ -/*! @{ */ - -#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) -#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) -/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: - * Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding - * EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle - * the EPINUSE bit when it clears the Active bit for the buffer. - */ -#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) -/*! @} */ - -/*! @name INTSTAT - USB interrupt status register */ -/*! @{ */ - -#define USB_INTSTAT_EP0OUT_MASK (0x1U) -#define USB_INTSTAT_EP0OUT_SHIFT (0U) -/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set - * if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is - * successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a - * NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a - * one to it. - */ -#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) - -#define USB_INTSTAT_EP0IN_MASK (0x2U) -#define USB_INTSTAT_EP0IN_SHIFT (1U) -/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if - * NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this - * bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can - * clear this bit by writing a one to it. - */ -#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) - -#define USB_INTSTAT_EP1OUT_MASK (0x4U) -#define USB_INTSTAT_EP1OUT_SHIFT (2U) -/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes - * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be - * set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by - * writing a one to it. - */ -#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) - -#define USB_INTSTAT_EP1IN_MASK (0x8U) -#define USB_INTSTAT_EP1IN_SHIFT (3U) -/*! EP1IN - Interrupt status register bit for the EP1 IN direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions - * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be - * set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing - * a one to it. - */ -#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) - -#define USB_INTSTAT_EP2OUT_MASK (0x10U) -#define USB_INTSTAT_EP2OUT_SHIFT (4U) -/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes - * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be - * set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by - * writing a one to it. - */ -#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) - -#define USB_INTSTAT_EP2IN_MASK (0x20U) -#define USB_INTSTAT_EP2IN_SHIFT (5U) -/*! EP2IN - Interrupt status register bit for the EP2 IN direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions - * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be - * set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing - * a one to it. - */ -#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) - -#define USB_INTSTAT_EP3OUT_MASK (0x40U) -#define USB_INTSTAT_EP3OUT_SHIFT (6U) -/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes - * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be - * set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by - * writing a one to it. - */ -#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) - -#define USB_INTSTAT_EP3IN_MASK (0x80U) -#define USB_INTSTAT_EP3IN_SHIFT (7U) -/*! EP3IN - Interrupt status register bit for the EP3 IN direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions - * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be - * set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing - * a one to it. - */ -#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) - -#define USB_INTSTAT_EP4OUT_MASK (0x100U) -#define USB_INTSTAT_EP4OUT_SHIFT (8U) -/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes - * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be - * set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by - * writing a one to it. - */ -#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) - -#define USB_INTSTAT_EP4IN_MASK (0x200U) -#define USB_INTSTAT_EP4IN_SHIFT (9U) -/*! EP4IN - Interrupt status register bit for the EP4 IN direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions - * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be - * set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing - * a one to it. - */ -#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) - -#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) -#define USB_INTSTAT_FRAME_INT_SHIFT (30U) -/*! FRAME_INT - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit - * and the DCON bit are set. This bit can be used by software when handling isochronous - * endpoints. Software can clear this bit by writing a one to it. - */ -#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) - -#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) -#define USB_INTSTAT_DEV_INT_SHIFT (31U) -/*! DEV_INT - Device status interrupt. This bit is set by HW when one of the bits in the Device - * Status Change register are set. Software can clear this bit by writing a one to it. - */ -#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) -/*! @} */ - -/*! @name INTEN - USB interrupt enable register */ -/*! @{ */ - -#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) -#define USB_INTEN_EP_INT_EN_SHIFT (0U) -/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing - * bit. - */ -#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) - -#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) -#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) -/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt - * routing bit. - */ -#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) - -#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) -#define USB_INTEN_DEV_INT_EN_SHIFT (31U) -/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing - * bit. - */ -#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) -/*! @} */ - -/*! @name INTSETSTAT - USB set interrupt status register */ -/*! @{ */ - -#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) -#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) -/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt - * status bit is set. When this register is read, the same value as the USB interrupt status register - * is returned. - */ -#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) - -#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) -#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) -/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt - * status bit is set. When this register is read, the same value as the USB interrupt status - * register is returned. - */ -#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) - -#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) -#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) -/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt - * status bit is set. When this register is read, the same value as the USB interrupt status - * register is returned. - */ -#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) -/*! @} */ - -/*! @name EPTOGGLE - USB Endpoint toggle register */ -/*! @{ */ - -#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) -#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) -/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. - */ -#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USB_Register_Masks */ - - -/* USB - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USB0 base address */ - #define USB0_BASE (0x50084000u) - /** Peripheral USB0 base address */ - #define USB0_BASE_NS (0x40084000u) - /** Peripheral USB0 base pointer */ - #define USB0 ((USB_Type *)USB0_BASE) - /** Peripheral USB0 base pointer */ - #define USB0_NS ((USB_Type *)USB0_BASE_NS) - /** Array initializer of USB peripheral base addresses */ - #define USB_BASE_ADDRS { USB0_BASE } - /** Array initializer of USB peripheral base pointers */ - #define USB_BASE_PTRS { USB0 } - /** Array initializer of USB peripheral base addresses */ - #define USB_BASE_ADDRS_NS { USB0_BASE_NS } - /** Array initializer of USB peripheral base pointers */ - #define USB_BASE_PTRS_NS { USB0_NS } -#else - /** Peripheral USB0 base address */ - #define USB0_BASE (0x40084000u) - /** Peripheral USB0 base pointer */ - #define USB0 ((USB_Type *)USB0_BASE) - /** Array initializer of USB peripheral base addresses */ - #define USB_BASE_ADDRS { USB0_BASE } - /** Array initializer of USB peripheral base pointers */ - #define USB_BASE_PTRS { USB0 } -#endif -/** Interrupt vectors for the USB peripheral type */ -#define USB_IRQS { USB0_IRQn } -#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBFSH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer - * @{ - */ - -/** USBFSH - Register Layout Typedef */ -typedef struct { - __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */ - __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */ - __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */ - __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */ - __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */ - __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */ - __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */ - __I uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */ - __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */ - __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */ - __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */ - __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */ - __I uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */ - __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */ - __I uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */ - __I uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */ - __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */ - __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */ - __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */ - __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */ - __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */ - __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */ - uint8_t RESERVED_0[4]; - __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */ -} USBFSH_Type; - -/* ---------------------------------------------------------------------------- - -- USBFSH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBFSH_Register_Masks USBFSH Register Masks - * @{ - */ - -/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */ -/*! @{ */ - -#define USBFSH_HCREVISION_REV_MASK (0xFFU) -#define USBFSH_HCREVISION_REV_SHIFT (0U) -/*! REV - Revision. - */ -#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK) -/*! @} */ - -/*! @name HCCONTROL - Defines the operating modes of the HC */ -/*! @{ */ - -#define USBFSH_HCCONTROL_CBSR_MASK (0x3U) -#define USBFSH_HCCONTROL_CBSR_SHIFT (0U) -/*! CBSR - ControlBulkServiceRatio. - */ -#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK) - -#define USBFSH_HCCONTROL_PLE_MASK (0x4U) -#define USBFSH_HCCONTROL_PLE_SHIFT (2U) -/*! PLE - PeriodicListEnable. - */ -#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK) - -#define USBFSH_HCCONTROL_IE_MASK (0x8U) -#define USBFSH_HCCONTROL_IE_SHIFT (3U) -/*! IE - IsochronousEnable. - */ -#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK) - -#define USBFSH_HCCONTROL_CLE_MASK (0x10U) -#define USBFSH_HCCONTROL_CLE_SHIFT (4U) -/*! CLE - ControlListEnable. - */ -#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK) - -#define USBFSH_HCCONTROL_BLE_MASK (0x20U) -#define USBFSH_HCCONTROL_BLE_SHIFT (5U) -/*! BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. - */ -#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK) - -#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U) -#define USBFSH_HCCONTROL_HCFS_SHIFT (6U) -/*! HCFS - HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL - * 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin - * 1 ms later. - */ -#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK) - -#define USBFSH_HCCONTROL_IR_MASK (0x100U) -#define USBFSH_HCCONTROL_IR_SHIFT (8U) -/*! IR - InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. - */ -#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK) - -#define USBFSH_HCCONTROL_RWC_MASK (0x200U) -#define USBFSH_HCCONTROL_RWC_SHIFT (9U) -/*! RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling. - */ -#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK) - -#define USBFSH_HCCONTROL_RWE_MASK (0x400U) -#define USBFSH_HCCONTROL_RWE_SHIFT (10U) -/*! RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature - * upon the detection of upstream resume signaling. - */ -#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK) -/*! @} */ - -/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */ -/*! @{ */ - -#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U) -#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U) -/*! HCR - HostControllerReset This bit is set by HCD to initiate a software reset of HC. - */ -#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK) - -#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U) -#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U) -/*! CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. - */ -#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK) - -#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U) -#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U) -/*! BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. - */ -#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK) - -#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U) -#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U) -/*! OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC. - */ -#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK) - -#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U) -#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U) -/*! SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error. - */ -#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK) -/*! @} */ - -/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */ -/*! @{ */ - -#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U) -/*! SO - SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and - * after the update of HccaFrameNumber. - */ -#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U) -/*! WDH - WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead. - */ -#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U) -/*! SF - StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. - */ -#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U) -/*! RD - ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling. - */ -#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U) -/*! UE - UnrecoverableError This bit is set when HC detects a system error not related to USB. - */ -#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U) -/*! FNO - FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value, - * from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated. - */ -#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U) -/*! RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any - * of HcRhPortStatus[NumberofDownstreamPort] has changed. - */ -#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U) -#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U) -/*! OC - OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus. - */ -#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK) -/*! @} */ - -/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */ -/*! @{ */ - -#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U) -/*! SO - Scheduling Overrun interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK) - -#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U) -/*! WDH - HcDoneHead Writeback interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK) - -#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U) -/*! SF - Start of Frame interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK) - -#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U) -/*! RD - Resume Detect interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK) - -#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U) -/*! UE - Unrecoverable Error interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK) - -#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U) -/*! FNO - Frame Number Overflow interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK) - -#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U) -/*! RHSC - Root Hub Status Change interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK) - -#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U) -#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U) -/*! OC - Ownership Change interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK) - -#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U) -#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U) -/*! MIE - Master Interrupt Enable. - */ -#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK) -/*! @} */ - -/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */ -/*! @{ */ - -#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U) -/*! SO - Scheduling Overrun interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U) -/*! WDH - HcDoneHead Writeback interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U) -/*! SF - Start of Frame interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U) -/*! RD - Resume Detect interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U) -/*! UE - Unrecoverable Error interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U) -/*! FNO - Frame Number Overflow interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U) -/*! RHSC - Root Hub Status Change interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U) -#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U) -/*! OC - Ownership Change interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U) -#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U) -/*! MIE - A 0 written to this field is ignored by HC. - */ -#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK) -/*! @} */ - -/*! @name HCHCCA - Contains the physical address of the host controller communication area */ -/*! @{ */ - -#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U) -#define USBFSH_HCHCCA_HCCA_SHIFT (8U) -/*! HCCA - Base address of the Host Controller Communication Area. - */ -#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK) -/*! @} */ - -/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */ -/*! @{ */ - -#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U) -/*! PCED - The content of this register is updated by HC after a periodic ED is processed. - */ -#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK) -/*! @} */ - -/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */ -/*! @{ */ - -#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U) -#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U) -/*! CHED - HC traverses the Control list starting with the HcControlHeadED pointer. - */ -#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK) -/*! @} */ - -/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */ -/*! @{ */ - -#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U) -/*! CCED - ControlCurrentED. - */ -#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK) -/*! @} */ - -/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */ -/*! @{ */ - -#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U) -#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U) -/*! BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer. - */ -#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK) -/*! @} */ - -/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */ -/*! @{ */ - -#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U) -/*! BCED - BulkCurrentED This is advanced to the next ED after the HC has served the current one. - */ -#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK) -/*! @} */ - -/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */ -/*! @{ */ - -#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U) -#define USBFSH_HCDONEHEAD_DH_SHIFT (4U) -/*! DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. - */ -#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK) -/*! @} */ - -/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */ -/*! @{ */ - -#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU) -#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U) -/*! FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times. - */ -#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK) - -#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U) -#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U) -/*! FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data - * Packet Counter at the beginning of each frame. - */ -#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK) - -#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U) -#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U) -/*! FIT - FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval. - */ -#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK) -/*! @} */ - -/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */ -/*! @{ */ - -#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU) -#define USBFSH_HCFMREMAINING_FR_SHIFT (0U) -/*! FR - FrameRemaining This counter is decremented at each bit time. - */ -#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK) - -#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U) -#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U) -/*! FRT - FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval - * whenever FrameRemaining reaches 0. - */ -#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK) -/*! @} */ - -/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */ -/*! @{ */ - -#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU) -#define USBFSH_HCFMNUMBER_FN_SHIFT (0U) -/*! FN - FrameNumber This is incremented when HcFmRemaining is re-loaded. - */ -#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK) -/*! @} */ - -/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */ -/*! @{ */ - -#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU) -#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U) -/*! PS - PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization. - */ -#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK) -/*! @} */ - -/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */ -/*! @{ */ - -#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU) -#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U) -/*! LST - LSThreshold This field contains a value which is compared to the FrameRemaining field - * prior to initiating a Low Speed transaction. - */ -#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK) -/*! @} */ - -/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */ -/*! @{ */ - -#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU) -#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U) -/*! NDP - NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub. - */ -#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK) - -#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U) -#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U) -/*! PSM - PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled. - */ -#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK) - -#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U) -#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U) -/*! NPS - NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered. - */ -#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK) - -#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U) -#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U) -/*! DT - DeviceType This bit specifies that the root hub is not a compound device. - */ -#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK) - -#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U) -#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U) -/*! OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported. - */ -#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK) - -#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U) -#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U) -/*! NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported. - */ -#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK) - -#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U) -#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U) -/*! POTPGT - PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before - * accessing a powered-on port of the root hub. - */ -#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK) -/*! @} */ - -/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */ -/*! @{ */ - -#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU) -#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U) -/*! DR - DeviceRemovable Each bit is dedicated to a port of the Root Hub. - */ -#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK) - -#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U) -#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U) -/*! PPCM - PortPowerControlMask Each bit indicates if a port is affected by a global power control - * command when PowerSwitchingMode is set. - */ -#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK) -/*! @} */ - -/*! @name HCRHSTATUS - This register is divided into two parts */ -/*! @{ */ - -#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U) -#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U) -/*! LPS - (read) LocalPowerStatus The Root Hub does not support the local power status feature; - * thus, this bit is always read as 0. - */ -#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK) - -#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U) -#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U) -/*! OCI - OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented. - */ -#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK) - -#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U) -#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U) -/*! DRWE - (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume - * event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected - * interrupt. - */ -#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK) - -#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U) -#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U) -/*! LPSC - (read) LocalPowerStatusChange The root hub does not support the local power status feature. - */ -#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK) - -#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U) -#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U) -/*! OCIC - OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register. - */ -#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK) - -#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U) -#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U) -/*! CRWE - (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable. - */ -#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK) -/*! @} */ - -/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */ -/*! @{ */ - -#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U) -#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U) -/*! CCS - (read) CurrentConnectStatus This bit reflects the current state of the downstream port. - */ -#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK) - -#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U) -#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U) -/*! PES - (read) PortEnableStatus This bit indicates whether the port is enabled or disabled. - */ -#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK) - -#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U) -#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U) -/*! PSS - (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence. - */ -#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK) - -#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U) -#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U) -/*! POCI - (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in - * such a way that overcurrent conditions are reported on a per-port basis. - */ -#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK) - -#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U) -#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U) -/*! PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. - */ -#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK) - -#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U) -#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U) -/*! PPS - (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type - * of power switching implemented. - */ -#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK) - -#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U) -#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U) -/*! LSDA - (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. - */ -#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK) - -#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U) -#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U) -/*! CSC - ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. - */ -#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK) - -#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U) -#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U) -/*! PESC - PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared. - */ -#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK) - -#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U) -#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U) -/*! PSSC - PortSuspendStatusChange This bit is set when the full resume sequence is completed. - */ -#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK) - -#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U) -#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U) -/*! OCIC - PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis. - */ -#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK) - -#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U) -#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U) -/*! PRSC - PortResetStatusChange This bit is set at the end of the 10 ms port reset signal. - */ -#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK) -/*! @} */ - -/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ -/*! @{ */ - -#define USBFSH_PORTMODE_ID_MASK (0x1U) -#define USBFSH_PORTMODE_ID_SHIFT (0U) -/*! ID - Port ID pin value. - */ -#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK) - -#define USBFSH_PORTMODE_ID_EN_MASK (0x100U) -#define USBFSH_PORTMODE_ID_EN_SHIFT (8U) -/*! ID_EN - Port ID pin pull-up enable. - */ -#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK) - -#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) -#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U) -/*! DEV_ENABLE - 1: device 0: host. - */ -#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBFSH_Register_Masks */ - - -/* USBFSH - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USBFSH base address */ - #define USBFSH_BASE (0x500A2000u) - /** Peripheral USBFSH base address */ - #define USBFSH_BASE_NS (0x400A2000u) - /** Peripheral USBFSH base pointer */ - #define USBFSH ((USBFSH_Type *)USBFSH_BASE) - /** Peripheral USBFSH base pointer */ - #define USBFSH_NS ((USBFSH_Type *)USBFSH_BASE_NS) - /** Array initializer of USBFSH peripheral base addresses */ - #define USBFSH_BASE_ADDRS { USBFSH_BASE } - /** Array initializer of USBFSH peripheral base pointers */ - #define USBFSH_BASE_PTRS { USBFSH } - /** Array initializer of USBFSH peripheral base addresses */ - #define USBFSH_BASE_ADDRS_NS { USBFSH_BASE_NS } - /** Array initializer of USBFSH peripheral base pointers */ - #define USBFSH_BASE_PTRS_NS { USBFSH_NS } -#else - /** Peripheral USBFSH base address */ - #define USBFSH_BASE (0x400A2000u) - /** Peripheral USBFSH base pointer */ - #define USBFSH ((USBFSH_Type *)USBFSH_BASE) - /** Array initializer of USBFSH peripheral base addresses */ - #define USBFSH_BASE_ADDRS { USBFSH_BASE } - /** Array initializer of USBFSH peripheral base pointers */ - #define USBFSH_BASE_PTRS { USBFSH } -#endif -/** Interrupt vectors for the USBFSH peripheral type */ -#define USBFSH_IRQS { USB0_IRQn } -#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBFSH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBHSD Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer - * @{ - */ - -/** USBHSD - Register Layout Typedef */ -typedef struct { - __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ - __I uint32_t INFO; /**< USB Info register, offset: 0x4 */ - __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ - __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ - __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ - __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ - __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ - __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ - __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ - __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ - __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ - uint8_t RESERVED_0[8]; - __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ -} USBHSD_Type; - -/* ---------------------------------------------------------------------------- - -- USBHSD Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSD_Register_Masks USBHSD Register Masks - * @{ - */ - -/*! @name DEVCMDSTAT - USB Device Command/Status register */ -/*! @{ */ - -#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) -#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) -/*! DEV_ADDR - USB device address. - */ -#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK) - -#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U) -#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U) -/*! DEV_EN - USB device enable. - */ -#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK) - -#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U) -#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U) -/*! SETUP - SETUP token received. - */ -#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK) - -#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) -#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) -/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:. - */ -#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK) - -#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U) -#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U) -/*! LPM_SUP - LPM Supported:. - */ -#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK) - -#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) -/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP:. - */ -#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK) - -#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) -/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP:. - */ -#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK) - -#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) -/*! INTONNAK_CO - Interrupt on NAK for control OUT EP:. - */ -#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK) - -#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) -/*! INTONNAK_CI - Interrupt on NAK for control IN EP:. - */ -#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK) - -#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U) -#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U) -/*! DCON - Device status - connect. - */ -#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK) - -#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U) -#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U) -/*! DSUS - Device status - suspend. - */ -#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK) - -#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) -#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U) -/*! LPM_SUS - Device status - LPM Suspend. - */ -#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK) - -#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) -#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U) -/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. - */ -#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK) - -#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U) -#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U) -/*! Speed - This field indicates the speed at which the device operates: 00b: reserved 01b: - * full-speed 10b: high-speed 11b: super-speed (reserved for future use). - */ -#define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK) - -#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U) -#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U) -/*! DCON_C - Device status - connect change. - */ -#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK) - -#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) -#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U) -/*! DSUS_C - Device status - suspend change. - */ -#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK) - -#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U) -#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U) -/*! DRES_C - Device status - reset change. - */ -#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK) - -#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U) -#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U) -/*! VBUS_DEBOUNCED - This bit indicates if VBUS is detected or not. - */ -#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK) - -#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U) -#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U) -/*! PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification. - * 0b000..Test mode disabled. - * 0b001..Test_J. - * 0b010..Test_K. - * 0b011..Test_SE0_NAK. - * 0b100..Test_Packet. - * 0b101..Test_Force_Enable. - */ -#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK) -/*! @} */ - -/*! @name INFO - USB Info register */ -/*! @{ */ - -#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU) -#define USBHSD_INFO_FRAME_NR_SHIFT (0U) -/*! FRAME_NR - Frame number. - */ -#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK) - -#define USBHSD_INFO_ERR_CODE_MASK (0x7800U) -#define USBHSD_INFO_ERR_CODE_SHIFT (11U) -/*! ERR_CODE - The error code which last occurred:. - */ -#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK) - -#define USBHSD_INFO_MINREV_MASK (0xFF0000U) -#define USBHSD_INFO_MINREV_SHIFT (16U) -/*! MINREV - Minor revision. - */ -#define USBHSD_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MINREV_SHIFT)) & USBHSD_INFO_MINREV_MASK) - -#define USBHSD_INFO_MAJREV_MASK (0xFF000000U) -#define USBHSD_INFO_MAJREV_SHIFT (24U) -/*! MAJREV - Major revision. - */ -#define USBHSD_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MAJREV_SHIFT)) & USBHSD_INFO_MAJREV_MASK) -/*! @} */ - -/*! @name EPLISTSTART - USB EP Command/Status List start address */ -/*! @{ */ - -#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U) -#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U) -/*! EP_LIST_PRG - Programmable portion of the USB EP Command/Status List address. - */ -#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK) - -#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U) -#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U) -/*! EP_LIST_FIXED - Fixed portion of USB EP Command/Status List address. - */ -#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK) -/*! @} */ - -/*! @name DATABUFSTART - USB Data buffer start address */ -/*! @{ */ - -#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU) -#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U) -/*! DA_BUF - Start address of the memory page where all endpoint data buffers are located. - */ -#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK) -/*! @} */ - -/*! @name LPM - USB Link Power Management register */ -/*! @{ */ - -#define USBHSD_LPM_HIRD_HW_MASK (0xFU) -#define USBHSD_LPM_HIRD_HW_SHIFT (0U) -/*! HIRD_HW - Host Initiated Resume Duration - HW. - */ -#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK) - -#define USBHSD_LPM_HIRD_SW_MASK (0xF0U) -#define USBHSD_LPM_HIRD_SW_SHIFT (4U) -/*! HIRD_SW - Host Initiated Resume Duration - SW. - */ -#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK) - -#define USBHSD_LPM_DATA_PENDING_MASK (0x100U) -#define USBHSD_LPM_DATA_PENDING_SHIFT (8U) -/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will - * return a NYET handshake on every LPM token it receives. - */ -#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK) -/*! @} */ - -/*! @name EPSKIP - USB Endpoint skip */ -/*! @{ */ - -#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU) -#define USBHSD_EPSKIP_SKIP_SHIFT (0U) -/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must - * deactivate the buffer assigned to this endpoint and return control back to software. - */ -#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK) -/*! @} */ - -/*! @name EPINUSE - USB Endpoint Buffer in use */ -/*! @{ */ - -#define USBHSD_EPINUSE_BUF_MASK (0xFFCU) -#define USBHSD_EPINUSE_BUF_SHIFT (2U) -/*! BUF - Buffer in use: This register has one bit per physical endpoint. - */ -#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK) -/*! @} */ - -/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ -/*! @{ */ - -#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU) -#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U) -/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. - */ -#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK) -/*! @} */ - -/*! @name INTSTAT - USB interrupt status register */ -/*! @{ */ - -#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U) -#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U) -/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. - */ -#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK) - -#define USBHSD_INTSTAT_EP0IN_MASK (0x2U) -#define USBHSD_INTSTAT_EP0IN_SHIFT (1U) -/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. - */ -#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK) - -#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U) -#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U) -/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. - */ -#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK) - -#define USBHSD_INTSTAT_EP1IN_MASK (0x8U) -#define USBHSD_INTSTAT_EP1IN_SHIFT (3U) -/*! EP1IN - Interrupt status register bit for the EP1 IN direction. - */ -#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK) - -#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U) -#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U) -/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. - */ -#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK) - -#define USBHSD_INTSTAT_EP2IN_MASK (0x20U) -#define USBHSD_INTSTAT_EP2IN_SHIFT (5U) -/*! EP2IN - Interrupt status register bit for the EP2 IN direction. - */ -#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK) - -#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U) -#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U) -/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. - */ -#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK) - -#define USBHSD_INTSTAT_EP3IN_MASK (0x80U) -#define USBHSD_INTSTAT_EP3IN_SHIFT (7U) -/*! EP3IN - Interrupt status register bit for the EP3 IN direction. - */ -#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK) - -#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U) -#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U) -/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. - */ -#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK) - -#define USBHSD_INTSTAT_EP4IN_MASK (0x200U) -#define USBHSD_INTSTAT_EP4IN_SHIFT (9U) -/*! EP4IN - Interrupt status register bit for the EP4 IN direction. - */ -#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK) - -#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U) -#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U) -/*! EP5OUT - Interrupt status register bit for the EP5 OUT direction. - */ -#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK) - -#define USBHSD_INTSTAT_EP5IN_MASK (0x800U) -#define USBHSD_INTSTAT_EP5IN_SHIFT (11U) -/*! EP5IN - Interrupt status register bit for the EP5 IN direction. - */ -#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK) - -#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U) -#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U) -/*! FRAME_INT - Frame interrupt. - */ -#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK) - -#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U) -#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U) -/*! DEV_INT - Device status interrupt. - */ -#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK) -/*! @} */ - -/*! @name INTEN - USB interrupt enable register */ -/*! @{ */ - -#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU) -#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U) -/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line. - */ -#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK) - -#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U) -#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U) -/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line. - */ -#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK) - -#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U) -#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U) -/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line. - */ -#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK) -/*! @} */ - -/*! @name INTSETSTAT - USB set interrupt status register */ -/*! @{ */ - -#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU) -#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U) -/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. - */ -#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK) - -#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) -#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) -/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. - */ -#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK) - -#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) -#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U) -/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. - */ -#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK) -/*! @} */ - -/*! @name EPTOGGLE - USB Endpoint toggle register */ -/*! @{ */ - -#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU) -#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U) -/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. - */ -#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBHSD_Register_Masks */ - - -/* USBHSD - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USBHSD base address */ - #define USBHSD_BASE (0x50094000u) - /** Peripheral USBHSD base address */ - #define USBHSD_BASE_NS (0x40094000u) - /** Peripheral USBHSD base pointer */ - #define USBHSD ((USBHSD_Type *)USBHSD_BASE) - /** Peripheral USBHSD base pointer */ - #define USBHSD_NS ((USBHSD_Type *)USBHSD_BASE_NS) - /** Array initializer of USBHSD peripheral base addresses */ - #define USBHSD_BASE_ADDRS { USBHSD_BASE } - /** Array initializer of USBHSD peripheral base pointers */ - #define USBHSD_BASE_PTRS { USBHSD } - /** Array initializer of USBHSD peripheral base addresses */ - #define USBHSD_BASE_ADDRS_NS { USBHSD_BASE_NS } - /** Array initializer of USBHSD peripheral base pointers */ - #define USBHSD_BASE_PTRS_NS { USBHSD_NS } -#else - /** Peripheral USBHSD base address */ - #define USBHSD_BASE (0x40094000u) - /** Peripheral USBHSD base pointer */ - #define USBHSD ((USBHSD_Type *)USBHSD_BASE) - /** Array initializer of USBHSD peripheral base addresses */ - #define USBHSD_BASE_ADDRS { USBHSD_BASE } - /** Array initializer of USBHSD peripheral base pointers */ - #define USBHSD_BASE_PTRS { USBHSD } -#endif -/** Interrupt vectors for the USBHSD peripheral type */ -#define USBHSD_IRQS { USB1_IRQn } -#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBHSD_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBHSH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer - * @{ - */ - -/** USBHSH - Register Layout Typedef */ -typedef struct { - __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */ - __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */ - __IO uint32_t ATLPTD; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */ - __IO uint32_t ISOPTD; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */ - __IO uint32_t INTPTD; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */ - __IO uint32_t DATAPAYLOAD; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */ - __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */ - __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */ - __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */ - __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */ - __IO uint32_t ATLPTDD; /**< Done map for each ATL PTD, offset: 0x30 */ - __IO uint32_t ATLPTDS; /**< Skip map for each ATL PTD, offset: 0x34 */ - __IO uint32_t ISOPTDD; /**< Done map for each ISO PTD, offset: 0x38 */ - __IO uint32_t ISOPTDS; /**< Skip map for each ISO PTD, offset: 0x3C */ - __IO uint32_t INTPTDD; /**< Done map for each INT PTD, offset: 0x40 */ - __IO uint32_t INTPTDS; /**< Skip map for each INT PTD, offset: 0x44 */ - __IO uint32_t LASTPTD; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */ - uint8_t RESERVED_1[4]; - __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */ -} USBHSH_Type; - -/* ---------------------------------------------------------------------------- - -- USBHSH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSH_Register_Masks USBHSH Register Masks - * @{ - */ - -/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */ -/*! @{ */ - -#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU) -#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U) -/*! CAPLENGTH - Capability Length: This is used as an offset. - */ -#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK) - -#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U) -#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U) -/*! CHIPID - Chip identification: indicates major and minor revision of the IP: [31:24] = Major - * revision [23:16] = Minor revision Major revisions used: 0x01: USB2. - */ -#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK) -/*! @} */ - -/*! @name HCSPARAMS - Host Controller Structural Parameters */ -/*! @{ */ - -#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU) -#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U) -/*! N_PORTS - This register specifies the number of physical downstream ports implemented on this host controller. - */ -#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK) - -#define USBHSH_HCSPARAMS_PPC_MASK (0x10U) -#define USBHSH_HCSPARAMS_PPC_SHIFT (4U) -/*! PPC - This field indicates whether the host controller implementation includes port power control. - */ -#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK) - -#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U) -#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U) -/*! P_INDICATOR - This bit indicates whether the ports support port indicator control. - */ -#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK) -/*! @} */ - -/*! @name FLADJ_FRINDEX - Frame Length Adjustment */ -/*! @{ */ - -#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU) -#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U) -/*! FLADJ - Frame Length Timing Value. - */ -#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK) - -#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U) -#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U) -/*! FRINDEX - Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet. - */ -#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) -/*! @} */ - -/*! @name ATLPTD - Memory base address where ATL PTD0 is stored */ -/*! @{ */ - -#define USBHSH_ATLPTD_ATL_CUR_MASK (0x1F0U) -#define USBHSH_ATLPTD_ATL_CUR_SHIFT (4U) -/*! ATL_CUR - This indicates the current PTD that is used by the hardware when it is processing the ATL list. - */ -#define USBHSH_ATLPTD_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_CUR_SHIFT)) & USBHSH_ATLPTD_ATL_CUR_MASK) - -#define USBHSH_ATLPTD_ATL_BASE_MASK (0xFFFFFE00U) -#define USBHSH_ATLPTD_ATL_BASE_SHIFT (9U) -/*! ATL_BASE - Base address to be used by the hardware to find the start of the ATL list. - */ -#define USBHSH_ATLPTD_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_BASE_SHIFT)) & USBHSH_ATLPTD_ATL_BASE_MASK) -/*! @} */ - -/*! @name ISOPTD - Memory base address where ISO PTD0 is stored */ -/*! @{ */ - -#define USBHSH_ISOPTD_ISO_FIRST_MASK (0x3E0U) -#define USBHSH_ISOPTD_ISO_FIRST_SHIFT (5U) -/*! ISO_FIRST - This indicates the first PTD that is used by the hardware when it is processing the ISO list. - */ -#define USBHSH_ISOPTD_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_FIRST_SHIFT)) & USBHSH_ISOPTD_ISO_FIRST_MASK) - -#define USBHSH_ISOPTD_ISO_BASE_MASK (0xFFFFFC00U) -#define USBHSH_ISOPTD_ISO_BASE_SHIFT (10U) -/*! ISO_BASE - Base address to be used by the hardware to find the start of the ISO list. - */ -#define USBHSH_ISOPTD_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_BASE_SHIFT)) & USBHSH_ISOPTD_ISO_BASE_MASK) -/*! @} */ - -/*! @name INTPTD - Memory base address where INT PTD0 is stored */ -/*! @{ */ - -#define USBHSH_INTPTD_INT_FIRST_MASK (0x3E0U) -#define USBHSH_INTPTD_INT_FIRST_SHIFT (5U) -/*! INT_FIRST - This indicates the first PTD that is used by the hardware when it is processing the INT list. - */ -#define USBHSH_INTPTD_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_FIRST_SHIFT)) & USBHSH_INTPTD_INT_FIRST_MASK) - -#define USBHSH_INTPTD_INT_BASE_MASK (0xFFFFFC00U) -#define USBHSH_INTPTD_INT_BASE_SHIFT (10U) -/*! INT_BASE - Base address to be used by the hardware to find the start of the INT list. - */ -#define USBHSH_INTPTD_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_BASE_SHIFT)) & USBHSH_INTPTD_INT_BASE_MASK) -/*! @} */ - -/*! @name DATAPAYLOAD - Memory base address that indicates the start of the data payload buffers */ -/*! @{ */ - -#define USBHSH_DATAPAYLOAD_DAT_BASE_MASK (0xFFFF0000U) -#define USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT (16U) -/*! DAT_BASE - Base address to be used by the hardware to find the start of the data payload section. - */ -#define USBHSH_DATAPAYLOAD_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT)) & USBHSH_DATAPAYLOAD_DAT_BASE_MASK) -/*! @} */ - -/*! @name USBCMD - USB Command register */ -/*! @{ */ - -#define USBHSH_USBCMD_RS_MASK (0x1U) -#define USBHSH_USBCMD_RS_SHIFT (0U) -/*! RS - Run/Stop: 1b = Run. - */ -#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK) - -#define USBHSH_USBCMD_HCRESET_MASK (0x2U) -#define USBHSH_USBCMD_HCRESET_SHIFT (1U) -/*! HCRESET - Host Controller Reset: This control bit is used by the software to reset the host controller. - */ -#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK) - -#define USBHSH_USBCMD_FLS_MASK (0xCU) -#define USBHSH_USBCMD_FLS_SHIFT (2U) -/*! FLS - Frame List Size: This field specifies the size of the frame list. - */ -#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK) - -#define USBHSH_USBCMD_LHCR_MASK (0x80U) -#define USBHSH_USBCMD_LHCR_SHIFT (7U) -/*! LHCR - Light Host Controller Reset: This bit allows the driver software to reset the host - * controller without affecting the state of the ports. - */ -#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK) - -#define USBHSH_USBCMD_ATL_EN_MASK (0x100U) -#define USBHSH_USBCMD_ATL_EN_SHIFT (8U) -/*! ATL_EN - ATL List enabled. - */ -#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK) - -#define USBHSH_USBCMD_ISO_EN_MASK (0x200U) -#define USBHSH_USBCMD_ISO_EN_SHIFT (9U) -/*! ISO_EN - ISO List enabled. - */ -#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK) - -#define USBHSH_USBCMD_INT_EN_MASK (0x400U) -#define USBHSH_USBCMD_INT_EN_SHIFT (10U) -/*! INT_EN - INT List enabled. - */ -#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK) -/*! @} */ - -/*! @name USBSTS - USB Interrupt Status register */ -/*! @{ */ - -#define USBHSH_USBSTS_PCD_MASK (0x4U) -#define USBHSH_USBSTS_PCD_SHIFT (2U) -/*! PCD - Port Change Detect: The host controller sets this bit to logic 1 when any port has a - * change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a - * result of a J-K transition detected on a suspended port. - */ -#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK) - -#define USBHSH_USBSTS_FLR_MASK (0x8U) -#define USBHSH_USBSTS_FLR_SHIFT (3U) -/*! FLR - Frame List Rollover: The host controller sets this bit to logic 1 when the frame list - * index rolls over its maximum value to 0. - */ -#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK) - -#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U) -#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U) -/*! ATL_IRQ - ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed. - */ -#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK) - -#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U) -#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U) -/*! ISO_IRQ - ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed. - */ -#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK) - -#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U) -#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U) -/*! INT_IRQ - INT IRQ: Indicates that an INT PTD (with I-bit set) was completed. - */ -#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK) - -#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U) -#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U) -/*! SOF_IRQ - SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set. - */ -#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK) -/*! @} */ - -/*! @name USBINTR - USB Interrupt Enable register */ -/*! @{ */ - -#define USBHSH_USBINTR_PCDE_MASK (0x4U) -#define USBHSH_USBINTR_PCDE_SHIFT (2U) -/*! PCDE - Port Change Detect Interrupt Enable: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK) - -#define USBHSH_USBINTR_FLRE_MASK (0x8U) -#define USBHSH_USBINTR_FLRE_SHIFT (3U) -/*! FLRE - Frame List Rollover Interrupt Enable: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK) - -#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U) -#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U) -/*! ATL_IRQ_E - ATL IRQ Enable bit: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK) - -#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U) -#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U) -/*! ISO_IRQ_E - ISO IRQ Enable bit: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK) - -#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U) -#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U) -/*! INT_IRQ_E - INT IRQ Enable bit: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK) - -#define USBHSH_USBINTR_SOF_E_MASK (0x80000U) -#define USBHSH_USBINTR_SOF_E_SHIFT (19U) -/*! SOF_E - SOF Interrupt Enable bit: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK) -/*! @} */ - -/*! @name PORTSC1 - Port Status and Control register */ -/*! @{ */ - -#define USBHSH_PORTSC1_CCS_MASK (0x1U) -#define USBHSH_PORTSC1_CCS_SHIFT (0U) -/*! CCS - Current Connect Status: Logic 1 indicates a device is present on the port. - */ -#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK) - -#define USBHSH_PORTSC1_CSC_MASK (0x2U) -#define USBHSH_PORTSC1_CSC_SHIFT (1U) -/*! CSC - Connect Status Change: Logic 1 means that the value of CCS has changed. - */ -#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK) - -#define USBHSH_PORTSC1_PED_MASK (0x4U) -#define USBHSH_PORTSC1_PED_SHIFT (2U) -/*! PED - Port Enabled/Disabled. - */ -#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK) - -#define USBHSH_PORTSC1_PEDC_MASK (0x8U) -#define USBHSH_PORTSC1_PEDC_SHIFT (3U) -/*! PEDC - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed. - */ -#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK) - -#define USBHSH_PORTSC1_OCA_MASK (0x10U) -#define USBHSH_PORTSC1_OCA_SHIFT (4U) -/*! OCA - Over-current active: Logic 1 means that this port has an over-current condition. - */ -#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK) - -#define USBHSH_PORTSC1_OCC_MASK (0x20U) -#define USBHSH_PORTSC1_OCC_SHIFT (5U) -/*! OCC - Over-current change: Logic 1 means that the value of OCA has changed. - */ -#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK) - -#define USBHSH_PORTSC1_FPR_MASK (0x40U) -#define USBHSH_PORTSC1_FPR_SHIFT (6U) -/*! FPR - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port. - */ -#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK) - -#define USBHSH_PORTSC1_SUSP_MASK (0x80U) -#define USBHSH_PORTSC1_SUSP_SHIFT (7U) -/*! SUSP - Suspend: Logic 1 means port is in the suspend state. - */ -#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK) - -#define USBHSH_PORTSC1_PR_MASK (0x100U) -#define USBHSH_PORTSC1_PR_SHIFT (8U) -/*! PR - Port Reset: Logic 1 means the port is in the reset state. - */ -#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK) - -#define USBHSH_PORTSC1_LS_MASK (0xC00U) -#define USBHSH_PORTSC1_LS_SHIFT (10U) -/*! LS - Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. - */ -#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK) - -#define USBHSH_PORTSC1_PP_MASK (0x1000U) -#define USBHSH_PORTSC1_PP_SHIFT (12U) -/*! PP - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register. - */ -#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK) - -#define USBHSH_PORTSC1_PIC_MASK (0xC000U) -#define USBHSH_PORTSC1_PIC_SHIFT (14U) -/*! PIC - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the - * HCSPARAMS register is logic 0. - */ -#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK) - -#define USBHSH_PORTSC1_PTC_MASK (0xF0000U) -#define USBHSH_PORTSC1_PTC_SHIFT (16U) -/*! PTC - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value. - */ -#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK) - -#define USBHSH_PORTSC1_PSPD_MASK (0x300000U) -#define USBHSH_PORTSC1_PSPD_SHIFT (20U) -/*! PSPD - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved. - */ -#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK) - -#define USBHSH_PORTSC1_WOO_MASK (0x400000U) -#define USBHSH_PORTSC1_WOO_SHIFT (22U) -/*! WOO - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to - * overcurrent conditions as wake-up events. - */ -#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK) -/*! @} */ - -/*! @name ATLPTDD - Done map for each ATL PTD */ -/*! @{ */ - -#define USBHSH_ATLPTDD_ATL_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_ATLPTDD_ATL_DONE_SHIFT (0U) -/*! ATL_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - */ -#define USBHSH_ATLPTDD_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDD_ATL_DONE_SHIFT)) & USBHSH_ATLPTDD_ATL_DONE_MASK) -/*! @} */ - -/*! @name ATLPTDS - Skip map for each ATL PTD */ -/*! @{ */ - -#define USBHSH_ATLPTDS_ATL_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_ATLPTDS_ATL_SKIP_SHIFT (0U) -/*! ATL_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be - * skipped, independent of the V bit setting. - */ -#define USBHSH_ATLPTDS_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDS_ATL_SKIP_SHIFT)) & USBHSH_ATLPTDS_ATL_SKIP_MASK) -/*! @} */ - -/*! @name ISOPTDD - Done map for each ISO PTD */ -/*! @{ */ - -#define USBHSH_ISOPTDD_ISO_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_ISOPTDD_ISO_DONE_SHIFT (0U) -/*! ISO_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - */ -#define USBHSH_ISOPTDD_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDD_ISO_DONE_SHIFT)) & USBHSH_ISOPTDD_ISO_DONE_MASK) -/*! @} */ - -/*! @name ISOPTDS - Skip map for each ISO PTD */ -/*! @{ */ - -#define USBHSH_ISOPTDS_ISO_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_ISOPTDS_ISO_SKIP_SHIFT (0U) -/*! ISO_SKIP - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - */ -#define USBHSH_ISOPTDS_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDS_ISO_SKIP_SHIFT)) & USBHSH_ISOPTDS_ISO_SKIP_MASK) -/*! @} */ - -/*! @name INTPTDD - Done map for each INT PTD */ -/*! @{ */ - -#define USBHSH_INTPTDD_INT_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_INTPTDD_INT_DONE_SHIFT (0U) -/*! INT_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - */ -#define USBHSH_INTPTDD_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDD_INT_DONE_SHIFT)) & USBHSH_INTPTDD_INT_DONE_MASK) -/*! @} */ - -/*! @name INTPTDS - Skip map for each INT PTD */ -/*! @{ */ - -#define USBHSH_INTPTDS_INT_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_INTPTDS_INT_SKIP_SHIFT (0U) -/*! INT_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be - * skipped, independent of the V bit setting. - */ -#define USBHSH_INTPTDS_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDS_INT_SKIP_SHIFT)) & USBHSH_INTPTDS_INT_SKIP_MASK) -/*! @} */ - -/*! @name LASTPTD - Marks the last PTD in the list for ISO, INT and ATL */ -/*! @{ */ - -#define USBHSH_LASTPTD_ATL_LAST_MASK (0x1FU) -#define USBHSH_LASTPTD_ATL_LAST_SHIFT (0U) -/*! ATL_LAST - If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed. - */ -#define USBHSH_LASTPTD_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ATL_LAST_SHIFT)) & USBHSH_LASTPTD_ATL_LAST_MASK) - -#define USBHSH_LASTPTD_ISO_LAST_MASK (0x1F00U) -#define USBHSH_LASTPTD_ISO_LAST_SHIFT (8U) -/*! ISO_LAST - This indicates the last PTD in the ISO list. - */ -#define USBHSH_LASTPTD_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ISO_LAST_SHIFT)) & USBHSH_LASTPTD_ISO_LAST_MASK) - -#define USBHSH_LASTPTD_INT_LAST_MASK (0x1F0000U) -#define USBHSH_LASTPTD_INT_LAST_SHIFT (16U) -/*! INT_LAST - This indicates the last PTD in the INT list. - */ -#define USBHSH_LASTPTD_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_INT_LAST_SHIFT)) & USBHSH_LASTPTD_INT_LAST_MASK) -/*! @} */ - -/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ -/*! @{ */ - -#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) -#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U) -/*! DEV_ENABLE - If this bit is set to one, one of the ports will behave as a USB device. - */ -#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK) - -#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U) -#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U) -/*! SW_CTRL_PDCOM - This bit indicates if the PHY power-down input is controlled by software or by hardware. - */ -#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK) - -#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U) -#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U) -/*! SW_PDCOM - This bit is only used when SW_CTRL_PDCOM is set to 1b. - */ -#define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBHSH_Register_Masks */ - - -/* USBHSH - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USBHSH base address */ - #define USBHSH_BASE (0x500A3000u) - /** Peripheral USBHSH base address */ - #define USBHSH_BASE_NS (0x400A3000u) - /** Peripheral USBHSH base pointer */ - #define USBHSH ((USBHSH_Type *)USBHSH_BASE) - /** Peripheral USBHSH base pointer */ - #define USBHSH_NS ((USBHSH_Type *)USBHSH_BASE_NS) - /** Array initializer of USBHSH peripheral base addresses */ - #define USBHSH_BASE_ADDRS { USBHSH_BASE } - /** Array initializer of USBHSH peripheral base pointers */ - #define USBHSH_BASE_PTRS { USBHSH } - /** Array initializer of USBHSH peripheral base addresses */ - #define USBHSH_BASE_ADDRS_NS { USBHSH_BASE_NS } - /** Array initializer of USBHSH peripheral base pointers */ - #define USBHSH_BASE_PTRS_NS { USBHSH_NS } -#else - /** Peripheral USBHSH base address */ - #define USBHSH_BASE (0x400A3000u) - /** Peripheral USBHSH base pointer */ - #define USBHSH ((USBHSH_Type *)USBHSH_BASE) - /** Array initializer of USBHSH peripheral base addresses */ - #define USBHSH_BASE_ADDRS { USBHSH_BASE } - /** Array initializer of USBHSH peripheral base pointers */ - #define USBHSH_BASE_PTRS { USBHSH } -#endif -/** Interrupt vectors for the USBHSH peripheral type */ -#define USBHSH_IRQS { USB1_IRQn } -#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBHSH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBPHY Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer - * @{ - */ - -/** USBPHY - Register Layout Typedef */ -typedef struct { - __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ - __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ - __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ - __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ - __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ - __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ - __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ - __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ - __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ - __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ - __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ - __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ - __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ - __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ - __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ - __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ - __I uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ - uint8_t RESERVED_0[92]; - __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */ - __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */ - __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */ - __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */ - uint8_t RESERVED_1[16]; - __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */ - __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */ - __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */ - __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */ - uint8_t RESERVED_2[48]; - __IO uint32_t ANACTRLr; /**< USB PHY Analog Control Register, offset: 0x100 */ - __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */ - __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */ - __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */ -} USBPHY_Type; - -/* ---------------------------------------------------------------------------- - -- USBPHY Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBPHY_Register_Masks USBPHY Register Masks - * @{ - */ - -/*! @name PWD - USB PHY Power-Down Register */ -/*! @{ */ - -#define USBPHY_PWD_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) - -#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) - -#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) - -#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) - -#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) - -#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) - -#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) -/*! @} */ - -/*! @name PWD_SET - USB PHY Power-Down Register */ -/*! @{ */ - -#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) - -#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) - -#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) - -#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) - -#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) - -#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) - -#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) -/*! @} */ - -/*! @name PWD_CLR - USB PHY Power-Down Register */ -/*! @{ */ - -#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) - -#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) - -#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) - -#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) - -#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) - -#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) - -#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) -/*! @} */ - -/*! @name PWD_TOG - USB PHY Power-Down Register */ -/*! @{ */ - -#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) - -#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) - -#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) - -#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) - -#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) - -#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) - -#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) -/*! @} */ - -/*! @name TX - USB PHY Transmitter Control Register */ -/*! @{ */ - -#define USBPHY_TX_D_CAL_MASK (0xFU) -#define USBPHY_TX_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) - -#define USBPHY_TX_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK) - -#define USBPHY_TX_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DN_SHIFT)) & USBPHY_TX_TXENCAL45DN_MASK) - -#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) - -#define USBPHY_TX_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name TX_SET - USB PHY Transmitter Control Register */ -/*! @{ */ - -#define USBPHY_TX_SET_D_CAL_MASK (0xFU) -#define USBPHY_TX_SET_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) - -#define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK) - -#define USBPHY_TX_SET_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_SET_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_SET_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DN_SHIFT)) & USBPHY_TX_SET_TXENCAL45DN_MASK) - -#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) - -#define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_SET_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name TX_CLR - USB PHY Transmitter Control Register */ -/*! @{ */ - -#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) -#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) - -#define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK) - -#define USBPHY_TX_CLR_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_CLR_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_CLR_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DN_MASK) - -#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) - -#define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_CLR_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name TX_TOG - USB PHY Transmitter Control Register */ -/*! @{ */ - -#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) -#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) - -#define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK) - -#define USBPHY_TX_TOG_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_TOG_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_TOG_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DN_MASK) - -#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) - -#define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_TOG_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name RX - USB PHY Receiver Control Register */ -/*! @{ */ - -#define USBPHY_RX_ENVADJ_MASK (0x7U) -#define USBPHY_RX_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) - -#define USBPHY_RX_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) - -#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) -/*! @} */ - -/*! @name RX_SET - USB PHY Receiver Control Register */ -/*! @{ */ - -#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) -#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) - -#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) - -#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) -/*! @} */ - -/*! @name RX_CLR - USB PHY Receiver Control Register */ -/*! @{ */ - -#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) -#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) - -#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) - -#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) -/*! @} */ - -/*! @name RX_TOG - USB PHY Receiver Control Register */ -/*! @{ */ - -#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) -#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) - -#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) - -#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) -/*! @} */ - -/*! @name CTRL - USB PHY General Control Register */ -/*! @{ */ - -#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) - -#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) -#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) -#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) - -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) - -#define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK) - -#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) -#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) -#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) - -#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) -#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) -#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) - -#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) -#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) -#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) - -#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) -#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) -#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) - -#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) - -#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) - -#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) - -#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) -#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) -#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) - -#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) -#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) -#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) - -#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) - -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) - -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) - -#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) -#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) -#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) - -#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) -#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) -#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) - -#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) -#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT (25U) -#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK) - -#define USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK (0x4000000U) -#define USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT (26U) -#define USBPHY_CTRL_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK) - -#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) - -#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) - -#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) - -#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_SET - USB PHY General Control Register */ -/*! @{ */ - -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) - -#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) -#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) -#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) - -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) - -#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK) - -#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) -#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) -#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) - -#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) -#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) -#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) - -#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) -#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) -#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) - -#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) -#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) -#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) - -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) - -#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) - -#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) - -#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) -#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) -#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) - -#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) -#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) -#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) - -#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) - -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) - -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) - -#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) -#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) -#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) - -#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) -#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) -#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) - -#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) -#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT (25U) -#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK) - -#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK (0x4000000U) -#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT (26U) -#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK) - -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) - -#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) - -#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) - -#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_CLR - USB PHY General Control Register */ -/*! @{ */ - -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) - -#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) -#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) -#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) - -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) - -#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK) - -#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) - -#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) -#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) -#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) - -#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) -#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) -#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) - -#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) -#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) -#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) - -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) - -#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) - -#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) - -#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) -#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) -#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) - -#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) -#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) -#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) - -#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) - -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) - -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) - -#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) -#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) -#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) - -#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) -#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) -#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) - -#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT (25U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK) - -#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK (0x4000000U) -#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT (26U) -#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK) - -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) - -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) - -#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) - -#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_TOG - USB PHY General Control Register */ -/*! @{ */ - -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) - -#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) -#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) -#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) - -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) - -#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK) - -#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) - -#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) -#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) -#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) - -#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) -#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) -#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) - -#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) -#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) -#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) - -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) - -#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) - -#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) - -#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) -#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) -#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) - -#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) -#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) -#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) - -#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) - -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) - -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) - -#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) -#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) -#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) - -#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) -#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) -#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) - -#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT (25U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK) - -#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK (0x4000000U) -#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT (26U) -#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK) - -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) - -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) - -#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) - -#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) -/*! @} */ - -/*! @name STATUS - USB PHY Status Register */ -/*! @{ */ - -#define USBPHY_STATUS_OK_STATUS_3V_MASK (0x1U) -#define USBPHY_STATUS_OK_STATUS_3V_SHIFT (0U) -#define USBPHY_STATUS_OK_STATUS_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OK_STATUS_3V_SHIFT)) & USBPHY_STATUS_OK_STATUS_3V_MASK) - -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) -/*! HOSTDISCONDETECT_STATUS - * 0b0..USB cable disconnect has not been detected at the local host - * 0b1..USB cable disconnect has been detected at the local host - */ -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) - -#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) -#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) -/*! DEVPLUGIN_STATUS - * 0b0..No attachment to a USB host is detected - * 0b1..Cable attachment to a USB host is detected - */ -#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) - -#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) -#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) -#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) -/*! @} */ - -/*! @name PLL_SIC - USB PHY PLL Control/Status Register */ -/*! @{ */ - -#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) - -#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) - -#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) - -#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) - -#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) - -#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) - -#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) - -#define USBPHY_PLL_SIC_PLL_PREDIV_MASK (0x40000000U) -#define USBPHY_PLL_SIC_PLL_PREDIV_SHIFT (30U) -#define USBPHY_PLL_SIC_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_PREDIV_MASK) - -#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */ -/*! @{ */ - -#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) - -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) - -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK (0x40000000U) -#define USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT (30U) -#define USBPHY_PLL_SIC_SET_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */ -/*! @{ */ - -#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) - -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) - -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK (0x40000000U) -#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT (30U) -#define USBPHY_PLL_SIC_CLR_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */ -/*! @{ */ - -#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) - -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) - -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK (0x40000000U) -#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT (30U) -#define USBPHY_PLL_SIC_TOG_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */ -/*! @{ */ - -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U) -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U) -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U) -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U) -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK (0x2000U) -#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. - * 0b1..Select the external ID value. - */ -#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) -#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. - * 0b1..Select the external VBUS VALID value. - */ -#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK (0x80000U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT (19U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK) - -#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x700000U) -#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b000..Powers down the VBUS_VALID comparator - * 0b111..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK) - -#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */ -/*! @{ */ - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U) -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U) -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U) -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U) -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK (0x2000U) -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. - * 0b1..Select the external ID value. - */ -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. - * 0b1..Select the external VBUS VALID value. - */ -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK (0x80000U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT (19U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U) -#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b000..Powers down the VBUS_VALID comparator - * 0b111..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */ -/*! @{ */ - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U) -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U) -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U) -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK (0x2000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. - * 0b1..Select the external ID value. - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - * 0b0..Select the muxed value chosen using VBUS_OVERRIDE_EN. - * 0b1..Select the external VBUS VALID value. - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK (0x80000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT (19U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b000..Powers down the VBUS_VALID comparator - * 0b111..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */ -/*! @{ */ - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U) -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U) -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U) -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK (0x2000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - * 0b0..Select the muxed value chosen using ID_OVERRIDE_EN. - * 0b1..Select the external ID value. - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. - * 0b1..Select the external VBUS VALID value. - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK (0x80000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT (19U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b000..Powers down the VBUS_VALID comparator - * 0b111..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) -/*! @} */ - -/*! @name ANACTRL - USB PHY Analog Control Register */ -/*! @{ */ - -#define USBPHY_ANACTRL_LVI_EN_MASK (0x2U) -#define USBPHY_ANACTRL_LVI_EN_SHIFT (1U) -#define USBPHY_ANACTRL_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_LVI_EN_SHIFT)) & USBPHY_ANACTRL_LVI_EN_MASK) - -#define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU) -#define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U) -#define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) - -#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) -/*! @} */ - -/*! @name ANACTRL_SET - USB PHY Analog Control Register */ -/*! @{ */ - -#define USBPHY_ANACTRL_SET_LVI_EN_MASK (0x2U) -#define USBPHY_ANACTRL_SET_LVI_EN_SHIFT (1U) -#define USBPHY_ANACTRL_SET_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_LVI_EN_SHIFT)) & USBPHY_ANACTRL_SET_LVI_EN_MASK) - -#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU) -#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U) -#define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK) - -#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) -/*! @} */ - -/*! @name ANACTRL_CLR - USB PHY Analog Control Register */ -/*! @{ */ - -#define USBPHY_ANACTRL_CLR_LVI_EN_MASK (0x2U) -#define USBPHY_ANACTRL_CLR_LVI_EN_SHIFT (1U) -#define USBPHY_ANACTRL_CLR_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_LVI_EN_SHIFT)) & USBPHY_ANACTRL_CLR_LVI_EN_MASK) - -#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU) -#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U) -#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK) - -#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) -/*! @} */ - -/*! @name ANACTRL_TOG - USB PHY Analog Control Register */ -/*! @{ */ - -#define USBPHY_ANACTRL_TOG_LVI_EN_MASK (0x2U) -#define USBPHY_ANACTRL_TOG_LVI_EN_SHIFT (1U) -#define USBPHY_ANACTRL_TOG_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_LVI_EN_SHIFT)) & USBPHY_ANACTRL_TOG_LVI_EN_MASK) - -#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU) -#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U) -#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK) - -#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBPHY_Register_Masks */ - - -/* USBPHY - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USBPHY base address */ - #define USBPHY_BASE (0x50038000u) - /** Peripheral USBPHY base address */ - #define USBPHY_BASE_NS (0x40038000u) - /** Peripheral USBPHY base pointer */ - #define USBPHY ((USBPHY_Type *)USBPHY_BASE) - /** Peripheral USBPHY base pointer */ - #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) - /** Array initializer of USBPHY peripheral base addresses */ - #define USBPHY_BASE_ADDRS { USBPHY_BASE } - /** Array initializer of USBPHY peripheral base pointers */ - #define USBPHY_BASE_PTRS { USBPHY } - /** Array initializer of USBPHY peripheral base addresses */ - #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } - /** Array initializer of USBPHY peripheral base pointers */ - #define USBPHY_BASE_PTRS_NS { USBPHY_NS } -#else - /** Peripheral USBPHY base address */ - #define USBPHY_BASE (0x40038000u) - /** Peripheral USBPHY base pointer */ - #define USBPHY ((USBPHY_Type *)USBPHY_BASE) - /** Array initializer of USBPHY peripheral base addresses */ - #define USBPHY_BASE_ADDRS { USBPHY_BASE } - /** Array initializer of USBPHY peripheral base pointers */ - #define USBPHY_BASE_PTRS { USBPHY } -#endif -/** Interrupt vectors for the USBPHY peripheral type */ -#define USBPHY_IRQS { USB1_PHY_IRQn } - -/*! - * @} - */ /* end of group USBPHY_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- UTICK Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer - * @{ - */ - -/** UTICK - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ - __IO uint32_t STAT; /**< Status register., offset: 0x4 */ - __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ - __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ - __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ -} UTICK_Type; - -/* ---------------------------------------------------------------------------- - -- UTICK Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Register_Masks UTICK Register Masks - * @{ - */ - -/*! @name CTRL - Control register. */ -/*! @{ */ - -#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) -#define UTICK_CTRL_DELAYVAL_SHIFT (0U) -/*! DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer - * clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer. - */ -#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) - -#define UTICK_CTRL_REPEAT_MASK (0x80000000U) -#define UTICK_CTRL_REPEAT_SHIFT (31U) -/*! REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. - */ -#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) -/*! @} */ - -/*! @name STAT - Status register. */ -/*! @{ */ - -#define UTICK_STAT_INTR_MASK (0x1U) -#define UTICK_STAT_INTR_SHIFT (0U) -/*! INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any - * value to this register clears this flag. - */ -#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) - -#define UTICK_STAT_ACTIVE_MASK (0x2U) -#define UTICK_STAT_ACTIVE_SHIFT (1U) -/*! ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. - */ -#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) -/*! @} */ - -/*! @name CFG - Capture configuration register. */ -/*! @{ */ - -#define UTICK_CFG_CAPEN0_MASK (0x1U) -#define UTICK_CFG_CAPEN0_SHIFT (0U) -/*! CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled. - */ -#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) - -#define UTICK_CFG_CAPEN1_MASK (0x2U) -#define UTICK_CFG_CAPEN1_SHIFT (1U) -/*! CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled. - */ -#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) - -#define UTICK_CFG_CAPEN2_MASK (0x4U) -#define UTICK_CFG_CAPEN2_SHIFT (2U) -/*! CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled. - */ -#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) - -#define UTICK_CFG_CAPEN3_MASK (0x8U) -#define UTICK_CFG_CAPEN3_SHIFT (3U) -/*! CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled. - */ -#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) - -#define UTICK_CFG_CAPPOL0_MASK (0x100U) -#define UTICK_CFG_CAPPOL0_SHIFT (8U) -/*! CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. - */ -#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) - -#define UTICK_CFG_CAPPOL1_MASK (0x200U) -#define UTICK_CFG_CAPPOL1_SHIFT (9U) -/*! CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. - */ -#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) - -#define UTICK_CFG_CAPPOL2_MASK (0x400U) -#define UTICK_CFG_CAPPOL2_SHIFT (10U) -/*! CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. - */ -#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) - -#define UTICK_CFG_CAPPOL3_MASK (0x800U) -#define UTICK_CFG_CAPPOL3_SHIFT (11U) -/*! CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. - */ -#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) -/*! @} */ - -/*! @name CAPCLR - Capture clear register. */ -/*! @{ */ - -#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) -#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) -/*! CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value. - */ -#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) - -#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) -#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) -/*! CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value. - */ -#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) - -#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) -#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) -/*! CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value. - */ -#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) - -#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) -#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) -/*! CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value. - */ -#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) -/*! @} */ - -/*! @name CAP - Capture register . */ -/*! @{ */ - -#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) -#define UTICK_CAP_CAP_VALUE_SHIFT (0U) -/*! CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower - * than the actual value of the Micro-tick Timer at the moment of the capture event. - */ -#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) - -#define UTICK_CAP_VALID_MASK (0x80000000U) -#define UTICK_CAP_VALID_SHIFT (31U) -/*! VALID - Capture Valid. When 1, a value has been captured based on a transition of the related - * UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. - */ -#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) -/*! @} */ - -/* The count of UTICK_CAP */ -#define UTICK_CAP_COUNT (4U) - - -/*! - * @} - */ /* end of group UTICK_Register_Masks */ - - -/* UTICK - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE (0x5000E000u) - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE_NS (0x4000E000u) - /** Peripheral UTICK0 base pointer */ - #define UTICK0 ((UTICK_Type *)UTICK0_BASE) - /** Peripheral UTICK0 base pointer */ - #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS { UTICK0_BASE } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS { UTICK0 } - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS_NS { UTICK0_NS } -#else - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE (0x4000E000u) - /** Peripheral UTICK0 base pointer */ - #define UTICK0 ((UTICK_Type *)UTICK0_BASE) - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS { UTICK0_BASE } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS { UTICK0 } -#endif -/** Interrupt vectors for the UTICK peripheral type */ -#define UTICK_IRQS { UTICK0_IRQn } - -/*! - * @} - */ /* end of group UTICK_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- WWDT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer - * @{ - */ - -/** WWDT - Register Layout Typedef */ -typedef struct { - __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ - __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ - __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ - __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ - uint8_t RESERVED_0[4]; - __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ - __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ -} WWDT_Type; - -/* ---------------------------------------------------------------------------- - -- WWDT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Register_Masks WWDT Register Masks - * @{ - */ - -/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ -/*! @{ */ - -#define WWDT_MOD_WDEN_MASK (0x1U) -#define WWDT_MOD_WDEN_SHIFT (0U) -/*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the - * watchdog timer will run permanently. - * 0b0..Stop. The watchdog timer is stopped. - * 0b1..Run. The watchdog timer is running. - */ -#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) - -#define WWDT_MOD_WDRESET_MASK (0x2U) -#define WWDT_MOD_WDRESET_SHIFT (1U) -/*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. - * 0b0..Interrupt. A watchdog time-out will not cause a chip reset. - * 0b1..Reset. A watchdog time-out will cause a chip reset. - */ -#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) - -#define WWDT_MOD_WDTOF_MASK (0x4U) -#define WWDT_MOD_WDTOF_SHIFT (2U) -/*! WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by - * events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a - * chip reset if WDRESET = 1. - */ -#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) - -#define WWDT_MOD_WDINT_MASK (0x8U) -#define WWDT_MOD_WDINT_SHIFT (3U) -/*! WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. - * Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the - * WARNINT value is equal to the value of the TV register. This can occur if the value of - * WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. - */ -#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) - -#define WWDT_MOD_WDPROTECT_MASK (0x10U) -#define WWDT_MOD_WDPROTECT_SHIFT (4U) -/*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. - * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time. - * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. - */ -#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) -/*! @} */ - -/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ -/*! @{ */ - -#define WWDT_TC_COUNT_MASK (0xFFFFFFU) -#define WWDT_TC_COUNT_SHIFT (0U) -/*! COUNT - Watchdog time-out value. - */ -#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) -/*! @} */ - -/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ -/*! @{ */ - -#define WWDT_FEED_FEED_MASK (0xFFU) -#define WWDT_FEED_FEED_SHIFT (0U) -/*! FEED - Feed value should be 0xAA followed by 0x55. - */ -#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) -/*! @} */ - -/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ -/*! @{ */ - -#define WWDT_TV_COUNT_MASK (0xFFFFFFU) -#define WWDT_TV_COUNT_SHIFT (0U) -/*! COUNT - Counter timer value. - */ -#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) -/*! @} */ - -/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ -/*! @{ */ - -#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) -#define WWDT_WARNINT_WARNINT_SHIFT (0U) -/*! WARNINT - Watchdog warning interrupt compare value. - */ -#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) -/*! @} */ - -/*! @name WINDOW - Watchdog Window compare value. */ -/*! @{ */ - -#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) -#define WWDT_WINDOW_WINDOW_SHIFT (0U) -/*! WINDOW - Watchdog window value. - */ -#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group WWDT_Register_Masks */ - - -/* WWDT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral WWDT base address */ - #define WWDT_BASE (0x5000C000u) - /** Peripheral WWDT base address */ - #define WWDT_BASE_NS (0x4000C000u) - /** Peripheral WWDT base pointer */ - #define WWDT ((WWDT_Type *)WWDT_BASE) - /** Peripheral WWDT base pointer */ - #define WWDT_NS ((WWDT_Type *)WWDT_BASE_NS) - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS { WWDT_BASE } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS { WWDT } - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS_NS { WWDT_BASE_NS } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS_NS { WWDT_NS } -#else - /** Peripheral WWDT base address */ - #define WWDT_BASE (0x4000C000u) - /** Peripheral WWDT base pointer */ - #define WWDT ((WWDT_Type *)WWDT_BASE) - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS { WWDT_BASE } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS { WWDT } -#endif -/** Interrupt vectors for the WWDT peripheral type */ -#define WWDT_IRQS { WDT_BOD_IRQn } - -/*! - * @} - */ /* end of group WWDT_Peripheral_Access_Layer */ - - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop - #else - #pragma pop - #endif -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -/*! - * @} - */ /* end of group Peripheral_access_layer */ - - -/* ---------------------------------------------------------------------------- - -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - * @{ - */ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang system_header - #endif -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma system_include -#endif - -/** - * @brief Mask and left-shift a bit field value for use in a register bit range. - * @param field Name of the register bit field. - * @param value Value of the bit field. - * @return Masked and shifted value. - */ -#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) -/** - * @brief Mask and right-shift a register value to extract a bit field value. - * @param field Name of the register bit field. - * @param value Value of the register. - * @return Masked and shifted bit field value. - */ -#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) - -/*! - * @} - */ /* end of group Bit_Field_Generic_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SDK Compatibility - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDK_Compatibility_Symbols SDK Compatibility - * @{ - */ - -/** High Speed SPI (Flexcomm 8) interrupt name */ -#define LSPI_HS_IRQn FLEXCOMM8_IRQn - -/*! - * @brief Get the chip value. - * - * @return chip version, 0x0: A0 version chip, 0x1: A1 version chip, 0xFF: invalid version. - */ -static inline uint32_t Chip_GetVersion(void) -{ - uint32_t deviceRevision; - - deviceRevision = SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK; - - if(0UL == deviceRevision) /* A0 device revision is 0 */ - { - return 0x0; - } - else if(1UL == deviceRevision) /* A1 device revision is 1 */ - { - return 0x1; - } - else - { - return 0xFF; - } -} - - -/*! - * @} - */ /* end of group SDK_Compatibility_Symbols */ - - -#endif /* _LPC55S28_H_ */ - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/LPC55S28.xml b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/LPC55S28.xml deleted file mode 100644 index 48160084ca6..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/LPC55S28.xml +++ /dev/null @@ -1,84663 +0,0 @@ - - - nxp.com - LPC55S28 - 1.0 - LPC55S28JBD100,LPC55S28JBD64,LPC55S28JEV98 - -Copyright 2016-2021 NXP -All rights reserved. - -SPDX-License-Identifier: BSD-3-Clause - - - CM33 - r2p0 - little - true - true - true - 3 - false - - 8 - 32 - - - FLASH_CFPA0 - FLASH_CFPA - FLASH_CFPA - FLASH_CFPA - 0x9E000 - - 0 - 0x200 - registers - - - - HEADER - no description available - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - VERSION - no description available - 0x4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - S_FW_Version - Secure firmware version (Monotonic counter) - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - NS_FW_Version - Non-Secure firmware version (Monotonic counter) - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - ROTKH_REVOKE - no description available - 0x18 - 32 - read-write - 0 - 0xFFFFFFFF - - - RoTK0_EN - RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - 0 - 2 - read-write - - - RoTK1_EN - RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - 2 - 2 - read-write - - - RoTK2_EN - RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - 4 - 2 - read-write - - - RoTK3_EN - RoT Key 3 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - 6 - 2 - read-write - - - - - VENDOR_USAGE - no description available - 0x1C - 32 - read-write - 0 - 0xFFFFFFFF - - - DBG_VENDOR_USAGE - DBG_VENDOR_USAGE. - 0 - 16 - read-write - - - INVERSE_VALUE - inverse value of bits [15:0] - 16 - 16 - read-write - - - - - DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. - 0x20 - 32 - read-write - 0 - 0xFFFFFFFF - - - NIDEN - Non Secure non-invasive debug enable - 0 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - DBGEN - Non Secure debug enable - 1 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - SPNIDEN - Secure non-invasive debug enable - 2 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - SPIDEN - Secure invasive debug enable - 3 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - TAPEN - JTAG TAP enable - 4 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable - 5 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - ISP_CMD_EN - ISP Boot Command enable - 6 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - FA_CMD_EN - FA Command enable - 7 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - ME_CMD_EN - Flash Mass Erase Command enable - 8 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable - 9 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - UUID_CHECK - Enforce UUID match during Debug authentication. - 15 - 1 - read-write - - - INVERSE_VALUE - inverse value of bits [15:0] - 16 - 16 - read-write - - - - - DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. - 0x24 - 32 - read-write - 0 - 0xFFFFFFFF - - - NIDEN - Non Secure non-invasive debug fixed state - 0 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - DBGEN - Non Secure debug fixed state - 1 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - SPNIDEN - Secure non-invasive debug fixed state - 2 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - SPIDEN - Secure invasive debug fixed state - 3 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - TAPEN - JTAG TAP fixed state - 4 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state - 5 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - ISP_CMD_EN - ISP Boot Command fixed state - 6 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - FA_CMD_EN - FA Command fixed state - 7 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - ME_CMD_EN - Flash Mass Erase Command fixed state - 8 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state - 9 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - INVERSE_VALUE - inverse value of bits [15:0] - 16 - 16 - read-write - - - - - ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. - 0x28 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. - 0x2C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE0 - no description available - PRINCE_REGION0_IV_CODE - 0x30 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_HEADER0 - no description available - PRINCE_REGION0_IV_CODE - 0x30 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE1 - no description available - PRINCE_REGION0_IV_CODE - 0x34 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_HEADER1 - no description available - PRINCE_REGION0_IV_CODE - 0x34 - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - no description available - 0 - 2 - read-write - - - INDEX - no description available - 8 - 4 - read-write - - - SIZE - no description available - 24 - 6 - read-write - - - - - PRINCE_REGION0_IV_BODY0 - no description available - PRINCE_REGION0_IV_CODE - 0x38 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE2 - no description available - PRINCE_REGION0_IV_CODE - 0x38 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY1 - no description available - PRINCE_REGION0_IV_CODE - 0x3C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE3 - no description available - PRINCE_REGION0_IV_CODE - 0x3C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY2 - no description available - PRINCE_REGION0_IV_CODE - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE4 - no description available - PRINCE_REGION0_IV_CODE - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY3 - no description available - PRINCE_REGION0_IV_CODE - 0x44 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE5 - no description available - PRINCE_REGION0_IV_CODE - 0x44 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY4 - no description available - PRINCE_REGION0_IV_CODE - 0x48 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE6 - no description available - PRINCE_REGION0_IV_CODE - 0x48 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY5 - no description available - PRINCE_REGION0_IV_CODE - 0x4C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE7 - no description available - PRINCE_REGION0_IV_CODE - 0x4C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY6 - no description available - PRINCE_REGION0_IV_CODE - 0x50 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE8 - no description available - PRINCE_REGION0_IV_CODE - 0x50 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY7 - no description available - PRINCE_REGION0_IV_CODE - 0x54 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE9 - no description available - PRINCE_REGION0_IV_CODE - 0x54 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY8 - no description available - PRINCE_REGION0_IV_CODE - 0x58 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE10 - no description available - PRINCE_REGION0_IV_CODE - 0x58 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY9 - no description available - PRINCE_REGION0_IV_CODE - 0x5C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE11 - no description available - PRINCE_REGION0_IV_CODE - 0x5C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY10 - no description available - PRINCE_REGION0_IV_CODE - 0x60 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE12 - no description available - PRINCE_REGION0_IV_CODE - 0x60 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY11 - no description available - PRINCE_REGION0_IV_CODE - 0x64 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE13 - no description available - PRINCE_REGION0_IV_CODE - 0x64 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE0 - no description available - PRINCE_REGION1_IV_CODE - 0x68 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_HEADER0 - no description available - PRINCE_REGION1_IV_CODE - 0x68 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE1 - no description available - PRINCE_REGION1_IV_CODE - 0x6C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_HEADER1 - no description available - PRINCE_REGION1_IV_CODE - 0x6C - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - no description available - 0 - 2 - read-write - - - INDEX - no description available - 8 - 4 - read-write - - - SIZE - no description available - 24 - 6 - read-write - - - - - PRINCE_REGION1_IV_BODY0 - no description available - PRINCE_REGION1_IV_CODE - 0x70 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE2 - no description available - PRINCE_REGION1_IV_CODE - 0x70 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY1 - no description available - PRINCE_REGION1_IV_CODE - 0x74 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE3 - no description available - PRINCE_REGION1_IV_CODE - 0x74 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY2 - no description available - PRINCE_REGION1_IV_CODE - 0x78 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE4 - no description available - PRINCE_REGION1_IV_CODE - 0x78 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY3 - no description available - PRINCE_REGION1_IV_CODE - 0x7C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE5 - no description available - PRINCE_REGION1_IV_CODE - 0x7C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY4 - no description available - PRINCE_REGION1_IV_CODE - 0x80 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE6 - no description available - PRINCE_REGION1_IV_CODE - 0x80 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY5 - no description available - PRINCE_REGION1_IV_CODE - 0x84 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE7 - no description available - PRINCE_REGION1_IV_CODE - 0x84 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY6 - no description available - PRINCE_REGION1_IV_CODE - 0x88 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE8 - no description available - PRINCE_REGION1_IV_CODE - 0x88 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY7 - no description available - PRINCE_REGION1_IV_CODE - 0x8C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE9 - no description available - PRINCE_REGION1_IV_CODE - 0x8C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY8 - no description available - PRINCE_REGION1_IV_CODE - 0x90 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE10 - no description available - PRINCE_REGION1_IV_CODE - 0x90 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY9 - no description available - PRINCE_REGION1_IV_CODE - 0x94 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE11 - no description available - PRINCE_REGION1_IV_CODE - 0x94 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY10 - no description available - PRINCE_REGION1_IV_CODE - 0x98 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE12 - no description available - PRINCE_REGION1_IV_CODE - 0x98 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY11 - no description available - PRINCE_REGION1_IV_CODE - 0x9C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE13 - no description available - PRINCE_REGION1_IV_CODE - 0x9C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE0 - no description available - PRINCE_REGION2_IV_CODE - 0xA0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_HEADER0 - no description available - PRINCE_REGION2_IV_CODE - 0xA0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE1 - no description available - PRINCE_REGION2_IV_CODE - 0xA4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_HEADER1 - no description available - PRINCE_REGION2_IV_CODE - 0xA4 - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - no description available - 0 - 2 - read-write - - - INDEX - no description available - 8 - 4 - read-write - - - SIZE - no description available - 24 - 6 - read-write - - - - - PRINCE_REGION2_IV_BODY0 - no description available - PRINCE_REGION2_IV_CODE - 0xA8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE2 - no description available - PRINCE_REGION2_IV_CODE - 0xA8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY1 - no description available - PRINCE_REGION2_IV_CODE - 0xAC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE3 - no description available - PRINCE_REGION2_IV_CODE - 0xAC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY2 - no description available - PRINCE_REGION2_IV_CODE - 0xB0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE4 - no description available - PRINCE_REGION2_IV_CODE - 0xB0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY3 - no description available - PRINCE_REGION2_IV_CODE - 0xB4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE5 - no description available - PRINCE_REGION2_IV_CODE - 0xB4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY4 - no description available - PRINCE_REGION2_IV_CODE - 0xB8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE6 - no description available - PRINCE_REGION2_IV_CODE - 0xB8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY5 - no description available - PRINCE_REGION2_IV_CODE - 0xBC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE7 - no description available - PRINCE_REGION2_IV_CODE - 0xBC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY6 - no description available - PRINCE_REGION2_IV_CODE - 0xC0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE8 - no description available - PRINCE_REGION2_IV_CODE - 0xC0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY7 - no description available - PRINCE_REGION2_IV_CODE - 0xC4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE9 - no description available - PRINCE_REGION2_IV_CODE - 0xC4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY8 - no description available - PRINCE_REGION2_IV_CODE - 0xC8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE10 - no description available - PRINCE_REGION2_IV_CODE - 0xC8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY9 - no description available - PRINCE_REGION2_IV_CODE - 0xCC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE11 - no description available - PRINCE_REGION2_IV_CODE - 0xCC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY10 - no description available - PRINCE_REGION2_IV_CODE - 0xD0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE12 - no description available - PRINCE_REGION2_IV_CODE - 0xD0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY11 - no description available - PRINCE_REGION2_IV_CODE - 0xD4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE13 - no description available - PRINCE_REGION2_IV_CODE - 0xD4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - 56 - 0x4 - CUSTOMER_DEFINED[%s] - Customer Defined (Programable through ROM API) - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - 8 - 0x4 - SHA256_DIGEST[%s] - SHA256_DIGESTindex for DIGEST[((index * 32) + 31):(index * 32)] - 0x1E0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - - - FLASH_CFPA_SCRATCH - FLASH_CFPA - FLASH_CFPA - 0x9DE00 - - 0 - 0x200 - registers - - - - FLASH_CFPA1 - FLASH_CFPA - FLASH_CFPA - 0x9E200 - - 0 - 0x200 - registers - - - - FLASH_CMPA - FLASH_CMPA - FLASH_CMPA - 0x9E400 - - 0 - 0x200 - registers - - - - BOOT_CFG - no description available - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - DEFAULT_ISP_MODE - Default ISP mode: - 4 - 3 - read-write - - - AUTO_ISP - Auto ISP - 0 - - - USB_HID_ISP - USB_HID_ISP - 0x1 - - - UART_ISP - UART ISP - 0x2 - - - SPI_ISP - SPI Slave ISP - 0x3 - - - I2C_ISP - I2C Slave ISP - 0x4 - - - DISABLE - Disable ISP fall through - 0x7 - - - - - BOOT_SPEED - Core clock: - 7 - 2 - read-write - - - VALUE_0 - Defined by NMPA.SYSTEM_SPEED_CODE - 0 - - - VALUE_1 - 96MHz FRO - 0x1 - - - VALUE_2 - 48MHz FRO - 0x2 - - - - - BOOT_FAILURE_PIN - GPIO port and pin number to use for indicating failure reason. The toggle rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO pin - 24 - 8 - read-write - - - - - SPI_FLASH_CFG - no description available - 0x4 - 32 - read-write - 0 - 0xFFFFFFFF - - - SPI_RECOVERY_BOOT_EN - SPI flash recovery boot is enabled, if non-zero value is written to this field. - 0 - 5 - read-write - - - - - USB_ID - no description available - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - USB_VENDOR_ID - no description available - 0 - 16 - read-write - - - USB_PRODUCT_ID - no description available - 16 - 16 - read-write - - - - - SDIO_CFG - no description available - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - CC_SOCU_PIN - no description available - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - NIDEN - Non Secure non-invasive debug enable - 0 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - DBGEN - Non Secure debug enable - 1 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - SPNIDEN - Secure non-invasive debug enable - 2 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - SPIDEN - Secure invasive debug enable - 3 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - TAPEN - JTAG TAP enable - 4 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable - 5 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - ISP_CMD_EN - ISP Boot Command enable - 6 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - FA_CMD_EN - FA Command enable - 7 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - ME_CMD_EN - Flash Mass Erase Command enable - 8 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable - 9 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - UUID_CHECK - Enforce UUID match during Debug authentication. - 15 - 1 - read-write - - - INVERSE_VALUE - inverse value of bits [15:0] - 16 - 16 - read-write - - - - - CC_SOCU_DFLT - no description available - 0x14 - 32 - read-write - 0 - 0xFFFFFFFF - - - NIDEN - Non Secure non-invasive debug fixed state - 0 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - DBGEN - Non Secure debug fixed state - 1 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - SPNIDEN - Secure non-invasive debug fixed state - 2 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - SPIDEN - Secure invasive debug fixed state - 3 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - TAPEN - JTAG TAP fixed state - 4 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state - 5 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - ISP_CMD_EN - ISP Boot Command fixed state - 6 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - FA_CMD_EN - FA Command fixed state - 7 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - ME_CMD_EN - Flash Mass Erase Command fixed state - 8 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state - 9 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - INVERSE_VALUE - inverse value of bits [15:0] - 16 - 16 - read-write - - - - - VENDOR_USAGE - no description available - 0x18 - 32 - read-write - 0 - 0xFFFFFFFF - - - VENDOR_USAGE - Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area. - 16 - 16 - read-write - - - - - SECURE_BOOT_CFG - Secure boot configuration flags. - 0x1C - 32 - read-write - 0 - 0xFFFFFFFF - - - RSA4K - Use RSA4096 keys only. - 0 - 2 - read-write - - - VALUE_0 - Allow RSA2048 and higher - 0 - - - VALUE_1 - RSA4096 only - 0x1 - - - VALUE_2 - RSA4096 only - 0x2 - - - VALUE_3 - RSA4096 only - 0x3 - - - - - DICE_INC_NXP_CFG - Include NXP area in DICE computation. - 2 - 2 - read-write - - - NOT_INCLUD - not included - 0 - - - INCLUD - included - 0x1 - - - VALUE_2 - included - 0x2 - - - VALUE_3 - included - 0x3 - - - - - DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. - 4 - 2 - read-write - - - NOT_INCLUD - not included - 0 - - - UNCLUD - included - 0x1 - - - VALUE_2 - included - 0x2 - - - VALUE_3 - included - 0x3 - - - - - SKIP_DICE - Skip DICE computation - 6 - 2 - read-write - - - ENABLE - Enable DICE - 0 - - - DISABLE - Disable DICE - 0x1 - - - VALUE_2 - Disable DICE - 0x2 - - - VALUE_3 - Disable DICE - 0x3 - - - - - TZM_IMAGE_TYPE - TrustZone-M mode - 8 - 2 - read-write - - - VALUE_0 - TZ-M image mode is taken from application image header - 0 - - - VALUE_1 - TZ-M disabled image, boots to non-secure mode - 0x1 - - - VALUE_2 - TZ-M enabled image, boots to secure mode - 0x2 - - - VALUE_3 - TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header - 0x3 - - - - - BLOCK_SET_KEY - Block PUF key code generation - 10 - 2 - read-write - - - ALLOW - Allow PUF Key Code generation - 0 - - - DISABLE - Disable PUF Key Code generation - 0x1 - - - VALUE_2 - Disable PUF Key Code generation - 0x2 - - - VALUE_3 - Disable PUF Key Code generation - 0x3 - - - - - BLOCK_ENROLL - Block PUF enrollement - 12 - 2 - read-write - - - ALLOW - Allow PUF enroll operation - 0 - - - DISABLE - Disable PUF enroll operation - 0x1 - - - VALUE_2 - Disable PUF enroll operation - 0x2 - - - VALUE_3 - Disable PUF enroll operation - 0x3 - - - - - DICE_INC_SEC_EPOCH - Include security EPOCH in DICE - 14 - 2 - read-write - - - SEC_BOOT_EN - Secure boot enable - 30 - 2 - read-write - - - DISABLE - Plain image (internal flash with or without CRC) - 0 - - - ENABLE - Boot signed images. (internal flash, RSA signed) - 0x1 - - - VALUE_2 - Boot signed images. (internal flash, RSA signed) - 0x2 - - - VALUE_3 - Boot signed images. (internal flash, RSA signed) - 0x3 - - - - - - - PRINCE_BASE_ADDR - no description available - 0x20 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADDR0_PRG - Programmable portion of the base address of region 0 - 0 - 4 - read-write - - - ADDR1_PRG - Programmable portion of the base address of region 1 - 4 - 4 - read-write - - - ADDR2_PRG - Programmable portion of the base address of region 2 - 8 - 4 - read-write - - - LOCK_REG0 - Lock PRINCE region0 settings - 18 - 2 - read-write - - - UNLOCK - Region is not locked - 0 - - - LOCK - Region is locked - 0x1 - - - VALUE_2 - Region is locked - 0x2 - - - VALUE_3 - Region is locked - 0x3 - - - - - LOCK_REG1 - Lock PRINCE region1 settings - 20 - 2 - read-write - - - UNLOCK - Region is not locked - 0 - - - LOCK - Region is locked - 0x1 - - - VALUE_2 - Region is locked - 0x2 - - - VALUE_3 - Region is locked - 0x3 - - - - - REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased together - 24 - 2 - read-write - - - DISABLE - Region is disabled - 0 - - - ENABLE - Region is enabled - 0x1 - - - VALUE_2 - Region is enabled - 0x2 - - - VALUE_3 - Region is enabled - 0x3 - - - - - REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased together - 26 - 2 - read-write - - - DISABLE - Region is disabled - 0 - - - ENABLE - Region is enabled - 0x1 - - - VALUE_2 - Region is enabled - 0x2 - - - VALUE_3 - Region is enabled - 0x3 - - - - - REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased together - 28 - 2 - read-write - - - DISABLE - Region is disabled - 0 - - - ENABLE - Region is enabled - 0x1 - - - VALUE_2 - Region is enabled - 0x2 - - - VALUE_3 - Region is enabled - 0x3 - - - - - - - PRINCE_SR_0 - Region 0, sub-region enable - 0x24 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_SR_1 - Region 1, sub-region enable - 0x28 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_SR_2 - Region 2, sub-region enable - 0x2C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - XTAL_32KHZ_CAPABANK_TRIM - Xtal 32kHz capabank triming. - 0x30 - 32 - read-write - 0 - 0xFFFFFFFF - - - TRIM_VALID - XTAL 32kHz capa bank trimmings - 0 - 1 - read-write - - - NOT_TRIM - Capa Bank trimmings not valid. Default trimmings value are used - 0 - - - VALID - Capa Bank trimmings valid - 0x1 - - - - - XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. - 1 - 10 - read-write - - - PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. - 11 - 10 - read-write - - - PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. - 21 - 10 - read-write - - - - - XTAL_16MHZ_CAPABANK_TRIM - Xtal 16MHz capabank triming. - 0x34 - 32 - read-write - 0 - 0xFFFFFFFF - - - TRIM_VALID - XTAL 16MHz capa bank trimmings - 0 - 1 - read-write - - - NOT_TRIM - Capa Bank trimmings not valid. Default trimmings value are used - 0 - - - VALID - Capa Bank trimmings valid - 0x1 - - - - - XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. - 1 - 10 - read-write - - - PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. - 11 - 10 - read-write - - - PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. - 21 - 10 - read-write - - - - - 8 - 0x4 - ROTKH[%s] - ROTKHindex for Root of Trust Keys Table hash[(((7 - index) * 32) + 31):((7 - index) * 32)] - 0x50 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - 56 - 0x4 - CUSTOMER_DEFINED[%s] - Customer Defined (Programable through ROM API) - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - 8 - 0x4 - SHA256_DIGEST[%s] - SHA256_DIGESTindex for DIGEST[((index * 32) + 31):(index * 32)] - 0x1E0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - - - FLASH_KEY_STORE - FLASH_KEY_STORE - FLASH_KEY_STORE - 0x9E600 - - 0 - 0x600 - registers - - - - HEADER - Valid Key Sore Header : 0x95959595 - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - puf_discharge_time_in_ms - puf discharge time in ms. - 0x4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - 298 - 0x4 - ACTIVATION_CODE[%s] - . - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_HEADER0 - . - SBKEY_KEY_CODE - 0x4B0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE0 - . - SBKEY_KEY_CODE - 0x4B0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_HEADER1 - . - SBKEY_KEY_CODE - 0x4B4 - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - . - 0 - 2 - read-write - - - INDEX - . - 8 - 4 - read-write - - - SIZE - . - 24 - 6 - read-write - - - - - SBKEY_KEY_CODE1 - . - SBKEY_KEY_CODE - 0x4B4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY0 - . - SBKEY_KEY_CODE - 0x4B8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE2 - . - SBKEY_KEY_CODE - 0x4B8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY1 - . - SBKEY_KEY_CODE - 0x4BC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE3 - . - SBKEY_KEY_CODE - 0x4BC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY2 - . - SBKEY_KEY_CODE - 0x4C0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE4 - . - SBKEY_KEY_CODE - 0x4C0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY3 - . - SBKEY_KEY_CODE - 0x4C4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE5 - . - SBKEY_KEY_CODE - 0x4C4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY4 - . - SBKEY_KEY_CODE - 0x4C8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE6 - . - SBKEY_KEY_CODE - 0x4C8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY5 - . - SBKEY_KEY_CODE - 0x4CC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE7 - . - SBKEY_KEY_CODE - 0x4CC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY6 - . - SBKEY_KEY_CODE - 0x4D0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE8 - . - SBKEY_KEY_CODE - 0x4D0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY7 - . - SBKEY_KEY_CODE - 0x4D4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE9 - . - SBKEY_KEY_CODE - 0x4D4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY8 - . - SBKEY_KEY_CODE - 0x4D8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE10 - . - SBKEY_KEY_CODE - 0x4D8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY9 - . - SBKEY_KEY_CODE - 0x4DC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE11 - . - SBKEY_KEY_CODE - 0x4DC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY10 - . - SBKEY_KEY_CODE - 0x4E0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE12 - . - SBKEY_KEY_CODE - 0x4E0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY11 - . - SBKEY_KEY_CODE - 0x4E4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE13 - . - SBKEY_KEY_CODE - 0x4E4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_HEADER0 - . - USER_KEK_KEY_CODE - 0x4E8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE0 - . - USER_KEK_KEY_CODE - 0x4E8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_HEADER1 - . - USER_KEK_KEY_CODE - 0x4EC - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - . - 0 - 2 - read-write - - - INDEX - . - 8 - 4 - read-write - - - SIZE - . - 24 - 6 - read-write - - - - - USER_KEK_KEY_CODE1 - . - USER_KEK_KEY_CODE - 0x4EC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY0 - . - USER_KEK_KEY_CODE - 0x4F0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE2 - . - USER_KEK_KEY_CODE - 0x4F0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY1 - . - USER_KEK_KEY_CODE - 0x4F4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE3 - . - USER_KEK_KEY_CODE - 0x4F4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY2 - . - USER_KEK_KEY_CODE - 0x4F8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE4 - . - USER_KEK_KEY_CODE - 0x4F8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY3 - . - USER_KEK_KEY_CODE - 0x4FC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE5 - . - USER_KEK_KEY_CODE - 0x4FC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY4 - . - USER_KEK_KEY_CODE - 0x500 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE6 - . - USER_KEK_KEY_CODE - 0x500 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY5 - . - USER_KEK_KEY_CODE - 0x504 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE7 - . - USER_KEK_KEY_CODE - 0x504 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY6 - . - USER_KEK_KEY_CODE - 0x508 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE8 - . - USER_KEK_KEY_CODE - 0x508 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY7 - . - USER_KEK_KEY_CODE - 0x50C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE9 - . - USER_KEK_KEY_CODE - 0x50C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY8 - . - USER_KEK_KEY_CODE - 0x510 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE10 - . - USER_KEK_KEY_CODE - 0x510 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY9 - . - USER_KEK_KEY_CODE - 0x514 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE11 - . - USER_KEK_KEY_CODE - 0x514 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY10 - . - USER_KEK_KEY_CODE - 0x518 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE12 - . - USER_KEK_KEY_CODE - 0x518 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY11 - . - USER_KEK_KEY_CODE - 0x51C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE13 - . - USER_KEK_KEY_CODE - 0x51C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_HEADER0 - . - UDS_KEY_CODE - 0x520 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE0 - . - UDS_KEY_CODE - 0x520 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_HEADER1 - . - UDS_KEY_CODE - 0x524 - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - . - 0 - 2 - read-write - - - INDEX - . - 8 - 4 - read-write - - - SIZE - . - 24 - 6 - read-write - - - - - UDS_KEY_CODE1 - . - UDS_KEY_CODE - 0x524 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY0 - . - UDS_KEY_CODE - 0x528 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE2 - . - UDS_KEY_CODE - 0x528 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY1 - . - UDS_KEY_CODE - 0x52C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE3 - . - UDS_KEY_CODE - 0x52C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY2 - . - UDS_KEY_CODE - 0x530 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE4 - . - UDS_KEY_CODE - 0x530 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY3 - . - UDS_KEY_CODE - 0x534 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE5 - . - UDS_KEY_CODE - 0x534 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY4 - . - UDS_KEY_CODE - 0x538 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE6 - . - UDS_KEY_CODE - 0x538 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY5 - . - UDS_KEY_CODE - 0x53C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE7 - . - UDS_KEY_CODE - 0x53C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY6 - . - UDS_KEY_CODE - 0x540 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE8 - . - UDS_KEY_CODE - 0x540 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY7 - . - UDS_KEY_CODE - 0x544 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE9 - . - UDS_KEY_CODE - 0x544 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY8 - . - UDS_KEY_CODE - 0x548 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE10 - . - UDS_KEY_CODE - 0x548 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY9 - . - UDS_KEY_CODE - 0x54C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE11 - . - UDS_KEY_CODE - 0x54C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY10 - . - UDS_KEY_CODE - 0x550 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE12 - . - UDS_KEY_CODE - 0x550 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY11 - . - UDS_KEY_CODE - 0x554 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE13 - . - UDS_KEY_CODE - 0x554 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_HEADER0 - . - PRINCE_REGION0_KEY_CODE - 0x558 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE0 - . - PRINCE_REGION0_KEY_CODE - 0x558 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_HEADER1 - . - PRINCE_REGION0_KEY_CODE - 0x55C - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - . - 0 - 2 - read-write - - - INDEX - . - 8 - 4 - read-write - - - SIZE - . - 24 - 6 - read-write - - - - - PRINCE_REGION0_KEY_CODE1 - . - PRINCE_REGION0_KEY_CODE - 0x55C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY0 - . - PRINCE_REGION0_KEY_CODE - 0x560 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE2 - . - PRINCE_REGION0_KEY_CODE - 0x560 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY1 - . - PRINCE_REGION0_KEY_CODE - 0x564 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE3 - . - PRINCE_REGION0_KEY_CODE - 0x564 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY2 - . - PRINCE_REGION0_KEY_CODE - 0x568 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE4 - . - PRINCE_REGION0_KEY_CODE - 0x568 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY3 - . - PRINCE_REGION0_KEY_CODE - 0x56C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE5 - . - PRINCE_REGION0_KEY_CODE - 0x56C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY4 - . - PRINCE_REGION0_KEY_CODE - 0x570 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE6 - . - PRINCE_REGION0_KEY_CODE - 0x570 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY5 - . - PRINCE_REGION0_KEY_CODE - 0x574 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE7 - . - PRINCE_REGION0_KEY_CODE - 0x574 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY6 - . - PRINCE_REGION0_KEY_CODE - 0x578 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE8 - . - PRINCE_REGION0_KEY_CODE - 0x578 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY7 - . - PRINCE_REGION0_KEY_CODE - 0x57C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE9 - . - PRINCE_REGION0_KEY_CODE - 0x57C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY8 - . - PRINCE_REGION0_KEY_CODE - 0x580 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE10 - . - PRINCE_REGION0_KEY_CODE - 0x580 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY9 - . - PRINCE_REGION0_KEY_CODE - 0x584 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE11 - . - PRINCE_REGION0_KEY_CODE - 0x584 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY10 - . - PRINCE_REGION0_KEY_CODE - 0x588 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE12 - . - PRINCE_REGION0_KEY_CODE - 0x588 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY11 - . - PRINCE_REGION0_KEY_CODE - 0x58C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE13 - . - PRINCE_REGION0_KEY_CODE - 0x58C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_HEADER0 - . - PRINCE_REGION1_KEY_CODE - 0x590 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE0 - . - PRINCE_REGION1_KEY_CODE - 0x590 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_HEADER1 - . - PRINCE_REGION1_KEY_CODE - 0x594 - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - . - 0 - 2 - read-write - - - INDEX - . - 8 - 4 - read-write - - - SIZE - . - 24 - 6 - read-write - - - - - PRINCE_REGION1_KEY_CODE1 - . - PRINCE_REGION1_KEY_CODE - 0x594 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY0 - . - PRINCE_REGION1_KEY_CODE - 0x598 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE2 - . - PRINCE_REGION1_KEY_CODE - 0x598 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY1 - . - PRINCE_REGION1_KEY_CODE - 0x59C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE3 - . - PRINCE_REGION1_KEY_CODE - 0x59C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY2 - . - PRINCE_REGION1_KEY_CODE - 0x5A0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE4 - . - PRINCE_REGION1_KEY_CODE - 0x5A0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY3 - . - PRINCE_REGION1_KEY_CODE - 0x5A4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE5 - . - PRINCE_REGION1_KEY_CODE - 0x5A4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY4 - . - PRINCE_REGION1_KEY_CODE - 0x5A8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE6 - . - PRINCE_REGION1_KEY_CODE - 0x5A8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY5 - . - PRINCE_REGION1_KEY_CODE - 0x5AC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE7 - . - PRINCE_REGION1_KEY_CODE - 0x5AC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY6 - . - PRINCE_REGION1_KEY_CODE - 0x5B0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE8 - . - PRINCE_REGION1_KEY_CODE - 0x5B0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY7 - . - PRINCE_REGION1_KEY_CODE - 0x5B4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE9 - . - PRINCE_REGION1_KEY_CODE - 0x5B4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY8 - . - PRINCE_REGION1_KEY_CODE - 0x5B8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE10 - . - PRINCE_REGION1_KEY_CODE - 0x5B8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY9 - . - PRINCE_REGION1_KEY_CODE - 0x5BC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE11 - . - PRINCE_REGION1_KEY_CODE - 0x5BC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY10 - . - PRINCE_REGION1_KEY_CODE - 0x5C0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE12 - . - PRINCE_REGION1_KEY_CODE - 0x5C0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY11 - . - PRINCE_REGION1_KEY_CODE - 0x5C4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE13 - . - PRINCE_REGION1_KEY_CODE - 0x5C4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_HEADER0 - . - PRINCE_REGION2_KEY_CODE - 0x5C8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE0 - . - PRINCE_REGION2_KEY_CODE - 0x5C8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_HEADER1 - . - PRINCE_REGION2_KEY_CODE - 0x5CC - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - . - 0 - 2 - read-write - - - INDEX - . - 8 - 4 - read-write - - - SIZE - . - 24 - 6 - read-write - - - - - PRINCE_REGION2_KEY_CODE1 - . - PRINCE_REGION2_KEY_CODE - 0x5CC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY0 - . - PRINCE_REGION2_KEY_CODE - 0x5D0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE2 - . - PRINCE_REGION2_KEY_CODE - 0x5D0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY1 - . - PRINCE_REGION2_KEY_CODE - 0x5D4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE3 - . - PRINCE_REGION2_KEY_CODE - 0x5D4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY2 - . - PRINCE_REGION2_KEY_CODE - 0x5D8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE4 - . - PRINCE_REGION2_KEY_CODE - 0x5D8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY3 - . - PRINCE_REGION2_KEY_CODE - 0x5DC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE5 - . - PRINCE_REGION2_KEY_CODE - 0x5DC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY4 - . - PRINCE_REGION2_KEY_CODE - 0x5E0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE6 - . - PRINCE_REGION2_KEY_CODE - 0x5E0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY5 - . - PRINCE_REGION2_KEY_CODE - 0x5E4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE7 - . - PRINCE_REGION2_KEY_CODE - 0x5E4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY6 - . - PRINCE_REGION2_KEY_CODE - 0x5E8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE8 - . - PRINCE_REGION2_KEY_CODE - 0x5E8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY7 - . - PRINCE_REGION2_KEY_CODE - 0x5EC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE9 - . - PRINCE_REGION2_KEY_CODE - 0x5EC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY8 - . - PRINCE_REGION2_KEY_CODE - 0x5F0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE10 - . - PRINCE_REGION2_KEY_CODE - 0x5F0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY9 - . - PRINCE_REGION2_KEY_CODE - 0x5F4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE11 - . - PRINCE_REGION2_KEY_CODE - 0x5F4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY10 - . - PRINCE_REGION2_KEY_CODE - 0x5F8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE12 - . - PRINCE_REGION2_KEY_CODE - 0x5F8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY11 - . - PRINCE_REGION2_KEY_CODE - 0x5FC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE13 - . - PRINCE_REGION2_KEY_CODE - 0x5FC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - - - SYSCON - SYSCON - SYSCON - 0x40000000 - - 0 - 0x1000 - registers - - - - MEMORYREMAP - Memory Remap control register - 0 - 32 - read-write - 0 - 0x3 - - - MAP - Select the location of the vector table :. - 0 - 2 - read-write - - - ROM0 - Vector Table in ROM. - 0 - - - RAM1 - Vector Table in RAM. - 0x1 - - - FLASH0 - Vector Table in Flash. - 0x2 - - - FLASH1 - Vector Table in Flash. - 0x3 - - - - - - - AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest - 0x10 - 32 - read-write - 0 - 0x3FFFFFF - - - PRI_CPU0_CBUS - CPU0 C-AHB bus. - 0 - 2 - read-write - - - PRI_CPU0_SBUS - CPU0 S-AHB bus. - 2 - 2 - read-write - - - PRI_CPU1_CBUS - CPU1 C-AHB bus. - 4 - 2 - read-write - - - PRI_CPU1_SBUS - CPU1 S-AHB bus. - 6 - 2 - read-write - - - PRI_USB_FS - USB-FS.(USB0) - 8 - 2 - read-write - - - PRI_SDMA0 - DMA0 controller priority. - 10 - 2 - read-write - - - PRI_SDIO - SDIO. - 16 - 2 - read-write - - - PRI_PQ - PQ (HW Accelerator). - 18 - 2 - read-write - - - PRI_HASH_AES - HASH_AES. - 20 - 2 - read-write - - - PRI_USB_HS - USB-HS.(USB1) - 22 - 2 - read-write - - - PRI_SDMA1 - DMA1 controller priority. - 24 - 2 - read-write - - - - - CPU0STCKCAL - System tick calibration for secure part of CPU0 - 0x38 - 32 - read-write - 0 - 0x3FFFFFF - - - TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. - 0 - 24 - read-write - - - SKEW - Initial value for the Systick timer. - 24 - 1 - read-write - - - NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference clock provided; 1 = no reference clock provided. - 25 - 1 - read-write - - - - - CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 - 0x3C - 32 - read-write - 0 - 0x3FFFFFF - - - TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. - 0 - 24 - read-write - - - SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. - 24 - 1 - read-write - - - NOREF - Initial value for the Systick timer. - 25 - 1 - read-write - - - - - CPU1STCKCAL - System tick calibration for CPU1 - 0x40 - 32 - read-write - 0 - 0x3FFFFFF - - - TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. - 0 - 24 - read-write - - - SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. - 24 - 1 - read-write - - - NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference clock provided; 1 = no reference clock provided. - 25 - 1 - read-write - - - - - NMISRC - NMI Source Select - 0x48 - 32 - read-write - 0 - 0xC0003F3F - - - IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0. - 0 - 6 - read-write - - - IRQCPU1 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1, if enabled by NMIENCPU1. - 8 - 6 - read-write - - - NMIENCPU1 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU1. - 30 - 1 - read-write - - - NMIENCPU0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. - 31 - 1 - read-write - - - - - PRESETCTRL0 - Peripheral reset control 0 - PRESETCTRL - 0x100 - 32 - read-write - 0 - 0xCFFE9FA - - - ROM_RST - ROM reset control. - 1 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SRAM_CTRL1_RST - SRAM Controller 1 reset control. - 3 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SRAM_CTRL2_RST - SRAM Controller 2 reset control. - 4 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SRAM_CTRL3_RST - SRAM Controller 3 reset control. - 5 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SRAM_CTRL4_RST - SRAM Controller 4 reset control. - 6 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FLASH_RST - Flash controller reset control. - 7 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FMC_RST - FMC controller reset control. - 8 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - MUX_RST - Input Mux reset control. - 11 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - IOCON_RST - I/O controller reset control. - 13 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GPIO0_RST - GPIO0 reset control. - 14 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GPIO1_RST - GPIO1 reset control. - 15 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GPIO2_RST - GPIO2 reset control. - 16 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GPIO3_RST - GPIO3 reset control. - 17 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - PINT_RST - Pin interrupt (PINT) reset control. - 18 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GINT_RST - Group interrupt (GINT) reset control. - 19 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - DMA0_RST - DMA0 reset control. - 20 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - CRCGEN_RST - CRCGEN reset control. - 21 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - WWDT_RST - Watchdog Timer reset control. - 22 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - RTC_RST - Real Time Clock (RTC) reset control. - 23 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - MAILBOX_RST - Inter CPU communication Mailbox reset control. - 26 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - ADC_RST - ADC reset control. - 27 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - - - PRESETCTRLX0 - Peripheral reset control register - PRESETCTRL - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - PRESETCTRL1 - Peripheral reset control 1 - PRESETCTRL - 0x104 - 32 - read-write - 0 - 0xDE57FC47 - - - MRT_RST - MRT reset control. - 0 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - OSTIMER_RST - OS Event Timer reset control. - 1 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SCT_RST - SCT reset control. - 2 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SCTIPU_RST - SCTIPU reset control. - 6 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - UTICK_RST - UTICK reset control. - 10 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC0_RST - FC0 reset control. - 11 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC1_RST - FC1 reset control. - 12 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC2_RST - FC2 reset control. - 13 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC3_RST - FC3 reset control. - 14 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC4_RST - FC4 reset control. - 15 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC5_RST - FC5 reset control. - 16 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC6_RST - FC6 reset control. - 17 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC7_RST - FC7 reset control. - 18 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - TIMER2_RST - Timer 2 reset control. - 22 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - USB0_DEV_RST - USB0 DEV reset control. - 25 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - TIMER0_RST - Timer 0 reset control. - 26 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - TIMER1_RST - Timer 1 reset control. - 27 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - - - PRESETCTRLX1 - Peripheral reset control register - PRESETCTRL - 0x104 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - PRESETCTRL2 - Peripheral reset control 2 - PRESETCTRL - 0x108 - 32 - read-write - 0 - 0x7FFF77FE - - - DMA1_RST - DMA1 reset control. - 1 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - COMP_RST - Comparator reset control. - 2 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SDIO_RST - SDIO reset control. - 3 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - USB1_HOST_RST - USB1 Host reset control. - 4 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - USB1_DEV_RST - USB1 dev reset control. - 5 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - USB1_RAM_RST - USB1 RAM reset control. - 6 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - USB1_PHY_RST - USB1 PHY reset control. - 7 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FREQME_RST - Frequency meter reset control. - 8 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - RNG_RST - RNG reset control. - 13 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SYSCTL_RST - SYSCTL Block reset. - 15 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - USB0_HOSTM_RST - USB0 Host Master reset control. - 16 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - USB0_HOSTS_RST - USB0 Host Slave reset control. - 17 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - HASH_AES_RST - HASH_AES reset control. - 18 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - PQ_RST - Power Quad reset control. - 19 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - PLULUT_RST - PLU LUT reset control. - 20 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - TIMER3_RST - Timer 3 reset control. - 21 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - TIMER4_RST - Timer 4 reset control. - 22 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - PUF_RST - PUF reset control reset control. - 23 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - CASPER_RST - Casper reset control. - 24 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - ANALOG_CTRL_RST - analog control reset control. - 27 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - HS_LSPI_RST - HS LSPI reset control. - 28 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GPIO_SEC_RST - GPIO secure reset control. - 29 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GPIO_SEC_INT_RST - GPIO secure int reset control. - 30 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - - - PRESETCTRLX2 - Peripheral reset control register - PRESETCTRL - 0x108 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - 3 - 0x4 - PRESETCTRLSET[%s] - Peripheral reset control set register - 0x120 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - 3 - 0x4 - PRESETCTRLCLR[%s] - Peripheral reset control clear register - 0x140 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - SWR_RESET - generate a software_reset - 0x160 - 32 - write-only - 0 - 0xFFFFFFFF - - - SWR_RESET - Write 0x5A00_0001 to generate a software_reset. - 0 - 32 - write-only - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Generate a software reset. - 0x5A000001 - - - - - - - AHBCLKCTRL0 - AHB Clock control 0 - AHBCLKCTRL - 0x200 - 32 - read-write - 0x180 - 0xCFFE9FA - - - ROM - Enables the clock for the ROM. - 1 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. - 3 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. - 4 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - SRAM_CTRL3 - Enables the clock for the SRAM Controller 3. - 5 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - SRAM_CTRL4 - Enables the clock for the SRAM Controller 4. - 6 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FLASH - Enables the clock for the Flash controller. - 7 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FMC - Enables the clock for the FMC controller. - 8 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - MUX - Enables the clock for the Input Mux. - 11 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - IOCON - Enables the clock for the I/O controller. - 13 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GPIO0 - Enables the clock for the GPIO0. - 14 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GPIO1 - Enables the clock for the GPIO1. - 15 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GPIO2 - Enables the clock for the GPIO2. - 16 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GPIO3 - Enables the clock for the GPIO3. - 17 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - PINT - Enables the clock for the Pin interrupt (PINT). - 18 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GINT - Enables the clock for the Group interrupt (GINT). - 19 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - DMA0 - Enables the clock for the DMA0. - 20 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - CRCGEN - Enables the clock for the CRCGEN. - 21 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - WWDT - Enables the clock for the Watchdog Timer. - 22 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - RTC - Enables the clock for the Real Time Clock (RTC). - 23 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - MAILBOX - Enables the clock for the Inter CPU communication Mailbox. - 26 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - ADC - Enables the clock for the ADC. - 27 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - - - AHBCLKCTRLX0 - Peripheral reset control register - AHBCLKCTRL - 0x200 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - AHBCLKCTRL1 - AHB Clock control 1 - AHBCLKCTRL - 0x204 - 32 - read-write - 0 - 0xDE57FC47 - - - MRT - Enables the clock for the MRT. - 0 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - OSTIMER - Enables the clock for the OS Event Timer. - 1 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - SCT - Enables the clock for the SCT. - 2 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - UTICK - Enables the clock for the UTICK. - 10 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC0 - Enables the clock for the FC0. - 11 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC1 - Enables the clock for the FC1. - 12 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC2 - Enables the clock for the FC2. - 13 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC3 - Enables the clock for the FC3. - 14 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC4 - Enables the clock for the FC4. - 15 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC5 - Enables the clock for the FC5. - 16 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC6 - Enables the clock for the FC6. - 17 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC7 - Enables the clock for the FC7. - 18 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - TIMER2 - Enables the clock for the Timer 2. - 22 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - USB0_DEV - Enables the clock for the USB0 DEV. - 25 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - TIMER0 - Enables the clock for the Timer 0. - 26 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - TIMER1 - Enables the clock for the Timer 1. - 27 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - - - AHBCLKCTRLX1 - Peripheral reset control register - AHBCLKCTRL - 0x204 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - AHBCLKCTRL2 - AHB Clock control 2 - AHBCLKCTRL - 0x208 - 32 - read-write - 0 - 0x7FFF77FE - - - DMA1 - Enables the clock for the DMA1. - 1 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - COMP - Enables the clock for the Comparator. - 2 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - SDIO - Enables the clock for the SDIO. - 3 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - USB1_HOST - Enables the clock for the USB1 Host. - 4 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - USB1_DEV - Enables the clock for the USB1 dev. - 5 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - USB1_RAM - Enables the clock for the USB1 RAM. - 6 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - USB1_PHY - Enables the clock for the USB1 PHY. - 7 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FREQME - Enables the clock for the Frequency meter. - 8 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - RNG - Enables the clock for the RNG. - 13 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - SYSCTL - SYSCTL block clock. - 15 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - USB0_HOSTM - Enables the clock for the USB0 Host Master. - 16 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - USB0_HOSTS - Enables the clock for the USB0 Host Slave. - 17 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - HASH_AES - Enables the clock for the HASH_AES. - 18 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - PQ - Enables the clock for the Power Quad. - 19 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - PLULUT - Enables the clock for the PLU LUT. - 20 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - TIMER3 - Enables the clock for the Timer 3. - 21 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - TIMER4 - Enables the clock for the Timer 4. - 22 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - PUF - Enables the clock for the PUF reset control. - 23 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - CASPER - Enables the clock for the Casper. - 24 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - ANALOG_CTRL - Enables the clock for the analog control. - 27 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - HS_LSPI - Enables the clock for the HS LSPI. - 28 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GPIO_SEC - Enables the clock for the GPIO secure. - 29 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GPIO_SEC_INT - Enables the clock for the GPIO secure int. - 30 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - - - AHBCLKCTRLX2 - Peripheral reset control register - AHBCLKCTRL - 0x208 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - 3 - 0x4 - AHBCLKCTRLSET[%s] - Peripheral reset control register - 0x220 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - 3 - 0x4 - AHBCLKCTRLCLR[%s] - Peripheral reset control register - 0x240 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select - SYSTICKCLKSEL - 0x260 - 32 - read-write - 0x7 - 0x7 - - - SEL - System Tick Timer for CPU0 source select. - 0 - 3 - read-write - - - ENUM_0x0 - System Tick 0 divided clock. - 0 - - - ENUM_0x1 - FRO 1MHz clock. - 0x1 - - - ENUM_0x2 - Oscillator 32 kHz clock. - 0x2 - - - ENUM_0x3 - No clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - SYSTICKCLKSELX0 - Peripheral reset control register - SYSTICKCLKSEL - 0x260 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - TRACECLKSEL - Trace clock source select - 0x268 - 32 - read-write - 0x7 - 0x7 - - - SEL - Trace clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Trace divided clock. - 0 - - - ENUM_0x1 - FRO 1MHz clock. - 0x1 - - - ENUM_0x2 - Oscillator 32 kHz clock. - 0x2 - - - ENUM_0x3 - No clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - CTIMERCLKSEL0 - CTimer 0 clock source select - CTIMERCLKSEL - 0x26C - 32 - read-write - 0x7 - 0x7 - - - SEL - CTimer 0 clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - CTIMERCLKSELX0 - Peripheral reset control register - CTIMERCLKSEL - 0x26C - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - CTIMERCLKSEL1 - CTimer 1 clock source select - CTIMERCLKSEL - 0x270 - 32 - read-write - 0x7 - 0x7 - - - SEL - CTimer 1 clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - CTIMERCLKSELX1 - Peripheral reset control register - CTIMERCLKSEL - 0x270 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - CTIMERCLKSEL2 - CTimer 2 clock source select - CTIMERCLKSEL - 0x274 - 32 - read-write - 0x7 - 0x7 - - - SEL - CTimer 2 clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - CTIMERCLKSELX2 - Peripheral reset control register - CTIMERCLKSEL - 0x274 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - CTIMERCLKSEL3 - CTimer 3 clock source select - CTIMERCLKSEL - 0x278 - 32 - read-write - 0x7 - 0x7 - - - SEL - CTimer 3 clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - CTIMERCLKSELX3 - Peripheral reset control register - CTIMERCLKSEL - 0x278 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - CTIMERCLKSEL4 - CTimer 4 clock source select - CTIMERCLKSEL - 0x27C - 32 - read-write - 0x7 - 0x7 - - - SEL - CTimer 4 clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - CTIMERCLKSELX4 - Peripheral reset control register - CTIMERCLKSEL - 0x27C - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - MAINCLKSELA - Main clock A source select - 0x280 - 32 - read-write - 0 - 0x7 - - - SEL - Main clock A source select. - 0 - 3 - read-write - - - ENUM_0x0 - FRO 12 MHz clock. - 0 - - - ENUM_0x1 - CLKIN clock. - 0x1 - - - ENUM_0x2 - FRO 1MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - - - - - MAINCLKSELB - Main clock source select - 0x284 - 32 - read-write - 0 - 0x7 - - - SEL - Main clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main Clock A. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - PLL1 clock. - 0x2 - - - ENUM_0x3 - Oscillator 32 kHz clock. - 0x3 - - - - - - - CLKOUTSEL - CLKOUT clock source select - 0x288 - 32 - read-write - 0x7 - 0x7 - - - SEL - CLKOUT clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - CLKIN clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - PLL1 clock. - 0x5 - - - ENUM_0x6 - Oscillator 32kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - PLL0CLKSEL - PLL0 clock source select - 0x290 - 32 - read-write - 0x7 - 0x7 - - - SEL - PLL0 clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - FRO 12 MHz clock. - 0 - - - ENUM_0x1 - CLKIN clock. - 0x1 - - - ENUM_0x2 - FRO 1MHz clock. - 0x2 - - - ENUM_0x3 - Oscillator 32kHz clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - PLL1CLKSEL - PLL1 clock source select - 0x294 - 32 - read-write - 0x7 - 0x7 - - - SEL - PLL1 clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - FRO 12 MHz clock. - 0 - - - ENUM_0x1 - CLKIN clock. - 0x1 - - - ENUM_0x2 - FRO 1MHz clock. - 0x2 - - - ENUM_0x3 - Oscillator 32kHz clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - ADCCLKSEL - ADC clock source select - 0x2A4 - 32 - read-write - 0x7 - 0x7 - - - SEL - ADC clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - FRO 96 MHz clock. - 0x2 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - USB0CLKSEL - FS USB clock source select - 0x2A8 - 32 - read-write - 0x7 - 0x7 - - - SEL - FS USB clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - PLL1 clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2B0 - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX0 - Peripheral reset control register - FCCLKSEL - 0x2B0 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2B4 - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX1 - Peripheral reset control register - FCCLKSEL - 0x2B4 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2B8 - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX2 - Peripheral reset control register - FCCLKSEL - 0x2B8 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2BC - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX3 - Peripheral reset control register - FCCLKSEL - 0x2BC - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2C0 - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX4 - Peripheral reset control register - FCCLKSEL - 0x2C0 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2C4 - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX5 - Peripheral reset control register - FCCLKSEL - 0x2C4 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2C8 - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX6 - Peripheral reset control register - FCCLKSEL - 0x2C8 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2CC - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX7 - Peripheral reset control register - FCCLKSEL - 0x2CC - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - HSLSPICLKSEL - HS LSPI clock source select - 0x2D0 - 32 - read-write - 0x7 - 0x7 - - - SEL - HS LSPI clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - MCLKCLKSEL - MCLK clock source select - 0x2E0 - 32 - read-write - 0x7 - 0x7 - - - SEL - MCLK clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - FRO 96 MHz clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - SCTCLKSEL - SCTimer/PWM clock source select - 0x2F0 - 32 - read-write - 0x7 - 0x7 - - - SEL - SCTimer/PWM clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - CLKIN clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - SDIOCLKSEL - SDIO clock source select - 0x2F8 - 32 - read-write - 0x7 - 0x7 - - - SEL - SDIO clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - PLL1 clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 - 0x300 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - SYSTICKCLKDIV1 - System Tick Timer divider for CPU1 - 0x304 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - TRACECLKDIV - TRACE clock divider - 0x308 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 - FLEXFRGCTRL - 0x320 - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL0 - Peripheral reset control register - FLEXFRGCTRL - 0x320 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 - FLEXFRGCTRL - 0x324 - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL1 - Peripheral reset control register - FLEXFRGCTRL - 0x324 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 - FLEXFRGCTRL - 0x328 - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL2 - Peripheral reset control register - FLEXFRGCTRL - 0x328 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 - FLEXFRGCTRL - 0x32C - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL3 - Peripheral reset control register - FLEXFRGCTRL - 0x32C - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 - FLEXFRGCTRL - 0x330 - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL4 - Peripheral reset control register - FLEXFRGCTRL - 0x330 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 - FLEXFRGCTRL - 0x334 - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL5 - Peripheral reset control register - FLEXFRGCTRL - 0x334 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 - FLEXFRGCTRL - 0x338 - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL6 - Peripheral reset control register - FLEXFRGCTRL - 0x338 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 - FLEXFRGCTRL - 0x33C - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL7 - Peripheral reset control register - FLEXFRGCTRL - 0x33C - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - AHBCLKDIV - System clock divider - 0x380 - 32 - read-write - 0 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - CLKOUTDIV - CLKOUT clock divider - 0x384 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - FROHFDIV - FRO_HF (96MHz) clock divider - 0x388 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - WDTCLKDIV - WDT clock divider - 0x38C - 32 - read-write - 0x40000000 - 0xE000003F - - - DIV - Clock divider value. - 0 - 6 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - ADCCLKDIV - ADC clock divider - 0x394 - 32 - read-write - 0x40000000 - 0xE0000007 - - - DIV - Clock divider value. - 0 - 3 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - USB0CLKDIV - USB0 Clock divider - 0x398 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - MCLKDIV - I2S MCLK clock divider - 0x3AC - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - SCTCLKDIV - SCT/PWM clock divider - 0x3B4 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - SDIOCLKDIV - SDIO clock divider - 0x3BC - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - PLL0CLKDIV - PLL0 clock divider - 0x3C4 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) - 0x3FC - 32 - read-write - 0 - 0xFFFFFFFF - - - CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL). - 0 - 32 - read-write - - - FREEZE - all hardware clock configruration are freeze. - 0 - - - ENABLE - update all clock configuration. - 0x1 - - - - - - - FMCCR - FMC configuration register - 0x400 - 32 - read-write - 0x2000 - 0xFFFFFFFF - - - FETCHCFG - Instruction fetch configuration. - 0 - 2 - read-write - - - NOBUF - Instruction fetches from flash are not buffered. - 0 - - - ONEBUF - One buffer is used for all instruction fetches. - 0x1 - - - ALLBUF - All buffers may be used for instruction fetches. - 0x2 - - - - - DATACFG - Data read configuration. - 2 - 2 - read-write - - - NOBUF - Data accesses from flash are not buffered. - 0 - - - ONEBUF - One buffer is used for all data accesses. - 0x1 - - - ALLBUF - All buffers can be used for data accesses. - 0x2 - - - - - ACCEL - Acceleration enable. - 4 - 1 - read-write - - - DISABLE - Flash acceleration is disabled. - 0 - - - ENABLE - Flash acceleration is enabled. - 0x1 - - - - - PREFEN - Prefetch enable. - 5 - 1 - read-write - - - DISABLE - No instruction prefetch is performed. - 0 - - - ENABLE - Instruction prefetch is enabled. - 0x1 - - - - - PREFOVR - Prefetch override. - 6 - 1 - read-write - - - NORMAL - Any previously initiated prefetch will be completed. - 0 - - - OVERRIDE - Any previously initiated prefetch will be aborted, and the next flash line following the current execution address will be prefetched if not already buffered. - 0x1 - - - - - FLASHTIM - Flash memory access time. - 12 - 4 - read-write - - - FLASHTIM0 - 1 system clock flash access time (for system clock rates up to 11 MHz). - 0 - - - FLASHTIM1 - 2 system clocks flash access time (for system clock rates up to 22 MHz). - 0x1 - - - FLASHTIM2 - 3 system clocks flash access time (for system clock rates up to 33 MHz). - 0x2 - - - FLASHTIM3 - 4 system clocks flash access time (for system clock rates up to 44 MHz). - 0x3 - - - FLASHTIM4 - 5 system clocks flash access time (for system clock rates up to 55 MHz). - 0x4 - - - FLASHTIM5 - 6 system clocks flash access time (for system clock rates up to 66 MHz). - 0x5 - - - FLASHTIM6 - 7 system clocks flash access time (for system clock rates up to 77 MHz). - 0x6 - - - FLASHTIM7 - 8 system clocks flash access time (for system clock rates up to 88 MHz). - 0x7 - - - FLASHTIM8 - 9 system clocks flash access time (for system clock rates up to 100 MHz). - 0x8 - - - FLASHTIM9 - 10 system clocks flash access time (for system clock rates up to 115 MHz). - 0x9 - - - FLASHTIM10 - 11 system clocks flash access time (for system clock rates up to 130 MHz). - 0xA - - - FLASHTIM11 - 12 system clocks flash access time (for system clock rates up to 150 MHz). - 0xB - - - - - - - USB0NEEDCLKCTRL - USB0 need clock control - 0x40C - 32 - read-write - 0 - 0x1F - - - AP_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal control:. - 0 - 1 - read-write - - - HW_CTRL - Under hardware control. - 0 - - - FORCED - Forced high. - 0x1 - - - - - POL_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. - 1 - 1 - read-write - - - FALLING - Falling edge of device USB0_NEEDCLK triggers wake-up. - 0 - - - RISING - Rising edge of device USB0_NEEDCLK triggers wake-up. - 0x1 - - - - - AP_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal control:. - 2 - 1 - read-write - - - HW_CTRL - Under hardware control. - 0 - - - FORCED - Forced high. - 0x1 - - - - - POL_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. - 3 - 1 - read-write - - - FALLING - Falling edge of device USB0_NEEDCLK triggers wake-up. - 0 - - - RISING - Rising edge of device USB0_NEEDCLK triggers wake-up. - 0x1 - - - - - - - USB0NEEDCLKSTAT - USB0 need clock status - 0x410 - 32 - read-write - 0 - 0x3 - - - DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal status:. - 0 - 1 - read-only - - - LOW - USB0 Device clock is low. - 0 - - - HIGH - USB0 Device clock is high. - 0x1 - - - - - HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal status:. - 1 - 1 - read-only - - - LOW - USB0 Host clock is low. - 0 - - - HIGH - USB0 Host clock is high. - 0x1 - - - - - - - FMCFLUSH - FMCflush control - 0x41C - 32 - write-only - 0 - 0xFFFFFFFF - - - FLUSH - Flush control - 0 - 1 - write-only - - - NO_FLUSH - No action is performed. - 0 - - - FLUSH - Flush the FMC buffer contents. - 0x1 - - - - - - - MCLKIO - MCLK control - 0x420 - 32 - read-write - 0 - 0xFFFFFFFF - - - MCLKIO - MCLK control. - 0 - 1 - read-write - - - INPUT - input mode. - 0 - - - OUTPUT - output mode. - 0x1 - - - - - - - USB1NEEDCLKCTRL - USB1 need clock control - 0x424 - 32 - read-write - 0x10 - 0x1F - - - AP_HS_DEV_NEEDCLK - USB1 Device need_clock signal control: - 0 - 1 - read-write - - - HW_CTRL - HOST_NEEDCLK is under hardware control. - 0 - - - FORCED - HOST_NEEDCLK is forced high. - 0x1 - - - - - POL_HS_DEV_NEEDCLK - USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt: - 1 - 1 - read-write - - - FALLING - Falling edge of DEV_NEEDCLK triggers wake-up. - 0 - - - RISING - Rising edge of DEV_NEEDCLK triggers wake-up. - 0x1 - - - - - AP_HS_HOST_NEEDCLK - USB1 Host need clock signal control: - 2 - 1 - read-write - - - HW_CTRL - HOST_NEEDCLK is under hardware control. - 0 - - - FORCED - HOST_NEEDCLK is forced high. - 0x1 - - - - - POL_HS_HOST_NEEDCLK - USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. - 3 - 1 - read-write - - - FALLING - Falling edge of HOST_NEEDCLK triggers wake-up. - 0 - - - RISING - Rising edge of HOST_NEEDCLK triggers wake-up. - 0x1 - - - - - HS_DEV_WAKEUP_N - Software override of device controller PHY wake up logic. - 4 - 1 - read-write - - - FORCE_WUP - Forces USB1_PHY to wake-up. - 0 - - - NORMAL_WUP - Normal USB1_PHY behavior. - 0x1 - - - - - - - USB1NEEDCLKSTAT - USB1 need clock status - 0x428 - 32 - read-write - 0 - 0x3 - - - DEV_NEEDCLK - USB1 Device need_clock signal status:. - 0 - 1 - read-only - - - LOW - DEV_NEEDCLK is low. - 0 - - - HIGH - DEV_NEEDCLK is high. - 0x1 - - - - - HOST_NEEDCLK - USB1 Host need_clock signal status:. - 1 - 1 - read-only - - - LOW - HOST_NEEDCLK is low. - 0 - - - HIGH - HOST_NEEDCLK is high. - 0x1 - - - - - - - SDIOCLKCTRL - SDIO CCLKIN phase and delay control - 0x460 - 32 - read-write - 0 - 0x9F9F008F - - - CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in. - 0 - 2 - read-write - - - ENUM_0_DEG - 0 degree shift. - 0 - - - ENUM_90_DEG - 90 degree shift. - 0x1 - - - ENUM_180_DEG - 180 degree shift. - 0x2 - - - ENUM_270_DEG - 270 degree shift. - 0x3 - - - - - CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. - 2 - 2 - read-write - - - ENUM_0_DEG - 0 degree shift. - 0 - - - ENUM_90_DEG - 90 degree shift. - 0x1 - - - ENUM_180_DEG - 180 degree shift. - 0x2 - - - ENUM_270_DEG - 270 degree shift. - 0x3 - - - - - PHASE_ACTIVE - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE. - 7 - 1 - read-write - - - BYPASSED - Bypassed. - 0 - - - PH_SHIFT - Activates phase shift logic. When active, the clock divider is active and phase delays are enabled. - 0x1 - - - - - CCLK_DRV_DELAY - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in. - 16 - 5 - read-write - - - CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field. - 23 - 1 - read-write - - - DISABLE - Disable drive delay. - 0 - - - ENABLE - Enable drive delay. - 0x1 - - - - - CCLK_SAMPLE_DELAY - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. - 24 - 5 - read-write - - - CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. - 31 - 1 - read-write - - - DISABLE - Disables sample delay. - 0 - - - ENABLE - Enables sample delay. - 0x1 - - - - - - - PLL1CTRL - PLL1 550m control - 0x560 - 32 - read-write - 0 - 0x1FFFFFF - - - SELR - Bandwidth select R value. - 0 - 4 - read-write - - - SELI - Bandwidth select I value. - 4 - 6 - read-write - - - SELP - Bandwidth select P value. - 10 - 5 - read-write - - - BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - 15 - 1 - read-write - - - USED - use PLL. - 0 - - - BYPASSED - PLL input clock is sent directly to the PLL output. - 0x1 - - - - - BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - 16 - 1 - read-write - - - USED - use the divide-by-2 divider in the post-divider. - 0 - - - BYPASSED - bypass of the divide-by-2 divider in the post-divider. - 0x1 - - - - - LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. - 17 - 1 - read-write - - - BWDIRECT - control of the bandwidth of the PLL. - 18 - 1 - read-write - - - SYNC - the bandwidth is changed synchronously with the feedback-divider. - 0 - - - DIRECT - modify the bandwidth of the PLL directly. - 0x1 - - - - - BYPASSPREDIV - bypass of the pre-divider. - 19 - 1 - read-write - - - USED - use the pre-divider. - 0 - - - BYPASSED - bypass of the pre-divider. - 0x1 - - - - - BYPASSPOSTDIV - bypass of the post-divider. - 20 - 1 - read-write - - - USED - use the post-divider. - 0 - - - BYPASSED - bypass of the post-divider. - 0x1 - - - - - CLKEN - enable the output clock. - 21 - 1 - read-write - - - DISABLE - Disable the output clock. - 0 - - - ENABLE - Enable the output clock. - 0x1 - - - - - FRMEN - 1: free running mode. - 22 - 1 - read-write - - - FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable. - 23 - 1 - read-write - - - SKEWEN - Skew mode. - 24 - 1 - read-write - - - DISABLE - skewmode is disable. - 0 - - - ENABLE - skewmode is enable. - 0x1 - - - - - - - PLL1STAT - PLL1 550m status - 0x564 - 32 - read-write - 0 - 0x1F - - - LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. - 0 - 1 - read-only - - - PREDIVACK - pre-divider ratio change acknowledge. - 1 - 1 - read-only - - - FEEDDIVACK - feedback divider ratio change acknowledge. - 2 - 1 - read-only - - - POSTDIVACK - post-divider ratio change acknowledge. - 3 - 1 - read-only - - - FRMDET - free running detector output (active high). - 4 - 1 - read-only - - - - - PLL1NDEC - PLL1 550m N divider - 0x568 - 32 - read-write - 0 - 0x1FF - - - NDIV - pre-divider divider ratio (N-divider). - 0 - 8 - read-write - - - NREQ - pre-divider ratio change request. - 8 - 1 - read-write - - - - - PLL1MDEC - PLL1 550m M divider - 0x56C - 32 - read-write - 0 - 0x1FFFF - - - MDIV - feedback divider divider ratio (M-divider). - 0 - 16 - read-write - - - MREQ - feedback ratio change request. - 16 - 1 - read-write - - - - - PLL1PDEC - PLL1 550m P divider - 0x570 - 32 - read-write - 0 - 0x3F - - - PDIV - post-divider divider ratio (P-divider) - 0 - 5 - read-write - - - PREQ - feedback ratio change request. - 5 - 1 - read-write - - - - - PLL0CTRL - PLL0 550m control - 0x580 - 32 - read-write - 0 - 0x1FFFFFF - - - SELR - Bandwidth select R value. - 0 - 4 - read-write - - - SELI - Bandwidth select I value. - 4 - 6 - read-write - - - SELP - Bandwidth select P value. - 10 - 5 - read-write - - - BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - 15 - 1 - read-write - - - USED - use PLL. - 0 - - - BYPASSED - Bypass PLL input clock is sent directly to the PLL output. - 0x1 - - - - - BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - 16 - 1 - read-write - - - USED - use the divide-by-2 divider in the post-divider. - 0 - - - BYPASSED - bypass of the divide-by-2 divider in the post-divider. - 0x1 - - - - - LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. - 17 - 1 - read-write - - - BWDIRECT - Control of the bandwidth of the PLL. - 18 - 1 - read-write - - - SYNC - the bandwidth is changed synchronously with the feedback-divider. - 0 - - - DIRECT - modify the bandwidth of the PLL directly. - 0x1 - - - - - BYPASSPREDIV - bypass of the pre-divider. - 19 - 1 - read-write - - - USED - use the pre-divider. - 0 - - - BYPASSED - bypass of the pre-divider. - 0x1 - - - - - BYPASSPOSTDIV - bypass of the post-divider. - 20 - 1 - read-write - - - USED - use the post-divider. - 0 - - - BYPASSED - bypass of the post-divider. - 0x1 - - - - - CLKEN - enable the output clock. - 21 - 1 - read-write - - - DISABLE - disable the output clock. - 0 - - - ENABLE - enable the output clock. - 0x1 - - - - - FRMEN - free running mode. - 22 - 1 - read-write - - - DISABLE - free running mode is disable. - 0 - - - ENABLE - free running mode is enable. - 0x1 - - - - - FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable. - 23 - 1 - read-write - - - SKEWEN - skew mode. - 24 - 1 - read-write - - - DISABLE - skew mode is disable. - 0 - - - ENABLE - skew mode is enable. - 0x1 - - - - - - - PLL0STAT - PLL0 550m status - 0x584 - 32 - read-write - 0 - 0x1F - - - LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. - 0 - 1 - read-only - - - PREDIVACK - pre-divider ratio change acknowledge. - 1 - 1 - read-only - - - FEEDDIVACK - feedback divider ratio change acknowledge. - 2 - 1 - read-only - - - POSTDIVACK - post-divider ratio change acknowledge. - 3 - 1 - read-only - - - FRMDET - free running detector output (active high). - 4 - 1 - read-only - - - - - PLL0NDEC - PLL0 550m N divider - 0x588 - 32 - read-write - 0 - 0x1FF - - - NDIV - pre-divider divider ratio (N-divider). - 0 - 8 - read-write - - - NREQ - pre-divider ratio change request. - 8 - 1 - read-write - - - - - PLL0PDEC - PLL0 550m P divider - 0x58C - 32 - read-write - 0 - 0x3F - - - PDIV - post-divider divider ratio (P-divider) - 0 - 5 - read-write - - - PREQ - feedback ratio change request. - 5 - 1 - read-write - - - - - PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 - 0x590 - 32 - read-write - 0 - 0xFFFFFFFF - - - MD_LBS - input word of the wrapper bit 31 to 0. - 0 - 32 - read-write - - - - - PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 - 0x594 - 32 - read-write - 0 - 0x1FFFFFFF - - - MD_MBS - input word of the wrapper bit 32. - 0 - 1 - read-write - - - MD_REQ - md change request. - 1 - 1 - read-write - - - MF - programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3. - 2 - 3 - read-write - - - MR - programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1. - 5 - 3 - read-write - - - MC - modulation waveform control Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency spectrum. - 8 - 2 - read-write - - - MDIV_EXT - to select an external mdiv value. - 10 - 16 - read-write - - - MREQ - to select an external mreq value. - 26 - 1 - read-write - - - DITHER - dithering between two modulation frequencies in a random way or in a pseudo random way (white noise), in order to decrease the probability that the modulated waveform will occur with the same phase on a particular point on the screen. - 27 - 1 - read-write - - - SEL_EXT - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext. - 28 - 1 - read-write - - - - - FUNCRETENTIONCTRL - Functional retention control register - 0x704 - 32 - read-write - 0x50C000 - 0xFFFFFF - - - FUNCRETENA - functional retention in power down only. - 0 - 1 - read-write - - - DISABLE - disable functional retention. - 0 - - - ENABLE - enable functional retention. - 0x1 - - - - - RET_START - Start address divided by 4 inside SRAMX bank. - 1 - 13 - read-write - - - RET_LENTH - lenth of Scan chains to save. - 14 - 10 - read-write - - - - - CPUCTRL - CPU Control for multiple processors - 0x800 - 32 - read-write - 0x2C - 0x3D - - - CPU1CLKEN - CPU1 clock enable. - 3 - 1 - read-write - - - DISABLE - The CPU1 clock is not enabled. - 0 - - - ENABLE - The CPU1 clock is enabled. - 0x1 - - - - - CPU1RSTEN - CPU1 reset. - 5 - 1 - read-write - - - RELEASED - The CPU1 is not being reset. - 0 - - - ASSERTED - The CPU1 is being reset. - 0x1 - - - - - - - CPBOOT - Coprocessor Boot Address - 0x804 - 32 - read-write - 0 - 0xFFFFFFFF - - - CPBOOT - Coprocessor Boot Address for CPU1. - 0 - 32 - read-write - - - - - CPSTAT - CPU Status - 0x80C - 32 - read-write - 0 - 0xF - - - CPU0SLEEPING - The CPU0 sleeping state. - 0 - 1 - read-only - - - AWAKE - the CPU is not sleeping. - 0 - - - SLEEPING - the CPU is sleeping. - 0x1 - - - - - CPU1SLEEPING - The CPU1 sleeping state. - 1 - 1 - read-only - - - AWAKE - the CPU is not sleeping. - 0 - - - SLEEPING - the CPU is sleeping. - 0x1 - - - - - CPU0LOCKUP - The CPU0 lockup state. - 2 - 1 - read-only - - - AWAKE - the CPU is not in lockup. - 0 - - - SLEEPING - the CPU is in lockup. - 0x1 - - - - - CPU1LOCKUP - The CPU1 lockup state. - 3 - 1 - read-only - - - AWAKE - the CPU is not in lockup. - 0 - - - SLEEPING - the CPU is in lockup. - 0x1 - - - - - - - CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures - 0xA18 - 32 - read-write - 0x1 - 0x3FF - - - XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. - 1 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. - 2 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. - 3 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. - 4 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - CLKIN_ENA - Enable clock_in clock for clock module. - 5 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. - 6 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. - 7 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration. - 8 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. - 9 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - - - COMP_INT_CTRL - Comparator Interrupt control - 0xB10 - 32 - read-write - 0 - 0x3F - - - INT_ENABLE - Analog Comparator interrupt enable control:. - 0 - 1 - read-write - - - INT_DISABLE - interrupt disable. - 0 - - - INT_ENABLE - interrupt enable. - 0x1 - - - - - INT_CLEAR - Analog Comparator interrupt clear. - 1 - 1 - read-write - - - NONE - No effect. - 0 - - - CLEAR - Clear the interrupt. Self-cleared bit. - 0x1 - - - - - INT_CTRL - Comparator interrupt type selector:. - 2 - 3 - read-write - - - EDGE_DISABLE - The analog comparator interrupt edge sensitive is disabled. - 0 - - - LVL_DISABLE - The analog comparator interrupt level sensitive is disabled. - 0x1 - - - EDGE_RISING - analog comparator interrupt is rising edge sensitive. - 0x2 - - - LVL_HIGH - Analog Comparator interrupt is high level sensitive. - 0x3 - - - EDGE_FALLING - analog comparator interrupt is falling edge sensitive. - 0x4 - - - LVL_LOW - Analog Comparator interrupt is low level sensitive. - 0x5 - - - EDGE_BOTH - analog comparator interrupt is rising and falling edge sensitive. - 0x6 - - - LVL_DIS2 - The analog comparator interrupt level sensitive is disabled. - 0x7 - - - - - INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. - 5 - 1 - read-write - - - FILTER_INT - Select Analog Comparator filtered output as input for interrupt detection. - 0 - - - RAW_INT - Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when Analog comparator is used as wake up source in Power down mode. - 0x1 - - - - - - - COMP_INT_STATUS - Comparator Interrupt status - 0xB14 - 32 - read-write - 0 - 0x7 - - - STATUS - Interrupt status BEFORE Interrupt Enable. - 0 - 1 - read-only - - - NO_INT - no interrupt pending. - 0 - - - PENDING - interrupt pending. - 0x1 - - - - - INT_STATUS - Interrupt status AFTER Interrupt Enable. - 1 - 1 - read-only - - - NO_INT - no interrupt pending. - 0 - - - PENDING - interrupt pending. - 0x1 - - - - - VAL - comparator analog output. - 2 - 1 - read-only - - - SMALLER - P+ is smaller than P-. - 0 - - - GREATER - P+ is greater than P-. - 0x1 - - - - - - - AUTOCLKGATEOVERRIDE - Control automatic clock gating - 0xE04 - 32 - read-write - 0xFFFF - 0xFFFFFFFF - - - ROM - Control automatic clock gating of ROM controller. - 0 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - RAMX_CTRL - Control automatic clock gating of RAMX controller. - 1 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - RAM0_CTRL - Control automatic clock gating of RAM0 controller. - 2 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - RAM1_CTRL - Control automatic clock gating of RAM1 controller. - 3 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - RAM2_CTRL - Control automatic clock gating of RAM2 controller. - 4 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - RAM3_CTRL - Control automatic clock gating of RAM3 controller. - 5 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - RAM4_CTRL - Control automatic clock gating of RAM4 controller. - 6 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. - 7 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. - 8 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - CRCGEN - Control automatic clock gating of CRCGEN controller. - 11 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - SDMA0 - Control automatic clock gating of DMA0 controller. - 12 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - SDMA1 - Control automatic clock gating of DMA1 controller. - 13 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - USB0 - Control automatic clock gating of USB controller. - 14 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - SYSCON - Control automatic clock gating of synchronous system controller registers bank. - 15 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. - 16 - 16 - write-only - - - DISABLE - Bit Fields 0 - 15 of this register are not updated - 0 - - - ENABLE - Bit Fields 0 - 15 of this register are updated - 0xC0DE - - - - - - - GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module - 0xE08 - 32 - read-write - 0 - 0x1 - - - PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module. - 0 - 1 - read-write - - - USED - use the first stage of synchonization inside GPIO_INT module. - 0 - - - BYPASS - bypass of the first stage of synchonization inside GPIO_INT module. - 0x1 - - - - - - - DEBUG_LOCK_EN - Control write access to security registers. - 0xFA0 - 32 - read-write - 0x5 - 0xF - - - LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, CODESECURITYPROTCPU1, CPU0_DEBUG_FEATURES, CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. - 0 - 4 - read-write - - - DISABLE - Any other value than b1010: disable write access to all 6 registers. - 0 - - - ENABLE - 1010: Enable write access to all 6 registers. - 0xA - - - - - - - DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control. - 0xFA4 - 32 - read-write - 0 - 0xFFF - - - CPU0_DBGEN - CPU0 Invasive debug control:. - 0 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU0_NIDEN - CPU0 Non Invasive debug control:. - 2 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU0_SPIDEN - CPU0 Secure Invasive debug control:. - 4 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. - 6 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU1_DBGEN - CPU1 Invasive debug control:. - 8 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU1_NIDEN - CPU1 Non Invasive debug control:. - 10 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - - - DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register. - 0xFA8 - 32 - read-write - 0x555 - 0xFFF - - - CPU0_DBGEN - CPU0 (CPU0) Invasive debug control:. - 0 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU0_NIDEN - CPU0 Non Invasive debug control:. - 2 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU0_SPIDEN - CPU0 Secure Invasive debug control:. - 4 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. - 6 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU1_DBGEN - CPU1 Invasive debug control:. - 8 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU1_NIDEN - CPU1 Non Invasive debug control:. - 10 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - - - KEY_BLOCK - block quiddikey/PUF all index. - 0xFBC - 32 - write-only - 0x3CC35AA5 - 0xFFFFFFFF - - - KEY_BLOCK - Write a value to block quiddikey/PUF all index. - 0 - 32 - write-only - - - - - DEBUG_AUTH_BEACON - Debug authentication BEACON register - 0xFC0 - 32 - read-write - 0 - 0xFFFFFFFF - - - BEACON - Set by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to application code. - 0 - 32 - read-write - - - - - DEVICE_ID0 - Device ID - 0xFF8 - 32 - read-only - 0 - 0xFFFFFFFF - - - ROM_REV_MINOR - ROM revision. - 20 - 4 - read-only - - - - - DIEID - Chip revision ID and Number - 0xFFC - 32 - read-only - 0x426B0 - 0xFFFFFF - - - REV_ID - Chip Metal Revision ID. - 0 - 4 - read-only - - - MCO_NUM_IN_DIE_ID - Chip Number 0x426B. - 4 - 20 - read-only - - - - - - - IOCON - I/O pin configuration (IOCON) - IOCON - 0x40001000 - - 0 - 0x100 - registers - - - - PIO0_0 - Digital I/O control for port 0 pins PIO0_0 - 0 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_1 - Digital I/O control for port 0 pins PIO0_1 - 0x4 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_2 - Digital I/O control for port 0 pins PIO0_2 - 0x8 - 32 - read-write - 0x110 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_3 - Digital I/O control for port 0 pins PIO0_3 - 0xC - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_4 - Digital I/O control for port 0 pins PIO0_4 - 0x10 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_5 - Digital I/O control for port 0 pins PIO0_5 - 0x14 - 32 - read-write - 0x120 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_6 - Digital I/O control for port 0 pins PIO0_6 - 0x18 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_7 - Digital I/O control for port 0 pins PIO0_7 - 0x1C - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_8 - Digital I/O control for port 0 pins PIO0_8 - 0x20 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_9 - Digital I/O control for port 0 pins PIO0_9 - 0x24 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_10 - Digital I/O control for port 0 pins PIO0_10 - 0x28 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_11 - Digital I/O control for port 0 pins PIO0_11 - 0x2C - 32 - read-write - 0x116 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_12 - Digital I/O control for port 0 pins PIO0_12 - 0x30 - 32 - read-write - 0x126 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_13 - Digital I/O control for port 0 pins PIO0_13 - 0x34 - 32 - read-write - 0x5000 - 0xFFFF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - SSEL - Supply Selection bit. - 11 - 1 - read-write - - - SEL3V3 - 3V3 Signaling in I2C Mode. - 0 - - - SEL1V8 - 1V8 Signaling in I2C Mode. - 0x1 - - - - - FILTEROFF - Controls input glitch filter. - 12 - 1 - read-write - - - ENABLED - Filter enabled. - 0 - - - DISABLED - Filter disabled. - 0x1 - - - - - ECS - Pull-up current source enable in I2C mode. - 13 - 1 - read-write - - - DISABLED - Disabled. IO is in open drain cell. - 0 - - - ENABLED - Enabled. Pull resistor is conencted. - 0x1 - - - - - EGP - Switch between GPIO mode and I2C mode. - 14 - 1 - read-write - - - I2C_MODE - I2C mode. - 0 - - - GPIO_MODE - GPIO mode. - 0x1 - - - - - I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. - 15 - 1 - read-write - - - FAST_MODE - I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. - 0 - - - STANDARD_MODE - I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. - 0x1 - - - - - - - PIO0_14 - Digital I/O control for port 0 pins PIO0_14 - 0x38 - 32 - read-write - 0x5000 - 0xFFFF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - SSEL - Supply Selection bit. - 11 - 1 - read-write - - - SEL3V3 - 3V3 Signaling in I2C Mode. - 0 - - - SEL1V8 - 1V8 Signaling in I2C Mode. - 0x1 - - - - - FILTEROFF - Controls input glitch filter. - 12 - 1 - read-write - - - ENABLED - Filter enabled. - 0 - - - DISABLED - Filter disabled. - 0x1 - - - - - ECS - Pull-up current source enable in I2C mode. - 13 - 1 - read-write - - - DISABLED - Disabled. IO is in open drain cell. - 0 - - - ENABLED - Enabled. Pull resistor is conencted. - 0x1 - - - - - EGP - Switch between GPIO mode and I2C mode. - 14 - 1 - read-write - - - I2C_MODE - I2C mode. - 0 - - - GPIO_MODE - GPIO mode. - 0x1 - - - - - I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. - 15 - 1 - read-write - - - FAST_MODE - I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. - 0 - - - STANDARD_MODE - I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. - 0x1 - - - - - - - PIO0_15 - Digital I/O control for port 0 pins PIO0_15 - 0x3C - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_16 - Digital I/O control for port 0 pins PIO0_16 - 0x40 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_17 - Digital I/O control for port 0 pins PIO0_17 - 0x44 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_18 - Digital I/O control for port 0 pins PIO0_18 - 0x48 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_19 - Digital I/O control for port 0 pins PIO0_19 - 0x4C - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_20 - Digital I/O control for port 0 pins PIO0_20 - 0x50 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_21 - Digital I/O control for port 0 pins PIO0_21 - 0x54 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_22 - Digital I/O control for port 0 pins PIO0_22 - 0x58 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_23 - Digital I/O control for port 0 pins PIO0_23 - 0x5C - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_24 - Digital I/O control for port 0 pins PIO0_24 - 0x60 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_25 - Digital I/O control for port 0 pins PIO0_25 - 0x64 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_26 - Digital I/O control for port 0 pins PIO0_26 - 0x68 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_27 - Digital I/O control for port 0 pins PIO0_27 - 0x6C - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_28 - Digital I/O control for port 0 pins PIO0_28 - 0x70 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_29 - Digital I/O control for port 0 pins PIO0_29 - 0x74 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_30 - Digital I/O control for port 0 pins PIO0_30 - 0x78 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_31 - Digital I/O control for port 0 pins PIO0_31 - 0x7C - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO1_0 - Digital I/O control for port 1 pins PIO1_0 - 0x80 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO1_1 - Digital I/O control for port 1 pins PIO1_1 - 0x84 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_2 - Digital I/O control for port 1 pins PIO1_2 - 0x88 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_3 - Digital I/O control for port 1 pins PIO1_3 - 0x8C - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_4 - Digital I/O control for port 1 pins PIO1_4 - 0x90 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_5 - Digital I/O control for port 1 pins PIO1_5 - 0x94 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_6 - Digital I/O control for port 1 pins PIO1_6 - 0x98 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_7 - Digital I/O control for port 1 pins PIO1_7 - 0x9C - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_8 - Digital I/O control for port 1 pins PIO1_8 - 0xA0 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO1_9 - Digital I/O control for port 1 pins PIO1_9 - 0xA4 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO1_10 - Digital I/O control for port 1 pins PIO1_10 - 0xA8 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_11 - Digital I/O control for port 1 pins PIO1_11 - 0xAC - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_12 - Digital I/O control for port 1 pins PIO1_12 - 0xB0 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_13 - Digital I/O control for port 1 pins PIO1_13 - 0xB4 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_14 - Digital I/O control for port 1 pins PIO1_14 - 0xB8 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO1_15 - Digital I/O control for port 1 pins PIO1_15 - 0xBC - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_16 - Digital I/O control for port 1 pins PIO1_16 - 0xC0 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_17 - Digital I/O control for port 1 pins PIO1_17 - 0xC4 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_18 - Digital I/O control for port 1 pins PIO1_18 - 0xC8 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_19 - Digital I/O control for port 1 pins PIO1_19 - 0xCC - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO1_20 - Digital I/O control for port 1 pins PIO1_20 - 0xD0 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_21 - Digital I/O control for port 1 pins PIO1_21 - 0xD4 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_22 - Digital I/O control for port 1 pins PIO1_22 - 0xD8 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_23 - Digital I/O control for port 1 pins PIO1_23 - 0xDC - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_24 - Digital I/O control for port 1 pins PIO1_24 - 0xE0 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_25 - Digital I/O control for port 1 pins PIO1_25 - 0xE4 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_26 - Digital I/O control for port 1 pins PIO1_26 - 0xE8 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_27 - Digital I/O control for port 1 pins PIO1_27 - 0xEC - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_28 - Digital I/O control for port 1 pins PIO1_28 - 0xF0 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_29 - Digital I/O control for port 1 pins PIO1_29 - 0xF4 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_30 - Digital I/O control for port 1 pins PIO1_30 - 0xF8 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_31 - Digital I/O control for port 1 pins PIO1_31 - 0xFC - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - - - GINT0 - Group GPIO input interrupt (GINT0/1) - GINT - GINT - 0x40002000 - - 0 - 0x48 - registers - - - GINT0 - 2 - - - - CTRL - GPIO grouped interrupt control register - 0 - 32 - read-write - 0 - 0x7 - - - INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. - 0 - 1 - read-write - - - NO_REQUEST - No request. No interrupt request is pending. - 0 - - - REQUEST_ACTIVE - Request active. Interrupt request is active. - 0x1 - - - - - COMB - Combine enabled inputs for group interrupt - 1 - 1 - read-write - - - OR - Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). - 0 - - - AND - And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). - 0x1 - - - - - TRIG - Group interrupt trigger - 2 - 1 - read-write - - - EDGE_TRIGGERED - Edge-triggered. - 0 - - - LEVEL_TRIGGERED - Level-triggered. - 0x1 - - - - - - - 2 - 0x4 - PORT_POL[%s] - GPIO grouped interrupt port 0 polarity register - 0x20 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. - 0 - 32 - read-write - - - - - 2 - 0x4 - PORT_ENA[%s] - GPIO grouped interrupt port 0 enable register - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. - 0 - 32 - read-write - - - - - - - GINT1 - Group GPIO input interrupt (GINT0/1) - GINT - 0x40003000 - - 0 - 0x48 - registers - - - GINT1 - 3 - - - - PINT - Pin interrupt and pattern match (PINT) - PINT - PINT - 0x40004000 - - 0 - 0x34 - registers - - - PIN_INT0 - 4 - - - PIN_INT1 - 5 - - - PIN_INT2 - 6 - - - PIN_INT3 - 7 - - - PIN_INT4 - 32 - - - PIN_INT5 - 33 - - - PIN_INT6 - 34 - - - PIN_INT7 - 35 - - - - ISEL - Pin Interrupt Mode register - 0 - 32 - read-write - 0 - 0xFF - - - PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive - 0 - 8 - read-write - - - - - IENR - Pin interrupt level or rising edge interrupt enable register - 0x4 - 32 - read-write - 0 - 0xFF - - - ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. - 0 - 8 - read-write - - - - - SIENR - Pin interrupt level or rising edge interrupt set register - 0x8 - 32 - write-only - 0 - 0 - - - SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. - 0 - 8 - write-only - - - - - CIENR - Pin interrupt level (rising edge interrupt) clear register - 0xC - 32 - write-only - 0 - 0 - - - CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. - 0 - 8 - write-only - - - - - IENF - Pin interrupt active level or falling edge interrupt enable register - 0x10 - 32 - read-write - 0 - 0xFF - - - ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. - 0 - 8 - read-write - - - - - SIENF - Pin interrupt active level or falling edge interrupt set register - 0x14 - 32 - write-only - 0 - 0 - - - SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. - 0 - 8 - write-only - - - - - CIENF - Pin interrupt active level or falling edge interrupt clear register - 0x18 - 32 - write-only - 0 - 0 - - - CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. - 0 - 8 - write-only - - - - - RISE - Pin interrupt rising edge register - 0x1C - 32 - read-write - 0 - 0xFF - - - RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. - 0 - 8 - read-write - - - - - FALL - Pin interrupt falling edge register - 0x20 - 32 - read-write - 0 - 0xFF - - - FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. - 0 - 8 - read-write - - - - - IST - Pin interrupt status register - 0x24 - 32 - read-write - 0 - 0xFF - - - PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). - 0 - 8 - read-write - - - - - PMCTRL - Pattern match interrupt control register - 0x28 - 32 - read-write - 0 - 0xFF000003 - - - SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. - 0 - 1 - read-write - - - PIN_INTERRUPT - Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. - 0 - - - PATTERN_MATCH - Pattern match. Interrupts are driven in response to pattern matches. - 0x1 - - - - - ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. - 1 - 1 - read-write - - - DISABLED - Disabled. RXEV output to the CPU is disabled. - 0 - - - ENABLED - Enabled. RXEV output to the CPU is enabled. - 0x1 - - - - - PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs. - 24 - 8 - read-write - - - - - PMSRC - Pattern match interrupt bit-slice source register - 0x2C - 32 - read-write - 0 - 0xFFFFFF00 - - - SRC0 - Selects the input source for bit slice 0 - 8 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. - 0x7 - - - - - SRC1 - Selects the input source for bit slice 1 - 11 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. - 0x7 - - - - - SRC2 - Selects the input source for bit slice 2 - 14 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. - 0x7 - - - - - SRC3 - Selects the input source for bit slice 3 - 17 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. - 0x7 - - - - - SRC4 - Selects the input source for bit slice 4 - 20 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. - 0x7 - - - - - SRC5 - Selects the input source for bit slice 5 - 23 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. - 0x7 - - - - - SRC6 - Selects the input source for bit slice 6 - 26 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. - 0x7 - - - - - SRC7 - Selects the input source for bit slice 7 - 29 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. - 0x7 - - - - - - - PMCFG - Pattern match interrupt bit slice configuration register - 0x30 - 32 - read-write - 0 - 0xFFFFFF7F - - - PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. - 0 - 1 - read-write - - - NO_EFFECT - No effect. Slice 0 is not an endpoint. - 0 - - - ENDPOINT - endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. - 0x1 - - - - - PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. - 1 - 1 - read-write - - - NO_EFFECT - No effect. Slice 1 is not an endpoint. - 0 - - - ENDPOINT - endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. - 0x1 - - - - - PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. - 2 - 1 - read-write - - - NO_EFFECT - No effect. Slice 2 is not an endpoint. - 0 - - - ENDPOINT - endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. - 0x1 - - - - - PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. - 3 - 1 - read-write - - - NO_EFFECT - No effect. Slice 3 is not an endpoint. - 0 - - - ENDPOINT - endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. - 0x1 - - - - - PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. - 4 - 1 - read-write - - - NO_EFFECT - No effect. Slice 4 is not an endpoint. - 0 - - - ENDPOINT - endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. - 0x1 - - - - - PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. - 5 - 1 - read-write - - - NO_EFFECT - No effect. Slice 5 is not an endpoint. - 0 - - - ENDPOINT - endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. - 0x1 - - - - - PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. - 6 - 1 - read-write - - - NO_EFFECT - No effect. Slice 6 is not an endpoint. - 0 - - - ENDPOINT - endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. - 0x1 - - - - - CFG0 - Specifies the match contribution condition for bit slice 0. - 8 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - CFG1 - Specifies the match contribution condition for bit slice 1. - 11 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - CFG2 - Specifies the match contribution condition for bit slice 2. - 14 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - CFG3 - Specifies the match contribution condition for bit slice 3. - 17 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - CFG4 - Specifies the match contribution condition for bit slice 4. - 20 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - CFG5 - Specifies the match contribution condition for bit slice 5. - 23 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - CFG6 - Specifies the match contribution condition for bit slice 6. - 26 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - CFG7 - Specifies the match contribution condition for bit slice 7. - 29 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - - - - - SECPINT - Pin interrupt and pattern match (PINT) - PINT - 0x40005000 - - 0 - 0x34 - registers - - - SEC_HYPERVISOR_CALL - 49 - - - SEC_GPIO_INT0_IRQ0 - 50 - - - SEC_GPIO_INT0_IRQ1 - 51 - - - SEC_VIO - 53 - - - - INPUTMUX - Input multiplexing (INPUT MUX) - INPUTMUX - 0x40006000 - - 0 - 0x7B4 - registers - - - - 7 - 0x4 - SCT0_INMUX[%s] - Input mux register for SCT0 input - 0 - 32 - read-write - 0x1F - 0x1F - - - INP_N - Input number to SCT0 inputs 0 to 6.. - 0 - 5 - read-write - - - val0 - SCT_GPI0 function selected from IOCON register - 0 - - - val1 - SCT_GPI1 function selected from IOCON register - 0x1 - - - val2 - SCT_GPI2 function selected from IOCON register - 0x2 - - - val3 - SCT_GPI3 function selected from IOCON register - 0x3 - - - val4 - SCT_GPI4 function selected from IOCON register - 0x4 - - - val5 - SCT_GPI5 function selected from IOCON register - 0x5 - - - val6 - SCT_GPI6 function selected from IOCON register - 0x6 - - - val7 - SCT_GPI7 function selected from IOCON register - 0x7 - - - val8 - T0_OUT0 ctimer 0 match[0] output - 0x8 - - - val9 - T1_OUT0 ctimer 1 match[0] output - 0x9 - - - val10 - T2_OUT0 ctimer 2 match[0] output - 0xA - - - val11 - T3_OUT0 ctimer 3 match[0] output - 0xB - - - val12 - T4_OUT0 ctimer 4 match[0] output - 0xC - - - val13 - ADC_IRQ interrupt request from ADC - 0xD - - - val14 - GPIOINT_BMATCH - 0xE - - - val15 - USB0_FRAME_TOGGLE - 0xF - - - val16 - USB1_FRAME_TOGGLE - 0x10 - - - val17 - COMP_OUTPUT output from analog comparator - 0x11 - - - val18 - I2S_SHARED_SCK[0] output from I2S pin sharing - 0x12 - - - val19 - I2S_SHARED_SCK[1] output from I2S pin sharing - 0x13 - - - val20 - I2S_SHARED_WS[0] output from I2S pin sharing - 0x14 - - - val21 - I2S_SHARED_WS[1] output from I2S pin sharing - 0x15 - - - val22 - ARM_TXEV interrupt event from cpu0 or cpu1 - 0x16 - - - val23 - DEBUG_HALTED from cpu0 or cpu1 - 0x17 - - - val24 - None - 0x18 - - - val24 - None - 0x19 - - - val24 - None - 0x1A - - - val24 - None - 0x1B - - - val24 - None - 0x1C - - - val24 - None - 0x1D - - - val24 - None - 0x1E - - - val24 - None - 0x1F - - - - - - - 4 - 0x4 - TIMER0CAPTSEL[%s] - Capture select registers for TIMER0 inputs - 0x20 - 32 - read-write - 0x1F - 0x1F - - - CAPTSEL - Input number to TIMER0 capture inputs 0 to 4 - 0 - 5 - read-write - - - val0 - CT_INP0 function selected from IOCON register - 0 - - - val1 - CT_INP1 function selected from IOCON register - 0x1 - - - val2 - CT_INP2 function selected from IOCON register - 0x2 - - - val3 - CT_INP3 function selected from IOCON register - 0x3 - - - val4 - CT_INP4 function selected from IOCON register - 0x4 - - - val5 - CT_INP5 function selected from IOCON register - 0x5 - - - val6 - CT_INP6 function selected from IOCON register - 0x6 - - - val7 - CT_INP7 function selected from IOCON register - 0x7 - - - val8 - CT_INP8 function selected from IOCON register - 0x8 - - - val9 - CT_INP9 function selected from IOCON register - 0x9 - - - val10 - CT_INP10 function selected from IOCON register - 0xA - - - val11 - CT_INP11 function selected from IOCON register - 0xB - - - val12 - CT_INP12 function selected from IOCON register - 0xC - - - val13 - CT_INP13 function selected from IOCON register - 0xD - - - val14 - CT_INP14 function selected from IOCON register - 0xE - - - val15 - CT_INP15 function selected from IOCON register - 0xF - - - val16 - CT_INP16 function selected from IOCON register - 0x10 - - - val17 - None - 0x11 - - - val18 - None - 0x12 - - - val19 - None - 0x13 - - - val20 - USB0_FRAME_TOGGLE - 0x14 - - - val21 - USB1_FRAME_TOGGLE - 0x15 - - - val22 - COMP_OUTPUT output from analog comparator - 0x16 - - - val23 - I2S_SHARED_WS[0] output from I2S pin sharing - 0x17 - - - val24 - I2S_SHARED_WS[1] output from I2S pin sharing - 0x18 - - - val25 - None - 0x19 - - - val25 - None - 0x1A - - - val25 - None - 0x1B - - - val25 - None - 0x1C - - - val25 - None - 0x1D - - - val25 - None - 0x1E - - - val25 - None - 0x1F - - - - - - - 4 - 0x4 - TIMER1CAPTSEL[%s] - Capture select registers for TIMER1 inputs - 0x40 - 32 - read-write - 0x1F - 0x1F - - - CAPTSEL - Input number to TIMER1 capture inputs 0 to 4 - 0 - 5 - read-write - - - val0 - CT_INP0 function selected from IOCON register - 0 - - - val1 - CT_INP1 function selected from IOCON register - 0x1 - - - val2 - CT_INP2 function selected from IOCON register - 0x2 - - - val3 - CT_INP3 function selected from IOCON register - 0x3 - - - val4 - CT_INP4 function selected from IOCON register - 0x4 - - - val5 - CT_INP5 function selected from IOCON register - 0x5 - - - val6 - CT_INP6 function selected from IOCON register - 0x6 - - - val7 - CT_INP7 function selected from IOCON register - 0x7 - - - val8 - CT_INP8 function selected from IOCON register - 0x8 - - - val9 - CT_INP9 function selected from IOCON register - 0x9 - - - val10 - CT_INP10 function selected from IOCON register - 0xA - - - val11 - CT_INP11 function selected from IOCON register - 0xB - - - val12 - CT_INP12 function selected from IOCON register - 0xC - - - val13 - CT_INP13 function selected from IOCON register - 0xD - - - val14 - CT_INP14 function selected from IOCON register - 0xE - - - val15 - CT_INP15 function selected from IOCON register - 0xF - - - val16 - CT_INP16 function selected from IOCON register - 0x10 - - - val17 - None - 0x11 - - - val18 - None - 0x12 - - - val19 - None - 0x13 - - - val20 - USB0_FRAME_TOGGLE - 0x14 - - - val21 - USB1_FRAME_TOGGLE - 0x15 - - - val22 - COMP_OUTPUT output from analog comparator - 0x16 - - - val23 - I2S_SHARED_WS[0] output from I2S pin sharing - 0x17 - - - val24 - I2S_SHARED_WS[1] output from I2S pin sharing - 0x18 - - - val25 - None - 0x19 - - - val25 - None - 0x1A - - - val25 - None - 0x1B - - - val25 - None - 0x1C - - - val25 - None - 0x1D - - - val25 - None - 0x1E - - - val25 - None - 0x1F - - - - - - - 4 - 0x4 - TIMER2CAPTSEL[%s] - Capture select registers for TIMER2 inputs - 0x60 - 32 - read-write - 0x1F - 0x1F - - - CAPTSEL - Input number to TIMER2 capture inputs 0 to 4 - 0 - 5 - read-write - - - val0 - CT_INP0 function selected from IOCON register - 0 - - - val1 - CT_INP1 function selected from IOCON register - 0x1 - - - val2 - CT_INP2 function selected from IOCON register - 0x2 - - - val3 - CT_INP3 function selected from IOCON register - 0x3 - - - val4 - CT_INP4 function selected from IOCON register - 0x4 - - - val5 - CT_INP5 function selected from IOCON register - 0x5 - - - val6 - CT_INP6 function selected from IOCON register - 0x6 - - - val7 - CT_INP7 function selected from IOCON register - 0x7 - - - val8 - CT_INP8 function selected from IOCON register - 0x8 - - - val9 - CT_INP9 function selected from IOCON register - 0x9 - - - val10 - CT_INP10 function selected from IOCON register - 0xA - - - val11 - CT_INP11 function selected from IOCON register - 0xB - - - val12 - CT_INP12 function selected from IOCON register - 0xC - - - val13 - CT_INP13 function selected from IOCON register - 0xD - - - val14 - CT_INP14 function selected from IOCON register - 0xE - - - val15 - CT_INP15 function selected from IOCON register - 0xF - - - val16 - CT_INP16 function selected from IOCON register - 0x10 - - - val17 - None - 0x11 - - - val18 - None - 0x12 - - - val19 - None - 0x13 - - - val20 - USB0_FRAME_TOGGLE - 0x14 - - - val21 - USB1_FRAME_TOGGLE - 0x15 - - - val22 - COMP_OUTPUT output from analog comparator - 0x16 - - - val23 - I2S_SHARED_WS[0] output from I2S pin sharing - 0x17 - - - val24 - I2S_SHARED_WS[1] output from I2S pin sharing - 0x18 - - - val25 - None - 0x19 - - - val25 - None - 0x1A - - - val25 - None - 0x1B - - - val25 - None - 0x1C - - - val25 - None - 0x1D - - - val25 - None - 0x1E - - - val25 - None - 0x1F - - - - - - - 8 - 0x4 - PINTSEL[%s] - Pin interrupt select register - 0xC0 - 32 - read-write - 0x7F - 0x7F - - - INTPIN - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. - 0 - 7 - read-write - - - - - 23 - 0x4 - DMA0_ITRIG_INMUX[%s] - Trigger select register for DMA0 channel - 0xE0 - 32 - read-write - 0x1F - 0x1F - - - INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22). - 0 - 5 - read-write - - - val0 - Pin interrupt 0 - 0 - - - val1 - Pin interrupt 1 - 0x1 - - - val2 - Pin interrupt 2 - 0x2 - - - val3 - Pin interrupt 3 - 0x3 - - - val4 - Timer CTIMER0 Match 0 - 0x4 - - - val5 - Timer CTIMER0 Match 1 - 0x5 - - - val6 - Timer CTIMER1 Match 0 - 0x6 - - - val7 - Timer CTIMER1 Match 1 - 0x7 - - - val8 - Timer CTIMER2 Match 0 - 0x8 - - - val9 - Timer CTIMER2 Match 1 - 0x9 - - - val10 - Timer CTIMER3 Match 0 - 0xA - - - val11 - Timer CTIMER3 Match 1 - 0xB - - - val12 - Timer CTIMER4 Match 0 - 0xC - - - val13 - Timer CTIMER4 Match 1 - 0xD - - - val14 - COMP_OUTPUT - 0xE - - - val15 - DMA0 output trigger mux 0 - 0xF - - - val16 - DMA0 output trigger mux 1 - 0x10 - - - val17 - DMA0 output trigger mux 1 - 0x11 - - - val18 - DMA0 output trigger mux 3 - 0x12 - - - val19 - SCT0 DMA request 0 - 0x13 - - - val20 - SCT0 DMA request 1 - 0x14 - - - val21 - HASH DMA RX trigger - 0x15 - - - val22 - None - 0x16 - - - val22 - None - 0x17 - - - val22 - None - 0x18 - - - val22 - None - 0x19 - - - val22 - None - 0x1A - - - val22 - None - 0x1B - - - val22 - None - 0x1C - - - val22 - None - 0x1D - - - val22 - None - 0x1E - - - val22 - None - 0x1F - - - - - - - 4 - 0x4 - DMA0_OTRIG_INMUX[%s] - DMA0 output trigger selection to become DMA0 trigger - 0x160 - 32 - read-write - 0x1F - 0x1F - - - INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22). - 0 - 5 - read-write - - - - - FREQMEAS_REF - Selection for frequency measurement reference clock - 0x180 - 32 - read-write - 0x1F - 0x1F - - - CLKIN - Clock source number (decimal value) for frequency measure function reference clock: - 0 - 5 - read-write - - - VALUE0 - External main crystal oscilator (Clock_in). - 0 - - - VALUE1 - FRO 12MHz clock. - 0x1 - - - VALUE2 - FRO 96MHz clock. - 0x2 - - - VALUE3 - Watchdog oscillator / FRO1MHz clock. - 0x3 - - - VALUE4 - 32 kHz oscillator (32k_clk) clock. - 0x4 - - - VALUE5 - main clock (main_clock). - 0x5 - - - VALUE6 - FREQME_GPIO_CLK_A. - 0x6 - - - VALUE7 - FREQME_GPIO_CLK_B. - 0x7 - - - - - - - FREQMEAS_TARGET - Selection for frequency measurement target clock - 0x184 - 32 - read-write - 0x1F - 0x1F - - - CLKIN - Clock source number (decimal value) for frequency measure function target clock: - 0 - 5 - read-write - - - VALUE0 - External main crystal oscilator (Clock_in). - 0 - - - VALUE1 - FRO 12MHz clock. - 0x1 - - - VALUE2 - FRO 96MHz clock. - 0x2 - - - VALUE3 - Watchdog oscillator / FRO1MHz clock. - 0x3 - - - VALUE4 - 32 kHz oscillator (32k_clk) clock. - 0x4 - - - VALUE5 - main clock (main_clock). - 0x5 - - - VALUE6 - FREQME_GPIO_CLK_A. - 0x6 - - - VALUE7 - FREQME_GPIO_CLK_B. - 0x7 - - - - - - - 4 - 0x4 - TIMER3CAPTSEL[%s] - Capture select registers for TIMER3 inputs - 0x1A0 - 32 - read-write - 0x1F - 0x1F - - - CAPTSEL - Input number to TIMER3 capture inputs 0 to 4 - 0 - 5 - read-write - - - val0 - CT_INP0 function selected from IOCON register - 0 - - - val1 - CT_INP1 function selected from IOCON register - 0x1 - - - val2 - CT_INP2 function selected from IOCON register - 0x2 - - - val3 - CT_INP3 function selected from IOCON register - 0x3 - - - val4 - CT_INP4 function selected from IOCON register - 0x4 - - - val5 - CT_INP5 function selected from IOCON register - 0x5 - - - val6 - CT_INP6 function selected from IOCON register - 0x6 - - - val7 - CT_INP7 function selected from IOCON register - 0x7 - - - val8 - CT_INP8 function selected from IOCON register - 0x8 - - - val9 - CT_INP9 function selected from IOCON register - 0x9 - - - val10 - CT_INP10 function selected from IOCON register - 0xA - - - val11 - CT_INP11 function selected from IOCON register - 0xB - - - val12 - CT_INP12 function selected from IOCON register - 0xC - - - val13 - CT_INP13 function selected from IOCON register - 0xD - - - val14 - CT_INP14 function selected from IOCON register - 0xE - - - val15 - CT_INP15 function selected from IOCON register - 0xF - - - val16 - CT_INP16 function selected from IOCON register - 0x10 - - - val17 - CT_INP17 function selected from IOCON register - 0x11 - - - val18 - CT_INP18 function selected from IOCON register - 0x12 - - - val19 - CT_INP19 function selected from IOCON register - 0x13 - - - val20 - USB0_FRAME_TOGGLE - 0x14 - - - val21 - USB1_FRAME_TOGGLE - 0x15 - - - val22 - COMP_OUTPUT output from analog comparator - 0x16 - - - val23 - I2S_SHARED_WS[0] output from I2S pin sharing - 0x17 - - - val24 - I2S_SHARED_WS[1] output from I2S pin sharing - 0x18 - - - val25 - None - 0x19 - - - val25 - None - 0x1A - - - val25 - None - 0x1B - - - val25 - None - 0x1C - - - val25 - None - 0x1D - - - val25 - None - 0x1E - - - val25 - None - 0x1F - - - - - - - 4 - 0x4 - TIMER4CAPTSEL[%s] - Capture select registers for TIMER4 inputs - 0x1C0 - 32 - read-write - 0x1F - 0x1F - - - CAPTSEL - Input number to TIMER4 capture inputs 0 to 4 - 0 - 5 - read-write - - - val0 - CT_INP0 function selected from IOCON register - 0 - - - val1 - CT_INP1 function selected from IOCON register - 0x1 - - - val2 - CT_INP2 function selected from IOCON register - 0x2 - - - val3 - CT_INP3 function selected from IOCON register - 0x3 - - - val4 - CT_INP4 function selected from IOCON register - 0x4 - - - val5 - CT_INP5 function selected from IOCON register - 0x5 - - - val6 - CT_INP6 function selected from IOCON register - 0x6 - - - val7 - CT_INP7 function selected from IOCON register - 0x7 - - - val8 - CT_INP8 function selected from IOCON register - 0x8 - - - val9 - CT_INP9 function selected from IOCON register - 0x9 - - - val10 - CT_INP10 function selected from IOCON register - 0xA - - - val11 - CT_INP11 function selected from IOCON register - 0xB - - - val12 - CT_INP12 function selected from IOCON register - 0xC - - - val13 - CT_INP13 function selected from IOCON register - 0xD - - - val14 - CT_INP14 function selected from IOCON register - 0xE - - - val15 - CT_INP15 function selected from IOCON register - 0xF - - - val16 - CT_INP16 function selected from IOCON register - 0x10 - - - val17 - CT_INP17 function selected from IOCON register - 0x11 - - - val18 - CT_INP18 function selected from IOCON register - 0x12 - - - val19 - CT_INP19 function selected from IOCON register - 0x13 - - - val20 - USB0_FRAME_TOGGLE - 0x14 - - - val21 - USB1_FRAME_TOGGLE - 0x15 - - - val22 - COMP_OUTPUT output from analog comparator - 0x16 - - - val23 - I2S_SHARED_WS[0] output from I2S pin sharing - 0x17 - - - val24 - I2S_SHARED_WS[1] output from I2S pin sharing - 0x18 - - - val25 - None - 0x19 - - - val25 - None - 0x1A - - - val25 - None - 0x1B - - - val25 - None - 0x1C - - - val25 - None - 0x1D - - - val25 - None - 0x1E - - - val25 - None - 0x1F - - - - - - - 2 - 0x4 - PINTSECSEL[%s] - Pin interrupt secure select register - 0x1E0 - 32 - read-write - 0x3F - 0x3F - - - INTPIN - Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31. - 0 - 6 - read-write - - - - - 10 - 0x4 - DMA1_ITRIG_INMUX[%s] - Trigger select register for DMA1 channel - 0x200 - 32 - read-write - 0xF - 0xF - - - INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9). - 0 - 4 - read-write - - - val0 - Pin interrupt 0 - 0 - - - val1 - Pin interrupt 1 - 0x1 - - - val2 - Pin interrupt 2 - 0x2 - - - val3 - Pin interrupt 3 - 0x3 - - - val4 - Timer CTIMER0 Match 0 - 0x4 - - - val5 - Timer CTIMER0 Match 1 - 0x5 - - - val6 - Timer CTIMER2 Match 0 - 0x6 - - - val7 - Timer CTIMER4 Match 0 - 0x7 - - - val8 - DMA1 output trigger mux 0 - 0x8 - - - val9 - DMA1 output trigger mux 1 - 0x9 - - - val10 - DMA1 output trigger mux 2 - 0xA - - - val11 - DMA1 output trigger mux 3 - 0xB - - - val12 - SCT0 DMA request 0 - 0xC - - - val13 - SCT0 DMA request 1 - 0xD - - - val14 - HASH DMA RX trigger - 0xE - - - val15 - None - 0xF - - - - - - - 4 - 0x4 - DMA1_OTRIG_INMUX[%s] - DMA1 output trigger selection to become DMA1 trigger - 0x240 - 32 - read-write - 0xF - 0xF - - - INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9). - 0 - 4 - read-write - - - - - DMA0_REQ_ENA - Enable DMA0 requests - 0x740 - 32 - read-write - 0x7FFFFF - 0x7FFFFF - - - REQ_ENA - Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - 0 - 23 - read-write - - - - - DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register - 0x748 - 32 - write-only - 0 - 0x7FFFFF - - - SET - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register - 0 - 23 - write-only - - - - - DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register - 0x750 - 32 - write-only - 0 - 0x7FFFFF - - - CLR - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register - 0 - 23 - write-only - - - - - DMA1_REQ_ENA - Enable DMA1 requests - 0x760 - 32 - read-write - 0x3FF - 0x3FF - - - REQ_ENA - Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - 0 - 10 - read-write - - - - - DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register - 0x768 - 32 - write-only - 0 - 0x3FF - - - SET - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register - 0 - 10 - write-only - - - - - DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register - 0x770 - 32 - write-only - 0 - 0x3FF - - - CLR - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register - 0 - 10 - write-only - - - - - DMA0_ITRIG_ENA - Enable DMA0 triggers - 0x780 - 32 - read-write - 0x3FFFFF - 0x3FFFFF - - - ITRIG_ENA - Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - 0 - 22 - read-write - - - - - DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register - 0x788 - 32 - write-only - 0 - 0x3FFFFF - - - SET - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no change in DMA0_ITRIG_ENA register - 0 - 22 - write-only - - - - - DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register - 0x790 - 32 - write-only - 0 - 0x3FFFFF - - - CLR - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_ITRIG_ENA register - 0 - 22 - write-only - - - - - DMA1_ITRIG_ENA - Enable DMA1 triggers - 0x7A0 - 32 - read-write - 0x7FFF - 0x7FFF - - - ITRIG_ENA - Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - 0 - 15 - read-write - - - - - DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register - 0x7A8 - 32 - write-only - 0 - 0x7FFF - - - SET - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no change in DMA1_ITRIG_ENA register - 0 - 15 - write-only - - - - - DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register - 0x7B0 - 32 - write-only - 0 - 0x7FFF - - - CLR - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIG_ENA register - 0 - 15 - write-only - - - - - - - CTIMER0 - Standard counter/timers (CTIMER0 to 4) - CTIMER - CTIMER - 0x40008000 - - 0 - 0x88 - registers - - - CTIMER0 - 10 - - - - IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. - 0 - 32 - read-write - 0 - 0xFF - - - MR0INT - Interrupt flag for match channel 0. - 0 - 1 - read-write - - - MR1INT - Interrupt flag for match channel 1. - 1 - 1 - read-write - - - MR2INT - Interrupt flag for match channel 2. - 2 - 1 - read-write - - - MR3INT - Interrupt flag for match channel 3. - 3 - 1 - read-write - - - CR0INT - Interrupt flag for capture channel 0 event. - 4 - 1 - read-write - - - CR1INT - Interrupt flag for capture channel 1 event. - 5 - 1 - read-write - - - CR2INT - Interrupt flag for capture channel 2 event. - 6 - 1 - read-write - - - CR3INT - Interrupt flag for capture channel 3 event. - 7 - 1 - read-write - - - - - TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. - 0x4 - 32 - read-write - 0 - 0x3 - - - CEN - Counter enable. - 0 - 1 - read-write - - - DISABLED - Disabled.The counters are disabled. - 0 - - - ENABLED - Enabled. The Timer Counter and Prescale Counter are enabled. - 0x1 - - - - - CRST - Counter reset. - 1 - 1 - read-write - - - DISABLED - Disabled. Do nothing. - 0 - - - ENABLED - Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero. - 0x1 - - - - - - - TC - Timer Counter - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - TCVAL - Timer counter value. - 0 - 32 - read-write - - - - - PR - Prescale Register - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - PRVAL - Prescale counter value. - 0 - 32 - read-write - - - - - PC - Prescale Counter - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - PCVAL - Prescale counter value. - 0 - 32 - read-write - - - - - MCR - Match Control Register - 0x14 - 32 - read-write - 0 - 0xF000FFF - - - MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. - 0 - 1 - read-write - - - MR0R - Reset on MR0: the TC will be reset if MR0 matches it. - 1 - 1 - read-write - - - MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. - 2 - 1 - read-write - - - MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. - 3 - 1 - read-write - - - MR1R - Reset on MR1: the TC will be reset if MR1 matches it. - 4 - 1 - read-write - - - MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. - 5 - 1 - read-write - - - MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. - 6 - 1 - read-write - - - MR2R - Reset on MR2: the TC will be reset if MR2 matches it. - 7 - 1 - read-write - - - MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. - 8 - 1 - read-write - - - MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. - 9 - 1 - read-write - - - MR3R - Reset on MR3: the TC will be reset if MR3 matches it. - 10 - 1 - read-write - - - MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. - 11 - 1 - read-write - - - MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). - 24 - 1 - read-write - - - MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). - 25 - 1 - read-write - - - MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). - 26 - 1 - read-write - - - MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). - 27 - 1 - read-write - - - - - 4 - 0x4 - MR[%s] - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. - 0x18 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCH - Timer counter match value. - 0 - 32 - read-write - - - - - CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. - 0x28 - 32 - read-write - 0 - 0xFFF - - - CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 0 - 1 - read-write - - - CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 1 - 1 - read-write - - - CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. - 2 - 1 - read-write - - - CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 3 - 1 - read-write - - - CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 4 - 1 - read-write - - - CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. - 5 - 1 - read-write - - - CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 6 - 1 - read-write - - - CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 7 - 1 - read-write - - - CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. - 8 - 1 - read-write - - - CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 9 - 1 - read-write - - - CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 10 - 1 - read-write - - - CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. - 11 - 1 - read-write - - - - - 4 - 0x4 - CR[%s] - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. - 0x2C - 32 - read-only - 0 - 0xFFFFFFFF - - - CAP - Timer counter capture value. - 0 - 32 - read-only - - - - - EMR - External Match Register. The EMR controls the match function and the external match pins. - 0x3C - 32 - read-write - 0 - 0xFFF - - - EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - 0 - 1 - read-write - - - EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - 1 - 1 - read-write - - - EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - 2 - 1 - read-write - - - EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - 3 - 1 - read-write - - - EMC0 - External Match Control 0. Determines the functionality of External Match 0. - 4 - 2 - read-write - - - DO_NOTHING - Do Nothing. - 0 - - - CLEAR - Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). - 0x1 - - - SET - Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). - 0x2 - - - TOGGLE - Toggle. Toggle the corresponding External Match bit/output. - 0x3 - - - - - EMC1 - External Match Control 1. Determines the functionality of External Match 1. - 6 - 2 - read-write - - - DO_NOTHING - Do Nothing. - 0 - - - CLEAR - Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). - 0x1 - - - SET - Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). - 0x2 - - - TOGGLE - Toggle. Toggle the corresponding External Match bit/output. - 0x3 - - - - - EMC2 - External Match Control 2. Determines the functionality of External Match 2. - 8 - 2 - read-write - - - DO_NOTHING - Do Nothing. - 0 - - - CLEAR - Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). - 0x1 - - - SET - Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). - 0x2 - - - TOGGLE - Toggle. Toggle the corresponding External Match bit/output. - 0x3 - - - - - EMC3 - External Match Control 3. Determines the functionality of External Match 3. - 10 - 2 - read-write - - - DO_NOTHING - Do Nothing. - 0 - - - CLEAR - Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). - 0x1 - - - SET - Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). - 0x2 - - - TOGGLE - Toggle. Toggle the corresponding External Match bit/output. - 0x3 - - - - - - - CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. - 0x70 - 32 - read-write - 0 - 0xFF - - - CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. - 0 - 2 - read-write - - - TIMER - Timer Mode. Incremented every rising APB bus clock edge. - 0 - - - COUNTER_RISING_EDGE - Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. - 0x1 - - - COUNTER_FALLING_EDGE - Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. - 0x2 - - - COUNTER_DUAL_EDGE - Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. - 0x3 - - - - - CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. - 2 - 2 - read-write - - - CHANNEL_0 - Channel 0. CAPn.0 for CTIMERn - 0 - - - CHANNEL_1 - Channel 1. CAPn.1 for CTIMERn - 0x1 - - - CHANNEL_2 - Channel 2. CAPn.2 for CTIMERn - 0x2 - - - CHANNEL_3 - Channel 3. CAPn.3 for CTIMERn - 0x3 - - - - - ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. - 4 - 1 - read-write - - - SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. - 5 - 3 - read-write - - - CHANNEL_0_RISING - Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - 0 - - - CHANNEL_0_FALLING - Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - 0x1 - - - CHANNEL_1_RISING - Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - 0x2 - - - CHANNEL_1_FALLING - Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - 0x3 - - - CHANNEL_2_RISING - Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - 0x4 - - - CHANNEL_2_FALLING - Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - 0x5 - - - - - - - PWMC - PWM Control Register. This register enables PWM mode for the external match pins. - 0x74 - 32 - read-write - 0 - 0xF - - - PWMEN0 - PWM mode enable for channel0. - 0 - 1 - read-write - - - MATCH - Match. CTIMERn_MAT0 is controlled by EM0. - 0 - - - PWM - PWM. PWM mode is enabled for CTIMERn_MAT0. - 0x1 - - - - - PWMEN1 - PWM mode enable for channel1. - 1 - 1 - read-write - - - MATCH - Match. CTIMERn_MAT01 is controlled by EM1. - 0 - - - PWM - PWM. PWM mode is enabled for CTIMERn_MAT1. - 0x1 - - - - - PWMEN2 - PWM mode enable for channel2. - 2 - 1 - read-write - - - MATCH - Match. CTIMERn_MAT2 is controlled by EM2. - 0 - - - PWM - PWM. PWM mode is enabled for CTIMERn_MAT2. - 0x1 - - - - - PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. - 3 - 1 - read-write - - - MATCH - Match. CTIMERn_MAT3 is controlled by EM3. - 0 - - - PWM - PWM. PWM mode is enabled for CT132Bn_MAT3. - 0x1 - - - - - - - 4 - 0x4 - MSR[%s] - Match Shadow Register - 0x78 - 32 - read-write - 0 - 0xFFFFFFFF - - - SHADOW - Timer counter match shadow value. - 0 - 32 - read-write - - - - - - - CTIMER1 - Standard counter/timers (CTIMER0 to 4) - CTIMER - 0x40009000 - - 0 - 0x88 - registers - - - CTIMER1 - 11 - - - - CTIMER2 - Standard counter/timers (CTIMER0 to 4) - CTIMER - 0x40028000 - - 0 - 0x88 - registers - - - CTIMER2 - 36 - - - - CTIMER3 - Standard counter/timers (CTIMER0 to 4) - CTIMER - 0x40029000 - - 0 - 0x88 - registers - - - CTIMER3 - 13 - - - - CTIMER4 - Standard counter/timers (CTIMER0 to 4) - CTIMER - 0x4002A000 - - 0 - 0x88 - registers - - - CTIMER4 - 37 - - - - WWDT - Windowed Watchdog Timer (WWDT) - WWDT - 0x4000C000 - - 0 - 0x1C - registers - - - WDT_BOD - 0 - - - - MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. - 0 - 32 - read-write - 0 - 0x3F - - - WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently. - 0 - 1 - read-write - - - STOP - Stop. The watchdog timer is stopped. - 0 - - - RUN - Run. The watchdog timer is running. - 0x1 - - - - - WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. - 1 - 1 - read-write - - - INTERRUPT - Interrupt. A watchdog time-out will not cause a chip reset. - 0 - - - RESET - Reset. A watchdog time-out will cause a chip reset. - 0x1 - - - - - WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1. - 2 - 1 - read-write - - - WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. - 3 - 1 - read-write - - - WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. - 4 - 1 - read-write - - - FLEXIBLE - Flexible. The watchdog time-out value (TC) can be changed at any time. - 0 - - - THRESHOLD - Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. - 0x1 - - - - - - - TC - Watchdog timer constant register. This 24-bit register determines the time-out value. - 0x4 - 32 - read-write - 0xFF - 0xFFFFFF - - - COUNT - Watchdog time-out value. - 0 - 24 - read-write - - - - - FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. - 0x8 - 32 - write-only - 0 - 0 - - - FEED - Feed value should be 0xAA followed by 0x55. - 0 - 8 - write-only - - - - - TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. - 0xC - 32 - read-only - 0xFF - 0xFFFFFF - - - COUNT - Counter timer value. - 0 - 24 - read-only - - - - - WARNINT - Watchdog Warning Interrupt compare value. - 0x14 - 32 - read-write - 0 - 0x3FF - - - WARNINT - Watchdog warning interrupt compare value. - 0 - 10 - read-write - - - - - WINDOW - Watchdog Window compare value. - 0x18 - 32 - read-write - 0xFFFFFF - 0xFFFFFF - - - WINDOW - Watchdog window value. - 0 - 24 - read-write - - - - - - - MRT0 - Multi-Rate Timer (MRT) - MRT - 0x4000D000 - - 0 - 0xFC - registers - - - MRT0 - 9 - - - - 4 - 0x10 - CHANNEL[%s] - no description available - 0 - - INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. - 0 - 32 - read-write - 0 - 0x80FFFFFF - - - IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval. - 0 - 24 - read-write - - - LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. - 31 - 1 - read-write - - - NO_FORCE_LOAD - No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected. - 0 - - - FORCE_LOAD - Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. - 0x1 - - - - - - - TIMER - MRT Timer register. This register reads the value of the down-counter. - 0x4 - 32 - read-only - 0xFFFFFF - 0xFFFFFF - - - VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF). - 0 - 24 - read-only - - - - - CTRL - MRT Control register. This register controls the MRT modes. - 0x8 - 32 - read-write - 0 - 0x7 - - - INTEN - Enable the TIMERn interrupt. - 0 - 1 - read-write - - - DISABLED - Disabled. TIMERn interrupt is disabled. - 0 - - - ENABLED - Enabled. TIMERn interrupt is enabled. - 0x1 - - - - - MODE - Selects timer mode. - 1 - 2 - read-write - - - REPEAT_INTERRUPT_MODE - Repeat interrupt mode. - 0 - - - ONE_SHOT_INTERRUPT_MODE - One-shot interrupt mode. - 0x1 - - - ONE_SHOT_STALL_MODE - One-shot stall mode. - 0x2 - - - - - - - STAT - MRT Status register. - 0xC - 32 - read-write - 0 - 0x7 - - - INTFLAG - Monitors the interrupt flag. - 0 - 1 - read-write - - - NO_PENDING_INTERRUPT - No pending interrupt. Writing a zero is equivalent to no operation. - 0 - - - PENDING_INTERRUPT - Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. - 0x1 - - - - - RUN - Indicates the state of TIMERn. This bit is read-only. - 1 - 1 - read-write - - - IDLE_STATE - Idle state. TIMERn is stopped. - 0 - - - RUNNING - Running. TIMERn is running. - 0x1 - - - - - INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes. - 2 - 1 - read-write - - - NO - This channel is not in use. - 0 - - - YES - This channel is in use. - 0x1 - - - - - - - - MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. - 0xF0 - 32 - read-write - 0x173 - 0x800001FF - - - NOC - Identifies the number of channels in this MRT.(4 channels on this device.) - 0 - 4 - read-write - - - NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.) - 4 - 5 - read-write - - - MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. - 31 - 1 - read-write - - - HARDWARE_STATUS_MODE - Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. - 0 - - - MULTI_TASK_MODE - Multi-task mode. - 0x1 - - - - - - - IDLE_CH - Idle channel register. This register returns the number of the first idle channel. - 0xF4 - 32 - read-only - 0 - 0xF0 - - - CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details. - 4 - 4 - read-only - - - - - IRQ_FLAG - Global interrupt flag register - 0xF8 - 32 - read-write - 0 - 0xF - - - GFLAG0 - Monitors the interrupt flag of TIMER0. - 0 - 1 - read-write - - - NO_PENDING_INTERRUPT - No pending interrupt. Writing a zero is equivalent to no operation. - 0 - - - PENDING_INTERRUPT - Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. - 0x1 - - - - - GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0. - 1 - 1 - read-write - - - GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0. - 2 - 1 - read-write - - - GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0. - 3 - 1 - read-write - - - - - - - UTICK0 - Micro-tick Timer (UTICK) - UTICK - 0x4000E000 - - 0 - 0x20 - registers - - - UTICK0 - 8 - - - - CTRL - Control register. - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer. - 0 - 31 - read-write - - - REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. - 31 - 1 - read-write - - - - - STAT - Status register. - 0x4 - 32 - read-write - 0 - 0x3 - - - INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any value to this register clears this flag. - 0 - 1 - read-write - - - ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. - 1 - 1 - read-write - - - - - CFG - Capture configuration register. - 0x8 - 32 - read-write - 0 - 0xF0F - - - CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled. - 0 - 1 - read-write - - - CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled. - 1 - 1 - read-write - - - CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled. - 2 - 1 - read-write - - - CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled. - 3 - 1 - read-write - - - CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. - 8 - 1 - read-write - - - CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. - 9 - 1 - read-write - - - CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. - 10 - 1 - read-write - - - CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. - 11 - 1 - read-write - - - - - CAPCLR - Capture clear register. - 0xC - 32 - write-only - 0 - 0 - - - CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value. - 0 - 1 - write-only - - - CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value. - 1 - 1 - write-only - - - CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value. - 2 - 1 - write-only - - - CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value. - 3 - 1 - write-only - - - - - 4 - 0x4 - CAP[%s] - Capture register . - 0x10 - 32 - read-only - 0 - 0xFFFFFFFF - - - CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower than the actual value of the Micro-tick Timer at the moment of the capture event. - 0 - 31 - read-only - - - VALID - Capture Valid. When 1, a value has been captured based on a transition of the related UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. - 31 - 1 - read-only - - - - - - - ANACTRL - ANALOGCTRL - ANACTRL - 0x40013000 - - 0 - 0x108 - registers - - - - ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) - 0 - 32 - read-write - 0 - 0x1 - - - FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source. - 0 - 1 - read-write - - - EFUSE - FRO192M trimming and 'Enable' comes from eFUSE. - 0 - - - FRO192MCTRL - FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers. - 0x1 - - - - - - - ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers - 0x4 - 32 - read-only - 0x50000000 - 0xF0003FFF - - - FLASH_PWRDWN - Flash Power Down status. - 12 - 1 - read-only - - - PWRUP - Flash is not in power down mode. - 0 - - - PWRDWN - Flash is in power down mode. - 0x1 - - - - - FLASH_INIT_ERROR - Flash initialization error status. - 13 - 1 - read-only - - - NOERROR - No error. - 0 - - - ERROR - At least one error occured during flash initialization.. - 0x1 - - - - - - - FREQ_ME_CTRL - Frequency Measure function control register - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPVAL_SCALE - Frequency measure result /Frequency measur scale - 0 - 31 - read-write - - - PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 30:0). - 31 - 1 - read-write - - - - - FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register - 0x10 - 32 - read-write - 0x80D01A - 0xF3FFFFBF - - - ENA_12MHZCLK - 12 MHz clock control. - 14 - 1 - read-write - - - DISABLE - 12 MHz clock is disabled. - 0 - - - ENABLE - 12 MHz clock is enabled. - 0x1 - - - - - ENA_48MHZCLK - 48 MHz clock control. - 15 - 1 - read-write - - - ENABLE - 48 MHz clock is enabled. - 0x1 - - - - - DAC_TRIM - Frequency trim. - 16 - 8 - read-write - - - USBCLKADJ - If this bit is set and the USB peripheral is enabled into full speed device mode, the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF packets. - 24 - 1 - read-write - - - USBMODCHG - If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0. - 25 - 1 - read-only - - - ENA_96MHZCLK - 96 MHz clock control. - 30 - 1 - read-write - - - DISABLE - 96 MHz clock is disabled. - 0 - - - ENABLE - 96 MHz clock is enabled. - 0x1 - - - - - WRTRIM - This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields. - 31 - 1 - write-only - - - - - FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register - 0x14 - 32 - read-write - 0x3 - 0x3 - - - CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. - 0 - 1 - read-only - - - NOCLKOUT - No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). - 0 - - - CLKOUT - Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). - 0x1 - - - - - ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses the threshold voltage of a SLVT transistor, this output signal will go high. It is also possible to observe the clk_valid signal. - 1 - 1 - read-only - - - - - ADC_CTRL - General Purpose ADC VBAT Divider branch control - 0x18 - 32 - read-write - 0 - 0x1 - - - VBATDIVENABLE - Switch On/Off VBAT divider branch. - 0 - 1 - read-write - - - DISABLE - VBAT divider branch is disabled. - 0 - - - ENABLE - VBAT divider branch is enabled. - 0x1 - - - - - - - XO32M_CTRL - High speed Crystal Oscillator Control register - 0x20 - 32 - read-write - 0x21428A - 0x1FFFFFFE - - - SLAVE - Xo in slave mode. - 4 - 1 - read-write - - - OSC_CAP_IN - Tune capa banks of High speed Crystal Oscillator input pin - 8 - 7 - read-write - - - OSC_CAP_OUT - Tune capa banks of High speed Crystal Oscillator output pin - 15 - 7 - read-write - - - ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. - 22 - 1 - read-write - - - DISABLE - XO AC buffer bypass is disabled. - 0 - - - ENABLE - XO AC buffer bypass is enabled. - 0x1 - - - - - ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL. - 23 - 1 - read-write - - - DISABLE - High speed Crystal oscillator output to USB HS PLL is disabled. - 0 - - - ENABLE - High speed Crystal oscillator output to USB HS PLL is enabled. - 0x1 - - - - - ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system. - 24 - 1 - read-write - - - DISABLE - High speed Crystal oscillator output to CPU system is disabled. - 0 - - - ENABLE - High speed Crystal oscillator output to CPU system is enabled. - 0x1 - - - - - - - XO32M_STATUS - High speed Crystal Oscillator Status register - 0x24 - 32 - read-only - 0 - 0x1 - - - XO_READY - Indicates XO out frequency statibilty. - 0 - 1 - read-only - - - NOT_STABLE - XO output frequency is not yet stable. - 0 - - - STABLE - XO output frequency is stable. - 0x1 - - - - - - - BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register - 0x30 - 32 - read-write - 0 - 0x3F - - - BODVBAT_INT_ENABLE - BOD VBAT interrupt control. - 0 - 1 - read-write - - - DISABLE - BOD VBAT interrupt is disabled. - 0 - - - ENABLE - BOD VBAT interrupt is enabled. - 0x1 - - - - - BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit. - 1 - 1 - read-write - - - BODCORE_INT_ENABLE - BOD CORE interrupt control. - 2 - 1 - read-write - - - DISABLE - BOD CORE interrupt is disabled. - 0 - - - ENABLE - BOD CORE interrupt is enabled. - 0x1 - - - - - BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. - 3 - 1 - read-write - - - DCDC_INT_ENABLE - DCDC interrupt control. - 4 - 1 - read-write - - - DISABLE - DCDC interrupt is disabled. - 0 - - - ENABLE - DCDC interrupt is enabled. - 0x1 - - - - - DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. - 5 - 1 - read-write - - - - - BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register - 0x34 - 32 - read-only - 0x104 - 0x1FF - - - BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. - 0 - 1 - read-only - - - NOT_PENDING - No interrupt pending.. - 0 - - - PENDING - Interrupt pending.. - 0x1 - - - - - BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. - 1 - 1 - read-only - - - NOT_PENDING - No interrupt pending.. - 0 - - - PENDING - Interrupt pending.. - 0x1 - - - - - BODVBAT_VAL - Current value of BOD VBAT power status output. - 2 - 1 - read-only - - - NOT_OK - VBAT voltage level is below the threshold. - 0 - - - OK - VBAT voltage level is above the threshold. - 0x1 - - - - - BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. - 3 - 1 - read-only - - - NOT_PENDING - No interrupt pending.. - 0 - - - PENDING - Interrupt pending.. - 0x1 - - - - - BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. - 4 - 1 - read-only - - - NOT_PENDING - No interrupt pending.. - 0 - - - PENDING - Interrupt pending.. - 0x1 - - - - - BODCORE_VAL - Current value of BOD CORE power status output. - 5 - 1 - read-only - - - NOT_OK - CORE voltage level is below the threshold. - 0 - - - OK - CORE voltage level is above the threshold. - 0x1 - - - - - DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. - 6 - 1 - read-only - - - NOT_PENDING - No interrupt pending.. - 0 - - - PENDING - Interrupt pending.. - 0x1 - - - - - DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. - 7 - 1 - read-only - - - NOT_PENDING - No interrupt pending.. - 0 - - - PENDING - Interrupt pending.. - 0x1 - - - - - DCDC_VAL - Current value of DCDC power status output. - 8 - 1 - read-only - - - NOT_OK - DCDC output Voltage is below the targeted regulation level. - 0 - - - OK - DCDC output Voltage is above the targeted regulation level. - 0x1 - - - - - - - RINGO0_CTRL - First Ring Oscillator module control register. - 0x40 - 32 - read-write - 0x40 - 0x803F1FFF - - - SL - Select short or long ringo (for all ringos types). - 0 - 1 - read-write - - - SHORT - Select short ringo (few elements). - 0 - - - LONG - Select long ringo (many elements). - 0x1 - - - - - FS - Ringo frequency output divider. - 1 - 1 - read-write - - - FAST - High frequency output (frequency lower than 100 MHz). - 0 - - - SLOW - Low frequency output (frequency lower than 10 MHz). - 0x1 - - - - - SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control. - 2 - 2 - read-write - - - NORMAL - Normal mode. - 0 - - - P_MONITOR - P-Monitor mode. Measure with weak P transistor. - 0x1 - - - N_MONITOR - P-Monitor mode. Measure with weak N transistor. - 0x2 - - - FORBIDDEN - Don't use. - 0x3 - - - - - PD - Ringo module Power control. - 4 - 1 - read-write - - - POWERED_ON - The Ringo module is enabled. - 0 - - - POWERED_DOWN - The Ringo module is disabled. - 0x1 - - - - - E_ND0 - First NAND2-based ringo control. - 5 - 1 - read-write - - - DISABLE - First NAND2-based ringo is disabled. - 0 - - - ENABLE - First NAND2-based ringo is enabled. - 0x1 - - - - - E_ND1 - Second NAND2-based ringo control. - 6 - 1 - read-write - - - DISABLE - Second NAND2-based ringo is disabled. - 0 - - - ENABLE - Second NAND2-based ringo is enabled. - 0x1 - - - - - E_NR0 - First NOR2-based ringo control. - 7 - 1 - read-write - - - DISABLE - First NOR2-based ringo is disabled. - 0 - - - ENABLE - First NOR2-based ringo is enabled. - 0x1 - - - - - E_NR1 - Second NOR2-based ringo control. - 8 - 1 - read-write - - - DISABLE - Second NORD2-based ringo is disabled. - 0 - - - ENABLE - Second NORD2-based ringo is enabled. - 0x1 - - - - - E_IV0 - First Inverter-based ringo control. - 9 - 1 - read-write - - - DISABLE - First INV-based ringo is disabled. - 0 - - - ENABLE - First INV-based ringo is enabled. - 0x1 - - - - - E_IV1 - Second Inverter-based ringo control. - 10 - 1 - read-write - - - DISABLE - Second INV-based ringo is disabled. - 0 - - - ENABLE - Second INV-based ringo is enabled. - 0x1 - - - - - E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control. - 11 - 1 - read-write - - - DISABLE - First PN-based ringo is disabled. - 0 - - - ENABLE - First PN-based ringo is enabled. - 0x1 - - - - - E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control. - 12 - 1 - read-write - - - DISABLE - Second PN-based ringo is disabled. - 0 - - - ENABLE - Second PN-based ringo is enabled. - 0x1 - - - - - DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) - 16 - 4 - read-write - - - DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. - 31 - 1 - read-only - - - - - RINGO1_CTRL - Second Ring Oscillator module control register. - 0x44 - 32 - read-write - 0x40 - 0x803F01FF - - - S - Select short or long ringo (for all ringos types). - 0 - 1 - read-write - - - SHORT - Select short ringo (few elements). - 0 - - - LONG - Select long ringo (many elements). - 0x1 - - - - - FS - Ringo frequency output divider. - 1 - 1 - read-write - - - FAST - High frequency output (frequency lower than 100 MHz). - 0 - - - SLOW - Low frequency output (frequency lower than 10 MHz). - 0x1 - - - - - PD - Ringo module Power control. - 2 - 1 - read-write - - - POWERED_ON - The Ringo module is enabled. - 0 - - - POWERED_DOWN - The Ringo module is disabled. - 0x1 - - - - - E_R24 - . - 3 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_R35 - . - 4 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M2 - Metal 2 (M2) monitor control. - 5 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M3 - Metal 3 (M3) monitor control. - 6 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M4 - Metal 4 (M4) monitor control. - 7 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M5 - Metal 5 (M5) monitor control. - 8 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) - 16 - 4 - read-write - - - DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. - 31 - 1 - read-only - - - - - RINGO2_CTRL - Third Ring Oscillator module control register. - 0x48 - 32 - read-write - 0x40 - 0x803F01FF - - - S - Select short or long ringo (for all ringos types). - 0 - 1 - read-write - - - SHORT - Select short ringo (few elements). - 0 - - - LONG - Select long ringo (many elements). - 0x1 - - - - - FS - Ringo frequency output divider. - 1 - 1 - read-write - - - FAST - High frequency output (frequency lower than 100 MHz). - 0 - - - SLOW - Low frequency output (frequency lower than 10 MHz). - 0x1 - - - - - PD - Ringo module Power control. - 2 - 1 - read-write - - - POWERED_ON - The Ringo module is enabled. - 0 - - - POWERED_DOWN - The Ringo module is disabled. - 0x1 - - - - - E_R24 - . - 3 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_R35 - . - 4 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M2 - Metal 2 (M2) monitor control. - 5 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M3 - Metal 3 (M3) monitor control. - 6 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M4 - Metal 4 (M4) monitor control. - 7 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M5 - Metal 5 (M5) monitor control. - 8 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) - 16 - 4 - read-write - - - DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. - 31 - 1 - read-only - - - - - LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register - 0xB0 - 32 - read-write - 0x3A0 - 0x3FE - - - BYPASS - Activate LDO bypass. - 1 - 1 - read-write - - - DISABLE - Disable bypass mode (for normal operations). - 0 - - - ENABLE - Activate LDO bypass. - 0x1 - - - - - HIGHZ - . - 2 - 1 - read-write - - - NORMALMPEDANCE - Output in High normal state. - 0 - - - HIGHIMPEDANCE - Output in High Impedance state. - 0x1 - - - - - VOUT - Sets the LDO output level. - 3 - 3 - read-write - - - V_0P750 - 0.750 V. - 0 - - - V_0P775 - 0.775 V. - 0x1 - - - V_0P800 - 0.800 V. - 0x2 - - - V_0P825 - 0.825 V. - 0x3 - - - V_0P850 - 0.850 V. - 0x4 - - - V_0P875 - 0.875 V. - 0x5 - - - V_0P900 - 0.900 V. - 0x6 - - - V_0P925 - 0.925 V. - 0x7 - - - - - IBIAS - Adjust the biasing current. - 6 - 2 - read-write - - - STABMODE - Stability configuration. - 8 - 2 - read-write - - - - - AUX_BIAS - AUX_BIAS - 0xB4 - 32 - read-write - 0x703A0 - 0x3FFFFE - - - VREF1VENABLE - Control output of 1V reference voltage. - 1 - 1 - read-write - - - DISABLE - Output of 1V reference voltage buffer is bypassed. - 0 - - - ENABLE - Output of 1V reference voltage is enabled. - 0x1 - - - - - ITRIM - current trimming control word. - 2 - 5 - read-write - - - PTATITRIM - current trimming control word for ptat current. - 7 - 5 - read-write - - - VREF1VTRIM - voltage trimming control word. - 12 - 5 - read-write - - - VREF1VCURVETRIM - Control bit to configure trimming state of mirror. - 17 - 3 - read-write - - - ITRIMCTRL0 - Control bit to configure trimming state of mirror. - 20 - 1 - read-write - - - ITRIMCTRL1 - Control bit to configure trimming state of mirror. - 21 - 1 - read-write - - - - - USBHS_PHY_CTRL - USB High Speed Phy Control - 0x100 - 32 - read-write - 0x8 - 0xF - - - usb_vbusvalid_ext - Override value for Vbus if using external detectors. - 0 - 1 - read-write - - - usb_id_ext - Override value for ID if using external detectors. - 1 - 1 - read-write - - - - - USBHS_PHY_TRIM - USB High Speed Phy Trim values - 0x104 - 32 - read-write - 0 - 0xFFFFFF - - - trim_usb_reg_env_tail_adj_vd - Adjusts time constant of HS RX squelch (envelope) comparator. - 0 - 2 - read-write - - - trim_usbphy_tx_d_cal - . - 2 - 4 - read-write - - - trim_usbphy_tx_cal45dp - . - 6 - 5 - read-write - - - trim_usbphy_tx_cal45dm - . - 11 - 5 - read-write - - - trim_usb2_refbias_tst - . - 16 - 2 - read-write - - - trim_usb2_refbias_vbgadj - . - 18 - 3 - read-write - - - trim_pll_ctrl0_div_sel - . - 21 - 3 - read-write - - - - - - - PMC - PMC - PMC - 0x40020000 - - 0 - 0xD8 - registers - - - ACMP - 24 - - - - STATUS - Power Management Controller FSM (Finite State Machines) status - 0x4 - 32 - read-only - 0 - 0xF00FFFFF - - - BOOTMODE - Latest IC Boot cause:. - 18 - 2 - read-only - - - POWERUP - Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset). - 0 - - - DEEPSLEEP - Latest IC boot was from DEEP SLEEP low power mode. - 0x1 - - - POWERDOWN - Latest IC boot was from POWER DOWN low power mode. - 0x2 - - - DEEPPOWERDOWN - Latest IC boot was from DEEP POWER DOWN low power mode. - 0x3 - - - - - - - RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x8 - 32 - read-write - 0 - 0xF - - - DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). - 0 - 1 - read-write - - - DISABLE - Reset event from DEEP POWER DOWN mode is disable. - 0 - - - ENABLE - Reset event from DEEP POWER DOWN mode is enable. - 0x1 - - - - - BODVBATRESETENABLE - BOD VBAT reset enable. - 1 - 1 - read-write - - - DISABLE - BOD VBAT reset is disable. - 0 - - - ENABLE - BOD VBAT reset is enable. - 0x1 - - - - - BODCORERESETENABLE - BOD CORE reset enable. - 2 - 1 - read-write - - - DISABLE - BOD CORE reset is disable. - 0 - - - ENABLE - BOD CORE reset is enable. - 0x1 - - - - - SWRRESETENABLE - Software reset enable. - 3 - 1 - read-write - - - DISABLE - Software reset is disable. - 0 - - - ENABLE - Software reset is enable. - 0x1 - - - - - - - DCDC0 - DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x10 - 32 - read-write - 0x10C4E68 - 0x7FFFFFF - - - RC - Constant On-Time calibration. - 0 - 6 - read-write - - - ICOMP - Select the type of ZCD comparator. - 6 - 2 - read-write - - - ISEL - Alter Internal biasing currents. - 8 - 2 - read-write - - - ICENABLE - Selection of auto scaling of COT period with variations in VDD. - 10 - 1 - read-write - - - TMOS - One-shot generator reference current trimming signal. - 11 - 5 - read-write - - - DISABLEISENSE - Disable Current sensing. - 16 - 1 - read-write - - - VOUT - Set output regulation voltage. - 17 - 4 - read-write - - - V_DCDC_0P950 - 0.95 V. - 0 - - - V_DCDC_0P975 - 0.975 V. - 0x1 - - - V_DCDC_1P000 - 1 V. - 0x2 - - - V_DCDC_1P025 - 1.025 V. - 0x3 - - - V_DCDC_1P050 - 1.05 V. - 0x4 - - - V_DCDC_1P075 - 1.075 V. - 0x5 - - - V_DCDC_1P100 - 1.1 V. - 0x6 - - - V_DCDC_1P125 - 1.125 V. - 0x7 - - - V_DCDC_1P150 - 1.15 V. - 0x8 - - - V_DCDC_1P175 - 1.175 V. - 0x9 - - - V_DCDC_1P200 - 1.2 V. - 0xA - - - - - SLICINGENABLE - Enable staggered switching of power switches. - 21 - 1 - read-write - - - INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. - 22 - 1 - read-write - - - VOUT_PWD - Set output regulation voltage during Deep Sleep. - 23 - 4 - read-write - - - - - DCDC1 - DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x14 - 32 - read-write - 0x1803A98 - 0xFFFFFFFF - - - RTRIMOFFET - Adjust the offset voltage of BJT based comparator. - 0 - 4 - read-write - - - RSENSETRIM - Adjust Max inductor peak current limiting. - 4 - 4 - read-write - - - DTESTENABLE - Enable Digital test signals. - 8 - 1 - read-write - - - SETCURVE - Bandgap calibration parameter. - 9 - 2 - read-write - - - SETDC - Bandgap calibration parameter. - 11 - 4 - read-write - - - DTESTSEL - Select the output signal for test. - 15 - 3 - read-write - - - ISCALEENABLE - Modify COT behavior. - 18 - 1 - read-write - - - FORCEBYPASS - Force bypass mode. - 19 - 1 - read-write - - - TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. - 20 - 4 - read-write - - - FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. - 24 - 1 - read-write - - - LCENABLE - Change the range of the peak detector of current inside the inductor. - 25 - 1 - read-write - - - TOFF - Constant Off-Time calibration input. - 26 - 5 - read-write - - - TOFFENABLE - Enable Constant Off-Time feature. - 31 - 1 - read-write - - - - - LDOPMU - Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x1C - 32 - read-write - 0x10EF718 - 0x31FFFFF - - - VADJ - Sets the Always-On domain LDO output level. - 0 - 5 - read-write - - - V_1P220 - 1.22 V. - 0 - - - V_0P700 - 0.7 V. - 0x1 - - - V_0P725 - 0.725 V. - 0x2 - - - V_0P750 - 0.75 V. - 0x3 - - - V_0P775 - 0.775 V. - 0x4 - - - V_0P800 - 0.8 V. - 0x5 - - - V_0P825 - 0.825 V. - 0x6 - - - V_0P850 - 0.85 V. - 0x7 - - - V_0P875 - 0.875 V. - 0x8 - - - V_0P900 - 0.9 V. - 0x9 - - - V_0P960 - 0.96 V. - 0xA - - - V_0P970 - 0.97 V. - 0xB - - - V_0P980 - 0.98 V. - 0xC - - - V_0P990 - 0.99 V. - 0xD - - - V_1P000 - 1 V. - 0xE - - - V_1P010 - 1.01 V. - 0xF - - - V_1P020 - 1.02 V. - 0x10 - - - V_1P030 - 1.03 V. - 0x11 - - - V_1P040 - 1.04 V. - 0x12 - - - V_1P050 - 1.05 V. - 0x13 - - - V_1P060 - 1.06 V. - 0x14 - - - V_1P070 - 1.07 V. - 0x15 - - - V_1P080 - 1.08 V. - 0x16 - - - V_1P090 - 1.09 V. - 0x17 - - - V_1P100 - 1.1 V. - 0x18 - - - V_1P110 - 1.11 V. - 0x19 - - - V_1P120 - 1.12 V. - 0x1A - - - V_1P130 - 1.13 V. - 0x1B - - - V_1P140 - 1.14 V. - 0x1C - - - V_1P150 - 1.15 V. - 0x1D - - - V_1P160 - 1.16 V. - 0x1E - - - V_1P220_1 - 1.22 V. - 0x1F - - - - - VADJ_PWD - Sets the Always-On domain LDO output level in all power down modes. - 5 - 5 - read-write - - - VADJ_BOOST - Sets the Always-On domain LDO Boost output level. - 10 - 5 - read-write - - - VADJ_BOOST_PWD - Sets the Always-On domain LDO Boost output level in all power down modes. - 15 - 5 - read-write - - - BOOST_ENA - Control the LDO AO boost mode in ACTIVE mode. - 24 - 1 - read-write - - - DISABLE - LDO AO Boost Mode is disable. - 0 - - - ENABLE - LDO AO Boost Mode is enable. - 0x1 - - - - - BOOST_ENA_PWD - Control the LDO AO boost mode in the different low power modes (DEEP SLEEP, POWERDOWN, and DEEP POWER DOWN). - 25 - 1 - read-write - - - DISABLE - LDO AO Boost Mode is disable. - 0 - - - ENABLE - LDO AO Boost Mode is enable. - 0x1 - - - - - - - BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] - 0x30 - 32 - read-write - 0x47 - 0x7F - - - TRIGLVL - BoD trigger level. - 0 - 5 - read-write - - - V_1P00 - 1.00 V. - 0 - - - V_1P10 - 1.10 V. - 0x1 - - - V_1P20 - 1.20 V. - 0x2 - - - V_1P30 - 1.30 V. - 0x3 - - - V_1P40 - 1.40 V. - 0x4 - - - V_1P50 - 1.50 V. - 0x5 - - - V_1P60 - 1.60 V. - 0x6 - - - V_1P65 - 1.65 V. - 0x7 - - - V_1P70 - 1.70 V. - 0x8 - - - V_1P75 - 1.75 V. - 0x9 - - - V_1P80 - 1.80 V. - 0xA - - - V_1P90 - 1.90 V. - 0xB - - - V_2P00 - 2.00 V. - 0xC - - - V_2P10 - 2.10 V. - 0xD - - - V_2P20 - 2.20 V. - 0xE - - - V_2P30 - 2.30 V. - 0xF - - - V_2P40 - 2.40 V. - 0x10 - - - V_2P50 - 2.50 V. - 0x11 - - - V_2P60 - 2.60 V. - 0x12 - - - V_2P70 - 2.70 V. - 0x13 - - - V_2P80 - 2.806 V. - 0x14 - - - V_2P90 - 2.90 V. - 0x15 - - - V_3P00 - 3.00 V. - 0x16 - - - V_3P10 - 3.10 V. - 0x17 - - - V_3P20 - 3.20 V. - 0x18 - - - V_3P30_2 - 3.30 V. - 0x19 - - - V_3P30_3 - 3.30 V. - 0x1A - - - V_3P30_4 - 3.30 V. - 0x1B - - - V_3P30_5 - 3.30 V. - 0x1C - - - V_3P30_6 - 3.30 V. - 0x1D - - - V_3P30_7 - 3.30 V. - 0x1E - - - V_3P30_8 - 3.30 V. - 0x1F - - - - - HYST - BoD Hysteresis control. - 5 - 2 - read-write - - - HYST_25MV - 25 mV. - 0 - - - HYST_50MV - 50 mV. - 0x1 - - - HYST_75MV - 75 mV. - 0x2 - - - HYST_100MV - 100 mV. - 0x3 - - - - - - - REFFASTWKUP - Analog References fast wake-up Control register [Reset by: PoR] - 0x40 - 32 - read-write - 0x1 - 0x3 - - - LPWKUP - Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP POWER DOWN): . - 0 - 1 - read-write - - - DISABLE - Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode. - 0 - - - ENABLE - Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode. - 0x1 - - - - - HWWKUP - Analog References fast wake-up in case of Hardware Pin reset: . - 1 - 1 - read-write - - - DISABLE - Analog References fast wake-up feature is disabled in case of Hardware Pin reset. - 0 - - - ENABLE - Analog References fast wake-up feature is enabled in case of Hardware Pin reset. - 0x1 - - - - - - - XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] - 0x4C - 32 - read-write - 0x204052 - 0x3FFFFFE - - - IREF - reference output current selection inputs. - 1 - 2 - read-write - - - TEST - Oscillator Test Mode. - 3 - 1 - read-write - - - IBIAS - bias current selection inputs. - 4 - 2 - read-write - - - AMPL - oscillator amplitude selection inputs. - 6 - 2 - read-write - - - CAPBANKIN - Capa bank setting input. - 8 - 7 - read-write - - - CAPBANKOUT - Capa bank setting output. - 15 - 7 - read-write - - - CAPTESTSTARTSRCSEL - Source selection for xo32k_captest_start_ao_set. - 22 - 1 - read-write - - - CAPSTART - Sourced from CAPTESTSTART. - 0 - - - CALIB - Sourced from calibration. - 0x1 - - - - - CAPTESTSTART - Start test. - 23 - 1 - read-write - - - CAPTESTENABLE - Enable signal for cap test. - 24 - 1 - read-write - - - CAPTESTOSCINSEL - Select the input for test. - 25 - 1 - read-write - - - OSCOUT - Oscillator output pin (osc_out). - 0 - - - OSCIN - Oscillator input pin (osc_in). - 0x1 - - - - - - - COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x50 - 32 - read-write - 0xA - 0xFF7FFE - - - HYST - Hysteris when hyst = '1'. - 1 - 1 - read-write - - - DISABLE - Hysteresis is disable. - 0 - - - ENABLE - Hysteresis is enable. - 0x1 - - - - - VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). - 2 - 1 - read-write - - - INTERNALREF - Select internal VREF. - 0 - - - VDDA - Select VDDA. - 0x1 - - - - - LOWPOWER - Low power mode. - 3 - 1 - read-write - - - HIGHSPEED - High speed mode. - 0 - - - LOWSPEED - Low power mode (Low speed). - 0x1 - - - - - PMUX - Control word for P multiplexer:. - 4 - 3 - read-write - - - VREF - VREF (See fiedl VREFINPUT). - 0 - - - CMP0_A - Pin P0_0. - 0x1 - - - CMP0_B - Pin P0_9. - 0x2 - - - CMP0_C - Pin P0_18. - 0x3 - - - CMP0_D - Pin P1_14. - 0x4 - - - CMP0_E - Pin P2_23. - 0x5 - - - - - NMUX - Control word for N multiplexer:. - 7 - 3 - read-write - - - VREF - VREF (See field VREFINPUT). - 0 - - - CMP0_A - Pin P0_0. - 0x1 - - - CMP0_B - Pin P0_9. - 0x2 - - - CMP0_C - Pin P0_18. - 0x3 - - - CMP0_D - Pin P1_14. - 0x4 - - - CMP0_E - Pin P2_23. - 0x5 - - - - - VREF - Control reference voltage step, per steps of (VREFINPUT/31). - 10 - 5 - read-write - - - FILTERCGF_SAMPLEMODE - Control the filtering of the Analog Comparator output. - 16 - 2 - read-write - - - BYPASS - Bypass mode. - 0 - - - FILTER1CLK - Filter 1 clock period. - 0x1 - - - FILTER2CLK - Filter 2 clock period. - 0x2 - - - FILTER3CLK - Filter 3 clock period. - 0x3 - - - - - FILTERCGF_CLKDIV - Filter Clock divider. - 18 - 3 - read-write - - - FILTER_1CLK_PERIOD - Filter clock period duration equals 1 Analog Comparator clock period. - 0 - - - FILTER_2CLK_PERIOD - Filter clock period duration equals 2 Analog Comparator clock period. - 0x1 - - - FILTER_4CLK_PERIOD - Filter clock period duration equals 4 Analog Comparator clock period. - 0x2 - - - FILTER_8CLK_PERIOD - Filter clock period duration equals 8 Analog Comparator clock period. - 0x3 - - - FILTER_16CLK_PERIOD - Filter clock period duration equals 16 Analog Comparator clock period. - 0x4 - - - FILTER_32CLK_PERIOD - Filter clock period duration equals 32 Analog Comparator clock period. - 0x5 - - - FILTER_64CLK_PERIOD - Filter clock period duration equals 64 Analog Comparator clock period. - 0x6 - - - FILTER_128CLK_PERIOD - Filter clock period duration equals 128 Analog Comparator clock period. - 0x7 - - - - - - - WAKEUPIOCTRL - Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] - 0x64 - 32 - read-write - 0 - 0xFF - - - RISINGEDGEWAKEUP0 - Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:. - 0 - 1 - read-write - - - DISABLE - Rising edge detection is disable. - 0 - - - ENABLE - Rising edge detection is enable. - 0x1 - - - - - FALLINGEDGEWAKEUP0 - Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:. - 1 - 1 - read-write - - - DISABLE - Falling edge detection is disable. - 0 - - - ENABLE - Falling edge detection is enable. - 0x1 - - - - - RISINGEDGEWAKEUP1 - Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:. - 2 - 1 - read-write - - - DISABLE - Rising edge detection is disable. - 0 - - - ENABLE - Rising edge detection is enable. - 0x1 - - - - - FALLINGEDGEWAKEUP1 - Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:. - 3 - 1 - read-write - - - DISABLE - Falling edge detection is disable. - 0 - - - ENABLE - Falling edge detection is enable. - 0x1 - - - - - RISINGEDGEWAKEUP2 - Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:. - 4 - 1 - read-write - - - DISABLE - Rising edge detection is disable. - 0 - - - ENABLE - Rising edge detection is enable. - 0x1 - - - - - FALLINGEDGEWAKEUP2 - Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:. - 5 - 1 - read-write - - - DISABLE - Falling edge detection is disable. - 0 - - - ENABLE - Falling edge detection is enable. - 0x1 - - - - - RISINGEDGEWAKEUP3 - Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes:. - 6 - 1 - read-write - - - DISABLE - Rising edge detection is disable. - 0 - - - ENABLE - Rising edge detection is enable. - 0x1 - - - - - FALLINGEDGEWAKEUP3 - Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes:. - 7 - 1 - read-write - - - DISABLE - Falling edge detection is disable. - 0 - - - ENABLE - Falling edge detection is enable. - 0x1 - - - - - MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode - 8 - 1 - read-write - - - MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode - 9 - 1 - read-write - - - MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode - 10 - 1 - read-write - - - MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode - 11 - 1 - read-write - - - - - WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode - 0x68 - 32 - read-write - 0 - 0xF - - - WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. - 0 - 1 - read-only - - - NOEVENT - Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. - 0 - - - EVENT - Last wake up from Deep Power down mode was triggred by wake up I/O 0. - 0x1 - - - - - WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. - 1 - 1 - read-write - - - NOEVENT - Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. - 0 - - - EVENT - Last wake up from Deep Power down mode was triggred by wake up I/O 1. - 0x1 - - - - - WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. - 2 - 1 - read-write - - - NOEVENT - Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. - 0 - - - EVENT - Last wake up from Deep Power down mode was triggred by wake up I/O 2. - 0x1 - - - - - WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. - 3 - 1 - read-write - - - NOEVENT - Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. - 0 - - - EVENT - Last wake up from Deep Power down mode was triggred by wake up I/O 3. - 0x1 - - - - - - - STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] - 0x74 - 32 - read-write - 0x6 - 0x7 - - - XTAL32KOK - XTAL oscillator 32 K OK signal. - 0 - 1 - read-only - - - XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. - 2 - 1 - read-write - - - NOFAIL - No oscillation failure has been detetced since the last time this bit has been cleared. - 0 - - - FAILURE - At least one oscillation failure has been detetced since the last time this bit has been cleared. - 0x1 - - - - - - - AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] - 0x84 - 32 - read-write - 0 - 0xFFFFFFFF - - - POR - The last chip reset was caused by a Power On Reset. - 4 - 1 - read-write - - - PADRESET - The last chip reset was caused by a Pin Reset. - 5 - 1 - read-write - - - BODRESET - The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. - 6 - 1 - read-write - - - SYSTEMRESET - The last chip reset was caused by a System Reset requested by the ARM CPU. - 7 - 1 - read-write - - - WDTRESET - The last chip reset was caused by the Watchdog Timer. - 8 - 1 - read-write - - - SWRRESET - The last chip reset was caused by a Software event. - 9 - 1 - read-write - - - DPDRESET_WAKEUPIO - The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode. - 10 - 1 - read-write - - - DPDRESET_RTC - The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode. - 11 - 1 - read-write - - - DPDRESET_OSTIMER - The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode. - 12 - 1 - read-write - - - BOOTERRORCOUNTER - ROM Boot Fatal Error Counter. - 16 - 4 - read-write - - - - - MISCCTRL - Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x90 - 32 - read-write - 0 - 0xFFFF - - - LDODEEPSLEEPREF - Select LDO Deep Sleep reference source. - 0 - 1 - read-write - - - FLASHBUFFER - LDO DEEP Sleep uses Flash buffer biasing as reference. - 0 - - - BGP0P8V - LDO DEEP Sleep uses Band Gap 0.8V as reference. - 0x1 - - - - - LDOMEMHIGHZMODE - Control the activation of LDO MEM High Z mode. - 1 - 1 - read-write - - - DISABLE - LDO MEM High Z mode is disabled. - 0 - - - ENABLE - LDO MEM High Z mode is enabled. - 0x1 - - - - - LOWPWR_FLASH_BUF - no description available - 2 - 1 - read-write - - - MISCCTRL_3_8 - Reserved. - 3 - 5 - read-write - - - MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode - 8 - 1 - read-write - - - MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode - 9 - 1 - read-write - - - MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode - 10 - 1 - read-write - - - MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode - 11 - 1 - read-write - - - DISABLE_BLEED - Controls LDO MEM bleed current. This field is expected to be controlled by the Low Power Software only in DEEP SLEEP low power mode. - 12 - 1 - read-write - - - BLEED_ENABLE - LDO_MEM bleed current is enabled. - 0 - - - BLEED_DISABLE - LDO_MEM bleed current is disabled. Should be set before entering in Deep Sleep low power mode and cleared after wake up from Deep SLeep low power mode. - 0x1 - - - - - MISCCTRL_13_14 - Reserved. - 13 - 2 - read-write - - - WAKUPIO_RST - WAKEUP IO event detector reset control. - 15 - 1 - read-write - - - RELEASED - Wakeup IO is not reset. - 0 - - - ASSERTED - Wakeup IO is reset. - 0x1 - - - - - - - RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] - 0x98 - 32 - read-write - 0x3FF0008 - 0xC7FF800F - - - SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . - 0 - 1 - read-write - - - FRO32K - FRO 32 KHz. - 0 - - - XTAL32K - XTAL 32KHz. - 0x1 - - - - - CLK1KHZDIV - Actual division ratio is : 28 + CLK1KHZDIV. - 1 - 3 - read-write - - - CLK1KHZDIVUPDATEREQ - RTC 1KHz clock Divider status flag. - 15 - 1 - read-write - - - CLK1HZDIV - Actual division ratio is : 31744 + CLK1HZDIV. - 16 - 11 - read-write - - - CLK1HZDIVHALT - Halts the divider counter. - 30 - 1 - read-write - - - CLK1HZDIVUPDATEREQ - RTC 1Hz Divider status flag. - 31 - 1 - read-write - - - - - OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] - 0x9C - 32 - read-write - 0x8 - 0xF - - - SOFTRESET - Active high reset. - 0 - 1 - read-write - - - CLOCKENABLE - Enable OSTIMER 32 KHz clock. - 1 - 1 - read-write - - - DPDWAKEUPENABLE - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode). - 2 - 1 - read-write - - - OSC32KPD - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K. - 3 - 1 - read-write - - - - - PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0xB8 - 32 - read-write - 0xDEFFC4 - 0xFFFFEF - - - PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD). - 3 - 1 - read-write - - - POWEREDON - BOD VBAT is powered. - 0 - - - POWEREDOFF - BOD VBAT is powered down. - 0x1 - - - - - PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. - 6 - 1 - read-write - - - POWEREDON - FRO32KHz is powered. - 0 - - - POWEREDOFF - FRO32KHz is powered down. - 0x1 - - - - - PDEN_XTAL32K - Controls power to crystal 32 KHz. - 7 - 1 - read-write - - - POWEREDON - Crystal 32KHz is powered. - 0 - - - POWEREDOFF - Crystal 32KHz is powered down. - 0x1 - - - - - PDEN_XTAL32M - Controls power to high speed crystal. - 8 - 1 - read-write - - - POWEREDON - High speed crystal is powered. - 0 - - - POWEREDOFF - High speed crystal is powered down. - 0x1 - - - - - PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). - 9 - 1 - read-write - - - POWEREDON - PLL0 is powered. - 0 - - - POWEREDOFF - PLL0 is powered down. - 0x1 - - - - - PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1). - 10 - 1 - read-write - - - POWEREDON - PLL1 is powered. - 0 - - - POWEREDOFF - PLL1 is powered down. - 0x1 - - - - - PDEN_USBFSPHY - Controls power to USB Full Speed phy. - 11 - 1 - read-write - - - POWEREDON - USB Full Speed phy is powered. - 0 - - - POWEREDOFF - USB Full Speed phy is powered down. - 0x1 - - - - - PDEN_USBHSPHY - Controls power to USB High Speed Phy. - 12 - 1 - read-write - - - POWEREDON - USB HS phy is powered. - 0 - - - POWEREDOFF - USB HS phy is powered down. - 0x1 - - - - - PDEN_COMP - Controls power to Analog Comparator. - 13 - 1 - read-write - - - POWEREDON - Analog Comparator is powered. - 0 - - - POWEREDOFF - Analog Comparator is powered down. - 0x1 - - - - - PDEN_LDOUSBHS - Controls power to USB high speed LDO. - 18 - 1 - read-write - - - POWEREDON - USB high speed LDO is powered. - 0 - - - POWEREDOFF - USB high speed LDO is powered down. - 0x1 - - - - - PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS) - 19 - 1 - read-write - - - POWEREDON - auxiliary biasing is powered. - 0 - - - POWEREDOFF - auxiliary biasing is powered down. - 0x1 - - - - - PDEN_LDOXO32M - Controls power to high speed crystal LDO. - 20 - 1 - read-write - - - POWEREDON - High speed crystal LDO is powered. - 0 - - - POWEREDOFF - High speed crystal LDO is powered down. - 0x1 - - - - - PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources. - 22 - 1 - read-write - - - POWEREDON - TRNG clocks are powered. - 0 - - - POWEREDOFF - TRNG clocks are powered down. - 0x1 - - - - - PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. - 23 - 1 - read-write - - - POWEREDON - PLL0 Sread spectrum module is powered. - 0 - - - POWEREDOFF - PLL0 Sread spectrum module is powered down. - 0x1 - - - - - - - PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0xC0 - 32 - write-only - 0 - 0xFFFFFFFF - - - PDRUNCFGSET0 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. - 0 - 32 - write-only - - - - - PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0xC8 - 32 - write-only - 0 - 0xFFFFFFFF - - - PDRUNCFGCLR0 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. - 0 - 32 - write-only - - - - - SRAMCTRL - All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] - 0xD4 - 32 - read-write - 0x1 - 0x1FF - - - SMB - Source Biasing voltage. - 0 - 2 - read-write - - - LOW - Low leakage. - 0 - - - MEDIUM - Medium leakage. - 0x1 - - - HIGHEST - Highest leakage. - 0x2 - - - DISABLE - Disable. - 0x3 - - - - - RM - Read Margin control settings. - 2 - 3 - read-write - - - WM - Write Margin control settings. - 5 - 3 - read-write - - - WRME - Write read margin enable. - 8 - 1 - read-write - - - - - - - SYSCTL - system controller - SYSCTL - 0x40023000 - - 0 - 0x104 - registers - - - - UPDATELCKOUT - update lock out control - 0 - 32 - read-write - 0 - 0x1 - - - UPDATELCKOUT - All Registers - 0 - 1 - read-write - - - NORMAL_MODE - Normal Mode. Can be written to. - 0 - - - PROTECTED_MODE - Protected Mode. Cannot be written to. - 0x1 - - - - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - FCCTRLSEL%s - Selects the source for SCK going into Flexcomm index - 0x40 - 32 - read-write - 0 - 0x3030303 - - - SCKINSEL - Selects the source for SCK going into this Flexcomm. - 0 - 2 - read-writeOnce - - - ORIG_FLEX_I2S_SIGNALS - Selects the dedicated FCn_SCK function for this Flexcomm. - 0 - - - SHARED_SET0_I2S_SIGNALS - SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - 0x1 - - - SHARED_SET1_I2S_SIGNALS - SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - 0x2 - - - - - WSINSEL - Selects the source for WS going into this Flexcomm. - 8 - 2 - read-write - - - ORIG_FLEX_I2S_SIGNALS - Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. - 0 - - - SHARED_SET0_I2S_SIGNALS - WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - 0x1 - - - SHARED_SET1_I2S_SIGNALS - WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - 0x2 - - - - - DATAINSEL - Selects the source for DATA input to this Flexcomm. - 16 - 2 - read-write - - - ORIG_FLEX_I2S_SIGNALS - Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. - 0 - - - SHARED_SET0_I2S_SIGNALS - Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - 0x1 - - - SHARED_SET1_I2S_SIGNALS - Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - 0x2 - - - - - DATAOUTSEL - Selects the source for DATA output from this Flexcomm. - 24 - 2 - read-write - - - ORIG_FLEX_I2S_SIGNALS - Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. - 0 - - - SHARED_SET0_I2S_SIGNALS - Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - 0x1 - - - SHARED_SET1_I2S_SIGNALS - Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - 0x2 - - - - - - - 2 - 0x4 - 0,1 - SHAREDCTRLSET%s - Selects sources and data combinations for shared signal set index. - 0x80 - 32 - read-write - 0 - 0xFF0777 - - - SHAREDSCKSEL - Selects the source for SCK of this shared signal set. - 0 - 3 - read-write - - - FLEXCOMM0 - SCK for this shared signal set comes from Flexcomm 0. - 0 - - - FLEXCOMM1 - SCK for this shared signal set comes from Flexcomm 1. - 0x1 - - - FLEXCOMM2 - SCK for this shared signal set comes from Flexcomm 2. - 0x2 - - - FLEXCOMM3 - SCK for this shared signal set comes from Flexcomm 3. - 0x3 - - - FLEXCOMM4 - SCK for this shared signal set comes from Flexcomm 4. - 0x4 - - - FLEXCOMM5 - SCK for this shared signal set comes from Flexcomm 5. - 0x5 - - - FLEXCOMM6 - SCK for this shared signal set comes from Flexcomm 6. - 0x6 - - - FLEXCOMM7 - SCK for this shared signal set comes from Flexcomm 7. - 0x7 - - - - - SHAREDWSSEL - Selects the source for WS of this shared signal set. - 4 - 3 - read-write - - - FLEXCOMM0 - WS for this shared signal set comes from Flexcomm 0. - 0 - - - FLEXCOMM1 - WS for this shared signal set comes from Flexcomm 1. - 0x1 - - - FLEXCOMM2 - WS for this shared signal set comes from Flexcomm 2. - 0x2 - - - FLEXCOMM3 - WS for this shared signal set comes from Flexcomm 3. - 0x3 - - - FLEXCOMM4 - WS for this shared signal set comes from Flexcomm 4. - 0x4 - - - FLEXCOMM5 - WS for this shared signal set comes from Flexcomm 5. - 0x5 - - - FLEXCOMM6 - WS for this shared signal set comes from Flexcomm 6. - 0x6 - - - FLEXCOMM7 - WS for this shared signal set comes from Flexcomm 7. - 0x7 - - - - - SHAREDDATASEL - Selects the source for DATA input for this shared signal set. - 8 - 3 - read-write - - - FLEXCOMM0 - DATA input for this shared signal set comes from Flexcomm 0. - 0 - - - FLEXCOMM1 - DATA input for this shared signal set comes from Flexcomm 1. - 0x1 - - - FLEXCOMM2 - DATA input for this shared signal set comes from Flexcomm 2. - 0x2 - - - FLEXCOMM3 - DATA input for this shared signal set comes from Flexcomm 3. - 0x3 - - - FLEXCOMM4 - DATA input for this shared signal set comes from Flexcomm 4. - 0x4 - - - FLEXCOMM5 - DATA input for this shared signal set comes from Flexcomm 5. - 0x5 - - - FLEXCOMM6 - DATA input for this shared signal set comes from Flexcomm 6. - 0x6 - - - FLEXCOMM7 - DATA input for this shared signal set comes from Flexcomm 7. - 0x7 - - - - - FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set. - 16 - 1 - read-write - - - INPUT - Data output from FC0 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC0 does contribute to this shared set. - 0x1 - - - - - FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set. - 17 - 1 - read-write - - - INPUT - Data output from FC1 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC1 does contribute to this shared set. - 0x1 - - - - - FC2DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. - 18 - 1 - read-write - - - INPUT - Data output from FC2 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC2 does contribute to this shared set. - 0x1 - - - - - FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set. - 20 - 1 - read-write - - - INPUT - Data output from FC4 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC4 does contribute to this shared set. - 0x1 - - - - - FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set. - 21 - 1 - read-write - - - INPUT - Data output from FC5 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC5 does contribute to this shared set. - 0x1 - - - - - FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set. - 22 - 1 - read-write - - - INPUT - Data output from FC6 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC6 does contribute to this shared set. - 0x1 - - - - - FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set. - 23 - 1 - read-write - - - INPUT - Data output from FC7 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC7 does contribute to this shared set. - 0x1 - - - - - - - USB_HS_STATUS - Status register for USB HS - 0x100 - 32 - read-only - 0 - 0x1C0FF00 - - - USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply. - 0 - 1 - read-only - - - SUPPLY_3V_OK - 3v3 supply is good. - 0 - - - SUPPLY_3V_LOW - 3v3 supply is too low. - 0x1 - - - - - - - - - RTC - Real-Time Clock (RTC) - RTC - 0x4002C000 - - 0 - 0x60 - registers - - - RTC - 29 - - - - CTRL - RTC control register - 0 - 32 - read-write - 0x1 - 0x7FD - - - SWRESET - Software reset control - 0 - 1 - read-write - - - NOT_IN_RESET - Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. - 0 - - - IN_RESET - In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared. - 0x1 - - - - - ALARM1HZ - RTC 1 Hz timer alarm flag status. - 2 - 1 - read-write - - - NO_MATCH - No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. - 0 - - - MATCH - Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. - 0x1 - - - - - WAKE1KHZ - RTC 1 kHz timer wake-up flag status. - 3 - 1 - read-write - - - RUN - Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. - 0 - - - TIMEOUT - Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. - 0x1 - - - - - ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. - 4 - 1 - read-write - - - DISABLE - Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. - 0 - - - ENABLE - Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. - 0x1 - - - - - WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. - 5 - 1 - read-write - - - DISABLE - Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - 0 - - - ENABLE - Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. - 0x1 - - - - - RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). - 6 - 1 - read-write - - - DISABLE - Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - 0 - - - ENABLE - Enable. The 1 kHz RTC timer is enabled. - 0x1 - - - - - RTC_EN - RTC enable. - 7 - 1 - read-write - - - DISABLE - Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register. - 0 - - - ENABLE - Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register. - 0x1 - - - - - RTC_OSC_PD - RTC oscillator power-down control. - 8 - 1 - read-write - - - POWER_UP - See RTC_OSC_BYPASS - 0 - - - POWERED_DOWN - RTC oscillator is powered-down. - 0x1 - - - - - RTC_OSC_BYPASS - RTC oscillator bypass control. - 9 - 1 - read-write - - - USED - The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. - 0 - - - BYPASS - The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. - 0x1 - - - - - RTC_SUBSEC_ENA - RTC Sub-second counter control. - 10 - 1 - read-write - - - POWER_UP - The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second counter, this bit will always read-back as a '0'. - 0 - - - POWERED_DOWN - The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip exits deep power-down mode. - 0x1 - - - - - - - MATCH - RTC match register - 0x4 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. - 0 - 32 - read-write - - - - - COUNT - RTC counter register - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after the RTC_EN bit is set. - 0 - 32 - read-write - - - - - WAKE - High-resolution/wake-up timer control register - 0xC - 32 - read-write - 0 - 0xFFFF - - - VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence. Do not write to this register while counting is in progress. - 0 - 16 - read-write - - - - - SUBSEC - Sub-second counter register - 0x10 - 32 - read-write - 0 - 0xFFFF - - - SUBSEC - A read reflects the current value of the 32KHz sub-second counter. This counter is cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This counter must be re-enabled after exiting deep power-down mode or after the main RTC module is disabled and re-enabled. On modules not equipped with a sub-second counter, this register will read-back as all zeroes. - 0 - 15 - read-only - - - - - 8 - 0x4 - GPREG[%s] - General Purpose register - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied. - 0 - 32 - read-write - - - - - - - OSTIMER - Synchronous OS/Event timer with Wakeup Timer - OSTIMER - 0x4002D000 - - 0 - 0x20 - registers - - - OS_EVENT - 38 - - - - EVTIMERL - EVTIMER Low Register - 0 - 32 - read-only - 0 - 0xFFFFFFFF - - - EVTIMER_COUNT_VALUE - A read reflects the current value of the lower 32 bits of the 42-bits EVTIMER. Note: There is only one EVTIMER, readable from all domains. - 0 - 32 - read-only - - - - - EVTIMERH - EVTIMER High Register - 0x4 - 32 - read-write - 0 - 0xFFFFFFFF - - - EVTIMER_COUNT_VALUE - A read reflects the current value of the upper 10 bits of the 42-bits EVTIMER. Note there is only one EVTIMER, readable from all domains. - 0 - 10 - read-only - - - - - CAPTURE_L - Capture Low Register - 0x8 - 32 - read-only - 0 - 0xFFFFFFFF - - - CAPTURE_VALUE - A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). - 0 - 32 - read-only - - - - - CAPTURE_H - Capture High Register - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPTURE_VALUE - A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). - 0 - 10 - read-only - - - - - MATCH_L - Match Low Register - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCH_VALUE - The value written to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. - 0 - 32 - read-write - - - - - MATCH_H - Match High Register - 0x14 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCH_VALUE - The value written (upper 10 bits) to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. - 0 - 10 - read-write - - - - - OSEVENT_CTRL - OS_EVENT TIMER Control Register - 0x1C - 32 - read-write - 0 - 0x7 - - - OSTIMER_INTRFLAG - This bit is set when a match occurs between the central 42-bits EVTIMER and the value programmed in the match-register pair. This bit is cleared by writing a '1'. Writes to clear this bit are asynchronous. It should be done before a new match value is written into the MATCH_L/H registers. - 0 - 1 - read-write - - - OSTIMER_INTENA - When this bit is '1' an interrupt/wakeup request to the domain processor will be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests due to the OSTIMER_INTR flag are blocked. - 1 - 1 - read-write - - - MATCH_WR_RDY - This bit will be low when it is safe to write to reload the Match Registers. In typical applications it should not be necessary to test this bit. [1] - 2 - 1 - read-only - - - - - - - FLASH - FLASH - FLASH - 0x40034000 - - 0 - 0x1000 - registers - - - - CMD - command register - 0 - 32 - write-only - 0 - 0xFFFFFFFF - - - CMD - command register. - 0 - 32 - write-only - - - - - EVENT - event register - 0x4 - 32 - write-only - 0 - 0x7 - - - RST - When bit is set, the controller and flash are reset. - 0 - 1 - write-only - - - WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active. - 1 - 1 - write-only - - - ABORT - When bit is set, a running program/erase command is aborted. - 2 - 1 - write-only - - - - - STARTA - start (or only) address for next flash command - 0x10 - 32 - read-write - 0 - 0x3FFFF - - - STARTA - Address / Start address for commands that take an address (range) as a parameter. - 0 - 18 - read-write - - - - - STOPA - end address for next flash command, if command operates on address ranges - 0x14 - 32 - read-write - 0 - 0x3FFFF - - - STOPA - Stop address for commands that take an address range as a parameter (the word specified by STOPA is included in the address range). - 0 - 18 - read-write - - - - - 4 - 0x4 - DATAW[%s] - data register, word 0-7; Memory data, or command parameter, or command result. - 0x80 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATAW - no description available - 0 - 32 - read-write - - - - - INT_CLR_ENABLE - Clear interrupt enable bits - 0xFD8 - 32 - write-only - 0 - 0xF - - - FAIL - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - 0 - 1 - write-only - - - ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - 1 - 1 - write-only - - - DONE - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - 2 - 1 - write-only - - - ECC_ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - 3 - 1 - write-only - - - - - INT_SET_ENABLE - Set interrupt enable bits - 0xFDC - 32 - write-only - 0 - 0xF - - - FAIL - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - 0 - 1 - write-only - - - ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - 1 - 1 - write-only - - - DONE - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - 2 - 1 - write-only - - - ECC_ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - 3 - 1 - write-only - - - - - INT_STATUS - Interrupt status bits - 0xFE0 - 32 - read-write - 0 - 0xF - - - FAIL - This status bit is set if execution of a (legal) command failed. - 0 - 1 - read-only - - - ERR - This status bit is set if execution of an illegal command is detected. - 1 - 1 - read-only - - - DONE - This status bit is set at the end of command execution. - 2 - 1 - read-only - - - ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested read, or a speculative read, or reads performed by a controller command), a correctable or uncorrectable error is detected by ECC decoding logic. - 3 - 1 - read-only - - - - - INT_ENABLE - Interrupt enable bits - 0xFE4 - 32 - read-write - 0 - 0xF - - - FAIL - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - 0 - 1 - read-only - - - ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - 1 - 1 - read-only - - - DONE - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - 2 - 1 - read-only - - - ECC_ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - 3 - 1 - read-only - - - - - INT_CLR_STATUS - Clear interrupt status bits - 0xFE8 - 32 - write-only - 0 - 0xF - - - FAIL - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - 0 - 1 - write-only - - - ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - 1 - 1 - write-only - - - DONE - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - 2 - 1 - write-only - - - ECC_ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - 3 - 1 - write-only - - - - - INT_SET_STATUS - Set interrupt status bits - 0xFEC - 32 - write-only - 0 - 0xF - - - FAIL - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - 0 - 1 - write-only - - - ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - 1 - 1 - write-only - - - DONE - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - 2 - 1 - write-only - - - ECC_ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - 3 - 1 - write-only - - - - - MODULE_ID - Controller+Memory module identification - 0xFFC - 32 - read-only - 0xC40F0800 - 0xFFFFFFFF - - - APERTURE - Aperture i. - 0 - 8 - read-only - - - MINOR_REV - Minor revision i. - 8 - 4 - read-only - - - MAJOR_REV - Major revision i. - 12 - 4 - read-only - - - ID - Identifier. - 16 - 16 - read-only - - - - - - - PRINCE - PRINCE - PRINCE - 0x40035000 - - 0 - 0x40 - registers - - - - ENC_ENABLE - Encryption Enable register - 0 - 32 - read-write - 0 - 0x1 - - - EN - Encryption Enable. - 0 - 1 - read-write - - - DISABLED - Encryption of writes to the flash controller DATAW* registers is disabled. - 0 - - - ENABLED - Encryption of writes to the flash controller DATAW* registers is enabled. - 0x1 - - - - - - - MASK_LSB - Data Mask register, 32 Least Significant Bits - 0x4 - 32 - write-only - 0 - 0xFFFFFFFF - - - MASKVAL - Value of the 32 Least Significant Bits of the 64-bit data mask. - 0 - 32 - write-only - - - - - MASK_MSB - Data Mask register, 32 Most Significant Bits - 0x8 - 32 - write-only - 0 - 0xFFFFFFFF - - - MASKVAL - Value of the 32 Most Significant Bits of the 64-bit data mask. - 0 - 32 - write-only - - - - - LOCK - Lock register - 0xC - 32 - read-write - 0 - 0x107 - - - LOCKREG0 - Lock Region 0 registers. - 0 - 1 - read-write - - - DISABLED - Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. - 0 - - - ENABLED - Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. - 0x1 - - - - - LOCKREG1 - Lock Region 1 registers. - 1 - 1 - read-write - - - DISABLED - Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. - 0 - - - ENABLED - Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. - 0x1 - - - - - LOCKREG2 - Lock Region 2 registers. - 2 - 1 - read-write - - - DISABLED - Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. - 0 - - - ENABLED - Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. - 0x1 - - - - - LOCKMASK - Lock the Mask registers. - 8 - 1 - read-write - - - DISABLED - Disabled. MASK_LSB, and MASK_MSB are writable.. - 0 - - - ENABLED - Enabled. MASK_LSB, and MASK_MSB are not writable.. - 0x1 - - - - - - - IV_LSB0 - Initial Vector register for region 0, Least Significant Bits - 0x10 - 32 - write-only - 0 - 0xFFFFFFFF - - - IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - 0 - 32 - write-only - - - - - IV_MSB0 - Initial Vector register for region 0, Most Significant Bits - 0x14 - 32 - write-only - 0 - 0xFFFFFFFF - - - IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - 0 - 32 - write-only - - - - - BASE_ADDR0 - Base Address for region 0 register - 0x18 - 32 - read-write - 0 - 0xFFFFF - - - ADDR_FIXED - Fixed portion of the base address of region 0. - 0 - 18 - read-only - - - ADDR_PRG - Programmable portion of the base address of region 0. - 18 - 2 - read-write - - - - - SR_ENABLE0 - Sub-Region Enable register for region 0 - 0x1C - 32 - read-write - 0 - 0xFFFFFFFF - - - EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0. - 0 - 32 - read-write - - - - - IV_LSB1 - Initial Vector register for region 1, Least Significant Bits - 0x20 - 32 - write-only - 0 - 0xFFFFFFFF - - - IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - 0 - 32 - write-only - - - - - IV_MSB1 - Initial Vector register for region 1, Most Significant Bits - 0x24 - 32 - write-only - 0 - 0xFFFFFFFF - - - IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - 0 - 32 - write-only - - - - - BASE_ADDR1 - Base Address for region 1 register - 0x28 - 32 - read-write - 0x40000 - 0xFFFFF - - - ADDR_FIXED - Fixed portion of the base address of region 1. - 0 - 18 - read-only - - - ADDR_PRG - Programmable portion of the base address of region 1. - 18 - 2 - read-write - - - - - SR_ENABLE1 - Sub-Region Enable register for region 1 - 0x2C - 32 - read-write - 0 - 0xFFFFFFFF - - - EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1. - 0 - 32 - read-write - - - - - IV_LSB2 - Initial Vector register for region 2, Least Significant Bits - 0x30 - 32 - write-only - 0 - 0xFFFFFFFF - - - IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - 0 - 32 - write-only - - - - - IV_MSB2 - Initial Vector register for region 2, Most Significant Bits - 0x34 - 32 - write-only - 0 - 0xFFFFFFFF - - - IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - 0 - 32 - write-only - - - - - BASE_ADDR2 - Base Address for region 2 register - 0x38 - 32 - read-write - 0x80000 - 0xFFFFF - - - ADDR_FIXED - Fixed portion of the base address of region 2. - 0 - 18 - read-only - - - ADDR_PRG - Programmable portion of the base address of region 2. - 18 - 2 - read-write - - - - - SR_ENABLE2 - Sub-Region Enable register for region 2 - 0x3C - 32 - read-write - 0 - 0xFFFFFFFF - - - EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2. - 0 - 32 - read-write - - - - - - - USBPHY - Universal System Bus Physical Layer - USBPHY - 0x40038000 - - 0 - 0x110 - registers - - - USB1_PHY - 46 - - - - PWD - USB PHY Power-Down Register - 0 - 32 - read-write - 0x1E1C00 - 0xFFFFFFFF - - - TXPWDFS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 10 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - 0x1 - - - - - TXPWDIBIAS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 11 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - 0x1 - - - - - TXPWDV2I - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 12 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY transmit V-to-I converter and the current mirror - 0x1 - - - - - RXPWDENV - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 17 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed receiver envelope detector (squelch signal) - 0x1 - - - - - RXPWD1PT1 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 18 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed differential receiver. - 0x1 - - - - - RXPWDDIFF - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 19 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed differential receive - 0x1 - - - - - RXPWDRX - This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 20 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the entire USB PHY receiver block except for the full-speed differential receiver - 0x1 - - - - - - - PWD_SET - USB PHY Power-Down Register - 0x4 - 32 - read-write - 0x1E1C00 - 0xFFFFFFFF - - - TXPWDFS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 10 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - 0x1 - - - - - TXPWDIBIAS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 11 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - 0x1 - - - - - TXPWDV2I - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 12 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY transmit V-to-I converter and the current mirror - 0x1 - - - - - RXPWDENV - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 17 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed receiver envelope detector (squelch signal) - 0x1 - - - - - RXPWD1PT1 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 18 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed differential receiver. - 0x1 - - - - - RXPWDDIFF - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 19 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed differential receive - 0x1 - - - - - RXPWDRX - This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 20 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the entire USB PHY receiver block except for the full-speed differential receiver - 0x1 - - - - - - - PWD_CLR - USB PHY Power-Down Register - 0x8 - 32 - read-write - 0x1E1C00 - 0xFFFFFFFF - - - TXPWDFS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 10 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - 0x1 - - - - - TXPWDIBIAS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 11 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - 0x1 - - - - - TXPWDV2I - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 12 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY transmit V-to-I converter and the current mirror - 0x1 - - - - - RXPWDENV - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 17 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed receiver envelope detector (squelch signal) - 0x1 - - - - - RXPWD1PT1 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 18 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed differential receiver. - 0x1 - - - - - RXPWDDIFF - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 19 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed differential receive - 0x1 - - - - - RXPWDRX - This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 20 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the entire USB PHY receiver block except for the full-speed differential receiver - 0x1 - - - - - - - PWD_TOG - USB PHY Power-Down Register - 0xC - 32 - read-write - 0x1E1C00 - 0xFFFFFFFF - - - TXPWDFS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 10 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - 0x1 - - - - - TXPWDIBIAS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 11 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - 0x1 - - - - - TXPWDV2I - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 12 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY transmit V-to-I converter and the current mirror - 0x1 - - - - - RXPWDENV - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 17 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed receiver envelope detector (squelch signal) - 0x1 - - - - - RXPWD1PT1 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 18 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed differential receiver. - 0x1 - - - - - RXPWDDIFF - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 19 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed differential receive - 0x1 - - - - - RXPWDRX - This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 20 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the entire USB PHY receiver block except for the full-speed differential receiver - 0x1 - - - - - - - TX - USB PHY Transmitter Control Register - 0x10 - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - D_CAL - Decode to trim the nominal 17 - 0 - 4 - read-write - - - value0 - Maximum current, approximately 19% above nominal. - 0 - - - value7 - Nominal - 0x7 - - - value15 - Minimum current, approximately 19% below nominal. - 0xF - - - - - TXCAL45DM - Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin - 8 - 4 - read-write - - - TXENCAL45DN - Enable resistance calibration on DN. - 13 - 1 - read-write - - - TXCAL45DP - Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin - 16 - 4 - read-write - - - TXENCAL45DP - Enable resistance calibration on DP. - 21 - 1 - read-write - - - - - TX_SET - USB PHY Transmitter Control Register - 0x14 - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - D_CAL - Decode to trim the nominal 17 - 0 - 4 - read-write - - - value0 - Maximum current, approximately 19% above nominal. - 0 - - - value7 - Nominal - 0x7 - - - value15 - Minimum current, approximately 19% below nominal. - 0xF - - - - - TXCAL45DM - Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin - 8 - 4 - read-write - - - TXENCAL45DN - Enable resistance calibration on DN. - 13 - 1 - read-write - - - TXCAL45DP - Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin - 16 - 4 - read-write - - - TXENCAL45DP - Enable resistance calibration on DP. - 21 - 1 - read-write - - - - - TX_CLR - USB PHY Transmitter Control Register - 0x18 - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - D_CAL - Decode to trim the nominal 17 - 0 - 4 - read-write - - - value0 - Maximum current, approximately 19% above nominal. - 0 - - - value7 - Nominal - 0x7 - - - value15 - Minimum current, approximately 19% below nominal. - 0xF - - - - - TXCAL45DM - Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin - 8 - 4 - read-write - - - TXENCAL45DN - Enable resistance calibration on DN. - 13 - 1 - read-write - - - TXCAL45DP - Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin - 16 - 4 - read-write - - - TXENCAL45DP - Enable resistance calibration on DP. - 21 - 1 - read-write - - - - - TX_TOG - USB PHY Transmitter Control Register - 0x1C - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - D_CAL - Decode to trim the nominal 17 - 0 - 4 - read-write - - - value0 - Maximum current, approximately 19% above nominal. - 0 - - - value7 - Nominal - 0x7 - - - value15 - Minimum current, approximately 19% below nominal. - 0xF - - - - - TXCAL45DM - Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin - 8 - 4 - read-write - - - TXENCAL45DN - Enable resistance calibration on DN. - 13 - 1 - read-write - - - TXCAL45DP - Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin - 16 - 4 - read-write - - - TXENCAL45DP - Enable resistance calibration on DP. - 21 - 1 - read-write - - - - - RX - USB PHY Receiver Control Register - 0x20 - 32 - read-write - 0 - 0xFFFFFFFF - - - ENVADJ - The ENVADJ field adjusts the trip point for the envelope detector - 0 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.1000 V - 0 - - - value1 - Trip-Level Voltage is 0.1125 V - 0x1 - - - value2 - Trip-Level Voltage is 0.1250 V - 0x2 - - - value3 - Trip-Level Voltage is 0.0875 V - 0x3 - - - - - DISCONADJ - The DISCONADJ field adjusts the trip point for the disconnect detector. - 4 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.56875 V - 0 - - - value1 - Trip-Level Voltage is 0.55000 V - 0x1 - - - value2 - Trip-Level Voltage is 0.58125 V - 0x2 - - - value3 - Trip-Level Voltage is 0.60000 V - 0x3 - - - - - RXDBYPASS - This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver - 22 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - 0x1 - - - - - - - RX_SET - USB PHY Receiver Control Register - 0x24 - 32 - read-write - 0 - 0xFFFFFFFF - - - ENVADJ - The ENVADJ field adjusts the trip point for the envelope detector - 0 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.1000 V - 0 - - - value1 - Trip-Level Voltage is 0.1125 V - 0x1 - - - value2 - Trip-Level Voltage is 0.1250 V - 0x2 - - - value3 - Trip-Level Voltage is 0.0875 V - 0x3 - - - - - DISCONADJ - The DISCONADJ field adjusts the trip point for the disconnect detector. - 4 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.56875 V - 0 - - - value1 - Trip-Level Voltage is 0.55000 V - 0x1 - - - value2 - Trip-Level Voltage is 0.58125 V - 0x2 - - - value3 - Trip-Level Voltage is 0.60000 V - 0x3 - - - - - RXDBYPASS - This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver - 22 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - 0x1 - - - - - - - RX_CLR - USB PHY Receiver Control Register - 0x28 - 32 - read-write - 0 - 0xFFFFFFFF - - - ENVADJ - The ENVADJ field adjusts the trip point for the envelope detector - 0 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.1000 V - 0 - - - value1 - Trip-Level Voltage is 0.1125 V - 0x1 - - - value2 - Trip-Level Voltage is 0.1250 V - 0x2 - - - value3 - Trip-Level Voltage is 0.0875 V - 0x3 - - - - - DISCONADJ - The DISCONADJ field adjusts the trip point for the disconnect detector. - 4 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.56875 V - 0 - - - value1 - Trip-Level Voltage is 0.55000 V - 0x1 - - - value2 - Trip-Level Voltage is 0.58125 V - 0x2 - - - value3 - Trip-Level Voltage is 0.60000 V - 0x3 - - - - - RXDBYPASS - This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver - 22 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - 0x1 - - - - - - - RX_TOG - USB PHY Receiver Control Register - 0x2C - 32 - read-write - 0 - 0xFFFFFFFF - - - ENVADJ - The ENVADJ field adjusts the trip point for the envelope detector - 0 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.1000 V - 0 - - - value1 - Trip-Level Voltage is 0.1125 V - 0x1 - - - value2 - Trip-Level Voltage is 0.1250 V - 0x2 - - - value3 - Trip-Level Voltage is 0.0875 V - 0x3 - - - - - DISCONADJ - The DISCONADJ field adjusts the trip point for the disconnect detector. - 4 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.56875 V - 0 - - - value1 - Trip-Level Voltage is 0.55000 V - 0x1 - - - value2 - Trip-Level Voltage is 0.58125 V - 0x2 - - - value3 - Trip-Level Voltage is 0.60000 V - 0x3 - - - - - RXDBYPASS - This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver - 22 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - 0x1 - - - - - - - CTRL - USB PHY General Control Register - 0x30 - 32 - read-write - 0xC0000000 - 0xFFFFFFFF - - - ENHOSTDISCONDETECT - For host mode, enables high-speed disconnect detector - 1 - 1 - read-write - - - ENIRQHOSTDISCON - Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode - 2 - 1 - read-write - - - HOSTDISCONDETECT_IRQ - Indicates that the device has disconnected in High-Speed mode - 3 - 1 - read-write - - - ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode - 4 - 1 - read-write - - - value0 - Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - 0 - - - value1 - Enables 200kohm pullup resistors on USB_DP and USB_DM pins - 0x1 - - - - - DEVPLUGIN_POLARITY - Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in - 5 - 1 - read-write - - - RESUMEIRQSTICKY - Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it - 8 - 1 - read-write - - - ENIRQRESUMEDETECT - Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line - 9 - 1 - read-write - - - RESUME_IRQ - Resume IRQ: Indicates that the host is sending a wake-up after suspend - 10 - 1 - read-write - - - DEVPLUGIN_IRQ - Indicates that the device is connected - 12 - 1 - read-write - - - ENUTMILEVEL2 - Enables UTMI+ Level 2 operation for the USB HS PHY - 14 - 1 - read-write - - - ENUTMILEVEL3 - Enables UTMI+ Level 3 operation for the USB HS PHY - 15 - 1 - read-write - - - ENIRQWAKEUP - Enable wake-up IRQ: Enables interrupt for the wake-up events. - 16 - 1 - read-write - - - WAKEUP_IRQ - Wake-up IRQ: Indicates that there is a wak-eup event - 17 - 1 - read-write - - - AUTORESUME_EN - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) - 18 - 1 - read-write - - - ENAUTOCLR_CLKGATE - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended - 19 - 1 - read-write - - - ENAUTOCLR_PHY_PWD - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended - 20 - 1 - read-write - - - ENDPDMCHG_WKUP - Enable DP DM change wake-up: Not for customer use - 21 - 1 - read-write - - - ENVBUSCHG_WKUP - Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended - 23 - 1 - read-write - - - ENAUTOCLR_USBCLKGATE - Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 25 - 1 - read-write - - - ENAUTOSET_USBCLKS - Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 26 - 1 - read-write - - - HOST_FORCE_LS_SE0 - Forces the next FS packet that is transmitted to have a EOP with low-speed timing - 28 - 1 - read-write - - - UTMI_SUSPENDM - Used by the PHY to indicate a powered-down state - 29 - 1 - read-write - - - CLKGATE - Gate UTMI Clocks - 30 - 1 - read-write - - - SFTRST - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers - 31 - 1 - read-write - - - - - CTRL_SET - USB PHY General Control Register - 0x34 - 32 - read-write - 0xC0000000 - 0xFFFFFFFF - - - ENHOSTDISCONDETECT - For host mode, enables high-speed disconnect detector - 1 - 1 - read-write - - - ENIRQHOSTDISCON - Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode - 2 - 1 - read-write - - - HOSTDISCONDETECT_IRQ - Indicates that the device has disconnected in High-Speed mode - 3 - 1 - read-write - - - ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode - 4 - 1 - read-write - - - value0 - Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - 0 - - - value1 - Enables 200kohm pullup resistors on USB_DP and USB_DM pins - 0x1 - - - - - DEVPLUGIN_POLARITY - Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in - 5 - 1 - read-write - - - RESUMEIRQSTICKY - Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it - 8 - 1 - read-write - - - ENIRQRESUMEDETECT - Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line - 9 - 1 - read-write - - - RESUME_IRQ - Resume IRQ: Indicates that the host is sending a wake-up after suspend - 10 - 1 - read-write - - - DEVPLUGIN_IRQ - Indicates that the device is connected - 12 - 1 - read-write - - - ENUTMILEVEL2 - Enables UTMI+ Level 2 operation for the USB HS PHY - 14 - 1 - read-write - - - ENUTMILEVEL3 - Enables UTMI+ Level 3 operation for the USB HS PHY - 15 - 1 - read-write - - - ENIRQWAKEUP - Enable wake-up IRQ: Enables interrupt for the wake-up events. - 16 - 1 - read-write - - - WAKEUP_IRQ - Wake-up IRQ: Indicates that there is a wak-eup event - 17 - 1 - read-write - - - AUTORESUME_EN - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) - 18 - 1 - read-write - - - ENAUTOCLR_CLKGATE - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended - 19 - 1 - read-write - - - ENAUTOCLR_PHY_PWD - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended - 20 - 1 - read-write - - - ENDPDMCHG_WKUP - Enable DP DM change wake-up: Not for customer use - 21 - 1 - read-write - - - ENVBUSCHG_WKUP - Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended - 23 - 1 - read-write - - - ENAUTOCLR_USBCLKGATE - Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 25 - 1 - read-write - - - ENAUTOSET_USBCLKS - Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 26 - 1 - read-write - - - HOST_FORCE_LS_SE0 - Forces the next FS packet that is transmitted to have a EOP with low-speed timing - 28 - 1 - read-write - - - UTMI_SUSPENDM - Used by the PHY to indicate a powered-down state - 29 - 1 - read-only - - - CLKGATE - Gate UTMI Clocks - 30 - 1 - read-write - - - SFTRST - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers - 31 - 1 - read-write - - - - - CTRL_CLR - USB PHY General Control Register - 0x38 - 32 - read-write - 0xC0000000 - 0xFFFFFFFF - - - ENHOSTDISCONDETECT - For host mode, enables high-speed disconnect detector - 1 - 1 - read-write - - - ENIRQHOSTDISCON - Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode - 2 - 1 - read-write - - - HOSTDISCONDETECT_IRQ - Indicates that the device has disconnected in High-Speed mode - 3 - 1 - read-write - - - ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode - 4 - 1 - read-write - - - value0 - Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - 0 - - - value1 - Enables 200kohm pullup resistors on USB_DP and USB_DM pins - 0x1 - - - - - DEVPLUGIN_POLARITY - Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in - 5 - 1 - read-write - - - RESUMEIRQSTICKY - Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it - 8 - 1 - read-write - - - ENIRQRESUMEDETECT - Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line - 9 - 1 - read-write - - - RESUME_IRQ - Resume IRQ: Indicates that the host is sending a wake-up after suspend - 10 - 1 - read-write - - - DEVPLUGIN_IRQ - Indicates that the device is connected - 12 - 1 - read-write - - - ENUTMILEVEL2 - Enables UTMI+ Level 2 operation for the USB HS PHY - 14 - 1 - read-write - - - ENUTMILEVEL3 - Enables UTMI+ Level 3 operation for the USB HS PHY - 15 - 1 - read-write - - - ENIRQWAKEUP - Enable wake-up IRQ: Enables interrupt for the wake-up events. - 16 - 1 - read-write - - - WAKEUP_IRQ - Wake-up IRQ: Indicates that there is a wak-eup event - 17 - 1 - read-write - - - AUTORESUME_EN - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) - 18 - 1 - read-write - - - ENAUTOCLR_CLKGATE - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended - 19 - 1 - read-write - - - ENAUTOCLR_PHY_PWD - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended - 20 - 1 - read-write - - - ENDPDMCHG_WKUP - Enable DP DM change wake-up: Not for customer use - 21 - 1 - read-write - - - ENVBUSCHG_WKUP - Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended - 23 - 1 - read-write - - - ENAUTOCLR_USBCLKGATE - Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 25 - 1 - read-write - - - ENAUTOSET_USBCLKS - Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 26 - 1 - read-write - - - HOST_FORCE_LS_SE0 - Forces the next FS packet that is transmitted to have a EOP with low-speed timing - 28 - 1 - read-write - - - UTMI_SUSPENDM - Used by the PHY to indicate a powered-down state - 29 - 1 - read-write - - - CLKGATE - Gate UTMI Clocks - 30 - 1 - read-write - - - SFTRST - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers - 31 - 1 - read-write - - - - - CTRL_TOG - USB PHY General Control Register - 0x3C - 32 - read-write - 0xC0000000 - 0xFFFFFFFF - - - ENHOSTDISCONDETECT - For host mode, enables high-speed disconnect detector - 1 - 1 - read-write - - - ENIRQHOSTDISCON - Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode - 2 - 1 - read-write - - - HOSTDISCONDETECT_IRQ - Indicates that the device has disconnected in High-Speed mode - 3 - 1 - read-write - - - ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode - 4 - 1 - read-write - - - value0 - Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - 0 - - - value1 - Enables 200kohm pullup resistors on USB_DP and USB_DM pins - 0x1 - - - - - DEVPLUGIN_POLARITY - Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in - 5 - 1 - read-write - - - RESUMEIRQSTICKY - Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it - 8 - 1 - read-write - - - ENIRQRESUMEDETECT - Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line - 9 - 1 - read-write - - - RESUME_IRQ - Resume IRQ: Indicates that the host is sending a wake-up after suspend - 10 - 1 - read-write - - - DEVPLUGIN_IRQ - Indicates that the device is connected - 12 - 1 - read-write - - - ENUTMILEVEL2 - Enables UTMI+ Level 2 operation for the USB HS PHY - 14 - 1 - read-write - - - ENUTMILEVEL3 - Enables UTMI+ Level 3 operation for the USB HS PHY - 15 - 1 - read-write - - - ENIRQWAKEUP - Enable wake-up IRQ: Enables interrupt for the wake-up events. - 16 - 1 - read-write - - - WAKEUP_IRQ - Wake-up IRQ: Indicates that there is a wak-eup event - 17 - 1 - read-write - - - AUTORESUME_EN - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) - 18 - 1 - read-write - - - ENAUTOCLR_CLKGATE - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended - 19 - 1 - read-write - - - ENAUTOCLR_PHY_PWD - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended - 20 - 1 - read-write - - - ENDPDMCHG_WKUP - Enable DP DM change wake-up: Not for customer use - 21 - 1 - read-write - - - ENVBUSCHG_WKUP - Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended - 23 - 1 - read-write - - - ENAUTOCLR_USBCLKGATE - Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 25 - 1 - read-write - - - ENAUTOSET_USBCLKS - Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 26 - 1 - read-write - - - HOST_FORCE_LS_SE0 - Forces the next FS packet that is transmitted to have a EOP with low-speed timing - 28 - 1 - read-write - - - UTMI_SUSPENDM - Used by the PHY to indicate a powered-down state - 29 - 1 - read-write - - - CLKGATE - Gate UTMI Clocks - 30 - 1 - read-write - - - SFTRST - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers - 31 - 1 - read-write - - - - - STATUS - USB PHY Status Register - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - OK_STATUS_3V - Indicates the USB 3v power rails are in range. - 0 - 1 - read-only - - - HOSTDISCONDETECT_STATUS - Indicates at the local host (downstream) port that the remote device has disconnected while in High-Speed mode - 3 - 1 - read-only - - - value0 - USB cable disconnect has not been detected at the local host - 0 - - - value1 - USB cable disconnect has been detected at the local host - 0x1 - - - - - DEVPLUGIN_STATUS - Status indicator for non-standard resistive plugged-in detection Indicates that the device has been connected on the USB_DP and USB_DM lines using the nonstandard resistive plugged-in detection method controlled by CTRL[4] - 6 - 1 - read-only - - - value0 - No attachment to a USB host is detected - 0 - - - value1 - Cable attachment to a USB host is detected - 0x1 - - - - - RESUME_STATUS - Indicates that the host is sending a wake-up after Suspend and has triggered an interrupt. - 10 - 1 - read-only - - - - - PLL_SIC - USB PHY PLL Control/Status Register - 0xA0 - 32 - read-write - 0xD12000 - 0xFFFFFFFF - - - PLL_EN_USB_CLKS - Enables the USB clock from PLL to USB PHY - 6 - 1 - read-write - - - PLL_POWER - Power up the USB PLL - 12 - 1 - read-write - - - PLL_ENABLE - Enables the clock output from the USB PLL - 13 - 1 - read-write - - - REFBIAS_PWD_SEL - Reference bias power down select. - 19 - 1 - read-write - - - value0 - Selects PLL_POWER to control the reference bias - 0 - - - value1 - Selects REFBIAS_PWD to control the reference bias - 0x1 - - - - - REFBIAS_PWD - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. - 20 - 1 - read-write - - - PLL_REG_ENABLE - This field controls the USB PLL regulator, set to enable the regulator - 21 - 1 - read-write - - - PLL_DIV_SEL - This field controls the USB PLL feedback loop divider - 22 - 3 - read-write - - - value0 - Divide by 13 - 0 - - - value1 - Divide by 15 - 0x1 - - - value2 - Divide by 16 - 0x2 - - - value3 - Divide by 20 - 0x3 - - - value4 - Divide by 22 - 0x4 - - - value5 - Divide by 25 - 0x5 - - - value6 - Divide by 30 - 0x6 - - - value7 - Divide by 240 - 0x7 - - - - - PLL_PREDIV - This is selection between /1 or /2 to expand the range of ref input clock. - 30 - 1 - read-write - - - PLL_LOCK - USB PLL lock status indicator - 31 - 1 - read-only - - - value0 - PLL is not currently locked - 0 - - - value1 - PLL is currently locked - 0x1 - - - - - - - PLL_SIC_SET - USB PHY PLL Control/Status Register - 0xA4 - 32 - read-write - 0xD12000 - 0xFFFFFFFF - - - PLL_EN_USB_CLKS - Enables the USB clock from PLL to USB PHY - 6 - 1 - read-write - - - PLL_POWER - Power up the USB PLL - 12 - 1 - read-write - - - PLL_ENABLE - Enables the clock output from the USB PLL - 13 - 1 - read-write - - - REFBIAS_PWD_SEL - Reference bias power down select. - 19 - 1 - read-write - - - value0 - Selects PLL_POWER to control the reference bias - 0 - - - value1 - Selects REFBIAS_PWD to control the reference bias - 0x1 - - - - - REFBIAS_PWD - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. - 20 - 1 - read-write - - - PLL_REG_ENABLE - This field controls the USB PLL regulator, set to enable the regulator - 21 - 1 - read-write - - - PLL_DIV_SEL - This field controls the USB PLL feedback loop divider - 22 - 3 - read-write - - - value0 - Divide by 13 - 0 - - - value1 - Divide by 15 - 0x1 - - - value2 - Divide by 16 - 0x2 - - - value3 - Divide by 20 - 0x3 - - - value4 - Divide by 22 - 0x4 - - - value5 - Divide by 25 - 0x5 - - - value6 - Divide by 30 - 0x6 - - - value7 - Divide by 240 - 0x7 - - - - - PLL_PREDIV - This is selection between /1 or /2 to expand the range of ref input clock. - 30 - 1 - read-write - - - PLL_LOCK - USB PLL lock status indicator - 31 - 1 - read-only - - - value0 - PLL is not currently locked - 0 - - - value1 - PLL is currently locked - 0x1 - - - - - - - PLL_SIC_CLR - USB PHY PLL Control/Status Register - 0xA8 - 32 - read-write - 0xD12000 - 0xFFFFFFFF - - - PLL_EN_USB_CLKS - Enables the USB clock from PLL to USB PHY - 6 - 1 - read-write - - - PLL_POWER - Power up the USB PLL - 12 - 1 - read-write - - - PLL_ENABLE - Enables the clock output from the USB PLL - 13 - 1 - read-write - - - REFBIAS_PWD_SEL - Reference bias power down select. - 19 - 1 - read-write - - - value0 - Selects PLL_POWER to control the reference bias - 0 - - - value1 - Selects REFBIAS_PWD to control the reference bias - 0x1 - - - - - REFBIAS_PWD - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. - 20 - 1 - read-write - - - PLL_REG_ENABLE - This field controls the USB PLL regulator, set to enable the regulator - 21 - 1 - read-write - - - PLL_DIV_SEL - This field controls the USB PLL feedback loop divider - 22 - 3 - read-write - - - value0 - Divide by 13 - 0 - - - value1 - Divide by 15 - 0x1 - - - value2 - Divide by 16 - 0x2 - - - value3 - Divide by 20 - 0x3 - - - value4 - Divide by 22 - 0x4 - - - value5 - Divide by 25 - 0x5 - - - value6 - Divide by 30 - 0x6 - - - value7 - Divide by 240 - 0x7 - - - - - PLL_PREDIV - This is selection between /1 or /2 to expand the range of ref input clock. - 30 - 1 - read-write - - - PLL_LOCK - USB PLL lock status indicator - 31 - 1 - read-only - - - value0 - PLL is not currently locked - 0 - - - value1 - PLL is currently locked - 0x1 - - - - - - - PLL_SIC_TOG - USB PHY PLL Control/Status Register - 0xAC - 32 - read-write - 0xD12000 - 0xFFFFFFFF - - - PLL_EN_USB_CLKS - Enables the USB clock from PLL to USB PHY - 6 - 1 - read-write - - - PLL_POWER - Power up the USB PLL - 12 - 1 - read-write - - - PLL_ENABLE - Enables the clock output from the USB PLL - 13 - 1 - read-write - - - REFBIAS_PWD_SEL - Reference bias power down select. - 19 - 1 - read-write - - - value0 - Selects PLL_POWER to control the reference bias - 0 - - - value1 - Selects REFBIAS_PWD to control the reference bias - 0x1 - - - - - REFBIAS_PWD - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. - 20 - 1 - read-write - - - PLL_REG_ENABLE - This field controls the USB PLL regulator, set to enable the regulator - 21 - 1 - read-write - - - PLL_DIV_SEL - This field controls the USB PLL feedback loop divider - 22 - 3 - read-write - - - value0 - Divide by 13 - 0 - - - value1 - Divide by 15 - 0x1 - - - value2 - Divide by 16 - 0x2 - - - value3 - Divide by 20 - 0x3 - - - value4 - Divide by 22 - 0x4 - - - value5 - Divide by 25 - 0x5 - - - value6 - Divide by 30 - 0x6 - - - value7 - Divide by 240 - 0x7 - - - - - PLL_PREDIV - This is selection between /1 or /2 to expand the range of ref input clock. - 30 - 1 - read-write - - - PLL_LOCK - USB PLL lock status indicator - 31 - 1 - read-only - - - value0 - PLL is not currently locked - 0 - - - value1 - PLL is currently locked - 0x1 - - - - - - - USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register - 0xC0 - 32 - read-write - 0x700004 - 0xFFFFFFFF - - - VBUSVALID_THRESH - Sets the threshold for the VBUSVALID comparator - 0 - 3 - read-write - - - value0 - 4.0V - 0 - - - value1 - 4.1V - 0x1 - - - value2 - 4.2V - 0x2 - - - value3 - 4.3V - 0x3 - - - value4 - 4.4V(Default) - 0x4 - - - value5 - 4.5V - 0x5 - - - value6 - 4.6V - 0x6 - - - value7 - 4.7V - 0x7 - - - - - VBUS_OVERRIDE_EN - VBUS detect signal override enable - 3 - 1 - read-write - - - value0 - Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - 0 - - - value1 - Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - 0x1 - - - - - SESSEND_OVERRIDE - Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 - 4 - 1 - read-write - - - BVALID_OVERRIDE - Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 - 5 - 1 - read-write - - - AVALID_OVERRIDE - Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 - 6 - 1 - read-write - - - VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 - 7 - 1 - read-write - - - VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 8 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the VBUS_VALID_3V detector results for signal reported to the USB controller - 0x1 - - - - - VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 9 - 2 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the Session Valid comparator results for signal reported to the USB controller - 0x1 - - - value2 - Use the Session Valid comparator results for signal reported to the USB controller - 0x2 - - - - - ID_OVERRIDE_EN - Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. - 11 - 1 - read-write - - - ID_OVERRIDE - ID override value. - 12 - 1 - read-write - - - EXT_ID_OVERRIDE_EN - Enable ID override using the pinmuxed value: - 13 - 1 - read-write - - - value0 - Select the Muxed value chosen using ID_OVERRIDE_EN. - 0 - - - value1 - Select the external ID value. - 0x1 - - - - - EXT_VBUS_OVERRIDE_EN - Enable VBUS override using the pinmuxed value. - 14 - 1 - read-write - - - value0 - Select the Muxed value chosen using VBUS_OVERRIDE_EN. - 0 - - - value1 - Select the external VBUS VALID value. - 0x1 - - - - - VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator - 18 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator for VBUS_VALID results - 0 - - - value1 - Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - 0x1 - - - - - VBUSVALID_5VDETECT - no description available - 19 - 1 - read-write - - - PWRUP_CMPS - Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector - 20 - 3 - read-write - - - value0 - Powers down the VBUS_VALID comparator - 0 - - - value1 - Enables the VBUS_VALID comparator (default) - 0x7 - - - - - DISCHARGE_VBUS - Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground - 26 - 1 - read-write - - - value0 - VBUS discharge resistor is disabled (Default) - 0 - - - value1 - VBUS discharge resistor is enabled - 0x1 - - - - - - - USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register - 0xC4 - 32 - read-write - 0x700004 - 0xFFFFFFFF - - - VBUSVALID_THRESH - Sets the threshold for the VBUSVALID comparator - 0 - 3 - read-write - - - value0 - 4.0V - 0 - - - value1 - 4.1V - 0x1 - - - value2 - 4.2V - 0x2 - - - value3 - 4.3V - 0x3 - - - value4 - 4.4V(Default) - 0x4 - - - value5 - 4.5V - 0x5 - - - value6 - 4.6V - 0x6 - - - value7 - 4.7V - 0x7 - - - - - VBUS_OVERRIDE_EN - VBUS detect signal override enable - 3 - 1 - read-write - - - value0 - Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - 0 - - - value1 - Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - 0x1 - - - - - SESSEND_OVERRIDE - Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 - 4 - 1 - read-write - - - BVALID_OVERRIDE - Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 - 5 - 1 - read-write - - - AVALID_OVERRIDE - Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 - 6 - 1 - read-write - - - VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 - 7 - 1 - read-write - - - VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 8 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the VBUS_VALID_3V detector results for signal reported to the USB controller - 0x1 - - - - - VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 9 - 2 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the Session Valid comparator results for signal reported to the USB controller - 0x1 - - - value2 - Use the Session Valid comparator results for signal reported to the USB controller - 0x2 - - - - - ID_OVERRIDE_EN - Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. - 11 - 1 - read-write - - - ID_OVERRIDE - ID override value. - 12 - 1 - read-write - - - EXT_ID_OVERRIDE_EN - Enable ID override using the pinmuxed value: - 13 - 1 - read-write - - - value0 - Select the Muxed value chosen using ID_OVERRIDE_EN. - 0 - - - value1 - Select the external ID value. - 0x1 - - - - - EXT_VBUS_OVERRIDE_EN - Enable VBUS override using the pinmuxed value. - 14 - 1 - read-write - - - value0 - Select the Muxed value chosen using VBUS_OVERRIDE_EN. - 0 - - - value1 - Select the external VBUS VALID value. - 0x1 - - - - - VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator - 18 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator for VBUS_VALID results - 0 - - - value1 - Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - 0x1 - - - - - VBUSVALID_5VDETECT - no description available - 19 - 1 - read-write - - - PWRUP_CMPS - Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector - 20 - 3 - read-write - - - value0 - Powers down the VBUS_VALID comparator - 0 - - - value1 - Enables the VBUS_VALID comparator (default) - 0x7 - - - - - DISCHARGE_VBUS - Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground - 26 - 1 - read-write - - - value0 - VBUS discharge resistor is disabled (Default) - 0 - - - value1 - VBUS discharge resistor is enabled - 0x1 - - - - - - - USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register - 0xC8 - 32 - read-write - 0x700004 - 0xFFFFFFFF - - - VBUSVALID_THRESH - Sets the threshold for the VBUSVALID comparator - 0 - 3 - read-write - - - value0 - 4.0V - 0 - - - value1 - 4.1V - 0x1 - - - value2 - 4.2V - 0x2 - - - value3 - 4.3V - 0x3 - - - value4 - 4.4V(Default) - 0x4 - - - value5 - 4.5V - 0x5 - - - value6 - 4.6V - 0x6 - - - value7 - 4.7V - 0x7 - - - - - VBUS_OVERRIDE_EN - VBUS detect signal override enable - 3 - 1 - read-write - - - value0 - Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - 0 - - - value1 - Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - 0x1 - - - - - SESSEND_OVERRIDE - Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 - 4 - 1 - read-write - - - BVALID_OVERRIDE - Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 - 5 - 1 - read-write - - - AVALID_OVERRIDE - Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 - 6 - 1 - read-write - - - VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 - 7 - 1 - read-write - - - VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 8 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the VBUS_VALID_3V detector results for signal reported to the USB controller - 0x1 - - - - - VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 9 - 2 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the Session Valid comparator results for signal reported to the USB controller - 0x1 - - - value2 - Use the Session Valid comparator results for signal reported to the USB controller - 0x2 - - - - - ID_OVERRIDE_EN - Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. - 11 - 1 - read-write - - - ID_OVERRIDE - ID override value. - 12 - 1 - read-write - - - EXT_ID_OVERRIDE_EN - Enable ID override using the pinmuxed value: - 13 - 1 - read-write - - - value0 - Select the Muxed value chosen using ID_OVERRIDE_EN. - 0 - - - value1 - Select the external ID value. - 0x1 - - - - - EXT_VBUS_OVERRIDE_EN - Enable VBUS override using the pin muxed value. - 14 - 1 - read-write - - - value0 - Select the muxed value chosen using VBUS_OVERRIDE_EN. - 0 - - - value1 - Select the external VBUS VALID value. - 0x1 - - - - - VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator - 18 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator for VBUS_VALID results - 0 - - - value1 - Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - 0x1 - - - - - VBUSVALID_5VDETECT - no description available - 19 - 1 - read-write - - - PWRUP_CMPS - Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector - 20 - 3 - read-write - - - value0 - Powers down the VBUS_VALID comparator - 0 - - - value1 - Enables the VBUS_VALID comparator (default) - 0x7 - - - - - DISCHARGE_VBUS - Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground - 26 - 1 - read-write - - - value0 - VBUS discharge resistor is disabled (Default) - 0 - - - value1 - VBUS discharge resistor is enabled - 0x1 - - - - - - - USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register - 0xCC - 32 - read-write - 0x700004 - 0xFFFFFFFF - - - VBUSVALID_THRESH - Sets the threshold for the VBUSVALID comparator - 0 - 3 - read-write - - - value0 - 4.0V - 0 - - - value1 - 4.1V - 0x1 - - - value2 - 4.2V - 0x2 - - - value3 - 4.3V - 0x3 - - - value4 - 4.4V(Default) - 0x4 - - - value5 - 4.5V - 0x5 - - - value6 - 4.6V - 0x6 - - - value7 - 4.7V - 0x7 - - - - - VBUS_OVERRIDE_EN - VBUS detect signal override enable - 3 - 1 - read-write - - - value0 - Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - 0 - - - value1 - Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - 0x1 - - - - - SESSEND_OVERRIDE - Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 - 4 - 1 - read-write - - - BVALID_OVERRIDE - Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 - 5 - 1 - read-write - - - AVALID_OVERRIDE - Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 - 6 - 1 - read-write - - - VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 - 7 - 1 - read-write - - - VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 8 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the VBUS_VALID_3V detector results for signal reported to the USB controller - 0x1 - - - - - VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 9 - 2 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the Session Valid comparator results for signal reported to the USB controller - 0x1 - - - value2 - Use the Session Valid comparator results for signal reported to the USB controller - 0x2 - - - - - ID_OVERRIDE_EN - Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. - 11 - 1 - read-write - - - ID_OVERRIDE - ID override value. - 12 - 1 - read-write - - - EXT_ID_OVERRIDE_EN - Enable ID override using the pin muxed value. - 13 - 1 - read-write - - - value0 - Select the muxed value chosen using ID_OVERRIDE_EN. - 0 - - - value1 - Select the external ID value. - 0x1 - - - - - EXT_VBUS_OVERRIDE_EN - Enable VBUS override using the pin muxed value. - 14 - 1 - read-write - - - value0 - Select the Muxed value chosen using VBUS_OVERRIDE_EN. - 0 - - - value1 - Select the external VBUS VALID value. - 0x1 - - - - - VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator - 18 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator for VBUS_VALID results - 0 - - - value1 - Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - 0x1 - - - - - VBUSVALID_5VDETECT - no description available - 19 - 1 - read-write - - - PWRUP_CMPS - Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector - 20 - 3 - read-write - - - value0 - Powers down the VBUS_VALID comparator - 0 - - - value1 - Enables the VBUS_VALID comparator (default) - 0x7 - - - - - DISCHARGE_VBUS - Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground - 26 - 1 - read-write - - - value0 - VBUS discharge resistor is disabled (Default) - 0 - - - value1 - VBUS discharge resistor is enabled - 0x1 - - - - - - - ANACTRL - USB PHY Analog Control Register - 0x100 - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - LVI_EN - Vow voltage detector enable bit. - 1 - 1 - read-write - - - PFD_CLK_SEL - For normal USB operation, this bit field must remain at value 2'b00. - 2 - 2 - read-write - - - DEV_PULLDOWN - Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins - 10 - 1 - read-write - - - value0 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - 0 - - - value1 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - 0x1 - - - - - - - ANACTRL_SET - USB PHY Analog Control Register - 0x104 - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - LVI_EN - Vow voltage detector enable bit. - 1 - 1 - read-write - - - PFD_CLK_SEL - For normal USB operation, this bit field must remain at value 2'b00. - 2 - 2 - read-write - - - DEV_PULLDOWN - Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins - 10 - 1 - read-write - - - value0 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - 0 - - - value1 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - 0x1 - - - - - - - ANACTRL_CLR - USB PHY Analog Control Register - 0x108 - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - LVI_EN - Vow voltage detector enable bit. - 1 - 1 - read-write - - - PFD_CLK_SEL - For normal USB operation, this bit field must remain at value 2'b00. - 2 - 2 - read-write - - - DEV_PULLDOWN - Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins - 10 - 1 - read-write - - - value0 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - 0 - - - value1 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - 0x1 - - - - - - - ANACTRL_TOG - USB PHY Analog Control Register - 0x10C - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - LVI_EN - Vow voltage detector enable bit. - 1 - 1 - read-write - - - PFD_CLK_SEL - For normal USB operation, this bit field must remain at value 2'b00. - 2 - 2 - read-write - - - DEV_PULLDOWN - Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins - 10 - 1 - read-write - - - value0 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - 0 - - - value1 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - 0x1 - - - - - - - - - RNG - RNG - RNG - 0x4003A000 - - 0 - 0x1000 - registers - - - - RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read - 0 - 32 - read-only - 0 - 0xFFFFFFFF - - - RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read. - 0 - 32 - read-only - - - - - COUNTER_VAL - no description available - 0x8 - 32 - read-write - 0 - 0x1FFF - - - CLK_RATIO - Gives the ratio between the internal clocks frequencies and the register clock frequency for evaluation and certification purposes. - 0 - 8 - read-only - - - REFRESH_CNT - Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER. - 8 - 5 - read-only - - - - - COUNTER_CFG - no description available - 0xC - 32 - read-write - 0 - 0x3FF - - - MODE - 00: disabled 01: update once. - 0 - 2 - read-write - - - CLOCK_SEL - Selects the internal clock on which to compute statistics. - 2 - 3 - read-write - - - SHIFT4X - To be used to add precision to clock_ratio and determine 'entropy refill'. - 5 - 3 - read-write - - - - - ONLINE_TEST_CFG - no description available - 0x10 - 32 - read-write - 0 - 0x7 - - - ACTIVATE - 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER. - 0 - 1 - read-write - - - DATA_SEL - Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10: RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this field. - 1 - 2 - read-write - - - - - ONLINE_TEST_VAL - no description available - 0x14 - 32 - read-write - 0 - 0xFFF - - - LIVE_CHI_SQUARED - This value is updated as described in field 'activate'. - 0 - 4 - read-only - - - MIN_CHI_SQUARED - This field is reset when 'activate'==0. - 4 - 4 - read-only - - - MAX_CHI_SQUARED - This field is reset when 'activate'==0. - 8 - 4 - read-only - - - - - MODULEID - IP identifier - 0xFFC - 32 - read-only - 0xA0B83200 - 0xFFFFFFFF - - - APERTURE - Aperture i. - 0 - 8 - read-only - - - MIN_REV - Minor revision i. - 8 - 4 - read-only - - - MAJ_REV - Major revision i. - 12 - 4 - read-only - - - ID - Identifier. - 16 - 16 - read-only - - - - - - - PUF - PUFCTRL - PUF - 0x4003B000 - - 0 - 0x260 - registers - - - PUF - 56 - - - - CTRL - PUF Control register - 0 - 32 - read-write - 0 - 0x5F - - - zeroize - Begin Zeroize operation for PUF and go to Error state - 0 - 1 - read-write - - - enroll - Begin Enroll operation - 1 - 1 - read-write - - - start - Begin Start operation - 2 - 1 - read-write - - - GENERATEKEY - Begin Set Intrinsic Key operation - 3 - 1 - read-write - - - SETKEY - Begin Set User Key operation - 4 - 1 - read-write - - - GETKEY - Begin Get Key operation - 6 - 1 - read-write - - - - - KEYINDEX - PUF Key Index register - 0x4 - 32 - read-write - 0 - 0xF - - - KEYIDX - Key index for Set Key operations - 0 - 4 - read-write - - - - - KEYSIZE - PUF Key Size register - 0x8 - 32 - read-write - 0 - 0x3F - - - KEYSIZE - Key size for Set Key operations - 0 - 6 - read-write - - - - - STAT - PUF Status register - 0x20 - 32 - read-write - 0x1 - 0xF7 - - - busy - Indicates that operation is in progress - 0 - 1 - read-only - - - SUCCESS - Last operation was successful - 1 - 1 - read-only - - - error - PUF is in the Error state and no operations can be performed - 2 - 1 - read-only - - - KEYINREQ - Request for next part of key - 4 - 1 - read-only - - - KEYOUTAVAIL - Next part of key is available - 5 - 1 - read-only - - - CODEINREQ - Request for next part of AC/KC - 6 - 1 - read-only - - - CODEOUTAVAIL - Next part of AC/KC is available - 7 - 1 - read-only - - - - - ALLOW - PUF Allow register - 0x28 - 32 - read-write - 0 - 0x8F - - - ALLOWENROLL - Enroll operation is allowed - 0 - 1 - read-only - - - ALLOWSTART - Start operation is allowed - 1 - 1 - read-only - - - ALLOWSETKEY - Set Key operations are allowed - 2 - 1 - read-only - - - ALLOWGETKEY - Get Key operation is allowed - 3 - 1 - read-only - - - - - KEYINPUT - PUF Key Input register - 0x40 - 32 - write-only - 0 - 0xFFFFFFFF - - - KEYIN - Key input data - 0 - 32 - write-only - - - - - CODEINPUT - PUF Code Input register - 0x44 - 32 - write-only - 0 - 0xFFFFFFFF - - - CODEIN - AC/KC input data - 0 - 32 - write-only - - - - - CODEOUTPUT - PUF Code Output register - 0x48 - 32 - read-only - 0 - 0xFFFFFFFF - - - CODEOUT - AC/KC output data - 0 - 32 - read-only - - - - - KEYOUTINDEX - PUF Key Output Index register - 0x60 - 32 - read-write - 0 - 0xF - - - KEYOUTIDX - Key index for the key that is currently output via the Key Output register - 0 - 4 - read-only - - - - - KEYOUTPUT - PUF Key Output register - 0x64 - 32 - read-only - 0 - 0xFFFFFFFF - - - KEYOUT - Key output data - 0 - 32 - read-only - - - - - IFSTAT - PUF Interface Status and clear register - 0xDC - 32 - read-write - 0 - 0x1 - - - ERROR - Indicates that an APB error has occurred,Writing logic1 clears the if_error bit - 0 - 1 - read-write - - - - - VERSION - PUF version register. - 0xFC - 32 - read-only - 0 - 0xFFFFFFFF - - - VERSION - Version of the PUF module. - 0 - 32 - read-only - - - - - INTEN - PUF Interrupt Enable - 0x100 - 32 - read-write - 0 - 0xF7 - - - READYEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - 0 - 1 - read-write - - - SUCCESEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - 1 - 1 - read-write - - - ERROREN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - 2 - 1 - read-write - - - KEYINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - 4 - 1 - read-write - - - KEYOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - 5 - 1 - read-write - - - CODEINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - 6 - 1 - read-write - - - CODEOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - 7 - 1 - read-write - - - - - INTSTAT - PUF interrupt status - 0x104 - 32 - read-write - 0 - 0xF7 - - - READY - Triggers on falling edge of busy, write 1 to clear - 0 - 1 - read-write - - - SUCCESS - Level sensitive interrupt, cleared when interrupt source clears - 1 - 1 - read-write - - - ERROR - Level sensitive interrupt, cleared when interrupt source clears - 2 - 1 - read-write - - - KEYINREQ - Level sensitive interrupt, cleared when interrupt source clears - 4 - 1 - read-write - - - KEYOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears - 5 - 1 - read-write - - - CODEINREQ - Level sensitive interrupt, cleared when interrupt source clears - 6 - 1 - read-write - - - CODEOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears - 7 - 1 - read-write - - - - - PWRCTRL - PUF RAM Power Control - 0x108 - 32 - read-write - 0xF8 - 0xFD - - - RAMON - Power on the PUF RAM. - 0 - 1 - read-write - - - RAMSTAT - PUF RAM status. - 1 - 1 - read-write - - - - - CFG - PUF config register for block bits - 0x10C - 32 - read-write - 0 - 0x3 - - - BLOCKENROLL_SETKEY - Block enroll operation. Write 1 to set, cleared on reset. - 0 - 1 - read-write - - - BLOCKKEYOUTPUT - Block set key operation. Write 1 to set, cleared on reset. - 1 - 1 - read-write - - - - - KEYLOCK - Only reset in case of full IC reset - 0x200 - 32 - read-write - 0xAA - 0xFF - - - KEY0 - "10:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is allowed. 00, 01, 11:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." - 0 - 2 - read-write - - - KEY1 - "10:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is allowed. 00, 01, 11:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." - 2 - 2 - read-write - - - KEY2 - "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." - 4 - 2 - read-write - - - KEY3 - "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." - 6 - 2 - read-write - - - - - KEYENABLE - no description available - 0x204 - 32 - read-write - 0x55 - 0xFF - - - KEY0 - "10: Data coming out from PUF Index 0 interface are shifted in KEY0 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY0 register." - 0 - 2 - read-write - - - KEY1 - "10: Data coming out from PUF Index 0 interface are shifted in KEY1 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY1 register." - 2 - 2 - read-write - - - KEY2 - "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY2 register." - 4 - 2 - read-write - - - KEY3 - "10: Data coming out from PUF Index 0 interface are shifted in KEY3 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." - 6 - 2 - read-write - - - - - KEYRESET - Reinitialize Keys shift registers counters - 0x208 - 32 - write-only - 0 - 0xFFFFFFFF - - - KEY0 - 10: Reset KEY0 shift register. Self clearing. Must be done before loading any new key. - 0 - 2 - write-only - - - KEY1 - 10: Reset KEY1 shift register. Self clearing. Must be done before loading any new key. - 2 - 2 - write-only - - - KEY2 - 10: Reset KEY2 shift register. Self clearing. Must be done before loading any new key. - 4 - 2 - write-only - - - KEY3 - 10: Reset KEY3 shift register. Self clearing. Must be done before loading any new key. - 6 - 2 - write-only - - - - - IDXBLK_L - no description available - 0x20C - 32 - read-write - 0x8000AAAA - 0xC000FFFF - - - IDX1 - Use to block PUF index 1 - 2 - 2 - read-write - - - IDX2 - Use to block PUF index 2 - 4 - 2 - read-write - - - IDX3 - Use to block PUF index 3 - 6 - 2 - read-write - - - IDX4 - Use to block PUF index 4 - 8 - 2 - read-write - - - IDX5 - Use to block PUF index 5 - 10 - 2 - read-write - - - IDX6 - Use to block PUF index 6 - 12 - 2 - read-write - - - IDX7 - Use to block PUF index 7 - 14 - 2 - read-write - - - LOCK_IDX - Lock 0 to 7 PUF key indexes - 30 - 2 - write-only - - - - - IDXBLK_H_DP - no description available - 0x210 - 32 - read-write - 0xAAAA - 0xFFFFFFFF - - - IDX8 - Use to block PUF index 8 - 0 - 2 - read-write - - - IDX9 - Use to block PUF index 9 - 2 - 2 - read-write - - - IDX10 - Use to block PUF index 10 - 4 - 2 - read-write - - - IDX11 - Use to block PUF index 11 - 6 - 2 - read-write - - - IDX12 - Use to block PUF index 12 - 8 - 2 - read-write - - - IDX13 - Use to block PUF index 13 - 10 - 2 - read-write - - - IDX14 - Use to block PUF index 14 - 12 - 2 - read-write - - - IDX15 - Use to block PUF index 15 - 14 - 2 - read-write - - - - - 4 - 0x4 - KEYMASK[%s] - Only reset in case of full IC reset - 0x214 - 32 - write-only - 0 - 0xFFFFFFFF - - - KEYMASK - no description available - 0 - 32 - write-only - - - - - IDXBLK_H - no description available - 0x254 - 32 - read-write - 0x8000AAAA - 0xC000FFFF - - - IDX8 - Use to block PUF index 8 - 0 - 2 - read-write - - - IDX9 - Use to block PUF index 9 - 2 - 2 - read-write - - - IDX10 - Use to block PUF index 10 - 4 - 2 - read-write - - - IDX11 - Use to block PUF index 11 - 6 - 2 - read-write - - - IDX12 - Use to block PUF index 12 - 8 - 2 - read-write - - - IDX13 - Use to block PUF index 13 - 10 - 2 - read-write - - - IDX14 - Use to block PUF index 14 - 12 - 2 - read-write - - - IDX15 - Use to block PUF index 15 - 14 - 2 - read-write - - - LOCK_IDX - Lock 8 to 15 PUF key indexes - 30 - 2 - write-only - - - - - IDXBLK_L_DP - no description available - 0x258 - 32 - read-write - 0xAAAA - 0xFFFF - - - IDX1 - Use to block PUF index 1 - 2 - 2 - read-write - - - IDX2 - Use to block PUF index 2 - 4 - 2 - read-write - - - IDX3 - Use to block PUF index 3 - 6 - 2 - read-write - - - IDX4 - Use to block PUF index 4 - 8 - 2 - read-write - - - IDX5 - Use to block PUF index 5 - 10 - 2 - read-write - - - IDX6 - Use to block PUF index 6 - 12 - 2 - read-write - - - IDX7 - Use to block PUF index 7 - 14 - 2 - read-write - - - - - SHIFT_STATUS - no description available - 0x25C - 32 - read-write - 0 - 0xFFFF - - - KEY0 - Index counter from key 0 shift register - 0 - 4 - read-only - - - KEY1 - Index counter from key 1 shift register - 4 - 4 - read-only - - - KEY2 - Index counter from key 2 shift register - 8 - 4 - read-only - - - KEY3 - Index counter from key 3 shift register - 12 - 4 - read-only - - - - - - - PLU - LPC80X Programmable Logic Unit (PLU) - PLU - 0x4003D000 - - 0 - 0xC20 - registers - - - PLU - 52 - - - - 26 - 0x20 - LUT[%s] - no description available - 0 - - 5 - 0x4 - 0,1,2,3,4 - LUT_INP_MUX%s - LUTn input x MUX - 0 - 32 - read-write - 0 - 0x3F - - - LUTn_INPx - Selects the input source to be connected to LUT0 input0. For each LUT, the slot associated with the output from LUTn itself is tied low. - 0 - 6 - read-write - - - plu_inputs0 - The PLU primary inputs 0. - 0 - - - plu_inputs1 - The PLU primary inputs 1. - 0x1 - - - plu_inputs2 - The PLU primary inputs 2. - 0x2 - - - plu_inputs3 - The PLU primary inputs 3. - 0x3 - - - plu_inputs4 - The PLU primary inputs 4. - 0x4 - - - plu_inputs5 - The PLU primary inputs 5. - 0x5 - - - lut_outputs0 - The output of LUT0. - 0x6 - - - lut_outputs1 - The output of LUT1. - 0x7 - - - lut_outputs2 - The output of LUT2. - 0x8 - - - lut_outputs3 - The output of LUT3. - 0x9 - - - lut_outputs4 - The output of LUT4. - 0xA - - - lut_outputs5 - The output of LUT5. - 0xB - - - lut_outputs6 - The output of LUT6. - 0xC - - - lut_outputs7 - The output of LUT7. - 0xD - - - lut_outputs8 - The output of LUT8. - 0xE - - - lut_outputs9 - The output of LUT9. - 0xF - - - lut_outputs10 - The output of LUT10. - 0x10 - - - lut_outputs11 - The output of LUT11. - 0x11 - - - lut_outputs12 - The output of LUT12. - 0x12 - - - lut_outputs13 - The output of LUT13. - 0x13 - - - lut_outputs14 - The output of LUT14. - 0x14 - - - lut_outputs15 - The output of LUT15. - 0x15 - - - lut_outputs16 - The output of LUT16. - 0x16 - - - lut_outputs17 - The output of LUT17. - 0x17 - - - lut_outputs18 - The output of LUT18. - 0x18 - - - lut_outputs19 - The output of LUT19. - 0x19 - - - lut_outputs20 - The output of LUT20. - 0x1A - - - lut_outputs21 - The output of LUT21. - 0x1B - - - lut_outputs22 - The output of LUT22. - 0x1C - - - lut_outputs23 - The output of LUT23. - 0x1D - - - lut_outputs24 - The output of LUT24. - 0x1E - - - lut_outputs25 - The output of LUT25. - 0x1F - - - state0 - state(0). - 0x20 - - - state1 - state(1). - 0x21 - - - state2 - state(2). - 0x22 - - - state3 - state(3). - 0x23 - - - - - - - - 26 - 0x4 - LUT_TRUTH[%s] - Specifies the Truth Table contents for LUTLUTn - 0x800 - 32 - read-write - 0 - 0xFFFFFFFF - - - LUTn_TRUTH - Specifies the Truth Table contents for LUT0.. - 0 - 32 - read-write - - - - - OUTPUTS - Provides the current state of the 8 designated PLU Outputs. - 0x900 - 32 - read-write - 0 - 0xFFFFFFFF - - - OUTPUT_STATE - Provides the current state of the 8 designated PLU Outputs.. - 0 - 8 - read-only - - - - - WAKEINT_CTRL - Wakeup interrupt control for PLU - 0x904 - 32 - read-write - 0 - 0xFFFFFFFF - - - MASK - Interrupt mask (which of the 8 PLU Outputs contribute to interrupt) - 0 - 8 - read-write - - - FILTER_MODE - control input of the PLU, add filtering for glitch. - 8 - 2 - read-write - - - BYPASS - Bypass mode. - 0 - - - FILTER1CLK - Filter 1 clock period. - 0x1 - - - FILTER2CLK - Filter 2 clock period. - 0x2 - - - FILTER3CLK - Filter 3 clock period. - 0x3 - - - - - FILTER_CLKSEL - hclk is divided by 2**filter_clksel. - 10 - 2 - read-write - - - FRO1MHZ - Selects the 1 MHz low-power oscillator as the filter clock. - 0 - - - FRO12MHZ - Selects the 12 Mhz FRO as the filter clock. - 0x1 - - - OTHER_CLOCK - Selects a third filter clock source, if provided. - 0x2 - - - - - LATCH_ENABLE - latch the interrupt , then can be cleared with next bit INTR_CLEAR - 12 - 1 - read-write - - - INTR_CLEAR - Write to clear wakeint_latched - 13 - 1 - read-write - oneToClear - - - - - 8 - 0x4 - OUTPUT_MUX[%s] - Selects the source to be connected to PLU Output OUTPUT_n - 0xC00 - 32 - read-write - 0 - 0xFFFFFFFF - - - OUTPUTn - Selects the source to be connected to PLU Output 0. - 0 - 5 - read-write - - - plu_output0 - The PLU output 0. - 0 - - - plu_output1 - The PLU output 1. - 0x1 - - - plu_output2 - The PLU output 2. - 0x2 - - - plu_output3 - The PLU output 3. - 0x3 - - - plu_output4 - The PLU output 4. - 0x4 - - - plu_output5 - The PLU output 5. - 0x5 - - - plu_output6 - The PLU output 6. - 0x6 - - - plu_output7 - The PLU output 7. - 0x7 - - - plu_output8 - The PLU output 8. - 0x8 - - - plu_output9 - The PLU output 9. - 0x9 - - - plu_output10 - The PLU output 10. - 0xA - - - plu_output11 - The PLU output 11. - 0xB - - - plu_output12 - The PLU output 12. - 0xC - - - plu_output13 - The PLU output 13. - 0xD - - - plu_output14 - The PLU output 14. - 0xE - - - plu_output15 - The PLU output 15. - 0xF - - - plu_output16 - The PLU output 16. - 0x10 - - - plu_output17 - The PLU output 17. - 0x11 - - - plu_output18 - The PLU output 18. - 0x12 - - - plu_output19 - The PLU output 19. - 0x13 - - - plu_output20 - The PLU output 20. - 0x14 - - - plu_output21 - The PLU output 21. - 0x15 - - - plu_output22 - The PLU output 22. - 0x16 - - - plu_output23 - The PLU output 23. - 0x17 - - - plu_output24 - The PLU output 24. - 0x18 - - - plu_output25 - The PLU output 25. - 0x19 - - - state0 - state(0). - 0x1A - - - state1 - state(1). - 0x1B - - - state2 - state(2). - 0x1C - - - state3 - state(3). - 0x1D - - - - - - - - - DMA0 - DMA controller - DMA - DMA - 0x40082000 - - 0 - 0x56C - registers - - - DMA0 - 1 - - - - CTRL - DMA control. - 0 - 32 - read-write - 0 - 0x1 - - - ENABLE - DMA controller master enable. - 0 - 1 - read-write - - - DISABLED - Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled. - 0 - - - ENABLED - Enabled. The DMA controller is enabled. - 0x1 - - - - - - - INTSTAT - Interrupt status. - 0x4 - 32 - read-only - 0 - 0x6 - - - ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. - 1 - 1 - read-only - - - NOT_PENDING - Not pending. No enabled interrupts are pending. - 0 - - - PENDING - Pending. At least one enabled interrupt is pending. - 0x1 - - - - - ACTIVEERRINT - Summarizes whether any error interrupts are pending. - 2 - 1 - read-only - - - NOT_PENDING - Not pending. No error interrupts are pending. - 0 - - - PENDING - Pending. At least one error interrupt is pending. - 0x1 - - - - - - - SRAMBASE - SRAM address of the channel configuration table. - 0x8 - 32 - read-write - 0 - 0xFFFFFE00 - - - OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the table must begin on a 512 byte boundary. - 9 - 23 - read-write - - - - - ENABLESET0 - Channel Enable read and Set for all DMA channels. - 0x20 - 32 - read-write - 0 - 0xFFFFFFFF - - - ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. - 0 - 32 - read-write - - - - - ENABLECLR0 - Channel Enable Clear for all DMA channels. - 0x28 - 32 - write-only - 0 - 0 - - - CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved. - 0 - 32 - write-only - - - - - ACTIVE0 - Channel Active status for all DMA channels. - 0x30 - 32 - read-only - 0 - 0xFFFFFFFF - - - ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. - 0 - 32 - read-only - - - - - BUSY0 - Channel Busy status for all DMA channels. - 0x38 - 32 - read-only - 0 - 0xFFFFFFFF - - - BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. - 0 - 32 - read-only - - - - - ERRINT0 - Error Interrupt status for all DMA channels. - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active. - 0 - 32 - read-write - - - - - INTENSET0 - Interrupt Enable read and Set for all DMA channels. - 0x48 - 32 - read-write - 0 - 0xFFFFFFFF - - - INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. - 0 - 32 - read-write - - - - - INTENCLR0 - Interrupt Enable Clear for all DMA channels. - 0x50 - 32 - write-only - 0 - 0 - - - CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. - 0 - 32 - write-only - - - - - INTA0 - Interrupt A status for all DMA channels. - 0x58 - 32 - read-write - 0 - 0xFFFFFFFF - - - IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. - 0 - 32 - read-write - - - - - INTB0 - Interrupt B status for all DMA channels. - 0x60 - 32 - read-write - 0 - 0xFFFFFFFF - - - IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. - 0 - 32 - read-write - - - - - SETVALID0 - Set ValidPending control bits for all DMA channels. - 0x68 - 32 - write-only - 0 - 0 - - - SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n - 0 - 32 - write-only - - - - - SETTRIG0 - Set Trigger control bits for all DMA channels. - 0x70 - 32 - write-only - 0 - 0 - - - TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. - 0 - 32 - write-only - - - - - ABORT0 - Channel Abort control for all DMA channels. - 0x78 - 32 - write-only - 0 - 0 - - - ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. - 0 - 32 - write-only - - - - - 23 - 0x10 - CHANNEL[%s] - no description available - 0x400 - - CFG - Configuration register for DMA channel . - 0 - 32 - read-write - 0 - 0x7CF73 - - - PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. - 0 - 1 - read-write - - - DISABLED - Disabled. Peripheral DMA requests are disabled. - 0 - - - ENABLED - Enabled. Peripheral DMA requests are enabled. - 0x1 - - - - - HWTRIGEN - Hardware Triggering Enable for this channel. - 1 - 1 - read-write - - - DISABLED - Disabled. Hardware triggering is not used. - 0 - - - ENABLED - Enabled. Use hardware triggering. - 0x1 - - - - - TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. - 4 - 1 - read-write - - - ACTIVE_LOW_FALLING - Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. - 0 - - - ACTIVE_HIGH_RISING - Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. - 0x1 - - - - - TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. - 5 - 1 - read-write - - - EDGE - Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. - 0 - - - LEVEL - Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. - 0x1 - - - - - TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. - 6 - 1 - read-write - - - SINGLE - Single transfer. Hardware trigger causes a single transfer. - 0 - - - BURST - Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. - 0x1 - - - - - BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. - 8 - 4 - read-write - - - SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. - 14 - 1 - read-write - - - DISABLED - Disabled. Source burst wrapping is not enabled for this DMA channel. - 0 - - - ENABLED - Enabled. Source burst wrapping is enabled for this DMA channel. - 0x1 - - - - - DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. - 15 - 1 - read-write - - - DISABLED - Disabled. Destination burst wrapping is not enabled for this DMA channel. - 0 - - - ENABLED - Enabled. Destination burst wrapping is enabled for this DMA channel. - 0x1 - - - - - CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. - 16 - 3 - read-write - - - - - CTLSTAT - Control and status register for DMA channel . - 0x4 - 32 - read-only - 0 - 0x5 - - - VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. - 0 - 1 - read-only - - - NO_EFFECT - No effect. No effect on DMA operation. - 0 - - - VALID_PENDING - Valid pending. - 0x1 - - - - - TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. - 2 - 1 - read-only - - - NOT_TRIGGERED - Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. - 0 - - - TRIGGERED - Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. - 0x1 - - - - - - - XFERCFG - Transfer configuration register for DMA channel . - 0x8 - 32 - read-write - 0 - 0x3FFF33F - - - CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. - 0 - 1 - read-write - - - NOT_VALID - Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. - 0 - - - VALID - Valid. The current channel descriptor is considered valid. - 0x1 - - - - - RELOAD - Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. - 1 - 1 - read-write - - - DISABLED - Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. - 0 - - - ENABLED - Enabled. Reload the channels' control structure when the current descriptor is exhausted. - 0x1 - - - - - SWTRIG - Software Trigger. - 2 - 1 - read-write - - - NOT_SET - Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. - 0 - - - SET - Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. - 0x1 - - - - - CLRTRIG - Clear Trigger. - 3 - 1 - read-write - - - NOT_CLEARED - Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. - 0 - - - CLEARED - Cleared. The trigger is cleared when this descriptor is exhausted - 0x1 - - - - - SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. - 4 - 1 - read-write - - - NO_EFFECT - No effect. - 0 - - - SET - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. - 0x1 - - - - - SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. - 5 - 1 - read-write - - - NO_EFFECT - No effect. - 0 - - - SET - Set. The INTB flag for this channel will be set when the current descriptor is exhausted. - 0x1 - - - - - WIDTH - Transfer width used for this DMA channel. - 8 - 2 - read-write - - - BIT_8 - 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). - 0 - - - BIT_16 - 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). - 0x1 - - - BIT_32 - 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). - 0x2 - - - - - SRCINC - Determines whether the source address is incremented for each DMA transfer. - 12 - 2 - read-write - - - NO_INCREMENT - No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. - 0 - - - WIDTH_X_1 - 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. - 0x1 - - - WIDTH_X_2 - 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. - 0x2 - - - WIDTH_X_4 - 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. - 0x3 - - - - - DSTINC - Determines whether the destination address is incremented for each DMA transfer. - 14 - 2 - read-write - - - NO_INCREMENT - No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. - 0 - - - WIDTH_X_1 - 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. - 0x1 - - - WIDTH_X_2 - 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. - 0x2 - - - WIDTH_X_4 - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. - 0x3 - - - - - XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. - 16 - 10 - read-write - - - - - - - - DMA1 - DMA controller - DMA - 0x400A7000 - - 0 - 0x49C - registers - - - DMA1 - 58 - - - - USB0 - USB 2.0 Device Controller - USB - 0x40084000 - - 0 - 0x38 - registers - - - USB0_NEEDCLK - 27 - - - USB0 - 28 - - - - DEVCMDSTAT - USB Device Command/Status register - 0 - 32 - read-write - 0x800 - 0x171BFBFF - - - DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request. - 0 - 7 - read-write - - - DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. - 7 - 1 - read-write - - - SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. - 8 - 1 - read-write - - - FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: - 9 - 1 - read-write - - - NORMAL - USB_NEEDCLK has normal function. - 0 - - - ALWAYS_ON - USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. - 0x1 - - - - - LPM_SUP - LPM Supported: - 11 - 1 - read-write - - - NO - LPM not supported. - 0 - - - YES - LPM supported. - 0x1 - - - - - INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP - 12 - 1 - read-write - - - DISABLED - Only acknowledged packets generate an interrupt - 0 - - - ENABLED - Both acknowledged and NAKed packets generate interrupts. - 0x1 - - - - - INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP - 13 - 1 - read-write - - - DISABLED - Only acknowledged packets generate an interrupt - 0 - - - ENABLED - Both acknowledged and NAKed packets generate interrupts. - 0x1 - - - - - INTONNAK_CO - Interrupt on NAK for control OUT EP - 14 - 1 - read-write - - - DISABLED - Only acknowledged packets generate an interrupt - 0 - - - ENABLED - Both acknowledged and NAKed packets generate interrupts. - 0x1 - - - - - INTONNAK_CI - Interrupt on NAK for control IN EP - 15 - 1 - read-write - - - DISABLED - Only acknowledged packets generate an interrupt - 0 - - - ENABLED - Both acknowledged and NAKed packets generate interrupts. - 0x1 - - - - - DCON - Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VBUSDEBOUNCED bit is one. - 16 - 1 - read-write - - - DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect. - 17 - 1 - read-write - - - LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one. - 19 - 1 - read-write - - - LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction. - 20 - 1 - read-only - - - DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. - 24 - 1 - read-write - - - DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on its upstream port. The bit is reset by writing a one to it. - 25 - 1 - read-write - - - DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it. - 26 - 1 - read-write - - - VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. - 28 - 1 - read-only - - - - - INFO - USB Info register - 0x4 - 32 - read-write - 0 - 0x7FFF - - - FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device. - 0 - 11 - read-only - - - ERR_CODE - The error code which last occurred: - 11 - 4 - read-write - - - NO_ERROR - No error - 0 - - - PID_ENCODING_ERROR - PID encoding error - 0x1 - - - PID_UNKNOWN - PID unknown - 0x2 - - - PACKET_UNEXPECTED - Packet unexpected - 0x3 - - - TOKEN_CRC_ERROR - Token CRC error - 0x4 - - - DATA_CRC_ERROR - Data CRC error - 0x5 - - - TIMEOUT - Time out - 0x6 - - - BABBLE - Babble - 0x7 - - - TRUNCATED_EOP - Truncated EOP - 0x8 - - - SENT_RECEIVED_NAK - Sent/Received NAK - 0x9 - - - SENT_STALL - Sent Stall - 0xA - - - OVERRUN - Overrun - 0xB - - - SENT_EMPTY_PACKET - Sent empty packet - 0xC - - - BITSTUFF_ERROR - Bitstuff error - 0xD - - - SYNC_ERROR - Sync error - 0xE - - - WRONG_DATA_TOGGLE - Wrong data toggle - 0xF - - - - - MINREV - Minor Revision. - 16 - 8 - read-only - - - MAJREV - Major Revision. - 24 - 8 - read-only - - - - - EPLISTSTART - USB EP Command/Status List start address - 0x8 - 32 - read-write - 0 - 0xFFFFFF00 - - - EP_LIST - Start address of the USB EP Command/Status List. - 8 - 24 - read-write - - - - - DATABUFSTART - USB Data buffer start address - 0xC - 32 - read-write - 0 - 0xFFC00000 - - - DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located. - 22 - 10 - read-write - - - - - LPM - USB Link Power Management register - 0x10 - 32 - read-write - 0 - 0x1FF - - - HIRD_HW - Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token - 0 - 4 - read-only - - - HIRD_SW - Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. - 4 - 4 - read-write - - - DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1. - 8 - 1 - read-write - - - - - EPSKIP - USB Endpoint skip - 0x14 - 32 - read-write - 0 - 0x3FFFFFFF - - - SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. - 0 - 10 - read-write - - - - - EPINUSE - USB Endpoint Buffer in use - 0x18 - 32 - read-write - 0 - 0x3FC - - - BUF - Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 0. 1: HW is accessing buffer 1. - 2 - 8 - read-write - - - - - EPBUFCFG - USB Endpoint Buffer Configuration register - 0x1C - 32 - read-write - 0 - 0x3FC - - - BUF_SB - Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer. - 2 - 8 - read-write - - - - - INTSTAT - USB interrupt status register - 0x20 - 32 - read-write - 0 - 0xC00003FF - - - EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it. - 0 - 1 - read-write - - - EP0IN - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it. - 1 - 1 - read-write - - - EP1OUT - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it. - 2 - 1 - read-write - - - EP1IN - Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it. - 3 - 1 - read-write - - - EP2OUT - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it. - 4 - 1 - read-write - - - EP2IN - Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it. - 5 - 1 - read-write - - - EP3OUT - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it. - 6 - 1 - read-write - - - EP3IN - Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it. - 7 - 1 - read-write - - - EP4OUT - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it. - 8 - 1 - read-write - - - EP4IN - Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it. - 9 - 1 - read-write - - - FRAME_INT - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it. - 30 - 1 - read-write - - - DEV_INT - Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it. - 31 - 1 - read-write - - - - - INTEN - USB interrupt enable register - 0x24 - 32 - read-write - 0 - 0xC00003FF - - - EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. - 0 - 10 - read-write - - - FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. - 30 - 1 - read-write - - - DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. - 31 - 1 - read-write - - - - - INTSETSTAT - USB set interrupt status register - 0x28 - 32 - read-write - 0 - 0xC00003FF - - - EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. - 0 - 10 - read-write - - - FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. - 30 - 1 - read-write - - - DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. - 31 - 1 - read-write - - - - - EPTOGGLE - USB Endpoint toggle register - 0x34 - 32 - read-write - 0 - 0x3FF - - - TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. - 0 - 10 - read-write - - - - - - - SCT0 - SCTimer/PWM (SCT) - SCT - 0x40085000 - - 0 - 0x550 - registers - - - SCT0 - 12 - - - - CONFIG - SCT configuration register - 0 - 32 - read-write - 0x1E00 - 0x61FFF - - - UNIFY - SCT operation - 0 - 1 - read-write - - - DUAL_COUNTER - The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. - 0 - - - UNIFIED_COUNTER - The SCT operates as a unified 32-bit counter. - 0x1 - - - - - CLKMODE - SCT clock mode - 1 - 2 - read-write - - - SYSTEM_CLOCK_MODE - System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. - 0 - - - SAMPLED_SYSTEM_CLOCK_MODE - Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode. - 0x1 - - - SCT_INPUT_CLOCK_MODE - SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. - 0x2 - - - ASYNCHRONOUS_MODE - Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock. - 0x3 - - - - - CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register. - 3 - 4 - read-write - - - INPUT_0_RISING_EDGES - Rising edges on input 0. - 0 - - - INPUT_0_FALLING_EDGE - Falling edges on input 0. - 0x1 - - - INPUT_1_RISING_EDGES - Rising edges on input 1. - 0x2 - - - INPUT_1_FALLING_EDGE - Falling edges on input 1. - 0x3 - - - INPUT_2_RISING_EDGES - Rising edges on input 2. - 0x4 - - - INPUT_2_FALLING_EDGE - Falling edges on input 2. - 0x5 - - - INPUT_3_RISING_EDGES - Rising edges on input 3. - 0x6 - - - INPUT_3_FALLING_EDGE - Falling edges on input 3. - 0x7 - - - INPUT_4_RISING_EDGES - Rising edges on input 4. - 0x8 - - - INPUT_4_FALLING_EDGE - Falling edges on input 4. - 0x9 - - - INPUT_5_RISING_EDGES - Rising edges on input 5. - 0xA - - - INPUT_5_FALLING_EDGE - Falling edges on input 5. - 0xB - - - INPUT_6_RISING_EDGES - Rising edges on input 6. - 0xC - - - INPUT_6_FALLING_EDGE - Falling edges on input 6. - 0xD - - - INPUT_7_RISING_EDGES - Rising edges on input 7. - 0xE - - - INPUT_7_FALLING_EDGE - Falling edges on input 7. - 0xF - - - - - NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. - 7 - 1 - read-write - - - NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. - 8 - 1 - read-write - - - INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field. - 9 - 4 - read-write - - - AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. - 17 - 1 - read-write - - - AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. - 18 - 1 - read-write - - - - - CTRL - SCT control register - 0x4 - 32 - read-write - 0x40004 - 0x1FFF1FFF - - - DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. - 0 - 1 - read-write - - - STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes. - 1 - 1 - read-write - - - HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset. - 2 - 1 - read-write - - - CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. - 3 - 1 - read-write - - - BIDIR_L - L or unified counter direction select - 4 - 1 - read-write - - - UP - Up. The counter counts up to a limit condition, then is cleared to zero. - 0 - - - UP_DOWN - Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. - 0x1 - - - - - PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - 5 - 8 - read-write - - - DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. - 16 - 1 - read-write - - - STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. - 17 - 1 - read-write - - - HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset. - 18 - 1 - read-write - - - CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. - 19 - 1 - read-write - - - BIDIR_H - Direction select - 20 - 1 - read-write - - - UP - The H counter counts up to its limit condition, then is cleared to zero. - 0 - - - UP_DOWN - The H counter counts up to its limit, then counts down to a limit condition or to 0. - 0x1 - - - - - PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - 21 - 8 - read-write - - - - - LIMIT - SCT limit event select register - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - 16 - 16 - read-write - - - - - HALT - SCT halt event select register - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - 16 - 16 - read-write - - - - - STOP - SCT stop event select register - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - 16 - 16 - read-write - - - - - START - SCT start event select register - 0x14 - 32 - read-write - 0 - 0xFFFFFFFF - - - STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - 16 - 16 - read-write - - - - - COUNT - SCT counter register - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter. - 0 - 16 - read-write - - - CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter. - 16 - 16 - read-write - - - - - STATE - SCT state register - 0x44 - 32 - read-write - 0 - 0x1F001F - - - STATE_L - State variable. - 0 - 5 - read-write - - - STATE_H - State variable. - 16 - 5 - read-write - - - - - INPUT - SCT input register - 0x48 - 32 - read-only - 0 - 0xFFFFFFFF - - - AIN0 - Input 0 state. Input 0 state on the last SCT clock edge. - 0 - 1 - read-only - - - AIN1 - Input 1 state. Input 1 state on the last SCT clock edge. - 1 - 1 - read-only - - - AIN2 - Input 2 state. Input 2 state on the last SCT clock edge. - 2 - 1 - read-only - - - AIN3 - Input 3 state. Input 3 state on the last SCT clock edge. - 3 - 1 - read-only - - - AIN4 - Input 4 state. Input 4 state on the last SCT clock edge. - 4 - 1 - read-only - - - AIN5 - Input 5 state. Input 5 state on the last SCT clock edge. - 5 - 1 - read-only - - - AIN6 - Input 6 state. Input 6 state on the last SCT clock edge. - 6 - 1 - read-only - - - AIN7 - Input 7 state. Input 7 state on the last SCT clock edge. - 7 - 1 - read-only - - - AIN8 - Input 8 state. Input 8 state on the last SCT clock edge. - 8 - 1 - read-only - - - AIN9 - Input 9 state. Input 9 state on the last SCT clock edge. - 9 - 1 - read-only - - - AIN10 - Input 10 state. Input 10 state on the last SCT clock edge. - 10 - 1 - read-only - - - AIN11 - Input 11 state. Input 11 state on the last SCT clock edge. - 11 - 1 - read-only - - - AIN12 - Input 12 state. Input 12 state on the last SCT clock edge. - 12 - 1 - read-only - - - AIN13 - Input 13 state. Input 13 state on the last SCT clock edge. - 13 - 1 - read-only - - - AIN14 - Input 14 state. Input 14 state on the last SCT clock edge. - 14 - 1 - read-only - - - AIN15 - Input 15 state. Input 15 state on the last SCT clock edge. - 15 - 1 - read-only - - - SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC. - 16 - 1 - read-only - - - SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC. - 17 - 1 - read-only - - - SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC. - 18 - 1 - read-only - - - SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC. - 19 - 1 - read-only - - - SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC. - 20 - 1 - read-only - - - SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC. - 21 - 1 - read-only - - - SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC. - 22 - 1 - read-only - - - SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC. - 23 - 1 - read-only - - - SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC. - 24 - 1 - read-only - - - SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC. - 25 - 1 - read-only - - - SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC. - 26 - 1 - read-only - - - SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC. - 27 - 1 - read-only - - - SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC. - 28 - 1 - read-only - - - SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC. - 29 - 1 - read-only - - - SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC. - 30 - 1 - read-only - - - SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC. - 31 - 1 - read-only - - - - - REGMODE - SCT match/capture mode register - 0x4C - 32 - read-write - 0 - 0xFFFFFFFF - - - REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match register. 1 = register operates as capture register. - 0 - 16 - read-write - - - REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match registers. 1 = register operates as capture registers. - 16 - 16 - read-write - - - - - OUTPUT - SCT output register - 0x50 - 32 - read-write - 0 - 0xFFFF - - - OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. - 0 - 16 - read-write - - - - - OUTPUTDIRCTRL - SCT output counter direction control register - 0x54 - 32 - read-write - 0 - 0xFFFFFFFF - - - SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. - 0 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. - 2 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. - 4 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. - 6 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. - 8 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. - 10 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. - 12 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. - 14 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. - 16 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. - 18 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. - 20 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. - 22 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. - 24 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. - 26 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. - 28 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. - 30 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - - - RES - SCT conflict resolution register - 0x58 - 32 - read-write - 0 - 0xFFFFFFFF - - - O0RES - Effect of simultaneous set and clear on output 0. - 0 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR0 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O1RES - Effect of simultaneous set and clear on output 1. - 2 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR1 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O2RES - Effect of simultaneous set and clear on output 2. - 4 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output n (or set based on the SETCLR2 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O3RES - Effect of simultaneous set and clear on output 3. - 6 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR3 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O4RES - Effect of simultaneous set and clear on output 4. - 8 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR4 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O5RES - Effect of simultaneous set and clear on output 5. - 10 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR5 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O6RES - Effect of simultaneous set and clear on output 6. - 12 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR6 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O7RES - Effect of simultaneous set and clear on output 7. - 14 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output n (or set based on the SETCLR7 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O8RES - Effect of simultaneous set and clear on output 8. - 16 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR8 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O9RES - Effect of simultaneous set and clear on output 9. - 18 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR9 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O10RES - Effect of simultaneous set and clear on output 10. - 20 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR10 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O11RES - Effect of simultaneous set and clear on output 11. - 22 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR11 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O12RES - Effect of simultaneous set and clear on output 12. - 24 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR12 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O13RES - Effect of simultaneous set and clear on output 13. - 26 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR13 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O14RES - Effect of simultaneous set and clear on output 14. - 28 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR14 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O15RES - Effect of simultaneous set and clear on output 15. - 30 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR15 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - - - DMAREQ0 - SCT DMA request 0 register - 0x5C - 32 - read-write - 0 - 0xC000FFFF - - - DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. - 30 - 1 - read-write - - - DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. - 31 - 1 - read-write - - - - - DMAREQ1 - SCT DMA request 1 register - 0x60 - 32 - read-write - 0 - 0xC000FFFF - - - DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. - 30 - 1 - read-write - - - DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. - 31 - 1 - read-write - - - - - EVEN - SCT event interrupt enable register - 0xF0 - 32 - read-write - 0 - 0xFFFF - - - IEN - The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - - - EVFLAG - SCT event flag register - 0xF4 - 32 - read-write - 0 - 0xFFFF - - - FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - - - CONEN - SCT conflict interrupt enable register - 0xF8 - 32 - read-write - 0 - 0xFFFF - - - NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. - 0 - 16 - read-write - - - - - CONFLAG - SCT conflict flag register - 0xFC - 32 - read-write - 0 - 0xC000FFFF - - - NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. - 0 - 16 - read-write - - - BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful. - 30 - 1 - read-write - - - BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted. - 31 - 1 - read-write - - - - - CAP0 - SCT capture register of capture channel - CAP_MATCH - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH0 - SCT match value register of match channels - CAP_MATCH - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP1 - SCT capture register of capture channel - CAP_MATCH - 0x104 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH1 - SCT match value register of match channels - CAP_MATCH - 0x104 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP2 - SCT capture register of capture channel - CAP_MATCH - 0x108 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH2 - SCT match value register of match channels - CAP_MATCH - 0x108 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP3 - SCT capture register of capture channel - CAP_MATCH - 0x10C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH3 - SCT match value register of match channels - CAP_MATCH - 0x10C - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP4 - SCT capture register of capture channel - CAP_MATCH - 0x110 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH4 - SCT match value register of match channels - CAP_MATCH - 0x110 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP5 - SCT capture register of capture channel - CAP_MATCH - 0x114 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH5 - SCT match value register of match channels - CAP_MATCH - 0x114 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP6 - SCT capture register of capture channel - CAP_MATCH - 0x118 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH6 - SCT match value register of match channels - CAP_MATCH - 0x118 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP7 - SCT capture register of capture channel - CAP_MATCH - 0x11C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH7 - SCT match value register of match channels - CAP_MATCH - 0x11C - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP8 - SCT capture register of capture channel - CAP_MATCH - 0x120 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH8 - SCT match value register of match channels - CAP_MATCH - 0x120 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP9 - SCT capture register of capture channel - CAP_MATCH - 0x124 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH9 - SCT match value register of match channels - CAP_MATCH - 0x124 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP10 - SCT capture register of capture channel - CAP_MATCH - 0x128 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH10 - SCT match value register of match channels - CAP_MATCH - 0x128 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP11 - SCT capture register of capture channel - CAP_MATCH - 0x12C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH11 - SCT match value register of match channels - CAP_MATCH - 0x12C - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP12 - SCT capture register of capture channel - CAP_MATCH - 0x130 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH12 - SCT match value register of match channels - CAP_MATCH - 0x130 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP13 - SCT capture register of capture channel - CAP_MATCH - 0x134 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH13 - SCT match value register of match channels - CAP_MATCH - 0x134 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP14 - SCT capture register of capture channel - CAP_MATCH - 0x138 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH14 - SCT match value register of match channels - CAP_MATCH - 0x138 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP15 - SCT capture register of capture channel - CAP_MATCH - 0x13C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH15 - SCT match value register of match channels - CAP_MATCH - 0x13C - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAPCTRL0 - SCT capture control register - CAPCTRL_MATCHREL - 0x200 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL0 - SCT match reload value register - CAPCTRL_MATCHREL - 0x200 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL1 - SCT capture control register - CAPCTRL_MATCHREL - 0x204 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL1 - SCT match reload value register - CAPCTRL_MATCHREL - 0x204 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL2 - SCT capture control register - CAPCTRL_MATCHREL - 0x208 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL2 - SCT match reload value register - CAPCTRL_MATCHREL - 0x208 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL3 - SCT capture control register - CAPCTRL_MATCHREL - 0x20C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL3 - SCT match reload value register - CAPCTRL_MATCHREL - 0x20C - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL4 - SCT capture control register - CAPCTRL_MATCHREL - 0x210 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL4 - SCT match reload value register - CAPCTRL_MATCHREL - 0x210 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL5 - SCT capture control register - CAPCTRL_MATCHREL - 0x214 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL5 - SCT match reload value register - CAPCTRL_MATCHREL - 0x214 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL6 - SCT capture control register - CAPCTRL_MATCHREL - 0x218 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL6 - SCT match reload value register - CAPCTRL_MATCHREL - 0x218 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL7 - SCT capture control register - CAPCTRL_MATCHREL - 0x21C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL7 - SCT match reload value register - CAPCTRL_MATCHREL - 0x21C - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL8 - SCT capture control register - CAPCTRL_MATCHREL - 0x220 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL8 - SCT match reload value register - CAPCTRL_MATCHREL - 0x220 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL9 - SCT capture control register - CAPCTRL_MATCHREL - 0x224 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL9 - SCT match reload value register - CAPCTRL_MATCHREL - 0x224 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL10 - SCT capture control register - CAPCTRL_MATCHREL - 0x228 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL10 - SCT match reload value register - CAPCTRL_MATCHREL - 0x228 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL11 - SCT capture control register - CAPCTRL_MATCHREL - 0x22C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL11 - SCT match reload value register - CAPCTRL_MATCHREL - 0x22C - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL12 - SCT capture control register - CAPCTRL_MATCHREL - 0x230 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL12 - SCT match reload value register - CAPCTRL_MATCHREL - 0x230 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL13 - SCT capture control register - CAPCTRL_MATCHREL - 0x234 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL13 - SCT match reload value register - CAPCTRL_MATCHREL - 0x234 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL14 - SCT capture control register - CAPCTRL_MATCHREL - 0x238 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL14 - SCT match reload value register - CAPCTRL_MATCHREL - 0x238 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL15 - SCT capture control register - CAPCTRL_MATCHREL - 0x23C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL15 - SCT match reload value register - CAPCTRL_MATCHREL - 0x23C - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - 16 - 0x8 - EV[%s] - no description available - 0x300 - - EV_STATE - SCT event state register 0 - 0 - 32 - read-write - 0 - 0xFFFF - - - STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT. - 0 - 16 - read-write - - - - - EV_CTRL - SCT event control register 0 - 0x4 - 32 - read-write - 0 - 0x7FFFFF - - - MATCHSEL - Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. - 0 - 4 - read-write - - - HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. - 4 - 1 - read-write - - - L_COUNTER - Selects the L state and the L match register selected by MATCHSEL. - 0 - - - H_COUNTER - Selects the H state and the H match register selected by MATCHSEL. - 0x1 - - - - - OUTSEL - Input/output select - 5 - 1 - read-write - - - INPUT - Selects the inputs selected by IOSEL. - 0 - - - OUTPUT - Selects the outputs selected by IOSEL. - 0x1 - - - - - IOSEL - Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. - 6 - 4 - read-write - - - IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . - 10 - 2 - read-write - - - LOW - LOW - 0 - - - RISE - Rise - 0x1 - - - FALL - Fall - 0x2 - - - HIGH - HIGH - 0x3 - - - - - COMBMODE - Selects how the specified match and I/O condition are used and combined. - 12 - 2 - read-write - - - OR - OR. The event occurs when either the specified match or I/O condition occurs. - 0 - - - MATCH - MATCH. Uses the specified match only. - 0x1 - - - IO - IO. Uses the specified I/O condition only. - 0x2 - - - AND - AND. The event occurs when the specified match and I/O condition occur simultaneously. - 0x3 - - - - - STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. - 14 - 1 - read-write - - - ADD - STATEV value is added into STATE (the carry-out is ignored). - 0 - - - LOAD - STATEV value is loaded into STATE. - 0x1 - - - - - STATEV - This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. - 15 - 5 - read-write - - - MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. - 20 - 1 - read-write - - - DIRECTION - Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. - 21 - 2 - read-write - - - DIRECTION_INDEPENDENT - Direction independent. This event is triggered regardless of the count direction. - 0 - - - COUNTING_UP - Counting up. This event is triggered only during up-counting when BIDIR = 1. - 0x1 - - - COUNTING_DOWN - Counting down. This event is triggered only during down-counting when BIDIR = 1. - 0x2 - - - - - - - - 10 - 0x8 - OUT[%s] - no description available - 0x500 - - OUT_SET - SCT output 0 set register - 0 - 32 - read-write - 0 - 0xFFFF - - - SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. - 0 - 16 - read-write - - - - - OUT_CLR - SCT output 0 clear register - 0x4 - 32 - read-write - 0 - 0xFFFF - - - CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. - 0 - 16 - read-write - - - - - - - - FLEXCOMM0 - Flexcomm serial communication - FLEXCOMM - FLEXCOMM - 0x40086000 - - 0 - 0x1000 - registers - - - FLEXCOMM0 - 14 - - - - PSELID - Peripheral Select and Flexcomm ID register. - 0xFF8 - 32 - read-write - 0x101000 - 0xFFFFF0FF - - - PERSEL - Peripheral Select. This field is writable by software. - 0 - 3 - read-write - - - NO_PERIPH_SELECTED - No peripheral selected. - 0 - - - USART - USART function selected. - 0x1 - - - SPI - SPI function selected. - 0x2 - - - I2C - I2C function selected. - 0x3 - - - I2S_TRANSMIT - I2S transmit function selected. - 0x4 - - - I2S_RECEIVE - I2S receive function selected. - 0x5 - - - - - LOCK - Lock the peripheral select. This field is writable by software. - 3 - 1 - read-write - - - UNLOCKED - Peripheral select can be changed by software. - 0 - - - LOCKED - Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. - 0x1 - - - - - USARTPRESENT - USART present indicator. This field is Read-only. - 4 - 1 - read-only - - - NOT_PRESENT - This Flexcomm does not include the USART function. - 0 - - - PRESENT - This Flexcomm includes the USART function. - 0x1 - - - - - SPIPRESENT - SPI present indicator. This field is Read-only. - 5 - 1 - read-only - - - NOT_PRESENT - This Flexcomm does not include the SPI function. - 0 - - - PRESENT - This Flexcomm includes the SPI function. - 0x1 - - - - - I2CPRESENT - I2C present indicator. This field is Read-only. - 6 - 1 - read-only - - - NOT_PRESENT - This Flexcomm does not include the I2C function. - 0 - - - PRESENT - This Flexcomm includes the I2C function. - 0x1 - - - - - I2SPRESENT - I 2S present indicator. This field is Read-only. - 7 - 1 - read-only - - - NOT_PRESENT - This Flexcomm does not include the I2S function. - 0 - - - PRESENT - This Flexcomm includes the I2S function. - 0x1 - - - - - ID - Flexcomm ID. - 12 - 20 - read-only - - - - - PID - Peripheral identification register. - 0xFFC - 32 - read-only - 0 - 0xFFFFFFFF - - - APERTURE - size aperture for the register port on the bus (APB or AHB). - 0 - 8 - read-only - - - MINOR_REV - Minor revision of module implementation. - 8 - 4 - read-only - - - MAJOR_REV - Major revision of module implementation. - 12 - 4 - read-only - - - ID - Module identifier for the selected function. - 16 - 16 - read-only - - - - - - - FLEXCOMM1 - Flexcomm serial communication - FLEXCOMM - 0x40087000 - - 0 - 0x1000 - registers - - - FLEXCOMM1 - 15 - - - - FLEXCOMM2 - Flexcomm serial communication - FLEXCOMM - 0x40088000 - - 0 - 0x1000 - registers - - - FLEXCOMM2 - 16 - - - - FLEXCOMM3 - Flexcomm serial communication - FLEXCOMM - 0x40089000 - - 0 - 0x1000 - registers - - - FLEXCOMM3 - 17 - - - - FLEXCOMM4 - Flexcomm serial communication - FLEXCOMM - 0x4008A000 - - 0 - 0x1000 - registers - - - FLEXCOMM4 - 18 - - - - FLEXCOMM5 - Flexcomm serial communication - FLEXCOMM - 0x40096000 - - 0 - 0x1000 - registers - - - FLEXCOMM5 - 19 - - - - FLEXCOMM6 - Flexcomm serial communication - FLEXCOMM - 0x40097000 - - 0 - 0x1000 - registers - - - FLEXCOMM6 - 20 - - - - FLEXCOMM7 - Flexcomm serial communication - FLEXCOMM - 0x40098000 - - 0 - 0x1000 - registers - - - FLEXCOMM7 - 21 - - - - FLEXCOMM8 - Flexcomm serial communication - FLEXCOMM - 0x4009F000 - - 0 - 0x1000 - registers - - - FLEXCOMM8 - 59 - - - - I2C0 - I2C-bus interfaces - FLEXCOMM0 - I2C - I2C - 0x40086000 - - 0 - 0x1000 - registers - - - FLEXCOMM0 - 14 - - - - CFG - Configuration for shared functions. - 0x800 - 32 - read-write - 0 - 0x3F - - - MSTEN - Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset. - 0 - 1 - read-write - - - DISABLED - Disabled. The I2C Master function is disabled. - 0 - - - ENABLED - Enabled. The I2C Master function is enabled. - 0x1 - - - - - SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. - 1 - 1 - read-write - - - DISABLED - Disabled. The I2C slave function is disabled. - 0 - - - ENABLED - Enabled. The I2C slave function is enabled. - 0x1 - - - - - MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset. - 2 - 1 - read-write - - - DISABLED - Disabled. The I2C Monitor function is disabled. - 0 - - - ENABLED - Enabled. The I2C Monitor function is enabled. - 0x1 - - - - - TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. - 3 - 1 - read-write - - - DISABLED - Disabled. Time-out function is disabled. - 0 - - - ENABLED - Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system. - 0x1 - - - - - MONCLKSTR - Monitor function Clock Stretching. - 4 - 1 - read-write - - - DISABLED - Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical. - 0 - - - ENABLED - Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function. - 0x1 - - - - - HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor. - 5 - 1 - read-write - - - FAST_MODE_PLUS - Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin, - 0 - - - HIGH_SPEED - High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information. - 0x1 - - - - - - - STAT - Status register for Master, Slave, and Monitor functions. - 0x804 - 32 - read-write - 0x801 - 0x30FFF5F - - - MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt. - 0 - 1 - read-only - - - IN_PROGRESS - In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. - 0 - - - PENDING - Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit. - 0x1 - - - - - MSTSTATE - Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses. - 1 - 3 - read-only - - - IDLE - Idle. The Master function is available to be used for a new transaction. - 0 - - - RECEIVE_READY - Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. - 0x1 - - - TRANSMIT_READY - Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. - 0x2 - - - NACK_ADDRESS - NACK Address. Slave NACKed address. - 0x3 - - - NACK_DATA - NACK Data. Slave NACKed transmitted data. - 0x4 - - - - - MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - 4 - 1 - read-write - - - NO_LOSS - No Arbitration Loss has occurred. - 0 - - - ARBITRATION_LOSS - Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. - 0x1 - - - - - MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - 6 - 1 - read-write - - - NO_ERROR - No Start/Stop Error has occurred. - 0 - - - ERROR - The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled. - 0x1 - - - - - SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched. - 8 - 1 - read-only - - - IN_PROGRESS - In progress. The Slave function does not currently need service. - 0 - - - PENDING - Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. - 0x1 - - - - - SLVSTATE - Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes. - 9 - 2 - read-only - - - SLAVE_ADDRESS - Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. - 0 - - - SLAVE_RECEIVE - Slave receive. Received data is available (Slave Receiver mode). - 0x1 - - - SLAVE_TRANSMIT - Slave transmit. Data can be transmitted (Slave Transmitter mode). - 0x2 - - - - - SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. - 11 - 1 - read-only - - - STRETCHING - Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. - 0 - - - NOT_STRETCHING - Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time. - 0x1 - - - - - SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. - 12 - 2 - read-only - - - ADDRESS0 - Address 0. Slave address 0 was matched. - 0 - - - ADDRESS1 - Address 1. Slave address 1 was matched. - 0x1 - - - ADDRESS2 - Address 2. Slave address 2 was matched. - 0x2 - - - ADDRESS3 - Address 3. Slave address 3 was matched. - 0x3 - - - - - SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data. - 14 - 1 - read-only - - - NOT_SELECTED - Not selected. The Slave function is not currently selected. - 0 - - - SELECTED - Selected. The Slave function is currently selected. - 0x1 - - - - - SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. - 15 - 1 - read-write - - - NOT_DESELECTED - Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag. - 0 - - - DESELECTED - Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. - 0x1 - - - - - MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. - 16 - 1 - read-only - - - NO_DATA - No data. The Monitor function does not currently have data available. - 0 - - - DATA_WAITING - Data waiting. The Monitor function has data waiting to be read. - 0x1 - - - - - MONOV - Monitor Overflow flag. - 17 - 1 - read-write - - - NO_OVERRUN - No overrun. Monitor data has not overrun. - 0 - - - OVERRUN - Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. - 0x1 - - - - - MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. - 18 - 1 - read-only - - - INACTIVE - Inactive. The Monitor function considers the I2C bus to be inactive. - 0 - - - ACTIVE - Active. The Monitor function considers the I2C bus to be active. - 0x1 - - - - - MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit. - 19 - 1 - read-write - - - NOT_IDLE - Not idle. The I2C bus is not idle, or this flag has been cleared by software. - 0 - - - IDLE - Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. - 0x1 - - - - - EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle. - 24 - 1 - read-write - - - NO_TIMEOUT - No time-out. I2C bus events have not caused a time-out. - 0 - - - EVEN_TIMEOUT - Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. - 0x1 - - - - - SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. - 25 - 1 - read-write - - - NO_TIMEOUT - No time-out. SCL low time has not caused a time-out. - 0 - - - TIMEOUT - Time-out. SCL low time has caused a time-out. - 0x1 - - - - - - - INTENSET - Interrupt Enable Set and read register. - 0x808 - 32 - read-write - 0 - 0x30B8951 - - - MSTPENDINGEN - Master Pending interrupt Enable. - 0 - 1 - read-write - - - DISABLED - Disabled. The MstPending interrupt is disabled. - 0 - - - ENABLED - Enabled. The MstPending interrupt is enabled. - 0x1 - - - - - MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. - 4 - 1 - read-write - - - DISABLED - Disabled. The MstArbLoss interrupt is disabled. - 0 - - - ENABLED - Enabled. The MstArbLoss interrupt is enabled. - 0x1 - - - - - MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. - 6 - 1 - read-write - - - DISABLED - Disabled. The MstStStpErr interrupt is disabled. - 0 - - - ENABLED - Enabled. The MstStStpErr interrupt is enabled. - 0x1 - - - - - SLVPENDINGEN - Slave Pending interrupt Enable. - 8 - 1 - read-write - - - DISABLED - Disabled. The SlvPending interrupt is disabled. - 0 - - - ENABLED - Enabled. The SlvPending interrupt is enabled. - 0x1 - - - - - SLVNOTSTREN - Slave Not Stretching interrupt Enable. - 11 - 1 - read-write - - - DISABLED - Disabled. The SlvNotStr interrupt is disabled. - 0 - - - ENABLED - Enabled. The SlvNotStr interrupt is enabled. - 0x1 - - - - - SLVDESELEN - Slave Deselect interrupt Enable. - 15 - 1 - read-write - - - DISABLED - Disabled. The SlvDeSel interrupt is disabled. - 0 - - - ENABLED - Enabled. The SlvDeSel interrupt is enabled. - 0x1 - - - - - MONRDYEN - Monitor data Ready interrupt Enable. - 16 - 1 - read-write - - - DISABLED - Disabled. The MonRdy interrupt is disabled. - 0 - - - ENABLED - Enabled. The MonRdy interrupt is enabled. - 0x1 - - - - - MONOVEN - Monitor Overrun interrupt Enable. - 17 - 1 - read-write - - - DISABLED - Disabled. The MonOv interrupt is disabled. - 0 - - - ENABLED - Enabled. The MonOv interrupt is enabled. - 0x1 - - - - - MONIDLEEN - Monitor Idle interrupt Enable. - 19 - 1 - read-write - - - DISABLED - Disabled. The MonIdle interrupt is disabled. - 0 - - - ENABLED - Enabled. The MonIdle interrupt is enabled. - 0x1 - - - - - EVENTTIMEOUTEN - Event time-out interrupt Enable. - 24 - 1 - read-write - - - DISABLED - Disabled. The Event time-out interrupt is disabled. - 0 - - - ENABLED - Enabled. The Event time-out interrupt is enabled. - 0x1 - - - - - SCLTIMEOUTEN - SCL time-out interrupt Enable. - 25 - 1 - read-write - - - DISABLED - Disabled. The SCL time-out interrupt is disabled. - 0 - - - ENABLED - Enabled. The SCL time-out interrupt is enabled. - 0x1 - - - - - - - INTENCLR - Interrupt Enable Clear register. - 0x80C - 32 - write-only - 0 - 0 - - - MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented. - 0 - 1 - write-only - - - MSTARBLOSSCLR - Master Arbitration Loss interrupt clear. - 4 - 1 - write-only - - - MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear. - 6 - 1 - write-only - - - SLVPENDINGCLR - Slave Pending interrupt clear. - 8 - 1 - write-only - - - SLVNOTSTRCLR - Slave Not Stretching interrupt clear. - 11 - 1 - write-only - - - SLVDESELCLR - Slave Deselect interrupt clear. - 15 - 1 - write-only - - - MONRDYCLR - Monitor data Ready interrupt clear. - 16 - 1 - write-only - - - MONOVCLR - Monitor Overrun interrupt clear. - 17 - 1 - write-only - - - MONIDLECLR - Monitor Idle interrupt clear. - 19 - 1 - write-only - - - EVENTTIMEOUTCLR - Event time-out interrupt clear. - 24 - 1 - write-only - - - SCLTIMEOUTCLR - SCL time-out interrupt clear. - 25 - 1 - write-only - - - - - TIMEOUT - Time-out value register. - 0x810 - 32 - read-write - 0xFFFF - 0xFFFF - - - TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. - 0 - 4 - read-write - - - TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock. - 4 - 12 - read-write - - - - - CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. - 0x814 - 32 - read-write - 0 - 0xFFFF - - - DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use. - 0 - 16 - read-write - - - - - INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. - 0x818 - 32 - read-only - 0x801 - 0x30B8951 - - - MSTPENDING - Master Pending. - 0 - 1 - read-only - - - MSTARBLOSS - Master Arbitration Loss flag. - 4 - 1 - read-only - - - MSTSTSTPERR - Master Start/Stop Error flag. - 6 - 1 - read-only - - - SLVPENDING - Slave Pending. - 8 - 1 - read-only - - - SLVNOTSTR - Slave Not Stretching status. - 11 - 1 - read-only - - - SLVDESEL - Slave Deselected flag. - 15 - 1 - read-only - - - MONRDY - Monitor Ready. - 16 - 1 - read-only - - - MONOV - Monitor Overflow flag. - 17 - 1 - read-only - - - MONIDLE - Monitor Idle flag. - 19 - 1 - read-only - - - EVENTTIMEOUT - Event time-out Interrupt flag. - 24 - 1 - read-only - - - SCLTIMEOUT - SCL time-out Interrupt flag. - 25 - 1 - read-only - - - - - MSTCTL - Master control register. - 0x820 - 32 - read-write - 0 - 0xE - - - MSTCONTINUE - Master Continue. This bit is write-only. - 0 - 1 - write-only - - - NO_EFFECT - No effect. - 0 - - - CONTINUE - Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. - 0x1 - - - - - MSTSTART - Master Start control. This bit is write-only. - 1 - 1 - read-write - - - NO_EFFECT - No effect. - 0 - - - START - Start. A Start will be generated on the I2C bus at the next allowed time. - 0x1 - - - - - MSTSTOP - Master Stop control. This bit is write-only. - 2 - 1 - read-write - - - NO_EFFECT - No effect. - 0 - - - STOP - Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode). - 0x1 - - - - - MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write. - 3 - 1 - read-write - - - DISABLED - Disable. No DMA requests are generated for master operation. - 0 - - - ENABLED - Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. - 0x1 - - - - - - - MSTTIME - Master timing configuration. - 0x824 - 32 - read-write - 0x77 - 0x77 - - - MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. - 0 - 3 - read-write - - - CLOCKS_2 - 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. - 0 - - - CLOCKS_3 - 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. - 0x1 - - - CLOCKS_4 - 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. - 0x2 - - - CLOCKS_5 - 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. - 0x3 - - - CLOCKS_6 - 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. - 0x4 - - - CLOCKS_7 - 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. - 0x5 - - - CLOCKS_8 - 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. - 0x6 - - - CLOCKS_9 - 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. - 0x7 - - - - - MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. - 4 - 3 - read-write - - - CLOCKS_2 - 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. - 0 - - - CLOCKS_3 - 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . - 0x1 - - - CLOCKS_4 - 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. - 0x2 - - - CLOCKS_5 - 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. - 0x3 - - - CLOCKS_6 - 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. - 0x4 - - - CLOCKS_7 - 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. - 0x5 - - - CLOCKS_8 - 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. - 0x6 - - - CLOCKS_9 - 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. - 0x7 - - - - - - - MSTDAT - Combined Master receiver and transmitter data register. - 0x828 - 32 - read-write - 0 - 0xFF - - - DATA - Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function. - 0 - 8 - read-write - - - - - SLVCTL - Slave control register. - 0x840 - 32 - read-write - 0 - 0x30B - - - SLVCONTINUE - Slave Continue. - 0 - 1 - read-write - - - NO_EFFECT - No effect. - 0 - - - CONTINUE - Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1. - 0x1 - - - - - SLVNACK - Slave NACK. - 1 - 1 - read-write - - - NO_EFFECT - No effect. - 0 - - - NACK - NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). - 0x1 - - - - - SLVDMA - Slave DMA enable. - 3 - 1 - read-write - - - DISABLED - Disabled. No DMA requests are issued for Slave mode operation. - 0 - - - ENABLED - Enabled. DMA requests are issued for I2C slave data transmission and reception. - 0x1 - - - - - AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt. - 8 - 1 - read-write - - - NORMAL - Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored). - 0 - - - AUTOMATIC_ACK - A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. - 0x1 - - - - - AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation. - 9 - 1 - read-write - - - I2C_WRITE - The expected next operation in Automatic Mode is an I2C write. - 0 - - - I2C_READ - The expected next operation in Automatic Mode is an I2C read. - 0x1 - - - - - - - SLVDAT - Combined Slave receiver and transmitter data register. - 0x844 - 32 - read-write - 0 - 0xFF - - - DATA - Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function. - 0 - 8 - read-write - - - - - SLVADR0 - Slave address register. - 0x848 - 32 - read-write - 0x1 - 0xFF - - - SADISABLE - Slave Address n Disable. - 0 - 1 - read-write - - - ENABLED - Enabled. Slave Address n is enabled. - 0 - - - DISABLED - Ignored Slave Address n is ignored. - 0x1 - - - - - SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. - 1 - 7 - read-write - - - AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations. - 15 - 1 - read-write - - - NORMAL - Normal operation, matching I2C addresses are not ignored. - 0 - - - AUTOMATIC - Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction. - 0x1 - - - - - - - SLVADR1 - Slave address register. - 0x84C - 32 - read-write - 0x1 - 0xFF - - - SADISABLE - Slave Address n Disable. - 0 - 1 - read-write - - - ENABLED - Enabled. Slave Address n is enabled. - 0 - - - DISABLED - Ignored Slave Address n is ignored. - 0x1 - - - - - SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. - 1 - 7 - read-write - - - - - SLVADR2 - Slave address register. - 0x850 - 32 - read-write - 0x1 - 0xFF - - - SADISABLE - Slave Address n Disable. - 0 - 1 - read-write - - - ENABLED - Enabled. Slave Address n is enabled. - 0 - - - DISABLED - Ignored Slave Address n is ignored. - 0x1 - - - - - SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. - 1 - 7 - read-write - - - - - SLVADR3 - Slave address register. - 0x854 - 32 - read-write - 0x1 - 0xFF - - - SADISABLE - Slave Address n Disable. - 0 - 1 - read-write - - - ENABLED - Enabled. Slave Address n is enabled. - 0 - - - DISABLED - Ignored Slave Address n is ignored. - 0x1 - - - - - SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. - 1 - 7 - read-write - - - - - SLVQUAL0 - Slave Qualification for address 0. - 0x858 - 32 - read-write - 0 - 0xFF - - - QUALMODE0 - Qualify mode for slave address 0. - 0 - 1 - read-write - - - MASK - Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. - 0 - - - EXTEND - Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. - 0x1 - - - - - SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). - 1 - 7 - read-write - - - - - MONRXDAT - Monitor receiver data register. - 0x880 - 32 - read-only - 0 - 0x7FF - - - MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. - 0 - 8 - read-only - - - MONSTART - Monitor Received Start. - 8 - 1 - read-only - - - NO_START_DETECTED - No start detected. The Monitor function has not detected a Start event on the I2C bus. - 0 - - - START_DETECTED - Start detected. The Monitor function has detected a Start event on the I2C bus. - 0x1 - - - - - MONRESTART - Monitor Received Repeated Start. - 9 - 1 - read-only - - - NOT_DETECTED - No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. - 0 - - - DETECTED - Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. - 0x1 - - - - - MONNACK - Monitor Received NACK. - 10 - 1 - read-only - - - ACKNOWLEDGED - Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. - 0 - - - NOT_ACKNOWLEDGED - Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. - 0x1 - - - - - - - ID - Peripheral identification register. - 0xFFC - 32 - read-only - 0 - 0xFFFFFFFF - - - APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - 0 - 8 - read-only - - - MINOR_REV - Minor revision of module implementation. - 8 - 4 - read-only - - - MAJOR_REV - Major revision of module implementation. - 12 - 4 - read-only - - - ID - Module identifier for the selected function. - 16 - 16 - read-only - - - - - - - I2C1 - I2C-bus interfaces - FLEXCOMM1 - I2C - 0x40087000 - - 0 - 0x1000 - registers - - - FLEXCOMM1 - 15 - - - - I2C2 - I2C-bus interfaces - FLEXCOMM2 - I2C - 0x40088000 - - 0 - 0x1000 - registers - - - FLEXCOMM2 - 16 - - - - I2C3 - I2C-bus interfaces - FLEXCOMM3 - I2C - 0x40089000 - - 0 - 0x1000 - registers - - - FLEXCOMM3 - 17 - - - - I2C4 - I2C-bus interfaces - FLEXCOMM4 - I2C - 0x4008A000 - - 0 - 0x1000 - registers - - - FLEXCOMM4 - 18 - - - - I2C5 - I2C-bus interfaces - FLEXCOMM5 - I2C - 0x40096000 - - 0 - 0x1000 - registers - - - FLEXCOMM5 - 19 - - - - I2C6 - I2C-bus interfaces - FLEXCOMM6 - I2C - 0x40097000 - - 0 - 0x1000 - registers - - - FLEXCOMM6 - 20 - - - - I2C7 - I2C-bus interfaces - FLEXCOMM7 - I2C - 0x40098000 - - 0 - 0x1000 - registers - - - FLEXCOMM7 - 21 - - - - I2S0 - I2S interface - FLEXCOMM0 - I2S - I2S - 0x40086000 - - 0 - 0x1000 - registers - - - FLEXCOMM0 - 14 - - - - CFG1 - Configuration register 1 for the primary channel pair. - 0xC00 - 32 - read-write - 0 - 0x1F3FFF - - - MAINENABLE - Main enable for I 2S function in this Flexcomm - 0 - 1 - read-write - - - DISABLED - All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags are reset. No other channel pairs can be enabled. - 0 - - - ENABLED - This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. - 0x1 - - - - - DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame. - 1 - 1 - read-write - - - NORMAL - Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. - 0 - - - PAUSE - A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. - 0x1 - - - - - PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. - 2 - 2 - read-write - - - PAIRS_1 - 1 I2S channel pairs in this flexcomm - 0 - - - PAIRS_2 - 2 I2S channel pairs in this flexcomm - 0x1 - - - PAIRS_3 - 3 I2S channel pairs in this flexcomm - 0x2 - - - PAIRS_4 - 4 I2S channel pairs in this flexcomm - 0x3 - - - - - MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. - 4 - 2 - read-write - - - NORMAL_SLAVE_MODE - Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. - 0 - - - WS_SYNC_MASTER - WS synchronized master. WS is received from another master and used to synchronize the generation of SCK, when divided from the Flexcomm function clock. - 0x1 - - - MASTER_USING_SCK - Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. - 0x2 - - - NORMAL_MASTER - Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. - 0x3 - - - - - MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples. - 6 - 2 - read-write - - - CLASSIC_MODE - I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece of left channel data occurring during the first phase, and one pieces of right channel data occurring during the second phase. In this mode, the data region begins one clock after the leading WS edge for the frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. - 0 - - - DSP_MODE_WS_50_DUTYCYCLE - DSP mode where WS has a 50% duty cycle. See remark for mode 0. - 0x1 - - - DSP_MODE_WS_1_CLOCK - DSP mode where WS has a one clock long pulse at the beginning of each data frame. - 0x2 - - - DSP_MODE_WS_1_DATA - DSP mode where WS has a one data slot long pulse at the beginning of each data frame. - 0x3 - - - - - RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. - 8 - 1 - read-write - - - RIGHT_HIGH - The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO bits 31:16 are used for the right channel. - 0 - - - RIGHT_LOW - The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO bits 15:0 are used for the right channel. - 0x1 - - - - - LEFTJUST - Left Justify data. - 9 - 1 - read-write - - - RIGHT_JUSTIFIED - Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data in the stream on the data bus. - 0 - - - LEFT_JUSTIFIED - Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would correspond to left justified data in the stream on the data bus. - 0x1 - - - - - ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers. - 10 - 1 - read-write - - - DUAL_CHANNEL - I2S data for this channel pair is treated as left and right channels. - 0 - - - SINGLE_CHANNEL - I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data for the single channel of data is placed at the clock defined by POSITION. - 0x1 - - - - - SCK_POL - SCK polarity. - 12 - 1 - read-write - - - FALLING_EDGE - Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). - 0 - - - RISING_EDGE - Data is launched on SCK rising edges and sampled on SCK falling edges. - 0x1 - - - - - WS_POL - WS polarity. - 13 - 1 - read-write - - - NOT_INVERTED - Data frames begin at a falling edge of WS (standard for classic I2S). - 0 - - - INVERTED - WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). - 0x1 - - - - - DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the I2S: Determines the size of data transfers between the FIFO and the I2S serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = data is 32 bits in length - 16 - 5 - read-write - - - - - CFG2 - Configuration register 2 for the primary channel pair. - 0xC04 - 32 - read-write - 0 - 0x1FF01FF - - - FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger than DATALEN in order for the WS pulse to be generated correctly. - 0 - 9 - read-write - - - POSITION - Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION defines the location of data in both the left phase and right phase, starting one clock after the WS edge. In other modes, POSITION defines the location of data within the entire frame. ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS phase. 0x002 = data begins at bit position 2 within the frame or WS phase. - 16 - 9 - read-write - - - - - STAT - Status register for the primary channel pair. - 0xC08 - 32 - read-write - 0 - 0xD - - - BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. - 0 - 1 - read-only - - - IDLE - The transmitter/receiver for channel pair is currently idle. - 0 - - - BUSY - The transmitter/receiver for channel pair is currently processing data. - 0x1 - - - - - SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream. - 1 - 1 - write-only - - - NO_ERROR - No error has been recorded. - 0 - - - ERROR - An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. - 0x1 - - - - - LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair. - 2 - 1 - read-only - - - LEFT_CHANNEL - Left channel. - 0 - - - RIGHT_CHANNEL - Right channel. - 0x1 - - - - - DATAPAUSED - Data Paused status flag. Applies to all I2S channels - 3 - 1 - read-only - - - NOT_PAUSED - Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. - 0 - - - PAUSED - A data pause has been requested and is now in force. - 0x1 - - - - - - - DIV - Clock divider, used by all channel pairs. - 0xC1C - 32 - read-write - 0 - 0xFFF - - - DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is divided by 4,096. - 0 - 12 - read-write - - - - - FIFOCFG - FIFO configuration and enable register. - 0xE00 - 32 - read-write - 0 - 0x7F033 - - - ENABLETX - Enable the transmit FIFO. - 0 - 1 - read-write - - - DISABLED - The transmit FIFO is not enabled. - 0 - - - ENABLED - The transmit FIFO is enabled. - 0x1 - - - - - ENABLERX - Enable the receive FIFO. - 1 - 1 - read-write - - - DISABLED - The receive FIFO is not enabled. - 0 - - - ENABLED - The receive FIFO is enabled. - 0x1 - - - - - TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused. - 2 - 1 - read-write - - - LAST_VALUE - If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 bits or less, or when MONO = 1 for this channel pair. - 0 - - - ZERO - If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. - 0x1 - - - - - PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. - 3 - 1 - read-write - - - BIT_24 - 48-bit I2S FIFO entries are handled as all 24-bit values. - 0 - - - BIT_32_16 - 48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. - 0x1 - - - - - SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - 4 - 2 - read-only - - - DMATX - DMA configuration for transmit. - 12 - 1 - read-write - - - DISABLED - DMA is not used for the transmit function. - 0 - - - ENABLED - Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - 0x1 - - - - - DMARX - DMA configuration for receive. - 13 - 1 - read-write - - - DISABLED - DMA is not used for the receive function. - 0 - - - ENABLED - Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - 0x1 - - - - - WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 14 - 1 - read-write - - - DISABLED - Only enabled interrupts will wake up the device form reduced power modes. - 0 - - - ENABLED - A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. - 0x1 - - - - - WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 15 - 1 - read-write - - - DISABLED - Only enabled interrupts will wake up the device form reduced power modes. - 0 - - - ENABLED - A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. - 0x1 - - - - - EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - 16 - 1 - read-write - - - EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - 17 - 1 - read-write - - - - - FIFOSTAT - FIFO status register. - 0xE04 - 32 - read-write - 0x30 - 0x1F1FFB - - - TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. - 0 - 1 - read-write - - - RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - 1 - 1 - read-write - - - PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. - 3 - 1 - read-only - - - TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - 4 - 1 - read-only - - - TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. - 5 - 1 - read-only - - - RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - 6 - 1 - read-only - - - RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. - 7 - 1 - read-only - - - TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. - 8 - 5 - read-only - - - RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. - 16 - 5 - read-only - - - - - FIFOTRIG - FIFO trigger settings for interrupt and DMA request. - 0xE08 - 32 - read-write - 0 - 0xF0F03 - - - TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - 0 - 1 - read-write - - - DISABLED - Transmit FIFO level does not generate a FIFO level trigger. - 0 - - - ENABLED - An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - 0x1 - - - - - RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - 1 - 1 - read-write - - - DISABLED - Receive FIFO level does not generate a FIFO level trigger. - 0 - - - ENABLED - An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - 0x1 - - - - - TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). - 8 - 4 - read-write - - - RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). - 16 - 4 - read-write - - - - - FIFOINTENSET - FIFO interrupt enable set (enable) and read register. - 0xE10 - 32 - read-write - 0 - 0xF - - - TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - 0 - 1 - read-write - - - DISABLED - No interrupt will be generated for a transmit error. - 0 - - - ENABLED - An interrupt will be generated when a transmit error occurs. - 0x1 - - - - - RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - 1 - 1 - read-write - - - DISABLED - No interrupt will be generated for a receive error. - 0 - - - ENABLED - An interrupt will be generated when a receive error occurs. - 0x1 - - - - - TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 2 - 1 - read-write - - - DISABLED - No interrupt will be generated based on the TX FIFO level. - 0 - - - ENABLED - If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. - 0x1 - - - - - RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 3 - 1 - read-write - - - DISABLED - No interrupt will be generated based on the RX FIFO level. - 0 - - - ENABLED - If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. - 0x1 - - - - - - - FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. - 0xE14 - 32 - read-write - 0 - 0xF - - - TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - 0 - 1 - read-write - - - RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - 1 - 1 - read-write - - - TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - 2 - 1 - read-write - - - RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - 3 - 1 - read-write - - - - - FIFOINTSTAT - FIFO interrupt status register. - 0xE18 - 32 - read-only - 0 - 0x1F - - - TXERR - TX FIFO error. - 0 - 1 - read-only - - - RXERR - RX FIFO error. - 1 - 1 - read-only - - - TXLVL - Transmit FIFO level interrupt. - 2 - 1 - read-only - - - RXLVL - Receive FIFO level interrupt. - 3 - 1 - read-only - - - PERINT - Peripheral interrupt. - 4 - 1 - read-only - - - - - FIFOWR - FIFO write data. - 0xE20 - 32 - write-only - 0 - 0 - - - TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details. - 0 - 32 - write-only - - - - - FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. - 0xE24 - 32 - write-only - 0 - 0 - - - TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. - 0 - 24 - write-only - - - - - FIFORD - FIFO read data. - 0xE30 - 32 - read-only - 0 - 0 - - - RXDATA - Received data from the FIFO. The number of bits used depends on configuration details. - 0 - 32 - read-only - - - - - FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. - 0xE34 - 32 - read-only - 0 - 0xFFFFFF - - - RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. - 0 - 24 - read-only - - - - - FIFORDNOPOP - FIFO data read with no FIFO pop. - 0xE40 - 32 - read-only - 0 - 0 - - - RXDATA - Received data from the FIFO. - 0 - 32 - read-only - - - - - FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. - 0xE44 - 32 - read-only - 0 - 0xFFFFFF - - - RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. - 0 - 24 - read-only - - - - - FIFOSIZE - FIFO size register - 0xE48 - 32 - read-write - 0x8 - 0xFFFFFFFF - - - FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - 0 - 5 - read-only - - - - - ID - I2S Module identification - 0xFFC - 32 - read-only - 0xE0900000 - 0xFFFFFFFF - - - APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - 0 - 8 - read-only - - - MINOR_REV - Minor revision of module implementation, starting at 0. - 8 - 4 - read-only - - - MAJOR_REV - Major revision of module implementation, starting at 0. - 12 - 4 - read-only - - - ID - Unique module identifier for this IP block. - 16 - 16 - read-only - - - - - - - I2S1 - I2S interface - FLEXCOMM1 - I2S - 0x40087000 - - 0 - 0x1000 - registers - - - FLEXCOMM1 - 15 - - - - I2S2 - I2S interface - FLEXCOMM2 - I2S - 0x40088000 - - 0 - 0x1000 - registers - - - FLEXCOMM2 - 16 - - - - I2S3 - I2S interface - FLEXCOMM3 - I2S - 0x40089000 - - 0 - 0x1000 - registers - - - FLEXCOMM3 - 17 - - - - I2S4 - I2S interface - FLEXCOMM4 - I2S - 0x4008A000 - - 0 - 0x1000 - registers - - - FLEXCOMM4 - 18 - - - - I2S5 - I2S interface - FLEXCOMM5 - I2S - 0x40096000 - - 0 - 0x1000 - registers - - - FLEXCOMM5 - 19 - - - - I2S6 - I2S interface - FLEXCOMM6 - I2S - 0x40097000 - - 0 - 0x1000 - registers - - - FLEXCOMM6 - 20 - - - - I2S7 - I2S interface - FLEXCOMM7 - I2S - 0x40098000 - - 0 - 0x1000 - registers - - - FLEXCOMM7 - 21 - - - - SPI0 - Serial Peripheral Interfaces (SPI) - FLEXCOMM0 - SPI - SPI - 0x40086000 - - 0 - 0x1000 - registers - - - FLEXCOMM0 - 14 - - - - CFG - SPI Configuration register - 0x400 - 32 - read-write - 0 - 0xFBD - - - ENABLE - SPI enable. - 0 - 1 - read-write - - - DISABLED - Disabled. The SPI is disabled and the internal state machine and counters are reset. - 0 - - - ENABLED - Enabled. The SPI is enabled for operation. - 0x1 - - - - - MASTER - Master mode select. - 2 - 1 - read-write - - - SLAVE_MODE - Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. - 0 - - - MASTER_MODE - Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. - 0x1 - - - - - LSBF - LSB First mode enable. - 3 - 1 - read-write - - - STANDARD - Standard. Data is transmitted and received in standard MSB first order. - 0 - - - REVERSE - Reverse. Data is transmitted and received in reverse order (LSB first). - 0x1 - - - - - CPHA - Clock Phase select. - 4 - 1 - read-write - - - CHANGE - Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge. - 0 - - - CAPTURE - Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge. - 0x1 - - - - - CPOL - Clock Polarity select. - 5 - 1 - read-write - - - LOW - Low. The rest state of the clock (between transfers) is low. - 0 - - - HIGH - High. The rest state of the clock (between transfers) is high. - 0x1 - - - - - LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. - 7 - 1 - read-write - - - DISABLED - Disabled. - 0 - - - ENABLED - Enabled. - 0x1 - - - - - SPOL0 - SSEL0 Polarity select. - 8 - 1 - read-write - - - LOW - Low. The SSEL0 pin is active low. - 0 - - - HIGH - High. The SSEL0 pin is active high. - 0x1 - - - - - SPOL1 - SSEL1 Polarity select. - 9 - 1 - read-write - - - LOW - Low. The SSEL1 pin is active low. - 0 - - - HIGH - High. The SSEL1 pin is active high. - 0x1 - - - - - SPOL2 - SSEL2 Polarity select. - 10 - 1 - read-write - - - LOW - Low. The SSEL2 pin is active low. - 0 - - - HIGH - High. The SSEL2 pin is active high. - 0x1 - - - - - SPOL3 - SSEL3 Polarity select. - 11 - 1 - read-write - - - LOW - Low. The SSEL3 pin is active low. - 0 - - - HIGH - High. The SSEL3 pin is active high. - 0x1 - - - - - - - DLY - SPI Delay register - 0x404 - 32 - read-write - 0 - 0xFFFF - - - PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. - 0 - 4 - read-write - - - POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. - 4 - 4 - read-write - - - FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. - 8 - 4 - read-write - - - TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times. - 12 - 4 - read-write - - - - - STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. - 0x408 - 32 - read-write - 0x100 - 0x1C0 - - - SSA - Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software. - 4 - 1 - write-only - - - SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software. - 5 - 1 - write-only - - - STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition. - 6 - 1 - read-only - - - ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. - 7 - 1 - read-write - - - MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data. - 8 - 1 - read-only - - - - - INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. - 0x40C - 32 - read-write - 0 - 0x130 - - - SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. - 4 - 1 - read-write - - - DISABLED - Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. - 0 - - - ENABLED - Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. - 0x1 - - - - - SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. - 5 - 1 - read-write - - - DISABLED - Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. - 0 - - - ENABLED - Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. - 0x1 - - - - - MSTIDLEEN - Master idle interrupt enable. - 8 - 1 - read-write - - - DISABLED - No interrupt will be generated when the SPI master function is idle. - 0 - - - ENABLED - An interrupt will be generated when the SPI master function is fully idle. - 0x1 - - - - - - - INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. - 0x410 - 32 - write-only - 0 - 0 - - - SSAEN - Writing 1 clears the corresponding bit in the INTENSET register. - 4 - 1 - write-only - - - SSDEN - Writing 1 clears the corresponding bit in the INTENSET register. - 5 - 1 - write-only - - - MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register. - 8 - 1 - write-only - - - - - DIV - SPI clock Divider - 0x424 - 32 - read-write - 0 - 0xFFFF - - - DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536. - 0 - 16 - read-write - - - - - INTSTAT - SPI Interrupt Status - 0x428 - 32 - read-only - 0 - 0x130 - - - SSA - Slave Select Assert. - 4 - 1 - read-only - - - SSD - Slave Select Deassert. - 5 - 1 - read-only - - - MSTIDLE - Master Idle status flag. - 8 - 1 - read-only - - - - - FIFOCFG - FIFO configuration and enable register. - 0xE00 - 32 - read-write - 0 - 0x7F033 - - - ENABLETX - Enable the transmit FIFO. - 0 - 1 - read-write - - - DISABLED - The transmit FIFO is not enabled. - 0 - - - ENABLED - The transmit FIFO is enabled. - 0x1 - - - - - ENABLERX - Enable the receive FIFO. - 1 - 1 - read-write - - - DISABLED - The receive FIFO is not enabled. - 0 - - - ENABLED - The receive FIFO is enabled. - 0x1 - - - - - SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - 4 - 2 - read-only - - - DMATX - DMA configuration for transmit. - 12 - 1 - read-write - - - DISABLED - DMA is not used for the transmit function. - 0 - - - ENABLED - Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - 0x1 - - - - - DMARX - DMA configuration for receive. - 13 - 1 - read-write - - - DISABLED - DMA is not used for the receive function. - 0 - - - ENABLED - Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - 0x1 - - - - - WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 14 - 1 - read-write - - - DISABLED - Only enabled interrupts will wake up the device form reduced power modes. - 0 - - - ENABLED - A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. - 0x1 - - - - - WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 15 - 1 - read-write - - - DISABLED - Only enabled interrupts will wake up the device form reduced power modes. - 0 - - - ENABLED - A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. - 0x1 - - - - - EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - 16 - 1 - read-write - - - EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - 17 - 1 - read-write - - - - - FIFOSTAT - FIFO status register. - 0xE04 - 32 - read-write - 0x30 - 0x1F1FFB - - - TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. - 0 - 1 - read-write - - - RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - 1 - 1 - read-write - - - PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. - 3 - 1 - read-only - - - TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - 4 - 1 - read-only - - - TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. - 5 - 1 - read-only - - - RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - 6 - 1 - read-only - - - RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. - 7 - 1 - read-only - - - TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. - 8 - 5 - read-only - - - RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. - 16 - 5 - read-only - - - - - FIFOTRIG - FIFO trigger settings for interrupt and DMA request. - 0xE08 - 32 - read-write - 0 - 0xF0F03 - - - TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - 0 - 1 - read-write - - - DISABLED - Transmit FIFO level does not generate a FIFO level trigger. - 0 - - - ENABLED - An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - 0x1 - - - - - RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - 1 - 1 - read-write - - - DISABLED - Receive FIFO level does not generate a FIFO level trigger. - 0 - - - ENABLED - An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - 0x1 - - - - - TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). - 8 - 4 - read-write - - - RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). - 16 - 4 - read-write - - - - - FIFOINTENSET - FIFO interrupt enable set (enable) and read register. - 0xE10 - 32 - read-write - 0 - 0xF - - - TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - 0 - 1 - read-write - - - DISABLED - No interrupt will be generated for a transmit error. - 0 - - - ENABLED - An interrupt will be generated when a transmit error occurs. - 0x1 - - - - - RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - 1 - 1 - read-write - - - DISABLED - No interrupt will be generated for a receive error. - 0 - - - ENABLED - An interrupt will be generated when a receive error occurs. - 0x1 - - - - - TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 2 - 1 - read-write - - - DISABLED - No interrupt will be generated based on the TX FIFO level. - 0 - - - ENABLED - If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. - 0x1 - - - - - RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 3 - 1 - read-write - - - DISABLED - No interrupt will be generated based on the RX FIFO level. - 0 - - - ENABLED - If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. - 0x1 - - - - - - - FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. - 0xE14 - 32 - read-write - 0 - 0xF - - - TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - 0 - 1 - read-write - - - RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - 1 - 1 - read-write - - - TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - 2 - 1 - read-write - - - RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - 3 - 1 - read-write - - - - - FIFOINTSTAT - FIFO interrupt status register. - 0xE18 - 32 - read-only - 0 - 0x1F - - - TXERR - TX FIFO error. - 0 - 1 - read-only - - - RXERR - RX FIFO error. - 1 - 1 - read-only - - - TXLVL - Transmit FIFO level interrupt. - 2 - 1 - read-only - - - RXLVL - Receive FIFO level interrupt. - 3 - 1 - read-only - - - PERINT - Peripheral interrupt. - 4 - 1 - read-only - - - - - FIFOWR - FIFO write data. - 0xE20 - 32 - write-only - 0 - 0 - - - TXDATA - Transmit data to the FIFO. - 0 - 16 - write-only - - - TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. - 16 - 1 - write-only - - - ASSERTED - SSEL0 asserted. - 0 - - - NOT_ASSERTED - SSEL0 not asserted. - 0x1 - - - - - TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. - 17 - 1 - write-only - - - ASSERTED - SSEL1 asserted. - 0 - - - NOT_ASSERTED - SSEL1 not asserted. - 0x1 - - - - - TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. - 18 - 1 - write-only - - - ASSERTED - SSEL2 asserted. - 0 - - - NOT_ASSERTED - SSEL2 not asserted. - 0x1 - - - - - TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. - 19 - 1 - write-only - - - ASSERTED - SSEL3 asserted. - 0 - - - NOT_ASSERTED - SSEL3 not asserted. - 0x1 - - - - - EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register. - 20 - 1 - write-only - - - NOT_DEASSERTED - SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. - 0 - - - DEASSERTED - SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. - 0x1 - - - - - EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. - 21 - 1 - write-only - - - NOT_EOF - Data not EOF. This piece of data transmitted is not treated as the end of a frame. - 0 - - - EOF - Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted. - 0x1 - - - - - RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA. - 22 - 1 - write-only - - - READ - Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received. - 0 - - - IGNORE - Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated. - 0x1 - - - - - LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length. - 24 - 4 - write-only - - - - - FIFORD - FIFO read data. - 0xE30 - 32 - read-only - 0 - 0xE1FF - - - RXDATA - Received data from the FIFO. - 0 - 16 - read-only - - - RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. - 16 - 1 - read-only - - - RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. - 17 - 1 - read-only - - - RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. - 18 - 1 - read-only - - - RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. - 19 - 1 - read-only - - - SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bits. - 20 - 1 - read-only - - - - - FIFORDNOPOP - FIFO data read with no FIFO pop. - 0xE40 - 32 - read-only - 0 - 0xE1FF - - - RXDATA - Received data from the FIFO. - 0 - 16 - read-only - - - RXSSEL0_N - Slave Select for receive. - 16 - 1 - read-only - - - RXSSEL1_N - Slave Select for receive. - 17 - 1 - read-only - - - RXSSEL2_N - Slave Select for receive. - 18 - 1 - read-only - - - RXSSEL3_N - Slave Select for receive. - 19 - 1 - read-only - - - SOT - Start of transfer flag. - 20 - 1 - read-only - - - - - FIFOSIZE - FIFO size register - 0xE48 - 32 - read-write - 0x8 - 0xFFFFFFFF - - - FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - 0 - 5 - read-only - - - - - ID - Peripheral identification register. - 0xFFC - 32 - read-only - 0xE0201200 - 0xFFFFFFFF - - - APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - 0 - 8 - read-only - - - MINOR_REV - Minor revision of module implementation. - 8 - 4 - read-only - - - MAJOR_REV - Major revision of module implementation. - 12 - 4 - read-only - - - ID - Module identifier for the selected function. - 16 - 16 - read-only - - - - - - - SPI1 - Serial Peripheral Interfaces (SPI) - FLEXCOMM1 - SPI - 0x40087000 - - 0 - 0x1000 - registers - - - FLEXCOMM1 - 15 - - - - SPI2 - Serial Peripheral Interfaces (SPI) - FLEXCOMM2 - SPI - 0x40088000 - - 0 - 0x1000 - registers - - - FLEXCOMM2 - 16 - - - - SPI3 - Serial Peripheral Interfaces (SPI) - FLEXCOMM3 - SPI - 0x40089000 - - 0 - 0x1000 - registers - - - FLEXCOMM3 - 17 - - - - SPI4 - Serial Peripheral Interfaces (SPI) - FLEXCOMM4 - SPI - 0x4008A000 - - 0 - 0x1000 - registers - - - FLEXCOMM4 - 18 - - - - SPI5 - Serial Peripheral Interfaces (SPI) - FLEXCOMM5 - SPI - 0x40096000 - - 0 - 0x1000 - registers - - - FLEXCOMM5 - 19 - - - - SPI6 - Serial Peripheral Interfaces (SPI) - FLEXCOMM6 - SPI - 0x40097000 - - 0 - 0x1000 - registers - - - FLEXCOMM6 - 20 - - - - SPI7 - Serial Peripheral Interfaces (SPI) - FLEXCOMM7 - SPI - 0x40098000 - - 0 - 0x1000 - registers - - - FLEXCOMM7 - 21 - - - - SPI8 - Serial Peripheral Interfaces (SPI) - FLEXCOMM8 - SPI - 0x4009F000 - - 0 - 0x1000 - registers - - - FLEXCOMM8 - 59 - - - - USART0 - USARTs - FLEXCOMM0 - USART - USART - 0x40086000 - - 0 - 0x1000 - registers - - - FLEXCOMM0 - 14 - - - - CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. - 0 - 32 - read-write - 0 - 0xFDDBFD - - - ENABLE - USART Enable. - 0 - 1 - read-write - - - DISABLED - Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available. - 0 - - - ENABLED - Enabled. The USART is enabled for operation. - 0x1 - - - - - DATALEN - Selects the data size for the USART. - 2 - 2 - read-write - - - BIT_7 - 7 bit Data length. - 0 - - - BIT_8 - 8 bit Data length. - 0x1 - - - BIT_9 - 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. - 0x2 - - - - - PARITYSEL - Selects what type of parity is used by the USART. - 4 - 2 - read-write - - - NO_PARITY - No parity. - 0 - - - EVEN_PARITY - Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. - 0x2 - - - ODD_PARITY - Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. - 0x3 - - - - - STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. - 6 - 1 - read-write - - - BIT_1 - 1 stop bit. - 0 - - - BITS_2 - 2 stop bits. This setting should only be used for asynchronous communication. - 0x1 - - - - - MODE32K - Selects standard or 32 kHz clocking mode. - 7 - 1 - read-write - - - DISABLED - Disabled. USART uses standard clocking. - 0 - - - ENABLED - Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. - 0x1 - - - - - LINMODE - LIN break mode enable. - 8 - 1 - read-write - - - DISABLED - Disabled. Break detect and generate is configured for normal operation. - 0 - - - ENABLED - Enabled. Break detect and generate is configured for LIN bus operation. - 0x1 - - - - - CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. - 9 - 1 - read-write - - - DISABLED - No flow control. The transmitter does not receive any automatic flow control signal. - 0 - - - ENABLED - Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. - 0x1 - - - - - SYNCEN - Selects synchronous or asynchronous operation. - 11 - 1 - read-write - - - ASYNCHRONOUS_MODE - Asynchronous mode. - 0 - - - SYNCHRONOUS_MODE - Synchronous mode. - 0x1 - - - - - CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. - 12 - 1 - read-write - - - FALLING_EDGE - Falling edge. Un_RXD is sampled on the falling edge of SCLK. - 0 - - - RISING_EDGE - Rising edge. Un_RXD is sampled on the rising edge of SCLK. - 0x1 - - - - - SYNCMST - Synchronous mode Master select. - 14 - 1 - read-write - - - SLAVE - Slave. When synchronous mode is enabled, the USART is a slave. - 0 - - - MASTER - Master. When synchronous mode is enabled, the USART is a master. - 0x1 - - - - - LOOP - Selects data loopback mode. - 15 - 1 - read-write - - - NORMAL - Normal operation. - 0 - - - LOOPBACK - Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. - 0x1 - - - - - OETA - Output Enable Turnaround time enable for RS-485 operation. - 18 - 1 - read-write - - - DISABLED - Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. - 0 - - - ENABLED - Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted. - 0x1 - - - - - AUTOADDR - Automatic Address matching enable. - 19 - 1 - read-write - - - DISABLED - Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). - 0 - - - ENABLED - Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match. - 0x1 - - - - - OESEL - Output Enable Select. - 20 - 1 - read-write - - - STANDARD - Standard. The RTS signal is used as the standard flow control function. - 0 - - - RS_485 - RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. - 0x1 - - - - - OEPOL - Output Enable Polarity. - 21 - 1 - read-write - - - LOW - Low. If selected by OESEL, the output enable is active low. - 0 - - - HIGH - High. If selected by OESEL, the output enable is active high. - 0x1 - - - - - RXPOL - Receive data polarity. - 22 - 1 - read-write - - - STANDARD - Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. - 0 - - - INVERTED - Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. - 0x1 - - - - - TXPOL - Transmit data polarity. - 23 - 1 - read-write - - - STANDARD - Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. - 0 - - - INVERTED - Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. - 0x1 - - - - - - - CTL - USART Control register. USART control settings that are more likely to change during operation. - 0x4 - 32 - read-write - 0 - 0x10346 - - - TXBRKEN - Break Enable. - 1 - 1 - read-write - - - NORMAL - Normal operation. - 0 - - - CONTINOUS - Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. - 0x1 - - - - - ADDRDET - Enable address detect mode. - 2 - 1 - read-write - - - DISABLED - Disabled. The USART presents all incoming data. - 0 - - - ENABLED - Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. - 0x1 - - - - - TXDIS - Transmit Disable. - 6 - 1 - read-write - - - ENABLED - Not disabled. USART transmitter is not disabled. - 0 - - - DISABLED - Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. - 0x1 - - - - - CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. - 8 - 1 - read-write - - - CLOCK_ON_CHARACTER - Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. - 0 - - - CONTINOUS_CLOCK - Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). - 0x1 - - - - - CLRCCONRX - Clear Continuous Clock. - 9 - 1 - read-write - - - NO_EFFECT - No effect. No effect on the CC bit. - 0 - - - AUTO_CLEAR - Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. - 0x1 - - - - - AUTOBAUD - Autobaud enable. - 16 - 1 - read-write - - - DISABLED - Disabled. USART is in normal operating mode. - 0 - - - ENABLED - Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. - 0x1 - - - - - - - STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. - 0x8 - 32 - read-write - 0xA - 0x45A - - - RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data. - 1 - 1 - read-only - - - TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data. - 3 - 1 - read-only - - - CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. - 4 - 1 - read-only - - - DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. - 5 - 1 - write-only - - - TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). - 6 - 1 - read-only - - - RXBRK - Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high. - 10 - 1 - read-only - - - DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software. - 11 - 1 - write-only - - - START - This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software. - 12 - 1 - write-only - - - FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. - 13 - 1 - write-only - - - PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. - 14 - 1 - write-only - - - RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception. - 15 - 1 - write-only - - - ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto baud time-out. - 16 - 1 - write-only - - - - - INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. - 0xC - 32 - read-write - 0 - 0x1F868 - - - TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). - 3 - 1 - read-write - - - DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input. - 5 - 1 - read-write - - - TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details. - 6 - 1 - read-write - - - DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted). - 11 - 1 - read-write - - - STARTEN - When 1, enables an interrupt when a received start bit has been detected. - 12 - 1 - read-write - - - FRAMERREN - When 1, enables an interrupt when a framing error has been detected. - 13 - 1 - read-write - - - PARITYERREN - When 1, enables an interrupt when a parity error has been detected. - 14 - 1 - read-write - - - RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. - 15 - 1 - read-write - - - ABERREN - When 1, enables an interrupt when an auto baud error occurs. - 16 - 1 - read-write - - - - - INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. - 0x10 - 32 - write-only - 0 - 0 - - - TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register. - 3 - 1 - write-only - - - DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register. - 5 - 1 - write-only - - - TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register. - 6 - 1 - write-only - - - DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register. - 11 - 1 - write-only - - - STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register. - 12 - 1 - write-only - - - FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - 13 - 1 - write-only - - - PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - 14 - 1 - write-only - - - RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register. - 15 - 1 - write-only - - - ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - 16 - 1 - write-only - - - - - BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. - 0x20 - 32 - read-write - 0 - 0xFFFF - - - BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. - 0 - 16 - read-write - - - - - INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. - 0x24 - 32 - read-only - 0 - 0x1F968 - - - TXIDLE - Transmitter Idle status. - 3 - 1 - read-only - - - DELTACTS - This bit is set when a change in the state of the CTS input is detected. - 5 - 1 - read-only - - - TXDISINT - Transmitter Disabled Interrupt flag. - 6 - 1 - read-only - - - DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. - 11 - 1 - read-only - - - START - This bit is set when a start is detected on the receiver input. - 12 - 1 - read-only - - - FRAMERRINT - Framing Error interrupt flag. - 13 - 1 - read-only - - - PARITYERRINT - Parity Error interrupt flag. - 14 - 1 - read-only - - - RXNOISEINT - Received Noise interrupt flag. - 15 - 1 - read-only - - - ABERRINT - Auto baud Error Interrupt flag. - 16 - 1 - read-only - - - - - OSR - Oversample selection register for asynchronous communication. - 0x28 - 32 - read-write - 0xF - 0xF - - - OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. - 0 - 4 - read-write - - - - - ADDR - Address register for automatic address matching. - 0x2C - 32 - read-write - 0 - 0xFF - - - ADDRESS - 8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). - 0 - 8 - read-write - - - - - FIFOCFG - FIFO configuration and enable register. - 0xE00 - 32 - read-write - 0 - 0x7F033 - - - ENABLETX - Enable the transmit FIFO. - 0 - 1 - read-write - - - DISABLED - The transmit FIFO is not enabled. - 0 - - - ENABLED - The transmit FIFO is enabled. - 0x1 - - - - - ENABLERX - Enable the receive FIFO. - 1 - 1 - read-write - - - DISABLED - The receive FIFO is not enabled. - 0 - - - ENABLED - The receive FIFO is enabled. - 0x1 - - - - - SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - 4 - 2 - read-only - - - DMATX - DMA configuration for transmit. - 12 - 1 - read-write - - - DISABLED - DMA is not used for the transmit function. - 0 - - - ENABLED - Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - 0x1 - - - - - DMARX - DMA configuration for receive. - 13 - 1 - read-write - - - DISABLED - DMA is not used for the receive function. - 0 - - - ENABLED - Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - 0x1 - - - - - WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 14 - 1 - read-write - - - DISABLED - Only enabled interrupts will wake up the device form reduced power modes. - 0 - - - ENABLED - A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. - 0x1 - - - - - WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 15 - 1 - read-write - - - DISABLED - Only enabled interrupts will wake up the device form reduced power modes. - 0 - - - ENABLED - A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. - 0x1 - - - - - EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - 16 - 1 - read-write - - - EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - 17 - 1 - read-write - - - - - FIFOSTAT - FIFO status register. - 0xE04 - 32 - read-write - 0x30 - 0x1F1FFB - - - TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. - 0 - 1 - read-write - - - RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - 1 - 1 - read-write - - - PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. - 3 - 1 - read-only - - - TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - 4 - 1 - read-only - - - TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. - 5 - 1 - read-only - - - RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - 6 - 1 - read-only - - - RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. - 7 - 1 - read-only - - - TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. - 8 - 5 - read-only - - - RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. - 16 - 5 - read-only - - - - - FIFOTRIG - FIFO trigger settings for interrupt and DMA request. - 0xE08 - 32 - read-write - 0 - 0xF0F03 - - - TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - 0 - 1 - read-write - - - DISABLED - Transmit FIFO level does not generate a FIFO level trigger. - 0 - - - ENABLED - An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - 0x1 - - - - - RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - 1 - 1 - read-write - - - DISABLED - Receive FIFO level does not generate a FIFO level trigger. - 0 - - - ENABLED - An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - 0x1 - - - - - TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). - 8 - 4 - read-write - - - RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). - 16 - 4 - read-write - - - - - FIFOINTENSET - FIFO interrupt enable set (enable) and read register. - 0xE10 - 32 - read-write - 0 - 0xF - - - TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - 0 - 1 - read-write - - - DISABLED - No interrupt will be generated for a transmit error. - 0 - - - ENABLED - An interrupt will be generated when a transmit error occurs. - 0x1 - - - - - RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - 1 - 1 - read-write - - - DISABLED - No interrupt will be generated for a receive error. - 0 - - - ENABLED - An interrupt will be generated when a receive error occurs. - 0x1 - - - - - TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 2 - 1 - read-write - - - DISABLED - No interrupt will be generated based on the TX FIFO level. - 0 - - - ENABLED - If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. - 0x1 - - - - - RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 3 - 1 - read-write - - - DISABLED - No interrupt will be generated based on the RX FIFO level. - 0 - - - ENABLED - If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. - 0x1 - - - - - - - FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. - 0xE14 - 32 - read-write - 0 - 0xF - - - TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - 0 - 1 - read-write - - - RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - 1 - 1 - read-write - - - TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - 2 - 1 - read-write - - - RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - 3 - 1 - read-write - - - - - FIFOINTSTAT - FIFO interrupt status register. - 0xE18 - 32 - read-only - 0 - 0x1F - - - TXERR - TX FIFO error. - 0 - 1 - read-only - - - RXERR - RX FIFO error. - 1 - 1 - read-only - - - TXLVL - Transmit FIFO level interrupt. - 2 - 1 - read-only - - - RXLVL - Receive FIFO level interrupt. - 3 - 1 - read-only - - - PERINT - Peripheral interrupt. - 4 - 1 - read-only - - - - - FIFOWR - FIFO write data. - 0xE20 - 32 - write-only - 0 - 0 - - - TXDATA - Transmit data to the FIFO. - 0 - 9 - write-only - - - - - FIFORD - FIFO read data. - 0xE30 - 32 - read-only - 0 - 0xE1FF - - - RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. - 0 - 9 - read-only - - - FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. - 13 - 1 - read-only - - - PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. - 14 - 1 - read-only - - - RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. - 15 - 1 - read-only - - - - - FIFORDNOPOP - FIFO data read with no FIFO pop. - 0xE40 - 32 - read-only - 0 - 0xE1FF - - - RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. - 0 - 9 - read-only - - - FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. - 13 - 1 - read-only - - - PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. - 14 - 1 - read-only - - - RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. - 15 - 1 - read-only - - - - - FIFOSIZE - FIFO size register - 0xE48 - 32 - read-write - 0x8 - 0xFFFFFFFF - - - FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - 0 - 5 - read-only - - - - - ID - Peripheral identification register. - 0xFFC - 32 - read-only - 0 - 0xFFFFFFFF - - - APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - 0 - 8 - read-only - - - MINOR_REV - Minor revision of module implementation. - 8 - 4 - read-only - - - MAJOR_REV - Major revision of module implementation. - 12 - 4 - read-only - - - ID - Module identifier for the selected function. - 16 - 16 - read-only - - - - - - - USART1 - USARTs - FLEXCOMM1 - USART - 0x40087000 - - 0 - 0x1000 - registers - - - FLEXCOMM1 - 15 - - - - USART2 - USARTs - FLEXCOMM2 - USART - 0x40088000 - - 0 - 0x1000 - registers - - - FLEXCOMM2 - 16 - - - - USART3 - USARTs - FLEXCOMM3 - USART - 0x40089000 - - 0 - 0x1000 - registers - - - FLEXCOMM3 - 17 - - - - USART4 - USARTs - FLEXCOMM4 - USART - 0x4008A000 - - 0 - 0x1000 - registers - - - FLEXCOMM4 - 18 - - - - USART5 - USARTs - FLEXCOMM5 - USART - 0x40096000 - - 0 - 0x1000 - registers - - - FLEXCOMM5 - 19 - - - - USART6 - USARTs - FLEXCOMM6 - USART - 0x40097000 - - 0 - 0x1000 - registers - - - FLEXCOMM6 - 20 - - - - USART7 - USARTs - FLEXCOMM7 - USART - 0x40098000 - - 0 - 0x1000 - registers - - - FLEXCOMM7 - 21 - - - - GPIO - General Purpose I/O (GPIO) - GPIO - 0x4008C000 - - 0 - 0x2488 - registers - - - - 2 - 0x20 - B[%s] - no description available - 0 - - 32 - 0x1 - B_[%s] - Byte pin registers for all port GPIO pins - 0 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - - 2 - 0x80 - W[%s] - no description available - 0x1000 - - 32 - 0x4 - W_[%s] - Word pin registers for all port GPIO pins - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - - 2 - 0x4 - DIR[%s] - Direction registers for all port GPIO pins - 0x2000 - 32 - read-write - 0 - 0xFFFFFFFF - - - DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output. - 0 - 32 - read-write - - - - - 2 - 0x4 - MASK[%s] - Mask register for all port GPIO pins - 0x2080 - 32 - read-write - 0 - 0xFFFFFFFF - - - MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. - 0 - 32 - read-write - - - - - 2 - 0x4 - PIN[%s] - Port pin register for all port GPIO pins - 0x2100 - 32 - read-write - 0 - 0xFFFFFFFF - - - PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. - 0 - 32 - read-write - - - - - 2 - 0x4 - MPIN[%s] - Masked port register for all port GPIO pins - 0x2180 - 32 - read-write - 0 - 0xFFFFFFFF - - - MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. - 0 - 32 - read-write - - - - - 2 - 0x4 - SET[%s] - Write: Set register for port. Read: output bits for port - 0x2200 - 32 - read-write - 0 - 0xFFFFFFFF - - - SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. - 0 - 32 - read-write - - - - - 2 - 0x4 - CLR[%s] - Clear port for all port GPIO pins - 0x2280 - 32 - write-only - 0 - 0 - - - CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit. - 0 - 32 - write-only - - - - - 2 - 0x4 - NOT[%s] - Toggle port for all port GPIO pins - 0x2300 - 32 - write-only - 0 - 0 - - - NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit. - 0 - 32 - write-only - - - - - 2 - 0x4 - DIRSET[%s] - Set pin direction bits for port - 0x2380 - 32 - write-only - 0 - 0 - - - DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit. - 0 - 32 - write-only - - - - - 2 - 0x4 - DIRCLR[%s] - Clear pin direction bits for port - 0x2400 - 32 - write-only - 0 - 0 - - - DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit. - 0 - 32 - write-only - - - - - 2 - 0x4 - DIRNOT[%s] - Toggle pin direction bits for port - 0x2480 - 32 - write-only - 0 - 0 - - - DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit. - 0 - 32 - write-only - - - - - - - USBHSD - USB1 High-speed Device Controller - USBHSD - 0x40094000 - - 0 - 0x38 - registers - - - USB1 - 47 - - - USB1_NEEDCLK - 48 - - - - DEVCMDSTAT - USB Device Command/Status register - 0 - 32 - read-write - 0x800 - 0xF7DBFFFF - - - DEV_ADDR - USB device address. - 0 - 7 - read-write - - - DEV_EN - USB device enable. - 7 - 1 - read-write - - - SETUP - SETUP token received. - 8 - 1 - read-write - - - FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:. - 9 - 1 - read-write - - - LPM_SUP - LPM Supported:. - 11 - 1 - read-write - - - INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP:. - 12 - 1 - read-write - - - INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP:. - 13 - 1 - read-write - - - INTONNAK_CO - Interrupt on NAK for control OUT EP:. - 14 - 1 - read-write - - - INTONNAK_CI - Interrupt on NAK for control IN EP:. - 15 - 1 - read-write - - - DCON - Device status - connect. - 16 - 1 - read-write - - - DSUS - Device status - suspend. - 17 - 1 - read-write - - - LPM_SUS - Device status - LPM Suspend. - 19 - 1 - read-write - - - LPM_REWP - LPM Remote Wake-up Enabled by USB host. - 20 - 1 - read-only - - - Speed - This field indicates the speed at which the device operates: 00b: reserved 01b: full-speed 10b: high-speed 11b: super-speed (reserved for future use). - 22 - 2 - read-only - - - DCON_C - Device status - connect change. - 24 - 1 - read-write - - - DSUS_C - Device status - suspend change. - 25 - 1 - read-write - - - DRES_C - Device status - reset change. - 26 - 1 - read-write - - - VBUS_DEBOUNCED - This bit indicates if VBUS is detected or not. - 28 - 1 - read-only - - - PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification. - 29 - 3 - read-write - - - DISABLE - Test mode disabled. - 0 - - - TEST_J - Test_J. - 0x1 - - - TEST_K - Test_K. - 0x2 - - - TEST_SE0_NAK - Test_SE0_NAK. - 0x3 - - - TEST_PACKET - Test_Packet. - 0x4 - - - TEST_FORCE_ENABLE - Test_Force_Enable. - 0x5 - - - - - - - INFO - USB Info register - 0x4 - 32 - read-only - 0x2000000 - 0xFFFF7FFF - - - FRAME_NR - Frame number. - 0 - 11 - read-only - - - ERR_CODE - The error code which last occurred:. - 11 - 4 - read-only - - - MINREV - Minor revision. - 16 - 8 - read-only - - - MAJREV - Major revision. - 24 - 8 - read-only - - - - - EPLISTSTART - USB EP Command/Status List start address - 0x8 - 32 - read-write - 0 - 0xFFFFFF00 - - - EP_LIST_PRG - Programmable portion of the USB EP Command/Status List address. - 8 - 12 - read-write - - - EP_LIST_FIXED - Fixed portion of USB EP Command/Status List address. - 20 - 12 - read-only - - - - - DATABUFSTART - USB Data buffer start address - 0xC - 32 - read-write - 0x41000000 - 0xFFFFFFFF - - - DA_BUF - Start address of the memory page where all endpoint data buffers are located. - 0 - 32 - read-write - - - - - LPM - USB Link Power Management register - 0x10 - 32 - read-write - 0 - 0x1FF - - - HIRD_HW - Host Initiated Resume Duration - HW. - 0 - 4 - read-only - - - HIRD_SW - Host Initiated Resume Duration - SW. - 4 - 4 - read-write - - - DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. - 8 - 1 - read-write - - - - - EPSKIP - USB Endpoint skip - 0x14 - 32 - read-write - 0 - 0xFFF - - - SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. - 0 - 12 - read-write - - - - - EPINUSE - USB Endpoint Buffer in use - 0x18 - 32 - read-write - 0 - 0xFFC - - - BUF - Buffer in use: This register has one bit per physical endpoint. - 2 - 10 - read-write - - - - - EPBUFCFG - USB Endpoint Buffer Configuration register - 0x1C - 32 - read-write - 0 - 0xFFC - - - BUF_SB - Buffer usage: This register has one bit per physical endpoint. - 2 - 10 - read-write - - - - - INTSTAT - USB interrupt status register - 0x20 - 32 - read-write - 0 - 0xC0000FFF - - - EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. - 0 - 1 - read-write - - - EP0IN - Interrupt status register bit for the Control EP0 IN direction. - 1 - 1 - read-write - - - EP1OUT - Interrupt status register bit for the EP1 OUT direction. - 2 - 1 - read-write - - - EP1IN - Interrupt status register bit for the EP1 IN direction. - 3 - 1 - read-write - - - EP2OUT - Interrupt status register bit for the EP2 OUT direction. - 4 - 1 - read-write - - - EP2IN - Interrupt status register bit for the EP2 IN direction. - 5 - 1 - read-write - - - EP3OUT - Interrupt status register bit for the EP3 OUT direction. - 6 - 1 - read-write - - - EP3IN - Interrupt status register bit for the EP3 IN direction. - 7 - 1 - read-write - - - EP4OUT - Interrupt status register bit for the EP4 OUT direction. - 8 - 1 - read-write - - - EP4IN - Interrupt status register bit for the EP4 IN direction. - 9 - 1 - read-write - - - EP5OUT - Interrupt status register bit for the EP5 OUT direction. - 10 - 1 - read-write - - - EP5IN - Interrupt status register bit for the EP5 IN direction. - 11 - 1 - read-write - - - FRAME_INT - Frame interrupt. - 30 - 1 - read-write - - - DEV_INT - Device status interrupt. - 31 - 1 - read-write - - - - - INTEN - USB interrupt enable register - 0x24 - 32 - read-write - 0 - 0xC0000FFF - - - EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. - 0 - 12 - read-write - - - FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. - 30 - 1 - read-write - - - DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. - 31 - 1 - read-write - - - - - INTSETSTAT - USB set interrupt status register - 0x28 - 32 - read-write - 0 - 0xC0000FFF - - - EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. - 0 - 12 - read-write - - - FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. - 30 - 1 - read-write - - - DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. - 31 - 1 - read-write - - - - - EPTOGGLE - USB Endpoint toggle register - 0x34 - 32 - read-only - 0 - 0x3FFFFFFF - - - TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. - 0 - 30 - read-only - - - - - - - CRC_ENGINE - CRC engine - CRC - 0x40095000 - - 0 - 0xC - registers - - - - MODE - CRC mode register - 0 - 32 - read-write - 0 - 0x3F - - - CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial - 0 - 2 - read-write - - - BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) - 2 - 1 - read-write - - - CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA - 3 - 1 - read-write - - - BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM - 4 - 1 - read-write - - - CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM - 5 - 1 - read-write - - - - - SEED - CRC seed register - 0x4 - 32 - read-write - 0xFFFF - 0xFFFFFFFF - - - CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses. - 0 - 32 - read-write - - - - - SUM - CRC checksum register - SUM_WR_DATA - 0x8 - 32 - read-only - 0xFFFF - 0xFFFFFFFF - - - CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. - 0 - 32 - read-only - - - - - WR_DATA - CRC data register - SUM_WR_DATA - 0x8 - 32 - write-only - 0 - 0 - - - CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions. - 0 - 32 - write-only - - - - - - - SDIF - SDMMC - SDIF - 0x4009B000 - - 0 - 0x300 - registers - - - SDIO - 42 - - - - CTRL - Control register - 0 - 32 - read-write - 0 - 0x2070FD7 - - - CONTROLLER_RESET - Controller reset. - 0 - 1 - read-write - - - FIFO_RESET - Fifo reset. - 1 - 1 - read-write - - - DMA_RESET - DMA reset. - 2 - 1 - read-write - - - INT_ENABLE - Global interrupt enable/disable bit. - 4 - 1 - read-write - - - READ_WAIT - Read/wait. - 6 - 1 - read-write - - - SEND_IRQ_RESPONSE - Send irq response. - 7 - 1 - read-write - - - ABORT_READ_DATA - Abort read data. - 8 - 1 - read-write - - - SEND_CCSD - Send ccsd. - 9 - 1 - read-write - - - SEND_AUTO_STOP_CCSD - Send auto stop ccsd. - 10 - 1 - read-write - - - CEATA_DEVICE_INTERRUPT_STATUS - CEATA device interrupt status. - 11 - 1 - read-write - - - CARD_VOLTAGE_A0 - Controls the state of the SD_VOLT0 pin. - 16 - 1 - read-write - - - CARD_VOLTAGE_A1 - Controls the state of the SD_VOLT1 pin. - 17 - 1 - read-write - - - CARD_VOLTAGE_A2 - Controls the state of the SD_VOLT2 pin. - 18 - 1 - read-write - - - USE_INTERNAL_DMAC - SD/MMC DMA use. - 25 - 1 - read-write - - - - - PWREN - Power Enable register - 0x4 - 32 - read-write - 0 - 0x3 - - - POWER_ENABLE0 - Power on/off switch for card 0; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card 0. - 0 - 1 - read-write - - - POWER_ENABLE1 - Power on/off switch for card 1; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card 1. - 1 - 1 - read-write - - - - - CLKDIV - Clock Divider register - 0x8 - 32 - read-write - 0 - 0xFF - - - CLK_DIVIDER0 - Clock divider-0 value. - 0 - 8 - read-write - - - - - CLKENA - Clock Enable register - 0x10 - 32 - read-write - 0 - 0x30003 - - - CCLK0_ENABLE - Clock-enable control for SD card 0 clock. - 0 - 1 - read-write - - - CCLK1_ENABLE - Clock-enable control for SD card 1 clock. - 1 - 1 - read-write - - - CCLK0_LOW_POWER - Low-power control for SD card 0 clock. - 16 - 1 - read-write - - - CCLK1_LOW_POWER - Low-power control for SD card 1 clock. - 17 - 1 - read-write - - - - - TMOUT - Time-out register - 0x14 - 32 - read-write - 0xFFFFFF40 - 0xFFFFFFFF - - - RESPONSE_TIMEOUT - Response time-out value. - 0 - 8 - read-write - - - DATA_TIMEOUT - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. - 8 - 24 - read-write - - - - - CTYPE - Card Type register - 0x18 - 32 - read-write - 0 - 0x30003 - - - CARD0_WIDTH0 - Indicates if card 0 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD0_WIDTH1 is not enabled (bit 16 in this register is set to 0). - 0 - 1 - read-write - - - CARD1_WIDTH0 - Indicates if card 1 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD1_WIDTH1 is not enabled (bit 16 in this register is set to 0). - 1 - 1 - read-write - - - CARD0_WIDTH1 - Indicates if card 0 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. - 16 - 1 - read-write - - - CARD1_WIDTH1 - Indicates if card 1 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. - 17 - 1 - read-write - - - - - BLKSIZ - Block Size register - 0x1C - 32 - read-write - 0x200 - 0xFFFF - - - BLOCK_SIZE - Block size. - 0 - 16 - read-write - - - - - BYTCNT - Byte Count register - 0x20 - 32 - read-write - 0x200 - 0xFFFFFFFF - - - BYTE_COUNT - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. - 0 - 32 - read-write - - - - - INTMASK - Interrupt Mask register - 0x24 - 32 - read-write - 0 - 0x1FFFF - - - CDET - Card detect. - 0 - 1 - read-write - - - RE - Response error. - 1 - 1 - read-write - - - CDONE - Command done. - 2 - 1 - read-write - - - DTO - Data transfer over. - 3 - 1 - read-write - - - TXDR - Transmit FIFO data request. - 4 - 1 - read-write - - - RXDR - Receive FIFO data request. - 5 - 1 - read-write - - - RCRC - Response CRC error. - 6 - 1 - read-write - - - DCRC - Data CRC error. - 7 - 1 - read-write - - - RTO - Response time-out. - 8 - 1 - read-write - - - DRTO - Data read time-out. - 9 - 1 - read-write - - - HTO - Data starvation-by-host time-out (HTO). - 10 - 1 - read-write - - - FRUN - FIFO underrun/overrun error. - 11 - 1 - read-write - - - HLE - Hardware locked write error. - 12 - 1 - read-write - - - SBE - Start-bit error. - 13 - 1 - read-write - - - ACD - Auto command done. - 14 - 1 - read-write - - - EBE - End-bit error (read)/Write no CRC. - 15 - 1 - read-write - - - SDIO_INT_MASK - Mask SDIO interrupt. - 16 - 1 - read-write - - - - - CMDARG - Command Argument register - 0x28 - 32 - read-write - 0 - 0xFFFFFFFF - - - CMD_ARG - Value indicates command argument to be passed to card. - 0 - 32 - read-write - - - - - CMD - Command register - 0x2C - 32 - read-write - 0 - 0xBFFFFFFF - - - CMD_INDEX - Command index. - 0 - 6 - read-write - - - RESPONSE_EXPECT - Response expect. - 6 - 1 - read-write - - - RESPONSE_LENGTH - Response length. - 7 - 1 - read-write - - - CHECK_RESPONSE_CRC - Check response CRC. - 8 - 1 - read-write - - - DATA_EXPECTED - Data expected. - 9 - 1 - read-write - - - READ_WRITE - read/write. - 10 - 1 - read-write - - - TRANSFER_MODE - Transfer mode. - 11 - 1 - read-write - - - SEND_AUTO_STOP - Send auto stop. - 12 - 1 - read-write - - - WAIT_PRVDATA_COMPLETE - Wait prvdata complete. - 13 - 1 - read-write - - - STOP_ABORT_CMD - Stop abort command. - 14 - 1 - read-write - - - SEND_INITIALIZATION - Send initialization. - 15 - 1 - read-write - - - CARD_NUMBER - Specifies the card number of SDCARD for which the current Command is being executed - 16 - 5 - read-write - - - CARD0 - Command will be execute on SDCARD 0 - 0 - - - CARD1 - Command will be execute on SDCARD 1 - 0x1 - - - - - UPDATE_CLOCK_REGISTERS_ONLY - Update clock registers only. - 21 - 1 - read-write - - - READ_CEATA_DEVICE - Read ceata device. - 22 - 1 - read-write - - - CCS_EXPECTED - CCS expected. - 23 - 1 - read-write - - - ENABLE_BOOT - Enable Boot - this bit should be set only for mandatory boot mode. - 24 - 1 - read-write - - - EXPECT_BOOT_ACK - Expect Boot Acknowledge. - 25 - 1 - read-write - - - DISABLE_BOOT - Disable Boot. - 26 - 1 - read-write - - - BOOT_MODE - Boot Mode. - 27 - 1 - read-write - - - VOLT_SWITCH - Voltage switch bit. - 28 - 1 - read-write - - - USE_HOLD_REG - Use Hold Register. - 29 - 1 - read-write - - - START_CMD - Start command. - 31 - 1 - read-write - - - - - 4 - 0x4 - RESP[%s] - Response register - 0x30 - 32 - read-write - 0 - 0xFFFFFFFF - - - RESPONSE - Bits of response. - 0 - 32 - read-write - - - - - MINTSTS - Masked Interrupt Status register - 0x40 - 32 - read-write - 0 - 0x1FFFF - - - CDET - Card detect. - 0 - 1 - read-write - - - RE - Response error. - 1 - 1 - read-write - - - CDONE - Command done. - 2 - 1 - read-write - - - DTO - Data transfer over. - 3 - 1 - read-write - - - TXDR - Transmit FIFO data request. - 4 - 1 - read-write - - - RXDR - Receive FIFO data request. - 5 - 1 - read-write - - - RCRC - Response CRC error. - 6 - 1 - read-write - - - DCRC - Data CRC error. - 7 - 1 - read-write - - - RTO - Response time-out. - 8 - 1 - read-write - - - DRTO - Data read time-out. - 9 - 1 - read-write - - - HTO - Data starvation-by-host time-out (HTO). - 10 - 1 - read-write - - - FRUN - FIFO underrun/overrun error. - 11 - 1 - read-write - - - HLE - Hardware locked write error. - 12 - 1 - read-write - - - SBE - Start-bit error. - 13 - 1 - read-write - - - ACD - Auto command done. - 14 - 1 - read-write - - - EBE - End-bit error (read)/write no CRC. - 15 - 1 - read-write - - - SDIO_INTERRUPT - Interrupt from SDIO card. - 16 - 1 - read-write - - - - - RINTSTS - Raw Interrupt Status register - 0x44 - 32 - read-write - 0 - 0x1FFFF - - - CDET - Card detect. - 0 - 1 - read-write - - - RE - Response error. - 1 - 1 - read-write - - - CDONE - Command done. - 2 - 1 - read-write - - - DTO - Data transfer over. - 3 - 1 - read-write - - - TXDR - Transmit FIFO data request. - 4 - 1 - read-write - - - RXDR - Receive FIFO data request. - 5 - 1 - read-write - - - RCRC - Response CRC error. - 6 - 1 - read-write - - - DCRC - Data CRC error. - 7 - 1 - read-write - - - RTO_BAR - Response time-out (RTO)/Boot Ack Received (BAR). - 8 - 1 - read-write - - - DRTO_BDS - Data read time-out (DRTO)/Boot Data Start (BDS). - 9 - 1 - read-write - - - HTO - Data starvation-by-host time-out (HTO). - 10 - 1 - read-write - - - FRUN - FIFO underrun/overrun error. - 11 - 1 - read-write - - - HLE - Hardware locked write error. - 12 - 1 - read-write - - - SBE - Start-bit error. - 13 - 1 - read-write - - - ACD - Auto command done. - 14 - 1 - read-write - - - EBE - End-bit error (read)/write no CRC. - 15 - 1 - read-write - - - SDIO_INTERRUPT - Interrupt from SDIO card. - 16 - 1 - read-write - - - - - STATUS - Status register - 0x48 - 32 - read-write - 0x406 - 0xFFFFFFFF - - - FIFO_RX_WATERMARK - FIFO reached Receive watermark level; not qualified with data transfer. - 0 - 1 - read-write - - - FIFO_TX_WATERMARK - FIFO reached Transmit watermark level; not qualified with data transfer. - 1 - 1 - read-write - - - FIFO_EMPTY - FIFO is empty status. - 2 - 1 - read-write - - - FIFO_FULL - FIFO is full status. - 3 - 1 - read-write - - - CMDFSMSTATES - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The command FSM state is represented using 19 bits. - 4 - 4 - read-write - - - DATA_3_STATUS - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present. - 8 - 1 - read-write - - - DATA_BUSY - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy. - 9 - 1 - read-write - - - DATA_STATE_MC_BUSY - Data transmit or receive state-machine is busy. - 10 - 1 - read-write - - - RESPONSE_INDEX - Index of previous response, including any auto-stop sent by core. - 11 - 6 - read-write - - - FIFO_COUNT - FIFO count - Number of filled locations in FIFO. - 17 - 13 - read-write - - - DMA_ACK - DMA acknowledge signal state. - 30 - 1 - read-write - - - DMA_REQ - DMA request signal state. - 31 - 1 - read-write - - - - - FIFOTH - FIFO Threshold Watermark register - 0x4C - 32 - read-write - 0x1F0000 - 0x7FFF0FFF - - - TX_WMARK - FIFO threshold watermark level when transmitting data to card. - 0 - 12 - read-write - - - RX_WMARK - FIFO threshold watermark level when receiving data to card. - 16 - 12 - read-write - - - DMA_MTS - Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE. - 28 - 3 - read-write - - - - - CDETECT - Card Detect register - 0x50 - 32 - read-write - 0 - 0x1 - - - CARD0_DETECT - Card 0 detect - 0 - 1 - read-write - - - CARD1_DETECT - Card 1 detect - 1 - 1 - read-write - - - - - WRTPRT - Write Protect register - 0x54 - 32 - read-write - 0 - 0x1 - - - WRITE_PROTECT - Write protect. - 0 - 1 - read-write - - - - - TCBCNT - Transferred CIU Card Byte Count register - 0x5C - 32 - read-write - 0 - 0xFFFFFFFF - - - TRANS_CARD_BYTE_COUNT - Number of bytes transferred by CIU unit to card. - 0 - 32 - read-write - - - - - TBBCNT - Transferred Host to BIU-FIFO Byte Count register - 0x60 - 32 - read-write - 0 - 0xFFFFFFFF - - - TRANS_FIFO_BYTE_COUNT - Number of bytes transferred between Host/DMA memory and BIU FIFO. - 0 - 32 - read-write - - - - - DEBNCE - Debounce Count register - 0x64 - 32 - read-write - 0xFFFFFF - 0xFFFFFF - - - DEBOUNCE_COUNT - Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms. - 0 - 24 - read-write - - - - - RST_N - Hardware Reset - 0x78 - 32 - read-write - 0x1 - 0x1 - - - CARD_RESET - Hardware reset. - 0 - 1 - read-write - - - - - BMOD - Bus Mode register - 0x80 - 32 - read-write - 0 - 0x7FF - - - SWR - Software Reset. - 0 - 1 - read-write - - - FB - Fixed Burst. - 1 - 1 - read-write - - - DSL - Descriptor Skip Length. - 2 - 5 - read-write - - - DE - SD/MMC DMA Enable. - 7 - 1 - read-write - - - PBL - Programmable Burst Length. - 8 - 3 - read-write - - - - - PLDMND - Poll Demand register - 0x84 - 32 - read-write - 0 - 0xFFFFFFFF - - - PD - Poll Demand. - 0 - 32 - read-write - - - - - DBADDR - Descriptor List Base Address register - 0x88 - 32 - read-write - 0 - 0xFFFFFFFF - - - SDL - Start of Descriptor List. - 0 - 32 - read-write - - - - - IDSTS - Internal DMAC Status register - 0x8C - 32 - read-write - 0 - 0x1FF37 - - - TI - Transmit Interrupt. - 0 - 1 - read-write - - - RI - Receive Interrupt. - 1 - 1 - read-write - - - FBE - Fatal Bus Error Interrupt. - 2 - 1 - read-write - - - DU - Descriptor Unavailable Interrupt. - 4 - 1 - read-write - - - CES - Card Error Summary. - 5 - 1 - read-write - - - NIS - Normal Interrupt Summary. - 8 - 1 - read-write - - - AIS - Abnormal Interrupt Summary. - 9 - 1 - read-write - - - EB - Error Bits. - 10 - 3 - read-write - - - FSM - DMAC state machine present state. - 13 - 4 - read-write - - - - - IDINTEN - Internal DMAC Interrupt Enable register - 0x90 - 32 - read-write - 0 - 0x337 - - - TI - Transmit Interrupt Enable. - 0 - 1 - read-write - - - RI - Receive Interrupt Enable. - 1 - 1 - read-write - - - FBE - Fatal Bus Error Enable. - 2 - 1 - read-write - - - DU - Descriptor Unavailable Interrupt. - 4 - 1 - read-write - - - CES - Card Error summary Interrupt Enable. - 5 - 1 - read-write - - - NIS - Normal Interrupt Summary Enable. - 8 - 1 - read-write - - - AIS - Abnormal Interrupt Summary Enable. - 9 - 1 - read-write - - - - - DSCADDR - Current Host Descriptor Address register - 0x94 - 32 - read-write - 0 - 0xFFFFFFFF - - - HDA - Host Descriptor Address Pointer. - 0 - 32 - read-write - - - - - BUFADDR - Current Buffer Descriptor Address register - 0x98 - 32 - read-write - 0 - 0xFFFFFFFF - - - HBA - Host Buffer Address Pointer. - 0 - 32 - read-write - - - - - CARDTHRCTL - Card Threshold Control - 0x100 - 32 - read-write - 0 - 0xFF0003 - - - CARDRDTHREN - Card Read Threshold Enable. - 0 - 1 - read-write - - - BSYCLRINTEN - Busy Clear Interrupt Enable. - 1 - 1 - read-write - - - CARDTHRESHOLD - Card Threshold size. - 16 - 8 - read-write - - - - - BACKENDPWR - Power control - 0x104 - 32 - read-write - 0 - 0x1 - - - BACKENDPWR - Back-end Power control for card application. - 0 - 1 - read-write - - - - - 64 - 0x4 - FIFO[%s] - SDIF FIFO - 0x200 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - SDIF FIFO. - 0 - 32 - read-write - - - - - - - DBGMAILBOX - MCU Debugger Mailbox - DBGMAILBOX - 0x4009C000 - - 0 - 0x100 - registers - - - - CSW - CRC mode register - 0 - 32 - read-write - 0 - 0x3F - - - RESYNCH_REQ - Debugger will set this bit to 1 to request a resynchronrisation - 0 - 1 - read-write - - - REQ_PENDING - Request is pending from debugger (i.e unread value in REQUEST) - 1 - 1 - read-write - - - DBG_OR_ERR - Debugger overrun error (previous REQUEST overwritten before being picked up by ROM) - 2 - 1 - read-write - - - AHB_OR_ERR - AHB overrun Error (Return value overwritten by ROM) - 3 - 1 - read-write - - - SOFT_RESET - Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to this bit will cause a soft reset for DM. - 4 - 1 - read-write - - - CHIP_RESET_REQ - Write only bit. Once written will cause the chip to reset (note that the DM is not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event) - 5 - 1 - write-only - - - - - REQUEST - CRC seed register - 0x4 - 32 - read-write - 0xFFFF - 0xFFFFFFFF - - - REQ - Request Value - 0 - 32 - read-write - - - - - RETURN - Return value from ROM. - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - RET - The Return value from ROM. - 0 - 32 - read-write - - - - - ID - Identification register - 0xFC - 32 - read-only - 0x2A0000 - 0xFFFFFFFF - - - ID - Identification value. - 0 - 32 - read-only - - - - - - - ADC0 - ADC - ADC - 0x400A0000 - - 0 - 0x1000 - registers - - - ADC0 - 22 - - - - VERID - Version ID Register - 0 - 32 - read-only - 0x1002C0B - 0xFFFFFFFF - - - RES - Resolution - 0 - 1 - read-only - - - RES_0 - Up to 13-bit differential/12-bit single ended resolution supported. - 0 - - - RES_1 - Up to 16-bit differential/16-bit single ended resolution supported. - 0x1 - - - - - DIFFEN - Differential Supported - 1 - 1 - read-only - - - DIFFEN_0 - Differential operation not supported. - 0 - - - DIFFEN_1 - Differential operation supported. CMDLa[CTYPE] controls fields implemented. - 0x1 - - - - - MVI - Multi Vref Implemented - 3 - 1 - read-only - - - MVI_0 - Single voltage reference high (VREFH) input supported. - 0 - - - MVI_1 - Multiple voltage reference high (VREFH) inputs supported. - 0x1 - - - - - CSW - Channel Scale Width - 4 - 3 - read-only - - - CSW_0 - Channel scaling not supported. - 0 - - - CSW_1 - Channel scaling supported. 1-bit CSCALE control field. - 0x1 - - - CSW_6 - Channel scaling supported. 6-bit CSCALE control field. - 0x6 - - - - - VR1RNGI - Voltage Reference 1 Range Control Bit Implemented - 8 - 1 - read-only - - - VR1RNGI_0 - Range control not required. CFG[VREF1RNG] is not implemented. - 0 - - - VR1RNGI_1 - Range control required. CFG[VREF1RNG] is implemented. - 0x1 - - - - - IADCKI - Internal ADC Clock implemented - 9 - 1 - read-only - - - IADCKI_0 - Internal clock source not implemented. - 0 - - - IADCKI_1 - Internal clock source (and CFG[ADCKEN]) implemented. - 0x1 - - - - - CALOFSI - Calibration Function Implemented - 10 - 1 - read-only - - - CALOFSI_0 - Calibration Not Implemented. - 0 - - - CALOFSI_1 - Calibration Implemented. - 0x1 - - - - - NUM_SEC - Number of Single Ended Outputs Supported - 11 - 1 - read-only - - - NUM_SEC_0 - This design supports one single ended conversion at a time. - 0 - - - NUM_SEC_1 - This design supports two simultanious single ended conversions. - 0x1 - - - - - NUM_FIFO - Number of FIFOs - 12 - 3 - read-only - - - NUM_FIFO_0 - N/A - 0 - - - NUM_FIFO_1 - This design supports one result FIFO. - 0x1 - - - NUM_FIFO_2 - This design supports two result FIFOs. - 0x2 - - - NUM_FIFO_3 - This design supports three result FIFOs. - 0x3 - - - NUM_FIFO_4 - This design supports four result FIFOs. - 0x4 - - - - - MINOR - Minor Version Number - 16 - 8 - read-only - - - MAJOR - Major Version Number - 24 - 8 - read-only - - - - - PARAM - Parameter Register - 0x4 - 32 - read-only - 0xF041010 - 0xFFFFFFFF - - - TRIG_NUM - Trigger Number - 0 - 8 - read-only - - - FIFOSIZE - Result FIFO Depth - 8 - 8 - read-only - - - FIFOSIZE_1 - Result FIFO depth = 1 dataword. - 0x1 - - - FIFOSIZE_4 - Result FIFO depth = 4 datawords. - 0x4 - - - FIFOSIZE_8 - Result FIFO depth = 8 datawords. - 0x8 - - - FIFOSIZE_16 - Result FIFO depth = 16 datawords. - 0x10 - - - FIFOSIZE_32 - Result FIFO depth = 32 datawords. - 0x20 - - - FIFOSIZE_64 - Result FIFO depth = 64 datawords. - 0x40 - - - - - CV_NUM - Compare Value Number - 16 - 8 - read-only - - - CMD_NUM - Command Buffer Number - 24 - 8 - read-only - - - - - CTRL - ADC Control Register - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCEN - ADC Enable - 0 - 1 - read-write - - - ADCEN_0 - ADC is disabled. - 0 - - - ADCEN_1 - ADC is enabled. - 0x1 - - - - - RST - Software Reset - 1 - 1 - read-write - - - RST_0 - ADC logic is not reset. - 0 - - - RST_1 - ADC logic is reset. - 0x1 - - - - - DOZEN - Doze Enable - 2 - 1 - read-write - - - DOZEN_0 - ADC is enabled in Doze mode. - 0 - - - DOZEN_1 - ADC is disabled in Doze mode. - 0x1 - - - - - CAL_REQ - Auto-Calibration Request - 3 - 1 - read-write - - - CAL_REQ_0 - No request for auto-calibration has been made. - 0 - - - CAL_REQ_1 - A request for auto-calibration has been made - 0x1 - - - - - CALOFS - Configure for offset calibration function - 4 - 1 - read-write - - - CALOFS_0 - Calibration function disabled - 0 - - - CALOFS_1 - Request for offset calibration function - 0x1 - - - - - RSTFIFO0 - Reset FIFO 0 - 8 - 1 - read-write - - - RSTFIFO0_0 - No effect. - 0 - - - RSTFIFO0_1 - FIFO 0 is reset. - 0x1 - - - - - RSTFIFO1 - Reset FIFO 1 - 9 - 1 - read-write - - - RSTFIFO1_0 - No effect. - 0 - - - RSTFIFO1_1 - FIFO 1 is reset. - 0x1 - - - - - CAL_AVGS - Auto-Calibration Averages - 16 - 3 - read-write - - - CAL_AVGS_0 - Single conversion. - 0 - - - CAL_AVGS_1 - 2 conversions averaged. - 0x1 - - - CAL_AVGS_2 - 4 conversions averaged. - 0x2 - - - CAL_AVGS_3 - 8 conversions averaged. - 0x3 - - - CAL_AVGS_4 - 16 conversions averaged. - 0x4 - - - CAL_AVGS_5 - 32 conversions averaged. - 0x5 - - - CAL_AVGS_6 - 64 conversions averaged. - 0x6 - - - CAL_AVGS_7 - 128 conversions averaged. - 0x7 - - - - - - - STAT - ADC Status Register - 0x14 - 32 - read-write - 0 - 0xFFFFFFFF - - - RDY0 - Result FIFO 0 Ready Flag - 0 - 1 - read-only - - - RDY0_0 - Result FIFO 0 data level not above watermark level. - 0 - - - RDY0_1 - Result FIFO 0 holding data above watermark level. - 0x1 - - - - - FOF0 - Result FIFO 0 Overflow Flag - 1 - 1 - read-write - oneToClear - - - FOF0_0 - No result FIFO 0 overflow has occurred since the last time the flag was cleared. - 0 - - - FOF0_1 - At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. - 0x1 - - - - - RDY1 - Result FIFO1 Ready Flag - 2 - 1 - read-only - - - RDY1_0 - Result FIFO1 data level not above watermark level. - 0 - - - RDY1_1 - Result FIFO1 holding data above watermark level. - 0x1 - - - - - FOF1 - Result FIFO1 Overflow Flag - 3 - 1 - read-write - oneToClear - - - FOF1_0 - No result FIFO1 overflow has occurred since the last time the flag was cleared. - 0 - - - FOF1_1 - At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - 0x1 - - - - - TEXC_INT - Interrupt Flag For High Priority Trigger Exception - 8 - 1 - read-write - oneToClear - - - TEXC_INT_0 - No trigger exceptions have occurred. - 0 - - - TEXC_INT_1 - A trigger exception has occurred and is pending acknowledgement. - 0x1 - - - - - TCOMP_INT - Interrupt Flag For Trigger Completion - 9 - 1 - read-write - oneToClear - - - TCOMP_INT_0 - Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. - 0 - - - TCOMP_INT_1 - Trigger sequence has been completed and all data is stored in the associated FIFO. - 0x1 - - - - - CAL_RDY - Calibration Ready - 10 - 1 - read-only - - - CAL_RDY_0 - Calibration is incomplete or hasn't been ran. - 0 - - - CAL_RDY_1 - The ADC is calibrated. - 0x1 - - - - - ADC_ACTIVE - ADC Active - 11 - 1 - read-only - - - ADC_ACTIVE_0 - The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. - 0 - - - ADC_ACTIVE_1 - The ADC is processing a conversion, running through the power up delay, or servicing a trigger. - 0x1 - - - - - TRGACT - Trigger Active - 16 - 4 - read-only - - - TRGACT_0 - Command (sequence) associated with Trigger 0 currently being executed. - 0 - - - TRGACT_1 - Command (sequence) associated with Trigger 1 currently being executed. - 0x1 - - - TRGACT_2 - Command (sequence) associated with Trigger 2 currently being executed. - 0x2 - - - TRGACT_3 - Command (sequence) from the associated Trigger number is currently being executed. - 0x3 - - - TRGACT_4 - Command (sequence) from the associated Trigger number is currently being executed. - 0x4 - - - TRGACT_5 - Command (sequence) from the associated Trigger number is currently being executed. - 0x5 - - - TRGACT_6 - Command (sequence) from the associated Trigger number is currently being executed. - 0x6 - - - TRGACT_7 - Command (sequence) from the associated Trigger number is currently being executed. - 0x7 - - - TRGACT_8 - Command (sequence) from the associated Trigger number is currently being executed. - 0x8 - - - TRGACT_9 - Command (sequence) from the associated Trigger number is currently being executed. - 0x9 - - - - - CMDACT - Command Active - 24 - 4 - read-only - - - CMDACT_0 - No command is currently in progress. - 0 - - - CMDACT_1 - Command 1 currently being executed. - 0x1 - - - CMDACT_2 - Command 2 currently being executed. - 0x2 - - - CMDACT_3 - Associated command number is currently being executed. - 0x3 - - - CMDACT_4 - Associated command number is currently being executed. - 0x4 - - - CMDACT_5 - Associated command number is currently being executed. - 0x5 - - - CMDACT_6 - Associated command number is currently being executed. - 0x6 - - - CMDACT_7 - Associated command number is currently being executed. - 0x7 - - - CMDACT_8 - Associated command number is currently being executed. - 0x8 - - - CMDACT_9 - Associated command number is currently being executed. - 0x9 - - - - - - - IE - Interrupt Enable Register - 0x18 - 32 - read-write - 0 - 0xFFFFFFFF - - - FWMIE0 - FIFO 0 Watermark Interrupt Enable - 0 - 1 - read-write - - - FWMIE0_0 - FIFO 0 watermark interrupts are not enabled. - 0 - - - FWMIE0_1 - FIFO 0 watermark interrupts are enabled. - 0x1 - - - - - FOFIE0 - Result FIFO 0 Overflow Interrupt Enable - 1 - 1 - read-write - - - FOFIE0_0 - FIFO 0 overflow interrupts are not enabled. - 0 - - - FOFIE0_1 - FIFO 0 overflow interrupts are enabled. - 0x1 - - - - - FWMIE1 - FIFO1 Watermark Interrupt Enable - 2 - 1 - read-write - - - FWMIE1_0 - FIFO1 watermark interrupts are not enabled. - 0 - - - FWMIE1_1 - FIFO1 watermark interrupts are enabled. - 0x1 - - - - - FOFIE1 - Result FIFO1 Overflow Interrupt Enable - 3 - 1 - read-write - - - FOFIE1_0 - No result FIFO1 overflow has occurred since the last time the flag was cleared. - 0 - - - FOFIE1_1 - At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - 0x1 - - - - - TEXC_IE - Trigger Exception Interrupt Enable - 8 - 1 - read-write - - - TEXC_IE_0 - Trigger exception interrupts are disabled. - 0 - - - TEXC_IE_1 - Trigger exception interrupts are enabled. - 0x1 - - - - - TCOMP_IE - Trigger Completion Interrupt Enable - 16 - 16 - read-write - - - TCOMP_IE_0 - Trigger completion interrupts are disabled. - 0 - - - TCOMP_IE_1 - Trigger completion interrupts are enabled for trigger source 0 only. - 0x1 - - - TCOMP_IE_2 - Trigger completion interrupts are enabled for trigger source 1 only. - 0x2 - - - TCOMP_IE_3 - Associated trigger completion interrupts are enabled. - 0x3 - - - TCOMP_IE_4 - Associated trigger completion interrupts are enabled. - 0x4 - - - TCOMP_IE_5 - Associated trigger completion interrupts are enabled. - 0x5 - - - TCOMP_IE_6 - Associated trigger completion interrupts are enabled. - 0x6 - - - TCOMP_IE_7 - Associated trigger completion interrupts are enabled. - 0x7 - - - TCOMP_IE_8 - Associated trigger completion interrupts are enabled. - 0x8 - - - TCOMP_IE_9 - Associated trigger completion interrupts are enabled. - 0x9 - - - TCOMP_IE_65535 - Trigger completion interrupts are enabled for every trigger source. - 0xFFFF - - - - - - - DE - DMA Enable Register - 0x1C - 32 - read-write - 0 - 0xFFFFFFFF - - - FWMDE0 - FIFO 0 Watermark DMA Enable - 0 - 1 - read-write - - - FWMDE0_0 - DMA request disabled. - 0 - - - FWMDE0_1 - DMA request enabled. - 0x1 - - - - - FWMDE1 - FIFO1 Watermark DMA Enable - 1 - 1 - read-write - - - FWMDE1_0 - DMA request disabled. - 0 - - - FWMDE1_1 - DMA request enabled. - 0x1 - - - - - - - CFG - ADC Configuration Register - 0x20 - 32 - read-write - 0x800000 - 0xFFFFFFFF - - - TPRICTRL - ADC trigger priority control - 0 - 2 - read-write - - - TPRICTRL_0 - If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started. - 0 - - - TPRICTRL_1 - If a higher priority trigger is received during command processing, the current command is stopped after after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. - 0x1 - - - TPRICTRL_2 - If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger. - 0x2 - - - - - PWRSEL - Power Configuration Select - 4 - 2 - read-write - - - PWRSEL_0 - Lowest power setting. - 0 - - - PWRSEL_1 - Higher power setting than 0b0. - 0x1 - - - PWRSEL_2 - Higher power setting than 0b1. - 0x2 - - - PWRSEL_3 - Highest power setting. - 0x3 - - - - - REFSEL - Voltage Reference Selection - 6 - 2 - read-write - - - REFSEL_0 - (Default) Option 1 setting. - 0 - - - REFSEL_1 - Option 2 setting. - 0x1 - - - REFSEL_2 - Option 3 setting. - 0x2 - - - - - TRES - Trigger Resume Enable - 8 - 1 - read-write - - - TRES_0 - Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. - 0 - - - TRES_1 - Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. - 0x1 - - - - - TCMDRES - Trigger Command Resume - 9 - 1 - read-write - - - TCMDRES_0 - Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. - 0 - - - TCMDRES_1 - Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. - 0x1 - - - - - HPT_EXDI - High Priority Trigger Exception Disable - 10 - 1 - read-write - - - HPT_EXDI_0 - High priority trigger exceptions are enabled. - 0 - - - HPT_EXDI_1 - High priority trigger exceptions are disabled. - 0x1 - - - - - PUDLY - Power Up Delay - 16 - 8 - read-write - - - PWREN - ADC Analog Pre-Enable - 28 - 1 - read-write - - - PWREN_0 - ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. - 0 - - - PWREN_1 - ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog will remain pre-enabled, and no additional delays will be executed. - 0x1 - - - - - - - PAUSE - ADC Pause Register - 0x24 - 32 - read-write - 0 - 0xFFFFFFFF - - - PAUSEDLY - Pause Delay - 0 - 9 - read-write - - - PAUSEEN - PAUSE Option Enable - 31 - 1 - read-write - - - PAUSEEN_0 - Pause operation disabled - 0 - - - PAUSEEN_1 - Pause operation enabled - 0x1 - - - - - - - SWTRIG - Software Trigger Register - 0x34 - 32 - read-write - 0 - 0xFFFFFFFF - - - SWT0 - Software trigger 0 event - 0 - 1 - read-write - - - SWT0_0 - No trigger 0 event generated. - 0 - - - SWT0_1 - Trigger 0 event generated. - 0x1 - - - - - SWT1 - Software trigger 1 event - 1 - 1 - read-write - - - SWT1_0 - No trigger 1 event generated. - 0 - - - SWT1_1 - Trigger 1 event generated. - 0x1 - - - - - SWT2 - Software trigger 2 event - 2 - 1 - read-write - - - SWT2_0 - No trigger 2 event generated. - 0 - - - SWT2_1 - Trigger 2 event generated. - 0x1 - - - - - SWT3 - Software trigger 3 event - 3 - 1 - read-write - - - SWT3_0 - No trigger 3 event generated. - 0 - - - SWT3_1 - Trigger 3 event generated. - 0x1 - - - - - SWT4 - Software trigger 4 event - 4 - 1 - read-write - - - SWT4_0 - No trigger 4 event generated. - 0 - - - SWT4_1 - Trigger 4 event generated. - 0x1 - - - - - SWT5 - Software trigger 5 event - 5 - 1 - read-write - - - SWT5_0 - No trigger 5 event generated. - 0 - - - SWT5_1 - Trigger 5 event generated. - 0x1 - - - - - SWT6 - Software trigger 6 event - 6 - 1 - read-write - - - SWT6_0 - No trigger 6 event generated. - 0 - - - SWT6_1 - Trigger 6 event generated. - 0x1 - - - - - SWT7 - Software trigger 7 event - 7 - 1 - read-write - - - SWT7_0 - No trigger 7 event generated. - 0 - - - SWT7_1 - Trigger 7 event generated. - 0x1 - - - - - SWT8 - Software trigger 8 event - 8 - 1 - read-write - - - SWT8_0 - No trigger 8 event generated. - 0 - - - SWT8_1 - Trigger 8 event generated. - 0x1 - - - - - SWT9 - Software trigger 9 event - 9 - 1 - read-write - - - SWT9_0 - No trigger 9 event generated. - 0 - - - SWT9_1 - Trigger 9 event generated. - 0x1 - - - - - SWT10 - Software trigger 10 event - 10 - 1 - read-write - - - SWT10_0 - No trigger 10 event generated. - 0 - - - SWT10_1 - Trigger 10 event generated. - 0x1 - - - - - SWT11 - Software trigger 11 event - 11 - 1 - read-write - - - SWT11_0 - No trigger 11 event generated. - 0 - - - SWT11_1 - Trigger 11 event generated. - 0x1 - - - - - SWT12 - Software trigger 12 event - 12 - 1 - read-write - - - SWT12_0 - No trigger 12 event generated. - 0 - - - SWT12_1 - Trigger 12 event generated. - 0x1 - - - - - SWT13 - Software trigger 13 event - 13 - 1 - read-write - - - SWT13_0 - No trigger 13 event generated. - 0 - - - SWT13_1 - Trigger 13 event generated. - 0x1 - - - - - SWT14 - Software trigger 14 event - 14 - 1 - read-write - - - SWT14_0 - No trigger 14 event generated. - 0 - - - SWT14_1 - Trigger 14 event generated. - 0x1 - - - - - SWT15 - Software trigger 15 event - 15 - 1 - read-write - - - SWT15_0 - No trigger 15 event generated. - 0 - - - SWT15_1 - Trigger 15 event generated. - 0x1 - - - - - - - TSTAT - Trigger Status Register - 0x38 - 32 - read-write - 0 - 0xFFFFFFFF - - - TEXC_NUM - Trigger Exception Number - 0 - 16 - read-write - oneToClear - - - TEXC_NUM_0 - No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. - 0 - - - TEXC_NUM_1 - Trigger 0 has been interrupted by a high priority exception. - 0x1 - - - TEXC_NUM_2 - Trigger 1 has been interrupted by a high priority exception. - 0x2 - - - TEXC_NUM_3 - Associated trigger sequence has interrupted by a high priority exception. - 0x3 - - - TEXC_NUM_4 - Associated trigger sequence has interrupted by a high priority exception. - 0x4 - - - TEXC_NUM_5 - Associated trigger sequence has interrupted by a high priority exception. - 0x5 - - - TEXC_NUM_6 - Associated trigger sequence has interrupted by a high priority exception. - 0x6 - - - TEXC_NUM_7 - Associated trigger sequence has interrupted by a high priority exception. - 0x7 - - - TEXC_NUM_8 - Associated trigger sequence has interrupted by a high priority exception. - 0x8 - - - TEXC_NUM_9 - Associated trigger sequence has interrupted by a high priority exception. - 0x9 - - - TEXC_NUM_65535 - Every trigger sequence has been interrupted by a high priority exception. - 0xFFFF - - - - - TCOMP_FLAG - Trigger Completion Flag - 16 - 16 - read-write - oneToClear - - - TCOMP_FLAG_0 - No triggers have been completed. Trigger completion interrupts are disabled. - 0 - - - TCOMP_FLAG_1 - Trigger 0 has been completed and triger 0 has enabled completion interrupts. - 0x1 - - - TCOMP_FLAG_2 - Trigger 1 has been completed and triger 1 has enabled completion interrupts. - 0x2 - - - TCOMP_FLAG_3 - Associated trigger sequence has completed and has enabled completion interrupts. - 0x3 - - - TCOMP_FLAG_4 - Associated trigger sequence has completed and has enabled completion interrupts. - 0x4 - - - TCOMP_FLAG_5 - Associated trigger sequence has completed and has enabled completion interrupts. - 0x5 - - - TCOMP_FLAG_6 - Associated trigger sequence has completed and has enabled completion interrupts. - 0x6 - - - TCOMP_FLAG_7 - Associated trigger sequence has completed and has enabled completion interrupts. - 0x7 - - - TCOMP_FLAG_8 - Associated trigger sequence has completed and has enabled completion interrupts. - 0x8 - - - TCOMP_FLAG_9 - Associated trigger sequence has completed and has enabled completion interrupts. - 0x9 - - - TCOMP_FLAG_65535 - Every trigger sequence has been completed and every trigger has enabled completion interrupts. - 0xFFFF - - - - - - - OFSTRIM - ADC Offset Trim Register - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - OFSTRIM_A - Trim for offset - 0 - 5 - read-write - - - OFSTRIM_B - Trim for offset - 16 - 5 - read-write - - - - - 16 - 0x4 - TCTRL[%s] - Trigger Control Register - 0xA0 - 32 - read-write - 0 - 0xFFFFFFFF - - - HTEN - Trigger enable - 0 - 1 - read-write - - - HTEN_0 - Hardware trigger source disabled - 0 - - - HTEN_1 - Hardware trigger source enabled - 0x1 - - - - - FIFO_SEL_A - SAR Result Destination For Channel A - 1 - 1 - read-write - - - FIFO_SEL_A_0 - Result written to FIFO 0 - 0 - - - FIFO_SEL_A_1 - Result written to FIFO 1 - 0x1 - - - - - FIFO_SEL_B - SAR Result Destination For Channel B - 2 - 1 - read-write - - - FIFO_SEL_B_0 - Result written to FIFO 0 - 0 - - - FIFO_SEL_B_1 - Result written to FIFO 1 - 0x1 - - - - - TPRI - Trigger priority setting - 8 - 4 - read-write - - - TPRI_0 - Set to highest priority, Level 1 - 0 - - - TPRI_1 - Set to corresponding priority level - 0x1 - - - TPRI_2 - Set to corresponding priority level - 0x2 - - - TPRI_3 - Set to corresponding priority level - 0x3 - - - TPRI_4 - Set to corresponding priority level - 0x4 - - - TPRI_5 - Set to corresponding priority level - 0x5 - - - TPRI_6 - Set to corresponding priority level - 0x6 - - - TPRI_7 - Set to corresponding priority level - 0x7 - - - TPRI_8 - Set to corresponding priority level - 0x8 - - - TPRI_9 - Set to corresponding priority level - 0x9 - - - TPRI_15 - Set to lowest priority, Level 16 - 0xF - - - - - RSYNC - Trigger Resync - 15 - 1 - read-write - - - TDLY - Trigger delay select - 16 - 4 - read-write - - - TCMD - Trigger command select - 24 - 4 - read-write - - - TCMD_0 - Not a valid selection from the command buffer. Trigger event is ignored. - 0 - - - TCMD_1 - CMD1 is executed - 0x1 - - - TCMD_2 - Corresponding CMD is executed - 0x2 - - - TCMD_3 - Corresponding CMD is executed - 0x3 - - - TCMD_4 - Corresponding CMD is executed - 0x4 - - - TCMD_5 - Corresponding CMD is executed - 0x5 - - - TCMD_6 - Corresponding CMD is executed - 0x6 - - - TCMD_7 - Corresponding CMD is executed - 0x7 - - - TCMD_8 - Corresponding CMD is executed - 0x8 - - - TCMD_9 - Corresponding CMD is executed - 0x9 - - - TCMD_15 - CMD15 is executed - 0xF - - - - - - - 2 - 0x4 - FCTRL[%s] - FIFO Control Register - 0xE0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FCOUNT - Result FIFO counter - 0 - 5 - read-only - - - FWMARK - Watermark level selection - 16 - 4 - read-write - - - - - 2 - 0x4 - GCC[%s] - Gain Calibration Control - 0xF0 - 32 - read-only - 0 - 0xFFFFFFFF - - - GAIN_CAL - Gain Calibration Value - 0 - 16 - read-only - - - RDY - Gain Calibration Value Valid - 24 - 1 - read-only - - - RDY_0 - The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. - 0 - - - RDY_1 - The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. - 0x1 - - - - - - - 2 - 0x4 - GCR[%s] - Gain Calculation Result - 0xF8 - 32 - read-write - 0 - 0xFFFFFFFF - - - GCALR - Gain Calculation Result - 0 - 16 - read-write - - - RDY - Gain Calculation Ready - 24 - 1 - read-write - - - RDY_0 - The gain offset calculation value is invalid. - 0 - - - RDY_1 - The gain calibration value is valid. - 0x1 - - - - - - - CMDL1 - ADC Command Low Buffer Register - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH1 - ADC Command High Buffer Register - 0x104 - 32 - read-write - 0 - 0xFFFFFFFF - - - CMPEN - Compare Function Enable - 0 - 2 - read-write - - - CMPEN_0 - Compare disabled. - 0 - - - CMPEN_2 - Compare enabled. Store on true. - 0x2 - - - CMPEN_3 - Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - 0x3 - - - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL2 - ADC Command Low Buffer Register - 0x108 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH2 - ADC Command High Buffer Register - 0x10C - 32 - read-write - 0 - 0xFFFFFFFF - - - CMPEN - Compare Function Enable - 0 - 2 - read-write - - - CMPEN_0 - Compare disabled. - 0 - - - CMPEN_2 - Compare enabled. Store on true. - 0x2 - - - CMPEN_3 - Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - 0x3 - - - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL3 - ADC Command Low Buffer Register - 0x110 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH3 - ADC Command High Buffer Register - 0x114 - 32 - read-write - 0 - 0xFFFFFFFF - - - CMPEN - Compare Function Enable - 0 - 2 - read-write - - - CMPEN_0 - Compare disabled. - 0 - - - CMPEN_2 - Compare enabled. Store on true. - 0x2 - - - CMPEN_3 - Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - 0x3 - - - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL4 - ADC Command Low Buffer Register - 0x118 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH4 - ADC Command High Buffer Register - 0x11C - 32 - read-write - 0 - 0xFFFFFFFF - - - CMPEN - Compare Function Enable - 0 - 2 - read-write - - - CMPEN_0 - Compare disabled. - 0 - - - CMPEN_2 - Compare enabled. Store on true. - 0x2 - - - CMPEN_3 - Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - 0x3 - - - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL5 - ADC Command Low Buffer Register - 0x120 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH5 - ADC Command High Buffer Register - 0x124 - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL6 - ADC Command Low Buffer Register - 0x128 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH6 - ADC Command High Buffer Register - 0x12C - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL7 - ADC Command Low Buffer Register - 0x130 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH7 - ADC Command High Buffer Register - 0x134 - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL8 - ADC Command Low Buffer Register - 0x138 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH8 - ADC Command High Buffer Register - 0x13C - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL9 - ADC Command Low Buffer Register - 0x140 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH9 - ADC Command High Buffer Register - 0x144 - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL10 - ADC Command Low Buffer Register - 0x148 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH10 - ADC Command High Buffer Register - 0x14C - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL11 - ADC Command Low Buffer Register - 0x150 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH11 - ADC Command High Buffer Register - 0x154 - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL12 - ADC Command Low Buffer Register - 0x158 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH12 - ADC Command High Buffer Register - 0x15C - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL13 - ADC Command Low Buffer Register - 0x160 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH13 - ADC Command High Buffer Register - 0x164 - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL14 - ADC Command Low Buffer Register - 0x168 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH14 - ADC Command High Buffer Register - 0x16C - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL15 - ADC Command Low Buffer Register - 0x170 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH15 - ADC Command High Buffer Register - 0x174 - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - 4 - 0x4 - 1,2,3,4 - CV%s - Compare Value Register - 0x200 - 32 - read-write - 0 - 0xFFFFFFFF - - - CVL - Compare Value Low. - 0 - 16 - read-write - - - CVH - Compare Value High. - 16 - 16 - read-write - - - - - 2 - 0x4 - RESFIFO[%s] - ADC Data Result FIFO Register - 0x300 - 32 - read-only - 0 - 0xFFFFFFFF - - - D - Data result - 0 - 16 - read-only - - - TSRC - Trigger Source - 16 - 4 - read-only - - - TSRC_0 - Trigger source 0 initiated this conversion. - 0 - - - TSRC_1 - Trigger source 1 initiated this conversion. - 0x1 - - - TSRC_2 - Corresponding trigger source initiated this conversion. - 0x2 - - - TSRC_3 - Corresponding trigger source initiated this conversion. - 0x3 - - - TSRC_4 - Corresponding trigger source initiated this conversion. - 0x4 - - - TSRC_5 - Corresponding trigger source initiated this conversion. - 0x5 - - - TSRC_6 - Corresponding trigger source initiated this conversion. - 0x6 - - - TSRC_7 - Corresponding trigger source initiated this conversion. - 0x7 - - - TSRC_8 - Corresponding trigger source initiated this conversion. - 0x8 - - - TSRC_9 - Corresponding trigger source initiated this conversion. - 0x9 - - - TSRC_15 - Trigger source 15 initiated this conversion. - 0xF - - - - - LOOPCNT - Loop count value - 20 - 4 - read-only - - - LOOPCNT_0 - Result is from initial conversion in command. - 0 - - - LOOPCNT_1 - Result is from second conversion in command. - 0x1 - - - LOOPCNT_2 - Result is from LOOPCNT+1 conversion in command. - 0x2 - - - LOOPCNT_3 - Result is from LOOPCNT+1 conversion in command. - 0x3 - - - LOOPCNT_4 - Result is from LOOPCNT+1 conversion in command. - 0x4 - - - LOOPCNT_5 - Result is from LOOPCNT+1 conversion in command. - 0x5 - - - LOOPCNT_6 - Result is from LOOPCNT+1 conversion in command. - 0x6 - - - LOOPCNT_7 - Result is from LOOPCNT+1 conversion in command. - 0x7 - - - LOOPCNT_8 - Result is from LOOPCNT+1 conversion in command. - 0x8 - - - LOOPCNT_9 - Result is from LOOPCNT+1 conversion in command. - 0x9 - - - LOOPCNT_15 - Result is from 16th conversion in command. - 0xF - - - - - CMDSRC - Command Buffer Source - 24 - 4 - read-only - - - CMDSRC_0 - Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer. - 0 - - - CMDSRC_1 - CMD1 buffer used as control settings for this conversion. - 0x1 - - - CMDSRC_2 - Corresponding command buffer used as control settings for this conversion. - 0x2 - - - CMDSRC_3 - Corresponding command buffer used as control settings for this conversion. - 0x3 - - - CMDSRC_4 - Corresponding command buffer used as control settings for this conversion. - 0x4 - - - CMDSRC_5 - Corresponding command buffer used as control settings for this conversion. - 0x5 - - - CMDSRC_6 - Corresponding command buffer used as control settings for this conversion. - 0x6 - - - CMDSRC_7 - Corresponding command buffer used as control settings for this conversion. - 0x7 - - - CMDSRC_8 - Corresponding command buffer used as control settings for this conversion. - 0x8 - - - CMDSRC_9 - Corresponding command buffer used as control settings for this conversion. - 0x9 - - - CMDSRC_15 - CMD15 buffer used as control settings for this conversion. - 0xF - - - - - VALID - FIFO entry is valid - 31 - 1 - read-only - - - VALID_0 - FIFO is empty. Discard any read from RESFIFO. - 0 - - - VALID_1 - FIFO record read from RESFIFO is valid. - 0x1 - - - - - - - 33 - 0x4 - CAL_GAR[%s] - Calibration General A-Side Registers - 0x400 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAL_GAR_VAL - Calibration General A Side Register Element - 0 - 16 - read-write - - - - - 33 - 0x4 - CAL_GBR[%s] - Calibration General B-Side Registers - 0x500 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAL_GBR_VAL - Calibration General B Side Register Element - 0 - 16 - read-write - - - - - TST - ADC Test Register - 0xFFC - 32 - read-write - 0 - 0xFFFFFFFF - - - CST_LONG - Calibration Sample Time Long - 0 - 1 - read-write - - - CST_LONG_0 - Normal sample time. Minimum sample time of 3 ADCK cycles. - 0 - - - CST_LONG_1 - Increased sample time. 67 ADCK cycles total sample time. - 0x1 - - - - - FOFFM - Force M-side positive offset - 8 - 1 - read-write - - - FOFFM_0 - Normal operation. No forced offset. - 0 - - - FOFFM_1 - Test configuration. Forced positive offset on MDAC. - 0x1 - - - - - FOFFP - Force P-side positive offset - 9 - 1 - read-write - - - FOFFP_0 - Normal operation. No forced offset. - 0 - - - FOFFP_1 - Test configuration. Forced positive offset on PDAC. - 0x1 - - - - - FOFFM2 - Force M-side negative offset - 10 - 1 - read-write - - - FOFFM2_0 - Normal operation. No forced offset. - 0 - - - FOFFM2_1 - Test configuration. Forced negative offset on MDAC. - 0x1 - - - - - FOFFP2 - Force P-side negative offset - 11 - 1 - read-write - - - FOFFP2_0 - Normal operation. No forced offset. - 0 - - - FOFFP2_1 - Test configuration. Forced negative offset on PDAC. - 0x1 - - - - - TESTEN - Enable test configuration - 23 - 1 - read-write - - - TESTEN_0 - Normal operation. Test configuration not enabled. - 0 - - - TESTEN_1 - Hardware BIST Test in progress. - 0x1 - - - - - - - - - USBFSH - USB0 Full-speed Host controller - USBFSH - 0x400A2000 - - 0 - 0x60 - registers - - - USB0_NEEDCLK - 27 - - - USB0 - 28 - - - - HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) - 0 - 32 - read-only - 0x10 - 0xFF - - - REV - Revision. - 0 - 8 - read-only - - - - - HCCONTROL - Defines the operating modes of the HC - 0x4 - 32 - read-write - 0 - 0x7FF - - - CBSR - ControlBulkServiceRatio. - 0 - 2 - read-write - - - PLE - PeriodicListEnable. - 2 - 1 - read-write - - - IE - IsochronousEnable. - 3 - 1 - read-write - - - CLE - ControlListEnable. - 4 - 1 - read-write - - - BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. - 5 - 1 - read-write - - - HCFS - HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin 1 ms later. - 6 - 2 - read-write - - - IR - InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. - 8 - 1 - read-write - - - RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling. - 9 - 1 - read-write - - - RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature upon the detection of upstream resume signaling. - 10 - 1 - read-write - - - - - HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) - 0x8 - 32 - read-write - 0 - 0xCF - - - HCR - HostControllerReset This bit is set by HCD to initiate a software reset of HC. - 0 - 1 - read-write - - - CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. - 1 - 1 - read-write - - - BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. - 2 - 1 - read-write - - - OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC. - 3 - 1 - read-write - - - SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error. - 6 - 2 - read-write - - - - - HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits - 0xC - 32 - read-write - 0 - 0xFFFFFC7F - - - SO - SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and after the update of HccaFrameNumber. - 0 - 1 - read-write - - - WDH - WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead. - 1 - 1 - read-write - - - SF - StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. - 2 - 1 - read-write - - - RD - ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling. - 3 - 1 - read-write - - - UE - UnrecoverableError This bit is set when HC detects a system error not related to USB. - 4 - 1 - read-write - - - FNO - FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value, from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated. - 5 - 1 - read-write - - - RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed. - 6 - 1 - read-write - - - OC - OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus. - 10 - 22 - read-write - - - - - HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt - 0x10 - 32 - read-write - 0 - 0xC000007F - - - SO - Scheduling Overrun interrupt. - 0 - 1 - read-write - - - WDH - HcDoneHead Writeback interrupt. - 1 - 1 - read-write - - - SF - Start of Frame interrupt. - 2 - 1 - read-write - - - RD - Resume Detect interrupt. - 3 - 1 - read-write - - - UE - Unrecoverable Error interrupt. - 4 - 1 - read-write - - - FNO - Frame Number Overflow interrupt. - 5 - 1 - read-write - - - RHSC - Root Hub Status Change interrupt. - 6 - 1 - read-write - - - OC - Ownership Change interrupt. - 30 - 1 - read-write - - - MIE - Master Interrupt Enable. - 31 - 1 - read-write - - - - - HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt - 0x14 - 32 - read-write - 0 - 0xC000007F - - - SO - Scheduling Overrun interrupt. - 0 - 1 - read-write - - - WDH - HcDoneHead Writeback interrupt. - 1 - 1 - read-write - - - SF - Start of Frame interrupt. - 2 - 1 - read-write - - - RD - Resume Detect interrupt. - 3 - 1 - read-write - - - UE - Unrecoverable Error interrupt. - 4 - 1 - read-write - - - FNO - Frame Number Overflow interrupt. - 5 - 1 - read-write - - - RHSC - Root Hub Status Change interrupt. - 6 - 1 - read-write - - - OC - Ownership Change interrupt. - 30 - 1 - read-write - - - MIE - A 0 written to this field is ignored by HC. - 31 - 1 - read-write - - - - - HCHCCA - Contains the physical address of the host controller communication area - 0x18 - 32 - read-write - 0 - 0xFFFFFF00 - - - HCCA - Base address of the Host Controller Communication Area. - 8 - 24 - read-write - - - - - HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor - 0x1C - 32 - read-write - 0 - 0xFFFFFFF0 - - - PCED - The content of this register is updated by HC after a periodic ED is processed. - 4 - 28 - read-only - - - - - HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list - 0x20 - 32 - read-write - 0 - 0xFFFFFFF0 - - - CHED - HC traverses the Control list starting with the HcControlHeadED pointer. - 4 - 28 - read-write - - - - - HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list - 0x24 - 32 - read-write - 0 - 0xFFFFFFF0 - - - CCED - ControlCurrentED. - 4 - 28 - read-write - - - - - HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list - 0x28 - 32 - read-write - 0 - 0xFFFFFFF0 - - - BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer. - 4 - 28 - read-write - - - - - HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list - 0x2C - 32 - read-write - 0 - 0xFFFFFFF0 - - - BCED - BulkCurrentED This is advanced to the next ED after the HC has served the current one. - 4 - 28 - read-write - - - - - HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue - 0x30 - 32 - read-write - 0 - 0xFFFFFFF0 - - - DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. - 4 - 28 - read-only - - - - - HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun - 0x34 - 32 - read-write - 0x2EDF - 0xFFFF3FFF - - - FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times. - 0 - 14 - read-write - - - FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame. - 16 - 15 - read-write - - - FIT - FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval. - 31 - 1 - read-write - - - - - HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame - 0x38 - 32 - read-write - 0 - 0x80003FFF - - - FR - FrameRemaining This counter is decremented at each bit time. - 0 - 14 - read-only - - - FRT - FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0. - 31 - 1 - read-only - - - - - HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD - 0x3C - 32 - read-write - 0 - 0xFFFF - - - FN - FrameNumber This is incremented when HcFmRemaining is re-loaded. - 0 - 16 - read-only - - - - - HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list - 0x40 - 32 - read-write - 0 - 0x3FFF - - - PS - PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization. - 0 - 14 - read-write - - - - - HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF - 0x44 - 32 - read-write - 0x628 - 0xFFF - - - LST - LSThreshold This field contains a value which is compared to the FrameRemaining field prior to initiating a Low Speed transaction. - 0 - 12 - read-write - - - - - HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub - 0x48 - 32 - read-write - 0xFF000902 - 0xFF001FFF - - - NDP - NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub. - 0 - 8 - read-write - - - PSM - PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled. - 8 - 1 - read-write - - - NPS - NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered. - 9 - 1 - read-write - - - DT - DeviceType This bit specifies that the root hub is not a compound device. - 10 - 1 - read-write - - - OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported. - 11 - 1 - read-write - - - NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported. - 12 - 1 - read-write - - - POTPGT - PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before accessing a powered-on port of the root hub. - 24 - 8 - read-write - - - - - HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub - 0x4C - 32 - read-write - 0 - 0x3FFFFFFF - - - DR - DeviceRemovable Each bit is dedicated to a port of the Root Hub. - 0 - 16 - read-write - - - PPCM - PortPowerControlMask Each bit indicates if a port is affected by a global power control command when PowerSwitchingMode is set. - 16 - 16 - read-write - - - - - HCRHSTATUS - This register is divided into two parts - 0x50 - 32 - read-write - 0 - 0x80038003 - - - LPS - (read) LocalPowerStatus The Root Hub does not support the local power status feature; thus, this bit is always read as 0. - 0 - 1 - read-write - - - OCI - OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented. - 1 - 1 - read-write - - - DRWE - (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected interrupt. - 15 - 1 - read-write - - - LPSC - (read) LocalPowerStatusChange The root hub does not support the local power status feature. - 16 - 1 - read-write - - - OCIC - OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register. - 17 - 1 - read-write - - - CRWE - (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable. - 31 - 1 - read-write - - - - - HCRHPORTSTATUS - Controls and reports the port events on a per-port basis - 0x54 - 32 - read-write - 0 - 0x1F031F - - - CCS - (read) CurrentConnectStatus This bit reflects the current state of the downstream port. - 0 - 1 - read-write - - - PES - (read) PortEnableStatus This bit indicates whether the port is enabled or disabled. - 1 - 1 - read-write - - - PSS - (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence. - 2 - 1 - read-write - - - POCI - (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in such a way that overcurrent conditions are reported on a per-port basis. - 3 - 1 - read-write - - - PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. - 4 - 1 - read-write - - - PPS - (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type of power switching implemented. - 8 - 1 - read-write - - - LSDA - (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. - 9 - 1 - read-write - - - CSC - ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. - 16 - 1 - read-write - - - PESC - PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared. - 17 - 1 - read-write - - - PSSC - PortSuspendStatusChange This bit is set when the full resume sequence is completed. - 18 - 1 - read-write - - - OCIC - PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis. - 19 - 1 - read-write - - - PRSC - PortResetStatusChange This bit is set at the end of the 10 ms port reset signal. - 20 - 1 - read-write - - - - - PORTMODE - Controls the port if it is attached to the host block or the device block - 0x5C - 32 - read-write - 0 - 0x10101 - - - ID - Port ID pin value. - 0 - 1 - read-write - - - ID_EN - Port ID pin pull-up enable. - 8 - 1 - read-write - - - DEV_ENABLE - 1: device 0: host. - 16 - 1 - read-write - - - - - - - USBHSH - USB1 High-speed Host Controller - USBHSH - 0x400A3000 - - 0 - 0x54 - registers - - - USB1 - 47 - - - USB1_NEEDCLK - 48 - - - - CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block - 0 - 32 - read-only - 0x1010010 - 0xFFFF00FF - - - CAPLENGTH - Capability Length: This is used as an offset. - 0 - 8 - read-only - - - CHIPID - Chip identification: indicates major and minor revision of the IP: [31:24] = Major revision [23:16] = Minor revision Major revisions used: 0x01: USB2. - 16 - 16 - read-only - - - - - HCSPARAMS - Host Controller Structural Parameters - 0x4 - 32 - read-only - 0x10011 - 0x1001F - - - N_PORTS - This register specifies the number of physical downstream ports implemented on this host controller. - 0 - 4 - read-only - - - PPC - This field indicates whether the host controller implementation includes port power control. - 4 - 1 - read-only - - - P_INDICATOR - This bit indicates whether the ports support port indicator control. - 16 - 1 - read-only - - - - - FLADJ_FRINDEX - Frame Length Adjustment - 0xC - 32 - read-write - 0x20 - 0x3FFF003F - - - FLADJ - Frame Length Timing Value. - 0 - 6 - read-write - - - FRINDEX - Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet. - 16 - 14 - read-write - - - - - ATLPTD - Memory base address where ATL PTD0 is stored - 0x10 - 32 - read-write - 0 - 0xFFFFFFF0 - - - ATL_CUR - This indicates the current PTD that is used by the hardware when it is processing the ATL list. - 4 - 5 - read-write - - - ATL_BASE - Base address to be used by the hardware to find the start of the ATL list. - 9 - 23 - read-write - - - - - ISOPTD - Memory base address where ISO PTD0 is stored - 0x14 - 32 - read-write - 0 - 0xFFFFFFE0 - - - ISO_FIRST - This indicates the first PTD that is used by the hardware when it is processing the ISO list. - 5 - 5 - read-write - - - ISO_BASE - Base address to be used by the hardware to find the start of the ISO list. - 10 - 22 - read-write - - - - - INTPTD - Memory base address where INT PTD0 is stored - 0x18 - 32 - read-write - 0 - 0xFFFFFFE0 - - - INT_FIRST - This indicates the first PTD that is used by the hardware when it is processing the INT list. - 5 - 5 - read-write - - - INT_BASE - Base address to be used by the hardware to find the start of the INT list. - 10 - 22 - read-write - - - - - DATAPAYLOAD - Memory base address that indicates the start of the data payload buffers - 0x1C - 32 - read-write - 0 - 0xFFFF0000 - - - DAT_BASE - Base address to be used by the hardware to find the start of the data payload section. - 16 - 16 - read-write - - - - - USBCMD - USB Command register - 0x20 - 32 - read-write - 0 - 0x1F00078F - - - RS - Run/Stop: 1b = Run. - 0 - 1 - read-write - - - HCRESET - Host Controller Reset: This control bit is used by the software to reset the host controller. - 1 - 1 - read-write - - - FLS - Frame List Size: This field specifies the size of the frame list. - 2 - 2 - read-write - - - LHCR - Light Host Controller Reset: This bit allows the driver software to reset the host controller without affecting the state of the ports. - 7 - 1 - read-write - - - ATL_EN - ATL List enabled. - 8 - 1 - read-write - - - ISO_EN - ISO List enabled. - 9 - 1 - read-write - - - INT_EN - INT List enabled. - 10 - 1 - read-write - - - - - USBSTS - USB Interrupt Status register - 0x24 - 32 - read-write - 0 - 0xF000C - - - PCD - Port Change Detect: The host controller sets this bit to logic 1 when any port has a change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a result of a J-K transition detected on a suspended port. - 2 - 1 - read-write - - - FLR - Frame List Rollover: The host controller sets this bit to logic 1 when the frame list index rolls over its maximum value to 0. - 3 - 1 - read-write - - - ATL_IRQ - ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed. - 16 - 1 - read-write - - - ISO_IRQ - ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed. - 17 - 1 - read-write - - - INT_IRQ - INT IRQ: Indicates that an INT PTD (with I-bit set) was completed. - 18 - 1 - read-write - - - SOF_IRQ - SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set. - 19 - 1 - read-write - - - - - USBINTR - USB Interrupt Enable register - 0x28 - 32 - read-write - 0 - 0xF000C - - - PCDE - Port Change Detect Interrupt Enable: 1: enable 0: disable. - 2 - 1 - read-write - - - FLRE - Frame List Rollover Interrupt Enable: 1: enable 0: disable. - 3 - 1 - read-write - - - ATL_IRQ_E - ATL IRQ Enable bit: 1: enable 0: disable. - 16 - 1 - read-write - - - ISO_IRQ_E - ISO IRQ Enable bit: 1: enable 0: disable. - 17 - 1 - read-write - - - INT_IRQ_E - INT IRQ Enable bit: 1: enable 0: disable. - 18 - 1 - read-write - - - SOF_E - SOF Interrupt Enable bit: 1: enable 0: disable. - 19 - 1 - read-write - - - - - PORTSC1 - Port Status and Control register - 0x2C - 32 - read-write - 0 - 0xFFFFDFFF - - - CCS - Current Connect Status: Logic 1 indicates a device is present on the port. - 0 - 1 - read-write - - - CSC - Connect Status Change: Logic 1 means that the value of CCS has changed. - 1 - 1 - read-write - - - PED - Port Enabled/Disabled. - 2 - 1 - read-write - - - PEDC - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed. - 3 - 1 - read-write - - - OCA - Over-current active: Logic 1 means that this port has an over-current condition. - 4 - 1 - read-write - - - OCC - Over-current change: Logic 1 means that the value of OCA has changed. - 5 - 1 - read-write - - - FPR - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port. - 6 - 1 - read-write - - - SUSP - Suspend: Logic 1 means port is in the suspend state. - 7 - 1 - read-write - - - PR - Port Reset: Logic 1 means the port is in the reset state. - 8 - 1 - read-write - - - LS - Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. - 10 - 2 - read-only - - - PP - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register. - 12 - 1 - read-write - - - PIC - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is logic 0. - 14 - 2 - read-write - - - PTC - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value. - 16 - 4 - read-write - - - PSPD - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved. - 20 - 2 - read-write - - - WOO - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to overcurrent conditions as wake-up events. - 22 - 1 - read-write - - - - - ATLPTDD - Done map for each ATL PTD - 0x30 - 32 - read-write - 0 - 0xFFFFFFFF - - - ATL_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - 0 - 32 - read-write - - - - - ATLPTDS - Skip map for each ATL PTD - 0x34 - 32 - read-write - 0 - 0xFFFFFFFF - - - ATL_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be skipped, independent of the V bit setting. - 0 - 32 - read-write - - - - - ISOPTDD - Done map for each ISO PTD - 0x38 - 32 - read-write - 0 - 0xFFFFFFFF - - - ISO_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - 0 - 32 - read-write - - - - - ISOPTDS - Skip map for each ISO PTD - 0x3C - 32 - read-write - 0 - 0xFFFFFFFF - - - ISO_SKIP - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - 0 - 32 - read-write - - - - - INTPTDD - Done map for each INT PTD - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - INT_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - 0 - 32 - read-write - - - - - INTPTDS - Skip map for each INT PTD - 0x44 - 32 - read-write - 0 - 0xFFFFFFFF - - - INT_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be skipped, independent of the V bit setting. - 0 - 32 - read-write - - - - - LASTPTD - Marks the last PTD in the list for ISO, INT and ATL - 0x48 - 32 - read-write - 0 - 0x1F1F1F - - - ATL_LAST - If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed. - 0 - 5 - read-write - - - ISO_LAST - This indicates the last PTD in the ISO list. - 8 - 5 - read-write - - - INT_LAST - This indicates the last PTD in the INT list. - 16 - 5 - read-write - - - - - PORTMODE - Controls the port if it is attached to the host block or the device block - 0x50 - 32 - read-write - 0x40000 - 0xD0101 - - - DEV_ENABLE - If this bit is set to one, one of the ports will behave as a USB device. - 16 - 1 - read-write - - - SW_CTRL_PDCOM - This bit indicates if the PHY power-down input is controlled by software or by hardware. - 18 - 1 - read-write - - - SW_PDCOM - This bit is only used when SW_CTRL_PDCOM is set to 1b. - 19 - 1 - read-write - - - - - - - HASHCRYPT - Hash-Crypt peripheral - HASHCRYPT - 0x400A4000 - - 0 - 0xA0 - registers - - - HASHCRYPT - 54 - - - - CTRL - Control register to enable and operate Hash and Crypto - 0 - 32 - read-write - 0 - 0x3317 - - - Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if specific modes beyond SHA1 and SHA2-256 are available. - 0 - 3 - read-write - - - DISABLED - Disabled - 0 - - - SHA1 - SHA1 is enabled - 0x1 - - - SHA2_256 - SHA2-256 is enabled - 0x2 - - - AES - AES if available (see also CRYPTCFG register for more controls) - 0x4 - - - ICB_AES - ICB-AES if available (see also CRYPTCFG register for more controls) - 0x5 - - - - - New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING Status bit will clear for a cycle during the initialization from New=1. - 4 - 1 - write-only - - - START - Starts a new Hash/Crypto and initializes the Digest/Result. - 0x1 - - - - - DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words and then will process the Hash. If Cryptographic, it will load as many words as needed, including key if not already loaded. It will then request again. Normal model is that the DMA interrupts the processor when its length expires. Note that if the processor will write the key and optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be expected to load those for the 1st block (when needed). - 8 - 1 - read-write - - - NOT_USED - DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used. - 0 - - - PUSH - DMA will push in the data. - 0x1 - - - - - DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the DMA has to know to switch direction and the locations. This can be used for crypto uses. - 9 - 1 - read-write - - - NOTUSED - DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. - 0 - - - - - HASHSWPB - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For cryptographic swapping, see the CRYPTCFG register. - 12 - 1 - read-write - - - - - STATUS - Indicates status of Hash peripheral. - 0x4 - 32 - read-write - 0 - 0x3F0037 - - - WAITING - If 1, the block is waiting for more data to process. - 0 - 1 - read-only - - - NOT_WAITING - Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set if IsLast is set nor will it set until at least 1 word is read of the output. - 0 - - - WAITING - Waiting for data to be written in (16 words) - 0x1 - - - - - DIGEST - For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block already started. For Cryptographic uses, this will be set for each block processed, indicating OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared when any data is written, when New is written, for Cryptographic uses when the last word is read out, or when the block is disabled. - 1 - 1 - read-only - - - NOT_READY - No Digest is ready - 0 - - - READY - Digest is ready. Application may read it or may write more data - 0x1 - - - - - ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT field will indicate which block it was on. - 2 - 1 - read-write - oneToClear - - - NO_ERROR - No error. - 0 - - - ERROR - An error occurred since last cleared (written 1 to clear). - 0x1 - - - - - NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING) - 4 - 1 - read-only - - - NOT_NEED - No Key is needed and writes will not be treated as Key - 0 - - - NEED - Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. - 0x1 - - - - - NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING) - 5 - 1 - read-only - - - NOT_NEED - No IV/Nonce is needed, either because written already or because not needed. - 0 - - - NEED - IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. - 0x1 - - - - - ICBIDX - If ICB-AES is selected, then reads as the ICB index count based on ICBSTRM (from CRYPTCFG). That is, if 3 bits of ICBSTRM, then this will count from 0 to 7 and then back to 0. On 0, it has to compute the full ICB, quicker when not 0. - 16 - 6 - read-only - - - - - INTENSET - Write 1 to enable interrupts; reads back with which are set. - 0x8 - 32 - read-write - 0 - 0x7 - - - WAITING - Indicates if should interrupt when waiting for data input. - 0 - 1 - read-write - - - NO_INTERRUPT - Will not interrupt when waiting. - 0 - - - INTERRUPT - Will interrupt when waiting - 0x1 - - - - - DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). - 1 - 1 - read-write - - - NO_INTERRUPT - Will not interrupt when Digest is ready - 0 - - - INTERRUPT - Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). - 0x1 - - - - - ERROR - Indicates if should interrupt on an ERROR (as defined in Status) - 2 - 1 - read-write - - - NOT_INTERRUPT - Will not interrupt on Error. - 0 - - - INTERRUPT - Will interrupt on Error (until cleared). - 0x1 - - - - - - - INTENCLR - Write 1 to clear interrupts. - 0xC - 32 - read-write - 0 - 0 - - - WAITING - Write 1 to clear mask. - 0 - 1 - read-write - oneToClear - - - DIGEST - Write 1 to clear mask. - 1 - 1 - read-write - oneToClear - - - ERROR - Write 1 to clear mask. - 2 - 1 - read-write - oneToClear - - - - - MEMCTRL - Setup Master to access memory (if available) - 0x10 - 32 - read-write - 0 - 0x7FF0001 - - - MASTER - Enables mastering. - 0 - 1 - read-write - - - NOT_USED - Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. - 0 - - - ENABLED - Mastering is enabled and DMA and INDATA should not be used. - 0x1 - - - - - COUNT - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks to copy starting at MEMADDR. This register will decrement after each block is copied, ending in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA interrupt will occur on ever block. If a bus error occurs, it will stop with this field set to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) blocks to hash. - 16 - 11 - read-write - - - - - MEMADDR - Address to start memory access from (if available). - 0x14 - 32 - read-write - 0 - 0xFFFFFFFF - - - BASE - Address base to start copying from, word aligned (so bits 1:0 must be 0). This field will advance as it processes the words. If it fails with a bus error, the register will contain the failing word. N:Address in Flash or RAM space; RAM only as mapped in this part. May also be able to address SPIFI. - 0 - 32 - read-write - - - - - INDATA - Input of 16 words at a time to load up buffer. - 0x20 - 32 - write-only - 0 - 0 - - - DATA - Write next word in little-endian form. The hash requires big endian word data, but this block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block will swap the word to restore into big endian. - 0 - 32 - write-only - - - - - 7 - 0x4 - ALIAS[%s] - no description available - 0x24 - 32 - write-only - 0 - 0 - - - DATA - Write next word in little-endian form. The hash requires big endian word data, but this block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block will swap the word to restore into big endian. - 0 - 32 - write-only - - - - - 8 - 0x4 - DIGEST0[%s] - no description available - 0x40 - 32 - read-only - 0 - 0xFFFFFFFF - - - DIGEST - One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1. - 0 - 32 - read-only - - - - - CRYPTCFG - Crypto settings for AES and Salsa and ChaCha - 0x80 - 32 - read-write - 0 - 0xF31FFF - - - MSW1ST_OUT - If 1, OUTDATA0 will be read Most significant word 1st for AES. Else it will be read in normal little endian - Least significant word 1st. Note: only if allowed by configuration. - 0 - 1 - read-write - - - SWAPKEY - If 1, will Swap the key input (bytes in each word). - 1 - 1 - read-write - - - SWAPDAT - If 1, will SWAP the data and IV inputs (bytes in each word). - 2 - 1 - read-write - - - MSW1ST - If 1, load of key, IV, and data is MSW 1st for AES. Else, the words are little endian. Note: only if allowed by configuration. - 3 - 1 - read-write - - - AESMODE - AES Cipher mode to use if plain AES - 4 - 2 - read-write - - - ECB - ECB - used as is - 0 - - - CBC - CBC mode (see details on IV/nonce) - 0x1 - - - CTR - CTR mode (see details on IV/nonce). See also AESCTRPOS. - 0x2 - - - - - AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB - 6 - 1 - read-write - - - ENCRYPT - Encrypt - 0 - - - DECRYPT - Decrypt - 0x1 - - - - - AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are used, only the highest level is permitted to select this. - 7 - 1 - read-write - - - NORMAL_WAY - User key provided in normal way - 0 - - - HIDDEN_WAY - Secret key provided in hidden way by HW - 0x1 - - - - - AESKEYSZ - Sets the AES key size - 8 - 2 - read-write - - - BITS_128 - 128 bit key - 0 - - - BITS_192 - 192 bit key - 0x1 - - - BITS_256 - 256 bit key - 0x2 - - - - - AESCTRPOS - Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other use CTR should use ECB directly and do its own XOR and so on. - 10 - 3 - read-write - - - STREAMLAST - Is 1 if last stream block. If not 1, then the engine will compute the next "hash". - 16 - 1 - read-write - - - ICBSZ - This sets the ICB size between 32 and 128 bits, using the following rules. Note that the counter is assumed to occupy the low order bits of the IV. - 20 - 2 - read-write - - - BITS_32 - 32 bits of the IV/ctr are used (from 127:96) - 0 - - - BITS_64 - 64 bits of the IV/ctr are used (from 127:64) - 0x1 - - - BITS_96 - 96 bits of the IV/ctr are used (from 127:32) - 0x2 - - - BIT_128 - All 128 bits of the IV/ctr are used - 0x3 - - - - - ICBSTRM - The size of the ICB-AES stream that can be pushed before needing to compute a new IV/ctr (counter start). This optimizes the performance of the stream of blocks after the 1st. - 22 - 2 - read-write - - - BLOCKS_8 - 8 blocks - 0 - - - BLOCKS_16 - 16 blocks - 0x1 - - - BLOCKS_32 - 32 blocks - 0x2 - - - BLOCKS_64 - 64 blocks - 0x3 - - - - - - - CONFIG - Returns the configuration of this block in this chip - indicates what services are available. - 0x84 - 32 - read-write - 0 - 0 - - - DUAL - 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit - 0 - 1 - read-only - - - DMA - 1 if DMA is connected - 1 - 1 - read-only - - - AHB - 1 if AHB Master is enabled - 3 - 1 - read-only - - - AES - 1 if AES 128 included - 6 - 1 - read-only - - - AESKEY - 1 if AES 192 and 256 also included - 7 - 1 - read-only - - - SECRET - 1 if AES Secret key available - 8 - 1 - read-only - - - ICB - 1 if ICB over AES included - 11 - 1 - read-only - - - - - LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. - 0x8C - 32 - read-write - 0 - 0xFFF3 - - - SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. If locked already, may only write if at same or higher security level as lock. Reads as: 0 if unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the only readable registers if locked and current state is lower than lock level. - 0 - 2 - read-write - - - UNLOCK - Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests. - 0 - - - LOCK - Locks to the current security level. AHB Master will issue requests at this level. - 0x1 - - - - - PATTERN - Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0 - 4 - 12 - read-write - - - - - 4 - 0x4 - MASK[%s] - no description available - 0x90 - 32 - write-only - 0 - 0 - - - MASK - A random word. - 0 - 32 - write-only - - - - - - - CASPER - CASPER - CASPER - 0x400A5000 - - 0 - 0x84 - registers - - - CASER - 55 - - - - CTRL0 - Contains the offsets of AB and CD in the RAM. - 0 - 32 - read-write - 0 - 0x1FFD0005 - - - ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up - 0 - 1 - read-write - - - PAIR0 - Bank-pair 0 (1st) - 0 - - - PAIR1 - Bank-pair 1 (2nd) - 0x1 - - - - - ABOFF - Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up - 2 - 11 - read-write - - - CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up - 16 - 1 - read-write - - - PAIR0 - Bank-pair 0 (1st) - 0 - - - PAIR1 - Bank-pair 1 (2nd) - 0x1 - - - - - CDOFF - Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the AB values - 18 - 11 - read-write - - - - - CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. - 0x4 - 32 - read-write - 0 - 0xDFFDFFFF - - - ITER - Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate. - 0 - 8 - read-write - - - MODE - Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active. - 8 - 8 - read-write - - - RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally this is not the same bank as ABBPAIR (when 4-up supported) - 16 - 1 - read-write - - - PAIR0 - Bank-pair 0 (1st) - 0 - - - PAIR1 - Bank-pair 1 (2nd) - 0x1 - - - - - RESOFF - Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the AB and CD values - 18 - 11 - read-write - - - CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: - 30 - 2 - read-write - - - NO_SKIP - No Skip - 0 - - - SKIP_IF_1 - Skip if Carry is 1 - 0x1 - - - SKIP_IF_0 - Skip if Carry is 0 - 0x2 - - - SET_AND_SKIP - Set CTRLOFF to CDOFF and Skip - 0x3 - - - - - - - LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. - 0x8 - 32 - read-write - 0 - 0x1FFD00FF - - - COUNT - Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one op - does not iterate, write N means N control pairs to load - 0 - 8 - read-write - - - CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not matter which bank is used as this is loaded when not performing an operation. - 16 - 1 - read-write - - - PAIR0 - Bank-pair 0 (1st) - 0 - - - PAIR1 - Bank-pair 1 (2nd) - 0x1 - - - - - CTRLOFF - DWord Offset of CTRL pair to load next. - 18 - 11 - read-write - - - - - STATUS - Indicates operational status and would contain the carry bit if used. - 0xC - 32 - read-write - 0 - 0x31 - - - DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. - 0 - 1 - read-write - - - BUSY - Busy or just cleared - 0 - - - COMPLETED - Completed last operation - 0x1 - - - - - CARRY - Last carry value if operation produced a carry bit - 4 - 1 - read-only - - - NO_CARRY - Carry was 0 or no carry - 0 - - - CARRY - Carry was 1 - 0x1 - - - - - BUSY - Indicates if the accelerator is busy performing an operation - 5 - 1 - read-only - - - IDLE - Not busy - is idle - 0 - - - BUSY - Is busy - 0x1 - - - - - - - INTENSET - Sets interrupts - 0x10 - 32 - read-write - 0 - 0x1 - - - DONE - Set if the accelerator should interrupt when done. - 0 - 1 - read-write - - - NO_INTERRUPT - Do not interrupt when done - 0 - - - INTERRUPT - Interrupt when done - 0x1 - - - - - - - INTENCLR - Clears interrupts - 0x14 - 32 - read-write - 0 - 0x1 - - - DONE - Written to clear an interrupt set with INTENSET. - 0 - 1 - read-write - oneToClear - - - IGNORED - If written 0, ignored - 0 - - - NO_INTERRUPT - If written 1, do not Interrupt when done - 0x1 - - - - - - - INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) - 0x18 - 32 - read-write - 0 - 0x1 - - - DONE - If set, interrupt is caused by accelerator being done. - 0 - 1 - read-only - - - NOT_CAUSED - Not caused by accelerator being done - 0 - - - CAUSED - Caused by accelerator being done - 0x1 - - - - - - - AREG - A register - 0x20 - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - BREG - B register - 0x24 - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - CREG - C register - 0x28 - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - DREG - D register - 0x2C - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - RES0 - Result register 0 - 0x30 - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - RES1 - Result register 1 - 0x34 - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - RES2 - Result register 2 - 0x38 - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - RES3 - Result register 3 - 0x3C - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - MASK - Optional mask register - 0x60 - 32 - read-write - 0 - 0xFFFFFFFF - - - MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values - 0 - 32 - read-write - - - - - REMASK - Optional re-mask register - 0x64 - 32 - read-write - 0 - 0xFFFFFFFF - - - MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values - 0 - 32 - read-write - - - - - LOCK - Security lock register - 0x80 - 32 - read-write - 0 - 0x1FFFF - - - LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. - 0 - 1 - read-write - - - UNLOCK - unlock - 0 - - - LOCK - Lock to current security level - 0x1 - - - - - KEY - Must be written as 0x73D to change the register. - 4 - 13 - read-write - - - KWY_VALUE - If set during write, will allow lock or unlock - 0x73D - - - - - - - - - SECGPIO - General Purpose I/O (GPIO) - GPIO - 0x400A8000 - - 0 - 0x2484 - registers - - - - B0_0 - Byte pin registers for all port GPIO pins - 0 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_1 - Byte pin registers for all port GPIO pins - 0x1 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_2 - Byte pin registers for all port GPIO pins - 0x2 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_3 - Byte pin registers for all port GPIO pins - 0x3 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_4 - Byte pin registers for all port GPIO pins - 0x4 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_5 - Byte pin registers for all port GPIO pins - 0x5 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_6 - Byte pin registers for all port GPIO pins - 0x6 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_7 - Byte pin registers for all port GPIO pins - 0x7 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_8 - Byte pin registers for all port GPIO pins - 0x8 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_9 - Byte pin registers for all port GPIO pins - 0x9 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_10 - Byte pin registers for all port GPIO pins - 0xA - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_11 - Byte pin registers for all port GPIO pins - 0xB - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_12 - Byte pin registers for all port GPIO pins - 0xC - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_13 - Byte pin registers for all port GPIO pins - 0xD - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_14 - Byte pin registers for all port GPIO pins - 0xE - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_15 - Byte pin registers for all port GPIO pins - 0xF - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_16 - Byte pin registers for all port GPIO pins - 0x10 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_17 - Byte pin registers for all port GPIO pins - 0x11 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_18 - Byte pin registers for all port GPIO pins - 0x12 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_19 - Byte pin registers for all port GPIO pins - 0x13 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_20 - Byte pin registers for all port GPIO pins - 0x14 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_21 - Byte pin registers for all port GPIO pins - 0x15 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_22 - Byte pin registers for all port GPIO pins - 0x16 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_23 - Byte pin registers for all port GPIO pins - 0x17 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_24 - Byte pin registers for all port GPIO pins - 0x18 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_25 - Byte pin registers for all port GPIO pins - 0x19 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_26 - Byte pin registers for all port GPIO pins - 0x1A - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_27 - Byte pin registers for all port GPIO pins - 0x1B - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_28 - Byte pin registers for all port GPIO pins - 0x1C - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_29 - Byte pin registers for all port GPIO pins - 0x1D - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_30 - Byte pin registers for all port GPIO pins - 0x1E - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_31 - Byte pin registers for all port GPIO pins - 0x1F - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - W0_0 - Word pin registers for all port GPIO pins - 0x1000 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_1 - Word pin registers for all port GPIO pins - 0x1004 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_2 - Word pin registers for all port GPIO pins - 0x1008 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_3 - Word pin registers for all port GPIO pins - 0x100C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_4 - Word pin registers for all port GPIO pins - 0x1010 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_5 - Word pin registers for all port GPIO pins - 0x1014 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_6 - Word pin registers for all port GPIO pins - 0x1018 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_7 - Word pin registers for all port GPIO pins - 0x101C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_8 - Word pin registers for all port GPIO pins - 0x1020 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_9 - Word pin registers for all port GPIO pins - 0x1024 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_10 - Word pin registers for all port GPIO pins - 0x1028 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_11 - Word pin registers for all port GPIO pins - 0x102C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_12 - Word pin registers for all port GPIO pins - 0x1030 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_13 - Word pin registers for all port GPIO pins - 0x1034 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_14 - Word pin registers for all port GPIO pins - 0x1038 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_15 - Word pin registers for all port GPIO pins - 0x103C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_16 - Word pin registers for all port GPIO pins - 0x1040 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_17 - Word pin registers for all port GPIO pins - 0x1044 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_18 - Word pin registers for all port GPIO pins - 0x1048 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_19 - Word pin registers for all port GPIO pins - 0x104C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_20 - Word pin registers for all port GPIO pins - 0x1050 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_21 - Word pin registers for all port GPIO pins - 0x1054 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_22 - Word pin registers for all port GPIO pins - 0x1058 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_23 - Word pin registers for all port GPIO pins - 0x105C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_24 - Word pin registers for all port GPIO pins - 0x1060 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_25 - Word pin registers for all port GPIO pins - 0x1064 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_26 - Word pin registers for all port GPIO pins - 0x1068 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_27 - Word pin registers for all port GPIO pins - 0x106C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_28 - Word pin registers for all port GPIO pins - 0x1070 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_29 - Word pin registers for all port GPIO pins - 0x1074 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_30 - Word pin registers for all port GPIO pins - 0x1078 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_31 - Word pin registers for all port GPIO pins - 0x107C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - DIR0 - Direction registers for all port GPIO pins - 0x2000 - 32 - read-write - 0 - 0xFFFFFFFF - - - DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output. - 0 - 32 - read-write - - - - - MASK0 - Mask register for all port GPIO pins - 0x2080 - 32 - read-write - 0 - 0xFFFFFFFF - - - MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. - 0 - 32 - read-write - - - - - PIN0 - Port pin register for all port GPIO pins - 0x2100 - 32 - read-write - 0 - 0xFFFFFFFF - - - PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. - 0 - 32 - read-write - - - - - MPIN0 - Masked port register for all port GPIO pins - 0x2180 - 32 - read-write - 0 - 0xFFFFFFFF - - - MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. - 0 - 32 - read-write - - - - - SET0 - Write: Set register for port. Read: output bits for port - 0x2200 - 32 - read-write - 0 - 0xFFFFFFFF - - - SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. - 0 - 32 - read-write - - - - - CLR0 - Clear port for all port GPIO pins - 0x2280 - 32 - write-only - 0 - 0 - - - CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit. - 0 - 32 - write-only - - - - - NOT0 - Toggle port for all port GPIO pins - 0x2300 - 32 - write-only - 0 - 0 - - - NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit. - 0 - 32 - write-only - - - - - DIRSET0 - Set pin direction bits for port - 0x2380 - 32 - write-only - 0 - 0 - - - DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit. - 0 - 32 - write-only - - - - - DIRCLR0 - Clear pin direction bits for port - 0x2400 - 32 - write-only - 0 - 0 - - - DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit. - 0 - 32 - write-only - - - - - DIRNOT0 - Toggle pin direction bits for port - 0x2480 - 32 - write-only - 0 - 0 - - - DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit. - 0 - 32 - write-only - - - - - - - AHB_SECURE_CTRL - AHB secure controller - AHB_SECURE_CTRL - 0x400AC000 - - 0 - 0x1000 - registers - - - - SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_FLASH_MEM_RULE0 - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_FLASH_MEM_RULE1 - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. - 0x14 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_FLASH_MEM_RULE2 - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. - 0x18 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_ROM_MEM_RULE0 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. - 0x20 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_ROM_MEM_RULE1 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. - 0x24 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_ROM_MEM_RULE2 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. - 0x28 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_ROM_MEM_RULE3 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. - 0x2C - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. - 0x30 - 32 - read-write - 0 - 0xFFFFFFFF - - - RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAMX_MEM_RULE0 - Security access rules for RAMX slaves. - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. - 0x50 - 32 - read-write - 0 - 0xFFFFFFFF - - - RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM0_MEM_RULE0 - Security access rules for RAM0 slaves. - 0x60 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM0_MEM_RULE1 - Security access rules for RAM0 slaves. - 0x64 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. - 0x70 - 32 - read-write - 0 - 0xFFFFFFFF - - - RAM1_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM1_MEM_RULE0 - Security access rules for RAM1 slaves. - 0x80 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM1_MEM_RULE1 - Security access rules for RAM1 slaves. - 0x84 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. - 0x90 - 32 - read-write - 0 - 0xFFFFFFFF - - - RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM2_MEM_RULE0 - Security access rules for RAM2 slaves. - 0xA0 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM2_MEM_RULE1 - Security access rules for RAM2 slaves. - 0xA4 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. - 0xB0 - 32 - read-write - 0 - 0xFFFFFFFF - - - RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM3_MEM_RULE0 - Security access rules for RAM3 slaves. - 0xC0 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM3_MEM_RULE1 - Security access rules for RAM3 slaves. - 0xC4 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. - 0xD0 - 32 - read-write - 0 - 0xFFFFFFFF - - - RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM4_MEM_RULE0 - Security access rules for RAM4 slaves. - 0xE0 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. - 0xF0 - 32 - read-write - 0 - 0xFFFFFFFF - - - APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - SYSCON_RULE - System Configuration - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - IOCON_RULE - I/O Configuration - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - GINT0_RULE - GPIO input Interrupt 0 - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - GINT1_RULE - GPIO input Interrupt 1 - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - PINT_RULE - Pin Interrupt and Pattern match - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SEC_PINT_RULE - Secure Pin Interrupt and Pattern match - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - INPUTMUX_RULE - Peripheral input multiplexing - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. - 0x104 - 32 - read-write - 0 - 0xFFFFFFFF - - - CTIMER0_RULE - Standard counter/Timer 0 - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - CTIMER1_RULE - Standard counter/Timer 1 - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - WWDT_RULE - Windiwed wtachdog Timer - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - MRT_RULE - Multi-rate Timer - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - UTICK_RULE - Micro-Timer - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. - 0x108 - 32 - read-write - 0 - 0xFFFFFFFF - - - ANACTRL_RULE - Analog Modules controller - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. - 0x110 - 32 - read-write - 0 - 0xFFFFFFFF - - - PMC_RULE - Power Management Controller - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SYSCTRL_RULE - System Controller - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. - 0x114 - 32 - read-write - 0 - 0xFFFFFFFF - - - CTIMER2_RULE - Standard counter/Timer 2 - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - CTIMER3_RULE - Standard counter/Timer 3 - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - CTIMER4_RULE - Standard counter/Timer 4 - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RTC_RULE - Real Time Counter - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - OSEVENT_RULE - OS Event Timer - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. - 0x118 - 32 - read-write - 0 - 0xFFFFFFFF - - - FLASH_CTRL_RULE - Flash Controller - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - PRINCE_RULE - Prince - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. - 0x11C - 32 - read-write - 0 - 0xFFFFFFFF - - - USBHPHY_RULE - USB High Speed Phy controller - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RNG_RULE - True Random Number Generator - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - PUF_RULE - PUF - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - PLU_RULE - Programmable Look-Up logic - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. - 0x120 - 32 - read-write - 0 - 0xFFFFFFFF - - - DMA0_RULE - DMA Controller - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - FS_USB_DEV_RULE - USB Full-speed device - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SCT_RULE - SCTimer - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - FLEXCOMM0_RULE - Flexcomm interface 0 - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - FLEXCOMM1_RULE - Flexcomm interface 1 - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. - 0x124 - 32 - read-write - 0 - 0xFFFFFFFF - - - FLEXCOMM2_RULE - Flexcomm interface 2 - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - FLEXCOMM3_RULE - Flexcomm interface 3 - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - FLEXCOMM4_RULE - Flexcomm interface 4 - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - MAILBOX_RULE - Inter CPU communication Mailbox - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - GPIO0_RULE - High Speed GPIO - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. - 0x130 - 32 - read-write - 0 - 0xFFFFFFFF - - - USB_HS_DEV_RULE - USB high Speed device registers - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - CRC_RULE - CRC engine - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - FLEXCOMM5_RULE - Flexcomm interface 5 - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - FLEXCOMM6_RULE - Flexcomm interface 6 - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. - 0x134 - 32 - read-write - 0 - 0xFFFFFFFF - - - FLEXCOMM7_RULE - Flexcomm interface 7 - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SDIO_RULE - SDMMC card interface - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - HS_LSPI_RULE - High Speed SPI - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_AHB_PORT10_SLAVE0_RULE - Security access rules for AHB peripherals. - 0x140 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADC_RULE - ADC - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - USB_FS_HOST_RULE - USB Full Speed Host registers. - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - USB_HS_HOST_RULE - USB High speed host registers - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - HASH_RULE - SHA-2 crypto registers - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - CASPER_RULE - RSA/ECC crypto accelerator - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - PQ_RULE - Power Quad (CPU0 processor hardware accelerator) - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - DMA1_RULE - DMA Controller (Secure) - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_AHB_PORT10_SLAVE1_RULE - Security access rules for AHB peripherals. - 0x144 - 32 - read-write - 0 - 0xFFFFFFFF - - - GPIO1_RULE - Secure High Speed GPIO - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - AHB_SEC_CTRL_RULE - AHB Secure Controller - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. - 0x150 - 32 - read-write - 0 - 0xFFFFFFFF - - - AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. - 0x160 - 32 - read-write - 0 - 0xFFFFFFFF - - - RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. - 0x170 - 32 - read-write - 0 - 0xFFFFFFFF - - - SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - 12 - 0x4 - sec_vio_addr[%s] - most recent security violation address for AHB port n - 0xE00 - 32 - read-only - 0 - 0xFFFFFFFF - - - SEC_VIO_ADDR - security violation address for AHB port - 0 - 32 - read-only - - - - - 12 - 0x4 - sec_vio_misc_info[%s] - most recent security violation miscellaneous information for AHB port n - 0xE80 - 32 - read-only - 0 - 0xFF3 - - - SEC_VIO_INFO_WRITE - security violation access read/write indicator. - 0 - 1 - read-only - - - READ - Read access. - 0 - - - WRITE - Write access. - 0x1 - - - - - SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator. - 1 - 1 - read-only - - - CODE - Code access. - 0 - - - DATA - Data access. - 0x1 - - - - - SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level - 4 - 4 - read-only - - - SEC_VIO_INFO_MASTER - security violation master number - 8 - 4 - read-only - - - VALUE_0 - CPU0 Code. - 0 - - - VALUE_1 - CPU0 System. - 0x1 - - - VALUE_2 - CPU1 Data. - 0x2 - - - VALUE_3 - CPU1 System. - 0x3 - - - VALUE_4 - USB-HS Device. - 0x4 - - - VALUE_5 - SDMA0. - 0x5 - - - VALUE_8 - SDIO. - 0x8 - - - VALUE_9 - PowerQuad. - 0x9 - - - VALUE_10 - HASH. - 0xA - - - VALUE_11 - USB-FS Host. - 0xB - - - VALUE_12 - SDMA1. - 0xC - - - - - - - SEC_VIO_INFO_VALID - security violation address/information registers valid flags - 0xF00 - 32 - read-write - 0 - 0x3FFFF - - - VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear. - 0 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear. - 1 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear. - 2 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear. - 3 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear. - 4 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear. - 5 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear. - 6 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear. - 7 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear. - 8 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear. - 9 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID10 - violation information valid flag for AHB port 10. Write 1 to clear. - 10 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID11 - violation information valid flag for AHB port 11. Write 1 to clear. - 11 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - - - SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. - 0xF80 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0 - 0 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1 - 1 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2 - 2 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3 - 3 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4 - 4 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5 - 5 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6 - 6 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7 - 7 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8 - 8 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9 - 9 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10 - 10 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11 - 11 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12 - 12 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13 - 13 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14 - 14 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15 - 15 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16 - 16 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17 - 17 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18 - 18 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19 - 19 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20 - 20 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21 - 21 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22 - 22 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23 - 23 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24 - 24 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25 - 25 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26 - 26 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27 - 27 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28 - 28 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29 - 29 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30 - 30 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31 - 31 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - - - SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. - 0xF84 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0 - 0 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1 - 1 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2 - 2 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3 - 3 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4 - 4 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5 - 5 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6 - 6 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7 - 7 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8 - 8 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9 - 9 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10 - 10 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11 - 11 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12 - 12 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13 - 13 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14 - 14 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15 - 15 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16 - 16 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17 - 17 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18 - 18 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19 - 19 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20 - 20 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21 - 21 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22 - 22 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23 - 23 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24 - 24 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25 - 25 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26 - 26 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27 - 27 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28 - 28 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29 - 29 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30 - 30 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31 - 31 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - - - SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 - 0xF90 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - SYS_IRQ - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts - 0 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SDMA0_IRQ - System DMA 0 (non-secure) interrupt. - 1 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_GLOBALINT0_IRQ - GPIO Group 0 interrupt. - 2 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_GLOBALINT1_IRQ - GPIO Group 1 interrupt. - 3 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_INT0_IRQ0 - Pin interrupt 0 or pattern match engine slice 0 interrupt. - 4 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_INT0_IRQ1 - Pin interrupt 1 or pattern match engine slice 1 interrupt. - 5 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_INT0_IRQ2 - Pin interrupt 2 or pattern match engine slice 2 interrupt. - 6 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_INT0_IRQ3 - Pin interrupt 3 or pattern match engine slice 3 interrupt. - 7 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - UTICK_IRQ - Micro Tick Timer interrupt. - 8 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - MRT_IRQ - Multi-Rate Timer interrupt. - 9 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - CTIMER0_IRQ - Standard counter/timer 0 interrupt. - 10 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - CTIMER1_IRQ - Standard counter/timer 1 interrupt. - 11 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SCT_IRQ - SCTimer/PWM interrupt. - 12 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - CTIMER3_IRQ - Standard counter/timer 3 interrupt. - 13 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM0_IRQ - Flexcomm 0 interrupt (USART, SPI, I2C, I2S). - 14 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM1_IRQ - Flexcomm 1 interrupt (USART, SPI, I2C, I2S). - 15 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM2_IRQ - Flexcomm 2 interrupt (USART, SPI, I2C, I2S). - 16 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM3_IRQ - Flexcomm 3 interrupt (USART, SPI, I2C, I2S). - 17 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM4_IRQ - Flexcomm 4 interrupt (USART, SPI, I2C, I2S). - 18 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM5_IRQ - Flexcomm 5 interrupt (USART, SPI, I2C, I2S). - 19 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM6_IRQ - Flexcomm 6 interrupt (USART, SPI, I2C, I2S). - 20 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM7_IRQ - Flexcomm 7 interrupt (USART, SPI, I2C, I2S). - 21 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - ADC_IRQ - General Purpose ADC interrupt. - 22 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED0 - Reserved. Read value is undefined, only zero should be written. - 23 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - ACMP_IRQ - Analog Comparator interrupt. - 24 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED1 - Reserved. Read value is undefined, only zero should be written. - 25 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED2 - Reserved. Read value is undefined, only zero should be written. - 26 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - USB0_NEEDCLK - USB Full Speed Controller Clock request interrupt. - 27 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - USB0_IRQ - USB Full Speed Controller interrupt. - 28 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RTC_IRQ - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ - 29 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED3 - Reserved. Read value is undefined, only zero should be written. - 30 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - MAILBOX_IRQ - Mailbox interrupt. - 31 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - - - SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 - 0xF94 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - GPIO_INT0_IRQ4 - Pin interrupt 4 or pattern match engine slice 4 interrupt. - 0 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_INT0_IRQ5 - Pin interrupt 5 or pattern match engine slice 5 interrupt. - 1 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_INT0_IRQ6 - Pin interrupt 6 or pattern match engine slice 6 interrupt. - 2 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_INT0_IRQ7 - Pin interrupt 7 or pattern match engine slice 7 interrupt. - 3 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - CTIMER2_IRQ - Standard counter/timer 2 interrupt. - 4 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - CTIMER4_IRQ - Standard counter/timer 4 interrupt. - 5 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - OS_EVENT_TIMER_IRQ - OS Event Timer and OS Event Timer Wakeup interrupts - 6 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED0 - Reserved. Read value is undefined, only zero should be written. - 7 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED1 - Reserved. Read value is undefined, only zero should be written. - 8 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED2 - Reserved. Read value is undefined, only zero should be written. - 9 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SDIO_IRQ - SDIO Controller interrupt. - 10 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED3 - Reserved. Read value is undefined, only zero should be written. - 11 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED4 - Reserved. Read value is undefined, only zero should be written. - 12 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED5 - Reserved. Read value is undefined, only zero should be written. - 13 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - USB1_PHY_IRQ - USB High Speed PHY Controller interrupt. - 14 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - USB1_IRQ - USB High Speed Controller interrupt. - 15 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - USB1_NEEDCLK - USB High Speed Controller Clock request interrupt. - 16 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SEC_HYPERVISOR_CALL_IRQ - Secure fault Hyper Visor call interrupt. - 17 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SEC_GPIO_INT0_IRQ0 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt. - 18 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SEC_GPIO_INT0_IRQ1 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt. - 19 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - PLU_IRQ - Programmable Look-Up Controller interrupt. - 20 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SEC_VIO_IRQ - Security Violation interrupt. - 21 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SHA_IRQ - HASH-AES interrupt. - 22 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - CASPER_IRQ - CASPER interrupt. - 23 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - PUFKEY_IRQ - PUF interrupt. - 24 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - PQ_IRQ - Power Quad interrupt. - 25 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SDMA1_IRQ - System DMA 1 (Secure) interrupt - 26 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - LSPI_HS_IRQ - High Speed SPI interrupt - 27 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - - - SEC_MASK_LOCK - Security General Purpose register access control. - 0xFBC - 32 - read-write - 0xAAA - 0xFFF - - - SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock. - 0 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock. - 2 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - SEC_CPU1_INT_MASK0_LOCK - SEC_CPU_INT_MASK0 register write-lock. - 8 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - SEC_CPU1_INT_MASK1_LOCK - SEC_CPU_INT_MASK1 register write-lock. - 10 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - - - MASTER_SEC_LEVEL - master secure level register - 0xFD0 - 32 - read-write - 0x80000000 - 0xFFFFFFFF - - - CPU1C - Micro-Cortex M33 (CPU1) Code bus. - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - CPU1S - Micro-Cortex M33 (CPU1) System bus. - 6 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - USBFSD - USB Full Speed Device. - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SDMA0 - System DMA 0. - 10 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SDIO - SDIO. - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - PQ - Power Quad. - 18 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - HASH - Hash. - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - USBFSH - USB Full speed Host. - 22 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SDMA1 - System DMA 1 security level. - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock. - 30 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - - - MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register - 0xFD4 - 32 - read-write - 0xBFFFFFFF - 0xFFFFFFFF - - - CPU1C - Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C) - 4 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - CPU1S - Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S) - 6 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) - 8 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) - 10 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - SDIO - SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO) - 16 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - PQ - Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ) - 18 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) - 20 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) - 22 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) - 24 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock. - 30 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - - - CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) - 0xFEC - 32 - read-write - 0x800002AA - 0xC00003FF - - - LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock. - 0 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock. - 2 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. - 4 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock. - 6 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock. - 8 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock. - 30 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - - - CPU1_LOCK_REG - Miscalleneous control signals for in micro-Cortex M33 (CPU1) - 0xFF0 - 32 - read-write - 0x8000000A - 0xC000000F - - - LOCK_NS_VTOR - micro-Cortex M33 (CPU1) VTOR_NS register write-lock. - 0 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - LOCK_NS_MPU - micro-Cortex M33 (CPU1) non-secure MPU register write-lock. - 2 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - CPU1_LOCK_REG_LOCK - CPU1_LOCK_REG write-lock. - 30 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - - - MISC_CTRL_DP_REG - secure control duplicate register - 0xFF8 - 32 - read-write - 0xAAAA - 0xFFFF - - - WRITE_LOCK - Write lock. - 0 - 2 - read-write - - - RESTRICTED - Restricted mode. - 0x1 - - - ACCESSIBLE - Secure control registers can be written. - 0x2 - - - - - ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. - 2 - 2 - read-write - - - ENABLE - Restricted mode. - 0x1 - - - DISABLE - Disable check. - 0x2 - - - - - ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. - 4 - 2 - read-write - - - ENABLE - Restricted mode. - 0x1 - - - DISABLE - Disable check. - 0x2 - - - - - ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. - 6 - 2 - read-write - - - ENABLE - Restricted mode. - 0x1 - - - DISABLE - Disable check. - 0x2 - - - - - DISABLE_VIOLATION_ABORT - Disable secure violation abort. - 8 - 2 - read-write - - - DISABLE - Disable abort fort secure checker. - 0x1 - - - ENABLE - Enable abort fort secure checker. - 0x2 - - - - - DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. - 10 - 2 - read-write - - - TIER_MODE - Simple master in tier mode. - 0x1 - - - STRICT_MODE - Simple master in strict mode. - 0x2 - - - - - DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. - 12 - 2 - read-write - - - TIER_MODE - Smart master in tier mode. - 0x1 - - - STRICT_MODE - Smart master in strict mode. - 0x2 - - - - - IDAU_ALL_NS - Disable IDAU. - 14 - 2 - read-write - - - DISABLE - IDAU is disable. - 0x1 - - - ENABLE - IDAU is enabled. - 0x2 - - - - - - - MISC_CTRL_REG - secure control register - 0xFFC - 32 - read-write - 0xAAAA - 0xFFFF - - - WRITE_LOCK - Write lock. - 0 - 2 - read-write - - - RESTRICTED - Restricted mode. - 0x1 - - - ACCESSIBLE - Secure control registers can be written. - 0x2 - - - - - ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. - 2 - 2 - read-write - - - ENABLE - Enabled (restricted mode) - 0x1 - - - DISABLE - Disable check. - 0x2 - - - - - ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. - 4 - 2 - read-write - - - ENABLE - Enabled (restricted mode) - 0x1 - - - DISABLE - Disable check. - 0x2 - - - - - ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. - 6 - 2 - read-write - - - ENABLE - Enabled (restricted mode) - 0x1 - - - DISABLE - Disable check. - 0x2 - - - - - DISABLE_VIOLATION_ABORT - Disable secure violation abort. - 8 - 2 - read-write - - - DISABLE - Disable abort fort secure checker. - 0x1 - - - ENABLE - Enable abort fort secure checker. - 0x2 - - - - - DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. - 10 - 2 - read-write - - - TIER_MODE - Simple master in tier mode. - 0x1 - - - STRICT_MODE - Simple master in strict mode. - 0x2 - - - - - DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. - 12 - 2 - read-write - - - TIER_MODE - Smart master in tier mode. - 0x1 - - - STRICT_MODE - Smart master in strict mode. - 0x2 - - - - - IDAU_ALL_NS - Disable IDAU. - 14 - 2 - read-write - - - DISABLE - IDAU is disable. - 0x1 - - - ENABLE - IDAU is enabled. - 0x2 - - - - - - - - - SCnSCB - no description available - SCNSCB - 0xE000E000 - - 0 - 0x10 - registers - - - - CPPWR - Coprocessor Power Control Register - 0xC - 32 - read-write - 0 - 0 - - - SU0 - State UNKNOWN 0. - 0 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS0 - State UNKNOWN Secure only 0. - 1 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU0 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU0 field is only accessible from the Secure state. - 0x1 - - - - - SU1 - State UNKNOWN 1. - 2 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS1 - State UNKNOWN Secure only 1. - 3 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU7 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU7 field is only accessible from the Secure state. - 0x1 - - - - - SU2 - State UNKNOWN 2. - 4 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS2 - State UNKNOWN Secure only 2. - 5 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU2 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU2 field is only accessible from the Secure state. - 0x1 - - - - - SU3 - State UNKNOWN 3. - 6 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS3 - State UNKNOWN Secure only 3. - 7 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU3 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU3 field is only accessible from the Secure state. - 0x1 - - - - - SU4 - State UNKNOWN 4. - 8 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS4 - State UNKNOWN Secure only 4. - 9 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU4 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU4 field is only accessible from the Secure state. - 0x1 - - - - - SU5 - State UNKNOWN 5. - 10 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS5 - State UNKNOWN Secure only 5. - 11 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU5 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU5 field is only accessible from the Secure state. - 0x1 - - - - - SU6 - State UNKNOWN 6. - 12 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS6 - State UNKNOWN Secure only 6. - 13 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU6 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU6 field is only accessible from the Secure state. - 0x1 - - - - - SU7 - State UNKNOWN 7. - 14 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS7 - State UNKNOWN Secure only 7. - 15 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU7 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU7 field is only accessible from the Secure state. - 0x1 - - - - - SU10 - State UNKNOWN 10. - 20 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The floating-point state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The floating-point state is permitted to become UNKNOWN - 0x1 - - - - - SUS10 - State UNKNOWN Secure only 10. - 21 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU10 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU10 field is only accessible from the Secure state. - 0x1 - - - - - SU11 - State UNKNOWN 11. - 22 - 1 - read-write - - - SUS11 - State UNKNOWN Secure only 11. - 23 - 1 - read-write - - - - - - - NVIC - no description available - NVIC - 0xE000E100 - - 0 - 0xE04 - registers - - - - 16 - 0x4 - ISER[%s] - Interrupt Set Enable Register - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - SETENA0 - Interrupt set-enable bits. - 0 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA1 - Interrupt set-enable bits. - 1 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA2 - Interrupt set-enable bits. - 2 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA3 - Interrupt set-enable bits. - 3 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA4 - Interrupt set-enable bits. - 4 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA5 - Interrupt set-enable bits. - 5 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA6 - Interrupt set-enable bits. - 6 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA7 - Interrupt set-enable bits. - 7 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA8 - Interrupt set-enable bits. - 8 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA9 - Interrupt set-enable bits. - 9 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA10 - Interrupt set-enable bits. - 10 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA11 - Interrupt set-enable bits. - 11 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA12 - Interrupt set-enable bits. - 12 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA13 - Interrupt set-enable bits. - 13 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA14 - Interrupt set-enable bits. - 14 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA15 - Interrupt set-enable bits. - 15 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA16 - Interrupt set-enable bits. - 16 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA17 - Interrupt set-enable bits. - 17 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA18 - Interrupt set-enable bits. - 18 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA19 - Interrupt set-enable bits. - 19 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA20 - Interrupt set-enable bits. - 20 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA21 - Interrupt set-enable bits. - 21 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA22 - Interrupt set-enable bits. - 22 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA23 - Interrupt set-enable bits. - 23 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA24 - Interrupt set-enable bits. - 24 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA25 - Interrupt set-enable bits. - 25 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA26 - Interrupt set-enable bits. - 26 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA27 - Interrupt set-enable bits. - 27 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA28 - Interrupt set-enable bits. - 28 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA29 - Interrupt set-enable bits. - 29 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA30 - Interrupt set-enable bits. - 30 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA31 - Interrupt set-enable bits. - 31 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - - - 16 - 0x4 - ICER[%s] - Interrupt Clear Enable Register - 0x80 - 32 - read-write - 0 - 0xFFFFFFFF - - - CLRENA0 - Interrupt clear-enable bits. - 0 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA1 - Interrupt clear-enable bits. - 1 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA2 - Interrupt clear-enable bits. - 2 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA3 - Interrupt clear-enable bits. - 3 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA4 - Interrupt clear-enable bits. - 4 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA5 - Interrupt clear-enable bits. - 5 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA6 - Interrupt clear-enable bits. - 6 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA7 - Interrupt clear-enable bits. - 7 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA8 - Interrupt clear-enable bits. - 8 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA9 - Interrupt clear-enable bits. - 9 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA10 - Interrupt clear-enable bits. - 10 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA11 - Interrupt clear-enable bits. - 11 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA12 - Interrupt clear-enable bits. - 12 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA13 - Interrupt clear-enable bits. - 13 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA14 - Interrupt clear-enable bits. - 14 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA15 - Interrupt clear-enable bits. - 15 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA16 - Interrupt clear-enable bits. - 16 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA17 - Interrupt clear-enable bits. - 17 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA18 - Interrupt clear-enable bits. - 18 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA19 - Interrupt clear-enable bits. - 19 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA20 - Interrupt clear-enable bits. - 20 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA21 - Interrupt clear-enable bits. - 21 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA22 - Interrupt clear-enable bits. - 22 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA23 - Interrupt clear-enable bits. - 23 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA24 - Interrupt clear-enable bits. - 24 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA25 - Interrupt clear-enable bits. - 25 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA26 - Interrupt clear-enable bits. - 26 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA27 - Interrupt clear-enable bits. - 27 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA28 - Interrupt clear-enable bits. - 28 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA29 - Interrupt clear-enable bits. - 29 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA30 - Interrupt clear-enable bits. - 30 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA31 - Interrupt clear-enable bits. - 31 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - - - 16 - 0x4 - ISPR[%s] - Interrupt Set Pending Register - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - SETPEND0 - Interrupt set-pending bits. - 0 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND1 - Interrupt set-pending bits. - 1 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND2 - Interrupt set-pending bits. - 2 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND3 - Interrupt set-pending bits. - 3 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND4 - Interrupt set-pending bits. - 4 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND5 - Interrupt set-pending bits. - 5 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND6 - Interrupt set-pending bits. - 6 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND7 - Interrupt set-pending bits. - 7 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND8 - Interrupt set-pending bits. - 8 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND9 - Interrupt set-pending bits. - 9 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND10 - Interrupt set-pending bits. - 10 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND11 - Interrupt set-pending bits. - 11 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND12 - Interrupt set-pending bits. - 12 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND13 - Interrupt set-pending bits. - 13 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND14 - Interrupt set-pending bits. - 14 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND15 - Interrupt set-pending bits. - 15 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND16 - Interrupt set-pending bits. - 16 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND17 - Interrupt set-pending bits. - 17 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND18 - Interrupt set-pending bits. - 18 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND19 - Interrupt set-pending bits. - 19 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND20 - Interrupt set-pending bits. - 20 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND21 - Interrupt set-pending bits. - 21 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND22 - Interrupt set-pending bits. - 22 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND23 - Interrupt set-pending bits. - 23 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND24 - Interrupt set-pending bits. - 24 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND25 - Interrupt set-pending bits. - 25 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND26 - Interrupt set-pending bits. - 26 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND27 - Interrupt set-pending bits. - 27 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND28 - Interrupt set-pending bits. - 28 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND29 - Interrupt set-pending bits. - 29 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND30 - Interrupt set-pending bits. - 30 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND31 - Interrupt set-pending bits. - 31 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - - - 16 - 0x4 - ICPR[%s] - Interrupt Clear Pending Register - 0x180 - 32 - read-write - 0 - 0xFFFFFFFF - - - CLRPEND0 - Interrupt clear-pending bits. - 0 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND1 - Interrupt clear-pending bits. - 1 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND2 - Interrupt clear-pending bits. - 2 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND3 - Interrupt clear-pending bits. - 3 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND4 - Interrupt clear-pending bits. - 4 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND5 - Interrupt clear-pending bits. - 5 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND6 - Interrupt clear-pending bits. - 6 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND7 - Interrupt clear-pending bits. - 7 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND8 - Interrupt clear-pending bits. - 8 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND9 - Interrupt clear-pending bits. - 9 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND10 - Interrupt clear-pending bits. - 10 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND11 - Interrupt clear-pending bits. - 11 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND12 - Interrupt clear-pending bits. - 12 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND13 - Interrupt clear-pending bits. - 13 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND14 - Interrupt clear-pending bits. - 14 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND15 - Interrupt clear-pending bits. - 15 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND16 - Interrupt clear-pending bits. - 16 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND17 - Interrupt clear-pending bits. - 17 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND18 - Interrupt clear-pending bits. - 18 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND19 - Interrupt clear-pending bits. - 19 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND20 - Interrupt clear-pending bits. - 20 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND21 - Interrupt clear-pending bits. - 21 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND22 - Interrupt clear-pending bits. - 22 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND23 - Interrupt clear-pending bits. - 23 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND24 - Interrupt clear-pending bits. - 24 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND25 - Interrupt clear-pending bits. - 25 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND26 - Interrupt clear-pending bits. - 26 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND27 - Interrupt clear-pending bits. - 27 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND28 - Interrupt clear-pending bits. - 28 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND29 - Interrupt clear-pending bits. - 29 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND30 - Interrupt clear-pending bits. - 30 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND31 - Interrupt clear-pending bits. - 31 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - - - 16 - 0x4 - IABR[%s] - Interrupt Active Bit Register - 0x200 - 32 - read-write - 0 - 0 - - - ACTIVE0 - Active state bits. - 0 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE1 - Active state bits. - 1 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE2 - Active state bits. - 2 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE3 - Active state bits. - 3 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE4 - Active state bits. - 4 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE5 - Active state bits. - 5 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE6 - Active state bits. - 6 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE7 - Active state bits. - 7 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE8 - Active state bits. - 8 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE9 - Active state bits. - 9 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE10 - Active state bits. - 10 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE11 - Active state bits. - 11 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE12 - Active state bits. - 12 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE13 - Active state bits. - 13 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE14 - Active state bits. - 14 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE15 - Active state bits. - 15 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE16 - Active state bits. - 16 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE17 - Active state bits. - 17 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE18 - Active state bits. - 18 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE19 - Active state bits. - 19 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE20 - Active state bits. - 20 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE21 - Active state bits. - 21 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE22 - Active state bits. - 22 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE23 - Active state bits. - 23 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE24 - Active state bits. - 24 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE25 - Active state bits. - 25 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE26 - Active state bits. - 26 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE27 - Active state bits. - 27 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE28 - Active state bits. - 28 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE29 - Active state bits. - 29 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE30 - Active state bits. - 30 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE31 - Active state bits. - 31 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - - - 16 - 0x4 - ITNS[%s] - Interrupt Target Non-secure Register - 0x280 - 32 - read-write - 0 - 0 - - - INTS0 - Interrupt Targets Non-secure bits. - 0 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS1 - Interrupt Targets Non-secure bits. - 1 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS2 - Interrupt Targets Non-secure bits. - 2 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS3 - Interrupt Targets Non-secure bits. - 3 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS4 - Interrupt Targets Non-secure bits. - 4 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS5 - Interrupt Targets Non-secure bits. - 5 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS6 - Interrupt Targets Non-secure bits. - 6 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS7 - Interrupt Targets Non-secure bits. - 7 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS8 - Interrupt Targets Non-secure bits. - 8 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS9 - Interrupt Targets Non-secure bits. - 9 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS10 - Interrupt Targets Non-secure bits. - 10 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS11 - Interrupt Targets Non-secure bits. - 11 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS12 - Interrupt Targets Non-secure bits. - 12 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS13 - Interrupt Targets Non-secure bits. - 13 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS14 - Interrupt Targets Non-secure bits. - 14 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS15 - Interrupt Targets Non-secure bits. - 15 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS16 - Interrupt Targets Non-secure bits. - 16 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS17 - Interrupt Targets Non-secure bits. - 17 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS18 - Interrupt Targets Non-secure bits. - 18 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS19 - Interrupt Targets Non-secure bits. - 19 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS20 - Interrupt Targets Non-secure bits. - 20 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS21 - Interrupt Targets Non-secure bits. - 21 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS22 - Interrupt Targets Non-secure bits. - 22 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS23 - Interrupt Targets Non-secure bits. - 23 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS24 - Interrupt Targets Non-secure bits. - 24 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS25 - Interrupt Targets Non-secure bits. - 25 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS26 - Interrupt Targets Non-secure bits. - 26 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS27 - Interrupt Targets Non-secure bits. - 27 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS28 - Interrupt Targets Non-secure bits. - 28 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS29 - Interrupt Targets Non-secure bits. - 29 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS30 - Interrupt Targets Non-secure bits. - 30 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS31 - Interrupt Targets Non-secure bits. - 31 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - - - 120 - 0x4 - IPR[%s] - Interrupt Priority Register - 0x300 - 32 - read-write - 0 - 0 - - - PRI_0 - no description available - 0 - 8 - read-write - - - PRI_1 - no description available - 8 - 8 - read-write - - - PRI_2 - no description available - 16 - 8 - read-write - - - PRI_3 - no description available - 24 - 8 - read-write - - - - - STIR - Software Trigger Interrupt Register - 0xE00 - 32 - write-only - 0 - 0xFFFFFFFF - - - INTID - Interrupt ID of the interrupt to trigger, in the range 0-479. - 0 - 9 - write-only - - - - - - - SCB - no description available - SCB - 0xE000ED00 - - 0 - 0x90 - registers - - - - AIRCR - Application Interrupt and Reset Control Register - 0xC - 32 - read-write - 0xFA050000 - 0xFFFFFFFF - - - VECTCLRACTIVE - Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is UNPREDICTABLE. This bit is not banked between Security states. - 1 - 1 - write-only - - - SYSRESETREQ - System reset request. This bit allows software or a debugger to request a system reset. This bit is not banked between Security states. RW if SYSRESETREQS is 0. When SYSRESETREQS is set to 1, from Non-secure state this bit acts as RAZ/WI. - 2 - 1 - read-write - - - NO_REQUEST - Do not request a system reset. - 0 - - - REQUEST_RESET - Request a system reset. - 0x1 - - - - - SYSRESETREQS - System reset request, Secure state only. The value of this bit defines whether the SYSRESETREQ bit is functional for Non-secure use. This bit is not banked between Security states. RW from Secure State and RAZ/WI from Non-secure state. - 3 - 1 - read-write - - - SECURE_AND_NON_SECURE - SYSRESETREQ functionality is available to both Security states. - 0 - - - SECURE_ONLY - SYSRESETREQ functionality is only available to Secure state. - 0x1 - - - - - PRIGROUP - Interrupt priority grouping field. This field determines the split of group priority from subpriority. This bit is banked between Security states - 8 - 3 - read-write - - - BFHFNMINS - BusFault, HardFault, and NMI Non-secure enable. The value of this bit defines whether BusFault and NMI exceptions are Non-secure, and whether exceptions target the Non-secure HardFault exception. This bit is not banked between Security states. RW from Secure-state and RO from Non-secure state. - 13 - 1 - read-write - - - SECURE - BusFault, HardFault, and NMI are Secure. - 0 - - - NON_SECURE - BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault. - 0x1 - - - - - PRIS - Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. This bit is not banked between Security states. RW from Secure state and RAZ/WI from Non-secure state. - 14 - 1 - read-write - - - SAME_PRIORITY - Priority ranges of Secure and Non-secure exceptions are identical - 0 - - - SECURE_PRIORITIZED - Non-secure exceptions are de-prioritized - 0x1 - - - - - ENDIANNESS - Data endianness bit. This bit is not banked between Security states. - 15 - 1 - read-only - - - LITTLE_ENDIAN - Little-endian. - 0 - - - BIG_ENDIAN - Big-endian - 0x1 - - - - - VECTKEY - Register key: Reads as 0xFA05. On writes, write 0x5FA to VECTKEY, otherwise the write is ignored. This Field is not banked between Security states. - 16 - 16 - read-only - - - - - SCR - The SCR controls features of entry to and exit from low-power state. - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - SLEEPONEXIT - Indicates sleep-on-exit when returning from Handler mode to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. This bit is banked between Security states. - 1 - 1 - read-write - - - NOT_SLEEP - Do not sleep when returning to Thread mode. - 0 - - - SLEEP - Enter sleep, or deep sleep, on return from an ISR - 0x1 - - - - - SLEEPDEEP - Controls whether the processor uses sleep or deep sleep as its low-power mode. This bit is not banked between Security states. - 2 - 1 - read-write - - - SLEEP - Sleep. - 0 - - - DEEP_SLEEP - Deep sleep. - 0x1 - - - - - SLEEPDEEPS - Controls whether the SLEEPDEEP bit is only accessible from the Secure state. This bit in only accessible from the Secure state, and behaves as RAZ/WI when accessed from the Nonsecure state. This bit is not banked between Security states. - 3 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SLEEPDEEP bit is accessible from both Security states. - 0 - - - SECURE_ONLY - The SLEEPDEEP bit behaves as RAZ/WI when accessed from the Non-secure state. - 0x1 - - - - - SEVONPEND - Send Event on Pending bit. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event. This bit is banked between Security states. - 4 - 1 - read-write - - - EXCLUDE_DISABLED_INTERRUPTS - Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. - 0 - - - INCLUDE_DISABLED_INTERRUPTS - Enabled events and all interrupts, including disabled interrupts, can wakeup the processor - 0x1 - - - - - - - SHCSR - System Handler Control and State Register - 0x24 - 32 - read-write - 0 - 0xFFFFFFFF - - - MEMFAULTACT - MemManage exception active. - 0 - 1 - read-write - - - NOT_ACTIVE - MemManage exception is not active. - 0 - - - ACTIVE - MemManage exception is active. - 0x1 - - - - - BUSFAULTACT - BusFault exception active. - 1 - 1 - read-write - - - NOT_ACTIVE - BusFault exception is not active. - 0 - - - ACTIVE - BusFault exception is active. - 0x1 - - - - - HARDFAULTACT - HardFault exception active. - 2 - 1 - read-write - - - NOT_ACTIVE - HardFault exception is not active. - 0 - - - ACTIVE - HardFault exception is active. - 0x1 - - - - - USGFAULTACT - UsageFault exception active. - 3 - 1 - read-write - - - NOT_ACTIVE - UsageFault exception is not active. - 0 - - - ACTIVE - UsageFault exception is active. - 0x1 - - - - - SECUREFAULTACT - SecureFault exception active - 4 - 1 - read-write - - - NOT_ACTIVE - SecureFault exception is not active. - 0 - - - ACTIVE - SecureFault exception is active. - 0x1 - - - - - NMIACT - NMI exception active. - 5 - 1 - read-write - - - NOT_ACTIVE - NMI exception is not active. - 0 - - - ACTIVE - NMI exception is active. - 0x1 - - - - - SVCALLACT - SVCall active. - 7 - 1 - read-write - - - NOT_ACTIVE - SVCall exception is not active. - 0 - - - ACTIVE - SVCall exception is active. - 0x1 - - - - - MONITORACT - Debug monitor active. - 8 - 1 - read-write - - - NOT_ACTIVE - Debug monitor exception is not active. - 0 - - - ACTIVE - Debug monitor exception is active. - 0x1 - - - - - PENDSVACT - PendSV exception active. - 10 - 1 - read-write - - - NOT_ACTIVE - PendSV exception is not active. - 0 - - - ACTIVE - PendSV exception is active. - 0x1 - - - - - SYSTICKACT - SysTick exception active. - 11 - 1 - read-write - - - NOT_ACTIVE - SysTick exception is not active. - 0 - - - ACTIVE - SysTick exception is active. - 0x1 - - - - - USGFAULTPENDED - UsageFault exception pending. - 12 - 1 - read-write - - - NOT_PENDING - UsageFault exception is not pending. - 0 - - - PENDING - UsageFault exception is pending. - 0x1 - - - - - MEMFAULTPENDED - MemManage exception pending. - 13 - 1 - read-write - - - NOT_PENDING - MemManage exception is not pending. - 0 - - - PENDING - MemManage exception is pending. - 0x1 - - - - - BUSFAULTPENDED - BusFault exception pending. - 14 - 1 - read-write - - - NOT_PENDING - BusFault exception is pending. - 0 - - - PENDING - BusFault exception is not pending. - 0x1 - - - - - SVCALLPENDED - SVCall pending. - 15 - 1 - read-write - - - NOT_PENDING - SVCall exception is not pending. - 0 - - - PENDING - SVCall exception is pending. - 0x1 - - - - - MEMFAULTENA - MemManage enable. - 16 - 1 - read-write - - - DISABLED - MemManage exception is disabled. - 0 - - - ENABLED - MemManage exception is enabled. - 0x1 - - - - - BUSFAULTENA - BusFault enable. - 17 - 1 - read-write - - - DISABLED - BusFault is disabled. - 0 - - - ENABLED - BusFault is enabled. - 0x1 - - - - - USGFAULTENA - UsageFault enable. - 18 - 1 - read-write - - - DISABLED - UsageFault is disabled. - 0 - - - ENABLED - UsageFault is enabled. - 0x1 - - - - - SECUREFAULTENA - SecureFault exception enable. - 19 - 1 - read-write - - - DISABLED - SecureFault exception is disabled. - 0 - - - ENABLED - SecureFault exception is enabled. - 0x1 - - - - - SECUREFAULTPENDED - SecureFault exception pended state bit. - 20 - 1 - read-write - - - DISABLED - SecureFault exception modification is disabled. - 0 - - - ENABLED - SecureFault exception modification is enabled. - 0x1 - - - - - HARDFAULTPENDED - HardFault exception pended state - 21 - 1 - read-write - - - DISABLED - HardFault exception modification is disabled. - 0 - - - ENABLED - HardFault exception modification is enabled. - 0x1 - - - - - - - NSACR - Non-secure Access Control Register - 0x8C - 32 - read-write - 0 - 0 - - - CP0 - CP0 access. - 0 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP1 - CP1 access. - 1 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP2 - CP2 access. - 2 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP3 - CP3 access. - 3 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP4 - CP4 access. - 4 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP5 - CP5 access. - 5 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP6 - CP6 access. - 6 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP7 - CP7 access. - 7 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP10 - CP10 access. - 10 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to the Floating-point Extension generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to the Floatingpoint Extension permitted. - 0x1 - - - - - CP11 - CP11 access. - 11 - 1 - read-write - - - - - - - SAU - no description available - SAU - 0xE000EDD0 - - 0 - 0xEC - registers - - - - CTRL - Security Attribution Unit Control Register - 0xD0 - 32 - read-write - 0 - 0xFFFFFFFF - - - ENABLE - Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region. - 0 - 1 - read-write - - - DISABLED - The SAU is disabled. - 0 - - - ENABLED - The SAU is enabled. - 0x1 - - - - - ALLNS - All Non-secure. - 1 - 1 - read-write - - - SECURED_MEMORY - Memory is marked as Secure and is not Non-secure callable. - 0 - - - NON_SECURED_MEMORY - Memory is marked as Non-secure. - 0x1 - - - - - - - TYPE - Security Attribution Unit Type Register - 0xD4 - 32 - read-write - 0 - 0xFFFFFFFF - - - SREGION - SAU regions. The number of implemented SAU regions. - 0 - 8 - read-write - - - - - RNR - Security Attribution Unit Region Number Register - 0xD8 - 32 - read-write - 0 - 0 - - - REGION - Region number. - 0 - 8 - read-write - - - - - RBAR - Security Attribution Unit Region Base Address Register - 0xDC - 32 - read-write - 0 - 0 - - - BADDR - Base address. Holds bits[31:5] of the base address for the selected SAU region. Bits[4:0] of the base address are defined as 0x00. - 5 - 27 - read-write - - - - - RLAR - Security Attribution Unit Region Limit Address Register - 0xE0 - 32 - read-write - 0 - 0 - - - ENABLE - Enable. SAU region enable. - 0 - 1 - read-write - - - ENABLED - SAU region is enabled. - 0 - - - DISABLED - SAU region is disabled. - 0x1 - - - - - NSC - Non-secure callable. Controls whether Non-secure state is permitted to execute an SG instruction from this region. - 1 - 1 - read-write - - - NOT_NON_SECURE_CALLABLE - Region is not Non-secure callable. - 0 - - - NON_SECURE_CALLABLE - Region is Non-secure callable. - 0x1 - - - - - LADDR - Limit address. Holds bits[31:5] of the limit address for the selected SAU region. Bits[4:0] of the limit address are defined as 0x1F. - 5 - 27 - read-write - - - - - SFSR - Secure Fault Status Register - 0xE4 - 32 - read-write - 0 - 0xFFFFFFFF - - - INVEP - Invalid entry point. - 0 - 1 - read-write - - - NO_ERROR - Error has not occurred. - 0 - - - ERROR - Error has occurred. - 0x1 - - - - - INVIS - Invalid integrity signature flag. - 1 - 1 - read-write - - - NO_ERROR - Error has not occurred. - 0 - - - ERROR - Error has occurred. - 0x1 - - - - - INVER - Invalid exception return flag. - 2 - 1 - read-write - - - NO_ERROR - Error has not occurred. - 0 - - - ERROR - Error has occurred. - 0x1 - - - - - AUVIOL - Attribution unit violation flag. - 3 - 1 - read-write - - - NO_ERROR - Error has not occurred. - 0 - - - ERROR - Error has occurred. - 0x1 - - - - - INVTRAN - Invalid transition flag. - 4 - 1 - read-write - - - NO_ERROR - Error has not occurred. - 0 - - - ERROR - Error has occurred. - 0x1 - - - - - LSPERR - Lazy state preservation error flag. - 5 - 1 - read-write - - - NO_ERROR - Error has not occurred. - 0 - - - ERROR - Error has occurred. - 0x1 - - - - - SFARVALID - Secure fault address valid. - 6 - 1 - read-write - - - NOT_VALID - SFAR content not valid. - 0 - - - VALID - SFAR content valid. - 0x1 - - - - - LSERR - Lazy state error flag. - 7 - 1 - read-write - - - NO_ERROR - Error has not occurred - 0 - - - ERROR - Error has occurred. - 0x1 - - - - - - - SFAR - Secure Fault Address Register - 0xE8 - 32 - read-write - 0 - 0 - - - ADDRESS - When the SFARVALID bit of the SFSR is set to 1, this field holds the address of an access that caused an SAU violation. - 0 - 32 - read-write - - - - - - - \ No newline at end of file diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/LPC55S28_features.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/LPC55S28_features.h deleted file mode 100644 index 2a34f883d9f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/LPC55S28_features.h +++ /dev/null @@ -1,433 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.1, 2019-05-16 -** Build: b220303 -** -** Abstract: -** Chip specific module features. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** - rev. 1.1 (2019-05-16) -** Initial A1 version based on v1.3UM -** -** ################################################################### -*/ - -#ifndef _LPC55S28_FEATURES_H_ -#define _LPC55S28_FEATURES_H_ - -/* SOC module features */ - -/* @brief CASPER availability on the SoC. */ -#define FSL_FEATURE_SOC_CASPER_COUNT (1) -/* @brief CRC availability on the SoC. */ -#define FSL_FEATURE_SOC_CRC_COUNT (1) -/* @brief CTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_CTIMER_COUNT (5) -/* @brief DMA availability on the SoC. */ -#define FSL_FEATURE_SOC_DMA_COUNT (2) -/* @brief FLASH availability on the SoC. */ -#define FSL_FEATURE_SOC_FLASH_COUNT (1) -/* @brief FLEXCOMM availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) -/* @brief GINT availability on the SoC. */ -#define FSL_FEATURE_SOC_GINT_COUNT (2) -/* @brief GPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_GPIO_COUNT (1) -/* @brief SECGPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_SECGPIO_COUNT (1) -/* @brief HASHCRYPT availability on the SoC. */ -#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) -/* @brief I2C availability on the SoC. */ -#define FSL_FEATURE_SOC_I2C_COUNT (8) -/* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (8) -/* @brief INPUTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) -/* @brief IOCON availability on the SoC. */ -#define FSL_FEATURE_SOC_IOCON_COUNT (1) -/* @brief LPADC availability on the SoC. */ -#define FSL_FEATURE_SOC_LPADC_COUNT (1) -/* @brief MRT availability on the SoC. */ -#define FSL_FEATURE_SOC_MRT_COUNT (1) -/* @brief OSTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) -/* @brief PINT availability on the SoC. */ -#define FSL_FEATURE_SOC_PINT_COUNT (1) -/* @brief SECPINT availability on the SoC. */ -#define FSL_FEATURE_SOC_SECPINT_COUNT (1) -/* @brief PMC availability on the SoC. */ -#define FSL_FEATURE_SOC_PMC_COUNT (1) -/* @brief PUF availability on the SoC. */ -#define FSL_FEATURE_SOC_PUF_COUNT (1) -/* @brief LPC_RNG1 availability on the SoC. */ -#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) -/* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (1) -/* @brief SCT availability on the SoC. */ -#define FSL_FEATURE_SOC_SCT_COUNT (1) -/* @brief SDIF availability on the SoC. */ -#define FSL_FEATURE_SOC_SDIF_COUNT (1) -/* @brief SPI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPI_COUNT (9) -/* @brief SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCON_COUNT (1) -/* @brief SYSCTL1 availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) -/* @brief USART availability on the SoC. */ -#define FSL_FEATURE_SOC_USART_COUNT (8) -/* @brief USB availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_COUNT (1) -/* @brief USBFSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBFSH_COUNT (1) -/* @brief USBHSD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSD_COUNT (1) -/* @brief USBHSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSH_COUNT (1) -/* @brief USBPHY availability on the SoC. */ -#define FSL_FEATURE_SOC_USBPHY_COUNT (1) -/* @brief UTICK availability on the SoC. */ -#define FSL_FEATURE_SOC_UTICK_COUNT (1) -/* @brief WWDT availability on the SoC. */ -#define FSL_FEATURE_SOC_WWDT_COUNT (1) - -/* LPADC module features */ - -/* @brief FIFO availability on the SoC. */ -#define FSL_FEATURE_LPADC_FIFO_COUNT (2) -/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) -/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) -/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) -/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) -/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) -/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) -/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) -/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) -/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) -/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) -/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) -/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) -/* @brief Has calibration (bitfield CFG[CALOFS]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) -/* @brief Has offset trim (register OFSTRIM). */ -#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) -/* @brief Has Trigger status register. */ -#define FSL_FEATURE_LPADC_HAS_TSTAT (1) -/* @brief Has power select (bitfield CFG[PWRSEL]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) -/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) -/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) -/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) -/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) -/* @brief Conversion averaged bitfiled width. */ -#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) -/* @brief Has internal temperature sensor. */ -#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) -/* @brief Temperature sensor parameter A (slope). */ -#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (744.6f) -/* @brief Temperature sensor parameter B (offset). */ -#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (313.7f) -/* @brief Temperature sensor parameter Alpha. */ -#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.5f) -/* @brief the buffer size of temperature sensor. */ -#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U) - -/* ANALOGCTRL module features */ - -/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ -#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) -/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ -#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (0) -/* @brief Has auxiliary bias(register AUX_BIAS). */ -#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1) - -/* CASPER module features */ - -/* @brief Base address of the CASPER dedicated RAM */ -#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) -/* @brief SW interleaving of the CASPER dedicated RAM */ -#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1) -/* @brief CASPER dedicated RAM offset */ -#define FSL_FEATURE_CASPER_RAM_OFFSET (0xE) - -/* CTIMER module features */ - -/* @brief CTIMER has no capture channel. */ -#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) -/* @brief CTIMER has no capture 2 interrupt. */ -#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) -/* @brief CTIMER capture 3 interrupt. */ -#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) -/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ -#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) -/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ -#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) - -/* DMA module features */ - -/* @brief Number of channels */ -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23) -/* @brief Align size of DMA descriptor */ -#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) -/* @brief DMA head link descriptor table align size */ -#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) - -/* FLEXCOMM module features */ - -/* @brief FLEXCOMM0 USART INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) -/* @brief FLEXCOMM0 SPI INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) -/* @brief FLEXCOMM0 I2C INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) -/* @brief FLEXCOMM0 I2S INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) -/* @brief FLEXCOMM1 USART INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) -/* @brief FLEXCOMM1 SPI INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) -/* @brief FLEXCOMM1 I2C INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) -/* @brief FLEXCOMM1 I2S INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) -/* @brief FLEXCOMM2 USART INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) -/* @brief FLEXCOMM2 SPI INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) -/* @brief FLEXCOMM2 I2C INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) -/* @brief FLEXCOMM2 I2S INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) -/* @brief FLEXCOMM3 USART INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) -/* @brief FLEXCOMM3 SPI INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) -/* @brief FLEXCOMM3 I2C INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) -/* @brief FLEXCOMM3 I2S INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) -/* @brief FLEXCOMM4 USART INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) -/* @brief FLEXCOMM4 SPI INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) -/* @brief FLEXCOMM4 I2C INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) -/* @brief FLEXCOMM4 I2S INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) -/* @brief FLEXCOMM5 USART INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) -/* @brief FLEXCOMM5 SPI INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) -/* @brief FLEXCOMM5 I2C INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) -/* @brief FLEXCOMM5 I2S INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) -/* @brief FLEXCOMM6 USART INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) -/* @brief FLEXCOMM6 SPI INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) -/* @brief FLEXCOMM6 I2C INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) -/* @brief FLEXCOMM6 I2S INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) -/* @brief FLEXCOMM7 USART INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) -/* @brief FLEXCOMM7 SPI INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) -/* @brief FLEXCOMM7 I2C INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) -/* @brief FLEXCOMM7 I2S INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) -/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ -#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) -/* @brief I2S has DMIC interconnection */ -#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) - -/* HASHCRYPT module features */ - -/* @brief the address of alias offset */ -#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000) - -/* I2S module features */ - -/* @brief I2S support dual channel transfer. */ -#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0) -/* @brief I2S has DMIC interconnection */ -#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) - -/* IOCON module features */ - -/* @brief Func bit field width */ -#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) - -/* MRT module features */ - -/* @brief number of channels. */ -#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) - -/* PINT module features */ - -/* @brief Number of connected outputs */ -#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) - -/* PLU module features */ - -/* @brief Has WAKEINT_CTRL register. */ -#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) - -/* PMC module features */ - -/* @brief UTICK does not support PD configure. */ -#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) -/* @brief WDT OSC does not support PD configure. */ -#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) - -/* POWERLIB module features */ - -/* @brief Powerlib API is different with other LPC series devices. */ -#define FSL_FEATURE_POWERLIB_EXTEND (1) - -/* PUF module features */ - -/* @brief Number of PUF key slots available on device. */ -#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4) -/* @brief the shift status value */ -#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) - -/* RTC module features */ - -/* No feature definitions */ - -/* SCT module features */ - -/* @brief Number of events */ -#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) -/* @brief Number of states */ -#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) -/* @brief Number of match capture */ -#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) -/* @brief Number of outputs */ -#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) - -/* SDIF module features */ - -/* @brief FIFO depth, every location is a WORD */ -#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) -/* @brief Max DMA buffer size */ -#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) -/* @brief Max source clock in HZ */ -#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) -/* @brief support 2 cards */ -#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1) - -/* SECPINT module features */ - -/* @brief Number of connected outputs */ -#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) - -/* SYSCON module features */ - -/* @brief Flash page size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) -/* @brief Flash sector size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) -/* @brief Flash size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288) -/* @brief Has Power Down mode */ -#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) -/* @brief CCM_ANALOG availability on the SoC. */ -#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) -/* @brief Starter register discontinuous. */ -#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) - -/* SYSCTL1 module features */ - -/* No feature definitions */ - -/* USB module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USB_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USB version */ -#define FSL_FEATURE_USB_VERSION (200) -/* @brief Number of the endpoint in USB FS */ -#define FSL_FEATURE_USB_EP_NUM (5) - -/* USBFSH module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USBFSH version */ -#define FSL_FEATURE_USBFSH_VERSION (200) - -/* USBHSD module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USBHSD version */ -#define FSL_FEATURE_USBHSD_VERSION (300) -/* @brief Number of the endpoint in USB HS */ -#define FSL_FEATURE_USBHSD_EP_NUM (6) - -/* USBHSH module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USBHSH version */ -#define FSL_FEATURE_USBHSH_VERSION (300) - -/* USBPHY module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBPHY_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USBHSD version */ -#define FSL_FEATURE_USBPHY_VERSION (300) -/* @brief Number of the endpoint in USB HS */ -#define FSL_FEATURE_USBPHY_EP_NUM (6) - -/* WWDT module features */ - -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) -/* @brief WWDT does not support oscillator lock. */ -#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) - -#endif /* _LPC55S28_FEATURES_H_ */ - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/LPC55S28_flash.scf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/LPC55S28_flash.scf deleted file mode 100644 index 84289f2b967..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/LPC55S28_flash.scf +++ /dev/null @@ -1,83 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c -/* -** ################################################################### -** Processors: LPC55S28JBD100_cm33_core0 -** LPC55S28JBD64_cm33_core0 -** LPC55S28JEV98_cm33_core0 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b200722 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2020 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#define m_interrupts_start 0x00000000 -#define m_interrupts_size 0x00000200 - -#define m_text_start 0x00000200 -#define m_text_size 0x0007FDFF - -#define m_data_start 0x20000000 -#define m_data_size 0x00030000 - -#define m_usb_sram_start 0x40100000 -#define m_usb_sram_size 0x00004000 - - -LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region - - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - - RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (*m_usb_bdt) - } - - RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (*m_usb_global) - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/LPC55S28_ram.scf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/LPC55S28_ram.scf deleted file mode 100644 index f12097b4318..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/LPC55S28_ram.scf +++ /dev/null @@ -1,83 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c -/* -** ################################################################### -** Processors: LPC55S28JBD100_cm33_core0 -** LPC55S28JBD64_cm33_core0 -** LPC55S28JEV98_cm33_core0 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b200722 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2020 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#define m_interrupts_start 0x04000000 -#define m_interrupts_size 0x00000200 - -#define m_text_start 0x04000200 -#define m_text_size 0x00007DFF - -#define m_data_start 0x20000000 -#define m_data_size 0x00030000 - -#define m_usb_sram_start 0x40100000 -#define m_usb_sram_size 0x00004000 - - -LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region - - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - - RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (*m_usb_bdt) - } - - RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (*m_usb_global) - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/LPC55XX_512.FLM b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/LPC55XX_512.FLM deleted file mode 100644 index 254ce6d452f..00000000000 Binary files a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/LPC55XX_512.FLM and /dev/null differ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/LPC55xx.dbgconf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/LPC55xx.dbgconf deleted file mode 100644 index 1cc3a2af84a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/LPC55xx.dbgconf +++ /dev/null @@ -1,18 +0,0 @@ -// <<< Use Configuration Wizard in Context Menu >>> - -// SWO pin -// The SWO (Serial Wire Output) pin optionally provides data from the ITM -// for an external debug tool to evaluate. -// <0=> PIO0_10 -// <1=> PIO0_8 -SWO_Pin = 0; -// - -// Debug Configuration -// StopAfterBootloader Stop after Bootloader -// -Dbg_CR = 0x00000001; -// - - -// <<< end of configuration section >>> \ No newline at end of file diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/startup_LPC55S28.S b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/startup_LPC55S28.S deleted file mode 100644 index 9c7c155949d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/startup_LPC55S28.S +++ /dev/null @@ -1,801 +0,0 @@ -/* --------------------------------------------------------------------------------------- - * @file: startup_LPC55S28.s - * @purpose: CMSIS Cortex-M33 Core Device Startup File for the LPC55S28 - * @version: 1.1 - * @date: 2019-5-16 - * ---------------------------------------------------------------------------------------*/ -/* - * Copyright 1997-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - - .syntax unified - .arch armv8-m.main - .eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */ - - .section .isr_vector, "a" - .align 2 - .globl __Vectors - -__Vectors: - .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long MemManage_Handler /* MPU Fault Handler*/ - .long BusFault_Handler /* Bus Fault Handler*/ - .long UsageFault_Handler /* Usage Fault Handler*/ - .long SecureFault_Handler /* Secure Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long DebugMon_Handler /* Debug Monitor Handler*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts*/ - .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ - .long DMA0_IRQHandler /* DMA0 controller */ - .long GINT0_IRQHandler /* GPIO group 0 */ - .long GINT1_IRQHandler /* GPIO group 1 */ - .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - .long UTICK0_IRQHandler /* Micro-tick Timer */ - .long MRT0_IRQHandler /* Multi-rate timer */ - .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ - .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ - .long SCT0_IRQHandler /* SCTimer/PWM */ - .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ - .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long ADC0_IRQHandler /* ADC0 */ - .long Reserved39_IRQHandler /* Reserved interrupt */ - .long ACMP_IRQHandler /* ACMP interrupts */ - .long Reserved41_IRQHandler /* Reserved interrupt */ - .long Reserved42_IRQHandler /* Reserved interrupt */ - .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ - .long USB0_IRQHandler /* USB device */ - .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ - .long Reserved46_IRQHandler /* Reserved interrupt */ - .long Reserved47_IRQHandler /* Reserved interrupt */ - .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ - .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ - .long OS_EVENT_IRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ - .long Reserved55_IRQHandler /* Reserved interrupt */ - .long Reserved56_IRQHandler /* Reserved interrupt */ - .long Reserved57_IRQHandler /* Reserved interrupt */ - .long SDIO_IRQHandler /* SD/MMC */ - .long Reserved59_IRQHandler /* Reserved interrupt */ - .long Reserved60_IRQHandler /* Reserved interrupt */ - .long Reserved61_IRQHandler /* Reserved interrupt */ - .long USB1_PHY_IRQHandler /* USB1_PHY */ - .long USB1_IRQHandler /* USB1 interrupt */ - .long USB1_NEEDCLK_IRQHandler /* USB1 activity */ - .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ - .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ - .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ - .long PLU_IRQHandler /* PLU interrupt */ - .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ - .long HASHCRYPT_IRQHandler /* HASHCRYPT interrupt */ - .long CASER_IRQHandler /* CASPER interrupt */ - .long PUF_IRQHandler /* PUF interrupt */ - .long PQ_IRQHandler /* PQ interrupt */ - .long DMA1_IRQHandler /* DMA1 interrupt */ - .long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ - .size __Vectors, . - __Vectors - - .text - .thumb - -/* Reset Handler */ - .thumb_func - .align 2 - .weak Reset_Handler - .type Reset_Handler, %function - -Reset_Handler: - cpsid i /* Mask interrupts */ - .equ VTOR, 0xE000ED08 - ldr r0, =VTOR - ldr r1, =__Vectors - str r1, [r0] - ldr r2, [r1] - msr msp, r2 - ldr R0, =Image$$ARM_LIB_STACK$$ZI$$Base - msr msplim, R0 - ldr r0,=SystemInit - blx r0 - cpsie i /* Unmask interrupts */ - ldr r0,=__main - bx r0 - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - .align 1 - .thumb_func - .weak WDT_BOD_IRQHandler - .type WDT_BOD_IRQHandler, %function -WDT_BOD_IRQHandler: - ldr r0,=WDT_BOD_DriverIRQHandler - bx r0 - .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler - - .align 1 - .thumb_func - .weak DMA0_IRQHandler - .type DMA0_IRQHandler, %function -DMA0_IRQHandler: - ldr r0,=DMA0_DriverIRQHandler - bx r0 - .size DMA0_IRQHandler, . - DMA0_IRQHandler - - .align 1 - .thumb_func - .weak GINT0_IRQHandler - .type GINT0_IRQHandler, %function -GINT0_IRQHandler: - ldr r0,=GINT0_DriverIRQHandler - bx r0 - .size GINT0_IRQHandler, . - GINT0_IRQHandler - - .align 1 - .thumb_func - .weak GINT1_IRQHandler - .type GINT1_IRQHandler, %function -GINT1_IRQHandler: - ldr r0,=GINT1_DriverIRQHandler - bx r0 - .size GINT1_IRQHandler, . - GINT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT0_IRQHandler - .type PIN_INT0_IRQHandler, %function -PIN_INT0_IRQHandler: - ldr r0,=PIN_INT0_DriverIRQHandler - bx r0 - .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT1_IRQHandler - .type PIN_INT1_IRQHandler, %function -PIN_INT1_IRQHandler: - ldr r0,=PIN_INT1_DriverIRQHandler - bx r0 - .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT2_IRQHandler - .type PIN_INT2_IRQHandler, %function -PIN_INT2_IRQHandler: - ldr r0,=PIN_INT2_DriverIRQHandler - bx r0 - .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT3_IRQHandler - .type PIN_INT3_IRQHandler, %function -PIN_INT3_IRQHandler: - ldr r0,=PIN_INT3_DriverIRQHandler - bx r0 - .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler - - .align 1 - .thumb_func - .weak UTICK0_IRQHandler - .type UTICK0_IRQHandler, %function -UTICK0_IRQHandler: - ldr r0,=UTICK0_DriverIRQHandler - bx r0 - .size UTICK0_IRQHandler, . - UTICK0_IRQHandler - - .align 1 - .thumb_func - .weak MRT0_IRQHandler - .type MRT0_IRQHandler, %function -MRT0_IRQHandler: - ldr r0,=MRT0_DriverIRQHandler - bx r0 - .size MRT0_IRQHandler, . - MRT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER0_IRQHandler - .type CTIMER0_IRQHandler, %function -CTIMER0_IRQHandler: - ldr r0,=CTIMER0_DriverIRQHandler - bx r0 - .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER1_IRQHandler - .type CTIMER1_IRQHandler, %function -CTIMER1_IRQHandler: - ldr r0,=CTIMER1_DriverIRQHandler - bx r0 - .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler - - .align 1 - .thumb_func - .weak SCT0_IRQHandler - .type SCT0_IRQHandler, %function -SCT0_IRQHandler: - ldr r0,=SCT0_DriverIRQHandler - bx r0 - .size SCT0_IRQHandler, . - SCT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER3_IRQHandler - .type CTIMER3_IRQHandler, %function -CTIMER3_IRQHandler: - ldr r0,=CTIMER3_DriverIRQHandler - bx r0 - .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM0_IRQHandler - .type FLEXCOMM0_IRQHandler, %function -FLEXCOMM0_IRQHandler: - ldr r0,=FLEXCOMM0_DriverIRQHandler - bx r0 - .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM1_IRQHandler - .type FLEXCOMM1_IRQHandler, %function -FLEXCOMM1_IRQHandler: - ldr r0,=FLEXCOMM1_DriverIRQHandler - bx r0 - .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM2_IRQHandler - .type FLEXCOMM2_IRQHandler, %function -FLEXCOMM2_IRQHandler: - ldr r0,=FLEXCOMM2_DriverIRQHandler - bx r0 - .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM3_IRQHandler - .type FLEXCOMM3_IRQHandler, %function -FLEXCOMM3_IRQHandler: - ldr r0,=FLEXCOMM3_DriverIRQHandler - bx r0 - .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM4_IRQHandler - .type FLEXCOMM4_IRQHandler, %function -FLEXCOMM4_IRQHandler: - ldr r0,=FLEXCOMM4_DriverIRQHandler - bx r0 - .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM5_IRQHandler - .type FLEXCOMM5_IRQHandler, %function -FLEXCOMM5_IRQHandler: - ldr r0,=FLEXCOMM5_DriverIRQHandler - bx r0 - .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM6_IRQHandler - .type FLEXCOMM6_IRQHandler, %function -FLEXCOMM6_IRQHandler: - ldr r0,=FLEXCOMM6_DriverIRQHandler - bx r0 - .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM7_IRQHandler - .type FLEXCOMM7_IRQHandler, %function -FLEXCOMM7_IRQHandler: - ldr r0,=FLEXCOMM7_DriverIRQHandler - bx r0 - .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_IRQHandler - .type ADC0_IRQHandler, %function -ADC0_IRQHandler: - ldr r0,=ADC0_DriverIRQHandler - bx r0 - .size ADC0_IRQHandler, . - ADC0_IRQHandler - - .align 1 - .thumb_func - .weak Reserved39_IRQHandler - .type Reserved39_IRQHandler, %function -Reserved39_IRQHandler: - ldr r0,=Reserved39_DriverIRQHandler - bx r0 - .size Reserved39_IRQHandler, . - Reserved39_IRQHandler - - .align 1 - .thumb_func - .weak ACMP_IRQHandler - .type ACMP_IRQHandler, %function -ACMP_IRQHandler: - ldr r0,=ACMP_DriverIRQHandler - bx r0 - .size ACMP_IRQHandler, . - ACMP_IRQHandler - - .align 1 - .thumb_func - .weak Reserved41_IRQHandler - .type Reserved41_IRQHandler, %function -Reserved41_IRQHandler: - ldr r0,=Reserved41_DriverIRQHandler - bx r0 - .size Reserved41_IRQHandler, . - Reserved41_IRQHandler - - .align 1 - .thumb_func - .weak Reserved42_IRQHandler - .type Reserved42_IRQHandler, %function -Reserved42_IRQHandler: - ldr r0,=Reserved42_DriverIRQHandler - bx r0 - .size Reserved42_IRQHandler, . - Reserved42_IRQHandler - - .align 1 - .thumb_func - .weak USB0_NEEDCLK_IRQHandler - .type USB0_NEEDCLK_IRQHandler, %function -USB0_NEEDCLK_IRQHandler: - ldr r0,=USB0_NEEDCLK_DriverIRQHandler - bx r0 - .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak USB0_IRQHandler - .type USB0_IRQHandler, %function -USB0_IRQHandler: - ldr r0,=USB0_DriverIRQHandler - bx r0 - .size USB0_IRQHandler, . - USB0_IRQHandler - - .align 1 - .thumb_func - .weak RTC_IRQHandler - .type RTC_IRQHandler, %function -RTC_IRQHandler: - ldr r0,=RTC_DriverIRQHandler - bx r0 - .size RTC_IRQHandler, . - RTC_IRQHandler - - .align 1 - .thumb_func - .weak Reserved46_IRQHandler - .type Reserved46_IRQHandler, %function -Reserved46_IRQHandler: - ldr r0,=Reserved46_DriverIRQHandler - bx r0 - .size Reserved46_IRQHandler, . - Reserved46_IRQHandler - - .align 1 - .thumb_func - .weak Reserved47_IRQHandler - .type Reserved47_IRQHandler, %function -Reserved47_IRQHandler: - ldr r0,=Reserved47_DriverIRQHandler - bx r0 - .size Reserved47_IRQHandler, . - Reserved47_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT4_IRQHandler - .type PIN_INT4_IRQHandler, %function -PIN_INT4_IRQHandler: - ldr r0,=PIN_INT4_DriverIRQHandler - bx r0 - .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT5_IRQHandler - .type PIN_INT5_IRQHandler, %function -PIN_INT5_IRQHandler: - ldr r0,=PIN_INT5_DriverIRQHandler - bx r0 - .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT6_IRQHandler - .type PIN_INT6_IRQHandler, %function -PIN_INT6_IRQHandler: - ldr r0,=PIN_INT6_DriverIRQHandler - bx r0 - .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT7_IRQHandler - .type PIN_INT7_IRQHandler, %function -PIN_INT7_IRQHandler: - ldr r0,=PIN_INT7_DriverIRQHandler - bx r0 - .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER2_IRQHandler - .type CTIMER2_IRQHandler, %function -CTIMER2_IRQHandler: - ldr r0,=CTIMER2_DriverIRQHandler - bx r0 - .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER4_IRQHandler - .type CTIMER4_IRQHandler, %function -CTIMER4_IRQHandler: - ldr r0,=CTIMER4_DriverIRQHandler - bx r0 - .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler - - .align 1 - .thumb_func - .weak OS_EVENT_IRQHandler - .type OS_EVENT_IRQHandler, %function -OS_EVENT_IRQHandler: - ldr r0,=OS_EVENT_DriverIRQHandler - bx r0 - .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler - - .align 1 - .thumb_func - .weak Reserved55_IRQHandler - .type Reserved55_IRQHandler, %function -Reserved55_IRQHandler: - ldr r0,=Reserved55_DriverIRQHandler - bx r0 - .size Reserved55_IRQHandler, . - Reserved55_IRQHandler - - .align 1 - .thumb_func - .weak Reserved56_IRQHandler - .type Reserved56_IRQHandler, %function -Reserved56_IRQHandler: - ldr r0,=Reserved56_DriverIRQHandler - bx r0 - .size Reserved56_IRQHandler, . - Reserved56_IRQHandler - - .align 1 - .thumb_func - .weak Reserved57_IRQHandler - .type Reserved57_IRQHandler, %function -Reserved57_IRQHandler: - ldr r0,=Reserved57_DriverIRQHandler - bx r0 - .size Reserved57_IRQHandler, . - Reserved57_IRQHandler - - .align 1 - .thumb_func - .weak SDIO_IRQHandler - .type SDIO_IRQHandler, %function -SDIO_IRQHandler: - ldr r0,=SDIO_DriverIRQHandler - bx r0 - .size SDIO_IRQHandler, . - SDIO_IRQHandler - - .align 1 - .thumb_func - .weak Reserved59_IRQHandler - .type Reserved59_IRQHandler, %function -Reserved59_IRQHandler: - ldr r0,=Reserved59_DriverIRQHandler - bx r0 - .size Reserved59_IRQHandler, . - Reserved59_IRQHandler - - .align 1 - .thumb_func - .weak Reserved60_IRQHandler - .type Reserved60_IRQHandler, %function -Reserved60_IRQHandler: - ldr r0,=Reserved60_DriverIRQHandler - bx r0 - .size Reserved60_IRQHandler, . - Reserved60_IRQHandler - - .align 1 - .thumb_func - .weak Reserved61_IRQHandler - .type Reserved61_IRQHandler, %function -Reserved61_IRQHandler: - ldr r0,=Reserved61_DriverIRQHandler - bx r0 - .size Reserved61_IRQHandler, . - Reserved61_IRQHandler - - .align 1 - .thumb_func - .weak USB1_PHY_IRQHandler - .type USB1_PHY_IRQHandler, %function -USB1_PHY_IRQHandler: - ldr r0,=USB1_PHY_DriverIRQHandler - bx r0 - .size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler - - .align 1 - .thumb_func - .weak USB1_IRQHandler - .type USB1_IRQHandler, %function -USB1_IRQHandler: - ldr r0,=USB1_DriverIRQHandler - bx r0 - .size USB1_IRQHandler, . - USB1_IRQHandler - - .align 1 - .thumb_func - .weak USB1_NEEDCLK_IRQHandler - .type USB1_NEEDCLK_IRQHandler, %function -USB1_NEEDCLK_IRQHandler: - ldr r0,=USB1_NEEDCLK_DriverIRQHandler - bx r0 - .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak SEC_HYPERVISOR_CALL_IRQHandler - .type SEC_HYPERVISOR_CALL_IRQHandler, %function -SEC_HYPERVISOR_CALL_IRQHandler: - ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler - bx r0 - .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ0_IRQHandler - .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function -SEC_GPIO_INT0_IRQ0_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ1_IRQHandler - .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function -SEC_GPIO_INT0_IRQ1_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak PLU_IRQHandler - .type PLU_IRQHandler, %function -PLU_IRQHandler: - ldr r0,=PLU_DriverIRQHandler - bx r0 - .size PLU_IRQHandler, . - PLU_IRQHandler - - .align 1 - .thumb_func - .weak SEC_VIO_IRQHandler - .type SEC_VIO_IRQHandler, %function -SEC_VIO_IRQHandler: - ldr r0,=SEC_VIO_DriverIRQHandler - bx r0 - .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler - - .align 1 - .thumb_func - .weak HASHCRYPT_IRQHandler - .type HASHCRYPT_IRQHandler, %function -HASHCRYPT_IRQHandler: - ldr r0,=HASHCRYPT_DriverIRQHandler - bx r0 - .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler - - .align 1 - .thumb_func - .weak CASER_IRQHandler - .type CASER_IRQHandler, %function -CASER_IRQHandler: - ldr r0,=CASER_DriverIRQHandler - bx r0 - .size CASER_IRQHandler, . - CASER_IRQHandler - - .align 1 - .thumb_func - .weak PUF_IRQHandler - .type PUF_IRQHandler, %function -PUF_IRQHandler: - ldr r0,=PUF_DriverIRQHandler - bx r0 - .size PUF_IRQHandler, . - PUF_IRQHandler - - .align 1 - .thumb_func - .weak PQ_IRQHandler - .type PQ_IRQHandler, %function -PQ_IRQHandler: - ldr r0,=PQ_DriverIRQHandler - bx r0 - .size PQ_IRQHandler, . - PQ_IRQHandler - - .align 1 - .thumb_func - .weak DMA1_IRQHandler - .type DMA1_IRQHandler, %function -DMA1_IRQHandler: - ldr r0,=DMA1_DriverIRQHandler - bx r0 - .size DMA1_IRQHandler, . - DMA1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM8_IRQHandler - .type FLEXCOMM8_IRQHandler, %function -FLEXCOMM8_IRQHandler: - ldr r0,=FLEXCOMM8_DriverIRQHandler - bx r0 - .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm -/* Exception Handlers */ - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SecureFault_Handler - def_irq_handler DebugMon_Handler - def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ - def_irq_handler DMA0_DriverIRQHandler /* DMA0 controller */ - def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */ - def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */ - def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */ - def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */ - def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */ - def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */ - def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */ - def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */ - def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler ADC0_DriverIRQHandler /* ADC0 */ - def_irq_handler Reserved39_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler ACMP_DriverIRQHandler /* ACMP interrupts */ - def_irq_handler Reserved41_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved42_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */ - def_irq_handler USB0_DriverIRQHandler /* USB device */ - def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */ - def_irq_handler Reserved46_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved47_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler PIN_INT4_DriverIRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - def_irq_handler PIN_INT5_DriverIRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - def_irq_handler PIN_INT6_DriverIRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - def_irq_handler PIN_INT7_DriverIRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - def_irq_handler CTIMER2_DriverIRQHandler /* Standard counter/timer CTIMER2 */ - def_irq_handler CTIMER4_DriverIRQHandler /* Standard counter/timer CTIMER4 */ - def_irq_handler OS_EVENT_DriverIRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ - def_irq_handler Reserved55_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved56_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved57_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler SDIO_DriverIRQHandler /* SD/MMC */ - def_irq_handler Reserved59_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved60_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved61_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler USB1_PHY_DriverIRQHandler /* USB1_PHY */ - def_irq_handler USB1_DriverIRQHandler /* USB1 interrupt */ - def_irq_handler USB1_NEEDCLK_DriverIRQHandler /* USB1 activity */ - def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler /* SEC_HYPERVISOR_CALL interrupt */ - def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ - def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ - def_irq_handler PLU_DriverIRQHandler /* PLU interrupt */ - def_irq_handler SEC_VIO_DriverIRQHandler /* SEC_VIO interrupt */ - def_irq_handler HASHCRYPT_DriverIRQHandler /* HASHCRYPT interrupt */ - def_irq_handler CASER_DriverIRQHandler /* CASPER interrupt */ - def_irq_handler PUF_DriverIRQHandler /* PUF interrupt */ - def_irq_handler PQ_DriverIRQHandler /* PQ interrupt */ - def_irq_handler DMA1_DriverIRQHandler /* DMA1 interrupt */ - def_irq_handler FLEXCOMM8_DriverIRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ - - .end diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_anactrl.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_anactrl.c deleted file mode 100644 index 68175b880a3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_anactrl.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright 2018-2021, NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_anactrl.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.anactrl" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for ANACTRL module. - * - * @param base ANACTRL peripheral base address - */ -static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to ANACTRL bases for each instance. */ -static ANACTRL_Type *const s_anactrlBases[] = ANACTRL_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to ANACTRL clocks for each instance. */ -static const clock_ip_name_t s_anactrlClocks[] = ANALOGCTRL_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! - * brief Get the ANACTRL instance from peripheral base address. - * - * param base ANACTRL peripheral base address. - * return ANACTRL instance. - */ -static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_anactrlBases); instance++) - { - if (s_anactrlBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_anactrlBases)); - - return instance; -} - -/*! - * brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function. - * - * param base ANACTRL peripheral base address. - */ -void ANACTRL_Init(ANACTRL_Type *base) -{ - assert(NULL != base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock for ANACTRL instance. */ - CLOCK_EnableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function. - * - * param base ANACTRL peripheral base address. - */ -void ANACTRL_Deinit(ANACTRL_Type *base) -{ - assert(NULL != base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock for ANACTRL instance. */ - CLOCK_DisableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock output - * and enable/disable 96MHZ clock output. - * - * param base ANACTRL peripheral base address. - * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure. - */ -void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32 = base->FRO192M_CTRL; - - tmp32 &= ~(ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK); - - if (config->enable12MHzClk) - { - tmp32 |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK; - } - if (config->enable96MHzClk) - { - tmp32 |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; - } - - base->FRO192M_CTRL |= tmp32; -} - -/*! - * brief Gets the default configuration of FRO192M. - * The default values are: - * code - config->enable12MHzClk = true; - config->enable96MHzClk = false; - endcode - * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure. - */ -void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enable12MHzClk = true; - config->enable96MHzClk = false; -} - -/*! - * brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU - * system, and so on. - * - * param base ANACTRL peripheral base address. - * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure. - */ -void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32 = base->XO32M_CTRL; - - tmp32 &= ~(ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK | ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK); - - /* Set XO32M CTRL. */ -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) - tmp32 &= ~ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; - if (config->enablePllUsbOutput) - { - tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; - } -#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ - - if (config->enableACBufferBypass) - { - tmp32 |= ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; - } - - if (config->enableSysCLkOutput) - { - tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; - } - base->XO32M_CTRL = tmp32; - -#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) - if (config->enableADCOutput) - { - base->DUMMY_CTRL |= ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK; - } - else - { - base->DUMMY_CTRL &= ~ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK; - } -#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ -} - -/*! - * brief Gets the default configuration of XO32M. - * The default values are: - * code - config->enableSysCLkOutput = false; - config->enableACBufferBypass = false; - endcode - * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure. - */ -void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) - config->enablePllUsbOutput = false; -#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ - config->enableSysCLkOutput = false; - config->enableACBufferBypass = false; -#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) - config->enableADCOutput = true; -#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ -} - -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) -/*! - * brief Measures the frequency of the target clock source. - * - * This function measures target frequency according to a accurate reference frequency.The formula is: - * Ftarget = (CAPVAL * Freference) / ((1<= 2U); - - uint32_t targetClkFreq = 0U; - uint32_t capval = 0U; - - /* Init a measurement cycle. */ - base->FREQ_ME_CTRL = ANACTRL_FREQ_ME_CTRL_PROG_MASK + ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(scale); - while (ANACTRL_FREQ_ME_CTRL_PROG_MASK == (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_PROG_MASK)) - { - } - - /* Calculate the target clock frequency. */ - capval = (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK); - targetClkFreq = (capval * refClkFreq) / ((1UL << scale) - 1UL); - - return targetClkFreq; -} -#endif /* FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_anactrl.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_anactrl.h deleted file mode 100644 index 4ca845b5a9a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_anactrl.h +++ /dev/null @@ -1,377 +0,0 @@ -/* - * Copyright 2018-2021, NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __FSL_ANACTRL_H__ -#define __FSL_ANACTRL_H__ - -#include "fsl_common.h" - -/*! - * @addtogroup anactrl - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief ANACTRL driver version. */ -#define FSL_ANACTRL_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*!< Version 2.3.0. */` - -/*! - * @brief ANACTRL interrupt flags - */ -enum _anactrl_interrupt_flags -{ -#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) - kANACTRL_BodVDDMainFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_MASK, /*!< BOD VDDMAIN Interrupt status - before Interrupt Enable. */ - kANACTRL_BodVDDMainInterruptFlag = - ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_MASK, /*!< BOD VDDMAIN Interrupt status - after Interrupt Enable. */ - kANACTRL_BodVDDMainPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_MASK, /*!< Current value of BOD VDDMAIN - power status output. */ -#else - kANACTRL_BodVbatFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK, /*!< BOD VBAT Interrupt status before - Interrupt Enable. */ - kANACTRL_BodVbatInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK, /*!< BOD VBAT Interrupt status - after Interrupt Enable. */ - kANACTRL_BodVbatPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK, /*!< Current value of BOD VBAT power - status output. */ -#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */ - kANACTRL_BodCoreFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK, /*!< BOD CORE Interrupt status before - Interrupt Enable. */ - kANACTRL_BodCoreInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK, /*!< BOD CORE Interrupt status - after Interrupt Enable. */ - kANACTRL_BodCorePowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK, /*!< Current value of BOD CORE power - status output. */ - kANACTRL_DcdcFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK, /*!< DCDC Interrupt status before - Interrupt Enable. */ - kANACTRL_DcdcInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK, /*!< DCDC Interrupt status after - Interrupt Enable. */ - kANACTRL_DcdcPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK, /*!< Current value of DCDC power - status output. */ -}; - -/*! - * @brief ANACTRL interrupt control - */ -enum _anactrl_interrupt -{ -#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) - kANACTRL_BodVDDMainInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_MASK, /*!< BOD VDDMAIN - interrupt control. */ -#else - kANACTRL_BodVbatInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK, /*!< BOD VBAT interrupt - control. */ -#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */ - kANACTRL_BodCoreInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK, /*!< BOD CORE interrupt - control. */ - kANACTRL_DcdcInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK, /*!< DCDC interrupt control. */ -}; - -/*! - * @brief ANACTRL status flags - */ -enum _anactrl_flags -{ - kANACTRL_FlashPowerDownFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK, /*!< Flash power-down status. */ - kANACTRL_FlashInitErrorFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK, /*!< Flash initialization - error status. */ -}; - -/*! - * @brief ANACTRL FRO192M and XO32M status flags - */ -enum _anactrl_osc_flags -{ - kANACTRL_OutputClkValidFlag = ANACTRL_FRO192M_STATUS_CLK_VALID_MASK, /*!< Output clock valid signal. */ - kANACTRL_CCOThresholdVoltageFlag = ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK, /*!< CCO threshold voltage detector - output (signal vcco_ok). */ - kANACTRL_XO32MOutputReadyFlag = ANACTRL_XO32M_STATUS_XO_READY_MASK << 16U, /*!< Indicates XO out - frequency statibilty. */ -}; - -/*! - * @brief Configuration for FRO192M - * - * This structure holds the configuration settings for the on-chip high-speed Free Running Oscillator. To initialize - * this structure to reasonable defaults, call the ANACTRL_GetDefaultFro192MConfig() function and pass a - * pointer to your config structure instance. - */ -typedef struct _anactrl_fro192M_config -{ - bool enable12MHzClk; /*!< Enable 12MHz clock. */ - bool enable96MHzClk; /*!< Enable 96MHz clock. */ -} anactrl_fro192M_config_t; - -/*! - * @brief Configuration for XO32M - * - * This structure holds the configuration settings for the 32 MHz crystal oscillator. To initialize this - * structure to reasonable defaults, call the ANACTRL_GetDefaultXo32MConfig() function and pass a - * pointer to your config structure instance. - */ -typedef struct _anactrl_xo32M_config -{ - bool enableACBufferBypass; /*!< Enable XO AC buffer bypass in pll and top level. */ -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) - bool enablePllUsbOutput; /*!< Enable XO 32 MHz output to USB HS PLL. */ -#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ - bool enableSysCLkOutput; /*!< Enable XO 32 MHz output to CPU system, SCT, and CLKOUT */ -#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) - bool enableADCOutput; /*!< Enable High speed crystal oscillator output to ADC. */ -#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ -} anactrl_xo32M_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function. - * - * @param base ANACTRL peripheral base address. - */ -void ANACTRL_Init(ANACTRL_Type *base); - -/*! - * @brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function. - * - * @param base ANACTRL peripheral base address. - */ -void ANACTRL_Deinit(ANACTRL_Type *base); -/* @} */ - -/*! - * @name Set oscillators - * @{ - */ - -/*! - * @brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock - * output and enable/disable 96MHZ clock output. - * - * @param base ANACTRL peripheral base address. - * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure. - */ -void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config); - -/*! - * @brief Gets the default configuration of FRO192M. - * The default values are: - * @code - config->enable12MHzClk = true; - config->enable96MHzClk = false; - @endcode - * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure. - */ -void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config); - -/*! - * @brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU - * system, and so on. - * - * @param base ANACTRL peripheral base address. - * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure. - */ -void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config); - -/*! - * @brief Gets the default configuration of XO32M. - * The default values are: - * @code - config->enableSysCLkOutput = false; - config->enableACBufferBypass = false; - @endcode - * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure. - */ -void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config); - -/* @} */ - -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) -/*! - * @name Measure Frequency - * @{ - */ - -/*! - * @brief Measures the frequency of the target clock source. - * - * This function measures target frequency according to a accurate reference frequency.The formula is: - * Ftarget = (CAPVAL * Freference) / ((1<BOD_DCDC_INT_CTRL |= (0x15U & mask); -} - -/*! - * @brief Disables the ANACTRL interrupts. - * - * @param base ANACTRL peripheral base address. - * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration. - */ -static inline void ANACTRL_DisableInterrupts(ANACTRL_Type *base, uint32_t mask) -{ - base->BOD_DCDC_INT_CTRL &= ~(0x15U & mask); -} - -/*! - * @brief Clears the ANACTRL interrupts. - * - * @param base ANACTRL peripheral base address. - * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration. - */ -static inline void ANACTRL_ClearInterrupts(ANACTRL_Type *base, uint32_t mask) -{ - base->BOD_DCDC_INT_CTRL |= (uint32_t)(mask << 1UL); -} -/* @} */ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets ANACTRL status flags. - * - * This function gets Analog control status flags. The flags are returned as the logical - * OR value of the enumerators @ref _anactrl_flags. To check for a specific status, - * compare the return value with enumerators in the @ref _anactrl_flags. - * For example, to check whether the flash is in power down mode: - * @code - * if (kANACTRL_FlashPowerDownFlag & ANACTRL_ANACTRL_GetStatusFlags(ANACTRL)) - * { - * ... - * } - * @endcode - * - * @param base ANACTRL peripheral base address. - * @return ANACTRL status flags which are given in the enumerators in the @ref _anactrl_flags. - */ -static inline uint32_t ANACTRL_GetStatusFlags(ANACTRL_Type *base) -{ - return base->ANALOG_CTRL_STATUS; -} - -/*! - * @brief Gets ANACTRL oscillators status flags. - * - * This function gets Anactrl oscillators status flags. The flags are returned as the logical - * OR value of the enumerators @ref _anactrl_osc_flags. To check for a specific status, - * compare the return value with enumerators in the @ref _anactrl_osc_flags. - * For example, to check whether the FRO192M clock output is valid: - * @code - * if (kANACTRL_OutputClkValidFlag & ANACTRL_ANACTRL_GetOscStatusFlags(ANACTRL)) - * { - * ... - * } - * @endcode - * - * @param base ANACTRL peripheral base address. - * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags. - */ -static inline uint32_t ANACTRL_GetOscStatusFlags(ANACTRL_Type *base) -{ - return (base->FRO192M_STATUS & 0xFFU) | ((base->XO32M_STATUS & 0xFFU) << 16U); -} - -/*! - * @brief Gets ANACTRL interrupt status flags. - * - * This function gets Anactrl interrupt status flags. The flags are returned as the logical - * OR value of the enumerators @ref _anactrl_interrupt_flags. To check for a specific status, - * compare the return value with enumerators in the @ref _anactrl_interrupt_flags. - * For example, to check whether the VBAT voltage level is above the threshold: - * @code - * if (kANACTRL_BodVbatPowerFlag & ANACTRL_ANACTRL_GetInterruptStatusFlags(ANACTRL)) - * { - * ... - * } - * @endcode - * - * @param base ANACTRL peripheral base address. - * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags. - */ -static inline uint32_t ANACTRL_GetInterruptStatusFlags(ANACTRL_Type *base) -{ - return base->BOD_DCDC_INT_STATUS & 0x1FFU; -} -/* @} */ - -#if (defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) && (FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG == 1U)) -/*! - * @brief Aux_Bias Control Interfaces - * @{ - */ - -/*! - * @brief Enables/disabless 1V reference voltage buffer. - * - * @param base ANACTRL peripheral base address. - * @param enable Used to enable or disable 1V reference voltage buffer. - */ -static inline void ANACTRL_EnableVref1V(ANACTRL_Type *base, bool enable) -{ - if (enable) - { - base->AUX_BIAS |= ANACTRL_AUX_BIAS_VREF1VENABLE_MASK; - } - else - { - base->AUX_BIAS &= ~ANACTRL_AUX_BIAS_VREF1VENABLE_MASK; - } -} - -/* @} */ -#endif /* defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) */ - -#if defined(__cplusplus) -} -#endif - -/* @}*/ - -#endif /* __FSL_ANACTRL_H__ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_casper.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_casper.c deleted file mode 100644 index 97c2613fd16..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_casper.c +++ /dev/null @@ -1,3433 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_casper.h" -#include /* ceil TODO check if really need it */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.casper" -#endif - -/* Recoding length for the secure scalar multiplication: - * Use n=256 and w=4 --> compute ciel(384/3) = 86 + 1 digits - * Use n=384 and w=4 --> compute ciel(384/3) = 128 + 1 digits - * Use n=521 and w=4 --> compute ciel(521/3) = 174 + 1 digits - */ - -/*!< Recoding length for the secure scalar multiplication */ -enum _casper_ecc_recode_len -{ - kCASPER_ECC_P256_recode_len = 87u, - kCASPER_ECC_P384_recode_len = 129u, - kCASPER_ECC_P521_recode_len = 175u, -}; - -enum _casper_ecc_N_bitlen -{ - kCASPER_ECC_P256_N_bitlen = 256u, - kCASPER_ECC_P384_N_bitlen = 384u, - kCASPER_ECC_P521_N_bitlen = 576u, -}; - -enum _casper_ecc_N_wordlen -{ - kCASPER_ECC_P256_wordlen = 256U / 32U, - kCASPER_ECC_P384_wordlen = 384u / 32U, - kCASPER_ECC_P521_wordlen = 576u / 32U, -}; - -#if defined(__GNUC__) -/* Enforce O1 optimize level, specifically to remove strict-aliasing option. - (-fno-strict-aliasing is required for this driver). */ -#pragma GCC push_options -#pragma GCC optimize("-O1") -#endif - -#if (defined(__CC_ARM) || defined(__ARMCC_VERSION)) -/* Enforce optimization off for clang, specifically to remove strict-aliasing option. -(-fno-strict-aliasing is required for this driver). */ -#pragma clang optimize off -#endif - -/* CASPER driver allows usage of 256, 384 and 521 ECC */ -#define CASPER_MAX_ECC_SIZE_WORDLEN (576u / 32U) -#define CASPER_RECODE_LENGTH_MAX 175 - -#define CASPER_RAM_BASE_NS (FSL_FEATURE_CASPER_RAM_BASE_ADDRESS) - -#if defined(FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED) && FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED -#define CASPER_RAM_OFFSET (FSL_FEATURE_CASPER_RAM_OFFSET) -#define INTERLEAVE(addr) \ - (((((((addr) >> 2U) & 0x00000001U) << CASPER_RAM_OFFSET) + (((addr) >> 3U) << 2U) + ((addr)&0x00000003U)) & \ - 0xFFFFU) | \ - s_casperRamBase) -#define DEINTERLEAVE(addr) INTERLEAVE(addr) -#define GET_WORD(addr) (*((uint32_t *)DEINTERLEAVE((uint32_t)(addr)))) -#define GET_DWORD(addr) (((uint64_t)GET_WORD(addr)) | (((uint64_t)GET_WORD(((uint32_t)(addr)) + 4U)) << 32U)) -#define SET_WORD(addr, value) *((uint32_t *)INTERLEAVE((uint32_t)(addr))) = ((uint32_t)(value)) -#define SET_DWORD(addr, value) \ - do \ - { \ - SET_WORD(addr, (uint32_t)(value & 0xFFFFFFFFU)); \ - SET_WORD(((uint32_t)(addr)) + 4U, (uint32_t)((value & 0xFFFFFFFF00000000U) >> 32U)); \ - } while (false) - -/* memcopy is always word aligned */ -/* interleaved to interleaved - static void CASPER_MEMCPY_I2I(void *dst, const void *src, size_t siz) - */ -#define CASPER_MEMCPY_I2I(dst, src, siz) \ - \ - { \ - uint32_t *dst32 = (uint32_t *)(dst); \ - const uint32_t *src32 = (const uint32_t *)(const uint32_t *)(src); \ - uint32_t i; \ - for (i = 0U; i < (siz) / 4U; i++) \ - { \ - SET_WORD(&dst32[i], GET_WORD(&src32[i])); \ - } \ - } - -/* interleaved to non-interleaved - static void CASPER_MEMCPY_I2N(void *dst, const void *src, size_t siz) - */ -#define CASPER_MEMCPY_I2N(dst, src, siz) \ - \ - { \ - uint32_t *dst32 = (uint32_t *)(dst); \ - const uint32_t *src32 = (const uint32_t *)(const uint32_t *)(src); \ - uint32_t i; \ - for (i = 0U; i < (siz) / 4U; i++) \ - { \ - dst32[i] = GET_WORD(&src32[i]); \ - } \ - } - -/* non-interleaved to interleaved - static void CASPER_MEMCPY_N2I(void *dst, const void *src, size_t siz) - */ -#define CASPER_MEMCPY_N2I(dst, src, siz) \ - \ - { \ - volatile uint32_t *dst32 = (uint32_t *)(dst); \ - const uint32_t *src32 = (const uint32_t *)(const uint32_t *)(src); \ - uint32_t i; \ - for (i = 0U; i < (siz) / 4U; i++) \ - { \ - SET_WORD(&dst32[i], src32[i]); \ - } \ - } -#else -#define GET_WORD(addr) (*((uint32_t *)(uint32_t)(addr))) -#define GET_DWORD(addr) (*((uint64_t *)(addr))) -#define SET_WORD(addr, value) *((uint32_t *)(uint32_t)(addr)) = ((uint32_t)(value)) -#define SET_DWORD(addr, value) *((uint64_t *)(addr)) = ((uint64_t)(value)) - -#define CASPER_MEMCPY_I2I(dst, src, siz) (void)memcpy(dst, src, siz) -#define CASPER_MEMCPY_I2N(dst, src, siz) (void)memcpy(dst, src, siz) -#define CASPER_MEMCPY_N2I(dst, src, siz) (void)memcpy(dst, src, siz) -#endif - -#define WORK_BUFF_MUL4 (N_wordlen_max * 4 + 2) /* ! working buffer is 4xN_wordlen to allow in place math */ -#define N_bytelen (N_wordlen * 4U) /* for memory copy and the like */ -#define N_dwordlen (unsigned)(N_wordlen / 2U) - -#define PreZeroW(i, w_out) \ - for ((i) = 0U; (i) < N_wordlen; (i) += 4U) \ - { \ - SET_WORD(&(w_out)[(i) + 0U], 0U); \ - SET_WORD(&(w_out)[(i) + 1U], 0U); \ - SET_WORD(&(w_out)[(i) + 2U], 0U); \ - SET_WORD(&(w_out)[(i) + 3U], 0U); \ - } /* unrolled partly */ -#define PreZeroW2up(i, w_out) \ - for (i = N_wordlen; i <= N_wordlen * 2U; i += 4U) \ - { \ - SET_WORD(&w_out[i + 0U], 0U); \ - SET_WORD(&w_out[i + 1U], 0U); \ - SET_WORD(&w_out[i + 2U], 0U); \ - SET_WORD(&w_out[i + 3U], 0U); \ - } /* unrolled partly */ - -/* Macros for the ECC component in Casper */ - -/* CASPER memory layout for ECC */ - -#define CASPER_MEM ((uint32_t *)msg_ret) - -/* Currently these macros work on 32-bit platforms */ - -#define add(c1, c0, a, b) \ - \ - do \ - { \ - uint32_t _t; \ - _t = a + b; \ - c1 = (uint32_t)(_t < a); \ - c0 = _t; \ - \ - } while (false) - -#define add_cout(carry, c, a, b) add((carry), (c), (a), (b)) - -#define add_cout_cin(carryout, c, a, b, carryin) \ - do \ - { \ - uint64_t _t = (uint64_t)(a) + (b) + (carryin); \ - (c) = (uint32_t)_t; \ - (carryout) = (uint32_t)(_t >> 32); \ - } while (false) - -#define sub_borrowout(borrow, c, a, b) \ - do \ - { \ - uint32_t _b = (uint32_t)((b) > (a)); \ - (c) = (a) - (b); \ - (borrow) = _b; \ - } while (false) - -#define sub_borrowin_borrowout(borrowout, c, a, b, borrowin) \ - do \ - { \ - uint32_t _t, _borrow1, _borrow2; \ - sub_borrowout(_borrow1, _t, (a), (b)); \ - sub_borrowout(_borrow2, (c), _t, (borrowin)); \ - (borrowout) = _borrow1 + _borrow2; \ - } while (false) - -#define sub_borrowout_1(borrow, c, a) \ - do \ - { \ - uint32_t _b = 0; \ - c = a - b; \ - borrow = _b; \ - } while (false) - -#define sub_borrowin_borrowout_1(borrowout, c, a, borrowin) \ - do \ - { \ - uint32_t _t, _borrow1, _borrow2; \ - sub_borrowout_1(_borrow1, _t, a); \ - sub_borrowout(_borrow2, c, _t, borrowin); \ - borrowout = _borrow1 + _borrow2; \ - } while (false) - -/* 32 x 32 --> 64-bit multiplication - * (c1,c0) = a * b - */ -#define mul(c1, c0, a, b) \ - \ - do \ - { \ - uint64_t __m; \ - __m = (uint64_t)a * (uint64_t)b; \ - c0 = (uint32_t)__m; \ - c1 = (uint32_t)(__m >> (uint64_t)32); \ - \ - } while (false) - -/* Multiply-and-accumulate - * (c1,c0) = a*b+c0 - */ -#define muladd(c1, c0, a, b) \ - \ - do \ - { \ - uint32_t __ma = c0; \ - mul(c1, c0, a, b); \ - c0 = c0 + __ma; \ - c1 = c1 + (c0 < __ma); \ - \ - } while (0) - -/* Multiply-and-accumulate-accumulate - * (c1,c0) = a*b+c0+c1 - */ -#define muladdadd(c1, c0, a, b) \ - \ - do \ - { \ - uint32_t __maa0 = c0, __maa1 = c1; \ - mul(c1, c0, a, b); \ - c0 = c0 + __maa0; \ - c1 = c1 + (c0 < __maa0); \ - c0 = c0 + __maa1; \ - c1 = c1 + (c0 < __maa1); \ - \ - } while (0) - -#define square_casper(c, a) multiply_casper(c, a, a) -#define sub_casper(c, a, b) CASPER_montsub(c, a, b, &CASPER_MEM[(N_wordlen + 4U)]) -#define add_casper(c, a, b) CASPER_montadd(c, a, b, &CASPER_MEM[(N_wordlen + 4U)]) -#define mul2_casper(c, a) add_casper(c, a, a) -#define half(c, a, b) CASPER_half(c, a, b) -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* The model for this algo is that it can be implemented for a fixed size RSA key */ -/* for max speed. If this is made into a variable (to allow varying size), then */ -/* it will be slower by a bit. */ -/* The file is compiled with N_bitlen passed in as number of bits of the RSA key */ -/* #define N_bitlen 2048 */ -static size_t N_wordlen = 0U; /* ! number of words (e.g. 4096/32 is 128 words) */ - -static uint32_t s_casperRamBase = CASPER_RAM_BASE_NS; -static uint32_t *msg_ret = (uint32_t *)CASPER_RAM_BASE_NS; - -/* NISTp-256 = 2^256-2^224+2^192+2^96-1 */ -static uint32_t NISTp256[256 / 32u] = {0xffffffffU, 0xffffffffU, 0xffffffffU, 0x00000000, - 0x00000000, 0x00000000, 0x00000001, 0xffffffffU}; - -/* The cardinality of the curve E(F_p) */ -static uint32_t NISTp256_q[256 / 32u] = {0xfc632551U, 0xf3b9cac2U, 0xa7179e84U, 0xbce6faadU, - 0xffffffffU, 0xffffffffU, 0x00000000, 0xffffffffU}; - -/* R = 2^256 mod p, the value "1" in Montgomery form. */ -static uint32_t NISTr256[256 / 32u] = {0x00000001, 0x00000000, 0x00000000, 0xffffffffU, - 0xffffffffU, 0xffffffffU, 0xfffffffeU, 0x00000000}; - -static uint32_t Np256[2] = {1, 0}; - -/* NISTp-384 = 2^384 - 2^128 - 2^96 + 2^32 - 1 */ -static uint32_t NISTp384[384 / 32u] = {0xffffffffU, 0x00000000, 0x00000000, 0xffffffffU, 0xfffffffeU, 0xffffffffU, - 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU}; - -/* The cardinality of the curve E(F_p) */ -static uint32_t NISTp384_q[384 / 32u] = {0xccc52973U, 0xecec196aU, 0x48b0a77aU, 0x581a0db2U, 0xf4372ddfU, 0xc7634d81U, - 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU}; - -/* R = 2^256 mod p, the value "1" in Montgomery form. */ -static uint32_t NISTr384[384 / 32u] = {0x00000001, 0xffffffffU, 0xffffffffU, 0x00000000, 0x1, 0, 0, 0, 0, 0, 0, 0}; - -// -p^-1 mod 2^64 = 0x100000001 -static uint32_t Np384[2] = {1, 1}; - -/* NISTp-521 = 2^521 - 1 */ -static uint32_t NISTp521[576 / 32U] = {0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, - 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, - 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0x1ffU, 0}; - -/* The cardinality of the curve E(F_p) */ -static uint32_t NISTp521_q[576 / 32U] = {0x91386409U, 0xbb6fb71eU, 0x899c47aeU, 0x3bb5c9b8U, 0xf709a5d0U, 0x7fcc0148U, - 0xbf2f966bU, 0x51868783U, 0xfffffffaU, 0xffffffffU, 0xffffffffU, 0xffffffffU, - 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0x1ffU, 0}; - -/* R = 2^576 mod p, the value "1" in Montgomery form. */ -static uint32_t NISTr521[576 / 32U] = {0, 0x800000, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - -/* -p^-1 mod 2^64 = 1 */ -static uint32_t Np521[2] = {1, 0}; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/* Convert a projective point (X1 : Y1 : Z1) - * to the affine point (X3, Y3) = (X1/Z1^2,Y1/Z1^3) - * The memory of (X3, Y3) and (X1 : Y1 : Z1) should not overlap - */ -void Jac_toAffine(uint32_t *X3, uint32_t *Y3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1); - -/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2 : Y2 : Z2) - * where (X1: Y1: Z1) != (X2 : Y2 : Z2) - * (X3 : Y3: Z3) may be the same as one of the inputs. - */ -void Jac_addition(uint32_t *X3, - uint32_t *Y3, - uint32_t *Z3, - uint32_t *X1, - uint32_t *Y1, - uint32_t *Z1, - uint32_t *X2, - uint32_t *Y2, - uint32_t *Z2); - -/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2, Y2) - * where (X1: Y1: Z1) != (X2, Y2) - * (X3 : Y3: Z3) may not overlap with (X1: Y1: Z1). - * Source: 2004 Hankerson?Menezes?Vanstone, page 91. - */ -void Jac_add_affine( - uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *X2, uint32_t *Y2); - -/* Point doubling from: 2004 Hankerson?Menezes?Vanstone, page 91. - * Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X1 : Y1 : Z1) - * (X3 : Y3: Z3) may be the same as the input. - */ -void Jac_double(uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1); - -/* Constant time elliptic curve scalar multiplication. - * Source: https://eprint.iacr.org/2014/130.pdf - * when using w = 4. - * Computes (X3 : Y3 : Z3) = k * (X1, Y1) \in E(F_p) - * p is the prime used to define the finite field F_p - * q is the (prime) order of the curve - */ -void Jac_scalar_multiplication( - uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *k, uint32_t *p, uint32_t *q); - -/* Compute the double scalar multiplication - * (X3 : Y3 : Z3) = k1 * (X1, Y1) + k2 * (X2, Y2) - * Using Shamir's trick and precomputing 16 points. - * This code is *not* constant time since this is used - * for verification only. - */ -void double_scalar_multiplication(uint32_t *X3, - uint32_t *Y3, - uint32_t *Z3, - uint32_t *X1, - uint32_t *Y1, - uint32_t *k1, - uint32_t *X2, - uint32_t *Y2, - uint32_t *k2); - -/* Compute inversion modulo NIST-p384 using Fermats little theorem. - * Using c = a^(p-2) = a^(-1) mod p. - * This computes the modular inversion if all arithmetic is "regular" - * modular arithmetic or computes automatically the Montgomery inverse - * if all arithmetic is Montgomery arithmetic. - */ -static void invert_mod_p384(uint32_t *c, uint32_t *a); - -/* Modular inversion for NIST-P256 */ -static void invert_mod_p256(uint32_t *c, uint32_t *a); - -/* Modular inversion for NIST-P521 */ -static void invert_mod_p521(uint32_t *c, uint32_t *a); - -// A and C do not need to be in Casper memory -static void toMontgomery_ECC_P256(uint32_t *C, uint32_t *A); -static void toMontgomery_ECC_P384(uint32_t *C, uint32_t *A); -static void toMontgomery_ECC_P521(uint32_t *C, uint32_t *A); - -static void CASPER_montsub(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod); -static void CASPER_montadd(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod); - -/* Compute c = a/2 mod p where b is scratch space. */ -static void CASPER_half(uint32_t *c, uint32_t *a, uint32_t *b); - -void CASPER_MEMCPY(void *dst, const void *src, size_t siz); - -static void multiply_casper(uint32_t w_out[], const uint32_t a[], const uint32_t b[]); - -static uint8_t int8abs(int8_t v); - -/* Constant time select c = a if m = 0 or - * c = b if m = 1 - * a, b, c are n words - */ -static void casper_select(uint32_t *c, uint32_t *a, uint32_t *b, int m, int n); - -/* Dumb n-limb addition of c=a+b, return carry. */ -static uint32_t add_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n); - -#if 0 -/* Dumb n-limb addition of c=a+b, return carry. */ -static uint32_t add_n(uint32_t *c, uint32_t *a, uint32_t *b, int n); - -/* Dumb n-limb subtraction of c=a-b, return borrow. */ -static uint32_t sub_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n); -#endif - -/* Dumb n-limb subtraction of c=a-b, return borrow. */ -static uint32_t sub_n(uint32_t *c, uint32_t *a, uint32_t *b, int n); - -int RSA_SignatureToPlaintextFast(const unsigned signature[N_wordlen_max], - const unsigned exp_pubkey, - const unsigned pubkey[N_wordlen_max], - unsigned MsgRet[WORK_BUFF_MUL4]); - -int RSA_MontSignatureToPlaintextFast(const unsigned mont_signature[N_wordlen_max], - const unsigned exp_pubkey, - const unsigned pubkey[N_wordlen_max], - unsigned MsgRet[WORK_BUFF_MUL4]); - -void MultprecMultiply(unsigned w_out[], const unsigned u[], const unsigned v[]); - -void MultprecGenNp64(const unsigned *Nmod, unsigned *np64_ret); -void MultprecMontPrepareX(unsigned Xmont_out[], const unsigned x[], const unsigned Rp[], const unsigned Nmod[]); -void MultprecModulo(unsigned r_out[], const unsigned v[], int top); -void MultprecCiosMul( - unsigned w_out[], const unsigned a[], const unsigned b[], const unsigned Nmod[], const unsigned *Np); -void MultprecMontCalcRp(unsigned Rp[], const unsigned exp_pubkey, const unsigned Nmod[]); - -static void MultprecCiosMul_ct( - uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np); - -static void MultprecCiosMul521_ct( - uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np); - -static void shiftrightSysram(uint32_t *z, uint32_t *x, uint32_t c); -static void shiftright(uint32_t *z, uint32_t *x, uint32_t c); -static void shiftleft(uint32_t *z, uint32_t *x, uint32_t c); - -/******************************************************************************* - * Code - ******************************************************************************/ - -__STATIC_FORCEINLINE uint32_t CA_MK_OFF(const void *addr) -{ - return ((uint32_t)(const uint32_t *)addr - s_casperRamBase); -} - -#if 1 -__STATIC_FORCEINLINE void Accel_done(void) -{ - register uint32_t status; - do - { - status = CASPER->STATUS; - } while (0U == (status & CASPER_STATUS_DONE_MASK)); -} - -__STATIC_FORCEINLINE void Accel_SetABCD_Addr(uint32_t ab, uint32_t cd) -{ - CASPER->CTRL0 = ab | (cd << 16); /* CDoffset << 16 | ABoffset */ -} - -__STATIC_FORCEINLINE void Accel_crypto_mul(uint32_t ctrl1) -{ - CASPER->CTRL1 = ctrl1; -} -#else -#include "intrinsics.h" -#define Accel_done() \ - { \ - register uint32_t status; \ - do \ - { \ - status = CASPER_Rd32b(CASPER_CP_STATUS); \ - } while (0 == (status & CASPER_STATUS_DONE_MASK)); \ - } -#if 0 -__STATIC_FORCEINLINE void Accel_done(void) -{ - register uint32_t status; - do - { - status = CASPER->STATUS; - } while (0 == (status & CASPER_STATUS_DONE_MASK)); -} -#endif -#define Accel_SetABCD_Addr(ab, cd) CASPER_Wr32b((uint32_t)ab | ((uint32_t)cd << 16), CASPER_CP_CTRL0); -#define Accel_crypto_mul(ctrl1) CASPER_Wr32b((uint32_t)ctrl1, CASPER_CP_CTRL1); -#endif - -__STATIC_FORCEINLINE uint32_t Accel_IterOpcodeResaddr(uint32_t iter, uint32_t opcode, uint32_t resAddr) -{ - return CASPER_CTRL1_ITER(iter) | CASPER_CTRL1_MODE(opcode) | (resAddr << 16); -} - -void CASPER_MEMCPY(void *dst, const void *src, size_t siz) -{ - bool bdst = - ((((uint32_t)(uint32_t *)dst) | 0x10000000u) >= ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) && - (((uint32_t)(uint32_t *)dst) | 0x10000000u) < - ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) + 8u * 1024u); - - bool bsrc = ((((uint32_t)(const uint32_t *)src) | 0x10000000u) >= - ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) && - (((uint32_t)(const uint32_t *)src) | 0x10000000u) < - ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) + 8u * 1024u); - - if (bdst && bsrc) - { - CASPER_MEMCPY_I2I(dst, src, siz); - } - else if (bdst && !bsrc) - { - CASPER_MEMCPY_N2I(dst, src, siz); - } - else if (!bdst && bsrc) - { - CASPER_MEMCPY_I2N(dst, src, siz); - } - else - { - (void)memcpy(dst, src, siz); - } -} - -/* Constant time select c = a if m = 0 or - * c = b if m = 1 - * a, b, c are n words - */ -static void casper_select(uint32_t *c, uint32_t *a, uint32_t *b, int m, int n) -{ - uint32_t m1 = 0U - (uint32_t)m, m2 = ~m1; - int i; - - for (i = 0; i < n; i++) - { - SET_WORD(&c[i], (GET_WORD(&a[i]) & m2) | (GET_WORD(&b[i]) & m1)); - } -} - -/* Compute R`, which is R mod N. This is done using subtraction */ -/* R has 1 in N_wordlen, but we do not fill it in since borrowed. */ -/* Exp-pubkey only used to optimize for exp=3 */ -void MultprecMontCalcRp(unsigned Rp[], const unsigned exp_pubkey, const unsigned Nmod[]) -{ - uint32_t i; - - /* R is 2^n where n is 1 bit longer than Nmod, so 1 followed by 32 or 64 0 words for example */ - /* Note that Nmod's upper most bit has to be 1 by definition, so one subtract is enough. We */ - /* do not set the 1 since it is "borrowed" so no point */ - PreZeroW(i, Rp); - Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(Rp))); - Accel_done(); - /* final borrow cannot happen since we know we started with a larger number */ -} - -/* MultprecMultiply - multiple w=u*v (per Knuth) */ -/* w_out is 2x the size of u and v */ -void MultprecMultiply(unsigned w_out[], const unsigned u[], const unsigned v[]) -{ - uint32_t i, j; - - /* Knuth 4.3.1 - Algorithm M */ - /* Compute w = u * v */ - /* u and v are N bits long in 32 bit word form */ - /* w is 2*N bits long in 32 bit word form */ - /* Note: We just multiply in place */ - - /* Step 1. Fill w[t-1:0] with 0s, the upper half will be written as we go */ - PreZeroW(i, w_out); - - /* We do 1st pass NOSUM so we do not have to 0 output */ - Accel_SetABCD_Addr(CA_MK_OFF(&v[0]), CA_MK_OFF(u)); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpMul6464NoSum, CA_MK_OFF(&w_out[0]))); - Accel_done(); - /* Step 2. iterate over N words of v using j */ - for (j = 2U; j < N_wordlen; j += 2U) - { - /* Step 2b. Check for 0 on v word - skip if so since we 0ed already */ - /* Step 3. Iterate over N words of u using i - perform Multiply-accumulate */ - if (0U != (GET_WORD(&v[j])) || 0U != (GET_WORD(&v[j + 1U]))) - { - Accel_SetABCD_Addr(CA_MK_OFF(&v[j]), CA_MK_OFF(u)); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpMul6464Sum, CA_MK_OFF(&w_out[j]))); - Accel_done(); - } - } -} - -/* MultprecModulo performs divide to get remainer as needed for RSA */ -/* This performs (q,r) = u/v, but we do not keep q */ -/* r_out is module (remainder) and is 2*N */ -/* u is in r_out (1st N) at start (passed in) */ -/* v is N long */ -void MultprecModulo(unsigned r_out[], const unsigned v[], int top) -{ - uint64_t u64; /* use 64 bit math mixed with 32 bit */ - unsigned u32; /* allows us to work on U in 32 bit */ - unsigned u_n, ul16, uh16, *u_shft; /* u_shft is because r_out is u initially */ - unsigned vl16, vh16, v_Nm1; - unsigned q_hat, r_hat, q_over; - unsigned borrow, carry; - uint32_t i; - int j, tmp; - - /* Knuth 4.3.1 - Algorithm D */ - /* Compute q = u / v giving remainder r = u mod v */ - /* -- we only want r, so we build qhat but do not store the Qs */ - /* v is N long, with u,q,r 2N long because u is slowly replavced by r. */ - /* We normalize/unnormlize per Knuth in the buffer (not copied) */ - - /* Step 1. Normalize value so MSb is in v[n-1]. Remember that v is */ - /* the public key - to call it a 2048 bit number, they cannot have 0 */ - /* in the MSb (or it would be less than 2048 bits) and so we know we */ - /* are normalized already. Therefore, u is effectively shifted already. */ - /* For u, we have it in r_out. u[n] holds any overflow */ - /* Since divide on CM3/4 is 32/32=32, we break into 16 bit halves, but */ - /* multiply can be 32x32=64. */ - u_n = 0; - u_shft = r_out; /* u (shifted) is in r_out */ - - v_Nm1 = GET_WORD(&v[N_wordlen - 1U]); /* MSw of public key */ - vl16 = v_Nm1 & 0xFFFFU; /* lower 16 */ - vh16 = v_Nm1 >> 16; /* upper 16 */ - /* Step 2. Iterate j from m-n down to 0 (M selected per Knuth as 2*N) */ - for (j = top; j >= 0; j--) - { - /* Step 3. estimate q_hat as (U[j+n]*B + U[j+n-1]) / V[n-1] */ - /* Note: using subset of Knuth algo since v is 1/2 len of u (which is */ - /* from multiply or x^2 leading into this). */ - u32 = u_n; /* pickup u4u3u2, knowing u4 is 0 */ - u64 = ((uint64_t)u_n << 32) | GET_WORD(&u_shft[(uint32_t)j + N_wordlen - 1U]); - ul16 = (unsigned int)(u64 & 0xFFFFU); /* lower 16 */ - uh16 = (unsigned int)((u64 >> 16) & 0xFFFFU); /* upper 16 */ - - /* we see if even possible (u large enough relative to v) */ - if ((u32 - v_Nm1) <= u32) - { - u32 -= v_Nm1; - q_over = 1; /* overflow from the sub */ - } - else - { - q_over = 0; - } - /* q_hat = u32 / vh16 -- is the upper partial value */ - /* estimate; if too much, then back down by 1 or 2 */ - q_hat = u32 / vh16; - r_hat = u32 - (q_hat * vh16); - /* see if Q is more than 16 bits or remainder is too large (over div) */ - if ((q_hat == 0x10000U) || ((q_hat * vl16) > ((r_hat << 16) | uh16))) - { - /* too much - undo a division */ - q_hat--; - r_hat += vh16; - /* check if still too much */ - if ((r_hat < 0x10000U) && ((q_hat * vl16) > ((r_hat << 16) | uh16))) - { - q_hat--; /* yes, so undo a 2nd */ - } - } - - /* compose u3u2uh16, then sub q_hat*v if OK */ - u64 = (((uint64_t)u32 << 16) | uh16) - ((uint64_t)q_hat * v_Nm1); - if (0U != (u64 >> 48)) - { - /* no, so add v back */ - u32 = (unsigned)(u64 + v_Nm1); - q_hat--; - } - else - { - u32 = (unsigned)u64; - } - tmp = (int32_t)(uint32_t)(q_hat << 16); /* quotient upper part */ - - /* divide lower part: q = u2uh16ul16 / v. */ - /* estimate and add back if over divdied */ - q_hat = u32 / vh16; - r_hat = u32 - (q_hat * vh16); - if ((q_hat == 0x10000U) || ((q_hat * vl16) > ((r_hat << 16) | ul16))) - { - /* too much - undo a division */ - q_hat--; - r_hat += vh16; - /* check if still too much */ - if ((r_hat < 0x10000U) && ((q_hat * vl16) > ((r_hat << 16) | ul16))) - { - q_hat--; /* yes, so undo a 2nd */ - } - } - - /* compose u2uh16ul16, then sub q_hat*v if OK */ - u64 = (((uint64_t)u32 << 16) | ul16) - ((uint64_t)q_hat * v_Nm1); - if (0U != (u64 >> 48)) - { - /* no, so add v back */ - r_hat = (unsigned)(u64 + v_Nm1); - q_hat--; - } - else - { - r_hat = (unsigned)u64; - } - q_hat |= (unsigned)tmp; /* other half of the quotient */ - while ((q_over != 0U) || ((uint64_t)q_hat * GET_WORD(&v[N_wordlen - 2U])) > - ((1ULL << 32) * r_hat) + (uint64_t)GET_WORD(&u_shft[(uint32_t)j + N_wordlen - 2U])) - { /* if Qhat>b, then reduce to b-1, then adjust up Rhat */ - q_hat--; - r_hat += v_Nm1; - if (r_hat < v_Nm1) - { - break; /* no overflow */ - /* else repeat since Rhat >= b */ - } - } - - /* Step 4. Multiply and subtract. We know the amount, */ - /* so we do the schoolboy math. Have to do on */ - /* the large value. */ - if (q_hat != 0U) - { - borrow = 0; - for (i = 0; i < N_wordlen; i++) - { - u64 = (uint64_t)q_hat * GET_WORD(&v[i]) + borrow; - borrow = (unsigned)(u64 >> 32); - if (GET_WORD(&u_shft[i + (unsigned)j]) < (unsigned)u64) - { - borrow++; /* carry the overflow */ - } - SET_WORD(&u_shft[i + (unsigned)j], GET_WORD(&u_shft[i + (unsigned)j]) - (unsigned)u64); - } - u_n -= borrow; /* overflow from shift left does not fit otherwise */ - } - - /* Store 5. (update Q - we don't), and add back V to remainder if we over-subtracted */ - /* That restores remainder to correct (we could only be off by 1) */ - /* This should happen very rarely. */ - if (u_n != 0U) - { - carry = 0; - for (i = 0; i < N_wordlen; i++) - { - SET_WORD(&u_shft[i + (unsigned)j], GET_WORD(&u_shft[i + (unsigned)j]) + carry); - carry = (GET_WORD(&u_shft[i + (unsigned)j]) < carry) ? 1U : 0U; - SET_WORD(&u_shft[i + (unsigned)j], GET_WORD(&u_shft[i + (unsigned)j]) + GET_WORD(&v[i])); - if (GET_WORD(&u_shft[i + (unsigned)j]) < GET_WORD(&v[i])) - { - carry++; - } - } - } - u_n = GET_WORD( - &u_shft[(uint32_t)j + N_wordlen - 1U]); /* hold upper part of u to catch overflow (to borrow from) */ - } - /* low N bits of r are valid as remainder */ -} - -/* We convert X into a Mont form number. Note length of arrays: */ -/* x is N_wordlen, Nmod is N_wordlen */ -/* Rp is N_wordlen (it is R` which is R mod N) */ -/* Xmont_out is N_wordlen*2+1 */ -void MultprecMontPrepareX(unsigned Xmont_out[], const unsigned x[], const unsigned Rp[], const unsigned Nmod[]) -{ - MultprecMultiply(Xmont_out, x, Rp); - MultprecModulo(Xmont_out, Nmod, (int32_t)N_wordlen); -} - -void MultprecGenNp64(const unsigned *Nmod, unsigned *np64_ret) /* only pass the low order double word */ -{ - uint64_t nprime, Nmod_0; - Nmod_0 = GET_WORD(&Nmod[0]) | ((uint64_t)GET_WORD(&Nmod[1]) << 32); - -#define COMP_NPN_1 ((2U - Nmod_0 * nprime) * nprime) /* computes N`*N0=1 mod 2^P where P is the partial built up */ - nprime = (((2U + Nmod_0) & 4U) << 1) + Nmod_0; /* mod 2^4 */ - nprime = COMP_NPN_1; - nprime = COMP_NPN_1; - nprime = COMP_NPN_1; - nprime = COMP_NPN_1; - /* 8 multiplies of uint64_t */ - *((uint64_t *)(uintptr_t)np64_ret) = (~0ULL - nprime) + 1ULL; -} - -/* CIOS Multiply. This is the Coarse Integrated form where the values are */ -/* multiplied and reduced for each step of "i". This uses less memory and */ -/* is faster as a result. Note that this is used to square as well as mul, */ -/* so not as fast as pure squaring could be. */ -void MultprecCiosMul( - unsigned w_out[], const unsigned a[], const unsigned b[], const unsigned Nmod[], const unsigned *Np) -{ - int j; - uint32_t i; - uint64_t *m64 = (uint64_t *)(uintptr_t)&msg_ret[kCASPER_RamOffset_M64]; - uint64_t Np64; - uint64_t carry; - uint64_t *a64, *b64, *w64, *N64; - - Np64 = *(uint64_t *)(uintptr_t)Np; - - a64 = (uint64_t *)(uintptr_t)a; - b64 = (uint64_t *)(uintptr_t)b; - w64 = (uint64_t *)(uintptr_t)w_out; - N64 = (uint64_t *)(uintptr_t)Nmod; - - if (a != NULL) - { /* if !a, we are reducing only */ - PreZeroW(i, w_out); - } - SET_DWORD(&w64[N_dwordlen], 0ULL); - SET_DWORD(&w64[N_dwordlen + 1U], 0ULL); - /* with accelerator */ - - /* loop i and then reduce after each j round */ - for (i = 0; i < N_dwordlen; i++) - { - /* Step 3. Iterate over N words of u using i - perform Multiply-accumulate */ - /* push-pull: we do a*b and then separately m*n (reduce) */ - if (a != NULL) - { /* if mul&reduce vs. reduce only */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(&b64[i]), CA_MK_OFF(a64)); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); - Accel_done(); - /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ - /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ - /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ - /* w64[N_dwordlen+1] = g_carry; */ - carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); - SET_DWORD(&w64[N_dwordlen + 1U], carry); - } - SET_DWORD(&m64[0], GET_DWORD(&w64[0]) * Np64); /* prime for 1st; modulo a double-word */ - - /* we are reducing, so the 1st [0th] 64 bit value product is tossed, but we */ - /* need its carry. We let the accel do this separately - really need a mode to */ - /* do this "reduce" since it is natural */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(m64), CA_MK_OFF(&N64[0])); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(&w64[0]))); - Accel_done(); - carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); - - Accel_SetABCD_Addr(CA_MK_OFF(&w64[1]), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpCopy, CA_MK_OFF(&w64[0]))); - - Accel_done(); - SET_DWORD(&w64[N_dwordlen], (GET_DWORD(&w64[N_dwordlen + 1U]) + carry)); - } - - /* now check if need to subtract Nmod */ - if (0U != (GET_WORD(&w_out[N_wordlen]))) - { - j = 1; /* we have to subtract for sure if carry up */ - } - else - { - j = 0; - for (i = N_wordlen - 1U; i > 0U; i--) - { - if (GET_WORD(&w_out[i]) != GET_WORD(&Nmod[i])) - { - j = (int32_t)(GET_WORD(&w_out[i]) > GET_WORD(&Nmod[i])); /* if larger sub */ - break; /* we would remove the break if worrying about side channel */ - } - } - } - if (0 == j) - { - return; /* Is smaller than Nmod, so done. */ - } - Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(w_out))); - Accel_done(); - /* last borrow is OK since we know it could only be <2N and */ -} - -/* RSA_MontSignatureToPlaintextFast: */ -/* MsgRet[] = Message return buffer - must be large enough to hold input and output (4*N+2) */ -/* exp_pubkey = the "e" that the value is raised to. Usually 3 or 0x10001. */ -/* signature = N bitpos len long "message" to process in Montgomery form - so saving conversion (divide) */ -/* pubkey = N bitpos len long public key to process signature with */ -/* returns: 0 */ -/* */ -/* Algo: compute M = signaturen^e mod public_key */ -/* where M is original plaintext, signature is signed value */ -/* note: e is usually either 0x3 or 0x10001 */ -int RSA_MontSignatureToPlaintextFast(const unsigned mont_signature[N_wordlen_max], - const unsigned exp_pubkey, - const unsigned pubkey[N_wordlen_max], - unsigned MsgRet[WORK_BUFF_MUL4]) -{ - int bidx = 0; - int bitpos; - unsigned np64[2]; - - /* MsgRet working area: */ - /* 0..N = RESULT, starting with S` */ - /* N..N*2 = S` and then working BASE during math. */ - /* N*2..N*4+2 = temp working area for Mont mul */ - - /* 1. Copy sig into MsgRet so we have one working result buffer */ - CASPER_MEMCPY_I2I((uint32_t *)(uintptr_t)&MsgRet[kCASPER_RamOffset_Result], - (const uint32_t *)(uintptr_t)mont_signature, N_bytelen); - MultprecGenNp64(pubkey, np64); /* Generate N` from LSW of N (LSW being lowest 64b word) */ - bitpos = (int8_t)(uint8_t)(31U - __CLZ(exp_pubkey)); /* count of bits after the left most 1 */ - while (--bitpos >= 0) - { - /* This operates on: */ - /* result = 1; */ - /* base = signature */ - /* loop while exponent bits from MSb to LSb */ - /* if (exp bit is 1) */ - /* result = result * base */ - /* base = base^2 */ - /* Because the MSb of exp is always 1 by definition, we can invert this a bit: */ - /* base = signature` */ - /* result = base; equivalent to result = 1*base from 1st pass, but now square is needed 1st */ - /* loop while exponent bits from MSb-1 to LSb */ - /* base = base^2 */ - /* if (exp bit is 1) */ - /* result = result * base */ - /* This ends up doing the same thing but skips two wasteful steps of multiplying by 1 and */ - /* a final squaring never used. */ - /* */ - /* Next we have the problem that CIOS mul needs a separate dest buffer. So, we bounce */ - /* base between base and temp, and likewise for result. */ - MultprecCiosMul(&MsgRet[(bidx != 0) ? kCASPER_RamOffset_Base : kCASPER_RamOffset_TempBase], - &MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], - &MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], pubkey, np64); - if (0U != (exp_pubkey & (uint32_t)(uint8_t)(1U << (uint8_t)bitpos))) /* where e is 1 */ - { - /* result has result, so we need to work into other temp area */ - MultprecCiosMul(&MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], - &MsgRet[kCASPER_RamOffset_Result], - &MsgRet[(bidx != 0) ? kCASPER_RamOffset_Base : kCASPER_RamOffset_TempBase], pubkey, np64); - /* we have to copy back to result */ - - // CASPER_MEMCPY_I2I(&MsgRet[kCASPER_RamOffset_Result], - // &MsgRet[bidx ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], N_bytelen); - } - else - { - bidx = (int32_t)(uint32_t) ~(unsigned)bidx; - } - } - - CASPER_MEMCPY_I2I((uint32_t *)(uintptr_t)&MsgRet[kCASPER_RamOffset_Result], - (uint32_t *)(uintptr_t)&MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], - N_bytelen); - - /* final step is one more reduction to get back to normal form (ie. divide R out) */ - MultprecCiosMul(&MsgRet[kCASPER_RamOffset_Result], NULL, NULL, pubkey, np64); - return (0); /* always 0 */ -} - -/* RSA_SignatureToPlaintextFast: */ -/* MsgRet[] = Message return buffer - must be large enough to hold input and output (4*N+2) */ -/* exp_pubkey = the "e" that the value is raised to. Usually 3 or 0x10001. */ -/* signature = N bitpos len long "message" to process in normal form - so converted to Mont form */ -/* pubkey = N bitpos len long public key to process signature with */ -/* returns: 0 */ -/* */ -/* Algo: compute M = signaturen^e mod public_key */ -/* where M is original plaintext, signature is signed value */ -/* note: e is usually either 0x3 or 0x10001 */ -int RSA_SignatureToPlaintextFast(const unsigned signature[N_wordlen_max], - const unsigned exp_pubkey, - const unsigned pubkey[N_wordlen_max], - unsigned MsgRet[WORK_BUFF_MUL4]) -{ - /* MsgRet working area: */ - /* 0..N = RESULT, starting with S`; it is used for R` just during creation of S` */ - /* N..N*2 = S` and then working BASE during math. Note overflow beyond N*2 when making S` */ - /* N*2..N*4+2 = temp working area for Mont mul */ - - MultprecMontCalcRp(&MsgRet[kCASPER_RamOffset_Result], exp_pubkey, pubkey); /* calculate R` (=R mod N) */ - MultprecMontPrepareX(&MsgRet[kCASPER_RamOffset_Base], signature, &MsgRet[kCASPER_RamOffset_Result], - pubkey); /* X*R1` mod N */ - return (RSA_MontSignatureToPlaintextFast(&MsgRet[kCASPER_RamOffset_Base], exp_pubkey, pubkey, MsgRet)); -} - -/*! - * brief Performs modular exponentiation - (A^E) mod N. - * - * This function performs modular exponentiation. - * - * param base CASPER base address - * param signature first addend (in little endian format) - * param pubN modulus (in little endian format) - * param wordLen Size of pubN in bytes - * param pubE exponent - * param[out] plaintext Output array to store result of operation (in little endian format) - */ -void CASPER_ModExp( - CASPER_Type *base, const uint8_t *signature, const uint8_t *pubN, size_t wordLen, uint32_t pubE, uint8_t *plaintext) -{ -#define PK_LOC &msg_ret[kCASPER_RamOffset_Modulus] -#define SIG_LOC &msg_ret[(unsigned)kCASPER_RamOffset_Modulus + N_wordlen_max] - - N_wordlen = wordLen; /* set global variable for key length - used by RSA_SignatureToPlaintextFast() */ - CASPER_MEMCPY_N2I(PK_LOC, (const uint32_t *)(uintptr_t)pubN, N_bytelen); - CASPER_MEMCPY_N2I(SIG_LOC, (const uint32_t *)(uintptr_t)signature, N_bytelen); - (void)RSA_SignatureToPlaintextFast((const unsigned *)(uintptr_t)(SIG_LOC), pubE, - (const unsigned *)(uintptr_t)(PK_LOC), (unsigned int *)(uintptr_t)msg_ret); - - CASPER_MEMCPY_I2N((uint32_t *)(uintptr_t)plaintext, msg_ret, N_bytelen); -} - -/*! - * brief Enables clock and disables reset for CASPER peripheral. - * - * Enable clock and disable reset for CASPER. - * - * param base CASPER base address - */ -void CASPER_Init(CASPER_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(CASPER_CLOCKS) - CLOCK_EnableClock(kCLOCK_Casper); -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if defined(CASPER_RSTS) - RESET_PeripheralReset(kCASPER_RST_SHIFT_RSTn); -#endif -#if defined(FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE) && (FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE > 0) - /* Enable hardware interleaving to RAMX0 and RAMX1 for CASPER */ - SYSCON->CASPER_CTRL = SYSCON_CASPER_CTRL_INTERLEAVE(1); -#endif /* FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE */ - /* If Casper init is called with secure address, use secure addres also for accessing Casper RAM. */ - s_casperRamBase = (unsigned)CASPER_RAM_BASE_NS | ((uint32_t)base & 0x10000000u); - msg_ret = (uint32_t *)s_casperRamBase; -} - -/*! - * brief Disables clock for CASPER peripheral. - * - * Disable clock and enable reset. - * - * param base CASPER base address - */ -void CASPER_Deinit(CASPER_Type *base) -{ -#if defined(CASPER_RSTS) - RESET_SetPeripheralReset(kCASPER_RST_SHIFT_RSTn); -#endif -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(CASPER_CLOCKS) - CLOCK_DisableClock(kCLOCK_Casper); -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/* New ECC code which uses Casper. */ - -/* Set the prime modulus mod in Casper memory. - */ -void CASPER_ecc_init(casper_algo_t curve) -{ - uint32_t *mod; - - if (curve == kCASPER_ECC_P256) - { - N_wordlen = 256U / 32U; - mod = NISTp256; - } - - if (curve == kCASPER_ECC_P384) - { - N_wordlen = 384U / 32U; - mod = NISTp384; - } - - if (curve == kCASPER_ECC_P521) - { - N_wordlen = 576U / 32U; - mod = NISTp521; - } - - CASPER_MEMCPY(&CASPER_MEM[(N_wordlen + 4U)], mod, N_wordlen * sizeof(uint32_t)); - uint8_t a[((CASPER_MAX_ECC_SIZE_WORDLEN + 4U) - CASPER_MAX_ECC_SIZE_WORDLEN) * sizeof(uint32_t)] = {0}; - CASPER_MEMCPY(&CASPER_MEM[(N_wordlen + 4U) + N_wordlen], a, ((N_wordlen + 4U) - N_wordlen) * sizeof(uint32_t)); -} - -void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2) -{ - uint32_t a[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; - uint32_t b[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; - uint32_t c = 0; - CASPER_MEMCPY(a, op1, N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(b, op2, N_wordlen * sizeof(uint32_t)); - - do - { - uint32_t _i; - c = (a[0] ^ b[0]); - for (_i = 1; _i < N_wordlen; _i++) - { - c |= (a[_i] ^ b[_i]); - } - } while (false); - - *res = (int32_t)c; -} - -void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1) -{ - uint32_t a[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; - uint32_t c = 0; - CASPER_MEMCPY(a, op1, N_wordlen * sizeof(uint32_t)); - - do - { - uint32_t _i; - c = a[0]; - for (_i = 1; _i < N_wordlen; _i++) - { - c |= a[_i]; - } - } while (false); - - *res = (int32_t)c; -} - -void CASPER_ECC_SECP256R1_Mul( - CASPER_Type *base, uint32_t resX[8], uint32_t resY[8], uint32_t X[8], uint32_t Y[8], uint32_t scalar[8]) -{ - uint32_t X1[8] = {0}; - uint32_t Y1[8] = {0}; - toMontgomery_ECC_P256(X1, X); - toMontgomery_ECC_P256(Y1, Y); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - - Jac_scalar_multiplication( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - scalar, NISTp256, NISTp256_q); - - Jac_toAffine( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - - /* Montgomery to Normal */ - /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ - uint32_t one[(kCASPER_ECC_P256_wordlen + 4U)] = {0x0}; - one[0] = 0x1u; - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - one, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - - /* copy out to result */ - CASPER_MEMCPY( - resX, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - resY, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP256R1_MulAdd(CASPER_Type *base, - uint32_t resX[8], - uint32_t resY[8], - uint32_t X1[8], - uint32_t Y1[8], - uint32_t scalar1[8], - uint32_t X2[8], - uint32_t Y2[8], - uint32_t scalar2[8]) -{ - uint32_t zeroes[(kCASPER_ECC_P256_wordlen + 4U)] = {0}; - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - X2, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - Y2, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - - toMontgomery_ECC_P256( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - toMontgomery_ECC_P256( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - toMontgomery_ECC_P256( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - toMontgomery_ECC_P256( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); - double_scalar_multiplication( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - scalar1, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - scalar2); - - Jac_toAffine( - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - - uint32_t one[(kCASPER_ECC_P256_wordlen + 4U)] = {0x0}; - one[0] = 0x1u; - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - one, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - - CASPER_MEMCPY(resX, - (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(resY, - (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP384R1_Mul( - CASPER_Type *base, uint32_t resX[12], uint32_t resY[12], uint32_t X[12], uint32_t Y[12], uint32_t scalar[12]) -{ - uint32_t X1[12] = {0}; - uint32_t Y1[12] = {0}; - toMontgomery_ECC_P384(X1, X); - toMontgomery_ECC_P384(Y1, Y); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - - Jac_scalar_multiplication( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - scalar, NISTp384, NISTp384_q); - - Jac_toAffine( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - - /* Montgomery to Normal */ - /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ - uint32_t one[12] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - one, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - - /* copy out to result */ - CASPER_MEMCPY( - resX, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - resY, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base, - uint32_t resX[12], - uint32_t resY[12], - uint32_t X1[12], - uint32_t Y1[12], - uint32_t scalar1[12], - uint32_t X2[12], - uint32_t Y2[12], - uint32_t scalar2[12]) -{ - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - X2, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - Y2, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - - toMontgomery_ECC_P384( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - toMontgomery_ECC_P384( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - toMontgomery_ECC_P384( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - toMontgomery_ECC_P384( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - - double_scalar_multiplication( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - scalar1, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - scalar2); - - Jac_toAffine( - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - - uint32_t one[12] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - one, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - - CASPER_MEMCPY(resX, - (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + - 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(resY, - (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + - 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP521R1_Mul( - CASPER_Type *base, uint32_t resX[18], uint32_t resY[18], uint32_t X[18], uint32_t Y[18], uint32_t scalar[18]) -{ - uint32_t X1[18] = {0}; - uint32_t Y1[18] = {0}; - toMontgomery_ECC_P521(X1, X); - toMontgomery_ECC_P521(Y1, Y); - - CASPER_MEMCPY( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - - Jac_scalar_multiplication( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 7U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 8U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - scalar, NISTp521, NISTp521_q); - - Jac_toAffine( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 7U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 8U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - - /* Montgomery to Normal */ - /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ - uint32_t one[18] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; - CASPER_MEMCPY( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - one, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - - /* copy out to result */ - CASPER_MEMCPY( - resX, - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - resY, - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP521R1_MulAdd(CASPER_Type *base, - uint32_t resX[18], - uint32_t resY[18], - uint32_t X1[18], - uint32_t Y1[18], - uint32_t scalar1[18], - uint32_t X2[18], - uint32_t Y2[18], - uint32_t scalar2[18]) -{ - uint32_t zeroes[(kCASPER_ECC_P521_wordlen + 4U)] = {0}; - - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - X2, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - Y2, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - - toMontgomery_ECC_P521( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - toMontgomery_ECC_P521( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - toMontgomery_ECC_P521( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - toMontgomery_ECC_P521( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); - double_scalar_multiplication( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - scalar1, - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - scalar2); - - Jac_toAffine( - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - - uint32_t one[(kCASPER_ECC_P521_wordlen + 4U)] = {0x0}; - one[0] = 0x1u; - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - one, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + - 2U * ((uint32_t)(uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - - CASPER_MEMCPY( - resX, - (&CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - resY, - (&CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); -} - -// CIOS Multiply. This is the Coarse Integrated form where the values are -// multiplied and reduced for each step of "i". This uses less memory and -// is faster as a result. Note that this is used to square as well as mul, -// so not as fast as pure squaring could be. -static void MultprecCiosMul_ct( - uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np) -{ - uint32_t j; - uint64_t *m64 = (uint64_t *)(uintptr_t)&msg_ret[kCASPER_RamOffset_M64]; - uint64_t Np64; - uint64_t carry; - uint64_t *a64, *b64, *w64, *N64; - uint32_t *T1 = &CASPER_MEM[0], borrow; - - Np64 = *(uint64_t *)(uintptr_t)Np; - - a64 = (uint64_t *)(uintptr_t)a; - b64 = (uint64_t *)(uintptr_t)b; - w64 = (uint64_t *)(uintptr_t)w_out; - N64 = (uint64_t *)(uintptr_t)Nmod; - - if (a != NULL) - { /* if !a, we are reducing only */ - PreZeroW(j, w_out); - } - SET_DWORD(&w64[N_dwordlen], 0ULL); - SET_DWORD(&w64[N_dwordlen + 1U], 0ULL); - /* with accelerator */ - - /* loop j and then reduce after each j round */ - for (j = 0; j < N_dwordlen; j++) - { - /* Step 3. Iterate over N words of u using j - perform Multiply-accumulate */ - /* push-pull: we do a*b and then separately m*n (reduce) */ - if (a != NULL) - { /* if mul&reduce vs. reduce only */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(&b64[j]), CA_MK_OFF(a64)); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); - Accel_done(); - /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ - /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ - /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ - /* w64[N_dwordlen+1] = g_carry; */ - carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); - SET_DWORD(&w64[N_dwordlen + 1U], carry); - } - SET_DWORD(&m64[0], GET_DWORD(&w64[0]) * Np64); /* prime for 1st; modulo a double-word */ - - /* we are reducing, so the 1st [0th] 64 bit value product is tossed, but we */ - /* need its carry. We let the accel do this separately - really need a mode to */ - /* do this "reduce" since it is natural */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(m64), CA_MK_OFF(&N64[0])); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(&w64[0]))); - Accel_done(); - carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); - - Accel_SetABCD_Addr(CA_MK_OFF(&w64[1]), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpCopy, CA_MK_OFF(&w64[0]))); - - Accel_done(); - SET_DWORD(&w64[N_dwordlen], (GET_DWORD(&w64[N_dwordlen + 1U]) + carry)); - } - - /* now check if need to subtract Nmod */ - CASPER_MEMCPY_I2I(T1, w_out, (N_wordlen + 1U) * sizeof(uint32_t)); - - /* Compute w = w - N */ - Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(w_out))); - Accel_done(); - - // if w_out > T1 then there was a borrow - borrow = (uint32_t)(GET_WORD(&((uint32_t *)w_out)[N_wordlen]) > GET_WORD(&T1[N_wordlen])); - - SET_WORD(&w_out[N_wordlen + 1U], 0); - SET_WORD(&w_out[N_wordlen], 0); - casper_select(w_out, w_out, T1, (int32_t)borrow, (int16_t)(uint16_t)N_wordlen); -} - -/* Compute C = A - B % mod - * Assumes all operand have two extra limbs to store carry. - */ -static void CASPER_montsub(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod) -{ - uint64_t *b64, *c64, *m64, *tmp; - int borrow; - - b64 = (uint64_t *)(uintptr_t)B; - c64 = (uint64_t *)(uintptr_t)C; - m64 = (uint64_t *)(uintptr_t)mod; - - tmp = (uint64_t *)(uintptr_t)&CASPER_MEM[0]; - - CASPER_MEMCPY(tmp, A, N_wordlen * sizeof(uint32_t)); - - /* Compute tmp = A - B. */ - Accel_SetABCD_Addr(CA_MK_OFF(b64), 0); - - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(tmp))); - Accel_done(); - - borrow = (int32_t)((GET_WORD(&((uint32_t *)(uintptr_t)tmp)[N_wordlen - 1U])) > GET_WORD(&A[N_wordlen - 1U])); - CASPER_MEMCPY(c64, tmp, N_wordlen * sizeof(uint32_t)); - - /* Compute C = Mod + tmp */ - Accel_SetABCD_Addr(CA_MK_OFF(m64), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpAdd64, CA_MK_OFF(c64))); - Accel_done(); - - casper_select(C, (uint32_t *)(uintptr_t)tmp, C, borrow, (int16_t)(uint16_t)N_wordlen); -} - -/* Compute C = A + B % mod - * Assumes all operand have two extra limbs to store carry. - */ -static void CASPER_montadd(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod) -{ - uint64_t *b64, *c64, *m64, *tmp; - int borrow; - - b64 = (uint64_t *)(uintptr_t)B; - c64 = (uint64_t *)(uintptr_t)C; - m64 = (uint64_t *)(uintptr_t)mod; - - tmp = (uint64_t *)(uintptr_t)&CASPER_MEM[0]; - - CASPER_MEMCPY(tmp, A, N_wordlen * sizeof(uint32_t)); - SET_DWORD(&tmp[N_wordlen / 2U], 0ULL); - SET_DWORD(&b64[N_wordlen / 2U], 0ULL); - SET_DWORD(&m64[N_wordlen / 2U], 0ULL); - - /* Compute tmp = A + B using one additonal double-length limb. */ - Accel_SetABCD_Addr(CA_MK_OFF(b64), 0); - - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U, (uint32_t)kCASPER_OpAdd64, CA_MK_OFF(tmp))); - Accel_done(); - - CASPER_MEMCPY(c64, tmp, (N_wordlen + 2U) * sizeof(uint32_t)); - - /* Compute C = Mod - tmp */ - Accel_SetABCD_Addr(CA_MK_OFF(m64), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(c64))); - Accel_done(); - - // borrow = g_carry; - borrow = (int32_t)(GET_WORD(&C[N_wordlen]) > GET_WORD(&(((uint32_t *)(uintptr_t)tmp)[N_wordlen]))); - casper_select(C, C, (uint32_t *)(uintptr_t)tmp, borrow, (int16_t)(uint16_t)N_wordlen); -} - -/* Compute c = a/2 mod p where b is scratch space. */ -static void CASPER_half(uint32_t *c, uint32_t *a, uint32_t *b) -{ - shiftright(b, a, 1U); /* Compute a/2 and (a+p)/2 */ - - /* Compute tmp = a + p using one additonal double-length limb. */ - CASPER_MEMCPY(c, a, N_wordlen * sizeof(uint32_t)); - SET_WORD(&c[N_wordlen], 0); - SET_WORD(&c[N_wordlen + 1U], 0U); - - Accel_SetABCD_Addr(CA_MK_OFF(((uint64_t *)(uintptr_t)&CASPER_MEM[(N_wordlen + 4U)])), 0); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_wordlen / 2U, (uint32_t)kCASPER_OpAdd64, CA_MK_OFF(((uint64_t *)(uintptr_t)c)))); - Accel_done(); - - shiftright(c, c, 1U); - SET_WORD(&c[N_wordlen - 1U], GET_WORD(&c[N_wordlen - 1U]) | (GET_WORD(&c[N_wordlen]) << 31)); - SET_WORD(&c[N_wordlen], 0U); - casper_select(c, b, c, (int32_t)(uint32_t)(GET_WORD(&a[0]) & 1U), (int16_t)(uint16_t)(N_wordlen)); -} - -static uint32_t casper_get_word(uint32_t *addr) -{ - return GET_WORD(addr); -} - -/* Shift right by 1 <= c <= 31. z[] and x[] in system RAM, no interleaving macros used. */ -static void shiftrightSysram(uint32_t *z, uint32_t *x, uint32_t c) -{ - z[0] = (x[1] << (32U - (c))) | (x[0] >> (c)); - z[1] = (x[2] << (32U - (c))) | (x[1] >> (c)); - z[2] = (x[3] << (32U - (c))) | (x[2] >> (c)); - z[3] = (x[4] << (32U - (c))) | (x[3] >> (c)); - z[4] = (x[5] << (32U - (c))) | (x[4] >> (c)); - z[5] = (x[6] << (32U - (c))) | (x[5] >> (c)); - z[6] = (x[7] << (32U - (c))) | (x[6] >> (c)); - - if (N_wordlen == 18U) - { - z[7] = (x[8] << (32U - (c))) | (x[7] >> (c)); - z[8] = (x[9] << (32U - (c))) | (x[8] >> (c)); - z[9] = (x[10] << (32U - (c))) | (x[9] >> (c)); - z[10] = (x[11] << (32U - (c))) | (x[10] >> (c)); - z[11] = (x[12] << (32U - (c))) | (x[11] >> (c)); - z[12] = (x[13] << (32U - (c))) | (x[12] >> (c)); - z[13] = (x[14] << (32U - (c))) | (x[13] >> (c)); - z[14] = (x[15] << (32U - (c))) | (x[14] >> (c)); - z[15] = (x[16] << (32U - (c))) | (x[15] >> (c)); - z[16] = (x[17] << (32U - (c))) | (x[16] >> (c)); - z[17] = (x[17] >> (c)); - } - - if (N_wordlen == 12U) - { - z[7] = (x[8] << (32U - (c))) | (x[7] >> (c)); - z[8] = (x[9] << (32U - (c))) | (x[8] >> (c)); - z[9] = (x[10] << (32U - (c))) | (x[9] >> (c)); - z[10] = (x[11] << (32U - (c))) | (x[10] >> (c)); - z[11] = (x[11] >> (c)); - } - if (N_wordlen == 8U) - { - z[7] = (x[7] >> (c)); - } -} -/* Shift right by 1 <= c <= 31. */ -static void shiftright(uint32_t *z, uint32_t *x, uint32_t c) -{ - SET_WORD(&z[0], (GET_WORD(&x[1]) << (32U - (c))) | (GET_WORD(&x[0]) >> (c))); - SET_WORD(&z[1], (GET_WORD(&x[2]) << (32U - (c))) | (GET_WORD(&x[1]) >> (c))); - SET_WORD(&z[2], (GET_WORD(&x[3]) << (32U - (c))) | (GET_WORD(&x[2]) >> (c))); - SET_WORD(&z[3], (GET_WORD(&x[4]) << (32U - (c))) | (GET_WORD(&x[3]) >> (c))); - SET_WORD(&z[4], (GET_WORD(&x[5]) << (32U - (c))) | (GET_WORD(&x[4]) >> (c))); - SET_WORD(&z[5], (GET_WORD(&x[6]) << (32U - (c))) | (GET_WORD(&x[5]) >> (c))); - SET_WORD(&z[6], (GET_WORD(&x[7]) << (32U - (c))) | (GET_WORD(&x[6]) >> (c))); - - if (N_wordlen == 18U) - { - SET_WORD(&z[7], (GET_WORD(&x[8]) << (32U - (c))) | (GET_WORD(&x[7]) >> (c))); - SET_WORD(&z[8], (GET_WORD(&x[9]) << (32U - (c))) | (GET_WORD(&x[8]) >> (c))); - SET_WORD(&z[9], (GET_WORD(&x[10]) << (32U - (c))) | (GET_WORD(&x[9]) >> (c))); - SET_WORD(&z[10], (GET_WORD(&x[11]) << (32U - (c))) | (GET_WORD(&x[10]) >> (c))); - SET_WORD(&z[11], (GET_WORD(&x[12]) << (32U - (c))) | (GET_WORD(&x[11]) >> (c))); - SET_WORD(&z[12], (GET_WORD(&x[13]) << (32U - (c))) | (GET_WORD(&x[12]) >> (c))); - SET_WORD(&z[13], (GET_WORD(&x[14]) << (32U - (c))) | (GET_WORD(&x[13]) >> (c))); - SET_WORD(&z[14], (GET_WORD(&x[15]) << (32U - (c))) | (GET_WORD(&x[14]) >> (c))); - SET_WORD(&z[15], (GET_WORD(&x[16]) << (32U - (c))) | (GET_WORD(&x[15]) >> (c))); - SET_WORD(&z[16], (GET_WORD(&x[17]) << (32U - (c))) | (GET_WORD(&x[16]) >> (c))); - SET_WORD(&z[17], (GET_WORD(&x[17]) >> (c))); - } - if (N_wordlen == 12U) - { - SET_WORD(&z[7], (GET_WORD(&x[8]) << (32U - (c))) | (GET_WORD(&x[7]) >> (c))); - SET_WORD(&z[8], (GET_WORD(&x[9]) << (32U - (c))) | (GET_WORD(&x[8]) >> (c))); - SET_WORD(&z[9], (GET_WORD(&x[10]) << (32U - (c))) | (GET_WORD(&x[9]) >> (c))); - SET_WORD(&z[10], (GET_WORD(&x[11]) << (32U - (c))) | (GET_WORD(&x[10]) >> (c))); - SET_WORD(&z[11], (GET_WORD(&x[11]) >> (c))); - } - if (N_wordlen == 8U) - { - SET_WORD((&z[7]), (GET_WORD(&x[7]) >> (c))); - } -} -/* Shift left by 1 <= c <= 31. */ -static void shiftleft(uint32_t *z, uint32_t *x, uint32_t c) -{ - if (N_wordlen == 18U) - { - SET_WORD(&z[17], (GET_WORD(&x[17]) << (c)) | GET_WORD(&z[16]) >> (32U - (c))); - SET_WORD(&z[16], (GET_WORD(&x[16]) << (c)) | GET_WORD(&z[15]) >> (32U - (c))); - SET_WORD(&z[15], (GET_WORD(&x[15]) << (c)) | GET_WORD(&z[14]) >> (32U - (c))); - SET_WORD(&z[14], (GET_WORD(&x[14]) << (c)) | GET_WORD(&z[13]) >> (32U - (c))); - SET_WORD(&z[13], (GET_WORD(&x[13]) << (c)) | GET_WORD(&z[12]) >> (32U - (c))); - SET_WORD(&z[12], (GET_WORD(&x[12]) << (c)) | GET_WORD(&z[11]) >> (32U - (c))); - SET_WORD(&z[11], (GET_WORD(&x[11]) << (c)) | GET_WORD(&z[10]) >> (32U - (c))); - SET_WORD(&z[10], (GET_WORD(&x[10]) << (c)) | GET_WORD(&z[9]) >> (32U - (c))); - SET_WORD(&z[9], (GET_WORD(&x[9]) << (c)) | GET_WORD(&z[8]) >> (32U - (c))); - SET_WORD(&z[8], (GET_WORD(&x[8]) << (c)) | GET_WORD(&z[7]) >> (32U - (c))); - } - if (N_wordlen == 12U) - { - SET_WORD(&z[11], (GET_WORD(&x[11]) << (c)) | GET_WORD(&z[10]) >> (32U - (c))); - SET_WORD(&z[10], (GET_WORD(&x[10]) << (c)) | GET_WORD(&z[9]) >> (32U - (c))); - SET_WORD(&z[9], (GET_WORD(&x[9]) << (c)) | GET_WORD(&z[8]) >> (32U - (c))); - SET_WORD(&z[8], (GET_WORD(&x[8]) << (c)) | GET_WORD(&z[7]) >> (32U - (c))); - } - SET_WORD(&z[7], (GET_WORD(&x[7]) << (c)) | GET_WORD(&z[6]) >> (32U - (c))); - SET_WORD(&z[6], (GET_WORD(&x[6]) << (c)) | GET_WORD(&z[5]) >> (32U - (c))); - SET_WORD(&z[5], (GET_WORD(&x[5]) << (c)) | GET_WORD(&z[4]) >> (32U - (c))); - SET_WORD(&z[4], (GET_WORD(&x[4]) << (c)) | GET_WORD(&z[3]) >> (32U - (c))); - SET_WORD(&z[3], (GET_WORD(&x[3]) << (c)) | GET_WORD(&z[2]) >> (32U - (c))); - SET_WORD(&z[2], (GET_WORD(&x[2]) << (c)) | GET_WORD(&z[1]) >> (32U - (c))); - SET_WORD(&z[1], (GET_WORD(&x[1]) << (c)) | GET_WORD(&z[0]) >> (32U - (c))); - SET_WORD(&z[0], (GET_WORD(&x[0]) << (c))); -} - -static void multiply_casper(uint32_t w_out[], const uint32_t a[], const uint32_t b[]) -{ - uint32_t *Np; - - if (N_wordlen == 8U) - { - Np = Np256; - MultprecCiosMul_ct(w_out, a, b, &CASPER_MEM[(N_wordlen + 4U)], Np); - } - if (N_wordlen == 12U) - { - Np = Np384; - MultprecCiosMul_ct(w_out, a, b, &CASPER_MEM[(N_wordlen + 4U)], Np); - } - - if (N_wordlen == 18U) - { - Np = Np521; - MultprecCiosMul521_ct(w_out, a, b, &CASPER_MEM[(N_wordlen + 4U)], Np); - } -} -/* Convert a projective point (X1 : Y1 : Z1) - * to the affine point (X3, Y3) = (X1/Z1^2,Y1/Z1^3) - * The memory of (X3, Y3) and (X1 : Y1 : Z1) should not overlap - */ -void Jac_toAffine(uint32_t *X3, uint32_t *Y3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1) -{ - uint32_t *T1, *T2; - - T1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; - T2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; - - square_casper(T1, Z1); // Z^2 - multiply_casper(T2, T1, Z1); // Z^3 - - // Montgomery inverse - if (N_wordlen == 8U) - { - invert_mod_p256(T1, T2); - } - - if (N_wordlen == 12U) - { - invert_mod_p384(T1, T2); - } - - if (N_wordlen == 18U) - { - invert_mod_p521(T1, T2); - } - - multiply_casper(Y3, Y1, T1); // Y3 = Y/Z^3 - multiply_casper(T2, T1, Z1); // Z^-2 - multiply_casper(X3, X1, T2); // X3 = X/Z^2 -} - -/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2 : Y2 : Z2) - * where (X1: Y1: Z1) != (X2 : Y2 : Z2) - * (X3 : Y3: Z3) may be the same as one of the inputs. - */ -void Jac_addition(uint32_t *X3, - uint32_t *Y3, - uint32_t *Z3, - uint32_t *X1, - uint32_t *Y1, - uint32_t *Z1, - uint32_t *X2, - uint32_t *Y2, - uint32_t *Z2) -{ - uint32_t *Z1Z1, *Z2Z2, *U1, *S1, *J, *H, *V, *t0, *t1; - int m1, m2; - - Z1Z1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; - Z2Z2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; - U1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 2U * (N_wordlen + 4U)]; - S1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 3U * (N_wordlen + 4U)]; - J = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 4U * (N_wordlen + 4U)]; - H = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 5U * (N_wordlen + 4U)]; - V = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 6U * (N_wordlen + 4U)]; - t0 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 7U * (N_wordlen + 4U)]; - t1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 8U * (N_wordlen + 4U)]; - - CASPER_ECC_equal_to_zero(&m1, Z1); - CASPER_ECC_equal_to_zero(&m2, Z2); - if (m1 == 0) - { - CASPER_MEMCPY(X3, X2, N_wordlen * 4U); - CASPER_MEMCPY(Y3, Y2, N_wordlen * 4U); - CASPER_MEMCPY(Z3, Z2, N_wordlen * 4U); - return; - } - if (m2 == 0) - { - CASPER_MEMCPY(X3, X1, N_wordlen * 4U); - CASPER_MEMCPY(Y3, Y1, N_wordlen * 4U); - CASPER_MEMCPY(Z3, Z1, N_wordlen * 4U); - return; - } - - square_casper(Z1Z1, Z1); - square_casper(Z2Z2, Z2); - multiply_casper(U1, X1, Z2Z2); - multiply_casper(H, X2, Z1Z1); /* if H equals U1 then X's are the same */ - multiply_casper(t0, Z2, Z2Z2); - multiply_casper(S1, Y1, t0); - multiply_casper(t0, Z1, Z1Z1); - multiply_casper(J, Y2, t0); /* if (S1 == J) then Y's are the same */ - - CASPER_ECC_equal(&m1, H, U1); /* If H and U1 match then the X-coordinates are the same. */ - CASPER_ECC_equal(&m2, S1, J); /* If S1 and J match then the Y-coordinates are the same. */ - if (m1 == 0) - { - if (m2 == 0) - { - Jac_double(X3, Y3, Z3, X1, Y1, Z1); - return; - } - /* else { - We work with the point at infinity. - The Z-coordinate will be set to zero in this function. - } */ - } - - sub_casper(H, H, U1); - mul2_casper(t0, H); - square_casper(t1, t0); - sub_casper(t0, J, S1); - multiply_casper(J, H, t1); - multiply_casper(V, U1, t1); - mul2_casper(U1, t0); - square_casper(t0, U1); - mul2_casper(t1, V); - sub_casper(t0, t0, J); - sub_casper(X3, t0, t1); - sub_casper(t0, V, X3); - multiply_casper(t1, S1, J); - mul2_casper(t1, t1); - multiply_casper(V, U1, t0); - sub_casper(Y3, V, t1); - add_casper(V, Z1, Z2); - square_casper(t1, V); - sub_casper(t1, t1, Z1Z1); - sub_casper(t1, t1, Z2Z2); - multiply_casper(Z3, t1, H); -} - -/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2, Y2) - * where (X1: Y1: Z1) != (X2, Y2) - * (X3 : Y3: Z3) may not overlap with (X1: Y1: Z1). - * Source: 2004 Hankerson?Menezes?Vanstone, page 91. - */ -void Jac_add_affine( - uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *X2, uint32_t *Y2) -{ - uint32_t *T1, *T2, *T3, *T4, *T5; - uint32_t *ONE = NULL; - int m1, m2; - - if (N_wordlen == 8U) - { - ONE = NISTr256; - } - if (N_wordlen == 12U) - { - ONE = NISTr384; - } - if (N_wordlen == 18U) - { - ONE = NISTr521; - } - - T1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; - T2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; - T3 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 2U * (N_wordlen + 4U)]; - T4 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 3U * (N_wordlen + 4U)]; - T5 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 4U * (N_wordlen + 4U)]; - - CASPER_ECC_equal_to_zero(&m1, Z1); - if (m1 == 0) - { - CASPER_MEMCPY(X3, X2, N_wordlen * 4U); - CASPER_MEMCPY(Y3, Y2, N_wordlen * 4U); - CASPER_MEMCPY(Z3, ONE, N_wordlen * 4U); - return; - } - - CASPER_MEMCPY(T5, Z1, N_wordlen * sizeof(uint32_t)); - square_casper(T3, Z1); - multiply_casper(T2, T3, Z1); - multiply_casper(T4, T3, X2); - multiply_casper(T3, T2, Y2); - - CASPER_ECC_equal(&m1, T4, X1); - CASPER_ECC_equal(&m2, T3, Y1); - if (m1 == 0) - { - if (m2 == 0) - { - Jac_double(X3, Y3, Z3, X1, Y1, Z1); - return; - } - /* else { - We work with the point at infinity. - The Z-coordinate will be set to zero in this function. - } */ - } - - sub_casper(T1, T4, X1); - sub_casper(T2, T3, Y1); - multiply_casper(Z3, T5, T1); - square_casper(T3, T1); - multiply_casper(T4, T3, T1); - multiply_casper(T5, T3, X1); - mul2_casper(T1, T5); - square_casper(X3, T2); - sub_casper(X3, X3, T1); - sub_casper(X3, X3, T4); - sub_casper(T3, T5, X3); - multiply_casper(T1, T3, T2); - multiply_casper(T2, T4, Y1); - sub_casper(Y3, T1, T2); -} - -static uint32_t casper_get_word(uint32_t *addr); - -/* Point doubling from: 2004 Hankerson?Menezes?Vanstone, page 91. - * Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X1 : Y1 : Z1) - * (X3 : Y3: Z3) may be the same as the input. - */ -void Jac_double(uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1) -{ - uint32_t *T1, *T2, *T3, *T4, *T5; - - T1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; - T2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; - T3 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 2U * (N_wordlen + 4U)]; - T4 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 3U * (N_wordlen + 4U)]; - T5 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 4U * (N_wordlen + 4U)]; - - square_casper(T1, Z1); - sub_casper(T3, X1, T1); - add_casper(T1, X1, T1); - multiply_casper(T4, T3, T1); - - mul2_casper(T3, T4); - - add_casper(T2, T3, T4); - - mul2_casper(Y3, Y1); - - CASPER_MEMCPY(T5, Z1, N_wordlen * sizeof(uint32_t)); - multiply_casper(Z3, Y3, T5); - - square_casper(T5, Y3); - - multiply_casper(T3, T5, X1); - - square_casper(Y3, T5); - - half(T5, Y3, T4); - - square_casper(X3, T2); - - mul2_casper(T1, T3); - - sub_casper(X3, X3, T1); - - sub_casper(T1, T3, X3); - - multiply_casper(T3, T1, T2); - - sub_casper(Y3, T3, T5); -} - -/* Recoding for a signed fixed window. - * Source: https://eprint.iacr.org/2014/130.pdf, Algorithm 6 - * Recode the n-bit integer k into ciel(log2(n)/(w-1)) digits - * where each digit is in - * { +/- 1, +/- 3, ..., +/- 2^(w-1)-1 } - * and put the result in c. - */ -static void recode(int8_t *c, uint32_t *k, int n, int w) -{ - int i, t; - uint32_t K[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; - (void)memcpy(K, k, (size_t)ceil(((double)n / 8.))); - t = (n + (w - 2)) / (w - 1); - for (i = 0; i < t; i++) - { - c[i] = (int8_t)(uint8_t)((K[0] & ((uint32_t)(uint32_t)(1UL << (uint32_t)w) - 1UL)) - - (uint32_t)(uint32_t)(1UL << ((uint32_t)w - 1UL))); - shiftrightSysram(K, K, (unsigned)w - 1U); - (void)add_n_1(K, K, (uint32_t)c[i] >> 31, (int16_t)(uint16_t)N_wordlen); - } - c[t] = (int8_t)K[0]; -} - -static uint32_t sub_n(uint32_t *c, uint32_t *a, uint32_t *b, int n) -{ - int i; - uint32_t borrow; - sub_borrowout(borrow, GET_WORD(&c[0]), a[0], GET_WORD(&b[0])); - for (i = 1; i < n; i++) - { - sub_borrowin_borrowout(borrow, GET_WORD(&c[i]), a[i], GET_WORD(&b[i]), borrow); - } - return borrow; -} - -#if 0 -/* Dumb n-limb subtraction of c=a-b, return borrow. */ -static uint32_t sub_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n) { - int i; - uint32_t borrow; - sub_borrowout(borrow, c[0], a[0], b); - for (i = 1; i < n; i++) { - sub_borrowin_borrowout_1(borrow, c[i], a[i], borrow); - } - return borrow; -} - -/* Dumb n-limb addition of c=a+b, return carry. */ -static uint32_t add_n(uint32_t *c, uint32_t *a, uint32_t *b, int n) { - int i; - uint32_t carry; - add_cout(carry, c[0], a[0], b[0]); - for (i = 1; i < n; i++) { - add_cout_cin(carry, c[i], a[i], b[i], carry); - } - return carry; -} -#endif - -/* Dumb n-limb addition of c=a+b, return carry. */ -static uint32_t add_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n) -{ - int i; - uint32_t carry; - add_cout(carry, c[0], a[0], b); - for (i = 1; i < n; i++) - { - add_cout_cin(carry, c[i], a[i], 0U, carry); - } - return carry; -} - -static uint8_t int8abs(int8_t v) -{ - return ((v < 0) ? ((uint8_t)-v) : ((uint8_t)v)); -} - -/* Constant time elliptic curve scalar multiplication. - * Source: https://eprint.iacr.org/2014/130.pdf - * when using w = 4. - * Computes (X3 : Y3 : Z3) = k * (X1, Y1) \in E(F_p) - * p is the prime used to define the finite field F_p - * q is the (prime) order of the curve - */ -void Jac_scalar_multiplication( - uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *k, uint32_t *p, uint32_t *q) -{ - uint32_t *scalar, *M, *X, *Y, *Z, *mem; - uint32_t *ONE = NULL; - int i, sign, odd; - uint8_t index; - size_t recodeLength = 175u; - size_t bitlen = 0u; - int8_t rec[CASPER_RECODE_LENGTH_MAX] = {0}; - - if (N_wordlen == 8U) - { - recodeLength = (size_t)kCASPER_ECC_P256_recode_len; - bitlen = (size_t)kCASPER_ECC_P256_N_bitlen; - ONE = NISTr256; - } - - if (N_wordlen == 12U) - { - recodeLength = (size_t)kCASPER_ECC_P384_recode_len; - bitlen = (size_t)kCASPER_ECC_P384_N_bitlen; - ONE = NISTr384; - } - - if (N_wordlen == 18U) - { - recodeLength = (size_t)kCASPER_ECC_P521_recode_len; - bitlen = (size_t)521U; - ONE = NISTr521; - } - - /* Point to the start of the LUT table space. */ - mem = &CASPER_MEM[(20U * N_wordlen + 80U)]; - - scalar = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * (N_wordlen + 4U)]; - X = &CASPER_MEM[(20U * N_wordlen + 80U) + 13U * (N_wordlen + 4U)]; - Y = &CASPER_MEM[(20U * N_wordlen + 80U) + 14U * (N_wordlen + 4U)]; - Z = &CASPER_MEM[(20U * N_wordlen + 80U) + 15U * (N_wordlen + 4U)]; - M = &CASPER_MEM[(20U * N_wordlen + 80U) + 16U * (N_wordlen + 4U)]; - - /* Point to memory the recoded scalar. - */ - CASPER_MEMCPY(scalar, k, sizeof(uint32_t) * N_wordlen); - -/* Precomputation: compute 1*P, 3*P, 5*P, and 7*P */ -#define FSL_CASPER_LUT(P, x) (mem + (3U * ((P)-1U) / 2U + (x)) * (N_wordlen + 4U)) - - /* Set 1*P */ - CASPER_MEMCPY(Z3, ONE, N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(FSL_CASPER_LUT(1U, 0U), X1, N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(FSL_CASPER_LUT(1U, 1U), Y1, N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(FSL_CASPER_LUT(1U, 2U), Z3, N_wordlen * sizeof(uint32_t)); - - /* Compute 2*P */ - Jac_double(X3, Y3, Z3, X1, Y1, Z3); - - /* Compute 3*P = 2P + P */ - Jac_add_affine(FSL_CASPER_LUT(3U, 0U), FSL_CASPER_LUT(3U, 1U), FSL_CASPER_LUT(3U, 2U), X3, Y3, Z3, X1, Y1); - - /* Compute 5*P = 3P + 2P */ - Jac_addition(FSL_CASPER_LUT(5U, 0U), FSL_CASPER_LUT(5U, 1U), FSL_CASPER_LUT(5U, 2U), FSL_CASPER_LUT(3U, 0U), - FSL_CASPER_LUT(3U, 1U), FSL_CASPER_LUT(3U, 2U), X3, Y3, Z3); - - /* Compute 7*P = 5P + 2P */ - Jac_addition(FSL_CASPER_LUT(7U, 0U), FSL_CASPER_LUT(7U, 1U), FSL_CASPER_LUT(7U, 2U), FSL_CASPER_LUT(5U, 0U), - FSL_CASPER_LUT(5U, 1U), FSL_CASPER_LUT(5U, 2U), X3, Y3, Z3); - - /* Recode the scalar */ - odd = (int32_t)((uint32_t)(casper_get_word(&scalar[0]) & 1U)); - (void)sub_n(M, q, scalar, (int16_t)(uint16_t)N_wordlen); // todo!!! - casper_select(scalar, M, scalar, odd, (int16_t)(uint16_t)N_wordlen); - - /* Use n=384 and w=4 --> compute ciel(384/3) = 128 + 1 digits */ - uint32_t scalarSysram[CASPER_MAX_ECC_SIZE_WORDLEN]; - CASPER_MEMCPY(scalarSysram, scalar, /*CASPER_*/ N_wordlen * sizeof(uint32_t)); - recode(rec, scalarSysram, (int32_t)bitlen, 4); - - /* Set the first value. */ - index = int8abs(rec[recodeLength - 1U]); - sign = (int32_t)(uint32_t)(uint8_t)(((uint8_t)rec[recodeLength - 1U]) >> 7); - - CASPER_MEMCPY(X3, FSL_CASPER_LUT((uint32_t)index, 0U), N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Y3, FSL_CASPER_LUT((uint32_t)index, 1U), N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Z3, FSL_CASPER_LUT((uint32_t)index, 2U), N_wordlen * sizeof(uint32_t)); - - /* Get the correct LUT element in constant time by touching - * all elements and masking out the correct one. - */ - -#define GET_LUT(x, y, z, index) \ - do \ - { \ - int m; \ - CASPER_MEMCPY((x), FSL_CASPER_LUT(1U, 0U), N_wordlen * sizeof(uint32_t)); \ - CASPER_MEMCPY((y), FSL_CASPER_LUT(1U, 1U), N_wordlen * sizeof(uint32_t)); \ - CASPER_MEMCPY((z), FSL_CASPER_LUT(1U, 2U), N_wordlen * sizeof(uint32_t)); \ - m = (int32_t)((index) == 3U); \ - casper_select((x), (x), FSL_CASPER_LUT(3U, 0U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((y), (y), FSL_CASPER_LUT(3U, 1U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((z), (z), FSL_CASPER_LUT(3U, 2U), m, (int16_t)(uint16_t)N_wordlen); \ - m = (int32_t)((index) == 5U); \ - casper_select((x), (x), FSL_CASPER_LUT(5U, 0U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((y), (y), FSL_CASPER_LUT(5U, 1U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((z), (z), FSL_CASPER_LUT(5U, 2U), m, (int16_t)(uint16_t)N_wordlen); \ - m = (int32_t)((index) == 7U); \ - casper_select((x), (x), FSL_CASPER_LUT(7U, 0U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((y), (y), FSL_CASPER_LUT(7U, 1U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((z), (z), FSL_CASPER_LUT(7U, 2U), m, (int16_t)(uint16_t)N_wordlen); \ - } while (false) - - GET_LUT(X3, Y3, Z3, index); - - /* Compute -y and select the positive or negative point. */ - (void)sub_n(M, p, Y3, (int16_t)(uint16_t)N_wordlen); // todo!!! - casper_select(Y3, Y3, M, sign, (int16_t)(uint16_t)N_wordlen); - - for (i = (int)(uint32_t)(recodeLength - 2U); i >= 0; i--) - { - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - - index = int8abs(rec[i]); - sign = (int32_t)(uint32_t)(uint8_t)(((uint8_t)rec[i]) >> 7); - - GET_LUT(X, Y, Z, index); - - /* Compute -y and select the positive or negative point. */ - (void)sub_n(scalar, p, Y, (int16_t)(uint16_t)N_wordlen); // todo!!! - casper_select(scalar, Y, scalar, sign, (int16_t)(uint16_t)N_wordlen); - - Jac_addition(X3, Y3, Z3, X3, Y3, Z3, X, scalar, Z); - } - - (void)sub_n(M, p, Y3, (int16_t)(uint16_t)N_wordlen); // todo!!! - - casper_select(Y3, M, Y3, odd, (int16_t)(uint16_t)N_wordlen); -} - -#undef FSL_CASPER_LUT -#undef GET_LUT - -/* - * Pre-compute the following 16 points: - * 00 00 = 0*P + 0*Q <-- Not needed when using sliding windows - * 00 01 = 0*P + 1*Q <-- Not needed when using sliding windows - * 00 10 = 0*P + 2*Q - * 00 11 = 0*P + 3*Q - * - * 01 00 = 1*P + 0*Q <-- Not needed when using sliding windows - * 01 01 = 1*P + 1*Q <-- Not needed when using sliding windows - * 01 10 = 1*P + 2*Q - * 01 11 = 1*P + 3*Q - * - * 10 00 = 2*P + 0*Q - * 10 01 = 2*P + 1*Q - * 10 10 = 2*P + 2*Q - * 10 11 = 2*P + 3*Q - * - * 11 00 = 3*P + 0*Q - * 11 01 = 3*P + 1*Q - * 11 10 = 3*P + 2*Q - * 11 11 = 3*P + 3*Q - * - * index = (bitsi||bitsj)-2 - (biti != 0)*2 - * - * Input: P = (X1 : Y1 : Z1) and - * Q = (X2 : Y2 : Z2) - * Output: mem, memory location for the LUT. - */ - -static void precompute_double_scalar_LUT16(uint32_t *Px, uint32_t *Py, uint32_t *Qx, uint32_t *Qy) -{ - uint32_t *Q2x, *Q2y, *Q2z, *P2x, *P2y, *P2z, *Z, *mem; - uint32_t *ONE = NULL; - uint32_t index = 0; - - if (N_wordlen == 8U) - { - ONE = NISTr256; - } - - if (N_wordlen == 12U) - { - ONE = NISTr384; - } - - Q2x = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 0U * (N_wordlen + 4U)]; - Q2y = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 1U * (N_wordlen + 4U)]; - Q2z = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 2U * (N_wordlen + 4U)]; - - /* Re-use memory from different scratch space since no - * projective point addition is used below. */ - P2x = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 5U * (N_wordlen + 4U)]; - P2z = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 6U * (N_wordlen + 4U)]; - P2y = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 7U * (N_wordlen + 4U)]; - Z = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 8U * (N_wordlen + 4U)]; - - mem = &CASPER_MEM[(20U * N_wordlen + 80U)]; - - CASPER_MEMCPY(Z, ONE, N_wordlen * sizeof(uint32_t)); - - // 00 10 = 0*P + 2*Q - Jac_double(Q2x, Q2y, Q2z, Qx, Qy, Z); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 00 11 = 0*P + 3*Q - Jac_add_affine(P2x, P2y, P2z, Q2x, Q2y, Q2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 01 10 = 1*P + 2*Q - Jac_add_affine(P2x, P2y, P2z, Q2x, Q2y, Q2z, Px, Py); - CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 01 11 = 1*P + 3*Q - Jac_add_affine(P2x, P2y, P2z, P2x, P2y, P2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 10 00 = 2*P + 0*Q - Jac_double(P2x, P2y, P2z, Px, Py, Z); - CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 10 01 = 2*P + 1*Q - Jac_add_affine(Q2x, Q2y, Q2z, P2x, P2y, P2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 10 10 = 2*P + 2*Q - Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 10 11 = 2*P + 3*Q - Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 11 00 = 3*P + 0*Q - Jac_add_affine(P2x, P2y, P2z, P2x, P2y, P2z, Px, Py); - CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 11 01 = 3*P + 1*Q - Jac_add_affine(Q2x, Q2y, Q2z, P2x, P2y, P2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 11 10 = 3*P + 2*Q - Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 11 11 = 3*P + 3*Q - Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; -} - -/* - * Pre-compute the following 4 points: - * 0 0 = 0*P + 0*Q <-- Not needed when using sliding windows - * 0 1 = 0*P + 1*Q - * - * 1 0 = 1*P + 0*Q - * 1 1 = 1*P + 1*Q - * - * index = (bitsj+1) & (0-bitsi) - * - * Input: P = (X1 : Y1 : Z1) and - * Q = (X2 : Y2 : Z2) - * Output: mem, memory location for the LUT. - */ - -static void precompute_double_scalar_LUT4(uint32_t *Px, uint32_t *Py, uint32_t *Qx, uint32_t *Qy) -{ - uint32_t *Z, *mem, *ONE; - uint32_t index = 0; - - ONE = NISTr521; - - /* Re-use memory from different scratch space since no - * projective point addition is used below. */ - Z = &CASPER_MEM[(11U * N_wordlen + 4U) + 5U * (N_wordlen + 4U)]; - mem = &CASPER_MEM[(20U * N_wordlen + 80U)]; - - CASPER_MEMCPY(Z, ONE, N_wordlen * sizeof(uint32_t)); - - // 0*P + 1*Q - CASPER_MEMCPY(&mem[index], Qx, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Qy, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 1*P + 0*Q - CASPER_MEMCPY(&mem[index], Px, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Py, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 1*P + 1*Q - Jac_add_affine(&mem[index], &mem[index + N_wordlen], &mem[index + 2U * N_wordlen], Px, Py, Z, Qx, Qy); -} - -#define GETLUTX(x) (3U * (x)*N_wordlen) -#define GETLUTY(x) (3U * (x)*N_wordlen + 1U * N_wordlen) -#define GETLUTZ(x) (3U * (x)*N_wordlen + 2U * N_wordlen) - -/* Compute the double scalar multiplication - * (X3 : Y3 : Z3) = k1 * (X1, Y1) + k2 * (X2, Y2) - * Using Shamir's trick and precomputing 16 points. - * This code is *not* constant time since this is used - * for verification only. - */ -void double_scalar_multiplication(uint32_t *X3, - uint32_t *Y3, - uint32_t *Z3, - uint32_t *X1, - uint32_t *Y1, - uint32_t *k1, - uint32_t *X2, - uint32_t *Y2, - uint32_t *k2) -{ - uint32_t index = 0, c = 0; - uint32_t *p1 = NULL, *p2 = NULL, x1, x2, *lut, *Tx = NULL, *Ty = NULL, *Tz = NULL; - size_t bitlen, shiftr, shiftl = 0u; - - if (N_wordlen == 8U) - { - bitlen = (size_t)kCASPER_ECC_P256_N_bitlen; - precompute_double_scalar_LUT16(X1, Y1, X2, Y2); - shiftr = 30U; - shiftl = 2U; - } - - if (N_wordlen == 12U) - { - bitlen = (size_t)kCASPER_ECC_P384_N_bitlen; - precompute_double_scalar_LUT16(X1, Y1, X2, Y2); - shiftr = 30U; - shiftl = 2U; - } - - if (N_wordlen == 18U) - { - bitlen = (size_t)kCASPER_ECC_P521_N_bitlen; - precompute_double_scalar_LUT4(X1, Y1, X2, Y2); - shiftr = 31U; - shiftl = 1U; - } - - lut = &CASPER_MEM[(20U * N_wordlen + 80U)]; - - if (N_wordlen == 8U || N_wordlen == 12U) - { - p1 = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen]; - p2 = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 1U * (N_wordlen + 4U)]; - - Tx = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 2U * (N_wordlen + 4U)]; - Ty = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 3U * (N_wordlen + 4U)]; - Tz = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 4U * (N_wordlen + 4U)]; - } - - if (N_wordlen == 18U) - { - p1 = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen]; - p2 = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 1U * (N_wordlen + 4U)]; - - Tx = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 2U * (N_wordlen + 4U)]; - Ty = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 3U * (N_wordlen + 4U)]; - Tz = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 4U * (N_wordlen + 4U)]; - } - - CASPER_MEMCPY(p1, k1, sizeof(uint32_t) * N_wordlen); - CASPER_MEMCPY(p2, k2, sizeof(uint32_t) * N_wordlen); - - /* Check if we can slide. */ - while (((casper_get_word(&p1[N_wordlen - 1U]) | casper_get_word(&p2[N_wordlen - 1U])) >> 31) == 0U && c < bitlen) - { - shiftleft(p1, p1, 1U); - shiftleft(p2, p2, 1U); - c++; - /* No doubling needed. */ - } - - /* Set the first value. */ - x1 = casper_get_word(&p1[N_wordlen - 1U]) >> shiftr; - x2 = casper_get_word(&p2[N_wordlen - 1U]) >> shiftr; - if (N_wordlen == 8U || N_wordlen == 12U) - { - index = (x2 | (x1 << 2)) - 2U - (uint32_t)(x1 != 0U) * 2U; - } - - if (N_wordlen == 18U) - { - index = (((x2) + 1U) & (0U - (x1))); - } - shiftleft(p1, p1, shiftl); - shiftleft(p2, p2, shiftl); - - CASPER_MEMCPY(X3, &lut[GETLUTX(index)], N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Y3, &lut[GETLUTY(index)], N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Z3, &lut[GETLUTZ(index)], N_wordlen * sizeof(uint32_t)); - c += shiftl; - - // todo: create an is_zero function - - while ((casper_get_word(&p1[0]) | casper_get_word(&p1[1]) | casper_get_word(&p1[2]) | casper_get_word(&p1[3]) | - casper_get_word(&p1[4]) | casper_get_word(&p1[5]) | casper_get_word(&p1[6]) | casper_get_word(&p1[7]) | - casper_get_word(&p1[8]) | casper_get_word(&p1[9]) | casper_get_word(&p1[10]) | casper_get_word(&p1[11]) | - casper_get_word(&p1[12]) | casper_get_word(&p1[13]) | casper_get_word(&p1[14]) | casper_get_word(&p1[15]) | - casper_get_word(&p1[16]) | casper_get_word(&p1[17]) | casper_get_word(&p2[0]) | casper_get_word(&p2[1]) | - casper_get_word(&p2[2]) | casper_get_word(&p2[3]) | casper_get_word(&p2[4]) | casper_get_word(&p2[5]) | - casper_get_word(&p2[6]) | casper_get_word(&p2[7]) | casper_get_word(&p2[8]) | casper_get_word(&p2[9]) | - casper_get_word(&p2[10]) | casper_get_word(&p2[11]) | casper_get_word(&p2[12]) | casper_get_word(&p2[13]) | - casper_get_word(&p2[14]) | casper_get_word(&p2[15]) | casper_get_word(&p2[16]) | - casper_get_word(&p2[17])) != 0U) - { - /* Check if we can slide. */ - while (((casper_get_word(&p1[N_wordlen - 1U]) | casper_get_word(&p2[N_wordlen - 1U])) >> 31) == 0U && - c < bitlen) - { - shiftleft(p1, p1, 1U); - shiftleft(p2, p2, 1U); - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - c++; - } - - if (c >= (bitlen - 1U)) - { - break; - } - - for (uint32_t i = 0; i < shiftl; i++) - { - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - } - - x1 = casper_get_word(&p1[N_wordlen - 1U]) >> shiftr; - x2 = casper_get_word(&p2[N_wordlen - 1U]) >> shiftr; - - if (N_wordlen == 8U || N_wordlen == 12U) - { - index = (x2 | (x1 << 2)) - 2U - (uint32_t)(x1 != 0U) * 2U; - } - - if (N_wordlen == 18U) - { - index = (((x2) + 1U) & (0U - (x1))); - } - - shiftleft(p1, p1, shiftl); - shiftleft(p2, p2, shiftl); - - CASPER_MEMCPY(Tx, &lut[GETLUTX(index)], N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Ty, &lut[GETLUTY(index)], N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Tz, &lut[GETLUTZ(index)], N_wordlen * sizeof(uint32_t)); - - Jac_addition(X3, Y3, Z3, X3, Y3, Z3, Tx, Ty, - Tz); //&lut[GETLUTX(index)], &lut[GETLUTY(index)], &lut[GETLUTZ(index)]); - c += shiftl; - } - - /* Special case in the end. */ - if (c == (bitlen - 1U)) - { - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - x1 = casper_get_word(&p1[N_wordlen - 1U]) >> 31; - x2 = casper_get_word(&p2[N_wordlen - 1U]) >> 31; - if (0U != x1) - { - Jac_add_affine(X3, Y3, Z3, X3, Y3, Z3, X1, Y1); - } - if (x2 != 0U) - { - Jac_add_affine(X3, Y3, Z3, X3, Y3, Z3, X2, Y2); - } - c++; - } - - while (c < bitlen) - { - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - c++; - } -} - -static void invert_mod_p256(uint32_t *c, uint32_t *a) -{ - int i; - uint32_t *t, *t2, *s1, *s2, *s4, *s8, *tmp; - - /* Assuming it is safe to use the ECC scratch size. */ - t = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - t2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - s1 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - s2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - s4 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - s8 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 7U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - tmp = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 8U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - - // t2 = n^(2^1)*n # 11 - square_casper(tmp, a); - multiply_casper(t2, tmp, a); - - // s1 = t2^(2^2)*t2 # F - square_casper(s1, t2); - square_casper(tmp, s1); - multiply_casper(s1, tmp, t2); - - // s2 = s1^(2^4)*s1 # FF - square_casper(s2, s1); - // for (i = 1; i < 4; i++) square(s2, s2); - square_casper(tmp, s2); - square_casper(s2, tmp); - square_casper(tmp, s2); - multiply_casper(s2, tmp, s1); - - // s4 = s2^(2^8)*s2 # FFFF - square_casper(s4, s2); - for (i = 1; i < 7; i += 2) - { - square_casper(tmp, s4); - square_casper(s4, tmp); - } - square_casper(tmp, s4); - multiply_casper(s4, tmp, s2); - - // s8 = s4^(2^16)*s4 # FFFFFFFF - square_casper(s8, s4); - for (i = 1; i < 15; i += 2) - { - square_casper(tmp, s8); - square_casper(s8, tmp); - } - square_casper(tmp, s8); - multiply_casper(s8, tmp, s4); - - // t = s8^(2^32)*n # ffffffff00000001 - square_casper(tmp, s8); - for (i = 1; i < 31; i += 2) - { - square_casper(t, tmp); - square_casper(tmp, t); - } - square_casper(t, tmp); - multiply_casper(tmp, t, a); - - // t = t^(2^128)*s8 # ffffffff00000001000000000000000000000000ffffffff - for (i = 0; i < 128; i += 2) - { - square_casper(t, tmp); - square_casper(tmp, t); - } - multiply_casper(t, tmp, s8); - - // t = t^(2^32)*s8 # ffffffff00000001000000000000000000000000ffffffffffffffff - for (i = 0; i < 32; i += 2) - { - square_casper(tmp, t); - square_casper(t, tmp); - } - multiply_casper(tmp, t, s8); - - // t = t^(2^16)*s4 # ffffffff00000001000000000000000000000000ffffffffffffffffffff - for (i = 0; i < 16; i += 2) - { - square_casper(t, tmp); - square_casper(tmp, t); - } - multiply_casper(t, tmp, s4); - - // t = t^(2^8)*s2 # ffffffff00000001000000000000000000000000ffffffffffffffffffffff - for (i = 0; i < 8; i += 2) - { - square_casper(tmp, t); - square_casper(t, tmp); - } - multiply_casper(tmp, t, s2); - - // t = t^(2^4)*s1 # ffffffff00000001000000000000000000000000fffffffffffffffffffffff - for (i = 0; i < 4; i += 2) - { - square_casper(t, tmp); - square_casper(tmp, t); - } - multiply_casper(t, tmp, s1); - - // t = t^(2^2)*t2 - square_casper(tmp, t); - square_casper(t, tmp); - multiply_casper(tmp, t, t2); - - // t = t^(2^2)*n # ffffffff00000001000000000000000000000000fffffffffffffffffffffffd - square_casper(t, tmp); - square_casper(tmp, t); - multiply_casper(c, tmp, a); -} - -// A and C do not need to be in Casper memory -static void toMontgomery_ECC_P256(uint32_t *C, uint32_t *A) -{ - /* R^2 = 2^512 mod p, used to convert values to Montgomery form. */ - uint32_t R2[kCASPER_ECC_P256_wordlen] = {0x00000003, 0x00000000, 0xffffffffU, 0xfffffffbU, - 0xfffffffeU, 0xffffffffU, 0xfffffffdU, 0x4}; - uint32_t *T1, *T2, *T3; - T1 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - T2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - T3 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - - CASPER_MEMCPY(T1, R2, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(T2, A, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - - multiply_casper(T3, T2, T1); - CASPER_MEMCPY(C, T3, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); -} - -/* Compute inversion modulo NIST-p384 using Fermats little theorem. - * Using c = a^(p-2) = a^(-1) mod p. - * This computes the modular inversion if all arithmetic is "regular" - * modular arithmetic or computes automatically the Montgomery inverse - * if all arithmetic is Montgomery arithmetic. - */ - -static void invert_mod_p384(uint32_t *c, uint32_t *a) -{ - int i; - uint32_t *e, *d, *tmp, *t0, *t1, *t2, *t3, *t4, *t5, *t6; // 10 residues needed - - /* Assuming it is safe to use the LUT scratch size. - * Hence, do not invert while elements in the LUT are needed. - */ - e = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - d = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - tmp = - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t0 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t1 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t4 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 7U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t5 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 8U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t6 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - - square_casper(tmp, a); // 2 - square_casper(t1, tmp); // 4 - square_casper(tmp, t1); // 8 - multiply_casper(t2, tmp, t1); // 12 - multiply_casper(d, a, t2); // 13 - multiply_casper(e, d, a); // 14 - multiply_casper(t0, e, a); // 15 - - // t1 = t0^(2^4)*t0 # ff - square_casper(tmp, t0); - square_casper(t1, tmp); - square_casper(tmp, t1); - square_casper(t2, tmp); - multiply_casper(t1, t2, t0); - - // t2 = t1^(2^8)*t1 # 4f - square_casper(tmp, t1); - for (i = 0; i < 3; i++) - { - square_casper(t3, tmp); - square_casper(tmp, t3); - } - square_casper(t3, tmp); - multiply_casper(t2, t3, t1); - - // t3 = t2^(2^16)*t2 # 8f - square_casper(tmp, t2); - for (i = 0; i < 7; i++) - { - square_casper(t4, tmp); - square_casper(tmp, t4); - } - square_casper(t4, tmp); - multiply_casper(t3, t4, t2); - - // t4 = t3^(2^32)*t3 # 16f - square_casper(tmp, t3); - for (i = 0; i < 15; i++) - { - square_casper(t5, tmp); - square_casper(tmp, t5); - } - square_casper(t5, tmp); - multiply_casper(t4, t5, t3); - - // t5 = t4^(2^64)*t4 # 32f - square_casper(tmp, t4); - for (i = 0; i < 31; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t4); - - // t5 = t5^(2^64)*t4 # 48f - square_casper(tmp, t5); - for (i = 0; i < 31; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t4); - - // t5 = t5^(2^32)*t3 # 56f - square_casper(tmp, t5); - for (i = 0; i < 15; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t3); - - // t5 = t5^(2^16)*t2 # 60f - square_casper(tmp, t5); - for (i = 0; i < 7; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t2); - - // t5 = t5^(2^8)*t1 # 62f - square_casper(tmp, t5); - for (i = 0; i < 3; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t1); - - // n = t5^(2^4)*t0 # 63f - square_casper(tmp, t5); - for (i = 0; i < 1; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t0); - - // n = n^(2^4)*e - square_casper(tmp, t5); - for (i = 0; i < 1; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, e); - - // n = n^(2^32)*t3 - square_casper(tmp, t5); - for (i = 0; i < 15; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t3); - - // n = n^(2^64) - square_casper(tmp, t5); - for (i = 0; i < 31; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t5, tmp); - - // n = n^(2^16)*t2 - square_casper(tmp, t5); - for (i = 0; i < 7; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t2); - - // n = n^(2^8)*t1 - square_casper(tmp, t5); - for (i = 0; i < 3; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t1); - - // n = n^(2^4)*t0 - square_casper(tmp, t5); - for (i = 0; i < 1; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t0); - - // n = n^(2^4)*d - square_casper(tmp, t5); - for (i = 0; i < 1; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(c, t6, d); -} - -// A and C do not need to be in Casper memory -static void toMontgomery_ECC_P384(uint32_t *C, uint32_t *A) -{ - /* R^2 = 2^768 mod p, used to convert values to Montgomery form. */ - uint32_t R2[kCASPER_ECC_P384_wordlen] = {0x00000001, 0xfffffffeU, 0x00000000, 0x00000002, 0x00000000, 0xfffffffeU, - 0x00000000, 0x00000002, 0x1, 0x0, 0x0, 0x0}; - uint32_t *T1, *T2, *T3; - T1 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - T2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U))) + - 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - T3 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U))) + - 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - - CASPER_MEMCPY(T1, R2, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(T2, A, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - - multiply_casper(T3, T2, T1); - CASPER_MEMCPY(C, T3, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); -} - -static void invert_mod_p521(uint32_t *c, uint32_t *a) -{ - int i; - uint32_t *e3, *d2, *d3, *d4, *T2, *T4; // 6 residues needed - - /* Assuming it is safe to use the LUT scratch size. - * Hence, do not invert while elements in the LUT are needed. - */ - e3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - d2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - d3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - d4 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - T2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - T4 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - - square_casper(d2, a); - multiply_casper(T2, d2, a); - - // d3 = 2^2 * T2 - square_casper(d3, T2); - square_casper(e3, d3); - multiply_casper(T4, e3, T2); - - // d3 = 2^4 * T4 - square_casper(d3, T4); - square_casper(e3, d3); - square_casper(d3, e3); - square_casper(e3, d3); - multiply_casper(d2, e3, T4); - - // d3 = 2^8 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - for (i = 0; i < 3; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d4, e3, d2); - - // d3 = 2^16 * d2 - square_casper(d3, d4); - square_casper(e3, d3); - for (i = 0; i < 7; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d2, e3, d4); - - // d3 = 2^32 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - for (i = 0; i < 15; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d4, e3, d2); - - // d3 = 2^64 * d2 - square_casper(d3, d4); - square_casper(e3, d3); - for (i = 0; i < 31; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d2, e3, d4); - - // d3 = 2^128 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - for (i = 0; i < 63; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d4, e3, d2); - - // d3 = 2^256 * d2 - square_casper(d3, d4); - square_casper(e3, d3); - for (i = 0; i < 127; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d2, e3, d4); - - // d3 = 2^2 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - multiply_casper(d2, e3, T2); - - // d3 = 2^4 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - square_casper(d3, e3); - square_casper(e3, d3); - multiply_casper(d2, e3, T4); - - square_casper(d3, d2); - multiply_casper(d2, d3, a); - - // d3 = 2 ^ 2 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - multiply_casper(c, e3, a); -} - -static void toMontgomery_ECC_P521(uint32_t *C, uint32_t *A) -{ - /* R^2 = 2^1088 mod p, used to convert values to Montgomery form. */ - // uint32_t R2[NUM_LIMBS] = { 0x00000000, 0x4000, 0, 0, - // 0, 0, 0, 0, - // 0, 0, 0, 0, - // 0 }; - /* R^2 = 2^1152 mod p, used to convert values to Montgomery form. */ - uint32_t R2[kCASPER_ECC_P521_wordlen] = {0, 0, 0, 0x4000, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - - uint32_t *T1, *T2, *T3; - T1 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - T2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - T3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - - CASPER_MEMCPY(T1, R2, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(T2, A, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - - multiply_casper(T3, T2, T1); - CASPER_MEMCPY(C, T3, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); -} - -static void MultprecCiosMul521_ct( - uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np) -{ - uint32_t j; - uint64_t carry; - uint64_t *a64, *b64, *w64; - - uint32_t *T1 = &CASPER_MEM[0], borrow; - - a64 = (uint64_t *)(uintptr_t)a; - b64 = (uint64_t *)(uintptr_t)b; - w64 = (uint64_t *)(uintptr_t)w_out; - - if (a != NULL) - { /* if !a, we are reducing only */ - PreZeroW(j, w_out); - } - SET_DWORD(&w64[N_dwordlen], 0ULL); - SET_DWORD(&w64[N_dwordlen + 1U], 0ULL); - /* with accelerator */ - - /* loop j and then reduce after each j round */ - for (j = 0; j < N_dwordlen; j++) - { - /* Step 3. Iterate over N words of u using j - perform Multiply-accumulate */ - /* push-pull: we do a*b and then separately m*n (reduce) */ - if (a != NULL) - { /* if mul&reduce vs. reduce only */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(&b64[j]), CA_MK_OFF(a64)); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); - Accel_done(); - /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ - /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ - /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ - /* w64[N_dwordlen+1] = g_carry; */ - carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); - SET_DWORD(&w64[N_dwordlen + 1U], carry); - } - - /* Fast reduction using only shifts for this special shape: - * (c - (-p^-1*c mod 2^64) * p)/2^64 = - * (c - c_0 * p)/2^64 = - * (\sum_{j=0}^9 c_i*2^64 - c_0 * p)/2^64 = - * (\sum_{j=0}^9 c_i*2^64 - c_0 * (2^521-1))/2^64 = - * (\sum_{j=0}^9 c_i*2^64 - c_0 * 2^521 - c_0)/2^64 = - * c_1 + c_2*2^64 + c_3*2^128 + c_4*2^192 + c_5*2^256 + c_6*2^320 + c_7*2^384 + c_8*2^448 + c_9*2^512 + c_0 * - * 2^{448 + 9} so one only needs to compute this 128-bit addition: [c_8, c_9] + c_0 * 2^9 - */ - - uint64_t *p64 = (uint64_t *)(uintptr_t)T1; - - /* p64[0] = w64[0] << 9;*/ - SET_DWORD(&p64[0], GET_DWORD(&w64[0]) << 9U); - /* p64[1] = w64[0] >> (64 - 9); */ - SET_DWORD(&p64[1], GET_DWORD(&w64[0]) >> (64 - 9)); - /* w64[0] = w64[1]; */ - SET_DWORD(&w64[0], GET_DWORD(&w64[1])); - /* w64[1] = w64[2]; */ - SET_DWORD(&w64[1], GET_DWORD(&w64[2])); - /* w64[2] = w64[3]; */ - SET_DWORD(&w64[2], GET_DWORD(&w64[3])); - /* w64[3] = w64[4]; */ - SET_DWORD(&w64[3], GET_DWORD(&w64[4])); - /* w64[4] = w64[5]; */ - SET_DWORD(&w64[4], GET_DWORD(&w64[5])); - /* w64[5] = w64[6]; */ - SET_DWORD(&w64[5], GET_DWORD(&w64[6])); - /* w64[6] = w64[7]; */ - SET_DWORD(&w64[6], GET_DWORD(&w64[7])); - - /* Compute p64 = p64 + {w64[8], w64[9]} using one additonal double-length limb, - * where p64 = w64[0] * 2^9. - */ - Accel_SetABCD_Addr(CA_MK_OFF(&w64[8]), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(2, (uint32_t)kCASPER_OpAdd64, /* kCASPER_OpAdd64, */ - CA_MK_OFF(p64))); - Accel_done(); - - /* w64[7] = p64[0]; */ - SET_DWORD(&w64[7], GET_DWORD(&p64[0])); - /* w64[8] = p64[1]; */ - SET_DWORD(&w64[8], GET_DWORD(&p64[1])); - /* w64[9] = 0; */ - SET_DWORD(&w64[9], (uint64_t)0U); - } - - /* memcpy(T1, w_out, (NUM_LIMBS + 1) * sizeof(uint32_t)); */ - /* now check if need to subtract Nmod */ - CASPER_MEMCPY_I2I(T1, w_out, (N_wordlen + 1U) * sizeof(uint32_t)); - - /* Compute w = w - N */ - Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(w_out))); - Accel_done(); - - /* if w_out > T1 then there was a borrow */ - /* borrow = (((uint32_t*)w_out)[NUM_LIMBS] > T1[NUM_LIMBS]); */ - borrow = (uint32_t)(GET_WORD(&((uint32_t *)w_out)[N_wordlen]) > GET_WORD(&T1[N_wordlen])); - SET_WORD(&w_out[N_wordlen + 1U], 0); - SET_WORD(&w_out[N_wordlen], 0); - /* w_out[NUM_LIMBS + 1] = 0; */ - /* w_out[NUM_LIMBS] = 0; */ - casper_select(w_out, w_out, T1, (int32_t)borrow, (int32_t)N_wordlen); -} - -#if defined(__GNUC__) -/* End of enforcing O1 optimize level for gcc*/ -#pragma GCC pop_options -#endif - -#if (defined(__CC_ARM) || defined(__ARMCC_VERSION)) -// End of enforcing optimize off for clang -#pragma clang optimize on -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_casper.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_casper.h deleted file mode 100644 index 328dc101116..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_casper.h +++ /dev/null @@ -1,386 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CASPER_H_ -#define _FSL_CASPER_H_ - -#include "fsl_common.h" - -/*! @file */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! - * @addtogroup casper_driver - * @{ - */ -/*! @name Driver version */ -/*@{*/ -/*! @brief CASPER driver version. Version 2.2.3. - * - * Current version: 2.2.3 - * - * Change log: - * - Version 2.0.0 - * - Initial version - * - Version 2.0.1 - * - Bug fix KPSDK-24531 double_scalar_multiplication() result may be all zeroes for some specific input - * - Version 2.0.2 - * - Bug fix KPSDK-25015 CASPER_MEMCPY hard-fault on LPC55xx when both source and destination buffers are outside of - * CASPER_RAM - * - Version 2.0.3 - * - Bug fix KPSDK-28107 RSUB, FILL and ZERO operations not implemented in enum _casper_operation. - * - Version 2.0.4 - * - For GCC compiler, enforce O1 optimize level, specifically to remove strict-aliasing option. - * This driver is very specific and requires -fno-strict-aliasing. - * - Version 2.0.5 - * - Fix sign-compare warning. - * - Version 2.0.6 - * - Fix IAR Pa082 warning. - * - Version 2.0.7 - * - Fix MISRA-C 2012 issue. - * - Version 2.0.8 - * - Add feature macro for CASPER_RAM_OFFSET. - * - Version 2.0.9 - * - Remove unused function Jac_oncurve(). - * - Fix ECC384 build. - * - Version 2.0.10 - * - Fix MISRA-C 2012 issue. - * - Version 2.1.0 - * - Add ECC NIST P-521 elliptic curve. - * - Version 2.2.0 - * - Rework driver to support multiple curves at once. - * - Version 2.2.1 - * - Fix MISRA-C 2012 issue. - * - Version 2.2.2 - * - Enable hardware interleaving to RAMX0 and RAMX1 for CASPER by feature macro FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE - * - Version 2.2.3 - * - Added macro into CASPER_Init and CASPER_Deinit to support devices without clock and reset control. - */ -#define FSL_CASPER_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) -/*@}*/ - -/*! @brief CASPER operation - * - */ -typedef enum _casper_operation -{ - kCASPER_OpMul6464NoSum = 0x01, /*! Walking 1 or more of J loop, doing r=a*b using 64x64=128*/ - kCASPER_OpMul6464Sum = - 0x02, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but assume inner j loop*/ - kCASPER_OpMul6464FullSum = - 0x03, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but sum all of w. */ - kCASPER_OpMul6464Reduce = - 0x04, /*! Walking 1 or more of J loop, doing c,r[-1]=r+a*b using 64x64=128, but skip 1st write*/ - kCASPER_OpAdd64 = 0x08, /*! Walking add with off_AB, and in/out off_RES doing c,r=r+a+c using 64+64=65*/ - kCASPER_OpSub64 = 0x09, /*! Walking subtract with off_AB, and in/out off_RES doing r=r-a using 64-64=64, with last - borrow implicit if any*/ - kCASPER_OpDouble64 = 0x0A, /*! Walking add to self with off_RES doing c,r=r+r+c using 64+64=65*/ - kCASPER_OpXor64 = 0x0B, /*! Walking XOR with off_AB, and in/out off_RES doing r=r^a using 64^64=64*/ - kCASPER_OpRSub64 = 0x0C, /*! Walking subtract with off_AB, and in/out off_RES using r=a-r */ - kCASPER_OpShiftLeft32 = - 0x10, /*! Walking shift left doing r1,r=(b*D)|r1, where D is 2^amt and is loaded by app (off_CD not used)*/ - kCASPER_OpShiftRight32 = 0x11, /*! Walking shift right doing r,r1=(b*D)|r1, where D is 2^(32-amt) and is loaded by - app (off_CD not used) and off_RES starts at MSW*/ - kCASPER_OpCopy = 0x14, /*! Copy from ABoff to resoff, 64b at a time*/ - kCASPER_OpRemask = 0x15, /*! Copy and mask from ABoff to resoff, 64b at a time*/ - kCASPER_OpFill = 0x16, /*! Fill RESOFF using 64 bits at a time with value in A and B */ - kCASPER_OpZero = 0x17, /*! Fill RESOFF using 64 bits at a time of 0s */ - kCASPER_OpCompare = 0x18, /*! Compare two arrays, running all the way to the end*/ - kCASPER_OpCompareFast = 0x19, /*! Compare two arrays, stopping on 1st !=*/ -} casper_operation_t; - -/*! @brief Algorithm used for CASPER operation */ -typedef enum _casper_algo_t -{ - kCASPER_ECC_P256 = 0x01, /*!< ECC_P256*/ - kCASPER_ECC_P384 = 0x02, /*!< ECC_P384 */ - kCASPER_ECC_P521 = 0x03, /*!< ECC_P521 */ -} casper_algo_t; - -#define CASPER_CP 1 -#define CASPER_CP_CTRL0 (0x0 >> 2) -#define CASPER_CP_CTRL1 (0x4 >> 2) -#define CASPER_CP_LOADER (0x8 >> 2) -#define CASPER_CP_STATUS (0xC >> 2) -#define CASPER_CP_INTENSET (0x10 >> 2) -#define CASPER_CP_INTENCLR (0x14 >> 2) -#define CASPER_CP_INTSTAT (0x18 >> 2) -#define CASPER_CP_AREG (0x20 >> 2) -#define CASPER_CP_BREG (0x24 >> 2) -#define CASPER_CP_CREG (0x28 >> 2) -#define CASPER_CP_DREG (0x2C >> 2) -#define CASPER_CP_RES0 (0x30 >> 2) -#define CASPER_CP_RES1 (0x34 >> 2) -#define CASPER_CP_RES2 (0x38 >> 2) -#define CASPER_CP_RES3 (0x3C >> 2) -#define CASPER_CP_MASK (0x60 >> 2) -#define CASPER_CP_REMASK (0x64 >> 2) -#define CASPER_CP_LOCK (0x80 >> 2) -#define CASPER_CP_ID (0xFFC >> 2) -/* mcr (cp, opc1, value, CRn, CRm, opc2) */ -#define CASPER_Wr32b(value, off) __arm_mcr(CASPER_CP, 0, value, ((off >> 4)), (off), 0) -/* mcrr(coproc, opc1, value, CRm) */ -#define CASPER_Wr64b(value, off) __arm_mcrr(CASPER_CP, 0, value, off) -/* mrc(coproc, opc1, CRn, CRm, opc2) */ -#define CASPER_Rd32b(off) __arm_mrc(CASPER_CP, 0, ((off >> 4)), (off), 0) - -/* The model for this algo is that it can be implemented for a fixed size RSA key */ -/* for max speed. If this is made into a variable (to allow varying size), then */ -/* it will be slower by a bit. */ -/* The file is compiled with N_bitlen passed in as number of bits of the RSA key */ -/* #define N_bitlen 2048 */ -#define N_wordlen_max (4096U / 32U) - -enum -{ - kCASPER_RamOffset_Result = 0x0u, - kCASPER_RamOffset_Base = (N_wordlen_max + 8u), - kCASPER_RamOffset_TempBase = (2u * N_wordlen_max + 16u), - kCASPER_RamOffset_Modulus = (kCASPER_RamOffset_TempBase + N_wordlen_max + 4u), - kCASPER_RamOffset_M64 = 1022U, -}; - -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup casper_driver - * @{ - */ - -/*! - * @brief Enables clock and disables reset for CASPER peripheral. - * - * Enable clock and disable reset for CASPER. - * - * @param base CASPER base address - */ -void CASPER_Init(CASPER_Type *base); - -/*! - * @brief Disables clock for CASPER peripheral. - * - * Disable clock and enable reset. - * - * @param base CASPER base address - */ -void CASPER_Deinit(CASPER_Type *base); - -/*! - *@} - */ /* end of casper_driver */ - -/******************************************************************************* - * PKHA API - ******************************************************************************/ - -/*! - * @addtogroup casper_driver_pkha - * @{ - */ - -/*! - * @brief Performs modular exponentiation - (A^E) mod N. - * - * This function performs modular exponentiation. - * - * @param base CASPER base address - * @param signature first addend (in little endian format) - * @param pubN modulus (in little endian format) - * @param wordLen Size of pubN in bytes - * @param pubE exponent - * @param[out] plaintext Output array to store result of operation (in little endian format) - */ -void CASPER_ModExp(CASPER_Type *base, - const uint8_t *signature, - const uint8_t *pubN, - size_t wordLen, - uint32_t pubE, - uint8_t *plaintext); - -/*! - * @brief Initialize prime modulus mod in Casper memory . - * - * Set the prime modulus mod in Casper memory and set N_wordlen - * according to selected algorithm. - * - * @param curve elliptic curve algoritm - */ -void CASPER_ecc_init(casper_algo_t curve); - -/*! - * @brief Performs ECC secp256r1 point single scalar multiplication - * - * This function performs ECC secp256r1 point single scalar multiplication - * [resX; resY] = scalar * [X; Y] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate in normal form, little endian. - * @param[out] resY Output Y affine coordinate in normal form, little endian. - * @param X Input X affine coordinate in normal form, little endian. - * @param Y Input Y affine coordinate in normal form, little endian. - * @param scalar Input scalar integer, in normal form, little endian. - */ -void CASPER_ECC_SECP256R1_Mul( - CASPER_Type *base, uint32_t resX[8], uint32_t resY[8], uint32_t X[8], uint32_t Y[8], uint32_t scalar[8]); - -/*! - * @brief Performs ECC secp256r1 point double scalar multiplication - * - * This function performs ECC secp256r1 point double scalar multiplication - * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate. - * @param[out] resY Output Y affine coordinate. - * @param X1 Input X1 affine coordinate. - * @param Y1 Input Y1 affine coordinate. - * @param scalar1 Input scalar1 integer. - * @param X2 Input X2 affine coordinate. - * @param Y2 Input Y2 affine coordinate. - * @param scalar2 Input scalar2 integer. - */ -void CASPER_ECC_SECP256R1_MulAdd(CASPER_Type *base, - uint32_t resX[8], - uint32_t resY[8], - uint32_t X1[8], - uint32_t Y1[8], - uint32_t scalar1[8], - uint32_t X2[8], - uint32_t Y2[8], - uint32_t scalar2[8]); - -/*! - * @brief Performs ECC secp384r1 point single scalar multiplication - * - * This function performs ECC secp384r1 point single scalar multiplication - * [resX; resY] = scalar * [X; Y] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate in normal form, little endian. - * @param[out] resY Output Y affine coordinate in normal form, little endian. - * @param X Input X affine coordinate in normal form, little endian. - * @param Y Input Y affine coordinate in normal form, little endian. - * @param scalar Input scalar integer, in normal form, little endian. - */ -void CASPER_ECC_SECP384R1_Mul( - CASPER_Type *base, uint32_t resX[12], uint32_t resY[12], uint32_t X[12], uint32_t Y[12], uint32_t scalar[12]); - -/*! - * @brief Performs ECC secp384r1 point double scalar multiplication - * - * This function performs ECC secp384r1 point double scalar multiplication - * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate. - * @param[out] resY Output Y affine coordinate. - * @param X1 Input X1 affine coordinate. - * @param Y1 Input Y1 affine coordinate. - * @param scalar1 Input scalar1 integer. - * @param X2 Input X2 affine coordinate. - * @param Y2 Input Y2 affine coordinate. - * @param scalar2 Input scalar2 integer. - */ -void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base, - uint32_t resX[12], - uint32_t resY[12], - uint32_t X1[12], - uint32_t Y1[12], - uint32_t scalar1[12], - uint32_t X2[12], - uint32_t Y2[12], - uint32_t scalar2[12]); - -/*! - * @brief Performs ECC secp521r1 point single scalar multiplication - * - * This function performs ECC secp521r1 point single scalar multiplication - * [resX; resY] = scalar * [X; Y] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate in normal form, little endian. - * @param[out] resY Output Y affine coordinate in normal form, little endian. - * @param X Input X affine coordinate in normal form, little endian. - * @param Y Input Y affine coordinate in normal form, little endian. - * @param scalar Input scalar integer, in normal form, little endian. - */ -void CASPER_ECC_SECP521R1_Mul( - CASPER_Type *base, uint32_t resX[18], uint32_t resY[18], uint32_t X[18], uint32_t Y[18], uint32_t scalar[18]); - -/*! - * @brief Performs ECC secp521r1 point double scalar multiplication - * - * This function performs ECC secp521r1 point double scalar multiplication - * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate. - * @param[out] resY Output Y affine coordinate. - * @param X1 Input X1 affine coordinate. - * @param Y1 Input Y1 affine coordinate. - * @param scalar1 Input scalar1 integer. - * @param X2 Input X2 affine coordinate. - * @param Y2 Input Y2 affine coordinate. - * @param scalar2 Input scalar2 integer. - */ -void CASPER_ECC_SECP521R1_MulAdd(CASPER_Type *base, - uint32_t resX[18], - uint32_t resY[18], - uint32_t X1[18], - uint32_t Y1[18], - uint32_t scalar1[18], - uint32_t X2[18], - uint32_t Y2[18], - uint32_t scalar2[18]); - -void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2); -void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1); - -/*! - *@} - */ /* end of casper_driver_pkha */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_CASPER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_clock.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_clock.c deleted file mode 100644 index 80460c09050..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_clock.c +++ /dev/null @@ -1,2106 +0,0 @@ -/* - * Copyright 2017 - 2021 , NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_clock.h" -#include "fsl_power.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.clock" -#endif -#define NVALMAX (0x100U) -#define PVALMAX (0x20U) -#define MVALMAX (0x10000U) - -#define PLL_MAX_N_DIV 0x100U - -/*-------------------------------------------------------------------------- -!!! If required these #defines can be moved to chip library file -----------------------------------------------------------------------------*/ - -#define PLL_SSCG1_MDEC_VAL_P (10U) /* MDEC is in bits 25 downto 10 */ -#define PLL_SSCG1_MDEC_VAL_M (0xFFFFULL << PLL_SSCG1_MDEC_VAL_P) -#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */ -#define PLL_NDEC_VAL_M (0xFFUL << PLL_NDEC_VAL_P) -#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */ -#define PLL_PDEC_VAL_M (0x1FUL << PLL_PDEC_VAL_P) - -#define PLL_MIN_CCO_FREQ_MHZ (275000000U) -#define PLL_MAX_CCO_FREQ_MHZ (550000000U) -#define PLL_LOWER_IN_LIMIT (2000U) /*!< Minimum PLL input rate */ -#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */ -#define PLL_MIN_IN_SSMODE (3000000U) -#define PLL_MAX_IN_SSMODE \ - (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */ - -/* PLL NDEC reg */ -#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) -/* PLL PDEC reg */ -#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M) -/* SSCG control1 */ -#define PLL_SSCG1_MDEC_VAL_SET(value) (((uint64_t)(value) << PLL_SSCG1_MDEC_VAL_P) & PLL_SSCG1_MDEC_VAL_M) - -/* PLL0 SSCG control1 */ -#define PLL0_SSCG_MD_FRACT_P 0U -#define PLL0_SSCG_MD_INT_P 25U -#define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) -#define PLL0_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL0_SSCG_MD_INT_P) - -#define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_FRACT_M) -#define PLL0_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_INT_P) & PLL0_SSCG_MD_INT_M) - -/* Saved value of PLL output rate, computed whenever needed to save run-time - computation on each call to retrive the PLL rate. */ -static uint32_t s_Pll0_Freq; -static uint32_t s_Pll1_Freq; - -/** External clock rate on the CLKIN pin in Hz. If not used, - set this to 0. Otherwise, set it to the exact rate in Hz this pin is - being driven at. */ -static uint32_t s_Ext_Clk_Freq = 16000000U; -static uint32_t s_I2S_Mclk_Freq = 0U; -static uint32_t s_PLU_ClkIn_Freq = 0U; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ -static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); -/* Get predivider (N) from PLL0 NDEC setting */ -static uint32_t findPll0PreDiv(void); -/* Get predivider (N) from PLL1 NDEC setting */ -static uint32_t findPll1PreDiv(void); -/* Get postdivider (P) from PLL0 PDEC setting */ -static uint32_t findPll0PostDiv(void); -/* Get multiplier (M) from PLL0 MDEC and SSCG settings */ -static float findPll0MMult(void); -/* Get the greatest common divisor */ -static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); -/* Set PLL output based on desired output rate */ -static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS); -/* Update local PLL rate variable */ -static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup); - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Clock Selection for IP */ -/** - * brief Configure the clock selection muxes. - * param connection : Clock to be configured. - * return Nothing - */ -void CLOCK_AttachClk(clock_attach_id_t connection) -{ - uint8_t mux; - uint8_t sel; - uint16_t item; - uint32_t tmp32 = (uint32_t)connection; - uint32_t i; - volatile uint32_t *pClkSel; - - pClkSel = &(SYSCON->SYSTICKCLKSELX[0]); - - if (kNONE_to_NONE != connection) - { - for (i = 0U; i < 2U; i++) - { - if (tmp32 == 0U) - { - break; - } - item = (uint16_t)GET_ID_ITEM(tmp32); - if (item != 0U) - { - mux = GET_ID_ITEM_MUX(item); - sel = GET_ID_ITEM_SEL(item); - if (mux == CM_RTCOSC32KCLKSEL) - { - PMC->RTCOSC32K |= sel; - } - else - { - pClkSel[mux] = sel; - } - } - tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */ - } - } -} - -/* Return the actual clock attach id */ -/** - * brief Get the actual clock attach id. - * This fuction uses the offset in input attach id, then it reads the actual source value in - * the register and combine the offset to obtain an actual attach id. - * param attachId : Clock attach id to get. - * return Clock source value. - */ -clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId) -{ - uint8_t mux; - uint8_t actualSel; - uint32_t tmp32 = (uint32_t)attachId; - uint32_t i; - uint32_t actualAttachId = 0U; - uint32_t selector = GET_ID_SELECTOR(tmp32); - volatile uint32_t *pClkSel; - - pClkSel = &(SYSCON->SYSTICKCLKSELX[0]); - - if (kNONE_to_NONE == attachId) - { - return kNONE_to_NONE; - } - - for (i = 0U; i < 2U; i++) - { - mux = GET_ID_ITEM_MUX(tmp32); - if (tmp32 != 0UL) - { - if (mux == CM_RTCOSC32KCLKSEL) - { - actualSel = (uint8_t)(PMC->RTCOSC32K); - } - else - { - actualSel = (uint8_t)(pClkSel[mux]); - } - - /* Consider the combination of two registers */ - actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i); - } - tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */ - } - - actualAttachId |= selector; - - return (clock_attach_id_t)actualAttachId; -} - -/* Set IP Clock Divider */ -/** - * brief Setup peripheral clock dividers. - * param div_name : Clock divider name - * param divided_by_value: Value to be divided - * param reset : Whether to reset the divider counter. - * return Nothing - */ -void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) -{ - volatile uint32_t *pClkDiv; - - pClkDiv = &(SYSCON->SYSTICKCLKDIV0); - if ((div_name >= kCLOCK_DivFlexFrg0) && (div_name <= kCLOCK_DivFlexFrg7)) - { - /*!< Flexcomm Interface function clock = (clock selected via FCCLKSEL) / (1+ MULT /DIV), DIV = 0xFF */ - ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = - SYSCON_FLEXFRG0CTRL_DIV_MASK | SYSCON_FLEXFRG0CTRL_MULT(divided_by_value); - } - else - { - if (reset) - { - ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = 1UL << 29U; - } - if (divided_by_value == 0U) /*!< halt */ - { - ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = 1UL << 30U; - } - else - { - ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = (divided_by_value - 1U); - } - } -} - -/* Set RTC 1KHz Clock Divider */ -/** - * brief Setup rtc 1khz clock divider. - * param divided_by_value: Value to be divided - * return Nothing - */ -void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value) -{ - PMC->RTCOSC32K |= (((divided_by_value - 28U) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT) | PMC_RTCOSC32K_CLK1KHZDIV_MASK); -} - -/* Set RTC 1KHz Clock Divider */ -/** - * brief Setup rtc 1hz clock divider. - * param divided_by_value: Value to be divided - * return Nothing - */ -void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value) -{ - if (divided_by_value == 0U) /*!< halt */ - { - PMC->RTCOSC32K |= (1UL << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT); - } - else - { - PMC->RTCOSC32K |= - (((divided_by_value - 31744U) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT) | PMC_RTCOSC32K_CLK1HZDIV_MASK); - } -} - -/* Set FRO Clocking */ -/** - * brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). - * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is - * enabled. - * param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ) - * return returns success or fail status. - */ -status_t CLOCK_SetupFROClocking(uint32_t iFreq) -{ - if ((iFreq != 12000000U) && (iFreq != 48000000U) && (iFreq != 96000000U)) - { - return kStatus_Fail; - } - /* Enable Analog Control module */ - SYSCON->PRESETCTRLCLR[2] = (1UL << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT); - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK; - /* Power up the FRO192M */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); - - if (iFreq == 96000000U) - { - ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(1); - } - /* always enable - else if (iFreq == 48000000U) - { - ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(1); - }*/ - else - { - ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(1); - } - return kStatus_Success; -} - -/* Set the FLASH wait states for the passed frequency */ -/** - * brief Set the flash wait states for the input freuqency. - * param iFreq: Input frequency - * return Nothing - */ -void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq) -{ - uint32_t num_wait_states; /* Flash Controller & FMC internal number of Wait States (minus 1) */ - - if (iFreq <= 11000000UL) - { - /* [0 - 11 MHz] */ - num_wait_states = 0UL; - } - else if (iFreq <= 22000000UL) - { - /* [11 MHz - 22 MHz] */ - num_wait_states = 1UL; - } - else if (iFreq <= 33000000UL) - { - /* [22 MHz - 33 MHz] */ - num_wait_states = 2UL; - } - else if (iFreq <= 44000000UL) - { - /* [33 MHz - 44 MHz] */ - num_wait_states = 3UL; - } - else if (iFreq <= 55000000UL) - { - /* [44 MHz - 55 MHz] */ - num_wait_states = 4UL; - } - else if (iFreq <= 66000000UL) - { - /* [55 MHz - 662 MHz] */ - num_wait_states = 5UL; - } - else if (iFreq <= 77000000UL) - { - /* [66 MHz - 77 MHz] */ - num_wait_states = 6UL; - } - else if (iFreq <= 88000000UL) - { - /* [77 MHz - 88 MHz] */ - num_wait_states = 7UL; - } - else if (iFreq <= 100000000UL) - { - /* [88 MHz - 100 MHz] */ - num_wait_states = 8UL; - } - else if (iFreq <= 115000000UL) - { - /* [100 MHz - 115 MHz] */ - num_wait_states = 9UL; - } - else if (iFreq <= 130000000UL) - { - /* [115 MHz - 130 MHz] */ - num_wait_states = 10UL; - } - else if (iFreq <= 150000000UL) - { - /* [130 MHz - 150 MHz] */ - num_wait_states = 11UL; - } - else - { - /* Above 150 MHz */ - num_wait_states = 12UL; - } - - FLASH->INT_CLR_STATUS = 0x1FUL; /* Clear all status flags */ - - FLASH->DATAW[0] = (FLASH->DATAW[0] & 0xFFFFFFF0UL) | - (num_wait_states & (SYSCON_FMCCR_FLASHTIM_MASK >> SYSCON_FMCCR_FLASHTIM_SHIFT)); - - FLASH->CMD = 0x2; /* CMD_SET_READ_MODE */ - - /* Wait until the cmd is completed (without error) */ - while (0UL == (FLASH->INT_STATUS & FLASH_INT_STATUS_DONE_MASK)) - { - ; - } - - /* Adjust FMC waiting time cycles (num_wait_states) */ - SYSCON->FMCCR = (SYSCON->FMCCR & ~SYSCON_FMCCR_FLASHTIM_MASK) | - ((num_wait_states << SYSCON_FMCCR_FLASHTIM_SHIFT) & SYSCON_FMCCR_FLASHTIM_MASK); -} - -/* Set EXT OSC Clk */ -/** - * brief Initialize the external osc clock to given frequency. - * Crystal oscillator with an operating frequency of 12 MHz to 32 MHz. - * Option for external clock input (bypass mode) for clock frequencies of up to 25 MHz. - * param iFreq : Desired frequency (must be equal to exact rate in Hz) - * return returns success or fail status. - */ -status_t CLOCK_SetupExtClocking(uint32_t iFreq) -{ - if (iFreq > 32000000U) - { - return kStatus_Fail; - } - /* Turn on power for crystal 32 MHz */ - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); - /* Enable clock_in clock for clock module. */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; - - s_Ext_Clk_Freq = iFreq; - return kStatus_Success; -} - -/* Set I2S MCLK Clk */ -/** - * brief Initialize the I2S MCLK clock to given frequency. - * param iFreq : Desired frequency (must be equal to exact rate in Hz) - * return returns success or fail status. - */ -status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq) -{ - s_I2S_Mclk_Freq = iFreq; - return kStatus_Success; -} - -/* Set PLU CLKIN Clk */ -/** - * brief Initialize the PLU CLKIN clock to given frequency. - * param iFreq : Desired frequency (must be equal to exact rate in Hz) - * return returns success or fail status. - */ -status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq) -{ - s_PLU_ClkIn_Freq = iFreq; - return kStatus_Success; -} - -/* Get CLOCK OUT Clk */ -/*! brief Return Frequency of ClockOut - * return Frequency of ClockOut - */ -uint32_t CLOCK_GetClockOutClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->CLKOUTSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - - case 2U: - freq = CLOCK_GetExtClkFreq(); - break; - - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - - case 5U: - freq = CLOCK_GetPll1OutFreq(); - break; - - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - - case 7U: - freq = 0U; - break; - - default: - assert(false); - break; - } - return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U); -} - -/* Get ADC Clk */ -/*! brief Return Frequency of Adc Clock - * return Frequency of Adc. - */ -uint32_t CLOCK_GetAdcClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->ADCCLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 2U: - freq = CLOCK_GetFroHfFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - assert(false); - break; - } - - return freq / ((SYSCON->ADCCLKDIV & SYSCON_ADCCLKDIV_DIV_MASK) + 1U); -} - -/* Get USB0 Clk */ -/*! brief Return Frequency of Usb0 Clock - * return Frequency of Usb0 Clock. - */ -uint32_t CLOCK_GetUsb0ClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->USB0CLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 5U: - freq = CLOCK_GetPll1OutFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - assert(false); - break; - } - - return freq / ((SYSCON->USB0CLKDIV & 0xffU) + 1U); -} - -/* Get USB1 Clk */ -/*! brief Return Frequency of Usb1 Clock - * return Frequency of Usb1 Clock. - */ -uint32_t CLOCK_GetUsb1ClkFreq(void) -{ - return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; -} - -/* Get MCLK Clk */ -/*! brief Return Frequency of MClk Clock - * return Frequency of MClk Clock. - */ -uint32_t CLOCK_GetMclkClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->MCLKCLKSEL) - { - case 0U: - freq = CLOCK_GetFroHfFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - assert(false); - break; - } - - return freq / ((SYSCON->MCLKDIV & 0xffU) + 1U); -} - -/* Get SCTIMER Clk */ -/*! brief Return Frequency of SCTimer Clock - * return Frequency of SCTimer Clock. - */ -uint32_t CLOCK_GetSctClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->SCTCLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 2U: - freq = CLOCK_GetExtClkFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 5U: - freq = CLOCK_GetI2SMClkFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - assert(false); - break; - } - - return freq / ((SYSCON->SCTCLKDIV & 0xffU) + 1U); -} - -/* Get SDIO Clk */ -/*! brief Return Frequency of SDIO Clock - * return Frequency of SDIO Clock. - */ -uint32_t CLOCK_GetSdioClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->SDIOCLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 5U: - freq = CLOCK_GetPll1OutFreq(); - break; - case 7U: - freq = 0U; - break; - default: - assert(false); - break; - } - - return freq / ((SYSCON->SDIOCLKDIV & 0xffU) + 1U); -} - -/* Get FRO 12M Clk */ -/*! brief Return Frequency of FRO 12MHz - * return Frequency of FRO 12MHz - */ -uint32_t CLOCK_GetFro12MFreq(void) -{ - return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; -} - -/* Get FRO 1M Clk */ -/*! brief Return Frequency of FRO 1MHz - * return Frequency of FRO 1MHz - */ -uint32_t CLOCK_GetFro1MFreq(void) -{ - return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; -} - -/* Get EXT OSC Clk */ -/*! brief Return Frequency of External Clock - * return Frequency of External Clock. If no external clock is used returns 0. - */ -uint32_t CLOCK_GetExtClkFreq(void) -{ - return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; -} - -/* Get WATCH DOG Clk */ -/*! brief Return Frequency of Watchdog - * return Frequency of Watchdog - */ -uint32_t CLOCK_GetWdtClkFreq(void) -{ - return CLOCK_GetFro1MFreq() / ((SYSCON->WDTCLKDIV & SYSCON_WDTCLKDIV_DIV_MASK) + 1U); -} - -/* Get HF FRO Clk */ -/*! brief Return Frequency of High-Freq output of FRO - * return Frequency of High-Freq output of FRO - */ -uint32_t CLOCK_GetFroHfFreq(void) -{ - return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; -} - -/* Get SYSTEM PLL Clk */ -/*! brief Return Frequency of PLL - * return Frequency of PLL - */ -uint32_t CLOCK_GetPll0OutFreq(void) -{ - return s_Pll0_Freq; -} - -/* Get USB PLL Clk */ -/*! brief Return Frequency of USB PLL - * return Frequency of PLL - */ -uint32_t CLOCK_GetPll1OutFreq(void) -{ - return s_Pll1_Freq; -} - -/* Get RTC OSC Clk */ -/*! brief Return Frequency of 32kHz osc - * return Frequency of 32kHz osc - */ -uint32_t CLOCK_GetOsc32KFreq(void) -{ - return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && - (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? - CLK_RTC_32K_CLK : - ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && - (0UL != (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? - CLK_RTC_32K_CLK : - 0U; -} - -/* Get MAIN Clk */ -/*! brief Return Frequency of Core System - * return Frequency of Core System - */ -uint32_t CLOCK_GetCoreSysClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->MAINCLKSELB) - { - case 0U: - if (SYSCON->MAINCLKSELA == 0U) - { - freq = CLOCK_GetFro12MFreq(); - } - else if (SYSCON->MAINCLKSELA == 1U) - { - freq = CLOCK_GetExtClkFreq(); - } - else if (SYSCON->MAINCLKSELA == 2U) - { - freq = CLOCK_GetFro1MFreq(); - } - else if (SYSCON->MAINCLKSELA == 3U) - { - freq = CLOCK_GetFroHfFreq(); - } - else - { - /* Add comments to prevent the case of MISRA C-2012 rule 15.7. */ - } - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 2U: - freq = CLOCK_GetPll1OutFreq(); - break; - - case 3U: - freq = CLOCK_GetOsc32KFreq(); - break; - - default: - freq = 0U; - break; - } - - return freq; -} - -/* Get I2S MCLK Clk */ -/*! brief Return Frequency of I2S MCLK Clock - * return Frequency of I2S MCLK Clock - */ -uint32_t CLOCK_GetI2SMClkFreq(void) -{ - return s_I2S_Mclk_Freq; -} - -/* Get PLU CLKIN Clk */ -/*! brief Return Frequency of PLU CLKIN Clock - * return Frequency of PLU CLKIN Clock - */ -uint32_t CLOCK_GetPLUClkInFreq(void) -{ - return s_PLU_ClkIn_Freq; -} - -/* Get FLEXCOMM input clock */ -/*! brief Return Frequency of flexcomm input clock - * param id : flexcomm instance id - * return Frequency value - */ -uint32_t CLOCK_GetFlexCommInputClock(uint32_t id) -{ - uint32_t freq = 0U; - - switch (SYSCON->FCCLKSELX[id]) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U); - break; - case 2U: - freq = CLOCK_GetFro12MFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); - break; - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - case 5U: - freq = CLOCK_GetI2SMClkFreq(); - break; - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - assert(false); - break; - } - - return freq; -} - -/* Get FLEXCOMM Clk */ -uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) -{ - uint32_t freq = 0U; - uint32_t frgMul = 0U; - uint32_t frgDiv = 0U; - - freq = CLOCK_GetFlexCommInputClock(id); - frgMul = (SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_MULT_MASK) >> 8U; - frgDiv = SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_DIV_MASK; - return (uint32_t)(((uint64_t)freq * ((uint64_t)frgDiv + 1ULL)) / (frgMul + frgDiv + 1UL)); -} - -/* Get HS_LPSI Clk */ -uint32_t CLOCK_GetHsLspiClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->HSLSPICLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U); - break; - case 2U: - freq = CLOCK_GetFro12MFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); - break; - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - assert(false); - break; - } - - return freq; -} - -/* Get CTimer Clk */ -/*! brief Return Frequency of CTimer functional Clock - * return Frequency of CTimer functional Clock - */ -uint32_t CLOCK_GetCTimerClkFreq(uint32_t id) -{ - uint32_t freq = 0U; - - switch (SYSCON->CTIMERCLKSELX[id]) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - case 5U: - freq = CLOCK_GetI2SMClkFreq(); - break; - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - assert(false); - break; - } - - return freq; -} - -/* Get Systick Clk */ -/*! brief Return Frequency of SystickClock - * return Frequency of Systick Clock - */ -uint32_t CLOCK_GetSystickClkFreq(uint32_t id) -{ - volatile uint32_t *pSystickClkDiv; - pSystickClkDiv = &(SYSCON->SYSTICKCLKDIV0); - uint32_t freq = 0U; - - switch (SYSCON->SYSTICKCLKSELX[id]) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq() / ((((volatile uint32_t *)pSystickClkDiv)[(uint32_t)id] & 0xffU) + 1U); - break; - case 1U: - freq = CLOCK_GetFro1MFreq(); - break; - case 2U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq; -} - -/* Set FlexComm Clock */ -/** - * brief Set the flexcomm output frequency. - * param id : flexcomm instance id - * freq : output frequency - * return 0 : the frequency range is out of range. - * 1 : switch successfully. - */ -uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq) -{ - uint32_t input = CLOCK_GetFlexCommClkFreq(id); - uint32_t mul; - - if ((freq > 48000000UL) || (freq > input) || (input / freq >= 2UL)) - { - /* FRG output frequency should be less than equal to 48MHz */ - return 0UL; - } - else - { - mul = (uint32_t)((((uint64_t)input - freq) * 256ULL) / ((uint64_t)freq)); - SYSCON->FLEXFRGXCTRL[id] = (mul << 8U) | 0xFFU; - return 1UL; - } -} - -/* Get IP Clk */ -/*! brief Return Frequency of selected clock - * return Frequency of selected clock - */ -uint32_t CLOCK_GetFreq(clock_name_t clockName) -{ - uint32_t freq; - switch (clockName) - { - case kCLOCK_CoreSysClk: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case kCLOCK_BusClk: - freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); - break; - case kCLOCK_ClockOut: - freq = CLOCK_GetClockOutClkFreq(); - break; - case kCLOCK_Pll1Out: - freq = CLOCK_GetPll1OutFreq(); - break; - case kCLOCK_Mclk: - freq = CLOCK_GetMclkClkFreq(); - break; - case kCLOCK_FroHf: - freq = CLOCK_GetFroHfFreq(); - break; - case kCLOCK_Fro12M: - freq = CLOCK_GetFro12MFreq(); - break; - case kCLOCK_ExtClk: - freq = CLOCK_GetExtClkFreq(); - break; - case kCLOCK_Pll0Out: - freq = CLOCK_GetPll0OutFreq(); - break; - case kCLOCK_FlexI2S: - freq = CLOCK_GetI2SMClkFreq(); - break; - default: - freq = 0U; - break; - } - return freq; -} - -/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ -static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) -{ - uint32_t seli, selp; - /* bandwidth: compute selP from Multiplier */ - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ - { - selp = (M >> 2U) + 1U; - if (selp >= 31U) - { - selp = 31U; - } - *pSelP = selp; - - if (M >= 8000UL) - { - seli = 1UL; - } - else if (M >= 122UL) - { - seli = (uint32_t)(8000UL / M); /*floor(8000/M) */ - } - else - { - seli = 2UL * ((uint32_t)(M / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ - } - - if (seli >= 63UL) - { - seli = 63UL; - } - *pSelI = seli; - - *pSelR = 0U; - } - else - { - /* Note: If the spread spectrum mode, choose N to ensure 3 MHz < Fin/N < 5 MHz */ - *pSelP = 3U; - *pSelI = 4U; - *pSelR = 4U; - } -} - -/* Get predivider (N) from PLL0 NDEC setting */ -static uint32_t findPll0PreDiv(void) -{ - uint32_t preDiv = 1UL; - - /* Direct input is not used? */ - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) - { - preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; - if (preDiv == 0UL) - { - preDiv = 1UL; - } - } - return preDiv; -} - -/* Get predivider (N) from PLL1 NDEC setting */ -static uint32_t findPll1PreDiv(void) -{ - uint32_t preDiv = 1UL; - - /* Direct input is not used? */ - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) - { - preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; - if (preDiv == 0UL) - { - preDiv = 1UL; - } - } - return preDiv; -} - -/* Get postdivider (P) from PLL0 PDEC setting */ -static uint32_t findPll0PostDiv(void) -{ - uint32_t postDiv = 1UL; - - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) - { - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) - { - postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; - } - else - { - postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); - } - if (postDiv == 0UL) - { - postDiv = 2UL; - } - } - return postDiv; -} - -/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ -static float findPll0MMult(void) -{ - float mMult = 1.0F; - float mMult_fract; - uint32_t mMult_int; - - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) - { - mMult = - (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); - } - else - { - mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); - mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL0_SSCG_MD_INT_P); - mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL0_SSCG_MD_FRACT_M) / - (float)(uint32_t)(1UL << PLL0_SSCG_MD_INT_P)); - mMult = (float)mMult_int + mMult_fract; - } - if(0ULL == ((uint64_t)mMult)) - { - mMult = 1.0F; - } - return mMult; -} - -/* Find greatest common divisor between m and n */ -static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) -{ - uint32_t tmp; - - while (n != 0U) - { - tmp = n; - n = m % n; - m = tmp; - } - - return m; -} - -/* - * Set PLL0 output based on desired output rate. - * In this function, the it calculates the PLL0 setting for output frequency from input clock - * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. - * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. - */ -static pll_error_t CLOCK_GetPll0ConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) -{ - uint32_t nDivOutHz, fccoHz; - uint32_t pllPreDivider, pllMultiplier, pllPostDivider; - uint32_t pllDirectInput, pllDirectOutput; - uint32_t pllSelP, pllSelI, pllSelR, uplimoff; - - /* Baseline parameters (no input or output dividers) */ - pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ - pllPostDivider = 1U; /* 1 implies post-divider will be disabled */ - pllDirectOutput = 1U; - - /* Verify output rate parameter */ - if (foutHz > PLL_MAX_CCO_FREQ_MHZ) - { - /* Maximum PLL output with post divider=1 cannot go above this frequency */ - return kStatus_PLL_OutputTooHigh; - } - if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) - { - /* Minmum PLL output with maximum post divider cannot go below this frequency */ - return kStatus_PLL_OutputTooLow; - } - - /* If using SS mode, input clock needs to be between 3MHz and 20MHz */ - if (useSS) - { - /* Verify input rate parameter */ - if (finHz < PLL_MIN_IN_SSMODE) - { - /* Input clock into the PLL cannot be lower than this */ - return kStatus_PLL_InputTooLow; - } - /* PLL input in SS mode must be under 20MHz */ - if (finHz > (PLL_MAX_IN_SSMODE * NVALMAX)) - { - return kStatus_PLL_InputTooHigh; - } - } - else - { - /* Verify input rate parameter */ - if (finHz < PLL_LOWER_IN_LIMIT) - { - /* Input clock into the PLL cannot be lower than this */ - return kStatus_PLL_InputTooLow; - } - if (finHz > PLL_HIGHER_IN_LIMIT) - { - /* Input clock into the PLL cannot be higher than this */ - return kStatus_PLL_InputTooHigh; - } - } - - /* Find the optimal CCO frequency for the output and input that - will keep it inside the PLL CCO range. This may require - tweaking the post-divider for the PLL. */ - fccoHz = foutHz; - while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) - { - /* CCO output is less than minimum CCO range, so the CCO output - needs to be bumped up and the post-divider is used to bring - the PLL output back down. */ - pllPostDivider++; - if (pllPostDivider > PVALMAX) - { - return kStatus_PLL_OutsideIntLimit; - } - - /* Target CCO goes up, PLL output goes down */ - /* divide-by-2 divider in the post-divider is always work*/ - fccoHz = foutHz * (pllPostDivider * 2U); - pllDirectOutput = 0U; - } - - /* Determine if a pre-divider is needed to get the best frequency */ - if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) - { - uint32_t a = FindGreatestCommonDivisor(fccoHz, finHz); - - if (a > PLL_LOWER_IN_LIMIT) - { - a = finHz / a; - if ((a != 0U) && (a < PLL_MAX_N_DIV)) - { - pllPreDivider = a; - } - } - } - - /* Bypass pre-divider hardware if pre-divider is 1 */ - if (pllPreDivider > 1U) - { - pllDirectInput = 0U; - } - else - { - pllDirectInput = 1U; - } - - /* Determine PLL multipler */ - nDivOutHz = (finHz / pllPreDivider); - pllMultiplier = (fccoHz / nDivOutHz); - - /* Find optimal values for filter */ - if (useSS == false) - { - /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ - if ((nDivOutHz * ((pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) - { - pllMultiplier++; - } - - /* Setup filtering */ - pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR); - uplimoff = 0U; - - /* Get encoded value for M (mult) and use manual filter, disable SS mode */ - pSetup->pllsscg[1] = - (uint32_t)((PLL_SSCG1_MDEC_VAL_SET(pllMultiplier)) | (1UL << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)); - } - else - { - uint64_t fc; - - /* Filtering will be handled by SSC */ - pllSelR = 0U; - pllSelI = 0U; - pllSelP = 0U; - uplimoff = 1U; - - /* The PLL multiplier will get very close and slightly under the - desired target frequency. A small fractional component can be - added to fine tune the frequency upwards to the target. */ - fc = (((uint64_t)fccoHz % (uint64_t)nDivOutHz) << 25U) / nDivOutHz; - - /* Set multiplier */ - pSetup->pllsscg[0] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) | PLL0_SSCG_MD_FRACT_SET((uint32_t)fc)); - pSetup->pllsscg[1] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) >> 32U); - } - - /* Get encoded values for N (prediv) and P (postdiv) */ - pSetup->pllndec = PLL_NDEC_VAL_SET(pllPreDivider); - pSetup->pllpdec = PLL_PDEC_VAL_SET(pllPostDivider); - - /* PLL control */ - pSetup->pllctrl = (pllSelR << SYSCON_PLL0CTRL_SELR_SHIFT) | /* Filter coefficient */ - (pllSelI << SYSCON_PLL0CTRL_SELI_SHIFT) | /* Filter coefficient */ - (pllSelP << SYSCON_PLL0CTRL_SELP_SHIFT) | /* Filter coefficient */ - (0UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT) | /* PLL bypass mode disabled */ - (uplimoff << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */ - (pllDirectInput << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */ - (pllDirectOutput << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT) | /* Bypass post-divider? */ - (1UL << SYSCON_PLL0CTRL_CLKEN_SHIFT); /* Ensure the PLL clock output */ - - return kStatus_PLL_Success; -} - -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) -/* Alloct the static buffer for cache. */ -static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; -static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; -static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; -static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; -static uint32_t s_PllSetupCacheIdx = 0U; -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - -/* - * Calculate the PLL setting values from input clock freq to output freq. - */ -static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) -{ - pll_error_t retErr; -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - uint32_t i; - - for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) - { - if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && (useSS == s_UseSSCache[i])) - { - /* Hit the target in cache buffer. */ - pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl; - pSetup->pllndec = s_PllSetupCacheStruct[i].pllndec; - pSetup->pllpdec = s_PllSetupCacheStruct[i].pllpdec; - pSetup->pllsscg[0] = s_PllSetupCacheStruct[i].pllsscg[0]; - pSetup->pllsscg[1] = s_PllSetupCacheStruct[i].pllsscg[1]; - retErr = kStatus_PLL_Success; - break; - } - } - - if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - { - return retErr; - } -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - - retErr = CLOCK_GetPll0ConfigInternal(finHz, foutHz, pSetup, useSS); - -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - /* Cache the most recent calulation result into buffer. */ - s_FinHzCache[s_PllSetupCacheIdx] = finHz; - s_FoutHzCache[s_PllSetupCacheIdx] = foutHz; - s_UseSSCache[s_PllSetupCacheIdx] = useSS; - - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndec = pSetup->pllndec; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdec = pSetup->pllpdec; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[0] = pSetup->pllsscg[0]; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[1] = pSetup->pllsscg[1]; - /* Update the index for next available buffer. */ - s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - - return retErr; -} - -/* Update local PLL rate variable */ -static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup) -{ - s_Pll0_Freq = CLOCK_GetPLL0OutFromSetup(pSetup); -} - -/* Return System PLL input clock rate */ -/*! brief Return PLL0 input clock rate - * return PLL0 input clock rate - */ -uint32_t CLOCK_GetPLL0InClockRate(void) -{ - uint32_t clkRate = 0U; - - switch ((SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK)) - { - case 0x00U: - clkRate = CLK_FRO_12MHZ; - break; - - case 0x01U: - clkRate = CLOCK_GetExtClkFreq(); - break; - - case 0x02U: - clkRate = CLOCK_GetFro1MFreq(); - break; - - case 0x03U: - clkRate = CLOCK_GetOsc32KFreq(); - break; - - default: - clkRate = 0U; - break; - } - - return clkRate; -} - -/* Return PLL1 input clock rate */ -uint32_t CLOCK_GetPLL1InClockRate(void) -{ - uint32_t clkRate = 0U; - - switch ((SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK)) - { - case 0x00U: - clkRate = CLK_FRO_12MHZ; - break; - - case 0x01U: - clkRate = CLOCK_GetExtClkFreq(); - break; - - case 0x02U: - clkRate = CLOCK_GetFro1MFreq(); - break; - - case 0x03U: - clkRate = CLOCK_GetOsc32KFreq(); - break; - - default: - clkRate = 0U; - break; - } - - return clkRate; -} - -/* Return PLL0 output clock rate from setup structure */ -/*! brief Return PLL0 output clock rate from setup structure - * param pSetup : Pointer to a PLL setup structure - * return PLL0 output clock rate the setup structure will generate - */ -uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup) -{ - uint32_t clkRate = 0; - uint32_t prediv, postdiv; - float workRate = 0.0F; - - /* Get the input clock frequency of PLL. */ - clkRate = CLOCK_GetPLL0InClockRate(); - - if (((pSetup->pllctrl & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && - ((pSetup->pllctrl & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && - ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && - ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) - { - prediv = findPll0PreDiv(); - postdiv = findPll0PostDiv(); - /* Adjust input clock */ - clkRate = clkRate / prediv; - /* MDEC used for rate */ - workRate = (float)clkRate * (float)findPll0MMult(); - workRate /= (float)postdiv; - } - - return (uint32_t)workRate; -} - -/* Set the current PLL0 Rate */ -/*! brief Store the current PLL rate - * param rate: Current rate of the PLL - * return Nothing - **/ -void CLOCK_SetStoredPLL0ClockRate(uint32_t rate) -{ - s_Pll0_Freq = rate; -} - -/* Return PLL0 output clock rate */ -/*! brief Return PLL0 output clock rate - * param recompute : Forces a PLL rate recomputation if true - * return PLL0 output clock rate - * note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetPLL0OutClockRate(bool recompute) -{ - pll_setup_t Setup; - uint32_t rate; - - if ((recompute) || (s_Pll0_Freq == 0U)) - { - Setup.pllctrl = SYSCON->PLL0CTRL; - Setup.pllndec = SYSCON->PLL0NDEC; - Setup.pllpdec = SYSCON->PLL0PDEC; - Setup.pllsscg[0] = SYSCON->PLL0SSCG0; - Setup.pllsscg[1] = SYSCON->PLL0SSCG1; - - CLOCK_GetPLL0OutFromSetupUpdate(&Setup); - } - - rate = s_Pll0_Freq; - - return rate; -} - -/* Set PLL0 output based on the passed PLL setup data */ -/*! brief Set PLL output based on the passed PLL setup data - * param pControl : Pointer to populated PLL control structure to generate setup with - * param pSetup : Pointer to PLL setup structure to be filled - * return PLL_ERROR_SUCCESS on success, or PLL setup error code - * note Actual frequency for setup may vary from the desired frequency based on the - * accuracy of input clocks, rounding, non-fractional PLL mode, etc. - */ -pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup) -{ - uint32_t inRate; - bool useSS = ((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0U); - - pll_error_t pllError; - - /* Determine input rate for the PLL */ - if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U) - { - inRate = pControl->inputRate; - } - else - { - inRate = CLOCK_GetPLL0InClockRate(); - } - - /* PLL flag options */ - pllError = CLOCK_GetPll0Config(inRate, pControl->desiredRate, pSetup, useSS); - if ((useSS) && (pllError == kStatus_PLL_Success)) - { - /* If using SS mode, then some tweaks are made to the generated setup */ - pSetup->pllsscg[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc; - if (pControl->mfDither) - { - pSetup->pllsscg[1] |= (1UL << SYSCON_PLL0SSCG1_DITHER_SHIFT); - } - } - - return pllError; -} - -/* Set PLL0 output from PLL setup structure */ -/*! brief Set PLL output from PLL setup structure (precise frequency) - * param pSetup : Pointer to populated PLL setup structure - * param flagcfg : Flag configuration for PLL config structure - * return PLL_ERROR_SUCCESS on success, or PLL setup error code - * note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg) -{ - uint32_t inRate, clkRate, prediv; - - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_PLL0); - POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); - - pSetup->flags = flagcfg; - - /* Write PLL setup data */ - SYSCON->PLL0CTRL = pSetup->pllctrl; - SYSCON->PLL0NDEC = pSetup->pllndec; - SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ - SYSCON->PLL0PDEC = pSetup->pllpdec; - SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ - SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; - SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; - SYSCON->PLL0SSCG1 = - pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT); /* latch */ - - POWER_DisablePD(kPDRUNCFG_PD_PLL0); - POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); - - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) - { - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ - { - inRate = CLOCK_GetPLL0InClockRate(); - prediv = findPll0PreDiv(); - /* Adjust input clock */ - clkRate = inRate / prediv; - /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ - if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) - { - while (CLOCK_IsPLL0Locked() == false) - { - } - } - else - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval - to insure the PLL will be stable */ - } - } - else /* spread spectrum mode */ - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to - insure the PLL will be stable */ - } - } - - /* Update current programmed PLL rate var */ - CLOCK_GetPLL0OutFromSetupUpdate(pSetup); - - /* System voltage adjustment, occurs prior to setting main system clock */ - if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U) - { - POWER_SetVoltageForFreq(s_Pll0_Freq); - } - - return kStatus_PLL_Success; -} - -/* Setup PLL Frequency from pre-calculated value */ -/** - * brief Set PLL0 output from PLL setup structure (precise frequency) - * param pSetup : Pointer to populated PLL setup structure - * return kStatus_PLL_Success on success, or PLL setup error code - * note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup) -{ - uint32_t inRate, clkRate, prediv; - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_PLL0); - POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); - - /* Write PLL setup data */ - SYSCON->PLL0CTRL = pSetup->pllctrl; - SYSCON->PLL0NDEC = pSetup->pllndec; - SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ - SYSCON->PLL0PDEC = pSetup->pllpdec; - SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ - SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; - SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; - SYSCON->PLL0SSCG1 = - pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* latch */ - - POWER_DisablePD(kPDRUNCFG_PD_PLL0); - POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); - - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) - { - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ - { - inRate = CLOCK_GetPLL0InClockRate(); - prediv = findPll0PreDiv(); - /* Adjust input clock */ - clkRate = inRate / prediv; - /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ - if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) - { - while (CLOCK_IsPLL0Locked() == false) - { - } - } - else - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval - to insure the PLL will be stable */ - } - } - else /* spread spectrum mode */ - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to - insure the PLL will be stable */ - } - } - - /* Update current programmed PLL rate var */ - s_Pll0_Freq = pSetup->pllRate; - - return kStatus_PLL_Success; -} - -/* Setup PLL1 Frequency from pre-calculated value */ -/** - * brief Set PLL1 output from PLL setup structure (precise frequency) - * param pSetup : Pointer to populated PLL setup structure - * return kStatus_PLL_Success on success, or PLL setup error code - * note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup) -{ - uint32_t inRate, clkRate, prediv; - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_PLL1); - - /* Write PLL setup data */ - SYSCON->PLL1CTRL = pSetup->pllctrl; - SYSCON->PLL1NDEC = pSetup->pllndec; - SYSCON->PLL1NDEC = pSetup->pllndec | (1UL << SYSCON_PLL1NDEC_NREQ_SHIFT); /* latch */ - SYSCON->PLL1PDEC = pSetup->pllpdec; - SYSCON->PLL1PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL1PDEC_PREQ_SHIFT); /* latch */ - SYSCON->PLL1MDEC = pSetup->pllmdec; - SYSCON->PLL1MDEC = pSetup->pllmdec | (1UL << SYSCON_PLL1MDEC_MREQ_SHIFT); /* latch */ - - POWER_DisablePD(kPDRUNCFG_PD_PLL1); - - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) - { - inRate = CLOCK_GetPLL1InClockRate(); - prediv = findPll1PreDiv(); - /* Adjust input clock */ - clkRate = inRate / prediv; - /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ - if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) - { - while (CLOCK_IsPLL1Locked() == false) - { - } - } - else - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to - insure the PLL will be stable */ - } - } - - /* Update current programmed PLL rate var */ - s_Pll1_Freq = pSetup->pllRate; - - return kStatus_PLL_Success; -} - -/* Set PLL0 clock based on the input frequency and multiplier */ -/*! brief Set PLL0 output based on the multiplier and input frequency - * param multiply_by : multiplier - * param input_freq : Clock input frequency of the PLL - * return Nothing - * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this - * function does not disable or enable PLL power, wait for PLL lock, - * or adjust system voltages. These must be done in the application. - * The function will not alter any source clocks (ie, main systen clock) - * that may use the PLL, so these should be setup prior to and after - * exiting the function. - */ -void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq) -{ - uint32_t cco_freq = input_freq * multiply_by; - uint32_t pdec = 1U; - uint32_t selr; - uint32_t seli; - uint32_t selp; - uint32_t mdec, ndec; - - while (cco_freq < 275000000U) - { - multiply_by <<= 1U; /* double value in each iteration */ - pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */ - cco_freq = input_freq * multiply_by; - } - - selr = 0U; - - if (multiply_by >= 8000UL) - { - seli = 1UL; - } - else if (multiply_by >= 122UL) - { - seli = (uint32_t)(8000UL / multiply_by); /*floor(8000/M) */ - } - else - { - seli = 2UL * ((uint32_t)(multiply_by / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ - } - - if (seli >= 63U) - { - seli = 63U; - } - - { - selp = 31U; - } - - if (pdec > 1U) - { - pdec = pdec / 2U; /* Account for minus 1 encoding */ - /* Translate P value */ - } - - mdec = (uint32_t)PLL_SSCG1_MDEC_VAL_SET(multiply_by); - ndec = 0x1U; /* pre divide by 1 (hardcoded) */ - - SYSCON->PLL0CTRL = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_BYPASSPOSTDIV(0) | - SYSCON_PLL0CTRL_BYPASSPOSTDIV2(0) | (selr << SYSCON_PLL0CTRL_SELR_SHIFT) | - (seli << SYSCON_PLL0CTRL_SELI_SHIFT) | (selp << SYSCON_PLL0CTRL_SELP_SHIFT); - SYSCON->PLL0PDEC = pdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* set Pdec value and assert preq */ - SYSCON->PLL0NDEC = ndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* set Pdec value and assert preq */ - SYSCON->PLL0SSCG1 = - mdec | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* select non sscg MDEC value, assert mreq and select mdec value */ -} - -/* Enable USB DEVICE FULL SPEED clock */ -/*! brief Enable USB Device FS clock. - * param src : clock source - * param freq: clock frequency - * Enable USB Device Full Speed clock. - */ -bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq) -{ - bool ret = true; - - CLOCK_DisableClock(kCLOCK_Usbd0); - - if (kCLOCK_UsbfsSrcFro == src) - { - switch (freq) - { - case 96000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ - break; - - default: - ret = false; - break; - } - /* Turn ON FRO HF */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); - /* Enable FRO 96MHz output */ - ANACTRL->FRO192M_CTRL = - ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK | ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK; - /* Select FRO 96 or 48 MHz */ - CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); - } - else - { - /*!< Configure XTAL32M */ - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ - (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ - - /*!< Set up PLL1 */ - POWER_DisablePD(kPDRUNCFG_PD_PLL1); - CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ - const pll_setup_t pll1Setup = { - .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U), - .pllndec = SYSCON_PLL1NDEC_NDIV(1U), - .pllpdec = SYSCON_PLL1PDEC_PDIV(5U), - .pllmdec = SYSCON_PLL1MDEC_MDIV(30U), - .pllRate = 48000000U, - .flags = PLL_SETUPFLAG_WAITLOCK}; - (void)CLOCK_SetPLL1Freq(&pll1Setup); - - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); - CLOCK_AttachClk(kPLL1_to_USB0_CLK); - SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - } - CLOCK_EnableClock(kCLOCK_Usbd0); - CLOCK_EnableClock(kCLOCK_UsbRam1); - - return ret; -} - -/* Enable USB HOST FULL SPEED clock */ -/*! brief Enable USB HOST FS clock. - * param src : clock source - * param freq: clock frequency - * Enable USB HOST Full Speed clock. - */ -bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq) -{ - bool ret = true; - - CLOCK_DisableClock(kCLOCK_Usbhmr0); - CLOCK_DisableClock(kCLOCK_Usbhsl0); - - if (kCLOCK_UsbfsSrcFro == src) - { - switch (freq) - { - case 96000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ - break; - - default: - ret = false; - break; - } - /* Turn ON FRO HF */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); - /* Enable FRO 96MHz output */ - ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; - /* Select FRO 96 MHz */ - CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); - } - else - { - /*!< Configure XTAL32M */ - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ - (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ - - /*!< Set up PLL1 */ - POWER_DisablePD(kPDRUNCFG_PD_PLL1); - CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ - const pll_setup_t pll1Setup = { - .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U), - .pllndec = SYSCON_PLL1NDEC_NDIV(1U), - .pllpdec = SYSCON_PLL1PDEC_PDIV(5U), - .pllmdec = SYSCON_PLL1MDEC_MDIV(30U), - .pllRate = 48000000U, - .flags = PLL_SETUPFLAG_WAITLOCK}; - (void)CLOCK_SetPLL1Freq(&pll1Setup); - - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); - CLOCK_AttachClk(kPLL1_to_USB0_CLK); - SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - } - CLOCK_EnableClock(kCLOCK_Usbhmr0); - CLOCK_EnableClock(kCLOCK_Usbhsl0); - CLOCK_EnableClock(kCLOCK_UsbRam1); - - return ret; -} - -/* Enable USB PHY clock */ -bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) -{ - volatile uint32_t i; - uint32_t phyPllDiv = 0U; - uint16_t multiplier = 0U; - bool ret = true; - - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); - POWER_DisablePD(kPDRUNCFG_PD_FRO32K); /*!< Ensure FRO32k is on */ - POWER_DisablePD(kPDRUNCFG_PD_XTAL32K); /*!< Ensure xtal32k is on */ - POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /*!< Ensure xtal32k is on */ - POWER_DisablePD(kPDRUNCFG_PD_LDOUSBHS); /*!< Ensure xtal32k is on */ - - /* wait to make sure PHY power is fully up */ - i = 100000U; - while ((i--) != 0U) - { - __ASM("nop"); - } - - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL(1); - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_PHY(1); - - USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; - - multiplier = (uint16_t)(480000000UL / freq); - - switch (multiplier) - { - case 15U: - { - phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(0U); - break; - } - case 16U: - { - phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(1U); - break; - } - case 20U: - { - phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(2U); - break; - } - case 24U: - { - phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(4U); - break; - } - case 25U: - { - phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(5U); - break; - } - case 30U: - { - phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(6U); - break; - } - case 40U: - { - phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(7U); - break; - } - default: - { - ret = false; - break; - } - } - - if (ret) - { - USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | phyPllDiv; - USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK; - USBPHY->PLL_SIC_CLR = (1UL << 16U); // Reserved. User must set this bit to 0x0 - USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_POWER_MASK; - USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK; - - USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; - USBPHY->PWD_SET = 0x0; - } - - return ret; -} - -/* Enable USB DEVICE HIGH SPEED clock */ -bool CLOCK_EnableUsbhs0DeviceClock(clock_usbhs_src_t src, uint32_t freq) -{ - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1); - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_DEV(1); - - /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1); - return true; -} - -/* Enable USB HOST HIGH SPEED clock */ -bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq) -{ - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1); - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_HOST(1); - - /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1); - - return true; -} - -/*! @brief Enable the OSTIMER 32k clock. - * @return Nothing - */ -void CLOCK_EnableOstimer32kClock(void) -{ - PMC->OSTIMERr |= PMC_OSTIMER_CLOCKENABLE_MASK; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_clock.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_clock.h deleted file mode 100644 index f7e60559cef..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_clock.h +++ /dev/null @@ -1,1506 +0,0 @@ -/* - * Copyright 2017 - 2021, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CLOCK_H_ -#define _FSL_CLOCK_H_ - -#include "fsl_common.h" - -/*! @addtogroup clock */ -/*! @{ */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CLOCK driver version 2.3.6. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 6)) -/*@}*/ - -/*! @brief Configure whether driver controls clock - * - * When set to 0, peripheral drivers will enable clock in initialize function - * and disable clock in de-initialize function. When set to 1, peripheral - * driver will not control the clock, application could control the clock out of - * the driver. - * - * @note All drivers share this feature switcher. If it is set to 1, application - * should handle clock enable and disable for all drivers. - */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) -#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 -#endif - -/*! - * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. - * - * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function - * would cache the recent calulation and accelerate the execution to get the - * right settings. - */ -#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT -#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U -#endif - -/* Definition for delay API in clock driver, users can redefine it to the real application. */ -#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY -#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (150000000UL) -#endif - -/*! @brief Clock ip name array for ROM. */ -#define ROM_CLOCKS \ - { \ - kCLOCK_Rom \ - } -/*! @brief Clock ip name array for SRAM. */ -#define SRAM_CLOCKS \ - { \ - kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3, kCLOCK_Sram4 \ - } -/*! @brief Clock ip name array for FLASH. */ -#define FLASH_CLOCKS \ - { \ - kCLOCK_Flash \ - } -/*! @brief Clock ip name array for FMC. */ -#define FMC_CLOCKS \ - { \ - kCLOCK_Fmc \ - } -/*! @brief Clock ip name array for INPUTMUX. */ -#define INPUTMUX_CLOCKS \ - { \ - kCLOCK_InputMux0 \ - } -/*! @brief Clock ip name array for IOCON. */ -#define IOCON_CLOCKS \ - { \ - kCLOCK_Iocon \ - } -/*! @brief Clock ip name array for GPIO. */ -#define GPIO_CLOCKS \ - { \ - kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3 \ - } -/*! @brief Clock ip name array for PINT. */ -#define PINT_CLOCKS \ - { \ - kCLOCK_Pint \ - } -/*! @brief Clock ip name array for GINT. */ -#define GINT_CLOCKS \ - { \ - kCLOCK_Gint, kCLOCK_Gint \ - } -/*! @brief Clock ip name array for DMA. */ -#define DMA_CLOCKS \ - { \ - kCLOCK_Dma0, kCLOCK_Dma1 \ - } -/*! @brief Clock ip name array for CRC. */ -#define CRC_CLOCKS \ - { \ - kCLOCK_Crc \ - } -/*! @brief Clock ip name array for WWDT. */ -#define WWDT_CLOCKS \ - { \ - kCLOCK_Wwdt \ - } -/*! @brief Clock ip name array for RTC. */ -#define RTC_CLOCKS \ - { \ - kCLOCK_Rtc \ - } -/*! @brief Clock ip name array for Mailbox. */ -#define MAILBOX_CLOCKS \ - { \ - kCLOCK_Mailbox \ - } -/*! @brief Clock ip name array for LPADC. */ -#define LPADC_CLOCKS \ - { \ - kCLOCK_Adc0 \ - } -/*! @brief Clock ip name array for MRT. */ -#define MRT_CLOCKS \ - { \ - kCLOCK_Mrt \ - } -/*! @brief Clock ip name array for OSTIMER. */ -#define OSTIMER_CLOCKS \ - { \ - kCLOCK_OsTimer0 \ - } -/*! @brief Clock ip name array for SCT0. */ -#define SCT_CLOCKS \ - { \ - kCLOCK_Sct0 \ - } -/*! @brief Clock ip name array for UTICK. */ -#define UTICK_CLOCKS \ - { \ - kCLOCK_Utick0 \ - } -/*! @brief Clock ip name array for FLEXCOMM. */ -#define FLEXCOMM_CLOCKS \ - { \ - kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \ - kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi \ - } -/*! @brief Clock ip name array for LPUART. */ -#define LPUART_CLOCKS \ - { \ - kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \ - kCLOCK_MinUart6, kCLOCK_MinUart7 \ - } - -/*! @brief Clock ip name array for BI2C. */ -#define BI2C_CLOCKS \ - { \ - kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \ - } -/*! @brief Clock ip name array for LSPI. */ -#define LPSPI_CLOCKS \ - { \ - kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \ - } -/*! @brief Clock ip name array for FLEXI2S. */ -#define FLEXI2S_CLOCKS \ - { \ - kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \ - kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \ - } -/*! @brief Clock ip name array for CTIMER. */ -#define CTIMER_CLOCKS \ - { \ - kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ - } -/*! @brief Clock ip name array for COMP */ -#define COMP_CLOCKS \ - { \ - kCLOCK_Comp \ - } -/*! @brief Clock ip name array for SDIO. */ -#define SDIO_CLOCKS \ - { \ - kCLOCK_Sdio \ - } -/*! @brief Clock ip name array for USB1CLK. */ -#define USB1CLK_CLOCKS \ - { \ - kCLOCK_Usb1Clk \ - } -/*! @brief Clock ip name array for FREQME. */ -#define FREQME_CLOCKS \ - { \ - kCLOCK_Freqme \ - } -/*! @brief Clock ip name array for USBRAM. */ -#define USBRAM_CLOCKS \ - { \ - kCLOCK_UsbRam1 \ - } -/*! @brief Clock ip name array for RNG. */ -#define RNG_CLOCKS \ - { \ - kCLOCK_Rng \ - } -/*! @brief Clock ip name array for USBHMR0. */ -#define USBHMR0_CLOCKS \ - { \ - kCLOCK_Usbhmr0 \ - } -/*! @brief Clock ip name array for USBHSL0. */ -#define USBHSL0_CLOCKS \ - { \ - kCLOCK_Usbhsl0 \ - } -/*! @brief Clock ip name array for HashCrypt. */ -#define HASHCRYPT_CLOCKS \ - { \ - kCLOCK_HashCrypt \ - } -/*! @brief Clock ip name array for PowerQuad. */ -#define POWERQUAD_CLOCKS \ - { \ - kCLOCK_PowerQuad \ - } -/*! @brief Clock ip name array for PLULUT. */ -#define PLULUT_CLOCKS \ - { \ - kCLOCK_PluLut \ - } -/*! @brief Clock ip name array for PUF. */ -#define PUF_CLOCKS \ - { \ - kCLOCK_Puf \ - } -/*! @brief Clock ip name array for CASPER. */ -#define CASPER_CLOCKS \ - { \ - kCLOCK_Casper \ - } -/*! @brief Clock ip name array for ANALOGCTRL. */ -#define ANALOGCTRL_CLOCKS \ - { \ - kCLOCK_AnalogCtrl \ - } -/*! @brief Clock ip name array for HS_LSPI. */ -#define HS_LSPI_CLOCKS \ - { \ - kCLOCK_Hs_Lspi \ - } -/*! @brief Clock ip name array for GPIO_SEC. */ -#define GPIO_SEC_CLOCKS \ - { \ - kCLOCK_Gpio_Sec \ - } -/*! @brief Clock ip name array for GPIO_SEC_INT. */ -#define GPIO_SEC_INT_CLOCKS \ - { \ - kCLOCK_Gpio_Sec_Int \ - } -/*! @brief Clock ip name array for USBD. */ -#define USBD_CLOCKS \ - { \ - kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \ - } -/*! @brief Clock ip name array for USBH. */ -#define USBH_CLOCKS \ - { \ - kCLOCK_Usbh1 \ - } -#define PLU_CLOCKS \ - { \ - kCLOCK_PluLut \ - } -#define SYSCTL_CLOCKS \ - { \ - kCLOCK_Sysctl \ - } -/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ -/*------------------------------------------------------------------------------ - clock_ip_name_t definition: -------------------------------------------------------------------------------*/ - -#define CLK_GATE_REG_OFFSET_SHIFT 8U -#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U -#define CLK_GATE_BIT_SHIFT_SHIFT 0U -#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU - -#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ - ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ - (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) - -#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) -#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) - -#define AHB_CLK_CTRL0 0 -#define AHB_CLK_CTRL1 1 -#define AHB_CLK_CTRL2 2 - -/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ -typedef enum _clock_ip_name -{ - kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */ - kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /*!< Clock gate name: Rom. */ - - kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /*!< Clock gate name: Sram1. */ - - kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /*!< Clock gate name: Sram2. */ - - kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /*!< Clock gate name: Sram3. */ - - kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), /*!< Clock gate name: Sram4. */ - - kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /*!< Clock gate name: Flash. */ - - kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /*!< Clock gate name: Fmc. */ - - kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /*!< Clock gate name: InputMux. */ - - kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Iocon. */ - - kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Gpio0. */ - - kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Gpio1. */ - - kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), /*!< Clock gate name: Gpio2. */ - - kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), /*!< Clock gate name: Gpio3. */ - - kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), /*!< Clock gate name: Pint. */ - - kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gint. */ - - kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Dma0. */ - - kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Crc. */ - - kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Wwdt. */ - - kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Rtc. */ - - kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), /*!< Clock gate name: Mailbox. */ - - kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), /*!< Clock gate name: Adc0. */ - - kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), /*!< Clock gate name: Mrt. */ - - kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), /*!< Clock gate name: OsTimer0. */ - - kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), /*!< Clock gate name: Sct0. */ - - kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), /*!< Clock gate name: Utick0. */ - - kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexComm0. */ - - kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexComm1. */ - - kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexComm2. */ - - kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexComm3. */ - - kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexComm4. */ - - kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexComm5. */ - - kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexComm6. */ - - kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexComm7. */ - - kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: MinUart0. */ - - kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: MinUart1. */ - - kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: MinUart2. */ - - kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: MinUart3. */ - - kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: MinUart4. */ - - kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: MinUart5. */ - - kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: MinUart6. */ - - kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: MinUart7. */ - - kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LSpi0. */ - - kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LSpi1. */ - - kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LSpi2. */ - - kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LSpi3. */ - - kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LSpi4. */ - - kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LSpi5. */ - - kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LSpi6. */ - - kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LSpi7. */ - - kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: BI2c0. */ - - kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: BI2c1. */ - - kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: BI2c2. */ - - kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: BI2c3. */ - - kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: BI2c4. */ - - kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: BI2c5. */ - - kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: BI2c6. */ - - kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: BI2c7. */ - - kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexI2s0. */ - - kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexI2s1. */ - - kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexI2s2. */ - - kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexI2s3. */ - - kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexI2s4. */ - - kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexI2s5. */ - - kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexI2s6. */ - - kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexI2s7. */ - - kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), /*!< Clock gate name: Timer2. */ - - kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), /*!< Clock gate name: Usbd0. */ - - kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), /*!< Clock gate name: Timer0. */ - - kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), /*!< Clock gate name: Timer1. */ - - kCLOCK_Pvt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28), /*!< Clock gate name: Pvt. */ - - kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30), /*!< Clock gate name: Ezha. */ - - kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), /*!< Clock gate name: Ezhb. */ - - kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), /*!< Clock gate name: Dma1. */ - - kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), /*!< Clock gate name: Comp. */ - - kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3), /*!< Clock gate name: Sdio. */ - - kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), /*!< Clock gate name: Usbh1. */ - - kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), /*!< Clock gate name: Usbd1. */ - - kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), /*!< Clock gate name: UsbRam1. */ - - kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), /*!< Clock gate name: Usb1Clk. */ - - kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), /*!< Clock gate name: Freqme. */ - - kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), /*!< Clock gate name: Rng. */ - - kCLOCK_InputMux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: InputMux1. */ - - kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: Sysctl. */ - - kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), /*!< Clock gate name: Usbhmr0. */ - - kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), /*!< Clock gate name: Usbhsl0. */ - - kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), /*!< Clock gate name: HashCrypt. */ - - kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19), /*!< Clock gate name: PowerQuad. */ - - kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), /*!< Clock gate name: PluLut. */ - - kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), /*!< Clock gate name: Timer3. */ - - kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), /*!< Clock gate name: Timer4. */ - - kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), /*!< Clock gate name: Puf. */ - - kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), /*!< Clock gate name: Casper. */ - - kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27), /*!< Clock gate name: AnalogCtrl. */ - - kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28), /*!< Clock gate name: Lspi. */ - - kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), /*!< Clock gate name: GPIO Sec. */ - - kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30) /*!< Clock gate name: GPIO SEC Int. */ -} clock_ip_name_t; - -/*! @brief Peripherals clock source definition. */ -#define BUS_CLK kCLOCK_BusClk - -#define I2C0_CLK_SRC BUS_CLK - -/*! @brief Clock name used to get clock frequency. */ -typedef enum _clock_name -{ - kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ - kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ - kCLOCK_ClockOut, /*!< CLOCKOUT */ - kCLOCK_FroHf, /*!< FRO48/96 */ - kCLOCK_Pll1Out, /*!< PLL1 Output */ - kCLOCK_Mclk, /*!< MCLK */ - kCLOCK_Fro12M, /*!< FRO12M */ - kCLOCK_ExtClk, /*!< External Clock */ - kCLOCK_Pll0Out, /*!< PLL0 Output */ - kCLOCK_FlexI2S, /*!< FlexI2S clock */ - -} clock_name_t; - -/*! @brief Clock Mux Switches - * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable - * starting from LSB upwards - * - * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* - * - */ - -#define CLK_ATTACH_ID(mux, sel, pos) \ - ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((uint32_t)(pos)*12U)) -#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U) -#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U)) - -#define GET_ID_ITEM(connection) ((connection)&0xFFFU) -#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U) -#define GET_ID_ITEM_MUX(connection) (((uint8_t)connection) & 0xFFU) -#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF00U) >> 8U) - 1U)) -#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) - -#define CM_SYSTICKCLKSEL0 0U -#define CM_SYSTICKCLKSEL1 1U -#define CM_TRACECLKSEL 2U -#define CM_CTIMERCLKSEL0 3U -#define CM_CTIMERCLKSEL1 4U -#define CM_CTIMERCLKSEL2 5U -#define CM_CTIMERCLKSEL3 6U -#define CM_CTIMERCLKSEL4 7U -#define CM_MAINCLKSELA 8U -#define CM_MAINCLKSELB 9U -#define CM_CLKOUTCLKSEL 10U -#define CM_PLL0CLKSEL 12U -#define CM_PLL1CLKSEL 13U -#define CM_ADCASYNCCLKSEL 17U -#define CM_USB0CLKSEL 18U -#define CM_FXCOMCLKSEL0 20U -#define CM_FXCOMCLKSEL1 21U -#define CM_FXCOMCLKSEL2 22U -#define CM_FXCOMCLKSEL3 23U -#define CM_FXCOMCLKSEL4 24U -#define CM_FXCOMCLKSEL5 25U -#define CM_FXCOMCLKSEL6 26U -#define CM_FXCOMCLKSEL7 27U -#define CM_HSLSPICLKSEL 28U -#define CM_MCLKCLKSEL 32U -#define CM_SCTCLKSEL 36U -#define CM_SDIOCLKSEL 38U - -#define CM_RTCOSC32KCLKSEL 63U - -/*! - * @brief The enumerator of clock attach Id. - */ -typedef enum _clock_attach_id -{ - - kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO12M to MAIN_CLK. */ - - kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach EXT_CLK to MAIN_CLK. */ - - kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO1M to MAIN_CLK. */ - - kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO_HF to MAIN_CLK. */ - - kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0), /*!< Attach PLL0 to MAIN_CLK. */ - - kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), /*!< Attach PLL1 to MAIN_CLK. */ - - kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), /*!< Attach OSC32K to MAIN_CLK. */ - - kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Attach MAIN_CLK to CLKOUT. */ - - kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Attach PLL0 to CLKOUT. */ - - kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Attach EXT_CLK to CLKOUT. */ - - kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Attach FRO_HF to CLKOUT. */ - - kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Attach FRO1M to CLKOUT. */ - - kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Attach PLL1 to CLKOUT. */ - - kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Attach OSC32K to CLKOUT. */ - - kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< Attach NONE to SYS_CLKOUT. */ - - kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0), /*!< Attach FRO12M to PLL0. */ - - kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1), /*!< Attach EXT_CLK to PLL0. */ - - kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2), /*!< Attach FRO1M to PLL0. */ - - kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3), /*!< Attach OSC32K to PLL0. */ - - kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7), /*!< Attach NONE to PLL0. */ - - kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), /*!< Attach MAIN_CLK to ADC_CLK. */ - - kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), /*!< Attach PLL0 to ADC_CLK. */ - - kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), /*!< Attach FRO_HF to ADC_CLK. */ - - kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), /*!< Attach NONE to ADC_CLK. */ - - kMAIN_CLK_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0), /*!< Attach MAIN_CLK to USB0_CLK. */ - - kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1), /*!< Attach PLL0 to USB0_CLK. */ - - kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3), /*!< Attach FRO_HF to USB0_CLK. */ - - kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5), /*!< Attach PLL1 to USB0_CLK. */ - - kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7), /*!< Attach NONE to USB0_CLK. */ - - kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), /*!< Attach MAIN_CLK to FLEXCOMM0. */ - - kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), /*!< Attach PLL0_DIV to FLEXCOMM0. */ - - kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), /*!< Attach FRO12M to FLEXCOMM0. */ - - kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM0. */ - - kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), /*!< Attach FRO1M to FLEXCOMM0. */ - - kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5), /*!< Attach MCLK to FLEXCOMM0. */ - - kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6), /*!< Attach OSC32K to FLEXCOMM0. */ - - kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */ - - kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), /*!< Attach MAIN_CLK to FLEXCOMM1. */ - - kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), /*!< Attach PLL0_DIV to FLEXCOMM1. */ - - kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), /*!< Attach FRO12M to FLEXCOMM1. */ - - kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM1. */ - - kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), /*!< Attach FRO1M to FLEXCOMM1. */ - - kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5), /*!< Attach MCLK to FLEXCOMM1. */ - - kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6), /*!< Attach OSC32K to FLEXCOMM1. */ - - kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */ - - kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), /*!< Attach MAIN_CLK to FLEXCOMM2. */ - - kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), /*!< Attach PLL0_DIV to FLEXCOMM2. */ - - kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), /*!< Attach FRO12M to FLEXCOMM2. */ - - kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM2. */ - - kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), /*!< Attach FRO1M to FLEXCOMM2. */ - - kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5), /*!< Attach MCLK to FLEXCOMM2. */ - - kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6), /*!< Attach OSC32K to FLEXCOMM2. */ - - kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */ - - kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), /*!< Attach MAIN_CLK to FLEXCOMM3. */ - - kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), /*!< Attach PLL0_DIV to FLEXCOMM3. */ - - kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), /*!< Attach FRO12M to FLEXCOMM3. */ - - kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM3. */ - - kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), /*!< Attach FRO1M to FLEXCOMM3. */ - - kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5), /*!< Attach MCLK to FLEXCOMM3. */ - - kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6), /*!< Attach OSC32K to FLEXCOMM3. */ - - kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */ - - kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), /*!< Attach MAIN_CLK to FLEXCOMM4. */ - - kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), /*!< Attach PLL0_DIV to FLEXCOMM4. */ - - kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), /*!< Attach FRO12M to FLEXCOMM4. */ - - kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM4. */ - - kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), /*!< Attach FRO1M to FLEXCOMM4. */ - - kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5), /*!< Attach MCLK to FLEXCOMM4. */ - - kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6), /*!< Attach OSC32K to FLEXCOMM4. */ - - kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */ - - kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), /*!< Attach MAIN_CLK to FLEXCOMM5. */ - - kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), /*!< Attach PLL0_DIV to FLEXCOMM5. */ - - kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), /*!< Attach FRO12M to FLEXCOMM5. */ - - kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM5. */ - - kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), /*!< Attach FRO1M to FLEXCOMM5. */ - - kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5), /*!< Attach MCLK to FLEXCOMM5. */ - - kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6), /*!< Attach OSC32K to FLEXCOMM5. */ - - kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */ - - kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), /*!< Attach MAIN_CLK to FLEXCOMM6. */ - - kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), /*!< Attach PLL0_DIV to FLEXCOMM6. */ - - kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), /*!< Attach FRO12M to FLEXCOMM6. */ - - kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM6. */ - - kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), /*!< Attach FRO1M to FLEXCOMM6. */ - - kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5), /*!< Attach MCLK to FLEXCOMM6. */ - - kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6), /*!< Attach OSC32K to FLEXCOMM6. */ - - kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */ - - kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), /*!< Attach MAIN_CLK to FLEXCOMM7. */ - - kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), /*!< Attach PLL0_DIV to FLEXCOMM7. */ - - kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), /*!< Attach FRO12M to FLEXCOMM7. */ - - kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM7. */ - - kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), /*!< Attach FRO1M to FLEXCOMM7. */ - - kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5), /*!< Attach MCLK to FLEXCOMM7. */ - - kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6), /*!< Attach OSC32K to FLEXCOMM7. */ - - kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */ - - kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0), /*!< Attach MAIN_CLK to HSLSPI. */ - - kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1), /*!< Attach PLL0_DIV to HSLSPI. */ - - kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2), /*!< Attach FRO12M to HSLSPI. */ - - kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3), /*!< Attach FRO_HF_DIV to HSLSPI. */ - - kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4), /*!< Attach FRO1M to HSLSPI. */ - - kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6), /*!< Attach OSC32K to HSLSPI. */ - - kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7), /*!< Attach NONE to HSLSPI. */ - - kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), /*!< Attach FRO_HF to MCLK. */ - - kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), /*!< Attach PLL0 to MCLK. */ - - kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), /*!< Attach NONE to MCLK. */ - - kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), /*!< Attach MAIN_CLK to SCT_CLK. */ - - kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), /*!< Attach PLL0 to SCT_CLK. */ - - kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), /*!< Attach EXT_CLK to SCT_CLK. */ - - kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), /*!< Attach FRO_HF to SCT_CLK. */ - - kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5), /*!< Attach MCLK to SCT_CLK. */ - - kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), /*!< Attach NONE to SCT_CLK. */ - - kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0), /*!< Attach MAIN_CLK to SDIO_CLK. */ - - kPLL0_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1), /*!< Attach PLL0 to SDIO_CLK. */ - - kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3), /*!< Attach FRO_HF to SDIO_CLK. */ - - kPLL1_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 5), /*!< Attach PLL1 to SDIO_CLK. */ - - kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7), /*!< Attach NONE to SDIO_CLK. */ - - kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0), /*!< Attach FRO32K to OSC32K. */ - - kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1), /*!< Attach XTAL32K to OSC32K. */ - - kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), /*!< Attach TRACE_DIV to TRACE. */ - - kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), /*!< Attach FRO1M to TRACE. */ - - kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), /*!< Attach OSC32K to TRACE. */ - - kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), /*!< Attach NONE to TRACE. */ - - kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), /*!< Attach SYSTICK_DIV0 to SYSTICK0. */ - - kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), /*!< Attach FRO1M to SYSTICK0. */ - - kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), /*!< Attach OSC32K to SYSTICK0. */ - - kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), /*!< Attach NONE to SYSTICK0. */ - - kSYSTICK_DIV1_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 0), /*!< Attach SYSTICK_DIV1 to SYSTICK1. */ - - kFRO1M_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 1), /*!< Attach FRO1M to SYSTICK1. */ - - kOSC32K_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 2), /*!< Attach OSC32K to SYSTICK1. */ - - kNONE_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 7), /*!< Attach NONE to SYSTICK1. */ - - kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0), /*!< Attach FRO12M to PLL1. */ - - kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1), /*!< Attach EXT_CLK to PLL1. */ - - kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2), /*!< Attach FRO1M to PLL1. */ - - kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3), /*!< Attach OSC32K to PLL1. */ - - kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7), /*!< Attach NONE to PLL1. */ - - kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), /*!< Attach MAIN_CLK to CTIMER0. */ - - kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), /*!< Attach PLL0 to CTIMER0. */ - - kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), /*!< Attach FRO_HF to CTIMER0. */ - - kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), /*!< Attach FRO1M to CTIMER0. */ - - kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), /*!< Attach MCLK to CTIMER0. */ - - kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), /*!< Attach OSC32K to CTIMER0. */ - - kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7), /*!< Attach NONE to CTIMER0. */ - - kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), /*!< Attach MAIN_CLK to CTIMER1. */ - - kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), /*!< Attach PLL0 to CTIMER1. */ - - kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), /*!< Attach FRO_HF to CTIMER1. */ - - kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), /*!< Attach FRO1M to CTIMER1. */ - - kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), /*!< Attach MCLK to CTIMER1. */ - - kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), /*!< Attach OSC32K to CTIMER1. */ - - kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7), /*!< Attach NONE to CTIMER1. */ - - kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), /*!< Attach MAIN_CLK to CTIMER2. */ - - kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), /*!< Attach PLL0 to CTIMER2. */ - - kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), /*!< Attach FRO_HF to CTIMER2. */ - - kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), /*!< Attach FRO1M to CTIMER2. */ - - kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), /*!< Attach MCLK to CTIMER2. */ - - kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), /*!< Attach OSC32K to CTIMER2. */ - - kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7), /*!< Attach NONE to CTIMER2. */ - - kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), /*!< Attach MAIN_CLK to CTIMER3. */ - - kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), /*!< Attach PLL0 to CTIMER3. */ - - kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), /*!< Attach FRO_HF to CTIMER3. */ - - kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), /*!< Attach FRO1M to CTIMER3. */ - - kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), /*!< Attach MCLK to CTIMER3. */ - - kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), /*!< Attach OSC32K to CTIMER3. */ - - kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7), /*!< Attach NONE to CTIMER3. */ - - kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), /*!< Attach MAIN_CLK to CTIMER4. */ - - kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), /*!< Attach PLL0 to CTIMER4. */ - - kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), /*!< Attach FRO_HF to CTIMER4. */ - - kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), /*!< Attach FRO1M to CTIMER4. */ - - kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), /*!< Attach MCLK to CTIMER4. */ - - kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), /*!< Attach OSC32K to CTIMER4. */ - - kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7), /*!< Attach NONE to CTIMER4. */ - - kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */ - -} clock_attach_id_t; - -/*! @brief Clock dividers */ -typedef enum _clock_div_name -{ - kCLOCK_DivSystickClk0 = 0, /*!< Systick Clk0 Divider. */ - - kCLOCK_DivSystickClk1 = 1, /*!< Systick Clk1 Divider. */ - - kCLOCK_DivArmTrClkDiv = 2, /*!< Arm Tr Clk Div Divider. */ - - kCLOCK_DivFlexFrg0 = 8, /*!< Flex Frg0 Divider. */ - - kCLOCK_DivFlexFrg1 = 9, /*!< Flex Frg1 Divider. */ - - kCLOCK_DivFlexFrg2 = 10, /*!< Flex Frg2 Divider. */ - - kCLOCK_DivFlexFrg3 = 11, /*!< Flex Frg3 Divider. */ - - kCLOCK_DivFlexFrg4 = 12, /*!< Flex Frg4 Divider. */ - - kCLOCK_DivFlexFrg5 = 13, /*!< Flex Frg5 Divider. */ - - kCLOCK_DivFlexFrg6 = 14, /*!< Flex Frg6 Divider. */ - - kCLOCK_DivFlexFrg7 = 15, /*!< Flex Frg7 Divider. */ - - kCLOCK_DivAhbClk = 32, /*!< Ahb Clock Divider. */ - - kCLOCK_DivClkOut = 33, /*!< Clk Out Divider. */ - - kCLOCK_DivFrohfClk = 34, /*!< Frohf Clock Divider. */ - - kCLOCK_DivWdtClk = 35, /*!< Wdt Clock Divider. */ - - kCLOCK_DivAdcAsyncClk = 37, /*!< Adc Async Clock Divider. */ - - kCLOCK_DivUsb0Clk = 38, /*!< Usb0 Clock Divider. */ - - kCLOCK_DivMClk = 43, /*!< I2S MCLK Clock Divider. */ - - kCLOCK_DivSctClk = 45, /*!< Sct Clock Divider. */ - - kCLOCK_DivSdioClk = 47, /*!< Sdio Clock Divider. */ - - kCLOCK_DivPll0Clk = 49 /*!< PLL clock divider. */ -} clock_div_name_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief Enable the clock for specific IP. - * @param clk Clock to be enabled. - * @return Nothing - */ -static inline void CLOCK_EnableClock(clock_ip_name_t clk) -{ - uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); -} -/** - * @brief Disable the clock for specific IP. - * @param clk Clock to be Disabled. - * @return Nothing - */ -static inline void CLOCK_DisableClock(clock_ip_name_t clk) -{ - uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); -} -/** - * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). - * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is - * enabled. - * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ) - * @return returns success or fail status. - */ -status_t CLOCK_SetupFROClocking(uint32_t iFreq); -/** - * @brief Set the flash wait states for the input freuqency. - * @param iFreq : Input frequency - * @return Nothing - */ -void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq); -/** - * @brief Initialize the external osc clock to given frequency. - * @param iFreq : Desired frequency (must be equal to exact rate in Hz) - * @return returns success or fail status. - */ -status_t CLOCK_SetupExtClocking(uint32_t iFreq); -/** - * @brief Initialize the I2S MCLK clock to given frequency. - * @param iFreq : Desired frequency (must be equal to exact rate in Hz) - * @return returns success or fail status. - */ -status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq); -/** - * @brief Initialize the PLU CLKIN clock to given frequency. - * @param iFreq : Desired frequency (must be equal to exact rate in Hz) - * @return returns success or fail status. - */ -status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq); -/** - * @brief Configure the clock selection muxes. - * @param connection : Clock to be configured. - * @return Nothing - */ -void CLOCK_AttachClk(clock_attach_id_t connection); -/** - * @brief Get the actual clock attach id. - * This fuction uses the offset in input attach id, then it reads the actual source value in - * the register and combine the offset to obtain an actual attach id. - * @param attachId : Clock attach id to get. - * @return Clock source value. - */ -clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId); -/** - * @brief Setup peripheral clock dividers. - * @param div_name : Clock divider name - * @param divided_by_value: Value to be divided - * @param reset : Whether to reset the divider counter. - * @return Nothing - */ -void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset); -/** - * @brief Setup rtc 1khz clock divider. - * @param divided_by_value: Value to be divided - * @return Nothing - */ -void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value); -/** - * @brief Setup rtc 1hz clock divider. - * @param divided_by_value: Value to be divided - * @return Nothing - */ -void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value); - -/** - * @brief Set the flexcomm output frequency. - * @param id : flexcomm instance id - * @param freq : output frequency - * @return 0 : the frequency range is out of range. - * 1 : switch successfully. - */ -uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq); - -/*! @brief Return Frequency of flexcomm input clock - * @param id : flexcomm instance id - * @return Frequency value - */ -uint32_t CLOCK_GetFlexCommInputClock(uint32_t id); - -/*! @brief Return Frequency of selected clock - * @return Frequency of selected clock - */ -uint32_t CLOCK_GetFreq(clock_name_t clockName); -/*! @brief Return Frequency of FRO 12MHz - * @return Frequency of FRO 12MHz - */ -uint32_t CLOCK_GetFro12MFreq(void); -/*! @brief Return Frequency of FRO 1MHz - * @return Frequency of FRO 1MHz - */ -uint32_t CLOCK_GetFro1MFreq(void); -/*! @brief Return Frequency of ClockOut - * @return Frequency of ClockOut - */ -uint32_t CLOCK_GetClockOutClkFreq(void); -/*! @brief Return Frequency of Adc Clock - * @return Frequency of Adc. - */ -uint32_t CLOCK_GetAdcClkFreq(void); -/*! @brief Return Frequency of Usb0 Clock - * @return Frequency of Usb0 Clock. - */ -uint32_t CLOCK_GetUsb0ClkFreq(void); -/*! @brief Return Frequency of Usb1 Clock - * @return Frequency of Usb1 Clock. - */ -uint32_t CLOCK_GetUsb1ClkFreq(void); -/*! @brief Return Frequency of MClk Clock - * @return Frequency of MClk Clock. - */ -uint32_t CLOCK_GetMclkClkFreq(void); -/*! @brief Return Frequency of SCTimer Clock - * @return Frequency of SCTimer Clock. - */ -uint32_t CLOCK_GetSctClkFreq(void); -/*! @brief Return Frequency of SDIO Clock - * @return Frequency of SDIO Clock. - */ -uint32_t CLOCK_GetSdioClkFreq(void); -/*! @brief Return Frequency of External Clock - * @return Frequency of External Clock. If no external clock is used returns 0. - */ -uint32_t CLOCK_GetExtClkFreq(void); -/*! @brief Return Frequency of Watchdog - * @return Frequency of Watchdog - */ -uint32_t CLOCK_GetWdtClkFreq(void); -/*! @brief Return Frequency of High-Freq output of FRO - * @return Frequency of High-Freq output of FRO - */ -uint32_t CLOCK_GetFroHfFreq(void); -/*! @brief Return Frequency of PLL - * @return Frequency of PLL - */ -uint32_t CLOCK_GetPll0OutFreq(void); -/*! @brief Return Frequency of USB PLL - * @return Frequency of PLL - */ -uint32_t CLOCK_GetPll1OutFreq(void); -/*! @brief Return Frequency of 32kHz osc - * @return Frequency of 32kHz osc - */ -uint32_t CLOCK_GetOsc32KFreq(void); -/*! @brief Return Frequency of Core System - * @return Frequency of Core System - */ -uint32_t CLOCK_GetCoreSysClkFreq(void); -/*! @brief Return Frequency of I2S MCLK Clock - * @return Frequency of I2S MCLK Clock - */ -uint32_t CLOCK_GetI2SMClkFreq(void); -/*! @brief Return Frequency of PLU CLKIN Clock - * @return Frequency of PLU CLKIN Clock - */ -uint32_t CLOCK_GetPLUClkInFreq(void); -/*! @brief Return Frequency of FlexComm Clock - * @return Frequency of FlexComm Clock - */ -uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id); -/*! @brief Return Frequency of High speed SPI Clock - * @return Frequency of High speed SPI Clock - */ -uint32_t CLOCK_GetHsLspiClkFreq(void); -/*! @brief Return Frequency of CTimer functional Clock - * @return Frequency of CTimer functional Clock - */ -uint32_t CLOCK_GetCTimerClkFreq(uint32_t id); -/*! @brief Return Frequency of SystickClock - * @return Frequency of Systick Clock - */ -uint32_t CLOCK_GetSystickClkFreq(uint32_t id); - -/*! @brief Return PLL0 input clock rate - * @return PLL0 input clock rate - */ -uint32_t CLOCK_GetPLL0InClockRate(void); - -/*! @brief Return PLL1 input clock rate - * @return PLL1 input clock rate - */ -uint32_t CLOCK_GetPLL1InClockRate(void); - -/*! @brief Return PLL0 output clock rate - * @param recompute : Forces a PLL rate recomputation if true - * @return PLL0 output clock rate - * @note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetPLL0OutClockRate(bool recompute); - -/*! @brief Enables and disables PLL0 bypass mode - * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass - * @return PLL0 output clock rate - */ -__STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass) -{ - if (bypass) - { - SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); - } - else - { - SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); - } -} - -/*! @brief Enables and disables PLL1 bypass mode - * @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass - * @return PLL1 output clock rate - */ -__STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass) -{ - if (bypass) - { - SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); - } - else - { - SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); - } -} - -/*! @brief Check if PLL is locked or not - * @return true if the PLL is locked, false if not locked - */ -__STATIC_INLINE bool CLOCK_IsPLL0Locked(void) -{ - return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0UL); -} - -/*! @brief Check if PLL1 is locked or not - * @return true if the PLL1 is locked, false if not locked - */ -__STATIC_INLINE bool CLOCK_IsPLL1Locked(void) -{ - return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0UL); -} - -/*! @brief Store the current PLL0 rate - * @param rate: Current rate of the PLL0 - * @return Nothing - **/ -void CLOCK_SetStoredPLL0ClockRate(uint32_t rate); - -/*! @brief PLL configuration structure flags for 'flags' field - * These flags control how the PLL configuration function sets up the PLL setup structure.
- * - * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the - * configuration structure must be assigned with the expected PLL frequency. If the - * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration - * function and the driver will determine the PLL rate from the currently selected - * PLL source. This flag might be used to configure the PLL input clock more accurately - * when using the WDT oscillator or a more dyanmic CLKIN source.
- * - * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the - * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider - * are not used.
- */ -#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */ -#define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U) -/*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */ - -/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency - * See (MF) field in the PLL0SSCG1 register in the UM. - */ -typedef enum _ss_progmodfm -{ - kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */ - kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */ - kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */ - kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */ - kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */ - kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */ - kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */ - kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */ -} ss_progmodfm_t; - -/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth - * See (MR) field in the PLL0SSCG1 register in the UM. - */ -typedef enum _ss_progmoddp -{ - kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */ - kSS_MR_K1 = (1 << 23), /*!< k = 1 */ - kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */ - kSS_MR_K2 = (3 << 23), /*!< k = 2 */ - kSS_MR_K3 = (4 << 23), /*!< k = 3 */ - kSS_MR_K4 = (5 << 23), /*!< k = 4 */ - kSS_MR_K6 = (6 << 23), /*!< k = 6 */ - kSS_MR_K8 = (7 << 23) /*!< k = 8 */ -} ss_progmoddp_t; - -/*! @brief PLL Spread Spectrum (SS) Modulation waveform control - * See (MC) field in the PLL0SSCG1 register in the UM.
- * Compensation for low pass filtering of the PLL to get a triangular - * modulation at the output of the PLL, giving a flat frequency spectrum. - */ -typedef enum _ss_modwvctrl -{ - kSS_MC_NOC = (0 << 26), /*!< no compensation */ - kSS_MC_RECC = (2 << 26), /*!< recommended setting */ - kSS_MC_MAXC = (3 << 26), /*!< max. compensation */ -} ss_modwvctrl_t; - -/*! @brief PLL configuration structure - * - * This structure can be used to configure the settings for a PLL - * setup structure. Fill in the desired configuration for the PLL - * and call the PLL setup function to fill in a PLL setup structure. - */ -typedef struct _pll_config -{ - uint32_t desiredRate; /*!< Desired PLL rate in Hz */ - uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */ - uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ - ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - ss_modwvctrl_t - ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ - bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - -} pll_config_t; - -/*! @brief PLL setup structure flags for 'flags' field - * These flags control how the PLL setup function sets up the PLL - */ -#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */ -#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ -#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */ -#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */ - -/*! @brief PLL0 setup structure - * This structure can be used to pre-build a PLL setup configuration - * at run-time and quickly set the PLL to the configuration. It can be - * populated with the PLL setup function. If powering up or waiting - * for PLL lock, the PLL input clock source should be configured prior - * to PLL setup. - */ -typedef struct _pll_setup -{ - uint32_t pllctrl; /*!< PLL control register PLL0CTRL */ - uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */ - uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */ - uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */ - uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/ - uint32_t pllRate; /*!< Acutal PLL rate */ - uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ -} pll_setup_t; - -/*! @brief PLL status definitions - */ -typedef enum _pll_error -{ - kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ - kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ - kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ - kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ - kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ - kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */ - kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */ - kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */ -} pll_error_t; - -/*! @brief USB FS clock source definition. */ -typedef enum _clock_usbfs_src -{ - kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 MHz. */ - kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, /*!< Use PLL0 output. */ - kCLOCK_UsbfsSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */ - kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, /*!< Use PLL1 clock. */ - - kCLOCK_UsbfsSrcNone = - SYSCON_USB0CLKSEL_SEL(7) /*!COMP & ~(PMC_COMP_LOWPOWER_MASK | PMC_COMP_HYST_MASK | PMC_COMP_FILTERCGF_CLKDIV_MASK | - PMC_COMP_FILTERCGF_SAMPLEMODE_MASK)); - - if (true == config->enableLowPower) - { - tmpReg |= PMC_COMP_LOWPOWER_MASK; - } - else - { - tmpReg &= ~PMC_COMP_LOWPOWER_MASK; - } - - if (true == config->enableHysteresis) - { - tmpReg |= PMC_COMP_HYST_MASK; - } - else - { - tmpReg &= ~PMC_COMP_HYST_MASK; - } - - tmpReg |= (PMC_COMP_FILTERCGF_CLKDIV(config->filterClockDivider) | - PMC_COMP_FILTERCGF_SAMPLEMODE(config->filterSampleMode)); - - PMC->COMP = tmpReg; -} - -/*! - * @brief CMP deinitialization. - * - * This function gates the clock for CMP module. - */ -void CMP_Deinit(void) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(kCLOCK_Comp); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Initializes the CMP user configuration structure. - * - * This function initializes the user configuration structure to these default values. - * @code - * config->enableHysteresis = true; - * config->enableLowPower = true; - * config->filterClockDivider = kCMP_FilterClockDivide1; - * config->filterSampleMode = kCMP_FilterSampleMode0; - * @endcode - * @param config Pointer to the configuration structure. - */ -void CMP_GetDefaultConfig(cmp_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enableHysteresis = true; - config->enableLowPower = true; - config->filterClockDivider = kCMP_FilterClockDivide1; - config->filterSampleMode = kCMP_FilterSampleMode0; -} - -/*! - * @brief Configures the VREFINPUT. - * - * @param config Pointer to the configuration structure. - */ -void CMP_SetVREF(const cmp_vref_config_t *config) -{ - assert(NULL != config); - assert(config->vrefValue < 32U); - - uint32_t tmpReg = PMC->COMP & ~(PMC_COMP_VREF_MASK | PMC_COMP_VREFINPUT_MASK); - - tmpReg |= PMC_COMP_VREFINPUT(config->vrefSource) | PMC_COMP_VREF(config->vrefValue); - - PMC->COMP = tmpReg; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_cmp.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_cmp.h deleted file mode 100644 index 1afdc972808..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_cmp.h +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Copyright 2018-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __FSL_CMP_H_ -#define __FSL_CMP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup cmp_1 - * @{ - */ - -/****************************************************************************** - * Definitions. - *****************************************************************************/ -/*! @name Driver version */ -/*@{*/ -/*! @brief Driver version 2.2.1. */ -#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 1U)) -/*@}*/ - -/*! @brief CMP input mux for positive and negative sides. */ -enum _cmp_input_mux -{ - kCMP_InputVREF = 0U, /*!< Cmp input from VREF. */ - kCMP_Input1 = 1U, /*!< Cmp input source 1. */ - kCMP_Input2 = 2U, /*!< Cmp input source 2. */ - kCMP_Input3 = 3U, /*!< Cmp input source 3. */ - kCMP_Input4 = 4U, /*!< Cmp input source 4. */ - kCMP_Input5 = 5U, /*!< Cmp input source 5. */ -}; - -/*! @brief CMP interrupt type. */ -enum _cmp_interrupt_type -{ - kCMP_EdgeDisable = 0U, /*!< Disable edge interupt. */ - kCMP_EdgeRising = 2U, /*!< Interrupt on falling edge. */ - kCMP_EdgeFalling = 4U, /*!< Interrupt on rising edge. */ - kCMP_EdgeRisingFalling = 6U, /*!< Interrupt on both rising and falling edges. */ - - kCMP_LevelDisable = 1U, /*!< Disable level interupt. */ - kCMP_LevelHigh = 3U, /*!< Interrupt on high level. */ - kCMP_LevelLow = 5U, /*!< Interrupt on low level. */ -}; - -/*! @brief CMP Voltage Reference source. */ -typedef enum _cmp_vref_source -{ - KCMP_VREFSourceVDDA = 1U, /*!< Select VDDA as VREF. */ - KCMP_VREFSourceInternalVREF = 0U, /*!< Select internal VREF as VREF. */ -} cmp_vref_source_t; - -typedef struct _cmp_vref_config -{ - cmp_vref_source_t vrefSource; /*!< Reference voltage source. */ - uint8_t vrefValue; /*!< Reference voltage step. Available range is 0-31. Per step equals to VREFINPUT/31. */ -} cmp_vref_config_t; - -/*! @brief CMP Filter sample mode. */ -typedef enum _cmp_filtercgf_samplemode -{ - kCMP_FilterSampleMode0 = 0U, /*!< Bypass mode. Filtering is disabled. */ - kCMP_FilterSampleMode1 = 1U, /*!< Filter 1 clock period. */ - kCMP_FilterSampleMode2 = 2U, /*!< Filter 2 clock period. */ - kCMP_FilterSampleMode3 = 3U /*!< Filter 3 clock period. */ -} cmp_filtercgf_samplemode_t; - -/*! @brief CMP Filter clock divider. */ -typedef enum _cmp_filtercgf_clkdiv -{ - kCMP_FilterClockDivide1 = 0U, /*!< Filter clock period duration equals 1 analog comparator clock period. */ - kCMP_FilterClockDivide2 = 1U, /*!< Filter clock period duration equals 2 analog comparator clock period. */ - kCMP_FilterClockDivide4 = 2U, /*!< Filter clock period duration equals 4 analog comparator clock period. */ - kCMP_FilterClockDivide8 = 3U, /*!< Filter clock period duration equals 8 analog comparator clock period. */ - kCMP_FilterClockDivide16 = 4U, /*!< Filter clock period duration equals 16 analog comparator clock period. */ - kCMP_FilterClockDivide32 = 5U, /*!< Filter clock period duration equals 32 analog comparator clock period. */ - kCMP_FilterClockDivide64 = 6U /*!< Filter clock period duration equals 64 analog comparator clock period. */ -} cmp_filtercgf_clkdiv_t; - -/*! @brief CMP configuration structure. */ -typedef struct _cmp_config -{ - bool enableHysteresis; /*!< Enable hysteresis. */ - bool enableLowPower; /*!< Enable low power mode. */ - cmp_filtercgf_clkdiv_t filterClockDivider; /* Filter clock divider. Filter clock equals the Analog Comparator clock - divided by 2^FILTERCGF_CLKDIV. */ - cmp_filtercgf_samplemode_t - filterSampleMode; /* Filter sample mode. Control the filtering of the Analog Comparator output. */ -} cmp_config_t; - -/************************************************************************************************* - * API - ************************************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief CMP initialization. - * - * This function enables the CMP module and do necessary settings. - * - * @param config Pointer to the configuration structure. - */ -void CMP_Init(const cmp_config_t *config); - -/*! - * @brief CMP deinitialization. - * - * This function gates the clock for CMP module. - */ -void CMP_Deinit(void); - -/*! - * @brief Initializes the CMP user configuration structure. - * - * This function initializes the user configuration structure to these default values. - * @code - * config->enableHysteresis = true; - * config->enableLowPower = true; - * config->filterClockDivider = kCMP_FilterClockDivide1; - * config->filterSampleMode = kCMP_FilterSampleMode0; - * @endcode - * @param config Pointer to the configuration structure. - */ -void CMP_GetDefaultConfig(cmp_config_t *config); - -/* @} */ - -/*! - * @name Compare Interface - * @{ - */ - -/* - * @brief Set the input channels for the comparator. - * - * @param positiveChannel Positive side input channel number. See "_cmp_input_mux". - * @param negativeChannel Negative side input channel number. See "_cmp_input_mux". - */ -static inline void CMP_SetInputChannels(uint8_t positiveChannel, uint8_t negativeChannel) -{ - PMC->COMP &= ~(PMC_COMP_PMUX_MASK | PMC_COMP_NMUX_MASK); - PMC->COMP |= (PMC_COMP_PMUX(positiveChannel) | PMC_COMP_NMUX(negativeChannel)); -} - -/*! - * @brief Configures the VREFINPUT. - * - * @param config Pointer to the configuration structure. - */ -void CMP_SetVREF(const cmp_vref_config_t *config); - -/*! - * @brief Get CMP compare output. - * - * @return The output result. true: voltage on positive side is greater than negative side. - * false: voltage on positive side is lower than negative side. - */ -static inline bool CMP_GetOutput(void) -{ - return SYSCON_COMP_INT_STATUS_VAL_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_VAL_MASK); -} - -/* @} */ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief CMP enable interrupt. - * - * @param type CMP interrupt type. See "_cmp_interrupt_type". - */ -static inline void CMP_EnableInterrupt(uint32_t type) -{ - SYSCON->COMP_INT_CTRL |= (SYSCON_COMP_INT_CTRL_INT_CTRL(type) | SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK); -} - -/*! - * @brief CMP disable interrupt. - * - */ -static inline void CMP_DisableInterrupt(void) -{ - SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK; -} - -/*! - * @brief CMP clear interrupt. - * - */ -static inline void CMP_ClearInterrupt(void) -{ - SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK; -} - -/*! - * @brief Select which Analog comparator output (filtered or un-filtered) is used for interrupt detection. - * - * @param enable false: Select Analog Comparator raw output (unfiltered) as input for interrupt detection. - * true: Select Analog Comparator filtered output as input for interrupt detection. - * - * @note: When CMP is configured as the wakeup source in power down mode, this function must use the raw output as the - * interupt source, that is, call this function and set parameter enable to false. - */ -static inline void CMP_EnableFilteredInterruptSource(bool enable) -{ - if (enable) - { - SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; - } - else - { - SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; - } -} -/* @} */ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Get CMP interrupt status before interupt enable. - * - * @return Interrupt status. true: interrupt pending, - * false: no interrupt pending. - */ -static inline bool CMP_GetPreviousInterruptStatus(void) -{ - return SYSCON_COMP_INT_STATUS_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_STATUS_MASK); -} - -/*! - * @brief Get CMP interrupt status after interupt enable. - * - * @return Interrupt status. true: interrupt pending, - * false: no interrupt pending. - */ -static inline bool CMP_GetInterruptStatus(void) -{ - return SYSCON_COMP_INT_STATUS_INT_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK); -} -/* @} */ - -/*! - * @name Filter Interface - * @{ - */ - -/*! - * @brief CMP Filter Sample Config. - * - * This function allows the users to configure the sampling mode and clock divider of the CMP Filter. - * - * @param filterSampleMode CMP Select filter sample mode - * @param filterClockDivider CMP Set fileter clock divider - */ -static inline void CMP_FilterSampleConfig(cmp_filtercgf_samplemode_t filterSampleMode, - cmp_filtercgf_clkdiv_t filterClockDivider) -{ - uint32_t comp = PMC->COMP; - - comp &= ~(PMC_COMP_FILTERCGF_CLKDIV_MASK | PMC_COMP_FILTERCGF_SAMPLEMODE_MASK); - comp |= (((uint32_t)filterClockDivider << PMC_COMP_FILTERCGF_CLKDIV_SHIFT) | - ((uint32_t)filterSampleMode << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)); - - PMC->COMP = comp; -} -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ -#endif /* __FSL_CMP_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_common.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_common.c deleted file mode 100644 index d3af9fdfc67..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_common.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" - -#define SDK_MEM_MAGIC_NUMBER 12345U - -typedef struct _mem_align_control_block -{ - uint16_t identifier; /*!< Identifier for the memory control block. */ - uint16_t offset; /*!< offset from aligned address to real address */ -} mem_align_cb_t; - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.common" -#endif - -#if !((defined(__DSC__) && defined(__CW__))) -void *SDK_Malloc(size_t size, size_t alignbytes) -{ - mem_align_cb_t *p_cb = NULL; - uint32_t alignedsize; - - /* Check overflow. */ - alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes); - if (alignedsize < size) - { - return NULL; - } - - if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t)) - { - return NULL; - } - - alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t); - - union - { - void *pointer_value; - uintptr_t unsigned_value; - } p_align_addr, p_addr; - - p_addr.pointer_value = malloc((size_t)alignedsize); - - if (p_addr.pointer_value == NULL) - { - return NULL; - } - - p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes); - - p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U); - p_cb->identifier = SDK_MEM_MAGIC_NUMBER; - p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value); - - return p_align_addr.pointer_value; -} - -void SDK_Free(void *ptr) -{ - union - { - void *pointer_value; - uintptr_t unsigned_value; - } p_free; - p_free.pointer_value = ptr; - mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U); - - if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) - { - return; - } - - p_free.unsigned_value = p_free.unsigned_value - p_cb->offset; - - free(p_free.pointer_value); -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_common.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_common.h deleted file mode 100644 index d9cb304f2f8..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_common.h +++ /dev/null @@ -1,316 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_COMMON_H_ -#define _FSL_COMMON_H_ - -#include -#include -#include -#include -#include - -#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__) -#include -#endif - -#include "fsl_device_registers.h" - -/*! - * @addtogroup ksdk_common - * @{ - */ - -/******************************************************************************* - * Configurations - ******************************************************************************/ - -/*! @brief Macro to use the default weak IRQ handler in drivers. */ -#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ -#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Construct a status code value from a group and code number. */ -#define MAKE_STATUS(group, code) ((((group)*100L) + (code))) - -/*! @brief Construct the version number for drivers. - * - * The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M) - * and 16-bit platforms(such as DSC). - * - * @verbatim - - | Unused || Major Version || Minor Version || Bug Fix | - 31 25 24 17 16 9 8 0 - - @endverbatim - */ -#define MAKE_VERSION(major, minor, bugfix) (((major) * 65536L) + ((minor) * 256L) + (bugfix)) - -/*! @name Driver version */ -/*@{*/ -/*! @brief common driver version. */ -#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 2)) -/*@}*/ - -/* Debug console type definition. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */ - -/*! @brief Status group numbers. */ -enum _status_groups -{ - kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ - kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ - kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ - kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ - kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ - kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ - kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ - kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ - kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ - kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ - kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ - kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ - kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ - kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ - kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ - kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ - kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ - kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ - kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ - kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ - kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ - kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ - kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ - kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ - kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ - kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ - kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ - kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ - kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ - kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ - kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ - kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ - kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ - kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ - kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ - kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ - kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ - kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ - kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ - kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ - kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ - kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ - kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ - kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ - kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ - kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ - kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ - kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ - kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ - kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ - kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ - kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ - kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ - kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ - kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ - kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ - kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ - kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ - kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ - kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ - kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ - kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ - kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ - kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ - kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ - kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ - kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ - kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ - kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ - kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ - kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ - kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ - kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ - kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/ - kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */ - kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */ - kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */ - - kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ - kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ - kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ - kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ - kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ - kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ - kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ - kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ - kStatusGroup_HAL_I2S = 129, /*!< Group number for HAL I2S status codes. */ - kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ - kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ - kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ - kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ - kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ - kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ - kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ - kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ - kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ - kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ - kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ - kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ - kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ - kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ - kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */ - kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */ - kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */ - kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */ - kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */ - kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */ - kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */ - kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */ - kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */ - kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */ - kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */ - kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */ - kStatusGroup_CSS_PKC = 161, /*!< Group number for CSS PKC status codes. */ - kStatusGroup_HOSTIF = 162, /*!< Group number for HOSTIF status codes. */ - kStatusGroup_CLIF = 163, /*!< Group number for CLIF status codes. */ - kStatusGroup_BMA = 164, /*!< Group number for BMA status codes. */ -}; - -/*! \public - * @brief Generic status return codes. - */ -enum -{ - kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */ - kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */ - kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */ - kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */ - kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */ - kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */ - kStatus_NoTransferInProgress = - MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */ - kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */ - kStatus_NoData = - MAKE_STATUS(kStatusGroup_Generic, 8), /*!< Generic status for no data is found for the operation. */ -}; - -/*! @brief Type used for all status and error return values. */ -typedef int32_t status_t; - -/*! - * @name Min/max macros - * @{ - */ -#if !defined(MIN) -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) -#endif - -#if !defined(MAX) -#define MAX(a, b) (((a) > (b)) ? (a) : (b)) -#endif -/* @} */ - -/*! @brief Computes the number of elements in an array. */ -#if !defined(ARRAY_SIZE) -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) -#endif - -/*! @name UINT16_MAX/UINT32_MAX value */ -/* @{ */ -#if !defined(UINT16_MAX) -#define UINT16_MAX ((uint16_t)-1) -#endif - -#if !defined(UINT32_MAX) -#define UINT32_MAX ((uint32_t)-1) -#endif -/* @} */ - -/*! @name Suppress fallthrough warning macro */ -/* For switch case code block, if case section ends without "break;" statement, there wil be - fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. - To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each - case section which misses "break;"statement. - */ -/* @{ */ -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) -#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough)) -#else -#define SUPPRESS_FALL_THROUGH_WARNING() -#endif -/* @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -#if !((defined(__DSC__) && defined(__CW__))) -/*! - * @brief Allocate memory with given alignment and aligned size. - * - * This is provided to support the dynamically allocated memory - * used in cache-able region. - * @param size The length required to malloc. - * @param alignbytes The alignment size. - * @retval The allocated memory. - */ -void *SDK_Malloc(size_t size, size_t alignbytes); - -/*! - * @brief Free memory. - * - * @param ptr The memory to be release. - */ -void SDK_Free(void *ptr); -#endif - -/*! - * @brief Delay at least for some time. - * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, - * if precise delay count was needed, please implement a new delay function with hardware timer. - * - * @param delayTime_us Delay time in unit of microsecond. - * @param coreClock_Hz Core clock frequency with Hz. - */ -void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#if (defined(__DSC__) && defined(__CW__)) -#include "fsl_common_dsc.h" -#elif defined(__XCC__) -#include "fsl_common_dsp.h" -#else -#include "fsl_common_arm.h" -#endif - -#endif /* _FSL_COMMON_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_common_arm.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_common_arm.c deleted file mode 100644 index e77a265ce43..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_common_arm.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.common_arm" -#endif - -#ifndef __GIC_PRIO_BITS -#if defined(ENABLE_RAM_VECTOR_TABLE) -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) -{ -#ifdef __VECTOR_TABLE -#undef __VECTOR_TABLE -#endif - -/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) - extern uint32_t Image$$VECTOR_ROM$$Base[]; - extern uint32_t Image$$VECTOR_RAM$$Base[]; - extern uint32_t Image$$RW_m_data$$Base[]; - -#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base -#define __VECTOR_RAM Image$$VECTOR_RAM$$Base -#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) -#elif defined(__ICCARM__) - extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; -#elif defined(__GNUC__) - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; - extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; - uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); -#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ - uint32_t n; - uint32_t ret; - uint32_t irqMaskValue; - - irqMaskValue = DisableGlobalIRQ(); - if (SCB->VTOR != (uint32_t)__VECTOR_RAM) - { - /* Copy the vector table from ROM to RAM */ - for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) - { - __VECTOR_RAM[n] = __VECTOR_TABLE[n]; - } - /* Point the VTOR to the position of vector table */ - SCB->VTOR = (uint32_t)__VECTOR_RAM; - } - - ret = __VECTOR_RAM[(int32_t)irq + 16]; - /* make sure the __VECTOR_RAM is noncachable */ - __VECTOR_RAM[(int32_t)irq + 16] = irqHandler; - - EnableGlobalIRQ(irqMaskValue); - - return ret; -} -#endif /* ENABLE_RAM_VECTOR_TABLE. */ -#endif /* __GIC_PRIO_BITS. */ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - -/* - * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, - * powerlib should be used instead of these functions. - */ -#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) - -/* - * When the SYSCON STARTER registers are discontinuous, these functions are - * implemented in fsl_power.c. - */ -#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) - -void EnableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t intNumber = (uint32_t)interrupt; - - uint32_t index = 0; - - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERSET[index] = 1UL << intNumber; - (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */ -} - -void DisableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t intNumber = (uint32_t)interrupt; - - (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */ - uint32_t index = 0; - - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERCLR[index] = 1UL << intNumber; -} -#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ -#endif /* FSL_FEATURE_POWERLIB_EXTEND */ -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - -#if defined(SDK_DELAY_USE_DWT) && defined(DWT) -/* Use WDT. */ -static void enableCpuCycleCounter(void) -{ - /* Make sure the DWT trace fucntion is enabled. */ - if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) - { - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - } - - /* CYCCNT not supported on this device. */ - assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); - - /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */ - if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) - { - DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; - } -} - -static uint32_t getCpuCycleCount(void) -{ - return DWT->CYCCNT; -} -#else /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ -/* Use software loop. */ -#if defined(__CC_ARM) /* This macro is arm v5 specific */ -/* clang-format off */ -__ASM static void DelayLoop(uint32_t count) -{ -loop - SUBS R0, R0, #1 - CMP R0, #0 - BNE loop - BX LR -} -/* clang-format on */ -#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__) -/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler, - * use SUB and CMP here for compatibility */ -static void DelayLoop(uint32_t count) -{ - __ASM volatile(" MOV R0, %0" : : "r"(count)); - __ASM volatile( - "loop: \n" -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) - " SUB R0, R0, #1 \n" -#else - " SUBS R0, R0, #1 \n" -#endif - " CMP R0, #0 \n" - - " BNE loop \n" - : - : - : "r0"); -} -#endif /* defined(__CC_ARM) */ -#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ - -/*! - * @brief Delay at least for some time. - * Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have - * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and - * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports - * up to 4294967 in current code. If long time delay is needed, please implement a new delay function. - * - * @param delayTime_us Delay time in unit of microsecond. - * @param coreClock_Hz Core clock frequency with Hz. - */ -void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) -{ - uint64_t count; - - if (delayTime_us > 0U) - { - count = USEC_TO_COUNT(delayTime_us, coreClock_Hz); - - assert(count <= UINT32_MAX); - -#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */ - - enableCpuCycleCounter(); - /* Calculate the count ticks. */ - count += getCpuCycleCount(); - - if (count > UINT32_MAX) - { - count -= UINT32_MAX; - /* Wait for cyccnt overflow. */ - while (count < getCpuCycleCount()) - { - } - } - - /* Wait for cyccnt reach count value. */ - while (count > getCpuCycleCount()) - { - } -#else - /* Divide value may be different in various environment to ensure delay is precise. - * Every loop count includes three instructions, due to Cortex-M7 sometimes executes - * two instructions in one period, through test here set divide 1.5. Other M cores use - * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does - * not matter because other instructions outside while loop is enough to fill the time. - */ -#if (__CORTEX_M == 7) - count = count / 3U * 2U; -#else - count = count / 4U; -#endif - DelayLoop((uint32_t)count); -#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_common_arm.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_common_arm.h deleted file mode 100644 index 2678ff625c7..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_common_arm.h +++ /dev/null @@ -1,671 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_COMMON_ARM_H_ -#define _FSL_COMMON_ARM_H_ - -/* - * For CMSIS pack RTE. - * CMSIS pack RTE generates "RTC_Components.h" which contains the statements - * of the related element for all selected software components. - */ -#ifdef _RTE_ -#include "RTE_Components.h" -#endif - -/*! - * @addtogroup ksdk_common - * @{ - */ - -/*! @name Atomic modification - * - * These macros are used for atomic access, such as read-modify-write - * to the peripheral registers. - * - * - SDK_ATOMIC_LOCAL_ADD - * - SDK_ATOMIC_LOCAL_SET - * - SDK_ATOMIC_LOCAL_CLEAR - * - SDK_ATOMIC_LOCAL_TOGGLE - * - SDK_ATOMIC_LOCAL_CLEAR_AND_SET - * - * Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr - * means the address of the peripheral register or variable you want to modify - * atomically, the parameter @c clearBits is the bits to clear, the parameter - * @c setBits it the bits to set. - * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this: - * - * @code - volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR; - - SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02); - @endcode - * - * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result, - * register bit1:bit0 = 0b10. - * - * @note For the platforms don't support exclusive load and store, these macros - * disable the global interrupt to pretect the modification. - * - * @note These macros only guarantee the local processor atomic operations. For - * the multi-processor devices, use hardware semaphore such as SEMA42 to - * guarantee exclusive access if necessary. - * - * @{ - */ - -/* clang-format off */ -#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) -/* clang-format on */ - -/* If the LDREX and STREX are supported, use them. */ -#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \ - do \ - { \ - (val) = __LDREXB(addr); \ - (ops); \ - } while (0UL != __STREXB((val), (addr))) - -#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \ - do \ - { \ - (val) = __LDREXH(addr); \ - (ops); \ - } while (0UL != __STREXH((val), (addr))) - -#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \ - do \ - { \ - (val) = __LDREXW(addr); \ - (ops); \ - } while (0UL != __STREXW((val), (addr))) - -static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val); -} - -static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val); -} - -static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val); -} - -static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val); -} - -static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val); -} - -static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val); -} - -static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits); -} - -static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits); -} - -static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits); -} - -static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits); -} - -static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits); -} - -static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits); -} - -static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits); -} - -static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits); -} - -static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits); -} - -static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); -} - -static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); -} - -static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); -} - -#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ - ((1UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalAdd1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \ - ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \ - _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val)))) - -#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ - ((1UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ - ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ - _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) - -#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ - ((1UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalClear1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ - ((2UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalClear2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ - _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) - -#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ - ((1UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalToggle1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ - ((2UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalToggle2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ - _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) - -#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ - ((1UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(clearBits), (uint8_t)(setBits)) : \ - ((2UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(clearBits), (uint16_t)(setBits)) : \ - _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(clearBits), (uint32_t)(setBits)))) -#else - -#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ - do \ - { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) += (val); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ - do \ - { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) |= (bits); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ - do \ - { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) &= ~(bits); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ - do \ - { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) ^= (bits); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ - do \ - { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) = (*(addr) & ~(clearBits)) | (setBits); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#endif -/* @} */ - -/*! @name Timer utilities */ -/* @{ */ -/*! Macro to convert a microsecond period to raw count value */ -#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) -/*! Macro to convert a raw count value to microsecond */ -#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000000U / (clockFreqInHz)) - -/*! Macro to convert a millisecond period to raw count value */ -#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) -/*! Macro to convert a raw count value to millisecond */ -#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz)) -/* @} */ - -/*! @name ISR exit barrier - * @{ - * - * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - * exception return operation might vector to incorrect interrupt. - * For Cortex-M7, if core speed much faster than peripheral register write speed, - * the peripheral interrupt flags may be still set after exiting ISR, this results to - * the same error similar with errata 83869. - */ -#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U)) -#define SDK_ISR_EXIT_BARRIER __DSB() -#else -#define SDK_ISR_EXIT_BARRIER -#endif - -/* @} */ - -/*! @name Alignment variable definition macros */ -/* @{ */ -#if (defined(__ICCARM__)) -/* - * Workaround to disable MISRA C message suppress warnings for IAR compiler. - * http:/ /supp.iar.com/Support/?note=24725 - */ -_Pragma("diag_suppress=Pm120") -#define SDK_PRAGMA(x) _Pragma(#x) - _Pragma("diag_error=Pm120") -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var -#elif defined(__GNUC__) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) -#else -#error Toolchain not supported -#endif - -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#endif - -/*! Macro to change a value to a given size aligned value */ -#define SDK_SIZEALIGN(var, alignbytes) \ - ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) -/* @} */ - -/*! @name Non-cacheable region definition macros */ -/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or - * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable - * variables, please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, - * these zero-inited variables will be initialized to zero in system startup. - */ -/* @{ */ - -#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \ - defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) - -#if (defined(__ICCARM__)) -#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" -#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" - -#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var -#if (defined(__CC_ARM)) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var -#else -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var -#endif - -#elif (defined(__GNUC__)) -/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" - * in your projects to make sure the non-cacheable section variables will be initialized in system startup. - */ -#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) -#else -#error Toolchain not supported. -#endif - -#else - -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes) -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes) - -#endif - -/* @} */ - -/*! - * @name Time sensitive region - * @{ - */ -#if (defined(__ICCARM__)) -#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" -#define AT_QUICKACCESS_SECTION_DATA(var) var @"DataQuickAccess" -#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ - SDK_PRAGMA(data_alignment = alignbytes) var @"DataQuickAccess" -#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func -#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var -#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ - __attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var -#elif (defined(__GNUC__)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func -#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var -#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ - __attribute__((section("DataQuickAccess"))) var __attribute__((aligned(alignbytes))) -#else -#error Toolchain not supported. -#endif /* defined(__ICCARM__) */ - -/*! @name Ram Function */ -#if (defined(__ICCARM__)) -#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" -#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func -#elif (defined(__GNUC__)) -#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func -#else -#error Toolchain not supported. -#endif /* defined(__ICCARM__) */ -/* @} */ - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - void DefaultISR(void); -#endif - -/* - * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t - * defined in previous of this file. - */ -#include "fsl_clock.h" - -/* - * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral - */ -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) -#include "fsl_reset.h" -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief Enable specific interrupt. - * - * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt enabled successfully - * @retval kStatus_Fail Failed to enable the interrupt - */ -static inline status_t EnableIRQ(IRQn_Type interrupt) -{ - status_t status = kStatus_Success; - - if (NotAvail_IRQn == interrupt) - { - status = kStatus_Fail; - } - -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - status = kStatus_Fail; - } -#endif - - else - { -#if defined(__GIC_PRIO_BITS) - GIC_EnableIRQ(interrupt); -#else - NVIC_EnableIRQ(interrupt); -#endif - } - - return status; -} - -/*! - * @brief Disable specific interrupt. - * - * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt disabled successfully - * @retval kStatus_Fail Failed to disable the interrupt - */ -static inline status_t DisableIRQ(IRQn_Type interrupt) -{ - status_t status = kStatus_Success; - - if (NotAvail_IRQn == interrupt) - { - status = kStatus_Fail; - } - -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - status = kStatus_Fail; - } -#endif - - else - { -#if defined(__GIC_PRIO_BITS) - GIC_DisableIRQ(interrupt); -#else - NVIC_DisableIRQ(interrupt); -#endif - } - - return status; -} - -/*! - * @brief Disable the global IRQ - * - * Disable the global interrupt and return the current primask register. User is required to provided the primask - * register for the EnableGlobalIRQ(). - * - * @return Current primask value. - */ -static inline uint32_t DisableGlobalIRQ(void) -{ -#if defined(CPSR_I_Msk) - uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; - - __disable_irq(); - - return cpsr; -#else - uint32_t regPrimask = __get_PRIMASK(); - - __disable_irq(); - - return regPrimask; -#endif -} - -/*! - * @brief Enable the global IRQ - * - * Set the primask register with the provided primask value but not just enable the primask. The idea is for the - * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to - * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. - * - * @param primask value of primask register to be restored. The primask value is supposed to be provided by the - * DisableGlobalIRQ(). - */ -static inline void EnableGlobalIRQ(uint32_t primask) -{ -#if defined(CPSR_I_Msk) - __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); -#else - __set_PRIMASK(primask); -#endif -} - -#if defined(ENABLE_RAM_VECTOR_TABLE) -/*! - * @brief install IRQ handler - * - * @param irq IRQ number - * @param irqHandler IRQ handler address - * @return The old IRQ handler address - */ -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); -#endif /* ENABLE_RAM_VECTOR_TABLE. */ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - -/* - * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, - * powerlib should be used instead of these functions. - */ -#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) -/*! - * @brief Enable specific interrupt for wake-up from deep-sleep mode. - * - * Enable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). - * - * @param interrupt The IRQ number. - */ -void EnableDeepSleepIRQ(IRQn_Type interrupt); - -/*! - * @brief Disable specific interrupt for wake-up from deep-sleep mode. - * - * Disable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). - * - * @param interrupt The IRQ number. - */ -void DisableDeepSleepIRQ(IRQn_Type interrupt); -#endif /* FSL_FEATURE_POWERLIB_EXTEND */ -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @} */ - -#endif /* _FSL_COMMON_ARM_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_crc.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_crc.c deleted file mode 100644 index c73f84997af..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_crc.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2019-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_crc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_crc" -#endif - -#if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT -/* @brief Default user configuration structure for CRC-CCITT */ -#define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT -/*< CRC-CCIT polynomial x^16 + x^12 + x^5 + x^0 */ -#define CRC_DRIVER_DEFAULT_REVERSE_IN false -/*< Default is no bit reverse */ -#define CRC_DRIVER_DEFAULT_COMPLEMENT_IN false -/*< Default is without complement of written data */ -#define CRC_DRIVER_DEFAULT_REVERSE_OUT false -/*< Default is no bit reverse */ -#define CRC_DRIVER_DEFAULT_COMPLEMENT_OUT false -/*< Default is without complement of CRC data register read data */ -#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU -/*< Default initial checksum */ -#endif /* CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Enables and configures the CRC peripheral module. - * - * This functions enables the CRC peripheral clock in the LPC SYSCON block. - * It also configures the CRC engine and starts checksum computation by writing the seed. - * - * param base CRC peripheral address. - * param config CRC module configuration structure. - */ -void CRC_Init(CRC_Type *base, const crc_config_t *config) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* enable clock to CRC */ - CLOCK_EnableClock(kCLOCK_Crc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_CRC_HAS_NO_RESET) && FSL_FEATURE_CRC_HAS_NO_RESET) - RESET_PeripheralReset(kCRC_RST_SHIFT_RSTn); -#endif - - /* configure CRC module and write the seed */ - base->MODE = CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) | - CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) | - CRC_MODE_CMPL_SUM(config->complementOut); - base->SEED = config->seed; -} - -/*! - * brief Loads default values to CRC protocol configuration structure. - * - * Loads default values to CRC protocol configuration structure. The default values are: - * code - * config->polynomial = kCRC_Polynomial_CRC_CCITT; - * config->reverseIn = false; - * config->complementIn = false; - * config->reverseOut = false; - * config->complementOut = false; - * config->seed = 0xFFFFU; - * endcode - * - * param config CRC protocol configuration structure - */ -void CRC_GetDefaultConfig(crc_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_REVERSE_IN, - CRC_DRIVER_DEFAULT_COMPLEMENT_IN, CRC_DRIVER_DEFAULT_REVERSE_OUT, - CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED}; - - *config = default_config; -} - -/*! - * brief resets CRC peripheral module. - * - * param base CRC peripheral address. - */ -void CRC_Reset(CRC_Type *base) -{ - crc_config_t config; - CRC_GetDefaultConfig(&config); - CRC_Init(base, &config); -} - -/*! - * brief Write seed (initial checksum) to CRC peripheral module. - * - * param base CRC peripheral address. - * param seed CRC Seed value. - */ -void CRC_WriteSeed(CRC_Type *base, uint32_t seed) -{ - /* write the seed (initial checksum) */ - base->SEED = seed; -} - -/*! - * brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure. - * - * The values, including seed, can be used to resume CRC calculation later. - - * param base CRC peripheral address. - * param config CRC protocol configuration structure - */ -void CRC_GetConfig(CRC_Type *base, crc_config_t *config) -{ - /* extract CRC mode settings */ - uint32_t mode = base->MODE; - config->polynomial = - (crc_polynomial_t)(uint32_t)(((uint32_t)(mode & CRC_MODE_CRC_POLY_MASK)) >> CRC_MODE_CRC_POLY_SHIFT); - config->reverseIn = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK); - config->complementIn = (bool)(mode & CRC_MODE_CMPL_WR_MASK); - config->reverseOut = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK); - config->complementOut = (bool)(mode & CRC_MODE_CMPL_SUM_MASK); - - /* reset CRC sum bit reverse and 1's complement setting, so its value can be used as a seed */ - base->MODE = mode & ~((1U << CRC_MODE_BIT_RVS_SUM_SHIFT) | (1U << CRC_MODE_CMPL_SUM_SHIFT)); - - /* now we can obtain intermediate raw CRC sum value */ - config->seed = base->SUM; - - /* restore original CRC sum bit reverse and 1's complement setting */ - base->MODE = mode; -} - -/*! - * brief Writes data to the CRC module. - * - * Writes input data buffer bytes to CRC data register. - * - * param base CRC peripheral address. - * param data Input data stream, MSByte in data[0]. - * param dataSize Size of the input data buffer in bytes. - */ -void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) -{ - const uint32_t *data32; - - /* 8-bit reads and writes till source address is aligned 4 bytes */ - while ((0U != dataSize) && (0U != ((uint32_t)data & 3U))) - { - *((__O uint8_t *)&(base->WR_DATA)) = *data; - data++; - dataSize--; - } - - /* use 32-bit reads and writes as long as possible */ - data32 = (const uint32_t *)(uint32_t)data; - while (dataSize >= sizeof(uint32_t)) - { - *((__O uint32_t *)&(base->WR_DATA)) = *data32; - data32++; - dataSize -= sizeof(uint32_t); - } - - data = (const uint8_t *)data32; - - /* 8-bit reads and writes till end of data buffer */ - while (0U != dataSize) - { - *((__O uint8_t *)&(base->WR_DATA)) = *data; - data++; - dataSize--; - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_crc.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_crc.h deleted file mode 100644 index 08e08bd57d3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_crc.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2019-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CRC_H_ -#define _FSL_CRC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup crc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CRC driver version. Version 2.1.1. - * - * Current version: 2.1.1 - * - * Change log: - * - Version 2.0.0 - * - initial version - * - Version 2.0.1 - * - add explicit type cast when writing to WR_DATA - * - Version 2.0.2 - * - Fix MISRA issue - * - Version 2.1.0 - * - Add CRC_WriteSeed function - * - Version 2.1.1 - * - Fix MISRA issue - */ -#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) -/*@}*/ - -#ifndef CRC_DRIVER_CUSTOM_DEFAULTS -/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Uses CRC-16/CCITT-FALSE as default. */ -#define CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT 1 -#endif - -/*! @brief CRC polynomials to use. */ -typedef enum _crc_polynomial -{ - kCRC_Polynomial_CRC_CCITT = 0U, /*!< x^16+x^12+x^5+1 */ - kCRC_Polynomial_CRC_16 = 1U, /*!< x^16+x^15+x^2+1 */ - kCRC_Polynomial_CRC_32 = 2U /*!< x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */ -} crc_polynomial_t; - -/*! - * @brief CRC protocol configuration. - * - * This structure holds the configuration for the CRC protocol. - * - */ -typedef struct _crc_config -{ - crc_polynomial_t polynomial; /*!< CRC polynomial. */ - bool reverseIn; /*!< Reverse bits on input. */ - bool complementIn; /*!< Perform 1's complement on input. */ - bool reverseOut; /*!< Reverse bits on output. */ - bool complementOut; /*!< Perform 1's complement on output. */ - uint32_t seed; /*!< Starting checksum value. */ -} crc_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Enables and configures the CRC peripheral module. - * - * This functions enables the CRC peripheral clock in the LPC SYSCON block. - * It also configures the CRC engine and starts checksum computation by writing the seed. - * - * @param base CRC peripheral address. - * @param config CRC module configuration structure. - */ -void CRC_Init(CRC_Type *base, const crc_config_t *config); - -/*! - * @brief Disables the CRC peripheral module. - * - * This functions disables the CRC peripheral clock in the LPC SYSCON block. - * - * @param base CRC peripheral address. - */ -static inline void CRC_Deinit(CRC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* disable clock to CRC */ - CLOCK_DisableClock(kCLOCK_Crc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief resets CRC peripheral module. - * - * @param base CRC peripheral address. - */ -void CRC_Reset(CRC_Type *base); - -/*! - * @brief Write seed to CRC peripheral module. - * - * @param base CRC peripheral address. - * @param seed CRC Seed value. - */ -void CRC_WriteSeed(CRC_Type *base, uint32_t seed); - -/*! - * @brief Loads default values to CRC protocol configuration structure. - * - * Loads default values to CRC protocol configuration structure. The default values are: - * @code - * config->polynomial = kCRC_Polynomial_CRC_CCITT; - * config->reverseIn = false; - * config->complementIn = false; - * config->reverseOut = false; - * config->complementOut = false; - * config->seed = 0xFFFFU; - * @endcode - * - * @param config CRC protocol configuration structure - */ -void CRC_GetDefaultConfig(crc_config_t *config); - -/*! - * @brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure. - * - * The values, including seed, can be used to resume CRC calculation later. - - * @param base CRC peripheral address. - * @param config CRC protocol configuration structure - */ -void CRC_GetConfig(CRC_Type *base, crc_config_t *config); - -/*! - * @brief Writes data to the CRC module. - * - * Writes input data buffer bytes to CRC data register. - * - * @param base CRC peripheral address. - * @param data Input data stream, MSByte in data[0]. - * @param dataSize Size of the input data buffer in bytes. - */ -void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize); - -/*! - * @brief Reads 32-bit checksum from the CRC module. - * - * Reads CRC data register. - * - * @param base CRC peripheral address. - * @return final 32-bit checksum, after configured bit reverse and complement operations. - */ -static inline uint32_t CRC_Get32bitResult(CRC_Type *base) -{ - return base->SUM; -} - -/*! - * @brief Reads 16-bit checksum from the CRC module. - * - * Reads CRC data register. - * - * @param base CRC peripheral address. - * @return final 16-bit checksum, after configured bit reverse and complement operations. - */ -static inline uint16_t CRC_Get16bitResult(CRC_Type *base) -{ - return (uint16_t)base->SUM; -} - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_CRC_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_ctimer.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_ctimer.c deleted file mode 100644 index e53bebdd013..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_ctimer.c +++ /dev/null @@ -1,577 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_ctimer.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.ctimer" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base Ctimer peripheral base address - * - * @return The Timer instance - */ -static uint32_t CTIMER_GetInstance(CTIMER_Type *base); - -/*! - * @brief CTIMER generic IRQ handle function. - * - * @param index FlexCAN peripheral instance index. - */ -static void CTIMER_GenericIRQHandler(uint32_t index); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to Timer bases for each instance. */ -static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to Timer clocks for each instance. */ -static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET -/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N; -#else -/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; -#endif -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/*! @brief Pointers real ISRs installed by drivers for each instance. */ -static ctimer_callback_t *s_ctimerCallback[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = {0}; - -/*! @brief Callback type installed by drivers for each instance. */ -static ctimer_callback_type_t ctimerCallbackType[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = { - kCTIMER_SingleCallback}; - -/*! @brief Array to map timer instance to IRQ number. */ -static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t CTIMER_GetInstance(CTIMER_Type *base) -{ - uint32_t instance; - uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ctimerArrayCount; instance++) - { - if (s_ctimerBases[instance] == base) - { - break; - } - } - - assert(instance < ctimerArrayCount); - - return instance; -} - -/*! - * brief Ungates the clock and configures the peripheral for basic operation. - * - * note This API should be called at the beginning of the application before using the driver. - * - * param base Ctimer peripheral base address - * param config Pointer to the user configuration structure. - */ -void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) -{ - assert(config != NULL); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the timer clock*/ - CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -/* Reset the module. */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) - RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]); -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/* Setup the cimer mode and count select */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input); -#endif - /* Setup the timer prescale value */ - base->PR = CTIMER_PR_PRVAL(config->prescale); -} - -/*! - * brief Gates the timer clock. - * - * param base Ctimer peripheral base address - */ -void CTIMER_Deinit(CTIMER_Type *base) -{ - uint32_t index = CTIMER_GetInstance(base); - /* Stop the timer */ - base->TCR &= ~CTIMER_TCR_CEN_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the timer clock*/ - CLOCK_DisableClock(s_ctimerClocks[index]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Disable IRQ at NVIC Level */ - (void)DisableIRQ(s_ctimerIRQ[index]); -} - -/*! - * brief Fills in the timers configuration structure with the default settings. - * - * The default values are: - * code - * config->mode = kCTIMER_TimerMode; - * config->input = kCTIMER_Capture_0; - * config->prescale = 0; - * endcode - * param config Pointer to the user configuration structure. - */ -void CTIMER_GetDefaultConfig(ctimer_config_t *config) -{ - assert(config != NULL); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* Run as a timer */ - config->mode = kCTIMER_TimerMode; - /* This field is ignored when mode is timer */ - config->input = kCTIMER_Capture_0; - /* Timer counter is incremented on every APB bus clock */ - config->prescale = 0; -} - -/*! - * brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function can manually assign the specified channel to set the PWM cycle. - * - * note When setting PWM output from multiple output pins, all should use the same PWM - * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. - * - * param base Ctimer peripheral base address - * param pwmPeriodChannel Specify the channel to control the PWM period - * param matchChannel Match pin to be used to output the PWM signal - * param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 - * param pwmFreq_Hz PWM signal frequency in Hz - * param srcClock_Hz Timer counter clock in Hz - * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt will be generated. - * - * return kStatus_Success on success - * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM cycle - */ -status_t CTIMER_SetupPwm(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - bool enableInt) -{ - assert(pwmFreq_Hz > 0U); - - uint32_t reg; - uint32_t period, pulsePeriod = 0; - uint32_t timerClock = srcClock_Hz / (base->PR + 1U); - uint32_t index = CTIMER_GetInstance(base); - - if (matchChannel == pwmPeriodChannel) - { - return kStatus_Fail; - } - - /* Enable PWM mode on the match channel */ - base->PWMC |= (1UL << (uint32_t)matchChannel); - - /* Clear the stop, reset and interrupt bits for this channel */ - reg = base->MCR; - reg &= - ~(((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK)) - << ((uint32_t)matchChannel * 3U)); - - /* If call back function is valid then enable match interrupt for the channel */ - if (enableInt) - { - reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); - } - - /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ - reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); - - base->MCR = reg; - - /* Calculate PWM period match value */ - period = (timerClock / pwmFreq_Hz) - 1U; - - /* Calculate pulse width match value */ - if (dutyCyclePercent == 0U) - { - pulsePeriod = period + 1U; - } - else - { - pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; - } - - /* Specified channel pwmPeriodChannel will define the PWM period */ - base->MR[pwmPeriodChannel] = period; - - /* This will define the PWM pulse period */ - base->MR[matchChannel] = pulsePeriod; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); - /* If call back function is valid then enable interrupt and update the call back function */ - if (enableInt) - { - (void)EnableIRQ(s_ctimerIRQ[index]); - } - - return kStatus_Success; -} - -/*! - * brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function can manually assign the specified channel to set the PWM cycle. - * - * note When setting PWM output from multiple output pins, all should use the same PWM - * period - * - * param base Ctimer peripheral base address - * param pwmPeriodChannel Specify the channel to control the PWM period - * param matchChannel Match pin to be used to output the PWM signal - * param pwmPeriod PWM period match value - * param pulsePeriod Pulse width match value - * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt will be generated. - * - * return kStatus_Success on success - * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM period - */ -status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint32_t pwmPeriod, - uint32_t pulsePeriod, - bool enableInt) -{ -/* Some CTimers only have 16bits , so the value is limited*/ -#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B - assert(!((FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32) && (pulsePeriod > 0xFFFFU))); -#endif - - uint32_t reg; - uint32_t index = CTIMER_GetInstance(base); - - if (matchChannel == pwmPeriodChannel) - { - return kStatus_Fail; - } - - /* Enable PWM mode on PWM pulse channel */ - base->PWMC |= (1UL << (uint32_t)matchChannel); - - /* Clear the stop, reset and interrupt bits for PWM pulse channel */ - reg = base->MCR; - reg &= - ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) - << ((uint32_t)matchChannel * 3U)); - - /* If call back function is valid then enable match interrupt for PWM pulse channel */ - if (enableInt) - { - reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); - } - - /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ - reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); - - base->MCR = reg; - - /* Specified channel pwmPeriodChannel will define the PWM period */ - base->MR[pwmPeriodChannel] = pwmPeriod; - - /* This will define the PWM pulse period */ - base->MR[matchChannel] = pulsePeriod; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); - /* If call back function is valid then enable interrupt and update the call back function */ - if (enableInt) - { - (void)EnableIRQ(s_ctimerIRQ[index]); - } - - return kStatus_Success; -} - -/*! - * brief Updates the duty cycle of an active PWM signal. - * - * note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. - * This function can manually assign the specified channel to set the PWM cycle. - * - * param base Ctimer peripheral base address - * param pwmPeriodChannel Specify the channel to control the PWM period - * param matchChannel Match pin to be used to output the PWM signal - * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 - */ -void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent) -{ - uint32_t pulsePeriod = 0, period; - - /* Specified channel pwmPeriodChannel defines the PWM period */ - period = base->MR[pwmPeriodChannel]; - - /* For 0% dutycyle, make pulse period greater than period so the event will never occur */ - if (dutyCyclePercent == 0U) - { - pulsePeriod = period + 1U; - } - else - { - pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; - } - - /* Update dutycycle */ - base->MR[matchChannel] = pulsePeriod; -} - -/*! - * brief Setup the match register. - * - * User configuration is used to setup the match value and action to be taken when a match occurs. - * - * param base Ctimer peripheral base address - * param matchChannel Match register to configure - * param config Pointer to the match configuration structure - */ -void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config) -{ -/* Some CTimers only have 16bits , so the value is limited*/ -#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B - assert(!(FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32 && config->matchValue > 0xFFFFU)); -#endif - uint32_t reg; - uint32_t index = CTIMER_GetInstance(base); - - /* Set the counter operation when a match on this channel occurs */ - reg = base->MCR; - reg &= - ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) - << ((uint32_t)matchChannel * 3U)); - reg |= ((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)matchChannel * 3U))); - reg |= ((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)matchChannel * 3U))); - reg |= ((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); - base->MCR = reg; - - reg = base->EMR; - /* Set the match output operation when a match on this channel occurs */ - reg &= ~(((uint32_t)CTIMER_EMR_EMC0_MASK) << ((uint32_t)matchChannel * 2U)); - reg |= ((uint32_t)config->outControl) << (CTIMER_EMR_EMC0_SHIFT + ((uint32_t)matchChannel * 2U)); - - /* Set the initial state of the EM bit/output */ - reg &= ~(((uint32_t)CTIMER_EMR_EM0_MASK) << (uint32_t)matchChannel); - reg |= ((uint32_t)config->outPinInitState) << (uint32_t)matchChannel; - base->EMR = reg; - - /* Set the match value */ - base->MR[matchChannel] = config->matchValue; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); - /* If interrupt is enabled then enable interrupt and update the call back function */ - if (config->enableInterrupt) - { - (void)EnableIRQ(s_ctimerIRQ[index]); - } -} - -/*! - * brief Get the status of output match. - * - * This function gets the status of output MAT, whether or not this output is connected to a pin. - * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - * - * param base Ctimer peripheral base address - * param matchChannel External match channel, user can obtain the status of multiple match channels - * at the same time by using the logic of "|" - * enumeration ::ctimer_external_match_t - * return The mask of external match channel status flags. Users need to use the - * _ctimer_external_match type to decode the return variables. - */ -uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel) -{ - return (base->EMR & matchChannel); -} - -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) -/*! - * brief Setup the capture. - * - * param base Ctimer peripheral base address - * param capture Capture channel to configure - * param edge Edge on the channel that will trigger a capture - * param enableInt Flag to enable channel interrupts, if enabled then the registered call back - * is called upon capture - */ -void CTIMER_SetupCapture(CTIMER_Type *base, - ctimer_capture_channel_t capture, - ctimer_capture_edge_t edge, - bool enableInt) -{ - uint32_t reg = base->CCR; - uint32_t index = CTIMER_GetInstance(base); - - /* Set the capture edge */ - reg &= ~((uint32_t)((uint32_t)CTIMER_CCR_CAP0RE_MASK | (uint32_t)CTIMER_CCR_CAP0FE_MASK | - (uint32_t)CTIMER_CCR_CAP0I_MASK) - << ((uint32_t)capture * 3U)); - reg |= ((uint32_t)edge) << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U)); - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, (((uint32_t)kCTIMER_Capture0Flag) << (uint32_t)capture)); - /* If call back function is valid then enable capture interrupt for the channel and update the call back function */ - if (enableInt) - { - reg |= ((uint32_t)CTIMER_CCR_CAP0I_MASK) << ((uint32_t)capture * 3U); - (void)EnableIRQ(s_ctimerIRQ[index]); - } - base->CCR = reg; -} -#endif - -/*! - * brief Register callback. - * - * param base Ctimer peripheral base address - * param cb_func callback function - * param cb_type callback function type, singular or multiple - */ -void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type) -{ - uint32_t index = CTIMER_GetInstance(base); - s_ctimerCallback[index] = cb_func; - ctimerCallbackType[index] = cb_type; -} - -/*! - * brief CTIMER generic IRQ handle function. - * - * param index FlexCAN peripheral instance index. - */ -static void CTIMER_GenericIRQHandler(uint32_t index) -{ - uint32_t int_stat, i, mask; - /* Get Interrupt status flags */ - int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]); - /* Clear the status flags that were set */ - CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat); - if (ctimerCallbackType[index] == kCTIMER_SingleCallback) - { - if (s_ctimerCallback[index][0] != NULL) - { - s_ctimerCallback[index][0](int_stat); - } - } - else - { -#if defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE - for (i = 0; i <= CTIMER_IR_MR3INT_SHIFT; i++) -#else -#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT - for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) -#else -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) - for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) -#else - for (i = 0; i <= CTIMER_IR_CR1INT_SHIFT; i++) -#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ -#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ -#endif - { - mask = 0x01UL << i; - /* For each status flag bit that was set call the callback function if it is valid */ - if (((int_stat & mask) != 0U) && (s_ctimerCallback[index][i] != NULL)) - { - s_ctimerCallback[index][i](int_stat); - } - } - } - SDK_ISR_EXIT_BARRIER; -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(CTIMER0) -void CTIMER0_DriverIRQHandler(void); -void CTIMER0_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(0); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CTIMER1) -void CTIMER1_DriverIRQHandler(void); -void CTIMER1_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(1); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CTIMER2) -void CTIMER2_DriverIRQHandler(void); -void CTIMER2_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(2); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CTIMER3) -void CTIMER3_DriverIRQHandler(void); -void CTIMER3_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(3); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CTIMER4) -void CTIMER4_DriverIRQHandler(void); -void CTIMER4_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(4); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_ctimer.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_ctimer.h deleted file mode 100644 index ca39c95d30e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_ctimer.h +++ /dev/null @@ -1,533 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_CTIMER_H_ -#define _FSL_CTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup ctimer - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) /*!< Version 2.2.2 */ -/*@}*/ - -/*! @brief List of Timer capture channels */ -typedef enum _ctimer_capture_channel -{ - kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ - kCTIMER_Capture_1, /*!< Timer capture channel 1 */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - kCTIMER_Capture_2, /*!< Timer capture channel 2 */ -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - kCTIMER_Capture_3 /*!< Timer capture channel 3 */ -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ -} ctimer_capture_channel_t; - -/*! @brief List of capture edge options */ -typedef enum _ctimer_capture_edge -{ - kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */ - kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */ - kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */ -} ctimer_capture_edge_t; - -/*! @brief List of Timer match registers */ -typedef enum _ctimer_match -{ - kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */ - kCTIMER_Match_1, /*!< Timer match register 1 */ - kCTIMER_Match_2, /*!< Timer match register 2 */ - kCTIMER_Match_3 /*!< Timer match register 3 */ -} ctimer_match_t; - -/*! @brief List of external match */ -typedef enum _ctimer_external_match -{ - kCTIMER_External_Match_0 = (1U << 0), /*!< External match 0 */ - kCTIMER_External_Match_1 = (1U << 1), /*!< External match 1 */ - kCTIMER_External_Match_2 = (1U << 2), /*!< External match 2 */ - kCTIMER_External_Match_3 = (1U << 3) /*!< External match 3 */ -} ctimer_external_match_t; - -/*! @brief List of output control options */ -typedef enum _ctimer_match_output_control -{ - kCTIMER_Output_NoAction = 0U, /*!< No action is taken */ - kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */ - kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */ - kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */ -} ctimer_match_output_control_t; - -/*! @brief List of Timer modes */ -typedef enum _ctimer_timer_mode -{ - kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */ - kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */ - kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */ - kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */ -} ctimer_timer_mode_t; - -/*! @brief List of Timer interrupts */ -typedef enum _ctimer_interrupt_enable -{ - kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ - kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ - kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ - kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ - kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ -#endif -} ctimer_interrupt_enable_t; - -/*! @brief List of Timer flags */ -typedef enum _ctimer_status_flags -{ - kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ - kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ - kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ - kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ - kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) - kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ -#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ -#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT - kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ -#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ -#endif -} ctimer_status_flags_t; - -typedef void (*ctimer_callback_t)(uint32_t flags); - -/*! @brief Callback type when registering for a callback. When registering a callback - * an array of function pointers is passed the size could be 1 or 8, the callback - * type will tell that. - */ -typedef enum -{ - kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. - based on the status flags different channels needs to be handled differently */ - kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. - for both match/capture */ -} ctimer_callback_type_t; - -/*! - * @brief Match configuration - * - * This structure holds the configuration settings for each match register. - */ -typedef struct _ctimer_match_config -{ - uint32_t matchValue; /*!< This is stored in the match register */ - bool enableCounterReset; /*!< true: Match will reset the counter - false: Match will not reser the counter */ - bool enableCounterStop; /*!< true: Match will stop the counter - false: Match will not stop the counter */ - ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */ - bool outPinInitState; /*!< Initial value of the EM bit/output */ - bool enableInterrupt; /*!< true: Generate interrupt upon match - false: Do not generate interrupt on match */ - -} ctimer_match_config_t; - -/*! - * @brief Timer configuration structure - * - * This structure holds the configuration settings for the Timer peripheral. To initialize this - * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a - * pointer to the configuration structure instance. - * - * The configuration structure can be made constant so as to reside in flash. - */ -typedef struct _ctimer_config -{ - ctimer_timer_mode_t mode; /*!< Timer mode */ - ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer - modes that rely on this input signal to increment TC */ - uint32_t prescale; /*!< Prescale value */ -} ctimer_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application before using the driver. - * - * @param base Ctimer peripheral base address - * @param config Pointer to the user configuration structure. - */ -void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config); - -/*! - * @brief Gates the timer clock. - * - * @param base Ctimer peripheral base address - */ -void CTIMER_Deinit(CTIMER_Type *base); - -/*! - * @brief Fills in the timers configuration structure with the default settings. - * - * The default values are: - * @code - * config->mode = kCTIMER_TimerMode; - * config->input = kCTIMER_Capture_0; - * config->prescale = 0; - * @endcode - * @param config Pointer to the user configuration structure. - */ -void CTIMER_GetDefaultConfig(ctimer_config_t *config); - -/*! @}*/ - -/*! - * @name PWM setup operations - * @{ - */ - -/*! - * @brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function can manually assign the specified channel to set the PWM cycle. - * - * @note When setting PWM output from multiple output pins, all should use the same PWM - * period - * - * @param base Ctimer peripheral base address - * @param pwmPeriodChannel Specify the channel to control the PWM period - * @param matchChannel Match pin to be used to output the PWM signal - * @param pwmPeriod PWM period match value - * @param pulsePeriod Pulse width match value - * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt will be generated. - */ -status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint32_t pwmPeriod, - uint32_t pulsePeriod, - bool enableInt); - -/*! - * @brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function can manually assign the specified channel to set the PWM cycle. - * - * @note When setting PWM output from multiple output pins, all should use the same PWM - * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. - * - * @param base Ctimer peripheral base address - * @param pwmPeriodChannel Specify the channel to control the PWM period - * @param matchChannel Match pin to be used to output the PWM signal - * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz Timer counter clock in Hz - * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt will be generated. - */ -status_t CTIMER_SetupPwm(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - bool enableInt); - -/*! - * @brief Updates the pulse period of an active PWM signal. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match pin to be used to output the PWM signal - * @param pulsePeriod New PWM pulse width match value - */ -static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod) -{ - /* Update PWM pulse period match value */ - base->MR[matchChannel] = pulsePeriod; -} - -/*! - * @brief Updates the duty cycle of an active PWM signal. - * - * @note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. - * This function can manually assign the specified channel to set the PWM cycle. - * - * @param base Ctimer peripheral base address - * @param pwmPeriodChannel Specify the channel to control the PWM period - * @param matchChannel Match pin to be used to output the PWM signal - * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 - */ -void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent); - -/*! @}*/ - -/*! - * @brief Setup the match register. - * - * User configuration is used to setup the match value and action to be taken when a match occurs. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match register to configure - * @param config Pointer to the match configuration structure - */ -void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config); - -/*! - * @brief Get the status of output match. - * - * This function gets the status of output MAT, whether or not this output is connected to a pin. - * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - * - * @param base Ctimer peripheral base address - * @param matchChannel External match channel, user can obtain the status of multiple match channels - * at the same time by using the logic of "|" - * enumeration ::ctimer_external_match_t - * @return The mask of external match channel status flags. Users need to use the - * _ctimer_external_match type to decode the return variables. - */ -uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel); - -/*! - * @brief Setup the capture. - * - * @param base Ctimer peripheral base address - * @param capture Capture channel to configure - * @param edge Edge on the channel that will trigger a capture - * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back - * is called upon capture - */ -void CTIMER_SetupCapture(CTIMER_Type *base, - ctimer_capture_channel_t capture, - ctimer_capture_edge_t edge, - bool enableInt); - -/*! - * @brief Get the timer count value from TC register. - * - * @param base Ctimer peripheral base address. - * @return return the timer count value. - */ -static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base) -{ - return (base->TC); -} - -/*! - * @brief Register callback. - * - * @param base Ctimer peripheral base address - * @param cb_func callback function - * @param cb_type callback function type, singular or multiple - */ -void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type); - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected Timer interrupts. - * - * @param base Ctimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) -{ - /* Enable match interrupts */ - base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); - -/* Enable capture interrupts */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - | CTIMER_CCR_CAP2I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - ); -#endif -} - -/*! - * @brief Disables the selected Timer interrupts. - * - * @param base Ctimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) -{ - /* Disable match interrupts */ - base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK)); - -/* Disable capture interrupts */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - | CTIMER_CCR_CAP2I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - )); -#endif -} - -/*! - * @brief Gets the enabled Timer interrupts. - * - * @param base Ctimer peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) -{ - uint32_t enabledIntrs = 0; - - /* Get all the match interrupts enabled */ - enabledIntrs = - base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); - -/* Get all the capture interrupts enabled */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - | CTIMER_CCR_CAP2I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - ); -#endif - - return enabledIntrs; -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the Timer status flags. - * - * @param base Ctimer peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::ctimer_status_flags_t - */ -static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base) -{ - return base->IR; -} - -/*! - * @brief Clears the Timer status flags. - * - * @param base Ctimer peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::ctimer_status_flags_t - */ -static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask) -{ - base->IR = mask; -} - -/*! @}*/ - -/*! - * @name Counter Start and Stop - * @{ - */ - -/*! - * @brief Starts the Timer counter. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_StartTimer(CTIMER_Type *base) -{ - base->TCR |= CTIMER_TCR_CEN_MASK; -} - -/*! - * @brief Stops the Timer counter. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_StopTimer(CTIMER_Type *base) -{ - base->TCR &= ~CTIMER_TCR_CEN_MASK; -} - -/*! @}*/ - -/*! - * @brief Reset the counter. - * - * The timer counter and prescale counter are reset on the next positive edge of the APB clock. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_Reset(CTIMER_Type *base) -{ - base->TCR |= CTIMER_TCR_CRST_MASK; - base->TCR &= ~CTIMER_TCR_CRST_MASK; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_CTIMER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_dma.c deleted file mode 100644 index 6b7bc594ad0..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_dma.c +++ /dev/null @@ -1,1079 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_dma.h" -#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) -#include "fsl_memory.h" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_dma" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for DMA. - * - * @param base DMA peripheral base address. - */ -static uint32_t DMA_GetInstance(DMA_Type *base); - -/*! - * @brief Get virtual channel number. - * - * @param base DMA peripheral base address. - */ -static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map DMA instance number to base pointer. */ -static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map DMA instance number to clock name. */ -static const clock_ip_name_t s_dmaClockName[] = DMA_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET) -/*! @brief Pointers to DMA resets for each instance. */ -static const reset_ip_name_t s_dmaResets[] = DMA_RSTS_N; -#endif /*! @brief Array to map DMA instance number to IRQ number. */ -static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS; - -/*! @brief Pointers to transfer handle for each DMA channel. */ -static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_ALL_CHANNELS]; - -/*! @brief DMA driver internal descriptor table */ -#ifdef FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE -SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE); -#else -#if (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) -AT_NONCACHEABLE_SECTION_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -#else -SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -#endif /* (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) */ -#endif /* FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE */ - -#if defined(DMA1) -#ifdef FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE -SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE); -#else -#if (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) -AT_NONCACHEABLE_SECTION_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -#else -SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -#endif /* (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) */ -#endif /* FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE */ -static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0, s_dma_descriptor_table1}; -#else -static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0}; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t DMA_GetInstance(DMA_Type *base) -{ - uint32_t instance; - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++) - { - if (s_dmaBases[instance] == base) - { - break; - } - } - assert(instance < ARRAY_SIZE(s_dmaBases)); - - return instance; -} - -static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base) -{ - uint32_t startChannel = 0, instance = 0; - uint32_t i = 0; - - instance = DMA_GetInstance(base); - - /* Compute start channel */ - for (i = 0; i < instance; i++) - { - startChannel += (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(s_dmaBases[i]); - } - - return startChannel; -} - -/*! - * brief Initializes DMA peripheral. - * - * This function enable the DMA clock, set descriptor table and - * enable DMA peripheral. - * - * param base DMA peripheral base address. - */ -void DMA_Init(DMA_Type *base) -{ - uint32_t instance = DMA_GetInstance(base); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* enable dma clock gate */ - CLOCK_EnableClock(s_dmaClockName[DMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET) - /* Reset the DMA module */ - RESET_PeripheralReset(s_dmaResets[DMA_GetInstance(base)]); -#endif - /* set descriptor table */ -#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) - base->SRAMBASE = MEMORY_ConvertMemoryMapAddress((uint32_t)s_dma_descriptor_table[instance], kMEMORY_Local2DMA); -#else - base->SRAMBASE = (uint32_t)s_dma_descriptor_table[instance]; -#endif - /* enable dma peripheral */ - base->CTRL |= DMA_CTRL_ENABLE_MASK; -} - -/*! - * brief Deinitializes DMA peripheral. - * - * This function gates the DMA clock. - * - * param base DMA peripheral base address. - */ -void DMA_Deinit(DMA_Type *base) -{ - /* Disable DMA peripheral */ - base->CTRL &= ~(DMA_CTRL_ENABLE_MASK); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(s_dmaClockName[DMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Set trigger settings of DMA channel. - * deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig. - * - * param base DMA peripheral base address. - * param channel DMA channel number. - * param trigger trigger configuration. - */ -void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger) -{ - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); - assert((channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)) && (NULL != trigger)); - - uint32_t tmpReg = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | - DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | - DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK); - tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); - tmpReg |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); - base->CHANNEL[channel].CFG = tmpReg; -} - -/*! - * brief Gets the remaining bytes of the current DMA descriptor transfer. - * - * param base DMA peripheral base address. - * param channel DMA channel number. - * return The number of bytes which have not been transferred yet. - */ -uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) -{ - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); - assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - - /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes - * impossible to distinguish between: - * - transfer finishes (represented by value '0x3FF') - * - and remaining 1024 bytes to transfer (value 0x3FF) - * for all descriptor in chain, except the last one. - * If you decide to use this function, please use 1023 transfers as maximal value */ - - /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */ - if ((!DMA_ChannelIsActive(base, channel)) && - (0x3FFUL == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> - DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))) - { - return 0UL; - } - - return ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> - DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + - 1UL; -} - -/* Verify and convert dma_xfercfg_t to XFERCFG register */ -static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr) -{ - assert(xfercfg != NULL); - /* check source increment */ - assert((xfercfg->srcInc <= (uint8_t)kDMA_AddressInterleave4xWidth) && - (xfercfg->dstInc <= (uint8_t)kDMA_AddressInterleave4xWidth)); - /* check data width */ - assert(xfercfg->byteWidth <= (uint8_t)kDMA_Transfer32BitWidth); - /* check transfer count */ - assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT); - - uint32_t xfer = 0; - - /* set valid flag - descriptor is ready now */ - xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid); - /* set reload - allow link to next descriptor */ - xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload); - /* set swtrig flag - start transfer */ - xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig); - /* set transfer count */ - xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig); - /* set INTA */ - xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA); - /* set INTB */ - xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB); - /* set data width */ - xfer |= DMA_CHANNEL_XFERCFG_WIDTH(xfercfg->byteWidth == 4U ? 2U : xfercfg->byteWidth - 1UL); - /* set source increment value */ - xfer |= DMA_CHANNEL_XFERCFG_SRCINC( - (xfercfg->srcInc == (uint8_t)kDMA_AddressInterleave4xWidth) ? (xfercfg->srcInc - 1UL) : xfercfg->srcInc); - /* set destination increment value */ - xfer |= DMA_CHANNEL_XFERCFG_DSTINC( - (xfercfg->dstInc == (uint8_t)kDMA_AddressInterleave4xWidth) ? (xfercfg->dstInc - 1UL) : xfercfg->dstInc); - /* set transfer count */ - xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1UL); - - /* store xferCFG */ - *xfercfg_addr = xfer; -} - -/*! - * brief setup dma descriptor - * Note: This function do not support configure wrap descriptor. - * param desc DMA descriptor address. - * param xfercfg Transfer configuration for DMA descriptor. - * param srcStartAddr Start address of source address. - * param dstStartAddr Start address of destination address. - * param nextDesc Address of next descriptor in chain. - */ -void DMA_SetupDescriptor( - dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) -{ - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - -#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) - srcStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)srcStartAddr, kMEMORY_Local2DMA); - dstStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)dstStartAddr, kMEMORY_Local2DMA); - nextDesc = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)nextDesc, kMEMORY_Local2DMA); -#endif - - uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; - - width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT; - srcInc = (xfercfg & DMA_CHANNEL_XFERCFG_SRCINC_MASK) >> DMA_CHANNEL_XFERCFG_SRCINC_SHIFT; - dstInc = (xfercfg & DMA_CHANNEL_XFERCFG_DSTINC_MASK) >> DMA_CHANNEL_XFERCFG_DSTINC_SHIFT; - transferCount = ((xfercfg & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1U; - - /* covert register value to actual value */ - if (width == 2U) - { - width = kDMA_Transfer32BitWidth; - } - else - { - width += 1U; - } - - /* - * Transfers of 16 bit width require an address alignment to a multiple of 2 bytes. - * Transfers of 32 bit width require an address alignment to a multiple of 4 bytes. - * Transfers of 8 bit width can be at any address - */ - if (((NULL != srcStartAddr) && (0UL == ((uint32_t)(uint32_t *)srcStartAddr) % width)) && - ((NULL != dstStartAddr) && (0UL == ((uint32_t)(uint32_t *)dstStartAddr) % width))) - { - if (srcInc == 3U) - { - srcInc = kDMA_AddressInterleave4xWidth; - } - - if (dstInc == 3U) - { - dstInc = kDMA_AddressInterleave4xWidth; - } - - desc->xfercfg = xfercfg; - desc->srcEndAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); - desc->dstEndAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); - desc->linkToNextDesc = nextDesc; - } - else - { - /* if address alignment not satisfy the requirement, reset the descriptor to make sure DMA generate error */ - desc->xfercfg = 0U; - desc->srcEndAddr = NULL; - desc->dstEndAddr = NULL; - } -} - -/*! - * brief setup dma channel descriptor - * Note: This function support configure wrap descriptor. - * param desc DMA descriptor address. - * param xfercfg Transfer configuration for DMA descriptor. - * param srcStartAddr Start address of source address. - * param dstStartAddr Start address of destination address. - * param nextDesc Address of next descriptor in chain. - * param wrapType burst wrap type. - * param burstSize burst size, reference _dma_burst_size. - */ -void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, - uint32_t xfercfg, - void *srcStartAddr, - void *dstStartAddr, - void *nextDesc, - dma_burst_wrap_t wrapType, - uint32_t burstSize) -{ - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - -#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) - srcStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)srcStartAddr, kMEMORY_Local2DMA); - dstStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)dstStartAddr, kMEMORY_Local2DMA); - nextDesc = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)nextDesc, kMEMORY_Local2DMA); -#endif - - uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; - - width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT; - srcInc = (xfercfg & DMA_CHANNEL_XFERCFG_SRCINC_MASK) >> DMA_CHANNEL_XFERCFG_SRCINC_SHIFT; - dstInc = (xfercfg & DMA_CHANNEL_XFERCFG_DSTINC_MASK) >> DMA_CHANNEL_XFERCFG_DSTINC_SHIFT; - transferCount = ((xfercfg & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1U; - - /* covert register value to actual value */ - if (width == 2U) - { - width = kDMA_Transfer32BitWidth; - } - else - { - width += 1U; - } - - /* - * Transfers of 16 bit width require an address alignment to a multiple of 2 bytes. - * Transfers of 32 bit width require an address alignment to a multiple of 4 bytes. - * Transfers of 8 bit width can be at any address - */ - if (((NULL != srcStartAddr) && (0UL == ((uint32_t)(uint32_t *)srcStartAddr) % width)) && - ((NULL != dstStartAddr) && (0UL == ((uint32_t)(uint32_t *)dstStartAddr) % width))) - { - if (srcInc == 3U) - { - srcInc = kDMA_AddressInterleave4xWidth; - } - - if (dstInc == 3U) - { - dstInc = kDMA_AddressInterleave4xWidth; - } - - desc->xfercfg = xfercfg; - - if (wrapType == kDMA_NoWrap) - { - desc->srcEndAddr = - DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); - desc->dstEndAddr = - DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); - } - /* for the wrap transfer, the destination address should be determined by the burstSize/width/interleave size */ - if (wrapType == kDMA_SrcWrap) - { - desc->srcEndAddr = - (uint32_t *)((uint32_t)(uint32_t *)srcStartAddr + ((1UL << burstSize) - 1UL) * width * srcInc); - desc->dstEndAddr = - DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); - } - if (wrapType == kDMA_DstWrap) - { - desc->srcEndAddr = - DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); - desc->dstEndAddr = - (uint32_t *)((uint32_t)(uint32_t *)dstStartAddr + ((1UL << burstSize) - 1UL) * width * dstInc); - } - if (wrapType == kDMA_SrcAndDstWrap) - { - desc->srcEndAddr = - (uint32_t *)(((uint32_t)(uint32_t *)srcStartAddr) + ((1UL << burstSize) - 1UL) * width * srcInc); - desc->dstEndAddr = - (uint32_t *)(((uint32_t)(uint32_t *)dstStartAddr) + ((1UL << burstSize) - 1UL) * width * dstInc); - } - - desc->linkToNextDesc = nextDesc; - } - else - { - /* if address alignment not satisfy the requirement, reset the descriptor to make sure DMA generate error */ - desc->xfercfg = 0U; - desc->srcEndAddr = NULL; - desc->dstEndAddr = NULL; - } -} - -/*! - * brief Create application specific DMA descriptor - * to be used in a chain in transfer - * deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor - * param desc DMA descriptor address. - * param xfercfg Transfer configuration for DMA descriptor. - * param srcAddr Address of last item to transmit - * param dstAddr Address of last item to receive. - * param nextDesc Address of next descriptor in chain. - */ -void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc) -{ - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - assert((NULL != srcAddr) && (0UL == ((uint32_t)(uint32_t *)srcAddr) % xfercfg->byteWidth)); - assert((NULL != dstAddr) && (0UL == ((uint32_t)(uint32_t *)dstAddr) % xfercfg->byteWidth)); - - uint32_t xfercfg_reg = 0; - - DMA_SetupXferCFG(xfercfg, &xfercfg_reg); - - /* Set descriptor structure */ - DMA_SetupDescriptor(desc, xfercfg_reg, srcAddr, dstAddr, nextDesc); -} - -/*! - * brief Abort running transfer by handle. - * - * This function aborts DMA transfer specified by handle. - * - * param handle DMA handle pointer. - */ -void DMA_AbortTransfer(dma_handle_t *handle) -{ - assert(NULL != handle); - - DMA_DisableChannel(handle->base, handle->channel); - while ((DMA_COMMON_CONST_REG_GET(handle->base, handle->channel, BUSY) & - (1UL << DMA_CHANNEL_INDEX(handle->base, handle->channel))) != 0UL) - { - } - DMA_COMMON_REG_GET(handle->base, handle->channel, ABORT) |= 1UL << DMA_CHANNEL_INDEX(handle->base, handle->channel); - DMA_EnableChannel(handle->base, handle->channel); -} - -/*! - * brief Creates the DMA handle. - * - * This function is called if using transaction API for DMA. This function - * initializes the internal state of DMA handle. - * - * param handle DMA handle pointer. The DMA handle stores callback function and - * parameters. - * param base DMA peripheral base address. - * param channel DMA channel number. - */ -void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel) -{ - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); - assert((NULL != handle) && (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - - uint32_t dmaInstance; - uint32_t startChannel = 0; - /* base address is invalid DMA instance */ - dmaInstance = DMA_GetInstance(base); - startChannel = DMA_GetVirtualStartChannel(base); - - (void)memset(handle, 0, sizeof(*handle)); - handle->base = base; - handle->channel = (uint8_t)channel; - s_DMAHandle[startChannel + channel] = handle; - /* Enable NVIC interrupt */ - (void)EnableIRQ(s_dmaIRQNumber[dmaInstance]); - /* Enable channel interrupt */ - DMA_EnableChannelInterrupts(handle->base, channel); -} - -/*! - * brief Installs a callback function for the DMA transfer. - * - * This callback is called in DMA IRQ handler. Use the callback to do something after - * the current major loop transfer completes. - * - * param handle DMA handle pointer. - * param callback DMA callback function pointer. - * param userData Parameter for callback function. - */ -void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData) -{ - assert(handle != NULL); - - handle->callback = callback; - handle->userData = userData; -} - -/*! - * brief Prepares the DMA transfer structure. - * deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer and - * DMA_PrepareChannelXfer. - * This function prepares the transfer configuration structure according to the user input. - * - * param config The user configuration structure of type dma_transfer_t. - * param srcAddr DMA transfer source address. - * param dstAddr DMA transfer destination address. - * param byteWidth DMA transfer destination address width(bytes). - * param transferBytes DMA transfer bytes to be transferred. - * param type DMA transfer type. - * param nextDesc Chain custom descriptor to transfer. - * note The data address and the data width must be consistent. For example, if the SRC - * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in - * source address error(SAE). - */ -void DMA_PrepareTransfer(dma_transfer_config_t *config, - void *srcAddr, - void *dstAddr, - uint32_t byteWidth, - uint32_t transferBytes, - dma_transfer_type_t type, - void *nextDesc) -{ - uint32_t xfer_count; - assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr)); - assert((byteWidth == 1UL) || (byteWidth == 2UL) || (byteWidth == 4UL)); - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - - /* check max */ - xfer_count = transferBytes / byteWidth; - assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0UL == transferBytes % byteWidth)); - - (void)memset(config, 0, sizeof(*config)); - - if (type == kDMA_MemoryToMemory) - { - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 1; - config->isPeriph = false; - } - - else if (type == kDMA_PeripheralToMemory) - { - /* Peripheral register - source doesn't increment */ - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 1; - config->isPeriph = true; - } - else if (type == kDMA_MemoryToPeripheral) - { - /* Peripheral register - destination doesn't increment */ - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - } - /* kDMA_StaticToStatic */ - else - { - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - } - - config->dstAddr = (uint8_t *)dstAddr; - config->srcAddr = (uint8_t *)srcAddr; - config->nextDesc = (uint8_t *)nextDesc; - config->xfercfg.transferCount = (uint16_t)xfer_count; - config->xfercfg.byteWidth = (uint8_t)byteWidth; - config->xfercfg.intA = true; - config->xfercfg.reload = nextDesc != NULL; - config->xfercfg.valid = true; -} - -/*! - * brief set channel config. - * - * This function provide a interface to configure channel configuration reisters. - * - * param base DMA base address. - * param channel DMA channel number. - * param config channel configurations structure. - */ -void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph) -{ - assert(channel < (uint32_t)FSL_FEATURE_DMA_MAX_CHANNELS); - - uint32_t tmpReg = DMA_CHANNEL_CFG_PERIPHREQEN_MASK; - - if (trigger != NULL) - { - tmpReg |= DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | - DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | - DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK; - } - - tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); - - if (trigger != NULL) - { - tmpReg |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); - } - - tmpReg |= DMA_CHANNEL_CFG_PERIPHREQEN(isPeriph); - - base->CHANNEL[channel].CFG = tmpReg; -} - -/*! - * brief Prepare channel transfer configurations. - * - * This function used to prepare channel transfer configurations. - * - * param config Pointer to DMA channel transfer configuration structure. - * param srcStartAddr source start address. - * param dstStartAddr destination start address. - * param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * param type transfer type. - * param trigger DMA channel trigger configurations. - * param nextDesc address of next descriptor. - */ -void DMA_PrepareChannelTransfer(dma_channel_config_t *config, - void *srcStartAddr, - void *dstStartAddr, - uint32_t xferCfg, - dma_transfer_type_t type, - dma_channel_trigger_t *trigger, - void *nextDesc) -{ - assert((NULL != config) && (NULL != srcStartAddr) && (NULL != dstStartAddr)); - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - - /* check max */ - (void)memset(config, 0, sizeof(*config)); - - if (type == kDMA_MemoryToMemory) - { - config->isPeriph = false; - } - else if (type == kDMA_PeripheralToMemory) - { - config->isPeriph = true; - } - else if (type == kDMA_MemoryToPeripheral) - { - config->isPeriph = true; - } - /* kDMA_StaticToStatic */ - else - { - config->isPeriph = true; - } - - config->dstStartAddr = (uint8_t *)dstStartAddr; - config->srcStartAddr = (uint8_t *)srcStartAddr; - config->nextDesc = (uint8_t *)nextDesc; - config->trigger = trigger; - config->xferCfg = xferCfg; -} - -/*! - * brief load channel transfer decriptor. - * - * This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA - * transfer, the head descriptor table is defined in DMA driver, it is useful for the case: - * 1. for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly - * and then call this api to load the configured descriptor to driver descriptor table. code DMA_Init(DMA0); - * DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL); - * DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL); - * DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc); - * DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL); - * while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL)) - * {} - * endcode - * - * param base DMA base address. - * param channel DMA channel. - * param descriptor configured DMA descriptor. - */ -void DMA_LoadChannelDescriptor(DMA_Type *base, uint32_t channel, dma_descriptor_t *descriptor) -{ - assert(NULL != descriptor); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); - assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - - uint32_t instance = DMA_GetInstance(base); - dma_descriptor_t *channelDescriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][channel]); - - channelDescriptor->xfercfg = descriptor->xfercfg; - channelDescriptor->srcEndAddr = descriptor->srcEndAddr; - channelDescriptor->dstEndAddr = descriptor->dstEndAddr; - channelDescriptor->linkToNextDesc = descriptor->linkToNextDesc; - - /* Set channel XFERCFG register according first channel descriptor. */ - base->CHANNEL[channel].XFERCFG = descriptor->xfercfg; -} - -/*! - * brief Install DMA descriptor memory. - * - * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong - * transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has - * a default DMA descriptor buffer, but it support one DMA descriptor for one channel only. - * User should be take care about the address of DMA descriptor pool which required align with 512BYTE. - * - * param handle Pointer to DMA channel transfer handle. - * param addr DMA descriptor address - * param num DMA descriptor number. - */ -void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr) -{ - assert(addr != NULL); - -#if defined FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn - assert((((uint32_t)(uint32_t *)addr) & ((uint32_t)FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn(base) - 1UL)) == 0U); -#else - assert((((uint32_t)(uint32_t *)addr) & ((uint32_t)FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0U); -#endif - /* reconfigure the DMA descriptor base address */ - base->SRAMBASE = (uint32_t)(uint32_t *)addr; -} - -/*! - * brief Submit channel transfer paramter directly. - * - * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table - * is defined in DMA driver, it is useful for the case: - * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used - for it. - * code - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, - bytes), srcStartAddr, dstStartAddr, NULL); - DMA_StartTransfer(handle) - * endcode - * - * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is - required, then application should prepare - * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc2); - DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, NULL); - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, - bytes), srcStartAddr, dstStartAddr, nextDesc0); - DMA_StartTransfer(handle); - * endcode - * - * param handle Pointer to DMA handle. - * param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * param srcStartAddr source start address. - * param dstStartAddr destination start address. - * param nextDesc address of next descriptor. - */ -void DMA_SubmitChannelTransferParameter( - dma_handle_t *handle, uint32_t xferCfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) -{ - assert((NULL != srcStartAddr) && (NULL != dstStartAddr)); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); - assert(handle->channel < (uint8_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - - uint32_t instance = DMA_GetInstance(handle->base); - dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); - - DMA_SetupDescriptor(descriptor, xferCfg, srcStartAddr, dstStartAddr, nextDesc); - - /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = xferCfg; -} - -/*! - * brief Submit channel descriptor. - * - * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table - is defined in - * DMA driver, this functiono is typical for the ping pong case: - * - * 1. for the ping pong case, application should responsible for the descriptor, for example, application should - * prepare two descriptor table with macro. - * code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc0); - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelDescriptor(handle, nextDesc0); - DMA_StartTransfer(handle); - * endcode - * - * param handle Pointer to DMA handle. - * param descriptor descriptor to submit. - */ -void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descriptor) -{ - assert((NULL != handle) && (NULL != descriptor)); - - DMA_LoadChannelDescriptor(handle->base, handle->channel, descriptor); -} - -/*! - * brief Submits the DMA channel transfer request. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * It is used for the case: - * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used - for it. - * code - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,NULL); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * endcode - * - * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is - required, then application should prepare - * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc2); - DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, NULL); - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * endcode - * - * 3. for the ping pong case, application should responsible for link descriptor, for example, application should - prepare - * two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc0); - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * endcode - * param handle DMA handle pointer. - * param config Pointer to DMA transfer configuration structure. - * retval kStatus_DMA_Success It means submit transfer request succeed. - * retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config) -{ - assert((NULL != handle) && (NULL != config)); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); - assert(handle->channel < (uint8_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - uint32_t instance = DMA_GetInstance(handle->base); - dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); - - /* Previous transfer has not finished */ - if (DMA_ChannelIsActive(handle->base, handle->channel)) - { - return kStatus_DMA_Busy; - } - - /* setup channgel trigger configurations */ - DMA_SetChannelConfig(handle->base, handle->channel, config->trigger, config->isPeriph); - - DMA_SetupChannelDescriptor( - descriptor, config->xferCfg, config->srcStartAddr, config->dstStartAddr, config->nextDesc, - config->trigger == NULL ? kDMA_NoWrap : config->trigger->wrap, - (config->trigger == NULL ? (uint32_t)kDMA_BurstSize1 : - ((uint32_t)config->trigger->burst & (DMA_CHANNEL_CFG_BURSTPOWER_MASK)) >> - DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)); - - /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = config->xferCfg; - - return kStatus_Success; -} - -/*! - * brief Submits the DMA transfer request. - * deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * - * param handle DMA handle pointer. - * param config Pointer to DMA transfer configuration structure. - * retval kStatus_DMA_Success It means submit transfer request succeed. - * retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) -{ - assert((NULL != handle) && (NULL != config)); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); - assert(handle->channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - - uint32_t instance = DMA_GetInstance(handle->base); - dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); - - /* Previous transfer has not finished */ - if (DMA_ChannelIsActive(handle->base, handle->channel)) - { - return kStatus_DMA_Busy; - } - - /* enable/disable peripheral request */ - if (config->isPeriph) - { - DMA_EnableChannelPeriphRq(handle->base, handle->channel); - } - else - { - DMA_DisableChannelPeriphRq(handle->base, handle->channel); - } - - DMA_CreateDescriptor(descriptor, &config->xfercfg, config->srcAddr, config->dstAddr, config->nextDesc); - /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = descriptor->xfercfg; - - return kStatus_Success; -} - -/*! - * brief DMA start transfer. - * - * This function enables the channel request. User can call this function after submitting the transfer request - * It will trigger transfer start with software trigger only when hardware trigger is not used. - * - * param handle DMA handle pointer. - */ -void DMA_StartTransfer(dma_handle_t *handle) -{ - assert(NULL != handle); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); - - uint32_t channel = handle->channel; - assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - - /* enable channel */ - DMA_EnableChannel(handle->base, channel); - - /* Do software trigger only when HW trigger is not enabled. */ - if ((handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK) == 0U) - { - handle->base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; - } -} - -void DMA_IRQHandle(DMA_Type *base) -{ - dma_handle_t *handle; - uint8_t channel_index; - uint32_t startChannel = DMA_GetVirtualStartChannel(base); - uint32_t i = 0; - bool intEnabled = false, intA = false, intB = false; - - /* Find channels that have completed transfer */ - for (i = 0; i < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base); i++) - { - handle = s_DMAHandle[i + startChannel]; - /* Handle is not present */ - if (NULL == handle) - { - continue; - } - channel_index = DMA_CHANNEL_INDEX(base, handle->channel); - /* Channel uses INTA flag */ - intEnabled = ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTENSET) & (1UL << channel_index)) != 0UL); - intA = ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTA) & (1UL << channel_index)) != 0UL); - if (intEnabled && intA) - { - /* Clear INTA flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, INTA, (1UL << channel_index)); - if (handle->callback != NULL) - { - (handle->callback)(handle, handle->userData, true, kDMA_IntA); - } - } - - intB = ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTB) & (1UL << channel_index)) != 0UL); - /* Channel uses INTB flag */ - if (intEnabled && intB) - { - /* Clear INTB flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, INTB, (1UL << channel_index)); - if (handle->callback != NULL) - { - (handle->callback)(handle, handle->userData, true, kDMA_IntB); - } - } - /* Error flag */ - if ((DMA_COMMON_REG_GET(handle->base, handle->channel, ERRINT) & (1UL << channel_index)) != 0UL) - { - /* Clear error flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, ERRINT, (1UL << channel_index)); - if (handle->callback != NULL) - { - (handle->callback)(handle, handle->userData, false, kDMA_IntError); - } - } - } -} - -void DMA0_DriverIRQHandler(void); -void DMA0_DriverIRQHandler(void) -{ - DMA_IRQHandle(DMA0); - SDK_ISR_EXIT_BARRIER; -} - -#if defined(DMA1) -void DMA1_DriverIRQHandler(void); -void DMA1_DriverIRQHandler(void) -{ - DMA_IRQHandle(DMA1); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_dma.h deleted file mode 100644 index 0e857752e58..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_dma.h +++ /dev/null @@ -1,892 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_DMA_H_ -#define _FSL_DMA_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup dma - * @{ - */ - -/*! @file */ -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief DMA driver version */ -#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 4)) /*!< Version 2.4.4. */ -/*@}*/ - -/*! @brief DMA max transfer size */ -#define DMA_MAX_TRANSFER_COUNT 0x400U -/*! @brief DMA channel numbers */ -#if defined FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_MAX_CHANNELS FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_ALL_CHANNELS (FSL_FEATURE_DMA_NUMBER_OF_CHANNELS * FSL_FEATURE_SOC_DMA_COUNT) -#endif -/*! @brief DMA head link descriptor table align size */ -#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) -/*! @brief DMA head descriptor table allocate macro - * To simplify user interface, this macro will help allocate descriptor memory, - * user just need to provide the name and the number for the allocate descriptor. - * - * @param name Allocate decriptor name. - * @param number Number of descriptor to be allocated. - */ -#define DMA_ALLOCATE_HEAD_DESCRIPTORS(name, number) \ - SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE) -/*! @brief DMA head descriptor table allocate macro at noncacheable section - * To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, - * user just need to provide the name and the number for the allocate descriptor. - * - * @param name Allocate decriptor name. - * @param number Number of descriptor to be allocated. - */ -#define DMA_ALLOCATE_HEAD_DESCRIPTORS_AT_NONCACHEABLE(name, number) \ - AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE) -/*! @brief DMA link descriptor table allocate macro - * To simplify user interface, this macro will help allocate descriptor memory, - * user just need to provide the name and the number for the allocate descriptor. - * - * @param name Allocate decriptor name. - * @param number Number of descriptor to be allocated. - */ -#define DMA_ALLOCATE_LINK_DESCRIPTORS(name, number) \ - SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE) -/*! @brief DMA link descriptor table allocate macro at noncacheable section - * To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, - * user just need to provide the name and the number for the allocate descriptor. - * - * @param name Allocate decriptor name. - * @param number Number of descriptor to be allocated. - */ -#define DMA_ALLOCATE_LINK_DESCRIPTORS_AT_NONCACHEABLE(name, number) \ - AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE) -/*! @brief DMA transfer buffer address need to align with the transfer width */ -#define DMA_ALLOCATE_DATA_TRANSFER_BUFFER(name, width) SDK_ALIGN(name, width) -/* Channel group consists of 32 channels. channel_group = 0 */ -#define DMA_CHANNEL_GROUP(channel) (((uint8_t)(channel)) >> 5U) -/* Channel index in channel group. channel_index = (channel % (channel number per instance)) */ -#define DMA_CHANNEL_INDEX(base, channel) (((uint8_t)(channel)) & 0x1FU) -/*! @brief DMA linked descriptor address algin size */ -#define DMA_COMMON_REG_GET(base, channel, reg) \ - (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) -#define DMA_COMMON_CONST_REG_GET(base, channel, reg) \ - (((volatile const uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) -#define DMA_COMMON_REG_SET(base, channel, reg, value) \ - (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)] = (value)) - -/*! @brief DMA descriptor end address calculate - * @param start start address - * @param inc address interleave size - * @param bytes transfer bytes - * @param width transfer width - */ -#define DMA_DESCRIPTOR_END_ADDRESS(start, inc, bytes, width) \ - ((uint32_t *)((uint32_t)(start) + (inc) * (bytes) - (inc) * (width))) - -/*! @brief DMA channel transfer configurations macro - * @param reload true is reload link descriptor after current exhaust, false is not - * @param clrTrig true is clear trigger status, wait software trigger, false is not - * @param intA enable interruptA - * @param intB enable interruptB - * @param width transfer width - * @param srcInc source address interleave size - * @param dstInc destination address interleave size - * @param bytes transfer bytes - */ -#define DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes) \ - DMA_CHANNEL_XFERCFG_CFGVALID_MASK | DMA_CHANNEL_XFERCFG_RELOAD(reload) | DMA_CHANNEL_XFERCFG_CLRTRIG(clrTrig) | \ - DMA_CHANNEL_XFERCFG_SETINTA(intA) | DMA_CHANNEL_XFERCFG_SETINTB(intB) | \ - DMA_CHANNEL_XFERCFG_WIDTH(width == 4UL ? 2UL : (width - 1UL)) | \ - DMA_CHANNEL_XFERCFG_SRCINC(srcInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (srcInc - 1UL) : srcInc) | \ - DMA_CHANNEL_XFERCFG_DSTINC(dstInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (dstInc - 1UL) : dstInc) | \ - DMA_CHANNEL_XFERCFG_XFERCOUNT(bytes / width - 1UL) - -/*! @brief _dma_transfer_status DMA transfer status */ -enum -{ - kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the - transfer request. */ -}; - -/*! @brief _dma_addr_interleave_size dma address interleave size */ -enum -{ - kDMA_AddressInterleave0xWidth = 0U, /*!< dma source/destination address no interleave */ - kDMA_AddressInterleave1xWidth = 1U, /*!< dma source/destination address interleave 1xwidth */ - kDMA_AddressInterleave2xWidth = 2U, /*!< dma source/destination address interleave 2xwidth */ - kDMA_AddressInterleave4xWidth = 4U, /*!< dma source/destination address interleave 3xwidth */ -}; - -/*! @brief _dma_transfer_width dma transfer width */ -enum -{ - kDMA_Transfer8BitWidth = 1U, /*!< dma channel transfer bit width is 8 bit */ - kDMA_Transfer16BitWidth = 2U, /*!< dma channel transfer bit width is 16 bit */ - kDMA_Transfer32BitWidth = 4U, /*!< dma channel transfer bit width is 32 bit */ -}; - -/*! @brief DMA descriptor structure */ -typedef struct _dma_descriptor -{ - volatile uint32_t xfercfg; /*!< Transfer configuration */ - void *srcEndAddr; /*!< Last source address of DMA transfer */ - void *dstEndAddr; /*!< Last destination address of DMA transfer */ - void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */ -} dma_descriptor_t; - -/*! @brief DMA transfer configuration */ -typedef struct _dma_xfercfg -{ - bool valid; /*!< Descriptor is ready to transfer */ - bool reload; /*!< Reload channel configuration register after - current descriptor is exhausted */ - bool swtrig; /*!< Perform software trigger. Transfer if fired - when 'valid' is set */ - bool clrtrig; /*!< Clear trigger */ - bool intA; /*!< Raises IRQ when transfer is done and set IRQA status register flag */ - bool intB; /*!< Raises IRQ when transfer is done and set IRQB status register flag */ - uint8_t byteWidth; /*!< Byte width of data to transfer */ - uint8_t srcInc; /*!< Increment source address by 'srcInc' x 'byteWidth' */ - uint8_t dstInc; /*!< Increment destination address by 'dstInc' x 'byteWidth' */ - uint16_t transferCount; /*!< Number of transfers */ -} dma_xfercfg_t; - -/*! @brief DMA channel priority */ -typedef enum _dma_priority -{ - kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */ - kDMA_ChannelPriority1, /*!< Channel priority 1 */ - kDMA_ChannelPriority2, /*!< Channel priority 2 */ - kDMA_ChannelPriority3, /*!< Channel priority 3 */ - kDMA_ChannelPriority4, /*!< Channel priority 4 */ - kDMA_ChannelPriority5, /*!< Channel priority 5 */ - kDMA_ChannelPriority6, /*!< Channel priority 6 */ - kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */ -} dma_priority_t; - -/*! @brief DMA interrupt flags */ -typedef enum _dma_int -{ - kDMA_IntA, /*!< DMA interrupt flag A */ - kDMA_IntB, /*!< DMA interrupt flag B */ - kDMA_IntError, /*!< DMA interrupt flag error */ -} dma_irq_t; - -/*! @brief DMA trigger type*/ -typedef enum _dma_trigger_type -{ - kDMA_NoTrigger = 0, /*!< Trigger is disabled */ - kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */ - kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | - DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */ - kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */ - kDMA_RisingEdgeTrigger = - DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */ -} dma_trigger_type_t; - -/*! @brief _dma_burst_size DMA burst size*/ -enum -{ - kDMA_BurstSize1 = 0U, /*!< burst size 1 transfer */ - kDMA_BurstSize2 = 1U, /*!< burst size 2 transfer */ - kDMA_BurstSize4 = 2U, /*!< burst size 4 transfer */ - kDMA_BurstSize8 = 3U, /*!< burst size 8 transfer */ - kDMA_BurstSize16 = 4U, /*!< burst size 16 transfer */ - kDMA_BurstSize32 = 5U, /*!< burst size 32 transfer */ - kDMA_BurstSize64 = 6U, /*!< burst size 64 transfer */ - kDMA_BurstSize128 = 7U, /*!< burst size 128 transfer */ - kDMA_BurstSize256 = 8U, /*!< burst size 256 transfer */ - kDMA_BurstSize512 = 9U, /*!< burst size 512 transfer */ - kDMA_BurstSize1024 = 10U, /*!< burst size 1024 transfer */ -}; - -/*! @brief DMA trigger burst */ -typedef enum _dma_trigger_burst -{ - kDMA_SingleTransfer = 0, /*!< Single transfer */ - kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */ - kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */ - kDMA_EdgeBurstTransfer2 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */ - kDMA_EdgeBurstTransfer4 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */ - kDMA_EdgeBurstTransfer8 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */ - kDMA_EdgeBurstTransfer16 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */ - kDMA_EdgeBurstTransfer32 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */ - kDMA_EdgeBurstTransfer64 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */ - kDMA_EdgeBurstTransfer128 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */ - kDMA_EdgeBurstTransfer256 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */ - kDMA_EdgeBurstTransfer512 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */ - kDMA_EdgeBurstTransfer1024 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */ -} dma_trigger_burst_t; - -/*! @brief DMA burst wrapping */ -typedef enum _dma_burst_wrap -{ - kDMA_NoWrap = 0, /*!< Wrapping is disabled */ - kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */ - kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */ - kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | - DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */ -} dma_burst_wrap_t; - -/*! @brief DMA transfer type */ -typedef enum _dma_transfer_type -{ - kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */ - kDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory (increment only destination) */ - kDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral (increment only source)*/ - kDMA_StaticToStatic, /*!< Peripheral to static memory (do not increment source or destination) */ -} dma_transfer_type_t; - -/*! @brief DMA channel trigger */ -typedef struct _dma_channel_trigger -{ - dma_trigger_type_t type; /*!< Select hardware trigger as edge triggered or level triggered. */ - dma_trigger_burst_t burst; /*!< Select whether hardware triggers cause a single or burst transfer. */ - dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */ -} dma_channel_trigger_t; - -/*! @brief DMA channel trigger */ -typedef struct _dma_channel_config -{ - void *srcStartAddr; /*!< Source data address */ - void *dstStartAddr; /*!< Destination data address */ - void *nextDesc; /*!< Chain custom descriptor */ - uint32_t xferCfg; /*!< channel transfer configurations */ - dma_channel_trigger_t *trigger; /*!< DMA trigger type */ - bool isPeriph; /*!< select the request type */ -} dma_channel_config_t; - -/*! @brief DMA transfer configuration */ -typedef struct _dma_transfer_config -{ - uint8_t *srcAddr; /*!< Source data address */ - uint8_t *dstAddr; /*!< Destination data address */ - uint8_t *nextDesc; /*!< Chain custom descriptor */ - dma_xfercfg_t xfercfg; /*!< Transfer options */ - bool isPeriph; /*!< DMA transfer is driven by peripheral */ -} dma_transfer_config_t; - -/*! @brief Callback for DMA */ -struct _dma_handle; - -/*! @brief Define Callback function for DMA. */ -typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode); - -/*! @brief DMA transfer handle structure */ -typedef struct _dma_handle -{ - dma_callback callback; /*!< Callback function. Invoked when transfer - of descriptor with interrupt flag finishes */ - void *userData; /*!< Callback function parameter */ - DMA_Type *base; /*!< DMA peripheral base address */ - uint8_t channel; /*!< DMA channel number */ -} dma_handle_t; - -/******************************************************************************* - * APIs - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name DMA initialization and De-initialization - * @{ - */ - -/*! - * @brief Initializes DMA peripheral. - * - * This function enable the DMA clock, set descriptor table and - * enable DMA peripheral. - * - * @param base DMA peripheral base address. - */ -void DMA_Init(DMA_Type *base); - -/*! - * @brief Deinitializes DMA peripheral. - * - * This function gates the DMA clock. - * - * @param base DMA peripheral base address. - */ -void DMA_Deinit(DMA_Type *base); - -/*! - * @brief Install DMA descriptor memory. - * - * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong - * transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has - * a default DMA descriptor buffer, but it support one DMA descriptor for one channel only. - * - * @param base DMA base address. - * @param addr DMA descriptor address - */ -void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr); - -/* @} */ - -/*! - * @name DMA Channel Operation - * @{ - */ - -/*! - * @brief Return whether DMA channel is processing transfer - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return True for active state, false otherwise. - */ -static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - - return (DMA_COMMON_CONST_REG_GET(base, channel, ACTIVE) & (1UL << DMA_CHANNEL_INDEX(base, channel))) != 0UL; -} - -/*! - * @brief Return whether DMA channel is busy - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return True for busy state, false otherwise. - */ -static inline bool DMA_ChannelIsBusy(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - - return (DMA_COMMON_CONST_REG_GET(base, channel, BUSY) & (1UL << DMA_CHANNEL_INDEX(base, channel))) != 0UL; -} - -/*! - * @brief Enables the interrupt source for the DMA transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - DMA_COMMON_REG_GET(base, channel, INTENSET) |= 1UL << DMA_CHANNEL_INDEX(base, channel); -} - -/*! - * @brief Disables the interrupt source for the DMA transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - DMA_COMMON_REG_GET(base, channel, INTENCLR) |= 1UL << DMA_CHANNEL_INDEX(base, channel); -} - -/*! - * @brief Enable DMA channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - DMA_COMMON_REG_GET(base, channel, ENABLESET) |= 1UL << DMA_CHANNEL_INDEX(base, channel); -} - -/*! - * @brief Disable DMA channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - DMA_COMMON_REG_GET(base, channel, ENABLECLR) |= 1UL << DMA_CHANNEL_INDEX(base, channel); -} - -/*! - * @brief Set PERIPHREQEN of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK; -} - -/*! - * @brief Get PERIPHREQEN value of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return True for enabled PeriphRq, false for disabled. - */ -static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK; -} - -/*! - * @brief Set trigger settings of DMA channel. - * @deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param trigger trigger configuration. - */ -void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger); - -/*! - * @brief set channel config. - * - * This function provide a interface to configure channel configuration reisters. - * - * @param base DMA base address. - * @param channel DMA channel number. - * @param trigger channel configurations structure. - * @param isPeriph true is periph request, false is not. - */ -void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph); - -/*! - * @brief Gets the remaining bytes of the current DMA descriptor transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return The number of bytes which have not been transferred yet. - */ -uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel); - -/*! - * @brief Set priority of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param priority Channel priority value. - */ -static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - base->CHANNEL[channel].CFG = - (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority); -} - -/*! - * @brief Get priority of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return Channel priority value. - */ -static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - return (dma_priority_t)(uint8_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> - DMA_CHANNEL_CFG_CHPRIORITY_SHIFT); -} - -/*! - * @brief Set channel configuration valid. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_SetChannelConfigValid(DMA_Type *base, uint32_t channel) -{ - base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_CFGVALID_MASK; -} - -/*! - * @brief Do software trigger for the channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DoChannelSoftwareTrigger(DMA_Type *base, uint32_t channel) -{ - base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; -} - -/*! - * @brief Load channel transfer configurations. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param xfer transfer configurations. - */ -static inline void DMA_LoadChannelTransferConfig(DMA_Type *base, uint32_t channel, uint32_t xfer) -{ - base->CHANNEL[channel].XFERCFG = xfer; -} - -/*! - * @brief Create application specific DMA descriptor - * to be used in a chain in transfer - * @deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor. - * @param desc DMA descriptor address. - * @param xfercfg Transfer configuration for DMA descriptor. - * @param srcAddr Address of last item to transmit - * @param dstAddr Address of last item to receive. - * @param nextDesc Address of next descriptor in chain. - */ -void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc); - -/*! - * @brief setup dma descriptor - * - * Note: This function do not support configure wrap descriptor. - * - * @param desc DMA descriptor address. - * @param xfercfg Transfer configuration for DMA descriptor. - * @param srcStartAddr Start address of source address. - * @param dstStartAddr Start address of destination address. - * @param nextDesc Address of next descriptor in chain. - */ -void DMA_SetupDescriptor( - dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc); - -/*! - * @brief setup dma channel descriptor - * - * Note: This function support configure wrap descriptor. - * - * @param desc DMA descriptor address. - * @param xfercfg Transfer configuration for DMA descriptor. - * @param srcStartAddr Start address of source address. - * @param dstStartAddr Start address of destination address. - * @param nextDesc Address of next descriptor in chain. - * @param wrapType burst wrap type. - * @param burstSize burst size, reference _dma_burst_size. - */ -void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, - uint32_t xfercfg, - void *srcStartAddr, - void *dstStartAddr, - void *nextDesc, - dma_burst_wrap_t wrapType, - uint32_t burstSize); - -/*! - * @brief load channel transfer decriptor. - * - * This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA - * transfer, the head descriptor table is defined in DMA driver, it is useful for the case: - * 1. for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly - * and then call this api to load the configured descriptor to driver descriptor table. - * @code - * DMA_Init(DMA0); - * DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL); - * DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL); - * DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc); - * DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL); - * while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL)) - * {} - * @endcode - * - * @param base DMA base address. - * @param channel DMA channel. - * @param descriptor configured DMA descriptor. - */ -void DMA_LoadChannelDescriptor(DMA_Type *base, uint32_t channel, dma_descriptor_t *descriptor); - -/* @} */ - -/*! - * @name DMA Transactional Operation - * @{ - */ - -/*! - * @brief Abort running transfer by handle. - * - * This function aborts DMA transfer specified by handle. - * - * @param handle DMA handle pointer. - */ -void DMA_AbortTransfer(dma_handle_t *handle); - -/*! - * @brief Creates the DMA handle. - * - * This function is called if using transaction API for DMA. This function - * initializes the internal state of DMA handle. - * - * @param handle DMA handle pointer. The DMA handle stores callback function and - * parameters. - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel); - -/*! - * @brief Installs a callback function for the DMA transfer. - * - * This callback is called in DMA IRQ handler. Use the callback to do something after - * the current major loop transfer completes. - * - * @param handle DMA handle pointer. - * @param callback DMA callback function pointer. - * @param userData Parameter for callback function. - */ -void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData); - -/*! - * @brief Prepares the DMA transfer structure. - * @deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer. - * This function prepares the transfer configuration structure according to the user input. - * - * @param config The user configuration structure of type dma_transfer_t. - * @param srcAddr DMA transfer source address. - * @param dstAddr DMA transfer destination address. - * @param byteWidth DMA transfer destination address width(bytes). - * @param transferBytes DMA transfer bytes to be transferred. - * @param type DMA transfer type. - * @param nextDesc Chain custom descriptor to transfer. - * @note The data address and the data width must be consistent. For example, if the SRC - * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in - * source address error(SAE). - */ -void DMA_PrepareTransfer(dma_transfer_config_t *config, - void *srcAddr, - void *dstAddr, - uint32_t byteWidth, - uint32_t transferBytes, - dma_transfer_type_t type, - void *nextDesc); - -/*! - * @brief Prepare channel transfer configurations. - * - * This function used to prepare channel transfer configurations. - * - * @param config Pointer to DMA channel transfer configuration structure. - * @param srcStartAddr source start address. - * @param dstStartAddr destination start address. - * @param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * @param type transfer type. - * @param trigger DMA channel trigger configurations. - * @param nextDesc address of next descriptor. - */ -void DMA_PrepareChannelTransfer(dma_channel_config_t *config, - void *srcStartAddr, - void *dstStartAddr, - uint32_t xferCfg, - dma_transfer_type_t type, - dma_channel_trigger_t *trigger, - void *nextDesc); - -/*! - * @brief Submits the DMA transfer request. - * @deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * - * @param handle DMA handle pointer. - * @param config Pointer to DMA transfer configuration structure. - * @retval kStatus_DMA_Success It means submit transfer request succeed. - * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config); - -/*! - * @brief Submit channel transfer paramter directly. - * - * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table - * is defined in DMA driver, it is useful for the case: - * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used - for it. - * @code - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, - bytes), srcStartAddr, dstStartAddr, NULL); - DMA_StartTransfer(handle) - * @endcode - * - * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is - required, then application should prepare - * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * @code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc2); - DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, NULL); - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, - bytes), srcStartAddr, dstStartAddr, nextDesc0); - DMA_StartTransfer(handle); - * @endcode - * - * @param handle Pointer to DMA handle. - * @param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * @param srcStartAddr source start address. - * @param dstStartAddr destination start address. - * @param nextDesc address of next descriptor. - */ -void DMA_SubmitChannelTransferParameter( - dma_handle_t *handle, uint32_t xferCfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc); - -/*! - * @brief Submit channel descriptor. - * - * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table - is defined in - * DMA driver, this functiono is typical for the ping pong case: - * - * 1. for the ping pong case, application should responsible for the descriptor, for example, application should - * prepare two descriptor table with macro. - * @code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc0); - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelDescriptor(handle, nextDesc0); - DMA_StartTransfer(handle); - * @endcode - * - * @param handle Pointer to DMA handle. - * @param descriptor descriptor to submit. - */ -void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descriptor); - -/*! - * @brief Submits the DMA channel transfer request. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * It is used for the case: - * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used - for it. - * @code - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,NULL); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * @endcode - * - * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is - required, then application should prepare - * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * @code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc2); - DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, NULL); - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * @endcode - * - * 3. for the ping pong case, application should responsible for link descriptor, for example, application should - prepare - * two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * @code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc0); - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * @endcode - * @param handle DMA handle pointer. - * @param config Pointer to DMA transfer configuration structure. - * @retval kStatus_DMA_Success It means submit transfer request succeed. - * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config); - -/*! - * @brief DMA start transfer. - * - * This function enables the channel request. User can call this function after submitting the transfer request - * It will trigger transfer start with software trigger only when hardware trigger is not used. - * - * @param handle DMA handle pointer. - */ -void DMA_StartTransfer(dma_handle_t *handle); - -/*! - * @brief DMA IRQ handler for descriptor transfer complete. - * - * This function clears the channel major interrupt flag and call - * the callback function if it is not NULL. - * - * @param base DMA base address. - */ -void DMA_IRQHandle(DMA_Type *base); - -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/* @} */ - -#endif /*_FSL_DMA_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_flexcomm.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_flexcomm.c deleted file mode 100644 index 7a21a1ce0ea..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_flexcomm.c +++ /dev/null @@ -1,412 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm" -#endif - -/*! - * @brief Used for conversion between `void*` and `uint32_t`. - */ -typedef union pvoid_to_u32 -{ - void *pvoid; - uint32_t u32; -} pvoid_to_u32_t; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! @brief Set the FLEXCOMM mode . */ -static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock); - -/*! @brief check whether flexcomm supports peripheral type */ -static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map FLEXCOMM instance number to base address. */ -static const uint32_t s_flexcommBaseAddrs[] = FLEXCOMM_BASE_ADDRS; - -/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ -static flexcomm_irq_handler_t s_flexcommIrqHandler[ARRAY_SIZE(s_flexcommBaseAddrs)]; - -/*! @brief Pointers to handles for each instance to provide context to interrupt routines */ -static void *s_flexcommHandle[ARRAY_SIZE(s_flexcommBaseAddrs)]; - -/*! @brief Array to map FLEXCOMM instance number to IRQ number. */ -IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief IDs of clock for each FLEXCOMM module */ -static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) -/*! @brief Pointers to FLEXCOMM resets for each instance. */ -static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* check whether flexcomm supports peripheral type */ -static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph) -{ - if (periph == FLEXCOMM_PERIPH_NONE) - { - return true; - } - else if (periph <= FLEXCOMM_PERIPH_I2S_TX) - { - return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false; - } - else if (periph == FLEXCOMM_PERIPH_I2S_RX) - { - return (base->PSELID & (1U << 7U)) > (uint32_t)0U ? true : false; - } - else - { - return false; - } -} - -/* Get the index corresponding to the FLEXCOMM */ -/*! brief Returns instance number for FLEXCOMM module with given base address. */ -uint32_t FLEXCOMM_GetInstance(void *base) -{ - uint32_t i; - pvoid_to_u32_t BaseAddr; - BaseAddr.pvoid = base; - - for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++) - { - if (BaseAddr.u32 == s_flexcommBaseAddrs[i]) - { - break; - } - } - - assert(i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT); - return i; -} - -/* Changes FLEXCOMM mode */ -static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock) -{ - /* Check whether peripheral type is present */ - if (!FLEXCOMM_PeripheralIsPresent(base, periph)) - { - return kStatus_OutOfRange; - } - - /* Flexcomm is locked to different peripheral type than expected */ - if (((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) != 0U) && - ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph)) - { - return kStatus_Fail; - } - - /* Check if we are asked to lock */ - if (lock != 0) - { - base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK; - } - else - { - base->PSELID = (uint32_t)periph; - } - - return kStatus_Success; -} - -/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ -status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) -{ - uint32_t idx = FLEXCOMM_GetInstance(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the peripheral clock */ - CLOCK_EnableClock(s_flexcommClocks[idx]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) - /* Reset the FLEXCOMM module */ - RESET_PeripheralReset(s_flexcommResets[idx]); -#endif - - /* Set the FLEXCOMM to given peripheral */ - return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0); -} - -/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM - * mode */ -void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(base); - - /* Clear handler first to avoid execution of the handler with wrong handle */ - s_flexcommIrqHandler[instance] = NULL; - s_flexcommHandle[instance] = flexcommHandle; - s_flexcommIrqHandler[instance] = handler; - SDK_ISR_EXIT_BARRIER; -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(FLEXCOMM0) -void FLEXCOMM0_DriverIRQHandler(void); -void FLEXCOMM0_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM0); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM1) -void FLEXCOMM1_DriverIRQHandler(void); -void FLEXCOMM1_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM1); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM2) -void FLEXCOMM2_DriverIRQHandler(void); -void FLEXCOMM2_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM2); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM3) -void FLEXCOMM3_DriverIRQHandler(void); -void FLEXCOMM3_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM3); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM4) -void FLEXCOMM4_DriverIRQHandler(void); -void FLEXCOMM4_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM4); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} - -#endif - -#if defined(FLEXCOMM5) -void FLEXCOMM5_DriverIRQHandler(void); -void FLEXCOMM5_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM5); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM6) -void FLEXCOMM6_DriverIRQHandler(void); -void FLEXCOMM6_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM6); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM7) -void FLEXCOMM7_DriverIRQHandler(void); -void FLEXCOMM7_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM7); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM8) -void FLEXCOMM8_DriverIRQHandler(void); -void FLEXCOMM8_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM8); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM9) -void FLEXCOMM9_DriverIRQHandler(void); -void FLEXCOMM9_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM9); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM10) -void FLEXCOMM10_DriverIRQHandler(void); -void FLEXCOMM10_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM10); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM11) -void FLEXCOMM11_DriverIRQHandler(void); -void FLEXCOMM11_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM11); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM12) -void FLEXCOMM12_DriverIRQHandler(void); -void FLEXCOMM12_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM12); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM13) -void FLEXCOMM13_DriverIRQHandler(void); -void FLEXCOMM13_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM13); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM14) -void FLEXCOMM14_DriverIRQHandler(void); -void FLEXCOMM14_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM14); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM15) -void FLEXCOMM15_DriverIRQHandler(void); -void FLEXCOMM15_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM15); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM16) -void FLEXCOMM16_DriverIRQHandler(void); -void FLEXCOMM16_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM16); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_flexcomm.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_flexcomm.h deleted file mode 100644 index f96086fdecc..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_flexcomm.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_FLEXCOMM_H_ -#define _FSL_FLEXCOMM_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup flexcomm_driver - * @{ - */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FlexCOMM driver version 2.0.2. */ -#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -/*! @brief FLEXCOMM peripheral modes. */ -typedef enum -{ - FLEXCOMM_PERIPH_NONE, /*!< No peripheral */ - FLEXCOMM_PERIPH_USART, /*!< USART peripheral */ - FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */ - FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */ - FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */ - FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */ -} FLEXCOMM_PERIPH_T; - -/*! @brief Typedef for interrupt handler. */ -typedef void (*flexcomm_irq_handler_t)(void *base, void *handle); - -/*! @brief Array with IRQ number for each FLEXCOMM module. */ -extern IRQn_Type const kFlexcommIrqs[]; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @brief Returns instance number for FLEXCOMM module with given base address. */ -uint32_t FLEXCOMM_GetInstance(void *base); - -/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ -status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph); - -/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM - * mode */ -void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle); - -#if defined(__cplusplus) -} -#endif - -/*@}*/ - -#endif /* _FSL_FLEXCOMM_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_fro_calib.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_fro_calib.h deleted file mode 100644 index 9662444a526..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_fro_calib.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2017, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_FRO_CALIB_H_ -#define _FSL_FRO_CALIB_H_ - -#include "fsl_common.h" -#include "fsl_device_registers.h" -#include - -/*! - * @addtogroup power - * @{ - */ -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FRO_CALIB driver version 1.0.0. */ -#define FSL_FRO_CALIB_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) -/*@}*/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.fro_calib" -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Returns the version of the FRO Calibration library */ -unsigned int fro_calib_Get_Lib_Ver(void); - -/* ctimer instance */ -/* ctimer clock frquency in KHz */ -void Chip_TIMER_Instance_Freq(CTIMER_Type *base, unsigned int ctimerFreq); - -/* USB_SOF_Event */ -/* Application software should be written to make sure the USB_SOF_EVENT() is */ -/* being called with lower interrupt latency for calibration to work properly */ -void USB_SOF_Event(void); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* _FSL_FRO_CALIB_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_gint.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_gint.c deleted file mode 100644 index 9dc2e5eff0d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_gint.c +++ /dev/null @@ -1,372 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_gint.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.gint" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to GINT bases for each instance. */ -static GINT_Type *const s_gintBases[FSL_FEATURE_SOC_GINT_COUNT] = GINT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Clocks for each instance. */ -static const clock_ip_name_t s_gintClocks[FSL_FEATURE_SOC_GINT_COUNT] = GINT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -/*! @brief Resets for each instance. */ -static const reset_ip_name_t s_gintResets[FSL_FEATURE_SOC_GINT_COUNT] = GINT_RSTS; -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/* @brief Irq number for each instance */ -static const IRQn_Type s_gintIRQ[FSL_FEATURE_SOC_GINT_COUNT] = GINT_IRQS; - -/*! @brief Callback function array for GINT(s). */ -static gint_cb_t s_gintCallback[FSL_FEATURE_SOC_GINT_COUNT]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t GINT_GetInstance(GINT_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_gintBases); instance++) - { - if (s_gintBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_gintBases)); - - return instance; -} - -/*! - * brief Initialize GINT peripheral. - - * This function initializes the GINT peripheral and enables the clock. - * - * param base Base address of the GINT peripheral. - * - * retval None. - */ -void GINT_Init(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - s_gintCallback[instance] = NULL; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the peripheral clock */ - CLOCK_EnableClock(s_gintClocks[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_gintResets[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -} - -/*! - * brief Setup GINT peripheral control parameters. - - * This function sets the control parameters of GINT peripheral. - * - * param base Base address of the GINT peripheral. - * param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. - * param trig Controls if the enabled inputs are level or edge sensitive based on polarity. - * param callback This function is called when configured group interrupt is generated. - * - * retval None. - */ -void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - base->CTRL = (GINT_CTRL_COMB(comb) | GINT_CTRL_TRIG(trig)); - - /* Save callback pointer */ - s_gintCallback[instance] = callback; -} - -/*! - * brief Get GINT peripheral control parameters. - - * This function returns the control parameters of GINT peripheral. - * - * param base Base address of the GINT peripheral. - * param comb Pointer to store combine input value. - * param trig Pointer to store trigger value. - * param callback Pointer to store callback function. - * - * retval None. - */ -void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback) -{ - uint32_t instance; - uint32_t combValue; - uint32_t trigValue; - - instance = GINT_GetInstance(base); - - combValue = (base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT; - *comb = (gint_comb_t)combValue; - trigValue = (base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT; - *trig = (gint_trig_t)trigValue; - *callback = s_gintCallback[instance]; -} - -/*! - * brief Configure GINT peripheral pins. - - * This function enables and controls the polarity of enabled pin(s) of a given port. - * - * param base Base address of the GINT peripheral. - * param port Port number. - * param polarityMask Each bit position selects the polarity of the corresponding enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * param enableMask Each bit position selects if the corresponding pin is enabled or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * retval None. - */ -void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask) -{ - base->PORT_POL[port] = polarityMask; - base->PORT_ENA[port] = enableMask; -} - -/*! - * brief Get GINT peripheral pin configuration. - - * This function returns the pin configuration of a given port. - * - * param base Base address of the GINT peripheral. - * param port Port number. - * param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding - enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled - or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * retval None. - */ -void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask) -{ - *polarityMask = base->PORT_POL[port]; - *enableMask = base->PORT_ENA[port]; -} - -/*! - * brief Enable callback. - - * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * param base Base address of the GINT peripheral. - * - * retval None. - */ -void GINT_EnableCallback(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - /* If GINT is configured in "AND" mode a spurious interrupt is generated. - Clear status and pending interrupt before enabling the irq in NVIC. */ - GINT_ClrStatus(base); - NVIC_ClearPendingIRQ(s_gintIRQ[instance]); - (void)EnableIRQ(s_gintIRQ[instance]); -} - -/*! - * brief Disable callback. - - * This function disables the interrupt for the selected GINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * param base Base address of the peripheral. - * - * retval None. - */ -void GINT_DisableCallback(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - (void)DisableIRQ(s_gintIRQ[instance]); - GINT_ClrStatus(base); - NVIC_ClearPendingIRQ(s_gintIRQ[instance]); -} - -/*! - * brief Deinitialize GINT peripheral. - - * This function disables the GINT clock. - * - * param base Base address of the GINT peripheral. - * - * retval None. - */ -void GINT_Deinit(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - /* Cleanup */ - GINT_DisableCallback(base); - s_gintCallback[instance] = NULL; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_gintResets[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the peripheral clock */ - CLOCK_DisableClock(s_gintClocks[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(GINT0) -void GINT0_DriverIRQHandler(void); -void GINT0_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[0]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[0] != NULL) - { - s_gintCallback[0](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT1) -void GINT1_DriverIRQHandler(void); -void GINT1_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[1]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[1] != NULL) - { - s_gintCallback[1](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT2) -void GINT2_DriverIRQHandler(void); -void GINT2_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[2]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[2] != NULL) - { - s_gintCallback[2](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT3) -void GINT3_DriverIRQHandler(void); -void GINT3_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[3]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[3] != NULL) - { - s_gintCallback[3](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT4) -void GINT4_DriverIRQHandler(void); -void GINT4_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[4]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[4] != NULL) - { - s_gintCallback[4](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT5) -void GINT5_DriverIRQHandler(void); -void GINT5_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[5]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[5] != NULL) - { - s_gintCallback[5](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT6) -void GINT6_DriverIRQHandler(void); -void GINT6_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[6]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[6] != NULL) - { - s_gintCallback[6](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT7) -void GINT7_DriverIRQHandler(void); -void GINT7_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[7]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[7] != NULL) - { - s_gintCallback[7](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_gint.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_gint.h deleted file mode 100644 index adc301a9e0d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_gint.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_GINT_H_ -#define _FSL_GINT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup gint_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3. */ -/*@}*/ - -/*! @brief GINT combine inputs type */ -typedef enum _gint_comb -{ - kGINT_CombineOr = 0U, /*!< A grouped interrupt is generated when any one of the enabled inputs is active */ - kGINT_CombineAnd = 1U /*!< A grouped interrupt is generated when all enabled inputs are active */ -} gint_comb_t; - -/*! @brief GINT trigger type */ -typedef enum _gint_trig -{ - kGINT_TrigEdge = 0U, /*!< Edge triggered based on polarity */ - kGINT_TrigLevel = 1U /*!< Level triggered based on polarity */ -} gint_trig_t; - -/* @brief GINT port type */ -typedef enum _gint_port -{ - kGINT_Port0 = 0U, - kGINT_Port1 = 1U, -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 2U) - kGINT_Port2 = 2U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 3U) - kGINT_Port3 = 3U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 4U) - kGINT_Port4 = 4U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 5U) - kGINT_Port5 = 5U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 6U) - kGINT_Port6 = 6U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 7U) - kGINT_Port7 = 7U, -#endif -} gint_port_t; - -/*! @brief GINT Callback function. */ -typedef void (*gint_cb_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize GINT peripheral. - - * This function initializes the GINT peripheral and enables the clock. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_Init(GINT_Type *base); - -/*! - * @brief Setup GINT peripheral control parameters. - - * This function sets the control parameters of GINT peripheral. - * - * @param base Base address of the GINT peripheral. - * @param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. - * @param trig Controls if the enabled inputs are level or edge sensitive based on polarity. - * @param callback This function is called when configured group interrupt is generated. - * - * @retval None. - */ -void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback); - -/*! - * @brief Get GINT peripheral control parameters. - - * This function returns the control parameters of GINT peripheral. - * - * @param base Base address of the GINT peripheral. - * @param comb Pointer to store combine input value. - * @param trig Pointer to store trigger value. - * @param callback Pointer to store callback function. - * - * @retval None. - */ -void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback); - -/*! - * @brief Configure GINT peripheral pins. - - * This function enables and controls the polarity of enabled pin(s) of a given port. - * - * @param base Base address of the GINT peripheral. - * @param port Port number. - * @param polarityMask Each bit position selects the polarity of the corresponding enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * @param enableMask Each bit position selects if the corresponding pin is enabled or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * @retval None. - */ -void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask); - -/*! - * @brief Get GINT peripheral pin configuration. - - * This function returns the pin configuration of a given port. - * - * @param base Base address of the GINT peripheral. - * @param port Port number. - * @param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding - enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * @param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled - or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * @retval None. - */ -void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask); - -/*! - * @brief Enable callback. - - * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_EnableCallback(GINT_Type *base); - -/*! - * @brief Disable callback. - - * This function disables the interrupt for the selected GINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * @param base Base address of the peripheral. - * - * @retval None. - */ -void GINT_DisableCallback(GINT_Type *base); - -/*! - * @brief Clear GINT status. - - * This function clears the GINT status bit. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -static inline void GINT_ClrStatus(GINT_Type *base) -{ - base->CTRL |= GINT_CTRL_INT_MASK; -} - -/*! - * @brief Get GINT status. - - * This function returns the GINT status. - * - * @param base Base address of the GINT peripheral. - * - * @retval status = 0 No group interrupt request. = 1 Group interrupt request active. - */ -static inline uint32_t GINT_GetStatus(GINT_Type *base) -{ - return (base->CTRL & GINT_CTRL_INT_MASK); -} - -/*! - * @brief Deinitialize GINT peripheral. - - * This function disables the GINT clock. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_Deinit(GINT_Type *base); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_GINT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_gpio.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_gpio.c deleted file mode 100644 index be100d5e9e3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_gpio.c +++ /dev/null @@ -1,317 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_gpio.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map FGPIO instance number to clock name. */ -static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) -/*! @brief Pointers to GPIO resets for each instance. */ -static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N; -#endif -/******************************************************************************* - * Prototypes - ************ ******************************************************************/ -/*! - * @brief Enable GPIO port clock. - * - * @param base GPIO peripheral base pointer. - * @param port GPIO port number. - */ -static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port); - -/******************************************************************************* - * Code - ******************************************************************************/ -static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - assert(port < ARRAY_SIZE(s_gpioClockName)); - - /* Upgate the GPIO clock */ - CLOCK_EnableClock(s_gpioClockName[port]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Initializes the GPIO peripheral. - * - * This function ungates the GPIO clock. - * - * param base GPIO peripheral base pointer. - * param port GPIO port number. - */ -void GPIO_PortInit(GPIO_Type *base, uint32_t port) -{ - GPIO_EnablePortClock(base, port); - -#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) - /* Reset the GPIO module */ - RESET_PeripheralReset(s_gpioResets[port]); -#endif -} - -/*! - * brief Initializes a GPIO pin used by the board. - * - * To initialize the GPIO, define a pin configuration, either input or output, in the user file. - * Then, call the GPIO_PinInit() function. - * - * This is an example to define an input pin or output pin configuration: - * code - * Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * endcode - * - * param base GPIO peripheral base pointer(Typically GPIO) - * param port GPIO port number - * param pin GPIO pin number - * param config GPIO pin configuration pointer - */ -void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) -{ - GPIO_EnablePortClock(base, port); - - if (config->pinDirection == kGPIO_DigitalInput) - { -#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) - base->DIRCLR[port] = 1UL << pin; -#else - base->DIR[port] &= ~(1UL << pin); -#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ - } - else - { - /* Set default output value */ - if (config->outputLogic == 0U) - { - base->CLR[port] = (1UL << pin); - } - else - { - base->SET[port] = (1UL << pin); - } -/* Set pin direction */ -#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) - base->DIRSET[port] = 1UL << pin; -#else - base->DIR[port] |= 1UL << pin; -#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ - } -} - -#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT -/*! - * @brief Set the configuration of pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param pin GPIO pin number. - * @param config GPIO pin interrupt configuration.. - */ -void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config) -{ - base->INTEDG[port] = (base->INTEDG[port] & ~(1UL << pin)) | ((uint32_t)config->mode << pin); - - base->INTPOL[port] = (base->INTPOL[port] & ~(1UL << pin)) | ((uint32_t)config->polarity << pin); -} - -/*! - * @brief Enables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] | mask; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] | mask; - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Disables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] & ~mask; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] & ~mask; - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Clears multiple pins interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTSTATA[port] = mask; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTSTATB[port] = mask; - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @ Read port interrupt status. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param index GPIO interrupt number. - * @retval masked GPIO status value - */ -uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index) -{ - uint32_t status = 0U; - - if ((uint32_t)kGPIO_InterruptA == index) - { - status = base->INTSTATA[port]; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - status = base->INTSTATB[port]; - } - else - { - /*Should not enter here*/ - } - return status; -} - -/*! - * @brief Enables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] | (1UL << pin); - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] | (1UL << pin); - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Disables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] & ~(1UL << pin); - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] & ~(1UL << pin); - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Clears the specific pin interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTSTATA[port] = 1UL << pin; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTSTATB[port] = 1UL << pin; - } - else - { - /*Should not enter here*/ - } -} -#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_gpio.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_gpio.h deleted file mode 100644 index 50a33f89208..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_gpio.h +++ /dev/null @@ -1,364 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _LPC_GPIO_H_ -#define _LPC_GPIO_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_gpio - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPC GPIO driver version. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 7)) -/*@}*/ - -/*! @brief LPC GPIO direction definition */ -typedef enum _gpio_pin_direction -{ - kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ - kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ -} gpio_pin_direction_t; - -/*! - * @brief The GPIO pin configuration structure. - * - * Every pin can only be configured as either output pin or input pin at a time. - * If configured as a input pin, then leave the outputConfig unused. - */ -typedef struct _gpio_pin_config -{ - gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ - /* Output configurations, please ignore if configured as a input one */ - uint8_t outputLogic; /*!< Set default output logic, no use in input */ -} gpio_pin_config_t; - -#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT) -#define GPIO_PIN_INT_LEVEL 0x00U -#define GPIO_PIN_INT_EDGE 0x01U - -#define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U -#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U - -/*! @brief GPIO Pin Interrupt enable mode */ -typedef enum _gpio_pin_enable_mode -{ - kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */ - kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE /*!< Generate Pin Interrupt on edge mode */ -} gpio_pin_enable_mode_t; - -/*! @brief GPIO Pin Interrupt enable polarity */ -typedef enum _gpio_pin_enable_polarity -{ - kGPIO_PinIntEnableHighOrRise = - PINT_PIN_INT_HIGH_OR_RISE_TRIGGER, /*!< Generate Pin Interrupt on high level or rising edge */ - kGPIO_PinIntEnableLowOrFall = - PINT_PIN_INT_LOW_OR_FALL_TRIGGER /*!< Generate Pin Interrupt on low level or falling edge */ -} gpio_pin_enable_polarity_t; - -/*! @brief LPC GPIO interrupt index definition */ -typedef enum _gpio_interrupt_index -{ - kGPIO_InterruptA = 0U, /*!< Set current pin as interrupt A*/ - kGPIO_InterruptB = 1U, /*!< Set current pin as interrupt B*/ -} gpio_interrupt_index_t; - -/*! @brief Configures the interrupt generation condition. */ -typedef struct _gpio_interrupt_config -{ - uint8_t mode; /* The trigger mode of GPIO interrupts */ - uint8_t polarity; /* The polarity of GPIO interrupts */ -} gpio_interrupt_config_t; -#endif - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @name GPIO Configuration */ -/*@{*/ - -/*! - * @brief Initializes the GPIO peripheral. - * - * This function ungates the GPIO clock. - * - * @param base GPIO peripheral base pointer. - * @param port GPIO port number. - */ -void GPIO_PortInit(GPIO_Type *base, uint32_t port); - -/*! - * @brief Initializes a GPIO pin used by the board. - * - * To initialize the GPIO, define a pin configuration, either input or output, in the user file. - * Then, call the GPIO_PinInit() function. - * - * This is an example to define an input pin or output pin configuration: - * @code - * Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * @endcode - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @param config GPIO pin configuration pointer - */ -void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config); - -/*@}*/ - -/*! @name GPIO Output Operations */ -/*@{*/ - -/*! - * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @param output GPIO pin output logic level. - * - 0: corresponding pin output low-logic level. - * - 1: corresponding pin output high-logic level. - */ -static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) -{ - base->B[port][pin] = output; -} - -/*@}*/ -/*! @name GPIO Input Operations */ -/*@{*/ - -/*! - * @brief Reads the current input value of the GPIO PIN. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @retval GPIO port input value - * - 0: corresponding pin input low-logic level. - * - 1: corresponding pin input high-logic level. - */ -static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) -{ - return (uint32_t)base->B[port][pin]; -} - -/*@}*/ - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 1. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->SET[port] = mask; -} - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 0. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->CLR[port] = mask; -} - -/*! - * @brief Reverses current output logic of the multiple GPIO pins. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->NOT[port] = mask; -} - -/*@}*/ - -/*! - * @brief Reads the current input value of the whole GPIO port. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - */ -static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port) -{ - return (uint32_t)base->PIN[port]; -} - -/*@}*/ -/*! @name GPIO Mask Operations */ -/*@{*/ - -/*! - * @brief Sets port mask, 0 - enable pin, 1 - disable pin. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->MASK[port] = mask; -} - -/*! - * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param output GPIO port output value. - */ -static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output) -{ - base->MPIN[port] = output; -} - -/*! - * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be - * affected. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @retval masked GPIO port value - */ -static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) -{ - return (uint32_t)base->MPIN[port]; -} - -#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT -/*! - * @brief Set the configuration of pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param pin GPIO pin number. - * @param config GPIO pin interrupt configuration.. - */ -void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config); - -/*! - * @brief Enables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); - -/*! - * @brief Disables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); - -/*! - * @brief Clears pin interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); - -/*! - * @ Read port interrupt status. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param index GPIO interrupt number. - * @retval masked GPIO status value - */ -uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index); - -/*! - * @brief Enables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); - -/*! - * @brief Disables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); - -/*! - * @brief Clears the specific pin interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); - -#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* _LPC_GPIO_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_hashcrypt.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_hashcrypt.c deleted file mode 100644 index 85943dcfdd3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_hashcrypt.c +++ /dev/null @@ -1,1726 +0,0 @@ -/* - * Copyright 2017-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_hashcrypt.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.hashcrypt" -#endif - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*!< SHA-1 and SHA-256 block size */ -#define SHA_BLOCK_SIZE 64U -/*!< max number of blocks that can be proccessed in one run (master mode) */ -#define SHA_MASTER_MAX_BLOCKS 2048U - -/*!< Use standard C library memcpy */ -#define hashcrypt_memcpy memcpy - -/*! Internal states of the HASH creation process */ -typedef enum _hashcrypt_sha_algo_state -{ - kHASHCRYPT_HashInit = 1u, /*!< Init state, the NEW bit in SHA Control register has not been written yet. */ - kHASHCRYPT_HashUpdate, /*!< Update state, DIGEST registers contain running hash, NEW bit in SHA control register has - been written. */ -} hashcrypt_sha_algo_state_t; - -/*! 64-byte block represented as byte array of 16 32-bit words */ -typedef union _sha_hash_block -{ - uint32_t w[SHA_BLOCK_SIZE / 4]; /*!< array of 32-bit words */ - uint8_t b[SHA_BLOCK_SIZE]; /*!< byte array */ -} hashcrypt_sha_block_t; - -/*! internal sha context structure */ -typedef struct _hashcrypt_sha_ctx_internal -{ - hashcrypt_sha_block_t blk; /*!< memory buffer. only full 64-byte blocks are written to SHA during hash updates */ - size_t blksz; /*!< number of valid bytes in memory buffer */ - hashcrypt_algo_t algo; /*!< selected algorithm from the set of supported algorithms */ - hashcrypt_sha_algo_state_t state; /*!< finite machine state of the hash software process */ - size_t fullMessageSize; /*!< track message size during SHA_Update(). The value is used for padding. */ - uint32_t remainingBlcks; /*!< number of remaining blocks to process in AHB master mode */ - hashcrypt_callback_t hashCallback; /*!< pointer to HASH callback function */ - void - *userData; /*!< user data to be passed as an argument to callback function, once callback is invoked from isr */ -#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) - uint32_t runningHash[8]; /*!< running hash. up to SHA-256, that is 32 bytes. */ -#endif -} hashcrypt_sha_ctx_internal_t; - -#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) -#define SHA1_LEN 5u -#define SHA256_LEN 8u -#endif - -/*!< SHA-1 and SHA-256 digest length in bytes */ -enum _hashcrypt_sha_digest_len -{ - kHASHCRYPT_OutLenSha1 = 20u, - kHASHCRYPT_OutLenSha256 = 32u, -}; - -/*!< pointer to hash context structure used by isr */ -static hashcrypt_hash_ctx_t *s_ctx; - -/*!< macro for checking build time condition. It is used to assure the hashcrypt_sha_ctx_internal_t can fit into - * hashcrypt_hash_ctx_t */ -#define BUILD_ASSERT(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused)) - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * @brief Swap bytes withing 32-bit word. - * - * This function changes endianess of a 32-bit word. - * - * @param in 32-bit unsigned integer - * @return 32-bit unsigned integer with different endianess (big endian to little endian and vice versa). - */ - -#define swap_bytes(in) __REV(in) - -/*! - * @brief Increment a 16 byte integer. - * - * This function increments by one a 16 byte integer. - * - * @param input Pointer to a 16 byte integer to be incremented by one. - */ -static void ctrIncrement(uint8_t *input) -{ - int i = 15; - while (input[i] == (uint8_t)0xFFu) - { - input[i] = (uint8_t)0x00u; - i--; - if (i < 0) - { - return; - } - } - - if (i >= 0) - { - input[i] += (uint8_t)1u; - } -} - -/*! - * @brief Reads an unaligned word. - * - * This function creates a 32-bit word from an input array of four bytes. - * - * @param src Input array of four bytes. The array can start at any address in memory. - * @return 32-bit unsigned int created from the input byte array. - */ - -/* Force lower optimization for Keil, otherwise it replaces inline LDR with LDM */ -#if defined(__CC_ARM) -#pragma push -#pragma O0 -#endif - -static inline uint32_t hashcrypt_get_word_from_unaligned(const uint8_t *srcAddr) -{ -#if (!(defined(__CORTEX_M)) || (defined(__CORTEX_M) && (__CORTEX_M == 0))) - register const uint8_t *src = srcAddr; - /* Cortex M0 does not support misaligned loads */ - if (0U != ((uint32_t)src & 0x3u)) - { - union _align_bytes_t - { - uint32_t word; - uint8_t byte[sizeof(uint32_t)]; - } my_bytes; - - my_bytes.byte[0] = *src; - my_bytes.byte[1] = src[1]; - my_bytes.byte[2] = src[2]; - my_bytes.byte[3] = src[3]; - return my_bytes.word; - } - else - { - /* addr aligned to 0-modulo-4 so it is safe to type cast */ - return *((const uint32_t *)(uint32_t)src); - } -#elif defined(__CC_ARM) - /* -O3 optimization in Keil 5.15 and 5.16a uses LDM instruction here (LDM r4!, {r0}) - * which is wrong, because srcAddr might be unaligned. - * LDM on unaligned address causes hard-fault. in contrary, - * LDR supports unaligned address on Cortex M4 */ - - register uint32_t retVal; - __asm - { - LDR retVal, [srcAddr] - } - return retVal; -#else - return *((const uint32_t *)(uintptr_t)srcAddr); -#endif -} - -/* End lower optimization */ -#if defined(__CC_ARM) -#pragma pop -#endif - -static status_t hashcrypt_get_key_from_unaligned_src(uint8_t *dest, const uint8_t *src, size_t size) -{ - status_t retVal = kStatus_InvalidArgument; - uint32_t i; - - /* destination is SDK driver internal workspace and it must be aligned */ - assert(0x0u == ((uint32_t)dest & 0x1u)); - if (0U != ((uint32_t)dest & 0x1u)) - { - return retVal; - } - - for (i = 0; i < ((uint32_t)size / 4u); i++) - { - ((uint32_t *)(uintptr_t)dest)[i] = hashcrypt_get_word_from_unaligned(&src[i * sizeof(uint32_t)]); - } - - return kStatus_Success; -} - -/*! - * @brief LDM to SHA engine INDATA and ALIAS registers. - * - * This function writes 16 words starting from the src address (must be word aligned) - * to the dst address. Dst address does not increment (destination is peripheral module register INDATA). - * Src address increments to load 16 consecutive words. - * - * @param dst peripheral register address (word aligned) - * @param src address of the input 512-bit block (16 words) (word aligned) - * - */ -__STATIC_FORCEINLINE void hashcrypt_sha_ldm_stm_16_words(HASHCRYPT_Type *base, const uint32_t *src) -{ - /* Data Synchronization Barrier */ - __DSB(); - /* - typedef struct _one_block - { - uint32_t a[8]; - } one_block_t; - - volatile one_block_t *ldst = (void *)(uintptr_t)(&base->INDATA); - one_block_t *lsrc = (void *)(uintptr_t)src; - *ldst = lsrc[0]; - *ldst = lsrc[1]; - */ - - /* Data Synchronization Barrier prevent compiler from reordering memory write when -O2 or higher is used. */ - /* The address is passed to the crypto engine for hashing below, therefore out */ - /* of order memory write due to compiler optimization must be prevented. */ - __DSB(); - - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(src); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(1); - - __DSB(); -} - -/*! - * @brief Loads data to Hashcrypt engine INDATA register. - * - * This function writes desired number of bytes starting from the src address - * to the dst address. Dst address does not increment (destination is peripheral module register INDATA). - * Src address increments to load consecutive words. - * - * @param src address of the input block - * @param size number of bytes to write - * - */ -__STATIC_INLINE void hashcrypt_load_data(HASHCRYPT_Type *base, uint32_t *src, size_t size) -{ - /* 16 bytes aligned input block */ - uint32_t __attribute__((aligned(4))) inAlign[HASHCRYPT_AES_BLOCK_SIZE / sizeof(uint32_t)]; - uint32_t *in; - uint8_t i; - - in = src; - /* Check if address of src data is aligned */ - if ((0U != ((uint32_t)in & 3U))) - { - for (i = 0; i < ((uint32_t)size / 4U); i++) - { - inAlign[i] = hashcrypt_get_word_from_unaligned((uint8_t *)&src[i]); - } - in = &inAlign[0]; - } - - if (size >= sizeof(uint32_t)) - { - base->INDATA = in[0]; - size -= sizeof(uint32_t); - } - - for (uint32_t j = 0; j < size / 4U; j++) - { - base->ALIAS[j] = in[j + 1U]; - } -} - -/*! - * @brief Checks availability of HW AES key. - * - * This function checks if the AES key is present at dedicated hardware bus - * and can be used at actual security level. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @return kStatus_Success if available, kStatus_Fail otherwise. - * - */ -static status_t hashcrypt_check_need_key(HASHCRYPT_Type *base, hashcrypt_handle_t *handle) -{ - if (handle->keyType == kHASHCRYPT_SecretKey) - { - volatile uint32_t wait = 50u; - /* wait until STATUS register is non-zero */ - while ((wait > 0U) && (base->STATUS == 0U)) - { - wait--; - } - /* if NEEDKEY bit is not set, HW key is available */ - if (0U == (base->STATUS & HASHCRYPT_STATUS_NEEDKEY_MASK)) - { - return kStatus_Success; - } - /* NEEDKEY is set, HW key is not available */ - return kStatus_Fail; - } - else - { - /* in case user key is used, return success */ - return kStatus_Success; - } -} - -/*! - * @brief Read OUTDATA registers. - * - * This function copies OUTDATA to output buffer. - * - * @param base Hachcrypt peripheral base address. - * @param[out] output Output buffer. - * @param Number of bytes to copy. - */ -static void hashcrypt_get_data(HASHCRYPT_Type *base, uint32_t *output, size_t outputSize) -{ - uint32_t digest[8]; - - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - - /* Data Synchronization Barrier */ - __DSB(); - - for (int i = 0; i < 8; i++) - { - digest[i] = swap_bytes(base->DIGEST0[i]); - } - - if (outputSize > sizeof(digest)) - { - outputSize = sizeof(digest); - } - (void)hashcrypt_memcpy(output, digest, outputSize); -} - -/*! - * @brief Initialize the Hashcrypt engine for new operation. - * - * This function sets NEW and MODE fields in Hashcrypt Control register to start new operation. - * - * @param base Hashcrypt peripheral base address. - * @param hashcrypt_algo_t Internal context. - */ -static void hashcrypt_engine_init(HASHCRYPT_Type *base, hashcrypt_algo_t algo) -{ - /* NEW bit must be set before we switch from previous mode otherwise new mode will not work correctly */ - base->CTRL = HASHCRYPT_CTRL_NEW_HASH(1); - base->CTRL = HASHCRYPT_CTRL_MODE(algo) | HASHCRYPT_CTRL_NEW_HASH(1); -} - -/*! - * @brief Deinitialization of the Hashcrypt engine. - * - * This function sets MODE field in Hashcrypt Control register to zero - disabled. - * This reduces power consumption of HASHCRYPT. - * - * @param base Hashcrypt peripheral base address. - */ -static inline void hashcrypt_engine_deinit(HASHCRYPT_Type *base) -{ - base->CTRL &= ~(HASHCRYPT_CTRL_MODE_MASK); -} - -/*! - * @brief Loads user key to INDATA register. - * - * This function writes user key stored in handle into HashCrypt INDATA register. - * - * @param base Hashcrypt peripheral base address. - * @param handle Handle used for this request. - */ -static void hashcrypt_aes_load_userKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle) -{ - size_t keySize = 0; - - switch (handle->keySize) - { - case kHASHCRYPT_Aes128: - keySize = 16; - break; - case kHASHCRYPT_Aes192: - keySize = 24; - break; - case kHASHCRYPT_Aes256: - keySize = 32; - break; - default: - /* All the cases have been listed above, the default clause should not be reached. */ - break; - } - if (keySize == 0U) - { - return; - } - hashcrypt_load_data(base, &handle->keyWord[0], keySize); -} - -/*! - * @brief Performs AES encryption/decryption of one data block. - * - * This function encrypts/decrypts one block of data with specified size. - * - * @param base Hashcrypt peripheral base address. - * @param input input data - * @param output output data - * @param size size of data block to process in bytes (must be 16bytes multiple). - */ -static status_t hashcrypt_aes_one_block_aligned(HASHCRYPT_Type *base, - const uint8_t *input, - uint8_t *output, - size_t size) -{ - status_t status = kStatus_Fail; - uint32_t idx = 0; - - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(input); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(size / 16U); - while (size >= HASHCRYPT_AES_BLOCK_SIZE) - { - /* Get result */ - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - - for (int i = 0; i < 4; i++) - { - ((uint32_t *)(uintptr_t)output + idx)[i] = swap_bytes(base->DIGEST0[i]); - } - - idx += HASHCRYPT_AES_BLOCK_SIZE / 4U; - size -= HASHCRYPT_AES_BLOCK_SIZE; - } - - if (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * @brief Performs AES encryption/decryption of one data block. - * - * This function encrypts/decrypts one block of data with specified size. - * - * @param base Hashcrypt peripheral base address. - * @param input input data - * @param output output data - * @param size size of data block to process in bytes (must be 16bytes multiple). - */ -static status_t hashcrypt_aes_one_block_unaligned(HASHCRYPT_Type *base, - const uint8_t *input, - uint8_t *output, - size_t size) -{ - status_t status = kStatus_Fail; - - /* we use AHB master mode as much as possible */ - /* however, it can work only with aligned input data */ - /* so, if unaligned, we do memcpy to temp buffer on stack, which is aligned, and use AHB mode to read data in */ - /* then we read data back to it and do memcpy to the output buffer */ - uint32_t temp[256 / sizeof(uint32_t)]; - int cnt = 0; - while (size != 0U) - { - size_t actSz = size >= 256u ? 256u : size; - size_t actSzOrig = actSz; - (void)memcpy(temp, (const uint32_t *)(uintptr_t)(input + 256 * cnt), actSz); - size -= actSz; - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(temp); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(actSz / 16U); - uint32_t outidx = 0; - while (actSz != 0U) - { - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - for (int i = 0; i < 4; i++) - { - (temp + outidx)[i] = swap_bytes(base->DIGEST0[i]); - } - outidx += HASHCRYPT_AES_BLOCK_SIZE / 4U; - actSz -= HASHCRYPT_AES_BLOCK_SIZE; - } - (void)memcpy(output + 256 * cnt, (const uint8_t *)(uintptr_t)temp, actSzOrig); - cnt++; - } - - if (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * @brief Performs AES encryption/decryption of one data block. - * - * This function encrypts/decrypts one block of data with specified size. - * - * @param base Hashcrypt peripheral base address. - * @param input input data - * @param output output data - * @param size size of data block to process in bytes (must be 16bytes multiple). - */ -static status_t hashcrypt_aes_one_block(HASHCRYPT_Type *base, const uint8_t *input, uint8_t *output, size_t size) -{ - status_t status = kStatus_Fail; - - /*MEMCTRL bitfield for COUNT is 11 bits, and this limits the number of blocks to process in one Master run to 2047 - (2^11 -1) blocks . Each block is 16bytes long, so biggest data size which can we do in one Master run is (2047 - blocks *16 bytes) = 32752 So, when size is overflowing HASHCRYPT_MEMCTRL_COUNT field of MEMCTRL register, we split - our data into more smaller chunks */ - - if (size > 32752U) - - { - size_t numBlock = size / 32752U; /* number of blocks, each block is processed in one run*/ - size_t remainingSize = size - (numBlock * 32752U); /* size of last block */ - - if ((0U != ((uint32_t)input & 0x3u)) || (0U != ((uint32_t)output & 0x3u))) /* If data is unaligned*/ - { - for (uint32_t i = 0; i < numBlock; i++) - { - status = hashcrypt_aes_one_block_unaligned(base, input, output, 32752U); - input += 32752U; - output += 32752U; - } - status = hashcrypt_aes_one_block_unaligned(base, input, output, remainingSize); - } - else /* If data is aligned*/ - { - for (uint32_t i = 0; i < numBlock; i++) - { - status = hashcrypt_aes_one_block_aligned(base, input, output, 32752U); - input += 32752U; - output += 32752U; - } - status = hashcrypt_aes_one_block_aligned(base, input, output, remainingSize); - } - } - - else /* size is less than COUNT field of MEMCTRL register so we can process all data at once */ - { - /* we use AHB master mode as much as possible */ - /* however, it can work only with aligned input data */ - /* so, if unaligned, we do memcpy to temp buffer on stack, which is aligned, and use AHB mode to read data in */ - /* then we read data back to it and do memcpy to the output buffer */ - if ((0U != ((uint32_t)input & 0x3u)) || (0U != ((uint32_t)output & 0x3u))) - { - status = hashcrypt_aes_one_block_unaligned(base, input, output, size); - } - else - { - status = hashcrypt_aes_one_block_aligned(base, input, output, size); - } - } - return status; -} - -/*! - * @brief Check validity of algoritm. - * - * This function checks the validity of input argument. - * - * @param algo Tested algorithm value. - * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. - */ -static status_t hashcrypt_sha_check_input_alg(HASHCRYPT_Type *base, hashcrypt_algo_t algo) -{ - if ((algo == kHASHCRYPT_Sha1) || (algo == kHASHCRYPT_Sha256)) - { - return kStatus_Success; - } - - return kStatus_InvalidArgument; -} - -/*! - * @brief Check validity of input arguments. - * - * This function checks the validity of input arguments. - * - * @param base SHA peripheral base address. - * @param ctx Memory buffer given by user application where the SHA_Init/SHA_Update/SHA_Finish store context. - * @param algo Tested algorithm value. - * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. - */ -static status_t hashcrypt_sha_check_input_args(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo) -{ - /* Check validity of input algorithm */ - if (kStatus_Success != hashcrypt_sha_check_input_alg(base, algo)) - { - return kStatus_InvalidArgument; - } - - if ((NULL == ctx) || (NULL == base)) - { - return kStatus_InvalidArgument; - } - - return kStatus_Success; -} - -/*! - * @brief Check validity of internal software context. - * - * This function checks if the internal context structure looks correct. - * - * @param ctxInternal Internal context. - * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. - */ -static status_t hashcrypt_sha_check_context(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) -{ - if ((NULL == ctxInternal) || (kStatus_Success != hashcrypt_sha_check_input_alg(base, ctxInternal->algo))) - { - return kStatus_InvalidArgument; - } - return kStatus_Success; -} - -/*! - * @brief Load 512-bit block (16 words) into SHA engine. - * - * This function aligns the input block and moves it into SHA engine INDATA. - * CPU polls the WAITING bit and then moves data by using LDM and STM instructions. - * - * @param base SHA peripheral base address. - * @param blk 512-bit block - */ -static void hashcrypt_sha_one_block(HASHCRYPT_Type *base, const uint8_t *blk) -{ - uint32_t temp[SHA_BLOCK_SIZE / sizeof(uint32_t)]; - const uint32_t *actBlk; - - /* make sure the 512-bit block is word aligned */ - if (0U != ((uintptr_t)blk & 0x3u)) - { - (void)hashcrypt_memcpy(temp, (const uint32_t *)(uintptr_t)blk, SHA_BLOCK_SIZE); - actBlk = (const uint32_t *)(uintptr_t)temp; - } - else - { - actBlk = (const uint32_t *)(uintptr_t)blk; - } - - /* poll waiting. */ - while (0U == (base->STATUS & HASHCRYPT_STATUS_WAITING_MASK)) - { - } - /* feed INDATA (and ALIASes). use STM instruction. */ - hashcrypt_sha_ldm_stm_16_words(base, actBlk); -} - -/*! - * @brief Adds message to current hash. - * - * This function merges the message to fill the internal buffer, empties the internal buffer if - * it becomes full, then process all remaining message data. - * - * - * @param base SHA peripheral base address. - * @param ctxInternal Internal context. - * @param message Input message. - * @param messageSize Size of input message in bytes. - * @return kStatus_Success. - */ -static status_t hashcrypt_sha_process_message_data(HASHCRYPT_Type *base, - hashcrypt_sha_ctx_internal_t *ctxInternal, - const uint8_t *message, - size_t messageSize) -{ - /* first fill the internal buffer to full block */ - if (ctxInternal->blksz != 0U) - { - size_t toCopy = SHA_BLOCK_SIZE - ctxInternal->blksz; - (void)hashcrypt_memcpy(&ctxInternal->blk.b[ctxInternal->blksz], message, toCopy); - message += toCopy; - messageSize -= toCopy; - - /* process full internal block */ - hashcrypt_sha_one_block(base, &ctxInternal->blk.b[0]); - } - - /* process all full blocks in message[] */ - if (messageSize >= SHA_BLOCK_SIZE) - { - if (0U != ((uintptr_t)message & 0x3u)) - { - while (messageSize >= SHA_BLOCK_SIZE) - { - hashcrypt_sha_one_block(base, message); - message += SHA_BLOCK_SIZE; - messageSize -= SHA_BLOCK_SIZE; - } - } - else - { - /* poll waiting. */ - while (0U == (base->STATUS & HASHCRYPT_STATUS_WAITING_MASK)) - { - } - uint32_t blkNum = (messageSize >> 6); /* div by 64 bytes */ - uint32_t blkBytes = blkNum * 64u; /* number of bytes in 64 bytes blocks */ - __DSB(); - __ISB(); - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(message); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(blkNum); - message += blkBytes; - messageSize -= blkBytes; - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - } - } - - /* copy last incomplete message bytes into internal block */ - (void)hashcrypt_memcpy(&ctxInternal->blk.b[0], message, messageSize); - ctxInternal->blksz = messageSize; - return kStatus_Success; -} - -/*! - * @brief Finalize the running hash to make digest. - * - * This function empties the internal buffer, adds padding bits, and generates final digest. - * - * @param base SHA peripheral base address. - * @param ctxInternal Internal context. - * @return kStatus_Success. - */ -static status_t hashcrypt_sha_finalize(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) -{ - hashcrypt_sha_block_t lastBlock; - - (void)memset(&lastBlock, 0, sizeof(hashcrypt_sha_block_t)); - - /* this is last call, so need to flush buffered message bytes along with padding */ - if (ctxInternal->blksz <= 55u) - { - /* last data is 440 bits or less. */ - (void)hashcrypt_memcpy(&lastBlock.b[0], &ctxInternal->blk.b[0], ctxInternal->blksz); - lastBlock.b[ctxInternal->blksz] = (uint8_t)0x80U; - lastBlock.w[SHA_BLOCK_SIZE / 4U - 1U] = swap_bytes(8u * ctxInternal->fullMessageSize); - hashcrypt_sha_one_block(base, &lastBlock.b[0]); - } - else - { - if (ctxInternal->blksz < SHA_BLOCK_SIZE) - { - ctxInternal->blk.b[ctxInternal->blksz] = (uint8_t)0x80U; - for (uint32_t i = ctxInternal->blksz + 1u; i < SHA_BLOCK_SIZE; i++) - { - ctxInternal->blk.b[i] = 0; - } - } - else - { - lastBlock.b[0] = (uint8_t)0x80U; - } - - hashcrypt_sha_one_block(base, &ctxInternal->blk.b[0]); - lastBlock.w[SHA_BLOCK_SIZE / 4U - 1U] = swap_bytes(8u * ctxInternal->fullMessageSize); - hashcrypt_sha_one_block(base, &lastBlock.b[0]); - } - /* poll wait for final digest */ - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - return kStatus_Success; -} - -static void hashcrypt_save_running_hash(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) -{ -#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) - size_t len = (ctxInternal->algo == kHASHCRYPT_Sha1) ? SHA1_LEN : SHA256_LEN; - - /* Wait until digest is ready */ - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - - /* Store partial digest to context */ - for (uint32_t i = 0; i < len; i++) - { - ctxInternal->runningHash[i] = base->DIGEST0[i]; - } -#endif -} - -static void hashcrypt_restore_running_hash(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) -{ -#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) - size_t len = (ctxInternal->algo == kHASHCRYPT_Sha1) ? SHA1_LEN : SHA256_LEN; - - /* When switching from different mode, need to set NEW bit to work properly */ - if ((base->CTRL & HASHCRYPT_CTRL_MODE_MASK) != HASHCRYPT_CTRL_MODE(ctxInternal->algo)) - { - base->CTRL = HASHCRYPT_CTRL_NEW_HASH(1); - base->CTRL = HASHCRYPT_CTRL_MODE(ctxInternal->algo) | HASHCRYPT_CTRL_NEW_HASH(1); - } - /* Set RELOAD bit to allow registers to be used */ - base->CTRL |= HASHCRYPT_CTRL_RELOAD_MASK; - - /* Reload partial hash digest */ - for (uint32_t i = 0; i < len; i++) - { - base->RELOAD[i] = ctxInternal->runningHash[i]; - } - /* Clear RELOAD register before continuing */ - base->CTRL &= ~HASHCRYPT_CTRL_RELOAD_MASK; -#endif -} - -status_t HASHCRYPT_SHA(HASHCRYPT_Type *base, - hashcrypt_algo_t algo, - const uint8_t *input, - size_t inputSize, - uint8_t *output, - size_t *outputSize) -{ - hashcrypt_hash_ctx_t hashCtx; - status_t status; - - status = HASHCRYPT_SHA_Init(base, &hashCtx, algo); - if (status != kStatus_Success) - { - return status; - } - - status = HASHCRYPT_SHA_Update(base, &hashCtx, input, inputSize); - if (status != kStatus_Success) - { - return status; - } - - status = HASHCRYPT_SHA_Finish(base, &hashCtx, output, outputSize); - - return status; -} - -status_t HASHCRYPT_SHA_Init(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo) -{ - status_t status; - - hashcrypt_sha_ctx_internal_t *ctxInternal; - /* compile time check for the correct structure size */ - BUILD_ASSERT(sizeof(hashcrypt_hash_ctx_t) >= sizeof(hashcrypt_sha_ctx_internal_t), hashcrypt_hash_ctx_t_size); - - status = hashcrypt_sha_check_input_args(base, ctx, algo); - if (status != kStatus_Success) - { - return status; - } - - /* set algorithm in context struct for later use */ - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; - ctxInternal->algo = algo; - ctxInternal->blksz = 0u; -#ifdef HASHCRYPT_SHA_DO_WIPE_CONTEXT - for (int i = 0; i < sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]); i++) - { - ctxInternal->blk.w[i] = 0u; - } -#endif /* HASHCRYPT_SHA_DO_WIPE_CONTEXT */ - ctxInternal->state = kHASHCRYPT_HashInit; - ctxInternal->fullMessageSize = 0; - return kStatus_Success; -} - -status_t HASHCRYPT_SHA_Update(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize) -{ - bool isUpdateState; - status_t status; - hashcrypt_sha_ctx_internal_t *ctxInternal; - size_t blockSize; - - if (inputSize == 0U) - { - return kStatus_Success; - } - - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; -#ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT - status = hashcrypt_sha_check_context(base, ctxInternal); - if (kStatus_Success != status) - { - return status; - } -#endif /* HASHCRYPT_SHA_DO_CHECK_CONTEXT */ - - ctxInternal->fullMessageSize += inputSize; - blockSize = SHA_BLOCK_SIZE; - /* if we are still less than 64 bytes, keep only in context */ - if ((ctxInternal->blksz + inputSize) <= blockSize) - { - (void)hashcrypt_memcpy((&ctxInternal->blk.b[0]) + ctxInternal->blksz, input, inputSize); - ctxInternal->blksz += inputSize; - return kStatus_Success; - } - else - { - isUpdateState = ctxInternal->state == kHASHCRYPT_HashUpdate; - if (!isUpdateState) - { - /* start NEW hash */ - hashcrypt_engine_init(base, ctxInternal->algo); - ctxInternal->state = kHASHCRYPT_HashUpdate; - } - else - { - hashcrypt_restore_running_hash(base, ctxInternal); - } - } - - /* process message data */ - /* Data Synchronization Barrier */ - __DSB(); - status = hashcrypt_sha_process_message_data(base, ctxInternal, input, inputSize); - hashcrypt_save_running_hash(base, ctxInternal); - return status; -} - -status_t HASHCRYPT_SHA_Finish(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize) -{ - size_t algOutSize = 0; - status_t status; - hashcrypt_sha_ctx_internal_t *ctxInternal; -#ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT - uint32_t *ctxW; - uint32_t i; -#endif /* HASHCRYPT_SHA_DO_CHECK_CONTEXT */ - - if (output == NULL) - { - return kStatus_InvalidArgument; - } - - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; -#ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT - status = hashcrypt_sha_check_context(base, ctxInternal); - if (kStatus_Success != status) - { - return status; - } -#endif /* HASHCRYPT_SHA_DO_CHECK_CONTEXT */ - - if (ctxInternal->state == kHASHCRYPT_HashInit) - { - hashcrypt_engine_init(base, ctxInternal->algo); - } - else - { - hashcrypt_restore_running_hash(base, ctxInternal); - } - - size_t outSize = 0u; - - /* compute algorithm output length */ - switch (ctxInternal->algo) - { - case kHASHCRYPT_Sha1: - outSize = (size_t)kHASHCRYPT_OutLenSha1; - break; - case kHASHCRYPT_Sha256: - outSize = (size_t)kHASHCRYPT_OutLenSha256; - break; - default: - /* All the cases have been listed above, the default clause should not be reached. */ - break; - } - algOutSize = outSize; - - /* flush message last incomplete block, if there is any, and add padding bits */ - status = hashcrypt_sha_finalize(base, ctxInternal); - - if (outputSize != NULL) - { - if (algOutSize < *outputSize) - { - *outputSize = algOutSize; - } - else - { - algOutSize = *outputSize; - } - } - - hashcrypt_get_data(base, (uint32_t *)(uintptr_t)output, algOutSize); - -#ifdef HASHCRYPT_SHA_DO_WIPE_CONTEXT - ctxW = (uint32_t *)ctx; - for (i = 0; i < HASHCRYPT_HASH_CTX_SIZE; i++) - { - ctxW[i] = 0u; - } -#endif /* HASHCRYPT_SHA_DO_WIPE_CONTEXT */ - return status; -} - -void HASHCRYPT_SHA_SetCallback(HASHCRYPT_Type *base, - hashcrypt_hash_ctx_t *ctx, - hashcrypt_callback_t callback, - void *userData) -{ - hashcrypt_sha_ctx_internal_t *ctxInternal; - - s_ctx = ctx; - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; - ctxInternal->hashCallback = callback; - ctxInternal->userData = userData; - - (void)EnableIRQ(HASHCRYPT_IRQn); -} - -status_t HASHCRYPT_SHA_UpdateNonBlocking(HASHCRYPT_Type *base, - hashcrypt_hash_ctx_t *ctx, - const uint8_t *input, - size_t inputSize) -{ - hashcrypt_sha_ctx_internal_t *ctxInternal; - uint32_t numBlocks; - status_t status; - - if (inputSize == 0U) - { - return kStatus_Success; - } - - if (0U != ((uintptr_t)input & 0x3U)) - { - return kStatus_Fail; - } - - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; - status = hashcrypt_sha_check_context(base, ctxInternal); - if (kStatus_Success != status) - { - return status; - } - - ctxInternal->fullMessageSize = inputSize; - ctxInternal->remainingBlcks = inputSize / SHA_BLOCK_SIZE; - ctxInternal->blksz = inputSize % SHA_BLOCK_SIZE; - - /* copy last incomplete block to context */ - if ((ctxInternal->blksz > 0U) && (ctxInternal->blksz <= SHA_BLOCK_SIZE)) - { - (void)hashcrypt_memcpy((&ctxInternal->blk.b[0]), input + SHA_BLOCK_SIZE * ctxInternal->remainingBlcks, - ctxInternal->blksz); - } - - if (ctxInternal->remainingBlcks >= SHA_MASTER_MAX_BLOCKS) - { - numBlocks = SHA_MASTER_MAX_BLOCKS - 1U; - } - else - { - numBlocks = ctxInternal->remainingBlcks; - } - /* update remainingBlks so that ISR can run another hash if necessary */ - ctxInternal->remainingBlcks -= numBlocks; - - /* compute hash using AHB Master mode for full blocks */ - if (numBlocks > 0U) - { - ctxInternal->state = kHASHCRYPT_HashUpdate; - hashcrypt_engine_init(base, ctxInternal->algo); - - /* Enable digest and error interrupts and start hash */ - base->INTENSET = HASHCRYPT_INTENCLR_DIGEST_MASK | HASHCRYPT_INTENCLR_ERROR_MASK; - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(input); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(numBlocks); - } - /* no full blocks, invoke callback directly */ - else - { - ctxInternal->hashCallback(HASHCRYPT, ctx, status, ctxInternal->userData); - } - - return status; -} - -status_t HASHCRYPT_AES_SetKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *key, size_t keySize) -{ - status_t retVal = kStatus_InvalidArgument; - - switch (keySize) - { - case 16: - handle->keySize = kHASHCRYPT_Aes128; - break; - case 24: - handle->keySize = kHASHCRYPT_Aes192; - break; - case 32: - handle->keySize = kHASHCRYPT_Aes256; - break; - default: - handle->keySize = kHASHCRYPT_InvalidKey; - break; - } - - if (handle->keySize == kHASHCRYPT_InvalidKey) - { - return retVal; - } - - if (handle->keyType == kHASHCRYPT_SecretKey) - { - /* for kHASHCRYPT_SecretKey just return Success */ - retVal = kStatus_Success; - } - else if (handle->keyType == kHASHCRYPT_UserKey) - { - retVal = hashcrypt_get_key_from_unaligned_src((uint8_t *)&handle->keyWord[0], key, keySize); - } - else - { - retVal = kStatus_InvalidArgument; - } - - return retVal; -} - -status_t HASHCRYPT_AES_EncryptEcb( - HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size) -{ - status_t status = kStatus_Fail; - - if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesEcb) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load message and get result */ - status = hashcrypt_aes_one_block(base, plaintext, ciphertext, size); - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - - return status; -} - -status_t HASHCRYPT_AES_DecryptEcb( - HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size) -{ - status_t status = kStatus_Fail; - - if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesEcb) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_DECRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load message and get result */ - status = hashcrypt_aes_one_block(base, ciphertext, plaintext, size); - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -status_t HASHCRYPT_AES_EncryptCbc(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t iv[16]) -{ - status_t status = kStatus_Fail; - - if (0U != ((size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load 16b iv */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, 16); - - /* load message and get result */ - status = hashcrypt_aes_one_block(base, plaintext, ciphertext, size); - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -status_t HASHCRYPT_AES_DecryptCbc(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t iv[16]) -{ - status_t status = kStatus_Fail; - - if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_DECRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load iv */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, 16); - - /* load message and get result */ - status = hashcrypt_aes_one_block(base, ciphertext, plaintext, size); - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *input, - uint8_t *output, - size_t size, - uint8_t counter[HASHCRYPT_AES_BLOCK_SIZE], - uint8_t counterlast[HASHCRYPT_AES_BLOCK_SIZE], - size_t *szLeft) -{ - uint32_t lastSize; - uint8_t lastBlock[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - uint8_t *lastEncryptedCounter; - status_t status = kStatus_Fail; - - if (handle->keySize == kHASHCRYPT_InvalidKey) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCtr) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load nonce */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)counter, 16); - - lastSize = size % HASHCRYPT_AES_BLOCK_SIZE; - size -= lastSize; - - /* encrypt full 16byte blocks */ - status = hashcrypt_aes_one_block(base, input, output, size); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - - while (size != 0U) - { - ctrIncrement(counter); - size -= 16u; - input += 16; - output += 16; - } - - if (lastSize != 0U) - { - if (counterlast != NULL) - { - lastEncryptedCounter = counterlast; - } - else - { - lastEncryptedCounter = lastBlock; - } - - /* Perform encryption with all zeros to get last counter. XOR with zeros doesn't change. */ - status = hashcrypt_aes_one_block(base, lastBlock, lastEncryptedCounter, HASHCRYPT_AES_BLOCK_SIZE); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* remain output = input XOR counterlast */ - for (uint32_t i = 0; i < lastSize; i++) - { - output[i] = input[i] ^ lastEncryptedCounter[i]; - } - /* Increment counter parameter */ - ctrIncrement(counter); - } - else - { - lastSize = HASHCRYPT_AES_BLOCK_SIZE; - /* no remaining bytes in couterlast so clearing it */ - if (counterlast != NULL) - { - (void)memset(counterlast, 0, HASHCRYPT_AES_BLOCK_SIZE); - } - } - - if (szLeft != NULL) - { - *szLeft = HASHCRYPT_AES_BLOCK_SIZE - lastSize; - } - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return kStatus_Success; -} - -status_t HASHCRYPT_AES_CryptOfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *input, - uint8_t *output, - size_t size, - const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]) -{ - status_t status = kStatus_Fail; - uint8_t zeroes[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - uint8_t blockOutput[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - - if (handle->keySize == kHASHCRYPT_InvalidKey) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load iv */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, HASHCRYPT_AES_BLOCK_SIZE); - - /*Use AES CBC mode and feed input with zeroes as input*/ - /*Output block is then XORed with input*/ - - while (size >= 16u) - { - status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* XOR input with output block to get output*/ - for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) - { - output[i] = input[i] ^ blockOutput[i]; - } - size -= 16u; - output += 16; - input += 16; - } - - /* OFB can have non-block multiple size.*/ - if (size != 0U) - { - status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - - /* XOR input with output block to get output*/ - for (uint32_t i = 0; i < size; i++) - { - output[i] = input[i] ^ blockOutput[i]; - } - } - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -status_t HASHCRYPT_AES_EncryptCfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]) -{ - status_t status = kStatus_Fail; - uint8_t zeroes[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - uint8_t blockOutput[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - - /* For CFB mode size must be 16-byte multiple */ - if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load iv */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, HASHCRYPT_AES_BLOCK_SIZE); - - /*Use AES CBC mode and feed input with zeroes for first block */ - /*Output block is then XORed with plaintext to get ciphertext*/ - - status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* XOR plaintext with output block to get ciphertext*/ - for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) - { - ciphertext[i] = plaintext[i] ^ blockOutput[i]; - } - size -= 16u; - - /*Remaining blocks use previous plaintext as input for aes block function */ - while (size >= 16u) - { - status = hashcrypt_aes_one_block(base, plaintext, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - ciphertext += 16; - plaintext += 16; - - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* XOR plaintext with output block to get ciphertext*/ - for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) - { - ciphertext[i] = plaintext[i] ^ blockOutput[i]; - } - size -= 16u; - } - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -status_t HASHCRYPT_AES_DecryptCfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]) -{ - status_t status = kStatus_Fail; - uint8_t zeroes[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - uint8_t blockOutput[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - - /* For CFB mode size must be 16-byte multiple */ - if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load iv */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, HASHCRYPT_AES_BLOCK_SIZE); - - /*Use AES CBC mode and feed input with zeroes for first block */ - /*Output block is then XORed with ciphertext to get plaintext*/ - - status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* XOR ciphertext with output block to get plaintext*/ - for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) - { - plaintext[i] = ciphertext[i] ^ blockOutput[i]; - } - size -= 16u; - - /*Remaining blocks use previous plaintext as input for aes block function */ - while (size >= 16u) - { - status = hashcrypt_aes_one_block(base, plaintext, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - ciphertext += 16; - plaintext += 16; - - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* XOR plaintext with ciphertext block to get plaintext*/ - for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) - { - plaintext[i] = ciphertext[i] ^ blockOutput[i]; - } - size -= 16u; - } - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -void HASHCRYPT_DriverIRQHandler(void); -void HASHCRYPT_DriverIRQHandler(void) -{ - hashcrypt_sha_ctx_internal_t *ctxInternal; - HASHCRYPT_Type *base = HASHCRYPT; - uint32_t numBlocks; - status_t status; - - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)s_ctx; - - if (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) - { - if (ctxInternal->remainingBlcks > 0U) - { - if (ctxInternal->remainingBlcks >= SHA_MASTER_MAX_BLOCKS) - { - numBlocks = SHA_MASTER_MAX_BLOCKS - 1U; - } - else - { - numBlocks = ctxInternal->remainingBlcks; - } - /* some blocks still remaining, update remainingBlcks for next ISR and start another hash */ - ctxInternal->remainingBlcks -= numBlocks; - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(numBlocks); - return; - } - /* no full blocks left, disable interrupts and AHB master mode */ - base->INTENCLR = HASHCRYPT_INTENCLR_DIGEST_MASK | HASHCRYPT_INTENCLR_ERROR_MASK; - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(0); - hashcrypt_save_running_hash(base, ctxInternal); - status = kStatus_Success; - } - else - { - status = kStatus_Fail; - } - - /* Invoke callback if there is one */ - if (NULL != ctxInternal->hashCallback) - { - ctxInternal->hashCallback(HASHCRYPT, s_ctx, status, ctxInternal->userData); - } -} - -void HASHCRYPT_Init(HASHCRYPT_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_HashCrypt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - RESET_PeripheralReset(kHASHCRYPT_RST_SHIFT_RSTn); -} - -void HASHCRYPT_Deinit(HASHCRYPT_Type *base) -{ - RESET_SetPeripheralReset(kHASHCRYPT_RST_SHIFT_RSTn); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_HashCrypt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_hashcrypt.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_hashcrypt.h deleted file mode 100644 index fa15b8cf710..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_hashcrypt.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - * Copyright 2017-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_HASHCRYPT_H_ -#define _FSL_HASHCRYPT_H_ - -#include "fsl_common.h" - -/*! @brief HASHCRYPT status return codes. */ -enum _hashcrypt_status -{ - kStatus_HASHCRYPT_Again = - MAKE_STATUS(kStatusGroup_HASHCRYPT, 0), /*!< Non-blocking function shall be called again. */ -}; - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! - * @addtogroup hashcrypt_driver - * @{ - */ -/*! @name Driver version */ -/*@{*/ -/*! @brief HASHCRYPT driver version. Version 2.2.6. - * - * Current version: 2.2.6 - * - * Change log: - * - Version 2.0.0 - * - Initial version - * - Version 2.0.1 - * - Support loading AES key from unaligned address - * - Version 2.0.2 - * - Support loading AES key from unaligned address for different compiler and core variants - * - Version 2.0.3 - * - Remove SHA512 and AES ICB algorithm definitions - * - Version 2.0.4 - * - Add SHA context switch support - * - Version 2.1.0 - * - Update the register name and macro to align with new header. - * - Version 2.1.1 - * - Fix MISRA C-2012. - * - Version 2.1.2 - * - Support loading AES input data from unaligned address. - * - Version 2.1.3 - * - Fix MISRA C-2012. - * - Version 2.1.4 - * - Fix context switch cannot work when switching from AES. - * - Version 2.1.5 - * - Add data synchronization barrier inside hashcrypt_sha_ldm_stm_16_words() - * to prevent possible optimization issue. - * - Version 2.2.0 - * - Add AES-OFB and AES-CFB mixed IP/SW modes. - * - Version 2.2.1 - * - Add data synchronization barrier inside hashcrypt_sha_ldm_stm_16_words() - * prevent compiler from reordering memory write when -O2 or higher is used. - * - Version 2.2.2 - * - Add data synchronization barrier inside hashcrypt_sha_ldm_stm_16_words() - * to fix optimization issue - * - Version 2.2.3 - * - Added check for size in hashcrypt_aes_one_block to prevent overflowing COUNT field in MEMCTRL register, if its - * bigger than COUNT field do a multiple runs. - * - Version 2.2.4 - * - In all HASHCRYPT_AES_xx functions have been added setting CTRL_MODE bitfield to 0 after processing data, which - * decreases power consumption. - * - Version 2.2.5 - * - Add data synchronization barrier and instruction synchronization barrier inside - * hashcrypt_sha_process_message_data() to fix optimization issue - * - Version 2.2.6 - * - Add data synchronization barrier inside HASHCRYPT_SHA_Update() and hashcrypt_get_data() function to fix - * optimization issue on MDK and ARMGCC release targets - */ -#define FSL_HASHCRYPT_DRIVER_VERSION (MAKE_VERSION(2, 2, 6)) -/*@}*/ - -/*! @brief Algorithm definitions correspond with the values for Mode field in Control register !*/ -#define HASHCRYPT_MODE_SHA1 0x1 -#define HASHCRYPT_MODE_SHA256 0x2 -#define HASHCRYPT_MODE_AES 0x4 - -/*! @brief Algorithm used for Hashcrypt operation */ -typedef enum _hashcrypt_algo_t -{ - kHASHCRYPT_Sha1 = HASHCRYPT_MODE_SHA1, /*!< SHA_1 */ - kHASHCRYPT_Sha256 = HASHCRYPT_MODE_SHA256, /*!< SHA_256 */ - kHASHCRYPT_Aes = HASHCRYPT_MODE_AES, /*!< AES */ -} hashcrypt_algo_t; - -/*! @} */ - -/******************************************************************************* - * AES Definitions - *******************************************************************************/ - -/*! - * @addtogroup hashcrypt_driver_aes - * @{ - */ - -/*! AES block size in bytes */ -#define HASHCRYPT_AES_BLOCK_SIZE 16U -#define AES_ENCRYPT 0 -#define AES_DECRYPT 1 - -/*! @brief AES mode */ -typedef enum _hashcrypt_aes_mode_t -{ - kHASHCRYPT_AesEcb = 0U, /*!< AES ECB mode */ - kHASHCRYPT_AesCbc = 1U, /*!< AES CBC mode */ - kHASHCRYPT_AesCtr = 2U, /*!< AES CTR mode */ -} hashcrypt_aes_mode_t; - -/*! @brief Size of AES key */ -typedef enum _hashcrypt_aes_keysize_t -{ - kHASHCRYPT_Aes128 = 0U, /*!< AES 128 bit key */ - kHASHCRYPT_Aes192 = 1U, /*!< AES 192 bit key */ - kHASHCRYPT_Aes256 = 2U, /*!< AES 256 bit key */ - kHASHCRYPT_InvalidKey = 3U, /*!< AES invalid key */ -} hashcrypt_aes_keysize_t; - -/*! @brief HASHCRYPT key source selection. - * - */ -typedef enum _hashcrypt_key -{ - kHASHCRYPT_UserKey = 0xc3c3U, /*!< HASHCRYPT user key */ - kHASHCRYPT_SecretKey = 0x3c3cU, /*!< HASHCRYPT secret key (dedicated hw bus from PUF) */ -} hashcrypt_key_t; - -/*! @brief Specify HASHCRYPT's key resource. */ -struct _hashcrypt_handle -{ - uint32_t keyWord[8]; /*!< Copy of user key (set by HASHCRYPT_AES_SetKey(). */ - hashcrypt_aes_keysize_t keySize; - hashcrypt_key_t keyType; /*!< For operations with key (such as AES encryption/decryption), specify key type. */ -} __attribute__((aligned)); - -typedef struct _hashcrypt_handle hashcrypt_handle_t; - -/*! - *@} - */ /* end of hashcrypt_driver_aes */ - -/******************************************************************************* - * HASH Definitions - ******************************************************************************/ -/*! - * @addtogroup hashcrypt_driver_hash - * @{ - */ - -/*! @brief HASHCRYPT HASH Context size. */ -#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) -#define HASHCRYPT_HASH_CTX_SIZE 30 -#else -#define HASHCRYPT_HASH_CTX_SIZE 22 -#endif - -/*! @brief Storage type used to save hash context. */ -typedef struct _hashcrypt_hash_ctx_t -{ - uint32_t x[HASHCRYPT_HASH_CTX_SIZE]; /*!< storage */ -} hashcrypt_hash_ctx_t; - -/*! @brief HASHCRYPT background hash callback function. */ -typedef void (*hashcrypt_callback_t)(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, status_t status, void *userData); - -/*! - *@} - */ /* end of hashcrypt_driver_hash */ - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup hashcrypt_driver - * @{ - */ - -/*! - * @brief Enables clock and disables reset for HASHCRYPT peripheral. - * - * Enable clock and disable reset for HASHCRYPT. - * - * @param base HASHCRYPT base address - */ -void HASHCRYPT_Init(HASHCRYPT_Type *base); - -/*! - * @brief Disables clock for HASHCRYPT peripheral. - * - * Disable clock and enable reset. - * - * @param base HASHCRYPT base address - */ -void HASHCRYPT_Deinit(HASHCRYPT_Type *base); - -/*! - *@} - */ /* end of hashcrypt_driver */ - -/******************************************************************************* - * AES API - ******************************************************************************/ - -/*! - * @addtogroup hashcrypt_driver_aes - * @{ - */ - -/*! - * @brief Set AES key to hashcrypt_handle_t struct and optionally to HASHCRYPT. - * - * Sets the AES key for encryption/decryption with the hashcrypt_handle_t structure. - * The hashcrypt_handle_t input argument specifies key source. - * - * @param base HASHCRYPT peripheral base address. - * @param handle Handle used for the request. - * @param key 0-mod-4 aligned pointer to AES key. - * @param keySize AES key size in bytes. Shall equal 16, 24 or 32. - * @return status from set key operation - */ -status_t HASHCRYPT_AES_SetKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *key, size_t keySize); - -/*! - * @brief Encrypts AES on one or multiple 128-bit block(s). - * - * Encrypts AES. - * The source plaintext and destination ciphertext can overlap in system memory. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @return Status from encrypt operation - */ -status_t HASHCRYPT_AES_EncryptEcb( - HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size); - -/*! - * @brief Decrypts AES on one or multiple 128-bit block(s). - * - * Decrypts AES. - * The source ciphertext and destination plaintext can overlap in system memory. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param ciphertext Input plain text to encrypt - * @param[out] plaintext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @return Status from decrypt operation - */ -status_t HASHCRYPT_AES_DecryptEcb( - HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size); - -/*! - * @brief Encrypts AES using CBC block mode. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return Status from encrypt operation - */ -status_t HASHCRYPT_AES_EncryptCbc(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t iv[16]); - -/*! - * @brief Decrypts AES using CBC block mode. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param ciphertext Input cipher text to decrypt - * @param[out] plaintext Output plain text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return Status from decrypt operation - */ -status_t HASHCRYPT_AES_DecryptCbc(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t iv[16]); - -/*! - * @brief Encrypts or decrypts AES using CTR block mode. - * - * Encrypts or decrypts AES using CTR block mode. - * AES CTR mode uses only forward AES cipher and same algorithm for encryption and decryption. - * The only difference between encryption and decryption is that, for encryption, the input argument - * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text - * and the output argument is plain text. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param input Input data for CTR block mode - * @param[out] output Output data for CTR block mode - * @param size Size of input and output data in bytes - * @param[in,out] counter Input counter (updates on return) - * @param[out] counterlast Output cipher of last counter, for chained CTR calls (statefull encryption). NULL can be - * passed if chained calls are - * not used. - * @param[out] szLeft Output number of bytes in left unused in counterlast block. NULL can be passed if chained calls - * are not used. - * @return Status from encrypt operation - */ -status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *input, - uint8_t *output, - size_t size, - uint8_t counter[HASHCRYPT_AES_BLOCK_SIZE], - uint8_t counterlast[HASHCRYPT_AES_BLOCK_SIZE], - size_t *szLeft); - -/*! - * @brief Encrypts or decrypts AES using OFB block mode. - * - * Encrypts or decrypts AES using OFB block mode. - * AES OFB mode uses only forward AES cipher and same algorithm for encryption and decryption. - * The only difference between encryption and decryption is that, for encryption, the input argument - * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text - * and the output argument is plain text. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param input Input data for OFB block mode - * @param[out] output Output data for OFB block mode - * @param size Size of input and output data in bytes - * @param iv Input initial vector to combine with the first input block. - * @return Status from encrypt operation - */ - -status_t HASHCRYPT_AES_CryptOfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *input, - uint8_t *output, - size_t size, - const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]); - -/*! - * @brief Encrypts AES using CFB block mode. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return Status from encrypt operation - */ - -status_t HASHCRYPT_AES_EncryptCfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t iv[16]); - -/*! - * @brief Decrypts AES using CFB block mode. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param ciphertext Input cipher text to decrypt - * @param[out] plaintext Output plaintext text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return Status from encrypt operation - */ - -status_t HASHCRYPT_AES_DecryptCfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t iv[16]); -/*! - *@} - */ /* end of hashcrypt_driver_aes */ - -/******************************************************************************* - * HASH API - ******************************************************************************/ - -/*! - * @addtogroup hashcrypt_driver_hash - * @{ - */ - -/*! - * @brief Create HASH on given data - * - * Perform the full SHA in one function call. The function is blocking. - * - * @param base HASHCRYPT peripheral base address - * @param algo Underlaying algorithm to use for hash computation. - * @param input Input data - * @param inputSize Size of input data in bytes - * @param[out] output Output hash data - * @param[out] outputSize Output parameter storing the size of the output hash in bytes - * @return Status of the one call hash operation. - */ -status_t HASHCRYPT_SHA(HASHCRYPT_Type *base, - hashcrypt_algo_t algo, - const uint8_t *input, - size_t inputSize, - uint8_t *output, - size_t *outputSize); - -/*! - * @brief Initialize HASH context - * - * This function initializes the HASH. - * - * @param base HASHCRYPT peripheral base address - * @param[out] ctx Output hash context - * @param algo Underlaying algorithm to use for hash computation. - * @return Status of initialization - */ -status_t HASHCRYPT_SHA_Init(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo); - -/*! - * @brief Add data to current HASH - * - * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be - * hashed. The functions blocks. If it returns kStatus_Success, the running hash - * has been updated (HASHCRYPT has processed the input data), so the memory at \p input pointer - * can be released back to system. The HASHCRYPT context buffer is updated with the running hash - * and with all necessary information to support possible context switch. - * - * @param base HASHCRYPT peripheral base address - * @param[in,out] ctx HASH context - * @param input Input data - * @param inputSize Size of input data in bytes - * @return Status of the hash update operation - */ -status_t HASHCRYPT_SHA_Update(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize); - -/*! - * @brief Finalize hashing - * - * Outputs the final hash (computed by HASHCRYPT_HASH_Update()) and erases the context. - * - * @param base HASHCRYPT peripheral base address - * @param[in,out] ctx Input hash context - * @param[out] output Output hash data - * @param[in,out] outputSize Optional parameter (can be passed as NULL). On function entry, it specifies the size of - * output[] buffer. On function return, it stores the number of updated output bytes. - * @return Status of the hash finish operation - */ -status_t HASHCRYPT_SHA_Finish(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize); - -/*! - *@} - */ /* end of hashcrypt_driver_hash */ - -/*! - * @addtogroup hashcrypt_background_driver_hash - * @{ - */ - -/*! - * @brief Initializes the HASHCRYPT handle for background hashing. - * - * This function initializes the hash context for background hashing - * (Non-blocking) APIs. This is less typical interface to hash function, but can be used - * for parallel processing, when main CPU has something else to do. - * Example is digital signature RSASSA-PKCS1-V1_5-VERIFY((n,e),M,S) algorithm, where - * background hashing of M can be started, then CPU can compute S^e mod n - * (in parallel with background hashing) and once the digest becomes available, - * CPU can proceed to comparison of EM with EM'. - * - * @param base HASHCRYPT peripheral base address. - * @param[out] ctx Hash context. - * @param callback Callback function. - * @param userData User data (to be passed as an argument to callback function, once callback is invoked from isr). - */ -void HASHCRYPT_SHA_SetCallback(HASHCRYPT_Type *base, - hashcrypt_hash_ctx_t *ctx, - hashcrypt_callback_t callback, - void *userData); - -/*! - * @brief Create running hash on given data. - * - * Configures the HASHCRYPT to compute new running hash as AHB master - * and returns immediately. HASHCRYPT AHB Master mode supports only aligned \p input - * address and can be called only once per continuous block of data. Every call to this function - * must be preceded with HASHCRYPT_SHA_Init() and finished with HASHCRYPT_SHA_Finish(). - * Once callback function is invoked by HASHCRYPT isr, it should set a flag - * for the main application to finalize the hashing (padding) and to read out the final digest - * by calling HASHCRYPT_SHA_Finish(). - * - * @param base HASHCRYPT peripheral base address - * @param ctx Specifies callback. Last incomplete 512-bit block of the input is copied into clear buffer for padding. - * @param input 32-bit word aligned pointer to Input data. - * @param inputSize Size of input data in bytes (must be word aligned) - * @return Status of the hash update operation. - */ -status_t HASHCRYPT_SHA_UpdateNonBlocking(HASHCRYPT_Type *base, - hashcrypt_hash_ctx_t *ctx, - const uint8_t *input, - size_t inputSize); -/*! - *@} - */ /* end of hashcrypt_background_driver_hash */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_HASHCRYPT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2c.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2c.c deleted file mode 100644 index 9ecde80c90a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2c.c +++ /dev/null @@ -1,2085 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_i2c.h" -#include "fsl_flexcomm.h" -#include -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c" -#endif - -/*! @brief Common sets of flags used by the driver's transactional layer internally. */ -enum _i2c_flag_constants -{ - kI2C_MasterIrqFlags = I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | - I2C_INTSTAT_EVENTTIMEOUT_MASK | I2C_INTSTAT_SCLTIMEOUT_MASK, - kI2C_SlaveIrqFlags = I2C_INTSTAT_SLVPENDING_MASK | I2C_INTSTAT_SLVDESEL_MASK, -}; - -/*! - * @brief Used for conversion from `flexcomm_irq_handler_t` to `flexcomm_i2c_master_irq_handler_t` and - * `flexcomm_i2c_slave_irq_handler_t`. - */ -typedef union i2c_to_flexcomm -{ - flexcomm_i2c_master_irq_handler_t i2c_master_handler; - flexcomm_i2c_slave_irq_handler_t i2c_slave_handler; - flexcomm_irq_handler_t flexcomm_handler; -} i2c_to_flexcomm_t; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Waits for Master Pending status bit to set and check for bus error status. - * - * @param base The I2C peripheral base address. - * @return Bus status. - */ -static status_t I2C_PendingStatusWait(I2C_Type *base); - -/*! - * @brief Prepares the transfer state machine and fills in the command buffer. - * @param base The I2C peripheral base address. - * @param handle Master nonblocking driver handle. - * @param xfer The I2C transfer configuration structure. - */ -static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Resets the slave hardware state machine. - * According to documentation, after disabling slave to rest the slave hardware state machine, the register - * configuration remains unchanged. - * @param base The I2C peripheral base address. - */ -static void I2C_SlaveInternalStateMachineReset(I2C_Type *base); - -/*! - * @brief Compute CLKDIV - * - * This function computes CLKDIV value according to the given bus speed and Flexcomm source clock frequency. - * This setting is used by hardware during slave clock stretching. - * - * @param base The I2C peripheral base address. - * @return status of the operation - */ -static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal); - -/*! - * @brief Poll wait for the SLVPENDING flag. - * - * Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register. - * - * @param base The I2C peripheral base address. - * @return status register at time the SLVPENDING bit is read as set - */ -static uint32_t I2C_SlavePollPending(I2C_Type *base); - -/*! - * @brief Invoke event from I2C_SlaveTransferHandleIRQ(). - * - * Sets the event type to transfer structure and invokes the event callback, if it has been - * enabled by eventMask. - * - * @param base The I2C peripheral base address. - * @param handle The I2C slave handle for non-blocking APIs. - * @param event The I2C slave event to invoke. - */ -static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event); - -/*! - * @brief Handle slave address match event. - * - * Called by Slave interrupt routine to ACK or NACK the matched address. - * It also determines master direction (read or write). - * - * @param base The I2C peripheral base address. - * @return true if the matched address is ACK'ed - * @return false if the matched address is NACK'ed - */ -static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle); - -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. - * @param txData Data to be transmitted to master in response to master read from slave requests. NULL if slave RX only. - * @param txSize Size of txData buffer in bytes. - * @param rxData Data where received data from master will be stored in response to master write to slave requests. NULL - * if slave TX only. - * @param rxSize Size of rxData buffer in bytes. - * @retval #kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, - i2c_slave_handle_t *handle, - const void *txData, - size_t txSize, - void *rxData, - size_t rxSize, - uint32_t eventMask); - -/*! - * @brief Execute master transfer software state machine until FIFOs are exhausted. - * - * For master transmit, the states would be kStartState->kTransmitSubaddrState->kTransmitDataState->kStopState - * For master receive, the states would be kStartState->kTransmitSubaddrState->kStartState->kReceiveDataState-> - * kWaitForCompletionState - * - * @param handle Master nonblocking driver handle. - * @param[out] isDone Set to true if the transfer has completed. - * @retval #kStatus_Success - * @retval #kStatus_I2C_ArbitrationLost - * @retval #kStatus_I2C_Nak - */ -static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone); - -/*! - * @brief Checks the slave response to master's start signal. - * - * @param base I2C peripheral base address. - * @retval kStatus_Success Successfully complete the data transmission. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStataus_I2C_Nak Transfer error, receive NAK during addressing. - */ -static status_t I2C_MasterCheckStartResponse(I2C_Type *base); -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map i2c instance number to base address. */ -static const uint32_t s_i2cBaseAddrs[FSL_FEATURE_SOC_I2C_COUNT] = I2C_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_i2cIRQ[] = I2C_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * param base The I2C peripheral base address. - * return I2C instance number starting from 0. - */ -uint32_t I2C_GetInstance(I2C_Type *base) -{ - uint32_t i; - for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_I2C_COUNT; i++) - { - if ((uint32_t)base == s_i2cBaseAddrs[i]) - { - break; - } - } - assert(i < (uint32_t)FSL_FEATURE_SOC_I2C_COUNT); - return i; -} - -/*! - * brief Provides a default configuration for the I2C master peripheral. - * - * This function provides the following default configuration for the I2C master peripheral: - * code - * masterConfig->enableMaster = true; - * masterConfig->baudRate_Bps = 100000U; - * masterConfig->enableTimeout = false; - * endcode - * - * After calling this function, you can override any settings in order to customize the configuration, - * prior to initializing the master driver with I2C_MasterInit(). - * - * param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. - */ -void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) -{ - /* Initializes the configure structure to zero. */ - (void)memset(masterConfig, 0, sizeof(*masterConfig)); - - masterConfig->enableMaster = true; - masterConfig->baudRate_Bps = 100000U; - masterConfig->enableTimeout = false; - masterConfig->timeout_Ms = 35; -} - -/*! - * brief Initializes the I2C master peripheral. - * - * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user - * provided configuration. A software reset is performed prior to configuration. - * - * param base The I2C peripheral base address. - * param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of - * defaults - * that you can override. - * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, - * filter widths, and timeout periods. - */ -void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) -{ - (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); - I2C_MasterEnable(base, masterConfig->enableMaster); - I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); - I2C_MasterSetTimeoutValue(base, masterConfig->timeout_Ms, srcClock_Hz); -} - -/*! - * brief Deinitializes the I2C master peripheral. - * - * This function disables the I2C master peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * param base The I2C peripheral base address. - */ -void I2C_MasterDeinit(I2C_Type *base) -{ - I2C_MasterEnable(base, false); -} - -/*! - * brief Gets the I2C status flags. - * - * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit - * in the return value is set if the flag is asserted. - * - * param base The I2C peripheral base address. - * return State of the status flags: - * - 1: related status flag is set. - * - 0: related status flag is not set. - * see ref _i2c_status_flags, ref _i2c_master_status_flags and ref _i2c_slave_status_flags. - */ -uint32_t I2C_GetStatusFlags(I2C_Type *base) -{ - uint32_t statusMask = base->STAT; - if ((statusMask & (uint32_t)I2C_STAT_MSTSTATE_MASK) == 0UL) - { - statusMask |= (uint32_t)kI2C_MasterIdleFlag; - } - if (((statusMask & (uint32_t)I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == 3UL) - { - statusMask = (statusMask & ~(uint32_t)I2C_STAT_MSTSTATE_MASK) | (uint32_t)kI2C_MasterAddrNackFlag; - } - if ((statusMask & (uint32_t)I2C_STAT_SLVSTATE_MASK) == 0UL) - { - statusMask |= (uint32_t)kI2C_SlaveAddressedFlag; - } - if ((statusMask & (uint32_t)I2C_STAT_SLVIDX_MASK) == 0UL) - { - statusMask |= (uint32_t)kI2C_SlaveAddress0MatchFlag; - } - if (((statusMask & (uint32_t)I2C_STAT_SLVIDX_MASK) >> I2C_STAT_SLVIDX_SHIFT) == 3UL) - { - statusMask = (statusMask & ~(uint32_t)I2C_STAT_SLVIDX_MASK) | (uint32_t)kI2C_SlaveAddress3MatchFlag; - } - return statusMask; -} - -/*! - * brief Sets the I2C bus frequency for master transactions. - * - * The I2C master is automatically disabled and re-enabled as necessary to configure the baud - * rate. Do not call this function during a transfer, or the transfer is aborted. - * - * param base The I2C peripheral base address. - * param srcClock_Hz I2C functional clock frequency in Hertz. - * param baudRate_Bps Requested bus frequency in bits per second. - */ -void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) -{ - uint32_t scl, divider; - uint32_t mindivider; - uint32_t err, best_err; - uint32_t best_scl = 0U; - uint32_t best_div = 0U; - -#if defined(FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) && (FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) - /* - * RFT1717/RFT1437: workaround for hardware bug when using DMA - * I2C peripheral clock frequency has to be fixed at 8MHz - * source clock is 32MHz or 48MHz so divider is a round integer value - */ - best_div = srcClock_Hz / 8000000U; - best_scl = 8000000U / baudRate_Bps; - - if ((8000000U / best_scl - baudRate_Bps) > (baudRate_Bps - (8000000U / (best_scl + 1U)))) - { - best_scl = best_scl + 1U; - } - - /* - * Fallback to usual baudrate computation method, when: - * 1.Master SCL frequency does not fit in workaround range, - * 2.User's setting of baudRate_Bps is 400kHz while the clock frequency after divval is larger than 2MHz - */ - if ((best_scl > 18U) || ((best_scl < 4U)) || ((baudRate_Bps == 400000U) && (srcClock_Hz / best_div > 2000000U))) - { -#endif /*FSL_FEATURE_I2C_PREPCLKFRG_8MHZ*/ - - /* Calculate the minimal divider value to make sure the clock frequency after divval is not larger than 2MHz */ - /* This is required in RM in order to generate 400kHz baudrate */ - mindivider = ((srcClock_Hz * 10U) / 2000000U + 5U) / 10U; - /* If the scl value with current mindivider is smaller than 4, which is the minimal value register can achieve, - update mindivider */ - if ((srcClock_Hz / mindivider / baudRate_Bps) < 4U) - { - mindivider = srcClock_Hz / 4U / baudRate_Bps; - } - /* Calculate the ideal div and scl value*/ - best_err = 0U; - for (divider = mindivider; divider <= 0x10000U; divider++) - { - /* Calculte ideal scl value, round up the value */ - scl = ((srcClock_Hz * 10U) / (divider * baudRate_Bps) + 5U) / 10U; - - /* adjust it if it is out of range */ - scl = (scl > 18U) ? 18U : scl; - - /* calculate error */ - err = srcClock_Hz - (baudRate_Bps * scl * divider); - if ((err < best_err) || (best_err == 0U)) - { - best_div = divider; - best_scl = scl; - best_err = err; - } - - if ((err == 0U) || (scl <= 4U)) - { - /* either exact value was found - or scl is at its min (it would be even smaller in the next iteration for sure) */ - break; - } - } -#if defined(FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) && (FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) - } -#endif /*FSL_FEATURE_I2C_PREPCLKFRG_8MHZ*/ - base->CLKDIV = I2C_CLKDIV_DIVVAL(best_div - 1U); - if (best_scl % 2U == 0U) - { - base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl / 2U - 2U) | I2C_MSTTIME_MSTSCLHIGH(best_scl / 2U - 2U); - } - else - { - base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl / 2U - 1U) | I2C_MSTTIME_MSTSCLHIGH(best_scl / 2U - 2U); - } -} - -/*! - * brief Sets the I2C bus timeout value. - * - * If the SCL signal remains low or bus does not have event longer than the timeout value, kI2C_SclTimeoutFlag or - * kI2C_EventTimeoutFlag is set. This can indicete the bus is held by slave or any fault occurs to the I2C module. - * - * param base The I2C peripheral base address. - * param timeout_Ms Timeout value in millisecond. - * param srcClock_Hz I2C functional clock frequency in Hertz. - */ -void I2C_MasterSetTimeoutValue(I2C_Type *base, uint8_t timeout_Ms, uint32_t srcClock_Hz) -{ - assert((timeout_Ms != 0U) && (srcClock_Hz != 0U)); - - /* The low 4 bits of the timout reister TIMEOUT is hard-wired to be 1, so the the time out value is always 16 times - the I2C functional clock, we only need to calculate the high bits. */ - uint32_t timeoutValue = ((uint32_t)timeout_Ms * srcClock_Hz / 16UL / 100UL + 5UL) / 10UL; - if (timeoutValue > 0x1000UL) - { - timeoutValue = 0x1000UL; - } - timeoutValue = ((timeoutValue - 1UL) << 4UL) | 0xFUL; - base->TIMEOUT = timeoutValue; -} - -static status_t I2C_PendingStatusWait(I2C_Type *base) -{ - status_t result = kStatus_Success; - uint32_t status; - -#if I2C_RETRY_TIMES != 0U - uint32_t waitTimes = I2C_RETRY_TIMES; -#endif - - do - { - status = I2C_GetStatusFlags(base); - if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) - { - result = kStatus_I2C_EventTimeout; - } - if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) - { - result = kStatus_I2C_SclLowTimeout; - } -#if defined(FSL_FEATURE_I2C_TIMEOUT_RECOVERY) && FSL_FEATURE_I2C_TIMEOUT_RECOVERY - if (result != kStatus_Success) - { - I2C_MasterEnable(base, false); - I2C_MasterEnable(base, true); - break; - } -#endif -#if I2C_RETRY_TIMES != 0U - waitTimes--; - } while (((status & (uint32_t)kI2C_MasterPendingFlag) == 0U) && (waitTimes != 0U)); - - if (waitTimes == 0U) - { -#if defined(FSL_FEATURE_I2C_TIMEOUT_RECOVERY) && FSL_FEATURE_I2C_TIMEOUT_RECOVERY - I2C_MasterEnable(base, false); - I2C_MasterEnable(base, true); -#endif - return kStatus_I2C_Timeout; - } -#else - } while ((status & (uint32_t)kI2C_MasterPendingFlag) == 0U); -#endif - - if ((status & (uint32_t)kI2C_MasterArbitrationLostFlag) != 0U) - { - result = kStatus_I2C_ArbitrationLost; - } - - if ((status & (uint32_t)kI2C_MasterStartStopErrorFlag) != 0U) - { - result = kStatus_I2C_StartStopError; - } - - /* Clear controller state. */ - I2C_ClearStatusFlags( - base, (uint32_t)kI2C_MasterAllClearFlags | (uint32_t)kI2C_EventTimeoutFlag | (uint32_t)kI2C_SclTimeoutFlag); - - return result; -} - -/*! - * brief Sends a START on the I2C bus. - * - * This function is used to initiate a new master mode transfer by sending the START signal. - * The slave address is sent following the I2C START signal. - * - * param base I2C peripheral base pointer - * param address 7-bit slave device address. - * param direction Master transfer directions(transmit/receive). - * retval kStatus_Success Successfully send the start signal. - * retval kStatus_I2C_Busy Current bus is busy. - */ -status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) -{ - status_t result; - result = I2C_PendingStatusWait(base); - if (result != kStatus_Success) - { - return result; - } - - /* Write Address and RW bit to data register */ - base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1U); - /* Start the transfer */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - - return kStatus_Success; -} - -/*! - * brief Sends a STOP signal on the I2C bus. - * - * retval kStatus_Success Successfully send the stop signal. - * retval kStatus_I2C_Timeout Send stop signal failed, timeout. - */ -status_t I2C_MasterStop(I2C_Type *base) -{ - status_t result = I2C_PendingStatusWait(base); - if (result != kStatus_Success) - { - return result; - } - - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - return kStatus_Success; -} - -/*! - * brief Performs a polling send transfer on the I2C bus. - * - * Sends up to a txSize number of bytes to the previously addressed slave device. The slave may - * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this - * function returns #kStatus_I2C_Nak. - * - * param base The I2C peripheral base address. - * param txBuff The pointer to the data to be transferred. - * param txSize The length in bytes of the data to be transferred. - * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * retval kStatus_Success Data was sent successfully. - * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags) -{ - uint32_t master_state; - status_t err; - - const uint8_t *buf = (const uint8_t *)txBuff; - - assert(txBuff != NULL); - - err = kStatus_Success; - while (txSize != 0U) - { - err = I2C_PendingStatusWait(base); - - if (err != kStatus_Success) - { - return err; - } - - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - switch (master_state) - { - case I2C_STAT_MSTCODE_TXREADY: - /* ready to send next byte */ - base->MSTDAT = *buf++; - txSize--; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - break; - - case I2C_STAT_MSTCODE_NACKADR: - case I2C_STAT_MSTCODE_NACKDAT: - err = kStatus_I2C_Nak; - /* Issue nack signal when nacked by slave. */ - (void)I2C_MasterStop(base); - break; - - default: - /* unexpected state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - if (err != kStatus_Success) - { - return err; - } - } - - err = I2C_PendingStatusWait(base); - - if (err != kStatus_Success) - { - return err; - } - -#if !I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK - /* Check nack signal. If master is nacked by slave of the last byte, return kStatus_I2C_Nak. */ - if (((base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == (uint32_t)I2C_STAT_MSTCODE_NACKDAT) - { - (void)I2C_MasterStop(base); - return kStatus_I2C_Nak; - } -#endif - - if (0U == (flags & (uint32_t)kI2C_TransferNoStopFlag)) - { - /* Initiate stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - err = I2C_PendingStatusWait(base); - if (err != kStatus_Success) - { - return err; - } - } - - return kStatus_Success; -} - -/*! - * brief Performs a polling receive transfer on the I2C bus. - * - * param base The I2C peripheral base address. - * param rxBuff The pointer to the data to be transferred. - * param rxSize The length in bytes of the data to be transferred. - * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * retval kStatus_Success Data was received successfully. - * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags) -{ - uint32_t master_state; - status_t err; - - uint8_t *buf = (uint8_t *)(rxBuff); - - assert(rxBuff != NULL); - - err = kStatus_Success; - while (rxSize != 0U) - { - err = I2C_PendingStatusWait(base); - - if (err != kStatus_Success) - { - return err; - } - - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - switch (master_state) - { - case I2C_STAT_MSTCODE_RXREADY: - /* ready to send next byte */ - *(buf++) = (uint8_t)base->MSTDAT; - if (--rxSize != 0U) - { - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - } - else - { - if ((flags & (uint32_t)kI2C_TransferNoStopFlag) == 0U) - { - /* initiate NAK and stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - err = I2C_PendingStatusWait(base); - } - } - break; - - case I2C_STAT_MSTCODE_NACKADR: - case I2C_STAT_MSTCODE_NACKDAT: - /* slave nacked the last byte */ - err = kStatus_I2C_Nak; - break; - - default: - /* unexpected state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - if (err != kStatus_Success) - { - return err; - } - } - - return kStatus_Success; -} - -static status_t I2C_MasterCheckStartResponse(I2C_Type *base) -{ - /* Wait for start signal to be transmitted. */ - status_t result = I2C_PendingStatusWait(base); - - if (result != kStatus_Success) - { - return result; - } - - if (((base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == I2C_STAT_MSTCODE_NACKADR) - { - (void)I2C_MasterStop(base); - return kStatus_I2C_Addr_Nak; - } - return kStatus_Success; -} - -/*! - * brief Performs a master polling transfer on the I2C bus. - * - * note The API does not return until the transfer succeeds or fails due - * to arbitration lost or receiving a NAK. - * - * param base I2C peripheral base address. - * param xfer Pointer to the transfer structure. - * retval kStatus_Success Successfully complete the data transmission. - * retval kStatus_I2C_Busy Previous transmission still not finished. - * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - * retval kStataus_I2C_Addr_Nak Transfer error, receive NAK during addressing. - */ -status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) -{ - status_t result = kStatus_Success; - uint32_t subaddress; - uint8_t subaddrBuf[4]; - i2c_direction_t direction; - int i; - - assert(xfer != NULL); - - /* If start signal is requested, send start signal. */ - if (0U == (xfer->flags & (uint32_t)kI2C_TransferNoStartFlag)) - { - direction = (xfer->subaddressSize != 0U) ? kI2C_Write : xfer->direction; - result = I2C_MasterStart(base, xfer->slaveAddress, direction); - if (result == kStatus_Success) - { - result = I2C_MasterCheckStartResponse(base); - if (result != kStatus_Success) - { - return result; - } - if ((xfer->subaddressSize) != 0U) - { - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) - { - subaddrBuf[i] = (uint8_t)subaddress & 0xffU; - subaddress >>= 8; - } - /* Send subaddress. */ - result = - I2C_MasterWriteBlocking(base, subaddrBuf, xfer->subaddressSize, (uint32_t)kI2C_TransferNoStopFlag); - if (result != kStatus_Success) - { - if (result == kStatus_I2C_Nak) - { - (void)I2C_MasterStop(base); - return kStatus_I2C_Addr_Nak; - } - } - else if (xfer->direction == kI2C_Read) - { - result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction); - if (result == kStatus_Success) - { - result = I2C_MasterCheckStartResponse(base); - if (result != kStatus_Success) - { - return result; - } - } - } - else - { - /* Empty else block to avoid MISRA 14.1 violation. */ - } - } - } - } - - if (result == kStatus_Success) - { - if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0U)) - { - /* Transmit data. */ - result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); - } - else - { - if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0U)) - { - /* Receive Data. */ - result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags); - } - } - } - - if (result == kStatus_I2C_Nak) - { - (void)I2C_MasterStop(base); - } - - return result; -} - -/*! - * brief Creates a new handle for the I2C master non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. - * - * param base The I2C peripheral base address. - * param[out] handle Pointer to the I2C master driver handle. - * param callback User provided pointer to the asynchronous callback function. - * param userData User provided pointer to the application callback data. - */ -void I2C_MasterTransferCreateHandle(I2C_Type *base, - i2c_master_handle_t *handle, - i2c_master_transfer_callback_t callback, - void *userData) -{ - assert(handle != NULL); - - uint32_t instance; - i2c_to_flexcomm_t handler; - handler.i2c_master_handler = I2C_MasterTransferHandleIRQ; - - /* Clear out the handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Save base and instance. */ - handle->completionCallback = callback; - handle->userData = userData; - - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - (void)EnableIRQ(s_i2cIRQ[instance]); -} - -/*! - * brief Performs a non-blocking transaction on the I2C bus. - * - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - * param xfer The pointer to the transfer descriptor. - * retval kStatus_Success The transaction was started successfully. - * retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking - * transaction is already in progress. - */ -status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) -{ - status_t result; - - assert(handle != NULL); - assert(xfer != NULL); - assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); - - /* Return busy if another transaction is in progress. */ - if (handle->state != (uint8_t)kIdleState) - { - return kStatus_I2C_Busy; - } - - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - - /* Prepare transfer state machine. */ - result = I2C_InitTransferStateMachine(base, handle, xfer); - - /* Clear error flags. */ - I2C_ClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Enable I2C internal IRQ sources. */ - I2C_EnableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - - return result; -} - -/*! - * brief Returns number of bytes transferred so far. - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - * param[out] count Number of bytes transferred so far by the non-blocking transaction. - * retval kStatus_Success - * retval #kStatus_I2C_Busy - */ -status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state == (uint8_t)kIdleState) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* There is no necessity to disable interrupts as we read a single integer value */ - *count = handle->transferCount; - return kStatus_Success; -} - -/*! - * brief Terminates a non-blocking I2C master transmission early. - * - * note It is not safe to call this function from an IRQ handler that has a higher priority than the - * I2C peripheral's IRQ priority. - * - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - * retval kStatus_Success A transaction was successfully aborted. - * retval #kStatus_I2C_Timeout Timeout during polling for flags. - */ -status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) -{ - status_t result = kStatus_Success; - uint32_t master_state; - - if (handle->state != (uint8_t)kIdleState) - { - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - - /* Wait until module is ready */ - result = I2C_PendingStatusWait(base); - - if (result != kStatus_Success) - { - handle->state = (uint8_t)kIdleState; - return result; - } - - /* Get the state of the I2C module */ - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if (master_state != (uint32_t)I2C_STAT_MSTCODE_IDLE) - { - /* Send a stop command to finalize the transfer. */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - - /* Wait until the STOP is completed */ - result = I2C_PendingStatusWait(base); - - if (result != kStatus_Success) - { - handle->state = (uint8_t)kIdleState; - return result; - } - } - - /* Reset handle. */ - handle->state = (uint8_t)kIdleState; - handle->checkAddrNack = false; - } - return kStatus_Success; -} - -static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) -{ - struct _i2c_master_transfer *transfer; - - handle->transfer = *xfer; - transfer = &(handle->transfer); - - handle->transferCount = 0; - handle->remainingBytes = transfer->dataSize; - handle->buf = (uint8_t *)transfer->data; - handle->remainingSubaddr = 0; - handle->checkAddrNack = false; - - if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) - { - /* Start condition shall be ommited, switch directly to next phase */ - if (transfer->dataSize == 0U) - { - handle->state = (uint8_t)kStopState; - } - else if (handle->transfer.direction == kI2C_Write) - { - handle->state = (uint8_t)kTransmitDataState; - } - else if (handle->transfer.direction == kI2C_Read) - { - handle->state = (uint8_t)kReceiveDataBeginState; - } - else - { - return kStatus_I2C_InvalidParameter; - } - } - else - { - if (transfer->subaddressSize != 0U) - { - int i; - uint32_t subaddress; - - if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) - { - return kStatus_I2C_InvalidParameter; - } - - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) - { - handle->subaddrBuf[i] = (uint8_t)subaddress & 0xffU; - subaddress >>= 8; - } - handle->remainingSubaddr = transfer->subaddressSize; - } - handle->state = (uint8_t)kStartState; - handle->checkAddrNack = true; - } - - return kStatus_Success; -} - -static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) -{ - uint32_t status; - uint32_t master_state; - struct _i2c_master_transfer *transfer; - status_t err; - - transfer = &(handle->transfer); - bool ignoreNak = ((handle->state == (uint8_t)kWaitForCompletionState) && (handle->remainingBytes == 0U)) -#if I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK - /* If master is nacked by slave after the last byte during transmit, ignore the nack. */ - || ((handle->state == (uint8_t)kStopState) && (handle->remainingBytes == 0U)) -#endif - ; - - *isDone = false; - - status = I2C_GetStatusFlags(base); - - if ((status & I2C_STAT_MSTARBLOSS_MASK) != 0U) - { - I2C_ClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); - return kStatus_I2C_ArbitrationLost; - } - - if ((status & I2C_STAT_MSTSTSTPERR_MASK) != 0U) - { - I2C_ClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); - return kStatus_I2C_StartStopError; - } - - /* Event timeout happens when the time since last bus event has been longer than the time specified by TIMEOUT - register. eg: Start signal fails to generate, no error status is set and transfer hangs if glitch on bus happens - before, the timeout status can be used to avoid the transfer hangs indefinitely. */ - if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) - { - I2C_ClearStatusFlags(base, (uint32_t)kI2C_EventTimeoutFlag); - return kStatus_I2C_EventTimeout; - } - - /* SCL timeout happens when the slave is holding the SCL line low and the time has been longer than the time - specified by TIMEOUT register. */ - if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) - { - I2C_ClearStatusFlags(base, (uint32_t)kI2C_SclTimeoutFlag); - return kStatus_I2C_SclLowTimeout; - } - - if ((status & I2C_STAT_MSTPENDING_MASK) == 0U) - { - return kStatus_I2C_Busy; - } - - /* Get the hardware state of the I2C module */ - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - if (((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || - (master_state == (uint32_t)I2C_STAT_MSTCODE_NACKDAT)) && - (ignoreNak != true)) - { - /* Slave NACKed last byte, issue stop and return error */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = (uint8_t)kWaitForCompletionState; - /* If master is nacked during slave probe or during sending subaddress, return kStatus_I2C_ADDR_Nak. */ - if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (handle->checkAddrNack)) - { - return kStatus_I2C_Addr_Nak; - } - else /* Otherwise just return kStatus_I2C_Nak */ - { - return kStatus_I2C_Nak; - } - } - - err = kStatus_Success; - switch (handle->state) - { - case (uint8_t)kStartState: - if (handle->remainingSubaddr != 0U) - { - /* Subaddress takes precedence over the data transfer, direction is always "write" in this case */ - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1U; - handle->state = (uint8_t)kTransmitSubaddrState; - } - else if (transfer->direction == kI2C_Write) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = (handle->remainingBytes != 0U) ? (uint8_t)kTransmitDataState : (uint8_t)kStopState; - } - else - { - base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; - handle->state = (handle->remainingBytes != 0U) ? (uint8_t)kReceiveDataState : (uint8_t)kStopState; - } - /* Send start condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - break; - - case (uint8_t)kTransmitSubaddrState: - if (master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) - { - return kStatus_I2C_UnexpectedState; - } - /* Most significant subaddress byte comes first */ - base->MSTDAT = handle->subaddrBuf[handle->transfer.subaddressSize - handle->remainingSubaddr]; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - if (--(handle->remainingSubaddr) != 0U) - { - /* There are still subaddress bytes to be transmitted */ - break; - } - if (handle->remainingBytes != 0U) - { - /* There is data to be transferred, if there is write to read turnaround it is necessary to perform - * repeated start */ - handle->state = (transfer->direction == kI2C_Read) ? (uint8_t)kStartState : (uint8_t)kTransmitDataState; - } - else - { - /* No more data, schedule stop condition */ - handle->state = (uint8_t)kStopState; - } - break; - - case (uint8_t)kTransmitDataState: - handle->checkAddrNack = false; - if (master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) - { - return kStatus_I2C_UnexpectedState; - } - base->MSTDAT = *(handle->buf)++; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - if (--handle->remainingBytes == 0U) - { - /* No more data, schedule stop condition */ - handle->state = (uint8_t)kStopState; - } - handle->transferCount++; - break; - - case (uint8_t)kReceiveDataBeginState: - handle->checkAddrNack = false; - if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) - { - return kStatus_I2C_UnexpectedState; - } - (void)base->MSTDAT; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - handle->state = (uint8_t)kReceiveDataState; - break; - - case (uint8_t)kReceiveDataState: - handle->checkAddrNack = false; - if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) - { - return kStatus_I2C_UnexpectedState; - } - *(handle->buf)++ = (uint8_t)base->MSTDAT; - if (--handle->remainingBytes != 0U) - { - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - } - else - { - /* No more data expected, issue NACK and STOP right away */ - if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStopFlag)) - { - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - } - handle->state = (uint8_t)kWaitForCompletionState; - } - handle->transferCount++; - break; - - case (uint8_t)kStopState: - handle->checkAddrNack = false; - if ((transfer->flags & (uint32_t)kI2C_TransferNoStopFlag) != 0U) - { - /* Stop condition is omitted, we are done */ - *isDone = true; - handle->state = (uint8_t)kIdleState; - break; - } - /* Send stop condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = (uint8_t)kWaitForCompletionState; - break; - - case (uint8_t)kWaitForCompletionState: - *isDone = true; - handle->state = (uint8_t)kIdleState; - break; - - case (uint8_t)kIdleState: - default: - /* State machine shall not be invoked again once it enters the idle state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - return err; -} - -/*! - * brief Reusable routine to handle master interrupts. - * note This function does not need to be called unless you are reimplementing the - * nonblocking API's interrupt handler routines to add special functionality. - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - */ -void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle) -{ - bool isDone; - status_t result; - - /* Don't do anything if we don't have a valid handle. */ - if (NULL == handle) - { - return; - } - - result = I2C_RunTransferStateMachine(base, handle, &isDone); - - if ((result != kStatus_Success) || isDone) - { - /* Restore handle to idle state. */ - handle->state = (uint8_t)kIdleState; - - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - - /* Invoke callback. */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } -} - -static void I2C_SlaveInternalStateMachineReset(I2C_Type *base) -{ - I2C_SlaveEnable(base, false); /* clear SLVEN Slave enable bit */ -} - -static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal) -{ - uint32_t dataSetupTime_ns; - - switch ((uint8_t)(busSpeed)) - { - case (uint8_t)kI2C_SlaveStandardMode: - dataSetupTime_ns = 250U; - break; - - case (uint8_t)kI2C_SlaveFastMode: - dataSetupTime_ns = 100U; - break; - - case (uint8_t)kI2C_SlaveFastModePlus: - dataSetupTime_ns = 50U; - break; - - case (uint8_t)kI2C_SlaveHsMode: - dataSetupTime_ns = 10U; - break; - - default: - dataSetupTime_ns = 0U; - break; - } - - if (0U == dataSetupTime_ns) - { - return kStatus_InvalidArgument; - } - - /* divVal = (sourceClock_Hz / 1000000) * (dataSetupTime_ns / 1000) */ - *divVal = srcClock_Hz / 1000U; - *divVal = (*divVal) * dataSetupTime_ns; - *divVal = (*divVal) / 1000000U; - - if ((*divVal) > I2C_CLKDIV_DIVVAL_MASK) - { - *divVal = I2C_CLKDIV_DIVVAL_MASK; - } - - return kStatus_Success; -} - -static uint32_t I2C_SlavePollPending(I2C_Type *base) -{ - uint32_t stat; - -#if I2C_RETRY_TIMES != 0U - uint32_t waitTimes = I2C_RETRY_TIMES; -#endif - do - { - stat = base->STAT; -#if I2C_RETRY_TIMES != 0U - waitTimes--; - } while ((0U == (stat & I2C_STAT_SLVPENDING_MASK)) && (waitTimes != 0U)); - - if (waitTimes == 0U) - { - return (uint32_t)kStatus_I2C_Timeout; - } -#else - } while (0U == (stat & I2C_STAT_SLVPENDING_MASK)); -#endif - - return stat; -} - -static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event) -{ - uint32_t eventMask = handle->transfer.eventMask; - handle->transfer.event = event; - if (((handle->callback) != NULL) && ((eventMask & (uint32_t)event) != 0U)) - { - handle->callback(base, &handle->transfer, handle->userData); - - size_t txSize = handle->transfer.txSize; - size_t rxSize = handle->transfer.rxSize; - /* if after event callback we have data buffer (callback func has added new data), keep transfer busy */ - if (false == handle->isBusy) - { - if (((handle->transfer.txData != NULL) && (txSize != 0U)) || - ((handle->transfer.rxData != NULL) && (rxSize != 0U))) - { - handle->isBusy = true; - } - } - - /* Clear the transferred count now that we have a new buffer. */ - if ((event == kI2C_SlaveReceiveEvent) || (event == kI2C_SlaveTransmitEvent)) - { - handle->transfer.transferredCount = 0; - } - } -} - -static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle) -{ - uint8_t addressByte0; - size_t txSize; - size_t rxSize; - - addressByte0 = (uint8_t)base->SLVDAT; - - /* store the matched address */ - handle->transfer.receivedAddress = addressByte0; - - /* R/nW */ - if ((addressByte0 & 1U) != 0U) - { - txSize = handle->transfer.txSize; - /* if we have no data in this transfer, call callback to get new */ - if ((handle->transfer.txData == NULL) || (txSize == 0U)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); - } - - txSize = handle->transfer.txSize; - /* NACK if we have no data in this transfer. */ - if ((handle->transfer.txData == NULL) || (txSize == 0U)) - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - return false; - } - - /* master wants to read, so slave transmit is next state */ - handle->slaveFsm = kI2C_SlaveFsmTransmit; - } - else - { - rxSize = handle->transfer.rxSize; - /* if we have no receive buffer in this transfer, call callback to get new */ - if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); - } - - rxSize = handle->transfer.rxSize; - /* NACK if we have no data in this transfer */ - if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - return false; - } - - /* master wants write, so slave receive is next state */ - handle->slaveFsm = kI2C_SlaveFsmReceive; - } - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - return true; -} - -static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, - i2c_slave_handle_t *handle, - const void *txData, - size_t txSize, - void *rxData, - size_t rxSize, - uint32_t eventMask) -{ - assert(handle != NULL); - - status_t status; - status = kStatus_Success; - - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); - - /* Return busy if another transaction is in progress. */ - if (handle->isBusy) - { - status = kStatus_I2C_Busy; - } - - /* Save transfer into handle. */ - handle->transfer.txData = (const uint8_t *)txData; - handle->transfer.txSize = txSize; - handle->transfer.rxData = (uint8_t *)rxData; - handle->transfer.rxSize = rxSize; - handle->transfer.transferredCount = 0; - handle->transfer.eventMask = eventMask | (uint32_t)kI2C_SlaveTransmitEvent | (uint32_t)kI2C_SlaveReceiveEvent; - handle->isBusy = true; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* Clear w1c flags. */ - base->STAT |= 0u; - - /* Enable I2C internal IRQ sources. */ - I2C_EnableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); - - return status; -} - -/*! - * brief Starts accepting master read from slave requests. - * - * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * param base The I2C peripheral base address. - * param transfer Pointer to #i2c_slave_transfer_t structure. - * param txData Pointer to data to send to master. - * param txSize Size of txData in bytes. - * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * retval kStatus_Success Slave transfers were successfully started. - * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetSendBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, txData, txSize, NULL, 0u, eventMask); -} - -/*! - * brief Starts accepting master write to slave requests. - * - * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * param base The I2C peripheral base address. - * param transfer Pointer to #i2c_slave_transfer_t structure. - * param rxData Pointer to data to store data from master. - * param rxSize Size of rxData in bytes. - * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * retval kStatus_Success Slave transfers were successfully started. - * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetReceiveBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, NULL, 0u, rxData, rxSize, eventMask); -} - -/*! - * brief Configures Slave Address n register. - * - * This function writes new value to Slave Address register. - * - * param base The I2C peripheral base address. - * param addressRegister The module supports multiple address registers. The parameter determines which one shall be - * changed. - * param address The slave address to be stored to the address register for matching. - * param addressDisable Disable matching of the specified address register. - */ -void I2C_SlaveSetAddress(I2C_Type *base, - i2c_slave_address_register_t addressRegister, - uint8_t address, - bool addressDisable) -{ - base->SLVADR[addressRegister] = I2C_SLVADR_SLVADR(address) | I2C_SLVADR_SADISABLE(addressDisable); -} - -/*! - * brief Provides a default configuration for the I2C slave peripheral. - * - * This function provides the following default configuration for the I2C slave peripheral: - * code - * slaveConfig->enableSlave = true; - * slaveConfig->address0.disable = false; - * slaveConfig->address0.address = 0u; - * slaveConfig->address1.disable = true; - * slaveConfig->address2.disable = true; - * slaveConfig->address3.disable = true; - * slaveConfig->busSpeed = kI2C_SlaveStandardMode; - * endcode - * - * After calling this function, override any settings to customize the configuration, - * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the a - * address0.address member of the configuration structure with the desired slave address. - * - * param[out] slaveConfig User provided configuration structure that is set to default values. Refer to - * #i2c_slave_config_t. - */ -void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) -{ - assert(slaveConfig != NULL); - - i2c_slave_config_t mySlaveConfig = {0}; - - /* default config enables slave address 0 match to general I2C call address zero */ - mySlaveConfig.enableSlave = true; - mySlaveConfig.address1.addressDisable = true; - mySlaveConfig.address2.addressDisable = true; - mySlaveConfig.address3.addressDisable = true; - - *slaveConfig = mySlaveConfig; -} - -/*! - * brief Initializes the I2C slave peripheral. - * - * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user - * provided configuration. - * - * param base The I2C peripheral base address. - * param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults - * that you can override. - * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide - * enough - * data setup time for master when slave stretches the clock. - */ -status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz) -{ - status_t status; - uint32_t divVal = 0; - - /* configure data setup time used when slave stretches clock */ - status = I2C_SlaveDivVal(srcClock_Hz, slaveConfig->busSpeed, &divVal); - if (kStatus_Success != status) - { - return status; - } - - (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); - - /* I2C Clock Divider register */ - base->CLKDIV = divVal; - - /* set Slave address */ - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister0, slaveConfig->address0.address, - slaveConfig->address0.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister1, slaveConfig->address1.address, - slaveConfig->address1.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister2, slaveConfig->address2.address, - slaveConfig->address2.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister3, slaveConfig->address3.address, - slaveConfig->address3.addressDisable); - - /* set Slave address 0 qual */ - base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(slaveConfig->qualMode) | I2C_SLVQUAL0_SLVQUAL0(slaveConfig->qualAddress); - - /* set Slave enable */ - base->CFG = I2C_CFG_SLVEN(slaveConfig->enableSlave); - - return status; -} - -/*! - * brief Deinitializes the I2C slave peripheral. - * - * This function disables the I2C slave peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * param base The I2C peripheral base address. - */ -void I2C_SlaveDeinit(I2C_Type *base) -{ - I2C_SlaveEnable(base, false); -} - -/*! - * brief Performs a polling send transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * param base The I2C peripheral base address. - * param txBuff The pointer to the data to be transferred. - * param txSize The length in bytes of the data to be transferred. - * return kStatus_Success Data has been sent. - * return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). - */ -status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) -{ - const uint8_t *buf = txBuff; - uint32_t stat; - bool slaveAddress; - bool slaveTransmit; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - - /* Get slave machine state */ - slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); - slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_TX); - - /* in I2C_SlaveSend() it shall be either slaveAddress or slaveTransmit */ - if (!(slaveAddress || slaveTransmit)) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - if (slaveAddress) - { - /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - - /* send bytes up to txSize */ - while (txSize != 0U) - { - slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_TX); - - if (!slaveTransmit) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - /* Write 8 bits of data to the SLVDAT register */ - base->SLVDAT = I2C_SLVDAT_DATA(*buf); - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* advance counters and pointers for next data */ - buf++; - txSize--; - - if (txSize != 0U) - { - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - } - - return kStatus_Success; -} - -/*! - * brief Performs a polling receive transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * param base The I2C peripheral base address. - * param rxBuff The pointer to the data to be transferred. - * param rxSize The length in bytes of the data to be transferred. - * return kStatus_Success Data has been received. - * return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). - */ -status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) -{ - uint8_t *buf = rxBuff; - uint32_t stat; - bool slaveAddress; - bool slaveReceive; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - - /* Get slave machine state */ - slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); - slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_RX); - - /* in I2C_SlaveReceive() it shall be either slaveAddress or slaveReceive */ - if (!(slaveAddress || slaveReceive)) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - if (slaveAddress) - { - /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - - /* receive bytes up to rxSize */ - while (rxSize != 0U) - { - slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_RX); - - if (!slaveReceive) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - /* Read 8 bits of data from the SLVDAT register */ - *buf = (uint8_t)base->SLVDAT; - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* advance counters and pointers for next data */ - buf++; - rxSize--; - - if (rxSize != 0U) - { - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - } - - return kStatus_Success; -} - -/*! - * brief Creates a new handle for the I2C slave non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. - * - * param base The I2C peripheral base address. - * param[out] handle Pointer to the I2C slave driver handle. - * param callback User provided pointer to the asynchronous callback function. - * param userData User provided pointer to the application callback data. - */ -void I2C_SlaveTransferCreateHandle(I2C_Type *base, - i2c_slave_handle_t *handle, - i2c_slave_transfer_callback_t callback, - void *userData) -{ - assert(handle != NULL); - - uint32_t instance; - i2c_to_flexcomm_t handler; - handler.i2c_slave_handler = I2C_SlaveTransferHandleIRQ; - - /* Clear out the handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Save base and instance. */ - handle->callback = callback; - handle->userData = userData; - - /* initialize fsm */ - handle->slaveFsm = kI2C_SlaveFsmAddressMatch; - - /* store pointer to handle into transfer struct */ - handle->transfer.handle = handle; - - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); - (void)EnableIRQ(s_i2cIRQ[instance]); -} - -/*! - * brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. - * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. - * - * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * param base The I2C peripheral base address. - * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * retval kStatus_Success Slave transfers were successfully started. - * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, handle, NULL, 0u, NULL, 0u, eventMask); -} - -/*! - * brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. - * - * param base I2C base pointer. - * param handle pointer to i2c_slave_handle_t structure. - * param count Number of bytes transferred so far by the non-blocking transaction. - * retval kStatus_InvalidArgument count is Invalid. - * retval kStatus_Success Successfully return the count. - */ -status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (!handle->isBusy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* For an active transfer, just return the count from the handle. */ - *count = handle->transfer.transferredCount; - - return kStatus_Success; -} - -/*! - * brief Aborts the slave non-blocking transfers. - * note This API could be called at any time to stop slave for handling the bus events. - * param base The I2C peripheral base address. - * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * retval kStatus_Success - * retval #kStatus_I2C_Idle - */ -void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) -{ - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); - - /* Set the SLVEN bit to 0 in the CFG register. */ - I2C_SlaveEnable(base, false); - - handle->isBusy = false; - handle->transfer.txSize = 0U; - handle->transfer.rxSize = 0U; -} - -/*! - * brief Reusable routine to handle slave interrupts. - * note This function does not need to be called unless you are reimplementing the - * non blocking API's interrupt handler routines to add special functionality. - * param base The I2C peripheral base address. - * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - */ -void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle) -{ - uint32_t i2cStatus = base->STAT; - uint8_t tmpdata; - size_t txSize; - size_t rxSize; - - if ((i2cStatus & I2C_STAT_SLVDESEL_MASK) != 0U) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveDeselectedEvent); - I2C_SlaveClearStatusFlags(base, I2C_STAT_SLVDESEL_MASK); - } - - /* SLVPENDING flag is cleared by writing I2C_SLVCTL_SLVCONTINUE_MASK to SLVCTL register */ - if ((i2cStatus & I2C_STAT_SLVPENDING_MASK) != 0U) - { - bool slaveAddress = - (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); - - if (slaveAddress) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveAddressMatchEvent); - (void)I2C_SlaveAddressIRQ(base, handle); - } - else - { - switch (handle->slaveFsm) - { - case kI2C_SlaveFsmReceive: - { - bool slaveReceive = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == - (uint32_t)I2C_STAT_SLVST_RX); - - if (slaveReceive) - { - rxSize = handle->transfer.rxSize; - /* if we have no receive buffer in this transfer, call callback to get new */ - if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); - } - - rxSize = handle->transfer.rxSize; - /* receive a byte */ - if ((handle->transfer.rxData != NULL) && (rxSize != 0U)) - { - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - tmpdata = (uint8_t)base->SLVDAT; - *(handle->transfer.rxData) = tmpdata; - (handle->transfer.rxSize)--; - (handle->transfer.rxData)++; - (handle->transfer.transferredCount)++; - } - - rxSize = handle->transfer.rxSize; - txSize = handle->transfer.txSize; - /* is this last transaction for this transfer? allow next transaction */ - if ((0U == rxSize) && (0U == txSize)) - { - handle->isBusy = false; - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); - } - } - else - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - } - } - break; - - case kI2C_SlaveFsmTransmit: - { - bool slaveTransmit = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == - (uint32_t)I2C_STAT_SLVST_TX); - - if (slaveTransmit) - { - txSize = handle->transfer.txSize; - /* if we have no data in this transfer, call callback to get new */ - if ((handle->transfer.txData == NULL) || (txSize == 0U)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); - } - - txSize = handle->transfer.txSize; - /* transmit a byte */ - if ((handle->transfer.txData != NULL) && (txSize != 0U)) - { - base->SLVDAT = *(handle->transfer.txData); - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - (handle->transfer.txSize)--; - (handle->transfer.txData)++; - (handle->transfer.transferredCount)++; - } - - rxSize = handle->transfer.rxSize; - txSize = handle->transfer.txSize; - /* is this last transaction for this transfer? allow next transaction */ - if ((0U == rxSize) && (0U == txSize)) - { - handle->isBusy = false; - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); - } - } - else - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - } - } - break; - - default: - /* incorrect state, slv_abort()? */ - break; - } - } - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2c.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2c.h deleted file mode 100644 index b521a1ad756..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2c.h +++ /dev/null @@ -1,1148 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2C_H_ -#define _FSL_I2C_H_ - -#include -#include "fsl_device_registers.h" -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define I2C_CFG_MASK 0x1f - -/*! - * @addtogroup i2c_driver - * @{ - */ - -/*! @file */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2C driver version. */ -#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) -/*@}*/ - -/*! @brief Retry times for waiting flag. */ -#ifndef I2C_RETRY_TIMES -#define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ -#endif - -/*! @brief Whether to ignore the nack signal of the last byte during master transmit. */ -#ifndef I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK -#define I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK \ - 1U /* Define to one means master ignores the last byte's nack and considers the transfer successful. */ -#endif - -/* definitions for MSTCODE bits in I2C Status register STAT */ -#define I2C_STAT_MSTCODE_IDLE (0U) /*!< Master Idle State Code */ -#define I2C_STAT_MSTCODE_RXREADY (1U) /*!< Master Receive Ready State Code */ -#define I2C_STAT_MSTCODE_TXREADY (2U) /*!< Master Transmit Ready State Code */ -#define I2C_STAT_MSTCODE_NACKADR (3U) /*!< Master NACK by slave on address State Code */ -#define I2C_STAT_MSTCODE_NACKDAT (4U) /*!< Master NACK by slave on data State Code */ - -/* definitions for SLVSTATE bits in I2C Status register STAT */ -#define I2C_STAT_SLVST_ADDR (0) -#define I2C_STAT_SLVST_RX (1) -#define I2C_STAT_SLVST_TX (2) - -/*! @brief I2C status return codes. */ -enum -{ - kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 0), /*!< The master is already performing a transfer. */ - kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 1), /*!< The slave driver is idle. */ - kStatus_I2C_Nak = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 2), /*!< The slave device sent a NAK in response to a byte. */ - kStatus_I2C_InvalidParameter = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 3), /*!< Unable to proceed due to invalid parameter. */ - kStatus_I2C_BitError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 4), /*!< Transferred bit was not seen on the bus. */ - kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 5), /*!< Arbitration lost error. */ - kStatus_I2C_NoTransferInProgress = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 6), /*!< Attempt to abort a transfer when one is not in progress. */ - kStatus_I2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */ - kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8), /*!< Start and stop error. */ - kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9), /*!< Unexpected state. */ - kStatus_I2C_Timeout = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, - 10), /*!< Timeout when waiting for I2C master/slave pending status to set to continue transfer. */ - kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 11), /*!< NAK received for Address */ - kStatus_I2C_EventTimeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 12), /*!< Timeout waiting for bus event. */ - kStatus_I2C_SclLowTimeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 13), /*!< Timeout SCL signal remains low. */ -}; - -/*! @} */ - -/*! - * @addtogroup i2c_driver - * @{ - */ - -/*! - * @brief I2C status flags. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -enum _i2c_status_flags -{ - kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. bit 0 */ - kI2C_MasterArbitrationLostFlag = - I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus. bit 4*/ - kI2C_MasterStartStopErrorFlag = - I2C_STAT_MSTSTSTPERR_MASK, /*!< There was an error during start or stop phase of the transaction. bit 6 */ - kI2C_MasterIdleFlag = 1UL << 5U, /*!< The I2C master idle status. bit 5 */ - kI2C_MasterRxReadyFlag = 1UL << I2C_STAT_MSTSTATE_SHIFT, /*!< The I2C master rx ready status. bit 1 */ - kI2C_MasterTxReadyFlag = 1UL << (I2C_STAT_MSTSTATE_SHIFT + 1U), /*!< The I2C master tx ready status. bit 2 */ - kI2C_MasterAddrNackFlag = 1UL << 7U, /*!< The I2C master address nack status. bit 7 */ - kI2C_MasterDataNackFlag = 1UL << (I2C_STAT_MSTSTATE_SHIFT + 2U), /*!< The I2C master data nack status. bit 3 */ - kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. bit 8 */ - kI2C_SlaveNotStretching = I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 - = yes, 1 = no). bit 11 */ - kI2C_SlaveSelected = - I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. bit 14 */ - kI2C_SaveDeselected = I2C_STAT_SLVDESEL_MASK, /*!< Indicates that slave was previously deselected (deselect event - took place, w1c). bit 15 */ - kI2C_SlaveAddressedFlag = 1UL << 22U, /*!< One of the I2C slave's 4 addresses is matched. bit 22 */ - kI2C_SlaveReceiveFlag = 1UL << I2C_STAT_SLVSTATE_SHIFT, /*!< Slave receive data available. bit 9 */ - kI2C_SlaveTransmitFlag = 1UL << (I2C_STAT_SLVSTATE_SHIFT + 1U), /*!< Slave data can be transmitted. bit 10 */ - kI2C_SlaveAddress0MatchFlag = 1UL << 20U, /*!< Slave address0 match. bit 20 */ - kI2C_SlaveAddress1MatchFlag = 1UL << I2C_STAT_SLVIDX_SHIFT, /*!< Slave address1 match. bit 12 */ - kI2C_SlaveAddress2MatchFlag = 1UL << (I2C_STAT_SLVIDX_SHIFT + 1U), /*!< Slave address2 match. bit 13 */ - kI2C_SlaveAddress3MatchFlag = 1UL << 21U, /*!< Slave address3 match. bit 21 */ - kI2C_MonitorReadyFlag = I2C_STAT_MONRDY_MASK, /*!< The I2C monitor ready interrupt. bit 16 */ - kI2C_MonitorOverflowFlag = I2C_STAT_MONOV_MASK, /*!< The monitor data overrun interrupt. bit 17 */ - kI2C_MonitorActiveFlag = I2C_STAT_MONACTIVE_MASK, /*!< The monitor is active. bit 18 */ - kI2C_MonitorIdleFlag = I2C_STAT_MONIDLE_MASK, /*!< The monitor idle interrupt. bit 19 */ - kI2C_EventTimeoutFlag = I2C_STAT_EVENTTIMEOUT_MASK, /*!< The bus event timeout interrupt. bit 24 */ - kI2C_SclTimeoutFlag = I2C_STAT_SCLTIMEOUT_MASK, /*!< The SCL timeout interrupt. bit 25 */ - - /* All master flags that can be cleared by software */ - kI2C_MasterAllClearFlags = kI2C_MasterArbitrationLostFlag | kI2C_MasterStartStopErrorFlag, - /* All slave flags that can be cleared by software */ - kI2C_SlaveAllClearFlags = kI2C_SaveDeselected, - /* All common flags that can be cleared by software */ - kI2C_CommonAllClearFlags = - kI2C_MonitorOverflowFlag | kI2C_MonitorIdleFlag | kI2C_EventTimeoutFlag | kI2C_SclTimeoutFlag, -}; - -/*! - * @brief I2C interrupt enable. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -enum _i2c_interrupt_enable -{ - kI2C_MasterPendingInterruptEnable = - I2C_STAT_MSTPENDING_MASK, /*!< The I2C master communication pending interrupt. */ - kI2C_MasterArbitrationLostInterruptEnable = - I2C_STAT_MSTARBLOSS_MASK, /*!< The I2C master arbitration lost interrupt. */ - kI2C_MasterStartStopErrorInterruptEnable = - I2C_STAT_MSTSTSTPERR_MASK, /*!< The I2C master start/stop timing error interrupt. */ - kI2C_SlavePendingInterruptEnable = I2C_STAT_SLVPENDING_MASK, /*!< The I2C slave communication pending interrupt. */ - kI2C_SlaveNotStretchingInterruptEnable = - I2C_STAT_SLVNOTSTR_MASK, /*!< The I2C slave not streching interrupt, deep-sleep mode can be entered only when - this interrupt occurs. */ - kI2C_SlaveDeselectedInterruptEnable = I2C_STAT_SLVDESEL_MASK, /*!< The I2C slave deselection interrupt. */ - kI2C_MonitorReadyInterruptEnable = I2C_STAT_MONRDY_MASK, /*!< The I2C monitor ready interrupt. */ - kI2C_MonitorOverflowInterruptEnable = I2C_STAT_MONOV_MASK, /*!< The monitor data overrun interrupt. */ - kI2C_MonitorIdleInterruptEnable = I2C_STAT_MONIDLE_MASK, /*!< The monitor idle interrupt. */ - kI2C_EventTimeoutInterruptEnable = I2C_STAT_EVENTTIMEOUT_MASK, /*!< The bus event timeout interrupt. */ - kI2C_SclTimeoutInterruptEnable = I2C_STAT_SCLTIMEOUT_MASK, /*!< The SCL timeout interrupt. */ - - /* All master interrupt sources */ - kI2C_MasterAllInterruptEnable = kI2C_MasterPendingInterruptEnable | kI2C_MasterArbitrationLostInterruptEnable | - kI2C_MasterStartStopErrorInterruptEnable, - /* All slave interrupt sources */ - kI2C_SlaveAllInterruptEnable = - kI2C_SlavePendingInterruptEnable | kI2C_SlaveNotStretchingInterruptEnable | kI2C_SlaveDeselectedInterruptEnable, - /* All common interrupt sources */ - kI2C_CommonAllInterruptEnable = kI2C_MonitorReadyInterruptEnable | kI2C_MonitorOverflowInterruptEnable | - kI2C_MonitorIdleInterruptEnable | kI2C_EventTimeoutInterruptEnable | - kI2C_SclTimeoutInterruptEnable, -}; -/*! @} */ - -/*! - * @addtogroup i2c_master_driver - * @{ - */ - -/*! @brief Direction of master and slave transfers. */ -typedef enum _i2c_direction -{ - kI2C_Write = 0U, /*!< Master transmit. */ - kI2C_Read = 1U /*!< Master receive. */ -} i2c_direction_t; - -/*! - * @brief Structure with settings to initialize the I2C master module. - * - * This structure holds configuration settings for the I2C peripheral. To initialize this - * structure to reasonable defaults, call the I2C_MasterGetDefaultConfig() function and - * pass a pointer to your configuration structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _i2c_master_config -{ - bool enableMaster; /*!< Whether to enable master mode. */ - uint32_t baudRate_Bps; /*!< Desired baud rate in bits per second. */ - bool enableTimeout; /*!< Enable internal timeout function. */ - uint8_t timeout_Ms; /*!< Event timeout and SCL low timeout value. */ -} i2c_master_config_t; - -/* Forward declaration of the transfer descriptor and handle typedefs. */ -/*! @brief I2C master transfer typedef */ -typedef struct _i2c_master_transfer i2c_master_transfer_t; - -/*! @brief I2C master handle typedef */ -typedef struct _i2c_master_handle i2c_master_handle_t; - -/*! - * @brief Master completion callback function pointer type. - * - * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use - * in the call to I2C_MasterTransferCreateHandle(). - * - * @param base The I2C peripheral base address. - * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, - i2c_master_handle_t *handle, - status_t completionStatus, - void *userData); - -/*! - * @brief Transfer option flags. - * - * @note These enumerations are intended to be OR'd together to form a bit mask of options for - * the #_i2c_master_transfer::flags field. - */ -enum _i2c_master_transfer_flags -{ - kI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ - kI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ - kI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ - kI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ -}; - -/*! @brief States for the state machine used by transactional APIs. */ -enum _i2c_transfer_states -{ - kIdleState = 0, - kTransmitSubaddrState, - kTransmitDataState, - kReceiveDataBeginState, - kReceiveDataState, - kReceiveLastDataState, - kStartState, - kStopState, - kWaitForCompletionState -}; - -/*! - * @brief Non-blocking transfer descriptor structure. - * - * This structure is used to pass transaction parameters to the I2C_MasterTransferNonBlocking() API. - */ -struct _i2c_master_transfer -{ - uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i2c_master_transfer_flags for available - options. Set to 0 or #kI2C_TransferDefaultFlag for normal transfers. */ - uint8_t slaveAddress; /*!< The 7-bit slave address. */ - i2c_direction_t direction; /*!< Either #kI2C_Read or #kI2C_Write. */ - uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ - size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ - void *data; /*!< Pointer to data to transfer. */ - size_t dataSize; /*!< Number of bytes to transfer. */ -}; - -/*! - * @brief Driver handle for master non-blocking APIs. - * @note The contents of this structure are private and subject to change. - */ -struct _i2c_master_handle -{ - uint8_t state; /*!< Transfer state machine current state. */ - uint32_t transferCount; /*!< Indicates progress of the transfer */ - uint32_t remainingBytes; /*!< Remaining byte count in current state. */ - uint8_t *buf; /*!< Buffer pointer for current state. */ - uint32_t remainingSubaddr; - uint8_t subaddrBuf[4]; - bool checkAddrNack; /*!< Whether to check the nack signal is detected during addressing. */ - i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ - i2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ - void *userData; /*!< Application data passed to callback. */ -}; - -/*! @} */ - -/*! - * @addtogroup i2c_slave_driver - * @{ - */ -/*! @brief I2C slave address register. */ -typedef enum _i2c_slave_address_register -{ - kI2C_SlaveAddressRegister0 = 0U, /*!< Slave Address 0 register. */ - kI2C_SlaveAddressRegister1 = 1U, /*!< Slave Address 1 register. */ - kI2C_SlaveAddressRegister2 = 2U, /*!< Slave Address 2 register. */ - kI2C_SlaveAddressRegister3 = 3U, /*!< Slave Address 3 register. */ -} i2c_slave_address_register_t; - -/*! @brief Data structure with 7-bit Slave address and Slave address disable. */ -typedef struct _i2c_slave_address -{ - uint8_t address; /*!< 7-bit Slave address SLVADR. */ - bool addressDisable; /*!< Slave address disable SADISABLE. */ -} i2c_slave_address_t; - -/*! @brief I2C slave address match options. */ -typedef enum _i2c_slave_address_qual_mode -{ - kI2C_QualModeMask = 0U, /*!< The SLVQUAL0 field (qualAddress) is used as a logical mask for matching address0. */ - kI2C_QualModeExtend = - 1U, /*!< The SLVQUAL0 (qualAddress) field is used to extend address 0 matching in a range of addresses. */ -} i2c_slave_address_qual_mode_t; - -/*! @brief I2C slave bus speed options. */ -typedef enum _i2c_slave_bus_speed -{ - kI2C_SlaveStandardMode = 0U, - kI2C_SlaveFastMode = 1U, - kI2C_SlaveFastModePlus = 2U, - kI2C_SlaveHsMode = 3U, -} i2c_slave_bus_speed_t; - -/*! - * @brief Structure with settings to initialize the I2C slave module. - * - * This structure holds configuration settings for the I2C slave peripheral. To initialize this - * structure to reasonable defaults, call the I2C_SlaveGetDefaultConfig() function and - * pass a pointer to your configuration structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _i2c_slave_config -{ - i2c_slave_address_t address0; /*!< Slave's 7-bit address and disable. */ - i2c_slave_address_t address1; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_t address2; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_t address3; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_qual_mode_t qualMode; /*!< Qualify mode for slave address 0. */ - uint8_t qualAddress; /*!< Slave address qualifier for address 0. */ - i2c_slave_bus_speed_t - busSpeed; /*!< Slave bus speed mode. If the slave function stretches SCL to allow for software response, it must - provide sufficient data setup time to the master before releasing the stretched clock. - This is accomplished by inserting one clock time of CLKDIV at that point. - The #busSpeed value is used to configure CLKDIV - such that one clock time is greater than the tSU;DAT value noted - in the I2C bus specification for the I2C mode that is being used. - If the #busSpeed mode is unknown at compile time, use the longest data setup time - kI2C_SlaveStandardMode (250 ns) */ - bool enableSlave; /*!< Enable slave mode. */ -} i2c_slave_config_t; - -/*! - * @brief Set of events sent to the callback for non blocking slave transfers. - * - * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together - * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable. - * Then, when the slave callback is invoked, it is passed the current event through its @a transfer - * parameter. - * - * @note These enumerations are meant to be OR'd together to form a bit mask of events. - */ -typedef enum _i2c_slave_transfer_event -{ - kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ - kI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit - (slave-transmitter role). */ - kI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received - data (slave-receiver role). */ - kI2C_SlaveCompletionEvent = 0x20U, /*!< All data in the active transfer have been consumed. */ - kI2C_SlaveDeselectedEvent = - 0x40U, /*!< The slave function has become deselected (SLVSEL flag changing from 1 to 0. */ - - /*! Bit mask of all available events. */ - kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | - kI2C_SlaveCompletionEvent | kI2C_SlaveDeselectedEvent, -} i2c_slave_transfer_event_t; - -/*! @brief I2C slave handle typedef. */ -typedef struct _i2c_slave_handle i2c_slave_handle_t; - -/*! @brief I2C slave transfer structure */ -typedef struct _i2c_slave_transfer -{ - i2c_slave_handle_t *handle; /*!< Pointer to handle that contains this transfer. */ - i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ - uint8_t receivedAddress; /*!< Matching address send by master. 7-bits plus R/nW bit0 */ - uint32_t eventMask; /*!< Mask of enabled events. */ - uint8_t *rxData; /*!< Transfer buffer for receive data */ - const uint8_t *txData; /*!< Transfer buffer for transmit data */ - size_t txSize; /*!< Transfer size */ - size_t rxSize; /*!< Transfer size */ - size_t transferredCount; /*!< Number of bytes transferred during this transfer. */ - status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for - #kI2C_SlaveCompletionEvent. */ -} i2c_slave_transfer_t; - -/*! - * @brief Slave event callback function pointer type. - * - * This callback is used only for the slave non-blocking transfer API. To install a callback, - * use the I2C_SlaveSetCallback() function after you have created a handle. - * - * @param base Base address for the I2C instance on which the event occurred. - * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *userData); - -/*! - * @brief I2C slave software finite state machine states. - */ -typedef enum _i2c_slave_fsm -{ - kI2C_SlaveFsmAddressMatch = 0u, - kI2C_SlaveFsmReceive = 2u, - kI2C_SlaveFsmTransmit = 3u, -} i2c_slave_fsm_t; - -/*! - * @brief I2C slave handle structure. - * @note The contents of this structure are private and subject to change. - */ -struct _i2c_slave_handle -{ - volatile i2c_slave_transfer_t transfer; /*!< I2C slave transfer. */ - volatile bool isBusy; /*!< Whether transfer is busy. */ - volatile i2c_slave_fsm_t slaveFsm; /*!< slave transfer state machine. */ - i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ - void *userData; /*!< Callback parameter passed to callback. */ -}; - -/*! @brief Typedef for master interrupt handler. */ -typedef void (*flexcomm_i2c_master_irq_handler_t)(I2C_Type *base, i2c_master_handle_t *handle); - -/*! @brief Typedef for slave interrupt handler. */ -typedef void (*flexcomm_i2c_slave_irq_handler_t)(I2C_Type *base, i2c_slave_handle_t *handle); -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup i2c_master_driver - * @{ - */ - -/*! @name Initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the I2C master peripheral. - * - * This function provides the following default configuration for the I2C master peripheral: - * @code - * masterConfig->enableMaster = true; - * masterConfig->baudRate_Bps = 100000U; - * masterConfig->enableTimeout = false; - * @endcode - * - * After calling this function, you can override any settings in order to customize the configuration, - * prior to initializing the master driver with I2C_MasterInit(). - * - * @param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. - */ -void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); - -/*! - * @brief Initializes the I2C master peripheral. - * - * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user - * provided configuration. A software reset is performed prior to configuration. - * - * @param base The I2C peripheral base address. - * @param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of - * defaults - * that you can override. - * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, - * filter widths, and timeout periods. - */ -void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes the I2C master peripheral. - * - * This function disables the I2C master peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -void I2C_MasterDeinit(I2C_Type *base); - -/*! - * @brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * @param base The I2C peripheral base address. - * @return I2C instance number starting from 0. - */ -uint32_t I2C_GetInstance(I2C_Type *base); - -/*! - * @brief Performs a software reset. - * - * Restores the I2C master peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -static inline void I2C_MasterReset(I2C_Type *base) -{ -} - -/*! - * @brief Enables or disables the I2C module as master. - * - * @param base The I2C peripheral base address. - * @param enable Pass true to enable or false to disable the specified I2C as master. - */ -static inline void I2C_MasterEnable(I2C_Type *base, bool enable) -{ - if (enable) - { - base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK; - } - else - { - base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK; - } -} - -/*@}*/ - -/*! @name Status */ -/*@{*/ -/*! - * @brief Gets the I2C status flags. - * - * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit - * in the return value is set if the flag is asserted. - * - * @param base The I2C peripheral base address. - * @return State of the status flags: - * - 1: related status flag is set. - * - 0: related status flag is not set. - * @see @ref _i2c_status_flags. - */ -uint32_t I2C_GetStatusFlags(I2C_Type *base); - -/*! - * @brief Clears the I2C status flag state. - * - * Refer to kI2C_CommonAllClearStatusFlags, kI2C_MasterAllClearStatusFlags and kI2C_SlaveAllClearStatusFlags to see - * the clearable flags. Attempts to clear other flags has no effect. - * - * @param base The I2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of the members in - * kI2C_CommonAllClearStatusFlags, kI2C_MasterAllClearStatusFlags and kI2C_SlaveAllClearStatusFlags. You may pass - * the result of a previous call to I2C_GetStatusFlags(). - * @see #_i2c_status_flags, _i2c_master_status_flags and _i2c_slave_status_flags. - */ -static inline void I2C_ClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - /* Only deal with the clearable flags */ - statusMask &= - ((uint32_t)kI2C_CommonAllClearFlags | (uint32_t)kI2C_MasterAllClearFlags | (uint32_t)kI2C_SlaveAllClearFlags); - base->STAT = statusMask; -} - -/*! - * @brief Clears the I2C master status flag state. - * @deprecated Do not use this function. It has been superceded by @ref I2C_ClearStatusFlags - * The following status register flags can be cleared: - * - #kI2C_MasterArbitrationLostFlag - * - #kI2C_MasterStartStopErrorFlag - * - * Attempts to clear other flags has no effect. - * - * @param base The I2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * #_i2c_status_flags enumerators OR'd together. You may pass the result of a previous call to - * I2C_GetStatusFlags(). - * @see _i2c_status_flags. - */ -static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - /* Allow clearing just master status flags */ - base->STAT = statusMask & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); -} - -/*@}*/ - -/*! @name Interrupts */ -/*@{*/ - -/*! - * @brief Enables the I2C interrupt requests. - * - * @param base The I2C peripheral base address. - * @param interruptMask Bit mask of interrupts to enable. See #_i2c_interrupt_enable for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2C_EnableInterrupts(I2C_Type *base, uint32_t interruptMask) -{ - base->INTENSET = interruptMask; -} - -/*! - * @brief Disables the I2C interrupt requests. - * - * @param base The I2C peripheral base address. - * @param interruptMask Bit mask of interrupts to disable. See #_i2c_interrupt_enable for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2C_DisableInterrupts(I2C_Type *base, uint32_t interruptMask) -{ - base->INTENCLR = interruptMask; -} - -/*! - * @brief Returns the set of currently enabled I2C interrupt requests. - * - * @param base The I2C peripheral base address. - * @return A bitmask composed of #_i2c_interrupt_enable enumerators OR'd together to indicate the - * set of enabled interrupts. - */ -static inline uint32_t I2C_GetEnabledInterrupts(I2C_Type *base) -{ - return base->INTSTAT; -} - -/*@}*/ - -/*! @name Bus operations */ -/*@{*/ - -/*! - * @brief Sets the I2C bus frequency for master transactions. - * - * The I2C master is automatically disabled and re-enabled as necessary to configure the baud - * rate. Do not call this function during a transfer, or the transfer is aborted. - * - * @param base The I2C peripheral base address. - * @param srcClock_Hz I2C functional clock frequency in Hertz. - * @param baudRate_Bps Requested bus frequency in bits per second. - */ -void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Sets the I2C bus timeout value. - * - * If the SCL signal remains low or bus does not have event longer than the timeout value, kI2C_SclTimeoutFlag or - * kI2C_EventTimeoutFlag is set. This can indicete the bus is held by slave or any fault occurs to the I2C module. - * - * @param base The I2C peripheral base address. - * @param timeout_Ms Timeout value in millisecond. - * @param srcClock_Hz I2C functional clock frequency in Hertz. - */ -void I2C_MasterSetTimeoutValue(I2C_Type *base, uint8_t timeout_Ms, uint32_t srcClock_Hz); - -/*! - * @brief Returns whether the bus is idle. - * - * Requires the master mode to be enabled. - * - * @param base The I2C peripheral base address. - * @retval true Bus is busy. - * @retval false Bus is idle. - */ -static inline bool I2C_MasterGetBusIdleState(I2C_Type *base) -{ - /* True if MSTPENDING flag is set and MSTSTATE is zero == idle */ - return ((base->STAT & (I2C_STAT_MSTPENDING_MASK | I2C_STAT_MSTSTATE_MASK)) == I2C_STAT_MSTPENDING_MASK); -} - -/*! - * @brief Sends a START on the I2C bus. - * - * This function is used to initiate a new master mode transfer by sending the START signal. - * The slave address is sent following the I2C START signal. - * - * @param base I2C peripheral base pointer - * @param address 7-bit slave device address. - * @param direction Master transfer directions(transmit/receive). - * @retval kStatus_Success Successfully send the start signal. - * @retval kStatus_I2C_Busy Current bus is busy. - */ -status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); - -/*! - * @brief Sends a STOP signal on the I2C bus. - * - * @retval kStatus_Success Successfully send the stop signal. - * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. - */ -status_t I2C_MasterStop(I2C_Type *base); - -/*! - * @brief Sends a REPEATED START on the I2C bus. - * - * @param base I2C peripheral base pointer - * @param address 7-bit slave device address. - * @param direction Master transfer directions(transmit/receive). - * @retval kStatus_Success Successfully send the start signal. - * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. - */ -static inline status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) -{ - return I2C_MasterStart(base, address, direction); -} - -/*! - * @brief Performs a polling send transfer on the I2C bus. - * - * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may - * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this - * function returns #kStatus_I2C_Nak. - * - * @param base The I2C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * @retval kStatus_Success Data was sent successfully. - * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags); - -/*! - * @brief Performs a polling receive transfer on the I2C bus. - * - * @param base The I2C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * @retval kStatus_Success Data was received successfully. - * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags); - -/*! - * @brief Performs a master polling transfer on the I2C bus. - * - * @note The API does not return until the transfer succeeds or fails due - * to arbitration lost or receiving a NAK. - * - * @param base I2C peripheral base address. - * @param xfer Pointer to the transfer structure. - * @retval kStatus_Success Successfully complete the data transmission. - * @retval kStatus_I2C_Busy Previous transmission still not finished. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - * @retval kStataus_I2C_Addr_Nak Transfer error, receive NAK during addressing. - */ -status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); - -/*@}*/ - -/*! @name Non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the I2C master non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. - * - * @param base The I2C peripheral base address. - * @param[out] handle Pointer to the I2C master driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void I2C_MasterTransferCreateHandle(I2C_Type *base, - i2c_master_handle_t *handle, - i2c_master_transfer_callback_t callback, - void *userData); - -/*! - * @brief Performs a non-blocking transaction on the I2C bus. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @param xfer The pointer to the transfer descriptor. - * @retval kStatus_Success The transaction was started successfully. - * @retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking - * transaction is already in progress. - */ -status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Returns number of bytes transferred so far. - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @param[out] count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_Success - * @retval #kStatus_I2C_Busy - */ -status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); - -/*! - * @brief Terminates a non-blocking I2C master transmission early. - * - * @note It is not safe to call this function from an IRQ handler that has a higher priority than the - * I2C peripheral's IRQ priority. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @retval kStatus_Success A transaction was successfully aborted. - * @retval #kStatus_I2C_Timeout Timeout during polling for flags. - */ -status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); - -/*@}*/ - -/*! @name IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle master interrupts. - * @note This function does not need to be called unless you are reimplementing the - * nonblocking API's interrupt handler routines to add special functionality. - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - */ -void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle); - -/*@}*/ - -/*! @} */ /* end of i2c_master_driver */ - -/*! - * @addtogroup i2c_slave_driver - * @{ - */ - -/*! @name Slave initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the I2C slave peripheral. - * - * This function provides the following default configuration for the I2C slave peripheral: - * @code - * slaveConfig->enableSlave = true; - * slaveConfig->address0.disable = false; - * slaveConfig->address0.address = 0u; - * slaveConfig->address1.disable = true; - * slaveConfig->address2.disable = true; - * slaveConfig->address3.disable = true; - * slaveConfig->busSpeed = kI2C_SlaveStandardMode; - * @endcode - * - * After calling this function, override any settings to customize the configuration, - * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the @a - * address0.address member of the configuration structure with the desired slave address. - * - * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to - * #i2c_slave_config_t. - */ -void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); - -/*! - * @brief Initializes the I2C slave peripheral. - * - * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user - * provided configuration. - * - * @param base The I2C peripheral base address. - * @param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults - * that you can override. - * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide - * enough - * data setup time for master when slave stretches the clock. - */ -status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz); - -/*! - * @brief Configures Slave Address n register. - * - * This function writes new value to Slave Address register. - * - * @param base The I2C peripheral base address. - * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be - * changed. - * @param address The slave address to be stored to the address register for matching. - * @param addressDisable Disable matching of the specified address register. - */ -void I2C_SlaveSetAddress(I2C_Type *base, - i2c_slave_address_register_t addressRegister, - uint8_t address, - bool addressDisable); - -/*! - * @brief Deinitializes the I2C slave peripheral. - * - * This function disables the I2C slave peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -void I2C_SlaveDeinit(I2C_Type *base); - -/*! - * @brief Enables or disables the I2C module as slave. - * - * @param base The I2C peripheral base address. - * @param enable True to enable or flase to disable. - */ -static inline void I2C_SlaveEnable(I2C_Type *base, bool enable) -{ - /* Set or clear the SLVEN bit in the CFG register. */ - base->CFG = I2C_CFG_SLVEN(enable); -} - -/*@}*/ /* end of Slave initialization and deinitialization */ - -/*! @name Slave status */ -/*@{*/ - -/*! - * @brief Clears the I2C status flag state. - * - * The following status register flags can be cleared: - * - slave deselected flag - * - * Attempts to clear other flags has no effect. - * - * @param base The I2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * _i2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to - * I2C_SlaveGetStatusFlags(). - * @see _i2c_slave_flags. - */ -static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - /* Allow clearing just slave status flags */ - base->STAT = statusMask & I2C_STAT_SLVDESEL_MASK; -} - -/*@}*/ /* end of Slave status */ - -/*! @name Slave bus operations */ -/*@{*/ - -/*! - * @brief Performs a polling send transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * @param base The I2C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @return kStatus_Success Data has been sent. - * @return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). - */ -status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); - -/*! - * @brief Performs a polling receive transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * @param base The I2C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @return kStatus_Success Data has been received. - * @return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). - */ -status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); - -/*@}*/ /* end of Slave bus operations */ - -/*! @name Slave non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the I2C slave non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. - * - * @param base The I2C peripheral base address. - * @param[out] handle Pointer to the I2C slave driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void I2C_SlaveTransferCreateHandle(I2C_Type *base, - i2c_slave_handle_t *handle, - i2c_slave_transfer_callback_t callback, - void *userData); - -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. - * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); - -/*! - * @brief Starts accepting master read from slave requests. - * - * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param transfer Pointer to #i2c_slave_transfer_t structure. - * @param txData Pointer to data to send to master. - * @param txSize Size of txData in bytes. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetSendBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask); - -/*! - * @brief Starts accepting master write to slave requests. - * - * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param transfer Pointer to #i2c_slave_transfer_t structure. - * @param rxData Pointer to data to store data from master. - * @param rxSize Size of rxData in bytes. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetReceiveBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask); - -/*! - * @brief Returns the slave address sent by the I2C master. - * - * This function should only be called from the address match event callback #kI2C_SlaveAddressMatchEvent. - * - * @param base The I2C peripheral base address. - * @param transfer The I2C slave transfer. - * @return The 8-bit address matched by the I2C slave. Bit 0 contains the R/w direction bit, and - * the 7-bit slave address is in the upper 7 bits. - */ -static inline uint32_t I2C_SlaveGetReceivedAddress(I2C_Type *base, volatile i2c_slave_transfer_t *transfer) -{ - return transfer->receivedAddress; -} - -/*! - * @brief Aborts the slave non-blocking transfers. - * @note This API could be called at any time to stop slave for handling the bus events. - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * @retval kStatus_Success - * @retval #kStatus_I2C_Idle - */ -void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); - -/*! - * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_slave_handle_t structure. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_InvalidArgument count is Invalid. - * @retval kStatus_Success Successfully return the count. - */ -status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); - -/*@}*/ /* end of Slave non-blocking */ - -/*! @name Slave IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle slave interrupts. - * @note This function does not need to be called unless you are reimplementing the - * non blocking API's interrupt handler routines to add special functionality. - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - */ -void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle); - -/*@}*/ /* end of Slave IRQ handler */ - -/*! @} */ /* end of i2c_slave_driver */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2C_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2c_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2c_dma.c deleted file mode 100644 index 45d47e59073..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2c_dma.c +++ /dev/null @@ -1,652 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_i2c_dma.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c_dma" -#endif - -/*transfer = *xfer; - transfer = &(handle->transfer); - - handle->transferCount = 0U; - handle->remainingBytesDMA = 0U; - handle->buf = (uint8_t *)transfer->data; - handle->remainingSubaddr = 0U; - - if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) - { - handle->checkAddrNack = false; - /* Start condition shall not be ommited, switch directly to next phase */ - if (transfer->dataSize == 0U) - { - handle->state = (uint8_t)kStopState; - } - else if (handle->transfer.direction == kI2C_Write) - { - handle->state = (uint8_t)kTransmitDataState; - } - else if (handle->transfer.direction == kI2C_Read) - { - handle->state = (xfer->dataSize == 1U) ? (uint8_t)kReceiveLastDataState : (uint8_t)kReceiveDataState; - } - else - { - return kStatus_I2C_InvalidParameter; - } - } - else - { - if (transfer->subaddressSize != 0U) - { - int i; - uint32_t subaddress; - - if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) - { - return kStatus_I2C_InvalidParameter; - } - - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) - { - handle->subaddrBuf[i] = (uint8_t)subaddress & 0xffU; - subaddress >>= 8; - } - handle->remainingSubaddr = transfer->subaddressSize; - } - - handle->state = (uint8_t)kStartState; - handle->checkAddrNack = true; - } - - return kStatus_Success; -} - -static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - uint32_t transfer_size; - dma_transfer_config_t xferConfig; - uint32_t address; - address = (uint32_t)&base->MSTDAT; - - /* Update transfer count */ - int32_t count = handle->buf - (uint8_t *)handle->transfer.data; - assert(count >= 0); - handle->transferCount = (uint32_t)count; - - /* Check if there is anything to be transferred at all */ - if (handle->remainingBytesDMA == 0U) - { - /* No data to be transferrred, disable DMA */ - base->MSTCTL = 0; - return; - } - - /* Calculate transfer size */ - transfer_size = handle->remainingBytesDMA; - if (transfer_size > (uint32_t)I2C_MAX_DMA_TRANSFER_COUNT) - { - transfer_size = (uint32_t)I2C_MAX_DMA_TRANSFER_COUNT; - } - - switch (handle->transfer.direction) - { - case kI2C_Write: - DMA_PrepareTransfer(&xferConfig, handle->buf, (uint32_t *)address, sizeof(uint8_t), transfer_size, - kDMA_MemoryToPeripheral, NULL); - break; - - case kI2C_Read: - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, handle->buf, sizeof(uint8_t), transfer_size, - kDMA_PeripheralToMemory, NULL); - break; - - default: - /* This should never happen */ - assert(0); - break; - } - - (void)DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - DMA_StartTransfer(handle->dmaHandle); - - handle->remainingBytesDMA -= transfer_size; - handle->buf += transfer_size; - handle->checkAddrNack = false; -} - -static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone) -{ - uint32_t status; - uint32_t master_state; - struct _i2c_master_transfer *transfer; - dma_transfer_config_t xferConfig; - status_t err; - uint32_t start_flag = 0U; - uint32_t address; - address = (uint32_t)&base->MSTDAT; - - transfer = &(handle->transfer); - - *isDone = false; - - status = I2C_GetStatusFlags(base); - - if ((status & (uint32_t)I2C_STAT_MSTARBLOSS_MASK) != 0U) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_ArbitrationLost; - } - - if ((status & (uint32_t)I2C_STAT_MSTSTSTPERR_MASK) != 0U) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_StartStopError; - } - - /* Event timeout happens when the time since last bus event has been longer than the time specified by TIMEOUT - register. eg: Start signal fails to generate, no error status is set and transfer hangs if glitch on bus happens - before, the timeout status can be used to avoid the transfer hangs indefinitely. */ - if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) - { - I2C_ClearStatusFlags(base, (uint32_t)kI2C_EventTimeoutFlag); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_EventTimeout; - } - - /* SCL timeout happens when the slave is holding the SCL line low and the time has been longer than the time - specified by TIMEOUT register. */ - if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) - { - I2C_ClearStatusFlags(base, (uint32_t)kI2C_SclTimeoutFlag); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_SclLowTimeout; - } - - if ((status & (uint32_t)I2C_STAT_MSTPENDING_MASK) == 0U) - { - return kStatus_I2C_Busy; - } - - /* Get the state of the I2C module */ - master_state = (base->STAT & (uint32_t)I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (master_state == (uint32_t)I2C_STAT_MSTCODE_NACKDAT)) - { - /* Slave NACKed last byte, issue stop and return error */ - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = (uint8_t)kWaitForCompletionState; - if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (handle->checkAddrNack == true)) - { - return kStatus_I2C_Addr_Nak; - } - else - { - return kStatus_I2C_Nak; - } - } - - err = kStatus_Success; - - if (handle->state == (uint8_t)kStartState) - { - /* set start flag for later use */ - start_flag = I2C_MSTCTL_MSTSTART_MASK; - - if (handle->remainingSubaddr != 0U) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = (uint8_t)kTransmitSubaddrState; - } - else if (transfer->direction == kI2C_Write) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - if (transfer->dataSize == 0U) - { - /* No data to be transferred, initiate start and schedule stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - handle->state = (uint8_t)kStopState; - return err; - } - handle->state = (uint8_t)kTransmitDataState; - } - else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0U)) - { - base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; - if (transfer->dataSize == 1U) - { - /* The very last byte is always received by means of SW */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - handle->state = (uint8_t)kReceiveLastDataState; - return err; - } - handle->state = (uint8_t)kReceiveDataState; - } - else - { - handle->state = (uint8_t)kIdleState; - err = kStatus_I2C_UnexpectedState; - return err; - } - } - - switch (handle->state) - { - case (uint8_t)kTransmitSubaddrState: - if ((master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) && (0U == start_flag)) - { - return kStatus_I2C_UnexpectedState; - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - - /* Prepare and submit DMA transfer. */ - DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (uint32_t *)address, sizeof(uint8_t), - handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL); - (void)DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - DMA_StartTransfer(handle->dmaHandle); - handle->remainingSubaddr = 0; - if (transfer->dataSize != 0U) - { - /* There is data to be transferred, if there is write to read turnaround it is necessary to perform - * repeated start */ - handle->state = (transfer->direction == kI2C_Read) ? (uint8_t)kStartState : (uint8_t)kTransmitDataState; - } - else - { - /* No more data, schedule stop condition */ - handle->state = (uint8_t)kStopState; - } - break; - - case (uint8_t)kTransmitDataState: - if ((master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) && (0U == start_flag)) - { - return kStatus_I2C_UnexpectedState; - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - handle->remainingBytesDMA = handle->transfer.dataSize; - - I2C_RunDMATransfer(base, handle); - - /* Schedule stop condition */ - handle->state = (uint8_t)kStopState; - handle->checkAddrNack = false; - break; - - case (uint8_t)kReceiveDataState: - if ((master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) && (0U == start_flag)) - { - if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStartFlag)) - { - return kStatus_I2C_UnexpectedState; - } - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - handle->remainingBytesDMA = handle->transfer.dataSize - 1U; - - if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) - { - /* Read the master data register to avoid the data be read again */ - (void)base->MSTDAT; - } - I2C_RunDMATransfer(base, handle); - - /* Schedule reception of last data byte */ - handle->state = (uint8_t)kReceiveLastDataState; - handle->checkAddrNack = false; - break; - - case (uint8_t)kReceiveLastDataState: - if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) - { - return kStatus_I2C_UnexpectedState; - } - - ((uint8_t *)transfer->data)[transfer->dataSize - 1U] = (uint8_t)base->MSTDAT; - handle->transferCount++; - - /* No more data expected, issue NACK and STOP right away */ - if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStopFlag)) - { - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - } - handle->state = (uint8_t)kWaitForCompletionState; - break; - - case (uint8_t)kStopState: - if ((transfer->flags & (uint32_t)kI2C_TransferNoStopFlag) != 0U) - { - /* Stop condition is omitted, we are done */ - *isDone = true; - handle->state = (uint8_t)kIdleState; - break; - } - /* Send stop condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = (uint8_t)kWaitForCompletionState; - break; - - case (uint8_t)kWaitForCompletionState: - *isDone = true; - handle->state = (uint8_t)kIdleState; - break; - - case (uint8_t)kStartState: - case (uint8_t)kIdleState: - default: - /* State machine shall not be invoked again once it enters the idle state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - return err; -} - -static void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - bool isDone; - status_t result; - - /* Don't do anything if we don't have a valid handle. */ - if (NULL == handle) - { - return; - } - - result = I2C_RunTransferStateMachineDMA(base, handle, &isDone); - - if ((result != kStatus_Success) || isDone) - { - /* Restore handle to idle state. */ - handle->state = (uint8_t)kIdleState; - - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | - I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); - - /* Invoke callback. */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } -} - -static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) -{ - i2c_master_dma_private_handle_t *dmaPrivateHandle; - - /* Don't do anything if we don't have a valid handle. */ - if (NULL == handle) - { - return; - } - - dmaPrivateHandle = (i2c_master_dma_private_handle_t *)userData; - I2C_RunDMATransfer(dmaPrivateHandle->base, dmaPrivateHandle->handle); -} - -/*! - * brief Init the I2C handle which is used in transactional functions - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - * param callback pointer to user callback function - * param userData user param passed to the callback function - * param dmaHandle DMA handle pointer - */ -void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, - i2c_master_dma_handle_t *handle, - i2c_master_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *dmaHandle) -{ - assert(handle != NULL); - assert(dmaHandle != NULL); - - uint32_t instance; - i2c_dma_to_flexcomm_t handler; - handler.i2c_dma_master_handler = I2C_MasterTransferDMAHandleIRQ; - - /* Zero handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Set the user callback and userData. */ - handle->completionCallback = callback; - handle->userData = userData; - - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | - I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); - (void)EnableIRQ(s_i2cIRQ[instance]); - - /* Set the handle for DMA. */ - handle->dmaHandle = dmaHandle; - - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - DMA_SetCallback(dmaHandle, I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]); -} - -/*! - * brief Performs a master dma non-blocking transfer on the I2C bus - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - * param xfer pointer to transfer structure of i2c_master_transfer_t - * retval kStatus_Success Sucessully complete the data transmission. - * retval kStatus_I2C_Busy Previous transmission still not finished. - * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. - */ -status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer) -{ - status_t result; - - assert(handle != NULL); - assert(xfer != NULL); - assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); - - /* Return busy if another transaction is in progress. */ - if (handle->state != (uint8_t)kIdleState) - { - return kStatus_I2C_Busy; - } - - /* Prepare transfer state machine. */ - result = I2C_InitTransferStateMachineDMA(base, handle, xfer); - - /* Clear error flags. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Enable I2C internal IRQ sources */ - /* Enable arbitration lost interrupt, start/stop error interrupt and master pending interrupt. - The master pending flag is not set during dma transfer. */ - I2C_EnableInterrupts(base, I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | - I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); - - return result; -} - -/*! - * brief Get master transfer status during a dma non-blocking transfer - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - * param count Number of bytes transferred so far by the non-blocking transaction. - */ -status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state == (uint8_t)kIdleState) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* There is no necessity to disable interrupts as we read a single integer value */ - *count = handle->transferCount; - return kStatus_Success; -} - -/*! - * brief Abort a master dma non-blocking transfer in a early time - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - */ -void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - uint32_t status; - uint32_t master_state; - - if (handle->state != (uint8_t)kIdleState) - { - DMA_AbortTransfer(handle->dmaHandle); - - /* Disable DMA */ - base->MSTCTL = 0; - - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | - I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); - - /* Wait until module is ready */ - do - { - status = I2C_GetStatusFlags(base); - } while ((status & (uint8_t)I2C_STAT_MSTPENDING_MASK) == 0U); - - /* Clear controller state. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Get the state of the I2C module */ - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if (master_state != (uint32_t)I2C_STAT_MSTCODE_IDLE) - { - /* Send a stop command to finalize the transfer. */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - - /* Wait until module is ready */ - do - { - status = I2C_GetStatusFlags(base); - } while ((status & (uint32_t)I2C_STAT_MSTPENDING_MASK) == 0U); - - /* Clear controller state. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - } - - /* Reset the state to idle. */ - handle->state = (uint8_t)kIdleState; - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2c_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2c_dma.h deleted file mode 100644 index 07899f9c7c9..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2c_dma.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2C_DMA_H_ -#define _FSL_I2C_DMA_H_ - -#include "fsl_i2c.h" -#include "fsl_dma.h" - -/*! - * @addtogroup i2c_dma_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2C DMA driver version. */ -#define FSL_I2C_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) -/*@}*/ - -/*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */ -#define I2C_MAX_DMA_TRANSFER_COUNT 1024 - -/*! @brief I2C master dma handle typedef. */ -typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t; - -/*! @brief I2C master dma transfer callback typedef. */ -typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base, - i2c_master_dma_handle_t *handle, - status_t status, - void *userData); - -/*! @brief Typedef for master dma handler. */ -typedef void (*flexcomm_i2c_dma_master_irq_handler_t)(I2C_Type *base, i2c_master_dma_handle_t *handle); - -/*! @brief I2C master dma transfer structure. */ -struct _i2c_master_dma_handle -{ - uint8_t state; /*!< Transfer state machine current state. */ - uint32_t transferCount; /*!< Indicates progress of the transfer */ - uint32_t remainingBytesDMA; /*!< Remaining byte count to be transferred using DMA. */ - uint8_t *buf; /*!< Buffer pointer for current state. */ - uint32_t remainingSubaddr; - uint8_t subaddrBuf[4]; - bool checkAddrNack; /*!< Whether to check the nack signal is detected during addressing. */ - dma_handle_t *dmaHandle; /*!< The DMA handler used. */ - i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ - i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */ - void *userData; /*!< Callback parameter passed to callback function. */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus. */ - -/*! - * @name I2C Block DMA Transfer Operation - * @{ - */ - -/*! - * @brief Init the I2C handle which is used in transactional functions - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param callback pointer to user callback function - * @param userData user param passed to the callback function - * @param dmaHandle DMA handle pointer - */ -void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, - i2c_master_dma_handle_t *handle, - i2c_master_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *dmaHandle); - -/*! - * @brief Performs a master dma non-blocking transfer on the I2C bus - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param xfer pointer to transfer structure of i2c_master_transfer_t - * @retval kStatus_Success Sucessully complete the data transmission. - * @retval kStatus_I2C_Busy Previous transmission still not finished. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. - */ -status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Get master transfer status during a dma non-blocking transfer - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param count Number of bytes transferred so far by the non-blocking transaction. - */ -status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count); - -/*! - * @brief Abort a master dma non-blocking transfer in a early time - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - */ -void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle); - -/* @} */ -#if defined(__cplusplus) -} -#endif /*_cplusplus. */ -/*@}*/ -#endif /*_FSL_I2C_DMA_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2s.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2s.c deleted file mode 100644 index c13f2f4bcd4..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2s.c +++ /dev/null @@ -1,1198 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_i2s.h" -#include "fsl_flexcomm.h" -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s" -#endif - -/* TODO - absent in device header files, should be there */ -#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) -#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) -#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) -#define I2S_FIFOCFG_PACK48_MASK (0x8U) -#define I2S_FIFOCFG_PACK48_SHIFT (3U) -#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) -/*! @brief i2s empty tx fifo timeout value */ -#define I2S_FIFO_DEPTH (8U) -#define I2S_TX_ONE_SAMPLE_MAX_TIMEOUT (125U) /* 8K/8bit one sample need 125us*/ -#define I2S_TX_FIFO_EMPTY_TIMEOUT(count) (count) * I2S_TX_ONE_SAMPLE_MAX_TIMEOUT -/*! @brief _i2s_state I2S states. */ -enum -{ - kI2S_StateIdle = 0x0, /*!< Not performing transfer */ - kI2S_StateTx, /*!< Performing transmit */ - kI2S_StateTxWaitToWriteDummyData, /*!< Wait on FIFO in order to write final dummy data there */ - kI2S_StateTxWaitForEmptyFifo, /*!< Wait for FIFO to be flushed */ - kI2S_StateRx, /*!< Performing receive */ -}; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -static void I2S_Config(I2S_Type *base, const i2s_config_t *config); -static void I2S_TxEnable(I2S_Type *base, bool enable); -static void I2S_RxEnable(I2S_Type *base, bool enable); -static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map i2c instance number to base address. */ -static const uint32_t s_i2sBaseAddrs[] = I2S_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_i2sIRQ[] = I2S_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! - * @brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * @param base The I2S peripheral base address. - * @return I2S instance number starting from 0. - */ -static uint32_t I2S_GetInstance(I2S_Type *base) -{ - uint32_t i; - for (i = 0; i < (uint32_t)ARRAY_SIZE(s_i2sBaseAddrs); i++) - { - if ((uint32_t)base == s_i2sBaseAddrs[i]) - { - return i; - } - } - assert(false); - return 0; -} - -/*! - * brief Transmitter bit clock rate configurations. - * - * param base SAI base pointer. - * param sourceClockHz, bit clock source frequency. - * param sampleRate audio data sample rate. - * param bitWidth, audio data bitWidth. - * param channelNumbers, audio channel numbers. - */ -void I2S_SetBitClockRate( - I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers) -{ - uint32_t bitClockDivider = sourceClockHz / sampleRate / bitWidth / channelNumbers; - - assert(bitClockDivider >= 1U); - base->DIV = I2S_DIV_DIV(bitClockDivider - 1U); -} - -/*! - * brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S transmission using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_TxGetDefaultConfig(). - * - * note This API should be called at the beginning of the application to use - * the I2S driver. - * - * param base I2S base pointer. - * param config pointer to I2S configuration structure. - */ -void I2S_TxInit(I2S_Type *base, const i2s_config_t *config) -{ - uint32_t cfg = 0U; - uint32_t trig = 0U; - - (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_TX); - I2S_Config(base, config); - - /* Configure FIFO */ - - cfg |= I2S_FIFOCFG_ENABLETX(1U); /* enable TX FIFO */ - cfg |= I2S_FIFOCFG_EMPTYTX(1U); /* empty TX FIFO */ - cfg |= I2S_FIFOCFG_TXI2SE0(config->txEmptyZero); /* transmit zero when buffer becomes empty or last item */ - cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ - trig |= I2S_FIFOTRIG_TXLVLENA(1U); /* enable TX FIFO trigger */ - trig |= I2S_FIFOTRIG_TXLVL(config->watermark); /* set TX FIFO trigger level */ - - base->FIFOCFG = cfg; - base->FIFOTRIG = trig; -} - -/*! - * brief Initializes the FLEXCOMM peripheral for I2S receive functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S receive using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_RxGetDefaultConfig(). - * - * note This API should be called at the beginning of the application to use - * the I2S driver. - * - * param base I2S base pointer. - * param config pointer to I2S configuration structure. - */ -void I2S_RxInit(I2S_Type *base, const i2s_config_t *config) -{ - uint32_t cfg = 0U; - uint32_t trig = 0U; - - (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_RX); - I2S_Config(base, config); - - /* Configure FIFO */ - - cfg |= I2S_FIFOCFG_ENABLERX(1U); /* enable RX FIFO */ - cfg |= I2S_FIFOCFG_EMPTYRX(1U); /* empty RX FIFO */ - cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ - trig |= I2S_FIFOTRIG_RXLVLENA(1U); /* enable RX FIFO trigger */ - trig |= I2S_FIFOTRIG_RXLVL(config->watermark); /* set RX FIFO trigger level */ - - base->FIFOCFG = cfg; - base->FIFOTRIG = trig; -} - -/*! - * brief Flush the valid data in TX fifo. - * - * param base I2S base pointer. - * return kStatus_Fail empty TX fifo failed, kStatus_Success empty tx fifo success. - */ -status_t I2S_EmptyTxFifo(I2S_Type *base) -{ - uint32_t timeout = I2S_TX_FIFO_EMPTY_TIMEOUT(I2S_FIFO_DEPTH); - - while (((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) && (timeout != 0U)) - { - timeout -= I2S_TX_ONE_SAMPLE_MAX_TIMEOUT; - SDK_DelayAtLeastUs(I2S_TX_ONE_SAMPLE_MAX_TIMEOUT, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - } - - /* The last piece of valid data can be still being transmitted from I2S at this moment */ - timeout = I2S_TX_ONE_SAMPLE_MAX_TIMEOUT; - /* Write additional data to FIFO */ - base->FIFOWR = 0U; - while (((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) && (timeout != 0U)) - { - timeout -= I2S_TX_ONE_SAMPLE_MAX_TIMEOUT; - SDK_DelayAtLeastUs(I2S_TX_ONE_SAMPLE_MAX_TIMEOUT, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - } - - return ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) ? kStatus_Fail : kStatus_Success; -} - -/*! - * brief Sets the I2S Tx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_TxInit(). - * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified - * before calling I2S_TxInit(). - * Example: - code - i2s_config_t config; - I2S_TxGetDefaultConfig(&config); - endcode - * - * Default values: - * code - * config->masterSlave = kI2S_MasterSlaveNormalMaster; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = true; - * config->pack48 = false; - * endcode - * - * param config pointer to I2S configuration structure. - */ -void I2S_TxGetDefaultConfig(i2s_config_t *config) -{ - config->masterSlave = kI2S_MasterSlaveNormalMaster; - config->mode = kI2S_ModeI2sClassic; - config->rightLow = false; - config->leftJust = false; -#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) - config->pdmData = false; -#endif - config->sckPol = false; - config->wsPol = false; - config->divider = 1U; - config->oneChannel = false; - config->dataLength = 16U; - config->frameLength = 32U; - config->position = 0U; - config->watermark = 4U; - config->txEmptyZero = true; - config->pack48 = false; -} - -/*! - * brief Sets the I2S Rx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_RxInit(). - * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified - * before calling I2S_RxInit(). - * Example: - code - i2s_config_t config; - I2S_RxGetDefaultConfig(&config); - endcode - * - * Default values: - * code - * config->masterSlave = kI2S_MasterSlaveNormalSlave; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = false; - * config->pack48 = false; - * endcode - * - * param config pointer to I2S configuration structure. - */ -void I2S_RxGetDefaultConfig(i2s_config_t *config) -{ - config->masterSlave = kI2S_MasterSlaveNormalSlave; - config->mode = kI2S_ModeI2sClassic; - config->rightLow = false; - config->leftJust = false; -#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) - config->pdmData = false; -#endif - config->sckPol = false; - config->wsPol = false; - config->divider = 1U; - config->oneChannel = false; - config->dataLength = 16U; - config->frameLength = 32U; - config->position = 0U; - config->watermark = 4U; - config->txEmptyZero = false; - config->pack48 = false; -} - -static void I2S_Config(I2S_Type *base, const i2s_config_t *config) -{ - assert(config != NULL); - - uint32_t cfg1 = 0U; - uint32_t cfg2 = 0U; - - /* set master/slave configuration */ - cfg1 |= I2S_CFG1_MSTSLVCFG(config->masterSlave); - - /* set I2S mode */ - cfg1 |= I2S_CFG1_MODE(config->mode); - - /* set right low (channel swap) */ - cfg1 |= I2S_CFG1_RIGHTLOW(config->rightLow); - - /* set data justification */ - cfg1 |= I2S_CFG1_LEFTJUST(config->leftJust); - -#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) - if (FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn((FLEXCOMM_Type *)(uint32_t)base) > 0) - { - /* set source to PDM dmic */ - cfg1 |= I2S_CFG1_PDMDATA(config->pdmData); - } -#endif - - /* set SCLK polarity */ - cfg1 |= I2S_CFG1_SCK_POL(config->sckPol); - - /* set WS polarity */ - cfg1 |= I2S_CFG1_WS_POL(config->wsPol); - - /* set mono mode */ - cfg1 |= I2S_CFG1_ONECHANNEL(config->oneChannel); - - /* set data length */ - cfg1 |= I2S_CFG1_DATALEN(config->dataLength - 1UL); - - /* set frame length */ - cfg2 |= I2S_CFG2_FRAMELEN(config->frameLength - 1UL); - - /* set data position of this channel pair within the frame */ - cfg2 |= I2S_CFG2_POSITION(config->position); - - /* write to registers */ - base->CFG1 = cfg1; - base->CFG2 = cfg2; - - /* set the clock divider */ - base->DIV = I2S_DIV_DIV(config->divider - 1UL); -} - -/*! - * brief De-initializes the I2S peripheral. - * - * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit - * or I2S_RxInit is called to enable the clock. - * - * param base I2S base pointer. - */ -void I2S_Deinit(I2S_Type *base) -{ - /* TODO gate FLEXCOMM clock via FLEXCOMM driver */ -} - -static void I2S_TxEnable(I2S_Type *base, bool enable) -{ - if (enable) - { - I2S_Enable(base); - I2S_EnableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); - } - else - { - I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); - I2S_Disable(base); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - } -} - -static void I2S_RxEnable(I2S_Type *base, bool enable) -{ - if (enable) - { - I2S_Enable(base); - I2S_EnableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); - } - else - { - I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); - I2S_Disable(base); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - } -} - -static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer) -{ - assert(transfer->data != NULL); - - if (transfer->data == NULL) - { - return kStatus_InvalidArgument; - } - - assert(transfer->dataSize > 0U); - if (transfer->dataSize <= 0U) - { - return kStatus_InvalidArgument; - } - - if (handle->dataLength == 4U) - { - /* No alignment and data length requirements */ - } - else if ((handle->dataLength >= 5U) && (handle->dataLength <= 8U)) - { - assert((((uint32_t)transfer->data) % 2U) == 0U); - if ((((uint32_t)transfer->data) % 2U) != 0U) - { - /* Data not 2-bytes aligned */ - return kStatus_InvalidArgument; - } - - assert((transfer->dataSize % 2U) == 0U); - if ((transfer->dataSize % 2U) != 0U) - { - /* Data not in pairs of left/right channel bytes */ - return kStatus_InvalidArgument; - } - } - else if ((handle->dataLength >= 9U) && (handle->dataLength <= 16U)) - { - assert((((uint32_t)transfer->data) % 4U) == 0U); - if ((((uint32_t)transfer->data) % 4U) != 0U) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - - assert((transfer->dataSize % 4U) == 0U); - if ((transfer->dataSize % 4U) != 0U) - { - /* Data lenght not multiply of 4 */ - return kStatus_InvalidArgument; - } - } - else if ((handle->dataLength >= 17U) && (handle->dataLength <= 24U)) - { - assert((transfer->dataSize % 6U) == 0U); - if ((transfer->dataSize % 6U) != 0U) - { - /* Data lenght not multiply of 6 */ - return kStatus_InvalidArgument; - } - - assert(!((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U))); - if ((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U)) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - } - else /* if (handle->dataLength >= 25U) */ - { - assert((((uint32_t)transfer->data) % 4U) == 0U); - if ((((uint32_t)transfer->data) % 4U) != 0U) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - - if (handle->oneChannel) - { - assert((transfer->dataSize % 4U) == 0U); - if ((transfer->dataSize % 4U) != 0U) - { - /* Data lenght not multiply of 4 */ - return kStatus_InvalidArgument; - } - } - else - { - assert((transfer->dataSize % 8U) == 0U); - if ((transfer->dataSize % 8U) != 0U) - { - /* Data lenght not multiply of 8 */ - return kStatus_InvalidArgument; - } - } - } - - return kStatus_Success; -} - -#if (defined(FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) && FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) -/*! - * brief Enables I2S secondary channel. - * - * param base I2S base pointer. - * param channel seondary channel channel number, reference _i2s_secondary_channel. - * param oneChannel true is treated as single channel, functionality left channel for this pair. - * param position define the location within the frame of the data, should not bigger than 0x1FFU. - */ -void I2S_EnableSecondaryChannel(I2S_Type *base, uint32_t channel, bool oneChannel, uint32_t position) -{ - assert(channel <= (uint32_t)kI2S_SecondaryChannel3); -#if defined FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn - assert(FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn((FLEXCOMM_Type *)(uint32_t)base) == 1); -#endif - - uint32_t pcfg1 = base->SECCHANNEL[channel].PCFG1; - uint32_t pcfg2 = base->SECCHANNEL[channel].PCFG2; - - pcfg1 &= ~I2S_CFG1_ONECHANNEL_MASK; - pcfg1 |= I2S_CFG1_MAINENABLE_MASK | I2S_CFG1_ONECHANNEL(oneChannel); - - pcfg2 &= ~I2S_CFG2_POSITION_MASK; - pcfg2 |= I2S_CFG2_POSITION(position); - - base->SECCHANNEL[channel].PCFG1 = pcfg1; - base->SECCHANNEL[channel].PCFG2 = pcfg2; -} -#endif - -/*! - * brief Initializes handle for transfer of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) -{ - assert(handle != NULL); - - uint32_t instance; - - /* Clear out the handle */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2S_GetInstance(base); - - /* Save callback and user data */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Remember some items set previously by configuration */ - handle->watermark = (uint8_t)((base->FIFOTRIG & I2S_FIFOTRIG_TXLVL_MASK) >> I2S_FIFOTRIG_TXLVL_SHIFT); - handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT) != 0U ? true : false; - handle->dataLength = (uint8_t)((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; - handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT) != 0u ? true : false; - - handle->useFifo48H = false; - - /* Register IRQ handling */ - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_TxHandleIRQ, handle); - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); - (void)EnableIRQ(s_i2sIRQ[instance]); -} - -/*! - * brief Begins or queue sending of the given data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) -{ - assert(handle != NULL); - - status_t result; - - if (handle == NULL) - { - return kStatus_InvalidArgument; - } - - result = I2S_ValidateBuffer(handle, &transfer); - if (result != kStatus_Success) - { - return result; - } - - if (handle->i2sQueue[handle->queueUser].dataSize != 0UL) - { - /* Previously prepared buffers not processed yet */ - return kStatus_I2S_Busy; - } - - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_TXLVL_MASK)) | I2S_FIFOTRIG_TXLVL(handle->watermark); - I2S_TxEnable(base, true); - - return kStatus_Success; -} - -/*! - * brief Aborts sending of data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle) -{ - assert(handle != NULL); - - /* Disable I2S operation and interrupts */ - I2S_TxEnable(base, false); - - /* Reset state */ - handle->state = (uint32_t)kI2S_StateIdle; - - /* Clear transfer queue */ - (void)memset((void *)&handle->i2sQueue, 0, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); - handle->queueDriver = 0U; - handle->queueUser = 0U; -} - -/*! - * brief Initializes handle for reception of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) -{ - assert(handle != NULL); - - uint32_t instance; - - /* Clear out the handle */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2S_GetInstance(base); - - /* Save callback and user data */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Remember some items set previously by configuration */ - handle->watermark = (uint8_t)((base->FIFOTRIG & I2S_FIFOTRIG_RXLVL_MASK) >> I2S_FIFOTRIG_RXLVL_SHIFT); - handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT) != 0UL ? true : false; - handle->dataLength = (uint8_t)((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; - handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT) != 0UL ? true : false; - - handle->useFifo48H = false; - - /* Register IRQ handling */ - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_RxHandleIRQ, handle); - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); - - (void)EnableIRQ(s_i2sIRQ[instance]); -} - -/*! - * brief Begins or queue reception of data into given buffer. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. - */ -status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) -{ - assert(handle != NULL); - - status_t result; - - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - result = I2S_ValidateBuffer(handle, &transfer); - if (result != kStatus_Success) - { - return result; - } - - if (handle->i2sQueue[handle->queueUser].dataSize != 0UL) - { - /* Previously prepared buffers not processed yet */ - return kStatus_I2S_Busy; - } - - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_RXLVL_MASK)) | I2S_FIFOTRIG_RXLVL(handle->watermark); - I2S_RxEnable(base, true); - - return kStatus_Success; -} - -/*! - * brief Aborts receiving of data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle) -{ - assert(handle != NULL); - - /* Disable I2S operation and interrupts */ - I2S_RxEnable(base, false); - - /* Reset state */ - handle->state = (uint32_t)kI2S_StateIdle; - - /* Clear transfer queue */ - (void)memset((void *)&handle->i2sQueue, 0, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); - handle->queueDriver = 0U; - handle->queueUser = 0U; -} - -/*! - * brief Returns number of bytes transferred so far. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param[out] count number of bytes transferred so far by the non-blocking transaction. - * - * retval kStatus_Success - * retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - assert(count != NULL); - - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - if (handle->state == (uint32_t)kI2S_StateIdle) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->transferCount; - - return kStatus_Success; -} - -/*! - * brief Returns number of buffer underruns or overruns. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param[out] count number of transmit errors encountered so far by the non-blocking transaction. - * - * retval kStatus_Success - * retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - assert(count != NULL); - - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - if (handle->state == (uint32_t)kI2S_StateIdle) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->errorCount; - - return kStatus_Success; -} - -/*! - * brief Invoked from interrupt handler when transmit FIFO level decreases. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) -{ - uint32_t intstat = base->FIFOINTSTAT; - uint32_t data; - uint8_t queueDriverIndex = handle->queueDriver; - uint32_t dataAddr = (uint32_t)handle->i2sQueue[queueDriverIndex].data; - uint32_t dataSize = handle->i2sQueue[queueDriverIndex].dataSize; - - if ((intstat & I2S_FIFOINTSTAT_TXERR_MASK) != 0UL) - { - handle->errorCount++; - - /* Clear TX error interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_TXERR(1U); - } - - if ((intstat & I2S_FIFOINTSTAT_TXLVL_MASK) != 0UL) - { - if ((handle->state != (uint32_t)kI2S_StateTx) && (dataSize != 0U) && (dataAddr != 0U)) - { - handle->state = (uint32_t)kI2S_StateTx; - } - - if (handle->state == (uint32_t)kI2S_StateTx) - { - /* Send data */ - - while (((base->FIFOSTAT & I2S_FIFOSTAT_TXNOTFULL_MASK) != 0UL) && (dataSize > 0U)) - { - /* Write output data */ - if (handle->dataLength == 4U) - { - data = *((uint8_t *)dataAddr); - base->FIFOWR = ((data & 0xF0U) << 12U) | (data & 0xFU); - dataAddr++; - handle->transferCount++; - dataSize--; - } - else if (handle->dataLength <= 8U) - { - data = *((volatile uint16_t *)dataAddr); - if (handle->oneChannel) - { - base->FIFOWR = (data & 0xFFU); - dataAddr += sizeof(uint8_t); - handle->transferCount += sizeof(uint8_t); - dataSize -= sizeof(uint8_t); - } - else - { - base->FIFOWR = ((data & 0xFF00U) << 8U) | (data & 0xFFU); - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - } - else if (handle->dataLength <= 16U) - { - data = *((volatile uint32_t *)(dataAddr)); - if (handle->oneChannel) - { - base->FIFOWR = data & 0xFFFFU; - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - else - { - base->FIFOWR = data; - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - } - else if (handle->dataLength <= 24U) - { - if (handle->pack48) - { - if (handle->useFifo48H) - { - base->FIFOWR48H = *((volatile uint16_t *)(dataAddr)); - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - handle->useFifo48H = false; - } - else - { - base->FIFOWR = *((volatile uint32_t *)(dataAddr)); - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - handle->useFifo48H = true; - } - } - else - { - data = (uint32_t)(*(uint8_t *)(dataAddr++)); - data |= ((uint32_t)(*(uint8_t *)(dataAddr++))) << 8U; - data |= ((uint32_t)(*(uint8_t *)(dataAddr++))) << 16U; - if ((handle->useFifo48H) && (handle->oneChannel == false)) - { - base->FIFOWR48H = data; - handle->useFifo48H = false; - } - else - { - base->FIFOWR = data; - handle->useFifo48H = true; - } - handle->transferCount += 3U; - dataSize -= 3U; - } - } - else /* if (handle->dataLength <= 32U) */ - { - base->FIFOWR = *((volatile uint32_t *)(dataAddr)); - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - - if (dataSize == 0U) - { - handle->i2sQueue[queueDriverIndex].dataSize = 0U; - /* Actual data buffer sent out, switch to a next one */ - handle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; - - /* Notify user */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); - } - - /* Check if the next buffer contains anything to send */ - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* Everything has been written to FIFO */ - handle->state = kI2S_StateTxWaitToWriteDummyData; - break; - } - } - else - { - handle->i2sQueue[queueDriverIndex].dataSize = dataSize; - handle->i2sQueue[queueDriverIndex].data = (uint8_t *)dataAddr; - } - } - } - else if (handle->state == (uint32_t)kI2S_StateTxWaitToWriteDummyData) - { - /* Write dummy data */ - if ((handle->dataLength > 16U) && (handle->dataLength < 25U)) - { - if (handle->useFifo48H) - { - base->FIFOWR48H = 0U; - handle->useFifo48H = false; - } - else - { - base->FIFOWR = 0U; - base->FIFOWR48H = 0U; - } - } - else - { - base->FIFOWR = 0U; - } - - /* Next time invoke this handler when FIFO becomes empty (TX level 0) */ - base->FIFOTRIG &= ~I2S_FIFOTRIG_TXLVL_MASK; - handle->state = (uint32_t)kI2S_StateTxWaitForEmptyFifo; - } - else if (handle->state == (uint32_t)kI2S_StateTxWaitForEmptyFifo) - { - /* FIFO, including additional dummy data, has been emptied now, - * all relevant data should have been output from peripheral */ - - /* Stop transfer */ - I2S_Disable(base); - I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - - /* Reset state */ - handle->state = (uint32_t)kI2S_StateIdle; - - /* Notify user */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); - } - } - else - { - /* Do nothing */ - } - - /* Clear TX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_TXLVL(1U); - } -} - -/*! - * brief Invoked from interrupt handler when receive FIFO level decreases. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) -{ - uint32_t intstat = base->FIFOINTSTAT; - uint32_t data; - uint8_t queueDriverIndex = handle->queueDriver; - uint32_t dataAddr = (uint32_t)handle->i2sQueue[queueDriverIndex].data; - uint32_t dataSize = handle->i2sQueue[queueDriverIndex].dataSize; - - if ((intstat & I2S_FIFOINTSTAT_RXERR_MASK) != 0UL) - { - handle->errorCount++; - - /* Clear RX error interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXERR(1U); - } - - if ((intstat & I2S_FIFOINTSTAT_RXLVL_MASK) != 0UL) - { - while (((base->FIFOSTAT & I2S_FIFOSTAT_RXNOTEMPTY_MASK) != 0UL) && (dataSize > 0U)) - { - /* Read input data */ - if (handle->dataLength == 4U) - { - data = base->FIFORD; - *((uint8_t *)dataAddr) = (uint8_t)(((data & 0x000F0000U) >> 12U) | (data & 0x0000000FU)); - dataAddr++; - handle->transferCount++; - dataSize--; - } - else if (handle->dataLength <= 8U) - { - data = base->FIFORD; - - if (handle->oneChannel) - { - *((volatile uint8_t *)dataAddr) = (uint8_t)(data & 0xFFU); - dataAddr += sizeof(uint8_t); - handle->transferCount += sizeof(uint8_t); - dataSize -= sizeof(uint8_t); - } - else - { - *((volatile uint16_t *)dataAddr) = (uint16_t)(((data >> 8U) & 0xFF00U) | (data & 0xFFU)); - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - } - else if (handle->dataLength <= 16U) - { - data = base->FIFORD; - - if (handle->oneChannel) - { - *((volatile uint16_t *)dataAddr) = (uint16_t)(data & 0xFFFFU); - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - else - { - *((volatile uint32_t *)dataAddr) = data; - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - } - else if (handle->dataLength <= 24U) - { - if (handle->pack48) - { - if (handle->useFifo48H) - { - data = base->FIFORD48H; - handle->useFifo48H = false; - - *((volatile uint16_t *)dataAddr) = (uint16_t)data; - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - else - { - data = base->FIFORD; - handle->useFifo48H = true; - - *((volatile uint32_t *)dataAddr) = data; - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - } - else - { - if (handle->useFifo48H) - { - data = base->FIFORD48H; - handle->useFifo48H = false; - } - else - { - data = base->FIFORD; - handle->useFifo48H = true; - } - - *(uint8_t *)(dataAddr++) = (uint8_t)(data & 0xFFU); - *(uint8_t *)(dataAddr++) = (uint8_t)((data >> 8U) & 0xFFU); - *(uint8_t *)(dataAddr++) = (uint8_t)((data >> 16U) & 0xFFU); - handle->transferCount += 3U; - dataSize -= 3U; - } - } - else /* if (handle->dataLength <= 32U) */ - { - data = base->FIFORD; - *((volatile uint32_t *)dataAddr) = data; - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - - if (dataSize == 0U) - { - handle->i2sQueue[queueDriverIndex].dataSize = 0U; - /* Actual data buffer filled with input data, switch to a next one */ - handle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; - - /* Notify user */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); - } - - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* No other buffer prepared to receive data into */ - - /* Disable I2S operation and interrupts */ - I2S_Disable(base); - I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - - /* Reset state */ - handle->state = (uint32_t)kI2S_StateIdle; - - /* Notify user */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); - } - - /* Clear RX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); - - return; - } - } - else - { - handle->i2sQueue[queueDriverIndex].dataSize = dataSize; - handle->i2sQueue[queueDriverIndex].data = (uint8_t *)dataAddr; - } - } - - /* Clear RX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2s.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2s.h deleted file mode 100644 index e0787d6b145..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2s.h +++ /dev/null @@ -1,513 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2S_H_ -#define _FSL_I2S_H_ - -#include "fsl_device_registers.h" -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup i2s_driver - * @{ - */ - -/*! @file */ - -/*! @name Driver version */ -/*@{*/ - -/*! @brief I2S driver version 2.3.1. */ -#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) -/*@}*/ - -#ifndef I2S_NUM_BUFFERS - -/*! @brief Number of buffers . */ -#define I2S_NUM_BUFFERS (4U) - -#endif - -/*! @brief _i2s_status I2S status codes. */ -enum -{ - kStatus_I2S_BufferComplete = - MAKE_STATUS(kStatusGroup_I2S, 0), /*!< Transfer from/into a single buffer has completed */ - kStatus_I2S_Done = MAKE_STATUS(kStatusGroup_I2S, 1), /*!< All buffers transfers have completed */ - kStatus_I2S_Busy = - MAKE_STATUS(kStatusGroup_I2S, 2), /*!< Already performing a transfer and cannot queue another buffer */ -}; - -/*! - * @brief I2S flags. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -typedef enum _i2s_flags -{ - kI2S_TxErrorFlag = I2S_FIFOINTENSET_TXERR_MASK, /*!< TX error interrupt */ - kI2S_TxLevelFlag = I2S_FIFOINTENSET_TXLVL_MASK, /*!< TX level interrupt */ - kI2S_RxErrorFlag = I2S_FIFOINTENSET_RXERR_MASK, /*!< RX error interrupt */ - kI2S_RxLevelFlag = I2S_FIFOINTENSET_RXLVL_MASK /*!< RX level interrupt */ -} i2s_flags_t; - -/*! @brief Master / slave mode. */ -typedef enum _i2s_master_slave -{ - kI2S_MasterSlaveNormalSlave = 0x0, /*!< Normal slave */ - kI2S_MasterSlaveWsSyncMaster = 0x1, /*!< WS synchronized master */ - kI2S_MasterSlaveExtSckMaster = 0x2, /*!< Master using existing SCK */ - kI2S_MasterSlaveNormalMaster = 0x3 /*!< Normal master */ -} i2s_master_slave_t; - -/*! @brief I2S mode. */ -typedef enum _i2s_mode -{ - kI2S_ModeI2sClassic = 0x0, /*!< I2S classic mode */ - kI2S_ModeDspWs50 = 0x1, /*!< DSP mode, WS having 50% duty cycle */ - kI2S_ModeDspWsShort = 0x2, /*!< DSP mode, WS having one clock long pulse */ - kI2S_ModeDspWsLong = 0x3 /*!< DSP mode, WS having one data slot long pulse */ -} i2s_mode_t; - -/*! @brief _i2s_secondary_channel I2S secondary channel. */ -enum -{ - kI2S_SecondaryChannel1 = 0U, /*!< secondary channel 1 */ - kI2S_SecondaryChannel2 = 1U, /*!< secondary channel 2 */ - kI2S_SecondaryChannel3 = 2U, /*!< secondary channel 3 */ -}; - -/*! @brief I2S configuration structure. */ -typedef struct _i2s_config -{ - i2s_master_slave_t masterSlave; /*!< Master / slave configuration */ - i2s_mode_t mode; /*!< I2S mode */ - bool rightLow; /*!< Right channel data in low portion of FIFO */ - bool leftJust; /*!< Left justify data in FIFO */ -#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) - bool pdmData; /*!< Data source is the D-Mic subsystem */ -#endif - bool sckPol; /*!< SCK polarity */ - bool wsPol; /*!< WS polarity */ - uint16_t divider; /*!< Flexcomm function clock divider (1 - 4096) */ - bool oneChannel; /*!< true mono, false stereo */ - uint8_t dataLength; /*!< Data length (4 - 32) */ - uint16_t frameLength; /*!< Frame width (4 - 512) */ - uint16_t position; /*!< Data position in the frame */ - uint8_t watermark; /*!< FIFO trigger level */ - bool txEmptyZero; /*!< Transmit zero when buffer becomes empty or last item */ - bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit - values) */ -} i2s_config_t; - -/*! @brief Buffer to transfer from or receive audio data into. */ -typedef struct _i2s_transfer -{ - uint8_t *data; /*!< Pointer to data buffer. */ - size_t dataSize; /*!< Buffer size in bytes. */ -} i2s_transfer_t; - -/*! @brief Transactional state of the intialized transfer or receive I2S operation. */ -typedef struct _i2s_handle i2s_handle_t; - -/*! - * @brief Callback function invoked from transactional API - * on completion of a single buffer transfer. - * - * @param base I2S base pointer. - * @param handle pointer to I2S transaction. - * @param completionStatus status of the transaction. - * @param userData optional pointer to user arguments data. - */ -typedef void (*i2s_transfer_callback_t)(I2S_Type *base, - i2s_handle_t *handle, - status_t completionStatus, - void *userData); - -/*! @brief Members not to be accessed / modified outside of the driver. */ -struct _i2s_handle -{ - volatile uint32_t state; /*!< State of transfer */ - i2s_transfer_callback_t completionCallback; /*!< Callback function pointer */ - void *userData; /*!< Application data passed to callback */ - bool oneChannel; /*!< true mono, false stereo */ - uint8_t dataLength; /*!< Data length (4 - 32) */ - bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit - values) */ - uint8_t watermark; /*!< FIFO trigger level */ - bool useFifo48H; /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */ - - volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ - volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ - volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ - volatile uint32_t errorCount; /*!< Number of buffer underruns/overruns */ - volatile uint32_t transferCount; /*!< Number of bytes transferred */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S transmission using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_TxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the I2S driver. - * - * @param base I2S base pointer. - * @param config pointer to I2S configuration structure. - */ -void I2S_TxInit(I2S_Type *base, const i2s_config_t *config); - -/*! - * @brief Initializes the FLEXCOMM peripheral for I2S receive functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S receive using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_RxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the I2S driver. - * - * @param base I2S base pointer. - * @param config pointer to I2S configuration structure. - */ -void I2S_RxInit(I2S_Type *base, const i2s_config_t *config); - -/*! - * @brief Sets the I2S Tx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_TxInit(). - * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified - * before calling I2S_TxInit(). - * Example: - @code - i2s_config_t config; - I2S_TxGetDefaultConfig(&config); - @endcode - * - * Default values: - * @code - * config->masterSlave = kI2S_MasterSlaveNormalMaster; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = true; - * config->pack48 = false; - * @endcode - * - * @param config pointer to I2S configuration structure. - */ -void I2S_TxGetDefaultConfig(i2s_config_t *config); - -/*! - * @brief Sets the I2S Rx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_RxInit(). - * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified - * before calling I2S_RxInit(). - * Example: - @code - i2s_config_t config; - I2S_RxGetDefaultConfig(&config); - @endcode - * - * Default values: - * @code - * config->masterSlave = kI2S_MasterSlaveNormalSlave; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = false; - * config->pack48 = false; - * @endcode - * - * @param config pointer to I2S configuration structure. - */ -void I2S_RxGetDefaultConfig(i2s_config_t *config); - -/*! - * @brief De-initializes the I2S peripheral. - * - * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit - * or I2S_RxInit is called to enable the clock. - * - * @param base I2S base pointer. - */ -void I2S_Deinit(I2S_Type *base); - -/*! - * @brief Transmitter/Receiver bit clock rate configurations. - * - * @param base SAI base pointer. - * @param sourceClockHz bit clock source frequency. - * @param sampleRate audio data sample rate. - * @param bitWidth audio data bitWidth. - * @param channelNumbers audio channel numbers. - */ -void I2S_SetBitClockRate( - I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers); - -/*! @} */ - -/*! - * @name Non-blocking API - * @{ - */ - -/*! - * @brief Initializes handle for transfer of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); - -/*! - * @brief Begins or queue sending of the given data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts sending of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Initializes handle for reception of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); - -/*! - * @brief Begins or queue reception of data into given buffer. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. - */ -status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts receiving of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Returns number of bytes transferred so far. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param[out] count number of bytes transferred so far by the non-blocking transaction. - * - * @retval kStatus_Success - * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); - -/*! - * @brief Returns number of buffer underruns or overruns. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param[out] count number of transmit errors encountered so far by the non-blocking transaction. - * - * @retval kStatus_Success - * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); - -/*! @} */ - -/*! - * @name Enable / disable - * @{ - */ - -/*! - * @brief Enables I2S operation. - * - * @param base I2S base pointer. - */ -static inline void I2S_Enable(I2S_Type *base) -{ - base->CFG1 |= I2S_CFG1_MAINENABLE(1U); -} - -#if (defined(FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) && FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) -/*! - * @brief Enables I2S secondary channel. - * - * @param base I2S base pointer. - * @param channel seondary channel channel number, reference _i2s_secondary_channel. - * @param oneChannel true is treated as single channel, functionality left channel for this pair. - * @param position define the location within the frame of the data, should not bigger than 0x1FFU. - */ -void I2S_EnableSecondaryChannel(I2S_Type *base, uint32_t channel, bool oneChannel, uint32_t position); - -/*! - * @brief Disables I2S secondary channel. - * - * @param base I2S base pointer. - * @param channel seondary channel channel number, reference _i2s_secondary_channel. - */ -static inline void I2S_DisableSecondaryChannel(I2S_Type *base, uint32_t channel) -{ -#if defined FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn - assert(FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn((FLEXCOMM_Type *)(uint32_t)base) == 1); -#endif - - base->SECCHANNEL[channel].PCFG1 &= ~I2S_CFG1_MAINENABLE_MASK; -} -#endif -/*! - * @brief Disables I2S operation. - * - * @param base I2S base pointer. - */ -static inline void I2S_Disable(I2S_Type *base) -{ - base->CFG1 &= (~I2S_CFG1_MAINENABLE(1U)); -} - -/*! @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables I2S FIFO interrupts. - * - * @param base I2S base pointer. - * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2S_EnableInterrupts(I2S_Type *base, uint32_t interruptMask) -{ - base->FIFOINTENSET = interruptMask; -} - -/*! - * @brief Disables I2S FIFO interrupts. - * - * @param base I2S base pointer. - * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2S_DisableInterrupts(I2S_Type *base, uint32_t interruptMask) -{ - base->FIFOINTENCLR = interruptMask; -} - -/*! - * @brief Returns the set of currently enabled I2S FIFO interrupts. - * - * @param base I2S base pointer. - * - * @return A bitmask composed of #i2s_flags_t enumerators OR'd together - * to indicate the set of enabled interrupts. - */ -static inline uint32_t I2S_GetEnabledInterrupts(I2S_Type *base) -{ - return base->FIFOINTENSET; -} - -/*! - * @brief Flush the valid data in TX fifo. - * - * @param base I2S base pointer. - * @return kStatus_Fail empty TX fifo failed, kStatus_Success empty tx fifo success. - */ -status_t I2S_EmptyTxFifo(I2S_Type *base); - -/*! - * @brief Invoked from interrupt handler when transmit FIFO level decreases. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Invoked from interrupt handler when receive FIFO level decreases. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); - -/*! @} */ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2S_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2s_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2s_dma.c deleted file mode 100644 index 84f25b30e91..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2s_dma.c +++ /dev/null @@ -1,848 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_dma.h" -#include "fsl_i2s_dma.h" -#include "fsl_flexcomm.h" -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s_dma" -#endif - -#define DMA_MAX_TRANSFER_BYTES (DMA_MAX_TRANSFER_COUNT * sizeof(uint32_t)) -#define DMA_DESCRIPTORS (2U) - -/*i2sQueue[handle->queueUser].dataSize != 0UL) - { - /* Previously prepared buffers not processed yet, reject request */ - return kStatus_I2S_Busy; - } - - /* Enqueue data */ - privateHandle->descriptorQueue[handle->queueUser].data = transfer.data; - privateHandle->descriptorQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - return kStatus_Success; -} - -static uint32_t I2S_GetInstance(I2S_Type *base) -{ - uint32_t i; - - for (i = 0U; i < ARRAY_SIZE(s_I2sBaseAddrs); i++) - { - if ((uint32_t)base == s_I2sBaseAddrs[i]) - { - return i; - } - } - - assert(false); - return 0U; -} - -static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle) -{ - DMA_DisableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); -} - -static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle) -{ - if (handle->state != (uint32_t)kI2S_DmaStateIdle) - { - DMA_EnableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); - } -} - -/*! - * brief Initializes handle for transfer of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param dmaHandle pointer to dma handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData) -{ - assert(handle != NULL); - assert(dmaHandle != NULL); - - uint32_t instance = I2S_GetInstance(base); - i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - - (void)memset(handle, 0, sizeof(*handle)); - handle->state = (uint32_t)kI2S_DmaStateIdle; - handle->dmaHandle = dmaHandle; - handle->completionCallback = callback; - handle->userData = userData; - - handle->bytesPerFrame = (uint8_t)((((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U) / 8U); - /* if one channel is disabled, bytesPerFrame should be 4U, user should pay attention that when data length is - * shorter than 16, the data format: left data put in 0-15 bit and right data should put in 16-31 - */ - if (((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) == 0U)) - { - handle->bytesPerFrame = 4U; - } - /* since DMA do not support 24bit transfer width, use 32bit instead */ - if (handle->bytesPerFrame == 3U) - { - handle->bytesPerFrame = 4U; - } - - (void)memset(privateHandle, 0, sizeof(*privateHandle)); - privateHandle->base = base; - privateHandle->handle = handle; - - DMA_SetCallback(dmaHandle, I2S_DMACallback, privateHandle); -} - -/*! - * brief Begins or queue sending of the given data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) -{ - status_t status; - - I2S_DisableDMAInterrupts(handle); - - /* Enqueue transfer buffer */ - status = I2S_EnqueueUserBuffer(base, handle, transfer); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - - /* Initialize DMA transfer */ - if (handle->state == (uint32_t)kI2S_DmaStateIdle) - { - handle->state = (uint32_t)kI2S_DmaStateTx; - status = I2S_StartTransferDMA(base, handle); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - } - - I2S_AddTransferDMA(base, handle); - I2S_EnableDMAInterrupts(handle); - - return kStatus_Success; -} - -/*! - * brief Aborts transfer of data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - assert(handle != NULL); - assert(handle->dmaHandle != NULL); - - uint32_t instance = I2S_GetInstance(base); - i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - - I2S_DisableDMAInterrupts(handle); - - /* Abort operation */ - DMA_AbortTransfer(handle->dmaHandle); - - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - /* Disable TX */ - I2S_TxEnableDMA(base, false); - } - else - { - /* Disable RX */ - I2S_RxEnableDMA(base, false); - } - - I2S_Disable(base); - - /* Reset state */ - handle->state = (uint32_t)kI2S_DmaStateIdle; - - /* Clear transfer queue */ - (void)memset((void *)&(handle->i2sQueue), 0, sizeof(handle->i2sQueue)); - handle->queueDriver = 0U; - handle->queueUser = 0U; - - /* Clear internal state */ - (void)memset((void *)&(privateHandle->descriptorQueue), 0, sizeof(privateHandle->descriptorQueue)); - (void)memset((void *)&(privateHandle->enqueuedBytes), 0, sizeof(privateHandle->enqueuedBytes)); - privateHandle->enqueuedBytesStart = 0U; - privateHandle->enqueuedBytesEnd = 0U; - privateHandle->dmaDescriptorsUsed = 0U; - privateHandle->descriptor = 0U; - privateHandle->queueDescriptor = 0U; - privateHandle->intA = false; -} - -/*! - * brief Initializes handle for reception of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param dmaHandle pointer to dma handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData) -{ - I2S_TxTransferCreateHandleDMA(base, handle, dmaHandle, callback, userData); -} - -/*! - * brief Begins or queue reception of data into given buffer. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with buffers - * which are not full. - */ -status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) -{ - status_t status; - - I2S_DisableDMAInterrupts(handle); - - /* Enqueue transfer buffer */ - status = I2S_EnqueueUserBuffer(base, handle, transfer); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - - /* Initialize DMA transfer */ - if (handle->state == (uint32_t)kI2S_DmaStateIdle) - { - handle->state = (uint32_t)kI2S_DmaStateRx; - status = I2S_StartTransferDMA(base, handle); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - } - - I2S_AddTransferDMA(base, handle); - I2S_EnableDMAInterrupts(handle); - - return kStatus_Success; -} - -static void I2S_TxEnableDMA(I2S_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= I2S_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= (~I2S_FIFOCFG_DMATX_MASK); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - } -} - -static void I2S_RxEnableDMA(I2S_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= I2S_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= (~I2S_FIFOCFG_DMARX_MASK); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - } -} - -static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer) -{ - assert(transfer != NULL); - - uint16_t transferBytes; - - if (transfer->dataSize >= (2UL * DMA_MAX_TRANSFER_BYTES)) - { - transferBytes = DMA_MAX_TRANSFER_BYTES; - } - else if (transfer->dataSize > DMA_MAX_TRANSFER_BYTES) - { - transferBytes = (uint16_t)(transfer->dataSize / 2U); - if ((transferBytes % 4U) != 0U) - { - transferBytes -= (transferBytes % 4U); - } - } - else - { - transferBytes = (uint16_t)transfer->dataSize; - } - - return transferBytes; -} - -/*! - * brief Install DMA descriptor memory for loop transfer only. - * - * This function used to register DMA descriptor memory for the i2s loop dma transfer. - * - * It must be callbed before I2S_TransferSendLoopDMA/I2S_TransferReceiveLoopDMA and after - * I2S_RxTransferCreateHandleDMA/I2S_TxTransferCreateHandleDMA. - * - * User should be take care about the address of DMA descriptor pool which required align with 16BYTE at least. - * - * param handle Pointer to i2s DMA transfer handle. - * param dmaDescriptorAddr DMA descriptor start address. - * param dmaDescriptorNum DMA descriptor number. - */ -void I2S_TransferInstallLoopDMADescriptorMemory(i2s_dma_handle_t *handle, - void *dmaDescriptorAddr, - size_t dmaDescriptorNum) -{ - assert(handle != NULL); - assert((((uint32_t)(uint32_t *)dmaDescriptorAddr) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == - 0UL); - - handle->i2sLoopDMADescriptor = (dma_descriptor_t *)dmaDescriptorAddr; - handle->i2sLoopDMADescriptorNum = dmaDescriptorNum; -} - -static status_t I2S_TransferLoopDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - i2s_transfer_t *xfer, - uint32_t loopTransferCount) -{ - assert(handle != NULL); - assert(handle->dmaHandle != NULL); - assert(xfer != NULL); - - uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; - i2s_transfer_t *currentTransfer = xfer; - bool intA = true; - - if (handle->i2sLoopDMADescriptor == NULL) - { - return kStatus_InvalidArgument; - } - - if (handle->state == (uint32_t)kI2S_DmaStateBusyLoopTransfer) - { - return kStatus_I2S_Busy; - } - - for (uint32_t i = 0U; i < loopTransferCount; i++) - { - currentTransfer = &xfer[i]; - - if ((currentTransfer->data == NULL) || (currentTransfer->dataSize == 0U) || - (i >= handle->i2sLoopDMADescriptorNum) || - (currentTransfer->dataSize / handle->bytesPerFrame > DMA_MAX_TRANSFER_COUNT)) - { - return kStatus_InvalidArgument; - } - - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - srcAddr = (uint32_t *)(uint32_t)currentTransfer->data; - destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); - srcInc = 1U; - destInc = 0UL; - } - else - { - srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); - destAddr = (uint32_t *)(uint32_t)currentTransfer->data; - srcInc = 0U; - destInc = 1UL; - } - - intA = intA == true ? false : true; - - if (i == (loopTransferCount - 1U)) - { - /* set up linked descriptor */ - DMA_SetupDescriptor(&handle->i2sLoopDMADescriptor[i], - DMA_CHANNEL_XFER(1UL, 0UL, intA, !intA, handle->bytesPerFrame, srcInc, destInc, - currentTransfer->dataSize), - srcAddr, destAddr, &handle->i2sLoopDMADescriptor[0U]); - } - else - { - /* set up linked descriptor */ - DMA_SetupDescriptor(&handle->i2sLoopDMADescriptor[i], - DMA_CHANNEL_XFER(1UL, 0UL, intA, !intA, handle->bytesPerFrame, srcInc, destInc, - currentTransfer->dataSize), - srcAddr, destAddr, &handle->i2sLoopDMADescriptor[i + 1U]); - } - } - - /* transferSize make sense to non link transfer only */ - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - srcAddr = (uint32_t *)(uint32_t)xfer->data; - destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); - srcInc = 1U; - destInc = 0UL; - } - else - { - srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); - destAddr = (uint32_t *)(uint32_t)xfer->data; - srcInc = 0U; - destInc = 1UL; - } - - DMA_SubmitChannelTransferParameter( - handle->dmaHandle, - DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 1UL, handle->bytesPerFrame, srcInc, destInc, (uint32_t)xfer->dataSize), srcAddr, - destAddr, (void *)&handle->i2sLoopDMADescriptor[1U]); - - /* Submit and start initial DMA transfer */ - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - I2S_TxEnableDMA(base, true); - } - else - { - I2S_RxEnableDMA(base, true); - } - DMA_EnableChannelPeriphRq(handle->dmaHandle->base, handle->dmaHandle->channel); - /* start transfer */ - DMA_StartTransfer(handle->dmaHandle); - I2S_Enable(base); - - handle->state = (uint32_t)kI2S_DmaStateBusyLoopTransfer; - - return kStatus_Success; -} - -/*! - * brief Send loop transfer data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * This function support loop transfer, such as A->B->...->A, the loop transfer chain - * will be converted into a chain of descriptor and submit to dma. - * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, - * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. - * - * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support - * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop - * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. - * - * param base I2S peripheral base address. - * param handle Pointer to usart_dma_handle_t structure. - * param xfer I2S DMA transfer structure. See #i2s_transfer_t. - * param i2s_channel I2S start channel number - * retval kStatus_Success - */ -status_t I2S_TransferSendLoopDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - i2s_transfer_t *xfer, - uint32_t loopTransferCount) -{ - assert(handle != NULL); - assert(handle->i2sLoopDMADescriptor != NULL); - - handle->state = (uint32_t)kI2S_DmaStateTx; - - return I2S_TransferLoopDMA(base, handle, xfer, loopTransferCount); -} - -/*! - * brief Receive loop transfer data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * This function support loop transfer, such as A->B->...->A, the loop transfer chain - * will be converted into a chain of descriptor and submit to dma. - * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, - * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. - * - * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support - * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop - * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. - * - * param base I2S peripheral base address. - * param handle Pointer to usart_dma_handle_t structure. - * param xfer I2S DMA transfer structure. See #i2s_transfer_t. - * param i2s_channel I2S start channel number - * retval kStatus_Success - */ -status_t I2S_TransferReceiveLoopDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - i2s_transfer_t *xfer, - uint32_t loopTransferCount) -{ - assert(handle != NULL); - assert(handle->i2sLoopDMADescriptor != NULL); - - handle->state = (uint32_t)kI2S_DmaStateRx; - - return I2S_TransferLoopDMA(base, handle, xfer, loopTransferCount); -} - -static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - uint32_t instance = I2S_GetInstance(base); - i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - volatile i2s_transfer_t *transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); - uint16_t transferBytes = I2S_GetTransferBytes(transfer); - uint32_t i = 0U; - uint32_t xferConfig = 0U; - uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; - - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - srcAddr = (uint32_t *)(uint32_t)transfer->data; - destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); - srcInc = 1U; - destInc = 0UL; - } - else - { - srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); - destAddr = (uint32_t *)(uint32_t)transfer->data; - srcInc = 0U; - destInc = 1UL; - } - /* Initial descriptor is stored in another place in memory, but treat it as another descriptor for simplicity */ - privateHandle->dmaDescriptorsUsed = 1U; - privateHandle->intA = false; - - /* submit transfer parameter directly */ - xferConfig = DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 1UL, handle->bytesPerFrame, srcInc, destInc, (uint32_t)transferBytes); - - DMA_SubmitChannelTransferParameter(handle->dmaHandle, xferConfig, srcAddr, destAddr, - (void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U])); - - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; - privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; - - transfer->dataSize -= transferBytes; - transfer->data = (uint8_t *)((uint32_t)transfer->data + transferBytes); - - if (transfer->dataSize == 0U) - { - transfer->data = NULL; - privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; - } - - /* Link the DMA descriptors for the case when no additional transfer is queued before the initial one finishes - * The configuration for the DMA dummy descriptor make no sense to tx or rx transfer, since it will be overwritten - * when another transfer request comes before the previous finished. - * To make sure the audio data transfer continuously, application must request another transfer by call - * I2S_RxTransferReceiveDMA or I2S_TxTransferSendDMA before previous transfer finished. - */ - for (i = 0; i < DMA_DESCRIPTORS; i++) - { - /* DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 0UL, sizeof(uint32_t), 0U, 0U, 8U) = 0x10203UL */ - DMA_SetupDescriptor( - &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + i]), 0x10203UL, - ((handle->state == (uint32_t)kI2S_DmaStateTx) ? &s_DummyBufferTx : (uint32_t *)(uint32_t)(&(base->FIFORD))), - ((handle->state == (uint32_t)kI2S_DmaStateTx) ? (uint32_t *)(uint32_t)(&(base->FIFOWR)) : &s_DummyBufferRx), - &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + ((i + 1U) % DMA_DESCRIPTORS)])); - } - - /* Submit and start initial DMA transfer */ - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - I2S_TxEnableDMA(base, true); - } - else - { - I2S_RxEnableDMA(base, true); - } - /* enable I2S peripheral request and put the channel into triggered status */ - DMA_EnableChannelPeriphRq(handle->dmaHandle->base, handle->dmaHandle->channel); - DMA_StartTransfer(handle->dmaHandle); - - I2S_Enable(base); - - return kStatus_Success; -} - -static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - volatile i2s_transfer_t *transfer; - uint16_t transferBytes; - uint32_t instance; - i2s_dma_private_handle_t *privateHandle; - dma_descriptor_t *descriptor; - dma_descriptor_t *nextDescriptor; - uint32_t xferConfig = 0U; - bool intA = false; - uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; - - instance = I2S_GetInstance(base); - privateHandle = &(s_DmaPrivateHandle[instance]); - - while (privateHandle->dmaDescriptorsUsed < DMA_DESCRIPTORS) - { - transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); - intA = privateHandle->intA; - if (transfer->dataSize == 0U) - { - /* Nothing to be added */ - return; - } - - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - srcAddr = (uint32_t *)(uint32_t)transfer->data; - destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); - srcInc = 1U; - destInc = 0UL; - } - else - { - srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); - destAddr = (uint32_t *)(uint32_t)transfer->data; - srcInc = 0U; - destInc = 1UL; - } - - /* Determine currently configured descriptor and the other which it will link to */ - descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); - privateHandle->descriptor = (privateHandle->descriptor + 1U) % DMA_DESCRIPTORS; - nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); - - transferBytes = I2S_GetTransferBytes(transfer); - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; - privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; - - xferConfig = - DMA_CHANNEL_XFER(1UL, 0UL, !intA, intA, handle->bytesPerFrame, srcInc, destInc, (uint32_t)transferBytes); - - DMA_SetupDescriptor(descriptor, xferConfig, srcAddr, destAddr, nextDescriptor); - - /* Advance internal state */ - privateHandle->dmaDescriptorsUsed++; - privateHandle->intA = !privateHandle->intA; - - transfer->dataSize -= transferBytes; - transfer->data += transferBytes; - if (transfer->dataSize == 0U) - { - transfer->data = NULL; - privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; - } - } -} - -/*! - * brief Invoked from DMA interrupt handler. - * - * param handle pointer to DMA handle structure. - * param userData argument for user callback. - * param transferDone if transfer was done. - * param tcds - */ -void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds) -{ - i2s_dma_private_handle_t *privateHandle = (i2s_dma_private_handle_t *)userData; - i2s_dma_handle_t *i2sHandle = privateHandle->handle; - I2S_Type *base = privateHandle->base; - uint8_t queueDriverIndex = i2sHandle->queueDriver; - uint32_t enqueueBytes = privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart]; - uint32_t queueDataAddr = (uint32_t)i2sHandle->i2sQueue[queueDriverIndex].data; - - if ((!transferDone) || (i2sHandle->state == (uint32_t)kI2S_DmaStateIdle)) - { - return; - } - - if (privateHandle->dmaDescriptorsUsed > 0U) - { - /* Finished descriptor, decrease amount of data to be processed */ - - i2sHandle->i2sQueue[queueDriverIndex].dataSize -= enqueueBytes; - i2sHandle->i2sQueue[queueDriverIndex].data = (uint8_t *)(queueDataAddr + enqueueBytes); - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] = 0U; - privateHandle->enqueuedBytesStart = (privateHandle->enqueuedBytesStart + 1U) % DMA_DESCRIPTORS; - privateHandle->dmaDescriptorsUsed--; - } - - if (i2sHandle->i2sQueue[queueDriverIndex].dataSize == 0U) - { - /* Entire user buffer sent or received - advance to next one */ - i2sHandle->i2sQueue[queueDriverIndex].data = NULL; - i2sHandle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; - /* Notify user about buffer completion */ - if (i2sHandle->completionCallback != NULL) - { - (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_BufferComplete, i2sHandle->userData); - } - } - - if (i2sHandle->state != (uint32_t)kI2S_DmaStateBusyLoopTransfer) - { - /* check next buffer queue is avaliable or not */ - if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U) - { - if (i2sHandle->state == (uint32_t)kI2S_DmaStateTx) - { - (void)I2S_EmptyTxFifo(base); - } - /* All user buffers processed */ - I2S_TransferAbortDMA(base, i2sHandle); - } - else - { - /* Enqueue another user buffer to DMA if it could not be done when in I2S_Rx/TxTransferSendDMA */ - I2S_AddTransferDMA(base, i2sHandle); - } - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2s_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2s_dma.h deleted file mode 100644 index ec63472653a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_i2s_dma.h +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2S_DMA_H_ -#define _FSL_I2S_DMA_H_ - -#include "fsl_device_registers.h" -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -#include "fsl_dma.h" -#include "fsl_i2s.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup i2s_dma_driver - * @{ - */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2S DMA driver version 2.3.1. */ -#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) -/*@}*/ - -/*! @brief Members not to be accessed / modified outside of the driver. */ -typedef struct _i2s_dma_handle i2s_dma_handle_t; - -/*! - * @brief Callback function invoked from DMA API on completion. - * - * @param base I2S base pointer. - * @param handle pointer to I2S transaction. - * @param completionStatus status of the transaction. - * @param userData optional pointer to user arguments data. - */ -typedef void (*i2s_dma_transfer_callback_t)(I2S_Type *base, - i2s_dma_handle_t *handle, - status_t completionStatus, - void *userData); -/*! @brief i2s dma handle */ -struct _i2s_dma_handle -{ - uint32_t state; /*!< Internal state of I2S DMA transfer */ - uint8_t bytesPerFrame; /*!< bytes per frame */ - i2s_dma_transfer_callback_t completionCallback; /*!< Callback function pointer */ - void *userData; /*!< Application data passed to callback */ - dma_handle_t *dmaHandle; /*!< DMA handle */ - volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ - volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ - volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ - - dma_descriptor_t *i2sLoopDMADescriptor; /*!< descriptor pool pointer */ - size_t i2sLoopDMADescriptorNum; /*!< number of descriptor in descriptors pool */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! @} */ - -/*! - * @name DMA API - * @{ - */ - -/*! - * @brief Initializes handle for transfer of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param dmaHandle pointer to dma handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData); - -/*! - * @brief Begins or queue sending of the given data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts transfer of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle); - -/*! - * @brief Initializes handle for reception of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param dmaHandle pointer to dma handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData); - -/*! - * @brief Begins or queue reception of data into given buffer. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers - * which are not full. - */ -status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Invoked from DMA interrupt handler. - * - * @param handle pointer to DMA handle structure. - * @param userData argument for user callback. - * @param transferDone if transfer was done. - * @param tcds - */ -void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds); - -/*! - * @brief Install DMA descriptor memory for loop transfer only. - * - * This function used to register DMA descriptor memory for the i2s loop dma transfer. - * - * It must be callbed before I2S_TransferSendLoopDMA/I2S_TransferReceiveLoopDMA and after - * I2S_RxTransferCreateHandleDMA/I2S_TxTransferCreateHandleDMA. - * - * User should be take care about the address of DMA descriptor pool which required align with 16BYTE at least. - * - * @param handle Pointer to i2s DMA transfer handle. - * @param dmaDescriptorAddr DMA descriptor start address. - * @param dmaDescriptorNum DMA descriptor number. - */ -void I2S_TransferInstallLoopDMADescriptorMemory(i2s_dma_handle_t *handle, - void *dmaDescriptorAddr, - size_t dmaDescriptorNum); - -/*! - * @brief Send link transfer data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * This function support loop transfer, such as A->B->...->A, the loop transfer chain - * will be converted into a chain of descriptor and submit to dma. - * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, - * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. - * - * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support - * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop - * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. - * - * @param base I2S peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param xfer I2S DMA transfer structure. See #i2s_transfer_t. - * @param loopTransferCount loop count - * @retval kStatus_Success - */ -status_t I2S_TransferSendLoopDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - i2s_transfer_t *xfer, - uint32_t loopTransferCount); - -/*! - * @brief Receive link transfer data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * This function support loop transfer, such as A->B->...->A, the loop transfer chain - * will be converted into a chain of descriptor and submit to dma. - * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, - * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. - * - * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support - * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop - * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. - * - * @param base I2S peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param xfer I2S DMA transfer structure. See #i2s_transfer_t. - * @param loopTransferCount loop count - * @retval kStatus_Success - */ -status_t I2S_TransferReceiveLoopDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - i2s_transfer_t *xfer, - uint32_t loopTransferCount); - -/*! @} */ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2S_DMA_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_iap.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_iap.c deleted file mode 100644 index 712b0faef71..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_iap.c +++ /dev/null @@ -1,666 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "fsl_iap.h" -#include "fsl_iap_ffr.h" -#include "fsl_iap_kbp.h" -#include "fsl_iap_skboot_authenticate.h" -#include "fsl_device_registers.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.iap1" -#endif - -#if (defined(LPC5512_SERIES) || defined(LPC5514_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ - defined(LPC55S16_SERIES) || defined(LPC5524_SERIES) || defined(LPC5502_SERIES) || defined(LPC5504_SERIES) || \ - defined(LPC5506_SERIES) || defined(LPC55S04_SERIES) || defined(LPC55S06_SERIES)) - -#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1301fe00U) - -#elif (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || defined(LPC5526_SERIES) || \ - defined(LPC55S26_SERIES) || defined(LPC5528_SERIES) || defined(LPC55S28_SERIES) || \ - defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES)) - -#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x130010f0U) - -#else -#error "No valid CPU defined!" - -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -static status_t get_cfpa_higher_version(flash_config_t *config); - -/*! - * @name flash and ffr Structure - * @{ - */ - -typedef union functionCommandOption -{ - uint32_t commandAddr; - status_t (*eraseCommand)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - status_t (*programCommand)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); - status_t (*verifyProgramCommand)(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - status_t (*flashReadCommand)(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); -} function_command_option_t; - -/* - *!@brief Structure of version property. - * - *!@ingroup bl_core - */ -typedef union StandardVersion -{ - struct - { - uint32_t bugfix : 8; /*!< bugfix version [7:0] */ - uint32_t minor : 8; /*!< minor version [15:8] */ - uint32_t major : 8; /*!< major version [23:16] */ - uint32_t name : 8; /*!< name [31:24] */ - }; - uint32_t version; /*!< combined version numbers. */ -#if defined(__cplusplus) - StandardVersion() : version(0) - { - } - StandardVersion(uint32_t version) : version(version) - { - } -#endif -} standard_version_t; - -/*! @brief Interface for the flash driver.*/ -typedef struct version1FlashDriverInterface -{ - standard_version_t version; /*!< flash driver API version number.*/ - - /*!< Flash driver.*/ - status_t (*flash_init)(flash_config_t *config); - status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); - status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); - status_t (*flash_verify_program)(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); - uint32_t reserved[3]; /*! Reserved for future use */ - /*!< Flash FFR driver*/ - status_t (*ffr_init)(flash_config_t *config); - status_t (*ffr_lock_all)(flash_config_t *config); - status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); - status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); - status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); - status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode); - status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); - status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); - status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); -} version1_flash_driver_interface_t; - -/*! @brief Interface for the flash driver.*/ -typedef struct version0FlashDriverInterface -{ - standard_version_t version; /*!< flash driver API version number.*/ - - /*!< Flash driver.*/ - status_t (*flash_init)(flash_config_t *config); - status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); - status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); - status_t (*flash_verify_program)(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); - - /*!< Flash FFR driver*/ - status_t (*ffr_init)(flash_config_t *config); - status_t (*ffr_lock_all)(flash_config_t *config); - status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); - status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); - status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); - status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode); - status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); - status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); - status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); -} version0_flash_driver_interface_t; - -typedef union flashDriverInterface -{ - const version1_flash_driver_interface_t *version1FlashDriver; - const version0_flash_driver_interface_t *version0FlashDriver; -} flash_driver_interface_t; - -/*! @}*/ - -/*! - * @name Bootloader API and image authentication Structure - * @{ - */ - -/*! @brief Interface for Bootloader API functions. */ -typedef struct _kb_interface -{ - /*!< Initialize the API. */ - status_t (*kb_init_function)(kb_session_ref_t **session, const kb_options_t *options); - status_t (*kb_deinit_function)(kb_session_ref_t *session); - status_t (*kb_execute_function)(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength); -} kb_interface_t; - -//! @brief Interface for image authentication API -typedef struct _skboot_authenticate_interface -{ - skboot_status_t (*skboot_authenticate_function)(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified); - void (*skboot_hashcrypt_irq_handler)(void); -} skboot_authenticate_interface_t; -/*! @}*/ - -/*! - * @brief Root of the bootloader API tree. - * - * An instance of this struct resides in read-only memory in the bootloader. It - * provides a user application access to APIs exported by the bootloader. - * - * @note The order of existing fields must not be changed. - */ -typedef struct BootloaderTree -{ - void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing. */ - standard_version_t bootloader_version; /*!< Bootloader version number. */ - const char *copyright; /*!< Copyright string. */ - const uint32_t reserved0; /*!< Do NOT use. */ - flash_driver_interface_t flashDriver; - const kb_interface_t *kbApi; /*!< Bootloader API. */ - const uint32_t reserved1[4]; /*!< Do NOT use. */ - const skboot_authenticate_interface_t *skbootAuthenticate; /*!< Image authentication API. */ -} bootloader_tree_t; - -/******************************************************************************* - * Prototype - ******************************************************************************/ -static uint32_t get_rom_api_version(void); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! Get pointer to flash driver API table in ROM. */ -#define VERSION1_FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver.version1FlashDriver -#define VERSION0_FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver.version0FlashDriver -#define LPC55S69_REV0_FLASH_READ_ADDR (0x130043a3U) -#define LPC55S69_REV1_FLASH_READ_ADDR (0x13007539U) -#define LPC55S16_REV0_FLASH_READ_ADDR (0x1300ade5U) - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t get_rom_api_version(void) -{ - if (BOOTLOADER_API_TREE_POINTER->bootloader_version.major == 3u) - { - return 1u; - } - else - { - return 0u; - } -} - -/*! - * @brief Initializes the global flash properties structure members. - * - * This function checks and initializes the Flash module for the other Flash APIs. - */ -status_t FLASH_Init(flash_config_t *config) -{ - status_t status; - /* Initialize the clock to 96MHz */ - config->modeConfig.sysFreqInMHz = (uint32_t)kSysToFlashFreq_defaultInMHz; - if (get_rom_api_version() == 1u) - { - status = VERSION1_FLASH_API_TREE->flash_init(config); - } - else - { - status = VERSION0_FLASH_API_TREE->flash_init(config); - } - - if (config->PFlashTotalSize == 0xA0000U) - { - config->PFlashTotalSize -= 17U * config->PFlashPageSize; - } - - return status; -} - -/*! - * @brief Erases the flash sectors encompassed by parameters passed into function. - * - * This function erases the appropriate number of flash sectors based on the - * desired start address and length. - */ -status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) -{ - if (get_rom_api_version() == 0u) - { - function_command_option_t runCmdFuncOption; - runCmdFuncOption.commandAddr = 0x1300413bU; /*!< get the flash erase api location adress in rom */ - return runCmdFuncOption.eraseCommand(config, start, lengthInBytes, key); - } - else - { - return VERSION1_FLASH_API_TREE->flash_erase(config, start, lengthInBytes, key); - } -} - -/*! See fsl_iap.h for documentation of this function. */ -status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) -{ - if (get_rom_api_version() == 0u) - { - function_command_option_t runCmdFuncOption; - runCmdFuncOption.commandAddr = 0x1300419dU; /*!< get the flash program api location adress in rom*/ - return runCmdFuncOption.programCommand(config, start, src, lengthInBytes); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->flash_program(config, start, src, lengthInBytes); - } -} - -/*! See fsl_iap.h for documentation of this function. */ -status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes) -{ - if (get_rom_api_version() == 0u) - { - /*!< get the flash read api location adress in rom*/ - function_command_option_t runCmdFuncOption; - runCmdFuncOption.commandAddr = LPC55S69_REV0_FLASH_READ_ADDR; - return runCmdFuncOption.flashReadCommand(config, start, dest, lengthInBytes); - } - else - { - /*!< get the flash read api location adress in rom*/ - function_command_option_t runCmdFuncOption; - if ((SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK) != 0u) - { - runCmdFuncOption.commandAddr = LPC55S69_REV1_FLASH_READ_ADDR; - } - else - { - runCmdFuncOption.commandAddr = LPC55S16_REV0_FLASH_READ_ADDR; - } - return runCmdFuncOption.flashReadCommand(config, start, dest, lengthInBytes); - } -} - -/*! See fsl_iap.h for documentation of this function. */ -status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) -{ - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->flash_verify_erase(config, start, lengthInBytes); -} - -/*! - * @brief Verifies programming of the desired flash area at a specified margin level. - * - * This function verifies the data programed in the flash memory using the - * Flash Program Check Command and compares it to the expected data for a given - * flash area as determined by the start address and length. - */ -status_t FLASH_VerifyProgram(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData) -{ - if (get_rom_api_version() == 0u) - { - function_command_option_t runCmdFuncOption; - runCmdFuncOption.commandAddr = 0x1300427dU; /*!< get the flash verify program api location adress in rom*/ - return runCmdFuncOption.verifyProgramCommand(config, start, lengthInBytes, expectedData, failedAddress, - failedData); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->flash_verify_program(config, start, lengthInBytes, expectedData, failedAddress, - failedData); - } -} - -/*! - * @brief Returns the desired flash property. - */ -status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) -{ - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->flash_get_property(config, whichProperty, value); -} -/******************************************************************************** - * fsl iap ffr CODE - *******************************************************************************/ - -static status_t get_cfpa_higher_version(flash_config_t *config) -{ - uint32_t pageData[FLASH_FFR_MAX_PAGE_SIZE / sizeof(uint32_t)]; - uint32_t versionPing = 0U; - uint32_t versionPong = 0U; - - /* Get the CFPA ping page data and the corresponding version */ - config->ffrConfig.cfpaPageOffset = 1U; - status_t status = FFR_GetCustomerInfieldData(config, (uint8_t *)pageData, 0U, FLASH_FFR_MAX_PAGE_SIZE); - if (status != (int32_t)kStatus_FLASH_Success) - { - return status; - } - versionPing = pageData[1]; - - /* Get the CFPA pong page data and the corresponding version */ - config->ffrConfig.cfpaPageOffset = 2U; - status = FFR_GetCustomerInfieldData(config, (uint8_t *)pageData, 0U, FLASH_FFR_MAX_PAGE_SIZE); - if (status != (int32_t)kStatus_FLASH_Success) - { - return status; - } - versionPong = pageData[1]; - - /* Compare the CFPA ping version and pong version and set it correctly in flash_config structure */ - if (versionPing > versionPong) - { - config->ffrConfig.cfpaPageVersion = versionPing; - config->ffrConfig.cfpaPageOffset = 1U; - } - else - { - config->ffrConfig.cfpaPageVersion = versionPong; - config->ffrConfig.cfpaPageOffset = 2U; - } - return (int32_t)kStatus_FLASH_Success; -} - -/*! - * Initializes the global FFR properties structure members. - */ -status_t FFR_Init(flash_config_t *config) -{ - status_t status; - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - status = VERSION0_FLASH_API_TREE->ffr_init(config); - if (status != (status_t)kStatus_FLASH_Success) - { - return status; - } - return get_cfpa_higher_version(config); - } - else - { - assert(VERSION1_FLASH_API_TREE); - status = VERSION1_FLASH_API_TREE->ffr_init(config); - if (status != (status_t)kStatus_FLASH_Success) - { - return status; - } - return get_cfpa_higher_version(config); - } -} - -/*! - * Enable firewall for all flash banks. - */ -status_t FFR_Lock_All(flash_config_t *config) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_lock_all(config); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_lock_all(config); - } -} - -/*! - * APIs to access CMPA pages; - * This routine will erase "customer factory page" and program the page with passed data. - */ -status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part); - } -} - -/*! - * See fsl_iap_ffr.h for documentation of this function. - */ -status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_get_uuid(config, uuid); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_get_uuid(config, uuid); - } -} - -/*! - * APIs to access CMPA pages - * Read data stored in 'Customer Factory CFG Page'. - */ -status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len); - } -} - -/*! - * This routine writes the 3 pages allocated for Key store data, - * Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state. - */ -status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_keystore_write(config, pKeyStore); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_keystore_write(config, pKeyStore); - } -} - -/*! See fsl_iap_ffr.h for documentation of this function. */ -status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode); - } -} - -/*! See fsl_iap_ffr.h for documentation of this function. */ -status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex); - } -} - -/*! - * APIs to access CFPA pages - * This routine will erase CFPA and program the CFPA page with passed data. - */ -status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len); - } -} - -/*! - * APIs to access CFPA pages - * Generic read function, used by customer to read data stored in 'Customer In-field Page'. - */ -status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len); - } -} - -/******************************************************************************** - * Bootloader API - *******************************************************************************/ -/*! - * @brief Initialize ROM API for a given operation. - * - * Inits the ROM API based on the options provided by the application in the second - * argument. Every call to rom_init() should be paired with a call to rom_deinit(). - */ -status_t kb_init(kb_session_ref_t **session, const kb_options_t *options) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->kbApi->kb_init_function(session, options); -} - -/*! - * @brief Cleans up the ROM API context. - * - * After this call, the @a context parameter can be reused for another operation - * by calling rom_init() again. - */ -status_t kb_deinit(kb_session_ref_t *session) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->kbApi->kb_deinit_function(session); -} - -/*! - * Perform the operation configured during init. - * - * This application must call this API repeatedly, passing in sequential chunks of - * data from the boot image (SB file) that is to be processed. The ROM will perform - * the selected operation on this data and return. The application may call this - * function with as much or as little data as it wishes, which can be used to select - * the granularity of time given to the application in between executing the operation. - * - * @param context Current ROM context pointer. - * @param data Buffer of boot image data provided to the ROM by the application. - * @param dataLength Length in bytes of the data in the buffer provided to the ROM. - * - * @retval #kStatus_Success The operation has completed successfully. - * @retval #kStatus_Fail An error occurred while executing the operation. - * @retval #kStatus_RomApiNeedMoreData No error occurred, but the ROM needs more data to - * continue processing the boot image. - */ -status_t kb_execute(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->kbApi->kb_execute_function(session, data, dataLength); -} - -/******************************************************************************** - * Image authentication API - *******************************************************************************/ - -/*! - * @brief Authenticate entry function with ARENA allocator init - * - * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface - */ -skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->skbootAuthenticate->skboot_authenticate_function(imageStartAddr, - isSignVerified); -} - -/*! - * @brief Interface for image authentication API - */ -void HASH_IRQHandler(void) -{ - assert(BOOTLOADER_API_TREE_POINTER); - BOOTLOADER_API_TREE_POINTER->skbootAuthenticate->skboot_hashcrypt_irq_handler(); -} -/******************************************************************************** - * EOF - *******************************************************************************/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_iap.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_iap.h deleted file mode 100644 index f7b318b66bd..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_iap.h +++ /dev/null @@ -1,528 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __FSL_IAP_H_ -#define __FSL_IAP_H_ - -#include "fsl_common.h" -/*! - * @addtogroup flash_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! - * @name Flash version - * @{ - */ -/*! @brief Constructs the version number for drivers. */ -#if !defined(MAKE_VERSION) -#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) -#endif - -/*! @brief Flash driver version for SDK*/ -#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4. */ - -/*! @brief Flash driver version for ROM*/ -enum _flash_driver_version_constants -{ - kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ - kFLASH_DriverVersionMajor = 2, /*!< Major flash driver version.*/ - kFLASH_DriverVersionMinor = 1, /*!< Minor flash driver version.*/ - kFLASH_DriverVersionBugfix = 3 /*!< Bugfix for flash driver version.*/ -}; - -/*@}*/ - -/*! - * @name Flash configuration - * @{ - */ -/*! @brief Flash IP Type. */ -#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC) -#define FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC (1) -#endif -#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_FC) -#define FSL_FEATURE_FLASH_IP_IS_C040HD_FC (0) -#endif - -/*! - * @name Flash status - * @{ - */ -/*! @brief Flash driver status group. */ -#if defined(kStatusGroup_FlashDriver) -#define kStatusGroupGeneric kStatusGroup_Generic -#define kStatusGroupFlashDriver kStatusGroup_FlashDriver -#elif defined(kStatusGroup_FLASHIAP) -#define kStatusGroupGeneric kStatusGroup_Generic -#define kStatusGroupFlashDriver kStatusGroup_FLASH -#else -#define kStatusGroupGeneric 0 -#define kStatusGroupFlashDriver 1 -#endif - -/*! @brief Constructs a status code value from a group and a code number. */ -#if !defined(MAKE_STATUS) -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) -#endif - -/*! - * @brief Flash driver status codes. - */ -enum _flash_status -{ - kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ - kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ - kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ - kStatus_FLASH_AlignmentError = - MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ - kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ - kStatus_FLASH_AccessError = - MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ - kStatus_FLASH_ProtectionViolation = MAKE_STATUS( - kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ - kStatus_FLASH_CommandFailure = - MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ - kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ - kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/ - kStatus_FLASH_RegionExecuteOnly = - MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/ - kStatus_FLASH_ExecuteInRamFunctionNotReady = - MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/ - - kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Flash API is not supported.*/ - kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< The flash property is read-only.*/ - kStatus_FLASH_InvalidPropertyValue = - MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< The flash property value is out of range.*/ - kStatus_FLASH_InvalidSpeculationOption = - MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< The option of flash prefetch speculation is invalid.*/ - kStatus_FLASH_EccError = MAKE_STATUS(kStatusGroupFlashDriver, - 0x10), /*!< A correctable or uncorrectable error during command execution. */ - kStatus_FLASH_CompareError = - MAKE_STATUS(kStatusGroupFlashDriver, 0x11), /*!< Destination and source memory contents do not match. */ - kStatus_FLASH_RegulationLoss = MAKE_STATUS(kStatusGroupFlashDriver, 0x12), /*!< A loss of regulation during read. */ - kStatus_FLASH_InvalidWaitStateCycles = - MAKE_STATUS(kStatusGroupFlashDriver, 0x13), /*!< The wait state cycle set to r/w mode is invalid. */ - - kStatus_FLASH_OutOfDateCfpaPage = - MAKE_STATUS(kStatusGroupFlashDriver, 0x20), /*!< CFPA page version is out of date. */ - kStatus_FLASH_BlankIfrPageData = MAKE_STATUS(kStatusGroupFlashDriver, 0x21), /*!< Blank page cannnot be read. */ - kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce = - MAKE_STATUS(kStatusGroupFlashDriver, 0x22), /*!< Encrypted flash subregions are not erased at once. */ - kStatus_FLASH_ProgramVerificationNotAllowed = MAKE_STATUS( - kStatusGroupFlashDriver, 0x23), /*!< Program verification is not allowed when the encryption is enabled. */ - kStatus_FLASH_HashCheckError = - MAKE_STATUS(kStatusGroupFlashDriver, 0x24), /*!< Hash check of page data is failed. */ - kStatus_FLASH_SealedFfrRegion = MAKE_STATUS(kStatusGroupFlashDriver, 0x25), /*!< The FFR region is sealed. */ - kStatus_FLASH_FfrRegionWriteBroken = MAKE_STATUS( - kStatusGroupFlashDriver, 0x26), /*!< The FFR Spec region is not allowed to be written discontinuously. */ - kStatus_FLASH_NmpaAccessNotAllowed = - MAKE_STATUS(kStatusGroupFlashDriver, 0x27), /*!< The NMPA region is not allowed to be read/written/erased. */ - kStatus_FLASH_CmpaCfgDirectEraseNotAllowed = - MAKE_STATUS(kStatusGroupFlashDriver, 0x28), /*!< The CMPA Cfg region is not allowed to be erased directly. */ - kStatus_FLASH_FfrBankIsLocked = MAKE_STATUS(kStatusGroupFlashDriver, 0x29), /*!< The FFR bank region is locked. */ -}; -/*@}*/ - -/*! - * @name Flash API key - * @{ - */ -/*! @brief Constructs the four character code for the Flash driver API key. */ -#if !defined(FOUR_CHAR_CODE) -#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) -#endif - -/*! - * @brief Enumeration for Flash driver API keys. - * - * @note The resulting value is built with a byte order such that the string - * being readable in expected order when viewed in a hex editor, if the value - * is treated as a 32-bit little endian value. - */ -enum _flash_driver_api_keys -{ - kFLASH_ApiEraseKey = FOUR_CHAR_CODE('l', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ -}; -/*@}*/ - -/*! - * @brief Enumeration for various flash properties. - */ -typedef enum _flash_property_tag -{ - kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ - kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ - kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ - kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ - kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ - - kFLASH_PropertyPflashPageSize = 0x30U, /*!< Pflash page size property.*/ - kFLASH_PropertyPflashSystemFreq = 0x31U, /*!< System Frequency System Frequency.*/ - - kFLASH_PropertyFfrSectorSize = 0x40U, /*!< FFR sector size property.*/ - kFLASH_PropertyFfrTotalSize = 0x41U, /*!< FFR total size property.*/ - kFLASH_PropertyFfrBlockBaseAddr = 0x42U, /*!< FFR block base address property.*/ - kFLASH_PropertyFfrPageSize = 0x43U, /*!< FFR page size property.*/ -} flash_property_tag_t; - -/*! - * @brief Enumeration for flash max pages to erase. - */ -enum _flash_max_erase_page_value -{ - kFLASH_MaxPagesToErase = 100U /*!< The max value in pages to erase. */ -}; - -/*! - * @brief Enumeration for flash alignment property. - */ -enum _flash_alignment_property -{ - kFLASH_AlignementUnitVerifyErase = 4, /*!< The alignment unit in bytes used for verify erase operation.*/ - kFLASH_AlignementUnitProgram = 512, /*!< The alignment unit in bytes used for program operation.*/ - /*kFLASH_AlignementUnitVerifyProgram = 4,*/ /*!< The alignment unit in bytes used for verify program operation.*/ - kFLASH_AlignementUnitSingleWordRead = 16 /*!< The alignment unit in bytes used for SingleWordRead command.*/ -}; - -/*! - * @brief Enumeration for flash read ecc option - */ -enum _flash_read_ecc_option -{ - kFLASH_ReadWithEccOn = 0, /*! ECC is on */ - kFLASH_ReadWithEccOff = 1, /*! ECC is off */ -}; - -/* set flash Controller timing before flash init */ -enum _flash_freq_tag -{ - kSysToFlashFreq_lowInMHz = 12u, - kSysToFlashFreq_defaultInMHz = 96u, -}; - -/*! - * @brief Enumeration for flash read margin option - */ -enum _flash_read_margin_option -{ - kFLASH_ReadMarginNormal = 0, /*!< Normal read */ - kFLASH_ReadMarginVsProgram = 1, /*!< Margin vs. program */ - kFLASH_ReadMarginVsErase = 2, /*!< Margin vs. erase */ - kFLASH_ReadMarginIllegalBitCombination = 3 /*!< Illegal bit combination */ -}; - -/*! - * @brief Enumeration for flash read dmacc option - */ -enum _flash_read_dmacc_option -{ - kFLASH_ReadDmaccDisabled = 0, /*!< Memory word */ - kFLASH_ReadDmaccEnabled = 1, /*!< DMACC word */ -}; - -/*! - * @brief Enumeration for flash ramp control option - */ -enum _flash_ramp_control_option -{ - kFLASH_RampControlDivisionFactorReserved = 0, /*!< Reserved */ - kFLASH_RampControlDivisionFactor256 = 1, /*!< clk48mhz / 256 = 187.5KHz */ - kFLASH_RampControlDivisionFactor128 = 2, /*!< clk48mhz / 128 = 375KHz */ - kFLASH_RampControlDivisionFactor64 = 3 /*!< clk48mhz / 64 = 750KHz */ -}; - -/*! @brief Flash ECC log info. */ -typedef struct _flash_ecc_log -{ - uint32_t firstEccEventAddress; - uint32_t eccErrorCount; - uint32_t eccCorrectionCount; - uint32_t reserved; -} flash_ecc_log_t; - -/*! @brief Flash controller paramter config. */ -typedef struct _flash_mode_config -{ - uint32_t sysFreqInMHz; - /* ReadSingleWord parameter. */ - struct - { - uint8_t readWithEccOff : 1; - uint8_t readMarginLevel : 2; - uint8_t readDmaccWord : 1; - uint8_t reserved0 : 4; - uint8_t reserved1[3]; - } readSingleWord; - /* SetWriteMode parameter. */ - struct - { - uint8_t programRampControl; - uint8_t eraseRampControl; - uint8_t reserved[2]; - } setWriteMode; - /* SetReadMode parameter. */ - struct - { - uint16_t readInterfaceTimingTrim; - uint16_t readControllerTimingTrim; - uint8_t readWaitStates; - uint8_t reserved[3]; - } setReadMode; -} flash_mode_config_t; - -/*! @brief Flash controller paramter config. */ -typedef struct _flash_ffr_config -{ - uint32_t ffrBlockBase; - uint32_t ffrTotalSize; - uint32_t ffrPageSize; - uint32_t cfpaPageVersion; - uint32_t cfpaPageOffset; -} flash_ffr_config_t; - -/*! @brief Flash driver state information. - * - * An instance of this structure is allocated by the user of the flash driver and - * passed into each of the driver APIs. - */ -typedef struct _flash_config -{ - uint32_t PFlashBlockBase; /*!< A base address of the first PFlash block */ - uint32_t PFlashTotalSize; /*!< The size of the combined PFlash block. */ - uint32_t PFlashBlockCount; /*!< A number of PFlash blocks. */ - uint32_t PFlashPageSize; /*!< The size in bytes of a page of PFlash. */ - uint32_t PFlashSectorSize; /*!< The size in bytes of a sector of PFlash. */ - flash_ffr_config_t ffrConfig; - flash_mode_config_t modeConfig; -} flash_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization - * @{ - */ - -/*! - * @brief Initializes the global flash properties structure members. - * - * This function checks and initializes the Flash module for the other Flash APIs. - * - * @param config Pointer to the storage for the driver runtime state. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_Init(flash_config_t *config); - -/*@}*/ - -/*! - * @name Erasing - * @{ - */ - -/*! - * @brief Erases the flash sectors encompassed by parameters passed into function. - * - * This function erases the appropriate number of flash sectors based on the - * desired start address and length. - * - * @param config The pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be erased. - * The start address need to be 512bytes-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words) - * to be erased. Must be 512bytes-aligned. - * @param key The value used to validate all flash erase APIs. - * - * @retval #kStatus_FLASH_Success API was executed successfully; - * the appropriate number of flash sectors based on the desired - * start address and length were erased successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_AddressError The address is out of range. - * @retval #kStatus_FLASH_EraseKeyError The API erase key is invalid. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - -/*@}*/ - -/*! - * @name Programming - * @{ - */ - -/*! - * @brief Programs flash with data at locations passed in through parameters. - * - * This function programs the flash memory with the desired data for a given - * flash area as determined by the start address and the length. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be programmed. Must be - * 512bytes-aligned. - * @param src A pointer to the source buffer of data that is to be programmed - * into the flash. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be programmed. Must be 512bytes-aligned. - * - * @retval #kStatus_FLASH_Success API was executed successfully; the desired data were programed successfully - * into flash based on desired start address and length. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); - -/*@}*/ - -/*! - * @brief Reads flash at locations passed in through parameters. - * - * This function read the flash memory from a given flash area as determined - * by the start address and the length. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be read. - * @param dest A pointer to the dest buffer of data that is to be read - * from the flash. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be read. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); - -/*! - * @name Verification - * @{ - */ - -/*! - * @brief Verifies an erasure of the desired flash area at a specified margin level. - * - * This function checks the appropriate number of flash sectors based on - * the desired start address and length to check whether the flash is erased - * to the specified read margin level. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be verified. - * The start address need to be 512bytes-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be verified. Must be 512bytes-aligned. - * - * @retval #kStatus_FLASH_Success API was executed successfully; the specified FLASH region has been erased. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); - -/*! - * @brief Verifies programming of the desired flash area at a specified margin level. - * - * This function verifies the data programed in the flash memory using the - * Flash Program Check Command and compares it to the expected data for a given - * flash area as determined by the start address and length. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be verified. need be 512bytes-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be verified. need be 512bytes-aligned. - * @param expectedData A pointer to the expected data that is to be - * verified against. - * @param failedAddress A pointer to the returned failing address. - * @param failedData A pointer to the returned failing data. Some derivatives do - * not include failed data as part of the FCCOBx registers. In this - * case, zeros are returned upon failure. - * - * @retval #kStatus_FLASH_Success API was executed successfully; - * the desired data have been successfully programed into specified FLASH region. - * - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_VerifyProgram(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - -/*@}*/ - -/*! - * @name Properties - * @{ - */ - -/*! - * @brief Returns the desired flash property. - * - * @param config A pointer to the storage for the driver runtime state. - * @param whichProperty The desired property from the list of properties in - * enum flash_property_tag_t - * @param value A pointer to the value returned for the desired flash property. - * - * @retval #kStatus_FLASH_Success API was executed successfully; the flash property was stored to value. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_UnknownProperty An unknown property tag. - */ -status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); - -/*@}*/ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* __FLASH_FLASH_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_iap_ffr.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_iap_ffr.h deleted file mode 100644 index 9481e07af14..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_iap_ffr.h +++ /dev/null @@ -1,388 +0,0 @@ -/* - * Copyright 2018-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __FSL_IAP_FFR_H_ -#define __FSL_IAP_FFR_H_ - -#include "fsl_iap.h" - -/*! - * @addtogroup flash_ifr_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! - * @name Flash IFR version - * @{ - */ -/*! @brief Flash IFR driver version for SDK*/ -#define FSL_FLASH_IFR_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ -/*@}*/ - -/*! @brief Alignment(down) utility. */ -#if !defined(ALIGN_DOWN) -#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) -#endif - -/*! @brief Alignment(up) utility. */ -#if !defined(ALIGN_UP) -#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) -#endif - -#define FLASH_FFR_MAX_PAGE_SIZE (512u) -#define FLASH_FFR_HASH_DIGEST_SIZE (32u) -#define FLASH_FFR_IV_CODE_SIZE (52u) - -/*! @brief flash ffr page offset. */ -enum _flash_ffr_page_offset -{ - kFfrPageOffset_CFPA = 0, /*!< Customer In-Field programmed area*/ - kFfrPageOffset_CFPA_Scratch = 0, /*!< CFPA Scratch page */ - kFfrPageOffset_CFPA_Cfg = 1, /*!< CFPA Configuration area (Ping page)*/ - kFfrPageOffset_CFPA_CfgPong = 2, /*!< Same as CFPA page (Pong page)*/ - - kFfrPageOffset_CMPA = 3, /*!< Customer Manufacturing programmed area*/ - kFfrPageOffset_CMPA_Cfg = 3, /*!< CMPA Configuration area (Part of CMPA)*/ - kFfrPageOffset_CMPA_Key = 4, /*!< Key Store area (Part of CMPA)*/ - - kFfrPageOffset_NMPA = 7, /*!< NXP Manufacturing programmed area*/ - kFfrPageOffset_NMPA_Romcp = 7, /*!< ROM patch area (Part of NMPA)*/ - kFfrPageOffset_NMPA_Repair = 9, /*!< Repair area (Part of NMPA)*/ - kFfrPageOffset_NMPA_Cfg = 15, /*!< NMPA configuration area (Part of NMPA)*/ - kFfrPageOffset_NMPA_End = 16, /*!< Reserved (Part of NMPA)*/ -}; - -/*! @brief flash ffr page number. */ -enum _flash_ffr_page_num -{ - kFfrPageNum_CFPA = 3, /*!< Customer In-Field programmed area*/ - kFfrPageNum_CMPA = 4, /*!< Customer Manufacturing programmed area*/ - kFfrPageNum_NMPA = 10, /*!< NXP Manufacturing programmed area*/ - - kFfrPageNum_CMPA_Cfg = 1, - kFfrPageNum_CMPA_Key = 3, - kFfrPageNum_NMPA_Romcp = 2, - - kFfrPageNum_SpecArea = kFfrPageNum_CFPA + kFfrPageNum_CMPA, - kFfrPageNum_Total = (kFfrPageNum_CFPA + kFfrPageNum_CMPA + kFfrPageNum_NMPA), -}; - -enum _flash_ffr_block_size -{ - kFfrBlockSize_Key = 52u, - kFfrBlockSize_ActivationCode = 1192u, -}; - -typedef enum _cfpa_cfg_cmpa_prog_process -{ - kFfrCmpaProgProcess_Pre = 0x0u, - kFfrCmpaProgProcess_Post = 0xFFFFFFFFu, -} cmpa_prog_process_t; - -typedef struct _cfpa_cfg_iv_code -{ - uint32_t keycodeHeader; - uint8_t reserved[FLASH_FFR_IV_CODE_SIZE]; -} cfpa_cfg_iv_code_t; - -typedef struct _cfpa_cfg_info -{ - uint32_t header; /*!< [0x000-0x003] */ - uint32_t version; /*!< [0x004-0x007 */ - uint32_t secureFwVersion; /*!< [0x008-0x00b */ - uint32_t nsFwVersion; /*!< [0x00c-0x00f] */ - uint32_t imageKeyRevoke; /*!< [0x010-0x013] */ - uint8_t reserved0[4]; /*!< [0x014-0x017] */ - uint32_t rotkhRevoke; /*!< [0x018-0x01b] */ - uint32_t vendorUsage; /*!< [0x01c-0x01f] */ - uint32_t dcfgNsPin; /*!< [0x020-0x013] */ - uint32_t dcfgNsDflt; /*!< [0x024-0x017] */ - uint32_t enableFaMode; /*!< [0x028-0x02b] */ - uint8_t reserved1[4]; /*!< [0x02c-0x02f] */ - cfpa_cfg_iv_code_t ivCodePrinceRegion[3]; /*!< [0x030-0x0d7] */ - uint8_t reserved2[264]; /*!< [0x0d8-0x1df] */ - uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */ -} cfpa_cfg_info_t; - -#define FFR_BOOTCFG_BOOTSPEED_MASK (0x18U) -#define FFR_BOOTCFG_BOOTSPEED_SHIFT (7U) -#define FFR_BOOTCFG_BOOTSPEED_48MHZ (0x0U) -#define FFR_BOOTCFG_BOOTSPEED_96MHZ (0x1U) - -#define FFR_USBID_VENDORID_MASK (0xFFFFU) -#define FFR_USBID_VENDORID_SHIFT (0U) -#define FFR_USBID_PRODUCTID_MASK (0xFFFF0000U) -#define FFR_USBID_PRODUCTID_SHIFT (16U) - -typedef struct _cmpa_cfg_info -{ - uint32_t bootCfg; /*!< [0x000-0x003] */ - uint32_t spiFlashCfg; /*!< [0x004-0x007] */ - struct - { - uint16_t vid; - uint16_t pid; - } usbId; /*!< [0x008-0x00b] */ - uint32_t sdioCfg; /*!< [0x00c-0x00f] */ - uint32_t dcfgPin; /*!< [0x010-0x013] */ - uint32_t dcfgDflt; /*!< [0x014-0x017] */ - uint32_t dapVendorUsage; /*!< [0x018-0x01b] */ - uint32_t secureBootCfg; /*!< [0x01c-0x01f] */ - uint32_t princeBaseAddr; /*!< [0x020-0x023] */ - uint32_t princeSr[3]; /*!< [0x024-0x02f] */ - uint8_t reserved0[32]; /*!< [0x030-0x04f] */ - uint32_t rotkh[8]; /*!< [0x050-0x06f] */ - uint8_t reserved1[368]; /*!< [0x070-0x1df] */ - uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */ -} cmpa_cfg_info_t; - -typedef struct _cmpa_key_store_header -{ - uint32_t header; - uint8_t reserved[4]; -} cmpa_key_store_header_t; - -#define FFR_SYSTEM_SPEED_CODE_MASK (0x3U) -#define FFR_SYSTEM_SPEED_CODE_SHIFT (0U) -#define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ (0x0U) -#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_24MHZ (0x1U) -#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_48MHZ (0x2U) -#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_96MHZ (0x3U) - -#define FFR_PERIPHERALCFG_PERI_MASK (0x7FFFFFFFU) -#define FFR_PERIPHERALCFG_PERI_SHIFT (0U) -#define FFR_PERIPHERALCFG_COREEN_MASK (0x10000000U) -#define FFR_PERIPHERALCFG_COREEN_SHIFT (31U) - -typedef struct _nmpa_cfg_info -{ - uint16_t fro32kCfg; /*!< [0x000-0x001] */ - uint8_t reserved0[6]; /*!< [0x002-0x007] */ - uint8_t sysCfg; /*!< [0x008-0x008] */ - uint8_t reserved1[7]; /*!< [0x009-0x00f] */ - struct - { - uint32_t data; - uint32_t reserved[3]; - } GpoInitData[3]; /*!< [0x010-0x03f] */ - uint32_t GpoDataChecksum[4]; /*!< [0x040-0x04f] */ - uint32_t finalTestBatchId[4]; /*!< [0x050-0x05f] */ - uint32_t deviceType; /*!< [0x060-0x063] */ - uint32_t finalTestProgVersion; /*!< [0x064-0x067] */ - uint32_t finalTestDate; /*!< [0x068-0x06b] */ - uint32_t finalTestTime; /*!< [0x06c-0x06f] */ - uint32_t uuid[4]; /*!< [0x070-0x07f] */ - uint8_t reserved2[32]; /*!< [0x080-0x09f] */ - uint32_t peripheralCfg; /*!< [0x0a0-0x0a3] */ - uint32_t ramSizeCfg; /*!< [0x0a4-0x0a7] */ - uint32_t flashSizeCfg; /*!< [0x0a8-0x0ab] */ - uint8_t reserved3[36]; /*!< [0x0ac-0x0cf] */ - uint8_t fro1mCfg; /*!< [0x0d0-0x0d0] */ - uint8_t reserved4[15]; /*!< [0x0d1-0x0df] */ - uint32_t dcdc[4]; /*!< [0x0e0-0x0ef] */ - uint32_t bod; /*!< [0x0f0-0x0f3] */ - uint8_t reserved5[12]; /*!< [0x0f4-0x0ff] */ - uint8_t calcHashReserved[192]; /*!< [0x100-0x1bf] */ - uint8_t sha256[32]; /*!< [0x1c0-0x1df] */ - uint32_t ecidBackup[4]; /*!< [0x1e0-0x1ef] */ - uint32_t pageChecksum[4]; /*!< [0x1f0-0x1ff] */ -} nmpa_cfg_info_t; - -typedef struct _ffr_key_store -{ - uint8_t reserved[3][FLASH_FFR_MAX_PAGE_SIZE]; -} ffr_key_store_t; - -typedef enum _ffr_key_type -{ - kFFR_KeyTypeSbkek = 0x00U, - kFFR_KeyTypeUser = 0x01U, - kFFR_KeyTypeUds = 0x02U, - kFFR_KeyTypePrinceRegion0 = 0x03U, - kFFR_KeyTypePrinceRegion1 = 0x04U, - kFFR_KeyTypePrinceRegion2 = 0x05U, -} ffr_key_type_t; - -typedef enum _ffr_bank_type -{ - kFFR_BankTypeBank0_NMPA = 0x00U, - kFFR_BankTypeBank1_CMPA = 0x01U, - kFFR_BankTypeBank2_CFPA = 0x02U -} ffr_bank_type_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name FFR APIs - * @{ - */ - -/*! - * @brief Initializes the global FFR properties structure members. - * - * @param config A pointer to the storage for the driver runtime state. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - */ -status_t FFR_Init(flash_config_t *config); - -/*! - * @brief Enable firewall for all flash banks. - * - * CFPA, CMPA, and NMPA flash areas region will be locked, After this function executed; - * Unless the board is reset again. - * - * @param config A pointer to the storage for the driver runtime state. - * - * @retval #kStatus_FLASH_Success An invalid argument is provided. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - */ -status_t FFR_Lock_All(flash_config_t *config); - -/*! - * @brief APIs to access CFPA pages - * - * This routine will erase CFPA and program the CFPA page with passed data. - * - * @param config A pointer to the storage for the driver runtime state. - * @param page_data A pointer to the source buffer of data that is to be programmed - * into the CFPA. - * @param valid_len The length, given in bytes, to be programmed. - * - * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CFPA. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_FfrBankIsLocked The CFPA was locked. - * @retval #kStatus_FLASH_OutOfDateCfpaPage It is not newest CFPA page. - */ -status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); - -/*! - * @brief APIs to access CFPA pages - * - * Generic read function, used by customer to read data stored in 'Customer In-field Page'. - * - * @param config A pointer to the storage for the driver runtime state. - * @param pData A pointer to the dest buffer of data that is to be read from 'Customer In-field Page'. - * @param offset An offset from the 'Customer In-field Page' start address. - * @param len The length, given in bytes, to be read. - * - * @retval #kStatus_FLASH_Success Get data from 'Customer In-field Page'. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_CommandFailure access error. - */ -status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - -/*! - * @brief APIs to access CMPA pages - * - * This routine will erase "customer factory page" and program the page with passed data. - * If 'seal_part' parameter is TRUE then the routine will compute SHA256 hash of - * the page contents and then programs the pages. - * 1.During development customer code uses this API with 'seal_part' set to FALSE. - * 2.During manufacturing this parameter should be set to TRUE to seal the part - * from further modifications - * 3.This routine checks if the page is sealed or not. A page is said to be sealed if - * the SHA256 value in the page has non-zero value. On boot ROM locks the firewall for - * the region if hash is programmed anyways. So, write/erase commands will fail eventually. - * - * @param config A pointer to the storage for the driver runtime state. - * @param page_data A pointer to the source buffer of data that is to be programmed - * into the "customer factory page". - * @param seal_part Set fasle for During development customer code. - * - * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CMPA. - * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. - * @retval kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_CommandFailure access error. - */ -status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part); - -/*! - * @brief APIs to access CMPA page - * - * Read data stored in 'Customer Factory CFG Page'. - * - * @param config A pointer to the storage for the driver runtime state. - * @param pData A pointer to the dest buffer of data that is to be read - * from the Customer Factory CFG Page. - * @param offset Address offset relative to the CMPA area. - * @param len The length, given in bytes to be read. - * - * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. - * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. - * @retval kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_CommandFailure access error. - */ -status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - -/*! - * @brief APIs to access CMPA page - * - * 1.SW should use this API routine to get the UUID of the chip. - * 2.Calling routine should pass a pointer to buffer which can hold 128-bit value. - */ -status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid); - -/*! - * @brief This routine writes the 3 pages allocated for Key store data, - * - * 1.Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state. - * 2.Optional routines to set individual data members (activation code, key codes etc) to construct - * the key store structure in RAM before committing it to IFR/FFR. - * - * @param config A pointer to the storage for the driver runtime state. - * @param pKeyStore A Pointer to the 3 pages allocated for Key store data. - * that will be written to 'customer factory page'. - * - * @retval #kStatus_FLASH_Success The key were programed successfully into FFR. - * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. - * @retval kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_CommandFailure access error. - */ -status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore); - -/*! - * @brief Get/Read Key store code routines - * - * 1. Calling code should pass buffer pointer which can hold activation code 1192 bytes. - * 2. Check if flash aperture is small or regular and read the data appropriately. - */ -status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode); - -/*! - * @brief Get/Read Key store code routines - * - * 1. Calling code should pass buffer pointer which can hold key code 52 bytes. - * 2. Check if flash aperture is small or regular and read the data appropriately. - * 3. keyIndex specifies which key code is read. - */ -status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); - -/*@}*/ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /*! __FSL_FLASH_FFR_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_iap_kbp.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_iap_kbp.h deleted file mode 100644 index 453a89a8fde..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_iap_kbp.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * Copyright (c) 2020-2021, Freescale Semiconductor, Inc. - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_IAP_KBP_H_ -#define _FSL_IAP_KBP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup kb_driver - * @{ - */ -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @brief ROM API status group number */ -#define kStatusGroup_RomApi (108U) - -/*! @brief ROM API status codes. */ -enum -{ - kStatus_RomApiExecuteCompleted = kStatus_Success, /*!< ROM successfully process the whole sb file/boot image.*/ - kStatus_RomApiNeedMoreData = - MAKE_STATUS(kStatusGroup_RomApi, 1), /*!< ROM needs more data to continue processing the boot image.*/ - kStatus_RomApiBufferSizeNotEnough = - MAKE_STATUS(kStatusGroup_RomApi, - 2), /*!< The user buffer is not enough for use by Kboot during execution of the operation.*/ - kStatus_RomApiInvalidBuffer = - MAKE_STATUS(kStatusGroup_RomApi, 3), /*!< The user buffer is not ok for sbloader or authentication.*/ -}; - -/*! - * @brief Details of the operation to be performed by the ROM. - * - * The #kRomAuthenticateImage operation requires the entire signed image to be - * available to the application. - */ -typedef enum _kb_operation -{ - kRomAuthenticateImage = 1, /*!< Authenticate a signed image.*/ - kRomLoadImage = 2, /*!< Load SB file.*/ - kRomOperationCount = 3, -} kb_operation_t; - -/*! - * @brief Security constraint flags, Security profile flags. - */ -enum _kb_security_profile -{ - kKbootMinRSA4096 = (1 << 16), -}; - -/*! - * @brief Memory region definition. - */ -typedef struct _kb_region -{ - uint32_t address; - uint32_t length; -} kb_region_t; - -/*! - * @brief User-provided options passed into kb_init(). - * - * The buffer field is a pointer to memory provided by the caller for use by - * Kboot during execution of the operation. Minimum size is the size of each - * certificate in the chain plus 432 bytes additional per certificate. - * - * The profile field is a mask that specifies which features are required in - * the SB file or image being processed. This includes the minimum AES and RSA - * key sizes. See the _kb_security_profile enum for profile mask constants. - * The image being loaded or authenticated must match the profile or an error will - * be returned. - * - * minBuildNumber is an optional field that can be used to prevent version - * rollback. The API will check the build number of the image, and if it is less - * than minBuildNumber will fail with an error. - * - * maxImageLength is used to verify the offsetToCertificateBlockHeaderInBytes - * value at the beginning of a signed image. It should be set to the length of - * the SB file. If verifying an image in flash, it can be set to the internal - * flash size or a large number like 0x10000000. - * - * userRHK can optionally be used by the user to override the RHK in IFR. If - * userRHK is not NULL, it points to a 32-byte array containing the SHA-256 of - * the root certificate's RSA public key. - * - * The regions field points to an array of memory regions that the SB file being - * loaded is allowed to access. If regions is NULL, then all memory is - * accessible by the SB file. This feature is required to prevent a malicious - * image from erasing good code or RAM contents while it is being loaded, only - * for us to find that the image is inauthentic when we hit the end of the - * section. - * - * overrideSBBootSectionID lets the caller override the default section of the - * SB file that is processed during a kKbootLoadSB operation. By default, - * the section specified in the firstBootableSectionID field of the SB header - * is loaded. If overrideSBBootSectionID is non-zero, then the section with - * the given ID will be loaded instead. - * - * The userSBKEK field lets a user provide their own AES-256 key for unwrapping - * keys in an SB file during the kKbootLoadSB operation. userSBKEK should point - * to a 32-byte AES-256 key. If userSBKEK is NULL then the IFR SBKEK will be used. - * After kb_init() returns, the caller should zero out the data pointed to by - * userSBKEK, as the API will have installed the key in the CAU3. - */ - -typedef struct _kb_load_sb -{ - uint32_t profile; - uint32_t minBuildNumber; - uint32_t overrideSBBootSectionID; - uint32_t *userSBKEK; - uint32_t regionCount; - const kb_region_t *regions; -} kb_load_sb_t; - -typedef struct _kb_authenticate -{ - uint32_t profile; - uint32_t minBuildNumber; - uint32_t maxImageLength; - uint32_t *userRHK; -} kb_authenticate_t; - -typedef struct _kb_options -{ - uint32_t version; /*!< Should be set to kKbootApiVersion.*/ - uint8_t *buffer; /*!< Caller-provided buffer used by Kboot.*/ - uint32_t bufferLength; - kb_operation_t op; - union - { - kb_authenticate_t authenticate; /*! Settings for kKbootAuthenticate operation.*/ - kb_load_sb_t loadSB; /*! Settings for kKbootLoadSB operation.*/ - }; -} kb_options_t; - -/*! - * @brief Interface to memory operations for one region of memory. - */ -typedef struct _memory_region_interface -{ - status_t (*init)(void); - status_t (*read)(uint32_t address, uint32_t length, uint8_t *buffer); - status_t (*write)(uint32_t address, uint32_t length, const uint8_t *buffer); - status_t (*fill)(uint32_t address, uint32_t length, uint32_t pattern); - status_t (*flush)(void); - status_t (*erase)(uint32_t address, uint32_t length); - status_t (*config)(uint32_t *buffer); - status_t (*erase_all)(void); -} memory_region_interface_t; - -/*! - * @brief Structure of a memory map entry. - */ -typedef struct _memory_map_entry -{ - uint32_t startAddress; - uint32_t endAddress; - uint32_t memoryProperty; - uint32_t memoryId; - const memory_region_interface_t *memoryInterface; -} memory_map_entry_t; - -typedef struct _kb_opaque_session_ref -{ - kb_options_t context; - bool cau3Initialized; - memory_map_entry_t *memoryMap; -} kb_session_ref_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize ROM API for a given operation. - * - * Inits the ROM API based on the options provided by the application in the second - * argument. Every call to rom_init() should be paired with a call to rom_deinit(). - * - * @retval #kStatus_Success API was executed successfully. - * @retval #kStatus_InvalidArgument An invalid argument is provided. - * @retval #kStatus_RomApiBufferSizeNotEnough The user buffer is not enough for use by Kboot during execution of the - * operation. - * @retval #kStatus_RomApiInvalidBuffer The user buffer is not ok for sbloader or authentication. - * @retval #kStatus_SKBOOT_Fail Return the failed status of secure boot. - * @retval #kStatus_SKBOOT_KeyStoreMarkerInvalid The key code for the particular PRINCE region is not present in the - * keystore - * @retval #kStatus_SKBOOT_Success Return the successful status of secure boot. - */ -status_t kb_init(kb_session_ref_t **session, const kb_options_t *options); - -/*! - * @brief Cleans up the ROM API context. - * - * After this call, the context parameter can be reused for another operation - * by calling rom_init() again. - * - * @retval #kStatus_Success API was executed successfully - */ -status_t kb_deinit(kb_session_ref_t *session); - -/*! - * Perform the operation configured during init. - * - * This application must call this API repeatedly, passing in sequential chunks of - * data from the boot image (SB file) that is to be processed. The ROM will perform - * the selected operation on this data and return. The application may call this - * function with as much or as little data as it wishes, which can be used to select - * the granularity of time given to the application in between executing the operation. - * - * @param session Current ROM context pointer. - * @param data Buffer of boot image data provided to the ROM by the application. - * @param dataLength Length in bytes of the data in the buffer provided to the ROM. - * - * @retval #kStatus_Success ROM successfully process the part of sb file/boot image. - * @retval #kStatus_RomApiExecuteCompleted ROM successfully process the whole sb file/boot image. - * @retval #kStatus_Fail An error occurred while executing the operation. - * @retval #kStatus_RomApiNeedMoreData No error occurred, but the ROM needs more data to - * continue processing the boot image. - * @retval #kStatus_RomApiBufferSizeNotEnough user buffer is not enough for - * use by Kboot during execution of the operation. - */ -status_t kb_execute(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength); - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_IAP_KBP_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_iap_skboot_authenticate.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_iap_skboot_authenticate.h deleted file mode 100644 index 67a513bc3cf..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_iap_skboot_authenticate.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _FSL_IAP_SKBOOT_AUTHENTICATE_H_ -#define _FSL_IAP_SKBOOT_AUTHENTICATE_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup skboot_authenticate - * @{ - */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @brief SKBOOT return status*/ -typedef enum _skboot_status -{ - kStatus_SKBOOT_Success = 0x5ac3c35au, /*!< SKBOOT return success status.*/ - kStatus_SKBOOT_Fail = 0xc35ac35au, /*!< SKBOOT return fail status.*/ - kStatus_SKBOOT_InvalidArgument = 0xc35a5ac3u, /*!< SKBOOT return invalid argument status.*/ - kStatus_SKBOOT_KeyStoreMarkerInvalid = 0xc3c35a5au, /*!< SKBOOT return Keystore invalid Marker status.*/ - kStatus_SKBOOT_HashcryptFinishedWithStatusSuccess = - 0xc15a5ac3, /*!< SKBOOT return Hashcrypt finished with the success status.*/ - kStatus_SKBOOT_HashcryptFinishedWithStatusFail = - 0xc15a5acb, /*!< SKBOOT return Hashcrypt finished with the fail status.*/ -} skboot_status_t; - -/*! @brief Secure bool flag*/ -typedef enum _secure_bool -{ - kSECURE_TRUE = 0xc33cc33cU, /*!< Secure true flag.*/ - kSECURE_FALSE = 0x5aa55aa5U, /*!< Secure false flag.*/ - kSECURE_CALLPROTECT_SECURITY_FLAGS = 0xc33c5aa5U, /*!< Secure call protect the security flag.*/ - kSECURE_CALLPROTECT_IS_APP_READY = 0x5aa5c33cU, /*!< Secure call protect the app is ready flag.*/ - kSECURE_TRACKER_VERIFIED = 0x55aacc33U, /*!< Secure tracker verified flag.*/ -} secure_bool_t; - -/******************************************************************************* - * Externs - ******************************************************************************/ - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Authenticate entry function with ARENA allocator init - * - * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface - */ -skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified); - -/*! - * @brief Interface for image authentication API - */ -void HASH_IRQHandler(void); - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_IAP_SKBOOT_AUTHENTICATE_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_inputmux.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_inputmux.c deleted file mode 100644 index 5ef935985fb..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_inputmux.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_inputmux.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.inputmux" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Initialize INPUTMUX peripheral. - - * This function enables the INPUTMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * - * retval None. - */ -void INPUTMUX_Init(INPUTMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE - CLOCK_EnableClock(kCLOCK_Sct); - CLOCK_EnableClock(kCLOCK_Dma); -#else - CLOCK_EnableClock(kCLOCK_InputMux); -#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Attaches a signal - * - * This function gates the INPUTPMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * param index Destination peripheral to attach the signal to. - * param connection Selects connection. - * - * retval None. - */ -void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection) -{ - uint32_t pmux_id; - uint32_t output_id; - - /* extract pmux to be used */ - pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT; - /* extract function number */ - output_id = ((uint32_t)(connection)) & ((1UL << PMUX_SHIFT) - 1U); - /* programm signal */ - *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4U)) = output_id; -} - -#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) -/*! - * brief Enable/disable a signal - * - * This function gates the INPUTPMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * param signal Enable signal register id and bit offset. - * param enable Selects enable or disable. - * - * retval None. - */ -void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable) -{ - uint32_t ena_id; - uint32_t ena_id_mask = (1UL << (32U - ENA_SHIFT)) - 1U; - uint32_t bit_offset; - -#if defined(FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX) && FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX - uint32_t chmux_offset; - uint32_t chmux_value; - - /* Only enable need to update channel mux */ - if (enable && ((((uint32_t)signal) & (1UL << CHMUX_AVL_SHIFT)) != 0U)) - { - chmux_offset = (((uint32_t)signal) >> CHMUX_OFF_SHIFT) & ((1UL << (CHMUX_AVL_SHIFT - CHMUX_OFF_SHIFT)) - 1UL); - chmux_value = (((uint32_t)signal) >> CHMUX_VAL_SHIFT) & ((1UL << (CHMUX_OFF_SHIFT - CHMUX_VAL_SHIFT)) - 1UL); - *(volatile uint32_t *)(((uint32_t)base) + chmux_offset) = chmux_value; - } - ena_id_mask = (1UL << (CHMUX_VAL_SHIFT - ENA_SHIFT)) - 1U; -#endif - /* extract enable register to be used */ - ena_id = (((uint32_t)signal) >> ENA_SHIFT) & ena_id_mask; - /* extract enable bit offset */ - bit_offset = ((uint32_t)signal) & ((1UL << ENA_SHIFT) - 1U); - /* set signal */ - if (enable) - { - *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1UL << bit_offset); - } - else - { - *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1UL << bit_offset); - } -} -#endif - -/*! - * brief Deinitialize INPUTMUX peripheral. - - * This function disables the INPUTMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * - * retval None. - */ -void INPUTMUX_Deinit(INPUTMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE - CLOCK_DisableClock(kCLOCK_Sct); - CLOCK_DisableClock(kCLOCK_Dma); -#else - CLOCK_DisableClock(kCLOCK_InputMux); -#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_inputmux.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_inputmux.h deleted file mode 100644 index ddb9e26c55f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_inputmux.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_INPUTMUX_H_ -#define _FSL_INPUTMUX_H_ - -#include "fsl_inputmux_connections.h" -#include "fsl_common.h" - -/*! - * @addtogroup inputmux_driver - * @{ - */ - -/*! @file */ -/*! @file fsl_inputmux_connections.h */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Group interrupt driver version for SDK */ -#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) -/*@}*/ - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @brief Initialize INPUTMUX peripheral. - - * This function enables the INPUTMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * - * @retval None. - */ -void INPUTMUX_Init(INPUTMUX_Type *base); - -/*! - * @brief Attaches a signal - * - * This function gates the INPUTPMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * @param index Destination peripheral to attach the signal to. - * @param connection Selects connection. - * - * @retval None. - */ -void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection); - -#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) -/*! - * @brief Enable/disable a signal - * - * This function gates the INPUTPMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * @param signal Enable signal register id and bit offset. - * @param enable Selects enable or disable. - * - * @retval None. - */ -void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable); -#endif - -/*! - * @brief Deinitialize INPUTMUX peripheral. - - * This function disables the INPUTMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * - * @retval None. - */ -void INPUTMUX_Deinit(INPUTMUX_Type *base); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_INPUTMUX_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_inputmux_connections.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_inputmux_connections.h deleted file mode 100644 index 6031941dcaa..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_inputmux_connections.h +++ /dev/null @@ -1,496 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_INPUTMUX_CONNECTIONS_ -#define _FSL_INPUTMUX_CONNECTIONS_ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" -#endif - -/*! - * @addtogroup inputmux_driver - * @{ - */ - -/*! - * @name Input multiplexing connections - * @{ - */ - -/*! @brief Periphinmux IDs */ -#define SCT0_INMUX0 0x00U -#define TIMER0CAPTSEL0 0x20U -#define TIMER1CAPTSEL0 0x40U -#define TIMER2CAPTSEL0 0x60U -#define PINTSEL_PMUX_ID 0xC0U -#define PINTSEL0 0xC0U -#define DMA0_ITRIG_INMUX0 0xE0U -#define DMA0_OTRIG_INMUX0 0x160U -#define FREQMEAS_REF_REG 0x180U -#define FREQMEAS_TARGET_REG 0x184U -#define TIMER3CAPTSEL0 0x1A0U -#define TIMER4CAPTSEL0 0x1C0U -#define PINTSECSEL0 0x1E0U -#define DMA1_ITRIG_INMUX0 0x200U -#define DMA1_OTRIG_INMUX0 0x240U -#define DMA0_REQ_ENA_ID 0x740U -#define DMA1_REQ_ENA_ID 0x760U -#define DMA0_ITRIG_ENA_ID 0x780U -#define DMA1_ITRIG_ENA_ID 0x7A0U -#define ENA_SHIFT 8U -#define PMUX_SHIFT 20U - -/*! @brief INPUTMUX connections type */ -typedef enum _inputmux_connection_t -{ - /*!< SCT0 INMUX. */ - kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToSct0 = 8U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToSct0 = 9U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToSct0 = 10U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToSct0 = 11U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToSct0 = 12U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_AdcIrqToSct0 = 13U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToSct0 = 14U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToSct0 = 16U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_CompOutToSct0 = 17U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedSck0ToSct0 = 18U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedSck1ToSct0 = 19U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToSct0 = 20U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToSct0 = 21U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_ArmTxevToSct0 = 22U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_DebugHaltedToSct0 = 23U + (SCT0_INMUX0 << PMUX_SHIFT), - - /*!< TIMER0 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer0Captsel = 0U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer0Captsel = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer0Captsel = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer0Captsel = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToTimer0Captsel = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - - /*!< TIMER1 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer1Captsel = 0U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer1Captsel = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer1Captsel = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer1Captsel = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToTimer1Captsel = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - - /*!< TIMER2 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer2Captsel = 0U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer2Captsel = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer2Captsel = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer2Captsel = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToTimer2Captsel = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - - /*!< Pin interrupt select. */ - kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL0 << PMUX_SHIFT), - - /*!< DMA0 Input trigger. */ - kINPUTMUX_PinInt0ToDma0 = 0U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt1ToDma0 = 1U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt2ToDma0 = 2U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt3ToDma0 = 3U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToDma0 = 4U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M1ToDma0 = 5U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToDma0 = 6U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M1ToDma0 = 7U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToDma0 = 8U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M1ToDma0 = 9U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToDma0 = 10U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M1ToDma0 = 11U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToDma0 = 12U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M1ToDma0 = 13U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_CompOutToDma0 = 14U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig0ToDma0 = 15U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig1ToDma0 = 16U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig2ToDma0 = 17U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig3ToDma0 = 18U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq0ToDma0 = 19U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq1ToDma0 = 20U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_HashDmaRxToDma0 = 21U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - - /*!< DMA0 output trigger. */ - kINPUTMUX_Dma0Hash0TxTrigoutToTriginChannels = 0U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0HsLspiRxTrigoutToTriginChannels = 2U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0HsLspiTxTrigoutToTriginChannels = 3U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm3RxTrigoutToTriginChannels = 8U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm3TxTrigoutToTriginChannels = 9U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm2RxTrigoutToTriginChannels = 10U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm2TxTrigoutToTriginChannels = 11U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm4RxTrigoutToTriginChannels = 12U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm4TxTrigoutToTriginChannels = 13U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm5RxTrigoutToTriginChannels = 14U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm5TxTrigoutToTriginChannels = 15U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm6RxTrigoutToTriginChannels = 16U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm6TxTrigoutToTriginChannels = 17U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm7RxTrigoutToTriginChannels = 18U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm7TxTrigoutToTriginChannels = 19U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Adc0Ch0TrigoutToTriginChannels = 21U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Adc0Ch1TrigoutToTriginChannels = 22U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - - /*!< Selection for frequency measurement reference clock. */ - kINPUTMUX_ExternOscToFreqmeasRef = 0U + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_Fro12MhzToFreqmeasRef = 1u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_Fro96MhzToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_WdtOscToFreqmeasRef = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_32KhzOscToFreqmeasRef = 4u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_MainClkToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_aRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_bRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT), - - /*!< Selection for frequency measurement target clock. */ - kINPUTMUX_ExternOscToFreqmeasTarget = 0U + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_Fro12MhzToFreqmeasTarget = 1u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_Fro96MhzToFreqmeasTarget = 2u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_WdtOscToFreqmeasTarget = 3u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_32KhzOscToFreqmeasTarget = 4u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_MainClkToFreqmeasTarget = 5u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_aTarget = 6u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_bTarget = 7u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - - /*!< TIMER3 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer3Captsel = 0U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer3Captsel = 17U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer3Captsel = 18U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer3Captsel = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToTimer3Captsel = 21U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - - /*!< Timer4 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer4Captsel = 0U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer4Captsel = 17U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer4Captsel = 18U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer4Captsel = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToTimer4Captsel = 21U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - - /*Pin interrupt secure select */ - kINPUTMUX_GpioPort0Pin0ToPintSecsel = 0U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin1ToPintSecsel = 1U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin2ToPintSecsel = 2U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin3ToPintSecsel = 3U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin4ToPintSecsel = 4U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin5ToPintSecsel = 5U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin6ToPintSecsel = 6U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin7ToPintSecsel = 7U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin8ToPintSecsel = 8U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin9ToPintSecsel = 9U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin10ToPintSecsel = 10U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin11ToPintSecsel = 11U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin12ToPintSecsel = 12U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin13ToPintSecsel = 13U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin14ToPintSecsel = 14U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin15ToPintSecsel = 15U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin16ToPintSecsel = 16U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin17ToPintSecsel = 17U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin18ToPintSecsel = 18U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin19ToPintSecsel = 19U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin20ToPintSecsel = 20U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin21ToPintSecsel = 21U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin22ToPintSecsel = 22U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin23ToPintSecsel = 23U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin24ToPintSecsel = 24U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin25ToPintSecsel = 25U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin26ToPintSecsel = 26U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin27ToPintSecsel = 27U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin28ToPintSecsel = 28U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin29ToPintSecsel = 29U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin30ToPintSecsel = 30U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin31ToPintSecsel = 31U + (PINTSECSEL0 << PMUX_SHIFT), - - /*!< DMA1 Input trigger. */ - kINPUTMUX_PinInt0ToDma1 = 0U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt1ToDma1 = 1U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt2ToDma1 = 2U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt3ToDma1 = 3U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToDma1 = 4U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M1ToDma1 = 5U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToDma1 = 6U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToDma1 = 7U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig0ToDma1 = 8U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig1ToDma1 = 9U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig2ToDma1 = 10U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig3ToDma1 = 11U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq0ToDma1 = 12U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq1ToDma1 = 13U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_HashDmaRxToDma1 = 14U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - - /*!< DMA1 output trigger. */ - kINPUTMUX_Dma1Hash0TxTrigoutToTriginChannels = 0U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1HsLspiRxTrigoutToTriginChannels = 2U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1HsLspiTxTrigoutToTriginChannels = 3U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm3RxTrigoutToTriginChannels = 8U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm3TxTrigoutToTriginChannels = 9U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), -} inputmux_connection_t; - -/*! @brief INPUTMUX signal enable/disable type */ -typedef enum _inputmux_signal_t -{ - /*!< DMA0 REQ signal. */ - kINPUTMUX_HashCryptToDmac0Ch0RequestEna = 0U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm8RxToDmac0Ch2RequestEna = 2U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm8TxToDmac0Ch3RequestEna = 3U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm0RxToDmac0Ch4RequestEna = 4U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm0TxToDmac0Ch5RequestEna = 5U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm1RxToDmac0Ch6RequestEna = 6U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm1TxToDmac0Ch7RequestEna = 7U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm3RxToDmac0Ch8RequestEna = 8U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm3TxToDmac0Ch9RequestEna = 9U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm2RxToDmac0Ch10RequestEna = 10U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm2TxToDmac0Ch11RequestEna = 11U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm4RxToDmac0Ch12RequestEna = 12U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm4TxToDmac0Ch13RequestEna = 13U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm5RxToDmac0Ch14RequestEna = 14U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm5TxToDmac0Ch15RequestEna = 15U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm6RxToDmac0Ch16RequestEna = 16U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm6TxToDmac0Ch17RequestEna = 17U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm7RxToDmac0Ch18RequestEna = 18U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm7TxToDmac0Ch19RequestEna = 19U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Adc0FIFO0ToDmac0Ch21RequestEna = 21U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Adc0FIFO1ToDmac0Ch22RequestEna = 22U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - - /*!< DMA1 REQ signal. */ - kINPUTMUX_HashCryptToDmac1Ch0RequestEna = 0U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm8RxToDmac1Ch2RequestEna = 2U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm8TxToDmac1Ch3RequestEna = 3U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm0RxToDmac1Ch4RequestEna = 4U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm0TxToDmac1Ch5RequestEna = 5U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm1RxToDmac1Ch6RequestEna = 6U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm1TxToDmac1Ch7RequestEna = 7U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm3RxToDmac1Ch8RequestEna = 8U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm3TxToDmac1Ch9RequestEna = 9U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - - /*!< DMA0 input trigger source enable. */ - kINPUTMUX_Dmac0InputTriggerPint0Ena = 0U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerPint1Ena = 1U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerPint2Ena = 2U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerPint3Ena = 3U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer0M0Ena = 4U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer0M1Ena = 5U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer1M0Ena = 6U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer1M1Ena = 7U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer2M0Ena = 8U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer2M1Ena = 9U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer3M0Ena = 10U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer3M1Ena = 11U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer4M0Ena = 12U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer4M1Ena = 13U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCompOutEna = 14U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerDma0Out0Ena = 15U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerDma0Out1Ena = 16U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerDma0Out2Ena = 17U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerDma0Out3Ena = 18U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerSctDmac0Ena = 19U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerSctDmac1Ena = 20U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerHashOutEna = 21U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - - /*!< DMA1 input trigger source enable. */ - kINPUTMUX_Dmac1InputTriggerPint0Ena = 0U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerPint1Ena = 1U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerPint2Ena = 2U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerPint3Ena = 3U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerCtimer0M0Ena = 4U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerCtimer0M1Ena = 5U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerCtimer2M0Ena = 6U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerCtimer4M0Ena = 7U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerDma1Out0Ena = 8U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerDma1Out1Ena = 9U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerDma1Out2Ena = 10U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerDma1Out3Ena = 11U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerSctDmac0Ena = 12U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerSctDmac1Ena = 13U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerHashOutEna = 14U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), -} inputmux_signal_t; - -/*@}*/ - -/*@}*/ - -#endif /* _FSL_INPUTMUX_CONNECTIONS_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_iocon.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_iocon.h deleted file mode 100644 index e705e91f66c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_iocon.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_IOCON_H_ -#define _FSL_IOCON_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_iocon - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon" -#endif - -/*! @name Driver version */ -/*@{*/ -/*! @brief IOCON driver version. */ -#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) -/*@}*/ - -/** - * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format - */ -typedef struct _iocon_group -{ - uint8_t port; /* Pin port */ - uint8_t pin; /* Pin number */ - uint8_t ionumber; /* IO number */ - uint16_t modefunc; /* Function and mode */ -} iocon_group_t; - -/** - * @brief IOCON function and mode selection definitions - * @note See the User Manual for specific modes and functions supported by the various pins. - */ -#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ -#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ -#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ -#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ -#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ -#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ -#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ -#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ -#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) -#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ -#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ -#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ -#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ -#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ -#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ -#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ -#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ -#endif /* FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH */ - -#if defined(IOCON_PIO_MODE_SHIFT) -#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ -#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ -#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ -#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ -#endif - -#if defined(IOCON_PIO_I2CSLEW_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_MODE (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ -#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */ -#endif - -#if defined(IOCON_PIO_EGP_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_MODE (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ -#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */ -#endif - -#if defined(IOCON_PIO_SLEW_SHIFT) -#define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ -#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ -#endif - -#if defined(IOCON_PIO_INVERT_SHIFT) -#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */ -#endif - -#if defined(IOCON_PIO_DIGIMODE_SHIFT) -#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */ -#define IOCON_DIGITAL_EN \ - (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */ -#endif - -#if defined(IOCON_PIO_FILTEROFF_SHIFT) -#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ -#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ -#endif - -#if defined(IOCON_PIO_I2CDRIVE_SHIFT) -#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ -#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ -#endif - -#if defined(IOCON_PIO_OD_SHIFT) -#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */ -#endif - -#if defined(IOCON_PIO_I2CFILTER_SHIFT) -#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ -#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */ -#endif - -#if defined(IOCON_PIO_ASW_SHIFT) -#define IOCON_AWS_EN (0x1 << IOCON_PIO_ASW_SHIFT) /*!< Enables analog switch function */ -#endif - -#if defined(IOCON_PIO_SSEL_SHIFT) -#define IOCON_SSEL_3V3 (0x0 << IOCON_PIO_SSEL_SHIFT) /*!< 3V3 signaling in I2C mode */ -#define IOCON_SSEL_1V8 (0x1 << IOCON_PIO_SSEL_SHIFT) /*!< 1V8 signaling in I2C mode */ -#endif - -#if defined(IOCON_PIO_ECS_SHIFT) -#define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */ -#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */ -#endif - -#if defined(IOCON_PIO_S_MODE_SHIFT) -#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ -#define IOCON_S_MODE_1CLK \ - (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_2CLK \ - (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_3CLK \ - (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ -#endif - -#if defined(IOCON_PIO_CLK_DIV_SHIFT) -#define IOCON_CLKDIV(div) \ - ((div) \ - << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ -#endif - -#if defined(__cplusplus) -extern "C" { -#endif - -#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) -/** - * @brief Sets I/O Control pin mux - * @param base : The base of IOCON peripheral on the chip - * @param ionumber : GPIO number to mux - * @param modefunc : OR'ed values of type IOCON_* - * @return Nothing - */ -__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc) -{ - base->PIO[ionumber] = modefunc; -} -#else -/** - * @brief Sets I/O Control pin mux - * @param base : The base of IOCON peripheral on the chip - * @param port : GPIO port to mux - * @param pin : GPIO pin to mux - * @param modefunc : OR'ed values of type IOCON_* - * @return Nothing - */ -__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc) -{ - base->PIO[port][pin] = modefunc; -} -#endif - -/** - * @brief Set all I/O Control pin muxing - * @param base : The base of IOCON peripheral on the chip - * @param pinArray : Pointer to array of pin mux selections - * @param arrayLength : Number of entries in pinArray - * @return Nothing - */ -__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength) -{ - uint32_t i; - - for (i = 0; i < arrayLength; i++) - { -#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) - IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc); -#else - IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc); -#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */ - } -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_IOCON_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_lpadc.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_lpadc.c deleted file mode 100644 index 7835e6fc454..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_lpadc.c +++ /dev/null @@ -1,612 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_lpadc.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpadc" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for LPADC module. - * - * @param base LPADC peripheral base address - */ -static uint32_t LPADC_GetInstance(ADC_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to LPADC bases for each instance. */ -static ADC_Type *const s_lpadcBases[] = ADC_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to LPADC clocks for each instance. */ -static const clock_ip_name_t s_lpadcClocks[] = LPADC_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t LPADC_GetInstance(ADC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_lpadcBases); instance++) - { - if (s_lpadcBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_lpadcBases)); - - return instance; -} - -/*! - * brief Initializes the LPADC module. - * - * param base LPADC peripheral base address. - * param config Pointer to configuration structure. See "lpadc_config_t". - */ -void LPADC_Init(ADC_Type *base, const lpadc_config_t *config) -{ - /* Check if the pointer is available. */ - assert(config != NULL); - - uint32_t tmp32 = 0U; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock for LPADC instance. */ - (void)CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the module. */ - LPADC_DoResetConfig(base); -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - LPADC_DoResetFIFO0(base); - LPADC_DoResetFIFO1(base); -#else - LPADC_DoResetFIFO(base); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - - /* Disable the module before setting configuration. */ - LPADC_Enable(base, false); - - /* Configure the module generally. */ - if (config->enableInDozeMode) - { - base->CTRL &= ~ADC_CTRL_DOZEN_MASK; - } - else - { - base->CTRL |= ADC_CTRL_DOZEN_MASK; - } - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS - /* Set calibration average mode. */ - base->CTRL |= ADC_CTRL_CAL_AVGS(config->conversionAverageMode); -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - -/* ADCx_CFG. */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - if (config->enableInternalClock) - { - tmp32 |= ADC_CFG_ADCKEN_MASK; - } -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - if (config->enableVref1LowVoltage) - { - tmp32 |= ADC_CFG_VREF1RNG_MASK; - } -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - if (config->enableAnalogPreliminary) - { - tmp32 |= ADC_CFG_PWREN_MASK; - } - tmp32 |= ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */ - | ADC_CFG_REFSEL(config->referenceVoltageSource) /* Reference voltage. */ - | ADC_CFG_PWRSEL(config->powerLevelMode) /* Power configuration. */ - | ADC_CFG_TPRICTRL(config->triggerPriorityPolicy); /* Trigger priority policy. */ - base->CFG = tmp32; - - /* ADCx_PAUSE. */ - if (config->enableConvPause) - { - base->PAUSE = ADC_PAUSE_PAUSEEN_MASK | ADC_PAUSE_PAUSEDLY(config->convPauseDelay); - } - else - { - base->PAUSE = 0U; - } - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - /* ADCx_FCTRL0. */ - base->FCTRL[0] = ADC_FCTRL_FWMARK(config->FIFO0Watermark); - /* ADCx_FCTRL1. */ - base->FCTRL[1] = ADC_FCTRL_FWMARK(config->FIFO1Watermark); -#else - /* ADCx_FCTRL. */ - base->FCTRL = ADC_FCTRL_FWMARK(config->FIFOWatermark); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - - /* Enable the module after setting configuration. */ - LPADC_Enable(base, true); -} - -/*! - * brief Gets an available pre-defined settings for initial configuration. - * - * This function initializes the converter configuration structure with an available settings. The default values are: - * code - * config->enableInDozeMode = true; - * config->conversionAverageMode = kLPADC_ConversionAverage1; - * config->enableAnalogPreliminary = false; - * config->powerUpDelay = 0x80; - * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - * config->powerLevelMode = kLPADC_PowerLevelAlt1; - * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; - * config->enableConvPause = false; - * config->convPauseDelay = 0U; - * config->FIFO0Watermark = 0U; - * config->FIFO1Watermark = 0U; - * config->FIFOWatermark = 0U; - * endcode - * param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConfig(lpadc_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - config->enableInternalClock = false; -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - config->enableVref1LowVoltage = false; -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - config->enableInDozeMode = true; -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS - /* Set calibration average mode. */ - config->conversionAverageMode = kLPADC_ConversionAverage1; -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - config->enableAnalogPreliminary = false; - config->powerUpDelay = 0x80; - config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - config->powerLevelMode = kLPADC_PowerLevelAlt1; - config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; - config->enableConvPause = false; - config->convPauseDelay = 0U; -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - config->FIFO0Watermark = 0U; - config->FIFO1Watermark = 0U; -#else - config->FIFOWatermark = 0U; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ -} - -/*! - * brief De-initializes the LPADC module. - * - * param base LPADC peripheral base address. - */ -void LPADC_Deinit(ADC_Type *base) -{ - /* Disable the module. */ - LPADC_Enable(base, false); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the clock. */ - (void)CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * brief Get the result in conversion FIFOn. - * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. - * param index Result FIFO index. - * - * return Status whether FIFOn entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index) -{ - assert(result != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - tmp32 = base->RESFIFO[index]; - - if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) - { - return false; /* FIFO is empty. Discard any read from RESFIFO. */ - } - - result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; - result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; - result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; - result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); - - return true; -} -#else -/*! - * brief Get the result in conversion FIFO. - * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFO. - * - * return Status whether FIFO entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result) -{ - assert(result != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - tmp32 = base->RESFIFO; - - if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) - { - return false; /* FIFO is empty. Discard any read from RESFIFO. */ - } - - result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; - result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; - result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; - result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); - - return true; -} -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * brief Configure the conversion trigger source. - * - * Each programmable trigger can launch the conversion command in command buffer. - * - * param base LPADC peripheral base address. - * param triggerId ID for each trigger. Typically, the available value range is from 0. - * param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. - */ -void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config) -{ - assert(triggerId < ADC_TCTRL_COUNT); /* Check if the triggerId is available in this device. */ - assert(config != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - tmp32 = ADC_TCTRL_TCMD(config->targetCommandId) /* Trigger command select. */ - | ADC_TCTRL_TDLY(config->delayPower) /* Trigger delay select. */ - | ADC_TCTRL_TPRI(config->priority) /* Trigger priority setting. */ -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - | ADC_TCTRL_FIFO_SEL_A(config->channelAFIFOSelect) -#if !(defined(FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) && FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) - | ADC_TCTRL_FIFO_SEL_B(config->channelBFIFOSelect) -#endif /* FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - ; - if (config->enableHardwareTrigger) - { - tmp32 |= ADC_TCTRL_HTEN_MASK; - } - - base->TCTRL[triggerId] = tmp32; -} - -/*! - * brief Gets an available pre-defined settings for trigger's configuration. - * - * This function initializes the trigger's configuration structure with an available settings. The default values are: - * code - * config->commandIdSource = 0U; - * config->loopCountIndex = 0U; - * config->triggerIdSource = 0U; - * config->enableHardwareTrigger = false; - * config->channelAFIFOSelect = 0U; - * config->channelBFIFOSelect = 0U; - * endcode - * param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config) -{ - assert(config != NULL); /* Check if the input pointer is available. */ - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->targetCommandId = 0U; - config->delayPower = 0U; - config->priority = 0U; -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - config->channelAFIFOSelect = 0U; - config->channelBFIFOSelect = 0U; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - config->enableHardwareTrigger = false; -} - -/*! - * brief Configure conversion command. - * - * param base LPADC peripheral base address. - * param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. - * param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. - */ -void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config) -{ - assert(commandId < (ADC_CMDL_COUNT + 1U)); /* Check if the commandId is available on this device. */ - assert(config != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32 = 0; - - commandId--; /* The available command number are 1-15, while the index of register group are 0-14. */ - - /* ADCx_CMDL. */ - tmp32 = ADC_CMDL_ADCH(config->channelNumber); /* Channel number. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - tmp32 |= ADC_CMDL_CSCALE(config->sampleScaleMode); /* Full/Part scale input voltage. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE - tmp32 |= ADC_CMDL_CTYPE(config->sampleChannelMode); -#else - switch (config->sampleChannelMode) /* Sample input. */ - { - case kLPADC_SampleChannelSingleEndSideB: - tmp32 |= ADC_CMDL_ABSEL_MASK; - break; -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF - case kLPADC_SampleChannelDiffBothSideAB: - tmp32 |= ADC_CMDL_DIFF_MASK; - break; - case kLPADC_SampleChannelDiffBothSideBA: - tmp32 |= ADC_CMDL_ABSEL_MASK | ADC_CMDL_DIFF_MASK; - break; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_DIFF */ - default: /* kLPADC_SampleChannelSingleEndSideA. */ - break; - } -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - tmp32 |= ADC_CMDL_MODE(config->conversionResolutionMode); -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ - base->CMD[commandId].CMDL = tmp32; - - /* ADCx_CMDH. */ - tmp32 = ADC_CMDH_NEXT(config->chainedNextCommandNumber) /* Next Command Select. */ - | ADC_CMDH_LOOP(config->loopCount) /* Loop Count Select. */ - | ADC_CMDH_AVGS(config->hardwareAverageMode) /* Hardware Average Select. */ - | ADC_CMDH_STS(config->sampleTimeMode) /* Sample Time Select. */ - | ADC_CMDH_CMPEN(config->hardwareCompareMode); /* Hardware compare enable. */ -#if (defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) - if (config->enableWaitTrigger) - { - tmp32 |= ADC_CMDH_WAIT_TRIG_MASK; /* Wait trigger enable. */ - } -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ - - if (config->enableAutoChannelIncrement) - { - tmp32 |= ADC_CMDH_LWI_MASK; - } - base->CMD[commandId].CMDH = tmp32; - - /* Hardware compare settings. - * Not all Command Buffers have an associated Compare Value register. The compare function is only available on - * Command Buffers that have a corresponding Compare Value register. - */ - if (kLPADC_HardwareCompareDisabled != config->hardwareCompareMode) - { - /* Check if the hardware compare feature is available for indicated command buffer. */ - assert(commandId < ADC_CV_COUNT); - - /* Set CV register. */ - base->CV[commandId] = ADC_CV_CVH(config->hardwareCompareValueHigh) /* Compare value high. */ - | ADC_CV_CVL(config->hardwareCompareValueLow); /* Compare value low. */ - } -} - -/*! - * brief Gets an available pre-defined settings for conversion command's configuration. - * - * This function initializes the conversion command's configuration structure with an available settings. The default - * values are: - * code - * config->sampleScaleMode = kLPADC_SampleFullScale; - * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; - * config->channelNumber = 0U; - * config->chainedNextCmdNumber = 0U; - * config->enableAutoChannelIncrement = false; - * config->loopCount = 0U; - * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - * config->sampleTimeMode = kLPADC_SampleTimeADCK3; - * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - * config->hardwareCompareValueHigh = 0U; - * config->hardwareCompareValueLow = 0U; - * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; - * config->enableWaitTrigger = false; - * endcode - * param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config) -{ - assert(config != NULL); /* Check if the input pointer is available. */ - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - config->sampleScaleMode = kLPADC_SampleFullScale; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ - config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; - config->channelNumber = 0U; - config->chainedNextCommandNumber = 0U; /* No next command defined. */ - config->enableAutoChannelIncrement = false; - config->loopCount = 0U; - config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - config->sampleTimeMode = kLPADC_SampleTimeADCK3; - config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - config->hardwareCompareValueHigh = 0U; /* No used. */ - config->hardwareCompareValueLow = 0U; /* No used. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG - config->enableWaitTrigger = false; -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ -} - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS -/*! - * brief Enable the calibration function. - * - * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes - * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value - * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- - * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the - * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. - * - * param base LPADC peripheral base address. - * param enable switcher to the calibration function. - */ -void LPADC_EnableCalibration(ADC_Type *base, bool enable) -{ - LPADC_Enable(base, false); - if (enable) - { - base->CFG |= ADC_CFG_CALOFS_MASK; - } - else - { - base->CFG &= ~ADC_CFG_CALOFS_MASK; - } - LPADC_Enable(base, true); -} - -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! - * brief Do auto calibration. - * - * Calibration function should be executed before using converter in application. It used the software trigger and a - * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API - * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) - * -LPADC_SetConvTriggerConfig(...) - * - * param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base) -{ - assert(0u == LPADC_GetConvResultCount(base)); - - uint32_t mLpadcCMDL; - uint32_t mLpadcCMDH; - uint32_t mLpadcTrigger; - lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct; - lpadc_conv_command_config_t mLpadcCommandConfigStruct; - lpadc_conv_result_t mLpadcResultConfigStruct; - - /* Enable the calibration function. */ - LPADC_EnableCalibration(base, true); - - /* Keep the CMD and TRG state here and restore it later if the calibration completes.*/ - mLpadcCMDL = base->CMD[0].CMDL; /* CMD1L. */ - mLpadcCMDH = base->CMD[0].CMDH; /* CMD1H. */ - mLpadcTrigger = base->TCTRL[0]; /* Trigger0. */ - - /* Set trigger0 configuration - for software trigger. */ - LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct); - mLpadcTriggerConfigStruct.targetCommandId = 1U; /* CMD1 is executed. */ - LPADC_SetConvTriggerConfig(base, 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */ - - /* Set conversion CMD configuration. */ - LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct); - mLpadcCommandConfigStruct.hardwareAverageMode = kLPADC_HardwareAverageCount128; - LPADC_SetConvCommandConfig(base, 1U, &mLpadcCommandConfigStruct); /* Set CMD1 configuration. */ - - /* Do calibration. */ - LPADC_DoSoftwareTrigger(base, 1U); /* 1U is trigger0 mask. */ - while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct)) - { - } - /* The valid bits of data are bits 14:3 in the RESFIFO register. */ - LPADC_SetOffsetValue(base, (uint32_t)(mLpadcResultConfigStruct.convValue) >> 3UL); - /* Disable the calibration function. */ - LPADC_EnableCalibration(base, false); - - /* restore CMD and TRG registers. */ - base->CMD[0].CMDL = mLpadcCMDL; /* CMD1L. */ - base->CMD[0].CMDH = mLpadcCMDH; /* CMD1H. */ - base->TCTRL[0] = mLpadcTrigger; /* Trigger0. */ -} -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS -/*! - * brief Do offset calibration. - * - * param base LPADC peripheral base address. - */ -void LPADC_DoOffsetCalibration(ADC_Type *base) -{ - LPADC_EnableOffsetCalibration(base, true); - while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) - { - } -} - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ -/*! - * brief Do auto calibration. - * - * param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base) -{ - assert((0u == LPADC_GetConvResultCount(base, 0)) && (0u == LPADC_GetConvResultCount(base, 1))); - - uint32_t GCCa; - uint32_t GCCb; - uint32_t GCRa; - uint32_t GCRb; - - /* Request gain calibration. */ - base->CTRL |= ADC_CTRL_CAL_REQ_MASK; - while ((ADC_GCC_RDY_MASK != (base->GCC[0] & ADC_GCC_RDY_MASK)) || - (ADC_GCC_RDY_MASK != (base->GCC[1] & ADC_GCC_RDY_MASK))) - { - } - - /* Calculate gain offset. */ - GCCa = (base->GCC[0] & ADC_GCC_GAIN_CAL_MASK); - GCCb = (base->GCC[1] & ADC_GCC_GAIN_CAL_MASK); - GCRa = (uint16_t)((GCCa << 16U) / - (0x1FFFFU - GCCa)); /* Gain_CalA = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[0])) - 1. */ - GCRb = (uint16_t)((GCCb << 16U) / - (0x1FFFFU - GCCb)); /* Gain_CalB = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[1])) - 1. */ - base->GCR[0] = ADC_GCR_GCALR(GCRa); - base->GCR[1] = ADC_GCR_GCALR(GCRb); - - /* Indicate the values are valid. */ - base->GCR[0] |= ADC_GCR_RDY_MASK; - base->GCR[1] |= ADC_GCR_RDY_MASK; - - while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) - { - } -} -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_lpadc.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_lpadc.h deleted file mode 100644 index d3e5a9ec30a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_lpadc.h +++ /dev/null @@ -1,964 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_LPADC_H_ -#define _FSL_LPADC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpadc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPADC driver version 2.5.1. */ -#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 5, 1)) -/*@}*/ - -/*! - * @brief Define the MACRO function to get command status from status value. - * - * The statusVal is the return value from LPADC_GetStatusFlags(). - */ -#define LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal) ((statusVal & ADC_STAT_CMDACT_MASK) >> ADC_STAT_CMDACT_SHIFT) - -/*! - * @brief Define the MACRO function to get trigger status from status value. - * - * The statusVal is the return value from LPADC_GetStatusFlags(). - */ -#define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT) - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Define hardware flags of the module. - */ -enum _lpadc_status_flags -{ - kLPADC_ResultFIFO0OverflowFlag = ADC_STAT_FOF0_MASK, /*!< Indicates that more data has been written to the Result - FIFO 0 than it can hold. */ - kLPADC_ResultFIFO0ReadyFlag = ADC_STAT_RDY0_MASK, /*!< Indicates when the number of valid datawords in the result - FIFO 0 is greater than the setting watermark level. */ - kLPADC_ResultFIFO1OverflowFlag = ADC_STAT_FOF1_MASK, /*!< Indicates that more data has been written to the Result - FIFO 1 than it can hold. */ - kLPADC_ResultFIFO1ReadyFlag = ADC_STAT_RDY1_MASK, /*!< Indicates when the number of valid datawords in the result - FIFO 1 is greater than the setting watermark level. */ -}; - -/*! - * @brief Define interrupt switchers of the module. - */ -enum _lpadc_interrupt_enable -{ - kLPADC_ResultFIFO0OverflowInterruptEnable = ADC_IE_FOFIE0_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF0 flag is asserted. */ - kLPADC_FIFO0WatermarkInterruptEnable = ADC_IE_FWMIE0_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY0 flag is asserted. */ - kLPADC_ResultFIFO1OverflowInterruptEnable = ADC_IE_FOFIE1_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF1 flag is asserted. */ - kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY1 flag is asserted. */ -#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) - kLPADC_TriggerExceptionInterruptEnable = ADC_IE_TEXC_IE_MASK, /*!< Configures ADC to generate trigger exception - interrupt. */ - kLPADC_Trigger0CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 0UL), /*!< Configures ADC to generate interrupt - when trigger 0 completion. */ - kLPADC_Trigger1CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 1UL), /*!< Configures ADC to generate interrupt - when trigger 1 completion. */ - kLPADC_Trigger2CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 2UL), /*!< Configures ADC to generate interrupt - when trigger 2 completion. */ - kLPADC_Trigger3CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 3UL), /*!< Configures ADC to generate interrupt - when trigger 3 completion. */ - kLPADC_Trigger4CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 4UL), /*!< Configures ADC to generate interrupt - when trigger 4 completion. */ - kLPADC_Trigger5CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 5UL), /*!< Configures ADC to generate interrupt - when trigger 5 completion. */ - kLPADC_Trigger6CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 6UL), /*!< Configures ADC to generate interrupt - when trigger 6 completion. */ - kLPADC_Trigger7CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 7UL), /*!< Configures ADC to generate interrupt - when trigger 7 completion. */ - kLPADC_Trigger8CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 8UL), /*!< Configures ADC to generate interrupt - when trigger 8 completion. */ - kLPADC_Trigger9CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 9UL), /*!< Configures ADC to generate interrupt - when trigger 9 completion. */ - kLPADC_Trigger10CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 10UL), /*!< Configures ADC to generate interrupt - when trigger 10 completion. */ - kLPADC_Trigger11CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 11UL), /*!< Configures ADC to generate interrupt - when trigger 11 completion. */ - kLPADC_Trigger12CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 12UL), /*!< Configures ADC to generate interrupt - when trigger 12 completion. */ - kLPADC_Trigger13CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 13UL), /*!< Configures ADC to generate interrupt - when trigger 13 completion. */ - kLPADC_Trigger14CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 14UL), /*!< Configures ADC to generate interrupt - when trigger 14 completion. */ - kLPADC_Trigger15CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 15UL), /*!< Configures ADC to generate interrupt - when trigger 15 completion. */ -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ -}; -#else -/*! - * @brief Define hardware flags of the module. - */ -enum _lpadc_status_flags -{ - kLPADC_ResultFIFOOverflowFlag = ADC_STAT_FOF_MASK, /*!< Indicates that more data has been written to the Result FIFO - than it can hold. */ - kLPADC_ResultFIFOReadyFlag = ADC_STAT_RDY_MASK, /*!< Indicates when the number of valid datawords in the result FIFO - is greater than the setting watermark level. */ -}; - -/*! - * @brief Define interrupt switchers of the module. - */ -enum _lpadc_interrupt_enable -{ - kLPADC_ResultFIFOOverflowInterruptEnable = ADC_IE_FOFIE_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF flag is asserted. */ - kLPADC_FIFOWatermarkInterruptEnable = ADC_IE_FWMIE_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY flag is asserted. */ -}; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) -/*! - * @brief The enumerator of lpadc trigger status flags, including interrupted flags and completed flags. - */ -enum _lpadc_trigger_status_flags -{ - kLPADC_Trigger0InterruptedFlag = 1UL << 0UL, /*!< Trigger 0 is interrupted by a high priority exception. */ - kLPADC_Trigger1InterruptedFlag = 1UL << 1UL, /*!< Trigger 1 is interrupted by a high priority exception. */ - kLPADC_Trigger2InterruptedFlag = 1UL << 2UL, /*!< Trigger 2 is interrupted by a high priority exception. */ - kLPADC_Trigger3InterruptedFlag = 1UL << 3UL, /*!< Trigger 3 is interrupted by a high priority exception. */ - kLPADC_Trigger4InterruptedFlag = 1UL << 4UL, /*!< Trigger 4 is interrupted by a high priority exception. */ - kLPADC_Trigger5InterruptedFlag = 1UL << 5UL, /*!< Trigger 5 is interrupted by a high priority exception. */ - kLPADC_Trigger6InterruptedFlag = 1UL << 6UL, /*!< Trigger 6 is interrupted by a high priority exception. */ - kLPADC_Trigger7InterruptedFlag = 1UL << 7UL, /*!< Trigger 7 is interrupted by a high priority exception. */ - kLPADC_Trigger8InterruptedFlag = 1UL << 8UL, /*!< Trigger 8 is interrupted by a high priority exception. */ - kLPADC_Trigger9InterruptedFlag = 1UL << 9UL, /*!< Trigger 9 is interrupted by a high priority exception. */ - kLPADC_Trigger10InterruptedFlag = 1UL << 10UL, /*!< Trigger 10 is interrupted by a high priority exception. */ - kLPADC_Trigger11InterruptedFlag = 1UL << 11UL, /*!< Trigger 11 is interrupted by a high priority exception. */ - kLPADC_Trigger12InterruptedFlag = 1UL << 12UL, /*!< Trigger 12 is interrupted by a high priority exception. */ - kLPADC_Trigger13InterruptedFlag = 1UL << 13UL, /*!< Trigger 13 is interrupted by a high priority exception. */ - kLPADC_Trigger14InterruptedFlag = 1UL << 14UL, /*!< Trigger 14 is interrupted by a high priority exception. */ - kLPADC_Trigger15InterruptedFlag = 1UL << 15UL, /*!< Trigger 15 is interrupted by a high priority exception. */ - - kLPADC_Trigger0CompletedFlag = 1UL << 16UL, /*!< Trigger 0 is completed and - trigger 0 has enabled completion interrupts. */ - kLPADC_Trigger1CompletedFlag = 1UL << 17UL, /*!< Trigger 1 is completed and - trigger 1 has enabled completion interrupts. */ - kLPADC_Trigger2CompletedFlag = 1UL << 18UL, /*!< Trigger 2 is completed and - trigger 2 has enabled completion interrupts. */ - kLPADC_Trigger3CompletedFlag = 1UL << 19UL, /*!< Trigger 3 is completed and - trigger 3 has enabled completion interrupts. */ - kLPADC_Trigger4CompletedFlag = 1UL << 20UL, /*!< Trigger 4 is completed and - trigger 4 has enabled completion interrupts. */ - kLPADC_Trigger5CompletedFlag = 1UL << 21UL, /*!< Trigger 5 is completed and - trigger 5 has enabled completion interrupts. */ - kLPADC_Trigger6CompletedFlag = 1UL << 22UL, /*!< Trigger 6 is completed and - trigger 6 has enabled completion interrupts. */ - kLPADC_Trigger7CompletedFlag = 1UL << 23UL, /*!< Trigger 7 is completed and - trigger 7 has enabled completion interrupts. */ - kLPADC_Trigger8CompletedFlag = 1UL << 24UL, /*!< Trigger 8 is completed and - trigger 8 has enabled completion interrupts. */ - kLPADC_Trigger9CompletedFlag = 1UL << 25UL, /*!< Trigger 9 is completed and - trigger 9 has enabled completion interrupts. */ - kLPADC_Trigger10CompletedFlag = 1UL << 26UL, /*!< Trigger 10 is completed and - trigger 10 has enabled completion interrupts. */ - kLPADC_Trigger11CompletedFlag = 1UL << 27UL, /*!< Trigger 11 is completed and - trigger 11 has enabled completion interrupts. */ - kLPADC_Trigger12CompletedFlag = 1UL << 28UL, /*!< Trigger 12 is completed and - trigger 12 has enabled completion interrupts. */ - kLPADC_Trigger13CompletedFlag = 1UL << 29UL, /*!< Trigger 13 is completed and - trigger 13 has enabled completion interrupts. */ - kLPADC_Trigger14CompletedFlag = 1UL << 30UL, /*!< Trigger 14 is completed and - trigger 14 has enabled completion interrupts. */ - kLPADC_Trigger15CompletedFlag = 1UL << 31UL, /*!< Trigger 15 is completed and - trigger 15 has enabled completion interrupts. */ -}; -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ - -/*! - * @brief Define enumeration of sample scale mode. - * - * The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum - * possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the - * reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows - * conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode. - */ -typedef enum _lpadc_sample_scale_mode -{ - kLPADC_SamplePartScale = 0U, /*!< Use divided input voltage signal. (Factor of 30/64). */ - kLPADC_SampleFullScale = 1U, /*!< Full scale (Factor of 1). */ -} lpadc_sample_scale_mode_t; - -/*! - * @brief Define enumeration of channel sample mode. - * - * The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B. - */ -typedef enum _lpadc_sample_channel_mode -{ - kLPADC_SampleChannelSingleEndSideA = 0U, /*!< Single end mode, using side A. */ - kLPADC_SampleChannelSingleEndSideB = 1U, /*!< Single end mode, using side B. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF - kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minus side. */ - kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minus side. */ -#elif defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE - kLPADC_SampleChannelDiffBothSide = 2U, /*!< Differential mode, using A and B. */ - kLPADC_SampleChannelDualSingleEndBothSide = - 3U, /*!< Dual-Single-Ended Mode. Both A side and B side channels are converted independently. */ -#endif -} lpadc_sample_channel_mode_t; - -/*! - * @brief Define enumeration of hardware average selection. - * - * It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to - * capture temporary results while the averaging iterations are executed. - */ -typedef enum _lpadc_hardware_average_mode -{ - kLPADC_HardwareAverageCount1 = 0U, /*!< Single conversion. */ - kLPADC_HardwareAverageCount2 = 1U, /*!< 2 conversions averaged. */ - kLPADC_HardwareAverageCount4 = 2U, /*!< 4 conversions averaged. */ - kLPADC_HardwareAverageCount8 = 3U, /*!< 8 conversions averaged. */ - kLPADC_HardwareAverageCount16 = 4U, /*!< 16 conversions averaged. */ - kLPADC_HardwareAverageCount32 = 5U, /*!< 32 conversions averaged. */ - kLPADC_HardwareAverageCount64 = 6U, /*!< 64 conversions averaged. */ - kLPADC_HardwareAverageCount128 = 7U, /*!< 128 conversions averaged. */ -} lpadc_hardware_average_mode_t; - -/*! - * @brief Define enumeration of sample time selection. - * - * The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher - * impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption - * when command looping and sequencing is configured and high conversion rates are not required. - */ -typedef enum _lpadc_sample_time_mode -{ - kLPADC_SampleTimeADCK3 = 0U, /*!< 3 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK5 = 1U, /*!< 5 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK7 = 2U, /*!< 7 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK11 = 3U, /*!< 11 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK19 = 4U, /*!< 19 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK35 = 5U, /*!< 35 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK67 = 6U, /*!< 69 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK131 = 7U, /*!< 131 ADCK cycles total sample time. */ -} lpadc_sample_time_mode_t; - -/*! - * @brief Define enumeration of hardware compare mode. - * - * After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting - * guides operation of the automatic compare function to optionally only store when the compare operation is true. - * When compare is enabled, the conversion result is compared to the compare values. - */ -typedef enum _lpadc_hardware_compare_mode -{ - kLPADC_HardwareCompareDisabled = 0U, /*!< Compare disabled. */ - kLPADC_HardwareCompareStoreOnTrue = 2U, /*!< Compare enabled. Store on true. */ - kLPADC_HardwareCompareRepeatUntilTrue = 3U, /*!< Compare enabled. Repeat channel acquisition until true. */ -} lpadc_hardware_compare_mode_t; - -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE -/*! - * @brief Define enumeration of conversion resolution mode. - * - * Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to - * #lpadc_sample_channel_mode_t - */ -typedef enum _lpadc_conversion_resolution_mode -{ - kLPADC_ConversionResolutionStandard = 0U, /*!< Standard resolution. Single-ended 12-bit conversion, Differential - 13-bit conversion with 2’s complement output. */ - kLPADC_ConversionResolutionHigh = 1U, /*!< High resolution. Single-ended 16-bit conversion; Differential 16-bit - conversion with 2’s complement output. */ -} lpadc_conversion_resolution_mode_t; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS -/*! - * @brief Define enumeration of conversion averages mode. - * - * Configure the converion average number for auto-calibration. - */ -typedef enum _lpadc_conversion_average_mode -{ - kLPADC_ConversionAverage1 = 0U, /*!< Single conversion. */ - kLPADC_ConversionAverage2 = 1U, /*!< 2 conversions averaged. */ - kLPADC_ConversionAverage4 = 2U, /*!< 4 conversions averaged. */ - kLPADC_ConversionAverage8 = 3U, /*!< 8 conversions averaged. */ - kLPADC_ConversionAverage16 = 4U, /*!< 16 conversions averaged. */ - kLPADC_ConversionAverage32 = 5U, /*!< 32 conversions averaged. */ - kLPADC_ConversionAverage64 = 6U, /*!< 64 conversions averaged. */ - kLPADC_ConversionAverage128 = 7U, /*!< 128 conversions averaged. */ -} lpadc_conversion_average_mode_t; -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - -/*! - * @brief Define enumeration of reference voltage source. - * - * For detail information, need to check the SoC's specification. - */ -typedef enum _lpadc_reference_voltage_mode -{ - kLPADC_ReferenceVoltageAlt1 = 0U, /*!< Option 1 setting. */ - kLPADC_ReferenceVoltageAlt2 = 1U, /*!< Option 2 setting. */ - kLPADC_ReferenceVoltageAlt3 = 2U, /*!< Option 3 setting. */ -} lpadc_reference_voltage_source_t; - -/*! - * @brief Define enumeration of power configuration. - * - * Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be - * possible. Refer to the device data sheet for power and performance capabilities for each setting. - */ -typedef enum _lpadc_power_level_mode -{ - kLPADC_PowerLevelAlt1 = 0U, /*!< Lowest power setting. */ - kLPADC_PowerLevelAlt2 = 1U, /*!< Next lowest power setting. */ - kLPADC_PowerLevelAlt3 = 2U, /*!< ... */ - kLPADC_PowerLevelAlt4 = 3U, /*!< Highest power setting. */ -} lpadc_power_level_mode_t; - -/*! - * @brief Define enumeration of trigger priority policy. - * - * This selection controls how higher priority triggers are handled. - */ -typedef enum _lpadc_trigger_priority_policy -{ - kLPADC_TriggerPriorityPreemptImmediately = 0U, /*!< If a higher priority trigger is detected during command - processing, the current conversion is aborted and the new - command specified by the trigger is started. */ - kLPADC_TriggerPriorityPreemptSoftly = 1U, /*!< If a higher priority trigger is received during command processing, - the current conversion is completed (including averaging iterations - and compare function if enabled) and stored to the result FIFO - before the higher priority trigger/command is initiated. */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY) && FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY - kLPADC_TriggerPriorityPreemptSubsequently = 2U, /*!< If a higher priority trigger is received during command - processing, the current command will be completed (averaging, - looping, compare) before servicing the higher priority trigger. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY */ -} lpadc_trigger_priority_policy_t; - -/*! - * @brief LPADC global configuration. - * - * This structure would used to keep the settings for initialization. - */ -typedef struct -{ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock - selection logic at the chip level and is optionally used for the ADC clock source. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - bool enableVref1LowVoltage; /*!< If voltage reference option1 input is below 1.8V, it should be "true". - If voltage reference option1 input is above 1.8V, it should be "false". */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - bool enableInDozeMode; /*!< Control system transition to Stop and Wait power modes while ADC is converting. When - enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the - ADC will wait for the current averaging iteration/FIFO storage to complete before - acknowledging stop or wait mode entry. */ -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS - lpadc_conversion_average_mode_t conversionAverageMode; /*!< Auto-Calibration Averages. */ -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - bool enableAnalogPreliminary; /*!< ADC analog circuits are pre-enabled and ready to execute conversions without - startup delays(at the cost of higher DC current consumption). */ - uint32_t powerUpDelay; /*!< When the analog circuits are not pre-enabled, the ADC analog circuits are only powered - while the ADC is active and there is a counted delay defined by this field after an - initial trigger transitions the ADC from its Idle state to allow time for the analog - circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must - result in a longer delay than the analog startup time. */ - lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for - conversions.*/ - lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */ - lpadc_trigger_priority_policy_t triggerPriorityPolicy; /*!< Control how higher priority triggers are handled, see to - lpadc_trigger_priority_policy_t. */ - bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during - command execution sequencing between LOOP iterations, between commands in a sequence, and - between conversions when command is executing in "Compare Until True" configuration. */ - uint32_t convPauseDelay; /*!< Controls the duration of pausing during command execution sequencing. The pause delay - is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing - function is enabled. The available value range is in 9-bit. */ -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - /* for FIFO0. */ - uint32_t FIFO0Watermark; /*!< FIFO0Watermark is a programmable threshold setting. When the number of datawords - stored in the ADC Result FIFO0 is greater than the value in this field, the ready flag - would be asserted to indicate stored data has reached the programmable threshold. */ - /* for FIFO1. */ - uint32_t FIFO1Watermark; /*!< FIFO1Watermark is a programmable threshold setting. When the number of datawords - stored in the ADC Result FIFO1 is greater than the value in this field, the ready flag - would be asserted to indicate stored data has reached the programmable threshold. */ -#else - /* for FIFO. */ - uint32_t FIFOWatermark; /*!< FIFOWatermark is a programmable threshold setting. When the number of datawords stored - in the ADC Result FIFO is greater than the value in this field, the ready flag would be - asserted to indicate stored data has reached the programmable threshold. */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ -} lpadc_config_t; - -/*! - * @brief Define structure to keep the configuration for conversion command. - */ -typedef struct -{ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ - lpadc_sample_channel_mode_t sampleChannelMode; /*!< Channel sample mode. */ - uint32_t channelNumber; /*!< Channel number, select the channel or channel pair. */ - uint32_t chainedNextCommandNumber; /*!< Selects the next command to be executed after this command completes. - 1-15 is available, 0 is to terminate the chain after this command. */ - bool enableAutoChannelIncrement; /*!< Loop with increment: when disabled, the "loopCount" field selects the number - of times the selected channel is converted consecutively; when enabled, the - "loopCount" field defines how many consecutive channels are converted as part - of the command execution. */ - uint32_t loopCount; /*!< Selects how many times this command executes before finish and transition to the next - command or Idle state. Command executes LOOP+1 times. 0-15 is available. */ - lpadc_hardware_average_mode_t hardwareAverageMode; /*!< Hardware average selection. */ - lpadc_sample_time_mode_t sampleTimeMode; /*!< Sample time selection. */ - - lpadc_hardware_compare_mode_t hardwareCompareMode; /*!< Hardware compare selection. */ - uint32_t hardwareCompareValueHigh; /*!< Compare Value High. The available value range is in 16-bit. */ - uint32_t hardwareCompareValueLow; /*!< Compare Value Low. The available value range is in 16-bit. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - lpadc_conversion_resolution_mode_t conversionResolutionMode; /*!< Conversion resolution mode. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG - bool enableWaitTrigger; /*!< Wait for trigger assertion before execution: when disabled, this command will be - automatically executed; when enabled, the active trigger must be asserted again before - executing this command. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ -} lpadc_conv_command_config_t; - -/*! - * @brief Define structure to keep the configuration for conversion trigger. - */ -typedef struct -{ - uint32_t targetCommandId; /*!< Select the command from command buffer to execute upon detect of the associated - trigger event. */ - uint32_t delayPower; /*!< Select the trigger delay duration to wait at the start of servicing a trigger event. - When this field is clear, then no delay is incurred. When this field is set to a non-zero - value, the duration for the delay is 2^delayPower ADCK cycles. The available value range - is 4-bit. */ - uint32_t priority; /*!< Sets the priority of the associated trigger source. If two or more triggers have the same - priority level setting, the lower order trigger event has the higher priority. The lower - value for this field is for the higher priority, the available value range is 1-bit. */ -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - uint8_t channelAFIFOSelect; /* SAR Result Destination For Channel A. */ - uint8_t channelBFIFOSelect; /* SAR Result Destination For Channel B. */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - bool enableHardwareTrigger; /*!< Enable hardware trigger source to initiate conversion on the rising edge of the - input trigger source or not. THe software trigger is always available. */ -} lpadc_conv_trigger_config_t; - -/*! - * @brief Define the structure to keep the conversion result. - */ -typedef struct -{ - uint32_t commandIdSource; /*!< Indicate the command buffer being executed that generated this result. */ - uint32_t loopCountIndex; /*!< Indicate the loop count value during command execution that generated this result. */ - uint32_t triggerIdSource; /*!< Indicate the trigger source that initiated a conversion and generated this result. */ - uint16_t convValue; /*!< Data result. */ -} lpadc_conv_result_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ -/*! - * @name Initialization & de-initialization. - * @{ - */ - -/*! - * @brief Initializes the LPADC module. - * - * @param base LPADC peripheral base address. - * @param config Pointer to configuration structure. See "lpadc_config_t". - */ -void LPADC_Init(ADC_Type *base, const lpadc_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for initial configuration. - * - * This function initializes the converter configuration structure with an available settings. The default values are: - * @code - * config->enableInDozeMode = true; - * config->enableAnalogPreliminary = false; - * config->powerUpDelay = 0x80; - * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - * config->powerLevelMode = kLPADC_PowerLevelAlt1; - * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; - * config->enableConvPause = false; - * config->convPauseDelay = 0U; - * config->FIFOWatermark = 0U; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConfig(lpadc_config_t *config); - -/*! - * @brief De-initializes the LPADC module. - * - * @param base LPADC peripheral base address. - */ -void LPADC_Deinit(ADC_Type *base); - -/*! - * @brief Switch on/off the LPADC module. - * - * @param base LPADC peripheral base address. - * @param enable switcher to the module. - */ -static inline void LPADC_Enable(ADC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= ADC_CTRL_ADCEN_MASK; - } - else - { - base->CTRL &= ~ADC_CTRL_ADCEN_MASK; - } -} - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Do reset the conversion FIFO0. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO0(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO0_MASK; -} - -/*! - * @brief Do reset the conversion FIFO1. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO1(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO1_MASK; -} -#else -/*! - * @brief Do reset the conversion FIFO. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO_MASK; -} -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * @brief Do reset the module's configuration. - * - * Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL). - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetConfig(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RST_MASK; - base->CTRL &= ~ADC_CTRL_RST_MASK; -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Get status flags. - * - * @param base LPADC peripheral base address. - * @return status flags' mask. See to #_lpadc_status_flags. - */ -static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base) -{ - return base->STAT; -} - -/*! - * @brief Clear status flags. - * - * Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for flags to be cleared. See to #_lpadc_status_flags. - */ -static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) -{ - base->STAT = mask; -} - -#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) -/*! - * @brief Get trigger status flags to indicate which trigger sequences have been completed or interrupted by a high - * priority trigger exception. - * - * @param base LPADC peripheral base address. - * @return The OR'ed value of @ref _lpadc_trigger_status_flags. - */ -static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base) -{ - return base->TSTAT; -} - -/*! - * @brief Clear trigger status flags. - * - * @param base LPADC peripheral base address. - * @param mask The mask of trigger status flags to be cleared, should be the - * OR'ed value of @ref _lpadc_trigger_status_flags. - */ -static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask) -{ - base->TSTAT = mask; -} -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enable interrupts. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. - */ -static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask) -{ - base->IE |= mask; -} - -/*! - * @brief Disable interrupts. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. - */ -static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask) -{ - base->IE &= ~mask; -} - -/*! - * @name DMA Control - * @{ - */ - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Switch on/off the DMA trigger for FIFO0 watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFO0WatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE0_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE0_MASK; - } -} - -/*! - * @brief Switch on/off the DMA trigger for FIFO1 watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFO1WatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE1_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE1_MASK; - } -} -#else -/*! - * @brief Switch on/off the DMA trigger for FIFO watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE_MASK; - } -} -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - /* @} */ - -/*! - * @name Trigger and conversion with FIFO. - * @{ - */ - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Get the count of result kept in conversion FIFOn. - * - * @param base LPADC peripheral base address. - * @param index Result FIFO index. - * @return The count of result kept in conversion FIFOn. - */ -static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index) -{ - return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL[index]) >> ADC_FCTRL_FCOUNT_SHIFT; -} - -/*! - * brief Get the result in conversion FIFOn. - * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. - * param index Result FIFO index. - * - * return Status whether FIFOn entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index); -#else -/*! - * @brief Get the count of result kept in conversion FIFO. - * - * @param base LPADC peripheral base address. - * @return The count of result kept in conversion FIFO. - */ -static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base) -{ - return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL) >> ADC_FCTRL_FCOUNT_SHIFT; -} - -/*! - * @brief Get the result in conversion FIFO. - * - * @param base LPADC peripheral base address. - * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. - * - * @return Status whether FIFO entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * @brief Configure the conversion trigger source. - * - * Each programmable trigger can launch the conversion command in command buffer. - * - * @param base LPADC peripheral base address. - * @param triggerId ID for each trigger. Typically, the available value range is from 0. - * @param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. - */ -void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for trigger's configuration. - * - * This function initializes the trigger's configuration structure with an available settings. The default values are: - * @code - * config->commandIdSource = 0U; - * config->loopCountIndex = 0U; - * config->triggerIdSource = 0U; - * config->enableHardwareTrigger = false; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config); - -/*! - * @brief Do software trigger to conversion command. - * - * @param base LPADC peripheral base address. - * @param triggerIdMask Mask value for software trigger indexes, which count from zero. - */ -static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask) -{ - /* Writes to ADCx_SWTRIG register are ignored while ADCx_CTRL[ADCEN] is clear. */ - base->SWTRIG = triggerIdMask; -} - -/*! - * @brief Configure conversion command. - * - * @param base LPADC peripheral base address. - * @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. - * @param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. - */ -void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for conversion command's configuration. - * - * This function initializes the conversion command's configuration structure with an available settings. The default - * values are: - * @code - * config->sampleScaleMode = kLPADC_SampleFullScale; - * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; - * config->channelNumber = 0U; - * config->chainedNextCmdNumber = 0U; - * config->enableAutoChannelIncrement = false; - * config->loopCount = 0U; - * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - * config->sampleTimeMode = kLPADC_SampleTimeADCK3; - * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - * config->hardwareCompareValueHigh = 0U; - * config->hardwareCompareValueLow = 0U; - * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; - * config->enableWaitTrigger = false; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config); - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS -/*! - * @brief Enable the calibration function. - * - * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes - * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value - * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- - * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the - * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. - * - * @param base LPADC peripheral base address. - * @param enable switcher to the calibration function. - */ -void LPADC_EnableCalibration(ADC_Type *base, bool enable); -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! - * @brief Set proper offset value to trim ADC. - * - * To minimize the offset during normal operation, software should read the conversion result from - * the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register. - * - * @param base LPADC peripheral base address. - * @param value Setting offset value. - */ -static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value) -{ - base->OFSTRIM = (value & ADC_OFSTRIM_OFSTRIM_MASK) >> ADC_OFSTRIM_OFSTRIM_SHIFT; -} - -/*! - * @brief Do auto calibration. - * - * Calibration function should be executed before using converter in application. It used the software trigger and a - * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API - * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) - * -LPADC_SetConvTriggerConfig(...) - * - * @param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base); -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! - * @brief Set proper offset value to trim ADC. - * - * Set the offset trim value for offset calibration manually. - * - * @param base LPADC peripheral base address. - * @param valueA Setting offset value A. - * @param valueB Setting offset value B. - * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. - */ -static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t valueA, uint32_t valueB) -{ - base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB); -} -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ - -/*! - * @brief Enable the offset calibration function. - * - * @param base LPADC peripheral base address. - * @param enable switcher to the calibration function. - */ -static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= ADC_CTRL_CALOFS_MASK; - } - else - { - base->CTRL &= ~ADC_CTRL_CALOFS_MASK; - } -} - -/*! - * @brief Do offset calibration. - * - * @param base LPADC peripheral base address. - */ -void LPADC_DoOffsetCalibration(ADC_Type *base); - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ -/*! - * brief Do auto calibration. - * - * param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base); -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ - -/* @} */ - -#if defined(__cplusplus) -} -#endif -/*! - * @} - */ -#endif /* _FSL_LPADC_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_mrt.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_mrt.c deleted file mode 100644 index 69697a21b5c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_mrt.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_mrt.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.mrt" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base Multi-Rate timer peripheral base address - * - * @return The MRT instance - */ -static uint32_t MRT_GetInstance(MRT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to MRT bases for each instance. */ -static MRT_Type *const s_mrtBases[] = MRT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to MRT clocks for each instance. */ -static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(MRT_RSTS_N) -/*! @brief Pointers to MRT resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_mrtResets[] = MRT_RSTS_N; -#elif defined(MRT_RSTS) -/*! @brief Pointers to MRT resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_mrtResets[] = MRT_RSTS; -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t MRT_GetInstance(MRT_Type *base) -{ - uint32_t instance; - uint32_t mrtArrayCount = (sizeof(s_mrtBases) / sizeof(s_mrtBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < mrtArrayCount; instance++) - { - if (s_mrtBases[instance] == base) - { - break; - } - } - - assert(instance < mrtArrayCount); - - return instance; -} - -/*! - * brief Ungates the MRT clock and configures the peripheral for basic operation. - * - * note This API should be called at the beginning of the application using the MRT driver. - * - * param base Multi-Rate timer peripheral base address - * param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in - * MODCFG reigster, param config is useless. - */ -void MRT_Init(MRT_Type *base, const mrt_config_t *config) -{ - assert(config != NULL); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate the MRT clock */ - CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(MRT_RSTS_N) || defined(MRT_RSTS) - /* Reset the module. */ - RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]); -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) - /* Set timer operating mode */ - base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask); -#endif -} - -/*! - * brief Gate the MRT clock - * - * param base Multi-Rate timer peripheral base address - */ -void MRT_Deinit(MRT_Type *base) -{ - /* Stop all the timers */ - MRT_StopTimer(base, kMRT_Channel_0); - MRT_StopTimer(base, kMRT_Channel_1); -#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 2U) - MRT_StopTimer(base, kMRT_Channel_2); -#endif -#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 3U) - MRT_StopTimer(base, kMRT_Channel_3); -#endif - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the MRT clock*/ - CLOCK_DisableClock(s_mrtClocks[MRT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Used to update the timer period in units of count. - * - * The new value will be immediately loaded or will be loaded at the end of the current time - * interval. For one-shot interrupt mode the new value will be immediately loaded. - * - * note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * param base Multi-Rate timer peripheral base address - * param channel Timer channel number - * param count Timer period in units of ticks - * param immediateLoad true: Load the new value immediately into the TIMER register; - * false: Load the new value at the end of current timer interval - */ -void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - - uint32_t newValue = count; - if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == (uint8_t)kMRT_OneShotMode) || (immediateLoad)) - { - /* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */ - newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK; - } - - /* Update the timer interval value */ - base->CHANNEL[channel].INTVAL = newValue; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_mrt.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_mrt.h deleted file mode 100644 index 7829d984e20..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_mrt.h +++ /dev/null @@ -1,366 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_MRT_H_ -#define _FSL_MRT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup mrt - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3 */ -/*@}*/ - -/*! @brief List of MRT channels */ -typedef enum _mrt_chnl -{ - kMRT_Channel_0 = 0U, /*!< MRT channel number 0*/ - kMRT_Channel_1, /*!< MRT channel number 1 */ - kMRT_Channel_2, /*!< MRT channel number 2 */ - kMRT_Channel_3 /*!< MRT channel number 3 */ -} mrt_chnl_t; - -/*! @brief List of MRT timer modes */ -typedef enum _mrt_timer_mode -{ - kMRT_RepeatMode = (0 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< Repeat Interrupt mode */ - kMRT_OneShotMode = (1 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< One-shot Interrupt mode */ - kMRT_OneShotStallMode = (2 << MRT_CHANNEL_CTRL_MODE_SHIFT) /*!< One-shot stall mode */ -} mrt_timer_mode_t; - -/*! @brief List of MRT interrupts */ -typedef enum _mrt_interrupt_enable -{ - kMRT_TimerInterruptEnable = MRT_CHANNEL_CTRL_INTEN_MASK /*!< Timer interrupt enable*/ -} mrt_interrupt_enable_t; - -/*! @brief List of MRT status flags */ -typedef enum _mrt_status_flags -{ - kMRT_TimerInterruptFlag = MRT_CHANNEL_STAT_INTFLAG_MASK, /*!< Timer interrupt flag */ - kMRT_TimerRunFlag = MRT_CHANNEL_STAT_RUN_MASK, /*!< Indicates state of the timer */ -} mrt_status_flags_t; - -/*! - * @brief MRT configuration structure - * - * This structure holds the configuration settings for the MRT peripheral. To initialize this - * structure to reasonable defaults, call the MRT_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _mrt_config -{ - bool enableMultiTask; /*!< true: Timers run in multi-task mode; false: Timers run in hardware status mode */ -} mrt_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the MRT clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the MRT driver. - * - * @param base Multi-Rate timer peripheral base address - * @param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in - * MODCFG reigster, param config is useless. - */ -void MRT_Init(MRT_Type *base, const mrt_config_t *config); - -/*! - * @brief Gate the MRT clock - * - * @param base Multi-Rate timer peripheral base address - */ -void MRT_Deinit(MRT_Type *base); - -/*! - * @brief Fill in the MRT config struct with the default settings - * - * The default values are: - * @code - * config->enableMultiTask = false; - * @endcode - * @param config Pointer to user's MRT config structure. - */ -static inline void MRT_GetDefaultConfig(mrt_config_t *config) -{ - assert(config != NULL); -#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) - /* Use hardware status operating mode */ - config->enableMultiTask = false; -#endif -} - -/*! - * @brief Sets up an MRT channel mode. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Channel that is being configured. - * @param mode Timer mode to use for the channel. - */ -static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - - uint32_t reg = base->CHANNEL[channel].CTRL; - - /* Clear old value */ - reg &= ~MRT_CHANNEL_CTRL_MODE_MASK; - /* Add the new mode */ - reg |= (uint32_t)mode; - - base->CHANNEL[channel].CTRL = reg; -} - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the MRT interrupt. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].CTRL |= mask; -} - -/*! - * @brief Disables the selected MRT interrupt. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to disable. This is a logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].CTRL &= ~mask; -} - -/*! - * @brief Gets the enabled MRT interrupts. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the MRT status flags - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::mrt_status_flags_t - */ -static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK)); -} - -/*! - * @brief Clears the MRT status flags. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::mrt_status_flags_t - */ -static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK); -} - -/*! @}*/ - -/*! - * @name Read and Write the timer period - * @{ - */ - -/*! - * @brief Used to update the timer period in units of count. - * - * The new value will be immediately loaded or will be loaded at the end of the current time - * interval. For one-shot interrupt mode the new value will be immediately loaded. - * - * @note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param count Timer period in units of ticks - * @param immediateLoad true: Load the new value immediately into the TIMER register; - * false: Load the new value at the end of current timer interval - */ -void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad); - -/*! - * @brief Reads the current timer counting value. - * - * This function returns the real-time timer counting value, in a range from 0 to a - * timer period. - * - * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return Current timer counting value in ticks - */ -static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - return base->CHANNEL[channel].TIMER; -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the timer counting. - * - * After calling this function, timers load period value, counts down to 0 and - * depending on the timer mode it will either load the respective start value again or stop. - * - * @note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - * @param count Timer period in units of ticks. Count can contain the LOAD bit, which control the force load feature. - */ -static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - assert((uint32_t)(count & ~MRT_CHANNEL_INTVAL_LOAD_MASK) <= (uint32_t)MRT_CHANNEL_INTVAL_IVALUE_MASK); - /* Write the timer interval value */ - base->CHANNEL[channel].INTVAL = count; -} - -/*! - * @brief Stops the timer counting. - * - * This function stops the timer from counting. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - */ -static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - /* Stop the timer immediately */ - base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK; -} - -/*! @}*/ - -/*! - * @name Get & release channel - * @{ - */ - -/*! - * @brief Find the available channel. - * - * This function returns the lowest available channel number. - * - * @param base Multi-Rate timer peripheral base address - */ -static inline uint32_t MRT_GetIdleChannel(MRT_Type *base) -{ - return base->IDLE_CH; -} - -#if !(defined(FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) && FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) -/*! - * @brief Release the channel when the timer is using the multi-task mode. - * - * In multi-task mode, the INUSE flags allow more control over when MRT channels are released for - * further use. The user can hold on to a channel acquired by calling MRT_GetIdleChannel() for as - * long as it is needed and release it by calling this function. This removes the need to ask for - * an available channel for every use. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - */ -static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - - uint32_t reg = base->CHANNEL[channel].STAT; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg = ~MRT_CHANNEL_STAT_INTFLAG_MASK; - reg |= MRT_CHANNEL_STAT_INUSE_MASK; - - base->CHANNEL[channel].STAT = reg; -} -#endif - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_MRT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_ostimer.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_ostimer.c deleted file mode 100644 index c3acfb0e48f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_ostimer.c +++ /dev/null @@ -1,381 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_ostimer.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.ostimer" -#endif - -/* Typedef for interrupt handler. */ -typedef void (*ostimer_isr_t)(OSTIMER_Type *base, ostimer_callback_t cb); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base OSTIMER peripheral base address - * - * @return The OSTIMER instance - */ -static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base); - -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) -/* @brief Translate the value from gray-code to decimal by the Code Gray in SYSCTL. - * - * @param gray The gray value input. - * - * @return the decimal value. - */ -static uint64_t OSTIMER_GrayToDecimalbyCodeGray(uint64_t gray); -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of OSTIMER handle. */ -static ostimer_callback_t s_ostimerHandle[FSL_FEATURE_SOC_OSTIMER_COUNT]; -/* Array of OSTIMER peripheral base address. */ -static OSTIMER_Type *const s_ostimerBases[] = OSTIMER_BASE_PTRS; -/* Array of OSTIMER IRQ number. */ -static const IRQn_Type s_ostimerIRQ[] = OSTIMER_IRQS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of OSTIMER clock name. */ -static const clock_ip_name_t s_ostimerClock[] = OSTIMER_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/* OSTIMER ISR for transactional APIs. */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -static ostimer_isr_t s_ostimerIsr = (ostimer_isr_t)DefaultISR; -#else -static ostimer_isr_t s_ostimerIsr; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* @brief Function for getting the instance number of OS timer. */ -static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_ostimerBases); instance++) - { - if (s_ostimerBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_ostimerBases)); - - return instance; -} - -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) -/* @brief Translate the value from gray-code to decimal by the Code Gray in SYSCTL. - * - * @param gray The gray value input. - * - * @return the decimal value. - */ -static uint64_t OSTIMER_GrayToDecimalbyCodeGray(uint64_t gray) -{ - uint64_t decOut; - - SYSCTL->CODE_GRAY_LSB = (uint32_t)(gray & 0xFFFFFFFFU); - SYSCTL->CODE_GRAY_MSB = (uint32_t)((gray >> 32U) & 0x3FFU); // limit to 42bits as OSevent timer - __NOP(); - decOut = ((uint64_t)(SYSCTL->CODE_BIN_MSB) & 0x3FFU) << 32U; - decOut |= (uint64_t)(SYSCTL->CODE_BIN_LSB); - - return decOut; -} -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ - -/* @brief Translate the value from gray-code to decimal. */ -/* - * @param gray The gray value input. - * - * @return the decimal value. - */ -uint64_t OSTIMER_GrayToDecimal(uint64_t gray) -{ -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) - return OSTIMER_GrayToDecimalbyCodeGray(gray); -#else - uint64_t temp = gray; - while (temp != 0U) - { - temp >>= 1U; - gray ^= temp; - } - - return gray; -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ -} - -/* @brief Enable the OSTIMER interrupt. - * - * After calling this function, the OSTIMER driver will enable/disable the IRQ and module interrupt enablement. - * - * @param base OSTIMER peripheral base address. - * @param enable enable/disable the IRQ and module interrupt enablement. - * - true: Disable the IRQ and module interrupt enablement. - * - false: Disable the IRQ and module interrupt enablement. - * @return none - */ -static void OSTIMER_EnableInterrupt(OSTIMER_Type *base, bool enable) -{ - assert(NULL != base); - - if (enable) - { - /* Enable the IRQ and module interrupt enablement. */ - (void)EnableIRQ(s_ostimerIRQ[OSTIMER_GetInstance(base)]); - base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; - } - else - { - /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ - (void)DisableIRQ(s_ostimerIRQ[OSTIMER_GetInstance(base)]); - base->OSEVENT_CTRL &= ~OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; /* Clear interrupt flag by writing 1. */ - } -} - -/*! - * @brief Initializes an OSTIMER by turning it's clock on. - * - */ -void OSTIMER_Init(OSTIMER_Type *base) -{ - assert(NULL != base); - - uint32_t instance = OSTIMER_GetInstance(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if !(defined(FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) && FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) - /* Enable the OSTIMER 32k clock in PMC module. */ - CLOCK_EnableOstimer32kClock(); -#endif - /* Enable clock for OSTIMER. */ - CLOCK_EnableClock(s_ostimerClock[instance]); -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) - CLOCK_EnableClock(kCLOCK_Sysctl); -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Deinitializes a OSTIMER instance. - * - * This function shuts down OSTIMER clock - * - * @param base OSTIMER peripheral base address. - */ -void OSTIMER_Deinit(OSTIMER_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable clock for OSTIMER. */ - CLOCK_DisableClock(s_ostimerClock[OSTIMER_GetInstance(base)]); -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) - CLOCK_DisableClock(kCLOCK_Sysctl); -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Get OSTIMER status Flags. - * - * This returns the status flag. - * Currently, only match interrupt flag can be got. - * - * @param base OSTIMER peripheral base address. - * @return status register value - */ -uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base) -{ - return base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK; -} - -/*! - * @brief Clear Status Interrupt Flags. - * - * This clears intr status flag. - * Currently, only match interrupt flag can be cleared. - * - * @param base OSTIMER peripheral base address. - * @param mask Clear bit mask. - * @return none - */ -void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask) -{ - base->OSEVENT_CTRL |= mask; -} - -/*! - * @brief Set the match raw value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. - * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is gray-code format) - * - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. - * @retval kStatus_Fail - Set match raw value fail. - */ -status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) -{ -#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK - uint64_t decValueTimer; -#endif - status_t status; - uint64_t tmp = count; - uint32_t instance = OSTIMER_GetInstance(base); - - /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ - OSTIMER_EnableInterrupt(base, false); - - s_ostimerIsr = OSTIMER_HandleIRQ; - s_ostimerHandle[instance] = cb; - - /* Set the match value. */ - base->MATCH_L = (uint32_t)tmp; - base->MATCH_H = (uint32_t)(tmp >> 32U); - -#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK - /* Workaround-2019-12-30: - * Since OSTimer's counter register is Gray-encoded, it would cost more time to write register. When EVTimer Match - * Write Ready bit is low, which means the previous match value has been updated successfully by that time, it is - * safe to reload (write) the Match Registers. Even if there is the RM comment that "In typical applications, it - * should not be necessary to test this bit", but we found the interruption would not be reported when the delta - * timer user added is smaller(IE: RT595 11us in 1MHz typical application) in release version." To prevent such - * issue from happening, we'd better wait for the match value to update successfully before enabling IRQ. - */ - while (0U != (base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)) - { - } - - /* After the WR_RDY bit became low, we need to check whether current time goes ahead of the match value we set. - * (1) If current timer value has gone ahead of the match value, the interrupt will not be reported before 64-bit - * timer value over flow. We need to check whether the interrupt flag has been set or not: if yes, we will enable - * interrupt and return success; if not, we will return fail directly. - * (2) If current timer value has not gone ahead of match value, we will enable interrupt and return success. - */ - decValueTimer = OSTIMER_GetCurrentTimerValue(base); - if ((decValueTimer >= OSTIMER_GrayToDecimal(tmp)) && - (0U == (base->OSEVENT_CTRL & (uint32_t)kOSTIMER_MatchInterruptFlag))) - { - status = kStatus_Fail; - } - else -#endif /* #ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK */ - { - /* Enable the module interrupt enablement. */ - OSTIMER_EnableInterrupt(base, true); - status = kStatus_Success; - } - - return status; -} - -/*! - * @brief Set the match value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code in - * API. ) - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @retval kStatus_Success - Set match value and enable interrupt Successfully. - * @retval kStatus_Fail - Set match value fail. - */ -status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) -{ - uint64_t tmp = OSTIMER_DecimalToGray(count); - - return OSTIMER_SetMatchRawValue(base, tmp, cb); -} - -/*! - * @brief Get current timer count value from OSTIMER. - * - * This function will get a decimal timer count value. - * The RAW value of timer count is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of OSTIMER which will formated to decimal value. - */ -uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = OSTIMER_GetCurrentTimerRawValue(base); - - return OSTIMER_GrayToDecimal(tmp); -} - -/*! - * @brief Get the capture value from OSTIMER. - * - * This function will get a capture decimal-value from OSTIMER. - * The RAW value of timer capture is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of capture register, data format is decimal. - */ -uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = OSTIMER_GetCaptureRawValue(base); - - return OSTIMER_GrayToDecimal(tmp); -} - -void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb) -{ - /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ - OSTIMER_EnableInterrupt(base, false); - - if (cb != NULL) - { - cb(); - } -} - -#if defined(OSTIMER0) -void OS_EVENT_DriverIRQHandler(void); -void OS_EVENT_DriverIRQHandler(void) -{ - s_ostimerIsr(OSTIMER0, s_ostimerHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(OSTIMER) -void OS_EVENT_DriverIRQHandler(void); -void OS_EVENT_DriverIRQHandler(void) -{ - s_ostimerIsr(OSTIMER, s_ostimerHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_ostimer.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_ostimer.h deleted file mode 100644 index c74a7931362..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_ostimer.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_OSTIMER_H_ -#define _FSL_OSTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup ostimer - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief OSTIMER driver version. */ -#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) -/*@}*/ - -/*! - * @brief OSTIMER status flags. - */ -enum _ostimer_flags -{ - kOSTIMER_MatchInterruptFlag = (OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK), /*!< Match interrupt flag bit, sets if - the match value was reached. */ -}; - -/*! @brief ostimer callback function. */ -typedef void (*ostimer_callback_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes an OSTIMER by turning its bus clock on - * - */ -void OSTIMER_Init(OSTIMER_Type *base); - -/*! - * @brief Deinitializes a OSTIMER instance. - * - * This function shuts down OSTIMER bus clock - * - * @param base OSTIMER peripheral base address. - */ -void OSTIMER_Deinit(OSTIMER_Type *base); - -/*! - * @brief Translate the value from gray-code to decimal. - * - * @param gray The gray value input. - * @return The decimal value. - */ -uint64_t OSTIMER_GrayToDecimal(uint64_t gray); - -/*! - * @brief Translate the value from decimal to gray-code. - * - * @param dec The decimal value. - * @return The gray code of the input value. - */ -static inline uint64_t OSTIMER_DecimalToGray(uint64_t dec) -{ - return (dec ^ (dec >> 1U)); -} - -/*! - * @brief Get OSTIMER status Flags. - * - * This returns the status flag. - * Currently, only match interrupt flag can be got. - * - * @param base OSTIMER peripheral base address. - * @return status register value - */ -uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base); - -/*! - * @brief Clear Status Interrupt Flags. - * - * This clears intrrupt status flag. - * Currently, only match interrupt flag can be cleared. - * - * @param base OSTIMER peripheral base address. - * @param mask Clear bit mask. - * @return none - */ -void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask); - -/*! - * @brief Set the match raw value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. - * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is gray-code format) - * - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. - * @retval kStatus_Fail - Set match raw value fail. - */ -status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); - -/*! - * @brief Set the match value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central OS TIMER. - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code - * internally.) - * - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @retval kStatus_Success - Set match value and enable interrupt Successfully. - * @retval kStatus_Fail - Set match value fail. - */ -status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); - -/*! - * @brief Set value to OSTIMER MATCH register directly. - * - * This function writes the input value to OSTIMER MATCH register directly, - * it does not touch any other registers. Note that, the data format is - * gray-code. The function @ref OSTIMER_DecimalToGray could convert decimal - * value to gray code. - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value (Value is gray-code format). - */ -static inline void OSTIMER_SetMatchRegister(OSTIMER_Type *base, uint64_t value) -{ -#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK - /* Wait for MATCH register ready for write. */ - while (0U != (base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)) - { - } -#endif - - base->MATCH_L = (uint32_t)value; - base->MATCH_H = (uint32_t)(value >> 32U); -} - -/*! - * @brief Enable the OSTIMER counter match interrupt. - * - * Enable the timer counter match interrupt. The interrupt happens when OSTIMER - * counter matches the value in MATCH registers. - * - * @param base OSTIMER peripheral base address. - */ -static inline void OSTIMER_EnableMatchInterrupt(OSTIMER_Type *base) -{ - base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; -} - -/*! - * @brief Disable the OSTIMER counter match interrupt. - * - * Disable the timer counter match interrupt. The interrupt happens when OSTIMER - * counter matches the value in MATCH registers. - * - * @param base OSTIMER peripheral base address. - */ -static inline void OSTIMER_DisableMatchInterrupt(OSTIMER_Type *base) -{ - base->OSEVENT_CTRL &= ~OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; -} - -/*! - * @brief Get current timer raw count value from OSTIMER. - * - * This function will get a gray code type timer count value from OS timer register. - * The raw value of timer count is gray code format. - * - * @param base OSTIMER peripheral base address. - * @return Raw value of OSTIMER, gray code format. - */ -static inline uint64_t OSTIMER_GetCurrentTimerRawValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = base->EVTIMERL; - tmp |= (uint64_t)(base->EVTIMERH) << 32U; - - return tmp; -} - -/*! - * @brief Get current timer count value from OSTIMER. - * - * This function will get a decimal timer count value. - * The RAW value of timer count is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of OSTIMER which will be formated to decimal value. - */ -uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base); - -/*! - * @brief Get the capture value from OSTIMER. - * - * This function will get a captured gray-code value from OSTIMER. - * The Raw value of timer capture is gray code format. - * - * @param base OSTIMER peripheral base address. - * @return Raw value of capture register, data format is gray code. - */ -static inline uint64_t OSTIMER_GetCaptureRawValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = base->CAPTURE_L; - tmp |= (uint64_t)(base->CAPTURE_H) << 32U; - - return tmp; -} - -/*! - * @brief Get the capture value from OSTIMER. - * - * This function will get a capture decimal-value from OSTIMER. - * The RAW value of timer capture is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of capture register, data format is decimal. - */ -uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base); - -/*! - * @brief OS timer interrupt Service Handler. - * - * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request - * in OSTIMER_SetMatchValue()). - * if no user callback is scheduled, the interrupt will simply be cleared. - * - * @param base OS timer peripheral base address. - * @param cb callback scheduled for this instance of OS timer - * @return none - */ -void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb); -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_OSTIMER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_pint.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_pint.c deleted file mode 100644 index c5557dd030f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_pint.c +++ /dev/null @@ -1,971 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_pint.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.pint" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -/*! @brief Irq number array */ -static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS + - FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; - -/*! @brief Callback function array for SECPINT(s). */ -static pint_cb_t s_secpintCallback[FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS]; -#else -/*! @brief Irq number array */ -static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - -/*! @brief Callback function array for PINT(s). */ -static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Initialize PINT peripheral. - - * This function initializes the PINT peripheral and enables the clock. - * - * param base Base address of the PINT peripheral. - * - * retval None. - */ -void PINT_Init(PINT_Type *base) -{ - uint32_t i; - uint32_t pmcfg = 0; - uint8_t pintcount = 0; - assert(base != NULL); - - if (base == PINT) - { - pintcount = FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; - /* clear PINT callback array*/ - for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_pintCallback[i] = NULL; - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - pintcount = FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; - /* clear SECPINT callback array*/ - for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_secpintCallback[i] = NULL; - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - - /* Disable all bit slices for pint*/ - for (i = 0; i < pintcount; i++) - { - pmcfg = pmcfg | ((uint32_t)kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U))); - } - -#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_GpioInt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) - - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio_Sec); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - -#else - - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Pint); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } - else - { - /* if need config SECURE PINT device,then enable secure pint interrupt clock */ -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio_Sec_Int); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } -#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ - - /* Disable all pattern match bit slices */ - base->PMCFG = pmcfg; -} - -/*! - * brief Configure PINT peripheral pin interrupt. - - * This function configures a given pin interrupt. - * - * param base Base address of the PINT peripheral. - * param intr Pin interrupt. - * param enable Selects detection logic. - * param callback Callback. - * - * retval None. - */ -void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback) -{ - assert(base != NULL); - - /* Clear Rise and Fall flags first */ - PINT_PinInterruptClrRiseFlag(base, intr); - PINT_PinInterruptClrFallFlag(base, intr); - - /* Security PINT uses additional callback array */ - if (base == PINT) - { - s_pintCallback[intr] = callback; - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - s_secpintCallback[intr] = callback; -#endif - } - - /* select level or edge sensitive */ - base->ISEL = (base->ISEL & ~(1UL << (uint32_t)intr)) | - ((((uint32_t)enable & PINT_PIN_INT_LEVEL) != 0U) ? (1UL << (uint32_t)intr) : 0U); - - /* enable rising or level interrupt */ - if (((unsigned)enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE)) != 0U) - { - base->SIENR = 1UL << (uint32_t)intr; - } - else - { - base->CIENR = 1UL << (uint32_t)intr; - } - - /* Enable falling or select high level */ - if (((unsigned)enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL) != 0U) - { - base->SIENF = 1UL << (uint32_t)intr; - } - else - { - base->CIENF = 1UL << (uint32_t)intr; - } -} - -/*! - * brief Get PINT peripheral pin interrupt configuration. - - * This function returns the configuration of a given pin interrupt. - * - * param base Base address of the PINT peripheral. - * param pintr Pin interrupt. - * param enable Pointer to store the detection logic. - * param callback Callback. - * - * retval None. - */ -void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback) -{ - uint32_t mask; - bool level; - - assert(base != NULL); - - *enable = kPINT_PinIntEnableNone; - level = false; - - mask = 1UL << (uint32_t)pintr; - if ((base->ISEL & mask) != 0U) - { - /* Pin interrupt is level sensitive */ - level = true; - } - - if ((base->IENR & mask) != 0U) - { - if (level) - { - /* Level interrupt is enabled */ - *enable = kPINT_PinIntEnableLowLevel; - } - else - { - /* Rising edge interrupt */ - *enable = kPINT_PinIntEnableRiseEdge; - } - } - - if ((base->IENF & mask) != 0U) - { - if (level) - { - /* Level interrupt is active high */ - *enable = kPINT_PinIntEnableHighLevel; - } - else - { - /* Either falling or both edge */ - if (*enable == kPINT_PinIntEnableRiseEdge) - { - /* Rising and faling edge */ - *enable = kPINT_PinIntEnableBothEdges; - } - else - { - /* Falling edge */ - *enable = kPINT_PinIntEnableFallEdge; - } - } - } - - /* Security PINT uses additional callback array */ - if (base == PINT) - { - *callback = s_pintCallback[pintr]; - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - *callback = s_secpintCallback[pintr]; -#endif - } -} - -/*! - * brief Configure PINT pattern match. - - * This function configures a given pattern match bit slice. - * - * param base Base address of the PINT peripheral. - * param bslice Pattern match bit slice number. - * param cfg Pointer to bit slice configuration. - * - * retval None. - */ -void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) -{ - uint32_t src_shift; - uint32_t cfg_shift; - uint32_t pmcfg; - uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; - uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; - - assert(base != NULL); - - src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); - cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); - - /* Input source selection for selected bit slice */ - base->PMSRC = (base->PMSRC & ~(tmp_src_shift << src_shift)) | ((uint32_t)(cfg->bs_src) << src_shift); - - /* Bit slice configuration */ - pmcfg = base->PMCFG; - pmcfg = (pmcfg & ~(tmp_cfg_shift << cfg_shift)) | ((uint32_t)(cfg->bs_cfg) << cfg_shift); - - /* If end point is true, enable the bits */ - if ((uint32_t)bslice != 7UL) - { - if (cfg->end_point) - { - pmcfg |= (1UL << (uint32_t)bslice); - } - else - { - pmcfg &= ~(1UL << (uint32_t)bslice); - } - } - - base->PMCFG = pmcfg; - - /* Save callback pointer */ - if (base == PINT) - { - if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) - { - s_pintCallback[bslice] = cfg->callback; - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - { - s_secpintCallback[bslice] = cfg->callback; - } -#endif - } -} - -/*! - * brief Get PINT pattern match configuration. - - * This function returns the configuration of a given pattern match bit slice. - * - * param base Base address of the PINT peripheral. - * param bslice Pattern match bit slice number. - * param cfg Pointer to bit slice configuration. - * - * retval None. - */ -void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) -{ - uint32_t src_shift; - uint32_t cfg_shift; - uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; - uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; - - assert(base != NULL); - - src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); - cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); - - cfg->bs_src = (pint_pmatch_input_src_t)(uint32_t)((base->PMSRC & (tmp_src_shift << src_shift)) >> src_shift); - cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)(uint32_t)((base->PMCFG & (tmp_cfg_shift << cfg_shift)) >> cfg_shift); - - if ((uint32_t)bslice == 7U) - { - cfg->end_point = true; - } - else - { - cfg->end_point = (((base->PMCFG & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice) != 0U) ? true : false; - } - - if (base == PINT) - { - if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) - { - cfg->callback = s_pintCallback[bslice]; - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - { - cfg->callback = s_secpintCallback[bslice]; - } -#endif - } -} - -/*! - * brief Reset pattern match detection logic. - - * This function resets the pattern match detection logic if any of the product term is matching. - * - * param base Base address of the PINT peripheral. - * - * retval pmstatus Each bit position indicates the match status of corresponding bit slice. - * = 0 Match was detected. = 1 Match was not detected. - */ -uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base) -{ - uint32_t pmctrl; - uint32_t pmstatus; - uint32_t pmsrc; - - pmctrl = base->PMCTRL; - pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT; - if (pmstatus != 0UL) - { - /* Reset Pattern match engine detection logic */ - pmsrc = base->PMSRC; - base->PMSRC = pmsrc; - } - return (pmstatus); -} - -/*! - * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. - - * This function clears the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr) -{ - uint32_t pinIntMode = base->ISEL & (1UL << (uint32_t)pintr); - uint32_t pinIntStatus = base->IST & (1UL << (uint32_t)pintr); - - /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ - if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) - { - base->IST = (1UL << (uint32_t)pintr); - } -} - -/*! - * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. - - * This function clears the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_PinInterruptClrStatusAll(PINT_Type *base) -{ - uint32_t pinIntMode = 0; - uint32_t pinIntStatus = 0; - uint32_t pinIntCount = 0; - uint32_t mask = 0; - uint32_t i; - - if (base == PINT) - { - pinIntCount = (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - pinIntCount = (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - - for (i = 0; i < pinIntCount; i++) - { - pinIntMode = base->ISEL & (1UL << i); - pinIntStatus = base->IST & (1UL << i); - - /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ - if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) - { - mask |= 1UL << i; - } - } - - base->IST = mask; -} - -/*! - * brief Enable callback. - - * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * param base Base address of the PINT peripheral. - * - * retval None. - */ -void PINT_EnableCallback(PINT_Type *base) -{ - uint32_t i; - - assert(base != NULL); - - if (base == PINT) - { - for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i]); - (void)EnableIRQ(s_pintIRQ[i]); - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - (void)EnableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } -} - -/*! - * brief enable callback by pin index. - - * This function enables callback by pin index instead of enabling all pins. - * - * param base Base address of the peripheral. - * param pinIdx pin index. - * - * retval None. - */ -void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) -{ - assert(base != NULL); - - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); - -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - /* Get the right security pint irq index in array */ - if (base == SECPINT) - { - pintIdx = - (pint_pin_int_t)(uint32_t)((uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS); - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - - NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); - (void)EnableIRQ(s_pintIRQ[pintIdx]); -} - -/*! - * brief Disable callback. - - * This function disables the interrupt for the selected PINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * param base Base address of the peripheral. - * - * retval None. - */ -void PINT_DisableCallback(PINT_Type *base) -{ - uint32_t i; - - assert(base != NULL); - - if (base == PINT) - { - for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - (void)DisableIRQ(s_pintIRQ[i]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i]); - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - (void)DisableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } -} - -/*! - * brief disable callback by pin index. - - * This function disables callback by pin index instead of disabling all pins. - * - * param base Base address of the peripheral. - * param pinIdx pin index. - * - * retval None. - */ -void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) -{ - assert(base != NULL); - - if (base == PINT) - { - (void)DisableIRQ(s_pintIRQ[pintIdx]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); - NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - (void)DisableIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); - NVIC_ClearPendingIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); -#endif - } -} - -/*! - * brief Deinitialize PINT peripheral. - - * This function disables the PINT clock. - * - * param base Base address of the PINT peripheral. - * - * retval None. - */ -void PINT_Deinit(PINT_Type *base) -{ - uint32_t i; - - assert(base != NULL); - - /* Cleanup */ - PINT_DisableCallback(base); - if (base == PINT) - { - /* clear PINT callback array*/ - for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_pintCallback[i] = NULL; - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - /* clear SECPINT callback array */ - for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_secpintCallback[i] = NULL; - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - -#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_GpioInt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) - - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio_Sec); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - -#else - - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Pint); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } - else - { - /* if need config SECURE PINT device,then enable secure pint interrupt clock */ -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio_Sec_Int); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } -#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ -} -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -/* IRQ handler functions overloading weak symbols in the startup */ -void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void); -void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void) -{ - uint32_t pmstatus = 0; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); - /* Call user function */ - if (s_secpintCallback[kPINT_SecPinInt0] != NULL) - { - s_secpintCallback[kPINT_SecPinInt0](kPINT_SecPinInt0, pmstatus); - } - if ((SECPINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt0); - } - SDK_ISR_EXIT_BARRIER; -} - -#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) -/* IRQ handler functions overloading weak symbols in the startup */ -void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void); -void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); - /* Call user function */ - if (s_secpintCallback[kPINT_SecPinInt1] != NULL) - { - s_secpintCallback[kPINT_SecPinInt1](kPINT_SecPinInt1, pmstatus); - } - if ((SECPINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt1); - } - SDK_ISR_EXIT_BARRIER; -} -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - -/* IRQ handler functions overloading weak symbols in the startup */ -void PIN_INT0_DriverIRQHandler(void); -void PIN_INT0_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt0] != NULL) - { - s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus); - } - if ((PINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); - } - SDK_ISR_EXIT_BARRIER; -} - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) -void PIN_INT1_DriverIRQHandler(void); -void PIN_INT1_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt1] != NULL) - { - s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus); - } - if ((PINT->ISEL & 0x2U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) -void PIN_INT2_DriverIRQHandler(void); -void PIN_INT2_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt2] != NULL) - { - s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus); - } - if ((PINT->ISEL & 0x4U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) -void PIN_INT3_DriverIRQHandler(void); -void PIN_INT3_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt3] != NULL) - { - s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus); - } - if ((PINT->ISEL & 0x8U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) -void PIN_INT4_DriverIRQHandler(void); -void PIN_INT4_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt4] != NULL) - { - s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus); - } - if ((PINT->ISEL & 0x10U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT5_DAC1_IRQHandler(void); -void PIN_INT5_DAC1_IRQHandler(void) -#else -void PIN_INT5_DriverIRQHandler(void); -void PIN_INT5_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt5] != NULL) - { - s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus); - } - if ((PINT->ISEL & 0x20U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT6_USART3_IRQHandler(void); -void PIN_INT6_USART3_IRQHandler(void) -#else -void PIN_INT6_DriverIRQHandler(void); -void PIN_INT6_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt6] != NULL) - { - s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus); - } - if ((PINT->ISEL & 0x40U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT7_USART4_IRQHandler(void); -void PIN_INT7_USART4_IRQHandler(void) -#else -void PIN_INT7_DriverIRQHandler(void); -void PIN_INT7_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt7] != NULL) - { - s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus); - } - if ((PINT->ISEL & 0x80U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7); - } - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_pint.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_pint.h deleted file mode 100644 index eb7ed612b92..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_pint.h +++ /dev/null @@ -1,581 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_PINT_H_ -#define _FSL_PINT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup pint_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 1, 9)) /*!< Version 2.1.9 */ -/*@}*/ - -/* Number of interrupt line supported by PINT */ -#define PINT_PIN_INT_COUNT 8U - -/* Number of interrupt line supported by SECURE PINT */ -#define SEC_PINT_PIN_INT_COUNT 2U - -/* Number of input sources supported by PINT */ -#define PINT_INPUT_COUNT 8U - -/* PININT Bit slice source register bits */ -#define PININT_BITSLICE_SRC_START 8U -#define PININT_BITSLICE_SRC_MASK 7U - -/* PININT Bit slice configuration register bits */ -#define PININT_BITSLICE_CFG_START 8U -#define PININT_BITSLICE_CFG_MASK 7U -#define PININT_BITSLICE_ENDP_MASK 7U - -#define PINT_PIN_INT_LEVEL 0x10U -#define PINT_PIN_INT_EDGE 0x00U -#define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U -#define PINT_PIN_INT_RISE 0x01U -#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE) -#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) -#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) -#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL) -#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) - -/*! @brief PINT Pin Interrupt enable type */ -typedef enum _pint_pin_enable -{ - kPINT_PinIntEnableNone = 0U, /*!< Do not generate Pin Interrupt */ - kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE, /*!< Generate Pin Interrupt on rising edge */ - kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE, /*!< Generate Pin Interrupt on falling edge */ - kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */ - kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL, /*!< Generate Pin Interrupt on low level */ - kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */ -} pint_pin_enable_t; - -/*! @brief PINT Pin Interrupt type */ -typedef enum _pint_int -{ - kPINT_PinInt0 = 0U, /*!< Pin Interrupt 0 */ -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_PinInt1 = 1U, /*!< Pin Interrupt 1 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) - kPINT_PinInt2 = 2U, /*!< Pin Interrupt 2 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) - kPINT_PinInt3 = 3U, /*!< Pin Interrupt 3 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) - kPINT_PinInt4 = 4U, /*!< Pin Interrupt 4 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) - kPINT_PinInt5 = 5U, /*!< Pin Interrupt 5 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) - kPINT_PinInt6 = 6U, /*!< Pin Interrupt 6 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) - kPINT_PinInt7 = 7U, /*!< Pin Interrupt 7 */ -#endif -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) - kPINT_SecPinInt0 = 0U, /*!< Secure Pin Interrupt 0 */ -#endif -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_SecPinInt1 = 1U, /*!< Secure Pin Interrupt 1 */ -#endif -} pint_pin_int_t; - -/*! @brief PINT Pattern Match bit slice input source type */ -typedef enum _pint_pmatch_input_src -{ - kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */ - kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */ - kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */ - kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */ - kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */ - kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */ - kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */ - kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */ - kPINT_SecPatternMatchInp0Src = 0U, /*!< Input source 0 */ - kPINT_SecPatternMatchInp1Src = 1U, /*!< Input source 1 */ -} pint_pmatch_input_src_t; - -/*! @brief PINT Pattern Match bit slice type */ -typedef enum _pint_pmatch_bslice -{ - kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) - kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) - kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) - kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) - kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) - kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) - kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */ -#endif -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) - kPINT_SecPatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ -#endif -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_SecPatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ -#endif -} pint_pmatch_bslice_t; - -/*! @brief PINT Pattern Match configuration type */ -typedef enum _pint_pmatch_bslice_cfg -{ - kPINT_PatternMatchAlways = 0U, /*!< Always Contributes to product term match */ - kPINT_PatternMatchStickyRise = 1U, /*!< Sticky Rising edge */ - kPINT_PatternMatchStickyFall = 2U, /*!< Sticky Falling edge */ - kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */ - kPINT_PatternMatchHigh = 4U, /*!< High level */ - kPINT_PatternMatchLow = 5U, /*!< Low level */ - kPINT_PatternMatchNever = 6U, /*!< Never contributes to product term match */ - kPINT_PatternMatchBothEdges = 7U, /*!< Either rising or falling edge */ -} pint_pmatch_bslice_cfg_t; - -/*! @brief PINT Callback function. */ -typedef void (*pint_cb_t)(pint_pin_int_t pintr, uint32_t pmatch_status); - -typedef struct _pint_pmatch_cfg -{ - pint_pmatch_input_src_t bs_src; - pint_pmatch_bslice_cfg_t bs_cfg; - bool end_point; - pint_cb_t callback; -} pint_pmatch_cfg_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize PINT peripheral. - - * This function initializes the PINT peripheral and enables the clock. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_Init(PINT_Type *base); - -/*! - * @brief Configure PINT peripheral pin interrupt. - - * This function configures a given pin interrupt. - * - * @param base Base address of the PINT peripheral. - * @param intr Pin interrupt. - * @param enable Selects detection logic. - * @param callback Callback. - * - * @retval None. - */ -void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback); - -/*! - * @brief Get PINT peripheral pin interrupt configuration. - - * This function returns the configuration of a given pin interrupt. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * @param enable Pointer to store the detection logic. - * @param callback Callback. - * - * @retval None. - */ -void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback); - -/*! - * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. - - * This function clears the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr); - -/*! - * @brief Get Selected pin interrupt status. - - * This function returns the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval status = 0 No pin interrupt request. = 1 Selected Pin interrupt request active. - */ -static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->IST & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. - - * This function clears the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_PinInterruptClrStatusAll(PINT_Type *base); - -/*! - * @brief Get all pin interrupts status. - - * This function returns the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval status Each bit position indicates the status of corresponding pin interrupt. - * = 0 No pin interrupt request. = 1 Pin interrupt request active. - */ -static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base) -{ - return (base->IST); -} - -/*! - * @brief Clear Selected pin interrupt fall flag. - - * This function clears the selected pin interrupt fall flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - base->FALL = (1UL << (uint32_t)pintr); -} - -/*! - * @brief Get selected pin interrupt fall flag. - - * This function returns the selected pin interrupt fall flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval flag = 0 Falling edge has not been detected. = 1 Falling edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->FALL & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupt fall flags. - - * This function clears the fall flag for all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base) -{ - base->FALL = PINT_FALL_FDET_MASK; -} - -/*! - * @brief Get all pin interrupt fall flags. - - * This function returns the fall flag of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval flags Each bit position indicates the falling edge detection of the corresponding pin interrupt. - * 0 Falling edge has not been detected. = 1 Falling edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base) -{ - return (base->FALL); -} - -/*! - * @brief Clear Selected pin interrupt rise flag. - - * This function clears the selected pin interrupt rise flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - base->RISE = (1UL << (uint32_t)pintr); -} - -/*! - * @brief Get selected pin interrupt rise flag. - - * This function returns the selected pin interrupt rise flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval flag = 0 Rising edge has not been detected. = 1 Rising edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->RISE & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupt rise flags. - - * This function clears the rise flag for all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base) -{ - base->RISE = PINT_RISE_RDET_MASK; -} - -/*! - * @brief Get all pin interrupt rise flags. - - * This function returns the rise flag of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval flags Each bit position indicates the rising edge detection of the corresponding pin interrupt. - * 0 Rising edge has not been detected. = 1 Rising edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base) -{ - return (base->RISE); -} - -/*! - * @brief Configure PINT pattern match. - - * This function configures a given pattern match bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * @param cfg Pointer to bit slice configuration. - * - * @retval None. - */ -void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); - -/*! - * @brief Get PINT pattern match configuration. - - * This function returns the configuration of a given pattern match bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * @param cfg Pointer to bit slice configuration. - * - * @retval None. - */ -void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); - -/*! - * @brief Get pattern match bit slice status. - - * This function returns the status of selected bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * - * @retval status = 0 Match has not been detected. = 1 Match has been detected. - */ -static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_bslice_t bslice) -{ - return ((base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT) & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice; -} - -/*! - * @brief Get status of all pattern match bit slices. - - * This function returns the status of all bit slices. - * - * @param base Base address of the PINT peripheral. - * - * @retval status Each bit position indicates the match status of corresponding bit slice. - * = 0 Match has not been detected. = 1 Match has been detected. - */ -static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base) -{ - return base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT; -} - -/*! - * @brief Reset pattern match detection logic. - - * This function resets the pattern match detection logic if any of the product term is matching. - * - * @param base Base address of the PINT peripheral. - * - * @retval pmstatus Each bit position indicates the match status of corresponding bit slice. - * = 0 Match was detected. = 1 Match was not detected. - */ -uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base); - -/*! - * @brief Enable pattern match function. - - * This function enables the pattern match function. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchEnable(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) | PINT_PMCTRL_SEL_PMATCH_MASK; -} - -/*! - * @brief Disable pattern match function. - - * This function disables the pattern match function. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchDisable(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) & ~PINT_PMCTRL_SEL_PMATCH_MASK; -} - -/*! - * @brief Enable RXEV output. - - * This function enables the pattern match RXEV output. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) | PINT_PMCTRL_ENA_RXEV_MASK; -} - -/*! - * @brief Disable RXEV output. - - * This function disables the pattern match RXEV output. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) & ~PINT_PMCTRL_ENA_RXEV_MASK; -} - -/*! - * @brief Enable callback. - - * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_EnableCallback(PINT_Type *base); - -/*! - * @brief Disable callback. - - * This function disables the interrupt for the selected PINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * @param base Base address of the peripheral. - * - * @retval None. - */ -void PINT_DisableCallback(PINT_Type *base); - -/*! - * @brief Deinitialize PINT peripheral. - - * This function disables the PINT clock. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_Deinit(PINT_Type *base); - -/*! - * @brief enable callback by pin index. - - * This function enables callback by pin index instead of enabling all pins. - * - * @param base Base address of the peripheral. - * @param pintIdx pin index. - * - * @retval None. - */ -void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); - -/*! - * @brief disable callback by pin index. - - * This function disables callback by pin index instead of disabling all pins. - * - * @param base Base address of the peripheral. - * @param pintIdx pin index. - * - * @retval None. - */ -void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_PINT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_plu.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_plu.c deleted file mode 100644 index b50f472675e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_plu.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_plu.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.plu" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Gets the instance from the base address - * - * @param base PLU peripheral base address - * - * @return The PLU instance - */ -static uint32_t PLU_GetInstance(PLU_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to PLU bases for each instance. */ -static PLU_Type *const s_pluBases[] = PLU_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to PLU clocks for each instance. */ -static const clock_ip_name_t s_pluClocks[] = PLU_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -/*! @brief Pointers to PLU resets for each instance. */ -static const reset_ip_name_t s_lpuResets[] = PLU_RSTS_N; -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t PLU_GetInstance(PLU_Type *base) -{ - uint32_t instance; - uint32_t pluArrayCount = (sizeof(s_pluBases) / sizeof(s_pluBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < pluArrayCount; instance++) - { - if (s_pluBases[instance] == base) - { - break; - } - } - - assert(instance < pluArrayCount); - - return instance; -} - -/*! - * brief Ungates the PLU clock and reset the module. - * - * note This API should be called at the beginning of the application using the PLU driver. - * - * param base PLU peripheral base address - */ -void PLU_Init(PLU_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the PLU peripheral clock */ - CLOCK_EnableClock(s_pluClocks[PLU_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_lpuResets[PLU_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -} - -/*! - * brief Gate the PLU clock - * - * param base PLU peripheral base address - */ -void PLU_Deinit(PLU_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the module clock */ - CLOCK_DisableClock((s_pluClocks[PLU_GetInstance(base)])); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -#if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG -/*! - * @brief Gets an available pre-defined settings for wakeup/interrupt control. - * - * This function initializes the initial configuration structure with an available settings. The default values are: - * @code - * config->filterMode = kPLU_WAKEINT_FILTER_MODE_BYPASS; - * config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC; - * @endcode - * @param config Pointer to configuration structure. - */ -void PLU_GetDefaultWakeIntConfig(plu_wakeint_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->filterMode = kPLU_WAKEINT_FILTER_MODE_BYPASS; - config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC; -} - -/*! - * @brief Enable PLU outputs wakeup/interrupt request. - * - * This function enables Any of the eight selected PLU outputs to contribute to an asynchronous wake-up or an interrupt - * request. - * - * Note: If a PLU_CLKIN is provided, the raw wake-up/interrupt request will be set on the rising-edge of the PLU_CLKIN - * whenever the raw request signal is high. This registered signal will be glitch-free and just use the default wakeint - * config by PLU_GetDefaultWakeIntConfig(). If not, have to specify the filter mode and clock source to eliminate the - * glitches caused by long and widely disparate delays through the network of LUTs making up the PLU. This way may - * increase power consumption in low-power operating modes and inject delay before the wake-up/interrupt request is - * generated. - * - * @param base PLU peripheral base address. - * @param interruptMask PLU interrupt mask (see @ref _plu_interrupt_mask enumeration). - * @param config Pointer to configuration structure (see @ref plu_wakeint_config_t typedef enumeration) - */ -void PLU_EnableWakeIntRequest(PLU_Type *base, uint32_t interruptMask, const plu_wakeint_config_t *config) -{ - uint32_t tmp32 = 0U; - - tmp32 = PLU_WAKEINT_CTRL_FILTER_MODE(config->filterMode) | PLU_WAKEINT_CTRL_FILTER_CLKSEL(config->clockSource) | - PLU_WAKEINT_CTRL_MASK(interruptMask); - - base->WAKEINT_CTRL = tmp32; -} - -/*! - * @brief Clear the latched interrupt - * - * This function clears the wake-up/interrupt request flag latched by PLU_LatchInterrupt() - * - * Note: It is not necessary for the PLU bus clock to be enabled in order to write-to or read-back this bit. - * - * @param base PLU peripheral base address. - */ -void PLU_ClearLatchedInterrupt(PLU_Type *base) -{ - base->WAKEINT_CTRL |= PLU_WAKEINT_CTRL_INTR_CLEAR_MASK; - /* It will take a delay of up to 1.5 PLU_CLKIN clock cycles before this write-to-clear takes effect. */ - while (PLU_WAKEINT_CTRL_INTR_CLEAR_MASK == (base->WAKEINT_CTRL & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK)) - { - } -} -#endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_plu.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_plu.h deleted file mode 100644 index 0c94d49091d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_plu.h +++ /dev/null @@ -1,374 +0,0 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_PLU_H_ -#define _FSL_PLU_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup plu - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_PLU_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1 */ - /*@}*/ - -/*! @brief Index of LUT */ -typedef enum _plu_lut_index -{ - kPLU_LUT_0 = 0U, /*!< 5-input Look-up Table 0 */ - kPLU_LUT_1 = 1U, /*!< 5-input Look-up Table 1 */ - kPLU_LUT_2 = 2U, /*!< 5-input Look-up Table 2 */ - kPLU_LUT_3 = 3U, /*!< 5-input Look-up Table 3 */ - kPLU_LUT_4 = 4U, /*!< 5-input Look-up Table 4 */ - kPLU_LUT_5 = 5U, /*!< 5-input Look-up Table 5 */ - kPLU_LUT_6 = 6U, /*!< 5-input Look-up Table 6 */ - kPLU_LUT_7 = 7U, /*!< 5-input Look-up Table 7 */ - kPLU_LUT_8 = 8U, /*!< 5-input Look-up Table 8 */ - kPLU_LUT_9 = 9U, /*!< 5-input Look-up Table 9 */ - kPLU_LUT_10 = 10U, /*!< 5-input Look-up Table 10 */ - kPLU_LUT_11 = 11U, /*!< 5-input Look-up Table 11 */ - kPLU_LUT_12 = 12U, /*!< 5-input Look-up Table 12 */ - kPLU_LUT_13 = 13U, /*!< 5-input Look-up Table 13 */ - kPLU_LUT_14 = 14U, /*!< 5-input Look-up Table 14 */ - kPLU_LUT_15 = 15U, /*!< 5-input Look-up Table 15 */ - kPLU_LUT_16 = 16U, /*!< 5-input Look-up Table 16 */ - kPLU_LUT_17 = 17U, /*!< 5-input Look-up Table 17 */ - kPLU_LUT_18 = 18U, /*!< 5-input Look-up Table 18 */ - kPLU_LUT_19 = 19U, /*!< 5-input Look-up Table 19 */ - kPLU_LUT_20 = 20U, /*!< 5-input Look-up Table 20 */ - kPLU_LUT_21 = 21U, /*!< 5-input Look-up Table 21 */ - kPLU_LUT_22 = 22U, /*!< 5-input Look-up Table 22 */ - kPLU_LUT_23 = 23U, /*!< 5-input Look-up Table 23 */ - kPLU_LUT_24 = 24U, /*!< 5-input Look-up Table 24 */ - kPLU_LUT_25 = 25U /*!< 5-input Look-up Table 25 */ -} plu_lut_index_t; - -/*! @brief Inputs of LUT. 5 input present for each LUT. */ -typedef enum _plu_lut_in_index -{ - kPLU_LUT_IN_0 = 0U, /*!< LUT input 0 */ - kPLU_LUT_IN_1 = 1U, /*!< LUT input 1 */ - kPLU_LUT_IN_2 = 2U, /*!< LUT input 2 */ - kPLU_LUT_IN_3 = 3U, /*!< LUT input 3 */ - kPLU_LUT_IN_4 = 4U /*!< LUT input 4 */ -} plu_lut_in_index_t; - -/*! @brief Available sources of LUT input */ -typedef enum _plu_lut_input_source -{ - kPLU_LUT_IN_SRC_PLU_IN_0 = 0U, /*!< Select PLU input 0 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_1 = 1U, /*!< Select PLU input 1 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_2 = 2U, /*!< Select PLU input 2 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_3 = 3U, /*!< Select PLU input 3 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_4 = 4U, /*!< Select PLU input 4 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_5 = 5U, /*!< Select PLU input 5 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_0 = 6U, /*!< Select LUT output 0 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_1 = 7U, /*!< Select LUT output 1 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_2 = 8U, /*!< Select LUT output 2 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_3 = 9U, /*!< Select LUT output 3 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_4 = 10U, /*!< Select LUT output 4 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_5 = 11U, /*!< Select LUT output 5 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_6 = 12U, /*!< Select LUT output 6 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_7 = 13U, /*!< Select LUT output 7 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_8 = 14U, /*!< Select LUT output 8 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_9 = 15U, /*!< Select LUT output 9 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_10 = 16U, /*!< Select LUT output 10 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_11 = 17U, /*!< Select LUT output 11 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_12 = 18U, /*!< Select LUT output 12 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_13 = 19U, /*!< Select LUT output 13 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_14 = 20U, /*!< Select LUT output 14 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_15 = 21U, /*!< Select LUT output 15 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_16 = 22U, /*!< Select LUT output 16 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_17 = 23U, /*!< Select LUT output 17 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_18 = 24U, /*!< Select LUT output 18 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_19 = 25U, /*!< Select LUT output 19 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_20 = 26U, /*!< Select LUT output 20 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_21 = 27U, /*!< Select LUT output 21 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_22 = 28U, /*!< Select LUT output 22 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_23 = 29U, /*!< Select LUT output 23 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_24 = 30U, /*!< Select LUT output 24 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_25 = 31U, /*!< Select LUT output 25 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_FLIPFLOP_0 = 32U, /*!< Select Flip-Flops state 0 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_FLIPFLOP_1 = 33U, /*!< Select Flip-Flops state 1 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_FLIPFLOP_2 = 34U, /*!< Select Flip-Flops state 2 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_FLIPFLOP_3 = 35U /*!< Select Flip-Flops state 3 to be connected to LUTn Input x */ -} plu_lut_input_source_t; - -/*! @brief PLU output multiplexer registers */ -typedef enum _plu_output_index -{ - kPLU_OUTPUT_0 = 0U, /*!< PLU OUTPUT 0 */ - kPLU_OUTPUT_1 = 1U, /*!< PLU OUTPUT 1 */ - kPLU_OUTPUT_2 = 2U, /*!< PLU OUTPUT 2 */ - kPLU_OUTPUT_3 = 3U, /*!< PLU OUTPUT 3 */ - kPLU_OUTPUT_4 = 4U, /*!< PLU OUTPUT 4 */ - kPLU_OUTPUT_5 = 5U, /*!< PLU OUTPUT 5 */ - kPLU_OUTPUT_6 = 6U, /*!< PLU OUTPUT 6 */ - kPLU_OUTPUT_7 = 7U /*!< PLU OUTPUT 7 */ -} plu_output_index_t; - -/*! @brief Available sources of PLU output */ -typedef enum _plu_output_source -{ - kPLU_OUT_SRC_LUT_0 = 0U, /*!< Select LUT0 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_1 = 1U, /*!< Select LUT1 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_2 = 2U, /*!< Select LUT2 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_3 = 3U, /*!< Select LUT3 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_4 = 4U, /*!< Select LUT4 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_5 = 5U, /*!< Select LUT5 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_6 = 6U, /*!< Select LUT6 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_7 = 7U, /*!< Select LUT7 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_8 = 8U, /*!< Select LUT8 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_9 = 9U, /*!< Select LUT9 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_10 = 10U, /*!< Select LUT10 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_11 = 11U, /*!< Select LUT11 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_12 = 12U, /*!< Select LUT12 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_13 = 13U, /*!< Select LUT13 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_14 = 14U, /*!< Select LUT14 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_15 = 15U, /*!< Select LUT15 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_16 = 16U, /*!< Select LUT16 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_17 = 17U, /*!< Select LUT17 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_18 = 18U, /*!< Select LUT18 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_19 = 19U, /*!< Select LUT19 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_20 = 20U, /*!< Select LUT20 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_21 = 21U, /*!< Select LUT21 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_22 = 22U, /*!< Select LUT22 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_23 = 23U, /*!< Select LUT23 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_24 = 24U, /*!< Select LUT24 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_25 = 25U, /*!< Select LUT25 output to be connected to PLU output */ - kPLU_OUT_SRC_FLIPFLOP_0 = 26U, /*!< Select Flip-Flops state(0) to be connected to PLU output */ - kPLU_OUT_SRC_FLIPFLOP_1 = 27U, /*!< Select Flip-Flops state(1) to be connected to PLU output */ - kPLU_OUT_SRC_FLIPFLOP_2 = 28U, /*!< Select Flip-Flops state(2) to be connected to PLU output */ - kPLU_OUT_SRC_FLIPFLOP_3 = 29U /*!< Select Flip-Flops state(3) to be connected to PLU output */ -} plu_output_source_t; - -#if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG - -/*! @brief The enumerator of PLU Interrupt. */ -enum _plu_interrupt_mask -{ - kPLU_OUTPUT_0_INTERRUPT_MASK = 1 << 0, /*!< Select PLU output 0 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_1_INTERRUPT_MASK = 1 << 1, /*!< Select PLU output 1 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_2_INTERRUPT_MASK = 1 << 2, /*!< Select PLU output 2 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_3_INTERRUPT_MASK = 1 << 3, /*!< Select PLU output 3 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_4_INTERRUPT_MASK = 1 << 4, /*!< Select PLU output 4 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_5_INTERRUPT_MASK = 1 << 5, /*!< Select PLU output 5 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_6_INTERRUPT_MASK = 1 << 6, /*!< Select PLU output 6 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_7_INTERRUPT_MASK = 1 << 7 /*!< Select PLU output 7 contribute to interrupt/wake-up generation */ -}; - -/*! @brief Control input of the PLU, add filtering for glitch. */ -typedef enum _plu_wakeint_filter_mode -{ - kPLU_WAKEINT_FILTER_MODE_BYPASS = 0U, /*!< Select Bypass mode */ - kPLU_WAKEINT_FILTER_MODE_1_CLK_PERIOD = 1U, /*!< Filter 1 clock period */ - kPLU_WAKEINT_FILTER_MODE_2_CLK_PERIOD = 2U, /*!< Filter 2 clock period */ - kPLU_WAKEINT_FILTER_MODE_3_CLK_PERIOD = 3U /*!< Filter 3 clock period */ -} plu_wakeint_filter_mode_t; - -/*! @brief Clock source for filter mode. */ -typedef enum _plu_wakeint_filter_clock_source -{ - kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC = 0U, /*!< Select the 1MHz low-power oscillator as the filter clock */ - kPLU_WAKEINT_FILTER_CLK_SRC_12MHZ_FRO = 1U, /*!< Select the 12MHz FRO as the filer clock */ - kPLU_WAKEINT_FILTER_CLK_SRC_ALT = 2U /*!< Select a third clock source */ -} plu_wakeint_filter_clock_source_t; - -/*! @brief Wake configuration. */ -typedef struct _plu_wakeint_config -{ - plu_wakeint_filter_mode_t filterMode; /*!< Filter Mode. */ - plu_wakeint_filter_clock_source_t clockSource; /*!< The clock source for filter mode. */ -} plu_wakeint_config_t; -#endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Enable the PLU clock and reset the module. - * - * @note This API should be called at the beginning of the application using the PLU driver. - * - * @param base PLU peripheral base address - */ -void PLU_Init(PLU_Type *base); - -/*! - * @brief Gate the PLU clock - * - * @param base PLU peripheral base address - */ -void PLU_Deinit(PLU_Type *base); - -/*! @}*/ - -/*! - * @name Set input/output source and Truth Table - * @{ - */ - -/*! - * @brief Set Input source of LUT. - * - * Note: An external clock must be applied to the PLU_CLKIN input when using FFs. - * For each LUT, the slot associated with the output from LUTn itself is tied low. - * - * @param base PLU peripheral base address. - * @param lutIndex LUT index (see @ref plu_lut_index_t typedef enumeration). - * @param lutInIndex LUT input index (see @ref plu_lut_in_index_t typedef enumeration). - * @param inputSrc LUT input source (see @ref plu_lut_input_source_t typedef enumeration). - */ -static inline void PLU_SetLutInputSource(PLU_Type *base, - plu_lut_index_t lutIndex, - plu_lut_in_index_t lutInIndex, - plu_lut_input_source_t inputSrc) -{ - PLU->LUT[lutIndex].INP_MUX[lutInIndex] = (uint32_t)inputSrc; -} - -/*! - * @brief Set Output source of PLU. - * - * Note: An external clock must be applied to the PLU_CLKIN input when using FFs. - * - * @param base PLU peripheral base address. - * @param outputIndex PLU output index (see @ref plu_output_index_t typedef enumeration). - * @param outputSrc PLU output source (see @ref plu_output_source_t typedef enumeration). - */ -static inline void PLU_SetOutputSource(PLU_Type *base, plu_output_index_t outputIndex, plu_output_source_t outputSrc) -{ - base->OUTPUT_MUX[outputIndex] = (uint32_t)outputSrc; -} - -/*! - * @brief Set Truth Table of LUT. - * - * @param base PLU peripheral base address. - * @param lutIndex LUT index (see @ref plu_lut_index_t typedef enumeration). - * @param truthTable Truth Table value. - */ -static inline void PLU_SetLutTruthTable(PLU_Type *base, plu_lut_index_t lutIndex, uint32_t truthTable) -{ - base->LUT_TRUTH[lutIndex] = truthTable; -} - -/*! @}*/ - -/*! - * @name Read current Output State - * @{ - */ - -/*! - * @brief Read the current state of the 8 designated PLU Outputs. - * - * Note: The PLU bus clock must be re-enabled prior to reading the Outpus Register if PLU bus clock is - * shut-off. - * - * @param base PLU peripheral base address. - * @return Current PLU output state value. - */ -static inline uint32_t PLU_ReadOutputState(PLU_Type *base) -{ - return (base->OUTPUTS & PLU_OUTPUTS_OUTPUT_STATE_MASK); -} - -/*! @}*/ - -#if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG -/*! - * @name Wake-up/Interrupt Control - * @{ - */ - -/*! - * @brief Gets an available pre-defined settings for wakeup/interrupt control. - * - * This function initializes the initial configuration structure with an available settings. The default values are: - * @code - * config->filterMode = kPLU_WAKEINT_FILTER_MODE_BYPASS; - * config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC; - * @endcode - * @param config Pointer to configuration structure. - */ -void PLU_GetDefaultWakeIntConfig(plu_wakeint_config_t *config); - -/*! - * @brief Enable PLU outputs wakeup/interrupt request. - * - * This function enables Any of the eight selected PLU outputs to contribute to an asynchronous wake-up or an interrupt - * request. - * - * Note: If a PLU_CLKIN is provided, the raw wake-up/interrupt request will be set on the rising-edge of the PLU_CLKIN - * whenever the raw request signal is high. This registered signal will be glitch-free and just use the default wakeint - * config by PLU_GetDefaultWakeIntConfig(). If not, have to specify the filter mode and clock source to eliminate the - * glitches caused by long and widely disparate delays through the network of LUTs making up the PLU. This way may - * increase power consumption in low-power operating modes and inject delay before the wake-up/interrupt request is - * generated. - * - * @param base PLU peripheral base address. - * @param interruptMask PLU interrupt mask (see @ref _plu_interrupt_mask enumeration). - * @param config Pointer to configuration structure (see @ref plu_wakeint_config_t typedef enumeration) - */ -void PLU_EnableWakeIntRequest(PLU_Type *base, uint32_t interruptMask, const plu_wakeint_config_t *config); - -/*! - * @brief Latch an interrupt - * - * This function latches the interrupt and then it can be cleared with PLU_ClearLatchedInterrupt(). - * - * Note: This mode is not compatible with use of the glitch filter. If this bit is set, the FILTER MODE should be set - * to kPLU_WAKEINT_FILTER_MODE_BYPASS (Bypass Mode) and PLU_CLKIN should be provided. If this bit is set, the - * wake-up/interrupt request will be set on the rising-edge of PLU_CLKIN whenever the raw wake-up/interrupt signal is - * high. The request must be cleared by software. - * - * @param base PLU peripheral base address. - */ -static inline void PLU_LatchInterrupt(PLU_Type *base) -{ - base->WAKEINT_CTRL |= PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK; -} - -/*! - * @brief Clear the latched interrupt - * - * This function clears the wake-up/interrupt request flag latched by PLU_LatchInterrupt() - * - * Note: It is not necessary for the PLU bus clock to be enabled in order to write-to or read-back this bit. - * - * @param base PLU peripheral base address. - */ -void PLU_ClearLatchedInterrupt(PLU_Type *base); - -/*! @}*/ -#endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_PLU_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_power.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_power.c deleted file mode 100644 index f5204543836..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_power.c +++ /dev/null @@ -1,1831 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_common.h" -#include "fsl_power.h" -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.power" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/** @brief Low Power main structure */ -typedef enum -{ - VD_AON = 0x0, /*!< Digital Always On power domain */ - VD_MEM = 0x1, /*!< Memories (SRAM) power domain */ - VD_DCDC = 0x2, /*!< Core logic power domain */ - VD_DEEPSLEEP = 0x3 /*!< Core logic power domain */ -} LPC_POWER_DOMAIN_T; - -/** - * @brief LDO_FLASH_NV & LDO_USB voltage settings - */ -typedef enum _v_flashnv -{ - V_LDOFLASHNV_1P650 = 0, /*!< 0.95 V */ - V_LDOFLASHNV_1P700 = 1, /*!< 0.975 V */ - V_LDOFLASHNV_1P750 = 2, /*!< 1 V */ - V_LDOFLASHNV_0P800 = 3, /*!< 1.025 V */ - V_LDOFLASHNV_1P850 = 4, /*!< 1.050 V */ - V_LDOFLASHNV_1P900 = 5, /*!< 1.075 V */ - V_LDOFLASHNV_1P950 = 6, /*!< 1.1 V */ - V_LDOFLASHNV_2P000 = 7 /*!< 1.125 V */ -} v_flashnv_t; - -/** @brief Low Power main structure */ -typedef struct -{ /* */ - __IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */ - __IO uint32_t PDCTRL0; /*!< Power Down control : controls power of various modules - in the different Low power modes, including ROM */ - __IO uint32_t SRAMRETCTRL; /*!< Power Down control : controls power SRAM instances - in the different Low power modes */ - __IO uint32_t CPURETCTRL; /*!< CPU0 retention control : controls CPU retention parameters in POWER DOWN modes */ - __IO uint64_t VOLTAGE; /*!< Voltage control in Low Power Modes */ - __IO uint64_t WAKEUPSRC; /*!< Wake up sources control for sleepcon */ - __IO uint64_t WAKEUPINT; /*!< Wake up sources control for ARM */ - __IO uint32_t HWWAKE; /*!< Interrupt that can postpone power down modes - in case an interrupt is pending when the processor request deepsleep */ - __IO uint32_t WAKEUPIOSRC; /*!< Wake up I/O sources in DEEP POWER DOWN mode */ - __IO uint32_t TIMERCFG; /*!< Wake up timers configuration */ - __IO uint32_t TIMERCOUNT; /*!< Wake up Timer count*/ - __IO uint32_t POWERCYCLE; /*!< Cancels entry in Low Power mode if set with 0xDEADABBA (might be used by some - interrupt handlers)*/ -} LPC_LOWPOWER_T; - -/* */ -#define LOWPOWER_POWERCYCLE_CANCELLED 0xDEADABBAUL /*!< */ - -/** - * @brief SRAM Low Power Modes - */ -#define LOWPOWER_SRAM_LPMODE_MASK (0xFUL) -#define LOWPOWER_SRAM_LPMODE_ACTIVE (0x6UL) /*!< SRAM functional mode */ -#define LOWPOWER_SRAM_LPMODE_SLEEP (0xFUL) /*!< SRAM Sleep mode (Data retention, fast wake up) */ -#define LOWPOWER_SRAM_LPMODE_DEEPSLEEP (0x8UL) /*!< SRAM Deep Sleep mode (Data retention, slow wake up) */ -#define LOWPOWER_SRAM_LPMODE_SHUTDOWN (0x9UL) /*!< SRAM Shut Down mode (no data retention) */ -#define LOWPOWER_SRAM_LPMODE_POWERUP (0xAUL) /*!< SRAM is powering up */ - -/** - * @brief Wake up timers configuration in Low Power Modes - */ -#define LOWPOWER_TIMERCFG_CTRL_INDEX 0 -#define LOWPOWER_TIMERCFG_CTRL_MASK (0x1UL << LOWPOWER_TIMERCFG_CTRL_INDEX) -#define LOWPOWER_TIMERCFG_TIMER_INDEX 1 -#define LOWPOWER_TIMERCFG_TIMER_MASK (0x7UL << LOWPOWER_TIMERCFG_TIMER_INDEX) -#define LOWPOWER_TIMERCFG_OSC32K_INDEX 4 -#define LOWPOWER_TIMERCFG_OSC32K_MASK (0x1UL << LOWPOWER_TIMERCFG_OSC32K_INDEX) - -#define LOWPOWER_TIMERCFG_CTRL_DISABLE 0 /*!< Wake Timer Disable */ -#define LOWPOWER_TIMERCFG_CTRL_ENABLE 1 /*!< Wake Timer Enable */ - -/** - * @brief Primary Wake up timers configuration in Low Power Modes - */ -#define LOWPOWER_TIMERCFG_TIMER_RTC1KHZ 0 /*!< 1 KHz Real Time Counter (RTC) used as wake up source */ -#define LOWPOWER_TIMERCFG_TIMER_RTC1HZ 1 /*!< 1 Hz Real Time Counter (RTC) used as wake up source */ -#define LOWPOWER_TIMERCFG_TIMER_OSTIMER 2 /*!< OS Event Timer used as wake up source */ - -#define LOWPOWER_TIMERCFG_OSC32K_FRO32KHZ 0 /*!< Wake up Timers uses FRO 32 KHz as clock source */ -#define LOWPOWER_TIMERCFG_OSC32K_XTAL32KHZ 1 /*!< Wake up Timers uses Chrystal 32 KHz as clock source */ - -//! @brief Interface for lowpower functions -typedef struct LowpowerDriverInterface -{ - void (*power_cycle_cpu_and_flash)(void); - void (*set_lowpower_mode)(LPC_LOWPOWER_T *p_lowpower_cfg); -} lowpower_driver_interface_t; - -/**< DCDC Power Profiles */ -typedef enum -{ - DCDC_POWER_PROFILE_LOW, /**< LOW (for CPU frequencies below DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ) */ - DCDC_POWER_PROFILE_MEDIUM, /**< MEDIUM (for CPU frequencies between DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ and - DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ) */ - DCDC_POWER_PROFILE_HIGH, /**< HIGH (for CPU frequencies between DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ and - DCDC_POWER_PROFILE_HIGH_MAX_FREQ_HZ) */ -} lowpower_dcdc_power_profile_enum; - -/**< Manufacturing Process Corners */ -typedef enum -{ - PROCESS_CORNER_SSS, /**< Slow Corner Process */ - PROCESS_CORNER_NNN, /**< Nominal Corner Process */ - PROCESS_CORNER_FFF, /**< Fast Corner Process */ - PROCESS_CORNER_OTHERS, /**< SFN, SNF, NFS, Poly Res ... Corner Process */ -} lowpower_process_corner_enum; - -/** - * @brief DCDC voltage settings - */ -typedef enum _v_dcdc -{ - V_DCDC_0P950 = 0, /*!< 0.95 V */ - V_DCDC_0P975 = 1, /*!< 0.975 V */ - V_DCDC_1P000 = 2, /*!< 1 V */ - V_DCDC_1P025 = 3, /*!< 1.025 V */ - V_DCDC_1P050 = 4, /*!< 1.050 V */ - V_DCDC_1P075 = 5, /*!< 1.075 V */ - V_DCDC_1P100 = 6, /*!< 1.1 V */ - V_DCDC_1P125 = 7, /*!< 1.125 V */ - V_DCDC_1P150 = 8, /*!< 1.150 V */ - V_DCDC_1P175 = 9, /*!< 1.175 V */ - V_DCDC_1P200 = 10 /*!< 1.2 V */ -} v_dcdc_t; - -/** - * @brief Deep Sleep LDO voltage settings - */ -typedef enum _v_deepsleep -{ - V_DEEPSLEEP_0P900 = 0, /*!< 0.9 V */ - V_DEEPSLEEP_0P925 = 1, /*!< 0.925 V */ - V_DEEPSLEEP_0P950 = 2, /*!< 0.95 V */ - V_DEEPSLEEP_0P975 = 3, /*!< 0.975 V */ - V_DEEPSLEEP_1P000 = 4, /*!< 1.000 V */ - V_DEEPSLEEP_1P025 = 5, /*!< 1.025 V */ - V_DEEPSLEEP_1P050 = 6, /*!< 1.050 V */ - V_DEEPSLEEP_1P075 = 7 /*!< 1.075 V */ -} v_deepsleep_t; - -/** - * @brief Always On and Memories LDO voltage settings - */ -typedef enum _v_ao -{ - V_AO_0P700 = 1, /*!< 0.7 V */ - V_AO_0P725 = 2, /*!< 0.725 V */ - V_AO_0P750 = 3, /*!< 0.75 V */ - V_AO_0P775 = 4, /*!< 0.775 V */ - V_AO_0P800 = 5, /*!< 0.8 V */ - V_AO_0P825 = 6, /*!< 0.825 V */ - V_AO_0P850 = 7, /*!< 0.85 V */ - V_AO_0P875 = 8, /*!< 0.875 V */ - V_AO_0P900 = 9, /*!< 0.9 V */ - V_AO_0P960 = 10, /*!< 0.96 V */ - V_AO_0P970 = 11, /*!< 0.97 V */ - V_AO_0P980 = 12, /*!< 0.98 V */ - V_AO_0P990 = 13, /*!< 0.99 V */ - V_AO_1P000 = 14, /*!< 1 V */ - V_AO_1P010 = 15, /*!< 1.01 V */ - V_AO_1P020 = 16, /*!< 1.02 V */ - V_AO_1P030 = 17, /*!< 1.03 V */ - V_AO_1P040 = 18, /*!< 1.04 V */ - V_AO_1P050 = 19, /*!< 1.05 V */ - V_AO_1P060 = 20, /*!< 1.06 V */ - V_AO_1P070 = 21, /*!< 1.07 V */ - V_AO_1P080 = 22, /*!< 1.08 V */ - V_AO_1P090 = 23, /*!< 1.09 V */ - V_AO_1P100 = 24, /*!< 1.1 V */ - V_AO_1P110 = 25, /*!< 1.11 V */ - V_AO_1P120 = 26, /*!< 1.12 V */ - V_AO_1P130 = 27, /*!< 1.13 V */ - V_AO_1P140 = 28, /*!< 1.14 V */ - V_AO_1P150 = 29, /*!< 1.15 V */ - V_AO_1P160 = 30, /*!< 1.16 V */ - V_AO_1P220 = 31 /*!< 1.22 V */ -} v_ao_t; - -/* Low Power modes */ -#define LOWPOWER_CFG_LPMODE_INDEX 0 -#define LOWPOWER_CFG_LPMODE_MASK (0x3UL << LOWPOWER_CFG_LPMODE_INDEX) -#define LOWPOWER_CFG_SELCLOCK_INDEX 2 -#define LOWPOWER_CFG_SELCLOCK_MASK (0x1UL << LOWPOWER_CFG_SELCLOCK_INDEX) -#define LOWPOWER_CFG_SELMEMSUPPLY_INDEX 3 -#define LOWPOWER_CFG_SELMEMSUPPLY_MASK (0x1UL << LOWPOWER_CFG_SELMEMSUPPLY_INDEX) -#define LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX 4 -#define LOWPOWER_CFG_MEMLOWPOWERMODE_MASK (0x1UL << LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX) -#define LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX 5 -#define LOWPOWER_CFG_LDODEEPSLEEPREF_MASK (0x1UL << LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX) - -#define LOWPOWER_CFG_LPMODE_ACTIVE 0 /*!< ACTIVE mode */ -#define LOWPOWER_CFG_LPMODE_DEEPSLEEP 1 /*!< DEEP SLEEP mode */ -#define LOWPOWER_CFG_LPMODE_POWERDOWN 2 /*!< POWER DOWN mode */ -#define LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN 3 /*!< DEEP POWER DOWN mode */ -#define LOWPOWER_CFG_LPMODE_SLEEP 4 /*!< SLEEP mode */ - -#define LOWPOWER_CFG_SELCLOCK_1MHZ 0 /*!< The 1 MHz clock is used during the configuration of the PMC */ -#define LOWPOWER_CFG_SELCLOCK_12MHZ \ - 1 /*!< The 12 MHz clock is used during the configuration of the PMC (to speed up PMC configuration process)*/ - -#define LOWPOWER_CFG_SELMEMSUPPLY_LDOMEM 0 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_MEM */ -#define LOWPOWER_CFG_SELMEMSUPPLY_LDODEEPSLEEP \ - 1 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_DEEP_SLEEP (or DCDC) */ - -#define LOWPOWER_CFG_MEMLOWPOWERMODE_SOURCEBIASING \ - 0 /*!< All SRAM instances use "Source Biasing" as low power mode technic (it is recommended to set LDO_MEM as high \ - as possible -- 1.1V typical -- during low power mode) */ -#define LOWPOWER_CFG_MEMLOWPOWERMODE_VOLTAGESCALING \ - 1 /*!< All SRAM instances use "Voltage Scaling" as low power mode technic (it is recommended to set LDO_MEM as low \ - as possible -- down to 0.7V -- during low power mode) */ - -#define LOWPOWER_CFG_LDODEEPSLEEPREF_FLASHBUFFER 0 /*!< LDO DEEP SLEEP uses Flash Buffer as reference */ -#define LOWPOWER_CFG_LDODEEPSLEEPREF_BANDGAG0P8V 1 /*!< LDO DEEP SLEEP uses Band Gap 0.8V as reference */ - -/* CPU Retention Control*/ -#define LOWPOWER_CPURETCTRL_ENA_INDEX 0 -#define LOWPOWER_CPURETCTRL_ENA_MASK (0x1UL << LOWPOWER_CPURETCTRL_ENA_INDEX) -#define LOWPOWER_CPURETCTRL_MEMBASE_INDEX 1 -#define LOWPOWER_CPURETCTRL_MEMBASE_MASK (0x1FFFUL << LOWPOWER_CPURETCTRL_MEMBASE_INDEX) -#define LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX 14 -#define LOWPOWER_CPURETCTRL_RETDATALENGTH_MASK (0x3FFUL << LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX) - -/* Voltgae setting*/ -#define DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ \ - (100000000U) /* Maximum System Frequency allowed with DCDC Power Profile LOW */ -#define DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ \ - (130000000U) /* Maximum System Frequency allowed with DCDC Power Profile MEDIUM */ -#define DCDC_POWER_PROFILE_HIGH_MAX_FREQ_HZ \ - (150000000U) /* Maximum System Frequency allowed with DCDC Power Profile HIGH */ -#define PROCESS_NNN_AVG_HZ (19300000U) /* Average Ring OScillator value for Nominal (NNN) Manufacturing Process */ -#define PROCESS_NNN_STD_HZ \ - (400000U) /* Standard Deviation Ring OScillator value for Nominal (NNN) Manufacturing Process */ -#define PROCESS_NNN_LIMITS \ - (6U) /* Nominal (NNN) Manufacturing Process Ring Oscillator values limit (with respect to the Average value) */ -#define PROCESS_NNN_MIN_HZ \ - (PROCESS_NNN_AVG_HZ - \ - (PROCESS_NNN_LIMITS * \ - PROCESS_NNN_STD_HZ)) /* Minimum Ring OScillator value for Nominal (NNN) Manufacturing Process */ -#define PROCESS_NNN_MAX_HZ \ - (PROCESS_NNN_AVG_HZ + \ - (PROCESS_NNN_LIMITS * \ - PROCESS_NNN_STD_HZ)) /* Maximum Ring OScillator value for Nominal (NNN) Manufacturing Process */ -#define VOLTAGE_SSS_LOW_MV (1075U) /* Voltage Settings for : Process=SSS, DCDC Power Profile=LOW */ -#define VOLTAGE_SSS_MED_MV (1150U) /* Voltage Settings for : Process=SSS, DCDC Power Profile=MEDIUM */ -#define VOLTAGE_SSS_HIG_MV (1200U) /* Voltage Settings for : Process=SSS, DCDC Power Profile=HIGH */ -#define VOLTAGE_NNN_LOW_MV (1000U) /* Voltage Settings for : Process=NNN, DCDC Power Profile=LOW */ -#define VOLTAGE_NNN_MED_MV (1100U) /* Voltage Settings for : Process=NNN, DCDC Power Profile=MEDIUM */ -#define VOLTAGE_NNN_HIG_MV (1150U) /* Voltage Settings for : Process=NNN, DCDC Power Profile=HIGH */ -#define VOLTAGE_FFF_LOW_MV (1000U) /* Voltage Settings for : Process=FFF, DCDC Power Profile=LOW */ -#define VOLTAGE_FFF_MED_MV (1025U) /* Voltage Settings for : Process=FFF, DCDC Power Profile=MEDIUM */ -#define VOLTAGE_FFF_HIG_MV (1050U) /* Voltage Settings for : Process=FFF, DCDC Power Profile=HIGH */ - -/** - * @brief LDO Voltage control in Low Power Modes - */ -#define LOWPOWER_VOLTAGE_LDO_PMU_INDEX 0 -#define LOWPOWER_VOLTAGE_LDO_PMU_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) -#define LOWPOWER_VOLTAGE_LDO_MEM_INDEX 5 -#define LOWPOWER_VOLTAGE_LDO_MEM_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) -#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX 10 -#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_MASK (0x7ULL << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX) -#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX 19 -#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) -#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX 24 -#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) -#define LOWPOWER_VOLTAGE_DCDC_INDEX 29 -#define LOWPOWER_VOLTAGE_DCDC_MASK (0xFULL << LOWPOWER_VOLTAGE_DCDC_INDEX) - -/*! @brief set and clear bit MACRO's. */ -#define U32_SET_BITS(P, B) ((*(uint32_t *)P) |= (B)) -#define U32_CLR_BITS(P, B) ((*(uint32_t *)P) &= ~(B)) -/* Return values from Config (N-2) page of flash */ -#define GET_16MXO_TRIM() (*(uint32_t *)0x9FCC8) -#define GET_32KXO_TRIM() (*(uint32_t *)0x9FCCC) - -#define CPU_RETENTION_RAMX_STORAGE_START_ADDR (0x04006000) - -#define XO_SLAVE_EN (1) -/******************************************************************************* - * Codes - ******************************************************************************/ - -/******************************************************************************* - * LOCAL FUNCTIONS PROTOTYPES - ******************************************************************************/ -static void lf_get_deepsleep_core_supply_cfg(uint32_t exclude_from_pd, uint32_t *dcdc_voltage); -static uint32_t lf_set_ldo_ao_ldo_mem_voltage(uint32_t p_lp_mode, uint32_t p_dcdc_voltage); -static uint32_t lf_wakeup_io_ctrl(uint32_t p_wakeup_io_ctrl); -static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity); - -static void lowpower_set_dcdc_power_profile(lowpower_dcdc_power_profile_enum dcdc_power_profile); -static lowpower_process_corner_enum lowpower_get_part_process_corner(void); -static void lowpower_set_voltage_for_process(lowpower_dcdc_power_profile_enum dcdc_power_profile); - -/** - * @brief Configures and enters in low power mode - * @param p_lowpower_cfg: pointer to a structure that contains all low power mode parameters - * @return Nothing - * - * !!! IMPORTANT NOTES : - * 1 - CPU Interrupt Enable registers are updated with p_lowpower_cfg->WAKEUPINT. They are NOT restored by the - * API. - * 2 - The Non Maskable Interrupt (NMI) should be disable before calling this API (otherwise, there is a risk - * of Dead Lock). - * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip - * reset) - */ -static void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg); - -/** - * @brief - * @param - * @return - */ -static void lf_set_dcdc_power_profile_low(void) -{ -#define DCDC_POWER_PROFILE_LOW_0_ADDRS (0x9FCE0U) -#define DCDC_POWER_PROFILE_LOW_1_ADDRS (0x9FCE4U) - - uint32_t dcdcTrimValue0 = (*((volatile unsigned int *)(DCDC_POWER_PROFILE_LOW_0_ADDRS))); - uint32_t dcdcTrimValue1 = (*((volatile unsigned int *)(DCDC_POWER_PROFILE_LOW_1_ADDRS))); - - if (0UL != (dcdcTrimValue0 & 0x1UL)) - { - PMC->DCDC0 = dcdcTrimValue0 >> 1; - PMC->DCDC1 = dcdcTrimValue1; - } -} - -/** - * @brief Configures and enters in low power mode - * @param : p_lowpower_cfg - * @return Nothing - */ -static void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg) -{ - lowpower_driver_interface_t *s_lowpowerDriver; - /* Judging the core and call the corresponding API base address*/ - if (0UL == Chip_GetVersion()) - { - s_lowpowerDriver = (lowpower_driver_interface_t *)(0x130010d4UL); - } - else - { - s_lowpowerDriver = (lowpower_driver_interface_t *)(0x13001204UL); - } - /* PMC clk set to 12 MHZ */ - p_lowpower_cfg->CFG |= (uint32_t)LOWPOWER_CFG_SELCLOCK_12MHZ << LOWPOWER_CFG_SELCLOCK_INDEX; - - /* Enable Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP - * POWER DOWN) and Hardware Pin reset */ - PMC->REFFASTWKUP = (PMC->REFFASTWKUP & (~PMC_REFFASTWKUP_LPWKUP_MASK) & (~PMC_REFFASTWKUP_HWWKUP_MASK)) | - PMC_REFFASTWKUP_LPWKUP(1) | PMC_REFFASTWKUP_HWWKUP(1); - - /* SRAM uses Voltage Scaling in all Low Power modes */ - PMC->SRAMCTRL = (PMC->SRAMCTRL & (~PMC_SRAMCTRL_SMB_MASK)) | PMC_SRAMCTRL_SMB(3); - - /* CPU Retention configuration : preserve the value of FUNCRETENTIONCTRL.RET_LENTH which is a Hardware defined - * parameter. */ - p_lowpower_cfg->CPURETCTRL = (SYSCON->FUNCRETENTIONCTRL & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) | - (p_lowpower_cfg->CPURETCTRL & (~SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK)); - - /* Switch System Clock to FRO12Mhz (the configuration before calling this function will not be restored back) */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* Switch main clock to FRO12MHz */ - CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /* Main clock divided by 1 */ - SYSCON->FMCCR = (SYSCON->FMCCR & 0xFFFF0000UL) | 0x201AUL; /* Adjust FMC waiting time cycles */ - lf_set_dcdc_power_profile_low(); /* Align DCDC Power profile with the 12 MHz clock (DCDC Power Profile LOW) */ - - (*(s_lowpowerDriver->set_lowpower_mode))(p_lowpower_cfg); - - /* Restore the configuration of the MISCCTRL Register : LOWPWR_FLASH_BUF = 0, LDOMEMBLEEDDSLP = 0, LDOMEMHIGHZMODE = - * 0 */ - PMC->MISCCTRL &= (~PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK) & (~PMC_MISCCTRL_DISABLE_BLEED_MASK) & - (~PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK); -} - -/** - * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event - * @param None - * @return Nothing - */ -void POWER_CycleCpuAndFlash(void) -{ - /* Judging the core and call the corresponding API base address*/ - lowpower_driver_interface_t *s_lowpowerDriver; - if (0UL == Chip_GetVersion()) - { - s_lowpowerDriver = (lowpower_driver_interface_t *)(0x130010d4UL); - } - else - { - s_lowpowerDriver = (lowpower_driver_interface_t *)(0x13001204UL); - } - (*(s_lowpowerDriver->power_cycle_cpu_and_flash))(); -}; - -/** - * brief PMC Deep Sleep function call - * return nothing - */ -void POWER_EnterDeepSleep(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t hardware_wake_ctrl) -{ - LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ - uint32_t cpu0_nmi_enable; - uint32_t cpu0_int_enable_0; - uint32_t cpu0_int_enable_1; - uint32_t dcdc_voltage; - uint32_t pmc_reset_ctrl; - /* Clear Low Power Mode configuration variable */ - (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); - - /* Configure Low Power Mode configuration variable */ - lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPSLEEP - << LOWPOWER_CFG_LPMODE_INDEX; /* DEEPSLEEP mode */ - - lf_get_deepsleep_core_supply_cfg(exclude_from_pd, &dcdc_voltage); - - if (((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_USB1_PHY) != 0UL) && - ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_LDOUSBHS) != 0UL)) - { - /* USB High Speed is required as wake-up source in Deep Sleep mode: make sure LDO FLASH NV stays powered during - * deep-sleep */ - exclude_from_pd = exclude_from_pd | (uint32_t)kPDRUNCFG_PD_LDOFLASHNV; - } - - /* DCDC will be always used during Deep Sleep (instead of LDO Deep Sleep); Make sure LDO MEM & Analog references - * will stay powered, Shut down ROM */ - lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd & ~(uint32_t)kPDRUNCFG_PD_DCDC & ~(uint32_t)kPDRUNCFG_PD_LDOMEM & - ~(uint32_t)kPDRUNCFG_PD_BIAS) | - (uint32_t)kPDRUNCFG_PD_LDODEEPSLEEP | (uint32_t)kPDRUNCFG_PD_ROM; - - /* Voltage control in DeepSleep Low Power Modes */ - /* The Memories Voltage settings below are for voltage scaling */ - lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_POWERDOWN, dcdc_voltage); - - /* SRAM retention control during POWERDOWN */ - lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; - - /* CPU Wake up & Interrupt sources control */ - lv_low_power_mode_cfg.WAKEUPINT = wakeup_interrupts; - lv_low_power_mode_cfg.WAKEUPSRC = wakeup_interrupts; - - /* Interrupts that allow DMA transfers with Flexcomm without waking up the Processor */ - if (0UL != (hardware_wake_ctrl & (LOWPOWER_HWWAKE_PERIPHERALS | LOWPOWER_HWWAKE_SDMA0 | LOWPOWER_HWWAKE_SDMA1))) - { - lv_low_power_mode_cfg.HWWAKE = (hardware_wake_ctrl & ~LOWPOWER_HWWAKE_FORCED) | LOWPOWER_HWWAKE_ENABLE_FRO192M; - } - - cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ - SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ - - /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power - * API */ - cpu0_int_enable_0 = NVIC->ISER[0]; - cpu0_int_enable_1 = NVIC->ISER[1]; - - pmc_reset_ctrl = PMC->RESETCTRL; - if (0UL != (pmc_reset_ctrl & PMC_RESETCTRL_BODCORERESETENABLE_MASK)) - { - /* BoD CORE reset is activated, so make sure BoD Core won't be shutdown */ - lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_BODCORE; - } - if (0UL != (pmc_reset_ctrl & PMC_RESETCTRL_BODVBATRESETENABLE_MASK)) - { - /* BoD VBAT reset is activated, so make sure BoD VBAT won't be shutdown */ - lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_BODVBAT; - } - - /* Enter low power mode */ - POWER_EnterLowPower(&lv_low_power_mode_cfg); - - /* Restore the configuration of the NMI Register */ - SYSCON->NMISRC |= cpu0_nmi_enable; - - /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the - * low power API */ - NVIC->ISER[0] = cpu0_int_enable_0; - NVIC->ISER[1] = cpu0_int_enable_1; -} - -/** - * brief PMC power Down function call - * return nothing - */ -void POWER_EnterPowerDown(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t cpu_retention_ctrl) -{ - LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ - uint32_t cpu0_nmi_enable; - uint32_t cpu0_int_enable_0; - uint32_t cpu0_int_enable_1; - uint64_t wakeup_src_int; - uint32_t pmc_reset_ctrl; - - uint32_t analog_ctrl_regs[12]; /* To store Analog Controller Regristers */ - - /* Clear Low Power Mode configuration variable */ - (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); - - /* Configure Low Power Mode configuration variable */ - lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_POWERDOWN - << LOWPOWER_CFG_LPMODE_INDEX; /* POWER DOWN mode */ - - /* Only FRO32K, XTAL32K, COMP, BIAS and LDO_MEM can be stay powered during POWERDOWN (valid from application point - * of view; Hardware allows BODVBAT, LDODEEPSLEEP and FRO1M to stay powered, that's why they are excluded below) */ - lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd) | (uint32_t)kPDRUNCFG_PD_BODVBAT | (uint32_t)kPDRUNCFG_PD_FRO1M | - (uint32_t)kPDRUNCFG_PD_LDODEEPSLEEP; - - /* SRAM retention control during POWERDOWN */ - lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; - - /* Sanity check: If retention is required for any of SRAM instances, make sure LDO MEM will stay powered */ - if ((sram_retention_ctrl & 0x7FFFUL) != 0UL) - { - lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_LDOMEM; - } - - /* Voltage control in Low Power Modes */ - /* The Memories Voltage settings below are for voltage scaling */ - lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_POWERDOWN, 0); - - /* CPU0 retention Ctrl. - * For the time being, we do not allow customer to relocate the CPU retention area in SRAMX, meaning that the - * retention area range is [0x0400_6000 - 0x0400_6600] (beginning of RAMX2) If required by customer, - * cpu_retention_ctrl[13:1] will be used for that to modify the default retention area - */ - lv_low_power_mode_cfg.CPURETCTRL = - (cpu_retention_ctrl & LOWPOWER_CPURETCTRL_ENA_MASK) | - ((((uint32_t)CPU_RETENTION_RAMX_STORAGE_START_ADDR >> 2UL) << LOWPOWER_CPURETCTRL_MEMBASE_INDEX) & - LOWPOWER_CPURETCTRL_MEMBASE_MASK); - if (0UL != (cpu_retention_ctrl & 0x1UL)) - { - /* CPU retention is required: store Analog Controller Registers */ - analog_ctrl_regs[0] = ANACTRL->FRO192M_CTRL; - analog_ctrl_regs[1] = ANACTRL->ANALOG_CTRL_CFG; - analog_ctrl_regs[2] = ANACTRL->ADC_CTRL; - analog_ctrl_regs[3] = ANACTRL->XO32M_CTRL; - analog_ctrl_regs[4] = ANACTRL->BOD_DCDC_INT_CTRL; - analog_ctrl_regs[5] = ANACTRL->RINGO0_CTRL; - analog_ctrl_regs[6] = ANACTRL->RINGO1_CTRL; - analog_ctrl_regs[7] = ANACTRL->RINGO2_CTRL; - analog_ctrl_regs[8] = ANACTRL->LDO_XO32M; - analog_ctrl_regs[9] = ANACTRL->AUX_BIAS; - analog_ctrl_regs[10] = ANACTRL->USBHS_PHY_CTRL; - analog_ctrl_regs[11] = ANACTRL->USBHS_PHY_TRIM; - } - - /* CPU Wake up & Interrupt sources control : only WAKEUP_GPIO_GLOBALINT0, WAKEUP_GPIO_GLOBALINT1, WAKEUP_FLEXCOMM3, - * WAKEUP_ACMP_CAPT, WAKEUP_RTC_LITE_ALARM_WAKEUP, WAKEUP_OS_EVENT_TIMER, WAKEUP_ALLWAKEUPIOS */ - wakeup_src_int = (uint64_t)(WAKEUP_GPIO_GLOBALINT0 | WAKEUP_GPIO_GLOBALINT1 | WAKEUP_FLEXCOMM3 | WAKEUP_ACMP_CAPT | - WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER | WAKEUP_ALLWAKEUPIOS); - lv_low_power_mode_cfg.WAKEUPINT = wakeup_interrupts & wakeup_src_int; - lv_low_power_mode_cfg.WAKEUPSRC = wakeup_interrupts & wakeup_src_int; - - cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ - SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ - - /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power - * API */ - cpu0_int_enable_0 = NVIC->ISER[0]; - cpu0_int_enable_1 = NVIC->ISER[1]; - - pmc_reset_ctrl = PMC->RESETCTRL; - /* Disable BoD VBAT and BoD Core resets */ - PMC->RESETCTRL = - pmc_reset_ctrl & (~(PMC_RESETCTRL_BODVBATRESETENABLE_MASK | PMC_RESETCTRL_BODCORERESETENABLE_MASK)); - - /* Enter low power mode */ - POWER_EnterLowPower(&lv_low_power_mode_cfg); - - /*** We'll reach this point in case of POWERDOWN with CPU retention or if the POWERDOWN has not been taken (for - instance because an interrupt is pending). In case of CPU retention, assumption is that the SRAM containing the - stack used to call this function shall be preserved during low power ***/ - - /* Restore the configuration of the NMI Register */ - SYSCON->NMISRC |= cpu0_nmi_enable; - - /* Restore PMC RESETCTRL register */ - PMC->RESETCTRL = pmc_reset_ctrl; - - /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the - * low power API */ - NVIC->ISER[0] = cpu0_int_enable_0; - NVIC->ISER[1] = cpu0_int_enable_1; - - if (0UL != (cpu_retention_ctrl & 0x1UL)) - { - /* Restore Analog Controller Registers */ - ANACTRL->FRO192M_CTRL = analog_ctrl_regs[0] | ANACTRL_FRO192M_CTRL_WRTRIM_MASK; - ANACTRL->ANALOG_CTRL_CFG = analog_ctrl_regs[1]; - ANACTRL->ADC_CTRL = analog_ctrl_regs[2]; - ANACTRL->XO32M_CTRL = analog_ctrl_regs[3]; - ANACTRL->BOD_DCDC_INT_CTRL = analog_ctrl_regs[4]; - ANACTRL->RINGO0_CTRL = analog_ctrl_regs[5]; - ANACTRL->RINGO1_CTRL = analog_ctrl_regs[6]; - ANACTRL->RINGO2_CTRL = analog_ctrl_regs[7]; - ANACTRL->LDO_XO32M = analog_ctrl_regs[8]; - ANACTRL->AUX_BIAS = analog_ctrl_regs[9]; - ANACTRL->USBHS_PHY_CTRL = analog_ctrl_regs[10]; - ANACTRL->USBHS_PHY_TRIM = analog_ctrl_regs[11]; - } -} - -/** - * brief PMC Deep Sleep Power Down function call - * return nothing - */ -void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t wakeup_io_ctrl) -{ - LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ - uint32_t cpu0_nmi_enable; - uint32_t cpu0_int_enable_0; - uint32_t cpu0_int_enable_1; - uint32_t pmc_reset_ctrl; - - /* Clear Low Power Mode configuration variable */ - (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); - - /* Configure Low Power Mode configuration variable */ - lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN - << LOWPOWER_CFG_LPMODE_INDEX; /* DEEP POWER DOWN mode */ - - /* Only FRO32K, XTAL32K and LDO_MEM can be stay powered during DEEPPOWERDOWN (valid from application point of view; - * Hardware allows BODVBAT, BIAS FRO1M and COMP to stay powered, that's why they are excluded below) */ - lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd) | (uint32_t)kPDRUNCFG_PD_BIAS | (uint32_t)kPDRUNCFG_PD_BODVBAT | - (uint32_t)kPDRUNCFG_PD_FRO1M | (uint32_t)kPDRUNCFG_PD_COMP; - - /* SRAM retention control during DEEPPOWERDOWN */ - sram_retention_ctrl = - sram_retention_ctrl & - (~(LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 | LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 | LOWPOWER_SRAMRETCTRL_RETEN_RAM00)); - - /* SRAM retention control during DEEPPOWERDOWN */ - lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; - - /* Sanity check: If retention is required for any of SRAM instances, make sure LDO MEM will stay powered */ - if ((sram_retention_ctrl & 0x7FFFUL) != 0UL) - { - lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_LDOMEM; - } - - /* Voltage control in Low Power Modes */ - /* The Memories Voltage settings below are for voltage scaling */ - lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN, 0); - - lv_low_power_mode_cfg.WAKEUPINT = - wakeup_interrupts & (WAKEUP_RTC_LITE_ALARM_WAKEUP | - WAKEUP_OS_EVENT_TIMER); /* CPU Wake up sources control : only WAKEUP_RTC_LITE_ALARM_WAKEUP, - WAKEUP_OS_EVENT_TIMER */ - lv_low_power_mode_cfg.WAKEUPSRC = - wakeup_interrupts & - (WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER | - WAKEUP_ALLWAKEUPIOS); /*!< Hardware Wake up sources control: : only WAKEUP_RTC_LITE_ALARM_WAKEUP, - WAKEUP_OS_EVENT_TIMER and WAKEUP_ALLWAKEUPIOS */ - - /* Wake up I/O sources */ - lv_low_power_mode_cfg.WAKEUPIOSRC = lf_wakeup_io_ctrl(wakeup_io_ctrl); - - cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ - SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ - - /* Save the configuration of the CPU interrupt enable Registers */ - cpu0_int_enable_0 = NVIC->ISER[0]; - cpu0_int_enable_1 = NVIC->ISER[1]; - - /* Save the configuration of the PMC RESETCTRL register */ - pmc_reset_ctrl = PMC->RESETCTRL; - /* Disable BoD VBAT and BoD Core resets */ - PMC->RESETCTRL = - pmc_reset_ctrl & (~(PMC_RESETCTRL_BODVBATRESETENABLE_MASK | PMC_RESETCTRL_BODCORERESETENABLE_MASK)); - - /* Disable LDO MEM bleed current */ - // PMC->MISCCTRL |= PMC_MISCCTRL_DISABLE_BLEED_MASK; - - /* Enter low power mode */ - POWER_EnterLowPower(&lv_low_power_mode_cfg); - - /* Restore the configuration of the NMI Register */ - SYSCON->NMISRC |= cpu0_nmi_enable; - - /* Restore PMC RESETCTRL register */ - PMC->RESETCTRL = pmc_reset_ctrl; - - /* Restore the configuration of the CPU interrupt enable Registers */ - NVIC->ISER[0] = cpu0_int_enable_0; - NVIC->ISER[1] = cpu0_int_enable_1; -} - -/** - * brief PMC Sleep function call - * return nothing - */ -void POWER_EnterSleep(void) -{ - uint32_t pmsk; - pmsk = __get_PRIMASK(); - __disable_irq(); - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - __WFI(); - __set_PRIMASK(pmsk); -} - -/** - * @brief Get Digital Core logic supply source to be used during Deep Sleep. - * @param [in] exclude_from_pd: COmpoenents NOT to be powered down during Deep Sleep - * @param [out] core_supply: 0 = LDO DEEPSLEEP will be used / 1 = DCDC will be used - * @param [out] dcdc_voltage: as defined by V_DCDC_* in fsl_power.h - - * @return Nothing - */ -static void lf_get_deepsleep_core_supply_cfg(uint32_t exclude_from_pd, uint32_t *dcdc_voltage) -{ - *dcdc_voltage = (uint32_t)V_DCDC_0P950; /* Default value */ - - if (((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_USB1_PHY) != 0UL) && - ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_LDOUSBHS) != 0UL)) - { - /* USB High Speed is required as wake-up source in Deep Sleep mode */ - PMC->MISCCTRL |= PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK; /* Force flash buffer in low power mode */ - *dcdc_voltage = - (uint32_t)V_DCDC_1P000; /* Set DCDC voltage to be 1.000 V (USB HS IP cannot work below 0.990 V) */ - } -} - -/** - * @brief - * @param - * @return - */ -static uint32_t lf_set_ldo_ao_ldo_mem_voltage(uint32_t p_lp_mode, uint32_t p_dcdc_voltage) -{ -#define FLASH_NMPA_LDO_AO_ADDRS (0x9FCF4U) -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK (0x100U) -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK (0x3E00U) -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT (9U) -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK (0x10000U) -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK (0x3E0000U) -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT (17U) -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK (0x1000000U) -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK (0x3E000000U) -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT (25U) - - uint32_t ldo_ao_trim, voltage; - uint32_t lv_v_ldo_pmu, lv_v_ldo_pmu_boost; - - ldo_ao_trim = (*((volatile unsigned int *)(FLASH_NMPA_LDO_AO_ADDRS))); - - switch (p_lp_mode) - { - case LOWPOWER_CFG_LPMODE_DEEPSLEEP: - { - if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK) != 0UL) - { - /* Apply settings coming from Flash */ - lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK) >> FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT; - lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ - } - else - { - /* Apply default settings */ - lv_v_ldo_pmu = (uint32_t)V_AO_0P900; - lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P850; - } - } - break; - - case LOWPOWER_CFG_LPMODE_POWERDOWN: - { - if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK) != 0UL) - { - /* Apply settings coming from Flash */ - lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK) >> FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT; - lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ - } - else - { - /* Apply default settings */ - lv_v_ldo_pmu = (uint32_t)V_AO_0P800; - lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P750; - } - } - break; - - case LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN: - { - if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK) != 0UL) - { - /* Apply settings coming from Flash */ - lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK) >> FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT; - lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ - } - else - { - /* Apply default settings */ - lv_v_ldo_pmu = (uint32_t)V_AO_0P800; - lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P750; - } - } - break; - - default: - /* Should never reach this point */ - lv_v_ldo_pmu = (uint32_t)V_AO_1P100; - lv_v_ldo_pmu_boost = (uint32_t)V_AO_1P050; - break; - } - - /* The Memories Voltage settings below are for voltage scaling */ - voltage = - (lv_v_ldo_pmu << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) | /* */ - (lv_v_ldo_pmu_boost << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) | /* */ - ((uint32_t)V_AO_0P750 << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) | /* Set to 0.75V (voltage Scaling) */ - ((uint32_t)V_AO_0P700 << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) | /* Set to 0.7V (voltage Scaling) */ - ((uint32_t)V_DEEPSLEEP_0P900 - << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX) | /* Set to 0.90 V (Not used because LDO_DEEP_SLEEP is disabled)*/ - (p_dcdc_voltage << LOWPOWER_VOLTAGE_DCDC_INDEX) /* */ - ; - - return (voltage); -} - -/** - * @brief - * @param - * @return - */ -static uint32_t lf_wakeup_io_ctrl(uint32_t p_wakeup_io_ctrl) -{ - uint32_t wake_up_type; - uint32_t misc_ctrl_reg; - uint8_t use_external_pullupdown = 0; - - /* Configure Pull up & Pull down based on the required wake-up edge */ - CLOCK_EnableClock(kCLOCK_Iocon); - - misc_ctrl_reg = 0UL; - - /* Wake-up I/O 0 */ - wake_up_type = (p_wakeup_io_ctrl & 0x3UL) >> LOWPOWER_WAKEUPIOSRC_PIO0_INDEX; - use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK) >> - LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX); - - if (use_external_pullupdown == 0UL) - { - if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) - { - /* Rising edge and both rising and falling edges */ - IOCON->PIO[1][1] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ - misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; - } - else - { - if (wake_up_type == 2UL) - { - /* Falling edge only */ - IOCON->PIO[1][1] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ - misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; - p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; - } - else - { - /* Wake-up I/O is disabled : set it as required by the user */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as Plain Input */ - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; - } - else - { - /* Wake-up I/O is configured as pull-up or pull-down */ - misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; - } - } - } - } - else - { - /* MISCCTRL[8]:WAKEUPIOCTRL[8]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */ - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; - misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; - } - - /* Wake-up I/O 1 */ - wake_up_type = (p_wakeup_io_ctrl & 0xCUL) >> LOWPOWER_WAKEUPIOSRC_PIO1_INDEX; - use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK) >> - LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX); - - if (use_external_pullupdown == 0UL) - { - if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) - { - /* Rising edge and both rising and falling edges */ - IOCON->PIO[0][28] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ - misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; - } - else - { - if (wake_up_type == 2UL) - { - /* Falling edge only */ - IOCON->PIO[0][28] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ - misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; - p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; - } - else - { - /* Wake-up I/O is disabled : set it as required by the user */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as Plain Input */ - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; - } - else - { - /* Wake-up I/O is configured as pull-up or pull-down */ - misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; - } - } - } - } - else - { - /* MISCCTRL[9]:WAKEUPIOCTRL[9]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */ - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; - misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; - } - - /* Wake-up I/O 2 */ - wake_up_type = (p_wakeup_io_ctrl & 0x30UL) >> LOWPOWER_WAKEUPIOSRC_PIO2_INDEX; - use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK) >> - LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX); - - if (use_external_pullupdown == 0UL) - { - if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) - { - /* Rising edge and both rising and falling edges */ - IOCON->PIO[1][18] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ - misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; - } - else - { - if (wake_up_type == 2UL) - { - /* Falling edge only */ - IOCON->PIO[1][18] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ - misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; - p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; - } - else - { - /* Wake-up I/O is disabled : set it as required by the user */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as Plain Input */ - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; - } - else - { - /* Wake-up I/O is configured as pull-up or pull-down */ - misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; - } - } - } - } - else - { - /* MISCCTRL[10]:WAKEUPIOCTRL[10]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */ - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; - misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; - } - - /* Wake-up I/O 3 */ - wake_up_type = (p_wakeup_io_ctrl & 0xC0UL) >> LOWPOWER_WAKEUPIOSRC_PIO3_INDEX; - use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK) >> - LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX); - - if (use_external_pullupdown == 0UL) - { - if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) - { - /* Rising edge and both rising and falling edges */ - IOCON->PIO[1][30] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ - misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; - } - else - { - if (wake_up_type == 2UL) - { - /* Falling edge only */ - IOCON->PIO[1][30] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ - misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; - p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; - } - else - { - /* Wake-up I/O is disabled : set it as required by the user */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as Plain Input */ - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; - } - else - { - /* Wake-up I/O is configured as pull-up or pull-down */ - misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; - } - } - } - } - else - { - /* MISCCTRL[11]:WAKEUPIOCTRL[11]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */ - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; - misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; - } - - PMC->MISCCTRL = (PMC->MISCCTRL & 0xFFFFF0FFUL) | misc_ctrl_reg; - PMC->WAKEUPIOCTRL = p_wakeup_io_ctrl & 0xFFFUL; - - /* - * Defined according to : - * - LOWPOWER_WAKEUPIOSRC_ in fsl_power.h - * - LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_<...> in fsl_power.h - */ - return (p_wakeup_io_ctrl & 0xFFFUL); -} - -/** - * @brief - * @param - * @return - */ -static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity) -{ - /* Compensate for discontinuity in the capacitor banks */ - if (u8OscCap < 64U) - { - if (u8OscCap >= u8CapBankDiscontinuity) - { - u8OscCap -= u8CapBankDiscontinuity; - } - else - { - u8OscCap = 0U; - } - } - else - { - if (u8OscCap <= (127U - u8CapBankDiscontinuity)) - { - u8OscCap += u8CapBankDiscontinuity; - } - else - { - u8OscCap = 127U; - } - } - return u8OscCap; -} - -/** - * @brief Described in fsl_common.h - * @param - * @return - */ -static void lowpower_set_system_voltage(uint32_t system_voltage_mv) -{ - /* - * Set system voltage - */ - uint32_t lv_ldo_ao = (uint32_t)V_AO_1P100; /* */ - uint32_t lv_ldo_ao_boost = (uint32_t)V_AO_1P150; /* */ - uint32_t lv_dcdc = (uint32_t)V_DCDC_1P100; /* */ - - if (system_voltage_mv <= 950UL) - { - lv_dcdc = (uint32_t)V_DCDC_0P950; - lv_ldo_ao = (uint32_t)V_AO_0P960; - lv_ldo_ao_boost = (uint32_t)V_AO_1P010; - } - else if (system_voltage_mv <= 975UL) - { - lv_dcdc = (uint32_t)V_DCDC_0P975; - lv_ldo_ao = (uint32_t)V_AO_0P980; - lv_ldo_ao_boost = (uint32_t)V_AO_1P030; - } - else if (system_voltage_mv <= 1000UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P000; - lv_ldo_ao = (uint32_t)V_AO_1P000; - lv_ldo_ao_boost = (uint32_t)V_AO_1P050; - } - else if (system_voltage_mv <= 1025UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P025; - lv_ldo_ao = (uint32_t)V_AO_1P030; - lv_ldo_ao_boost = (uint32_t)V_AO_1P080; - } - else if (system_voltage_mv <= 1050UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P050; - lv_ldo_ao = (uint32_t)V_AO_1P060; - lv_ldo_ao_boost = (uint32_t)V_AO_1P110; - } - else if (system_voltage_mv <= 1075UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P075; - lv_ldo_ao = (uint32_t)V_AO_1P080; - lv_ldo_ao_boost = (uint32_t)V_AO_1P130; - } - else if (system_voltage_mv <= 1100UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P100; - lv_ldo_ao = (uint32_t)V_AO_1P100; - lv_ldo_ao_boost = (uint32_t)V_AO_1P150; - } - else if (system_voltage_mv <= 1125UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P125; - lv_ldo_ao = (uint32_t)V_AO_1P130; - lv_ldo_ao_boost = (uint32_t)V_AO_1P160; - } - else if (system_voltage_mv <= 1150UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P150; - lv_ldo_ao = (uint32_t)V_AO_1P160; - lv_ldo_ao_boost = (uint32_t)V_AO_1P220; - } - else if (system_voltage_mv <= 1175UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P175; - lv_ldo_ao = (uint32_t)V_AO_1P160; - lv_ldo_ao_boost = (uint32_t)V_AO_1P220; - } - else - { - lv_dcdc = (uint32_t)V_DCDC_1P200; - lv_ldo_ao = (uint32_t)V_AO_1P160; - lv_ldo_ao_boost = (uint32_t)V_AO_1P220; - } - - /* Set up LDO Always-On voltages */ - PMC->LDOPMU = (PMC->LDOPMU & (~PMC_LDOPMU_VADJ_MASK) & (~PMC_LDOPMU_VADJ_BOOST_MASK)) | PMC_LDOPMU_VADJ(lv_ldo_ao) | - PMC_LDOPMU_VADJ_BOOST(lv_ldo_ao_boost); - - /* Set up DCDC voltage */ - PMC->DCDC0 = (PMC->DCDC0 & (~PMC_DCDC0_VOUT_MASK)) | PMC_DCDC0_VOUT(lv_dcdc); -} - -/** - * @brief Described in fsl_common.h - * @param - * @return - */ -static void lowpower_set_dcdc_power_profile(lowpower_dcdc_power_profile_enum dcdc_power_profile) -{ -#define FLASH_NMPA_BASE (0x9FC00u) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ADDRS (FLASH_NMPA_BASE + 0xE0U) // (0x9FCE0U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ADDRS (FLASH_NMPA_BASE + 0xE4U) // (0x9FCE4U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ADDRS (FLASH_NMPA_BASE + 0xE8U) // (0x9FCE8U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ADDRS (FLASH_NMPA_BASE + 0xECU) // (0x9FCECU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ADDRS (FLASH_NMPA_BASE + 0xD8U) // (0x9FCD8U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ADDRS (FLASH_NMPA_BASE + 0xDCU) // (0x9FCDCU) - - const uint32_t PMC_DCDC0_DEFAULT = 0x010C4E68; - const uint32_t PMC_DCDC1_DEFAULT = 0x01803A98; - - uint32_t dcdcTrimValue0; - uint32_t dcdcTrimValue1; - - switch (dcdc_power_profile) - { - case DCDC_POWER_PROFILE_LOW: - /* Low */ - dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ADDRS))); - dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ADDRS))); - - if (0UL != (dcdcTrimValue0 & 0x1UL)) - { - dcdcTrimValue0 = dcdcTrimValue0 >> 1; - - PMC->DCDC0 = dcdcTrimValue0; - PMC->DCDC1 = dcdcTrimValue1; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : DCDC Power Profile set to " - "LOW" - "\n"); -#endif - } - break; - - case DCDC_POWER_PROFILE_MEDIUM: - /* Medium */ - dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ADDRS))); - dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ADDRS))); - - if (0UL != (dcdcTrimValue0 & 0x1UL)) - { - dcdcTrimValue0 = dcdcTrimValue0 >> 1; - - PMC->DCDC0 = dcdcTrimValue0; - PMC->DCDC1 = dcdcTrimValue1; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : DCDC Power Profile set to " - "MEDIUM" - "\n"); -#endif - } - break; - - case DCDC_POWER_PROFILE_HIGH: - /* High */ - dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ADDRS))); - dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ADDRS))); - - if (0UL != (dcdcTrimValue0 & 0x1UL)) - { - dcdcTrimValue0 = dcdcTrimValue0 >> 1; - - PMC->DCDC0 = dcdcTrimValue0; - PMC->DCDC1 = dcdcTrimValue1; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : DCDC Power Profile set to " - "HIGH" - "\n"); -#endif - } - break; - - default: - /* Low */ - PMC->DCDC0 = PMC_DCDC0_DEFAULT; - PMC->DCDC1 = PMC_DCDC1_DEFAULT; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : DCDC Power Profile set to " - "LOW" - "\n"); -#endif - break; - } -} - -/** - * @brief - * @param - * @return - */ -static lowpower_process_corner_enum lowpower_get_part_process_corner(void) -{ -#define FLASH_NMPA_PVT_MONITOR_0_RINGO_ADDRS (FLASH_NMPA_BASE + 0x130U) -#define FLASH_NMPA_PVT_MONITOR_1_RINGO_ADDRS (FLASH_NMPA_BASE + 0x140U) - - lowpower_process_corner_enum part_process_corner; - uint32_t pvt_ringo_hz; - uint32_t pvt_ringo_0 = (*((volatile unsigned int *)(FLASH_NMPA_PVT_MONITOR_0_RINGO_ADDRS))); - uint32_t pvt_ringo_1 = (*((volatile unsigned int *)(FLASH_NMPA_PVT_MONITOR_1_RINGO_ADDRS))); - - /* - * Check that the PVT Monitors Trimmings in flash are valid. - */ - if (0UL != (pvt_ringo_0 & 0x1UL)) - { - /* PVT Trimmings in Flash are valid */ - pvt_ringo_0 = pvt_ringo_0 >> 1; - } - else - { - /* PVT Trimmings in Flash are NOT valid (average value assumed) */ - pvt_ringo_0 = PROCESS_NNN_AVG_HZ; - } - - if (0UL != (pvt_ringo_1 & 0x1UL)) - { - /* PVT Trimmings in Flash are valid */ - pvt_ringo_1 = pvt_ringo_1 >> 1; - } - else - { - /* PVT Trimmings in Flash are NOT valid (average value assumed) */ - pvt_ringo_1 = PROCESS_NNN_AVG_HZ; - } - - if (pvt_ringo_1 <= pvt_ringo_0) - { - pvt_ringo_hz = pvt_ringo_1; - } - else - { - pvt_ringo_hz = pvt_ringo_0; - } - - /* - * Determine the process corner based on the value of the Ring Oscillator frequency - */ - if (pvt_ringo_hz <= PROCESS_NNN_MIN_HZ) - { - /* SSS Process Corner */ - part_process_corner = PROCESS_CORNER_SSS; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : Process Corner : " - "SSS" - "\n"); -#endif - } - else - { - if (pvt_ringo_hz <= PROCESS_NNN_MAX_HZ) - { - /* NNN Process Corner */ - part_process_corner = PROCESS_CORNER_NNN; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : Process Corner : " - "NNN" - "\n"); -#endif - } - else - { - /* FFF Process Corner */ - part_process_corner = PROCESS_CORNER_FFF; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : Process Corner : " - "FFF" - "\n"); -#endif - } - } - - return (part_process_corner); -} - -/** - * @brief Described in fsl_common.h - * @param - * @return - */ -static void lowpower_set_voltage_for_process(lowpower_dcdc_power_profile_enum dcdc_power_profile) -{ - /* Get Sample Process Corner */ - lowpower_process_corner_enum part_process_corner = lowpower_get_part_process_corner(); - - switch (part_process_corner) - { - case PROCESS_CORNER_SSS: - /* Slow Corner */ - { - switch (dcdc_power_profile) - { - case DCDC_POWER_PROFILE_MEDIUM: - /* Medium */ - lowpower_set_system_voltage(VOLTAGE_SSS_MED_MV); - break; - - case DCDC_POWER_PROFILE_HIGH: - /* High */ - lowpower_set_system_voltage(VOLTAGE_SSS_HIG_MV); - break; - - default: - /* DCDC_POWER_PROFILE_LOW */ - lowpower_set_system_voltage(VOLTAGE_SSS_LOW_MV); - break; - } // switch(dcdc_power_profile) - } - break; - - case PROCESS_CORNER_FFF: - /* Fast Corner */ - { - switch (dcdc_power_profile) - { - case DCDC_POWER_PROFILE_MEDIUM: - /* Medium */ - lowpower_set_system_voltage(VOLTAGE_FFF_MED_MV); - break; - - case DCDC_POWER_PROFILE_HIGH: - /* High */ - lowpower_set_system_voltage(VOLTAGE_FFF_HIG_MV); - break; - - default: - /* DCDC_POWER_PROFILE_LOW */ - lowpower_set_system_voltage(VOLTAGE_FFF_LOW_MV); - break; - } // switch(dcdc_power_profile) - } - break; - - default: - /* Nominal (NNN) and all others Process Corners : assume Nominal Corner */ - { - switch (dcdc_power_profile) - { - case DCDC_POWER_PROFILE_MEDIUM: - /* Medium */ - lowpower_set_system_voltage(VOLTAGE_NNN_MED_MV); - break; - - case DCDC_POWER_PROFILE_HIGH: - /* High */ - lowpower_set_system_voltage(VOLTAGE_NNN_HIG_MV); - break; - - default: - /* DCDC_POWER_PROFILE_LOW */ - lowpower_set_system_voltage(VOLTAGE_NNN_LOW_MV); - break; - } // switch(dcdc_power_profile) - break; - } - } // switch(part_process_corner) -} - -/** - * @brief Described in fsl_common.h - * @param - * @return - */ -void POWER_SetVoltageForFreq(uint32_t system_freq_hz) -{ - if (system_freq_hz <= DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ) - { - /* [0 Hz - DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz] */ - lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_LOW); /* DCDC VOUT = 1.05 V by default */ - lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_LOW); - } - else - { - if (system_freq_hz <= DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ) - { - /* ]DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz - DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz] */ - lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_MEDIUM); /* DCDC VOUT = 1.15 V by default */ - lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_MEDIUM); - } - else - { - /* > DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz */ - lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_HIGH); /* DCDC VOUT = 1.2 V by default */ - lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_HIGH); - } - } -} - -void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, - int32_t pi32_16MfXtalPPcbParCappF_x100, - int32_t pi32_16MfXtalNPcbParCappF_x100) -{ - uint32_t u32XOTrimValue; - uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF, u8XOSlave; - int32_t iaXin_x4, ibXin, iaXout_x4, ibXout; - int32_t iXOCapInpF_x100, iXOCapOutpF_x100; - uint8_t u8XOCapInCtrl, u8XOCapOutCtrl; - uint32_t u32RegVal; - int32_t i32Tmp; - - /* Enable and set LDO, if not already done */ - POWER_SetXtal16mhzLdo(); - /* Get Cal values from Flash */ - u32XOTrimValue = GET_16MXO_TRIM(); - /* Check validity and apply */ - if ((0UL != (u32XOTrimValue & 1UL)) && (0UL != ((u32XOTrimValue >> 15UL) & 1UL))) - { - /* These fields are 7 bits, unsigned */ - u8IECXinCapCal6pF = (uint8_t)((u32XOTrimValue >> 1UL) & 0x7fUL); - u8IECXinCapCal8pF = (uint8_t)((u32XOTrimValue >> 8UL) & 0x7fUL); - u8IECXoutCapCal6pF = (uint8_t)((u32XOTrimValue >> 16UL) & 0x7fUL); - u8IECXoutCapCal8pF = (uint8_t)((u32XOTrimValue >> 23UL) & 0x7fUL); - /* This field is 1 bit */ - u8XOSlave = (uint8_t)((u32XOTrimValue >> 30UL) & 0x1UL); - /* Linear fit coefficients calculation */ - iaXin_x4 = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF; - ibXin = (int)u8IECXinCapCal6pF - iaXin_x4 * 3; - iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF; - ibXout = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3; - } - else - { - iaXin_x4 = 20; // gain in LSB/pF - ibXin = -9; // offset in LSB - iaXout_x4 = 20; // gain in LSB/pF - ibXout = -13; // offset in LSB - u8XOSlave = 0; - } - /* In & out load cap calculation with derating */ - iXOCapInpF_x100 = 2 * pi32_16MfXtalIecLoadpF_x100 - pi32_16MfXtalNPcbParCappF_x100 + - 39 * ((int32_t)XO_SLAVE_EN - (int32_t)u8XOSlave) - 15; - iXOCapOutpF_x100 = 2 * pi32_16MfXtalIecLoadpF_x100 - pi32_16MfXtalPPcbParCappF_x100 - 21; - /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */ - i32Tmp = ((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400; - u8XOCapInCtrl = (uint8_t)i32Tmp; - i32Tmp = ((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400; - u8XOCapOutCtrl = (uint8_t)i32Tmp; - /* Read register and clear fields to be written */ - u32RegVal = ANACTRL->XO32M_CTRL; - u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); - /* Configuration of 32 MHz XO output buffers */ -#if (XO_SLAVE_EN == 0) - u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); -#else - u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; -#endif - /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */ - u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT; - u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT; - /* Write back to register */ - ANACTRL->XO32M_CTRL = u32RegVal; -} - -void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, - int32_t pi32_32kfXtalPPcbParCappF_x100, - int32_t pi32_32kfXtalNPcbParCappF_x100) -{ - uint32_t u32XOTrimValue; - uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF; - int32_t iaXin_x4, ibXin, iaXout_x4, ibXout; - int32_t iXOCapInpF_x100, iXOCapOutpF_x100; - uint8_t u8XOCapInCtrl, u8XOCapOutCtrl; - uint32_t u32RegVal; - int32_t i32Tmp; - /* Get Cal values from Flash */ - u32XOTrimValue = GET_32KXO_TRIM(); - /* check validity and apply */ - if ((0UL != (u32XOTrimValue & 1UL)) && (0UL != ((u32XOTrimValue >> 15UL) & 1UL))) - { - /* These fields are 7 bits, unsigned */ - u8IECXinCapCal6pF = (uint8_t)((u32XOTrimValue >> 1UL) & 0x7fUL); - u8IECXinCapCal8pF = (uint8_t)((u32XOTrimValue >> 8UL) & 0x7fUL); - u8IECXoutCapCal6pF = (uint8_t)((u32XOTrimValue >> 16UL) & 0x7fUL); - u8IECXoutCapCal8pF = (uint8_t)((u32XOTrimValue >> 23UL) & 0x7fUL); - /* Linear fit coefficients calculation */ - iaXin_x4 = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF; - ibXin = (int)u8IECXinCapCal6pF - iaXin_x4 * 3; - iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF; - ibXout = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3; - } - else - { - iaXin_x4 = 16; // gain in LSB/pF - ibXin = 12; // offset in LSB - iaXout_x4 = 16; // gain in LSB/pF - ibXout = 11; // offset in LSB - } - - /* In & out load cap calculation with derating */ - iXOCapInpF_x100 = 2 * pi32_32kfXtalIecLoadpF_x100 - pi32_32kfXtalNPcbParCappF_x100 - 130; - iXOCapOutpF_x100 = 2 * pi32_32kfXtalIecLoadpF_x100 - pi32_32kfXtalPPcbParCappF_x100 - 41; - - /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */ - i32Tmp = ((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400; - u8XOCapInCtrl = (uint8_t)i32Tmp; - i32Tmp = ((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400; - u8XOCapOutCtrl = (uint8_t)i32Tmp; - - /* Read register and clear fields to be written */ - u32RegVal = PMC->XTAL32K; - u32RegVal &= ~(PMC_XTAL32K_CAPBANKIN_MASK | PMC_XTAL32K_CAPBANKOUT_MASK); - - /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */ - u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 23) << PMC_XTAL32K_CAPBANKIN_SHIFT; - u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 23) << PMC_XTAL32K_CAPBANKOUT_SHIFT; - - /* Write back to register */ - PMC->XTAL32K = u32RegVal; -} - -void POWER_SetXtal16mhzLdo(void) -{ - uint32_t temp; - const uint32_t u32Mask = - (ANACTRL_LDO_XO32M_VOUT_MASK | ANACTRL_LDO_XO32M_IBIAS_MASK | ANACTRL_LDO_XO32M_STABMODE_MASK); - - const uint32_t u32Value = - (ANACTRL_LDO_XO32M_VOUT(0x5) | ANACTRL_LDO_XO32M_IBIAS(0x2) | ANACTRL_LDO_XO32M_STABMODE(0x1)); - - /* Enable & set-up XTAL 32 MHz clock LDO */ - temp = ANACTRL->LDO_XO32M; - - if ((temp & u32Mask) != u32Value) - { - temp &= ~u32Mask; - - /* - * Enable the XTAL32M LDO - * Adjust the output voltage level, 0x5 for 1.1V - * Adjust the biasing current, 0x2 value - * Stability configuration, 0x1 default mode - */ - temp |= u32Value; - - ANACTRL->LDO_XO32M = temp; - - /* Delay for LDO to be up */ - // CLOCK_uDelay(20); - } - - /* Enable LDO XO32M */ - PMC->PDRUNCFGCLR0 = PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK; -} - -/** - * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes. - * @param p_reset_cause : the device reset cause, according to the definition of power_device_reset_cause_t type. - * @param p_boot_mode : the device boot mode, according to the definition of power_device_boot_mode_t type. - * @param p_wakeupio_cause: the wake-up pin sources, according to the definition of register PMC->WAKEIOCAUSE[3:0]. - - * @return Nothing - * - * !!! IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA !!! - * !!! valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06) !!! - * !!! when FALLING EDGE DETECTION is enabled on wake-up pins: !!! - * - 1. p_wakeupio_cause is NOT ACCURATE - * - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when - * several wake-up sources are enabled during DEEP-POWER-DOWN - * (like enabling wake-up on RTC and Falling edge wake-up pins) - * - */ -void POWER_GetWakeUpCause(power_device_reset_cause_t *p_reset_cause, - power_device_boot_mode_t *p_boot_mode, - uint32_t *p_wakeupio_cause) -{ - uint32_t reset_cause_reg; - uint32_t boot_mode_reg; - -#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ - defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ - defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) - reset_cause_reg = (PMC->AOREG1) & 0x3FF0UL; -#else /* LPC55S69/28 */ - reset_cause_reg = (PMC->AOREG1) & 0x1FF0UL; -#endif - - /* - * Prioritize interrupts source with respect to their critical level - */ -#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ - defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ - defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) - if (0UL != (reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK)) - { /* Code Watchdog Reset */ - *p_reset_cause = kRESET_CAUSE_CDOGRESET; - *p_boot_mode = kBOOT_MODE_POWER_UP; - *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ - } - else -#endif - { - if (0UL != (reset_cause_reg & PMC_AOREG1_WDTRESET_MASK)) - { /* Watchdog Timer Reset */ - *p_reset_cause = kRESET_CAUSE_WDTRESET; - *p_boot_mode = kBOOT_MODE_POWER_UP; - *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ - } - else - { - if (0UL != (reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK)) - { /* ARM System Reset */ - *p_reset_cause = kRESET_CAUSE_ARMSYSTEMRESET; - *p_boot_mode = kBOOT_MODE_POWER_UP; - *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ - } - else - { - boot_mode_reg = (PMC->STATUS & PMC_STATUS_BOOTMODE_MASK) >> PMC_STATUS_BOOTMODE_SHIFT; - - if (boot_mode_reg == 0UL) /* POWER-UP: Power On Reset, Pin reset, Brown Out Detectors, Software Reset */ - { - *p_boot_mode = kBOOT_MODE_POWER_UP; /* All non wake-up from a Low Power mode */ - *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ - - /* - * Prioritise Reset causes, starting from the strongest (Power On Reset) - */ - if (0UL != (reset_cause_reg & PMC_AOREG1_POR_MASK)) - { /* Power On Reset */ - *p_reset_cause = kRESET_CAUSE_POR; - } - else - { - if (0UL != (reset_cause_reg & PMC_AOREG1_BODRESET_MASK)) - { /* Brown-out Detector reset (either BODVBAT or BODCORE) */ - *p_reset_cause = kRESET_CAUSE_BODRESET; - } - else - { - if (0UL != (reset_cause_reg & PMC_AOREG1_PADRESET_MASK)) - { /* Hardware Pin Reset */ - *p_reset_cause = kRESET_CAUSE_PADRESET; - } - else - { - if (0UL != (reset_cause_reg & PMC_AOREG1_SWRRESET_MASK)) - { /* Software triggered Reset */ - *p_reset_cause = kRESET_CAUSE_SWRRESET; - } - else - { /* Unknown Reset Cause */ - *p_reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC; - } - } - } - } - -#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ - defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ - defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) - /* Transfer the control of the 4 wake-up pins to IOCON (instead of the Power Management Controller - */ - PMC->WAKEUPIOCTRL = PMC->WAKEUPIOCTRL & (~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK); -#endif - } - else /* DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN */ - { - /* - * 1- First, save wakeup_io_cause register ... - */ - *p_wakeupio_cause = PMC->WAKEIOCAUSE; - - if (boot_mode_reg == 3UL) /* DEEP-POWER-DOWN */ - { - *p_boot_mode = kBOOT_MODE_LP_DEEP_POWER_DOWN; - - switch (((reset_cause_reg >> PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT) & 0x7UL)) - { - case 1: - *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO; - break; - case 2: - *p_reset_cause = kRESET_CAUSE_DPDRESET_RTC; - break; - case 3: - *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC; - break; - case 4: - *p_reset_cause = kRESET_CAUSE_DPDRESET_OSTIMER; - break; - case 5: - *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER; - break; - case 6: - *p_reset_cause = kRESET_CAUSE_DPDRESET_RTC_OSTIMER; - break; - case 7: - *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER; - break; - default: - /* Unknown Reset Cause */ - *p_reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC; - break; - } - -#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ - defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ - defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) - /* - * 2- Next, transfer the control of the 4 wake-up pins - * to IOCON (instead of the Power Management Controller) - */ - PMC->WAKEUPIOCTRL = PMC->WAKEUPIOCTRL & (~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK); -#endif - } - else /* DEEP-SLEEP and POWER-DOWN */ - { - *p_reset_cause = kRESET_CAUSE_NOT_RELEVANT; - - /* - * The control of the 4 wake-up pins is already in IOCON, - * so there is nothing special to do. - */ - - if (boot_mode_reg == 1UL) /* DEEP-SLEEP */ - { - *p_boot_mode = kBOOT_MODE_LP_DEEP_SLEEP; - } - else /* POWER-DOWN */ - { - *p_boot_mode = kBOOT_MODE_LP_POWER_DOWN; - - } /* if ( boot_mode_reg == 1 ) DEEP-SLEEP */ - - } /* if ( boot_mode == 3 ) DEEP-POWER-DOWN */ - - } /* if ( boot_mode == 0 ) POWER-UP */ - - } /* if ( reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK ) */ - - } /* if ( reset_cause_reg & PMC_AOREG1_WDTRESET_MASK ) */ - - } /* if ( reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK ) */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_power.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_power.h deleted file mode 100644 index 6a9de7a9f50..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_power.h +++ /dev/null @@ -1,611 +0,0 @@ -/* - * Copyright 2017, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_POWER_H_ -#define _FSL_POWER_H_ - -#include "fsl_common.h" -#include "fsl_device_registers.h" -#include - -/*! - * @addtogroup power - * @{ - */ -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief power driver version 1.0.0. */ -#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) -/*@}*/ - -/* Power mode configuration API parameter */ -typedef enum _power_mode_config -{ - kPmu_Sleep = 0U, - kPmu_Deep_Sleep = 1U, - kPmu_PowerDown = 2U, - kPmu_Deep_PowerDown = 3U, -} power_mode_cfg_t; - -/** - * @brief Analog components power modes control during low power modes - */ -typedef enum pd_bits -{ - kPDRUNCFG_PD_DCDC = (1UL << 0), - kPDRUNCFG_PD_BIAS = (1UL << 1), - kPDRUNCFG_PD_BODCORE = (1UL << 2), - kPDRUNCFG_PD_BODVBAT = (1UL << 3), - kPDRUNCFG_PD_FRO1M = (1UL << 4), - kPDRUNCFG_PD_FRO192M = (1UL << 5), - kPDRUNCFG_PD_FRO32K = (1UL << 6), - kPDRUNCFG_PD_XTAL32K = (1UL << 7), - kPDRUNCFG_PD_XTAL32M = (1UL << 8), - kPDRUNCFG_PD_PLL0 = (1UL << 9), - kPDRUNCFG_PD_PLL1 = (1UL << 10), - kPDRUNCFG_PD_USB0_PHY = (1UL << 11), - kPDRUNCFG_PD_USB1_PHY = (1UL << 12), - kPDRUNCFG_PD_COMP = (1UL << 13), - kPDRUNCFG_PD_TEMPSENS = (1UL << 14), - kPDRUNCFG_PD_GPADC = (1UL << 15), - kPDRUNCFG_PD_LDOMEM = (1UL << 16), - kPDRUNCFG_PD_LDODEEPSLEEP = (1UL << 17), - kPDRUNCFG_PD_LDOUSBHS = (1UL << 18), - kPDRUNCFG_PD_LDOGPADC = (1UL << 19), - kPDRUNCFG_PD_LDOXO32M = (1UL << 20), - kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21), - kPDRUNCFG_PD_RNG = (1UL << 22), - kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23), - kPDRUNCFG_PD_ROM = (1UL << 24), - /* - This enum member has no practical meaning,it is used to avoid MISRA issue, - user should not trying to use it. - */ - kPDRUNCFG_ForceUnsigned = 0x80000000U, -} pd_bit_t; - -/*! @brief BOD VBAT level */ -typedef enum _power_bod_vbat_level -{ - kPOWER_BodVbatLevel1000mv = 0, /*!< Brown out detector VBAT level 1V */ - kPOWER_BodVbatLevel1100mv = 1, /*!< Brown out detector VBAT level 1.1V */ - kPOWER_BodVbatLevel1200mv = 2, /*!< Brown out detector VBAT level 1.2V */ - kPOWER_BodVbatLevel1300mv = 3, /*!< Brown out detector VBAT level 1.3V */ - kPOWER_BodVbatLevel1400mv = 4, /*!< Brown out detector VBAT level 1.4V */ - kPOWER_BodVbatLevel1500mv = 5, /*!< Brown out detector VBAT level 1.5V */ - kPOWER_BodVbatLevel1600mv = 6, /*!< Brown out detector VBAT level 1.6V */ - kPOWER_BodVbatLevel1650mv = 7, /*!< Brown out detector VBAT level 1.65V */ - kPOWER_BodVbatLevel1700mv = 8, /*!< Brown out detector VBAT level 1.7V */ - kPOWER_BodVbatLevel1750mv = 9, /*!< Brown out detector VBAT level 1.75V */ - kPOWER_BodVbatLevel1800mv = 10, /*!< Brown out detector VBAT level 1.8V */ - kPOWER_BodVbatLevel1900mv = 11, /*!< Brown out detector VBAT level 1.9V */ - kPOWER_BodVbatLevel2000mv = 12, /*!< Brown out detector VBAT level 2V */ - kPOWER_BodVbatLevel2100mv = 13, /*!< Brown out detector VBAT level 2.1V */ - kPOWER_BodVbatLevel2200mv = 14, /*!< Brown out detector VBAT level 2.2V */ - kPOWER_BodVbatLevel2300mv = 15, /*!< Brown out detector VBAT level 2.3V */ - kPOWER_BodVbatLevel2400mv = 16, /*!< Brown out detector VBAT level 2.4V */ - kPOWER_BodVbatLevel2500mv = 17, /*!< Brown out detector VBAT level 2.5V */ - kPOWER_BodVbatLevel2600mv = 18, /*!< Brown out detector VBAT level 2.6V */ - kPOWER_BodVbatLevel2700mv = 19, /*!< Brown out detector VBAT level 2.7V */ - kPOWER_BodVbatLevel2806mv = 20, /*!< Brown out detector VBAT level 2.806V */ - kPOWER_BodVbatLevel2900mv = 21, /*!< Brown out detector VBAT level 2.9V */ - kPOWER_BodVbatLevel3000mv = 22, /*!< Brown out detector VBAT level 3.0V */ - kPOWER_BodVbatLevel3100mv = 23, /*!< Brown out detector VBAT level 3.1V */ - kPOWER_BodVbatLevel3200mv = 24, /*!< Brown out detector VBAT level 3.2V */ - kPOWER_BodVbatLevel3300mv = 25, /*!< Brown out detector VBAT level 3.3V */ -} power_bod_vbat_level_t; - -/*! @brief BOD Hysteresis control */ -typedef enum _power_bod_hyst -{ - kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */ - kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */ - kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */ - kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */ -} power_bod_hyst_t; - -/*! @brief BOD core level */ -typedef enum _power_bod_core_level -{ - kPOWER_BodCoreLevel600mv = 0, /*!< Brown out detector core level 600mV */ - kPOWER_BodCoreLevel650mv = 1, /*!< Brown out detector core level 650mV */ - kPOWER_BodCoreLevel700mv = 2, /*!< Brown out detector core level 700mV */ - kPOWER_BodCoreLevel750mv = 3, /*!< Brown out detector core level 750mV */ - kPOWER_BodCoreLevel800mv = 4, /*!< Brown out detector core level 800mV */ - kPOWER_BodCoreLevel850mv = 5, /*!< Brown out detector core level 850mV */ - kPOWER_BodCoreLevel900mv = 6, /*!< Brown out detector core level 900mV */ - kPOWER_BodCoreLevel950mv = 7, /*!< Brown out detector core level 950mV */ -} power_bod_core_level_t; - -/** - * @brief Device Reset Causes - */ -typedef enum _power_device_reset_cause -{ - kRESET_CAUSE_POR = 0UL, /*!< Power On Reset */ - kRESET_CAUSE_PADRESET = 1UL, /*!< Hardware Pin Reset */ - kRESET_CAUSE_BODRESET = 2UL, /*!< Brown-out Detector reset (either BODVBAT or BODCORE) */ - kRESET_CAUSE_ARMSYSTEMRESET = 3UL, /*!< ARM System Reset */ - kRESET_CAUSE_WDTRESET = 4UL, /*!< Watchdog Timer Reset */ - kRESET_CAUSE_SWRRESET = 5UL, /*!< Software Reset */ - kRESET_CAUSE_CDOGRESET = 6UL, /*!< Code Watchdog Reset */ - /* Reset causes in DEEP-POWER-DOWN low power mode */ - kRESET_CAUSE_DPDRESET_WAKEUPIO = 7UL, /*!< Any of the 4 wake-up pins */ - kRESET_CAUSE_DPDRESET_RTC = 8UL, /*!< Real Time Counter (RTC) */ - kRESET_CAUSE_DPDRESET_OSTIMER = 9UL, /*!< OS Event Timer (OSTIMER) */ - kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC = 10UL, /*!< Any of the 4 wake-up pins and RTC (it is not possible to distinguish - which of these 2 events occured first) */ - kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER = 11UL, /*!< Any of the 4 wake-up pins and OSTIMER (it is not possible to - distinguish which of these 2 events occured first) */ - kRESET_CAUSE_DPDRESET_RTC_OSTIMER = 12UL, /*!< Real Time Counter or OS Event Timer (it is not possible to - distinguish which of these 2 events occured first) */ - kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER = 13UL, /*!< Any of the 4 wake-up pins (it is not possible to distinguish - which of these 3 events occured first) */ - /* Miscallenous */ - kRESET_CAUSE_NOT_RELEVANT = - 14UL, /*!< No reset cause (for example, this code is used when waking up from DEEP-SLEEP low power mode) */ - kRESET_CAUSE_NOT_DETERMINISTIC = 15UL, /*!< Unknown Reset Cause. Should be treated like "Hardware Pin Reset" from an - application point of view. */ -} power_device_reset_cause_t; - -/** - * @brief Device Boot Modes - */ -typedef enum _power_device_boot_mode -{ - kBOOT_MODE_POWER_UP = - 0UL, /*!< All non Low Power Mode wake up (Power On Reset, Pin Reset, BoD Reset, ARM System Reset ... ) */ - kBOOT_MODE_LP_DEEP_SLEEP = 1UL, /*!< Wake up from DEEP-SLEEP Low Power mode */ - kBOOT_MODE_LP_POWER_DOWN = 2UL, /*!< Wake up from POWER-DOWN Low Power mode */ - kBOOT_MODE_LP_DEEP_POWER_DOWN = 4UL, /*!< Wake up from DEEP-POWER-DOWN Low Power mode */ -} power_device_boot_mode_t; - -/** - * @brief SRAM instances retention control during low power modes - */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 \ - (1UL << 0) /*!< Enable SRAMX_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 \ - (1UL << 1) /*!< Enable SRAMX_1 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 \ - (1UL << 2) /*!< Enable SRAMX_2 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 \ - (1UL << 3) /*!< Enable SRAMX_3 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM00 \ - (1UL << 4) /*!< Enable SRAM0_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM01 \ - (1UL << 5) /*!< Enable SRAM0_1 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM10 \ - (1UL << 6) /*!< Enable SRAM1_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM20 \ - (1UL << 7) /*!< Enable SRAM2_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM30 \ - (1UL << 8) /*!< Enable SRAM3_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM31 \ - (1UL << 9) /*!< Enable SRAM3_1 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM40 \ - (1UL << 10) /*!< Enable SRAM4_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM41 \ - (1UL << 11) /*!< Enable SRAM4_1 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM42 \ - (1UL << 12) /*!< Enable SRAM4_2 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM43 \ - (1UL << 13) /*!< Enable SRAM4_3 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_USB_HS \ - (1UL << 14) /*!< Enable SRAM USB HS retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_PUF \ - (1UL << 15) /*!< Enable SRAM PUFF retention when entering in Low power modes */ - -/** - * @brief Low Power Modes Wake up sources - */ -#define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/ -#define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */ -#define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */ -#define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */ -#define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */ -#define WAKEUP_ACMP_CAPT (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -// reserved (1ULL << 25) -// reserved (1ULL << 26) -#define WAKEUP_USB0_NEEDCLK (1ULL << 27) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_USB0 (1ULL << 28) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ -#define WAKEUP_EZH_ARCH_B (1ULL << 30) /*!< [SLEEP, ] */ -#define WAKEUP_WAKEUP_MAILBOX (1ULL << 31) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ -// reserved (1ULL << 39) -// reserved (1ULL << 40) -// reserved (1ULL << 41) -#define WAKEUP_SDIO (1ULL << 42) /*!< [SLEEP, ] */ -// reserved (1ULL << 43) -// reserved (1ULL << 44) -// reserved (1ULL << 45) -// reserved (1ULL << 46) -#define WAKEUP_USB1 (1ULL << 47) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_USB1_NEEDCLK (1ULL << 48) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */ -#define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SEC_VIO (1ULL << 53) -#define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */ -#define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */ -#define WAKEUP_PUFF (1ULL << 56) /*!< [SLEEP, ] */ -#define WAKEUP_PQ (1ULL << 57) /*!< [SLEEP, ] */ -#define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */ -// reserved WAKEUP_PVTVF0_AMBER (1ULL << 60) -// reserved WAKEUP_PVTVF0_RED (1ULL << 61) -// reserved WAKEUP_PVTVF1_AMBER (1ULL << 62) -#define WAKEUP_ALLWAKEUPIOS (1ULL << 63) /*!< [ , DEEP POWER DOWN] */ - -/** - * @brief Sleep Postpone - */ -#define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */ -#define LOWPOWER_HWWAKE_PERIPHERALS \ - (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause \ - peripheral clocking to wake up temporarily while the related status is asserted */ -#define LOWPOWER_HWWAKE_SDMA0 \ - (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA \ - completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ -#define LOWPOWER_HWWAKE_SDMA1 \ - (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA \ - completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ -#define LOWPOWER_HWWAKE_ENABLE_FRO192M \ - (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of \ - LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set */ - -#define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */ -#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */ -/** - * @brief Wake up I/O sources - */ -#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */ -#define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */ -#define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */ -#define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */ - -#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */ -#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */ -#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */ -#define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */ - -#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX 8 /*!< Wake-up I/O 0 pull-up/down configuration index */ -#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX 9 /*!< Wake-up I/O 1 pull-up/down configuration index */ -#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX 10 /*!< Wake-up I/O 2 pull-up/down configuration index */ -#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX 11 /*!< Wake-up I/O 3 pull-up/down configuration index */ - -#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down mask */ -#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down mask */ -#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down mask */ -#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down mask */ - -#define LOWPOWER_WAKEUPIO_PULLDOWN 0 /*!< Select pull-down */ -#define LOWPOWER_WAKEUPIO_PULLUP 1 /*!< Select pull-up */ - -#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX \ - 12 /*!< Wake-up I/O 0 pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX \ - 13 /*!< Wake-up I/O 1 pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX \ - 14 /*!< Wake-up I/O 2 pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX \ - 15 /*!< Wake-up I/O 3 pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down disable/enable mask */ -#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down disable/enable mask */ -#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down disable/enable mask */ -#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down disable/enable mask */ - -#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX \ - (16) /*!< Wake-up I/O 0 use external pull-up/down disable/enable control index*/ -#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX \ - (17) /*!< Wake-up I/O 1 use external pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX \ - (18) /*!< Wake-up I/O 2 use external pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX \ - (19) /*!< Wake-up I/O 3 use external pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 use external pull-up/down \ - disable/enable mask, 0: disable, 1: enable */ -#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 use external pull-up/down \ - disable/enable mask, 0: disable, 1: enable */ -#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 use external pull-up/down \ - disable/enable mask, 0: disable, 1: enable */ -#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 use external pull-up/down \ - disable/enable mask, 0: disable, 1: enable */ - -#ifdef __cplusplus -extern "C" { -#endif -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral - * - * @param en peripheral for which to enable the PDRUNCFG bit - * @return none - */ -static inline void POWER_EnablePD(pd_bit_t en) -{ - /* PDRUNCFGSET */ - PMC->PDRUNCFGSET0 = (uint32_t)en; -} - -/*! - * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral - * - * @param en peripheral for which to disable the PDRUNCFG bit - * @return none - */ -static inline void POWER_DisablePD(pd_bit_t en) -{ - /* PDRUNCFGCLR */ - PMC->PDRUNCFGCLR0 = (uint32_t)en; -} - -/*! - * @brief set BOD VBAT level. - * - * @param level BOD detect level - * @param hyst BoD Hysteresis control - * @param enBodVbatReset VBAT brown out detect reset - */ -static inline void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset) -{ - PMC->BODVBAT = (PMC->BODVBAT & (~(PMC_BODVBAT_TRIGLVL_MASK | PMC_BODVBAT_HYST_MASK))) | PMC_BODVBAT_TRIGLVL(level) | - PMC_BODVBAT_HYST(hyst); - PMC->RESETCTRL = - (PMC->RESETCTRL & (~PMC_RESETCTRL_BODVBATRESETENABLE_MASK)) | PMC_RESETCTRL_BODVBATRESETENABLE(enBodVbatReset); -} - -#if defined(PMC_BODCORE_TRIGLVL_MASK) -/*! - * @brief set BOD core level. - * - * @param level BOD detect level - * @param hyst BoD Hysteresis control - * @param enBodCoreReset core brown out detect reset - */ -static inline void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset) -{ - PMC->BODCORE = (PMC->BODCORE & (~(PMC_BODCORE_TRIGLVL_MASK | PMC_BODCORE_HYST_MASK))) | PMC_BODCORE_TRIGLVL(level) | - PMC_BODCORE_HYST(hyst); - PMC->RESETCTRL = - (PMC->RESETCTRL & (~PMC_RESETCTRL_BODCORERESETENABLE_MASK)) | PMC_RESETCTRL_BODCORERESETENABLE(enBodCoreReset); -} -#endif - -/*! - * @brief API to enable deep sleep bit in the ARM Core. - * - * @return none - */ -static inline void POWER_EnableDeepSleep(void) -{ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; -} - -/*! - * @brief API to disable deep sleep bit in the ARM Core. - * - * @return none - */ -static inline void POWER_DisableDeepSleep(void) -{ - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; -} - -/** - * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event - * This MUST BE EXECUTED outside the Flash: - * either from ROM or from SRAM. The rest could stay in Flash. But, for consistency, it is - * preferable to have all functions defined in this file implemented in ROM. - * - * @return Nothing - */ -void POWER_CycleCpuAndFlash(void); - -/** - * @brief Configures and enters in DEEP-SLEEP low power mode - * @param exclude_from_pd: - * @param sram_retention_ctrl: - * @param wakeup_interrupts: - * @param hardware_wake_ctrl: - - * @return Nothing - * - * !!! IMPORTANT NOTES : - 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. - * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in - case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). - * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be - restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip - reset) reset) - */ -void POWER_EnterDeepSleep(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t hardware_wake_ctrl); - -/** - * @brief Configures and enters in POWERDOWN low power mode - * @param exclude_from_pd: - * @param sram_retention_ctrl: - * @param wakeup_interrupts: - * @param cpu_retention_ctrl: 0 = CPU retention is disable / 1 = CPU retention is enabled, all other values are - RESERVED. - - * @return Nothing - * - * !!! IMPORTANT NOTES : - 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. - * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in - case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). - * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be - restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance - containing the stack used to call this function WILL BE preserved during low power (via parameter - "sram_retention_ctrl") - * 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip - reset) reset) - */ - -void POWER_EnterPowerDown(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t cpu_retention_ctrl); - -/** - * @brief Configures and enters in DEEPPOWERDOWN low power mode - * @param exclude_from_pd: - * @param sram_retention_ctrl: - * @param wakeup_interrupts: - * @param wakeup_io_ctrl: - - * @return Nothing - * - * !!! IMPORTANT NOTES : - 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. - * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back if - DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be - restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip - reset) - */ -void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t wakeup_io_ctrl); - -/** - * @brief Configures and enters in SLEEP low power mode - * @param : - * @return Nothing - */ -void POWER_EnterSleep(void); - -/*! - * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency. - * - * @param system_freq_hz - The desired frequency (in Hertz) at which the part would like to operate, - * note that the voltage and flash wait states should be set before changing frequency - * @return none - */ -void POWER_SetVoltageForFreq(uint32_t system_freq_hz); - -/** - * @brief Sets board-specific trim values for 16MHz XTAL - * @param pi32_16MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 - * @param pi32_16MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF - * becomes 120 - * @param pi32_16MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF - * becomes 120 - * @return none - * @note Following default Values can be used: - * pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 - * pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20 - * pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 - */ -extern void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, - int32_t pi32_16MfXtalPPcbParCappF_x100, - int32_t pi32_16MfXtalNPcbParCappF_x100); -/** - * @brief Sets board-specific trim values for 32kHz XTAL - * @param pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 - * @param pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF - becomes 120 - * @param pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF - becomes 120 - - * @return none - * @note Following default Values can be used: - * pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 - * pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40 - * pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 - */ -extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, - int32_t pi32_32kfXtalPPcbParCappF_x100, - int32_t pi32_32kfXtalNPcbParCappF_x100); -/** - * @brief Enables and sets LDO for 16MHz XTAL - * - * @return none - */ -extern void POWER_SetXtal16mhzLdo(void); - -/** - * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes. - * @param p_reset_cause : the device reset cause, according to the definition of power_device_reset_cause_t type. - * @param p_boot_mode : the device boot mode, according to the definition of power_device_boot_mode_t type. - * @param p_wakeupio_cause: the wake-up pin sources, according to the definition of register PMC->WAKEIOCAUSE[3:0]. - - * @return Nothing - * - * !!! IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA !!! - * !!! valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06) !!! - * !!! when FALLING EDGE DETECTION is enabled on wake-up pins: !!! - * - 1. p_wakeupio_cause is NOT ACCURATE - * - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when - * several wake-up sources are enabled during DEEP-POWER-DOWN - * (like enabling wake-up on RTC and Falling edge wake-up pins) - * - */ -void POWER_GetWakeUpCause(power_device_reset_cause_t *p_reset_cause, - power_device_boot_mode_t *p_boot_mode, - uint32_t *p_wakeupio_cause); -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* _FSL_POWER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_prince.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_prince.c deleted file mode 100644 index 63e4c278528..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_prince.c +++ /dev/null @@ -1,1096 +0,0 @@ -/* - * Copyright 2018 - 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_prince.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ - -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.prince" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -static secure_bool_t PRINCE_CheckerAlgorithm(uint32_t address, - uint32_t length, - prince_flags_t flag, - flash_config_t *flash_context) -{ - uint32_t temp_base = 0, temp_sr = 0, region_index = 0, contiguous_start_index = 0, contiguous_end_index = 32; - secure_bool_t is_prince_region_contiguous = kSECURE_TRUE; - uint8_t prince_iv_code[FLASH_FFR_IV_CODE_SIZE] = {0}; - - if (address >= flash_context->ffrConfig.ffrBlockBase) - { - /* If it is not in flash region, return true to allow erase/write operation. */ - return kSECURE_TRUE; - } - - /* Iterate for all PRINCE regions */ - for (region_index = (uint32_t)kPRINCE_Region0; region_index <= (uint32_t)kPRINCE_Region2; region_index++) - { - contiguous_start_index = 0; - contiguous_end_index = 32; - switch (region_index) - { - case (uint32_t)kPRINCE_Region0: - temp_base = PRINCE->BASE_ADDR0; - temp_sr = PRINCE->SR_ENABLE0; - break; - - case (uint32_t)kPRINCE_Region1: - temp_base = PRINCE->BASE_ADDR1; - temp_sr = PRINCE->SR_ENABLE1; - break; - - case (uint32_t)kPRINCE_Region2: - temp_base = PRINCE->BASE_ADDR2; - temp_sr = PRINCE->SR_ENABLE2; - break; - - default: - /* All the cases have been listed above, the default clause should not be reached. */ - break; - } - - if (((address >= temp_base) && - ((address + length) < (temp_base + (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 32U * 1024U)))) && - (temp_sr != 0U)) - { - /* Check if the mask is contiguous */ - secure_bool_t first_set_bit_found = kSECURE_FALSE; - secure_bool_t contiguous_end_found = kSECURE_FALSE; - for (uint32_t i = 0; i < 32U; i++) - { - if (0U != (temp_sr & (1UL << i))) - { - if (kSECURE_FALSE == first_set_bit_found) - { - first_set_bit_found = kSECURE_TRUE; - contiguous_start_index = i; - } - if (kSECURE_TRUE == contiguous_end_found) - { - is_prince_region_contiguous = kSECURE_FALSE; - break; - } - } - else - { - if ((kSECURE_TRUE == first_set_bit_found) && (kSECURE_FALSE == contiguous_end_found)) - { - contiguous_end_found = kSECURE_TRUE; - contiguous_end_index = i; - } - } - } - } - else - { - continue; /* No encryption enabled, continue with the next region checking. */ - } - - /* Check if the provided memory range covers all addresses defined in the SR mask */ - if ((kSECURE_TRUE == is_prince_region_contiguous) && - ((address <= (temp_base + (contiguous_start_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U)))) && - (((address + length) >= - (temp_base + (contiguous_end_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U))))) - { - /* In case of erase operation, invalidate the old PRINCE IV by regenerating the new one */ - if (kPRINCE_Flag_EraseCheck == flag) - { - /* Re-generate the PRINCE IV in case of erase operation */ - - /* Generate new IV code for the PRINCE region and store the new IV into the respective FFRs */ - if (kStatus_Success == - PRINCE_GenNewIV((prince_region_t)region_index, &prince_iv_code[0], true, flash_context)) - { - /* Store the new IV for the PRINCE region into PRINCE registers. */ - if (kStatus_Success == PRINCE_LoadIV((prince_region_t)region_index, &prince_iv_code[0])) - { - /* Encryption is enabled, all subregions are to be erased/written at once, IV successfully - * regenerated, return true to allow erase operation. */ - return kSECURE_TRUE; - } - } - /* Encryption is enabled, all subregions are to be erased/written at once but IV has not been correctly - * regenerated, return false to disable erase operation. */ - return kSECURE_FALSE; - } - - /* Encryption is enabled and all subregions are to be erased/written at once, return true to allow - * erase/write operation. */ - return kSECURE_TRUE; - } - /* The provided memory range does not cover all addresses defined in the SR mask. */ - else - { - /* Is the provided memory range outside the addresses defined by the SR mask? */ - if ((kSECURE_TRUE == is_prince_region_contiguous) && - ((((address + length) <= - (temp_base + (contiguous_start_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U)))) || - ((address >= (temp_base + (contiguous_end_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U)))))) - { - /* No encryption enabled for the provided memory range, true could be returned to allow erase/write - operation, but due to the same base address for all three prince regions on Niobe4Mini we should - continue with other regions (SR mask) checking. */ - continue; - } - else - { - /* Encryption is enabled but not all subregions are to be erased/written at once, return false to - * disable erase/write operation. */ - return kSECURE_FALSE; - } - } - } - return kSECURE_TRUE; -} -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Generate new IV code. - * - * This function generates new IV code and stores it into the persistent memory. - * Ensure about 800 bytes free space on the stack when calling this routine with the store parameter set to true! - * - * @param region PRINCE region index. - * @param iv_code IV code pointer used for storing the newly generated 52 bytes long IV code. - * @param store flag to allow storing the newly generated IV code into the persistent memory (FFR). - * @param flash_context pointer to the flash driver context structure. - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise, kStatus_Fail is also returned if the key code for the particular - * PRINCE region is not present in the keystore (though new IV code has been provided) - */ -status_t PRINCE_GenNewIV(prince_region_t region, uint8_t *iv_code, bool store, flash_config_t *flash_context) -{ - status_t status = kStatus_Fail; - uint8_t prince_iv_code[FLASH_FFR_IV_CODE_SIZE] = {0}; - uint8_t tempBuffer[FLASH_FFR_MAX_PAGE_SIZE] = {0}; - - /* Make sure PUF is started to allow key and IV code decryption and generation */ - if (true != PUF_IsGetKeyAllowed(PUF)) - { - return status; - } - - /* Generate new IV code for the PRINCE region */ - status = - PUF_SetIntrinsicKey(PUF, (puf_key_index_register_t)(uint32_t)((uint32_t)kPUF_KeyIndex_02 + (uint32_t)region), 8, - &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); - if ((kStatus_Success == status) && (true == store)) - { - /* Store the new IV code for the PRINCE region into the respective FFRs. */ - /* Create a new version of "Customer Field Programmable" (CFP) page. */ - if ((int32_t)kStatus_FLASH_Success == - FFR_GetCustomerInfieldData(flash_context, (uint8_t *)tempBuffer, 0, FLASH_FFR_MAX_PAGE_SIZE)) - { - /* Set the IV code in the page */ - (void)memcpy(&tempBuffer[offsetof(cfpa_cfg_info_t, ivCodePrinceRegion) + - (((uint32_t)region * sizeof(cfpa_cfg_iv_code_t))) + 4U], - &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); - - uint32_t *p32 = (uint32_t *)(uint32_t)tempBuffer; - uint32_t version = p32[1]; - if (version == 0xFFFFFFFFu) - { - return kStatus_Fail; - } - version++; - p32[1] = version; - - /* Program the page and enable firewall for "Customer field area" */ - if ((int32_t)kStatus_FLASH_Success == - FFR_InfieldPageWrite(flash_context, (uint8_t *)tempBuffer, FLASH_FFR_MAX_PAGE_SIZE)) - { - status = kStatus_Success; - } - else - { - status = kStatus_Fail; - } - } - } - if (status == kStatus_Success) - { - /* Pass the new IV code */ - (void)memcpy(iv_code, &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); - } - - return status; -} -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Load IV code. - * - * This function enables IV code loading into the PRINCE bus encryption engine. - * - * @param region PRINCE region index. - * @param iv_code IV code pointer used for passing the IV code. - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise - */ -status_t PRINCE_LoadIV(prince_region_t region, uint8_t *iv_code) -{ - status_t status = kStatus_Fail; - uint32_t keyIndex = (0x0Fu & (uint32_t)iv_code[1]); - uint8_t prince_iv[8] = {0}; - - /* Make sure PUF is started to allow key and IV code decryption and generation */ - if (true != PUF_IsGetKeyAllowed(PUF)) - { - return kStatus_Fail; - } - - /* Check if region number matches the PUF index value */ - if (((uint32_t)kPUF_KeyIndex_02 + (uint32_t)region) == (uint32_t)keyIndex) - { - /* Decrypt the IV */ - if (kStatus_Success == PUF_GetKey(PUF, iv_code, FLASH_FFR_IV_CODE_SIZE, &prince_iv[0], 8)) - { - /* Store the new IV for the PRINCE region into PRINCE registers. */ - (void)PRINCE_SetRegionIV(PRINCE, (prince_region_t)region, prince_iv); - status = kStatus_Success; - } - } - - return status; -} -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Allow encryption/decryption for specified address range. - * - * This function sets the encryption/decryption for specified address range. - * The SR mask value for the selected Prince region is calculated from provided - * start_address and length parameters. This calculated value is OR'ed with the - * actual SR mask value and stored into the PRINCE SR_ENABLE register and also - * into the persistent memory (FFR) to be used after the device reset. It is - * possible to define several nonadjacent encrypted areas within one Prince - * region when calling this function repeatedly. If the length parameter is set - * to 0, the SR mask value is set to 0 and thus the encryption/decryption for - * the whole selected Prince region is disabled. - * Ensure about 800 bytes free space on the stack when calling this routine! - * - * @param region PRINCE region index. - * @param start_address start address of the area to be encrypted/decrypted. - * @param length length of the area to be encrypted/decrypted. - * @param flash_context pointer to the flash driver context structure. - * @param regenerate_iv flag to allow IV code regenerating, storing into - * the persistent memory (FFR) and loading into the PRINCE engine - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise - */ -status_t PRINCE_SetEncryptForAddressRange( - prince_region_t region, uint32_t start_address, uint32_t length, flash_config_t *flash_context, bool regenerate_iv) -{ - status_t status = kStatus_Fail; - uint32_t srEnableRegister = 0; - uint32_t alignedStartAddress; - uint32_t prince_base_addr_ffr_word = 0; - uint32_t end_address = start_address + length; - uint32_t prince_region_base_address = 0; - uint8_t tempBuffer[FLASH_FFR_MAX_PAGE_SIZE] = {0}; - - /* Check input parameters. */ - if (NULL == flash_context) - { - return kStatus_Fail; - } - - /* Check the address range, region borders crossing. */ -#if (defined(FSL_PRINCE_DRIVER_LPC55S0x)) || (defined(FSL_PRINCE_DRIVER_LPC55S1x)) || \ - (defined(FSL_PRINCE_DRIVER_LPC55S2x)) || (defined(FSL_PRINCE_DRIVER_LPC55S3x)) - if ((start_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) || - ((start_address < FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) && (end_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR))) - { - return kStatus_Fail; - } -#endif -#if (defined(FSL_PRINCE_DRIVER_LPC55S6x)) - if ((start_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) || - ((start_address < 0x40000U) && (end_address > 0x40000U)) || - ((start_address < 0x80000U) && (end_address > 0x80000U)) || - ((start_address < FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) && (end_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR))) - { - return kStatus_Fail; - } -#endif - - if (true == regenerate_iv) - { - uint8_t prince_iv_code[FLASH_FFR_IV_CODE_SIZE] = {0}; - - /* Generate new IV code for the PRINCE region and store the new IV into the respective FFRs */ - status = PRINCE_GenNewIV((prince_region_t)region, &prince_iv_code[0], true, flash_context); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - /* Store the new IV for the PRINCE region into PRINCE registers. */ - status = PRINCE_LoadIV((prince_region_t)region, &prince_iv_code[0]); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - } - - alignedStartAddress = ALIGN_DOWN(start_address, (int32_t)FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024); - - uint32_t subregion = alignedStartAddress / (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U); - if (subregion < (32U)) - { - /* PRINCE_Region0 */ - prince_region_base_address = 0; - } - else if (subregion < (64U)) - { - /* PRINCE_Region1 */ - subregion = subregion - 32U; - prince_region_base_address = 0x40000; - } - else - { - /* PRINCE_Region2 */ - subregion = subregion - 64U; - prince_region_base_address = 0x80000; - } - - /* If length > 0 then srEnableRegister mask is set based on the alignedStartAddress and the length. - If the length is 0, srEnableRegister should be kept 0 (no subregion enabled). */ - if (length != 0U) - { - srEnableRegister = (1UL << subregion); - alignedStartAddress += (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U); - - while (alignedStartAddress < (start_address + length)) - { - subregion++; - srEnableRegister |= (1UL << subregion); - alignedStartAddress += (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U); - } - - uint32_t srEnableRegisterActual = 0; - (void)PRINCE_GetRegionSREnable(PRINCE, (prince_region_t)region, &srEnableRegisterActual); - srEnableRegister |= srEnableRegisterActual; - } - - /* Store BASE_ADDR into PRINCE register before storing the SR to avoid en/decryption triggering - from addresses being defined by current BASE_ADDR register content (could be 0 and the decryption - of actually executed code can be started causing the hardfault then). */ - status = PRINCE_SetRegionBaseAddress(PRINCE, (prince_region_t)region, prince_region_base_address); - if (kStatus_Success != status) - { - return status; - } - - /* Store SR into PRINCE register */ - status = PRINCE_SetRegionSREnable(PRINCE, (prince_region_t)region, srEnableRegister); - if (kStatus_Success != status) - { - return status; - } - - /* Store SR and BASE_ADDR into CMPA FFR */ - if (kStatus_Success == FFR_GetCustomerData(flash_context, (uint8_t *)&tempBuffer, 0, FLASH_FFR_MAX_PAGE_SIZE)) - { - /* Set the PRINCE_SR_X in the page */ - (void)memcpy((uint32_t *)(uintptr_t)&tempBuffer[offsetof(cmpa_cfg_info_t, princeSr) + - ((uint32_t)region * sizeof(uint32_t))], - &srEnableRegister, sizeof(uint32_t)); - /* Set the ADDRX_PRG in the page */ - (void)memcpy(&prince_base_addr_ffr_word, - (const uint32_t *)(uintptr_t)&tempBuffer[offsetof(cmpa_cfg_info_t, princeBaseAddr)], - sizeof(uint32_t)); - prince_base_addr_ffr_word &= - ~(((uint32_t)FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) << ((uint32_t)region * 4U)); - prince_base_addr_ffr_word |= (((prince_region_base_address >> PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT) & - FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) - << ((uint32_t)region * 4U)); - (void)memcpy((uint32_t *)(uintptr_t)&tempBuffer[offsetof(cmpa_cfg_info_t, princeBaseAddr)], - &prince_base_addr_ffr_word, sizeof(uint32_t)); - - /* Program the CMPA page, set seal_part parameter to false (used during development to avoid sealing the - * part) - */ - status = FFR_CustFactoryPageWrite(flash_context, (uint8_t *)tempBuffer, false); - } - - return status; -} -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -/*! - * @brief Gets the PRINCE Sub-Region Enable register. - * - * This function gets PRINCE SR_ENABLE register. - * - * @param base PRINCE peripheral address. - * @param region PRINCE region index. - * @param sr_enable Sub-Region Enable register pointer. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_GetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t *sr_enable) -{ - status_t status = kStatus_Success; - - switch (region) - { - case kPRINCE_Region0: - *sr_enable = base->SR_ENABLE0; - break; - - case kPRINCE_Region1: - *sr_enable = base->SR_ENABLE1; - break; - - case kPRINCE_Region2: - *sr_enable = base->SR_ENABLE2; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - return status; -} - -/*! - * @brief Gets the PRINCE region base address register. - * - * This function gets PRINCE BASE_ADDR register. - * - * @param base PRINCE peripheral address. - * @param region PRINCE region index. - * @param region_base_addr Region base address pointer. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_GetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t *region_base_addr) -{ - status_t status = kStatus_Success; - - switch (region) - { - case kPRINCE_Region0: - *region_base_addr = base->BASE_ADDR0; - break; - - case kPRINCE_Region1: - *region_base_addr = base->BASE_ADDR1; - break; - - case kPRINCE_Region2: - *region_base_addr = base->BASE_ADDR2; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - return status; -} - -/*! - * @brief Sets the PRINCE region IV. - * - * This function sets specified AES IV for the given region. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param iv 64-bit AES IV in little-endian byte order. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_SetRegionIV(PRINCE_Type *base, prince_region_t region, const uint8_t iv[8]) -{ - status_t status = kStatus_Fail; - volatile uint32_t *IVMsb_reg = NULL; - volatile uint32_t *IVLsb_reg = NULL; - - switch (region) - { - case kPRINCE_Region0: - IVLsb_reg = &base->IV_LSB0; - IVMsb_reg = &base->IV_MSB0; - break; - - case kPRINCE_Region1: - IVLsb_reg = &base->IV_LSB1; - IVMsb_reg = &base->IV_MSB1; - break; - - case kPRINCE_Region2: - IVLsb_reg = &base->IV_LSB2; - IVMsb_reg = &base->IV_MSB2; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - if (status != kStatus_InvalidArgument) - { - *IVLsb_reg = ((uint32_t *)(uintptr_t)iv)[0]; - *IVMsb_reg = ((uint32_t *)(uintptr_t)iv)[1]; - status = kStatus_Success; - } - - return status; -} - -/*! - * @brief Sets the PRINCE region base address. - * - * This function configures PRINCE region base address. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param region_base_addr Base Address for region. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_SetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t region_base_addr) -{ - status_t status = kStatus_Success; - - /* Check input parameters. */ -#if (defined(FSL_PRINCE_DRIVER_LPC55S0x)) || (defined(FSL_PRINCE_DRIVER_LPC55S1x)) || \ - (defined(FSL_PRINCE_DRIVER_LPC55S2x)) || (defined(FSL_PRINCE_DRIVER_LPC55S3x)) - if (region_base_addr > 0U) - { - return kStatus_InvalidArgument; - } -#endif -#if (defined(FSL_PRINCE_DRIVER_LPC55S6x)) - if (region_base_addr > 0x80000U) - { - return kStatus_InvalidArgument; - } -#endif - - switch (region) - { - case kPRINCE_Region0: - base->BASE_ADDR0 = region_base_addr; - break; - - case kPRINCE_Region1: - base->BASE_ADDR1 = region_base_addr; - break; - - case kPRINCE_Region2: - base->BASE_ADDR2 = region_base_addr; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - return status; -} - -/*! - * @brief Sets the PRINCE Sub-Region Enable register. - * - * This function configures PRINCE SR_ENABLE register. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param sr_enable Sub-Region Enable register value. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_SetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t sr_enable) -{ - status_t status = kStatus_Success; - - switch (region) - { - case kPRINCE_Region0: - base->SR_ENABLE0 = sr_enable; - break; - - case kPRINCE_Region1: - base->SR_ENABLE1 = sr_enable; - break; - - case kPRINCE_Region2: - base->SR_ENABLE2 = sr_enable; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - return status; -} - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Erases the flash sectors encompassed by parameters passed into function. - * - * This function erases the appropriate number of flash sectors based on the - * desired start address and length. It deals with the flash erase function - * complenentary to the standard erase API of the IAP1 driver. This implementation - * additionally checks if the whole encrypted PRINCE subregions are erased at once - * to avoid secrets revealing. The checker implementation is limited to one contiguous - * PRINCE-controlled memory area. - * - * @param config The pointer to the flash driver context structure. - * @param start The start address of the desired flash memory to be erased. - * The start address needs to be prince-sburegion-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words) - * to be erased. Must be prince-sburegion-size-aligned. - * @param key The value used to validate all flash erase APIs. - * - * @return #kStatus_FLASH_Success API was executed successfully. - * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @return #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. - * @return #kStatus_FLASH_AddressError The address is out of range. - * @return #kStatus_FLASH_EraseKeyError The API erase key is invalid. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @return #kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce Encrypted flash subregions are not erased at once. - */ -status_t PRINCE_FlashEraseWithChecker(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) -{ - /* Check input parameters. */ - if (NULL == config) - { - return kStatus_Fail; - } - /* Check that the whole encrypted region is erased at once. */ - if (kSECURE_TRUE != PRINCE_CheckerAlgorithm(start, lengthInBytes, kPRINCE_Flag_EraseCheck, config)) - { - return (int32_t)kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce; - } - return FLASH_Erase(config, start, lengthInBytes, key); -} - -/*! - * @brief Programs flash with data at locations passed in through parameters. - * - * This function programs the flash memory with the desired data for a given - * flash area as determined by the start address and the length. It deals with the - * flash program function complenentary to the standard program API of the IAP1 driver. - * This implementation additionally checks if the whole PRINCE subregions are - * programmed at once to avoid secrets revealing. The checker implementation is limited - * to one contiguous PRINCE-controlled memory area. - * - * @param config The pointer to the flash driver context structure. - * @param start The start address of the desired flash memory to be programmed. Must be - * prince-sburegion-aligned. - * @param src A pointer to the source buffer of data that is to be programmed - * into the flash. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be programmed. Must be prince-sburegion-size-aligned. - * - * @return #kStatus_FLASH_Success API was executed successfully. - * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @return #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @return #kStatus_FLASH_AddressError Address is out of range. - * @return #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @return #kStatus_FLASH_SizeError Encrypted flash subregions are not programmed at once. - */ -status_t PRINCE_FlashProgramWithChecker(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) -{ - /* Check input parameters. */ - if (NULL == config) - { - return kStatus_Fail; - } - /* Check that the whole encrypted subregions will be writen at once. */ - if (kSECURE_TRUE != PRINCE_CheckerAlgorithm(start, lengthInBytes, kPRINCE_Flag_WriteCheck, config)) - { - return (int32_t)kStatus_FLASH_SizeError; - } - return FLASH_Program(config, start, src, lengthInBytes); -} -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if defined(FSL_PRINCE_DRIVER_LPC55S3x) -static status_t PRINCE_CSS_generate_random(uint8_t *output, size_t outputByteLen); -static status_t PRINCE_CSS_check_key(uint8_t keyIdx, mcuxClCss_KeyProp_t *pKeyProp); -static status_t PRINCE_CSS_gen_iv_key(void); -static status_t PRINCE_CSS_enable(void); -static status_t PRINCE_CSS_calculate_iv(uint32_t *IvReg); - -/*! - * @brief Configures PRINCE setting. - * - * This function does the initial PRINCE configuration via ROM IAP API call. - * PRINCE_SR_x configuration for each region configuration is stored into FFR (CMPA). - * PRINCE IV erase counters (MCTR_INT_IV_CTRx) in CFPA are updated accordingly. - * - * Note: This function is expected to be called once in the device lifetime, - * typically during the initial device provisioning, since it is programming the CMPA pages in PFR flash. - * - * @param coreCtx The pointer to the ROM API driver context structure. - * @param config The pointer to the PRINCE driver configuration structure. - * - * @retval #kStatus_Success - * @retval #kStatus_CommandUnsupported - * @retval #kStatus_InvalidArgument - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed - * @retval #kStatusMemoryRangeInvalid - * @retval #kStatus_Fail - * @retval #kStatus_OutOfRange - * @retval #kStatus_SPI_BaudrateNotSupport - */ -status_t PRINCE_Configure(api_core_context_t *coreCtx, prince_prot_region_arg_t *config) -{ - /* Enable CSS and check keys */ - if (kStatus_Success != PRINCE_CSS_enable()) - { - return kStatus_Fail; - } - - return MEM_Config(coreCtx, (uint32_t *)config, kMemoryInternal); -} - -/*! - * @brief Configures PRINCE setting. - * - * This function is used to re-configure PRINCE IP based on configuration stored in FFR. - * This function also needs to be called after wake up from power-down mode to regenerate IV - * encryption key in CSS key store whose presence is necessary for correct PRINCE operation - * during erase and write operations to encrypted regions of internal flash memory - * (dependency for correct operation of MEM_Erase() and MEM_Write() after wake up from power-down mode). - * - * @param coreCtx The pointer to the ROM API driver context structure. - * - * @retval #kStatus_Success - * @retval #kStatus_Fail - */ -status_t PRINCE_Reconfigure(api_core_context_t *coreCtx) -{ - status_t status = kStatus_Fail; - uint64_t princeMask; - uint32_t IvReg[4] = {0}; - uint32_t ivEraseCounter[3]; - uint32_t srEnable[3]; - uint32_t uuid[4]; - flash_config_t flash_config; - uint32_t lockWord; - uint8_t lock[3]; - - /* Enable CSS and check keys */ - status = PRINCE_CSS_enable(); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - /* Set PRINCE mask value. */ - status = PRINCE_CSS_generate_random((uint8_t *)&princeMask, sizeof(princeMask)); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - PRINCE_SetMask(PRINCE, princeMask); - - /* Clean up Flash driver structure and Init*/ - memset(&flash_config, 0, sizeof(flash_config_t)); - if (FLASH_Init(&flash_config) != kStatus_Success) - { - return kStatus_Fail; - } - - /* FFR Init */ - if (FFR_Init(&flash_config) != kStatus_Success) - { - return kStatus_Fail; - } - - /* Get UUID from FFR */ - status = FFR_GetUUID(&flash_config, (uint8_t *)uuid); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - /* Check version of CFPA scratch first */ - uint32_t cfpaScratchVer = 0u; - memcpy(&cfpaScratchVer, (void *)(CFPA_SCRATCH_VER), sizeof(uint32_t)); - - /* Get CFPA version using FFR ROM API */ - uint32_t cfpaVer = 0u; - if (kStatus_Success != - FFR_GetCustomerInfieldData(&flash_config, (uint8_t *)&cfpaVer, CFPA_VER_OFFSET, sizeof(uint32_t))) - { - status = kStatus_Fail; - return status; - } - - /* Compare the version of CFPA scratch and version of CFPA returned by ROM API */ - if (cfpaScratchVer > cfpaVer) - { - /* Get PRINCE_IV_CTRs from CFPA scratch */ - memcpy(&ivEraseCounter, (void *)CFPA_SCRATCH_IV, sizeof(uint32_t) * PRINCE_REGION_COUNT); - } - else - { - /* Get PRINCE_IV_CTRs IVs from CFPA ping/pong page */ - status = FFR_GetCustomerInfieldData(&flash_config, (uint8_t *)ivEraseCounter, CFPA_PRINCE_IV_OFFSET, - sizeof(uint32_t) * PRINCE_REGION_COUNT); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - } - - /* Get PRINCE sub-region enable word from FFR */ - status = FFR_GetCustomerData(&flash_config, (uint8_t *)srEnable, CMPA_PRINCE_SR_OFFSET, - sizeof(uint32_t) * PRINCE_REGION_COUNT); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - /* Get PRINCE lock setting from FFR */ - status = FFR_GetCustomerData(&flash_config, (uint8_t *)&lockWord, CMPA_PRINCE_LOCK_OFFSET, sizeof(uint32_t)); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - lock[0] = (lockWord & PRINCE_BASE_ADDR_LOCK_REG0_MASK) >> PRINCE_BASE_ADDR_LOCK_REG0_SHIFT; - lock[1] = (lockWord & PRINCE_BASE_ADDR_LOCK_REG1_MASK) >> PRINCE_BASE_ADDR_LOCK_REG1_SHIFT; - lock[2] = (lockWord & PRINCE_BASE_ADDR_LOCK_REG2_MASK) >> PRINCE_BASE_ADDR_LOCK_REG2_SHIFT; - - /* Iterate for all internal PRINCE regions */ - for (prince_region_t region = kPRINCE_Region0; region <= kPRINCE_Region2; region++) - { - /* Set region base address. Should be always 0x0 on LPC55S36 */ - status = PRINCE_SetRegionBaseAddress(PRINCE, (prince_region_t)region, 0x0u); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - status = PRINCE_SetRegionSREnable(PRINCE, region, srEnable[region]); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - /* Prepare ivSeed for current region */ - IvReg[0] = uuid[0]; - IvReg[1] = uuid[1]; - IvReg[2] = uuid[2] ^ region; - IvReg[3] = ivEraseCounter[region]; - - /* Calculate IV as IvReg = AES_ECB_ENC(DUK_derived_key, {ctx_erase_counter, ctx_id}) */ - status = PRINCE_CSS_calculate_iv(IvReg); - if (status != kStatus_Success) - { - return kStatus_Fail; - } - - /* Load IV into PRINCE registers */ - status = PRINCE_SetRegionIV(PRINCE, (prince_region_t)region, (uint8_t *)IvReg); - if (status != kStatus_Success) - { - return kStatus_Fail; - } - - /* Lock region if required */ - if ((lock[region] == 0x1u) || (lock[region] == 0x2u) || (lock[region] == 0x3u)) - { - PRINCE_SetLock(PRINCE, (kPRINCE_Region0Lock << region)); - } - } - - /* Break the main loop in case that error occured during PRINCE configuration */ - if (status != kStatus_Success) - { - return kStatus_Fail; - } - - /* When ENC_ENABLE is set, reading from PRINCE-encrypted regions is disabled. */ - /* For LPC55S36, the ENC_ENABLE is self-cleared after programming memory. */ - PRINCE_EncryptDisable(PRINCE); - return status; -} - -static status_t PRINCE_CSS_generate_random(uint8_t *output, size_t outputByteLen) -{ - status_t status = kStatus_Fail; - - // PRNG needs to be initialized; this can be done by calling mcuxClCss_KeyDelete_Async - // (delete any key slot, can be empty) - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_KeyDelete_Async(18)); - // mcuxClCss_KeyDelete_Async is a flow-protected function: Check the protection token and the return value - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_KeyDelete_Async) != token) || (MCUXCLCSS_STATUS_OK_WAIT != result)) - return kStatus_Fail; // Expect that no error occurred, meaning that the mcuxClCss_KeyDelete_Async operation was - // started. - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - // Wait for operation to finish - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_WaitForOperation(MCUXCLCSS_ERROR_FLAGS_CLEAR)); - // mcuxClCss_WaitForOperation is a flow-protected function: Check the protection token and the return value - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_WaitForOperation) != token) || (MCUXCLCSS_STATUS_OK != result)) - return kStatus_Fail; // Expect that no error occurred, meaning that the mcuxClCss_WaitForOperation operation was - // started. - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_Prng_GetRandom(output, outputByteLen)); - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_Prng_GetRandom) != token) || (MCUXCLCSS_STATUS_OK != result)) - return kStatus_Fail; - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - status = kStatus_Success; - return status; -} - -static status_t PRINCE_CSS_check_key(uint8_t keyIdx, mcuxClCss_KeyProp_t *pKeyProp) -{ - /* Check if CSS required keys are available in CSS keystore */ - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, - mcuxClCss_GetKeyProperties(keyIdx, pKeyProp)); // Get key propertis from the CSS. - // mcuxClCss_GetKeyProperties is a flow-protected function: Check the protection token and the return value - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_GetKeyProperties) != token) || (MCUXCLCSS_STATUS_OK != result)) - return kStatus_Fail; - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - return kStatus_Success; -} - -static status_t PRINCE_CSS_gen_iv_key(void) -{ - /* The NXP_DIE_MEM_IV_ENC_SK is not loaded and needs to be regenerated (power-down wakeup) */ - /* Set KDF mask and key properties for NXP_DIE_MEM_IV_ENC_SK */ - SYSCON->CSS_KDF_MASK = SYSCON_CSS_KDF_MASK; - static const uint32_t ddata2[3] = {0x62032504, 0x72f04280, 0x87a2bbae}; - mcuxClCss_KeyProp_t keyProp; - /* Set key properties in structure */ - keyProp.word.value = CSS_CSS_KS2_ks2_uaes_MASK | CSS_CSS_KS2_ks2_fgp_MASK | CSS_CSS_KS2_ks2_kact_MASK; - status_t status = kStatus_Fail; - - /* Generate the key using CKDF */ - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN( - result, token, - mcuxClCss_Ckdf_Sp800108_Async((mcuxClCss_KeyIndex_t)0, (mcuxClCss_KeyIndex_t)NXP_DIE_MEM_IV_ENC_SK, keyProp, - (uint8_t const *)ddata2)); - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_Ckdf_Sp800108_Async) != token) && (MCUXCLCSS_STATUS_OK != result)) - { - return kStatus_Fail; - } - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - /* Wait for CKDF to finish */ - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_WaitForOperation(MCUXCLCSS_ERROR_FLAGS_CLEAR)); - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_WaitForOperation) == token) && (MCUXCLCSS_STATUS_OK == result)) - { - status = kStatus_Success; - } - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - return status; -} - -static status_t PRINCE_CSS_enable(void) -{ - mcuxClCss_KeyProp_t key_properties; - status_t status = kStatus_Fail; - - /* Enable CSS and related clocks */ - status = CSS_PowerDownWakeupInit(CSS); - if (status != kStatus_Success) - { - return kStatus_Fail; - } - - /* Check if MEM_ENC_SK key is available in CSS keystore */ - status = PRINCE_CSS_check_key(NXP_DIE_MEM_ENC_SK, &key_properties); - if (status != kStatus_Success || key_properties.bits.kactv != 1u) - { - return kStatus_Fail; - } - - /* Check if MEM_IV_ENC_SK key is available in CSS keystore */ - status = PRINCE_CSS_check_key(NXP_DIE_MEM_IV_ENC_SK, &key_properties); - if (status != kStatus_Success || key_properties.bits.kactv != 1u) - { - return PRINCE_CSS_gen_iv_key(); - } - - return kStatus_Success; -} - -static status_t PRINCE_CSS_calculate_iv(uint32_t *IvReg) -{ - mcuxClCss_CipherOption_t cipherOptions = {0}; - status_t status = kStatus_Fail; - - /* Configure CSS for AES ECB-128, using NXP_DIE_MEM_IV_ENC_SK key */ - cipherOptions.bits.cphmde = MCUXCLCSS_CIPHERPARAM_ALGORITHM_AES_ECB; - cipherOptions.bits.dcrpt = MCUXCLCSS_CIPHER_ENCRYPT; - cipherOptions.bits.extkey = MCUXCLCSS_CIPHER_INTERNAL_KEY; - - do - { - /* Calculate IV as IvReg = AES_ECB_ENC(NXP_DIE_MEM_IV_ENC_SK, ivSeed[127:0]) */ - /* ivSeed[127:0] = {UUID[96:0] ^ regionNumber[1:0], ivEraseCounter[31:0]} */ - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN( - result, token, - mcuxClCss_Cipher_Async(cipherOptions, (mcuxClCss_KeyIndex_t)NXP_DIE_MEM_IV_ENC_SK, NULL, - MCUXCLCSS_CIPHER_KEY_SIZE_AES_128, (uint8_t *)IvReg, MCUXCLCSS_CIPHER_BLOCK_SIZE_AES, - NULL, (uint8_t *)IvReg)); - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_Cipher_Async) != token) || (MCUXCLCSS_STATUS_OK_WAIT != result)) - break; - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN( - result, token, - mcuxClCss_WaitForOperation( - MCUXCLCSS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClCss_Enable_Async operation to complete. - // mcuxClCss_WaitForOperation is a flow-protected function: Check the protection token and the return value - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_WaitForOperation) == token) && (MCUXCLCSS_STATUS_OK == result)) - { - status = kStatus_Success; - } - MCUX_CSSL_FP_FUNCTION_CALL_END(); - } while (0); - - return status; -} -#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_prince.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_prince.h deleted file mode 100644 index 1d702ae499b..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_prince.h +++ /dev/null @@ -1,522 +0,0 @@ -/* - * Copyright 2018 - 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_PRINCE_H_ -#define _FSL_PRINCE_H_ - -#include "fsl_common.h" - -#include FFR_INCLUDE - -/*! - * @addtogroup prince - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief PRINCE driver version 2.5.0. - * - * Current version: 2.5.0 - * - * Change log: - * - Version 2.0.0 - * - Initial version. - * - Version 2.1.0 - * - Update for the A1 rev. of LPC55Sxx serie. - * - Version 2.2.0 - * - Add runtime checking of the A0 and A1 rev. of LPC55Sxx serie to support - * both silicone revisions. - * - Version 2.3.0 - * - Add support for LPC55S1x and LPC55S2x series - * - Version 2.3.0 - * - Fix MISRA-2012 issues. - * - Version 2.3.1 - * - Add support for LPC55S0x series - * - Version 2.3.2 - * - Fix documentation of enumeration. Extend PRINCE example. - * - Version 2.4.0 - * - Add support for LPC55S3x series - * - Version 2.5.0 - * - Add PRINCE_Config() and PRINCE_Reconfig() features. - */ -#define FSL_PRINCE_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) -/*@}*/ - -#if (defined(LPC55S04_SERIES) || defined(LPC55S06_SERIES)) -/* LPC55S0x series*/ -#define FSL_PRINCE_DRIVER_LPC55S0x -#include "fsl_puf.h" - -#elif (defined(LPC55S14_SERIES) || defined(LPC55S16_SERIES)) -/* LPC55S1x series*/ -#define FSL_PRINCE_DRIVER_LPC55S1x -#include "fsl_puf.h" - -#elif (defined(LPC55S26_SERIES) || defined(LPC55S28_SERIES)) -/* LPC55S2x series*/ -#define FSL_PRINCE_DRIVER_LPC55S2x -#include "fsl_puf.h" - -#elif (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || \ - defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES)) -/* LPC55S6x series*/ -#define FSL_PRINCE_DRIVER_LPC55S6x -#include "fsl_puf.h" - -#elif (defined(LPC55S36_SERIES)) -/* LPC55S3x series*/ -#define FSL_PRINCE_DRIVER_LPC55S3x -#define PRINCE PRINCE0 -#include "fsl_mem_interface.h" -#include "fsl_css.h" // Power Down Wake-up Init -#include // Interface to the entire nxpClCss component -#include // Code flow protection -#else -#error "No valid CPU defined!" -#endif - -#define FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB (8U) -#define FSL_PRINCE_DRIVER_MAX_FLASH_ADDR \ - ((uint32_t)FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES - (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 2U * 1024U)) - -#if !defined(ALIGN_DOWN) -#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) -#endif - -/*! @brief Secure status enumeration. */ -typedef enum _skboot_status -{ - kStatus_SKBOOT_Success = 0x5ac3c35au, /*!< PRINCE Success */ - kStatus_SKBOOT_Fail = 0xc35ac35au, /*!< PRINCE Fail */ - kStatus_SKBOOT_InvalidArgument = 0xc35a5ac3u, /*!< PRINCE Invalid argument */ - kStatus_SKBOOT_KeyStoreMarkerInvalid = 0xc3c35a5au, /*!< PRINCE Invalid marker */ -} skboot_status_t; - -/*! @brief Secure boolean enumeration. */ -typedef enum _secure_bool -{ - kSECURE_TRUE = 0xc33cc33cU, /*!< PRINCE true */ - kSECURE_FALSE = 0x5aa55aa5U, /*!< PRINCE false */ -} secure_bool_t; - -/*! @brief Prince region. */ -typedef enum _prince_region -{ - kPRINCE_Region0 = 0U, /*!< PRINCE region 0 */ - kPRINCE_Region1 = 1U, /*!< PRINCE region 1 */ - kPRINCE_Region2 = 2U, /*!< PRINCE region 2 */ -} prince_region_t; - -/*! @brief Prince lock. */ -typedef enum _prince_lock -{ - kPRINCE_Region0Lock = 1U, /*!< PRINCE region 0 lock */ - kPRINCE_Region1Lock = 2U, /*!< PRINCE region 1 lock */ - kPRINCE_Region2Lock = 4U, /*!< PRINCE region 2 lock */ - kPRINCE_MaskLock = 256U, /*!< PRINCE mask register lock */ -} prince_lock_t; - -/*! @brief Prince flag. */ -typedef enum _prince_flags -{ - kPRINCE_Flag_None = 0U, /*!< PRINCE Flag None */ - kPRINCE_Flag_EraseCheck = 1U, /*!< PRINCE Flag Erase check */ - kPRINCE_Flag_WriteCheck = 2U, /*!< PRINCE Flag Write check */ -} prince_flags_t; - -#if defined(FSL_PRINCE_DRIVER_LPC55S3x) -typedef struct -{ - uint32_t target_prince_region : 2; // 0/1/2 - uint32_t reserved : 22; - uint32_t tag : 8; // Fixed to 0x50 ('P') -} prince_prot_region_option_t; -typedef struct -{ - prince_prot_region_option_t option; - uint32_t start; - uint32_t length; -} prince_prot_region_arg_t; - -/*! @brief Prince fixed tag in prince_prot_region_option_t structure */ -#define PRINCE_TAG 0x50u -#define PRINCE_TAG_SHIFT 24u -/*! @brief Prince region count */ -#define PRINCE_REGION_COUNT 3u -/*! @brief Define for CSS key store indexes */ -#define NXP_DIE_MEM_ENC_SK 2u -#define NXP_DIE_MEM_IV_ENC_SK 4u -/*! @brief KDF mask and key properties for NXP_DIE_MEM_IV_ENC_SK (see SYSCON documentation)*/ -#define SYSCON_CSS_KDF_MASK 0x07000FCF -/*! @brief CFPA version and IV indexes (see Protected Flash Region table) */ -#define CFPA_VER_OFFSET 0x04 -#define CFPA_PRINCE_IV_OFFSET 0x14u -/*! @brief CMPA SR and lock indexes (see Protected Flash Region table) */ -#define CMPA_PRINCE_SR_OFFSET 0x24u -#define CMPA_PRINCE_LOCK_OFFSET 0x20u -/*! @brief CFPA scrach version and IV addresses (see Protected Flash Region table) */ -#define CFPA_SCRATCH_VER 0x3dc04 -#define CFPA_SCRATCH_IV 0x3dc14 -/*! @brief CMPA lock bit-field defines (see Protected Flash Region table) */ -#define PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (16u) -#define PRINCE_BASE_ADDR_LOCK_REG0_MASK (0x3u << PRINCE_BASE_ADDR_LOCK_REG0_SHIFT) -#define PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (18u) -#define PRINCE_BASE_ADDR_LOCK_REG1_MASK (0x3u << PRINCE_BASE_ADDR_LOCK_REG1_SHIFT) -#define PRINCE_BASE_ADDR_LOCK_REG2_SHIFT (20u) -#define PRINCE_BASE_ADDR_LOCK_REG2_MASK (0x3u << PRINCE_BASE_ADDR_LOCK_REG2_SHIFT) - -#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Enable data encryption. - * - * This function enables PRINCE on-the-fly data encryption. - * - * @param base PRINCE peripheral address. - */ -static inline void PRINCE_EncryptEnable(PRINCE_Type *base) -{ - base->ENC_ENABLE = 1u; -} - -/*! - * @brief Disable data encryption. - * - * This function disables PRINCE on-the-fly data encryption. - * - * @param base PRINCE peripheral address. - */ -static inline void PRINCE_EncryptDisable(PRINCE_Type *base) -{ - base->ENC_ENABLE = 0u; -} - -/*! - * @brief Is Enable data encryption. - * - * This function test if PRINCE on-the-fly data encryption is enabled. - * - * @param base PRINCE peripheral address. - * @return true if enabled, false if not - */ -static inline bool PRINCE_IsEncryptEnable(PRINCE_Type *base) -{ - return (base->ENC_ENABLE == 1u) ? true : false; -} - -/*! - * @brief Sets PRINCE data mask. - * - * This function sets the PRINCE mask that is used to mask decrypted data. - * - * @param base PRINCE peripheral address. - * @param mask 64-bit data mask value. - */ -static inline void PRINCE_SetMask(PRINCE_Type *base, uint64_t mask) -{ - base->MASK_LSB = (uint32_t)(mask & 0xffffffffu); - base->MASK_MSB = (uint32_t)(mask >> 32u); -} - -/*! - * @brief Locks access for specified region registers or data mask register. - * - * This function sets lock on specified region registers or mask register. - * - * @param base PRINCE peripheral address. - * @param lock registers to lock. This is a logical OR of members of the - * enumeration ::prince_lock_t - */ -static inline void PRINCE_SetLock(PRINCE_Type *base, uint32_t lock) -{ - base->LOCK = lock & 0x1ffu; -} - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Generate new IV code. - * - * This function generates new IV code and stores it into the persistent memory. - * Ensure about 800 bytes free space on the stack when calling this routine with the store parameter set to true! - * - * @param region PRINCE region index. - * @param iv_code IV code pointer used for storing the newly generated 52 bytes long IV code. - * @param store flag to allow storing the newly generated IV code into the persistent memory (FFR). - * @param flash_context pointer to the flash driver context structure. - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise, kStatus_Fail is also returned if the key code for the particular - * PRINCE region is not present in the keystore (though new IV code has been provided) - */ -status_t PRINCE_GenNewIV(prince_region_t region, uint8_t *iv_code, bool store, flash_config_t *flash_context); -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Load IV code. - * - * This function enables IV code loading into the PRINCE bus encryption engine. - * - * @param region PRINCE region index. - * @param iv_code IV code pointer used for passing the IV code. - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise - */ -status_t PRINCE_LoadIV(prince_region_t region, uint8_t *iv_code); -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Allow encryption/decryption for specified address range. - * - * This function sets the encryption/decryption for specified address range. - * The SR mask value for the selected Prince region is calculated from provided - * start_address and length parameters. This calculated value is OR'ed with the - * actual SR mask value and stored into the PRINCE SR_ENABLE register and also - * into the persistent memory (FFR) to be used after the device reset. It is - * possible to define several nonadjacent encrypted areas within one Prince - * region when calling this function repeatedly. If the length parameter is set - * to 0, the SR mask value is set to 0 and thus the encryption/decryption for - * the whole selected Prince region is disabled. - * Ensure about 800 bytes free space on the stack when calling this routine! - * - * @param region PRINCE region index. - * @param start_address start address of the area to be encrypted/decrypted. - * @param length length of the area to be encrypted/decrypted. - * @param flash_context pointer to the flash driver context structure. - * @param regenerate_iv flag to allow IV code regenerating, storing into - * the persistent memory (FFR) and loading into the PRINCE engine - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise - */ -status_t PRINCE_SetEncryptForAddressRange( - prince_region_t region, uint32_t start_address, uint32_t length, flash_config_t *flash_context, bool regenerate_iv); -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -/*! - * @brief Gets the PRINCE Sub-Region Enable register. - * - * This function gets PRINCE SR_ENABLE register. - * - * @param base PRINCE peripheral address. - * @param region PRINCE region index. - * @param sr_enable Sub-Region Enable register pointer. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_GetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t *sr_enable); - -/*! - * @brief Gets the PRINCE region base address register. - * - * This function gets PRINCE BASE_ADDR register. - * - * @param base PRINCE peripheral address. - * @param region PRINCE region index. - * @param region_base_addr Region base address pointer. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_GetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t *region_base_addr); - -/*! - * @brief Sets the PRINCE region IV. - * - * This function sets specified AES IV for the given region. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param iv 64-bit AES IV in little-endian byte order. - */ -status_t PRINCE_SetRegionIV(PRINCE_Type *base, prince_region_t region, const uint8_t iv[8]); - -/*! - * @brief Sets the PRINCE region base address. - * - * This function configures PRINCE region base address. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param region_base_addr Base Address for region. - */ -status_t PRINCE_SetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t region_base_addr); - -/*! - * @brief Sets the PRINCE Sub-Region Enable register. - * - * This function configures PRINCE SR_ENABLE register. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param sr_enable Sub-Region Enable register value. - */ -status_t PRINCE_SetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t sr_enable); - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Erases the flash sectors encompassed by parameters passed into function. - * - * This function erases the appropriate number of flash sectors based on the - * desired start address and length. It deals with the flash erase function - * complenentary to the standard erase API of the IAP1 driver. This implementation - * additionally checks if the whole encrypted PRINCE subregions are erased at once - * to avoid secrets revealing. The checker implementation is limited to one contiguous - * PRINCE-controlled memory area. - * - * @param config The pointer to the flash driver context structure. - * @param start The start address of the desired flash memory to be erased. - * The start address needs to be prince-sburegion-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words) - * to be erased. Must be prince-sburegion-size-aligned. - * @param key The value used to validate all flash erase APIs. - * - * @return #kStatus_FLASH_Success API was executed successfully. - * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @return #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. - * @return #kStatus_FLASH_AddressError The address is out of range. - * @return #kStatus_FLASH_EraseKeyError The API erase key is invalid. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @return #kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce Encrypted flash subregions are not erased at once. - */ -status_t PRINCE_FlashEraseWithChecker(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Programs flash with data at locations passed in through parameters. - * - * This function programs the flash memory with the desired data for a given - * flash area as determined by the start address and the length. It deals with the - * flash program function complenentary to the standard program API of the IAP1 driver. - * This implementation additionally checks if the whole PRINCE subregions are - * programmed at once to avoid secrets revealing. The checker implementation is limited - * to one contiguous PRINCE-controlled memory area. - * - * @param config The pointer to the flash driver context structure. - * @param start The start address of the desired flash memory to be programmed. Must be - * prince-sburegion-aligned. - * @param src A pointer to the source buffer of data that is to be programmed - * into the flash. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be programmed. Must be prince-sburegion-size-aligned. - * - * @return #kStatus_FLASH_Success API was executed successfully. - * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @return #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @return #kStatus_FLASH_AddressError Address is out of range. - * @return #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @return #kStatus_FLASH_SizeError Encrypted flash subregions are not programmed at once. - */ -status_t PRINCE_FlashProgramWithChecker(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Configures PRINCE setting. - * - * This function does the initial PRINCE configuration via ROM IAP API call. - * PRINCE_SR_x configuration for each region configuration is stored into FFR (CMPA). - * PRINCE IV erase counters (MCTR_INT_IV_CTRx) in CFPA are updated accordingly. - * - * Note: This function is expected to be called once in the device lifetime, - * typically during the initial device provisioning, since it is programming the CMPA pages in PFR flash. - * - * @param coreCtx The pointer to the ROM API driver context structure. - * @param config The pointer to the PRINCE driver configuration structure. - * - * @retval #kStatus_Success - * @retval #kStatus_CommandUnsupported - * @retval #kStatus_InvalidArgument - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed - * @retval #kStatusMemoryRangeInvalid - * @retval #kStatus_Fail - * @retval #kStatus_OutOfRange - * @retval #kStatus_SPI_BaudrateNotSupport - */ -status_t PRINCE_Configure(api_core_context_t *coreCtx, prince_prot_region_arg_t *config); -#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Reconfigures PRINCE setting. - * - * This function is used to re-configure PRINCE IP based on configuration stored in FFR. - * This function also needs to be called after wake up from power-down mode to regenerate IV - * encryption key in CSS key store whose presence is necessary for correct PRINCE operation - * during erase and write operations to encrypted regions of internal flash memory - * (dependency for correct operation of MEM_Erase() and MEM_Write() after wake up from power-down mode). - * - * @param coreCtx The pointer to the ROM API driver context structure. - * - * @retval #kStatus_Success - * @retval #kStatus_CommandUnsupported - * @retval #kStatus_InvalidArgument - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed - * @retval #kStatusMemoryRangeInvalid - * @retval #kStatus_Fail - * @retval #kStatus_OutOfRange - * @retval #kStatus_SPI_BaudrateNotSupport - */ -status_t PRINCE_Reconfigure(api_core_context_t *coreCtx); -#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if (defined(FSL_PRINCE_DRIVER_LPC55S0x)) || defined(FSL_PRINCE_DRIVER_LPC55S1x) || defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Gets the PRINCE Error status register. - * - * @param base PRINCE peripheral address. - * - * @return PRINCE Error status register - */ -static inline uint32_t PRINCE_GetErrorStatus(PRINCE_Type *base) -{ - return base->ERR; -} - -/*! - * @brief Clears the PRINCE Error status register. - * - * @param base PRINCE peripheral address. - */ -static inline void PRINCE_ClearErrorStatus(PRINCE_Type *base) -{ - base->ERR = 0U; -} -#endif /* defined(FSL_PRINCE_DRIVER_LPC55S0x) || defined(FSL_PRINCE_DRIVER_LPC55S1x) || \ - defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_PRINCE_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_puf.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_puf.c deleted file mode 100644 index d82299ed243..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_puf.c +++ /dev/null @@ -1,949 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_puf.h" -#include "fsl_clock.h" -#include "fsl_common.h" - -#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) -#include "fsl_reset.h" -#endif /* FSL_FEATURE_PUF_HAS_NO_RESET */ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.puf" -#endif - -/* RT6xx POWER CONTROL bit masks */ -#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) -#define PUF_PWRCTRL_CKDIS_MASK (0x4U) -#define PUF_PWRCTRL_RAMINIT_MASK (0x8U) -#define PUF_PWRCTRL_RAMPSWLARGEMA_MASK (0x10U) -#define PUF_PWRCTRL_RAMPSWLARGEMP_MASK (0x20U) -#define PUF_PWRCTRL_RAMPSWSMALLMA_MASK (0x40U) -#define PUF_PWRCTRL_RAMPSWSMALLMP_MASK (0x80U) -#endif - -#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) -#define DEFAULT_CKGATING 0x0u -#define PUF_ENABLE_MASK 0xFFFFFFFEu -#define PUF_ENABLE_CTRL 0x1u - -#else -static void puf_wait_usec(volatile uint32_t usec, uint32_t coreClockFrequencyMHz) -{ - SDK_DelayAtLeastUs(usec, coreClockFrequencyMHz * 1000000U); - - /* Instead of calling SDK_DelayAtLeastUs() implement delay loop here */ - // while (usec > 0U) - // { - // usec--; - - // number of MHz is directly number of core clocks to wait 1 usec. - // the while loop below is actually 4 clocks so divide by 4 for ~1 usec - // volatile uint32_t ticksCount = coreClockFrequencyMHz / 4u + 1u; - // while (0U != ticksCount--) - // { - // } - // } -} -#endif /* defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) */ - -static status_t puf_waitForInit(PUF_Type *base) -{ - status_t status = kStatus_Fail; - - /* wait until status register reads non-zero. All zero is not valid. It should be BUSY or OK or ERROR */ - while (0U == base->STAT) - { - } - - /* wait if busy */ - while ((base->STAT & PUF_STAT_BUSY_MASK) != 0U) - { - } - - /* return status */ - if (0U != (base->STAT & (PUF_STAT_SUCCESS_MASK | PUF_STAT_ERROR_MASK))) - { - status = kStatus_Success; - } - - return status; -} - -static void puf_powerOn(PUF_Type *base, puf_config_t *conf) -{ -#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) - /* RT6xxs */ - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK); - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_RAMINIT_MASK); -#elif defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* LPCXpresso55s16 */ - conf->puf_sram_base->CFG |= PUF_ENABLE_CTRL; - while (0U == (PUF_SRAM_CTRL_STATUS_READY_MASK & conf->puf_sram_base->STATUS)) - { - } -#else /* !FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ - /* LPCXpresso55s69 & LPCXpresso54S018 */ - base->PWRCTRL = PUF_PWRCTRL_RAMON_MASK; - while (0U == (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL)) - { - } -#endif /* FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ -} -/*! - * brief Powercycle PUF - * - * This function make powercycle of PUF. - * - * param base PUF peripheral base address - * param conf PUF configuration structure - * return Status of the powercycle operation. - */ -status_t PUF_PowerCycle(PUF_Type *base, puf_config_t *conf) -{ -#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) - /* RT6xxs */ - uint32_t coreClockFrequencyMHz = conf->coreClockFrequencyHz / 1000000u; - - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* disable RAM CK */ - - /* enter ASPS mode */ - base->PWRCTRL = (PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* SLEEP = 1 */ - base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK); /* enable RAM CK */ - base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | PUF_PWRCTRL_RAMPSWLARGEMP_MASK | - PUF_PWRCTRL_RAMPSWSMALLMA_MASK | PUF_PWRCTRL_RAMPSWSMALLMP_MASK); /* SLEEP=1, PSW*=1 */ - - /* Wait enough time to discharge fully */ - puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); - - /* write PWRCTRL=0x38. wait time > 1 us */ - base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | - PUF_PWRCTRL_RAMPSWLARGEMP_MASK); /* SLEEP=1. PSWSMALL*=0. PSWLARGE*=1. */ - puf_wait_usec(1, coreClockFrequencyMHz); - - /* write PWRCTRL=0x8. wait time > 1 us */ - base->PWRCTRL = PUF_PWRCTRL_RAMINIT_MASK; /* SLEEP=1. PSWSMALL*=0. PSWLARGE*=0 */ - puf_wait_usec(1, coreClockFrequencyMHz); - - base->PWRCTRL = (PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_RAMINIT_MASK); - - /* Generate INITN low pulse */ - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK); - base->PWRCTRL = PUF_PWRCTRL_RAM_ON_MASK; -#elif defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* LPCXpresso55s16 */ - conf->puf_sram_base->CFG &= PUF_ENABLE_MASK; -#else - /* LPCXpresso55s69 & LPCXpresso54S018 */ - base->PWRCTRL = 0x0u; - while (0U != (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL)) - { - } - - /* Wait enough time to discharge fully */ - puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); -#endif - -#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) - /* Reset PUF and reenable power to PUF SRAM */ - RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); -#endif /* FSL_TEATURE_PUF_HAS_NO_RESET */ - puf_powerOn(base, conf); - - return kStatus_Success; -} - -/*! - * brief Sets the default configuration of PUF - * - * This function initialize PUF config structure to default values. - * - * param conf PUF configuration structure - */ -void PUF_GetDefaultConfig(puf_config_t *conf) -{ -#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* LPCXpresso55s16 */ - conf->puf_sram_base = PUF_SRAM_CTRL; - - /* Default configuration after reset */ - conf->CKGATING = DEFAULT_CKGATING; /* PUF SRAM Clock Gating */ -#endif /* FSL_FEATURE_PUF_HAS_SRAM_CTRL */ - - conf->dischargeTimeMsec = KEYSTORE_PUF_DISCHARGE_TIME_FIRST_TRY_MS; - conf->coreClockFrequencyHz = CLOCK_GetFreq(kCLOCK_CoreSysClk); - - return; -} - -/*! - * brief Initialize PUF - * - * This function enables power to PUF block and waits until the block initializes. - * - * param base PUF peripheral base address - * param conf PUF configuration structure - * return Status of the init operation - */ -status_t PUF_Init(PUF_Type *base, puf_config_t *conf) -{ - status_t status = kStatus_Fail; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Puf); -#endif -#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) - /* Reset PUF */ - RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); -#endif /* FSL_FEATURE_PUF_HAS_NO_RESET */ - -#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* Set configuration for SRAM */ - conf->puf_sram_base->CFG |= PUF_SRAM_CTRL_CFG_CKGATING(conf->CKGATING); - -#endif /* FSL_FEATURE_PUF_HAS_SRAM_CTRL */ - - /* Enable power to PUF SRAM */ - puf_powerOn(base, conf); - - /* Wait for peripheral to become ready */ - status = puf_waitForInit(base); - - /* In case of error or enroll or start not allowed, do power-cycle */ - /* First try with shorter discharge time, if then it also fails try with longer time */ - /* conf->dischargeTimeMsec = KEYSTORE_PUF_DISCHARGE_TIME_FIRST_TRY_MS; */ - if ((status != kStatus_Success) || (0U == (base->ALLOW & (PUF_ALLOW_ALLOWENROLL_MASK | PUF_ALLOW_ALLOWSTART_MASK)))) - { - (void)PUF_PowerCycle(base, conf); - status = puf_waitForInit(base); - } - - /* In case of error or enroll or start not allowed, do power-cycle with worst discharge timing */ - if ((status != kStatus_Success) || (0U == (base->ALLOW & (PUF_ALLOW_ALLOWENROLL_MASK | PUF_ALLOW_ALLOWSTART_MASK)))) - { - conf->dischargeTimeMsec = KEYSTORE_PUF_DISCHARGE_TIME_MAX_MS; - (void)PUF_PowerCycle(base, conf); - status = puf_waitForInit(base); - } - - return status; -} - -/*! - * brief Denitialize PUF - * - * This function disables power to PUF SRAM and peripheral clock. - * - * param base PUF peripheral base address - * param conf PUF configuration structure - */ -void PUF_Deinit(PUF_Type *base, puf_config_t *conf) -{ -#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) - /* RT6xxs */ - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* disable RAM CK */ - - /* enter ASPS mode */ - base->PWRCTRL = (PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* SLEEP = 1 */ - base->PWRCTRL = PUF_PWRCTRL_RAMINIT_MASK; /* enable RAM CK */ - base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | PUF_PWRCTRL_RAMPSWLARGEMP_MASK | - PUF_PWRCTRL_RAMPSWSMALLMA_MASK | PUF_PWRCTRL_RAMPSWSMALLMP_MASK); /* SLEEP=1, PSW*=1 */ - puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); -#elif defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* LPCXpresso55s16 */ - conf->puf_sram_base = PUF_SRAM_CTRL; - conf->puf_sram_base->CFG &= PUF_ENABLE_MASK; -#else /* !FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ - /* LPCXpresso55s69 & LPCXpresso54S018 */ - base->PWRCTRL = 0x00u; - puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); -#endif - -#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) - RESET_SetPeripheralReset(kPUF_RST_SHIFT_RSTn); -#endif /* FSL_FEATURE_PUF_HAS_NO_RESET */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Puf); -#endif -} - -/*! - * brief Enroll PUF - * - * This function derives a digital fingerprint, generates the corresponding Activation Code (AC) - * and returns it to be stored in an NVM or a file. This step needs to be - * performed only once for each device. This function may be permanently disallowed by a fuse. - * - * param base PUF peripheral base address - * param[out] activationCode Word aligned address of the resulting activation code. - * param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. - * return Status of enroll operation. - */ -status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize) -{ - status_t status = kStatus_Fail; - uint32_t *activationCodeAligned = NULL; - register uint32_t temp32 = 0; - - /* check that activation code buffer size is at least 1192 bytes */ - if (activationCodeSize < PUF_ACTIVATION_CODE_SIZE) - { - return kStatus_InvalidArgument; - } - - /* only work with aligned activationCode */ - if (0U != (0x3u & (uintptr_t)activationCode)) - { - return kStatus_InvalidArgument; - } - - activationCodeAligned = (uint32_t *)(uintptr_t)activationCode; - - /* check if ENROLL is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWENROLL_MASK)) - { - return kStatus_EnrollNotAllowed; - } - - /* begin */ - base->CTRL = PUF_CTRL_ENROLL_MASK; - - /* check status */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* read out AC */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) - { - temp32 = base->CODEOUTPUT; - if (activationCodeSize >= sizeof(uint32_t)) - { - *activationCodeAligned = temp32; - activationCodeAligned++; - activationCodeSize -= sizeof(uint32_t); - } - } - } - - if (((base->STAT & PUF_STAT_SUCCESS_MASK) != 0U) && (activationCodeSize == 0U)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Start PUF - * - * The Activation Code generated during the Enroll operation is used to - * reconstruct the digital fingerprint. This needs to be done after every power-up - * and reset. - * - * param base PUF peripheral base address - * param activationCode Word aligned address of the input activation code. - * param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. - * return Status of start operation. - */ -status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize) -{ - status_t status = kStatus_Fail; - const uint32_t *activationCodeAligned = NULL; - register uint32_t temp32 = 0; - - /* check that activation code size is at least 1192 bytes */ - if (activationCodeSize < 1192U) - { - return kStatus_InvalidArgument; - } - - /* only work with aligned activationCode */ - if (0U != (0x3u & (uintptr_t)activationCode)) - { - return kStatus_InvalidArgument; - } - - activationCodeAligned = (const uint32_t *)(uintptr_t)activationCode; - - /* check if START is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSTART_MASK)) - { - return kStatus_StartNotAllowed; - } - - /* begin */ - base->CTRL = PUF_CTRL_START_MASK; - - /* check status */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy send AC */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_CODEINREQ_MASK & base->STAT)) - { - if (activationCodeSize >= sizeof(uint32_t)) - { - temp32 = *activationCodeAligned; - activationCodeAligned++; - activationCodeSize -= sizeof(uint32_t); - } - base->CODEINPUT = temp32; - } - } - - /* get status */ - if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Set intrinsic key - * - * The digital fingerprint generated during the Enroll/Start - * operations is used to generate a Key Code (KC) that defines a unique intrinsic - * key. This KC is returned to be stored in an NVM or a file. This operation - * needs to be done only once for each intrinsic key. - * Each time a Set Intrinsic Key operation is executed a new unique key is - * generated. - * - * param base PUF peripheral base address - * param keyIndex PUF key index register - * param keySize Size of the intrinsic key to generate in bytes. - * param[out] keyCode Word aligned address of the resulting key code. - * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * return Status of set intrinsic key operation. - */ -status_t PUF_SetIntrinsicKey( - PUF_Type *base, puf_key_index_register_t keyIndex, size_t keySize, uint8_t *keyCode, size_t keyCodeSize) -{ - status_t status = kStatus_Fail; - uint32_t *keyCodeAligned = NULL; - register uint32_t temp32 = 0; - - /* check if SET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSETKEY_MASK)) - { - return kStatus_Fail; - } - - /* only work with aligned keyCode */ - if (0U != (0x3u & (uintptr_t)keyCode)) - { - return kStatus_InvalidArgument; - } - - /* Check that keySize is in the correct range and that it is multiple of 8 */ - if ((keySize < (uint32_t)kPUF_KeySizeMin) || (keySize > (uint32_t)kPUF_KeySizeMax) || (0U != (keySize & 0x7U))) - { - return kStatus_InvalidArgument; - } - - /* check that keyCodeSize is correct for given keySize */ - if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize)) - { - return kStatus_InvalidArgument; - } - - if ((uint32_t)keyIndex > (uint32_t)kPUF_KeyIndexMax) - { - return kStatus_InvalidArgument; - } - - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - - /* program the key size and index */ - base->KEYSIZE = keySize >> 3; - base->KEYINDEX = (uint32_t)keyIndex; - - /* begin */ - base->CTRL = PUF_CTRL_GENERATEKEY_MASK; - - /* wait till command is accepted */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy read KC */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) - { - temp32 = base->CODEOUTPUT; - if (keyCodeSize >= sizeof(uint32_t)) - { - *keyCodeAligned = temp32; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - } - } - - /* get status */ - if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Set user key - * - * The digital fingerprint generated during the Enroll/Start - * operations and a user key (UK) provided as input are used to - * generate a Key Code (KC). This KC is sent returned to be stored - * in an NVM or a file. This operation needs to be done only once for each user key. - * - * param base PUF peripheral base address - * param keyIndex PUF key index register - * param userKey Word aligned address of input user key. - * param userKeySize Size of the input user key in bytes. - * param[out] keyCode Word aligned address of the resulting key code. - * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize). - * return Status of set user key operation. - */ -status_t PUF_SetUserKey(PUF_Type *base, - puf_key_index_register_t keyIndex, - const uint8_t *userKey, - size_t userKeySize, - uint8_t *keyCode, - size_t keyCodeSize) -{ - status_t status = kStatus_Fail; - uint32_t *keyCodeAligned = NULL; - const uint32_t *userKeyAligned = NULL; - register uint32_t temp32 = 0; - - /* check if SET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSETKEY_MASK)) - { - return kStatus_Fail; - } - - /* only work with aligned keyCode */ - if (0U != (0x3u & (uintptr_t)keyCode)) - { - return kStatus_InvalidArgument; - } - - /* Check that userKeySize is in the correct range and that it is multiple of 8 */ - if ((userKeySize < (uint32_t)kPUF_KeySizeMin) || (userKeySize > (uint32_t)kPUF_KeySizeMax) || - (0U != (userKeySize & 0x7U))) - { - return kStatus_InvalidArgument; - } - - /* check that keyCodeSize is correct for given userKeySize */ - if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize)) - { - return kStatus_InvalidArgument; - } - - if ((uint32_t)keyIndex > (uint32_t)kPUF_KeyIndexMax) - { - return kStatus_InvalidArgument; - } - - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - userKeyAligned = (const uint32_t *)(uintptr_t)userKey; - - /* program the key size and index */ - base->KEYSIZE = userKeySize >> 3; /* convert to 64-bit blocks */ - base->KEYINDEX = (uint32_t)keyIndex; - - /* We have to store the user key on index 0 swaped for HW bus */ - if (keyIndex == kPUF_KeyIndex_00) - { - userKeyAligned = userKeyAligned + (userKeySize / sizeof(uint32_t)); - } - - /* begin */ - base->CTRL = PUF_CTRL_SETKEY_MASK; - - /* wait till command is accepted */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy write UK and read KC */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_KEYINREQ_MASK & base->STAT)) - { - if (userKeySize >= sizeof(uint32_t)) - { -#if defined(LPC54S018_SERIES) - if (keyIndex == kPUF_KeyIndex_00) - { - userKeyAligned--; - temp32 = *userKeyAligned; - userKeySize -= sizeof(uint32_t); - } -#else - if (keyIndex == kPUF_KeyIndex_00) - { - userKeyAligned--; - temp32 = __REV(*userKeyAligned); - userKeySize--; - } -#endif /* defined(LPC54S018_SERIES) */ - else if (keyIndex != kPUF_KeyIndex_00) - { - temp32 = *userKeyAligned; - userKeyAligned++; - userKeySize -= sizeof(uint32_t); - } - else - { - /* Intentional empty */ - } - } - base->KEYINPUT = temp32; - } - - if (0U != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) - { - temp32 = base->CODEOUTPUT; - if (keyCodeSize >= sizeof(uint32_t)) - { - *keyCodeAligned = temp32; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - } - } - - /* get status */ - if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -static status_t puf_getHwKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize) -{ - status_t status = kStatus_Fail; - uint32_t *keyCodeAligned = NULL; - register uint32_t temp32 = 0; - - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - - /* begin */ - base->CTRL = PUF_CTRL_GETKEY_MASK; - - /* wait till command is accepted */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy send KC, key is reconstructed to HW bus */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_CODEINREQ_MASK & base->STAT)) - { - if (keyCodeSize >= sizeof(uint32_t)) - { - temp32 = *keyCodeAligned; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - base->CODEINPUT = temp32; - } - } - - /* get status */ - if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Reconstruct hw bus key from a key code - * - * The digital fingerprint generated during the Start operation and the KC - * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This - * operation needs to be done every time a key is needed. - * This function accepts only Key Codes created for PUF index register kPUF_KeyIndex_00. - * Such a key is output directly to a dedicated hardware bus. The reconstructed key is not exposed to system memory. - * - * param base PUF peripheral base address - * param keyCode Word aligned address of the input key code. - * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * param keySlot key slot to output on hw bus. Parameter is ignored on devices with less than two key slots. - * param keyMask key masking value. Shall be random for each POR/reset. Value does not have to be cryptographicaly - * secure. - * return Status of get key operation. - */ -status_t PUF_GetHwKey( - PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, puf_key_slot_t keySlot, uint32_t keyMask) -{ - status_t status = kStatus_Fail; - uint32_t keyIndex; - - /* check if GET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK)) - { - return kStatus_Fail; - } - - /* only work with aligned keyCode */ - if (0U != (0x3u & (uintptr_t)keyCode)) - { - return kStatus_Fail; - } - - /* check that keyCodeSize is at least PUF_MIN_KEY_CODE_SIZE */ - if (keyCodeSize < PUF_MIN_KEY_CODE_SIZE) - { - return kStatus_InvalidArgument; - } - - keyIndex = (uint32_t)(0x0Fu & (uint32_t)keyCode[1]); - - /* check the Key Code header byte 1. index must be zero for the hw key. */ - if (kPUF_KeyIndex_00 != (puf_key_index_register_t)keyIndex) - { - return kStatus_Fail; - } - -#if defined(PUF_KEYMASK_COUNT) && (PUF_KEYMASK_COUNT > 0) - volatile uint32_t *keyMask_reg = NULL; - uint32_t regVal = ((uint32_t)2U << ((uint32_t)2U * (uint32_t)keySlot)); - - switch (keySlot) - { - case kPUF_KeySlot0: - keyMask_reg = &base->KEYMASK[0]; - break; - - case kPUF_KeySlot1: - keyMask_reg = &base->KEYMASK[1]; - break; -#if (PUF_KEYMASK_COUNT > 2) - case kPUF_KeySlot2: - keyMask_reg = &base->KEYMASK[2]; - break; - - case kPUF_KeySlot3: - keyMask_reg = &base->KEYMASK[3]; - break; -#endif /* PUF_KEYMASK_COUNT > 2 */ - default: - status = kStatus_InvalidArgument; - break; - } -#endif /* PUF_KEYMASK_COUNT */ - - if (status != kStatus_InvalidArgument) - { -#if defined(PUF_KEYMASK_COUNT) && (PUF_KEYMASK_COUNT > 0) - base->KEYRESET = regVal; - base->KEYENABLE = regVal; - *keyMask_reg = keyMask; -#endif /* FSL_FEATURE_PUF_HAS_KEYSLOTS */ - - status = puf_getHwKey(base, keyCode, keyCodeSize); - -#if defined(FSL_FEATURE_PUF_HAS_SHIFT_STATUS) && (FSL_FEATURE_PUF_HAS_SHIFT_STATUS > 0) - size_t keyWords = 0; - - if (status == kStatus_Success) - { - /* if the corresponding shift count does not match, return fail anyway */ - keyWords = ((((size_t)keyCode[3]) * 2U) - 1u) << ((size_t)keySlot << 2U); - if (keyWords != ((0x0FUL << ((uint32_t)keySlot << 2U)) & base->SHIFT_STATUS)) - { - status = kStatus_Fail; - } - } -#elif defined(PUF_IDXBLK_SHIFT_IND_KEY0_MASK) && PUF_IDXBLK_SHIFT_IND_KEY0_MASK - size_t keyWords = 0; - - if (status == kStatus_Success) - { - /* if the corresponding shift count does not match, return fail anyway */ - keyWords = ((((size_t)keyCode[3]) * 2U) - 1u) << ((size_t)keySlot << 2U); - if (keyWords != ((0x0FUL << ((uint32_t)keySlot << 2U)) & base->IDXBLK_SHIFT)) - { - status = kStatus_Fail; - } - } -#endif /* FSL_FEATURE_PUF_HAS_SHIFT_STATUS || PUF_IDXBLK_SHIFT_IND_KEY0_MASK */ - } - - return status; -} - -/*! - * brief Checks if Get Key operation is allowed. - * - * This function returns true if get key operation is allowed. - * - * param base PUF peripheral base address - * return true if get key operation is allowed - */ -bool PUF_IsGetKeyAllowed(PUF_Type *base) -{ - /* check if GET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK)) - { - return false; - } - - return true; -} - -/*! - * brief Reconstruct key from a key code - * - * The digital fingerprint generated during the Start operation and the KC - * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This - * operation needs to be done every time a key is needed. - * This function accepts only Key Codes created for PUF index registers kPUF_KeyIndex_01 to kPUF_KeyIndex_15. - * - * param base PUF peripheral base address - * param keyCode Word aligned address of the input key code. - * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * param[out] key Word aligned address of output key. - * param keySize Size of the output key in bytes. - * return Status of get key operation. - */ -status_t PUF_GetKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize) -{ - status_t status = kStatus_Fail; - uint32_t *keyCodeAligned = NULL; - uint32_t *keyAligned = NULL; - uint32_t keyIndex; - register uint32_t temp32 = 0; - - /* check if GET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK)) - { - return kStatus_Fail; - } - - /* only work with aligned keyCode */ - if (0U != (0x3u & (uintptr_t)keyCode)) - { - return kStatus_Fail; - } - - /* only work with aligned key */ - if (0U != (0x3u & (uintptr_t)key)) - { - return kStatus_Fail; - } - - /* check that keyCodeSize is correct for given keySize */ - if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize)) - { - return kStatus_InvalidArgument; - } - - keyIndex = (0x0Fu & (uint32_t)keyCode[1]); - - /* check the Key Code header byte 1. index must be non-zero for the register key. */ - if (kPUF_KeyIndex_00 == (puf_key_index_register_t)keyIndex) - { - return kStatus_Fail; - } - - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - keyAligned = (uint32_t *)(uintptr_t)key; - - /* begin */ - base->CTRL = PUF_CTRL_GETKEY_MASK; - - /* wait till command is accepted */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy send KC, read key */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_CODEINREQ_MASK & base->STAT)) - { - temp32 = 0; - if (keyCodeSize >= sizeof(uint32_t)) - { - temp32 = *keyCodeAligned; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - base->CODEINPUT = temp32; - } - - if (0U != (PUF_STAT_KEYOUTAVAIL_MASK & base->STAT)) - { - keyIndex = base->KEYOUTINDEX; - temp32 = base->KEYOUTPUT; - if (keySize >= sizeof(uint32_t)) - { - *keyAligned = temp32; - keyAligned++; - keySize -= sizeof(uint32_t); - } - } - } - - /* get status */ - if ((keyIndex != 0U) && (0U != (base->STAT & PUF_STAT_SUCCESS_MASK))) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Zeroize PUF - * - * This function clears all PUF internal logic and puts the PUF to error state. - * - * param base PUF peripheral base address - * return Status of the zeroize operation. - */ -status_t PUF_Zeroize(PUF_Type *base) -{ - status_t status = kStatus_Fail; - - /* zeroize command is always allowed */ - base->CTRL = PUF_CTRL_ZEROIZE_MASK; - - /* check that command is accepted */ - if ((0U != (base->STAT & PUF_STAT_ERROR_MASK)) && (0U == base->ALLOW)) - { - status = kStatus_Success; - } - - return status; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_puf.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_puf.h deleted file mode 100644 index b8a5c51c856..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_puf.h +++ /dev/null @@ -1,335 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PUF_H_ -#define _PUF_H_ - -#include -#include - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! - * @addtogroup puf_driver - * @{ - */ -/*! @name Driver version */ -/*@{*/ -/*! @brief PUF driver version. Version 2.1.6. - * - * Current version: 2.1.6 - * - * Change log: - * - 2.0.0 - * - Initial version. - * - 2.0.1 - * - Fixed puf_wait_usec function optimization issue. - * - 2.0.2 - * - Add PUF configuration structure and support for PUF SRAM controller. - * Remove magic constants. - * - 2.0.3 - * - Fix MISRA C-2012 issue. - * - 2.1.0 - * - Align driver with PUF SRAM controller registers on LPCXpresso55s16. - * - Update initizalition logic . - * - 2.1.1 - * - Fix ARMGCC build warning . - * - 2.1.2 - * - Update: Add automatic big to little endian swap for user - * (pre-shared) keys destinated to secret hardware bus (PUF key index 0). - * - 2.1.3 - * - Fix MISRA C-2012 issue. - * - 2.1.4 - * - Replace register uint32_t ticksCount with volatile uint32_t ticksCount in puf_wait_usec() to prevent optimization - * out delay loop. - * - 2.1.5 - * - Use common SDK delay in puf_wait_usec() - * - 2.1.6 - * - Changed wait time in PUF_Init(), when initialization fails it will try PUF_Powercycle() with shorter time. If - * this shorter time will also fail, initialization will be tried with worst case time as before. - */ -#define FSL_PUF_DRIVER_VERSION (MAKE_VERSION(2, 1, 6)) -/*@}*/ - -typedef enum _puf_key_index_register -{ - kPUF_KeyIndex_00 = 0x00U, - kPUF_KeyIndex_01 = 0x01U, - kPUF_KeyIndex_02 = 0x02U, - kPUF_KeyIndex_03 = 0x03U, - kPUF_KeyIndex_04 = 0x04U, - kPUF_KeyIndex_05 = 0x05U, - kPUF_KeyIndex_06 = 0x06U, - kPUF_KeyIndex_07 = 0x07U, - kPUF_KeyIndex_08 = 0x08U, - kPUF_KeyIndex_09 = 0x09U, - kPUF_KeyIndex_10 = 0x0AU, - kPUF_KeyIndex_11 = 0x0BU, - kPUF_KeyIndex_12 = 0x0CU, - kPUF_KeyIndex_13 = 0x0DU, - kPUF_KeyIndex_14 = 0x0EU, - kPUF_KeyIndex_15 = 0x0FU, -} puf_key_index_register_t; - -typedef enum _puf_min_max -{ - kPUF_KeySizeMin = 8u, - kPUF_KeySizeMax = 512u, - kPUF_KeyIndexMax = kPUF_KeyIndex_15, -} puf_min_max_t; - -/*! @brief PUF key slot. */ -typedef enum _puf_key_slot -{ - kPUF_KeySlot0 = 0U, /*!< PUF key slot 0 */ - kPUF_KeySlot1 = 1U, /*!< PUF key slot 1 */ -#if defined(PUF_KEYMASK_COUNT) && (PUF_KEYMASK_COUNT > 2) - kPUF_KeySlot2 = 2U, /*!< PUF key slot 2 */ - kPUF_KeySlot3 = 3U, /*!< PUF key slot 3 */ -#endif -} puf_key_slot_t; - -typedef struct -{ - uint32_t dischargeTimeMsec; - uint32_t coreClockFrequencyHz; -#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* LPCXpresso55s16 */ - PUF_SRAM_CTRL_Type *puf_sram_base; - uint8_t CKGATING; -#endif /* FSL_FEATURE_PUF_HAS_SRAM_CTRL */ -} puf_config_t; -/*! @brief Get Key Code size in bytes from key size in bytes at compile time. */ -#define PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(x) ((160u + (((((x) << 3) + 255u) >> 8) << 8)) >> 3) -#define PUF_MIN_KEY_CODE_SIZE PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(8UL) -#define PUF_ACTIVATION_CODE_SIZE 1192U -#define KEYSTORE_PUF_DISCHARGE_TIME_FIRST_TRY_MS 50 -#define KEYSTORE_PUF_DISCHARGE_TIME_MAX_MS 400 - -/*! PUF status return codes. */ -enum -{ - kStatus_EnrollNotAllowed = MAKE_STATUS(kStatusGroup_PUF, 1), - kStatus_StartNotAllowed = MAKE_STATUS(kStatusGroup_PUF, 2) -}; - -/*! @} */ -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @brief Sets the default configuration of PUF - * - * This function initialize PUF config structure to default values. - * - * @param conf PUF configuration structure - */ -void PUF_GetDefaultConfig(puf_config_t *conf); - -/*! - * @brief Initialize PUF - * - * This function enables power to PUF block and waits until the block initializes. - * - * @param base PUF peripheral base address - * @param conf PUF configuration structure - * @return Status of the init operation - */ -status_t PUF_Init(PUF_Type *base, puf_config_t *conf); - -/*! - * @brief Denitialize PUF - * - * This function disables power to PUF SRAM and peripheral clock. - * - * @param base PUF peripheral base address - * @param conf PUF configuration structure - */ -void PUF_Deinit(PUF_Type *base, puf_config_t *conf); - -/*! - * @brief Enroll PUF - * - * This function derives a digital fingerprint, generates the corresponding Activation Code (AC) - * and returns it to be stored in an NVM or a file. This step needs to be - * performed only once for each device. This function may be permanently disallowed by a fuse. - * - * @param base PUF peripheral base address - * @param[out] activationCode Word aligned address of the resulting activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. - * @return Status of enroll operation. - */ -status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize); - -/*! - * @brief Start PUF - * - * The Activation Code generated during the Enroll operation is used to - * reconstruct the digital fingerprint. This needs to be done after every power-up - * and reset. - * - * @param base PUF peripheral base address - * @param activationCode Word aligned address of the input activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. - * @return Status of start operation. - */ -status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize); - -/*! - * @brief Set intrinsic key - * - * The digital fingerprint generated during the Enroll/Start - * operations is used to generate a Key Code (KC) that defines a unique intrinsic - * key. This KC is returned to be stored in an NVM or a file. This operation - * needs to be done only once for each intrinsic key. - * Each time a Set Intrinsic Key operation is executed a new unique key is - * generated. - * - * @param base PUF peripheral base address - * @param keyIndex PUF key index register - * @param keySize Size of the intrinsic key to generate in bytes. - * @param[out] keyCode Word aligned address of the resulting key code. - * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * @return Status of set intrinsic key operation. - */ -status_t PUF_SetIntrinsicKey( - PUF_Type *base, puf_key_index_register_t keyIndex, size_t keySize, uint8_t *keyCode, size_t keyCodeSize); - -/*! - * @brief Set user key - * - * The digital fingerprint generated during the Enroll/Start - * operations and a user key (UK) provided as input are used to - * generate a Key Code (KC). This KC is sent returned to be stored - * in an NVM or a file. This operation needs to be done only once for each user key. - * - * @param base PUF peripheral base address - * @param keyIndex PUF key index register - * @param userKey Word aligned address of input user key. - * @param userKeySize Size of the input user key in bytes. - * @param[out] keyCode Word aligned address of the resulting key code. - * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize). - * @return Status of set user key operation. - */ -status_t PUF_SetUserKey(PUF_Type *base, - puf_key_index_register_t keyIndex, - const uint8_t *userKey, - size_t userKeySize, - uint8_t *keyCode, - size_t keyCodeSize); - -/*! - * @brief Reconstruct key from a key code - * - * The digital fingerprint generated during the Start operation and the KC - * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This - * operation needs to be done every time a key is needed. - * This function accepts only Key Codes created for PUF index registers kPUF_KeyIndex_01 to kPUF_KeyIndex_15. - * - * @param base PUF peripheral base address - * @param keyCode Word aligned address of the input key code. - * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * @param[out] key Word aligned address of output key. - * @param keySize Size of the output key in bytes. - * @return Status of get key operation. - */ -status_t PUF_GetKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize); - -/*! - * @brief Reconstruct hw bus key from a key code - * - * The digital fingerprint generated during the Start operation and the KC - * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This - * operation needs to be done every time a key is needed. - * This function accepts only Key Codes created for PUF index register kPUF_KeyIndex_00. - * Such a key is output directly to a dedicated hardware bus. The reconstructed key is not exposed to system memory. - * - * @param base PUF peripheral base address - * @param keyCode Word aligned address of the input key code. - * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * @param keySlot key slot to output on hw bus. Parameter is ignored on devices with less than two key slots. - * @param keyMask key masking value. Shall be random for each POR/reset. Value does not have to be cryptographicaly - * secure. - * @return Status of get key operation. - */ -status_t PUF_GetHwKey( - PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, puf_key_slot_t keySlot, uint32_t keyMask); - -/*! - * @brief Zeroize PUF - * - * This function clears all PUF internal logic and puts the PUF to error state. - * - * @param base PUF peripheral base address - * @return Status of the zeroize operation. - */ -status_t PUF_Zeroize(PUF_Type *base); - -/*! - * @brief Checks if Get Key operation is allowed. - * - * This function returns true if get key operation is allowed. - * - * @param base PUF peripheral base address - * @return true if get key operation is allowed - */ -bool PUF_IsGetKeyAllowed(PUF_Type *base); - -#if defined(PUF_CFG_BLOCKKEYOUTPUT_MASK) && PUF_CFG_BLOCKKEYOUTPUT_MASK -static inline void PUF_BlockSetKey(PUF_Type *base) -{ - base->CFG |= PUF_CFG_BLOCKKEYOUTPUT_MASK; /* block set key */ -} -#endif /* PUF_CFG_BLOCKKEYOUTPUT_MASK */ - -#if defined(PUF_CFG_PUF_BLOCK_SET_KEY_MASK) && PUF_CFG_PUF_BLOCK_SET_KEY_MASK -static inline void PUF_BlockSetKey(PUF_Type *base) -{ - base->CFG |= PUF_CFG_PUF_BLOCK_SET_KEY_MASK; /* block set key */ -} -#endif /* PUF_CFG_PUF_BLOCK_SET_KEY_MASK */ - -#if defined(PUF_CFG_BLOCKENROLL_SETKEY_MASK) && PUF_CFG_BLOCKENROLL_SETKEY_MASK -static inline void PUF_BlockEnroll(PUF_Type *base) -{ - base->CFG |= PUF_CFG_BLOCKENROLL_SETKEY_MASK; /* block enroll */ -} -#endif /* PUF_CFG_BLOCKENROLL_SETKEY_MASK */ - -#if defined(PUF_CFG_PUF_BLOCK_ENROLL_MASK) && PUF_CFG_PUF_BLOCK_ENROLL_MASK -static inline void PUF_BlockEnroll(PUF_Type *base) -{ - base->CFG |= PUF_CFG_PUF_BLOCK_ENROLL_MASK; /* block enroll */ -} -#endif /* PUF_CFG_PUF_BLOCK_ENROLL_MASK */ - -/*! - * @brief Powercycle PUF - * - * This function make powercycle. - * - * @param base PUF peripheral base address - * @param conf PUF configuration structure - * @return Status of the powercycle operation. - */ -status_t PUF_PowerCycle(PUF_Type *base, puf_config_t *conf); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -#endif /* _PUF_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_reset.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_reset.c deleted file mode 100644 index 4326e0dae24..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_reset.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#include "fsl_reset.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.reset" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - -/*! - * brief Assert reset to peripheral. - * - * Asserts reset signal to specified peripheral module. - * - * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_SetPeripheralReset(reset_ip_name_t peripheral) -{ - const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; - const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); - const uint32_t bitMask = 1UL << bitPos; - - assert(bitPos < 32u); - - /* reset register is in SYSCON */ - /* set bit */ - SYSCON->PRESETCTRLSET[regIndex] = bitMask; - /* wait until it reads 0b1 */ - while (0u == (SYSCON->PRESETCTRLX[regIndex] & bitMask)) - { - } -} - -/*! - * brief Clear reset to peripheral. - * - * Clears reset signal to specified peripheral module, allows it to operate. - * - * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) -{ - const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; - const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); - const uint32_t bitMask = 1UL << bitPos; - - assert(bitPos < 32u); - - /* reset register is in SYSCON */ - - /* clear bit */ - SYSCON->PRESETCTRLCLR[regIndex] = bitMask; - /* wait until it reads 0b0 */ - while (bitMask == (SYSCON->PRESETCTRLX[regIndex] & bitMask)) - { - } -} - -/*! - * brief Reset peripheral module. - * - * Reset peripheral module. - * - * param peripheral Peripheral to reset. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_PeripheralReset(reset_ip_name_t peripheral) -{ - RESET_SetPeripheralReset(peripheral); - RESET_ClearPeripheralReset(peripheral); -} - -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_reset.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_reset.h deleted file mode 100644 index 314f6c66a37..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_reset.h +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_RESET_H_ -#define _FSL_RESET_H_ - -#include -#include -#include -#include -#include "fsl_device_registers.h" - -/*! - * @addtogroup reset - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief reset driver version 2.0.3. */ -#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ - -/*! - * @brief Enumeration for peripheral reset control bits - * - * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers - */ -typedef enum _SYSCON_RSTn -{ - kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */ - kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */ - kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */ - kSRAM3_RST_SHIFT_RSTn = 0 | 5U, /**< SRAM3 reset control */ - kSRAM4_RST_SHIFT_RSTn = 0 | 6U, /**< SRAM4 reset control */ - kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ - kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ - kSPIFI_RST_SHIFT_RSTn = 0 | 10U, /**< SPIFI reset control */ - kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */ - kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ - kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ - kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ - kGPIO2_RST_SHIFT_RSTn = 0 | 16U, /**< GPIO2 reset control */ - kGPIO3_RST_SHIFT_RSTn = 0 | 17U, /**< GPIO3 reset control */ - kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ - kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ - kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ - kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ - kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ - kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */ - kMAILBOX_RST_SHIFT_RSTn = 0 | 26U, /**< Mailbox reset control */ - kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ - - kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ - kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */ - kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ - kSCTIPU_RST_SHIFT_RSTn = 65536 | 6U, /**< SCTIPU reset control */ - kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ - kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ - kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ - kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ - kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ - kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ - kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ - kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ - kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ - kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */ - kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0 Device reset control */ - kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */ - kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */ - kPVT_RST_SHIFT_RSTn = 65536 | 28U, /**< PVT reset control */ - kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */ - kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */ - - kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */ - kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */ - kSDIO_RST_SHIFT_RSTn = 131072 | 3U, /**< SDIO reset control */ - kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USBHS Host reset control */ - kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USBHS Device reset control */ - kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB RAM reset control */ - kUSB1_RST_SHIFT_RSTn = 131072 | 7U, /**< USBHS reset control */ - kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */ - kGPIO4_RST_SHIFT_RSTn = 131072 | 9U, /**< GPIO4 reset control */ - kGPIO5_RST_SHIFT_RSTn = 131072 | 10U, /**< GPIO5 reset control */ - kAES_RST_SHIFT_RSTn = 131072 | 11U, /**< AES reset control */ - kOTP_RST_SHIFT_RSTn = 131072 | 12U, /**< OTP reset control */ - kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */ - kMUX1_RST_SHIFT_RSTn = 131072 | 14U, /**< Input mux1 reset control */ - kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */ - kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */ - kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */ - kPOWERQUAD_RST_SHIFT_RSTn = 131072 | 19U, /**< PowerQuad reset control */ - kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */ - kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */ - kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */ - kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */ - kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */ - kCAP0_RST_SHIFT_RSTn = 131072 | 25U, /**< CASPER reset control */ - kOSTIMER1_RST_SHIFT_RSTn = 131072 | 26U, /**< OSTIMER1 reset control */ - kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */ - kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */ - kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */ - kGPIOSECINT_RST_SHIFT_RSTn = 131072 | 30U, /**< GPIO Secure int reset control */ -} SYSCON_RSTn_t; - -/** Array initializers with peripheral reset bits **/ -#define ADC_RSTS \ - { \ - kADC0_RST_SHIFT_RSTn \ - } /* Reset bits for ADC peripheral */ -#define AES_RSTS \ - { \ - kAES_RST_SHIFT_RSTn \ - } /* Reset bits for AES peripheral */ -#define CRC_RSTS \ - { \ - kCRC_RST_SHIFT_RSTn \ - } /* Reset bits for CRC peripheral */ -#define CTIMER_RSTS \ - { \ - kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \ - kCTIMER4_RST_SHIFT_RSTn \ - } /* Reset bits for CTIMER peripheral */ -#define DMA_RSTS_N \ - { \ - kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \ - } /* Reset bits for DMA peripheral */ - -#define FLEXCOMM_RSTS \ - { \ - kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ - kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kHSLSPI_RST_SHIFT_RSTn \ - } /* Reset bits for FLEXCOMM peripheral */ -#define GINT_RSTS \ - { \ - kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ - } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ -#define GPIO_RSTS_N \ - { \ - kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \ - kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn \ - } /* Reset bits for GPIO peripheral */ -#define INPUTMUX_RSTS \ - { \ - kMUX0_RST_SHIFT_RSTn, kMUX1_RST_SHIFT_RSTn \ - } /* Reset bits for INPUTMUX peripheral */ -#define IOCON_RSTS \ - { \ - kIOCON_RST_SHIFT_RSTn \ - } /* Reset bits for IOCON peripheral */ -#define FLASH_RSTS \ - { \ - kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ - } /* Reset bits for Flash peripheral */ -#define MRT_RSTS \ - { \ - kMRT_RST_SHIFT_RSTn \ - } /* Reset bits for MRT peripheral */ -#define OTP_RSTS \ - { \ - kOTP_RST_SHIFT_RSTn \ - } /* Reset bits for OTP peripheral */ -#define PINT_RSTS \ - { \ - kPINT_RST_SHIFT_RSTn \ - } /* Reset bits for PINT peripheral */ -#define RNG_RSTS \ - { \ - kRNG_RST_SHIFT_RSTn \ - } /* Reset bits for RNG peripheral */ -#define SDIO_RST \ - { \ - kSDIO_RST_SHIFT_RSTn \ - } /* Reset bits for SDIO peripheral */ -#define SCT_RSTS \ - { \ - kSCT0_RST_SHIFT_RSTn \ - } /* Reset bits for SCT peripheral */ -#define SPIFI_RSTS \ - { \ - kSPIFI_RST_SHIFT_RSTn \ - } /* Reset bits for SPIFI peripheral */ -#define USB0D_RST \ - { \ - kUSB0D_RST_SHIFT_RSTn \ - } /* Reset bits for USB0D peripheral */ -#define USB0HMR_RST \ - { \ - kUSB0HMR_RST_SHIFT_RSTn \ - } /* Reset bits for USB0HMR peripheral */ -#define USB0HSL_RST \ - { \ - kUSB0HSL_RST_SHIFT_RSTn \ - } /* Reset bits for USB0HSL peripheral */ -#define USB1H_RST \ - { \ - kUSB1H_RST_SHIFT_RSTn \ - } /* Reset bits for USB1H peripheral */ -#define USB1D_RST \ - { \ - kUSB1D_RST_SHIFT_RSTn \ - } /* Reset bits for USB1D peripheral */ -#define USB1RAM_RST \ - { \ - kUSB1RAM_RST_SHIFT_RSTn \ - } /* Reset bits for USB1RAM peripheral */ -#define UTICK_RSTS \ - { \ - kUTICK_RST_SHIFT_RSTn \ - } /* Reset bits for UTICK peripheral */ -#define WWDT_RSTS \ - { \ - kWWDT_RST_SHIFT_RSTn \ - } /* Reset bits for WWDT peripheral */ -#define CAPT_RSTS_N \ - { \ - kCAP0_RST_SHIFT_RSTn \ - } /* Reset bits for CAPT peripheral */ -#define PLU_RSTS_N \ - { \ - kPLULUT_RST_SHIFT_RSTn \ - } /* Reset bits for PLU peripheral */ -#define OSTIMER_RSTS \ - { \ - kOSTIMER0_RST_SHIFT_RSTn \ - } /* Reset bits for OSTIMER peripheral */ -#define POWERQUAD_RSTS \ - { \ - kPOWERQUAD_RST_SHIFT_RSTn \ - } /* Reset bits for Powerquad peripheral */ -#define CASPER_RSTS \ - { \ - kCASPER_RST_SHIFT_RSTn \ - } /* Reset bits for Casper peripheral */ -#define HASHCRYPT_RSTS \ - { \ - kHASHCRYPT_RST_SHIFT_RSTn \ - } /* Reset bits for Hashcrypt peripheral */ -#define PUF_RSTS \ - { \ - kPUF_RST_SHIFT_RSTn \ - } /* Reset bits for PUF peripheral */ -typedef SYSCON_RSTn_t reset_ip_name_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Assert reset to peripheral. - * - * Asserts reset signal to specified peripheral module. - * - * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_SetPeripheralReset(reset_ip_name_t peripheral); - -/*! - * @brief Clear reset to peripheral. - * - * Clears reset signal to specified peripheral module, allows it to operate. - * - * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); - -/*! - * @brief Reset peripheral module. - * - * Reset peripheral module. - * - * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_PeripheralReset(reset_ip_name_t peripheral); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_RESET_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_rng.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_rng.c deleted file mode 100644 index 1b2e9d4d61e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_rng.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright 2017, 2019, 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_rng.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.rng_1" -#endif - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/******************************************************************************* - * Prototypes - *******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -static void rng_accumulateEntropy(RNG_Type *base) -{ - uint32_t minChiSq; - uint32_t maxChiSq; - - /* Steps to accumulate entropy, more info can be found in LPC55SXX UM*/ - - /* Select fourth clock on which to compute CHI SQUARE statistics*/ - base->COUNTER_CFG = (base->COUNTER_CFG & ~RNG_COUNTER_CFG_CLOCK_SEL_MASK) | RNG_COUNTER_CFG_CLOCK_SEL(4U); - - /* Activate CHI computing */ - base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(1U); - - /* Read min chi squared value, on power on should be higher than max chi squared value */ - minChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT); - - /* Read max chi squared value */ - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - - /* Wait until minChiSq decreases and become smaller than maxChiSq*/ - while (minChiSq > (maxChiSq - 1U)) - { - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - minChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT); - } -} - -/*! - * @brief Gets a entry data from the RNG. - * - * This function gets an entropy data from RNG. - */ -static uint32_t rng_readEntropy(RNG_Type *base) -{ - uint32_t data; - uint32_t refreshCnt, maxChiSq, tmpShift4x; - - /* Activate CHI computing */ - base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(1); - - /* Wait for refresh count become 31 to refill fresh entropy since last read of random number*/ - do - { - refreshCnt = ((base->COUNTER_VAL & RNG_COUNTER_VAL_REFRESH_CNT_MASK) >> RNG_COUNTER_VAL_REFRESH_CNT_SHIFT); - } while (refreshCnt < 31U); - - /* reading RANDOM_NUMBER register will reset refCnt to 0 */ - data = base->RANDOM_NUMBER; - - /* Perform CHI computing by checking max chi squared value */ - /* Wait until maxChiSq become smaller or equal than 4, then next random number can be read*/ - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - - while (maxChiSq > 4U) - { - /* Deactivate CHI computing to reset*/ - base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(0); - - /* read Shift4x register, if is less than 7 increment it and then start accumulating entropy again */ - tmpShift4x = ((base->COUNTER_CFG & RNG_COUNTER_CFG_SHIFT4X_MASK) >> RNG_COUNTER_CFG_SHIFT4X_SHIFT); - if (tmpShift4x < 7U) - { - tmpShift4x++; - base->COUNTER_CFG = - (base->COUNTER_CFG & ~RNG_COUNTER_CFG_SHIFT4X_MASK) | RNG_COUNTER_CFG_SHIFT4X(tmpShift4x); - } - rng_accumulateEntropy(base); - - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - } - - return data; -} - -void RNG_Init(RNG_Type *base) -{ - uint32_t maxChiSq, tmpShift4x; - - /* Clear ring oscilator disable bit*/ - PMC->PDRUNCFGCLR0 = PMC_PDRUNCFG0_PDEN_RNG_MASK; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Rng); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kRNG_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - - /* Turn on CHI Squared test */ - /* Activate CHI computing and wait until min chi squared become smaller than max chi squared */ - rng_accumulateEntropy(base); - - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - - /* When maxChiSq is bigger than 4 its assumed there is not enough entropy and previous steps are repeated */ - /* When maxChiSq is 4 or less initialization is complete and random number can be read*/ - while (maxChiSq > 4U) - { - /* Deactivate CHI coputing to reset*/ - base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(0); - - /* read Shift4x register, if is less than 7 increment it and then start accumulating entropy again */ - tmpShift4x = ((base->COUNTER_CFG & RNG_COUNTER_CFG_SHIFT4X_MASK) >> RNG_COUNTER_CFG_SHIFT4X_SHIFT); - if (tmpShift4x < 7U) - { - tmpShift4x++; - base->COUNTER_CFG = - (base->COUNTER_CFG & ~RNG_COUNTER_CFG_SHIFT4X_MASK) | RNG_COUNTER_CFG_SHIFT4X(tmpShift4x); - } - rng_accumulateEntropy(base); - - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - } -} - -void RNG_Deinit(RNG_Type *base) -{ - /* Set ring oscilator disable bit*/ - PMC->PDRUNCFGSET0 = PMC_PDRUNCFG0_PDEN_RNG_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kRNG_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Rng); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -status_t RNG_GetRandomData(RNG_Type *base, void *data, size_t dataSize) -{ - status_t result = kStatus_Fail; - uint32_t random32; - uint32_t randomSize; - uint8_t *pRandom; - uint8_t *pData = (uint8_t *)data; - uint32_t i; - - /* Check input parameters.*/ - if (!((base != NULL) && (data != NULL) && (dataSize != 0U))) - { - result = kStatus_InvalidArgument; - } - else - { - /* Check that ring oscilator is enabled */ - if (0U == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_RNG_MASK)) - { - do - { - /* Read Entropy.*/ - random32 = rng_readEntropy(base); - pRandom = (uint8_t *)&random32; - - if (dataSize < sizeof(random32)) - { - randomSize = dataSize; - } - else - { - randomSize = sizeof(random32); - } - - for (i = 0; i < randomSize; i++) - { - *pData++ = *pRandom++; - } - - dataSize -= randomSize; - } while (dataSize > 0U); - - result = kStatus_Success; - } - } - - return result; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_rng.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_rng.h deleted file mode 100644 index 38279cad7fa..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_rng.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2017, 2019, 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_RNG_DRIVER_H_ -#define _FSL_RNG_DRIVER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup rng - * @{ - */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief RNG driver version. Version 2.0.3. - * - * Current version: 2.0.3 - * - * Change log: - * - Version 2.0.0 - * - Initial version - * - * - Version 2.0.1 - * - Fix MISRA C-2012 issue. - * - * - Version 2.0.2 - * - Add RESET_PeripheralReset function inside RNG_Init and RNG_Deinit functions. - * - * - Version 2.0.3 - * - Modified RNG_Init and RNG_GetRandomData functions, added rng_accumulateEntropy and rng_readEntropy functions. - * - These changes are reflecting recommended usage of RNG according to device UM. - */ -#define FSL_RNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initializes the RNG. - * - * This function initializes the RNG. - * When called, the RNG module and ring oscillator is enabled. - * - * @param base RNG base address - * @return If successful, returns the kStatus_RNG_Success. Otherwise, it returns an error. - */ -void RNG_Init(RNG_Type *base); - -/*! - * @brief Shuts down the RNG. - * - * This function shuts down the RNG. - * - * @param base RNG base address. - */ -void RNG_Deinit(RNG_Type *base); - -/*! - * @brief Gets random data. - * - * This function gets random data from the RNG. - * - * @param base RNG base address. - * @param data Pointer address used to store random data. - * @param dataSize Size of the buffer pointed by the data parameter. - * @return random data - */ -status_t RNG_GetRandomData(RNG_Type *base, void *data, size_t dataSize); - -/*! - * @brief Returns random 32-bit number. - * - * This function gets random number from the RNG. - * - * @param base RNG base address. - * @return random number - */ -static inline uint32_t RNG_GetRandomWord(RNG_Type *base) -{ - return base->RANDOM_NUMBER; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /*_FSL_RNG_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_rtc.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_rtc.c deleted file mode 100644 index b39370b6830..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_rtc.c +++ /dev/null @@ -1,322 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_rtc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_rtc" -#endif - -#define SECONDS_IN_A_DAY (86400U) -#define SECONDS_IN_A_HOUR (3600U) -#define SECONDS_IN_A_MINUTE (60U) -#define DAYS_IN_A_YEAR (365U) -#define YEAR_RANGE_START (1970U) -#define YEAR_RANGE_END (2099U) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Check whether the date and time passed in is valid - * - * @param datetime Pointer to structure where the date and time details are stored - * - * @return Returns false if the date & time details are out of range; true if in range - */ -static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime); - -/*! - * @brief Convert time data from datetime to seconds - * - * @param datetime Pointer to datetime structure where the date and time details are stored - * - * @return The result of the conversion in seconds - */ -static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime); - -/*! - * @brief Convert time data from seconds to a datetime structure - * - * @param seconds Seconds value that needs to be converted to datetime format - * @param datetime Pointer to the datetime structure where the result of the conversion is stored - */ -static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime); - -/******************************************************************************* - * Code - ******************************************************************************/ -static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Check year, month, hour, minute, seconds */ - if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || - (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) - { - /* If not correct then error*/ - return false; - } - - /* Adjust the days in February for a leap year */ - if ((((datetime->year & 3U) == 0U) && (datetime->year % 100U != 0U)) || (datetime->year % 400U == 0U)) - { - daysPerMonth[2] = 29U; - } - - /* Check the validity of the day */ - if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) - { - return false; - } - - return true; -} - -static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Number of days from begin of the non Leap-year*/ - /* Number of days from begin of the non Leap-year*/ - uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; - uint32_t seconds; - - /* Compute number of days from 1970 till given year*/ - seconds = ((uint32_t)datetime->year - 1970U) * DAYS_IN_A_YEAR; - /* Add leap year days */ - seconds += (((uint32_t)datetime->year / 4U) - (1970U / 4U)); - /* Add number of days till given month*/ - seconds += monthDays[datetime->month]; - /* Add days in given month. We subtract the current day as it is - * represented in the hours, minutes and seconds field*/ - seconds += ((uint32_t)datetime->day - 1U); - /* For leap year if month less than or equal to Febraury, decrement day counter*/ - if (((datetime->year & 3U) == 0x00U) && (datetime->month <= 2U)) - { - seconds--; - } - - seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + - (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; - - return seconds; -} - -static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint8_t i; - uint16_t daysInYear; - uint32_t secondsRemaining; - uint32_t days; - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Start with the seconds value that is passed in to be converted to date time format */ - secondsRemaining = seconds; - - /* Calcuate the number of days, we add 1 for the current day which is represented in the - * hours and seconds field - */ - days = secondsRemaining / SECONDS_IN_A_DAY + 1U; - - /* Update seconds left*/ - secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; - - /* Calculate the datetime hour, minute and second fields */ - datetime->hour = (uint8_t)(secondsRemaining / SECONDS_IN_A_HOUR); - secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; - datetime->minute = (uint8_t)(secondsRemaining / 60U); - datetime->second = (uint8_t)(secondsRemaining % SECONDS_IN_A_MINUTE); - - /* Calculate year */ - daysInYear = DAYS_IN_A_YEAR; - datetime->year = YEAR_RANGE_START; - while (days > daysInYear) - { - /* Decrease day count by a year and increment year by 1 */ - days -= daysInYear; - datetime->year++; - - /* Adjust the number of days for a leap year */ - if ((datetime->year & 3U) != 0x00U) - { - daysInYear = DAYS_IN_A_YEAR; - } - else - { - daysInYear = DAYS_IN_A_YEAR + 1U; - } - } - - /* Adjust the days in February for a leap year */ - if ((datetime->year & 3U) == 0x00U) - { - daysPerMonth[2] = 29U; - } - - for (i = 1U; i <= 12U; i++) - { - if (days <= daysPerMonth[i]) - { - datetime->month = i; - break; - } - else - { - days -= daysPerMonth[i]; - } - } - - datetime->day = (uint8_t)days; -} - -/*! - * brief Ungate the RTC clock and enables the RTC oscillator. - * - * note This API should be called at the beginning of the application using the RTC driver. - * - * param base RTC peripheral base address - */ -void RTC_Init(RTC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the RTC peripheral clock */ - CLOCK_EnableClock(kCLOCK_Rtc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_RTC_HAS_NO_RESET) && FSL_FEATURE_RTC_HAS_NO_RESET) - RESET_PeripheralReset(kRTC_RST_SHIFT_RSTn); -#endif - /* Make sure the reset bit is cleared */ - base->CTRL &= ~RTC_CTRL_SWRESET_MASK; - -#if !(defined(FSL_FEATURE_RTC_HAS_NO_OSC_PD) && FSL_FEATURE_RTC_HAS_NO_OSC_PD) - /* Make sure the RTC OSC is powered up */ - base->CTRL &= ~RTC_CTRL_RTC_OSC_PD_MASK; -#endif -} - -/*! - * brief Set the RTC date and time according to the given time structure. - * - * The RTC counter must be stopped prior to calling this function as writes to the RTC - * seconds register will fail if the RTC counter is running. - * - * param base RTC peripheral base address - * param datetime Pointer to structure where the date and time details to set are stored - * - * return kStatus_Success: Success in setting the time and starting the RTC - * kStatus_InvalidArgument: Error because the datetime format is incorrect - */ -status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Return error if the time provided is not valid */ - if (!(RTC_CheckDatetimeFormat(datetime))) - { - return kStatus_InvalidArgument; - } - - /* Set time in seconds */ - base->COUNT = RTC_ConvertDatetimeToSeconds(datetime); - - return kStatus_Success; -} - -/*! - * brief Gets the RTC time and stores it in the given time structure. - * - * param base RTC peripheral base address - * param datetime Pointer to structure where the date and time details are stored. - */ -void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t seconds = 0; - - seconds = RTC_GetSecondsTimerCount(base); - RTC_ConvertSecondsToDatetime(seconds, datetime); -} - -/*! - * brief Set the RTC alarm time - * - * The function checks whether the specified alarm time is greater than the present - * time. If not, the function does not set the alarm and returns an error. - * - * param base RTC peripheral base address - * param alarmTime Pointer to structure where the alarm time is stored. - * - * return kStatus_Success: success in setting the RTC alarm - * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect - * kStatus_Fail: Error because the alarm time has already passed - */ -status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) -{ - assert(alarmTime != NULL); - - uint32_t alarmSeconds = 0; - uint32_t currSeconds = 0; - - /* Return error if the alarm time provided is not valid */ - if (!(RTC_CheckDatetimeFormat(alarmTime))) - { - return kStatus_InvalidArgument; - } - - alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime); - - /* Get the current time */ - currSeconds = RTC_GetSecondsTimerCount(base); - - /* Return error if the alarm time has passed */ - if (alarmSeconds < currSeconds) - { - return kStatus_Fail; - } - - /* Set alarm in seconds*/ - base->MATCH = alarmSeconds; - - return kStatus_Success; -} - -/*! - * brief Return the RTC alarm time. - * - * param base RTC peripheral base address - * param datetime Pointer to structure where the alarm date and time details are stored. - */ -void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t alarmSeconds = 0; - - /* Get alarm in seconds */ - alarmSeconds = base->MATCH; - - RTC_ConvertSecondsToDatetime(alarmSeconds, datetime); -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_rtc.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_rtc.h deleted file mode 100644 index a960d8baf7c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_rtc.h +++ /dev/null @@ -1,493 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_RTC_H_ -#define _FSL_RTC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup rtc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*!< Version 2.1.2 */ -/*@}*/ - -/*! @brief List of RTC interrupts */ -typedef enum _rtc_interrupt_enable -{ - kRTC_AlarmInterruptEnable = RTC_CTRL_ALARMDPD_EN_MASK, /*!< Alarm interrupt.*/ - kRTC_WakeupInterruptEnable = RTC_CTRL_WAKEDPD_EN_MASK /*!< Wake-up interrupt.*/ -} rtc_interrupt_enable_t; - -/*! @brief List of RTC flags */ -typedef enum _rtc_status_flags -{ - kRTC_AlarmFlag = RTC_CTRL_ALARM1HZ_MASK, /*!< Alarm flag*/ - kRTC_WakeupFlag = RTC_CTRL_WAKE1KHZ_MASK /*!< 1kHz wake-up timer flag*/ -} rtc_status_flags_t; - -/*! @brief Structure is used to hold the date and time */ -typedef struct _rtc_datetime -{ - uint16_t year; /*!< Range from 1970 to 2099.*/ - uint8_t month; /*!< Range from 1 to 12.*/ - uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ - uint8_t hour; /*!< Range from 0 to 23.*/ - uint8_t minute; /*!< Range from 0 to 59.*/ - uint8_t second; /*!< Range from 0 to 59.*/ -} rtc_datetime_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Un-gate the RTC clock and enable the RTC oscillator. - * - * @note This API should be called at the beginning of the application using the RTC driver. - * - * @param base RTC peripheral base address - */ -void RTC_Init(RTC_Type *base); - -/*! - * @brief Stop the timer and gate the RTC clock - * - * @param base RTC peripheral base address - */ -static inline void RTC_Deinit(RTC_Type *base) -{ - /* Stop the RTC timer */ - base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the module clock */ - CLOCK_DisableClock(kCLOCK_Rtc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! @}*/ - -/*! - * @name Current Time & Alarm - * @{ - */ - -/*! - * @brief Set the RTC date and time according to the given time structure. - * - * The RTC counter must be stopped prior to calling this function as writes to the RTC - * seconds register will fail if the RTC counter is running. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the date and time details to set are stored - * - * @return kStatus_Success: Success in setting the time and starting the RTC - * kStatus_InvalidArgument: Error because the datetime format is incorrect - */ -status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime); - -/*! - * @brief Get the RTC time and stores it in the given time structure. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the date and time details are stored. - */ -void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime); - -/*! - * @brief Set the RTC alarm time - * - * The function checks whether the specified alarm time is greater than the present - * time. If not, the function does not set the alarm and returns an error. - * - * @param base RTC peripheral base address - * @param alarmTime Pointer to structure where the alarm time is stored. - * - * @return kStatus_Success: success in setting the RTC alarm - * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect - * kStatus_Fail: Error because the alarm time has already passed - */ -status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime); - -/*! - * @brief Return the RTC alarm time. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the alarm date and time details are stored. - */ -void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime); - -/*! @}*/ - -/*! - * @name RTC wake-up timer (1KHZ) Enable - * @{ - */ - -/*! - * @brief Enable the RTC wake-up timer (1KHZ). - * - * After calling this function, the RTC driver will use/un-use the RTC wake-up (1KHZ) at the same time. - * - * @param base RTC peripheral base address - * @param enable Use/Un-use the RTC wake-up timer. - * - true: Use RTC wake-up timer at the same time. - * - false: Un-use RTC wake-up timer, RTC only use the normal seconds timer by default. - */ -static inline void RTC_EnableWakeupTimer(RTC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK; - } - else - { - base->CTRL &= ~RTC_CTRL_RTC1KHZ_EN_MASK; - } -} - -/*! - * @brief Get the enabled status of the RTC wake-up timer (1KHZ). - * - - * @param base RTC peripheral base address - * - * @return The enabled status of RTC wake-up timer (1KHZ). - */ -static inline uint32_t RTC_GetEnabledWakeupTimer(RTC_Type *base) -{ - return (base->CTRL & RTC_CTRL_RTC1KHZ_EN_MASK); -} - -/*! @}*/ - -/*! - * @brief Set the RTC seconds timer (1HZ) MATCH value. - * - * @param base RTC peripheral base address - * @param matchValue The value to be set into the RTC MATCH register - */ -static inline void RTC_SetSecondsTimerMatch(RTC_Type *base, uint32_t matchValue) -{ - /* Set the start match value into the default RTC seconds timer (1HZ). */ - base->MATCH = matchValue; -} - -/*! - * @brief Read actual RTC seconds timer (1HZ) MATCH value. - * - * @param base RTC peripheral base address - * - * @return The actual RTC seconds timer (1HZ) MATCH value. - */ -static inline uint32_t RTC_GetSecondsTimerMatch(RTC_Type *base) -{ - /* Read the RTC default seconds timer (1HZ) MATCH value. */ - return base->MATCH; -} - -/*! - * @brief Set the RTC seconds timer (1HZ) COUNT value. - * - * @param base RTC peripheral base address - * @param countValue The value to be loaded into the RTC COUNT register - */ -static inline void RTC_SetSecondsTimerCount(RTC_Type *base, uint32_t countValue) -{ - /* Set the start count value into the default RTC seconds timer (1HZ). */ - base->COUNT = countValue; -} - -/*! - * @brief Read the actual RTC seconds timer (1HZ) COUNT value. - * - * @param base RTC peripheral base address - * - * @return The actual RTC seconds timer (1HZ) COUNT value. - */ -static inline uint32_t RTC_GetSecondsTimerCount(RTC_Type *base) -{ - uint32_t a, b; - - /* Follow the RF document to read the RTC default seconds timer (1HZ) counter value. */ - do - { - a = base->COUNT; - b = base->COUNT; - } while (a != b); - - return b; -} - -/*! - * @brief Enable the RTC wake-up timer (1KHZ) and set countdown value to the RTC WAKE register. - * - * @param base RTC peripheral base address - * @param wakeupValue The value to be loaded into the WAKE register in RTC wake-up timer (1KHZ). - */ -static inline void RTC_SetWakeupCount(RTC_Type *base, uint16_t wakeupValue) -{ - /* Use the RTC wake-up timer (1KHZ) */ - base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK; - - /* Set the start countdown value into the RTC WAKE register */ - base->WAKE = RTC_WAKE_VAL((uint32_t)wakeupValue); -} - -/*! - * @brief Read the actual value from the WAKE register value in RTC wake-up timer (1KHZ). - * - * @param base RTC peripheral base address - * - * @return The actual value of the WAKE register value in RTC wake-up timer (1HZ). - */ -static inline uint16_t RTC_GetWakeupCount(RTC_Type *base) -{ - /* Read current wake-up countdown value */ - return (uint16_t)((base->WAKE & RTC_WAKE_VAL_MASK) >> RTC_WAKE_VAL_SHIFT); -} - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enable the wake-up timer interrupt from deep power down mode. - * - * @param base RTC peripheral base address - * @param enable Enable/Disable wake-up timer interrupt from deep power down mode. - * - true: Enable wake-up timer interrupt from deep power down mode. - * - false: Disable wake-up timer interrupt from deep power down mode. - */ -static inline void RTC_EnableWakeUpTimerInterruptFromDPD(RTC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= RTC_CTRL_WAKEDPD_EN_MASK; - } - else - { - base->CTRL &= ~RTC_CTRL_WAKEDPD_EN_MASK; - } -} - -/*! - * @brief Enable the alarm timer interrupt from deep power down mode. - * - * @param base RTC peripheral base address - * @param enable Enable/Disable alarm timer interrupt from deep power down mode. - * - true: Enable alarm timer interrupt from deep power down mode. - * - false: Disable alarm timer interrupt from deep power down mode. - */ -static inline void RTC_EnableAlarmTimerInterruptFromDPD(RTC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= RTC_CTRL_ALARMDPD_EN_MASK; - } - else - { - base->CTRL &= ~RTC_CTRL_ALARMDPD_EN_MASK; - } -} - -/*! - * @brief Enables the selected RTC interrupts. - * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableAlarmTimerInterruptFromDPD - * and RTC_EnableWakeUpTimerInterruptFromDPD - * - * @param base RTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) -{ - uint32_t reg = base->CTRL; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK); - reg |= mask; - - base->CTRL = reg; -} - -/*! - * @brief Disables the selected RTC interrupts. - * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableAlarmTimerInterruptFromDPD - * and RTC_EnableWakeUpTimerInterruptFromDPD - * - * @param base RTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) -{ - uint32_t reg = base->CTRL; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK | mask); - - base->CTRL = reg; -} - -/*! - * @brief Get the enabled RTC interrupts. - * @deprecated Do not use this function. It will be deleted in next release version. - * - * @param base RTC peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) -{ - return (base->CTRL & (RTC_CTRL_ALARMDPD_EN_MASK | RTC_CTRL_WAKEDPD_EN_MASK)); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Get the RTC status flags - * - * @param base RTC peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::rtc_status_flags_t - */ -static inline uint32_t RTC_GetStatusFlags(RTC_Type *base) -{ - return (base->CTRL & (RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK)); -} - -/*! - * @brief Clear the RTC status flags. - * - * @param base RTC peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::rtc_status_flags_t - */ -static inline void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) -{ - uint32_t reg = base->CTRL; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK); - - /* Write 1 to the flags we wish to clear */ - reg |= mask; - - base->CTRL = reg; -} - -/*! @}*/ - -/*! - * @name Timer Enable - * @{ - */ - -/*! - * @brief Enable the RTC timer counter. - * - * After calling this function, the RTC inner counter increments once a second when only using the RTC seconds timer - * (1hz), while the RTC inner wake-up timer countdown once a millisecond when using RTC wake-up timer (1KHZ) at the - * same time. RTC timer contain two timers, one is the RTC normal seconds timer, the other one is the RTC wake-up timer, - * the RTC enable bit is the master switch for the whole RTC timer, so user can use the RTC seconds (1HZ) timer - * independly, but they can't use the RTC wake-up timer (1KHZ) independently. - * - * @param base RTC peripheral base address - * @param enable Enable/Disable RTC Timer counter. - * - true: Enable RTC Timer counter. - * - false: Disable RTC Timer counter. - */ -static inline void RTC_EnableTimer(RTC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= RTC_CTRL_RTC_EN_MASK; - } - else - { - base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; - } -} - -/*! - * @brief Starts the RTC time counter. - * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableTimer - * - * After calling this function, the timer counter increments once a second provided SR[TOF] or - * SR[TIF] are not set. - * - * @param base RTC peripheral base address - */ -static inline void RTC_StartTimer(RTC_Type *base) -{ - base->CTRL |= RTC_CTRL_RTC_EN_MASK; -} - -/*! - * @brief Stops the RTC time counter. - * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableTimer - * - * RTC's seconds register can be written to only when the timer is stopped. - * - * @param base RTC peripheral base address - */ -static inline void RTC_StopTimer(RTC_Type *base) -{ - base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; -} - -/*! @}*/ - -/*! - * @brief Perform a software reset on the RTC module. - * - * This resets all RTC registers to their reset value. The bit is cleared by software explicitly clearing it. - * - * @param base RTC peripheral base address - */ -static inline void RTC_Reset(RTC_Type *base) -{ - base->CTRL |= RTC_CTRL_SWRESET_MASK; - base->CTRL &= ~RTC_CTRL_SWRESET_MASK; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_RTC_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_sctimer.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_sctimer.c deleted file mode 100644 index 4208097a8b9..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_sctimer.c +++ /dev/null @@ -1,791 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sctimer.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.sctimer" -#endif - -/*! @brief Typedef for interrupt handler. */ -typedef void (*sctimer_isr_t)(SCT_Type *base); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base SCTimer peripheral base address - * - * @return The SCTimer instance - */ -static uint32_t SCTIMER_GetInstance(SCT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to SCT bases for each instance. */ -static SCT_Type *const s_sctBases[] = SCT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to SCT clocks for each instance. */ -static const clock_ip_name_t s_sctClocks[] = SCT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET -/*! @brief Pointers to SCT resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_sctResets[] = SCT_RSTS_N; -#else -/*! @brief Pointers to SCT resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_sctResets[] = SCT_RSTS; -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/*!< @brief SCTimer event Callback function. */ -static sctimer_event_callback_t s_eventCallback[FSL_FEATURE_SCT_NUMBER_OF_EVENTS]; - -/*!< @brief Keep track of SCTimer event number */ -static uint32_t s_currentEvent; - -/*!< @brief Keep track of SCTimer state number */ -static uint32_t s_currentState; - -/*!< @brief Keep track of SCTimer unify 32-bit or low 16-bit match/capture register number. */ -static uint32_t s_currentMatch; -/*!< @brief Keep track of SCTimer high 16-bit match/capture register number. */ -static uint32_t s_currentMatchhigh; - -/*! @brief Pointer to SCTimer IRQ handler */ -static sctimer_isr_t s_sctimerIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t SCTIMER_GetInstance(SCT_Type *base) -{ - uint32_t instance; - uint32_t sctArrayCount = (sizeof(s_sctBases) / sizeof(s_sctBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < sctArrayCount; instance++) - { - if (s_sctBases[instance] == base) - { - break; - } - } - - assert(instance < sctArrayCount); - - return instance; -} - -/*! - * brief Ungates the SCTimer clock and configures the peripheral for basic operation. - * - * note This API should be called at the beginning of the application using the SCTimer driver. - * - * param base SCTimer peripheral base address - * param config Pointer to the user configuration structure. - * - * return kStatus_Success indicates success; Else indicates failure. - */ -status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config) -{ - assert(NULL != config); - - uint32_t i; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the SCTimer clock*/ - CLOCK_EnableClock(s_sctClocks[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_sctResets[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - - /* Setup the counter operation. For Current Driver interface SCTIMER_Init don't know detail - * frequency of input clock, but User know it. So the INSYNC have to set by user level. */ - base->CONFIG = SCT_CONFIG_CKSEL(config->clockSelect) | SCT_CONFIG_CLKMODE(config->clockMode) | - SCT_CONFIG_UNIFY(config->enableCounterUnify) | SCT_CONFIG_INSYNC(config->inputsync); - - /* Write to the control register, keep the counters halted. */ - base->CTRL = - SCT_CTRL_BIDIR_L(config->enableBidirection_l) | SCT_CTRL_PRE_L(config->prescale_l) | SCT_CTRL_HALT_L_MASK; - /* Clear the counter after changing the PRE value. */ - base->CTRL |= SCT_CTRL_CLRCTR_L_MASK; - - if (!(config->enableCounterUnify)) - { - base->CTRL |= - SCT_CTRL_BIDIR_H(config->enableBidirection_h) | SCT_CTRL_PRE_H(config->prescale_h) | SCT_CTRL_HALT_H_MASK; - base->CTRL |= SCT_CTRL_CLRCTR_H_MASK; - } - - /* Initial state of channel output */ - base->OUTPUT = config->outInitState; - - /* Clear the global variables */ - s_currentEvent = 0U; - s_currentState = 0U; - s_currentMatch = 0U; - s_currentMatchhigh = 0U; - - /* Clear the callback array */ - for (i = 0; i < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) - { - s_eventCallback[i] = NULL; - } - - /* Save interrupt handler */ - s_sctimerIsr = SCTIMER_EventHandleIRQ; - - return kStatus_Success; -} - -/*! - * brief Gates the SCTimer clock. - * - * param base SCTimer peripheral base address - */ -void SCTIMER_Deinit(SCT_Type *base) -{ - /* Halt the counters */ - base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the SCTimer clock*/ - CLOCK_DisableClock(s_sctClocks[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Fills in the SCTimer configuration structure with the default settings. - * - * The default values are: - * code - * config->enableCounterUnify = true; - * config->clockMode = kSCTIMER_System_ClockMode; - * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - * config->enableBidirection_l = false; - * config->enableBidirection_h = false; - * config->prescale_l = 0U; - * config->prescale_h = 0U; - * config->outInitState = 0U; - * config->inputsync = 0xFU; - * endcode - * param config Pointer to the user configuration structure. - */ -void SCTIMER_GetDefaultConfig(sctimer_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* SCT operates as a unified 32-bit counter */ - config->enableCounterUnify = true; - /* System clock clocks the entire SCT module */ - config->clockMode = kSCTIMER_System_ClockMode; - /* This is used only by certain clock modes */ - config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - /* Up count mode only for the unified counter */ - config->enableBidirection_l = false; - /* Up count mode only for Counte_H */ - config->enableBidirection_h = false; - /* Prescale factor of 1 */ - config->prescale_l = 0U; - /* Prescale factor of 1 for Counter_H*/ - config->prescale_h = 0U; - /* Clear outputs */ - config->outInitState = 0U; - /* Default value is 0xFU, it can be clear as 0 when speical conditions met. - * Condition can be clear as 0: (for all Clock Modes): - * (1) The corresponding input is already synchronous to the SCTimer/PWM clock. - * (2) The SCTimer/PWM clock frequency does not exceed 100 MHz. - * Note: The SCTimer/PWM clock is the bus/system clock for CKMODE 0-2 or asynchronous input - * clock for CKMODE3. - * Another condition can be clear as 0: (for CKMODE2 only) - * (1) The corresponding input is synchronous to the designated CKMODE2 input clock. - * (2) The CKMODE2 input clock frequency is less than one-third the frequency of the bus/system clock. - * Default value set as 0U, input0~input3 are set as bypasses. */ - config->inputsync = 0xFU; -} - -/*! - * brief Configures the PWM signal parameters. - * - * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This - * function will create 2 events; one of the events will trigger on match with the pulse value - * and the other will trigger when the counter matches the PWM period. The PWM period event is - * also used as a limit event to reset the counter or change direction. Both events are enabled - * for the same state. The state number can be retrieved by calling the function - * SCTIMER_GetCurrentStateNumber(). - * The counter is set to operate as one 32-bit counter (unify bit is set to 1). - * The counter operates in bi-directional mode when generating a center-aligned PWM. - * - * note When setting PWM output from multiple output pins, they all should use the same PWM mode - * i.e all PWM's should be either edge-aligned or center-aligned. - * When using this API, the PWM signal frequency of all the initialized channels must be the same. - * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the - * API's pwmFreq_Hz. - * - * param base SCTimer peripheral base address - * param pwmParams PWM parameters to configure the output - * param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t - * param pwmFreq_Hz PWM signal frequency in Hz - * param srcClock_Hz SCTimer counter clock in Hz - * param event Pointer to a variable where the PWM period event number is stored - * - * return kStatus_Success on success - * kStatus_Fail If we have hit the limit in terms of number of events created or if - * an incorrect PWM dutycylce is passed in. - */ -status_t SCTIMER_SetupPwm(SCT_Type *base, - const sctimer_pwm_signal_param_t *pwmParams, - sctimer_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - uint32_t *event) -{ - assert(NULL != pwmParams); - assert(0U != srcClock_Hz); - assert(0U != pwmFreq_Hz); - assert((uint32_t)pwmParams->output < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - - /* If we do not have enough events available (this function will create two events), - * the function will return fail. - */ - status_t status = kStatus_Fail; - status_t status2; - uint32_t period, pulsePeriod = 0; - uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1U); - uint32_t periodEvent = 0, pulseEvent = 0; - uint32_t reg; - - if ((s_currentEvent + 2U) <= (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS) - { - /* Use bi-directional mode for center-aligned PWM */ - if (mode == kSCTIMER_CenterAlignedPwm) - { - base->CTRL |= SCT_CTRL_BIDIR_L_MASK; - } - - /* Calculate PWM period match value */ - if (mode == kSCTIMER_EdgeAlignedPwm) - { - period = (sctClock / pwmFreq_Hz) - 1U; - } - else - { - period = sctClock / (pwmFreq_Hz * 2U); - } - - /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ - if (pwmParams->dutyCyclePercent >= 100U) - { - pulsePeriod = period + 2U; - } - else - { - pulsePeriod = (uint32_t)(((uint64_t)period * pwmParams->dutyCyclePercent) / 100U); - } - - /* Schedule an event when we reach the PWM period */ - status = - SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, period, 0, kSCTIMER_Counter_U, &periodEvent); - - /* Schedule an event when we reach the pulse width */ - status2 = SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, pulsePeriod, 0, kSCTIMER_Counter_U, - &pulseEvent); - - if ((kStatus_Success == status) && (kStatus_Success == status2)) - { - /* Reset the counter when we reach the PWM period */ - SCTIMER_SetupCounterLimitAction(base, kSCTIMER_Counter_U, periodEvent); - - /* Return the period event to the user */ - *event = periodEvent; - - /* For high-true level */ - if ((uint32_t)pwmParams->level == (uint32_t)kSCTIMER_HighTrue) - { - if (mode == kSCTIMER_EdgeAlignedPwm) - { - /* Set the initial output level to low which is the inactive state */ - base->OUTPUT &= ~(1UL << (uint32_t)pwmParams->output); - /* Set the output when we reach the PWM period */ - SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, periodEvent); - /* Clear the output when we reach the PWM pulse value */ - SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, pulseEvent); - } - else - { - /* Set the initial output level to high which is the inactive state */ - base->OUTPUT |= (1UL << (uint32_t)pwmParams->output); - /* Clear the output when we reach the PWM pulse event */ - SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, pulseEvent); - /* Reverse output when down counting */ - reg = base->OUTPUTDIRCTRL; - reg &= ~((uint32_t)SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2U * (uint32_t)pwmParams->output)); - reg |= (1UL << (2U * (uint32_t)pwmParams->output)); - base->OUTPUTDIRCTRL = reg; - } - } - /* For low-true level */ - else - { - if (mode == kSCTIMER_EdgeAlignedPwm) - { - /* Set the initial output level to high which is the inactive state */ - base->OUTPUT |= (1UL << (uint32_t)pwmParams->output); - /* Clear the output when we reach the PWM period */ - SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, periodEvent); - /* Set the output when we reach the PWM pulse value */ - SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, pulseEvent); - } - else - { - /* Set the initial output level to low which is the inactive state */ - base->OUTPUT &= ~(1UL << (uint32_t)pwmParams->output); - /* Set the output when we reach the PWM pulse event */ - SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, pulseEvent); - /* Reverse output when down counting */ - reg = base->OUTPUTDIRCTRL; - reg &= ~((uint32_t)SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2U * (uint32_t)pwmParams->output)); - reg |= (1UL << (2U * (uint32_t)pwmParams->output)); - base->OUTPUTDIRCTRL = reg; - } - } - } - else - { - status = kStatus_Fail; - } - } - - return status; -} - -/*! - * brief Updates the duty cycle of an active PWM signal. - * - * Before calling this function, the counter is set to operate as one 32-bit counter (unify bit is set to 1). - * - * param base SCTimer peripheral base address - * param output The output to configure - * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 - * param event Event number associated with this PWM signal. This was returned to the user by the - * function SCTIMER_SetupPwm(). - */ -void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event) - -{ - assert(dutyCyclePercent <= 100U); - assert((uint32_t)output < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - - uint32_t periodMatchReg, pulseMatchReg; - uint32_t pulsePeriod = 0, period; - - /* Retrieve the match register number for the PWM period */ - periodMatchReg = base->EV[event].CTRL & SCT_EV_CTRL_MATCHSEL_MASK; - - /* Retrieve the match register number for the PWM pulse period */ - pulseMatchReg = base->EV[event + 1U].CTRL & SCT_EV_CTRL_MATCHSEL_MASK; - - period = base->MATCH[periodMatchReg]; - - /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ - if (dutyCyclePercent >= 100U) - { - pulsePeriod = period + 2U; - } - else - { - pulsePeriod = (uint32_t)(((uint64_t)period * dutyCyclePercent) / 100U); - } - - /* Stop the counter before updating match register */ - SCTIMER_StopTimer(base, (uint32_t)kSCTIMER_Counter_U); - - /* Update dutycycle */ - base->MATCH[pulseMatchReg] = SCT_MATCH_MATCHn_L(pulsePeriod); - base->MATCHREL[pulseMatchReg] = SCT_MATCHREL_RELOADn_L(pulsePeriod); - - /* Restart the counter */ - SCTIMER_StartTimer(base, (uint32_t)kSCTIMER_Counter_U); -} - -/*! - * brief Create an event that is triggered on a match or IO and schedule in current state. - * - * This function will configure an event using the options provided by the user. If the event type uses - * the counter match, then the function will set the user provided match value into a match register - * and put this match register number into the event control register. - * The event is enabled for the current state and the event number is increased by one at the end. - * The function returns the event number; this event number can be used to configure actions to be - * done when this event is triggered. - * - * param base SCTimer peripheral base address - * param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t - * param matchValue The match value that will be programmed to a match register - * param whichIO The input or output that will be involved in event triggering. This field - * is ignored if the event type is "match only" - * param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * param event Pointer to a variable where the new event number is stored - * - * return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of events created or - if we have reached the limit in terms of number of match registers - */ -status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, - sctimer_event_t howToMonitor, - uint32_t matchValue, - uint32_t whichIO, - sctimer_counter_t whichCounter, - uint32_t *event) -{ - uint32_t combMode = (((uint32_t)howToMonitor & SCT_EV_CTRL_COMBMODE_MASK) >> SCT_EV_CTRL_COMBMODE_SHIFT); - uint32_t currentCtrlVal = (uint32_t)howToMonitor; - status_t status = kStatus_Success; - uint32_t temp = 0; - - if (s_currentEvent < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS) - { - if (2U == combMode) - { - base->EV[s_currentEvent].CTRL = currentCtrlVal | SCT_EV_CTRL_IOSEL(whichIO); - } - else - { - if ((0U == combMode) || (3U == combMode)) - { - currentCtrlVal |= SCT_EV_CTRL_IOSEL(whichIO); - } - - if ((kSCTIMER_Counter_L == whichCounter) && (0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) - { - if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatch); - - /* Use Counter_L bits if user wants to setup the Low counter */ - base->MATCH_ACCESS16BIT[s_currentMatch].MATCHL = (uint16_t)matchValue; - base->MATCHREL_ACCESS16BIT[s_currentMatch].MATCHRELL = (uint16_t)matchValue; - base->EV[s_currentEvent].CTRL = currentCtrlVal; - - /* Increment the match register number */ - s_currentMatch++; - } - else - { - /* An error would occur if we have hit the limit in terms of number of match registers */ - status = kStatus_Fail; - } - } - else if ((kSCTIMER_Counter_H == whichCounter) && (0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) - { - if (s_currentMatchhigh < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatchhigh); - - /* Use Counter_H bits if user wants to setup the High counter */ - currentCtrlVal |= SCT_EV_CTRL_HEVENT(1U); - temp = base->MATCH_ACCESS16BIT[s_currentMatchhigh].MATCHL; - base->MATCH[s_currentMatchhigh] = temp | (matchValue << 16U); - temp = base->MATCHREL_ACCESS16BIT[s_currentMatchhigh].MATCHRELL; - base->MATCHREL[s_currentMatchhigh] = temp | (matchValue << 16U); - - base->EV[s_currentEvent].CTRL = currentCtrlVal; - /* Increment the match register number */ - s_currentMatchhigh++; - } - else - { - /* An error would occur if we have hit the limit in terms of number of match registers */ - status = kStatus_Fail; - } - } - else if ((kSCTIMER_Counter_U == whichCounter) && (0U != (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) - { - if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - /* Use Counter_L bits if counter is operating in 32-bit mode */ - currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatch); - - base->MATCH[s_currentMatch] = matchValue; - base->MATCHREL[s_currentMatch] = matchValue; - base->EV[s_currentEvent].CTRL = currentCtrlVal; - - /* Increment the match register number */ - s_currentMatch++; - } - else - { - /* An error would occur if we have hit the limit in terms of number of match registers */ - status = kStatus_Fail; - } - } - else - { - /* The used counter must match the CONFIG[UNIFY] bit selection */ - status = kStatus_Fail; - } - } - - if (kStatus_Success == status) - { - /* Enable the event in the current state */ - base->EV[s_currentEvent].STATE = (1UL << s_currentState); - - /* Return the event number */ - *event = s_currentEvent; - - /* Increment the event number */ - s_currentEvent++; - } - } - else - { - /* An error would occur if we have hit the limit in terms of number of events created */ - status = kStatus_Fail; - } - - return status; -} - -/*! - * brief Enable an event in the current state. - * - * This function will allow the event passed in to trigger in the current state. The event must - * be created earlier by either calling the function SCTIMER_SetupPwm() or function - * SCTIMER_CreateAndScheduleEvent() . - * - * param base SCTimer peripheral base address - * param event Event number to enable in the current state - * - */ -void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event) -{ - /* Enable event in the current state */ - base->EV[event].STATE |= (1UL << s_currentState); -} - -/*! - * brief Increase the state by 1 - * - * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new - * state. - * - * param base SCTimer peripheral base address - * - * return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of states used - - */ -status_t SCTIMER_IncreaseState(SCT_Type *base) -{ - status_t status = kStatus_Success; - - /* Return an error if we have hit the limit in terms of states used */ - if (s_currentState >= (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES) - { - status = kStatus_Fail; - } - else - { - s_currentState++; - } - - return status; -} - -/*! - * brief Provides the current state - * - * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). - * - * param base SCTimer peripheral base address - * - * return The current state - */ -uint32_t SCTIMER_GetCurrentState(SCT_Type *base) -{ - return s_currentState; -} - -/*! - * brief Toggle the output level. - * - * This change in the output level is triggered by the event number that is passed in by the user. - * - * param base SCTimer peripheral base address - * param whichIO The output to toggle - * param event Event number that will trigger the output change - */ -void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - uint32_t reg; - - /* Set the same event to set and clear the output */ - base->OUT[whichIO].CLR |= (1UL << event); - base->OUT[whichIO].SET |= (1UL << event); - - /* Set the conflict resolution to toggle output */ - reg = base->RES; - reg &= ~(((uint32_t)SCT_RES_O0RES_MASK) << (2U * whichIO)); - reg |= ((uint32_t)(kSCTIMER_ResolveToggle)) << (2U * whichIO); - base->RES = reg; -} - -/*! - * brief Setup capture of the counter value on trigger of a selected event - * - * param base SCTimer peripheral base address - * param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * param captureRegister Pointer to a variable where the capture register number will be returned. User - * can read the captured value from this register when the specified event is triggered. - * param event Event number that will trigger the capture - * - * return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of match/capture registers available - */ -status_t SCTIMER_SetupCaptureAction(SCT_Type *base, - sctimer_counter_t whichCounter, - uint32_t *captureRegister, - uint32_t event) -{ - status_t status; - uint32_t temp = 0; - - if ((kSCTIMER_Counter_L == whichCounter) || (kSCTIMER_Counter_U == whichCounter)) - { - if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - /* Set the bit to enable event */ - base->CAPCTRL_ACCESS16BIT[s_currentMatch].CAPCTRLL |= SCT_CAPCTRLL_CAPCTRLL(1UL << event); - - /* Set this resource to be a capture rather than match */ - base->REGMODE_ACCESS16BIT.REGMODEL |= SCT_REGMODEL_REGMODEL(1UL << s_currentMatch); - - /* Return the match register number */ - *captureRegister = s_currentMatch; - - /* Increase the match register number */ - s_currentMatch++; - - status = kStatus_Success; - } - else - { - /* Return an error if we have hit the limit in terms of number of capture/match registers used */ - status = kStatus_Fail; - } - } - else - { - if (s_currentMatchhigh < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - /* Set bit to enable event */ - temp = base->CAPCTRL_ACCESS16BIT[s_currentMatchhigh].CAPCTRLL; - base->CAPCTRL[s_currentMatchhigh] = temp | ((uint32_t)((uint32_t)(1UL << event) << 16U) & 0xFFFF000U); - /* Set this resource to be a capture rather than match */ - temp = base->REGMODE_ACCESS16BIT.REGMODEL; - base->REGMODE = temp | ((uint32_t)((uint32_t)(1UL << s_currentMatchhigh) << 16U) & 0xFFFF000U); - - /* Return the match register number */ - *captureRegister = s_currentMatchhigh; - - /* Increase the match register number */ - s_currentMatchhigh++; - - status = kStatus_Success; - } - else - { - /* Return an error if we have hit the limit in terms of number of capture/match registers used */ - status = kStatus_Fail; - } - } - - return status; -} - -/*! - * brief Receive noticification when the event trigger an interrupt. - * - * If the interrupt for the event is enabled by the user, then a callback can be registered - * which will be invoked when the event is triggered - * - * param base SCTimer peripheral base address - * param event Event number that will trigger the interrupt - * param callback Function to invoke when the event is triggered - */ - -void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event) -{ - s_eventCallback[event] = callback; -} - -/*! - * brief SCTimer interrupt handler. - * - * param base SCTimer peripheral base address. - */ -void SCTIMER_EventHandleIRQ(SCT_Type *base) -{ - uint32_t eventFlag = SCT0->EVFLAG; - /* Only clear the flags whose interrupt field is enabled */ - uint32_t clearFlag = (eventFlag & SCT0->EVEN); - uint32_t mask = eventFlag; - uint32_t i; - - /* Invoke the callback for certain events */ - for (i = 0; i < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) - { - if ((mask & 0x1U) != 0U) - { - if (s_eventCallback[i] != NULL) - { - s_eventCallback[i](); - } - } - mask >>= 1UL; - - if (0U == mask) - { - /* All events have been handled. */ - break; - } - } - - /* Clear event interrupt flag */ - SCT0->EVFLAG = clearFlag; -} - -void SCT0_DriverIRQHandler(void); -void SCT0_DriverIRQHandler(void) -{ - s_sctimerIsr(SCT0); - SDK_ISR_EXIT_BARRIER; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_sctimer.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_sctimer.h deleted file mode 100644 index 283a5b7019f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_sctimer.h +++ /dev/null @@ -1,1258 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SCTIMER_H_ -#define _FSL_SCTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup sctimer - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 4, 4)) /*!< Version */ -/*@}*/ - -#ifndef SCT_EV_STATE_STATEMSKn -#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(x) & (1UL << FSL_FEATURE_SCT_NUMBER_OF_STATES) - 1UL)) -#endif - -/*! @brief SCTimer PWM operation modes */ -typedef enum _sctimer_pwm_mode -{ - kSCTIMER_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */ - kSCTIMER_CenterAlignedPwm /*!< Center-aligned PWM */ -} sctimer_pwm_mode_t; - -/*! @brief SCTimer counters type. */ -typedef enum _sctimer_counter -{ - kSCTIMER_Counter_L = (1U << 0), /*!< 16-bit Low counter. */ - kSCTIMER_Counter_H = (1U << 1), /*!< 16-bit High counter. */ - kSCTIMER_Counter_U = (1U << 2), /*!< 32-bit Unified counter. */ -} sctimer_counter_t; - -/*! @brief List of SCTimer input pins */ -typedef enum _sctimer_input -{ - kSCTIMER_Input_0 = 0U, /*!< SCTIMER input 0 */ - kSCTIMER_Input_1, /*!< SCTIMER input 1 */ - kSCTIMER_Input_2, /*!< SCTIMER input 2 */ - kSCTIMER_Input_3, /*!< SCTIMER input 3 */ - kSCTIMER_Input_4, /*!< SCTIMER input 4 */ - kSCTIMER_Input_5, /*!< SCTIMER input 5 */ - kSCTIMER_Input_6, /*!< SCTIMER input 6 */ - kSCTIMER_Input_7 /*!< SCTIMER input 7 */ -} sctimer_input_t; - -/*! @brief List of SCTimer output pins */ -typedef enum _sctimer_out -{ - kSCTIMER_Out_0 = 0U, /*!< SCTIMER output 0*/ - kSCTIMER_Out_1, /*!< SCTIMER output 1 */ - kSCTIMER_Out_2, /*!< SCTIMER output 2 */ - kSCTIMER_Out_3, /*!< SCTIMER output 3 */ - kSCTIMER_Out_4, /*!< SCTIMER output 4 */ - kSCTIMER_Out_5, /*!< SCTIMER output 5 */ - kSCTIMER_Out_6, /*!< SCTIMER output 6 */ - kSCTIMER_Out_7, /*!< SCTIMER output 7 */ - kSCTIMER_Out_8, /*!< SCTIMER output 8 */ - kSCTIMER_Out_9 /*!< SCTIMER output 9 */ -} sctimer_out_t; - -/*! @brief SCTimer PWM output pulse mode: high-true, low-true or no output */ -typedef enum _sctimer_pwm_level_select -{ - kSCTIMER_LowTrue = 0U, /*!< Low true pulses */ - kSCTIMER_HighTrue /*!< High true pulses */ -} sctimer_pwm_level_select_t; - -/*! @brief Options to configure a SCTimer PWM signal */ -typedef struct _sctimer_pwm_signal_param -{ - sctimer_out_t output; /*!< The output pin to use to generate the PWM signal */ - sctimer_pwm_level_select_t level; /*!< PWM output active level select. */ - uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 - 0 = always inactive signal (0% duty cycle) - 100 = always active signal (100% duty cycle).*/ -} sctimer_pwm_signal_param_t; - -/*! @brief SCTimer clock mode options */ -typedef enum _sctimer_clock_mode -{ - kSCTIMER_System_ClockMode = 0U, /*!< System Clock Mode */ - kSCTIMER_Sampled_ClockMode, /*!< Sampled System Clock Mode */ - kSCTIMER_Input_ClockMode, /*!< SCT Input Clock Mode */ - kSCTIMER_Asynchronous_ClockMode /*!< Asynchronous Mode */ -} sctimer_clock_mode_t; - -/*! @brief SCTimer clock select options */ -typedef enum _sctimer_clock_select -{ - kSCTIMER_Clock_On_Rise_Input_0 = 0U, /*!< Rising edges on input 0 */ - kSCTIMER_Clock_On_Fall_Input_0, /*!< Falling edges on input 0 */ - kSCTIMER_Clock_On_Rise_Input_1, /*!< Rising edges on input 1 */ - kSCTIMER_Clock_On_Fall_Input_1, /*!< Falling edges on input 1 */ - kSCTIMER_Clock_On_Rise_Input_2, /*!< Rising edges on input 2 */ - kSCTIMER_Clock_On_Fall_Input_2, /*!< Falling edges on input 2 */ - kSCTIMER_Clock_On_Rise_Input_3, /*!< Rising edges on input 3 */ - kSCTIMER_Clock_On_Fall_Input_3, /*!< Falling edges on input 3 */ - kSCTIMER_Clock_On_Rise_Input_4, /*!< Rising edges on input 4 */ - kSCTIMER_Clock_On_Fall_Input_4, /*!< Falling edges on input 4 */ - kSCTIMER_Clock_On_Rise_Input_5, /*!< Rising edges on input 5 */ - kSCTIMER_Clock_On_Fall_Input_5, /*!< Falling edges on input 5 */ - kSCTIMER_Clock_On_Rise_Input_6, /*!< Rising edges on input 6 */ - kSCTIMER_Clock_On_Fall_Input_6, /*!< Falling edges on input 6 */ - kSCTIMER_Clock_On_Rise_Input_7, /*!< Rising edges on input 7 */ - kSCTIMER_Clock_On_Fall_Input_7 /*!< Falling edges on input 7 */ -} sctimer_clock_select_t; - -/*! - * @brief SCTimer output conflict resolution options. - * - * Specifies what action should be taken if multiple events dictate that a given output should be - * both set and cleared at the same time - */ -typedef enum _sctimer_conflict_resolution -{ - kSCTIMER_ResolveNone = 0U, /*!< No change */ - kSCTIMER_ResolveSet, /*!< Set output */ - kSCTIMER_ResolveClear, /*!< Clear output */ - kSCTIMER_ResolveToggle /*!< Toggle output */ -} sctimer_conflict_resolution_t; - -/*! @brief List of SCTimer event generation active direction when the counters are operating in BIDIR mode. */ -typedef enum _sctimer_event_active_direction -{ - kSCTIMER_ActiveIndependent = 0U, /*!< This event is triggered regardless of the count direction. */ - kSCTIMER_ActiveInCountUp, /*!< This event is triggered only during up-counting when BIDIR = 1. */ - kSCTIMER_ActiveInCountDown /*!< This event is triggered only during down-counting when BIDIR = 1. */ -} sctimer_event_active_direction_t; - -/*! @brief List of SCTimer event types */ -typedef enum _sctimer_event -{ - kSCTIMER_InputLowOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_MatchEventOnly = - (1 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_InputLowEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_InputLowAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT) -} sctimer_event_t; - -/*! @brief SCTimer callback typedef. */ -typedef void (*sctimer_event_callback_t)(void); - -/*! @brief List of SCTimer interrupts */ -typedef enum _sctimer_interrupt_enable -{ - kSCTIMER_Event0InterruptEnable = (1U << 0), /*!< Event 0 interrupt */ - kSCTIMER_Event1InterruptEnable = (1U << 1), /*!< Event 1 interrupt */ - kSCTIMER_Event2InterruptEnable = (1U << 2), /*!< Event 2 interrupt */ - kSCTIMER_Event3InterruptEnable = (1U << 3), /*!< Event 3 interrupt */ - kSCTIMER_Event4InterruptEnable = (1U << 4), /*!< Event 4 interrupt */ - kSCTIMER_Event5InterruptEnable = (1U << 5), /*!< Event 5 interrupt */ - kSCTIMER_Event6InterruptEnable = (1U << 6), /*!< Event 6 interrupt */ - kSCTIMER_Event7InterruptEnable = (1U << 7), /*!< Event 7 interrupt */ - kSCTIMER_Event8InterruptEnable = (1U << 8), /*!< Event 8 interrupt */ - kSCTIMER_Event9InterruptEnable = (1U << 9), /*!< Event 9 interrupt */ - kSCTIMER_Event10InterruptEnable = (1U << 10), /*!< Event 10 interrupt */ - kSCTIMER_Event11InterruptEnable = (1U << 11), /*!< Event 11 interrupt */ - kSCTIMER_Event12InterruptEnable = (1U << 12), /*!< Event 12 interrupt */ -} sctimer_interrupt_enable_t; - -/*! @brief List of SCTimer flags */ -typedef enum _sctimer_status_flags -{ - kSCTIMER_Event0Flag = (1U << 0), /*!< Event 0 Flag */ - kSCTIMER_Event1Flag = (1U << 1), /*!< Event 1 Flag */ - kSCTIMER_Event2Flag = (1U << 2), /*!< Event 2 Flag */ - kSCTIMER_Event3Flag = (1U << 3), /*!< Event 3 Flag */ - kSCTIMER_Event4Flag = (1U << 4), /*!< Event 4 Flag */ - kSCTIMER_Event5Flag = (1U << 5), /*!< Event 5 Flag */ - kSCTIMER_Event6Flag = (1U << 6), /*!< Event 6 Flag */ - kSCTIMER_Event7Flag = (1U << 7), /*!< Event 7 Flag */ - kSCTIMER_Event8Flag = (1U << 8), /*!< Event 8 Flag */ - kSCTIMER_Event9Flag = (1U << 9), /*!< Event 9 Flag */ - kSCTIMER_Event10Flag = (1U << 10), /*!< Event 10 Flag */ - kSCTIMER_Event11Flag = (1U << 11), /*!< Event 11 Flag */ - kSCTIMER_Event12Flag = (1U << 12), /*!< Event 12 Flag */ - kSCTIMER_BusErrorLFlag = - (1U << SCT_CONFLAG_BUSERRL_SHIFT), /*!< Bus error due to write when L counter was not halted */ - kSCTIMER_BusErrorHFlag = - (int)(1U << SCT_CONFLAG_BUSERRH_SHIFT) /*!< Bus error due to write when H counter was not halted */ -} sctimer_status_flags_t; - -/*! - * @brief SCTimer configuration structure - * - * This structure holds the configuration settings for the SCTimer peripheral. To initialize this - * structure to reasonable defaults, call the SCTMR_GetDefaultConfig() function and pass a - * pointer to the configuration structure instance. - * - * The configuration structure can be made constant so as to reside in flash. - */ -typedef struct _sctimer_config -{ - bool enableCounterUnify; /*!< true: SCT operates as a unified 32-bit counter; - false: SCT operates as two 16-bit counters. - User can use the 16-bit low counter and the 16-bit high counters at the - same time; for Hardware limit, user can not use unified 32-bit counter - and any 16-bit low/high counter at the same time. */ - sctimer_clock_mode_t clockMode; /*!< SCT clock mode value */ - sctimer_clock_select_t clockSelect; /*!< SCT clock select value */ - bool enableBidirection_l; /*!< true: Up-down count mode for the L or unified counter - false: Up count mode only for the L or unified counter */ - bool enableBidirection_h; /*!< true: Up-down count mode for the H or unified counter - false: Up count mode only for the H or unified counter. - This field is used only if the enableCounterUnify is set - to false */ - uint8_t prescale_l; /*!< Prescale value to produce the L or unified counter clock */ - uint8_t prescale_h; /*!< Prescale value to produce the H counter clock. - This field is used only if the enableCounterUnify is set - to false */ - uint8_t outInitState; /*!< Defines the initial output value */ - uint8_t inputsync; /*!< SCT INSYNC value, INSYNC field in the CONFIG register, from bit9 to bit 16. - it is used to define synchronization for input N: - bit 9 = input 0 - bit 10 = input 1 - bit 11 = input 2 - bit 12 = input 3 - All other bits are reserved (bit13 ~bit 16). - How User to set the the value for the member inputsync. - IE: delay for input0, and input 1, bypasses for input 2 and input 3 - MACRO definition in user level. - \#define INPUTSYNC0 (0U) - \#define INPUTSYNC1 (1U) - \#define INPUTSYNC2 (2U) - \#define INPUTSYNC3 (3U) - User Code. - sctimerInfo.inputsync = (1 << INPUTSYNC2) | (1 << INPUTSYNC3); */ -} sctimer_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the SCTimer clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the SCTimer driver. - * - * @param base SCTimer peripheral base address - * @param config Pointer to the user configuration structure. - * - * @return kStatus_Success indicates success; Else indicates failure. - */ -status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config); - -/*! - * @brief Gates the SCTimer clock. - * - * @param base SCTimer peripheral base address - */ -void SCTIMER_Deinit(SCT_Type *base); - -/*! - * @brief Fills in the SCTimer configuration structure with the default settings. - * - * The default values are: - * @code - * config->enableCounterUnify = true; - * config->clockMode = kSCTIMER_System_ClockMode; - * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - * config->enableBidirection_l = false; - * config->enableBidirection_h = false; - * config->prescale_l = 0U; - * config->prescale_h = 0U; - * config->outInitState = 0U; - * config->inputsync = 0xFU; - * @endcode - * @param config Pointer to the user configuration structure. - */ -void SCTIMER_GetDefaultConfig(sctimer_config_t *config); - -/*! @}*/ - -/*! - * @name PWM setup operations - * @{ - */ - -/*! - * @brief Configures the PWM signal parameters. - * - * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This - * function will create 2 events; one of the events will trigger on match with the pulse value - * and the other will trigger when the counter matches the PWM period. The PWM period event is - * also used as a limit event to reset the counter or change direction. Both events are enabled - * for the same state. The state number can be retrieved by calling the function - * SCTIMER_GetCurrentStateNumber(). - * The counter is set to operate as one 32-bit counter (unify bit is set to 1). - * The counter operates in bi-directional mode when generating a center-aligned PWM. - * - * @note When setting PWM output from multiple output pins, they all should use the same PWM mode - * i.e all PWM's should be either edge-aligned or center-aligned. - * When using this API, the PWM signal frequency of all the initialized channels must be the same. - * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the - * API's pwmFreq_Hz. - * - * @param base SCTimer peripheral base address - * @param pwmParams PWM parameters to configure the output - * @param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz SCTimer counter clock in Hz - * @param event Pointer to a variable where the PWM period event number is stored - * - * @return kStatus_Success on success - * kStatus_Fail If we have hit the limit in terms of number of events created or if - * an incorrect PWM dutycylce is passed in. - */ -status_t SCTIMER_SetupPwm(SCT_Type *base, - const sctimer_pwm_signal_param_t *pwmParams, - sctimer_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - uint32_t *event); - -/*! - * @brief Updates the duty cycle of an active PWM signal. - * - * Before calling this function, the counter is set to operate as one 32-bit counter (unify bit is set to 1). - * - * @param base SCTimer peripheral base address - * @param output The output to configure - * @param dutyCyclePercent New PWM pulse width; the value should be between 1 to 100 - * @param event Event number associated with this PWM signal. This was returned to the user by the - * function SCTIMER_SetupPwm(). - */ -void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event); - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline void SCTIMER_EnableInterrupts(SCT_Type *base, uint32_t mask) -{ - base->EVEN |= mask; -} - -/*! - * @brief Disables the selected SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline void SCTIMER_DisableInterrupts(SCT_Type *base, uint32_t mask) -{ - base->EVEN &= ~mask; -} - -/*! - * @brief Gets the enabled SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline uint32_t SCTIMER_GetEnabledInterrupts(SCT_Type *base) -{ - return (base->EVEN & 0xFFFFU); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the SCTimer status flags. - * - * @param base SCTimer peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::sctimer_status_flags_t - */ -static inline uint32_t SCTIMER_GetStatusFlags(SCT_Type *base) -{ - uint32_t statusFlags = 0; - - /* Add the recorded events */ - statusFlags = (base->EVFLAG & 0xFFFFU); - - /* Add bus error flags */ - statusFlags |= (base->CONFLAG & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); - - return statusFlags; -} - -/*! - * @brief Clears the SCTimer status flags. - * - * @param base SCTimer peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::sctimer_status_flags_t - */ -static inline void SCTIMER_ClearStatusFlags(SCT_Type *base, uint32_t mask) -{ - /* Write to the flag registers */ - base->EVFLAG = (mask & 0xFFFFU); - base->CONFLAG = (mask & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); -} - -/*! @}*/ - -/*! - * @name Counter Start and Stop - * @{ - */ - -/*! - * @brief Starts the SCTimer counter. - * - * @note In 16-bit mode, we can enable both Counter_L and Counter_H, In 32-bit mode, we only can select Counter_U. - * - * @param base SCTimer peripheral base address - * @param countertoStart The SCTimer counters to enable. This is a logical OR of members of the - * enumeration ::sctimer_counter_t. - */ -static inline void SCTIMER_StartTimer(SCT_Type *base, uint32_t countertoStart) -{ - switch (countertoStart) - { - case (uint32_t)kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_L bit when user wants to start the Low counter */ - base->CTRL_ACCESS16BIT.CTRLL &= ~((uint16_t)SCT_CTRLL_HALT_L_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_H bit when user wants to start the High counter */ - base->CTRL_ACCESS16BIT.CTRLH &= ~((uint16_t)SCT_CTRLH_HALT_H_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_L | (uint32_t)kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_L/HALT_H bit when user wants to H counter and L counter at same time */ - base->CTRL &= ~(SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_L bit when the counter is operating in 32-bit mode (unify counter). */ - base->CTRL &= ~(SCT_CTRL_HALT_L_MASK); - break; - - default: - /* Counter_L/Counter_H can't work together with Counter_U. */ - assert(false); - break; - } -} - -/*! - * @brief Halts the SCTimer counter. - * - * @param base SCTimer peripheral base address - * @param countertoStop The SCTimer counters to stop. This is a logical OR of members of the - * enumeration ::sctimer_counter_t. - */ -static inline void SCTIMER_StopTimer(SCT_Type *base, uint32_t countertoStop) -{ - switch (countertoStop) - { - case (uint32_t)kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Set HALT_L bit when user wants to start the Low counter */ - base->CTRL_ACCESS16BIT.CTRLL |= (SCT_CTRLL_HALT_L_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Set HALT_H bit when user wants to start the High counter */ - base->CTRL_ACCESS16BIT.CTRLH |= (SCT_CTRLH_HALT_H_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_L | (uint32_t)kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_L/HALT_H bit when user wants to H counter and L counter at same time */ - base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Set HALT_L bit when the counter is operating in 32-bit mode (unify counter). */ - base->CTRL |= (SCT_CTRL_HALT_L_MASK); - break; - - default: - /* Counter_L/Counter_H can't work together with Counter_U. */ - assert(false); - break; - } -} - -/*! @}*/ - -/*! - * @name Functions to create a new event and manage the state logic - * @{ - */ - -/*! - * @brief Create an event that is triggered on a match or IO and schedule in current state. - * - * This function will configure an event using the options provided by the user. If the event type uses - * the counter match, then the function will set the user provided match value into a match register - * and put this match register number into the event control register. - * The event is enabled for the current state and the event number is increased by one at the end. - * The function returns the event number; this event number can be used to configure actions to be - * done when this event is triggered. - * - * @param base SCTimer peripheral base address - * @param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t - * @param matchValue The match value that will be programmed to a match register - * @param whichIO The input or output that will be involved in event triggering. This field - * is ignored if the event type is "match only" - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Pointer to a variable where the new event number is stored - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of events created or - if we have reached the limit in terms of number of match registers - */ -status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, - sctimer_event_t howToMonitor, - uint32_t matchValue, - uint32_t whichIO, - sctimer_counter_t whichCounter, - uint32_t *event); - -/*! - * @brief Enable an event in the current state. - * - * This function will allow the event passed in to trigger in the current state. The event must - * be created earlier by either calling the function SCTIMER_SetupPwm() or function - * SCTIMER_CreateAndScheduleEvent() . - * - * @param base SCTimer peripheral base address - * @param event Event number to enable in the current state - * - */ -void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event); - -/*! - * @brief Increase the state by 1 - * - * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new - * state. - * - * @param base SCTimer peripheral base address - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of states used - - */ -status_t SCTIMER_IncreaseState(SCT_Type *base); - -/*! - * @brief Provides the current state - * - * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). - * - * @param base SCTimer peripheral base address - * - * @return The current state - */ -uint32_t SCTIMER_GetCurrentState(SCT_Type *base); - -/*! - * @brief Set the counter current state. - * - * The function is to set the state variable bit field of STATE register. Writing to the STATE_L, STATE_H, or unified - * register is only allowed when the corresponding counter is halted (HALT bits are set to 1 in the CTRL register). - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param state The counter current state number (only support range from 0~31). - */ -static inline void SCTIMER_SetCounterState(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t state) -{ - /* SCT only support 0 ~ FSL_FEATURE_SCT_NUMBER_OF_STATES state value. */ - assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); - - SCTIMER_StopTimer(base, (uint32_t)whichCounter); - - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_L bits when user wants to setup the Low counter */ - base->STATE_ACCESS16BIT.STATEL = SCT_STATEL_STATEL(state); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_H bits when user wants to start the High counter */ - base->STATE_ACCESS16BIT.STATEH = SCT_STATEH_STATEH(state); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_L bits when counter is operating in 32-bit mode (unify counter). */ - base->STATE = SCT_STATE_STATE_L(state); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } - - SCTIMER_StartTimer(base, (uint32_t)whichCounter); -} - -/*! - * @brief Get the counter current state value. - * - * The function is to get the state variable bit field of STATE register. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @return The the counter current state value. - */ -static inline uint16_t SCTIMER_GetCounterState(SCT_Type *base, sctimer_counter_t whichCounter) -{ - uint16_t regs; - - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_L bits when user wants to setup the Low counter */ - regs = base->STATE_ACCESS16BIT.STATEL & SCT_STATEL_STATEL_MASK; - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_H bits when user wants to start the High counter */ - regs = base->STATE_ACCESS16BIT.STATEH & SCT_STATEH_STATEH_MASK; - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_L bits when counter is operating in 32-bit mode (unify counter). */ - regs = (uint16_t)(base->STATE & SCT_STATE_STATE_L_MASK); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } - - return regs; -} - -/*! @}*/ - -/*! - * @name Actions to take in response to an event - * @{ - */ - -/*! - * @brief Setup capture of the counter value on trigger of a selected event - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param captureRegister Pointer to a variable where the capture register number will be returned. User - * can read the captured value from this register when the specified event is triggered. - * @param event Event number that will trigger the capture - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of match/capture registers available - */ -status_t SCTIMER_SetupCaptureAction(SCT_Type *base, - sctimer_counter_t whichCounter, - uint32_t *captureRegister, - uint32_t event); - -/*! - * @brief Receive noticification when the event trigger an interrupt. - * - * If the interrupt for the event is enabled by the user, then a callback can be registered - * which will be invoked when the event is triggered - * - * @param base SCTimer peripheral base address - * @param event Event number that will trigger the interrupt - * @param callback Function to invoke when the event is triggered - */ - -void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event); - -/*! - * @brief Change the load method of transition to the specified state. - * - * Change the load method of transition, it will be triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param event Event number that will change the method to trigger the state transition - * @param fgLoad The method to load highest-numbered event occurring for that state to the STATE register. - * - true: Load the STATEV value to STATE when the event occurs to be the next state. - * - false: Add the STATEV value to STATE when the event occurs to be the next state. - */ -static inline void SCTIMER_SetupStateLdMethodAction(SCT_Type *base, uint32_t event, bool fgLoad) -{ - uint32_t reg = base->EV[event].CTRL; - - if (fgLoad) - { - /* Load the STATEV value to STATE when the event occurs to be the next state */ - reg |= SCT_EV_CTRL_STATELD_MASK; - } - else - { - /* Add the STATEV value to STATE when the event occurs to be the next state */ - reg &= ~SCT_EV_CTRL_STATELD_MASK; - } - - base->EV[event].CTRL = reg; -} - -/*! - * @brief Transition to the specified state with Load method. - * - * This transition will be triggered by the event number that is passed in by the user, the method decide how to load - * the highest-numbered event occurring for that state to the STATE register. - * - * @param base SCTimer peripheral base address - * @param nextState The next state SCTimer will transition to - * @param event Event number that will trigger the state transition - * @param fgLoad The method to load the highest-numbered event occurring for that state to the STATE register. - * - true: Load the STATEV value to STATE when the event occurs to be the next state. - * - false: Add the STATEV value to STATE when the event occurs to be the next state. - */ -static inline void SCTIMER_SetupNextStateActionwithLdMethod(SCT_Type *base, - uint32_t nextState, - uint32_t event, - bool fgLoad) -{ - uint32_t reg = base->EV[event].CTRL; - - reg &= ~(SCT_EV_CTRL_STATEV_MASK | SCT_EV_CTRL_STATELD_MASK); - - reg |= SCT_EV_CTRL_STATEV(nextState); - - if (fgLoad) - { - /* Load the STATEV value when the event occurs to be the next state */ - reg |= SCT_EV_CTRL_STATELD_MASK; - } - - base->EV[event].CTRL = reg; -} - -/*! - * @brief Transition to the specified state. - * @deprecated Do not use this function. It has been superceded by @ref SCTIMER_SetupNextStateActionwithLdMethod - * - * This transition will be triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param nextState The next state SCTimer will transition to - * @param event Event number that will trigger the state transition - */ -static inline void SCTIMER_SetupNextStateAction(SCT_Type *base, uint32_t nextState, uint32_t event) -{ - uint32_t reg = base->EV[event].CTRL; - - reg &= ~(SCT_EV_CTRL_STATEV_MASK); - /* Load the STATEV value when the event occurs to be the next state */ - reg |= SCT_EV_CTRL_STATEV(nextState) | SCT_EV_CTRL_STATELD_MASK; - - base->EV[event].CTRL = reg; -} - -/*! - * @brief Setup event active direction when the counters are operating in BIDIR mode. - * - * @param base SCTimer peripheral base address - * @param activeDirection Event generation active direction, see @ref sctimer_event_active_direction_t. - * @param event Event number that need setup the active direction. - */ -static inline void SCTIMER_SetupEventActiveDirection(SCT_Type *base, - sctimer_event_active_direction_t activeDirection, - uint32_t event) -{ - uint32_t reg = base->EV[event].CTRL; - - reg &= ~(SCT_EV_CTRL_DIRECTION_MASK); - - reg |= SCT_EV_CTRL_DIRECTION(activeDirection); - - base->EV[event].CTRL = reg; -} - -/*! - * @brief Set the Output. - * - * This output will be set when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to set - * @param event Event number that will trigger the output change - */ -static inline void SCTIMER_SetupOutputSetAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - base->OUT[whichIO].SET |= (1UL << event); -} - -/*! - * @brief Clear the Output. - * - * This output will be cleared when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to clear - * @param event Event number that will trigger the output change - */ -static inline void SCTIMER_SetupOutputClearAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - base->OUT[whichIO].CLR |= (1UL << event); -} - -/*! - * @brief Toggle the output level. - * - * This change in the output level is triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to toggle - * @param event Event number that will trigger the output change - */ -void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event); - -/*! - * @brief Limit the running counter. - * - * The counter is limited when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Event number that will trigger the counter to be limited - */ -static inline void SCTIMER_SetupCounterLimitAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->LIMIT_ACCESS16BIT.LIMITL |= SCT_LIMITL_LIMITL(1UL << event); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->LIMIT_ACCESS16BIT.LIMITH |= SCT_LIMITH_LIMITH(1UL << event); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->LIMIT |= SCT_LIMIT_LIMMSK_L(1UL << event); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } -} - -/*! - * @brief Stop the running counter. - * - * The counter is stopped when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Event number that will trigger the counter to be stopped - */ -static inline void SCTIMER_SetupCounterStopAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->STOP_ACCESS16BIT.STOPL |= SCT_STOPL_STOPL(1UL << event); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->STOP_ACCESS16BIT.STOPH |= SCT_STOPH_STOPH(1UL << event); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->STOP |= SCT_STOP_STOPMSK_L(1UL << event); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } -} - -/*! - * @brief Re-start the stopped counter. - * - * The counter will re-start when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Event number that will trigger the counter to re-start - */ -static inline void SCTIMER_SetupCounterStartAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->START_ACCESS16BIT.STARTL |= SCT_STARTL_STARTL(1UL << event); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->START_ACCESS16BIT.STARTH |= SCT_STARTH_STARTH(1UL << event); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->START |= SCT_START_STARTMSK_L(1UL << event); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } -} - -/*! - * @brief Halt the running counter. - * - * The counter is disabled (halted) when the event number that is passed in by the user is - * triggered. When the counter is halted, all further events are disabled. The HALT condition - * can only be removed by calling the SCTIMER_StartTimer() function. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Event number that will trigger the counter to be halted - */ -static inline void SCTIMER_SetupCounterHaltAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->HALT_ACCESS16BIT.HALTL |= SCT_HALTL_HALTL(1UL << event); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->HALT_ACCESS16BIT.HALTH |= SCT_HALTH_HALTH(1UL << event); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->HALT |= SCT_HALT_HALTMSK_L(1UL << event); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } -} - -#if !(defined(FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) && FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) -/*! - * @brief Generate a DMA request. - * - * DMA request will be triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param dmaNumber The DMA request to generate - * @param event Event number that will trigger the DMA request - */ -static inline void SCTIMER_SetupDmaTriggerAction(SCT_Type *base, uint32_t dmaNumber, uint32_t event) -{ - if (dmaNumber == 0U) - { - base->DMAREQ0 |= (1UL << event); - } - else - { - base->DMAREQ1 |= (1UL << event); - } -} -#endif /* FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST */ - -/*! - * @brief Set the value of counter. - * - * The function is to set the value of Count register, Writing to the COUNT_L, COUNT_H, or unified register - * is only allowed when the corresponding counter is halted (HALT bits are set to 1 in the CTRL register). - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param value the counter value update to the COUNT register. - */ -static inline void SCTIMER_SetCOUNTValue(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t value) -{ - SCTIMER_StopTimer(base, (uint32_t)whichCounter); - - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(value <= 0xFFFFU); - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->COUNT_ACCESS16BIT.COUNTL = (uint16_t)value; - break; - - case kSCTIMER_Counter_H: - assert(value <= 0xFFFFU); - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->COUNT_ACCESS16BIT.COUNTH = (uint16_t)value; - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->COUNT &= ~SCT_COUNT_CTR_L_MASK; - base->COUNT |= SCT_COUNT_CTR_L(value); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } - - SCTIMER_StartTimer(base, (uint32_t)whichCounter); -} - -/*! - * @brief Get the value of counter. - * - * The function is to read the value of Count register, software can read the counter registers at any time.. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @return The value of counter selected. - */ -static inline uint32_t SCTIMER_GetCOUNTValue(SCT_Type *base, sctimer_counter_t whichCounter) -{ - uint32_t value; - - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - value = base->COUNT_ACCESS16BIT.COUNTL; - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - value = base->COUNT_ACCESS16BIT.COUNTH; - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - value = base->COUNT; - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } - - return value; -} - -/*! - * @brief Set the state mask bit field of EV_STATE register. - * - * @param base SCTimer peripheral base address - * @param event The EV_STATE register be set. - * @param state The state value in which the event is enabled to occur. - */ -static inline void SCTIMER_SetEventInState(SCT_Type *base, uint32_t event, uint32_t state) -{ - assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); - assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); - - base->EV[event].STATE |= SCT_EV_STATE_STATEMSKn((uint32_t)1U << state); -} - -/*! - * @brief Clear the state mask bit field of EV_STATE register. - * - * @param base SCTimer peripheral base address - * @param event The EV_STATE register be clear. - * @param state The state value in which the event is disabled to occur. - */ -static inline void SCTIMER_ClearEventInState(SCT_Type *base, uint32_t event, uint32_t state) -{ - assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); - assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); - - base->EV[event].STATE &= ~SCT_EV_STATE_STATEMSKn((uint32_t)1U << state); -} - -/*! - * @brief Get the state mask bit field of EV_STATE register. - * - * @note This function is to check whether the event is enabled in a specific state. - * - * @param base SCTimer peripheral base address - * @param event The EV_STATE register be read. - * @param state The state value. - * - * @return The the state mask bit field of EV_STATE register. - * - true: The event is enable in state. - * - false: The event is disable in state. - */ -static inline bool SCTIMER_GetEventInState(SCT_Type *base, uint32_t event, uint32_t state) -{ - assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); - assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); - - return (0U != (base->EV[event].STATE & SCT_EV_STATE_STATEMSKn((uint32_t)1U << state))); -} - -/*! - * @brief SCTimer interrupt handler. - * - * @param base SCTimer peripheral base address. - */ -void SCTIMER_EventHandleIRQ(SCT_Type *base); - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_SCTIMER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_sdif.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_sdif.c deleted file mode 100644 index ba2fbafd71b..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_sdif.c +++ /dev/null @@ -1,1688 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sdif.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.sdif" -#endif - -/* Typedef for interrupt handler. */ -typedef void (*sdif_isr_t)(SDIF_Type *base, sdif_handle_t *handle); - -/*! @brief convert the name here, due to RM use SDIO */ -#define SDIF_DriverIRQHandler SDIO_DriverIRQHandler -/*! @brief define the controller support sd/sdio card version 2.0 */ -#define SDIF_SUPPORT_SD_VERSION (0x20) -/*! @brief define the controller support mmc card version 4.4 */ -#define SDIF_SUPPORT_MMC_VERSION (0x44) - -#ifndef SDIF_TIMEOUT_VALUE -/*! @brief define the timeout counter, used to polling the start bit auto-cleared when sending clock sync command */ -#define SDIF_TIMEOUT_VALUE (~0U) -#endif - -#ifndef SDIF_RESET_TIMEOUT_VALUE -/*! @brief define the reset timeout counter, two AHB clock cycle, the reset should auto-cleared. */ -#define SDIF_RESET_TIMEOUT_VALUE (100U) -#endif - -/*! @brief this value can be any value */ -#define SDIF_POLL_DEMAND_VALUE (0xFFU) -/*! @brief DMA descriptor buffer1 size */ -#define SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(x) ((x)&0x1FFFU) -/*! @brief DMA descriptor buffer2 size */ -#define SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(x) (((x)&0x1FFFU) << 13U) -/*! @brief RX water mark value */ -#define SDIF_RX_WATERMARK (15U) -/*! @brief TX water mark value */ -#define SDIF_TX_WATERMARK (16U) -/*! @brief check flag avalibility */ -#define IS_SDIF_FLAG_SET(reg, flag) (((reg) & ((uint32_t)flag)) != 0UL) -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get the instance. - * - * @param base SDIF peripheral base address. - * @return Instance number. - */ -static uint32_t SDIF_GetInstance(SDIF_Type *base); - -/* - * @brief config the SDIF interface before transfer between the card and host - * @param SDIF base address - * @param transfer config structure - * @param enDMA DMA enable flag - */ -static status_t SDIF_TransferConfig(SDIF_Type *base, sdif_transfer_t *transfer, bool enDMA); - -/* - * @brief wait the command done function and check error status - * @param SDIF base address - * @param command config structure - */ -static status_t SDIF_WaitCommandDone(SDIF_Type *base, sdif_command_t *command); - -/* - * @brief transfer data in a blocking way - * @param SDIF base address - * @param data config structure - * @param indicate current transfer mode:DMA or polling - */ -static status_t SDIF_TransferDataBlocking(SDIF_Type *base, sdif_data_t *data, bool isDMA); - -/* - * @brief read the command response - * @param SDIF base address - * @param sdif command pointer - */ -static status_t SDIF_ReadCommandResponse(SDIF_Type *base, sdif_command_t *command); - -/* - * @brief handle transfer command interrupt - * @param SDIF base address - * @param sdif handle - * @param interrupt mask flags - */ -static void SDIF_TransferHandleCommand(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags); - -/* - * @brief handle transfer data interrupt - * @param SDIF base address - * @param sdif handle - * @param interrupt mask flags - */ -static void SDIF_TransferHandleData(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags); - -/* - * @brief handle DMA transfer - * @param SDIF base address - * @param sdif handle - * @param interrupt mask flag - */ -static void SDIF_TransferHandleDMA(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags); - -/* - * @brief driver IRQ handler - * @param SDIF base address - * @param sdif handle - */ -static void SDIF_TransferHandleIRQ(SDIF_Type *base, sdif_handle_t *handle); - -/* - * @brief read data port - * @param SDIF base address - * @param sdif data - * @param the number of data been transferred - */ -static uint32_t SDIF_ReadDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords); - -/* - * @brief write data port - * @param SDIF base address - * @param sdif data - * @param the number of data been transferred - */ -static uint32_t SDIF_WriteDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords); - -/* - * @brief read data by blocking way - * @param SDIF base address - * @param sdif data - */ -static status_t SDIF_ReadDataPortBlocking(SDIF_Type *base, sdif_data_t *data); - -/* - * @brief write data by blocking way - * @param SDIF base address - * @param sdif data - */ -static status_t SDIF_WriteDataPortBlocking(SDIF_Type *base, sdif_data_t *data); - -/* - * @brief handle sdio interrupt - * This function will call the SDIO interrupt callback - * @param SDIF base address - * @param SDIF handle - */ -static void SDIF_TransferHandleSDIOInterrupt(SDIF_Type *base, sdif_handle_t *handle); - -/* - * @brief handle card detect - * This function will call the cardInserted callback - * @param SDIF base addres - * @param SDIF handle - */ -static void SDIF_TransferHandleCardDetect(SDIF_Type *base, sdif_handle_t *handle); - -/* - * @brief set command register - * This api include polling the status of the bit START_COMMAND, if 0 used as timeout value, then this function - * will return directly without polling the START_CMD status. - * - * @param base SDIF base addres - * @param cmdIndex command index - * @param argument command argument - * @param timeout timeout value - * - * @return kStatus_Success, kStatus_SDIF_SyncCmdTimeout - */ -static status_t SDIF_SetCommandRegister(SDIF_Type *base, uint32_t cmdIndex, uint32_t argument, uint32_t timeout); - -/* - * @brief SDIF sync clock command function. - * - * This function will try to recovery the host while sending clock command failed. - * - * @param base SDIF base addres - * - * @return kStatus_Success, kStatus_SDIF_SyncCmdTimeout - */ -static status_t SDIF_SyncClockCommand(SDIF_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief SDIF internal handle pointer array */ -static sdif_handle_t *s_sdifHandle[FSL_FEATURE_SOC_SDIF_COUNT]; - -/*! @brief SDIF base pointer array */ -static SDIF_Type *const s_sdifBase[] = SDIF_BASE_PTRS; - -/*! @brief SDIF IRQ name array */ -static const IRQn_Type s_sdifIRQ[] = SDIF_IRQS; - -/* SDIF ISR for transactional APIs. */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -static sdif_isr_t s_sdifIsr = (sdif_isr_t)DefaultISR; -#else -static sdif_isr_t s_sdifIsr; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t SDIF_GetInstance(SDIF_Type *base) -{ - uint8_t instance = 0U; - - while ((instance < ARRAY_SIZE(s_sdifBase)) && (s_sdifBase[instance] != base)) - { - instance++; - } - - assert(instance < ARRAY_SIZE(s_sdifBase)); - - return instance; -} - -static status_t SDIF_TransferConfig(SDIF_Type *base, sdif_transfer_t *transfer, bool enDMA) -{ - sdif_command_t *command = transfer->command; - sdif_data_t *data = transfer->data; - - if ((command == NULL) || ((data != NULL) && (data->blockSize > SDIF_BLKSIZ_BLOCK_SIZE_MASK))) - { - return kStatus_SDIF_InvalidArgument; - } - - if (data != NULL) - { - /* config the block size register ,the block size maybe smaller than FIFO - depth, will test on the board */ - base->BLKSIZ = SDIF_BLKSIZ_BLOCK_SIZE(data->blockSize); - /* config the byte count register */ - base->BYTCNT = SDIF_BYTCNT_BYTE_COUNT(data->blockSize * data->blockCount); - - command->flags |= (uint32_t)kSDIF_DataExpect; /* need transfer data flag */ - - if (data->txData != NULL) - { - command->flags |= (uint32_t)kSDIF_DataWriteToCard; /* data transfer direction */ - } - else - { - /* config the card read threshold,enable the card read threshold */ - if (data->blockSize <= (SDIF_FIFO_COUNT * sizeof(uint32_t))) - { - base->CARDTHRCTL = SDIF_CARDTHRCTL_CARDRDTHREN_MASK | SDIF_CARDTHRCTL_CARDTHRESHOLD(data->blockSize); - } - else - { - base->CARDTHRCTL &= ~SDIF_CARDTHRCTL_CARDRDTHREN_MASK; - } - } - - if (data->streamTransfer) - { - command->flags |= - (uint32_t)kSDIF_DataStreamTransfer; /* indicate if use stream transfer or block transfer */ - } - - if ((data->enableAutoCommand12) && - (data->blockCount > 1UL)) /* indicate if auto stop will send after the data transfer done */ - { - command->flags |= (uint32_t)kSDIF_DataTransferAutoStop; - } - } - /* R2 response length long */ - if (command->responseType == (uint32_t)kCARD_ResponseTypeR2) - { - command->flags |= ((uint32_t)kSDIF_CmdCheckResponseCRC | (uint32_t)kSDIF_CmdResponseLengthLong | - (uint32_t)kSDIF_CmdResponseExpect); - } - else if ((command->responseType == (uint32_t)kCARD_ResponseTypeR3) || - (command->responseType == (uint32_t)kCARD_ResponseTypeR4)) - { - command->flags |= (uint32_t)kSDIF_CmdResponseExpect; /* response R3 do not check Response CRC */ - } - else - { - if (command->responseType != (uint32_t)kCARD_ResponseTypeNone) - { - command->flags |= ((uint32_t)kSDIF_CmdCheckResponseCRC | (uint32_t)kSDIF_CmdResponseExpect); - } - } - - if (command->type == (uint32_t)kCARD_CommandTypeAbort) - { - command->flags |= (uint32_t)kSDIF_TransferStopAbort; - } - - /* wait pre-transfer complete */ - command->flags |= (uint32_t)kSDIF_WaitPreTransferComplete | (uint32_t)kSDIF_CmdDataUseHoldReg; - - /* handle interrupt and status mask */ - if (data != NULL) - { - SDIF_ClearInterruptStatus(base, (uint32_t)kSDIF_AllInterruptStatus); - if (enDMA) - { - SDIF_ClearInternalDMAStatus(base, kSDIF_DMAAllStatus); - SDIF_EnableDmaInterrupt(base, kSDIF_DMAAllStatus); - SDIF_EnableInterrupt(base, (uint32_t)kSDIF_CommandTransferStatus); - } - else - { - SDIF_EnableInterrupt(base, (uint32_t)kSDIF_CommandTransferStatus | (uint32_t)kSDIF_DataTransferStatus); - } - } - else - { - SDIF_ClearInterruptStatus(base, kSDIF_CommandTransferStatus); - SDIF_EnableInterrupt(base, kSDIF_CommandTransferStatus); - } - - return kStatus_Success; -} - -static status_t SDIF_ReadCommandResponse(SDIF_Type *base, sdif_command_t *command) -{ - /* check if command exist,if not, do not read the response */ - if (NULL != command) - { - /* read response */ - command->response[0U] = base->RESP[0U]; - if (command->responseType == (uint32_t)kCARD_ResponseTypeR2) - { - command->response[1U] = base->RESP[1U]; - command->response[2U] = base->RESP[2U]; - command->response[3U] = base->RESP[3U]; - } - - if ((command->responseErrorFlags != 0U) && ((command->responseType == (uint32_t)kCARD_ResponseTypeR1) || - (command->responseType == (uint32_t)kCARD_ResponseTypeR1b) || - (command->responseType == (uint32_t)kCARD_ResponseTypeR6) || - (command->responseType == (uint32_t)kCARD_ResponseTypeR5))) - { - if (((command->responseErrorFlags) & (command->response[0U])) != 0UL) - { - return kStatus_SDIF_ResponseError; - } - } - } - - return kStatus_Success; -} - -static status_t SDIF_WaitCommandDone(SDIF_Type *base, sdif_command_t *command) -{ - uint32_t status = 0U; - uint32_t errorStatus = (uint32_t)kSDIF_ResponseError | (uint32_t)kSDIF_ResponseTimeout | - (uint32_t)kSDIF_DataStartBitError | (uint32_t)kSDIF_HardwareLockError | - (uint32_t)kSDIF_ResponseCRCError; - - do - { - status = SDIF_GetInterruptStatus(base); - } while ((status & (errorStatus | (uint32_t)kSDIF_CommandDone)) == 0UL); - /* clear interrupt status flag first */ - SDIF_ClearInterruptStatus(base, status & (uint32_t)kSDIF_CommandTransferStatus); - if ((status & errorStatus) != 0UL) - { - return kStatus_SDIF_SendCmdFail; - } - else - { - return SDIF_ReadCommandResponse(base, command); - } -} - -static status_t SDIF_SetCommandRegister(SDIF_Type *base, uint32_t cmdIndex, uint32_t argument, uint32_t timeout) -{ - uint32_t syncTimeout = timeout; - - base->CMDARG = argument; - base->CMD = cmdIndex | SDIF_CMD_START_CMD_MASK; - - while ((base->CMD & SDIF_CMD_START_CMD_MASK) == SDIF_CMD_START_CMD_MASK) - { - if (timeout == 0U) - { - break; - } - - if (0UL == syncTimeout) - { - return kStatus_SDIF_SyncCmdTimeout; - } - - --syncTimeout; - } - - return kStatus_Success; -} - -/*! - * brief SDIF release the DMA descriptor to DMA engine - * this function should be called when DMA descriptor unavailable status occurs - * param base SDIF peripheral base address. - * param sdif DMA config pointer - */ -status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig) -{ - assert(NULL != dmaConfig); - assert(NULL != dmaConfig->dmaDesBufferStartAddr); - - sdif_dma_descriptor_t *dmaDesAddr; - uint32_t *tempDMADesBuffer = dmaConfig->dmaDesBufferStartAddr; - uint32_t dmaDesBufferSize = 0UL; - - dmaDesAddr = (sdif_dma_descriptor_t *)(uint32_t)tempDMADesBuffer; - - /* chain descriptor mode */ - if (dmaConfig->mode == kSDIF_ChainDMAMode) - { - while (((dmaDesAddr->dmaDesAttribute & SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG) != - SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG) && - (dmaDesBufferSize < dmaConfig->dmaDesBufferLen * sizeof(uint32_t))) - { - /* set the OWN bit */ - dmaDesAddr->dmaDesAttribute |= SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG; - dmaDesAddr++; - dmaDesBufferSize += sizeof(sdif_dma_descriptor_t); - } - /* if access dma des address overflow, return fail */ - if (dmaDesBufferSize > dmaConfig->dmaDesBufferLen * sizeof(uint32_t)) - { - return kStatus_Fail; - } - dmaDesAddr->dmaDesAttribute |= SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG; - } - /* dual descriptor mode */ - else - { - while (((dmaDesAddr->dmaDesAttribute & SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG) != - SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG) && - (dmaDesBufferSize < dmaConfig->dmaDesBufferLen * sizeof(uint32_t))) - { - dmaDesAddr = (sdif_dma_descriptor_t *)(uint32_t)tempDMADesBuffer; - dmaDesAddr->dmaDesAttribute |= SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG; - tempDMADesBuffer += dmaConfig->dmaDesSkipLen; - } - /* if access dma des address overflow, return fail */ - if (dmaDesBufferSize > dmaConfig->dmaDesBufferLen * sizeof(uint32_t)) - { - return kStatus_Fail; - } - dmaDesAddr->dmaDesAttribute |= SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG; - } - /* reload DMA descriptor */ - base->PLDMND = SDIF_POLL_DEMAND_VALUE; - - return kStatus_Success; -} - -static uint32_t SDIF_ReadDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords) -{ - uint32_t i; - uint32_t totalWords; - uint32_t wordsCanBeRead; /* The words can be read at this time. */ - uint32_t readWatermark = ((base->FIFOTH & SDIF_FIFOTH_RX_WMARK_MASK) >> SDIF_FIFOTH_RX_WMARK_SHIFT); - - if ((base->CTRL & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) == 0UL) - { - if (data->blockSize % sizeof(uint32_t) != 0U) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */ - if (readWatermark >= totalWords) - { - wordsCanBeRead = totalWords; - } - /* If watermark level is less than totalWords and left words to be sent is equal or bigger than readWatermark, - transfers watermark level words. */ - else if ((readWatermark < totalWords) && ((totalWords - transferredWords) >= readWatermark)) - { - wordsCanBeRead = readWatermark; - } - /* If watermark level is less than totalWords and left words to be sent is less than readWatermark, transfers - left - words. */ - else - { - wordsCanBeRead = (totalWords - transferredWords); - } - - i = 0U; - while (i < wordsCanBeRead) - { - data->rxData[transferredWords++] = base->FIFO[i]; - i++; - } - } - - return transferredWords; -} - -static uint32_t SDIF_WriteDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords) -{ - uint32_t i; - uint32_t totalWords; - uint32_t wordsCanBeWrite; /* The words can be read at this time. */ - uint32_t writeWatermark = ((base->FIFOTH & SDIF_FIFOTH_TX_WMARK_MASK) >> SDIF_FIFOTH_TX_WMARK_SHIFT); - - if ((base->CTRL & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) == 0UL) - { - if (data->blockSize % sizeof(uint32_t) != 0U) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */ - if (writeWatermark >= totalWords) - { - wordsCanBeWrite = totalWords; - } - /* If watermark level is less than totalWords and left words to be sent is equal or bigger than writeWatermark, - transfers watermark level words. */ - else if ((writeWatermark < totalWords) && ((totalWords - transferredWords) >= writeWatermark)) - { - wordsCanBeWrite = writeWatermark; - } - /* If watermark level is less than totalWords and left words to be sent is less than writeWatermark, transfers - left - words. */ - else - { - wordsCanBeWrite = (totalWords - transferredWords); - } - - i = 0U; - while (i < wordsCanBeWrite) - { - base->FIFO[i] = data->txData[transferredWords++]; - i++; - } - } - - return transferredWords; -} - -static status_t SDIF_ReadDataPortBlocking(SDIF_Type *base, sdif_data_t *data) -{ - uint32_t totalWords; - uint32_t transferredWords = 0U; - status_t error = kStatus_Success; - uint32_t status; - bool transferOver = false; - - if (data->blockSize % sizeof(uint32_t) != 0UL) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - while ((transferredWords < totalWords) && (error == kStatus_Success)) - { - /* wait data transfer complete or reach RX watermark */ - do - { - status = SDIF_GetInterruptStatus(base); - if (IS_SDIF_FLAG_SET(status, kSDIF_DataTransferError)) - { - if (!(data->enableIgnoreError)) - { - error = kStatus_Fail; - break; - } - } - } while (!IS_SDIF_FLAG_SET(status, ((uint32_t)kSDIF_DataTransferOver | (uint32_t)kSDIF_ReadFIFORequest)) && - (!transferOver)); - - if (IS_SDIF_FLAG_SET(status, kSDIF_DataTransferOver)) - { - transferOver = true; - } - - if (error == kStatus_Success) - { - transferredWords = SDIF_ReadDataPort(base, data, transferredWords); - } - - /* clear interrupt status */ - SDIF_ClearInterruptStatus(base, status); - } - - return error; -} - -static status_t SDIF_WriteDataPortBlocking(SDIF_Type *base, sdif_data_t *data) -{ - uint32_t totalWords; - uint32_t transferredWords = 0U; - status_t error = kStatus_Success; - uint32_t status; - - if (data->blockSize % sizeof(uint32_t) != 0UL) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - while ((transferredWords < totalWords) && (error == kStatus_Success)) - { - /* wait data transfer complete or reach RX watermark */ - do - { - status = SDIF_GetInterruptStatus(base); - if (IS_SDIF_FLAG_SET(status, kSDIF_DataTransferError)) - { - if (!(data->enableIgnoreError)) - { - error = kStatus_Fail; - } - } - } while (!(IS_SDIF_FLAG_SET(status, kSDIF_WriteFIFORequest))); - - if (error == kStatus_Success) - { - transferredWords = SDIF_WriteDataPort(base, data, transferredWords); - } - - /* clear interrupt status */ - SDIF_ClearInterruptStatus(base, status); - } - - while ((SDIF_GetInterruptStatus(base) & (uint32_t)kSDIF_DataTransferOver) != (uint32_t)kSDIF_DataTransferOver) - { - } - - if (IS_SDIF_FLAG_SET(SDIF_GetInterruptStatus(base), kSDIF_DataTransferError)) - { - if (!(data->enableIgnoreError)) - { - error = kStatus_Fail; - } - } - SDIF_ClearInterruptStatus(base, ((uint32_t)kSDIF_DataTransferOver | (uint32_t)kSDIF_DataTransferError)); - - return error; -} - -/*! - * brief reset the different block of the interface. - * param base SDIF peripheral base address. - * param mask indicate which block to reset. - * param timeout value,set to wait the bit self clear - * return reset result. - */ -bool SDIF_Reset(SDIF_Type *base, uint32_t mask, uint32_t timeout) -{ - /* reset through CTRL */ - base->CTRL |= mask; - /* DMA software reset */ - if (IS_SDIF_FLAG_SET(mask, kSDIF_ResetDMAInterface)) - { - /* disable DMA first then do DMA software reset */ - base->BMOD = (base->BMOD & (~SDIF_BMOD_DE_MASK)) | SDIF_BMOD_SWR_MASK; - } - - /* check software DMA reset here for DMA reset also need to check this bit */ - while ((base->CTRL & mask) != 0UL) - { - if (0UL == timeout) - { - break; - } - timeout--; - } - - return timeout != 0UL ? true : false; -} - -static status_t SDIF_TransferDataBlocking(SDIF_Type *base, sdif_data_t *data, bool isDMA) -{ - assert(NULL != data); - - uint32_t dmaStatus = 0UL; - status_t error = kStatus_Success; - - /* in DMA mode, only need to wait the complete flag and check error */ - if (isDMA) - { - do - { - dmaStatus = SDIF_GetInternalDMAStatus(base); - if (IS_SDIF_FLAG_SET(dmaStatus, (uint32_t)kSDIF_DMAFatalBusError)) - { - SDIF_ClearInternalDMAStatus( - base, (uint32_t)kSDIF_DMAFatalBusError | (uint32_t)kSDIF_AbnormalInterruptSummary); - error = kStatus_SDIF_DMATransferFailWithFBE; /* in this condition,need reset */ - } - /* Card error summary, include EBE,SBE,Data CRC,RTO,DRTO,Response error */ - if (IS_SDIF_FLAG_SET(dmaStatus, (uint32_t)kSDIF_DMACardErrorSummary)) - { - SDIF_ClearInternalDMAStatus( - base, (uint32_t)kSDIF_DMACardErrorSummary | (uint32_t)kSDIF_AbnormalInterruptSummary); - if (!(data->enableIgnoreError)) - { - error = kStatus_SDIF_DataTransferFail; - } - - /* if error occur, then return */ - break; - } - } while (!(IS_SDIF_FLAG_SET( - dmaStatus, ((uint32_t)kSDIF_DMATransFinishOneDescriptor | (uint32_t)kSDIF_DMARecvFinishOneDescriptor)))); - - /* clear the corresponding status bit */ - SDIF_ClearInternalDMAStatus( - base, ((uint32_t)kSDIF_DMATransFinishOneDescriptor | (uint32_t)kSDIF_DMARecvFinishOneDescriptor | - (uint32_t)kSDIF_NormalInterruptSummary)); - - SDIF_ClearInterruptStatus(base, SDIF_GetInterruptStatus(base)); - - if (error != kStatus_Success) - { - return kStatus_SDIF_DataTransferFail; - } - } - else - { - if (data->rxData != NULL) - { - error = SDIF_ReadDataPortBlocking(base, data); - if (error != kStatus_Success) - { - return kStatus_SDIF_DataTransferFail; - } - } - else - { - error = SDIF_WriteDataPortBlocking(base, data); - if (error != kStatus_Success) - { - return kStatus_SDIF_DataTransferFail; - } - } - } - - return kStatus_Success; -} - -/*! - * brief send command to the card - * - * This api include polling the status of the bit START_COMMAND, if 0 used as timeout value, then this function - * will return directly without polling the START_CMD status. - * param base SDIF peripheral base address. - * param command configuration collection. - * param timeout the timeout value of polling START_CMD auto clear status. - * return command excute status - */ -status_t SDIF_SendCommand(SDIF_Type *base, sdif_command_t *cmd, uint32_t timeout) -{ - assert(NULL != cmd); - - return SDIF_SetCommandRegister(base, SDIF_CMD_CMD_INDEX(cmd->index) | (cmd->flags & (~SDIF_CMD_CMD_INDEX_MASK)), - cmd->argument, timeout); -} - -/*! - * brief SDIF send initialize 80 clocks for SD card after initial - * param base SDIF peripheral base address. - * param timeout value - */ -bool SDIF_SendCardActive(SDIF_Type *base, uint32_t timeout) -{ - bool enINT = false; - - /* add for conflict with interrupt mode,close the interrupt temporary */ - if ((base->CTRL & SDIF_CTRL_INT_ENABLE_MASK) == SDIF_CTRL_INT_ENABLE_MASK) - { - enINT = true; - base->CTRL &= ~SDIF_CTRL_INT_ENABLE_MASK; - } - SDIF_ClearInterruptStatus(base, kSDIF_CommandDone); - SDIF_EnableInterrupt(base, kSDIF_CommandDone); - - /* send initialization command */ - if (SDIF_SetCommandRegister(base, SDIF_CMD_SEND_INITIALIZATION_MASK, 0UL, timeout) != kStatus_Success) - { - return false; - } - - /* wait command done */ - while ((SDIF_GetInterruptStatus(base) & (uint32_t)kSDIF_CommandDone) != (uint32_t)kSDIF_CommandDone) - { - } - - /* clear status */ - SDIF_ClearInterruptStatus(base, kSDIF_CommandDone); - SDIF_DisableInterrupt(base, kSDIF_CommandDone); - - /* add for conflict with interrupt mode */ - if (enINT) - { - base->CTRL |= SDIF_CTRL_INT_ENABLE_MASK; - } - - return true; -} - -/*! - * brief SDIF config the clock delay - * This function is used to config the cclk_in delay to - * sample and driver the data ,should meet the min setup - * time and hold time, and user need to config this parameter - * according to your board setting - * param target freq work mode - * param divider not used in this function anymore, use DELAY value instead of phase directly. - */ -void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider) -{ - uint32_t sdioClkCtrl = SYSCON->SDIOCLKCTRL; - - sdioClkCtrl = SYSCON->SDIOCLKCTRL & - (~(SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK | - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK)); - - if (target_HZ >= SDIF_CLOCK_RANGE_NEED_DELAY) - { -#ifdef SDIF_HIGHSPEED_SAMPLE_DELAY - sdioClkCtrl |= SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_HIGHSPEED_SAMPLE_DELAY); -#endif -#ifdef SDIF_HIGHSPEED_DRV_DELAY - sdioClkCtrl |= - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_HIGHSPEED_DRV_DELAY); -#endif - } - else - { -#if defined(SDIF_DEFAULT_MODE_SAMPLE_DELAY) - sdioClkCtrl |= SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_DEFAULT_MODE_SAMPLE_DELAY); -#endif -#if defined(SDIF_DEFAULT_MODE_DRV_DELAY) - sdioClkCtrl |= SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_DEFAULT_MODE_DRV_DELAY); -#endif - } - - SYSCON->SDIOCLKCTRL = sdioClkCtrl; -} - -static status_t SDIF_SyncClockCommand(SDIF_Type *base) -{ - uint32_t syncTimeout = 10000U; - uint32_t sendCommandRetry = 3U; - - do - { - /* update the clock register and wait the pre-transfer complete */ - if (SDIF_SetCommandRegister( - base, (uint32_t)kSDIF_CmdUpdateClockRegisterOnly | (uint32_t)kSDIF_WaitPreTransferComplete, 0UL, - syncTimeout) == kStatus_Success) - { - break; - } - /* if send clock command timeout, it means that polling START_CMD cleared failed, CIU cannot take command at - * this comment, so reset the host controller to recover the CIU interface and state machine. - */ - (void)SDIF_Reset(base, kSDIF_ResetController, syncTimeout); - sendCommandRetry--; - } while (sendCommandRetry != 0U); - - if (sendCommandRetry == 0U) - { - return kStatus_Fail; - } - - return kStatus_Success; -} - -/*! - * brief Sets the card bus clock frequency. - * - * param base SDIF peripheral base address. - * param srcClock_Hz SDIF source clock frequency united in Hz. - * param target_HZ card bus clock frequency united in Hz. - * return The nearest frequency of busClock_Hz configured to SD bus. - */ -uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t target_HZ) -{ - uint32_t divider = 0UL, targetFreq = target_HZ; - - /* if target freq bigger than the source clk, set the target_HZ to - src clk, this interface can run up to 52MHZ with card */ - if (srcClock_Hz < targetFreq) - { - targetFreq = srcClock_Hz; - } - - /* disable the clock first,need sync to CIU*/ - SDIF_EnableCardClock(base, false); - - if (SDIF_SyncClockCommand(base) != kStatus_Success) - { - return 0U; - } - - /*calculate the divider*/ - if (targetFreq != srcClock_Hz) - { - divider = srcClock_Hz / targetFreq; - while (srcClock_Hz / divider > targetFreq) - { - divider++; - } - - if (divider > (SDIF_CLKDIV_CLK_DIVIDER0_MASK * 2UL)) - { - /* Note: if assert occur here, it means that the source clock frequency is too high, the suggestion is - * reconfigure the SDIF divider in SYSCON to get a properly source clock */ - assert(false); - divider = (SDIF_CLKDIV_CLK_DIVIDER0_MASK * 2UL); - } - - divider = (divider + 1UL) / 2UL; - } - /* load the clock divider */ - base->CLKDIV = SDIF_CLKDIV_CLK_DIVIDER0(divider); - /* update the divider to CIU */ - if (SDIF_SyncClockCommand(base) != kStatus_Success) - { - return 0U; - } - - /* enable the card clock and sync to CIU */ - SDIF_EnableCardClock(base, true); - (void)SDIF_SyncClockCommand(base); - - /* config the clock delay to meet the hold time and setup time */ - SDIF_ConfigClockDelay(target_HZ, divider); - - /* return the actual card clock freq */ - return (divider != 0UL) ? (srcClock_Hz / (divider * 2UL)) : srcClock_Hz; -} - -/*! - * brief SDIF abort the read data when SDIF card is in suspend state - * Once assert this bit,data state machine will be reset which is waiting for the - * next blocking data,used in SDIO card suspend sequence,should call after suspend - * cmd send - * param base SDIF peripheral base address. - * param timeout value to wait this bit self clear which indicate the data machine - * reset to idle - */ -bool SDIF_AbortReadData(SDIF_Type *base, uint32_t timeout) -{ - /* assert this bit to reset the data machine to abort the read data */ - base->CTRL |= SDIF_CTRL_ABORT_READ_DATA_MASK; - /* polling the bit self clear */ - while ((base->CTRL & SDIF_CTRL_ABORT_READ_DATA_MASK) == SDIF_CTRL_ABORT_READ_DATA_MASK) - { - if (0UL == timeout) - { - break; - } - timeout--; - } - - return IS_SDIF_FLAG_SET(base->CTRL, SDIF_CTRL_ABORT_READ_DATA_MASK) ? false : true; -} - -/*! - * brief SDIF internal DMA config function - * param base SDIF peripheral base address. - * param internal DMA configuration collection - * param data buffer pointer - * param data buffer size - */ -status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, const uint32_t *data, uint32_t dataSize) -{ - assert(NULL != config); - assert(NULL != data); - - uint32_t dmaEntry = 0UL, i, dmaBufferSize = 0UL, dmaBuffer1Size = 0UL; - uint32_t *tempDMADesBuffer = config->dmaDesBufferStartAddr; - const uint32_t *dataBuffer = data; - sdif_dma_descriptor_t *descriptorPoniter = NULL; - uint32_t maxDMABuffer = (uint32_t)FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE * ((uint32_t)config->mode); - - if ((((uint32_t)data % SDIF_INTERNAL_DMA_ADDR_ALIGN) != 0UL) || - (((uint32_t)tempDMADesBuffer % SDIF_INTERNAL_DMA_ADDR_ALIGN) != 0UL)) - { - return kStatus_SDIF_DMAAddrNotAlign; - } - - /* check the read/write data size,must be a multiple of 4 */ - if (dataSize % sizeof(uint32_t) != 0UL) - { - dataSize += sizeof(uint32_t) - (dataSize % sizeof(uint32_t)); - } - - /*config the bus mode*/ - if (config->enableFixBurstLen) - { - base->BMOD |= SDIF_BMOD_FB_MASK; - } - - /* calculate the dma descriptor entry due to DMA buffer size limit */ - /* if data size smaller than one descriptor buffer size */ - if (dataSize > maxDMABuffer) - { - dmaEntry = dataSize / maxDMABuffer + ((dataSize % maxDMABuffer) != 0UL ? 1UL : 0UL); - } - else /* need one dma descriptor */ - { - dmaEntry = 1UL; - } - - /* check the DMA descriptor buffer len one more time,it is user's responsibility to make sure the DMA descriptor - table - size is bigger enough to hold the transfer descriptor */ - if (config->dmaDesBufferLen * sizeof(uint32_t) < (dmaEntry * sizeof(sdif_dma_descriptor_t) + config->dmaDesSkipLen)) - { - return kStatus_SDIF_DescriptorBufferLenError; - } - - if (config->mode == kSDIF_DualDMAMode) - { - base->BMOD |= SDIF_BMOD_DSL(config->dmaDesSkipLen); /* config the distance between the DMA descriptor */ - for (i = 0UL; i < dmaEntry; i++) - { - if (dataSize > (uint32_t)FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE) - { - dmaBufferSize = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE; - dataSize -= dmaBufferSize; - dmaBuffer1Size = dataSize > (uint32_t)FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE ? - (uint32_t)FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE : - dataSize; - dataSize -= dmaBuffer1Size; - } - else - { - dmaBufferSize = dataSize; - dmaBuffer1Size = 0UL; - } - - descriptorPoniter = (sdif_dma_descriptor_t *)(uint32_t)tempDMADesBuffer; - if (i == 0UL) - { - descriptorPoniter->dmaDesAttribute = SDIF_DMA_DESCRIPTOR_DATA_BUFFER_START_FLAG | - SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG | - SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; - } - else - { - descriptorPoniter->dmaDesAttribute = - SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG | SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; - } - descriptorPoniter->dmaDataBufferSize = - SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(dmaBufferSize) | SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(dmaBuffer1Size); - - descriptorPoniter->dmaDataBufferAddr0 = dataBuffer; - descriptorPoniter->dmaDataBufferAddr1 = dataBuffer + dmaBufferSize / sizeof(uint32_t); - dataBuffer += (dmaBufferSize + dmaBuffer1Size) / sizeof(uint32_t); - - /* descriptor skip length */ - tempDMADesBuffer += config->dmaDesSkipLen + sizeof(sdif_dma_descriptor_t) / sizeof(uint32_t); - } - /* enable the completion interrupt when reach the last descriptor */ - descriptorPoniter->dmaDesAttribute &= ~SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; - descriptorPoniter->dmaDesAttribute |= - SDIF_DMA_DESCRIPTOR_DATA_BUFFER_END_FLAG | SDIF_DMA_DESCRIPTOR_DESCRIPTOR_END_FLAG; - } - else - { - for (i = 0UL; i < dmaEntry; i++) - { - if (dataSize > (uint32_t)FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE) - { - dmaBufferSize = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE; - dataSize -= (uint32_t)FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE; - } - else - { - dmaBufferSize = dataSize; - } - - descriptorPoniter = (sdif_dma_descriptor_t *)(uint32_t)tempDMADesBuffer; - if (i == 0UL) - { - descriptorPoniter->dmaDesAttribute = - SDIF_DMA_DESCRIPTOR_DATA_BUFFER_START_FLAG | SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG | - SDIF_DMA_DESCRIPTOR_SECOND_ADDR_CHAIN_FLAG | SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; - } - else - { - descriptorPoniter->dmaDesAttribute = SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG | - SDIF_DMA_DESCRIPTOR_SECOND_ADDR_CHAIN_FLAG | - SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; - } - descriptorPoniter->dmaDataBufferSize = - SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(dmaBufferSize); /* use only buffer 1 for data buffer*/ - descriptorPoniter->dmaDataBufferAddr0 = dataBuffer; - dataBuffer += dmaBufferSize / sizeof(uint32_t); - tempDMADesBuffer += - sizeof(sdif_dma_descriptor_t) / sizeof(uint32_t); /* calculate the next descriptor address */ - /* this descriptor buffer2 pointer to the next descriptor address */ - descriptorPoniter->dmaDataBufferAddr1 = tempDMADesBuffer; - } - /* enable the completion interrupt when reach the last descriptor */ - descriptorPoniter->dmaDesAttribute &= ~SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; - descriptorPoniter->dmaDesAttribute |= SDIF_DMA_DESCRIPTOR_DATA_BUFFER_END_FLAG; - } - - /* use internal DMA interface */ - base->CTRL |= SDIF_CTRL_USE_INTERNAL_DMAC_MASK; - /* enable the internal SD/MMC DMA */ - base->BMOD |= SDIF_BMOD_DE_MASK; - /* load DMA descriptor buffer address */ - base->DBADDR = (uint32_t)config->dmaDesBufferStartAddr; - - return kStatus_Success; -} - -#if defined(FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD) && FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD -/*! - * brief set card data bus width - * param base SDIF peripheral base address. - * param data bus width type - */ -void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type) -{ - if (type == kSDIF_Bus1BitWidth) - { - base->CTYPE &= ~(SDIF_CTYPE_CARD0_WIDTH0_MASK | SDIF_CTYPE_CARD0_WIDTH1_MASK); - } - else if (type == kSDIF_Bus4BitWidth) - { - base->CTYPE = (base->CTYPE & (~SDIF_CTYPE_CARD0_WIDTH1_MASK)) | SDIF_CTYPE_CARD0_WIDTH0_MASK; - } - else - { - base->CTYPE |= SDIF_CTYPE_CARD0_WIDTH1_MASK; - } -} - -/*! - * brief set card1 data bus width - * param base SDIF peripheral base address. - * param data bus width type - */ -void SDIF_SetCard1BusWidth(SDIF_Type *base, sdif_bus_width_t type) -{ - if (type == kSDIF_Bus1BitWidth) - { - base->CTYPE &= ~(SDIF_CTYPE_CARD1_WIDTH0_MASK | SDIF_CTYPE_CARD1_WIDTH1_MASK); - } - else if (type == kSDIF_Bus4BitWidth) - { - base->CTYPE = (base->CTYPE & (~SDIF_CTYPE_CARD1_WIDTH1_MASK)) | SDIF_CTYPE_CARD1_WIDTH0_MASK; - } - else - { - base->CTYPE |= SDIF_CTYPE_CARD1_WIDTH1_MASK; - } -} -#else -/*! - * brief set card data bus width - * param base SDIF peripheral base address. - * param data bus width type - */ -void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type) -{ - if (type == kSDIF_Bus1BitWidth) - { - base->CTYPE &= ~(SDIF_CTYPE_CARD_WIDTH0_MASK | SDIF_CTYPE_CARD_WIDTH1_MASK); - } - else if (type == kSDIF_Bus4BitWidth) - { - base->CTYPE = (base->CTYPE & (~SDIF_CTYPE_CARD_WIDTH1_MASK)) | SDIF_CTYPE_CARD_WIDTH0_MASK; - } - else - { - base->CTYPE |= SDIF_CTYPE_CARD_WIDTH1_MASK; - } -} -#endif - -/*! - * brief SDIF module initialization function. - * - * Configures the SDIF according to the user configuration. - * param base SDIF peripheral base address. - * param config SDIF configuration information. - */ -void SDIF_Init(SDIF_Type *base, sdif_config_t *config) -{ - assert(NULL != config); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Sdio); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kSDIO_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - - /*config timeout register */ - base->TMOUT = ((base->TMOUT) & ~(SDIF_TMOUT_RESPONSE_TIMEOUT_MASK | SDIF_TMOUT_DATA_TIMEOUT_MASK)) | - SDIF_TMOUT_RESPONSE_TIMEOUT(config->responseTimeout) | SDIF_TMOUT_DATA_TIMEOUT(config->dataTimeout); - - /* config the card detect debounce clock count */ - base->DEBNCE = SDIF_DEBNCE_DEBOUNCE_COUNT(config->cardDetDebounce_Clock); - - /*config the watermark/burst transfer value */ - base->FIFOTH = - SDIF_FIFOTH_TX_WMARK(SDIF_TX_WATERMARK) | SDIF_FIFOTH_RX_WMARK(SDIF_RX_WATERMARK) | SDIF_FIFOTH_DMA_MTS(1U); - - /* disable all the interrupt */ - SDIF_DisableInterrupt(base, kSDIF_AllInterruptStatus); - - /* clear all interrupt/DMA status */ - SDIF_ClearInterruptStatus(base, kSDIF_AllInterruptStatus); - SDIF_ClearInternalDMAStatus(base, kSDIF_DMAAllStatus); -} - -/*! - * brief SDIF transfer function data/cmd in a blocking way - * param base SDIF peripheral base address. - * param DMA config structure - * 1. NULL - * In this condition, polling transfer mode is selected - * 2. avaliable DMA config - * In this condition, DMA transfer mode is selected - * param sdif transfer configuration collection - */ -status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sdif_transfer_t *transfer) -{ - assert(NULL != transfer); - - bool enDMA = true; - sdif_data_t *data = transfer->data; - status_t error = kStatus_Fail; - - /* if need transfer data in dma mode, config the DMA descriptor first */ - if ((data != NULL) && (dmaConfig != NULL)) - { - if ((error = SDIF_InternalDMAConfig(base, dmaConfig, data->rxData != NULL ? data->rxData : data->txData, - data->blockSize * data->blockCount)) == - kStatus_SDIF_DescriptorBufferLenError) - { - return kStatus_SDIF_DescriptorBufferLenError; - } - /* if DMA descriptor address or data buffer address not align with SDIF_INTERNAL_DMA_ADDR_ALIGN, switch to - polling transfer mode, disable the internal DMA */ - if (error == kStatus_SDIF_DMAAddrNotAlign) - { - enDMA = false; - } - } - else - { - enDMA = false; - } - - if (!enDMA) - { - SDIF_EnableInternalDMA(base, false); - } - - /* config the transfer parameter */ - if (SDIF_TransferConfig(base, transfer, enDMA) != kStatus_Success) - { - return kStatus_SDIF_InvalidArgument; - } - - /* send command first, do not wait start bit auto cleared, command done bit should wait while sending normal command - */ - if (SDIF_SendCommand(base, transfer->command, 0UL) != kStatus_Success) - { - return kStatus_SDIF_SendCmdFail; - } - - if (SDIF_WaitCommandDone(base, transfer->command) != kStatus_Success) - { - return kStatus_SDIF_SendCmdFail; - } - /* if use DMA transfer mode ,check the corresponding status bit */ - if (data != NULL) - { - /* handle data transfer */ - error = SDIF_TransferDataBlocking(base, data, enDMA); - if (error != kStatus_Success) - { - return kStatus_SDIF_DataTransferFail; - } - } - - return kStatus_Success; -} - -/*! - * brief SDIF transfer function data/cmd in a non-blocking way - * this API should be use in interrupt mode, when use this API user - * must call SDIF_TransferCreateHandle first, all status check through - * interrupt - * param base SDIF peripheral base address. - * param sdif handle - * param DMA config structure - * This parameter can be config as: - * 1. NULL - In this condition, polling transfer mode is selected - 2. avaliable DMA config - In this condition, DMA transfer mode is selected - * param sdif transfer configuration collection - */ -status_t SDIF_TransferNonBlocking(SDIF_Type *base, - sdif_handle_t *handle, - sdif_dma_config_t *dmaConfig, - sdif_transfer_t *transfer) -{ - assert(NULL != transfer); - - sdif_data_t *data = transfer->data; - status_t error = kStatus_Fail; - bool enDMA = true; - - /* save the data and command before transfer */ - handle->data = transfer->data; - handle->command = transfer->command; - handle->transferredWords = 0U; - - if ((data != NULL) && (dmaConfig != NULL)) - { - /* use internal DMA mode to transfer between the card and host*/ - if ((error = SDIF_InternalDMAConfig(base, dmaConfig, data->rxData != NULL ? data->rxData : data->txData, - data->blockSize * data->blockCount)) == - kStatus_SDIF_DescriptorBufferLenError) - { - return kStatus_SDIF_DescriptorBufferLenError; - } - /* if DMA descriptor address or data buffer address not align with SDIF_INTERNAL_DMA_ADDR_ALIGN, switch to - polling transfer mode, disable the internal DMA */ - if (error == kStatus_SDIF_DMAAddrNotAlign) - { - enDMA = false; - } - } - else - { - enDMA = false; - } - - if (!enDMA) - { - SDIF_EnableInternalDMA(base, false); - } - - /* config the transfer parameter */ - if (SDIF_TransferConfig(base, transfer, enDMA) != kStatus_Success) - { - return kStatus_SDIF_InvalidArgument; - } - - /* send command first, do not wait start bit auto cleared, command done bit should wait while sending normal command - */ - return SDIF_SendCommand(base, transfer->command, 0UL); -} - -/*! - * brief Creates the SDIF handle. - * register call back function for interrupt and enable the interrupt - * param base SDIF peripheral base address. - * param handle SDIF handle pointer. - * param callback Structure pointer to contain all callback functions. - * param userData Callback function parameter. - */ -void SDIF_TransferCreateHandle(SDIF_Type *base, - sdif_handle_t *handle, - sdif_transfer_callback_t *callback, - void *userData) -{ - assert(handle != NULL); - assert(callback != NULL); - - /* reset the handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Set the callback. */ - handle->callback.SDIOInterrupt = callback->SDIOInterrupt; - handle->callback.DMADesUnavailable = callback->DMADesUnavailable; - handle->callback.CommandReload = callback->CommandReload; - handle->callback.TransferComplete = callback->TransferComplete; - handle->callback.cardInserted = callback->cardInserted; - handle->callback.cardRemoved = callback->cardRemoved; - handle->userData = userData; - - /* Save the handle in global variables to support the double weak mechanism. */ - s_sdifHandle[SDIF_GetInstance(base)] = handle; - - /* save IRQ handler */ - s_sdifIsr = SDIF_TransferHandleIRQ; - - /* enable the global interrupt */ - SDIF_EnableGlobalInterrupt(base, true); - - (void)EnableIRQ(s_sdifIRQ[SDIF_GetInstance(base)]); -} - -/*! - * brief SDIF return the controller capability - * param base SDIF peripheral base address. - * param sdif capability pointer - */ -void SDIF_GetCapability(SDIF_Type *base, sdif_capability_t *capability) -{ - assert(NULL != capability); - - /* Initializes the configure structure to zero. */ - (void)memset(capability, 0, sizeof(*capability)); - - capability->sdVersion = SDIF_SUPPORT_SD_VERSION; - capability->mmcVersion = SDIF_SUPPORT_MMC_VERSION; - capability->maxBlockLength = SDIF_BLKSIZ_BLOCK_SIZE_MASK; - /* set the max block count = max byte count / max block size */ - capability->maxBlockCount = SDIF_BYTCNT_BYTE_COUNT_MASK / SDIF_BLKSIZ_BLOCK_SIZE_MASK; - capability->flags = (uint32_t)kSDIF_SupportHighSpeedFlag | (uint32_t)kSDIF_SupportDmaFlag | - (uint32_t)kSDIF_SupportSuspendResumeFlag | (uint32_t)kSDIF_SupportV330Flag | - (uint32_t)kSDIF_Support4BitFlag | (uint32_t)kSDIF_Support8BitFlag; -} - -static void SDIF_TransferHandleCommand(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags) -{ - assert(handle->command != NULL); - - /* cmd buffer full, in this condition user need re-send the command */ - if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_HardwareLockError)) - { - if (handle->callback.CommandReload != NULL) - { - handle->callback.CommandReload(base, handle->userData); - } - } - /* transfer command done */ - else - { - if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_CommandDone)) - { - /* transfer error */ - if ((IS_SDIF_FLAG_SET(interruptFlags, ((uint32_t)kSDIF_ResponseError | (uint32_t)kSDIF_ResponseCRCError | - (uint32_t)kSDIF_ResponseTimeout))) || - (SDIF_ReadCommandResponse(base, handle->command) != kStatus_Success)) - { - if (handle->callback.TransferComplete != NULL) - { - handle->callback.TransferComplete(base, handle, kStatus_SDIF_SendCmdFail, handle->userData); - } - } - else - { - if (handle->callback.TransferComplete != NULL) - { - handle->callback.TransferComplete(base, handle, kStatus_SDIF_SendCmdSuccess, handle->userData); - } - } - } - } - - SDIF_DisableInterrupt(base, kSDIF_CommandTransferStatus); - handle->command = NULL; -} - -static void SDIF_TransferHandleData(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags) -{ - assert(handle->data != NULL); - - status_t transferStatus = kStatus_SDIF_BusyTransferring; - uint32_t transferredWords = handle->transferredWords; - - /* data starvation by host time out, software should read/write FIFO*/ - if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_DataStarvationByHostTimeout)) - { - if (handle->data->rxData != NULL) - { - handle->transferredWords = SDIF_ReadDataPort(base, handle->data, transferredWords); - } - else if (handle->data->txData != NULL) - { - handle->transferredWords = SDIF_WriteDataPort(base, handle->data, transferredWords); - } - else - { - transferStatus = kStatus_SDIF_DataTransferFail; - } - } - /* data transfer fail */ - else if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_DataTransferError)) - { - if (!handle->data->enableIgnoreError) - { - transferStatus = kStatus_SDIF_DataTransferFail; - } - else - { - transferStatus = kStatus_SDIF_DataTransferSuccess; - } - } - /* need fill data to FIFO */ - else if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_WriteFIFORequest)) - { - handle->transferredWords = SDIF_WriteDataPort(base, handle->data, transferredWords); - } - /* need read data from FIFO */ - else if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_ReadFIFORequest)) - { - handle->transferredWords = SDIF_ReadDataPort(base, handle->data, transferredWords); - } - else - { - /* Intentional empty */ - } - - /* data transfer over */ - if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_DataTransferOver)) - { - while ((handle->data->rxData != NULL) && ((base->STATUS & SDIF_STATUS_FIFO_COUNT_MASK) != 0UL)) - { - handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords); - } - transferStatus = kStatus_SDIF_DataTransferSuccess; - } - - if ((handle->callback.TransferComplete != NULL) && (transferStatus != kStatus_SDIF_BusyTransferring)) - { - handle->callback.TransferComplete(base, handle, transferStatus, handle->userData); - handle->data = NULL; - } -} - -static void SDIF_TransferHandleDMA(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags) -{ - status_t transferStatus = kStatus_SDIF_DataTransferFail; - - if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_DMAFatalBusError)) - { - transferStatus = kStatus_SDIF_DMATransferFailWithFBE; - } - else if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_DMADescriptorUnavailable)) - { - if (handle->callback.DMADesUnavailable != NULL) - { - handle->callback.DMADesUnavailable(base, handle->userData); - } - } - else if (IS_SDIF_FLAG_SET(interruptFlags, - ((uint32_t)kSDIF_AbnormalInterruptSummary | (uint32_t)kSDIF_DMACardErrorSummary)) && - (!handle->data->enableIgnoreError)) - { - transferStatus = kStatus_SDIF_DataTransferFail; - } - /* card normal summary */ - else - { - transferStatus = kStatus_SDIF_DataTransferSuccess; - } - - if (handle->callback.TransferComplete != NULL) - { - handle->callback.TransferComplete(base, handle, transferStatus, handle->userData); - handle->data = NULL; - } - - SDIF_DisableDmaInterrupt(base, kSDIF_DMAAllStatus); -} - -static void SDIF_TransferHandleSDIOInterrupt(SDIF_Type *base, sdif_handle_t *handle) -{ - if (handle->callback.SDIOInterrupt != NULL) - { - handle->callback.SDIOInterrupt(base, handle->userData); - } -} - -static void SDIF_TransferHandleCardDetect(SDIF_Type *base, sdif_handle_t *handle) -{ - if (SDIF_DetectCardInsert(base, false) == 1UL) - { - if ((handle->callback.cardInserted) != NULL) - { - handle->callback.cardInserted(base, handle->userData); - } - } - else - { - if ((handle->callback.cardRemoved) != NULL) - { - handle->callback.cardRemoved(base, handle->userData); - } - } -} - -static void SDIF_TransferHandleIRQ(SDIF_Type *base, sdif_handle_t *handle) -{ - assert(handle != NULL); - - uint32_t interruptFlags, dmaInterruptFlags; - - interruptFlags = SDIF_GetEnabledInterruptStatus(base); - dmaInterruptFlags = SDIF_GetEnabledDMAInterruptStatus(base); - - if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_CommandTransferStatus)) - { - SDIF_TransferHandleCommand(base, handle, interruptFlags); - } - if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_DataTransferStatus)) - { - SDIF_TransferHandleData(base, handle, interruptFlags); - } - if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_SDIOInterrupt)) - { - SDIF_TransferHandleSDIOInterrupt(base, handle); - } - if (IS_SDIF_FLAG_SET(dmaInterruptFlags, kSDIF_DMAAllStatus)) - { - SDIF_TransferHandleDMA(base, handle, dmaInterruptFlags); - } - if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_CardDetect)) - { - SDIF_TransferHandleCardDetect(base, handle); - } - - SDIF_ClearInterruptStatus(base, interruptFlags); - SDIF_ClearInternalDMAStatus(base, dmaInterruptFlags); -} - -/*! - * brief SDIF module deinit function. - * user should call this function follow with IP reset - * param base SDIF peripheral base address. - */ -void SDIF_Deinit(SDIF_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(kCLOCK_Sdio); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* disable the SDIOCLKCTRL */ - SYSCON->SDIOCLKCTRL &= ~(SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kSDIO_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -} - -#if defined(SDIF) -void SDIF_DriverIRQHandler(void); -void SDIF_DriverIRQHandler(void) -{ - assert(s_sdifHandle[0] != NULL); - - s_sdifIsr(SDIF, s_sdifHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_sdif.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_sdif.h deleted file mode 100644 index 9c1a7ea5b64..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_sdif.h +++ /dev/null @@ -1,1035 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SDIF_H_ -#define _FSL_SDIF_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup sdif - * @{ - */ - -/********************************** - * Definitions. - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Driver version 2.0.15. */ -#define FSL_SDIF_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 0U)) -/*@}*/ - -/*! @brief SDIOCLKCTRL setting - * Below clock delay setting should depend on specific platform, so - * it can be redefined when timing mismatch issue occur. - * Such as: response error/CRC error and so on - */ -/*! @brief clock range value which need to add delay to avoid timing issue */ -#ifndef SDIF_CLOCK_RANGE_NEED_DELAY -#define SDIF_CLOCK_RANGE_NEED_DELAY (50000000U) -#endif - -/* - * Fixed delay configuration - * min hold time:2ns - * min setup time: 6ns - * delay = (x+1)*250ps - */ -/*! @brief High speed mode clk_sample fixed delay*/ -#ifndef SDIF_HIGHSPEED_SAMPLE_DELAY -#define SDIF_HIGHSPEED_SAMPLE_DELAY (12U) /*!< 12 * 250ps = 3ns */ -#endif -/*! @brief High speed mode clk_drv fixed delay */ -#ifndef SDIF_HIGHSPEED_DRV_DELAY -#define SDIF_HIGHSPEED_DRV_DELAY (31U) /*!< 31 * 250ps = 7.75ns */ -#endif - -/* - * Phase shift delay configuration - * 0 degree: no delay - * 90 degree: 0.25/source clk value - * 180 degree: 0.50/source clk value - * 270 degree: 0.75/source clk value - */ -/*! @brief High speed mode clk_sample phase shift */ -#ifndef SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT -#define SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT (0U) -#endif -/*! @brief High speed mode clk_drv phase shift */ -#ifndef SDIF_HIGHSPEED_DRV_PHASE_SHIFT -#define SDIF_HIGHSPEED_DRV_PHASE_SHIFT (1U) /* 90 degrees clk_drv phase delay */ -#endif -/*! @brief default mode sample fixed delay */ -#ifndef SDIF_DEFAULT_MODE_SAMPLE_DELAY -#define SDIF_DEFAULT_MODE_SAMPLE_DELAY (12U) /*!< 12 * 250ps = 3ns */ -#endif - -#ifndef SDIF_DEFAULT_MODE_DRV_DELAY -#define SDIF_DEFAULT_MODE_DRV_DELAY (31U) /*!< 31 * 250ps = 7.75ns */ -#endif - -/*! @brief SDIF internal DMA descriptor address and the data buffer address align */ -#define SDIF_INTERNAL_DMA_ADDR_ALIGN (4U) -/*! @brief SDIF DMA descriptor flag */ -#define SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG (1UL << 1U) -#define SDIF_DMA_DESCRIPTOR_DATA_BUFFER_END_FLAG (1UL << 2U) -#define SDIF_DMA_DESCRIPTOR_DATA_BUFFER_START_FLAG (1UL << 3U) -#define SDIF_DMA_DESCRIPTOR_SECOND_ADDR_CHAIN_FLAG (1UL << 4U) -#define SDIF_DMA_DESCRIPTOR_DESCRIPTOR_END_FLAG (1UL << 5U) -#define SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG (1UL << 31U) - -/*! @brief _sdif_status SDIF status */ -enum -{ - kStatus_SDIF_DescriptorBufferLenError = MAKE_STATUS(kStatusGroup_SDIF, 0U), /*!< Set DMA descriptor failed */ - kStatus_SDIF_InvalidArgument = MAKE_STATUS(kStatusGroup_SDIF, 1U), /*!< invalid argument status */ - kStatus_SDIF_SyncCmdTimeout = MAKE_STATUS(kStatusGroup_SDIF, 2U), /*!< sync command to CIU timeout status */ - kStatus_SDIF_SendCmdFail = MAKE_STATUS(kStatusGroup_SDIF, 3U), /*!< send command to card fail */ - kStatus_SDIF_SendCmdErrorBufferFull = - MAKE_STATUS(kStatusGroup_SDIF, 4U), /*!< send command to card fail, due to command buffer full - user need to resend this command */ - kStatus_SDIF_DMATransferFailWithFBE = - MAKE_STATUS(kStatusGroup_SDIF, 5U), /*!< DMA transfer data fail with fatal bus error , - to do with this error :issue a hard reset/controller reset*/ - kStatus_SDIF_DMATransferDescriptorUnavailable = - MAKE_STATUS(kStatusGroup_SDIF, 6U), /*!< DMA descriptor unavailable */ - kStatus_SDIF_DataTransferFail = MAKE_STATUS(kStatusGroup_SDIF, 6U), /*!< transfer data fail */ - kStatus_SDIF_ResponseError = MAKE_STATUS(kStatusGroup_SDIF, 7U), /*!< response error */ - kStatus_SDIF_DMAAddrNotAlign = MAKE_STATUS(kStatusGroup_SDIF, 8U), /*!< DMA address not align */ - kStatus_SDIF_BusyTransferring = MAKE_STATUS(kStatusGroup_SDIF, 9U), /*!< SDIF transfer busy status */ - kStatus_SDIF_DataTransferSuccess = MAKE_STATUS(kStatusGroup_SDIF, 10U), /*!< transfer data success */ - kStatus_SDIF_SendCmdSuccess = MAKE_STATUS(kStatusGroup_SDIF, 11U), /*!< transfer command success */ - -}; - -/*! @brief _sdif_capability_flag Host controller capabilities flag mask */ -enum -{ - kSDIF_SupportHighSpeedFlag = 0x1U, /*!< Support high-speed */ - kSDIF_SupportDmaFlag = 0x2U, /*!< Support DMA */ - kSDIF_SupportSuspendResumeFlag = 0x4U, /*!< Support suspend/resume */ - kSDIF_SupportV330Flag = 0x8U, /*!< Support voltage 3.3V */ - kSDIF_Support4BitFlag = 0x10U, /*!< Support 4 bit mode */ - kSDIF_Support8BitFlag = 0x20U, /*!< Support 8 bit mode */ -}; - -/*! @brief _sdif_reset_type define the reset type */ -enum -{ - kSDIF_ResetController = SDIF_CTRL_CONTROLLER_RESET_MASK, /*!< reset controller,will reset: BIU/CIU interface - CIU and state machine,ABORT_READ_DATA,SEND_IRQ_RESPONSE - and READ_WAIT bits of control register,START_CMD bit of - the command register*/ - kSDIF_ResetFIFO = SDIF_CTRL_FIFO_RESET_MASK, /*!< reset data FIFO*/ - kSDIF_ResetDMAInterface = SDIF_CTRL_DMA_RESET_MASK, /*!< reset DMA interface */ - - kSDIF_ResetAll = kSDIF_ResetController | kSDIF_ResetFIFO | /*!< reset all*/ - kSDIF_ResetDMAInterface, -}; - -/*! @brief define the card bus width type */ -typedef enum _sdif_bus_width -{ - kSDIF_Bus1BitWidth = 0U, /*!< 1bit bus width, 1bit mode and 4bit mode - share one register bit */ - kSDIF_Bus4BitWidth = 1U, /*!< 4bit mode mask */ - kSDIF_Bus8BitWidth = 2U, /*!< support 8 bit mode */ -} sdif_bus_width_t; - -/*! @brief _sdif_command_flags define the command flags */ -enum -{ - kSDIF_CmdResponseExpect = SDIF_CMD_RESPONSE_EXPECT_MASK, /*!< command request response*/ - kSDIF_CmdResponseLengthLong = SDIF_CMD_RESPONSE_LENGTH_MASK, /*!< command response length long */ - kSDIF_CmdCheckResponseCRC = SDIF_CMD_CHECK_RESPONSE_CRC_MASK, /*!< request check command response CRC*/ - kSDIF_DataExpect = SDIF_CMD_DATA_EXPECTED_MASK, /*!< request data transfer,either read/write*/ - kSDIF_DataWriteToCard = SDIF_CMD_READ_WRITE_MASK, /*!< data transfer direction */ - kSDIF_DataStreamTransfer = SDIF_CMD_TRANSFER_MODE_MASK, /*!< data transfer mode :stream/block transfer command */ - kSDIF_DataTransferAutoStop = SDIF_CMD_SEND_AUTO_STOP_MASK, /*!< data transfer with auto stop at the end of */ - kSDIF_WaitPreTransferComplete = - SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK, /*!< wait pre transfer complete before sending this cmd */ - kSDIF_TransferStopAbort = SDIF_CMD_STOP_ABORT_CMD_MASK, /*!< when host issue stop or abort cmd to stop data transfer - ,this bit should set so that cmd/data state-machines of CIU - can return to idle correctly*/ - kSDIF_SendInitialization = - SDIF_CMD_SEND_INITIALIZATION_MASK, /*!< send initialization 80 clocks for SD card after power on */ - kSDIF_CmdUpdateClockRegisterOnly = - SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK, /*!< send cmd update the CIU clock register only */ - kSDIF_CmdtoReadCEATADevice = SDIF_CMD_READ_CEATA_DEVICE_MASK, /*!< host is perform read access to CE-ATA device */ - kSDIF_CmdExpectCCS = SDIF_CMD_CCS_EXPECTED_MASK, /*!< command expect command completion signal signal */ - kSDIF_BootModeEnable = SDIF_CMD_ENABLE_BOOT_MASK, /*!< this bit should only be set for mandatory boot mode */ - kSDIF_BootModeExpectAck = SDIF_CMD_EXPECT_BOOT_ACK_MASK, /*!< boot mode expect ack */ - kSDIF_BootModeDisable = SDIF_CMD_DISABLE_BOOT_MASK, /*!< when software set this bit along with START_CMD, CIU - terminates the boot operation*/ - kSDIF_BootModeAlternate = SDIF_CMD_BOOT_MODE_MASK, /*!< select boot mode ,alternate or mandatory*/ - kSDIF_CmdVoltageSwitch = SDIF_CMD_VOLT_SWITCH_MASK, /*!< this bit set for CMD11 only */ - kSDIF_CmdDataUseHoldReg = SDIF_CMD_USE_HOLD_REG_MASK, /*!< cmd and data send to card through the HOLD register*/ -}; - -/*! @brief _sdif_command_type The command type */ -enum -{ - kCARD_CommandTypeNormal = 0U, /*!< Normal command */ - kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */ - kCARD_CommandTypeResume = 2U, /*!< Resume command */ - kCARD_CommandTypeAbort = 3U, /*!< Abort command */ -}; - -/*! - * @brief _sdif_response_type The command response type. - * - * Define the command response type from card to host controller. - */ -enum -{ - kCARD_ResponseTypeNone = 0U, /*!< Response type: none */ - kCARD_ResponseTypeR1 = 1U, /*!< Response type: R1 */ - kCARD_ResponseTypeR1b = 2U, /*!< Response type: R1b */ - kCARD_ResponseTypeR2 = 3U, /*!< Response type: R2 */ - kCARD_ResponseTypeR3 = 4U, /*!< Response type: R3 */ - kCARD_ResponseTypeR4 = 5U, /*!< Response type: R4 */ - kCARD_ResponseTypeR5 = 6U, /*!< Response type: R5 */ - kCARD_ResponseTypeR5b = 7U, /*!< Response type: R5b */ - kCARD_ResponseTypeR6 = 8U, /*!< Response type: R6 */ - kCARD_ResponseTypeR7 = 9U, /*!< Response type: R7 */ -}; - -/*! @brief _sdif_interrupt_mask define the interrupt mask flags */ -enum -{ - kSDIF_CardDetect = SDIF_INTMASK_CDET_MASK, /*!< mask for card detect */ - kSDIF_ResponseError = SDIF_INTMASK_RE_MASK, /*!< command response error */ - kSDIF_CommandDone = SDIF_INTMASK_CDONE_MASK, /*!< command transfer over*/ - kSDIF_DataTransferOver = SDIF_INTMASK_DTO_MASK, /*!< data transfer over flag*/ - kSDIF_WriteFIFORequest = SDIF_INTMASK_TXDR_MASK, /*!< write FIFO request */ - kSDIF_ReadFIFORequest = SDIF_INTMASK_RXDR_MASK, /*!< read FIFO request */ - kSDIF_ResponseCRCError = SDIF_INTMASK_RCRC_MASK, /*!< response CRC error */ - kSDIF_DataCRCError = SDIF_INTMASK_DCRC_MASK, /*!< data CRC error */ - kSDIF_ResponseTimeout = SDIF_INTMASK_RTO_MASK, /*!< response timeout */ - kSDIF_DataReadTimeout = SDIF_INTMASK_DRTO_MASK, /*!< read data timeout */ - kSDIF_DataStarvationByHostTimeout = SDIF_INTMASK_HTO_MASK, /*!< data starvation by host time out */ - kSDIF_FIFOError = SDIF_INTMASK_FRUN_MASK, /*!< indicate the FIFO under run or overrun error */ - kSDIF_HardwareLockError = SDIF_INTMASK_HLE_MASK, /*!< hardware lock write error */ - kSDIF_DataStartBitError = SDIF_INTMASK_SBE_MASK, /*!< start bit error */ - kSDIF_AutoCmdDone = SDIF_INTMASK_ACD_MASK, /*!< indicate the auto command done */ - kSDIF_DataEndBitError = SDIF_INTMASK_EBE_MASK, /*!< end bit error */ - kSDIF_SDIOInterrupt = SDIF_INTMASK_SDIO_INT_MASK_MASK, /*!< interrupt from the SDIO card */ - - kSDIF_CommandTransferStatus = kSDIF_ResponseError | kSDIF_CommandDone | kSDIF_ResponseCRCError | - kSDIF_ResponseTimeout | kSDIF_DataStartBitError | - kSDIF_HardwareLockError, /*!< command transfer status collection*/ - kSDIF_DataTransferStatus = kSDIF_DataTransferOver | kSDIF_WriteFIFORequest | kSDIF_ReadFIFORequest | - kSDIF_DataCRCError | kSDIF_DataReadTimeout | kSDIF_DataStarvationByHostTimeout | - kSDIF_FIFOError | kSDIF_DataStartBitError | - kSDIF_DataEndBitError, /*!< data transfer status collection */ - kSDIF_DataTransferError = - kSDIF_DataCRCError | kSDIF_FIFOError | kSDIF_DataStartBitError | kSDIF_DataEndBitError | kSDIF_DataReadTimeout, - kSDIF_AllInterruptStatus = 0x1FFFFU, /*!< all interrupt mask */ - -}; - -/*! @brief _sdif_dma_status define the internal DMA status flags */ -enum -{ - kSDIF_DMATransFinishOneDescriptor = SDIF_IDSTS_TI_MASK, /*!< DMA transfer finished for one DMA descriptor */ - kSDIF_DMARecvFinishOneDescriptor = SDIF_IDSTS_RI_MASK, /*!< DMA receive finished for one DMA descriptor */ - kSDIF_DMAFatalBusError = SDIF_IDSTS_FBE_MASK, /*!< DMA fatal bus error */ - kSDIF_DMADescriptorUnavailable = SDIF_IDSTS_DU_MASK, /*!< DMA descriptor unavailable */ - kSDIF_DMACardErrorSummary = SDIF_IDSTS_CES_MASK, /*!< card error summary */ - kSDIF_NormalInterruptSummary = SDIF_IDSTS_NIS_MASK, /*!< normal interrupt summary */ - kSDIF_AbnormalInterruptSummary = SDIF_IDSTS_AIS_MASK, /*!< abnormal interrupt summary*/ - - kSDIF_DMAAllStatus = kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor | kSDIF_DMAFatalBusError | - kSDIF_DMADescriptorUnavailable | kSDIF_DMACardErrorSummary | kSDIF_NormalInterruptSummary | - kSDIF_AbnormalInterruptSummary, - -}; - -/*! @brief _sdif_dma_descriptor_flag define the internal DMA descriptor flag - * @deprecated Do not use this enum anymore, please use SDIF_DMA_DESCRIPTOR_XXX_FLAG instead. - */ -enum -{ - kSDIF_DisableCompleteInterrupt = 0x2U, /*!< disable the complete interrupt flag for the ends - in the buffer pointed to by this descriptor*/ - kSDIF_DMADescriptorDataBufferEnd = 0x4U, /*!< indicate this descriptor contain the last data buffer of data */ - kSDIF_DMADescriptorDataBufferStart = 0x8U, /*!< indicate this descriptor contain the first data buffer - of data,if first buffer size is 0,next descriptor contain - the begin of the data*/ - - kSDIF_DMASecondAddrChained = 0x10U, /*!< indicate that the second addr in the descriptor is the - next descriptor addr not the data buffer */ - kSDIF_DMADescriptorEnd = 0x20U, /*!< indicate that the descriptor list reached its final descriptor*/ - kSDIF_DMADescriptorOwnByDMA = (int)0x80000000, /*!< indicate the descriptor is own by SD/MMC DMA */ -}; - -/*! @brief define the internal DMA mode */ -typedef enum _sdif_dma_mode -{ - kSDIF_ChainDMAMode = 0x01U, /* one descriptor with one buffer,but one descriptor point to another */ - kSDIF_DualDMAMode = 0x02U, /* dual mode is one descriptor with two buffer */ -} sdif_dma_mode_t; - -/*! @brief define the internal DMA descriptor */ -typedef struct _sdif_dma_descriptor -{ - uint32_t dmaDesAttribute; /*!< internal DMA attribute control and status */ - uint32_t dmaDataBufferSize; /*!< internal DMA transfer buffer size control */ - const uint32_t *dmaDataBufferAddr0; /*!< internal DMA buffer 0 addr ,the buffer size must be 32bit aligned */ - const uint32_t *dmaDataBufferAddr1; /*!< internal DMA buffer 1 addr ,the buffer size must be 32bit aligned */ - -} sdif_dma_descriptor_t; - -/*! @brief Defines the internal DMA configure structure. */ -typedef struct _sdif_dma_config -{ - bool enableFixBurstLen; /*!< fix burst len enable/disable flag,When set, the AHB will - use only SINGLE, INCR4, INCR8 or INCR16 during start of - normal burst transfers. When reset, the AHB will use SINGLE - and INCR burst transfer operations */ - - sdif_dma_mode_t mode; /*!< define the DMA mode */ - - uint8_t dmaDesSkipLen; /*!< define the descriptor skip length ,the length between two descriptor - this field is special for dual DMA mode */ - - uint32_t *dmaDesBufferStartAddr; /*!< internal DMA descriptor start address*/ - uint32_t dmaDesBufferLen; /*!< internal DMA buffer descriptor buffer len ,user need to pay attention to the - dma descriptor buffer length if it is bigger enough for your transfer */ - -} sdif_dma_config_t; - -/*! - * @brief Card data descriptor - */ -typedef struct _sdif_data -{ - bool streamTransfer; /*!< indicate this is a stream data transfer command */ - bool enableAutoCommand12; /*!< indicate if auto stop will send when data transfer over */ - bool enableIgnoreError; /*!< indicate if enable ignore error when transfer data */ - - size_t blockSize; /*!< Block size, take care when configure this parameter */ - uint32_t blockCount; /*!< Block count */ - uint32_t *rxData; /*!< data buffer to receive */ - const uint32_t *txData; /*!< data buffer to transfer */ -} sdif_data_t; - -/*! - * @brief Card command descriptor - * - * Define card command-related attribute. - */ -typedef struct _sdif_command -{ - uint32_t index; /*!< Command index */ - uint32_t argument; /*!< Command argument */ - uint32_t response[4U]; /*!< Response for this command */ - uint32_t type; /*!< define the command type */ - uint32_t responseType; /*!< Command response type */ - uint32_t flags; /*!< Cmd flags */ - uint32_t responseErrorFlags; /*!< response error flags, need to check the flags when - receive the cmd response */ -} sdif_command_t; - -/*! @brief Transfer state */ -typedef struct _sdif_transfer -{ - sdif_data_t *data; /*!< Data to transfer */ - sdif_command_t *command; /*!< Command to send */ -} sdif_transfer_t; - -/*! @brief Data structure to initialize the sdif */ -typedef struct _sdif_config -{ - uint8_t responseTimeout; /*!< command response timeout value */ - uint32_t cardDetDebounce_Clock; /*!< define the debounce clock count which will used in - card detect logic,typical value is 5-25ms */ - uint32_t dataTimeout; /*!< data timeout value */ -} sdif_config_t; - -/*! - * @brief SDIF capability information. - * Defines a structure to get the capability information of SDIF. - */ -typedef struct _sdif_capability -{ - uint32_t sdVersion; /*!< support SD card/sdio version */ - uint32_t mmcVersion; /*!< support emmc card version */ - uint32_t maxBlockLength; /*!< Maximum block length united as byte */ - uint32_t maxBlockCount; /*!< Maximum byte count can be transfered */ - uint32_t flags; /*!< Capability flags to indicate the support information */ -} sdif_capability_t; - -/*! @brief sdif callback functions. */ -typedef struct _sdif_transfer_callback -{ - void (*cardInserted)(SDIF_Type *base, void *userData); /*!< card insert call back */ - void (*cardRemoved)(SDIF_Type *base, void *userData); /*!< card remove call back */ - void (*SDIOInterrupt)(SDIF_Type *base, void *userData); /*!< SDIO card interrupt occurs */ - void (*DMADesUnavailable)(SDIF_Type *base, void *userData); /*!< DMA descriptor unavailable */ - void (*CommandReload)(SDIF_Type *base, void *userData); /*!< command buffer full,need re-load */ - void (*TransferComplete)(SDIF_Type *base, - void *handle, - status_t status, - void *userData); /*!< Transfer complete callback */ -} sdif_transfer_callback_t; - -/*! - * @brief sdif handle - * - * Defines the structure to save the sdif state information and callback function. The detail interrupt status when - * send command or transfer data can be obtained from interruptFlags field by using mask defined in - * sdif_interrupt_flag_t; - * @note All the fields except interruptFlags and transferredWords must be allocated by the user. - */ -typedef struct _sdif_handle -{ - /* Transfer parameter */ - sdif_data_t *volatile data; /*!< Data to transfer */ - sdif_command_t *volatile command; /*!< Command to send */ - - /* Transfer status */ - volatile uint32_t transferredWords; /*!< Words transferred by polling way */ - - /* Callback functions */ - sdif_transfer_callback_t callback; /*!< Callback function */ - void *userData; /*!< Parameter for transfer complete callback */ -} sdif_handle_t; - -/*! @brief sdif transfer function. */ -typedef status_t (*sdif_transfer_function_t)(SDIF_Type *base, sdif_transfer_t *content); - -/*! @brief sdif host descriptor */ -typedef struct _sdif_host -{ - SDIF_Type *base; /*!< sdif peripheral base address */ - uint32_t sourceClock_Hz; /*!< sdif source clock frequency united in Hz */ - sdif_config_t config; /*!< sdif configuration */ - sdif_transfer_function_t transfer; /*!< sdif transfer function */ - sdif_capability_t capability; /*!< sdif capability information */ -} sdif_host_t; - -/************************************************************************************************* - * API - ************************************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief SDIF module initialization function. - * - * Configures the SDIF according to the user configuration. - * @param base SDIF peripheral base address. - * @param config SDIF configuration information. - */ -void SDIF_Init(SDIF_Type *base, sdif_config_t *config); - -/*! - * @brief SDIF module deinit function. - * user should call this function follow with IP reset - * @param base SDIF peripheral base address. - */ -void SDIF_Deinit(SDIF_Type *base); - -/*! - * @brief SDIF send initialize 80 clocks for SD card after initial - * @param base SDIF peripheral base address. - * @param timeout timeout value - */ -bool SDIF_SendCardActive(SDIF_Type *base, uint32_t timeout); - -#if defined(FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD) && FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD -/*! - * @brief SDIF module enable/disable card0 clock. - * @param base SDIF peripheral base address. - * @param enable enable/disable flag - */ -static inline void SDIF_EnableCardClock(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CLKENA |= SDIF_CLKENA_CCLK0_ENABLE_MASK; - } - else - { - base->CLKENA &= SDIF_CLKENA_CCLK0_ENABLE_MASK; - } -} - -/*! - * @brief SDIF module enable/disable card1 clock. - * @param base SDIF peripheral base address. - * @param enable enable/disable flag - */ -static inline void SDIF_EnableCard1Clock(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CLKENA |= SDIF_CLKENA_CCLK1_ENABLE_MASK; - } - else - { - base->CLKENA &= ~SDIF_CLKENA_CCLK1_ENABLE_MASK; - } -} - -/*! - * @brief SDIF module enable/disable module disable the card clock - * to enter low power mode when card is idle,for SDIF cards, if - * interrupts must be detected, clock should not be stopped - * @param base SDIF peripheral base address. - * @param enable enable/disable flag - */ -static inline void SDIF_EnableLowPowerMode(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CLKENA |= SDIF_CLKENA_CCLK0_LOW_POWER_MASK; - } - else - { - base->CLKENA &= ~SDIF_CLKENA_CCLK0_LOW_POWER_MASK; - } -} - -/*! - * @brief SDIF module enable/disable module disable the card clock - * to enter low power mode when card is idle,for SDIF cards, if - * interrupts must be detected, clock should not be stopped - * @param base SDIF peripheral base address. - * @param enable enable/disable flag - */ -static inline void SDIF_EnableCard1LowPowerMode(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CLKENA |= SDIF_CLKENA_CCLK1_LOW_POWER_MASK; - } - else - { - base->CLKENA &= ~SDIF_CLKENA_CCLK1_LOW_POWER_MASK; - } -} - -/*! - * @brief enable/disable the card0 power. - * once turn power on, software should wait for regulator/switch - * ramp-up time before trying to initialize card. - * @param base SDIF peripheral base address. - * @param enable enable/disable flag. - */ -static inline void SDIF_EnableCardPower(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->PWREN |= SDIF_PWREN_POWER_ENABLE0_MASK; - } - else - { - base->PWREN &= ~SDIF_PWREN_POWER_ENABLE0_MASK; - } -} - -/*! - * @brief enable/disable the card1 power. - * once turn power on, software should wait for regulator/switch - * ramp-up time before trying to initialize card. - * @param base SDIF peripheral base address. - * @param enable enable/disable flag. - */ -static inline void SDIF_EnableCard1Power(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->PWREN |= SDIF_PWREN_POWER_ENABLE1_MASK; - } - else - { - base->PWREN &= ~SDIF_PWREN_POWER_ENABLE1_MASK; - } -} - -/*! - * @brief set card0 data bus width - * @param base SDIF peripheral base address. - * @param type data bus width type - */ -void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type); - -/*! - * @brief set card1 data bus width - * @param base SDIF peripheral base address. - * @param type data bus width type - */ -void SDIF_SetCard1BusWidth(SDIF_Type *base, sdif_bus_width_t type); - -/*! - * @brief SDIF module detect card0 insert status function. - * @param base SDIF peripheral base address. - * @param data3 indicate use data3 as card insert detect pin - * @retval 1 card is inserted - * 0 card is removed - */ -static inline uint32_t SDIF_DetectCardInsert(SDIF_Type *base, bool data3) -{ - if (data3) - { - return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1UL : 0UL; - } - else - { - return (base->CDETECT & SDIF_CDETECT_CARD0_DETECT_MASK) == 0UL ? 1UL : 0UL; - } -} - -/*! - * @brief SDIF module detect card1 insert status function. - * @param base SDIF peripheral base address. - * @param data3 indicate use data3 as card insert detect pin - * @retval 1 card is inserted - * 0 card is removed - */ -static inline uint32_t SDIF_DetectCard1Insert(SDIF_Type *base, bool data3) -{ - if (data3) - { - return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1UL : 0UL; - } - else - { - return (base->CDETECT & SDIF_CDETECT_CARD1_DETECT_MASK) == 0UL ? 1UL : 0UL; - } -} -#else -/*! - * @brief SDIF module enable/disable card clock. - * @param base SDIF peripheral base address. - * @param enable enable/disable flag - */ -static inline void SDIF_EnableCardClock(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CLKENA |= SDIF_CLKENA_CCLK_ENABLE_MASK; - } - else - { - base->CLKENA &= ~SDIF_CLKENA_CCLK_ENABLE_MASK; - } -} - -/*! - * @brief SDIF module enable/disable module disable the card clock - * to enter low power mode when card is idle,for SDIF cards, if - * interrupts must be detected, clock should not be stopped - * @param base SDIF peripheral base address. - * @param enable enable/disable flag - */ -static inline void SDIF_EnableLowPowerMode(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CLKENA |= SDIF_CLKENA_CCLK_LOW_POWER_MASK; - } - else - { - base->CLKENA &= ~SDIF_CLKENA_CCLK_LOW_POWER_MASK; - } -} - -/*! - * @brief enable/disable the card power. - * once turn power on, software should wait for regulator/switch - * ramp-up time before trying to initialize card. - * @param base SDIF peripheral base address. - * @param enable enable/disable flag. - */ -static inline void SDIF_EnableCardPower(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->PWREN |= SDIF_PWREN_POWER_ENABLE_MASK; - } - else - { - base->PWREN &= ~SDIF_PWREN_POWER_ENABLE_MASK; - } -} - -/*! - * @brief set card data bus width - * @param base SDIF peripheral base address. - * @param type bus width type - */ -void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type); - -/*! - * @brief SDIF module detect card insert status function. - * @param base SDIF peripheral base address. - * @param data3 indicate use data3 as card insert detect pin - * @retval 1 card is inserted - * 0 card is removed - */ -static inline uint32_t SDIF_DetectCardInsert(SDIF_Type *base, bool data3) -{ - if (data3) - { - return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1UL : 0UL; - } - else - { - return (base->CDETECT & SDIF_CDETECT_CARD_DETECT_MASK) == 0UL ? 1UL : 0UL; - } -} -#endif - -/*! - * @brief Sets the card bus clock frequency. - * - * @param base SDIF peripheral base address. - * @param srcClock_Hz SDIF source clock frequency united in Hz. - * @param target_HZ card bus clock frequency united in Hz. - * @return The nearest frequency of busClock_Hz configured to SD bus. - */ -uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t target_HZ); - -/*! - * @brief reset the different block of the interface. - * @param base SDIF peripheral base address. - * @param mask indicate which block to reset. - * @param timeout timeout value,set to wait the bit self clear - * @return reset result. - */ -bool SDIF_Reset(SDIF_Type *base, uint32_t mask, uint32_t timeout); - -/*! - * @brief get the card write protect status - * @param base SDIF peripheral base address. - */ -static inline uint32_t SDIF_GetCardWriteProtect(SDIF_Type *base) -{ - return base->WRTPRT & SDIF_WRTPRT_WRITE_PROTECT_MASK; -} - -/*! - * @brief toggle state on hardware reset PIN - * This is used which card has a reset PIN typically. - * @param base SDIF peripheral base address. - */ -static inline void SDIF_AssertHardwareReset(SDIF_Type *base) -{ - base->RST_N &= ~SDIF_RST_N_CARD_RESET_MASK; -} - -/*! - * @brief send command to the card - * - * This api include polling the status of the bit START_COMMAND, if 0 used as timeout value, then this function - * will return directly without polling the START_CMD status. - * @param base SDIF peripheral base address. - * @param cmd configuration collection - * @param timeout the timeout value of polling START_CMD auto clear status. - * @return command excute status - */ -status_t SDIF_SendCommand(SDIF_Type *base, sdif_command_t *cmd, uint32_t timeout); - -/*! - * @brief SDIF enable/disable global interrupt - * @param base SDIF peripheral base address. - * @param enable enable/disable flag - */ -static inline void SDIF_EnableGlobalInterrupt(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= SDIF_CTRL_INT_ENABLE_MASK; - } - else - { - base->CTRL &= ~SDIF_CTRL_INT_ENABLE_MASK; - } -} - -/*! - * @brief SDIF enable interrupt - * @param base SDIF peripheral base address. - * @param mask mask - */ -static inline void SDIF_EnableInterrupt(SDIF_Type *base, uint32_t mask) -{ - base->INTMASK |= mask; -} - -/*! - * @brief SDIF disable interrupt - * @param base SDIF peripheral base address. - * @param mask mask - */ -static inline void SDIF_DisableInterrupt(SDIF_Type *base, uint32_t mask) -{ - base->INTMASK &= ~mask; -} - -/*! - * @brief SDIF get interrupt status - * @param base SDIF peripheral base address. - */ -static inline uint32_t SDIF_GetInterruptStatus(SDIF_Type *base) -{ - return base->MINTSTS; -} - -/*! - * @brief SDIF get enabled interrupt status - * @param base SDIF peripheral base address. - */ -static inline uint32_t SDIF_GetEnabledInterruptStatus(SDIF_Type *base) -{ - uint32_t intStatus = base->MINTSTS; - - return intStatus & base->INTMASK; -} - -/*! - * @brief SDIF clear interrupt status - * @param base SDIF peripheral base address. - * @param mask mask to clear - */ -static inline void SDIF_ClearInterruptStatus(SDIF_Type *base, uint32_t mask) -{ - base->RINTSTS &= mask; -} - -/*! - * @brief Creates the SDIF handle. - * register call back function for interrupt and enable the interrupt - * @param base SDIF peripheral base address. - * @param handle SDIF handle pointer. - * @param callback Structure pointer to contain all callback functions. - * @param userData Callback function parameter. - */ -void SDIF_TransferCreateHandle(SDIF_Type *base, - sdif_handle_t *handle, - sdif_transfer_callback_t *callback, - void *userData); - -/*! - * @brief SDIF enable DMA interrupt - * @param base SDIF peripheral base address. - * @param mask mask to set - */ -static inline void SDIF_EnableDmaInterrupt(SDIF_Type *base, uint32_t mask) -{ - base->IDINTEN |= mask; -} - -/*! - * @brief SDIF disable DMA interrupt - * @param base SDIF peripheral base address. - * @param mask mask to clear - */ -static inline void SDIF_DisableDmaInterrupt(SDIF_Type *base, uint32_t mask) -{ - base->IDINTEN &= ~mask; -} - -/*! - * @brief SDIF get internal DMA status - * @param base SDIF peripheral base address. - * @return the internal DMA status register - */ -static inline uint32_t SDIF_GetInternalDMAStatus(SDIF_Type *base) -{ - return base->IDSTS; -} - -/*! - * @brief SDIF get enabled internal DMA interrupt status - * @param base SDIF peripheral base address. - * @return the internal DMA status register - */ -static inline uint32_t SDIF_GetEnabledDMAInterruptStatus(SDIF_Type *base) -{ - uint32_t intStatus = base->IDSTS; - - return intStatus & base->IDINTEN; -} -/*! - * @brief SDIF clear internal DMA status - * @param base SDIF peripheral base address. - * @param mask mask to clear - */ -static inline void SDIF_ClearInternalDMAStatus(SDIF_Type *base, uint32_t mask) -{ - base->IDSTS &= mask; -} - -/*! - * @brief SDIF internal DMA config function - * @param base SDIF peripheral base address. - * @param config DMA configuration collection - * @param data buffer pointer - * @param dataSize buffer size - */ -status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, const uint32_t *data, uint32_t dataSize); - -/*! - * @brief SDIF internal DMA enable - * @param base SDIF peripheral base address. - * @param enable internal DMA enable or disable flag. - */ -static inline void SDIF_EnableInternalDMA(SDIF_Type *base, bool enable) -{ - if (enable) - { - /* use internal DMA interface */ - base->CTRL |= SDIF_CTRL_USE_INTERNAL_DMAC_MASK; - /* enable the internal SD/MMC DMA */ - base->BMOD |= SDIF_BMOD_DE_MASK; - } - else - { - /* use internal DMA interface */ - base->CTRL &= ~SDIF_CTRL_USE_INTERNAL_DMAC_MASK; - /* enable the internal SD/MMC DMA */ - base->BMOD &= ~SDIF_BMOD_DE_MASK; - } -} - -/*! - * @brief SDIF send read wait to SDIF card function - * @param base SDIF peripheral base address. - */ -static inline void SDIF_SendReadWait(SDIF_Type *base) -{ - base->CTRL |= SDIF_CTRL_READ_WAIT_MASK; -} - -/*! - * @brief SDIF abort the read data when SDIF card is in suspend state - * Once assert this bit,data state machine will be reset which is waiting for the - * next blocking data,used in SDIO card suspend sequence,should call after suspend - * cmd send - * @param base SDIF peripheral base address. - * @param timeout timeout value to wait this bit self clear which indicate the data machine - * reset to idle - */ -bool SDIF_AbortReadData(SDIF_Type *base, uint32_t timeout); - -/*! - * @brief SDIF enable/disable CE-ATA card interrupt - * this bit should set together with the card register - * @param base SDIF peripheral base address. - * @param enable enable/disable flag - */ -static inline void SDIF_EnableCEATAInterrupt(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK; - } - else - { - base->CTRL &= ~SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK; - } -} - -/*! - * @brief SDIF transfer function data/cmd in a non-blocking way - * this API should be use in interrupt mode, when use this API user - * must call SDIF_TransferCreateHandle first, all status check through - * interrupt - * @param base SDIF peripheral base address. - * @param handle handle - * @param dmaConfig config structure - * This parameter can be config as: - * 1. NULL - In this condition, polling transfer mode is selected - 2. avaliable DMA config - In this condition, DMA transfer mode is selected - * @param transfer transfer configuration collection - */ -status_t SDIF_TransferNonBlocking(SDIF_Type *base, - sdif_handle_t *handle, - sdif_dma_config_t *dmaConfig, - sdif_transfer_t *transfer); - -/*! - * @brief SDIF transfer function data/cmd in a blocking way - * @param base SDIF peripheral base address. - * @param dmaConfig config structure - * 1. NULL - * In this condition, polling transfer mode is selected - * 2. avaliable DMA config - * In this condition, DMA transfer mode is selected - * @param transfer transfer configuration collection - */ -status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sdif_transfer_t *transfer); - -/*! - * @brief SDIF release the DMA descriptor to DMA engine - * this function should be called when DMA descriptor unavailable status occurs - * @param base SDIF peripheral base address. - * @param dmaConfig DMA config pointer - */ -status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig); - -/*! - * @brief SDIF return the controller capability - * @param base SDIF peripheral base address. - * @param capability capability pointer - */ -void SDIF_GetCapability(SDIF_Type *base, sdif_capability_t *capability); - -/*! - * @brief SDIF return the controller status - * @param base SDIF peripheral base address. - */ -static inline uint32_t SDIF_GetControllerStatus(SDIF_Type *base) -{ - return base->STATUS; -} - -/*! - * @brief SDIF send command complete signal disable to CE-ATA card - * @param base SDIF peripheral base address. - * @param withAutoStop auto stop flag - */ -static inline void SDIF_SendCCSD(SDIF_Type *base, bool withAutoStop) -{ - if (withAutoStop) - { - base->CTRL |= SDIF_CTRL_SEND_CCSD_MASK | SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK; - } - else - { - base->CTRL |= SDIF_CTRL_SEND_CCSD_MASK; - } -} - -/*! - * @brief SDIF config the clock delay - * This function is used to config the cclk_in delay to - * sample and driver the data ,should meet the min setup - * time and hold time, and user need to config this parameter - * according to your board setting - * @param target_HZ freq work mode - * @param divider not used in this function anymore, use DELAY value instead of phase directly. - */ -void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider); - -/* @} */ - -#if defined(__cplusplus) -} -#endif -/*! @} */ - -#endif /* _FSL_sdif_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_spi.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_spi.c deleted file mode 100644 index 456361e6204..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_spi.c +++ /dev/null @@ -1,1072 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_spi.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi" -#endif - -/* Note: FIFOCFG[SIZE] has always value 1 = 8 items depth */ - -#if defined(FSL_FEATURE_SPI_FIFOSIZE_CFG) && (FSL_FEATURE_SPI_FIFOSIZE_CFG) -#define SPI_FIFO_DEPTH(base) 4 -#else -#define SPI_FIFO_DEPTH(base) ((((base)->FIFOCFG & SPI_FIFOCFG_SIZE_MASK) >> SPI_FIFOCFG_SIZE_SHIFT) << 3) -#endif /*FSL_FEATURE_SPI_FIFOSIZE_CFG*/ - -/* Convert transfer count to transfer bytes. dataWidth is a - * range <0,15>. Range <8,15> represents 2B transfer */ -#define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U)) -#define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U)) -#if defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) && (FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) -#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK)) -#else -#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK) | (SPI_CFG_SPOL3_MASK)) -#endif /*FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE*/ - -/*! - * @brief Used for conversion from `flexcomm_irq_handler_t` to `flexcomm_spi_master_irq_handler_t` and - * `flexcomm_spi_slave_irq_handler_t`. - */ -typedef union spi_to_flexcomm -{ - flexcomm_spi_master_irq_handler_t spi_master_handler; - flexcomm_spi_slave_irq_handler_t spi_slave_handler; - flexcomm_irq_handler_t flexcomm_handler; -} spi_to_flexcomm_t; - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief internal SPI config array */ -static spi_config_t g_configs[FSL_FEATURE_SOC_SPI_COUNT] = {(spi_data_width_t)0}; - -/*! @brief Array to map SPI instance number to base address. */ -static const uint32_t s_spiBaseAddrs[FSL_FEATURE_SOC_SPI_COUNT] = SPI_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_spiIRQ[] = SPI_IRQS; - -/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ -volatile uint8_t s_dummyData[FSL_FEATURE_SOC_SPI_COUNT] = {0}; -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Get the index corresponding to the FLEXCOMM */ -/*! brief Returns instance number for SPI peripheral base address. */ -uint32_t SPI_GetInstance(SPI_Type *base) -{ - uint32_t i; - - for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_SPI_COUNT; i++) - { - if ((uint32_t)base == s_spiBaseAddrs[i]) - { - break; - } - } - - assert(i < (uint32_t)FSL_FEATURE_SOC_SPI_COUNT); - return i; -} - -/*! - * brief Set up the dummy data. - * - * param base SPI peripheral address. - * param dummyData Data to be transferred when tx buffer is NULL. - */ -void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData) -{ - uint32_t instance = SPI_GetInstance(base); - s_dummyData[instance] = dummyData; -} - -/*! - * brief Returns the configurations. - * - * param base SPI peripheral address. - * return return configurations which contain datawidth and SSEL numbers. - * return data type is a pointer of spi_config_t. - */ -void *SPI_GetConfig(SPI_Type *base) -{ - uint32_t instance; - instance = SPI_GetInstance(base); - return &g_configs[instance]; -} - -/*! - * brief Sets the SPI master configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). - * User may use the initialized structure unchanged in SPI_MasterInit(), or modify - * some fields of the structure before calling SPI_MasterInit(). After calling this API, - * the master is ready to transfer. - * Example: - code - spi_master_config_t config; - SPI_MasterGetDefaultConfig(&config); - endcode - * - * param config pointer to master config structure - */ -void SPI_MasterGetDefaultConfig(spi_master_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enableLoopback = false; - config->enableMaster = true; - config->polarity = kSPI_ClockPolarityActiveHigh; - config->phase = kSPI_ClockPhaseFirstEdge; - config->direction = kSPI_MsbFirst; - config->baudRate_Bps = 500000U; - config->dataWidth = kSPI_Data8Bits; - config->sselNum = kSPI_Ssel0; - config->txWatermark = (uint8_t)kSPI_TxFifo0; - config->rxWatermark = (uint8_t)kSPI_RxFifo1; - config->sselPol = kSPI_SpolActiveAllLow; - config->delayConfig.preDelay = 0U; - config->delayConfig.postDelay = 0U; - config->delayConfig.frameDelay = 0U; - config->delayConfig.transferDelay = 0U; -} - -/*! - * brief Initializes the SPI with master configuration. - * - * The configuration structure can be filled by user from scratch, or be set with default - * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. - * Example - code - spi_master_config_t config = { - .baudRate_Bps = 400000, - ... - }; - SPI_MasterInit(SPI0, &config); - endcode - * - * param base SPI base pointer - * param config pointer to master configuration structure - * param srcClock_Hz Source clock frequency. - */ -status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz) -{ - status_t result = kStatus_Success; - uint32_t instance; - uint32_t tmpConfig; - - /* assert params */ - assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); - if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* initialize flexcomm to SPI mode */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); - if (kStatus_Success != result) - { - return result; - } - - /* set divider */ - result = SPI_MasterSetBaud(base, config->baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - - /* get instance number */ - instance = SPI_GetInstance(base); - - /* configure SPI mode */ - tmpConfig = base->CFG; - tmpConfig &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | - SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); - /* phase */ - tmpConfig |= SPI_CFG_CPHA(config->phase); - /* polarity */ - tmpConfig |= SPI_CFG_CPOL(config->polarity); - /* direction */ - tmpConfig |= SPI_CFG_LSBF(config->direction); - /* master mode */ - tmpConfig |= SPI_CFG_MASTER(1); - /* loopback */ - tmpConfig |= SPI_CFG_LOOP(config->enableLoopback); - /* configure active level for all CS */ - tmpConfig |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); - base->CFG = tmpConfig; - - /* store configuration */ - g_configs[instance].dataWidth = config->dataWidth; - g_configs[instance].sselNum = config->sselNum; - /* enable FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; - /* trigger level - empty txFIFO, one item in rxFIFO */ - tmpConfig = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); - tmpConfig |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable generating interrupts for FIFOTRIG levels */ - tmpConfig |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; - /* set FIFOTRIG */ - base->FIFOTRIG = tmpConfig; - - /* Set the delay configuration. */ - SPI_SetTransferDelay(base, &config->delayConfig); - /* Set the dummy data. */ - SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); - - SPI_Enable(base, config->enableMaster); - return kStatus_Success; -} - -/*! - * brief Sets the SPI slave configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). - * Modify some fields of the structure before calling SPI_SlaveInit(). - * Example: - code - spi_slave_config_t config; - SPI_SlaveGetDefaultConfig(&config); - endcode - * - * param config pointer to slave configuration structure - */ -void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enableSlave = true; - config->polarity = kSPI_ClockPolarityActiveHigh; - config->phase = kSPI_ClockPhaseFirstEdge; - config->direction = kSPI_MsbFirst; - config->dataWidth = kSPI_Data8Bits; - config->txWatermark = (uint8_t)kSPI_TxFifo0; - config->rxWatermark = (uint8_t)kSPI_RxFifo1; - config->sselPol = kSPI_SpolActiveAllLow; -} - -/*! - * brief Initializes the SPI with slave configuration. - * - * The configuration structure can be filled by user from scratch or be set with - * default values by SPI_SlaveGetDefaultConfig(). - * After calling this API, the slave is ready to transfer. - * Example - code - spi_slave_config_t config = { - .polarity = flexSPIClockPolarity_ActiveHigh; - .phase = flexSPIClockPhase_FirstEdge; - .direction = flexSPIMsbFirst; - ... - }; - SPI_SlaveInit(SPI0, &config); - endcode - * - * param base SPI base pointer - * param config pointer to slave configuration structure - */ -status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) -{ - status_t result = kStatus_Success; - uint32_t instance; - uint32_t tmpConfig; - - /* assert params */ - assert(!((NULL == base) || (NULL == config))); - if ((NULL == base) || (NULL == config)) - { - return kStatus_InvalidArgument; - } - /* configure flexcomm to SPI, enable clock gate */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); - if (kStatus_Success != result) - { - return result; - } - - instance = SPI_GetInstance(base); - - /* configure SPI mode */ - tmpConfig = base->CFG; - tmpConfig &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | - SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); - /* phase */ - tmpConfig |= SPI_CFG_CPHA(config->phase); - /* polarity */ - tmpConfig |= SPI_CFG_CPOL(config->polarity); - /* direction */ - tmpConfig |= SPI_CFG_LSBF(config->direction); - /* configure active level for all CS */ - tmpConfig |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); - base->CFG = tmpConfig; - - /* store configuration */ - g_configs[instance].dataWidth = config->dataWidth; - /* empty and enable FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; - /* trigger level - empty txFIFO, one item in rxFIFO */ - tmpConfig = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); - tmpConfig |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable generating interrupts for FIFOTRIG levels */ - tmpConfig |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; - /* set FIFOTRIG */ - base->FIFOTRIG = tmpConfig; - - SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); - - SPI_Enable(base, config->enableSlave); - return kStatus_Success; -} - -/*! - * brief De-initializes the SPI. - * - * Calling this API resets the SPI module, gates the SPI clock. - * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. - * - * param base SPI base pointer - */ -void SPI_Deinit(SPI_Type *base) -{ - /* Assert arguments */ - assert(NULL != base); - /* Disable interrupts, disable dma requests, disable peripheral */ - base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXERR_MASK | SPI_FIFOINTENCLR_RXERR_MASK | SPI_FIFOINTENCLR_TXLVL_MASK | - SPI_FIFOINTENCLR_RXLVL_MASK; - base->FIFOCFG &= ~(SPI_FIFOCFG_DMATX_MASK | SPI_FIFOCFG_DMARX_MASK); - base->CFG &= ~(SPI_CFG_ENABLE_MASK); -} - -/*! - * brief Enables the DMA request from SPI txFIFO. - * - * param base SPI base pointer - * param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableTxDMA(SPI_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= SPI_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= ~SPI_FIFOCFG_DMATX_MASK; - } -} - -/*! - * brief Enables the DMA request from SPI rxFIFO. - * - * param base SPI base pointer - * param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableRxDMA(SPI_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= SPI_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= ~SPI_FIFOCFG_DMARX_MASK; - } -} - -/*! - * brief Sets the baud rate for SPI transfer. This is only used in master. - * - * param base SPI base pointer - * param baudrate_Bps baud rate needed in Hz. - * param srcClock_Hz SPI source clock frequency in Hz. - */ -status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) -{ - uint32_t tmpDiv; - - /* assert params */ - assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))); - if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* calculate baudrate, round up the result */ - tmpDiv = ((srcClock_Hz * 10U) / baudrate_Bps + 5U) / 10U - 1U; - if (tmpDiv > 0xFFFFU) - { - return kStatus_SPI_BaudrateNotSupport; - } - base->DIV &= ~SPI_DIV_DIVVAL_MASK; - base->DIV |= SPI_DIV_DIVVAL(tmpDiv); - return kStatus_Success; -} - -/*! - * brief Writes a data into the SPI data register. - * - * param base SPI base pointer - * param data needs to be write. - * param configFlags transfer configuration options ref spi_xfer_option_t - */ -void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags) -{ - uint32_t control = 0U; - uint32_t instance; - - /* check params */ - assert(NULL != base); - /* get and check instance */ - instance = SPI_GetInstance(base); - - /* set data width */ - control |= (uint32_t)SPI_FIFOWR_LEN((g_configs[instance].dataWidth)); - /* set sssel */ - control |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL((uint32_t)(g_configs[instance].sselNum)))); - /* mask configFlags */ - control |= (configFlags & (uint32_t)SPI_FIFOWR_FLAGS_MASK); - /* control should not affect lower 16 bits */ - assert(0U == (control & 0xFFFFU)); - base->FIFOWR = data | control; -} - -/*! - * brief Initializes the SPI master handle. - * - * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * param base SPI peripheral base address. - * param handle SPI handle pointer. - * param callback Callback function. - * param userData User data. - */ -status_t SPI_MasterTransferCreateHandle(SPI_Type *base, - spi_master_handle_t *handle, - spi_master_callback_t callback, - void *userData) -{ - /* check 'base' */ - assert(NULL != base); - /* check 'handle' */ - assert(NULL != handle); - - uint32_t instance; - spi_to_flexcomm_t handler; - - /* get flexcomm instance by 'base' param */ - instance = SPI_GetInstance(base); - - (void)memset(handle, 0, sizeof(*handle)); - /* Initialize the handle */ - if ((base->CFG & SPI_CFG_MASTER_MASK) != 0U) - { - handler.spi_master_handler = SPI_MasterTransferHandleIRQ; - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - } - else - { - handler.spi_slave_handler = SPI_SlaveTransferHandleIRQ; - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - } - - handle->dataWidth = (uint8_t)(g_configs[instance].dataWidth); - /* in slave mode, the sselNum is not important */ - handle->sselNum = (uint8_t)(g_configs[instance].sselNum); - handle->txWatermark = (uint8_t)SPI_FIFOTRIG_TXLVL_GET(base); - handle->rxWatermark = (uint8_t)SPI_FIFOTRIG_RXLVL_GET(base); - handle->callback = callback; - handle->userData = userData; - - /* Enable SPI NVIC */ - (void)EnableIRQ(s_spiIRQ[instance]); - - return kStatus_Success; -} - -/*! - * brief Transfers a block of data using a polling method. - * - * param base SPI base pointer - * param xfer pointer to spi_xfer_config_t structure - * retval kStatus_Success Successfully start a transfer. - * retval kStatus_InvalidArgument Input argument is invalid. - * retval kStatus_SPI_Timeout The transfer timed out and was aborted. - */ -status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) -{ - uint32_t instance; - uint32_t tx_ctrl = 0U, last_ctrl = 0U; - uint32_t tmp32, rxRemainingBytes, txRemainingBytes, dataWidth; - uint32_t toReceiveCount = 0; - uint8_t *txData, *rxData; - uint32_t fifoDepth; -#if SPI_RETRY_TIMES - uint32_t waitTimes = SPI_RETRY_TIMES; -#endif - - /* check params */ - assert(!((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); - if ((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) - { - return kStatus_InvalidArgument; - } - - fifoDepth = SPI_FIFO_DEPTH(base); - txData = xfer->txData; - rxData = xfer->rxData; - txRemainingBytes = (txData != NULL) ? xfer->dataSize : 0U; - rxRemainingBytes = (rxData != NULL) ? xfer->dataSize : 0U; - - instance = SPI_GetInstance(base); - dataWidth = (uint32_t)(g_configs[instance].dataWidth); - - /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ - if ((dataWidth > (uint32_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U)) - { - return kStatus_InvalidArgument; - } - - /* clear tx/rx errors and empty FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - /* select slave to talk with */ - tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL((uint32_t)(g_configs[instance].sselNum)))); - /* set width of data - range asserted at entry */ - tx_ctrl |= SPI_FIFOWR_LEN(dataWidth); - /* delay for frames */ - tx_ctrl |= ((xfer->configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; - /* end of transfer */ - last_ctrl |= ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; - /* last index of loop */ - while ((txRemainingBytes != 0U) || (rxRemainingBytes != 0U) || (toReceiveCount != 0U)) - { -#if SPI_RETRY_TIMES - if (--waitTimes == 0U) - { - return kStatus_SPI_Timeout; - } -#endif - /* if rxFIFO is not empty */ - if ((base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) != 0U) - { - tmp32 = base->FIFORD; - /* rxBuffer is not empty */ - if (rxRemainingBytes != 0U) - { - *(rxData++) = (uint8_t)tmp32; - rxRemainingBytes--; - /* read 16 bits at once */ - if (dataWidth > 8U) - { - *(rxData++) = (uint8_t)(tmp32 >> 8); - rxRemainingBytes--; - } - } - /* decrease number of data expected to receive */ - toReceiveCount -= 1U; - } - /* transmit if txFIFO is not full and data to receive does not exceed FIFO depth */ - if (((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) != 0U) && (toReceiveCount < fifoDepth) && - ((txRemainingBytes != 0U) || (rxRemainingBytes >= SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1U)))) - { - /* txBuffer is not empty */ - if (txRemainingBytes != 0U) - { - tmp32 = *(txData++); - txRemainingBytes--; - /* write 16 bit at once */ - if (dataWidth > 8U) - { - tmp32 |= ((uint32_t)(*(txData++))) << 8U; - txRemainingBytes--; - } - if (txRemainingBytes == 0U) - { - tx_ctrl |= last_ctrl; - } - } - else - { - tmp32 = (uint32_t)s_dummyData[instance]; - tmp32 |= (uint32_t)s_dummyData[instance] << 8U; - /* last transfer */ - if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1U)) - { - tx_ctrl |= last_ctrl; - } - } - /* send data */ - tmp32 = tx_ctrl | tmp32; - base->FIFOWR = tmp32; - toReceiveCount += 1U; - } - } - /* wait if TX FIFO of previous transfer is not empty */ -#if SPI_RETRY_TIMES - waitTimes = SPI_RETRY_TIMES; - while ((0U == (base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) && (0U != --waitTimes)) -#else - while (0U == (base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) -#endif - { - } -#if SPI_RETRY_TIMES - if (waitTimes == 0U) - { - return kStatus_SPI_Timeout; - } -#endif - return kStatus_Success; -} - -/*! - * brief Performs a non-blocking SPI interrupt transfer. - * - * param base SPI peripheral base address. - * param handle pointer to spi_master_handle_t structure which stores the transfer state - * param xfer pointer to spi_xfer_config_t structure - * retval kStatus_Success Successfully start a transfer. - * retval kStatus_InvalidArgument Input argument is invalid. - * retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer) -{ - /* check params */ - assert( - !((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) - { - return kStatus_InvalidArgument; - } - - /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ - assert(!((handle->dataWidth > (uint8_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U))); - if ((handle->dataWidth > (uint8_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U)) - { - return kStatus_InvalidArgument; - } - - /* Check if SPI is busy */ - if (handle->state == (uint32_t)kStatus_SPI_Busy) - { - return kStatus_SPI_Busy; - } - - /* Set the handle information */ - handle->txData = xfer->txData; - handle->rxData = xfer->rxData; - /* set count */ - handle->txRemainingBytes = (xfer->txData != NULL) ? xfer->dataSize : 0U; - handle->rxRemainingBytes = (xfer->rxData != NULL) ? xfer->dataSize : 0U; - handle->totalByteCount = xfer->dataSize; - /* other options */ - handle->toReceiveCount = 0; - handle->configFlags = xfer->configFlags; - /* Set the SPI state to busy */ - handle->state = (uint32_t)kStatus_SPI_Busy; - /* clear FIFOs when transfer starts */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - /* enable generating txIRQ and rxIRQ, first transfer is fired by empty txFIFO */ - base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK; - return kStatus_Success; -} - -/*! - * brief Transfers a block of data using a polling method. - * - * This function will do a half-duplex transfer for SPI master, This is a blocking function, - * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, - * users can set transmit first or receive first. - * - * param base SPI base pointer - * param xfer pointer to spi_half_duplex_transfer_t structure - * return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer) -{ - assert(xfer != NULL); - - spi_transfer_t tempXfer = {0}; - status_t status; - - if (xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the pcs pin keep assert between transmit and receive. */ - if (xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); - } - else - { - tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; - } - - status = SPI_MasterTransferBlocking(base, &tempXfer); - - if (status != kStatus_Success) - { - return status; - } - - if (xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - /* SPI transfer blocking. */ - status = SPI_MasterTransferBlocking(base, &tempXfer); - - return status; -} - -/*! - * brief Performs a non-blocking SPI interrupt transfer. - * - * This function using polling way to do the first half transimission and using interrupts to - * do the second half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * param base SPI peripheral base address. - * param handle pointer to spi_master_handle_t structure which stores the transfer state - * param xfer pointer to spi_half_duplex_transfer_t structure - * return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, - spi_master_handle_t *handle, - spi_half_duplex_transfer_t *xfer) -{ - assert(xfer != NULL); - assert(handle != NULL); - spi_transfer_t tempXfer = {0}; - status_t status; - - if (xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the PCS pin keep assert between transmit and receive. */ - if (xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); - } - else - { - tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; - } - - status = SPI_MasterTransferBlocking(base, &tempXfer); - if (status != kStatus_Success) - { - return status; - } - - if (xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - status = SPI_MasterTransferNonBlocking(base, handle, &tempXfer); - - return status; -} - -/*! - * brief Gets the master transfer count. - * - * This function gets the master transfer count. - * - * param base SPI peripheral base address. - * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * param count The number of bytes transferred by using the non-blocking transaction. - * return status of status_t. - */ -status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count) -{ - assert(NULL != handle); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != (uint32_t)kStatus_SPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - *count = handle->totalByteCount - handle->rxRemainingBytes; - return kStatus_Success; -} - -/*! - * brief SPI master aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * param base SPI peripheral base address. - * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle) -{ - assert(NULL != handle); - - /* Disable interrupt requests*/ - base->FIFOINTENSET &= ~(SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK); - /* Empty FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - - handle->state = (uint32_t)kStatus_SPI_Idle; - handle->txRemainingBytes = 0U; - handle->rxRemainingBytes = 0U; -} - -static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *handle) -{ - uint32_t tx_ctrl = 0U, last_ctrl = 0U, tmp32; - bool loopContinue; - uint32_t fifoDepth; - /* Get flexcomm instance by 'base' param */ - uint32_t instance = SPI_GetInstance(base); - size_t txRemainingBytes; - size_t rxRemainingBytes; - uint8_t toReceiveCount; - - /* check params */ - assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData))); - - fifoDepth = SPI_FIFO_DEPTH(base); - /* select slave to talk with */ - tx_ctrl |= ((uint32_t)SPI_DEASSERT_ALL & (uint32_t)SPI_ASSERTNUM_SSEL(handle->sselNum)); - /* set width of data */ - tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth); - /* delay for frames */ - tx_ctrl |= ((handle->configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; - /* end of transfer */ - last_ctrl |= ((handle->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; - do - { - loopContinue = false; - - /* rxFIFO is not empty */ - if ((base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) != 0U) - { - tmp32 = base->FIFORD; - /* rxBuffer is not empty */ - if (handle->rxRemainingBytes != 0U) - { - /* low byte must go first */ - *(handle->rxData++) = (uint8_t)tmp32; - handle->rxRemainingBytes--; - /* read 16 bits at once */ - if (handle->dataWidth > (uint8_t)kSPI_Data8Bits) - { - *(handle->rxData++) = (uint8_t)(tmp32 >> 8); - handle->rxRemainingBytes--; - } - } - - /* decrease number of data expected to receive */ - handle->toReceiveCount -= 1; - loopContinue = true; - } - - /* - txFIFO is not full - * - we cannot cause rxFIFO overflow by sending more data than is the depth of FIFO - * - txBuffer is not empty or the next 'toReceiveCount' data can fit into rxBuffer - */ - txRemainingBytes = handle->txRemainingBytes; - rxRemainingBytes = handle->rxRemainingBytes; - toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; - if (((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) != 0U) && ((uint32_t)toReceiveCount < fifoDepth) && - ((txRemainingBytes != 0U) || - (rxRemainingBytes >= SPI_COUNT_TO_BYTES(handle->dataWidth, (uint32_t)toReceiveCount + 1U)))) - { - /* txBuffer is not empty */ - if ((txRemainingBytes != 0U) && (handle->txData != NULL)) - { - /* low byte must go first */ - tmp32 = *(handle->txData++); - handle->txRemainingBytes--; - txRemainingBytes = handle->txRemainingBytes; - /* write 16 bit at once */ - if (handle->dataWidth > (uint8_t)kSPI_Data8Bits) - { - tmp32 |= ((uint32_t)(*(handle->txData++))) << 8U; - handle->txRemainingBytes--; - txRemainingBytes = handle->txRemainingBytes; - } - /* last transfer */ - if (handle->txRemainingBytes == 0U) - { - tx_ctrl |= last_ctrl; - } - } - else - { - tmp32 = (uint32_t)s_dummyData[instance]; - tmp32 |= (uint32_t)s_dummyData[instance] << 8U; - /* last transfer */ - if (rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, (uint32_t)toReceiveCount + 1U)) - { - tx_ctrl |= last_ctrl; - } - } - /* send data */ - tmp32 = tx_ctrl | tmp32; - base->FIFOWR = tmp32; - /* increase number of expected data to receive */ - handle->toReceiveCount += 1; - toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; - loopContinue = true; - } - } while (loopContinue); -} - -/*! - * brief Interrupts the handler for the SPI. - * - * param base SPI peripheral base address. - * param handle pointer to spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle) -{ - assert((NULL != base) && (NULL != handle)); - size_t txRemainingBytes; - uint8_t toReceiveCount; - - /* IRQ behaviour: - * - first interrupt is triggered by empty txFIFO. The transfer function - * then tries empty rxFIFO and fill txFIFO interleaved that results to - * strategy to process as many items as possible. - * - the next IRQs can be: - * rxIRQ from nonempty rxFIFO which requires to empty rxFIFO. - * txIRQ from empty txFIFO which requires to refill txFIFO. - * - last interrupt is triggered by empty txFIFO. The last state is - * known by empty rxBuffer and txBuffer. If there is nothing to receive - * or send - both operations have been finished and interrupts can be - * disabled. - */ - - /* Data to send or read or expected to receive */ - if ((handle->txRemainingBytes != 0U) || (handle->rxRemainingBytes != 0U) || (handle->toReceiveCount != 0)) - { - /* Transmit or receive data */ - SPI_TransferHandleIRQInternal(base, handle); - /* No data to send or read or receive. Transfer ends. Set txTrigger to 0 level and - * enable txIRQ to confirm when txFIFO becomes empty */ - if ((0U == handle->txRemainingBytes) && (0U == handle->rxRemainingBytes) && (0 == handle->toReceiveCount)) - { - base->FIFOTRIG = base->FIFOTRIG & (~SPI_FIFOTRIG_TXLVL_MASK); - base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK; - } - else - { - uint32_t rxRemainingCount = SPI_BYTES_TO_COUNT(handle->dataWidth, handle->rxRemainingBytes); - /* If, there are no data to send or rxFIFO is already filled with necessary number of dummy data, - * disable txIRQ. From this point only rxIRQ is used to receive data without any transmission */ - toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; - if ((0U == handle->txRemainingBytes) && (rxRemainingCount <= toReceiveCount)) - { - base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXLVL_MASK; - } - /* Nothing to receive or transmit, but we still have pending data which are bellow rxLevel. - * Cannot clear rxFIFO, txFIFO might be still active */ - if (rxRemainingCount == 0U) - { - txRemainingBytes = handle->txRemainingBytes; - if ((txRemainingBytes == 0U) && (toReceiveCount != 0U) && - (toReceiveCount < SPI_FIFOTRIG_RXLVL_GET(base) + 1U)) - { - base->FIFOTRIG = (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | - SPI_FIFOTRIG_RXLVL((uint32_t)toReceiveCount - 1U); - } - } - else - { - /* Expected to receive less data than rxLevel value, we have to update rxLevel */ - if (rxRemainingCount < (SPI_FIFOTRIG_RXLVL_GET(base) + 1U)) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(rxRemainingCount - 1U); - } - } - } - } - else - { - /* Empty txFIFO is confirmed. Disable IRQs and restore triggers values */ - base->FIFOINTENCLR = SPI_FIFOINTENCLR_RXLVL_MASK | SPI_FIFOINTENCLR_TXLVL_MASK; - base->FIFOTRIG = (base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_RXLVL_MASK))) | - SPI_FIFOTRIG_RXLVL(handle->rxWatermark) | SPI_FIFOTRIG_TXLVL(handle->txWatermark); - /* set idle state and call user callback */ - handle->state = (uint32_t)kStatus_SPI_Idle; - if (handle->callback != NULL) - { - (handle->callback)(base, handle, handle->state, handle->userData); - } - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_spi.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_spi.h deleted file mode 100644 index 2320e574cc9..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_spi.h +++ /dev/null @@ -1,746 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SPI_H_ -#define _FSL_SPI_H_ - -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/*! - * @addtogroup spi_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SPI driver version. */ -#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) -/*@}*/ - -/*! @brief Global variable for dummy data value setting. */ -extern volatile uint8_t s_dummyData[]; - -#ifndef SPI_DUMMYDATA -/*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */ -#define SPI_DUMMYDATA (0xFFU) -#endif - -/*! @brief Retry times for waiting flag. */ -#ifndef SPI_RETRY_TIMES -#define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ -#endif - -#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFFUL) -#define SPI_CTRLMASK (0xFFFF0000U) - -#define SPI_ASSERTNUM_SSEL(n) ((~(1UL << ((n) + 16UL))) & 0xF0000UL) -#define SPI_DEASSERTNUM_SSEL(n) (1UL << ((n) + 16UL)) -#define SPI_DEASSERT_ALL (0xF0000UL) - -#define SPI_FIFOWR_FLAGS_MASK (~(SPI_DEASSERT_ALL | SPI_FIFOWR_TXDATA_MASK | SPI_FIFOWR_LEN_MASK)) - -#define SPI_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_TXLVL_MASK) >> SPI_FIFOTRIG_TXLVL_SHIFT) -#define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT) - -/*! @brief SPI transfer option.*/ -typedef enum _spi_xfer_option -{ - kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), /*!< A delay may be inserted, defined in the DLY register.*/ - kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< SSEL will be deasserted at the end of a transfer */ -} spi_xfer_option_t; - -/*! @brief SPI data shifter direction options.*/ -typedef enum _spi_shift_direction -{ - kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */ - kSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. */ -} spi_shift_direction_t; - -/*! @brief SPI clock polarity configuration.*/ -typedef enum _spi_clock_polarity -{ - kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */ - kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */ -} spi_clock_polarity_t; - -/*! @brief SPI clock phase configuration.*/ -typedef enum _spi_clock_phase -{ - kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first - * cycle of a data transfer. */ - kSPI_ClockPhaseSecondEdge /*!< First edge on SCK occurs at the start of the - * first cycle of a data transfer. */ -} spi_clock_phase_t; - -/*! @brief txFIFO watermark values */ -typedef enum _spi_txfifo_watermark -{ - kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */ - kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */ - kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */ - kSPI_TxFifo3 = 3, /*!< SPI tx watermark at 3 items */ - kSPI_TxFifo4 = 4, /*!< SPI tx watermark at 4 items */ - kSPI_TxFifo5 = 5, /*!< SPI tx watermark at 5 items */ - kSPI_TxFifo6 = 6, /*!< SPI tx watermark at 6 items */ - kSPI_TxFifo7 = 7, /*!< SPI tx watermark at 7 items */ -} spi_txfifo_watermark_t; - -/*! @brief rxFIFO watermark values */ -typedef enum _spi_rxfifo_watermark -{ - kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */ - kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */ - kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */ - kSPI_RxFifo4 = 3, /*!< SPI rx watermark at 4 items */ - kSPI_RxFifo5 = 4, /*!< SPI rx watermark at 5 items */ - kSPI_RxFifo6 = 5, /*!< SPI rx watermark at 6 items */ - kSPI_RxFifo7 = 6, /*!< SPI rx watermark at 7 items */ - kSPI_RxFifo8 = 7, /*!< SPI rx watermark at 8 items */ -} spi_rxfifo_watermark_t; - -/*! @brief Transfer data width */ -typedef enum _spi_data_width -{ - kSPI_Data4Bits = 3, /*!< 4 bits data width */ - kSPI_Data5Bits = 4, /*!< 5 bits data width */ - kSPI_Data6Bits = 5, /*!< 6 bits data width */ - kSPI_Data7Bits = 6, /*!< 7 bits data width */ - kSPI_Data8Bits = 7, /*!< 8 bits data width */ - kSPI_Data9Bits = 8, /*!< 9 bits data width */ - kSPI_Data10Bits = 9, /*!< 10 bits data width */ - kSPI_Data11Bits = 10, /*!< 11 bits data width */ - kSPI_Data12Bits = 11, /*!< 12 bits data width */ - kSPI_Data13Bits = 12, /*!< 13 bits data width */ - kSPI_Data14Bits = 13, /*!< 14 bits data width */ - kSPI_Data15Bits = 14, /*!< 15 bits data width */ - kSPI_Data16Bits = 15, /*!< 16 bits data width */ -} spi_data_width_t; - -/*! @brief Slave select */ -typedef enum _spi_ssel -{ - kSPI_Ssel0 = 0, /*!< Slave select 0 */ - kSPI_Ssel1 = 1, /*!< Slave select 1 */ - kSPI_Ssel2 = 2, /*!< Slave select 2 */ - kSPI_Ssel3 = 3, /*!< Slave select 3 */ -} spi_ssel_t; - -/*! @brief ssel polarity */ -typedef enum _spi_spol -{ - kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0(1), - kSPI_Spol1ActiveHigh = SPI_CFG_SPOL1(1), - kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2(1), -#if defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) && (FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) - kSPI_SpolActiveAllHigh = (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh), -#else - kSPI_Spol3ActiveHigh = SPI_CFG_SPOL3(1), - kSPI_SpolActiveAllHigh = - (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh | kSPI_Spol3ActiveHigh), -#endif - kSPI_SpolActiveAllLow = 0, -} spi_spol_t; - -/*! - * @brief SPI delay time configure structure. - * Note: - * The DLY register controls several programmable delays related to SPI signalling, - * it stands for how many SPI clock time will be inserted. - * The maxinun value of these delay time is 15. - */ -typedef struct _spi_delay_config -{ - uint8_t preDelay; /*!< Delay between SSEL assertion and the beginning of transfer. */ - uint8_t postDelay; /*!< Delay between the end of transfer and SSEL deassertion. */ - uint8_t frameDelay; /*!< Delay between frame to frame. */ - uint8_t transferDelay; /*!< Delay between transfer to transfer. */ -} spi_delay_config_t; - -/*! @brief SPI master user configure structure.*/ -typedef struct _spi_master_config -{ - bool enableLoopback; /*!< Enable loopback for test purpose */ - bool enableMaster; /*!< Enable SPI at initialization time */ - spi_clock_polarity_t polarity; /*!< Clock polarity */ - spi_clock_phase_t phase; /*!< Clock phase */ - spi_shift_direction_t direction; /*!< MSB or LSB */ - uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */ - spi_data_width_t dataWidth; /*!< Width of the data */ - spi_ssel_t sselNum; /*!< Slave select number */ - spi_spol_t sselPol; /*!< Configure active CS polarity */ - uint8_t txWatermark; /*!< txFIFO watermark */ - uint8_t rxWatermark; /*!< rxFIFO watermark */ - spi_delay_config_t delayConfig; /*!< Delay configuration. */ -} spi_master_config_t; - -/*! @brief SPI slave user configure structure.*/ -typedef struct _spi_slave_config -{ - bool enableSlave; /*!< Enable SPI at initialization time */ - spi_clock_polarity_t polarity; /*!< Clock polarity */ - spi_clock_phase_t phase; /*!< Clock phase */ - spi_shift_direction_t direction; /*!< MSB or LSB */ - spi_data_width_t dataWidth; /*!< Width of the data */ - spi_spol_t sselPol; /*!< Configure active CS polarity */ - uint8_t txWatermark; /*!< txFIFO watermark */ - uint8_t rxWatermark; /*!< rxFIFO watermark */ -} spi_slave_config_t; - -/*! @brief SPI transfer status.*/ -enum -{ - kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0), /*!< SPI bus is busy */ - kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1), /*!< SPI is idle */ - kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI error */ - kStatus_SPI_BaudrateNotSupport = - MAKE_STATUS(kStatusGroup_LPC_SPI, 3), /*!< Baudrate is not support in current clock source */ - kStatus_SPI_Timeout = MAKE_STATUS(kStatusGroup_LPC_SPI, 4) /*!< SPI timeout polling status flags. */ -}; - -/*! @brief SPI interrupt sources.*/ -enum _spi_interrupt_enable -{ - kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, /*!< Rx level interrupt */ - kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, /*!< Tx level interrupt */ -}; - -/*! @brief SPI status flags.*/ -enum _spi_statusflags -{ - kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK, /*!< txFifo is empty */ - kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK, /*!< txFifo is not full */ - kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, /*!< rxFIFO is not empty */ - kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK, /*!< rxFIFO is full */ -}; - -/*! @brief SPI transfer structure */ -typedef struct _spi_transfer -{ - uint8_t *txData; /*!< Send buffer */ - uint8_t *rxData; /*!< Receive buffer */ - uint32_t configFlags; /*!< Additional option to control transfer, @ref spi_xfer_option_t. */ - size_t dataSize; /*!< Transfer bytes */ -} spi_transfer_t; - -/*! @brief SPI half-duplex(master only) transfer structure */ -typedef struct _spi_half_duplex_transfer -{ - uint8_t *txData; /*!< Send buffer */ - uint8_t *rxData; /*!< Receive buffer */ - size_t txDataSize; /*!< Transfer bytes for transmit */ - size_t rxDataSize; /*!< Transfer bytes */ - uint32_t configFlags; /*!< Transfer configuration flags, @ref spi_xfer_option_t. */ - bool isPcsAssertInTransfer; /*!< If PCS pin keep assert between transmit and receive. true for assert and false for - deassert. */ - bool isTransmitFirst; /*!< True for transmit first and false for receive first. */ -} spi_half_duplex_transfer_t; - -/*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */ -typedef struct _spi_config -{ - spi_data_width_t dataWidth; - spi_ssel_t sselNum; -} spi_config_t; - -/*! @brief Master handle type */ -typedef struct _spi_master_handle spi_master_handle_t; - -/*! @brief Slave handle type */ -typedef spi_master_handle_t spi_slave_handle_t; - -/*! @brief SPI master callback for finished transmit */ -typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI slave callback for finished transmit */ -typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI transfer handle structure */ -struct _spi_master_handle -{ - uint8_t *volatile txData; /*!< Transfer buffer */ - uint8_t *volatile rxData; /*!< Receive buffer */ - volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */ - volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */ - volatile int8_t toReceiveCount; /*!< The number of data expected to receive in data width. Since the received count - and sent count should be the same to complete the transfer, if the sent count is - x and the received count is y, toReceiveCount is x-y. */ - size_t totalByteCount; /*!< A number of transfer bytes */ - volatile uint32_t state; /*!< SPI internal state */ - spi_master_callback_t callback; /*!< SPI callback */ - void *userData; /*!< Callback parameter */ - uint8_t dataWidth; /*!< Width of the data [Valid values: 1 to 16] */ - uint8_t sselNum; /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */ - uint32_t configFlags; /*!< Additional option to control transfer */ - uint8_t txWatermark; /*!< txFIFO watermark */ - uint8_t rxWatermark; /*!< rxFIFO watermark */ -}; - -/*! @brief Typedef for master interrupt handler. */ -typedef void (*flexcomm_spi_master_irq_handler_t)(SPI_Type *base, spi_master_handle_t *handle); - -/*! @brief Typedef for slave interrupt handler. */ -typedef void (*flexcomm_spi_slave_irq_handler_t)(SPI_Type *base, spi_slave_handle_t *handle); -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @brief Returns instance number for SPI peripheral base address. */ -uint32_t SPI_GetInstance(SPI_Type *base); - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Sets the SPI master configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). - * User may use the initialized structure unchanged in SPI_MasterInit(), or modify - * some fields of the structure before calling SPI_MasterInit(). After calling this API, - * the master is ready to transfer. - * Example: - @code - spi_master_config_t config; - SPI_MasterGetDefaultConfig(&config); - @endcode - * - * @param config pointer to master config structure - */ -void SPI_MasterGetDefaultConfig(spi_master_config_t *config); - -/*! - * @brief Initializes the SPI with master configuration. - * - * The configuration structure can be filled by user from scratch, or be set with default - * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. - * Example - @code - spi_master_config_t config = { - .baudRate_Bps = 400000, - ... - }; - SPI_MasterInit(SPI0, &config); - @endcode - * - * @param base SPI base pointer - * @param config pointer to master configuration structure - * @param srcClock_Hz Source clock frequency. - */ -status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Sets the SPI slave configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). - * Modify some fields of the structure before calling SPI_SlaveInit(). - * Example: - @code - spi_slave_config_t config; - SPI_SlaveGetDefaultConfig(&config); - @endcode - * - * @param config pointer to slave configuration structure - */ -void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config); - -/*! - * @brief Initializes the SPI with slave configuration. - * - * The configuration structure can be filled by user from scratch or be set with - * default values by SPI_SlaveGetDefaultConfig(). - * After calling this API, the slave is ready to transfer. - * Example - @code - spi_slave_config_t config = { - .polarity = flexSPIClockPolarity_ActiveHigh; - .phase = flexSPIClockPhase_FirstEdge; - .direction = flexSPIMsbFirst; - ... - }; - SPI_SlaveInit(SPI0, &config); - @endcode - * - * @param base SPI base pointer - * @param config pointer to slave configuration structure - */ -status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config); - -/*! - * @brief De-initializes the SPI. - * - * Calling this API resets the SPI module, gates the SPI clock. - * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. - * - * @param base SPI base pointer - */ -void SPI_Deinit(SPI_Type *base); - -/*! - * @brief Enable or disable the SPI Master or Slave - * @param base SPI base pointer - * @param enable or disable ( true = enable, false = disable) - */ -static inline void SPI_Enable(SPI_Type *base, bool enable) -{ - if (enable) - { - base->CFG |= SPI_CFG_ENABLE_MASK; - } - else - { - base->CFG &= ~SPI_CFG_ENABLE_MASK; - } -} - -/*! @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the status flag. - * - * @param base SPI base pointer - * @return SPI Status, use status flag to AND @ref _spi_statusflags could get the related status. - */ -static inline uint32_t SPI_GetStatusFlags(SPI_Type *base) -{ - assert(NULL != base); - return base->FIFOSTAT; -} - -/*! @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the interrupt for the SPI. - * - * @param base SPI base pointer - * @param irqs SPI interrupt source. The parameter can be any combination of the following values: - * @arg kSPI_RxLvlIrq - * @arg kSPI_TxLvlIrq - */ -static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs) -{ - assert(NULL != base); - base->FIFOINTENSET = irqs; -} - -/*! - * @brief Disables the interrupt for the SPI. - * - * @param base SPI base pointer - * @param irqs SPI interrupt source. The parameter can be any combination of the following values: - * @arg kSPI_RxLvlIrq - * @arg kSPI_TxLvlIrq - */ -static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs) -{ - assert(NULL != base); - base->FIFOINTENCLR = irqs; -} - -/*! @} */ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Enables the DMA request from SPI txFIFO. - * - * @param base SPI base pointer - * @param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableTxDMA(SPI_Type *base, bool enable); - -/*! - * @brief Enables the DMA request from SPI rxFIFO. - * - * @param base SPI base pointer - * @param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableRxDMA(SPI_Type *base, bool enable); - -/*! @} */ - -/*! - * @name Bus Operations - * @{ - */ -/*! - * @brief Returns the configurations. - * - * @param base SPI peripheral address. - * @return return configurations which contain datawidth and SSEL numbers. - * return data type is a pointer of spi_config_t. - */ -void *SPI_GetConfig(SPI_Type *base); - -/*! - * @brief Sets the baud rate for SPI transfer. This is only used in master. - * - * @param base SPI base pointer - * @param baudrate_Bps baud rate needed in Hz. - * @param srcClock_Hz SPI source clock frequency in Hz. - */ -status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Writes a data into the SPI data register. - * - * @param base SPI base pointer - * @param data needs to be write. - * @param configFlags transfer configuration options @ref spi_xfer_option_t - */ -void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags); - -/*! - * @brief Gets a data from the SPI data register. - * - * @param base SPI base pointer - * @return Data in the register. - */ -static inline uint32_t SPI_ReadData(SPI_Type *base) -{ - assert(NULL != base); - return base->FIFORD; -} - -/*! - * @brief Set delay time for transfer. - * the delay uint is SPI clock time, maximum value is 0xF. - * @param base SPI base pointer - * @param config configuration for delay option @ref spi_delay_config_t. - */ -static inline void SPI_SetTransferDelay(SPI_Type *base, const spi_delay_config_t *config) -{ - assert(NULL != base); - assert(NULL != config); - base->DLY = (SPI_DLY_PRE_DELAY(config->preDelay) | SPI_DLY_POST_DELAY(config->postDelay) | - SPI_DLY_FRAME_DELAY(config->frameDelay) | SPI_DLY_TRANSFER_DELAY(config->transferDelay)); -} - -/*! - * @brief Set up the dummy data. - * - * @param base SPI peripheral address. - * @param dummyData Data to be transferred when tx buffer is NULL. - */ -void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData); - -/*! @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the SPI master handle. - * - * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback Callback function. - * @param userData User data. - */ -status_t SPI_MasterTransferCreateHandle(SPI_Type *base, - spi_master_handle_t *handle, - spi_master_callback_t callback, - void *userData); - -/*! - * @brief Transfers a block of data using a polling method. - * - * @param base SPI base pointer - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Timeout The transfer timed out and was aborted. - */ -status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer); - -/*! - * @brief Performs a non-blocking SPI interrupt transfer. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer); - -/*! - * @brief Transfers a block of data using a polling method. - * - * This function will do a half-duplex transfer for SPI master, This is a blocking function, - * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, - * users can set transmit first or receive first. - * - * @param base SPI base pointer - * @param xfer pointer to spi_half_duplex_transfer_t structure - * @return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer); - -/*! - * @brief Performs a non-blocking SPI interrupt transfer. - * - * This function using polling way to do the first half transimission and using interrupts to - * do the second half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_half_duplex_transfer_t structure - * @return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, - spi_master_handle_t *handle, - spi_half_duplex_transfer_t *xfer); - -/*! - * @brief Gets the master transfer count. - * - * This function gets the master transfer count. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * @param count The number of bytes transferred by using the non-blocking transaction. - * @return status of status_t. - */ -status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count); - -/*! - * @brief SPI master aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle); - -/*! - * @brief Interrupts the handler for the SPI. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle); - -/*! - * @brief Initializes the SPI slave handle. - * - * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback Callback function. - * @param userData User data. - */ -static inline status_t SPI_SlaveTransferCreateHandle(SPI_Type *base, - spi_slave_handle_t *handle, - spi_slave_callback_t callback, - void *userData) -{ - return SPI_MasterTransferCreateHandle(base, handle, callback, userData); -} - -/*! - * @brief Performs a non-blocking SPI slave interrupt transfer. - * - * @note The API returns immediately after the transfer initialization is finished. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer) -{ - return SPI_MasterTransferNonBlocking(base, handle, xfer); -} - -/*! - * @brief Gets the slave transfer count. - * - * This function gets the slave transfer count. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * @param count The number of bytes transferred by using the non-blocking transaction. - * @return status of status_t. - */ -static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count) -{ - return SPI_MasterTransferGetCount(base, (spi_master_handle_t *)handle, count); -} - -/*! - * @brief SPI slave aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state. - */ -static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle) -{ - SPI_MasterTransferAbort(base, (spi_master_handle_t *)handle); -} - -/*! - * @brief Interrupts a handler for the SPI slave. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_slave_handle_t structure which stores the transfer state - */ -static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle) -{ - SPI_MasterTransferHandleIRQ(base, handle); -} - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_SPI_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_spi_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_spi_dma.c deleted file mode 100644 index ed0aaa6a9fa..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_spi_dma.c +++ /dev/null @@ -1,568 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_spi_dma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi_dma" -#endif - -/*configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; - *fifowr |= ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; -} - -static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr) -{ - *fifowr |= ((uint32_t)SPI_DEASSERT_ALL & (~(uint32_t)SPI_DEASSERTNUM_SSEL((uint32_t)config->sselNum))); - /* set width of data - range asserted at entry */ - *fifowr |= SPI_FIFOWR_LEN(config->dataWidth); -} - -static void PrepareTxLastWord(spi_transfer_t *xfer, uint32_t *txLastWord, spi_config_t *config) -{ - if (config->dataWidth > kSPI_Data8Bits) - { - *txLastWord = (((uint32_t)xfer->txData[xfer->dataSize - 1U] << 8U) | (xfer->txData[xfer->dataSize - 2U])); - } - else - { - *txLastWord = xfer->txData[xfer->dataSize - 1U]; - } - XferToFifoWR(xfer, txLastWord); - SpiConfigToFifoWR(config, txLastWord); -} - -static void SPI_SetupDummy(SPI_Type *base, spi_dma_txdummy_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p) -{ - uint32_t instance = SPI_GetInstance(base); - uint32_t dummydata = (uint32_t)s_dummyData[instance]; - dummydata |= (uint32_t)s_dummyData[instance] << 8U; - - dummy->word = dummydata; - dummy->lastWord = dummydata; - - XferToFifoWR(xfer, &dummy->word); - XferToFifoWR(xfer, &dummy->lastWord); - SpiConfigToFifoWR(spi_config_p, &dummy->word); - SpiConfigToFifoWR(spi_config_p, &dummy->lastWord); - /* Clear the end of transfer bit for continue word transfer. */ - dummy->word &= (~(uint32_t)kSPI_FrameAssert); -} - -/*! - * brief Initialize the SPI master DMA handle. - * - * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * param base SPI peripheral base address. - * param handle SPI handle pointer. - * param callback User callback function called at the end of a transfer. - * param userData User data for callback. - * param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle) -{ - uint32_t instance; - - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } - /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - instance = SPI_GetInstance(base); - - (void)memset(handle, 0, sizeof(*handle)); - /* Set spi base to handle */ - handle->txHandle = txHandle; - handle->rxHandle = rxHandle; - handle->callback = callback; - handle->userData = userData; - - /* Set SPI state to idle */ - handle->state = (uint8_t)kSPI_Idle; - - /* Set handle to global state */ - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - /* Install callback for Tx dma channel */ - DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]); - DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]); - - return kStatus_Success; -} - -/*! - * brief Perform a non-blocking SPI transfer using DMA. - * - * note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * param base SPI peripheral base address. - * param handle SPI DMA handle pointer. - * param xfer Pointer to dma transfer structure. - * retval kStatus_Success Successfully start a transfer. - * retval kStatus_InvalidArgument Input argument is invalid. - * retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) -{ - assert(!((NULL == handle) || (NULL == xfer))); - - uint32_t instance; - status_t result = kStatus_Success; - spi_config_t *spi_config_p; - uint32_t address; - - if ((NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - - /* Byte size is zero. */ - if (xfer->dataSize == 0U) - { - return kStatus_InvalidArgument; - } - /* cannot get instance from base address */ - instance = SPI_GetInstance(base); - - /* Check if the device is busy */ - if (handle->state == (uint8_t)kSPI_Busy) - { - return kStatus_SPI_Busy; - } - else - { - /* Clear FIFOs before transfer. */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - - dma_transfer_config_t xferConfig = {0}; - spi_config_p = (spi_config_t *)SPI_GetConfig(base); - - handle->state = (uint8_t)kSPI_Busy; - handle->transferSize = xfer->dataSize; - - /* receive */ - SPI_EnableRxDMA(base, true); - address = (uint32_t)&base->FIFORD; - if (xfer->rxData != NULL) - { - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, xfer->rxData, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_PeripheralToMemory, NULL); - } - else - { - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, &s_rxDummy, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_StaticToStatic, NULL); - } - (void)DMA_SubmitTransfer(handle->rxHandle, &xferConfig); - handle->rxInProgress = true; - DMA_StartTransfer(handle->rxHandle); - - /* transmit */ - SPI_EnableTxDMA(base, true); - address = (uint32_t)&base->FIFOWR; - if (xfer->txData != NULL) - { - if ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) - { - PrepareTxLastWord(xfer, &s_txLastWord[instance], spi_config_p); - } - /* If end of tranfer function is enabled and data transfer frame is bigger then 1, use dma - * descriptor to send the last data. - */ - if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2U) : (xfer->dataSize > 1U))) - { - dma_xfercfg_t tmp_xfercfg; - tmp_xfercfg.valid = true; - tmp_xfercfg.swtrig = true; - tmp_xfercfg.intA = true; - tmp_xfercfg.byteWidth = 4U; - tmp_xfercfg.srcInc = 0; - tmp_xfercfg.dstInc = 0; - tmp_xfercfg.transferCount = 1; - tmp_xfercfg.reload = false; - tmp_xfercfg.clrtrig = false; - tmp_xfercfg.intB = false; - /* Create chained descriptor to transmit last word */ - DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txLastWord[instance], - (uint32_t *)address, NULL); - - DMA_PrepareTransfer( - &xferConfig, xfer->txData, (uint32_t *)address, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2U) : (xfer->dataSize - 1U)), - kDMA_MemoryToPeripheral, &s_spi_descriptor_table[instance]); - /* Disable interrupts for first descriptor to avoid calling callback twice. */ - xferConfig.xfercfg.intA = false; - xferConfig.xfercfg.intB = false; - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - else - { - DMA_PrepareTransfer( - &xferConfig, xfer->txData, (uint32_t *)address, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_MemoryToPeripheral, NULL); - (void)DMA_SubmitTransfer(handle->txHandle, &xferConfig); - } - } - else - { - /* Setup tx dummy data. */ - SPI_SetupDummy(base, &s_txDummy[instance], xfer, spi_config_p); - if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2U) : (xfer->dataSize > 1U))) - { - dma_xfercfg_t tmp_xfercfg; - tmp_xfercfg.valid = true; - tmp_xfercfg.swtrig = true; - tmp_xfercfg.intA = true; - tmp_xfercfg.byteWidth = (uint8_t)sizeof(uint32_t); - tmp_xfercfg.srcInc = 0; - tmp_xfercfg.dstInc = 0; - tmp_xfercfg.transferCount = 1; - tmp_xfercfg.reload = false; - tmp_xfercfg.clrtrig = false; - tmp_xfercfg.intB = false; - /* Create chained descriptor to transmit last word */ - DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord, - (uint32_t *)address, NULL); - /* Use common API to setup first descriptor */ - DMA_PrepareTransfer( - &xferConfig, &s_txDummy[instance].word, (uint32_t *)address, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2U) : (xfer->dataSize - 1U)), - kDMA_StaticToStatic, &s_spi_descriptor_table[instance]); - /* Disable interrupts for first descriptor to avoid calling callback twice */ - xferConfig.xfercfg.intA = false; - xferConfig.xfercfg.intB = false; - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - else - { - DMA_PrepareTransfer( - &xferConfig, &s_txDummy[instance].word, (uint32_t *)address, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_StaticToStatic, NULL); - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - } - - handle->txInProgress = true; - uint32_t tmpData = 0U; - uint32_t writeAddress = (uint32_t) & (base->FIFOWR) + 2UL; - XferToFifoWR(xfer, &tmpData); - SpiConfigToFifoWR(spi_config_p, &tmpData); - - /* Setup the control info. - * Halfword writes to just the control bits (offset 0xE22) doesn't push anything into the FIFO. - * And the data access type of control bits must be uint16_t, byte writes or halfword writes to FIFOWR - * will push the data and the current control bits into the FIFO. - */ - if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize == 2U) : (xfer->dataSize == 1U))) - { - *(uint16_t *)writeAddress = (uint16_t)(tmpData >> 16U); - } - else - { - /* Clear the SPI_FIFOWR_EOT_MASK bit when data is not the last. */ - tmpData &= (~(uint32_t)kSPI_FrameAssert); - *(uint16_t *)writeAddress = (uint16_t)(tmpData >> 16U); - } - - DMA_StartTransfer(handle->txHandle); - } - - return result; -} - -/*! - * brief Transfers a block of data using a DMA method. - * - * This function using polling way to do the first half transimission and using DMA way to - * do the srcond half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * param base SPI base pointer - * param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. - * param transfer A pointer to the spi_half_duplex_transfer_t structure. - * return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer) -{ - assert((xfer != NULL) && (handle != NULL)); - spi_transfer_t tempXfer = {0}; - status_t status; - - if (xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the pcs pin keep assert between transmit and receive. */ - if (xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); - } - else - { - tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; - } - - status = SPI_MasterTransferBlocking(base, &tempXfer); - if (status != kStatus_Success) - { - return status; - } - - if (xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - status = SPI_MasterTransferDMA(base, handle, &tempXfer); - - return status; -} - -static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) -{ - spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; - spi_dma_handle_t *spiHandle = privHandle->handle; - SPI_Type *base = privHandle->base; - - /* change the state */ - spiHandle->rxInProgress = false; - - /* All finished, call the callback */ - if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) - { - spiHandle->state = (uint8_t)kSPI_Idle; - if (spiHandle->callback != NULL) - { - (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); - } - } -} - -static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) -{ - spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; - spi_dma_handle_t *spiHandle = privHandle->handle; - SPI_Type *base = privHandle->base; - - /* change the state */ - spiHandle->txInProgress = false; - - /* All finished, call the callback */ - if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) - { - spiHandle->state = (uint8_t)kSPI_Idle; - if (spiHandle->callback != NULL) - { - (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); - } - } -} - -/*! - * brief Abort a SPI transfer using DMA. - * - * param base SPI peripheral base address. - * param handle SPI DMA handle pointer. - */ -void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) -{ - assert(NULL != handle); - - /* Stop tx transfer first */ - DMA_AbortTransfer(handle->txHandle); - /* Then rx transfer */ - DMA_AbortTransfer(handle->rxHandle); - - /* Set the handle state */ - handle->txInProgress = false; - handle->rxInProgress = false; - handle->state = (uint8_t)kSPI_Idle; -} - -/*! - * brief Gets the master DMA transfer remaining bytes. - * - * This function gets the master DMA transfer remaining bytes. - * - * param base SPI peripheral base address. - * param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * param count A number of bytes transferred by the non-blocking transaction. - * return status of status_t. - */ -status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != (uint8_t)kSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - size_t bytes; - - bytes = DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel); - - *count = handle->transferSize - bytes; - - return kStatus_Success; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_spi_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_spi_dma.h deleted file mode 100644 index 614c37d791a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_spi_dma.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SPI_DMA_H_ -#define _FSL_SPI_DMA_H_ - -#include "fsl_dma.h" -#include "fsl_spi.h" - -/*! - * @addtogroup spi_dma_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SPI DMA driver version 2.1.1. */ -#define FSL_SPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) -/*@}*/ - -typedef struct _spi_dma_handle spi_dma_handle_t; - -/*! @brief SPI DMA callback called at the end of transfer. */ -typedef void (*spi_dma_callback_t)(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI DMA transfer handle, users should not touch the content of the handle.*/ -struct _spi_dma_handle -{ - volatile bool txInProgress; /*!< Send transfer finished */ - volatile bool rxInProgress; /*!< Receive transfer finished */ - dma_handle_t *txHandle; /*!< DMA handler for SPI send */ - dma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ - uint8_t bytesPerFrame; /*!< Bytes in a frame for SPI transfer */ - spi_dma_callback_t callback; /*!< Callback for SPI DMA transfer */ - void *userData; /*!< User Data for SPI DMA callback */ - uint32_t state; /*!< Internal state of SPI DMA transfer */ - size_t transferSize; /*!< Bytes need to be transfer */ -}; - -/******************************************************************************* - * APIs - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name DMA Transactional - * @{ - */ - -/*! - * @brief Initialize the SPI master DMA handle. - * - * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback User callback function called at the end of a transfer. - * @param userData User data for callback. - * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle); - -/*! - * @brief Perform a non-blocking SPI transfer using DMA. - * - * @note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - * @param xfer Pointer to dma transfer structure. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer); - -/*! - * @brief Transfers a block of data using a DMA method. - * - * This function using polling way to do the first half transimission and using DMA way to - * do the srcond half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * @param base SPI base pointer - * @param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. - * @param xfer A pointer to the spi_half_duplex_transfer_t structure. - * @return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer); - -/*! - * @brief Initialize the SPI slave DMA handle. - * - * This function initializes the SPI slave DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback User callback function called at the end of a transfer. - * @param userData User data for callback. - * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -static inline status_t SPI_SlaveTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle) -{ - return SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle); -} - -/*! - * @brief Perform a non-blocking SPI transfer using DMA. - * - * @note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - * @param xfer Pointer to dma transfer structure. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -static inline status_t SPI_SlaveTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) -{ - return SPI_MasterTransferDMA(base, handle, xfer); -} - -/*! - * @brief Abort a SPI transfer using DMA. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - */ -void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle); - -/*! - * @brief Gets the master DMA transfer remaining bytes. - * - * This function gets the master DMA transfer remaining bytes. - * - * @param base SPI peripheral base address. - * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * @param count A number of bytes transferred by the non-blocking transaction. - * @return status of status_t. - */ -status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count); - -/*! - * @brief Abort a SPI transfer using DMA. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - */ -static inline void SPI_SlaveTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) -{ - SPI_MasterTransferAbortDMA(base, handle); -} - -/*! - * @brief Gets the slave DMA transfer remaining bytes. - * - * This function gets the slave DMA transfer remaining bytes. - * - * @param base SPI peripheral base address. - * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * @param count A number of bytes transferred by the non-blocking transaction. - * @return status of status_t. - */ -static inline status_t SPI_SlaveTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) -{ - return SPI_MasterTransferGetCountDMA(base, handle, count); -} - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_SPI_DMA_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_sysctl.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_sysctl.c deleted file mode 100644 index 1d0dd9ccf64..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_sysctl.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sysctl.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.sysctl" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get the instance. - * - * @param base SYSCTL peripheral base address. - * @return Instance number. - */ -static uint32_t SYSCTL_GetInstance(SYSCTL_Type *base); - -/*! - * @brief Enable SYSCTL write protect - * - * @param base SYSCTL peripheral base address. - * @param regAddr register address - * @param value value to write. - */ -static void SYSCTL_UpdateRegister(SYSCTL_Type *base, volatile uint32_t *regAddr, uint32_t value); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief SYSCTL base address array name */ -static SYSCTL_Type *const s_sysctlBase[] = SYSCTL_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief SYSCTL clock array name */ -static const clock_ip_name_t s_sysctlClock[] = SYSCTL_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static void SYSCTL_UpdateRegister(SYSCTL_Type *base, volatile uint32_t *regAddr, uint32_t value) -{ - base->UPDATELCKOUT &= ~SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK; - *regAddr = value; - base->UPDATELCKOUT |= SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK; -} - -static uint32_t SYSCTL_GetInstance(SYSCTL_Type *base) -{ - uint8_t instance = 0; - - while ((instance < ARRAY_SIZE(s_sysctlBase)) && (s_sysctlBase[instance] != base)) - { - instance++; - } - - assert(instance < ARRAY_SIZE(s_sysctlBase)); - - return instance; -} - -/*! - * @brief SYSCTL initial - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Init(SYSCTL_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable SYSCTL clock. */ - CLOCK_EnableClock(s_sysctlClock[SYSCTL_GetInstance(base)]); -#endif -} - -/*! - * @brief SYSCTL deinit - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Deinit(SYSCTL_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable SYSCTL clock. */ - CLOCK_DisableClock(s_sysctlClock[SYSCTL_GetInstance(base)]); -#endif -} - -/*! - * @brief SYSCTL share set configure for separate signal - * - * @param base Base address of the SYSCTL peripheral - * @param flexCommIndex index of flexcomm,reference _sysctl_share_src - * @param setIndex share set for sck, reference _sysctl_share_set_index - * - */ -void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set) -{ - uint32_t tempReg = base->FCCTRLSEL[flexCommIndex]; - - tempReg &= ~((uint32_t)SYSCTL_FCCTRLSEL_SCKINSEL_MASK << (uint32_t)signal); - tempReg |= (set + 1U) << (uint32_t)signal; - - SYSCTL_UpdateRegister(base, &base->FCCTRLSEL[flexCommIndex], tempReg); -} - -/*! - * @brief SYSCTL share set configure for flexcomm - * - * @param base Base address of the SYSCTL peripheral. - * @param flexCommIndex index of flexcomm, reference _sysctl_share_src - * @param sckSet share set for sck,reference _sysctl_share_set_index - * @param wsSet share set for ws, reference _sysctl_share_set_index - * @param dataInSet share set for data in, reference _sysctl_share_set_index - * @param dataOutSet share set for data out, reference _sysctl_share_set_index - * - */ -void SYSCTL_SetFlexcommShareSet( - SYSCTL_Type *base, uint32_t flexCommIndex, uint32_t sckSet, uint32_t wsSet, uint32_t dataInSet, uint32_t dataOutSet) -{ - uint32_t tempReg = base->FCCTRLSEL[flexCommIndex]; - - tempReg &= ~(SYSCTL_FCCTRLSEL_SCKINSEL_MASK | SYSCTL_FCCTRLSEL_WSINSEL_MASK | SYSCTL_FCCTRLSEL_DATAINSEL_MASK | - SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK); - tempReg |= SYSCTL_FCCTRLSEL_SCKINSEL(sckSet + 1U) | SYSCTL_FCCTRLSEL_WSINSEL(wsSet + 1U) | - SYSCTL_FCCTRLSEL_DATAINSEL(dataInSet + 1U) | SYSCTL_FCCTRLSEL_DATAOUTSEL(dataOutSet + 1U); - - SYSCTL_UpdateRegister(base, &base->FCCTRLSEL[flexCommIndex], tempReg); -} - -/*! - * @brief SYSCTL share set source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param sckShareSrc sck source for this share set,reference _sysctl_share_src - * @param wsShareSrc ws source for this share set,reference _sysctl_share_src - * @param dataInShareSrc data in source for this share set,reference _sysctl_share_src - * @param dataOutShareSrc data out source for this share set,reference _sysctl_dataout_mask - * - */ -void SYSCTL_SetShareSetSrc(SYSCTL_Type *base, - uint32_t setIndex, - uint32_t sckShareSrc, - uint32_t wsShareSrc, - uint32_t dataInShareSrc, - uint32_t dataOutShareSrc) -{ - uint32_t tempReg = base->SHAREDCTRLSET[setIndex]; - - /* WS,SCK,DATA IN */ - tempReg &= ~(SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK | SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK | - SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK); - tempReg |= SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(sckShareSrc) | SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(wsShareSrc) | - SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(dataInShareSrc); - - /* data out */ - tempReg &= ~(SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK | SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK | - SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK | SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK | - SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK); - tempReg |= dataOutShareSrc; - - SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg); -} - -/*! - * @brief SYSCTL sck source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param sckShareSrc sck source fro this share set,reference _sysctl_share_src - * - */ -void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base, - uint32_t setIndex, - sysctl_sharedctrlset_signal_t signal, - uint32_t shareSrc) -{ - uint32_t tempReg = base->SHAREDCTRLSET[setIndex]; - - if (signal == kSYSCTL_SharedCtrlSignalDataOut) - { - tempReg |= 1UL << ((uint32_t)signal + shareSrc); - } - else - { - tempReg &= ~((uint32_t)SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK << (uint32_t)signal); - tempReg |= shareSrc << (uint32_t)signal; - } - - SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg); -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_sysctl.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_sysctl.h deleted file mode 100644 index 0a1be88469c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_sysctl.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_SYSCTL_H_ -#define _FSL_SYSCTL_H_ - -#include "fsl_common.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup sysctl - * @{ - */ - -/*! @file */ -/*! @file fsl_sysctl.h */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Group sysctl driver version for SDK */ -#define FSL_SYSCTL_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) /*!< Version 2.0.5. */ -/*@}*/ - -/*! @brief SYSCTL share set*/ -enum _sysctl_share_set_index -{ - kSYSCTL_ShareSet0 = 0, /*!< share set 0 */ - kSYSCTL_ShareSet1 = 1, /*!< share set 1 */ -}; - -/*! @brief SYSCTL flexcomm signal */ -typedef enum _sysctl_fcctrlsel_signal -{ - kSYSCTL_FlexcommSignalSCK = SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT, /*!< SCK signal */ - kSYSCTL_FlexcommSignalWS = SYSCTL_FCCTRLSEL_WSINSEL_SHIFT, /*!< WS signal */ - kSYSCTL_FlexcommSignalDataIn = SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT, /*!< Data in signal */ - kSYSCTL_FlexcommSignalDataOut = SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT, /*!< Data out signal */ -} sysctl_fcctrlsel_signal_t; - -/*! @brief SYSCTL flexcomm index*/ -enum _sysctl_share_src -{ - kSYSCTL_Flexcomm0 = 0, /*!< share set 0 */ - kSYSCTL_Flexcomm1 = 1, /*!< share set 1 */ - kSYSCTL_Flexcomm2 = 2, /*!< share set 2 */ - kSYSCTL_Flexcomm4 = 4, /*!< share set 4 */ - kSYSCTL_Flexcomm5 = 5, /*!< share set 5 */ - kSYSCTL_Flexcomm6 = 6, /*!< share set 6 */ - kSYSCTL_Flexcomm7 = 7, /*!< share set 7 */ -}; - -/*! @brief SYSCTL shared data out mask */ -enum _sysctl_dataout_mask -{ - kSYSCTL_Flexcomm0DataOut = SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK, /*!< share set 0 */ - kSYSCTL_Flexcomm1DataOut = SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK, /*!< share set 1 */ - kSYSCTL_Flexcomm2DataOut = SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK, /*!< share set 2 */ - kSYSCTL_Flexcomm4DataOut = SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK, /*!< share set 4 */ - kSYSCTL_Flexcomm5DataOut = SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK, /*!< share set 5 */ - kSYSCTL_Flexcomm6DataOut = SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK, /*!< share set 6 */ - kSYSCTL_Flexcomm7DataOut = SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK, /*!< share set 7 */ -}; - -/*! @brief SYSCTL flexcomm signal */ -typedef enum _sysctl_sharedctrlset_signal -{ - kSYSCTL_SharedCtrlSignalSCK = SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT, /*!< SCK signal */ - kSYSCTL_SharedCtrlSignalWS = SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT, /*!< WS signal */ - kSYSCTL_SharedCtrlSignalDataIn = SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT, /*!< Data in signal */ - kSYSCTL_SharedCtrlSignalDataOut = SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT, /*!< Data out signal */ -} sysctl_sharedctrlset_signal_t; -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief SYSCTL initial - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Init(SYSCTL_Type *base); - -/*! - * @brief SYSCTL deinit - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Deinit(SYSCTL_Type *base); - -/* @} */ - -/*! - * @name SYSCTL share signal configure - * @{ - */ - -/*! - * @brief SYSCTL share set configure for flexcomm - * - * @param base Base address of the SYSCTL peripheral. - * @param flexCommIndex index of flexcomm, reference _sysctl_share_src - * @param sckSet share set for sck,reference _sysctl_share_set_index - * @param wsSet share set for ws, reference _sysctl_share_set_index - * @param dataInSet share set for data in, reference _sysctl_share_set_index - * @param dataOutSet share set for data out, reference _sysctl_dataout_mask - * - */ -void SYSCTL_SetFlexcommShareSet(SYSCTL_Type *base, - uint32_t flexCommIndex, - uint32_t sckSet, - uint32_t wsSet, - uint32_t dataInSet, - uint32_t dataOutSet); - -/*! - * @brief SYSCTL share set configure for separate signal - * - * @param base Base address of the SYSCTL peripheral - * @param flexCommIndex index of flexcomm,reference _sysctl_share_src - * @param signal FCCTRLSEL signal shift - * @param set share set for sck, reference _sysctl_share_set_index - * - */ -void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set); - -/*! - * @brief SYSCTL share set source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param sckShareSrc sck source for this share set,reference _sysctl_share_src - * @param wsShareSrc ws source for this share set,reference _sysctl_share_src - * @param dataInShareSrc data in source for this share set,reference _sysctl_share_src - * @param dataOutShareSrc data out source for this share set,reference _sysctl_dataout_mask - * - */ -void SYSCTL_SetShareSetSrc(SYSCTL_Type *base, - uint32_t setIndex, - uint32_t sckShareSrc, - uint32_t wsShareSrc, - uint32_t dataInShareSrc, - uint32_t dataOutShareSrc); - -/*! - * @brief SYSCTL sck source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param signal FCCTRLSEL signal shift - * @param shareSrc sck source fro this share set,reference _sysctl_share_src - * - */ -void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base, - uint32_t setIndex, - sysctl_sharedctrlset_signal_t signal, - uint32_t shareSrc); - -/* @} */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_SYSCTL_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_usart.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_usart.c deleted file mode 100644 index 3286174f27b..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_usart.c +++ /dev/null @@ -1,1206 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_usart.h" -#include "fsl_device_registers.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart" -#endif - -/*! - * @brief Used for conversion from `flexcomm_usart_irq_handler_t` to `flexcomm_irq_handler_t` - */ -typedef union usart_to_flexcomm -{ - flexcomm_usart_irq_handler_t usart_master_handler; - flexcomm_irq_handler_t flexcomm_handler; -} usart_to_flexcomm_t; - -enum -{ - kUSART_TxIdle, /* TX idle. */ - kUSART_TxBusy, /* TX busy. */ - kUSART_RxIdle, /* RX idle. */ - kUSART_RxBusy /* RX busy. */ -}; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief IRQ name array */ -static const IRQn_Type s_usartIRQ[] = USART_IRQS; - -/*! @brief Array to map USART instance number to base address. */ -static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Get the index corresponding to the USART */ -/*! brief Returns instance number for USART peripheral base address. */ -uint32_t USART_GetInstance(USART_Type *base) -{ - uint32_t i; - - for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT; i++) - { - if ((uint32_t)base == s_usartBaseAddrs[i]) - { - break; - } - } - - assert(i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT); - return i; -} - -/*! - * brief Get the length of received data in RX ring buffer. - * - * param handle USART handle pointer. - * return Length of received data in RX ring buffer. - */ -size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) -{ - size_t size; - - /* Check arguments */ - assert(NULL != handle); - uint16_t rxRingBufferHead = handle->rxRingBufferHead; - uint16_t rxRingBufferTail = handle->rxRingBufferTail; - - if (rxRingBufferTail > rxRingBufferHead) - { - size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail; - } - else - { - size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail; - } - return size; -} - -static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle) -{ - bool full; - - /* Check arguments */ - assert(NULL != handle); - - if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) - { - full = true; - } - else - { - full = false; - } - return full; -} - -/*! - * brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific USART handle. - * - * When the RX ring buffer is used, data received are stored into the ring buffer even when the - * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * - * note When using the RX ring buffer, one byte is reserved for internal use. In other - * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. - * param ringBufferSize size of the ring buffer. - */ -void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) -{ - /* Check arguments */ - assert(NULL != base); - assert(NULL != handle); - assert(NULL != ringBuffer); - - /* Setup the ringbuffer address */ - handle->rxRingBuffer = ringBuffer; - handle->rxRingBufferSize = ringBufferSize; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; - /* ring buffer is ready we can start receiving data */ - base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -} - -/*! - * brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) -{ - /* Check arguments */ - assert(NULL != base); - assert(NULL != handle); - - if (handle->rxState == (uint8_t)kUSART_RxIdle) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK; - } - handle->rxRingBuffer = NULL; - handle->rxRingBufferSize = 0U; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; -} - -/*! - * brief Initializes a USART instance with user configuration structure and peripheral clock. - * - * This function configures the USART module with the user-defined settings. The user can configure the configuration - * structure and also get the default configuration by using the USART_GetDefaultConfig() function. - * Example below shows how to use this API to configure USART. - * code - * usart_config_t usartConfig; - * usartConfig.baudRate_Bps = 115200U; - * usartConfig.parityMode = kUSART_ParityDisabled; - * usartConfig.stopBitCount = kUSART_OneStopBit; - * USART_Init(USART1, &usartConfig, 20000000U); - * endcode - * - * param base USART peripheral base address. - * param config Pointer to user-defined configuration structure. - * param srcClock_Hz USART clock source frequency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_InvalidArgument USART base address is not valid - * retval kStatus_Success Status USART initialize succeed - */ -status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz) -{ - int result; - - /* check arguments */ - assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); - if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* initialize flexcomm to USART mode */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART); - if (kStatus_Success != result) - { - return result; - } - - if (config->enableTx) - { - /* empty and enable txFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK; - /* setup trigger level */ - base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK); - base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark); - /* enable trigger interrupt */ - base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK; - } - - /* empty and enable rxFIFO */ - if (config->enableRx) - { - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK; - /* setup trigger level */ - base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK); - base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable trigger interrupt */ - base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK; - } - /* setup configuration and enable USART */ - base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | - USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | - USART_CFG_SYNCEN((uint32_t)config->syncMode >> 1) | USART_CFG_SYNCMST((uint8_t)config->syncMode) | - USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_MODE32K(config->enableMode32k) | - USART_CFG_CTSEN(config->enableHardwareFlowControl) | USART_CFG_ENABLE_MASK; - - /* Setup baudrate */ - if (config->enableMode32k) - { - if ((9600U % config->baudRate_Bps) == 0U) - { - base->BRG = 9600U / config->baudRate_Bps; - } - else - { - return kStatus_USART_BaudrateNotSupport; - } - } - else - { - result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - } - /* Setting continuous Clock configuration. used for synchronous mode. */ - USART_EnableContinuousSCLK(base, config->enableContinuousSCLK); - - return kStatus_Success; -} - -/*! - * brief Deinitializes a USART instance. - * - * This function waits for TX complete, disables TX and RX, and disables the USART clock. - * - * param base USART peripheral base address. - */ -void USART_Deinit(USART_Type *base) -{ - /* Check arguments */ - assert(NULL != base); - while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) - { - } - /* Disable interrupts, disable dma requests, disable peripheral */ - base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK | - USART_FIFOINTENCLR_RXLVL_MASK; - base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK); - base->CFG &= ~(USART_CFG_ENABLE_MASK); -} - -/*! - * brief Gets the default configuration structure. - * - * This function initializes the USART configuration structure to a default value. The default - * values are: - * usartConfig->baudRate_Bps = 115200U; - * usartConfig->parityMode = kUSART_ParityDisabled; - * usartConfig->stopBitCount = kUSART_OneStopBit; - * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; - * usartConfig->loopback = false; - * usartConfig->enableTx = false; - * usartConfig->enableRx = false; - * - * param config Pointer to configuration structure. - */ -void USART_GetDefaultConfig(usart_config_t *config) -{ - /* Check arguments */ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* Set always all members ! */ - config->baudRate_Bps = 115200U; - config->parityMode = kUSART_ParityDisabled; - config->stopBitCount = kUSART_OneStopBit; - config->bitCountPerChar = kUSART_8BitsPerChar; - config->loopback = false; - config->enableRx = false; - config->enableTx = false; - config->enableMode32k = false; - config->txWatermark = kUSART_TxFifo0; - config->rxWatermark = kUSART_RxFifo1; - config->syncMode = kUSART_SyncModeDisabled; - config->enableContinuousSCLK = false; - config->clockPolarity = kUSART_RxSampleOnFallingEdge; - config->enableHardwareFlowControl = false; -} - -/*! - * brief Sets the USART instance baud rate. - * - * This function configures the USART module baud rate. This function is used to update - * the USART module baud rate after the USART module is initialized by the USART_Init. - * code - * USART_SetBaudRate(USART1, 115200U, 20000000U); - * endcode - * - * param base USART peripheral base address. - * param baudrate_Bps USART baudrate to be set. - * param srcClock_Hz USART clock source frequency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_Success Set baudrate succeed. - * retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) -{ - uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1; - uint32_t osrval, brgval, diff, baudrate; - - /* check arguments */ - assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))); - if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* If synchronous master mode is enabled, only configure the BRG value. */ - if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U) - { - if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U) - { - brgval = srcClock_Hz / baudrate_Bps; - base->BRG = brgval - 1U; - } - } - else - { - /* - * Smaller values of OSR can make the sampling position within a data bit less accurate and may - * potentially cause more noise errors or incorrect data. - */ - for (osrval = best_osrval; osrval >= 8U; osrval--) - { - brgval = (((srcClock_Hz * 10U) / ((osrval + 1U) * baudrate_Bps)) - 5U) / 10U; - if (brgval > 0xFFFFU) - { - continue; - } - baudrate = srcClock_Hz / ((osrval + 1U) * (brgval + 1U)); - diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); - if (diff < best_diff) - { - best_diff = diff; - best_osrval = osrval; - best_brgval = brgval; - } - } - - /* Check to see if actual baud rate is within 3% of desired baud rate - * based on the best calculated OSR and BRG value */ - baudrate = srcClock_Hz / ((best_osrval + 1U) * (best_brgval + 1U)); - diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); - if (diff > ((baudrate_Bps / 100U) * 3U)) - { - return kStatus_USART_BaudrateNotSupport; - } - - /* value over range */ - if (best_brgval > 0xFFFFU) - { - return kStatus_USART_BaudrateNotSupport; - } - - base->OSR = best_osrval; - base->BRG = best_brgval; - } - - return kStatus_Success; -} - -/*! - * brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source. - * - * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator - * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting - * SYSCON_RTCOSCCTRL_EN bit to 1. - * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that - * 9600 can evenly divide, eg: 4800, 3200. - * - * param base USART peripheral base address. - * param baudRate_Bps USART baudrate to be set.. - * param enableMode32k true is 32k mode, false is normal mode. - * param srcClock_Hz USART clock source frequency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_Success Set baudrate succeed. - * retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz) -{ - status_t result = kStatus_Success; - base->CFG &= ~(USART_CFG_ENABLE_MASK); - if (enableMode32k) - { - base->CFG |= USART_CFG_MODE32K_MASK; - if ((9600U % baudRate_Bps) == 0U) - { - base->BRG = 9600U / baudRate_Bps - 1U; - } - else - { - return kStatus_USART_BaudrateNotSupport; - } - } - else - { - base->CFG &= ~(USART_CFG_MODE32K_MASK); - result = USART_SetBaudRate(base, baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - } - base->CFG |= USART_CFG_ENABLE_MASK; - return result; -} - -/*! - * brief Enable 9-bit data mode for USART. - * - * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user. - * - * param base USART peripheral base address. - * param enable true to enable, false to disable. - */ -void USART_Enable9bitMode(USART_Type *base, bool enable) -{ - assert(base != NULL); - - uint32_t temp = 0U; - - if (enable) - { - /* Set USART 9-bit mode, disable parity. */ - temp = base->CFG & ~((uint32_t)USART_CFG_DATALEN_MASK | (uint32_t)USART_CFG_PARITYSEL_MASK); - temp |= (uint32_t)USART_CFG_DATALEN(0x2U); - base->CFG = temp; - } - else - { - /* Set USART to 8-bit mode. */ - base->CFG &= ~((uint32_t)USART_CFG_DATALEN_MASK); - base->CFG |= (uint32_t)USART_CFG_DATALEN(0x1U); - } -} - -/*! - * brief Transmit an address frame in 9-bit data mode. - * - * param base USART peripheral base address. - * param address USART slave address. - */ -void USART_SendAddress(USART_Type *base, uint8_t address) -{ - assert(base != NULL); - base->FIFOWR = ((uint32_t)address | 0x100UL); -} - -/*! - * brief Writes to the TX register using a blocking method. - * - * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO - * to have room and writes data to the TX buffer. - * - * param base USART peripheral base address. - * param data Start address of the data to write. - * param length Size of the data to write. - * retval kStatus_USART_Timeout Transmission timed out and was aborted. - * retval kStatus_InvalidArgument Invalid argument. - * retval kStatus_Success Successfully wrote all data. - */ -status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) -{ - /* Check arguments */ - assert(!((NULL == base) || (NULL == data))); -#if UART_RETRY_TIMES - uint32_t waitTimes; -#endif - if ((NULL == base) || (NULL == data)) - { - return kStatus_InvalidArgument; - } - /* Check whether txFIFO is enabled */ - if (0U == (base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK)) - { - return kStatus_InvalidArgument; - } - for (; length > 0U; length--) - { - /* Loop until txFIFO get some space for new data */ -#if UART_RETRY_TIMES - waitTimes = UART_RETRY_TIMES; - while ((0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) && (--waitTimes != 0U)) -#else - while (0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) -#endif - { - } -#if UART_RETRY_TIMES - if (0U == waitTimes) - { - return kStatus_USART_Timeout; - } -#endif - base->FIFOWR = *data; - data++; - } - /* Wait to finish transfer */ -#if UART_RETRY_TIMES - waitTimes = UART_RETRY_TIMES; - while ((0U == (base->STAT & USART_STAT_TXIDLE_MASK)) && (--waitTimes != 0U)) -#else - while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) -#endif - { - } -#if UART_RETRY_TIMES - if (0U == waitTimes) - { - return kStatus_USART_Timeout; - } -#endif - return kStatus_Success; -} - -/*! - * brief Read RX data register using a blocking method. - * - * This function polls the RX register, waits for the RX register to be full or for RX FIFO to - * have data and read data from the TX register. - * - * param base USART peripheral base address. - * param data Start address of the buffer to store the received data. - * param length Size of the buffer. - * retval kStatus_USART_FramingError Receiver overrun happened while receiving data. - * retval kStatus_USART_ParityError Noise error happened while receiving data. - * retval kStatus_USART_NoiseError Framing error happened while receiving data. - * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. - * retval kStatus_USART_Timeout Transmission timed out and was aborted. - * retval kStatus_Success Successfully received all data. - */ -status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) -{ - uint32_t statusFlag; - status_t status = kStatus_Success; -#if UART_RETRY_TIMES - uint32_t waitTimes; -#endif - - /* check arguments */ - assert(!((NULL == base) || (NULL == data))); - if ((NULL == base) || (NULL == data)) - { - return kStatus_InvalidArgument; - } - - /* Check whether rxFIFO is enabled */ - if ((base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK) == 0U) - { - return kStatus_Fail; - } - for (; length > 0U; length--) - { - /* loop until rxFIFO have some data to read */ -#if UART_RETRY_TIMES - waitTimes = UART_RETRY_TIMES; - while (((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) && (--waitTimes != 0U)) -#else - while ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) -#endif - { - } -#if UART_RETRY_TIMES - if (waitTimes == 0U) - { - status = kStatus_USART_Timeout; - break; - } -#endif - /* check rxFIFO statusFlag */ - if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) - { - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; - status = kStatus_USART_RxError; - break; - } - /* check receive statusFlag */ - statusFlag = base->STAT; - /* Clear all status flags */ - base->STAT |= statusFlag; - if ((statusFlag & USART_STAT_PARITYERRINT_MASK) != 0U) - { - status = kStatus_USART_ParityError; - } - if ((statusFlag & USART_STAT_FRAMERRINT_MASK) != 0U) - { - status = kStatus_USART_FramingError; - } - if ((statusFlag & USART_STAT_RXNOISEINT_MASK) != 0U) - { - status = kStatus_USART_NoiseError; - } - - if (kStatus_Success == status) - { - *data = (uint8_t)base->FIFORD; - data++; - } - else - { - break; - } - } - return status; -} - -/*! - * brief Initializes the USART handle. - * - * This function initializes the USART handle which can be used for other USART - * transactional APIs. Usually, for a specified USART instance, - * call this API once to get the initialized handle. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param callback The callback function. - * param userData The parameter of the callback function. - */ -status_t USART_TransferCreateHandle(USART_Type *base, - usart_handle_t *handle, - usart_transfer_callback_t callback, - void *userData) -{ - /* Check 'base' */ - assert(!((NULL == base) || (NULL == handle))); - - uint32_t instance = 0; - usart_to_flexcomm_t handler; - handler.usart_master_handler = USART_TransferHandleIRQ; - - if ((NULL == base) || (NULL == handle)) - { - return kStatus_InvalidArgument; - } - - instance = USART_GetInstance(base); - - (void)memset(handle, 0, sizeof(*handle)); - /* Set the TX/RX state. */ - handle->rxState = (uint8_t)kUSART_RxIdle; - handle->txState = (uint8_t)kUSART_TxIdle; - /* Set the callback and user data. */ - handle->callback = callback; - handle->userData = userData; - handle->rxWatermark = (uint8_t)USART_FIFOTRIG_RXLVL_GET(base); - handle->txWatermark = (uint8_t)USART_FIFOTRIG_TXLVL_GET(base); - - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - - /* Enable interrupt in NVIC. */ - (void)EnableIRQ(s_usartIRQ[instance]); - - return kStatus_Success; -} - -/*! - * brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in the IRQ handler, the USART driver calls the callback - * function and passes the ref kStatus_USART_TxIdle as status parameter. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART transfer structure. See #usart_transfer_t. - * retval kStatus_Success Successfully start the data transmission. - * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer) -{ - /* Check arguments */ - assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - /* Check xfer members */ - assert(!((0U == xfer->dataSize) || (NULL == xfer->txData))); - if ((0U == xfer->dataSize) || (NULL == xfer->txData)) - { - return kStatus_InvalidArgument; - } - - /* Return error if current TX busy. */ - if ((uint8_t)kUSART_TxBusy == handle->txState) - { - return kStatus_USART_TxBusy; - } - else - { - /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up the - * handle value. */ - uint32_t interruptMask = USART_GetEnabledInterrupts(base); - USART_DisableInterrupts(base, interruptMask); - handle->txData = xfer->txData; - handle->txDataSize = xfer->dataSize; - handle->txDataSizeAll = xfer->dataSize; - handle->txState = (uint8_t)kUSART_TxBusy; - /* Enable transmiter interrupt and the previously disabled interrupt. */ - USART_EnableInterrupts(base, interruptMask | (uint32_t)kUSART_TxLevelInterruptEnable); - } - return kStatus_Success; -} - -/*! - * brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out - * how many bytes are still not sent out. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) -{ - assert(NULL != handle); - - /* Disable interrupts */ - USART_DisableInterrupts(base, (uint32_t)kUSART_TxLevelInterruptEnable); - /* Empty txFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK; - - handle->txDataSize = 0U; - handle->txState = (uint8_t)kUSART_TxIdle; -} - -/*! - * brief Get the number of bytes that have been sent out to bus. - * - * This function gets the number of bytes that have been sent out to bus by interrupt method. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Send bytes count. - * retval kStatus_NoTransferInProgress No send in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != count); - - if ((uint8_t)kUSART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - handle->txDataSize - - ((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); - - return kStatus_Success; -} - -/*! - * brief Receives a buffer of data using an interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function, which - * returns without waiting for all data to be received. - * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and - * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in the ring buffer is not enough to read, the receive - * request is saved by the USART driver. When the new data arrives, the receive request - * is serviced first. When all data is received, the USART driver notifies the upper layer - * through a callback function and passes the status parameter ref kStatus_USART_RxIdle. - * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. - * The 5 bytes are copied to the xfer->data and this function returns with the - * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is - * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to the xfer->data. When all data is received, the upper layer is notified. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART transfer structure, see #usart_transfer_t. - * param receivedBytes Bytes received from the ring buffer directly. - * retval kStatus_Success Successfully queue the transfer into transmit queue. - * retval kStatus_USART_RxBusy Previous receive request is not finished. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveNonBlocking(USART_Type *base, - usart_handle_t *handle, - usart_transfer_t *xfer, - size_t *receivedBytes) -{ - uint32_t i; - /* How many bytes to copy from ring buffer to user memory. */ - size_t bytesToCopy = 0U; - /* How many bytes to receive. */ - size_t bytesToReceive; - /* How many bytes currently have received. */ - size_t bytesCurrentReceived; - uint32_t interruptMask = 0U; - - /* Check arguments */ - assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - /* Check xfer members */ - assert(!((0U == xfer->dataSize) || (NULL == xfer->rxData))); - if ((0U == xfer->dataSize) || (NULL == xfer->rxData)) - { - return kStatus_InvalidArgument; - } - - /* Enable address detect when address match is enabled. */ - if ((base->CFG & (uint32_t)USART_CFG_AUTOADDR_MASK) != 0U) - { - base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK; - } - - /* How to get data: - 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize - to uart handle, enable interrupt to store received data to xfer->data. When - all data received, trigger callback. - 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. - If there are enough data in ring buffer, copy them to xfer->data and return. - If there are not enough data in ring buffer, copy all of them to xfer->data, - save the xfer->data remained empty space to uart handle, receive data - to this empty space and trigger callback when finished. */ - if ((uint8_t)kUSART_RxBusy == handle->rxState) - { - return kStatus_USART_RxBusy; - } - else - { - bytesToReceive = xfer->dataSize; - bytesCurrentReceived = 0U; - /* If RX ring buffer is used. */ - if (handle->rxRingBuffer != NULL) - { - /* Disable IRQ, protect ring buffer. */ - interruptMask = USART_GetEnabledInterrupts(base); - USART_DisableInterrupts(base, interruptMask); - - /* How many bytes in RX ring buffer currently. */ - bytesToCopy = USART_TransferGetRxRingBufferLength(handle); - if (bytesToCopy != 0U) - { - bytesToCopy = MIN(bytesToReceive, bytesToCopy); - bytesToReceive -= bytesToCopy; - /* Copy data from ring buffer to user memory. */ - for (i = 0U; i < bytesToCopy; i++) - { - xfer->rxData[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; - /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ - if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - } - /* If ring buffer does not have enough data, still need to read more data. */ - if (bytesToReceive != 0U) - { - /* No data in ring buffer, save the request to UART handle. */ - handle->rxData = xfer->rxData + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = xfer->dataSize; - handle->rxState = (uint8_t)kUSART_RxBusy; - } - /* Re-enable IRQ. */ - USART_EnableInterrupts(base, interruptMask); - /* Call user callback since all data are received. */ - if (0U == bytesToReceive) - { - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); - } - } - } - /* Ring buffer not used. */ - else - { - /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up - * the handle value. */ - interruptMask = USART_GetEnabledInterrupts(base); - USART_DisableInterrupts(base, interruptMask); - handle->rxData = xfer->rxData + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = (uint8_t)kUSART_RxBusy; - - /* Enable RX interrupt. */ - base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK; - /* Re-enable IRQ. */ - USART_EnableInterrupts(base, interruptMask); - } - /* Return the how many bytes have read. */ - if (receivedBytes != NULL) - { - *receivedBytes = bytesCurrentReceived; - } - } - return kStatus_Success; -} - -/*! - * brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out - * how many bytes not received yet. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) -{ - assert(NULL != handle); - - /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ - if (NULL == handle->rxRingBuffer) - { - /* Disable interrupts */ - USART_DisableInterrupts(base, (uint32_t)kUSART_RxLevelInterruptEnable); - /* Empty rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - } - - handle->rxDataSize = 0U; - handle->rxState = (uint8_t)kUSART_RxIdle; -} - -/*! - * brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Receive bytes count. - * retval kStatus_NoTransferInProgress No receive in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != count); - - if ((uint8_t)kUSART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - handle->rxDataSize; - - return kStatus_Success; -} - -/*! - * brief USART IRQ handle function. - * - * This function handles the USART transmit and receive IRQ request. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) -{ - /* Check arguments */ - assert((NULL != base) && (NULL != handle)); - - bool receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); - bool sendEnabled = (handle->txDataSize != 0U); - uint8_t rxdata; - size_t tmpsize; - - /* If RX overrun. */ - if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) - { - /* Clear rx error state. */ - base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxError, handle->userData); - } - } - /* TX under run, happens when slave is in synchronous mode and the data is not written in tx register in time. */ - if ((base->FIFOSTAT & USART_FIFOSTAT_TXERR_MASK) != 0U) - { - /* Clear tx error state. */ - base->FIFOSTAT |= USART_FIFOSTAT_TXERR_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_TxError, handle->userData); - } - } - /* If noise error. */ - if ((base->STAT & USART_STAT_RXNOISEINT_MASK) != 0U) - { - /* Clear rx error state. */ - base->STAT |= USART_STAT_RXNOISEINT_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_NoiseError, handle->userData); - } - } - /* If framing error. */ - if ((base->STAT & USART_STAT_FRAMERRINT_MASK) != 0U) - { - /* Clear rx error state. */ - base->STAT |= USART_STAT_FRAMERRINT_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_FramingError, handle->userData); - } - } - /* If parity error. */ - if ((base->STAT & USART_STAT_PARITYERRINT_MASK) != 0U) - { - /* Clear rx error state. */ - base->STAT |= USART_STAT_PARITYERRINT_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_ParityError, handle->userData); - } - } - while ((receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) || - (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U))) - { - /* Receive data */ - if (receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) - { - /* Clear address detect when RXFIFO has data. */ - base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK; - /* Receive to app bufffer if app buffer is present */ - if (handle->rxDataSize != 0U) - { - rxdata = (uint8_t)base->FIFORD; - *handle->rxData = rxdata; - handle->rxDataSize--; - handle->rxData++; - receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); - if (0U == handle->rxDataSize) - { - if (NULL == handle->rxRingBuffer) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; - } - handle->rxState = (uint8_t)kUSART_RxIdle; - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); - } - } - } - /* Otherwise receive to ring buffer if ring buffer is present */ - else - { - if (handle->rxRingBuffer != NULL) - { - /* If RX ring buffer is full, trigger callback to notify over run. */ - if (USART_TransferIsRxRingBufferFull(handle)) - { - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData); - } - } - /* If ring buffer is still full after callback function, the oldest data is overridden. */ - if (USART_TransferIsRxRingBufferFull(handle)) - { - /* Increase handle->rxRingBufferTail to make room for new data. */ - if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - /* Read data. */ - rxdata = (uint8_t)base->FIFORD; - handle->rxRingBuffer[handle->rxRingBufferHead] = rxdata; - /* Increase handle->rxRingBufferHead. */ - if ((size_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferHead = 0U; - } - else - { - handle->rxRingBufferHead++; - } - } - } - } - /* Send data */ - if (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U)) - { - base->FIFOWR = *handle->txData; - handle->txDataSize--; - handle->txData++; - sendEnabled = handle->txDataSize != 0U; - if (!sendEnabled) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK; - - base->INTENSET = USART_INTENSET_TXIDLEEN_MASK; - } - } - } - - /* Tx idle and the interrupt is enabled. */ - if ((0U != (base->INTENSET & USART_INTENSET_TXIDLEEN_MASK)) && (0U != (base->INTSTAT & USART_INTSTAT_TXIDLE_MASK))) - { - /* Set txState to idle only when all data has been sent out to bus. */ - handle->txState = (uint8_t)kUSART_TxIdle; - /* Disable tx idle interrupt */ - base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK; - - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); - } - } - - /* ring buffer is not used */ - if (NULL == handle->rxRingBuffer) - { - tmpsize = handle->rxDataSize; - - /* restore if rx transfer ends and rxLevel is different from default value */ - if ((tmpsize == 0U) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark)) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark); - } - /* decrease level if rx transfer is bellow */ - if ((tmpsize != 0U) && (tmpsize < (USART_FIFOTRIG_RXLVL_GET(base) + 1U))) - { - base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(tmpsize - 1U)); - } - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_usart.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_usart.h deleted file mode 100644 index ef4715c4c5c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_usart.h +++ /dev/null @@ -1,903 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_USART_H_ -#define _FSL_USART_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup usart_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief USART driver version. */ -#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 7, 0)) -/*@}*/ - -#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT) -#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT) - -/*! @brief Retry times for waiting flag. */ -#ifndef UART_RETRY_TIMES -#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */ -#endif - -/*! @brief Error codes for the USART driver. */ -enum -{ - kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */ - kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */ - kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */ - kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */ - kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */ - kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */ - kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */ - kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */ - kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */ - kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */ - kStatus_USART_BaudrateNotSupport = - MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */ -#if UART_RETRY_TIMES - kStatus_USART_Timeout = MAKE_STATUS(kStatusGroup_LPC_USART, 14), /*!< USART time out. */ -#endif -}; - -/*! @brief USART synchronous mode. */ -typedef enum _usart_sync_mode -{ - kUSART_SyncModeDisabled = 0x0U, /*!< Asynchronous mode. */ - kUSART_SyncModeSlave = 0x2U, /*!< Synchronous slave mode. */ - kUSART_SyncModeMaster = 0x3U, /*!< Synchronous master mode. */ -} usart_sync_mode_t; - -/*! @brief USART parity mode. */ -typedef enum _usart_parity_mode -{ - kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */ - kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ - kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ -} usart_parity_mode_t; - -/*! @brief USART stop bit count. */ -typedef enum _usart_stop_bit_count -{ - kUSART_OneStopBit = 0U, /*!< One stop bit */ - kUSART_TwoStopBit = 1U, /*!< Two stop bits */ -} usart_stop_bit_count_t; - -/*! @brief USART data size. */ -typedef enum _usart_data_len -{ - kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */ - kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */ -} usart_data_len_t; - -/*! @brief USART clock polarity configuration, used in sync mode.*/ -typedef enum _usart_clock_polarity -{ - kUSART_RxSampleOnFallingEdge = 0x0U, /*!< Un_RXD is sampled on the falling edge of SCLK. */ - kUSART_RxSampleOnRisingEdge = 0x1U, /*!< Un_RXD is sampled on the rising edge of SCLK. */ -} usart_clock_polarity_t; - -/*! @brief txFIFO watermark values */ -typedef enum _usart_txfifo_watermark -{ - kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */ - kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */ - kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */ - kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */ - kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */ - kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */ - kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */ - kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */ -} usart_txfifo_watermark_t; - -/*! @brief rxFIFO watermark values */ -typedef enum _usart_rxfifo_watermark -{ - kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */ - kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */ - kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */ - kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */ - kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */ - kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */ - kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */ - kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */ -} usart_rxfifo_watermark_t; - -/*! - * @brief USART interrupt configuration structure, default settings all disabled. - */ -enum _usart_interrupt_enable -{ - kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK), - kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK), - kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK), - kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK), - kUSART_TxIdleInterruptEnable = (USART_INTENSET_TXIDLEEN_MASK << 16U), /*!< Transmitter idle. */ - kUSART_CtsChangeInterruptEnable = - (USART_INTENSET_DELTACTSEN_MASK << 16U), /*!< Change in the state of the CTS input. */ - kUSART_RxBreakChangeInterruptEnable = - (USART_INTENSET_DELTARXBRKEN_MASK), /*!< Break condition asserted or deasserted. */ - kUSART_RxStartInterruptEnable = (USART_INTENSET_STARTEN_MASK), /*!< Rx start bit detected. */ - kUSART_FramingErrorInterruptEnable = (USART_INTENSET_FRAMERREN_MASK), /*!< Framing error detected. */ - kUSART_ParityErrorInterruptEnable = (USART_INTENSET_PARITYERREN_MASK), /*!< Parity error detected. */ - kUSART_NoiseErrorInterruptEnable = (USART_INTENSET_RXNOISEEN_MASK), /*!< Noise error detected. */ - kUSART_AutoBaudErrorInterruptEnable = (USART_INTENSET_ABERREN_MASK), /*!< Auto baudrate error detected. */ - - kUSART_AllInterruptEnables = - kUSART_TxErrorInterruptEnable | kUSART_RxErrorInterruptEnable | kUSART_TxLevelInterruptEnable | - kUSART_RxLevelInterruptEnable | kUSART_TxIdleInterruptEnable | kUSART_CtsChangeInterruptEnable | - kUSART_RxBreakChangeInterruptEnable | kUSART_RxStartInterruptEnable | kUSART_FramingErrorInterruptEnable | - kUSART_ParityErrorInterruptEnable | kUSART_NoiseErrorInterruptEnable | kUSART_AutoBaudErrorInterruptEnable, -}; - -/*! - * @brief USART status flags. - * - * This provides constants for the USART status flags for use in the USART functions. - */ -enum _usart_flags -{ - kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */ - kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */ - kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */ - kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */ - kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */ - kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */ - kUSART_RxIdleFlag = (USART_STAT_RXIDLE_MASK << 16U), /*!< Receiver idle. */ - kUSART_TxIdleFlag = (USART_STAT_TXIDLE_MASK << 16U), /*!< Transmitter idle. */ - kUSART_CtsAssertFlag = (USART_STAT_CTS_MASK << 16U), /*!< CTS signal high. */ - kUSART_CtsChangeFlag = (USART_STAT_DELTACTS_MASK << 16U), /*!< CTS signal changed interrupt status. */ - kUSART_BreakDetectFlag = (USART_STAT_RXBRK_MASK), /*!< Break detected. Self cleared when rx pin goes high again. */ - kUSART_BreakDetectChangeFlag = (USART_STAT_DELTARXBRK_MASK), /*!< Break detect change interrupt flag. A change in - the state of receiver break detection. */ - kUSART_RxStartFlag = (USART_STAT_START_MASK), /*!< Rx start bit detected interrupt flag. */ - kUSART_FramingErrorFlag = (USART_STAT_FRAMERRINT_MASK), /*!< Framing error interrupt flag. */ - kUSART_ParityErrorFlag = (USART_STAT_PARITYERRINT_MASK), /*!< parity error interrupt flag. */ - kUSART_NoiseErrorFlag = (USART_STAT_RXNOISEINT_MASK), /*!< Noise error interrupt flag. */ - kUSART_AutobaudErrorFlag = (USART_STAT_ABERR_MASK), /*!< Auto baudrate error interrupt flag, caused by the baudrate - counter timeout before the end of start bit. */ - - kUSART_AllClearFlags = kUSART_TxError | kUSART_RxError | kUSART_CtsChangeFlag | kUSART_BreakDetectChangeFlag | - kUSART_RxStartFlag | kUSART_FramingErrorFlag | kUSART_ParityErrorFlag | - kUSART_NoiseErrorFlag | kUSART_AutobaudErrorFlag, -}; - -/*! @brief USART configuration structure. */ -typedef struct _usart_config -{ - uint32_t baudRate_Bps; /*!< USART baud rate */ - usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ - usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ - usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */ - bool loopback; /*!< Enable peripheral loopback */ - bool enableRx; /*!< Enable RX */ - bool enableTx; /*!< Enable TX */ - bool enableContinuousSCLK; /*!< USART continuous Clock generation enable in synchronous master mode. */ - bool enableMode32k; /*!< USART uses 32 kHz clock from the RTC oscillator as the clock source. */ - bool enableHardwareFlowControl; /*!< Enable hardware control RTS/CTS */ - usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ - usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */ - usart_clock_polarity_t clockPolarity; /*!< Selects the clock polarity and sampling edge in synchronous mode. */ -} usart_config_t; - -/*! @brief USART transfer structure. */ -typedef struct _usart_transfer -{ - /* - * Use separate TX and RX data pointer, because TX data is const data. - * The member data is kept for backward compatibility. - */ - union - { - uint8_t *data; /*!< The buffer of data to be transfer.*/ - uint8_t *rxData; /*!< The buffer to receive data. */ - const uint8_t *txData; /*!< The buffer of data to be sent. */ - }; - size_t dataSize; /*!< The byte count to be transfer. */ -} usart_transfer_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _usart_handle usart_handle_t; - -/*! @brief USART transfer callback function. */ -typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData); - -/*! @brief USART handle structure. */ -struct _usart_handle -{ - const uint8_t *volatile txData; /*!< Address of remaining data to send. */ - volatile size_t txDataSize; /*!< Size of the remaining data to send. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ - volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - - uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ - size_t rxRingBufferSize; /*!< Size of the ring buffer. */ - volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ - volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ - - usart_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< USART callback function parameter.*/ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ - - uint8_t txWatermark; /*!< txFIFO watermark */ - uint8_t rxWatermark; /*!< rxFIFO watermark */ -}; - -/*! @brief Typedef for usart interrupt handler. */ -typedef void (*flexcomm_usart_irq_handler_t)(USART_Type *base, usart_handle_t *handle); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! @brief Returns instance number for USART peripheral base address. */ -uint32_t USART_GetInstance(USART_Type *base); - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes a USART instance with user configuration structure and peripheral clock. - * - * This function configures the USART module with the user-defined settings. The user can configure the configuration - * structure and also get the default configuration by using the USART_GetDefaultConfig() function. - * Example below shows how to use this API to configure USART. - * @code - * usart_config_t usartConfig; - * usartConfig.baudRate_Bps = 115200U; - * usartConfig.parityMode = kUSART_ParityDisabled; - * usartConfig.stopBitCount = kUSART_OneStopBit; - * USART_Init(USART1, &usartConfig, 20000000U); - * @endcode - * - * @param base USART peripheral base address. - * @param config Pointer to user-defined configuration structure. - * @param srcClock_Hz USART clock source frequency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_InvalidArgument USART base address is not valid - * @retval kStatus_Success Status USART initialize succeed - */ -status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes a USART instance. - * - * This function waits for TX complete, disables TX and RX, and disables the USART clock. - * - * @param base USART peripheral base address. - */ -void USART_Deinit(USART_Type *base); - -/*! - * @brief Gets the default configuration structure. - * - * This function initializes the USART configuration structure to a default value. The default - * values are: - * usartConfig->baudRate_Bps = 115200U; - * usartConfig->parityMode = kUSART_ParityDisabled; - * usartConfig->stopBitCount = kUSART_OneStopBit; - * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; - * usartConfig->loopback = false; - * usartConfig->enableTx = false; - * usartConfig->enableRx = false; - * - * @param config Pointer to configuration structure. - */ -void USART_GetDefaultConfig(usart_config_t *config); - -/*! - * @brief Sets the USART instance baud rate. - * - * This function configures the USART module baud rate. This function is used to update - * the USART module baud rate after the USART module is initialized by the USART_Init. - * @code - * USART_SetBaudRate(USART1, 115200U, 20000000U); - * @endcode - * - * @param base USART peripheral base address. - * @param baudrate_Bps USART baudrate to be set. - * @param srcClock_Hz USART clock source frequency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_Success Set baudrate succeed. - * @retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source - * - * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator - * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting - * SYSCON_RTCOSCCTRL_EN bit to 1. - * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that - * 9600 can evenly divide, eg: 4800, 3200. - * - * @param base USART peripheral base address. - * @param baudRate_Bps USART baudrate to be set.. - * @param enableMode32k true is 32k mode, false is normal mode. - * @param srcClock_Hz USART clock source frequency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_Success Set baudrate succeed. - * @retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz); - -/*! - * @brief Enable 9-bit data mode for USART. - * - * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user. - * - * @param base USART peripheral base address. - * @param enable true to enable, false to disable. - */ -void USART_Enable9bitMode(USART_Type *base, bool enable); - -/*! - * @brief Set the USART slave address. - * - * This function configures the address for USART module that works as slave in 9-bit data mode. When the address - * detection is enabled, the frame it receices with MSB being 1 is considered as an address frame, otherwise it is - * considered as data frame. Once the address frame matches slave's own addresses, this slave is addressed. This - * address frame and its following data frames are stored in the receive buffer, otherwise the frames will be discarded. - * To un-address a slave, just send an address frame with unmatched address. - * - * @note Any USART instance joined in the multi-slave system can work as slave. The position of the address mark is the - * same as the parity bit when parity is enabled for 8 bit and 9 bit data formats. - * - * @param base USART peripheral base address. - * @param address USART slave address. - */ -static inline void USART_SetMatchAddress(USART_Type *base, uint8_t address) -{ - /* Configure match address. */ - base->ADDR = (uint32_t)address; -} - -/*! - * @brief Enable the USART match address feature. - * - * @param base USART peripheral base address. - * @param match true to enable match address, false to disable. - */ -static inline void USART_EnableMatchAddress(USART_Type *base, bool match) -{ - /* Configure match address enable bit. */ - if (match) - { - base->CFG |= (uint32_t)USART_CFG_AUTOADDR_MASK; - base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK; - } - else - { - base->CFG &= ~(uint32_t)USART_CFG_AUTOADDR_MASK; - base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK; - } -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Get USART status flags. - * - * This function get all USART status flags, the flags are returned as the logical - * OR value of the enumerators @ref _usart_flags. To check a specific status, - * compare the return value with enumerators in @ref _usart_flags. - * For example, to check whether the TX is empty: - * @code - * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1)) - * { - * ... - * } - * @endcode - * - * @param base USART peripheral base address. - * @return USART status flags which are ORed by the enumerators in the _usart_flags. - */ -static inline uint32_t USART_GetStatusFlags(USART_Type *base) -{ - return (base->FIFOSTAT & 0xFFUL) | (base->STAT & 0xFFUL) << 16U | (base->STAT & 0xFFFF00UL); -} - -/*! - * @brief Clear USART status flags. - * - * This function clear supported USART status flags - * Flags that can be cleared or set are: - * kUSART_TxError - * kUSART_RxError - * For example: - * @code - * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError) - * @endcode - * - * @param base USART peripheral base address. - * @param mask status flags to be cleared. - */ -static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask) -{ - mask &= (uint32_t)kUSART_AllClearFlags; - /* Clear the clearable status in STAT register. */ - base->STAT = (mask & 0xFFFF00UL) | ((mask & 0xFF0000UL) >> 16U); - /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */ - base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK); -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ -/*! - * @brief Enables USART interrupts according to the provided mask. - * - * This function enables the USART interrupts according to the provided mask. The mask - * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. - * For example, to enable TX empty interrupt and RX full interrupt: - * @code - * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); - * @endcode - * - * @param base USART peripheral base address. - * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable. - */ -static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) -{ - mask &= (uint32_t)kUSART_AllInterruptEnables; - base->INTENSET = (mask & 0x1FF00UL) | ((mask & 0xFF0000UL) >> 16U); - base->FIFOINTENSET = mask & 0xFUL; -} - -/*! - * @brief Disables USART interrupts according to a provided mask. - * - * This function disables the USART interrupts according to a provided mask. The mask - * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. - * This example shows how to disable the TX empty interrupt and RX full interrupt: - * @code - * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); - * @endcode - * - * @param base USART peripheral base address. - * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable. - */ -static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) -{ - mask &= (uint32_t)kUSART_AllInterruptEnables; - base->INTENCLR = (mask & 0x1FF00UL) | ((mask & 0xFF0000UL) >> 16U); - base->FIFOINTENCLR = mask & 0xFUL; -} - -/*! - * @brief Returns enabled USART interrupts. - * - * This function returns the enabled USART interrupts. - * - * @param base USART peripheral base address. - */ -static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base) -{ - return (base->INTENSET & 0x1FF00UL) | ((base->INTENSET & 0xFFUL) << 16UL) | (base->FIFOINTENSET & 0xFUL); -} - -/*! - * @brief Enable DMA for Tx - */ -static inline void USART_EnableTxDMA(USART_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK); - } -} - -/*! - * @brief Enable DMA for Rx - */ -static inline void USART_EnableRxDMA(USART_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK); - } -} - -/*! - * @brief Enable CTS. - * This function will determine whether CTS is used for flow control. - * - * @param base USART peripheral base address. - * @param enable Enable CTS or not, true for enable and false for disable. - */ -static inline void USART_EnableCTS(USART_Type *base, bool enable) -{ - if (enable) - { - base->CFG |= USART_CFG_CTSEN_MASK; - } - else - { - base->CFG &= ~USART_CFG_CTSEN_MASK; - } -} - -/*! - * @brief Continuous Clock generation. - * By default, SCLK is only output while data is being transmitted in synchronous mode. - * Enable this funciton, SCLK will run continuously in synchronous mode, allowing - * characters to be received on Un_RxD independently from transmission on Un_TXD). - * - * @param base USART peripheral base address. - * @param enable Enable Continuous Clock generation mode or not, true for enable and false for disable. - */ -static inline void USART_EnableContinuousSCLK(USART_Type *base, bool enable) -{ - if (enable) - { - base->CTL |= USART_CTL_CC_MASK; - } - else - { - base->CTL &= ~USART_CTL_CC_MASK; - } -} - -/*! - * @brief Enable Continuous Clock generation bit auto clear. - * While enable this cuntion, the Continuous Clock bit is automatically cleared when a complete - * character has been received. This bit is cleared at the same time. - * - * @param base USART peripheral base address. - * @param enable Enable auto clear or not, true for enable and false for disable. - */ -static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable) -{ - if (enable) - { - base->CTL |= USART_CTL_CLRCCONRX_MASK; - } - else - { - base->CTL &= ~USART_CTL_CLRCCONRX_MASK; - } -} - -/*! - * @brief Sets the rx FIFO watermark. - * - * @param base USART peripheral base address. - * @param water Rx FIFO watermark. - */ -static inline void USART_SetRxFifoWatermark(USART_Type *base, uint8_t water) -{ - assert(water <= (USART_FIFOTRIG_RXLVL_MASK >> USART_FIFOTRIG_RXLVL_SHIFT)); - base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_RXLVL_MASK) | USART_FIFOTRIG_RXLVL(water); -} - -/*! - * @brief Sets the tx FIFO watermark. - * - * @param base USART peripheral base address. - * @param water Tx FIFO watermark. - */ -static inline void USART_SetTxFifoWatermark(USART_Type *base, uint8_t water) -{ - assert(water <= (USART_FIFOTRIG_TXLVL_MASK >> USART_FIFOTRIG_TXLVL_SHIFT)); - base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_TXLVL_MASK) | USART_FIFOTRIG_TXLVL(water); -} -/* @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Writes to the FIFOWR register. - * - * This function writes data to the txFIFO directly. The upper layer must ensure - * that txFIFO has space for data to write before calling this function. - * - * @param base USART peripheral base address. - * @param data The byte to write. - */ -static inline void USART_WriteByte(USART_Type *base, uint8_t data) -{ - base->FIFOWR = data; -} - -/*! - * @brief Reads the FIFORD register directly. - * - * This function reads data from the rxFIFO directly. The upper layer must - * ensure that the rxFIFO is not empty before calling this function. - * - * @param base USART peripheral base address. - * @return The byte read from USART data register. - */ -static inline uint8_t USART_ReadByte(USART_Type *base) -{ - return (uint8_t)base->FIFORD; -} - -/*! - * @brief Gets the rx FIFO data count. - * - * @param base USART peripheral base address. - * @return rx FIFO data count. - */ -static inline uint8_t USART_GetRxFifoCount(USART_Type *base) -{ - return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_RXLVL_MASK) >> USART_FIFOSTAT_RXLVL_SHIFT); -} - -/*! - * @brief Gets the tx FIFO data count. - * - * @param base USART peripheral base address. - * @return tx FIFO data count. - */ -static inline uint8_t USART_GetTxFifoCount(USART_Type *base) -{ - return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); -} - -/*! - * @brief Transmit an address frame in 9-bit data mode. - * - * @param base USART peripheral base address. - * @param address USART slave address. - */ -void USART_SendAddress(USART_Type *base, uint8_t address); - -/*! - * @brief Writes to the TX register using a blocking method. - * - * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO - * to have room and writes data to the TX buffer. - * - * @param base USART peripheral base address. - * @param data Start address of the data to write. - * @param length Size of the data to write. - * @retval kStatus_USART_Timeout Transmission timed out and was aborted. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_Success Successfully wrote all data. - */ -status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length); - -/*! - * @brief Read RX data register using a blocking method. - * - * This function polls the RX register, waits for the RX register to be full or for RX FIFO to - * have data and read data from the TX register. - * - * @param base USART peripheral base address. - * @param data Start address of the buffer to store the received data. - * @param length Size of the buffer. - * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data. - * @retval kStatus_USART_ParityError Noise error happened while receiving data. - * @retval kStatus_USART_NoiseError Framing error happened while receiving data. - * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. - * @retval kStatus_USART_Timeout Transmission timed out and was aborted. - * @retval kStatus_Success Successfully received all data. - */ -status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the USART handle. - * - * This function initializes the USART handle which can be used for other USART - * transactional APIs. Usually, for a specified USART instance, - * call this API once to get the initialized handle. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param callback The callback function. - * @param userData The parameter of the callback function. - */ -status_t USART_TransferCreateHandle(USART_Type *base, - usart_handle_t *handle, - usart_transfer_callback_t callback, - void *userData); - -/*! - * @brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in the IRQ handler, the USART driver calls the callback - * function and passes the @ref kStatus_USART_TxIdle as status parameter. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART transfer structure. See #usart_transfer_t. - * @retval kStatus_Success Successfully start the data transmission. - * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific USART handle. - * - * When the RX ring buffer is used, data received are stored into the ring buffer even when the - * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * - * @note When using the RX ring buffer, one byte is reserved for internal use. In other - * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. - * @param ringBufferSize size of the ring buffer. - */ -void USART_TransferStartRingBuffer(USART_Type *base, - usart_handle_t *handle, - uint8_t *ringBuffer, - size_t ringBufferSize); - -/*! - * @brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the length of received data in RX ring buffer. - * - * @param handle USART handle pointer. - * @return Length of received data in RX ring buffer. - */ -size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle); - -/*! - * @brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out - * how many bytes are still not sent out. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been sent out to bus. - * - * This function gets the number of bytes that have been sent out to bus by interrupt method. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Send bytes count. - * @retval kStatus_NoTransferInProgress No send in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); - -/*! - * @brief Receives a buffer of data using an interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function, which - * returns without waiting for all data to be received. - * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and - * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in the ring buffer is not enough to read, the receive - * request is saved by the USART driver. When the new data arrives, the receive request - * is serviced first. When all data is received, the USART driver notifies the upper layer - * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle. - * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. - * The 5 bytes are copied to the xfer->data and this function returns with the - * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is - * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to the xfer->data. When all data is received, the upper layer is notified. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART transfer structure, see #usart_transfer_t. - * @param receivedBytes Bytes received from the ring buffer directly. - * @retval kStatus_Success Successfully queue the transfer into transmit queue. - * @retval kStatus_USART_RxBusy Previous receive request is not finished. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveNonBlocking(USART_Type *base, - usart_handle_t *handle, - usart_transfer_t *xfer, - size_t *receivedBytes); - -/*! - * @brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out - * how many bytes not received yet. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); - -/*! - * @brief USART IRQ handle function. - * - * This function handles the USART transmit and receive IRQ request. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_USART_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_usart_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_usart_dma.c deleted file mode 100644 index 60c2d5284c5..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_usart_dma.c +++ /dev/null @@ -1,392 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_usart.h" -#include "fsl_device_registers.h" -#include "fsl_dma.h" -#include "fsl_flexcomm.h" -#include "fsl_usart_dma.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_dma" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ -enum -{ - kUSART_TxIdle, /* TX idle. */ - kUSART_TxBusy, /* TX busy. */ - kUSART_RxIdle, /* RX idle. */ - kUSART_RxBusy /* RX busy. */ -}; - -/*! @brief Typedef for usart DMA interrupt handler. */ -typedef void (*flexcomm_usart_dma_irq_handler_t)(USART_Type *base, usart_dma_handle_t *handle); - -/*base, false); - - /* Enable tx idle interrupt */ - usartPrivateHandle->base->INTENSET = USART_INTENSET_TXIDLEEN_MASK; -} - -static void USART_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode) -{ - assert(handle != NULL); - assert(param != NULL); - - usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param; - - /* Disable UART RX DMA. */ - USART_EnableRxDMA(usartPrivateHandle->base, false); - - usartPrivateHandle->handle->rxState = (uint8_t)kUSART_RxIdle; - - if (usartPrivateHandle->handle->callback != NULL) - { - usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_RxIdle, - usartPrivateHandle->handle->userData); - } -} - -/*! - * brief Initializes the USART handle which is used in transactional functions. - * param base USART peripheral base address. - * param handle Pointer to usart_dma_handle_t structure. - * param callback Callback function. - * param userData User data. - * param txDmaHandle User-requested DMA handle for TX DMA transfer. - * param rxDmaHandle User-requested DMA handle for RX DMA transfer. - */ -status_t USART_TransferCreateHandleDMA(USART_Type *base, - usart_dma_handle_t *handle, - usart_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *txDmaHandle, - dma_handle_t *rxDmaHandle) -{ - uint32_t instance = 0; - - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } - /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - instance = USART_GetInstance(base); - - (void)memset(handle, 0, sizeof(*handle)); - /* assign 'base' and 'handle' */ - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - /* set tx/rx 'idle' state */ - handle->rxState = (uint8_t)kUSART_RxIdle; - handle->txState = (uint8_t)kUSART_TxIdle; - - handle->callback = callback; - handle->userData = userData; - - handle->rxDmaHandle = rxDmaHandle; - handle->txDmaHandle = txDmaHandle; - - /* Set USART_TransferDMAHandleIRQ as DMA IRQ handler */ - usart_dma_to_flexcomm_t handler; - handler.usart_dma_handler = USART_TransferDMAHandleIRQ; - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - /* Enable NVIC IRQ. */ - (void)EnableIRQ(s_usartIRQ[instance]); - - /* Configure TX. */ - if (txDmaHandle != NULL) - { - DMA_SetCallback(txDmaHandle, USART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]); - } - - /* Configure RX. */ - if (rxDmaHandle != NULL) - { - DMA_SetCallback(rxDmaHandle, USART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]); - } - - return kStatus_Success; -} - -/*! - * brief Sends data using DMA. - * - * This function sends data using DMA. This is a non-blocking function, which returns - * right away. When all data is sent, the send callback function is called. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART DMA transfer structure. See #usart_transfer_t. - * retval kStatus_Success if succeed, others failed. - * retval kStatus_USART_TxBusy Previous transfer on going. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) -{ - assert(handle != NULL); - assert(handle->txDmaHandle != NULL); - assert(xfer != NULL); - assert(xfer->data != NULL); - assert(xfer->dataSize != 0U); - - dma_transfer_config_t xferConfig; - status_t status; - uint32_t address = (uint32_t)&base->FIFOWR; - - /* If previous TX not finished. */ - if ((uint8_t)kUSART_TxBusy == handle->txState) - { - status = kStatus_USART_TxBusy; - } - else - { - handle->txState = (uint8_t)kUSART_TxBusy; - handle->txDataSizeAll = xfer->dataSize; - - /* Enable DMA request from txFIFO */ - USART_EnableTxDMA(base, true); - - /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, xfer->data, (uint32_t *)address, sizeof(uint8_t), xfer->dataSize, - kDMA_MemoryToPeripheral, NULL); - - /* Submit transfer. */ - (void)DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); - DMA_StartTransfer(handle->txDmaHandle); - - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Receives data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * param base USART peripheral base address. - * param handle Pointer to usart_dma_handle_t structure. - * param xfer USART DMA transfer structure. See #usart_transfer_t. - * retval kStatus_Success if succeed, others failed. - * retval kStatus_USART_RxBusy Previous transfer on going. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) -{ - assert(handle != NULL); - assert(handle->rxDmaHandle != NULL); - assert(xfer != NULL); - assert(xfer->data != NULL); - assert(xfer->dataSize != 0U); - - dma_transfer_config_t xferConfig; - status_t status; - uint32_t address = (uint32_t)&base->FIFORD; - - /* If previous RX not finished. */ - if ((uint8_t)kUSART_RxBusy == handle->rxState) - { - status = kStatus_USART_RxBusy; - } - else - { - handle->rxState = (uint8_t)kUSART_RxBusy; - handle->rxDataSizeAll = xfer->dataSize; - - /* Enable DMA request from rxFIFO */ - USART_EnableRxDMA(base, true); - - /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, xfer->data, sizeof(uint8_t), xfer->dataSize, - kDMA_PeripheralToMemory, NULL); - - /* Submit transfer. */ - (void)DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); - DMA_StartTransfer(handle->rxDmaHandle); - - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Aborts the sent data using DMA. - * - * This function aborts send data using DMA. - * - * param base USART peripheral base address - * param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle) -{ - assert(NULL != handle); - assert(NULL != handle->txDmaHandle); - - /* Stop transfer. */ - DMA_AbortTransfer(handle->txDmaHandle); - handle->txState = (uint8_t)kUSART_TxIdle; -} - -/*! - * brief Aborts the received data using DMA. - * - * This function aborts the received data using DMA. - * - * param base USART peripheral base address - * param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle) -{ - assert(NULL != handle); - assert(NULL != handle->rxDmaHandle); - - /* Stop transfer. */ - DMA_AbortTransfer(handle->rxDmaHandle); - handle->rxState = (uint8_t)kUSART_RxIdle; -} - -/*! - * brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Receive bytes count. - * retval kStatus_NoTransferInProgress No receive in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != handle->rxDmaHandle); - assert(NULL != count); - - if ((uint8_t)kUSART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); - - return kStatus_Success; -} - -/*! - * brief Get the number of bytes that have been sent. - * - * This function gets the number of bytes that have been sent. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Sent bytes count. - * retval kStatus_NoTransferInProgress No receive in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != handle->txDmaHandle); - assert(NULL != count); - - if ((uint8_t)kUSART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel); - - return kStatus_Success; -} - -void USART_TransferDMAHandleIRQ(USART_Type *base, usart_dma_handle_t *handle) -{ - /* Check arguments */ - assert((NULL != base) && (NULL != handle)); - - /* Tx idle interrupt happens means that all the tx data have been sent out to bus, set the tx state to idle */ - handle->txState = (uint8_t)kUSART_TxIdle; - - /* Disable tx idle interrupt */ - base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK; - - /* Invoke callback */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_usart_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_usart_dma.h deleted file mode 100644 index 2166803b5f2..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_usart_dma.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_USART_DMA_H_ -#define _FSL_USART_DMA_H_ - -#include "fsl_common.h" -#include "fsl_dma.h" -#include "fsl_usart.h" - -/*! - * @addtogroup usart_dma_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief USART dma driver version. */ -#define FSL_USART_DMA_DRIVER_VERSION (MAKE_VERSION(2, 6, 0)) -/*@}*/ - -/* Forward declaration of the handle typedef. */ -typedef struct _usart_dma_handle usart_dma_handle_t; - -/*! @brief UART transfer callback function. */ -typedef void (*usart_dma_transfer_callback_t)(USART_Type *base, - usart_dma_handle_t *handle, - status_t status, - void *userData); - -/*! - * @brief UART DMA handle - */ -struct _usart_dma_handle -{ - USART_Type *base; /*!< UART peripheral base address. */ - - usart_dma_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< UART callback function parameter.*/ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - - dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */ - dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name DMA transactional - * @{ - */ - -/*! - * @brief Initializes the USART handle which is used in transactional functions. - * @param base USART peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param callback Callback function. - * @param userData User data. - * @param txDmaHandle User-requested DMA handle for TX DMA transfer. - * @param rxDmaHandle User-requested DMA handle for RX DMA transfer. - */ -status_t USART_TransferCreateHandleDMA(USART_Type *base, - usart_dma_handle_t *handle, - usart_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *txDmaHandle, - dma_handle_t *rxDmaHandle); - -/*! - * @brief Sends data using DMA. - * - * This function sends data using DMA. This is a non-blocking function, which returns - * right away. When all data is sent, the send callback function is called. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART DMA transfer structure. See #usart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_USART_TxBusy Previous transfer on going. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Receives data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * @param base USART peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param xfer USART DMA transfer structure. See #usart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_USART_RxBusy Previous transfer on going. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Aborts the sent data using DMA. - * - * This function aborts send data using DMA. - * - * @param base USART peripheral base address - * @param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle); - -/*! - * @brief Aborts the received data using DMA. - * - * This function aborts the received data using DMA. - * - * @param base USART peripheral base address - * @param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); - -/*! - * @brief Get the number of bytes that have been sent. - * - * This function gets the number of bytes that have been sent. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Sent bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_USART_DMA_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_utick.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_utick.c deleted file mode 100644 index 0eea419cd34..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_utick.c +++ /dev/null @@ -1,230 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019, 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_utick.h" -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG) -#include "fsl_power.h" -#endif -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.utick" -#endif - -/* Typedef for interrupt handler. */ -typedef void (*utick_isr_t)(UTICK_Type *base, utick_callback_t cb); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base UTICK peripheral base address - * - * @return The UTICK instance - */ -static uint32_t UTICK_GetInstance(UTICK_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of UTICK handle. */ -static utick_callback_t s_utickHandle[FSL_FEATURE_SOC_UTICK_COUNT]; -/* Array of UTICK peripheral base address. */ -static UTICK_Type *const s_utickBases[] = UTICK_BASE_PTRS; -/* Array of UTICK IRQ number. */ -static const IRQn_Type s_utickIRQ[] = UTICK_IRQS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of UTICK clock name. */ -static const clock_ip_name_t s_utickClock[] = UTICK_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) -/*! @brief Pointers to UTICK resets for each instance. */ -static const reset_ip_name_t s_utickResets[] = UTICK_RSTS; -#endif - -/* UTICK ISR for transactional APIs. */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -static utick_isr_t s_utickIsr = (utick_isr_t)DefaultISR; -#else -static utick_isr_t s_utickIsr; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t UTICK_GetInstance(UTICK_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_utickBases); instance++) - { - if (s_utickBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_utickBases)); - - return instance; -} - -/*! - * brief Starts UTICK. - * - * This function starts a repeat/onetime countdown with an optional callback - * - * param base UTICK peripheral base address. - * param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) - * return none - */ -void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb) -{ - uint32_t instance; - - /* Get instance from peripheral base address. */ - instance = UTICK_GetInstance(base); - - /* Save the handle in global variables to support the double weak mechanism. */ - s_utickHandle[instance] = cb; -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) && \ - !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)) - EnableDeepSleepIRQ(s_utickIRQ[instance]); -#else - (void)EnableIRQ(s_utickIRQ[instance]); -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT && !FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ - base->CTRL = count | UTICK_CTRL_REPEAT(mode); -} - -/*! - * brief Initializes an UTICK by turning its bus clock on - * - */ -void UTICK_Init(UTICK_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable utick clock */ - CLOCK_EnableClock(s_utickClock[UTICK_GetInstance(base)]); -#endif - -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) - RESET_PeripheralReset(s_utickResets[UTICK_GetInstance(base)]); -#endif - -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG) - /* Power up Watchdog oscillator*/ - POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC); -#endif - - s_utickIsr = UTICK_HandleIRQ; -} - -/*! - * brief Deinitializes a UTICK instance. - * - * This function shuts down Utick bus clock - * - * param base UTICK peripheral base address. - */ -void UTICK_Deinit(UTICK_Type *base) -{ - /* Turn off utick */ - base->CTRL = 0; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable utick clock */ - CLOCK_DisableClock(s_utickClock[UTICK_GetInstance(base)]); -#endif -} - -/*! - * brief Get Status Flags. - * - * This returns the status flag - * - * param base UTICK peripheral base address. - * return status register value - */ -uint32_t UTICK_GetStatusFlags(UTICK_Type *base) -{ - return (base->STAT); -} - -/*! - * brief Clear Status Interrupt Flags. - * - * This clears intr status flag - * - * param base UTICK peripheral base address. - * return none - */ -void UTICK_ClearStatusFlags(UTICK_Type *base) -{ - base->STAT = UTICK_STAT_INTR_MASK; -} - -/*! - * brief UTICK Interrupt Service Handler. - * - * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request - * in UTICK_SetTick()). - * if no user callback is scheduled, the interrupt will simply be cleared. - * - * param base UTICK peripheral base address. - * param cb callback scheduled for this instance of UTICK - * return none - */ -void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb) -{ - UTICK_ClearStatusFlags(base); - if (cb != NULL) - { - cb(); - } -} - -#if defined(UTICK0) -void UTICK0_DriverIRQHandler(void); -void UTICK0_DriverIRQHandler(void) -{ - s_utickIsr(UTICK0, s_utickHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif -#if defined(UTICK1) -void UTICK1_DriverIRQHandler(void); -void UTICK1_DriverIRQHandler(void) -{ - s_utickIsr(UTICK1, s_utickHandle[1]); - SDK_ISR_EXIT_BARRIER; -} -#endif -#if defined(UTICK2) -void UTICK2_DriverIRQHandler(void); -void UTICK2_DriverIRQHandler(void) -{ - s_utickIsr(UTICK2, s_utickHandle[2]); - SDK_ISR_EXIT_BARRIER; -} -#endif -#if defined(UTICK) -void UTICK_DriverIRQHandler(void); -void UTICK_DriverIRQHandler(void) -{ - s_utickIsr(UTICK, s_utickHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_utick.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_utick.h deleted file mode 100644 index 48c7d6b86de..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_utick.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019, 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_UTICK_H_ -#define _FSL_UTICK_H_ - -#include "fsl_common.h" -/*! - * @addtogroup utick - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief UTICK driver version 2.0.5. */ -#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) -/*@}*/ - -/*! @brief UTICK timer operational mode. */ -typedef enum _utick_mode -{ - kUTICK_Onetime = 0x0U, /*!< Trigger once*/ - kUTICK_Repeat = 0x1U, /*!< Trigger repeatedly */ -} utick_mode_t; - -/*! @brief UTICK callback function. */ -typedef void (*utick_callback_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes an UTICK by turning its bus clock on - * - */ -void UTICK_Init(UTICK_Type *base); - -/*! - * @brief Deinitializes a UTICK instance. - * - * This function shuts down Utick bus clock - * - * @param base UTICK peripheral base address. - */ -void UTICK_Deinit(UTICK_Type *base); -/*! - * @brief Get Status Flags. - * - * This returns the status flag - * - * @param base UTICK peripheral base address. - * @return status register value - */ -uint32_t UTICK_GetStatusFlags(UTICK_Type *base); -/*! - * @brief Clear Status Interrupt Flags. - * - * This clears intr status flag - * - * @param base UTICK peripheral base address. - * @return none - */ -void UTICK_ClearStatusFlags(UTICK_Type *base); - -/*! - * @brief Starts UTICK. - * - * This function starts a repeat/onetime countdown with an optional callback - * - * @param base UTICK peripheral base address. - * @param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * @param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * @param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) - * @return none - */ -void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb); -/*! - * @brief UTICK Interrupt Service Handler. - * - * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request - * in UTICK_SetTick()). - * if no user callback is scheduled, the interrupt will simply be cleared. - * - * @param base UTICK peripheral base address. - * @param cb callback scheduled for this instance of UTICK - * @return none - */ -void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_UTICK_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_wwdt.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_wwdt.c deleted file mode 100644 index 6680148acf7..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_wwdt.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_wwdt.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.wwdt" -#endif - -#define FREQUENCY_3MHZ (3000000U) -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Gets the instance from the base address - * - * @param base WWDT peripheral base address - * - * @return The WWDT instance - */ -static uint32_t WWDT_GetInstance(WWDT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to WWDT bases for each instance. */ -static WWDT_Type *const s_wwdtBases[] = WWDT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to WWDT clocks for each instance. */ -static const clock_ip_name_t s_wwdtClocks[] = WWDT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) -/*! @brief Pointers to WWDT resets for each instance. */ -static const reset_ip_name_t s_wwdtResets[] = WWDT_RSTS; -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t WWDT_GetInstance(WWDT_Type *base) -{ - uint32_t instance; - uint32_t wwdtArrayCount = (sizeof(s_wwdtBases) / sizeof(s_wwdtBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < wwdtArrayCount; instance++) - { - if (s_wwdtBases[instance] == base) - { - break; - } - } - - assert(instance < wwdtArrayCount); - - return instance; -} - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Initializes WWDT configure structure. - * - * This function initializes the WWDT configure structure to default value. The default - * value are: - * code - * config->enableWwdt = true; - * config->enableWatchdogReset = false; - * config->enableWatchdogProtect = false; - * config->enableLockOscillator = false; - * config->windowValue = 0xFFFFFFU; - * config->timeoutValue = 0xFFFFFFU; - * config->warningValue = 0; - * endcode - * - * param config Pointer to WWDT config structure. - * see wwdt_config_t - */ -void WWDT_GetDefaultConfig(wwdt_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* Enable the watch dog */ - config->enableWwdt = true; - /* Disable the watchdog timeout reset */ - config->enableWatchdogReset = false; - /* Disable the watchdog protection for updating the timeout value */ - config->enableWatchdogProtect = false; -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) - /* Do not lock the watchdog oscillator */ - config->enableLockOscillator = false; -#endif - /* Windowing is not in effect */ - config->windowValue = 0xFFFFFFU; - /* Set the timeout value to the max */ - config->timeoutValue = 0xFFFFFFU; - /* No warning is provided */ - config->warningValue = 0; - /* Set clock frequency. */ - config->clockFreq_Hz = 0U; -} - -/*! - * brief Initializes the WWDT. - * - * This function initializes the WWDT. When called, the WWDT runs according to the configuration. - * - * Example: - * code - * wwdt_config_t config; - * WWDT_GetDefaultConfig(&config); - * config.timeoutValue = 0x7ffU; - * WWDT_Init(wwdt_base,&config); - * endcode - * - * param base WWDT peripheral base address - * param config The configuration of WWDT - */ -void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config) -{ - assert(NULL != config); - - uint32_t value = 0U; - uint32_t DelayUs = 0U; - uint32_t primaskValue = 0U; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the WWDT clock */ - CLOCK_EnableClock(s_wwdtClocks[WWDT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) - /* Reset the module. */ - RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]); -#endif - -#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) - /* PMC RESETCAUSE: set bit to clear it by write 1. */ - PMC->RESETCAUSE = PMC_RESETCAUSE_WDTRESET_MASK; - /* Enable the watchdog reset event to affect the system in the Power Management Controller */ - PMC->CTRL |= PMC_CTRL_WDTRESETENABLE_MASK; -#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ - -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) - value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) | - WWDT_MOD_LOCK(config->enableLockOscillator); -#else - value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset); -#endif - /* Clear legacy flag in the MOD register by software writing a "1" to this bit field.. */ - if (0U != (base->MOD & WWDT_MOD_WDINT_MASK)) - { - value |= WWDT_MOD_WDINT_MASK; - } - /* Set configuration */ - primaskValue = DisableGlobalIRQ(); - base->TC = WWDT_TC_COUNT(config->timeoutValue); - base->MOD = value; - base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue); - base->WARNINT = WWDT_WARNINT_WARNINT(config->warningValue); - /* Refreshes the WWDT timer. */ - base->FEED = WWDT_FIRST_WORD_OF_REFRESH; - base->FEED = WWDT_SECOND_WORD_OF_REFRESH; - EnableGlobalIRQ(primaskValue); - /* Read counter value to wait wwdt timer start*/ - if (config->enableWwdt) - { - while (base->TV == 0xFFUL) - { - } - } - - /* This WDPROTECT bit can be set once by software and is only cleared by a reset */ - if (config->enableWatchdogProtect && (0U == (base->MOD & WWDT_MOD_WDPROTECT_MASK))) - { - /* The config->clockFreq_Hz must be set in order to config the delay time. */ - assert(0U != config->clockFreq_Hz); - - /* Set the WDPROTECT bit after the Feed Sequence (0xAA, 0x55) with 3 WDCLK delay */ - DelayUs = FREQUENCY_3MHZ / config->clockFreq_Hz + 1U; - SDK_DelayAtLeastUs(DelayUs, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - - base->MOD |= WWDT_MOD_WDPROTECT(1U); - } -} - -/*! - * brief Shuts down the WWDT. - * - * This function shuts down the WWDT. - * - * param base WWDT peripheral base address - */ -void WWDT_Deinit(WWDT_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the WWDT clock */ - CLOCK_DisableClock(s_wwdtClocks[WWDT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Refreshes the WWDT timer. - * - * This function feeds the WWDT. - * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. - * - * param base WWDT peripheral base address - */ -void WWDT_Refresh(WWDT_Type *base) -{ - uint32_t primaskValue = 0U; - - /* Disable the global interrupt to protect refresh sequence */ - primaskValue = DisableGlobalIRQ(); - base->FEED = WWDT_FIRST_WORD_OF_REFRESH; - base->FEED = WWDT_SECOND_WORD_OF_REFRESH; - EnableGlobalIRQ(primaskValue); -} - -/*! - * brief Clear WWDT flag. - * - * This function clears WWDT status flag. - * - * Example for clearing warning flag: - * code - * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); - * endcode - * param base WWDT peripheral base address - * param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask) -{ - /* Clear the WDINT bit so that we don't accidentally clear it */ - uint32_t reg = (base->MOD & (~WWDT_MOD_WDINT_MASK)); - - /* Clear timeout by writing a zero */ - if (0U != (mask & (uint32_t)kWWDT_TimeoutFlag)) - { - reg &= ~WWDT_MOD_WDTOF_MASK; -#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) - /* PMC RESETCAUSE: set bit to clear it */ - PMC->RESETCAUSE = PMC_RESETCAUSE_WDTRESET_MASK; -#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ - } - - /* Clear warning interrupt flag by writing a one */ - if (0U != (mask & (uint32_t)kWWDT_WarningFlag)) - { - reg |= WWDT_MOD_WDINT_MASK; - } - - base->MOD = reg; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_wwdt.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_wwdt.h deleted file mode 100644 index 25462534966..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_wwdt.h +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_WWDT_H_ -#define _FSL_WWDT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup wwdt - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Defines WWDT driver version. */ -#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 1, 9)) -/*@}*/ - -/*! @name Refresh sequence */ -/*@{*/ -#define WWDT_FIRST_WORD_OF_REFRESH (0xAAU) /*!< First word of refresh sequence */ -#define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */ -/*@}*/ - -/*! @brief Describes WWDT configuration structure. */ -typedef struct _wwdt_config -{ - bool enableWwdt; /*!< Enables or disables WWDT */ - bool enableWatchdogReset; /*!< true: Watchdog timeout will cause a chip reset - false: Watchdog timeout will not cause a chip reset */ - bool enableWatchdogProtect; /*!< true: Enable watchdog protect i.e timeout value can only be - changed after counter is below warning & window values - false: Disable watchdog protect; timeout value can be changed - at any time */ -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) - bool enableLockOscillator; /*!< true: Disabling or powering down the watchdog oscillator is prevented - Once set, this bit can only be cleared by a reset - false: Do not lock oscillator */ -#endif - uint32_t windowValue; /*!< Window value, set this to 0xFFFFFF if windowing is not in effect */ - uint32_t timeoutValue; /*!< Timeout value */ - uint32_t warningValue; /*!< Watchdog time counter value that will generate a - warning interrupt. Set this to 0 for no warning */ - uint32_t clockFreq_Hz; /*!< Watchdog clock source frequency. */ -} wwdt_config_t; - -/*! - * @brief WWDT status flags. - * - * This structure contains the WWDT status flags for use in the WWDT functions. - */ -enum _wwdt_status_flags_t -{ - kWWDT_TimeoutFlag = WWDT_MOD_WDTOF_MASK, /*!< Time-out flag, set when the timer times out */ - kWWDT_WarningFlag = WWDT_MOD_WDINT_MASK /*!< Warning interrupt flag, set when timer is below the value WDWARNINT */ -}; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name WWDT Initialization and De-initialization - * @{ - */ - -/*! - * @brief Initializes WWDT configure structure. - * - * This function initializes the WWDT configure structure to default value. The default - * value are: - * @code - * config->enableWwdt = true; - * config->enableWatchdogReset = false; - * config->enableWatchdogProtect = false; - * config->enableLockOscillator = false; - * config->windowValue = 0xFFFFFFU; - * config->timeoutValue = 0xFFFFFFU; - * config->warningValue = 0; - * @endcode - * - * @param config Pointer to WWDT config structure. - * @see wwdt_config_t - */ -void WWDT_GetDefaultConfig(wwdt_config_t *config); - -/*! - * @brief Initializes the WWDT. - * - * This function initializes the WWDT. When called, the WWDT runs according to the configuration. - * - * Example: - * @code - * wwdt_config_t config; - * WWDT_GetDefaultConfig(&config); - * config.timeoutValue = 0x7ffU; - * WWDT_Init(wwdt_base,&config); - * @endcode - * - * @param base WWDT peripheral base address - * @param config The configuration of WWDT - */ -void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config); - -/*! - * @brief Shuts down the WWDT. - * - * This function shuts down the WWDT. - * - * @param base WWDT peripheral base address - */ -void WWDT_Deinit(WWDT_Type *base); - -/* @} */ - -/*! - * @name WWDT Functional Operation - * @{ - */ - -/*! - * @brief Enables the WWDT module. - * - * This function write value into WWDT_MOD register to enable the WWDT, it is a write-once bit; - * once this bit is set to one and a watchdog feed is performed, the watchdog timer will run - * permanently. - * - * @param base WWDT peripheral base address - */ -static inline void WWDT_Enable(WWDT_Type *base) -{ - base->MOD |= WWDT_MOD_WDEN_MASK; -} - -/*! - * @brief Disables the WWDT module. - * @deprecated Do not use this function. It will be deleted in next release version, for - * once the bit field of WDEN written with a 1, it can not be re-written with a 0. - * - * This function write value into WWDT_MOD register to disable the WWDT. - * - * @param base WWDT peripheral base address - */ -static inline void WWDT_Disable(WWDT_Type *base) -{ - base->MOD &= ~WWDT_MOD_WDEN_MASK; -} - -/*! - * @brief Gets all WWDT status flags. - * - * This function gets all status flags. - * - * Example for getting Timeout Flag: - * @code - * uint32_t status; - * status = WWDT_GetStatusFlags(wwdt_base) & kWWDT_TimeoutFlag; - * @endcode - * @param base WWDT peripheral base address - * @return The status flags. This is the logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -static inline uint32_t WWDT_GetStatusFlags(WWDT_Type *base) -{ -#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) - uint32_t status; - /* WDTOF is not set in case of WD reset - get info from PMC instead */ - status = (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); - if (PMC->RESETCAUSE & PMC_RESETCAUSE_WDTRESET_MASK) - { - status |= kWWDT_TimeoutFlag; - } - return status; -#else - return (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); -#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ -} - -/*! - * @brief Clear WWDT flag. - * - * This function clears WWDT status flag. - * - * Example for clearing warning flag: - * @code - * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); - * @endcode - * @param base WWDT peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask); - -/*! - * @brief Set the WWDT warning value. - * - * The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog - * interrupt. When the watchdog timer counter is no longer greater than the value defined by - * WARNINT, an interrupt will be generated after the subsequent WDCLK. - * - * @param base WWDT peripheral base address - * @param warningValue WWDT warning value. - */ -static inline void WWDT_SetWarningValue(WWDT_Type *base, uint32_t warningValue) -{ - base->WARNINT = WWDT_WARNINT_WARNINT(warningValue); -} - -/*! - * @brief Set the WWDT timeout value. - * - * This function sets the timeout value. Every time a feed sequence occurs the value in the TC - * register is loaded into the Watchdog timer. Writing a value below 0xFF will cause 0xFF to be - * loaded into the TC register. Thus the minimum time-out interval is TWDCLK*256*4. - * If enableWatchdogProtect flag is true in wwdt_config_t config structure, any attempt to change - * the timeout value before the watchdog counter is below the warning and window values - * will cause a watchdog reset and set the WDTOF flag. - * - * @param base WWDT peripheral base address - * @param timeoutCount WWDT timeout value, count of WWDT clock tick. - */ -static inline void WWDT_SetTimeoutValue(WWDT_Type *base, uint32_t timeoutCount) -{ - base->TC = WWDT_TC_COUNT(timeoutCount); -} - -/*! - * @brief Sets the WWDT window value. - * - * The WINDOW register determines the highest TV value allowed when a watchdog feed is performed. - * If a feed sequence occurs when timer value is greater than the value in WINDOW, a watchdog - * event will occur. To disable windowing, set windowValue to 0xFFFFFF (maximum possible timer - * value) so windowing is not in effect. - * - * @param base WWDT peripheral base address - * @param windowValue WWDT window value. - */ -static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue) -{ - base->WINDOW = WWDT_WINDOW_WINDOW(windowValue); -} - -/*! - * @brief Refreshes the WWDT timer. - * - * This function feeds the WWDT. - * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. - * - * @param base WWDT peripheral base address - */ -void WWDT_Refresh(WWDT_Type *base); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_WWDT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/fsl_device_registers.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/fsl_device_registers.h deleted file mode 100644 index 1daee083862..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/fsl_device_registers.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __FSL_DEVICE_REGISTERS_H__ -#define __FSL_DEVICE_REGISTERS_H__ - -/* - * Include the cpu specific register header files. - * - * The CPU macro should be declared in the project or makefile. - */ -#if (defined(CPU_LPC55S28JBD100) || defined(CPU_LPC55S28JBD64) || defined(CPU_LPC55S28JEV98)) - -#define LPC55S28_SERIES - -/* CMSIS-style register definitions */ -#include "LPC55S28.h" -/* CPU specific feature definitions */ -#include "LPC55S28_features.h" - -#else -#error "No valid CPU defined!" -#endif - -#endif /* __FSL_DEVICE_REGISTERS_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/gcc/LPC55S28_flash.ld b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/gcc/LPC55S28_flash.ld deleted file mode 100644 index 8c1a25098de..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/gcc/LPC55S28_flash.ld +++ /dev/null @@ -1,213 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S28JBD100_cm33_core0 -** LPC55S28JBD64_cm33_core0 -** LPC55S28JEV98_cm33_core0 -** -** Compiler: GNU C Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b200722 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2020 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000200 - m_text (RX) : ORIGIN = 0x00000200, LENGTH = 0x0007FE00 - m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00030000 - m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000 -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into internal flash */ - .interrupts : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.ramfunc*) /* for functions in ram */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - m_usb_bdt (NOLOAD) : - { - . = ALIGN(512); - *(m_usb_bdt) - } > m_usb_sram - - m_usb_global (NOLOAD) : - { - *(m_usb_global) - } > m_usb_sram - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/gcc/LPC55S28_ram.ld b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/gcc/LPC55S28_ram.ld deleted file mode 100644 index 94ef00b5f65..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/gcc/LPC55S28_ram.ld +++ /dev/null @@ -1,213 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S28JBD100_cm33_core0 -** LPC55S28JBD64_cm33_core0 -** LPC55S28JEV98_cm33_core0 -** -** Compiler: GNU C Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b200722 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2020 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x04000000, LENGTH = 0x00000200 - m_text (RX) : ORIGIN = 0x04000200, LENGTH = 0x00007E00 - m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00030000 - m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000 -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into internal flash */ - .interrupts : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.ramfunc*) /* for functions in ram */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - m_usb_bdt (NOLOAD) : - { - . = ALIGN(512); - *(m_usb_bdt) - } > m_usb_sram - - m_usb_global (NOLOAD) : - { - *(m_usb_global) - } > m_usb_sram - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/gcc/startup_LPC55S28.S b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/gcc/startup_LPC55S28.S deleted file mode 100644 index 622c9348d07..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/gcc/startup_LPC55S28.S +++ /dev/null @@ -1,884 +0,0 @@ -/* --------------------------------------------------------------------------*/ -/* @file: startup_LPC55S28.s */ -/* @purpose: CMSIS Cortex-M33 Core Device Startup File */ -/* LPC55S28 */ -/* @version: 1.1 */ -/* @date: 2019-5-16 */ -/* --------------------------------------------------------------------------*/ -/* */ -/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2021 NXP */ -/* All rights reserved. */ -/* */ -/* SPDX-License-Identifier: BSD-3-Clause */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - - - .syntax unified - .arch armv8-m.main - - .section .isr_vector, "a" - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long MemManage_Handler /* MPU Fault Handler*/ - .long BusFault_Handler /* Bus Fault Handler*/ - .long UsageFault_Handler /* Usage Fault Handler*/ - .long SecureFault_Handler /* Secure Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long DebugMon_Handler /* Debug Monitor Handler*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts */ - .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ - .long DMA0_IRQHandler /* DMA0 controller */ - .long GINT0_IRQHandler /* GPIO group 0 */ - .long GINT1_IRQHandler /* GPIO group 1 */ - .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - .long UTICK0_IRQHandler /* Micro-tick Timer */ - .long MRT0_IRQHandler /* Multi-rate timer */ - .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ - .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ - .long SCT0_IRQHandler /* SCTimer/PWM */ - .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ - .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long ADC0_IRQHandler /* ADC0 */ - .long Reserved39_IRQHandler /* Reserved interrupt */ - .long ACMP_IRQHandler /* ACMP interrupts */ - .long Reserved41_IRQHandler /* Reserved interrupt */ - .long Reserved42_IRQHandler /* Reserved interrupt */ - .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ - .long USB0_IRQHandler /* USB device */ - .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ - .long Reserved46_IRQHandler /* Reserved interrupt */ - .long Reserved47_IRQHandler /* Reserved interrupt */ - .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ - .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ - .long OS_EVENT_IRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ - .long Reserved55_IRQHandler /* Reserved interrupt */ - .long Reserved56_IRQHandler /* Reserved interrupt */ - .long Reserved57_IRQHandler /* Reserved interrupt */ - .long SDIO_IRQHandler /* SD/MMC */ - .long Reserved59_IRQHandler /* Reserved interrupt */ - .long Reserved60_IRQHandler /* Reserved interrupt */ - .long Reserved61_IRQHandler /* Reserved interrupt */ - .long USB1_PHY_IRQHandler /* USB1_PHY */ - .long USB1_IRQHandler /* USB1 interrupt */ - .long USB1_NEEDCLK_IRQHandler /* USB1 activity */ - .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ - .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ - .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ - .long PLU_IRQHandler /* PLU interrupt */ - .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ - .long HASHCRYPT_IRQHandler /* HASHCRYPT interrupt */ - .long CASER_IRQHandler /* CASPER interrupt */ - .long PUF_IRQHandler /* PUF interrupt */ - .long PQ_IRQHandler /* PQ interrupt */ - .long DMA1_IRQHandler /* DMA1 interrupt */ - .long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ - - .size __Vectors, . - __Vectors - - .text - .thumb - -/* Reset Handler */ - .thumb_func - .align 2 - .globl Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - cpsid i /* Mask interrupts */ - .equ VTOR, 0xE000ED08 - ldr r0, =VTOR - ldr r1, =__Vectors - str r1, [r0] - ldr r2, [r1] - msr msp, r2 - ldr R0, =__StackLimit - msr msplim, R0 -#ifndef __NO_SYSTEM_INIT - ldr r0,=SystemInit - blx r0 -#endif -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -#if 1 -/* Here are two copies of loop implemenations. First one favors code size - * and the second one favors performance. Default uses the first one. - * Change to "#if 0" to use the second one */ -.LC0: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .LC0 -#else - subs r3, r2 - ble .LC1 -.LC0: - subs r3, #4 - ldr r0, [r1, r3] - str r0, [r2, r3] - bgt .LC0 -.LC1: -#endif - -#ifdef __STARTUP_CLEAR_BSS -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * Loop to zero out BSS section, which uses following symbols - * in linker script: - * __bss_start__: start of BSS section. Must align to 4 - * __bss_end__: end of BSS section. Must align to 4 - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.LC2: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC2 -#endif /* __STARTUP_CLEAR_BSS */ - -/* Add stack / heap initializaiton */ - movs r0, 0 - ldr r1, =__HeapBase - ldr r2, =__HeapLimit -.LC3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC3 - - ldr r1, =__StackLimit - ldr r2, =__StackTop -.LC4: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC4 -/*End of stack / heap initializaiton */ - cpsie i /* Unmask interrupts */ - -#ifndef __START -#define __START _start -#endif -#ifndef __ATOLLIC__ - ldr r0,=__START - blx r0 -#else - ldr r0,=__libc_init_array - blx r0 - ldr r0,=main - bx r0 -#endif - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - - .align 1 - .thumb_func - .weak WDT_BOD_IRQHandler - .type WDT_BOD_IRQHandler, %function -WDT_BOD_IRQHandler: - ldr r0,=WDT_BOD_DriverIRQHandler - bx r0 - .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler - - .align 1 - .thumb_func - .weak DMA0_IRQHandler - .type DMA0_IRQHandler, %function -DMA0_IRQHandler: - ldr r0,=DMA0_DriverIRQHandler - bx r0 - .size DMA0_IRQHandler, . - DMA0_IRQHandler - - .align 1 - .thumb_func - .weak GINT0_IRQHandler - .type GINT0_IRQHandler, %function -GINT0_IRQHandler: - ldr r0,=GINT0_DriverIRQHandler - bx r0 - .size GINT0_IRQHandler, . - GINT0_IRQHandler - - .align 1 - .thumb_func - .weak GINT1_IRQHandler - .type GINT1_IRQHandler, %function -GINT1_IRQHandler: - ldr r0,=GINT1_DriverIRQHandler - bx r0 - .size GINT1_IRQHandler, . - GINT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT0_IRQHandler - .type PIN_INT0_IRQHandler, %function -PIN_INT0_IRQHandler: - ldr r0,=PIN_INT0_DriverIRQHandler - bx r0 - .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT1_IRQHandler - .type PIN_INT1_IRQHandler, %function -PIN_INT1_IRQHandler: - ldr r0,=PIN_INT1_DriverIRQHandler - bx r0 - .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT2_IRQHandler - .type PIN_INT2_IRQHandler, %function -PIN_INT2_IRQHandler: - ldr r0,=PIN_INT2_DriverIRQHandler - bx r0 - .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT3_IRQHandler - .type PIN_INT3_IRQHandler, %function -PIN_INT3_IRQHandler: - ldr r0,=PIN_INT3_DriverIRQHandler - bx r0 - .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler - - .align 1 - .thumb_func - .weak UTICK0_IRQHandler - .type UTICK0_IRQHandler, %function -UTICK0_IRQHandler: - ldr r0,=UTICK0_DriverIRQHandler - bx r0 - .size UTICK0_IRQHandler, . - UTICK0_IRQHandler - - .align 1 - .thumb_func - .weak MRT0_IRQHandler - .type MRT0_IRQHandler, %function -MRT0_IRQHandler: - ldr r0,=MRT0_DriverIRQHandler - bx r0 - .size MRT0_IRQHandler, . - MRT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER0_IRQHandler - .type CTIMER0_IRQHandler, %function -CTIMER0_IRQHandler: - ldr r0,=CTIMER0_DriverIRQHandler - bx r0 - .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER1_IRQHandler - .type CTIMER1_IRQHandler, %function -CTIMER1_IRQHandler: - ldr r0,=CTIMER1_DriverIRQHandler - bx r0 - .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler - - .align 1 - .thumb_func - .weak SCT0_IRQHandler - .type SCT0_IRQHandler, %function -SCT0_IRQHandler: - ldr r0,=SCT0_DriverIRQHandler - bx r0 - .size SCT0_IRQHandler, . - SCT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER3_IRQHandler - .type CTIMER3_IRQHandler, %function -CTIMER3_IRQHandler: - ldr r0,=CTIMER3_DriverIRQHandler - bx r0 - .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM0_IRQHandler - .type FLEXCOMM0_IRQHandler, %function -FLEXCOMM0_IRQHandler: - ldr r0,=FLEXCOMM0_DriverIRQHandler - bx r0 - .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM1_IRQHandler - .type FLEXCOMM1_IRQHandler, %function -FLEXCOMM1_IRQHandler: - ldr r0,=FLEXCOMM1_DriverIRQHandler - bx r0 - .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM2_IRQHandler - .type FLEXCOMM2_IRQHandler, %function -FLEXCOMM2_IRQHandler: - ldr r0,=FLEXCOMM2_DriverIRQHandler - bx r0 - .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM3_IRQHandler - .type FLEXCOMM3_IRQHandler, %function -FLEXCOMM3_IRQHandler: - ldr r0,=FLEXCOMM3_DriverIRQHandler - bx r0 - .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM4_IRQHandler - .type FLEXCOMM4_IRQHandler, %function -FLEXCOMM4_IRQHandler: - ldr r0,=FLEXCOMM4_DriverIRQHandler - bx r0 - .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM5_IRQHandler - .type FLEXCOMM5_IRQHandler, %function -FLEXCOMM5_IRQHandler: - ldr r0,=FLEXCOMM5_DriverIRQHandler - bx r0 - .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM6_IRQHandler - .type FLEXCOMM6_IRQHandler, %function -FLEXCOMM6_IRQHandler: - ldr r0,=FLEXCOMM6_DriverIRQHandler - bx r0 - .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM7_IRQHandler - .type FLEXCOMM7_IRQHandler, %function -FLEXCOMM7_IRQHandler: - ldr r0,=FLEXCOMM7_DriverIRQHandler - bx r0 - .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_IRQHandler - .type ADC0_IRQHandler, %function -ADC0_IRQHandler: - ldr r0,=ADC0_DriverIRQHandler - bx r0 - .size ADC0_IRQHandler, . - ADC0_IRQHandler - - .align 1 - .thumb_func - .weak Reserved39_IRQHandler - .type Reserved39_IRQHandler, %function -Reserved39_IRQHandler: - ldr r0,=Reserved39_DriverIRQHandler - bx r0 - .size Reserved39_IRQHandler, . - Reserved39_IRQHandler - - .align 1 - .thumb_func - .weak ACMP_IRQHandler - .type ACMP_IRQHandler, %function -ACMP_IRQHandler: - ldr r0,=ACMP_DriverIRQHandler - bx r0 - .size ACMP_IRQHandler, . - ACMP_IRQHandler - - .align 1 - .thumb_func - .weak Reserved41_IRQHandler - .type Reserved41_IRQHandler, %function -Reserved41_IRQHandler: - ldr r0,=Reserved41_DriverIRQHandler - bx r0 - .size Reserved41_IRQHandler, . - Reserved41_IRQHandler - - .align 1 - .thumb_func - .weak Reserved42_IRQHandler - .type Reserved42_IRQHandler, %function -Reserved42_IRQHandler: - ldr r0,=Reserved42_DriverIRQHandler - bx r0 - .size Reserved42_IRQHandler, . - Reserved42_IRQHandler - - .align 1 - .thumb_func - .weak USB0_NEEDCLK_IRQHandler - .type USB0_NEEDCLK_IRQHandler, %function -USB0_NEEDCLK_IRQHandler: - ldr r0,=USB0_NEEDCLK_DriverIRQHandler - bx r0 - .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak USB0_IRQHandler - .type USB0_IRQHandler, %function -USB0_IRQHandler: - ldr r0,=USB0_DriverIRQHandler - bx r0 - .size USB0_IRQHandler, . - USB0_IRQHandler - - .align 1 - .thumb_func - .weak RTC_IRQHandler - .type RTC_IRQHandler, %function -RTC_IRQHandler: - ldr r0,=RTC_DriverIRQHandler - bx r0 - .size RTC_IRQHandler, . - RTC_IRQHandler - - .align 1 - .thumb_func - .weak Reserved46_IRQHandler - .type Reserved46_IRQHandler, %function -Reserved46_IRQHandler: - ldr r0,=Reserved46_DriverIRQHandler - bx r0 - .size Reserved46_IRQHandler, . - Reserved46_IRQHandler - - .align 1 - .thumb_func - .weak Reserved47_IRQHandler - .type Reserved47_IRQHandler, %function -Reserved47_IRQHandler: - ldr r0,=Reserved47_DriverIRQHandler - bx r0 - .size Reserved47_IRQHandler, . - Reserved47_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT4_IRQHandler - .type PIN_INT4_IRQHandler, %function -PIN_INT4_IRQHandler: - ldr r0,=PIN_INT4_DriverIRQHandler - bx r0 - .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT5_IRQHandler - .type PIN_INT5_IRQHandler, %function -PIN_INT5_IRQHandler: - ldr r0,=PIN_INT5_DriverIRQHandler - bx r0 - .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT6_IRQHandler - .type PIN_INT6_IRQHandler, %function -PIN_INT6_IRQHandler: - ldr r0,=PIN_INT6_DriverIRQHandler - bx r0 - .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT7_IRQHandler - .type PIN_INT7_IRQHandler, %function -PIN_INT7_IRQHandler: - ldr r0,=PIN_INT7_DriverIRQHandler - bx r0 - .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER2_IRQHandler - .type CTIMER2_IRQHandler, %function -CTIMER2_IRQHandler: - ldr r0,=CTIMER2_DriverIRQHandler - bx r0 - .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER4_IRQHandler - .type CTIMER4_IRQHandler, %function -CTIMER4_IRQHandler: - ldr r0,=CTIMER4_DriverIRQHandler - bx r0 - .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler - - .align 1 - .thumb_func - .weak OS_EVENT_IRQHandler - .type OS_EVENT_IRQHandler, %function -OS_EVENT_IRQHandler: - ldr r0,=OS_EVENT_DriverIRQHandler - bx r0 - .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler - - .align 1 - .thumb_func - .weak Reserved55_IRQHandler - .type Reserved55_IRQHandler, %function -Reserved55_IRQHandler: - ldr r0,=Reserved55_DriverIRQHandler - bx r0 - .size Reserved55_IRQHandler, . - Reserved55_IRQHandler - - .align 1 - .thumb_func - .weak Reserved56_IRQHandler - .type Reserved56_IRQHandler, %function -Reserved56_IRQHandler: - ldr r0,=Reserved56_DriverIRQHandler - bx r0 - .size Reserved56_IRQHandler, . - Reserved56_IRQHandler - - .align 1 - .thumb_func - .weak Reserved57_IRQHandler - .type Reserved57_IRQHandler, %function -Reserved57_IRQHandler: - ldr r0,=Reserved57_DriverIRQHandler - bx r0 - .size Reserved57_IRQHandler, . - Reserved57_IRQHandler - - .align 1 - .thumb_func - .weak SDIO_IRQHandler - .type SDIO_IRQHandler, %function -SDIO_IRQHandler: - ldr r0,=SDIO_DriverIRQHandler - bx r0 - .size SDIO_IRQHandler, . - SDIO_IRQHandler - - .align 1 - .thumb_func - .weak Reserved59_IRQHandler - .type Reserved59_IRQHandler, %function -Reserved59_IRQHandler: - ldr r0,=Reserved59_DriverIRQHandler - bx r0 - .size Reserved59_IRQHandler, . - Reserved59_IRQHandler - - .align 1 - .thumb_func - .weak Reserved60_IRQHandler - .type Reserved60_IRQHandler, %function -Reserved60_IRQHandler: - ldr r0,=Reserved60_DriverIRQHandler - bx r0 - .size Reserved60_IRQHandler, . - Reserved60_IRQHandler - - .align 1 - .thumb_func - .weak Reserved61_IRQHandler - .type Reserved61_IRQHandler, %function -Reserved61_IRQHandler: - ldr r0,=Reserved61_DriverIRQHandler - bx r0 - .size Reserved61_IRQHandler, . - Reserved61_IRQHandler - - .align 1 - .thumb_func - .weak USB1_PHY_IRQHandler - .type USB1_PHY_IRQHandler, %function -USB1_PHY_IRQHandler: - ldr r0,=USB1_PHY_DriverIRQHandler - bx r0 - .size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler - - .align 1 - .thumb_func - .weak USB1_IRQHandler - .type USB1_IRQHandler, %function -USB1_IRQHandler: - ldr r0,=USB1_DriverIRQHandler - bx r0 - .size USB1_IRQHandler, . - USB1_IRQHandler - - .align 1 - .thumb_func - .weak USB1_NEEDCLK_IRQHandler - .type USB1_NEEDCLK_IRQHandler, %function -USB1_NEEDCLK_IRQHandler: - ldr r0,=USB1_NEEDCLK_DriverIRQHandler - bx r0 - .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak SEC_HYPERVISOR_CALL_IRQHandler - .type SEC_HYPERVISOR_CALL_IRQHandler, %function -SEC_HYPERVISOR_CALL_IRQHandler: - ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler - bx r0 - .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ0_IRQHandler - .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function -SEC_GPIO_INT0_IRQ0_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ1_IRQHandler - .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function -SEC_GPIO_INT0_IRQ1_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak PLU_IRQHandler - .type PLU_IRQHandler, %function -PLU_IRQHandler: - ldr r0,=PLU_DriverIRQHandler - bx r0 - .size PLU_IRQHandler, . - PLU_IRQHandler - - .align 1 - .thumb_func - .weak SEC_VIO_IRQHandler - .type SEC_VIO_IRQHandler, %function -SEC_VIO_IRQHandler: - ldr r0,=SEC_VIO_DriverIRQHandler - bx r0 - .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler - - .align 1 - .thumb_func - .weak HASHCRYPT_IRQHandler - .type HASHCRYPT_IRQHandler, %function -HASHCRYPT_IRQHandler: - ldr r0,=HASHCRYPT_DriverIRQHandler - bx r0 - .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler - - .align 1 - .thumb_func - .weak CASER_IRQHandler - .type CASER_IRQHandler, %function -CASER_IRQHandler: - ldr r0,=CASER_DriverIRQHandler - bx r0 - .size CASER_IRQHandler, . - CASER_IRQHandler - - .align 1 - .thumb_func - .weak PUF_IRQHandler - .type PUF_IRQHandler, %function -PUF_IRQHandler: - ldr r0,=PUF_DriverIRQHandler - bx r0 - .size PUF_IRQHandler, . - PUF_IRQHandler - - .align 1 - .thumb_func - .weak PQ_IRQHandler - .type PQ_IRQHandler, %function -PQ_IRQHandler: - ldr r0,=PQ_DriverIRQHandler - bx r0 - .size PQ_IRQHandler, . - PQ_IRQHandler - - .align 1 - .thumb_func - .weak DMA1_IRQHandler - .type DMA1_IRQHandler, %function -DMA1_IRQHandler: - ldr r0,=DMA1_DriverIRQHandler - bx r0 - .size DMA1_IRQHandler, . - DMA1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM8_IRQHandler - .type FLEXCOMM8_IRQHandler, %function -FLEXCOMM8_IRQHandler: - ldr r0,=FLEXCOMM8_DriverIRQHandler - bx r0 - .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm -/* Exception Handlers */ - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SecureFault_Handler - def_irq_handler DebugMon_Handler - def_irq_handler WDT_BOD_DriverIRQHandler - def_irq_handler DMA0_DriverIRQHandler - def_irq_handler GINT0_DriverIRQHandler - def_irq_handler GINT1_DriverIRQHandler - def_irq_handler PIN_INT0_DriverIRQHandler - def_irq_handler PIN_INT1_DriverIRQHandler - def_irq_handler PIN_INT2_DriverIRQHandler - def_irq_handler PIN_INT3_DriverIRQHandler - def_irq_handler UTICK0_DriverIRQHandler - def_irq_handler MRT0_DriverIRQHandler - def_irq_handler CTIMER0_DriverIRQHandler - def_irq_handler CTIMER1_DriverIRQHandler - def_irq_handler SCT0_DriverIRQHandler - def_irq_handler CTIMER3_DriverIRQHandler - def_irq_handler FLEXCOMM0_DriverIRQHandler - def_irq_handler FLEXCOMM1_DriverIRQHandler - def_irq_handler FLEXCOMM2_DriverIRQHandler - def_irq_handler FLEXCOMM3_DriverIRQHandler - def_irq_handler FLEXCOMM4_DriverIRQHandler - def_irq_handler FLEXCOMM5_DriverIRQHandler - def_irq_handler FLEXCOMM6_DriverIRQHandler - def_irq_handler FLEXCOMM7_DriverIRQHandler - def_irq_handler ADC0_DriverIRQHandler - def_irq_handler Reserved39_DriverIRQHandler - def_irq_handler ACMP_DriverIRQHandler - def_irq_handler Reserved41_DriverIRQHandler - def_irq_handler Reserved42_DriverIRQHandler - def_irq_handler USB0_NEEDCLK_DriverIRQHandler - def_irq_handler USB0_DriverIRQHandler - def_irq_handler RTC_DriverIRQHandler - def_irq_handler Reserved46_DriverIRQHandler - def_irq_handler Reserved47_DriverIRQHandler - def_irq_handler PIN_INT4_DriverIRQHandler - def_irq_handler PIN_INT5_DriverIRQHandler - def_irq_handler PIN_INT6_DriverIRQHandler - def_irq_handler PIN_INT7_DriverIRQHandler - def_irq_handler CTIMER2_DriverIRQHandler - def_irq_handler CTIMER4_DriverIRQHandler - def_irq_handler OS_EVENT_DriverIRQHandler - def_irq_handler Reserved55_DriverIRQHandler - def_irq_handler Reserved56_DriverIRQHandler - def_irq_handler Reserved57_DriverIRQHandler - def_irq_handler SDIO_DriverIRQHandler - def_irq_handler Reserved59_DriverIRQHandler - def_irq_handler Reserved60_DriverIRQHandler - def_irq_handler Reserved61_DriverIRQHandler - def_irq_handler USB1_PHY_DriverIRQHandler - def_irq_handler USB1_DriverIRQHandler - def_irq_handler USB1_NEEDCLK_DriverIRQHandler - def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler - def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler - def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler - def_irq_handler PLU_DriverIRQHandler - def_irq_handler SEC_VIO_DriverIRQHandler - def_irq_handler HASHCRYPT_DriverIRQHandler - def_irq_handler CASER_DriverIRQHandler - def_irq_handler PUF_DriverIRQHandler - def_irq_handler PQ_DriverIRQHandler - def_irq_handler DMA1_DriverIRQHandler - def_irq_handler FLEXCOMM8_DriverIRQHandler - - .end diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/iar/LPC55S28_flash.icf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/iar/LPC55S28_flash.icf deleted file mode 100644 index e8ed6140aaa..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/iar/LPC55S28_flash.icf +++ /dev/null @@ -1,99 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S28JBD100_cm33_core0 -** LPC55S28JBD64_cm33_core0 -** LPC55S28JEV98_cm33_core0 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b200722 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2020 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -define symbol usb_bdt_size = 0x0; -/* Stack and Heap Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define symbol m_interrupts_start = 0x00000000; -define symbol m_interrupts_end = 0x000001FF; - -define symbol m_text_start = 0x00000200; -define symbol m_text_end = 0x0007FFFF; - - define symbol m_data_start = 0x20000000; - define symbol m_data_end = 0x2002FFFF; - - -define symbol m_usb_sram_start = 0x40100000; -define symbol m_usb_sram_end = 0x40103FFF; - -define memory mem with size = 4G; - -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -if (isdefinedsymbol(__use_shmem__)) { - define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; -} - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - - -/* regions for USB */ -define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; -define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; -place in USB_BDT_region { section m_usb_bdt }; -place in USB_SRAM_region { section m_usb_global }; - -initialize by copy { readwrite, section .textrw }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - /* Required in a multi-threaded application */ - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; -if (isdefinedsymbol(__use_shmem__)) { - do not initialize { section rpmsg_sh_mem_section }; -} - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; - - - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/iar/LPC55S28_ram.icf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/iar/LPC55S28_ram.icf deleted file mode 100644 index 5c17caa28a1..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/iar/LPC55S28_ram.icf +++ /dev/null @@ -1,99 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S28JBD100_cm33_core0 -** LPC55S28JBD64_cm33_core0 -** LPC55S28JEV98_cm33_core0 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b200722 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2020 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -define symbol usb_bdt_size = 0x0; -/* Stack and Heap Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define symbol m_interrupts_start = 0x04000000; -define symbol m_interrupts_end = 0x040001FF; - -define symbol m_text_start = 0x04000200; -define symbol m_text_end = 0x04007FFF; - - define symbol m_data_start = 0x20000000; - define symbol m_data_end = 0x2002FFFF; - - -define symbol m_usb_sram_start = 0x40100000; -define symbol m_usb_sram_end = 0x40103FFF; - -define memory mem with size = 4G; - -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -if (isdefinedsymbol(__use_shmem__)) { - define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; -} - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - - -/* regions for USB */ -define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; -define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; -place in USB_BDT_region { section m_usb_bdt }; -place in USB_SRAM_region { section m_usb_global }; - -initialize by copy { readwrite, section .textrw }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - /* Required in a multi-threaded application */ - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; -if (isdefinedsymbol(__use_shmem__)) { - do not initialize { section rpmsg_sh_mem_section }; -} - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; - - - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/iar/startup_LPC55S28.s b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/iar/startup_LPC55S28.s deleted file mode 100644 index 478782b168b..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/iar/startup_LPC55S28.s +++ /dev/null @@ -1,635 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC55S28.s -; * @purpose: CMSIS Cortex-M33 Core Device Startup File -; * LPC55S28 -; * @version: 1.1 -; * @date: 2019-5-16 -; *---------------------------------------------------------------------------- -; * -; Copyright 1997-2016 Freescale Semiconductor, Inc. -; Copyright 2016-2021 NXP -; All rights reserved. -; -; SPDX-License-Identifier: BSD-3-Clause -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__iar_init$$done: ; The vector table is not needed - ; until after copy initialization is done - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD SecureFault_Handler - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt - DCD DMA0_IRQHandler ; DMA0 controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD ADC0_IRQHandler ; ADC0 - DCD Reserved39_IRQHandler ; Reserved interrupt - DCD ACMP_IRQHandler ; ACMP interrupts - DCD Reserved41_IRQHandler ; Reserved interrupt - DCD Reserved42_IRQHandler ; Reserved interrupt - DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt - DCD USB0_IRQHandler ; USB device - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD Reserved46_IRQHandler ; Reserved interrupt - DCD Reserved47_IRQHandler ; Reserved interrupt - DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int - DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int - DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int - DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int - DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 - DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 - DCD OS_EVENT_IRQHandler ; OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts - DCD Reserved55_IRQHandler ; Reserved interrupt - DCD Reserved56_IRQHandler ; Reserved interrupt - DCD Reserved57_IRQHandler ; Reserved interrupt - DCD SDIO_IRQHandler ; SD/MMC - DCD Reserved59_IRQHandler ; Reserved interrupt - DCD Reserved60_IRQHandler ; Reserved interrupt - DCD Reserved61_IRQHandler ; Reserved interrupt - DCD USB1_PHY_IRQHandler ; USB1_PHY - DCD USB1_IRQHandler ; USB1 interrupt - DCD USB1_NEEDCLK_IRQHandler ; USB1 activity - DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt - DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT0_IRQ0 interrupt - DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT0_IRQ1 interrupt - DCD PLU_IRQHandler ; PLU interrupt - DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt - DCD HASHCRYPT_IRQHandler ; HASHCRYPT interrupt - DCD CASER_IRQHandler ; CASPER interrupt - DCD PUF_IRQHandler ; PUF interrupt - DCD PQ_IRQHandler ; PQ interrupt - DCD DMA1_IRQHandler ; DMA1 interrupt - DCD FLEXCOMM8_IRQHandler ; Flexcomm Interface 8 (SPI, , FLEXCOMM) -__Vectors_End - - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__vector_table - STR R1, [R0] - LDR R2, [R1] - MSR MSP, R2 - LDR R0, =sfb(CSTACK) - MSR MSPLIM, R0 - CPSIE I ; Unmask interrupts - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SecureFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SecureFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK WDT_BOD_IRQHandler - PUBWEAK WDT_BOD_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -WDT_BOD_IRQHandler - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler - LDR R0, =DMA0_DriverIRQHandler - BX R0 - PUBWEAK GINT0_IRQHandler - PUBWEAK GINT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT0_IRQHandler - LDR R0, =GINT0_DriverIRQHandler - BX R0 - PUBWEAK GINT1_IRQHandler - PUBWEAK GINT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT1_IRQHandler - LDR R0, =GINT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT0_IRQHandler - PUBWEAK PIN_INT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT0_IRQHandler - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT1_IRQHandler - PUBWEAK PIN_INT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT1_IRQHandler - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT2_IRQHandler - PUBWEAK PIN_INT2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT2_IRQHandler - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT3_IRQHandler - PUBWEAK PIN_INT3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT3_IRQHandler - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - PUBWEAK UTICK0_IRQHandler - PUBWEAK UTICK0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UTICK0_IRQHandler - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - PUBWEAK MRT0_IRQHandler - PUBWEAK MRT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -MRT0_IRQHandler - LDR R0, =MRT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER0_IRQHandler - PUBWEAK CTIMER0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER0_IRQHandler - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER1_IRQHandler - PUBWEAK CTIMER1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER1_IRQHandler - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - PUBWEAK SCT0_IRQHandler - PUBWEAK SCT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SCT0_IRQHandler - LDR R0, =SCT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER3_IRQHandler - PUBWEAK CTIMER3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER3_IRQHandler - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM0_IRQHandler - PUBWEAK FLEXCOMM0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM0_IRQHandler - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM1_IRQHandler - PUBWEAK FLEXCOMM1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM1_IRQHandler - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM2_IRQHandler - PUBWEAK FLEXCOMM2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM2_IRQHandler - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM3_IRQHandler - PUBWEAK FLEXCOMM3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM3_IRQHandler - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM4_IRQHandler - PUBWEAK FLEXCOMM4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM4_IRQHandler - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM5_IRQHandler - PUBWEAK FLEXCOMM5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM5_IRQHandler - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM6_IRQHandler - PUBWEAK FLEXCOMM6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM6_IRQHandler - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM7_IRQHandler - PUBWEAK FLEXCOMM7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM7_IRQHandler - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - PUBWEAK ADC0_IRQHandler - PUBWEAK ADC0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_IRQHandler - LDR R0, =ADC0_DriverIRQHandler - BX R0 - PUBWEAK Reserved39_IRQHandler - PUBWEAK Reserved39_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved39_IRQHandler - LDR R0, =Reserved39_DriverIRQHandler - BX R0 - PUBWEAK ACMP_IRQHandler - PUBWEAK ACMP_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ACMP_IRQHandler - LDR R0, =ACMP_DriverIRQHandler - BX R0 - PUBWEAK Reserved41_IRQHandler - PUBWEAK Reserved41_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved41_IRQHandler - LDR R0, =Reserved41_DriverIRQHandler - BX R0 - PUBWEAK Reserved42_IRQHandler - PUBWEAK Reserved42_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved42_IRQHandler - LDR R0, =Reserved42_DriverIRQHandler - BX R0 - PUBWEAK USB0_NEEDCLK_IRQHandler - PUBWEAK USB0_NEEDCLK_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_NEEDCLK_IRQHandler - LDR R0, =USB0_NEEDCLK_DriverIRQHandler - BX R0 - PUBWEAK USB0_IRQHandler - PUBWEAK USB0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_IRQHandler - LDR R0, =USB0_DriverIRQHandler - BX R0 - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -RTC_IRQHandler - LDR R0, =RTC_DriverIRQHandler - BX R0 - PUBWEAK Reserved46_IRQHandler - PUBWEAK Reserved46_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved46_IRQHandler - LDR R0, =Reserved46_DriverIRQHandler - BX R0 - PUBWEAK Reserved47_IRQHandler - PUBWEAK Reserved47_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved47_IRQHandler - LDR R0, =Reserved47_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT4_IRQHandler - PUBWEAK PIN_INT4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT4_IRQHandler - LDR R0, =PIN_INT4_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT5_IRQHandler - PUBWEAK PIN_INT5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT5_IRQHandler - LDR R0, =PIN_INT5_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT6_IRQHandler - PUBWEAK PIN_INT6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT6_IRQHandler - LDR R0, =PIN_INT6_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT7_IRQHandler - PUBWEAK PIN_INT7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT7_IRQHandler - LDR R0, =PIN_INT7_DriverIRQHandler - BX R0 - PUBWEAK CTIMER2_IRQHandler - PUBWEAK CTIMER2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER2_IRQHandler - LDR R0, =CTIMER2_DriverIRQHandler - BX R0 - PUBWEAK CTIMER4_IRQHandler - PUBWEAK CTIMER4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER4_IRQHandler - LDR R0, =CTIMER4_DriverIRQHandler - BX R0 - PUBWEAK OS_EVENT_IRQHandler - PUBWEAK OS_EVENT_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -OS_EVENT_IRQHandler - LDR R0, =OS_EVENT_DriverIRQHandler - BX R0 - PUBWEAK Reserved55_IRQHandler - PUBWEAK Reserved55_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved55_IRQHandler - LDR R0, =Reserved55_DriverIRQHandler - BX R0 - PUBWEAK Reserved56_IRQHandler - PUBWEAK Reserved56_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved56_IRQHandler - LDR R0, =Reserved56_DriverIRQHandler - BX R0 - PUBWEAK Reserved57_IRQHandler - PUBWEAK Reserved57_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved57_IRQHandler - LDR R0, =Reserved57_DriverIRQHandler - BX R0 - PUBWEAK SDIO_IRQHandler - PUBWEAK SDIO_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SDIO_IRQHandler - LDR R0, =SDIO_DriverIRQHandler - BX R0 - PUBWEAK Reserved59_IRQHandler - PUBWEAK Reserved59_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved59_IRQHandler - LDR R0, =Reserved59_DriverIRQHandler - BX R0 - PUBWEAK Reserved60_IRQHandler - PUBWEAK Reserved60_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved60_IRQHandler - LDR R0, =Reserved60_DriverIRQHandler - BX R0 - PUBWEAK Reserved61_IRQHandler - PUBWEAK Reserved61_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved61_IRQHandler - LDR R0, =Reserved61_DriverIRQHandler - BX R0 - PUBWEAK USB1_PHY_IRQHandler - PUBWEAK USB1_PHY_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB1_PHY_IRQHandler - LDR R0, =USB1_PHY_DriverIRQHandler - BX R0 - PUBWEAK USB1_IRQHandler - PUBWEAK USB1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB1_IRQHandler - LDR R0, =USB1_DriverIRQHandler - BX R0 - PUBWEAK USB1_NEEDCLK_IRQHandler - PUBWEAK USB1_NEEDCLK_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB1_NEEDCLK_IRQHandler - LDR R0, =USB1_NEEDCLK_DriverIRQHandler - BX R0 - PUBWEAK SEC_HYPERVISOR_CALL_IRQHandler - PUBWEAK SEC_HYPERVISOR_CALL_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_HYPERVISOR_CALL_IRQHandler - LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler - BX R0 - PUBWEAK SEC_GPIO_INT0_IRQ0_IRQHandler - PUBWEAK SEC_GPIO_INT0_IRQ0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_GPIO_INT0_IRQ0_IRQHandler - LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler - BX R0 - PUBWEAK SEC_GPIO_INT0_IRQ1_IRQHandler - PUBWEAK SEC_GPIO_INT0_IRQ1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_GPIO_INT0_IRQ1_IRQHandler - LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler - BX R0 - PUBWEAK PLU_IRQHandler - PUBWEAK PLU_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PLU_IRQHandler - LDR R0, =PLU_DriverIRQHandler - BX R0 - PUBWEAK SEC_VIO_IRQHandler - PUBWEAK SEC_VIO_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_VIO_IRQHandler - LDR R0, =SEC_VIO_DriverIRQHandler - BX R0 - PUBWEAK HASHCRYPT_IRQHandler - PUBWEAK HASHCRYPT_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -HASHCRYPT_IRQHandler - LDR R0, =HASHCRYPT_DriverIRQHandler - BX R0 - PUBWEAK CASER_IRQHandler - PUBWEAK CASER_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CASER_IRQHandler - LDR R0, =CASER_DriverIRQHandler - BX R0 - PUBWEAK PUF_IRQHandler - PUBWEAK PUF_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PUF_IRQHandler - LDR R0, =PUF_DriverIRQHandler - BX R0 - PUBWEAK PQ_IRQHandler - PUBWEAK PQ_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PQ_IRQHandler - LDR R0, =PQ_DriverIRQHandler - BX R0 - PUBWEAK DMA1_IRQHandler - PUBWEAK DMA1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA1_IRQHandler - LDR R0, =DMA1_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM8_IRQHandler - PUBWEAK FLEXCOMM8_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM8_IRQHandler - LDR R0, =FLEXCOMM8_DriverIRQHandler - BX R0 -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_DriverIRQHandler -Reserved39_DriverIRQHandler -ACMP_DriverIRQHandler -Reserved41_DriverIRQHandler -Reserved42_DriverIRQHandler -USB0_NEEDCLK_DriverIRQHandler -USB0_DriverIRQHandler -RTC_DriverIRQHandler -Reserved46_DriverIRQHandler -Reserved47_DriverIRQHandler -PIN_INT4_DriverIRQHandler -PIN_INT5_DriverIRQHandler -PIN_INT6_DriverIRQHandler -PIN_INT7_DriverIRQHandler -CTIMER2_DriverIRQHandler -CTIMER4_DriverIRQHandler -OS_EVENT_DriverIRQHandler -Reserved55_DriverIRQHandler -Reserved56_DriverIRQHandler -Reserved57_DriverIRQHandler -SDIO_DriverIRQHandler -Reserved59_DriverIRQHandler -Reserved60_DriverIRQHandler -Reserved61_DriverIRQHandler -USB1_PHY_DriverIRQHandler -USB1_DriverIRQHandler -USB1_NEEDCLK_DriverIRQHandler -SEC_HYPERVISOR_CALL_DriverIRQHandler -SEC_GPIO_INT0_IRQ0_DriverIRQHandler -SEC_GPIO_INT0_IRQ1_DriverIRQHandler -PLU_DriverIRQHandler -SEC_VIO_DriverIRQHandler -HASHCRYPT_DriverIRQHandler -CASER_DriverIRQHandler -PUF_DriverIRQHandler -PQ_DriverIRQHandler -DMA1_DriverIRQHandler -FLEXCOMM8_DriverIRQHandler -DefaultISR - B . - - END diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/system_LPC55S28.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/system_LPC55S28.c deleted file mode 100644 index d427d42fa16..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/system_LPC55S28.c +++ /dev/null @@ -1,378 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S28JBD100 -** LPC55S28JBD64 -** LPC55S28JEV98 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b220117 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** - rev. 1.1 (2019-05-16) -** Initial A1 version based on v1.3UM -** -** ################################################################### -*/ - -/*! - * @file LPC55S28 - * @version 1.1 - * @date 2019-05-16 - * @brief Device specific configuration file for LPC55S28 (implementation file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include -#include "fsl_device_registers.h" - -/* PLL0 SSCG control1 */ -#define PLL_SSCG_MD_FRACT_P 0U -#define PLL_SSCG_MD_INT_P 25U -#define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P) -#define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P) - -/* Get predivider (N) from PLL0 NDEC setting */ -static uint32_t findPll0PreDiv(void) -{ - uint32_t preDiv = 1UL; - - /* Direct input is not used? */ - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) - { - preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; - if (preDiv == 0UL) - { - preDiv = 1UL; - } - } - return preDiv; -} - -/* Get postdivider (P) from PLL0 PDEC setting */ -static uint32_t findPll0PostDiv(void) -{ - uint32_t postDiv = 1; - - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) - { - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) - { - postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; - } - else - { - postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); - } - if (postDiv == 0UL) - { - postDiv = 2UL; - } - } - return postDiv; -} - -/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ -static float findPll0MMult(void) -{ - float mMult = 1.0F; - float mMult_fract; - uint32_t mMult_int; - - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) - { - mMult = (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); - } - else - { - mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); - mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P); - mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M) / - (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); - mMult = (float)mMult_int + mMult_fract; - } - if (0ULL == ((uint64_t)mMult)) - { - mMult = 1.0F; - } - return mMult; -} - -/* Get predivider (N) from PLL1 NDEC setting */ -static uint32_t findPll1PreDiv(void) -{ - uint32_t preDiv = 1UL; - - /* Direct input is not used? */ - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) - { - preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; - if (preDiv == 0UL) - { - preDiv = 1UL; - } - } - return preDiv; -} - -/* Get postdivider (P) from PLL1 PDEC setting */ -static uint32_t findPll1PostDiv(void) -{ - uint32_t postDiv = 1UL; - - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0UL) - { - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) != 0UL) - { - postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK; - } - else - { - postDiv = 2UL * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK); - } - if (postDiv == 0UL) - { - postDiv = 2UL; - } - } - return postDiv; -} - -/* Get multiplier (M) from PLL1 MDEC settings */ -static uint32_t findPll1MMult(void) -{ - uint32_t mMult = 1UL; - - mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK; - - if (mMult == 0UL) - { - mMult = 1UL; - } - return mMult; -} - -/* Get FRO 12M Clk */ -/*! brief Return Frequency of FRO 12MHz - * return Frequency of FRO 12MHz - */ -static uint32_t GetFro12MFreq(void) -{ - return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; -} - -/* Get FRO 1M Clk */ -/*! brief Return Frequency of FRO 1MHz - * return Frequency of FRO 1MHz - */ -static uint32_t GetFro1MFreq(void) -{ - return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; -} - -/* Get EXT OSC Clk */ -/*! brief Return Frequency of External Clock - * return Frequency of External Clock. If no external clock is used returns 0. - */ -static uint32_t GetExtClkFreq(void) -{ - return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? CLK_CLK_IN : 0U; -} - -/* Get HF FRO Clk */ -/*! brief Return Frequency of High-Freq output of FRO - * return Frequency of High-Freq output of FRO - */ -static uint32_t GetFroHfFreq(void) -{ - return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; -} - -/* Get RTC OSC Clk */ -/*! brief Return Frequency of 32kHz osc - * return Frequency of 32kHz osc - */ -static uint32_t GetOsc32KFreq(void) -{ - return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? - CLK_RTC_32K_CLK : - ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && ((PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK) != 0UL)) ? - CLK_RTC_32K_CLK : - 0U; -} - - - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ - -__attribute__ ((weak)) void SystemInit (void) { -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ - #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ - - SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ - -#if defined(__MCUXPRESSO) - extern void(*const g_pfnVectors[]) (void); - SCB->VTOR = (uint32_t) &g_pfnVectors; -#else - extern void *__Vectors; - SCB->VTOR = (uint32_t) &__Vectors; -#endif - SYSCON->TRACECLKDIV = 0; -/* Optionally enable RAM banks that may be off by default at reset */ -#if !defined(DONT_ENABLE_DISABLED_RAMBANKS) - SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK - | SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK; -#endif - SystemInitHook(); -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate (void) { - uint32_t clkRate = 0; - uint32_t prediv, postdiv; - uint64_t workRate; - uint64_t workRate1; - - switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) - { - case 0x00: /* MAINCLKSELA clock (main_clk_a)*/ - switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = GetFro12MFreq(); - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = GetExtClkFreq(); - break; - case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = GetFro1MFreq(); - break; - default: /* = 0x03 = FRO 96 MHz (fro_hf) */ - clkRate = GetFroHfFreq(); - break; - } - break; - case 0x01: /* PLL0 clock (pll0_clk)*/ - switch (SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = GetFro12MFreq(); - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = GetExtClkFreq(); - break; - case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = GetFro1MFreq(); - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = GetOsc32KFreq(); - break; - default: - clkRate = 0UL; - break; - } - if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) - { - prediv = findPll0PreDiv(); - postdiv = findPll0PostDiv(); - /* Adjust input clock */ - clkRate = clkRate / prediv; - /* MDEC used for rate */ - workRate = (uint64_t)clkRate * (uint64_t)findPll0MMult(); - clkRate = (uint32_t)(workRate / ((uint64_t)postdiv)); - } - break; - case 0x02: /* PLL1 clock (pll1_clk)*/ - switch (SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = GetFro12MFreq(); - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = GetExtClkFreq(); - break; - case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = GetFro1MFreq(); - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = GetOsc32KFreq(); - break; - default: - clkRate = 0UL; - break; - } - if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0UL)) - { - /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ - prediv = findPll1PreDiv(); - postdiv = findPll1PostDiv(); - /* Adjust input clock */ - clkRate = clkRate / prediv; - - /* MDEC used for rate */ - workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult(); - clkRate = (uint32_t)(workRate1 / ((uint64_t)postdiv)); - } - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = GetOsc32KFreq(); - break; - default: - clkRate = 0UL; - break; - } - SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL); -} - -/* ---------------------------------------------------------------------------- - -- SystemInitHook() - ---------------------------------------------------------------------------- */ - -__attribute__ ((weak)) void SystemInitHook (void) { - /* Void implementation of the weak function. */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/system_LPC55S28.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/system_LPC55S28.h deleted file mode 100644 index 06d8f678e5a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/LPC55S28/system_LPC55S28.h +++ /dev/null @@ -1,112 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S28JBD100 -** LPC55S28JBD64 -** LPC55S28JEV98 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b220117 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** - rev. 1.1 (2019-05-16) -** Initial A1 version based on v1.3UM -** -** ################################################################### -*/ - -/*! - * @file LPC55S28 - * @version 1.1 - * @date 2019-05-16 - * @brief Device specific configuration file for LPC55S28 (header file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef _SYSTEM_LPC55S28_H_ -#define _SYSTEM_LPC55S28_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ -#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ -#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ -#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ -#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ -#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ - - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -/** - * @brief SystemInit function hook. - * - * This weak function allows to call specific initialization code during the - * SystemInit() execution.This can be used when an application specific code needs - * to be called as close to the reset entry as possible (for example the Multicore - * Manager MCMGR_EarlyInit() function call). - * NOTE: No global r/w variables can be used in this hook function because the - * initialization of these variables happens after this function. - */ -void SystemInitHook (void); - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_LPC55S28_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/SConscript b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/SConscript deleted file mode 100644 index 37f8441322d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S28/SConscript +++ /dev/null @@ -1,59 +0,0 @@ -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -path = [cwd + '/../CMSIS/Core/Include',cwd + '/components/codec', cwd + '/LPC55S28', cwd + '/LPC55S28/drivers', cwd + '/middleware/sdmmc/inc', cwd + '/middleware/sdmmc/port'] -src = Split(''' - LPC55S28/system_LPC55S28.c - ''') - -if rtconfig.PLATFORM in ['gcc']: - src += ['LPC55S28/gcc/startup_LPC55S28.S'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - src += ['LPC55S28/arm/startup_LPC55S28.s'] -elif rtconfig.PLATFORM in ['iccarm']: - src += ['LPC55S28/iar/startup_LPC55S28.s'] - -src += ['LPC55S28/drivers/fsl_anactrl.c'] -src += ['LPC55S28/drivers/fsl_casper.c'] -src += ['LPC55S28/drivers/fsl_clock.c'] -src += ['LPC55S28/drivers/fsl_cmp.c'] -src += ['LPC55S28/drivers/fsl_common.c'] -src += ['LPC55S28/drivers/fsl_common_arm.c'] -src += ['LPC55S28/drivers/fsl_crc.c'] -src += ['LPC55S28/drivers/fsl_ctimer.c'] -src += ['LPC55S28/drivers/fsl_flexcomm.c'] -src += ['LPC55S28/drivers/fsl_dma.c'] -src += ['LPC55S28/drivers/fsl_gint.c'] -src += ['LPC55S28/drivers/fsl_gpio.c'] -src += ['LPC55S28/drivers/fsl_hashcrypt.c'] -src += ['LPC55S28/drivers/fsl_i2c.c'] -src += ['LPC55S28/drivers/fsl_i2c_dma.c'] -src += ['LPC55S28/drivers/fsl_i2s.c'] -src += ['LPC55S28/drivers/fsl_i2s_dma.c'] -src += ['LPC55S28/drivers/fsl_iap.c'] -src += ['LPC55S28/drivers/fsl_inputmux.c'] -src += ['LPC55S28/drivers/fsl_lpadc.c'] -src += ['LPC55S28/drivers/fsl_mrt.c'] -src += ['LPC55S28/drivers/fsl_ostimer.c'] -src += ['LPC55S28/drivers/fsl_pint.c'] -src += ['LPC55S28/drivers/fsl_plu.c'] -src += ['LPC55S28/drivers/fsl_power.c'] -src += ['LPC55S28/drivers/fsl_puf.c'] -src += ['LPC55S28/drivers/fsl_reset.c'] -src += ['LPC55S28/drivers/fsl_rng.c'] -src += ['LPC55S28/drivers/fsl_rtc.c'] -src += ['LPC55S28/drivers/fsl_sctimer.c'] -src += ['LPC55S28/drivers/fsl_sdif.c'] -src += ['LPC55S28/drivers/fsl_spi.c'] -src += ['LPC55S28/drivers/fsl_spi_dma.c'] -src += ['LPC55S28/drivers/fsl_sysctl.c'] -src += ['LPC55S28/drivers/fsl_usart.c'] -src += ['LPC55S28/drivers/fsl_usart_dma.c'] -src += ['LPC55S28/drivers/fsl_utick.c'] -src += ['LPC55S28/drivers/fsl_wwdt.c'] - - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) - -Return('group') diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/LPC55S36.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/LPC55S36.h deleted file mode 100644 index f9d299eb552..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/LPC55S36.h +++ /dev/null @@ -1,62734 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S36JBD100 -** LPC55S36JHI48 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 -** Version: rev. 1.1, 2021-08-04 -** Build: b220118 -** -** Abstract: -** CMSIS Peripheral Access Layer for LPC55S36 -** -** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2021-04-12) -** Initial version based on RM DraftF -** - rev. 1.1 (2021-08-04) -** Initial version based on RM DraftG -** -** ################################################################### -*/ - -/*! - * @file LPC55S36.h - * @version 1.1 - * @date 2021-08-04 - * @brief CMSIS Peripheral Access Layer for LPC55S36 - * - * CMSIS Peripheral Access Layer for LPC55S36 - */ - -#ifndef _LPC55S36_H_ -#define _LPC55S36_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0001U - - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 136 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Auxiliary constants */ - NotAvail_IRQn = -128, /**< Not available device specific interrupt */ - - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ - - /* Device specific interrupts */ - WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */ - DMA0_IRQn = 1, /**< DMA0 controller */ - GINT0_IRQn = 2, /**< GPIO group 0 */ - GINT1_IRQn = 3, /**< GPIO group 1 */ - PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ - PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ - PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ - PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ - UTICK0_IRQn = 8, /**< Micro-tick Timer */ - MRT0_IRQn = 9, /**< Multi-rate timer */ - CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ - CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ - SCT0_IRQn = 12, /**< SCTimer/PWM */ - CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ - FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - ADC0_IRQn = 22, /**< ADC0 */ - ADC1_IRQn = 23, /**< ADC1 */ - ACMP_IRQn = 24, /**< ACMP interrupts */ - DMIC_IRQn = 25, /**< Digital microphone and DMIC subsystem */ - HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */ - USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ - USB0_IRQn = 28, /**< USB device */ - RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ - EZH_ARCH_B0_IRQn = 30, /**< EZH interrupt */ - WAKEUP_IRQn = 31, /**< Wakeup interrupt */ - PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ - PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ - PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ - PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ - CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ - CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ - OS_EVENT_IRQn = 38, /**< OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ - FlexSPI0_IRQn = 39, /**< FlexSPI interrupt */ - Reserved56_IRQn = 40, /**< Reserved interrupt */ - Reserved57_IRQn = 41, /**< Reserved interrupt */ - Reserved58_IRQn = 42, /**< Reserved interrupt */ - CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */ - CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */ - SPI_FILTER_IRQn = 45, /**< SPI Filter interrupt */ - Reserved62_IRQn = 46, /**< Reserved interrupt */ - Reserved63_IRQn = 47, /**< Reserved interrupt */ - Reserved64_IRQn = 48, /**< Reserved interrupt */ - SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */ - SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT00 interrupt */ - SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT01 interrupt */ - Freqme_IRQn = 52, /**< frequency measure interrupt */ - SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */ - CSS_IRQn = 54, /**< SHA interrupt */ - PKC_IRQn = 55, /**< CASPER interrupt */ - PUF_IRQn = 56, /**< PUF interrupt */ - POWERQUAD_IRQn = 57, /**< PowerQuad interrupt */ - DMA1_IRQn = 58, /**< DMA1 interrupt */ - FLEXCOMM8_IRQn = 59, /**< LSPI_HS interrupt */ - CDOG_IRQn = 60, /**< CodeWDG interrupt */ - Reserved77_IRQn = 61, /**< Reserved interrupt */ - I3C0_IRQn = 62, /**< I3C interrupt */ - Reserved79_IRQn = 63, /**< Reserved interrupt */ - Reserved80_IRQn = 64, /**< Reserved interrupt */ - CSS_IRQ1_IRQn = 65, /**< CSS_IRQ1 */ - Tamper_IRQn = 66, /**< Tamper */ - Reserved83_IRQn = 67, /**< Reserved interrupt */ - Reserved84_IRQn = 68, /**< Reserved interrupt */ - Reserved85_IRQn = 69, /**< Reserved interrupt */ - Reserved86_IRQn = 70, /**< Reserved interrupt */ - Reserved87_IRQn = 71, /**< Reserved interrupt */ - Reserved88_IRQn = 72, /**< Reserved interrupt */ - Reserved89_IRQn = 73, /**< Reserved interrupt */ - DAC0_IRQn = 74, /**< dac0 interrupt */ - DAC1_IRQn = 75, /**< dac1 interrupt */ - DAC2_IRQn = 76, /**< dac2 interrupt */ - HSCMP0_IRQn = 77, /**< hscmp0 interrupt */ - HSCMP1_IRQn = 78, /**< hscmp1 interrupt */ - HSCMP2_IRQn = 79, /**< hscmp2 interrupt */ - FLEXPWM0_CAPTURE_IRQn = 80, /**< flexpwm0_capture interrupt */ - FLEXPWM0_FAULT_IRQn = 81, /**< flexpwm0_fault interrupt */ - FLEXPWM0_RELOAD_ERROR_IRQn = 82, /**< flexpwm0_reload_error interrupt */ - FLEXPWM0_COMPARE0_IRQn = 83, /**< flexpwm0_compare0 interrupt */ - FLEXPWM0_RELOAD0_IRQn = 84, /**< flexpwm0_reload0 interrupt */ - FLEXPWM0_COMPARE1_IRQn = 85, /**< flexpwm0_compare1 interrupt */ - FLEXPWM0_RELOAD1_IRQn = 86, /**< flexpwm0_reload1 interrupt */ - FLEXPWM0_COMPARE2_IRQn = 87, /**< flexpwm0_compare2 interrupt */ - FLEXPWM0_RELOAD2_IRQn = 88, /**< flexpwm0_reload2 interrupt */ - FLEXPWM0_COMPARE3_IRQn = 89, /**< flexpwm0_compare3 interrupt */ - FLEXPWM0_RELOAD3_IRQn = 90, /**< flexpwm0_reload3 interrupt */ - FLEXPWM1_CAPTURE_IRQn = 91, /**< flexpwm1_capture interrupt */ - FLEXPWM1_FAULT_IRQn = 92, /**< flexpwm1_fault interrupt */ - FLEXPWM1_RELOAD_ERROR_IRQn = 93, /**< flexpwm1_reload_error interrupt */ - FLEXPWM1_COMPARE0_IRQn = 94, /**< flexpwm1_compare0 interrupt */ - FLEXPWM1_RELOAD0_IRQn = 95, /**< flexpwm1_reload0 interrupt */ - FLEXPWM1_COMPARE1_IRQn = 96, /**< flexpwm1_compare1 interrupt */ - FLEXPWM1_RELOAD1_IRQn = 97, /**< flexpwm1_reload1 interrupt */ - FLEXPWM1_COMPARE2_IRQn = 98, /**< flexpwm1_compare2 interrupt */ - FLEXPWM1_RELOAD2_IRQn = 99, /**< flexpwm1_reload2 interrupt */ - FLEXPWM1_COMPARE3_IRQn = 100, /**< flexpwm1_compare3 interrupt */ - FLEXPWM1_RELOAD3_IRQn = 101, /**< flexpwm1_reload3 interrupt */ - ENC0_COMPARE_IRQn = 102, /**< enc0_compare interrupt */ - ENC0_HOME_IRQn = 103, /**< enc0_home interrupt */ - ENC0_WDG_IRQn = 104, /**< enc0_wdg interrupt */ - ENC0_IDX_IRQn = 105, /**< enc0_idx interrupt */ - ENC1_COMPARE_IRQn = 106, /**< enc1_compare interrupt */ - ENC1_HOME_IRQn = 107, /**< enc1_home interrupt */ - ENC1_WDG_IRQn = 108, /**< enc1_wdg interrupt */ - ENC1_IDX_IRQn = 109, /**< enc1_idx interrupt */ - ITRC0_IRQn = 110, /**< itrc0 interrupt */ - Reserved127_IRQn = 111, /**< Reserved interrupt */ - CSSV2_ERR_IRQn = 112, /**< cssv2_err interrupt */ - PKC_ERR_IRQn = 113, /**< pkc_err interrupt */ - Reserved130_IRQn = 114, /**< Reserved interrupt */ - Reserved131_IRQn = 115, /**< Reserved interrupt */ - Reserved132_IRQn = 116, /**< Reserved interrupt */ - Reserved133_IRQn = 117, /**< Reserved interrupt */ - FLASH_IRQn = 118, /**< flash interrupt */ - RAM_PARITY_ECC_ERR_IRQn = 119 /**< ram_parity_ecc_err interrupt */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M33 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration - * @{ - */ - -#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ -#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ -#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ -#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ - -#include "core_cm33.h" /* Core Peripheral Access Layer */ -#include "system_LPC55S36.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Mapping Information - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Mapping_Information Mapping Information - * @{ - */ - -/** Mapping Information */ -/*! - * @addtogroup dma_request - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief Structure for the DMA hardware request - * - * Defines the structure for the DMA hardware request collections. The user can configure the - * hardware request to trigger the DMA transfer accordingly. The index - * of the hardware request varies according to the to SoC. - */ -typedef enum _dma_request_source -{ - kDma0RequestFLEXSPIRX = 0U, /**< FlexSPI RX */ - kDma1RequestUnusedDMARequest0 = 0U, /**< Unused DMA request 0 */ - kDma0RequestFLEXSPITX = 1U, /**< FlexSPI TX */ - kDma1RequestUnusedDMARequest1 = 1U, /**< Unused DMA request 1 */ - kDma0RequestHSSPIRX = 2U, /**< HS_SPI RX(Flexcomm Interface 8 RX) */ - kDma1RequestHSLSPIRX = 2U, /**< High Speed SPI RX( */ - kDma0RequestHSSPITX = 3U, /**< HS_SPI TX(Flexcomm Interface 8 TX) */ - kDma1RequestHSLSPITX = 3U, /**< High Speed SPI TX( */ - kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ - kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX */ - kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ - kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX */ - kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ - kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX */ - kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ - kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX */ - kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ - kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX */ - kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ - kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX */ - kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */ - kDma1RequestDmic0Ch0 = 10U, /**< DMIC0 CH0 */ - kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */ - kDma1RequestDmic0Ch1 = 11U, /**< DMIC0 CH1 */ - kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */ - kDma1RequestI3c0Rx = 12U, /**< I3C0 RX */ - kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */ - kDma1RequestI3c0Tx = 13U, /**< I3C0 TX */ - kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */ - kDma1RequestFLEXSPIRX = 14U, /**< FlexSpi RX */ - kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */ - kDma1RequestFLEXSPITX = 15U, /**< FlexSpi TX */ - kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */ - kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */ - kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */ - kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */ - kDma0RequestDAC0 = 20U, /**< DAC0 */ - kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */ - kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */ - kDma0RequestDMIC0CH0 = 23U, /**< DMIC0 channel0 */ - kDma0RequestDMIC0CH1 = 24U, /**< DMIC0 channel1 */ - kDma0RequestI3C0RX = 25U, /**< I3C0 RX */ - kDma0RequestI3C0TX = 26U, /**< I3C0 TX */ - kDma0RequestADC1FIFO0 = 27U, /**< ADC1 FIFO 0 */ - kDma0RequestADC1FIFO1 = 28U, /**< ADC1 FIFO 1 */ - kDma0RequestDAC1 = 29U, /**< DAC1 */ - kDma0RequestDAC2 = 30U, /**< DAC2 */ - kDma0RequestUnusedDMARequest31 = 31U, /**< Unused DMA request 31 */ - kDma0RequestUnusedDMARequest32 = 32U, /**< Unused DMA request 32 */ - kDma0RequestUnusedDMARequest33 = 33U, /**< Unused DMA request 33 */ - kDma0RequestUnusedDMARequest34 = 34U, /**< Unused DMA request 34 */ - kDma0RequestUnusedDMARequest35 = 35U, /**< Unused DMA request 35 */ - kDma0RequestUnassignedDMARequest36 = 36U, /**< Unassigned DMA request 36(but required for FlexPWM0_req_capt0) */ - kDma0RequestUnassignedDMARequest37 = 37U, /**< Unassigned DMA request 37(but required for FlexPWM0_req_capt1) */ - kDma0RequestUnassignedDMARequest38 = 38U, /**< Unassigned DMA request 38(but required for FlexPWM0_req_capt2) */ - kDma0RequestUnassignedDMARequest39 = 39U, /**< Unassigned DMA request 39(but required for FlexPWM0_req_capt3) */ - kDma0RequestUnassignedDMARequest40 = 40U, /**< Unassigned DMA request 40(but required for FlexPWM0_req_val0) */ - kDma0RequestUnassignedDMARequest41 = 41U, /**< Unassigned DMA request 41(but required for FlexPWM0_req_val1) */ - kDma0RequestUnassignedDMARequest42 = 42U, /**< Unassigned DMA request 42(but required for FlexPWM0_req_val2) */ - kDma0RequestUnassignedDMARequest43 = 43U, /**< Unassigned DMA request 43(but required for FlexPWM0_req_val3) */ - kDma0RequestUnassignedDMARequest44 = 44U, /**< Unassigned DMA request 44(but required for FlexPWM1_req_capt0) */ - kDma0RequestUnassignedDMARequest45 = 45U, /**< Unassigned DMA request 45(but required for FlexPWM1_req_capt1) */ - kDma0RequestUnassignedDMARequest46 = 46U, /**< Unassigned DMA request 46(but required for FlexPWM1_req_capt2) */ - kDma0RequestUnassignedDMARequest47 = 47U, /**< Unassigned DMA request 47(but required for FlexPWM1_req_capt3) */ - kDma0RequestUnassignedDMARequest48 = 48U, /**< Unassigned DMA request 48(but required for FlexPWM1_req_val0) */ - kDma0RequestUnassignedDMARequest49 = 49U, /**< Unassigned DMA request 49(but required for FlexPWM1_req_val1) */ - kDma0RequestUnassignedDMARequest50 = 50U, /**< Unassigned DMA request 50(but required for FlexPWM1_req_val2) */ - kDma0RequestUnassignedDMARequest51 = 51U, /**< Unassigned DMA request 51(but required for FlexPWM1_req_val3) */ -} dma_request_source_t; - -/* @} */ - - -/*! - * @} - */ /* end of group Mapping_Information */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #else - #pragma push - #pragma anon_unions - #endif -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ - __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ - __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ - __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ - __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ - __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ - uint8_t RESERVED_1[12]; - __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ - __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ - uint8_t RESERVED_2[4]; - __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ - uint8_t RESERVED_3[92]; - __IO uint32_t TCTRL[4]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ - uint8_t RESERVED_4[48]; - __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ - uint8_t RESERVED_5[8]; - __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ - __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ - struct { /* offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ - } CMD[15]; - uint8_t RESERVED_6[136]; - __IO uint32_t CV[15]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_7[196]; - __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ - uint8_t RESERVED_8[248]; - __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ - uint8_t RESERVED_9[124]; - __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ - -#define ADC_VERID_RES_MASK (0x1U) -#define ADC_VERID_RES_SHIFT (0U) -/*! RES - Resolution - * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. - * 0b1..Up to 16-bit differential/16-bit single ended resolution supported. - */ -#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) - -#define ADC_VERID_DIFFEN_MASK (0x2U) -#define ADC_VERID_DIFFEN_SHIFT (1U) -/*! DIFFEN - Differential Supported - * 0b0..Differential operation not supported. - * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented. - */ -#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) - -#define ADC_VERID_MVI_MASK (0x8U) -#define ADC_VERID_MVI_SHIFT (3U) -/*! MVI - Multi Vref Implemented - * 0b0..Single voltage reference high (VREFH) input supported. - * 0b1..Multiple voltage reference high (VREFH) inputs supported. - */ -#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) - -#define ADC_VERID_CSW_MASK (0x70U) -#define ADC_VERID_CSW_SHIFT (4U) -/*! CSW - Channel Scale Width - * 0b000..Channel scaling not supported. - * 0b001..Channel scaling supported. 1-bit CSCALE control field. - * 0b110..Channel scaling supported. 6-bit CSCALE control field. - */ -#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) - -#define ADC_VERID_VR1RNGI_MASK (0x100U) -#define ADC_VERID_VR1RNGI_SHIFT (8U) -/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented - * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. - * 0b1..Range control required. CFG[VREF1RNG] is implemented. - */ -#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) - -#define ADC_VERID_IADCKI_MASK (0x200U) -#define ADC_VERID_IADCKI_SHIFT (9U) -/*! IADCKI - Internal ADC Clock implemented - * 0b0..Internal clock source not implemented. - * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. - */ -#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) - -#define ADC_VERID_CALOFSI_MASK (0x400U) -#define ADC_VERID_CALOFSI_SHIFT (10U) -/*! CALOFSI - Calibration Function Implemented - * 0b0..Calibration Not Implemented. - * 0b1..Calibration Implemented. - */ -#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) - -#define ADC_VERID_NUM_SEC_MASK (0x800U) -#define ADC_VERID_NUM_SEC_SHIFT (11U) -/*! NUM_SEC - Number of Single Ended Outputs Supported - * 0b0..This design supports one single ended conversion at a time. - * 0b1..This design supports two simultanious single ended conversions. - */ -#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) - -#define ADC_VERID_NUM_FIFO_MASK (0x7000U) -#define ADC_VERID_NUM_FIFO_SHIFT (12U) -/*! NUM_FIFO - Number of FIFOs - * 0b000..N/A - * 0b001..This design supports one result FIFO. - * 0b010..This design supports two result FIFOs. - * 0b011..This design supports three result FIFOs. - * 0b100..This design supports four result FIFOs. - */ -#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) - -#define ADC_VERID_MINOR_MASK (0xFF0000U) -#define ADC_VERID_MINOR_SHIFT (16U) -/*! MINOR - Minor Version Number - */ -#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) - -#define ADC_VERID_MAJOR_MASK (0xFF000000U) -#define ADC_VERID_MAJOR_SHIFT (24U) -/*! MAJOR - Major Version Number - */ -#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ - -#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) -#define ADC_PARAM_TRIG_NUM_SHIFT (0U) -/*! TRIG_NUM - Trigger Number - */ -#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) - -#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) -#define ADC_PARAM_FIFOSIZE_SHIFT (8U) -/*! FIFOSIZE - Result FIFO Depth - * 0b00000001..Result FIFO depth = 1 dataword. - * 0b00000100..Result FIFO depth = 4 datawords. - * 0b00001000..Result FIFO depth = 8 datawords. - * 0b00010000..Result FIFO depth = 16 datawords. - * 0b00100000..Result FIFO depth = 32 datawords. - * 0b01000000..Result FIFO depth = 64 datawords. - */ -#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) - -#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) -#define ADC_PARAM_CV_NUM_SHIFT (16U) -/*! CV_NUM - Compare Value Number - */ -#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) - -#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) -#define ADC_PARAM_CMD_NUM_SHIFT (24U) -/*! CMD_NUM - Command Buffer Number - */ -#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) -/*! @} */ - -/*! @name CTRL - ADC Control Register */ -/*! @{ */ - -#define ADC_CTRL_ADCEN_MASK (0x1U) -#define ADC_CTRL_ADCEN_SHIFT (0U) -/*! ADCEN - ADC Enable - * 0b0..ADC is disabled. - * 0b1..ADC is enabled. - */ -#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) - -#define ADC_CTRL_RST_MASK (0x2U) -#define ADC_CTRL_RST_SHIFT (1U) -/*! RST - Software Reset - * 0b0..ADC logic is not reset. - * 0b1..ADC logic is reset. - */ -#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) - -#define ADC_CTRL_DOZEN_MASK (0x4U) -#define ADC_CTRL_DOZEN_SHIFT (2U) -/*! DOZEN - Doze Enable - * 0b0..ADC is enabled in low power mode. - * 0b1..ADC is disabled in low power mode. - */ -#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) - -#define ADC_CTRL_CAL_REQ_MASK (0x8U) -#define ADC_CTRL_CAL_REQ_SHIFT (3U) -/*! CAL_REQ - Auto-Calibration Request - * 0b0..No request for auto-calibration has been made. - * 0b1..A request for auto-calibration has been made - */ -#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) - -#define ADC_CTRL_CALOFS_MASK (0x10U) -#define ADC_CTRL_CALOFS_SHIFT (4U) -/*! CALOFS - Configure for offset calibration function - * 0b0..Calibration function disabled - * 0b1..Request for offset calibration function - */ -#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) - -#define ADC_CTRL_RSTFIFO0_MASK (0x100U) -#define ADC_CTRL_RSTFIFO0_SHIFT (8U) -/*! RSTFIFO0 - Reset FIFO 0 - * 0b0..No effect. - * 0b1..FIFO 0 is reset. - */ -#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) - -#define ADC_CTRL_RSTFIFO1_MASK (0x200U) -#define ADC_CTRL_RSTFIFO1_SHIFT (9U) -/*! RSTFIFO1 - Reset FIFO 1 - * 0b0..No effect. - * 0b1..FIFO 1 is reset. - */ -#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) - -#define ADC_CTRL_CAL_AVGS_MASK (0x70000U) -#define ADC_CTRL_CAL_AVGS_SHIFT (16U) -/*! CAL_AVGS - Auto-Calibration Averages - * 0b000..Single conversion. - * 0b001..2 conversions averaged. - * 0b010..4 conversions averaged. - * 0b011..8 conversions averaged. - * 0b100..16 conversions averaged. - * 0b101..32 conversions averaged. - * 0b110..64 conversions averaged. - * 0b111..128 conversions averaged. - */ -#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) -/*! @} */ - -/*! @name STAT - ADC Status Register */ -/*! @{ */ - -#define ADC_STAT_RDY0_MASK (0x1U) -#define ADC_STAT_RDY0_SHIFT (0U) -/*! RDY0 - Result FIFO 0 Ready Flag - * 0b0..Result FIFO 0 data level not above watermark level. - * 0b1..Result FIFO 0 holding data above watermark level. - */ -#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) - -#define ADC_STAT_FOF0_MASK (0x2U) -#define ADC_STAT_FOF0_SHIFT (1U) -/*! FOF0 - Result FIFO 0 Overflow Flag - * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) - -#define ADC_STAT_RDY1_MASK (0x4U) -#define ADC_STAT_RDY1_SHIFT (2U) -/*! RDY1 - Result FIFO1 Ready Flag - * 0b0..Result FIFO1 data level not above watermark level. - * 0b1..Result FIFO1 holding data above watermark level. - */ -#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) - -#define ADC_STAT_FOF1_MASK (0x8U) -#define ADC_STAT_FOF1_SHIFT (3U) -/*! FOF1 - Result FIFO1 Overflow Flag - * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) - -#define ADC_STAT_TEXC_INT_MASK (0x100U) -#define ADC_STAT_TEXC_INT_SHIFT (8U) -/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception - * 0b0..No trigger exceptions have occurred. - * 0b1..A trigger exception has occurred and is pending acknowledgement. - */ -#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) - -#define ADC_STAT_TCOMP_INT_MASK (0x200U) -#define ADC_STAT_TCOMP_INT_SHIFT (9U) -/*! TCOMP_INT - Interrupt Flag For Trigger Completion - * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. - * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. - */ -#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) - -#define ADC_STAT_CAL_RDY_MASK (0x400U) -#define ADC_STAT_CAL_RDY_SHIFT (10U) -/*! CAL_RDY - Calibration Ready - * 0b0..Calibration is incomplete or hasn't been ran. - * 0b1..The ADC is calibrated. - */ -#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) - -#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) -#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) -/*! ADC_ACTIVE - ADC Active - * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. - * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. - */ -#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) - -#define ADC_STAT_TRGACT_MASK (0x30000U) -#define ADC_STAT_TRGACT_SHIFT (16U) -/*! TRGACT - Trigger Active - * 0b00..Command (sequence) associated with Trigger 0 currently being executed. - * 0b01..Command (sequence) associated with Trigger 1 currently being executed. - * 0b10..Command (sequence) associated with Trigger 2 currently being executed. - * 0b11..Command (sequence) associated with Trigger 3 currently being executed. - */ -#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) - -#define ADC_STAT_CMDACT_MASK (0xF000000U) -#define ADC_STAT_CMDACT_SHIFT (24U) -/*! CMDACT - Command Active - * 0b0000..No command is currently in progress. - * 0b0001..Command 1 currently being executed. - * 0b0010..Command 2 currently being executed. - * 0b0011-0b1111..Associated command number is currently being executed. - */ -#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) -/*! @} */ - -/*! @name IE - Interrupt Enable Register */ -/*! @{ */ - -#define ADC_IE_FWMIE0_MASK (0x1U) -#define ADC_IE_FWMIE0_SHIFT (0U) -/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable - * 0b0..FIFO 0 watermark interrupts are not enabled. - * 0b1..FIFO 0 watermark interrupts are enabled. - */ -#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) - -#define ADC_IE_FOFIE0_MASK (0x2U) -#define ADC_IE_FOFIE0_SHIFT (1U) -/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable - * 0b0..FIFO 0 overflow interrupts are not enabled. - * 0b1..FIFO 0 overflow interrupts are enabled. - */ -#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) - -#define ADC_IE_FWMIE1_MASK (0x4U) -#define ADC_IE_FWMIE1_SHIFT (2U) -/*! FWMIE1 - FIFO1 Watermark Interrupt Enable - * 0b0..FIFO1 watermark interrupts are not enabled. - * 0b1..FIFO1 watermark interrupts are enabled. - */ -#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) - -#define ADC_IE_FOFIE1_MASK (0x8U) -#define ADC_IE_FOFIE1_SHIFT (3U) -/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable - * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) - -#define ADC_IE_TEXC_IE_MASK (0x100U) -#define ADC_IE_TEXC_IE_SHIFT (8U) -/*! TEXC_IE - Trigger Exception Interrupt Enable - * 0b0..Trigger exception interrupts are disabled. - * 0b1..Trigger exception interrupts are enabled. - */ -#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) - -#define ADC_IE_TCOMP_IE_MASK (0xF0000U) -#define ADC_IE_TCOMP_IE_SHIFT (16U) -/*! TCOMP_IE - Trigger Completion Interrupt Enable - * 0b0000..Trigger completion interrupts are disabled. - * 0b0001..Trigger completion interrupts are enabled for trigger source 0 only. - * 0b0010..Trigger completion interrupts are enabled for trigger source 1 only. - * 0b0011-0b1110..Associated trigger completion interrupts are enabled. - * 0b1111..Trigger completion interrupts are enabled for every trigger source. - */ -#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) -/*! @} */ - -/*! @name DE - DMA Enable Register */ -/*! @{ */ - -#define ADC_DE_FWMDE0_MASK (0x1U) -#define ADC_DE_FWMDE0_SHIFT (0U) -/*! FWMDE0 - FIFO 0 Watermark DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) - -#define ADC_DE_FWMDE1_MASK (0x2U) -#define ADC_DE_FWMDE1_SHIFT (1U) -/*! FWMDE1 - FIFO1 Watermark DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) -/*! @} */ - -/*! @name CFG - ADC Configuration Register */ -/*! @{ */ - -#define ADC_CFG_TPRICTRL_MASK (0x3U) -#define ADC_CFG_TPRICTRL_SHIFT (0U) -/*! TPRICTRL - ADC trigger priority control - * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted - * and the new command specified by the trigger is started. - * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after - * completing the current conversion. If averaging is enabled, the averaging loop will be completed. - * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. - * 0b10..If a higher priority trigger is received during command processing, the current command will be - * completed (averaging, looping, compare) before servicing the higher priority trigger. - * 0b11..RESERVED - */ -#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) - -#define ADC_CFG_PWRSEL_MASK (0x30U) -#define ADC_CFG_PWRSEL_SHIFT (4U) -/*! PWRSEL - Power Configuration Select - * 0b0x..Low power setting. - * 0b1x..High power setting. - */ -#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) - -#define ADC_CFG_REFSEL_MASK (0xC0U) -#define ADC_CFG_REFSEL_SHIFT (6U) -/*! REFSEL - Voltage Reference Selection - * 0b00..(Default) Option 1 setting. - * 0b01..Option 2 setting. - * 0b10..Option 3 setting. - * 0b11..Reserved - */ -#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) - -#define ADC_CFG_TRES_MASK (0x100U) -#define ADC_CFG_TRES_SHIFT (8U) -/*! TRES - Trigger Resume Enable - * 0b0..Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted. - * 0b1..Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted. - */ -#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) - -#define ADC_CFG_TCMDRES_MASK (0x200U) -#define ADC_CFG_TCMDRES_SHIFT (9U) -/*! TCMDRES - Trigger Command Resume - * 0b0..Trigger sequences interrupted by a high priority trigger exception is automatically restarted. - * 0b1..Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception. - */ -#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) - -#define ADC_CFG_HPT_EXDI_MASK (0x400U) -#define ADC_CFG_HPT_EXDI_SHIFT (10U) -/*! HPT_EXDI - High Priority Trigger Exception Disable - * 0b0..High priority trigger exceptions are enabled. - * 0b1..High priority trigger exceptions are disabled. - */ -#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) - -#define ADC_CFG_PUDLY_MASK (0xFF0000U) -#define ADC_CFG_PUDLY_SHIFT (16U) -/*! PUDLY - Power Up Delay - */ -#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) - -#define ADC_CFG_PWREN_MASK (0x10000000U) -#define ADC_CFG_PWREN_SHIFT (28U) -/*! PWREN - ADC Analog Pre-Enable - * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. - * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost - * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN - * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. - * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be - * executed. - */ -#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) -/*! @} */ - -/*! @name PAUSE - ADC Pause Register */ -/*! @{ */ - -#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) -#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) -/*! PAUSEDLY - Pause Delay - */ -#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) - -#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) -#define ADC_PAUSE_PAUSEEN_SHIFT (31U) -/*! PAUSEEN - PAUSE Option Enable - * 0b0..Pause operation disabled - * 0b1..Pause operation enabled - */ -#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) -/*! @} */ - -/*! @name SWTRIG - Software Trigger Register */ -/*! @{ */ - -#define ADC_SWTRIG_SWT0_MASK (0x1U) -#define ADC_SWTRIG_SWT0_SHIFT (0U) -/*! SWT0 - Software trigger 0 event - * 0b0..No trigger 0 event generated. - * 0b1..Trigger 0 event generated. - */ -#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) - -#define ADC_SWTRIG_SWT1_MASK (0x2U) -#define ADC_SWTRIG_SWT1_SHIFT (1U) -/*! SWT1 - Software trigger 1 event - * 0b0..No trigger 1 event generated. - * 0b1..Trigger 1 event generated. - */ -#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) - -#define ADC_SWTRIG_SWT2_MASK (0x4U) -#define ADC_SWTRIG_SWT2_SHIFT (2U) -/*! SWT2 - Software trigger 2 event - * 0b0..No trigger 2 event generated. - * 0b1..Trigger 2 event generated. - */ -#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) - -#define ADC_SWTRIG_SWT3_MASK (0x8U) -#define ADC_SWTRIG_SWT3_SHIFT (3U) -/*! SWT3 - Software trigger 3 event - * 0b0..No trigger 3 event generated. - * 0b1..Trigger 3 event generated. - */ -#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) -/*! @} */ - -/*! @name TSTAT - Trigger Status Register */ -/*! @{ */ - -#define ADC_TSTAT_TEXC_NUM_MASK (0xFU) -#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) -/*! TEXC_NUM - Trigger Exception Number - * 0b0000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. - * 0b0001..Trigger 0 has been interrupted by a high priority exception. - * 0b0010..Trigger 1 has been interrupted by a high priority exception. - * 0b0011-0b1110..Associated trigger sequence has interrupted by a high priority exception. - * 0b1111..Every trigger sequence has been interrupted by a high priority exception. - */ -#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) - -#define ADC_TSTAT_TCOMP_FLAG_MASK (0xF0000U) -#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) -/*! TCOMP_FLAG - Trigger Completion Flag - * 0b0000..No triggers have been completed. Trigger completion interrupts are disabled. - * 0b0001..Trigger 0 has been completed and triger 0 has enabled completion interrupts. - * 0b0010..Trigger 1 has been completed and triger 1 has enabled completion interrupts. - * 0b0011-0b1110..Associated trigger sequence has completed and has enabled completion interrupts. - * 0b1111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. - */ -#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) -/*! @} */ - -/*! @name OFSTRIM - ADC Offset Trim Register */ -/*! @{ */ - -#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) -#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) -/*! OFSTRIM_A - Trim for offset - */ -#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) - -#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) -#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) -/*! OFSTRIM_B - Trim for offset - */ -#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) -/*! @} */ - -/*! @name TCTRL - Trigger Control Register */ -/*! @{ */ - -#define ADC_TCTRL_HTEN_MASK (0x1U) -#define ADC_TCTRL_HTEN_SHIFT (0U) -/*! HTEN - Trigger enable - * 0b0..Hardware trigger source disabled - * 0b1..Hardware trigger source enabled - */ -#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) - -#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) -#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) -/*! FIFO_SEL_A - SAR Result Destination For Channel A - * 0b0..Result written to FIFO 0 - * 0b1..Result written to FIFO 1 - */ -#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) - -#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) -#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) -/*! FIFO_SEL_B - SAR Result Destination For Channel B - * 0b0..Result written to FIFO 0 - * 0b1..Result written to FIFO 1 - */ -#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) - -#define ADC_TCTRL_TPRI_MASK (0x300U) -#define ADC_TCTRL_TPRI_SHIFT (8U) -/*! TPRI - Trigger priority setting - * 0b00..Set to highest priority, Level 1 - * 0b01-0b10..Set to corresponding priority level - * 0b11..Set to lowest priority, Level 4 - */ -#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) - -#define ADC_TCTRL_RSYNC_MASK (0x8000U) -#define ADC_TCTRL_RSYNC_SHIFT (15U) -/*! RSYNC - Trigger Resync - */ -#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) - -#define ADC_TCTRL_TDLY_MASK (0xF0000U) -#define ADC_TCTRL_TDLY_SHIFT (16U) -/*! TDLY - Trigger delay select - */ -#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) - -#define ADC_TCTRL_TCMD_MASK (0xF000000U) -#define ADC_TCTRL_TCMD_SHIFT (24U) -/*! TCMD - Trigger command select - * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. - * 0b0001..CMD1 is executed - * 0b0010-0b1110..Corresponding CMD is executed - * 0b1111..CMD15 is executed - */ -#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) -/*! @} */ - -/* The count of ADC_TCTRL */ -#define ADC_TCTRL_COUNT (4U) - -/*! @name FCTRL - FIFO Control Register */ -/*! @{ */ - -#define ADC_FCTRL_FCOUNT_MASK (0x1FU) -#define ADC_FCTRL_FCOUNT_SHIFT (0U) -/*! FCOUNT - Result FIFO counter - */ -#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) - -#define ADC_FCTRL_FWMARK_MASK (0xF0000U) -#define ADC_FCTRL_FWMARK_SHIFT (16U) -/*! FWMARK - Watermark level selection - */ -#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) -/*! @} */ - -/* The count of ADC_FCTRL */ -#define ADC_FCTRL_COUNT (2U) - -/*! @name GCC - Gain Calibration Control */ -/*! @{ */ - -#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) -#define ADC_GCC_GAIN_CAL_SHIFT (0U) -/*! GAIN_CAL - Gain Calibration Value - */ -#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) - -#define ADC_GCC_RDY_MASK (0x1000000U) -#define ADC_GCC_RDY_SHIFT (24U) -/*! RDY - Gain Calibration Value Valid - * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. - * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. - */ -#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) -/*! @} */ - -/* The count of ADC_GCC */ -#define ADC_GCC_COUNT (2U) - -/*! @name GCR - Gain Calculation Result */ -/*! @{ */ - -#define ADC_GCR_GCALR_MASK (0xFFFFU) -#define ADC_GCR_GCALR_SHIFT (0U) -/*! GCALR - Gain Calculation Result - */ -#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) - -#define ADC_GCR_RDY_MASK (0x1000000U) -#define ADC_GCR_RDY_SHIFT (24U) -/*! RDY - Gain Calculation Ready - * 0b0..The gain offset calculation value is invalid. - * 0b1..The gain calibration value is valid. - */ -#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) -/*! @} */ - -/* The count of ADC_GCR */ -#define ADC_GCR_COUNT (2U) - -/*! @name CMDL - ADC Command Low Buffer Register */ -/*! @{ */ - -#define ADC_CMDL_ADCH_MASK (0x1FU) -#define ADC_CMDL_ADCH_SHIFT (0U) -/*! ADCH - Input channel select - * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. - * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. - * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. - * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. - * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. - * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. - */ -#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) - -#define ADC_CMDL_CTYPE_MASK (0x60U) -#define ADC_CMDL_CTYPE_SHIFT (5U) -/*! CTYPE - Conversion Type - * 0b00..Single-Ended Mode. Only A side channel is converted. - * 0b01..Single-Ended Mode. Only B side channel is converted. - * 0b10..Differential Mode. A-B. - * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - */ -#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) - -#define ADC_CMDL_MODE_MASK (0x80U) -#define ADC_CMDL_MODE_SHIFT (7U) -/*! MODE - Select resolution of conversions - * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - */ -#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) - -#define ADC_CMDL_ALTB_ADCH_MASK (0x1F0000U) -#define ADC_CMDL_ALTB_ADCH_SHIFT (16U) -/*! ALTB_ADCH - Alternate Channel B Input channel select - * 0b00000..Select CH0B - * 0b00001..Select CH1B - * 0b00010..Select CH2B - * 0b00011..Select CH3B - * 0b00100-0b11101..Select corresponding channel CHnB - * 0b11110..Select CH30B - * 0b11111..Select CH31B - */ -#define ADC_CMDL_ALTB_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ALTB_ADCH_SHIFT)) & ADC_CMDL_ALTB_ADCH_MASK) - -#define ADC_CMDL_ALTBEN_MASK (0x200000U) -#define ADC_CMDL_ALTBEN_SHIFT (21U) -/*! ALTBEN - Alternate Channel B Select Enable - * 0b0..ALTBEN_ADCH disabled. Channel A and Channel B inputs are selected based on ADCH settings. - * 0b1..ALTBEN_ADCH enabled. Channel A inputs selected by ADCH setting and Channel B inputs selected by ALTB_ADCH setting. - */ -#define ADC_CMDL_ALTBEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ALTBEN_SHIFT)) & ADC_CMDL_ALTBEN_MASK) -/*! @} */ - -/* The count of ADC_CMDL */ -#define ADC_CMDL_COUNT (15U) - -/*! @name CMDH - ADC Command High Buffer Register */ -/*! @{ */ - -#define ADC_CMDH_CMPEN_MASK (0x3U) -#define ADC_CMDH_CMPEN_SHIFT (0U) -/*! CMPEN - Compare Function Enable - * 0b00..Compare disabled. - * 0b01..Reserved - * 0b10..Compare enabled. Store on true. - * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - */ -#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) - -#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) -#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) -/*! WAIT_TRIG - Wait for trigger assertion before execution. - * 0b0..This command will be automatically executed. - * 0b1..The active trigger must be asserted again before executing this command. - */ -#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) - -#define ADC_CMDH_LWI_MASK (0x80U) -#define ADC_CMDH_LWI_SHIFT (7U) -/*! LWI - Loop with Increment - * 0b0..Auto channel increment disabled - * 0b1..Auto channel increment enabled - */ -#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) - -#define ADC_CMDH_STS_MASK (0x700U) -#define ADC_CMDH_STS_SHIFT (8U) -/*! STS - Sample Time Select - * 0b000..Minimum sample time of 3.5 ADCK cycles. - * 0b001..3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time. - * 0b010..3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time. - * 0b011..3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time. - * 0b100..3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time. - * 0b101..3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time. - * 0b110..3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time. - * 0b111..3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time. - */ -#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) - -#define ADC_CMDH_AVGS_MASK (0x7000U) -#define ADC_CMDH_AVGS_SHIFT (12U) -/*! AVGS - Hardware Average Select - * 0b000..Single conversion. - * 0b001..2 conversions averaged. - * 0b010..4 conversions averaged. - * 0b011..8 conversions averaged. - * 0b100..16 conversions averaged. - * 0b101..32 conversions averaged. - * 0b110..64 conversions averaged. - * 0b111..128 conversions averaged. - */ -#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) - -#define ADC_CMDH_LOOP_MASK (0xF0000U) -#define ADC_CMDH_LOOP_SHIFT (16U) -/*! LOOP - Loop Count Select - * 0b0000..Looping not enabled. Command executes 1 time. - * 0b0001..Loop 1 time. Command executes 2 times. - * 0b0010..Loop 2 times. Command executes 3 times. - * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. - * 0b1111..Loop 15 times. Command executes 16 times. - */ -#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) - -#define ADC_CMDH_NEXT_MASK (0xF000000U) -#define ADC_CMDH_NEXT_SHIFT (24U) -/*! NEXT - Next Command Select - * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority - * trigger pending, begin command associated with lower priority trigger. - * 0b0001..Select CMD1 command buffer register as next command. - * 0b0010-0b1110..Select corresponding CMD command buffer register as next command - * 0b1111..Select CMD15 command buffer register as next command. - */ -#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) -/*! @} */ - -/* The count of ADC_CMDH */ -#define ADC_CMDH_COUNT (15U) - -/*! @name CV - Compare Value Register */ -/*! @{ */ - -#define ADC_CV_CVL_MASK (0xFFFFU) -#define ADC_CV_CVL_SHIFT (0U) -/*! CVL - Compare Value Low. - */ -#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) - -#define ADC_CV_CVH_MASK (0xFFFF0000U) -#define ADC_CV_CVH_SHIFT (16U) -/*! CVH - Compare Value High. - */ -#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) -/*! @} */ - -/* The count of ADC_CV */ -#define ADC_CV_COUNT (15U) - -/*! @name RESFIFO - ADC Data Result FIFO Register */ -/*! @{ */ - -#define ADC_RESFIFO_D_MASK (0xFFFFU) -#define ADC_RESFIFO_D_SHIFT (0U) -/*! D - Data result - */ -#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) - -#define ADC_RESFIFO_TSRC_MASK (0x30000U) -#define ADC_RESFIFO_TSRC_SHIFT (16U) -/*! TSRC - Trigger Source - * 0b00..Trigger source 0 initiated this conversion. - * 0b01..Trigger source 1 initiated this conversion. - * 0b10-0b10..Corresponding trigger source initiated this conversion. - * 0b11..Trigger source 3 initiated this conversion. - */ -#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) - -#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) -#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) -/*! LOOPCNT - Loop count value - * 0b0000..Result is from initial conversion in command. - * 0b0001..Result is from second conversion in command. - * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. - * 0b1111..Result is from 16th conversion in command. - */ -#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) - -#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) -#define ADC_RESFIFO_CMDSRC_SHIFT (24U) -/*! CMDSRC - Command Buffer Source - * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state - * prior to an ADC conversion result dataword being stored to a RESFIFO buffer. - * 0b0001..CMD1 buffer used as control settings for this conversion. - * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. - * 0b1111..CMD15 buffer used as control settings for this conversion. - */ -#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) - -#define ADC_RESFIFO_VALID_MASK (0x80000000U) -#define ADC_RESFIFO_VALID_SHIFT (31U) -/*! VALID - FIFO entry is valid - * 0b0..FIFO is empty. Discard any read from RESFIFO. - * 0b1..FIFO record read from RESFIFO is valid. - */ -#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) -/*! @} */ - -/* The count of ADC_RESFIFO */ -#define ADC_RESFIFO_COUNT (2U) - -/*! @name CAL_GAR - Calibration General A-Side Registers */ -/*! @{ */ - -#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) -#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) -/*! CAL_GAR_VAL - Calibration General A Side Register Element - */ -#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) -/*! @} */ - -/* The count of ADC_CAL_GAR */ -#define ADC_CAL_GAR_COUNT (33U) - -/*! @name CAL_GBR - Calibration General B-Side Registers */ -/*! @{ */ - -#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) -#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) -/*! CAL_GBR_VAL - Calibration General B Side Register Element - */ -#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) -/*! @} */ - -/* The count of ADC_CAL_GBR */ -#define ADC_CAL_GBR_COUNT (33U) - - -/*! - * @} - */ /* end of group ADC_Register_Masks */ - - -/* ADC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral ADC0 base address */ - #define ADC0_BASE (0x500A0000u) - /** Peripheral ADC0 base address */ - #define ADC0_BASE_NS (0x400A0000u) - /** Peripheral ADC0 base pointer */ - #define ADC0 ((ADC_Type *)ADC0_BASE) - /** Peripheral ADC0 base pointer */ - #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) - /** Peripheral ADC1 base address */ - #define ADC1_BASE (0x500B1000u) - /** Peripheral ADC1 base address */ - #define ADC1_BASE_NS (0x400B1000u) - /** Peripheral ADC1 base pointer */ - #define ADC1 ((ADC_Type *)ADC1_BASE) - /** Peripheral ADC1 base pointer */ - #define ADC1_NS ((ADC_Type *)ADC1_BASE_NS) - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS { ADC0, ADC1 } - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS, ADC1_BASE_NS } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS_NS { ADC0_NS, ADC1_NS } -#else - /** Peripheral ADC0 base address */ - #define ADC0_BASE (0x400A0000u) - /** Peripheral ADC0 base pointer */ - #define ADC0 ((ADC_Type *)ADC0_BASE) - /** Peripheral ADC1 base address */ - #define ADC1_BASE (0x400B1000u) - /** Peripheral ADC1 base pointer */ - #define ADC1 ((ADC_Type *)ADC1_BASE) - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS { ADC0, ADC1 } -#endif -/** Interrupt vectors for the ADC peripheral type */ -#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } - -/*! - * @} - */ /* end of group ADC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ANACTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer - * @{ - */ - -/** ANACTRL - Register Layout Typedef */ -typedef struct { - __IO uint32_t ANALOG_CTRL_CFG; /**< Various Analog blocks configuration (like FRO 192MHz trimmings source ...), offset: 0x0 */ - __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Control and Status, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running Oscillator (FRO) Control, offset: 0x10 */ - __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running Oscillator (FRO) Status, offset: 0x14 */ - __IO uint32_t ADC_CTRL; /**< General Purpose ADC VBAT Divider branch control, offset: 0x18 */ - uint8_t RESERVED_1[4]; - __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */ - __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status, offset: 0x24 */ - uint8_t RESERVED_2[8]; - __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors & DCDC interrupt control, offset: 0x30 */ - __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupt status, offset: 0x34 */ - uint8_t RESERVED_3[120]; - __IO uint32_t LDO_XO32M; /**< High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register, offset: 0xB0 */ - uint8_t RESERVED_4[60]; - __IO uint32_t OSC_TESTBUS; /**< Oscillators Analog Macrobloc ACBUS and DCBUS control, offset: 0xF0 */ - uint8_t RESERVED_5[4]; - __IO uint32_t DUMMY_CTRL; /**< Dummy Control bus to analog modules, offset: 0xF8 */ -} ANACTRL_Type; - -/* ---------------------------------------------------------------------------- - -- ANACTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks - * @{ - */ - -/*! @name ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) */ -/*! @{ */ - -#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK (0x1U) -#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT (0U) -/*! FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source. - * 0b0..FRO192M trimming and 'Enable' comes from eFUSE. - * 0b1..FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers. - */ -#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT)) & ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK) -/*! @} */ - -/*! @name ANALOG_CTRL_STATUS - Analog Control and Status */ -/*! @{ */ - -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U) -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U) -/*! FLASH_PWRDWN - Flash Power Down status - * 0b0..Not in power down mode. - * 0b1..In power down mode. - */ -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK) - -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U) -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U) -/*! FLASH_INIT_ERROR - Flash initialization error status - * 0b0..No error - * 0b1..At least one error occurred - */ -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK) - -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_ECC_ERROR_FLAG_MASK (0x10000U) -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_ECC_ERROR_FLAG_SHIFT (16U) -/*! FLASH_ECC_ERROR_FLAG - Flash ECC Error Flag - */ -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_ECC_ERROR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_ECC_ERROR_FLAG_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_ECC_ERROR_FLAG_MASK) -/*! @} */ - -/*! @name FRO192M_CTRL - 192MHz Free Running Oscillator (FRO) Control */ -/*! @{ */ - -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U) -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U) -/*! ENA_12MHZCLK - 12 MHz clock control. - * 0b0..Disable the 12 MHz clock. - * 0b1..Enable the 12 MHz clock. - */ -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) - -#define ANACTRL_FRO192M_CTRL_FREQ_TRIM_MASK (0xFF0000U) -#define ANACTRL_FRO192M_CTRL_FREQ_TRIM_SHIFT (16U) -/*! FREQ_TRIM - Frequency trim. - */ -#define ANACTRL_FRO192M_CTRL_FREQ_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_FREQ_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_FREQ_TRIM_MASK) - -#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U) -#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U) -/*! USBCLKADJ - If USBCLKADJ bit is set and the USB peripheral is enabled for full speed device - * mode, the USB block will provide FRO clock adjustments to synchronize the frequency to the host - * clock using the SOF packets. - */ -#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK) - -#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U) -#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U) -/*! USBMODCHG - USBCLKADJ mode trim change - */ -#define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK) - -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U) -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U) -/*! ENA_96MHZCLK - 96 MHz clock control - * 0b0..Disable the 96 MHz clock. - * 0b1..Enable the 96 MHz clock. - */ -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) - -#define ANACTRL_FRO192M_CTRL_WRTRIM_MASK (0x80000000U) -#define ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT (31U) -/*! WRTRIM - This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields. - */ -#define ANACTRL_FRO192M_CTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_WRTRIM_MASK) -/*! @} */ - -/*! @name FRO192M_STATUS - 192MHz Free Running Oscillator (FRO) Status */ -/*! @{ */ - -#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U) -#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U) -/*! CLK_VALID - Output clock valid. - * 0b0..No output clock available - * 0b1..Output clock is available - */ -#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK) - -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U) -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U) -/*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). - */ -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK) -/*! @} */ - -/*! @name ADC_CTRL - General Purpose ADC VBAT Divider branch control */ -/*! @{ */ - -#define ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK (0x1U) -#define ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT (0U) -/*! VBATDIVENABLE - Switch On/Off VBAT divider branch. - * 0b0..VBAT divider branch is disabled. - * 0b1..VBAT divider branch is enabled. - */ -#define ANACTRL_ADC_CTRL_VBATDIVENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT)) & ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK) -/*! @} */ - -/*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */ -/*! @{ */ - -#define ANACTRL_XO32M_CTRL_SLAVE_MASK (0x10U) -#define ANACTRL_XO32M_CTRL_SLAVE_SHIFT (4U) -/*! SLAVE - XO in slave mode. - */ -#define ANACTRL_XO32M_CTRL_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_SLAVE_SHIFT)) & ANACTRL_XO32M_CTRL_SLAVE_MASK) - -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK (0x7F00U) -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT (8U) -/*! OSC_CAP_IN - Tune capa banks of High speed Crystal Oscillator input pin - */ -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK) - -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK (0x3F8000U) -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT (15U) -/*! OSC_CAP_OUT - Tune capa banks of High speed Crystal Oscillator output pin - */ -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK) - -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U) -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U) -/*! ACBUF_PASS_ENABLE - Allows XO32M to be configured in bypass mode. - * 0b0..XO bypass is disabled. - * 0b1..XO bypass is enabled. - */ -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK) - -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U) -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U) -/*! ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system. - * 0b0..Disable the oscillator. - * 0b1..Enable the oscillator. - */ -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) -/*! @} */ - -/*! @name XO32M_STATUS - High speed Crystal Oscillator Status */ -/*! @{ */ - -#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U) -#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U) -/*! XO_READY - Crystal Oscillator Ready - * 0b0..Frequency is not yet stable. - * 0b1..Frequency is stable. - */ -#define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK) -/*! @} */ - -/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors & DCDC interrupt control */ -/*! @{ */ - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_MASK (0x1U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_SHIFT (0U) -/*! BODVDDMAIN_INT_ENABLE - BOD VDDMAIN interrupt control. - * 0b0..Disable the interrupt. - * 0b1..Enable the interrupt. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_CLEAR_MASK (0x2U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_CLEAR_SHIFT (1U) -/*! BODVDDMAIN_INT_CLEAR - BOD VDDMAIN interrupt clear.1: Clear the interrupt. Self-cleared bit. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_CLEAR_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U) -/*! BODCORE_INT_ENABLE - BOD CORE interrupt control. - * 0b0..Disable the interrupt. - * 0b1..Enable the interrupt. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U) -/*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U) -/*! DCDC_INT_ENABLE - DCDC interrupt control. - * 0b0..Disable the interrupt. - * 0b1..Enable the interrupt. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U) -/*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK) -/*! @} */ - -/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupt status */ -/*! @{ */ - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_MASK (0x1U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_SHIFT (0U) -/*! BODVDDMAIN_STATUS - BOD VDDMAIN Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending. - * 0b1..Interrupt pending. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_MASK (0x2U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_SHIFT (1U) -/*! BODVDDMAIN_INT_STATUS - BOD VDDMAIN Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending. - * 0b1..Interrupt pending. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_MASK (0x4U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_SHIFT (2U) -/*! BODVDDMAIN_VAL - BOD VDDMAIN power status - * 0b0..Below the threshold. - * 0b1..Above the threshold. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U) -/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending. - * 0b1..Interrupt pending. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U) -/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending. - * 0b1..Interrupt pending. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U) -/*! BODCORE_VAL - BOD CORE power status - * 0b0..Below the threshold. - * 0b1..Above the threshold. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U) -/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending. - * 0b1..Interrupt pending. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U) -/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending. - * 0b1..Interrupt pending. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U) -/*! DCDC_VAL - DCDC power status - * 0b0..Below the target. - * 0b1..Above the target. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK) -/*! @} */ - -/*! @name LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register */ -/*! @{ */ - -#define ANACTRL_LDO_XO32M_BYPASS_MASK (0x2U) -#define ANACTRL_LDO_XO32M_BYPASS_SHIFT (1U) -/*! BYPASS - Activate LDO bypass. - * 0b0..Disable bypass mode (for normal operations). - * 0b1..Activate LDO bypass. - */ -#define ANACTRL_LDO_XO32M_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_BYPASS_SHIFT)) & ANACTRL_LDO_XO32M_BYPASS_MASK) - -#define ANACTRL_LDO_XO32M_HIGHZ_MASK (0x4U) -#define ANACTRL_LDO_XO32M_HIGHZ_SHIFT (2U) -/*! HIGHZ - . - * 0b0..Output in High normal state. - * 0b1..Output in High Impedance state. - */ -#define ANACTRL_LDO_XO32M_HIGHZ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_HIGHZ_SHIFT)) & ANACTRL_LDO_XO32M_HIGHZ_MASK) - -#define ANACTRL_LDO_XO32M_VOUT_MASK (0x38U) -#define ANACTRL_LDO_XO32M_VOUT_SHIFT (3U) -/*! VOUT - Sets the LDO output level. - * 0b000..0.750 V. - * 0b001..0.775 V. - * 0b010..0.800 V. - * 0b011..0.825 V. - * 0b100..0.850 V. - * 0b101..0.875 V. - * 0b110..0.900 V. - * 0b111..0.925 V. - */ -#define ANACTRL_LDO_XO32M_VOUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_VOUT_SHIFT)) & ANACTRL_LDO_XO32M_VOUT_MASK) - -#define ANACTRL_LDO_XO32M_IBIAS_MASK (0xC0U) -#define ANACTRL_LDO_XO32M_IBIAS_SHIFT (6U) -/*! IBIAS - Adjust the biasing current. - */ -#define ANACTRL_LDO_XO32M_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_IBIAS_SHIFT)) & ANACTRL_LDO_XO32M_IBIAS_MASK) - -#define ANACTRL_LDO_XO32M_STABMODE_MASK (0x300U) -#define ANACTRL_LDO_XO32M_STABMODE_SHIFT (8U) -/*! STABMODE - Stability configuration. - */ -#define ANACTRL_LDO_XO32M_STABMODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_STABMODE_SHIFT)) & ANACTRL_LDO_XO32M_STABMODE_MASK) -/*! @} */ - -/*! @name OSC_TESTBUS - Oscillators Analog Macrobloc ACBUS and DCBUS control */ -/*! @{ */ - -#define ANACTRL_OSC_TESTBUS_ACBUS_MASK (0x3FU) -#define ANACTRL_OSC_TESTBUS_ACBUS_SHIFT (0U) -/*! ACBUS - Alternate current BUS - */ -#define ANACTRL_OSC_TESTBUS_ACBUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_OSC_TESTBUS_ACBUS_SHIFT)) & ANACTRL_OSC_TESTBUS_ACBUS_MASK) - -#define ANACTRL_OSC_TESTBUS_DCBUS_MASK (0x3F0000U) -#define ANACTRL_OSC_TESTBUS_DCBUS_SHIFT (16U) -/*! DCBUS - Direct current BUS - */ -#define ANACTRL_OSC_TESTBUS_DCBUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_OSC_TESTBUS_DCBUS_SHIFT)) & ANACTRL_OSC_TESTBUS_DCBUS_MASK) -/*! @} */ - -/*! @name DUMMY_CTRL - Dummy Control bus to analog modules */ -/*! @{ */ - -#define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK (0xC00U) -#define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_SHIFT (10U) -/*! XO32M_ADC_CLK_MODE - Control High speed Crystal oscillator mode of the ADC clock. - * 0b00..High speed Crystal oscillator output to ADC is disabled. - * 0b01..High speed Crystal oscillator output to ADC is enable. - */ -#define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_SHIFT)) & ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ANACTRL_Register_Masks */ - - -/* ANACTRL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE (0x50013000u) - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE_NS (0x40013000u) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS) - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS { ANACTRL } - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS } -#else - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE (0x40013000u) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS { ANACTRL } -#endif - -/*! - * @} - */ /* end of group ANACTRL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- AOI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer - * @{ - */ - -/** AOI - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x4 */ - __IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */ - __IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */ - } BFCRT[4]; -} AOI_Type; - -/* ---------------------------------------------------------------------------- - -- AOI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AOI_Register_Masks AOI Register Masks - * @{ - */ - -/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */ -/*! @{ */ - -#define AOI_BFCRT01_PT1_DC_MASK (0x3U) -#define AOI_BFCRT01_PT1_DC_SHIFT (0U) -/*! PT1_DC - Product term 1, D input configuration - * 0b00..Force the D input in this product term to a logical zero - * 0b01..Pass the D input in this product term - * 0b10..Complement the D input in this product term - * 0b11..Force the D input in this product term to a logical one - */ -#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK) - -#define AOI_BFCRT01_PT1_CC_MASK (0xCU) -#define AOI_BFCRT01_PT1_CC_SHIFT (2U) -/*! PT1_CC - Product term 1, C input configuration - * 0b00..Force the C input in this product term to a logical zero - * 0b01..Pass the C input in this product term - * 0b10..Complement the C input in this product term - * 0b11..Force the C input in this product term to a logical one - */ -#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK) - -#define AOI_BFCRT01_PT1_BC_MASK (0x30U) -#define AOI_BFCRT01_PT1_BC_SHIFT (4U) -/*! PT1_BC - Product term 1, B input configuration - * 0b00..Force the B input in this product term to a logical zero - * 0b01..Pass the B input in this product term - * 0b10..Complement the B input in this product term - * 0b11..Force the B input in this product term to a logical one - */ -#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK) - -#define AOI_BFCRT01_PT1_AC_MASK (0xC0U) -#define AOI_BFCRT01_PT1_AC_SHIFT (6U) -/*! PT1_AC - Product term 1, A input configuration - * 0b00..Force the A input in this product term to a logical zero - * 0b01..Pass the A input in this product term - * 0b10..Complement the A input in this product term - * 0b11..Force the A input in this product term to a logical one - */ -#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK) - -#define AOI_BFCRT01_PT0_DC_MASK (0x300U) -#define AOI_BFCRT01_PT0_DC_SHIFT (8U) -/*! PT0_DC - Product term 0, D input configuration - * 0b00..Force the D input in this product term to a logical zero - * 0b01..Pass the D input in this product term - * 0b10..Complement the D input in this product term - * 0b11..Force the D input in this product term to a logical one - */ -#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK) - -#define AOI_BFCRT01_PT0_CC_MASK (0xC00U) -#define AOI_BFCRT01_PT0_CC_SHIFT (10U) -/*! PT0_CC - Product term 0, C input configuration - * 0b00..Force the C input in this product term to a logical zero - * 0b01..Pass the C input in this product term - * 0b10..Complement the C input in this product term - * 0b11..Force the C input in this product term to a logical one - */ -#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK) - -#define AOI_BFCRT01_PT0_BC_MASK (0x3000U) -#define AOI_BFCRT01_PT0_BC_SHIFT (12U) -/*! PT0_BC - Product term 0, B input configuration - * 0b00..Force the B input in this product term to a logical zero - * 0b01..Pass the B input in this product term - * 0b10..Complement the B input in this product term - * 0b11..Force the B input in this product term to a logical one - */ -#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK) - -#define AOI_BFCRT01_PT0_AC_MASK (0xC000U) -#define AOI_BFCRT01_PT0_AC_SHIFT (14U) -/*! PT0_AC - Product term 0, A input configuration - * 0b00..Force the A input in this product term to a logical zero - * 0b01..Pass the A input in this product term - * 0b10..Complement the A input in this product term - * 0b11..Force the A input in this product term to a logical one - */ -#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK) -/*! @} */ - -/* The count of AOI_BFCRT01 */ -#define AOI_BFCRT01_COUNT (4U) - -/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */ -/*! @{ */ - -#define AOI_BFCRT23_PT3_DC_MASK (0x3U) -#define AOI_BFCRT23_PT3_DC_SHIFT (0U) -/*! PT3_DC - Product term 3, D input configuration - * 0b00..Force the D input in this product term to a logical zero - * 0b01..Pass the D input in this product term - * 0b10..Complement the D input in this product term - * 0b11..Force the D input in this product term to a logical one - */ -#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK) - -#define AOI_BFCRT23_PT3_CC_MASK (0xCU) -#define AOI_BFCRT23_PT3_CC_SHIFT (2U) -/*! PT3_CC - Product term 3, C input configuration - * 0b00..Force the C input in this product term to a logical zero - * 0b01..Pass the C input in this product term - * 0b10..Complement the C input in this product term - * 0b11..Force the C input in this product term to a logical one - */ -#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK) - -#define AOI_BFCRT23_PT3_BC_MASK (0x30U) -#define AOI_BFCRT23_PT3_BC_SHIFT (4U) -/*! PT3_BC - Product term 3, B input configuration - * 0b00..Force the B input in this product term to a logical zero - * 0b01..Pass the B input in this product term - * 0b10..Complement the B input in this product term - * 0b11..Force the B input in this product term to a logical one - */ -#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK) - -#define AOI_BFCRT23_PT3_AC_MASK (0xC0U) -#define AOI_BFCRT23_PT3_AC_SHIFT (6U) -/*! PT3_AC - Product term 3, A input configuration - * 0b00..Force the A input in this product term to a logical zero - * 0b01..Pass the A input in this product term - * 0b10..Complement the A input in this product term - * 0b11..Force the A input in this product term to a logical one - */ -#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK) - -#define AOI_BFCRT23_PT2_DC_MASK (0x300U) -#define AOI_BFCRT23_PT2_DC_SHIFT (8U) -/*! PT2_DC - Product term 2, D input configuration - * 0b00..Force the D input in this product term to a logical zero - * 0b01..Pass the D input in this product term - * 0b10..Complement the D input in this product term - * 0b11..Force the D input in this product term to a logical one - */ -#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK) - -#define AOI_BFCRT23_PT2_CC_MASK (0xC00U) -#define AOI_BFCRT23_PT2_CC_SHIFT (10U) -/*! PT2_CC - Product term 2, C input configuration - * 0b00..Force the C input in this product term to a logical zero - * 0b01..Pass the C input in this product term - * 0b10..Complement the C input in this product term - * 0b11..Force the C input in this product term to a logical one - */ -#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK) - -#define AOI_BFCRT23_PT2_BC_MASK (0x3000U) -#define AOI_BFCRT23_PT2_BC_SHIFT (12U) -/*! PT2_BC - Product term 2, B input configuration - * 0b00..Force the B input in this product term to a logical zero - * 0b01..Pass the B input in this product term - * 0b10..Complement the B input in this product term - * 0b11..Force the B input in this product term to a logical one - */ -#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK) - -#define AOI_BFCRT23_PT2_AC_MASK (0xC000U) -#define AOI_BFCRT23_PT2_AC_SHIFT (14U) -/*! PT2_AC - Product term 2, A input configuration - * 0b00..Force the A input in this product term to a logical zero - * 0b01..Pass the A input in this product term - * 0b10..Complement the A input in this product term - * 0b11..Force the A input in this product term to a logical one - */ -#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK) -/*! @} */ - -/* The count of AOI_BFCRT23 */ -#define AOI_BFCRT23_COUNT (4U) - - -/*! - * @} - */ /* end of group AOI_Register_Masks */ - - -/* AOI - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral AOI0 base address */ - #define AOI0_BASE (0x500C7000u) - /** Peripheral AOI0 base address */ - #define AOI0_BASE_NS (0x400C7000u) - /** Peripheral AOI0 base pointer */ - #define AOI0 ((AOI_Type *)AOI0_BASE) - /** Peripheral AOI0 base pointer */ - #define AOI0_NS ((AOI_Type *)AOI0_BASE_NS) - /** Peripheral AOI1 base address */ - #define AOI1_BASE (0x500C8000u) - /** Peripheral AOI1 base address */ - #define AOI1_BASE_NS (0x400C8000u) - /** Peripheral AOI1 base pointer */ - #define AOI1 ((AOI_Type *)AOI1_BASE) - /** Peripheral AOI1 base pointer */ - #define AOI1_NS ((AOI_Type *)AOI1_BASE_NS) - /** Array initializer of AOI peripheral base addresses */ - #define AOI_BASE_ADDRS { AOI0_BASE, AOI1_BASE } - /** Array initializer of AOI peripheral base pointers */ - #define AOI_BASE_PTRS { AOI0, AOI1 } - /** Array initializer of AOI peripheral base addresses */ - #define AOI_BASE_ADDRS_NS { AOI0_BASE_NS, AOI1_BASE_NS } - /** Array initializer of AOI peripheral base pointers */ - #define AOI_BASE_PTRS_NS { AOI0_NS, AOI1_NS } -#else - /** Peripheral AOI0 base address */ - #define AOI0_BASE (0x400C7000u) - /** Peripheral AOI0 base pointer */ - #define AOI0 ((AOI_Type *)AOI0_BASE) - /** Peripheral AOI1 base address */ - #define AOI1_BASE (0x400C8000u) - /** Peripheral AOI1 base pointer */ - #define AOI1 ((AOI_Type *)AOI1_BASE) - /** Array initializer of AOI peripheral base addresses */ - #define AOI_BASE_ADDRS { AOI0_BASE, AOI1_BASE } - /** Array initializer of AOI peripheral base pointers */ - #define AOI_BASE_PTRS { AOI0, AOI1 } -#endif - -/*! - * @} - */ /* end of group AOI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CACHE64_CTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CACHE64_CTRL_Peripheral_Access_Layer CACHE64_CTRL Peripheral Access Layer - * @{ - */ - -/** CACHE64_CTRL - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[2048]; - __IO uint32_t CCR; /**< Cache control register, offset: 0x800 */ - __IO uint32_t CLCR; /**< Cache line control register, offset: 0x804 */ - __IO uint32_t CSAR; /**< Cache search address register, offset: 0x808 */ - __IO uint32_t CCVR; /**< Cache read/write value register, offset: 0x80C */ -} CACHE64_CTRL_Type; - -/* ---------------------------------------------------------------------------- - -- CACHE64_CTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CACHE64_CTRL_Register_Masks CACHE64_CTRL Register Masks - * @{ - */ - -/*! @name CCR - Cache control register */ -/*! @{ */ - -#define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) -#define CACHE64_CTRL_CCR_ENCACHE_SHIFT (0U) -/*! ENCACHE - Cache enable - * 0b0..Cache disabled - * 0b1..Cache enabled - */ -#define CACHE64_CTRL_CCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_ENCACHE_SHIFT)) & CACHE64_CTRL_CCR_ENCACHE_MASK) - -#define CACHE64_CTRL_CCR_ENWRBUF_MASK (0x2U) -#define CACHE64_CTRL_CCR_ENWRBUF_SHIFT (1U) -/*! ENWRBUF - Enable Write Buffer - * 0b0..Write buffer disabled - * 0b1..Write buffer enabled - */ -#define CACHE64_CTRL_CCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_ENWRBUF_SHIFT)) & CACHE64_CTRL_CCR_ENWRBUF_MASK) - -#define CACHE64_CTRL_CCR_INVW0_MASK (0x1000000U) -#define CACHE64_CTRL_CCR_INVW0_SHIFT (24U) -/*! INVW0 - Invalidate Way 0 - * 0b0..No operation - * 0b1..When setting the GO bit, invalidate all lines in way 0. - */ -#define CACHE64_CTRL_CCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW0_SHIFT)) & CACHE64_CTRL_CCR_INVW0_MASK) - -#define CACHE64_CTRL_CCR_PUSHW0_MASK (0x2000000U) -#define CACHE64_CTRL_CCR_PUSHW0_SHIFT (25U) -/*! PUSHW0 - Push Way 0 - * 0b0..No operation - * 0b1..When setting the GO bit, push all modified lines in way 0 - */ -#define CACHE64_CTRL_CCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_PUSHW0_SHIFT)) & CACHE64_CTRL_CCR_PUSHW0_MASK) - -#define CACHE64_CTRL_CCR_INVW1_MASK (0x4000000U) -#define CACHE64_CTRL_CCR_INVW1_SHIFT (26U) -/*! INVW1 - Invalidate Way 1 - * 0b0..No operation - * 0b1..When setting the GO bit, invalidate all lines in way 1 - */ -#define CACHE64_CTRL_CCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW1_SHIFT)) & CACHE64_CTRL_CCR_INVW1_MASK) - -#define CACHE64_CTRL_CCR_PUSHW1_MASK (0x8000000U) -#define CACHE64_CTRL_CCR_PUSHW1_SHIFT (27U) -/*! PUSHW1 - Push Way 1 - * 0b0..No operation - * 0b1..When setting the GO bit, push all modified lines in way 1 - */ -#define CACHE64_CTRL_CCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_PUSHW1_SHIFT)) & CACHE64_CTRL_CCR_PUSHW1_MASK) - -#define CACHE64_CTRL_CCR_GO_MASK (0x80000000U) -#define CACHE64_CTRL_CCR_GO_SHIFT (31U) -/*! GO - Initiate Cache Command - * 0b0..Write: no effect. Read: no cache command active. - * 0b1..Write: initiate command indicated by bits 27-24. Read: cache command active. - */ -#define CACHE64_CTRL_CCR_GO(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_GO_SHIFT)) & CACHE64_CTRL_CCR_GO_MASK) -/*! @} */ - -/*! @name CLCR - Cache line control register */ -/*! @{ */ - -#define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) -#define CACHE64_CTRL_CLCR_LGO_SHIFT (0U) -/*! LGO - Initiate Cache Line Command - * 0b0..Write: no effect. Read: no line command active. - * 0b1..Write: initiate line command indicated by bits 27-24. Read: line command active. - */ -#define CACHE64_CTRL_CLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK) - -#define CACHE64_CTRL_CLCR_CACHEADDR_MASK (0x3FFCU) -#define CACHE64_CTRL_CLCR_CACHEADDR_SHIFT (2U) -/*! CACHEADDR - Cache address - */ -#define CACHE64_CTRL_CLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_CACHEADDR_SHIFT)) & CACHE64_CTRL_CLCR_CACHEADDR_MASK) - -#define CACHE64_CTRL_CLCR_WSEL_MASK (0x4000U) -#define CACHE64_CTRL_CLCR_WSEL_SHIFT (14U) -/*! WSEL - Way select - * 0b0..Way 0 - * 0b1..Way 1 - */ -#define CACHE64_CTRL_CLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_WSEL_SHIFT)) & CACHE64_CTRL_CLCR_WSEL_MASK) - -#define CACHE64_CTRL_CLCR_TDSEL_MASK (0x10000U) -#define CACHE64_CTRL_CLCR_TDSEL_SHIFT (16U) -/*! TDSEL - Tag/Data Select - * 0b0..Data - * 0b1..Tag - */ -#define CACHE64_CTRL_CLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_TDSEL_SHIFT)) & CACHE64_CTRL_CLCR_TDSEL_MASK) - -#define CACHE64_CTRL_CLCR_LCIVB_MASK (0x100000U) -#define CACHE64_CTRL_CLCR_LCIVB_SHIFT (20U) -/*! LCIVB - Line Command Initial Valid Bit - */ -#define CACHE64_CTRL_CLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCIVB_SHIFT)) & CACHE64_CTRL_CLCR_LCIVB_MASK) - -#define CACHE64_CTRL_CLCR_LCIMB_MASK (0x200000U) -#define CACHE64_CTRL_CLCR_LCIMB_SHIFT (21U) -/*! LCIMB - Line Command Initial Modified Bit - */ -#define CACHE64_CTRL_CLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCIMB_SHIFT)) & CACHE64_CTRL_CLCR_LCIMB_MASK) - -#define CACHE64_CTRL_CLCR_LCWAY_MASK (0x400000U) -#define CACHE64_CTRL_CLCR_LCWAY_SHIFT (22U) -/*! LCWAY - Line Command Way - */ -#define CACHE64_CTRL_CLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCWAY_SHIFT)) & CACHE64_CTRL_CLCR_LCWAY_MASK) - -#define CACHE64_CTRL_CLCR_LCMD_MASK (0x3000000U) -#define CACHE64_CTRL_CLCR_LCMD_SHIFT (24U) -/*! LCMD - Line Command - * 0b00..Search and read or write - * 0b01..Invalidate - * 0b10..Push - * 0b11..Clear - */ -#define CACHE64_CTRL_CLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCMD_SHIFT)) & CACHE64_CTRL_CLCR_LCMD_MASK) - -#define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) -#define CACHE64_CTRL_CLCR_LADSEL_SHIFT (26U) -/*! LADSEL - Line Address Select - * 0b0..Cache address - * 0b1..Physical address - */ -#define CACHE64_CTRL_CLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK) - -#define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) -#define CACHE64_CTRL_CLCR_LACC_SHIFT (27U) -/*! LACC - Line access type - * 0b0..Read - * 0b1..Write - */ -#define CACHE64_CTRL_CLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK) -/*! @} */ - -/*! @name CSAR - Cache search address register */ -/*! @{ */ - -#define CACHE64_CTRL_CSAR_LGO_MASK (0x1U) -#define CACHE64_CTRL_CSAR_LGO_SHIFT (0U) -/*! LGO - Initiate Cache Line Command - * 0b0..Write: no effect. Read: no line command active. - * 0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active. - */ -#define CACHE64_CTRL_CSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_LGO_SHIFT)) & CACHE64_CTRL_CSAR_LGO_MASK) - -#define CACHE64_CTRL_CSAR_PHYADDR_MASK (0xFFFFFFFEU) -#define CACHE64_CTRL_CSAR_PHYADDR_SHIFT (1U) -/*! PHYADDR - Physical Address - */ -#define CACHE64_CTRL_CSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_PHYADDR_SHIFT)) & CACHE64_CTRL_CSAR_PHYADDR_MASK) -/*! @} */ - -/*! @name CCVR - Cache read/write value register */ -/*! @{ */ - -#define CACHE64_CTRL_CCVR_DATA_MASK (0xFFFFFFFFU) -#define CACHE64_CTRL_CCVR_DATA_SHIFT (0U) -/*! DATA - Cache read/write Data - */ -#define CACHE64_CTRL_CCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCVR_DATA_SHIFT)) & CACHE64_CTRL_CCVR_DATA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CACHE64_CTRL_Register_Masks */ - - -/* CACHE64_CTRL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CACHE64_CTRL0 base address */ - #define CACHE64_CTRL0_BASE (0x5002E000u) - /** Peripheral CACHE64_CTRL0 base address */ - #define CACHE64_CTRL0_BASE_NS (0x4002E000u) - /** Peripheral CACHE64_CTRL0 base pointer */ - #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) - /** Peripheral CACHE64_CTRL0 base pointer */ - #define CACHE64_CTRL0_NS ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE_NS) - /** Array initializer of CACHE64_CTRL peripheral base addresses */ - #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } - /** Array initializer of CACHE64_CTRL peripheral base pointers */ - #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } - /** Array initializer of CACHE64_CTRL peripheral base addresses */ - #define CACHE64_CTRL_BASE_ADDRS_NS { CACHE64_CTRL0_BASE_NS } - /** Array initializer of CACHE64_CTRL peripheral base pointers */ - #define CACHE64_CTRL_BASE_PTRS_NS { CACHE64_CTRL0_NS } -#else - /** Peripheral CACHE64_CTRL0 base address */ - #define CACHE64_CTRL0_BASE (0x4002E000u) - /** Peripheral CACHE64_CTRL0 base pointer */ - #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) - /** Array initializer of CACHE64_CTRL peripheral base addresses */ - #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } - /** Array initializer of CACHE64_CTRL peripheral base pointers */ - #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } -#endif -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** CACHE64_CTRL physical memory base address */ - #define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x38000000u } -/** CACHE64_CTRL physical memory size */ - #define CACHE64_CTRL_PHYMEM_SIZES { 0x08000000u, 0x08000000u } -/** CACHE64_CTRL physical memory base address */ - #define CACHE64_CTRL_PHYMEM_BASES_NS { 0x08000000u, 0x28000000u } -/** CACHE64_CTRL physical memory size */ - #define CACHE64_CTRL_PHYMEM_SIZES_NS { 0x08000000u, 0x08000000u } -#else -/** CACHE64_CTRL physical memory base address */ - #define CACHE64_CTRL_PHYMEM_BASES { 0x08000000u, 0x28000000u } -/** CACHE64_CTRL physical memory size */ - #define CACHE64_CTRL_PHYMEM_SIZES { 0x08000000u, 0x08000000u } -#endif -/* Backward compatibility */ - - -/*! - * @} - */ /* end of group CACHE64_CTRL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CACHE64_POLSEL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CACHE64_POLSEL_Peripheral_Access_Layer CACHE64_POLSEL Peripheral Access Layer - * @{ - */ - -/** CACHE64_POLSEL - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[20]; - __IO uint32_t REG0_TOP; /**< Region 0 Top Boundary, offset: 0x14 */ - __IO uint32_t REG1_TOP; /**< Region 1 Top Boundary, offset: 0x18 */ - __IO uint32_t POLSEL; /**< Policy Select, offset: 0x1C */ -} CACHE64_POLSEL_Type; - -/* ---------------------------------------------------------------------------- - -- CACHE64_POLSEL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CACHE64_POLSEL_Register_Masks CACHE64_POLSEL Register Masks - * @{ - */ - -/*! @name REG0_TOP - Region 0 Top Boundary */ -/*! @{ */ - -#define CACHE64_POLSEL_REG0_TOP_REG0_TOP_MASK (0x7FFFC00U) -#define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) -/*! REG0_TOP - Upper limit of Region 0 - */ -#define CACHE64_POLSEL_REG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) & CACHE64_POLSEL_REG0_TOP_REG0_TOP_MASK) -/*! @} */ - -/*! @name REG1_TOP - Region 1 Top Boundary */ -/*! @{ */ - -#define CACHE64_POLSEL_REG1_TOP_REG1_TOP_MASK (0x7FFFC00U) -#define CACHE64_POLSEL_REG1_TOP_REG1_TOP_SHIFT (10U) -/*! REG1_TOP - Upper limit of Region 1 - */ -#define CACHE64_POLSEL_REG1_TOP_REG1_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG1_TOP_REG1_TOP_SHIFT)) & CACHE64_POLSEL_REG1_TOP_REG1_TOP_MASK) -/*! @} */ - -/*! @name POLSEL - Policy Select */ -/*! @{ */ - -#define CACHE64_POLSEL_POLSEL_REG0_POLICY_MASK (0x3U) -#define CACHE64_POLSEL_POLSEL_REG0_POLICY_SHIFT (0U) -/*! REG0_POLICY - Policy Select for Region 0 - * 0b00..Non-cache - * 0b01..Write-thru - * 0b10..Write-back - * 0b11..Invalid - */ -#define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG0_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG0_POLICY_MASK) - -#define CACHE64_POLSEL_POLSEL_REG1_POLICY_MASK (0xCU) -#define CACHE64_POLSEL_POLSEL_REG1_POLICY_SHIFT (2U) -/*! REG1_POLICY - Policy Select for Region 0 - * 0b00..Non-cache - * 0b01..Write-thru - * 0b10..Write-back - * 0b11..Invalid - */ -#define CACHE64_POLSEL_POLSEL_REG1_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG1_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG1_POLICY_MASK) - -#define CACHE64_POLSEL_POLSEL_REG02_POLICY_MASK (0x30U) -#define CACHE64_POLSEL_POLSEL_REG02_POLICY_SHIFT (4U) -/*! REG02_POLICY - Policy Select for Region 0 - * 0b00..Non-cache - * 0b01..Write-thru - * 0b10..Write-back - * 0b11..Invalid - */ -#define CACHE64_POLSEL_POLSEL_REG02_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG02_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG02_POLICY_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CACHE64_POLSEL_Register_Masks */ - - -/* CACHE64_POLSEL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CACHE64_POLSEL0 base address */ - #define CACHE64_POLSEL0_BASE (0x5002E000u) - /** Peripheral CACHE64_POLSEL0 base address */ - #define CACHE64_POLSEL0_BASE_NS (0x4002E000u) - /** Peripheral CACHE64_POLSEL0 base pointer */ - #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) - /** Peripheral CACHE64_POLSEL0 base pointer */ - #define CACHE64_POLSEL0_NS ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE_NS) - /** Array initializer of CACHE64_POLSEL peripheral base addresses */ - #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } - /** Array initializer of CACHE64_POLSEL peripheral base pointers */ - #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } - /** Array initializer of CACHE64_POLSEL peripheral base addresses */ - #define CACHE64_POLSEL_BASE_ADDRS_NS { CACHE64_POLSEL0_BASE_NS } - /** Array initializer of CACHE64_POLSEL peripheral base pointers */ - #define CACHE64_POLSEL_BASE_PTRS_NS { CACHE64_POLSEL0_NS } -#else - /** Peripheral CACHE64_POLSEL0 base address */ - #define CACHE64_POLSEL0_BASE (0x4002E000u) - /** Peripheral CACHE64_POLSEL0 base pointer */ - #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) - /** Array initializer of CACHE64_POLSEL peripheral base addresses */ - #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } - /** Array initializer of CACHE64_POLSEL peripheral base pointers */ - #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } -#endif - -/*! - * @} - */ /* end of group CACHE64_POLSEL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CAN Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer - * @{ - */ - -/** CAN - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[12]; - __IO uint32_t DBTP; /**< Data Bit Timing and Prescaler, offset: 0xC */ - __IO uint32_t TEST; /**< Test, offset: 0x10 */ - uint8_t RESERVED_1[4]; - __IO uint32_t CCCR; /**< CC Control, offset: 0x18 */ - __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler, offset: 0x1C */ - __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */ - __I uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */ - __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */ - __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */ - uint8_t RESERVED_2[16]; - __I uint32_t ECR; /**< Error Counter, offset: 0x40 */ - __I uint32_t PSR; /**< Protocol Status, offset: 0x44 */ - __IO uint32_t TDCR; /**< Transmitter Delay Compensator, offset: 0x48 */ - uint8_t RESERVED_3[4]; - __IO uint32_t IR; /**< Interrupt, offset: 0x50 */ - __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */ - __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */ - __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */ - uint8_t RESERVED_4[32]; - __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */ - __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */ - __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */ - uint8_t RESERVED_5[4]; - __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */ - __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */ - __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */ - __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */ - __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */ - __I uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */ - __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */ - __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */ - __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */ - __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */ - __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */ - __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */ - __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */ - __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */ - __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */ - __I uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */ - __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */ - __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */ - __I uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */ - __I uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */ - __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */ - __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */ - uint8_t RESERVED_6[8]; - __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */ - __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */ - __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */ - uint8_t RESERVED_7[260]; - __IO uint32_t MRBA; /**< Message RAM Base Address, offset: 0x200 */ - uint8_t RESERVED_8[508]; - __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */ - uint8_t RESERVED_9[508]; - __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */ -} CAN_Type; - -/* ---------------------------------------------------------------------------- - -- CAN Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CAN_Register_Masks CAN Register Masks - * @{ - */ - -/*! @name DBTP - Data Bit Timing and Prescaler */ -/*! @{ */ - -#define CAN_DBTP_DSJW_MASK (0xFU) -#define CAN_DBTP_DSJW_SHIFT (0U) -/*! DSJW - Data (Re)Synchronization Jump Width - */ -#define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK) - -#define CAN_DBTP_DTSEG2_MASK (0xF0U) -#define CAN_DBTP_DTSEG2_SHIFT (4U) -/*! DTSEG2 - Data Time Segment After Sample Point - */ -#define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK) - -#define CAN_DBTP_DTSEG1_MASK (0x1F00U) -#define CAN_DBTP_DTSEG1_SHIFT (8U) -/*! DTSEG1 - Data Time Segment Before Sample Point - */ -#define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK) - -#define CAN_DBTP_DBRP_MASK (0x1F0000U) -#define CAN_DBTP_DBRP_SHIFT (16U) -/*! DBRP - Data Bit Rate Prescaler - */ -#define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK) - -#define CAN_DBTP_TDC_MASK (0x800000U) -#define CAN_DBTP_TDC_SHIFT (23U) -/*! TDC - Transmitter Delay Compensation - * 0b0..Transmitter delay compensation disabled - * 0b1..Transmitter delay compensation enabled - */ -#define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK) -/*! @} */ - -/*! @name TEST - Test */ -/*! @{ */ - -#define CAN_TEST_LBCK_MASK (0x10U) -#define CAN_TEST_LBCK_SHIFT (4U) -/*! LBCK - Loop Back Mode - * 0b0..Loop back mode is disabled. - * 0b1..Loop back mode is enabled. - */ -#define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK) - -#define CAN_TEST_TX_MASK (0x60U) -#define CAN_TEST_TX_SHIFT (5U) -/*! TX - Control of Transmit Pin - * 0b00..Loop back mode is disabled. - * 0b01..The sample point can be monitored at the CAN_TXD. - * 0b10..CAN_TXD pin is driven LOW/dominant. - * 0b11..CAN_TXD is driven HIGH/recessive. - */ -#define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK) - -#define CAN_TEST_RX_MASK (0x80U) -#define CAN_TEST_RX_SHIFT (7U) -/*! RX - Monitors the Actual Value of the CAN_RXD - * 0b0..The CAN bus is dominant (CAN_RXD = 0). - * 0b1..The CAN bus is recessive (CAN_RXD = 1). - */ -#define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK) -/*! @} */ - -/*! @name CCCR - CC Control */ -/*! @{ */ - -#define CAN_CCCR_INIT_MASK (0x1U) -#define CAN_CCCR_INIT_SHIFT (0U) -/*! INIT - Initialization - * 0b0..Normal operation - * 0b1..Initialization is started - */ -#define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK) - -#define CAN_CCCR_CCE_MASK (0x2U) -#define CAN_CCCR_CCE_SHIFT (1U) -/*! CCE - Configuration Change Enable - * 0b0..No write access. The CPU has no write access to the protected configuration registers. - * 0b1..Write access. The CPU has write access to the protected configuration registers. - */ -#define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK) - -#define CAN_CCCR_ASM_MASK (0x4U) -#define CAN_CCCR_ASM_SHIFT (2U) -/*! ASM - Restricted Operational Mode - * 0b0..Normal CAN operation - * 0b1..Restricted operation mode active - */ -#define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK) - -#define CAN_CCCR_CSA_MASK (0x8U) -#define CAN_CCCR_CSA_SHIFT (3U) -/*! CSA - Clock Stop Acknowledge - * 0b0..No clock stop acknowledged. - * 0b1..MCAN may be set in Power Down mode by stopping the internal MCAN clocks. - */ -#define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK) - -#define CAN_CCCR_CSR_MASK (0x10U) -#define CAN_CCCR_CSR_SHIFT (4U) -/*! CSR - Clock Stop Request - * 0b0..No clock stop is requested. - * 0b1..Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending - * transfer requests have been completed and the CAN bus reaches idle. - */ -#define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK) - -#define CAN_CCCR_MON_MASK (0x20U) -#define CAN_CCCR_MON_SHIFT (5U) -/*! MON - Bus Monitoring Mode - * 0b0..Bus Monitoring mode is disabled. - * 0b1..Bus Monitoring mode is enabled. - */ -#define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK) - -#define CAN_CCCR_DAR_MASK (0x40U) -#define CAN_CCCR_DAR_SHIFT (6U) -/*! DAR - Disable Automatic Retransmission - * 0b0..Automatic retransmission of messages not transmitted successfully enabled. - * 0b1..Automatic retransmission disabled. - */ -#define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK) - -#define CAN_CCCR_TEST_MASK (0x80U) -#define CAN_CCCR_TEST_SHIFT (7U) -/*! TEST - Test Mode Enable - * 0b0..Normal operation - * 0b1..Test mode enabled - */ -#define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK) - -#define CAN_CCCR_FDOE_MASK (0x100U) -#define CAN_CCCR_FDOE_SHIFT (8U) -/*! FDOE - CAN FD Operation Enable - * 0b0..CAN FD operation is disabled. - * 0b1..CAN FD operation is enabled. - */ -#define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK) - -#define CAN_CCCR_BRSE_MASK (0x200U) -#define CAN_CCCR_BRSE_SHIFT (9U) -/*! BRSE - Bit Rate Switching Enable - * 0b0..Bit rate switching for transmissions is disabled. - * 0b1..Bit rate switching for transmission is enabled. - */ -#define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK) - -#define CAN_CCCR_PXHD_MASK (0x1000U) -#define CAN_CCCR_PXHD_SHIFT (12U) -/*! PXHD - Protocol Exception Handling Disable - * 0b0..Protocol exception handling is enabled. - * 0b1..Protocol exception handling is disabled. - */ -#define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK) - -#define CAN_CCCR_EFBI_MASK (0x2000U) -#define CAN_CCCR_EFBI_SHIFT (13U) -/*! EFBI - Edge Filtering During Bus Integration - * 0b0..Edge filtering is disabled. - * 0b1..Two consecutive dominant quanta required to detect an edge for hard synchronization. - */ -#define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK) - -#define CAN_CCCR_TXP_MASK (0x4000U) -#define CAN_CCCR_TXP_SHIFT (14U) -/*! TXP - Transmit Pause - * 0b0..Transmit pause is disabled. - * 0b1..Transmit pause is enabled. - */ -#define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK) - -#define CAN_CCCR_NISO_MASK (0x8000U) -#define CAN_CCCR_NISO_SHIFT (15U) -/*! NISO - Non ISO Operation - * 0b0..CAN FD frame format will follow according to ISO11898-1. - * 0b1..CAN FD frame format will follow according to Bosch CAN FD Specification V1.0. - */ -#define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK) -/*! @} */ - -/*! @name NBTP - Nominal Bit Timing and Prescaler */ -/*! @{ */ - -#define CAN_NBTP_NTSEG2_MASK (0x7FU) -#define CAN_NBTP_NTSEG2_SHIFT (0U) -/*! NTSEG2 - Nominal Time Segment After Sample Point - */ -#define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK) - -#define CAN_NBTP_NTSEG1_MASK (0xFF00U) -#define CAN_NBTP_NTSEG1_SHIFT (8U) -/*! NTSEG1 - Nominal Time Segment Before Sample Point - */ -#define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK) - -#define CAN_NBTP_NBRP_MASK (0x1FF0000U) -#define CAN_NBTP_NBRP_SHIFT (16U) -/*! NBRP - Nominal Bit Rate Prescaler - */ -#define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK) - -#define CAN_NBTP_NSJW_MASK (0xFE000000U) -#define CAN_NBTP_NSJW_SHIFT (25U) -/*! NSJW - Nominal (Re)Synchronization Jump Width - */ -#define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK) -/*! @} */ - -/*! @name TSCC - Timestamp Counter Configuration */ -/*! @{ */ - -#define CAN_TSCC_TSS_MASK (0x3U) -#define CAN_TSCC_TSS_SHIFT (0U) -/*! TSS - Timestamp Select - * 0b00, 0b11..Timestamp counter value static at 0x0000 - * 0b01..Timestamp counter value incremented according to TCP bits - * 0b10..External timestamp counter value used - */ -#define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK) - -#define CAN_TSCC_TCP_MASK (0xF0000U) -#define CAN_TSCC_TCP_SHIFT (16U) -/*! TCP - Timestamp Counter Prescaler - */ -#define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK) -/*! @} */ - -/*! @name TSCV - Timestamp Counter Value */ -/*! @{ */ - -#define CAN_TSCV_TSC_MASK (0xFFFFU) -#define CAN_TSCV_TSC_SHIFT (0U) -/*! TSC - Timestamp Counter - */ -#define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK) -/*! @} */ - -/*! @name TOCC - Timeout Counter Configuration */ -/*! @{ */ - -#define CAN_TOCC_ETOC_MASK (0x1U) -#define CAN_TOCC_ETOC_SHIFT (0U) -/*! ETOC - Enable Timeout Counter - * 0b0..Timeout counter is disabled. - * 0b1..Timeout counter is enabled. - */ -#define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK) - -#define CAN_TOCC_TOS_MASK (0x6U) -#define CAN_TOCC_TOS_SHIFT (1U) -/*! TOS - Timeout Select - * 0b00..Continuous operation - * 0b01..Timeout is controlled by Tx event FIFO. - * 0b10..Timeout is controlled by Rx FIFO 0. - * 0b11..Timeout is controlled by Rx FIFO 1. - */ -#define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK) - -#define CAN_TOCC_TOP_MASK (0xFFFF0000U) -#define CAN_TOCC_TOP_SHIFT (16U) -/*! TOP - Timeout Period - */ -#define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK) -/*! @} */ - -/*! @name TOCV - Timeout Counter Value */ -/*! @{ */ - -#define CAN_TOCV_TOC_MASK (0xFFFFU) -#define CAN_TOCV_TOC_SHIFT (0U) -/*! TOC - Timeout Counter - */ -#define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK) -/*! @} */ - -/*! @name ECR - Error Counter */ -/*! @{ */ - -#define CAN_ECR_TEC_MASK (0xFFU) -#define CAN_ECR_TEC_SHIFT (0U) -/*! TEC - Transmit Error Counter - */ -#define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK) - -#define CAN_ECR_REC_MASK (0x7F00U) -#define CAN_ECR_REC_SHIFT (8U) -/*! REC - Receive Error Counter - */ -#define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK) - -#define CAN_ECR_RP_MASK (0x8000U) -#define CAN_ECR_RP_SHIFT (15U) -/*! RP - Receive Error Passive - * 0b0..Below error level. The receive counter is below the error passive level of 128. - * 0b1..At error level. The receive counter has reached the error passive level of 128. - */ -#define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK) - -#define CAN_ECR_CEL_MASK (0xFF0000U) -#define CAN_ECR_CEL_SHIFT (16U) -/*! CEL - CAN Error Logging - */ -#define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK) -/*! @} */ - -/*! @name PSR - Protocol Status */ -/*! @{ */ - -#define CAN_PSR_LEC_MASK (0x7U) -#define CAN_PSR_LEC_SHIFT (0U) -/*! LEC - Last Error Code - * 0b000..No error: No error has occurred since the LEC bits has been reset by successful reception or transmission. - * 0b001..Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where not allowed. - * 0b010..Form error: A fixed format part of a received frame has the wrong format. - * 0b011..AckError: The message transmitted by the MCAN was not acknowledged by another node. - * 0b100..Bit1Error: During the transmission of a message (with the exception of the arbitration field), the - * device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant. - * 0b101..Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload - * flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the - * monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 - * recessive bits has been monitored. This enables the CPU to monitor the processing of the Bus_Off recovery - * sequence (indicating the bus is not stuck at dominant or continuously disturbed). - * 0b110..CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does - * not match with the CRC calculated from the received data. - * 0b111..NoChange: Any read access to the protocol status register re-initializes the LEC bits to 0x7. When the - * LEC equals the value 0x7, no CAN bus event was detected since the last CPU read access to the protocol - * status register. - */ -#define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK) - -#define CAN_PSR_ACT_MASK (0x18U) -#define CAN_PSR_ACT_SHIFT (3U) -/*! ACT - Activity - * 0b00..Synchronizing - node is synchronizing on CAN communication. - * 0b01..Idle - node is neither receiver nor transmitter. - * 0b10..Receiver - node is operating as receiver. - * 0b11..Transmitter - node is operating as transmitter. - */ -#define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK) - -#define CAN_PSR_EP_MASK (0x20U) -#define CAN_PSR_EP_SHIFT (5U) -/*! EP - Error Passive - * 0b0..The MCAN is in Error_Active state. It normally takes part in bus communication and sends an active error - * flag when an error has been detected. - * 0b1..The MCAN is in the Error_Passive state. - */ -#define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK) - -#define CAN_PSR_EW_MASK (0x40U) -#define CAN_PSR_EW_SHIFT (6U) -/*! EW - Warning Status - * 0b0..Both error counters are below the Error_Warning limit of 96. - * 0b1..At least one of error counter has reached the Error_Warning limit of 96. - */ -#define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK) - -#define CAN_PSR_BO_MASK (0x80U) -#define CAN_PSR_BO_SHIFT (7U) -/*! BO - Bus Off Status - * 0b0..Disabled - * 0b1..Enabled - */ -#define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK) - -#define CAN_PSR_DLEC_MASK (0x700U) -#define CAN_PSR_DLEC_SHIFT (8U) -/*! DLEC - Data Phase Last Error Code - */ -#define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK) - -#define CAN_PSR_RESI_MASK (0x800U) -#define CAN_PSR_RESI_SHIFT (11U) -/*! RESI - ESI Flag of the Last Received CAN FD Message - * 0b0..Last received CAN FD message did not have its ESI flag set. - * 0b1..Last received CAN FD message had its ESI flag set. - */ -#define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK) - -#define CAN_PSR_RBRS_MASK (0x1000U) -#define CAN_PSR_RBRS_SHIFT (12U) -/*! RBRS - BRS Flag of Last Received CAN FD Message - * 0b0..Last received CAN FD message did not have its BRS flag set. - * 0b1..Last received CAN FD message had its BRS flag set. - */ -#define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK) - -#define CAN_PSR_RFDF_MASK (0x2000U) -#define CAN_PSR_RFDF_SHIFT (13U) -/*! RFDF - Received a CAN FD Message - * 0b0..No CAN FD message received since the last CPU reset. - * 0b1..Message in CAN FD format with FDF flag set has been received. - */ -#define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK) - -#define CAN_PSR_PXE_MASK (0x4000U) -#define CAN_PSR_PXE_SHIFT (14U) -/*! PXE - Protocol Exception Event - * 0b0..No protocol exception event occurred since last read access. - * 0b1..Protocol exception event occurred. - */ -#define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK) - -#define CAN_PSR_TDCV_MASK (0x7F0000U) -#define CAN_PSR_TDCV_SHIFT (16U) -/*! TDCV - Transmitter Delay Compensation Value - */ -#define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK) -/*! @} */ - -/*! @name TDCR - Transmitter Delay Compensator */ -/*! @{ */ - -#define CAN_TDCR_TDCF_MASK (0x7FU) -#define CAN_TDCR_TDCF_SHIFT (0U) -/*! TDCF - Transmitter Delay Compensation Filter Window Length - */ -#define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK) - -#define CAN_TDCR_TDCO_MASK (0x7F00U) -#define CAN_TDCR_TDCO_SHIFT (8U) -/*! TDCO - Transmitter Delay Compensation Offset - */ -#define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK) -/*! @} */ - -/*! @name IR - Interrupt */ -/*! @{ */ - -#define CAN_IR_RF0N_MASK (0x1U) -#define CAN_IR_RF0N_SHIFT (0U) -/*! RF0N - Rx FIFO 0 New Message - * 0b0..No new message written to Rx FIFO 0. - * 0b1..New message written to Rx FIFO 0. - */ -#define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK) - -#define CAN_IR_RF0W_MASK (0x2U) -#define CAN_IR_RF0W_SHIFT (1U) -/*! RF0W - Rx FIFO 0 Watermark Reached - * 0b0..Rx FIFO 0 fill level below watermark. - * 0b1..Rx FIFO 0 fill level reached watermark. - */ -#define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK) - -#define CAN_IR_RF0F_MASK (0x4U) -#define CAN_IR_RF0F_SHIFT (2U) -/*! RF0F - Rx FIFO 0 Full - * 0b0..Rx FIFO 0 not full. - * 0b1..Rx FIFO 0 full. - */ -#define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK) - -#define CAN_IR_RF0L_MASK (0x8U) -#define CAN_IR_RF0L_SHIFT (3U) -/*! RF0L - Rx FIFO 0 Message Lost - * 0b0..No Rx FIFO 0 message lost. - * 0b1..Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero. - */ -#define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK) - -#define CAN_IR_RF1N_MASK (0x10U) -#define CAN_IR_RF1N_SHIFT (4U) -/*! RF1N - Rx FIFO 1 New Message - * 0b0..No new message written to Rx FIFO 1. - * 0b1..New message written to Rx FIFO 1. - */ -#define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK) - -#define CAN_IR_RF1W_MASK (0x20U) -#define CAN_IR_RF1W_SHIFT (5U) -/*! RF1W - Rx FIFO 1 Watermark Reached - * 0b0..Rx FIFO 1 fill level below watermark. - * 0b1..Rx FIFO 1 fill level reached watermark. - */ -#define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK) - -#define CAN_IR_RF1F_MASK (0x40U) -#define CAN_IR_RF1F_SHIFT (6U) -/*! RF1F - Rx FIFO 1 Full - * 0b0..Rx FIFO 1 not full. - * 0b1..Rx FIFO 1 full. - */ -#define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK) - -#define CAN_IR_RF1L_MASK (0x80U) -#define CAN_IR_RF1L_SHIFT (7U) -/*! RF1L - Rx FIFO 1 Message Lost - * 0b0..No Rx FIFO 1 message lost. - * 0b1..Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero. - */ -#define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK) - -#define CAN_IR_HPM_MASK (0x100U) -#define CAN_IR_HPM_SHIFT (8U) -/*! HPM - High Priority Message - * 0b0..No high priority message received. - * 0b1..High priority message received. - */ -#define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK) - -#define CAN_IR_TC_MASK (0x200U) -#define CAN_IR_TC_SHIFT (9U) -/*! TC - Transmission Completed - * 0b0..No transmission completed. - * 0b1..Transmission completed. - */ -#define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK) - -#define CAN_IR_TCF_MASK (0x400U) -#define CAN_IR_TCF_SHIFT (10U) -/*! TCF - Transmission Cancellation Finished - * 0b0..No transmission cancellation finished. - * 0b1..Transmission cancellation finished. - */ -#define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK) - -#define CAN_IR_TFE_MASK (0x800U) -#define CAN_IR_TFE_SHIFT (11U) -/*! TFE - Tx FIFO Empty - * 0b0..Tx FIFO non-empty. - * 0b1..Tx FIFO empty. - */ -#define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK) - -#define CAN_IR_TEFN_MASK (0x1000U) -#define CAN_IR_TEFN_SHIFT (12U) -/*! TEFN - Tx Event FIFO New Entry - * 0b0..Tx event FIFO unchanged. - * 0b1..Tx Handler wrote Tx event FIFO element. - */ -#define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK) - -#define CAN_IR_TEFW_MASK (0x2000U) -#define CAN_IR_TEFW_SHIFT (13U) -/*! TEFW - Tx Event FIFO Watermark Reached - * 0b0..Tx event FIFO fill level below watermark. - * 0b1..Tx event FIFO fill level reached watermark. - */ -#define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK) - -#define CAN_IR_TEFF_MASK (0x4000U) -#define CAN_IR_TEFF_SHIFT (14U) -/*! TEFF - Tx Event FIFO Full - * 0b0..Tx event FIFO not full. - * 0b1..Tx event FIFO full. - */ -#define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK) - -#define CAN_IR_TEFL_MASK (0x8000U) -#define CAN_IR_TEFL_SHIFT (15U) -/*! TEFL - Tx Event FIFO Element Lost - * 0b0..No Tx event FIFO element lost. - * 0b1..Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size zero. - */ -#define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK) - -#define CAN_IR_TSW_MASK (0x10000U) -#define CAN_IR_TSW_SHIFT (16U) -/*! TSW - Timestamp Wraparound - * 0b0..No timestamp counter wraparound. - * 0b1..Timestamp counter wrapped around. - */ -#define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK) - -#define CAN_IR_MRAF_MASK (0x20000U) -#define CAN_IR_MRAF_SHIFT (17U) -/*! MRAF - Message RAM Access Failure - * 0b0..No message RAM access failure occurred. - * 0b1..Message RAM access failure occurred. - */ -#define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK) - -#define CAN_IR_TOO_MASK (0x40000U) -#define CAN_IR_TOO_SHIFT (18U) -/*! TOO - Timeout Occurred - * 0b0..No timeout. - * 0b1..Timeout reached. - */ -#define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK) - -#define CAN_IR_DRX_MASK (0x80000U) -#define CAN_IR_DRX_SHIFT (19U) -/*! DRX - Message Stored in Dedicated Rx Buffer - * 0b0..No Rx buffer updated. - * 0b1..At least one received message stored into an Rx buffer. - */ -#define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK) - -#define CAN_IR_BEC_MASK (0x100000U) -#define CAN_IR_BEC_SHIFT (20U) -/*! BEC - Bit Error Corrected - * 0b0..No bit error detected when reading from message RAM. - * 0b1..Bit error detected and corrected (example, ECC). - */ -#define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK) - -#define CAN_IR_BEU_MASK (0x200000U) -#define CAN_IR_BEU_SHIFT (21U) -/*! BEU - Bit Error Uncorrected - * 0b0..No bit error detected when reading from message RAM. - * 0b1..Bit error detected, uncorrected (example, parity logic). - */ -#define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK) - -#define CAN_IR_ELO_MASK (0x400000U) -#define CAN_IR_ELO_SHIFT (22U) -/*! ELO - Error Logging Overflow - * 0b0..CAN error logging counter did not overflow. - * 0b1..Overflow of CAN error logging counter occurred. - */ -#define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK) - -#define CAN_IR_EP_MASK (0x800000U) -#define CAN_IR_EP_SHIFT (23U) -/*! EP - Error Passive - * 0b0..Error_Passive status unchanged. - * 0b1..Error_Passive status changed. - */ -#define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK) - -#define CAN_IR_EW_MASK (0x1000000U) -#define CAN_IR_EW_SHIFT (24U) -/*! EW - Warning Status - * 0b0..Error_Warning status unchanged. - * 0b1..Error_Warning status changed. - */ -#define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK) - -#define CAN_IR_BO_MASK (0x2000000U) -#define CAN_IR_BO_SHIFT (25U) -/*! BO - Bus_Off Status - * 0b0..Bus_Off status unchanged. - * 0b1..Bus_Off status changed. - */ -#define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK) - -#define CAN_IR_WDI_MASK (0x4000000U) -#define CAN_IR_WDI_SHIFT (26U) -/*! WDI - Watchdog Interrupt - * 0b0..No message RAM watchdog event occurred. - * 0b1..Message RAM watchdog event due to missing READY. - */ -#define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK) - -#define CAN_IR_PEA_MASK (0x8000000U) -#define CAN_IR_PEA_SHIFT (27U) -/*! PEA - Protocol Error in Arbitration Phase - * 0b0..No protocol error in arbitration phase. - * 0b1..Protocol error in arbitration phase detected. - */ -#define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK) - -#define CAN_IR_PED_MASK (0x10000000U) -#define CAN_IR_PED_SHIFT (28U) -/*! PED - Protocol Error in Data Phase - * 0b0..No protocol error in data phase. - * 0b1..Protocol error in data phase detected. - */ -#define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK) - -#define CAN_IR_ARA_MASK (0x20000000U) -#define CAN_IR_ARA_SHIFT (29U) -/*! ARA - Access to Reserved Address - * 0b0..No access to reserved address occurred. - * 0b1..Access to reserved address occurred. - */ -#define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK) -/*! @} */ - -/*! @name IE - Interrupt Enable */ -/*! @{ */ - -#define CAN_IE_RF0NE_MASK (0x1U) -#define CAN_IE_RF0NE_SHIFT (0U) -/*! RF0NE - Rx FIFO 0 New Message Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK) - -#define CAN_IE_RF0WE_MASK (0x2U) -#define CAN_IE_RF0WE_SHIFT (1U) -/*! RF0WE - Rx FIFO 0 Watermark Reached Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK) - -#define CAN_IE_RF0FE_MASK (0x4U) -#define CAN_IE_RF0FE_SHIFT (2U) -/*! RF0FE - Rx FIFO 0 Full Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK) - -#define CAN_IE_RF0LE_MASK (0x8U) -#define CAN_IE_RF0LE_SHIFT (3U) -/*! RF0LE - Rx FIFO 0 Message Lost Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK) - -#define CAN_IE_RF1NE_MASK (0x10U) -#define CAN_IE_RF1NE_SHIFT (4U) -/*! RF1NE - Rx FIFO 1 New Message Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK) - -#define CAN_IE_RF1WE_MASK (0x20U) -#define CAN_IE_RF1WE_SHIFT (5U) -/*! RF1WE - Rx FIFO 1 Watermark Reached Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK) - -#define CAN_IE_RF1FE_MASK (0x40U) -#define CAN_IE_RF1FE_SHIFT (6U) -/*! RF1FE - Rx FIFO 1 Full Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK) - -#define CAN_IE_RF1LE_MASK (0x80U) -#define CAN_IE_RF1LE_SHIFT (7U) -/*! RF1LE - Rx FIFO 1 Message Lost Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK) - -#define CAN_IE_HPME_MASK (0x100U) -#define CAN_IE_HPME_SHIFT (8U) -/*! HPME - High Priority Message Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK) - -#define CAN_IE_TCE_MASK (0x200U) -#define CAN_IE_TCE_SHIFT (9U) -/*! TCE - Transmission Completed Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK) - -#define CAN_IE_TCFE_MASK (0x400U) -#define CAN_IE_TCFE_SHIFT (10U) -/*! TCFE - Transmission Cancellation Finished Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK) - -#define CAN_IE_TFEE_MASK (0x800U) -#define CAN_IE_TFEE_SHIFT (11U) -/*! TFEE - Tx FIFO Empty Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK) - -#define CAN_IE_TEFNE_MASK (0x1000U) -#define CAN_IE_TEFNE_SHIFT (12U) -/*! TEFNE - Tx Event FIFO New Entry Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK) - -#define CAN_IE_TEFWE_MASK (0x2000U) -#define CAN_IE_TEFWE_SHIFT (13U) -/*! TEFWE - Tx Event FIFO Watermark Reached Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK) - -#define CAN_IE_TEFFE_MASK (0x4000U) -#define CAN_IE_TEFFE_SHIFT (14U) -/*! TEFFE - Tx Event FIFO Full Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK) - -#define CAN_IE_TEFLE_MASK (0x8000U) -#define CAN_IE_TEFLE_SHIFT (15U) -/*! TEFLE - Tx Event FIFO Element Lost Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK) - -#define CAN_IE_TSWE_MASK (0x10000U) -#define CAN_IE_TSWE_SHIFT (16U) -/*! TSWE - Timestamp Wraparound Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK) - -#define CAN_IE_MRAFE_MASK (0x20000U) -#define CAN_IE_MRAFE_SHIFT (17U) -/*! MRAFE - Message RAM Access Failure Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK) - -#define CAN_IE_TOOE_MASK (0x40000U) -#define CAN_IE_TOOE_SHIFT (18U) -/*! TOOE - Timeout Occurred Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK) - -#define CAN_IE_DRXE_MASK (0x80000U) -#define CAN_IE_DRXE_SHIFT (19U) -/*! DRXE - Message Stored in Dedicated Rx Buffer Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK) - -#define CAN_IE_BECE_MASK (0x100000U) -#define CAN_IE_BECE_SHIFT (20U) -/*! BECE - Bit Error Corrected Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK) - -#define CAN_IE_BEUE_MASK (0x200000U) -#define CAN_IE_BEUE_SHIFT (21U) -/*! BEUE - Bit Error Uncorrected Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK) - -#define CAN_IE_ELOE_MASK (0x400000U) -#define CAN_IE_ELOE_SHIFT (22U) -/*! ELOE - Error Logging Overflow Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK) - -#define CAN_IE_EPE_MASK (0x800000U) -#define CAN_IE_EPE_SHIFT (23U) -/*! EPE - Error Passive Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK) - -#define CAN_IE_EWE_MASK (0x1000000U) -#define CAN_IE_EWE_SHIFT (24U) -/*! EWE - Warning Status Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK) - -#define CAN_IE_BOE_MASK (0x2000000U) -#define CAN_IE_BOE_SHIFT (25U) -/*! BOE - Bus_Off Status Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK) - -#define CAN_IE_WDIE_MASK (0x4000000U) -#define CAN_IE_WDIE_SHIFT (26U) -/*! WDIE - Watchdog Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK) - -#define CAN_IE_PEAE_MASK (0x8000000U) -#define CAN_IE_PEAE_SHIFT (27U) -/*! PEAE - Protocol Error in Arbitration Phase Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK) - -#define CAN_IE_PEDE_MASK (0x10000000U) -#define CAN_IE_PEDE_SHIFT (28U) -/*! PEDE - Protocol Error in Data Phase Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK) - -#define CAN_IE_ARAE_MASK (0x20000000U) -#define CAN_IE_ARAE_SHIFT (29U) -/*! ARAE - Access to Reserved Address Interrupt Enable - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK) -/*! @} */ - -/*! @name ILS - Interrupt Line Select */ -/*! @{ */ - -#define CAN_ILS_RF0NL_MASK (0x1U) -#define CAN_ILS_RF0NL_SHIFT (0U) -/*! RF0NL - Rx FIFO 0 New Message Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK) - -#define CAN_ILS_RF0WL_MASK (0x2U) -#define CAN_ILS_RF0WL_SHIFT (1U) -/*! RF0WL - Rx FIFO 0 Watermark Reached Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK) - -#define CAN_ILS_RF0FL_MASK (0x4U) -#define CAN_ILS_RF0FL_SHIFT (2U) -/*! RF0FL - Rx FIFO 0 Full Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK) - -#define CAN_ILS_RF0LL_MASK (0x8U) -#define CAN_ILS_RF0LL_SHIFT (3U) -/*! RF0LL - Rx FIFO 0 Message Lost Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK) - -#define CAN_ILS_RF1NL_MASK (0x10U) -#define CAN_ILS_RF1NL_SHIFT (4U) -/*! RF1NL - Rx FIFO 1 New Message Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK) - -#define CAN_ILS_RF1WL_MASK (0x20U) -#define CAN_ILS_RF1WL_SHIFT (5U) -/*! RF1WL - Rx FIFO 1 Watermark Reached Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK) - -#define CAN_ILS_RF1FL_MASK (0x40U) -#define CAN_ILS_RF1FL_SHIFT (6U) -/*! RF1FL - Rx FIFO 1 Full Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK) - -#define CAN_ILS_RF1LL_MASK (0x80U) -#define CAN_ILS_RF1LL_SHIFT (7U) -/*! RF1LL - Rx FIFO 1 Message Lost Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK) - -#define CAN_ILS_HPML_MASK (0x100U) -#define CAN_ILS_HPML_SHIFT (8U) -/*! HPML - High Priority Message Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK) - -#define CAN_ILS_TCL_MASK (0x200U) -#define CAN_ILS_TCL_SHIFT (9U) -/*! TCL - Transmission Completed Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK) - -#define CAN_ILS_TCFL_MASK (0x400U) -#define CAN_ILS_TCFL_SHIFT (10U) -/*! TCFL - Transmission Cancellation Finished Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK) - -#define CAN_ILS_TFEL_MASK (0x800U) -#define CAN_ILS_TFEL_SHIFT (11U) -/*! TFEL - Tx FIFO Empty Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK) - -#define CAN_ILS_TEFNL_MASK (0x1000U) -#define CAN_ILS_TEFNL_SHIFT (12U) -/*! TEFNL - Tx Event FIFO New Entry Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK) - -#define CAN_ILS_TEFWL_MASK (0x2000U) -#define CAN_ILS_TEFWL_SHIFT (13U) -/*! TEFWL - Tx Event FIFO Watermark Reached Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK) - -#define CAN_ILS_TEFFL_MASK (0x4000U) -#define CAN_ILS_TEFFL_SHIFT (14U) -/*! TEFFL - Tx Event FIFO Full Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK) - -#define CAN_ILS_TEFLL_MASK (0x8000U) -#define CAN_ILS_TEFLL_SHIFT (15U) -/*! TEFLL - Tx Event FIFO Element Lost Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK) - -#define CAN_ILS_TSWL_MASK (0x10000U) -#define CAN_ILS_TSWL_SHIFT (16U) -/*! TSWL - Timestamp Wraparound Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK) - -#define CAN_ILS_MRAFL_MASK (0x20000U) -#define CAN_ILS_MRAFL_SHIFT (17U) -/*! MRAFL - Message RAM Access Failure Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK) - -#define CAN_ILS_TOOL_MASK (0x40000U) -#define CAN_ILS_TOOL_SHIFT (18U) -/*! TOOL - Timeout Occurred Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK) - -#define CAN_ILS_DRXL_MASK (0x80000U) -#define CAN_ILS_DRXL_SHIFT (19U) -/*! DRXL - Message Stored in Dedicated Rx Buffer Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK) - -#define CAN_ILS_BECL_MASK (0x100000U) -#define CAN_ILS_BECL_SHIFT (20U) -/*! BECL - Bit Error Corrected Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK) - -#define CAN_ILS_BEUL_MASK (0x200000U) -#define CAN_ILS_BEUL_SHIFT (21U) -/*! BEUL - Bit Error Uncorrected Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK) - -#define CAN_ILS_ELOL_MASK (0x400000U) -#define CAN_ILS_ELOL_SHIFT (22U) -/*! ELOL - Error Logging Overflow Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK) - -#define CAN_ILS_EPL_MASK (0x800000U) -#define CAN_ILS_EPL_SHIFT (23U) -/*! EPL - Error Passive Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK) - -#define CAN_ILS_EWL_MASK (0x1000000U) -#define CAN_ILS_EWL_SHIFT (24U) -/*! EWL - Warning Status Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK) - -#define CAN_ILS_BOL_MASK (0x2000000U) -#define CAN_ILS_BOL_SHIFT (25U) -/*! BOL - Bus_Off Status Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK) - -#define CAN_ILS_WDIL_MASK (0x4000000U) -#define CAN_ILS_WDIL_SHIFT (26U) -/*! WDIL - Watchdog Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK) - -#define CAN_ILS_PEAL_MASK (0x8000000U) -#define CAN_ILS_PEAL_SHIFT (27U) -/*! PEAL - Protocol Error in Arbitration Phase Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK) - -#define CAN_ILS_PEDL_MASK (0x10000000U) -#define CAN_ILS_PEDL_SHIFT (28U) -/*! PEDL - Protocol Error in Data Phase Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK) - -#define CAN_ILS_ARAL_MASK (0x20000000U) -#define CAN_ILS_ARAL_SHIFT (29U) -/*! ARAL - Access to Reserved Address Interrupt Line - * 0b0..Interrupt assigned to interrupt line MCANx_INT0 - * 0b1..Interrupt assigned to interrupt line MCANx_INT1 - */ -#define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK) -/*! @} */ - -/*! @name ILE - Interrupt Line Enable */ -/*! @{ */ - -#define CAN_ILE_EINT0_MASK (0x1U) -#define CAN_ILE_EINT0_SHIFT (0U) -/*! EINT0 - Enable Interrupt Line 0 - * 0b0..Interrupt line to MCANx_INT0 is disabled. - * 0b1..Interrupt line to MCANx_INT0 is enabled. - */ -#define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK) - -#define CAN_ILE_EINT1_MASK (0x2U) -#define CAN_ILE_EINT1_SHIFT (1U) -/*! EINT1 - Enable Interrupt Line 1 - * 0b0..Interrupt line to MCANx_INT1 is disabled. - * 0b1..Interrupt line to MCANx_INT1 is enabled. - */ -#define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK) -/*! @} */ - -/*! @name GFC - Global Filter Configuration */ -/*! @{ */ - -#define CAN_GFC_RRFE_MASK (0x1U) -#define CAN_GFC_RRFE_SHIFT (0U) -/*! RRFE - Reject Remote Frames Extended - * 0b0..Filter remote frames with 29-bit extended IDs - * 0b1..Reject all remote frames with 29-bit extended IDs - */ -#define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK) - -#define CAN_GFC_RRFS_MASK (0x2U) -#define CAN_GFC_RRFS_SHIFT (1U) -/*! RRFS - Reject Remote Frames Standard - * 0b0..Filter remote frames with 11-bit standard IDs - * 0b1..Reject all remote frames with 11-bit standard IDs - */ -#define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK) - -#define CAN_GFC_ANFE_MASK (0xCU) -#define CAN_GFC_ANFE_SHIFT (2U) -/*! ANFE - Accept Non-matching Frames Extended - * 0b00..Accept in Rx FIFO 0 - * 0b01..Accept in Rx FIFO 1 - * 0b10, 0b11..Reject - */ -#define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK) - -#define CAN_GFC_ANFS_MASK (0x30U) -#define CAN_GFC_ANFS_SHIFT (4U) -/*! ANFS - Accept Non-matching Frames Standard - * 0b00..Accept in Rx FIFO 0 - * 0b01..Accept in Rx FIFO 1 - * 0b10, 0b11..Reject - */ -#define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK) -/*! @} */ - -/*! @name SIDFC - Standard ID Filter Configuration */ -/*! @{ */ - -#define CAN_SIDFC_FLSSA_MASK (0xFFFCU) -#define CAN_SIDFC_FLSSA_SHIFT (2U) -/*! FLSSA - Filter List Standard Start Address - */ -#define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK) - -#define CAN_SIDFC_LSS_MASK (0xFF0000U) -#define CAN_SIDFC_LSS_SHIFT (16U) -/*! LSS - List Size Standard - */ -#define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK) -/*! @} */ - -/*! @name XIDFC - Extended ID Filter Configuration */ -/*! @{ */ - -#define CAN_XIDFC_FLESA_MASK (0xFFFCU) -#define CAN_XIDFC_FLESA_SHIFT (2U) -/*! FLESA - Filter List Extended Start Address - */ -#define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK) - -#define CAN_XIDFC_LSE_MASK (0xFF0000U) -#define CAN_XIDFC_LSE_SHIFT (16U) -/*! LSE - List Size Extended - */ -#define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK) -/*! @} */ - -/*! @name XIDAM - Extended ID AND Mask */ -/*! @{ */ - -#define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU) -#define CAN_XIDAM_EIDM_SHIFT (0U) -/*! EIDM - Extended ID Mask - */ -#define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK) -/*! @} */ - -/*! @name HPMS - High Priority Message Status */ -/*! @{ */ - -#define CAN_HPMS_BIDX_MASK (0x3FU) -#define CAN_HPMS_BIDX_SHIFT (0U) -/*! BIDX - Buffer Index - */ -#define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK) - -#define CAN_HPMS_MSI_MASK (0xC0U) -#define CAN_HPMS_MSI_SHIFT (6U) -/*! MSI - Message Storage Indicator - * 0b00..No FIFO selected - * 0b01..FIFO message lost - * 0b10..Message stored in FIFO 0 - * 0b11..Message stored in FIFO 1 - */ -#define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK) - -#define CAN_HPMS_FIDX_MASK (0x7F00U) -#define CAN_HPMS_FIDX_SHIFT (8U) -/*! FIDX - Filter Index - */ -#define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK) - -#define CAN_HPMS_FLST_MASK (0x8000U) -#define CAN_HPMS_FLST_SHIFT (15U) -/*! FLST - Filter List - * 0b0..Standard filter list - * 0b1..Extended filter list - */ -#define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK) -/*! @} */ - -/*! @name NDAT1 - New Data 1 */ -/*! @{ */ - -#define CAN_NDAT1_ND_MASK (0xFFFFFFFFU) -#define CAN_NDAT1_ND_SHIFT (0U) -/*! ND - New Data - */ -#define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK) -/*! @} */ - -/*! @name NDAT2 - New Data 2 */ -/*! @{ */ - -#define CAN_NDAT2_ND_MASK (0xFFFFFFFFU) -#define CAN_NDAT2_ND_SHIFT (0U) -/*! ND - New Data - */ -#define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK) -/*! @} */ - -/*! @name RXF0C - Rx FIFO 0 Configuration */ -/*! @{ */ - -#define CAN_RXF0C_F0SA_MASK (0xFFFCU) -#define CAN_RXF0C_F0SA_SHIFT (2U) -/*! F0SA - Rx FIFO 0 Start Address - */ -#define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK) - -#define CAN_RXF0C_F0S_MASK (0x7F0000U) -#define CAN_RXF0C_F0S_SHIFT (16U) -/*! F0S - Rx FIFO 0 Size - */ -#define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK) - -#define CAN_RXF0C_F0WM_MASK (0x7F000000U) -#define CAN_RXF0C_F0WM_SHIFT (24U) -/*! F0WM - Rx FIFO 0 Watermark - */ -#define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK) - -#define CAN_RXF0C_F0OM_MASK (0x80000000U) -#define CAN_RXF0C_F0OM_SHIFT (31U) -/*! F0OM - FIFO 0 Operation Mode - * 0b0..FIFO 0 blocking mode - * 0b1..FIFO 0 overwrite mode - */ -#define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK) -/*! @} */ - -/*! @name RXF0S - Rx FIFO 0 Status */ -/*! @{ */ - -#define CAN_RXF0S_F0FL_MASK (0x7FU) -#define CAN_RXF0S_F0FL_SHIFT (0U) -/*! F0FL - Rx FIFO 0 Fill Level - */ -#define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK) - -#define CAN_RXF0S_F0GI_MASK (0x3F00U) -#define CAN_RXF0S_F0GI_SHIFT (8U) -/*! F0GI - Rx FIFO 0 Get Index - */ -#define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK) - -#define CAN_RXF0S_F0PI_MASK (0x3F0000U) -#define CAN_RXF0S_F0PI_SHIFT (16U) -/*! F0PI - Rx FIFO 0 Put Index - */ -#define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK) - -#define CAN_RXF0S_F0F_MASK (0x1000000U) -#define CAN_RXF0S_F0F_SHIFT (24U) -/*! F0F - Rx FIFO 0 Full - * 0b0..Rx FIFO 0 not full - * 0b1..Rx FIFO 0 full - */ -#define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK) - -#define CAN_RXF0S_RF0L_MASK (0x2000000U) -#define CAN_RXF0S_RF0L_SHIFT (25U) -/*! RF0L - Rx FIFO 0 Message Lost - */ -#define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK) -/*! @} */ - -/*! @name RXF0A - Rx FIFO 0 Acknowledge */ -/*! @{ */ - -#define CAN_RXF0A_F0AI_MASK (0x3FU) -#define CAN_RXF0A_F0AI_SHIFT (0U) -/*! F0AI - Rx FIFO 0 Acknowledge Index - */ -#define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK) -/*! @} */ - -/*! @name RXBC - Rx Buffer Configuration */ -/*! @{ */ - -#define CAN_RXBC_RBSA_MASK (0xFFFCU) -#define CAN_RXBC_RBSA_SHIFT (2U) -/*! RBSA - Rx Buffer Start Address - */ -#define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK) -/*! @} */ - -/*! @name RXF1C - Rx FIFO 1 Configuration */ -/*! @{ */ - -#define CAN_RXF1C_F1SA_MASK (0xFFFCU) -#define CAN_RXF1C_F1SA_SHIFT (2U) -/*! F1SA - Rx FIFO 1 Start Address - */ -#define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK) - -#define CAN_RXF1C_F1S_MASK (0x7F0000U) -#define CAN_RXF1C_F1S_SHIFT (16U) -/*! F1S - Rx FIFO 1 Size - */ -#define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK) - -#define CAN_RXF1C_F1WM_MASK (0x7F000000U) -#define CAN_RXF1C_F1WM_SHIFT (24U) -/*! F1WM - Rx FIFO 1 Watermark - */ -#define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK) - -#define CAN_RXF1C_F1OM_MASK (0x80000000U) -#define CAN_RXF1C_F1OM_SHIFT (31U) -/*! F1OM - FIFO 1 Operation Mode - * 0b0..FIFO 1 blocking mode - * 0b1..FIFO 1 overwrite mode - */ -#define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK) -/*! @} */ - -/*! @name RXF1S - Rx FIFO 1 Status */ -/*! @{ */ - -#define CAN_RXF1S_F1FL_MASK (0x7FU) -#define CAN_RXF1S_F1FL_SHIFT (0U) -/*! F1FL - Rx FIFO 1 Fill Level - */ -#define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK) - -#define CAN_RXF1S_F1GI_MASK (0x3F00U) -#define CAN_RXF1S_F1GI_SHIFT (8U) -/*! F1GI - Rx FIFO 1 Get Index - */ -#define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK) - -#define CAN_RXF1S_F1PI_MASK (0x3F0000U) -#define CAN_RXF1S_F1PI_SHIFT (16U) -/*! F1PI - Rx FIFO 1 Put Index - */ -#define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK) - -#define CAN_RXF1S_F1F_MASK (0x1000000U) -#define CAN_RXF1S_F1F_SHIFT (24U) -/*! F1F - Rx FIFO 1 Full - * 0b0..Rx FIFO 1 not full - * 0b1..Rx FIFO 1 full - */ -#define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK) - -#define CAN_RXF1S_RF1L_MASK (0x2000000U) -#define CAN_RXF1S_RF1L_SHIFT (25U) -/*! RF1L - Rx FIFO 1 message lost. - * 0b0..No Rx FIFO 1 message lost. - * 0b1..Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero. - */ -#define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK) -/*! @} */ - -/*! @name RXF1A - Rx FIFO 1 Acknowledge */ -/*! @{ */ - -#define CAN_RXF1A_F1AI_MASK (0x3FU) -#define CAN_RXF1A_F1AI_SHIFT (0U) -/*! F1AI - Rx FIFO 1 Acknowledge Index - */ -#define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK) -/*! @} */ - -/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */ -/*! @{ */ - -#define CAN_RXESC_F0DS_MASK (0x7U) -#define CAN_RXESC_F0DS_SHIFT (0U) -/*! F0DS - Rx FIFO 0 Data Field Size - * 0b000..8 byte data field - * 0b001..12 byte data field - * 0b010..16 byte data field - * 0b011..20 byte data field - * 0b100..24 byte data field - * 0b101..32 byte data field - * 0b110..48 byte data field - * 0b111..64 byte data field - */ -#define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK) - -#define CAN_RXESC_F1DS_MASK (0x70U) -#define CAN_RXESC_F1DS_SHIFT (4U) -/*! F1DS - Rx FIFO 1 Data Field Size - * 0b000..8 byte data field - * 0b001..12 byte data field - * 0b010..16 byte data field - * 0b011..20 byte data field - * 0b100..24 byte data field - * 0b101..32 byte data field - * 0b110..48 byte data field - * 0b111..64 byte data field - */ -#define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK) - -#define CAN_RXESC_RBDS_MASK (0x700U) -#define CAN_RXESC_RBDS_SHIFT (8U) -/*! RBDS - Rx Buffer Data Field Size - * 0b000..8 byte data field - * 0b001..12 byte data field - * 0b010..16 byte data field - * 0b011..20 byte data field - * 0b100..24 byte data field - * 0b101..32 byte data field - * 0b110..48 byte data field - * 0b111..64 byte data field - */ -#define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK) -/*! @} */ - -/*! @name TXBC - Tx Buffer Configuration */ -/*! @{ */ - -#define CAN_TXBC_TBSA_MASK (0xFFFCU) -#define CAN_TXBC_TBSA_SHIFT (2U) -/*! TBSA - Tx Buffers Start Address - */ -#define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK) - -#define CAN_TXBC_NDTB_MASK (0x3F0000U) -#define CAN_TXBC_NDTB_SHIFT (16U) -/*! NDTB - Number of Dedicated Transmit Buffers - */ -#define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK) - -#define CAN_TXBC_TFQS_MASK (0x3F000000U) -#define CAN_TXBC_TFQS_SHIFT (24U) -/*! TFQS - Transmit FIFO/Queue Size - */ -#define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK) - -#define CAN_TXBC_TFQM_MASK (0x40000000U) -#define CAN_TXBC_TFQM_SHIFT (30U) -/*! TFQM - Tx FIFO/Queue Mode - * 0b0..Tx FIFO operation - * 0b1..Tx queue operation - */ -#define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK) -/*! @} */ - -/*! @name TXFQS - Tx FIFO/Queue Status */ -/*! @{ */ - -#define CAN_TXFQS_TFGI_MASK (0x1F00U) -#define CAN_TXFQS_TFGI_SHIFT (8U) -/*! TFGI - Tx FIFO Get Index - */ -#define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK) - -#define CAN_TXFQS_TFQPI_MASK (0x1F0000U) -#define CAN_TXFQS_TFQPI_SHIFT (16U) -/*! TFQPI - Tx FIFO/Queue Put Index - */ -#define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK) - -#define CAN_TXFQS_TFQF_MASK (0x200000U) -#define CAN_TXFQS_TFQF_SHIFT (21U) -/*! TFQF - Tx FIFO/Queue Full - * 0b0..Tx FIFO/Queue not full - * 0b1..Tx FIFO/Queue full - */ -#define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK) -/*! @} */ - -/*! @name TXESC - Tx Buffer Element Size Configuration */ -/*! @{ */ - -#define CAN_TXESC_TBDS_MASK (0x7U) -#define CAN_TXESC_TBDS_SHIFT (0U) -/*! TBDS - Tx Buffer Data Field Size - * 0b000..8 byte data field - * 0b001..12 byte data field - * 0b010..16 byte data field - * 0b011..20 byte data field - * 0b100..24 byte data field - * 0b101..32 byte data field - * 0b110..48 byte data field - * 0b111..64 byte data field - */ -#define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK) -/*! @} */ - -/*! @name TXBRP - Tx Buffer Request Pending */ -/*! @{ */ - -#define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU) -#define CAN_TXBRP_TRP_SHIFT (0U) -/*! TRP - Transmission Request Pending - */ -#define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK) -/*! @} */ - -/*! @name TXBAR - Tx Buffer Add Request */ -/*! @{ */ - -#define CAN_TXBAR_AR_MASK (0xFFFFFFFFU) -#define CAN_TXBAR_AR_SHIFT (0U) -/*! AR - Add Request - */ -#define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK) -/*! @} */ - -/*! @name TXBCR - Tx Buffer Cancellation Request */ -/*! @{ */ - -#define CAN_TXBCR_CR_MASK (0xFFFFFFFFU) -#define CAN_TXBCR_CR_SHIFT (0U) -/*! CR - Cancellation Request - */ -#define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK) -/*! @} */ - -/*! @name TXBTO - Tx Buffer Transmission Occurred */ -/*! @{ */ - -#define CAN_TXBTO_TO_MASK (0xFFFFFFFFU) -#define CAN_TXBTO_TO_SHIFT (0U) -/*! TO - Transmission Occurred - */ -#define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK) -/*! @} */ - -/*! @name TXBCF - Tx Buffer Cancellation Finished */ -/*! @{ */ - -#define CAN_TXBCF_TO_MASK (0xFFFFFFFFU) -#define CAN_TXBCF_TO_SHIFT (0U) -/*! TO - Cancellation Finished - */ -#define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK) -/*! @} */ - -/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */ -/*! @{ */ - -#define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU) -#define CAN_TXBTIE_TIE_SHIFT (0U) -/*! TIE - Transmission Interrupt Enable - */ -#define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK) -/*! @} */ - -/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */ -/*! @{ */ - -#define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU) -#define CAN_TXBCIE_CFIE_SHIFT (0U) -/*! CFIE - Cancellation Finished Interrupt Enable - */ -#define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK) -/*! @} */ - -/*! @name TXEFC - Tx Event FIFO Configuration */ -/*! @{ */ - -#define CAN_TXEFC_EFSA_MASK (0xFFFCU) -#define CAN_TXEFC_EFSA_SHIFT (2U) -/*! EFSA - Event FIFO Start Address - */ -#define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK) - -#define CAN_TXEFC_EFS_MASK (0x3F0000U) -#define CAN_TXEFC_EFS_SHIFT (16U) -/*! EFS - Event FIFO Size - */ -#define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK) - -#define CAN_TXEFC_EFWM_MASK (0x3F000000U) -#define CAN_TXEFC_EFWM_SHIFT (24U) -/*! EFWM - Event FIFO Watermark - */ -#define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK) -/*! @} */ - -/*! @name TXEFS - Tx Event FIFO Status */ -/*! @{ */ - -#define CAN_TXEFS_EFFL_MASK (0x3FU) -#define CAN_TXEFS_EFFL_SHIFT (0U) -/*! EFFL - Event FIFO Fill Level - */ -#define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK) - -#define CAN_TXEFS_EFGI_MASK (0x1F00U) -#define CAN_TXEFS_EFGI_SHIFT (8U) -/*! EFGI - Event FIFO Get Index - */ -#define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK) - -#define CAN_TXEFS_EFPI_MASK (0x3F0000U) -#define CAN_TXEFS_EFPI_SHIFT (16U) -/*! EFPI - Event FIFO Put Index - */ -#define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK) - -#define CAN_TXEFS_EFF_MASK (0x1000000U) -#define CAN_TXEFS_EFF_SHIFT (24U) -/*! EFF - Event FIFO Full - * 0b0..Tx event FIFO not full - * 0b1..Tx event FIFO full - */ -#define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK) - -#define CAN_TXEFS_TEFL_MASK (0x2000000U) -#define CAN_TXEFS_TEFL_SHIFT (25U) -/*! TEFL - Tx Event FIFO Element Lost - * 0b0..No Tx event FIFO element lost. - * 0b1..Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size zero. - */ -#define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK) -/*! @} */ - -/*! @name TXEFA - Tx Event FIFO Acknowledge */ -/*! @{ */ - -#define CAN_TXEFA_EFAI_MASK (0x1FU) -#define CAN_TXEFA_EFAI_SHIFT (0U) -/*! EFAI - Event FIFO Acknowledge Index - */ -#define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK) -/*! @} */ - -/*! @name MRBA - Message RAM Base Address */ -/*! @{ */ - -#define CAN_MRBA_BA_MASK (0xFFFF0000U) -#define CAN_MRBA_BA_SHIFT (16U) -/*! BA - Base Address for the message RAM in the chip memory map. - */ -#define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK) -/*! @} */ - -/*! @name ETSCC - External Timestamp Counter Configuration */ -/*! @{ */ - -#define CAN_ETSCC_ETCP_MASK (0x7FFU) -#define CAN_ETSCC_ETCP_SHIFT (0U) -/*! ETCP - External Timestamp Prescaler Value - */ -#define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK) - -#define CAN_ETSCC_ETCE_MASK (0x80000000U) -#define CAN_ETSCC_ETCE_SHIFT (31U) -/*! ETCE - External Timestamp Counter Enable - * 0b0..External timestamp counter is disabled - * 0b1..External timestamp counter is enabled - */ -#define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK) -/*! @} */ - -/*! @name ETSCV - External Timestamp Counter Value */ -/*! @{ */ - -#define CAN_ETSCV_ETSC_MASK (0xFFFFU) -#define CAN_ETSCV_ETSC_SHIFT (0U) -/*! ETSC - External Timestamp Counter - */ -#define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CAN_Register_Masks */ - - -/* CAN - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CAN0 base address */ - #define CAN0_BASE (0x5009D000u) - /** Peripheral CAN0 base address */ - #define CAN0_BASE_NS (0x4009D000u) - /** Peripheral CAN0 base pointer */ - #define CAN0 ((CAN_Type *)CAN0_BASE) - /** Peripheral CAN0 base pointer */ - #define CAN0_NS ((CAN_Type *)CAN0_BASE_NS) - /** Array initializer of CAN peripheral base addresses */ - #define CAN_BASE_ADDRS { CAN0_BASE } - /** Array initializer of CAN peripheral base pointers */ - #define CAN_BASE_PTRS { CAN0 } - /** Array initializer of CAN peripheral base addresses */ - #define CAN_BASE_ADDRS_NS { CAN0_BASE_NS } - /** Array initializer of CAN peripheral base pointers */ - #define CAN_BASE_PTRS_NS { CAN0_NS } -#else - /** Peripheral CAN0 base address */ - #define CAN0_BASE (0x4009D000u) - /** Peripheral CAN0 base pointer */ - #define CAN0 ((CAN_Type *)CAN0_BASE) - /** Array initializer of CAN peripheral base addresses */ - #define CAN_BASE_ADDRS { CAN0_BASE } - /** Array initializer of CAN peripheral base pointers */ - #define CAN_BASE_PTRS { CAN0 } -#endif -/** Interrupt vectors for the CAN peripheral type */ -#define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn } } - -/*! - * @} - */ /* end of group CAN_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CDOG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer - * @{ - */ - -/** CDOG - Register Layout Typedef */ -typedef struct { - __IO uint32_t CONTROL; /**< Control, offset: 0x0 */ - __IO uint32_t RELOAD; /**< Instruction Timer reload, offset: 0x4 */ - __I uint32_t INSTRUCTION_TIMER; /**< Instruction Timer, offset: 0x8 */ - __I uint32_t SECURE_COUNTER; /**< Secure Counter, offset: 0xC */ - __I uint32_t STATUS; /**< Status 1, offset: 0x10 */ - __I uint32_t STATUS2; /**< Status 2, offset: 0x14 */ - __IO uint32_t FLAGS; /**< Flags, offset: 0x18 */ - __IO uint32_t PERSISTENT; /**< Persistent Data Storage, offset: 0x1C */ - __O uint32_t START; /**< START Command, offset: 0x20 */ - __O uint32_t STOP; /**< STOP Command, offset: 0x24 */ - __O uint32_t RESTART; /**< RESTART Command, offset: 0x28 */ - __O uint32_t ADD; /**< ADD Command, offset: 0x2C */ - __O uint32_t ADD1; /**< ADD1 Command, offset: 0x30 */ - __O uint32_t ADD16; /**< ADD16 Command, offset: 0x34 */ - __O uint32_t ADD256; /**< ADD256 Command, offset: 0x38 */ - __O uint32_t SUB; /**< SUB Command, offset: 0x3C */ - __O uint32_t SUB1; /**< SUB1 Command, offset: 0x40 */ - __O uint32_t SUB16; /**< SUB16 Command, offset: 0x44 */ - __O uint32_t SUB256; /**< SUB256 Command, offset: 0x48 */ -} CDOG_Type; - -/* ---------------------------------------------------------------------------- - -- CDOG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CDOG_Register_Masks CDOG Register Masks - * @{ - */ - -/*! @name CONTROL - Control */ -/*! @{ */ - -#define CDOG_CONTROL_LOCK_CTRL_MASK (0x3U) -#define CDOG_CONTROL_LOCK_CTRL_SHIFT (0U) -/*! LOCK_CTRL - Lock control - * 0b01..Locked - * 0b10..Unlocked - */ -#define CDOG_CONTROL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK) - -#define CDOG_CONTROL_TIMEOUT_CTRL_MASK (0x1CU) -#define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT (2U) -/*! TIMEOUT_CTRL - TIMEOUT fault control - * 0b100..Disable both reset and interrupt - * 0b001..Enable reset - * 0b010..Enable interrupt - */ -#define CDOG_CONTROL_TIMEOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK) - -#define CDOG_CONTROL_MISCOMPARE_CTRL_MASK (0xE0U) -#define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT (5U) -/*! MISCOMPARE_CTRL - MISCOMPARE fault control - * 0b100..Disable both reset and interrupt - * 0b001..Enable reset - * 0b010..Enable interrupt - */ -#define CDOG_CONTROL_MISCOMPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK) - -#define CDOG_CONTROL_SEQUENCE_CTRL_MASK (0x700U) -#define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT (8U) -/*! SEQUENCE_CTRL - SEQUENCE fault control - * 0b001..Enable reset - * 0b010..Enable interrupt - * 0b100..Disable both reset and interrupt - */ -#define CDOG_CONTROL_SEQUENCE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK) - -#define CDOG_CONTROL_STATE_CTRL_MASK (0x1C000U) -#define CDOG_CONTROL_STATE_CTRL_SHIFT (14U) -/*! STATE_CTRL - STATE fault control - * 0b001..Enable reset - * 0b010..Enable interrupt - * 0b100..Disable both reset and interrupt - */ -#define CDOG_CONTROL_STATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK) - -#define CDOG_CONTROL_ADDRESS_CTRL_MASK (0xE0000U) -#define CDOG_CONTROL_ADDRESS_CTRL_SHIFT (17U) -/*! ADDRESS_CTRL - ADDRESS fault control - * 0b001..Enable reset - * 0b010..Enable interrupt - * 0b100..Disable both reset and interrupt - */ -#define CDOG_CONTROL_ADDRESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK) - -#define CDOG_CONTROL_IRQ_PAUSE_MASK (0x30000000U) -#define CDOG_CONTROL_IRQ_PAUSE_SHIFT (28U) -/*! IRQ_PAUSE - IRQ pause control - * 0b01..Keep the timer running - * 0b10..Stop the timer - */ -#define CDOG_CONTROL_IRQ_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK) - -#define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK (0xC0000000U) -#define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT (30U) -/*! DEBUG_HALT_CTRL - DEBUG_HALT control - * 0b01..Keep the timer running - * 0b10..Stop the timer - */ -#define CDOG_CONTROL_DEBUG_HALT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK) -/*! @} */ - -/*! @name RELOAD - Instruction Timer reload */ -/*! @{ */ - -#define CDOG_RELOAD_RLOAD_MASK (0xFFFFFFFFU) -#define CDOG_RELOAD_RLOAD_SHIFT (0U) -/*! RLOAD - Instruction Timer reload value - */ -#define CDOG_RELOAD_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK) -/*! @} */ - -/*! @name INSTRUCTION_TIMER - Instruction Timer */ -/*! @{ */ - -#define CDOG_INSTRUCTION_TIMER_INSTIM_MASK (0xFFFFFFFFU) -#define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT (0U) -/*! INSTIM - Current value of the Instruction Timer - */ -#define CDOG_INSTRUCTION_TIMER_INSTIM(x) (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK) -/*! @} */ - -/*! @name SECURE_COUNTER - Secure Counter */ -/*! @{ */ - -#define CDOG_SECURE_COUNTER_SECCNT_MASK (0xFFFFFFFFU) -#define CDOG_SECURE_COUNTER_SECCNT_SHIFT (0U) -/*! SECCNT - Secure Counter - */ -#define CDOG_SECURE_COUNTER_SECCNT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SECURE_COUNTER_SECCNT_SHIFT)) & CDOG_SECURE_COUNTER_SECCNT_MASK) -/*! @} */ - -/*! @name STATUS - Status 1 */ -/*! @{ */ - -#define CDOG_STATUS_NUMTOF_MASK (0xFFU) -#define CDOG_STATUS_NUMTOF_SHIFT (0U) -/*! NUMTOF - Number of TIMEOUT faults since the last POR - */ -#define CDOG_STATUS_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK) - -#define CDOG_STATUS_NUMMISCOMPF_MASK (0xFF00U) -#define CDOG_STATUS_NUMMISCOMPF_SHIFT (8U) -/*! NUMMISCOMPF - Number of MISCOMPARE faults since the last POR - */ -#define CDOG_STATUS_NUMMISCOMPF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK) - -#define CDOG_STATUS_NUMILSEQF_MASK (0xFF0000U) -#define CDOG_STATUS_NUMILSEQF_SHIFT (16U) -/*! NUMILSEQF - Number of SEQUENCE faults since the last POR - */ -#define CDOG_STATUS_NUMILSEQF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK) - -#define CDOG_STATUS_CURST_MASK (0xF0000000U) -#define CDOG_STATUS_CURST_SHIFT (28U) -/*! CURST - Current State - */ -#define CDOG_STATUS_CURST(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK) -/*! @} */ - -/*! @name STATUS2 - Status 2 */ -/*! @{ */ - -#define CDOG_STATUS2_NUMCNTF_MASK (0xFFU) -#define CDOG_STATUS2_NUMCNTF_SHIFT (0U) -/*! NUMCNTF - Number of CONTROL faults since the last POR - */ -#define CDOG_STATUS2_NUMCNTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK) - -#define CDOG_STATUS2_NUMILLSTF_MASK (0xFF00U) -#define CDOG_STATUS2_NUMILLSTF_SHIFT (8U) -/*! NUMILLSTF - Number of STATE faults since the last POR - */ -#define CDOG_STATUS2_NUMILLSTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK) - -#define CDOG_STATUS2_NUMILLA_MASK (0xFF0000U) -#define CDOG_STATUS2_NUMILLA_SHIFT (16U) -/*! NUMILLA - Number of ADDRESS faults since the last POR - */ -#define CDOG_STATUS2_NUMILLA(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK) -/*! @} */ - -/*! @name FLAGS - Flags */ -/*! @{ */ - -#define CDOG_FLAGS_TO_FLAG_MASK (0x1U) -#define CDOG_FLAGS_TO_FLAG_SHIFT (0U) -/*! TO_FLAG - TIMEOUT fault flag - * 0b0..A TIMEOUT fault has not occurred - * 0b1..A TIMEOUT fault has occurred - */ -#define CDOG_FLAGS_TO_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK) - -#define CDOG_FLAGS_MISCOM_FLAG_MASK (0x2U) -#define CDOG_FLAGS_MISCOM_FLAG_SHIFT (1U) -/*! MISCOM_FLAG - MISCOMPARE fault flag - * 0b0..A MISCOMPARE fault has not occurred - * 0b1..A MISCOMPARE fault has occurred - */ -#define CDOG_FLAGS_MISCOM_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK) - -#define CDOG_FLAGS_SEQ_FLAG_MASK (0x4U) -#define CDOG_FLAGS_SEQ_FLAG_SHIFT (2U) -/*! SEQ_FLAG - SEQUENCE fault flag - * 0b0..A SEQUENCE fault has not occurred - * 0b1..A SEQUENCE fault has occurred - */ -#define CDOG_FLAGS_SEQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK) - -#define CDOG_FLAGS_CNT_FLAG_MASK (0x8U) -#define CDOG_FLAGS_CNT_FLAG_SHIFT (3U) -/*! CNT_FLAG - CONTROL fault flag - * 0b0..A CONTROL fault has not occurred - * 0b1..A CONTROL fault has occurred - */ -#define CDOG_FLAGS_CNT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK) - -#define CDOG_FLAGS_STATE_FLAG_MASK (0x10U) -#define CDOG_FLAGS_STATE_FLAG_SHIFT (4U) -/*! STATE_FLAG - STATE fault flag - * 0b0..A STATE fault has not occurred - * 0b1..A STATE fault has occurred - */ -#define CDOG_FLAGS_STATE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK) - -#define CDOG_FLAGS_ADDR_FLAG_MASK (0x20U) -#define CDOG_FLAGS_ADDR_FLAG_SHIFT (5U) -/*! ADDR_FLAG - ADDRESS fault flag - * 0b0..An ADDRESS fault has not occurred - * 0b1..An ADDRESS fault has occurred - */ -#define CDOG_FLAGS_ADDR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK) - -#define CDOG_FLAGS_POR_FLAG_MASK (0x10000U) -#define CDOG_FLAGS_POR_FLAG_SHIFT (16U) -/*! POR_FLAG - Power-on reset flag - * 0b0..A Power-on reset event has not occurred - * 0b1..A Power-on reset event has occurred - */ -#define CDOG_FLAGS_POR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK) -/*! @} */ - -/*! @name PERSISTENT - Persistent Data Storage */ -/*! @{ */ - -#define CDOG_PERSISTENT_PERSIS_MASK (0xFFFFFFFFU) -#define CDOG_PERSISTENT_PERSIS_SHIFT (0U) -/*! PERSIS - Persistent Storage - */ -#define CDOG_PERSISTENT_PERSIS(x) (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK) -/*! @} */ - -/*! @name START - START Command */ -/*! @{ */ - -#define CDOG_START_STRT_MASK (0xFFFFFFFFU) -#define CDOG_START_STRT_SHIFT (0U) -/*! STRT - Start command - */ -#define CDOG_START_STRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK) -/*! @} */ - -/*! @name STOP - STOP Command */ -/*! @{ */ - -#define CDOG_STOP_STP_MASK (0xFFFFFFFFU) -#define CDOG_STOP_STP_SHIFT (0U) -/*! STP - Stop command - */ -#define CDOG_STOP_STP(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK) -/*! @} */ - -/*! @name RESTART - RESTART Command */ -/*! @{ */ - -#define CDOG_RESTART_RSTRT_MASK (0xFFFFFFFFU) -#define CDOG_RESTART_RSTRT_SHIFT (0U) -/*! RSTRT - Restart command - */ -#define CDOG_RESTART_RSTRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK) -/*! @} */ - -/*! @name ADD - ADD Command */ -/*! @{ */ - -#define CDOG_ADD_AD_MASK (0xFFFFFFFFU) -#define CDOG_ADD_AD_SHIFT (0U) -/*! AD - ADD Write Value - */ -#define CDOG_ADD_AD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK) -/*! @} */ - -/*! @name ADD1 - ADD1 Command */ -/*! @{ */ - -#define CDOG_ADD1_AD1_MASK (0xFFFFFFFFU) -#define CDOG_ADD1_AD1_SHIFT (0U) -/*! AD1 - ADD 1 - */ -#define CDOG_ADD1_AD1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK) -/*! @} */ - -/*! @name ADD16 - ADD16 Command */ -/*! @{ */ - -#define CDOG_ADD16_AD16_MASK (0xFFFFFFFFU) -#define CDOG_ADD16_AD16_SHIFT (0U) -/*! AD16 - ADD 16 - */ -#define CDOG_ADD16_AD16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK) -/*! @} */ - -/*! @name ADD256 - ADD256 Command */ -/*! @{ */ - -#define CDOG_ADD256_AD256_MASK (0xFFFFFFFFU) -#define CDOG_ADD256_AD256_SHIFT (0U) -/*! AD256 - ADD 256 - */ -#define CDOG_ADD256_AD256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK) -/*! @} */ - -/*! @name SUB - SUB Command */ -/*! @{ */ - -#define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) -#define CDOG_SUB_S0B_SHIFT (0U) -/*! S0B - Subtract Write Value - */ -#define CDOG_SUB_S0B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK) -/*! @} */ - -/*! @name SUB1 - SUB1 Command */ -/*! @{ */ - -#define CDOG_SUB1_S1B_MASK (0xFFFFFFFFU) -#define CDOG_SUB1_S1B_SHIFT (0U) -/*! S1B - Subtract 1 - */ -#define CDOG_SUB1_S1B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_S1B_SHIFT)) & CDOG_SUB1_S1B_MASK) -/*! @} */ - -/*! @name SUB16 - SUB16 Command */ -/*! @{ */ - -#define CDOG_SUB16_SB16_MASK (0xFFFFFFFFU) -#define CDOG_SUB16_SB16_SHIFT (0U) -/*! SB16 - Subtract 16 - */ -#define CDOG_SUB16_SB16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK) -/*! @} */ - -/*! @name SUB256 - SUB256 Command */ -/*! @{ */ - -#define CDOG_SUB256_SB256_MASK (0xFFFFFFFFU) -#define CDOG_SUB256_SB256_SHIFT (0U) -/*! SB256 - Subtract 256 - */ -#define CDOG_SUB256_SB256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CDOG_Register_Masks */ - - -/* CDOG - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CDOG base address */ - #define CDOG_BASE (0x500A1000u) - /** Peripheral CDOG base address */ - #define CDOG_BASE_NS (0x400A1000u) - /** Peripheral CDOG base pointer */ - #define CDOG ((CDOG_Type *)CDOG_BASE) - /** Peripheral CDOG base pointer */ - #define CDOG_NS ((CDOG_Type *)CDOG_BASE_NS) - /** Array initializer of CDOG peripheral base addresses */ - #define CDOG_BASE_ADDRS { CDOG_BASE } - /** Array initializer of CDOG peripheral base pointers */ - #define CDOG_BASE_PTRS { CDOG } - /** Array initializer of CDOG peripheral base addresses */ - #define CDOG_BASE_ADDRS_NS { CDOG_BASE_NS } - /** Array initializer of CDOG peripheral base pointers */ - #define CDOG_BASE_PTRS_NS { CDOG_NS } -#else - /** Peripheral CDOG base address */ - #define CDOG_BASE (0x400A1000u) - /** Peripheral CDOG base pointer */ - #define CDOG ((CDOG_Type *)CDOG_BASE) - /** Array initializer of CDOG peripheral base addresses */ - #define CDOG_BASE_ADDRS { CDOG_BASE } - /** Array initializer of CDOG peripheral base pointers */ - #define CDOG_BASE_PTRS { CDOG } -#endif -/** Interrupt vectors for the CDOG peripheral type */ -#define CDOG_IRQS { CDOG_IRQn } - -/*! - * @} - */ /* end of group CDOG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CRC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer - * @{ - */ - -/** CRC - Register Layout Typedef */ -typedef struct { - union { /* offset: 0x0 */ - struct { /* offset: 0x0 */ - __IO uint8_t DATALL; /**< CRC_DATALL register, offset: 0x0 */ - __IO uint8_t DATALU; /**< CRC_DATALU register, offset: 0x1 */ - __IO uint8_t DATAHL; /**< CRC_DATAHL register, offset: 0x2 */ - __IO uint8_t DATAHU; /**< CRC_DATAHU register, offset: 0x3 */ - } ACCESS8BIT; - struct { /* offset: 0x0 */ - __IO uint16_t DATAL; /**< CRC_DATAL register, offset: 0x0 */ - __IO uint16_t DATAH; /**< CRC_DATAH register, offset: 0x2 */ - } ACCESS16BIT; - __IO uint32_t DATA; /**< CRC DATA register, offset: 0x0 */ - }; - union { /* offset: 0x4 */ - struct { /* offset: 0x4 */ - __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register, offset: 0x4 */ - __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register, offset: 0x5 */ - __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register, offset: 0x6 */ - __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register, offset: 0x7 */ - } GPOLY_ACCESS8BIT; - struct { /* offset: 0x4 */ - __IO uint16_t GPOLYL; /**< CRC_GPOLYL register, offset: 0x4 */ - __IO uint16_t GPOLYH; /**< CRC_GPOLYH register, offset: 0x6 */ - } GPOLY_ACCESS16BIT; - __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ - }; - union { /* offset: 0x8 */ - struct { /* offset: 0x8 */ - uint8_t RESERVED_0[3]; - __IO uint8_t CTRLHU; /**< CRC_CTRLHU register, offset: 0xB */ - } CTRL_ACCESS8BIT; - __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ - }; -} CRC_Type; - -/* ---------------------------------------------------------------------------- - -- CRC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Register_Masks CRC Register Masks - * @{ - */ - -/*! @name DATALL - CRC_DATALL register */ -/*! @{ */ - -#define CRC_DATALL_DATALL_MASK (0xFFU) -#define CRC_DATALL_DATALL_SHIFT (0U) -#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) -/*! @} */ - -/*! @name DATALU - CRC_DATALU register */ -/*! @{ */ - -#define CRC_DATALU_DATALU_MASK (0xFFU) -#define CRC_DATALU_DATALU_SHIFT (0U) -#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) -/*! @} */ - -/*! @name DATAHL - CRC_DATAHL register */ -/*! @{ */ - -#define CRC_DATAHL_DATAHL_MASK (0xFFU) -#define CRC_DATAHL_DATAHL_SHIFT (0U) -#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) -/*! @} */ - -/*! @name DATAHU - CRC_DATAHU register */ -/*! @{ */ - -#define CRC_DATAHU_DATAHU_MASK (0xFFU) -#define CRC_DATAHU_DATAHU_SHIFT (0U) -#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) -/*! @} */ - -/*! @name DATAL - CRC_DATAL register */ -/*! @{ */ - -#define CRC_DATAL_DATAL_MASK (0xFFFFU) -#define CRC_DATAL_DATAL_SHIFT (0U) -#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) -/*! @} */ - -/*! @name DATAH - CRC_DATAH register */ -/*! @{ */ - -#define CRC_DATAH_DATAH_MASK (0xFFFFU) -#define CRC_DATAH_DATAH_SHIFT (0U) -#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) -/*! @} */ - -/*! @name DATA - CRC DATA register */ -/*! @{ */ - -#define CRC_DATA_LL_MASK (0xFFU) -#define CRC_DATA_LL_SHIFT (0U) -/*! LL - CRC Low Lower Byte - */ -#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) - -#define CRC_DATA_LU_MASK (0xFF00U) -#define CRC_DATA_LU_SHIFT (8U) -/*! LU - CRC Low Upper Byte - */ -#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) - -#define CRC_DATA_HL_MASK (0xFF0000U) -#define CRC_DATA_HL_SHIFT (16U) -/*! HL - CRC High Lower Byte - */ -#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) - -#define CRC_DATA_HU_MASK (0xFF000000U) -#define CRC_DATA_HU_SHIFT (24U) -/*! HU - CRC High Upper Byte - */ -#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) -/*! @} */ - -/*! @name GPOLYLL - CRC_GPOLYLL register */ -/*! @{ */ - -#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) -#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) -#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) -/*! @} */ - -/*! @name GPOLYLU - CRC_GPOLYLU register */ -/*! @{ */ - -#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) -#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) -#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) -/*! @} */ - -/*! @name GPOLYHL - CRC_GPOLYHL register */ -/*! @{ */ - -#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) -#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) -#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) -/*! @} */ - -/*! @name GPOLYHU - CRC_GPOLYHU register */ -/*! @{ */ - -#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) -#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) -#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) -/*! @} */ - -/*! @name GPOLYL - CRC_GPOLYL register */ -/*! @{ */ - -#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) -#define CRC_GPOLYL_GPOLYL_SHIFT (0U) -#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) -/*! @} */ - -/*! @name GPOLYH - CRC_GPOLYH register */ -/*! @{ */ - -#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) -#define CRC_GPOLYH_GPOLYH_SHIFT (0U) -#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) -/*! @} */ - -/*! @name GPOLY - CRC Polynomial register */ -/*! @{ */ - -#define CRC_GPOLY_LOW_MASK (0xFFFFU) -#define CRC_GPOLY_LOW_SHIFT (0U) -/*! LOW - Low Polynominal Half-word - */ -#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) - -#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) -#define CRC_GPOLY_HIGH_SHIFT (16U) -/*! HIGH - High Polynominal Half-word - */ -#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) -/*! @} */ - -/*! @name CTRLHU - CRC_CTRLHU register */ -/*! @{ */ - -#define CRC_CTRLHU_TCRC_MASK (0x1U) -#define CRC_CTRLHU_TCRC_SHIFT (0U) -/*! TCRC - TCRC - * 0b0..16-bit CRC protocol. - * 0b1..32-bit CRC protocol. - */ -#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) - -#define CRC_CTRLHU_WAS_MASK (0x2U) -#define CRC_CTRLHU_WAS_SHIFT (1U) -/*! WAS - Write CRC DATA register As Seed - * 0b0..Writes to the CRC DATA register are data values. - * 0b1..Writes to the CRC DATA register are seed values. - */ -#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) - -#define CRC_CTRLHU_FXOR_MASK (0x4U) -#define CRC_CTRLHU_FXOR_SHIFT (2U) -/*! FXOR - Complement Read Of CRC DATA register - * 0b0..No XOR on reading. - * 0b1..Invert or complement the read value of the CRC DATA register. - */ -#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) - -#define CRC_CTRLHU_TOTR_MASK (0x30U) -#define CRC_CTRLHU_TOTR_SHIFT (4U) -/*! TOTR - Type Of Transpose For Read - * 0b00..No transposition. - * 0b01..Bits in bytes are transposed; bytes are not transposed. - * 0b10..Both bits in bytes and bytes are transposed. - * 0b11..Only bytes are transposed; no bits in a byte are transposed. - */ -#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) - -#define CRC_CTRLHU_TOT_MASK (0xC0U) -#define CRC_CTRLHU_TOT_SHIFT (6U) -/*! TOT - Type Of Transpose For Writes - * 0b00..No transposition. - * 0b01..Bits in bytes are transposed; bytes are not transposed. - * 0b10..Both bits in bytes and bytes are transposed. - * 0b11..Only bytes are transposed; no bits in a byte are transposed. - */ -#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) -/*! @} */ - -/*! @name CTRL - CRC Control register */ -/*! @{ */ - -#define CRC_CTRL_TCRC_MASK (0x1000000U) -#define CRC_CTRL_TCRC_SHIFT (24U) -/*! TCRC - TCRC - * 0b0..16-bit CRC protocol. - * 0b1..32-bit CRC protocol. - */ -#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) - -#define CRC_CTRL_WAS_MASK (0x2000000U) -#define CRC_CTRL_WAS_SHIFT (25U) -/*! WAS - Write CRC DATA register As Seed - * 0b0..Writes to the CRC DATA register are data values. - * 0b1..Writes to the CRC DATA register are seed values. - */ -#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) - -#define CRC_CTRL_FXOR_MASK (0x4000000U) -#define CRC_CTRL_FXOR_SHIFT (26U) -/*! FXOR - Complement Read Of CRC DATA register - * 0b0..No XOR on reading. - * 0b1..Invert or complement the read value of the CRC DATA register. - */ -#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) - -#define CRC_CTRL_TOTR_MASK (0x30000000U) -#define CRC_CTRL_TOTR_SHIFT (28U) -/*! TOTR - Type Of Transpose For Read - * 0b00..No transposition. - * 0b01..Bits in bytes are transposed; bytes are not transposed. - * 0b10..Both bits in bytes and bytes are transposed. - * 0b11..Only bytes are transposed; no bits in a byte are transposed. - */ -#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) - -#define CRC_CTRL_TOT_MASK (0xC0000000U) -#define CRC_CTRL_TOT_SHIFT (30U) -/*! TOT - Type Of Transpose For Writes - * 0b00..No transposition. - * 0b01..Bits in bytes are transposed; bytes are not transposed. - * 0b10..Both bits in bytes and bytes are transposed. - * 0b11..Only bytes are transposed; no bits in a byte are transposed. - */ -#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CRC_Register_Masks */ - - -/* CRC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CRC0 base address */ - #define CRC0_BASE (0x50095000u) - /** Peripheral CRC0 base address */ - #define CRC0_BASE_NS (0x40095000u) - /** Peripheral CRC0 base pointer */ - #define CRC0 ((CRC_Type *)CRC0_BASE) - /** Peripheral CRC0 base pointer */ - #define CRC0_NS ((CRC_Type *)CRC0_BASE_NS) - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS { CRC0_BASE } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS { CRC0 } - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS_NS { CRC0_BASE_NS } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS_NS { CRC0_NS } -#else - /** Peripheral CRC0 base address */ - #define CRC0_BASE (0x40095000u) - /** Peripheral CRC0 base pointer */ - #define CRC0 ((CRC_Type *)CRC0_BASE) - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS { CRC0_BASE } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS { CRC0 } -#endif - -/*! - * @} - */ /* end of group CRC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CSS Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CSS_Peripheral_Access_Layer CSS Peripheral Access Layer - * @{ - */ - -/** CSS - Register Layout Typedef */ -typedef struct { - __I uint32_t CSS_STATUS; /**< Status register, offset: 0x0 */ - __IO uint32_t CSS_CTRL; /**< CSS Control register, offset: 0x4 */ - __IO uint32_t CSS_CMDCFG0; /**< CSS command configuration register, offset: 0x8 */ - __IO uint32_t CSS_CFG; /**< CSS configuration register, offset: 0xC */ - __IO uint32_t CSS_KIDX0; /**< Keystore index 0 - for commands that access a single key, offset: 0x10 */ - __IO uint32_t CSS_KIDX1; /**< Keystore index 1 - for commands that access 2 keys, offset: 0x14 */ - __IO uint32_t CSS_KPROPIN; /**< key properties request, offset: 0x18 */ - uint8_t RESERVED_0[4]; - __IO uint32_t CSS_DMA_SRC0; /**< CSS DMA Source 0, offset: 0x20 */ - __IO uint32_t CSS_DMA_SRC0_LEN; /**< CSS DMA Source 0 length, offset: 0x24 */ - __IO uint32_t CSS_DMA_SRC1; /**< CSS DMA Source 1, offset: 0x28 */ - uint8_t RESERVED_1[4]; - __IO uint32_t CSS_DMA_SRC2; /**< CSS DMA Source 2, offset: 0x30 */ - __IO uint32_t CSS_DMA_SRC2_LEN; /**< CSS DMA Source 2 length, offset: 0x34 */ - __IO uint32_t CSS_DMA_RES0; /**< CSS DMA Result 0, offset: 0x38 */ - __IO uint32_t CSS_DMA_RES0_LEN; /**< CSS DMA Result 0 Size, offset: 0x3C */ - __IO uint32_t CSS_INT_ENABLE; /**< Interrupt enable, offset: 0x40 */ - __O uint32_t CSS_INT_STATUS_CLR; /**< Interrupt status clear, offset: 0x44 */ - __O uint32_t CSS_INT_STATUS_SET; /**< Interrupt status set, offset: 0x48 */ - __I uint32_t CSS_ERR_STATUS; /**< Status register, offset: 0x4C */ - __O uint32_t CSS_ERR_STATUS_CLR; /**< Interrupt status clear, offset: 0x50 */ - __I uint32_t CSS_VERSION; /**< CSS Version, offset: 0x54 */ - uint8_t RESERVED_2[4]; - __I uint32_t CSS_PRNG_DATOUT; /**< PRNG SW read out register, offset: 0x5C */ - __I uint32_t CSS_GDET_EVTCNT; /**< CSS GDET Event Counter, offset: 0x60 */ - __O uint32_t CSS_GDET_EVTCNT_CLR; /**< CSS GDET Event Counter Clear, offset: 0x64 */ - uint8_t RESERVED_3[152]; - __I uint32_t CSS_SHA2_STATUS; /**< CSS SHA2 Status Register, offset: 0x100 */ - __IO uint32_t CSS_SHA2_CTRL; /**< SHA2 Control register, offset: 0x104 */ - __IO uint32_t CSS_SHA2_DIN; /**< CSS SHA_DATA IN Register 0, offset: 0x108 */ - __I uint32_t CSS_SHA2_DOUT0; /**< CSS CSS_SHA_DATA Out Register 0, offset: 0x10C */ - __I uint32_t CSS_SHA2_DOUT1; /**< CSS SHA_DATA Out Register 1, offset: 0x110 */ - __I uint32_t CSS_SHA2_DOUT2; /**< CSS SHA_DATA Out Register 2, offset: 0x114 */ - __I uint32_t CSS_SHA2_DOUT3; /**< CSS SHA_DATA Out Register 3, offset: 0x118 */ - __I uint32_t CSS_SHA2_DOUT4; /**< CSS SHA_DATA Out Register 4, offset: 0x11C */ - __I uint32_t CSS_SHA2_DOUT5; /**< CSS SHA_DATA Out Register 5, offset: 0x120 */ - __I uint32_t CSS_SHA2_DOUT6; /**< CSS SHA_DATA Out Register 6, offset: 0x124 */ - __I uint32_t CSS_SHA2_DOUT7; /**< CSS SHA_DATA Out Register 7, offset: 0x128 */ - __I uint32_t CSS_SHA2_DOUT8; /**< CSS CSS_SHA_DATA Out Register 8, offset: 0x12C */ - __I uint32_t CSS_SHA2_DOUT9; /**< CSS SHA_DATA Out Register 9, offset: 0x130 */ - __I uint32_t CSS_SHA2_DOUT10; /**< CSS SHA_DATA Out Register 10, offset: 0x134 */ - __I uint32_t CSS_SHA2_DOUT11; /**< CSS SHA_DATA Out Register 11, offset: 0x138 */ - __I uint32_t CSS_SHA2_DOUT12; /**< CSS SHA_DATA Out Register 12, offset: 0x13C */ - __I uint32_t CSS_SHA2_DOUT13; /**< CSS SHA_DATA Out Register 13, offset: 0x140 */ - __I uint32_t CSS_SHA2_DOUT14; /**< CSS SHA_DATA Out Register 14, offset: 0x144 */ - __I uint32_t CSS_SHA2_DOUT15; /**< CSS SHA_DATA Out Register 15, offset: 0x148 */ - uint8_t RESERVED_4[4]; - __I uint32_t CSS_KS0; /**< Status register, offset: 0x150 */ - __I uint32_t CSS_KS1; /**< Status register, offset: 0x154 */ - __I uint32_t CSS_KS2; /**< Status register, offset: 0x158 */ - __I uint32_t CSS_KS3; /**< Status register, offset: 0x15C */ - __I uint32_t CSS_KS4; /**< Status register, offset: 0x160 */ - __I uint32_t CSS_KS5; /**< Status register, offset: 0x164 */ - __I uint32_t CSS_KS6; /**< Status register, offset: 0x168 */ - __I uint32_t CSS_KS7; /**< Status register, offset: 0x16C */ - __I uint32_t CSS_KS8; /**< Status register, offset: 0x170 */ - __I uint32_t CSS_KS9; /**< Status register, offset: 0x174 */ - __I uint32_t CSS_KS10; /**< Status register, offset: 0x178 */ - __I uint32_t CSS_KS11; /**< Status register, offset: 0x17C */ - __I uint32_t CSS_KS12; /**< Status register, offset: 0x180 */ - __I uint32_t CSS_KS13; /**< Status register, offset: 0x184 */ - __I uint32_t CSS_KS14; /**< Status register, offset: 0x188 */ - __I uint32_t CSS_KS15; /**< Status register, offset: 0x18C */ - __I uint32_t CSS_KS16; /**< Status register, offset: 0x190 */ - __I uint32_t CSS_KS17; /**< Status register, offset: 0x194 */ - __I uint32_t CSS_KS18; /**< Status register, offset: 0x198 */ - __I uint32_t CSS_KS19; /**< Status register, offset: 0x19C */ -} CSS_Type; - -/* ---------------------------------------------------------------------------- - -- CSS Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CSS_Register_Masks CSS Register Masks - * @{ - */ - -/*! @name CSS_STATUS - Status register */ -/*! @{ */ - -#define CSS_CSS_STATUS_css_busy_MASK (0x1U) -#define CSS_CSS_STATUS_css_busy_SHIFT (0U) -/*! css_busy - High to indicate the CSS is executing a Crypto Sequence - */ -#define CSS_CSS_STATUS_css_busy(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_css_busy_SHIFT)) & CSS_CSS_STATUS_css_busy_MASK) - -#define CSS_CSS_STATUS_css_irq_MASK (0x2U) -#define CSS_CSS_STATUS_css_irq_SHIFT (1U) -/*! css_irq - High to indicate the CSS has an active interrupt - */ -#define CSS_CSS_STATUS_css_irq(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_css_irq_SHIFT)) & CSS_CSS_STATUS_css_irq_MASK) - -#define CSS_CSS_STATUS_css_err_MASK (0x4U) -#define CSS_CSS_STATUS_css_err_SHIFT (2U) -/*! css_err - High to indicate the CSS has detected an internal error - */ -#define CSS_CSS_STATUS_css_err(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_css_err_SHIFT)) & CSS_CSS_STATUS_css_err_MASK) - -#define CSS_CSS_STATUS_prng_rdy_MASK (0x8U) -#define CSS_CSS_STATUS_prng_rdy_SHIFT (3U) -/*! prng_rdy - High to indicate the internal PRNG is ready. SFR - */ -#define CSS_CSS_STATUS_prng_rdy(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_prng_rdy_SHIFT)) & CSS_CSS_STATUS_prng_rdy_MASK) - -#define CSS_CSS_STATUS_ecdsa_vfy_status_MASK (0x30U) -#define CSS_CSS_STATUS_ecdsa_vfy_status_SHIFT (4U) -/*! ecdsa_vfy_status - Signature Verify Result Status - */ -#define CSS_CSS_STATUS_ecdsa_vfy_status(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_ecdsa_vfy_status_SHIFT)) & CSS_CSS_STATUS_ecdsa_vfy_status_MASK) - -#define CSS_CSS_STATUS_pprot_MASK (0xC0U) -#define CSS_CSS_STATUS_pprot_SHIFT (6U) -/*! pprot - Current command privilege level - */ -#define CSS_CSS_STATUS_pprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_pprot_SHIFT)) & CSS_CSS_STATUS_pprot_MASK) - -#define CSS_CSS_STATUS_drbg_ent_lvl_MASK (0x300U) -#define CSS_CSS_STATUS_drbg_ent_lvl_SHIFT (8U) -/*! drbg_ent_lvl - Entropy quality of the current DRBG instance. This value - */ -#define CSS_CSS_STATUS_drbg_ent_lvl(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_drbg_ent_lvl_SHIFT)) & CSS_CSS_STATUS_drbg_ent_lvl_MASK) - -#define CSS_CSS_STATUS_dtrng_busy_MASK (0x400U) -#define CSS_CSS_STATUS_dtrng_busy_SHIFT (10U) -/*! dtrng_busy - When set, it indicates the DTRNG is gathering entropy - */ -#define CSS_CSS_STATUS_dtrng_busy(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_dtrng_busy_SHIFT)) & CSS_CSS_STATUS_dtrng_busy_MASK) - -#define CSS_CSS_STATUS_gdet_irq_pos_MASK (0x800U) -#define CSS_CSS_STATUS_gdet_irq_pos_SHIFT (11U) -/*! gdet_irq_pos - IRQ for GDET has detected a negative glitch: active high irq - */ -#define CSS_CSS_STATUS_gdet_irq_pos(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_gdet_irq_pos_SHIFT)) & CSS_CSS_STATUS_gdet_irq_pos_MASK) - -#define CSS_CSS_STATUS_gdet_irq_neg_MASK (0x1000U) -#define CSS_CSS_STATUS_gdet_irq_neg_SHIFT (12U) -/*! gdet_irq_neg - IRQ for GDET has detected a positive glitch: active high irq - */ -#define CSS_CSS_STATUS_gdet_irq_neg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_gdet_irq_neg_SHIFT)) & CSS_CSS_STATUS_gdet_irq_neg_MASK) - -#define CSS_CSS_STATUS_status_rsvd_MASK (0xFFFFE000U) -#define CSS_CSS_STATUS_status_rsvd_SHIFT (13U) -/*! status_rsvd - reserved - */ -#define CSS_CSS_STATUS_status_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_status_rsvd_SHIFT)) & CSS_CSS_STATUS_status_rsvd_MASK) -/*! @} */ - -/*! @name CSS_CTRL - CSS Control register */ -/*! @{ */ - -#define CSS_CSS_CTRL_css_en_MASK (0x1U) -#define CSS_CSS_CTRL_css_en_SHIFT (0U) -/*! css_en - CSS enable 0=CSS disabled, 1= CSS is enabled - */ -#define CSS_CSS_CTRL_css_en(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CTRL_css_en_SHIFT)) & CSS_CSS_CTRL_css_en_MASK) - -#define CSS_CSS_CTRL_css_start_MASK (0x2U) -#define CSS_CSS_CTRL_css_start_SHIFT (1U) -/*! css_start - Write to 1 to start a CSS Operation - */ -#define CSS_CSS_CTRL_css_start(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CTRL_css_start_SHIFT)) & CSS_CSS_CTRL_css_start_MASK) - -#define CSS_CSS_CTRL_css_reset_MASK (0x4U) -#define CSS_CSS_CTRL_css_reset_SHIFT (2U) -/*! css_reset - Write to 1 to perform a CSS synchronous Reset - */ -#define CSS_CSS_CTRL_css_reset(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CTRL_css_reset_SHIFT)) & CSS_CSS_CTRL_css_reset_MASK) - -#define CSS_CSS_CTRL_css_cmd_MASK (0xF8U) -#define CSS_CSS_CTRL_css_cmd_SHIFT (3U) -/*! css_cmd - CSS Command Field: List of Valid commands: - */ -#define CSS_CSS_CTRL_css_cmd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CTRL_css_cmd_SHIFT)) & CSS_CSS_CTRL_css_cmd_MASK) - -#define CSS_CSS_CTRL_byte_order_MASK (0x100U) -#define CSS_CSS_CTRL_byte_order_SHIFT (8U) -/*! byte_order - Defines Endianness - 1: BigEndian, 0: Little Endian - */ -#define CSS_CSS_CTRL_byte_order(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CTRL_byte_order_SHIFT)) & CSS_CSS_CTRL_byte_order_MASK) - -#define CSS_CSS_CTRL_ctrl_rfu_MASK (0xFFFFFE00U) -#define CSS_CSS_CTRL_ctrl_rfu_SHIFT (9U) -/*! ctrl_rfu - reserved - */ -#define CSS_CSS_CTRL_ctrl_rfu(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CTRL_ctrl_rfu_SHIFT)) & CSS_CSS_CTRL_ctrl_rfu_MASK) -/*! @} */ - -/*! @name CSS_CMDCFG0 - CSS command configuration register */ -/*! @{ */ - -#define CSS_CSS_CMDCFG0_cmdcfg0_MASK (0xFFFFFFFFU) -#define CSS_CSS_CMDCFG0_cmdcfg0_SHIFT (0U) -/*! cmdcfg0 - refer to reference manual for assignment of this field - */ -#define CSS_CSS_CMDCFG0_cmdcfg0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CMDCFG0_cmdcfg0_SHIFT)) & CSS_CSS_CMDCFG0_cmdcfg0_MASK) -/*! @} */ - -/*! @name CSS_CFG - CSS configuration register */ -/*! @{ */ - -#define CSS_CSS_CFG_cfg_rsvd0_MASK (0xFFFFU) -#define CSS_CSS_CFG_cfg_rsvd0_SHIFT (0U) -/*! cfg_rsvd0 - reserved - */ -#define CSS_CSS_CFG_cfg_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CFG_cfg_rsvd0_SHIFT)) & CSS_CSS_CFG_cfg_rsvd0_MASK) - -#define CSS_CSS_CFG_adctrl_MASK (0x3FF0000U) -#define CSS_CSS_CFG_adctrl_SHIFT (16U) -/*! adctrl - maximum aes start delay - */ -#define CSS_CSS_CFG_adctrl(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CFG_adctrl_SHIFT)) & CSS_CSS_CFG_adctrl_MASK) - -#define CSS_CSS_CFG_cfg_rsvd1_MASK (0x7C000000U) -#define CSS_CSS_CFG_cfg_rsvd1_SHIFT (26U) -/*! cfg_rsvd1 - reserved - */ -#define CSS_CSS_CFG_cfg_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CFG_cfg_rsvd1_SHIFT)) & CSS_CSS_CFG_cfg_rsvd1_MASK) - -#define CSS_CSS_CFG_sha2_direct_MASK (0x80000000U) -#define CSS_CSS_CFG_sha2_direct_SHIFT (31U) -/*! sha2_direct - 1=enable sha2 direct mode: direct access from external - */ -#define CSS_CSS_CFG_sha2_direct(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CFG_sha2_direct_SHIFT)) & CSS_CSS_CFG_sha2_direct_MASK) -/*! @} */ - -/*! @name CSS_KIDX0 - Keystore index 0 - for commands that access a single key */ -/*! @{ */ - -#define CSS_CSS_KIDX0_kidx0_MASK (0x7FU) -#define CSS_CSS_KIDX0_kidx0_SHIFT (0U) -/*! kidx0 - keystore is indexed as an array of 128 bit key slots - */ -#define CSS_CSS_KIDX0_kidx0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KIDX0_kidx0_SHIFT)) & CSS_CSS_KIDX0_kidx0_MASK) - -#define CSS_CSS_KIDX0_kidx0_rsvd_MASK (0xFFFFFF80U) -#define CSS_CSS_KIDX0_kidx0_rsvd_SHIFT (7U) -/*! kidx0_rsvd - reserved - */ -#define CSS_CSS_KIDX0_kidx0_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KIDX0_kidx0_rsvd_SHIFT)) & CSS_CSS_KIDX0_kidx0_rsvd_MASK) -/*! @} */ - -/*! @name CSS_KIDX1 - Keystore index 1 - for commands that access 2 keys */ -/*! @{ */ - -#define CSS_CSS_KIDX1_kidx1_MASK (0x7FU) -#define CSS_CSS_KIDX1_kidx1_SHIFT (0U) -/*! kidx1 - keystore is indexed as an array of 128 bit key slots - */ -#define CSS_CSS_KIDX1_kidx1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KIDX1_kidx1_SHIFT)) & CSS_CSS_KIDX1_kidx1_MASK) - -#define CSS_CSS_KIDX1_kidx1_rsvd_MASK (0xFFFFFF80U) -#define CSS_CSS_KIDX1_kidx1_rsvd_SHIFT (7U) -/*! kidx1_rsvd - reserved - */ -#define CSS_CSS_KIDX1_kidx1_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KIDX1_kidx1_rsvd_SHIFT)) & CSS_CSS_KIDX1_kidx1_rsvd_MASK) -/*! @} */ - -/*! @name CSS_KPROPIN - key properties request */ -/*! @{ */ - -#define CSS_CSS_KPROPIN_kpropin_MASK (0xFFFFFFFFU) -#define CSS_CSS_KPROPIN_kpropin_SHIFT (0U) -/*! kpropin - for commands that create a key - requested properties - */ -#define CSS_CSS_KPROPIN_kpropin(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KPROPIN_kpropin_SHIFT)) & CSS_CSS_KPROPIN_kpropin_MASK) -/*! @} */ - -/*! @name CSS_DMA_SRC0 - CSS DMA Source 0 */ -/*! @{ */ - -#define CSS_CSS_DMA_SRC0_addr_src0_MASK (0xFFFFFFFFU) -#define CSS_CSS_DMA_SRC0_addr_src0_SHIFT (0U) -/*! addr_src0 - defines the System address of the start of the - */ -#define CSS_CSS_DMA_SRC0_addr_src0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_DMA_SRC0_addr_src0_SHIFT)) & CSS_CSS_DMA_SRC0_addr_src0_MASK) -/*! @} */ - -/*! @name CSS_DMA_SRC0_LEN - CSS DMA Source 0 length */ -/*! @{ */ - -#define CSS_CSS_DMA_SRC0_LEN_size_src0_len_MASK (0xFFFFFFFFU) -#define CSS_CSS_DMA_SRC0_LEN_size_src0_len_SHIFT (0U) -/*! size_src0_len - Size in bytes of the data to be transferred from - */ -#define CSS_CSS_DMA_SRC0_LEN_size_src0_len(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_DMA_SRC0_LEN_size_src0_len_SHIFT)) & CSS_CSS_DMA_SRC0_LEN_size_src0_len_MASK) -/*! @} */ - -/*! @name CSS_DMA_SRC1 - CSS DMA Source 1 */ -/*! @{ */ - -#define CSS_CSS_DMA_SRC1_addr_src1_MASK (0xFFFFFFFFU) -#define CSS_CSS_DMA_SRC1_addr_src1_SHIFT (0U) -/*! addr_src1 - defines the System address of the start of the - */ -#define CSS_CSS_DMA_SRC1_addr_src1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_DMA_SRC1_addr_src1_SHIFT)) & CSS_CSS_DMA_SRC1_addr_src1_MASK) -/*! @} */ - -/*! @name CSS_DMA_SRC2 - CSS DMA Source 2 */ -/*! @{ */ - -#define CSS_CSS_DMA_SRC2_addr_src2_MASK (0xFFFFFFFFU) -#define CSS_CSS_DMA_SRC2_addr_src2_SHIFT (0U) -/*! addr_src2 - defines the System address of the start of the - */ -#define CSS_CSS_DMA_SRC2_addr_src2(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_DMA_SRC2_addr_src2_SHIFT)) & CSS_CSS_DMA_SRC2_addr_src2_MASK) -/*! @} */ - -/*! @name CSS_DMA_SRC2_LEN - CSS DMA Source 2 length */ -/*! @{ */ - -#define CSS_CSS_DMA_SRC2_LEN_size_src2_len_MASK (0xFFFFFFFFU) -#define CSS_CSS_DMA_SRC2_LEN_size_src2_len_SHIFT (0U) -/*! size_src2_len - Size in bytes of the data to be transferred from - */ -#define CSS_CSS_DMA_SRC2_LEN_size_src2_len(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_DMA_SRC2_LEN_size_src2_len_SHIFT)) & CSS_CSS_DMA_SRC2_LEN_size_src2_len_MASK) -/*! @} */ - -/*! @name CSS_DMA_RES0 - CSS DMA Result 0 */ -/*! @{ */ - -#define CSS_CSS_DMA_RES0_addr_res0_MASK (0xFFFFFFFFU) -#define CSS_CSS_DMA_RES0_addr_res0_SHIFT (0U) -/*! addr_res0 - defines the System Start address of where the result - */ -#define CSS_CSS_DMA_RES0_addr_res0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_DMA_RES0_addr_res0_SHIFT)) & CSS_CSS_DMA_RES0_addr_res0_MASK) -/*! @} */ - -/*! @name CSS_DMA_RES0_LEN - CSS DMA Result 0 Size */ -/*! @{ */ - -#define CSS_CSS_DMA_RES0_LEN_size_res0_len_MASK (0xFFFFFFFFU) -#define CSS_CSS_DMA_RES0_LEN_size_res0_len_SHIFT (0U) -/*! size_res0_len - Size in bytes of the data to be transferred to - */ -#define CSS_CSS_DMA_RES0_LEN_size_res0_len(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_DMA_RES0_LEN_size_res0_len_SHIFT)) & CSS_CSS_DMA_RES0_LEN_size_res0_len_MASK) -/*! @} */ - -/*! @name CSS_INT_ENABLE - Interrupt enable */ -/*! @{ */ - -#define CSS_CSS_INT_ENABLE_int_en_MASK (0x1U) -#define CSS_CSS_INT_ENABLE_int_en_SHIFT (0U) -/*! int_en - Interrupt enable bit - */ -#define CSS_CSS_INT_ENABLE_int_en(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_ENABLE_int_en_SHIFT)) & CSS_CSS_INT_ENABLE_int_en_MASK) - -#define CSS_CSS_INT_ENABLE_gdet_int_en_MASK (0x2U) -#define CSS_CSS_INT_ENABLE_gdet_int_en_SHIFT (1U) -/*! gdet_int_en - GDET Interrupt enable bit - */ -#define CSS_CSS_INT_ENABLE_gdet_int_en(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_ENABLE_gdet_int_en_SHIFT)) & CSS_CSS_INT_ENABLE_gdet_int_en_MASK) - -#define CSS_CSS_INT_ENABLE_int_ena_rsvd_MASK (0xFFFFFFFCU) -#define CSS_CSS_INT_ENABLE_int_ena_rsvd_SHIFT (2U) -/*! int_ena_rsvd - reserved - */ -#define CSS_CSS_INT_ENABLE_int_ena_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_ENABLE_int_ena_rsvd_SHIFT)) & CSS_CSS_INT_ENABLE_int_ena_rsvd_MASK) -/*! @} */ - -/*! @name CSS_INT_STATUS_CLR - Interrupt status clear */ -/*! @{ */ - -#define CSS_CSS_INT_STATUS_CLR_int_clr_MASK (0x1U) -#define CSS_CSS_INT_STATUS_CLR_int_clr_SHIFT (0U) -/*! int_clr - Interrupt status clear - */ -#define CSS_CSS_INT_STATUS_CLR_int_clr(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_STATUS_CLR_int_clr_SHIFT)) & CSS_CSS_INT_STATUS_CLR_int_clr_MASK) - -#define CSS_CSS_INT_STATUS_CLR_gdet_int_clr_MASK (0x2U) -#define CSS_CSS_INT_STATUS_CLR_gdet_int_clr_SHIFT (1U) -/*! gdet_int_clr - GDET Interrupt status clear - */ -#define CSS_CSS_INT_STATUS_CLR_gdet_int_clr(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_STATUS_CLR_gdet_int_clr_SHIFT)) & CSS_CSS_INT_STATUS_CLR_gdet_int_clr_MASK) - -#define CSS_CSS_INT_STATUS_CLR_int_stsc_rsvd_MASK (0xFFFFFFFCU) -#define CSS_CSS_INT_STATUS_CLR_int_stsc_rsvd_SHIFT (2U) -/*! int_stsc_rsvd - reserved - */ -#define CSS_CSS_INT_STATUS_CLR_int_stsc_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_STATUS_CLR_int_stsc_rsvd_SHIFT)) & CSS_CSS_INT_STATUS_CLR_int_stsc_rsvd_MASK) -/*! @} */ - -/*! @name CSS_INT_STATUS_SET - Interrupt status set */ -/*! @{ */ - -#define CSS_CSS_INT_STATUS_SET_int_set_MASK (0x1U) -#define CSS_CSS_INT_STATUS_SET_int_set_SHIFT (0U) -/*! int_set - Set interrupt by software - */ -#define CSS_CSS_INT_STATUS_SET_int_set(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_STATUS_SET_int_set_SHIFT)) & CSS_CSS_INT_STATUS_SET_int_set_MASK) - -#define CSS_CSS_INT_STATUS_SET_gdet_int_neg_set_MASK (0x2U) -#define CSS_CSS_INT_STATUS_SET_gdet_int_neg_set_SHIFT (1U) -/*! gdet_int_neg_set - Set GDET interrupt by software - */ -#define CSS_CSS_INT_STATUS_SET_gdet_int_neg_set(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_STATUS_SET_gdet_int_neg_set_SHIFT)) & CSS_CSS_INT_STATUS_SET_gdet_int_neg_set_MASK) - -#define CSS_CSS_INT_STATUS_SET_gdet_int_pos_set_MASK (0x4U) -#define CSS_CSS_INT_STATUS_SET_gdet_int_pos_set_SHIFT (2U) -/*! gdet_int_pos_set - Set GDET interrupt by software - */ -#define CSS_CSS_INT_STATUS_SET_gdet_int_pos_set(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_STATUS_SET_gdet_int_pos_set_SHIFT)) & CSS_CSS_INT_STATUS_SET_gdet_int_pos_set_MASK) - -#define CSS_CSS_INT_STATUS_SET_int_stss_rsvd_MASK (0xFFFFFFF8U) -#define CSS_CSS_INT_STATUS_SET_int_stss_rsvd_SHIFT (3U) -/*! int_stss_rsvd - reserved - */ -#define CSS_CSS_INT_STATUS_SET_int_stss_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_STATUS_SET_int_stss_rsvd_SHIFT)) & CSS_CSS_INT_STATUS_SET_int_stss_rsvd_MASK) -/*! @} */ - -/*! @name CSS_ERR_STATUS - Status register */ -/*! @{ */ - -#define CSS_CSS_ERR_STATUS_bus_err_MASK (0x1U) -#define CSS_CSS_ERR_STATUS_bus_err_SHIFT (0U) -/*! bus_err - Bus access error: public or private bus - */ -#define CSS_CSS_ERR_STATUS_bus_err(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_bus_err_SHIFT)) & CSS_CSS_ERR_STATUS_bus_err_MASK) - -#define CSS_CSS_ERR_STATUS_opn_err_MASK (0x2U) -#define CSS_CSS_ERR_STATUS_opn_err_SHIFT (1U) -/*! opn_err - Operational error: - */ -#define CSS_CSS_ERR_STATUS_opn_err(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_opn_err_SHIFT)) & CSS_CSS_ERR_STATUS_opn_err_MASK) - -#define CSS_CSS_ERR_STATUS_alg_err_MASK (0x4U) -#define CSS_CSS_ERR_STATUS_alg_err_SHIFT (2U) -/*! alg_err - Algorithm error: An internal algorithm has - */ -#define CSS_CSS_ERR_STATUS_alg_err(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_alg_err_SHIFT)) & CSS_CSS_ERR_STATUS_alg_err_MASK) - -#define CSS_CSS_ERR_STATUS_itg_err_MASK (0x8U) -#define CSS_CSS_ERR_STATUS_itg_err_SHIFT (3U) -/*! itg_err - Data integrity error: - */ -#define CSS_CSS_ERR_STATUS_itg_err(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_itg_err_SHIFT)) & CSS_CSS_ERR_STATUS_itg_err_MASK) - -#define CSS_CSS_ERR_STATUS_flt_err_MASK (0x10U) -#define CSS_CSS_ERR_STATUS_flt_err_SHIFT (4U) -/*! flt_err - Hardware fault error: Attempt to change the value - */ -#define CSS_CSS_ERR_STATUS_flt_err(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_flt_err_SHIFT)) & CSS_CSS_ERR_STATUS_flt_err_MASK) - -#define CSS_CSS_ERR_STATUS_prng_err_MASK (0x20U) -#define CSS_CSS_ERR_STATUS_prng_err_SHIFT (5U) -/*! prng_err - User Read of CSS_PRNG_DATOUT when CSS_STATUS.PRNG_RDY - */ -#define CSS_CSS_ERR_STATUS_prng_err(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_prng_err_SHIFT)) & CSS_CSS_ERR_STATUS_prng_err_MASK) - -#define CSS_CSS_ERR_STATUS_err_lvl_MASK (0xC0U) -#define CSS_CSS_ERR_STATUS_err_lvl_SHIFT (6U) -/*! err_lvl - Indicates Error Level which has been triggerer. 0, 1 ,2 - */ -#define CSS_CSS_ERR_STATUS_err_lvl(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_err_lvl_SHIFT)) & CSS_CSS_ERR_STATUS_err_lvl_MASK) - -#define CSS_CSS_ERR_STATUS_dtrng_err_MASK (0x100U) -#define CSS_CSS_ERR_STATUS_dtrng_err_SHIFT (8U) -/*! dtrng_err - DTRNG unable to gather entropy with the current - */ -#define CSS_CSS_ERR_STATUS_dtrng_err(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_dtrng_err_SHIFT)) & CSS_CSS_ERR_STATUS_dtrng_err_MASK) - -#define CSS_CSS_ERR_STATUS_err_stat_rsvd_MASK (0xFFFFFE00U) -#define CSS_CSS_ERR_STATUS_err_stat_rsvd_SHIFT (9U) -/*! err_stat_rsvd - reserved - */ -#define CSS_CSS_ERR_STATUS_err_stat_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_err_stat_rsvd_SHIFT)) & CSS_CSS_ERR_STATUS_err_stat_rsvd_MASK) -/*! @} */ - -/*! @name CSS_ERR_STATUS_CLR - Interrupt status clear */ -/*! @{ */ - -#define CSS_CSS_ERR_STATUS_CLR_err_clr_MASK (0x1U) -#define CSS_CSS_ERR_STATUS_CLR_err_clr_SHIFT (0U) -/*! err_clr - 1=clear CSS error status bits and exit CSS error state - */ -#define CSS_CSS_ERR_STATUS_CLR_err_clr(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_CLR_err_clr_SHIFT)) & CSS_CSS_ERR_STATUS_CLR_err_clr_MASK) - -#define CSS_CSS_ERR_STATUS_CLR_err_stsc_rsvd_MASK (0xFFFFFFFEU) -#define CSS_CSS_ERR_STATUS_CLR_err_stsc_rsvd_SHIFT (1U) -/*! err_stsc_rsvd - reserved - */ -#define CSS_CSS_ERR_STATUS_CLR_err_stsc_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_CLR_err_stsc_rsvd_SHIFT)) & CSS_CSS_ERR_STATUS_CLR_err_stsc_rsvd_MASK) -/*! @} */ - -/*! @name CSS_VERSION - CSS Version */ -/*! @{ */ - -#define CSS_CSS_VERSION_z_MASK (0xFU) -#define CSS_CSS_VERSION_z_SHIFT (0U) -/*! z - extended revision version: possible values 0-9 - */ -#define CSS_CSS_VERSION_z(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_VERSION_z_SHIFT)) & CSS_CSS_VERSION_z_MASK) - -#define CSS_CSS_VERSION_y2_MASK (0xF0U) -#define CSS_CSS_VERSION_y2_SHIFT (4U) -/*! y2 - minor release versino digit0: possible values 0-9 - */ -#define CSS_CSS_VERSION_y2(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_VERSION_y2_SHIFT)) & CSS_CSS_VERSION_y2_MASK) - -#define CSS_CSS_VERSION_y1_MASK (0xF00U) -#define CSS_CSS_VERSION_y1_SHIFT (8U) -/*! y1 - minor release version digit1: possible values 0-9 - */ -#define CSS_CSS_VERSION_y1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_VERSION_y1_SHIFT)) & CSS_CSS_VERSION_y1_MASK) - -#define CSS_CSS_VERSION_x_MASK (0xF000U) -#define CSS_CSS_VERSION_x_SHIFT (12U) -/*! x - major release version: possible values 1-9 - */ -#define CSS_CSS_VERSION_x(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_VERSION_x_SHIFT)) & CSS_CSS_VERSION_x_MASK) - -#define CSS_CSS_VERSION_version_rsvd_MASK (0xFFFF0000U) -#define CSS_CSS_VERSION_version_rsvd_SHIFT (16U) -/*! version_rsvd - reserved - */ -#define CSS_CSS_VERSION_version_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_VERSION_version_rsvd_SHIFT)) & CSS_CSS_VERSION_version_rsvd_MASK) -/*! @} */ - -/*! @name CSS_PRNG_DATOUT - PRNG SW read out register */ -/*! @{ */ - -#define CSS_CSS_PRNG_DATOUT_prng_datout_MASK (0xFFFFFFFFU) -#define CSS_CSS_PRNG_DATOUT_prng_datout_SHIFT (0U) -/*! prng_datout - 32-bit wide pseudo-random number - */ -#define CSS_CSS_PRNG_DATOUT_prng_datout(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_PRNG_DATOUT_prng_datout_SHIFT)) & CSS_CSS_PRNG_DATOUT_prng_datout_MASK) -/*! @} */ - -/*! @name CSS_GDET_EVTCNT - CSS GDET Event Counter */ -/*! @{ */ - -#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_MASK (0xFFU) -#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_SHIFT (0U) -/*! gdet_evtcnt - Number of glitch event recorded - */ -#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_GDET_EVTCNT_gdet_evtcnt_SHIFT)) & CSS_CSS_GDET_EVTCNT_gdet_evtcnt_MASK) - -#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_clr_done_MASK (0x100U) -#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_clr_done_SHIFT (8U) -/*! gdet_evtcnt_clr_done - The GDET event counter has been cleared - */ -#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_clr_done(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_GDET_EVTCNT_gdet_evtcnt_clr_done_SHIFT)) & CSS_CSS_GDET_EVTCNT_gdet_evtcnt_clr_done_MASK) - -#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_rsvd_MASK (0xFFFFFE00U) -#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_rsvd_SHIFT (9U) -/*! gdet_evtcnt_rsvd - reserved - */ -#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_GDET_EVTCNT_gdet_evtcnt_rsvd_SHIFT)) & CSS_CSS_GDET_EVTCNT_gdet_evtcnt_rsvd_MASK) -/*! @} */ - -/*! @name CSS_GDET_EVTCNT_CLR - CSS GDET Event Counter Clear */ -/*! @{ */ - -#define CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_MASK (0x1U) -#define CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_SHIFT (0U) -/*! gdet_evtcnt_clr - 1=clear GDET event counter clear - */ -#define CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_SHIFT)) & CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_MASK) - -#define CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_rsvd_MASK (0xFFFFFFFEU) -#define CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_rsvd_SHIFT (1U) -/*! gdet_evtcnt_clr_rsvd - reserved - */ -#define CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_rsvd_SHIFT)) & CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_rsvd_MASK) -/*! @} */ - -/*! @name CSS_SHA2_STATUS - CSS SHA2 Status Register */ -/*! @{ */ - -#define CSS_CSS_SHA2_STATUS_sha2_busy_MASK (0x1U) -#define CSS_CSS_SHA2_STATUS_sha2_busy_SHIFT (0U) -/*! sha2_busy - SHA2 busy/idle status for sha direct - */ -#define CSS_CSS_SHA2_STATUS_sha2_busy(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_STATUS_sha2_busy_SHIFT)) & CSS_CSS_SHA2_STATUS_sha2_busy_MASK) - -#define CSS_CSS_SHA2_STATUS_status_rsvd1_MASK (0xFFFFFFFEU) -#define CSS_CSS_SHA2_STATUS_status_rsvd1_SHIFT (1U) -/*! status_rsvd1 - reserved - */ -#define CSS_CSS_SHA2_STATUS_status_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_STATUS_status_rsvd1_SHIFT)) & CSS_CSS_SHA2_STATUS_status_rsvd1_MASK) -/*! @} */ - -/*! @name CSS_SHA2_CTRL - SHA2 Control register */ -/*! @{ */ - -#define CSS_CSS_SHA2_CTRL_sha2_start_MASK (0x1U) -#define CSS_CSS_SHA2_CTRL_sha2_start_SHIFT (0U) -/*! sha2_start - Write to 1 to Init the SHA2 Module - */ -#define CSS_CSS_SHA2_CTRL_sha2_start(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_sha2_start_SHIFT)) & CSS_CSS_SHA2_CTRL_sha2_start_MASK) - -#define CSS_CSS_SHA2_CTRL_sha2_rst_MASK (0x2U) -#define CSS_CSS_SHA2_CTRL_sha2_rst_SHIFT (1U) -/*! sha2_rst - Write to 1 to Reset a SHA2 operation - */ -#define CSS_CSS_SHA2_CTRL_sha2_rst(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_sha2_rst_SHIFT)) & CSS_CSS_SHA2_CTRL_sha2_rst_MASK) - -#define CSS_CSS_SHA2_CTRL_sha2_init_MASK (0x4U) -#define CSS_CSS_SHA2_CTRL_sha2_init_SHIFT (2U) -/*! sha2_init - Write to 1 to Init the SHA2 Kernel - */ -#define CSS_CSS_SHA2_CTRL_sha2_init(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_sha2_init_SHIFT)) & CSS_CSS_SHA2_CTRL_sha2_init_MASK) - -#define CSS_CSS_SHA2_CTRL_sha2_load_MASK (0x8U) -#define CSS_CSS_SHA2_CTRL_sha2_load_SHIFT (3U) -/*! sha2_load - Write to 1 to Load the SHA2 Kernel - */ -#define CSS_CSS_SHA2_CTRL_sha2_load(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_sha2_load_SHIFT)) & CSS_CSS_SHA2_CTRL_sha2_load_MASK) - -#define CSS_CSS_SHA2_CTRL_sha2_mode_MASK (0x30U) -#define CSS_CSS_SHA2_CTRL_sha2_mode_SHIFT (4U) -/*! sha2_mode - SHA2 MODE: - */ -#define CSS_CSS_SHA2_CTRL_sha2_mode(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_sha2_mode_SHIFT)) & CSS_CSS_SHA2_CTRL_sha2_mode_MASK) - -#define CSS_CSS_SHA2_CTRL_ctrl_rsvd1_MASK (0x1C0U) -#define CSS_CSS_SHA2_CTRL_ctrl_rsvd1_SHIFT (6U) -/*! ctrl_rsvd1 - r-eserved - */ -#define CSS_CSS_SHA2_CTRL_ctrl_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_ctrl_rsvd1_SHIFT)) & CSS_CSS_SHA2_CTRL_ctrl_rsvd1_MASK) - -#define CSS_CSS_SHA2_CTRL_sha2_byte_order_MASK (0x200U) -#define CSS_CSS_SHA2_CTRL_sha2_byte_order_SHIFT (9U) -/*! sha2_byte_order - Write to 1 to Reverse byte endianess - */ -#define CSS_CSS_SHA2_CTRL_sha2_byte_order(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_sha2_byte_order_SHIFT)) & CSS_CSS_SHA2_CTRL_sha2_byte_order_MASK) - -#define CSS_CSS_SHA2_CTRL_ctrl_rsvd_MASK (0xFFFFFC00U) -#define CSS_CSS_SHA2_CTRL_ctrl_rsvd_SHIFT (10U) -/*! ctrl_rsvd - r-eserved - */ -#define CSS_CSS_SHA2_CTRL_ctrl_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_ctrl_rsvd_SHIFT)) & CSS_CSS_SHA2_CTRL_ctrl_rsvd_MASK) -/*! @} */ - -/*! @name CSS_SHA2_DIN - CSS SHA_DATA IN Register 0 */ -/*! @{ */ - -#define CSS_CSS_SHA2_DIN_sha_datin_MASK (0xFFFFFFFFU) -#define CSS_CSS_SHA2_DIN_sha_datin_SHIFT (0U) -/*! sha_datin - Output CSS_SHA_DATIN from CSS Application being executed - */ -#define CSS_CSS_SHA2_DIN_sha_datin(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DIN_sha_datin_SHIFT)) & CSS_CSS_SHA2_DIN_sha_datin_MASK) -/*! @} */ - -/*! @name CSS_SHA2_DOUT0 - CSS CSS_SHA_DATA Out Register 0 */ -/*! @{ */ - -#define CSS_CSS_SHA2_DOUT0_sha_data0_MASK (0xFFFFFFFFU) -#define CSS_CSS_SHA2_DOUT0_sha_data0_SHIFT (0U) -/*! sha_data0 - Output SHA_DATA from CSS Application being executed - */ -#define CSS_CSS_SHA2_DOUT0_sha_data0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT0_sha_data0_SHIFT)) & CSS_CSS_SHA2_DOUT0_sha_data0_MASK) -/*! @} */ - -/*! @name CSS_SHA2_DOUT1 - CSS SHA_DATA Out Register 1 */ -/*! @{ */ - -#define CSS_CSS_SHA2_DOUT1_sha_data1_MASK (0xFFFFFFFFU) -#define CSS_CSS_SHA2_DOUT1_sha_data1_SHIFT (0U) -/*! sha_data1 - Output SHA_DATA from CSS Application being executed - */ -#define CSS_CSS_SHA2_DOUT1_sha_data1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT1_sha_data1_SHIFT)) & CSS_CSS_SHA2_DOUT1_sha_data1_MASK) -/*! @} */ - -/*! @name CSS_SHA2_DOUT2 - CSS SHA_DATA Out Register 2 */ -/*! @{ */ - -#define CSS_CSS_SHA2_DOUT2_sha_data2_MASK (0xFFFFFFFFU) -#define CSS_CSS_SHA2_DOUT2_sha_data2_SHIFT (0U) -/*! sha_data2 - Output SHA_DATA from CSS Application being executed - */ -#define CSS_CSS_SHA2_DOUT2_sha_data2(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT2_sha_data2_SHIFT)) & CSS_CSS_SHA2_DOUT2_sha_data2_MASK) -/*! @} */ - -/*! @name CSS_SHA2_DOUT3 - CSS SHA_DATA Out Register 3 */ -/*! @{ */ - -#define CSS_CSS_SHA2_DOUT3_sha_data3_MASK (0xFFFFFFFFU) -#define CSS_CSS_SHA2_DOUT3_sha_data3_SHIFT (0U) -/*! sha_data3 - Output SHA_DATA from CSS Application being executed - */ -#define CSS_CSS_SHA2_DOUT3_sha_data3(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT3_sha_data3_SHIFT)) & CSS_CSS_SHA2_DOUT3_sha_data3_MASK) -/*! @} */ - -/*! @name CSS_SHA2_DOUT4 - CSS SHA_DATA Out Register 4 */ -/*! @{ */ - -#define CSS_CSS_SHA2_DOUT4_sha_data4_MASK (0xFFFFFFFFU) -#define CSS_CSS_SHA2_DOUT4_sha_data4_SHIFT (0U) -/*! sha_data4 - Output SHA_DATA from CSS Application being executed - */ -#define CSS_CSS_SHA2_DOUT4_sha_data4(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT4_sha_data4_SHIFT)) & CSS_CSS_SHA2_DOUT4_sha_data4_MASK) -/*! @} */ - -/*! @name CSS_SHA2_DOUT5 - CSS SHA_DATA Out Register 5 */ -/*! @{ */ - -#define CSS_CSS_SHA2_DOUT5_sha_data5_MASK (0xFFFFFFFFU) -#define CSS_CSS_SHA2_DOUT5_sha_data5_SHIFT (0U) -/*! sha_data5 - Output SHA_DATA from CSS Application being executed - */ -#define CSS_CSS_SHA2_DOUT5_sha_data5(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT5_sha_data5_SHIFT)) & CSS_CSS_SHA2_DOUT5_sha_data5_MASK) -/*! @} */ - -/*! @name CSS_SHA2_DOUT6 - CSS SHA_DATA Out Register 6 */ -/*! @{ */ - -#define CSS_CSS_SHA2_DOUT6_sha_data6_MASK (0xFFFFFFFFU) -#define CSS_CSS_SHA2_DOUT6_sha_data6_SHIFT (0U) -/*! sha_data6 - Output SHA_DATA from CSS Application being executed - */ -#define CSS_CSS_SHA2_DOUT6_sha_data6(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT6_sha_data6_SHIFT)) & CSS_CSS_SHA2_DOUT6_sha_data6_MASK) -/*! @} */ - -/*! @name CSS_SHA2_DOUT7 - CSS SHA_DATA Out Register 7 */ -/*! @{ */ - -#define CSS_CSS_SHA2_DOUT7_sha_data7_MASK (0xFFFFFFFFU) -#define CSS_CSS_SHA2_DOUT7_sha_data7_SHIFT (0U) -/*! sha_data7 - Output SHA_DATA from CSS Application being executed - */ -#define CSS_CSS_SHA2_DOUT7_sha_data7(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT7_sha_data7_SHIFT)) & CSS_CSS_SHA2_DOUT7_sha_data7_MASK) -/*! @} */ - -/*! @name CSS_SHA2_DOUT8 - CSS CSS_SHA_DATA Out Register 8 */ -/*! @{ */ - -#define CSS_CSS_SHA2_DOUT8_sha_data8_MASK (0xFFFFFFFFU) -#define CSS_CSS_SHA2_DOUT8_sha_data8_SHIFT (0U) -/*! sha_data8 - Output SHA_DATA from CSS Application being executed - */ -#define CSS_CSS_SHA2_DOUT8_sha_data8(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT8_sha_data8_SHIFT)) & CSS_CSS_SHA2_DOUT8_sha_data8_MASK) -/*! @} */ - -/*! @name CSS_SHA2_DOUT9 - CSS SHA_DATA Out Register 9 */ -/*! @{ */ - -#define CSS_CSS_SHA2_DOUT9_sha_data9_MASK (0xFFFFFFFFU) -#define CSS_CSS_SHA2_DOUT9_sha_data9_SHIFT (0U) -/*! sha_data9 - Output SHA_DATA from CSS Application being executed - */ -#define CSS_CSS_SHA2_DOUT9_sha_data9(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT9_sha_data9_SHIFT)) & CSS_CSS_SHA2_DOUT9_sha_data9_MASK) -/*! @} */ - -/*! @name CSS_SHA2_DOUT10 - CSS SHA_DATA Out Register 10 */ -/*! @{ */ - -#define CSS_CSS_SHA2_DOUT10_sha_data10_MASK (0xFFFFFFFFU) -#define CSS_CSS_SHA2_DOUT10_sha_data10_SHIFT (0U) -/*! sha_data10 - Output SHA_DATA from CSS Application being executed - */ -#define CSS_CSS_SHA2_DOUT10_sha_data10(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT10_sha_data10_SHIFT)) & CSS_CSS_SHA2_DOUT10_sha_data10_MASK) -/*! @} */ - -/*! @name CSS_SHA2_DOUT11 - CSS SHA_DATA Out Register 11 */ -/*! @{ */ - -#define CSS_CSS_SHA2_DOUT11_sha_data11_MASK (0xFFFFFFFFU) -#define CSS_CSS_SHA2_DOUT11_sha_data11_SHIFT (0U) -/*! sha_data11 - Output SHA_DATA from CSS Application being executed - */ -#define CSS_CSS_SHA2_DOUT11_sha_data11(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT11_sha_data11_SHIFT)) & CSS_CSS_SHA2_DOUT11_sha_data11_MASK) -/*! @} */ - -/*! @name CSS_SHA2_DOUT12 - CSS SHA_DATA Out Register 12 */ -/*! @{ */ - -#define CSS_CSS_SHA2_DOUT12_sha_data12_MASK (0xFFFFFFFFU) -#define CSS_CSS_SHA2_DOUT12_sha_data12_SHIFT (0U) -/*! sha_data12 - Output SHA_DATA from CSS Application being executed - */ -#define CSS_CSS_SHA2_DOUT12_sha_data12(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT12_sha_data12_SHIFT)) & CSS_CSS_SHA2_DOUT12_sha_data12_MASK) -/*! @} */ - -/*! @name CSS_SHA2_DOUT13 - CSS SHA_DATA Out Register 13 */ -/*! @{ */ - -#define CSS_CSS_SHA2_DOUT13_sha_data13_MASK (0xFFFFFFFFU) -#define CSS_CSS_SHA2_DOUT13_sha_data13_SHIFT (0U) -/*! sha_data13 - Output SHA_DATA from CSS Application being executed - */ -#define CSS_CSS_SHA2_DOUT13_sha_data13(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT13_sha_data13_SHIFT)) & CSS_CSS_SHA2_DOUT13_sha_data13_MASK) -/*! @} */ - -/*! @name CSS_SHA2_DOUT14 - CSS SHA_DATA Out Register 14 */ -/*! @{ */ - -#define CSS_CSS_SHA2_DOUT14_sha_data14_MASK (0xFFFFFFFFU) -#define CSS_CSS_SHA2_DOUT14_sha_data14_SHIFT (0U) -/*! sha_data14 - Output SHA_DATA from CSS Application being executed - */ -#define CSS_CSS_SHA2_DOUT14_sha_data14(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT14_sha_data14_SHIFT)) & CSS_CSS_SHA2_DOUT14_sha_data14_MASK) -/*! @} */ - -/*! @name CSS_SHA2_DOUT15 - CSS SHA_DATA Out Register 15 */ -/*! @{ */ - -#define CSS_CSS_SHA2_DOUT15_sha_data15_MASK (0xFFFFFFFFU) -#define CSS_CSS_SHA2_DOUT15_sha_data15_SHIFT (0U) -/*! sha_data15 - Output SHA_DATA from CSS Application being executed - */ -#define CSS_CSS_SHA2_DOUT15_sha_data15(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT15_sha_data15_SHIFT)) & CSS_CSS_SHA2_DOUT15_sha_data15_MASK) -/*! @} */ - -/*! @name CSS_KS0 - Status register */ -/*! @{ */ - -#define CSS_CSS_KS0_ks0_ksize_MASK (0x1U) -#define CSS_CSS_KS0_ks0_ksize_SHIFT (0U) -/*! ks0_ksize - Key size: 0-128, 1-256 - */ -#define CSS_CSS_KS0_ks0_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_ksize_SHIFT)) & CSS_CSS_KS0_ks0_ksize_MASK) - -#define CSS_CSS_KS0_ks0_rsvd0_MASK (0x1EU) -#define CSS_CSS_KS0_ks0_rsvd0_SHIFT (1U) -/*! ks0_rsvd0 - Reserved 0 - */ -#define CSS_CSS_KS0_ks0_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_rsvd0_SHIFT)) & CSS_CSS_KS0_ks0_rsvd0_MASK) - -#define CSS_CSS_KS0_ks0_kact_MASK (0x20U) -#define CSS_CSS_KS0_ks0_kact_SHIFT (5U) -/*! ks0_kact - Key is active - */ -#define CSS_CSS_KS0_ks0_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_kact_SHIFT)) & CSS_CSS_KS0_ks0_kact_MASK) - -#define CSS_CSS_KS0_ks0_kbase_MASK (0x40U) -#define CSS_CSS_KS0_ks0_kbase_SHIFT (6U) -/*! ks0_kbase - First slot in a multislot key - */ -#define CSS_CSS_KS0_ks0_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_kbase_SHIFT)) & CSS_CSS_KS0_ks0_kbase_MASK) - -#define CSS_CSS_KS0_ks0_fgp_MASK (0x80U) -#define CSS_CSS_KS0_ks0_fgp_SHIFT (7U) -/*! ks0_fgp - Hardware Feature General Purpose - */ -#define CSS_CSS_KS0_ks0_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_fgp_SHIFT)) & CSS_CSS_KS0_ks0_fgp_MASK) - -#define CSS_CSS_KS0_ks0_frtn_MASK (0x100U) -#define CSS_CSS_KS0_ks0_frtn_SHIFT (8U) -/*! ks0_frtn - Hardware Feature Retention - */ -#define CSS_CSS_KS0_ks0_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_frtn_SHIFT)) & CSS_CSS_KS0_ks0_frtn_MASK) - -#define CSS_CSS_KS0_ks0_fhwo_MASK (0x200U) -#define CSS_CSS_KS0_ks0_fhwo_SHIFT (9U) -/*! ks0_fhwo - Hardware Feature Output - */ -#define CSS_CSS_KS0_ks0_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_fhwo_SHIFT)) & CSS_CSS_KS0_ks0_fhwo_MASK) - -#define CSS_CSS_KS0_ks0_rsvd1_MASK (0x1C00U) -#define CSS_CSS_KS0_ks0_rsvd1_SHIFT (10U) -/*! ks0_rsvd1 - Reserved 1 - */ -#define CSS_CSS_KS0_ks0_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_rsvd1_SHIFT)) & CSS_CSS_KS0_ks0_rsvd1_MASK) - -#define CSS_CSS_KS0_ks0_ucmac_MASK (0x2000U) -#define CSS_CSS_KS0_ks0_ucmac_SHIFT (13U) -/*! ks0_ucmac - CMAC key - */ -#define CSS_CSS_KS0_ks0_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_ucmac_SHIFT)) & CSS_CSS_KS0_ks0_ucmac_MASK) - -#define CSS_CSS_KS0_ks0_uksk_MASK (0x4000U) -#define CSS_CSS_KS0_ks0_uksk_SHIFT (14U) -/*! ks0_uksk - KSK key - */ -#define CSS_CSS_KS0_ks0_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uksk_SHIFT)) & CSS_CSS_KS0_ks0_uksk_MASK) - -#define CSS_CSS_KS0_ks0_urtf_MASK (0x8000U) -#define CSS_CSS_KS0_ks0_urtf_SHIFT (15U) -/*! ks0_urtf - Real Time Fingerprint key - */ -#define CSS_CSS_KS0_ks0_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_urtf_SHIFT)) & CSS_CSS_KS0_ks0_urtf_MASK) - -#define CSS_CSS_KS0_ks0_uckdf_MASK (0x10000U) -#define CSS_CSS_KS0_ks0_uckdf_SHIFT (16U) -/*! ks0_uckdf - Derivation key for CKDF command - */ -#define CSS_CSS_KS0_ks0_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uckdf_SHIFT)) & CSS_CSS_KS0_ks0_uckdf_MASK) - -#define CSS_CSS_KS0_ks0_uhkdf_MASK (0x20000U) -#define CSS_CSS_KS0_ks0_uhkdf_SHIFT (17U) -/*! ks0_uhkdf - Derivation key for HKDF command - */ -#define CSS_CSS_KS0_ks0_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uhkdf_SHIFT)) & CSS_CSS_KS0_ks0_uhkdf_MASK) - -#define CSS_CSS_KS0_ks0_uecsg_MASK (0x40000U) -#define CSS_CSS_KS0_ks0_uecsg_SHIFT (18U) -/*! ks0_uecsg - Ecc signing key - */ -#define CSS_CSS_KS0_ks0_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uecsg_SHIFT)) & CSS_CSS_KS0_ks0_uecsg_MASK) - -#define CSS_CSS_KS0_ks0_uecdh_MASK (0x80000U) -#define CSS_CSS_KS0_ks0_uecdh_SHIFT (19U) -/*! ks0_uecdh - Ecc diffie hellman key - */ -#define CSS_CSS_KS0_ks0_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uecdh_SHIFT)) & CSS_CSS_KS0_ks0_uecdh_MASK) - -#define CSS_CSS_KS0_ks0_uaes_MASK (0x100000U) -#define CSS_CSS_KS0_ks0_uaes_SHIFT (20U) -/*! ks0_uaes - Aes key - */ -#define CSS_CSS_KS0_ks0_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uaes_SHIFT)) & CSS_CSS_KS0_ks0_uaes_MASK) - -#define CSS_CSS_KS0_ks0_uhmac_MASK (0x200000U) -#define CSS_CSS_KS0_ks0_uhmac_SHIFT (21U) -/*! ks0_uhmac - Hmac key - */ -#define CSS_CSS_KS0_ks0_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uhmac_SHIFT)) & CSS_CSS_KS0_ks0_uhmac_MASK) - -#define CSS_CSS_KS0_ks0_ukwk_MASK (0x400000U) -#define CSS_CSS_KS0_ks0_ukwk_SHIFT (22U) -/*! ks0_ukwk - Key wrapping key - */ -#define CSS_CSS_KS0_ks0_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_ukwk_SHIFT)) & CSS_CSS_KS0_ks0_ukwk_MASK) - -#define CSS_CSS_KS0_ks0_ukuok_MASK (0x800000U) -#define CSS_CSS_KS0_ks0_ukuok_SHIFT (23U) -/*! ks0_ukuok - Key unwrapping key - */ -#define CSS_CSS_KS0_ks0_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_ukuok_SHIFT)) & CSS_CSS_KS0_ks0_ukuok_MASK) - -#define CSS_CSS_KS0_ks0_utlspms_MASK (0x1000000U) -#define CSS_CSS_KS0_ks0_utlspms_SHIFT (24U) -/*! ks0_utlspms - TLS Pre Master Secret - */ -#define CSS_CSS_KS0_ks0_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_utlspms_SHIFT)) & CSS_CSS_KS0_ks0_utlspms_MASK) - -#define CSS_CSS_KS0_ks0_utlsms_MASK (0x2000000U) -#define CSS_CSS_KS0_ks0_utlsms_SHIFT (25U) -/*! ks0_utlsms - TLS Master Secret - */ -#define CSS_CSS_KS0_ks0_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_utlsms_SHIFT)) & CSS_CSS_KS0_ks0_utlsms_MASK) - -#define CSS_CSS_KS0_ks0_ukgsrc_MASK (0x4000000U) -#define CSS_CSS_KS0_ks0_ukgsrc_SHIFT (26U) -/*! ks0_ukgsrc - Supply KEYGEN source - */ -#define CSS_CSS_KS0_ks0_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_ukgsrc_SHIFT)) & CSS_CSS_KS0_ks0_ukgsrc_MASK) - -#define CSS_CSS_KS0_ks0_uhwo_MASK (0x8000000U) -#define CSS_CSS_KS0_ks0_uhwo_SHIFT (27U) -/*! ks0_uhwo - Hardware out key - */ -#define CSS_CSS_KS0_ks0_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uhwo_SHIFT)) & CSS_CSS_KS0_ks0_uhwo_MASK) - -#define CSS_CSS_KS0_ks0_uwrpok_MASK (0x10000000U) -#define CSS_CSS_KS0_ks0_uwrpok_SHIFT (28U) -/*! ks0_uwrpok - Ok to wrap key - */ -#define CSS_CSS_KS0_ks0_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uwrpok_SHIFT)) & CSS_CSS_KS0_ks0_uwrpok_MASK) - -#define CSS_CSS_KS0_ks0_uduk_MASK (0x20000000U) -#define CSS_CSS_KS0_ks0_uduk_SHIFT (29U) -/*! ks0_uduk - Device Unique Key - */ -#define CSS_CSS_KS0_ks0_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uduk_SHIFT)) & CSS_CSS_KS0_ks0_uduk_MASK) - -#define CSS_CSS_KS0_ks0_upprot_MASK (0xC0000000U) -#define CSS_CSS_KS0_ks0_upprot_SHIFT (30U) -/*! ks0_upprot - Priviledge level - */ -#define CSS_CSS_KS0_ks0_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_upprot_SHIFT)) & CSS_CSS_KS0_ks0_upprot_MASK) -/*! @} */ - -/*! @name CSS_KS1 - Status register */ -/*! @{ */ - -#define CSS_CSS_KS1_ks1_ksize_MASK (0x1U) -#define CSS_CSS_KS1_ks1_ksize_SHIFT (0U) -/*! ks1_ksize - Key size: 0-128, 1-256 - */ -#define CSS_CSS_KS1_ks1_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_ksize_SHIFT)) & CSS_CSS_KS1_ks1_ksize_MASK) - -#define CSS_CSS_KS1_ks1_rsvd0_MASK (0x1EU) -#define CSS_CSS_KS1_ks1_rsvd0_SHIFT (1U) -/*! ks1_rsvd0 - Reserved 0 - */ -#define CSS_CSS_KS1_ks1_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_rsvd0_SHIFT)) & CSS_CSS_KS1_ks1_rsvd0_MASK) - -#define CSS_CSS_KS1_ks1_kact_MASK (0x20U) -#define CSS_CSS_KS1_ks1_kact_SHIFT (5U) -/*! ks1_kact - Key is active - */ -#define CSS_CSS_KS1_ks1_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_kact_SHIFT)) & CSS_CSS_KS1_ks1_kact_MASK) - -#define CSS_CSS_KS1_ks1_kbase_MASK (0x40U) -#define CSS_CSS_KS1_ks1_kbase_SHIFT (6U) -/*! ks1_kbase - First slot in a multislot key - */ -#define CSS_CSS_KS1_ks1_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_kbase_SHIFT)) & CSS_CSS_KS1_ks1_kbase_MASK) - -#define CSS_CSS_KS1_ks1_fgp_MASK (0x80U) -#define CSS_CSS_KS1_ks1_fgp_SHIFT (7U) -/*! ks1_fgp - Hardware Feature General Purpose - */ -#define CSS_CSS_KS1_ks1_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_fgp_SHIFT)) & CSS_CSS_KS1_ks1_fgp_MASK) - -#define CSS_CSS_KS1_ks1_frtn_MASK (0x100U) -#define CSS_CSS_KS1_ks1_frtn_SHIFT (8U) -/*! ks1_frtn - Hardware Feature Retention - */ -#define CSS_CSS_KS1_ks1_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_frtn_SHIFT)) & CSS_CSS_KS1_ks1_frtn_MASK) - -#define CSS_CSS_KS1_ks1_fhwo_MASK (0x200U) -#define CSS_CSS_KS1_ks1_fhwo_SHIFT (9U) -/*! ks1_fhwo - Hardware Feature Output - */ -#define CSS_CSS_KS1_ks1_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_fhwo_SHIFT)) & CSS_CSS_KS1_ks1_fhwo_MASK) - -#define CSS_CSS_KS1_ks1_rsvd1_MASK (0x1C00U) -#define CSS_CSS_KS1_ks1_rsvd1_SHIFT (10U) -/*! ks1_rsvd1 - Reserved 1 - */ -#define CSS_CSS_KS1_ks1_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_rsvd1_SHIFT)) & CSS_CSS_KS1_ks1_rsvd1_MASK) - -#define CSS_CSS_KS1_ks1_ucmac_MASK (0x2000U) -#define CSS_CSS_KS1_ks1_ucmac_SHIFT (13U) -/*! ks1_ucmac - CMAC key - */ -#define CSS_CSS_KS1_ks1_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_ucmac_SHIFT)) & CSS_CSS_KS1_ks1_ucmac_MASK) - -#define CSS_CSS_KS1_ks1_uksk_MASK (0x4000U) -#define CSS_CSS_KS1_ks1_uksk_SHIFT (14U) -/*! ks1_uksk - KSK key - */ -#define CSS_CSS_KS1_ks1_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uksk_SHIFT)) & CSS_CSS_KS1_ks1_uksk_MASK) - -#define CSS_CSS_KS1_ks1_urtf_MASK (0x8000U) -#define CSS_CSS_KS1_ks1_urtf_SHIFT (15U) -/*! ks1_urtf - Real Time Fingerprint key - */ -#define CSS_CSS_KS1_ks1_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_urtf_SHIFT)) & CSS_CSS_KS1_ks1_urtf_MASK) - -#define CSS_CSS_KS1_ks1_uckdf_MASK (0x10000U) -#define CSS_CSS_KS1_ks1_uckdf_SHIFT (16U) -/*! ks1_uckdf - Derivation key for CKDF command - */ -#define CSS_CSS_KS1_ks1_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uckdf_SHIFT)) & CSS_CSS_KS1_ks1_uckdf_MASK) - -#define CSS_CSS_KS1_ks1_uhkdf_MASK (0x20000U) -#define CSS_CSS_KS1_ks1_uhkdf_SHIFT (17U) -/*! ks1_uhkdf - Derivation key for HKDF command - */ -#define CSS_CSS_KS1_ks1_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uhkdf_SHIFT)) & CSS_CSS_KS1_ks1_uhkdf_MASK) - -#define CSS_CSS_KS1_ks1_uecsg_MASK (0x40000U) -#define CSS_CSS_KS1_ks1_uecsg_SHIFT (18U) -/*! ks1_uecsg - Ecc signing key - */ -#define CSS_CSS_KS1_ks1_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uecsg_SHIFT)) & CSS_CSS_KS1_ks1_uecsg_MASK) - -#define CSS_CSS_KS1_ks1_uecdh_MASK (0x80000U) -#define CSS_CSS_KS1_ks1_uecdh_SHIFT (19U) -/*! ks1_uecdh - Ecc diffie hellman key - */ -#define CSS_CSS_KS1_ks1_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uecdh_SHIFT)) & CSS_CSS_KS1_ks1_uecdh_MASK) - -#define CSS_CSS_KS1_ks1_uaes_MASK (0x100000U) -#define CSS_CSS_KS1_ks1_uaes_SHIFT (20U) -/*! ks1_uaes - Aes key - */ -#define CSS_CSS_KS1_ks1_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uaes_SHIFT)) & CSS_CSS_KS1_ks1_uaes_MASK) - -#define CSS_CSS_KS1_ks1_uhmac_MASK (0x200000U) -#define CSS_CSS_KS1_ks1_uhmac_SHIFT (21U) -/*! ks1_uhmac - Hmac key - */ -#define CSS_CSS_KS1_ks1_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uhmac_SHIFT)) & CSS_CSS_KS1_ks1_uhmac_MASK) - -#define CSS_CSS_KS1_ks1_ukwk_MASK (0x400000U) -#define CSS_CSS_KS1_ks1_ukwk_SHIFT (22U) -/*! ks1_ukwk - Key wrapping key - */ -#define CSS_CSS_KS1_ks1_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_ukwk_SHIFT)) & CSS_CSS_KS1_ks1_ukwk_MASK) - -#define CSS_CSS_KS1_ks1_ukuok_MASK (0x800000U) -#define CSS_CSS_KS1_ks1_ukuok_SHIFT (23U) -/*! ks1_ukuok - Key unwrapping key - */ -#define CSS_CSS_KS1_ks1_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_ukuok_SHIFT)) & CSS_CSS_KS1_ks1_ukuok_MASK) - -#define CSS_CSS_KS1_ks1_utlspms_MASK (0x1000000U) -#define CSS_CSS_KS1_ks1_utlspms_SHIFT (24U) -/*! ks1_utlspms - TLS Pre Master Secret - */ -#define CSS_CSS_KS1_ks1_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_utlspms_SHIFT)) & CSS_CSS_KS1_ks1_utlspms_MASK) - -#define CSS_CSS_KS1_ks1_utlsms_MASK (0x2000000U) -#define CSS_CSS_KS1_ks1_utlsms_SHIFT (25U) -/*! ks1_utlsms - TLS Master Secret - */ -#define CSS_CSS_KS1_ks1_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_utlsms_SHIFT)) & CSS_CSS_KS1_ks1_utlsms_MASK) - -#define CSS_CSS_KS1_ks1_ukgsrc_MASK (0x4000000U) -#define CSS_CSS_KS1_ks1_ukgsrc_SHIFT (26U) -/*! ks1_ukgsrc - Supply KEYGEN source - */ -#define CSS_CSS_KS1_ks1_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_ukgsrc_SHIFT)) & CSS_CSS_KS1_ks1_ukgsrc_MASK) - -#define CSS_CSS_KS1_ks1_uhwo_MASK (0x8000000U) -#define CSS_CSS_KS1_ks1_uhwo_SHIFT (27U) -/*! ks1_uhwo - Hardware out key - */ -#define CSS_CSS_KS1_ks1_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uhwo_SHIFT)) & CSS_CSS_KS1_ks1_uhwo_MASK) - -#define CSS_CSS_KS1_ks1_uwrpok_MASK (0x10000000U) -#define CSS_CSS_KS1_ks1_uwrpok_SHIFT (28U) -/*! ks1_uwrpok - Ok to wrap key - */ -#define CSS_CSS_KS1_ks1_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uwrpok_SHIFT)) & CSS_CSS_KS1_ks1_uwrpok_MASK) - -#define CSS_CSS_KS1_ks1_uduk_MASK (0x20000000U) -#define CSS_CSS_KS1_ks1_uduk_SHIFT (29U) -/*! ks1_uduk - Device Unique Key - */ -#define CSS_CSS_KS1_ks1_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uduk_SHIFT)) & CSS_CSS_KS1_ks1_uduk_MASK) - -#define CSS_CSS_KS1_ks1_upprot_MASK (0xC0000000U) -#define CSS_CSS_KS1_ks1_upprot_SHIFT (30U) -/*! ks1_upprot - Priviledge level - */ -#define CSS_CSS_KS1_ks1_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_upprot_SHIFT)) & CSS_CSS_KS1_ks1_upprot_MASK) -/*! @} */ - -/*! @name CSS_KS2 - Status register */ -/*! @{ */ - -#define CSS_CSS_KS2_ks2_ksize_MASK (0x1U) -#define CSS_CSS_KS2_ks2_ksize_SHIFT (0U) -/*! ks2_ksize - Key size: 0-128, 1-256 - */ -#define CSS_CSS_KS2_ks2_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_ksize_SHIFT)) & CSS_CSS_KS2_ks2_ksize_MASK) - -#define CSS_CSS_KS2_ks2_rsvd0_MASK (0x1EU) -#define CSS_CSS_KS2_ks2_rsvd0_SHIFT (1U) -/*! ks2_rsvd0 - Reserved 0 - */ -#define CSS_CSS_KS2_ks2_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_rsvd0_SHIFT)) & CSS_CSS_KS2_ks2_rsvd0_MASK) - -#define CSS_CSS_KS2_ks2_kact_MASK (0x20U) -#define CSS_CSS_KS2_ks2_kact_SHIFT (5U) -/*! ks2_kact - Key is active - */ -#define CSS_CSS_KS2_ks2_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_kact_SHIFT)) & CSS_CSS_KS2_ks2_kact_MASK) - -#define CSS_CSS_KS2_ks2_kbase_MASK (0x40U) -#define CSS_CSS_KS2_ks2_kbase_SHIFT (6U) -/*! ks2_kbase - First slot in a multislot key - */ -#define CSS_CSS_KS2_ks2_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_kbase_SHIFT)) & CSS_CSS_KS2_ks2_kbase_MASK) - -#define CSS_CSS_KS2_ks2_fgp_MASK (0x80U) -#define CSS_CSS_KS2_ks2_fgp_SHIFT (7U) -/*! ks2_fgp - Hardware Feature General Purpose - */ -#define CSS_CSS_KS2_ks2_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_fgp_SHIFT)) & CSS_CSS_KS2_ks2_fgp_MASK) - -#define CSS_CSS_KS2_ks2_frtn_MASK (0x100U) -#define CSS_CSS_KS2_ks2_frtn_SHIFT (8U) -/*! ks2_frtn - Hardware Feature Retention - */ -#define CSS_CSS_KS2_ks2_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_frtn_SHIFT)) & CSS_CSS_KS2_ks2_frtn_MASK) - -#define CSS_CSS_KS2_ks2_fhwo_MASK (0x200U) -#define CSS_CSS_KS2_ks2_fhwo_SHIFT (9U) -/*! ks2_fhwo - Hardware Feature Output - */ -#define CSS_CSS_KS2_ks2_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_fhwo_SHIFT)) & CSS_CSS_KS2_ks2_fhwo_MASK) - -#define CSS_CSS_KS2_ks2_rsvd1_MASK (0x1C00U) -#define CSS_CSS_KS2_ks2_rsvd1_SHIFT (10U) -/*! ks2_rsvd1 - Reserved 1 - */ -#define CSS_CSS_KS2_ks2_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_rsvd1_SHIFT)) & CSS_CSS_KS2_ks2_rsvd1_MASK) - -#define CSS_CSS_KS2_ks2_ucmac_MASK (0x2000U) -#define CSS_CSS_KS2_ks2_ucmac_SHIFT (13U) -/*! ks2_ucmac - CMAC key - */ -#define CSS_CSS_KS2_ks2_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_ucmac_SHIFT)) & CSS_CSS_KS2_ks2_ucmac_MASK) - -#define CSS_CSS_KS2_ks2_uksk_MASK (0x4000U) -#define CSS_CSS_KS2_ks2_uksk_SHIFT (14U) -/*! ks2_uksk - KSK key - */ -#define CSS_CSS_KS2_ks2_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uksk_SHIFT)) & CSS_CSS_KS2_ks2_uksk_MASK) - -#define CSS_CSS_KS2_ks2_urtf_MASK (0x8000U) -#define CSS_CSS_KS2_ks2_urtf_SHIFT (15U) -/*! ks2_urtf - Real Time Fingerprint key - */ -#define CSS_CSS_KS2_ks2_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_urtf_SHIFT)) & CSS_CSS_KS2_ks2_urtf_MASK) - -#define CSS_CSS_KS2_ks2_uckdf_MASK (0x10000U) -#define CSS_CSS_KS2_ks2_uckdf_SHIFT (16U) -/*! ks2_uckdf - Derivation key for CKDF command - */ -#define CSS_CSS_KS2_ks2_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uckdf_SHIFT)) & CSS_CSS_KS2_ks2_uckdf_MASK) - -#define CSS_CSS_KS2_ks2_uhkdf_MASK (0x20000U) -#define CSS_CSS_KS2_ks2_uhkdf_SHIFT (17U) -/*! ks2_uhkdf - Derivation key for HKDF command - */ -#define CSS_CSS_KS2_ks2_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uhkdf_SHIFT)) & CSS_CSS_KS2_ks2_uhkdf_MASK) - -#define CSS_CSS_KS2_ks2_uecsg_MASK (0x40000U) -#define CSS_CSS_KS2_ks2_uecsg_SHIFT (18U) -/*! ks2_uecsg - Ecc signing key - */ -#define CSS_CSS_KS2_ks2_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uecsg_SHIFT)) & CSS_CSS_KS2_ks2_uecsg_MASK) - -#define CSS_CSS_KS2_ks2_uecdh_MASK (0x80000U) -#define CSS_CSS_KS2_ks2_uecdh_SHIFT (19U) -/*! ks2_uecdh - Ecc diffie hellman key - */ -#define CSS_CSS_KS2_ks2_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uecdh_SHIFT)) & CSS_CSS_KS2_ks2_uecdh_MASK) - -#define CSS_CSS_KS2_ks2_uaes_MASK (0x100000U) -#define CSS_CSS_KS2_ks2_uaes_SHIFT (20U) -/*! ks2_uaes - Aes key - */ -#define CSS_CSS_KS2_ks2_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uaes_SHIFT)) & CSS_CSS_KS2_ks2_uaes_MASK) - -#define CSS_CSS_KS2_ks2_uhmac_MASK (0x200000U) -#define CSS_CSS_KS2_ks2_uhmac_SHIFT (21U) -/*! ks2_uhmac - Hmac key - */ -#define CSS_CSS_KS2_ks2_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uhmac_SHIFT)) & CSS_CSS_KS2_ks2_uhmac_MASK) - -#define CSS_CSS_KS2_ks2_ukwk_MASK (0x400000U) -#define CSS_CSS_KS2_ks2_ukwk_SHIFT (22U) -/*! ks2_ukwk - Key wrapping key - */ -#define CSS_CSS_KS2_ks2_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_ukwk_SHIFT)) & CSS_CSS_KS2_ks2_ukwk_MASK) - -#define CSS_CSS_KS2_ks2_ukuok_MASK (0x800000U) -#define CSS_CSS_KS2_ks2_ukuok_SHIFT (23U) -/*! ks2_ukuok - Key unwrapping key - */ -#define CSS_CSS_KS2_ks2_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_ukuok_SHIFT)) & CSS_CSS_KS2_ks2_ukuok_MASK) - -#define CSS_CSS_KS2_ks2_utlspms_MASK (0x1000000U) -#define CSS_CSS_KS2_ks2_utlspms_SHIFT (24U) -/*! ks2_utlspms - TLS Pre Master Secret - */ -#define CSS_CSS_KS2_ks2_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_utlspms_SHIFT)) & CSS_CSS_KS2_ks2_utlspms_MASK) - -#define CSS_CSS_KS2_ks2_utlsms_MASK (0x2000000U) -#define CSS_CSS_KS2_ks2_utlsms_SHIFT (25U) -/*! ks2_utlsms - TLS Master Secret - */ -#define CSS_CSS_KS2_ks2_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_utlsms_SHIFT)) & CSS_CSS_KS2_ks2_utlsms_MASK) - -#define CSS_CSS_KS2_ks2_ukgsrc_MASK (0x4000000U) -#define CSS_CSS_KS2_ks2_ukgsrc_SHIFT (26U) -/*! ks2_ukgsrc - Supply KEYGEN source - */ -#define CSS_CSS_KS2_ks2_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_ukgsrc_SHIFT)) & CSS_CSS_KS2_ks2_ukgsrc_MASK) - -#define CSS_CSS_KS2_ks2_uhwo_MASK (0x8000000U) -#define CSS_CSS_KS2_ks2_uhwo_SHIFT (27U) -/*! ks2_uhwo - Hardware out key - */ -#define CSS_CSS_KS2_ks2_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uhwo_SHIFT)) & CSS_CSS_KS2_ks2_uhwo_MASK) - -#define CSS_CSS_KS2_ks2_uwrpok_MASK (0x10000000U) -#define CSS_CSS_KS2_ks2_uwrpok_SHIFT (28U) -/*! ks2_uwrpok - Ok to wrap key - */ -#define CSS_CSS_KS2_ks2_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uwrpok_SHIFT)) & CSS_CSS_KS2_ks2_uwrpok_MASK) - -#define CSS_CSS_KS2_ks2_uduk_MASK (0x20000000U) -#define CSS_CSS_KS2_ks2_uduk_SHIFT (29U) -/*! ks2_uduk - Device Unique Key - */ -#define CSS_CSS_KS2_ks2_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uduk_SHIFT)) & CSS_CSS_KS2_ks2_uduk_MASK) - -#define CSS_CSS_KS2_ks2_upprot_MASK (0xC0000000U) -#define CSS_CSS_KS2_ks2_upprot_SHIFT (30U) -/*! ks2_upprot - Priviledge level - */ -#define CSS_CSS_KS2_ks2_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_upprot_SHIFT)) & CSS_CSS_KS2_ks2_upprot_MASK) -/*! @} */ - -/*! @name CSS_KS3 - Status register */ -/*! @{ */ - -#define CSS_CSS_KS3_ks3_ksize_MASK (0x1U) -#define CSS_CSS_KS3_ks3_ksize_SHIFT (0U) -/*! ks3_ksize - Key size: 0-128, 1-256 - */ -#define CSS_CSS_KS3_ks3_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_ksize_SHIFT)) & CSS_CSS_KS3_ks3_ksize_MASK) - -#define CSS_CSS_KS3_ks3_rsvd0_MASK (0x1EU) -#define CSS_CSS_KS3_ks3_rsvd0_SHIFT (1U) -/*! ks3_rsvd0 - Reserved 0 - */ -#define CSS_CSS_KS3_ks3_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_rsvd0_SHIFT)) & CSS_CSS_KS3_ks3_rsvd0_MASK) - -#define CSS_CSS_KS3_ks3_kact_MASK (0x20U) -#define CSS_CSS_KS3_ks3_kact_SHIFT (5U) -/*! ks3_kact - Key is active - */ -#define CSS_CSS_KS3_ks3_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_kact_SHIFT)) & CSS_CSS_KS3_ks3_kact_MASK) - -#define CSS_CSS_KS3_ks3_kbase_MASK (0x40U) -#define CSS_CSS_KS3_ks3_kbase_SHIFT (6U) -/*! ks3_kbase - First slot in a multislot key - */ -#define CSS_CSS_KS3_ks3_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_kbase_SHIFT)) & CSS_CSS_KS3_ks3_kbase_MASK) - -#define CSS_CSS_KS3_ks3_fgp_MASK (0x80U) -#define CSS_CSS_KS3_ks3_fgp_SHIFT (7U) -/*! ks3_fgp - Hardware Feature General Purpose - */ -#define CSS_CSS_KS3_ks3_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_fgp_SHIFT)) & CSS_CSS_KS3_ks3_fgp_MASK) - -#define CSS_CSS_KS3_ks3_frtn_MASK (0x100U) -#define CSS_CSS_KS3_ks3_frtn_SHIFT (8U) -/*! ks3_frtn - Hardware Feature Retention - */ -#define CSS_CSS_KS3_ks3_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_frtn_SHIFT)) & CSS_CSS_KS3_ks3_frtn_MASK) - -#define CSS_CSS_KS3_ks3_fhwo_MASK (0x200U) -#define CSS_CSS_KS3_ks3_fhwo_SHIFT (9U) -/*! ks3_fhwo - Hardware Feature Output - */ -#define CSS_CSS_KS3_ks3_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_fhwo_SHIFT)) & CSS_CSS_KS3_ks3_fhwo_MASK) - -#define CSS_CSS_KS3_ks3_rsvd1_MASK (0x1C00U) -#define CSS_CSS_KS3_ks3_rsvd1_SHIFT (10U) -/*! ks3_rsvd1 - Reserved 1 - */ -#define CSS_CSS_KS3_ks3_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_rsvd1_SHIFT)) & CSS_CSS_KS3_ks3_rsvd1_MASK) - -#define CSS_CSS_KS3_ks3_ucmac_MASK (0x2000U) -#define CSS_CSS_KS3_ks3_ucmac_SHIFT (13U) -/*! ks3_ucmac - CMAC key - */ -#define CSS_CSS_KS3_ks3_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_ucmac_SHIFT)) & CSS_CSS_KS3_ks3_ucmac_MASK) - -#define CSS_CSS_KS3_ks3_uksk_MASK (0x4000U) -#define CSS_CSS_KS3_ks3_uksk_SHIFT (14U) -/*! ks3_uksk - KSK key - */ -#define CSS_CSS_KS3_ks3_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uksk_SHIFT)) & CSS_CSS_KS3_ks3_uksk_MASK) - -#define CSS_CSS_KS3_ks3_urtf_MASK (0x8000U) -#define CSS_CSS_KS3_ks3_urtf_SHIFT (15U) -/*! ks3_urtf - Real Time Fingerprint key - */ -#define CSS_CSS_KS3_ks3_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_urtf_SHIFT)) & CSS_CSS_KS3_ks3_urtf_MASK) - -#define CSS_CSS_KS3_ks3_uckdf_MASK (0x10000U) -#define CSS_CSS_KS3_ks3_uckdf_SHIFT (16U) -/*! ks3_uckdf - Derivation key for CKDF command - */ -#define CSS_CSS_KS3_ks3_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uckdf_SHIFT)) & CSS_CSS_KS3_ks3_uckdf_MASK) - -#define CSS_CSS_KS3_ks3_uhkdf_MASK (0x20000U) -#define CSS_CSS_KS3_ks3_uhkdf_SHIFT (17U) -/*! ks3_uhkdf - Derivation key for HKDF command - */ -#define CSS_CSS_KS3_ks3_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uhkdf_SHIFT)) & CSS_CSS_KS3_ks3_uhkdf_MASK) - -#define CSS_CSS_KS3_ks3_uecsg_MASK (0x40000U) -#define CSS_CSS_KS3_ks3_uecsg_SHIFT (18U) -/*! ks3_uecsg - Ecc signing key - */ -#define CSS_CSS_KS3_ks3_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uecsg_SHIFT)) & CSS_CSS_KS3_ks3_uecsg_MASK) - -#define CSS_CSS_KS3_ks3_uecdh_MASK (0x80000U) -#define CSS_CSS_KS3_ks3_uecdh_SHIFT (19U) -/*! ks3_uecdh - Ecc diffie hellman key - */ -#define CSS_CSS_KS3_ks3_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uecdh_SHIFT)) & CSS_CSS_KS3_ks3_uecdh_MASK) - -#define CSS_CSS_KS3_ks3_uaes_MASK (0x100000U) -#define CSS_CSS_KS3_ks3_uaes_SHIFT (20U) -/*! ks3_uaes - Aes key - */ -#define CSS_CSS_KS3_ks3_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uaes_SHIFT)) & CSS_CSS_KS3_ks3_uaes_MASK) - -#define CSS_CSS_KS3_ks3_uhmac_MASK (0x200000U) -#define CSS_CSS_KS3_ks3_uhmac_SHIFT (21U) -/*! ks3_uhmac - Hmac key - */ -#define CSS_CSS_KS3_ks3_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uhmac_SHIFT)) & CSS_CSS_KS3_ks3_uhmac_MASK) - -#define CSS_CSS_KS3_ks3_ukwk_MASK (0x400000U) -#define CSS_CSS_KS3_ks3_ukwk_SHIFT (22U) -/*! ks3_ukwk - Key wrapping key - */ -#define CSS_CSS_KS3_ks3_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_ukwk_SHIFT)) & CSS_CSS_KS3_ks3_ukwk_MASK) - -#define CSS_CSS_KS3_ks3_ukuok_MASK (0x800000U) -#define CSS_CSS_KS3_ks3_ukuok_SHIFT (23U) -/*! ks3_ukuok - Key unwrapping key - */ -#define CSS_CSS_KS3_ks3_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_ukuok_SHIFT)) & CSS_CSS_KS3_ks3_ukuok_MASK) - -#define CSS_CSS_KS3_ks3_utlspms_MASK (0x1000000U) -#define CSS_CSS_KS3_ks3_utlspms_SHIFT (24U) -/*! ks3_utlspms - TLS Pre Master Secret - */ -#define CSS_CSS_KS3_ks3_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_utlspms_SHIFT)) & CSS_CSS_KS3_ks3_utlspms_MASK) - -#define CSS_CSS_KS3_ks3_utlsms_MASK (0x2000000U) -#define CSS_CSS_KS3_ks3_utlsms_SHIFT (25U) -/*! ks3_utlsms - TLS Master Secret - */ -#define CSS_CSS_KS3_ks3_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_utlsms_SHIFT)) & CSS_CSS_KS3_ks3_utlsms_MASK) - -#define CSS_CSS_KS3_ks3_ukgsrc_MASK (0x4000000U) -#define CSS_CSS_KS3_ks3_ukgsrc_SHIFT (26U) -/*! ks3_ukgsrc - Supply KEYGEN source - */ -#define CSS_CSS_KS3_ks3_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_ukgsrc_SHIFT)) & CSS_CSS_KS3_ks3_ukgsrc_MASK) - -#define CSS_CSS_KS3_ks3_uhwo_MASK (0x8000000U) -#define CSS_CSS_KS3_ks3_uhwo_SHIFT (27U) -/*! ks3_uhwo - Hardware out key - */ -#define CSS_CSS_KS3_ks3_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uhwo_SHIFT)) & CSS_CSS_KS3_ks3_uhwo_MASK) - -#define CSS_CSS_KS3_ks3_uwrpok_MASK (0x10000000U) -#define CSS_CSS_KS3_ks3_uwrpok_SHIFT (28U) -/*! ks3_uwrpok - Ok to wrap key - */ -#define CSS_CSS_KS3_ks3_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uwrpok_SHIFT)) & CSS_CSS_KS3_ks3_uwrpok_MASK) - -#define CSS_CSS_KS3_ks3_uduk_MASK (0x20000000U) -#define CSS_CSS_KS3_ks3_uduk_SHIFT (29U) -/*! ks3_uduk - Device Unique Key - */ -#define CSS_CSS_KS3_ks3_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uduk_SHIFT)) & CSS_CSS_KS3_ks3_uduk_MASK) - -#define CSS_CSS_KS3_ks3_upprot_MASK (0xC0000000U) -#define CSS_CSS_KS3_ks3_upprot_SHIFT (30U) -/*! ks3_upprot - Priviledge level - */ -#define CSS_CSS_KS3_ks3_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_upprot_SHIFT)) & CSS_CSS_KS3_ks3_upprot_MASK) -/*! @} */ - -/*! @name CSS_KS4 - Status register */ -/*! @{ */ - -#define CSS_CSS_KS4_ks4_ksize_MASK (0x1U) -#define CSS_CSS_KS4_ks4_ksize_SHIFT (0U) -/*! ks4_ksize - Key size: 0-128, 1-256 - */ -#define CSS_CSS_KS4_ks4_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_ksize_SHIFT)) & CSS_CSS_KS4_ks4_ksize_MASK) - -#define CSS_CSS_KS4_ks4_rsvd0_MASK (0x1EU) -#define CSS_CSS_KS4_ks4_rsvd0_SHIFT (1U) -/*! ks4_rsvd0 - Reserved 0 - */ -#define CSS_CSS_KS4_ks4_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_rsvd0_SHIFT)) & CSS_CSS_KS4_ks4_rsvd0_MASK) - -#define CSS_CSS_KS4_ks4_kact_MASK (0x20U) -#define CSS_CSS_KS4_ks4_kact_SHIFT (5U) -/*! ks4_kact - Key is active - */ -#define CSS_CSS_KS4_ks4_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_kact_SHIFT)) & CSS_CSS_KS4_ks4_kact_MASK) - -#define CSS_CSS_KS4_ks4_kbase_MASK (0x40U) -#define CSS_CSS_KS4_ks4_kbase_SHIFT (6U) -/*! ks4_kbase - First slot in a multislot key - */ -#define CSS_CSS_KS4_ks4_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_kbase_SHIFT)) & CSS_CSS_KS4_ks4_kbase_MASK) - -#define CSS_CSS_KS4_ks4_fgp_MASK (0x80U) -#define CSS_CSS_KS4_ks4_fgp_SHIFT (7U) -/*! ks4_fgp - Hardware Feature General Purpose - */ -#define CSS_CSS_KS4_ks4_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_fgp_SHIFT)) & CSS_CSS_KS4_ks4_fgp_MASK) - -#define CSS_CSS_KS4_ks4_frtn_MASK (0x100U) -#define CSS_CSS_KS4_ks4_frtn_SHIFT (8U) -/*! ks4_frtn - Hardware Feature Retention - */ -#define CSS_CSS_KS4_ks4_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_frtn_SHIFT)) & CSS_CSS_KS4_ks4_frtn_MASK) - -#define CSS_CSS_KS4_ks4_fhwo_MASK (0x200U) -#define CSS_CSS_KS4_ks4_fhwo_SHIFT (9U) -/*! ks4_fhwo - Hardware Feature Output - */ -#define CSS_CSS_KS4_ks4_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_fhwo_SHIFT)) & CSS_CSS_KS4_ks4_fhwo_MASK) - -#define CSS_CSS_KS4_ks4_rsvd1_MASK (0x1C00U) -#define CSS_CSS_KS4_ks4_rsvd1_SHIFT (10U) -/*! ks4_rsvd1 - Reserved 1 - */ -#define CSS_CSS_KS4_ks4_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_rsvd1_SHIFT)) & CSS_CSS_KS4_ks4_rsvd1_MASK) - -#define CSS_CSS_KS4_ks4_ucmac_MASK (0x2000U) -#define CSS_CSS_KS4_ks4_ucmac_SHIFT (13U) -/*! ks4_ucmac - CMAC key - */ -#define CSS_CSS_KS4_ks4_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_ucmac_SHIFT)) & CSS_CSS_KS4_ks4_ucmac_MASK) - -#define CSS_CSS_KS4_ks4_uksk_MASK (0x4000U) -#define CSS_CSS_KS4_ks4_uksk_SHIFT (14U) -/*! ks4_uksk - KSK key - */ -#define CSS_CSS_KS4_ks4_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uksk_SHIFT)) & CSS_CSS_KS4_ks4_uksk_MASK) - -#define CSS_CSS_KS4_ks4_urtf_MASK (0x8000U) -#define CSS_CSS_KS4_ks4_urtf_SHIFT (15U) -/*! ks4_urtf - Real Time Fingerprint key - */ -#define CSS_CSS_KS4_ks4_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_urtf_SHIFT)) & CSS_CSS_KS4_ks4_urtf_MASK) - -#define CSS_CSS_KS4_ks4_uckdf_MASK (0x10000U) -#define CSS_CSS_KS4_ks4_uckdf_SHIFT (16U) -/*! ks4_uckdf - Derivation key for CKDF command - */ -#define CSS_CSS_KS4_ks4_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uckdf_SHIFT)) & CSS_CSS_KS4_ks4_uckdf_MASK) - -#define CSS_CSS_KS4_ks4_uhkdf_MASK (0x20000U) -#define CSS_CSS_KS4_ks4_uhkdf_SHIFT (17U) -/*! ks4_uhkdf - Derivation key for HKDF command - */ -#define CSS_CSS_KS4_ks4_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uhkdf_SHIFT)) & CSS_CSS_KS4_ks4_uhkdf_MASK) - -#define CSS_CSS_KS4_ks4_uecsg_MASK (0x40000U) -#define CSS_CSS_KS4_ks4_uecsg_SHIFT (18U) -/*! ks4_uecsg - Ecc signing key - */ -#define CSS_CSS_KS4_ks4_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uecsg_SHIFT)) & CSS_CSS_KS4_ks4_uecsg_MASK) - -#define CSS_CSS_KS4_ks4_uecdh_MASK (0x80000U) -#define CSS_CSS_KS4_ks4_uecdh_SHIFT (19U) -/*! ks4_uecdh - Ecc diffie hellman key - */ -#define CSS_CSS_KS4_ks4_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uecdh_SHIFT)) & CSS_CSS_KS4_ks4_uecdh_MASK) - -#define CSS_CSS_KS4_ks4_uaes_MASK (0x100000U) -#define CSS_CSS_KS4_ks4_uaes_SHIFT (20U) -/*! ks4_uaes - Aes key - */ -#define CSS_CSS_KS4_ks4_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uaes_SHIFT)) & CSS_CSS_KS4_ks4_uaes_MASK) - -#define CSS_CSS_KS4_ks4_uhmac_MASK (0x200000U) -#define CSS_CSS_KS4_ks4_uhmac_SHIFT (21U) -/*! ks4_uhmac - Hmac key - */ -#define CSS_CSS_KS4_ks4_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uhmac_SHIFT)) & CSS_CSS_KS4_ks4_uhmac_MASK) - -#define CSS_CSS_KS4_ks4_ukwk_MASK (0x400000U) -#define CSS_CSS_KS4_ks4_ukwk_SHIFT (22U) -/*! ks4_ukwk - Key wrapping key - */ -#define CSS_CSS_KS4_ks4_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_ukwk_SHIFT)) & CSS_CSS_KS4_ks4_ukwk_MASK) - -#define CSS_CSS_KS4_ks4_ukuok_MASK (0x800000U) -#define CSS_CSS_KS4_ks4_ukuok_SHIFT (23U) -/*! ks4_ukuok - Key unwrapping key - */ -#define CSS_CSS_KS4_ks4_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_ukuok_SHIFT)) & CSS_CSS_KS4_ks4_ukuok_MASK) - -#define CSS_CSS_KS4_ks4_utlspms_MASK (0x1000000U) -#define CSS_CSS_KS4_ks4_utlspms_SHIFT (24U) -/*! ks4_utlspms - TLS Pre Master Secret - */ -#define CSS_CSS_KS4_ks4_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_utlspms_SHIFT)) & CSS_CSS_KS4_ks4_utlspms_MASK) - -#define CSS_CSS_KS4_ks4_utlsms_MASK (0x2000000U) -#define CSS_CSS_KS4_ks4_utlsms_SHIFT (25U) -/*! ks4_utlsms - TLS Master Secret - */ -#define CSS_CSS_KS4_ks4_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_utlsms_SHIFT)) & CSS_CSS_KS4_ks4_utlsms_MASK) - -#define CSS_CSS_KS4_ks4_ukgsrc_MASK (0x4000000U) -#define CSS_CSS_KS4_ks4_ukgsrc_SHIFT (26U) -/*! ks4_ukgsrc - Supply KEYGEN source - */ -#define CSS_CSS_KS4_ks4_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_ukgsrc_SHIFT)) & CSS_CSS_KS4_ks4_ukgsrc_MASK) - -#define CSS_CSS_KS4_ks4_uhwo_MASK (0x8000000U) -#define CSS_CSS_KS4_ks4_uhwo_SHIFT (27U) -/*! ks4_uhwo - Hardware out key - */ -#define CSS_CSS_KS4_ks4_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uhwo_SHIFT)) & CSS_CSS_KS4_ks4_uhwo_MASK) - -#define CSS_CSS_KS4_ks4_uwrpok_MASK (0x10000000U) -#define CSS_CSS_KS4_ks4_uwrpok_SHIFT (28U) -/*! ks4_uwrpok - Ok to wrap key - */ -#define CSS_CSS_KS4_ks4_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uwrpok_SHIFT)) & CSS_CSS_KS4_ks4_uwrpok_MASK) - -#define CSS_CSS_KS4_ks4_uduk_MASK (0x20000000U) -#define CSS_CSS_KS4_ks4_uduk_SHIFT (29U) -/*! ks4_uduk - Device Unique Key - */ -#define CSS_CSS_KS4_ks4_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uduk_SHIFT)) & CSS_CSS_KS4_ks4_uduk_MASK) - -#define CSS_CSS_KS4_ks4_upprot_MASK (0xC0000000U) -#define CSS_CSS_KS4_ks4_upprot_SHIFT (30U) -/*! ks4_upprot - Priviledge level - */ -#define CSS_CSS_KS4_ks4_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_upprot_SHIFT)) & CSS_CSS_KS4_ks4_upprot_MASK) -/*! @} */ - -/*! @name CSS_KS5 - Status register */ -/*! @{ */ - -#define CSS_CSS_KS5_ks5_ksize_MASK (0x1U) -#define CSS_CSS_KS5_ks5_ksize_SHIFT (0U) -/*! ks5_ksize - Key size: 0-128, 1-256 - */ -#define CSS_CSS_KS5_ks5_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_ksize_SHIFT)) & CSS_CSS_KS5_ks5_ksize_MASK) - -#define CSS_CSS_KS5_ks5_rsvd0_MASK (0x1EU) -#define CSS_CSS_KS5_ks5_rsvd0_SHIFT (1U) -/*! ks5_rsvd0 - Reserved 0 - */ -#define CSS_CSS_KS5_ks5_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_rsvd0_SHIFT)) & CSS_CSS_KS5_ks5_rsvd0_MASK) - -#define CSS_CSS_KS5_ks5_kact_MASK (0x20U) -#define CSS_CSS_KS5_ks5_kact_SHIFT (5U) -/*! ks5_kact - Key is active - */ -#define CSS_CSS_KS5_ks5_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_kact_SHIFT)) & CSS_CSS_KS5_ks5_kact_MASK) - -#define CSS_CSS_KS5_ks5_kbase_MASK (0x40U) -#define CSS_CSS_KS5_ks5_kbase_SHIFT (6U) -/*! ks5_kbase - First slot in a multislot key - */ -#define CSS_CSS_KS5_ks5_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_kbase_SHIFT)) & CSS_CSS_KS5_ks5_kbase_MASK) - -#define CSS_CSS_KS5_ks5_fgp_MASK (0x80U) -#define CSS_CSS_KS5_ks5_fgp_SHIFT (7U) -/*! ks5_fgp - Hardware Feature General Purpose - */ -#define CSS_CSS_KS5_ks5_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_fgp_SHIFT)) & CSS_CSS_KS5_ks5_fgp_MASK) - -#define CSS_CSS_KS5_ks5_frtn_MASK (0x100U) -#define CSS_CSS_KS5_ks5_frtn_SHIFT (8U) -/*! ks5_frtn - Hardware Feature Retention - */ -#define CSS_CSS_KS5_ks5_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_frtn_SHIFT)) & CSS_CSS_KS5_ks5_frtn_MASK) - -#define CSS_CSS_KS5_ks5_fhwo_MASK (0x200U) -#define CSS_CSS_KS5_ks5_fhwo_SHIFT (9U) -/*! ks5_fhwo - Hardware Feature Output - */ -#define CSS_CSS_KS5_ks5_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_fhwo_SHIFT)) & CSS_CSS_KS5_ks5_fhwo_MASK) - -#define CSS_CSS_KS5_ks5_rsvd1_MASK (0x1C00U) -#define CSS_CSS_KS5_ks5_rsvd1_SHIFT (10U) -/*! ks5_rsvd1 - Reserved 1 - */ -#define CSS_CSS_KS5_ks5_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_rsvd1_SHIFT)) & CSS_CSS_KS5_ks5_rsvd1_MASK) - -#define CSS_CSS_KS5_ks5_ucmac_MASK (0x2000U) -#define CSS_CSS_KS5_ks5_ucmac_SHIFT (13U) -/*! ks5_ucmac - CMAC key - */ -#define CSS_CSS_KS5_ks5_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_ucmac_SHIFT)) & CSS_CSS_KS5_ks5_ucmac_MASK) - -#define CSS_CSS_KS5_ks5_uksk_MASK (0x4000U) -#define CSS_CSS_KS5_ks5_uksk_SHIFT (14U) -/*! ks5_uksk - KSK key - */ -#define CSS_CSS_KS5_ks5_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uksk_SHIFT)) & CSS_CSS_KS5_ks5_uksk_MASK) - -#define CSS_CSS_KS5_ks5_urtf_MASK (0x8000U) -#define CSS_CSS_KS5_ks5_urtf_SHIFT (15U) -/*! ks5_urtf - Real Time Fingerprint key - */ -#define CSS_CSS_KS5_ks5_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_urtf_SHIFT)) & CSS_CSS_KS5_ks5_urtf_MASK) - -#define CSS_CSS_KS5_ks5_uckdf_MASK (0x10000U) -#define CSS_CSS_KS5_ks5_uckdf_SHIFT (16U) -/*! ks5_uckdf - Derivation key for CKDF command - */ -#define CSS_CSS_KS5_ks5_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uckdf_SHIFT)) & CSS_CSS_KS5_ks5_uckdf_MASK) - -#define CSS_CSS_KS5_ks5_uhkdf_MASK (0x20000U) -#define CSS_CSS_KS5_ks5_uhkdf_SHIFT (17U) -/*! ks5_uhkdf - Derivation key for HKDF command - */ -#define CSS_CSS_KS5_ks5_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uhkdf_SHIFT)) & CSS_CSS_KS5_ks5_uhkdf_MASK) - -#define CSS_CSS_KS5_ks5_uecsg_MASK (0x40000U) -#define CSS_CSS_KS5_ks5_uecsg_SHIFT (18U) -/*! ks5_uecsg - Ecc signing key - */ -#define CSS_CSS_KS5_ks5_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uecsg_SHIFT)) & CSS_CSS_KS5_ks5_uecsg_MASK) - -#define CSS_CSS_KS5_ks5_uecdh_MASK (0x80000U) -#define CSS_CSS_KS5_ks5_uecdh_SHIFT (19U) -/*! ks5_uecdh - Ecc diffie hellman key - */ -#define CSS_CSS_KS5_ks5_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uecdh_SHIFT)) & CSS_CSS_KS5_ks5_uecdh_MASK) - -#define CSS_CSS_KS5_ks5_uaes_MASK (0x100000U) -#define CSS_CSS_KS5_ks5_uaes_SHIFT (20U) -/*! ks5_uaes - Aes key - */ -#define CSS_CSS_KS5_ks5_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uaes_SHIFT)) & CSS_CSS_KS5_ks5_uaes_MASK) - -#define CSS_CSS_KS5_ks5_uhmac_MASK (0x200000U) -#define CSS_CSS_KS5_ks5_uhmac_SHIFT (21U) -/*! ks5_uhmac - Hmac key - */ -#define CSS_CSS_KS5_ks5_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uhmac_SHIFT)) & CSS_CSS_KS5_ks5_uhmac_MASK) - -#define CSS_CSS_KS5_ks5_ukwk_MASK (0x400000U) -#define CSS_CSS_KS5_ks5_ukwk_SHIFT (22U) -/*! ks5_ukwk - Key wrapping key - */ -#define CSS_CSS_KS5_ks5_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_ukwk_SHIFT)) & CSS_CSS_KS5_ks5_ukwk_MASK) - -#define CSS_CSS_KS5_ks5_ukuok_MASK (0x800000U) -#define CSS_CSS_KS5_ks5_ukuok_SHIFT (23U) -/*! ks5_ukuok - Key unwrapping key - */ -#define CSS_CSS_KS5_ks5_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_ukuok_SHIFT)) & CSS_CSS_KS5_ks5_ukuok_MASK) - -#define CSS_CSS_KS5_ks5_utlspms_MASK (0x1000000U) -#define CSS_CSS_KS5_ks5_utlspms_SHIFT (24U) -/*! ks5_utlspms - TLS Pre Master Secret - */ -#define CSS_CSS_KS5_ks5_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_utlspms_SHIFT)) & CSS_CSS_KS5_ks5_utlspms_MASK) - -#define CSS_CSS_KS5_ks5_utlsms_MASK (0x2000000U) -#define CSS_CSS_KS5_ks5_utlsms_SHIFT (25U) -/*! ks5_utlsms - TLS Master Secret - */ -#define CSS_CSS_KS5_ks5_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_utlsms_SHIFT)) & CSS_CSS_KS5_ks5_utlsms_MASK) - -#define CSS_CSS_KS5_ks5_ukgsrc_MASK (0x4000000U) -#define CSS_CSS_KS5_ks5_ukgsrc_SHIFT (26U) -/*! ks5_ukgsrc - Supply KEYGEN source - */ -#define CSS_CSS_KS5_ks5_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_ukgsrc_SHIFT)) & CSS_CSS_KS5_ks5_ukgsrc_MASK) - -#define CSS_CSS_KS5_ks5_uhwo_MASK (0x8000000U) -#define CSS_CSS_KS5_ks5_uhwo_SHIFT (27U) -/*! ks5_uhwo - Hardware out key - */ -#define CSS_CSS_KS5_ks5_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uhwo_SHIFT)) & CSS_CSS_KS5_ks5_uhwo_MASK) - -#define CSS_CSS_KS5_ks5_uwrpok_MASK (0x10000000U) -#define CSS_CSS_KS5_ks5_uwrpok_SHIFT (28U) -/*! ks5_uwrpok - Ok to wrap key - */ -#define CSS_CSS_KS5_ks5_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uwrpok_SHIFT)) & CSS_CSS_KS5_ks5_uwrpok_MASK) - -#define CSS_CSS_KS5_ks5_uduk_MASK (0x20000000U) -#define CSS_CSS_KS5_ks5_uduk_SHIFT (29U) -/*! ks5_uduk - Device Unique Key - */ -#define CSS_CSS_KS5_ks5_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uduk_SHIFT)) & CSS_CSS_KS5_ks5_uduk_MASK) - -#define CSS_CSS_KS5_ks5_upprot_MASK (0xC0000000U) -#define CSS_CSS_KS5_ks5_upprot_SHIFT (30U) -/*! ks5_upprot - Priviledge level - */ -#define CSS_CSS_KS5_ks5_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_upprot_SHIFT)) & CSS_CSS_KS5_ks5_upprot_MASK) -/*! @} */ - -/*! @name CSS_KS6 - Status register */ -/*! @{ */ - -#define CSS_CSS_KS6_ks6_ksize_MASK (0x1U) -#define CSS_CSS_KS6_ks6_ksize_SHIFT (0U) -/*! ks6_ksize - Key size: 0-128, 1-256 - */ -#define CSS_CSS_KS6_ks6_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_ksize_SHIFT)) & CSS_CSS_KS6_ks6_ksize_MASK) - -#define CSS_CSS_KS6_ks6_rsvd0_MASK (0x1EU) -#define CSS_CSS_KS6_ks6_rsvd0_SHIFT (1U) -/*! ks6_rsvd0 - Reserved 0 - */ -#define CSS_CSS_KS6_ks6_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_rsvd0_SHIFT)) & CSS_CSS_KS6_ks6_rsvd0_MASK) - -#define CSS_CSS_KS6_ks6_kact_MASK (0x20U) -#define CSS_CSS_KS6_ks6_kact_SHIFT (5U) -/*! ks6_kact - Key is active - */ -#define CSS_CSS_KS6_ks6_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_kact_SHIFT)) & CSS_CSS_KS6_ks6_kact_MASK) - -#define CSS_CSS_KS6_ks6_kbase_MASK (0x40U) -#define CSS_CSS_KS6_ks6_kbase_SHIFT (6U) -/*! ks6_kbase - First slot in a multislot key - */ -#define CSS_CSS_KS6_ks6_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_kbase_SHIFT)) & CSS_CSS_KS6_ks6_kbase_MASK) - -#define CSS_CSS_KS6_ks6_fgp_MASK (0x80U) -#define CSS_CSS_KS6_ks6_fgp_SHIFT (7U) -/*! ks6_fgp - Hardware Feature General Purpose - */ -#define CSS_CSS_KS6_ks6_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_fgp_SHIFT)) & CSS_CSS_KS6_ks6_fgp_MASK) - -#define CSS_CSS_KS6_ks6_frtn_MASK (0x100U) -#define CSS_CSS_KS6_ks6_frtn_SHIFT (8U) -/*! ks6_frtn - Hardware Feature Retention - */ -#define CSS_CSS_KS6_ks6_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_frtn_SHIFT)) & CSS_CSS_KS6_ks6_frtn_MASK) - -#define CSS_CSS_KS6_ks6_fhwo_MASK (0x200U) -#define CSS_CSS_KS6_ks6_fhwo_SHIFT (9U) -/*! ks6_fhwo - Hardware Feature Output - */ -#define CSS_CSS_KS6_ks6_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_fhwo_SHIFT)) & CSS_CSS_KS6_ks6_fhwo_MASK) - -#define CSS_CSS_KS6_ks6_rsvd1_MASK (0x1C00U) -#define CSS_CSS_KS6_ks6_rsvd1_SHIFT (10U) -/*! ks6_rsvd1 - Reserved 1 - */ -#define CSS_CSS_KS6_ks6_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_rsvd1_SHIFT)) & CSS_CSS_KS6_ks6_rsvd1_MASK) - -#define CSS_CSS_KS6_ks6_ucmac_MASK (0x2000U) -#define CSS_CSS_KS6_ks6_ucmac_SHIFT (13U) -/*! ks6_ucmac - CMAC key - */ -#define CSS_CSS_KS6_ks6_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_ucmac_SHIFT)) & CSS_CSS_KS6_ks6_ucmac_MASK) - -#define CSS_CSS_KS6_ks6_uksk_MASK (0x4000U) -#define CSS_CSS_KS6_ks6_uksk_SHIFT (14U) -/*! ks6_uksk - KSK key - */ -#define CSS_CSS_KS6_ks6_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uksk_SHIFT)) & CSS_CSS_KS6_ks6_uksk_MASK) - -#define CSS_CSS_KS6_ks6_urtf_MASK (0x8000U) -#define CSS_CSS_KS6_ks6_urtf_SHIFT (15U) -/*! ks6_urtf - Real Time Fingerprint key - */ -#define CSS_CSS_KS6_ks6_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_urtf_SHIFT)) & CSS_CSS_KS6_ks6_urtf_MASK) - -#define CSS_CSS_KS6_ks6_uckdf_MASK (0x10000U) -#define CSS_CSS_KS6_ks6_uckdf_SHIFT (16U) -/*! ks6_uckdf - Derivation key for CKDF command - */ -#define CSS_CSS_KS6_ks6_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uckdf_SHIFT)) & CSS_CSS_KS6_ks6_uckdf_MASK) - -#define CSS_CSS_KS6_ks6_uhkdf_MASK (0x20000U) -#define CSS_CSS_KS6_ks6_uhkdf_SHIFT (17U) -/*! ks6_uhkdf - Derivation key for HKDF command - */ -#define CSS_CSS_KS6_ks6_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uhkdf_SHIFT)) & CSS_CSS_KS6_ks6_uhkdf_MASK) - -#define CSS_CSS_KS6_ks6_uecsg_MASK (0x40000U) -#define CSS_CSS_KS6_ks6_uecsg_SHIFT (18U) -/*! ks6_uecsg - Ecc signing key - */ -#define CSS_CSS_KS6_ks6_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uecsg_SHIFT)) & CSS_CSS_KS6_ks6_uecsg_MASK) - -#define CSS_CSS_KS6_ks6_uecdh_MASK (0x80000U) -#define CSS_CSS_KS6_ks6_uecdh_SHIFT (19U) -/*! ks6_uecdh - Ecc diffie hellman key - */ -#define CSS_CSS_KS6_ks6_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uecdh_SHIFT)) & CSS_CSS_KS6_ks6_uecdh_MASK) - -#define CSS_CSS_KS6_ks6_uaes_MASK (0x100000U) -#define CSS_CSS_KS6_ks6_uaes_SHIFT (20U) -/*! ks6_uaes - Aes key - */ -#define CSS_CSS_KS6_ks6_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uaes_SHIFT)) & CSS_CSS_KS6_ks6_uaes_MASK) - -#define CSS_CSS_KS6_ks6_uhmac_MASK (0x200000U) -#define CSS_CSS_KS6_ks6_uhmac_SHIFT (21U) -/*! ks6_uhmac - Hmac key - */ -#define CSS_CSS_KS6_ks6_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uhmac_SHIFT)) & CSS_CSS_KS6_ks6_uhmac_MASK) - -#define CSS_CSS_KS6_ks6_ukwk_MASK (0x400000U) -#define CSS_CSS_KS6_ks6_ukwk_SHIFT (22U) -/*! ks6_ukwk - Key wrapping key - */ -#define CSS_CSS_KS6_ks6_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_ukwk_SHIFT)) & CSS_CSS_KS6_ks6_ukwk_MASK) - -#define CSS_CSS_KS6_ks6_ukuok_MASK (0x800000U) -#define CSS_CSS_KS6_ks6_ukuok_SHIFT (23U) -/*! ks6_ukuok - Key unwrapping key - */ -#define CSS_CSS_KS6_ks6_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_ukuok_SHIFT)) & CSS_CSS_KS6_ks6_ukuok_MASK) - -#define CSS_CSS_KS6_ks6_utlspms_MASK (0x1000000U) -#define CSS_CSS_KS6_ks6_utlspms_SHIFT (24U) -/*! ks6_utlspms - TLS Pre Master Secret - */ -#define CSS_CSS_KS6_ks6_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_utlspms_SHIFT)) & CSS_CSS_KS6_ks6_utlspms_MASK) - -#define CSS_CSS_KS6_ks6_utlsms_MASK (0x2000000U) -#define CSS_CSS_KS6_ks6_utlsms_SHIFT (25U) -/*! ks6_utlsms - TLS Master Secret - */ -#define CSS_CSS_KS6_ks6_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_utlsms_SHIFT)) & CSS_CSS_KS6_ks6_utlsms_MASK) - -#define CSS_CSS_KS6_ks6_ukgsrc_MASK (0x4000000U) -#define CSS_CSS_KS6_ks6_ukgsrc_SHIFT (26U) -/*! ks6_ukgsrc - Supply KEYGEN source - */ -#define CSS_CSS_KS6_ks6_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_ukgsrc_SHIFT)) & CSS_CSS_KS6_ks6_ukgsrc_MASK) - -#define CSS_CSS_KS6_ks6_uhwo_MASK (0x8000000U) -#define CSS_CSS_KS6_ks6_uhwo_SHIFT (27U) -/*! ks6_uhwo - Hardware out key - */ -#define CSS_CSS_KS6_ks6_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uhwo_SHIFT)) & CSS_CSS_KS6_ks6_uhwo_MASK) - -#define CSS_CSS_KS6_ks6_uwrpok_MASK (0x10000000U) -#define CSS_CSS_KS6_ks6_uwrpok_SHIFT (28U) -/*! ks6_uwrpok - Ok to wrap key - */ -#define CSS_CSS_KS6_ks6_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uwrpok_SHIFT)) & CSS_CSS_KS6_ks6_uwrpok_MASK) - -#define CSS_CSS_KS6_ks6_uduk_MASK (0x20000000U) -#define CSS_CSS_KS6_ks6_uduk_SHIFT (29U) -/*! ks6_uduk - Device Unique Key - */ -#define CSS_CSS_KS6_ks6_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uduk_SHIFT)) & CSS_CSS_KS6_ks6_uduk_MASK) - -#define CSS_CSS_KS6_ks6_upprot_MASK (0xC0000000U) -#define CSS_CSS_KS6_ks6_upprot_SHIFT (30U) -/*! ks6_upprot - Priviledge level - */ -#define CSS_CSS_KS6_ks6_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_upprot_SHIFT)) & CSS_CSS_KS6_ks6_upprot_MASK) -/*! @} */ - -/*! @name CSS_KS7 - Status register */ -/*! @{ */ - -#define CSS_CSS_KS7_ks7_ksize_MASK (0x1U) -#define CSS_CSS_KS7_ks7_ksize_SHIFT (0U) -/*! ks7_ksize - Key size: 0-128, 1-256 - */ -#define CSS_CSS_KS7_ks7_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_ksize_SHIFT)) & CSS_CSS_KS7_ks7_ksize_MASK) - -#define CSS_CSS_KS7_ks7_rsvd0_MASK (0x1EU) -#define CSS_CSS_KS7_ks7_rsvd0_SHIFT (1U) -/*! ks7_rsvd0 - Reserved 0 - */ -#define CSS_CSS_KS7_ks7_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_rsvd0_SHIFT)) & CSS_CSS_KS7_ks7_rsvd0_MASK) - -#define CSS_CSS_KS7_ks7_kact_MASK (0x20U) -#define CSS_CSS_KS7_ks7_kact_SHIFT (5U) -/*! ks7_kact - Key is active - */ -#define CSS_CSS_KS7_ks7_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_kact_SHIFT)) & CSS_CSS_KS7_ks7_kact_MASK) - -#define CSS_CSS_KS7_ks7_kbase_MASK (0x40U) -#define CSS_CSS_KS7_ks7_kbase_SHIFT (6U) -/*! ks7_kbase - First slot in a multislot key - */ -#define CSS_CSS_KS7_ks7_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_kbase_SHIFT)) & CSS_CSS_KS7_ks7_kbase_MASK) - -#define CSS_CSS_KS7_ks7_fgp_MASK (0x80U) -#define CSS_CSS_KS7_ks7_fgp_SHIFT (7U) -/*! ks7_fgp - Hardware Feature General Purpose - */ -#define CSS_CSS_KS7_ks7_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_fgp_SHIFT)) & CSS_CSS_KS7_ks7_fgp_MASK) - -#define CSS_CSS_KS7_ks7_frtn_MASK (0x100U) -#define CSS_CSS_KS7_ks7_frtn_SHIFT (8U) -/*! ks7_frtn - Hardware Feature Retention - */ -#define CSS_CSS_KS7_ks7_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_frtn_SHIFT)) & CSS_CSS_KS7_ks7_frtn_MASK) - -#define CSS_CSS_KS7_ks7_fhwo_MASK (0x200U) -#define CSS_CSS_KS7_ks7_fhwo_SHIFT (9U) -/*! ks7_fhwo - Hardware Feature Output - */ -#define CSS_CSS_KS7_ks7_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_fhwo_SHIFT)) & CSS_CSS_KS7_ks7_fhwo_MASK) - -#define CSS_CSS_KS7_ks7_rsvd1_MASK (0x1C00U) -#define CSS_CSS_KS7_ks7_rsvd1_SHIFT (10U) -/*! ks7_rsvd1 - Reserved 1 - */ -#define CSS_CSS_KS7_ks7_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_rsvd1_SHIFT)) & CSS_CSS_KS7_ks7_rsvd1_MASK) - -#define CSS_CSS_KS7_ks7_ucmac_MASK (0x2000U) -#define CSS_CSS_KS7_ks7_ucmac_SHIFT (13U) -/*! ks7_ucmac - CMAC key - */ -#define CSS_CSS_KS7_ks7_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_ucmac_SHIFT)) & CSS_CSS_KS7_ks7_ucmac_MASK) - -#define CSS_CSS_KS7_ks7_uksk_MASK (0x4000U) -#define CSS_CSS_KS7_ks7_uksk_SHIFT (14U) -/*! ks7_uksk - KSK key - */ -#define CSS_CSS_KS7_ks7_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uksk_SHIFT)) & CSS_CSS_KS7_ks7_uksk_MASK) - -#define CSS_CSS_KS7_ks7_urtf_MASK (0x8000U) -#define CSS_CSS_KS7_ks7_urtf_SHIFT (15U) -/*! ks7_urtf - Real Time Fingerprint key - */ -#define CSS_CSS_KS7_ks7_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_urtf_SHIFT)) & CSS_CSS_KS7_ks7_urtf_MASK) - -#define CSS_CSS_KS7_ks7_uckdf_MASK (0x10000U) -#define CSS_CSS_KS7_ks7_uckdf_SHIFT (16U) -/*! ks7_uckdf - Derivation key for CKDF command - */ -#define CSS_CSS_KS7_ks7_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uckdf_SHIFT)) & CSS_CSS_KS7_ks7_uckdf_MASK) - -#define CSS_CSS_KS7_ks7_uhkdf_MASK (0x20000U) -#define CSS_CSS_KS7_ks7_uhkdf_SHIFT (17U) -/*! ks7_uhkdf - Derivation key for HKDF command - */ -#define CSS_CSS_KS7_ks7_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uhkdf_SHIFT)) & CSS_CSS_KS7_ks7_uhkdf_MASK) - -#define CSS_CSS_KS7_ks7_uecsg_MASK (0x40000U) -#define CSS_CSS_KS7_ks7_uecsg_SHIFT (18U) -/*! ks7_uecsg - Ecc signing key - */ -#define CSS_CSS_KS7_ks7_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uecsg_SHIFT)) & CSS_CSS_KS7_ks7_uecsg_MASK) - -#define CSS_CSS_KS7_ks7_uecdh_MASK (0x80000U) -#define CSS_CSS_KS7_ks7_uecdh_SHIFT (19U) -/*! ks7_uecdh - Ecc diffie hellman key - */ -#define CSS_CSS_KS7_ks7_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uecdh_SHIFT)) & CSS_CSS_KS7_ks7_uecdh_MASK) - -#define CSS_CSS_KS7_ks7_uaes_MASK (0x100000U) -#define CSS_CSS_KS7_ks7_uaes_SHIFT (20U) -/*! ks7_uaes - Aes key - */ -#define CSS_CSS_KS7_ks7_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uaes_SHIFT)) & CSS_CSS_KS7_ks7_uaes_MASK) - -#define CSS_CSS_KS7_ks7_uhmac_MASK (0x200000U) -#define CSS_CSS_KS7_ks7_uhmac_SHIFT (21U) -/*! ks7_uhmac - Hmac key - */ -#define CSS_CSS_KS7_ks7_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uhmac_SHIFT)) & CSS_CSS_KS7_ks7_uhmac_MASK) - -#define CSS_CSS_KS7_ks7_ukwk_MASK (0x400000U) -#define CSS_CSS_KS7_ks7_ukwk_SHIFT (22U) -/*! ks7_ukwk - Key wrapping key - */ -#define CSS_CSS_KS7_ks7_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_ukwk_SHIFT)) & CSS_CSS_KS7_ks7_ukwk_MASK) - -#define CSS_CSS_KS7_ks7_ukuok_MASK (0x800000U) -#define CSS_CSS_KS7_ks7_ukuok_SHIFT (23U) -/*! ks7_ukuok - Key unwrapping key - */ -#define CSS_CSS_KS7_ks7_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_ukuok_SHIFT)) & CSS_CSS_KS7_ks7_ukuok_MASK) - -#define CSS_CSS_KS7_ks7_utlspms_MASK (0x1000000U) -#define CSS_CSS_KS7_ks7_utlspms_SHIFT (24U) -/*! ks7_utlspms - TLS Pre Master Secret - */ -#define CSS_CSS_KS7_ks7_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_utlspms_SHIFT)) & CSS_CSS_KS7_ks7_utlspms_MASK) - -#define CSS_CSS_KS7_ks7_utlsms_MASK (0x2000000U) -#define CSS_CSS_KS7_ks7_utlsms_SHIFT (25U) -/*! ks7_utlsms - TLS Master Secret - */ -#define CSS_CSS_KS7_ks7_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_utlsms_SHIFT)) & CSS_CSS_KS7_ks7_utlsms_MASK) - -#define CSS_CSS_KS7_ks7_ukgsrc_MASK (0x4000000U) -#define CSS_CSS_KS7_ks7_ukgsrc_SHIFT (26U) -/*! ks7_ukgsrc - Supply KEYGEN source - */ -#define CSS_CSS_KS7_ks7_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_ukgsrc_SHIFT)) & CSS_CSS_KS7_ks7_ukgsrc_MASK) - -#define CSS_CSS_KS7_ks7_uhwo_MASK (0x8000000U) -#define CSS_CSS_KS7_ks7_uhwo_SHIFT (27U) -/*! ks7_uhwo - Hardware out key - */ -#define CSS_CSS_KS7_ks7_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uhwo_SHIFT)) & CSS_CSS_KS7_ks7_uhwo_MASK) - -#define CSS_CSS_KS7_ks7_uwrpok_MASK (0x10000000U) -#define CSS_CSS_KS7_ks7_uwrpok_SHIFT (28U) -/*! ks7_uwrpok - Ok to wrap key - */ -#define CSS_CSS_KS7_ks7_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uwrpok_SHIFT)) & CSS_CSS_KS7_ks7_uwrpok_MASK) - -#define CSS_CSS_KS7_ks7_uduk_MASK (0x20000000U) -#define CSS_CSS_KS7_ks7_uduk_SHIFT (29U) -/*! ks7_uduk - Device Unique Key - */ -#define CSS_CSS_KS7_ks7_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uduk_SHIFT)) & CSS_CSS_KS7_ks7_uduk_MASK) - -#define CSS_CSS_KS7_ks7_upprot_MASK (0xC0000000U) -#define CSS_CSS_KS7_ks7_upprot_SHIFT (30U) -/*! ks7_upprot - Priviledge level - */ -#define CSS_CSS_KS7_ks7_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_upprot_SHIFT)) & CSS_CSS_KS7_ks7_upprot_MASK) -/*! @} */ - -/*! @name CSS_KS8 - Status register */ -/*! @{ */ - -#define CSS_CSS_KS8_ks8_ksize_MASK (0x1U) -#define CSS_CSS_KS8_ks8_ksize_SHIFT (0U) -/*! ks8_ksize - Key size: 0-128, 1-256 - */ -#define CSS_CSS_KS8_ks8_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_ksize_SHIFT)) & CSS_CSS_KS8_ks8_ksize_MASK) - -#define CSS_CSS_KS8_ks8_rsvd0_MASK (0x1EU) -#define CSS_CSS_KS8_ks8_rsvd0_SHIFT (1U) -/*! ks8_rsvd0 - Reserved 0 - */ -#define CSS_CSS_KS8_ks8_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_rsvd0_SHIFT)) & CSS_CSS_KS8_ks8_rsvd0_MASK) - -#define CSS_CSS_KS8_ks8_kact_MASK (0x20U) -#define CSS_CSS_KS8_ks8_kact_SHIFT (5U) -/*! ks8_kact - Key is active - */ -#define CSS_CSS_KS8_ks8_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_kact_SHIFT)) & CSS_CSS_KS8_ks8_kact_MASK) - -#define CSS_CSS_KS8_ks8_kbase_MASK (0x40U) -#define CSS_CSS_KS8_ks8_kbase_SHIFT (6U) -/*! ks8_kbase - First slot in a multislot key - */ -#define CSS_CSS_KS8_ks8_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_kbase_SHIFT)) & CSS_CSS_KS8_ks8_kbase_MASK) - -#define CSS_CSS_KS8_ks8_fgp_MASK (0x80U) -#define CSS_CSS_KS8_ks8_fgp_SHIFT (7U) -/*! ks8_fgp - Hardware Feature General Purpose - */ -#define CSS_CSS_KS8_ks8_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_fgp_SHIFT)) & CSS_CSS_KS8_ks8_fgp_MASK) - -#define CSS_CSS_KS8_ks8_frtn_MASK (0x100U) -#define CSS_CSS_KS8_ks8_frtn_SHIFT (8U) -/*! ks8_frtn - Hardware Feature Retention - */ -#define CSS_CSS_KS8_ks8_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_frtn_SHIFT)) & CSS_CSS_KS8_ks8_frtn_MASK) - -#define CSS_CSS_KS8_ks8_fhwo_MASK (0x200U) -#define CSS_CSS_KS8_ks8_fhwo_SHIFT (9U) -/*! ks8_fhwo - Hardware Feature Output - */ -#define CSS_CSS_KS8_ks8_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_fhwo_SHIFT)) & CSS_CSS_KS8_ks8_fhwo_MASK) - -#define CSS_CSS_KS8_ks8_rsvd1_MASK (0x1C00U) -#define CSS_CSS_KS8_ks8_rsvd1_SHIFT (10U) -/*! ks8_rsvd1 - Reserved 1 - */ -#define CSS_CSS_KS8_ks8_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_rsvd1_SHIFT)) & CSS_CSS_KS8_ks8_rsvd1_MASK) - -#define CSS_CSS_KS8_ks8_ucmac_MASK (0x2000U) -#define CSS_CSS_KS8_ks8_ucmac_SHIFT (13U) -/*! ks8_ucmac - CMAC key - */ -#define CSS_CSS_KS8_ks8_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_ucmac_SHIFT)) & CSS_CSS_KS8_ks8_ucmac_MASK) - -#define CSS_CSS_KS8_ks8_uksk_MASK (0x4000U) -#define CSS_CSS_KS8_ks8_uksk_SHIFT (14U) -/*! ks8_uksk - KSK key - */ -#define CSS_CSS_KS8_ks8_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uksk_SHIFT)) & CSS_CSS_KS8_ks8_uksk_MASK) - -#define CSS_CSS_KS8_ks8_urtf_MASK (0x8000U) -#define CSS_CSS_KS8_ks8_urtf_SHIFT (15U) -/*! ks8_urtf - Real Time Fingerprint key - */ -#define CSS_CSS_KS8_ks8_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_urtf_SHIFT)) & CSS_CSS_KS8_ks8_urtf_MASK) - -#define CSS_CSS_KS8_ks8_uckdf_MASK (0x10000U) -#define CSS_CSS_KS8_ks8_uckdf_SHIFT (16U) -/*! ks8_uckdf - Derivation key for CKDF command - */ -#define CSS_CSS_KS8_ks8_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uckdf_SHIFT)) & CSS_CSS_KS8_ks8_uckdf_MASK) - -#define CSS_CSS_KS8_ks8_uhkdf_MASK (0x20000U) -#define CSS_CSS_KS8_ks8_uhkdf_SHIFT (17U) -/*! ks8_uhkdf - Derivation key for HKDF command - */ -#define CSS_CSS_KS8_ks8_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uhkdf_SHIFT)) & CSS_CSS_KS8_ks8_uhkdf_MASK) - -#define CSS_CSS_KS8_ks8_uecsg_MASK (0x40000U) -#define CSS_CSS_KS8_ks8_uecsg_SHIFT (18U) -/*! ks8_uecsg - Ecc signing key - */ -#define CSS_CSS_KS8_ks8_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uecsg_SHIFT)) & CSS_CSS_KS8_ks8_uecsg_MASK) - -#define CSS_CSS_KS8_ks8_uecdh_MASK (0x80000U) -#define CSS_CSS_KS8_ks8_uecdh_SHIFT (19U) -/*! ks8_uecdh - Ecc diffie hellman key - */ -#define CSS_CSS_KS8_ks8_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uecdh_SHIFT)) & CSS_CSS_KS8_ks8_uecdh_MASK) - -#define CSS_CSS_KS8_ks8_uaes_MASK (0x100000U) -#define CSS_CSS_KS8_ks8_uaes_SHIFT (20U) -/*! ks8_uaes - Aes key - */ -#define CSS_CSS_KS8_ks8_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uaes_SHIFT)) & CSS_CSS_KS8_ks8_uaes_MASK) - -#define CSS_CSS_KS8_ks8_uhmac_MASK (0x200000U) -#define CSS_CSS_KS8_ks8_uhmac_SHIFT (21U) -/*! ks8_uhmac - Hmac key - */ -#define CSS_CSS_KS8_ks8_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uhmac_SHIFT)) & CSS_CSS_KS8_ks8_uhmac_MASK) - -#define CSS_CSS_KS8_ks8_ukwk_MASK (0x400000U) -#define CSS_CSS_KS8_ks8_ukwk_SHIFT (22U) -/*! ks8_ukwk - Key wrapping key - */ -#define CSS_CSS_KS8_ks8_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_ukwk_SHIFT)) & CSS_CSS_KS8_ks8_ukwk_MASK) - -#define CSS_CSS_KS8_ks8_ukuok_MASK (0x800000U) -#define CSS_CSS_KS8_ks8_ukuok_SHIFT (23U) -/*! ks8_ukuok - Key unwrapping key - */ -#define CSS_CSS_KS8_ks8_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_ukuok_SHIFT)) & CSS_CSS_KS8_ks8_ukuok_MASK) - -#define CSS_CSS_KS8_ks8_utlspms_MASK (0x1000000U) -#define CSS_CSS_KS8_ks8_utlspms_SHIFT (24U) -/*! ks8_utlspms - TLS Pre Master Secret - */ -#define CSS_CSS_KS8_ks8_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_utlspms_SHIFT)) & CSS_CSS_KS8_ks8_utlspms_MASK) - -#define CSS_CSS_KS8_ks8_utlsms_MASK (0x2000000U) -#define CSS_CSS_KS8_ks8_utlsms_SHIFT (25U) -/*! ks8_utlsms - TLS Master Secret - */ -#define CSS_CSS_KS8_ks8_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_utlsms_SHIFT)) & CSS_CSS_KS8_ks8_utlsms_MASK) - -#define CSS_CSS_KS8_ks8_ukgsrc_MASK (0x4000000U) -#define CSS_CSS_KS8_ks8_ukgsrc_SHIFT (26U) -/*! ks8_ukgsrc - Supply KEYGEN source - */ -#define CSS_CSS_KS8_ks8_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_ukgsrc_SHIFT)) & CSS_CSS_KS8_ks8_ukgsrc_MASK) - -#define CSS_CSS_KS8_ks8_uhwo_MASK (0x8000000U) -#define CSS_CSS_KS8_ks8_uhwo_SHIFT (27U) -/*! ks8_uhwo - Hardware out key - */ -#define CSS_CSS_KS8_ks8_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uhwo_SHIFT)) & CSS_CSS_KS8_ks8_uhwo_MASK) - -#define CSS_CSS_KS8_ks8_uwrpok_MASK (0x10000000U) -#define CSS_CSS_KS8_ks8_uwrpok_SHIFT (28U) -/*! ks8_uwrpok - Ok to wrap key - */ -#define CSS_CSS_KS8_ks8_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uwrpok_SHIFT)) & CSS_CSS_KS8_ks8_uwrpok_MASK) - -#define CSS_CSS_KS8_ks8_uduk_MASK (0x20000000U) -#define CSS_CSS_KS8_ks8_uduk_SHIFT (29U) -/*! ks8_uduk - Device Unique Key - */ -#define CSS_CSS_KS8_ks8_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uduk_SHIFT)) & CSS_CSS_KS8_ks8_uduk_MASK) - -#define CSS_CSS_KS8_ks8_upprot_MASK (0xC0000000U) -#define CSS_CSS_KS8_ks8_upprot_SHIFT (30U) -/*! ks8_upprot - Priviledge level - */ -#define CSS_CSS_KS8_ks8_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_upprot_SHIFT)) & CSS_CSS_KS8_ks8_upprot_MASK) -/*! @} */ - -/*! @name CSS_KS9 - Status register */ -/*! @{ */ - -#define CSS_CSS_KS9_ks9_ksize_MASK (0x1U) -#define CSS_CSS_KS9_ks9_ksize_SHIFT (0U) -/*! ks9_ksize - Key size: 0-128, 1-256 - */ -#define CSS_CSS_KS9_ks9_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_ksize_SHIFT)) & CSS_CSS_KS9_ks9_ksize_MASK) - -#define CSS_CSS_KS9_ks9_rsvd0_MASK (0x1EU) -#define CSS_CSS_KS9_ks9_rsvd0_SHIFT (1U) -/*! ks9_rsvd0 - Reserved 0 - */ -#define CSS_CSS_KS9_ks9_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_rsvd0_SHIFT)) & CSS_CSS_KS9_ks9_rsvd0_MASK) - -#define CSS_CSS_KS9_ks9_kact_MASK (0x20U) -#define CSS_CSS_KS9_ks9_kact_SHIFT (5U) -/*! ks9_kact - Key is active - */ -#define CSS_CSS_KS9_ks9_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_kact_SHIFT)) & CSS_CSS_KS9_ks9_kact_MASK) - -#define CSS_CSS_KS9_ks9_kbase_MASK (0x40U) -#define CSS_CSS_KS9_ks9_kbase_SHIFT (6U) -/*! ks9_kbase - First slot in a multislot key - */ -#define CSS_CSS_KS9_ks9_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_kbase_SHIFT)) & CSS_CSS_KS9_ks9_kbase_MASK) - -#define CSS_CSS_KS9_ks9_fgp_MASK (0x80U) -#define CSS_CSS_KS9_ks9_fgp_SHIFT (7U) -/*! ks9_fgp - Hardware Feature General Purpose - */ -#define CSS_CSS_KS9_ks9_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_fgp_SHIFT)) & CSS_CSS_KS9_ks9_fgp_MASK) - -#define CSS_CSS_KS9_ks9_frtn_MASK (0x100U) -#define CSS_CSS_KS9_ks9_frtn_SHIFT (8U) -/*! ks9_frtn - Hardware Feature Retention - */ -#define CSS_CSS_KS9_ks9_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_frtn_SHIFT)) & CSS_CSS_KS9_ks9_frtn_MASK) - -#define CSS_CSS_KS9_ks9_fhwo_MASK (0x200U) -#define CSS_CSS_KS9_ks9_fhwo_SHIFT (9U) -/*! ks9_fhwo - Hardware Feature Output - */ -#define CSS_CSS_KS9_ks9_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_fhwo_SHIFT)) & CSS_CSS_KS9_ks9_fhwo_MASK) - -#define CSS_CSS_KS9_ks9_rsvd1_MASK (0x1C00U) -#define CSS_CSS_KS9_ks9_rsvd1_SHIFT (10U) -/*! ks9_rsvd1 - Reserved 1 - */ -#define CSS_CSS_KS9_ks9_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_rsvd1_SHIFT)) & CSS_CSS_KS9_ks9_rsvd1_MASK) - -#define CSS_CSS_KS9_ks9_ucmac_MASK (0x2000U) -#define CSS_CSS_KS9_ks9_ucmac_SHIFT (13U) -/*! ks9_ucmac - CMAC key - */ -#define CSS_CSS_KS9_ks9_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_ucmac_SHIFT)) & CSS_CSS_KS9_ks9_ucmac_MASK) - -#define CSS_CSS_KS9_ks9_uksk_MASK (0x4000U) -#define CSS_CSS_KS9_ks9_uksk_SHIFT (14U) -/*! ks9_uksk - KSK key - */ -#define CSS_CSS_KS9_ks9_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uksk_SHIFT)) & CSS_CSS_KS9_ks9_uksk_MASK) - -#define CSS_CSS_KS9_ks9_urtf_MASK (0x8000U) -#define CSS_CSS_KS9_ks9_urtf_SHIFT (15U) -/*! ks9_urtf - Real Time Fingerprint key - */ -#define CSS_CSS_KS9_ks9_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_urtf_SHIFT)) & CSS_CSS_KS9_ks9_urtf_MASK) - -#define CSS_CSS_KS9_ks9_uckdf_MASK (0x10000U) -#define CSS_CSS_KS9_ks9_uckdf_SHIFT (16U) -/*! ks9_uckdf - Derivation key for CKDF command - */ -#define CSS_CSS_KS9_ks9_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uckdf_SHIFT)) & CSS_CSS_KS9_ks9_uckdf_MASK) - -#define CSS_CSS_KS9_ks9_uhkdf_MASK (0x20000U) -#define CSS_CSS_KS9_ks9_uhkdf_SHIFT (17U) -/*! ks9_uhkdf - Derivation key for HKDF command - */ -#define CSS_CSS_KS9_ks9_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uhkdf_SHIFT)) & CSS_CSS_KS9_ks9_uhkdf_MASK) - -#define CSS_CSS_KS9_ks9_uecsg_MASK (0x40000U) -#define CSS_CSS_KS9_ks9_uecsg_SHIFT (18U) -/*! ks9_uecsg - Ecc signing key - */ -#define CSS_CSS_KS9_ks9_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uecsg_SHIFT)) & CSS_CSS_KS9_ks9_uecsg_MASK) - -#define CSS_CSS_KS9_ks9_uecdh_MASK (0x80000U) -#define CSS_CSS_KS9_ks9_uecdh_SHIFT (19U) -/*! ks9_uecdh - Ecc diffie hellman key - */ -#define CSS_CSS_KS9_ks9_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uecdh_SHIFT)) & CSS_CSS_KS9_ks9_uecdh_MASK) - -#define CSS_CSS_KS9_ks9_uaes_MASK (0x100000U) -#define CSS_CSS_KS9_ks9_uaes_SHIFT (20U) -/*! ks9_uaes - Aes key - */ -#define CSS_CSS_KS9_ks9_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uaes_SHIFT)) & CSS_CSS_KS9_ks9_uaes_MASK) - -#define CSS_CSS_KS9_ks9_uhmac_MASK (0x200000U) -#define CSS_CSS_KS9_ks9_uhmac_SHIFT (21U) -/*! ks9_uhmac - Hmac key - */ -#define CSS_CSS_KS9_ks9_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uhmac_SHIFT)) & CSS_CSS_KS9_ks9_uhmac_MASK) - -#define CSS_CSS_KS9_ks9_ukwk_MASK (0x400000U) -#define CSS_CSS_KS9_ks9_ukwk_SHIFT (22U) -/*! ks9_ukwk - Key wrapping key - */ -#define CSS_CSS_KS9_ks9_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_ukwk_SHIFT)) & CSS_CSS_KS9_ks9_ukwk_MASK) - -#define CSS_CSS_KS9_ks9_ukuok_MASK (0x800000U) -#define CSS_CSS_KS9_ks9_ukuok_SHIFT (23U) -/*! ks9_ukuok - Key unwrapping key - */ -#define CSS_CSS_KS9_ks9_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_ukuok_SHIFT)) & CSS_CSS_KS9_ks9_ukuok_MASK) - -#define CSS_CSS_KS9_ks9_utlspms_MASK (0x1000000U) -#define CSS_CSS_KS9_ks9_utlspms_SHIFT (24U) -/*! ks9_utlspms - TLS Pre Master Secret - */ -#define CSS_CSS_KS9_ks9_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_utlspms_SHIFT)) & CSS_CSS_KS9_ks9_utlspms_MASK) - -#define CSS_CSS_KS9_ks9_utlsms_MASK (0x2000000U) -#define CSS_CSS_KS9_ks9_utlsms_SHIFT (25U) -/*! ks9_utlsms - TLS Master Secret - */ -#define CSS_CSS_KS9_ks9_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_utlsms_SHIFT)) & CSS_CSS_KS9_ks9_utlsms_MASK) - -#define CSS_CSS_KS9_ks9_ukgsrc_MASK (0x4000000U) -#define CSS_CSS_KS9_ks9_ukgsrc_SHIFT (26U) -/*! ks9_ukgsrc - Supply KEYGEN source - */ -#define CSS_CSS_KS9_ks9_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_ukgsrc_SHIFT)) & CSS_CSS_KS9_ks9_ukgsrc_MASK) - -#define CSS_CSS_KS9_ks9_uhwo_MASK (0x8000000U) -#define CSS_CSS_KS9_ks9_uhwo_SHIFT (27U) -/*! ks9_uhwo - Hardware out key - */ -#define CSS_CSS_KS9_ks9_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uhwo_SHIFT)) & CSS_CSS_KS9_ks9_uhwo_MASK) - -#define CSS_CSS_KS9_ks9_uwrpok_MASK (0x10000000U) -#define CSS_CSS_KS9_ks9_uwrpok_SHIFT (28U) -/*! ks9_uwrpok - Ok to wrap key - */ -#define CSS_CSS_KS9_ks9_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uwrpok_SHIFT)) & CSS_CSS_KS9_ks9_uwrpok_MASK) - -#define CSS_CSS_KS9_ks9_uduk_MASK (0x20000000U) -#define CSS_CSS_KS9_ks9_uduk_SHIFT (29U) -/*! ks9_uduk - Device Unique Key - */ -#define CSS_CSS_KS9_ks9_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uduk_SHIFT)) & CSS_CSS_KS9_ks9_uduk_MASK) - -#define CSS_CSS_KS9_ks9_upprot_MASK (0xC0000000U) -#define CSS_CSS_KS9_ks9_upprot_SHIFT (30U) -/*! ks9_upprot - Priviledge level - */ -#define CSS_CSS_KS9_ks9_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_upprot_SHIFT)) & CSS_CSS_KS9_ks9_upprot_MASK) -/*! @} */ - -/*! @name CSS_KS10 - Status register */ -/*! @{ */ - -#define CSS_CSS_KS10_ks10_ksize_MASK (0x1U) -#define CSS_CSS_KS10_ks10_ksize_SHIFT (0U) -/*! ks10_ksize - Key size: 0-128, 1-256 - */ -#define CSS_CSS_KS10_ks10_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_ksize_SHIFT)) & CSS_CSS_KS10_ks10_ksize_MASK) - -#define CSS_CSS_KS10_ks10_rsvd0_MASK (0x1EU) -#define CSS_CSS_KS10_ks10_rsvd0_SHIFT (1U) -/*! ks10_rsvd0 - Reserved 0 - */ -#define CSS_CSS_KS10_ks10_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_rsvd0_SHIFT)) & CSS_CSS_KS10_ks10_rsvd0_MASK) - -#define CSS_CSS_KS10_ks10_kact_MASK (0x20U) -#define CSS_CSS_KS10_ks10_kact_SHIFT (5U) -/*! ks10_kact - Key is active - */ -#define CSS_CSS_KS10_ks10_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_kact_SHIFT)) & CSS_CSS_KS10_ks10_kact_MASK) - -#define CSS_CSS_KS10_ks10_kbase_MASK (0x40U) -#define CSS_CSS_KS10_ks10_kbase_SHIFT (6U) -/*! ks10_kbase - First slot in a multislot key - */ -#define CSS_CSS_KS10_ks10_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_kbase_SHIFT)) & CSS_CSS_KS10_ks10_kbase_MASK) - -#define CSS_CSS_KS10_ks10_fgp_MASK (0x80U) -#define CSS_CSS_KS10_ks10_fgp_SHIFT (7U) -/*! ks10_fgp - Hardware Feature General Purpose - */ -#define CSS_CSS_KS10_ks10_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_fgp_SHIFT)) & CSS_CSS_KS10_ks10_fgp_MASK) - -#define CSS_CSS_KS10_ks10_frtn_MASK (0x100U) -#define CSS_CSS_KS10_ks10_frtn_SHIFT (8U) -/*! ks10_frtn - Hardware Feature Retention - */ -#define CSS_CSS_KS10_ks10_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_frtn_SHIFT)) & CSS_CSS_KS10_ks10_frtn_MASK) - -#define CSS_CSS_KS10_ks10_fhwo_MASK (0x200U) -#define CSS_CSS_KS10_ks10_fhwo_SHIFT (9U) -/*! ks10_fhwo - Hardware Feature Output - */ -#define CSS_CSS_KS10_ks10_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_fhwo_SHIFT)) & CSS_CSS_KS10_ks10_fhwo_MASK) - -#define CSS_CSS_KS10_ks10_rsvd1_MASK (0x1C00U) -#define CSS_CSS_KS10_ks10_rsvd1_SHIFT (10U) -/*! ks10_rsvd1 - Reserved 1 - */ -#define CSS_CSS_KS10_ks10_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_rsvd1_SHIFT)) & CSS_CSS_KS10_ks10_rsvd1_MASK) - -#define CSS_CSS_KS10_ks10_ucmac_MASK (0x2000U) -#define CSS_CSS_KS10_ks10_ucmac_SHIFT (13U) -/*! ks10_ucmac - CMAC key - */ -#define CSS_CSS_KS10_ks10_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_ucmac_SHIFT)) & CSS_CSS_KS10_ks10_ucmac_MASK) - -#define CSS_CSS_KS10_ks10_uksk_MASK (0x4000U) -#define CSS_CSS_KS10_ks10_uksk_SHIFT (14U) -/*! ks10_uksk - KSK key - */ -#define CSS_CSS_KS10_ks10_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uksk_SHIFT)) & CSS_CSS_KS10_ks10_uksk_MASK) - -#define CSS_CSS_KS10_ks10_urtf_MASK (0x8000U) -#define CSS_CSS_KS10_ks10_urtf_SHIFT (15U) -/*! ks10_urtf - Real Time Fingerprint key - */ -#define CSS_CSS_KS10_ks10_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_urtf_SHIFT)) & CSS_CSS_KS10_ks10_urtf_MASK) - -#define CSS_CSS_KS10_ks10_uckdf_MASK (0x10000U) -#define CSS_CSS_KS10_ks10_uckdf_SHIFT (16U) -/*! ks10_uckdf - Derivation key for CKDF command - */ -#define CSS_CSS_KS10_ks10_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uckdf_SHIFT)) & CSS_CSS_KS10_ks10_uckdf_MASK) - -#define CSS_CSS_KS10_ks10_uhkdf_MASK (0x20000U) -#define CSS_CSS_KS10_ks10_uhkdf_SHIFT (17U) -/*! ks10_uhkdf - Derivation key for HKDF command - */ -#define CSS_CSS_KS10_ks10_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uhkdf_SHIFT)) & CSS_CSS_KS10_ks10_uhkdf_MASK) - -#define CSS_CSS_KS10_ks10_uecsg_MASK (0x40000U) -#define CSS_CSS_KS10_ks10_uecsg_SHIFT (18U) -/*! ks10_uecsg - Ecc signing key - */ -#define CSS_CSS_KS10_ks10_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uecsg_SHIFT)) & CSS_CSS_KS10_ks10_uecsg_MASK) - -#define CSS_CSS_KS10_ks10_uecdh_MASK (0x80000U) -#define CSS_CSS_KS10_ks10_uecdh_SHIFT (19U) -/*! ks10_uecdh - Ecc diffie hellman key - */ -#define CSS_CSS_KS10_ks10_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uecdh_SHIFT)) & CSS_CSS_KS10_ks10_uecdh_MASK) - -#define CSS_CSS_KS10_ks10_uaes_MASK (0x100000U) -#define CSS_CSS_KS10_ks10_uaes_SHIFT (20U) -/*! ks10_uaes - Aes key - */ -#define CSS_CSS_KS10_ks10_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uaes_SHIFT)) & CSS_CSS_KS10_ks10_uaes_MASK) - -#define CSS_CSS_KS10_ks10_uhmac_MASK (0x200000U) -#define CSS_CSS_KS10_ks10_uhmac_SHIFT (21U) -/*! ks10_uhmac - Hmac key - */ -#define CSS_CSS_KS10_ks10_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uhmac_SHIFT)) & CSS_CSS_KS10_ks10_uhmac_MASK) - -#define CSS_CSS_KS10_ks10_ukwk_MASK (0x400000U) -#define CSS_CSS_KS10_ks10_ukwk_SHIFT (22U) -/*! ks10_ukwk - Key wrapping key - */ -#define CSS_CSS_KS10_ks10_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_ukwk_SHIFT)) & CSS_CSS_KS10_ks10_ukwk_MASK) - -#define CSS_CSS_KS10_ks10_ukuok_MASK (0x800000U) -#define CSS_CSS_KS10_ks10_ukuok_SHIFT (23U) -/*! ks10_ukuok - Key unwrapping key - */ -#define CSS_CSS_KS10_ks10_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_ukuok_SHIFT)) & CSS_CSS_KS10_ks10_ukuok_MASK) - -#define CSS_CSS_KS10_ks10_utlspms_MASK (0x1000000U) -#define CSS_CSS_KS10_ks10_utlspms_SHIFT (24U) -/*! ks10_utlspms - TLS Pre Master Secret - */ -#define CSS_CSS_KS10_ks10_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_utlspms_SHIFT)) & CSS_CSS_KS10_ks10_utlspms_MASK) - -#define CSS_CSS_KS10_ks10_utlsms_MASK (0x2000000U) -#define CSS_CSS_KS10_ks10_utlsms_SHIFT (25U) -/*! ks10_utlsms - TLS Master Secret - */ -#define CSS_CSS_KS10_ks10_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_utlsms_SHIFT)) & CSS_CSS_KS10_ks10_utlsms_MASK) - -#define CSS_CSS_KS10_ks10_ukgsrc_MASK (0x4000000U) -#define CSS_CSS_KS10_ks10_ukgsrc_SHIFT (26U) -/*! ks10_ukgsrc - Supply KEYGEN source - */ -#define CSS_CSS_KS10_ks10_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_ukgsrc_SHIFT)) & CSS_CSS_KS10_ks10_ukgsrc_MASK) - -#define CSS_CSS_KS10_ks10_uhwo_MASK (0x8000000U) -#define CSS_CSS_KS10_ks10_uhwo_SHIFT (27U) -/*! ks10_uhwo - Hardware out key - */ -#define CSS_CSS_KS10_ks10_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uhwo_SHIFT)) & CSS_CSS_KS10_ks10_uhwo_MASK) - -#define CSS_CSS_KS10_ks10_uwrpok_MASK (0x10000000U) -#define CSS_CSS_KS10_ks10_uwrpok_SHIFT (28U) -/*! ks10_uwrpok - Ok to wrap key - */ -#define CSS_CSS_KS10_ks10_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uwrpok_SHIFT)) & CSS_CSS_KS10_ks10_uwrpok_MASK) - -#define CSS_CSS_KS10_ks10_uduk_MASK (0x20000000U) -#define CSS_CSS_KS10_ks10_uduk_SHIFT (29U) -/*! ks10_uduk - Device Unique Key - */ -#define CSS_CSS_KS10_ks10_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uduk_SHIFT)) & CSS_CSS_KS10_ks10_uduk_MASK) - -#define CSS_CSS_KS10_ks10_upprot_MASK (0xC0000000U) -#define CSS_CSS_KS10_ks10_upprot_SHIFT (30U) -/*! ks10_upprot - Priviledge level - */ -#define CSS_CSS_KS10_ks10_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_upprot_SHIFT)) & CSS_CSS_KS10_ks10_upprot_MASK) -/*! @} */ - -/*! @name CSS_KS11 - Status register */ -/*! @{ */ - -#define CSS_CSS_KS11_ks11_ksize_MASK (0x1U) -#define CSS_CSS_KS11_ks11_ksize_SHIFT (0U) -/*! ks11_ksize - Key size: 0-128, 1-256 - */ -#define CSS_CSS_KS11_ks11_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_ksize_SHIFT)) & CSS_CSS_KS11_ks11_ksize_MASK) - -#define CSS_CSS_KS11_ks11_rsvd0_MASK (0x1EU) -#define CSS_CSS_KS11_ks11_rsvd0_SHIFT (1U) -/*! ks11_rsvd0 - Reserved 0 - */ -#define CSS_CSS_KS11_ks11_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_rsvd0_SHIFT)) & CSS_CSS_KS11_ks11_rsvd0_MASK) - -#define CSS_CSS_KS11_ks11_kact_MASK (0x20U) -#define CSS_CSS_KS11_ks11_kact_SHIFT (5U) -/*! ks11_kact - Key is active - */ -#define CSS_CSS_KS11_ks11_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_kact_SHIFT)) & CSS_CSS_KS11_ks11_kact_MASK) - -#define CSS_CSS_KS11_ks11_kbase_MASK (0x40U) -#define CSS_CSS_KS11_ks11_kbase_SHIFT (6U) -/*! ks11_kbase - First slot in a multislot key - */ -#define CSS_CSS_KS11_ks11_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_kbase_SHIFT)) & CSS_CSS_KS11_ks11_kbase_MASK) - -#define CSS_CSS_KS11_ks11_fgp_MASK (0x80U) -#define CSS_CSS_KS11_ks11_fgp_SHIFT (7U) -/*! ks11_fgp - Hardware Feature General Purpose - */ -#define CSS_CSS_KS11_ks11_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_fgp_SHIFT)) & CSS_CSS_KS11_ks11_fgp_MASK) - -#define CSS_CSS_KS11_ks11_frtn_MASK (0x100U) -#define CSS_CSS_KS11_ks11_frtn_SHIFT (8U) -/*! ks11_frtn - Hardware Feature Retention - */ -#define CSS_CSS_KS11_ks11_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_frtn_SHIFT)) & CSS_CSS_KS11_ks11_frtn_MASK) - -#define CSS_CSS_KS11_ks11_fhwo_MASK (0x200U) -#define CSS_CSS_KS11_ks11_fhwo_SHIFT (9U) -/*! ks11_fhwo - Hardware Feature Output - */ -#define CSS_CSS_KS11_ks11_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_fhwo_SHIFT)) & CSS_CSS_KS11_ks11_fhwo_MASK) - -#define CSS_CSS_KS11_ks11_rsvd1_MASK (0x1C00U) -#define CSS_CSS_KS11_ks11_rsvd1_SHIFT (10U) -/*! ks11_rsvd1 - Reserved 1 - */ -#define CSS_CSS_KS11_ks11_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_rsvd1_SHIFT)) & CSS_CSS_KS11_ks11_rsvd1_MASK) - -#define CSS_CSS_KS11_ks11_ucmac_MASK (0x2000U) -#define CSS_CSS_KS11_ks11_ucmac_SHIFT (13U) -/*! ks11_ucmac - CMAC key - */ -#define CSS_CSS_KS11_ks11_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_ucmac_SHIFT)) & CSS_CSS_KS11_ks11_ucmac_MASK) - -#define CSS_CSS_KS11_ks11_uksk_MASK (0x4000U) -#define CSS_CSS_KS11_ks11_uksk_SHIFT (14U) -/*! ks11_uksk - KSK key - */ -#define CSS_CSS_KS11_ks11_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uksk_SHIFT)) & CSS_CSS_KS11_ks11_uksk_MASK) - -#define CSS_CSS_KS11_ks11_urtf_MASK (0x8000U) -#define CSS_CSS_KS11_ks11_urtf_SHIFT (15U) -/*! ks11_urtf - Real Time Fingerprint key - */ -#define CSS_CSS_KS11_ks11_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_urtf_SHIFT)) & CSS_CSS_KS11_ks11_urtf_MASK) - -#define CSS_CSS_KS11_ks11_uckdf_MASK (0x10000U) -#define CSS_CSS_KS11_ks11_uckdf_SHIFT (16U) -/*! ks11_uckdf - Derivation key for CKDF command - */ -#define CSS_CSS_KS11_ks11_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uckdf_SHIFT)) & CSS_CSS_KS11_ks11_uckdf_MASK) - -#define CSS_CSS_KS11_ks11_uhkdf_MASK (0x20000U) -#define CSS_CSS_KS11_ks11_uhkdf_SHIFT (17U) -/*! ks11_uhkdf - Derivation key for HKDF command - */ -#define CSS_CSS_KS11_ks11_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uhkdf_SHIFT)) & CSS_CSS_KS11_ks11_uhkdf_MASK) - -#define CSS_CSS_KS11_ks11_uecsg_MASK (0x40000U) -#define CSS_CSS_KS11_ks11_uecsg_SHIFT (18U) -/*! ks11_uecsg - Ecc signing key - */ -#define CSS_CSS_KS11_ks11_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uecsg_SHIFT)) & CSS_CSS_KS11_ks11_uecsg_MASK) - -#define CSS_CSS_KS11_ks11_uecdh_MASK (0x80000U) -#define CSS_CSS_KS11_ks11_uecdh_SHIFT (19U) -/*! ks11_uecdh - Ecc diffie hellman key - */ -#define CSS_CSS_KS11_ks11_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uecdh_SHIFT)) & CSS_CSS_KS11_ks11_uecdh_MASK) - -#define CSS_CSS_KS11_ks11_uaes_MASK (0x100000U) -#define CSS_CSS_KS11_ks11_uaes_SHIFT (20U) -/*! ks11_uaes - Aes key - */ -#define CSS_CSS_KS11_ks11_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uaes_SHIFT)) & CSS_CSS_KS11_ks11_uaes_MASK) - -#define CSS_CSS_KS11_ks11_uhmac_MASK (0x200000U) -#define CSS_CSS_KS11_ks11_uhmac_SHIFT (21U) -/*! ks11_uhmac - Hmac key - */ -#define CSS_CSS_KS11_ks11_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uhmac_SHIFT)) & CSS_CSS_KS11_ks11_uhmac_MASK) - -#define CSS_CSS_KS11_ks11_ukwk_MASK (0x400000U) -#define CSS_CSS_KS11_ks11_ukwk_SHIFT (22U) -/*! ks11_ukwk - Key wrapping key - */ -#define CSS_CSS_KS11_ks11_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_ukwk_SHIFT)) & CSS_CSS_KS11_ks11_ukwk_MASK) - -#define CSS_CSS_KS11_ks11_ukuok_MASK (0x800000U) -#define CSS_CSS_KS11_ks11_ukuok_SHIFT (23U) -/*! ks11_ukuok - Key unwrapping key - */ -#define CSS_CSS_KS11_ks11_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_ukuok_SHIFT)) & CSS_CSS_KS11_ks11_ukuok_MASK) - -#define CSS_CSS_KS11_ks11_utlspms_MASK (0x1000000U) -#define CSS_CSS_KS11_ks11_utlspms_SHIFT (24U) -/*! ks11_utlspms - TLS Pre Master Secret - */ -#define CSS_CSS_KS11_ks11_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_utlspms_SHIFT)) & CSS_CSS_KS11_ks11_utlspms_MASK) - -#define CSS_CSS_KS11_ks11_utlsms_MASK (0x2000000U) -#define CSS_CSS_KS11_ks11_utlsms_SHIFT (25U) -/*! ks11_utlsms - TLS Master Secret - */ -#define CSS_CSS_KS11_ks11_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_utlsms_SHIFT)) & CSS_CSS_KS11_ks11_utlsms_MASK) - -#define CSS_CSS_KS11_ks11_ukgsrc_MASK (0x4000000U) -#define CSS_CSS_KS11_ks11_ukgsrc_SHIFT (26U) -/*! ks11_ukgsrc - Supply KEYGEN source - */ -#define CSS_CSS_KS11_ks11_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_ukgsrc_SHIFT)) & CSS_CSS_KS11_ks11_ukgsrc_MASK) - -#define CSS_CSS_KS11_ks11_uhwo_MASK (0x8000000U) -#define CSS_CSS_KS11_ks11_uhwo_SHIFT (27U) -/*! ks11_uhwo - Hardware out key - */ -#define CSS_CSS_KS11_ks11_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uhwo_SHIFT)) & CSS_CSS_KS11_ks11_uhwo_MASK) - -#define CSS_CSS_KS11_ks11_uwrpok_MASK (0x10000000U) -#define CSS_CSS_KS11_ks11_uwrpok_SHIFT (28U) -/*! ks11_uwrpok - Ok to wrap key - */ -#define CSS_CSS_KS11_ks11_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uwrpok_SHIFT)) & CSS_CSS_KS11_ks11_uwrpok_MASK) - -#define CSS_CSS_KS11_ks11_uduk_MASK (0x20000000U) -#define CSS_CSS_KS11_ks11_uduk_SHIFT (29U) -/*! ks11_uduk - Device Unique Key - */ -#define CSS_CSS_KS11_ks11_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uduk_SHIFT)) & CSS_CSS_KS11_ks11_uduk_MASK) - -#define CSS_CSS_KS11_ks11_upprot_MASK (0xC0000000U) -#define CSS_CSS_KS11_ks11_upprot_SHIFT (30U) -/*! ks11_upprot - Priviledge level - */ -#define CSS_CSS_KS11_ks11_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_upprot_SHIFT)) & CSS_CSS_KS11_ks11_upprot_MASK) -/*! @} */ - -/*! @name CSS_KS12 - Status register */ -/*! @{ */ - -#define CSS_CSS_KS12_ks12_ksize_MASK (0x1U) -#define CSS_CSS_KS12_ks12_ksize_SHIFT (0U) -/*! ks12_ksize - Key size: 0-128, 1-256 - */ -#define CSS_CSS_KS12_ks12_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_ksize_SHIFT)) & CSS_CSS_KS12_ks12_ksize_MASK) - -#define CSS_CSS_KS12_ks12_rsvd0_MASK (0x1EU) -#define CSS_CSS_KS12_ks12_rsvd0_SHIFT (1U) -/*! ks12_rsvd0 - Reserved 0 - */ -#define CSS_CSS_KS12_ks12_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_rsvd0_SHIFT)) & CSS_CSS_KS12_ks12_rsvd0_MASK) - -#define CSS_CSS_KS12_ks12_kact_MASK (0x20U) -#define CSS_CSS_KS12_ks12_kact_SHIFT (5U) -/*! ks12_kact - Key is active - */ -#define CSS_CSS_KS12_ks12_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_kact_SHIFT)) & CSS_CSS_KS12_ks12_kact_MASK) - -#define CSS_CSS_KS12_ks12_kbase_MASK (0x40U) -#define CSS_CSS_KS12_ks12_kbase_SHIFT (6U) -/*! ks12_kbase - First slot in a multislot key - */ -#define CSS_CSS_KS12_ks12_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_kbase_SHIFT)) & CSS_CSS_KS12_ks12_kbase_MASK) - -#define CSS_CSS_KS12_ks12_fgp_MASK (0x80U) -#define CSS_CSS_KS12_ks12_fgp_SHIFT (7U) -/*! ks12_fgp - Hardware Feature General Purpose - */ -#define CSS_CSS_KS12_ks12_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_fgp_SHIFT)) & CSS_CSS_KS12_ks12_fgp_MASK) - -#define CSS_CSS_KS12_ks12_frtn_MASK (0x100U) -#define CSS_CSS_KS12_ks12_frtn_SHIFT (8U) -/*! ks12_frtn - Hardware Feature Retention - */ -#define CSS_CSS_KS12_ks12_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_frtn_SHIFT)) & CSS_CSS_KS12_ks12_frtn_MASK) - -#define CSS_CSS_KS12_ks12_fhwo_MASK (0x200U) -#define CSS_CSS_KS12_ks12_fhwo_SHIFT (9U) -/*! ks12_fhwo - Hardware Feature Output - */ -#define CSS_CSS_KS12_ks12_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_fhwo_SHIFT)) & CSS_CSS_KS12_ks12_fhwo_MASK) - -#define CSS_CSS_KS12_ks12_rsvd1_MASK (0x1C00U) -#define CSS_CSS_KS12_ks12_rsvd1_SHIFT (10U) -/*! ks12_rsvd1 - Reserved 1 - */ -#define CSS_CSS_KS12_ks12_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_rsvd1_SHIFT)) & CSS_CSS_KS12_ks12_rsvd1_MASK) - -#define CSS_CSS_KS12_ks12_ucmac_MASK (0x2000U) -#define CSS_CSS_KS12_ks12_ucmac_SHIFT (13U) -/*! ks12_ucmac - CMAC key - */ -#define CSS_CSS_KS12_ks12_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_ucmac_SHIFT)) & CSS_CSS_KS12_ks12_ucmac_MASK) - -#define CSS_CSS_KS12_ks12_uksk_MASK (0x4000U) -#define CSS_CSS_KS12_ks12_uksk_SHIFT (14U) -/*! ks12_uksk - KSK key - */ -#define CSS_CSS_KS12_ks12_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uksk_SHIFT)) & CSS_CSS_KS12_ks12_uksk_MASK) - -#define CSS_CSS_KS12_ks12_urtf_MASK (0x8000U) -#define CSS_CSS_KS12_ks12_urtf_SHIFT (15U) -/*! ks12_urtf - Real Time Fingerprint key - */ -#define CSS_CSS_KS12_ks12_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_urtf_SHIFT)) & CSS_CSS_KS12_ks12_urtf_MASK) - -#define CSS_CSS_KS12_ks12_uckdf_MASK (0x10000U) -#define CSS_CSS_KS12_ks12_uckdf_SHIFT (16U) -/*! ks12_uckdf - Derivation key for CKDF command - */ -#define CSS_CSS_KS12_ks12_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uckdf_SHIFT)) & CSS_CSS_KS12_ks12_uckdf_MASK) - -#define CSS_CSS_KS12_ks12_uhkdf_MASK (0x20000U) -#define CSS_CSS_KS12_ks12_uhkdf_SHIFT (17U) -/*! ks12_uhkdf - Derivation key for HKDF command - */ -#define CSS_CSS_KS12_ks12_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uhkdf_SHIFT)) & CSS_CSS_KS12_ks12_uhkdf_MASK) - -#define CSS_CSS_KS12_ks12_uecsg_MASK (0x40000U) -#define CSS_CSS_KS12_ks12_uecsg_SHIFT (18U) -/*! ks12_uecsg - Ecc signing key - */ -#define CSS_CSS_KS12_ks12_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uecsg_SHIFT)) & CSS_CSS_KS12_ks12_uecsg_MASK) - -#define CSS_CSS_KS12_ks12_uecdh_MASK (0x80000U) -#define CSS_CSS_KS12_ks12_uecdh_SHIFT (19U) -/*! ks12_uecdh - Ecc diffie hellman key - */ -#define CSS_CSS_KS12_ks12_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uecdh_SHIFT)) & CSS_CSS_KS12_ks12_uecdh_MASK) - -#define CSS_CSS_KS12_ks12_uaes_MASK (0x100000U) -#define CSS_CSS_KS12_ks12_uaes_SHIFT (20U) -/*! ks12_uaes - Aes key - */ -#define CSS_CSS_KS12_ks12_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uaes_SHIFT)) & CSS_CSS_KS12_ks12_uaes_MASK) - -#define CSS_CSS_KS12_ks12_uhmac_MASK (0x200000U) -#define CSS_CSS_KS12_ks12_uhmac_SHIFT (21U) -/*! ks12_uhmac - Hmac key - */ -#define CSS_CSS_KS12_ks12_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uhmac_SHIFT)) & CSS_CSS_KS12_ks12_uhmac_MASK) - -#define CSS_CSS_KS12_ks12_ukwk_MASK (0x400000U) -#define CSS_CSS_KS12_ks12_ukwk_SHIFT (22U) -/*! ks12_ukwk - Key wrapping key - */ -#define CSS_CSS_KS12_ks12_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_ukwk_SHIFT)) & CSS_CSS_KS12_ks12_ukwk_MASK) - -#define CSS_CSS_KS12_ks12_ukuok_MASK (0x800000U) -#define CSS_CSS_KS12_ks12_ukuok_SHIFT (23U) -/*! ks12_ukuok - Key unwrapping key - */ -#define CSS_CSS_KS12_ks12_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_ukuok_SHIFT)) & CSS_CSS_KS12_ks12_ukuok_MASK) - -#define CSS_CSS_KS12_ks12_utlspms_MASK (0x1000000U) -#define CSS_CSS_KS12_ks12_utlspms_SHIFT (24U) -/*! ks12_utlspms - TLS Pre Master Secret - */ -#define CSS_CSS_KS12_ks12_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_utlspms_SHIFT)) & CSS_CSS_KS12_ks12_utlspms_MASK) - -#define CSS_CSS_KS12_ks12_utlsms_MASK (0x2000000U) -#define CSS_CSS_KS12_ks12_utlsms_SHIFT (25U) -/*! ks12_utlsms - TLS Master Secret - */ -#define CSS_CSS_KS12_ks12_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_utlsms_SHIFT)) & CSS_CSS_KS12_ks12_utlsms_MASK) - -#define CSS_CSS_KS12_ks12_ukgsrc_MASK (0x4000000U) -#define CSS_CSS_KS12_ks12_ukgsrc_SHIFT (26U) -/*! ks12_ukgsrc - Supply KEYGEN source - */ -#define CSS_CSS_KS12_ks12_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_ukgsrc_SHIFT)) & CSS_CSS_KS12_ks12_ukgsrc_MASK) - -#define CSS_CSS_KS12_ks12_uhwo_MASK (0x8000000U) -#define CSS_CSS_KS12_ks12_uhwo_SHIFT (27U) -/*! ks12_uhwo - Hardware out key - */ -#define CSS_CSS_KS12_ks12_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uhwo_SHIFT)) & CSS_CSS_KS12_ks12_uhwo_MASK) - -#define CSS_CSS_KS12_ks12_uwrpok_MASK (0x10000000U) -#define CSS_CSS_KS12_ks12_uwrpok_SHIFT (28U) -/*! ks12_uwrpok - Ok to wrap key - */ -#define CSS_CSS_KS12_ks12_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uwrpok_SHIFT)) & CSS_CSS_KS12_ks12_uwrpok_MASK) - -#define CSS_CSS_KS12_ks12_uduk_MASK (0x20000000U) -#define CSS_CSS_KS12_ks12_uduk_SHIFT (29U) -/*! ks12_uduk - Device Unique Key - */ -#define CSS_CSS_KS12_ks12_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uduk_SHIFT)) & CSS_CSS_KS12_ks12_uduk_MASK) - -#define CSS_CSS_KS12_ks12_upprot_MASK (0xC0000000U) -#define CSS_CSS_KS12_ks12_upprot_SHIFT (30U) -/*! ks12_upprot - Priviledge level - */ -#define CSS_CSS_KS12_ks12_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_upprot_SHIFT)) & CSS_CSS_KS12_ks12_upprot_MASK) -/*! @} */ - -/*! @name CSS_KS13 - Status register */ -/*! @{ */ - -#define CSS_CSS_KS13_ks13_ksize_MASK (0x1U) -#define CSS_CSS_KS13_ks13_ksize_SHIFT (0U) -/*! ks13_ksize - Key size: 0-128, 1-256 - */ -#define CSS_CSS_KS13_ks13_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_ksize_SHIFT)) & CSS_CSS_KS13_ks13_ksize_MASK) - -#define CSS_CSS_KS13_ks13_rsvd0_MASK (0x1EU) -#define CSS_CSS_KS13_ks13_rsvd0_SHIFT (1U) -/*! ks13_rsvd0 - Reserved 0 - */ -#define CSS_CSS_KS13_ks13_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_rsvd0_SHIFT)) & CSS_CSS_KS13_ks13_rsvd0_MASK) - -#define CSS_CSS_KS13_ks13_kact_MASK (0x20U) -#define CSS_CSS_KS13_ks13_kact_SHIFT (5U) -/*! ks13_kact - Key is active - */ -#define CSS_CSS_KS13_ks13_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_kact_SHIFT)) & CSS_CSS_KS13_ks13_kact_MASK) - -#define CSS_CSS_KS13_ks13_kbase_MASK (0x40U) -#define CSS_CSS_KS13_ks13_kbase_SHIFT (6U) -/*! ks13_kbase - First slot in a multislot key - */ -#define CSS_CSS_KS13_ks13_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_kbase_SHIFT)) & CSS_CSS_KS13_ks13_kbase_MASK) - -#define CSS_CSS_KS13_ks13_fgp_MASK (0x80U) -#define CSS_CSS_KS13_ks13_fgp_SHIFT (7U) -/*! ks13_fgp - Hardware Feature General Purpose - */ -#define CSS_CSS_KS13_ks13_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_fgp_SHIFT)) & CSS_CSS_KS13_ks13_fgp_MASK) - -#define CSS_CSS_KS13_ks13_frtn_MASK (0x100U) -#define CSS_CSS_KS13_ks13_frtn_SHIFT (8U) -/*! ks13_frtn - Hardware Feature Retention - */ -#define CSS_CSS_KS13_ks13_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_frtn_SHIFT)) & CSS_CSS_KS13_ks13_frtn_MASK) - -#define CSS_CSS_KS13_ks13_fhwo_MASK (0x200U) -#define CSS_CSS_KS13_ks13_fhwo_SHIFT (9U) -/*! ks13_fhwo - Hardware Feature Output - */ -#define CSS_CSS_KS13_ks13_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_fhwo_SHIFT)) & CSS_CSS_KS13_ks13_fhwo_MASK) - -#define CSS_CSS_KS13_ks13_rsvd1_MASK (0x1C00U) -#define CSS_CSS_KS13_ks13_rsvd1_SHIFT (10U) -/*! ks13_rsvd1 - Reserved 1 - */ -#define CSS_CSS_KS13_ks13_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_rsvd1_SHIFT)) & CSS_CSS_KS13_ks13_rsvd1_MASK) - -#define CSS_CSS_KS13_ks13_ucmac_MASK (0x2000U) -#define CSS_CSS_KS13_ks13_ucmac_SHIFT (13U) -/*! ks13_ucmac - CMAC key - */ -#define CSS_CSS_KS13_ks13_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_ucmac_SHIFT)) & CSS_CSS_KS13_ks13_ucmac_MASK) - -#define CSS_CSS_KS13_ks13_uksk_MASK (0x4000U) -#define CSS_CSS_KS13_ks13_uksk_SHIFT (14U) -/*! ks13_uksk - KSK key - */ -#define CSS_CSS_KS13_ks13_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uksk_SHIFT)) & CSS_CSS_KS13_ks13_uksk_MASK) - -#define CSS_CSS_KS13_ks13_urtf_MASK (0x8000U) -#define CSS_CSS_KS13_ks13_urtf_SHIFT (15U) -/*! ks13_urtf - Real Time Fingerprint key - */ -#define CSS_CSS_KS13_ks13_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_urtf_SHIFT)) & CSS_CSS_KS13_ks13_urtf_MASK) - -#define CSS_CSS_KS13_ks13_uckdf_MASK (0x10000U) -#define CSS_CSS_KS13_ks13_uckdf_SHIFT (16U) -/*! ks13_uckdf - Derivation key for CKDF command - */ -#define CSS_CSS_KS13_ks13_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uckdf_SHIFT)) & CSS_CSS_KS13_ks13_uckdf_MASK) - -#define CSS_CSS_KS13_ks13_uhkdf_MASK (0x20000U) -#define CSS_CSS_KS13_ks13_uhkdf_SHIFT (17U) -/*! ks13_uhkdf - Derivation key for HKDF command - */ -#define CSS_CSS_KS13_ks13_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uhkdf_SHIFT)) & CSS_CSS_KS13_ks13_uhkdf_MASK) - -#define CSS_CSS_KS13_ks13_uecsg_MASK (0x40000U) -#define CSS_CSS_KS13_ks13_uecsg_SHIFT (18U) -/*! ks13_uecsg - Ecc signing key - */ -#define CSS_CSS_KS13_ks13_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uecsg_SHIFT)) & CSS_CSS_KS13_ks13_uecsg_MASK) - -#define CSS_CSS_KS13_ks13_uecdh_MASK (0x80000U) -#define CSS_CSS_KS13_ks13_uecdh_SHIFT (19U) -/*! ks13_uecdh - Ecc diffie hellman key - */ -#define CSS_CSS_KS13_ks13_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uecdh_SHIFT)) & CSS_CSS_KS13_ks13_uecdh_MASK) - -#define CSS_CSS_KS13_ks13_uaes_MASK (0x100000U) -#define CSS_CSS_KS13_ks13_uaes_SHIFT (20U) -/*! ks13_uaes - Aes key - */ -#define CSS_CSS_KS13_ks13_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uaes_SHIFT)) & CSS_CSS_KS13_ks13_uaes_MASK) - -#define CSS_CSS_KS13_ks13_uhmac_MASK (0x200000U) -#define CSS_CSS_KS13_ks13_uhmac_SHIFT (21U) -/*! ks13_uhmac - Hmac key - */ -#define CSS_CSS_KS13_ks13_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uhmac_SHIFT)) & CSS_CSS_KS13_ks13_uhmac_MASK) - -#define CSS_CSS_KS13_ks13_ukwk_MASK (0x400000U) -#define CSS_CSS_KS13_ks13_ukwk_SHIFT (22U) -/*! ks13_ukwk - Key wrapping key - */ -#define CSS_CSS_KS13_ks13_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_ukwk_SHIFT)) & CSS_CSS_KS13_ks13_ukwk_MASK) - -#define CSS_CSS_KS13_ks13_ukuok_MASK (0x800000U) -#define CSS_CSS_KS13_ks13_ukuok_SHIFT (23U) -/*! ks13_ukuok - Key unwrapping key - */ -#define CSS_CSS_KS13_ks13_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_ukuok_SHIFT)) & CSS_CSS_KS13_ks13_ukuok_MASK) - -#define CSS_CSS_KS13_ks13_utlspms_MASK (0x1000000U) -#define CSS_CSS_KS13_ks13_utlspms_SHIFT (24U) -/*! ks13_utlspms - TLS Pre Master Secret - */ -#define CSS_CSS_KS13_ks13_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_utlspms_SHIFT)) & CSS_CSS_KS13_ks13_utlspms_MASK) - -#define CSS_CSS_KS13_ks13_utlsms_MASK (0x2000000U) -#define CSS_CSS_KS13_ks13_utlsms_SHIFT (25U) -/*! ks13_utlsms - TLS Master Secret - */ -#define CSS_CSS_KS13_ks13_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_utlsms_SHIFT)) & CSS_CSS_KS13_ks13_utlsms_MASK) - -#define CSS_CSS_KS13_ks13_ukgsrc_MASK (0x4000000U) -#define CSS_CSS_KS13_ks13_ukgsrc_SHIFT (26U) -/*! ks13_ukgsrc - Supply KEYGEN source - */ -#define CSS_CSS_KS13_ks13_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_ukgsrc_SHIFT)) & CSS_CSS_KS13_ks13_ukgsrc_MASK) - -#define CSS_CSS_KS13_ks13_uhwo_MASK (0x8000000U) -#define CSS_CSS_KS13_ks13_uhwo_SHIFT (27U) -/*! ks13_uhwo - Hardware out key - */ -#define CSS_CSS_KS13_ks13_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uhwo_SHIFT)) & CSS_CSS_KS13_ks13_uhwo_MASK) - -#define CSS_CSS_KS13_ks13_uwrpok_MASK (0x10000000U) -#define CSS_CSS_KS13_ks13_uwrpok_SHIFT (28U) -/*! ks13_uwrpok - Ok to wrap key - */ -#define CSS_CSS_KS13_ks13_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uwrpok_SHIFT)) & CSS_CSS_KS13_ks13_uwrpok_MASK) - -#define CSS_CSS_KS13_ks13_uduk_MASK (0x20000000U) -#define CSS_CSS_KS13_ks13_uduk_SHIFT (29U) -/*! ks13_uduk - Device Unique Key - */ -#define CSS_CSS_KS13_ks13_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uduk_SHIFT)) & CSS_CSS_KS13_ks13_uduk_MASK) - -#define CSS_CSS_KS13_ks13_upprot_MASK (0xC0000000U) -#define CSS_CSS_KS13_ks13_upprot_SHIFT (30U) -/*! ks13_upprot - Priviledge level - */ -#define CSS_CSS_KS13_ks13_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_upprot_SHIFT)) & CSS_CSS_KS13_ks13_upprot_MASK) -/*! @} */ - -/*! @name CSS_KS14 - Status register */ -/*! @{ */ - -#define CSS_CSS_KS14_ks14_ksize_MASK (0x1U) -#define CSS_CSS_KS14_ks14_ksize_SHIFT (0U) -/*! ks14_ksize - Key size: 0-128, 1-256 - */ -#define CSS_CSS_KS14_ks14_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_ksize_SHIFT)) & CSS_CSS_KS14_ks14_ksize_MASK) - -#define CSS_CSS_KS14_ks14_rsvd0_MASK (0x1EU) -#define CSS_CSS_KS14_ks14_rsvd0_SHIFT (1U) -/*! ks14_rsvd0 - Reserved 0 - */ -#define CSS_CSS_KS14_ks14_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_rsvd0_SHIFT)) & CSS_CSS_KS14_ks14_rsvd0_MASK) - -#define CSS_CSS_KS14_ks14_kact_MASK (0x20U) -#define CSS_CSS_KS14_ks14_kact_SHIFT (5U) -/*! ks14_kact - Key is active - */ -#define CSS_CSS_KS14_ks14_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_kact_SHIFT)) & CSS_CSS_KS14_ks14_kact_MASK) - -#define CSS_CSS_KS14_ks14_kbase_MASK (0x40U) -#define CSS_CSS_KS14_ks14_kbase_SHIFT (6U) -/*! ks14_kbase - First slot in a multislot key - */ -#define CSS_CSS_KS14_ks14_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_kbase_SHIFT)) & CSS_CSS_KS14_ks14_kbase_MASK) - -#define CSS_CSS_KS14_ks14_fgp_MASK (0x80U) -#define CSS_CSS_KS14_ks14_fgp_SHIFT (7U) -/*! ks14_fgp - Hardware Feature General Purpose - */ -#define CSS_CSS_KS14_ks14_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_fgp_SHIFT)) & CSS_CSS_KS14_ks14_fgp_MASK) - -#define CSS_CSS_KS14_ks14_frtn_MASK (0x100U) -#define CSS_CSS_KS14_ks14_frtn_SHIFT (8U) -/*! ks14_frtn - Hardware Feature Retention - */ -#define CSS_CSS_KS14_ks14_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_frtn_SHIFT)) & CSS_CSS_KS14_ks14_frtn_MASK) - -#define CSS_CSS_KS14_ks14_fhwo_MASK (0x200U) -#define CSS_CSS_KS14_ks14_fhwo_SHIFT (9U) -/*! ks14_fhwo - Hardware Feature Output - */ -#define CSS_CSS_KS14_ks14_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_fhwo_SHIFT)) & CSS_CSS_KS14_ks14_fhwo_MASK) - -#define CSS_CSS_KS14_ks14_rsvd1_MASK (0x1C00U) -#define CSS_CSS_KS14_ks14_rsvd1_SHIFT (10U) -/*! ks14_rsvd1 - Reserved 1 - */ -#define CSS_CSS_KS14_ks14_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_rsvd1_SHIFT)) & CSS_CSS_KS14_ks14_rsvd1_MASK) - -#define CSS_CSS_KS14_ks14_ucmac_MASK (0x2000U) -#define CSS_CSS_KS14_ks14_ucmac_SHIFT (13U) -/*! ks14_ucmac - CMAC key - */ -#define CSS_CSS_KS14_ks14_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_ucmac_SHIFT)) & CSS_CSS_KS14_ks14_ucmac_MASK) - -#define CSS_CSS_KS14_ks14_uksk_MASK (0x4000U) -#define CSS_CSS_KS14_ks14_uksk_SHIFT (14U) -/*! ks14_uksk - KSK key - */ -#define CSS_CSS_KS14_ks14_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uksk_SHIFT)) & CSS_CSS_KS14_ks14_uksk_MASK) - -#define CSS_CSS_KS14_ks14_urtf_MASK (0x8000U) -#define CSS_CSS_KS14_ks14_urtf_SHIFT (15U) -/*! ks14_urtf - Real Time Fingerprint key - */ -#define CSS_CSS_KS14_ks14_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_urtf_SHIFT)) & CSS_CSS_KS14_ks14_urtf_MASK) - -#define CSS_CSS_KS14_ks14_uckdf_MASK (0x10000U) -#define CSS_CSS_KS14_ks14_uckdf_SHIFT (16U) -/*! ks14_uckdf - Derivation key for CKDF command - */ -#define CSS_CSS_KS14_ks14_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uckdf_SHIFT)) & CSS_CSS_KS14_ks14_uckdf_MASK) - -#define CSS_CSS_KS14_ks14_uhkdf_MASK (0x20000U) -#define CSS_CSS_KS14_ks14_uhkdf_SHIFT (17U) -/*! ks14_uhkdf - Derivation key for HKDF command - */ -#define CSS_CSS_KS14_ks14_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uhkdf_SHIFT)) & CSS_CSS_KS14_ks14_uhkdf_MASK) - -#define CSS_CSS_KS14_ks14_uecsg_MASK (0x40000U) -#define CSS_CSS_KS14_ks14_uecsg_SHIFT (18U) -/*! ks14_uecsg - Ecc signing key - */ -#define CSS_CSS_KS14_ks14_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uecsg_SHIFT)) & CSS_CSS_KS14_ks14_uecsg_MASK) - -#define CSS_CSS_KS14_ks14_uecdh_MASK (0x80000U) -#define CSS_CSS_KS14_ks14_uecdh_SHIFT (19U) -/*! ks14_uecdh - Ecc diffie hellman key - */ -#define CSS_CSS_KS14_ks14_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uecdh_SHIFT)) & CSS_CSS_KS14_ks14_uecdh_MASK) - -#define CSS_CSS_KS14_ks14_uaes_MASK (0x100000U) -#define CSS_CSS_KS14_ks14_uaes_SHIFT (20U) -/*! ks14_uaes - Aes key - */ -#define CSS_CSS_KS14_ks14_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uaes_SHIFT)) & CSS_CSS_KS14_ks14_uaes_MASK) - -#define CSS_CSS_KS14_ks14_uhmac_MASK (0x200000U) -#define CSS_CSS_KS14_ks14_uhmac_SHIFT (21U) -/*! ks14_uhmac - Hmac key - */ -#define CSS_CSS_KS14_ks14_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uhmac_SHIFT)) & CSS_CSS_KS14_ks14_uhmac_MASK) - -#define CSS_CSS_KS14_ks14_ukwk_MASK (0x400000U) -#define CSS_CSS_KS14_ks14_ukwk_SHIFT (22U) -/*! ks14_ukwk - Key wrapping key - */ -#define CSS_CSS_KS14_ks14_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_ukwk_SHIFT)) & CSS_CSS_KS14_ks14_ukwk_MASK) - -#define CSS_CSS_KS14_ks14_ukuok_MASK (0x800000U) -#define CSS_CSS_KS14_ks14_ukuok_SHIFT (23U) -/*! ks14_ukuok - Key unwrapping key - */ -#define CSS_CSS_KS14_ks14_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_ukuok_SHIFT)) & CSS_CSS_KS14_ks14_ukuok_MASK) - -#define CSS_CSS_KS14_ks14_utlspms_MASK (0x1000000U) -#define CSS_CSS_KS14_ks14_utlspms_SHIFT (24U) -/*! ks14_utlspms - TLS Pre Master Secret - */ -#define CSS_CSS_KS14_ks14_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_utlspms_SHIFT)) & CSS_CSS_KS14_ks14_utlspms_MASK) - -#define CSS_CSS_KS14_ks14_utlsms_MASK (0x2000000U) -#define CSS_CSS_KS14_ks14_utlsms_SHIFT (25U) -/*! ks14_utlsms - TLS Master Secret - */ -#define CSS_CSS_KS14_ks14_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_utlsms_SHIFT)) & CSS_CSS_KS14_ks14_utlsms_MASK) - -#define CSS_CSS_KS14_ks14_ukgsrc_MASK (0x4000000U) -#define CSS_CSS_KS14_ks14_ukgsrc_SHIFT (26U) -/*! ks14_ukgsrc - Supply KEYGEN source - */ -#define CSS_CSS_KS14_ks14_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_ukgsrc_SHIFT)) & CSS_CSS_KS14_ks14_ukgsrc_MASK) - -#define CSS_CSS_KS14_ks14_uhwo_MASK (0x8000000U) -#define CSS_CSS_KS14_ks14_uhwo_SHIFT (27U) -/*! ks14_uhwo - Hardware out key - */ -#define CSS_CSS_KS14_ks14_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uhwo_SHIFT)) & CSS_CSS_KS14_ks14_uhwo_MASK) - -#define CSS_CSS_KS14_ks14_uwrpok_MASK (0x10000000U) -#define CSS_CSS_KS14_ks14_uwrpok_SHIFT (28U) -/*! ks14_uwrpok - Ok to wrap key - */ -#define CSS_CSS_KS14_ks14_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uwrpok_SHIFT)) & CSS_CSS_KS14_ks14_uwrpok_MASK) - -#define CSS_CSS_KS14_ks14_uduk_MASK (0x20000000U) -#define CSS_CSS_KS14_ks14_uduk_SHIFT (29U) -/*! ks14_uduk - Device Unique Key - */ -#define CSS_CSS_KS14_ks14_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uduk_SHIFT)) & CSS_CSS_KS14_ks14_uduk_MASK) - -#define CSS_CSS_KS14_ks14_upprot_MASK (0xC0000000U) -#define CSS_CSS_KS14_ks14_upprot_SHIFT (30U) -/*! ks14_upprot - Priviledge level - */ -#define CSS_CSS_KS14_ks14_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_upprot_SHIFT)) & CSS_CSS_KS14_ks14_upprot_MASK) -/*! @} */ - -/*! @name CSS_KS15 - Status register */ -/*! @{ */ - -#define CSS_CSS_KS15_ks15_ksize_MASK (0x1U) -#define CSS_CSS_KS15_ks15_ksize_SHIFT (0U) -/*! ks15_ksize - Key size: 0-128, 1-256 - */ -#define CSS_CSS_KS15_ks15_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_ksize_SHIFT)) & CSS_CSS_KS15_ks15_ksize_MASK) - -#define CSS_CSS_KS15_ks15_rsvd0_MASK (0x1EU) -#define CSS_CSS_KS15_ks15_rsvd0_SHIFT (1U) -/*! ks15_rsvd0 - Reserved 0 - */ -#define CSS_CSS_KS15_ks15_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_rsvd0_SHIFT)) & CSS_CSS_KS15_ks15_rsvd0_MASK) - -#define CSS_CSS_KS15_ks15_kact_MASK (0x20U) -#define CSS_CSS_KS15_ks15_kact_SHIFT (5U) -/*! ks15_kact - Key is active - */ -#define CSS_CSS_KS15_ks15_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_kact_SHIFT)) & CSS_CSS_KS15_ks15_kact_MASK) - -#define CSS_CSS_KS15_ks15_kbase_MASK (0x40U) -#define CSS_CSS_KS15_ks15_kbase_SHIFT (6U) -/*! ks15_kbase - First slot in a multislot key - */ -#define CSS_CSS_KS15_ks15_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_kbase_SHIFT)) & CSS_CSS_KS15_ks15_kbase_MASK) - -#define CSS_CSS_KS15_ks15_fgp_MASK (0x80U) -#define CSS_CSS_KS15_ks15_fgp_SHIFT (7U) -/*! ks15_fgp - Hardware Feature General Purpose - */ -#define CSS_CSS_KS15_ks15_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_fgp_SHIFT)) & CSS_CSS_KS15_ks15_fgp_MASK) - -#define CSS_CSS_KS15_ks15_frtn_MASK (0x100U) -#define CSS_CSS_KS15_ks15_frtn_SHIFT (8U) -/*! ks15_frtn - Hardware Feature Retention - */ -#define CSS_CSS_KS15_ks15_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_frtn_SHIFT)) & CSS_CSS_KS15_ks15_frtn_MASK) - -#define CSS_CSS_KS15_ks15_fhwo_MASK (0x200U) -#define CSS_CSS_KS15_ks15_fhwo_SHIFT (9U) -/*! ks15_fhwo - Hardware Feature Output - */ -#define CSS_CSS_KS15_ks15_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_fhwo_SHIFT)) & CSS_CSS_KS15_ks15_fhwo_MASK) - -#define CSS_CSS_KS15_ks15_rsvd1_MASK (0x1C00U) -#define CSS_CSS_KS15_ks15_rsvd1_SHIFT (10U) -/*! ks15_rsvd1 - Reserved 1 - */ -#define CSS_CSS_KS15_ks15_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_rsvd1_SHIFT)) & CSS_CSS_KS15_ks15_rsvd1_MASK) - -#define CSS_CSS_KS15_ks15_ucmac_MASK (0x2000U) -#define CSS_CSS_KS15_ks15_ucmac_SHIFT (13U) -/*! ks15_ucmac - CMAC key - */ -#define CSS_CSS_KS15_ks15_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_ucmac_SHIFT)) & CSS_CSS_KS15_ks15_ucmac_MASK) - -#define CSS_CSS_KS15_ks15_uksk_MASK (0x4000U) -#define CSS_CSS_KS15_ks15_uksk_SHIFT (14U) -/*! ks15_uksk - KSK key - */ -#define CSS_CSS_KS15_ks15_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uksk_SHIFT)) & CSS_CSS_KS15_ks15_uksk_MASK) - -#define CSS_CSS_KS15_ks15_urtf_MASK (0x8000U) -#define CSS_CSS_KS15_ks15_urtf_SHIFT (15U) -/*! ks15_urtf - Real Time Fingerprint key - */ -#define CSS_CSS_KS15_ks15_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_urtf_SHIFT)) & CSS_CSS_KS15_ks15_urtf_MASK) - -#define CSS_CSS_KS15_ks15_uckdf_MASK (0x10000U) -#define CSS_CSS_KS15_ks15_uckdf_SHIFT (16U) -/*! ks15_uckdf - Derivation key for CKDF command - */ -#define CSS_CSS_KS15_ks15_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uckdf_SHIFT)) & CSS_CSS_KS15_ks15_uckdf_MASK) - -#define CSS_CSS_KS15_ks15_uhkdf_MASK (0x20000U) -#define CSS_CSS_KS15_ks15_uhkdf_SHIFT (17U) -/*! ks15_uhkdf - Derivation key for HKDF command - */ -#define CSS_CSS_KS15_ks15_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uhkdf_SHIFT)) & CSS_CSS_KS15_ks15_uhkdf_MASK) - -#define CSS_CSS_KS15_ks15_uecsg_MASK (0x40000U) -#define CSS_CSS_KS15_ks15_uecsg_SHIFT (18U) -/*! ks15_uecsg - Ecc signing key - */ -#define CSS_CSS_KS15_ks15_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uecsg_SHIFT)) & CSS_CSS_KS15_ks15_uecsg_MASK) - -#define CSS_CSS_KS15_ks15_uecdh_MASK (0x80000U) -#define CSS_CSS_KS15_ks15_uecdh_SHIFT (19U) -/*! ks15_uecdh - Ecc diffie hellman key - */ -#define CSS_CSS_KS15_ks15_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uecdh_SHIFT)) & CSS_CSS_KS15_ks15_uecdh_MASK) - -#define CSS_CSS_KS15_ks15_uaes_MASK (0x100000U) -#define CSS_CSS_KS15_ks15_uaes_SHIFT (20U) -/*! ks15_uaes - Aes key - */ -#define CSS_CSS_KS15_ks15_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uaes_SHIFT)) & CSS_CSS_KS15_ks15_uaes_MASK) - -#define CSS_CSS_KS15_ks15_uhmac_MASK (0x200000U) -#define CSS_CSS_KS15_ks15_uhmac_SHIFT (21U) -/*! ks15_uhmac - Hmac key - */ -#define CSS_CSS_KS15_ks15_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uhmac_SHIFT)) & CSS_CSS_KS15_ks15_uhmac_MASK) - -#define CSS_CSS_KS15_ks15_ukwk_MASK (0x400000U) -#define CSS_CSS_KS15_ks15_ukwk_SHIFT (22U) -/*! ks15_ukwk - Key wrapping key - */ -#define CSS_CSS_KS15_ks15_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_ukwk_SHIFT)) & CSS_CSS_KS15_ks15_ukwk_MASK) - -#define CSS_CSS_KS15_ks15_ukuok_MASK (0x800000U) -#define CSS_CSS_KS15_ks15_ukuok_SHIFT (23U) -/*! ks15_ukuok - Key unwrapping key - */ -#define CSS_CSS_KS15_ks15_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_ukuok_SHIFT)) & CSS_CSS_KS15_ks15_ukuok_MASK) - -#define CSS_CSS_KS15_ks15_utlspms_MASK (0x1000000U) -#define CSS_CSS_KS15_ks15_utlspms_SHIFT (24U) -/*! ks15_utlspms - TLS Pre Master Secret - */ -#define CSS_CSS_KS15_ks15_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_utlspms_SHIFT)) & CSS_CSS_KS15_ks15_utlspms_MASK) - -#define CSS_CSS_KS15_ks15_utlsms_MASK (0x2000000U) -#define CSS_CSS_KS15_ks15_utlsms_SHIFT (25U) -/*! ks15_utlsms - TLS Master Secret - */ -#define CSS_CSS_KS15_ks15_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_utlsms_SHIFT)) & CSS_CSS_KS15_ks15_utlsms_MASK) - -#define CSS_CSS_KS15_ks15_ukgsrc_MASK (0x4000000U) -#define CSS_CSS_KS15_ks15_ukgsrc_SHIFT (26U) -/*! ks15_ukgsrc - Supply KEYGEN source - */ -#define CSS_CSS_KS15_ks15_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_ukgsrc_SHIFT)) & CSS_CSS_KS15_ks15_ukgsrc_MASK) - -#define CSS_CSS_KS15_ks15_uhwo_MASK (0x8000000U) -#define CSS_CSS_KS15_ks15_uhwo_SHIFT (27U) -/*! ks15_uhwo - Hardware out key - */ -#define CSS_CSS_KS15_ks15_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uhwo_SHIFT)) & CSS_CSS_KS15_ks15_uhwo_MASK) - -#define CSS_CSS_KS15_ks15_uwrpok_MASK (0x10000000U) -#define CSS_CSS_KS15_ks15_uwrpok_SHIFT (28U) -/*! ks15_uwrpok - Ok to wrap key - */ -#define CSS_CSS_KS15_ks15_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uwrpok_SHIFT)) & CSS_CSS_KS15_ks15_uwrpok_MASK) - -#define CSS_CSS_KS15_ks15_uduk_MASK (0x20000000U) -#define CSS_CSS_KS15_ks15_uduk_SHIFT (29U) -/*! ks15_uduk - Device Unique Key - */ -#define CSS_CSS_KS15_ks15_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uduk_SHIFT)) & CSS_CSS_KS15_ks15_uduk_MASK) - -#define CSS_CSS_KS15_ks15_upprot_MASK (0xC0000000U) -#define CSS_CSS_KS15_ks15_upprot_SHIFT (30U) -/*! ks15_upprot - Priviledge level - */ -#define CSS_CSS_KS15_ks15_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_upprot_SHIFT)) & CSS_CSS_KS15_ks15_upprot_MASK) -/*! @} */ - -/*! @name CSS_KS16 - Status register */ -/*! @{ */ - -#define CSS_CSS_KS16_ks16_ksize_MASK (0x1U) -#define CSS_CSS_KS16_ks16_ksize_SHIFT (0U) -/*! ks16_ksize - Key size: 0-128, 1-256 - */ -#define CSS_CSS_KS16_ks16_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_ksize_SHIFT)) & CSS_CSS_KS16_ks16_ksize_MASK) - -#define CSS_CSS_KS16_ks16_rsvd0_MASK (0x1EU) -#define CSS_CSS_KS16_ks16_rsvd0_SHIFT (1U) -/*! ks16_rsvd0 - Reserved 0 - */ -#define CSS_CSS_KS16_ks16_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_rsvd0_SHIFT)) & CSS_CSS_KS16_ks16_rsvd0_MASK) - -#define CSS_CSS_KS16_ks16_kact_MASK (0x20U) -#define CSS_CSS_KS16_ks16_kact_SHIFT (5U) -/*! ks16_kact - Key is active - */ -#define CSS_CSS_KS16_ks16_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_kact_SHIFT)) & CSS_CSS_KS16_ks16_kact_MASK) - -#define CSS_CSS_KS16_ks16_kbase_MASK (0x40U) -#define CSS_CSS_KS16_ks16_kbase_SHIFT (6U) -/*! ks16_kbase - First slot in a multislot key - */ -#define CSS_CSS_KS16_ks16_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_kbase_SHIFT)) & CSS_CSS_KS16_ks16_kbase_MASK) - -#define CSS_CSS_KS16_ks16_fgp_MASK (0x80U) -#define CSS_CSS_KS16_ks16_fgp_SHIFT (7U) -/*! ks16_fgp - Hardware Feature General Purpose - */ -#define CSS_CSS_KS16_ks16_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_fgp_SHIFT)) & CSS_CSS_KS16_ks16_fgp_MASK) - -#define CSS_CSS_KS16_ks16_frtn_MASK (0x100U) -#define CSS_CSS_KS16_ks16_frtn_SHIFT (8U) -/*! ks16_frtn - Hardware Feature Retention - */ -#define CSS_CSS_KS16_ks16_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_frtn_SHIFT)) & CSS_CSS_KS16_ks16_frtn_MASK) - -#define CSS_CSS_KS16_ks16_fhwo_MASK (0x200U) -#define CSS_CSS_KS16_ks16_fhwo_SHIFT (9U) -/*! ks16_fhwo - Hardware Feature Output - */ -#define CSS_CSS_KS16_ks16_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_fhwo_SHIFT)) & CSS_CSS_KS16_ks16_fhwo_MASK) - -#define CSS_CSS_KS16_ks16_rsvd1_MASK (0x1C00U) -#define CSS_CSS_KS16_ks16_rsvd1_SHIFT (10U) -/*! ks16_rsvd1 - Reserved 1 - */ -#define CSS_CSS_KS16_ks16_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_rsvd1_SHIFT)) & CSS_CSS_KS16_ks16_rsvd1_MASK) - -#define CSS_CSS_KS16_ks16_ucmac_MASK (0x2000U) -#define CSS_CSS_KS16_ks16_ucmac_SHIFT (13U) -/*! ks16_ucmac - CMAC key - */ -#define CSS_CSS_KS16_ks16_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_ucmac_SHIFT)) & CSS_CSS_KS16_ks16_ucmac_MASK) - -#define CSS_CSS_KS16_ks16_uksk_MASK (0x4000U) -#define CSS_CSS_KS16_ks16_uksk_SHIFT (14U) -/*! ks16_uksk - KSK key - */ -#define CSS_CSS_KS16_ks16_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uksk_SHIFT)) & CSS_CSS_KS16_ks16_uksk_MASK) - -#define CSS_CSS_KS16_ks16_urtf_MASK (0x8000U) -#define CSS_CSS_KS16_ks16_urtf_SHIFT (15U) -/*! ks16_urtf - Real Time Fingerprint key - */ -#define CSS_CSS_KS16_ks16_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_urtf_SHIFT)) & CSS_CSS_KS16_ks16_urtf_MASK) - -#define CSS_CSS_KS16_ks16_uckdf_MASK (0x10000U) -#define CSS_CSS_KS16_ks16_uckdf_SHIFT (16U) -/*! ks16_uckdf - Derivation key for CKDF command - */ -#define CSS_CSS_KS16_ks16_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uckdf_SHIFT)) & CSS_CSS_KS16_ks16_uckdf_MASK) - -#define CSS_CSS_KS16_ks16_uhkdf_MASK (0x20000U) -#define CSS_CSS_KS16_ks16_uhkdf_SHIFT (17U) -/*! ks16_uhkdf - Derivation key for HKDF command - */ -#define CSS_CSS_KS16_ks16_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uhkdf_SHIFT)) & CSS_CSS_KS16_ks16_uhkdf_MASK) - -#define CSS_CSS_KS16_ks16_uecsg_MASK (0x40000U) -#define CSS_CSS_KS16_ks16_uecsg_SHIFT (18U) -/*! ks16_uecsg - Ecc signing key - */ -#define CSS_CSS_KS16_ks16_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uecsg_SHIFT)) & CSS_CSS_KS16_ks16_uecsg_MASK) - -#define CSS_CSS_KS16_ks16_uecdh_MASK (0x80000U) -#define CSS_CSS_KS16_ks16_uecdh_SHIFT (19U) -/*! ks16_uecdh - Ecc diffie hellman key - */ -#define CSS_CSS_KS16_ks16_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uecdh_SHIFT)) & CSS_CSS_KS16_ks16_uecdh_MASK) - -#define CSS_CSS_KS16_ks16_uaes_MASK (0x100000U) -#define CSS_CSS_KS16_ks16_uaes_SHIFT (20U) -/*! ks16_uaes - Aes key - */ -#define CSS_CSS_KS16_ks16_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uaes_SHIFT)) & CSS_CSS_KS16_ks16_uaes_MASK) - -#define CSS_CSS_KS16_ks16_uhmac_MASK (0x200000U) -#define CSS_CSS_KS16_ks16_uhmac_SHIFT (21U) -/*! ks16_uhmac - Hmac key - */ -#define CSS_CSS_KS16_ks16_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uhmac_SHIFT)) & CSS_CSS_KS16_ks16_uhmac_MASK) - -#define CSS_CSS_KS16_ks16_ukwk_MASK (0x400000U) -#define CSS_CSS_KS16_ks16_ukwk_SHIFT (22U) -/*! ks16_ukwk - Key wrapping key - */ -#define CSS_CSS_KS16_ks16_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_ukwk_SHIFT)) & CSS_CSS_KS16_ks16_ukwk_MASK) - -#define CSS_CSS_KS16_ks16_ukuok_MASK (0x800000U) -#define CSS_CSS_KS16_ks16_ukuok_SHIFT (23U) -/*! ks16_ukuok - Key unwrapping key - */ -#define CSS_CSS_KS16_ks16_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_ukuok_SHIFT)) & CSS_CSS_KS16_ks16_ukuok_MASK) - -#define CSS_CSS_KS16_ks16_utlspms_MASK (0x1000000U) -#define CSS_CSS_KS16_ks16_utlspms_SHIFT (24U) -/*! ks16_utlspms - TLS Pre Master Secret - */ -#define CSS_CSS_KS16_ks16_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_utlspms_SHIFT)) & CSS_CSS_KS16_ks16_utlspms_MASK) - -#define CSS_CSS_KS16_ks16_utlsms_MASK (0x2000000U) -#define CSS_CSS_KS16_ks16_utlsms_SHIFT (25U) -/*! ks16_utlsms - TLS Master Secret - */ -#define CSS_CSS_KS16_ks16_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_utlsms_SHIFT)) & CSS_CSS_KS16_ks16_utlsms_MASK) - -#define CSS_CSS_KS16_ks16_ukgsrc_MASK (0x4000000U) -#define CSS_CSS_KS16_ks16_ukgsrc_SHIFT (26U) -/*! ks16_ukgsrc - Supply KEYGEN source - */ -#define CSS_CSS_KS16_ks16_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_ukgsrc_SHIFT)) & CSS_CSS_KS16_ks16_ukgsrc_MASK) - -#define CSS_CSS_KS16_ks16_uhwo_MASK (0x8000000U) -#define CSS_CSS_KS16_ks16_uhwo_SHIFT (27U) -/*! ks16_uhwo - Hardware out key - */ -#define CSS_CSS_KS16_ks16_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uhwo_SHIFT)) & CSS_CSS_KS16_ks16_uhwo_MASK) - -#define CSS_CSS_KS16_ks16_uwrpok_MASK (0x10000000U) -#define CSS_CSS_KS16_ks16_uwrpok_SHIFT (28U) -/*! ks16_uwrpok - Ok to wrap key - */ -#define CSS_CSS_KS16_ks16_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uwrpok_SHIFT)) & CSS_CSS_KS16_ks16_uwrpok_MASK) - -#define CSS_CSS_KS16_ks16_uduk_MASK (0x20000000U) -#define CSS_CSS_KS16_ks16_uduk_SHIFT (29U) -/*! ks16_uduk - Device Unique Key - */ -#define CSS_CSS_KS16_ks16_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uduk_SHIFT)) & CSS_CSS_KS16_ks16_uduk_MASK) - -#define CSS_CSS_KS16_ks16_upprot_MASK (0xC0000000U) -#define CSS_CSS_KS16_ks16_upprot_SHIFT (30U) -/*! ks16_upprot - Priviledge level - */ -#define CSS_CSS_KS16_ks16_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_upprot_SHIFT)) & CSS_CSS_KS16_ks16_upprot_MASK) -/*! @} */ - -/*! @name CSS_KS17 - Status register */ -/*! @{ */ - -#define CSS_CSS_KS17_ks17_ksize_MASK (0x1U) -#define CSS_CSS_KS17_ks17_ksize_SHIFT (0U) -/*! ks17_ksize - Key size: 0-128, 1-256 - */ -#define CSS_CSS_KS17_ks17_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_ksize_SHIFT)) & CSS_CSS_KS17_ks17_ksize_MASK) - -#define CSS_CSS_KS17_ks17_rsvd0_MASK (0x1EU) -#define CSS_CSS_KS17_ks17_rsvd0_SHIFT (1U) -/*! ks17_rsvd0 - Reserved 0 - */ -#define CSS_CSS_KS17_ks17_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_rsvd0_SHIFT)) & CSS_CSS_KS17_ks17_rsvd0_MASK) - -#define CSS_CSS_KS17_ks17_kact_MASK (0x20U) -#define CSS_CSS_KS17_ks17_kact_SHIFT (5U) -/*! ks17_kact - Key is active - */ -#define CSS_CSS_KS17_ks17_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_kact_SHIFT)) & CSS_CSS_KS17_ks17_kact_MASK) - -#define CSS_CSS_KS17_ks17_kbase_MASK (0x40U) -#define CSS_CSS_KS17_ks17_kbase_SHIFT (6U) -/*! ks17_kbase - First slot in a multislot key - */ -#define CSS_CSS_KS17_ks17_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_kbase_SHIFT)) & CSS_CSS_KS17_ks17_kbase_MASK) - -#define CSS_CSS_KS17_ks17_fgp_MASK (0x80U) -#define CSS_CSS_KS17_ks17_fgp_SHIFT (7U) -/*! ks17_fgp - Hardware Feature General Purpose - */ -#define CSS_CSS_KS17_ks17_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_fgp_SHIFT)) & CSS_CSS_KS17_ks17_fgp_MASK) - -#define CSS_CSS_KS17_ks17_frtn_MASK (0x100U) -#define CSS_CSS_KS17_ks17_frtn_SHIFT (8U) -/*! ks17_frtn - Hardware Feature Retention - */ -#define CSS_CSS_KS17_ks17_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_frtn_SHIFT)) & CSS_CSS_KS17_ks17_frtn_MASK) - -#define CSS_CSS_KS17_ks17_fhwo_MASK (0x200U) -#define CSS_CSS_KS17_ks17_fhwo_SHIFT (9U) -/*! ks17_fhwo - Hardware Feature Output - */ -#define CSS_CSS_KS17_ks17_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_fhwo_SHIFT)) & CSS_CSS_KS17_ks17_fhwo_MASK) - -#define CSS_CSS_KS17_ks17_rsvd1_MASK (0x1C00U) -#define CSS_CSS_KS17_ks17_rsvd1_SHIFT (10U) -/*! ks17_rsvd1 - Reserved 1 - */ -#define CSS_CSS_KS17_ks17_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_rsvd1_SHIFT)) & CSS_CSS_KS17_ks17_rsvd1_MASK) - -#define CSS_CSS_KS17_ks17_ucmac_MASK (0x2000U) -#define CSS_CSS_KS17_ks17_ucmac_SHIFT (13U) -/*! ks17_ucmac - CMAC key - */ -#define CSS_CSS_KS17_ks17_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_ucmac_SHIFT)) & CSS_CSS_KS17_ks17_ucmac_MASK) - -#define CSS_CSS_KS17_ks17_uksk_MASK (0x4000U) -#define CSS_CSS_KS17_ks17_uksk_SHIFT (14U) -/*! ks17_uksk - KSK key - */ -#define CSS_CSS_KS17_ks17_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uksk_SHIFT)) & CSS_CSS_KS17_ks17_uksk_MASK) - -#define CSS_CSS_KS17_ks17_urtf_MASK (0x8000U) -#define CSS_CSS_KS17_ks17_urtf_SHIFT (15U) -/*! ks17_urtf - Real Time Fingerprint key - */ -#define CSS_CSS_KS17_ks17_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_urtf_SHIFT)) & CSS_CSS_KS17_ks17_urtf_MASK) - -#define CSS_CSS_KS17_ks17_uckdf_MASK (0x10000U) -#define CSS_CSS_KS17_ks17_uckdf_SHIFT (16U) -/*! ks17_uckdf - Derivation key for CKDF command - */ -#define CSS_CSS_KS17_ks17_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uckdf_SHIFT)) & CSS_CSS_KS17_ks17_uckdf_MASK) - -#define CSS_CSS_KS17_ks17_uhkdf_MASK (0x20000U) -#define CSS_CSS_KS17_ks17_uhkdf_SHIFT (17U) -/*! ks17_uhkdf - Derivation key for HKDF command - */ -#define CSS_CSS_KS17_ks17_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uhkdf_SHIFT)) & CSS_CSS_KS17_ks17_uhkdf_MASK) - -#define CSS_CSS_KS17_ks17_uecsg_MASK (0x40000U) -#define CSS_CSS_KS17_ks17_uecsg_SHIFT (18U) -/*! ks17_uecsg - Ecc signing key - */ -#define CSS_CSS_KS17_ks17_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uecsg_SHIFT)) & CSS_CSS_KS17_ks17_uecsg_MASK) - -#define CSS_CSS_KS17_ks17_uecdh_MASK (0x80000U) -#define CSS_CSS_KS17_ks17_uecdh_SHIFT (19U) -/*! ks17_uecdh - Ecc diffie hellman key - */ -#define CSS_CSS_KS17_ks17_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uecdh_SHIFT)) & CSS_CSS_KS17_ks17_uecdh_MASK) - -#define CSS_CSS_KS17_ks17_uaes_MASK (0x100000U) -#define CSS_CSS_KS17_ks17_uaes_SHIFT (20U) -/*! ks17_uaes - Aes key - */ -#define CSS_CSS_KS17_ks17_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uaes_SHIFT)) & CSS_CSS_KS17_ks17_uaes_MASK) - -#define CSS_CSS_KS17_ks17_uhmac_MASK (0x200000U) -#define CSS_CSS_KS17_ks17_uhmac_SHIFT (21U) -/*! ks17_uhmac - Hmac key - */ -#define CSS_CSS_KS17_ks17_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uhmac_SHIFT)) & CSS_CSS_KS17_ks17_uhmac_MASK) - -#define CSS_CSS_KS17_ks17_ukwk_MASK (0x400000U) -#define CSS_CSS_KS17_ks17_ukwk_SHIFT (22U) -/*! ks17_ukwk - Key wrapping key - */ -#define CSS_CSS_KS17_ks17_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_ukwk_SHIFT)) & CSS_CSS_KS17_ks17_ukwk_MASK) - -#define CSS_CSS_KS17_ks17_ukuok_MASK (0x800000U) -#define CSS_CSS_KS17_ks17_ukuok_SHIFT (23U) -/*! ks17_ukuok - Key unwrapping key - */ -#define CSS_CSS_KS17_ks17_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_ukuok_SHIFT)) & CSS_CSS_KS17_ks17_ukuok_MASK) - -#define CSS_CSS_KS17_ks17_utlspms_MASK (0x1000000U) -#define CSS_CSS_KS17_ks17_utlspms_SHIFT (24U) -/*! ks17_utlspms - TLS Pre Master Secret - */ -#define CSS_CSS_KS17_ks17_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_utlspms_SHIFT)) & CSS_CSS_KS17_ks17_utlspms_MASK) - -#define CSS_CSS_KS17_ks17_utlsms_MASK (0x2000000U) -#define CSS_CSS_KS17_ks17_utlsms_SHIFT (25U) -/*! ks17_utlsms - TLS Master Secret - */ -#define CSS_CSS_KS17_ks17_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_utlsms_SHIFT)) & CSS_CSS_KS17_ks17_utlsms_MASK) - -#define CSS_CSS_KS17_ks17_ukgsrc_MASK (0x4000000U) -#define CSS_CSS_KS17_ks17_ukgsrc_SHIFT (26U) -/*! ks17_ukgsrc - Supply KEYGEN source - */ -#define CSS_CSS_KS17_ks17_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_ukgsrc_SHIFT)) & CSS_CSS_KS17_ks17_ukgsrc_MASK) - -#define CSS_CSS_KS17_ks17_uhwo_MASK (0x8000000U) -#define CSS_CSS_KS17_ks17_uhwo_SHIFT (27U) -/*! ks17_uhwo - Hardware out key - */ -#define CSS_CSS_KS17_ks17_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uhwo_SHIFT)) & CSS_CSS_KS17_ks17_uhwo_MASK) - -#define CSS_CSS_KS17_ks17_uwrpok_MASK (0x10000000U) -#define CSS_CSS_KS17_ks17_uwrpok_SHIFT (28U) -/*! ks17_uwrpok - Ok to wrap key - */ -#define CSS_CSS_KS17_ks17_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uwrpok_SHIFT)) & CSS_CSS_KS17_ks17_uwrpok_MASK) - -#define CSS_CSS_KS17_ks17_uduk_MASK (0x20000000U) -#define CSS_CSS_KS17_ks17_uduk_SHIFT (29U) -/*! ks17_uduk - Device Unique Key - */ -#define CSS_CSS_KS17_ks17_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uduk_SHIFT)) & CSS_CSS_KS17_ks17_uduk_MASK) - -#define CSS_CSS_KS17_ks17_upprot_MASK (0xC0000000U) -#define CSS_CSS_KS17_ks17_upprot_SHIFT (30U) -/*! ks17_upprot - Priviledge level - */ -#define CSS_CSS_KS17_ks17_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_upprot_SHIFT)) & CSS_CSS_KS17_ks17_upprot_MASK) -/*! @} */ - -/*! @name CSS_KS18 - Status register */ -/*! @{ */ - -#define CSS_CSS_KS18_ks18_ksize_MASK (0x1U) -#define CSS_CSS_KS18_ks18_ksize_SHIFT (0U) -/*! ks18_ksize - Key size: 0-128, 1-256 - */ -#define CSS_CSS_KS18_ks18_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_ksize_SHIFT)) & CSS_CSS_KS18_ks18_ksize_MASK) - -#define CSS_CSS_KS18_ks18_rsvd0_MASK (0x1EU) -#define CSS_CSS_KS18_ks18_rsvd0_SHIFT (1U) -/*! ks18_rsvd0 - Reserved 0 - */ -#define CSS_CSS_KS18_ks18_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_rsvd0_SHIFT)) & CSS_CSS_KS18_ks18_rsvd0_MASK) - -#define CSS_CSS_KS18_ks18_kact_MASK (0x20U) -#define CSS_CSS_KS18_ks18_kact_SHIFT (5U) -/*! ks18_kact - Key is active - */ -#define CSS_CSS_KS18_ks18_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_kact_SHIFT)) & CSS_CSS_KS18_ks18_kact_MASK) - -#define CSS_CSS_KS18_ks18_kbase_MASK (0x40U) -#define CSS_CSS_KS18_ks18_kbase_SHIFT (6U) -/*! ks18_kbase - First slot in a multislot key - */ -#define CSS_CSS_KS18_ks18_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_kbase_SHIFT)) & CSS_CSS_KS18_ks18_kbase_MASK) - -#define CSS_CSS_KS18_ks18_fgp_MASK (0x80U) -#define CSS_CSS_KS18_ks18_fgp_SHIFT (7U) -/*! ks18_fgp - Hardware Feature General Purpose - */ -#define CSS_CSS_KS18_ks18_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_fgp_SHIFT)) & CSS_CSS_KS18_ks18_fgp_MASK) - -#define CSS_CSS_KS18_ks18_frtn_MASK (0x100U) -#define CSS_CSS_KS18_ks18_frtn_SHIFT (8U) -/*! ks18_frtn - Hardware Feature Retention - */ -#define CSS_CSS_KS18_ks18_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_frtn_SHIFT)) & CSS_CSS_KS18_ks18_frtn_MASK) - -#define CSS_CSS_KS18_ks18_fhwo_MASK (0x200U) -#define CSS_CSS_KS18_ks18_fhwo_SHIFT (9U) -/*! ks18_fhwo - Hardware Feature Output - */ -#define CSS_CSS_KS18_ks18_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_fhwo_SHIFT)) & CSS_CSS_KS18_ks18_fhwo_MASK) - -#define CSS_CSS_KS18_ks18_rsvd1_MASK (0x1C00U) -#define CSS_CSS_KS18_ks18_rsvd1_SHIFT (10U) -/*! ks18_rsvd1 - Reserved 1 - */ -#define CSS_CSS_KS18_ks18_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_rsvd1_SHIFT)) & CSS_CSS_KS18_ks18_rsvd1_MASK) - -#define CSS_CSS_KS18_ks18_ucmac_MASK (0x2000U) -#define CSS_CSS_KS18_ks18_ucmac_SHIFT (13U) -/*! ks18_ucmac - CMAC key - */ -#define CSS_CSS_KS18_ks18_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_ucmac_SHIFT)) & CSS_CSS_KS18_ks18_ucmac_MASK) - -#define CSS_CSS_KS18_ks18_uksk_MASK (0x4000U) -#define CSS_CSS_KS18_ks18_uksk_SHIFT (14U) -/*! ks18_uksk - KSK key - */ -#define CSS_CSS_KS18_ks18_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uksk_SHIFT)) & CSS_CSS_KS18_ks18_uksk_MASK) - -#define CSS_CSS_KS18_ks18_urtf_MASK (0x8000U) -#define CSS_CSS_KS18_ks18_urtf_SHIFT (15U) -/*! ks18_urtf - Real Time Fingerprint key - */ -#define CSS_CSS_KS18_ks18_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_urtf_SHIFT)) & CSS_CSS_KS18_ks18_urtf_MASK) - -#define CSS_CSS_KS18_ks18_uckdf_MASK (0x10000U) -#define CSS_CSS_KS18_ks18_uckdf_SHIFT (16U) -/*! ks18_uckdf - Derivation key for CKDF command - */ -#define CSS_CSS_KS18_ks18_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uckdf_SHIFT)) & CSS_CSS_KS18_ks18_uckdf_MASK) - -#define CSS_CSS_KS18_ks18_uhkdf_MASK (0x20000U) -#define CSS_CSS_KS18_ks18_uhkdf_SHIFT (17U) -/*! ks18_uhkdf - Derivation key for HKDF command - */ -#define CSS_CSS_KS18_ks18_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uhkdf_SHIFT)) & CSS_CSS_KS18_ks18_uhkdf_MASK) - -#define CSS_CSS_KS18_ks18_uecsg_MASK (0x40000U) -#define CSS_CSS_KS18_ks18_uecsg_SHIFT (18U) -/*! ks18_uecsg - Ecc signing key - */ -#define CSS_CSS_KS18_ks18_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uecsg_SHIFT)) & CSS_CSS_KS18_ks18_uecsg_MASK) - -#define CSS_CSS_KS18_ks18_uecdh_MASK (0x80000U) -#define CSS_CSS_KS18_ks18_uecdh_SHIFT (19U) -/*! ks18_uecdh - Ecc diffie hellman key - */ -#define CSS_CSS_KS18_ks18_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uecdh_SHIFT)) & CSS_CSS_KS18_ks18_uecdh_MASK) - -#define CSS_CSS_KS18_ks18_uaes_MASK (0x100000U) -#define CSS_CSS_KS18_ks18_uaes_SHIFT (20U) -/*! ks18_uaes - Aes key - */ -#define CSS_CSS_KS18_ks18_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uaes_SHIFT)) & CSS_CSS_KS18_ks18_uaes_MASK) - -#define CSS_CSS_KS18_ks18_uhmac_MASK (0x200000U) -#define CSS_CSS_KS18_ks18_uhmac_SHIFT (21U) -/*! ks18_uhmac - Hmac key - */ -#define CSS_CSS_KS18_ks18_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uhmac_SHIFT)) & CSS_CSS_KS18_ks18_uhmac_MASK) - -#define CSS_CSS_KS18_ks18_ukwk_MASK (0x400000U) -#define CSS_CSS_KS18_ks18_ukwk_SHIFT (22U) -/*! ks18_ukwk - Key wrapping key - */ -#define CSS_CSS_KS18_ks18_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_ukwk_SHIFT)) & CSS_CSS_KS18_ks18_ukwk_MASK) - -#define CSS_CSS_KS18_ks18_ukuok_MASK (0x800000U) -#define CSS_CSS_KS18_ks18_ukuok_SHIFT (23U) -/*! ks18_ukuok - Key unwrapping key - */ -#define CSS_CSS_KS18_ks18_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_ukuok_SHIFT)) & CSS_CSS_KS18_ks18_ukuok_MASK) - -#define CSS_CSS_KS18_ks18_utlspms_MASK (0x1000000U) -#define CSS_CSS_KS18_ks18_utlspms_SHIFT (24U) -/*! ks18_utlspms - TLS Pre Master Secret - */ -#define CSS_CSS_KS18_ks18_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_utlspms_SHIFT)) & CSS_CSS_KS18_ks18_utlspms_MASK) - -#define CSS_CSS_KS18_ks18_utlsms_MASK (0x2000000U) -#define CSS_CSS_KS18_ks18_utlsms_SHIFT (25U) -/*! ks18_utlsms - TLS Master Secret - */ -#define CSS_CSS_KS18_ks18_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_utlsms_SHIFT)) & CSS_CSS_KS18_ks18_utlsms_MASK) - -#define CSS_CSS_KS18_ks18_ukgsrc_MASK (0x4000000U) -#define CSS_CSS_KS18_ks18_ukgsrc_SHIFT (26U) -/*! ks18_ukgsrc - Supply KEYGEN source - */ -#define CSS_CSS_KS18_ks18_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_ukgsrc_SHIFT)) & CSS_CSS_KS18_ks18_ukgsrc_MASK) - -#define CSS_CSS_KS18_ks18_uhwo_MASK (0x8000000U) -#define CSS_CSS_KS18_ks18_uhwo_SHIFT (27U) -/*! ks18_uhwo - Hardware out key - */ -#define CSS_CSS_KS18_ks18_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uhwo_SHIFT)) & CSS_CSS_KS18_ks18_uhwo_MASK) - -#define CSS_CSS_KS18_ks18_uwrpok_MASK (0x10000000U) -#define CSS_CSS_KS18_ks18_uwrpok_SHIFT (28U) -/*! ks18_uwrpok - Ok to wrap key - */ -#define CSS_CSS_KS18_ks18_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uwrpok_SHIFT)) & CSS_CSS_KS18_ks18_uwrpok_MASK) - -#define CSS_CSS_KS18_ks18_uduk_MASK (0x20000000U) -#define CSS_CSS_KS18_ks18_uduk_SHIFT (29U) -/*! ks18_uduk - Device Unique Key - */ -#define CSS_CSS_KS18_ks18_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uduk_SHIFT)) & CSS_CSS_KS18_ks18_uduk_MASK) - -#define CSS_CSS_KS18_ks18_upprot_MASK (0xC0000000U) -#define CSS_CSS_KS18_ks18_upprot_SHIFT (30U) -/*! ks18_upprot - Priviledge level - */ -#define CSS_CSS_KS18_ks18_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_upprot_SHIFT)) & CSS_CSS_KS18_ks18_upprot_MASK) -/*! @} */ - -/*! @name CSS_KS19 - Status register */ -/*! @{ */ - -#define CSS_CSS_KS19_ks19_ksize_MASK (0x1U) -#define CSS_CSS_KS19_ks19_ksize_SHIFT (0U) -/*! ks19_ksize - Key size: 0-128, 1-256 - */ -#define CSS_CSS_KS19_ks19_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_ksize_SHIFT)) & CSS_CSS_KS19_ks19_ksize_MASK) - -#define CSS_CSS_KS19_ks19_rsvd0_MASK (0x1EU) -#define CSS_CSS_KS19_ks19_rsvd0_SHIFT (1U) -/*! ks19_rsvd0 - Reserved 0 - */ -#define CSS_CSS_KS19_ks19_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_rsvd0_SHIFT)) & CSS_CSS_KS19_ks19_rsvd0_MASK) - -#define CSS_CSS_KS19_ks19_kact_MASK (0x20U) -#define CSS_CSS_KS19_ks19_kact_SHIFT (5U) -/*! ks19_kact - Key is active - */ -#define CSS_CSS_KS19_ks19_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_kact_SHIFT)) & CSS_CSS_KS19_ks19_kact_MASK) - -#define CSS_CSS_KS19_ks19_kbase_MASK (0x40U) -#define CSS_CSS_KS19_ks19_kbase_SHIFT (6U) -/*! ks19_kbase - First slot in a multislot key - */ -#define CSS_CSS_KS19_ks19_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_kbase_SHIFT)) & CSS_CSS_KS19_ks19_kbase_MASK) - -#define CSS_CSS_KS19_ks19_fgp_MASK (0x80U) -#define CSS_CSS_KS19_ks19_fgp_SHIFT (7U) -/*! ks19_fgp - Hardware Feature General Purpose - */ -#define CSS_CSS_KS19_ks19_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_fgp_SHIFT)) & CSS_CSS_KS19_ks19_fgp_MASK) - -#define CSS_CSS_KS19_ks19_frtn_MASK (0x100U) -#define CSS_CSS_KS19_ks19_frtn_SHIFT (8U) -/*! ks19_frtn - Hardware Feature Retention - */ -#define CSS_CSS_KS19_ks19_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_frtn_SHIFT)) & CSS_CSS_KS19_ks19_frtn_MASK) - -#define CSS_CSS_KS19_ks19_fhwo_MASK (0x200U) -#define CSS_CSS_KS19_ks19_fhwo_SHIFT (9U) -/*! ks19_fhwo - Hardware Feature Output - */ -#define CSS_CSS_KS19_ks19_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_fhwo_SHIFT)) & CSS_CSS_KS19_ks19_fhwo_MASK) - -#define CSS_CSS_KS19_ks19_rsvd1_MASK (0x1C00U) -#define CSS_CSS_KS19_ks19_rsvd1_SHIFT (10U) -/*! ks19_rsvd1 - Reserved 1 - */ -#define CSS_CSS_KS19_ks19_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_rsvd1_SHIFT)) & CSS_CSS_KS19_ks19_rsvd1_MASK) - -#define CSS_CSS_KS19_ks19_ucmac_MASK (0x2000U) -#define CSS_CSS_KS19_ks19_ucmac_SHIFT (13U) -/*! ks19_ucmac - CMAC key - */ -#define CSS_CSS_KS19_ks19_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_ucmac_SHIFT)) & CSS_CSS_KS19_ks19_ucmac_MASK) - -#define CSS_CSS_KS19_ks19_uksk_MASK (0x4000U) -#define CSS_CSS_KS19_ks19_uksk_SHIFT (14U) -/*! ks19_uksk - KSK key - */ -#define CSS_CSS_KS19_ks19_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uksk_SHIFT)) & CSS_CSS_KS19_ks19_uksk_MASK) - -#define CSS_CSS_KS19_ks19_urtf_MASK (0x8000U) -#define CSS_CSS_KS19_ks19_urtf_SHIFT (15U) -/*! ks19_urtf - Real Time Fingerprint key - */ -#define CSS_CSS_KS19_ks19_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_urtf_SHIFT)) & CSS_CSS_KS19_ks19_urtf_MASK) - -#define CSS_CSS_KS19_ks19_uckdf_MASK (0x10000U) -#define CSS_CSS_KS19_ks19_uckdf_SHIFT (16U) -/*! ks19_uckdf - Derivation key for CKDF command - */ -#define CSS_CSS_KS19_ks19_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uckdf_SHIFT)) & CSS_CSS_KS19_ks19_uckdf_MASK) - -#define CSS_CSS_KS19_ks19_uhkdf_MASK (0x20000U) -#define CSS_CSS_KS19_ks19_uhkdf_SHIFT (17U) -/*! ks19_uhkdf - Derivation key for HKDF command - */ -#define CSS_CSS_KS19_ks19_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uhkdf_SHIFT)) & CSS_CSS_KS19_ks19_uhkdf_MASK) - -#define CSS_CSS_KS19_ks19_uecsg_MASK (0x40000U) -#define CSS_CSS_KS19_ks19_uecsg_SHIFT (18U) -/*! ks19_uecsg - Ecc signing key - */ -#define CSS_CSS_KS19_ks19_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uecsg_SHIFT)) & CSS_CSS_KS19_ks19_uecsg_MASK) - -#define CSS_CSS_KS19_ks19_uecdh_MASK (0x80000U) -#define CSS_CSS_KS19_ks19_uecdh_SHIFT (19U) -/*! ks19_uecdh - Ecc diffie hellman key - */ -#define CSS_CSS_KS19_ks19_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uecdh_SHIFT)) & CSS_CSS_KS19_ks19_uecdh_MASK) - -#define CSS_CSS_KS19_ks19_uaes_MASK (0x100000U) -#define CSS_CSS_KS19_ks19_uaes_SHIFT (20U) -/*! ks19_uaes - Aes key - */ -#define CSS_CSS_KS19_ks19_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uaes_SHIFT)) & CSS_CSS_KS19_ks19_uaes_MASK) - -#define CSS_CSS_KS19_ks19_uhmac_MASK (0x200000U) -#define CSS_CSS_KS19_ks19_uhmac_SHIFT (21U) -/*! ks19_uhmac - Hmac key - */ -#define CSS_CSS_KS19_ks19_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uhmac_SHIFT)) & CSS_CSS_KS19_ks19_uhmac_MASK) - -#define CSS_CSS_KS19_ks19_ukwk_MASK (0x400000U) -#define CSS_CSS_KS19_ks19_ukwk_SHIFT (22U) -/*! ks19_ukwk - Key wrapping key - */ -#define CSS_CSS_KS19_ks19_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_ukwk_SHIFT)) & CSS_CSS_KS19_ks19_ukwk_MASK) - -#define CSS_CSS_KS19_ks19_ukuok_MASK (0x800000U) -#define CSS_CSS_KS19_ks19_ukuok_SHIFT (23U) -/*! ks19_ukuok - Key unwrapping key - */ -#define CSS_CSS_KS19_ks19_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_ukuok_SHIFT)) & CSS_CSS_KS19_ks19_ukuok_MASK) - -#define CSS_CSS_KS19_ks19_utlspms_MASK (0x1000000U) -#define CSS_CSS_KS19_ks19_utlspms_SHIFT (24U) -/*! ks19_utlspms - TLS Pre Master Secret - */ -#define CSS_CSS_KS19_ks19_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_utlspms_SHIFT)) & CSS_CSS_KS19_ks19_utlspms_MASK) - -#define CSS_CSS_KS19_ks19_utlsms_MASK (0x2000000U) -#define CSS_CSS_KS19_ks19_utlsms_SHIFT (25U) -/*! ks19_utlsms - TLS Master Secret - */ -#define CSS_CSS_KS19_ks19_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_utlsms_SHIFT)) & CSS_CSS_KS19_ks19_utlsms_MASK) - -#define CSS_CSS_KS19_ks19_ukgsrc_MASK (0x4000000U) -#define CSS_CSS_KS19_ks19_ukgsrc_SHIFT (26U) -/*! ks19_ukgsrc - Supply KEYGEN source - */ -#define CSS_CSS_KS19_ks19_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_ukgsrc_SHIFT)) & CSS_CSS_KS19_ks19_ukgsrc_MASK) - -#define CSS_CSS_KS19_ks19_uhwo_MASK (0x8000000U) -#define CSS_CSS_KS19_ks19_uhwo_SHIFT (27U) -/*! ks19_uhwo - Hardware out key - */ -#define CSS_CSS_KS19_ks19_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uhwo_SHIFT)) & CSS_CSS_KS19_ks19_uhwo_MASK) - -#define CSS_CSS_KS19_ks19_uwrpok_MASK (0x10000000U) -#define CSS_CSS_KS19_ks19_uwrpok_SHIFT (28U) -/*! ks19_uwrpok - Ok to wrap key - */ -#define CSS_CSS_KS19_ks19_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uwrpok_SHIFT)) & CSS_CSS_KS19_ks19_uwrpok_MASK) - -#define CSS_CSS_KS19_ks19_uduk_MASK (0x20000000U) -#define CSS_CSS_KS19_ks19_uduk_SHIFT (29U) -/*! ks19_uduk - Device Unique Key - */ -#define CSS_CSS_KS19_ks19_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uduk_SHIFT)) & CSS_CSS_KS19_ks19_uduk_MASK) - -#define CSS_CSS_KS19_ks19_upprot_MASK (0xC0000000U) -#define CSS_CSS_KS19_ks19_upprot_SHIFT (30U) -/*! ks19_upprot - Priviledge level - */ -#define CSS_CSS_KS19_ks19_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_upprot_SHIFT)) & CSS_CSS_KS19_ks19_upprot_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CSS_Register_Masks */ - - -/* CSS - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CSS base address */ - #define CSS_BASE (0x50030000u) - /** Peripheral CSS base address */ - #define CSS_BASE_NS (0x40030000u) - /** Peripheral CSS base pointer */ - #define CSS ((CSS_Type *)CSS_BASE) - /** Peripheral CSS base pointer */ - #define CSS_NS ((CSS_Type *)CSS_BASE_NS) - /** Array initializer of CSS peripheral base addresses */ - #define CSS_BASE_ADDRS { CSS_BASE } - /** Array initializer of CSS peripheral base pointers */ - #define CSS_BASE_PTRS { CSS } - /** Array initializer of CSS peripheral base addresses */ - #define CSS_BASE_ADDRS_NS { CSS_BASE_NS } - /** Array initializer of CSS peripheral base pointers */ - #define CSS_BASE_PTRS_NS { CSS_NS } -#else - /** Peripheral CSS base address */ - #define CSS_BASE (0x40030000u) - /** Peripheral CSS base pointer */ - #define CSS ((CSS_Type *)CSS_BASE) - /** Array initializer of CSS peripheral base addresses */ - #define CSS_BASE_ADDRS { CSS_BASE } - /** Array initializer of CSS peripheral base pointers */ - #define CSS_BASE_PTRS { CSS } -#endif - -/*! - * @} - */ /* end of group CSS_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CTIMER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer - * @{ - */ - -/** CTIMER - Register Layout Typedef */ -typedef struct { - __IO uint32_t IR; /**< Interrupt Register, offset: 0x0 */ - __IO uint32_t TCR; /**< Timer Control Register, offset: 0x4 */ - __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ - __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ - __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ - __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ - __IO uint32_t MR[4]; /**< Match Register, array offset: 0x18, array step: 0x4 */ - __IO uint32_t CCR; /**< Capture Control Register, offset: 0x28 */ - __I uint32_t CR[4]; /**< Capture Register, array offset: 0x2C, array step: 0x4 */ - __IO uint32_t EMR; /**< External Match Register, offset: 0x3C */ - uint8_t RESERVED_0[48]; - __IO uint32_t CTCR; /**< Count Control Register, offset: 0x70 */ - __IO uint32_t PWMC; /**< PWM Control Register, offset: 0x74 */ - __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ -} CTIMER_Type; - -/* ---------------------------------------------------------------------------- - -- CTIMER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Register_Masks CTIMER Register Masks - * @{ - */ - -/*! @name IR - Interrupt Register */ -/*! @{ */ - -#define CTIMER_IR_MR0INT_MASK (0x1U) -#define CTIMER_IR_MR0INT_SHIFT (0U) -/*! MR0INT - Interrupt flag for match channel 0 - */ -#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) - -#define CTIMER_IR_MR1INT_MASK (0x2U) -#define CTIMER_IR_MR1INT_SHIFT (1U) -/*! MR1INT - Interrupt flag for match channel 1 - */ -#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) - -#define CTIMER_IR_MR2INT_MASK (0x4U) -#define CTIMER_IR_MR2INT_SHIFT (2U) -/*! MR2INT - Interrupt flag for match channel 2 - */ -#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) - -#define CTIMER_IR_MR3INT_MASK (0x8U) -#define CTIMER_IR_MR3INT_SHIFT (3U) -/*! MR3INT - Interrupt flag for match channel 3 - */ -#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) - -#define CTIMER_IR_CR0INT_MASK (0x10U) -#define CTIMER_IR_CR0INT_SHIFT (4U) -/*! CR0INT - Interrupt flag for capture channel 0 event - */ -#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) - -#define CTIMER_IR_CR1INT_MASK (0x20U) -#define CTIMER_IR_CR1INT_SHIFT (5U) -/*! CR1INT - Interrupt flag for capture channel 1 event - */ -#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) - -#define CTIMER_IR_CR2INT_MASK (0x40U) -#define CTIMER_IR_CR2INT_SHIFT (6U) -/*! CR2INT - Interrupt flag for capture channel 2 event - */ -#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) - -#define CTIMER_IR_CR3INT_MASK (0x80U) -#define CTIMER_IR_CR3INT_SHIFT (7U) -/*! CR3INT - Interrupt flag for capture channel 3 event - */ -#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) -/*! @} */ - -/*! @name TCR - Timer Control Register */ -/*! @{ */ - -#define CTIMER_TCR_CEN_MASK (0x1U) -#define CTIMER_TCR_CEN_SHIFT (0U) -/*! CEN - Counter enable - * 0b0..Disabled. The counters are disabled - * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. When the timer is enabled by an external - * trigger or globally enabled by the external global start enable register, the CEN bit will automatically be - * set to 1 - */ -#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) - -#define CTIMER_TCR_CRST_MASK (0x2U) -#define CTIMER_TCR_CRST_SHIFT (1U) -/*! CRST - Counter reset - * 0b0..Disabled. Do nothing - * 0b1..Enabled - */ -#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) - -#define CTIMER_TCR_AGCEN_MASK (0x10U) -#define CTIMER_TCR_AGCEN_SHIFT (4U) -/*! AGCEN - Allow Global Count Enable - * 0b0..Not allowed - * 0b1..Allow input global_enable=1 action to take effect - */ -#define CTIMER_TCR_AGCEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_AGCEN_SHIFT)) & CTIMER_TCR_AGCEN_MASK) - -#define CTIMER_TCR_ATCEN_MASK (0x20U) -#define CTIMER_TCR_ATCEN_SHIFT (5U) -/*! ATCEN - Allow Trigger Count Enable - * 0b0..Not allowed - * 0b1..Allow input trigger_enable=1 action to take effect - */ -#define CTIMER_TCR_ATCEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_ATCEN_SHIFT)) & CTIMER_TCR_ATCEN_MASK) -/*! @} */ - -/*! @name TC - Timer Counter */ -/*! @{ */ - -#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_TC_TCVAL_SHIFT (0U) -/*! TCVAL - Timer counter value - */ -#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) -/*! @} */ - -/*! @name PR - Prescale Register */ -/*! @{ */ - -#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PR_PRVAL_SHIFT (0U) -/*! PRVAL - Prescale reload value - */ -#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) -/*! @} */ - -/*! @name PC - Prescale Counter */ -/*! @{ */ - -#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PC_PCVAL_SHIFT (0U) -/*! PCVAL - Prescale counter value - */ -#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) -/*! @} */ - -/*! @name MCR - Match Control Register */ -/*! @{ */ - -#define CTIMER_MCR_MR0I_MASK (0x1U) -#define CTIMER_MCR_MR0I_SHIFT (0U) -/*! MR0I - Interrupt on MR0 - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) - -#define CTIMER_MCR_MR0R_MASK (0x2U) -#define CTIMER_MCR_MR0R_SHIFT (1U) -/*! MR0R - Reset on MR0 - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) - -#define CTIMER_MCR_MR0S_MASK (0x4U) -#define CTIMER_MCR_MR0S_SHIFT (2U) -/*! MR0S - Stop on MR0 - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) - -#define CTIMER_MCR_MR1I_MASK (0x8U) -#define CTIMER_MCR_MR1I_SHIFT (3U) -/*! MR1I - Interrupt on MR1 - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) - -#define CTIMER_MCR_MR1R_MASK (0x10U) -#define CTIMER_MCR_MR1R_SHIFT (4U) -/*! MR1R - Reset on MR1 - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) - -#define CTIMER_MCR_MR1S_MASK (0x20U) -#define CTIMER_MCR_MR1S_SHIFT (5U) -/*! MR1S - Stop on MR1 - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) - -#define CTIMER_MCR_MR2I_MASK (0x40U) -#define CTIMER_MCR_MR2I_SHIFT (6U) -/*! MR2I - Interrupt on MR2 - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) - -#define CTIMER_MCR_MR2R_MASK (0x80U) -#define CTIMER_MCR_MR2R_SHIFT (7U) -/*! MR2R - Reset on MR2 - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) - -#define CTIMER_MCR_MR2S_MASK (0x100U) -#define CTIMER_MCR_MR2S_SHIFT (8U) -/*! MR2S - Stop on MR2 - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) - -#define CTIMER_MCR_MR3I_MASK (0x200U) -#define CTIMER_MCR_MR3I_SHIFT (9U) -/*! MR3I - Interrupt on MR3 - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) - -#define CTIMER_MCR_MR3R_MASK (0x400U) -#define CTIMER_MCR_MR3R_SHIFT (10U) -/*! MR3R - Reset on MR3 - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) - -#define CTIMER_MCR_MR3S_MASK (0x800U) -#define CTIMER_MCR_MR3S_SHIFT (11U) -/*! MR3S - Stop on MR3 - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) - -#define CTIMER_MCR_MR0RL_MASK (0x1000000U) -#define CTIMER_MCR_MR0RL_SHIFT (24U) -/*! MR0RL - Reload MR0 - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) - -#define CTIMER_MCR_MR1RL_MASK (0x2000000U) -#define CTIMER_MCR_MR1RL_SHIFT (25U) -/*! MR1RL - Reload MR1 - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) - -#define CTIMER_MCR_MR2RL_MASK (0x4000000U) -#define CTIMER_MCR_MR2RL_SHIFT (26U) -/*! MR2RL - Reload MR2 - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) - -#define CTIMER_MCR_MR3RL_MASK (0x8000000U) -#define CTIMER_MCR_MR3RL_SHIFT (27U) -/*! MR3RL - Reload MR3 - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) -/*! @} */ - -/*! @name MR - Match Register */ -/*! @{ */ - -#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) -#define CTIMER_MR_MATCH_SHIFT (0U) -/*! MATCH - Timer counter match value - */ -#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) -/*! @} */ - -/* The count of CTIMER_MR */ -#define CTIMER_MR_COUNT (4U) - -/*! @name CCR - Capture Control Register */ -/*! @{ */ - -#define CTIMER_CCR_CAP0RE_MASK (0x1U) -#define CTIMER_CCR_CAP0RE_SHIFT (0U) -/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) - -#define CTIMER_CCR_CAP0FE_MASK (0x2U) -#define CTIMER_CCR_CAP0FE_SHIFT (1U) -/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) - -#define CTIMER_CCR_CAP0I_MASK (0x4U) -#define CTIMER_CCR_CAP0I_SHIFT (2U) -/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) - -#define CTIMER_CCR_CAP1RE_MASK (0x8U) -#define CTIMER_CCR_CAP1RE_SHIFT (3U) -/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) - -#define CTIMER_CCR_CAP1FE_MASK (0x10U) -#define CTIMER_CCR_CAP1FE_SHIFT (4U) -/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) - -#define CTIMER_CCR_CAP1I_MASK (0x20U) -#define CTIMER_CCR_CAP1I_SHIFT (5U) -/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) - -#define CTIMER_CCR_CAP2RE_MASK (0x40U) -#define CTIMER_CCR_CAP2RE_SHIFT (6U) -/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) - -#define CTIMER_CCR_CAP2FE_MASK (0x80U) -#define CTIMER_CCR_CAP2FE_SHIFT (7U) -/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) - -#define CTIMER_CCR_CAP2I_MASK (0x100U) -#define CTIMER_CCR_CAP2I_SHIFT (8U) -/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) - -#define CTIMER_CCR_CAP3RE_MASK (0x200U) -#define CTIMER_CCR_CAP3RE_SHIFT (9U) -/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) - -#define CTIMER_CCR_CAP3FE_MASK (0x400U) -#define CTIMER_CCR_CAP3FE_SHIFT (10U) -/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) - -#define CTIMER_CCR_CAP3I_MASK (0x800U) -#define CTIMER_CCR_CAP3I_SHIFT (11U) -/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt - * 0b0..Disabled - * 0b1..Enabled - */ -#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) -/*! @} */ - -/*! @name CR - Capture Register */ -/*! @{ */ - -#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) -#define CTIMER_CR_CAP_SHIFT (0U) -/*! CAP - Timer counter capture value - */ -#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) -/*! @} */ - -/* The count of CTIMER_CR */ -#define CTIMER_CR_COUNT (4U) - -/*! @name EMR - External Match Register */ -/*! @{ */ - -#define CTIMER_EMR_EM0_MASK (0x1U) -#define CTIMER_EMR_EM0_SHIFT (0U) -/*! EM0 - External Match 0 - */ -#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) - -#define CTIMER_EMR_EM1_MASK (0x2U) -#define CTIMER_EMR_EM1_SHIFT (1U) -/*! EM1 - External Match 1 - */ -#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) - -#define CTIMER_EMR_EM2_MASK (0x4U) -#define CTIMER_EMR_EM2_SHIFT (2U) -/*! EM2 - External Match 2 - */ -#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) - -#define CTIMER_EMR_EM3_MASK (0x8U) -#define CTIMER_EMR_EM3_SHIFT (3U) -/*! EM3 - External Match 3 - */ -#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) - -#define CTIMER_EMR_EMC0_MASK (0x30U) -#define CTIMER_EMR_EMC0_SHIFT (4U) -/*! EMC0 - External Match Control 0 - * 0b00..Do Nothing - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out) - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out) - * 0b11..Toggle. Toggle the corresponding External Match bit/output - */ -#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) - -#define CTIMER_EMR_EMC1_MASK (0xC0U) -#define CTIMER_EMR_EMC1_SHIFT (6U) -/*! EMC1 - External Match Control 1 - * 0b00..Do Nothing - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out) - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out) - * 0b11..Toggle. Toggle the corresponding External Match bit/output - */ -#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) - -#define CTIMER_EMR_EMC2_MASK (0x300U) -#define CTIMER_EMR_EMC2_SHIFT (8U) -/*! EMC2 - External Match Control 2 - * 0b00..Do Nothing - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out) - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out) - * 0b11..Toggle. Toggle the corresponding External Match bit/output - */ -#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) - -#define CTIMER_EMR_EMC3_MASK (0xC00U) -#define CTIMER_EMR_EMC3_SHIFT (10U) -/*! EMC3 - External Match Control 3 - * 0b00..Do Nothing - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out) - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out) - * 0b11..Toggle. Toggle the corresponding External Match bit/output - */ -#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) -/*! @} */ - -/*! @name CTCR - Count Control Register */ -/*! @{ */ - -#define CTIMER_CTCR_CTMODE_MASK (0x3U) -#define CTIMER_CTCR_CTMODE_SHIFT (0U) -/*! CTMODE - The Count Control Register (CTCR) is used to select between Timer and Counter mode, and - * in Counter mode to select the pin and edge(s) for counting. - * 0b00..Timer Mode - * 0b01..Counter Mode rising edge - * 0b10..Counter Mode falling edge - * 0b11..Counter Mode dual edge - */ -#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) - -#define CTIMER_CTCR_CINSEL_MASK (0xCU) -#define CTIMER_CTCR_CINSEL_SHIFT (2U) -/*! CINSEL - Count Input Select - * 0b00..Channel 0. CAPn[0] for CTIMERn - * 0b01..Channel 1. CAPn[1] for CTIMERn - * 0b10..Channel 2. CAPn[2] for CTIMERn - * 0b11..Channel 3. CAPn[3] for CTIMERn - */ -#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) - -#define CTIMER_CTCR_ENCC_MASK (0x10U) -#define CTIMER_CTCR_ENCC_SHIFT (4U) -#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) - -#define CTIMER_CTCR_SELCC_MASK (0xE0U) -#define CTIMER_CTCR_SELCC_SHIFT (5U) -/*! SELCC - Edge select - * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set) - * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set) - * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set) - * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set) - * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set) - * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set) - */ -#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) -/*! @} */ - -/*! @name PWMC - PWM Control Register */ -/*! @{ */ - -#define CTIMER_PWMC_PWMEN0_MASK (0x1U) -#define CTIMER_PWMC_PWMEN0_SHIFT (0U) -/*! PWMEN0 - PWM mode enable for channel 0 - * 0b0..Match. CTIMERn_MAT0 is controlled by EM0 - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0 - */ -#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) - -#define CTIMER_PWMC_PWMEN1_MASK (0x2U) -#define CTIMER_PWMC_PWMEN1_SHIFT (1U) -/*! PWMEN1 - PWM mode enable for channel 1 - * 0b0..Match. CTIMERn_MAT01 is controlled by EM1 - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1 - */ -#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) - -#define CTIMER_PWMC_PWMEN2_MASK (0x4U) -#define CTIMER_PWMC_PWMEN2_SHIFT (2U) -/*! PWMEN2 - PWM mode enable for channel 2 - * 0b0..Match. CTIMERn_MAT2 is controlled by EM2 - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2 - */ -#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) - -#define CTIMER_PWMC_PWMEN3_MASK (0x8U) -#define CTIMER_PWMC_PWMEN3_SHIFT (3U) -/*! PWMEN3 - PWM mode enable for channel 3. It is recommended to use match channel 3 to set the PWM cycle - * 0b0..Match. CTIMERn_MAT3 is controlled by EM3 - * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3 - */ -#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) -/*! @} */ - -/*! @name MSR - Match Shadow Register */ -/*! @{ */ - -#define CTIMER_MSR_MATCH_SHADOW_MASK (0xFFFFFFFFU) -#define CTIMER_MSR_MATCH_SHADOW_SHIFT (0U) -/*! MATCH_SHADOW - Timer counter match shadow value - */ -#define CTIMER_MSR_MATCH_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_SHADOW_SHIFT)) & CTIMER_MSR_MATCH_SHADOW_MASK) -/*! @} */ - -/* The count of CTIMER_MSR */ -#define CTIMER_MSR_COUNT (4U) - - -/*! - * @} - */ /* end of group CTIMER_Register_Masks */ - - -/* CTIMER - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE (0x50008000u) - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE_NS (0x40008000u) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE (0x50009000u) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE_NS (0x40009000u) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE (0x50028000u) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE_NS (0x40028000u) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE (0x50029000u) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE_NS (0x40029000u) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE (0x5002A000u) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE_NS (0x4002A000u) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } -#else - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE (0x40008000u) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE (0x40009000u) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE (0x40028000u) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE (0x40029000u) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE (0x4002A000u) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } -#endif -/** Interrupt vectors for the CTIMER peripheral type */ -#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } - -/*! - * @} - */ /* end of group CTIMER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DEBUGGER_MAILBOX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DEBUGGER_MAILBOX_Peripheral_Access_Layer DEBUGGER_MAILBOX Peripheral Access Layer - * @{ - */ - -/** DEBUGGER_MAILBOX - Register Layout Typedef */ -typedef struct { - __IO uint32_t CSW; /**< Command and status word, offset: 0x0 */ - __IO uint32_t REQUEST; /**< Request Value, offset: 0x4 */ - __IO uint32_t RETURN; /**< Return Value, offset: 0x8 */ - uint8_t RESERVED_0[240]; - __I uint32_t ID; /**< Identification, offset: 0xFC */ -} DEBUGGER_MAILBOX_Type; - -/* ---------------------------------------------------------------------------- - -- DEBUGGER_MAILBOX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DEBUGGER_MAILBOX_Register_Masks DEBUGGER_MAILBOX Register Masks - * @{ - */ - -/*! @name CSW - Command and status word */ -/*! @{ */ - -#define DEBUGGER_MAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) -#define DEBUGGER_MAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) -/*! RESYNCH_REQ - Re-synchronization Request - * 0b0..No Request - * 0b1..Request for re-synchronization - */ -#define DEBUGGER_MAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DEBUGGER_MAILBOX_CSW_RESYNCH_REQ_MASK) - -#define DEBUGGER_MAILBOX_CSW_REQ_PENDING_MASK (0x2U) -#define DEBUGGER_MAILBOX_CSW_REQ_PENDING_SHIFT (1U) -/*! REQ_PENDING - Request Pending - * 0b0..No Request Pending - * 0b1..Request for Re-synchronization Pending - */ -#define DEBUGGER_MAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_REQ_PENDING_SHIFT)) & DEBUGGER_MAILBOX_CSW_REQ_PENDING_MASK) - -#define DEBUGGER_MAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) -#define DEBUGGER_MAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) -/*! DBG_OR_ERR - Debug Overrun Error - * 0b0..No Debug Overrun error - * 0b1..Debug Overrun Error. A debug overrun occurred. - */ -#define DEBUGGER_MAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DEBUGGER_MAILBOX_CSW_DBG_OR_ERR_MASK) - -#define DEBUGGER_MAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) -#define DEBUGGER_MAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) -/*! AHB_OR_ERR - AHB Overrun Error - * 0b0..No AHB Overrun Error - * 0b1..AHB Overrun Error. An AHB overrun occurred. - */ -#define DEBUGGER_MAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DEBUGGER_MAILBOX_CSW_AHB_OR_ERR_MASK) - -#define DEBUGGER_MAILBOX_CSW_SOFT_RESET_MASK (0x10U) -#define DEBUGGER_MAILBOX_CSW_SOFT_RESET_SHIFT (4U) -/*! SOFT_RESET - Soft Reset - */ -#define DEBUGGER_MAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_SOFT_RESET_SHIFT)) & DEBUGGER_MAILBOX_CSW_SOFT_RESET_MASK) - -#define DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) -#define DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) -/*! CHIP_RESET_REQ - Chip Reset Request - */ -#define DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ_MASK) -/*! @} */ - -/*! @name REQUEST - Request Value */ -/*! @{ */ - -#define DEBUGGER_MAILBOX_REQUEST_REQUEST_MASK (0xFFFFFFFFU) -#define DEBUGGER_MAILBOX_REQUEST_REQUEST_SHIFT (0U) -/*! REQUEST - Request Value - */ -#define DEBUGGER_MAILBOX_REQUEST_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_REQUEST_REQUEST_SHIFT)) & DEBUGGER_MAILBOX_REQUEST_REQUEST_MASK) -/*! @} */ - -/*! @name RETURN - Return Value */ -/*! @{ */ - -#define DEBUGGER_MAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) -#define DEBUGGER_MAILBOX_RETURN_RET_SHIFT (0U) -/*! RET - Return Value - */ -#define DEBUGGER_MAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_RETURN_RET_SHIFT)) & DEBUGGER_MAILBOX_RETURN_RET_MASK) -/*! @} */ - -/*! @name ID - Identification */ -/*! @{ */ - -#define DEBUGGER_MAILBOX_ID_ID_MASK (0xFFFFFFFFU) -#define DEBUGGER_MAILBOX_ID_ID_SHIFT (0U) -/*! ID - Identification Value - */ -#define DEBUGGER_MAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_ID_ID_SHIFT)) & DEBUGGER_MAILBOX_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group DEBUGGER_MAILBOX_Register_Masks */ - - -/* DEBUGGER_MAILBOX - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral DEBUGGER_MAILBOX0 base address */ - #define DEBUGGER_MAILBOX0_BASE (0x5009C000u) - /** Peripheral DEBUGGER_MAILBOX0 base address */ - #define DEBUGGER_MAILBOX0_BASE_NS (0x4009C000u) - /** Peripheral DEBUGGER_MAILBOX0 base pointer */ - #define DEBUGGER_MAILBOX0 ((DEBUGGER_MAILBOX_Type *)DEBUGGER_MAILBOX0_BASE) - /** Peripheral DEBUGGER_MAILBOX0 base pointer */ - #define DEBUGGER_MAILBOX0_NS ((DEBUGGER_MAILBOX_Type *)DEBUGGER_MAILBOX0_BASE_NS) - /** Array initializer of DEBUGGER_MAILBOX peripheral base addresses */ - #define DEBUGGER_MAILBOX_BASE_ADDRS { DEBUGGER_MAILBOX0_BASE } - /** Array initializer of DEBUGGER_MAILBOX peripheral base pointers */ - #define DEBUGGER_MAILBOX_BASE_PTRS { DEBUGGER_MAILBOX0 } - /** Array initializer of DEBUGGER_MAILBOX peripheral base addresses */ - #define DEBUGGER_MAILBOX_BASE_ADDRS_NS { DEBUGGER_MAILBOX0_BASE_NS } - /** Array initializer of DEBUGGER_MAILBOX peripheral base pointers */ - #define DEBUGGER_MAILBOX_BASE_PTRS_NS { DEBUGGER_MAILBOX0_NS } -#else - /** Peripheral DEBUGGER_MAILBOX0 base address */ - #define DEBUGGER_MAILBOX0_BASE (0x4009C000u) - /** Peripheral DEBUGGER_MAILBOX0 base pointer */ - #define DEBUGGER_MAILBOX0 ((DEBUGGER_MAILBOX_Type *)DEBUGGER_MAILBOX0_BASE) - /** Array initializer of DEBUGGER_MAILBOX peripheral base addresses */ - #define DEBUGGER_MAILBOX_BASE_ADDRS { DEBUGGER_MAILBOX0_BASE } - /** Array initializer of DEBUGGER_MAILBOX peripheral base pointers */ - #define DEBUGGER_MAILBOX_BASE_PTRS { DEBUGGER_MAILBOX0 } -#endif - -/*! - * @} - */ /* end of group DEBUGGER_MAILBOX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer - * @{ - */ - -/** DMA - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< DMA control, offset: 0x0 */ - __I uint32_t INTSTAT; /**< Interrupt status, offset: 0x4 */ - __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table, offset: 0x8 */ - uint8_t RESERVED_0[20]; - struct { /* offset: 0x20, array step: 0x60 */ - __IO uint32_t ENABLESET; /**< Channel Enable read and set for all DMA channels, array offset: 0x20, array step: 0x60 */ - __IO uint32_t ENABLESET1; /**< Channel Enable read and set for all DMA channels, array offset: 0x24, array step: 0x60 */ - __IO uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels, array offset: 0x28, array step: 0x60 */ - __IO uint32_t ENABLECLR1; /**< Channel Enable Clear for all DMA channels, array offset: 0x2C, array step: 0x60 */ - __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels, array offset: 0x30, array step: 0x60 */ - __I uint32_t ACTIVE1; /**< Channel Active status for all DMA channels, array offset: 0x34, array step: 0x60 */ - __I uint32_t BUSY; /**< Channel Busy status for all DMA channels, array offset: 0x38, array step: 0x60 */ - __I uint32_t BUSY1; /**< Channel Busy status for all DMA channels, array offset: 0x3C, array step: 0x60 */ - __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels, array offset: 0x40, array step: 0x60 */ - __IO uint32_t ERRINT1; /**< Error Interrupt status for all DMA channels, array offset: 0x44, array step: 0x60 */ - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels, array offset: 0x48, array step: 0x60 */ - __IO uint32_t INTENSET1; /**< Interrupt Enable read and Set for all DMA channels, array offset: 0x4C, array step: 0x60 */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels, array offset: 0x50, array step: 0x60 */ - __O uint32_t INTENCLR1; /**< Interrupt Enable Clear for all DMA channels, array offset: 0x54, array step: 0x60 */ - __IO uint32_t INTA; /**< Interrupt A status for all DMA channels, array offset: 0x58, array step: 0x60 */ - __IO uint32_t INTA1; /**< Interrupt A status for all DMA channels, array offset: 0x5C, array step: 0x60 */ - __IO uint32_t INTB; /**< Interrupt B status for all DMA channels, array offset: 0x60, array step: 0x60 */ - __IO uint32_t INTB1; /**< Interrupt B status for all DMA channels, array offset: 0x64, array step: 0x60 */ - __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels, array offset: 0x68, array step: 0x60 */ - __O uint32_t SETVALID1; /**< Set ValidPending control bits for all DMA channels, array offset: 0x6C, array step: 0x60 */ - __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels, array offset: 0x70, array step: 0x60 */ - __O uint32_t SETTRIG1; /**< Set Trigger control bits for all DMA channels, array offset: 0x74, array step: 0x60 */ - __O uint32_t ABORT; /**< Channel Abort control for all DMA channels, array offset: 0x78, array step: 0x60 */ - __O uint32_t ABORT1; /**< Channel Abort control for all DMA channels, array offset: 0x7C, array step: 0x60 */ - } COMMON[1]; - uint8_t RESERVED_1[896]; - struct { /* offset: 0x400, array step: 0x10 */ - __IO uint32_t CFG; /**< Configuration register for DMA channel, array offset: 0x400, array step: 0x10 */ - __I uint32_t CTLSTAT; /**< Control and status register for DMA channel, array offset: 0x404, array step: 0x10 */ - __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel, array offset: 0x408, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } CHANNEL[52]; -} DMA_Type; - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/*! @name CTRL - DMA control */ -/*! @{ */ - -#define DMA_CTRL_ENABLE_MASK (0x1U) -#define DMA_CTRL_ENABLE_SHIFT (0U) -/*! ENABLE - DMA controller master enable. - * 0b0..DMA controller is disabled. - * 0b1..Enabled. - */ -#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status */ -/*! @{ */ - -#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) -#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) -/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. - * 0b0..No enabled interrupts are pending. - * 0b1..At least one enabled interrupt is pending. - */ -#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) - -#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) -#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) -/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. - * 0b0..No error interrupts are pending. - * 0b1..At least one error interrupt is pending. - */ -#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) -/*! @} */ - -/*! @name SRAMBASE - SRAM address of the channel configuration table */ -/*! @{ */ - -#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFF00U) /* Merged from fields with different position or width, of widths (22, 24), largest definition used */ -#define DMA_SRAMBASE_OFFSET_SHIFT (8U) -/*! OFFSET - Offset - */ -#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) /* Merged from fields with different position or width, of widths (22, 24), largest definition used */ -/*! @} */ - -/*! @name COMMON_ENABLESET - Channel Enable read and set for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_ENABLESET_ENABLE0_MASK (0x1U) -#define DMA_COMMON_ENABLESET_ENABLE0_SHIFT (0U) -/*! ENABLE0 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE0_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE0_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE1_MASK (0x2U) -#define DMA_COMMON_ENABLESET_ENABLE1_SHIFT (1U) -/*! ENABLE1 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE1_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE1_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE2_MASK (0x4U) -#define DMA_COMMON_ENABLESET_ENABLE2_SHIFT (2U) -/*! ENABLE2 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE2_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE2_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE3_MASK (0x8U) -#define DMA_COMMON_ENABLESET_ENABLE3_SHIFT (3U) -/*! ENABLE3 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE3_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE3_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE4_MASK (0x10U) -#define DMA_COMMON_ENABLESET_ENABLE4_SHIFT (4U) -/*! ENABLE4 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE4_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE4_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE5_MASK (0x20U) -#define DMA_COMMON_ENABLESET_ENABLE5_SHIFT (5U) -/*! ENABLE5 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE5_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE5_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE6_MASK (0x40U) -#define DMA_COMMON_ENABLESET_ENABLE6_SHIFT (6U) -/*! ENABLE6 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE6_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE6_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE7_MASK (0x80U) -#define DMA_COMMON_ENABLESET_ENABLE7_SHIFT (7U) -/*! ENABLE7 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE7_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE7_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE8_MASK (0x100U) -#define DMA_COMMON_ENABLESET_ENABLE8_SHIFT (8U) -/*! ENABLE8 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE8_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE8_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE9_MASK (0x200U) -#define DMA_COMMON_ENABLESET_ENABLE9_SHIFT (9U) -/*! ENABLE9 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE9_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE9_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE10_MASK (0x400U) -#define DMA_COMMON_ENABLESET_ENABLE10_SHIFT (10U) -/*! ENABLE10 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE10_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE10_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE11_MASK (0x800U) -#define DMA_COMMON_ENABLESET_ENABLE11_SHIFT (11U) -/*! ENABLE11 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE11_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE11_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE12_MASK (0x1000U) -#define DMA_COMMON_ENABLESET_ENABLE12_SHIFT (12U) -/*! ENABLE12 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE12_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE12_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE13_MASK (0x2000U) -#define DMA_COMMON_ENABLESET_ENABLE13_SHIFT (13U) -/*! ENABLE13 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE13_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE13_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE14_MASK (0x4000U) -#define DMA_COMMON_ENABLESET_ENABLE14_SHIFT (14U) -/*! ENABLE14 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE14_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE14_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE15_MASK (0x8000U) -#define DMA_COMMON_ENABLESET_ENABLE15_SHIFT (15U) -/*! ENABLE15 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE15_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE15_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE16_MASK (0x10000U) -#define DMA_COMMON_ENABLESET_ENABLE16_SHIFT (16U) -/*! ENABLE16 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE16_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE16_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE17_MASK (0x20000U) -#define DMA_COMMON_ENABLESET_ENABLE17_SHIFT (17U) -/*! ENABLE17 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE17_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE17_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE18_MASK (0x40000U) -#define DMA_COMMON_ENABLESET_ENABLE18_SHIFT (18U) -/*! ENABLE18 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE18_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE18_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE19_MASK (0x80000U) -#define DMA_COMMON_ENABLESET_ENABLE19_SHIFT (19U) -/*! ENABLE19 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE19_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE19_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE20_MASK (0x100000U) -#define DMA_COMMON_ENABLESET_ENABLE20_SHIFT (20U) -/*! ENABLE20 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE20_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE20_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE21_MASK (0x200000U) -#define DMA_COMMON_ENABLESET_ENABLE21_SHIFT (21U) -/*! ENABLE21 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE21_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE21_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE22_MASK (0x400000U) -#define DMA_COMMON_ENABLESET_ENABLE22_SHIFT (22U) -/*! ENABLE22 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE22_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE22_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE23_MASK (0x800000U) -#define DMA_COMMON_ENABLESET_ENABLE23_SHIFT (23U) -/*! ENABLE23 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE23_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE23_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE24_MASK (0x1000000U) -#define DMA_COMMON_ENABLESET_ENABLE24_SHIFT (24U) -/*! ENABLE24 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE24_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE24_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE25_MASK (0x2000000U) -#define DMA_COMMON_ENABLESET_ENABLE25_SHIFT (25U) -/*! ENABLE25 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE25_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE25_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE26_MASK (0x4000000U) -#define DMA_COMMON_ENABLESET_ENABLE26_SHIFT (26U) -/*! ENABLE26 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE26_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE26_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE27_MASK (0x8000000U) -#define DMA_COMMON_ENABLESET_ENABLE27_SHIFT (27U) -/*! ENABLE27 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE27_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE27_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE28_MASK (0x10000000U) -#define DMA_COMMON_ENABLESET_ENABLE28_SHIFT (28U) -/*! ENABLE28 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE28_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE28_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE29_MASK (0x20000000U) -#define DMA_COMMON_ENABLESET_ENABLE29_SHIFT (29U) -/*! ENABLE29 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE29_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE29_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE30_MASK (0x40000000U) -#define DMA_COMMON_ENABLESET_ENABLE30_SHIFT (30U) -/*! ENABLE30 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE30_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE30_MASK) - -#define DMA_COMMON_ENABLESET_ENABLE31_MASK (0x80000000U) -#define DMA_COMMON_ENABLESET_ENABLE31_SHIFT (31U) -/*! ENABLE31 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET_ENABLE31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE31_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE31_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLESET */ -#define DMA_COMMON_ENABLESET_COUNT (1U) - -/*! @name COMMON_ENABLESET1 - Channel Enable read and set for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_ENABLESET1_ENABLE32_MASK (0x1U) -#define DMA_COMMON_ENABLESET1_ENABLE32_SHIFT (0U) -/*! ENABLE32 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET1_ENABLE32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE32_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE32_MASK) - -#define DMA_COMMON_ENABLESET1_ENABLE33_MASK (0x2U) -#define DMA_COMMON_ENABLESET1_ENABLE33_SHIFT (1U) -/*! ENABLE33 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET1_ENABLE33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE33_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE33_MASK) - -#define DMA_COMMON_ENABLESET1_ENABLE34_MASK (0x4U) -#define DMA_COMMON_ENABLESET1_ENABLE34_SHIFT (2U) -/*! ENABLE34 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET1_ENABLE34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE34_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE34_MASK) - -#define DMA_COMMON_ENABLESET1_ENABLE35_MASK (0x8U) -#define DMA_COMMON_ENABLESET1_ENABLE35_SHIFT (3U) -/*! ENABLE35 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET1_ENABLE35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE35_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE35_MASK) - -#define DMA_COMMON_ENABLESET1_ENABLE36_MASK (0x10U) -#define DMA_COMMON_ENABLESET1_ENABLE36_SHIFT (4U) -/*! ENABLE36 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET1_ENABLE36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE36_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE36_MASK) - -#define DMA_COMMON_ENABLESET1_ENABLE37_MASK (0x20U) -#define DMA_COMMON_ENABLESET1_ENABLE37_SHIFT (5U) -/*! ENABLE37 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET1_ENABLE37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE37_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE37_MASK) - -#define DMA_COMMON_ENABLESET1_ENABLE38_MASK (0x40U) -#define DMA_COMMON_ENABLESET1_ENABLE38_SHIFT (6U) -/*! ENABLE38 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET1_ENABLE38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE38_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE38_MASK) - -#define DMA_COMMON_ENABLESET1_ENABLE39_MASK (0x80U) -#define DMA_COMMON_ENABLESET1_ENABLE39_SHIFT (7U) -/*! ENABLE39 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET1_ENABLE39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE39_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE39_MASK) - -#define DMA_COMMON_ENABLESET1_ENABLE40_MASK (0x100U) -#define DMA_COMMON_ENABLESET1_ENABLE40_SHIFT (8U) -/*! ENABLE40 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET1_ENABLE40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE40_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE40_MASK) - -#define DMA_COMMON_ENABLESET1_ENABLE41_MASK (0x200U) -#define DMA_COMMON_ENABLESET1_ENABLE41_SHIFT (9U) -/*! ENABLE41 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET1_ENABLE41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE41_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE41_MASK) - -#define DMA_COMMON_ENABLESET1_ENABLE42_MASK (0x400U) -#define DMA_COMMON_ENABLESET1_ENABLE42_SHIFT (10U) -/*! ENABLE42 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET1_ENABLE42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE42_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE42_MASK) - -#define DMA_COMMON_ENABLESET1_ENABLE43_MASK (0x800U) -#define DMA_COMMON_ENABLESET1_ENABLE43_SHIFT (11U) -/*! ENABLE43 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET1_ENABLE43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE43_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE43_MASK) - -#define DMA_COMMON_ENABLESET1_ENABLE44_MASK (0x1000U) -#define DMA_COMMON_ENABLESET1_ENABLE44_SHIFT (12U) -/*! ENABLE44 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET1_ENABLE44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE44_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE44_MASK) - -#define DMA_COMMON_ENABLESET1_ENABLE45_MASK (0x2000U) -#define DMA_COMMON_ENABLESET1_ENABLE45_SHIFT (13U) -/*! ENABLE45 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET1_ENABLE45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE45_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE45_MASK) - -#define DMA_COMMON_ENABLESET1_ENABLE46_MASK (0x4000U) -#define DMA_COMMON_ENABLESET1_ENABLE46_SHIFT (14U) -/*! ENABLE46 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET1_ENABLE46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE46_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE46_MASK) - -#define DMA_COMMON_ENABLESET1_ENABLE47_MASK (0x8000U) -#define DMA_COMMON_ENABLESET1_ENABLE47_SHIFT (15U) -/*! ENABLE47 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET1_ENABLE47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE47_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE47_MASK) - -#define DMA_COMMON_ENABLESET1_ENABLE48_MASK (0x10000U) -#define DMA_COMMON_ENABLESET1_ENABLE48_SHIFT (16U) -/*! ENABLE48 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET1_ENABLE48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE48_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE48_MASK) - -#define DMA_COMMON_ENABLESET1_ENABLE49_MASK (0x20000U) -#define DMA_COMMON_ENABLESET1_ENABLE49_SHIFT (17U) -/*! ENABLE49 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET1_ENABLE49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE49_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE49_MASK) - -#define DMA_COMMON_ENABLESET1_ENABLE50_MASK (0x40000U) -#define DMA_COMMON_ENABLESET1_ENABLE50_SHIFT (18U) -/*! ENABLE50 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET1_ENABLE50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE50_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE50_MASK) - -#define DMA_COMMON_ENABLESET1_ENABLE51_MASK (0x80000U) -#define DMA_COMMON_ENABLESET1_ENABLE51_SHIFT (19U) -/*! ENABLE51 - Enable for DMA channel - * 0b0..DMA channel is disabled. - * 0b1..DMA channel is enabled. - */ -#define DMA_COMMON_ENABLESET1_ENABLE51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE51_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE51_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLESET1 */ -#define DMA_COMMON_ENABLESET1_COUNT (1U) - -/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_ENABLECLR_CLR0_MASK (0x1U) -#define DMA_COMMON_ENABLECLR_CLR0_SHIFT (0U) -/*! CLR0 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR0_SHIFT)) & DMA_COMMON_ENABLECLR_CLR0_MASK) - -#define DMA_COMMON_ENABLECLR_CLR1_MASK (0x2U) -#define DMA_COMMON_ENABLECLR_CLR1_SHIFT (1U) -/*! CLR1 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR1_SHIFT)) & DMA_COMMON_ENABLECLR_CLR1_MASK) - -#define DMA_COMMON_ENABLECLR_CLR2_MASK (0x4U) -#define DMA_COMMON_ENABLECLR_CLR2_SHIFT (2U) -/*! CLR2 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR2_SHIFT)) & DMA_COMMON_ENABLECLR_CLR2_MASK) - -#define DMA_COMMON_ENABLECLR_CLR3_MASK (0x8U) -#define DMA_COMMON_ENABLECLR_CLR3_SHIFT (3U) -/*! CLR3 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR3_SHIFT)) & DMA_COMMON_ENABLECLR_CLR3_MASK) - -#define DMA_COMMON_ENABLECLR_CLR4_MASK (0x10U) -#define DMA_COMMON_ENABLECLR_CLR4_SHIFT (4U) -/*! CLR4 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR4_SHIFT)) & DMA_COMMON_ENABLECLR_CLR4_MASK) - -#define DMA_COMMON_ENABLECLR_CLR5_MASK (0x20U) -#define DMA_COMMON_ENABLECLR_CLR5_SHIFT (5U) -/*! CLR5 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR5_SHIFT)) & DMA_COMMON_ENABLECLR_CLR5_MASK) - -#define DMA_COMMON_ENABLECLR_CLR6_MASK (0x40U) -#define DMA_COMMON_ENABLECLR_CLR6_SHIFT (6U) -/*! CLR6 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR6_SHIFT)) & DMA_COMMON_ENABLECLR_CLR6_MASK) - -#define DMA_COMMON_ENABLECLR_CLR7_MASK (0x80U) -#define DMA_COMMON_ENABLECLR_CLR7_SHIFT (7U) -/*! CLR7 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR7_SHIFT)) & DMA_COMMON_ENABLECLR_CLR7_MASK) - -#define DMA_COMMON_ENABLECLR_CLR8_MASK (0x100U) -#define DMA_COMMON_ENABLECLR_CLR8_SHIFT (8U) -/*! CLR8 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR8_SHIFT)) & DMA_COMMON_ENABLECLR_CLR8_MASK) - -#define DMA_COMMON_ENABLECLR_CLR9_MASK (0x200U) -#define DMA_COMMON_ENABLECLR_CLR9_SHIFT (9U) -/*! CLR9 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR9_SHIFT)) & DMA_COMMON_ENABLECLR_CLR9_MASK) - -#define DMA_COMMON_ENABLECLR_CLR10_MASK (0x400U) -#define DMA_COMMON_ENABLECLR_CLR10_SHIFT (10U) -/*! CLR10 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR10_SHIFT)) & DMA_COMMON_ENABLECLR_CLR10_MASK) - -#define DMA_COMMON_ENABLECLR_CLR11_MASK (0x800U) -#define DMA_COMMON_ENABLECLR_CLR11_SHIFT (11U) -/*! CLR11 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR11_SHIFT)) & DMA_COMMON_ENABLECLR_CLR11_MASK) - -#define DMA_COMMON_ENABLECLR_CLR12_MASK (0x1000U) -#define DMA_COMMON_ENABLECLR_CLR12_SHIFT (12U) -/*! CLR12 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR12_SHIFT)) & DMA_COMMON_ENABLECLR_CLR12_MASK) - -#define DMA_COMMON_ENABLECLR_CLR13_MASK (0x2000U) -#define DMA_COMMON_ENABLECLR_CLR13_SHIFT (13U) -/*! CLR13 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR13_SHIFT)) & DMA_COMMON_ENABLECLR_CLR13_MASK) - -#define DMA_COMMON_ENABLECLR_CLR14_MASK (0x4000U) -#define DMA_COMMON_ENABLECLR_CLR14_SHIFT (14U) -/*! CLR14 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR14_SHIFT)) & DMA_COMMON_ENABLECLR_CLR14_MASK) - -#define DMA_COMMON_ENABLECLR_CLR15_MASK (0x8000U) -#define DMA_COMMON_ENABLECLR_CLR15_SHIFT (15U) -/*! CLR15 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR15_SHIFT)) & DMA_COMMON_ENABLECLR_CLR15_MASK) - -#define DMA_COMMON_ENABLECLR_CLR16_MASK (0x10000U) -#define DMA_COMMON_ENABLECLR_CLR16_SHIFT (16U) -/*! CLR16 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR16_SHIFT)) & DMA_COMMON_ENABLECLR_CLR16_MASK) - -#define DMA_COMMON_ENABLECLR_CLR17_MASK (0x20000U) -#define DMA_COMMON_ENABLECLR_CLR17_SHIFT (17U) -/*! CLR17 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR17_SHIFT)) & DMA_COMMON_ENABLECLR_CLR17_MASK) - -#define DMA_COMMON_ENABLECLR_CLR18_MASK (0x40000U) -#define DMA_COMMON_ENABLECLR_CLR18_SHIFT (18U) -/*! CLR18 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR18_SHIFT)) & DMA_COMMON_ENABLECLR_CLR18_MASK) - -#define DMA_COMMON_ENABLECLR_CLR19_MASK (0x80000U) -#define DMA_COMMON_ENABLECLR_CLR19_SHIFT (19U) -/*! CLR19 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR19_SHIFT)) & DMA_COMMON_ENABLECLR_CLR19_MASK) - -#define DMA_COMMON_ENABLECLR_CLR20_MASK (0x100000U) -#define DMA_COMMON_ENABLECLR_CLR20_SHIFT (20U) -/*! CLR20 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR20_SHIFT)) & DMA_COMMON_ENABLECLR_CLR20_MASK) - -#define DMA_COMMON_ENABLECLR_CLR21_MASK (0x200000U) -#define DMA_COMMON_ENABLECLR_CLR21_SHIFT (21U) -/*! CLR21 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR21_SHIFT)) & DMA_COMMON_ENABLECLR_CLR21_MASK) - -#define DMA_COMMON_ENABLECLR_CLR22_MASK (0x400000U) -#define DMA_COMMON_ENABLECLR_CLR22_SHIFT (22U) -/*! CLR22 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR22_SHIFT)) & DMA_COMMON_ENABLECLR_CLR22_MASK) - -#define DMA_COMMON_ENABLECLR_CLR23_MASK (0x800000U) -#define DMA_COMMON_ENABLECLR_CLR23_SHIFT (23U) -/*! CLR23 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR23_SHIFT)) & DMA_COMMON_ENABLECLR_CLR23_MASK) - -#define DMA_COMMON_ENABLECLR_CLR24_MASK (0x1000000U) -#define DMA_COMMON_ENABLECLR_CLR24_SHIFT (24U) -/*! CLR24 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR24_SHIFT)) & DMA_COMMON_ENABLECLR_CLR24_MASK) - -#define DMA_COMMON_ENABLECLR_CLR25_MASK (0x2000000U) -#define DMA_COMMON_ENABLECLR_CLR25_SHIFT (25U) -/*! CLR25 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR25_SHIFT)) & DMA_COMMON_ENABLECLR_CLR25_MASK) - -#define DMA_COMMON_ENABLECLR_CLR26_MASK (0x4000000U) -#define DMA_COMMON_ENABLECLR_CLR26_SHIFT (26U) -/*! CLR26 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR26_SHIFT)) & DMA_COMMON_ENABLECLR_CLR26_MASK) - -#define DMA_COMMON_ENABLECLR_CLR27_MASK (0x8000000U) -#define DMA_COMMON_ENABLECLR_CLR27_SHIFT (27U) -/*! CLR27 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR27_SHIFT)) & DMA_COMMON_ENABLECLR_CLR27_MASK) - -#define DMA_COMMON_ENABLECLR_CLR28_MASK (0x10000000U) -#define DMA_COMMON_ENABLECLR_CLR28_SHIFT (28U) -/*! CLR28 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR28_SHIFT)) & DMA_COMMON_ENABLECLR_CLR28_MASK) - -#define DMA_COMMON_ENABLECLR_CLR29_MASK (0x20000000U) -#define DMA_COMMON_ENABLECLR_CLR29_SHIFT (29U) -/*! CLR29 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR29_SHIFT)) & DMA_COMMON_ENABLECLR_CLR29_MASK) - -#define DMA_COMMON_ENABLECLR_CLR30_MASK (0x40000000U) -#define DMA_COMMON_ENABLECLR_CLR30_SHIFT (30U) -/*! CLR30 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR30_SHIFT)) & DMA_COMMON_ENABLECLR_CLR30_MASK) - -#define DMA_COMMON_ENABLECLR_CLR31_MASK (0x80000000U) -#define DMA_COMMON_ENABLECLR_CLR31_SHIFT (31U) -/*! CLR31 - Writing ones to this register clears the corresponding bits in ENABLESET0. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR_CLR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR31_SHIFT)) & DMA_COMMON_ENABLECLR_CLR31_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLECLR */ -#define DMA_COMMON_ENABLECLR_COUNT (1U) - -/*! @name COMMON_ENABLECLR1 - Channel Enable Clear for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_ENABLECLR1_CLR32_MASK (0x1U) -#define DMA_COMMON_ENABLECLR1_CLR32_SHIFT (0U) -/*! CLR32 - Writing ones to this register clears the corresponding bits in ENABLESET1. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR1_CLR32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR32_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR32_MASK) - -#define DMA_COMMON_ENABLECLR1_CLR33_MASK (0x2U) -#define DMA_COMMON_ENABLECLR1_CLR33_SHIFT (1U) -/*! CLR33 - Writing ones to this register clears the corresponding bits in ENABLESET1. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR1_CLR33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR33_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR33_MASK) - -#define DMA_COMMON_ENABLECLR1_CLR34_MASK (0x4U) -#define DMA_COMMON_ENABLECLR1_CLR34_SHIFT (2U) -/*! CLR34 - Writing ones to this register clears the corresponding bits in ENABLESET1. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR1_CLR34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR34_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR34_MASK) - -#define DMA_COMMON_ENABLECLR1_CLR35_MASK (0x8U) -#define DMA_COMMON_ENABLECLR1_CLR35_SHIFT (3U) -/*! CLR35 - Writing ones to this register clears the corresponding bits in ENABLESET1. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR1_CLR35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR35_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR35_MASK) - -#define DMA_COMMON_ENABLECLR1_CLR36_MASK (0x10U) -#define DMA_COMMON_ENABLECLR1_CLR36_SHIFT (4U) -/*! CLR36 - Writing ones to this register clears the corresponding bits in ENABLESET1. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR1_CLR36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR36_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR36_MASK) - -#define DMA_COMMON_ENABLECLR1_CLR37_MASK (0x20U) -#define DMA_COMMON_ENABLECLR1_CLR37_SHIFT (5U) -/*! CLR37 - Writing ones to this register clears the corresponding bits in ENABLESET1. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR1_CLR37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR37_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR37_MASK) - -#define DMA_COMMON_ENABLECLR1_CLR38_MASK (0x40U) -#define DMA_COMMON_ENABLECLR1_CLR38_SHIFT (6U) -/*! CLR38 - Writing ones to this register clears the corresponding bits in ENABLESET1. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR1_CLR38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR38_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR38_MASK) - -#define DMA_COMMON_ENABLECLR1_CLR39_MASK (0x80U) -#define DMA_COMMON_ENABLECLR1_CLR39_SHIFT (7U) -/*! CLR39 - Writing ones to this register clears the corresponding bits in ENABLESET1. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR1_CLR39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR39_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR39_MASK) - -#define DMA_COMMON_ENABLECLR1_CLR40_MASK (0x100U) -#define DMA_COMMON_ENABLECLR1_CLR40_SHIFT (8U) -/*! CLR40 - Writing ones to this register clears the corresponding bits in ENABLESET1. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR1_CLR40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR40_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR40_MASK) - -#define DMA_COMMON_ENABLECLR1_CLR41_MASK (0x200U) -#define DMA_COMMON_ENABLECLR1_CLR41_SHIFT (9U) -/*! CLR41 - Writing ones to this register clears the corresponding bits in ENABLESET1. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR1_CLR41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR41_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR41_MASK) - -#define DMA_COMMON_ENABLECLR1_CLR42_MASK (0x400U) -#define DMA_COMMON_ENABLECLR1_CLR42_SHIFT (10U) -/*! CLR42 - Writing ones to this register clears the corresponding bits in ENABLESET1. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR1_CLR42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR42_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR42_MASK) - -#define DMA_COMMON_ENABLECLR1_CLR43_MASK (0x800U) -#define DMA_COMMON_ENABLECLR1_CLR43_SHIFT (11U) -/*! CLR43 - Writing ones to this register clears the corresponding bits in ENABLESET1. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR1_CLR43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR43_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR43_MASK) - -#define DMA_COMMON_ENABLECLR1_CLR44_MASK (0x1000U) -#define DMA_COMMON_ENABLECLR1_CLR44_SHIFT (12U) -/*! CLR44 - Writing ones to this register clears the corresponding bits in ENABLESET1. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR1_CLR44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR44_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR44_MASK) - -#define DMA_COMMON_ENABLECLR1_CLR45_MASK (0x2000U) -#define DMA_COMMON_ENABLECLR1_CLR45_SHIFT (13U) -/*! CLR45 - Writing ones to this register clears the corresponding bits in ENABLESET1. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR1_CLR45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR45_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR45_MASK) - -#define DMA_COMMON_ENABLECLR1_CLR46_MASK (0x4000U) -#define DMA_COMMON_ENABLECLR1_CLR46_SHIFT (14U) -/*! CLR46 - Writing ones to this register clears the corresponding bits in ENABLESET1. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR1_CLR46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR46_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR46_MASK) - -#define DMA_COMMON_ENABLECLR1_CLR47_MASK (0x8000U) -#define DMA_COMMON_ENABLECLR1_CLR47_SHIFT (15U) -/*! CLR47 - Writing ones to this register clears the corresponding bits in ENABLESET1. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR1_CLR47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR47_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR47_MASK) - -#define DMA_COMMON_ENABLECLR1_CLR48_MASK (0x10000U) -#define DMA_COMMON_ENABLECLR1_CLR48_SHIFT (16U) -/*! CLR48 - Writing ones to this register clears the corresponding bits in ENABLESET1. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR1_CLR48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR48_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR48_MASK) - -#define DMA_COMMON_ENABLECLR1_CLR49_MASK (0x20000U) -#define DMA_COMMON_ENABLECLR1_CLR49_SHIFT (17U) -/*! CLR49 - Writing ones to this register clears the corresponding bits in ENABLESET1. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR1_CLR49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR49_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR49_MASK) - -#define DMA_COMMON_ENABLECLR1_CLR50_MASK (0x40000U) -#define DMA_COMMON_ENABLECLR1_CLR50_SHIFT (18U) -/*! CLR50 - Writing ones to this register clears the corresponding bits in ENABLESET1. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR1_CLR50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR50_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR50_MASK) - -#define DMA_COMMON_ENABLECLR1_CLR51_MASK (0x80000U) -#define DMA_COMMON_ENABLECLR1_CLR51_SHIFT (19U) -/*! CLR51 - Writing ones to this register clears the corresponding bits in ENABLESET1. - * 0b0..No effect. - * 0b1..DMA channel is cleared. - */ -#define DMA_COMMON_ENABLECLR1_CLR51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR51_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR51_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLECLR1 */ -#define DMA_COMMON_ENABLECLR1_COUNT (1U) - -/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_ACTIVE_ACTIVE0_MASK (0x1U) -#define DMA_COMMON_ACTIVE_ACTIVE0_SHIFT (0U) -/*! ACTIVE0 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE0_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE0_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE1_MASK (0x2U) -#define DMA_COMMON_ACTIVE_ACTIVE1_SHIFT (1U) -/*! ACTIVE1 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE1_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE1_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE2_MASK (0x4U) -#define DMA_COMMON_ACTIVE_ACTIVE2_SHIFT (2U) -/*! ACTIVE2 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE2_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE2_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE3_MASK (0x8U) -#define DMA_COMMON_ACTIVE_ACTIVE3_SHIFT (3U) -/*! ACTIVE3 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE3_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE3_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE4_MASK (0x10U) -#define DMA_COMMON_ACTIVE_ACTIVE4_SHIFT (4U) -/*! ACTIVE4 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE4_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE4_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE5_MASK (0x20U) -#define DMA_COMMON_ACTIVE_ACTIVE5_SHIFT (5U) -/*! ACTIVE5 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE5_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE5_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE6_MASK (0x40U) -#define DMA_COMMON_ACTIVE_ACTIVE6_SHIFT (6U) -/*! ACTIVE6 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE6_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE6_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE7_MASK (0x80U) -#define DMA_COMMON_ACTIVE_ACTIVE7_SHIFT (7U) -/*! ACTIVE7 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE7_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE7_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE8_MASK (0x100U) -#define DMA_COMMON_ACTIVE_ACTIVE8_SHIFT (8U) -/*! ACTIVE8 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE8_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE8_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE9_MASK (0x200U) -#define DMA_COMMON_ACTIVE_ACTIVE9_SHIFT (9U) -/*! ACTIVE9 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE9_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE9_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE10_MASK (0x400U) -#define DMA_COMMON_ACTIVE_ACTIVE10_SHIFT (10U) -/*! ACTIVE10 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE10_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE10_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE11_MASK (0x800U) -#define DMA_COMMON_ACTIVE_ACTIVE11_SHIFT (11U) -/*! ACTIVE11 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE11_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE11_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE12_MASK (0x1000U) -#define DMA_COMMON_ACTIVE_ACTIVE12_SHIFT (12U) -/*! ACTIVE12 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE12_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE12_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE13_MASK (0x2000U) -#define DMA_COMMON_ACTIVE_ACTIVE13_SHIFT (13U) -/*! ACTIVE13 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE13_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE13_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE14_MASK (0x4000U) -#define DMA_COMMON_ACTIVE_ACTIVE14_SHIFT (14U) -/*! ACTIVE14 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE14_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE14_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE15_MASK (0x8000U) -#define DMA_COMMON_ACTIVE_ACTIVE15_SHIFT (15U) -/*! ACTIVE15 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE15_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE15_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE16_MASK (0x10000U) -#define DMA_COMMON_ACTIVE_ACTIVE16_SHIFT (16U) -/*! ACTIVE16 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE16_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE16_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE17_MASK (0x20000U) -#define DMA_COMMON_ACTIVE_ACTIVE17_SHIFT (17U) -/*! ACTIVE17 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE17_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE17_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE18_MASK (0x40000U) -#define DMA_COMMON_ACTIVE_ACTIVE18_SHIFT (18U) -/*! ACTIVE18 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE18_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE18_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE19_MASK (0x80000U) -#define DMA_COMMON_ACTIVE_ACTIVE19_SHIFT (19U) -/*! ACTIVE19 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE19_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE19_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE20_MASK (0x100000U) -#define DMA_COMMON_ACTIVE_ACTIVE20_SHIFT (20U) -/*! ACTIVE20 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE20_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE20_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE21_MASK (0x200000U) -#define DMA_COMMON_ACTIVE_ACTIVE21_SHIFT (21U) -/*! ACTIVE21 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE21_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE21_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE22_MASK (0x400000U) -#define DMA_COMMON_ACTIVE_ACTIVE22_SHIFT (22U) -/*! ACTIVE22 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE22_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE22_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE23_MASK (0x800000U) -#define DMA_COMMON_ACTIVE_ACTIVE23_SHIFT (23U) -/*! ACTIVE23 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE23_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE23_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE24_MASK (0x1000000U) -#define DMA_COMMON_ACTIVE_ACTIVE24_SHIFT (24U) -/*! ACTIVE24 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE24_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE24_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE25_MASK (0x2000000U) -#define DMA_COMMON_ACTIVE_ACTIVE25_SHIFT (25U) -/*! ACTIVE25 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE25_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE25_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE26_MASK (0x4000000U) -#define DMA_COMMON_ACTIVE_ACTIVE26_SHIFT (26U) -/*! ACTIVE26 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE26_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE26_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE27_MASK (0x8000000U) -#define DMA_COMMON_ACTIVE_ACTIVE27_SHIFT (27U) -/*! ACTIVE27 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE27_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE27_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE28_MASK (0x10000000U) -#define DMA_COMMON_ACTIVE_ACTIVE28_SHIFT (28U) -/*! ACTIVE28 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE28_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE28_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE29_MASK (0x20000000U) -#define DMA_COMMON_ACTIVE_ACTIVE29_SHIFT (29U) -/*! ACTIVE29 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE29_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE29_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE30_MASK (0x40000000U) -#define DMA_COMMON_ACTIVE_ACTIVE30_SHIFT (30U) -/*! ACTIVE30 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE30_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE30_MASK) - -#define DMA_COMMON_ACTIVE_ACTIVE31_MASK (0x80000000U) -#define DMA_COMMON_ACTIVE_ACTIVE31_SHIFT (31U) -/*! ACTIVE31 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE_ACTIVE31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE31_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE31_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ACTIVE */ -#define DMA_COMMON_ACTIVE_COUNT (1U) - -/*! @name COMMON_ACTIVE1 - Channel Active status for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_ACTIVE1_ACTIVE32_MASK (0x1U) -#define DMA_COMMON_ACTIVE1_ACTIVE32_SHIFT (0U) -/*! ACTIVE32 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE1_ACTIVE32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE32_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE32_MASK) - -#define DMA_COMMON_ACTIVE1_ACTIVE33_MASK (0x2U) -#define DMA_COMMON_ACTIVE1_ACTIVE33_SHIFT (1U) -/*! ACTIVE33 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE1_ACTIVE33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE33_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE33_MASK) - -#define DMA_COMMON_ACTIVE1_ACTIVE34_MASK (0x4U) -#define DMA_COMMON_ACTIVE1_ACTIVE34_SHIFT (2U) -/*! ACTIVE34 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE1_ACTIVE34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE34_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE34_MASK) - -#define DMA_COMMON_ACTIVE1_ACTIVE35_MASK (0x8U) -#define DMA_COMMON_ACTIVE1_ACTIVE35_SHIFT (3U) -/*! ACTIVE35 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE1_ACTIVE35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE35_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE35_MASK) - -#define DMA_COMMON_ACTIVE1_ACTIVE36_MASK (0x10U) -#define DMA_COMMON_ACTIVE1_ACTIVE36_SHIFT (4U) -/*! ACTIVE36 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE1_ACTIVE36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE36_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE36_MASK) - -#define DMA_COMMON_ACTIVE1_ACTIVE37_MASK (0x20U) -#define DMA_COMMON_ACTIVE1_ACTIVE37_SHIFT (5U) -/*! ACTIVE37 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE1_ACTIVE37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE37_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE37_MASK) - -#define DMA_COMMON_ACTIVE1_ACTIVE38_MASK (0x40U) -#define DMA_COMMON_ACTIVE1_ACTIVE38_SHIFT (6U) -/*! ACTIVE38 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE1_ACTIVE38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE38_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE38_MASK) - -#define DMA_COMMON_ACTIVE1_ACTIVE39_MASK (0x80U) -#define DMA_COMMON_ACTIVE1_ACTIVE39_SHIFT (7U) -/*! ACTIVE39 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE1_ACTIVE39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE39_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE39_MASK) - -#define DMA_COMMON_ACTIVE1_ACTIVE40_MASK (0x100U) -#define DMA_COMMON_ACTIVE1_ACTIVE40_SHIFT (8U) -/*! ACTIVE40 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE1_ACTIVE40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE40_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE40_MASK) - -#define DMA_COMMON_ACTIVE1_ACTIVE41_MASK (0x200U) -#define DMA_COMMON_ACTIVE1_ACTIVE41_SHIFT (9U) -/*! ACTIVE41 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE1_ACTIVE41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE41_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE41_MASK) - -#define DMA_COMMON_ACTIVE1_ACTIVE42_MASK (0x400U) -#define DMA_COMMON_ACTIVE1_ACTIVE42_SHIFT (10U) -/*! ACTIVE42 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE1_ACTIVE42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE42_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE42_MASK) - -#define DMA_COMMON_ACTIVE1_ACTIVE43_MASK (0x800U) -#define DMA_COMMON_ACTIVE1_ACTIVE43_SHIFT (11U) -/*! ACTIVE43 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE1_ACTIVE43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE43_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE43_MASK) - -#define DMA_COMMON_ACTIVE1_ACTIVE44_MASK (0x1000U) -#define DMA_COMMON_ACTIVE1_ACTIVE44_SHIFT (12U) -/*! ACTIVE44 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE1_ACTIVE44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE44_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE44_MASK) - -#define DMA_COMMON_ACTIVE1_ACTIVE45_MASK (0x2000U) -#define DMA_COMMON_ACTIVE1_ACTIVE45_SHIFT (13U) -/*! ACTIVE45 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE1_ACTIVE45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE45_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE45_MASK) - -#define DMA_COMMON_ACTIVE1_ACTIVE46_MASK (0x4000U) -#define DMA_COMMON_ACTIVE1_ACTIVE46_SHIFT (14U) -/*! ACTIVE46 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE1_ACTIVE46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE46_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE46_MASK) - -#define DMA_COMMON_ACTIVE1_ACTIVE47_MASK (0x8000U) -#define DMA_COMMON_ACTIVE1_ACTIVE47_SHIFT (15U) -/*! ACTIVE47 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE1_ACTIVE47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE47_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE47_MASK) - -#define DMA_COMMON_ACTIVE1_ACTIVE48_MASK (0x10000U) -#define DMA_COMMON_ACTIVE1_ACTIVE48_SHIFT (16U) -/*! ACTIVE48 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE1_ACTIVE48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE48_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE48_MASK) - -#define DMA_COMMON_ACTIVE1_ACTIVE49_MASK (0x20000U) -#define DMA_COMMON_ACTIVE1_ACTIVE49_SHIFT (17U) -/*! ACTIVE49 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE1_ACTIVE49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE49_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE49_MASK) - -#define DMA_COMMON_ACTIVE1_ACTIVE50_MASK (0x40000U) -#define DMA_COMMON_ACTIVE1_ACTIVE50_SHIFT (18U) -/*! ACTIVE50 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE1_ACTIVE50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE50_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE50_MASK) - -#define DMA_COMMON_ACTIVE1_ACTIVE51_MASK (0x80000U) -#define DMA_COMMON_ACTIVE1_ACTIVE51_SHIFT (19U) -/*! ACTIVE51 - Active flag for DMA channel. - * 0b0..DMA channel is not active. - * 0b1..DMA channel is active. - */ -#define DMA_COMMON_ACTIVE1_ACTIVE51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE51_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE51_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ACTIVE1 */ -#define DMA_COMMON_ACTIVE1_COUNT (1U) - -/*! @name COMMON_BUSY - Channel Busy status for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_BUSY_BUSY0_MASK (0x1U) -#define DMA_COMMON_BUSY_BUSY0_SHIFT (0U) -/*! BUSY0 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY0_SHIFT)) & DMA_COMMON_BUSY_BUSY0_MASK) - -#define DMA_COMMON_BUSY_BUSY1_MASK (0x2U) -#define DMA_COMMON_BUSY_BUSY1_SHIFT (1U) -/*! BUSY1 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY1_SHIFT)) & DMA_COMMON_BUSY_BUSY1_MASK) - -#define DMA_COMMON_BUSY_BUSY2_MASK (0x4U) -#define DMA_COMMON_BUSY_BUSY2_SHIFT (2U) -/*! BUSY2 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY2_SHIFT)) & DMA_COMMON_BUSY_BUSY2_MASK) - -#define DMA_COMMON_BUSY_BUSY3_MASK (0x8U) -#define DMA_COMMON_BUSY_BUSY3_SHIFT (3U) -/*! BUSY3 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY3_SHIFT)) & DMA_COMMON_BUSY_BUSY3_MASK) - -#define DMA_COMMON_BUSY_BUSY4_MASK (0x10U) -#define DMA_COMMON_BUSY_BUSY4_SHIFT (4U) -/*! BUSY4 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY4_SHIFT)) & DMA_COMMON_BUSY_BUSY4_MASK) - -#define DMA_COMMON_BUSY_BUSY5_MASK (0x20U) -#define DMA_COMMON_BUSY_BUSY5_SHIFT (5U) -/*! BUSY5 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY5_SHIFT)) & DMA_COMMON_BUSY_BUSY5_MASK) - -#define DMA_COMMON_BUSY_BUSY6_MASK (0x40U) -#define DMA_COMMON_BUSY_BUSY6_SHIFT (6U) -/*! BUSY6 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY6_SHIFT)) & DMA_COMMON_BUSY_BUSY6_MASK) - -#define DMA_COMMON_BUSY_BUSY7_MASK (0x80U) -#define DMA_COMMON_BUSY_BUSY7_SHIFT (7U) -/*! BUSY7 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY7_SHIFT)) & DMA_COMMON_BUSY_BUSY7_MASK) - -#define DMA_COMMON_BUSY_BUSY8_MASK (0x100U) -#define DMA_COMMON_BUSY_BUSY8_SHIFT (8U) -/*! BUSY8 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY8_SHIFT)) & DMA_COMMON_BUSY_BUSY8_MASK) - -#define DMA_COMMON_BUSY_BUSY9_MASK (0x200U) -#define DMA_COMMON_BUSY_BUSY9_SHIFT (9U) -/*! BUSY9 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY9_SHIFT)) & DMA_COMMON_BUSY_BUSY9_MASK) - -#define DMA_COMMON_BUSY_BUSY10_MASK (0x400U) -#define DMA_COMMON_BUSY_BUSY10_SHIFT (10U) -/*! BUSY10 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY10_SHIFT)) & DMA_COMMON_BUSY_BUSY10_MASK) - -#define DMA_COMMON_BUSY_BUSY11_MASK (0x800U) -#define DMA_COMMON_BUSY_BUSY11_SHIFT (11U) -/*! BUSY11 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY11_SHIFT)) & DMA_COMMON_BUSY_BUSY11_MASK) - -#define DMA_COMMON_BUSY_BUSY12_MASK (0x1000U) -#define DMA_COMMON_BUSY_BUSY12_SHIFT (12U) -/*! BUSY12 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY12_SHIFT)) & DMA_COMMON_BUSY_BUSY12_MASK) - -#define DMA_COMMON_BUSY_BUSY13_MASK (0x2000U) -#define DMA_COMMON_BUSY_BUSY13_SHIFT (13U) -/*! BUSY13 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY13_SHIFT)) & DMA_COMMON_BUSY_BUSY13_MASK) - -#define DMA_COMMON_BUSY_BUSY14_MASK (0x4000U) -#define DMA_COMMON_BUSY_BUSY14_SHIFT (14U) -/*! BUSY14 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY14_SHIFT)) & DMA_COMMON_BUSY_BUSY14_MASK) - -#define DMA_COMMON_BUSY_BUSY15_MASK (0x8000U) -#define DMA_COMMON_BUSY_BUSY15_SHIFT (15U) -/*! BUSY15 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY15_SHIFT)) & DMA_COMMON_BUSY_BUSY15_MASK) - -#define DMA_COMMON_BUSY_BUSY16_MASK (0x10000U) -#define DMA_COMMON_BUSY_BUSY16_SHIFT (16U) -/*! BUSY16 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY16_SHIFT)) & DMA_COMMON_BUSY_BUSY16_MASK) - -#define DMA_COMMON_BUSY_BUSY17_MASK (0x20000U) -#define DMA_COMMON_BUSY_BUSY17_SHIFT (17U) -/*! BUSY17 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY17_SHIFT)) & DMA_COMMON_BUSY_BUSY17_MASK) - -#define DMA_COMMON_BUSY_BUSY18_MASK (0x40000U) -#define DMA_COMMON_BUSY_BUSY18_SHIFT (18U) -/*! BUSY18 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY18_SHIFT)) & DMA_COMMON_BUSY_BUSY18_MASK) - -#define DMA_COMMON_BUSY_BUSY19_MASK (0x80000U) -#define DMA_COMMON_BUSY_BUSY19_SHIFT (19U) -/*! BUSY19 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY19_SHIFT)) & DMA_COMMON_BUSY_BUSY19_MASK) - -#define DMA_COMMON_BUSY_BUSY20_MASK (0x100000U) -#define DMA_COMMON_BUSY_BUSY20_SHIFT (20U) -/*! BUSY20 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY20_SHIFT)) & DMA_COMMON_BUSY_BUSY20_MASK) - -#define DMA_COMMON_BUSY_BUSY21_MASK (0x200000U) -#define DMA_COMMON_BUSY_BUSY21_SHIFT (21U) -/*! BUSY21 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY21_SHIFT)) & DMA_COMMON_BUSY_BUSY21_MASK) - -#define DMA_COMMON_BUSY_BUSY22_MASK (0x400000U) -#define DMA_COMMON_BUSY_BUSY22_SHIFT (22U) -/*! BUSY22 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY22_SHIFT)) & DMA_COMMON_BUSY_BUSY22_MASK) - -#define DMA_COMMON_BUSY_BUSY23_MASK (0x800000U) -#define DMA_COMMON_BUSY_BUSY23_SHIFT (23U) -/*! BUSY23 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY23_SHIFT)) & DMA_COMMON_BUSY_BUSY23_MASK) - -#define DMA_COMMON_BUSY_BUSY24_MASK (0x1000000U) -#define DMA_COMMON_BUSY_BUSY24_SHIFT (24U) -/*! BUSY24 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY24_SHIFT)) & DMA_COMMON_BUSY_BUSY24_MASK) - -#define DMA_COMMON_BUSY_BUSY25_MASK (0x2000000U) -#define DMA_COMMON_BUSY_BUSY25_SHIFT (25U) -/*! BUSY25 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY25_SHIFT)) & DMA_COMMON_BUSY_BUSY25_MASK) - -#define DMA_COMMON_BUSY_BUSY26_MASK (0x4000000U) -#define DMA_COMMON_BUSY_BUSY26_SHIFT (26U) -/*! BUSY26 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY26_SHIFT)) & DMA_COMMON_BUSY_BUSY26_MASK) - -#define DMA_COMMON_BUSY_BUSY27_MASK (0x8000000U) -#define DMA_COMMON_BUSY_BUSY27_SHIFT (27U) -/*! BUSY27 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY27_SHIFT)) & DMA_COMMON_BUSY_BUSY27_MASK) - -#define DMA_COMMON_BUSY_BUSY28_MASK (0x10000000U) -#define DMA_COMMON_BUSY_BUSY28_SHIFT (28U) -/*! BUSY28 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY28_SHIFT)) & DMA_COMMON_BUSY_BUSY28_MASK) - -#define DMA_COMMON_BUSY_BUSY29_MASK (0x20000000U) -#define DMA_COMMON_BUSY_BUSY29_SHIFT (29U) -/*! BUSY29 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY29_SHIFT)) & DMA_COMMON_BUSY_BUSY29_MASK) - -#define DMA_COMMON_BUSY_BUSY30_MASK (0x40000000U) -#define DMA_COMMON_BUSY_BUSY30_SHIFT (30U) -/*! BUSY30 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY30_SHIFT)) & DMA_COMMON_BUSY_BUSY30_MASK) - -#define DMA_COMMON_BUSY_BUSY31_MASK (0x80000000U) -#define DMA_COMMON_BUSY_BUSY31_SHIFT (31U) -/*! BUSY31 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY_BUSY31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY31_SHIFT)) & DMA_COMMON_BUSY_BUSY31_MASK) -/*! @} */ - -/* The count of DMA_COMMON_BUSY */ -#define DMA_COMMON_BUSY_COUNT (1U) - -/*! @name COMMON_BUSY1 - Channel Busy status for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_BUSY1_BUSY32_MASK (0x1U) -#define DMA_COMMON_BUSY1_BUSY32_SHIFT (0U) -/*! BUSY32 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY1_BUSY32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY32_SHIFT)) & DMA_COMMON_BUSY1_BUSY32_MASK) - -#define DMA_COMMON_BUSY1_BUSY33_MASK (0x2U) -#define DMA_COMMON_BUSY1_BUSY33_SHIFT (1U) -/*! BUSY33 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY1_BUSY33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY33_SHIFT)) & DMA_COMMON_BUSY1_BUSY33_MASK) - -#define DMA_COMMON_BUSY1_BUSY34_MASK (0x4U) -#define DMA_COMMON_BUSY1_BUSY34_SHIFT (2U) -/*! BUSY34 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY1_BUSY34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY34_SHIFT)) & DMA_COMMON_BUSY1_BUSY34_MASK) - -#define DMA_COMMON_BUSY1_BUSY35_MASK (0x8U) -#define DMA_COMMON_BUSY1_BUSY35_SHIFT (3U) -/*! BUSY35 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY1_BUSY35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY35_SHIFT)) & DMA_COMMON_BUSY1_BUSY35_MASK) - -#define DMA_COMMON_BUSY1_BUSY36_MASK (0x10U) -#define DMA_COMMON_BUSY1_BUSY36_SHIFT (4U) -/*! BUSY36 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY1_BUSY36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY36_SHIFT)) & DMA_COMMON_BUSY1_BUSY36_MASK) - -#define DMA_COMMON_BUSY1_BUSY37_MASK (0x20U) -#define DMA_COMMON_BUSY1_BUSY37_SHIFT (5U) -/*! BUSY37 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY1_BUSY37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY37_SHIFT)) & DMA_COMMON_BUSY1_BUSY37_MASK) - -#define DMA_COMMON_BUSY1_BUSY38_MASK (0x40U) -#define DMA_COMMON_BUSY1_BUSY38_SHIFT (6U) -/*! BUSY38 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY1_BUSY38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY38_SHIFT)) & DMA_COMMON_BUSY1_BUSY38_MASK) - -#define DMA_COMMON_BUSY1_BUSY39_MASK (0x80U) -#define DMA_COMMON_BUSY1_BUSY39_SHIFT (7U) -/*! BUSY39 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY1_BUSY39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY39_SHIFT)) & DMA_COMMON_BUSY1_BUSY39_MASK) - -#define DMA_COMMON_BUSY1_BUSY40_MASK (0x100U) -#define DMA_COMMON_BUSY1_BUSY40_SHIFT (8U) -/*! BUSY40 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY1_BUSY40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY40_SHIFT)) & DMA_COMMON_BUSY1_BUSY40_MASK) - -#define DMA_COMMON_BUSY1_BUSY41_MASK (0x200U) -#define DMA_COMMON_BUSY1_BUSY41_SHIFT (9U) -/*! BUSY41 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY1_BUSY41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY41_SHIFT)) & DMA_COMMON_BUSY1_BUSY41_MASK) - -#define DMA_COMMON_BUSY1_BUSY42_MASK (0x400U) -#define DMA_COMMON_BUSY1_BUSY42_SHIFT (10U) -/*! BUSY42 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY1_BUSY42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY42_SHIFT)) & DMA_COMMON_BUSY1_BUSY42_MASK) - -#define DMA_COMMON_BUSY1_BUSY43_MASK (0x800U) -#define DMA_COMMON_BUSY1_BUSY43_SHIFT (11U) -/*! BUSY43 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY1_BUSY43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY43_SHIFT)) & DMA_COMMON_BUSY1_BUSY43_MASK) - -#define DMA_COMMON_BUSY1_BUSY44_MASK (0x1000U) -#define DMA_COMMON_BUSY1_BUSY44_SHIFT (12U) -/*! BUSY44 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY1_BUSY44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY44_SHIFT)) & DMA_COMMON_BUSY1_BUSY44_MASK) - -#define DMA_COMMON_BUSY1_BUSY45_MASK (0x2000U) -#define DMA_COMMON_BUSY1_BUSY45_SHIFT (13U) -/*! BUSY45 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY1_BUSY45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY45_SHIFT)) & DMA_COMMON_BUSY1_BUSY45_MASK) - -#define DMA_COMMON_BUSY1_BUSY46_MASK (0x4000U) -#define DMA_COMMON_BUSY1_BUSY46_SHIFT (14U) -/*! BUSY46 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY1_BUSY46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY46_SHIFT)) & DMA_COMMON_BUSY1_BUSY46_MASK) - -#define DMA_COMMON_BUSY1_BUSY47_MASK (0x8000U) -#define DMA_COMMON_BUSY1_BUSY47_SHIFT (15U) -/*! BUSY47 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY1_BUSY47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY47_SHIFT)) & DMA_COMMON_BUSY1_BUSY47_MASK) - -#define DMA_COMMON_BUSY1_BUSY48_MASK (0x10000U) -#define DMA_COMMON_BUSY1_BUSY48_SHIFT (16U) -/*! BUSY48 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY1_BUSY48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY48_SHIFT)) & DMA_COMMON_BUSY1_BUSY48_MASK) - -#define DMA_COMMON_BUSY1_BUSY49_MASK (0x20000U) -#define DMA_COMMON_BUSY1_BUSY49_SHIFT (17U) -/*! BUSY49 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY1_BUSY49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY49_SHIFT)) & DMA_COMMON_BUSY1_BUSY49_MASK) - -#define DMA_COMMON_BUSY1_BUSY50_MASK (0x40000U) -#define DMA_COMMON_BUSY1_BUSY50_SHIFT (18U) -/*! BUSY50 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY1_BUSY50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY50_SHIFT)) & DMA_COMMON_BUSY1_BUSY50_MASK) - -#define DMA_COMMON_BUSY1_BUSY51_MASK (0x80000U) -#define DMA_COMMON_BUSY1_BUSY51_SHIFT (19U) -/*! BUSY51 - Busy flag for DMA channel. - * 0b0..DMA channel is not busy. - * 0b1..DMA channel is busy. - */ -#define DMA_COMMON_BUSY1_BUSY51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY51_SHIFT)) & DMA_COMMON_BUSY1_BUSY51_MASK) -/*! @} */ - -/* The count of DMA_COMMON_BUSY1 */ -#define DMA_COMMON_BUSY1_COUNT (1U) - -/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_ERRINT_ERR0_MASK (0x1U) -#define DMA_COMMON_ERRINT_ERR0_SHIFT (0U) -/*! ERR0 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR0_SHIFT)) & DMA_COMMON_ERRINT_ERR0_MASK) - -#define DMA_COMMON_ERRINT_ERR1_MASK (0x2U) -#define DMA_COMMON_ERRINT_ERR1_SHIFT (1U) -/*! ERR1 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR1_SHIFT)) & DMA_COMMON_ERRINT_ERR1_MASK) - -#define DMA_COMMON_ERRINT_ERR2_MASK (0x4U) -#define DMA_COMMON_ERRINT_ERR2_SHIFT (2U) -/*! ERR2 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR2_SHIFT)) & DMA_COMMON_ERRINT_ERR2_MASK) - -#define DMA_COMMON_ERRINT_ERR3_MASK (0x8U) -#define DMA_COMMON_ERRINT_ERR3_SHIFT (3U) -/*! ERR3 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR3_SHIFT)) & DMA_COMMON_ERRINT_ERR3_MASK) - -#define DMA_COMMON_ERRINT_ERR4_MASK (0x10U) -#define DMA_COMMON_ERRINT_ERR4_SHIFT (4U) -/*! ERR4 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR4_SHIFT)) & DMA_COMMON_ERRINT_ERR4_MASK) - -#define DMA_COMMON_ERRINT_ERR5_MASK (0x20U) -#define DMA_COMMON_ERRINT_ERR5_SHIFT (5U) -/*! ERR5 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR5_SHIFT)) & DMA_COMMON_ERRINT_ERR5_MASK) - -#define DMA_COMMON_ERRINT_ERR6_MASK (0x40U) -#define DMA_COMMON_ERRINT_ERR6_SHIFT (6U) -/*! ERR6 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR6_SHIFT)) & DMA_COMMON_ERRINT_ERR6_MASK) - -#define DMA_COMMON_ERRINT_ERR7_MASK (0x80U) -#define DMA_COMMON_ERRINT_ERR7_SHIFT (7U) -/*! ERR7 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR7_SHIFT)) & DMA_COMMON_ERRINT_ERR7_MASK) - -#define DMA_COMMON_ERRINT_ERR8_MASK (0x100U) -#define DMA_COMMON_ERRINT_ERR8_SHIFT (8U) -/*! ERR8 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR8_SHIFT)) & DMA_COMMON_ERRINT_ERR8_MASK) - -#define DMA_COMMON_ERRINT_ERR9_MASK (0x200U) -#define DMA_COMMON_ERRINT_ERR9_SHIFT (9U) -/*! ERR9 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR9_SHIFT)) & DMA_COMMON_ERRINT_ERR9_MASK) - -#define DMA_COMMON_ERRINT_ERR10_MASK (0x400U) -#define DMA_COMMON_ERRINT_ERR10_SHIFT (10U) -/*! ERR10 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR10_SHIFT)) & DMA_COMMON_ERRINT_ERR10_MASK) - -#define DMA_COMMON_ERRINT_ERR11_MASK (0x800U) -#define DMA_COMMON_ERRINT_ERR11_SHIFT (11U) -/*! ERR11 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR11_SHIFT)) & DMA_COMMON_ERRINT_ERR11_MASK) - -#define DMA_COMMON_ERRINT_ERR12_MASK (0x1000U) -#define DMA_COMMON_ERRINT_ERR12_SHIFT (12U) -/*! ERR12 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR12_SHIFT)) & DMA_COMMON_ERRINT_ERR12_MASK) - -#define DMA_COMMON_ERRINT_ERR13_MASK (0x2000U) -#define DMA_COMMON_ERRINT_ERR13_SHIFT (13U) -/*! ERR13 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR13_SHIFT)) & DMA_COMMON_ERRINT_ERR13_MASK) - -#define DMA_COMMON_ERRINT_ERR14_MASK (0x4000U) -#define DMA_COMMON_ERRINT_ERR14_SHIFT (14U) -/*! ERR14 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR14_SHIFT)) & DMA_COMMON_ERRINT_ERR14_MASK) - -#define DMA_COMMON_ERRINT_ERR15_MASK (0x8000U) -#define DMA_COMMON_ERRINT_ERR15_SHIFT (15U) -/*! ERR15 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR15_SHIFT)) & DMA_COMMON_ERRINT_ERR15_MASK) - -#define DMA_COMMON_ERRINT_ERR16_MASK (0x10000U) -#define DMA_COMMON_ERRINT_ERR16_SHIFT (16U) -/*! ERR16 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR16_SHIFT)) & DMA_COMMON_ERRINT_ERR16_MASK) - -#define DMA_COMMON_ERRINT_ERR17_MASK (0x20000U) -#define DMA_COMMON_ERRINT_ERR17_SHIFT (17U) -/*! ERR17 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR17_SHIFT)) & DMA_COMMON_ERRINT_ERR17_MASK) - -#define DMA_COMMON_ERRINT_ERR18_MASK (0x40000U) -#define DMA_COMMON_ERRINT_ERR18_SHIFT (18U) -/*! ERR18 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR18_SHIFT)) & DMA_COMMON_ERRINT_ERR18_MASK) - -#define DMA_COMMON_ERRINT_ERR19_MASK (0x80000U) -#define DMA_COMMON_ERRINT_ERR19_SHIFT (19U) -/*! ERR19 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR19_SHIFT)) & DMA_COMMON_ERRINT_ERR19_MASK) - -#define DMA_COMMON_ERRINT_ERR20_MASK (0x100000U) -#define DMA_COMMON_ERRINT_ERR20_SHIFT (20U) -/*! ERR20 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR20_SHIFT)) & DMA_COMMON_ERRINT_ERR20_MASK) - -#define DMA_COMMON_ERRINT_ERR21_MASK (0x200000U) -#define DMA_COMMON_ERRINT_ERR21_SHIFT (21U) -/*! ERR21 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR21_SHIFT)) & DMA_COMMON_ERRINT_ERR21_MASK) - -#define DMA_COMMON_ERRINT_ERR22_MASK (0x400000U) -#define DMA_COMMON_ERRINT_ERR22_SHIFT (22U) -/*! ERR22 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR22_SHIFT)) & DMA_COMMON_ERRINT_ERR22_MASK) - -#define DMA_COMMON_ERRINT_ERR23_MASK (0x800000U) -#define DMA_COMMON_ERRINT_ERR23_SHIFT (23U) -/*! ERR23 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR23_SHIFT)) & DMA_COMMON_ERRINT_ERR23_MASK) - -#define DMA_COMMON_ERRINT_ERR24_MASK (0x1000000U) -#define DMA_COMMON_ERRINT_ERR24_SHIFT (24U) -/*! ERR24 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR24_SHIFT)) & DMA_COMMON_ERRINT_ERR24_MASK) - -#define DMA_COMMON_ERRINT_ERR25_MASK (0x2000000U) -#define DMA_COMMON_ERRINT_ERR25_SHIFT (25U) -/*! ERR25 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR25_SHIFT)) & DMA_COMMON_ERRINT_ERR25_MASK) - -#define DMA_COMMON_ERRINT_ERR26_MASK (0x4000000U) -#define DMA_COMMON_ERRINT_ERR26_SHIFT (26U) -/*! ERR26 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR26_SHIFT)) & DMA_COMMON_ERRINT_ERR26_MASK) - -#define DMA_COMMON_ERRINT_ERR27_MASK (0x8000000U) -#define DMA_COMMON_ERRINT_ERR27_SHIFT (27U) -/*! ERR27 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR27_SHIFT)) & DMA_COMMON_ERRINT_ERR27_MASK) - -#define DMA_COMMON_ERRINT_ERR28_MASK (0x10000000U) -#define DMA_COMMON_ERRINT_ERR28_SHIFT (28U) -/*! ERR28 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR28_SHIFT)) & DMA_COMMON_ERRINT_ERR28_MASK) - -#define DMA_COMMON_ERRINT_ERR29_MASK (0x20000000U) -#define DMA_COMMON_ERRINT_ERR29_SHIFT (29U) -/*! ERR29 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR29_SHIFT)) & DMA_COMMON_ERRINT_ERR29_MASK) - -#define DMA_COMMON_ERRINT_ERR30_MASK (0x40000000U) -#define DMA_COMMON_ERRINT_ERR30_SHIFT (30U) -/*! ERR30 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR30_SHIFT)) & DMA_COMMON_ERRINT_ERR30_MASK) - -#define DMA_COMMON_ERRINT_ERR31_MASK (0x80000000U) -#define DMA_COMMON_ERRINT_ERR31_SHIFT (31U) -/*! ERR31 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR31_SHIFT)) & DMA_COMMON_ERRINT_ERR31_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ERRINT */ -#define DMA_COMMON_ERRINT_COUNT (1U) - -/*! @name COMMON_ERRINT1 - Error Interrupt status for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_ERRINT1_ERR32_MASK (0x1U) -#define DMA_COMMON_ERRINT1_ERR32_SHIFT (0U) -/*! ERR32 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT1_ERR32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR32_SHIFT)) & DMA_COMMON_ERRINT1_ERR32_MASK) - -#define DMA_COMMON_ERRINT1_ERR33_MASK (0x2U) -#define DMA_COMMON_ERRINT1_ERR33_SHIFT (1U) -/*! ERR33 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT1_ERR33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR33_SHIFT)) & DMA_COMMON_ERRINT1_ERR33_MASK) - -#define DMA_COMMON_ERRINT1_ERR34_MASK (0x4U) -#define DMA_COMMON_ERRINT1_ERR34_SHIFT (2U) -/*! ERR34 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT1_ERR34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR34_SHIFT)) & DMA_COMMON_ERRINT1_ERR34_MASK) - -#define DMA_COMMON_ERRINT1_ERR35_MASK (0x8U) -#define DMA_COMMON_ERRINT1_ERR35_SHIFT (3U) -/*! ERR35 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT1_ERR35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR35_SHIFT)) & DMA_COMMON_ERRINT1_ERR35_MASK) - -#define DMA_COMMON_ERRINT1_ERR36_MASK (0x10U) -#define DMA_COMMON_ERRINT1_ERR36_SHIFT (4U) -/*! ERR36 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT1_ERR36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR36_SHIFT)) & DMA_COMMON_ERRINT1_ERR36_MASK) - -#define DMA_COMMON_ERRINT1_ERR37_MASK (0x20U) -#define DMA_COMMON_ERRINT1_ERR37_SHIFT (5U) -/*! ERR37 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT1_ERR37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR37_SHIFT)) & DMA_COMMON_ERRINT1_ERR37_MASK) - -#define DMA_COMMON_ERRINT1_ERR38_MASK (0x40U) -#define DMA_COMMON_ERRINT1_ERR38_SHIFT (6U) -/*! ERR38 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT1_ERR38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR38_SHIFT)) & DMA_COMMON_ERRINT1_ERR38_MASK) - -#define DMA_COMMON_ERRINT1_ERR39_MASK (0x80U) -#define DMA_COMMON_ERRINT1_ERR39_SHIFT (7U) -/*! ERR39 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT1_ERR39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR39_SHIFT)) & DMA_COMMON_ERRINT1_ERR39_MASK) - -#define DMA_COMMON_ERRINT1_ERR40_MASK (0x100U) -#define DMA_COMMON_ERRINT1_ERR40_SHIFT (8U) -/*! ERR40 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT1_ERR40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR40_SHIFT)) & DMA_COMMON_ERRINT1_ERR40_MASK) - -#define DMA_COMMON_ERRINT1_ERR41_MASK (0x200U) -#define DMA_COMMON_ERRINT1_ERR41_SHIFT (9U) -/*! ERR41 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT1_ERR41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR41_SHIFT)) & DMA_COMMON_ERRINT1_ERR41_MASK) - -#define DMA_COMMON_ERRINT1_ERR42_MASK (0x400U) -#define DMA_COMMON_ERRINT1_ERR42_SHIFT (10U) -/*! ERR42 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT1_ERR42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR42_SHIFT)) & DMA_COMMON_ERRINT1_ERR42_MASK) - -#define DMA_COMMON_ERRINT1_ERR43_MASK (0x800U) -#define DMA_COMMON_ERRINT1_ERR43_SHIFT (11U) -/*! ERR43 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT1_ERR43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR43_SHIFT)) & DMA_COMMON_ERRINT1_ERR43_MASK) - -#define DMA_COMMON_ERRINT1_ERR44_MASK (0x1000U) -#define DMA_COMMON_ERRINT1_ERR44_SHIFT (12U) -/*! ERR44 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT1_ERR44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR44_SHIFT)) & DMA_COMMON_ERRINT1_ERR44_MASK) - -#define DMA_COMMON_ERRINT1_ERR45_MASK (0x2000U) -#define DMA_COMMON_ERRINT1_ERR45_SHIFT (13U) -/*! ERR45 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT1_ERR45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR45_SHIFT)) & DMA_COMMON_ERRINT1_ERR45_MASK) - -#define DMA_COMMON_ERRINT1_ERR46_MASK (0x4000U) -#define DMA_COMMON_ERRINT1_ERR46_SHIFT (14U) -/*! ERR46 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT1_ERR46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR46_SHIFT)) & DMA_COMMON_ERRINT1_ERR46_MASK) - -#define DMA_COMMON_ERRINT1_ERR47_MASK (0x8000U) -#define DMA_COMMON_ERRINT1_ERR47_SHIFT (15U) -/*! ERR47 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT1_ERR47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR47_SHIFT)) & DMA_COMMON_ERRINT1_ERR47_MASK) - -#define DMA_COMMON_ERRINT1_ERR48_MASK (0x10000U) -#define DMA_COMMON_ERRINT1_ERR48_SHIFT (16U) -/*! ERR48 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT1_ERR48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR48_SHIFT)) & DMA_COMMON_ERRINT1_ERR48_MASK) - -#define DMA_COMMON_ERRINT1_ERR49_MASK (0x20000U) -#define DMA_COMMON_ERRINT1_ERR49_SHIFT (17U) -/*! ERR49 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT1_ERR49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR49_SHIFT)) & DMA_COMMON_ERRINT1_ERR49_MASK) - -#define DMA_COMMON_ERRINT1_ERR50_MASK (0x40000U) -#define DMA_COMMON_ERRINT1_ERR50_SHIFT (18U) -/*! ERR50 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT1_ERR50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR50_SHIFT)) & DMA_COMMON_ERRINT1_ERR50_MASK) - -#define DMA_COMMON_ERRINT1_ERR51_MASK (0x80000U) -#define DMA_COMMON_ERRINT1_ERR51_SHIFT (19U) -/*! ERR51 - Error Interrupt flag for DMA channel. - * 0b0..The Error Interrupt is not active for DMA channel. - * 0b1..The Error Interrupt is pending for DMA channel. - */ -#define DMA_COMMON_ERRINT1_ERR51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR51_SHIFT)) & DMA_COMMON_ERRINT1_ERR51_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ERRINT1 */ -#define DMA_COMMON_ERRINT1_COUNT (1U) - -/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_INTENSET_INTEN0_MASK (0x1U) -#define DMA_COMMON_INTENSET_INTEN0_SHIFT (0U) -/*! INTEN0 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN0_SHIFT)) & DMA_COMMON_INTENSET_INTEN0_MASK) - -#define DMA_COMMON_INTENSET_INTEN1_MASK (0x2U) -#define DMA_COMMON_INTENSET_INTEN1_SHIFT (1U) -/*! INTEN1 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN1_SHIFT)) & DMA_COMMON_INTENSET_INTEN1_MASK) - -#define DMA_COMMON_INTENSET_INTEN2_MASK (0x4U) -#define DMA_COMMON_INTENSET_INTEN2_SHIFT (2U) -/*! INTEN2 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN2_SHIFT)) & DMA_COMMON_INTENSET_INTEN2_MASK) - -#define DMA_COMMON_INTENSET_INTEN3_MASK (0x8U) -#define DMA_COMMON_INTENSET_INTEN3_SHIFT (3U) -/*! INTEN3 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN3_SHIFT)) & DMA_COMMON_INTENSET_INTEN3_MASK) - -#define DMA_COMMON_INTENSET_INTEN4_MASK (0x10U) -#define DMA_COMMON_INTENSET_INTEN4_SHIFT (4U) -/*! INTEN4 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN4_SHIFT)) & DMA_COMMON_INTENSET_INTEN4_MASK) - -#define DMA_COMMON_INTENSET_INTEN5_MASK (0x20U) -#define DMA_COMMON_INTENSET_INTEN5_SHIFT (5U) -/*! INTEN5 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN5_SHIFT)) & DMA_COMMON_INTENSET_INTEN5_MASK) - -#define DMA_COMMON_INTENSET_INTEN6_MASK (0x40U) -#define DMA_COMMON_INTENSET_INTEN6_SHIFT (6U) -/*! INTEN6 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN6_SHIFT)) & DMA_COMMON_INTENSET_INTEN6_MASK) - -#define DMA_COMMON_INTENSET_INTEN7_MASK (0x80U) -#define DMA_COMMON_INTENSET_INTEN7_SHIFT (7U) -/*! INTEN7 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN7_SHIFT)) & DMA_COMMON_INTENSET_INTEN7_MASK) - -#define DMA_COMMON_INTENSET_INTEN8_MASK (0x100U) -#define DMA_COMMON_INTENSET_INTEN8_SHIFT (8U) -/*! INTEN8 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN8_SHIFT)) & DMA_COMMON_INTENSET_INTEN8_MASK) - -#define DMA_COMMON_INTENSET_INTEN9_MASK (0x200U) -#define DMA_COMMON_INTENSET_INTEN9_SHIFT (9U) -/*! INTEN9 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN9_SHIFT)) & DMA_COMMON_INTENSET_INTEN9_MASK) - -#define DMA_COMMON_INTENSET_INTEN10_MASK (0x400U) -#define DMA_COMMON_INTENSET_INTEN10_SHIFT (10U) -/*! INTEN10 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN10_SHIFT)) & DMA_COMMON_INTENSET_INTEN10_MASK) - -#define DMA_COMMON_INTENSET_INTEN11_MASK (0x800U) -#define DMA_COMMON_INTENSET_INTEN11_SHIFT (11U) -/*! INTEN11 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN11_SHIFT)) & DMA_COMMON_INTENSET_INTEN11_MASK) - -#define DMA_COMMON_INTENSET_INTEN12_MASK (0x1000U) -#define DMA_COMMON_INTENSET_INTEN12_SHIFT (12U) -/*! INTEN12 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN12_SHIFT)) & DMA_COMMON_INTENSET_INTEN12_MASK) - -#define DMA_COMMON_INTENSET_INTEN13_MASK (0x2000U) -#define DMA_COMMON_INTENSET_INTEN13_SHIFT (13U) -/*! INTEN13 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN13_SHIFT)) & DMA_COMMON_INTENSET_INTEN13_MASK) - -#define DMA_COMMON_INTENSET_INTEN14_MASK (0x4000U) -#define DMA_COMMON_INTENSET_INTEN14_SHIFT (14U) -/*! INTEN14 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN14_SHIFT)) & DMA_COMMON_INTENSET_INTEN14_MASK) - -#define DMA_COMMON_INTENSET_INTEN15_MASK (0x8000U) -#define DMA_COMMON_INTENSET_INTEN15_SHIFT (15U) -/*! INTEN15 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN15_SHIFT)) & DMA_COMMON_INTENSET_INTEN15_MASK) - -#define DMA_COMMON_INTENSET_INTEN16_MASK (0x10000U) -#define DMA_COMMON_INTENSET_INTEN16_SHIFT (16U) -/*! INTEN16 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN16_SHIFT)) & DMA_COMMON_INTENSET_INTEN16_MASK) - -#define DMA_COMMON_INTENSET_INTEN17_MASK (0x20000U) -#define DMA_COMMON_INTENSET_INTEN17_SHIFT (17U) -/*! INTEN17 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN17_SHIFT)) & DMA_COMMON_INTENSET_INTEN17_MASK) - -#define DMA_COMMON_INTENSET_INTEN18_MASK (0x40000U) -#define DMA_COMMON_INTENSET_INTEN18_SHIFT (18U) -/*! INTEN18 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN18_SHIFT)) & DMA_COMMON_INTENSET_INTEN18_MASK) - -#define DMA_COMMON_INTENSET_INTEN19_MASK (0x80000U) -#define DMA_COMMON_INTENSET_INTEN19_SHIFT (19U) -/*! INTEN19 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN19_SHIFT)) & DMA_COMMON_INTENSET_INTEN19_MASK) - -#define DMA_COMMON_INTENSET_INTEN20_MASK (0x100000U) -#define DMA_COMMON_INTENSET_INTEN20_SHIFT (20U) -/*! INTEN20 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN20_SHIFT)) & DMA_COMMON_INTENSET_INTEN20_MASK) - -#define DMA_COMMON_INTENSET_INTEN21_MASK (0x200000U) -#define DMA_COMMON_INTENSET_INTEN21_SHIFT (21U) -/*! INTEN21 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN21_SHIFT)) & DMA_COMMON_INTENSET_INTEN21_MASK) - -#define DMA_COMMON_INTENSET_INTEN22_MASK (0x400000U) -#define DMA_COMMON_INTENSET_INTEN22_SHIFT (22U) -/*! INTEN22 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN22_SHIFT)) & DMA_COMMON_INTENSET_INTEN22_MASK) - -#define DMA_COMMON_INTENSET_INTEN23_MASK (0x800000U) -#define DMA_COMMON_INTENSET_INTEN23_SHIFT (23U) -/*! INTEN23 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN23_SHIFT)) & DMA_COMMON_INTENSET_INTEN23_MASK) - -#define DMA_COMMON_INTENSET_INTEN24_MASK (0x1000000U) -#define DMA_COMMON_INTENSET_INTEN24_SHIFT (24U) -/*! INTEN24 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN24_SHIFT)) & DMA_COMMON_INTENSET_INTEN24_MASK) - -#define DMA_COMMON_INTENSET_INTEN25_MASK (0x2000000U) -#define DMA_COMMON_INTENSET_INTEN25_SHIFT (25U) -/*! INTEN25 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN25_SHIFT)) & DMA_COMMON_INTENSET_INTEN25_MASK) - -#define DMA_COMMON_INTENSET_INTEN26_MASK (0x4000000U) -#define DMA_COMMON_INTENSET_INTEN26_SHIFT (26U) -/*! INTEN26 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN26_SHIFT)) & DMA_COMMON_INTENSET_INTEN26_MASK) - -#define DMA_COMMON_INTENSET_INTEN27_MASK (0x8000000U) -#define DMA_COMMON_INTENSET_INTEN27_SHIFT (27U) -/*! INTEN27 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN27_SHIFT)) & DMA_COMMON_INTENSET_INTEN27_MASK) - -#define DMA_COMMON_INTENSET_INTEN28_MASK (0x10000000U) -#define DMA_COMMON_INTENSET_INTEN28_SHIFT (28U) -/*! INTEN28 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN28_SHIFT)) & DMA_COMMON_INTENSET_INTEN28_MASK) - -#define DMA_COMMON_INTENSET_INTEN29_MASK (0x20000000U) -#define DMA_COMMON_INTENSET_INTEN29_SHIFT (29U) -/*! INTEN29 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN29_SHIFT)) & DMA_COMMON_INTENSET_INTEN29_MASK) - -#define DMA_COMMON_INTENSET_INTEN30_MASK (0x40000000U) -#define DMA_COMMON_INTENSET_INTEN30_SHIFT (30U) -/*! INTEN30 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN30_SHIFT)) & DMA_COMMON_INTENSET_INTEN30_MASK) - -#define DMA_COMMON_INTENSET_INTEN31_MASK (0x80000000U) -#define DMA_COMMON_INTENSET_INTEN31_SHIFT (31U) -/*! INTEN31 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN31_SHIFT)) & DMA_COMMON_INTENSET_INTEN31_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENSET */ -#define DMA_COMMON_INTENSET_COUNT (1U) - -/*! @name COMMON_INTENSET1 - Interrupt Enable read and Set for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_INTENSET1_INTEN32_MASK (0x1U) -#define DMA_COMMON_INTENSET1_INTEN32_SHIFT (0U) -/*! INTEN32 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET1_INTEN32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN32_SHIFT)) & DMA_COMMON_INTENSET1_INTEN32_MASK) - -#define DMA_COMMON_INTENSET1_INTEN33_MASK (0x2U) -#define DMA_COMMON_INTENSET1_INTEN33_SHIFT (1U) -/*! INTEN33 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET1_INTEN33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN33_SHIFT)) & DMA_COMMON_INTENSET1_INTEN33_MASK) - -#define DMA_COMMON_INTENSET1_INTEN34_MASK (0x4U) -#define DMA_COMMON_INTENSET1_INTEN34_SHIFT (2U) -/*! INTEN34 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET1_INTEN34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN34_SHIFT)) & DMA_COMMON_INTENSET1_INTEN34_MASK) - -#define DMA_COMMON_INTENSET1_INTEN35_MASK (0x8U) -#define DMA_COMMON_INTENSET1_INTEN35_SHIFT (3U) -/*! INTEN35 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET1_INTEN35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN35_SHIFT)) & DMA_COMMON_INTENSET1_INTEN35_MASK) - -#define DMA_COMMON_INTENSET1_INTEN36_MASK (0x10U) -#define DMA_COMMON_INTENSET1_INTEN36_SHIFT (4U) -/*! INTEN36 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET1_INTEN36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN36_SHIFT)) & DMA_COMMON_INTENSET1_INTEN36_MASK) - -#define DMA_COMMON_INTENSET1_INTEN37_MASK (0x20U) -#define DMA_COMMON_INTENSET1_INTEN37_SHIFT (5U) -/*! INTEN37 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET1_INTEN37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN37_SHIFT)) & DMA_COMMON_INTENSET1_INTEN37_MASK) - -#define DMA_COMMON_INTENSET1_INTEN38_MASK (0x40U) -#define DMA_COMMON_INTENSET1_INTEN38_SHIFT (6U) -/*! INTEN38 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET1_INTEN38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN38_SHIFT)) & DMA_COMMON_INTENSET1_INTEN38_MASK) - -#define DMA_COMMON_INTENSET1_INTEN39_MASK (0x80U) -#define DMA_COMMON_INTENSET1_INTEN39_SHIFT (7U) -/*! INTEN39 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET1_INTEN39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN39_SHIFT)) & DMA_COMMON_INTENSET1_INTEN39_MASK) - -#define DMA_COMMON_INTENSET1_INTEN40_MASK (0x100U) -#define DMA_COMMON_INTENSET1_INTEN40_SHIFT (8U) -/*! INTEN40 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET1_INTEN40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN40_SHIFT)) & DMA_COMMON_INTENSET1_INTEN40_MASK) - -#define DMA_COMMON_INTENSET1_INTEN41_MASK (0x200U) -#define DMA_COMMON_INTENSET1_INTEN41_SHIFT (9U) -/*! INTEN41 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET1_INTEN41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN41_SHIFT)) & DMA_COMMON_INTENSET1_INTEN41_MASK) - -#define DMA_COMMON_INTENSET1_INTEN42_MASK (0x400U) -#define DMA_COMMON_INTENSET1_INTEN42_SHIFT (10U) -/*! INTEN42 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET1_INTEN42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN42_SHIFT)) & DMA_COMMON_INTENSET1_INTEN42_MASK) - -#define DMA_COMMON_INTENSET1_INTEN43_MASK (0x800U) -#define DMA_COMMON_INTENSET1_INTEN43_SHIFT (11U) -/*! INTEN43 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET1_INTEN43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN43_SHIFT)) & DMA_COMMON_INTENSET1_INTEN43_MASK) - -#define DMA_COMMON_INTENSET1_INTEN44_MASK (0x1000U) -#define DMA_COMMON_INTENSET1_INTEN44_SHIFT (12U) -/*! INTEN44 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET1_INTEN44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN44_SHIFT)) & DMA_COMMON_INTENSET1_INTEN44_MASK) - -#define DMA_COMMON_INTENSET1_INTEN45_MASK (0x2000U) -#define DMA_COMMON_INTENSET1_INTEN45_SHIFT (13U) -/*! INTEN45 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET1_INTEN45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN45_SHIFT)) & DMA_COMMON_INTENSET1_INTEN45_MASK) - -#define DMA_COMMON_INTENSET1_INTEN46_MASK (0x4000U) -#define DMA_COMMON_INTENSET1_INTEN46_SHIFT (14U) -/*! INTEN46 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET1_INTEN46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN46_SHIFT)) & DMA_COMMON_INTENSET1_INTEN46_MASK) - -#define DMA_COMMON_INTENSET1_INTEN47_MASK (0x8000U) -#define DMA_COMMON_INTENSET1_INTEN47_SHIFT (15U) -/*! INTEN47 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET1_INTEN47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN47_SHIFT)) & DMA_COMMON_INTENSET1_INTEN47_MASK) - -#define DMA_COMMON_INTENSET1_INTEN48_MASK (0x10000U) -#define DMA_COMMON_INTENSET1_INTEN48_SHIFT (16U) -/*! INTEN48 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET1_INTEN48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN48_SHIFT)) & DMA_COMMON_INTENSET1_INTEN48_MASK) - -#define DMA_COMMON_INTENSET1_INTEN49_MASK (0x20000U) -#define DMA_COMMON_INTENSET1_INTEN49_SHIFT (17U) -/*! INTEN49 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET1_INTEN49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN49_SHIFT)) & DMA_COMMON_INTENSET1_INTEN49_MASK) - -#define DMA_COMMON_INTENSET1_INTEN50_MASK (0x40000U) -#define DMA_COMMON_INTENSET1_INTEN50_SHIFT (18U) -/*! INTEN50 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET1_INTEN50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN50_SHIFT)) & DMA_COMMON_INTENSET1_INTEN50_MASK) - -#define DMA_COMMON_INTENSET1_INTEN51_MASK (0x80000U) -#define DMA_COMMON_INTENSET1_INTEN51_SHIFT (19U) -/*! INTEN51 - Interrupt Enable read and set for DMA channel. - * 0b0..The Interrupt for DMA channel is disabled. - * 0b1..The Interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET1_INTEN51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN51_SHIFT)) & DMA_COMMON_INTENSET1_INTEN51_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENSET1 */ -#define DMA_COMMON_INTENSET1_COUNT (1U) - -/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_INTENCLR_CLR0_MASK (0x1U) -#define DMA_COMMON_INTENCLR_CLR0_SHIFT (0U) -/*! CLR0 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR0_SHIFT)) & DMA_COMMON_INTENCLR_CLR0_MASK) - -#define DMA_COMMON_INTENCLR_CLR1_MASK (0x2U) -#define DMA_COMMON_INTENCLR_CLR1_SHIFT (1U) -/*! CLR1 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR1_SHIFT)) & DMA_COMMON_INTENCLR_CLR1_MASK) - -#define DMA_COMMON_INTENCLR_CLR2_MASK (0x4U) -#define DMA_COMMON_INTENCLR_CLR2_SHIFT (2U) -/*! CLR2 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR2_SHIFT)) & DMA_COMMON_INTENCLR_CLR2_MASK) - -#define DMA_COMMON_INTENCLR_CLR3_MASK (0x8U) -#define DMA_COMMON_INTENCLR_CLR3_SHIFT (3U) -/*! CLR3 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR3_SHIFT)) & DMA_COMMON_INTENCLR_CLR3_MASK) - -#define DMA_COMMON_INTENCLR_CLR4_MASK (0x10U) -#define DMA_COMMON_INTENCLR_CLR4_SHIFT (4U) -/*! CLR4 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR4_SHIFT)) & DMA_COMMON_INTENCLR_CLR4_MASK) - -#define DMA_COMMON_INTENCLR_CLR5_MASK (0x20U) -#define DMA_COMMON_INTENCLR_CLR5_SHIFT (5U) -/*! CLR5 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR5_SHIFT)) & DMA_COMMON_INTENCLR_CLR5_MASK) - -#define DMA_COMMON_INTENCLR_CLR6_MASK (0x40U) -#define DMA_COMMON_INTENCLR_CLR6_SHIFT (6U) -/*! CLR6 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR6_SHIFT)) & DMA_COMMON_INTENCLR_CLR6_MASK) - -#define DMA_COMMON_INTENCLR_CLR7_MASK (0x80U) -#define DMA_COMMON_INTENCLR_CLR7_SHIFT (7U) -/*! CLR7 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR7_SHIFT)) & DMA_COMMON_INTENCLR_CLR7_MASK) - -#define DMA_COMMON_INTENCLR_CLR8_MASK (0x100U) -#define DMA_COMMON_INTENCLR_CLR8_SHIFT (8U) -/*! CLR8 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR8_SHIFT)) & DMA_COMMON_INTENCLR_CLR8_MASK) - -#define DMA_COMMON_INTENCLR_CLR9_MASK (0x200U) -#define DMA_COMMON_INTENCLR_CLR9_SHIFT (9U) -/*! CLR9 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR9_SHIFT)) & DMA_COMMON_INTENCLR_CLR9_MASK) - -#define DMA_COMMON_INTENCLR_CLR10_MASK (0x400U) -#define DMA_COMMON_INTENCLR_CLR10_SHIFT (10U) -/*! CLR10 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR10_SHIFT)) & DMA_COMMON_INTENCLR_CLR10_MASK) - -#define DMA_COMMON_INTENCLR_CLR11_MASK (0x800U) -#define DMA_COMMON_INTENCLR_CLR11_SHIFT (11U) -/*! CLR11 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR11_SHIFT)) & DMA_COMMON_INTENCLR_CLR11_MASK) - -#define DMA_COMMON_INTENCLR_CLR12_MASK (0x1000U) -#define DMA_COMMON_INTENCLR_CLR12_SHIFT (12U) -/*! CLR12 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR12_SHIFT)) & DMA_COMMON_INTENCLR_CLR12_MASK) - -#define DMA_COMMON_INTENCLR_CLR13_MASK (0x2000U) -#define DMA_COMMON_INTENCLR_CLR13_SHIFT (13U) -/*! CLR13 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR13_SHIFT)) & DMA_COMMON_INTENCLR_CLR13_MASK) - -#define DMA_COMMON_INTENCLR_CLR14_MASK (0x4000U) -#define DMA_COMMON_INTENCLR_CLR14_SHIFT (14U) -/*! CLR14 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR14_SHIFT)) & DMA_COMMON_INTENCLR_CLR14_MASK) - -#define DMA_COMMON_INTENCLR_CLR15_MASK (0x8000U) -#define DMA_COMMON_INTENCLR_CLR15_SHIFT (15U) -/*! CLR15 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR15_SHIFT)) & DMA_COMMON_INTENCLR_CLR15_MASK) - -#define DMA_COMMON_INTENCLR_CLR16_MASK (0x10000U) -#define DMA_COMMON_INTENCLR_CLR16_SHIFT (16U) -/*! CLR16 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR16_SHIFT)) & DMA_COMMON_INTENCLR_CLR16_MASK) - -#define DMA_COMMON_INTENCLR_CLR17_MASK (0x20000U) -#define DMA_COMMON_INTENCLR_CLR17_SHIFT (17U) -/*! CLR17 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR17_SHIFT)) & DMA_COMMON_INTENCLR_CLR17_MASK) - -#define DMA_COMMON_INTENCLR_CLR18_MASK (0x40000U) -#define DMA_COMMON_INTENCLR_CLR18_SHIFT (18U) -/*! CLR18 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR18_SHIFT)) & DMA_COMMON_INTENCLR_CLR18_MASK) - -#define DMA_COMMON_INTENCLR_CLR19_MASK (0x80000U) -#define DMA_COMMON_INTENCLR_CLR19_SHIFT (19U) -/*! CLR19 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR19_SHIFT)) & DMA_COMMON_INTENCLR_CLR19_MASK) - -#define DMA_COMMON_INTENCLR_CLR20_MASK (0x100000U) -#define DMA_COMMON_INTENCLR_CLR20_SHIFT (20U) -/*! CLR20 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR20_SHIFT)) & DMA_COMMON_INTENCLR_CLR20_MASK) - -#define DMA_COMMON_INTENCLR_CLR21_MASK (0x200000U) -#define DMA_COMMON_INTENCLR_CLR21_SHIFT (21U) -/*! CLR21 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR21_SHIFT)) & DMA_COMMON_INTENCLR_CLR21_MASK) - -#define DMA_COMMON_INTENCLR_CLR22_MASK (0x400000U) -#define DMA_COMMON_INTENCLR_CLR22_SHIFT (22U) -/*! CLR22 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR22_SHIFT)) & DMA_COMMON_INTENCLR_CLR22_MASK) - -#define DMA_COMMON_INTENCLR_CLR23_MASK (0x800000U) -#define DMA_COMMON_INTENCLR_CLR23_SHIFT (23U) -/*! CLR23 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR23_SHIFT)) & DMA_COMMON_INTENCLR_CLR23_MASK) - -#define DMA_COMMON_INTENCLR_CLR24_MASK (0x1000000U) -#define DMA_COMMON_INTENCLR_CLR24_SHIFT (24U) -/*! CLR24 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR24_SHIFT)) & DMA_COMMON_INTENCLR_CLR24_MASK) - -#define DMA_COMMON_INTENCLR_CLR25_MASK (0x2000000U) -#define DMA_COMMON_INTENCLR_CLR25_SHIFT (25U) -/*! CLR25 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR25_SHIFT)) & DMA_COMMON_INTENCLR_CLR25_MASK) - -#define DMA_COMMON_INTENCLR_CLR26_MASK (0x4000000U) -#define DMA_COMMON_INTENCLR_CLR26_SHIFT (26U) -/*! CLR26 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR26_SHIFT)) & DMA_COMMON_INTENCLR_CLR26_MASK) - -#define DMA_COMMON_INTENCLR_CLR27_MASK (0x8000000U) -#define DMA_COMMON_INTENCLR_CLR27_SHIFT (27U) -/*! CLR27 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR27_SHIFT)) & DMA_COMMON_INTENCLR_CLR27_MASK) - -#define DMA_COMMON_INTENCLR_CLR28_MASK (0x10000000U) -#define DMA_COMMON_INTENCLR_CLR28_SHIFT (28U) -/*! CLR28 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR28_SHIFT)) & DMA_COMMON_INTENCLR_CLR28_MASK) - -#define DMA_COMMON_INTENCLR_CLR29_MASK (0x20000000U) -#define DMA_COMMON_INTENCLR_CLR29_SHIFT (29U) -/*! CLR29 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR29_SHIFT)) & DMA_COMMON_INTENCLR_CLR29_MASK) - -#define DMA_COMMON_INTENCLR_CLR30_MASK (0x40000000U) -#define DMA_COMMON_INTENCLR_CLR30_SHIFT (30U) -/*! CLR30 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR30_SHIFT)) & DMA_COMMON_INTENCLR_CLR30_MASK) - -#define DMA_COMMON_INTENCLR_CLR31_MASK (0x80000000U) -#define DMA_COMMON_INTENCLR_CLR31_SHIFT (31U) -/*! CLR31 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. - */ -#define DMA_COMMON_INTENCLR_CLR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR31_SHIFT)) & DMA_COMMON_INTENCLR_CLR31_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENCLR */ -#define DMA_COMMON_INTENCLR_COUNT (1U) - -/*! @name COMMON_INTENCLR1 - Interrupt Enable Clear for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_INTENCLR1_CLR32_MASK (0x1U) -#define DMA_COMMON_INTENCLR1_CLR32_SHIFT (0U) -/*! CLR32 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. - */ -#define DMA_COMMON_INTENCLR1_CLR32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR32_SHIFT)) & DMA_COMMON_INTENCLR1_CLR32_MASK) - -#define DMA_COMMON_INTENCLR1_CLR33_MASK (0x2U) -#define DMA_COMMON_INTENCLR1_CLR33_SHIFT (1U) -/*! CLR33 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. - */ -#define DMA_COMMON_INTENCLR1_CLR33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR33_SHIFT)) & DMA_COMMON_INTENCLR1_CLR33_MASK) - -#define DMA_COMMON_INTENCLR1_CLR34_MASK (0x4U) -#define DMA_COMMON_INTENCLR1_CLR34_SHIFT (2U) -/*! CLR34 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. - */ -#define DMA_COMMON_INTENCLR1_CLR34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR34_SHIFT)) & DMA_COMMON_INTENCLR1_CLR34_MASK) - -#define DMA_COMMON_INTENCLR1_CLR35_MASK (0x8U) -#define DMA_COMMON_INTENCLR1_CLR35_SHIFT (3U) -/*! CLR35 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. - */ -#define DMA_COMMON_INTENCLR1_CLR35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR35_SHIFT)) & DMA_COMMON_INTENCLR1_CLR35_MASK) - -#define DMA_COMMON_INTENCLR1_CLR36_MASK (0x10U) -#define DMA_COMMON_INTENCLR1_CLR36_SHIFT (4U) -/*! CLR36 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. - */ -#define DMA_COMMON_INTENCLR1_CLR36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR36_SHIFT)) & DMA_COMMON_INTENCLR1_CLR36_MASK) - -#define DMA_COMMON_INTENCLR1_CLR37_MASK (0x20U) -#define DMA_COMMON_INTENCLR1_CLR37_SHIFT (5U) -/*! CLR37 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. - */ -#define DMA_COMMON_INTENCLR1_CLR37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR37_SHIFT)) & DMA_COMMON_INTENCLR1_CLR37_MASK) - -#define DMA_COMMON_INTENCLR1_CLR38_MASK (0x40U) -#define DMA_COMMON_INTENCLR1_CLR38_SHIFT (6U) -/*! CLR38 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. - */ -#define DMA_COMMON_INTENCLR1_CLR38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR38_SHIFT)) & DMA_COMMON_INTENCLR1_CLR38_MASK) - -#define DMA_COMMON_INTENCLR1_CLR39_MASK (0x80U) -#define DMA_COMMON_INTENCLR1_CLR39_SHIFT (7U) -/*! CLR39 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. - */ -#define DMA_COMMON_INTENCLR1_CLR39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR39_SHIFT)) & DMA_COMMON_INTENCLR1_CLR39_MASK) - -#define DMA_COMMON_INTENCLR1_CLR40_MASK (0x100U) -#define DMA_COMMON_INTENCLR1_CLR40_SHIFT (8U) -/*! CLR40 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. - */ -#define DMA_COMMON_INTENCLR1_CLR40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR40_SHIFT)) & DMA_COMMON_INTENCLR1_CLR40_MASK) - -#define DMA_COMMON_INTENCLR1_CLR41_MASK (0x200U) -#define DMA_COMMON_INTENCLR1_CLR41_SHIFT (9U) -/*! CLR41 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. - */ -#define DMA_COMMON_INTENCLR1_CLR41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR41_SHIFT)) & DMA_COMMON_INTENCLR1_CLR41_MASK) - -#define DMA_COMMON_INTENCLR1_CLR42_MASK (0x400U) -#define DMA_COMMON_INTENCLR1_CLR42_SHIFT (10U) -/*! CLR42 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. - */ -#define DMA_COMMON_INTENCLR1_CLR42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR42_SHIFT)) & DMA_COMMON_INTENCLR1_CLR42_MASK) - -#define DMA_COMMON_INTENCLR1_CLR43_MASK (0x800U) -#define DMA_COMMON_INTENCLR1_CLR43_SHIFT (11U) -/*! CLR43 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. - */ -#define DMA_COMMON_INTENCLR1_CLR43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR43_SHIFT)) & DMA_COMMON_INTENCLR1_CLR43_MASK) - -#define DMA_COMMON_INTENCLR1_CLR44_MASK (0x1000U) -#define DMA_COMMON_INTENCLR1_CLR44_SHIFT (12U) -/*! CLR44 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. - */ -#define DMA_COMMON_INTENCLR1_CLR44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR44_SHIFT)) & DMA_COMMON_INTENCLR1_CLR44_MASK) - -#define DMA_COMMON_INTENCLR1_CLR45_MASK (0x2000U) -#define DMA_COMMON_INTENCLR1_CLR45_SHIFT (13U) -/*! CLR45 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. - */ -#define DMA_COMMON_INTENCLR1_CLR45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR45_SHIFT)) & DMA_COMMON_INTENCLR1_CLR45_MASK) - -#define DMA_COMMON_INTENCLR1_CLR46_MASK (0x4000U) -#define DMA_COMMON_INTENCLR1_CLR46_SHIFT (14U) -/*! CLR46 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. - */ -#define DMA_COMMON_INTENCLR1_CLR46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR46_SHIFT)) & DMA_COMMON_INTENCLR1_CLR46_MASK) - -#define DMA_COMMON_INTENCLR1_CLR47_MASK (0x8000U) -#define DMA_COMMON_INTENCLR1_CLR47_SHIFT (15U) -/*! CLR47 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. - */ -#define DMA_COMMON_INTENCLR1_CLR47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR47_SHIFT)) & DMA_COMMON_INTENCLR1_CLR47_MASK) - -#define DMA_COMMON_INTENCLR1_CLR48_MASK (0x10000U) -#define DMA_COMMON_INTENCLR1_CLR48_SHIFT (16U) -/*! CLR48 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. - */ -#define DMA_COMMON_INTENCLR1_CLR48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR48_SHIFT)) & DMA_COMMON_INTENCLR1_CLR48_MASK) - -#define DMA_COMMON_INTENCLR1_CLR49_MASK (0x20000U) -#define DMA_COMMON_INTENCLR1_CLR49_SHIFT (17U) -/*! CLR49 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. - */ -#define DMA_COMMON_INTENCLR1_CLR49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR49_SHIFT)) & DMA_COMMON_INTENCLR1_CLR49_MASK) - -#define DMA_COMMON_INTENCLR1_CLR50_MASK (0x40000U) -#define DMA_COMMON_INTENCLR1_CLR50_SHIFT (18U) -/*! CLR50 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. - */ -#define DMA_COMMON_INTENCLR1_CLR50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR50_SHIFT)) & DMA_COMMON_INTENCLR1_CLR50_MASK) - -#define DMA_COMMON_INTENCLR1_CLR51_MASK (0x80000U) -#define DMA_COMMON_INTENCLR1_CLR51_SHIFT (19U) -/*! CLR51 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. - */ -#define DMA_COMMON_INTENCLR1_CLR51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR51_SHIFT)) & DMA_COMMON_INTENCLR1_CLR51_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENCLR1 */ -#define DMA_COMMON_INTENCLR1_COUNT (1U) - -/*! @name COMMON_INTA - Interrupt A status for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_INTA_INTA0_MASK (0x1U) -#define DMA_COMMON_INTA_INTA0_SHIFT (0U) -/*! INTA0 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA0_SHIFT)) & DMA_COMMON_INTA_INTA0_MASK) - -#define DMA_COMMON_INTA_INTA1_MASK (0x2U) -#define DMA_COMMON_INTA_INTA1_SHIFT (1U) -/*! INTA1 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA1_SHIFT)) & DMA_COMMON_INTA_INTA1_MASK) - -#define DMA_COMMON_INTA_INTA2_MASK (0x4U) -#define DMA_COMMON_INTA_INTA2_SHIFT (2U) -/*! INTA2 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA2_SHIFT)) & DMA_COMMON_INTA_INTA2_MASK) - -#define DMA_COMMON_INTA_INTA3_MASK (0x8U) -#define DMA_COMMON_INTA_INTA3_SHIFT (3U) -/*! INTA3 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA3_SHIFT)) & DMA_COMMON_INTA_INTA3_MASK) - -#define DMA_COMMON_INTA_INTA4_MASK (0x10U) -#define DMA_COMMON_INTA_INTA4_SHIFT (4U) -/*! INTA4 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA4_SHIFT)) & DMA_COMMON_INTA_INTA4_MASK) - -#define DMA_COMMON_INTA_INTA5_MASK (0x20U) -#define DMA_COMMON_INTA_INTA5_SHIFT (5U) -/*! INTA5 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA5_SHIFT)) & DMA_COMMON_INTA_INTA5_MASK) - -#define DMA_COMMON_INTA_INTA6_MASK (0x40U) -#define DMA_COMMON_INTA_INTA6_SHIFT (6U) -/*! INTA6 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA6_SHIFT)) & DMA_COMMON_INTA_INTA6_MASK) - -#define DMA_COMMON_INTA_INTA7_MASK (0x80U) -#define DMA_COMMON_INTA_INTA7_SHIFT (7U) -/*! INTA7 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA7_SHIFT)) & DMA_COMMON_INTA_INTA7_MASK) - -#define DMA_COMMON_INTA_INTA8_MASK (0x100U) -#define DMA_COMMON_INTA_INTA8_SHIFT (8U) -/*! INTA8 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA8_SHIFT)) & DMA_COMMON_INTA_INTA8_MASK) - -#define DMA_COMMON_INTA_INTA9_MASK (0x200U) -#define DMA_COMMON_INTA_INTA9_SHIFT (9U) -/*! INTA9 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA9_SHIFT)) & DMA_COMMON_INTA_INTA9_MASK) - -#define DMA_COMMON_INTA_INTA10_MASK (0x400U) -#define DMA_COMMON_INTA_INTA10_SHIFT (10U) -/*! INTA10 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA10_SHIFT)) & DMA_COMMON_INTA_INTA10_MASK) - -#define DMA_COMMON_INTA_INTA11_MASK (0x800U) -#define DMA_COMMON_INTA_INTA11_SHIFT (11U) -/*! INTA11 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA11_SHIFT)) & DMA_COMMON_INTA_INTA11_MASK) - -#define DMA_COMMON_INTA_INTA12_MASK (0x1000U) -#define DMA_COMMON_INTA_INTA12_SHIFT (12U) -/*! INTA12 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA12_SHIFT)) & DMA_COMMON_INTA_INTA12_MASK) - -#define DMA_COMMON_INTA_INTA13_MASK (0x2000U) -#define DMA_COMMON_INTA_INTA13_SHIFT (13U) -/*! INTA13 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA13_SHIFT)) & DMA_COMMON_INTA_INTA13_MASK) - -#define DMA_COMMON_INTA_INTA14_MASK (0x4000U) -#define DMA_COMMON_INTA_INTA14_SHIFT (14U) -/*! INTA14 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA14_SHIFT)) & DMA_COMMON_INTA_INTA14_MASK) - -#define DMA_COMMON_INTA_INTA15_MASK (0x8000U) -#define DMA_COMMON_INTA_INTA15_SHIFT (15U) -/*! INTA15 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA15_SHIFT)) & DMA_COMMON_INTA_INTA15_MASK) - -#define DMA_COMMON_INTA_INTA16_MASK (0x10000U) -#define DMA_COMMON_INTA_INTA16_SHIFT (16U) -/*! INTA16 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA16_SHIFT)) & DMA_COMMON_INTA_INTA16_MASK) - -#define DMA_COMMON_INTA_INTA17_MASK (0x20000U) -#define DMA_COMMON_INTA_INTA17_SHIFT (17U) -/*! INTA17 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA17_SHIFT)) & DMA_COMMON_INTA_INTA17_MASK) - -#define DMA_COMMON_INTA_INTA18_MASK (0x40000U) -#define DMA_COMMON_INTA_INTA18_SHIFT (18U) -/*! INTA18 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA18_SHIFT)) & DMA_COMMON_INTA_INTA18_MASK) - -#define DMA_COMMON_INTA_INTA19_MASK (0x80000U) -#define DMA_COMMON_INTA_INTA19_SHIFT (19U) -/*! INTA19 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA19_SHIFT)) & DMA_COMMON_INTA_INTA19_MASK) - -#define DMA_COMMON_INTA_INTA20_MASK (0x100000U) -#define DMA_COMMON_INTA_INTA20_SHIFT (20U) -/*! INTA20 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA20_SHIFT)) & DMA_COMMON_INTA_INTA20_MASK) - -#define DMA_COMMON_INTA_INTA21_MASK (0x200000U) -#define DMA_COMMON_INTA_INTA21_SHIFT (21U) -/*! INTA21 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA21_SHIFT)) & DMA_COMMON_INTA_INTA21_MASK) - -#define DMA_COMMON_INTA_INTA22_MASK (0x400000U) -#define DMA_COMMON_INTA_INTA22_SHIFT (22U) -/*! INTA22 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA22_SHIFT)) & DMA_COMMON_INTA_INTA22_MASK) - -#define DMA_COMMON_INTA_INTA23_MASK (0x800000U) -#define DMA_COMMON_INTA_INTA23_SHIFT (23U) -/*! INTA23 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA23_SHIFT)) & DMA_COMMON_INTA_INTA23_MASK) - -#define DMA_COMMON_INTA_INTA24_MASK (0x1000000U) -#define DMA_COMMON_INTA_INTA24_SHIFT (24U) -/*! INTA24 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA24_SHIFT)) & DMA_COMMON_INTA_INTA24_MASK) - -#define DMA_COMMON_INTA_INTA25_MASK (0x2000000U) -#define DMA_COMMON_INTA_INTA25_SHIFT (25U) -/*! INTA25 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA25_SHIFT)) & DMA_COMMON_INTA_INTA25_MASK) - -#define DMA_COMMON_INTA_INTA26_MASK (0x4000000U) -#define DMA_COMMON_INTA_INTA26_SHIFT (26U) -/*! INTA26 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA26_SHIFT)) & DMA_COMMON_INTA_INTA26_MASK) - -#define DMA_COMMON_INTA_INTA27_MASK (0x8000000U) -#define DMA_COMMON_INTA_INTA27_SHIFT (27U) -/*! INTA27 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA27_SHIFT)) & DMA_COMMON_INTA_INTA27_MASK) - -#define DMA_COMMON_INTA_INTA28_MASK (0x10000000U) -#define DMA_COMMON_INTA_INTA28_SHIFT (28U) -/*! INTA28 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA28_SHIFT)) & DMA_COMMON_INTA_INTA28_MASK) - -#define DMA_COMMON_INTA_INTA29_MASK (0x20000000U) -#define DMA_COMMON_INTA_INTA29_SHIFT (29U) -/*! INTA29 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA29_SHIFT)) & DMA_COMMON_INTA_INTA29_MASK) - -#define DMA_COMMON_INTA_INTA30_MASK (0x40000000U) -#define DMA_COMMON_INTA_INTA30_SHIFT (30U) -/*! INTA30 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA30_SHIFT)) & DMA_COMMON_INTA_INTA30_MASK) - -#define DMA_COMMON_INTA_INTA31_MASK (0x80000000U) -#define DMA_COMMON_INTA_INTA31_SHIFT (31U) -/*! INTA31 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_INTA31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA31_SHIFT)) & DMA_COMMON_INTA_INTA31_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTA */ -#define DMA_COMMON_INTA_COUNT (1U) - -/*! @name COMMON_INTA1 - Interrupt A status for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_INTA1_INTA32_MASK (0x1U) -#define DMA_COMMON_INTA1_INTA32_SHIFT (0U) -/*! INTA32 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA1_INTA32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA32_SHIFT)) & DMA_COMMON_INTA1_INTA32_MASK) - -#define DMA_COMMON_INTA1_INTA33_MASK (0x2U) -#define DMA_COMMON_INTA1_INTA33_SHIFT (1U) -/*! INTA33 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA1_INTA33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA33_SHIFT)) & DMA_COMMON_INTA1_INTA33_MASK) - -#define DMA_COMMON_INTA1_INTA34_MASK (0x4U) -#define DMA_COMMON_INTA1_INTA34_SHIFT (2U) -/*! INTA34 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA1_INTA34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA34_SHIFT)) & DMA_COMMON_INTA1_INTA34_MASK) - -#define DMA_COMMON_INTA1_INTA35_MASK (0x8U) -#define DMA_COMMON_INTA1_INTA35_SHIFT (3U) -/*! INTA35 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA1_INTA35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA35_SHIFT)) & DMA_COMMON_INTA1_INTA35_MASK) - -#define DMA_COMMON_INTA1_INTA36_MASK (0x10U) -#define DMA_COMMON_INTA1_INTA36_SHIFT (4U) -/*! INTA36 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA1_INTA36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA36_SHIFT)) & DMA_COMMON_INTA1_INTA36_MASK) - -#define DMA_COMMON_INTA1_INTA37_MASK (0x20U) -#define DMA_COMMON_INTA1_INTA37_SHIFT (5U) -/*! INTA37 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA1_INTA37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA37_SHIFT)) & DMA_COMMON_INTA1_INTA37_MASK) - -#define DMA_COMMON_INTA1_INTA38_MASK (0x40U) -#define DMA_COMMON_INTA1_INTA38_SHIFT (6U) -/*! INTA38 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA1_INTA38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA38_SHIFT)) & DMA_COMMON_INTA1_INTA38_MASK) - -#define DMA_COMMON_INTA1_INTA39_MASK (0x80U) -#define DMA_COMMON_INTA1_INTA39_SHIFT (7U) -/*! INTA39 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA1_INTA39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA39_SHIFT)) & DMA_COMMON_INTA1_INTA39_MASK) - -#define DMA_COMMON_INTA1_INTA40_MASK (0x100U) -#define DMA_COMMON_INTA1_INTA40_SHIFT (8U) -/*! INTA40 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA1_INTA40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA40_SHIFT)) & DMA_COMMON_INTA1_INTA40_MASK) - -#define DMA_COMMON_INTA1_INTA41_MASK (0x200U) -#define DMA_COMMON_INTA1_INTA41_SHIFT (9U) -/*! INTA41 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA1_INTA41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA41_SHIFT)) & DMA_COMMON_INTA1_INTA41_MASK) - -#define DMA_COMMON_INTA1_INTA42_MASK (0x400U) -#define DMA_COMMON_INTA1_INTA42_SHIFT (10U) -/*! INTA42 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA1_INTA42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA42_SHIFT)) & DMA_COMMON_INTA1_INTA42_MASK) - -#define DMA_COMMON_INTA1_INTA43_MASK (0x800U) -#define DMA_COMMON_INTA1_INTA43_SHIFT (11U) -/*! INTA43 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA1_INTA43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA43_SHIFT)) & DMA_COMMON_INTA1_INTA43_MASK) - -#define DMA_COMMON_INTA1_INTA44_MASK (0x1000U) -#define DMA_COMMON_INTA1_INTA44_SHIFT (12U) -/*! INTA44 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA1_INTA44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA44_SHIFT)) & DMA_COMMON_INTA1_INTA44_MASK) - -#define DMA_COMMON_INTA1_INTA45_MASK (0x2000U) -#define DMA_COMMON_INTA1_INTA45_SHIFT (13U) -/*! INTA45 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA1_INTA45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA45_SHIFT)) & DMA_COMMON_INTA1_INTA45_MASK) - -#define DMA_COMMON_INTA1_INTA46_MASK (0x4000U) -#define DMA_COMMON_INTA1_INTA46_SHIFT (14U) -/*! INTA46 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA1_INTA46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA46_SHIFT)) & DMA_COMMON_INTA1_INTA46_MASK) - -#define DMA_COMMON_INTA1_INTA47_MASK (0x8000U) -#define DMA_COMMON_INTA1_INTA47_SHIFT (15U) -/*! INTA47 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA1_INTA47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA47_SHIFT)) & DMA_COMMON_INTA1_INTA47_MASK) - -#define DMA_COMMON_INTA1_INTA48_MASK (0x10000U) -#define DMA_COMMON_INTA1_INTA48_SHIFT (16U) -/*! INTA48 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA1_INTA48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA48_SHIFT)) & DMA_COMMON_INTA1_INTA48_MASK) - -#define DMA_COMMON_INTA1_INTA49_MASK (0x20000U) -#define DMA_COMMON_INTA1_INTA49_SHIFT (17U) -/*! INTA49 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA1_INTA49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA49_SHIFT)) & DMA_COMMON_INTA1_INTA49_MASK) - -#define DMA_COMMON_INTA1_INTA50_MASK (0x40000U) -#define DMA_COMMON_INTA1_INTA50_SHIFT (18U) -/*! INTA50 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA1_INTA50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA50_SHIFT)) & DMA_COMMON_INTA1_INTA50_MASK) - -#define DMA_COMMON_INTA1_INTA51_MASK (0x80000U) -#define DMA_COMMON_INTA1_INTA51_SHIFT (19U) -/*! INTA51 - Interrupt A status for DMA channel. - * 0b0..The DMA channel interrupt A is not active. - * 0b1..The DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA1_INTA51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA51_SHIFT)) & DMA_COMMON_INTA1_INTA51_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTA1 */ -#define DMA_COMMON_INTA1_COUNT (1U) - -/*! @name COMMON_INTB - Interrupt B status for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_INTB_INTB0_MASK (0x1U) -#define DMA_COMMON_INTB_INTB0_SHIFT (0U) -/*! INTB0 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB0_SHIFT)) & DMA_COMMON_INTB_INTB0_MASK) - -#define DMA_COMMON_INTB_INTB1_MASK (0x2U) -#define DMA_COMMON_INTB_INTB1_SHIFT (1U) -/*! INTB1 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB1_SHIFT)) & DMA_COMMON_INTB_INTB1_MASK) - -#define DMA_COMMON_INTB_INTB2_MASK (0x4U) -#define DMA_COMMON_INTB_INTB2_SHIFT (2U) -/*! INTB2 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB2_SHIFT)) & DMA_COMMON_INTB_INTB2_MASK) - -#define DMA_COMMON_INTB_INTB3_MASK (0x8U) -#define DMA_COMMON_INTB_INTB3_SHIFT (3U) -/*! INTB3 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB3_SHIFT)) & DMA_COMMON_INTB_INTB3_MASK) - -#define DMA_COMMON_INTB_INTB4_MASK (0x10U) -#define DMA_COMMON_INTB_INTB4_SHIFT (4U) -/*! INTB4 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB4_SHIFT)) & DMA_COMMON_INTB_INTB4_MASK) - -#define DMA_COMMON_INTB_INTB5_MASK (0x20U) -#define DMA_COMMON_INTB_INTB5_SHIFT (5U) -/*! INTB5 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB5_SHIFT)) & DMA_COMMON_INTB_INTB5_MASK) - -#define DMA_COMMON_INTB_INTB6_MASK (0x40U) -#define DMA_COMMON_INTB_INTB6_SHIFT (6U) -/*! INTB6 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB6_SHIFT)) & DMA_COMMON_INTB_INTB6_MASK) - -#define DMA_COMMON_INTB_INTB7_MASK (0x80U) -#define DMA_COMMON_INTB_INTB7_SHIFT (7U) -/*! INTB7 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB7_SHIFT)) & DMA_COMMON_INTB_INTB7_MASK) - -#define DMA_COMMON_INTB_INTB8_MASK (0x100U) -#define DMA_COMMON_INTB_INTB8_SHIFT (8U) -/*! INTB8 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB8_SHIFT)) & DMA_COMMON_INTB_INTB8_MASK) - -#define DMA_COMMON_INTB_INTB9_MASK (0x200U) -#define DMA_COMMON_INTB_INTB9_SHIFT (9U) -/*! INTB9 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB9_SHIFT)) & DMA_COMMON_INTB_INTB9_MASK) - -#define DMA_COMMON_INTB_INTB10_MASK (0x400U) -#define DMA_COMMON_INTB_INTB10_SHIFT (10U) -/*! INTB10 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB10_SHIFT)) & DMA_COMMON_INTB_INTB10_MASK) - -#define DMA_COMMON_INTB_INTB11_MASK (0x800U) -#define DMA_COMMON_INTB_INTB11_SHIFT (11U) -/*! INTB11 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB11_SHIFT)) & DMA_COMMON_INTB_INTB11_MASK) - -#define DMA_COMMON_INTB_INTB12_MASK (0x1000U) -#define DMA_COMMON_INTB_INTB12_SHIFT (12U) -/*! INTB12 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB12_SHIFT)) & DMA_COMMON_INTB_INTB12_MASK) - -#define DMA_COMMON_INTB_INTB13_MASK (0x2000U) -#define DMA_COMMON_INTB_INTB13_SHIFT (13U) -/*! INTB13 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB13_SHIFT)) & DMA_COMMON_INTB_INTB13_MASK) - -#define DMA_COMMON_INTB_INTB14_MASK (0x4000U) -#define DMA_COMMON_INTB_INTB14_SHIFT (14U) -/*! INTB14 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB14_SHIFT)) & DMA_COMMON_INTB_INTB14_MASK) - -#define DMA_COMMON_INTB_INTB15_MASK (0x8000U) -#define DMA_COMMON_INTB_INTB15_SHIFT (15U) -/*! INTB15 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB15_SHIFT)) & DMA_COMMON_INTB_INTB15_MASK) - -#define DMA_COMMON_INTB_INTB16_MASK (0x10000U) -#define DMA_COMMON_INTB_INTB16_SHIFT (16U) -/*! INTB16 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB16_SHIFT)) & DMA_COMMON_INTB_INTB16_MASK) - -#define DMA_COMMON_INTB_INTB17_MASK (0x20000U) -#define DMA_COMMON_INTB_INTB17_SHIFT (17U) -/*! INTB17 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB17_SHIFT)) & DMA_COMMON_INTB_INTB17_MASK) - -#define DMA_COMMON_INTB_INTB18_MASK (0x40000U) -#define DMA_COMMON_INTB_INTB18_SHIFT (18U) -/*! INTB18 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB18_SHIFT)) & DMA_COMMON_INTB_INTB18_MASK) - -#define DMA_COMMON_INTB_INTB19_MASK (0x80000U) -#define DMA_COMMON_INTB_INTB19_SHIFT (19U) -/*! INTB19 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB19_SHIFT)) & DMA_COMMON_INTB_INTB19_MASK) - -#define DMA_COMMON_INTB_INTB20_MASK (0x100000U) -#define DMA_COMMON_INTB_INTB20_SHIFT (20U) -/*! INTB20 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB20_SHIFT)) & DMA_COMMON_INTB_INTB20_MASK) - -#define DMA_COMMON_INTB_INTB21_MASK (0x200000U) -#define DMA_COMMON_INTB_INTB21_SHIFT (21U) -/*! INTB21 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB21_SHIFT)) & DMA_COMMON_INTB_INTB21_MASK) - -#define DMA_COMMON_INTB_INTB22_MASK (0x400000U) -#define DMA_COMMON_INTB_INTB22_SHIFT (22U) -/*! INTB22 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB22_SHIFT)) & DMA_COMMON_INTB_INTB22_MASK) - -#define DMA_COMMON_INTB_INTB23_MASK (0x800000U) -#define DMA_COMMON_INTB_INTB23_SHIFT (23U) -/*! INTB23 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB23_SHIFT)) & DMA_COMMON_INTB_INTB23_MASK) - -#define DMA_COMMON_INTB_INTB24_MASK (0x1000000U) -#define DMA_COMMON_INTB_INTB24_SHIFT (24U) -/*! INTB24 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB24_SHIFT)) & DMA_COMMON_INTB_INTB24_MASK) - -#define DMA_COMMON_INTB_INTB25_MASK (0x2000000U) -#define DMA_COMMON_INTB_INTB25_SHIFT (25U) -/*! INTB25 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB25_SHIFT)) & DMA_COMMON_INTB_INTB25_MASK) - -#define DMA_COMMON_INTB_INTB26_MASK (0x4000000U) -#define DMA_COMMON_INTB_INTB26_SHIFT (26U) -/*! INTB26 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB26_SHIFT)) & DMA_COMMON_INTB_INTB26_MASK) - -#define DMA_COMMON_INTB_INTB27_MASK (0x8000000U) -#define DMA_COMMON_INTB_INTB27_SHIFT (27U) -/*! INTB27 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB27_SHIFT)) & DMA_COMMON_INTB_INTB27_MASK) - -#define DMA_COMMON_INTB_INTB28_MASK (0x10000000U) -#define DMA_COMMON_INTB_INTB28_SHIFT (28U) -/*! INTB28 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB28_SHIFT)) & DMA_COMMON_INTB_INTB28_MASK) - -#define DMA_COMMON_INTB_INTB29_MASK (0x20000000U) -#define DMA_COMMON_INTB_INTB29_SHIFT (29U) -/*! INTB29 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB29_SHIFT)) & DMA_COMMON_INTB_INTB29_MASK) - -#define DMA_COMMON_INTB_INTB30_MASK (0x40000000U) -#define DMA_COMMON_INTB_INTB30_SHIFT (30U) -/*! INTB30 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB30_SHIFT)) & DMA_COMMON_INTB_INTB30_MASK) - -#define DMA_COMMON_INTB_INTB31_MASK (0x80000000U) -#define DMA_COMMON_INTB_INTB31_SHIFT (31U) -/*! INTB31 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_INTB31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB31_SHIFT)) & DMA_COMMON_INTB_INTB31_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTB */ -#define DMA_COMMON_INTB_COUNT (1U) - -/*! @name COMMON_INTB1 - Interrupt B status for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_INTB1_INTB0_MASK (0x1U) -#define DMA_COMMON_INTB1_INTB0_SHIFT (0U) -/*! INTB0 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB1_INTB0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB0_SHIFT)) & DMA_COMMON_INTB1_INTB0_MASK) - -#define DMA_COMMON_INTB1_INTB1_MASK (0x2U) -#define DMA_COMMON_INTB1_INTB1_SHIFT (1U) -/*! INTB1 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB1_INTB1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB1_SHIFT)) & DMA_COMMON_INTB1_INTB1_MASK) - -#define DMA_COMMON_INTB1_INTB2_MASK (0x4U) -#define DMA_COMMON_INTB1_INTB2_SHIFT (2U) -/*! INTB2 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB1_INTB2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB2_SHIFT)) & DMA_COMMON_INTB1_INTB2_MASK) - -#define DMA_COMMON_INTB1_INTB3_MASK (0x8U) -#define DMA_COMMON_INTB1_INTB3_SHIFT (3U) -/*! INTB3 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB1_INTB3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB3_SHIFT)) & DMA_COMMON_INTB1_INTB3_MASK) - -#define DMA_COMMON_INTB1_INTB4_MASK (0x10U) -#define DMA_COMMON_INTB1_INTB4_SHIFT (4U) -/*! INTB4 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB1_INTB4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB4_SHIFT)) & DMA_COMMON_INTB1_INTB4_MASK) - -#define DMA_COMMON_INTB1_INTB5_MASK (0x20U) -#define DMA_COMMON_INTB1_INTB5_SHIFT (5U) -/*! INTB5 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB1_INTB5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB5_SHIFT)) & DMA_COMMON_INTB1_INTB5_MASK) - -#define DMA_COMMON_INTB1_INTB6_MASK (0x40U) -#define DMA_COMMON_INTB1_INTB6_SHIFT (6U) -/*! INTB6 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB1_INTB6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB6_SHIFT)) & DMA_COMMON_INTB1_INTB6_MASK) - -#define DMA_COMMON_INTB1_INTB7_MASK (0x80U) -#define DMA_COMMON_INTB1_INTB7_SHIFT (7U) -/*! INTB7 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB1_INTB7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB7_SHIFT)) & DMA_COMMON_INTB1_INTB7_MASK) - -#define DMA_COMMON_INTB1_INTB8_MASK (0x100U) -#define DMA_COMMON_INTB1_INTB8_SHIFT (8U) -/*! INTB8 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB1_INTB8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB8_SHIFT)) & DMA_COMMON_INTB1_INTB8_MASK) - -#define DMA_COMMON_INTB1_INTB9_MASK (0x200U) -#define DMA_COMMON_INTB1_INTB9_SHIFT (9U) -/*! INTB9 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB1_INTB9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB9_SHIFT)) & DMA_COMMON_INTB1_INTB9_MASK) - -#define DMA_COMMON_INTB1_INTB10_MASK (0x400U) -#define DMA_COMMON_INTB1_INTB10_SHIFT (10U) -/*! INTB10 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB1_INTB10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB10_SHIFT)) & DMA_COMMON_INTB1_INTB10_MASK) - -#define DMA_COMMON_INTB1_INTB11_MASK (0x800U) -#define DMA_COMMON_INTB1_INTB11_SHIFT (11U) -/*! INTB11 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB1_INTB11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB11_SHIFT)) & DMA_COMMON_INTB1_INTB11_MASK) - -#define DMA_COMMON_INTB1_INTB12_MASK (0x1000U) -#define DMA_COMMON_INTB1_INTB12_SHIFT (12U) -/*! INTB12 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB1_INTB12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB12_SHIFT)) & DMA_COMMON_INTB1_INTB12_MASK) - -#define DMA_COMMON_INTB1_INTB13_MASK (0x2000U) -#define DMA_COMMON_INTB1_INTB13_SHIFT (13U) -/*! INTB13 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB1_INTB13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB13_SHIFT)) & DMA_COMMON_INTB1_INTB13_MASK) - -#define DMA_COMMON_INTB1_INTB14_MASK (0x4000U) -#define DMA_COMMON_INTB1_INTB14_SHIFT (14U) -/*! INTB14 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB1_INTB14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB14_SHIFT)) & DMA_COMMON_INTB1_INTB14_MASK) - -#define DMA_COMMON_INTB1_INTB15_MASK (0x8000U) -#define DMA_COMMON_INTB1_INTB15_SHIFT (15U) -/*! INTB15 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB1_INTB15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB15_SHIFT)) & DMA_COMMON_INTB1_INTB15_MASK) - -#define DMA_COMMON_INTB1_INTB16_MASK (0x10000U) -#define DMA_COMMON_INTB1_INTB16_SHIFT (16U) -/*! INTB16 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB1_INTB16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB16_SHIFT)) & DMA_COMMON_INTB1_INTB16_MASK) - -#define DMA_COMMON_INTB1_INTB17_MASK (0x20000U) -#define DMA_COMMON_INTB1_INTB17_SHIFT (17U) -/*! INTB17 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB1_INTB17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB17_SHIFT)) & DMA_COMMON_INTB1_INTB17_MASK) - -#define DMA_COMMON_INTB1_INTB18_MASK (0x40000U) -#define DMA_COMMON_INTB1_INTB18_SHIFT (18U) -/*! INTB18 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB1_INTB18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB18_SHIFT)) & DMA_COMMON_INTB1_INTB18_MASK) - -#define DMA_COMMON_INTB1_INTB19_MASK (0x80000U) -#define DMA_COMMON_INTB1_INTB19_SHIFT (19U) -/*! INTB19 - Interrupt B status for DMA channel. - * 0b0..The DMA channel interrupt B is not active. - * 0b1..The DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB1_INTB19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB19_SHIFT)) & DMA_COMMON_INTB1_INTB19_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTB1 */ -#define DMA_COMMON_INTB1_COUNT (1U) - -/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_SETVALID_SETVALID0_MASK (0x1U) -#define DMA_COMMON_SETVALID_SETVALID0_SHIFT (0U) -/*! SETVALID0 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID0_SHIFT)) & DMA_COMMON_SETVALID_SETVALID0_MASK) - -#define DMA_COMMON_SETVALID_SETVALID1_MASK (0x2U) -#define DMA_COMMON_SETVALID_SETVALID1_SHIFT (1U) -/*! SETVALID1 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID1_SHIFT)) & DMA_COMMON_SETVALID_SETVALID1_MASK) - -#define DMA_COMMON_SETVALID_SETVALID2_MASK (0x4U) -#define DMA_COMMON_SETVALID_SETVALID2_SHIFT (2U) -/*! SETVALID2 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID2_SHIFT)) & DMA_COMMON_SETVALID_SETVALID2_MASK) - -#define DMA_COMMON_SETVALID_SETVALID3_MASK (0x8U) -#define DMA_COMMON_SETVALID_SETVALID3_SHIFT (3U) -/*! SETVALID3 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID3_SHIFT)) & DMA_COMMON_SETVALID_SETVALID3_MASK) - -#define DMA_COMMON_SETVALID_SETVALID4_MASK (0x10U) -#define DMA_COMMON_SETVALID_SETVALID4_SHIFT (4U) -/*! SETVALID4 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID4_SHIFT)) & DMA_COMMON_SETVALID_SETVALID4_MASK) - -#define DMA_COMMON_SETVALID_SETVALID5_MASK (0x20U) -#define DMA_COMMON_SETVALID_SETVALID5_SHIFT (5U) -/*! SETVALID5 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID5_SHIFT)) & DMA_COMMON_SETVALID_SETVALID5_MASK) - -#define DMA_COMMON_SETVALID_SETVALID6_MASK (0x40U) -#define DMA_COMMON_SETVALID_SETVALID6_SHIFT (6U) -/*! SETVALID6 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID6_SHIFT)) & DMA_COMMON_SETVALID_SETVALID6_MASK) - -#define DMA_COMMON_SETVALID_SETVALID7_MASK (0x80U) -#define DMA_COMMON_SETVALID_SETVALID7_SHIFT (7U) -/*! SETVALID7 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID7_SHIFT)) & DMA_COMMON_SETVALID_SETVALID7_MASK) - -#define DMA_COMMON_SETVALID_SETVALID8_MASK (0x100U) -#define DMA_COMMON_SETVALID_SETVALID8_SHIFT (8U) -/*! SETVALID8 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID8_SHIFT)) & DMA_COMMON_SETVALID_SETVALID8_MASK) - -#define DMA_COMMON_SETVALID_SETVALID9_MASK (0x200U) -#define DMA_COMMON_SETVALID_SETVALID9_SHIFT (9U) -/*! SETVALID9 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID9_SHIFT)) & DMA_COMMON_SETVALID_SETVALID9_MASK) - -#define DMA_COMMON_SETVALID_SETVALID10_MASK (0x400U) -#define DMA_COMMON_SETVALID_SETVALID10_SHIFT (10U) -/*! SETVALID10 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID10_SHIFT)) & DMA_COMMON_SETVALID_SETVALID10_MASK) - -#define DMA_COMMON_SETVALID_SETVALID11_MASK (0x800U) -#define DMA_COMMON_SETVALID_SETVALID11_SHIFT (11U) -/*! SETVALID11 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID11_SHIFT)) & DMA_COMMON_SETVALID_SETVALID11_MASK) - -#define DMA_COMMON_SETVALID_SETVALID12_MASK (0x1000U) -#define DMA_COMMON_SETVALID_SETVALID12_SHIFT (12U) -/*! SETVALID12 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID12_SHIFT)) & DMA_COMMON_SETVALID_SETVALID12_MASK) - -#define DMA_COMMON_SETVALID_SETVALID13_MASK (0x2000U) -#define DMA_COMMON_SETVALID_SETVALID13_SHIFT (13U) -/*! SETVALID13 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID13_SHIFT)) & DMA_COMMON_SETVALID_SETVALID13_MASK) - -#define DMA_COMMON_SETVALID_SETVALID14_MASK (0x4000U) -#define DMA_COMMON_SETVALID_SETVALID14_SHIFT (14U) -/*! SETVALID14 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID14_SHIFT)) & DMA_COMMON_SETVALID_SETVALID14_MASK) - -#define DMA_COMMON_SETVALID_SETVALID15_MASK (0x8000U) -#define DMA_COMMON_SETVALID_SETVALID15_SHIFT (15U) -/*! SETVALID15 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID15_SHIFT)) & DMA_COMMON_SETVALID_SETVALID15_MASK) - -#define DMA_COMMON_SETVALID_SETVALID16_MASK (0x10000U) -#define DMA_COMMON_SETVALID_SETVALID16_SHIFT (16U) -/*! SETVALID16 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID16_SHIFT)) & DMA_COMMON_SETVALID_SETVALID16_MASK) - -#define DMA_COMMON_SETVALID_SETVALID17_MASK (0x20000U) -#define DMA_COMMON_SETVALID_SETVALID17_SHIFT (17U) -/*! SETVALID17 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID17_SHIFT)) & DMA_COMMON_SETVALID_SETVALID17_MASK) - -#define DMA_COMMON_SETVALID_SETVALID18_MASK (0x40000U) -#define DMA_COMMON_SETVALID_SETVALID18_SHIFT (18U) -/*! SETVALID18 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID18_SHIFT)) & DMA_COMMON_SETVALID_SETVALID18_MASK) - -#define DMA_COMMON_SETVALID_SETVALID19_MASK (0x80000U) -#define DMA_COMMON_SETVALID_SETVALID19_SHIFT (19U) -/*! SETVALID19 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID19_SHIFT)) & DMA_COMMON_SETVALID_SETVALID19_MASK) - -#define DMA_COMMON_SETVALID_SETVALID20_MASK (0x100000U) -#define DMA_COMMON_SETVALID_SETVALID20_SHIFT (20U) -/*! SETVALID20 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID20_SHIFT)) & DMA_COMMON_SETVALID_SETVALID20_MASK) - -#define DMA_COMMON_SETVALID_SETVALID21_MASK (0x200000U) -#define DMA_COMMON_SETVALID_SETVALID21_SHIFT (21U) -/*! SETVALID21 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID21_SHIFT)) & DMA_COMMON_SETVALID_SETVALID21_MASK) - -#define DMA_COMMON_SETVALID_SETVALID22_MASK (0x400000U) -#define DMA_COMMON_SETVALID_SETVALID22_SHIFT (22U) -/*! SETVALID22 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID22_SHIFT)) & DMA_COMMON_SETVALID_SETVALID22_MASK) - -#define DMA_COMMON_SETVALID_SETVALID23_MASK (0x800000U) -#define DMA_COMMON_SETVALID_SETVALID23_SHIFT (23U) -/*! SETVALID23 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID23_SHIFT)) & DMA_COMMON_SETVALID_SETVALID23_MASK) - -#define DMA_COMMON_SETVALID_SETVALID24_MASK (0x1000000U) -#define DMA_COMMON_SETVALID_SETVALID24_SHIFT (24U) -/*! SETVALID24 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID24_SHIFT)) & DMA_COMMON_SETVALID_SETVALID24_MASK) - -#define DMA_COMMON_SETVALID_SETVALID25_MASK (0x2000000U) -#define DMA_COMMON_SETVALID_SETVALID25_SHIFT (25U) -/*! SETVALID25 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID25_SHIFT)) & DMA_COMMON_SETVALID_SETVALID25_MASK) - -#define DMA_COMMON_SETVALID_SETVALID26_MASK (0x4000000U) -#define DMA_COMMON_SETVALID_SETVALID26_SHIFT (26U) -/*! SETVALID26 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID26_SHIFT)) & DMA_COMMON_SETVALID_SETVALID26_MASK) - -#define DMA_COMMON_SETVALID_SETVALID27_MASK (0x8000000U) -#define DMA_COMMON_SETVALID_SETVALID27_SHIFT (27U) -/*! SETVALID27 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID27_SHIFT)) & DMA_COMMON_SETVALID_SETVALID27_MASK) - -#define DMA_COMMON_SETVALID_SETVALID28_MASK (0x10000000U) -#define DMA_COMMON_SETVALID_SETVALID28_SHIFT (28U) -/*! SETVALID28 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID28_SHIFT)) & DMA_COMMON_SETVALID_SETVALID28_MASK) - -#define DMA_COMMON_SETVALID_SETVALID29_MASK (0x20000000U) -#define DMA_COMMON_SETVALID_SETVALID29_SHIFT (29U) -/*! SETVALID29 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID29_SHIFT)) & DMA_COMMON_SETVALID_SETVALID29_MASK) - -#define DMA_COMMON_SETVALID_SETVALID30_MASK (0x40000000U) -#define DMA_COMMON_SETVALID_SETVALID30_SHIFT (30U) -/*! SETVALID30 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID30_SHIFT)) & DMA_COMMON_SETVALID_SETVALID30_MASK) - -#define DMA_COMMON_SETVALID_SETVALID31_MASK (0x80000000U) -#define DMA_COMMON_SETVALID_SETVALID31_SHIFT (31U) -/*! SETVALID31 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID_SETVALID31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID31_SHIFT)) & DMA_COMMON_SETVALID_SETVALID31_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETVALID */ -#define DMA_COMMON_SETVALID_COUNT (1U) - -/*! @name COMMON_SETVALID1 - Set ValidPending control bits for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_SETVALID1_SETVALID32_MASK (0x1U) -#define DMA_COMMON_SETVALID1_SETVALID32_SHIFT (0U) -/*! SETVALID32 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID1_SETVALID32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID32_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID32_MASK) - -#define DMA_COMMON_SETVALID1_SETVALID33_MASK (0x2U) -#define DMA_COMMON_SETVALID1_SETVALID33_SHIFT (1U) -/*! SETVALID33 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID1_SETVALID33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID33_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID33_MASK) - -#define DMA_COMMON_SETVALID1_SETVALID34_MASK (0x4U) -#define DMA_COMMON_SETVALID1_SETVALID34_SHIFT (2U) -/*! SETVALID34 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID1_SETVALID34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID34_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID34_MASK) - -#define DMA_COMMON_SETVALID1_SETVALID35_MASK (0x8U) -#define DMA_COMMON_SETVALID1_SETVALID35_SHIFT (3U) -/*! SETVALID35 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID1_SETVALID35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID35_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID35_MASK) - -#define DMA_COMMON_SETVALID1_SETVALID36_MASK (0x10U) -#define DMA_COMMON_SETVALID1_SETVALID36_SHIFT (4U) -/*! SETVALID36 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID1_SETVALID36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID36_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID36_MASK) - -#define DMA_COMMON_SETVALID1_SETVALID37_MASK (0x20U) -#define DMA_COMMON_SETVALID1_SETVALID37_SHIFT (5U) -/*! SETVALID37 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID1_SETVALID37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID37_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID37_MASK) - -#define DMA_COMMON_SETVALID1_SETVALID38_MASK (0x40U) -#define DMA_COMMON_SETVALID1_SETVALID38_SHIFT (6U) -/*! SETVALID38 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID1_SETVALID38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID38_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID38_MASK) - -#define DMA_COMMON_SETVALID1_SETVALID39_MASK (0x80U) -#define DMA_COMMON_SETVALID1_SETVALID39_SHIFT (7U) -/*! SETVALID39 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID1_SETVALID39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID39_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID39_MASK) - -#define DMA_COMMON_SETVALID1_SETVALID40_MASK (0x100U) -#define DMA_COMMON_SETVALID1_SETVALID40_SHIFT (8U) -/*! SETVALID40 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID1_SETVALID40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID40_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID40_MASK) - -#define DMA_COMMON_SETVALID1_SETVALID41_MASK (0x200U) -#define DMA_COMMON_SETVALID1_SETVALID41_SHIFT (9U) -/*! SETVALID41 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID1_SETVALID41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID41_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID41_MASK) - -#define DMA_COMMON_SETVALID1_SETVALID42_MASK (0x400U) -#define DMA_COMMON_SETVALID1_SETVALID42_SHIFT (10U) -/*! SETVALID42 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID1_SETVALID42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID42_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID42_MASK) - -#define DMA_COMMON_SETVALID1_SETVALID43_MASK (0x800U) -#define DMA_COMMON_SETVALID1_SETVALID43_SHIFT (11U) -/*! SETVALID43 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID1_SETVALID43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID43_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID43_MASK) - -#define DMA_COMMON_SETVALID1_SETVALID44_MASK (0x1000U) -#define DMA_COMMON_SETVALID1_SETVALID44_SHIFT (12U) -/*! SETVALID44 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID1_SETVALID44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID44_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID44_MASK) - -#define DMA_COMMON_SETVALID1_SETVALID45_MASK (0x2000U) -#define DMA_COMMON_SETVALID1_SETVALID45_SHIFT (13U) -/*! SETVALID45 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID1_SETVALID45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID45_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID45_MASK) - -#define DMA_COMMON_SETVALID1_SETVALID46_MASK (0x4000U) -#define DMA_COMMON_SETVALID1_SETVALID46_SHIFT (14U) -/*! SETVALID46 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID1_SETVALID46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID46_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID46_MASK) - -#define DMA_COMMON_SETVALID1_SETVALID47_MASK (0x8000U) -#define DMA_COMMON_SETVALID1_SETVALID47_SHIFT (15U) -/*! SETVALID47 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID1_SETVALID47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID47_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID47_MASK) - -#define DMA_COMMON_SETVALID1_SETVALID48_MASK (0x10000U) -#define DMA_COMMON_SETVALID1_SETVALID48_SHIFT (16U) -/*! SETVALID48 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID1_SETVALID48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID48_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID48_MASK) - -#define DMA_COMMON_SETVALID1_SETVALID49_MASK (0x20000U) -#define DMA_COMMON_SETVALID1_SETVALID49_SHIFT (17U) -/*! SETVALID49 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID1_SETVALID49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID49_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID49_MASK) - -#define DMA_COMMON_SETVALID1_SETVALID50_MASK (0x40000U) -#define DMA_COMMON_SETVALID1_SETVALID50_SHIFT (18U) -/*! SETVALID50 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID1_SETVALID50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID50_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID50_MASK) - -#define DMA_COMMON_SETVALID1_SETVALID51_MASK (0x80000U) -#define DMA_COMMON_SETVALID1_SETVALID51_SHIFT (19U) -/*! SETVALID51 - SetValid control for DMA channel. - * 0b0..No effect. - * 0b1..Sets the ValidPending control bit for DMA channel. - */ -#define DMA_COMMON_SETVALID1_SETVALID51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID51_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID51_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETVALID1 */ -#define DMA_COMMON_SETVALID1_COUNT (1U) - -/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_SETTRIG_SETTRIG0_MASK (0x1U) -#define DMA_COMMON_SETTRIG_SETTRIG0_SHIFT (0U) -/*! SETTRIG0 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG0_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG0_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG1_MASK (0x2U) -#define DMA_COMMON_SETTRIG_SETTRIG1_SHIFT (1U) -/*! SETTRIG1 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG1_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG1_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG2_MASK (0x4U) -#define DMA_COMMON_SETTRIG_SETTRIG2_SHIFT (2U) -/*! SETTRIG2 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG2_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG2_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG3_MASK (0x8U) -#define DMA_COMMON_SETTRIG_SETTRIG3_SHIFT (3U) -/*! SETTRIG3 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG3_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG3_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG4_MASK (0x10U) -#define DMA_COMMON_SETTRIG_SETTRIG4_SHIFT (4U) -/*! SETTRIG4 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG4_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG4_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG5_MASK (0x20U) -#define DMA_COMMON_SETTRIG_SETTRIG5_SHIFT (5U) -/*! SETTRIG5 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG5_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG5_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG6_MASK (0x40U) -#define DMA_COMMON_SETTRIG_SETTRIG6_SHIFT (6U) -/*! SETTRIG6 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG6_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG6_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG7_MASK (0x80U) -#define DMA_COMMON_SETTRIG_SETTRIG7_SHIFT (7U) -/*! SETTRIG7 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG7_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG7_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG8_MASK (0x100U) -#define DMA_COMMON_SETTRIG_SETTRIG8_SHIFT (8U) -/*! SETTRIG8 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG8_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG8_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG9_MASK (0x200U) -#define DMA_COMMON_SETTRIG_SETTRIG9_SHIFT (9U) -/*! SETTRIG9 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG9_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG9_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG10_MASK (0x400U) -#define DMA_COMMON_SETTRIG_SETTRIG10_SHIFT (10U) -/*! SETTRIG10 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG10_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG10_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG11_MASK (0x800U) -#define DMA_COMMON_SETTRIG_SETTRIG11_SHIFT (11U) -/*! SETTRIG11 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG11_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG11_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG12_MASK (0x1000U) -#define DMA_COMMON_SETTRIG_SETTRIG12_SHIFT (12U) -/*! SETTRIG12 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG12_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG12_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG13_MASK (0x2000U) -#define DMA_COMMON_SETTRIG_SETTRIG13_SHIFT (13U) -/*! SETTRIG13 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG13_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG13_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG14_MASK (0x4000U) -#define DMA_COMMON_SETTRIG_SETTRIG14_SHIFT (14U) -/*! SETTRIG14 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG14_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG14_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG15_MASK (0x8000U) -#define DMA_COMMON_SETTRIG_SETTRIG15_SHIFT (15U) -/*! SETTRIG15 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG15_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG15_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG16_MASK (0x10000U) -#define DMA_COMMON_SETTRIG_SETTRIG16_SHIFT (16U) -/*! SETTRIG16 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG16_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG16_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG17_MASK (0x20000U) -#define DMA_COMMON_SETTRIG_SETTRIG17_SHIFT (17U) -/*! SETTRIG17 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG17_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG17_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG18_MASK (0x40000U) -#define DMA_COMMON_SETTRIG_SETTRIG18_SHIFT (18U) -/*! SETTRIG18 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG18_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG18_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG19_MASK (0x80000U) -#define DMA_COMMON_SETTRIG_SETTRIG19_SHIFT (19U) -/*! SETTRIG19 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG19_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG19_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG20_MASK (0x100000U) -#define DMA_COMMON_SETTRIG_SETTRIG20_SHIFT (20U) -/*! SETTRIG20 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG20_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG20_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG21_MASK (0x200000U) -#define DMA_COMMON_SETTRIG_SETTRIG21_SHIFT (21U) -/*! SETTRIG21 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG21_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG21_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG22_MASK (0x400000U) -#define DMA_COMMON_SETTRIG_SETTRIG22_SHIFT (22U) -/*! SETTRIG22 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG22_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG22_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG23_MASK (0x800000U) -#define DMA_COMMON_SETTRIG_SETTRIG23_SHIFT (23U) -/*! SETTRIG23 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG23_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG23_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG24_MASK (0x1000000U) -#define DMA_COMMON_SETTRIG_SETTRIG24_SHIFT (24U) -/*! SETTRIG24 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG24_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG24_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG25_MASK (0x2000000U) -#define DMA_COMMON_SETTRIG_SETTRIG25_SHIFT (25U) -/*! SETTRIG25 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG25_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG25_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG26_MASK (0x4000000U) -#define DMA_COMMON_SETTRIG_SETTRIG26_SHIFT (26U) -/*! SETTRIG26 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG26_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG26_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG27_MASK (0x8000000U) -#define DMA_COMMON_SETTRIG_SETTRIG27_SHIFT (27U) -/*! SETTRIG27 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG27_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG27_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG28_MASK (0x10000000U) -#define DMA_COMMON_SETTRIG_SETTRIG28_SHIFT (28U) -/*! SETTRIG28 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG28_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG28_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG29_MASK (0x20000000U) -#define DMA_COMMON_SETTRIG_SETTRIG29_SHIFT (29U) -/*! SETTRIG29 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG29_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG29_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG30_MASK (0x40000000U) -#define DMA_COMMON_SETTRIG_SETTRIG30_SHIFT (30U) -/*! SETTRIG30 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG30_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG30_MASK) - -#define DMA_COMMON_SETTRIG_SETTRIG31_MASK (0x80000000U) -#define DMA_COMMON_SETTRIG_SETTRIG31_SHIFT (31U) -/*! SETTRIG31 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG_SETTRIG31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG31_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG31_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETTRIG */ -#define DMA_COMMON_SETTRIG_COUNT (1U) - -/*! @name COMMON_SETTRIG1 - Set Trigger control bits for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_SETTRIG1_SETTRIG32_MASK (0x1U) -#define DMA_COMMON_SETTRIG1_SETTRIG32_SHIFT (0U) -/*! SETTRIG32 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG1_SETTRIG32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG32_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG32_MASK) - -#define DMA_COMMON_SETTRIG1_SETTRIG33_MASK (0x2U) -#define DMA_COMMON_SETTRIG1_SETTRIG33_SHIFT (1U) -/*! SETTRIG33 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG1_SETTRIG33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG33_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG33_MASK) - -#define DMA_COMMON_SETTRIG1_SETTRIG34_MASK (0x4U) -#define DMA_COMMON_SETTRIG1_SETTRIG34_SHIFT (2U) -/*! SETTRIG34 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG1_SETTRIG34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG34_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG34_MASK) - -#define DMA_COMMON_SETTRIG1_SETTRIG35_MASK (0x8U) -#define DMA_COMMON_SETTRIG1_SETTRIG35_SHIFT (3U) -/*! SETTRIG35 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG1_SETTRIG35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG35_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG35_MASK) - -#define DMA_COMMON_SETTRIG1_SETTRIG36_MASK (0x10U) -#define DMA_COMMON_SETTRIG1_SETTRIG36_SHIFT (4U) -/*! SETTRIG36 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG1_SETTRIG36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG36_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG36_MASK) - -#define DMA_COMMON_SETTRIG1_SETTRIG37_MASK (0x20U) -#define DMA_COMMON_SETTRIG1_SETTRIG37_SHIFT (5U) -/*! SETTRIG37 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG1_SETTRIG37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG37_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG37_MASK) - -#define DMA_COMMON_SETTRIG1_SETTRIG38_MASK (0x40U) -#define DMA_COMMON_SETTRIG1_SETTRIG38_SHIFT (6U) -/*! SETTRIG38 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG1_SETTRIG38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG38_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG38_MASK) - -#define DMA_COMMON_SETTRIG1_SETTRIG39_MASK (0x80U) -#define DMA_COMMON_SETTRIG1_SETTRIG39_SHIFT (7U) -/*! SETTRIG39 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG1_SETTRIG39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG39_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG39_MASK) - -#define DMA_COMMON_SETTRIG1_SETTRIG40_MASK (0x100U) -#define DMA_COMMON_SETTRIG1_SETTRIG40_SHIFT (8U) -/*! SETTRIG40 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG1_SETTRIG40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG40_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG40_MASK) - -#define DMA_COMMON_SETTRIG1_SETTRIG41_MASK (0x200U) -#define DMA_COMMON_SETTRIG1_SETTRIG41_SHIFT (9U) -/*! SETTRIG41 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG1_SETTRIG41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG41_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG41_MASK) - -#define DMA_COMMON_SETTRIG1_SETTRIG42_MASK (0x400U) -#define DMA_COMMON_SETTRIG1_SETTRIG42_SHIFT (10U) -/*! SETTRIG42 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG1_SETTRIG42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG42_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG42_MASK) - -#define DMA_COMMON_SETTRIG1_SETTRIG43_MASK (0x800U) -#define DMA_COMMON_SETTRIG1_SETTRIG43_SHIFT (11U) -/*! SETTRIG43 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG1_SETTRIG43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG43_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG43_MASK) - -#define DMA_COMMON_SETTRIG1_SETTRIG44_MASK (0x1000U) -#define DMA_COMMON_SETTRIG1_SETTRIG44_SHIFT (12U) -/*! SETTRIG44 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG1_SETTRIG44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG44_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG44_MASK) - -#define DMA_COMMON_SETTRIG1_SETTRIG45_MASK (0x2000U) -#define DMA_COMMON_SETTRIG1_SETTRIG45_SHIFT (13U) -/*! SETTRIG45 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG1_SETTRIG45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG45_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG45_MASK) - -#define DMA_COMMON_SETTRIG1_SETTRIG46_MASK (0x4000U) -#define DMA_COMMON_SETTRIG1_SETTRIG46_SHIFT (14U) -/*! SETTRIG46 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG1_SETTRIG46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG46_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG46_MASK) - -#define DMA_COMMON_SETTRIG1_SETTRIG47_MASK (0x8000U) -#define DMA_COMMON_SETTRIG1_SETTRIG47_SHIFT (15U) -/*! SETTRIG47 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG1_SETTRIG47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG47_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG47_MASK) - -#define DMA_COMMON_SETTRIG1_SETTRIG48_MASK (0x10000U) -#define DMA_COMMON_SETTRIG1_SETTRIG48_SHIFT (16U) -/*! SETTRIG48 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG1_SETTRIG48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG48_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG48_MASK) - -#define DMA_COMMON_SETTRIG1_SETTRIG49_MASK (0x20000U) -#define DMA_COMMON_SETTRIG1_SETTRIG49_SHIFT (17U) -/*! SETTRIG49 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG1_SETTRIG49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG49_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG49_MASK) - -#define DMA_COMMON_SETTRIG1_SETTRIG50_MASK (0x40000U) -#define DMA_COMMON_SETTRIG1_SETTRIG50_SHIFT (18U) -/*! SETTRIG50 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG1_SETTRIG50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG50_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG50_MASK) - -#define DMA_COMMON_SETTRIG1_SETTRIG51_MASK (0x80000U) -#define DMA_COMMON_SETTRIG1_SETTRIG51_SHIFT (19U) -/*! SETTRIG51 - Set Trigger control bit for DMA channel. - * 0b0..No effect. - * 0b1..Sets the Trig bit for DMA channel. - */ -#define DMA_COMMON_SETTRIG1_SETTRIG51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG51_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG51_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETTRIG1 */ -#define DMA_COMMON_SETTRIG1_COUNT (1U) - -/*! @name COMMON_ABORT - Channel Abort control for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_ABORT_ABORT0_MASK (0x1U) -#define DMA_COMMON_ABORT_ABORT0_SHIFT (0U) -/*! ABORT0 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT0_SHIFT)) & DMA_COMMON_ABORT_ABORT0_MASK) - -#define DMA_COMMON_ABORT_ABORT1_MASK (0x2U) -#define DMA_COMMON_ABORT_ABORT1_SHIFT (1U) -/*! ABORT1 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT1_SHIFT)) & DMA_COMMON_ABORT_ABORT1_MASK) - -#define DMA_COMMON_ABORT_ABORT2_MASK (0x4U) -#define DMA_COMMON_ABORT_ABORT2_SHIFT (2U) -/*! ABORT2 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT2_SHIFT)) & DMA_COMMON_ABORT_ABORT2_MASK) - -#define DMA_COMMON_ABORT_ABORT3_MASK (0x8U) -#define DMA_COMMON_ABORT_ABORT3_SHIFT (3U) -/*! ABORT3 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT3_SHIFT)) & DMA_COMMON_ABORT_ABORT3_MASK) - -#define DMA_COMMON_ABORT_ABORT4_MASK (0x10U) -#define DMA_COMMON_ABORT_ABORT4_SHIFT (4U) -/*! ABORT4 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT4_SHIFT)) & DMA_COMMON_ABORT_ABORT4_MASK) - -#define DMA_COMMON_ABORT_ABORT5_MASK (0x20U) -#define DMA_COMMON_ABORT_ABORT5_SHIFT (5U) -/*! ABORT5 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT5_SHIFT)) & DMA_COMMON_ABORT_ABORT5_MASK) - -#define DMA_COMMON_ABORT_ABORT6_MASK (0x40U) -#define DMA_COMMON_ABORT_ABORT6_SHIFT (6U) -/*! ABORT6 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT6_SHIFT)) & DMA_COMMON_ABORT_ABORT6_MASK) - -#define DMA_COMMON_ABORT_ABORT7_MASK (0x80U) -#define DMA_COMMON_ABORT_ABORT7_SHIFT (7U) -/*! ABORT7 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT7_SHIFT)) & DMA_COMMON_ABORT_ABORT7_MASK) - -#define DMA_COMMON_ABORT_ABORT8_MASK (0x100U) -#define DMA_COMMON_ABORT_ABORT8_SHIFT (8U) -/*! ABORT8 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT8_SHIFT)) & DMA_COMMON_ABORT_ABORT8_MASK) - -#define DMA_COMMON_ABORT_ABORT9_MASK (0x200U) -#define DMA_COMMON_ABORT_ABORT9_SHIFT (9U) -/*! ABORT9 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT9_SHIFT)) & DMA_COMMON_ABORT_ABORT9_MASK) - -#define DMA_COMMON_ABORT_ABORT10_MASK (0x400U) -#define DMA_COMMON_ABORT_ABORT10_SHIFT (10U) -/*! ABORT10 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT10_SHIFT)) & DMA_COMMON_ABORT_ABORT10_MASK) - -#define DMA_COMMON_ABORT_ABORT11_MASK (0x800U) -#define DMA_COMMON_ABORT_ABORT11_SHIFT (11U) -/*! ABORT11 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT11_SHIFT)) & DMA_COMMON_ABORT_ABORT11_MASK) - -#define DMA_COMMON_ABORT_ABORT12_MASK (0x1000U) -#define DMA_COMMON_ABORT_ABORT12_SHIFT (12U) -/*! ABORT12 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT12_SHIFT)) & DMA_COMMON_ABORT_ABORT12_MASK) - -#define DMA_COMMON_ABORT_ABORT13_MASK (0x2000U) -#define DMA_COMMON_ABORT_ABORT13_SHIFT (13U) -/*! ABORT13 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT13_SHIFT)) & DMA_COMMON_ABORT_ABORT13_MASK) - -#define DMA_COMMON_ABORT_ABORT14_MASK (0x4000U) -#define DMA_COMMON_ABORT_ABORT14_SHIFT (14U) -/*! ABORT14 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT14_SHIFT)) & DMA_COMMON_ABORT_ABORT14_MASK) - -#define DMA_COMMON_ABORT_ABORT15_MASK (0x8000U) -#define DMA_COMMON_ABORT_ABORT15_SHIFT (15U) -/*! ABORT15 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT15_SHIFT)) & DMA_COMMON_ABORT_ABORT15_MASK) - -#define DMA_COMMON_ABORT_ABORT16_MASK (0x10000U) -#define DMA_COMMON_ABORT_ABORT16_SHIFT (16U) -/*! ABORT16 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT16_SHIFT)) & DMA_COMMON_ABORT_ABORT16_MASK) - -#define DMA_COMMON_ABORT_ABORT17_MASK (0x20000U) -#define DMA_COMMON_ABORT_ABORT17_SHIFT (17U) -/*! ABORT17 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT17_SHIFT)) & DMA_COMMON_ABORT_ABORT17_MASK) - -#define DMA_COMMON_ABORT_ABORT18_MASK (0x40000U) -#define DMA_COMMON_ABORT_ABORT18_SHIFT (18U) -/*! ABORT18 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT18_SHIFT)) & DMA_COMMON_ABORT_ABORT18_MASK) - -#define DMA_COMMON_ABORT_ABORT19_MASK (0x80000U) -#define DMA_COMMON_ABORT_ABORT19_SHIFT (19U) -/*! ABORT19 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT19_SHIFT)) & DMA_COMMON_ABORT_ABORT19_MASK) - -#define DMA_COMMON_ABORT_ABORT20_MASK (0x100000U) -#define DMA_COMMON_ABORT_ABORT20_SHIFT (20U) -/*! ABORT20 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT20_SHIFT)) & DMA_COMMON_ABORT_ABORT20_MASK) - -#define DMA_COMMON_ABORT_ABORT21_MASK (0x200000U) -#define DMA_COMMON_ABORT_ABORT21_SHIFT (21U) -/*! ABORT21 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT21_SHIFT)) & DMA_COMMON_ABORT_ABORT21_MASK) - -#define DMA_COMMON_ABORT_ABORT22_MASK (0x400000U) -#define DMA_COMMON_ABORT_ABORT22_SHIFT (22U) -/*! ABORT22 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT22_SHIFT)) & DMA_COMMON_ABORT_ABORT22_MASK) - -#define DMA_COMMON_ABORT_ABORT23_MASK (0x800000U) -#define DMA_COMMON_ABORT_ABORT23_SHIFT (23U) -/*! ABORT23 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT23_SHIFT)) & DMA_COMMON_ABORT_ABORT23_MASK) - -#define DMA_COMMON_ABORT_ABORT24_MASK (0x1000000U) -#define DMA_COMMON_ABORT_ABORT24_SHIFT (24U) -/*! ABORT24 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT24_SHIFT)) & DMA_COMMON_ABORT_ABORT24_MASK) - -#define DMA_COMMON_ABORT_ABORT25_MASK (0x2000000U) -#define DMA_COMMON_ABORT_ABORT25_SHIFT (25U) -/*! ABORT25 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT25_SHIFT)) & DMA_COMMON_ABORT_ABORT25_MASK) - -#define DMA_COMMON_ABORT_ABORT26_MASK (0x4000000U) -#define DMA_COMMON_ABORT_ABORT26_SHIFT (26U) -/*! ABORT26 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT26_SHIFT)) & DMA_COMMON_ABORT_ABORT26_MASK) - -#define DMA_COMMON_ABORT_ABORT27_MASK (0x8000000U) -#define DMA_COMMON_ABORT_ABORT27_SHIFT (27U) -/*! ABORT27 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT27_SHIFT)) & DMA_COMMON_ABORT_ABORT27_MASK) - -#define DMA_COMMON_ABORT_ABORT28_MASK (0x10000000U) -#define DMA_COMMON_ABORT_ABORT28_SHIFT (28U) -/*! ABORT28 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT28_SHIFT)) & DMA_COMMON_ABORT_ABORT28_MASK) - -#define DMA_COMMON_ABORT_ABORT29_MASK (0x20000000U) -#define DMA_COMMON_ABORT_ABORT29_SHIFT (29U) -/*! ABORT29 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT29_SHIFT)) & DMA_COMMON_ABORT_ABORT29_MASK) - -#define DMA_COMMON_ABORT_ABORT30_MASK (0x40000000U) -#define DMA_COMMON_ABORT_ABORT30_SHIFT (30U) -/*! ABORT30 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT30_SHIFT)) & DMA_COMMON_ABORT_ABORT30_MASK) - -#define DMA_COMMON_ABORT_ABORT31_MASK (0x80000000U) -#define DMA_COMMON_ABORT_ABORT31_SHIFT (31U) -/*! ABORT31 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT_ABORT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT31_SHIFT)) & DMA_COMMON_ABORT_ABORT31_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ABORT */ -#define DMA_COMMON_ABORT_COUNT (1U) - -/*! @name COMMON_ABORT1 - Channel Abort control for all DMA channels */ -/*! @{ */ - -#define DMA_COMMON_ABORT1_ABORT32_MASK (0x1U) -#define DMA_COMMON_ABORT1_ABORT32_SHIFT (0U) -/*! ABORT32 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT1_ABORT32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT32_SHIFT)) & DMA_COMMON_ABORT1_ABORT32_MASK) - -#define DMA_COMMON_ABORT1_ABORT33_MASK (0x2U) -#define DMA_COMMON_ABORT1_ABORT33_SHIFT (1U) -/*! ABORT33 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT1_ABORT33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT33_SHIFT)) & DMA_COMMON_ABORT1_ABORT33_MASK) - -#define DMA_COMMON_ABORT1_ABORT34_MASK (0x4U) -#define DMA_COMMON_ABORT1_ABORT34_SHIFT (2U) -/*! ABORT34 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT1_ABORT34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT34_SHIFT)) & DMA_COMMON_ABORT1_ABORT34_MASK) - -#define DMA_COMMON_ABORT1_ABORT35_MASK (0x8U) -#define DMA_COMMON_ABORT1_ABORT35_SHIFT (3U) -/*! ABORT35 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT1_ABORT35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT35_SHIFT)) & DMA_COMMON_ABORT1_ABORT35_MASK) - -#define DMA_COMMON_ABORT1_ABORT36_MASK (0x10U) -#define DMA_COMMON_ABORT1_ABORT36_SHIFT (4U) -/*! ABORT36 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT1_ABORT36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT36_SHIFT)) & DMA_COMMON_ABORT1_ABORT36_MASK) - -#define DMA_COMMON_ABORT1_ABORT37_MASK (0x20U) -#define DMA_COMMON_ABORT1_ABORT37_SHIFT (5U) -/*! ABORT37 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT1_ABORT37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT37_SHIFT)) & DMA_COMMON_ABORT1_ABORT37_MASK) - -#define DMA_COMMON_ABORT1_ABORT38_MASK (0x40U) -#define DMA_COMMON_ABORT1_ABORT38_SHIFT (6U) -/*! ABORT38 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT1_ABORT38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT38_SHIFT)) & DMA_COMMON_ABORT1_ABORT38_MASK) - -#define DMA_COMMON_ABORT1_ABORT39_MASK (0x80U) -#define DMA_COMMON_ABORT1_ABORT39_SHIFT (7U) -/*! ABORT39 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT1_ABORT39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT39_SHIFT)) & DMA_COMMON_ABORT1_ABORT39_MASK) - -#define DMA_COMMON_ABORT1_ABORT40_MASK (0x100U) -#define DMA_COMMON_ABORT1_ABORT40_SHIFT (8U) -/*! ABORT40 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT1_ABORT40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT40_SHIFT)) & DMA_COMMON_ABORT1_ABORT40_MASK) - -#define DMA_COMMON_ABORT1_ABORT41_MASK (0x200U) -#define DMA_COMMON_ABORT1_ABORT41_SHIFT (9U) -/*! ABORT41 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT1_ABORT41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT41_SHIFT)) & DMA_COMMON_ABORT1_ABORT41_MASK) - -#define DMA_COMMON_ABORT1_ABORT42_MASK (0x400U) -#define DMA_COMMON_ABORT1_ABORT42_SHIFT (10U) -/*! ABORT42 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT1_ABORT42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT42_SHIFT)) & DMA_COMMON_ABORT1_ABORT42_MASK) - -#define DMA_COMMON_ABORT1_ABORT43_MASK (0x800U) -#define DMA_COMMON_ABORT1_ABORT43_SHIFT (11U) -/*! ABORT43 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT1_ABORT43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT43_SHIFT)) & DMA_COMMON_ABORT1_ABORT43_MASK) - -#define DMA_COMMON_ABORT1_ABORT44_MASK (0x1000U) -#define DMA_COMMON_ABORT1_ABORT44_SHIFT (12U) -/*! ABORT44 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT1_ABORT44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT44_SHIFT)) & DMA_COMMON_ABORT1_ABORT44_MASK) - -#define DMA_COMMON_ABORT1_ABORT45_MASK (0x2000U) -#define DMA_COMMON_ABORT1_ABORT45_SHIFT (13U) -/*! ABORT45 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT1_ABORT45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT45_SHIFT)) & DMA_COMMON_ABORT1_ABORT45_MASK) - -#define DMA_COMMON_ABORT1_ABORT46_MASK (0x4000U) -#define DMA_COMMON_ABORT1_ABORT46_SHIFT (14U) -/*! ABORT46 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT1_ABORT46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT46_SHIFT)) & DMA_COMMON_ABORT1_ABORT46_MASK) - -#define DMA_COMMON_ABORT1_ABORT47_MASK (0x8000U) -#define DMA_COMMON_ABORT1_ABORT47_SHIFT (15U) -/*! ABORT47 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT1_ABORT47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT47_SHIFT)) & DMA_COMMON_ABORT1_ABORT47_MASK) - -#define DMA_COMMON_ABORT1_ABORT48_MASK (0x10000U) -#define DMA_COMMON_ABORT1_ABORT48_SHIFT (16U) -/*! ABORT48 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT1_ABORT48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT48_SHIFT)) & DMA_COMMON_ABORT1_ABORT48_MASK) - -#define DMA_COMMON_ABORT1_ABORT49_MASK (0x20000U) -#define DMA_COMMON_ABORT1_ABORT49_SHIFT (17U) -/*! ABORT49 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT1_ABORT49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT49_SHIFT)) & DMA_COMMON_ABORT1_ABORT49_MASK) - -#define DMA_COMMON_ABORT1_ABORT50_MASK (0x40000U) -#define DMA_COMMON_ABORT1_ABORT50_SHIFT (18U) -/*! ABORT50 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT1_ABORT50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT50_SHIFT)) & DMA_COMMON_ABORT1_ABORT50_MASK) - -#define DMA_COMMON_ABORT1_ABORT51_MASK (0x80000U) -#define DMA_COMMON_ABORT1_ABORT51_SHIFT (19U) -/*! ABORT51 - Abort control for DMA channel. - * 0b0..No effect. - * 0b1..Aborts DMA operations on channel. - */ -#define DMA_COMMON_ABORT1_ABORT51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT51_SHIFT)) & DMA_COMMON_ABORT1_ABORT51_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ABORT1 */ -#define DMA_COMMON_ABORT1_COUNT (1U) - -/*! @name CHANNEL_CFG - Configuration register for DMA channel */ -/*! @{ */ - -#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) -#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) -/*! PERIPHREQEN - Peripheral request Enable. - * 0b0..Peripheral DMA requests disabled. - * 0b1..Peripheral DMA requests enabled. - */ -#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) - -#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) -#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) -/*! HWTRIGEN - Hardware Triggering Enable for channel. - * 0b0..Hardware triggering not used for channel. - * 0b1..Hardware triggering used for channel. - */ -#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) - -#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) -#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) -/*! TRIGPOL - Trigger Polarity. - * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. - * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. - */ -#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) - -#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) -#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) -/*! TRIGTYPE - Trigger Type. - * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. - * 0b1..Level. - */ -#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) - -#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) -#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) -/*! TRIGBURST - Trigger Burst. - * 0b0..Single transfer. - * 0b1..Burst transfer. - */ -#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) - -#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) -#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) -/*! BURSTPOWER - Burst Power. - */ -#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) - -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) -/*! SRCBURSTWRAP - Source Burst Wrap. - * 0b0..Disabled. - * 0b1..Enabled. - */ -#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) - -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) -/*! DSTBURSTWRAP - Destination Burst Wrap. - * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. - * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. - */ -#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) - -#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) -#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) -/*! CHPRIORITY - Priority of channel when multiple DMA requests are pending. - */ -#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CFG */ -#define DMA_CHANNEL_CFG_COUNT (52U) - -/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel */ -/*! @{ */ - -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) -/*! VALIDPENDING - Valid pending flag for this channel. - * 0b0..No effect on DMA operation. - * 0b1..Valid pending. - */ -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) - -#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) -#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) -/*! TRIG - Trigger flag. - * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. - * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. - */ -#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CTLSTAT */ -#define DMA_CHANNEL_CTLSTAT_COUNT (52U) - -/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel */ -/*! @{ */ - -#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) -#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) -/*! CFGVALID - Configuration Valid flag. - * 0b0..Not valid. - * 0b1..Valid. - */ -#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) - -#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) -#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) -/*! RELOAD - Reload. - * 0b0..Disabled. The channels' control structure should not be reloaded when the current descriptor is exhausted. - * 0b1..Enabled. The channels' control structure should be reloaded when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) - -#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) -#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) -/*! SWTRIG - Software Trigger. - * 0b0..Not set. - * 0b1..Set. - */ -#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) - -#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) -#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) -/*! CLRTRIG - Clear Trigger. - * 0b0..Not cleared. - * 0b1..Cleared. - */ -#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) - -#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) -#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) -/*! SETINTA - Set Interrupt flag A for channel. - * 0b0..No effect. - * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) - -#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) -#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) -/*! SETINTB - Set Interrupt flag B for channel. - * 0b0..No effect. - * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) - -#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) -#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) -/*! WIDTH - Transfer width used for this DMA channel. - * 0b00..8-bit. - * 0b01..16-bit. - * 0b10..32-bit. - * 0b11..Reserved. - */ -#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) - -#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) -#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) -/*! SRCINC - Source address increment - * 0b00..No increment. - * 0b01..1 x width. - * 0b10..2 x width. - * 0b11..4 x width. - */ -#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) - -#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) -#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) -/*! DSTINC - Destination address increment - * 0b00..No increment. - * 0b01..1 x width. - * 0b10..2 x width. - * 0b11..4 x width. - */ -#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) - -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) -/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. - */ -#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_XFERCFG */ -#define DMA_CHANNEL_XFERCFG_COUNT (52U) - - -/*! - * @} - */ /* end of group DMA_Register_Masks */ - - -/* DMA - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral DMA0 base address */ - #define DMA0_BASE (0x50082000u) - /** Peripheral DMA0 base address */ - #define DMA0_BASE_NS (0x40082000u) - /** Peripheral DMA0 base pointer */ - #define DMA0 ((DMA_Type *)DMA0_BASE) - /** Peripheral DMA0 base pointer */ - #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) - /** Peripheral DMA1 base address */ - #define DMA1_BASE (0x500A7000u) - /** Peripheral DMA1 base address */ - #define DMA1_BASE_NS (0x400A7000u) - /** Peripheral DMA1 base pointer */ - #define DMA1 ((DMA_Type *)DMA1_BASE) - /** Peripheral DMA1 base pointer */ - #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS { DMA0, DMA1 } - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } -#else - /** Peripheral DMA0 base address */ - #define DMA0_BASE (0x40082000u) - /** Peripheral DMA0 base pointer */ - #define DMA0 ((DMA_Type *)DMA0_BASE) - /** Peripheral DMA1 base address */ - #define DMA1_BASE (0x400A7000u) - /** Peripheral DMA1 base pointer */ - #define DMA1 ((DMA_Type *)DMA1_BASE) - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS { DMA0, DMA1 } -#endif -/** Interrupt vectors for the DMA peripheral type */ -#define DMA_IRQS { DMA0_IRQn, DMA1_IRQn } - -/*! - * @} - */ /* end of group DMA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMIC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer - * @{ - */ - -/** DMIC - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x100 */ - __IO uint32_t OSR; /**< Oversample Rate, array offset: 0x0, array step: 0x100 */ - __IO uint32_t DIVHFCLK; /**< DMIC Clock, array offset: 0x4, array step: 0x100 */ - __IO uint32_t PREAC2FSCOEF; /**< Compensation Filter for 2 FS, array offset: 0x8, array step: 0x100 */ - __IO uint32_t PREAC4FSCOEF; /**< Compensation Filter for 4 FS, array offset: 0xC, array step: 0x100 */ - __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift, array offset: 0x10, array step: 0x100 */ - uint8_t RESERVED_0[108]; - __IO uint32_t FIFO_CTRL; /**< FIFO Control, array offset: 0x80, array step: 0x100 */ - __IO uint32_t FIFO_STATUS; /**< FIFO Status, array offset: 0x84, array step: 0x100 */ - __I uint32_t FIFO_DATA; /**< FIFO Data, array offset: 0x88, array step: 0x100 */ - __IO uint32_t PHY_CTRL; /**< Physical Control, array offset: 0x8C, array step: 0x100 */ - __IO uint32_t DC_CTRL; /**< DC Filter Control, array offset: 0x90, array step: 0x100 */ - uint8_t RESERVED_1[108]; - } CHANNEL[2]; - uint8_t RESERVED_0[3328]; - __IO uint32_t CHANEN; /**< Channel Enable, offset: 0xF00 */ - uint8_t RESERVED_1[12]; - __IO uint32_t USE2FS; /**< Use 2 FS register, offset: 0xF10 */ - __IO uint32_t GLOBAL_SYNC_EN; /**< Global Channel Synchronization Enable, offset: 0xF14 */ - __IO uint32_t GLOBAL_COUNT_VAL; /**< Global channel synchronization counter value, offset: 0xF18 */ - __IO uint32_t DECRESET; /**< DMIC decimator reset, offset: 0xF1C */ - uint8_t RESERVED_2[96]; - __IO uint32_t HWVADGAIN; /**< HWVAD Input Gain, offset: 0xF80 */ - __IO uint32_t HWVADHPFS; /**< HWVAD Filter Control, offset: 0xF84 */ - __IO uint32_t HWVADST10; /**< HWVAD Control, offset: 0xF88 */ - __IO uint32_t HWVADRSTT; /**< HWVAD Filter Reset, offset: 0xF8C */ - __IO uint32_t HWVADTHGN; /**< HWVAD Noise Estimator Gain, offset: 0xF90 */ - __IO uint32_t HWVADTHGS; /**< HWVAD Signal Estimator Gain, offset: 0xF94 */ - __I uint32_t HWVADLOWZ; /**< HWVAD Noise Envelope Estimator, offset: 0xF98 */ -} DMIC_Type; - -/* ---------------------------------------------------------------------------- - -- DMIC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMIC_Register_Masks DMIC Register Masks - * @{ - */ - -/*! @name CHANNEL_OSR - Oversample Rate */ -/*! @{ */ - -#define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU) -#define DMIC_CHANNEL_OSR_OSR_SHIFT (0U) -/*! OSR - Oversample Rate - */ -#define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_OSR */ -#define DMIC_CHANNEL_OSR_COUNT (2U) - -/*! @name CHANNEL_DIVHFCLK - DMIC Clock */ -/*! @{ */ - -#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU) -#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U) -/*! PDMDIV - PDM Clock Divider Value - * 0b0000..Divide by 1 - * 0b0001..Divide by 2 - * 0b0010..Divide by 3 - * 0b0011..Divide by 4 - * 0b0100..Divide by 6 - * 0b0101..Divide by 8 - * 0b0110..Divide by 12 - * 0b0111..Divide by 16 - * 0b1000..Divide by 24 - * 0b1001..Divide by 32 - * 0b1010..Divide by 48 - * 0b1011..Divide by 64 - * 0b1100..Divide by 96 - * 0b1101..Divide by 128 - * 0b1110-0b1111..Reserved - */ -#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_DIVHFCLK */ -#define DMIC_CHANNEL_DIVHFCLK_COUNT (2U) - -/*! @name CHANNEL_PREAC2FSCOEF - Compensation Filter for 2 FS */ -/*! @{ */ - -#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U) -#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U) -/*! COMP - Compensation value - * 0b00..Compensation = 0. This is the recommended setting. - * 0b01..Compensation = -0.16 - * 0b10..Compensation = -0.15 - * 0b11..Compensation = -0.13 - */ -#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_PREAC2FSCOEF */ -#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U) - -/*! @name CHANNEL_PREAC4FSCOEF - Compensation Filter for 4 FS */ -/*! @{ */ - -#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U) -#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U) -/*! COMP - Compensation value - * 0b00..Compensation = 0. This is the recommended setting. - * 0b01..Compensation = -0.16 - * 0b10..Compensation = -0.15 - * 0b11..Compensation = -0.13 - */ -#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_PREAC4FSCOEF */ -#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U) - -/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift */ -/*! @{ */ - -#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x1FU) -#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U) -/*! GAIN - Gain - */ -#define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_GAINSHIFT */ -#define DMIC_CHANNEL_GAINSHIFT_COUNT (2U) - -/*! @name CHANNEL_FIFO_CTRL - FIFO Control */ -/*! @{ */ - -#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U) -#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U) -/*! ENABLE - FIFO Enable. - * 0b0..Disabled. - * 0b1..FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register. - */ -#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK) - -#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U) -#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U) -/*! RESETN - FIFO Reset - * 0b0..Reset the FIFO. This must be cleared before resuming operation. - * 0b1..Normal operation - */ -#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK) - -#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U) -#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U) -/*! INTEN - Interrupt Enable. - * 0b0..FIFO level interrupts are not enabled. - * 0b1..FIFO level interrupts are enabled. - */ -#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK) - -#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U) -#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U) -/*! DMAEN - DMA Enable - * 0b0..DMA requests are not enabled. - * 0b1..DMA requests based on FIFO level are enabled. - */ -#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK) - -#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U) -#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U) -/*! TRIGLVL - FIFO Trigger Level for Interrupt - * 0b00000..Trigger when the FIFO has received one entry (is no longer empty). - * 0b00001..Trigger when the FIFO has received two entries. - * 0b01110..Trigger when the FIFO has received 15 entries. - * 0b01111..Trigger when the FIFO has received 16 entries (has become full). - */ -#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_FIFO_CTRL */ -#define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U) - -/*! @name CHANNEL_FIFO_STATUS - FIFO Status */ -/*! @{ */ - -#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U) -#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U) -/*! INT - Status of Interrupt (write 1 to clear) - */ -#define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK) - -#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U) -#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U) -/*! OVERRUN - Overrun Detected (write 1 to clear) - */ -#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK) - -#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U) -#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U) -/*! UNDERRUN - Underrun Detected (write 1 to clear) - */ -#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_FIFO_STATUS */ -#define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U) - -/*! @name CHANNEL_FIFO_DATA - FIFO Data */ -/*! @{ */ - -#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU) -#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U) -/*! DATA - PCM Data - */ -#define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_FIFO_DATA */ -#define DMIC_CHANNEL_FIFO_DATA_COUNT (2U) - -/*! @name CHANNEL_PHY_CTRL - Physical Control */ -/*! @{ */ - -#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U) -#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U) -/*! PHY_FALL - Capture DMIC on Falling edge (0 means on rising) - * 0b0..Capture PDM_DATA on the rising edge of PDM_CLK. - * 0b1..Capture PDM_DATA on the falling edge of PDM_CLK. - */ -#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK) - -#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U) -#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U) -/*! PHY_HALF - Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing) - * 0b0..Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing. - * 0b1..Use half rate sampling. The clock to the DMIC is sent at half the rate that the decimator is providing. - */ -#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_PHY_CTRL */ -#define DMIC_CHANNEL_PHY_CTRL_COUNT (2U) - -/*! @name CHANNEL_DC_CTRL - DC Filter Control */ -/*! @{ */ - -#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U) -#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U) -/*! DCPOLE - DC Block Filter - * 0b00..Flat Response, no filter - * 0b01..155 Hz - * 0b10..78 Hz - * 0b11..39 Hz - */ -#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK) - -#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U) -#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U) -/*! DCGAIN - DC Gain - */ -#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK) - -#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U) -#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U) -/*! SATURATEAT16BIT - Saturate at 16 Bit - * 0b0..Do not Saturate. Results roll over if out range and do not saturate. - * 0b1..Saturate. If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow. - */ -#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK) - -#define DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_MASK (0x200U) -#define DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_SHIFT (9U) -/*! SIGNEXTEND - Sign Extend - * 0b0..Disabled - * 0b1..Enabled - */ -#define DMIC_CHANNEL_DC_CTRL_SIGNEXTEND(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_MASK) -/*! @} */ - -/* The count of DMIC_CHANNEL_DC_CTRL */ -#define DMIC_CHANNEL_DC_CTRL_COUNT (2U) - -/*! @name CHANEN - Channel Enable */ -/*! @{ */ - -#define DMIC_CHANEN_EN_CH0_MASK (0x1U) -#define DMIC_CHANEN_EN_CH0_SHIFT (0U) -/*! EN_CH0 - Enable Channel n - * 0b0..PDM channel n is disabled. - * 0b1..PDM channel n is enabled. - */ -#define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK) - -#define DMIC_CHANEN_EN_CH1_MASK (0x2U) -#define DMIC_CHANEN_EN_CH1_SHIFT (1U) -/*! EN_CH1 - Enable Channel n - * 0b0..PDM channel n is disabled. - * 0b1..PDM channel n is enabled. - */ -#define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK) -/*! @} */ - -/*! @name USE2FS - Use 2 FS register */ -/*! @{ */ - -#define DMIC_USE2FS_USE2FS_MASK (0x1U) -#define DMIC_USE2FS_USE2FS_SHIFT (0U) -/*! USE2FS - Use 2FS register - * 0b0..Use 1 FS output for PCM data. - * 0b1..Use 2 FS output for PCM data. - */ -#define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK) -/*! @} */ - -/*! @name GLOBAL_SYNC_EN - Global Channel Synchronization Enable */ -/*! @{ */ - -#define DMIC_GLOBAL_SYNC_EN_CH_SYNC_EN_MASK (0x3U) -#define DMIC_GLOBAL_SYNC_EN_CH_SYNC_EN_SHIFT (0U) -/*! CH_SYNC_EN - Channel synch enable - */ -#define DMIC_GLOBAL_SYNC_EN_CH_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_GLOBAL_SYNC_EN_CH_SYNC_EN_SHIFT)) & DMIC_GLOBAL_SYNC_EN_CH_SYNC_EN_MASK) -/*! @} */ - -/*! @name GLOBAL_COUNT_VAL - Global channel synchronization counter value */ -/*! @{ */ - -#define DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL_MASK (0xFFFFFFFFU) -#define DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL_SHIFT (0U) -/*! CCOUNTVAL - Channel Counter Value - */ -#define DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL_SHIFT)) & DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL_MASK) -/*! @} */ - -/*! @name DECRESET - DMIC decimator reset */ -/*! @{ */ - -#define DMIC_DECRESET_DECRESET_MASK (0x3U) -#define DMIC_DECRESET_DECRESET_SHIFT (0U) -/*! DECRESET - Decimator reset - * 0b00..Disable - * 0b01..Enable - */ -#define DMIC_DECRESET_DECRESET(x) (((uint32_t)(((uint32_t)(x)) << DMIC_DECRESET_DECRESET_SHIFT)) & DMIC_DECRESET_DECRESET_MASK) -/*! @} */ - -/*! @name HWVADGAIN - HWVAD Input Gain */ -/*! @{ */ - -#define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU) -#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U) -/*! INPUTGAIN - Input Gain - * 0b0000..-10 bits - * 0b0001..-8 bits - * 0b0010..-6 bits - * 0b0011..-4 bits - * 0b0100..-2 bits - * 0b0101..0 bits (default) - * 0b0110..+2 bits - * 0b0111..+4 bits - * 0b1000..+6 bits - * 0b1001..+8 bits - * 0b1010..+10 bits - * 0b1011..+12 bits - * 0b1100..+14 bits - * 0b1101-0b1111..Reserved - */ -#define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK) -/*! @} */ - -/*! @name HWVADHPFS - HWVAD Filter Control */ -/*! @{ */ - -#define DMIC_HWVADHPFS_HPFS_MASK (0x3U) -#define DMIC_HWVADHPFS_HPFS_SHIFT (0U) -/*! HPFS - The HPFS field chooses the High Pass filter in first part of HWVAD. - * 0b00..Bypass - * 0b01..High Pass 1750 Hz - * 0b10..High Pass 215 Hz - * 0b11..Reserved - */ -#define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK) -/*! @} */ - -/*! @name HWVADST10 - HWVAD Control */ -/*! @{ */ - -#define DMIC_HWVADST10_ST10_MASK (0x1U) -#define DMIC_HWVADST10_ST10_SHIFT (0U) -/*! ST10 - STAGE 1 - * 0b0..Normal operation, waiting for HWVAD trigger event (stage 0). - * 0b1..Reset internal interrupt flag by writing a '1' (stage 1) pulse. - */ -#define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK) -/*! @} */ - -/*! @name HWVADRSTT - HWVAD Filter Reset */ -/*! @{ */ - -#define DMIC_HWVADRSTT_RSST_MASK (0x1U) -#define DMIC_HWVADRSTT_RSST_SHIFT (0U) -/*! RSST - Reset HWVAD - */ -#define DMIC_HWVADRSTT_RSST(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSST_SHIFT)) & DMIC_HWVADRSTT_RSST_MASK) -/*! @} */ - -/*! @name HWVADTHGN - HWVAD Noise Estimator Gain */ -/*! @{ */ - -#define DMIC_HWVADTHGN_THGN_MASK (0xFU) -#define DMIC_HWVADTHGN_THGN_SHIFT (0U) -/*! THGN - Gain Factor for Noise Estimator - */ -#define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK) -/*! @} */ - -/*! @name HWVADTHGS - HWVAD Signal Estimator Gain */ -/*! @{ */ - -#define DMIC_HWVADTHGS_THGS_MASK (0xFU) -#define DMIC_HWVADTHGS_THGS_SHIFT (0U) -/*! THGS - Signal Gain Factor - */ -#define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK) -/*! @} */ - -/*! @name HWVADLOWZ - HWVAD Noise Envelope Estimator */ -/*! @{ */ - -#define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU) -#define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U) -/*! LOWZ - Average Noise-floor Value - */ -#define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group DMIC_Register_Masks */ - - -/* DMIC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral DMIC0 base address */ - #define DMIC0_BASE (0x50090000u) - /** Peripheral DMIC0 base address */ - #define DMIC0_BASE_NS (0x40090000u) - /** Peripheral DMIC0 base pointer */ - #define DMIC0 ((DMIC_Type *)DMIC0_BASE) - /** Peripheral DMIC0 base pointer */ - #define DMIC0_NS ((DMIC_Type *)DMIC0_BASE_NS) - /** Array initializer of DMIC peripheral base addresses */ - #define DMIC_BASE_ADDRS { DMIC0_BASE } - /** Array initializer of DMIC peripheral base pointers */ - #define DMIC_BASE_PTRS { DMIC0 } - /** Array initializer of DMIC peripheral base addresses */ - #define DMIC_BASE_ADDRS_NS { DMIC0_BASE_NS } - /** Array initializer of DMIC peripheral base pointers */ - #define DMIC_BASE_PTRS_NS { DMIC0_NS } -#else - /** Peripheral DMIC0 base address */ - #define DMIC0_BASE (0x40090000u) - /** Peripheral DMIC0 base pointer */ - #define DMIC0 ((DMIC_Type *)DMIC0_BASE) - /** Array initializer of DMIC peripheral base addresses */ - #define DMIC_BASE_ADDRS { DMIC0_BASE } - /** Array initializer of DMIC peripheral base pointers */ - #define DMIC_BASE_PTRS { DMIC0 } -#endif -/** Interrupt vectors for the DMIC peripheral type */ -#define DMIC_IRQS { DMIC_IRQn } -#define DMIC_HWVAD_IRQS { HWVAD0_IRQn } - -/*! - * @} - */ /* end of group DMIC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ENC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ENC_Peripheral_Access_Layer ENC Peripheral Access Layer - * @{ - */ - -/** ENC - Register Layout Typedef */ -typedef struct { - __IO uint16_t CTRL; /**< Control Register, offset: 0x0 */ - __IO uint16_t FILT; /**< Input Filter Register, offset: 0x2 */ - __IO uint16_t WTR; /**< Watchdog Timeout Register, offset: 0x4 */ - __IO uint16_t POSD; /**< Position Difference Counter Register, offset: 0x6 */ - __I uint16_t POSDH; /**< Position Difference Hold Register, offset: 0x8 */ - __IO uint16_t REV; /**< Revolution Counter Register, offset: 0xA */ - __I uint16_t REVH; /**< Revolution Hold Register, offset: 0xC */ - __IO uint16_t UPOS; /**< Upper Position Counter Register, offset: 0xE */ - __IO uint16_t LPOS; /**< Lower Position Counter Register, offset: 0x10 */ - __I uint16_t UPOSH; /**< Upper Position Hold Register, offset: 0x12 */ - __I uint16_t LPOSH; /**< Lower Position Hold Register, offset: 0x14 */ - __IO uint16_t UINIT; /**< Upper Initialization Register, offset: 0x16 */ - __IO uint16_t LINIT; /**< Lower Initialization Register, offset: 0x18 */ - __I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */ - __IO uint16_t TST; /**< Test Register, offset: 0x1C */ - __IO uint16_t CTRL2; /**< Control 2 Register, offset: 0x1E */ - __IO uint16_t UMOD; /**< Upper Modulus Register, offset: 0x20 */ - __IO uint16_t LMOD; /**< Lower Modulus Register, offset: 0x22 */ - __IO uint16_t UCOMP; /**< Upper Position Compare Register, offset: 0x24 */ - __IO uint16_t LCOMP; /**< Lower Position Compare Register, offset: 0x26 */ - __I uint16_t LASTEDGE; /**< Last Edge Time Register, offset: 0x28 */ - __I uint16_t LASTEDGEH; /**< Last Edge Time Hold Register, offset: 0x2A */ - __I uint16_t POSDPER; /**< Position Difference Period Counter Register, offset: 0x2C */ - __I uint16_t POSDPERBFR; /**< Position Difference Period Buffer Register, offset: 0x2E */ - __I uint16_t POSDPERH; /**< Position Difference Period Hold Register, offset: 0x30 */ - __IO uint16_t CTRL3; /**< Control 3 Register, offset: 0x32 */ -} ENC_Type; - -/* ---------------------------------------------------------------------------- - -- ENC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ENC_Register_Masks ENC Register Masks - * @{ - */ - -/*! @name CTRL - Control Register */ -/*! @{ */ - -#define ENC_CTRL_CMPIE_MASK (0x1U) -#define ENC_CTRL_CMPIE_SHIFT (0U) -/*! CMPIE - Compare Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK) - -#define ENC_CTRL_CMPIRQ_MASK (0x2U) -#define ENC_CTRL_CMPIRQ_SHIFT (1U) -/*! CMPIRQ - Compare Interrupt Request - * 0b0..No match has occurred (the counter does not match the COMP value) - * 0b1..COMP match has occurred (the counter matches the COMP value) - */ -#define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK) - -#define ENC_CTRL_WDE_MASK (0x4U) -#define ENC_CTRL_WDE_SHIFT (2U) -/*! WDE - Watchdog Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK) - -#define ENC_CTRL_DIE_MASK (0x8U) -#define ENC_CTRL_DIE_SHIFT (3U) -/*! DIE - Watchdog Timeout Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK) - -#define ENC_CTRL_DIRQ_MASK (0x10U) -#define ENC_CTRL_DIRQ_SHIFT (4U) -/*! DIRQ - Watchdog Timeout Interrupt Request - * 0b0..No Watchdog timeout interrupt has occurred - * 0b1..Watchdog timeout interrupt has occurred - */ -#define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK) - -#define ENC_CTRL_XNE_MASK (0x20U) -#define ENC_CTRL_XNE_SHIFT (5U) -/*! XNE - Use Negative Edge of INDEX Pulse - * 0b0..Use positive edge of INDEX pulse - * 0b1..Use negative edge of INDEX pulse - */ -#define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK) - -#define ENC_CTRL_XIP_MASK (0x40U) -#define ENC_CTRL_XIP_SHIFT (6U) -/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS - * 0b0..INDEX pulse does not initialize the position counter - * 0b1..INDEX pulse initializes the position counter - */ -#define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK) - -#define ENC_CTRL_XIE_MASK (0x80U) -#define ENC_CTRL_XIE_SHIFT (7U) -/*! XIE - INDEX Pulse Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK) - -#define ENC_CTRL_XIRQ_MASK (0x100U) -#define ENC_CTRL_XIRQ_SHIFT (8U) -/*! XIRQ - INDEX Pulse Interrupt Request - * 0b0..INDEX pulse has not occurred - * 0b1..INDEX pulse has occurred - */ -#define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK) - -#define ENC_CTRL_PH1_MASK (0x200U) -#define ENC_CTRL_PH1_SHIFT (9U) -/*! PH1 - Enable Signal Phase Count Mode - * 0b0..Use the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal. - * 0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The - * PHASEB input and the REV bit control the counter direction: If CTRL[REV] = 0, PHASEB = 0, then count up If - * CTRL[REV] = 1, PHASEB = 1, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, - * PHASEB = 0, then count down - */ -#define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK) - -#define ENC_CTRL_REV_MASK (0x400U) -#define ENC_CTRL_REV_SHIFT (10U) -/*! REV - Enable Reverse Direction Counting - * 0b0..Count normally - * 0b1..Count in the reverse direction - */ -#define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK) - -#define ENC_CTRL_SWIP_MASK (0x800U) -#define ENC_CTRL_SWIP_SHIFT (11U) -/*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS - * 0b0..No action - * 0b1..Initialize position counter (using upper and lower initialization registers, UINIT and LINIT) - */ -#define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK) - -#define ENC_CTRL_HNE_MASK (0x1000U) -#define ENC_CTRL_HNE_SHIFT (12U) -/*! HNE - Use Negative Edge of HOME Input - * 0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS - * 0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS - */ -#define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK) - -#define ENC_CTRL_HIP_MASK (0x2000U) -#define ENC_CTRL_HIP_SHIFT (13U) -/*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS - * 0b0..No action - * 0b1..HOME signal initializes the position counter - */ -#define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK) - -#define ENC_CTRL_HIE_MASK (0x4000U) -#define ENC_CTRL_HIE_SHIFT (14U) -/*! HIE - HOME Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK) - -#define ENC_CTRL_HIRQ_MASK (0x8000U) -#define ENC_CTRL_HIRQ_SHIFT (15U) -/*! HIRQ - HOME Signal Transition Interrupt Request - * 0b0..No transition on the HOME signal has occurred - * 0b1..A transition on the HOME signal has occurred - */ -#define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK) -/*! @} */ - -/*! @name FILT - Input Filter Register */ -/*! @{ */ - -#define ENC_FILT_FILT_PER_MASK (0xFFU) -#define ENC_FILT_FILT_PER_SHIFT (0U) -/*! FILT_PER - Input Filter Sample Period - */ -#define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK) - -#define ENC_FILT_FILT_CNT_MASK (0x700U) -#define ENC_FILT_FILT_CNT_SHIFT (8U) -/*! FILT_CNT - Input Filter Sample Count - */ -#define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK) - -#define ENC_FILT_FILT_PRSC_MASK (0xE000U) -#define ENC_FILT_FILT_PRSC_SHIFT (13U) -/*! FILT_PRSC - prescaler divide IPbus clock to FILT clk - */ -#define ENC_FILT_FILT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PRSC_SHIFT)) & ENC_FILT_FILT_PRSC_MASK) -/*! @} */ - -/*! @name WTR - Watchdog Timeout Register */ -/*! @{ */ - -#define ENC_WTR_WDOG_MASK (0xFFFFU) -#define ENC_WTR_WDOG_SHIFT (0U) -/*! WDOG - WDOG - */ -#define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK) -/*! @} */ - -/*! @name POSD - Position Difference Counter Register */ -/*! @{ */ - -#define ENC_POSD_POSD_MASK (0xFFFFU) -#define ENC_POSD_POSD_SHIFT (0U) -/*! POSD - POSD - */ -#define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK) -/*! @} */ - -/*! @name POSDH - Position Difference Hold Register */ -/*! @{ */ - -#define ENC_POSDH_POSDH_MASK (0xFFFFU) -#define ENC_POSDH_POSDH_SHIFT (0U) -/*! POSDH - POSDH - */ -#define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK) -/*! @} */ - -/*! @name REV - Revolution Counter Register */ -/*! @{ */ - -#define ENC_REV_REV_MASK (0xFFFFU) -#define ENC_REV_REV_SHIFT (0U) -/*! REV - REV - */ -#define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK) -/*! @} */ - -/*! @name REVH - Revolution Hold Register */ -/*! @{ */ - -#define ENC_REVH_REVH_MASK (0xFFFFU) -#define ENC_REVH_REVH_SHIFT (0U) -/*! REVH - REVH - */ -#define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK) -/*! @} */ - -/*! @name UPOS - Upper Position Counter Register */ -/*! @{ */ - -#define ENC_UPOS_POS_MASK (0xFFFFU) -#define ENC_UPOS_POS_SHIFT (0U) -/*! POS - POS - */ -#define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK) -/*! @} */ - -/*! @name LPOS - Lower Position Counter Register */ -/*! @{ */ - -#define ENC_LPOS_POS_MASK (0xFFFFU) -#define ENC_LPOS_POS_SHIFT (0U) -/*! POS - POS - */ -#define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK) -/*! @} */ - -/*! @name UPOSH - Upper Position Hold Register */ -/*! @{ */ - -#define ENC_UPOSH_POSH_MASK (0xFFFFU) -#define ENC_UPOSH_POSH_SHIFT (0U) -/*! POSH - POSH - */ -#define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK) -/*! @} */ - -/*! @name LPOSH - Lower Position Hold Register */ -/*! @{ */ - -#define ENC_LPOSH_POSH_MASK (0xFFFFU) -#define ENC_LPOSH_POSH_SHIFT (0U) -/*! POSH - POSH - */ -#define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK) -/*! @} */ - -/*! @name UINIT - Upper Initialization Register */ -/*! @{ */ - -#define ENC_UINIT_INIT_MASK (0xFFFFU) -#define ENC_UINIT_INIT_SHIFT (0U) -/*! INIT - INIT - */ -#define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK) -/*! @} */ - -/*! @name LINIT - Lower Initialization Register */ -/*! @{ */ - -#define ENC_LINIT_INIT_MASK (0xFFFFU) -#define ENC_LINIT_INIT_SHIFT (0U) -/*! INIT - INIT - */ -#define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK) -/*! @} */ - -/*! @name IMR - Input Monitor Register */ -/*! @{ */ - -#define ENC_IMR_HOME_MASK (0x1U) -#define ENC_IMR_HOME_SHIFT (0U) -/*! HOME - HOME - */ -#define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK) - -#define ENC_IMR_INDEX_MASK (0x2U) -#define ENC_IMR_INDEX_SHIFT (1U) -/*! INDEX - INDEX - */ -#define ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK) - -#define ENC_IMR_PHB_MASK (0x4U) -#define ENC_IMR_PHB_SHIFT (2U) -/*! PHB - PHB - */ -#define ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK) - -#define ENC_IMR_PHA_MASK (0x8U) -#define ENC_IMR_PHA_SHIFT (3U) -/*! PHA - PHA - */ -#define ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK) - -#define ENC_IMR_FHOM_MASK (0x10U) -#define ENC_IMR_FHOM_SHIFT (4U) -/*! FHOM - FHOM - */ -#define ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK) - -#define ENC_IMR_FIND_MASK (0x20U) -#define ENC_IMR_FIND_SHIFT (5U) -/*! FIND - FIND - */ -#define ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK) - -#define ENC_IMR_FPHB_MASK (0x40U) -#define ENC_IMR_FPHB_SHIFT (6U) -/*! FPHB - FPHB - */ -#define ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK) - -#define ENC_IMR_FPHA_MASK (0x80U) -#define ENC_IMR_FPHA_SHIFT (7U) -/*! FPHA - FPHA - */ -#define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK) -/*! @} */ - -/*! @name TST - Test Register */ -/*! @{ */ - -#define ENC_TST_TEST_COUNT_MASK (0xFFU) -#define ENC_TST_TEST_COUNT_SHIFT (0U) -/*! TEST_COUNT - TEST_COUNT - */ -#define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK) - -#define ENC_TST_TEST_PERIOD_MASK (0x1F00U) -#define ENC_TST_TEST_PERIOD_SHIFT (8U) -/*! TEST_PERIOD - TEST_PERIOD - */ -#define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK) - -#define ENC_TST_QDN_MASK (0x2000U) -#define ENC_TST_QDN_SHIFT (13U) -/*! QDN - Quadrature Decoder Negative Signal - * 0b0..Generates a positive quadrature decoder signal - * 0b1..Generates a negative quadrature decoder signal - */ -#define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK) - -#define ENC_TST_TCE_MASK (0x4000U) -#define ENC_TST_TCE_SHIFT (14U) -/*! TCE - Test Counter Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK) - -#define ENC_TST_TEN_MASK (0x8000U) -#define ENC_TST_TEN_SHIFT (15U) -/*! TEN - Test Mode Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK) -/*! @} */ - -/*! @name CTRL2 - Control 2 Register */ -/*! @{ */ - -#define ENC_CTRL2_UPDHLD_MASK (0x1U) -#define ENC_CTRL2_UPDHLD_SHIFT (0U) -/*! UPDHLD - Update Hold Registers - * 0b0..Disable updates of hold registers on the rising edge of TRIGGER input signal - * 0b1..Enable updates of hold registers on the rising edge of TRIGGER input signal - */ -#define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK) - -#define ENC_CTRL2_UPDPOS_MASK (0x2U) -#define ENC_CTRL2_UPDPOS_SHIFT (1U) -/*! UPDPOS - Update Position Registers - * 0b0..No action for POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER - * 0b1..Clear POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER - */ -#define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK) - -#define ENC_CTRL2_MOD_MASK (0x4U) -#define ENC_CTRL2_MOD_SHIFT (2U) -/*! MOD - Enable Modulo Counting - * 0b0..Disable modulo counting - * 0b1..Enable modulo counting - */ -#define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK) - -#define ENC_CTRL2_DIR_MASK (0x8U) -#define ENC_CTRL2_DIR_SHIFT (3U) -/*! DIR - Count Direction Flag - * 0b0..Last count was in the down direction - * 0b1..Last count was in the up direction - */ -#define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK) - -#define ENC_CTRL2_RUIE_MASK (0x10U) -#define ENC_CTRL2_RUIE_SHIFT (4U) -/*! RUIE - Roll-under Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK) - -#define ENC_CTRL2_RUIRQ_MASK (0x20U) -#define ENC_CTRL2_RUIRQ_SHIFT (5U) -/*! RUIRQ - Roll-under Interrupt Request - * 0b0..No roll-under has occurred - * 0b1..Roll-under has occurred - */ -#define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK) - -#define ENC_CTRL2_ROIE_MASK (0x40U) -#define ENC_CTRL2_ROIE_SHIFT (6U) -/*! ROIE - Roll-over Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK) - -#define ENC_CTRL2_ROIRQ_MASK (0x80U) -#define ENC_CTRL2_ROIRQ_SHIFT (7U) -/*! ROIRQ - Roll-over Interrupt Request - * 0b0..No roll-over has occurred - * 0b1..Roll-over has occurred - */ -#define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK) - -#define ENC_CTRL2_REVMOD_MASK (0x100U) -#define ENC_CTRL2_REVMOD_SHIFT (8U) -/*! REVMOD - Revolution Counter Modulus Enable - * 0b0..Use INDEX pulse to increment/decrement revolution counter (REV) - * 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV) - */ -#define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK) - -#define ENC_CTRL2_OUTCTL_MASK (0x200U) -#define ENC_CTRL2_OUTCTL_SHIFT (9U) -/*! OUTCTL - Output Control - * 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP ) - * 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read - */ -#define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK) - -#define ENC_CTRL2_SABIE_MASK (0x400U) -#define ENC_CTRL2_SABIE_SHIFT (10U) -/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK) - -#define ENC_CTRL2_SABIRQ_MASK (0x800U) -#define ENC_CTRL2_SABIRQ_SHIFT (11U) -/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request - * 0b0..No simultaneous change of PHASEA and PHASEB has occurred - * 0b1..A simultaneous change of PHASEA and PHASEB has occurred - */ -#define ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK) -/*! @} */ - -/*! @name UMOD - Upper Modulus Register */ -/*! @{ */ - -#define ENC_UMOD_MOD_MASK (0xFFFFU) -#define ENC_UMOD_MOD_SHIFT (0U) -/*! MOD - MOD - */ -#define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK) -/*! @} */ - -/*! @name LMOD - Lower Modulus Register */ -/*! @{ */ - -#define ENC_LMOD_MOD_MASK (0xFFFFU) -#define ENC_LMOD_MOD_SHIFT (0U) -/*! MOD - MOD - */ -#define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK) -/*! @} */ - -/*! @name UCOMP - Upper Position Compare Register */ -/*! @{ */ - -#define ENC_UCOMP_COMP_MASK (0xFFFFU) -#define ENC_UCOMP_COMP_SHIFT (0U) -/*! COMP - COMP - */ -#define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK) -/*! @} */ - -/*! @name LCOMP - Lower Position Compare Register */ -/*! @{ */ - -#define ENC_LCOMP_COMP_MASK (0xFFFFU) -#define ENC_LCOMP_COMP_SHIFT (0U) -/*! COMP - COMP - */ -#define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK) -/*! @} */ - -/*! @name LASTEDGE - Last Edge Time Register */ -/*! @{ */ - -#define ENC_LASTEDGE_LASTEDGE_MASK (0xFFFFU) -#define ENC_LASTEDGE_LASTEDGE_SHIFT (0U) -/*! LASTEDGE - Last Edge Time Counter - */ -#define ENC_LASTEDGE_LASTEDGE(x) (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGE_LASTEDGE_SHIFT)) & ENC_LASTEDGE_LASTEDGE_MASK) -/*! @} */ - -/*! @name LASTEDGEH - Last Edge Time Hold Register */ -/*! @{ */ - -#define ENC_LASTEDGEH_LASTEDGEH_MASK (0xFFFFU) -#define ENC_LASTEDGEH_LASTEDGEH_SHIFT (0U) -/*! LASTEDGEH - Last Edge Time Hold - */ -#define ENC_LASTEDGEH_LASTEDGEH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGEH_LASTEDGEH_SHIFT)) & ENC_LASTEDGEH_LASTEDGEH_MASK) -/*! @} */ - -/*! @name POSDPER - Position Difference Period Counter Register */ -/*! @{ */ - -#define ENC_POSDPER_POSDPER_MASK (0xFFFFU) -#define ENC_POSDPER_POSDPER_SHIFT (0U) -/*! POSDPER - Position difference period - */ -#define ENC_POSDPER_POSDPER(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPER_POSDPER_SHIFT)) & ENC_POSDPER_POSDPER_MASK) -/*! @} */ - -/*! @name POSDPERBFR - Position Difference Period Buffer Register */ -/*! @{ */ - -#define ENC_POSDPERBFR_POSDPERBFR_MASK (0xFFFFU) -#define ENC_POSDPERBFR_POSDPERBFR_SHIFT (0U) -/*! POSDPERBFR - Position difference period buffer - */ -#define ENC_POSDPERBFR_POSDPERBFR(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERBFR_POSDPERBFR_SHIFT)) & ENC_POSDPERBFR_POSDPERBFR_MASK) -/*! @} */ - -/*! @name POSDPERH - Position Difference Period Hold Register */ -/*! @{ */ - -#define ENC_POSDPERH_POSDPERH_MASK (0xFFFFU) -#define ENC_POSDPERH_POSDPERH_SHIFT (0U) -/*! POSDPERH - Position difference period hold - */ -#define ENC_POSDPERH_POSDPERH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERH_POSDPERH_SHIFT)) & ENC_POSDPERH_POSDPERH_MASK) -/*! @} */ - -/*! @name CTRL3 - Control 3 Register */ -/*! @{ */ - -#define ENC_CTRL3_PMEN_MASK (0x1U) -#define ENC_CTRL3_PMEN_SHIFT (0U) -/*! PMEN - Period measurement function enable - * 0b0..Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS, or REV is read. - * 0b1..Period measurement functions are used. POSD is loaded to POSDH and then cleared only when POSD is read. - */ -#define ENC_CTRL3_PMEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PMEN_SHIFT)) & ENC_CTRL3_PMEN_MASK) - -#define ENC_CTRL3_PRSC_MASK (0xF0U) -#define ENC_CTRL3_PRSC_SHIFT (4U) -/*! PRSC - Prescaler - */ -#define ENC_CTRL3_PRSC(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PRSC_SHIFT)) & ENC_CTRL3_PRSC_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ENC_Register_Masks */ - - -/* ENC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral ENC0 base address */ - #define ENC0_BASE (0x500C4000u) - /** Peripheral ENC0 base address */ - #define ENC0_BASE_NS (0x400C4000u) - /** Peripheral ENC0 base pointer */ - #define ENC0 ((ENC_Type *)ENC0_BASE) - /** Peripheral ENC0 base pointer */ - #define ENC0_NS ((ENC_Type *)ENC0_BASE_NS) - /** Peripheral ENC1 base address */ - #define ENC1_BASE (0x500C6000u) - /** Peripheral ENC1 base address */ - #define ENC1_BASE_NS (0x400C6000u) - /** Peripheral ENC1 base pointer */ - #define ENC1 ((ENC_Type *)ENC1_BASE) - /** Peripheral ENC1 base pointer */ - #define ENC1_NS ((ENC_Type *)ENC1_BASE_NS) - /** Array initializer of ENC peripheral base addresses */ - #define ENC_BASE_ADDRS { ENC0_BASE, ENC1_BASE } - /** Array initializer of ENC peripheral base pointers */ - #define ENC_BASE_PTRS { ENC0, ENC1 } - /** Array initializer of ENC peripheral base addresses */ - #define ENC_BASE_ADDRS_NS { ENC0_BASE_NS, ENC1_BASE_NS } - /** Array initializer of ENC peripheral base pointers */ - #define ENC_BASE_PTRS_NS { ENC0_NS, ENC1_NS } -#else - /** Peripheral ENC0 base address */ - #define ENC0_BASE (0x400C4000u) - /** Peripheral ENC0 base pointer */ - #define ENC0 ((ENC_Type *)ENC0_BASE) - /** Peripheral ENC1 base address */ - #define ENC1_BASE (0x400C6000u) - /** Peripheral ENC1 base pointer */ - #define ENC1 ((ENC_Type *)ENC1_BASE) - /** Array initializer of ENC peripheral base addresses */ - #define ENC_BASE_ADDRS { ENC0_BASE, ENC1_BASE } - /** Array initializer of ENC peripheral base pointers */ - #define ENC_BASE_PTRS { ENC0, ENC1 } -#endif -/** Interrupt vectors for the ENC peripheral type */ -#define ENC_COMPARE_IRQS { ENC0_COMPARE_IRQn, ENC1_COMPARE_IRQn } -#define ENC_HOME_IRQS { ENC0_HOME_IRQn, ENC1_HOME_IRQn } -#define ENC_WDOG_IRQS { ENC0_WDG_IRQn, ENC1_WDG_IRQn } -#define ENC_INDEX_IRQS { ENC0_IDX_IRQn, ENC1_IDX_IRQn } - -/*! - * @} - */ /* end of group ENC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer - * @{ - */ - -/** FLASH - Register Layout Typedef */ -typedef struct { - __O uint32_t CMD; /**< Command, offset: 0x0 */ - __O uint32_t EVENT; /**< Event, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t STARTA; /**< Start address for next flash command, offset: 0x10 */ - __IO uint32_t STOPA; /**< End address for next flash command, offset: 0x14 */ - uint8_t RESERVED_1[104]; - __IO uint32_t DATAW[4]; /**< Data register, array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_2[3912]; - __O uint32_t INTEN_CLR; /**< Clear interrupt enables, offset: 0xFD8 */ - __O uint32_t INTEN_SET; /**< Set interrupt enables, offset: 0xFDC */ - __I uint32_t INTSTAT; /**< Interrupt status, offset: 0xFE0 */ - __I uint32_t INTEN; /**< Interrupt enable, offset: 0xFE4 */ - __O uint32_t INTSTAT_CLR; /**< Clear interrupt status, offset: 0xFE8 */ - __O uint32_t INTSTAT_SET; /**< Set interrupt status, offset: 0xFEC */ - uint8_t RESERVED_3[12]; - __I uint32_t MODULE_ID; /**< Module identification, offset: 0xFFC */ -} FLASH_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_Register_Masks FLASH Register Masks - * @{ - */ - -/*! @name CMD - Command */ -/*! @{ */ - -#define FLASH_CMD_CMD_MASK (0xFFFFFFFFU) -#define FLASH_CMD_CMD_SHIFT (0U) -/*! CMD - command register. - */ -#define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK) -/*! @} */ - -/*! @name EVENT - Event */ -/*! @{ */ - -#define FLASH_EVENT_RST_MASK (0x1U) -#define FLASH_EVENT_RST_SHIFT (0U) -/*! RST - When bit is set, the controller and flash are reset. - */ -#define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK) - -#define FLASH_EVENT_WAKEUP_MASK (0x2U) -#define FLASH_EVENT_WAKEUP_SHIFT (1U) -/*! WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active. - */ -#define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK) - -#define FLASH_EVENT_ABORT_MASK (0x4U) -#define FLASH_EVENT_ABORT_SHIFT (2U) -/*! ABORT - When bit is set, a running program/erase command is aborted. - */ -#define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK) -/*! @} */ - -/*! @name STARTA - Start address for next flash command */ -/*! @{ */ - -#define FLASH_STARTA_STARTA_MASK (0x3FFFU) -#define FLASH_STARTA_STARTA_SHIFT (0U) -/*! STARTA - Address / Start address for commands that take an address (range) as a parameter. - */ -#define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK) -/*! @} */ - -/*! @name STOPA - End address for next flash command */ -/*! @{ */ - -#define FLASH_STOPA_STOPA_MASK (0x3FFFFU) -#define FLASH_STOPA_STOPA_SHIFT (0U) -/*! STOPA - Stop address for commands that take an address range as a parameter (the word specified - * by STOPA is included in the address range). - */ -#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK) -/*! @} */ - -/*! @name DATAW - Data register */ -/*! @{ */ - -#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU) -#define FLASH_DATAW_DATAW_SHIFT (0U) -/*! DATAW - Memory data, or command parameter, or command result. - */ -#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK) -/*! @} */ - -/* The count of FLASH_DATAW */ -#define FLASH_DATAW_COUNT (4U) - -/*! @name INTEN_CLR - Clear interrupt enables */ -/*! @{ */ - -#define FLASH_INTEN_CLR_FAIL_MASK (0x1U) -#define FLASH_INTEN_CLR_FAIL_SHIFT (0U) -/*! FAIL - Clears the fail interrupt. - */ -#define FLASH_INTEN_CLR_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_CLR_FAIL_SHIFT)) & FLASH_INTEN_CLR_FAIL_MASK) - -#define FLASH_INTEN_CLR_ERR_MASK (0x2U) -#define FLASH_INTEN_CLR_ERR_SHIFT (1U) -/*! ERR - Clears the error interrupt. - */ -#define FLASH_INTEN_CLR_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_CLR_ERR_SHIFT)) & FLASH_INTEN_CLR_ERR_MASK) - -#define FLASH_INTEN_CLR_DONE_MASK (0x4U) -#define FLASH_INTEN_CLR_DONE_SHIFT (2U) -/*! DONE - Clears the done interrupt. - */ -#define FLASH_INTEN_CLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_CLR_DONE_SHIFT)) & FLASH_INTEN_CLR_DONE_MASK) - -#define FLASH_INTEN_CLR_ECC_ERR_MASK (0x8U) -#define FLASH_INTEN_CLR_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - Clears the ECC error interrupt. - */ -#define FLASH_INTEN_CLR_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_CLR_ECC_ERR_SHIFT)) & FLASH_INTEN_CLR_ECC_ERR_MASK) -/*! @} */ - -/*! @name INTEN_SET - Set interrupt enables */ -/*! @{ */ - -#define FLASH_INTEN_SET_FAIL_MASK (0x1U) -#define FLASH_INTEN_SET_FAIL_SHIFT (0U) -/*! FAIL - Sets Fail interrupt. - */ -#define FLASH_INTEN_SET_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_SET_FAIL_SHIFT)) & FLASH_INTEN_SET_FAIL_MASK) - -#define FLASH_INTEN_SET_ERR_MASK (0x2U) -#define FLASH_INTEN_SET_ERR_SHIFT (1U) -/*! ERR - Sets error interrupt - */ -#define FLASH_INTEN_SET_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_SET_ERR_SHIFT)) & FLASH_INTEN_SET_ERR_MASK) - -#define FLASH_INTEN_SET_DONE_MASK (0x4U) -#define FLASH_INTEN_SET_DONE_SHIFT (2U) -/*! DONE - Sets done interrupt. - */ -#define FLASH_INTEN_SET_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_SET_DONE_SHIFT)) & FLASH_INTEN_SET_DONE_MASK) - -#define FLASH_INTEN_SET_ECC_ERR_MASK (0x8U) -#define FLASH_INTEN_SET_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - Sets ECC error interrupt. - */ -#define FLASH_INTEN_SET_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_SET_ECC_ERR_SHIFT)) & FLASH_INTEN_SET_ECC_ERR_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status */ -/*! @{ */ - -#define FLASH_INTSTAT_FAIL_MASK (0x1U) -#define FLASH_INTSTAT_FAIL_SHIFT (0U) -/*! FAIL - This status bit is set if execution of a (legal) command failed. - */ -#define FLASH_INTSTAT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_FAIL_SHIFT)) & FLASH_INTSTAT_FAIL_MASK) - -#define FLASH_INTSTAT_ERR_MASK (0x2U) -#define FLASH_INTSTAT_ERR_SHIFT (1U) -/*! ERR - This status bit is set if execution of an illegal command is detected. - */ -#define FLASH_INTSTAT_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_ERR_SHIFT)) & FLASH_INTSTAT_ERR_MASK) - -#define FLASH_INTSTAT_DONE_MASK (0x4U) -#define FLASH_INTSTAT_DONE_SHIFT (2U) -/*! DONE - This status bit is set at the end of command execution. - */ -#define FLASH_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_DONE_SHIFT)) & FLASH_INTSTAT_DONE_MASK) - -#define FLASH_INTSTAT_ECC_ERR_MASK (0x8U) -#define FLASH_INTSTAT_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested - * read, or a speculative read, or reads performed by a controller command), a correctable or - * uncorrectable error is detected by ECC decoding logic. - */ -#define FLASH_INTSTAT_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_ECC_ERR_SHIFT)) & FLASH_INTSTAT_ECC_ERR_MASK) -/*! @} */ - -/*! @name INTEN - Interrupt enable */ -/*! @{ */ - -#define FLASH_INTEN_FAIL_MASK (0x1U) -#define FLASH_INTEN_FAIL_SHIFT (0U) -/*! FAIL - Enables fail interrupt. - */ -#define FLASH_INTEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_FAIL_SHIFT)) & FLASH_INTEN_FAIL_MASK) - -#define FLASH_INTEN_ERR_MASK (0x2U) -#define FLASH_INTEN_ERR_SHIFT (1U) -/*! ERR - Enables error interrupt. - */ -#define FLASH_INTEN_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_ERR_SHIFT)) & FLASH_INTEN_ERR_MASK) - -#define FLASH_INTEN_DONE_MASK (0x4U) -#define FLASH_INTEN_DONE_SHIFT (2U) -/*! DONE - Enables done interrupt. - */ -#define FLASH_INTEN_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_DONE_SHIFT)) & FLASH_INTEN_DONE_MASK) - -#define FLASH_INTEN_ECC_ERR_MASK (0x8U) -#define FLASH_INTEN_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - Enables ECC error interrupt. - */ -#define FLASH_INTEN_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_ECC_ERR_SHIFT)) & FLASH_INTEN_ECC_ERR_MASK) -/*! @} */ - -/*! @name INTSTAT_CLR - Clear interrupt status */ -/*! @{ */ - -#define FLASH_INTSTAT_CLR_FAIL_MASK (0x1U) -#define FLASH_INTSTAT_CLR_FAIL_SHIFT (0U) -/*! FAIL - Clears fail interrupt status. - */ -#define FLASH_INTSTAT_CLR_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_CLR_FAIL_SHIFT)) & FLASH_INTSTAT_CLR_FAIL_MASK) - -#define FLASH_INTSTAT_CLR_ERR_MASK (0x2U) -#define FLASH_INTSTAT_CLR_ERR_SHIFT (1U) -/*! ERR - Clears error interrupt status. - */ -#define FLASH_INTSTAT_CLR_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_CLR_ERR_SHIFT)) & FLASH_INTSTAT_CLR_ERR_MASK) - -#define FLASH_INTSTAT_CLR_DONE_MASK (0x4U) -#define FLASH_INTSTAT_CLR_DONE_SHIFT (2U) -/*! DONE - Clears done interrupt status. - */ -#define FLASH_INTSTAT_CLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_CLR_DONE_SHIFT)) & FLASH_INTSTAT_CLR_DONE_MASK) - -#define FLASH_INTSTAT_CLR_ECC_ERR_MASK (0x8U) -#define FLASH_INTSTAT_CLR_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - Clears ECC error interrupt status. - */ -#define FLASH_INTSTAT_CLR_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_CLR_ECC_ERR_SHIFT)) & FLASH_INTSTAT_CLR_ECC_ERR_MASK) -/*! @} */ - -/*! @name INTSTAT_SET - Set interrupt status */ -/*! @{ */ - -#define FLASH_INTSTAT_SET_FAIL_MASK (0x1U) -#define FLASH_INTSTAT_SET_FAIL_SHIFT (0U) -/*! FAIL - Sets fail interrupt status. - */ -#define FLASH_INTSTAT_SET_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_SET_FAIL_SHIFT)) & FLASH_INTSTAT_SET_FAIL_MASK) - -#define FLASH_INTSTAT_SET_ERR_MASK (0x2U) -#define FLASH_INTSTAT_SET_ERR_SHIFT (1U) -/*! ERR - Sets error interrupt status. - */ -#define FLASH_INTSTAT_SET_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_SET_ERR_SHIFT)) & FLASH_INTSTAT_SET_ERR_MASK) - -#define FLASH_INTSTAT_SET_DONE_MASK (0x4U) -#define FLASH_INTSTAT_SET_DONE_SHIFT (2U) -/*! DONE - Sets done interrupt status. - */ -#define FLASH_INTSTAT_SET_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_SET_DONE_SHIFT)) & FLASH_INTSTAT_SET_DONE_MASK) - -#define FLASH_INTSTAT_SET_ECC_ERR_MASK (0x8U) -#define FLASH_INTSTAT_SET_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - Sets ECC error interrupt status. - */ -#define FLASH_INTSTAT_SET_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_SET_ECC_ERR_SHIFT)) & FLASH_INTSTAT_SET_ECC_ERR_MASK) -/*! @} */ - -/*! @name MODULE_ID - Module identification */ -/*! @{ */ - -#define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U) -#define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision i. - */ -#define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK) - -#define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U) -#define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision i. - */ -#define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK) - -#define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U) -#define FLASH_MODULE_ID_ID_SHIFT (16U) -/*! ID - Identifier. - */ -#define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLASH_Register_Masks */ - - -/* FLASH - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH base address */ - #define FLASH_BASE (0x50034000u) - /** Peripheral FLASH base address */ - #define FLASH_BASE_NS (0x40034000u) - /** Peripheral FLASH base pointer */ - #define FLASH ((FLASH_Type *)FLASH_BASE) - /** Peripheral FLASH base pointer */ - #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS) - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS { FLASH_BASE } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS { FLASH } - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS_NS { FLASH_NS } -#else - /** Peripheral FLASH base address */ - #define FLASH_BASE (0x40034000u) - /** Peripheral FLASH base pointer */ - #define FLASH ((FLASH_Type *)FLASH_BASE) - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS { FLASH_BASE } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS { FLASH } -#endif - -/*! - * @} - */ /* end of group FLASH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer - * @{ - */ - -/** FLEXCOMM - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4088]; - __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm module ID, offset: 0xFF8 */ - __I uint32_t PID; /**< Peripheral Identification, offset: 0xFFC */ -} FLEXCOMM_Type; - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks - * @{ - */ - -/*! @name PSELID - Peripheral Select and Flexcomm module ID */ -/*! @{ */ - -#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) -#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) -/*! PERSEL - Peripheral Select - * 0b000..No peripheral selected. - * 0b001..USART function selected - * 0b010..SPI function selected - * 0b011..I2C - * 0b100..I2S Transmit - * 0b101..I2S Receive - * 0b110..Reserved - * 0b111..Reserved - */ -#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) - -#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) -#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) -/*! LOCK - Lock the peripheral select - * 0b0..Peripheral select can be changed by software. - * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm module or the entire device is reset. - */ -#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) - -#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) -#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) -/*! USARTPRESENT - USART present indicator - * 0b0..This Flexcomm module does not include the USART function. - * 0b1..This Flexcomm module includes the USART function. - */ -#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) - -#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) -#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) -/*! SPIPRESENT - SPI present indicator - * 0b0..This Flexcomm module does not include the SPI function. - * 0b1..This Flexcomm module includes the SPI function. - */ -#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) - -#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) -#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) -/*! I2CPRESENT - I2C present indicator - * 0b0..I2C Not Present - * 0b1..I2C Present - */ -#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) - -#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) -#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) -/*! I2SPRESENT - I2S Present - * 0b0..I2S Not Present - * 0b1..I2S Present - */ -#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) - -#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) -#define FLEXCOMM_PSELID_ID_SHIFT (12U) -/*! ID - Flexcomm ID - */ -#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) -/*! @} */ - -/*! @name PID - Peripheral Identification */ -/*! @{ */ - -#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) -#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) -/*! Minor_Rev - Minor revision of module implementation - */ -#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) - -#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U) -#define FLEXCOMM_PID_Major_Rev_SHIFT (12U) -/*! Major_Rev - Major revision of module implementation - */ -#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK) - -#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) -#define FLEXCOMM_PID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function - */ -#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLEXCOMM_Register_Masks */ - - -/* FLEXCOMM - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE (0x50086000u) - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE_NS (0x40086000u) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE (0x50087000u) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE_NS (0x40087000u) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE (0x50088000u) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE_NS (0x40088000u) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE (0x50089000u) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE_NS (0x40089000u) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE (0x5008A000u) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE_NS (0x4008A000u) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE (0x50096000u) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE_NS (0x40096000u) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE (0x50097000u) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE_NS (0x40097000u) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE (0x50098000u) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE_NS (0x40098000u) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE (0x5009F000u) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE_NS (0x4009F000u) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS) - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS_NS { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS_NS { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS } -#else - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE (0x40086000u) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE (0x40087000u) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE (0x40088000u) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE (0x40089000u) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE (0x4008A000u) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE (0x40096000u) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE (0x40097000u) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE (0x40098000u) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE (0x4009F000u) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } -#endif -/** Interrupt vectors for the FLEXCOMM peripheral type */ -#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } - -/*! - * @} - */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLEXSPI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer - * @{ - */ - -/** FLEXSPI - Register Layout Typedef */ -typedef struct { - __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ - __IO uint32_t MCR1; /**< Module Control Register 1, offset: 0x4 */ - __IO uint32_t MCR2; /**< Module Control Register 2, offset: 0x8 */ - __IO uint32_t AHBCR; /**< AHB Bus Control Register, offset: 0xC */ - __IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x10 */ - __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ - __I uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ - __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ - __IO uint32_t AHBRXBUFCR0[8]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_0[32]; - __IO uint32_t FLSHCR0[2]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ - uint8_t RESERVED_1[8]; - __IO uint32_t FLSHCR1[2]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ - uint8_t RESERVED_2[8]; - __IO uint32_t FLSHCR2[2]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_3[12]; - __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ - uint8_t RESERVED_4[8]; - __IO uint32_t IPCR0; /**< IP Control Register 0, offset: 0xA0 */ - __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ - uint8_t RESERVED_5[8]; - __IO uint32_t IPCMD; /**< IP Command Register, offset: 0xB0 */ - __IO uint32_t DLPR; /**< Data Learn Pattern Register, offset: 0xB4 */ - __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ - __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ - __IO uint32_t DLLCR[2]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ - uint8_t RESERVED_6[24]; - __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ - __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ - __I uint32_t STS2; /**< Status Register 2, offset: 0xE8 */ - __I uint32_t AHBSPNDSTS; /**< AHB Suspend Status Register, offset: 0xEC */ - __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ - __I uint32_t IPTXFSTS; /**< IP TX FIFO Status Register, offset: 0xF4 */ - uint8_t RESERVED_7[8]; - __I uint32_t RFDR[32]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */ - __O uint32_t TFDR[32]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */ - __IO uint32_t LUT[64]; /**< LUT 0..LUT 63, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_8[288]; - __IO uint32_t HADDRSTART; /**< HADDR REMAP START ADDR, offset: 0x420 */ - __IO uint32_t HADDREND; /**< HADDR REMAP END ADDR, offset: 0x424 */ - __IO uint32_t HADDROFFSET; /**< HADDR REMAP OFFSET, offset: 0x428 */ - __IO uint32_t IPEDCTRL; /**< IPED function control, offset: 0x42C */ - uint8_t RESERVED_9[208]; - __IO uint32_t IPEDCTXCTRL[2]; /**< IPED context control 0..IPED context control 1, array offset: 0x500, array step: 0x4 */ - uint8_t RESERVED_10[24]; - __IO uint32_t IPEDCTX0IV0; /**< IPED context0 IV0, offset: 0x520 */ - __IO uint32_t IPEDCTX0IV1; /**< IPED context0 IV1, offset: 0x524 */ - __IO uint32_t IPEDCTX0START; /**< Start address of region 0, offset: 0x528 */ - __IO uint32_t IPEDCTX0END; /**< End address of region 0, offset: 0x52C */ - __IO uint32_t IPEDCTX0AAD0; /**< IPED context0 AAD0, offset: 0x530 */ - __IO uint32_t IPEDCTX0AAD1; /**< IPED context0 AAD1, offset: 0x534 */ - uint8_t RESERVED_11[8]; - __IO uint32_t IPEDCTX1IV0; /**< IPED context1 IV0, offset: 0x540 */ - __IO uint32_t IPEDCTX1IV1; /**< IPED context1 IV1, offset: 0x544 */ - __IO uint32_t IPEDCTX1START; /**< Start address of region 1, offset: 0x548 */ - __IO uint32_t IPEDCTX1END; /**< End address of region 1, offset: 0x54C */ - __IO uint32_t IPEDCTX1AAD0; /**< IPED context1 AAD0, offset: 0x550 */ - __IO uint32_t IPEDCTX1AAD1; /**< IPED context1 AAD1, offset: 0x554 */ - uint8_t RESERVED_12[8]; - __IO uint32_t IPEDCTX2IV0; /**< IPED context2 IV0, offset: 0x560 */ - __IO uint32_t IPEDCTX2IV1; /**< IPED context2 IV1, offset: 0x564 */ - __IO uint32_t IPEDCTX2START; /**< Start address of region 2, offset: 0x568 */ - __IO uint32_t IPEDCTX2END; /**< End address of region 2, offset: 0x56C */ - __IO uint32_t IPEDCTX2AAD0; /**< IPED context2 AAD0, offset: 0x570 */ - __IO uint32_t IPEDCTX2AAD1; /**< IPED context2 AAD1, offset: 0x574 */ - uint8_t RESERVED_13[8]; - __IO uint32_t IPEDCTX3IV0; /**< IPED context3 IV0, offset: 0x580 */ - __IO uint32_t IPEDCTX3IV1; /**< IPED context3 IV1, offset: 0x584 */ - __IO uint32_t IPEDCTX3START; /**< Start address of region 3, offset: 0x588 */ - __IO uint32_t IPEDCTX3END; /**< End address of region 3, offset: 0x58C */ - __IO uint32_t IPEDCTX3AAD0; /**< IPED context3 AAD0, offset: 0x590 */ - __IO uint32_t IPEDCTX3AAD1; /**< IPED context3 AAD1, offset: 0x594 */ -} FLEXSPI_Type; - -/* ---------------------------------------------------------------------------- - -- FLEXSPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks - * @{ - */ - -/*! @name MCR0 - Module Control Register 0 */ -/*! @{ */ - -#define FLEXSPI_MCR0_SWRESET_MASK (0x1U) -#define FLEXSPI_MCR0_SWRESET_SHIFT (0U) -/*! SWRESET - Software Reset - */ -#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) - -#define FLEXSPI_MCR0_MDIS_MASK (0x2U) -#define FLEXSPI_MCR0_MDIS_SHIFT (1U) -/*! MDIS - Module Disable - */ -#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) - -#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) -#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) -/*! RXCLKSRC - Sample Clock source selection for Flash Reading - * 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally. - * 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. - * 0b10..SCLK output clock and loopback from SCLK pad - * 0b11..Flash provided Read strobe and input from DQS pad - */ -#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) - -#define FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U) -#define FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U) -/*! SERCLKDIV - Serial root clock - * 0b000..Divided by 1 - * 0b001..Divided by 2 - * 0b010..Divided by 3 - * 0b011..Divided by 4 - * 0b100..Divided by 5 - * 0b101..Divided by 6 - * 0b110..Divided by 7 - * 0b111..Divided by 8 - */ -#define FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK) - -#define FLEXSPI_MCR0_HSEN_MASK (0x800U) -#define FLEXSPI_MCR0_HSEN_SHIFT (11U) -/*! HSEN - Half Speed Serial Flash access Enable. - * 0b0..Disable divide by 2 of serial flash clock for half speed commands. - * 0b1..Enable divide by 2 of serial flash clock for half speed commands. - */ -#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) - -#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) -#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U) -/*! DOZEEN - Doze mode enable bit - * 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. - * 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system. - */ -#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) - -#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) -#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) -/*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications, - * external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is - * enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2). - * 0b0..Disable. - * 0b1..Enable. - */ -#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) - -#define FLEXSPI_MCR0_LEARNEN_MASK (0x8000U) -#define FLEXSPI_MCR0_LEARNEN_SHIFT (15U) -/*! LEARNEN - This bit is used to enable/disable data learning feature. When data learning is - * disabled, the sampling clock phase 0 is always used for RX data sampling even if LEARN instruction - * is correctly executed. - * 0b0..Disable. - * 0b1..Enable. - */ -#define FLEXSPI_MCR0_LEARNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_LEARNEN_SHIFT)) & FLEXSPI_MCR0_LEARNEN_MASK) - -#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) -#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) -/*! IPGRANTWAIT - Timeout wait cycle for IP command grant. - */ -#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) - -#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) -#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) -/*! AHBGRANTWAIT - Timeout wait cycle for AHB command grant. - */ -#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) -/*! @} */ - -/*! @name MCR1 - Module Control Register 1 */ -/*! @{ */ - -#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) -#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) -/*! AHBBUSWAIT - AHB Bus wait - */ -#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) - -#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) -#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) -/*! SEQWAIT - Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root - * Clock cycles. When sequence execution timeout occurs, there will be an interrupt generated - * (INTR[SEQTIMEOUT]) if this interrupt is enabled (INTEN[SEQTIMEOUTEN] is set 0x1) and AHB command is - * ignored by arbitrator. - */ -#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) -/*! @} */ - -/*! @name MCR2 - Module Control Register 2 */ -/*! @{ */ - -#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) -#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) -/*! CLRAHBBUFOPT - Clear AHB buffer - * 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. - * 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK. - */ -#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) - -#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) -#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) -/*! CLRLEARNPHASE - The sampling clock phase selection will be reset to phase 0 when this bit is - * written with 0x1. This bit will be auto-cleared immediately. - */ -#define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK) - -#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) -#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) -/*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2. - * 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx register setting will be applied to Flash A1/A2 separately. Disabled. - * 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2. FLSHA2CRx will be ignored. - */ -#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) - -#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) -#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) -/*! RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed. - */ -#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) -/*! @} */ - -/*! @name AHBCR - AHB Bus Control Register */ -/*! @{ */ - -#define FLEXSPI_AHBCR_CLRAHBRXBUF_MASK (0x2U) -#define FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT (1U) -/*! CLRAHBRXBUF - Clear the status/pointers of AHB RX Buffer. Auto-cleared. - */ -#define FLEXSPI_AHBCR_CLRAHBRXBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBRXBUF_MASK) - -#define FLEXSPI_AHBCR_CLRAHBTXBUF_MASK (0x4U) -#define FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT (2U) -/*! CLRAHBTXBUF - Clear the status/pointers of AHB TX Buffer. Auto-cleared. - */ -#define FLEXSPI_AHBCR_CLRAHBTXBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBTXBUF_MASK) - -#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) -#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) -/*! CACHABLEEN - Enable AHB bus cachable read access support. - * 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. - * 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first. - */ -#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) - -#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) -#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) -/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. - * 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus - * ready after all data is transmitted to External device and AHB command finished. - * 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is - * granted by arbitrator and will not wait for AHB command finished. - */ -#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) - -#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) -#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) -/*! PREFETCHEN - AHB Read Prefetch Enable. - */ -#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) - -#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) -#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) -/*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. - * 0b0..There is AHB read burst start address alignment limitation when flash is accessed in flash is word-addressable. - * 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB - * burst required to meet the alignment requirement. - */ -#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) - -#define FLEXSPI_AHBCR_READSZALIGN_MASK (0x400U) -#define FLEXSPI_AHBCR_READSZALIGN_SHIFT (10U) -/*! READSZALIGN - AHB Read Size Alignment - * 0b0..AHB read size will be decided by other register setting like PREFETCH_EN - * 0b1..AHB read size to up size to 8 bytes aligned, no prefetching - */ -#define FLEXSPI_AHBCR_READSZALIGN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK) - -#define FLEXSPI_AHBCR_ALIGNMENT_MASK (0x300000U) -#define FLEXSPI_AHBCR_ALIGNMENT_SHIFT (20U) -/*! ALIGNMENT - Decides all AHB read/write boundary. All access cross the boundary will be divided into smaller sub accesses. - * 0b00..No limit - * 0b01..1 KBytes - * 0b10..512 Bytes - * 0b11..256 Bytes - */ -#define FLEXSPI_AHBCR_ALIGNMENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK) -/*! @} */ - -/*! @name INTEN - Interrupt Enable Register */ -/*! @{ */ - -#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) -#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) -/*! IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable. - */ -#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) - -#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U) -#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U) -/*! IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable. - */ -#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) - -#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U) -#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U) -/*! AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable. - */ -#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) - -#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U) -#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U) -/*! IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable. - */ -#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) - -#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U) -#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U) -/*! AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable. - */ -#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) - -#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U) -#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U) -/*! IPRXWAEN - IP RX FIFO WaterMark available interrupt enable. - */ -#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) - -#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U) -#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U) -/*! IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable. - */ -#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) - -#define FLEXSPI_INTEN_DATALEARNFAILEN_MASK (0x80U) -#define FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT (7U) -/*! DATALEARNFAILEN - Data Learning failed interrupt enable. - */ -#define FLEXSPI_INTEN_DATALEARNFAILEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FLEXSPI_INTEN_DATALEARNFAILEN_MASK) - -#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) -#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) -/*! SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable. - */ -#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) - -#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) -#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) -/*! SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable. - */ -#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) - -#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U) -#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U) -/*! AHBBUSTIMEOUTEN - AHB Bus timeout interrupt. - */ -#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK) - -#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) -#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) -/*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable. - */ -#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) - -#define FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK (0x10000U) -#define FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT (16U) -/*! IPCMDSECUREVIOEN - IP command security violation interrupt enable. - */ -#define FLEXSPI_INTEN_IPCMDSECUREVIOEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT)) & FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK) - -#define FLEXSPI_INTEN_AHBGCMERREN_MASK (0x20000U) -#define FLEXSPI_INTEN_AHBGCMERREN_SHIFT (17U) -/*! AHBGCMERREN - AHB read gcm error interrupt enable. - */ -#define FLEXSPI_INTEN_AHBGCMERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBGCMERREN_SHIFT)) & FLEXSPI_INTEN_AHBGCMERREN_MASK) -/*! @} */ - -/*! @name INTR - Interrupt Register */ -/*! @{ */ - -#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) -#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) -/*! IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also - * generated when there is IPCMDGE or IPCMDERR interrupt generated. - */ -#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) - -#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U) -#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U) -/*! IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt. - */ -#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) - -#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) -#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) -/*! AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt. - */ -#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) - -#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U) -#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U) -/*! IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for - * IP command, this command will be ignored and not executed at all. - */ -#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) - -#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U) -#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) -/*! AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for - * AHB command, this command will be ignored and not executed at all. - */ -#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) - -#define FLEXSPI_INTR_IPRXWA_MASK (0x20U) -#define FLEXSPI_INTR_IPRXWA_SHIFT (5U) -/*! IPRXWA - IP RX FIFO watermark available interrupt. - */ -#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) - -#define FLEXSPI_INTR_IPTXWE_MASK (0x40U) -#define FLEXSPI_INTR_IPTXWE_SHIFT (6U) -/*! IPTXWE - IP TX FIFO watermark empty interrupt. - */ -#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) - -#define FLEXSPI_INTR_DATALEARNFAIL_MASK (0x80U) -#define FLEXSPI_INTR_DATALEARNFAIL_SHIFT (7U) -/*! DATALEARNFAIL - Data Learning failed interrupt. - */ -#define FLEXSPI_INTR_DATALEARNFAIL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK) - -#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U) -#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) -/*! SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt. - */ -#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) - -#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U) -#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) -/*! SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt. - */ -#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) - -#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U) -#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U) -/*! AHBBUSTIMEOUT - AHB Bus timeout interrupt. - */ -#define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK) - -#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) -#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) -/*! SEQTIMEOUT - Sequence execution timeout interrupt. - */ -#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) - -#define FLEXSPI_INTR_IPCMDSECUREVIO_MASK (0x10000U) -#define FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT (16U) -/*! IPCMDSECUREVIO - IP command security violation interrupt. - */ -#define FLEXSPI_INTR_IPCMDSECUREVIO(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT)) & FLEXSPI_INTR_IPCMDSECUREVIO_MASK) - -#define FLEXSPI_INTR_AHBGCMERR_MASK (0x20000U) -#define FLEXSPI_INTR_AHBGCMERR_SHIFT (17U) -/*! AHBGCMERR - AHB read gcm error interrupt. - */ -#define FLEXSPI_INTR_AHBGCMERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBGCMERR_SHIFT)) & FLEXSPI_INTR_AHBGCMERR_MASK) -/*! @} */ - -/*! @name LUTKEY - LUT Key Register */ -/*! @{ */ - -#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) -#define FLEXSPI_LUTKEY_KEY_SHIFT (0U) -/*! KEY - The Key to lock or unlock LUT. - */ -#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) -/*! @} */ - -/*! @name LUTCR - LUT Control Register */ -/*! @{ */ - -#define FLEXSPI_LUTCR_LOCK_MASK (0x1U) -#define FLEXSPI_LUTCR_LOCK_SHIFT (0U) -/*! LOCK - Lock LUT - */ -#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) - -#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) -#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) -/*! UNLOCK - Unlock LUT - */ -#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) - -#define FLEXSPI_LUTCR_PROTECT_MASK (0x4U) -#define FLEXSPI_LUTCR_PROTECT_SHIFT (2U) -/*! PROTECT - LUT protection - */ -#define FLEXSPI_LUTCR_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_PROTECT_SHIFT)) & FLEXSPI_LUTCR_PROTECT_MASK) -/*! @} */ - -/*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */ -/*! @{ */ - -#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU) -#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) -/*! BUFSZ - AHB RX Buffer Size in 64 bits. - */ -#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) - -#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) -#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) -/*! MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). - */ -#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) - -#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U) -#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) -/*! PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest. - */ -#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) - -#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) -#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) -/*! PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. - */ -#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) -/*! @} */ - -/* The count of FLEXSPI_AHBRXBUFCR0 */ -#define FLEXSPI_AHBRXBUFCR0_COUNT (8U) - -/*! @name FLSHCR0 - Flash Control Register 0 */ -/*! @{ */ - -#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) -#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) -/*! FLSHSZ - Flash Size in KByte. - */ -#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) - -#define FLEXSPI_FLSHCR0_SPLITWREN_MASK (0x40000000U) -#define FLEXSPI_FLSHCR0_SPLITWREN_SHIFT (30U) -/*! SPLITWREN - AHB write access split function control. - */ -#define FLEXSPI_FLSHCR0_SPLITWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITWREN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITWREN_MASK) - -#define FLEXSPI_FLSHCR0_SPLITRDEN_MASK (0x80000000U) -#define FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT (31U) -/*! SPLITRDEN - AHB read access split function control. - */ -#define FLEXSPI_FLSHCR0_SPLITRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITRDEN_MASK) -/*! @} */ - -/* The count of FLEXSPI_FLSHCR0 */ -#define FLEXSPI_FLSHCR0_COUNT (2U) - -/*! @name FLSHCR1 - Flash Control Register 1 */ -/*! @{ */ - -#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) -#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) -/*! TCSS - Serial Flash CS setup time. - */ -#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) - -#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U) -#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U) -/*! TCSH - Serial Flash CS Hold time. - */ -#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) - -#define FLEXSPI_FLSHCR1_WA_MASK (0x400U) -#define FLEXSPI_FLSHCR1_WA_SHIFT (10U) -/*! WA - Word Addressable. - */ -#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) - -#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U) -#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U) -/*! CAS - Column Address Size. - */ -#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) - -#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) -#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) -/*! CSINTERVALUNIT - CS interval unit - * 0b0..The CS interval unit is 1 serial clock cycle - * 0b1..The CS interval unit is 256 serial clock cycle - */ -#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) - -#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) -#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) -/*! CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection - * deassertion and flash device Chip selection assertion. If external flash has a limitation on - * the interval between command sequences, this field should be set accordingly. If there is no - * limitation, set this field with value 0x0. - */ -#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) -/*! @} */ - -/* The count of FLEXSPI_FLSHCR1 */ -#define FLEXSPI_FLSHCR1_COUNT (2U) - -/*! @name FLSHCR2 - Flash Control Register 2 */ -/*! @{ */ - -#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU) -#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) -/*! ARDSEQID - Sequence Index for AHB Read triggered Command in LUT. - */ -#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) - -#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) -#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) -/*! ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT. - */ -#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) - -#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U) -#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U) -/*! AWRSEQID - Sequence Index for AHB Write triggered Command. - */ -#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) - -#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) -#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) -/*! AWRSEQNUM - Sequence Number for AHB Write triggered Command. - */ -#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) - -#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) -#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) -/*! AWRWAIT - For certain devices (such as FPGA), it need some time to write data into internal - * memory after the command sequences finished on FlexSPI interface. If another Read command sequence - * comes before previous programming finished internally, the read data may be wrong. This field - * is used to hold AHB Bus ready for AHB write access to wait the programming finished in - * external device. Then there will be no AHB read command triggered before the programming finished in - * external device. The Wait cycle between AHB triggered command sequences finished on FlexSPI - * interface and AHB return Bus ready: AWRWAIT * AWRWAITUNIT - */ -#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) - -#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) -#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) -/*! AWRWAITUNIT - AWRWAIT unit - * 0b000..The AWRWAIT unit is 2 ahb clock cycle - * 0b001..The AWRWAIT unit is 8 ahb clock cycle - * 0b010..The AWRWAIT unit is 32 ahb clock cycle - * 0b011..The AWRWAIT unit is 128 ahb clock cycle - * 0b100..The AWRWAIT unit is 512 ahb clock cycle - * 0b101..The AWRWAIT unit is 2048 ahb clock cycle - * 0b110..The AWRWAIT unit is 8192 ahb clock cycle - * 0b111..The AWRWAIT unit is 32768 ahb clock cycle - */ -#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) - -#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) -#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) -/*! CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. - */ -#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) -/*! @} */ - -/* The count of FLEXSPI_FLSHCR2 */ -#define FLEXSPI_FLSHCR2_COUNT (2U) - -/*! @name FLSHCR4 - Flash Control Register 4 */ -/*! @{ */ - -#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) -#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) -/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. - * 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write - * burst start address alignment when flash is accessed in individual mode. - * 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write - * burst start address alignment when flash is accessed in individual mode. - */ -#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) - -#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) -#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) -/*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for - * memory device on port A, this bit must be set. - * 0b0..Write mask is disabled, DQS(RWDS) pin will not be driven when writing to external device. - * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. - */ -#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) -/*! @} */ - -/*! @name IPCR0 - IP Control Register 0 */ -/*! @{ */ - -#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) -#define FLEXSPI_IPCR0_SFAR_SHIFT (0U) -/*! SFAR - Serial Flash Address for IP command. - */ -#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) -/*! @} */ - -/*! @name IPCR1 - IP Control Register 1 */ -/*! @{ */ - -#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) -#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) -/*! IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command. - */ -#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) - -#define FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U) -#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U) -/*! ISEQID - Sequence Index in LUT for IP command. - */ -#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) - -#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U) -#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U) -/*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1. - */ -#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) -/*! @} */ - -/*! @name IPCMD - IP Command Register */ -/*! @{ */ - -#define FLEXSPI_IPCMD_TRG_MASK (0x1U) -#define FLEXSPI_IPCMD_TRG_SHIFT (0U) -/*! TRG - Setting this bit will trigger an IP Command. - */ -#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) -/*! @} */ - -/*! @name DLPR - Data Learn Pattern Register */ -/*! @{ */ - -#define FLEXSPI_DLPR_DLP_MASK (0xFFFFFFFFU) -#define FLEXSPI_DLPR_DLP_SHIFT (0U) -/*! DLP - Data Learning Pattern. - */ -#define FLEXSPI_DLPR_DLP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLPR_DLP_SHIFT)) & FLEXSPI_DLPR_DLP_MASK) -/*! @} */ - -/*! @name IPRXFCR - IP RX FIFO Control Register */ -/*! @{ */ - -#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) -#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) -/*! CLRIPRXF - Clear all valid data entries in IP RX FIFO. - */ -#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) - -#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) -#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) -/*! RXDMAEN - IP RX FIFO reading by DMA enabled. - * 0b0..IP RX FIFO would be read by processor. - * 0b1..IP RX FIFO would be read by DMA. - */ -#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) - -#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x1FCU) -#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) -/*! RXWMRK - Watermark level is (RXWMRK+1)*64 Bits. - */ -#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) -/*! @} */ - -/*! @name IPTXFCR - IP TX FIFO Control Register */ -/*! @{ */ - -#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) -#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) -/*! CLRIPTXF - Clear all valid data entries in IP TX FIFO. - */ -#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) - -#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) -#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) -/*! TXDMAEN - IP TX FIFO filling by DMA enabled. - * 0b0..IP TX FIFO would be filled by processor. - * 0b1..IP TX FIFO would be filled by DMA. - */ -#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) - -#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x1FCU) -#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) -/*! TXWMRK - Watermark level is (TXWMRK+1)*64 Bits. - */ -#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) -/*! @} */ - -/*! @name DLLCR - DLL Control Register 0 */ -/*! @{ */ - -#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U) -#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U) -/*! DLLEN - DLL calibration enable. - */ -#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) - -#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) -#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) -/*! DLLRESET - DLL reset - */ -#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) - -#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) -#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) -/*! SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle - * of reference clock (serial root clock). If serial root clock is >= 100 MHz, DLLEN set to 0x1, - * OVRDEN set to =0x0, then SLVDLYTARGET setting of 0xF is recommended. - */ -#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) - -#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) -#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U) -/*! OVRDEN - Slave clock delay line delay cell number selection override enable. - */ -#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) - -#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) -#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) -/*! OVRDVAL - Slave clock delay line delay cell number selection override value. - */ -#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) -/*! @} */ - -/* The count of FLEXSPI_DLLCR */ -#define FLEXSPI_DLLCR_COUNT (2U) - -/*! @name STS0 - Status Register 0 */ -/*! @{ */ - -#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U) -#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U) -/*! SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command - * sequence executing on FlexSPI interface. - */ -#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) - -#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U) -#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U) -/*! ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command - * sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state - * (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So - * this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE. - */ -#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) - -#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) -#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) -/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted - * by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). - * 0b00..Triggered by AHB read command (triggered by AHB read). - * 0b01..Triggered by AHB write command (triggered by AHB Write). - * 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG). - * 0b11..Triggered by suspended command (resumed). - */ -#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) - -#define FLEXSPI_STS0_DATALEARNPHASEA_MASK (0xF0U) -#define FLEXSPI_STS0_DATALEARNPHASEA_SHIFT (4U) -/*! DATALEARNPHASEA - Indicate the sampling clock phase selection on Port A after Data Learning. - */ -#define FLEXSPI_STS0_DATALEARNPHASEA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEA_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEA_MASK) -/*! @} */ - -/*! @name STS1 - Status Register 1 */ -/*! @{ */ - -#define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU) -#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) -/*! AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field - * will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). - */ -#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) - -#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) -#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) -/*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be - * cleared when INTR[AHBCMDERR] is write-1-clear(w1c). - * 0b0000..No error. - * 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence. - * 0b0011..There is unknown instruction opcode in the sequence. - * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. - * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. - * 0b1110..Sequence execution timeout. - */ -#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) - -#define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U) -#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) -/*! IPCMDERRID - Indicates the sequence Index when IP command error detected. - */ -#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) - -#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) -#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) -/*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be - * cleared when INTR[IPCMDERR] is write-1-clear(w1c). - * 0b0000..No error. - * 0b0010..IP command with JMP_ON_CS instruction used in the sequence. - * 0b0011..There is unknown instruction opcode in the sequence. - * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. - * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. - * 0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2). - * 0b1110..Sequence execution timeout. - * 0b1111..Flash boundary crossed. - */ -#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) -/*! @} */ - -/*! @name STS2 - Status Register 2 */ -/*! @{ */ - -#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) -#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) -/*! ASLVLOCK - Flash A sample clock slave delay line locked. - */ -#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) - -#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U) -#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U) -/*! AREFLOCK - Flash A sample clock reference delay line locked. - */ -#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) - -#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU) -#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U) -/*! ASLVSEL - Flash A sample clock slave delay line delay cell number selection . - */ -#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) - -#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U) -#define FLEXSPI_STS2_AREFSEL_SHIFT (8U) -/*! AREFSEL - Flash A sample clock reference delay line delay cell number selection. - */ -#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) -/*! @} */ - -/*! @name AHBSPNDSTS - AHB Suspend Status Register */ -/*! @{ */ - -#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) -#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) -/*! ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended. - */ -#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) - -#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU) -#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U) -/*! BUFID - AHB RX BUF ID for suspended command sequence. - */ -#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) - -#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) -#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) -/*! DATLFT - Left Data size for suspended command sequence (in byte). - */ -#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) -/*! @} */ - -/*! @name IPRXFSTS - IP RX FIFO Status Register */ -/*! @{ */ - -#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) -#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) -/*! FILL - Fill level of IP RX FIFO. - */ -#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) - -#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) -#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) -/*! RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits. - */ -#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) -/*! @} */ - -/*! @name IPTXFSTS - IP TX FIFO Status Register */ -/*! @{ */ - -#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) -#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) -/*! FILL - Fill level of IP TX FIFO. - */ -#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) - -#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) -#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) -/*! WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits. - */ -#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) -/*! @} */ - -/*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */ -/*! @{ */ - -#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) -#define FLEXSPI_RFDR_RXDATA_SHIFT (0U) -/*! RXDATA - RX Data - */ -#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) -/*! @} */ - -/* The count of FLEXSPI_RFDR */ -#define FLEXSPI_RFDR_COUNT (32U) - -/*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */ -/*! @{ */ - -#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) -#define FLEXSPI_TFDR_TXDATA_SHIFT (0U) -/*! TXDATA - TX Data - */ -#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) -/*! @} */ - -/* The count of FLEXSPI_TFDR */ -#define FLEXSPI_TFDR_COUNT (32U) - -/*! @name LUT - LUT 0..LUT 63 */ -/*! @{ */ - -#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU) -#define FLEXSPI_LUT_OPERAND0_SHIFT (0U) -/*! OPERAND0 - OPERAND0 - */ -#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) - -#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) -#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) -/*! NUM_PADS0 - NUM_PADS0 - */ -#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) - -#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) -#define FLEXSPI_LUT_OPCODE0_SHIFT (10U) -/*! OPCODE0 - OPCODE - */ -#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) - -#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) -#define FLEXSPI_LUT_OPERAND1_SHIFT (16U) -/*! OPERAND1 - OPERAND1 - */ -#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) - -#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) -#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) -/*! NUM_PADS1 - NUM_PADS1 - */ -#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) - -#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) -#define FLEXSPI_LUT_OPCODE1_SHIFT (26U) -/*! OPCODE1 - OPCODE1 - */ -#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) -/*! @} */ - -/* The count of FLEXSPI_LUT */ -#define FLEXSPI_LUT_COUNT (64U) - -/*! @name HADDRSTART - HADDR REMAP START ADDR */ -/*! @{ */ - -#define FLEXSPI_HADDRSTART_REMAPEN_MASK (0x1U) -#define FLEXSPI_HADDRSTART_REMAPEN_SHIFT (0U) -/*! REMAPEN - AHB Bus address remap function enable - * 0b0..HADDR REMAP Disabled - * 0b1..HADDR REMAP Enabled - */ -#define FLEXSPI_HADDRSTART_REMAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_REMAPEN_SHIFT)) & FLEXSPI_HADDRSTART_REMAPEN_MASK) - -#define FLEXSPI_HADDRSTART_ADDRSTART_MASK (0xFFFFF000U) -#define FLEXSPI_HADDRSTART_ADDRSTART_SHIFT (12U) -/*! ADDRSTART - HADDR start address - */ -#define FLEXSPI_HADDRSTART_ADDRSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_ADDRSTART_SHIFT)) & FLEXSPI_HADDRSTART_ADDRSTART_MASK) -/*! @} */ - -/*! @name HADDREND - HADDR REMAP END ADDR */ -/*! @{ */ - -#define FLEXSPI_HADDREND_ENDSTART_MASK (0xFFFFF000U) -#define FLEXSPI_HADDREND_ENDSTART_SHIFT (12U) -/*! ENDSTART - HADDR remap range's end addr, 4K aligned - */ -#define FLEXSPI_HADDREND_ENDSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDREND_ENDSTART_SHIFT)) & FLEXSPI_HADDREND_ENDSTART_MASK) -/*! @} */ - -/*! @name HADDROFFSET - HADDR REMAP OFFSET */ -/*! @{ */ - -#define FLEXSPI_HADDROFFSET_ADDROFFSET_MASK (0xFFFFF000U) -#define FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT (12U) -/*! ADDROFFSET - HADDR offset field, remapped address will be ADDR[31:12]=ADDR_original[31:12]+ADDROFFSET - */ -#define FLEXSPI_HADDROFFSET_ADDROFFSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT)) & FLEXSPI_HADDROFFSET_ADDROFFSET_MASK) -/*! @} */ - -/*! @name IPEDCTRL - IPED function control */ -/*! @{ */ - -#define FLEXSPI_IPEDCTRL_CONFIG_MASK (0x1U) -#define FLEXSPI_IPEDCTRL_CONFIG_SHIFT (0U) -/*! CONFIG - Drive IPED interface i_config. - */ -#define FLEXSPI_IPEDCTRL_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_CONFIG_SHIFT)) & FLEXSPI_IPEDCTRL_CONFIG_MASK) - -#define FLEXSPI_IPEDCTRL_IPED_EN_MASK (0x2U) -#define FLEXSPI_IPEDCTRL_IPED_EN_SHIFT (1U) -/*! IPED_EN - Drive IPED interface i_enable - */ -#define FLEXSPI_IPEDCTRL_IPED_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPED_EN_SHIFT)) & FLEXSPI_IPEDCTRL_IPED_EN_MASK) - -#define FLEXSPI_IPEDCTRL_IPWR_EN_MASK (0x4U) -#define FLEXSPI_IPEDCTRL_IPWR_EN_SHIFT (2U) -/*! IPWR_EN - IP write IPED CTR mode encryption enable - */ -#define FLEXSPI_IPEDCTRL_IPWR_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPWR_EN_SHIFT)) & FLEXSPI_IPEDCTRL_IPWR_EN_MASK) - -#define FLEXSPI_IPEDCTRL_AHBWR_EN_MASK (0x8U) -#define FLEXSPI_IPEDCTRL_AHBWR_EN_SHIFT (3U) -/*! AHBWR_EN - AHB write IPED CTR mode encryption enable - */ -#define FLEXSPI_IPEDCTRL_AHBWR_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHBWR_EN_SHIFT)) & FLEXSPI_IPEDCTRL_AHBWR_EN_MASK) - -#define FLEXSPI_IPEDCTRL_AHBRD_EN_MASK (0x10U) -#define FLEXSPI_IPEDCTRL_AHBRD_EN_SHIFT (4U) -/*! AHBRD_EN - AHB read IPED CTR mode decryption enable - */ -#define FLEXSPI_IPEDCTRL_AHBRD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHBRD_EN_SHIFT)) & FLEXSPI_IPEDCTRL_AHBRD_EN_MASK) - -#define FLEXSPI_IPEDCTRL_IPGCMWR_MASK (0x40U) -#define FLEXSPI_IPEDCTRL_IPGCMWR_SHIFT (6U) -/*! IPGCMWR - IP write GCM mode enable - */ -#define FLEXSPI_IPEDCTRL_IPGCMWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPGCMWR_SHIFT)) & FLEXSPI_IPEDCTRL_IPGCMWR_MASK) - -#define FLEXSPI_IPEDCTRL_AHGCMWR_MASK (0x80U) -#define FLEXSPI_IPEDCTRL_AHGCMWR_SHIFT (7U) -/*! AHGCMWR - AHB write IPED GCM mode encryption enable - */ -#define FLEXSPI_IPEDCTRL_AHGCMWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHGCMWR_SHIFT)) & FLEXSPI_IPEDCTRL_AHGCMWR_MASK) - -#define FLEXSPI_IPEDCTRL_AHBGCMRD_MASK (0x100U) -#define FLEXSPI_IPEDCTRL_AHBGCMRD_SHIFT (8U) -/*! AHBGCMRD - AHB read IPED GCM mode decryption enable - */ -#define FLEXSPI_IPEDCTRL_AHBGCMRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHBGCMRD_SHIFT)) & FLEXSPI_IPEDCTRL_AHBGCMRD_MASK) - -#define FLEXSPI_IPEDCTRL_IPED_PROTECT_MASK (0x200U) -#define FLEXSPI_IPEDCTRL_IPED_PROTECT_SHIFT (9U) -/*! IPED_PROTECT - when ipedctrl protect = 0 or priviledge access, no restriction when ipedctrl - * protect = 1, only priviledge access can write. - */ -#define FLEXSPI_IPEDCTRL_IPED_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPED_PROTECT_SHIFT)) & FLEXSPI_IPEDCTRL_IPED_PROTECT_MASK) - -#define FLEXSPI_IPEDCTRL_IPED_SWRESET_MASK (0x400U) -#define FLEXSPI_IPEDCTRL_IPED_SWRESET_SHIFT (10U) -/*! IPED_SWRESET - Drive IPED interface i_abort. - */ -#define FLEXSPI_IPEDCTRL_IPED_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPED_SWRESET_SHIFT)) & FLEXSPI_IPEDCTRL_IPED_SWRESET_MASK) -/*! @} */ - -/*! @name IPEDCTXCTRLX_IPEDCTXCTRL - IPED context control 0..IPED context control 1 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_MASK (0x3U) -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_SHIFT (0U) -/*! CTX0_FREEZE0 - Controls the RW properties of this field and region 0 context registers (CTX0_xxxx). - */ -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_MASK) - -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_MASK (0x3U) -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_SHIFT (0U) -/*! CTX0_FREEZE1 - Controls the RW properties of this field and region 0 context registers (CTX0_xxxx). - */ -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_MASK) - -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0_MASK (0xCU) -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0_SHIFT (2U) -/*! CTX1_FREEZE0 - Controls the RW properties of this field and region 1 context registers (CTX1_xxxx). - */ -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0_MASK) - -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1_MASK (0xCU) -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1_SHIFT (2U) -/*! CTX1_FREEZE1 - Controls the RW properties of this field and region 1 context registers (CTX1_xxxx). - */ -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1_MASK) - -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0_MASK (0x30U) -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0_SHIFT (4U) -/*! CTX2_FREEZE0 - Controls the RW properties of this field and region 2 context registers (CTX2_xxxx). - */ -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0_MASK) - -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1_MASK (0x30U) -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1_SHIFT (4U) -/*! CTX2_FREEZE1 - Controls the RW properties of this field and region 2 context registers (CTX2_xxxx). - */ -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1_MASK) - -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0_MASK (0xC0U) -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0_SHIFT (6U) -/*! CTX3_FREEZE0 - Controls the RW properties of this field and region 3 context registers (CTX3_xxxx). - */ -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0_MASK) - -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1_MASK (0xC0U) -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1_SHIFT (6U) -/*! CTX3_FREEZE1 - Controls the RW properties of this field and region 3 context registers (CTX3_xxxx). - */ -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1_MASK) -/*! @} */ - -/* The count of FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL */ -#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_COUNT (2U) - -/*! @name IPEDCTX0IV0 - IPED context0 IV0 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX0IV0_CTX0_IV0_MASK (0xFFFFFFFFU) -#define FLEXSPI_IPEDCTX0IV0_CTX0_IV0_SHIFT (0U) -/*! CTX0_IV0 - Lowest 32 bits of IV for region 0. - */ -#define FLEXSPI_IPEDCTX0IV0_CTX0_IV0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0IV0_CTX0_IV0_SHIFT)) & FLEXSPI_IPEDCTX0IV0_CTX0_IV0_MASK) -/*! @} */ - -/*! @name IPEDCTX0IV1 - IPED context0 IV1 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX0IV1_CTX0_IV1_MASK (0xFFFFFFFFU) -#define FLEXSPI_IPEDCTX0IV1_CTX0_IV1_SHIFT (0U) -/*! CTX0_IV1 - Highest 32 bits of IV for region 0. - */ -#define FLEXSPI_IPEDCTX0IV1_CTX0_IV1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0IV1_CTX0_IV1_SHIFT)) & FLEXSPI_IPEDCTX0IV1_CTX0_IV1_MASK) -/*! @} */ - -/*! @name IPEDCTX0START - Start address of region 0 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX0START_GCM_MASK (0x1U) -#define FLEXSPI_IPEDCTX0START_GCM_SHIFT (0U) -/*! GCM - If this bit is 1, current region is GCM mode region. - */ -#define FLEXSPI_IPEDCTX0START_GCM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0START_GCM_SHIFT)) & FLEXSPI_IPEDCTX0START_GCM_MASK) - -#define FLEXSPI_IPEDCTX0START_ahbbuserror_dis_MASK (0x2U) -#define FLEXSPI_IPEDCTX0START_ahbbuserror_dis_SHIFT (1U) -/*! ahbbuserror_dis - If this bit is 1, ahb bus error is disable. - */ -#define FLEXSPI_IPEDCTX0START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX0START_ahbbuserror_dis_MASK) - -#define FLEXSPI_IPEDCTX0START_start_address_MASK (0xFFFFFF00U) -#define FLEXSPI_IPEDCTX0START_start_address_SHIFT (8U) -/*! start_address - Start address of region 0. Minimal 256 Bytes aligned. It is system address. - */ -#define FLEXSPI_IPEDCTX0START_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0START_start_address_SHIFT)) & FLEXSPI_IPEDCTX0START_start_address_MASK) -/*! @} */ - -/*! @name IPEDCTX0END - End address of region 0 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX0END_end_address_MASK (0xFFFFFF00U) -#define FLEXSPI_IPEDCTX0END_end_address_SHIFT (8U) -/*! end_address - End address of region 0. Minimal 256 Bytes aligned. It is system address. - */ -#define FLEXSPI_IPEDCTX0END_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0END_end_address_SHIFT)) & FLEXSPI_IPEDCTX0END_end_address_MASK) -/*! @} */ - -/*! @name IPEDCTX0AAD0 - IPED context0 AAD0 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_MASK (0xFFFFFFFFU) -#define FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_SHIFT (0U) -/*! CTX0_AAD0 - Lowest 32 bits of AAD for region 0. - */ -#define FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_SHIFT)) & FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_MASK) -/*! @} */ - -/*! @name IPEDCTX0AAD1 - IPED context0 AAD1 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_MASK (0xFFFFFFFFU) -#define FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_SHIFT (0U) -/*! CTX0_AAD1 - Highest 32 bits of AAD for region 0. - */ -#define FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_SHIFT)) & FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_MASK) -/*! @} */ - -/*! @name IPEDCTX1IV0 - IPED context1 IV0 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX1IV0_CTX1_IV0_MASK (0xFFFFFFFFU) -#define FLEXSPI_IPEDCTX1IV0_CTX1_IV0_SHIFT (0U) -/*! CTX1_IV0 - Lowest 32 bits of IV for region 1. - */ -#define FLEXSPI_IPEDCTX1IV0_CTX1_IV0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1IV0_CTX1_IV0_SHIFT)) & FLEXSPI_IPEDCTX1IV0_CTX1_IV0_MASK) -/*! @} */ - -/*! @name IPEDCTX1IV1 - IPED context1 IV1 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX1IV1_CTX1_IV1_MASK (0xFFFFFFFFU) -#define FLEXSPI_IPEDCTX1IV1_CTX1_IV1_SHIFT (0U) -/*! CTX1_IV1 - Highest 32 bits of IV for region 1. - */ -#define FLEXSPI_IPEDCTX1IV1_CTX1_IV1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1IV1_CTX1_IV1_SHIFT)) & FLEXSPI_IPEDCTX1IV1_CTX1_IV1_MASK) -/*! @} */ - -/*! @name IPEDCTX1START - Start address of region 1 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX1START_GCM_MASK (0x1U) -#define FLEXSPI_IPEDCTX1START_GCM_SHIFT (0U) -/*! GCM - If this bit is 1, current region is GCM mode region. - */ -#define FLEXSPI_IPEDCTX1START_GCM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1START_GCM_SHIFT)) & FLEXSPI_IPEDCTX1START_GCM_MASK) - -#define FLEXSPI_IPEDCTX1START_ahbbuserror_dis_MASK (0x2U) -#define FLEXSPI_IPEDCTX1START_ahbbuserror_dis_SHIFT (1U) -/*! ahbbuserror_dis - If this bit is 1, ahb bus error is disable. - */ -#define FLEXSPI_IPEDCTX1START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX1START_ahbbuserror_dis_MASK) - -#define FLEXSPI_IPEDCTX1START_start_address_MASK (0xFFFFFF00U) -#define FLEXSPI_IPEDCTX1START_start_address_SHIFT (8U) -/*! start_address - Start address of region 1. Minimal 256 Bytes aligned. It is system address. - */ -#define FLEXSPI_IPEDCTX1START_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1START_start_address_SHIFT)) & FLEXSPI_IPEDCTX1START_start_address_MASK) -/*! @} */ - -/*! @name IPEDCTX1END - End address of region 1 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX1END_end_address_MASK (0xFFFFFF00U) -#define FLEXSPI_IPEDCTX1END_end_address_SHIFT (8U) -/*! end_address - End address of region 1. Minimal 256 Bytes aligned. It is system address. - */ -#define FLEXSPI_IPEDCTX1END_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1END_end_address_SHIFT)) & FLEXSPI_IPEDCTX1END_end_address_MASK) -/*! @} */ - -/*! @name IPEDCTX1AAD0 - IPED context1 AAD0 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_MASK (0xFFFFFFFFU) -#define FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_SHIFT (0U) -/*! CTX1_AAD0 - Lowest 32 bits of AAD for region 1. - */ -#define FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_SHIFT)) & FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_MASK) -/*! @} */ - -/*! @name IPEDCTX1AAD1 - IPED context1 AAD1 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_MASK (0xFFFFFFFFU) -#define FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_SHIFT (0U) -/*! CTX1_AAD1 - Highest 32 bits of AAD for region 1. - */ -#define FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_SHIFT)) & FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_MASK) -/*! @} */ - -/*! @name IPEDCTX2IV0 - IPED context2 IV0 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX2IV0_CTX2_IV0_MASK (0xFFFFFFFFU) -#define FLEXSPI_IPEDCTX2IV0_CTX2_IV0_SHIFT (0U) -/*! CTX2_IV0 - Lowest 32 bits of IV for region 2. - */ -#define FLEXSPI_IPEDCTX2IV0_CTX2_IV0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2IV0_CTX2_IV0_SHIFT)) & FLEXSPI_IPEDCTX2IV0_CTX2_IV0_MASK) -/*! @} */ - -/*! @name IPEDCTX2IV1 - IPED context2 IV1 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX2IV1_CTX2_IV1_MASK (0xFFFFFFFFU) -#define FLEXSPI_IPEDCTX2IV1_CTX2_IV1_SHIFT (0U) -/*! CTX2_IV1 - Highest 32 bits of IV for region 2. - */ -#define FLEXSPI_IPEDCTX2IV1_CTX2_IV1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2IV1_CTX2_IV1_SHIFT)) & FLEXSPI_IPEDCTX2IV1_CTX2_IV1_MASK) -/*! @} */ - -/*! @name IPEDCTX2START - Start address of region 2 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX2START_GCM_MASK (0x1U) -#define FLEXSPI_IPEDCTX2START_GCM_SHIFT (0U) -/*! GCM - If this bit is 1, current region is GCM mode region. - */ -#define FLEXSPI_IPEDCTX2START_GCM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2START_GCM_SHIFT)) & FLEXSPI_IPEDCTX2START_GCM_MASK) - -#define FLEXSPI_IPEDCTX2START_ahbbuserror_dis_MASK (0x2U) -#define FLEXSPI_IPEDCTX2START_ahbbuserror_dis_SHIFT (1U) -/*! ahbbuserror_dis - If this bit is 1, ahb bus error is disable. - */ -#define FLEXSPI_IPEDCTX2START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX2START_ahbbuserror_dis_MASK) - -#define FLEXSPI_IPEDCTX2START_start_address_MASK (0xFFFFFF00U) -#define FLEXSPI_IPEDCTX2START_start_address_SHIFT (8U) -/*! start_address - Start address of region 2. Minimal 256 Bytes aligned. It is system address. - */ -#define FLEXSPI_IPEDCTX2START_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2START_start_address_SHIFT)) & FLEXSPI_IPEDCTX2START_start_address_MASK) -/*! @} */ - -/*! @name IPEDCTX2END - End address of region 2 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX2END_end_address_MASK (0xFFFFFF00U) -#define FLEXSPI_IPEDCTX2END_end_address_SHIFT (8U) -/*! end_address - End address of region 2. Minimal 256 Bytes aligned. It is system address. - */ -#define FLEXSPI_IPEDCTX2END_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2END_end_address_SHIFT)) & FLEXSPI_IPEDCTX2END_end_address_MASK) -/*! @} */ - -/*! @name IPEDCTX2AAD0 - IPED context2 AAD0 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_MASK (0xFFFFFFFFU) -#define FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_SHIFT (0U) -/*! CTX2_AAD0 - Lowest 32 bits of AAD for region 2. - */ -#define FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_SHIFT)) & FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_MASK) -/*! @} */ - -/*! @name IPEDCTX2AAD1 - IPED context2 AAD1 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_MASK (0xFFFFFFFFU) -#define FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_SHIFT (0U) -/*! CTX2_AAD1 - Highest 32 bits of AAD for region 2. - */ -#define FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_SHIFT)) & FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_MASK) -/*! @} */ - -/*! @name IPEDCTX3IV0 - IPED context3 IV0 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX3IV0_CTX3_IV0_MASK (0xFFFFFFFFU) -#define FLEXSPI_IPEDCTX3IV0_CTX3_IV0_SHIFT (0U) -/*! CTX3_IV0 - Lowest 32 bits of IV for region 3. - */ -#define FLEXSPI_IPEDCTX3IV0_CTX3_IV0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3IV0_CTX3_IV0_SHIFT)) & FLEXSPI_IPEDCTX3IV0_CTX3_IV0_MASK) -/*! @} */ - -/*! @name IPEDCTX3IV1 - IPED context3 IV1 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX3IV1_CTX3_IV1_MASK (0xFFFFFFFFU) -#define FLEXSPI_IPEDCTX3IV1_CTX3_IV1_SHIFT (0U) -/*! CTX3_IV1 - Highest 32 bits of IV for region 3. - */ -#define FLEXSPI_IPEDCTX3IV1_CTX3_IV1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3IV1_CTX3_IV1_SHIFT)) & FLEXSPI_IPEDCTX3IV1_CTX3_IV1_MASK) -/*! @} */ - -/*! @name IPEDCTX3START - Start address of region 3 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX3START_GCM_MASK (0x1U) -#define FLEXSPI_IPEDCTX3START_GCM_SHIFT (0U) -/*! GCM - If this bit is 1, current region is GCM mode region. - */ -#define FLEXSPI_IPEDCTX3START_GCM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3START_GCM_SHIFT)) & FLEXSPI_IPEDCTX3START_GCM_MASK) - -#define FLEXSPI_IPEDCTX3START_ahbbuserror_dis_MASK (0x2U) -#define FLEXSPI_IPEDCTX3START_ahbbuserror_dis_SHIFT (1U) -/*! ahbbuserror_dis - If this bit is 1, ahb bus error is disable. - */ -#define FLEXSPI_IPEDCTX3START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX3START_ahbbuserror_dis_MASK) - -#define FLEXSPI_IPEDCTX3START_start_address_MASK (0xFFFFFF00U) -#define FLEXSPI_IPEDCTX3START_start_address_SHIFT (8U) -/*! start_address - Start address of region 3. Minimal 256 Bytes aligned. It is system address. - */ -#define FLEXSPI_IPEDCTX3START_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3START_start_address_SHIFT)) & FLEXSPI_IPEDCTX3START_start_address_MASK) -/*! @} */ - -/*! @name IPEDCTX3END - End address of region 3 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX3END_end_address_MASK (0xFFFFFF00U) -#define FLEXSPI_IPEDCTX3END_end_address_SHIFT (8U) -/*! end_address - End address of region 3. Minimal 256 Bytes aligned. It is system address. - */ -#define FLEXSPI_IPEDCTX3END_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3END_end_address_SHIFT)) & FLEXSPI_IPEDCTX3END_end_address_MASK) -/*! @} */ - -/*! @name IPEDCTX3AAD0 - IPED context3 AAD0 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_MASK (0xFFFFFFFFU) -#define FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_SHIFT (0U) -/*! CTX3_AAD0 - Lowest 32 bits of AAD for region 3. - */ -#define FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_SHIFT)) & FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_MASK) -/*! @} */ - -/*! @name IPEDCTX3AAD1 - IPED context3 AAD1 */ -/*! @{ */ - -#define FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_MASK (0xFFFFFFFFU) -#define FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_SHIFT (0U) -/*! CTX3_AAD1 - Highest 32 bits of AAD for region 3. - */ -#define FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_SHIFT)) & FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLEXSPI_Register_Masks */ - - -/* FLEXSPI - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLEXSPI0 base address */ - #define FLEXSPI0_BASE (0x500C0000u) - /** Peripheral FLEXSPI0 base address */ - #define FLEXSPI0_BASE_NS (0x400C0000u) - /** Peripheral FLEXSPI0 base pointer */ - #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) - /** Peripheral FLEXSPI0 base pointer */ - #define FLEXSPI0_NS ((FLEXSPI_Type *)FLEXSPI0_BASE_NS) - /** Array initializer of FLEXSPI peripheral base addresses */ - #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } - /** Array initializer of FLEXSPI peripheral base pointers */ - #define FLEXSPI_BASE_PTRS { FLEXSPI0 } - /** Array initializer of FLEXSPI peripheral base addresses */ - #define FLEXSPI_BASE_ADDRS_NS { FLEXSPI0_BASE_NS } - /** Array initializer of FLEXSPI peripheral base pointers */ - #define FLEXSPI_BASE_PTRS_NS { FLEXSPI0_NS } -#else - /** Peripheral FLEXSPI0 base address */ - #define FLEXSPI0_BASE (0x400C0000u) - /** Peripheral FLEXSPI0 base pointer */ - #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) - /** Array initializer of FLEXSPI peripheral base addresses */ - #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } - /** Array initializer of FLEXSPI peripheral base pointers */ - #define FLEXSPI_BASE_PTRS { FLEXSPI0 } -#endif -/** Interrupt vectors for the FLEXSPI peripheral type */ -#define FLEXSPI_IRQS { FlexSPI0_IRQn } -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI0 AMBA address */ -#define FlexSPI0_AMBA_BASE (0x18000000u) -/** FlexSPI0 AMBA address */ -#define FlexSPI0_AMBA_BASE_NS (0x08000000u) -#else -/** FlexSPI0 AMBA address */ -#define FlexSPI0_AMBA_BASE (0x08000000u) -#endif - - -/*! - * @} - */ /* end of group FLEXSPI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FREQME Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FREQME_Peripheral_Access_Layer FREQME Peripheral Access Layer - * @{ - */ - -/** FREQME - Register Layout Typedef */ -typedef struct { - union { /* offset: 0x0 */ - __I uint32_t FREQMECTRL_R; /**< Frequency Measurement (in Read mode), offset: 0x0 */ - __O uint32_t FREQMECTRL_W; /**< Frequency Measurement (in Write mode), offset: 0x0 */ - }; - __IO uint32_t FREQMECTRLSTAT; /**< Frequency Measurement Control Status, offset: 0x4 */ - __IO uint32_t FREQMEMIN; /**< Frequency Measurement Minimum, offset: 0x8 */ - __IO uint32_t FREQMEMAX; /**< Frequency Measurement Maximum, offset: 0xC */ -} FREQME_Type; - -/* ---------------------------------------------------------------------------- - -- FREQME Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FREQME_Register_Masks FREQME Register Masks - * @{ - */ - -/*! @name FREQMECTRL_R - Frequency Measurement (in Read mode) */ -/*! @{ */ - -#define FREQME_FREQMECTRL_R_RESULT_MASK (0x7FFFFFFFU) -#define FREQME_FREQMECTRL_R_RESULT_SHIFT (0U) -/*! RESULT - Result - */ -#define FREQME_FREQMECTRL_R_RESULT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_R_RESULT_SHIFT)) & FREQME_FREQMECTRL_R_RESULT_MASK) - -#define FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_MASK (0x80000000U) -#define FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_SHIFT (31U) -/*! MEASURE_IN_PROGRESS - Measure in Progress - * 0b0..Process complete. Measurement cycle is complete. The results are ready in the RESULT field. - * 0b1..In Progress. Measurement cycle is in progress. - */ -#define FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_MASK) -/*! @} */ - -/*! @name FREQMECTRL_W - Frequency Measurement (in Write mode) */ -/*! @{ */ - -#define FREQME_FREQMECTRL_W_REF_SCALE_MASK (0x1FU) -#define FREQME_FREQMECTRL_W_REF_SCALE_SHIFT (0U) -/*! REF_SCALE - Reference Clock Scaling Factor - * 0b00000..Count cycle = 2 ^ 0 = 1 - * 0b00001..Count cycle = 2 ^ 1 = 2 - * 0b00010..Count cycle = 2 ^ 2 = 4 - * 0b11111..Count cycle = 2 ^ 31 = 2,147,483,648 - */ -#define FREQME_FREQMECTRL_W_REF_SCALE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_REF_SCALE_SHIFT)) & FREQME_FREQMECTRL_W_REF_SCALE_MASK) - -#define FREQME_FREQMECTRL_W_PULSE_MODE_MASK (0x100U) -#define FREQME_FREQMECTRL_W_PULSE_MODE_SHIFT (8U) -/*! PULSE_MODE - Pulse Width Measurement mode select - * 0b0..Frequency Measurement Mode. FREQMECTRL works in a Frequency Measurement mode. Once the measurement starts - * (real count start is aligned at rising edge arrival on reference clock), the target counter increments by - * the target clock until the reference counter running by the reference clock reaches the count end point - * selected by REF_SCALE. - * 0b1..Pulse Width Measurement mode. FREQMECTRL works in a Pulse Width Measurement mode, measuring the high or - * low period of reference clock input selected by PULSE_POL. The target counter starts incrementing by the - * target clock once a corresponding trigger edge (rising edge for high period measurement and falling edge for - * low period) occurs. - */ -#define FREQME_FREQMECTRL_W_PULSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_PULSE_MODE_SHIFT)) & FREQME_FREQMECTRL_W_PULSE_MODE_MASK) - -#define FREQME_FREQMECTRL_W_PULSE_POL_MASK (0x200U) -#define FREQME_FREQMECTRL_W_PULSE_POL_SHIFT (9U) -/*! PULSE_POL - Pulse Polarity - * 0b0..High Period. High period of reference clock is measured in Pulse Width Measurement mode triggered by the - * rising edge on the reference clock input. - * 0b1..Low Period. Low period of reference clock is measured in Pulse Width Measurement mode triggered by the - * falling edge on the reference clock input. - */ -#define FREQME_FREQMECTRL_W_PULSE_POL(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_PULSE_POL_SHIFT)) & FREQME_FREQMECTRL_W_PULSE_POL_MASK) - -#define FREQME_FREQMECTRL_W_LT_MIN_INT_EN_MASK (0x1000U) -#define FREQME_FREQMECTRL_W_LT_MIN_INT_EN_SHIFT (12U) -/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable - * 0b0..Disable - * 0b1..Enable - */ -#define FREQME_FREQMECTRL_W_LT_MIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_LT_MIN_INT_EN_SHIFT)) & FREQME_FREQMECTRL_W_LT_MIN_INT_EN_MASK) - -#define FREQME_FREQMECTRL_W_GT_MAX_INT_EN_MASK (0x2000U) -#define FREQME_FREQMECTRL_W_GT_MAX_INT_EN_SHIFT (13U) -/*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable - * 0b0..Disable - * 0b1..Enable - */ -#define FREQME_FREQMECTRL_W_GT_MAX_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_GT_MAX_INT_EN_SHIFT)) & FREQME_FREQMECTRL_W_GT_MAX_INT_EN_MASK) - -#define FREQME_FREQMECTRL_W_RESULT_READY_INT_EN_MASK (0x4000U) -#define FREQME_FREQMECTRL_W_RESULT_READY_INT_EN_SHIFT (14U) -/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable - * 0b0..Disable - * 0b1..Enable - */ -#define FREQME_FREQMECTRL_W_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_RESULT_READY_INT_EN_SHIFT)) & FREQME_FREQMECTRL_W_RESULT_READY_INT_EN_MASK) - -#define FREQME_FREQMECTRL_W_CONTINUOUS_MODE_EN_MASK (0x40000000U) -#define FREQME_FREQMECTRL_W_CONTINUOUS_MODE_EN_SHIFT (30U) -/*! CONTINUOUS_MODE_EN - Continuous Mode Enable - * 0b0..Disable - * 0b1..Enable - */ -#define FREQME_FREQMECTRL_W_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_FREQMECTRL_W_CONTINUOUS_MODE_EN_MASK) - -#define FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_MASK (0x80000000U) -#define FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_SHIFT (31U) -/*! MEASURE_IN_PROGRESS - Measure in Progress - * 0b0..Force Terminate - * 0b1..Initiates Measurement Cycle - */ -#define FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_MASK) -/*! @} */ - -/*! @name FREQMECTRLSTAT - Frequency Measurement Control Status */ -/*! @{ */ - -#define FREQME_FREQMECTRLSTAT_REF_SCALE_MASK (0x1FU) -#define FREQME_FREQMECTRLSTAT_REF_SCALE_SHIFT (0U) -/*! REF_SCALE - Reference Scale Value - */ -#define FREQME_FREQMECTRLSTAT_REF_SCALE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_REF_SCALE_SHIFT)) & FREQME_FREQMECTRLSTAT_REF_SCALE_MASK) - -#define FREQME_FREQMECTRLSTAT_PULSE_MODE_MASK (0x100U) -#define FREQME_FREQMECTRLSTAT_PULSE_MODE_SHIFT (8U) -/*! PULSE_MODE - Pulse Mode Status - */ -#define FREQME_FREQMECTRLSTAT_PULSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_PULSE_MODE_SHIFT)) & FREQME_FREQMECTRLSTAT_PULSE_MODE_MASK) - -#define FREQME_FREQMECTRLSTAT_PULSE_POL_MASK (0x200U) -#define FREQME_FREQMECTRLSTAT_PULSE_POL_SHIFT (9U) -/*! PULSE_POL - Pulse Polarity Status - */ -#define FREQME_FREQMECTRLSTAT_PULSE_POL(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_PULSE_POL_SHIFT)) & FREQME_FREQMECTRLSTAT_PULSE_POL_MASK) - -#define FREQME_FREQMECTRLSTAT_LT_MIN_INT_EN_MASK (0x1000U) -#define FREQME_FREQMECTRLSTAT_LT_MIN_INT_EN_SHIFT (12U) -/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable Status - */ -#define FREQME_FREQMECTRLSTAT_LT_MIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_LT_MIN_INT_EN_SHIFT)) & FREQME_FREQMECTRLSTAT_LT_MIN_INT_EN_MASK) - -#define FREQME_FREQMECTRLSTAT_GT_MAX_INT_EN_MASK (0x2000U) -#define FREQME_FREQMECTRLSTAT_GT_MAX_INT_EN_SHIFT (13U) -/*! GT_MAX_INT_EN - Greater Then Maximum Interrupt Enable Status - */ -#define FREQME_FREQMECTRLSTAT_GT_MAX_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_GT_MAX_INT_EN_SHIFT)) & FREQME_FREQMECTRLSTAT_GT_MAX_INT_EN_MASK) - -#define FREQME_FREQMECTRLSTAT_RESULT_READY_INT_EN_MASK (0x4000U) -#define FREQME_FREQMECTRLSTAT_RESULT_READY_INT_EN_SHIFT (14U) -/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable Status - */ -#define FREQME_FREQMECTRLSTAT_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_RESULT_READY_INT_EN_SHIFT)) & FREQME_FREQMECTRLSTAT_RESULT_READY_INT_EN_MASK) - -#define FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK (0x1000000U) -#define FREQME_FREQMECTRLSTAT_LT_MIN_STAT_SHIFT (24U) -/*! LT_MIN_STAT - Less Than Minimum Results Status - */ -#define FREQME_FREQMECTRLSTAT_LT_MIN_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_LT_MIN_STAT_SHIFT)) & FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK) - -#define FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK (0x2000000U) -#define FREQME_FREQMECTRLSTAT_GT_MAX_STAT_SHIFT (25U) -/*! GT_MAX_STAT - Greater Than Maximum Result Status - */ -#define FREQME_FREQMECTRLSTAT_GT_MAX_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_GT_MAX_STAT_SHIFT)) & FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK) - -#define FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK (0x4000000U) -#define FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_SHIFT (26U) -/*! RESULT_READY_STAT - Result Ready Status - */ -#define FREQME_FREQMECTRLSTAT_RESULT_READY_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_SHIFT)) & FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK) - -#define FREQME_FREQMECTRLSTAT_CONTINUOUS_MODE_EN_MASK (0x40000000U) -#define FREQME_FREQMECTRLSTAT_CONTINUOUS_MODE_EN_SHIFT (30U) -/*! CONTINUOUS_MODE_EN - Continuous Mode Enable Status - */ -#define FREQME_FREQMECTRLSTAT_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_FREQMECTRLSTAT_CONTINUOUS_MODE_EN_MASK) - -#define FREQME_FREQMECTRLSTAT_MEASURE_IN_PROGRESS_MASK (0x80000000U) -#define FREQME_FREQMECTRLSTAT_MEASURE_IN_PROGRESS_SHIFT (31U) -/*! MEASURE_IN_PROGRESS - Measure in Progress Status - */ -#define FREQME_FREQMECTRLSTAT_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_FREQMECTRLSTAT_MEASURE_IN_PROGRESS_MASK) -/*! @} */ - -/*! @name FREQMEMIN - Frequency Measurement Minimum */ -/*! @{ */ - -#define FREQME_FREQMEMIN_MIN_VALUE_MASK (0x7FFFFFFFU) -#define FREQME_FREQMEMIN_MIN_VALUE_SHIFT (0U) -/*! MIN_VALUE - Minumum Value - */ -#define FREQME_FREQMEMIN_MIN_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMEMIN_MIN_VALUE_SHIFT)) & FREQME_FREQMEMIN_MIN_VALUE_MASK) -/*! @} */ - -/*! @name FREQMEMAX - Frequency Measurement Maximum */ -/*! @{ */ - -#define FREQME_FREQMEMAX_MAX_VALUE_MASK (0x7FFFFFFFU) -#define FREQME_FREQMEMAX_MAX_VALUE_SHIFT (0U) -/*! MAX_VALUE - Maximum Value - */ -#define FREQME_FREQMEMAX_MAX_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMEMAX_MAX_VALUE_SHIFT)) & FREQME_FREQMEMAX_MAX_VALUE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FREQME_Register_Masks */ - - -/* FREQME - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FREQME base address */ - #define FREQME_BASE (0x50013140u) - /** Peripheral FREQME base address */ - #define FREQME_BASE_NS (0x40013140u) - /** Peripheral FREQME base pointer */ - #define FREQME ((FREQME_Type *)FREQME_BASE) - /** Peripheral FREQME base pointer */ - #define FREQME_NS ((FREQME_Type *)FREQME_BASE_NS) - /** Array initializer of FREQME peripheral base addresses */ - #define FREQME_BASE_ADDRS { FREQME_BASE } - /** Array initializer of FREQME peripheral base pointers */ - #define FREQME_BASE_PTRS { FREQME } - /** Array initializer of FREQME peripheral base addresses */ - #define FREQME_BASE_ADDRS_NS { FREQME_BASE_NS } - /** Array initializer of FREQME peripheral base pointers */ - #define FREQME_BASE_PTRS_NS { FREQME_NS } -#else - /** Peripheral FREQME base address */ - #define FREQME_BASE (0x40013140u) - /** Peripheral FREQME base pointer */ - #define FREQME ((FREQME_Type *)FREQME_BASE) - /** Array initializer of FREQME peripheral base addresses */ - #define FREQME_BASE_ADDRS { FREQME_BASE } - /** Array initializer of FREQME peripheral base pointers */ - #define FREQME_BASE_PTRS { FREQME } -#endif -/** Interrupt vectors for the FREQME peripheral type */ -#define FREQME_IRQS { Freqme_IRQn } - -/*! - * @} - */ /* end of group FREQME_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer - * @{ - */ - -/** GINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< GPIO grouped interrupt control, offset: 0x0 */ - uint8_t RESERVED_0[28]; - __IO uint32_t PORT_POL[2]; /**< Port polarity, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[24]; - __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ -} GINT_Type; - -/* ---------------------------------------------------------------------------- - -- GINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Register_Masks GINT Register Masks - * @{ - */ - -/*! @name CTRL - GPIO grouped interrupt control */ -/*! @{ */ - -#define GINT_CTRL_INT_MASK (0x1U) -#define GINT_CTRL_INT_SHIFT (0U) -/*! INT - Group interrupt status - * 0b0..No interrupt request is pending. - * 0b1..Interrupt request is pending. - */ -#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) - -#define GINT_CTRL_COMB_MASK (0x2U) -#define GINT_CTRL_COMB_SHIFT (1U) -/*! COMB - Combine enabled inputs for group interrupt - * 0b0..OR functionality - * 0b1..AND functionality - */ -#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) - -#define GINT_CTRL_TRIG_MASK (0x4U) -#define GINT_CTRL_TRIG_SHIFT (2U) -/*! TRIG - Group interrupt trigger - * 0b0..Edge-triggered - * 0b1..Level-triggered - */ -#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) -/*! @} */ - -/*! @name PORT_POL - Port polarity */ -/*! @{ */ - -#define GINT_PORT_POL_POL0_MASK (0x1U) -#define GINT_PORT_POL_POL0_SHIFT (0U) -/*! POL0 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL0_SHIFT)) & GINT_PORT_POL_POL0_MASK) - -#define GINT_PORT_POL_POL1_MASK (0x2U) -#define GINT_PORT_POL_POL1_SHIFT (1U) -/*! POL1 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL1_SHIFT)) & GINT_PORT_POL_POL1_MASK) - -#define GINT_PORT_POL_POL2_MASK (0x4U) -#define GINT_PORT_POL_POL2_SHIFT (2U) -/*! POL2 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL2_SHIFT)) & GINT_PORT_POL_POL2_MASK) - -#define GINT_PORT_POL_POL3_MASK (0x8U) -#define GINT_PORT_POL_POL3_SHIFT (3U) -/*! POL3 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL3_SHIFT)) & GINT_PORT_POL_POL3_MASK) - -#define GINT_PORT_POL_POL4_MASK (0x10U) -#define GINT_PORT_POL_POL4_SHIFT (4U) -/*! POL4 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL4_SHIFT)) & GINT_PORT_POL_POL4_MASK) - -#define GINT_PORT_POL_POL5_MASK (0x20U) -#define GINT_PORT_POL_POL5_SHIFT (5U) -/*! POL5 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL5_SHIFT)) & GINT_PORT_POL_POL5_MASK) - -#define GINT_PORT_POL_POL6_MASK (0x40U) -#define GINT_PORT_POL_POL6_SHIFT (6U) -/*! POL6 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL6_SHIFT)) & GINT_PORT_POL_POL6_MASK) - -#define GINT_PORT_POL_POL7_MASK (0x80U) -#define GINT_PORT_POL_POL7_SHIFT (7U) -/*! POL7 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL7_SHIFT)) & GINT_PORT_POL_POL7_MASK) - -#define GINT_PORT_POL_POL8_MASK (0x100U) -#define GINT_PORT_POL_POL8_SHIFT (8U) -/*! POL8 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL8(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL8_SHIFT)) & GINT_PORT_POL_POL8_MASK) - -#define GINT_PORT_POL_POL9_MASK (0x200U) -#define GINT_PORT_POL_POL9_SHIFT (9U) -/*! POL9 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL9(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL9_SHIFT)) & GINT_PORT_POL_POL9_MASK) - -#define GINT_PORT_POL_POL10_MASK (0x400U) -#define GINT_PORT_POL_POL10_SHIFT (10U) -/*! POL10 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL10(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL10_SHIFT)) & GINT_PORT_POL_POL10_MASK) - -#define GINT_PORT_POL_POL11_MASK (0x800U) -#define GINT_PORT_POL_POL11_SHIFT (11U) -/*! POL11 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL11(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL11_SHIFT)) & GINT_PORT_POL_POL11_MASK) - -#define GINT_PORT_POL_POL12_MASK (0x1000U) -#define GINT_PORT_POL_POL12_SHIFT (12U) -/*! POL12 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL12(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL12_SHIFT)) & GINT_PORT_POL_POL12_MASK) - -#define GINT_PORT_POL_POL13_MASK (0x2000U) -#define GINT_PORT_POL_POL13_SHIFT (13U) -/*! POL13 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL13(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL13_SHIFT)) & GINT_PORT_POL_POL13_MASK) - -#define GINT_PORT_POL_POL14_MASK (0x4000U) -#define GINT_PORT_POL_POL14_SHIFT (14U) -/*! POL14 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL14(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL14_SHIFT)) & GINT_PORT_POL_POL14_MASK) - -#define GINT_PORT_POL_POL15_MASK (0x8000U) -#define GINT_PORT_POL_POL15_SHIFT (15U) -/*! POL15 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL15(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL15_SHIFT)) & GINT_PORT_POL_POL15_MASK) - -#define GINT_PORT_POL_POL16_MASK (0x10000U) -#define GINT_PORT_POL_POL16_SHIFT (16U) -/*! POL16 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL16(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL16_SHIFT)) & GINT_PORT_POL_POL16_MASK) - -#define GINT_PORT_POL_POL17_MASK (0x20000U) -#define GINT_PORT_POL_POL17_SHIFT (17U) -/*! POL17 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL17(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL17_SHIFT)) & GINT_PORT_POL_POL17_MASK) - -#define GINT_PORT_POL_POL18_MASK (0x40000U) -#define GINT_PORT_POL_POL18_SHIFT (18U) -/*! POL18 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL18(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL18_SHIFT)) & GINT_PORT_POL_POL18_MASK) - -#define GINT_PORT_POL_POL19_MASK (0x80000U) -#define GINT_PORT_POL_POL19_SHIFT (19U) -/*! POL19 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL19(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL19_SHIFT)) & GINT_PORT_POL_POL19_MASK) - -#define GINT_PORT_POL_POL20_MASK (0x100000U) -#define GINT_PORT_POL_POL20_SHIFT (20U) -/*! POL20 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL20(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL20_SHIFT)) & GINT_PORT_POL_POL20_MASK) - -#define GINT_PORT_POL_POL21_MASK (0x200000U) -#define GINT_PORT_POL_POL21_SHIFT (21U) -/*! POL21 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL21(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL21_SHIFT)) & GINT_PORT_POL_POL21_MASK) - -#define GINT_PORT_POL_POL22_MASK (0x400000U) -#define GINT_PORT_POL_POL22_SHIFT (22U) -/*! POL22 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL22(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL22_SHIFT)) & GINT_PORT_POL_POL22_MASK) - -#define GINT_PORT_POL_POL23_MASK (0x800000U) -#define GINT_PORT_POL_POL23_SHIFT (23U) -/*! POL23 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL23(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL23_SHIFT)) & GINT_PORT_POL_POL23_MASK) - -#define GINT_PORT_POL_POL24_MASK (0x1000000U) -#define GINT_PORT_POL_POL24_SHIFT (24U) -/*! POL24 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL24(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL24_SHIFT)) & GINT_PORT_POL_POL24_MASK) - -#define GINT_PORT_POL_POL25_MASK (0x2000000U) -#define GINT_PORT_POL_POL25_SHIFT (25U) -/*! POL25 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL25(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL25_SHIFT)) & GINT_PORT_POL_POL25_MASK) - -#define GINT_PORT_POL_POL26_MASK (0x4000000U) -#define GINT_PORT_POL_POL26_SHIFT (26U) -/*! POL26 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL26(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL26_SHIFT)) & GINT_PORT_POL_POL26_MASK) - -#define GINT_PORT_POL_POL27_MASK (0x8000000U) -#define GINT_PORT_POL_POL27_SHIFT (27U) -/*! POL27 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL27(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL27_SHIFT)) & GINT_PORT_POL_POL27_MASK) - -#define GINT_PORT_POL_POL28_MASK (0x10000000U) -#define GINT_PORT_POL_POL28_SHIFT (28U) -/*! POL28 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL28(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL28_SHIFT)) & GINT_PORT_POL_POL28_MASK) - -#define GINT_PORT_POL_POL29_MASK (0x20000000U) -#define GINT_PORT_POL_POL29_SHIFT (29U) -/*! POL29 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL29(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL29_SHIFT)) & GINT_PORT_POL_POL29_MASK) - -#define GINT_PORT_POL_POL30_MASK (0x40000000U) -#define GINT_PORT_POL_POL30_SHIFT (30U) -/*! POL30 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL30(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL30_SHIFT)) & GINT_PORT_POL_POL30_MASK) - -#define GINT_PORT_POL_POL31_MASK (0x80000000U) -#define GINT_PORT_POL_POL31_SHIFT (31U) -/*! POL31 - Polarity of pin n of the port - * 0b0..Pin is active LOW - * 0b1..Pin is active HIGH - */ -#define GINT_PORT_POL_POL31(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL31_SHIFT)) & GINT_PORT_POL_POL31_MASK) -/*! @} */ - -/* The count of GINT_PORT_POL */ -#define GINT_PORT_POL_COUNT (2U) - -/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ -/*! @{ */ - -#define GINT_PORT_ENA_ENA0_MASK (0x1U) -#define GINT_PORT_ENA_ENA0_SHIFT (0U) -/*! ENA0 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA0(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA0_SHIFT)) & GINT_PORT_ENA_ENA0_MASK) - -#define GINT_PORT_ENA_ENA1_MASK (0x2U) -#define GINT_PORT_ENA_ENA1_SHIFT (1U) -/*! ENA1 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA1(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA1_SHIFT)) & GINT_PORT_ENA_ENA1_MASK) - -#define GINT_PORT_ENA_ENA2_MASK (0x4U) -#define GINT_PORT_ENA_ENA2_SHIFT (2U) -/*! ENA2 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA2(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA2_SHIFT)) & GINT_PORT_ENA_ENA2_MASK) - -#define GINT_PORT_ENA_ENA3_MASK (0x8U) -#define GINT_PORT_ENA_ENA3_SHIFT (3U) -/*! ENA3 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA3(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA3_SHIFT)) & GINT_PORT_ENA_ENA3_MASK) - -#define GINT_PORT_ENA_ENA4_MASK (0x10U) -#define GINT_PORT_ENA_ENA4_SHIFT (4U) -/*! ENA4 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA4(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA4_SHIFT)) & GINT_PORT_ENA_ENA4_MASK) - -#define GINT_PORT_ENA_ENA5_MASK (0x20U) -#define GINT_PORT_ENA_ENA5_SHIFT (5U) -/*! ENA5 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA5(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA5_SHIFT)) & GINT_PORT_ENA_ENA5_MASK) - -#define GINT_PORT_ENA_ENA6_MASK (0x40U) -#define GINT_PORT_ENA_ENA6_SHIFT (6U) -/*! ENA6 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA6(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA6_SHIFT)) & GINT_PORT_ENA_ENA6_MASK) - -#define GINT_PORT_ENA_ENA7_MASK (0x80U) -#define GINT_PORT_ENA_ENA7_SHIFT (7U) -/*! ENA7 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA7(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA7_SHIFT)) & GINT_PORT_ENA_ENA7_MASK) - -#define GINT_PORT_ENA_ENA8_MASK (0x100U) -#define GINT_PORT_ENA_ENA8_SHIFT (8U) -/*! ENA8 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA8(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA8_SHIFT)) & GINT_PORT_ENA_ENA8_MASK) - -#define GINT_PORT_ENA_ENA9_MASK (0x200U) -#define GINT_PORT_ENA_ENA9_SHIFT (9U) -/*! ENA9 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA9(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA9_SHIFT)) & GINT_PORT_ENA_ENA9_MASK) - -#define GINT_PORT_ENA_ENA10_MASK (0x400U) -#define GINT_PORT_ENA_ENA10_SHIFT (10U) -/*! ENA10 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA10(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA10_SHIFT)) & GINT_PORT_ENA_ENA10_MASK) - -#define GINT_PORT_ENA_ENA11_MASK (0x800U) -#define GINT_PORT_ENA_ENA11_SHIFT (11U) -/*! ENA11 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA11(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA11_SHIFT)) & GINT_PORT_ENA_ENA11_MASK) - -#define GINT_PORT_ENA_ENA12_MASK (0x1000U) -#define GINT_PORT_ENA_ENA12_SHIFT (12U) -/*! ENA12 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA12(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA12_SHIFT)) & GINT_PORT_ENA_ENA12_MASK) - -#define GINT_PORT_ENA_ENA13_MASK (0x2000U) -#define GINT_PORT_ENA_ENA13_SHIFT (13U) -/*! ENA13 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA13(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA13_SHIFT)) & GINT_PORT_ENA_ENA13_MASK) - -#define GINT_PORT_ENA_ENA14_MASK (0x4000U) -#define GINT_PORT_ENA_ENA14_SHIFT (14U) -/*! ENA14 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA14(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA14_SHIFT)) & GINT_PORT_ENA_ENA14_MASK) - -#define GINT_PORT_ENA_ENA15_MASK (0x8000U) -#define GINT_PORT_ENA_ENA15_SHIFT (15U) -/*! ENA15 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA15(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA15_SHIFT)) & GINT_PORT_ENA_ENA15_MASK) - -#define GINT_PORT_ENA_ENA16_MASK (0x10000U) -#define GINT_PORT_ENA_ENA16_SHIFT (16U) -/*! ENA16 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA16(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA16_SHIFT)) & GINT_PORT_ENA_ENA16_MASK) - -#define GINT_PORT_ENA_ENA17_MASK (0x20000U) -#define GINT_PORT_ENA_ENA17_SHIFT (17U) -/*! ENA17 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA17(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA17_SHIFT)) & GINT_PORT_ENA_ENA17_MASK) - -#define GINT_PORT_ENA_ENA18_MASK (0x40000U) -#define GINT_PORT_ENA_ENA18_SHIFT (18U) -/*! ENA18 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA18(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA18_SHIFT)) & GINT_PORT_ENA_ENA18_MASK) - -#define GINT_PORT_ENA_ENA19_MASK (0x80000U) -#define GINT_PORT_ENA_ENA19_SHIFT (19U) -/*! ENA19 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA19(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA19_SHIFT)) & GINT_PORT_ENA_ENA19_MASK) - -#define GINT_PORT_ENA_ENA20_MASK (0x100000U) -#define GINT_PORT_ENA_ENA20_SHIFT (20U) -/*! ENA20 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA20(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA20_SHIFT)) & GINT_PORT_ENA_ENA20_MASK) - -#define GINT_PORT_ENA_ENA21_MASK (0x200000U) -#define GINT_PORT_ENA_ENA21_SHIFT (21U) -/*! ENA21 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA21(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA21_SHIFT)) & GINT_PORT_ENA_ENA21_MASK) - -#define GINT_PORT_ENA_ENA22_MASK (0x400000U) -#define GINT_PORT_ENA_ENA22_SHIFT (22U) -/*! ENA22 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA22(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA22_SHIFT)) & GINT_PORT_ENA_ENA22_MASK) - -#define GINT_PORT_ENA_ENA23_MASK (0x800000U) -#define GINT_PORT_ENA_ENA23_SHIFT (23U) -/*! ENA23 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA23(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA23_SHIFT)) & GINT_PORT_ENA_ENA23_MASK) - -#define GINT_PORT_ENA_ENA24_MASK (0x1000000U) -#define GINT_PORT_ENA_ENA24_SHIFT (24U) -/*! ENA24 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA24(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA24_SHIFT)) & GINT_PORT_ENA_ENA24_MASK) - -#define GINT_PORT_ENA_ENA25_MASK (0x2000000U) -#define GINT_PORT_ENA_ENA25_SHIFT (25U) -/*! ENA25 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA25(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA25_SHIFT)) & GINT_PORT_ENA_ENA25_MASK) - -#define GINT_PORT_ENA_ENA26_MASK (0x4000000U) -#define GINT_PORT_ENA_ENA26_SHIFT (26U) -/*! ENA26 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA26(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA26_SHIFT)) & GINT_PORT_ENA_ENA26_MASK) - -#define GINT_PORT_ENA_ENA27_MASK (0x8000000U) -#define GINT_PORT_ENA_ENA27_SHIFT (27U) -/*! ENA27 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA27(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA27_SHIFT)) & GINT_PORT_ENA_ENA27_MASK) - -#define GINT_PORT_ENA_ENA28_MASK (0x10000000U) -#define GINT_PORT_ENA_ENA28_SHIFT (28U) -/*! ENA28 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA28(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA28_SHIFT)) & GINT_PORT_ENA_ENA28_MASK) - -#define GINT_PORT_ENA_ENA29_MASK (0x20000000U) -#define GINT_PORT_ENA_ENA29_SHIFT (29U) -/*! ENA29 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA29(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA29_SHIFT)) & GINT_PORT_ENA_ENA29_MASK) - -#define GINT_PORT_ENA_ENA30_MASK (0x40000000U) -#define GINT_PORT_ENA_ENA30_SHIFT (30U) -/*! ENA30 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA30(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA30_SHIFT)) & GINT_PORT_ENA_ENA30_MASK) - -#define GINT_PORT_ENA_ENA31_MASK (0x80000000U) -#define GINT_PORT_ENA_ENA31_SHIFT (31U) -/*! ENA31 - Enables port pin n to contribute to the group interrupt - * 0b0..Pin is disabled and does not contribute to the grouped interrupt - * 0b1..Pin is enabled and contributes to the grouped interrupt - */ -#define GINT_PORT_ENA_ENA31(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA31_SHIFT)) & GINT_PORT_ENA_ENA31_MASK) -/*! @} */ - -/* The count of GINT_PORT_ENA */ -#define GINT_PORT_ENA_COUNT (2U) - - -/*! - * @} - */ /* end of group GINT_Register_Masks */ - - -/* GINT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral GINT0 base address */ - #define GINT0_BASE (0x50002000u) - /** Peripheral GINT0 base address */ - #define GINT0_BASE_NS (0x40002000u) - /** Peripheral GINT0 base pointer */ - #define GINT0 ((GINT_Type *)GINT0_BASE) - /** Peripheral GINT0 base pointer */ - #define GINT0_NS ((GINT_Type *)GINT0_BASE_NS) - /** Peripheral GINT1 base address */ - #define GINT1_BASE (0x50003000u) - /** Peripheral GINT1 base address */ - #define GINT1_BASE_NS (0x40003000u) - /** Peripheral GINT1 base pointer */ - #define GINT1 ((GINT_Type *)GINT1_BASE) - /** Peripheral GINT1 base pointer */ - #define GINT1_NS ((GINT_Type *)GINT1_BASE_NS) - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS { GINT0, GINT1 } - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS_NS { GINT0_BASE_NS, GINT1_BASE_NS } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS_NS { GINT0_NS, GINT1_NS } -#else - /** Peripheral GINT0 base address */ - #define GINT0_BASE (0x40002000u) - /** Peripheral GINT0 base pointer */ - #define GINT0 ((GINT_Type *)GINT0_BASE) - /** Peripheral GINT1 base address */ - #define GINT1_BASE (0x40003000u) - /** Peripheral GINT1 base pointer */ - #define GINT1 ((GINT_Type *)GINT1_BASE) - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS { GINT0, GINT1 } -#endif -/** Interrupt vectors for the GINT peripheral type */ -#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } - -/*! - * @} - */ /* end of group GINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer - * @{ - */ - -/** GPIO - Register Layout Typedef */ -typedef struct { - __IO uint8_t B[4][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ - uint8_t RESERVED_0[3968]; - __IO uint32_t W[4][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ - uint8_t RESERVED_1[3584]; - __O uint32_t DIR[4]; /**< Port direction, array offset: 0x2000, array step: 0x4 */ - uint8_t RESERVED_2[112]; - __IO uint32_t MASK[4]; /**< Port mask, array offset: 0x2080, array step: 0x4 */ - uint8_t RESERVED_3[112]; - __IO uint32_t PIN[4]; /**< Port pin, array offset: 0x2100, array step: 0x4 */ - uint8_t RESERVED_4[112]; - __IO uint32_t MPIN[4]; /**< Masked Port Pin, array offset: 0x2180, array step: 0x4 */ - uint8_t RESERVED_5[112]; - __IO uint32_t SET[4]; /**< Port set, array offset: 0x2200, array step: 0x4 */ - uint8_t RESERVED_6[112]; - __IO uint32_t CLR[4]; /**< Port clear, array offset: 0x2280, array step: 0x4 */ - uint8_t RESERVED_7[112]; - __O uint32_t NOT[4]; /**< Port toggle, array offset: 0x2300, array step: 0x4 */ - uint8_t RESERVED_8[112]; - __O uint32_t DIRSET[4]; /**< Port direction set, array offset: 0x2380, array step: 0x4 */ - uint8_t RESERVED_9[112]; - __IO uint32_t DIRCLR[4]; /**< Port direction clear, array offset: 0x2400, array step: 0x4 */ - uint8_t RESERVED_10[112]; - __O uint32_t DIRNOT[4]; /**< Port direction toggle, array offset: 0x2480, array step: 0x4 */ - uint8_t RESERVED_11[112]; - __IO uint32_t INTENA[4]; /**< Interrupt A enable control, array offset: 0x2500, array step: 0x4 */ - uint8_t RESERVED_12[112]; - __IO uint32_t INTENB[4]; /**< Interrupt B enable control, array offset: 0x2580, array step: 0x4 */ - uint8_t RESERVED_13[112]; - __IO uint32_t INTPOL[4]; /**< Interupt polarity control, array offset: 0x2600, array step: 0x4 */ - uint8_t RESERVED_14[112]; - __IO uint32_t INTEDG[4]; /**< Interrupt edge select, array offset: 0x2680, array step: 0x4 */ - uint8_t RESERVED_15[112]; - __IO uint32_t INTSTATA[4]; /**< Interrupt status for interrupt A, array offset: 0x2700, array step: 0x4 */ - uint8_t RESERVED_16[112]; - __IO uint32_t INTSTATB[4]; /**< Interrupt status for interrupt B, array offset: 0x2780, array step: 0x4 */ -} GPIO_Type; - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/*! @name BYTE_PIN_BYTE_PIN_B - Byte pin registers for all port GPIO pins */ -/*! @{ */ - -#define GPIO_BYTE_PIN_BYTE_PIN_B_PBYTE_MASK (0x1U) -#define GPIO_BYTE_PIN_BYTE_PIN_B_PBYTE_SHIFT (0U) -/*! PBYTE - Port Byte - */ -#define GPIO_BYTE_PIN_BYTE_PIN_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_BYTE_PIN_BYTE_PIN_B_PBYTE_SHIFT)) & GPIO_BYTE_PIN_BYTE_PIN_B_PBYTE_MASK) -/*! @} */ - -/* The count of GPIO_BYTE_PIN_BYTE_PIN_B */ -#define GPIO_BYTE_PIN_BYTE_PIN_B_COUNT (4U) - -/* The count of GPIO_BYTE_PIN_BYTE_PIN_B */ -#define GPIO_BYTE_PIN_BYTE_PIN_B_COUNT2 (32U) - -/*! @name WORD_PIN_WORD_PIN_W - Word pin registers for all port GPIO pins */ -/*! @{ */ - -#define GPIO_WORD_PIN_WORD_PIN_W_PWORD_MASK (0xFFFFFFFFU) -#define GPIO_WORD_PIN_WORD_PIN_W_PWORD_SHIFT (0U) -/*! PWORD - PWORD - */ -#define GPIO_WORD_PIN_WORD_PIN_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_WORD_PIN_WORD_PIN_W_PWORD_SHIFT)) & GPIO_WORD_PIN_WORD_PIN_W_PWORD_MASK) -/*! @} */ - -/* The count of GPIO_WORD_PIN_WORD_PIN_W */ -#define GPIO_WORD_PIN_WORD_PIN_W_COUNT (4U) - -/* The count of GPIO_WORD_PIN_WORD_PIN_W */ -#define GPIO_WORD_PIN_WORD_PIN_W_COUNT2 (32U) - -/*! @name DIR - Port direction */ -/*! @{ */ - -#define GPIO_DIR_DIRP0_MASK (0x1U) -#define GPIO_DIR_DIRP0_SHIFT (0U) -/*! DIRP0 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP0_SHIFT)) & GPIO_DIR_DIRP0_MASK) - -#define GPIO_DIR_DIRP1_MASK (0x2U) -#define GPIO_DIR_DIRP1_SHIFT (1U) -/*! DIRP1 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP1_SHIFT)) & GPIO_DIR_DIRP1_MASK) - -#define GPIO_DIR_DIRP2_MASK (0x4U) -#define GPIO_DIR_DIRP2_SHIFT (2U) -/*! DIRP2 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP2_SHIFT)) & GPIO_DIR_DIRP2_MASK) - -#define GPIO_DIR_DIRP3_MASK (0x8U) -#define GPIO_DIR_DIRP3_SHIFT (3U) -/*! DIRP3 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP3_SHIFT)) & GPIO_DIR_DIRP3_MASK) - -#define GPIO_DIR_DIRP4_MASK (0x10U) -#define GPIO_DIR_DIRP4_SHIFT (4U) -/*! DIRP4 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP4_SHIFT)) & GPIO_DIR_DIRP4_MASK) - -#define GPIO_DIR_DIRP5_MASK (0x20U) -#define GPIO_DIR_DIRP5_SHIFT (5U) -/*! DIRP5 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP5_SHIFT)) & GPIO_DIR_DIRP5_MASK) - -#define GPIO_DIR_DIRP6_MASK (0x40U) -#define GPIO_DIR_DIRP6_SHIFT (6U) -/*! DIRP6 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP6_SHIFT)) & GPIO_DIR_DIRP6_MASK) - -#define GPIO_DIR_DIRP7_MASK (0x80U) -#define GPIO_DIR_DIRP7_SHIFT (7U) -/*! DIRP7 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP7_SHIFT)) & GPIO_DIR_DIRP7_MASK) - -#define GPIO_DIR_DIRP8_MASK (0x100U) -#define GPIO_DIR_DIRP8_SHIFT (8U) -/*! DIRP8 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP8_SHIFT)) & GPIO_DIR_DIRP8_MASK) - -#define GPIO_DIR_DIRP9_MASK (0x200U) -#define GPIO_DIR_DIRP9_SHIFT (9U) -/*! DIRP9 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP9_SHIFT)) & GPIO_DIR_DIRP9_MASK) - -#define GPIO_DIR_DIRP10_MASK (0x400U) -#define GPIO_DIR_DIRP10_SHIFT (10U) -/*! DIRP10 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP10_SHIFT)) & GPIO_DIR_DIRP10_MASK) - -#define GPIO_DIR_DIRP11_MASK (0x800U) -#define GPIO_DIR_DIRP11_SHIFT (11U) -/*! DIRP11 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP11_SHIFT)) & GPIO_DIR_DIRP11_MASK) - -#define GPIO_DIR_DIRP12_MASK (0x1000U) -#define GPIO_DIR_DIRP12_SHIFT (12U) -/*! DIRP12 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP12_SHIFT)) & GPIO_DIR_DIRP12_MASK) - -#define GPIO_DIR_DIRP13_MASK (0x2000U) -#define GPIO_DIR_DIRP13_SHIFT (13U) -/*! DIRP13 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP13_SHIFT)) & GPIO_DIR_DIRP13_MASK) - -#define GPIO_DIR_DIRP14_MASK (0x4000U) -#define GPIO_DIR_DIRP14_SHIFT (14U) -/*! DIRP14 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP14_SHIFT)) & GPIO_DIR_DIRP14_MASK) - -#define GPIO_DIR_DIRP15_MASK (0x8000U) -#define GPIO_DIR_DIRP15_SHIFT (15U) -/*! DIRP15 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP15_SHIFT)) & GPIO_DIR_DIRP15_MASK) - -#define GPIO_DIR_DIRP16_MASK (0x10000U) -#define GPIO_DIR_DIRP16_SHIFT (16U) -/*! DIRP16 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP16_SHIFT)) & GPIO_DIR_DIRP16_MASK) - -#define GPIO_DIR_DIRP17_MASK (0x20000U) -#define GPIO_DIR_DIRP17_SHIFT (17U) -/*! DIRP17 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP17_SHIFT)) & GPIO_DIR_DIRP17_MASK) - -#define GPIO_DIR_DIRP18_MASK (0x40000U) -#define GPIO_DIR_DIRP18_SHIFT (18U) -/*! DIRP18 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP18_SHIFT)) & GPIO_DIR_DIRP18_MASK) - -#define GPIO_DIR_DIRP19_MASK (0x80000U) -#define GPIO_DIR_DIRP19_SHIFT (19U) -/*! DIRP19 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP19_SHIFT)) & GPIO_DIR_DIRP19_MASK) - -#define GPIO_DIR_DIRP20_MASK (0x100000U) -#define GPIO_DIR_DIRP20_SHIFT (20U) -/*! DIRP20 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP20_SHIFT)) & GPIO_DIR_DIRP20_MASK) - -#define GPIO_DIR_DIRP21_MASK (0x200000U) -#define GPIO_DIR_DIRP21_SHIFT (21U) -/*! DIRP21 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP21_SHIFT)) & GPIO_DIR_DIRP21_MASK) - -#define GPIO_DIR_DIRP22_MASK (0x400000U) -#define GPIO_DIR_DIRP22_SHIFT (22U) -/*! DIRP22 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP22_SHIFT)) & GPIO_DIR_DIRP22_MASK) - -#define GPIO_DIR_DIRP23_MASK (0x800000U) -#define GPIO_DIR_DIRP23_SHIFT (23U) -/*! DIRP23 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP23_SHIFT)) & GPIO_DIR_DIRP23_MASK) - -#define GPIO_DIR_DIRP24_MASK (0x1000000U) -#define GPIO_DIR_DIRP24_SHIFT (24U) -/*! DIRP24 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP24_SHIFT)) & GPIO_DIR_DIRP24_MASK) - -#define GPIO_DIR_DIRP25_MASK (0x2000000U) -#define GPIO_DIR_DIRP25_SHIFT (25U) -/*! DIRP25 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP25_SHIFT)) & GPIO_DIR_DIRP25_MASK) - -#define GPIO_DIR_DIRP26_MASK (0x4000000U) -#define GPIO_DIR_DIRP26_SHIFT (26U) -/*! DIRP26 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP26_SHIFT)) & GPIO_DIR_DIRP26_MASK) - -#define GPIO_DIR_DIRP27_MASK (0x8000000U) -#define GPIO_DIR_DIRP27_SHIFT (27U) -/*! DIRP27 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP27_SHIFT)) & GPIO_DIR_DIRP27_MASK) - -#define GPIO_DIR_DIRP28_MASK (0x10000000U) -#define GPIO_DIR_DIRP28_SHIFT (28U) -/*! DIRP28 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP28_SHIFT)) & GPIO_DIR_DIRP28_MASK) - -#define GPIO_DIR_DIRP29_MASK (0x20000000U) -#define GPIO_DIR_DIRP29_SHIFT (29U) -/*! DIRP29 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP29_SHIFT)) & GPIO_DIR_DIRP29_MASK) - -#define GPIO_DIR_DIRP30_MASK (0x40000000U) -#define GPIO_DIR_DIRP30_SHIFT (30U) -/*! DIRP30 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP30_SHIFT)) & GPIO_DIR_DIRP30_MASK) - -#define GPIO_DIR_DIRP31_MASK (0x80000000U) -#define GPIO_DIR_DIRP31_SHIFT (31U) -/*! DIRP31 - Selects pin direction for pin PIOa_b. - * 0b0..Input - * 0b1..Output - */ -#define GPIO_DIR_DIRP31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP31_SHIFT)) & GPIO_DIR_DIRP31_MASK) -/*! @} */ - -/* The count of GPIO_DIR */ -#define GPIO_DIR_COUNT (4U) - -/*! @name MASK - Port mask */ -/*! @{ */ - -#define GPIO_MASK_MASKP0_MASK (0x1U) -#define GPIO_MASK_MASKP0_SHIFT (0U) -/*! MASKP0 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP0_SHIFT)) & GPIO_MASK_MASKP0_MASK) - -#define GPIO_MASK_MASKP1_MASK (0x2U) -#define GPIO_MASK_MASKP1_SHIFT (1U) -/*! MASKP1 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP1_SHIFT)) & GPIO_MASK_MASKP1_MASK) - -#define GPIO_MASK_MASKP2_MASK (0x4U) -#define GPIO_MASK_MASKP2_SHIFT (2U) -/*! MASKP2 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP2_SHIFT)) & GPIO_MASK_MASKP2_MASK) - -#define GPIO_MASK_MASKP3_MASK (0x8U) -#define GPIO_MASK_MASKP3_SHIFT (3U) -/*! MASKP3 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP3_SHIFT)) & GPIO_MASK_MASKP3_MASK) - -#define GPIO_MASK_MASKP4_MASK (0x10U) -#define GPIO_MASK_MASKP4_SHIFT (4U) -/*! MASKP4 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP4_SHIFT)) & GPIO_MASK_MASKP4_MASK) - -#define GPIO_MASK_MASKP5_MASK (0x20U) -#define GPIO_MASK_MASKP5_SHIFT (5U) -/*! MASKP5 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP5_SHIFT)) & GPIO_MASK_MASKP5_MASK) - -#define GPIO_MASK_MASKP6_MASK (0x40U) -#define GPIO_MASK_MASKP6_SHIFT (6U) -/*! MASKP6 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP6_SHIFT)) & GPIO_MASK_MASKP6_MASK) - -#define GPIO_MASK_MASKP7_MASK (0x80U) -#define GPIO_MASK_MASKP7_SHIFT (7U) -/*! MASKP7 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP7_SHIFT)) & GPIO_MASK_MASKP7_MASK) - -#define GPIO_MASK_MASKP8_MASK (0x100U) -#define GPIO_MASK_MASKP8_SHIFT (8U) -/*! MASKP8 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP8_SHIFT)) & GPIO_MASK_MASKP8_MASK) - -#define GPIO_MASK_MASKP9_MASK (0x200U) -#define GPIO_MASK_MASKP9_SHIFT (9U) -/*! MASKP9 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP9_SHIFT)) & GPIO_MASK_MASKP9_MASK) - -#define GPIO_MASK_MASKP10_MASK (0x400U) -#define GPIO_MASK_MASKP10_SHIFT (10U) -/*! MASKP10 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP10_SHIFT)) & GPIO_MASK_MASKP10_MASK) - -#define GPIO_MASK_MASKP11_MASK (0x800U) -#define GPIO_MASK_MASKP11_SHIFT (11U) -/*! MASKP11 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP11_SHIFT)) & GPIO_MASK_MASKP11_MASK) - -#define GPIO_MASK_MASKP12_MASK (0x1000U) -#define GPIO_MASK_MASKP12_SHIFT (12U) -/*! MASKP12 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP12_SHIFT)) & GPIO_MASK_MASKP12_MASK) - -#define GPIO_MASK_MASKP13_MASK (0x2000U) -#define GPIO_MASK_MASKP13_SHIFT (13U) -/*! MASKP13 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP13_SHIFT)) & GPIO_MASK_MASKP13_MASK) - -#define GPIO_MASK_MASKP14_MASK (0x4000U) -#define GPIO_MASK_MASKP14_SHIFT (14U) -/*! MASKP14 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP14_SHIFT)) & GPIO_MASK_MASKP14_MASK) - -#define GPIO_MASK_MASKP15_MASK (0x8000U) -#define GPIO_MASK_MASKP15_SHIFT (15U) -/*! MASKP15 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP15_SHIFT)) & GPIO_MASK_MASKP15_MASK) - -#define GPIO_MASK_MASKP16_MASK (0x10000U) -#define GPIO_MASK_MASKP16_SHIFT (16U) -/*! MASKP16 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP16_SHIFT)) & GPIO_MASK_MASKP16_MASK) - -#define GPIO_MASK_MASKP17_MASK (0x20000U) -#define GPIO_MASK_MASKP17_SHIFT (17U) -/*! MASKP17 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP17_SHIFT)) & GPIO_MASK_MASKP17_MASK) - -#define GPIO_MASK_MASKP18_MASK (0x40000U) -#define GPIO_MASK_MASKP18_SHIFT (18U) -/*! MASKP18 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP18_SHIFT)) & GPIO_MASK_MASKP18_MASK) - -#define GPIO_MASK_MASKP19_MASK (0x80000U) -#define GPIO_MASK_MASKP19_SHIFT (19U) -/*! MASKP19 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP19_SHIFT)) & GPIO_MASK_MASKP19_MASK) - -#define GPIO_MASK_MASKP20_MASK (0x100000U) -#define GPIO_MASK_MASKP20_SHIFT (20U) -/*! MASKP20 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP20_SHIFT)) & GPIO_MASK_MASKP20_MASK) - -#define GPIO_MASK_MASKP21_MASK (0x200000U) -#define GPIO_MASK_MASKP21_SHIFT (21U) -/*! MASKP21 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP21_SHIFT)) & GPIO_MASK_MASKP21_MASK) - -#define GPIO_MASK_MASKP22_MASK (0x400000U) -#define GPIO_MASK_MASKP22_SHIFT (22U) -/*! MASKP22 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP22_SHIFT)) & GPIO_MASK_MASKP22_MASK) - -#define GPIO_MASK_MASKP23_MASK (0x800000U) -#define GPIO_MASK_MASKP23_SHIFT (23U) -/*! MASKP23 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP23_SHIFT)) & GPIO_MASK_MASKP23_MASK) - -#define GPIO_MASK_MASKP24_MASK (0x1000000U) -#define GPIO_MASK_MASKP24_SHIFT (24U) -/*! MASKP24 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP24_SHIFT)) & GPIO_MASK_MASKP24_MASK) - -#define GPIO_MASK_MASKP25_MASK (0x2000000U) -#define GPIO_MASK_MASKP25_SHIFT (25U) -/*! MASKP25 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP25_SHIFT)) & GPIO_MASK_MASKP25_MASK) - -#define GPIO_MASK_MASKP26_MASK (0x4000000U) -#define GPIO_MASK_MASKP26_SHIFT (26U) -/*! MASKP26 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP26_SHIFT)) & GPIO_MASK_MASKP26_MASK) - -#define GPIO_MASK_MASKP27_MASK (0x8000000U) -#define GPIO_MASK_MASKP27_SHIFT (27U) -/*! MASKP27 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP27_SHIFT)) & GPIO_MASK_MASKP27_MASK) - -#define GPIO_MASK_MASKP28_MASK (0x10000000U) -#define GPIO_MASK_MASKP28_SHIFT (28U) -/*! MASKP28 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP28_SHIFT)) & GPIO_MASK_MASKP28_MASK) - -#define GPIO_MASK_MASKP29_MASK (0x20000000U) -#define GPIO_MASK_MASKP29_SHIFT (29U) -/*! MASKP29 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP29_SHIFT)) & GPIO_MASK_MASKP29_MASK) - -#define GPIO_MASK_MASKP30_MASK (0x40000000U) -#define GPIO_MASK_MASKP30_SHIFT (30U) -/*! MASKP30 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP30_SHIFT)) & GPIO_MASK_MASKP30_MASK) - -#define GPIO_MASK_MASKP31_MASK (0x80000000U) -#define GPIO_MASK_MASKP31_SHIFT (31U) -/*! MASKP31 - Port Mask - * 0b0..Read MPIN: pin state; write MPIN: load output bit - * 0b1..Read MPIN: 0; write MPIN: output bit not affected - */ -#define GPIO_MASK_MASKP31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP31_SHIFT)) & GPIO_MASK_MASKP31_MASK) -/*! @} */ - -/* The count of GPIO_MASK */ -#define GPIO_MASK_COUNT (4U) - -/*! @name PIN - Port pin */ -/*! @{ */ - -#define GPIO_PIN_PORT0_MASK (0x1U) -#define GPIO_PIN_PORT0_SHIFT (0U) -/*! PORT0 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT0_SHIFT)) & GPIO_PIN_PORT0_MASK) - -#define GPIO_PIN_PORT1_MASK (0x2U) -#define GPIO_PIN_PORT1_SHIFT (1U) -/*! PORT1 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT1_SHIFT)) & GPIO_PIN_PORT1_MASK) - -#define GPIO_PIN_PORT2_MASK (0x4U) -#define GPIO_PIN_PORT2_SHIFT (2U) -/*! PORT2 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT2_SHIFT)) & GPIO_PIN_PORT2_MASK) - -#define GPIO_PIN_PORT3_MASK (0x8U) -#define GPIO_PIN_PORT3_SHIFT (3U) -/*! PORT3 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT3_SHIFT)) & GPIO_PIN_PORT3_MASK) - -#define GPIO_PIN_PORT4_MASK (0x10U) -#define GPIO_PIN_PORT4_SHIFT (4U) -/*! PORT4 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT4_SHIFT)) & GPIO_PIN_PORT4_MASK) - -#define GPIO_PIN_PORT5_MASK (0x20U) -#define GPIO_PIN_PORT5_SHIFT (5U) -/*! PORT5 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT5_SHIFT)) & GPIO_PIN_PORT5_MASK) - -#define GPIO_PIN_PORT6_MASK (0x40U) -#define GPIO_PIN_PORT6_SHIFT (6U) -/*! PORT6 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT6_SHIFT)) & GPIO_PIN_PORT6_MASK) - -#define GPIO_PIN_PORT7_MASK (0x80U) -#define GPIO_PIN_PORT7_SHIFT (7U) -/*! PORT7 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT7_SHIFT)) & GPIO_PIN_PORT7_MASK) - -#define GPIO_PIN_PORT8_MASK (0x100U) -#define GPIO_PIN_PORT8_SHIFT (8U) -/*! PORT8 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT8_SHIFT)) & GPIO_PIN_PORT8_MASK) - -#define GPIO_PIN_PORT9_MASK (0x200U) -#define GPIO_PIN_PORT9_SHIFT (9U) -/*! PORT9 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT9_SHIFT)) & GPIO_PIN_PORT9_MASK) - -#define GPIO_PIN_PORT10_MASK (0x400U) -#define GPIO_PIN_PORT10_SHIFT (10U) -/*! PORT10 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT10_SHIFT)) & GPIO_PIN_PORT10_MASK) - -#define GPIO_PIN_PORT11_MASK (0x800U) -#define GPIO_PIN_PORT11_SHIFT (11U) -/*! PORT11 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT11_SHIFT)) & GPIO_PIN_PORT11_MASK) - -#define GPIO_PIN_PORT12_MASK (0x1000U) -#define GPIO_PIN_PORT12_SHIFT (12U) -/*! PORT12 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT12_SHIFT)) & GPIO_PIN_PORT12_MASK) - -#define GPIO_PIN_PORT13_MASK (0x2000U) -#define GPIO_PIN_PORT13_SHIFT (13U) -/*! PORT13 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT13_SHIFT)) & GPIO_PIN_PORT13_MASK) - -#define GPIO_PIN_PORT14_MASK (0x4000U) -#define GPIO_PIN_PORT14_SHIFT (14U) -/*! PORT14 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT14_SHIFT)) & GPIO_PIN_PORT14_MASK) - -#define GPIO_PIN_PORT15_MASK (0x8000U) -#define GPIO_PIN_PORT15_SHIFT (15U) -/*! PORT15 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT15_SHIFT)) & GPIO_PIN_PORT15_MASK) - -#define GPIO_PIN_PORT16_MASK (0x10000U) -#define GPIO_PIN_PORT16_SHIFT (16U) -/*! PORT16 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT16_SHIFT)) & GPIO_PIN_PORT16_MASK) - -#define GPIO_PIN_PORT17_MASK (0x20000U) -#define GPIO_PIN_PORT17_SHIFT (17U) -/*! PORT17 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT17_SHIFT)) & GPIO_PIN_PORT17_MASK) - -#define GPIO_PIN_PORT18_MASK (0x40000U) -#define GPIO_PIN_PORT18_SHIFT (18U) -/*! PORT18 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT18_SHIFT)) & GPIO_PIN_PORT18_MASK) - -#define GPIO_PIN_PORT19_MASK (0x80000U) -#define GPIO_PIN_PORT19_SHIFT (19U) -/*! PORT19 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT19_SHIFT)) & GPIO_PIN_PORT19_MASK) - -#define GPIO_PIN_PORT20_MASK (0x100000U) -#define GPIO_PIN_PORT20_SHIFT (20U) -/*! PORT20 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT20_SHIFT)) & GPIO_PIN_PORT20_MASK) - -#define GPIO_PIN_PORT21_MASK (0x200000U) -#define GPIO_PIN_PORT21_SHIFT (21U) -/*! PORT21 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT21_SHIFT)) & GPIO_PIN_PORT21_MASK) - -#define GPIO_PIN_PORT22_MASK (0x400000U) -#define GPIO_PIN_PORT22_SHIFT (22U) -/*! PORT22 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT22_SHIFT)) & GPIO_PIN_PORT22_MASK) - -#define GPIO_PIN_PORT23_MASK (0x800000U) -#define GPIO_PIN_PORT23_SHIFT (23U) -/*! PORT23 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT23_SHIFT)) & GPIO_PIN_PORT23_MASK) - -#define GPIO_PIN_PORT24_MASK (0x1000000U) -#define GPIO_PIN_PORT24_SHIFT (24U) -/*! PORT24 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT24_SHIFT)) & GPIO_PIN_PORT24_MASK) - -#define GPIO_PIN_PORT25_MASK (0x2000000U) -#define GPIO_PIN_PORT25_SHIFT (25U) -/*! PORT25 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT25_SHIFT)) & GPIO_PIN_PORT25_MASK) - -#define GPIO_PIN_PORT26_MASK (0x4000000U) -#define GPIO_PIN_PORT26_SHIFT (26U) -/*! PORT26 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT26_SHIFT)) & GPIO_PIN_PORT26_MASK) - -#define GPIO_PIN_PORT27_MASK (0x8000000U) -#define GPIO_PIN_PORT27_SHIFT (27U) -/*! PORT27 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT27_SHIFT)) & GPIO_PIN_PORT27_MASK) - -#define GPIO_PIN_PORT28_MASK (0x10000000U) -#define GPIO_PIN_PORT28_SHIFT (28U) -/*! PORT28 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT28_SHIFT)) & GPIO_PIN_PORT28_MASK) - -#define GPIO_PIN_PORT29_MASK (0x20000000U) -#define GPIO_PIN_PORT29_SHIFT (29U) -/*! PORT29 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT29_SHIFT)) & GPIO_PIN_PORT29_MASK) - -#define GPIO_PIN_PORT30_MASK (0x40000000U) -#define GPIO_PIN_PORT30_SHIFT (30U) -/*! PORT30 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT30_SHIFT)) & GPIO_PIN_PORT30_MASK) - -#define GPIO_PIN_PORT31_MASK (0x80000000U) -#define GPIO_PIN_PORT31_SHIFT (31U) -/*! PORT31 - Port pins - * 0b0..Read- pin is low; Write- clear output bit - * 0b1..Read- pin is high; Write- set output bit - */ -#define GPIO_PIN_PORT31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT31_SHIFT)) & GPIO_PIN_PORT31_MASK) -/*! @} */ - -/* The count of GPIO_PIN */ -#define GPIO_PIN_COUNT (4U) - -/*! @name MPIN - Masked Port Pin */ -/*! @{ */ - -#define GPIO_MPIN_MPORTP0_MASK (0x1U) -#define GPIO_MPIN_MPORTP0_SHIFT (0U) -/*! MPORTP0 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP0_SHIFT)) & GPIO_MPIN_MPORTP0_MASK) - -#define GPIO_MPIN_MPORTP1_MASK (0x2U) -#define GPIO_MPIN_MPORTP1_SHIFT (1U) -/*! MPORTP1 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP1_SHIFT)) & GPIO_MPIN_MPORTP1_MASK) - -#define GPIO_MPIN_MPORTP2_MASK (0x4U) -#define GPIO_MPIN_MPORTP2_SHIFT (2U) -/*! MPORTP2 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP2_SHIFT)) & GPIO_MPIN_MPORTP2_MASK) - -#define GPIO_MPIN_MPORTP3_MASK (0x8U) -#define GPIO_MPIN_MPORTP3_SHIFT (3U) -/*! MPORTP3 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP3_SHIFT)) & GPIO_MPIN_MPORTP3_MASK) - -#define GPIO_MPIN_MPORTP4_MASK (0x10U) -#define GPIO_MPIN_MPORTP4_SHIFT (4U) -/*! MPORTP4 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP4_SHIFT)) & GPIO_MPIN_MPORTP4_MASK) - -#define GPIO_MPIN_MPORTP5_MASK (0x20U) -#define GPIO_MPIN_MPORTP5_SHIFT (5U) -/*! MPORTP5 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP5_SHIFT)) & GPIO_MPIN_MPORTP5_MASK) - -#define GPIO_MPIN_MPORTP6_MASK (0x40U) -#define GPIO_MPIN_MPORTP6_SHIFT (6U) -/*! MPORTP6 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP6_SHIFT)) & GPIO_MPIN_MPORTP6_MASK) - -#define GPIO_MPIN_MPORTP7_MASK (0x80U) -#define GPIO_MPIN_MPORTP7_SHIFT (7U) -/*! MPORTP7 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP7_SHIFT)) & GPIO_MPIN_MPORTP7_MASK) - -#define GPIO_MPIN_MPORTP8_MASK (0x100U) -#define GPIO_MPIN_MPORTP8_SHIFT (8U) -/*! MPORTP8 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP8_SHIFT)) & GPIO_MPIN_MPORTP8_MASK) - -#define GPIO_MPIN_MPORTP9_MASK (0x200U) -#define GPIO_MPIN_MPORTP9_SHIFT (9U) -/*! MPORTP9 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP9_SHIFT)) & GPIO_MPIN_MPORTP9_MASK) - -#define GPIO_MPIN_MPORTP10_MASK (0x400U) -#define GPIO_MPIN_MPORTP10_SHIFT (10U) -/*! MPORTP10 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP10_SHIFT)) & GPIO_MPIN_MPORTP10_MASK) - -#define GPIO_MPIN_MPORTP11_MASK (0x800U) -#define GPIO_MPIN_MPORTP11_SHIFT (11U) -/*! MPORTP11 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP11_SHIFT)) & GPIO_MPIN_MPORTP11_MASK) - -#define GPIO_MPIN_MPORTP12_MASK (0x1000U) -#define GPIO_MPIN_MPORTP12_SHIFT (12U) -/*! MPORTP12 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP12_SHIFT)) & GPIO_MPIN_MPORTP12_MASK) - -#define GPIO_MPIN_MPORTP13_MASK (0x2000U) -#define GPIO_MPIN_MPORTP13_SHIFT (13U) -/*! MPORTP13 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP13_SHIFT)) & GPIO_MPIN_MPORTP13_MASK) - -#define GPIO_MPIN_MPORTP14_MASK (0x4000U) -#define GPIO_MPIN_MPORTP14_SHIFT (14U) -/*! MPORTP14 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP14_SHIFT)) & GPIO_MPIN_MPORTP14_MASK) - -#define GPIO_MPIN_MPORTP15_MASK (0x8000U) -#define GPIO_MPIN_MPORTP15_SHIFT (15U) -/*! MPORTP15 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP15_SHIFT)) & GPIO_MPIN_MPORTP15_MASK) - -#define GPIO_MPIN_MPORTP16_MASK (0x10000U) -#define GPIO_MPIN_MPORTP16_SHIFT (16U) -/*! MPORTP16 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP16_SHIFT)) & GPIO_MPIN_MPORTP16_MASK) - -#define GPIO_MPIN_MPORTP17_MASK (0x20000U) -#define GPIO_MPIN_MPORTP17_SHIFT (17U) -/*! MPORTP17 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP17_SHIFT)) & GPIO_MPIN_MPORTP17_MASK) - -#define GPIO_MPIN_MPORTP18_MASK (0x40000U) -#define GPIO_MPIN_MPORTP18_SHIFT (18U) -/*! MPORTP18 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP18_SHIFT)) & GPIO_MPIN_MPORTP18_MASK) - -#define GPIO_MPIN_MPORTP19_MASK (0x80000U) -#define GPIO_MPIN_MPORTP19_SHIFT (19U) -/*! MPORTP19 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP19_SHIFT)) & GPIO_MPIN_MPORTP19_MASK) - -#define GPIO_MPIN_MPORTP20_MASK (0x100000U) -#define GPIO_MPIN_MPORTP20_SHIFT (20U) -/*! MPORTP20 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP20_SHIFT)) & GPIO_MPIN_MPORTP20_MASK) - -#define GPIO_MPIN_MPORTP21_MASK (0x200000U) -#define GPIO_MPIN_MPORTP21_SHIFT (21U) -/*! MPORTP21 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP21_SHIFT)) & GPIO_MPIN_MPORTP21_MASK) - -#define GPIO_MPIN_MPORTP22_MASK (0x400000U) -#define GPIO_MPIN_MPORTP22_SHIFT (22U) -/*! MPORTP22 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP22_SHIFT)) & GPIO_MPIN_MPORTP22_MASK) - -#define GPIO_MPIN_MPORTP23_MASK (0x800000U) -#define GPIO_MPIN_MPORTP23_SHIFT (23U) -/*! MPORTP23 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP23_SHIFT)) & GPIO_MPIN_MPORTP23_MASK) - -#define GPIO_MPIN_MPORTP24_MASK (0x1000000U) -#define GPIO_MPIN_MPORTP24_SHIFT (24U) -/*! MPORTP24 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP24_SHIFT)) & GPIO_MPIN_MPORTP24_MASK) - -#define GPIO_MPIN_MPORTP25_MASK (0x2000000U) -#define GPIO_MPIN_MPORTP25_SHIFT (25U) -/*! MPORTP25 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP25_SHIFT)) & GPIO_MPIN_MPORTP25_MASK) - -#define GPIO_MPIN_MPORTP26_MASK (0x4000000U) -#define GPIO_MPIN_MPORTP26_SHIFT (26U) -/*! MPORTP26 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP26_SHIFT)) & GPIO_MPIN_MPORTP26_MASK) - -#define GPIO_MPIN_MPORTP27_MASK (0x8000000U) -#define GPIO_MPIN_MPORTP27_SHIFT (27U) -/*! MPORTP27 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP27_SHIFT)) & GPIO_MPIN_MPORTP27_MASK) - -#define GPIO_MPIN_MPORTP28_MASK (0x10000000U) -#define GPIO_MPIN_MPORTP28_SHIFT (28U) -/*! MPORTP28 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP28_SHIFT)) & GPIO_MPIN_MPORTP28_MASK) - -#define GPIO_MPIN_MPORTP29_MASK (0x20000000U) -#define GPIO_MPIN_MPORTP29_SHIFT (29U) -/*! MPORTP29 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP29_SHIFT)) & GPIO_MPIN_MPORTP29_MASK) - -#define GPIO_MPIN_MPORTP30_MASK (0x40000000U) -#define GPIO_MPIN_MPORTP30_SHIFT (30U) -/*! MPORTP30 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP30_SHIFT)) & GPIO_MPIN_MPORTP30_MASK) - -#define GPIO_MPIN_MPORTP31_MASK (0x80000000U) -#define GPIO_MPIN_MPORTP31_SHIFT (31U) -/*! MPORTP31 - Mask bits for port pins - * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the - * corresponding bit in the MASK register is 0 - * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the - * corresponding bit in the MASK register is 0 - */ -#define GPIO_MPIN_MPORTP31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP31_SHIFT)) & GPIO_MPIN_MPORTP31_MASK) -/*! @} */ - -/* The count of GPIO_MPIN */ -#define GPIO_MPIN_COUNT (4U) - -/*! @name SET - Port set */ -/*! @{ */ - -#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) -#define GPIO_SET_SETP_SHIFT (0U) -/*! SETP - Read or set output bits - * 0b00000000000000000000000000000000..Read- output bit; write- no operation - * 0b00000000000000000000000000000001..Read- output bit; write- set output bit - */ -#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) -/*! @} */ - -/* The count of GPIO_SET */ -#define GPIO_SET_COUNT (4U) - -/*! @name CLR - Port clear */ -/*! @{ */ - -#define GPIO_CLR_CLRP0_MASK (0x1U) -#define GPIO_CLR_CLRP0_SHIFT (0U) -/*! CLRP0 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP0_SHIFT)) & GPIO_CLR_CLRP0_MASK) - -#define GPIO_CLR_CLRP1_MASK (0x2U) -#define GPIO_CLR_CLRP1_SHIFT (1U) -/*! CLRP1 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP1_SHIFT)) & GPIO_CLR_CLRP1_MASK) - -#define GPIO_CLR_CLRP2_MASK (0x4U) -#define GPIO_CLR_CLRP2_SHIFT (2U) -/*! CLRP2 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP2_SHIFT)) & GPIO_CLR_CLRP2_MASK) - -#define GPIO_CLR_CLRP3_MASK (0x8U) -#define GPIO_CLR_CLRP3_SHIFT (3U) -/*! CLRP3 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP3_SHIFT)) & GPIO_CLR_CLRP3_MASK) - -#define GPIO_CLR_CLRP4_MASK (0x10U) -#define GPIO_CLR_CLRP4_SHIFT (4U) -/*! CLRP4 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP4_SHIFT)) & GPIO_CLR_CLRP4_MASK) - -#define GPIO_CLR_CLRP5_MASK (0x20U) -#define GPIO_CLR_CLRP5_SHIFT (5U) -/*! CLRP5 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP5_SHIFT)) & GPIO_CLR_CLRP5_MASK) - -#define GPIO_CLR_CLRP6_MASK (0x40U) -#define GPIO_CLR_CLRP6_SHIFT (6U) -/*! CLRP6 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP6_SHIFT)) & GPIO_CLR_CLRP6_MASK) - -#define GPIO_CLR_CLRP7_MASK (0x80U) -#define GPIO_CLR_CLRP7_SHIFT (7U) -/*! CLRP7 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP7_SHIFT)) & GPIO_CLR_CLRP7_MASK) - -#define GPIO_CLR_CLRP8_MASK (0x100U) -#define GPIO_CLR_CLRP8_SHIFT (8U) -/*! CLRP8 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP8_SHIFT)) & GPIO_CLR_CLRP8_MASK) - -#define GPIO_CLR_CLRP9_MASK (0x200U) -#define GPIO_CLR_CLRP9_SHIFT (9U) -/*! CLRP9 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP9_SHIFT)) & GPIO_CLR_CLRP9_MASK) - -#define GPIO_CLR_CLRP10_MASK (0x400U) -#define GPIO_CLR_CLRP10_SHIFT (10U) -/*! CLRP10 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP10_SHIFT)) & GPIO_CLR_CLRP10_MASK) - -#define GPIO_CLR_CLRP11_MASK (0x800U) -#define GPIO_CLR_CLRP11_SHIFT (11U) -/*! CLRP11 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP11_SHIFT)) & GPIO_CLR_CLRP11_MASK) - -#define GPIO_CLR_CLRP12_MASK (0x1000U) -#define GPIO_CLR_CLRP12_SHIFT (12U) -/*! CLRP12 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP12_SHIFT)) & GPIO_CLR_CLRP12_MASK) - -#define GPIO_CLR_CLRP13_MASK (0x2000U) -#define GPIO_CLR_CLRP13_SHIFT (13U) -/*! CLRP13 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP13_SHIFT)) & GPIO_CLR_CLRP13_MASK) - -#define GPIO_CLR_CLRP14_MASK (0x4000U) -#define GPIO_CLR_CLRP14_SHIFT (14U) -/*! CLRP14 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP14_SHIFT)) & GPIO_CLR_CLRP14_MASK) - -#define GPIO_CLR_CLRP15_MASK (0x8000U) -#define GPIO_CLR_CLRP15_SHIFT (15U) -/*! CLRP15 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP15_SHIFT)) & GPIO_CLR_CLRP15_MASK) - -#define GPIO_CLR_CLRP16_MASK (0x10000U) -#define GPIO_CLR_CLRP16_SHIFT (16U) -/*! CLRP16 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP16_SHIFT)) & GPIO_CLR_CLRP16_MASK) - -#define GPIO_CLR_CLRP17_MASK (0x20000U) -#define GPIO_CLR_CLRP17_SHIFT (17U) -/*! CLRP17 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP17_SHIFT)) & GPIO_CLR_CLRP17_MASK) - -#define GPIO_CLR_CLRP18_MASK (0x40000U) -#define GPIO_CLR_CLRP18_SHIFT (18U) -/*! CLRP18 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP18_SHIFT)) & GPIO_CLR_CLRP18_MASK) - -#define GPIO_CLR_CLRP19_MASK (0x80000U) -#define GPIO_CLR_CLRP19_SHIFT (19U) -/*! CLRP19 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP19_SHIFT)) & GPIO_CLR_CLRP19_MASK) - -#define GPIO_CLR_CLRP20_MASK (0x100000U) -#define GPIO_CLR_CLRP20_SHIFT (20U) -/*! CLRP20 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP20_SHIFT)) & GPIO_CLR_CLRP20_MASK) - -#define GPIO_CLR_CLRP21_MASK (0x200000U) -#define GPIO_CLR_CLRP21_SHIFT (21U) -/*! CLRP21 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP21_SHIFT)) & GPIO_CLR_CLRP21_MASK) - -#define GPIO_CLR_CLRP22_MASK (0x400000U) -#define GPIO_CLR_CLRP22_SHIFT (22U) -/*! CLRP22 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP22_SHIFT)) & GPIO_CLR_CLRP22_MASK) - -#define GPIO_CLR_CLRP23_MASK (0x800000U) -#define GPIO_CLR_CLRP23_SHIFT (23U) -/*! CLRP23 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP23_SHIFT)) & GPIO_CLR_CLRP23_MASK) - -#define GPIO_CLR_CLRP24_MASK (0x1000000U) -#define GPIO_CLR_CLRP24_SHIFT (24U) -/*! CLRP24 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP24_SHIFT)) & GPIO_CLR_CLRP24_MASK) - -#define GPIO_CLR_CLRP25_MASK (0x2000000U) -#define GPIO_CLR_CLRP25_SHIFT (25U) -/*! CLRP25 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP25_SHIFT)) & GPIO_CLR_CLRP25_MASK) - -#define GPIO_CLR_CLRP26_MASK (0x4000000U) -#define GPIO_CLR_CLRP26_SHIFT (26U) -/*! CLRP26 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP26_SHIFT)) & GPIO_CLR_CLRP26_MASK) - -#define GPIO_CLR_CLRP27_MASK (0x8000000U) -#define GPIO_CLR_CLRP27_SHIFT (27U) -/*! CLRP27 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP27_SHIFT)) & GPIO_CLR_CLRP27_MASK) - -#define GPIO_CLR_CLRP28_MASK (0x10000000U) -#define GPIO_CLR_CLRP28_SHIFT (28U) -/*! CLRP28 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP28_SHIFT)) & GPIO_CLR_CLRP28_MASK) - -#define GPIO_CLR_CLRP29_MASK (0x20000000U) -#define GPIO_CLR_CLRP29_SHIFT (29U) -/*! CLRP29 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP29_SHIFT)) & GPIO_CLR_CLRP29_MASK) - -#define GPIO_CLR_CLRP30_MASK (0x40000000U) -#define GPIO_CLR_CLRP30_SHIFT (30U) -/*! CLRP30 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP30_SHIFT)) & GPIO_CLR_CLRP30_MASK) - -#define GPIO_CLR_CLRP31_MASK (0x80000000U) -#define GPIO_CLR_CLRP31_SHIFT (31U) -/*! CLRP31 - Clear output bits - * 0b0..No operation - * 0b1..Clears output bit - */ -#define GPIO_CLR_CLRP31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP31_SHIFT)) & GPIO_CLR_CLRP31_MASK) -/*! @} */ - -/* The count of GPIO_CLR */ -#define GPIO_CLR_COUNT (4U) - -/*! @name NOT - Port toggle */ -/*! @{ */ - -#define GPIO_NOT_NOTP0_MASK (0x1U) -#define GPIO_NOT_NOTP0_SHIFT (0U) -/*! NOTP0 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP0_SHIFT)) & GPIO_NOT_NOTP0_MASK) - -#define GPIO_NOT_NOTP1_MASK (0x2U) -#define GPIO_NOT_NOTP1_SHIFT (1U) -/*! NOTP1 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP1_SHIFT)) & GPIO_NOT_NOTP1_MASK) - -#define GPIO_NOT_NOTP2_MASK (0x4U) -#define GPIO_NOT_NOTP2_SHIFT (2U) -/*! NOTP2 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP2_SHIFT)) & GPIO_NOT_NOTP2_MASK) - -#define GPIO_NOT_NOTP3_MASK (0x8U) -#define GPIO_NOT_NOTP3_SHIFT (3U) -/*! NOTP3 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP3_SHIFT)) & GPIO_NOT_NOTP3_MASK) - -#define GPIO_NOT_NOTP4_MASK (0x10U) -#define GPIO_NOT_NOTP4_SHIFT (4U) -/*! NOTP4 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP4_SHIFT)) & GPIO_NOT_NOTP4_MASK) - -#define GPIO_NOT_NOTP5_MASK (0x20U) -#define GPIO_NOT_NOTP5_SHIFT (5U) -/*! NOTP5 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP5_SHIFT)) & GPIO_NOT_NOTP5_MASK) - -#define GPIO_NOT_NOTP6_MASK (0x40U) -#define GPIO_NOT_NOTP6_SHIFT (6U) -/*! NOTP6 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP6_SHIFT)) & GPIO_NOT_NOTP6_MASK) - -#define GPIO_NOT_NOTP7_MASK (0x80U) -#define GPIO_NOT_NOTP7_SHIFT (7U) -/*! NOTP7 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP7_SHIFT)) & GPIO_NOT_NOTP7_MASK) - -#define GPIO_NOT_NOTP8_MASK (0x100U) -#define GPIO_NOT_NOTP8_SHIFT (8U) -/*! NOTP8 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP8_SHIFT)) & GPIO_NOT_NOTP8_MASK) - -#define GPIO_NOT_NOTP9_MASK (0x200U) -#define GPIO_NOT_NOTP9_SHIFT (9U) -/*! NOTP9 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP9_SHIFT)) & GPIO_NOT_NOTP9_MASK) - -#define GPIO_NOT_NOTP10_MASK (0x400U) -#define GPIO_NOT_NOTP10_SHIFT (10U) -/*! NOTP10 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP10_SHIFT)) & GPIO_NOT_NOTP10_MASK) - -#define GPIO_NOT_NOTP11_MASK (0x800U) -#define GPIO_NOT_NOTP11_SHIFT (11U) -/*! NOTP11 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP11_SHIFT)) & GPIO_NOT_NOTP11_MASK) - -#define GPIO_NOT_NOTP12_MASK (0x1000U) -#define GPIO_NOT_NOTP12_SHIFT (12U) -/*! NOTP12 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP12_SHIFT)) & GPIO_NOT_NOTP12_MASK) - -#define GPIO_NOT_NOTP13_MASK (0x2000U) -#define GPIO_NOT_NOTP13_SHIFT (13U) -/*! NOTP13 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP13_SHIFT)) & GPIO_NOT_NOTP13_MASK) - -#define GPIO_NOT_NOTP14_MASK (0x4000U) -#define GPIO_NOT_NOTP14_SHIFT (14U) -/*! NOTP14 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP14_SHIFT)) & GPIO_NOT_NOTP14_MASK) - -#define GPIO_NOT_NOTP15_MASK (0x8000U) -#define GPIO_NOT_NOTP15_SHIFT (15U) -/*! NOTP15 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP15_SHIFT)) & GPIO_NOT_NOTP15_MASK) - -#define GPIO_NOT_NOTP16_MASK (0x10000U) -#define GPIO_NOT_NOTP16_SHIFT (16U) -/*! NOTP16 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP16_SHIFT)) & GPIO_NOT_NOTP16_MASK) - -#define GPIO_NOT_NOTP17_MASK (0x20000U) -#define GPIO_NOT_NOTP17_SHIFT (17U) -/*! NOTP17 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP17_SHIFT)) & GPIO_NOT_NOTP17_MASK) - -#define GPIO_NOT_NOTP18_MASK (0x40000U) -#define GPIO_NOT_NOTP18_SHIFT (18U) -/*! NOTP18 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP18_SHIFT)) & GPIO_NOT_NOTP18_MASK) - -#define GPIO_NOT_NOTP19_MASK (0x80000U) -#define GPIO_NOT_NOTP19_SHIFT (19U) -/*! NOTP19 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP19_SHIFT)) & GPIO_NOT_NOTP19_MASK) - -#define GPIO_NOT_NOTP20_MASK (0x100000U) -#define GPIO_NOT_NOTP20_SHIFT (20U) -/*! NOTP20 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP20_SHIFT)) & GPIO_NOT_NOTP20_MASK) - -#define GPIO_NOT_NOTP21_MASK (0x200000U) -#define GPIO_NOT_NOTP21_SHIFT (21U) -/*! NOTP21 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP21_SHIFT)) & GPIO_NOT_NOTP21_MASK) - -#define GPIO_NOT_NOTP22_MASK (0x400000U) -#define GPIO_NOT_NOTP22_SHIFT (22U) -/*! NOTP22 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP22_SHIFT)) & GPIO_NOT_NOTP22_MASK) - -#define GPIO_NOT_NOTP23_MASK (0x800000U) -#define GPIO_NOT_NOTP23_SHIFT (23U) -/*! NOTP23 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP23_SHIFT)) & GPIO_NOT_NOTP23_MASK) - -#define GPIO_NOT_NOTP24_MASK (0x1000000U) -#define GPIO_NOT_NOTP24_SHIFT (24U) -/*! NOTP24 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP24_SHIFT)) & GPIO_NOT_NOTP24_MASK) - -#define GPIO_NOT_NOTP25_MASK (0x2000000U) -#define GPIO_NOT_NOTP25_SHIFT (25U) -/*! NOTP25 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP25_SHIFT)) & GPIO_NOT_NOTP25_MASK) - -#define GPIO_NOT_NOTP26_MASK (0x4000000U) -#define GPIO_NOT_NOTP26_SHIFT (26U) -/*! NOTP26 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP26_SHIFT)) & GPIO_NOT_NOTP26_MASK) - -#define GPIO_NOT_NOTP27_MASK (0x8000000U) -#define GPIO_NOT_NOTP27_SHIFT (27U) -/*! NOTP27 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP27_SHIFT)) & GPIO_NOT_NOTP27_MASK) - -#define GPIO_NOT_NOTP28_MASK (0x10000000U) -#define GPIO_NOT_NOTP28_SHIFT (28U) -/*! NOTP28 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP28_SHIFT)) & GPIO_NOT_NOTP28_MASK) - -#define GPIO_NOT_NOTP29_MASK (0x20000000U) -#define GPIO_NOT_NOTP29_SHIFT (29U) -/*! NOTP29 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP29_SHIFT)) & GPIO_NOT_NOTP29_MASK) - -#define GPIO_NOT_NOTP30_MASK (0x40000000U) -#define GPIO_NOT_NOTP30_SHIFT (30U) -/*! NOTP30 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP30_SHIFT)) & GPIO_NOT_NOTP30_MASK) - -#define GPIO_NOT_NOTP31_MASK (0x80000000U) -#define GPIO_NOT_NOTP31_SHIFT (31U) -/*! NOTP31 - Toggle output bits - * 0b0..No operation - * 0b1..Toggle output bit - */ -#define GPIO_NOT_NOTP31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP31_SHIFT)) & GPIO_NOT_NOTP31_MASK) -/*! @} */ - -/* The count of GPIO_NOT */ -#define GPIO_NOT_COUNT (4U) - -/*! @name DIRSET - Port direction set */ -/*! @{ */ - -#define GPIO_DIRSET_DIRSETP0_MASK (0x1U) -#define GPIO_DIRSET_DIRSETP0_SHIFT (0U) -/*! DIRSETP0 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP0_SHIFT)) & GPIO_DIRSET_DIRSETP0_MASK) - -#define GPIO_DIRSET_DIRSETP1_MASK (0x2U) -#define GPIO_DIRSET_DIRSETP1_SHIFT (1U) -/*! DIRSETP1 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP1_SHIFT)) & GPIO_DIRSET_DIRSETP1_MASK) - -#define GPIO_DIRSET_DIRSETP2_MASK (0x4U) -#define GPIO_DIRSET_DIRSETP2_SHIFT (2U) -/*! DIRSETP2 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP2_SHIFT)) & GPIO_DIRSET_DIRSETP2_MASK) - -#define GPIO_DIRSET_DIRSETP3_MASK (0x8U) -#define GPIO_DIRSET_DIRSETP3_SHIFT (3U) -/*! DIRSETP3 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP3_SHIFT)) & GPIO_DIRSET_DIRSETP3_MASK) - -#define GPIO_DIRSET_DIRSETP4_MASK (0x10U) -#define GPIO_DIRSET_DIRSETP4_SHIFT (4U) -/*! DIRSETP4 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP4_SHIFT)) & GPIO_DIRSET_DIRSETP4_MASK) - -#define GPIO_DIRSET_DIRSETP5_MASK (0x20U) -#define GPIO_DIRSET_DIRSETP5_SHIFT (5U) -/*! DIRSETP5 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP5_SHIFT)) & GPIO_DIRSET_DIRSETP5_MASK) - -#define GPIO_DIRSET_DIRSETP6_MASK (0x40U) -#define GPIO_DIRSET_DIRSETP6_SHIFT (6U) -/*! DIRSETP6 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP6_SHIFT)) & GPIO_DIRSET_DIRSETP6_MASK) - -#define GPIO_DIRSET_DIRSETP7_MASK (0x80U) -#define GPIO_DIRSET_DIRSETP7_SHIFT (7U) -/*! DIRSETP7 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP7_SHIFT)) & GPIO_DIRSET_DIRSETP7_MASK) - -#define GPIO_DIRSET_DIRSETP8_MASK (0x100U) -#define GPIO_DIRSET_DIRSETP8_SHIFT (8U) -/*! DIRSETP8 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP8_SHIFT)) & GPIO_DIRSET_DIRSETP8_MASK) - -#define GPIO_DIRSET_DIRSETP9_MASK (0x200U) -#define GPIO_DIRSET_DIRSETP9_SHIFT (9U) -/*! DIRSETP9 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP9_SHIFT)) & GPIO_DIRSET_DIRSETP9_MASK) - -#define GPIO_DIRSET_DIRSETP10_MASK (0x400U) -#define GPIO_DIRSET_DIRSETP10_SHIFT (10U) -/*! DIRSETP10 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP10_SHIFT)) & GPIO_DIRSET_DIRSETP10_MASK) - -#define GPIO_DIRSET_DIRSETP11_MASK (0x800U) -#define GPIO_DIRSET_DIRSETP11_SHIFT (11U) -/*! DIRSETP11 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP11_SHIFT)) & GPIO_DIRSET_DIRSETP11_MASK) - -#define GPIO_DIRSET_DIRSETP12_MASK (0x1000U) -#define GPIO_DIRSET_DIRSETP12_SHIFT (12U) -/*! DIRSETP12 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP12_SHIFT)) & GPIO_DIRSET_DIRSETP12_MASK) - -#define GPIO_DIRSET_DIRSETP13_MASK (0x2000U) -#define GPIO_DIRSET_DIRSETP13_SHIFT (13U) -/*! DIRSETP13 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP13_SHIFT)) & GPIO_DIRSET_DIRSETP13_MASK) - -#define GPIO_DIRSET_DIRSETP14_MASK (0x4000U) -#define GPIO_DIRSET_DIRSETP14_SHIFT (14U) -/*! DIRSETP14 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP14_SHIFT)) & GPIO_DIRSET_DIRSETP14_MASK) - -#define GPIO_DIRSET_DIRSETP15_MASK (0x8000U) -#define GPIO_DIRSET_DIRSETP15_SHIFT (15U) -/*! DIRSETP15 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP15_SHIFT)) & GPIO_DIRSET_DIRSETP15_MASK) - -#define GPIO_DIRSET_DIRSETP16_MASK (0x10000U) -#define GPIO_DIRSET_DIRSETP16_SHIFT (16U) -/*! DIRSETP16 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP16_SHIFT)) & GPIO_DIRSET_DIRSETP16_MASK) - -#define GPIO_DIRSET_DIRSETP17_MASK (0x20000U) -#define GPIO_DIRSET_DIRSETP17_SHIFT (17U) -/*! DIRSETP17 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP17_SHIFT)) & GPIO_DIRSET_DIRSETP17_MASK) - -#define GPIO_DIRSET_DIRSETP18_MASK (0x40000U) -#define GPIO_DIRSET_DIRSETP18_SHIFT (18U) -/*! DIRSETP18 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP18_SHIFT)) & GPIO_DIRSET_DIRSETP18_MASK) - -#define GPIO_DIRSET_DIRSETP19_MASK (0x80000U) -#define GPIO_DIRSET_DIRSETP19_SHIFT (19U) -/*! DIRSETP19 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP19_SHIFT)) & GPIO_DIRSET_DIRSETP19_MASK) - -#define GPIO_DIRSET_DIRSETP20_MASK (0x100000U) -#define GPIO_DIRSET_DIRSETP20_SHIFT (20U) -/*! DIRSETP20 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP20_SHIFT)) & GPIO_DIRSET_DIRSETP20_MASK) - -#define GPIO_DIRSET_DIRSETP21_MASK (0x200000U) -#define GPIO_DIRSET_DIRSETP21_SHIFT (21U) -/*! DIRSETP21 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP21_SHIFT)) & GPIO_DIRSET_DIRSETP21_MASK) - -#define GPIO_DIRSET_DIRSETP22_MASK (0x400000U) -#define GPIO_DIRSET_DIRSETP22_SHIFT (22U) -/*! DIRSETP22 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP22_SHIFT)) & GPIO_DIRSET_DIRSETP22_MASK) - -#define GPIO_DIRSET_DIRSETP23_MASK (0x800000U) -#define GPIO_DIRSET_DIRSETP23_SHIFT (23U) -/*! DIRSETP23 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP23_SHIFT)) & GPIO_DIRSET_DIRSETP23_MASK) - -#define GPIO_DIRSET_DIRSETP24_MASK (0x1000000U) -#define GPIO_DIRSET_DIRSETP24_SHIFT (24U) -/*! DIRSETP24 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP24_SHIFT)) & GPIO_DIRSET_DIRSETP24_MASK) - -#define GPIO_DIRSET_DIRSETP25_MASK (0x2000000U) -#define GPIO_DIRSET_DIRSETP25_SHIFT (25U) -/*! DIRSETP25 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP25_SHIFT)) & GPIO_DIRSET_DIRSETP25_MASK) - -#define GPIO_DIRSET_DIRSETP26_MASK (0x4000000U) -#define GPIO_DIRSET_DIRSETP26_SHIFT (26U) -/*! DIRSETP26 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP26_SHIFT)) & GPIO_DIRSET_DIRSETP26_MASK) - -#define GPIO_DIRSET_DIRSETP27_MASK (0x8000000U) -#define GPIO_DIRSET_DIRSETP27_SHIFT (27U) -/*! DIRSETP27 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP27_SHIFT)) & GPIO_DIRSET_DIRSETP27_MASK) - -#define GPIO_DIRSET_DIRSETP28_MASK (0x10000000U) -#define GPIO_DIRSET_DIRSETP28_SHIFT (28U) -/*! DIRSETP28 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP28_SHIFT)) & GPIO_DIRSET_DIRSETP28_MASK) - -#define GPIO_DIRSET_DIRSETP29_MASK (0x20000000U) -#define GPIO_DIRSET_DIRSETP29_SHIFT (29U) -/*! DIRSETP29 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP29_SHIFT)) & GPIO_DIRSET_DIRSETP29_MASK) - -#define GPIO_DIRSET_DIRSETP30_MASK (0x40000000U) -#define GPIO_DIRSET_DIRSETP30_SHIFT (30U) -/*! DIRSETP30 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP30_SHIFT)) & GPIO_DIRSET_DIRSETP30_MASK) - -#define GPIO_DIRSET_DIRSETP31_MASK (0x80000000U) -#define GPIO_DIRSET_DIRSETP31_SHIFT (31U) -/*! DIRSETP31 - Direction set bits for Port pins - * 0b0..No operation - * 0b1..Sets direction bit - */ -#define GPIO_DIRSET_DIRSETP31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP31_SHIFT)) & GPIO_DIRSET_DIRSETP31_MASK) -/*! @} */ - -/* The count of GPIO_DIRSET */ -#define GPIO_DIRSET_COUNT (4U) - -/*! @name DIRCLR - Port direction clear */ -/*! @{ */ - -#define GPIO_DIRCLR_DIRCLRP0_MASK (0x1U) -#define GPIO_DIRCLR_DIRCLRP0_SHIFT (0U) -/*! DIRCLRP0 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP0_SHIFT)) & GPIO_DIRCLR_DIRCLRP0_MASK) - -#define GPIO_DIRCLR_DIRCLRP1_MASK (0x2U) -#define GPIO_DIRCLR_DIRCLRP1_SHIFT (1U) -/*! DIRCLRP1 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP1_SHIFT)) & GPIO_DIRCLR_DIRCLRP1_MASK) - -#define GPIO_DIRCLR_DIRCLRP2_MASK (0x4U) -#define GPIO_DIRCLR_DIRCLRP2_SHIFT (2U) -/*! DIRCLRP2 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP2_SHIFT)) & GPIO_DIRCLR_DIRCLRP2_MASK) - -#define GPIO_DIRCLR_DIRCLRP3_MASK (0x8U) -#define GPIO_DIRCLR_DIRCLRP3_SHIFT (3U) -/*! DIRCLRP3 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP3_SHIFT)) & GPIO_DIRCLR_DIRCLRP3_MASK) - -#define GPIO_DIRCLR_DIRCLRP4_MASK (0x10U) -#define GPIO_DIRCLR_DIRCLRP4_SHIFT (4U) -/*! DIRCLRP4 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP4_SHIFT)) & GPIO_DIRCLR_DIRCLRP4_MASK) - -#define GPIO_DIRCLR_DIRCLRP5_MASK (0x20U) -#define GPIO_DIRCLR_DIRCLRP5_SHIFT (5U) -/*! DIRCLRP5 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP5_SHIFT)) & GPIO_DIRCLR_DIRCLRP5_MASK) - -#define GPIO_DIRCLR_DIRCLRP6_MASK (0x40U) -#define GPIO_DIRCLR_DIRCLRP6_SHIFT (6U) -/*! DIRCLRP6 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP6_SHIFT)) & GPIO_DIRCLR_DIRCLRP6_MASK) - -#define GPIO_DIRCLR_DIRCLRP7_MASK (0x80U) -#define GPIO_DIRCLR_DIRCLRP7_SHIFT (7U) -/*! DIRCLRP7 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP7_SHIFT)) & GPIO_DIRCLR_DIRCLRP7_MASK) - -#define GPIO_DIRCLR_DIRCLRP8_MASK (0x100U) -#define GPIO_DIRCLR_DIRCLRP8_SHIFT (8U) -/*! DIRCLRP8 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP8_SHIFT)) & GPIO_DIRCLR_DIRCLRP8_MASK) - -#define GPIO_DIRCLR_DIRCLRP9_MASK (0x200U) -#define GPIO_DIRCLR_DIRCLRP9_SHIFT (9U) -/*! DIRCLRP9 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP9_SHIFT)) & GPIO_DIRCLR_DIRCLRP9_MASK) - -#define GPIO_DIRCLR_DIRCLRP10_MASK (0x400U) -#define GPIO_DIRCLR_DIRCLRP10_SHIFT (10U) -/*! DIRCLRP10 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP10_SHIFT)) & GPIO_DIRCLR_DIRCLRP10_MASK) - -#define GPIO_DIRCLR_DIRCLRP11_MASK (0x800U) -#define GPIO_DIRCLR_DIRCLRP11_SHIFT (11U) -/*! DIRCLRP11 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP11_SHIFT)) & GPIO_DIRCLR_DIRCLRP11_MASK) - -#define GPIO_DIRCLR_DIRCLRP12_MASK (0x1000U) -#define GPIO_DIRCLR_DIRCLRP12_SHIFT (12U) -/*! DIRCLRP12 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP12_SHIFT)) & GPIO_DIRCLR_DIRCLRP12_MASK) - -#define GPIO_DIRCLR_DIRCLRP13_MASK (0x2000U) -#define GPIO_DIRCLR_DIRCLRP13_SHIFT (13U) -/*! DIRCLRP13 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP13_SHIFT)) & GPIO_DIRCLR_DIRCLRP13_MASK) - -#define GPIO_DIRCLR_DIRCLRP14_MASK (0x4000U) -#define GPIO_DIRCLR_DIRCLRP14_SHIFT (14U) -/*! DIRCLRP14 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP14_SHIFT)) & GPIO_DIRCLR_DIRCLRP14_MASK) - -#define GPIO_DIRCLR_DIRCLRP15_MASK (0x8000U) -#define GPIO_DIRCLR_DIRCLRP15_SHIFT (15U) -/*! DIRCLRP15 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP15_SHIFT)) & GPIO_DIRCLR_DIRCLRP15_MASK) - -#define GPIO_DIRCLR_DIRCLRP16_MASK (0x10000U) -#define GPIO_DIRCLR_DIRCLRP16_SHIFT (16U) -/*! DIRCLRP16 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP16_SHIFT)) & GPIO_DIRCLR_DIRCLRP16_MASK) - -#define GPIO_DIRCLR_DIRCLRP17_MASK (0x20000U) -#define GPIO_DIRCLR_DIRCLRP17_SHIFT (17U) -/*! DIRCLRP17 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP17_SHIFT)) & GPIO_DIRCLR_DIRCLRP17_MASK) - -#define GPIO_DIRCLR_DIRCLRP18_MASK (0x40000U) -#define GPIO_DIRCLR_DIRCLRP18_SHIFT (18U) -/*! DIRCLRP18 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP18_SHIFT)) & GPIO_DIRCLR_DIRCLRP18_MASK) - -#define GPIO_DIRCLR_DIRCLRP19_MASK (0x80000U) -#define GPIO_DIRCLR_DIRCLRP19_SHIFT (19U) -/*! DIRCLRP19 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP19_SHIFT)) & GPIO_DIRCLR_DIRCLRP19_MASK) - -#define GPIO_DIRCLR_DIRCLRP20_MASK (0x100000U) -#define GPIO_DIRCLR_DIRCLRP20_SHIFT (20U) -/*! DIRCLRP20 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP20_SHIFT)) & GPIO_DIRCLR_DIRCLRP20_MASK) - -#define GPIO_DIRCLR_DIRCLRP21_MASK (0x200000U) -#define GPIO_DIRCLR_DIRCLRP21_SHIFT (21U) -/*! DIRCLRP21 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP21_SHIFT)) & GPIO_DIRCLR_DIRCLRP21_MASK) - -#define GPIO_DIRCLR_DIRCLRP22_MASK (0x400000U) -#define GPIO_DIRCLR_DIRCLRP22_SHIFT (22U) -/*! DIRCLRP22 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP22_SHIFT)) & GPIO_DIRCLR_DIRCLRP22_MASK) - -#define GPIO_DIRCLR_DIRCLRP23_MASK (0x800000U) -#define GPIO_DIRCLR_DIRCLRP23_SHIFT (23U) -/*! DIRCLRP23 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP23_SHIFT)) & GPIO_DIRCLR_DIRCLRP23_MASK) - -#define GPIO_DIRCLR_DIRCLRP24_MASK (0x1000000U) -#define GPIO_DIRCLR_DIRCLRP24_SHIFT (24U) -/*! DIRCLRP24 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP24_SHIFT)) & GPIO_DIRCLR_DIRCLRP24_MASK) - -#define GPIO_DIRCLR_DIRCLRP25_MASK (0x2000000U) -#define GPIO_DIRCLR_DIRCLRP25_SHIFT (25U) -/*! DIRCLRP25 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP25_SHIFT)) & GPIO_DIRCLR_DIRCLRP25_MASK) - -#define GPIO_DIRCLR_DIRCLRP26_MASK (0x4000000U) -#define GPIO_DIRCLR_DIRCLRP26_SHIFT (26U) -/*! DIRCLRP26 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP26_SHIFT)) & GPIO_DIRCLR_DIRCLRP26_MASK) - -#define GPIO_DIRCLR_DIRCLRP27_MASK (0x8000000U) -#define GPIO_DIRCLR_DIRCLRP27_SHIFT (27U) -/*! DIRCLRP27 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP27_SHIFT)) & GPIO_DIRCLR_DIRCLRP27_MASK) - -#define GPIO_DIRCLR_DIRCLRP28_MASK (0x10000000U) -#define GPIO_DIRCLR_DIRCLRP28_SHIFT (28U) -/*! DIRCLRP28 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP28_SHIFT)) & GPIO_DIRCLR_DIRCLRP28_MASK) - -#define GPIO_DIRCLR_DIRCLRP29_MASK (0x20000000U) -#define GPIO_DIRCLR_DIRCLRP29_SHIFT (29U) -/*! DIRCLRP29 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP29_SHIFT)) & GPIO_DIRCLR_DIRCLRP29_MASK) - -#define GPIO_DIRCLR_DIRCLRP30_MASK (0x40000000U) -#define GPIO_DIRCLR_DIRCLRP30_SHIFT (30U) -/*! DIRCLRP30 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP30_SHIFT)) & GPIO_DIRCLR_DIRCLRP30_MASK) - -#define GPIO_DIRCLR_DIRCLRP31_MASK (0x80000000U) -#define GPIO_DIRCLR_DIRCLRP31_SHIFT (31U) -/*! DIRCLRP31 - Clear direction bits. - * 0b0..No operation - * 0b1..Clears direction bits - */ -#define GPIO_DIRCLR_DIRCLRP31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP31_SHIFT)) & GPIO_DIRCLR_DIRCLRP31_MASK) -/*! @} */ - -/* The count of GPIO_DIRCLR */ -#define GPIO_DIRCLR_COUNT (4U) - -/*! @name DIRNOT - Port direction toggle */ -/*! @{ */ - -#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU) -#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) -/*! DIRNOTP - Toggle direction bits. - * 0b00000000000000000000000000000..No operation - * 0b00000000000000000000000000001..Toggles direction bit - */ -#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) -/*! @} */ - -/* The count of GPIO_DIRNOT */ -#define GPIO_DIRNOT_COUNT (4U) - -/*! @name INTENA - Interrupt A enable control */ -/*! @{ */ - -#define GPIO_INTENA_INT_EN0_MASK (0x1U) -#define GPIO_INTENA_INT_EN0_SHIFT (0U) -/*! INT_EN0 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN0_SHIFT)) & GPIO_INTENA_INT_EN0_MASK) - -#define GPIO_INTENA_INT_EN1_MASK (0x2U) -#define GPIO_INTENA_INT_EN1_SHIFT (1U) -/*! INT_EN1 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN1_SHIFT)) & GPIO_INTENA_INT_EN1_MASK) - -#define GPIO_INTENA_INT_EN2_MASK (0x4U) -#define GPIO_INTENA_INT_EN2_SHIFT (2U) -/*! INT_EN2 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN2_SHIFT)) & GPIO_INTENA_INT_EN2_MASK) - -#define GPIO_INTENA_INT_EN3_MASK (0x8U) -#define GPIO_INTENA_INT_EN3_SHIFT (3U) -/*! INT_EN3 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN3_SHIFT)) & GPIO_INTENA_INT_EN3_MASK) - -#define GPIO_INTENA_INT_EN4_MASK (0x10U) -#define GPIO_INTENA_INT_EN4_SHIFT (4U) -/*! INT_EN4 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN4_SHIFT)) & GPIO_INTENA_INT_EN4_MASK) - -#define GPIO_INTENA_INT_EN5_MASK (0x20U) -#define GPIO_INTENA_INT_EN5_SHIFT (5U) -/*! INT_EN5 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN5_SHIFT)) & GPIO_INTENA_INT_EN5_MASK) - -#define GPIO_INTENA_INT_EN6_MASK (0x40U) -#define GPIO_INTENA_INT_EN6_SHIFT (6U) -/*! INT_EN6 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN6_SHIFT)) & GPIO_INTENA_INT_EN6_MASK) - -#define GPIO_INTENA_INT_EN7_MASK (0x80U) -#define GPIO_INTENA_INT_EN7_SHIFT (7U) -/*! INT_EN7 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN7_SHIFT)) & GPIO_INTENA_INT_EN7_MASK) - -#define GPIO_INTENA_INT_EN8_MASK (0x100U) -#define GPIO_INTENA_INT_EN8_SHIFT (8U) -/*! INT_EN8 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN8_SHIFT)) & GPIO_INTENA_INT_EN8_MASK) - -#define GPIO_INTENA_INT_EN9_MASK (0x200U) -#define GPIO_INTENA_INT_EN9_SHIFT (9U) -/*! INT_EN9 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN9_SHIFT)) & GPIO_INTENA_INT_EN9_MASK) - -#define GPIO_INTENA_INT_EN10_MASK (0x400U) -#define GPIO_INTENA_INT_EN10_SHIFT (10U) -/*! INT_EN10 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN10_SHIFT)) & GPIO_INTENA_INT_EN10_MASK) - -#define GPIO_INTENA_INT_EN11_MASK (0x800U) -#define GPIO_INTENA_INT_EN11_SHIFT (11U) -/*! INT_EN11 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN11_SHIFT)) & GPIO_INTENA_INT_EN11_MASK) - -#define GPIO_INTENA_INT_EN12_MASK (0x1000U) -#define GPIO_INTENA_INT_EN12_SHIFT (12U) -/*! INT_EN12 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN12_SHIFT)) & GPIO_INTENA_INT_EN12_MASK) - -#define GPIO_INTENA_INT_EN13_MASK (0x2000U) -#define GPIO_INTENA_INT_EN13_SHIFT (13U) -/*! INT_EN13 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN13_SHIFT)) & GPIO_INTENA_INT_EN13_MASK) - -#define GPIO_INTENA_INT_EN14_MASK (0x4000U) -#define GPIO_INTENA_INT_EN14_SHIFT (14U) -/*! INT_EN14 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN14_SHIFT)) & GPIO_INTENA_INT_EN14_MASK) - -#define GPIO_INTENA_INT_EN15_MASK (0x8000U) -#define GPIO_INTENA_INT_EN15_SHIFT (15U) -/*! INT_EN15 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN15_SHIFT)) & GPIO_INTENA_INT_EN15_MASK) - -#define GPIO_INTENA_INT_EN16_MASK (0x10000U) -#define GPIO_INTENA_INT_EN16_SHIFT (16U) -/*! INT_EN16 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN16_SHIFT)) & GPIO_INTENA_INT_EN16_MASK) - -#define GPIO_INTENA_INT_EN17_MASK (0x20000U) -#define GPIO_INTENA_INT_EN17_SHIFT (17U) -/*! INT_EN17 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN17_SHIFT)) & GPIO_INTENA_INT_EN17_MASK) - -#define GPIO_INTENA_INT_EN18_MASK (0x40000U) -#define GPIO_INTENA_INT_EN18_SHIFT (18U) -/*! INT_EN18 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN18_SHIFT)) & GPIO_INTENA_INT_EN18_MASK) - -#define GPIO_INTENA_INT_EN19_MASK (0x80000U) -#define GPIO_INTENA_INT_EN19_SHIFT (19U) -/*! INT_EN19 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN19_SHIFT)) & GPIO_INTENA_INT_EN19_MASK) - -#define GPIO_INTENA_INT_EN20_MASK (0x100000U) -#define GPIO_INTENA_INT_EN20_SHIFT (20U) -/*! INT_EN20 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN20_SHIFT)) & GPIO_INTENA_INT_EN20_MASK) - -#define GPIO_INTENA_INT_EN21_MASK (0x200000U) -#define GPIO_INTENA_INT_EN21_SHIFT (21U) -/*! INT_EN21 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN21_SHIFT)) & GPIO_INTENA_INT_EN21_MASK) - -#define GPIO_INTENA_INT_EN22_MASK (0x400000U) -#define GPIO_INTENA_INT_EN22_SHIFT (22U) -/*! INT_EN22 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN22_SHIFT)) & GPIO_INTENA_INT_EN22_MASK) - -#define GPIO_INTENA_INT_EN23_MASK (0x800000U) -#define GPIO_INTENA_INT_EN23_SHIFT (23U) -/*! INT_EN23 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN23_SHIFT)) & GPIO_INTENA_INT_EN23_MASK) - -#define GPIO_INTENA_INT_EN24_MASK (0x1000000U) -#define GPIO_INTENA_INT_EN24_SHIFT (24U) -/*! INT_EN24 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN24_SHIFT)) & GPIO_INTENA_INT_EN24_MASK) - -#define GPIO_INTENA_INT_EN25_MASK (0x2000000U) -#define GPIO_INTENA_INT_EN25_SHIFT (25U) -/*! INT_EN25 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN25_SHIFT)) & GPIO_INTENA_INT_EN25_MASK) - -#define GPIO_INTENA_INT_EN26_MASK (0x4000000U) -#define GPIO_INTENA_INT_EN26_SHIFT (26U) -/*! INT_EN26 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN26_SHIFT)) & GPIO_INTENA_INT_EN26_MASK) - -#define GPIO_INTENA_INT_EN27_MASK (0x8000000U) -#define GPIO_INTENA_INT_EN27_SHIFT (27U) -/*! INT_EN27 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN27_SHIFT)) & GPIO_INTENA_INT_EN27_MASK) - -#define GPIO_INTENA_INT_EN28_MASK (0x10000000U) -#define GPIO_INTENA_INT_EN28_SHIFT (28U) -/*! INT_EN28 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN28_SHIFT)) & GPIO_INTENA_INT_EN28_MASK) - -#define GPIO_INTENA_INT_EN29_MASK (0x20000000U) -#define GPIO_INTENA_INT_EN29_SHIFT (29U) -/*! INT_EN29 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN29_SHIFT)) & GPIO_INTENA_INT_EN29_MASK) - -#define GPIO_INTENA_INT_EN30_MASK (0x40000000U) -#define GPIO_INTENA_INT_EN30_SHIFT (30U) -/*! INT_EN30 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN30_SHIFT)) & GPIO_INTENA_INT_EN30_MASK) - -#define GPIO_INTENA_INT_EN31_MASK (0x80000000U) -#define GPIO_INTENA_INT_EN31_SHIFT (31U) -/*! INT_EN31 - Interrupt A enable bits. - * 0b0..Pin does not contribute to GPIO interrupt A - * 0b1..Pin contributes to GPIO interrupt A - */ -#define GPIO_INTENA_INT_EN31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN31_SHIFT)) & GPIO_INTENA_INT_EN31_MASK) -/*! @} */ - -/* The count of GPIO_INTENA */ -#define GPIO_INTENA_COUNT (4U) - -/*! @name INTENB - Interrupt B enable control */ -/*! @{ */ - -#define GPIO_INTENB_INT_EN0_MASK (0x1U) -#define GPIO_INTENB_INT_EN0_SHIFT (0U) -/*! INT_EN0 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN0_SHIFT)) & GPIO_INTENB_INT_EN0_MASK) - -#define GPIO_INTENB_INT_EN1_MASK (0x2U) -#define GPIO_INTENB_INT_EN1_SHIFT (1U) -/*! INT_EN1 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN1_SHIFT)) & GPIO_INTENB_INT_EN1_MASK) - -#define GPIO_INTENB_INT_EN2_MASK (0x4U) -#define GPIO_INTENB_INT_EN2_SHIFT (2U) -/*! INT_EN2 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN2_SHIFT)) & GPIO_INTENB_INT_EN2_MASK) - -#define GPIO_INTENB_INT_EN3_MASK (0x8U) -#define GPIO_INTENB_INT_EN3_SHIFT (3U) -/*! INT_EN3 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN3_SHIFT)) & GPIO_INTENB_INT_EN3_MASK) - -#define GPIO_INTENB_INT_EN4_MASK (0x10U) -#define GPIO_INTENB_INT_EN4_SHIFT (4U) -/*! INT_EN4 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN4_SHIFT)) & GPIO_INTENB_INT_EN4_MASK) - -#define GPIO_INTENB_INT_EN5_MASK (0x20U) -#define GPIO_INTENB_INT_EN5_SHIFT (5U) -/*! INT_EN5 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN5_SHIFT)) & GPIO_INTENB_INT_EN5_MASK) - -#define GPIO_INTENB_INT_EN6_MASK (0x40U) -#define GPIO_INTENB_INT_EN6_SHIFT (6U) -/*! INT_EN6 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN6_SHIFT)) & GPIO_INTENB_INT_EN6_MASK) - -#define GPIO_INTENB_INT_EN7_MASK (0x80U) -#define GPIO_INTENB_INT_EN7_SHIFT (7U) -/*! INT_EN7 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN7_SHIFT)) & GPIO_INTENB_INT_EN7_MASK) - -#define GPIO_INTENB_INT_EN8_MASK (0x100U) -#define GPIO_INTENB_INT_EN8_SHIFT (8U) -/*! INT_EN8 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN8_SHIFT)) & GPIO_INTENB_INT_EN8_MASK) - -#define GPIO_INTENB_INT_EN9_MASK (0x200U) -#define GPIO_INTENB_INT_EN9_SHIFT (9U) -/*! INT_EN9 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN9_SHIFT)) & GPIO_INTENB_INT_EN9_MASK) - -#define GPIO_INTENB_INT_EN10_MASK (0x400U) -#define GPIO_INTENB_INT_EN10_SHIFT (10U) -/*! INT_EN10 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN10_SHIFT)) & GPIO_INTENB_INT_EN10_MASK) - -#define GPIO_INTENB_INT_EN11_MASK (0x800U) -#define GPIO_INTENB_INT_EN11_SHIFT (11U) -/*! INT_EN11 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN11_SHIFT)) & GPIO_INTENB_INT_EN11_MASK) - -#define GPIO_INTENB_INT_EN12_MASK (0x1000U) -#define GPIO_INTENB_INT_EN12_SHIFT (12U) -/*! INT_EN12 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN12_SHIFT)) & GPIO_INTENB_INT_EN12_MASK) - -#define GPIO_INTENB_INT_EN13_MASK (0x2000U) -#define GPIO_INTENB_INT_EN13_SHIFT (13U) -/*! INT_EN13 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN13_SHIFT)) & GPIO_INTENB_INT_EN13_MASK) - -#define GPIO_INTENB_INT_EN14_MASK (0x4000U) -#define GPIO_INTENB_INT_EN14_SHIFT (14U) -/*! INT_EN14 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN14_SHIFT)) & GPIO_INTENB_INT_EN14_MASK) - -#define GPIO_INTENB_INT_EN15_MASK (0x8000U) -#define GPIO_INTENB_INT_EN15_SHIFT (15U) -/*! INT_EN15 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN15_SHIFT)) & GPIO_INTENB_INT_EN15_MASK) - -#define GPIO_INTENB_INT_EN16_MASK (0x10000U) -#define GPIO_INTENB_INT_EN16_SHIFT (16U) -/*! INT_EN16 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN16_SHIFT)) & GPIO_INTENB_INT_EN16_MASK) - -#define GPIO_INTENB_INT_EN17_MASK (0x20000U) -#define GPIO_INTENB_INT_EN17_SHIFT (17U) -/*! INT_EN17 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN17_SHIFT)) & GPIO_INTENB_INT_EN17_MASK) - -#define GPIO_INTENB_INT_EN18_MASK (0x40000U) -#define GPIO_INTENB_INT_EN18_SHIFT (18U) -/*! INT_EN18 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN18_SHIFT)) & GPIO_INTENB_INT_EN18_MASK) - -#define GPIO_INTENB_INT_EN19_MASK (0x80000U) -#define GPIO_INTENB_INT_EN19_SHIFT (19U) -/*! INT_EN19 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN19_SHIFT)) & GPIO_INTENB_INT_EN19_MASK) - -#define GPIO_INTENB_INT_EN20_MASK (0x100000U) -#define GPIO_INTENB_INT_EN20_SHIFT (20U) -/*! INT_EN20 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN20_SHIFT)) & GPIO_INTENB_INT_EN20_MASK) - -#define GPIO_INTENB_INT_EN21_MASK (0x200000U) -#define GPIO_INTENB_INT_EN21_SHIFT (21U) -/*! INT_EN21 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN21_SHIFT)) & GPIO_INTENB_INT_EN21_MASK) - -#define GPIO_INTENB_INT_EN22_MASK (0x400000U) -#define GPIO_INTENB_INT_EN22_SHIFT (22U) -/*! INT_EN22 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN22_SHIFT)) & GPIO_INTENB_INT_EN22_MASK) - -#define GPIO_INTENB_INT_EN23_MASK (0x800000U) -#define GPIO_INTENB_INT_EN23_SHIFT (23U) -/*! INT_EN23 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN23_SHIFT)) & GPIO_INTENB_INT_EN23_MASK) - -#define GPIO_INTENB_INT_EN24_MASK (0x1000000U) -#define GPIO_INTENB_INT_EN24_SHIFT (24U) -/*! INT_EN24 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN24_SHIFT)) & GPIO_INTENB_INT_EN24_MASK) - -#define GPIO_INTENB_INT_EN25_MASK (0x2000000U) -#define GPIO_INTENB_INT_EN25_SHIFT (25U) -/*! INT_EN25 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN25_SHIFT)) & GPIO_INTENB_INT_EN25_MASK) - -#define GPIO_INTENB_INT_EN26_MASK (0x4000000U) -#define GPIO_INTENB_INT_EN26_SHIFT (26U) -/*! INT_EN26 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN26_SHIFT)) & GPIO_INTENB_INT_EN26_MASK) - -#define GPIO_INTENB_INT_EN27_MASK (0x8000000U) -#define GPIO_INTENB_INT_EN27_SHIFT (27U) -/*! INT_EN27 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN27_SHIFT)) & GPIO_INTENB_INT_EN27_MASK) - -#define GPIO_INTENB_INT_EN28_MASK (0x10000000U) -#define GPIO_INTENB_INT_EN28_SHIFT (28U) -/*! INT_EN28 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN28_SHIFT)) & GPIO_INTENB_INT_EN28_MASK) - -#define GPIO_INTENB_INT_EN29_MASK (0x20000000U) -#define GPIO_INTENB_INT_EN29_SHIFT (29U) -/*! INT_EN29 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN29_SHIFT)) & GPIO_INTENB_INT_EN29_MASK) - -#define GPIO_INTENB_INT_EN30_MASK (0x40000000U) -#define GPIO_INTENB_INT_EN30_SHIFT (30U) -/*! INT_EN30 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN30_SHIFT)) & GPIO_INTENB_INT_EN30_MASK) - -#define GPIO_INTENB_INT_EN31_MASK (0x80000000U) -#define GPIO_INTENB_INT_EN31_SHIFT (31U) -/*! INT_EN31 - Interrupt B enable bits. - * 0b0..Pin does not contribute to GPIO interrupt B - * 0b1..Pin contributes to GPIO interrupt B - */ -#define GPIO_INTENB_INT_EN31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN31_SHIFT)) & GPIO_INTENB_INT_EN31_MASK) -/*! @} */ - -/* The count of GPIO_INTENB */ -#define GPIO_INTENB_COUNT (4U) - -/*! @name INTPOL - Interupt polarity control */ -/*! @{ */ - -#define GPIO_INTPOL_POL_CTL0_MASK (0x1U) -#define GPIO_INTPOL_POL_CTL0_SHIFT (0U) -/*! POL_CTL0 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL0_SHIFT)) & GPIO_INTPOL_POL_CTL0_MASK) - -#define GPIO_INTPOL_POL_CTL1_MASK (0x2U) -#define GPIO_INTPOL_POL_CTL1_SHIFT (1U) -/*! POL_CTL1 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL1_SHIFT)) & GPIO_INTPOL_POL_CTL1_MASK) - -#define GPIO_INTPOL_POL_CTL2_MASK (0x4U) -#define GPIO_INTPOL_POL_CTL2_SHIFT (2U) -/*! POL_CTL2 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL2_SHIFT)) & GPIO_INTPOL_POL_CTL2_MASK) - -#define GPIO_INTPOL_POL_CTL3_MASK (0x8U) -#define GPIO_INTPOL_POL_CTL3_SHIFT (3U) -/*! POL_CTL3 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL3_SHIFT)) & GPIO_INTPOL_POL_CTL3_MASK) - -#define GPIO_INTPOL_POL_CTL4_MASK (0x10U) -#define GPIO_INTPOL_POL_CTL4_SHIFT (4U) -/*! POL_CTL4 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL4_SHIFT)) & GPIO_INTPOL_POL_CTL4_MASK) - -#define GPIO_INTPOL_POL_CTL5_MASK (0x20U) -#define GPIO_INTPOL_POL_CTL5_SHIFT (5U) -/*! POL_CTL5 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL5_SHIFT)) & GPIO_INTPOL_POL_CTL5_MASK) - -#define GPIO_INTPOL_POL_CTL6_MASK (0x40U) -#define GPIO_INTPOL_POL_CTL6_SHIFT (6U) -/*! POL_CTL6 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL6_SHIFT)) & GPIO_INTPOL_POL_CTL6_MASK) - -#define GPIO_INTPOL_POL_CTL7_MASK (0x80U) -#define GPIO_INTPOL_POL_CTL7_SHIFT (7U) -/*! POL_CTL7 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL7_SHIFT)) & GPIO_INTPOL_POL_CTL7_MASK) - -#define GPIO_INTPOL_POL_CTL8_MASK (0x100U) -#define GPIO_INTPOL_POL_CTL8_SHIFT (8U) -/*! POL_CTL8 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL8_SHIFT)) & GPIO_INTPOL_POL_CTL8_MASK) - -#define GPIO_INTPOL_POL_CTL9_MASK (0x200U) -#define GPIO_INTPOL_POL_CTL9_SHIFT (9U) -/*! POL_CTL9 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL9_SHIFT)) & GPIO_INTPOL_POL_CTL9_MASK) - -#define GPIO_INTPOL_POL_CTL10_MASK (0x400U) -#define GPIO_INTPOL_POL_CTL10_SHIFT (10U) -/*! POL_CTL10 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL10_SHIFT)) & GPIO_INTPOL_POL_CTL10_MASK) - -#define GPIO_INTPOL_POL_CTL11_MASK (0x800U) -#define GPIO_INTPOL_POL_CTL11_SHIFT (11U) -/*! POL_CTL11 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL11_SHIFT)) & GPIO_INTPOL_POL_CTL11_MASK) - -#define GPIO_INTPOL_POL_CTL12_MASK (0x1000U) -#define GPIO_INTPOL_POL_CTL12_SHIFT (12U) -/*! POL_CTL12 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL12_SHIFT)) & GPIO_INTPOL_POL_CTL12_MASK) - -#define GPIO_INTPOL_POL_CTL13_MASK (0x2000U) -#define GPIO_INTPOL_POL_CTL13_SHIFT (13U) -/*! POL_CTL13 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL13_SHIFT)) & GPIO_INTPOL_POL_CTL13_MASK) - -#define GPIO_INTPOL_POL_CTL14_MASK (0x4000U) -#define GPIO_INTPOL_POL_CTL14_SHIFT (14U) -/*! POL_CTL14 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL14_SHIFT)) & GPIO_INTPOL_POL_CTL14_MASK) - -#define GPIO_INTPOL_POL_CTL15_MASK (0x8000U) -#define GPIO_INTPOL_POL_CTL15_SHIFT (15U) -/*! POL_CTL15 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL15_SHIFT)) & GPIO_INTPOL_POL_CTL15_MASK) - -#define GPIO_INTPOL_POL_CTL16_MASK (0x10000U) -#define GPIO_INTPOL_POL_CTL16_SHIFT (16U) -/*! POL_CTL16 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL16_SHIFT)) & GPIO_INTPOL_POL_CTL16_MASK) - -#define GPIO_INTPOL_POL_CTL17_MASK (0x20000U) -#define GPIO_INTPOL_POL_CTL17_SHIFT (17U) -/*! POL_CTL17 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL17_SHIFT)) & GPIO_INTPOL_POL_CTL17_MASK) - -#define GPIO_INTPOL_POL_CTL18_MASK (0x40000U) -#define GPIO_INTPOL_POL_CTL18_SHIFT (18U) -/*! POL_CTL18 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL18_SHIFT)) & GPIO_INTPOL_POL_CTL18_MASK) - -#define GPIO_INTPOL_POL_CTL19_MASK (0x80000U) -#define GPIO_INTPOL_POL_CTL19_SHIFT (19U) -/*! POL_CTL19 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL19_SHIFT)) & GPIO_INTPOL_POL_CTL19_MASK) - -#define GPIO_INTPOL_POL_CTL20_MASK (0x100000U) -#define GPIO_INTPOL_POL_CTL20_SHIFT (20U) -/*! POL_CTL20 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL20_SHIFT)) & GPIO_INTPOL_POL_CTL20_MASK) - -#define GPIO_INTPOL_POL_CTL21_MASK (0x200000U) -#define GPIO_INTPOL_POL_CTL21_SHIFT (21U) -/*! POL_CTL21 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL21_SHIFT)) & GPIO_INTPOL_POL_CTL21_MASK) - -#define GPIO_INTPOL_POL_CTL22_MASK (0x400000U) -#define GPIO_INTPOL_POL_CTL22_SHIFT (22U) -/*! POL_CTL22 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL22_SHIFT)) & GPIO_INTPOL_POL_CTL22_MASK) - -#define GPIO_INTPOL_POL_CTL23_MASK (0x800000U) -#define GPIO_INTPOL_POL_CTL23_SHIFT (23U) -/*! POL_CTL23 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL23_SHIFT)) & GPIO_INTPOL_POL_CTL23_MASK) - -#define GPIO_INTPOL_POL_CTL24_MASK (0x1000000U) -#define GPIO_INTPOL_POL_CTL24_SHIFT (24U) -/*! POL_CTL24 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL24_SHIFT)) & GPIO_INTPOL_POL_CTL24_MASK) - -#define GPIO_INTPOL_POL_CTL25_MASK (0x2000000U) -#define GPIO_INTPOL_POL_CTL25_SHIFT (25U) -/*! POL_CTL25 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL25_SHIFT)) & GPIO_INTPOL_POL_CTL25_MASK) - -#define GPIO_INTPOL_POL_CTL26_MASK (0x4000000U) -#define GPIO_INTPOL_POL_CTL26_SHIFT (26U) -/*! POL_CTL26 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL26_SHIFT)) & GPIO_INTPOL_POL_CTL26_MASK) - -#define GPIO_INTPOL_POL_CTL27_MASK (0x8000000U) -#define GPIO_INTPOL_POL_CTL27_SHIFT (27U) -/*! POL_CTL27 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL27_SHIFT)) & GPIO_INTPOL_POL_CTL27_MASK) - -#define GPIO_INTPOL_POL_CTL28_MASK (0x10000000U) -#define GPIO_INTPOL_POL_CTL28_SHIFT (28U) -/*! POL_CTL28 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL28_SHIFT)) & GPIO_INTPOL_POL_CTL28_MASK) - -#define GPIO_INTPOL_POL_CTL29_MASK (0x20000000U) -#define GPIO_INTPOL_POL_CTL29_SHIFT (29U) -/*! POL_CTL29 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL29_SHIFT)) & GPIO_INTPOL_POL_CTL29_MASK) - -#define GPIO_INTPOL_POL_CTL30_MASK (0x40000000U) -#define GPIO_INTPOL_POL_CTL30_SHIFT (30U) -/*! POL_CTL30 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL30_SHIFT)) & GPIO_INTPOL_POL_CTL30_MASK) - -#define GPIO_INTPOL_POL_CTL31_MASK (0x80000000U) -#define GPIO_INTPOL_POL_CTL31_SHIFT (31U) -/*! POL_CTL31 - Polarity control for each pin - * 0b0..High level or rising edge triggered - * 0b1..Low level or falling edge triggered - */ -#define GPIO_INTPOL_POL_CTL31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL31_SHIFT)) & GPIO_INTPOL_POL_CTL31_MASK) -/*! @} */ - -/* The count of GPIO_INTPOL */ -#define GPIO_INTPOL_COUNT (4U) - -/*! @name INTEDG - Interrupt edge select */ -/*! @{ */ - -#define GPIO_INTEDG_EDGE0_MASK (0x1U) -#define GPIO_INTEDG_EDGE0_SHIFT (0U) -/*! EDGE0 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE0_SHIFT)) & GPIO_INTEDG_EDGE0_MASK) - -#define GPIO_INTEDG_EDGE1_MASK (0x2U) -#define GPIO_INTEDG_EDGE1_SHIFT (1U) -/*! EDGE1 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE1_SHIFT)) & GPIO_INTEDG_EDGE1_MASK) - -#define GPIO_INTEDG_EDGE2_MASK (0x4U) -#define GPIO_INTEDG_EDGE2_SHIFT (2U) -/*! EDGE2 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE2_SHIFT)) & GPIO_INTEDG_EDGE2_MASK) - -#define GPIO_INTEDG_EDGE3_MASK (0x8U) -#define GPIO_INTEDG_EDGE3_SHIFT (3U) -/*! EDGE3 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE3_SHIFT)) & GPIO_INTEDG_EDGE3_MASK) - -#define GPIO_INTEDG_EDGE4_MASK (0x10U) -#define GPIO_INTEDG_EDGE4_SHIFT (4U) -/*! EDGE4 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE4_SHIFT)) & GPIO_INTEDG_EDGE4_MASK) - -#define GPIO_INTEDG_EDGE5_MASK (0x20U) -#define GPIO_INTEDG_EDGE5_SHIFT (5U) -/*! EDGE5 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE5_SHIFT)) & GPIO_INTEDG_EDGE5_MASK) - -#define GPIO_INTEDG_EDGE6_MASK (0x40U) -#define GPIO_INTEDG_EDGE6_SHIFT (6U) -/*! EDGE6 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE6_SHIFT)) & GPIO_INTEDG_EDGE6_MASK) - -#define GPIO_INTEDG_EDGE7_MASK (0x80U) -#define GPIO_INTEDG_EDGE7_SHIFT (7U) -/*! EDGE7 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE7_SHIFT)) & GPIO_INTEDG_EDGE7_MASK) - -#define GPIO_INTEDG_EDGE8_MASK (0x100U) -#define GPIO_INTEDG_EDGE8_SHIFT (8U) -/*! EDGE8 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE8_SHIFT)) & GPIO_INTEDG_EDGE8_MASK) - -#define GPIO_INTEDG_EDGE9_MASK (0x200U) -#define GPIO_INTEDG_EDGE9_SHIFT (9U) -/*! EDGE9 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE9_SHIFT)) & GPIO_INTEDG_EDGE9_MASK) - -#define GPIO_INTEDG_EDGE10_MASK (0x400U) -#define GPIO_INTEDG_EDGE10_SHIFT (10U) -/*! EDGE10 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE10_SHIFT)) & GPIO_INTEDG_EDGE10_MASK) - -#define GPIO_INTEDG_EDGE11_MASK (0x800U) -#define GPIO_INTEDG_EDGE11_SHIFT (11U) -/*! EDGE11 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE11_SHIFT)) & GPIO_INTEDG_EDGE11_MASK) - -#define GPIO_INTEDG_EDGE12_MASK (0x1000U) -#define GPIO_INTEDG_EDGE12_SHIFT (12U) -/*! EDGE12 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE12_SHIFT)) & GPIO_INTEDG_EDGE12_MASK) - -#define GPIO_INTEDG_EDGE13_MASK (0x2000U) -#define GPIO_INTEDG_EDGE13_SHIFT (13U) -/*! EDGE13 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE13_SHIFT)) & GPIO_INTEDG_EDGE13_MASK) - -#define GPIO_INTEDG_EDGE14_MASK (0x4000U) -#define GPIO_INTEDG_EDGE14_SHIFT (14U) -/*! EDGE14 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE14_SHIFT)) & GPIO_INTEDG_EDGE14_MASK) - -#define GPIO_INTEDG_EDGE15_MASK (0x8000U) -#define GPIO_INTEDG_EDGE15_SHIFT (15U) -/*! EDGE15 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE15_SHIFT)) & GPIO_INTEDG_EDGE15_MASK) - -#define GPIO_INTEDG_EDGE16_MASK (0x10000U) -#define GPIO_INTEDG_EDGE16_SHIFT (16U) -/*! EDGE16 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE16_SHIFT)) & GPIO_INTEDG_EDGE16_MASK) - -#define GPIO_INTEDG_EDGE17_MASK (0x20000U) -#define GPIO_INTEDG_EDGE17_SHIFT (17U) -/*! EDGE17 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE17_SHIFT)) & GPIO_INTEDG_EDGE17_MASK) - -#define GPIO_INTEDG_EDGE18_MASK (0x40000U) -#define GPIO_INTEDG_EDGE18_SHIFT (18U) -/*! EDGE18 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE18_SHIFT)) & GPIO_INTEDG_EDGE18_MASK) - -#define GPIO_INTEDG_EDGE19_MASK (0x80000U) -#define GPIO_INTEDG_EDGE19_SHIFT (19U) -/*! EDGE19 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE19_SHIFT)) & GPIO_INTEDG_EDGE19_MASK) - -#define GPIO_INTEDG_EDGE20_MASK (0x100000U) -#define GPIO_INTEDG_EDGE20_SHIFT (20U) -/*! EDGE20 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE20_SHIFT)) & GPIO_INTEDG_EDGE20_MASK) - -#define GPIO_INTEDG_EDGE21_MASK (0x200000U) -#define GPIO_INTEDG_EDGE21_SHIFT (21U) -/*! EDGE21 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE21_SHIFT)) & GPIO_INTEDG_EDGE21_MASK) - -#define GPIO_INTEDG_EDGE22_MASK (0x400000U) -#define GPIO_INTEDG_EDGE22_SHIFT (22U) -/*! EDGE22 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE22_SHIFT)) & GPIO_INTEDG_EDGE22_MASK) - -#define GPIO_INTEDG_EDGE23_MASK (0x800000U) -#define GPIO_INTEDG_EDGE23_SHIFT (23U) -/*! EDGE23 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE23_SHIFT)) & GPIO_INTEDG_EDGE23_MASK) - -#define GPIO_INTEDG_EDGE24_MASK (0x1000000U) -#define GPIO_INTEDG_EDGE24_SHIFT (24U) -/*! EDGE24 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE24_SHIFT)) & GPIO_INTEDG_EDGE24_MASK) - -#define GPIO_INTEDG_EDGE25_MASK (0x2000000U) -#define GPIO_INTEDG_EDGE25_SHIFT (25U) -/*! EDGE25 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE25_SHIFT)) & GPIO_INTEDG_EDGE25_MASK) - -#define GPIO_INTEDG_EDGE26_MASK (0x4000000U) -#define GPIO_INTEDG_EDGE26_SHIFT (26U) -/*! EDGE26 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE26_SHIFT)) & GPIO_INTEDG_EDGE26_MASK) - -#define GPIO_INTEDG_EDGE27_MASK (0x8000000U) -#define GPIO_INTEDG_EDGE27_SHIFT (27U) -/*! EDGE27 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE27_SHIFT)) & GPIO_INTEDG_EDGE27_MASK) - -#define GPIO_INTEDG_EDGE28_MASK (0x10000000U) -#define GPIO_INTEDG_EDGE28_SHIFT (28U) -/*! EDGE28 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE28_SHIFT)) & GPIO_INTEDG_EDGE28_MASK) - -#define GPIO_INTEDG_EDGE29_MASK (0x20000000U) -#define GPIO_INTEDG_EDGE29_SHIFT (29U) -/*! EDGE29 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE29_SHIFT)) & GPIO_INTEDG_EDGE29_MASK) - -#define GPIO_INTEDG_EDGE30_MASK (0x40000000U) -#define GPIO_INTEDG_EDGE30_SHIFT (30U) -/*! EDGE30 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE30_SHIFT)) & GPIO_INTEDG_EDGE30_MASK) - -#define GPIO_INTEDG_EDGE31_MASK (0x80000000U) -#define GPIO_INTEDG_EDGE31_SHIFT (31U) -/*! EDGE31 - Edge or level mode select bits. - * 0b0..Level mode - * 0b1..Edge mode - */ -#define GPIO_INTEDG_EDGE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE31_SHIFT)) & GPIO_INTEDG_EDGE31_MASK) -/*! @} */ - -/* The count of GPIO_INTEDG */ -#define GPIO_INTEDG_COUNT (4U) - -/*! @name INTSTATA - Interrupt status for interrupt A */ -/*! @{ */ - -#define GPIO_INTSTATA_STATUS_MASK (0xFFFFFFFFU) -#define GPIO_INTSTATA_STATUS_SHIFT (0U) -/*! STATUS - Interrupt status. - */ -#define GPIO_INTSTATA_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTSTATA_STATUS_SHIFT)) & GPIO_INTSTATA_STATUS_MASK) -/*! @} */ - -/* The count of GPIO_INTSTATA */ -#define GPIO_INTSTATA_COUNT (4U) - -/*! @name INTSTATB - Interrupt status for interrupt B */ -/*! @{ */ - -#define GPIO_INTSTATB_STATUS_MASK (0xFFFFFFFFU) -#define GPIO_INTSTATB_STATUS_SHIFT (0U) -/*! STATUS - Interrupt status - */ -#define GPIO_INTSTATB_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTSTATB_STATUS_SHIFT)) & GPIO_INTSTATB_STATUS_MASK) -/*! @} */ - -/* The count of GPIO_INTSTATB */ -#define GPIO_INTSTATB_COUNT (4U) - - -/*! - * @} - */ /* end of group GPIO_Register_Masks */ - - -/* GPIO - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral GPIO base address */ - #define GPIO_BASE (0x5008C000u) - /** Peripheral GPIO base address */ - #define GPIO_BASE_NS (0x4008C000u) - /** Peripheral GPIO base pointer */ - #define GPIO ((GPIO_Type *)GPIO_BASE) - /** Peripheral GPIO base pointer */ - #define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE (0x500A8000u) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE_NS (0x400A8000u) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS) - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO, SECGPIO } - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS_NS { GPIO_BASE_NS, SECGPIO_BASE_NS } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS_NS { GPIO_NS, SECGPIO_NS } -#else - /** Peripheral GPIO base address */ - #define GPIO_BASE (0x4008C000u) - /** Peripheral GPIO base pointer */ - #define GPIO ((GPIO_Type *)GPIO_BASE) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE (0x400A8000u) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO, SECGPIO } -#endif - -/*! - * @} - */ /* end of group GPIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- HSCMP Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup HSCMP_Peripheral_Access_Layer HSCMP Peripheral Access Layer - * @{ - */ - -/** HSCMP - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t CCR0; /**< Comparator Control Register 0, offset: 0x8 */ - __IO uint32_t CCR1; /**< Comparator Control Register 1, offset: 0xC */ - __IO uint32_t CCR2; /**< Comparator Control Register 2, offset: 0x10 */ - uint8_t RESERVED_0[4]; - __IO uint32_t DCR; /**< DAC Control Register, offset: 0x18 */ - __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x1C */ - __IO uint32_t CSR; /**< Comparator Status Register, offset: 0x20 */ - __IO uint32_t RRCR0; /**< Round Robin Control Register 0, offset: 0x24 */ - __IO uint32_t RRCR1; /**< Round Robin Control Register 1, offset: 0x28 */ - __IO uint32_t RRCSR; /**< Round Robin Control and Status Register, offset: 0x2C */ - __IO uint32_t RRSR; /**< Round Robin Status Register, offset: 0x30 */ - uint8_t RESERVED_1[4]; - __IO uint32_t RRCR2; /**< Round Robin Control Register 2, offset: 0x38 */ -} HSCMP_Type; - -/* ---------------------------------------------------------------------------- - -- HSCMP Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup HSCMP_Register_Masks HSCMP Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ - -#define HSCMP_VERID_FEATURE_MASK (0xFFFFU) -#define HSCMP_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Specification Number - * 0b0000000000000001..Round robin feature - */ -#define HSCMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_VERID_FEATURE_SHIFT)) & HSCMP_VERID_FEATURE_MASK) - -#define HSCMP_VERID_MINOR_MASK (0xFF0000U) -#define HSCMP_VERID_MINOR_SHIFT (16U) -/*! MINOR - Minor Version Number - */ -#define HSCMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_VERID_MINOR_SHIFT)) & HSCMP_VERID_MINOR_MASK) - -#define HSCMP_VERID_MAJOR_MASK (0xFF000000U) -#define HSCMP_VERID_MAJOR_SHIFT (24U) -/*! MAJOR - Major Version Number - */ -#define HSCMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_VERID_MAJOR_SHIFT)) & HSCMP_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ - -#define HSCMP_PARAM_DAC_RES_MASK (0xFU) -#define HSCMP_PARAM_DAC_RES_SHIFT (0U) -/*! DAC_RES - DAC Resolution - * 0b0000..4 bit DAC - * 0b0001..6 bit DAC - * 0b0010..8 bit DAC - * 0b0011..10 bit DAC - * 0b0100..12 bit DAC - * 0b0101..14 bit DAC - * 0b0110..16 bit DAC - */ -#define HSCMP_PARAM_DAC_RES(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_PARAM_DAC_RES_SHIFT)) & HSCMP_PARAM_DAC_RES_MASK) -/*! @} */ - -/*! @name CCR0 - Comparator Control Register 0 */ -/*! @{ */ - -#define HSCMP_CCR0_CMP_EN_MASK (0x1U) -#define HSCMP_CCR0_CMP_EN_SHIFT (0U) -/*! CMP_EN - Comparator Enable - * 0b0..Disable (The analog logic remains off and consumes no power.) - * 0b1..Enable - */ -#define HSCMP_CCR0_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR0_CMP_EN_SHIFT)) & HSCMP_CCR0_CMP_EN_MASK) - -#define HSCMP_CCR0_CMP_STOP_EN_MASK (0x2U) -#define HSCMP_CCR0_CMP_STOP_EN_SHIFT (1U) -/*! CMP_STOP_EN - Comparator STOP Mode Enable - * 0b0..Disable the analog comparator regardless of CMP_EN. - * 0b1..Allow the analog comparator to be enabled by CMP_EN. - */ -#define HSCMP_CCR0_CMP_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR0_CMP_STOP_EN_SHIFT)) & HSCMP_CCR0_CMP_STOP_EN_MASK) - -#define HSCMP_CCR0_LINKEN_MASK (0x4U) -#define HSCMP_CCR0_LINKEN_SHIFT (2U) -/*! LINKEN - CMP-to-DAC Link Enable - * 0b0..Disable the CMP-to-DAC link: enabling or disabling the DAC is independent from enabling or disabling the CMP. - * 0b1..Enable the CMP-to-DAC link: the DAC enable/disable is controlled by the CMP_EN bit instead of DCR[DAC_EN]. - */ -#define HSCMP_CCR0_LINKEN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR0_LINKEN_SHIFT)) & HSCMP_CCR0_LINKEN_MASK) -/*! @} */ - -/*! @name CCR1 - Comparator Control Register 1 */ -/*! @{ */ - -#define HSCMP_CCR1_WINDOW_EN_MASK (0x1U) -#define HSCMP_CCR1_WINDOW_EN_SHIFT (0U) -/*! WINDOW_EN - Windowing Enable - * 0b0..Disable - * 0b1..Enable - */ -#define HSCMP_CCR1_WINDOW_EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_WINDOW_EN_SHIFT)) & HSCMP_CCR1_WINDOW_EN_MASK) - -#define HSCMP_CCR1_SAMPLE_EN_MASK (0x2U) -#define HSCMP_CCR1_SAMPLE_EN_SHIFT (1U) -/*! SAMPLE_EN - Sampling Enable - * 0b0..Disable - * 0b1..Enable - */ -#define HSCMP_CCR1_SAMPLE_EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_SAMPLE_EN_SHIFT)) & HSCMP_CCR1_SAMPLE_EN_MASK) - -#define HSCMP_CCR1_DMA_EN_MASK (0x4U) -#define HSCMP_CCR1_DMA_EN_SHIFT (2U) -/*! DMA_EN - DMA Enable - * 0b0..Disable - * 0b1..Enable - */ -#define HSCMP_CCR1_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_DMA_EN_SHIFT)) & HSCMP_CCR1_DMA_EN_MASK) - -#define HSCMP_CCR1_COUT_INV_MASK (0x8U) -#define HSCMP_CCR1_COUT_INV_SHIFT (3U) -/*! COUT_INV - Comparator Invert - * 0b0..Do not invert - * 0b1..Invert - */ -#define HSCMP_CCR1_COUT_INV(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_COUT_INV_SHIFT)) & HSCMP_CCR1_COUT_INV_MASK) - -#define HSCMP_CCR1_COUT_SEL_MASK (0x10U) -#define HSCMP_CCR1_COUT_SEL_SHIFT (4U) -/*! COUT_SEL - Comparator Output Select - * 0b0..Use COUT (filtered) - * 0b1..Use COUTA (unfiltered) - */ -#define HSCMP_CCR1_COUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_COUT_SEL_SHIFT)) & HSCMP_CCR1_COUT_SEL_MASK) - -#define HSCMP_CCR1_COUT_PEN_MASK (0x20U) -#define HSCMP_CCR1_COUT_PEN_SHIFT (5U) -/*! COUT_PEN - Comparator Output Pin Enable - * 0b0..Not available - * 0b1..Available - */ -#define HSCMP_CCR1_COUT_PEN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_COUT_PEN_SHIFT)) & HSCMP_CCR1_COUT_PEN_MASK) - -#define HSCMP_CCR1_COUTA_OWEN_MASK (0x40U) -#define HSCMP_CCR1_COUTA_OWEN_SHIFT (6U) -/*! COUTA_OWEN - COUTA_OW Enable - * 0b0..COUTA holds the last sampled value - * 0b1..COUTA is defined by the COUTA_OW bit - */ -#define HSCMP_CCR1_COUTA_OWEN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_COUTA_OWEN_SHIFT)) & HSCMP_CCR1_COUTA_OWEN_MASK) - -#define HSCMP_CCR1_COUTA_OW_MASK (0x80U) -#define HSCMP_CCR1_COUTA_OW_SHIFT (7U) -/*! COUTA_OW - COUTA Output Level for Closed Window - * 0b0..COUTA is 0 - * 0b1..COUTA is 1 - */ -#define HSCMP_CCR1_COUTA_OW(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_COUTA_OW_SHIFT)) & HSCMP_CCR1_COUTA_OW_MASK) - -#define HSCMP_CCR1_WINDOW_INV_MASK (0x100U) -#define HSCMP_CCR1_WINDOW_INV_SHIFT (8U) -/*! WINDOW_INV - WINDOW/SAMPLE Signal Invert - * 0b0..Do not invert - * 0b1..Invert - */ -#define HSCMP_CCR1_WINDOW_INV(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_WINDOW_INV_SHIFT)) & HSCMP_CCR1_WINDOW_INV_MASK) - -#define HSCMP_CCR1_WINDOW_CLS_MASK (0x200U) -#define HSCMP_CCR1_WINDOW_CLS_SHIFT (9U) -/*! WINDOW_CLS - COUT Event Window Close - * 0b0..COUT event cannot close the window - * 0b1..COUT event can close the window - */ -#define HSCMP_CCR1_WINDOW_CLS(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_WINDOW_CLS_SHIFT)) & HSCMP_CCR1_WINDOW_CLS_MASK) - -#define HSCMP_CCR1_EVT_SEL_MASK (0xC00U) -#define HSCMP_CCR1_EVT_SEL_SHIFT (10U) -/*! EVT_SEL - COUT Event Select - * 0b00..Rising edge - * 0b01..Falling edge - * 0b1x..Both edges - */ -#define HSCMP_CCR1_EVT_SEL(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_EVT_SEL_SHIFT)) & HSCMP_CCR1_EVT_SEL_MASK) - -#define HSCMP_CCR1_FILT_CNT_MASK (0x70000U) -#define HSCMP_CCR1_FILT_CNT_SHIFT (16U) -/*! FILT_CNT - Filter Sample Count - * 0b000..Filter is bypassed: COUT = COUTA - * 0b001..1 consecutive sample (Comparator output is simply sampled.) - * 0b010..2 consecutive samples - * 0b011..3 consecutive samples - * 0b100..4 consecutive samples - * 0b101..5 consecutive samples - * 0b110..6 consecutive samples - * 0b111..7 consecutive samples - */ -#define HSCMP_CCR1_FILT_CNT(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_FILT_CNT_SHIFT)) & HSCMP_CCR1_FILT_CNT_MASK) - -#define HSCMP_CCR1_FILT_PER_MASK (0xFF000000U) -#define HSCMP_CCR1_FILT_PER_SHIFT (24U) -/*! FILT_PER - Filter Sample Period - */ -#define HSCMP_CCR1_FILT_PER(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_FILT_PER_SHIFT)) & HSCMP_CCR1_FILT_PER_MASK) -/*! @} */ - -/*! @name CCR2 - Comparator Control Register 2 */ -/*! @{ */ - -#define HSCMP_CCR2_CMP_HPMD_MASK (0x1U) -#define HSCMP_CCR2_CMP_HPMD_SHIFT (0U) -/*! CMP_HPMD - CMP High Power Mode Select - * 0b0..Low power(speed) comparison mode - * 0b1..High power(speed) comparison mode - */ -#define HSCMP_CCR2_CMP_HPMD(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_CMP_HPMD_SHIFT)) & HSCMP_CCR2_CMP_HPMD_MASK) - -#define HSCMP_CCR2_CMP_NPMD_MASK (0x2U) -#define HSCMP_CCR2_CMP_NPMD_SHIFT (1U) -/*! CMP_NPMD - CMP Nano Power Mode Select - * 0b0..Disable (Mode is determined by CMP_HPMD.) - * 0b1..Enable - */ -#define HSCMP_CCR2_CMP_NPMD(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_CMP_NPMD_SHIFT)) & HSCMP_CCR2_CMP_NPMD_MASK) - -#define HSCMP_CCR2_OFFSET_MASK (0x4U) -#define HSCMP_CCR2_OFFSET_SHIFT (2U) -/*! OFFSET - Comparator Offset Control - * 0b0..Level 0: The hysteresis selected by HYSTCTR is valid for both directions (rising and falling). - * 0b1..Level 1: Hysteresis does not apply when INP (input-plus) crosses INM (input-minus) in the rising - * direction or when INM crosses INP in the falling direction. Hysteresis still applies for INP crossing INM in the - * falling direction. - */ -#define HSCMP_CCR2_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_OFFSET_SHIFT)) & HSCMP_CCR2_OFFSET_MASK) - -#define HSCMP_CCR2_HYSTCTR_MASK (0x30U) -#define HSCMP_CCR2_HYSTCTR_SHIFT (4U) -/*! HYSTCTR - Comparator Hysteresis Control - * 0b00..Level 0 - * 0b01..Level 1 - * 0b10..Level 2 - * 0b11..Level 3 - */ -#define HSCMP_CCR2_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_HYSTCTR_SHIFT)) & HSCMP_CCR2_HYSTCTR_MASK) - -#define HSCMP_CCR2_PSEL_MASK (0x70000U) -#define HSCMP_CCR2_PSEL_SHIFT (16U) -/*! PSEL - Plus Input MUX Select - * 0b000..Input 0p - * 0b001..Input 1p - * 0b010..Input 2p - * 0b011..Input 3p - * 0b100..Input 4p - * 0b101..Input 5p - * 0b110..Reserved - * 0b111..Internal DAC output - */ -#define HSCMP_CCR2_PSEL(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_PSEL_SHIFT)) & HSCMP_CCR2_PSEL_MASK) - -#define HSCMP_CCR2_MSEL_MASK (0x700000U) -#define HSCMP_CCR2_MSEL_SHIFT (20U) -/*! MSEL - Minus Input MUX Select - * 0b000..Input 0m - * 0b001..Input 1m - * 0b010..Input 2m - * 0b011..Input 3m - * 0b100..Input 4m - * 0b101..Input 5m - * 0b110..Reserved - * 0b111..Internal DAC output - */ -#define HSCMP_CCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_MSEL_SHIFT)) & HSCMP_CCR2_MSEL_MASK) - -#define HSCMP_CCR2_INPSEL_MASK (0x3000000U) -#define HSCMP_CCR2_INPSEL_SHIFT (24U) -/*! INPSEL - Input Plus Select - * 0b00..IN0: from the 8-bit DAC output - * 0b01..IN1: from the analog 8-1 mux - * 0b10..Reserved - * 0b11..Reserved - */ -#define HSCMP_CCR2_INPSEL(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_INPSEL_SHIFT)) & HSCMP_CCR2_INPSEL_MASK) - -#define HSCMP_CCR2_INMSEL_MASK (0x30000000U) -#define HSCMP_CCR2_INMSEL_SHIFT (28U) -/*! INMSEL - Input Minus Select - * 0b00..IN0: from the 8-bit DAC output - * 0b01..IN1: from the analog 8-1 mux - * 0b10..Reserved - * 0b11..Reserved - */ -#define HSCMP_CCR2_INMSEL(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_INMSEL_SHIFT)) & HSCMP_CCR2_INMSEL_MASK) -/*! @} */ - -/*! @name DCR - DAC Control Register */ -/*! @{ */ - -#define HSCMP_DCR_DAC_EN_MASK (0x1U) -#define HSCMP_DCR_DAC_EN_SHIFT (0U) -/*! DAC_EN - DAC Enable - * 0b0..Disable - * 0b1..Enable - */ -#define HSCMP_DCR_DAC_EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_DCR_DAC_EN_SHIFT)) & HSCMP_DCR_DAC_EN_MASK) - -#define HSCMP_DCR_DAC_HPMD_MASK (0x2U) -#define HSCMP_DCR_DAC_HPMD_SHIFT (1U) -/*! DAC_HPMD - DAC High Power Mode Select - * 0b0..Disable - * 0b1..Enable - */ -#define HSCMP_DCR_DAC_HPMD(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_DCR_DAC_HPMD_SHIFT)) & HSCMP_DCR_DAC_HPMD_MASK) - -#define HSCMP_DCR_VRSEL_MASK (0x100U) -#define HSCMP_DCR_VRSEL_SHIFT (8U) -/*! VRSEL - DAC Reference High Voltage Source Select - * 0b0..vrefh0 - * 0b1..vrefh1 - */ -#define HSCMP_DCR_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_DCR_VRSEL_SHIFT)) & HSCMP_DCR_VRSEL_MASK) - -#define HSCMP_DCR_DACOE_MASK (0x8000U) -#define HSCMP_DCR_DACOE_SHIFT (15U) -/*! DACOE - DAC Output Enable - * 0b0..Disable - * 0b1..Enable - */ -#define HSCMP_DCR_DACOE(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_DCR_DACOE_SHIFT)) & HSCMP_DCR_DACOE_MASK) - -#define HSCMP_DCR_DAC_DATA_MASK (0xFF0000U) -#define HSCMP_DCR_DAC_DATA_SHIFT (16U) -/*! DAC_DATA - DAC Output Voltage Select - */ -#define HSCMP_DCR_DAC_DATA(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_DCR_DAC_DATA_SHIFT)) & HSCMP_DCR_DAC_DATA_MASK) -/*! @} */ - -/*! @name IER - Interrupt Enable Register */ -/*! @{ */ - -#define HSCMP_IER_CFR_IE_MASK (0x1U) -#define HSCMP_IER_CFR_IE_SHIFT (0U) -/*! CFR_IE - Comparator Flag Rising Interrupt Enable - * 0b0..Disable - * 0b1..Enable: Assert an interrupt when CFR is set. - */ -#define HSCMP_IER_CFR_IE(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_IER_CFR_IE_SHIFT)) & HSCMP_IER_CFR_IE_MASK) - -#define HSCMP_IER_CFF_IE_MASK (0x2U) -#define HSCMP_IER_CFF_IE_SHIFT (1U) -/*! CFF_IE - Comparator Flag Falling Interrupt Enable - * 0b0..Disable - * 0b1..Enable: Assert an interrupt when CFF is set. - */ -#define HSCMP_IER_CFF_IE(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_IER_CFF_IE_SHIFT)) & HSCMP_IER_CFF_IE_MASK) - -#define HSCMP_IER_RRF_IE_MASK (0x4U) -#define HSCMP_IER_RRF_IE_SHIFT (2U) -/*! RRF_IE - Round-Robin Flag Interrupt Enable - * 0b0..Disable - * 0b1..Enable: Assert an interrupt when the comparison result changes for a given channel. - */ -#define HSCMP_IER_RRF_IE(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_IER_RRF_IE_SHIFT)) & HSCMP_IER_RRF_IE_MASK) -/*! @} */ - -/*! @name CSR - Comparator Status Register */ -/*! @{ */ - -#define HSCMP_CSR_CFR_MASK (0x1U) -#define HSCMP_CSR_CFR_SHIFT (0U) -/*! CFR - Analog Comparator Flag Rising - * 0b0..Not detected - * 0b1..Detected - */ -#define HSCMP_CSR_CFR(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CSR_CFR_SHIFT)) & HSCMP_CSR_CFR_MASK) - -#define HSCMP_CSR_CFF_MASK (0x2U) -#define HSCMP_CSR_CFF_SHIFT (1U) -/*! CFF - Analog Comparator Flag Falling - * 0b0..Not detected - * 0b1..Detected - */ -#define HSCMP_CSR_CFF(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CSR_CFF_SHIFT)) & HSCMP_CSR_CFF_MASK) - -#define HSCMP_CSR_RRF_MASK (0x4U) -#define HSCMP_CSR_RRF_SHIFT (2U) -/*! RRF - Round-Robin Flag - * 0b0..Not detected - * 0b1..Detected - */ -#define HSCMP_CSR_RRF(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CSR_RRF_SHIFT)) & HSCMP_CSR_RRF_MASK) - -#define HSCMP_CSR_COUT_MASK (0x100U) -#define HSCMP_CSR_COUT_SHIFT (8U) -/*! COUT - Analog Comparator Output - */ -#define HSCMP_CSR_COUT(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CSR_COUT_SHIFT)) & HSCMP_CSR_COUT_MASK) -/*! @} */ - -/*! @name RRCR0 - Round Robin Control Register 0 */ -/*! @{ */ - -#define HSCMP_RRCR0_RR_EN_MASK (0x1U) -#define HSCMP_RRCR0_RR_EN_SHIFT (0U) -/*! RR_EN - Round-Robin Enable - * 0b1..Enable - * 0b0..Disable - */ -#define HSCMP_RRCR0_RR_EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR0_RR_EN_SHIFT)) & HSCMP_RRCR0_RR_EN_MASK) - -#define HSCMP_RRCR0_RR_NSAM_MASK (0x300U) -#define HSCMP_RRCR0_RR_NSAM_SHIFT (8U) -/*! RR_NSAM - Number of Sample Clocks - * 0b00..0 clocks - * 0b01..1 clocks - * 0b10..2 clocks - * 0b11..3 clocks - */ -#define HSCMP_RRCR0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR0_RR_NSAM_SHIFT)) & HSCMP_RRCR0_RR_NSAM_MASK) - -#define HSCMP_RRCR0_RR_INITMOD_MASK (0x3F0000U) -#define HSCMP_RRCR0_RR_INITMOD_SHIFT (16U) -/*! RR_INITMOD - Initialization Delay Modulus - * 0b000000..63 cycles (same as 111111b) - * 0b000001-0b111111..1 to 63 cycles - */ -#define HSCMP_RRCR0_RR_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR0_RR_INITMOD_SHIFT)) & HSCMP_RRCR0_RR_INITMOD_MASK) -/*! @} */ - -/*! @name RRCR1 - Round Robin Control Register 1 */ -/*! @{ */ - -#define HSCMP_RRCR1_RR_CH0EN_MASK (0x1U) -#define HSCMP_RRCR1_RR_CH0EN_SHIFT (0U) -/*! RR_CH0EN - Channel 0 Input Enable in Trigger Mode - * 0b1..Enable - * 0b0..Disable - */ -#define HSCMP_RRCR1_RR_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH0EN_SHIFT)) & HSCMP_RRCR1_RR_CH0EN_MASK) - -#define HSCMP_RRCR1_RR_CH1EN_MASK (0x2U) -#define HSCMP_RRCR1_RR_CH1EN_SHIFT (1U) -/*! RR_CH1EN - Channel 1 Input Enable in Trigger Mode - * 0b1..Enable - * 0b0..Disable - */ -#define HSCMP_RRCR1_RR_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH1EN_SHIFT)) & HSCMP_RRCR1_RR_CH1EN_MASK) - -#define HSCMP_RRCR1_RR_CH2EN_MASK (0x4U) -#define HSCMP_RRCR1_RR_CH2EN_SHIFT (2U) -/*! RR_CH2EN - Channel 2 Input Enable in Trigger Mode - * 0b1..Enable - * 0b0..Disable - */ -#define HSCMP_RRCR1_RR_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH2EN_SHIFT)) & HSCMP_RRCR1_RR_CH2EN_MASK) - -#define HSCMP_RRCR1_RR_CH3EN_MASK (0x8U) -#define HSCMP_RRCR1_RR_CH3EN_SHIFT (3U) -/*! RR_CH3EN - Channel 3 Input Enable in Trigger Mode - * 0b1..Enable - * 0b0..Disable - */ -#define HSCMP_RRCR1_RR_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH3EN_SHIFT)) & HSCMP_RRCR1_RR_CH3EN_MASK) - -#define HSCMP_RRCR1_RR_CH4EN_MASK (0x10U) -#define HSCMP_RRCR1_RR_CH4EN_SHIFT (4U) -/*! RR_CH4EN - Channel 4 Input Enable in Trigger Mode - * 0b1..Enable - * 0b0..Disable - */ -#define HSCMP_RRCR1_RR_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH4EN_SHIFT)) & HSCMP_RRCR1_RR_CH4EN_MASK) - -#define HSCMP_RRCR1_RR_CH5EN_MASK (0x20U) -#define HSCMP_RRCR1_RR_CH5EN_SHIFT (5U) -/*! RR_CH5EN - Channel 5 Input Enable in Trigger Mode - * 0b1..Enable - * 0b0..Disable - */ -#define HSCMP_RRCR1_RR_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH5EN_SHIFT)) & HSCMP_RRCR1_RR_CH5EN_MASK) - -#define HSCMP_RRCR1_RR_CH6EN_MASK (0x40U) -#define HSCMP_RRCR1_RR_CH6EN_SHIFT (6U) -/*! RR_CH6EN - Channel 6 Input Enable in Trigger Mode - * 0b1..Enable - * 0b0..Disable - */ -#define HSCMP_RRCR1_RR_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH6EN_SHIFT)) & HSCMP_RRCR1_RR_CH6EN_MASK) - -#define HSCMP_RRCR1_RR_CH7EN_MASK (0x80U) -#define HSCMP_RRCR1_RR_CH7EN_SHIFT (7U) -/*! RR_CH7EN - Channel 7 Input Enable in Trigger Mode - * 0b1..Enable - * 0b0..Disable - */ -#define HSCMP_RRCR1_RR_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH7EN_SHIFT)) & HSCMP_RRCR1_RR_CH7EN_MASK) - -#define HSCMP_RRCR1_FIXP_MASK (0x10000U) -#define HSCMP_RRCR1_FIXP_SHIFT (16U) -/*! FIXP - Fixed Port - * 0b0..Fix the Plus port. Sweep only the inputs to the Minus port. - * 0b1..Fix the Minus port. Sweep only the inputs to the Plus port. - */ -#define HSCMP_RRCR1_FIXP(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_FIXP_SHIFT)) & HSCMP_RRCR1_FIXP_MASK) - -#define HSCMP_RRCR1_FIXCH_MASK (0x700000U) -#define HSCMP_RRCR1_FIXCH_SHIFT (20U) -/*! FIXCH - Fixed Channel Select - * 0b000..Channel 0 - * 0b001..Channel 1 - * 0b010..Channel 2 - * 0b011..Channel 3 - * 0b100..Channel 4 - * 0b101..Channel 5 - * 0b110..Channel 6 - * 0b111..Channel 7 - */ -#define HSCMP_RRCR1_FIXCH(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_FIXCH_SHIFT)) & HSCMP_RRCR1_FIXCH_MASK) -/*! @} */ - -/*! @name RRCSR - Round Robin Control and Status Register */ -/*! @{ */ - -#define HSCMP_RRCSR_RR_CH0OUT_MASK (0x1U) -#define HSCMP_RRCSR_RR_CH0OUT_SHIFT (0U) -/*! RR_CH0OUT - Comparison Result for Channel 0 - */ -#define HSCMP_RRCSR_RR_CH0OUT(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH0OUT_SHIFT)) & HSCMP_RRCSR_RR_CH0OUT_MASK) - -#define HSCMP_RRCSR_RR_CH1OUT_MASK (0x2U) -#define HSCMP_RRCSR_RR_CH1OUT_SHIFT (1U) -/*! RR_CH1OUT - Comparison Result for Channel 1 - */ -#define HSCMP_RRCSR_RR_CH1OUT(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH1OUT_SHIFT)) & HSCMP_RRCSR_RR_CH1OUT_MASK) - -#define HSCMP_RRCSR_RR_CH2OUT_MASK (0x4U) -#define HSCMP_RRCSR_RR_CH2OUT_SHIFT (2U) -/*! RR_CH2OUT - Comparison Result for Channel 2 - */ -#define HSCMP_RRCSR_RR_CH2OUT(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH2OUT_SHIFT)) & HSCMP_RRCSR_RR_CH2OUT_MASK) - -#define HSCMP_RRCSR_RR_CH3OUT_MASK (0x8U) -#define HSCMP_RRCSR_RR_CH3OUT_SHIFT (3U) -/*! RR_CH3OUT - Comparison Result for Channel 3 - */ -#define HSCMP_RRCSR_RR_CH3OUT(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH3OUT_SHIFT)) & HSCMP_RRCSR_RR_CH3OUT_MASK) - -#define HSCMP_RRCSR_RR_CH4OUT_MASK (0x10U) -#define HSCMP_RRCSR_RR_CH4OUT_SHIFT (4U) -/*! RR_CH4OUT - Comparison Result for Channel 4 - */ -#define HSCMP_RRCSR_RR_CH4OUT(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH4OUT_SHIFT)) & HSCMP_RRCSR_RR_CH4OUT_MASK) - -#define HSCMP_RRCSR_RR_CH5OUT_MASK (0x20U) -#define HSCMP_RRCSR_RR_CH5OUT_SHIFT (5U) -/*! RR_CH5OUT - Comparison Result for Channel 5 - */ -#define HSCMP_RRCSR_RR_CH5OUT(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH5OUT_SHIFT)) & HSCMP_RRCSR_RR_CH5OUT_MASK) - -#define HSCMP_RRCSR_RR_CH6OUT_MASK (0x40U) -#define HSCMP_RRCSR_RR_CH6OUT_SHIFT (6U) -/*! RR_CH6OUT - Comparison Result for Channel 6 - */ -#define HSCMP_RRCSR_RR_CH6OUT(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH6OUT_SHIFT)) & HSCMP_RRCSR_RR_CH6OUT_MASK) - -#define HSCMP_RRCSR_RR_CH7OUT_MASK (0x80U) -#define HSCMP_RRCSR_RR_CH7OUT_SHIFT (7U) -/*! RR_CH7OUT - Comparison Result for Channel 7 - */ -#define HSCMP_RRCSR_RR_CH7OUT(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH7OUT_SHIFT)) & HSCMP_RRCSR_RR_CH7OUT_MASK) -/*! @} */ - -/*! @name RRSR - Round Robin Status Register */ -/*! @{ */ - -#define HSCMP_RRSR_RR_CH0F_MASK (0x1U) -#define HSCMP_RRSR_RR_CH0F_SHIFT (0U) -/*! RR_CH0F - Channel 0 Input Changed Flag - * 0b0..Not different - * 0b1..Different - */ -#define HSCMP_RRSR_RR_CH0F(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH0F_SHIFT)) & HSCMP_RRSR_RR_CH0F_MASK) - -#define HSCMP_RRSR_RR_CH1F_MASK (0x2U) -#define HSCMP_RRSR_RR_CH1F_SHIFT (1U) -/*! RR_CH1F - Channel 1 Input Changed Flag - * 0b0..Not different - * 0b1..Different - */ -#define HSCMP_RRSR_RR_CH1F(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH1F_SHIFT)) & HSCMP_RRSR_RR_CH1F_MASK) - -#define HSCMP_RRSR_RR_CH2F_MASK (0x4U) -#define HSCMP_RRSR_RR_CH2F_SHIFT (2U) -/*! RR_CH2F - Channel 2 Input Changed Flag - * 0b0..Not different - * 0b1..Different - */ -#define HSCMP_RRSR_RR_CH2F(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH2F_SHIFT)) & HSCMP_RRSR_RR_CH2F_MASK) - -#define HSCMP_RRSR_RR_CH3F_MASK (0x8U) -#define HSCMP_RRSR_RR_CH3F_SHIFT (3U) -/*! RR_CH3F - Channel 3 Input Changed Flag - * 0b0..Not different - * 0b1..Different - */ -#define HSCMP_RRSR_RR_CH3F(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH3F_SHIFT)) & HSCMP_RRSR_RR_CH3F_MASK) - -#define HSCMP_RRSR_RR_CH4F_MASK (0x10U) -#define HSCMP_RRSR_RR_CH4F_SHIFT (4U) -/*! RR_CH4F - Channel 4 Input Changed Flag - * 0b0..Not different - * 0b1..Different - */ -#define HSCMP_RRSR_RR_CH4F(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH4F_SHIFT)) & HSCMP_RRSR_RR_CH4F_MASK) - -#define HSCMP_RRSR_RR_CH5F_MASK (0x20U) -#define HSCMP_RRSR_RR_CH5F_SHIFT (5U) -/*! RR_CH5F - Channel 5 Input Changed Flag - * 0b0..Not different - * 0b1..Different - */ -#define HSCMP_RRSR_RR_CH5F(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH5F_SHIFT)) & HSCMP_RRSR_RR_CH5F_MASK) - -#define HSCMP_RRSR_RR_CH6F_MASK (0x40U) -#define HSCMP_RRSR_RR_CH6F_SHIFT (6U) -/*! RR_CH6F - Channel 6 Input Changed Flag - * 0b0..Not different - * 0b1..Different - */ -#define HSCMP_RRSR_RR_CH6F(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH6F_SHIFT)) & HSCMP_RRSR_RR_CH6F_MASK) - -#define HSCMP_RRSR_RR_CH7F_MASK (0x80U) -#define HSCMP_RRSR_RR_CH7F_SHIFT (7U) -/*! RR_CH7F - Channel 7 Input Changed Flag - * 0b0..Not different - * 0b1..Different - */ -#define HSCMP_RRSR_RR_CH7F(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH7F_SHIFT)) & HSCMP_RRSR_RR_CH7F_MASK) -/*! @} */ - -/*! @name RRCR2 - Round Robin Control Register 2 */ -/*! @{ */ - -#define HSCMP_RRCR2_RR_TIMER_RELOAD_MASK (0xFFFFFFFU) -#define HSCMP_RRCR2_RR_TIMER_RELOAD_SHIFT (0U) -/*! RR_TIMER_RELOAD - Number of sample clocks - */ -#define HSCMP_RRCR2_RR_TIMER_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR2_RR_TIMER_RELOAD_SHIFT)) & HSCMP_RRCR2_RR_TIMER_RELOAD_MASK) - -#define HSCMP_RRCR2_RR_TIMER_EN_MASK (0x80000000U) -#define HSCMP_RRCR2_RR_TIMER_EN_SHIFT (31U) -/*! RR_TIMER_EN - Round-Robin internal timer enable. - * 0b0..Round-Robin internal timer is disabled. - * 0b1..Round-Robin internal timer is enabled. - */ -#define HSCMP_RRCR2_RR_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR2_RR_TIMER_EN_SHIFT)) & HSCMP_RRCR2_RR_TIMER_EN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group HSCMP_Register_Masks */ - - -/* HSCMP - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral HSCMP0 base address */ - #define HSCMP0_BASE (0x500B3000u) - /** Peripheral HSCMP0 base address */ - #define HSCMP0_BASE_NS (0x400B3000u) - /** Peripheral HSCMP0 base pointer */ - #define HSCMP0 ((HSCMP_Type *)HSCMP0_BASE) - /** Peripheral HSCMP0 base pointer */ - #define HSCMP0_NS ((HSCMP_Type *)HSCMP0_BASE_NS) - /** Peripheral HSCMP1 base address */ - #define HSCMP1_BASE (0x500B7000u) - /** Peripheral HSCMP1 base address */ - #define HSCMP1_BASE_NS (0x400B7000u) - /** Peripheral HSCMP1 base pointer */ - #define HSCMP1 ((HSCMP_Type *)HSCMP1_BASE) - /** Peripheral HSCMP1 base pointer */ - #define HSCMP1_NS ((HSCMP_Type *)HSCMP1_BASE_NS) - /** Peripheral HSCMP2 base address */ - #define HSCMP2_BASE (0x500BA000u) - /** Peripheral HSCMP2 base address */ - #define HSCMP2_BASE_NS (0x400BA000u) - /** Peripheral HSCMP2 base pointer */ - #define HSCMP2 ((HSCMP_Type *)HSCMP2_BASE) - /** Peripheral HSCMP2 base pointer */ - #define HSCMP2_NS ((HSCMP_Type *)HSCMP2_BASE_NS) - /** Array initializer of HSCMP peripheral base addresses */ - #define HSCMP_BASE_ADDRS { HSCMP0_BASE, HSCMP1_BASE, HSCMP2_BASE } - /** Array initializer of HSCMP peripheral base pointers */ - #define HSCMP_BASE_PTRS { HSCMP0, HSCMP1, HSCMP2 } - /** Array initializer of HSCMP peripheral base addresses */ - #define HSCMP_BASE_ADDRS_NS { HSCMP0_BASE_NS, HSCMP1_BASE_NS, HSCMP2_BASE_NS } - /** Array initializer of HSCMP peripheral base pointers */ - #define HSCMP_BASE_PTRS_NS { HSCMP0_NS, HSCMP1_NS, HSCMP2_NS } -#else - /** Peripheral HSCMP0 base address */ - #define HSCMP0_BASE (0x400B3000u) - /** Peripheral HSCMP0 base pointer */ - #define HSCMP0 ((HSCMP_Type *)HSCMP0_BASE) - /** Peripheral HSCMP1 base address */ - #define HSCMP1_BASE (0x400B7000u) - /** Peripheral HSCMP1 base pointer */ - #define HSCMP1 ((HSCMP_Type *)HSCMP1_BASE) - /** Peripheral HSCMP2 base address */ - #define HSCMP2_BASE (0x400BA000u) - /** Peripheral HSCMP2 base pointer */ - #define HSCMP2 ((HSCMP_Type *)HSCMP2_BASE) - /** Array initializer of HSCMP peripheral base addresses */ - #define HSCMP_BASE_ADDRS { HSCMP0_BASE, HSCMP1_BASE, HSCMP2_BASE } - /** Array initializer of HSCMP peripheral base pointers */ - #define HSCMP_BASE_PTRS { HSCMP0, HSCMP1, HSCMP2 } -#endif -/** Interrupt vectors for the HSCMP peripheral type */ -#define HSCMP_IRQS { HSCMP0_IRQn, HSCMP1_IRQn, HSCMP2_IRQn } - -/*! - * @} - */ /* end of group HSCMP_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2C Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer - * @{ - */ - -/** I2C - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[2048]; - __IO uint32_t CFG; /**< Configuration Register, offset: 0x800 */ - __IO uint32_t STAT; /**< Status Register, offset: 0x804 */ - __IO uint32_t INTENSET; /**< Interrupt Enable Set Register, offset: 0x808 */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear Register, offset: 0x80C */ - __IO uint32_t TIMEOUT; /**< Time-out Register, offset: 0x810 */ - __IO uint32_t CLKDIV; /**< Clock Divider Register, offset: 0x814 */ - __I uint32_t INTSTAT; /**< Interrupt Status Register, offset: 0x818 */ - uint8_t RESERVED_1[4]; - __IO uint32_t MSTCTL; /**< Master Control Register, offset: 0x820 */ - __IO uint32_t MSTTIME; /**< Master Timing Register, offset: 0x824 */ - __IO uint32_t MSTDAT; /**< Master Data Register, offset: 0x828 */ - uint8_t RESERVED_2[20]; - __IO uint32_t SLVCTL; /**< Slave Control Register, offset: 0x840 */ - __IO uint32_t SLVDAT; /**< Slave Data Register, offset: 0x844 */ - __IO uint32_t SLVADR[4]; /**< Slave Address Register, array offset: 0x848, array step: 0x4 */ - __IO uint32_t SLVQUAL0; /**< Slave Qualification for Address 0 Register, offset: 0x858 */ - uint8_t RESERVED_3[36]; - __I uint32_t MONRXDAT; /**< Monitor Receiver Data Register, offset: 0x880 */ - uint8_t RESERVED_4[1912]; - __I uint32_t ID; /**< Peripheral Identification Register, offset: 0xFFC */ -} I2C_Type; - -/* ---------------------------------------------------------------------------- - -- I2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Register_Masks I2C Register Masks - * @{ - */ - -/*! @name CFG - Configuration Register */ -/*! @{ */ - -#define I2C_CFG_MSTEN_MASK (0x1U) -#define I2C_CFG_MSTEN_SHIFT (0U) -/*! MSTEN - Master Enable - * 0b0..Disabled. The I2C Master function is disabled. When disabled, the Master configuration settings are not - * changed, but the Master function is internally reset. - * 0b1..Enabled. The I2C Master function is enabled. - */ -#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) - -#define I2C_CFG_SLVEN_MASK (0x2U) -#define I2C_CFG_SLVEN_SHIFT (1U) -/*! SLVEN - Slave Enable - * 0b0..Disabled. The I2C slave function is disabled. When disabled, the Slave configuration settings are not - * changed, but the Slave function is internally reset. - * 0b1..Enabled. The I2C slave function is enabled. - */ -#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) - -#define I2C_CFG_MONEN_MASK (0x4U) -#define I2C_CFG_MONEN_SHIFT (2U) -/*! MONEN - Monitor Enable - * 0b0..Disabled. The I2C Monitor function is disabled. When disabled, the Monitor function configuration - * settings are not changed, but the Monitor function is internally reset. - * 0b1..Enabled. The I2C Monitor function is enabled. - */ -#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) - -#define I2C_CFG_TIMEOUTEN_MASK (0x8U) -#define I2C_CFG_TIMEOUTEN_SHIFT (3U) -/*! TIMEOUTEN - I2C bus Time-out Enable - * 0b0..Disabled. The time-out function is disabled. When disabled, the time-out function is internally reset. - * 0b1..Enabled. The time-out function is enabled. Both types of time-out flags will be generated and will cause - * interrupts if those flags are enabled. Typically, only one time-out flag will be used in a system. - */ -#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) - -#define I2C_CFG_MONCLKSTR_MASK (0x10U) -#define I2C_CFG_MONCLKSTR_SHIFT (4U) -/*! MONCLKSTR - Monitor function Clock Stretching - * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able - * to read data provided by the Monitor function before it (the data) is overwritten. This mode can be used - * when non-invasive monitoring is critical. - * 0b1..Enabled. The Monitor function will perform clock stretching, to ensure that the software or DMA can read - * all incoming data supplied by the Monitor function. - */ -#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) - -#define I2C_CFG_HSCAPABLE_MASK (0x20U) -#define I2C_CFG_HSCAPABLE_SHIFT (5U) -/*! HSCAPABLE - High Speed mode Capable enable - * 0b0..Fast mode Plus enable - * 0b1..High Speed mode enable - */ -#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) -/*! @} */ - -/*! @name STAT - Status Register */ -/*! @{ */ - -#define I2C_STAT_MSTPENDING_MASK (0x1U) -#define I2C_STAT_MSTPENDING_SHIFT (0U) -/*! MSTPENDING - Master Pending - * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. - * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the - * idle state, then the master is waiting to receive or transmit data, or is waiting for the NACK bit. - */ -#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) - -#define I2C_STAT_MSTSTATE_MASK (0xEU) -#define I2C_STAT_MSTSTATE_SHIFT (1U) -/*! MSTSTATE - Master State code - * 0b000..Idle. The Master function is available to be used for a new transaction. - * 0b001..Receive ready. Received data is available (in Master Receiver mode). Address plus Read was previously sent and Acknowledged by a slave. - * 0b010..Transmit ready. Data can be transmitted (in Master Transmitter mode). Address plus Write was previously sent and Acknowledged by a slave. - * 0b011..NACK Address. Slave NACKed address. - * 0b100..NACK Data. Slave NACKed transmitted data. - */ -#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) - -#define I2C_STAT_MSTARBLOSS_MASK (0x10U) -#define I2C_STAT_MSTARBLOSS_SHIFT (4U) -/*! MSTARBLOSS - Master Arbitration Loss flag - * 0b0..No Arbitration Loss has occurred - * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master - * function has already stopped driving the bus and has gone into an idle state. Software can respond by doing - * nothing, or by sending a Start (to attempt to gain control of the bus when the bus next becomes idle). - */ -#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) - -#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) -/*! MSTSTSTPERR - Master Start/Stop Error flag - * 0b0..No Start/Stop Error has occurred. - * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when Start - * or Stop is not allowed by the I2C specification. The Master interface has stopped driving the bus and - * gone into an idle state; no action is required. A request for a Start could be made, or software could - * attempt to make sure that the bus has not stalled. - */ -#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) - -#define I2C_STAT_SLVPENDING_MASK (0x100U) -#define I2C_STAT_SLVPENDING_SHIFT (8U) -/*! SLVPENDING - Slave Pending - * 0b0..In progress. The Slave function does not currently need software service. - * 0b1..Pending. The Slave function needs software service. Information about what is needed is in the Slave state field (SLVSTATE). - */ -#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) - -#define I2C_STAT_SLVSTATE_MASK (0x600U) -#define I2C_STAT_SLVSTATE_SHIFT (9U) -/*! SLVSTATE - Slave State - * 0b00..Slave address. Address plus R/W received. At least one of the 4 slave addresses has been matched by hardware. - * 0b01..Slave receive. Received data is available (in Slave Receiver mode). - * 0b10..Slave transmit. Data can be transmitted (in Slave Transmitter mode). - * 0b11..Reserved - */ -#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) - -#define I2C_STAT_SLVNOTSTR_MASK (0x800U) -#define I2C_STAT_SLVNOTSTR_SHIFT (11U) -/*! SLVNOTSTR - Slave Not Stretching - * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleepmode cannot be entered at this time. - * 0b1..Not stretching. The slave function is not currently stretching the I2C bus clock. Deep-sleep mode can be entered at this time. - */ -#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) - -#define I2C_STAT_SLVIDX_MASK (0x3000U) -#define I2C_STAT_SLVIDX_SHIFT (12U) -/*! SLVIDX - Slave address match Index T - * 0b00..Address 0. Slave address 0 was matched. - * 0b01..Address 1. Slave address 1 was matched. - * 0b10..Address 2. Slave address 2 was matched. - * 0b11..Address 3. Slave address 3 was matched. - */ -#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) - -#define I2C_STAT_SLVSEL_MASK (0x4000U) -#define I2C_STAT_SLVSEL_SHIFT (14U) -/*! SLVSEL - Slave selected flag - * 0b0..Not selected. The Slave function is not currently selected. - * 0b1..Selected. The Slave function is currently selected. - */ -#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) - -#define I2C_STAT_SLVDESEL_MASK (0x8000U) -#define I2C_STAT_SLVDESEL_SHIFT (15U) -/*! SLVDESEL - Slave Deselected flag - * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that the Slave is - * currently selected. That information is in the SLVSEL flag. - * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag - * changing from 1 to 0. See SLVSEL for details about when that event occurs. - */ -#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) - -#define I2C_STAT_MONRDY_MASK (0x10000U) -#define I2C_STAT_MONRDY_SHIFT (16U) -/*! MONRDY - Monitor Ready - * 0b0..No data. The Monitor function does not currently have data available. - * 0b1..Data waiting. The Monitor function has data waiting to be read. - */ -#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) - -#define I2C_STAT_MONOV_MASK (0x20000U) -#define I2C_STAT_MONOV_SHIFT (17U) -/*! MONOV - Monitor Overflow flag - * 0b0..No overrun. Monitor data has not overrun. - * 0b1..Overrun. A Monitor data overrun has occurred. An overrun can only happen when Monitor clock stretching - * not enabled via the CFG[MONCLKSTR] bit. Writing 1 to MONOV bit clears the MONOV flag. - */ -#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) - -#define I2C_STAT_MONACTIVE_MASK (0x40000U) -#define I2C_STAT_MONACTIVE_SHIFT (18U) -/*! MONACTIVE - Monitor Active flag - * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. - * 0b1..Active. The Monitor function considers the I2C bus to be active. - */ -#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) - -#define I2C_STAT_MONIDLE_MASK (0x80000U) -#define I2C_STAT_MONIDLE_SHIFT (19U) -/*! MONIDLE - Monitor Idle flag - * 0b0..Not idle. The I2C bus is not idle, or MONIDLE flag has been cleared by software. - * 0b1..Idle. The I2C bus has gone idle at least once, since the last time MONIDLE flag was cleared by software. - */ -#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) - -#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) -/*! EVENTTIMEOUT - Event Time-out Interrupt flag - * 0b0..No time-out. I2C bus events have not caused a time-out. - * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. - */ -#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) - -#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) -/*! SCLTIMEOUT - SCL Time-out Interrupt flag - * 0b0..No time-out. SCL low time has not caused a time-out. - * 0b1..Time-out. SCL low time has caused a time-out. - */ -#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable Set Register */ -/*! @{ */ - -#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) -#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) -/*! MSTPENDINGEN - Master Pending interrupt Enable - * 0b0..Disabled. The MstPending interrupt is disabled. - * 0b1..Enabled. The MstPending interrupt is enabled. - */ -#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) - -#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) -#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) -/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable - * 0b0..Disabled. The MstArbLoss interrupt is disabled. - * 0b1..Enabled. The MstArbLoss interrupt is enabled. - */ -#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) - -#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) -#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) -/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable - * 0b0..Disabled. The MstStStpErr interrupt is disabled. - * 0b1..Enabled. The MstStStpErr interrupt is enabled. - */ -#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) - -#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) -#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) -/*! SLVPENDINGEN - Slave Pending interrupt Enable - * 0b0..Disabled. The SlvPending interrupt is disabled. - * 0b1..Enabled. The SlvPending interrupt is enabled. - */ -#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) - -#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) -#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) -/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable - * 0b0..Disabled. The SlvNotStr interrupt is disabled. - * 0b1..Enabled. The SlvNotStr interrupt is enabled. - */ -#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) - -#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) -#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) -/*! SLVDESELEN - Slave Deselect interrupt Enable - * 0b0..Disabled. The SlvDeSel interrupt is disabled. - * 0b1..Enabled. The SlvDeSel interrupt is enabled. - */ -#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) - -#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) -#define I2C_INTENSET_MONRDYEN_SHIFT (16U) -/*! MONRDYEN - Monitor data Ready interrupt Enable - * 0b0..Disabled. The MonRdy interrupt is disabled. - * 0b1..Enabled. The MonRdy interrupt is enabled. - */ -#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) - -#define I2C_INTENSET_MONOVEN_MASK (0x20000U) -#define I2C_INTENSET_MONOVEN_SHIFT (17U) -/*! MONOVEN - Monitor Overrun interrupt Enable - * 0b0..Disabled. The MonOv interrupt is disabled. - * 0b1..Enabled. The MonOv interrupt is enabled. - */ -#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) - -#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) -#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) -/*! MONIDLEEN - Monitor Idle interrupt Enable - * 0b0..Disabled. The MonIdle interrupt is disabled. - * 0b1..Enabled. The MonIdle interrupt is enabled. - */ -#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) - -#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) -#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) -/*! EVENTTIMEOUTEN - Event Time-out interrupt Enable - * 0b0..Disabled. The Event time-out interrupt is disabled. - * 0b1..Enabled. The Event time-out interrupt is enabled. - */ -#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) - -#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) -#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) -/*! SCLTIMEOUTEN - SCL Time-out interrupt Enable - * 0b0..Disabled. The SCL time-out interrupt is disabled. - * 0b1..Enabled. The SCL time-out interrupt is enabled. - */ -#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear Register */ -/*! @{ */ - -#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) -#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) -/*! MSTPENDINGCLR - Master Pending interrupt clear - * 0b0..No effect on interrupt - * 0b1..Clears the interrupt bit in INTENSET register - */ -#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) - -#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) -#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) -/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear - * 0b0..No effect on interrupt - * 0b1..Clears the interrupt bit in INTENSET register - */ -#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) - -#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) -#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) -/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear - * 0b0..No effect on interrupt - * 0b1..Clears the interrupt bit in INTENSET register - */ -#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) - -#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) -#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) -/*! SLVPENDINGCLR - Slave Pending interrupt clear - * 0b0..No effect on interrupt - * 0b1..Clears the interrupt bit in INTENSET register - */ -#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) - -#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) -#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) -/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear - * 0b0..No effect on interrupt - * 0b1..Clears the interrupt bit in INTENSET register - */ -#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) - -#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) -#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) -/*! SLVDESELCLR - Slave Deselect interrupt clear - * 0b0..No effect on interrupt - * 0b1..Clears the interrupt bit in INTENSET register - */ -#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) - -#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) -#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) -/*! MONRDYCLR - Monitor data Ready interrupt clear - * 0b0..No effect on interrupt - * 0b1..Clears the interrupt bit in INTENSET register - */ -#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) - -#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) -#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) -/*! MONOVCLR - Monitor Overrun interrupt clear - * 0b0..No effect on interrupt - * 0b1..Clears the interrupt bit in INTENSET register - */ -#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) - -#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) -#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) -/*! MONIDLECLR - Monitor Idle interrupt clear - * 0b0..No effect on interrupt - * 0b1..Clears the interrupt bit in INTENSET register - */ -#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) - -#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) -#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) -/*! EVENTTIMEOUTCLR - Event time-out interrupt clear - * 0b0..No effect on interrupt - * 0b1..Clears the interrupt bit in INTENSET register - */ -#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) - -#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) -#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) -/*! SCLTIMEOUTCLR - SCL time-out interrupt clear - * 0b0..No effect on interrupt - * 0b1..Clears the interrupt bit in INTENSET register - */ -#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) -/*! @} */ - -/*! @name TIMEOUT - Time-out Register */ -/*! @{ */ - -#define I2C_TIMEOUT_TOMIN_MASK (0xFU) -#define I2C_TIMEOUT_TOMIN_SHIFT (0U) -/*! TOMIN - Time-out time value, the bottom 4 bits - */ -#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) - -#define I2C_TIMEOUT_TO_MASK (0xFFF0U) -#define I2C_TIMEOUT_TO_SHIFT (4U) -/*! TO - Time-out time value - * 0b000000000000..A time-out will occur after 16 counts of the I2C function clock. - * 0b000000000001..A time-out will occur after 32 counts of the I2C function clock. - * 0b111111111111..A time-out will occur after 65,536 counts of the I2C function clock. - */ -#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) -/*! @} */ - -/*! @name CLKDIV - Clock Divider Register */ -/*! @{ */ - -#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) -#define I2C_CLKDIV_DIVVAL_SHIFT (0U) -/*! DIVVAL - Divider Value - * 0b0000000000000000..FCLK is used directly by the I2C. - * 0b0000000000000001..FCLK is divided by 2 before being used by the I2C. - * 0b0000000000000010..FCLK is divided by 3 before being used by the I2C. - * 0b1111111111111111..FCLK is divided by 65,536 before being used by the I2C. - */ -#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt Status Register */ -/*! @{ */ - -#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) -#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) -/*! MSTPENDING - Master Pending - * 0b0..Not active - * 0b1..Active - */ -#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) - -#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) -#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) -/*! MSTARBLOSS - Master Arbitration Loss flag - * 0b0..Not active - * 0b1..Active - */ -#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) - -#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) -/*! MSTSTSTPERR - Master Start/Stop Error flag - * 0b0..Not active - * 0b1..Active - */ -#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) - -#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) -#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) -/*! SLVPENDING - Slave Pending - * 0b0..Not active - * 0b1..Active - */ -#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) - -#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) -#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) -/*! SLVNOTSTR - Slave Not Stretching status - * 0b0..Not active - * 0b1..Active - */ -#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) - -#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) -#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) -/*! SLVDESEL - Slave Deselected flag - * 0b0..Not active - * 0b1..Active - */ -#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) - -#define I2C_INTSTAT_MONRDY_MASK (0x10000U) -#define I2C_INTSTAT_MONRDY_SHIFT (16U) -/*! MONRDY - Monitor Ready - * 0b0..Not active - * 0b1..Active - */ -#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) - -#define I2C_INTSTAT_MONOV_MASK (0x20000U) -#define I2C_INTSTAT_MONOV_SHIFT (17U) -/*! MONOV - Monitor Overflow flag - * 0b0..Not active - * 0b1..Active - */ -#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) - -#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) -#define I2C_INTSTAT_MONIDLE_SHIFT (19U) -/*! MONIDLE - Monitor Idle flag - * 0b0..Not active - * 0b1..Active - */ -#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) - -#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) -/*! EVENTTIMEOUT - Event Time-out Interrupt flag - * 0b0..Not active - * 0b1..Active - */ -#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) - -#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) -/*! SCLTIMEOUT - SCL Time-out Interrupt flag - * 0b0..Not active - * 0b1..Active - */ -#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name MSTCTL - Master Control Register */ -/*! @{ */ - -#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) -#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) -/*! MSTCONTINUE - Master Continue(write-only) - * 0b0..No effect - * 0b1..Continue. Informs the Master function to continue to the next operation. This action must done after - * writing transmit data, reading received data, or any other housekeeping related to the next bus operation. - */ -#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) - -#define I2C_MSTCTL_MSTSTART_MASK (0x2U) -#define I2C_MSTCTL_MSTSTART_SHIFT (1U) -/*! MSTSTART - Master Start control(write-only) - * 0b0..No effect - * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. - */ -#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) - -#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) -#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) -/*! MSTSTOP - Master Stop control(write-only) - * 0b0..No effect - * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave - * if the master is receiving data from the slave (in Master Receiver mode). - */ -#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) - -#define I2C_MSTCTL_MSTDMA_MASK (0x8U) -#define I2C_MSTCTL_MSTDMA_SHIFT (3U) -/*! MSTDMA - Master DMA enable - * 0b0..Disable. No DMA requests are generated for master operation. - * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating - * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. - */ -#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) -/*! @} */ - -/*! @name MSTTIME - Master Timing Register */ -/*! @{ */ - -#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) -#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) -/*! MSTSCLLOW - Master SCL Low time - * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. - * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. - * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. - * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. - * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. - * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. - * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. - * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. - */ -#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) - -#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) -#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) -/*! MSTSCLHIGH - Master SCL High time - * 0b000..2 clocks. Minimum SCL high time is 2 clocks of the I2C clock pre-divider. - * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . - * 0b010..4 clocks. Minimum SCL high time is 4 clocks of the I2C clock pre-divider. - * 0b011..5 clocks. Minimum SCL high time is 5 clocks of the I2C clock pre-divider. - * 0b100..6 clocks. Minimum SCL high time is 6 clocks of the I2C clock pre-divider. - * 0b101..7 clocks. Minimum SCL high time is 7 clocks of the I2C clock pre-divider. - * 0b110..8 clocks. Minimum SCL high time is 8 clocks of the I2C clock pre-divider. - * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. - */ -#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) -/*! @} */ - -/*! @name MSTDAT - Master Data Register */ -/*! @{ */ - -#define I2C_MSTDAT_DATA_MASK (0xFFU) -#define I2C_MSTDAT_DATA_SHIFT (0U) -/*! DATA - Master function data register - */ -#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVCTL - Slave Control Register */ -/*! @{ */ - -#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) -#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) -/*! SLVCONTINUE - Slave Continue - * 0b0..No effect - * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the STAT[SLVPENDING] - * flag. This must be done after writing transmit data, reading received data, or any other housekeeping - * related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be - * set unless SLVPENDING = 1. - */ -#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) - -#define I2C_SLVCTL_SLVNACK_MASK (0x2U) -#define I2C_SLVCTL_SLVNACK_SHIFT (1U) -/*! SLVNACK - Slave NACK - * 0b0..No effect - * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (in Slave Receiver mode). - */ -#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) - -#define I2C_SLVCTL_SLVDMA_MASK (0x8U) -#define I2C_SLVCTL_SLVDMA_SHIFT (3U) -/*! SLVDMA - Slave DMA enable - * 0b0..Disabled. No DMA requests are issued for Slave mode operation. - * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. - */ -#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) - -#define I2C_SLVCTL_AUTOACK_MASK (0x100U) -#define I2C_SLVCTL_AUTOACK_SHIFT (8U) -/*! AUTOACK - Automatic Acknowledge - * 0b0..Normal, non-automatic operation. If AUTONACK = 0, then a SlvPending interrupt is generated when a - * matching address is received. If AUTONACK = 1, then received addresses are NACKed (ignored). - * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, - * allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does - * not match AUTOMATCHREAD, then the behavior will depend on the SLVADR0[AUTONACK] bit: if AUTONACK is set, - * then it will be Nacked; if AUTONACK is clear, then a SlvPending interrupt is generated. - */ -#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) - -#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) -#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) -/*! AUTOMATCHREAD - Automatic Match Read - * 0b0..In Automatic Mode, the expected next operation is an I2C write. - * 0b1..In Automatic Mode, the expected next operation is an I2C read. - */ -#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) -/*! @} */ - -/*! @name SLVDAT - Slave Data Register */ -/*! @{ */ - -#define I2C_SLVDAT_DATA_MASK (0xFFU) -#define I2C_SLVDAT_DATA_SHIFT (0U) -/*! DATA - Slave function data register - */ -#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVADR - Slave Address Register */ -/*! @{ */ - -#define I2C_SLVADR_SADISABLE_MASK (0x1U) -#define I2C_SLVADR_SADISABLE_SHIFT (0U) -/*! SADISABLE - Slave Address n Disable - * 0b0..Enabled. Slave Address n is enabled. - * 0b1..Ignored. Slave Address n is ignored. - */ -#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) - -#define I2C_SLVADR_SLVADR_MASK (0xFEU) -#define I2C_SLVADR_SLVADR_SHIFT (1U) -/*! SLVADR - Slave Address. - */ -#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) - -#define I2C_SLVADR_AUTONACK_MASK (0x8000U) -#define I2C_SLVADR_AUTONACK_SHIFT (15U) -/*! AUTONACK - Automatic NACK operation - * 0b0..Normal operation, matching I2C addresses are not ignored. - * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, and the address - * matches SLVADRn, and AUTOMATCHREAD matches the direction. - */ -#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) -/*! @} */ - -/* The count of I2C_SLVADR */ -#define I2C_SLVADR_COUNT (4U) - -/*! @name SLVQUAL0 - Slave Qualification for Address 0 Register */ -/*! @{ */ - -#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) -#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) -/*! QUALMODE0 - Qualify mode for slave address 0 - * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. - * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. - */ -#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) - -#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) -#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) -/*! SLVQUAL0 - Slave address Qualifier for address 0 - */ -#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) -/*! @} */ - -/*! @name MONRXDAT - Monitor Receiver Data Register */ -/*! @{ */ - -#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) -#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) -/*! MONRXDAT - Monitor function Receiver Data - */ -#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) - -#define I2C_MONRXDAT_MONSTART_MASK (0x100U) -#define I2C_MONRXDAT_MONSTART_SHIFT (8U) -/*! MONSTART - Monitor Received Start - * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. - * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. - */ -#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) - -#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) -#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) -/*! MONRESTART - Monitor Received Repeated Start - * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. - * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. - */ -#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) - -#define I2C_MONRXDAT_MONNACK_MASK (0x400U) -#define I2C_MONRXDAT_MONNACK_SHIFT (10U) -/*! MONNACK - Monitor Received NACK - * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. - * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. - */ -#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) -/*! @} */ - -/*! @name ID - Peripheral Identification Register */ -/*! @{ */ - -#define I2C_ID_APERTURE_MASK (0xFFU) -#define I2C_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture - */ -#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) - -#define I2C_ID_MINOR_REV_MASK (0xF00U) -#define I2C_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation - */ -#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) - -#define I2C_ID_MAJOR_REV_MASK (0xF000U) -#define I2C_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation - */ -#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) - -#define I2C_ID_ID_MASK (0xFFFF0000U) -#define I2C_ID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function - */ -#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2C_Register_Masks */ - - -/* I2C - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral I2C0 base address */ - #define I2C0_BASE (0x50086000u) - /** Peripheral I2C0 base address */ - #define I2C0_BASE_NS (0x40086000u) - /** Peripheral I2C0 base pointer */ - #define I2C0 ((I2C_Type *)I2C0_BASE) - /** Peripheral I2C0 base pointer */ - #define I2C0_NS ((I2C_Type *)I2C0_BASE_NS) - /** Peripheral I2C1 base address */ - #define I2C1_BASE (0x50087000u) - /** Peripheral I2C1 base address */ - #define I2C1_BASE_NS (0x40087000u) - /** Peripheral I2C1 base pointer */ - #define I2C1 ((I2C_Type *)I2C1_BASE) - /** Peripheral I2C1 base pointer */ - #define I2C1_NS ((I2C_Type *)I2C1_BASE_NS) - /** Peripheral I2C2 base address */ - #define I2C2_BASE (0x50088000u) - /** Peripheral I2C2 base address */ - #define I2C2_BASE_NS (0x40088000u) - /** Peripheral I2C2 base pointer */ - #define I2C2 ((I2C_Type *)I2C2_BASE) - /** Peripheral I2C2 base pointer */ - #define I2C2_NS ((I2C_Type *)I2C2_BASE_NS) - /** Peripheral I2C3 base address */ - #define I2C3_BASE (0x50089000u) - /** Peripheral I2C3 base address */ - #define I2C3_BASE_NS (0x40089000u) - /** Peripheral I2C3 base pointer */ - #define I2C3 ((I2C_Type *)I2C3_BASE) - /** Peripheral I2C3 base pointer */ - #define I2C3_NS ((I2C_Type *)I2C3_BASE_NS) - /** Peripheral I2C4 base address */ - #define I2C4_BASE (0x5008A000u) - /** Peripheral I2C4 base address */ - #define I2C4_BASE_NS (0x4008A000u) - /** Peripheral I2C4 base pointer */ - #define I2C4 ((I2C_Type *)I2C4_BASE) - /** Peripheral I2C4 base pointer */ - #define I2C4_NS ((I2C_Type *)I2C4_BASE_NS) - /** Peripheral I2C5 base address */ - #define I2C5_BASE (0x50096000u) - /** Peripheral I2C5 base address */ - #define I2C5_BASE_NS (0x40096000u) - /** Peripheral I2C5 base pointer */ - #define I2C5 ((I2C_Type *)I2C5_BASE) - /** Peripheral I2C5 base pointer */ - #define I2C5_NS ((I2C_Type *)I2C5_BASE_NS) - /** Peripheral I2C6 base address */ - #define I2C6_BASE (0x50097000u) - /** Peripheral I2C6 base address */ - #define I2C6_BASE_NS (0x40097000u) - /** Peripheral I2C6 base pointer */ - #define I2C6 ((I2C_Type *)I2C6_BASE) - /** Peripheral I2C6 base pointer */ - #define I2C6_NS ((I2C_Type *)I2C6_BASE_NS) - /** Peripheral I2C7 base address */ - #define I2C7_BASE (0x50098000u) - /** Peripheral I2C7 base address */ - #define I2C7_BASE_NS (0x40098000u) - /** Peripheral I2C7 base pointer */ - #define I2C7 ((I2C_Type *)I2C7_BASE) - /** Peripheral I2C7 base pointer */ - #define I2C7_NS ((I2C_Type *)I2C7_BASE_NS) - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS_NS { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS_NS { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS } -#else - /** Peripheral I2C0 base address */ - #define I2C0_BASE (0x40086000u) - /** Peripheral I2C0 base pointer */ - #define I2C0 ((I2C_Type *)I2C0_BASE) - /** Peripheral I2C1 base address */ - #define I2C1_BASE (0x40087000u) - /** Peripheral I2C1 base pointer */ - #define I2C1 ((I2C_Type *)I2C1_BASE) - /** Peripheral I2C2 base address */ - #define I2C2_BASE (0x40088000u) - /** Peripheral I2C2 base pointer */ - #define I2C2 ((I2C_Type *)I2C2_BASE) - /** Peripheral I2C3 base address */ - #define I2C3_BASE (0x40089000u) - /** Peripheral I2C3 base pointer */ - #define I2C3 ((I2C_Type *)I2C3_BASE) - /** Peripheral I2C4 base address */ - #define I2C4_BASE (0x4008A000u) - /** Peripheral I2C4 base pointer */ - #define I2C4 ((I2C_Type *)I2C4_BASE) - /** Peripheral I2C5 base address */ - #define I2C5_BASE (0x40096000u) - /** Peripheral I2C5 base pointer */ - #define I2C5 ((I2C_Type *)I2C5_BASE) - /** Peripheral I2C6 base address */ - #define I2C6_BASE (0x40097000u) - /** Peripheral I2C6 base pointer */ - #define I2C6 ((I2C_Type *)I2C6_BASE) - /** Peripheral I2C7 base address */ - #define I2C7_BASE (0x40098000u) - /** Peripheral I2C7 base pointer */ - #define I2C7 ((I2C_Type *)I2C7_BASE) - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } -#endif -/** Interrupt vectors for the I2C peripheral type */ -#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2C_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2S Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer - * @{ - */ - -/** I2S - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[3072]; - __IO uint32_t CFG1; /**< Configuration Register 1 for the Primary Channel Pair, offset: 0xC00 */ - __IO uint32_t CFG2; /**< Configuration Register 2 for the Primary Channel Pair, offset: 0xC04 */ - __IO uint32_t STAT; /**< Status Register for the Primary Channel Pair, offset: 0xC08 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< Clock Divider, offset: 0xC1C */ - struct { /* offset: 0xC20, array step: 0x20 */ - __IO uint32_t PCFG1; /**< Configuration Register 1 for Channel Pair 1..Configuration Register 1 for Channel Pair 3, array offset: 0xC20, array step: 0x20 */ - __IO uint32_t PCFG2; /**< Configuration Register 2 for Channel Pair 1..Configuration Register 2 for Channel Pair 3, array offset: 0xC24, array step: 0x20 */ - __I uint32_t PSTAT; /**< Status Register for Channel Pair 1..Status Register for Channel Pair 3, array offset: 0xC28, array step: 0x20 */ - uint8_t RESERVED_0[20]; - } SECCHANNEL[3]; - uint8_t RESERVED_2[384]; - __IO uint32_t FIFOCFG; /**< FIFO Configuration and Enable, offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO Status, offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO Trigger Settings, offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO Interrupt Enable Set and Read, offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO Interrupt Enable Clear and Read, offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO Interrupt Status, offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __O uint32_t FIFOWR; /**< FIFO Write Data, offset: 0xE20 */ - __O uint32_t FIFOWR48H; /**< FIFO Write Data for Upper Data Bits, offset: 0xE24 */ - uint8_t RESERVED_5[8]; - __I uint32_t FIFORD; /**< FIFO Read Data, offset: 0xE30 */ - __I uint32_t FIFORD48H; /**< FIFO Read Data for Upper Data Bits, offset: 0xE34 */ - uint8_t RESERVED_6[8]; - __I uint32_t FIFORDNOPOP; /**< FIFO Data Read with No FIFO Pop, offset: 0xE40 */ - __I uint32_t FIFORD48HNOPOP; /**< FIFO Data Read for Upper Data Bits with No FIFO Pop, offset: 0xE44 */ - __I uint32_t FIFOSIZE; /**< FIFO Size Register, offset: 0xE48 */ - __IO uint32_t FIFORXTIMEOUTCFG; /**< FIFO Receive Timeout Configuration, offset: 0xE4C */ - __I uint32_t FIFORXTIMEOUTCNT; /**< FIFO Receive Timeout Counter, offset: 0xE50 */ - uint8_t RESERVED_7[424]; - __I uint32_t ID; /**< I2S Module Identification, offset: 0xFFC */ -} I2S_Type; - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/*! @name CFG1 - Configuration Register 1 for the Primary Channel Pair */ -/*! @{ */ - -#define I2S_CFG1_MAINENABLE_MASK (0x1U) -#define I2S_CFG1_MAINENABLE_SHIFT (0U) -/*! MAINENABLE - Main Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) - -#define I2S_CFG1_DATAPAUSE_MASK (0x2U) -#define I2S_CFG1_DATAPAUSE_SHIFT (1U) -/*! DATAPAUSE - Data Flow Pause - * 0b0..Normal operation - * 0b1..Pause - */ -#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) - -#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) -#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) -/*! PAIRCOUNT - Pair Count - * 0b00..One Pair - * 0b01..Two Pairs - * 0b10..Three Pairs - * 0b11..Four Pairs - */ -#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) - -#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) -#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) -/*! MSTSLVCFG - Master/Slave Configuration Selection - * 0b00..Normal Slave Mode - * 0b01..WS Synchronized Master Mode - * 0b10..Master Using an Existing SCK Mode - * 0b11..Normal Master Mode - */ -#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) - -#define I2S_CFG1_MODE_MASK (0xC0U) -#define I2S_CFG1_MODE_SHIFT (6U) -/*! MODE - Mode - * 0b00..Classic Mode - * 0b01..DSP mode WS 50% duty cycle - * 0b10..DSP mode WS 1 clock - * 0b11..DSP mode WS 1 data - */ -#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) - -#define I2S_CFG1_RIGHTLOW_MASK (0x100U) -#define I2S_CFG1_RIGHTLOW_SHIFT (8U) -/*! RIGHTLOW - Right Channel Low - * 0b0..Right high - * 0b1..Right low - */ -#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) - -#define I2S_CFG1_LEFTJUST_MASK (0x200U) -#define I2S_CFG1_LEFTJUST_SHIFT (9U) -/*! LEFTJUST - Left-Justify Data - * 0b0..Right-justified - * 0b1..Left-justified - */ -#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) - -#define I2S_CFG1_ONECHANNEL_MASK (0x400U) -#define I2S_CFG1_ONECHANNEL_SHIFT (10U) -/*! ONECHANNEL - Single Channel Mode - * 0b0..Dual channel - * 0b1..Single channel - */ -#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) - -#define I2S_CFG1_PDMDATA_MASK (0x800U) -#define I2S_CFG1_PDMDATA_SHIFT (11U) -/*! PDMDATA - PDM Data Selection - * 0b0..Normal Operation - * 0b1..DMIC subsystem - */ -#define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK) - -#define I2S_CFG1_SCK_POL_MASK (0x1000U) -#define I2S_CFG1_SCK_POL_SHIFT (12U) -/*! SCK_POL - SCK Polarity - * 0b0..Falling edge - * 0b1..Rising edge - */ -#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) - -#define I2S_CFG1_WS_POL_MASK (0x2000U) -#define I2S_CFG1_WS_POL_SHIFT (13U) -/*! WS_POL - WS Polarity - * 0b0..Not inverted - * 0b1..Inverted - */ -#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) - -#define I2S_CFG1_DATALEN_MASK (0x1F0000U) -#define I2S_CFG1_DATALEN_SHIFT (16U) -/*! DATALEN - Data Length - * 0b00011..Data is 4 bits in length. - * 0b00100..Data is 5 bits in length. - * 0b00111..Data is 8 bits in length. - * 0b11110..Data is 31 bits in length. - * 0b11111..Data is 32 bits in length. - */ -#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) -/*! @} */ - -/*! @name CFG2 - Configuration Register 2 for the Primary Channel Pair */ -/*! @{ */ - -#define I2S_CFG2_FRAMELEN_MASK (0x7FFU) -#define I2S_CFG2_FRAMELEN_SHIFT (0U) -/*! FRAMELEN - Frame Length - * 0b00000000011..Frame is 4 bits in total length - * 0b00000000100..Frame is 5 bits in total length - * 0b00111111111..Frame is 512 bits in total length - * 0b11111111111..Frame is 2048 bits in total length - */ -#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) - -#define I2S_CFG2_POSITION_MASK (0x7FF0000U) -#define I2S_CFG2_POSITION_SHIFT (16U) -/*! POSITION - Data Position - * 0b00000000000..Data begins at bit position 0 (the first bit position) within the frame or WS phase - * 0b00000000001..Data begins at bit position 1 within the frame or WS phase - * 0b00000000010..Data begins at bit position 2 within the frame or WS phase - */ -#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) -/*! @} */ - -/*! @name STAT - Status Register for the Primary Channel Pair */ -/*! @{ */ - -#define I2S_STAT_BUSY_MASK (0x1U) -#define I2S_STAT_BUSY_SHIFT (0U) -/*! BUSY - Busy Status - * 0b0..Idle - * 0b1..Busy - */ -#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) - -#define I2S_STAT_SLVFRMERR_MASK (0x2U) -#define I2S_STAT_SLVFRMERR_SHIFT (1U) -/*! SLVFRMERR - Slave Frame Error - * 0b0..No error - * 0b1..Error - */ -#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) - -#define I2S_STAT_LR_MASK (0x4U) -#define I2S_STAT_LR_SHIFT (2U) -/*! LR - Left/Right Indication - * 0b0..Left channel - * 0b1..Right channel - */ -#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) - -#define I2S_STAT_DATAPAUSED_MASK (0x8U) -#define I2S_STAT_DATAPAUSED_SHIFT (3U) -/*! DATAPAUSED - Data Paused - * 0b0..Not Paused - * 0b1..Paused - */ -#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) -/*! @} */ - -/*! @name DIV - Clock Divider */ -/*! @{ */ - -#define I2S_DIV_DIV_MASK (0xFFFU) -#define I2S_DIV_DIV_SHIFT (0U) -/*! DIV - Divider - * 0b000000000000..FCLK is used directly. - * 0b000000000001..FCLK is divided by 2. - * 0b000000000010..FCLK is divided by 3. - * 0b111111111111..FCLK is divided by 4,096. - */ -#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) -/*! @} */ - -/*! @name SECCHANNEL_PCFG1 - Configuration Register 1 for Channel Pair 1..Configuration Register 1 for Channel Pair 3 */ -/*! @{ */ - -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U) -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U) -/*! PAIRENABLE - Pair Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK) - -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U) -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U) -/*! ONECHANNEL - Single Channel Mode - * 0b0..Dual Channel - * 0b1..Single Channel - */ -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK) -/*! @} */ - -/* The count of I2S_SECCHANNEL_PCFG1 */ -#define I2S_SECCHANNEL_PCFG1_COUNT (3U) - -/*! @name SECCHANNEL_PCFG2 - Configuration Register 2 for Channel Pair 1..Configuration Register 2 for Channel Pair 3 */ -/*! @{ */ - -#define I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U) -#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U) -/*! POSITION - Data Position - */ -#define I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK) -/*! @} */ - -/* The count of I2S_SECCHANNEL_PCFG2 */ -#define I2S_SECCHANNEL_PCFG2_COUNT (3U) - -/*! @name SECCHANNEL_PSTAT - Status Register for Channel Pair 1..Status Register for Channel Pair 3 */ -/*! @{ */ - -#define I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U) -#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U) -/*! BUSY - Busy Status for Channel Pair - * 0b0..Idle. The transmitter/receiver for this channel pair is currently idle. - * 0b1..Busy. The transmitter/receiver for this channel pair is currently processing data. - */ -#define I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK) - -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U) -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U) -/*! SLVFRMERR - Save Frame Error Flag - * 0b0..No Error - * 0b1..Error - */ -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK) - -#define I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U) -#define I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U) -/*! LR - Left/Right Indication - * 0b0..Left channel - * 0b1..Right channel - */ -#define I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK) - -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U) -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U) -/*! DATAPAUSED - Data Paused Status Flag - * 0b0..Data Not Paused. Data is not currently paused. A data pause may have been requested but is not yet in - * force, waiting for an allowed pause point. Refer to the description in CFG1[DATAPAUSE]. - * 0b1..Data Paused. A data pause has been requested and is now in force. - */ -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK) -/*! @} */ - -/* The count of I2S_SECCHANNEL_PSTAT */ -#define I2S_SECCHANNEL_PSTAT_COUNT (3U) - -/*! @name FIFOCFG - FIFO Configuration and Enable */ -/*! @{ */ - -#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) -#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable Transmit FIFO - * 0b0..Disabled Transmit. The transmit FIFO is not enabled. - * 0b1..Enabled transmit. The transmit FIFO is enabled. - */ -#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) - -#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) -#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable Receive FIFO - * 0b0..Disabled. The receive FIFO is not enabled. - * 0b1..Enabled. The receive FIFO is enabled. - */ -#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) - -#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) -#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) -/*! TXI2SE0 - Transmit I2S Empty 0 - * 0b0..Last value - * 0b1..Zero - */ -#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) - -#define I2S_FIFOCFG_PACK48_MASK (0x8U) -#define I2S_FIFOCFG_PACK48_SHIFT (3U) -/*! PACK48 - Packing Format 48-bit data - * 0b0..Bits_24 - * 0b1..Bits_32_16 - */ -#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) - -#define I2S_FIFOCFG_SIZE_MASK (0x30U) -#define I2S_FIFOCFG_SIZE_SHIFT (4U) -/*! SIZE - FIFO Size Configuration - * 0b10..Size 32 Bits - * 0b11..Size 48 Bits - */ -#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) - -#define I2S_FIFOCFG_DMATX_MASK (0x1000U) -#define I2S_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA Transmit - * 0b0..Disabled - * 0b1..Enabled - */ -#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) - -#define I2S_FIFOCFG_DMARX_MASK (0x2000U) -#define I2S_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA Receive - * 0b0..Disabled - * 0b1..Enabled - */ -#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) - -#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) -#define I2S_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for Transmit FIFO Level - * 0b0..Disabled - * 0b1..Enabled - */ -#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) - -#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) -#define I2S_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for Receive FIFO Level - * 0b0..Only enabled interrupts wake up the device from reduced power modes. - * 0b1..A device wake-up for DMA occurs if the receive FIFO level reaches the value specified by FIFOTRIG[RXLVL], - * even when the RXLVL interrupt is not enabled. - */ -#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) - -#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) -/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - */ -#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) - -#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) -/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - */ -#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) - -#define I2S_FIFOCFG_POPDBG_MASK (0x40000U) -#define I2S_FIFOCFG_POPDBG_SHIFT (18U) -/*! POPDBG - Pop FIFO for Debug Reads - * 0b0..Debug reads of the FIFO do not pop the FIFO. - * 0b1..A debug read causes the FIFO to pop. - */ -#define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO Status */ -/*! @{ */ - -#define I2S_FIFOSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO Error - * 0b0..No transmit FIFO error occured - * 0b1..Transmit FIFO error occured - */ -#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) - -#define I2S_FIFOSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO Error - * 0b0..No receive FIFO error occured - * 0b1..Receive FIFO error occured - */ -#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) - -#define I2S_FIFOSTAT_PERINT_MASK (0x8U) -#define I2S_FIFOSTAT_PERINT_SHIFT (3U) -/*! PERINT - Peripheral Interrupt - * 0b0..No interrupt - * 0b1..Interrupt - */ -#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) - -#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) -/*! TXEMPTY - Transmit FIFO Empty - * 0b0..Transmit FIFO is not empty - * 0b1..Transmit FIFO is empty; however, the peripheral may still be processing the last piece of data. - */ -#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) - -#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) -/*! TXNOTFULL - Transmit FIFO Not Full - * 0b0..Transmit FIFO is full, and another write would cause an overflow - * 0b1..Transmit FIFO is not full, so more data can be written - */ -#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) - -#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -/*! RXNOTEMPTY - Receive FIFO Not Empty - * 0b0..Receive FIFO is empty - * 0b1..Receive FIFO is not empty, so data can be read. - */ -#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) - -#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) -#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) -/*! RXFULL - Receive FIFO Full - * 0b0..Receive FIFO is not full - * 0b1..Receive FIFO is full - */ -#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) - -#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO Current Level - * 0b00000..TX FIFO is empty - */ -#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) - -#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO Current Level - * 0b00000..RX FIFO is empty - */ -#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) - -#define I2S_FIFOSTAT_RXTIMEOUT_MASK (0x1000000U) -#define I2S_FIFOSTAT_RXTIMEOUT_SHIFT (24U) -/*! RXTIMEOUT - Receive FIFO Timeout - * 0b0..RX FIFO on - * 0b1..RX FIFO has timed out, based on the timeout configuration in the FIFORXTIMEOUTCFG register. - */ -#define I2S_FIFOSTAT_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXTIMEOUT_SHIFT)) & I2S_FIFOSTAT_RXTIMEOUT_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO Trigger Settings */ -/*! @{ */ - -#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO Level Trigger Enable - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger generates if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) - -#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO Level Trigger Enable - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger generates if the receive FIFO level reaches the value specified by the RXLVL. - */ -#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) - -#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) -#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO Level Trigger Point - * 0b0000..Trigger when the TX FIFO becomes empty. - * 0b0001..Trigger when the TX FIFO level decreases to one entry. - * 0b1111..Trigger when the TX FIFO level decreases to 15 entries (is no longer full). - */ -#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) - -#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO Level Trigger Point - * 0b0000..Trigger when the RX FIFO has received 1 entry (the FIFO is no longer empty). - * 0b0001..Trigger when the RX FIFO has received 2 entries. - * 0b1111..Trigger when the RX FIFO has received 16 entries (the FIFO has become full). - */ -#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO Interrupt Enable Set and Read */ -/*! @{ */ - -#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) -#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Transmit Error Interrupt - * 0b0..Disabled. No interrupt generates for a transmit error. - * 0b1..Enabled. An interrupt generates when a transmit error occurs. - */ -#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) - -#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) -#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Receive Error Interrupt - * 0b0..Disabled - * 0b1..Enabled - */ -#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) - -#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit Level Interrupt - * 0b0..Disabled - * 0b1..Enabled - */ -#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) - -#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Receive Level Interrupt - * 0b0..Disabled - * 0b1..Enabled - */ -#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) - -#define I2S_FIFOINTENSET_RXTIMEOUT_MASK (0x1000000U) -#define I2S_FIFOINTENSET_RXTIMEOUT_SHIFT (24U) -/*! RXTIMEOUT - Receive Timeout - * 0b0..No RX interrupt will be generated. - * 0b1..Asserts RX interrupt if RX FIFO Timeout event occurs. - */ -#define I2S_FIFOINTENSET_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXTIMEOUT_SHIFT)) & I2S_FIFOINTENSET_RXTIMEOUT_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO Interrupt Enable Clear and Read */ -/*! @{ */ - -#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) -#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) -/*! TXERR - Transmit Error Interrupt Clear - * 0b0..Interrupt is not cleared. - * 0b1..Interrupt is cleared. - */ -#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) - -#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) -#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) -/*! RXERR - Receive Error Interrupt Clear - * 0b0..Interrupt is not cleared. - * 0b1..Interrupt is cleared. - */ -#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) - -#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit Level Interrupt Clear - * 0b0..Interrupt is not cleared. - * 0b1..Interrupt is cleared. - */ -#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) - -#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) -/*! RXLVL - Receive Level Interrupt Clear - * 0b0..Interrupt is not cleared. - * 0b1..Interrupt is cleared. - */ -#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) - -#define I2S_FIFOINTENCLR_RXTIMEOUT_MASK (0x1000000U) -#define I2S_FIFOINTENCLR_RXTIMEOUT_SHIFT (24U) -/*! RXTIMEOUT - Receive Timeout - * 0b0..No effect - * 0b1..Clear the interrupt - */ -#define I2S_FIFOINTENCLR_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXTIMEOUT_SHIFT)) & I2S_FIFOINTENCLR_RXTIMEOUT_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO Interrupt Status */ -/*! @{ */ - -#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO Error Interrupt Status - * 0b0..Not pending - * 0b1..Pending - */ -#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) - -#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO Error Interrupt Status - * 0b0..Not pending - * 0b1..Pending - */ -#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) - -#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO Level Interrupt Status - * 0b0..Not pending - * 0b1..Pending - */ -#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) - -#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO Level Interrupt Status - * 0b0..Not pending - * 0b1..Pending - */ -#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) - -#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) -#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) -/*! PERINT - Peripheral Interrupt Status - * 0b0..Not pending - * 0b1..Pending - */ -#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) - -#define I2S_FIFOINTSTAT_RXTIMEOUT_MASK (0x1000000U) -#define I2S_FIFOINTSTAT_RXTIMEOUT_SHIFT (24U) -/*! RXTIMEOUT - Receive Timeout Status - * 0b0..Not pending - * 0b1..Pending - */ -#define I2S_FIFOINTSTAT_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXTIMEOUT_SHIFT)) & I2S_FIFOINTSTAT_RXTIMEOUT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO Write Data */ -/*! @{ */ - -#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFOWR_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit Data to the FIFO - */ -#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFOWR48H - FIFO Write Data for Upper Data Bits */ -/*! @{ */ - -#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) -#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit Data to the FIFO - */ -#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO Read Data */ -/*! @{ */ - -#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORD_RXDATA_SHIFT (0U) -/*! RXDATA - Received Data from the FIFO - */ -#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48H - FIFO Read Data for Upper Data Bits */ -/*! @{ */ - -#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48H_RXDATA_SHIFT (0U) -/*! RXDATA - Received Data from the FIFO - */ -#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO Data Read with No FIFO Pop */ -/*! @{ */ - -#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received Data from the FIFO - */ -#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48HNOPOP - FIFO Data Read for Upper Data Bits with No FIFO Pop */ -/*! @{ */ - -#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received Data from the FIFO - */ -#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) -/*! @} */ - -/*! @name FIFOSIZE - FIFO Size Register */ -/*! @{ */ - -#define I2S_FIFOSIZE_FIFOSIZE_MASK (0x1FU) -#define I2S_FIFOSIZE_FIFOSIZE_SHIFT (0U) -/*! FIFOSIZE - FIFO Size - */ -#define I2S_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSIZE_FIFOSIZE_SHIFT)) & I2S_FIFOSIZE_FIFOSIZE_MASK) -/*! @} */ - -/*! @name FIFORXTIMEOUTCFG - FIFO Receive Timeout Configuration */ -/*! @{ */ - -#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK (0xFFU) -#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT (0U) -/*! RXTIMEOUT_PRESCALER - Receive Timeout Counter Clock Prescaler - */ -#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT)) & I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK) - -#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK (0xFFFF00U) -#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT (8U) -/*! RXTIMEOUT_VALUE - Receive Timeout Value - */ -#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT)) & I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK) - -#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK (0x1000000U) -#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT (24U) -/*! RXTIMEOUT_EN - Receive Timeout Enable - * 0b0..Disable RX FIFO timeout - * 0b1..Enable RX FIFO timeout - */ -#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_EN(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT)) & I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK) - -#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK (0x2000000U) -#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT (25U) -/*! RXTIMEOUT_COW - Receive Timeout Continue On Write - * 0b0..RX FIFO timeout counter is reset every time data is transferred from the peripheral into the RX FIFO. - * 0b1..RX FIFO timeout counter is not reset every time data is transferred from the peripheral into the RX FIFO. - */ -#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COW(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT)) & I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK) - -#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK (0x4000000U) -#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT (26U) -/*! RXTIMEOUT_COE - Receive Timeout Continue On Empty - * 0b0..RX FIFO timeout counter is reset when the RX FIFO becomes empty. - * 0b1..RX FIFO timeout counter is not reset when the RX FIFO becomes empty. - */ -#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT)) & I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK) -/*! @} */ - -/*! @name FIFORXTIMEOUTCNT - FIFO Receive Timeout Counter */ -/*! @{ */ - -#define I2S_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK (0xFFFFU) -#define I2S_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT (0U) -/*! RXTIMEOUT_CNT - Current RX FIFO timeout counter value - */ -#define I2S_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT)) & I2S_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK) -/*! @} */ - -/*! @name ID - I2S Module Identification */ -/*! @{ */ - -#define I2S_ID_APERTURE_MASK (0xFFU) -#define I2S_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture - */ -#define I2S_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_APERTURE_SHIFT)) & I2S_ID_APERTURE_MASK) - -#define I2S_ID_MINOR_REV_MASK (0xF00U) -#define I2S_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor Revision - */ -#define I2S_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK) - -#define I2S_ID_MAJOR_REV_MASK (0xF000U) -#define I2S_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major Revision - */ -#define I2S_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK) - -#define I2S_ID_ID_MASK (0xFFFF0000U) -#define I2S_ID_ID_SHIFT (16U) -/*! ID - Module Identifier - */ -#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2S_Register_Masks */ - - -/* I2S - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral I2S0 base address */ - #define I2S0_BASE (0x50086000u) - /** Peripheral I2S0 base address */ - #define I2S0_BASE_NS (0x40086000u) - /** Peripheral I2S0 base pointer */ - #define I2S0 ((I2S_Type *)I2S0_BASE) - /** Peripheral I2S0 base pointer */ - #define I2S0_NS ((I2S_Type *)I2S0_BASE_NS) - /** Peripheral I2S1 base address */ - #define I2S1_BASE (0x50087000u) - /** Peripheral I2S1 base address */ - #define I2S1_BASE_NS (0x40087000u) - /** Peripheral I2S1 base pointer */ - #define I2S1 ((I2S_Type *)I2S1_BASE) - /** Peripheral I2S1 base pointer */ - #define I2S1_NS ((I2S_Type *)I2S1_BASE_NS) - /** Peripheral I2S2 base address */ - #define I2S2_BASE (0x50088000u) - /** Peripheral I2S2 base address */ - #define I2S2_BASE_NS (0x40088000u) - /** Peripheral I2S2 base pointer */ - #define I2S2 ((I2S_Type *)I2S2_BASE) - /** Peripheral I2S2 base pointer */ - #define I2S2_NS ((I2S_Type *)I2S2_BASE_NS) - /** Peripheral I2S3 base address */ - #define I2S3_BASE (0x50089000u) - /** Peripheral I2S3 base address */ - #define I2S3_BASE_NS (0x40089000u) - /** Peripheral I2S3 base pointer */ - #define I2S3 ((I2S_Type *)I2S3_BASE) - /** Peripheral I2S3 base pointer */ - #define I2S3_NS ((I2S_Type *)I2S3_BASE_NS) - /** Peripheral I2S4 base address */ - #define I2S4_BASE (0x5008A000u) - /** Peripheral I2S4 base address */ - #define I2S4_BASE_NS (0x4008A000u) - /** Peripheral I2S4 base pointer */ - #define I2S4 ((I2S_Type *)I2S4_BASE) - /** Peripheral I2S4 base pointer */ - #define I2S4_NS ((I2S_Type *)I2S4_BASE_NS) - /** Peripheral I2S5 base address */ - #define I2S5_BASE (0x50096000u) - /** Peripheral I2S5 base address */ - #define I2S5_BASE_NS (0x40096000u) - /** Peripheral I2S5 base pointer */ - #define I2S5 ((I2S_Type *)I2S5_BASE) - /** Peripheral I2S5 base pointer */ - #define I2S5_NS ((I2S_Type *)I2S5_BASE_NS) - /** Peripheral I2S6 base address */ - #define I2S6_BASE (0x50097000u) - /** Peripheral I2S6 base address */ - #define I2S6_BASE_NS (0x40097000u) - /** Peripheral I2S6 base pointer */ - #define I2S6 ((I2S_Type *)I2S6_BASE) - /** Peripheral I2S6 base pointer */ - #define I2S6_NS ((I2S_Type *)I2S6_BASE_NS) - /** Peripheral I2S7 base address */ - #define I2S7_BASE (0x50098000u) - /** Peripheral I2S7 base address */ - #define I2S7_BASE_NS (0x40098000u) - /** Peripheral I2S7 base pointer */ - #define I2S7 ((I2S_Type *)I2S7_BASE) - /** Peripheral I2S7 base pointer */ - #define I2S7_NS ((I2S_Type *)I2S7_BASE_NS) - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS_NS { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS_NS { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS } -#else - /** Peripheral I2S0 base address */ - #define I2S0_BASE (0x40086000u) - /** Peripheral I2S0 base pointer */ - #define I2S0 ((I2S_Type *)I2S0_BASE) - /** Peripheral I2S1 base address */ - #define I2S1_BASE (0x40087000u) - /** Peripheral I2S1 base pointer */ - #define I2S1 ((I2S_Type *)I2S1_BASE) - /** Peripheral I2S2 base address */ - #define I2S2_BASE (0x40088000u) - /** Peripheral I2S2 base pointer */ - #define I2S2 ((I2S_Type *)I2S2_BASE) - /** Peripheral I2S3 base address */ - #define I2S3_BASE (0x40089000u) - /** Peripheral I2S3 base pointer */ - #define I2S3 ((I2S_Type *)I2S3_BASE) - /** Peripheral I2S4 base address */ - #define I2S4_BASE (0x4008A000u) - /** Peripheral I2S4 base pointer */ - #define I2S4 ((I2S_Type *)I2S4_BASE) - /** Peripheral I2S5 base address */ - #define I2S5_BASE (0x40096000u) - /** Peripheral I2S5 base pointer */ - #define I2S5 ((I2S_Type *)I2S5_BASE) - /** Peripheral I2S6 base address */ - #define I2S6_BASE (0x40097000u) - /** Peripheral I2S6 base pointer */ - #define I2S6 ((I2S_Type *)I2S6_BASE) - /** Peripheral I2S7 base address */ - #define I2S7_BASE (0x40098000u) - /** Peripheral I2S7 base pointer */ - #define I2S7 ((I2S_Type *)I2S7_BASE) - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } -#endif -/** Interrupt vectors for the I2S peripheral type */ -#define I2S_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2S_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I3C Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer - * @{ - */ - -/** I3C - Register Layout Typedef */ -typedef struct { - __IO uint32_t MCONFIG; /**< Master Configuration, offset: 0x0 */ - __IO uint32_t SCONFIG; /**< Slave Configuration, offset: 0x4 */ - __IO uint32_t SSTATUS; /**< Slave Status, offset: 0x8 */ - __IO uint32_t SCTRL; /**< Slave Control, offset: 0xC */ - __IO uint32_t SINTSET; /**< Slave Interrupt Set, offset: 0x10 */ - __IO uint32_t SINTCLR; /**< Slave Interrupt Clear, offset: 0x14 */ - __I uint32_t SINTMASKED; /**< Slave Interrupt Mask, offset: 0x18 */ - __IO uint32_t SERRWARN; /**< Slave Errors and Warnings, offset: 0x1C */ - __IO uint32_t SDMACTRL; /**< Slave DMA Control, offset: 0x20 */ - uint8_t RESERVED_0[8]; - __IO uint32_t SDATACTRL; /**< Slave Data Control, offset: 0x2C */ - __O uint32_t SWDATAB; /**< Slave Write Data Byte, offset: 0x30 */ - __O uint32_t SWDATABE; /**< Slave Write Data Byte End, offset: 0x34 */ - __O uint32_t SWDATAH; /**< Slave Write Data Half-word, offset: 0x38 */ - __O uint32_t SWDATAHE; /**< Slave Write Data Half-word End, offset: 0x3C */ - __I uint32_t SRDATAB; /**< Slave Read Data Byte, offset: 0x40 */ - uint8_t RESERVED_1[4]; - __I uint32_t SRDATAH; /**< Slave Read Data Half-word, offset: 0x48 */ - uint8_t RESERVED_2[16]; - __I uint32_t SCAPABILITIES2; /**< Slave Capabilities 2, offset: 0x5C */ - __I uint32_t SCAPABILITIES; /**< Slave Capabilities, offset: 0x60 */ - __IO uint32_t SDYNADDR; /**< Slave Dynamic Address, offset: 0x64 */ - __IO uint32_t SMAXLIMITS; /**< Slave Maximum Limits, offset: 0x68 */ - __IO uint32_t SIDPARTNO; /**< Slave ID Part Number, offset: 0x6C */ - __IO uint32_t SIDEXT; /**< Slave ID Extension, offset: 0x70 */ - __IO uint32_t SVENDORID; /**< Slave Vendor ID, offset: 0x74 */ - __IO uint32_t STCCLOCK; /**< Slave Time Control Clock, offset: 0x78 */ - __I uint32_t SMSGMAPADDR; /**< Slave Message Map Address, offset: 0x7C */ - uint8_t RESERVED_3[4]; - __IO uint32_t MCTRL; /**< Master Main Control, offset: 0x84 */ - __IO uint32_t MSTATUS; /**< Master Status, offset: 0x88 */ - __IO uint32_t MIBIRULES; /**< Master In-band Interrupt Registry and Rules, offset: 0x8C */ - __IO uint32_t MINTSET; /**< Master Interrupt Set, offset: 0x90 */ - __IO uint32_t MINTCLR; /**< Master Interrupt Clear, offset: 0x94 */ - __I uint32_t MINTMASKED; /**< Master Interrupt Mask, offset: 0x98 */ - __IO uint32_t MERRWARN; /**< Master Errors and Warnings, offset: 0x9C */ - __IO uint32_t MDMACTRL; /**< Master DMA Control, offset: 0xA0 */ - uint8_t RESERVED_4[8]; - __IO uint32_t MDATACTRL; /**< Master Data Control, offset: 0xAC */ - __O uint32_t MWDATAB; /**< Master Write Data Byte, offset: 0xB0 */ - __O uint32_t MWDATABE; /**< Master Write Data Byte End, offset: 0xB4 */ - __O uint32_t MWDATAH; /**< Master Write Data Half-word, offset: 0xB8 */ - __O uint32_t MWDATAHE; /**< Master Write Data Byte End, offset: 0xBC */ - __I uint32_t MRDATAB; /**< Master Read Data Byte, offset: 0xC0 */ - uint8_t RESERVED_5[4]; - __I uint32_t MRDATAH; /**< Master Read Data Half-word, offset: 0xC8 */ - __O uint32_t MWDATAB1; /**< Byte-only Write Byte Data (to bus), offset: 0xCC */ - union { /* offset: 0xD0 */ - __O uint32_t MWMSG_SDR_CONTROL; /**< Master Write Message in SDR mode, offset: 0xD0 */ - __O uint32_t MWMSG_SDR_DATA; /**< Master Write Message Data in SDR mode, offset: 0xD0 */ - }; - __I uint32_t MRMSG_SDR; /**< Master Read Message in SDR mode, offset: 0xD4 */ - union { /* offset: 0xD8 */ - __O uint32_t MWMSG_DDR_CONTROL; /**< Master Write Message in DDR mode, offset: 0xD8 */ - __O uint32_t MWMSG_DDR_DATA; /**< Master Write Message Data in DDR mode, offset: 0xD8 */ - }; - __I uint32_t MRMSG_DDR; /**< Master Read Message in DDR mode, offset: 0xDC */ - uint8_t RESERVED_6[4]; - __IO uint32_t MDYNADDR; /**< Master Dynamic Address, offset: 0xE4 */ - uint8_t RESERVED_7[52]; - __I uint32_t SMAPCTRL0; /**< Map Feature Control 0, offset: 0x11C */ - uint8_t RESERVED_8[32]; - __IO uint32_t IBIEXT1; /**< Extended IBI Data 1, offset: 0x140 */ - __IO uint32_t IBIEXT2; /**< Extended IBI Data 2, offset: 0x144 */ - uint8_t RESERVED_9[3764]; - __I uint32_t SID; /**< Slave Module ID, offset: 0xFFC */ -} I3C_Type; - -/* ---------------------------------------------------------------------------- - -- I3C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I3C_Register_Masks I3C Register Masks - * @{ - */ - -/*! @name MCONFIG - Master Configuration */ -/*! @{ */ - -#define I3C_MCONFIG_MSTENA_MASK (0x3U) -#define I3C_MCONFIG_MSTENA_SHIFT (0U) -/*! MSTENA - Master enable - * 0b00..MASTER_OFF - * 0b01..MASTER_ON - * 0b10..MASTER_CAPABLE - * 0b11..I2C_MASTER_MODE - */ -#define I3C_MCONFIG_MSTENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK) - -#define I3C_MCONFIG_DISTO_MASK (0x8U) -#define I3C_MCONFIG_DISTO_SHIFT (3U) -/*! DISTO - Disable Timeout - */ -#define I3C_MCONFIG_DISTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK) - -#define I3C_MCONFIG_HKEEP_MASK (0x30U) -#define I3C_MCONFIG_HKEEP_SHIFT (4U) -/*! HKEEP - High-Keeper - * 0b00..NONE - * 0b01..WIRED_IN - * 0b10..PASSIVE_SDA - * 0b11..PASSIVE_ON_SDA_SCL - */ -#define I3C_MCONFIG_HKEEP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK) - -#define I3C_MCONFIG_ODSTOP_MASK (0x40U) -#define I3C_MCONFIG_ODSTOP_SHIFT (6U) -/*! ODSTOP - Open drain stop - */ -#define I3C_MCONFIG_ODSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK) - -#define I3C_MCONFIG_PPBAUD_MASK (0xF00U) -#define I3C_MCONFIG_PPBAUD_SHIFT (8U) -/*! PPBAUD - Push-pull baud rate - */ -#define I3C_MCONFIG_PPBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK) - -#define I3C_MCONFIG_PPLOW_MASK (0xF000U) -#define I3C_MCONFIG_PPLOW_SHIFT (12U) -/*! PPLOW - Push-Pull low - */ -#define I3C_MCONFIG_PPLOW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK) - -#define I3C_MCONFIG_ODBAUD_MASK (0xFF0000U) -#define I3C_MCONFIG_ODBAUD_SHIFT (16U) -/*! ODBAUD - Open drain baud rate - */ -#define I3C_MCONFIG_ODBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK) - -#define I3C_MCONFIG_ODHPP_MASK (0x1000000U) -#define I3C_MCONFIG_ODHPP_SHIFT (24U) -/*! ODHPP - Open Drain High Push-Pull - */ -#define I3C_MCONFIG_ODHPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK) - -#define I3C_MCONFIG_SKEW_MASK (0xE000000U) -#define I3C_MCONFIG_SKEW_SHIFT (25U) -/*! SKEW - Skew - */ -#define I3C_MCONFIG_SKEW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK) - -#define I3C_MCONFIG_I2CBAUD_MASK (0xF0000000U) -#define I3C_MCONFIG_I2CBAUD_SHIFT (28U) -/*! I2CBAUD - I2C baud rate - */ -#define I3C_MCONFIG_I2CBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK) -/*! @} */ - -/*! @name SCONFIG - Slave Configuration */ -/*! @{ */ - -#define I3C_SCONFIG_SLVENA_MASK (0x1U) -#define I3C_SCONFIG_SLVENA_SHIFT (0U) -/*! SLVENA - Slave enable - */ -#define I3C_SCONFIG_SLVENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK) - -#define I3C_SCONFIG_NACK_MASK (0x2U) -#define I3C_SCONFIG_NACK_SHIFT (1U) -/*! NACK - Not acknowledge - */ -#define I3C_SCONFIG_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK) - -#define I3C_SCONFIG_MATCHSS_MASK (0x4U) -#define I3C_SCONFIG_MATCHSS_SHIFT (2U) -/*! MATCHSS - Match START or STOP - */ -#define I3C_SCONFIG_MATCHSS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK) - -#define I3C_SCONFIG_S0IGNORE_MASK (0x8U) -#define I3C_SCONFIG_S0IGNORE_SHIFT (3U) -/*! S0IGNORE - S0/S1 errors ignore - */ -#define I3C_SCONFIG_S0IGNORE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK) - -#define I3C_SCONFIG_DDROK_MASK (0x10U) -#define I3C_SCONFIG_DDROK_SHIFT (4U) -/*! DDROK - DDR OK - */ -#define I3C_SCONFIG_DDROK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_DDROK_SHIFT)) & I3C_SCONFIG_DDROK_MASK) - -#define I3C_SCONFIG_IDRAND_MASK (0x100U) -#define I3C_SCONFIG_IDRAND_SHIFT (8U) -/*! IDRAND - ID random - */ -#define I3C_SCONFIG_IDRAND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_IDRAND_SHIFT)) & I3C_SCONFIG_IDRAND_MASK) - -#define I3C_SCONFIG_OFFLINE_MASK (0x200U) -#define I3C_SCONFIG_OFFLINE_SHIFT (9U) -/*! OFFLINE - Offline - */ -#define I3C_SCONFIG_OFFLINE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK) - -#define I3C_SCONFIG_BAMATCH_MASK (0xFF0000U) -#define I3C_SCONFIG_BAMATCH_SHIFT (16U) -/*! BAMATCH - Bus available match - */ -#define I3C_SCONFIG_BAMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK) - -#define I3C_SCONFIG_SADDR_MASK (0xFE000000U) -#define I3C_SCONFIG_SADDR_SHIFT (25U) -/*! SADDR - Static address - */ -#define I3C_SCONFIG_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK) -/*! @} */ - -/*! @name SSTATUS - Slave Status */ -/*! @{ */ - -#define I3C_SSTATUS_STNOTSTOP_MASK (0x1U) -#define I3C_SSTATUS_STNOTSTOP_SHIFT (0U) -/*! STNOTSTOP - Status not stop - */ -#define I3C_SSTATUS_STNOTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK) - -#define I3C_SSTATUS_STMSG_MASK (0x2U) -#define I3C_SSTATUS_STMSG_SHIFT (1U) -/*! STMSG - Status message - */ -#define I3C_SSTATUS_STMSG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK) - -#define I3C_SSTATUS_STCCCH_MASK (0x4U) -#define I3C_SSTATUS_STCCCH_SHIFT (2U) -/*! STCCCH - Status Common Command Code Handler - */ -#define I3C_SSTATUS_STCCCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK) - -#define I3C_SSTATUS_STREQRD_MASK (0x8U) -#define I3C_SSTATUS_STREQRD_SHIFT (3U) -/*! STREQRD - Status request read - */ -#define I3C_SSTATUS_STREQRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK) - -#define I3C_SSTATUS_STREQWR_MASK (0x10U) -#define I3C_SSTATUS_STREQWR_SHIFT (4U) -/*! STREQWR - Status request write - */ -#define I3C_SSTATUS_STREQWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK) - -#define I3C_SSTATUS_STDAA_MASK (0x20U) -#define I3C_SSTATUS_STDAA_SHIFT (5U) -/*! STDAA - Status Dynamic Address Assignment - */ -#define I3C_SSTATUS_STDAA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK) - -#define I3C_SSTATUS_STHDR_MASK (0x40U) -#define I3C_SSTATUS_STHDR_SHIFT (6U) -/*! STHDR - Status High Data Rate - */ -#define I3C_SSTATUS_STHDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK) - -#define I3C_SSTATUS_START_MASK (0x100U) -#define I3C_SSTATUS_START_SHIFT (8U) -/*! START - Start - */ -#define I3C_SSTATUS_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK) - -#define I3C_SSTATUS_MATCHED_MASK (0x200U) -#define I3C_SSTATUS_MATCHED_SHIFT (9U) -/*! MATCHED - Matched - */ -#define I3C_SSTATUS_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK) - -#define I3C_SSTATUS_STOP_MASK (0x400U) -#define I3C_SSTATUS_STOP_SHIFT (10U) -/*! STOP - Stop - */ -#define I3C_SSTATUS_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK) - -#define I3C_SSTATUS_RX_PEND_MASK (0x800U) -#define I3C_SSTATUS_RX_PEND_SHIFT (11U) -/*! RX_PEND - Received message pending - */ -#define I3C_SSTATUS_RX_PEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK) - -#define I3C_SSTATUS_TXNOTFULL_MASK (0x1000U) -#define I3C_SSTATUS_TXNOTFULL_SHIFT (12U) -/*! TXNOTFULL - Transmit buffer is not full - */ -#define I3C_SSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK) - -#define I3C_SSTATUS_DACHG_MASK (0x2000U) -#define I3C_SSTATUS_DACHG_SHIFT (13U) -/*! DACHG - DACHG - */ -#define I3C_SSTATUS_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK) - -#define I3C_SSTATUS_CCC_MASK (0x4000U) -#define I3C_SSTATUS_CCC_SHIFT (14U) -/*! CCC - Common Command Code - */ -#define I3C_SSTATUS_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK) - -#define I3C_SSTATUS_ERRWARN_MASK (0x8000U) -#define I3C_SSTATUS_ERRWARN_SHIFT (15U) -/*! ERRWARN - Error warning - */ -#define I3C_SSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK) - -#define I3C_SSTATUS_HDRMATCH_MASK (0x10000U) -#define I3C_SSTATUS_HDRMATCH_SHIFT (16U) -/*! HDRMATCH - High Data Rate command match - */ -#define I3C_SSTATUS_HDRMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK) - -#define I3C_SSTATUS_CHANDLED_MASK (0x20000U) -#define I3C_SSTATUS_CHANDLED_SHIFT (17U) -/*! CHANDLED - Common Command Code handled - */ -#define I3C_SSTATUS_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK) - -#define I3C_SSTATUS_EVENT_MASK (0x40000U) -#define I3C_SSTATUS_EVENT_SHIFT (18U) -/*! EVENT - Event - */ -#define I3C_SSTATUS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK) - -#define I3C_SSTATUS_EVDET_MASK (0x300000U) -#define I3C_SSTATUS_EVDET_SHIFT (20U) -/*! EVDET - Event details - * 0b00..NONE - * 0b01..NO_REQUEST - * 0b10..NACKED - * 0b11..ACKED - */ -#define I3C_SSTATUS_EVDET(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK) - -#define I3C_SSTATUS_IBIDIS_MASK (0x1000000U) -#define I3C_SSTATUS_IBIDIS_SHIFT (24U) -/*! IBIDIS - In-Band Interrupts are disabled - */ -#define I3C_SSTATUS_IBIDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK) - -#define I3C_SSTATUS_MRDIS_MASK (0x2000000U) -#define I3C_SSTATUS_MRDIS_SHIFT (25U) -/*! MRDIS - Master requests are disabled - */ -#define I3C_SSTATUS_MRDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK) - -#define I3C_SSTATUS_HJDIS_MASK (0x8000000U) -#define I3C_SSTATUS_HJDIS_SHIFT (27U) -/*! HJDIS - Hot-Join is disabled - */ -#define I3C_SSTATUS_HJDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK) - -#define I3C_SSTATUS_ACTSTATE_MASK (0x30000000U) -#define I3C_SSTATUS_ACTSTATE_SHIFT (28U) -/*! ACTSTATE - Activity state from Common Command Codes (CCC) - * 0b00..NO_LATENCY - * 0b01..LATENCY_1MS - * 0b10..LATENCY_100MS - * 0b11..LATENCY_10S - */ -#define I3C_SSTATUS_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK) - -#define I3C_SSTATUS_TIMECTRL_MASK (0xC0000000U) -#define I3C_SSTATUS_TIMECTRL_SHIFT (30U) -/*! TIMECTRL - Time control - * 0b00..NO_TIME_CONTROL - * 0b01.. - * 0b10..ASYNC_MODE - * 0b11.. - */ -#define I3C_SSTATUS_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK) -/*! @} */ - -/*! @name SCTRL - Slave Control */ -/*! @{ */ - -#define I3C_SCTRL_EVENT_MASK (0x3U) -#define I3C_SCTRL_EVENT_SHIFT (0U) -/*! EVENT - EVENT - * 0b00..NORMAL_MODE - * 0b01..IBI - * 0b10..MASTER_REQUEST - * 0b11..HOT_JOIN_REQUEST - */ -#define I3C_SCTRL_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EVENT_SHIFT)) & I3C_SCTRL_EVENT_MASK) - -#define I3C_SCTRL_EXTDATA_MASK (0x8U) -#define I3C_SCTRL_EXTDATA_SHIFT (3U) -/*! EXTDATA - Extended Data - */ -#define I3C_SCTRL_EXTDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EXTDATA_SHIFT)) & I3C_SCTRL_EXTDATA_MASK) - -#define I3C_SCTRL_IBIDATA_MASK (0xFF00U) -#define I3C_SCTRL_IBIDATA_SHIFT (8U) -/*! IBIDATA - In-Band Interrupt data - */ -#define I3C_SCTRL_IBIDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_IBIDATA_SHIFT)) & I3C_SCTRL_IBIDATA_MASK) - -#define I3C_SCTRL_PENDINT_MASK (0xF0000U) -#define I3C_SCTRL_PENDINT_SHIFT (16U) -/*! PENDINT - Pending interrupt - */ -#define I3C_SCTRL_PENDINT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_PENDINT_SHIFT)) & I3C_SCTRL_PENDINT_MASK) - -#define I3C_SCTRL_ACTSTATE_MASK (0x300000U) -#define I3C_SCTRL_ACTSTATE_SHIFT (20U) -/*! ACTSTATE - Activity state (of slave) - */ -#define I3C_SCTRL_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_ACTSTATE_SHIFT)) & I3C_SCTRL_ACTSTATE_MASK) - -#define I3C_SCTRL_VENDINFO_MASK (0xFF000000U) -#define I3C_SCTRL_VENDINFO_SHIFT (24U) -/*! VENDINFO - Vendor information - */ -#define I3C_SCTRL_VENDINFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_VENDINFO_SHIFT)) & I3C_SCTRL_VENDINFO_MASK) -/*! @} */ - -/*! @name SINTSET - Slave Interrupt Set */ -/*! @{ */ - -#define I3C_SINTSET_START_MASK (0x100U) -#define I3C_SINTSET_START_SHIFT (8U) -/*! START - Start interrupt enable - */ -#define I3C_SINTSET_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK) - -#define I3C_SINTSET_MATCHED_MASK (0x200U) -#define I3C_SINTSET_MATCHED_SHIFT (9U) -/*! MATCHED - Match interrupt enable - */ -#define I3C_SINTSET_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK) - -#define I3C_SINTSET_STOP_MASK (0x400U) -#define I3C_SINTSET_STOP_SHIFT (10U) -/*! STOP - Stop interrupt enable - */ -#define I3C_SINTSET_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK) - -#define I3C_SINTSET_RXPEND_MASK (0x800U) -#define I3C_SINTSET_RXPEND_SHIFT (11U) -/*! RXPEND - Receive interrupt enable - */ -#define I3C_SINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK) - -#define I3C_SINTSET_TXSEND_MASK (0x1000U) -#define I3C_SINTSET_TXSEND_SHIFT (12U) -/*! TXSEND - Transmit interrupt enable - */ -#define I3C_SINTSET_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK) - -#define I3C_SINTSET_DACHG_MASK (0x2000U) -#define I3C_SINTSET_DACHG_SHIFT (13U) -/*! DACHG - Dynamic address change interrupt enable - */ -#define I3C_SINTSET_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK) - -#define I3C_SINTSET_CCC_MASK (0x4000U) -#define I3C_SINTSET_CCC_SHIFT (14U) -/*! CCC - Common Command Code (CCC) (that was not handled by I3C module) interrupt enable - */ -#define I3C_SINTSET_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK) - -#define I3C_SINTSET_ERRWARN_MASK (0x8000U) -#define I3C_SINTSET_ERRWARN_SHIFT (15U) -/*! ERRWARN - Error/warning interrupt enable - */ -#define I3C_SINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK) - -#define I3C_SINTSET_DDRMATCHED_MASK (0x10000U) -#define I3C_SINTSET_DDRMATCHED_SHIFT (16U) -/*! DDRMATCHED - Double Data Rate (DDR) interrupt enable - */ -#define I3C_SINTSET_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK) - -#define I3C_SINTSET_CHANDLED_MASK (0x20000U) -#define I3C_SINTSET_CHANDLED_SHIFT (17U) -/*! CHANDLED - Common Command Code (CCC) (that was handled by I3C module) interrupt enable - */ -#define I3C_SINTSET_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK) - -#define I3C_SINTSET_EVENT_MASK (0x40000U) -#define I3C_SINTSET_EVENT_SHIFT (18U) -/*! EVENT - Event interrupt enable - */ -#define I3C_SINTSET_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK) -/*! @} */ - -/*! @name SINTCLR - Slave Interrupt Clear */ -/*! @{ */ - -#define I3C_SINTCLR_START_MASK (0x100U) -#define I3C_SINTCLR_START_SHIFT (8U) -/*! START - START interrupt enable clear - */ -#define I3C_SINTCLR_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK) - -#define I3C_SINTCLR_MATCHED_MASK (0x200U) -#define I3C_SINTCLR_MATCHED_SHIFT (9U) -/*! MATCHED - MATCHED interrupt enable clear - */ -#define I3C_SINTCLR_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK) - -#define I3C_SINTCLR_STOP_MASK (0x400U) -#define I3C_SINTCLR_STOP_SHIFT (10U) -/*! STOP - STOP interrupt enable clear - */ -#define I3C_SINTCLR_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK) - -#define I3C_SINTCLR_RXPEND_MASK (0x800U) -#define I3C_SINTCLR_RXPEND_SHIFT (11U) -/*! RXPEND - RXPEND interrupt enable clear - */ -#define I3C_SINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK) - -#define I3C_SINTCLR_TXSEND_MASK (0x1000U) -#define I3C_SINTCLR_TXSEND_SHIFT (12U) -/*! TXSEND - TXSEND interrupt enable clear - */ -#define I3C_SINTCLR_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK) - -#define I3C_SINTCLR_DACHG_MASK (0x2000U) -#define I3C_SINTCLR_DACHG_SHIFT (13U) -/*! DACHG - DACHG interrupt enable clear - */ -#define I3C_SINTCLR_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DACHG_SHIFT)) & I3C_SINTCLR_DACHG_MASK) - -#define I3C_SINTCLR_CCC_MASK (0x4000U) -#define I3C_SINTCLR_CCC_SHIFT (14U) -/*! CCC - CCC interrupt enable clear - */ -#define I3C_SINTCLR_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CCC_SHIFT)) & I3C_SINTCLR_CCC_MASK) - -#define I3C_SINTCLR_ERRWARN_MASK (0x8000U) -#define I3C_SINTCLR_ERRWARN_SHIFT (15U) -/*! ERRWARN - ERRWARN interrupt enable clear - */ -#define I3C_SINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK) - -#define I3C_SINTCLR_DDRMATCHED_MASK (0x10000U) -#define I3C_SINTCLR_DDRMATCHED_SHIFT (16U) -/*! DDRMATCHED - DDRMATCHED interrupt enable clear - */ -#define I3C_SINTCLR_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DDRMATCHED_SHIFT)) & I3C_SINTCLR_DDRMATCHED_MASK) - -#define I3C_SINTCLR_CHANDLED_MASK (0x20000U) -#define I3C_SINTCLR_CHANDLED_SHIFT (17U) -/*! CHANDLED - CHANDLED interrupt enable clear - */ -#define I3C_SINTCLR_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CHANDLED_SHIFT)) & I3C_SINTCLR_CHANDLED_MASK) - -#define I3C_SINTCLR_EVENT_MASK (0x40000U) -#define I3C_SINTCLR_EVENT_SHIFT (18U) -/*! EVENT - EVENT interrupt enable clear - */ -#define I3C_SINTCLR_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_EVENT_SHIFT)) & I3C_SINTCLR_EVENT_MASK) -/*! @} */ - -/*! @name SINTMASKED - Slave Interrupt Mask */ -/*! @{ */ - -#define I3C_SINTMASKED_START_MASK (0x100U) -#define I3C_SINTMASKED_START_SHIFT (8U) -/*! START - START interrupt mask - */ -#define I3C_SINTMASKED_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK) - -#define I3C_SINTMASKED_MATCHED_MASK (0x200U) -#define I3C_SINTMASKED_MATCHED_SHIFT (9U) -/*! MATCHED - MATCHED interrupt mask - */ -#define I3C_SINTMASKED_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK) - -#define I3C_SINTMASKED_STOP_MASK (0x400U) -#define I3C_SINTMASKED_STOP_SHIFT (10U) -/*! STOP - STOP interrupt mask - */ -#define I3C_SINTMASKED_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK) - -#define I3C_SINTMASKED_RXPEND_MASK (0x800U) -#define I3C_SINTMASKED_RXPEND_SHIFT (11U) -/*! RXPEND - RXPEND interrupt mask - */ -#define I3C_SINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK) - -#define I3C_SINTMASKED_TXSEND_MASK (0x1000U) -#define I3C_SINTMASKED_TXSEND_SHIFT (12U) -/*! TXSEND - TXSEND interrupt mask - */ -#define I3C_SINTMASKED_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK) - -#define I3C_SINTMASKED_DACHG_MASK (0x2000U) -#define I3C_SINTMASKED_DACHG_SHIFT (13U) -/*! DACHG - DACHG interrupt mask - */ -#define I3C_SINTMASKED_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DACHG_SHIFT)) & I3C_SINTMASKED_DACHG_MASK) - -#define I3C_SINTMASKED_CCC_MASK (0x4000U) -#define I3C_SINTMASKED_CCC_SHIFT (14U) -/*! CCC - CCC interrupt mask - */ -#define I3C_SINTMASKED_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CCC_SHIFT)) & I3C_SINTMASKED_CCC_MASK) - -#define I3C_SINTMASKED_ERRWARN_MASK (0x8000U) -#define I3C_SINTMASKED_ERRWARN_SHIFT (15U) -/*! ERRWARN - ERRWARN interrupt mask - */ -#define I3C_SINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK) - -#define I3C_SINTMASKED_DDRMATCHED_MASK (0x10000U) -#define I3C_SINTMASKED_DDRMATCHED_SHIFT (16U) -/*! DDRMATCHED - DDRMATCHED interrupt mask - */ -#define I3C_SINTMASKED_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DDRMATCHED_SHIFT)) & I3C_SINTMASKED_DDRMATCHED_MASK) - -#define I3C_SINTMASKED_CHANDLED_MASK (0x20000U) -#define I3C_SINTMASKED_CHANDLED_SHIFT (17U) -/*! CHANDLED - CHANDLED interrupt mask - */ -#define I3C_SINTMASKED_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CHANDLED_SHIFT)) & I3C_SINTMASKED_CHANDLED_MASK) - -#define I3C_SINTMASKED_EVENT_MASK (0x40000U) -#define I3C_SINTMASKED_EVENT_SHIFT (18U) -/*! EVENT - EVENT interrupt mask - */ -#define I3C_SINTMASKED_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_EVENT_SHIFT)) & I3C_SINTMASKED_EVENT_MASK) -/*! @} */ - -/*! @name SERRWARN - Slave Errors and Warnings */ -/*! @{ */ - -#define I3C_SERRWARN_ORUN_MASK (0x1U) -#define I3C_SERRWARN_ORUN_SHIFT (0U) -/*! ORUN - Overrun error - */ -#define I3C_SERRWARN_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK) - -#define I3C_SERRWARN_URUN_MASK (0x2U) -#define I3C_SERRWARN_URUN_SHIFT (1U) -/*! URUN - Underrun error - */ -#define I3C_SERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK) - -#define I3C_SERRWARN_URUNNACK_MASK (0x4U) -#define I3C_SERRWARN_URUNNACK_SHIFT (2U) -/*! URUNNACK - Underrun and Not Acknowledged (NACKed) error - */ -#define I3C_SERRWARN_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK) - -#define I3C_SERRWARN_TERM_MASK (0x8U) -#define I3C_SERRWARN_TERM_SHIFT (3U) -/*! TERM - Terminated error - */ -#define I3C_SERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK) - -#define I3C_SERRWARN_INVSTART_MASK (0x10U) -#define I3C_SERRWARN_INVSTART_SHIFT (4U) -/*! INVSTART - Invalid start error - */ -#define I3C_SERRWARN_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK) - -#define I3C_SERRWARN_SPAR_MASK (0x100U) -#define I3C_SERRWARN_SPAR_SHIFT (8U) -/*! SPAR - SDR parity error - */ -#define I3C_SERRWARN_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK) - -#define I3C_SERRWARN_HPAR_MASK (0x200U) -#define I3C_SERRWARN_HPAR_SHIFT (9U) -/*! HPAR - HDR parity error - */ -#define I3C_SERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK) - -#define I3C_SERRWARN_HCRC_MASK (0x400U) -#define I3C_SERRWARN_HCRC_SHIFT (10U) -/*! HCRC - HDR-DDR CRC error - */ -#define I3C_SERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK) - -#define I3C_SERRWARN_S0S1_MASK (0x800U) -#define I3C_SERRWARN_S0S1_SHIFT (11U) -/*! S0S1 - S0 or S1 error - */ -#define I3C_SERRWARN_S0S1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK) - -#define I3C_SERRWARN_OREAD_MASK (0x10000U) -#define I3C_SERRWARN_OREAD_SHIFT (16U) -/*! OREAD - Over-read error - */ -#define I3C_SERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK) - -#define I3C_SERRWARN_OWRITE_MASK (0x20000U) -#define I3C_SERRWARN_OWRITE_SHIFT (17U) -/*! OWRITE - Over-write error - */ -#define I3C_SERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK) -/*! @} */ - -/*! @name SDMACTRL - Slave DMA Control */ -/*! @{ */ - -#define I3C_SDMACTRL_DMAFB_MASK (0x3U) -#define I3C_SDMACTRL_DMAFB_SHIFT (0U) -/*! DMAFB - DMA Read (From-bus) trigger - * 0b00..DMA not used - * 0b01..DMA is enabled for 1 frame - * 0b10..DMA enable - * 0b11.. - */ -#define I3C_SDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK) - -#define I3C_SDMACTRL_DMATB_MASK (0xCU) -#define I3C_SDMACTRL_DMATB_SHIFT (2U) -/*! DMATB - DMA Write (To-bus) trigger - * 0b00..NOT_USED - * 0b01..ENABLE_ONE_FRAME - * 0b10..ENABLE - * 0b11.. - */ -#define I3C_SDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK) - -#define I3C_SDMACTRL_DMAWIDTH_MASK (0x30U) -#define I3C_SDMACTRL_DMAWIDTH_SHIFT (4U) -/*! DMAWIDTH - Width of DMA operations - * 0b00, 0b01..BYTE, Default = 1 - * 0b10..HALF_WORD - * 0b11.. - */ -#define I3C_SDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK) -/*! @} */ - -/*! @name SDATACTRL - Slave Data Control */ -/*! @{ */ - -#define I3C_SDATACTRL_FLUSHTB_MASK (0x1U) -#define I3C_SDATACTRL_FLUSHTB_SHIFT (0U) -/*! FLUSHTB - Flush the to-bus buffer/FIFO - */ -#define I3C_SDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK) - -#define I3C_SDATACTRL_FLUSHFB_MASK (0x2U) -#define I3C_SDATACTRL_FLUSHFB_SHIFT (1U) -/*! FLUSHFB - Flushes the from-bus buffer/FIFO - */ -#define I3C_SDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK) - -#define I3C_SDATACTRL_UNLOCK_MASK (0x8U) -#define I3C_SDATACTRL_UNLOCK_SHIFT (3U) -/*! UNLOCK - Unlock - */ -#define I3C_SDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK) - -#define I3C_SDATACTRL_TXTRIG_MASK (0x30U) -#define I3C_SDATACTRL_TXTRIG_SHIFT (4U) -/*! TXTRIG - Trigger level for TX FIFO emptiness - * 0b00..Trigger on empty - * 0b01..Trigger on ¼ full or less - * 0b10..Trigger on .5 full or less - * 0b11..Trigger on 1 less than full or less (Default) - */ -#define I3C_SDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK) - -#define I3C_SDATACTRL_RXTRIG_MASK (0xC0U) -#define I3C_SDATACTRL_RXTRIG_SHIFT (6U) -/*! RXTRIG - Trigger level for RX FIFO fullness - * 0b00..Trigger on not empty - * 0b01..Trigger on ¼ or more full - * 0b10..Trigger on .5 or more full - * 0b11..Trigger on 3/4 or more full - */ -#define I3C_SDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK) - -#define I3C_SDATACTRL_TXCOUNT_MASK (0x1F0000U) -#define I3C_SDATACTRL_TXCOUNT_SHIFT (16U) -/*! TXCOUNT - Count of bytes in TX - */ -#define I3C_SDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK) - -#define I3C_SDATACTRL_RXCOUNT_MASK (0x1F000000U) -#define I3C_SDATACTRL_RXCOUNT_SHIFT (24U) -/*! RXCOUNT - Count of bytes in RX - */ -#define I3C_SDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK) - -#define I3C_SDATACTRL_TXFULL_MASK (0x40000000U) -#define I3C_SDATACTRL_TXFULL_SHIFT (30U) -/*! TXFULL - TX is full - * 0b1..TX is full - * 0b0..TX is not full - */ -#define I3C_SDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK) - -#define I3C_SDATACTRL_RXEMPTY_MASK (0x80000000U) -#define I3C_SDATACTRL_RXEMPTY_SHIFT (31U) -/*! RXEMPTY - RX is empty - * 0b1..RX is empty - * 0b0..RX is not empty - */ -#define I3C_SDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK) -/*! @} */ - -/*! @name SWDATAB - Slave Write Data Byte */ -/*! @{ */ - -#define I3C_SWDATAB_DATA_MASK (0xFFU) -#define I3C_SWDATAB_DATA_SHIFT (0U) -/*! DATA - The data byte to send to the master - */ -#define I3C_SWDATAB_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK) - -#define I3C_SWDATAB_END_MASK (0x100U) -#define I3C_SWDATAB_END_SHIFT (8U) -/*! END - End - */ -#define I3C_SWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK) - -#define I3C_SWDATAB_END_ALSO_MASK (0x10000U) -#define I3C_SWDATAB_END_ALSO_SHIFT (16U) -/*! END_ALSO - End also - */ -#define I3C_SWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK) -/*! @} */ - -/*! @name SWDATABE - Slave Write Data Byte End */ -/*! @{ */ - -#define I3C_SWDATABE_DATA_MASK (0xFFU) -#define I3C_SWDATABE_DATA_SHIFT (0U) -/*! DATA - The data byte to send to the master - */ -#define I3C_SWDATABE_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK) -/*! @} */ - -/*! @name SWDATAH - Slave Write Data Half-word */ -/*! @{ */ - -#define I3C_SWDATAH_DATA0_MASK (0xFFU) -#define I3C_SWDATAH_DATA0_SHIFT (0U) -/*! DATA0 - The 1st byte to send to the master - */ -#define I3C_SWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK) - -#define I3C_SWDATAH_DATA1_MASK (0xFF00U) -#define I3C_SWDATAH_DATA1_SHIFT (8U) -/*! DATA1 - The 2nd byte to send to the master - */ -#define I3C_SWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK) - -#define I3C_SWDATAH_END_MASK (0x10000U) -#define I3C_SWDATAH_END_SHIFT (16U) -/*! END - End of message - */ -#define I3C_SWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK) -/*! @} */ - -/*! @name SWDATAHE - Slave Write Data Half-word End */ -/*! @{ */ - -#define I3C_SWDATAHE_DATA0_MASK (0xFFU) -#define I3C_SWDATAHE_DATA0_SHIFT (0U) -/*! DATA0 - The 1st byte to send to the master - */ -#define I3C_SWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK) - -#define I3C_SWDATAHE_DATA1_MASK (0xFF00U) -#define I3C_SWDATAHE_DATA1_SHIFT (8U) -/*! DATA1 - The 2nd byte to send to the master - */ -#define I3C_SWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK) -/*! @} */ - -/*! @name SRDATAB - Slave Read Data Byte */ -/*! @{ */ - -#define I3C_SRDATAB_DATA0_MASK (0xFFU) -#define I3C_SRDATAB_DATA0_SHIFT (0U) -/*! DATA0 - Byte read from the master - */ -#define I3C_SRDATAB_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK) -/*! @} */ - -/*! @name SRDATAH - Slave Read Data Half-word */ -/*! @{ */ - -#define I3C_SRDATAH_LSB_MASK (0xFFU) -#define I3C_SRDATAH_LSB_SHIFT (0U) -/*! LSB - The 1st byte read from the slave - */ -#define I3C_SRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK) - -#define I3C_SRDATAH_MSB_MASK (0xFF00U) -#define I3C_SRDATAH_MSB_SHIFT (8U) -/*! MSB - The 2nd byte read from the slave - */ -#define I3C_SRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK) -/*! @} */ - -/*! @name SCAPABILITIES2 - Slave Capabilities 2 */ -/*! @{ */ - -#define I3C_SCAPABILITIES2_MAPCNT_MASK (0xFU) -#define I3C_SCAPABILITIES2_MAPCNT_SHIFT (0U) -/*! MAPCNT - Map Count - */ -#define I3C_SCAPABILITIES2_MAPCNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_MAPCNT_SHIFT)) & I3C_SCAPABILITIES2_MAPCNT_MASK) - -#define I3C_SCAPABILITIES2_I2C10B_MASK (0x10U) -#define I3C_SCAPABILITIES2_I2C10B_SHIFT (4U) -/*! I2C10B - I2C 10-bit Address - * 0b0..Does not support I2C10B - * 0b1..Supports I2C10B - */ -#define I3C_SCAPABILITIES2_I2C10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2C10B_SHIFT)) & I3C_SCAPABILITIES2_I2C10B_MASK) - -#define I3C_SCAPABILITIES2_I2CRST_MASK (0x20U) -#define I3C_SCAPABILITIES2_I2CRST_SHIFT (5U) -/*! I2CRST - I2C SW Reset - * 0b0..Does not support I2CRST - * 0b1..Supports I2CRST - */ -#define I3C_SCAPABILITIES2_I2CRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CRST_SHIFT)) & I3C_SCAPABILITIES2_I2CRST_MASK) - -#define I3C_SCAPABILITIES2_I2CDEVID_MASK (0x40U) -#define I3C_SCAPABILITIES2_I2CDEVID_SHIFT (6U) -/*! I2CDEVID - I2C Device ID - * 0b0..Does not support I2CDEVID - * 0b1..Supports I2CDEVID - */ -#define I3C_SCAPABILITIES2_I2CDEVID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CDEVID_SHIFT)) & I3C_SCAPABILITIES2_I2CDEVID_MASK) - -#define I3C_SCAPABILITIES2_IBIEXT_MASK (0x100U) -#define I3C_SCAPABILITIES2_IBIEXT_SHIFT (8U) -/*! IBIEXT - In-Band Interrupt EXTDATA - * 0b0..Does not support IBIEXT - * 0b1..Supports IBIEXT - */ -#define I3C_SCAPABILITIES2_IBIEXT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIEXT_SHIFT)) & I3C_SCAPABILITIES2_IBIEXT_MASK) - -#define I3C_SCAPABILITIES2_IBIXREG_MASK (0x200U) -#define I3C_SCAPABILITIES2_IBIXREG_SHIFT (9U) -/*! IBIXREG - In-Band Interrupt Extended Register - * 0b0..Does not support IBIXREG - * 0b1..Supports IBIXREG - */ -#define I3C_SCAPABILITIES2_IBIXREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIXREG_SHIFT)) & I3C_SCAPABILITIES2_IBIXREG_MASK) - -#define I3C_SCAPABILITIES2_SLVRST_MASK (0x20000U) -#define I3C_SCAPABILITIES2_SLVRST_SHIFT (17U) -/*! SLVRST - Slave Reset - * 0b0..Does not support Slave Reset - * 0b1..Supports Slave Reset - */ -#define I3C_SCAPABILITIES2_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SLVRST_SHIFT)) & I3C_SCAPABILITIES2_SLVRST_MASK) - -#define I3C_SCAPABILITIES2_GROUP_MASK (0xC0000U) -#define I3C_SCAPABILITIES2_GROUP_SHIFT (18U) -/*! GROUP - GROUP - * 0b00..Does not supports v1.1 Group addressing - * 0b01..Supports one group - * 0b10..Supports two groups - * 0b11..Supports three groups - */ -#define I3C_SCAPABILITIES2_GROUP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_GROUP_SHIFT)) & I3C_SCAPABILITIES2_GROUP_MASK) - -#define I3C_SCAPABILITIES2_AASA_MASK (0x200000U) -#define I3C_SCAPABILITIES2_AASA_SHIFT (21U) -/*! AASA - Supports SETAASA - */ -#define I3C_SCAPABILITIES2_AASA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_AASA_SHIFT)) & I3C_SCAPABILITIES2_AASA_MASK) - -#define I3C_SCAPABILITIES2_SSTSUB_MASK (0x400000U) -#define I3C_SCAPABILITIES2_SSTSUB_SHIFT (22U) -/*! SSTSUB - Slave-Slave(s)-Tunnel subscriber capable - */ -#define I3C_SCAPABILITIES2_SSTSUB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTSUB_SHIFT)) & I3C_SCAPABILITIES2_SSTSUB_MASK) - -#define I3C_SCAPABILITIES2_SSTWR_MASK (0x800000U) -#define I3C_SCAPABILITIES2_SSTWR_SHIFT (23U) -/*! SSTWR - Slave-Slave(s)-Tunnel write capable - */ -#define I3C_SCAPABILITIES2_SSTWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTWR_SHIFT)) & I3C_SCAPABILITIES2_SSTWR_MASK) -/*! @} */ - -/*! @name SCAPABILITIES - Slave Capabilities */ -/*! @{ */ - -#define I3C_SCAPABILITIES_IDENA_MASK (0x3U) -#define I3C_SCAPABILITIES_IDENA_SHIFT (0U) -/*! IDENA - ID 48b handler - * 0b00..APPLICATION - * 0b01..HW - * 0b10..HW_BUT - * 0b11..PARTNO - */ -#define I3C_SCAPABILITIES_IDENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDENA_SHIFT)) & I3C_SCAPABILITIES_IDENA_MASK) - -#define I3C_SCAPABILITIES_IDREG_MASK (0x3CU) -#define I3C_SCAPABILITIES_IDREG_SHIFT (2U) -/*! IDREG - ID register - */ -#define I3C_SCAPABILITIES_IDREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK) - -#define I3C_SCAPABILITIES_HDRSUPP_MASK (0xC0U) -#define I3C_SCAPABILITIES_HDRSUPP_SHIFT (6U) -/*! HDRSUPP - HDR support - */ -#define I3C_SCAPABILITIES_HDRSUPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK) - -#define I3C_SCAPABILITIES_MASTER_MASK (0x200U) -#define I3C_SCAPABILITIES_MASTER_SHIFT (9U) -/*! MASTER - Master - * 0b0..MASTERNOTSUPPORTED - * 0b1..MASTERSUPPORTED - */ -#define I3C_SCAPABILITIES_MASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK) - -#define I3C_SCAPABILITIES_SADDR_MASK (0xC00U) -#define I3C_SCAPABILITIES_SADDR_SHIFT (10U) -/*! SADDR - Static address - * 0b00..NO_STATIC - * 0b01..STATIC - * 0b10..HW_CONTROL - * 0b11..CONFIG - */ -#define I3C_SCAPABILITIES_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK) - -#define I3C_SCAPABILITIES_CCCHANDLE_MASK (0xF000U) -#define I3C_SCAPABILITIES_CCCHANDLE_SHIFT (12U) -/*! CCCHANDLE - Common Command Codes (CCC) handling - */ -#define I3C_SCAPABILITIES_CCCHANDLE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK) - -#define I3C_SCAPABILITIES_IBI_MR_HJ_MASK (0x1F0000U) -#define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT (16U) -/*! IBI_MR_HJ - In-Band Interrupts, Master Requests, Hot Join events - */ -#define I3C_SCAPABILITIES_IBI_MR_HJ(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK) - -#define I3C_SCAPABILITIES_TIMECTRL_MASK (0x200000U) -#define I3C_SCAPABILITIES_TIMECTRL_SHIFT (21U) -/*! TIMECTRL - Time control - * 0b0..NO_TIME_CONTROL_TYPE - * 0b1..ATLEAST1_TIME_CONTROL - */ -#define I3C_SCAPABILITIES_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK) - -#define I3C_SCAPABILITIES_EXTFIFO_MASK (0x3800000U) -#define I3C_SCAPABILITIES_EXTFIFO_SHIFT (23U) -/*! EXTFIFO - External FIFO - * 0b000..NO_EXT_FIFO - * 0b001..STD_EXT_FIFO - * 0b010..REQUEST_EXT_FIFO - * 0b011.. - */ -#define I3C_SCAPABILITIES_EXTFIFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK) - -#define I3C_SCAPABILITIES_FIFOTX_MASK (0xC000000U) -#define I3C_SCAPABILITIES_FIFOTX_SHIFT (26U) -/*! FIFOTX - FIFO transmit - * 0b00..FIFO_2BYTE - * 0b01..FIFO_4BYTE: 4-byte TX FIFO - * 0b10..FIFO_8BYTE: 8-byte TX FIFO - * 0b11..FIFO_16BYTE: 16-byte TX FIFO or larger - */ -#define I3C_SCAPABILITIES_FIFOTX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK) - -#define I3C_SCAPABILITIES_FIFORX_MASK (0x30000000U) -#define I3C_SCAPABILITIES_FIFORX_SHIFT (28U) -/*! FIFORX - FIFO receive - * 0b00..FIFO_2BYTE - * 0b01..FIFO_4BYTE - * 0b10..FIFO_8BYTE - * 0b11..FIFO_16BYTE - */ -#define I3C_SCAPABILITIES_FIFORX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK) - -#define I3C_SCAPABILITIES_INT_MASK (0x40000000U) -#define I3C_SCAPABILITIES_INT_SHIFT (30U) -/*! INT - INT - * 0b1..Interrupts are supported - * 0b0..Interrupts are not supported - */ -#define I3C_SCAPABILITIES_INT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK) - -#define I3C_SCAPABILITIES_DMA_MASK (0x80000000U) -#define I3C_SCAPABILITIES_DMA_SHIFT (31U) -/*! DMA - DMA - * 0b1..DMA is supported - * 0b0..DMA is not supported - */ -#define I3C_SCAPABILITIES_DMA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK) -/*! @} */ - -/*! @name SDYNADDR - Slave Dynamic Address */ -/*! @{ */ - -#define I3C_SDYNADDR_DAVALID_MASK (0x1U) -#define I3C_SDYNADDR_DAVALID_SHIFT (0U) -/*! DAVALID - DAVALID - * 0b0..DANOTASSIGNED: a Dynamic Address is not assigned - * 0b1..DAASSIGNED: a Dynamic Address is assigned - */ -#define I3C_SDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DAVALID_SHIFT)) & I3C_SDYNADDR_DAVALID_MASK) - -#define I3C_SDYNADDR_DADDR_MASK (0xFEU) -#define I3C_SDYNADDR_DADDR_SHIFT (1U) -/*! DADDR - Dynamic address - */ -#define I3C_SDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DADDR_SHIFT)) & I3C_SDYNADDR_DADDR_MASK) - -#define I3C_SDYNADDR_MAPSA_MASK (0x1000U) -#define I3C_SDYNADDR_MAPSA_SHIFT (12U) -/*! MAPSA - Map a Static Address - */ -#define I3C_SDYNADDR_MAPSA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPSA_SHIFT)) & I3C_SDYNADDR_MAPSA_MASK) - -#define I3C_SDYNADDR_SA10B_MASK (0xE000U) -#define I3C_SDYNADDR_SA10B_SHIFT (13U) -/*! SA10B - 10bit Static Address - */ -#define I3C_SDYNADDR_SA10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_SA10B_SHIFT)) & I3C_SDYNADDR_SA10B_MASK) - -#define I3C_SDYNADDR_KEY_MASK (0xFFFF0000U) -#define I3C_SDYNADDR_KEY_SHIFT (16U) -/*! KEY - Key - */ -#define I3C_SDYNADDR_KEY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_KEY_SHIFT)) & I3C_SDYNADDR_KEY_MASK) -/*! @} */ - -/*! @name SMAXLIMITS - Slave Maximum Limits */ -/*! @{ */ - -#define I3C_SMAXLIMITS_MAXRD_MASK (0xFFFU) -#define I3C_SMAXLIMITS_MAXRD_SHIFT (0U) -/*! MAXRD - Maximum read length - */ -#define I3C_SMAXLIMITS_MAXRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXRD_SHIFT)) & I3C_SMAXLIMITS_MAXRD_MASK) - -#define I3C_SMAXLIMITS_MAXWR_MASK (0xFFF0000U) -#define I3C_SMAXLIMITS_MAXWR_SHIFT (16U) -/*! MAXWR - Maximum write length - */ -#define I3C_SMAXLIMITS_MAXWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXWR_SHIFT)) & I3C_SMAXLIMITS_MAXWR_MASK) -/*! @} */ - -/*! @name SIDPARTNO - Slave ID Part Number */ -/*! @{ */ - -#define I3C_SIDPARTNO_PARTNO_MASK (0xFFFFFFFFU) -#define I3C_SIDPARTNO_PARTNO_SHIFT (0U) -/*! PARTNO - Part number - */ -#define I3C_SIDPARTNO_PARTNO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK) -/*! @} */ - -/*! @name SIDEXT - Slave ID Extension */ -/*! @{ */ - -#define I3C_SIDEXT_DCR_MASK (0xFF00U) -#define I3C_SIDEXT_DCR_SHIFT (8U) -/*! DCR - Device Characteristic Register - */ -#define I3C_SIDEXT_DCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_DCR_SHIFT)) & I3C_SIDEXT_DCR_MASK) - -#define I3C_SIDEXT_BCR_MASK (0xFF0000U) -#define I3C_SIDEXT_BCR_SHIFT (16U) -/*! BCR - Bus Characteristics Register - */ -#define I3C_SIDEXT_BCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_BCR_SHIFT)) & I3C_SIDEXT_BCR_MASK) -/*! @} */ - -/*! @name SVENDORID - Slave Vendor ID */ -/*! @{ */ - -#define I3C_SVENDORID_VID_MASK (0x7FFFU) -#define I3C_SVENDORID_VID_SHIFT (0U) -/*! VID - Vendor ID - */ -#define I3C_SVENDORID_VID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SVENDORID_VID_SHIFT)) & I3C_SVENDORID_VID_MASK) -/*! @} */ - -/*! @name STCCLOCK - Slave Time Control Clock */ -/*! @{ */ - -#define I3C_STCCLOCK_ACCURACY_MASK (0xFFU) -#define I3C_STCCLOCK_ACCURACY_SHIFT (0U) -/*! ACCURACY - Clock accuracy - */ -#define I3C_STCCLOCK_ACCURACY(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_ACCURACY_SHIFT)) & I3C_STCCLOCK_ACCURACY_MASK) - -#define I3C_STCCLOCK_FREQ_MASK (0xFF00U) -#define I3C_STCCLOCK_FREQ_SHIFT (8U) -/*! FREQ - Clock frequency - */ -#define I3C_STCCLOCK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_FREQ_SHIFT)) & I3C_STCCLOCK_FREQ_MASK) -/*! @} */ - -/*! @name SMSGMAPADDR - Slave Message Map Address */ -/*! @{ */ - -#define I3C_SMSGMAPADDR_MAPLAST_MASK (0xFU) -#define I3C_SMSGMAPADDR_MAPLAST_SHIFT (0U) -/*! MAPLAST - Matched Address Index - */ -#define I3C_SMSGMAPADDR_MAPLAST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLAST_SHIFT)) & I3C_SMSGMAPADDR_MAPLAST_MASK) - -#define I3C_SMSGMAPADDR_LASTSTATIC_MASK (0x10U) -#define I3C_SMSGMAPADDR_LASTSTATIC_SHIFT (4U) -/*! LASTSTATIC - Last Static Address Matched - */ -#define I3C_SMSGMAPADDR_LASTSTATIC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_LASTSTATIC_SHIFT)) & I3C_SMSGMAPADDR_LASTSTATIC_MASK) - -#define I3C_SMSGMAPADDR_MAPLASTM1_MASK (0xF00U) -#define I3C_SMSGMAPADDR_MAPLASTM1_SHIFT (8U) -/*! MAPLASTM1 - Matched Previous Address Index 1 - */ -#define I3C_SMSGMAPADDR_MAPLASTM1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM1_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM1_MASK) - -#define I3C_SMSGMAPADDR_MAPLASTM2_MASK (0xF0000U) -#define I3C_SMSGMAPADDR_MAPLASTM2_SHIFT (16U) -/*! MAPLASTM2 - Matched Previous Index 2 - */ -#define I3C_SMSGMAPADDR_MAPLASTM2(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM2_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM2_MASK) -/*! @} */ - -/*! @name MCTRL - Master Main Control */ -/*! @{ */ - -#define I3C_MCTRL_REQUEST_MASK (0x7U) -#define I3C_MCTRL_REQUEST_SHIFT (0U) -/*! REQUEST - Request - * 0b000..NONE - * 0b001..EMITSTARTADDR - * 0b010..EMITSTOP - * 0b011..IBIACKNACK - * 0b100..PROCESSDAA - * 0b101.. - * 0b110..FORCEEXIT and SLAVERESET - * 0b111..AUTOIBI - */ -#define I3C_MCTRL_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK) - -#define I3C_MCTRL_TYPE_MASK (0x30U) -#define I3C_MCTRL_TYPE_SHIFT (4U) -/*! TYPE - Bus type with EmitStartAddr - * 0b00..I3C - * 0b01..I2C - * 0b10..DDR - * 0b11.. - */ -#define I3C_MCTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK) - -#define I3C_MCTRL_IBIRESP_MASK (0xC0U) -#define I3C_MCTRL_IBIRESP_SHIFT (6U) -/*! IBIRESP - In-Band Interrupt (IBI) response - * 0b00..ACK - * 0b01..NACK - * 0b10..ACK_WITH_MANDATORY - * 0b11..MANUAL - */ -#define I3C_MCTRL_IBIRESP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_IBIRESP_SHIFT)) & I3C_MCTRL_IBIRESP_MASK) - -#define I3C_MCTRL_DIR_MASK (0x100U) -#define I3C_MCTRL_DIR_SHIFT (8U) -/*! DIR - DIR - * 0b0..DIRWRITE: Write - * 0b1..DIRREAD: Read - */ -#define I3C_MCTRL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK) - -#define I3C_MCTRL_ADDR_MASK (0xFE00U) -#define I3C_MCTRL_ADDR_SHIFT (9U) -/*! ADDR - Address - */ -#define I3C_MCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK) - -#define I3C_MCTRL_RDTERM_MASK (0xFF0000U) -#define I3C_MCTRL_RDTERM_SHIFT (16U) -/*! RDTERM - Read terminate - */ -#define I3C_MCTRL_RDTERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK) -/*! @} */ - -/*! @name MSTATUS - Master Status */ -/*! @{ */ - -#define I3C_MSTATUS_STATE_MASK (0x7U) -#define I3C_MSTATUS_STATE_SHIFT (0U) -/*! STATE - State of the master - * 0b000..IDLE: the bus has STOPped. - * 0b001..SLVREQ - * 0b010..MSGSDR - * 0b011..NORMACT - * 0b100..MSGDDR - * 0b101..DAA - * 0b110..IBIACK - * 0b111..IBIRCV - */ -#define I3C_MSTATUS_STATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK) - -#define I3C_MSTATUS_BETWEEN_MASK (0x10U) -#define I3C_MSTATUS_BETWEEN_SHIFT (4U) -/*! BETWEEN - Between - * 0b0..Inactive - * 0b1..Active - */ -#define I3C_MSTATUS_BETWEEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK) - -#define I3C_MSTATUS_NACKED_MASK (0x20U) -#define I3C_MSTATUS_NACKED_SHIFT (5U) -/*! NACKED - Not acknowledged - */ -#define I3C_MSTATUS_NACKED(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK) - -#define I3C_MSTATUS_IBITYPE_MASK (0xC0U) -#define I3C_MSTATUS_IBITYPE_SHIFT (6U) -/*! IBITYPE - In-Band Interrupt (IBI) type - * 0b00..NONE - * 0b01..IBI - * 0b10..MR - * 0b11..HJ - */ -#define I3C_MSTATUS_IBITYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK) - -#define I3C_MSTATUS_SLVSTART_MASK (0x100U) -#define I3C_MSTATUS_SLVSTART_SHIFT (8U) -/*! SLVSTART - Slave start - */ -#define I3C_MSTATUS_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK) - -#define I3C_MSTATUS_MCTRLDONE_MASK (0x200U) -#define I3C_MSTATUS_MCTRLDONE_SHIFT (9U) -/*! MCTRLDONE - Master control done - */ -#define I3C_MSTATUS_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK) - -#define I3C_MSTATUS_COMPLETE_MASK (0x400U) -#define I3C_MSTATUS_COMPLETE_SHIFT (10U) -/*! COMPLETE - COMPLETE - */ -#define I3C_MSTATUS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK) - -#define I3C_MSTATUS_RXPEND_MASK (0x800U) -#define I3C_MSTATUS_RXPEND_SHIFT (11U) -/*! RXPEND - RXPEND - */ -#define I3C_MSTATUS_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK) - -#define I3C_MSTATUS_TXNOTFULL_MASK (0x1000U) -#define I3C_MSTATUS_TXNOTFULL_SHIFT (12U) -/*! TXNOTFULL - TX buffer/FIFO not yet full - */ -#define I3C_MSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK) - -#define I3C_MSTATUS_IBIWON_MASK (0x2000U) -#define I3C_MSTATUS_IBIWON_SHIFT (13U) -/*! IBIWON - In-Band Interrupt (IBI) won - */ -#define I3C_MSTATUS_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK) - -#define I3C_MSTATUS_ERRWARN_MASK (0x8000U) -#define I3C_MSTATUS_ERRWARN_SHIFT (15U) -/*! ERRWARN - Error or warning - */ -#define I3C_MSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK) - -#define I3C_MSTATUS_NOWMASTER_MASK (0x80000U) -#define I3C_MSTATUS_NOWMASTER_SHIFT (19U) -/*! NOWMASTER - Now master (now this module is a master) - */ -#define I3C_MSTATUS_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK) - -#define I3C_MSTATUS_IBIADDR_MASK (0x7F000000U) -#define I3C_MSTATUS_IBIADDR_SHIFT (24U) -/*! IBIADDR - IBI address - */ -#define I3C_MSTATUS_IBIADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIADDR_SHIFT)) & I3C_MSTATUS_IBIADDR_MASK) -/*! @} */ - -/*! @name MIBIRULES - Master In-band Interrupt Registry and Rules */ -/*! @{ */ - -#define I3C_MIBIRULES_ADDR0_MASK (0x3FU) -#define I3C_MIBIRULES_ADDR0_SHIFT (0U) -/*! ADDR0 - ADDR0 - */ -#define I3C_MIBIRULES_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR0_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK) - -#define I3C_MIBIRULES_ADDR1_MASK (0xFC0U) -#define I3C_MIBIRULES_ADDR1_SHIFT (6U) -/*! ADDR1 - ADDR1 - */ -#define I3C_MIBIRULES_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR1_MASK) - -#define I3C_MIBIRULES_ADDR2_MASK (0x3F000U) -#define I3C_MIBIRULES_ADDR2_SHIFT (12U) -/*! ADDR2 - ADDR2 - */ -#define I3C_MIBIRULES_ADDR2(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR2_SHIFT)) & I3C_MIBIRULES_ADDR2_MASK) - -#define I3C_MIBIRULES_ADDR3_MASK (0xFC0000U) -#define I3C_MIBIRULES_ADDR3_SHIFT (18U) -/*! ADDR3 - ADDR3 - */ -#define I3C_MIBIRULES_ADDR3(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR3_SHIFT)) & I3C_MIBIRULES_ADDR3_MASK) - -#define I3C_MIBIRULES_ADDR4_MASK (0x3F000000U) -#define I3C_MIBIRULES_ADDR4_SHIFT (24U) -/*! ADDR4 - ADDR4 - */ -#define I3C_MIBIRULES_ADDR4(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR4_SHIFT)) & I3C_MIBIRULES_ADDR4_MASK) - -#define I3C_MIBIRULES_MSB0_MASK (0x40000000U) -#define I3C_MIBIRULES_MSB0_SHIFT (30U) -/*! MSB0 - Set Most Significant address Bit to 0 - */ -#define I3C_MIBIRULES_MSB0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK) - -#define I3C_MIBIRULES_NOBYTE_MASK (0x80000000U) -#define I3C_MIBIRULES_NOBYTE_SHIFT (31U) -/*! NOBYTE - No IBI byte - */ -#define I3C_MIBIRULES_NOBYTE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK) -/*! @} */ - -/*! @name MINTSET - Master Interrupt Set */ -/*! @{ */ - -#define I3C_MINTSET_SLVSTART_MASK (0x100U) -#define I3C_MINTSET_SLVSTART_SHIFT (8U) -/*! SLVSTART - Slave start interrupt enable - */ -#define I3C_MINTSET_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK) - -#define I3C_MINTSET_MCTRLDONE_MASK (0x200U) -#define I3C_MINTSET_MCTRLDONE_SHIFT (9U) -/*! MCTRLDONE - Master control done interrupt enable - */ -#define I3C_MINTSET_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK) - -#define I3C_MINTSET_COMPLETE_MASK (0x400U) -#define I3C_MINTSET_COMPLETE_SHIFT (10U) -/*! COMPLETE - Completed message interrupt enable - */ -#define I3C_MINTSET_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK) - -#define I3C_MINTSET_RXPEND_MASK (0x800U) -#define I3C_MINTSET_RXPEND_SHIFT (11U) -/*! RXPEND - RX pending interrupt enable - */ -#define I3C_MINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK) - -#define I3C_MINTSET_TXNOTFULL_MASK (0x1000U) -#define I3C_MINTSET_TXNOTFULL_SHIFT (12U) -/*! TXNOTFULL - TX buffer/FIFO is not full interrupt enable - */ -#define I3C_MINTSET_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK) - -#define I3C_MINTSET_IBIWON_MASK (0x2000U) -#define I3C_MINTSET_IBIWON_SHIFT (13U) -/*! IBIWON - In-Band Interrupt (IBI) won interrupt enable - */ -#define I3C_MINTSET_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK) - -#define I3C_MINTSET_ERRWARN_MASK (0x8000U) -#define I3C_MINTSET_ERRWARN_SHIFT (15U) -/*! ERRWARN - Error or warning (ERRWARN) interrupt enable - */ -#define I3C_MINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK) - -#define I3C_MINTSET_NOWMASTER_MASK (0x80000U) -#define I3C_MINTSET_NOWMASTER_SHIFT (19U) -/*! NOWMASTER - Now master (now this I3C module is a master) interrupt enable - */ -#define I3C_MINTSET_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK) -/*! @} */ - -/*! @name MINTCLR - Master Interrupt Clear */ -/*! @{ */ - -#define I3C_MINTCLR_SLVSTART_MASK (0x100U) -#define I3C_MINTCLR_SLVSTART_SHIFT (8U) -/*! SLVSTART - SLVSTART interrupt enable clear - */ -#define I3C_MINTCLR_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK) - -#define I3C_MINTCLR_MCTRLDONE_MASK (0x200U) -#define I3C_MINTCLR_MCTRLDONE_SHIFT (9U) -/*! MCTRLDONE - MCTRLDONE interrupt enable clear - */ -#define I3C_MINTCLR_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK) - -#define I3C_MINTCLR_COMPLETE_MASK (0x400U) -#define I3C_MINTCLR_COMPLETE_SHIFT (10U) -/*! COMPLETE - COMPLETE interrupt enable clear - */ -#define I3C_MINTCLR_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK) - -#define I3C_MINTCLR_RXPEND_MASK (0x800U) -#define I3C_MINTCLR_RXPEND_SHIFT (11U) -/*! RXPEND - RXPEND interrupt enable clear - */ -#define I3C_MINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK) - -#define I3C_MINTCLR_TXNOTFULL_MASK (0x1000U) -#define I3C_MINTCLR_TXNOTFULL_SHIFT (12U) -/*! TXNOTFULL - TXNOTFULL interrupt enable clear - */ -#define I3C_MINTCLR_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK) - -#define I3C_MINTCLR_IBIWON_MASK (0x2000U) -#define I3C_MINTCLR_IBIWON_SHIFT (13U) -/*! IBIWON - IBIWON interrupt enable clear - */ -#define I3C_MINTCLR_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK) - -#define I3C_MINTCLR_ERRWARN_MASK (0x8000U) -#define I3C_MINTCLR_ERRWARN_SHIFT (15U) -/*! ERRWARN - ERRWARN interrupt enable clear - */ -#define I3C_MINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK) - -#define I3C_MINTCLR_NOWMASTER_MASK (0x80000U) -#define I3C_MINTCLR_NOWMASTER_SHIFT (19U) -/*! NOWMASTER - NOWMASTER interrupt enable clear - */ -#define I3C_MINTCLR_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK) -/*! @} */ - -/*! @name MINTMASKED - Master Interrupt Mask */ -/*! @{ */ - -#define I3C_MINTMASKED_SLVSTART_MASK (0x100U) -#define I3C_MINTMASKED_SLVSTART_SHIFT (8U) -/*! SLVSTART - SLVSTART interrupt mask - */ -#define I3C_MINTMASKED_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK) - -#define I3C_MINTMASKED_MCTRLDONE_MASK (0x200U) -#define I3C_MINTMASKED_MCTRLDONE_SHIFT (9U) -/*! MCTRLDONE - MCTRLDONE interrupt mask - */ -#define I3C_MINTMASKED_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK) - -#define I3C_MINTMASKED_COMPLETE_MASK (0x400U) -#define I3C_MINTMASKED_COMPLETE_SHIFT (10U) -/*! COMPLETE - COMPLETE interrupt mask - */ -#define I3C_MINTMASKED_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK) - -#define I3C_MINTMASKED_RXPEND_MASK (0x800U) -#define I3C_MINTMASKED_RXPEND_SHIFT (11U) -/*! RXPEND - RXPEND interrupt mask - */ -#define I3C_MINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK) - -#define I3C_MINTMASKED_TXNOTFULL_MASK (0x1000U) -#define I3C_MINTMASKED_TXNOTFULL_SHIFT (12U) -/*! TXNOTFULL - TXNOTFULL interrupt mask - */ -#define I3C_MINTMASKED_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK) - -#define I3C_MINTMASKED_IBIWON_MASK (0x2000U) -#define I3C_MINTMASKED_IBIWON_SHIFT (13U) -/*! IBIWON - IBIWON interrupt mask - */ -#define I3C_MINTMASKED_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK) - -#define I3C_MINTMASKED_ERRWARN_MASK (0x8000U) -#define I3C_MINTMASKED_ERRWARN_SHIFT (15U) -/*! ERRWARN - ERRWARN interrupt mask - */ -#define I3C_MINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK) - -#define I3C_MINTMASKED_NOWMASTER_MASK (0x80000U) -#define I3C_MINTMASKED_NOWMASTER_SHIFT (19U) -/*! NOWMASTER - NOWMASTER interrupt mask - */ -#define I3C_MINTMASKED_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK) -/*! @} */ - -/*! @name MERRWARN - Master Errors and Warnings */ -/*! @{ */ - -#define I3C_MERRWARN_NACK_MASK (0x4U) -#define I3C_MERRWARN_NACK_SHIFT (2U) -/*! NACK - Not acknowledge (NACK) error - */ -#define I3C_MERRWARN_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK) - -#define I3C_MERRWARN_WRABT_MASK (0x8U) -#define I3C_MERRWARN_WRABT_SHIFT (3U) -/*! WRABT - WRABT (Write abort) error - */ -#define I3C_MERRWARN_WRABT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK) - -#define I3C_MERRWARN_HPAR_MASK (0x200U) -#define I3C_MERRWARN_HPAR_SHIFT (9U) -/*! HPAR - High data rate parity - */ -#define I3C_MERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK) - -#define I3C_MERRWARN_HCRC_MASK (0x400U) -#define I3C_MERRWARN_HCRC_SHIFT (10U) -/*! HCRC - High data rate CRC error - */ -#define I3C_MERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK) - -#define I3C_MERRWARN_OREAD_MASK (0x10000U) -#define I3C_MERRWARN_OREAD_SHIFT (16U) -/*! OREAD - Over-read error - */ -#define I3C_MERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK) - -#define I3C_MERRWARN_OWRITE_MASK (0x20000U) -#define I3C_MERRWARN_OWRITE_SHIFT (17U) -/*! OWRITE - Over-write error - */ -#define I3C_MERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK) - -#define I3C_MERRWARN_MSGERR_MASK (0x40000U) -#define I3C_MERRWARN_MSGERR_SHIFT (18U) -/*! MSGERR - Message error - */ -#define I3C_MERRWARN_MSGERR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK) - -#define I3C_MERRWARN_INVREQ_MASK (0x80000U) -#define I3C_MERRWARN_INVREQ_SHIFT (19U) -/*! INVREQ - Invalid request error - */ -#define I3C_MERRWARN_INVREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK) - -#define I3C_MERRWARN_TIMEOUT_MASK (0x100000U) -#define I3C_MERRWARN_TIMEOUT_SHIFT (20U) -/*! TIMEOUT - TIMEOUT error - */ -#define I3C_MERRWARN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK) -/*! @} */ - -/*! @name MDMACTRL - Master DMA Control */ -/*! @{ */ - -#define I3C_MDMACTRL_DMAFB_MASK (0x3U) -#define I3C_MDMACTRL_DMAFB_SHIFT (0U) -/*! DMAFB - DMA from bus - * 0b00..NOT_USED - * 0b01..ENABLE_ONE_FRAME - * 0b10..ENABLE - * 0b11.. - */ -#define I3C_MDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK) - -#define I3C_MDMACTRL_DMATB_MASK (0xCU) -#define I3C_MDMACTRL_DMATB_SHIFT (2U) -/*! DMATB - DMA to bus - * 0b00..NOT_USED - * 0b01..ENABLE_ONE_FRAME - * 0b10..ENABLE - * 0b11.. - */ -#define I3C_MDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK) - -#define I3C_MDMACTRL_DMAWIDTH_MASK (0x30U) -#define I3C_MDMACTRL_DMAWIDTH_SHIFT (4U) -/*! DMAWIDTH - DMA width - * 0b00, 0b01..BYTE - * 0b10..HALF_WORD - * 0b11.. - */ -#define I3C_MDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK) -/*! @} */ - -/*! @name MDATACTRL - Master Data Control */ -/*! @{ */ - -#define I3C_MDATACTRL_FLUSHTB_MASK (0x1U) -#define I3C_MDATACTRL_FLUSHTB_SHIFT (0U) -/*! FLUSHTB - Flush to-bus buffer/FIFO - */ -#define I3C_MDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK) - -#define I3C_MDATACTRL_FLUSHFB_MASK (0x2U) -#define I3C_MDATACTRL_FLUSHFB_SHIFT (1U) -/*! FLUSHFB - Flush from-bus buffer/FIFO - */ -#define I3C_MDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK) - -#define I3C_MDATACTRL_UNLOCK_MASK (0x8U) -#define I3C_MDATACTRL_UNLOCK_SHIFT (3U) -/*! UNLOCK - Unlock - */ -#define I3C_MDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK) - -#define I3C_MDATACTRL_TXTRIG_MASK (0x30U) -#define I3C_MDATACTRL_TXTRIG_SHIFT (4U) -/*! TXTRIG - TX trigger level - * 0b00..Trigger on empty - * 0b01..Trigger on 1/4 full or less - * 0b10..Trigger on 1/2 full or less - * 0b11..Default. Trigger on 1 less than full or less - */ -#define I3C_MDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK) - -#define I3C_MDATACTRL_RXTRIG_MASK (0xC0U) -#define I3C_MDATACTRL_RXTRIG_SHIFT (6U) -/*! RXTRIG - RX trigger level - * 0b00..Trigger on not empty - * 0b01..Trigger on 1/4 full or more - * 0b10..Trigger on 1/2 full or more - * 0b11..Trigger on 3/4 full or more - */ -#define I3C_MDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK) - -#define I3C_MDATACTRL_TXCOUNT_MASK (0x1F0000U) -#define I3C_MDATACTRL_TXCOUNT_SHIFT (16U) -/*! TXCOUNT - TX byte count - */ -#define I3C_MDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK) - -#define I3C_MDATACTRL_RXCOUNT_MASK (0x1F000000U) -#define I3C_MDATACTRL_RXCOUNT_SHIFT (24U) -/*! RXCOUNT - RX byte count - */ -#define I3C_MDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK) - -#define I3C_MDATACTRL_TXFULL_MASK (0x40000000U) -#define I3C_MDATACTRL_TXFULL_SHIFT (30U) -/*! TXFULL - TX is full. - * 0b0..TX is not yet full. - * 0b1..TX is full. - */ -#define I3C_MDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK) - -#define I3C_MDATACTRL_RXEMPTY_MASK (0x80000000U) -#define I3C_MDATACTRL_RXEMPTY_SHIFT (31U) -/*! RXEMPTY - RX is empty. - * 0b0..RX is not yet empty. - * 0b1..RX is empty. - */ -#define I3C_MDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK) -/*! @} */ - -/*! @name MWDATAB - Master Write Data Byte */ -/*! @{ */ - -#define I3C_MWDATAB_VALUE_MASK (0xFFU) -#define I3C_MWDATAB_VALUE_SHIFT (0U) -/*! VALUE - Data byte - */ -#define I3C_MWDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK) - -#define I3C_MWDATAB_END_MASK (0x100U) -#define I3C_MWDATAB_END_SHIFT (8U) -/*! END - End of message - */ -#define I3C_MWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK) - -#define I3C_MWDATAB_END_ALSO_MASK (0x10000U) -#define I3C_MWDATAB_END_ALSO_SHIFT (16U) -/*! END_ALSO - End of message also - */ -#define I3C_MWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK) -/*! @} */ - -/*! @name MWDATABE - Master Write Data Byte End */ -/*! @{ */ - -#define I3C_MWDATABE_VALUE_MASK (0xFFU) -#define I3C_MWDATABE_VALUE_SHIFT (0U) -/*! VALUE - Data - */ -#define I3C_MWDATABE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK) -/*! @} */ - -/*! @name MWDATAH - Master Write Data Half-word */ -/*! @{ */ - -#define I3C_MWDATAH_DATA0_MASK (0xFFU) -#define I3C_MWDATAH_DATA0_SHIFT (0U) -/*! DATA0 - Data byte 0 - */ -#define I3C_MWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK) - -#define I3C_MWDATAH_DATA1_MASK (0xFF00U) -#define I3C_MWDATAH_DATA1_SHIFT (8U) -/*! DATA1 - Data byte 1 - */ -#define I3C_MWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK) - -#define I3C_MWDATAH_END_MASK (0x10000U) -#define I3C_MWDATAH_END_SHIFT (16U) -/*! END - End of message - */ -#define I3C_MWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK) -/*! @} */ - -/*! @name MWDATAHE - Master Write Data Byte End */ -/*! @{ */ - -#define I3C_MWDATAHE_DATA0_MASK (0xFFU) -#define I3C_MWDATAHE_DATA0_SHIFT (0U) -/*! DATA0 - DATA 0 - */ -#define I3C_MWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK) - -#define I3C_MWDATAHE_DATA1_MASK (0xFF00U) -#define I3C_MWDATAHE_DATA1_SHIFT (8U) -/*! DATA1 - DATA 1 - */ -#define I3C_MWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK) -/*! @} */ - -/*! @name MRDATAB - Master Read Data Byte */ -/*! @{ */ - -#define I3C_MRDATAB_VALUE_MASK (0xFFU) -#define I3C_MRDATAB_VALUE_SHIFT (0U) -/*! VALUE - VALUE - */ -#define I3C_MRDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK) -/*! @} */ - -/*! @name MRDATAH - Master Read Data Half-word */ -/*! @{ */ - -#define I3C_MRDATAH_LSB_MASK (0xFFU) -#define I3C_MRDATAH_LSB_SHIFT (0U) -/*! LSB - LSB - */ -#define I3C_MRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK) - -#define I3C_MRDATAH_MSB_MASK (0xFF00U) -#define I3C_MRDATAH_MSB_SHIFT (8U) -/*! MSB - MSB - */ -#define I3C_MRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK) -/*! @} */ - -/*! @name MWDATAB1 - Byte-only Write Byte Data (to bus) */ -/*! @{ */ - -#define I3C_MWDATAB1_VALUE_MASK (0xFFU) -#define I3C_MWDATAB1_VALUE_SHIFT (0U) -/*! VALUE - Value - */ -#define I3C_MWDATAB1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB1_VALUE_SHIFT)) & I3C_MWDATAB1_VALUE_MASK) -/*! @} */ - -/*! @name MWMSG_SDR_CONTROL - Master Write Message in SDR mode */ -/*! @{ */ - -#define I3C_MWMSG_SDR_CONTROL_DIR_MASK (0x1U) -#define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT (0U) -/*! DIR - Direction - * 0b0..Write - * 0b1..Read - */ -#define I3C_MWMSG_SDR_CONTROL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK) - -#define I3C_MWMSG_SDR_CONTROL_ADDR_MASK (0xFEU) -#define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT (1U) -/*! ADDR - Address to be written to - */ -#define I3C_MWMSG_SDR_CONTROL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK) - -#define I3C_MWMSG_SDR_CONTROL_END_MASK (0x100U) -#define I3C_MWMSG_SDR_CONTROL_END_SHIFT (8U) -/*! END - End of SDR message - */ -#define I3C_MWMSG_SDR_CONTROL_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK) - -#define I3C_MWMSG_SDR_CONTROL_I2C_MASK (0x400U) -#define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT (10U) -/*! I2C - I2C - * 0b0..I3C message - * 0b1..I2C message - */ -#define I3C_MWMSG_SDR_CONTROL_I2C(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK) - -#define I3C_MWMSG_SDR_CONTROL_LEN_MASK (0xF800U) -#define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT (11U) -/*! LEN - Length - */ -#define I3C_MWMSG_SDR_CONTROL_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK) -/*! @} */ - -/*! @name MWMSG_SDR_DATA - Master Write Message Data in SDR mode */ -/*! @{ */ - -#define I3C_MWMSG_SDR_DATA_DATA16B_MASK (0xFFFFU) -#define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT (0U) -/*! DATA16B - Data - */ -#define I3C_MWMSG_SDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK) -/*! @} */ - -/*! @name MRMSG_SDR - Master Read Message in SDR mode */ -/*! @{ */ - -#define I3C_MRMSG_SDR_DATA_MASK (0xFFFFU) -#define I3C_MRMSG_SDR_DATA_SHIFT (0U) -/*! DATA - Data - */ -#define I3C_MRMSG_SDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK) -/*! @} */ - -/*! @name MWMSG_DDR_CONTROL - Master Write Message in DDR mode */ -/*! @{ */ - -#define I3C_MWMSG_DDR_CONTROL_LEN_MASK (0x3FFU) -#define I3C_MWMSG_DDR_CONTROL_LEN_SHIFT (0U) -/*! LEN - Length of message - */ -#define I3C_MWMSG_DDR_CONTROL_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_DDR_CONTROL_LEN_MASK) - -#define I3C_MWMSG_DDR_CONTROL_END_MASK (0x4000U) -#define I3C_MWMSG_DDR_CONTROL_END_SHIFT (14U) -/*! END - End of message - */ -#define I3C_MWMSG_DDR_CONTROL_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL_END_MASK) -/*! @} */ - -/*! @name MWMSG_DDR_DATA - Master Write Message Data in DDR mode */ -/*! @{ */ - -#define I3C_MWMSG_DDR_DATA_DATA16B_MASK (0xFFFFU) -#define I3C_MWMSG_DDR_DATA_DATA16B_SHIFT (0U) -/*! DATA16B - Data - */ -#define I3C_MWMSG_DDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_DDR_DATA_DATA16B_MASK) -/*! @} */ - -/*! @name MRMSG_DDR - Master Read Message in DDR mode */ -/*! @{ */ - -#define I3C_MRMSG_DDR_DATA_MASK (0xFFFFU) -#define I3C_MRMSG_DDR_DATA_SHIFT (0U) -/*! DATA - Data - */ -#define I3C_MRMSG_DDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_DATA_SHIFT)) & I3C_MRMSG_DDR_DATA_MASK) -/*! @} */ - -/*! @name MDYNADDR - Master Dynamic Address */ -/*! @{ */ - -#define I3C_MDYNADDR_DAVALID_MASK (0x1U) -#define I3C_MDYNADDR_DAVALID_SHIFT (0U) -/*! DAVALID - Dynamic address valid - */ -#define I3C_MDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK) - -#define I3C_MDYNADDR_DADDR_MASK (0xFEU) -#define I3C_MDYNADDR_DADDR_SHIFT (1U) -/*! DADDR - Dynamic address - */ -#define I3C_MDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK) -/*! @} */ - -/*! @name SMAPCTRL0 - Map Feature Control 0 */ -/*! @{ */ - -#define I3C_SMAPCTRL0_ENA_MASK (0x1U) -#define I3C_SMAPCTRL0_ENA_SHIFT (0U) -/*! ENA - Enable - */ -#define I3C_SMAPCTRL0_ENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_ENA_SHIFT)) & I3C_SMAPCTRL0_ENA_MASK) - -#define I3C_SMAPCTRL0_DA_MASK (0xFEU) -#define I3C_SMAPCTRL0_DA_SHIFT (1U) -/*! DA - Dynamic Address - */ -#define I3C_SMAPCTRL0_DA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_DA_SHIFT)) & I3C_SMAPCTRL0_DA_MASK) - -#define I3C_SMAPCTRL0_CAUSE_MASK (0x700U) -#define I3C_SMAPCTRL0_CAUSE_SHIFT (8U) -/*! CAUSE - Cause - */ -#define I3C_SMAPCTRL0_CAUSE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_CAUSE_SHIFT)) & I3C_SMAPCTRL0_CAUSE_MASK) -/*! @} */ - -/*! @name IBIEXT1 - Extended IBI Data 1 */ -/*! @{ */ - -#define I3C_IBIEXT1_CNT_MASK (0x7U) -#define I3C_IBIEXT1_CNT_SHIFT (0U) -/*! CNT - Count - */ -#define I3C_IBIEXT1_CNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_CNT_SHIFT)) & I3C_IBIEXT1_CNT_MASK) - -#define I3C_IBIEXT1_MAX_MASK (0x70U) -#define I3C_IBIEXT1_MAX_SHIFT (4U) -/*! MAX - Maximum - */ -#define I3C_IBIEXT1_MAX(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_MAX_SHIFT)) & I3C_IBIEXT1_MAX_MASK) - -#define I3C_IBIEXT1_EXT1_MASK (0xFF00U) -#define I3C_IBIEXT1_EXT1_SHIFT (8U) -/*! EXT1 - Extra byte 1 - */ -#define I3C_IBIEXT1_EXT1(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT1_SHIFT)) & I3C_IBIEXT1_EXT1_MASK) - -#define I3C_IBIEXT1_EXT2_MASK (0xFF0000U) -#define I3C_IBIEXT1_EXT2_SHIFT (16U) -/*! EXT2 - Extra byte 2 - */ -#define I3C_IBIEXT1_EXT2(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT2_SHIFT)) & I3C_IBIEXT1_EXT2_MASK) - -#define I3C_IBIEXT1_EXT3_MASK (0xFF000000U) -#define I3C_IBIEXT1_EXT3_SHIFT (24U) -/*! EXT3 - Extra byte 3 - */ -#define I3C_IBIEXT1_EXT3(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT3_SHIFT)) & I3C_IBIEXT1_EXT3_MASK) -/*! @} */ - -/*! @name IBIEXT2 - Extended IBI Data 2 */ -/*! @{ */ - -#define I3C_IBIEXT2_EXT4_MASK (0xFFU) -#define I3C_IBIEXT2_EXT4_SHIFT (0U) -/*! EXT4 - Extra byte 4 - */ -#define I3C_IBIEXT2_EXT4(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT4_SHIFT)) & I3C_IBIEXT2_EXT4_MASK) - -#define I3C_IBIEXT2_EXT5_MASK (0xFF00U) -#define I3C_IBIEXT2_EXT5_SHIFT (8U) -/*! EXT5 - Extra byte 5 - */ -#define I3C_IBIEXT2_EXT5(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT5_SHIFT)) & I3C_IBIEXT2_EXT5_MASK) - -#define I3C_IBIEXT2_EXT6_MASK (0xFF0000U) -#define I3C_IBIEXT2_EXT6_SHIFT (16U) -/*! EXT6 - Extra byte 6 - */ -#define I3C_IBIEXT2_EXT6(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT6_SHIFT)) & I3C_IBIEXT2_EXT6_MASK) - -#define I3C_IBIEXT2_EXT7_MASK (0xFF000000U) -#define I3C_IBIEXT2_EXT7_SHIFT (24U) -/*! EXT7 - Extra byte 7 - */ -#define I3C_IBIEXT2_EXT7(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT7_SHIFT)) & I3C_IBIEXT2_EXT7_MASK) -/*! @} */ - -/*! @name SID - Slave Module ID */ -/*! @{ */ - -#define I3C_SID_ID_MASK (0xFFFFFFFFU) -#define I3C_SID_ID_SHIFT (0U) -/*! ID - ID - */ -#define I3C_SID_ID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SID_ID_SHIFT)) & I3C_SID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I3C_Register_Masks */ - - -/* I3C - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral I3C0 base address */ - #define I3C0_BASE (0x50016000u) - /** Peripheral I3C0 base address */ - #define I3C0_BASE_NS (0x40016000u) - /** Peripheral I3C0 base pointer */ - #define I3C0 ((I3C_Type *)I3C0_BASE) - /** Peripheral I3C0 base pointer */ - #define I3C0_NS ((I3C_Type *)I3C0_BASE_NS) - /** Array initializer of I3C peripheral base addresses */ - #define I3C_BASE_ADDRS { I3C0_BASE } - /** Array initializer of I3C peripheral base pointers */ - #define I3C_BASE_PTRS { I3C0 } - /** Array initializer of I3C peripheral base addresses */ - #define I3C_BASE_ADDRS_NS { I3C0_BASE_NS } - /** Array initializer of I3C peripheral base pointers */ - #define I3C_BASE_PTRS_NS { I3C0_NS } -#else - /** Peripheral I3C0 base address */ - #define I3C0_BASE (0x40016000u) - /** Peripheral I3C0 base pointer */ - #define I3C0 ((I3C_Type *)I3C0_BASE) - /** Array initializer of I3C peripheral base addresses */ - #define I3C_BASE_ADDRS { I3C0_BASE } - /** Array initializer of I3C peripheral base pointers */ - #define I3C_BASE_PTRS { I3C0 } -#endif -/** Interrupt vectors for the I3C peripheral type */ -#define I3C_IRQS { I3C0_IRQn } - -/*! - * @} - */ /* end of group I3C_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer - * @{ - */ - -/** INPUTMUX - Register Layout Typedef */ -typedef struct { - __IO uint32_t SCT0_INMUX[7]; /**< Inputmux register for SCT0 input, array offset: 0x0, array step: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t TIMER0CAP[4]; /**< Capture select register for TIMER0 inputs, array offset: 0x20, array step: 0x4 */ - __IO uint32_t TIMER0TRIG; /**< Trigger register for TIMER0, offset: 0x30 */ - uint8_t RESERVED_1[12]; - __IO uint32_t TIMER1CAP[4]; /**< Capture select register for TIMER1 inputs, array offset: 0x40, array step: 0x4 */ - __IO uint32_t TIMER1TRIG; /**< Trigger register for TIMER1, offset: 0x50 */ - uint8_t RESERVED_2[12]; - __IO uint32_t TIMER2CAP[4]; /**< Capture select register for TIMER2 inputs, array offset: 0x60, array step: 0x4 */ - __IO uint32_t TIMER2TRIG; /**< Trigger register for TIMER2, offset: 0x70 */ - uint8_t RESERVED_3[44]; - __IO uint32_t EZHARCHB_INMUX[8]; /**< Inputmux register for EZH arch B inputs, array offset: 0xA0, array step: 0x4 */ - __IO uint32_t PINTSEL[8]; /**< Pin interrupt select, array offset: 0xC0, array step: 0x4 */ - __IO uint32_t DMA0_ITRIG_INMUX[32]; /**< Trigger select for DMA0 channel, array offset: 0xE0, array step: 0x4 */ - __IO uint32_t DMA0_OTRIG_INMUX[7]; /**< DMA0 output trigger selection for DMA0 input trigger, array offset: 0x160, array step: 0x4 */ - uint8_t RESERVED_4[4]; - __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ - __IO uint32_t FREQMEAS_TAR; /**< Selection for frequency measurement target clock, offset: 0x184 */ - uint8_t RESERVED_5[24]; - __IO uint32_t TIMER3CAP[4]; /**< Capture select register for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */ - __IO uint32_t TIMER3TRIG; /**< Trigger register for TIMER3, offset: 0x1B0 */ - uint8_t RESERVED_6[12]; - __IO uint32_t TIMER4CAP[4]; /**< Capture select register for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */ - __IO uint32_t TIMER4TRIG; /**< Trigger register for TIMER4, offset: 0x1D0 */ - uint8_t RESERVED_7[12]; - __IO uint32_t PINTSECSEL[2]; /**< Pin interrupt secure select, array offset: 0x1E0, array step: 0x4 */ - uint8_t RESERVED_8[24]; - __IO uint32_t DMA1_ITRIG_INMUX[16]; /**< Trigger select for DMA1 channel, array offset: 0x200, array step: 0x4 */ - __IO uint32_t DMA1_OTRIG_INMUX[4]; /**< DMA1 output trigger selection for DMA1 input trigger, array offset: 0x240, array step: 0x4 */ - uint8_t RESERVED_9[16]; - __IO uint32_t HSCMP0_TRIG; /**< Input connections for HSCMP0, offset: 0x260 */ - uint8_t RESERVED_10[28]; - __IO uint32_t ADC0_TRIG[4]; /**< ADC0 Trigger input connections, array offset: 0x280, array step: 0x4 */ - uint8_t RESERVED_11[48]; - __IO uint32_t ADC1_TRIG[4]; /**< ADC1 Trigger input connections, array offset: 0x2C0, array step: 0x4 */ - uint8_t RESERVED_12[48]; - __IO uint32_t DAC0_TRIG; /**< DAC0 Trigger Inputs, offset: 0x300 */ - uint8_t RESERVED_13[28]; - __IO uint32_t DAC1_TRIG; /**< DAC1 Trigger Inputs, offset: 0x320 */ - uint8_t RESERVED_14[28]; - __IO uint32_t DAC2_TRIG; /**< DAC2 Trigger Inputs, offset: 0x340 */ - uint8_t RESERVED_15[28]; - __IO uint32_t ENC0_TRIG; /**< ENC0 Trigger Input Connections, offset: 0x360 */ - __IO uint32_t ENC0_HOME; /**< ENC0 Input Connections, offset: 0x364 */ - __IO uint32_t ENC0_INDEX; /**< ENC0 Input Connections, offset: 0x368 */ - __IO uint32_t ENC0_PHASEB; /**< ENC0 Input Connections, offset: 0x36C */ - __IO uint32_t ENC0_PHASEA; /**< ENC0 Input Connections, offset: 0x370 */ - uint8_t RESERVED_16[12]; - __IO uint32_t ENC1_TRIG; /**< ENC1 Trigger Input Connections, offset: 0x380 */ - __IO uint32_t ENC1_HOME; /**< ENC1 Input Connections, offset: 0x384 */ - __IO uint32_t ENC1_INDEX; /**< ENC1 Input Connections, offset: 0x388 */ - __IO uint32_t ENC1_PHASEB; /**< ENC1 Input Connections, offset: 0x38C */ - __IO uint32_t ENC1_PHASEA; /**< ENC1 Input Connections, offset: 0x390 */ - uint8_t RESERVED_17[12]; - __IO uint32_t PWM0_EXTSYNC[4]; /**< PWM0 external synchronization, array offset: 0x3A0, array step: 0x4 */ - __IO uint32_t PWM0_EXTA[4]; /**< PWM0 input trigger connections, array offset: 0x3B0, array step: 0x4 */ - __IO uint32_t PWM0_EXTFORCE; /**< PWM0 external force trigger connections, offset: 0x3C0 */ - __IO uint32_t PWM0_FAULT[4]; /**< PWM0 fault input trigger connections, array offset: 0x3C4, array step: 0x4 */ - uint8_t RESERVED_18[12]; - __IO uint32_t PWM1_EXTSYNC[4]; /**< PWM1 external synchronization, array offset: 0x3E0, array step: 0x4 */ - __IO uint32_t PWM1_EXTA[4]; /**< PWM1 input trigger connections, array offset: 0x3F0, array step: 0x4 */ - __IO uint32_t PWM1_EXTFORCE; /**< PWM1 external force trigger connections, offset: 0x400 */ - __IO uint32_t PWM1_FAULT[4]; /**< PWM1 fault input trigger connections, array offset: 0x404, array step: 0x4 */ - uint8_t RESERVED_19[12]; - __IO uint32_t PWM0_EXTCLK; /**< PWM0 external clock trigger connections, offset: 0x420 */ - __IO uint32_t PWM1_EXTCLK; /**< PWM1 external clock trigger connections, offset: 0x424 */ - uint8_t RESERVED_20[24]; - __IO uint32_t AOI0_IN[16]; /**< AOI0 trigger inputs, array offset: 0x440, array step: 0x4 */ - __IO uint32_t AOI1_IN[16]; /**< AOI1 trigger inputs, array offset: 0x480, array step: 0x4 */ - __IO uint32_t AOI_EXT_TRIG[8]; /**< AOI External Trigger Inputs, array offset: 0x4C0, array step: 0x4 */ - __IO uint32_t HSCMP1_TRIG; /**< Input connections for HSCMP1, offset: 0x4E0 */ - uint8_t RESERVED_21[28]; - __IO uint32_t HSCMP2_TRIG; /**< Input connections for HSCMP2, offset: 0x500 */ - uint8_t RESERVED_22[28]; - __IO uint32_t DMA0_ITRIG_INMUX32[20]; /**< Trigger select for DMA0 channel, array offset: 0x520, array step: 0x4 */ - uint8_t RESERVED_23[464]; - __IO uint32_t DMA0_REQEN0; /**< Enable DMA0 requests, offset: 0x740 */ - __IO uint32_t DMA0_REQEN1; /**< Enable DMA0 requests, offset: 0x744 */ - __O uint32_t DMA0_REQEN0_SET; /**< Set bits in DMA0_REQEN0 register, offset: 0x748 */ - __O uint32_t DMA0_REQEN1_SET; /**< Set bits in DMA0_REQEN1 register, offset: 0x74C */ - __O uint32_t DMA0_REQEN0_CLR; /**< Clear bits in DMA0_REQEN0 register, offset: 0x750 */ - __O uint32_t DMA0_REQEN1_CLR; /**< Clear bits in DMA0_REQEN1 register, offset: 0x754 */ - uint8_t RESERVED_24[8]; - __IO uint32_t DMA1_REQEN; /**< Enable DMA1 requests, offset: 0x760 */ - uint8_t RESERVED_25[4]; - __O uint32_t DMA1_REQEN_SET; /**< Set bits in DMA1_REQEN register, offset: 0x768 */ - uint8_t RESERVED_26[4]; - __O uint32_t DMA1_REQEN_CLR; /**< Clear bits in DMA1_REQEN register, offset: 0x770 */ - uint8_t RESERVED_27[12]; - __IO uint32_t DMA0_ITRIGEN0; /**< Enable DMA0 triggers, offset: 0x780 */ - __IO uint32_t DMA0_ITRIGEN1; /**< Enable DMA0 triggers, offset: 0x784 */ - __O uint32_t DMA0_ITRIGEN0_SET; /**< Set bits in DMA0_ITRIGEN0 register, offset: 0x788 */ - __O uint32_t DMA0_ITRIGEN1_SET; /**< Set bits in DMA0_ITRIGEN1 register, offset: 0x78C */ - __O uint32_t DMA0_ITRIGEN0_CLR; /**< Clear bits in DMA0_ITRIGEN0 register, offset: 0x790 */ - __O uint32_t DMA0_ITRIGEN1_CLR; /**< Clear bits in DMA0_ITRIGEN1 register, offset: 0x794 */ - uint8_t RESERVED_28[8]; - __IO uint32_t DMA1_ITRIGEN; /**< Enable DMA1 triggers, offset: 0x7A0 */ - uint8_t RESERVED_29[4]; - __O uint32_t DMA1_ITRIGEN_SET; /**< Set bits in DMA1_ITRIGEN register, offset: 0x7A8 */ - uint8_t RESERVED_30[4]; - __O uint32_t DMA1_ITRIGEN_CLR; /**< Clear bits in DMA1_ITRIGEN register, offset: 0x7B0 */ -} INPUTMUX_Type; - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks - * @{ - */ - -/*! @name SCT0_INMUX - Inputmux register for SCT0 input */ -/*! @{ */ - -#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x3FU) -#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) -/*! INP_N - Input number to SCT0 inputs 0 to 6. - * 0b000000..SCT_GPIO_IN_A function selected from IOCON register - * 0b000001..SCT_GPIO_IN_B function selected from IOCON register - * 0b000010..SCT_GPIO_IN_C function selected from IOCON register - * 0b000011..SCT_GPIO_IN_D function selected from IOCON register - * 0b000100..SCT_GPIO_IN_E function selected from IOCON register - * 0b000101..SCT_GPIO_IN_F function selected from IOCON register - * 0b000110..SCT_GPIO_IN_G function selected from IOCON register - * 0b000111..SCT_GPIO_IN_H function selected from IOCON register - * 0b001000..T0_MAT0 ctimer 0 match[0] output - * 0b001001..T1_MAT0 ctimer 1 match[0] output - * 0b001010..T2_MAT0 ctimer 2 match[0] output - * 0b001011..T3_MAT0 ctimer 3 match[0] output - * 0b001100..T4_MAT0 ctimer 4 match[0] output - * 0b001101..ADC0_IRQ interrupt request from ADC0 - * 0b001110..GPIOINT_BMATCH - * 0b001111..USB0_FRAME_TOGGLE - * 0b010000..Reserved - * 0b010001..ACMP0_OUT from analog comparator - * 0b010010..SHARED_I2S_SCLK0 output from I2S pin sharing - * 0b010011..SHARED_I2S_SCLK1 output from I2S pin sharing - * 0b010100..SHARED_I2S_WS0 output from I2S pin sharing - * 0b010101..SHARED_I2S_WS1 output from I2S pin sharing - * 0b010110..ARM_TXEV interrupt event from CPU0 - * 0b010111..DEBUG_HALTED from CPU0 - * 0b011000..ADC1_IRQ interrupt request from ADC1 - * 0b011001..ADC0_tcomp[0] - * 0b011010..ADC0_tcomp[1] - * 0b011011..ADC0_tcomp[2] - * 0b011100..ADC0_tcomp[3] - * 0b011101..ADC1_tcomp[0] - * 0b011110..ADC1_tcomp[1] - * 0b011111..ADC1_tcomp[2] - * 0b100000..ADC1_tcomp[3] - * 0b100001..HSCMP0_OUT - * 0b100010..HSCMP1_OUT - * 0b100011..HSCMP2_OUT - * 0b100100..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 - * 0b100101..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 - * 0b100110..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 - * 0b100111..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 - * 0b101000..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 - * 0b101001..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 - * 0b101010..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 - * 0b101011..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 - * 0b101100..ENC0_CMP/POS_MATCH - * 0b101101..ENC1_CMP/POS_MATCH - * 0b101110..AOI0_OUT0 - * 0b101111..AOI0_OUT1 - * 0b110000..AOI0_OUT2 - * 0b110001..AOI0_OUT3 - * 0b110010..AOI1_OUT0 - * 0b110011..AOI1_OUT1 - * 0b110100..AOI1_OUT2 - * 0b110101..AOI1_OUT3 - * 0b110110..FC3_SCK - * 0b110111..FC3_RXD_SDA_MOSI_DATA - * 0b111000..FC3_TXD_SCL_MISO_WS - * 0b111001..FC3_CTS_DSA_SSEL0 - * 0b111010..TMPR_OUT - * 0b111011-0b111111..None - */ -#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK) -/*! @} */ - -/* The count of INPUTMUX_SCT0_INMUX */ -#define INPUTMUX_SCT0_INMUX_COUNT (7U) - -/*! @name TIMER0CAP - Capture select register for TIMER0 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER0CAP_CAPTSEL_MASK (0x3FU) -#define INPUTMUX_TIMER0CAP_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 5 - * 0b000000..CTIMER_INP0 function selected from IOCON register - * 0b000001..CTIMER_INP1 function selected from IOCON register - * 0b000010..CTIMER_INP2 function selected from IOCON register - * 0b000011..CTIMER_INP3 function selected from IOCON register - * 0b000100..CTIMER_INP4 function selected from IOCON register - * 0b000101..CTIMER_INP5 function selected from IOCON register - * 0b000110..CTIMER_INP6 function selected from IOCON register - * 0b000111..CTIMER_INP7 function selected from IOCON register - * 0b001000..CTIMER_INP8 function selected from IOCON register - * 0b001001..CTIMER_INP9 function selected from IOCON register - * 0b001010..CTIMER_INP10 function selected from IOCON register - * 0b001011..CTIMER_INP11 function selected from IOCON register - * 0b001100..CTIMER_INP12 function selected from IOCON register - * 0b001101..CTIMER_INP13 function selected from IOCON register - * 0b001110..CTIMER_INP14 function selected from IOCON register - * 0b001111..CTIMER_INP15 function selected from IOCON register - * 0b010000..CTIMER_INP16 function selected from IOCON register - * 0b010001..CTIMER_INP17 function selected from IOCON register - * 0b010010..CTIMER_INP18 function selected from IOCON register - * 0b010011..CTIMER_INP19 function selected from IOCON register - * 0b010100..USB0_FRAME_TOGGLE - * 0b010101..Reserved - * 0b010110..ACMP0_OUT from analog comparator - * 0b010111..SHARED_I2S_WS0 output from I2S pin sharing - * 0b011000..SHARED_I2S_WS1 output from I2S pin sharing - * 0b011001..ADC0_IRQ - * 0b011010..ADC1_IRQ - * 0b011011..HSCMP0_OUT - * 0b011100..HSCMP1_OUT - * 0b011101..HSCMP2_OUT - * 0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 - * 0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 - * 0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 - * 0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 - * 0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 - * 0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 - * 0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 - * 0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 - * 0b100110..ENC0_CMP/POS_MATCH - * 0b100111..ENC1_CMP/POS_MATCH - * 0b101000..AOI0_OUT0 - * 0b101001..AOI0_OUT1 - * 0b101010..AOI0_OUT2 - * 0b101011..AOI0_OUT3 - * 0b101100..AOI1_OUT0 - * 0b101101..AOI1_OUT1 - * 0b101110..AOI1_OUT2 - * 0b101111..AOI1_OUT3 - * 0b110000..TMPR_OUT - * 0b110001-0b111111..None - */ -#define INPUTMUX_TIMER0CAP_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAP_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAP_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER0CAP */ -#define INPUTMUX_TIMER0CAP_COUNT (4U) - -/*! @name TIMER0TRIG - Trigger register for TIMER0 */ -/*! @{ */ - -#define INPUTMUX_TIMER0TRIG_TRIGIN_MASK (0x3FU) -#define INPUTMUX_TIMER0TRIG_TRIGIN_SHIFT (0U) -/*! TRIGIN - Input number to TIMER0 trigger inputs - * 0b000000..CTIMER_INP0 function selected from IOCON register - * 0b000001..CTIMER_INP1 function selected from IOCON register - * 0b000010..CTIMER_INP2 function selected from IOCON register - * 0b000011..CTIMER_INP3 function selected from IOCON register - * 0b000100..CTIMER_INP4 function selected from IOCON register - * 0b000101..CTIMER_INP5 function selected from IOCON register - * 0b000110..CTIMER_INP6 function selected from IOCON register - * 0b000111..CTIMER_INP7 function selected from IOCON register - * 0b001000..CTIMER_INP8 function selected from IOCON register - * 0b001001..CTIMER_INP9 function selected from IOCON register - * 0b001010..CTIMER_INP10 function selected from IOCON register - * 0b001011..CTIMER_INP11 function selected from IOCON register - * 0b001100..CTIMER_INP12 function selected from IOCON register - * 0b001101..CTIMER_INP13 function selected from IOCON register - * 0b001110..CTIMER_INP14 function selected from IOCON register - * 0b001111..CTIMER_INP15 function selected from IOCON register - * 0b010000..CTIMER_INP16 function selected from IOCON register - * 0b010001..CTIMER_INP17 function selected from IOCON register - * 0b010010..CTIMER_INP18 function selected from IOCON register - * 0b010011..CTIMER_INP19 function selected from IOCON register - * 0b010100..USB0_FRAME_TOGGLE - * 0b010101..Reserved - * 0b010110..ACMP0_OUT from analog comparator - * 0b010111..SHARED_I2S_WS0 output from I2S pin sharing - * 0b011000..SHARED_I2S_WS1 output from I2S pin sharing - * 0b011001..ADC0_IRQ - * 0b011010..ADC1_IRQ - * 0b011011..HSCMP0_OUT - * 0b011100..HSCMP1_OUT - * 0b011101..HSCMP2_OUT - * 0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 - * 0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 - * 0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 - * 0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 - * 0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 - * 0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 - * 0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 - * 0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 - * 0b100110..ENC0_CMP/POS_MATCH - * 0b100111..ENC1_CMP/POS_MATCH - * 0b101000..AOI0_OUT0 - * 0b101001..AOI0_OUT1 - * 0b101010..AOI0_OUT2 - * 0b101011..AOI0_OUT3 - * 0b101100..AOI1_OUT0 - * 0b101101..AOI1_OUT1 - * 0b101110..AOI1_OUT2 - * 0b101111..AOI1_OUT3 - * 0b110000..TMPR_OUT - * 0b110001-0b111111..None - */ -#define INPUTMUX_TIMER0TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0TRIG_TRIGIN_SHIFT)) & INPUTMUX_TIMER0TRIG_TRIGIN_MASK) -/*! @} */ - -/*! @name TIMER1CAP - Capture select register for TIMER1 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER1CAP_CAPTSEL_MASK (0x3FU) -#define INPUTMUX_TIMER1CAP_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 5 - * 0b000000..CTIMER_INP0 function selected from IOCON register - * 0b000001..CTIMER_INP1 function selected from IOCON register - * 0b000010..CTIMER_INP2 function selected from IOCON register - * 0b000011..CTIMER_INP3 function selected from IOCON register - * 0b000100..CTIMER_INP4 function selected from IOCON register - * 0b000101..CTIMER_INP5 function selected from IOCON register - * 0b000110..CTIMER_INP6 function selected from IOCON register - * 0b000111..CTIMER_INP7 function selected from IOCON register - * 0b001000..CTIMER_INP8 function selected from IOCON register - * 0b001001..CTIMER_INP9 function selected from IOCON register - * 0b001010..CTIMER_INP10 function selected from IOCON register - * 0b001011..CTIMER_INP11 function selected from IOCON register - * 0b001100..CTIMER_INP12 function selected from IOCON register - * 0b001101..CTIMER_INP13 function selected from IOCON register - * 0b001110..CTIMER_INP14 function selected from IOCON register - * 0b001111..CTIMER_INP15 function selected from IOCON register - * 0b010000..CTIMER_INP16 function selected from IOCON register - * 0b010001..CTIMER_INP17 function selected from IOCON register - * 0b010010..CTIMER_INP18 function selected from IOCON register - * 0b010011..CTIMER_INP19 function selected from IOCON register - * 0b010100..USB0_FRAME_TOGGLE - * 0b010101..Reserved - * 0b010110..ACMP0_OUT from analog comparator - * 0b010111..SHARED_I2S_WS0 output from I2S pin sharing - * 0b011000..SHARED_I2S_WS1 output from I2S pin sharing - * 0b011001..ADC0_IRQ - * 0b011010..ADC1_IRQ - * 0b011011..HSCMP0_OUT - * 0b011100..HSCMP1_OUT - * 0b011101..HSCMP2_OUT - * 0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 - * 0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 - * 0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 - * 0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 - * 0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 - * 0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 - * 0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 - * 0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 - * 0b100110..ENC0_CMP/POS_MATCH - * 0b100111..ENC1_CMP/POS_MATCH - * 0b101000..AOI0_OUT0 - * 0b101001..AOI0_OUT1 - * 0b101010..AOI0_OUT2 - * 0b101011..AOI0_OUT3 - * 0b101100..AOI1_OUT0 - * 0b101101..AOI1_OUT1 - * 0b101110..AOI1_OUT2 - * 0b101111..AOI1_OUT3 - * 0b110000..TMPR_OUT - * 0b110001-0b111111..None - */ -#define INPUTMUX_TIMER1CAP_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAP_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAP_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER1CAP */ -#define INPUTMUX_TIMER1CAP_COUNT (4U) - -/*! @name TIMER1TRIG - Trigger register for TIMER1 */ -/*! @{ */ - -#define INPUTMUX_TIMER1TRIG_TRIGIN_MASK (0x3FU) -#define INPUTMUX_TIMER1TRIG_TRIGIN_SHIFT (0U) -/*! TRIGIN - Input number to TIMER1 trigger inputs - * 0b000000..CTIMER_INP0 function selected from IOCON register - * 0b000001..CTIMER_INP1 function selected from IOCON register - * 0b000010..CTIMER_INP2 function selected from IOCON register - * 0b000011..CTIMER_INP3 function selected from IOCON register - * 0b000100..CTIMER_INP4 function selected from IOCON register - * 0b000101..CTIMER_INP5 function selected from IOCON register - * 0b000110..CTIMER_INP6 function selected from IOCON register - * 0b000111..CTIMER_INP7 function selected from IOCON register - * 0b001000..CTIMER_INP8 function selected from IOCON register - * 0b001001..CTIMER_INP9 function selected from IOCON register - * 0b001010..CTIMER_INP10 function selected from IOCON register - * 0b001011..CTIMER_INP11 function selected from IOCON register - * 0b001100..CTIMER_INP12 function selected from IOCON register - * 0b001101..CTIMER_INP13 function selected from IOCON register - * 0b001110..CTIMER_INP14 function selected from IOCON register - * 0b001111..CTIMER_INP15 function selected from IOCON register - * 0b010000..CTIMER_INP16 function selected from IOCON register - * 0b010001..CTIMER_INP17 function selected from IOCON register - * 0b010010..CTIMER_INP18 function selected from IOCON register - * 0b010011..CTIMER_INP19 function selected from IOCON register - * 0b010100..USB0_FRAME_TOGGLE - * 0b010101..Reserved - * 0b010110..ACMP0_OUT from analog comparator - * 0b010111..SHARED_I2S_WS0 output from I2S pin sharing - * 0b011000..SHARED_I2S_WS1 output from I2S pin sharing - * 0b011001..ADC0_IRQ - * 0b011010..ADC1_IRQ - * 0b011011..HSCMP0_OUT - * 0b011100..HSCMP1_OUT - * 0b011101..HSCMP2_OUT - * 0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 - * 0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 - * 0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 - * 0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 - * 0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 - * 0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 - * 0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 - * 0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 - * 0b100110..ENC0_CMP/POS_MATCH - * 0b100111..ENC1_CMP/POS_MATCH - * 0b101000..AOI0_OUT0 - * 0b101001..AOI0_OUT1 - * 0b101010..AOI0_OUT2 - * 0b101011..AOI0_OUT3 - * 0b101100..AOI1_OUT0 - * 0b101101..AOI1_OUT1 - * 0b101110..AOI1_OUT2 - * 0b101111..AOI1_OUT3 - * 0b110000..TMPR_OUT - * 0b110001-0b111111..None - */ -#define INPUTMUX_TIMER1TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1TRIG_TRIGIN_SHIFT)) & INPUTMUX_TIMER1TRIG_TRIGIN_MASK) -/*! @} */ - -/*! @name TIMER2CAP - Capture select register for TIMER2 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER2CAP_CAPTSEL_MASK (0x3FU) -#define INPUTMUX_TIMER2CAP_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 5 - * 0b000000..CTIMER_INP0 function selected from IOCON register - * 0b000001..CTIMER_INP1 function selected from IOCON register - * 0b000010..CTIMER_INP2 function selected from IOCON register - * 0b000011..CTIMER_INP3 function selected from IOCON register - * 0b000100..CTIMER_INP4 function selected from IOCON register - * 0b000101..CTIMER_INP5 function selected from IOCON register - * 0b000110..CTIMER_INP6 function selected from IOCON register - * 0b000111..CTIMER_INP7 function selected from IOCON register - * 0b001000..CTIMER_INP8 function selected from IOCON register - * 0b001001..CTIMER_INP9 function selected from IOCON register - * 0b001010..CTIMER_INP10 function selected from IOCON register - * 0b001011..CTIMER_INP11 function selected from IOCON register - * 0b001100..CTIMER_INP12 function selected from IOCON register - * 0b001101..CTIMER_INP13 function selected from IOCON register - * 0b001110..CTIMER_INP14 function selected from IOCON register - * 0b001111..CTIMER_INP15 function selected from IOCON register - * 0b010000..CTIMER_INP16 function selected from IOCON register - * 0b010001..CTIMER_INP17 function selected from IOCON register - * 0b010010..CTIMER_INP18 function selected from IOCON register - * 0b010011..CTIMER_INP19 function selected from IOCON register - * 0b010100..USB0_FRAME_TOGGLE - * 0b010101..Reserved - * 0b010110..ACMP0_OUT from analog comparator - * 0b010111..SHARED_I2S_WS0 output from I2S pin sharing - * 0b011000..SHARED_I2S_WS1 output from I2S pin sharing - * 0b011001..ADC0_IRQ - * 0b011010..ADC1_IRQ - * 0b011011..HSCMP0_OUT - * 0b011100..HSCMP1_OUT - * 0b011101..HSCMP2_OUT - * 0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 - * 0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 - * 0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 - * 0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 - * 0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 - * 0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 - * 0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 - * 0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 - * 0b100110..ENC0_CMP/POS_MATCH - * 0b100111..ENC1_CMP/POS_MATCH - * 0b101000..AOI0_OUT0 - * 0b101001..AOI0_OUT1 - * 0b101010..AOI0_OUT2 - * 0b101011..AOI0_OUT3 - * 0b101100..AOI1_OUT0 - * 0b101101..AOI1_OUT1 - * 0b101110..AOI1_OUT2 - * 0b101111..AOI1_OUT3 - * 0b110000..TMPR_OUT - * 0b110001-0b111111..None - */ -#define INPUTMUX_TIMER2CAP_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAP_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAP_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER2CAP */ -#define INPUTMUX_TIMER2CAP_COUNT (4U) - -/*! @name TIMER2TRIG - Trigger register for TIMER2 */ -/*! @{ */ - -#define INPUTMUX_TIMER2TRIG_TRIGIN_MASK (0x3FU) -#define INPUTMUX_TIMER2TRIG_TRIGIN_SHIFT (0U) -/*! TRIGIN - Input number to TIMER2 trigger inputs - * 0b000000..CTIMER_INP0 function selected from IOCON register - * 0b000001..CTIMER_INP1 function selected from IOCON register - * 0b000010..CTIMER_INP2 function selected from IOCON register - * 0b000011..CTIMER_INP3 function selected from IOCON register - * 0b000100..CTIMER_INP4 function selected from IOCON register - * 0b000101..CTIMER_INP5 function selected from IOCON register - * 0b000110..CTIMER_INP6 function selected from IOCON register - * 0b000111..CTIMER_INP7 function selected from IOCON register - * 0b001000..CTIMER_INP8 function selected from IOCON register - * 0b001001..CTIMER_INP9 function selected from IOCON register - * 0b001010..CTIMER_INP10 function selected from IOCON register - * 0b001011..CTIMER_INP11 function selected from IOCON register - * 0b001100..CTIMER_INP12 function selected from IOCON register - * 0b001101..CTIMER_INP13 function selected from IOCON register - * 0b001110..CTIMER_INP14 function selected from IOCON register - * 0b001111..CTIMER_INP15 function selected from IOCON register - * 0b010000..CTIMER_INP16 function selected from IOCON register - * 0b010001..CTIMER_INP17 function selected from IOCON register - * 0b010010..CTIMER_INP18 function selected from IOCON register - * 0b010011..CTIMER_INP19 function selected from IOCON register - * 0b010100..USB0_FRAME_TOGGLE - * 0b010101..Reserved - * 0b010110..ACMP0_OUT from analog comparator - * 0b010111..SHARED_I2S_WS0 output from I2S pin sharing - * 0b011000..SHARED_I2S_WS1 output from I2S pin sharing - * 0b011001..ADC0_IRQ - * 0b011010..ADC1_IRQ - * 0b011011..HSCMP0_OUT - * 0b011100..HSCMP1_OUT - * 0b011101..HSCMP2_OUT - * 0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 - * 0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 - * 0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 - * 0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 - * 0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 - * 0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 - * 0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 - * 0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 - * 0b100110..ENC0_CMP/POS_MATCH - * 0b100111..ENC1_CMP/POS_MATCH - * 0b101000..AOI0_OUT0 - * 0b101001..AOI0_OUT1 - * 0b101010..AOI0_OUT2 - * 0b101011..AOI0_OUT3 - * 0b101100..AOI1_OUT0 - * 0b101101..AOI1_OUT1 - * 0b101110..AOI1_OUT2 - * 0b101111..AOI1_OUT3 - * 0b110000..TMPR_OUT - * 0b110001-0b111111..None - */ -#define INPUTMUX_TIMER2TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2TRIG_TRIGIN_SHIFT)) & INPUTMUX_TIMER2TRIG_TRIGIN_MASK) -/*! @} */ - -/*! @name EZHARCHB_INMUX - Inputmux register for EZH arch B inputs */ -/*! @{ */ - -#define INPUTMUX_EZHARCHB_INMUX_INP_MASK (0x7FU) -#define INPUTMUX_EZHARCHB_INMUX_INP_SHIFT (0U) -/*! INP - Input number select to EZHARCHB input - * 0b0000000-0b0001111..GPI00_0 to GPIO0_15 functions synced to system clock, selected from IOCON register - * 0b0010000..SCT_OUT8 output from SCTimer, synced to system clock - * 0b0010001..SCT_OUT9 output from SCTimer, synced to system clock - * 0b0010010..Reserved - * 0b0010011..Reserved - * 0b0010100..MRT_IRQ0 Multi-rate timer interrupt request 0 - * 0b0010101..MRT_IRQ1 Multi-rate timer interrupt request 1 - * 0b0010110..T4_MAT3 ctimer 4 match[3] output - * 0b0010111..T4_MAT2 ctimer 4 match[2] output - * 0b0011000..T3_MAT3 ctimer 3 match[3] output - * 0b0011001..T3_MAT2 ctimer 3 match[2] output - * 0b0011010..T1_MAT3 ctimer 1 match[3] output - * 0b0011011..T1_MAT2 ctimer 1 match[2] output - * 0b0011100..UTICK0_IRQ Micro-tick timer interrupt, synced to system clock - * 0b0011101..WDT_IRQ Watchdog Timer interrupt request, synced to system clock - * 0b0011110..ADC0_IRQ interrupt request from ADC - * 0b0011111..ACMP0_IRQ Combined Analog comparator interrupt request - * 0b0100000..LSPI_HS_IRQ High speed Serial Peripheral interface interrupt request - * 0b0100001..FLEXCOMM7_IRQ Flexcomm7 interrupt synced to system clock - * 0b0100010..FLEXCOMM6_IRQ Flexcomm6 interrupt synced to system clock - * 0b0100011..FLEXCOMM5_IRQ Flexcomm5 interrupt synced to system clock - * 0b0100100..FLEXCOMM4_IRQ Flexcomm4 interrupt synced to system clock - * 0b0100101..FLEXCOMM3_IRQ Flexcomm3 interrupt synced to system clock - * 0b0100110..FLEXCOMM2_IRQ Flexcomm2 interrupt synced to system clock - * 0b0100111..FLEXCOMM1_IRQ Flexcomm1 interrupt synced to system clock - * 0b0101000..FLEXCOMM0_IRQ Flexcomm0 interrupt synced to system clock - * 0b0101001..DMA0_IRQ DMA0 interrupt request - * 0b0101010..DMA1_IRQ DMA1 interrupt request - * 0b0101011..SYS_IRQ combined WDT_INT Watchdog Timer interrupt request | FLASH_IRQ Flash interrupt request | BOD_IRQ BrownOut Detection interrupt request - * 0b0101100..RTC_COMBO_IRQ Real Time Clock Combined Alarm | Wake-up interrupt request - * 0b0101101..ARM_TXEV interrupt event from CPU0 - * 0b0101110..GPIOINT_BMATCH GPIO_INT boolean pattern match output - * 0b0101111..Reserved - * 0b0110000..Reserved - * 0b0110001..ACMP_OUT output from analog comparator - * 0b0110010..USB0_FRAME_TOGGLE - * 0b0110011..Reserved - * 0b0110100..OSTIMER_IRQ OS Timer interrupt request - * 0b0110101..ADC1 interrupt - * 0b0110110..HSCOMP0_IRQ/HSCOMP1_IRQ/HSCOMP2_IRQ - * 0b0110111..DAC0 interrupt - * 0b0111000..DAC1/2 interrupt - * 0b0111001..FlexPWM0 interrupt - * 0b0111010..FlexPWM1 interrupt - * 0b0111011..ENC0 interrupt - * 0b0111100..ENC1 interrupt - * 0b0111101..AOI0_OUT0 - * 0b0111110..AOI1_OUT0 - * 0b0111111..TMPR_OUT - * 0b1000000-0b1111110..Reserved - */ -#define INPUTMUX_EZHARCHB_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EZHARCHB_INMUX_INP_SHIFT)) & INPUTMUX_EZHARCHB_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_EZHARCHB_INMUX */ -#define INPUTMUX_EZHARCHB_INMUX_COUNT (8U) - -/*! @name PINTSEL - Pin interrupt select */ -/*! @{ */ - -#define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU) -#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) -/*! INTPIN - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = - * (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. - */ -#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PINTSEL */ -#define INPUTMUX_PINTSEL_COUNT (8U) - -/*! @name DMA0_ITRIG_INMUX - Trigger select for DMA0 channel */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x3FU) -#define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U) -/*! INP - Trigger input number (binary value) for DMA channel n (n = 0 to 31). - * 0b000000..FlexSPI_RX - * 0b000001..FlexSPI_TX - * 0b000010..GPIO_INT0 - * 0b000011..GPIO_INT1 - * 0b000100..GPIO_INT2 - * 0b000101..GPIO_INT3 - * 0b000110..T0_DMAREQ_M0 - * 0b000111..T0_DMAREQ_M1 - * 0b001000..T1_DMAREQ_M0 - * 0b001001..T1_DMAREQ_M1 - * 0b001010..T2_DMAREQ_M0 - * 0b001011..T2_DMAREQ_M1 - * 0b001100..T3_DMAREQ_M0 - * 0b001101..T3_DMAREQ_M1 - * 0b001110..T4_DMAREQ_M0 - * 0b001111..T4_DMAREQ_M1 - * 0b010000..ACMP0_OUT - * 0b010001..SDMA0_TRIGOUT_A - * 0b010010..SDMA0_TRIGOUT_B - * 0b010011..SDMA0_TRIGOUT_C - * 0b010100..SDMA0_TRIGOUT_D - * 0b010101..SCT_DMA0 - * 0b010110..SCT_DMA1 - * 0b010111..ADC0_tcomp[0] - * 0b011000..ADC1_tcomp[0] - * 0b011001..HSCMP0 - * 0b011010..HSCMP1 - * 0b011011..HSCMP2 - * 0b011100..AOI0_OUT0 - * 0b011101..AOI0_OUT1 - * 0b011110..AOI0_OUT2 - * 0b011111..AOI0_OUT3 - * 0b100000..AOI1_OUT0 - * 0b100001..AOI1_OUT1 - * 0b100010..AOI1_OUT2 - * 0b100011..AOI1_OUT3 - * 0b100100..FlexPWM0_req_capt0 - * 0b100101..FlexPWM0_req_capt1 - * 0b100110..FlexPWM0_req_capt2 - * 0b100111..FlexPWM0_req_capt3 - * 0b101000..FlexPWM0_req_val0 - * 0b101001..FlexPWM0_req_val1 - * 0b101010..FlexPWM0_req_val2 - * 0b101011..FlexPWM0_req_val3 - * 0b101100..FlexPWM1_req_capt0 - * 0b101101..FlexPWM1_req_capt1 - * 0b101110..FlexPWM1_req_capt2 - * 0b101111..FlexPWM1_req_capt3 - * 0b110000..FlexPWM1_req_val0 - * 0b110001..FlexPWM1_req_val1 - * 0b110010..FlexPWM1_req_val2 - * 0b110011..FlexPWM1_req_val3 - * 0b110100..TMPR_OUT - * 0b110110-0b111111..Reserved - */ -#define INPUTMUX_DMA0_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA0_ITRIG_INMUX */ -#define INPUTMUX_DMA0_ITRIG_INMUX_COUNT (32U) - -/*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection for DMA0 input trigger */ -/*! @{ */ - -#define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x3FU) -#define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U) -/*! INP - DMA trigger output number (binary value) for DMA channel n (n = 0 to 52). - */ -#define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA0_OTRIG_INMUX */ -#define INPUTMUX_DMA0_OTRIG_INMUX_COUNT (7U) - -/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ -/*! @{ */ - -#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) -/*! CLKIN - Clock source number (binary value) for frequency measure function target clock. - * 0b00000..XTAL32MHz - * 0b00001..FRO_OSC_12M - * 0b00010..FRO_OSC_96M - * 0b00011..WDOSC (FRO1M) - * 0b00100..32KHZ_OSC - * 0b00101..MAIN_SYS_CLOCK - * 0b00110..FREQME_GPIO_CLK_A - * 0b00111..FREQME_GPIO_CLK_B - * 0b01000..AOI0_OUT2 - * 0b01001..AOI1_OUT2 - */ -#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) -/*! @} */ - -/*! @name FREQMEAS_TAR - Selection for frequency measurement target clock */ -/*! @{ */ - -#define INPUTMUX_FREQMEAS_TAR_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_TAR_CLKIN_SHIFT (0U) -/*! CLKIN - Clock source number (binary value) for frequency measure function target clock - * 0b00000..XTAL32MHz - * 0b00001..FRO_OSC_12M - * 0b00010..FRO_OSC_96M - * 0b00011..WDOSC (FRO1M) - * 0b00100..32KHZ_OSC - * 0b00101..MAIN_SYS_CLOCK - * 0b00110..FREQME_GPIO_CLK_A - * 0b00111..FREQME_GPIO_CLK_B - * 0b01000..AOI0_OUT2 - * 0b01001..AOI1_OUT2 - */ -#define INPUTMUX_FREQMEAS_TAR_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TAR_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TAR_CLKIN_MASK) -/*! @} */ - -/*! @name TIMER3CAP - Capture select register for TIMER3 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER3CAP_CAPTSEL_MASK (0x3FU) -#define INPUTMUX_TIMER3CAP_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 5 - * 0b000000..CTIMER_INP0 function selected from IOCON register - * 0b000001..CTIMER_INP1 function selected from IOCON register - * 0b000010..CTIMER_INP2 function selected from IOCON register - * 0b000011..CTIMER_INP3 function selected from IOCON register - * 0b000100..CTIMER_INP4 function selected from IOCON register - * 0b000101..CTIMER_INP5 function selected from IOCON register - * 0b000110..CTIMER_INP6 function selected from IOCON register - * 0b000111..CTIMER_INP7 function selected from IOCON register - * 0b001000..CTIMER_INP8 function selected from IOCON register - * 0b001001..CTIMER_INP9 function selected from IOCON register - * 0b001010..CTIMER_INP10 function selected from IOCON register - * 0b001011..CTIMER_INP11 function selected from IOCON register - * 0b001100..CTIMER_INP12 function selected from IOCON register - * 0b001101..CTIMER_INP13 function selected from IOCON register - * 0b001110..CTIMER_INP14 function selected from IOCON register - * 0b001111..CTIMER_INP15 function selected from IOCON register - * 0b010000..CTIMER_INP16 function selected from IOCON register - * 0b010001..CTIMER_INP17 function selected from IOCON register - * 0b010010..CTIMER_INP18 function selected from IOCON register - * 0b010011..CTIMER_INP19 function selected from IOCON register - * 0b010100..USB0_FRAME_TOGGLE - * 0b010101..Reserved - * 0b010110..ACMP0_OUT from analog comparator - * 0b010111..SHARED_I2S_WS0 output from I2S pin sharing - * 0b011000..SHARED_I2S_WS1 output from I2S pin sharing - * 0b011001..ADC0_IRQ - * 0b011010..ADC1_IRQ - * 0b011011..HSCMP0_OUT - * 0b011100..HSCMP1_OUT - * 0b011101..HSCMP2_OUT - * 0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 - * 0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 - * 0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 - * 0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 - * 0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 - * 0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 - * 0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 - * 0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 - * 0b100110..ENC0_CMP/POS_MATCH - * 0b100111..ENC1_CMP/POS_MATCH - * 0b101000..AOI0_OUT0 - * 0b101001..AOI0_OUT1 - * 0b101010..AOI0_OUT2 - * 0b101011..AOI0_OUT3 - * 0b101100..AOI1_OUT0 - * 0b101101..AOI1_OUT1 - * 0b101110..AOI1_OUT2 - * 0b101111..AOI1_OUT3 - * 0b110000..TMPR_OUT - * 0b110001-0b111111..None - */ -#define INPUTMUX_TIMER3CAP_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAP_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAP_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER3CAP */ -#define INPUTMUX_TIMER3CAP_COUNT (4U) - -/*! @name TIMER3TRIG - Trigger register for TIMER3 */ -/*! @{ */ - -#define INPUTMUX_TIMER3TRIG_TRIGIN_MASK (0x3FU) -#define INPUTMUX_TIMER3TRIG_TRIGIN_SHIFT (0U) -/*! TRIGIN - Input number to TIMER3 trigger inputs - * 0b000000..CTIMER_INP0 function selected from IOCON register - * 0b000001..CTIMER_INP1 function selected from IOCON register - * 0b000010..CTIMER_INP2 function selected from IOCON register - * 0b000011..CTIMER_INP3 function selected from IOCON register - * 0b000100..CTIMER_INP4 function selected from IOCON register - * 0b000101..CTIMER_INP5 function selected from IOCON register - * 0b000110..CTIMER_INP6 function selected from IOCON register - * 0b000111..CTIMER_INP7 function selected from IOCON register - * 0b001000..CTIMER_INP8 function selected from IOCON register - * 0b001001..CTIMER_INP9 function selected from IOCON register - * 0b001010..CTIMER_INP10 function selected from IOCON register - * 0b001011..CTIMER_INP11 function selected from IOCON register - * 0b001100..CTIMER_INP12 function selected from IOCON register - * 0b001101..CTIMER_INP13 function selected from IOCON register - * 0b001110..CTIMER_INP14 function selected from IOCON register - * 0b001111..CTIMER_INP15 function selected from IOCON register - * 0b010000..CTIMER_INP16 function selected from IOCON register - * 0b010001..CTIMER_INP17 function selected from IOCON register - * 0b010010..CTIMER_INP18 function selected from IOCON register - * 0b010011..CTIMER_INP19 function selected from IOCON register - * 0b010100..USB0_FRAME_TOGGLE - * 0b010101..Reserved - * 0b010110..ACMP0_OUT from analog comparator - * 0b010111..SHARED_I2S_WS0 output from I2S pin sharing - * 0b011000..SHARED_I2S_WS1 output from I2S pin sharing - * 0b011001..ADC0_IRQ - * 0b011010..ADC1_IRQ - * 0b011011..HSCMP0_OUT - * 0b011100..HSCMP1_OUT - * 0b011101..HSCMP2_OUT - * 0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 - * 0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 - * 0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 - * 0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 - * 0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 - * 0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 - * 0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 - * 0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 - * 0b100110..ENC0_CMP/POS_MATCH - * 0b100111..ENC1_CMP/POS_MATCH - * 0b101000..AOI0_OUT0 - * 0b101001..AOI0_OUT1 - * 0b101010..AOI0_OUT2 - * 0b101011..AOI0_OUT3 - * 0b101100..AOI1_OUT0 - * 0b101101..AOI1_OUT1 - * 0b101110..AOI1_OUT2 - * 0b101111..AOI1_OUT3 - * 0b110000..TMPR_OUT - * 0b110001-0b111111..None - */ -#define INPUTMUX_TIMER3TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3TRIG_TRIGIN_SHIFT)) & INPUTMUX_TIMER3TRIG_TRIGIN_MASK) -/*! @} */ - -/*! @name TIMER4CAP - Capture select register for TIMER4 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER4CAP_CAPTSEL_MASK (0x3FU) -#define INPUTMUX_TIMER4CAP_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 5 - * 0b000000..CTIMER_INP0 function selected from IOCON register - * 0b000001..CTIMER_INP1 function selected from IOCON register - * 0b000010..CTIMER_INP2 function selected from IOCON register - * 0b000011..CTIMER_INP3 function selected from IOCON register - * 0b000100..CTIMER_INP4 function selected from IOCON register - * 0b000101..CTIMER_INP5 function selected from IOCON register - * 0b000110..CTIMER_INP6 function selected from IOCON register - * 0b000111..CTIMER_INP7 function selected from IOCON register - * 0b001000..CTIMER_INP8 function selected from IOCON register - * 0b001001..CTIMER_INP9 function selected from IOCON register - * 0b001010..CTIMER_INP10 function selected from IOCON register - * 0b001011..CTIMER_INP11 function selected from IOCON register - * 0b001100..CTIMER_INP12 function selected from IOCON register - * 0b001101..CTIMER_INP13 function selected from IOCON register - * 0b001110..CTIMER_INP14 function selected from IOCON register - * 0b001111..CTIMER_INP15 function selected from IOCON register - * 0b010000..CTIMER_INP16 function selected from IOCON register - * 0b010001..CTIMER_INP17 function selected from IOCON register - * 0b010010..CTIMER_INP18 function selected from IOCON register - * 0b010011..CTIMER_INP19 function selected from IOCON register - * 0b010100..USB0_FRAME_TOGGLE - * 0b010101..Reserved - * 0b010110..ACMP0_OUT from analog comparator - * 0b010111..SHARED_I2S_WS0 output from I2S pin sharing - * 0b011000..SHARED_I2S_WS1 output from I2S pin sharing - * 0b011001..ADC0_IRQ - * 0b011010..ADC1_IRQ - * 0b011011..HSCMP0_OUT - * 0b011100..HSCMP1_OUT - * 0b011101..HSCMP2_OUT - * 0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 - * 0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 - * 0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 - * 0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 - * 0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 - * 0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 - * 0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 - * 0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 - * 0b100110..ENC0_CMP/POS_MATCH - * 0b100111..ENC1_CMP/POS_MATCH - * 0b101000..AOI0_OUT0 - * 0b101001..AOI0_OUT1 - * 0b101010..AOI0_OUT2 - * 0b101011..AOI0_OUT3 - * 0b101100..AOI1_OUT0 - * 0b101101..AOI1_OUT1 - * 0b101110..AOI1_OUT2 - * 0b101111..AOI1_OUT3 - * 0b110000..TMPR_OUT - * 0b110001-0b111111..None - */ -#define INPUTMUX_TIMER4CAP_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAP_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAP_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER4CAP */ -#define INPUTMUX_TIMER4CAP_COUNT (4U) - -/*! @name TIMER4TRIG - Trigger register for TIMER4 */ -/*! @{ */ - -#define INPUTMUX_TIMER4TRIG_TRIGIN_MASK (0x3FU) -#define INPUTMUX_TIMER4TRIG_TRIGIN_SHIFT (0U) -/*! TRIGIN - Input number to TIMER4 trigger inputs - * 0b000000..CTIMER_INP0 function selected from IOCON register - * 0b000001..CTIMER_INP1 function selected from IOCON register - * 0b000010..CTIMER_INP2 function selected from IOCON register - * 0b000011..CTIMER_INP3 function selected from IOCON register - * 0b000100..CTIMER_INP4 function selected from IOCON register - * 0b000101..CTIMER_INP5 function selected from IOCON register - * 0b000110..CTIMER_INP6 function selected from IOCON register - * 0b000111..CTIMER_INP7 function selected from IOCON register - * 0b001000..CTIMER_INP8 function selected from IOCON register - * 0b001001..CTIMER_INP9 function selected from IOCON register - * 0b001010..CTIMER_INP10 function selected from IOCON register - * 0b001011..CTIMER_INP11 function selected from IOCON register - * 0b001100..CTIMER_INP12 function selected from IOCON register - * 0b001101..CTIMER_INP13 function selected from IOCON register - * 0b001110..CTIMER_INP14 function selected from IOCON register - * 0b001111..CTIMER_INP15 function selected from IOCON register - * 0b010000..CTIMER_INP16 function selected from IOCON register - * 0b010001..CTIMER_INP17 function selected from IOCON register - * 0b010010..CTIMER_INP18 function selected from IOCON register - * 0b010011..CTIMER_INP19 function selected from IOCON register - * 0b010100..USB0_FRAME_TOGGLE - * 0b010101..Reserved - * 0b010110..ACMP0_OUT from analog comparator - * 0b010111..SHARED_I2S_WS0 output from I2S pin sharing - * 0b011000..SHARED_I2S_WS1 output from I2S pin sharing - * 0b011001..ADC0_IRQ - * 0b011010..ADC1_IRQ - * 0b011011..HSCMP0_OUT - * 0b011100..HSCMP1_OUT - * 0b011101..HSCMP2_OUT - * 0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 - * 0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 - * 0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 - * 0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 - * 0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 - * 0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 - * 0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 - * 0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 - * 0b100110..ENC0_CMP/POS_MATCH - * 0b100111..ENC1_CMP/POS_MATCH - * 0b101000..AOI0_OUT0 - * 0b101001..AOI0_OUT1 - * 0b101010..AOI0_OUT2 - * 0b101011..AOI0_OUT3 - * 0b101100..AOI1_OUT0 - * 0b101101..AOI1_OUT1 - * 0b101110..AOI1_OUT2 - * 0b101111..AOI1_OUT3 - * 0b110000..TMPR_OUT - * 0b110001-0b111111..None - */ -#define INPUTMUX_TIMER4TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4TRIG_TRIGIN_SHIFT)) & INPUTMUX_TIMER4TRIG_TRIGIN_MASK) -/*! @} */ - -/*! @name PINTSECSEL - Pin interrupt secure select */ -/*! @{ */ - -#define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU) -#define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U) -/*! INTPIN - Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: - * INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31. - */ -#define INPUTMUX_PINTSECSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PINTSECSEL */ -#define INPUTMUX_PINTSECSEL_COUNT (2U) - -/*! @name DMA1_ITRIG_INMUX - Trigger select for DMA1 channel */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U) -/*! INP - Trigger input number (binary value) for DMA channel n (n = 0 to 14). - * 0b00000..Pin interrupt 0 (GPIO_INT0) - * 0b00001..Pin interrupt 1 (GPIO_INT1) - * 0b00010..Pin interrupt 2 (GPIO_INT2) - * 0b00011..Pin interrupt 3 (GPIO_INT3) - * 0b00100..Timer CTIMER0 Match 0 (T0_DMAREQ_M0) - * 0b00101..Timer CTIMER0 Match 1 (T0_DMAREQ_M1) - * 0b00110..Timer CTIMER2 Match 0 (T2_DMAREQ_M0) - * 0b00111..Timer CTIMER4 Match 0 (T4_DMAREQ_M0) - * 0b01000..SDMA1_TRIGOUT_A - * 0b01001..SDMA1_TRIGOUT_B - * 0b01010..SDMA1_TRIGOUT_C - * 0b01011..SDMA1_TRIGOUT_D - * 0b01100..SCT_DMA_REQ0 - * 0b01101..SCT_DMA_REQ1 - * 0b01110..FlexSPI_RX - * 0b01111..FlexSPI_TX - * 0b10000..AOI0_OUT0 - * 0b10001..AOI0_OUT1 - * 0b10010..AOI0_OUT2 - * 0b10011..AOI0_OUT3 - * 0b10100..AOI1_OUT0 - * 0b10101..AOI1_OUT1 - * 0b10110..AOI1_OUT2 - * 0b10111..AOI1_OUT3 - * 0b11000..TMPR_OUT - * 0b11001-0b11111..Reserved - */ -#define INPUTMUX_DMA1_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA1_ITRIG_INMUX */ -#define INPUTMUX_DMA1_ITRIG_INMUX_COUNT (16U) - -/*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection for DMA1 input trigger */ -/*! @{ */ - -#define INPUTMUX_DMA1_OTRIG_INMUX_SDMA1_CH_TRIGOUT_MASK (0xFU) -#define INPUTMUX_DMA1_OTRIG_INMUX_SDMA1_CH_TRIGOUT_SHIFT (0U) -/*! SDMA1_CH_TRIGOUT - DMA trigger output number (binary value) for DMA channel n (n = 0 to 15). - * 0b0000..SDMA1_CH0_TRIGOUT - * 0b0001..SDMA1_CH1_TRIGOUT - * 0b0010..SDMA1_CH2_TRIGOUT - * 0b0011..SDMA1_CH3_TRIGOUT - * 0b0100..SDMA1_CH4_TRIGOUT - * 0b0101..SDMA1_CH5_TRIGOUT - * 0b0110..SDMA1_CH6_TRIGOUT - * 0b0111..SDMA1_CH7_TRIGOUT - * 0b1000..SDMA1_CH8_TRIGOUT - * 0b1001..SDMA1_CH9_TRIGOUT - * 0b1010..SDMA1_CH10_TRIGOUT - * 0b1011..SDMA1_CH11_TRIGOUT - * 0b1100..SDMA1_CH12_TRIGOUT - * 0b1101..SDMA1_CH13_TRIGOUT - * 0b1110-0b1111..Reserved - */ -#define INPUTMUX_DMA1_OTRIG_INMUX_SDMA1_CH_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_SDMA1_CH_TRIGOUT_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_SDMA1_CH_TRIGOUT_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA1_OTRIG_INMUX */ -#define INPUTMUX_DMA1_OTRIG_INMUX_COUNT (4U) - -/*! @name HSCMP0_TRIG - Input connections for HSCMP0 */ -/*! @{ */ - -#define INPUTMUX_HSCMP0_TRIG_TRIGIN_MASK (0x3FU) -#define INPUTMUX_HSCMP0_TRIG_TRIGIN_SHIFT (0U) -/*! TRIGIN - CMP0 input trigger - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT6 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT6 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T0_MAT0 - * 0b001001..T4_MAT0 - * 0b001010..Reserved - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC1_tcomp[0] - * 0b001111..Reserved - * 0b010000..Reserved - * 0b010001..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 - * 0b010010..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 - * 0b010011..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 - * 0b010100..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 - * 0b010101..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 - * 0b010110..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 - * 0b010111..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 - * 0b011000..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 - * 0b011001..ENC0_CMP/POS_MATCH - * 0b011010..ENC1_CMP/POS_MATCH - * 0b011011..AOI0_OUT0 - * 0b011100..AOI0_OUT1 - * 0b011101..AOI0_OUT2 - * 0b011110..AOI0_OUT3 - * 0b011111..AOI1_OUT0 - * 0b100000..AOI1_OUT1 - * 0b100001..AOI1_OUT2 - * 0b100010..AOI1_OUT3 - * 0b100011..DMA0_TRIGOUT0 - * 0b100100..DMA0_TRIGOUT1 - * 0b100101..DMA0_TRIGOUT2 - */ -#define INPUTMUX_HSCMP0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_HSCMP0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_HSCMP0_TRIG_TRIGIN_MASK) -/*! @} */ - -/*! @name ADC0_TRIGN_ADC0_TRIG - ADC0 Trigger input connections */ -/*! @{ */ - -#define INPUTMUX_ADC0_TRIGN_ADC0_TRIG_TRIGIN_MASK (0x3FU) -#define INPUTMUX_ADC0_TRIGN_ADC0_TRIG_TRIGIN_SHIFT (0U) -/*! TRIGIN - ADC0 trigger inputs - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT1 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT9 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T3_MAT3 - * 0b001001..T4_MAT3 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM0_SM0_MUX_TRIG0 - * 0b011001..PWM0_SM0_MUX_TRIG1 - * 0b011010..PWM0_SM1_MUX_TRIG0 - * 0b011011..PWM0_SM1_MUX_TRIG1 - * 0b011100..PWM0_SM2_MUX_TRIG0 - * 0b011101..PWM0_SM2_MUX_TRIG1 - * 0b011110..PWM0_SM3_MUX_TRIG0 - * 0b011111..PWM0_SM3_MUX_TRIG1 - * 0b100000..PWM1_SM0_MUX_TRIG0 - * 0b100001..PWM1_SM0_MUX_TRIG1 - * 0b100010..PWM1_SM1_MUX_TRIG0 - * 0b100011..PWM1_SM1_MUX_TRIG1 - * 0b100100..PWM1_SM2_MUX_TRIG0 - * 0b100101..PWM1_SM2_MUX_TRIG1 - * 0b100110..PWM1_SM3_MUX_TRIG0 - * 0b100111..PWM1_SM3_MUX_TRIG1 - * 0b101000..ENC0_CMP/POS_MATCH - * 0b101001..ENC1_CMP/POS_MATCH - * 0b101010..AOI0_OUT0 - * 0b101011..AOI0_OUT1 - * 0b101100..AOI0_OUT2 - * 0b101101..AOI0_OUT3 - * 0b101110..AOI1_OUT0 - * 0b101111..AOI1_OUT1 - * 0b110000..AOI1_OUT2 - * 0b110001..AOI1_OUT3 - * 0b110010..DMA0_TRIGOUT0 - * 0b110011..DMA0_TRIGOUT1 - * 0b110100..DMA0_TRIGOUT2 - * 0b110101-0b111111..None - */ -#define INPUTMUX_ADC0_TRIGN_ADC0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC0_TRIGN_ADC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC0_TRIGN_ADC0_TRIG_TRIGIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_ADC0_TRIGN_ADC0_TRIG */ -#define INPUTMUX_ADC0_TRIGN_ADC0_TRIG_COUNT (4U) - -/*! @name ADC1_TRIGN_ADC1_TRIG - ADC1 Trigger input connections */ -/*! @{ */ - -#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_MASK (0x3FU) -#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_SHIFT (0U) -/*! TRIGIN - ADC1 trigger inputs - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT2 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT3 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T3_MAT2 - * 0b001001..T4_MAT1 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM0_SM0_MUX_TRIG0 - * 0b011001..PWM0_SM0_MUX_TRIG1 - * 0b011010..PWM0_SM1_MUX_TRIG0 - * 0b011011..PWM0_SM1_MUX_TRIG1 - * 0b011100..PWM0_SM2_MUX_TRIG0 - * 0b011101..PWM0_SM2_MUX_TRIG1 - * 0b011110..PWM0_SM3_MUX_TRIG0 - * 0b011111..PWM0_SM3_MUX_TRIG1 - * 0b100000..PWM1_SM0_MUX_TRIG0 - * 0b100001..PWM1_SM0_MUX_TRIG1 - * 0b100010..PWM1_SM1_MUX_TRIG0 - * 0b100011..PWM1_SM1_MUX_TRIG1 - * 0b100100..PWM1_SM2_MUX_TRIG0 - * 0b100101..PWM1_SM2_MUX_TRIG1 - * 0b100110..PWM1_SM3_MUX_TRIG0 - * 0b100111..PWM1_SM3_MUX_TRIG1 - * 0b101000..ENC0_CMP/POS_MATCH - * 0b101001..ENC1_CMP/POS_MATCH - * 0b101010..AOI0_OUT0 - * 0b101011..AOI0_OUT1 - * 0b101100..AOI0_OUT2 - * 0b101101..AOI0_OUT3 - * 0b101110..AOI1_OUT0 - * 0b101111..AOI1_OUT1 - * 0b110000..AOI1_OUT2 - * 0b110001..AOI1_OUT3 - * 0b110010..DMA0_TRIGOUT0 - * 0b110011..DMA0_TRIGOUT1 - * 0b110100..DMA0_TRIGOUT2 - * 0b110101-0b111111..None - */ -#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_ADC1_TRIGN_ADC1_TRIG */ -#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_COUNT (4U) - -/*! @name DAC0_TRIG - DAC0 Trigger Inputs */ -/*! @{ */ - -#define INPUTMUX_DAC0_TRIG_TRIGIN_MASK (0x1FU) -#define INPUTMUX_DAC0_TRIG_TRIGIN_SHIFT (0U) -/*! TRIGIN - DAC0 trigger input - * 0b00000..PIN_INT0 - * 0b00001..PIN_INT3 - * 0b00010..SCT_OUT4 - * 0b00011..SCT_OUT5 - * 0b00100..SCT_OUT0 - * 0b00101..T0_MAT3 - * 0b00110..T1_MAT3 - * 0b00111..T2_MAT3 - * 0b01000..T2_MAT0 - * 0b01001..T3_MAT0 - * 0b01010..ACMP0_OUT - * 0b01011..ARM_TXEV - * 0b01100..GPIOINT_BMATCH - * 0b01101..ADC0_tcomp[0] - * 0b01110..ADC1_tcomp[0] - * 0b01111..HSCMP0_OUT - * 0b10000..HSCMP1_OUT - * 0b10001..HSCMP2_OUT - * 0b10010..AOI0_OUT0 - * 0b10011..AOI0_OUT1 - * 0b10100..AOI0_OUT2 - * 0b10101..AOI0_OUT3 - * 0b10110..AOI1_OUT0 - * 0b10111..AOI1_OUT1 - * 0b11000..AOI1_OUT2 - * 0b11001..AOI1_OUT3 - * 0b11010..DMA0_TRIGOUT0 - * 0b11011..DMA0_TRIGOUT1 - * 0b11100..DMA0_TRIGOUT2 - */ -#define INPUTMUX_DAC0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DAC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_DAC0_TRIG_TRIGIN_MASK) -/*! @} */ - -/*! @name DAC1_TRIG - DAC1 Trigger Inputs */ -/*! @{ */ - -#define INPUTMUX_DAC1_TRIG_TRIGIN_MASK (0x1FU) -#define INPUTMUX_DAC1_TRIG_TRIGIN_SHIFT (0U) -/*! TRIGIN - DAC1 trigger input - * 0b00000..PIN_INT0 - * 0b00001..PIN_INT4 - * 0b00010..SCT_OUT4 - * 0b00011..SCT_OUT5 - * 0b00100..SCT_OUT1 - * 0b00101..T0_MAT3 - * 0b00110..T1_MAT3 - * 0b00111..T2_MAT3 - * 0b01000..T2_MAT1 - * 0b01001..T3_MAT1 - * 0b01010..ACMP0_OUT - * 0b01011..ARM_TXEV - * 0b01100..GPIOINT_BMATCH - * 0b01101..ADC0_tcomp[1] - * 0b01110..ADC1_tcomp[1] - * 0b01111..HSCMP0_OUT - * 0b10000..HSCMP1_OUT - * 0b10001..HSCMP2_OUT - * 0b10010..AOI0_OUT0 - * 0b10011..AOI0_OUT1 - * 0b10100..AOI0_OUT2 - * 0b10101..AOI0_OUT3 - * 0b10110..AOI1_OUT0 - * 0b10111..AOI1_OUT1 - * 0b11000..AOI1_OUT2 - * 0b11001..AOI1_OUT3 - * 0b11010..DMA0_TRIGOUT0 - * 0b11011..DMA0_TRIGOUT1 - * 0b11100..DMA0_TRIGOUT2 - */ -#define INPUTMUX_DAC1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DAC1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_DAC1_TRIG_TRIGIN_MASK) -/*! @} */ - -/*! @name DAC2_TRIG - DAC2 Trigger Inputs */ -/*! @{ */ - -#define INPUTMUX_DAC2_TRIG_TRIGIN_MASK (0x1FU) -#define INPUTMUX_DAC2_TRIG_TRIGIN_SHIFT (0U) -/*! TRIGIN - DAC2 trigger input - * 0b00000..PIN_INT0 - * 0b00001..PIN_INT5 - * 0b00010..SCT_OUT4 - * 0b00011..SCT_OUT5 - * 0b00100..SCT_OUT2 - * 0b00101..T0_MAT3 - * 0b00110..T1_MAT3 - * 0b00111..T2_MAT3 - * 0b01000..T2_MAT2 - * 0b01001..T3_MAT2 - * 0b01010..ACMP0_OUT - * 0b01011..ARM_TXEV - * 0b01100..GPIOINT_BMATCH - * 0b01101..ADC0_tcomp[2] - * 0b01110..ADC1_tcomp[2] - * 0b01111..HSCMP0_OUT - * 0b10000..HSCMP1_OUT - * 0b10001..HSCMP2_OUT - * 0b10010..AOI0_OUT0 - * 0b10011..AOI0_OUT1 - * 0b10100..AOI0_OUT2 - * 0b10101..AOI0_OUT3 - * 0b10110..AOI1_OUT0 - * 0b10111..AOI1_OUT1 - * 0b11000..AOI1_OUT2 - * 0b11001..AOI1_OUT3 - * 0b11010..DMA0_TRIGOUT0 - * 0b11011..DMA0_TRIGOUT1 - * 0b11100..DMA0_TRIGOUT2 - */ -#define INPUTMUX_DAC2_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DAC2_TRIG_TRIGIN_SHIFT)) & INPUTMUX_DAC2_TRIG_TRIGIN_MASK) -/*! @} */ - -/*! @name ENC0_TRIG - ENC0 Trigger Input Connections */ -/*! @{ */ - -#define INPUTMUX_ENC0_TRIG_TRIGIN_MASK (0x3FU) -#define INPUTMUX_ENC0_TRIG_TRIGIN_SHIFT (0U) -/*! TRIGIN - ENC0 input trigger - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT4 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT1 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T1_MAT0 - * 0b001001..T3_MAT0 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM1_SM0_MUX_TRIG0 - * 0b011001..PWM1_SM0_MUX_TRIG1 - * 0b011010..PWM1_SM1_MUX_TRIG0 - * 0b011011..PWM1_SM1_MUX_TRIG1 - * 0b011100..PWM1_SM2_MUX_TRIG0 - * 0b011101..PWM1_SM2_MUX_TRIG1 - * 0b011110..PWM1_SM3_MUX_TRIG0 - * 0b011111..PWM1_SM3_MUX_TRIG1 - * 0b100000..ENC0_CMP/POS_MATCH - * 0b100001..ENC1_CMP/POS_MATCH - * 0b100010..AOI0_OUT0 - * 0b100011..AOI0_OUT1 - * 0b100100..AOI0_OUT2 - * 0b100101..AOI0_OUT3 - * 0b100110..AOI1_OUT0 - * 0b100111..AOI1_OUT1 - * 0b101000..AOI1_OUT2 - * 0b101001..AOI1_OUT3 - * 0b101010..EXTTRIG_IN0 - * 0b101011..EXTTRIG_IN1 - * 0b101100..EXTTRIG_IN2 - * 0b101101..EXTTRIG_IN3 - * 0b101110..EXTTRIG_IN4 - * 0b101111..EXTTRIG_IN5 - * 0b110000..EXTTRIG_IN6 - * 0b110001..EXTTRIG_IN7 - * 0b110010..EXTTRIG_IN8 - * 0b110011..EXTTRIG_IN9 - * 0b110100..DMA0_TRIGOUT0 - * 0b110101..DMA0_TRIGOUT1 - * 0b110110..DMA0_TRIGOUT2 - */ -#define INPUTMUX_ENC0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ENC0_TRIG_TRIGIN_MASK) -/*! @} */ - -/*! @name ENC0_HOME - ENC0 Input Connections */ -/*! @{ */ - -#define INPUTMUX_ENC0_HOME_ENC0_HOME_MASK (0x3FU) -#define INPUTMUX_ENC0_HOME_ENC0_HOME_SHIFT (0U) -/*! ENC0_HOME - ENC0 Input Connections - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT4 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT1 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T1_MAT0 - * 0b001001..T3_MAT0 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM1_SM0_MUX_TRIG0 - * 0b011001..PWM1_SM0_MUX_TRIG1 - * 0b011010..PWM1_SM0_MUX_TRIG0 - * 0b011011..PWM1_SM1_MUX_TRIG1 - * 0b011100..PWM1_SM2_MUX_TRIG0 - * 0b011101..PWM1_SM2_MUX_TRIG1 - * 0b011110..PWM1_SM3_MUX_TRIG0 - * 0b011111..PWM1_SM3_MUX_TRIG1 - * 0b100000..ENC0_CMP/POS_MATCH - * 0b100001..ENC1_CMP/POS_MATCH - * 0b100010..AOI0_OUT0 - * 0b100011..AOI0_OUT1 - * 0b100100..AOI0_OUT2 - * 0b100101..AOI0_OUT3 - * 0b100110..AOI1_OUT0 - * 0b100111..AOI1_OUT1 - * 0b101000..AOI1_OUT2 - * 0b101001..AOI1_OUT3 - * 0b101010..EXTTRIG_IN0 - * 0b101011..EXTTRIG_IN1 - * 0b101100..EXTTRIG_IN2 - * 0b101101..EXTTRIG_IN3 - * 0b101110..EXTTRIG_IN4 - * 0b101111..EXTTRIG_IN5 - * 0b110000..EXTTRIG_IN6 - * 0b110001..EXTTRIG_IN7 - * 0b110010..EXTTRIG_IN8 - * 0b110011..EXTTRIG_IN9 - * 0b110100..DMA0_TRIGOUT0 - * 0b110101..DMA0_TRIGOUT1 - * 0b110110..DMA0_TRIGOUT2 - */ -#define INPUTMUX_ENC0_HOME_ENC0_HOME(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_HOME_ENC0_HOME_SHIFT)) & INPUTMUX_ENC0_HOME_ENC0_HOME_MASK) -/*! @} */ - -/*! @name ENC0_INDEX - ENC0 Input Connections */ -/*! @{ */ - -#define INPUTMUX_ENC0_INDEX_ENC0_INDEX_MASK (0x3FU) -#define INPUTMUX_ENC0_INDEX_ENC0_INDEX_SHIFT (0U) -/*! ENC0_INDEX - ENC0 Input Connections - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT4 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT1 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T1_MAT0 - * 0b001001..T3_MAT0 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM1_SM0_MUX_TRIG0 - * 0b011001..PWM1_SM0_MUX_TRIG1 - * 0b011010..PWM1_SM1_MUX_TRIG0 - * 0b011011..PWM1_SM1_MUX_TRIG1 - * 0b011100..PWM1_SM2_MUX_TRIG0 - * 0b011101..PWM1_SM2_MUX_TRIG1 - * 0b011110..PWM1_SM3_MUX_TRIG0 - * 0b011111..PWM1_SM3_MUX_TRIG1 - * 0b100000..ENC0_CMP/POS_MATCH - * 0b100001..ENC1_CMP/POS_MATCH - * 0b100010..AOI0_OUT0 - * 0b100011..AOI0_OUT1 - * 0b100100..AOI0_OUT2 - * 0b100101..AOI0_OUT3 - * 0b100110..AOI1_OUT0 - * 0b100111..AOI1_OUT1 - * 0b101000..AOI1_OUT2 - * 0b101001..AOI1_OUT3 - * 0b101010..EXTTRIG_IN0 - * 0b101011..EXTTRIG_IN1 - * 0b101100..EXTTRIG_IN2 - * 0b101101..EXTTRIG_IN3 - * 0b101110..EXTTRIG_IN4 - * 0b101111..EXTTRIG_IN5 - * 0b110000..EXTTRIG_IN6 - * 0b110001..EXTTRIG_IN7 - * 0b110010..EXTTRIG_IN8 - * 0b110011..EXTTRIG_IN9 - * 0b110100..DMA0_TRIGOUT0 - * 0b110101..DMA0_TRIGOUT1 - * 0b110110..DMA0_TRIGOUT2 - */ -#define INPUTMUX_ENC0_INDEX_ENC0_INDEX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_INDEX_ENC0_INDEX_SHIFT)) & INPUTMUX_ENC0_INDEX_ENC0_INDEX_MASK) -/*! @} */ - -/*! @name ENC0_PHASEB - ENC0 Input Connections */ -/*! @{ */ - -#define INPUTMUX_ENC0_PHASEB_ENC0_PHASEB_MASK (0x3FU) -#define INPUTMUX_ENC0_PHASEB_ENC0_PHASEB_SHIFT (0U) -/*! ENC0_PHASEB - ENC0 Input Connections - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT4 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT1 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T1_MAT0 - * 0b001001..T3_MAT0 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM1_SM0_MUX_TRIG0 - * 0b011001..PWM1_SM0_MUX_TRIG1 - * 0b011010..PWM1_SM1_MUX_TRIG0 - * 0b011011..PWM1_SM1_MUX_TRIG1 - * 0b011100..PWM1_SM2_MUX_TRIG0 - * 0b011101..PWM1_SM2_MUX_TRIG1 - * 0b011110..PWM1_SM3_MUX_TRIG0 - * 0b011111..PWM1_SM3_MUX_TRIG1 - * 0b100000..ENC0_CMP/POS_MATCH - * 0b100001..ENC1_CMP/POS_MATCH - * 0b100010..AOI0_OUT0 - * 0b100011..AOI0_OUT1 - * 0b100100..AOI0_OUT2 - * 0b100101..AOI0_OUT3 - * 0b100110..AOI1_OUT0 - * 0b100111..AOI1_OUT1 - * 0b101000..AOI1_OUT2 - * 0b101001..AOI1_OUT3 - * 0b101010..EXTTRIG_IN0 - * 0b101011..EXTTRIG_IN1 - * 0b101100..EXTTRIG_IN2 - * 0b101101..EXTTRIG_IN3 - * 0b101110..EXTTRIG_IN4 - * 0b101111..EXTTRIG_IN5 - * 0b110000..EXTTRIG_IN6 - * 0b110001..EXTTRIG_IN7 - * 0b110010..EXTTRIG_IN8 - * 0b110011..EXTTRIG_IN9 - * 0b110100..DMA0_TRIGOUT0 - * 0b110101..DMA0_TRIGOUT1 - * 0b110110..DMA0_TRIGOUT2 - */ -#define INPUTMUX_ENC0_PHASEB_ENC0_PHASEB(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_PHASEB_ENC0_PHASEB_SHIFT)) & INPUTMUX_ENC0_PHASEB_ENC0_PHASEB_MASK) -/*! @} */ - -/*! @name ENC0_PHASEA - ENC0 Input Connections */ -/*! @{ */ - -#define INPUTMUX_ENC0_PHASEA_ENC0_PHASEA_MASK (0x3FU) -#define INPUTMUX_ENC0_PHASEA_ENC0_PHASEA_SHIFT (0U) -/*! ENC0_PHASEA - ENC0 Input Connections - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT4 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT1 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T1_MAT0 - * 0b001001..T3_MAT0 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM1_SM0_MUX_TRIG0 - * 0b011001..PWM1_SM0_MUX_TRIG1 - * 0b011010..PWM1_SM1_MUX_TRIG0 - * 0b011011..PWM1_SM1_MUX_TRIG1 - * 0b011100..PWM1_SM2_MUX_TRIG0 - * 0b011101..PWM1_SM2_MUX_TRIG1 - * 0b011110..PWM1_SM3_MUX_TRIG0 - * 0b011111..PWM1_SM3_MUX_TRIG1 - * 0b100000..ENC0_CMP/POS_MATCH - * 0b100001..ENC1_CMP/POS_MATCH - * 0b100010..AOI0_OUT0 - * 0b100011..AOI0_OUT1 - * 0b100100..AOI0_OUT2 - * 0b100101..AOI0_OUT3 - * 0b100110..AOI1_OUT0 - * 0b100111..AOI1_OUT1 - * 0b101000..AOI1_OUT2 - * 0b101001..AOI1_OUT3 - * 0b101010..EXTTRIG_IN0 - * 0b101011..EXTTRIG_IN1 - * 0b101100..EXTTRIG_IN2 - * 0b101101..EXTTRIG_IN3 - * 0b101110..EXTTRIG_IN4 - * 0b101111..EXTTRIG_IN5 - * 0b110000..EXTTRIG_IN6 - * 0b110001..EXTTRIG_IN7 - * 0b110010..EXTTRIG_IN8 - * 0b110011..EXTTRIG_IN9 - * 0b110100..DMA0_TRIGOUT0 - * 0b110101..DMA0_TRIGOUT1 - * 0b110110..DMA0_TRIGOUT2 - */ -#define INPUTMUX_ENC0_PHASEA_ENC0_PHASEA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_PHASEA_ENC0_PHASEA_SHIFT)) & INPUTMUX_ENC0_PHASEA_ENC0_PHASEA_MASK) -/*! @} */ - -/*! @name ENC1_TRIG - ENC1 Trigger Input Connections */ -/*! @{ */ - -#define INPUTMUX_ENC1_TRIG_TRIGIN_MASK (0x3FU) -#define INPUTMUX_ENC1_TRIG_TRIGIN_SHIFT (0U) -/*! TRIGIN - ENC1 input trigger - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT5 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT7 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T1_MAT1 - * 0b001001..T3_MAT1 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM1_SM0_MUX_TRIG0 - * 0b011001..PWM1_SM0_MUX_TRIG1 - * 0b011010..PWM1_SM1_MUX_TRIG0 - * 0b011011..PWM1_SM1_MUX_TRIG1 - * 0b011100..PWM1_SM2_MUX_TRIG0 - * 0b011101..PWM1_SM2_MUX_TRIG1 - * 0b011110..PWM1_SM3_MUX_TRIG0 - * 0b011111..PWM1_SM3_MUX_TRIG1 - * 0b100000..ENC0_CMP/POS_MATCH - * 0b100001..ENC1_CMP/POS_MATCH - * 0b100010..AOI0_OUT0 - * 0b100011..AOI0_OUT1 - * 0b100100..AOI0_OUT2 - * 0b100101..AOI0_OUT3 - * 0b100110..AOI1_OUT0 - * 0b100111..AOI1_OUT1 - * 0b101000..AOI1_OUT2 - * 0b101001..AOI1_OUT3 - * 0b101010..EXTTRIG_IN0 - * 0b101011..EXTTRIG_IN1 - * 0b101100..EXTTRIG_IN2 - * 0b101101..EXTTRIG_IN3 - * 0b101110..EXTTRIG_IN4 - * 0b101111..EXTTRIG_IN5 - * 0b110000..EXTTRIG_IN6 - * 0b110001..EXTTRIG_IN7 - * 0b110010..EXTTRIG_IN8 - * 0b110011..EXTTRIG_IN9 - * 0b110100..DMA0_TRIGOUT0 - * 0b110101..DMA0_TRIGOUT1 - * 0b110110..DMA0_TRIGOUT2 - */ -#define INPUTMUX_ENC1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ENC1_TRIG_TRIGIN_MASK) -/*! @} */ - -/*! @name ENC1_HOME - ENC1 Input Connections */ -/*! @{ */ - -#define INPUTMUX_ENC1_HOME_ENC1_HOME_MASK (0x3FU) -#define INPUTMUX_ENC1_HOME_ENC1_HOME_SHIFT (0U) -/*! ENC1_HOME - ENC1 input trigger - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT5 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT7 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T1_MAT1 - * 0b001001..T3_MAT1 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM1_SM0_MUX_TRIG0 - * 0b011001..PWM1_SM0_MUX_TRIG1 - * 0b011010..PWM1_SM1_MUX_TRIG0 - * 0b011011..PWM1_SM1_MUX_TRIG1 - * 0b011100..PWM1_SM2_MUX_TRIG0 - * 0b011101..PWM1_SM2_MUX_TRIG1 - * 0b011110..PWM1_SM3_MUX_TRIG0 - * 0b011111..PWM1_SM3_MUX_TRIG1 - * 0b100000..ENC0_CMP/POS_MATCH - * 0b100001..ENC1_CMP/POS_MATCH - * 0b100010..AOI0_OUT0 - * 0b100011..AOI0_OUT1 - * 0b100100..AOI0_OUT2 - * 0b100101..AOI0_OUT3 - * 0b100110..AOI1_OUT0 - * 0b100111..AOI1_OUT1 - * 0b101000..AOI1_OUT2 - * 0b101001..AOI1_OUT3 - * 0b101010..EXTTRIG_IN0 - * 0b101011..EXTTRIG_IN1 - * 0b101100..EXTTRIG_IN2 - * 0b101101..EXTTRIG_IN3 - * 0b101110..EXTTRIG_IN4 - * 0b101111..EXTTRIG_IN5 - * 0b110000..EXTTRIG_IN6 - * 0b110001..EXTTRIG_IN7 - * 0b110010..EXTTRIG_IN8 - * 0b110011..EXTTRIG_IN9 - * 0b110100..DMA0_TRIGOUT0 - * 0b110101..DMA0_TRIGOUT1 - * 0b110110..DMA0_TRIGOUT2 - */ -#define INPUTMUX_ENC1_HOME_ENC1_HOME(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_HOME_ENC1_HOME_SHIFT)) & INPUTMUX_ENC1_HOME_ENC1_HOME_MASK) -/*! @} */ - -/*! @name ENC1_INDEX - ENC1 Input Connections */ -/*! @{ */ - -#define INPUTMUX_ENC1_INDEX_ENC1_INDEX_MASK (0x3FU) -#define INPUTMUX_ENC1_INDEX_ENC1_INDEX_SHIFT (0U) -/*! ENC1_INDEX - ENC1 input trigger - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT5 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT7 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T1_MAT1 - * 0b001001..T3_MAT1 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM1_SM0_MUX_TRIG0 - * 0b011001..PWM1_SM0_MUX_TRIG1 - * 0b011010..PWM1_SM1_MUX_TRIG0 - * 0b011011..PWM1_SM1_MUX_TRIG1 - * 0b011100..PWM1_SM2_MUX_TRIG0 - * 0b011101..PWM1_SM2_MUX_TRIG1 - * 0b011110..PWM1_SM3_MUX_TRIG0 - * 0b011111..PWM1_SM3_MUX_TRIG1 - * 0b100000..ENC0_CMP/POS_MATCH - * 0b100001..ENC1_CMP/POS_MATCH - * 0b100010..AOI0_OUT0 - * 0b100011..AOI0_OUT1 - * 0b100100..AOI0_OUT2 - * 0b100101..AOI0_OUT3 - * 0b100110..AOI1_OUT0 - * 0b100111..AOI1_OUT1 - * 0b101000..AOI1_OUT2 - * 0b101001..AOI1_OUT3 - * 0b101010..EXTTRIG_IN0 - * 0b101011..EXTTRIG_IN1 - * 0b101100..EXTTRIG_IN2 - * 0b101101..EXTTRIG_IN3 - * 0b101110..EXTTRIG_IN4 - * 0b101111..EXTTRIG_IN5 - * 0b110000..EXTTRIG_IN6 - * 0b110001..EXTTRIG_IN7 - * 0b110010..EXTTRIG_IN8 - * 0b110011..EXTTRIG_IN9 - * 0b110100..DMA0_TRIGOUT0 - * 0b110101..DMA0_TRIGOUT1 - * 0b110110..DMA0_TRIGOUT2 - */ -#define INPUTMUX_ENC1_INDEX_ENC1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_INDEX_ENC1_INDEX_SHIFT)) & INPUTMUX_ENC1_INDEX_ENC1_INDEX_MASK) -/*! @} */ - -/*! @name ENC1_PHASEB - ENC1 Input Connections */ -/*! @{ */ - -#define INPUTMUX_ENC1_PHASEB_ENC1_PHASEB_MASK (0x3FU) -#define INPUTMUX_ENC1_PHASEB_ENC1_PHASEB_SHIFT (0U) -/*! ENC1_PHASEB - ENC1 input trigger - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT5 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT7 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T1_MAT1 - * 0b001001..T3_MAT1 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM1_SM0_MUX_TRIG0 - * 0b011001..PWM1_SM0_MUX_TRIG1 - * 0b011010..PWM1_SM1_MUX_TRIG0 - * 0b011011..PWM1_SM1_MUX_TRIG1 - * 0b011100..PWM1_SM2_MUX_TRIG0 - * 0b011101..PWM1_SM2_MUX_TRIG1 - * 0b011110..PWM1_SM3_MUX_TRIG0 - * 0b011111..PWM1_SM3_MUX_TRIG1 - * 0b100000..ENC0_CMP/POS_MATCH - * 0b100001..ENC1_CMP/POS_MATCH - * 0b100010..AOI0_OUT0 - * 0b100011..AOI0_OUT1 - * 0b100100..AOI0_OUT2 - * 0b100101..AOI0_OUT3 - * 0b100110..AOI1_OUT0 - * 0b100111..AOI1_OUT1 - * 0b101000..AOI1_OUT2 - * 0b101001..AOI1_OUT3 - * 0b101010..EXTTRIG_IN0 - * 0b101011..EXTTRIG_IN1 - * 0b101100..EXTTRIG_IN2 - * 0b101101..EXTTRIG_IN3 - * 0b101110..EXTTRIG_IN4 - * 0b101111..EXTTRIG_IN5 - * 0b110000..EXTTRIG_IN6 - * 0b110001..EXTTRIG_IN7 - * 0b110010..EXTTRIG_IN8 - * 0b110011..EXTTRIG_IN9 - * 0b110100..DMA0_TRIGOUT0 - * 0b110101..DMA0_TRIGOUT1 - * 0b110110..DMA0_TRIGOUT2 - */ -#define INPUTMUX_ENC1_PHASEB_ENC1_PHASEB(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_PHASEB_ENC1_PHASEB_SHIFT)) & INPUTMUX_ENC1_PHASEB_ENC1_PHASEB_MASK) -/*! @} */ - -/*! @name ENC1_PHASEA - ENC1 Input Connections */ -/*! @{ */ - -#define INPUTMUX_ENC1_PHASEA_ENC1_PHASEA_MASK (0x3FU) -#define INPUTMUX_ENC1_PHASEA_ENC1_PHASEA_SHIFT (0U) -/*! ENC1_PHASEA - ENC1 input trigger - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT5 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT7 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T1_MAT1 - * 0b001001..T3_MAT1 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM1_SM0_MUX_TRIG0 - * 0b011001..PWM1_SM0_MUX_TRIG1 - * 0b011010..PWM1_SM1_MUX_TRIG0 - * 0b011011..PWM1_SM1_MUX_TRIG1 - * 0b011100..PWM1_SM2_MUX_TRIG0 - * 0b011101..PWM1_SM2_MUX_TRIG1 - * 0b011110..PWM1_SM3_MUX_TRIG0 - * 0b011111..PWM1_SM3_MUX_TRIG1 - * 0b100000..ENC0_CMP/POS_MATCH - * 0b100001..ENC1_CMP/POS_MATCH - * 0b100010..AOI0_OUT0 - * 0b100011..AOI0_OUT1 - * 0b100100..AOI0_OUT2 - * 0b100101..AOI0_OUT3 - * 0b100110..AOI1_OUT0 - * 0b100111..AOI1_OUT1 - * 0b101000..AOI1_OUT2 - * 0b101001..AOI1_OUT3 - * 0b101010..EXTTRIG_IN0 - * 0b101011..EXTTRIG_IN1 - * 0b101100..EXTTRIG_IN2 - * 0b101101..EXTTRIG_IN3 - * 0b101110..EXTTRIG_IN4 - * 0b101111..EXTTRIG_IN5 - * 0b110000..EXTTRIG_IN6 - * 0b110001..EXTTRIG_IN7 - * 0b110010..EXTTRIG_IN8 - * 0b110011..EXTTRIG_IN9 - * 0b110100..DMA0_TRIGOUT0 - * 0b110101..DMA0_TRIGOUT1 - * 0b110110..DMA0_TRIGOUT2 - */ -#define INPUTMUX_ENC1_PHASEA_ENC1_PHASEA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_PHASEA_ENC1_PHASEA_SHIFT)) & INPUTMUX_ENC1_PHASEA_ENC1_PHASEA_MASK) -/*! @} */ - -/*! @name PWM0_EXTSYNCN_PWM0_EXTSYNC - PWM0 external synchronization */ -/*! @{ */ - -#define INPUTMUX_PWM0_EXTSYNCN_PWM0_EXTSYNC_TRIGIN_MASK (0x3FU) -#define INPUTMUX_PWM0_EXTSYNCN_PWM0_EXTSYNC_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM0 - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT5 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT2 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T2_MAT0 - * 0b001001..T4_MAT0 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM1_SM0_MUX_TRIG0 - * 0b011001..PWM1_SM0_MUX_TRIG1 - * 0b011010..PWM1_SM1_MUX_TRIG0 - * 0b011011..PWM1_SM1_MUX_TRIG1 - * 0b011100..PWM1_SM2_MUX_TRIG0 - * 0b011101..PWM1_SM2_MUX_TRIG1 - * 0b011110..PWM1_SM3_MUX_TRIG0 - * 0b011111..PWM1_SM3_MUX_TRIG1 - * 0b100000..ENC0_CMP/POS_MATCH - * 0b100001..ENC1_CMP/POS_MATCH - * 0b100010..AOI0_OUT0 - * 0b100011..AOI0_OUT1 - * 0b100100..AOI0_OUT2 - * 0b100101..AOI0_OUT3 - * 0b100110..AOI1_OUT0 - * 0b100111..AOI1_OUT1 - * 0b101000..AOI1_OUT2 - * 0b101001..AOI1_OUT3 - * 0b101010..EXTTRIG_IN0 - * 0b101011..EXTTRIG_IN1 - * 0b101100..EXTTRIG_IN2 - * 0b101101..EXTTRIG_IN3 - * 0b101110..EXTTRIG_IN4 - * 0b101111..EXTTRIG_IN5 - * 0b110000..EXTTRIG_IN6 - * 0b110001..EXTTRIG_IN7 - * 0b110010..EXTTRIG_IN8 - * 0b110011..EXTTRIG_IN9 - * 0b110100..DMA0_TRIGOUT0 - * 0b110101..DMA0_TRIGOUT1 - * 0b110110..DMA0_TRIGOUT2 - */ -#define INPUTMUX_PWM0_EXTSYNCN_PWM0_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXTSYNCN_PWM0_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXTSYNCN_PWM0_EXTSYNC_TRIGIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PWM0_EXTSYNCN_PWM0_EXTSYNC */ -#define INPUTMUX_PWM0_EXTSYNCN_PWM0_EXTSYNC_COUNT (4U) - -/*! @name PWM0_EXTAN_PWM0_EXTA - PWM0 input trigger connections */ -/*! @{ */ - -#define INPUTMUX_PWM0_EXTAN_PWM0_EXTA_TRIGIN_MASK (0x3FU) -#define INPUTMUX_PWM0_EXTAN_PWM0_EXTA_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM0 - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT5 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT2 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T2_MAT0 - * 0b001001..T4_MAT0 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM1_SM0_MUX_TRIG0 - * 0b011001..PWM1_SM0_MUX_TRIG1 - * 0b011010..PWM1_SM1_MUX_TRIG0 - * 0b011011..PWM1_SM1_MUX_TRIG1 - * 0b011100..PWM1_SM2_MUX_TRIG0 - * 0b011101..PWM1_SM2_MUX_TRIG1 - * 0b011110..PWM1_SM3_MUX_TRIG0 - * 0b011111..PWM1_SM3_MUX_TRIG1 - * 0b100000..ENC0_CMP/POS_MATCH - * 0b100001..ENC1_CMP/POS_MATCH - * 0b100010..AOI0_OUT0 - * 0b100011..AOI0_OUT1 - * 0b100100..AOI0_OUT2 - * 0b100101..AOI0_OUT3 - * 0b100110..AOI1_OUT0 - * 0b100111..AOI1_OUT1 - * 0b101000..AOI1_OUT2 - * 0b101001..AOI1_OUT3 - * 0b101010..EXTTRIG_IN0 - * 0b101011..EXTTRIG_IN1 - * 0b101100..EXTTRIG_IN2 - * 0b101101..EXTTRIG_IN3 - * 0b101110..EXTTRIG_IN4 - * 0b101111..EXTTRIG_IN5 - * 0b110000..EXTTRIG_IN6 - * 0b110001..EXTTRIG_IN7 - * 0b110010..EXTTRIG_IN8 - * 0b110011..EXTTRIG_IN9 - * 0b110100..DMA0_TRIGOUT0 - * 0b110101..DMA0_TRIGOUT1 - * 0b110110..DMA0_TRIGOUT2 - */ -#define INPUTMUX_PWM0_EXTAN_PWM0_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXTAN_PWM0_EXTA_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXTAN_PWM0_EXTA_TRIGIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PWM0_EXTAN_PWM0_EXTA */ -#define INPUTMUX_PWM0_EXTAN_PWM0_EXTA_COUNT (4U) - -/*! @name PWM0_EXTFORCE - PWM0 external force trigger connections */ -/*! @{ */ - -#define INPUTMUX_PWM0_EXTFORCE_TRIGIN_MASK (0x3FU) -#define INPUTMUX_PWM0_EXTFORCE_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM0 - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT5 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT2 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T2_MAT0 - * 0b001001..T4_MAT0 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM1_SM0_MUX_TRIG0 - * 0b011001..PWM1_SM0_MUX_TRIG1 - * 0b011010..PWM1_SM1_MUX_TRIG0 - * 0b011011..PWM1_SM1_MUX_TRIG1 - * 0b011100..PWM1_SM2_MUX_TRIG0 - * 0b011101..PWM1_SM2_MUX_TRIG1 - * 0b011110..PWM1_SM3_MUX_TRIG0 - * 0b011111..PWM1_SM3_MUX_TRIG1 - * 0b100000..ENC0_CMP/POS_MATCH - * 0b100001..ENC1_CMP/POS_MATCH - * 0b100010..AOI0_OUT0 - * 0b100011..AOI0_OUT1 - * 0b100100..AOI0_OUT2 - * 0b100101..AOI0_OUT3 - * 0b100110..AOI1_OUT0 - * 0b100111..AOI1_OUT1 - * 0b101000..AOI1_OUT2 - * 0b101001..AOI1_OUT3 - * 0b101010..EXTTRIG_IN0 - * 0b101011..EXTTRIG_IN1 - * 0b101100..EXTTRIG_IN2 - * 0b101101..EXTTRIG_IN3 - * 0b101110..EXTTRIG_IN4 - * 0b101111..EXTTRIG_IN5 - * 0b110000..EXTTRIG_IN6 - * 0b110001..EXTTRIG_IN7 - * 0b110010..EXTTRIG_IN8 - * 0b110011..EXTTRIG_IN9 - * 0b110100..DMA0_TRIGOUT0 - * 0b110101..DMA0_TRIGOUT1 - * 0b110110..DMA0_TRIGOUT2 - */ -#define INPUTMUX_PWM0_EXTFORCE_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXTFORCE_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXTFORCE_TRIGIN_MASK) -/*! @} */ - -/*! @name PWM0_FAULTN_PWM0_FAULT - PWM0 fault input trigger connections */ -/*! @{ */ - -#define INPUTMUX_PWM0_FAULTN_PWM0_FAULT_TRIGIN_MASK (0x3FU) -#define INPUTMUX_PWM0_FAULTN_PWM0_FAULT_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM0 - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT5 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT2 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T2_MAT0 - * 0b001001..T4_MAT0 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM1_SM0_MUX_TRIG0 - * 0b011001..PWM1_SM0_MUX_TRIG1 - * 0b011010..PWM1_SM1_MUX_TRIG0 - * 0b011011..PWM1_SM1_MUX_TRIG1 - * 0b011100..PWM1_SM2_MUX_TRIG0 - * 0b011101..PWM1_SM2_MUX_TRIG1 - * 0b011110..PWM1_SM3_MUX_TRIG0 - * 0b011111..PWM1_SM3_MUX_TRIG1 - * 0b100000..ENC0_CMP/POS_MATCH - * 0b100001..ENC1_CMP/POS_MATCH - * 0b100010..AOI0_OUT0 - * 0b100011..AOI0_OUT1 - * 0b100100..AOI0_OUT2 - * 0b100101..AOI0_OUT3 - * 0b100110..AOI1_OUT0 - * 0b100111..AOI1_OUT1 - * 0b101000..AOI1_OUT2 - * 0b101001..AOI1_OUT3 - * 0b101010..EXTTRIG_IN0 - * 0b101011..EXTTRIG_IN1 - * 0b101100..EXTTRIG_IN2 - * 0b101101..EXTTRIG_IN3 - * 0b101110..EXTTRIG_IN4 - * 0b101111..EXTTRIG_IN5 - * 0b110000..EXTTRIG_IN6 - * 0b110001..EXTTRIG_IN7 - * 0b110010..EXTTRIG_IN8 - * 0b110011..EXTTRIG_IN9 - * 0b110100..DMA0_TRIGOUT0 - * 0b110101..DMA0_TRIGOUT1 - * 0b110110..DMA0_TRIGOUT2 - */ -#define INPUTMUX_PWM0_FAULTN_PWM0_FAULT_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_FAULTN_PWM0_FAULT_TRIGIN_SHIFT)) & INPUTMUX_PWM0_FAULTN_PWM0_FAULT_TRIGIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PWM0_FAULTN_PWM0_FAULT */ -#define INPUTMUX_PWM0_FAULTN_PWM0_FAULT_COUNT (4U) - -/*! @name PWM1_EXTSYNCN_PWM1_EXTSYNC - PWM1 external synchronization */ -/*! @{ */ - -#define INPUTMUX_PWM1_EXTSYNCN_PWM1_EXTSYNC_TRIGIN_MASK (0x3FU) -#define INPUTMUX_PWM1_EXTSYNCN_PWM1_EXTSYNC_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM1 - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT2 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT3 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T2_MAT1 - * 0b001001..T4_MAT1 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM0_SM0_MUX_TRIG0 - * 0b011001..PWM0_SM0_MUX_TRIG1 - * 0b011010..PWM0_SM1_MUX_TRIG0 - * 0b011011..PWM0_SM1_MUX_TRIG1 - * 0b011100..PWM0_SM2_MUX_TRIG0 - * 0b011101..PWM0_SM2_MUX_TRIG1 - * 0b011110..PWM0_SM3_MUX_TRIG0 - * 0b011111..PWM0_SM3_MUX_TRIG1 - * 0b100000..ENC0_CMP/POS_MATCH - * 0b100001..ENC1_CMP/POS_MATCH - * 0b100010..AOI0_OUT0 - * 0b100011..AOI0_OUT1 - * 0b100100..AOI0_OUT2 - * 0b100101..AOI0_OUT3 - * 0b100110..AOI1_OUT0 - * 0b100111..AOI1_OUT1 - * 0b101000..AOI1_OUT2 - * 0b101001..AOI1_OUT3 - * 0b101010..EXTTRIG_IN0 - * 0b101011..EXTTRIG_IN1 - * 0b101100..EXTTRIG_IN2 - * 0b101101..EXTTRIG_IN3 - * 0b101110..EXTTRIG_IN4 - * 0b101111..EXTTRIG_IN5 - * 0b110000..EXTTRIG_IN6 - * 0b110001..EXTTRIG_IN7 - * 0b110010..EXTTRIG_IN8 - * 0b110011..EXTTRIG_IN9 - * 0b110100..DMA0_TRIGOUT0 - * 0b110101..DMA0_TRIGOUT1 - * 0b110110..DMA0_TRIGOUT2 - */ -#define INPUTMUX_PWM1_EXTSYNCN_PWM1_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXTSYNCN_PWM1_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXTSYNCN_PWM1_EXTSYNC_TRIGIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PWM1_EXTSYNCN_PWM1_EXTSYNC */ -#define INPUTMUX_PWM1_EXTSYNCN_PWM1_EXTSYNC_COUNT (4U) - -/*! @name PWM1_EXTAN_PWM1_EXTA - PWM1 input trigger connections */ -/*! @{ */ - -#define INPUTMUX_PWM1_EXTAN_PWM1_EXTA_TRIGIN_MASK (0x3FU) -#define INPUTMUX_PWM1_EXTAN_PWM1_EXTA_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM1 - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT2 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT3 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T2_MAT1 - * 0b001001..T4_MAT1 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM0_SM0_MUX_TRIG0 - * 0b011001..PWM0_SM0_MUX_TRIG1 - * 0b011010..PWM0_SM1_MUX_TRIG0 - * 0b011011..PWM0_SM1_MUX_TRIG1 - * 0b011100..PWM0_SM2_MUX_TRIG0 - * 0b011101..PWM0_SM2_MUX_TRIG1 - * 0b011110..PWM0_SM3_MUX_TRIG0 - * 0b011111..PWM0_SM3_MUX_TRIG1 - * 0b100000..ENC0_CMP/POS_MATCH - * 0b100001..ENC1_CMP/POS_MATCH - * 0b100010..AOI0_OUT0 - * 0b100011..AOI0_OUT1 - * 0b100100..AOI0_OUT2 - * 0b100101..AOI0_OUT3 - * 0b100110..AOI1_OUT0 - * 0b100111..AOI1_OUT1 - * 0b101000..AOI1_OUT2 - * 0b101001..AOI1_OUT3 - * 0b101010..EXTTRIG_IN0 - * 0b101011..EXTTRIG_IN1 - * 0b101100..EXTTRIG_IN2 - * 0b101101..EXTTRIG_IN3 - * 0b101110..EXTTRIG_IN4 - * 0b101111..EXTTRIG_IN5 - * 0b110000..EXTTRIG_IN6 - * 0b110001..EXTTRIG_IN7 - * 0b110010..EXTTRIG_IN8 - * 0b110011..EXTTRIG_IN9 - * 0b110100..DMA0_TRIGOUT0 - * 0b110101..DMA0_TRIGOUT1 - * 0b110110..DMA0_TRIGOUT2 - */ -#define INPUTMUX_PWM1_EXTAN_PWM1_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXTAN_PWM1_EXTA_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXTAN_PWM1_EXTA_TRIGIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PWM1_EXTAN_PWM1_EXTA */ -#define INPUTMUX_PWM1_EXTAN_PWM1_EXTA_COUNT (4U) - -/*! @name PWM1_EXTFORCE - PWM1 external force trigger connections */ -/*! @{ */ - -#define INPUTMUX_PWM1_EXTFORCE_TRIGIN_MASK (0x3FU) -#define INPUTMUX_PWM1_EXTFORCE_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM1 - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT2 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT3 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T2_MAT1 - * 0b001001..T4_MAT1 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM0_SM0_MUX_TRIG0 - * 0b011001..PWM0_SM0_MUX_TRIG1 - * 0b011010..PWM0_SM1_MUX_TRIG0 - * 0b011011..PWM0_SM1_MUX_TRIG1 - * 0b011100..PWM0_SM2_MUX_TRIG0 - * 0b011101..PWM0_SM2_MUX_TRIG1 - * 0b011110..PWM0_SM3_MUX_TRIG0 - * 0b011111..PWM0_SM3_MUX_TRIG1 - * 0b100000..ENC0_CMP/POS_MATCH - * 0b100001..ENC1_CMP/POS_MATCH - * 0b100010..AOI0_OUT0 - * 0b100011..AOI0_OUT1 - * 0b100100..AOI0_OUT2 - * 0b100101..AOI0_OUT3 - * 0b100110..AOI1_OUT0 - * 0b100111..AOI1_OUT1 - * 0b101000..AOI1_OUT2 - * 0b101001..AOI1_OUT3 - * 0b101010..EXTTRIG_IN0 - * 0b101011..EXTTRIG_IN1 - * 0b101100..EXTTRIG_IN2 - * 0b101101..EXTTRIG_IN3 - * 0b101110..EXTTRIG_IN4 - * 0b101111..EXTTRIG_IN5 - * 0b110000..EXTTRIG_IN6 - * 0b110001..EXTTRIG_IN7 - * 0b110010..EXTTRIG_IN8 - * 0b110011..EXTTRIG_IN9 - * 0b110100..DMA0_TRIGOUT0 - * 0b110101..DMA0_TRIGOUT1 - * 0b110110..DMA0_TRIGOUT2 - */ -#define INPUTMUX_PWM1_EXTFORCE_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXTFORCE_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXTFORCE_TRIGIN_MASK) -/*! @} */ - -/*! @name PWM1_FAULTN_PWM1_FAULT - PWM1 fault input trigger connections */ -/*! @{ */ - -#define INPUTMUX_PWM1_FAULTN_PWM1_FAULT_TRIGIN_MASK (0x3FU) -#define INPUTMUX_PWM1_FAULTN_PWM1_FAULT_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM1 - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT2 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT3 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T2_MAT1 - * 0b001001..T4_MAT1 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM0_SM0_MUX_TRIG0 - * 0b011001..PWM0_SM0_MUX_TRIG1 - * 0b011010..PWM0_SM1_MUX_TRIG0 - * 0b011011..PWM0_SM1_MUX_TRIG1 - * 0b011100..PWM0_SM2_MUX_TRIG0 - * 0b011101..PWM0_SM2_MUX_TRIG1 - * 0b011110..PWM0_SM3_MUX_TRIG0 - * 0b011111..PWM0_SM3_MUX_TRIG1 - * 0b100000..ENC0_CMP/POS_MATCH - * 0b100001..ENC1_CMP/POS_MATCH - * 0b100010..AOI0_OUT0 - * 0b100011..AOI0_OUT1 - * 0b100100..AOI0_OUT2 - * 0b100101..AOI0_OUT3 - * 0b100110..AOI1_OUT0 - * 0b100111..AOI1_OUT1 - * 0b101000..AOI1_OUT2 - * 0b101001..AOI1_OUT3 - * 0b101010..EXTTRIG_IN0 - * 0b101011..EXTTRIG_IN1 - * 0b101100..EXTTRIG_IN2 - * 0b101101..EXTTRIG_IN3 - * 0b101110..EXTTRIG_IN4 - * 0b101111..EXTTRIG_IN5 - * 0b110000..EXTTRIG_IN6 - * 0b110001..EXTTRIG_IN7 - * 0b110010..EXTTRIG_IN8 - * 0b110011..EXTTRIG_IN9 - * 0b110100..DMA0_TRIGOUT0 - * 0b110101..DMA0_TRIGOUT1 - * 0b110110..DMA0_TRIGOUT2 - */ -#define INPUTMUX_PWM1_FAULTN_PWM1_FAULT_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_FAULTN_PWM1_FAULT_TRIGIN_SHIFT)) & INPUTMUX_PWM1_FAULTN_PWM1_FAULT_TRIGIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PWM1_FAULTN_PWM1_FAULT */ -#define INPUTMUX_PWM1_FAULTN_PWM1_FAULT_COUNT (4U) - -/*! @name PWM0_EXTCLK - PWM0 external clock trigger connections */ -/*! @{ */ - -#define INPUTMUX_PWM0_EXTCLK_TRIGIN_MASK (0x3FU) -#define INPUTMUX_PWM0_EXTCLK_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM0 - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT5 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT2 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T2_MAT0 - * 0b001001..T4_MAT0 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM1_SM0_MUX_TRIG0 - * 0b011001..PWM1_SM0_MUX_TRIG1 - * 0b011010..PWM1_SM1_MUX_TRIG0 - * 0b011011..PWM1_SM1_MUX_TRIG1 - * 0b011100..PWM1_SM2_MUX_TRIG0 - * 0b011101..PWM1_SM2_MUX_TRIG1 - * 0b011110..PWM1_SM3_MUX_TRIG0 - * 0b011111..PWM1_SM3_MUX_TRIG1 - * 0b100000..ENC0_CMP/POS_MATCH - * 0b100001..ENC1_CMP/POS_MATCH - * 0b100010..AOI0_OUT0 - * 0b100011..AOI0_OUT1 - * 0b100100..AOI0_OUT2 - * 0b100101..AOI0_OUT3 - * 0b100110..AOI1_OUT0 - * 0b100111..AOI1_OUT1 - * 0b101000..AOI1_OUT2 - * 0b101001..AOI1_OUT3 - * 0b101010..EXTTRIG_IN0 - * 0b101011..EXTTRIG_IN1 - * 0b101100..EXTTRIG_IN2 - * 0b101101..EXTTRIG_IN3 - * 0b101110..EXTTRIG_IN4 - * 0b101111..EXTTRIG_IN5 - * 0b110000..EXTTRIG_IN6 - * 0b110001..EXTTRIG_IN7 - * 0b110010..EXTTRIG_IN8 - * 0b110011..EXTTRIG_IN9 - * 0b110100..DMA0_TRIGOUT0 - * 0b110101..DMA0_TRIGOUT1 - * 0b110110..DMA0_TRIGOUT2 - */ -#define INPUTMUX_PWM0_EXTCLK_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXTCLK_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXTCLK_TRIGIN_MASK) -/*! @} */ - -/*! @name PWM1_EXTCLK - PWM1 external clock trigger connections */ -/*! @{ */ - -#define INPUTMUX_PWM1_EXTCLK_TRIGIN_MASK (0x3FU) -#define INPUTMUX_PWM1_EXTCLK_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM1 - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT2 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT3 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T2_MAT1 - * 0b001001..T4_MAT1 - * 0b001010..ACMP0_OUT - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[0] - * 0b001110..ADC0_tcomp[1] - * 0b001111..ADC0_tcomp[2] - * 0b010000..ADC0_tcomp[3] - * 0b010001..ADC1_tcomp[0] - * 0b010010..ADC1_tcomp[1] - * 0b010011..ADC1_tcomp[2] - * 0b010100..ADC1_tcomp[3] - * 0b010101..HSCMP0_OUT - * 0b010110..HSCMP1_OUT - * 0b010111..HSCMP2_OUT - * 0b011000..PWM0_SM0_MUX_TRIG0 - * 0b011001..PWM0_SM0_MUX_TRIG1 - * 0b011010..PWM0_SM1_MUX_TRIG0 - * 0b011011..PWM0_SM1_MUX_TRIG1 - * 0b011100..PWM0_SM2_MUX_TRIG0 - * 0b011101..PWM0_SM2_MUX_TRIG1 - * 0b011110..PWM0_SM3_MUX_TRIG0 - * 0b011111..PWM0_SM3_MUX_TRIG1 - * 0b100000..ENC0_CMP/POS_MATCH - * 0b100001..ENC1_CMP/POS_MATCH - * 0b100010..AOI0_OUT0 - * 0b100011..AOI0_OUT1 - * 0b100100..AOI0_OUT2 - * 0b100101..AOI0_OUT3 - * 0b100110..AOI1_OUT0 - * 0b100111..AOI1_OUT1 - * 0b101000..AOI1_OUT2 - * 0b101001..AOI1_OUT3 - * 0b101010..EXTTRIG_IN0 - * 0b101011..EXTTRIG_IN1 - * 0b101100..EXTTRIG_IN2 - * 0b101101..EXTTRIG_IN3 - * 0b101110..EXTTRIG_IN4 - * 0b101111..EXTTRIG_IN5 - * 0b110000..EXTTRIG_IN6 - * 0b110001..EXTTRIG_IN7 - * 0b110010..EXTTRIG_IN8 - * 0b110011..EXTTRIG_IN9 - * 0b110100..DMA0_TRIGOUT0 - * 0b110101..DMA0_TRIGOUT1 - * 0b110110..DMA0_TRIGOUT2 - */ -#define INPUTMUX_PWM1_EXTCLK_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXTCLK_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXTCLK_TRIGIN_MASK) -/*! @} */ - -/*! @name AOI0_IN - AOI0 trigger inputs */ -/*! @{ */ - -#define INPUTMUX_AOI0_IN_IN_MASK (0x3FU) -#define INPUTMUX_AOI0_IN_IN_SHIFT (0U) -/*! IN - Input trigger assignments - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT1 - * 0b000010..SCT_OUT0 - * 0b000011..SCT_OUT1 - * 0b000100..SCT_OUT2 - * 0b000101..SCT_OUT3 - * 0b000110..T0_MAT3 - * 0b000111..T1_MAT3 - * 0b001000..T2_MAT3 - * 0b001001..T2_MAT2 - * 0b001010..T3_MAT2 - * 0b001011..T4_MAT2 - * 0b001100..ACMP0_OUT - * 0b001101..GPIOINT_BMATCH - * 0b001110..ADC0_IRQ - * 0b001111..ADC1_IRQ - * 0b010000..ADC0_tcomp[0] - * 0b010001..ADC0_tcomp[1] - * 0b010010..ADC0_tcomp[2] - * 0b010011..ADC0_tcomp[3] - * 0b010100..ADC1_tcomp[0] - * 0b010101..ADC1_tcomp[1] - * 0b010110..ADC1_tcomp[2] - * 0b010111..ADC1_tcomp[3] - * 0b011000..HSCMP0_OUT - * 0b011001..HSCMP1_OUT - * 0b011010..HSCMP2_OUT - * 0b011011..PWM0_SM0_MUX_TRIG0 - * 0b011100..PWM0_SM0_MUX_TRIG1 - * 0b011101..PWM0_SM1_MUX_TRIG0 - * 0b011110..PWM0_SM1_MUX_TRIG1 - * 0b011111..PWM0_SM2_MUX_TRIG0 - * 0b100000..PWM0_SM2_MUX_TRIG1 - * 0b100001..PWM0_SM3_MUX_TRIG0 - * 0b100010..PWM0_SM3_MUX_TRIG1 - * 0b100011..PWM1_SM0_MUX_TRIG0 - * 0b100100..PWM1_SM0_MUX_TRIG1 - * 0b100101..PWM1_SM1_MUX_TRIG0 - * 0b100110..PWM1_SM1_MUX_TRIG1 - * 0b100111..PWM1_SM2_MUX_TRIG0 - * 0b101000..PWM1_SM2_MUX_TRIG1 - * 0b101001..PWM1_SM3_MUX_TRIG0 - * 0b101010..PWM1_SM3_MUX_TRIG1 - * 0b101011..ENC0_CMP/POS_MATCH - * 0b101100..ENC1_CMP/POS_MATCH - * 0b101101..EXTTRIG_IN0 - * 0b101110..EXTTRIG_IN1 - * 0b101111..EXTTRIG_IN2 - * 0b110000..EXTTRIG_IN3 - * 0b110001..Reserved - * 0b110010..Reserved - * 0b110011..DMA0_TRIGOUT0 - * 0b110100..DMA0_TRIGOUT1 - * 0b110101..DMA0_TRIGOUT2 - * 0b110110..DMA0_TRIGOUT3 - * 0b110111..DMA0_TRIGOUT4 - * 0b111000..DMA0_TRIGOUT5 - * 0b111001..DMA0_TRIGOUT6 - * 0b111010..DMA1_TRIGOUT0 - * 0b111011..DMA1_TRIGOUT1 - * 0b111100..DMA1_TRIGOUT2 - */ -#define INPUTMUX_AOI0_IN_IN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AOI0_IN_IN_SHIFT)) & INPUTMUX_AOI0_IN_IN_MASK) -/*! @} */ - -/* The count of INPUTMUX_AOI0_IN */ -#define INPUTMUX_AOI0_INPUTTRIGGER0 (16U) - -/*! @name AOI1_IN - AOI1 trigger inputs */ -/*! @{ */ - -#define INPUTMUX_AOI1_IN_IN_MASK (0x3FU) -#define INPUTMUX_AOI1_IN_IN_SHIFT (0U) -/*! IN - Input trigger assignments - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT1 - * 0b000010..SCT_OUT0 - * 0b000011..SCT_OUT1 - * 0b000100..SCT_OUT2 - * 0b000101..SCT_OUT3 - * 0b000110..T0_MAT3 - * 0b000111..T1_MAT3 - * 0b001000..T2_MAT3 - * 0b001001..T2_MAT2 - * 0b001010..T3_MAT2 - * 0b001011..T4_MAT2 - * 0b001100..ACMP0_OUT - * 0b001101..GPIOINT_BMATCH - * 0b001110..ADC0_IRQ - * 0b001111..ADC1_IRQ - * 0b010000..ADC0_tcomp[0] - * 0b010001..ADC0_tcomp[1] - * 0b010010..ADC0_tcomp[2] - * 0b010011..ADC0_tcomp[3] - * 0b010100..ADC1_tcomp[0] - * 0b010101..ADC1_tcomp[1] - * 0b010110..ADC1_tcomp[2] - * 0b010111..ADC1_tcomp[3] - * 0b011000..HSCMP0_OUT - * 0b011001..HSCMP1_OUT - * 0b011010..HSCMP2_OUT - * 0b011011..PWM0_SM0_MUX_TRIG0 - * 0b011100..PWM0_SM0_MUX_TRIG1 - * 0b011101..PWM0_SM1_MUX_TRIG0 - * 0b011110..PWM0_SM1_MUX_TRIG1 - * 0b011111..PWM0_SM2_MUX_TRIG0 - * 0b100000..PWM0_SM2_MUX_TRIG1 - * 0b100001..PWM0_SM3_MUX_TRIG0 - * 0b100010..PWM0_SM3_MUX_TRIG1 - * 0b100011..PWM1_SM0_MUX_TRIG0 - * 0b100100..PWM1_SM0_MUX_TRIG1 - * 0b100101..PWM1_SM1_MUX_TRIG0 - * 0b100110..PWM1_SM1_MUX_TRIG1 - * 0b100111..PWM1_SM2_MUX_TRIG0 - * 0b101000..PWM1_SM2_MUX_TRIG1 - * 0b101001..PWM1_SM3_MUX_TRIG0 - * 0b101010..PWM1_SM3_MUX_TRIG1 - * 0b101011..ENC0_CMP/POS_MATCH - * 0b101100..ENC1_CMP/POS_MATCH - * 0b101101..EXTTRIG_IN0 - * 0b101110..EXTTRIG_IN1 - * 0b101111..EXTTRIG_IN2 - * 0b110000..EXTTRIG_IN3 - * 0b110001..Reserved - * 0b110010..Reserved - * 0b110011..DMA0_TRIGOUT0 - * 0b110100..DMA0_TRIGOUT1 - * 0b110101..DMA0_TRIGOUT2 - * 0b110110..DMA0_TRIGOUT3 - * 0b110111..DMA0_TRIGOUT4 - * 0b111000..DMA0_TRIGOUT5 - * 0b111001..DMA0_TRIGOUT6 - * 0b111010..DMA1_TRIGOUT0 - * 0b111011..DMA1_TRIGOUT1 - * 0b111100..DMA1_TRIGOUT2 - */ -#define INPUTMUX_AOI1_IN_IN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AOI1_IN_IN_SHIFT)) & INPUTMUX_AOI1_IN_IN_MASK) -/*! @} */ - -/* The count of INPUTMUX_AOI1_IN */ -#define INPUTMUX_AOI1_INPUTTRIGGER0 (16U) - -/*! @name AOIX_EXT_TRIGN_AOI_EXT_TRIG - AOI External Trigger Inputs */ -/*! @{ */ - -#define INPUTMUX_AOIX_EXT_TRIGN_AOI_EXT_TRIG_TRIGIN_MASK (0x1FU) -#define INPUTMUX_AOIX_EXT_TRIGN_AOI_EXT_TRIG_TRIGIN_SHIFT (0U) -/*! TRIGIN - AOI external trigger inputs from 0 to 4. - * 0b00000..PIN_INT0 - * 0b00001..PIN_INT1 - * 0b00010..ADC0_IRQ - * 0b00011..ADC1_IRQ - * 0b00100..ADC0_tcomp[0] - * 0b00101..ADC1_tcomp[0] - * 0b00110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 - * 0b00111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 - * 0b01000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 - * 0b01001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 - * 0b01010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 - * 0b01011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 - * 0b01100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 - * 0b01101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 - * 0b01110..ENC0_CMP/POS_MATCH - * 0b01111..ENC1_CMP/POS_MATCH - * 0b10000..AOI0_OUT0 - * 0b10001..AOI0_OUT1 - * 0b10010..AOI0_OUT2 - * 0b10011..AOI0_OUT3 - * 0b10100..AOI1_OUT0 - * 0b10101..AOI1_OUT1 - * 0b10110..AOI1_OUT2 - * 0b10111..AOI1_OUT3 - * 0b11000..TMPR_OUT - * 0b11001-0b11111..None - */ -#define INPUTMUX_AOIX_EXT_TRIGN_AOI_EXT_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AOIX_EXT_TRIGN_AOI_EXT_TRIG_TRIGIN_SHIFT)) & INPUTMUX_AOIX_EXT_TRIGN_AOI_EXT_TRIG_TRIGIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_AOIX_EXT_TRIGN_AOI_EXT_TRIG */ -#define INPUTMUX_AOIX_EXT_TRIGN_AOI_EXT_TRIG_COUNT (8U) - -/*! @name HSCMP1_TRIG - Input connections for HSCMP1 */ -/*! @{ */ - -#define INPUTMUX_HSCMP1_TRIG_TRIGIN_MASK (0x3FU) -#define INPUTMUX_HSCMP1_TRIG_TRIGIN_SHIFT (0U) -/*! TRIGIN - CMP1 input trigger - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT7 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT7 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T0_MAT1 - * 0b001001..T4_MAT1 - * 0b001010..Reserved - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[1] - * 0b001110..ADC1_tcomp[1] - * 0b001111..Reserved - * 0b010000..Reserved - * 0b010001..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 - * 0b010010..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 - * 0b010011..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 - * 0b010100..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 - * 0b010101..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 - * 0b010110..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 - * 0b010111..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 - * 0b011000..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 - * 0b011001..ENC0_CMP/POS_MATCH - * 0b011010..ENC1_CMP/POS_MATCH - * 0b011011..AOI0_OUT0 - * 0b011100..AOI0_OUT1 - * 0b011101..AOI0_OUT2 - * 0b011110..AOI0_OUT3 - * 0b011111..AOI1_OUT0 - * 0b100000..AOI1_OUT1 - * 0b100001..AOI1_OUT2 - * 0b100010..AOI1_OUT3 - * 0b100011..DMA0_TRIGOUT0 - * 0b100100..DMA0_TRIGOUT1 - * 0b100101..DMA0_TRIGOUT2 - */ -#define INPUTMUX_HSCMP1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_HSCMP1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_HSCMP1_TRIG_TRIGIN_MASK) -/*! @} */ - -/*! @name HSCMP2_TRIG - Input connections for HSCMP2 */ -/*! @{ */ - -#define INPUTMUX_HSCMP2_TRIG_TRIGIN_MASK (0x3FU) -#define INPUTMUX_HSCMP2_TRIG_TRIGIN_SHIFT (0U) -/*! TRIGIN - CMP2 input trigger - * 0b000000..PIN_INT0 - * 0b000001..PIN_INT4 - * 0b000010..SCT_OUT4 - * 0b000011..SCT_OUT5 - * 0b000100..SCT_OUT8 - * 0b000101..T0_MAT3 - * 0b000110..T1_MAT3 - * 0b000111..T2_MAT3 - * 0b001000..T0_MAT2 - * 0b001001..T4_MAT2 - * 0b001010..Reserved - * 0b001011..ARM_TXEV - * 0b001100..GPIOINT_BMATCH - * 0b001101..ADC0_tcomp[2] - * 0b001110..ADC1_tcomp[2] - * 0b001111..Reserved - * 0b010000..Reserved - * 0b010001..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 - * 0b010010..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 - * 0b010011..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 - * 0b010100..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 - * 0b010101..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 - * 0b010110..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 - * 0b010111..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 - * 0b011000..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 - * 0b011001..ENC0_CMP/POS_MATCH - * 0b011010..ENC1_CMP/POS_MATCH - * 0b011011..AOI0_OUT0 - * 0b011100..AOI0_OUT1 - * 0b011101..AOI0_OUT2 - * 0b011110..AOI0_OUT3 - * 0b011111..AOI1_OUT0 - * 0b100000..AOI1_OUT1 - * 0b100001..AOI1_OUT2 - * 0b100010..AOI1_OUT3 - * 0b100011..DMA0_TRIGOUT0 - * 0b100100..DMA0_TRIGOUT1 - * 0b100101..DMA0_TRIGOUT2 - */ -#define INPUTMUX_HSCMP2_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_HSCMP2_TRIG_TRIGIN_SHIFT)) & INPUTMUX_HSCMP2_TRIG_TRIGIN_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_INMUX32 - Trigger select for DMA0 channel */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_INMUX32_INP_MASK (0x3FU) -#define INPUTMUX_DMA0_ITRIG_INMUX32_INP_SHIFT (0U) -/*! INP - Trigger input number (binary value) for DMA channel n (n = 32 to 51). - * 0b000000..FlexSPI_RX - * 0b000001..FlexSPI_TX - * 0b000010..GPIO_INT0 - * 0b000011..GPIO_INT1 - * 0b000100..GPIO_INT2 - * 0b000101..GPIO_INT3 - * 0b000110..T0_DMAREQ_M0 - * 0b000111..T0_DMAREQ_M1 - * 0b001000..T1_DMAREQ_M0 - * 0b001001..T1_DMAREQ_M1 - * 0b001010..T2_DMAREQ_M0 - * 0b001011..T2_DMAREQ_M1 - * 0b001100..T3_DMAREQ_M0 - * 0b001101..T3_DMAREQ_M1 - * 0b001110..T4_DMAREQ_M0 - * 0b001111..T4_DMAREQ_M1 - * 0b010000..ACMP0_OUT - * 0b010001..SDMA0_TRIGOUT_A - * 0b010010..SDMA0_TRIGOUT_B - * 0b010011..SDMA0_TRIGOUT_C - * 0b010100..SDMA0_TRIGOUT_D - * 0b010101..SCT_DMA0 - * 0b010110..SCT_DMA1 - * 0b010111..ADC0_tcomp[0] - * 0b011000..ADC1_tcomp[0] - * 0b011001..HSCMP0 - * 0b011010..HSCMP1 - * 0b011011..HSCMP2 - * 0b011100..AOI0_OUT0 - * 0b011101..AOI0_OUT1 - * 0b011110..AOI0_OUT2 - * 0b011111..AOI0_OUT3 - * 0b100000..AOI1_OUT0 - * 0b100001..AOI1_OUT1 - * 0b100010..AOI1_OUT2 - * 0b100011..AOI1_OUT3 - * 0b100100..FlexPWM0_req_capt0 - * 0b100101..FlexPWM0_req_capt1 - * 0b100110..FlexPWM0_req_capt2 - * 0b100111..FlexPWM0_req_capt3 - * 0b101000..FlexPWM0_req_val0 - * 0b101001..FlexPWM0_req_val1 - * 0b101010..FlexPWM0_req_val2 - * 0b101011..FlexPWM0_req_val3 - * 0b101100..FlexPWM1_req_capt0 - * 0b101101..FlexPWM1_req_capt1 - * 0b101110..FlexPWM1_req_capt2 - * 0b101111..FlexPWM1_req_capt3 - * 0b110000..FlexPWM1_req_val0 - * 0b110001..FlexPWM1_req_val1 - * 0b110010..FlexPWM1_req_val2 - * 0b110011..FlexPWM1_req_val3 - * 0b110100..TMPR_OUT - * 0b110110-0b111111..Reserved - */ -#define INPUTMUX_DMA0_ITRIG_INMUX32_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX32_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX32_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA0_ITRIG_INMUX32 */ -#define INPUTMUX_DMA0_ITRIG_INMUX32_COUNT (20U) - -/*! @name DMA0_REQEN0 - Enable DMA0 requests */ -/*! @{ */ - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA0_MASK (0x1U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA0_SHIFT (0U) -/*! REQ_ENA0 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA0_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA0_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA1_MASK (0x2U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA1_SHIFT (1U) -/*! REQ_ENA1 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA1_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA1_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA2_MASK (0x4U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA2_SHIFT (2U) -/*! REQ_ENA2 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA2_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA2_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA3_MASK (0x8U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA3_SHIFT (3U) -/*! REQ_ENA3 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA3_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA3_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA4_MASK (0x10U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA4_SHIFT (4U) -/*! REQ_ENA4 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA4_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA4_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA5_MASK (0x20U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA5_SHIFT (5U) -/*! REQ_ENA5 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA5_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA5_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA6_MASK (0x40U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA6_SHIFT (6U) -/*! REQ_ENA6 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA6_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA6_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA7_MASK (0x80U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA7_SHIFT (7U) -/*! REQ_ENA7 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA7_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA7_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA8_MASK (0x100U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA8_SHIFT (8U) -/*! REQ_ENA8 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA8_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA8_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA9_MASK (0x200U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA9_SHIFT (9U) -/*! REQ_ENA9 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA9_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA9_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA10_MASK (0x400U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA10_SHIFT (10U) -/*! REQ_ENA10 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA10_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA10_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA11_MASK (0x800U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA11_SHIFT (11U) -/*! REQ_ENA11 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA11_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA11_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA12_MASK (0x1000U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA12_SHIFT (12U) -/*! REQ_ENA12 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA12_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA12_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA13_MASK (0x2000U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA13_SHIFT (13U) -/*! REQ_ENA13 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA13_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA13_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA14_MASK (0x4000U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA14_SHIFT (14U) -/*! REQ_ENA14 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA14_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA14_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA15_MASK (0x8000U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA15_SHIFT (15U) -/*! REQ_ENA15 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA15_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA15_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA16_MASK (0x10000U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA16_SHIFT (16U) -/*! REQ_ENA16 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA16_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA16_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA17_MASK (0x20000U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA17_SHIFT (17U) -/*! REQ_ENA17 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA17_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA17_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA18_MASK (0x40000U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA18_SHIFT (18U) -/*! REQ_ENA18 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA18_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA18_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA19_MASK (0x80000U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA19_SHIFT (19U) -/*! REQ_ENA19 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA19_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA19_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA20_MASK (0x100000U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA20_SHIFT (20U) -/*! REQ_ENA20 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA20(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA20_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA20_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA21_MASK (0x200000U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA21_SHIFT (21U) -/*! REQ_ENA21 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA21(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA21_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA21_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA22_MASK (0x400000U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA22_SHIFT (22U) -/*! REQ_ENA22 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA22(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA22_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA22_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA23_MASK (0x800000U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA23_SHIFT (23U) -/*! REQ_ENA23 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA23(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA23_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA23_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA24_MASK (0x1000000U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA24_SHIFT (24U) -/*! REQ_ENA24 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA24(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA24_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA24_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA25_MASK (0x2000000U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA25_SHIFT (25U) -/*! REQ_ENA25 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA25(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA25_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA25_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA26_MASK (0x4000000U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA26_SHIFT (26U) -/*! REQ_ENA26 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA26(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA26_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA26_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA27_MASK (0x8000000U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA27_SHIFT (27U) -/*! REQ_ENA27 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA27(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA27_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA27_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA28_MASK (0x10000000U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA28_SHIFT (28U) -/*! REQ_ENA28 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA28(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA28_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA28_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA29_MASK (0x20000000U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA29_SHIFT (29U) -/*! REQ_ENA29 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA29(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA29_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA29_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA30_MASK (0x40000000U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA30_SHIFT (30U) -/*! REQ_ENA30 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA30(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA30_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA30_MASK) - -#define INPUTMUX_DMA0_REQEN0_REQ_ENA31_MASK (0x80000000U) -#define INPUTMUX_DMA0_REQEN0_REQ_ENA31_SHIFT (31U) -/*! REQ_ENA31 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQEN0_REQ_ENA31(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA31_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA31_MASK) -/*! @} */ - -/*! @name DMA0_REQEN1 - Enable DMA0 requests */ -/*! @{ */ - -#define INPUTMUX_DMA0_REQEN1_REQ_ENA0_MASK (0x1U) -#define INPUTMUX_DMA0_REQEN1_REQ_ENA0_SHIFT (0U) -/*! REQ_ENA0 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. - */ -#define INPUTMUX_DMA0_REQEN1_REQ_ENA0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA0_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA0_MASK) - -#define INPUTMUX_DMA0_REQEN1_REQ_ENA1_MASK (0x2U) -#define INPUTMUX_DMA0_REQEN1_REQ_ENA1_SHIFT (1U) -/*! REQ_ENA1 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. - */ -#define INPUTMUX_DMA0_REQEN1_REQ_ENA1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA1_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA1_MASK) - -#define INPUTMUX_DMA0_REQEN1_REQ_ENA2_MASK (0x4U) -#define INPUTMUX_DMA0_REQEN1_REQ_ENA2_SHIFT (2U) -/*! REQ_ENA2 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. - */ -#define INPUTMUX_DMA0_REQEN1_REQ_ENA2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA2_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA2_MASK) - -#define INPUTMUX_DMA0_REQEN1_REQ_ENA3_MASK (0x8U) -#define INPUTMUX_DMA0_REQEN1_REQ_ENA3_SHIFT (3U) -/*! REQ_ENA3 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. - */ -#define INPUTMUX_DMA0_REQEN1_REQ_ENA3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA3_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA3_MASK) - -#define INPUTMUX_DMA0_REQEN1_REQ_ENA4_MASK (0x10U) -#define INPUTMUX_DMA0_REQEN1_REQ_ENA4_SHIFT (4U) -/*! REQ_ENA4 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. - */ -#define INPUTMUX_DMA0_REQEN1_REQ_ENA4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA4_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA4_MASK) - -#define INPUTMUX_DMA0_REQEN1_REQ_ENA5_MASK (0x20U) -#define INPUTMUX_DMA0_REQEN1_REQ_ENA5_SHIFT (5U) -/*! REQ_ENA5 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. - */ -#define INPUTMUX_DMA0_REQEN1_REQ_ENA5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA5_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA5_MASK) - -#define INPUTMUX_DMA0_REQEN1_REQ_ENA6_MASK (0x40U) -#define INPUTMUX_DMA0_REQEN1_REQ_ENA6_SHIFT (6U) -/*! REQ_ENA6 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. - */ -#define INPUTMUX_DMA0_REQEN1_REQ_ENA6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA6_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA6_MASK) - -#define INPUTMUX_DMA0_REQEN1_REQ_ENA7_MASK (0x80U) -#define INPUTMUX_DMA0_REQEN1_REQ_ENA7_SHIFT (7U) -/*! REQ_ENA7 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. - */ -#define INPUTMUX_DMA0_REQEN1_REQ_ENA7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA7_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA7_MASK) - -#define INPUTMUX_DMA0_REQEN1_REQ_ENA8_MASK (0x100U) -#define INPUTMUX_DMA0_REQEN1_REQ_ENA8_SHIFT (8U) -/*! REQ_ENA8 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. - */ -#define INPUTMUX_DMA0_REQEN1_REQ_ENA8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA8_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA8_MASK) - -#define INPUTMUX_DMA0_REQEN1_REQ_ENA9_MASK (0x200U) -#define INPUTMUX_DMA0_REQEN1_REQ_ENA9_SHIFT (9U) -/*! REQ_ENA9 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. - */ -#define INPUTMUX_DMA0_REQEN1_REQ_ENA9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA9_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA9_MASK) - -#define INPUTMUX_DMA0_REQEN1_REQ_ENA10_MASK (0x400U) -#define INPUTMUX_DMA0_REQEN1_REQ_ENA10_SHIFT (10U) -/*! REQ_ENA10 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. - */ -#define INPUTMUX_DMA0_REQEN1_REQ_ENA10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA10_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA10_MASK) - -#define INPUTMUX_DMA0_REQEN1_REQ_ENA11_MASK (0x800U) -#define INPUTMUX_DMA0_REQEN1_REQ_ENA11_SHIFT (11U) -/*! REQ_ENA11 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. - */ -#define INPUTMUX_DMA0_REQEN1_REQ_ENA11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA11_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA11_MASK) - -#define INPUTMUX_DMA0_REQEN1_REQ_ENA12_MASK (0x1000U) -#define INPUTMUX_DMA0_REQEN1_REQ_ENA12_SHIFT (12U) -/*! REQ_ENA12 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. - */ -#define INPUTMUX_DMA0_REQEN1_REQ_ENA12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA12_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA12_MASK) - -#define INPUTMUX_DMA0_REQEN1_REQ_ENA13_MASK (0x2000U) -#define INPUTMUX_DMA0_REQEN1_REQ_ENA13_SHIFT (13U) -/*! REQ_ENA13 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. - */ -#define INPUTMUX_DMA0_REQEN1_REQ_ENA13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA13_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA13_MASK) - -#define INPUTMUX_DMA0_REQEN1_REQ_ENA14_MASK (0x4000U) -#define INPUTMUX_DMA0_REQEN1_REQ_ENA14_SHIFT (14U) -/*! REQ_ENA14 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. - */ -#define INPUTMUX_DMA0_REQEN1_REQ_ENA14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA14_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA14_MASK) - -#define INPUTMUX_DMA0_REQEN1_REQ_ENA15_MASK (0x8000U) -#define INPUTMUX_DMA0_REQEN1_REQ_ENA15_SHIFT (15U) -/*! REQ_ENA15 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. - */ -#define INPUTMUX_DMA0_REQEN1_REQ_ENA15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA15_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA15_MASK) - -#define INPUTMUX_DMA0_REQEN1_REQ_ENA16_MASK (0x10000U) -#define INPUTMUX_DMA0_REQEN1_REQ_ENA16_SHIFT (16U) -/*! REQ_ENA16 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. - */ -#define INPUTMUX_DMA0_REQEN1_REQ_ENA16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA16_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA16_MASK) - -#define INPUTMUX_DMA0_REQEN1_REQ_ENA17_MASK (0x20000U) -#define INPUTMUX_DMA0_REQEN1_REQ_ENA17_SHIFT (17U) -/*! REQ_ENA17 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. - */ -#define INPUTMUX_DMA0_REQEN1_REQ_ENA17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA17_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA17_MASK) - -#define INPUTMUX_DMA0_REQEN1_REQ_ENA18_MASK (0x40000U) -#define INPUTMUX_DMA0_REQEN1_REQ_ENA18_SHIFT (18U) -/*! REQ_ENA18 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. - */ -#define INPUTMUX_DMA0_REQEN1_REQ_ENA18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA18_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA18_MASK) - -#define INPUTMUX_DMA0_REQEN1_REQ_ENA19_MASK (0x80000U) -#define INPUTMUX_DMA0_REQEN1_REQ_ENA19_SHIFT (19U) -/*! REQ_ENA19 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. - */ -#define INPUTMUX_DMA0_REQEN1_REQ_ENA19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA19_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA19_MASK) -/*! @} */ - -/*! @name DMA0_REQEN0_SET - Set bits in DMA0_REQEN0 register */ -/*! @{ */ - -#define INPUTMUX_DMA0_REQEN0_SET_SET0_MASK (0x1U) -#define INPUTMUX_DMA0_REQEN0_SET_SET0_SHIFT (0U) -/*! SET0 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET0_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET0_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET1_MASK (0x2U) -#define INPUTMUX_DMA0_REQEN0_SET_SET1_SHIFT (1U) -/*! SET1 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET1_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET1_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET2_MASK (0x4U) -#define INPUTMUX_DMA0_REQEN0_SET_SET2_SHIFT (2U) -/*! SET2 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET2_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET2_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET3_MASK (0x8U) -#define INPUTMUX_DMA0_REQEN0_SET_SET3_SHIFT (3U) -/*! SET3 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET3_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET3_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET4_MASK (0x10U) -#define INPUTMUX_DMA0_REQEN0_SET_SET4_SHIFT (4U) -/*! SET4 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET4_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET4_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET5_MASK (0x20U) -#define INPUTMUX_DMA0_REQEN0_SET_SET5_SHIFT (5U) -/*! SET5 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET5_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET5_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET6_MASK (0x40U) -#define INPUTMUX_DMA0_REQEN0_SET_SET6_SHIFT (6U) -/*! SET6 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET6_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET6_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET7_MASK (0x80U) -#define INPUTMUX_DMA0_REQEN0_SET_SET7_SHIFT (7U) -/*! SET7 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET7_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET7_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET8_MASK (0x100U) -#define INPUTMUX_DMA0_REQEN0_SET_SET8_SHIFT (8U) -/*! SET8 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET8_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET8_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET9_MASK (0x200U) -#define INPUTMUX_DMA0_REQEN0_SET_SET9_SHIFT (9U) -/*! SET9 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET9_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET9_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET10_MASK (0x400U) -#define INPUTMUX_DMA0_REQEN0_SET_SET10_SHIFT (10U) -/*! SET10 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET10_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET10_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET11_MASK (0x800U) -#define INPUTMUX_DMA0_REQEN0_SET_SET11_SHIFT (11U) -/*! SET11 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET11_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET11_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET12_MASK (0x1000U) -#define INPUTMUX_DMA0_REQEN0_SET_SET12_SHIFT (12U) -/*! SET12 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET12_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET12_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET13_MASK (0x2000U) -#define INPUTMUX_DMA0_REQEN0_SET_SET13_SHIFT (13U) -/*! SET13 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET13_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET13_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET14_MASK (0x4000U) -#define INPUTMUX_DMA0_REQEN0_SET_SET14_SHIFT (14U) -/*! SET14 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET14_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET14_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET15_MASK (0x8000U) -#define INPUTMUX_DMA0_REQEN0_SET_SET15_SHIFT (15U) -/*! SET15 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET15_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET15_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET16_MASK (0x10000U) -#define INPUTMUX_DMA0_REQEN0_SET_SET16_SHIFT (16U) -/*! SET16 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET16_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET16_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET17_MASK (0x20000U) -#define INPUTMUX_DMA0_REQEN0_SET_SET17_SHIFT (17U) -/*! SET17 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET17_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET17_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET18_MASK (0x40000U) -#define INPUTMUX_DMA0_REQEN0_SET_SET18_SHIFT (18U) -/*! SET18 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET18_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET18_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET19_MASK (0x80000U) -#define INPUTMUX_DMA0_REQEN0_SET_SET19_SHIFT (19U) -/*! SET19 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET19_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET19_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET20_MASK (0x100000U) -#define INPUTMUX_DMA0_REQEN0_SET_SET20_SHIFT (20U) -/*! SET20 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET20(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET20_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET20_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET21_MASK (0x200000U) -#define INPUTMUX_DMA0_REQEN0_SET_SET21_SHIFT (21U) -/*! SET21 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET21(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET21_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET21_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET22_MASK (0x400000U) -#define INPUTMUX_DMA0_REQEN0_SET_SET22_SHIFT (22U) -/*! SET22 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET22(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET22_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET22_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET23_MASK (0x800000U) -#define INPUTMUX_DMA0_REQEN0_SET_SET23_SHIFT (23U) -/*! SET23 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET23(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET23_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET23_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET24_MASK (0x1000000U) -#define INPUTMUX_DMA0_REQEN0_SET_SET24_SHIFT (24U) -/*! SET24 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET24(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET24_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET24_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET25_MASK (0x2000000U) -#define INPUTMUX_DMA0_REQEN0_SET_SET25_SHIFT (25U) -/*! SET25 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET25(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET25_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET25_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET26_MASK (0x4000000U) -#define INPUTMUX_DMA0_REQEN0_SET_SET26_SHIFT (26U) -/*! SET26 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET26(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET26_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET26_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET27_MASK (0x8000000U) -#define INPUTMUX_DMA0_REQEN0_SET_SET27_SHIFT (27U) -/*! SET27 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET27(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET27_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET27_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET28_MASK (0x10000000U) -#define INPUTMUX_DMA0_REQEN0_SET_SET28_SHIFT (28U) -/*! SET28 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET28(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET28_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET28_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET29_MASK (0x20000000U) -#define INPUTMUX_DMA0_REQEN0_SET_SET29_SHIFT (29U) -/*! SET29 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET29(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET29_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET29_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET30_MASK (0x40000000U) -#define INPUTMUX_DMA0_REQEN0_SET_SET30_SHIFT (30U) -/*! SET30 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET30(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET30_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET30_MASK) - -#define INPUTMUX_DMA0_REQEN0_SET_SET31_MASK (0x80000000U) -#define INPUTMUX_DMA0_REQEN0_SET_SET31_SHIFT (31U) -/*! SET31 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_SET_SET31(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET31_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET31_MASK) -/*! @} */ - -/*! @name DMA0_REQEN1_SET - Set bits in DMA0_REQEN1 register */ -/*! @{ */ - -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA0_MASK (0x1U) -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA0_SHIFT (0U) -/*! REQ_ENA0 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA0_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA0_MASK) - -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA1_MASK (0x2U) -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA1_SHIFT (1U) -/*! REQ_ENA1 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA1_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA1_MASK) - -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA2_MASK (0x4U) -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA2_SHIFT (2U) -/*! REQ_ENA2 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA2_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA2_MASK) - -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA3_MASK (0x8U) -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA3_SHIFT (3U) -/*! REQ_ENA3 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA3_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA3_MASK) - -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA4_MASK (0x10U) -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA4_SHIFT (4U) -/*! REQ_ENA4 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA4_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA4_MASK) - -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA5_MASK (0x20U) -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA5_SHIFT (5U) -/*! REQ_ENA5 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA5_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA5_MASK) - -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA6_MASK (0x40U) -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA6_SHIFT (6U) -/*! REQ_ENA6 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA6_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA6_MASK) - -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA7_MASK (0x80U) -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA7_SHIFT (7U) -/*! REQ_ENA7 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA7_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA7_MASK) - -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA8_MASK (0x100U) -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA8_SHIFT (8U) -/*! REQ_ENA8 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA8_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA8_MASK) - -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA9_MASK (0x200U) -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA9_SHIFT (9U) -/*! REQ_ENA9 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA9_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA9_MASK) - -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA10_MASK (0x400U) -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA10_SHIFT (10U) -/*! REQ_ENA10 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA10_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA10_MASK) - -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA11_MASK (0x800U) -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA11_SHIFT (11U) -/*! REQ_ENA11 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA11_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA11_MASK) - -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA12_MASK (0x1000U) -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA12_SHIFT (12U) -/*! REQ_ENA12 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA12_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA12_MASK) - -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA13_MASK (0x2000U) -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA13_SHIFT (13U) -/*! REQ_ENA13 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA13_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA13_MASK) - -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA14_MASK (0x4000U) -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA14_SHIFT (14U) -/*! REQ_ENA14 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA14_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA14_MASK) - -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA15_MASK (0x8000U) -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA15_SHIFT (15U) -/*! REQ_ENA15 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA15_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA15_MASK) - -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA16_MASK (0x10000U) -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA16_SHIFT (16U) -/*! REQ_ENA16 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA16_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA16_MASK) - -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA17_MASK (0x20000U) -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA17_SHIFT (17U) -/*! REQ_ENA17 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA17_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA17_MASK) - -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA18_MASK (0x40000U) -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA18_SHIFT (18U) -/*! REQ_ENA18 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA18_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA18_MASK) - -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA19_MASK (0x80000U) -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA19_SHIFT (19U) -/*! REQ_ENA19 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA19_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA19_MASK) -/*! @} */ - -/*! @name DMA0_REQEN0_CLR - Clear bits in DMA0_REQEN0 register */ -/*! @{ */ - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR0_MASK (0x1U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR0_SHIFT (0U) -/*! CLR0 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR0_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR0_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR1_MASK (0x2U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR1_SHIFT (1U) -/*! CLR1 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR1_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR1_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR2_MASK (0x4U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR2_SHIFT (2U) -/*! CLR2 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR2_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR2_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR3_MASK (0x8U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR3_SHIFT (3U) -/*! CLR3 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR3_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR3_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR4_MASK (0x10U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR4_SHIFT (4U) -/*! CLR4 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR4_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR4_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR5_MASK (0x20U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR5_SHIFT (5U) -/*! CLR5 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR5_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR5_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR6_MASK (0x40U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR6_SHIFT (6U) -/*! CLR6 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR6_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR6_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR7_MASK (0x80U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR7_SHIFT (7U) -/*! CLR7 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR7_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR7_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR8_MASK (0x100U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR8_SHIFT (8U) -/*! CLR8 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR8_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR8_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR9_MASK (0x200U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR9_SHIFT (9U) -/*! CLR9 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR9_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR9_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR10_MASK (0x400U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR10_SHIFT (10U) -/*! CLR10 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR10_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR10_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR11_MASK (0x800U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR11_SHIFT (11U) -/*! CLR11 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR11_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR11_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR12_MASK (0x1000U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR12_SHIFT (12U) -/*! CLR12 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR12_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR12_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR13_MASK (0x2000U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR13_SHIFT (13U) -/*! CLR13 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR13_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR13_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR14_MASK (0x4000U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR14_SHIFT (14U) -/*! CLR14 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR14_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR14_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR15_MASK (0x8000U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR15_SHIFT (15U) -/*! CLR15 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR15_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR15_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR16_MASK (0x10000U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR16_SHIFT (16U) -/*! CLR16 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR16_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR16_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR17_MASK (0x20000U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR17_SHIFT (17U) -/*! CLR17 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR17_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR17_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR18_MASK (0x40000U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR18_SHIFT (18U) -/*! CLR18 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR18_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR18_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR19_MASK (0x80000U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR19_SHIFT (19U) -/*! CLR19 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR19_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR19_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR20_MASK (0x100000U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR20_SHIFT (20U) -/*! CLR20 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR20(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR20_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR20_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR21_MASK (0x200000U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR21_SHIFT (21U) -/*! CLR21 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR21(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR21_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR21_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR22_MASK (0x400000U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR22_SHIFT (22U) -/*! CLR22 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR22(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR22_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR22_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR23_MASK (0x800000U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR23_SHIFT (23U) -/*! CLR23 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR23(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR23_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR23_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR24_MASK (0x1000000U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR24_SHIFT (24U) -/*! CLR24 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR24(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR24_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR24_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR25_MASK (0x2000000U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR25_SHIFT (25U) -/*! CLR25 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR25(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR25_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR25_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR26_MASK (0x4000000U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR26_SHIFT (26U) -/*! CLR26 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR26(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR26_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR26_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR27_MASK (0x8000000U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR27_SHIFT (27U) -/*! CLR27 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR27(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR27_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR27_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR28_MASK (0x10000000U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR28_SHIFT (28U) -/*! CLR28 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR28(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR28_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR28_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR29_MASK (0x20000000U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR29_SHIFT (29U) -/*! CLR29 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR29(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR29_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR29_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR30_MASK (0x40000000U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR30_SHIFT (30U) -/*! CLR30 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR30(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR30_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR30_MASK) - -#define INPUTMUX_DMA0_REQEN0_CLR_CLR31_MASK (0x80000000U) -#define INPUTMUX_DMA0_REQEN0_CLR_CLR31_SHIFT (31U) -/*! CLR31 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. - */ -#define INPUTMUX_DMA0_REQEN0_CLR_CLR31(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR31_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR31_MASK) -/*! @} */ - -/*! @name DMA0_REQEN1_CLR - Clear bits in DMA0_REQEN1 register */ -/*! @{ */ - -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA0_MASK (0x1U) -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA0_SHIFT (0U) -/*! REQ_ENA0 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA0_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA0_MASK) - -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA1_MASK (0x2U) -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA1_SHIFT (1U) -/*! REQ_ENA1 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA1_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA1_MASK) - -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA2_MASK (0x4U) -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA2_SHIFT (2U) -/*! REQ_ENA2 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA2_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA2_MASK) - -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA3_MASK (0x8U) -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA3_SHIFT (3U) -/*! REQ_ENA3 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA3_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA3_MASK) - -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA4_MASK (0x10U) -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA4_SHIFT (4U) -/*! REQ_ENA4 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA4_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA4_MASK) - -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA5_MASK (0x20U) -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA5_SHIFT (5U) -/*! REQ_ENA5 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA5_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA5_MASK) - -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA6_MASK (0x40U) -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA6_SHIFT (6U) -/*! REQ_ENA6 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA6_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA6_MASK) - -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA7_MASK (0x80U) -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA7_SHIFT (7U) -/*! REQ_ENA7 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA7_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA7_MASK) - -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA8_MASK (0x100U) -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA8_SHIFT (8U) -/*! REQ_ENA8 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA8_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA8_MASK) - -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA9_MASK (0x200U) -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA9_SHIFT (9U) -/*! REQ_ENA9 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA9_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA9_MASK) - -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA10_MASK (0x400U) -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA10_SHIFT (10U) -/*! REQ_ENA10 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA10_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA10_MASK) - -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA11_MASK (0x800U) -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA11_SHIFT (11U) -/*! REQ_ENA11 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA11_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA11_MASK) - -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA12_MASK (0x1000U) -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA12_SHIFT (12U) -/*! REQ_ENA12 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA12_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA12_MASK) - -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA13_MASK (0x2000U) -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA13_SHIFT (13U) -/*! REQ_ENA13 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA13_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA13_MASK) - -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA14_MASK (0x4000U) -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA14_SHIFT (14U) -/*! REQ_ENA14 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA14_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA14_MASK) - -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA15_MASK (0x8000U) -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA15_SHIFT (15U) -/*! REQ_ENA15 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA15_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA15_MASK) - -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA16_MASK (0x10000U) -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA16_SHIFT (16U) -/*! REQ_ENA16 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA16_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA16_MASK) - -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA17_MASK (0x20000U) -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA17_SHIFT (17U) -/*! REQ_ENA17 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA17_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA17_MASK) - -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA18_MASK (0x40000U) -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA18_SHIFT (18U) -/*! REQ_ENA18 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA18_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA18_MASK) - -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA19_MASK (0x80000U) -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA19_SHIFT (19U) -/*! REQ_ENA19 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. - */ -#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA19_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA19_MASK) -/*! @} */ - -/*! @name DMA1_REQEN - Enable DMA1 requests */ -/*! @{ */ - -#define INPUTMUX_DMA1_REQEN_REQ_ENA0_MASK (0x1U) -#define INPUTMUX_DMA1_REQEN_REQ_ENA0_SHIFT (0U) -/*! REQ_ENA0 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA1_REQEN_REQ_ENA0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA0_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA0_MASK) - -#define INPUTMUX_DMA1_REQEN_REQ_ENA1_MASK (0x2U) -#define INPUTMUX_DMA1_REQEN_REQ_ENA1_SHIFT (1U) -/*! REQ_ENA1 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA1_REQEN_REQ_ENA1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA1_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA1_MASK) - -#define INPUTMUX_DMA1_REQEN_REQ_ENA2_MASK (0x4U) -#define INPUTMUX_DMA1_REQEN_REQ_ENA2_SHIFT (2U) -/*! REQ_ENA2 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA1_REQEN_REQ_ENA2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA2_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA2_MASK) - -#define INPUTMUX_DMA1_REQEN_REQ_ENA3_MASK (0x8U) -#define INPUTMUX_DMA1_REQEN_REQ_ENA3_SHIFT (3U) -/*! REQ_ENA3 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA1_REQEN_REQ_ENA3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA3_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA3_MASK) - -#define INPUTMUX_DMA1_REQEN_REQ_ENA4_MASK (0x10U) -#define INPUTMUX_DMA1_REQEN_REQ_ENA4_SHIFT (4U) -/*! REQ_ENA4 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA1_REQEN_REQ_ENA4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA4_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA4_MASK) - -#define INPUTMUX_DMA1_REQEN_REQ_ENA5_MASK (0x20U) -#define INPUTMUX_DMA1_REQEN_REQ_ENA5_SHIFT (5U) -/*! REQ_ENA5 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA1_REQEN_REQ_ENA5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA5_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA5_MASK) - -#define INPUTMUX_DMA1_REQEN_REQ_ENA6_MASK (0x40U) -#define INPUTMUX_DMA1_REQEN_REQ_ENA6_SHIFT (6U) -/*! REQ_ENA6 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA1_REQEN_REQ_ENA6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA6_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA6_MASK) - -#define INPUTMUX_DMA1_REQEN_REQ_ENA7_MASK (0x80U) -#define INPUTMUX_DMA1_REQEN_REQ_ENA7_SHIFT (7U) -/*! REQ_ENA7 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA1_REQEN_REQ_ENA7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA7_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA7_MASK) - -#define INPUTMUX_DMA1_REQEN_REQ_ENA8_MASK (0x100U) -#define INPUTMUX_DMA1_REQEN_REQ_ENA8_SHIFT (8U) -/*! REQ_ENA8 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA1_REQEN_REQ_ENA8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA8_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA8_MASK) - -#define INPUTMUX_DMA1_REQEN_REQ_ENA9_MASK (0x200U) -#define INPUTMUX_DMA1_REQEN_REQ_ENA9_SHIFT (9U) -/*! REQ_ENA9 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA1_REQEN_REQ_ENA9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA9_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA9_MASK) - -#define INPUTMUX_DMA1_REQEN_REQ_ENA10_MASK (0x400U) -#define INPUTMUX_DMA1_REQEN_REQ_ENA10_SHIFT (10U) -/*! REQ_ENA10 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA1_REQEN_REQ_ENA10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA10_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA10_MASK) - -#define INPUTMUX_DMA1_REQEN_REQ_ENA11_MASK (0x800U) -#define INPUTMUX_DMA1_REQEN_REQ_ENA11_SHIFT (11U) -/*! REQ_ENA11 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA1_REQEN_REQ_ENA11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA11_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA11_MASK) - -#define INPUTMUX_DMA1_REQEN_REQ_ENA12_MASK (0x1000U) -#define INPUTMUX_DMA1_REQEN_REQ_ENA12_SHIFT (12U) -/*! REQ_ENA12 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA1_REQEN_REQ_ENA12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA12_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA12_MASK) - -#define INPUTMUX_DMA1_REQEN_REQ_ENA13_MASK (0x2000U) -#define INPUTMUX_DMA1_REQEN_REQ_ENA13_SHIFT (13U) -/*! REQ_ENA13 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA1_REQEN_REQ_ENA13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA13_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA13_MASK) - -#define INPUTMUX_DMA1_REQEN_REQ_ENA14_MASK (0x4000U) -#define INPUTMUX_DMA1_REQEN_REQ_ENA14_SHIFT (14U) -/*! REQ_ENA14 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA1_REQEN_REQ_ENA14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA14_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA14_MASK) - -#define INPUTMUX_DMA1_REQEN_REQ_ENA15_MASK (0x8000U) -#define INPUTMUX_DMA1_REQEN_REQ_ENA15_SHIFT (15U) -/*! REQ_ENA15 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA1_REQEN_REQ_ENA15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA15_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA15_MASK) -/*! @} */ - -/*! @name DMA1_REQEN_SET - Set bits in DMA1_REQEN register */ -/*! @{ */ - -#define INPUTMUX_DMA1_REQEN_SET_SET0_MASK (0x1U) -#define INPUTMUX_DMA1_REQEN_SET_SET0_SHIFT (0U) -/*! SET0 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_SET_SET0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET0_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET0_MASK) - -#define INPUTMUX_DMA1_REQEN_SET_SET1_MASK (0x2U) -#define INPUTMUX_DMA1_REQEN_SET_SET1_SHIFT (1U) -/*! SET1 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_SET_SET1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET1_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET1_MASK) - -#define INPUTMUX_DMA1_REQEN_SET_SET2_MASK (0x4U) -#define INPUTMUX_DMA1_REQEN_SET_SET2_SHIFT (2U) -/*! SET2 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_SET_SET2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET2_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET2_MASK) - -#define INPUTMUX_DMA1_REQEN_SET_SET3_MASK (0x8U) -#define INPUTMUX_DMA1_REQEN_SET_SET3_SHIFT (3U) -/*! SET3 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_SET_SET3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET3_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET3_MASK) - -#define INPUTMUX_DMA1_REQEN_SET_SET4_MASK (0x10U) -#define INPUTMUX_DMA1_REQEN_SET_SET4_SHIFT (4U) -/*! SET4 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_SET_SET4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET4_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET4_MASK) - -#define INPUTMUX_DMA1_REQEN_SET_SET5_MASK (0x20U) -#define INPUTMUX_DMA1_REQEN_SET_SET5_SHIFT (5U) -/*! SET5 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_SET_SET5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET5_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET5_MASK) - -#define INPUTMUX_DMA1_REQEN_SET_SET6_MASK (0x40U) -#define INPUTMUX_DMA1_REQEN_SET_SET6_SHIFT (6U) -/*! SET6 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_SET_SET6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET6_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET6_MASK) - -#define INPUTMUX_DMA1_REQEN_SET_SET7_MASK (0x80U) -#define INPUTMUX_DMA1_REQEN_SET_SET7_SHIFT (7U) -/*! SET7 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_SET_SET7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET7_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET7_MASK) - -#define INPUTMUX_DMA1_REQEN_SET_SET8_MASK (0x100U) -#define INPUTMUX_DMA1_REQEN_SET_SET8_SHIFT (8U) -/*! SET8 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_SET_SET8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET8_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET8_MASK) - -#define INPUTMUX_DMA1_REQEN_SET_SET9_MASK (0x200U) -#define INPUTMUX_DMA1_REQEN_SET_SET9_SHIFT (9U) -/*! SET9 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_SET_SET9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET9_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET9_MASK) - -#define INPUTMUX_DMA1_REQEN_SET_SET10_MASK (0x400U) -#define INPUTMUX_DMA1_REQEN_SET_SET10_SHIFT (10U) -/*! SET10 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_SET_SET10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET10_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET10_MASK) - -#define INPUTMUX_DMA1_REQEN_SET_SET11_MASK (0x800U) -#define INPUTMUX_DMA1_REQEN_SET_SET11_SHIFT (11U) -/*! SET11 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_SET_SET11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET11_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET11_MASK) - -#define INPUTMUX_DMA1_REQEN_SET_SET12_MASK (0x1000U) -#define INPUTMUX_DMA1_REQEN_SET_SET12_SHIFT (12U) -/*! SET12 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_SET_SET12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET12_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET12_MASK) - -#define INPUTMUX_DMA1_REQEN_SET_SET13_MASK (0x2000U) -#define INPUTMUX_DMA1_REQEN_SET_SET13_SHIFT (13U) -/*! SET13 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_SET_SET13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET13_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET13_MASK) - -#define INPUTMUX_DMA1_REQEN_SET_SET14_MASK (0x4000U) -#define INPUTMUX_DMA1_REQEN_SET_SET14_SHIFT (14U) -/*! SET14 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_SET_SET14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET14_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET14_MASK) - -#define INPUTMUX_DMA1_REQEN_SET_SET15_MASK (0x8000U) -#define INPUTMUX_DMA1_REQEN_SET_SET15_SHIFT (15U) -/*! SET15 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_SET_SET15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET15_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET15_MASK) -/*! @} */ - -/*! @name DMA1_REQEN_CLR - Clear bits in DMA1_REQEN register */ -/*! @{ */ - -#define INPUTMUX_DMA1_REQEN_CLR_CLR0_MASK (0x1U) -#define INPUTMUX_DMA1_REQEN_CLR_CLR0_SHIFT (0U) -/*! CLR0 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_CLR_CLR0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR0_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR0_MASK) - -#define INPUTMUX_DMA1_REQEN_CLR_CLR1_MASK (0x2U) -#define INPUTMUX_DMA1_REQEN_CLR_CLR1_SHIFT (1U) -/*! CLR1 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_CLR_CLR1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR1_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR1_MASK) - -#define INPUTMUX_DMA1_REQEN_CLR_CLR2_MASK (0x4U) -#define INPUTMUX_DMA1_REQEN_CLR_CLR2_SHIFT (2U) -/*! CLR2 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_CLR_CLR2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR2_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR2_MASK) - -#define INPUTMUX_DMA1_REQEN_CLR_CLR3_MASK (0x8U) -#define INPUTMUX_DMA1_REQEN_CLR_CLR3_SHIFT (3U) -/*! CLR3 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_CLR_CLR3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR3_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR3_MASK) - -#define INPUTMUX_DMA1_REQEN_CLR_CLR4_MASK (0x10U) -#define INPUTMUX_DMA1_REQEN_CLR_CLR4_SHIFT (4U) -/*! CLR4 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_CLR_CLR4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR4_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR4_MASK) - -#define INPUTMUX_DMA1_REQEN_CLR_CLR5_MASK (0x20U) -#define INPUTMUX_DMA1_REQEN_CLR_CLR5_SHIFT (5U) -/*! CLR5 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_CLR_CLR5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR5_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR5_MASK) - -#define INPUTMUX_DMA1_REQEN_CLR_CLR6_MASK (0x40U) -#define INPUTMUX_DMA1_REQEN_CLR_CLR6_SHIFT (6U) -/*! CLR6 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_CLR_CLR6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR6_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR6_MASK) - -#define INPUTMUX_DMA1_REQEN_CLR_CLR7_MASK (0x80U) -#define INPUTMUX_DMA1_REQEN_CLR_CLR7_SHIFT (7U) -/*! CLR7 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_CLR_CLR7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR7_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR7_MASK) - -#define INPUTMUX_DMA1_REQEN_CLR_CLR8_MASK (0x100U) -#define INPUTMUX_DMA1_REQEN_CLR_CLR8_SHIFT (8U) -/*! CLR8 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_CLR_CLR8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR8_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR8_MASK) - -#define INPUTMUX_DMA1_REQEN_CLR_CLR9_MASK (0x200U) -#define INPUTMUX_DMA1_REQEN_CLR_CLR9_SHIFT (9U) -/*! CLR9 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_CLR_CLR9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR9_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR9_MASK) - -#define INPUTMUX_DMA1_REQEN_CLR_CLR10_MASK (0x400U) -#define INPUTMUX_DMA1_REQEN_CLR_CLR10_SHIFT (10U) -/*! CLR10 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_CLR_CLR10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR10_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR10_MASK) - -#define INPUTMUX_DMA1_REQEN_CLR_CLR11_MASK (0x800U) -#define INPUTMUX_DMA1_REQEN_CLR_CLR11_SHIFT (11U) -/*! CLR11 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_CLR_CLR11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR11_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR11_MASK) - -#define INPUTMUX_DMA1_REQEN_CLR_CLR12_MASK (0x1000U) -#define INPUTMUX_DMA1_REQEN_CLR_CLR12_SHIFT (12U) -/*! CLR12 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_CLR_CLR12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR12_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR12_MASK) - -#define INPUTMUX_DMA1_REQEN_CLR_CLR13_MASK (0x2000U) -#define INPUTMUX_DMA1_REQEN_CLR_CLR13_SHIFT (13U) -/*! CLR13 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_CLR_CLR13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR13_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR13_MASK) - -#define INPUTMUX_DMA1_REQEN_CLR_CLR14_MASK (0x4000U) -#define INPUTMUX_DMA1_REQEN_CLR_CLR14_SHIFT (14U) -/*! CLR14 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_CLR_CLR14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR14_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR14_MASK) - -#define INPUTMUX_DMA1_REQEN_CLR_CLR15_MASK (0x8000U) -#define INPUTMUX_DMA1_REQEN_CLR_CLR15_SHIFT (15U) -/*! CLR15 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register - */ -#define INPUTMUX_DMA1_REQEN_CLR_CLR15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR15_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR15_MASK) -/*! @} */ - -/*! @name DMA0_ITRIGEN0 - Enable DMA0 triggers */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN0_MASK (0x1U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN0_SHIFT (0U) -/*! ITRIGEN0 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN0_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN0_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN1_MASK (0x2U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN1_SHIFT (1U) -/*! ITRIGEN1 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN1_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN1_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN2_MASK (0x4U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN2_SHIFT (2U) -/*! ITRIGEN2 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN2_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN2_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN3_MASK (0x8U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN3_SHIFT (3U) -/*! ITRIGEN3 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN3_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN3_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN4_MASK (0x10U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN4_SHIFT (4U) -/*! ITRIGEN4 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN4_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN4_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN5_MASK (0x20U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN5_SHIFT (5U) -/*! ITRIGEN5 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN5_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN5_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN6_MASK (0x40U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN6_SHIFT (6U) -/*! ITRIGEN6 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN6_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN6_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN7_MASK (0x80U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN7_SHIFT (7U) -/*! ITRIGEN7 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN7_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN7_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN8_MASK (0x100U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN8_SHIFT (8U) -/*! ITRIGEN8 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN8_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN8_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN9_MASK (0x200U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN9_SHIFT (9U) -/*! ITRIGEN9 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN9_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN9_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN10_MASK (0x400U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN10_SHIFT (10U) -/*! ITRIGEN10 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN10_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN10_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN11_MASK (0x800U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN11_SHIFT (11U) -/*! ITRIGEN11 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN11_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN11_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN12_MASK (0x1000U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN12_SHIFT (12U) -/*! ITRIGEN12 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN12_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN12_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN13_MASK (0x2000U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN13_SHIFT (13U) -/*! ITRIGEN13 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN13_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN13_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN14_MASK (0x4000U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN14_SHIFT (14U) -/*! ITRIGEN14 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN14_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN14_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN15_MASK (0x8000U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN15_SHIFT (15U) -/*! ITRIGEN15 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN15_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN15_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN16_MASK (0x10000U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN16_SHIFT (16U) -/*! ITRIGEN16 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN16_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN16_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN17_MASK (0x20000U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN17_SHIFT (17U) -/*! ITRIGEN17 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN17_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN17_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN18_MASK (0x40000U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN18_SHIFT (18U) -/*! ITRIGEN18 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN18_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN18_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN19_MASK (0x80000U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN19_SHIFT (19U) -/*! ITRIGEN19 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN19_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN19_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN20_MASK (0x100000U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN20_SHIFT (20U) -/*! ITRIGEN20 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN20(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN20_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN20_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN21_MASK (0x200000U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN21_SHIFT (21U) -/*! ITRIGEN21 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN21(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN21_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN21_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN22_MASK (0x400000U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN22_SHIFT (22U) -/*! ITRIGEN22 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN22(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN22_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN22_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN23_MASK (0x800000U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN23_SHIFT (23U) -/*! ITRIGEN23 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN23(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN23_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN23_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN24_MASK (0x1000000U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN24_SHIFT (24U) -/*! ITRIGEN24 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN24(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN24_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN24_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN25_MASK (0x2000000U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN25_SHIFT (25U) -/*! ITRIGEN25 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN25(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN25_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN25_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN26_MASK (0x4000000U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN26_SHIFT (26U) -/*! ITRIGEN26 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN26(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN26_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN26_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN27_MASK (0x8000000U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN27_SHIFT (27U) -/*! ITRIGEN27 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN27(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN27_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN27_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN28_MASK (0x10000000U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN28_SHIFT (28U) -/*! ITRIGEN28 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN28(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN28_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN28_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN29_MASK (0x20000000U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN29_SHIFT (29U) -/*! ITRIGEN29 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN29(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN29_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN29_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN30_MASK (0x40000000U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN30_SHIFT (30U) -/*! ITRIGEN30 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN30(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN30_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN30_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN31_MASK (0x80000000U) -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN31_SHIFT (31U) -/*! ITRIGEN31 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN31(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN31_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN31_MASK) -/*! @} */ - -/*! @name DMA0_ITRIGEN1 - Enable DMA0 triggers */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN0_MASK (0x1U) -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN0_SHIFT (0U) -/*! ITRIGEN0 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN0_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN0_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN1_MASK (0x2U) -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN1_SHIFT (1U) -/*! ITRIGEN1 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN1_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN1_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN2_MASK (0x4U) -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN2_SHIFT (2U) -/*! ITRIGEN2 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN2_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN2_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN3_MASK (0x8U) -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN3_SHIFT (3U) -/*! ITRIGEN3 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN3_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN3_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN4_MASK (0x10U) -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN4_SHIFT (4U) -/*! ITRIGEN4 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN4_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN4_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN5_MASK (0x20U) -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN5_SHIFT (5U) -/*! ITRIGEN5 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN5_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN5_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN6_MASK (0x40U) -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN6_SHIFT (6U) -/*! ITRIGEN6 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN6_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN6_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN7_MASK (0x80U) -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN7_SHIFT (7U) -/*! ITRIGEN7 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN7_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN7_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN8_MASK (0x100U) -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN8_SHIFT (8U) -/*! ITRIGEN8 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN8_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN8_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN9_MASK (0x200U) -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN9_SHIFT (9U) -/*! ITRIGEN9 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN9_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN9_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN10_MASK (0x400U) -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN10_SHIFT (10U) -/*! ITRIGEN10 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN10_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN10_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN11_MASK (0x800U) -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN11_SHIFT (11U) -/*! ITRIGEN11 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN11_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN11_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN12_MASK (0x1000U) -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN12_SHIFT (12U) -/*! ITRIGEN12 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN12_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN12_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN13_MASK (0x2000U) -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN13_SHIFT (13U) -/*! ITRIGEN13 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN13_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN13_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN14_MASK (0x4000U) -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN14_SHIFT (14U) -/*! ITRIGEN14 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN14_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN14_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN15_MASK (0x8000U) -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN15_SHIFT (15U) -/*! ITRIGEN15 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN15_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN15_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN16_MASK (0x10000U) -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN16_SHIFT (16U) -/*! ITRIGEN16 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN16_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN16_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN17_MASK (0x20000U) -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN17_SHIFT (17U) -/*! ITRIGEN17 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN17_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN17_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN18_MASK (0x40000U) -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN18_SHIFT (18U) -/*! ITRIGEN18 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN18_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN18_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN19_MASK (0x80000U) -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN19_SHIFT (19U) -/*! ITRIGEN19 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. - */ -#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN19_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN19_MASK) -/*! @} */ - -/*! @name DMA0_ITRIGEN0_SET - Set bits in DMA0_ITRIGEN0 register */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET0_MASK (0x1U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET0_SHIFT (0U) -/*! SET0 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET0_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET0_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET1_MASK (0x2U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET1_SHIFT (1U) -/*! SET1 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET1_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET1_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET2_MASK (0x4U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET2_SHIFT (2U) -/*! SET2 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET2_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET2_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET3_MASK (0x8U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET3_SHIFT (3U) -/*! SET3 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET3_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET3_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET4_MASK (0x10U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET4_SHIFT (4U) -/*! SET4 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET4_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET4_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET5_MASK (0x20U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET5_SHIFT (5U) -/*! SET5 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET5_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET5_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET6_MASK (0x40U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET6_SHIFT (6U) -/*! SET6 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET6_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET6_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET7_MASK (0x80U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET7_SHIFT (7U) -/*! SET7 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET7_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET7_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET8_MASK (0x100U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET8_SHIFT (8U) -/*! SET8 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET8_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET8_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET9_MASK (0x200U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET9_SHIFT (9U) -/*! SET9 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET9_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET9_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET10_MASK (0x400U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET10_SHIFT (10U) -/*! SET10 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET10_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET10_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET11_MASK (0x800U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET11_SHIFT (11U) -/*! SET11 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET11_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET11_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET12_MASK (0x1000U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET12_SHIFT (12U) -/*! SET12 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET12_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET12_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET13_MASK (0x2000U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET13_SHIFT (13U) -/*! SET13 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET13_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET13_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET14_MASK (0x4000U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET14_SHIFT (14U) -/*! SET14 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET14_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET14_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET15_MASK (0x8000U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET15_SHIFT (15U) -/*! SET15 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET15_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET15_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET16_MASK (0x10000U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET16_SHIFT (16U) -/*! SET16 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET16_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET16_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET17_MASK (0x20000U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET17_SHIFT (17U) -/*! SET17 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET17_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET17_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET18_MASK (0x40000U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET18_SHIFT (18U) -/*! SET18 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET18_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET18_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET19_MASK (0x80000U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET19_SHIFT (19U) -/*! SET19 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET19_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET19_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET20_MASK (0x100000U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET20_SHIFT (20U) -/*! SET20 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET20(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET20_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET20_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET21_MASK (0x200000U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET21_SHIFT (21U) -/*! SET21 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET21(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET21_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET21_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET22_MASK (0x400000U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET22_SHIFT (22U) -/*! SET22 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET22(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET22_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET22_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET23_MASK (0x800000U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET23_SHIFT (23U) -/*! SET23 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET23(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET23_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET23_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET24_MASK (0x1000000U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET24_SHIFT (24U) -/*! SET24 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET24(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET24_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET24_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET25_MASK (0x2000000U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET25_SHIFT (25U) -/*! SET25 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET25(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET25_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET25_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET26_MASK (0x4000000U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET26_SHIFT (26U) -/*! SET26 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET26(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET26_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET26_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET27_MASK (0x8000000U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET27_SHIFT (27U) -/*! SET27 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET27(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET27_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET27_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET28_MASK (0x10000000U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET28_SHIFT (28U) -/*! SET28 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET28(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET28_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET28_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET29_MASK (0x20000000U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET29_SHIFT (29U) -/*! SET29 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET29(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET29_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET29_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET30_MASK (0x40000000U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET30_SHIFT (30U) -/*! SET30 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET30(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET30_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET30_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET31_MASK (0x80000000U) -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET31_SHIFT (31U) -/*! SET31 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_SET_SET31(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET31_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET31_MASK) -/*! @} */ - -/*! @name DMA0_ITRIGEN1_SET - Set bits in DMA0_ITRIGEN1 register */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET0_MASK (0x1U) -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET0_SHIFT (0U) -/*! SET0 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET0_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET0_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET1_MASK (0x2U) -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET1_SHIFT (1U) -/*! SET1 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET1_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET1_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET2_MASK (0x4U) -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET2_SHIFT (2U) -/*! SET2 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET2_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET2_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET3_MASK (0x8U) -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET3_SHIFT (3U) -/*! SET3 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET3_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET3_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET4_MASK (0x10U) -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET4_SHIFT (4U) -/*! SET4 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET4_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET4_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET5_MASK (0x20U) -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET5_SHIFT (5U) -/*! SET5 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET5_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET5_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET6_MASK (0x40U) -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET6_SHIFT (6U) -/*! SET6 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET6_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET6_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET7_MASK (0x80U) -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET7_SHIFT (7U) -/*! SET7 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET7_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET7_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET8_MASK (0x100U) -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET8_SHIFT (8U) -/*! SET8 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET8_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET8_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET9_MASK (0x200U) -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET9_SHIFT (9U) -/*! SET9 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET9_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET9_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET10_MASK (0x400U) -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET10_SHIFT (10U) -/*! SET10 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET10_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET10_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET11_MASK (0x800U) -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET11_SHIFT (11U) -/*! SET11 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET11_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET11_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET12_MASK (0x1000U) -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET12_SHIFT (12U) -/*! SET12 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET12_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET12_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET13_MASK (0x2000U) -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET13_SHIFT (13U) -/*! SET13 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET13_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET13_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET14_MASK (0x4000U) -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET14_SHIFT (14U) -/*! SET14 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET14_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET14_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET15_MASK (0x8000U) -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET15_SHIFT (15U) -/*! SET15 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET15_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET15_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET16_MASK (0x10000U) -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET16_SHIFT (16U) -/*! SET16 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET16_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET16_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET17_MASK (0x20000U) -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET17_SHIFT (17U) -/*! SET17 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET17_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET17_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET18_MASK (0x40000U) -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET18_SHIFT (18U) -/*! SET18 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET18_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET18_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET19_MASK (0x80000U) -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET19_SHIFT (19U) -/*! SET19 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_SET_SET19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET19_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET19_MASK) -/*! @} */ - -/*! @name DMA0_ITRIGEN0_CLR - Clear bits in DMA0_ITRIGEN0 register */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR0_MASK (0x1U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR0_SHIFT (0U) -/*! CLR0 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR0_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR0_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR1_MASK (0x2U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR1_SHIFT (1U) -/*! CLR1 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR1_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR1_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR2_MASK (0x4U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR2_SHIFT (2U) -/*! CLR2 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR2_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR2_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR3_MASK (0x8U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR3_SHIFT (3U) -/*! CLR3 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR3_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR3_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR4_MASK (0x10U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR4_SHIFT (4U) -/*! CLR4 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR4_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR4_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR5_MASK (0x20U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR5_SHIFT (5U) -/*! CLR5 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR5_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR5_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR6_MASK (0x40U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR6_SHIFT (6U) -/*! CLR6 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR6_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR6_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR7_MASK (0x80U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR7_SHIFT (7U) -/*! CLR7 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR7_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR7_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR8_MASK (0x100U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR8_SHIFT (8U) -/*! CLR8 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR8_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR8_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR9_MASK (0x200U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR9_SHIFT (9U) -/*! CLR9 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR9_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR9_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR10_MASK (0x400U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR10_SHIFT (10U) -/*! CLR10 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR10_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR10_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR11_MASK (0x800U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR11_SHIFT (11U) -/*! CLR11 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR11_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR11_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR12_MASK (0x1000U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR12_SHIFT (12U) -/*! CLR12 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR12_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR12_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR13_MASK (0x2000U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR13_SHIFT (13U) -/*! CLR13 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR13_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR13_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR14_MASK (0x4000U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR14_SHIFT (14U) -/*! CLR14 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR14_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR14_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR15_MASK (0x8000U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR15_SHIFT (15U) -/*! CLR15 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR15_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR15_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR16_MASK (0x10000U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR16_SHIFT (16U) -/*! CLR16 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR16_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR16_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR17_MASK (0x20000U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR17_SHIFT (17U) -/*! CLR17 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR17_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR17_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR18_MASK (0x40000U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR18_SHIFT (18U) -/*! CLR18 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR18_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR18_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR19_MASK (0x80000U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR19_SHIFT (19U) -/*! CLR19 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR19_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR19_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR20_MASK (0x100000U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR20_SHIFT (20U) -/*! CLR20 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR20(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR20_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR20_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR21_MASK (0x200000U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR21_SHIFT (21U) -/*! CLR21 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR21(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR21_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR21_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR22_MASK (0x400000U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR22_SHIFT (22U) -/*! CLR22 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR22(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR22_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR22_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR23_MASK (0x800000U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR23_SHIFT (23U) -/*! CLR23 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR23(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR23_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR23_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR24_MASK (0x1000000U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR24_SHIFT (24U) -/*! CLR24 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR24(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR24_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR24_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR25_MASK (0x2000000U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR25_SHIFT (25U) -/*! CLR25 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR25(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR25_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR25_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR26_MASK (0x4000000U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR26_SHIFT (26U) -/*! CLR26 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR26(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR26_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR26_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR27_MASK (0x8000000U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR27_SHIFT (27U) -/*! CLR27 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR27(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR27_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR27_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR28_MASK (0x10000000U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR28_SHIFT (28U) -/*! CLR28 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR28(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR28_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR28_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR29_MASK (0x20000000U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR29_SHIFT (29U) -/*! CLR29 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR29(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR29_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR29_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR30_MASK (0x40000000U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR30_SHIFT (30U) -/*! CLR30 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR30(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR30_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR30_MASK) - -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR31_MASK (0x80000000U) -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR31_SHIFT (31U) -/*! CLR31 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN0 register. - */ -#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR31(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR31_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR31_MASK) -/*! @} */ - -/*! @name DMA0_ITRIGEN1_CLR - Clear bits in DMA0_ITRIGEN1 register */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR0_MASK (0x1U) -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR0_SHIFT (0U) -/*! CLR0 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR0_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR0_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR1_MASK (0x2U) -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR1_SHIFT (1U) -/*! CLR1 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR1_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR1_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR2_MASK (0x4U) -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR2_SHIFT (2U) -/*! CLR2 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR2_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR2_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR3_MASK (0x8U) -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR3_SHIFT (3U) -/*! CLR3 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR3_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR3_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR4_MASK (0x10U) -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR4_SHIFT (4U) -/*! CLR4 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR4_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR4_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR5_MASK (0x20U) -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR5_SHIFT (5U) -/*! CLR5 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR5_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR5_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR6_MASK (0x40U) -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR6_SHIFT (6U) -/*! CLR6 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR6_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR6_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR7_MASK (0x80U) -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR7_SHIFT (7U) -/*! CLR7 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR7_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR7_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR8_MASK (0x100U) -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR8_SHIFT (8U) -/*! CLR8 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR8_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR8_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR9_MASK (0x200U) -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR9_SHIFT (9U) -/*! CLR9 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR9_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR9_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR10_MASK (0x400U) -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR10_SHIFT (10U) -/*! CLR10 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR10_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR10_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR11_MASK (0x800U) -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR11_SHIFT (11U) -/*! CLR11 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR11_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR11_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR12_MASK (0x1000U) -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR12_SHIFT (12U) -/*! CLR12 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR12_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR12_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR13_MASK (0x2000U) -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR13_SHIFT (13U) -/*! CLR13 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR13_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR13_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR14_MASK (0x4000U) -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR14_SHIFT (14U) -/*! CLR14 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR14_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR14_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR15_MASK (0x8000U) -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR15_SHIFT (15U) -/*! CLR15 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR15_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR15_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR16_MASK (0x10000U) -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR16_SHIFT (16U) -/*! CLR16 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR16_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR16_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR17_MASK (0x20000U) -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR17_SHIFT (17U) -/*! CLR17 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR17_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR17_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR18_MASK (0x40000U) -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR18_SHIFT (18U) -/*! CLR18 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR18_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR18_MASK) - -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR19_MASK (0x80000U) -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR19_SHIFT (19U) -/*! CLR19 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , - * no change in DMA0_ITRIGEN1 register. - */ -#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR19_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR19_MASK) -/*! @} */ - -/*! @name DMA1_ITRIGEN - Enable DMA1 triggers */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN0_MASK (0x1U) -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN0_SHIFT (0U) -/*! ITRIGEN0 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN0_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN0_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN1_MASK (0x2U) -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN1_SHIFT (1U) -/*! ITRIGEN1 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN1_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN1_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN2_MASK (0x4U) -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN2_SHIFT (2U) -/*! ITRIGEN2 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN2_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN2_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN3_MASK (0x8U) -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN3_SHIFT (3U) -/*! ITRIGEN3 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN3_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN3_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN4_MASK (0x10U) -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN4_SHIFT (4U) -/*! ITRIGEN4 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN4_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN4_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN5_MASK (0x20U) -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN5_SHIFT (5U) -/*! ITRIGEN5 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN5_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN5_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN6_MASK (0x40U) -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN6_SHIFT (6U) -/*! ITRIGEN6 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN6_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN6_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN7_MASK (0x80U) -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN7_SHIFT (7U) -/*! ITRIGEN7 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN7_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN7_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN8_MASK (0x100U) -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN8_SHIFT (8U) -/*! ITRIGEN8 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN8_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN8_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN9_MASK (0x200U) -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN9_SHIFT (9U) -/*! ITRIGEN9 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN9_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN9_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN10_MASK (0x400U) -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN10_SHIFT (10U) -/*! ITRIGEN10 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN10_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN10_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN11_MASK (0x800U) -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN11_SHIFT (11U) -/*! ITRIGEN11 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN11_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN11_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN12_MASK (0x1000U) -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN12_SHIFT (12U) -/*! ITRIGEN12 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN12_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN12_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN13_MASK (0x2000U) -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN13_SHIFT (13U) -/*! ITRIGEN13 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN13_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN13_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN14_MASK (0x4000U) -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN14_SHIFT (14U) -/*! ITRIGEN14 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN14_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN14_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN15_MASK (0x8000U) -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN15_SHIFT (15U) -/*! ITRIGEN15 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN15_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN15_MASK) -/*! @} */ - -/*! @name DMA1_ITRIGEN_SET - Set bits in DMA1_ITRIGEN register */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIGEN_SET_SET0_MASK (0x1U) -#define INPUTMUX_DMA1_ITRIGEN_SET_SET0_SHIFT (0U) -/*! SET0 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_SET_SET0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET0_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET0_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_SET_SET1_MASK (0x2U) -#define INPUTMUX_DMA1_ITRIGEN_SET_SET1_SHIFT (1U) -/*! SET1 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_SET_SET1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET1_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET1_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_SET_SET2_MASK (0x4U) -#define INPUTMUX_DMA1_ITRIGEN_SET_SET2_SHIFT (2U) -/*! SET2 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_SET_SET2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET2_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET2_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_SET_SET3_MASK (0x8U) -#define INPUTMUX_DMA1_ITRIGEN_SET_SET3_SHIFT (3U) -/*! SET3 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_SET_SET3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET3_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET3_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_SET_SET4_MASK (0x10U) -#define INPUTMUX_DMA1_ITRIGEN_SET_SET4_SHIFT (4U) -/*! SET4 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_SET_SET4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET4_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET4_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_SET_SET5_MASK (0x20U) -#define INPUTMUX_DMA1_ITRIGEN_SET_SET5_SHIFT (5U) -/*! SET5 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_SET_SET5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET5_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET5_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_SET_SET6_MASK (0x40U) -#define INPUTMUX_DMA1_ITRIGEN_SET_SET6_SHIFT (6U) -/*! SET6 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_SET_SET6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET6_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET6_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_SET_SET7_MASK (0x80U) -#define INPUTMUX_DMA1_ITRIGEN_SET_SET7_SHIFT (7U) -/*! SET7 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_SET_SET7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET7_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET7_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_SET_SET8_MASK (0x100U) -#define INPUTMUX_DMA1_ITRIGEN_SET_SET8_SHIFT (8U) -/*! SET8 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_SET_SET8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET8_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET8_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_SET_SET9_MASK (0x200U) -#define INPUTMUX_DMA1_ITRIGEN_SET_SET9_SHIFT (9U) -/*! SET9 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_SET_SET9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET9_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET9_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_SET_SET10_MASK (0x400U) -#define INPUTMUX_DMA1_ITRIGEN_SET_SET10_SHIFT (10U) -/*! SET10 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_SET_SET10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET10_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET10_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_SET_SET11_MASK (0x800U) -#define INPUTMUX_DMA1_ITRIGEN_SET_SET11_SHIFT (11U) -/*! SET11 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_SET_SET11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET11_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET11_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_SET_SET12_MASK (0x1000U) -#define INPUTMUX_DMA1_ITRIGEN_SET_SET12_SHIFT (12U) -/*! SET12 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_SET_SET12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET12_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET12_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_SET_SET13_MASK (0x2000U) -#define INPUTMUX_DMA1_ITRIGEN_SET_SET13_SHIFT (13U) -/*! SET13 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_SET_SET13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET13_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET13_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_SET_SET14_MASK (0x4000U) -#define INPUTMUX_DMA1_ITRIGEN_SET_SET14_SHIFT (14U) -/*! SET14 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_SET_SET14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET14_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET14_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_SET_SET15_MASK (0x8000U) -#define INPUTMUX_DMA1_ITRIGEN_SET_SET15_SHIFT (15U) -/*! SET15 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_SET_SET15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET15_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET15_MASK) -/*! @} */ - -/*! @name DMA1_ITRIGEN_CLR - Clear bits in DMA1_ITRIGEN register */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR0_MASK (0x1U) -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR0_SHIFT (0U) -/*! CLR0 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR0_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR0_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR1_MASK (0x2U) -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR1_SHIFT (1U) -/*! CLR1 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR1_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR1_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR2_MASK (0x4U) -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR2_SHIFT (2U) -/*! CLR2 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR2_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR2_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR3_MASK (0x8U) -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR3_SHIFT (3U) -/*! CLR3 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR3_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR3_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR4_MASK (0x10U) -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR4_SHIFT (4U) -/*! CLR4 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR4_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR4_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR5_MASK (0x20U) -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR5_SHIFT (5U) -/*! CLR5 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR5_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR5_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR6_MASK (0x40U) -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR6_SHIFT (6U) -/*! CLR6 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR6_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR6_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR7_MASK (0x80U) -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR7_SHIFT (7U) -/*! CLR7 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR7_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR7_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR8_MASK (0x100U) -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR8_SHIFT (8U) -/*! CLR8 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR8_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR8_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR9_MASK (0x200U) -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR9_SHIFT (9U) -/*! CLR9 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR9_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR9_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR10_MASK (0x400U) -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR10_SHIFT (10U) -/*! CLR10 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR10_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR10_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR11_MASK (0x800U) -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR11_SHIFT (11U) -/*! CLR11 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR11_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR11_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR12_MASK (0x1000U) -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR12_SHIFT (12U) -/*! CLR12 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR12_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR12_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR13_MASK (0x2000U) -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR13_SHIFT (13U) -/*! CLR13 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR13_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR13_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR14_MASK (0x4000U) -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR14_SHIFT (14U) -/*! CLR14 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR14_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR14_MASK) - -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR15_MASK (0x8000U) -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR15_SHIFT (15U) -/*! CLR15 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register - */ -#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR15_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR15_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group INPUTMUX_Register_Masks */ - - -/* INPUTMUX - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE (0x50006000u) - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE_NS (0x40006000u) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS) - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS { INPUTMUX } - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX_BASE_NS } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS_NS { INPUTMUX_NS } -#else - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE (0x40006000u) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS { INPUTMUX } -#endif - -/*! - * @} - */ /* end of group INPUTMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- IOCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer - * @{ - */ - -/** IOCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t PIO[4][32]; /**< Analog/Digital I/O control for port..Digital I/O control for port, array offset: 0x0, array step: index*0x80, index2*0x4 */ -} IOCON_Type; - -/* ---------------------------------------------------------------------------- - -- IOCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Register_Masks IOCON Register Masks - * @{ - */ - -/*! @name PIO - Analog/Digital I/O control for port..Digital I/O control for port */ -/*! @{ */ - -#define IOCON_PIO_FUNC_MASK (0xFU) -#define IOCON_PIO_FUNC_SHIFT (0U) -/*! FUNC - Signal(function) select - */ -#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) - -#define IOCON_PIO_MODE_MASK (0x30U) -#define IOCON_PIO_MODE_SHIFT (4U) -/*! MODE - Mode select (on-chip pull-up/pull-down resistor control) - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) - -#define IOCON_PIO_SLEW_MASK (0x40U) -#define IOCON_PIO_SLEW_SHIFT (6U) -/*! SLEW - Driver slew rate - * 0b0..Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - * 0b1..Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - */ -#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) - -#define IOCON_PIO_INVERT_MASK (0x80U) -#define IOCON_PIO_INVERT_SHIFT (7U) -/*! INVERT - Invert polarity of input signal - * 0b0..Don't invert the signal. - * 0b1..Invert the signal. - */ -#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) - -#define IOCON_PIO_DIGIMODE_MASK (0x100U) -#define IOCON_PIO_DIGIMODE_SHIFT (8U) -/*! DIGIMODE - Select Digital mode - * 0b0..Disable digital mode. Digital input set to 0. - * 0b1..Enable Digital mode. Digital input is enabled. - */ -#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) - -#define IOCON_PIO_OD_MASK (0x200U) -#define IOCON_PIO_OD_SHIFT (9U) -/*! OD - Controls open-drain mode - * 0b0..Normal. Normal push-pull output - * 0b1..Open-drain. Simulated open-drain output (high drive disabled). - */ -#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) - -#define IOCON_PIO_ASW0_MASK (0x400U) -#define IOCON_PIO_ASW0_SHIFT (10U) -/*! ASW0 - Analog switch input control - * 0b0..Analog switch is open. (disable) - * 0b1..Analog switch is closed. (enable) - */ -#define IOCON_PIO_ASW0(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW0_SHIFT)) & IOCON_PIO_ASW0_MASK) - -#define IOCON_PIO_ASW1_MASK (0x800U) -#define IOCON_PIO_ASW1_SHIFT (11U) -/*! ASW1 - Analog switch input control - * 0b0..Analog switch is open. (disable) - * 0b1..Analog switch is closed. (enable) - */ -#define IOCON_PIO_ASW1(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW1_SHIFT)) & IOCON_PIO_ASW1_MASK) - -#define IOCON_PIO_SSEL_MASK (0x800U) -#define IOCON_PIO_SSEL_SHIFT (11U) -/*! SSEL - Supply Selection bit. - * 0b0..3V3 Signaling in I2C Mode. - * 0b1..1V8 Signaling in I2C Mode. - */ -#define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK) - -#define IOCON_PIO_FILTEROFF_MASK (0x1000U) -#define IOCON_PIO_FILTEROFF_SHIFT (12U) -/*! FILTEROFF - Controls input glitch filter - * 0b0..Filter enabled. - * 0b1..Filter disabled. - */ -#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) - -#define IOCON_PIO_ECS_MASK (0x2000U) -#define IOCON_PIO_ECS_SHIFT (13U) -/*! ECS - Pull-up current source enable in I2C mode - * 0b1..Enabled. Pull resistor is conencted. - * 0b0..Disabled. IO is in open drain cell. - */ -#define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK) - -#define IOCON_PIO_EGP_MASK (0x4000U) -#define IOCON_PIO_EGP_SHIFT (14U) -/*! EGP - Switch between GPIO mode and I2C mode - * 0b0..I2C mode - * 0b1..GPIO mode. - */ -#define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK) - -#define IOCON_PIO_I2CFILTER_MASK (0x8000U) -#define IOCON_PIO_I2CFILTER_SHIFT (15U) -/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. - * 0b0..I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. - * 0b1..I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. - */ -#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) -/*! @} */ - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT (4U) - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT2 (32U) - - -/*! - * @} - */ /* end of group IOCON_Register_Masks */ - - -/* IOCON - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral IOCON base address */ - #define IOCON_BASE (0x50001000u) - /** Peripheral IOCON base address */ - #define IOCON_BASE_NS (0x40001000u) - /** Peripheral IOCON base pointer */ - #define IOCON ((IOCON_Type *)IOCON_BASE) - /** Peripheral IOCON base pointer */ - #define IOCON_NS ((IOCON_Type *)IOCON_BASE_NS) - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS { IOCON_BASE } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS { IOCON } - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS_NS { IOCON_BASE_NS } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS_NS { IOCON_NS } -#else - /** Peripheral IOCON base address */ - #define IOCON_BASE (0x40001000u) - /** Peripheral IOCON base pointer */ - #define IOCON ((IOCON_Type *)IOCON_BASE) - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS { IOCON_BASE } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS { IOCON } -#endif - -/*! - * @} - */ /* end of group IOCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ITRC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ITRC_Peripheral_Access_Layer ITRC Peripheral Access Layer - * @{ - */ - -/** ITRC - Register Layout Typedef */ -typedef struct { - __IO uint32_t STATUS; /**< ITRC outputs and IN0 to IN15 Status, offset: 0x0 */ - uint8_t RESERVED_0[4]; - __IO uint32_t OUT0_SEL0; /**< ITRC_IRQ trigger Source IN0 to IN15 selector 0, offset: 0x8 */ - __IO uint32_t OUT0_SEL1; /**< ITRC_IRQ Trigger source IN0 to IN15 selector 1, offset: 0xC */ - __IO uint32_t OUT1_SEL0; /**< CSS_RESET Trigger source IN0 to IN15 selector 0, offset: 0x10 */ - __IO uint32_t OUT1_SEL1; /**< CSS_RESET Trigger source IN0 to IN15 selector 1, offset: 0x14 */ - __IO uint32_t OUT2_SEL0; /**< PUF_ZEROIZE Trigger source IN0 to IN15 selector 0, offset: 0x18 */ - __IO uint32_t OUT2_SEL1; /**< PUF_ZEROIZE Trigger source IN0 to IN15 selector 1, offset: 0x1C */ - __IO uint32_t OUT3_SEL0; /**< RAM_ZEROIZE Trigger source IN0 to IN15 selector 0, offset: 0x20 */ - __IO uint32_t OUT3_SEL1; /**< RAM_ZEROIZE Trigger source IN0 to IN15 selector 1, offset: 0x24 */ - __IO uint32_t OUT4_SEL0; /**< CHIP_RESET Trigger source IN0 to IN15 selector 0, offset: 0x28 */ - __IO uint32_t OUT4_SEL1; /**< CHIP_RESET Trigger source IN0 to IN15 selector 1, offset: 0x2C */ - __IO uint32_t OUT5_SEL0; /**< TMPR_OUT0 IN0 to IN15 selector 0, offset: 0x30 */ - __IO uint32_t OUT5_SEL1; /**< TMPR_OUT0 IN0 to IN15 selector 1, offset: 0x34 */ - __IO uint32_t OUT6_SEL0; /**< TMPR_OUT1 IN0 to IN15 selector 0, offset: 0x38 */ - __IO uint32_t OUT6_SEL1; /**< TMPR_OUT1 IN0 to IN15 selector 1, offset: 0x3C */ - uint8_t RESERVED_1[176]; - __O uint32_t SW_EVENT0; /**< Software event 0, offset: 0xF0 */ - __O uint32_t SW_EVENT1; /**< Software event 1, offset: 0xF4 */ -} ITRC_Type; - -/* ---------------------------------------------------------------------------- - -- ITRC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ITRC_Register_Masks ITRC Register Masks - * @{ - */ - -/*! @name STATUS - ITRC outputs and IN0 to IN15 Status */ -/*! @{ */ - -#define ITRC_STATUS_IN0_STATUS_MASK (0x1U) -#define ITRC_STATUS_IN0_STATUS_SHIFT (0U) -/*! IN0_STATUS - Digital glitch detector event occurred. - */ -#define ITRC_STATUS_IN0_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN0_STATUS_SHIFT)) & ITRC_STATUS_IN0_STATUS_MASK) - -#define ITRC_STATUS_IN1_STATUS_MASK (0x2U) -#define ITRC_STATUS_IN1_STATUS_SHIFT (1U) -/*! IN1_STATUS - Tamper pins logic detected an event. - */ -#define ITRC_STATUS_IN1_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN1_STATUS_SHIFT)) & ITRC_STATUS_IN1_STATUS_MASK) - -#define ITRC_STATUS_IN2_STATUS_MASK (0x4U) -#define ITRC_STATUS_IN2_STATUS_SHIFT (2U) -/*! IN2_STATUS - Code watchdog detected an code execution anomaly. - */ -#define ITRC_STATUS_IN2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN2_STATUS_SHIFT)) & ITRC_STATUS_IN2_STATUS_MASK) - -#define ITRC_STATUS_IN3_STATUS_MASK (0x8U) -#define ITRC_STATUS_IN3_STATUS_SHIFT (3U) -/*! IN3_STATUS - Low voltage event (BoD) detected on VDD_MAIN rail. - */ -#define ITRC_STATUS_IN3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN3_STATUS_SHIFT)) & ITRC_STATUS_IN3_STATUS_MASK) - -#define ITRC_STATUS_IN4_STATUS_MASK (0x10U) -#define ITRC_STATUS_IN4_STATUS_SHIFT (4U) -/*! IN4_STATUS - Low voltage event (BoD) detected on VDD_CORE rail. - */ -#define ITRC_STATUS_IN4_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN4_STATUS_SHIFT)) & ITRC_STATUS_IN4_STATUS_MASK) - -#define ITRC_STATUS_IN5_STATUS_MASK (0x20U) -#define ITRC_STATUS_IN5_STATUS_SHIFT (5U) -/*! IN5_STATUS - Watch Dog timer event occurred. - */ -#define ITRC_STATUS_IN5_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN5_STATUS_SHIFT)) & ITRC_STATUS_IN5_STATUS_MASK) - -#define ITRC_STATUS_IN6_STATUS_MASK (0x40U) -#define ITRC_STATUS_IN6_STATUS_SHIFT (6U) -/*! IN6_STATUS - Flash ECC mismatch event occurred. - */ -#define ITRC_STATUS_IN6_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN6_STATUS_SHIFT)) & ITRC_STATUS_IN6_STATUS_MASK) - -#define ITRC_STATUS_IN7_STATUS_MASK (0x80U) -#define ITRC_STATUS_IN7_STATUS_SHIFT (7U) -/*! IN7_STATUS - AHB secure bus checkers detected illegal access. - */ -#define ITRC_STATUS_IN7_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN7_STATUS_SHIFT)) & ITRC_STATUS_IN7_STATUS_MASK) - -#define ITRC_STATUS_IN8_STATUS_MASK (0x100U) -#define ITRC_STATUS_IN8_STATUS_SHIFT (8U) -/*! IN8_STATUS - CSS error event occurred. - */ -#define ITRC_STATUS_IN8_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN8_STATUS_SHIFT)) & ITRC_STATUS_IN8_STATUS_MASK) - -#define ITRC_STATUS_IN10_STATUS_MASK (0x400U) -#define ITRC_STATUS_IN10_STATUS_SHIFT (10U) -/*! IN10_STATUS - PKC module detected an error event. - */ -#define ITRC_STATUS_IN10_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN10_STATUS_SHIFT)) & ITRC_STATUS_IN10_STATUS_MASK) - -#define ITRC_STATUS_IN14_STATUS_MASK (0x4000U) -#define ITRC_STATUS_IN14_STATUS_SHIFT (14U) -/*! IN14_STATUS - Software event 0 occurred. - */ -#define ITRC_STATUS_IN14_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN14_STATUS_SHIFT)) & ITRC_STATUS_IN14_STATUS_MASK) - -#define ITRC_STATUS_IN15_STATUS_MASK (0x8000U) -#define ITRC_STATUS_IN15_STATUS_SHIFT (15U) -/*! IN15_STATUS - Software event 1 occurred. - */ -#define ITRC_STATUS_IN15_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN15_STATUS_SHIFT)) & ITRC_STATUS_IN15_STATUS_MASK) - -#define ITRC_STATUS_OUT0_STATUS_MASK (0x10000U) -#define ITRC_STATUS_OUT0_STATUS_SHIFT (16U) -/*! OUT0_STATUS - ITRC triggered ITRC_IRQ output. - */ -#define ITRC_STATUS_OUT0_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT0_STATUS_SHIFT)) & ITRC_STATUS_OUT0_STATUS_MASK) - -#define ITRC_STATUS_OUT1_STATUS_MASK (0x20000U) -#define ITRC_STATUS_OUT1_STATUS_SHIFT (17U) -/*! OUT1_STATUS - ITRC triggered CSS_RESET to clear CSS key store. - */ -#define ITRC_STATUS_OUT1_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT1_STATUS_SHIFT)) & ITRC_STATUS_OUT1_STATUS_MASK) - -#define ITRC_STATUS_OUT2_STATUS_MASK (0x40000U) -#define ITRC_STATUS_OUT2_STATUS_SHIFT (18U) -/*! OUT2_STATUS - ITRC triggered PUF_ZEROIZE to clear PUF key store and RAM. - */ -#define ITRC_STATUS_OUT2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT2_STATUS_SHIFT)) & ITRC_STATUS_OUT2_STATUS_MASK) - -#define ITRC_STATUS_OUT3_STATUS_MASK (0x80000U) -#define ITRC_STATUS_OUT3_STATUS_SHIFT (19U) -/*! OUT3_STATUS - ITRC triggered RAM_ZEROIZE to clear retention and PKC RAM contents. - */ -#define ITRC_STATUS_OUT3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT3_STATUS_SHIFT)) & ITRC_STATUS_OUT3_STATUS_MASK) - -#define ITRC_STATUS_OUT4_STATUS_MASK (0x100000U) -#define ITRC_STATUS_OUT4_STATUS_SHIFT (20U) -/*! OUT4_STATUS - ITRC triggered CHIP_RESET to reset the chip after all other response process finished. - */ -#define ITRC_STATUS_OUT4_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT4_STATUS_SHIFT)) & ITRC_STATUS_OUT4_STATUS_MASK) - -#define ITRC_STATUS_OUT5_STATUS_MASK (0x200000U) -#define ITRC_STATUS_OUT5_STATUS_SHIFT (21U) -/*! OUT5_STATUS - ITRC triggered TMPR_OUT internal signal connected to various on-chip multiplexers. - */ -#define ITRC_STATUS_OUT5_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT5_STATUS_SHIFT)) & ITRC_STATUS_OUT5_STATUS_MASK) -/*! @} */ - -/*! @name OUT0_SEL0 - ITRC_IRQ trigger Source IN0 to IN15 selector 0 */ -/*! @{ */ - -#define ITRC_OUT0_SEL0_IN0_SEL0_MASK (0x3U) -#define ITRC_OUT0_SEL0_IN0_SEL0_SHIFT (0U) -/*! IN0_SEL0 - Selects digital glitch detector as a trigger source. - */ -#define ITRC_OUT0_SEL0_IN0_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN0_SEL0_MASK) - -#define ITRC_OUT0_SEL0_IN1_SEL0_MASK (0xCU) -#define ITRC_OUT0_SEL0_IN1_SEL0_SHIFT (2U) -/*! IN1_SEL0 - Selects tamper pin event as a trigger source. - */ -#define ITRC_OUT0_SEL0_IN1_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN1_SEL0_MASK) - -#define ITRC_OUT0_SEL0_IN2_SEL0_MASK (0x30U) -#define ITRC_OUT0_SEL0_IN2_SEL0_SHIFT (4U) -/*! IN2_SEL0 - Selects Code Watch Dog event as a trigger source. - */ -#define ITRC_OUT0_SEL0_IN2_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN2_SEL0_MASK) - -#define ITRC_OUT0_SEL0_IN3_SEL0_MASK (0xC0U) -#define ITRC_OUT0_SEL0_IN3_SEL0_SHIFT (6U) -/*! IN3_SEL0 - Selects low-voltage event on VDD_MAIN rail as a trigger source. - */ -#define ITRC_OUT0_SEL0_IN3_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN3_SEL0_MASK) - -#define ITRC_OUT0_SEL0_IN4_SEL0_MASK (0x300U) -#define ITRC_OUT0_SEL0_IN4_SEL0_SHIFT (8U) -/*! IN4_SEL0 - Selects low-voltage event on VDD_CORE rail as a trigger source. - */ -#define ITRC_OUT0_SEL0_IN4_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN4_SEL0_MASK) - -#define ITRC_OUT0_SEL0_IN5_SEL0_MASK (0xC00U) -#define ITRC_OUT0_SEL0_IN5_SEL0_SHIFT (10U) -/*! IN5_SEL0 - Selects Watch Dog timer event as a trigger source. - */ -#define ITRC_OUT0_SEL0_IN5_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN5_SEL0_MASK) - -#define ITRC_OUT0_SEL0_IN6_SEL0_MASK (0x3000U) -#define ITRC_OUT0_SEL0_IN6_SEL0_SHIFT (12U) -/*! IN6_SEL0 - Selects Flash ECC mismatch event as a trigger source. - */ -#define ITRC_OUT0_SEL0_IN6_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN6_SEL0_MASK) - -#define ITRC_OUT0_SEL0_IN7_SEL0_MASK (0xC000U) -#define ITRC_OUT0_SEL0_IN7_SEL0_SHIFT (14U) -/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source. - */ -#define ITRC_OUT0_SEL0_IN7_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN7_SEL0_MASK) - -#define ITRC_OUT0_SEL0_IN8_SEL0_MASK (0x30000U) -#define ITRC_OUT0_SEL0_IN8_SEL0_SHIFT (16U) -/*! IN8_SEL0 - Selects CSS error event as a trigger source. - */ -#define ITRC_OUT0_SEL0_IN8_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN8_SEL0_MASK) - -#define ITRC_OUT0_SEL0_IN10_SEL0_MASK (0x300000U) -#define ITRC_OUT0_SEL0_IN10_SEL0_SHIFT (20U) -/*! IN10_SEL0 - Selects PKC error event as a trigger source. - */ -#define ITRC_OUT0_SEL0_IN10_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN10_SEL0_MASK) - -#define ITRC_OUT0_SEL0_IN14_SEL0_MASK (0x30000000U) -#define ITRC_OUT0_SEL0_IN14_SEL0_SHIFT (28U) -/*! IN14_SEL0 - Selects software event 0 as a trigger source. - */ -#define ITRC_OUT0_SEL0_IN14_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN14_SEL0_MASK) - -#define ITRC_OUT0_SEL0_IN15_SEL0_MASK (0xC0000000U) -#define ITRC_OUT0_SEL0_IN15_SEL0_SHIFT (30U) -/*! IN15_SEL0 - Selects software event 1 as a trigger source. - */ -#define ITRC_OUT0_SEL0_IN15_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN15_SEL0_MASK) -/*! @} */ - -/*! @name OUT0_SEL1 - ITRC_IRQ Trigger source IN0 to IN15 selector 1 */ -/*! @{ */ - -#define ITRC_OUT0_SEL1_IN0_SEL1_MASK (0x3U) -#define ITRC_OUT0_SEL1_IN0_SEL1_SHIFT (0U) -/*! IN0_SEL1 - Selects digital glitch detector as a trigger source. - */ -#define ITRC_OUT0_SEL1_IN0_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN0_SEL1_MASK) - -#define ITRC_OUT0_SEL1_IN1_SEL1_MASK (0xCU) -#define ITRC_OUT0_SEL1_IN1_SEL1_SHIFT (2U) -/*! IN1_SEL1 - Selects tamper pin event as a trigger source. - */ -#define ITRC_OUT0_SEL1_IN1_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN1_SEL1_MASK) - -#define ITRC_OUT0_SEL1_IN2_SEL1_MASK (0x30U) -#define ITRC_OUT0_SEL1_IN2_SEL1_SHIFT (4U) -/*! IN2_SEL1 - Selects Code Watch Dog event as a trigger source. - */ -#define ITRC_OUT0_SEL1_IN2_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN2_SEL1_MASK) - -#define ITRC_OUT0_SEL1_IN3_SEL1_MASK (0xC0U) -#define ITRC_OUT0_SEL1_IN3_SEL1_SHIFT (6U) -/*! IN3_SEL1 - Selects low-voltage event on VDD_MAIN rail as a trigger source. - */ -#define ITRC_OUT0_SEL1_IN3_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN3_SEL1_MASK) - -#define ITRC_OUT0_SEL1_IN4_SEL1_MASK (0x300U) -#define ITRC_OUT0_SEL1_IN4_SEL1_SHIFT (8U) -/*! IN4_SEL1 - Selects low-voltage event on VDD_CORE rail as a trigger source. - */ -#define ITRC_OUT0_SEL1_IN4_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN4_SEL1_MASK) - -#define ITRC_OUT0_SEL1_IN5_SEL1_MASK (0xC00U) -#define ITRC_OUT0_SEL1_IN5_SEL1_SHIFT (10U) -/*! IN5_SEL1 - Selects Watch Dog timer event as a trigger source. - */ -#define ITRC_OUT0_SEL1_IN5_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN5_SEL1_MASK) - -#define ITRC_OUT0_SEL1_IN6_SEL1_MASK (0x3000U) -#define ITRC_OUT0_SEL1_IN6_SEL1_SHIFT (12U) -/*! IN6_SEL1 - Selects Flash ECC mismatch event as a trigger source. - */ -#define ITRC_OUT0_SEL1_IN6_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN6_SEL1_MASK) - -#define ITRC_OUT0_SEL1_IN7_SEL1_MASK (0xC000U) -#define ITRC_OUT0_SEL1_IN7_SEL1_SHIFT (14U) -/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source. - */ -#define ITRC_OUT0_SEL1_IN7_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN7_SEL1_MASK) - -#define ITRC_OUT0_SEL1_IN8_SEL1_MASK (0x30000U) -#define ITRC_OUT0_SEL1_IN8_SEL1_SHIFT (16U) -/*! IN8_SEL1 - Selects CSS error event as a trigger source. - */ -#define ITRC_OUT0_SEL1_IN8_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN8_SEL1_MASK) - -#define ITRC_OUT0_SEL1_IN10_SEL1_MASK (0x300000U) -#define ITRC_OUT0_SEL1_IN10_SEL1_SHIFT (20U) -/*! IN10_SEL1 - Selects PKC error event as a trigger source. - */ -#define ITRC_OUT0_SEL1_IN10_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN10_SEL1_MASK) - -#define ITRC_OUT0_SEL1_IN14_SEL1_MASK (0x30000000U) -#define ITRC_OUT0_SEL1_IN14_SEL1_SHIFT (28U) -/*! IN14_SEL1 - Selects software event 0 as a trigger source. - */ -#define ITRC_OUT0_SEL1_IN14_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN14_SEL1_MASK) - -#define ITRC_OUT0_SEL1_IN15_SEL1_MASK (0xC0000000U) -#define ITRC_OUT0_SEL1_IN15_SEL1_SHIFT (30U) -/*! IN15_SEL1 - Selects software event 1 as a trigger source. - */ -#define ITRC_OUT0_SEL1_IN15_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN15_SEL1_MASK) -/*! @} */ - -/*! @name OUT1_SEL0 - CSS_RESET Trigger source IN0 to IN15 selector 0 */ -/*! @{ */ - -#define ITRC_OUT1_SEL0_IN0_SEL0_MASK (0x3U) -#define ITRC_OUT1_SEL0_IN0_SEL0_SHIFT (0U) -/*! IN0_SEL0 - CSS_RESET Trigger source selector 0 register. - */ -#define ITRC_OUT1_SEL0_IN0_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN0_SEL0_MASK) - -#define ITRC_OUT1_SEL0_IN1_SEL0_MASK (0xCU) -#define ITRC_OUT1_SEL0_IN1_SEL0_SHIFT (2U) -/*! IN1_SEL0 - Selects tamper pin event as a trigger source. - */ -#define ITRC_OUT1_SEL0_IN1_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN1_SEL0_MASK) - -#define ITRC_OUT1_SEL0_IN2_SEL0_MASK (0x30U) -#define ITRC_OUT1_SEL0_IN2_SEL0_SHIFT (4U) -/*! IN2_SEL0 - Selects Code Watch Dog event as a trigger source. - */ -#define ITRC_OUT1_SEL0_IN2_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN2_SEL0_MASK) - -#define ITRC_OUT1_SEL0_IN3_SEL0_MASK (0xC0U) -#define ITRC_OUT1_SEL0_IN3_SEL0_SHIFT (6U) -/*! IN3_SEL0 - Selects low-voltage event on VDD_MAIN rail as a trigger source. - */ -#define ITRC_OUT1_SEL0_IN3_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN3_SEL0_MASK) - -#define ITRC_OUT1_SEL0_IN4_SEL0_MASK (0x300U) -#define ITRC_OUT1_SEL0_IN4_SEL0_SHIFT (8U) -/*! IN4_SEL0 - Selects low-voltage event on VDD_CORE rail as a trigger source. - */ -#define ITRC_OUT1_SEL0_IN4_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN4_SEL0_MASK) - -#define ITRC_OUT1_SEL0_IN5_SEL0_MASK (0xC00U) -#define ITRC_OUT1_SEL0_IN5_SEL0_SHIFT (10U) -/*! IN5_SEL0 - Selects Watch Dog timer event as a trigger source. - */ -#define ITRC_OUT1_SEL0_IN5_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN5_SEL0_MASK) - -#define ITRC_OUT1_SEL0_IN6_SEL0_MASK (0x3000U) -#define ITRC_OUT1_SEL0_IN6_SEL0_SHIFT (12U) -/*! IN6_SEL0 - Selects Flash ECC mismatch event as a trigger source. - */ -#define ITRC_OUT1_SEL0_IN6_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN6_SEL0_MASK) - -#define ITRC_OUT1_SEL0_IN7_SEL0_MASK (0xC000U) -#define ITRC_OUT1_SEL0_IN7_SEL0_SHIFT (14U) -/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source. - */ -#define ITRC_OUT1_SEL0_IN7_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN7_SEL0_MASK) - -#define ITRC_OUT1_SEL0_IN8_SEL0_MASK (0x30000U) -#define ITRC_OUT1_SEL0_IN8_SEL0_SHIFT (16U) -/*! IN8_SEL0 - Selects CSS error event as a trigger source. - */ -#define ITRC_OUT1_SEL0_IN8_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN8_SEL0_MASK) - -#define ITRC_OUT1_SEL0_IN10_SEL0_MASK (0x300000U) -#define ITRC_OUT1_SEL0_IN10_SEL0_SHIFT (20U) -/*! IN10_SEL0 - Selects PKC error event as a trigger source. - */ -#define ITRC_OUT1_SEL0_IN10_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN10_SEL0_MASK) - -#define ITRC_OUT1_SEL0_IN14_SEL0_MASK (0x30000000U) -#define ITRC_OUT1_SEL0_IN14_SEL0_SHIFT (28U) -/*! IN14_SEL0 - Selects software event 0 as a trigger source. - */ -#define ITRC_OUT1_SEL0_IN14_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN14_SEL0_MASK) - -#define ITRC_OUT1_SEL0_IN15_SEL0_MASK (0xC0000000U) -#define ITRC_OUT1_SEL0_IN15_SEL0_SHIFT (30U) -/*! IN15_SEL0 - Selects software event 1 as a trigger source. - */ -#define ITRC_OUT1_SEL0_IN15_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN15_SEL0_MASK) -/*! @} */ - -/*! @name OUT1_SEL1 - CSS_RESET Trigger source IN0 to IN15 selector 1 */ -/*! @{ */ - -#define ITRC_OUT1_SEL1_IN0_SEL1_MASK (0x3U) -#define ITRC_OUT1_SEL1_IN0_SEL1_SHIFT (0U) -/*! IN0_SEL1 - Selects digital glitch detector as a trigger source. - */ -#define ITRC_OUT1_SEL1_IN0_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN0_SEL1_MASK) - -#define ITRC_OUT1_SEL1_IN1_SEL1_MASK (0xCU) -#define ITRC_OUT1_SEL1_IN1_SEL1_SHIFT (2U) -/*! IN1_SEL1 - Selects tamper pin event as a trigger source. - */ -#define ITRC_OUT1_SEL1_IN1_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN1_SEL1_MASK) - -#define ITRC_OUT1_SEL1_IN2_SEL1_MASK (0x30U) -#define ITRC_OUT1_SEL1_IN2_SEL1_SHIFT (4U) -/*! IN2_SEL1 - Selects Code Watch Dog event as a trigger source. - */ -#define ITRC_OUT1_SEL1_IN2_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN2_SEL1_MASK) - -#define ITRC_OUT1_SEL1_IN3_SEL1_MASK (0xC0U) -#define ITRC_OUT1_SEL1_IN3_SEL1_SHIFT (6U) -/*! IN3_SEL1 - Selects low-voltage event on VDD_MAIN rail as a trigger source. - */ -#define ITRC_OUT1_SEL1_IN3_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN3_SEL1_MASK) - -#define ITRC_OUT1_SEL1_IN4_SEL1_MASK (0x300U) -#define ITRC_OUT1_SEL1_IN4_SEL1_SHIFT (8U) -/*! IN4_SEL1 - Selects low-voltage event on VDD_CORE rail as a trigger source. - */ -#define ITRC_OUT1_SEL1_IN4_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN4_SEL1_MASK) - -#define ITRC_OUT1_SEL1_IN5_SEL1_MASK (0xC00U) -#define ITRC_OUT1_SEL1_IN5_SEL1_SHIFT (10U) -/*! IN5_SEL1 - Selects Watch Dog timer event as a trigger source. - */ -#define ITRC_OUT1_SEL1_IN5_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN5_SEL1_MASK) - -#define ITRC_OUT1_SEL1_IN6_SEL1_MASK (0x3000U) -#define ITRC_OUT1_SEL1_IN6_SEL1_SHIFT (12U) -/*! IN6_SEL1 - Selects Flash ECC mismatch event as a trigger source. - */ -#define ITRC_OUT1_SEL1_IN6_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN6_SEL1_MASK) - -#define ITRC_OUT1_SEL1_IN7_SEL1_MASK (0xC000U) -#define ITRC_OUT1_SEL1_IN7_SEL1_SHIFT (14U) -/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source. - */ -#define ITRC_OUT1_SEL1_IN7_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN7_SEL1_MASK) - -#define ITRC_OUT1_SEL1_IN8_SEL1_MASK (0x30000U) -#define ITRC_OUT1_SEL1_IN8_SEL1_SHIFT (16U) -/*! IN8_SEL1 - Selects CSS error event as a trigger source. - */ -#define ITRC_OUT1_SEL1_IN8_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN8_SEL1_MASK) - -#define ITRC_OUT1_SEL1_IN10_SEL1_MASK (0x300000U) -#define ITRC_OUT1_SEL1_IN10_SEL1_SHIFT (20U) -/*! IN10_SEL1 - Selects PKC error event as a trigger source. - */ -#define ITRC_OUT1_SEL1_IN10_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN10_SEL1_MASK) - -#define ITRC_OUT1_SEL1_IN14_SEL1_MASK (0x30000000U) -#define ITRC_OUT1_SEL1_IN14_SEL1_SHIFT (28U) -/*! IN14_SEL1 - Selects software event 0 as a trigger source. - */ -#define ITRC_OUT1_SEL1_IN14_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN14_SEL1_MASK) - -#define ITRC_OUT1_SEL1_IN15_SEL1_MASK (0xC0000000U) -#define ITRC_OUT1_SEL1_IN15_SEL1_SHIFT (30U) -/*! IN15_SEL1 - Selects software event 1 as a trigger source. - */ -#define ITRC_OUT1_SEL1_IN15_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN15_SEL1_MASK) -/*! @} */ - -/*! @name OUT2_SEL0 - PUF_ZEROIZE Trigger source IN0 to IN15 selector 0 */ -/*! @{ */ - -#define ITRC_OUT2_SEL0_IN0_SEL0_MASK (0x3U) -#define ITRC_OUT2_SEL0_IN0_SEL0_SHIFT (0U) -/*! IN0_SEL0 - CSS_RESET Trigger source selector 0 register. - */ -#define ITRC_OUT2_SEL0_IN0_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN0_SEL0_MASK) - -#define ITRC_OUT2_SEL0_IN1_SEL0_MASK (0xCU) -#define ITRC_OUT2_SEL0_IN1_SEL0_SHIFT (2U) -/*! IN1_SEL0 - Selects tamper pin event as a trigger source. - */ -#define ITRC_OUT2_SEL0_IN1_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN1_SEL0_MASK) - -#define ITRC_OUT2_SEL0_IN2_SEL0_MASK (0x30U) -#define ITRC_OUT2_SEL0_IN2_SEL0_SHIFT (4U) -/*! IN2_SEL0 - Selects Code Watch Dog event as a trigger source. - */ -#define ITRC_OUT2_SEL0_IN2_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN2_SEL0_MASK) - -#define ITRC_OUT2_SEL0_IN3_SEL0_MASK (0xC0U) -#define ITRC_OUT2_SEL0_IN3_SEL0_SHIFT (6U) -/*! IN3_SEL0 - Selects low-voltage event on VDD_MAIN rail as a trigger source. - */ -#define ITRC_OUT2_SEL0_IN3_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN3_SEL0_MASK) - -#define ITRC_OUT2_SEL0_IN4_SEL0_MASK (0x300U) -#define ITRC_OUT2_SEL0_IN4_SEL0_SHIFT (8U) -/*! IN4_SEL0 - Selects low-voltage event on VDD_CORE rail as a trigger source. - */ -#define ITRC_OUT2_SEL0_IN4_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN4_SEL0_MASK) - -#define ITRC_OUT2_SEL0_IN5_SEL0_MASK (0xC00U) -#define ITRC_OUT2_SEL0_IN5_SEL0_SHIFT (10U) -/*! IN5_SEL0 - Selects Watch Dog timer event as a trigger source. - */ -#define ITRC_OUT2_SEL0_IN5_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN5_SEL0_MASK) - -#define ITRC_OUT2_SEL0_IN6_SEL0_MASK (0x3000U) -#define ITRC_OUT2_SEL0_IN6_SEL0_SHIFT (12U) -/*! IN6_SEL0 - Selects Flash ECC mismatch event as a trigger source. - */ -#define ITRC_OUT2_SEL0_IN6_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN6_SEL0_MASK) - -#define ITRC_OUT2_SEL0_IN7_SEL0_MASK (0xC000U) -#define ITRC_OUT2_SEL0_IN7_SEL0_SHIFT (14U) -/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source. - */ -#define ITRC_OUT2_SEL0_IN7_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN7_SEL0_MASK) - -#define ITRC_OUT2_SEL0_IN8_SEL0_MASK (0x30000U) -#define ITRC_OUT2_SEL0_IN8_SEL0_SHIFT (16U) -/*! IN8_SEL0 - Selects CSS error event as a trigger source. - */ -#define ITRC_OUT2_SEL0_IN8_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN8_SEL0_MASK) - -#define ITRC_OUT2_SEL0_IN10_SEL0_MASK (0x300000U) -#define ITRC_OUT2_SEL0_IN10_SEL0_SHIFT (20U) -/*! IN10_SEL0 - Selects PKC error event as a trigger source. - */ -#define ITRC_OUT2_SEL0_IN10_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN10_SEL0_MASK) - -#define ITRC_OUT2_SEL0_IN14_SEL0_MASK (0x30000000U) -#define ITRC_OUT2_SEL0_IN14_SEL0_SHIFT (28U) -/*! IN14_SEL0 - Selects software event 0 as a trigger source. - */ -#define ITRC_OUT2_SEL0_IN14_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN14_SEL0_MASK) - -#define ITRC_OUT2_SEL0_IN15_SEL0_MASK (0xC0000000U) -#define ITRC_OUT2_SEL0_IN15_SEL0_SHIFT (30U) -/*! IN15_SEL0 - Selects software event 1 as a trigger source. - */ -#define ITRC_OUT2_SEL0_IN15_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN15_SEL0_MASK) -/*! @} */ - -/*! @name OUT2_SEL1 - PUF_ZEROIZE Trigger source IN0 to IN15 selector 1 */ -/*! @{ */ - -#define ITRC_OUT2_SEL1_IN0_SEL1_MASK (0x3U) -#define ITRC_OUT2_SEL1_IN0_SEL1_SHIFT (0U) -/*! IN0_SEL1 - Selects digital glitch detector as a trigger source. - */ -#define ITRC_OUT2_SEL1_IN0_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN0_SEL1_MASK) - -#define ITRC_OUT2_SEL1_IN1_SEL1_MASK (0xCU) -#define ITRC_OUT2_SEL1_IN1_SEL1_SHIFT (2U) -/*! IN1_SEL1 - Selects tamper pin event as a trigger source. - */ -#define ITRC_OUT2_SEL1_IN1_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN1_SEL1_MASK) - -#define ITRC_OUT2_SEL1_IN2_SEL1_MASK (0x30U) -#define ITRC_OUT2_SEL1_IN2_SEL1_SHIFT (4U) -/*! IN2_SEL1 - Selects Code Watch Dog event as a trigger source. - */ -#define ITRC_OUT2_SEL1_IN2_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN2_SEL1_MASK) - -#define ITRC_OUT2_SEL1_IN3_SEL1_MASK (0xC0U) -#define ITRC_OUT2_SEL1_IN3_SEL1_SHIFT (6U) -/*! IN3_SEL1 - Selects low-voltage event on VDD_MAIN rail as a trigger source. - */ -#define ITRC_OUT2_SEL1_IN3_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN3_SEL1_MASK) - -#define ITRC_OUT2_SEL1_IN4_SEL1_MASK (0x300U) -#define ITRC_OUT2_SEL1_IN4_SEL1_SHIFT (8U) -/*! IN4_SEL1 - Selects low-voltage event on VDD_CORE rail as a trigger source. - */ -#define ITRC_OUT2_SEL1_IN4_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN4_SEL1_MASK) - -#define ITRC_OUT2_SEL1_IN5_SEL1_MASK (0xC00U) -#define ITRC_OUT2_SEL1_IN5_SEL1_SHIFT (10U) -/*! IN5_SEL1 - Selects Watch Dog timer event as a trigger source. - */ -#define ITRC_OUT2_SEL1_IN5_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN5_SEL1_MASK) - -#define ITRC_OUT2_SEL1_IN6_SEL1_MASK (0x3000U) -#define ITRC_OUT2_SEL1_IN6_SEL1_SHIFT (12U) -/*! IN6_SEL1 - Selects Flash ECC mismatch event as a trigger source. - */ -#define ITRC_OUT2_SEL1_IN6_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN6_SEL1_MASK) - -#define ITRC_OUT2_SEL1_IN7_SEL1_MASK (0xC000U) -#define ITRC_OUT2_SEL1_IN7_SEL1_SHIFT (14U) -/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source. - */ -#define ITRC_OUT2_SEL1_IN7_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN7_SEL1_MASK) - -#define ITRC_OUT2_SEL1_IN8_SEL1_MASK (0x30000U) -#define ITRC_OUT2_SEL1_IN8_SEL1_SHIFT (16U) -/*! IN8_SEL1 - Selects CSS error event as a trigger source. - */ -#define ITRC_OUT2_SEL1_IN8_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN8_SEL1_MASK) - -#define ITRC_OUT2_SEL1_IN10_SEL1_MASK (0x300000U) -#define ITRC_OUT2_SEL1_IN10_SEL1_SHIFT (20U) -/*! IN10_SEL1 - Selects PKC error event as a trigger source. - */ -#define ITRC_OUT2_SEL1_IN10_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN10_SEL1_MASK) - -#define ITRC_OUT2_SEL1_IN14_SEL1_MASK (0x30000000U) -#define ITRC_OUT2_SEL1_IN14_SEL1_SHIFT (28U) -/*! IN14_SEL1 - Selects software event 0 as a trigger source. - */ -#define ITRC_OUT2_SEL1_IN14_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN14_SEL1_MASK) - -#define ITRC_OUT2_SEL1_IN15_SEL1_MASK (0xC0000000U) -#define ITRC_OUT2_SEL1_IN15_SEL1_SHIFT (30U) -/*! IN15_SEL1 - Selects software event 1 as a trigger source. - */ -#define ITRC_OUT2_SEL1_IN15_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN15_SEL1_MASK) -/*! @} */ - -/*! @name OUT3_SEL0 - RAM_ZEROIZE Trigger source IN0 to IN15 selector 0 */ -/*! @{ */ - -#define ITRC_OUT3_SEL0_IN0_SEL0_MASK (0x3U) -#define ITRC_OUT3_SEL0_IN0_SEL0_SHIFT (0U) -/*! IN0_SEL0 - CSS_RESET Trigger source selector 0 register. - */ -#define ITRC_OUT3_SEL0_IN0_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN0_SEL0_MASK) - -#define ITRC_OUT3_SEL0_IN1_SEL0_MASK (0xCU) -#define ITRC_OUT3_SEL0_IN1_SEL0_SHIFT (2U) -/*! IN1_SEL0 - Selects tamper pin event as a trigger source. - */ -#define ITRC_OUT3_SEL0_IN1_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN1_SEL0_MASK) - -#define ITRC_OUT3_SEL0_IN2_SEL0_MASK (0x30U) -#define ITRC_OUT3_SEL0_IN2_SEL0_SHIFT (4U) -/*! IN2_SEL0 - Selects Code Watch Dog event as a trigger source. - */ -#define ITRC_OUT3_SEL0_IN2_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN2_SEL0_MASK) - -#define ITRC_OUT3_SEL0_IN3_SEL0_MASK (0xC0U) -#define ITRC_OUT3_SEL0_IN3_SEL0_SHIFT (6U) -/*! IN3_SEL0 - Selects low-voltage event on VDD_MAIN rail as a trigger source. - */ -#define ITRC_OUT3_SEL0_IN3_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN3_SEL0_MASK) - -#define ITRC_OUT3_SEL0_IN4_SEL0_MASK (0x300U) -#define ITRC_OUT3_SEL0_IN4_SEL0_SHIFT (8U) -/*! IN4_SEL0 - Selects low-voltage event on VDD_CORE rail as a trigger source. - */ -#define ITRC_OUT3_SEL0_IN4_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN4_SEL0_MASK) - -#define ITRC_OUT3_SEL0_IN5_SEL0_MASK (0xC00U) -#define ITRC_OUT3_SEL0_IN5_SEL0_SHIFT (10U) -/*! IN5_SEL0 - Selects Watch Dog timer event as a trigger source. - */ -#define ITRC_OUT3_SEL0_IN5_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN5_SEL0_MASK) - -#define ITRC_OUT3_SEL0_IN6_SEL0_MASK (0x3000U) -#define ITRC_OUT3_SEL0_IN6_SEL0_SHIFT (12U) -/*! IN6_SEL0 - Selects Flash ECC mismatch event as a trigger source. - */ -#define ITRC_OUT3_SEL0_IN6_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN6_SEL0_MASK) - -#define ITRC_OUT3_SEL0_IN7_SEL0_MASK (0xC000U) -#define ITRC_OUT3_SEL0_IN7_SEL0_SHIFT (14U) -/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source. - */ -#define ITRC_OUT3_SEL0_IN7_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN7_SEL0_MASK) - -#define ITRC_OUT3_SEL0_IN8_SEL0_MASK (0x30000U) -#define ITRC_OUT3_SEL0_IN8_SEL0_SHIFT (16U) -/*! IN8_SEL0 - Selects CSS error event as a trigger source. - */ -#define ITRC_OUT3_SEL0_IN8_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN8_SEL0_MASK) - -#define ITRC_OUT3_SEL0_IN10_SEL0_MASK (0x300000U) -#define ITRC_OUT3_SEL0_IN10_SEL0_SHIFT (20U) -/*! IN10_SEL0 - Selects PKC error event as a trigger source. - */ -#define ITRC_OUT3_SEL0_IN10_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN10_SEL0_MASK) - -#define ITRC_OUT3_SEL0_IN14_SEL0_MASK (0x30000000U) -#define ITRC_OUT3_SEL0_IN14_SEL0_SHIFT (28U) -/*! IN14_SEL0 - Selects software event 0 as a trigger source. - */ -#define ITRC_OUT3_SEL0_IN14_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN14_SEL0_MASK) - -#define ITRC_OUT3_SEL0_IN15_SEL0_MASK (0xC0000000U) -#define ITRC_OUT3_SEL0_IN15_SEL0_SHIFT (30U) -/*! IN15_SEL0 - Selects software event 1 as a trigger source. - */ -#define ITRC_OUT3_SEL0_IN15_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN15_SEL0_MASK) -/*! @} */ - -/*! @name OUT3_SEL1 - RAM_ZEROIZE Trigger source IN0 to IN15 selector 1 */ -/*! @{ */ - -#define ITRC_OUT3_SEL1_IN0_SEL1_MASK (0x3U) -#define ITRC_OUT3_SEL1_IN0_SEL1_SHIFT (0U) -/*! IN0_SEL1 - Selects digital glitch detector as a trigger source. - */ -#define ITRC_OUT3_SEL1_IN0_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN0_SEL1_MASK) - -#define ITRC_OUT3_SEL1_IN1_SEL1_MASK (0xCU) -#define ITRC_OUT3_SEL1_IN1_SEL1_SHIFT (2U) -/*! IN1_SEL1 - Selects tamper pin event as a trigger source. - */ -#define ITRC_OUT3_SEL1_IN1_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN1_SEL1_MASK) - -#define ITRC_OUT3_SEL1_IN2_SEL1_MASK (0x30U) -#define ITRC_OUT3_SEL1_IN2_SEL1_SHIFT (4U) -/*! IN2_SEL1 - Selects Code Watch Dog event as a trigger source. - */ -#define ITRC_OUT3_SEL1_IN2_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN2_SEL1_MASK) - -#define ITRC_OUT3_SEL1_IN3_SEL1_MASK (0xC0U) -#define ITRC_OUT3_SEL1_IN3_SEL1_SHIFT (6U) -/*! IN3_SEL1 - Selects low-voltage event on VDD_MAIN rail as a trigger source. - */ -#define ITRC_OUT3_SEL1_IN3_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN3_SEL1_MASK) - -#define ITRC_OUT3_SEL1_IN4_SEL1_MASK (0x300U) -#define ITRC_OUT3_SEL1_IN4_SEL1_SHIFT (8U) -/*! IN4_SEL1 - Selects low-voltage event on VDD_CORE rail as a trigger source. - */ -#define ITRC_OUT3_SEL1_IN4_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN4_SEL1_MASK) - -#define ITRC_OUT3_SEL1_IN5_SEL1_MASK (0xC00U) -#define ITRC_OUT3_SEL1_IN5_SEL1_SHIFT (10U) -/*! IN5_SEL1 - Selects Watch Dog timer event as a trigger source. - */ -#define ITRC_OUT3_SEL1_IN5_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN5_SEL1_MASK) - -#define ITRC_OUT3_SEL1_IN6_SEL1_MASK (0x3000U) -#define ITRC_OUT3_SEL1_IN6_SEL1_SHIFT (12U) -/*! IN6_SEL1 - Selects Flash ECC mismatch event as a trigger source. - */ -#define ITRC_OUT3_SEL1_IN6_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN6_SEL1_MASK) - -#define ITRC_OUT3_SEL1_IN7_SEL1_MASK (0xC000U) -#define ITRC_OUT3_SEL1_IN7_SEL1_SHIFT (14U) -/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source. - */ -#define ITRC_OUT3_SEL1_IN7_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN7_SEL1_MASK) - -#define ITRC_OUT3_SEL1_IN8_SEL1_MASK (0x30000U) -#define ITRC_OUT3_SEL1_IN8_SEL1_SHIFT (16U) -/*! IN8_SEL1 - Selects CSS error event as a trigger source. - */ -#define ITRC_OUT3_SEL1_IN8_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN8_SEL1_MASK) - -#define ITRC_OUT3_SEL1_IN10_SEL1_MASK (0x300000U) -#define ITRC_OUT3_SEL1_IN10_SEL1_SHIFT (20U) -/*! IN10_SEL1 - Selects PKC error event as a trigger source. - */ -#define ITRC_OUT3_SEL1_IN10_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN10_SEL1_MASK) - -#define ITRC_OUT3_SEL1_IN14_SEL1_MASK (0x30000000U) -#define ITRC_OUT3_SEL1_IN14_SEL1_SHIFT (28U) -/*! IN14_SEL1 - Selects software event 0 as a trigger source. - */ -#define ITRC_OUT3_SEL1_IN14_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN14_SEL1_MASK) - -#define ITRC_OUT3_SEL1_IN15_SEL1_MASK (0xC0000000U) -#define ITRC_OUT3_SEL1_IN15_SEL1_SHIFT (30U) -/*! IN15_SEL1 - Selects software event 1 as a trigger source. - */ -#define ITRC_OUT3_SEL1_IN15_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN15_SEL1_MASK) -/*! @} */ - -/*! @name OUT4_SEL0 - CHIP_RESET Trigger source IN0 to IN15 selector 0 */ -/*! @{ */ - -#define ITRC_OUT4_SEL0_IN0_SEL0_MASK (0x3U) -#define ITRC_OUT4_SEL0_IN0_SEL0_SHIFT (0U) -/*! IN0_SEL0 - CSS_RESET Trigger source selector 0 register. - */ -#define ITRC_OUT4_SEL0_IN0_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN0_SEL0_MASK) - -#define ITRC_OUT4_SEL0_IN1_SEL0_MASK (0xCU) -#define ITRC_OUT4_SEL0_IN1_SEL0_SHIFT (2U) -/*! IN1_SEL0 - Selects tamper pin event as a trigger source. - */ -#define ITRC_OUT4_SEL0_IN1_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN1_SEL0_MASK) - -#define ITRC_OUT4_SEL0_IN2_SEL0_MASK (0x30U) -#define ITRC_OUT4_SEL0_IN2_SEL0_SHIFT (4U) -/*! IN2_SEL0 - Selects Code Watch Dog event as a trigger source. - */ -#define ITRC_OUT4_SEL0_IN2_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN2_SEL0_MASK) - -#define ITRC_OUT4_SEL0_IN3_SEL0_MASK (0xC0U) -#define ITRC_OUT4_SEL0_IN3_SEL0_SHIFT (6U) -/*! IN3_SEL0 - Selects low-voltage event on VDD_MAIN rail as a trigger source. - */ -#define ITRC_OUT4_SEL0_IN3_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN3_SEL0_MASK) - -#define ITRC_OUT4_SEL0_IN4_SEL0_MASK (0x300U) -#define ITRC_OUT4_SEL0_IN4_SEL0_SHIFT (8U) -/*! IN4_SEL0 - Selects low-voltage event on VDD_CORE rail as a trigger source. - */ -#define ITRC_OUT4_SEL0_IN4_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN4_SEL0_MASK) - -#define ITRC_OUT4_SEL0_IN5_SEL0_MASK (0xC00U) -#define ITRC_OUT4_SEL0_IN5_SEL0_SHIFT (10U) -/*! IN5_SEL0 - Selects Watch Dog timer event as a trigger source. - */ -#define ITRC_OUT4_SEL0_IN5_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN5_SEL0_MASK) - -#define ITRC_OUT4_SEL0_IN6_SEL0_MASK (0x3000U) -#define ITRC_OUT4_SEL0_IN6_SEL0_SHIFT (12U) -/*! IN6_SEL0 - Selects Flash ECC mismatch event as a trigger source. - */ -#define ITRC_OUT4_SEL0_IN6_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN6_SEL0_MASK) - -#define ITRC_OUT4_SEL0_IN7_SEL0_MASK (0xC000U) -#define ITRC_OUT4_SEL0_IN7_SEL0_SHIFT (14U) -/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source. - */ -#define ITRC_OUT4_SEL0_IN7_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN7_SEL0_MASK) - -#define ITRC_OUT4_SEL0_IN8_SEL0_MASK (0x30000U) -#define ITRC_OUT4_SEL0_IN8_SEL0_SHIFT (16U) -/*! IN8_SEL0 - Selects CSS error event as a trigger source. - */ -#define ITRC_OUT4_SEL0_IN8_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN8_SEL0_MASK) - -#define ITRC_OUT4_SEL0_IN10_SEL0_MASK (0x300000U) -#define ITRC_OUT4_SEL0_IN10_SEL0_SHIFT (20U) -/*! IN10_SEL0 - Selects PKC error event as a trigger source. - */ -#define ITRC_OUT4_SEL0_IN10_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN10_SEL0_MASK) - -#define ITRC_OUT4_SEL0_IN14_SEL0_MASK (0x30000000U) -#define ITRC_OUT4_SEL0_IN14_SEL0_SHIFT (28U) -/*! IN14_SEL0 - Selects software event 0 as a trigger source. - */ -#define ITRC_OUT4_SEL0_IN14_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN14_SEL0_MASK) - -#define ITRC_OUT4_SEL0_IN15_SEL0_MASK (0xC0000000U) -#define ITRC_OUT4_SEL0_IN15_SEL0_SHIFT (30U) -/*! IN15_SEL0 - Selects software event 1 as a trigger source. - */ -#define ITRC_OUT4_SEL0_IN15_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN15_SEL0_MASK) -/*! @} */ - -/*! @name OUT4_SEL1 - CHIP_RESET Trigger source IN0 to IN15 selector 1 */ -/*! @{ */ - -#define ITRC_OUT4_SEL1_IN0_SEL1_MASK (0x3U) -#define ITRC_OUT4_SEL1_IN0_SEL1_SHIFT (0U) -/*! IN0_SEL1 - Selects digital glitch detector as a trigger source. - */ -#define ITRC_OUT4_SEL1_IN0_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN0_SEL1_MASK) - -#define ITRC_OUT4_SEL1_IN1_SEL1_MASK (0xCU) -#define ITRC_OUT4_SEL1_IN1_SEL1_SHIFT (2U) -/*! IN1_SEL1 - Selects tamper pin event as a trigger source. - */ -#define ITRC_OUT4_SEL1_IN1_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN1_SEL1_MASK) - -#define ITRC_OUT4_SEL1_IN2_SEL1_MASK (0x30U) -#define ITRC_OUT4_SEL1_IN2_SEL1_SHIFT (4U) -/*! IN2_SEL1 - Selects Code Watch Dog event as a trigger source. - */ -#define ITRC_OUT4_SEL1_IN2_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN2_SEL1_MASK) - -#define ITRC_OUT4_SEL1_IN3_SEL1_MASK (0xC0U) -#define ITRC_OUT4_SEL1_IN3_SEL1_SHIFT (6U) -/*! IN3_SEL1 - Selects low-voltage event on VDD_MAIN rail as a trigger source. - */ -#define ITRC_OUT4_SEL1_IN3_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN3_SEL1_MASK) - -#define ITRC_OUT4_SEL1_IN4_SEL1_MASK (0x300U) -#define ITRC_OUT4_SEL1_IN4_SEL1_SHIFT (8U) -/*! IN4_SEL1 - Selects low-voltage event on VDD_CORE rail as a trigger source. - */ -#define ITRC_OUT4_SEL1_IN4_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN4_SEL1_MASK) - -#define ITRC_OUT4_SEL1_IN5_SEL1_MASK (0xC00U) -#define ITRC_OUT4_SEL1_IN5_SEL1_SHIFT (10U) -/*! IN5_SEL1 - Selects Watch Dog timer event as a trigger source. - */ -#define ITRC_OUT4_SEL1_IN5_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN5_SEL1_MASK) - -#define ITRC_OUT4_SEL1_IN6_SEL1_MASK (0x3000U) -#define ITRC_OUT4_SEL1_IN6_SEL1_SHIFT (12U) -/*! IN6_SEL1 - Selects Flash ECC mismatch event as a trigger source. - */ -#define ITRC_OUT4_SEL1_IN6_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN6_SEL1_MASK) - -#define ITRC_OUT4_SEL1_IN7_SEL1_MASK (0xC000U) -#define ITRC_OUT4_SEL1_IN7_SEL1_SHIFT (14U) -/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source. - */ -#define ITRC_OUT4_SEL1_IN7_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN7_SEL1_MASK) - -#define ITRC_OUT4_SEL1_IN8_SEL1_MASK (0x30000U) -#define ITRC_OUT4_SEL1_IN8_SEL1_SHIFT (16U) -/*! IN8_SEL1 - Selects CSS error event as a trigger source. - */ -#define ITRC_OUT4_SEL1_IN8_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN8_SEL1_MASK) - -#define ITRC_OUT4_SEL1_IN10_SEL1_MASK (0x300000U) -#define ITRC_OUT4_SEL1_IN10_SEL1_SHIFT (20U) -/*! IN10_SEL1 - Selects PKC error event as a trigger source. - */ -#define ITRC_OUT4_SEL1_IN10_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN10_SEL1_MASK) - -#define ITRC_OUT4_SEL1_IN14_SEL1_MASK (0x30000000U) -#define ITRC_OUT4_SEL1_IN14_SEL1_SHIFT (28U) -/*! IN14_SEL1 - Selects software event 0 as a trigger source. - */ -#define ITRC_OUT4_SEL1_IN14_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN14_SEL1_MASK) - -#define ITRC_OUT4_SEL1_IN15_SEL1_MASK (0xC0000000U) -#define ITRC_OUT4_SEL1_IN15_SEL1_SHIFT (30U) -/*! IN15_SEL1 - Selects software event 1 as a trigger source. - */ -#define ITRC_OUT4_SEL1_IN15_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN15_SEL1_MASK) -/*! @} */ - -/*! @name OUT5_SEL0 - TMPR_OUT0 IN0 to IN15 selector 0 */ -/*! @{ */ - -#define ITRC_OUT5_SEL0_IN0_SEL0_MASK (0x3U) -#define ITRC_OUT5_SEL0_IN0_SEL0_SHIFT (0U) -/*! IN0_SEL0 - CSS_RESET Trigger source selector 0 register. - */ -#define ITRC_OUT5_SEL0_IN0_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN0_SEL0_MASK) - -#define ITRC_OUT5_SEL0_IN1_SEL0_MASK (0xCU) -#define ITRC_OUT5_SEL0_IN1_SEL0_SHIFT (2U) -/*! IN1_SEL0 - Selects tamper pin event as a trigger source. - */ -#define ITRC_OUT5_SEL0_IN1_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN1_SEL0_MASK) - -#define ITRC_OUT5_SEL0_IN2_SEL0_MASK (0x30U) -#define ITRC_OUT5_SEL0_IN2_SEL0_SHIFT (4U) -/*! IN2_SEL0 - Selects Code Watch Dog event as a trigger source. - */ -#define ITRC_OUT5_SEL0_IN2_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN2_SEL0_MASK) - -#define ITRC_OUT5_SEL0_IN3_SEL0_MASK (0xC0U) -#define ITRC_OUT5_SEL0_IN3_SEL0_SHIFT (6U) -/*! IN3_SEL0 - Selects low-voltage event on VDD_MAIN rail as a trigger source. - */ -#define ITRC_OUT5_SEL0_IN3_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN3_SEL0_MASK) - -#define ITRC_OUT5_SEL0_IN4_SEL0_MASK (0x300U) -#define ITRC_OUT5_SEL0_IN4_SEL0_SHIFT (8U) -/*! IN4_SEL0 - Selects low-voltage event on VDD_CORE rail as a trigger source. - */ -#define ITRC_OUT5_SEL0_IN4_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN4_SEL0_MASK) - -#define ITRC_OUT5_SEL0_IN5_SEL0_MASK (0xC00U) -#define ITRC_OUT5_SEL0_IN5_SEL0_SHIFT (10U) -/*! IN5_SEL0 - Selects Watch Dog timer event as a trigger source. - */ -#define ITRC_OUT5_SEL0_IN5_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN5_SEL0_MASK) - -#define ITRC_OUT5_SEL0_IN6_SEL0_MASK (0x3000U) -#define ITRC_OUT5_SEL0_IN6_SEL0_SHIFT (12U) -/*! IN6_SEL0 - Selects Flash ECC mismatch event as a trigger source. - */ -#define ITRC_OUT5_SEL0_IN6_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN6_SEL0_MASK) - -#define ITRC_OUT5_SEL0_IN7_SEL0_MASK (0xC000U) -#define ITRC_OUT5_SEL0_IN7_SEL0_SHIFT (14U) -/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source. - */ -#define ITRC_OUT5_SEL0_IN7_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN7_SEL0_MASK) - -#define ITRC_OUT5_SEL0_IN8_SEL0_MASK (0x30000U) -#define ITRC_OUT5_SEL0_IN8_SEL0_SHIFT (16U) -/*! IN8_SEL0 - Selects CSS error event as a trigger source. - */ -#define ITRC_OUT5_SEL0_IN8_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN8_SEL0_MASK) - -#define ITRC_OUT5_SEL0_IN10_SEL0_MASK (0x300000U) -#define ITRC_OUT5_SEL0_IN10_SEL0_SHIFT (20U) -/*! IN10_SEL0 - Selects PKC error event as a trigger source. - */ -#define ITRC_OUT5_SEL0_IN10_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN10_SEL0_MASK) - -#define ITRC_OUT5_SEL0_IN14_SEL0_MASK (0x30000000U) -#define ITRC_OUT5_SEL0_IN14_SEL0_SHIFT (28U) -/*! IN14_SEL0 - Selects software event 0 as a trigger source. - */ -#define ITRC_OUT5_SEL0_IN14_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN14_SEL0_MASK) - -#define ITRC_OUT5_SEL0_IN15_SEL0_MASK (0xC0000000U) -#define ITRC_OUT5_SEL0_IN15_SEL0_SHIFT (30U) -/*! IN15_SEL0 - Selects software event 1 as a trigger source. - */ -#define ITRC_OUT5_SEL0_IN15_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN15_SEL0_MASK) -/*! @} */ - -/*! @name OUT5_SEL1 - TMPR_OUT0 IN0 to IN15 selector 1 */ -/*! @{ */ - -#define ITRC_OUT5_SEL1_IN0_SEL1_MASK (0x3U) -#define ITRC_OUT5_SEL1_IN0_SEL1_SHIFT (0U) -/*! IN0_SEL1 - Selects digital glitch detector as a trigger source. - */ -#define ITRC_OUT5_SEL1_IN0_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN0_SEL1_MASK) - -#define ITRC_OUT5_SEL1_IN1_SEL1_MASK (0xCU) -#define ITRC_OUT5_SEL1_IN1_SEL1_SHIFT (2U) -/*! IN1_SEL1 - Selects tamper pin event as a trigger source. - */ -#define ITRC_OUT5_SEL1_IN1_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN1_SEL1_MASK) - -#define ITRC_OUT5_SEL1_IN2_SEL1_MASK (0x30U) -#define ITRC_OUT5_SEL1_IN2_SEL1_SHIFT (4U) -/*! IN2_SEL1 - Selects Code Watch Dog event as a trigger source. - */ -#define ITRC_OUT5_SEL1_IN2_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN2_SEL1_MASK) - -#define ITRC_OUT5_SEL1_IN3_SEL1_MASK (0xC0U) -#define ITRC_OUT5_SEL1_IN3_SEL1_SHIFT (6U) -/*! IN3_SEL1 - Selects low-voltage event on VDD_MAIN rail as a trigger source. - */ -#define ITRC_OUT5_SEL1_IN3_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN3_SEL1_MASK) - -#define ITRC_OUT5_SEL1_IN4_SEL1_MASK (0x300U) -#define ITRC_OUT5_SEL1_IN4_SEL1_SHIFT (8U) -/*! IN4_SEL1 - Selects low-voltage event on VDD_CORE rail as a trigger source. - */ -#define ITRC_OUT5_SEL1_IN4_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN4_SEL1_MASK) - -#define ITRC_OUT5_SEL1_IN5_SEL1_MASK (0xC00U) -#define ITRC_OUT5_SEL1_IN5_SEL1_SHIFT (10U) -/*! IN5_SEL1 - Selects Watch Dog timer event as a trigger source. - */ -#define ITRC_OUT5_SEL1_IN5_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN5_SEL1_MASK) - -#define ITRC_OUT5_SEL1_IN6_SEL1_MASK (0x3000U) -#define ITRC_OUT5_SEL1_IN6_SEL1_SHIFT (12U) -/*! IN6_SEL1 - Selects Flash ECC mismatch event as a trigger source. - */ -#define ITRC_OUT5_SEL1_IN6_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN6_SEL1_MASK) - -#define ITRC_OUT5_SEL1_IN7_SEL1_MASK (0xC000U) -#define ITRC_OUT5_SEL1_IN7_SEL1_SHIFT (14U) -/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source. - */ -#define ITRC_OUT5_SEL1_IN7_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN7_SEL1_MASK) - -#define ITRC_OUT5_SEL1_IN8_SEL1_MASK (0x30000U) -#define ITRC_OUT5_SEL1_IN8_SEL1_SHIFT (16U) -/*! IN8_SEL1 - Selects CSS error event as a trigger source. - */ -#define ITRC_OUT5_SEL1_IN8_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN8_SEL1_MASK) - -#define ITRC_OUT5_SEL1_IN10_SEL1_MASK (0x300000U) -#define ITRC_OUT5_SEL1_IN10_SEL1_SHIFT (20U) -/*! IN10_SEL1 - Selects PKC error event as a trigger source. - */ -#define ITRC_OUT5_SEL1_IN10_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN10_SEL1_MASK) - -#define ITRC_OUT5_SEL1_IN14_SEL1_MASK (0x30000000U) -#define ITRC_OUT5_SEL1_IN14_SEL1_SHIFT (28U) -/*! IN14_SEL1 - Selects software event 0 as a trigger source. - */ -#define ITRC_OUT5_SEL1_IN14_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN14_SEL1_MASK) - -#define ITRC_OUT5_SEL1_IN15_SEL1_MASK (0xC0000000U) -#define ITRC_OUT5_SEL1_IN15_SEL1_SHIFT (30U) -/*! IN15_SEL1 - Selects software event 1 as a trigger source. - */ -#define ITRC_OUT5_SEL1_IN15_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN15_SEL1_MASK) -/*! @} */ - -/*! @name OUT6_SEL0 - TMPR_OUT1 IN0 to IN15 selector 0 */ -/*! @{ */ - -#define ITRC_OUT6_SEL0_IN0_SEL0_MASK (0x3U) -#define ITRC_OUT6_SEL0_IN0_SEL0_SHIFT (0U) -/*! IN0_SEL0 - CSS_RESET Trigger source selector 0 register. - */ -#define ITRC_OUT6_SEL0_IN0_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN0_SEL0_MASK) - -#define ITRC_OUT6_SEL0_IN1_SEL0_MASK (0xCU) -#define ITRC_OUT6_SEL0_IN1_SEL0_SHIFT (2U) -/*! IN1_SEL0 - Selects tamper pin event as a trigger source. - */ -#define ITRC_OUT6_SEL0_IN1_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN1_SEL0_MASK) - -#define ITRC_OUT6_SEL0_IN2_SEL0_MASK (0x30U) -#define ITRC_OUT6_SEL0_IN2_SEL0_SHIFT (4U) -/*! IN2_SEL0 - Selects Code Watch Dog event as a trigger source. - */ -#define ITRC_OUT6_SEL0_IN2_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN2_SEL0_MASK) - -#define ITRC_OUT6_SEL0_IN3_SEL0_MASK (0xC0U) -#define ITRC_OUT6_SEL0_IN3_SEL0_SHIFT (6U) -/*! IN3_SEL0 - Selects low-voltage event on VDD_MAIN rail as a trigger source. - */ -#define ITRC_OUT6_SEL0_IN3_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN3_SEL0_MASK) - -#define ITRC_OUT6_SEL0_IN4_SEL0_MASK (0x300U) -#define ITRC_OUT6_SEL0_IN4_SEL0_SHIFT (8U) -/*! IN4_SEL0 - Selects low-voltage event on VDD_CORE rail as a trigger source. - */ -#define ITRC_OUT6_SEL0_IN4_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN4_SEL0_MASK) - -#define ITRC_OUT6_SEL0_IN5_SEL0_MASK (0xC00U) -#define ITRC_OUT6_SEL0_IN5_SEL0_SHIFT (10U) -/*! IN5_SEL0 - Selects Watch Dog timer event as a trigger source. - */ -#define ITRC_OUT6_SEL0_IN5_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN5_SEL0_MASK) - -#define ITRC_OUT6_SEL0_IN6_SEL0_MASK (0x3000U) -#define ITRC_OUT6_SEL0_IN6_SEL0_SHIFT (12U) -/*! IN6_SEL0 - Selects Flash ECC mismatch event as a trigger source. - */ -#define ITRC_OUT6_SEL0_IN6_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN6_SEL0_MASK) - -#define ITRC_OUT6_SEL0_IN7_SEL0_MASK (0xC000U) -#define ITRC_OUT6_SEL0_IN7_SEL0_SHIFT (14U) -/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source. - */ -#define ITRC_OUT6_SEL0_IN7_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN7_SEL0_MASK) - -#define ITRC_OUT6_SEL0_IN8_SEL0_MASK (0x30000U) -#define ITRC_OUT6_SEL0_IN8_SEL0_SHIFT (16U) -/*! IN8_SEL0 - Selects CSS error event as a trigger source. - */ -#define ITRC_OUT6_SEL0_IN8_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN8_SEL0_MASK) - -#define ITRC_OUT6_SEL0_IN10_SEL0_MASK (0x300000U) -#define ITRC_OUT6_SEL0_IN10_SEL0_SHIFT (20U) -/*! IN10_SEL0 - Selects PKC error event as a trigger source. - */ -#define ITRC_OUT6_SEL0_IN10_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN10_SEL0_MASK) - -#define ITRC_OUT6_SEL0_IN14_SEL0_MASK (0x30000000U) -#define ITRC_OUT6_SEL0_IN14_SEL0_SHIFT (28U) -/*! IN14_SEL0 - Selects software event 0 as a trigger source. - */ -#define ITRC_OUT6_SEL0_IN14_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN14_SEL0_MASK) - -#define ITRC_OUT6_SEL0_IN15_SEL0_MASK (0xC0000000U) -#define ITRC_OUT6_SEL0_IN15_SEL0_SHIFT (30U) -/*! IN15_SEL0 - Selects software event 1 as a trigger source. - */ -#define ITRC_OUT6_SEL0_IN15_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN15_SEL0_MASK) -/*! @} */ - -/*! @name OUT6_SEL1 - TMPR_OUT1 IN0 to IN15 selector 1 */ -/*! @{ */ - -#define ITRC_OUT6_SEL1_IN0_SEL1_MASK (0x3U) -#define ITRC_OUT6_SEL1_IN0_SEL1_SHIFT (0U) -/*! IN0_SEL1 - Selects digital glitch detector as a trigger source. - */ -#define ITRC_OUT6_SEL1_IN0_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN0_SEL1_MASK) - -#define ITRC_OUT6_SEL1_IN1_SEL1_MASK (0xCU) -#define ITRC_OUT6_SEL1_IN1_SEL1_SHIFT (2U) -/*! IN1_SEL1 - Selects tamper pin event as a trigger source. - */ -#define ITRC_OUT6_SEL1_IN1_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN1_SEL1_MASK) - -#define ITRC_OUT6_SEL1_IN2_SEL1_MASK (0x30U) -#define ITRC_OUT6_SEL1_IN2_SEL1_SHIFT (4U) -/*! IN2_SEL1 - Selects Code Watch Dog event as a trigger source. - */ -#define ITRC_OUT6_SEL1_IN2_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN2_SEL1_MASK) - -#define ITRC_OUT6_SEL1_IN3_SEL1_MASK (0xC0U) -#define ITRC_OUT6_SEL1_IN3_SEL1_SHIFT (6U) -/*! IN3_SEL1 - Selects low-voltage event on VDD_MAIN rail as a trigger source. - */ -#define ITRC_OUT6_SEL1_IN3_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN3_SEL1_MASK) - -#define ITRC_OUT6_SEL1_IN4_SEL1_MASK (0x300U) -#define ITRC_OUT6_SEL1_IN4_SEL1_SHIFT (8U) -/*! IN4_SEL1 - Selects low-voltage event on VDD_CORE rail as a trigger source. - */ -#define ITRC_OUT6_SEL1_IN4_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN4_SEL1_MASK) - -#define ITRC_OUT6_SEL1_IN5_SEL1_MASK (0xC00U) -#define ITRC_OUT6_SEL1_IN5_SEL1_SHIFT (10U) -/*! IN5_SEL1 - Selects Watch Dog timer event as a trigger source. - */ -#define ITRC_OUT6_SEL1_IN5_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN5_SEL1_MASK) - -#define ITRC_OUT6_SEL1_IN6_SEL1_MASK (0x3000U) -#define ITRC_OUT6_SEL1_IN6_SEL1_SHIFT (12U) -/*! IN6_SEL1 - Selects Flash ECC mismatch event as a trigger source. - */ -#define ITRC_OUT6_SEL1_IN6_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN6_SEL1_MASK) - -#define ITRC_OUT6_SEL1_IN7_SEL1_MASK (0xC000U) -#define ITRC_OUT6_SEL1_IN7_SEL1_SHIFT (14U) -/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source. - */ -#define ITRC_OUT6_SEL1_IN7_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN7_SEL1_MASK) - -#define ITRC_OUT6_SEL1_IN8_SEL1_MASK (0x30000U) -#define ITRC_OUT6_SEL1_IN8_SEL1_SHIFT (16U) -/*! IN8_SEL1 - Selects CSS error event as a trigger source. - */ -#define ITRC_OUT6_SEL1_IN8_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN8_SEL1_MASK) - -#define ITRC_OUT6_SEL1_IN10_SEL1_MASK (0x300000U) -#define ITRC_OUT6_SEL1_IN10_SEL1_SHIFT (20U) -/*! IN10_SEL1 - Selects PKC error event as a trigger source. - */ -#define ITRC_OUT6_SEL1_IN10_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN10_SEL1_MASK) - -#define ITRC_OUT6_SEL1_IN14_SEL1_MASK (0x30000000U) -#define ITRC_OUT6_SEL1_IN14_SEL1_SHIFT (28U) -/*! IN14_SEL1 - Selects software event 0 as a trigger source. - */ -#define ITRC_OUT6_SEL1_IN14_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN14_SEL1_MASK) - -#define ITRC_OUT6_SEL1_IN15_SEL1_MASK (0xC0000000U) -#define ITRC_OUT6_SEL1_IN15_SEL1_SHIFT (30U) -/*! IN15_SEL1 - Selects software event 1 as a trigger source. - */ -#define ITRC_OUT6_SEL1_IN15_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN15_SEL1_MASK) -/*! @} */ - -/*! @name SW_EVENT0 - Software event 0 */ -/*! @{ */ - -#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_MASK (0xFFFFFFFFU) -#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_SHIFT (0U) -/*! TRIGGER_SW_EVENT_0 - Trigger software event 0. - */ -#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_SHIFT)) & ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_MASK) -/*! @} */ - -/*! @name SW_EVENT1 - Software event 1 */ -/*! @{ */ - -#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_MASK (0xFFFFFFFFU) -#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_SHIFT (0U) -/*! TRIGGER_SW_EVENT_1 - Trigger software event 1. - */ -#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_SHIFT)) & ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ITRC_Register_Masks */ - - -/* ITRC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral ITRC0 base address */ - #define ITRC0_BASE (0x5000F000u) - /** Peripheral ITRC0 base address */ - #define ITRC0_BASE_NS (0x4000F000u) - /** Peripheral ITRC0 base pointer */ - #define ITRC0 ((ITRC_Type *)ITRC0_BASE) - /** Peripheral ITRC0 base pointer */ - #define ITRC0_NS ((ITRC_Type *)ITRC0_BASE_NS) - /** Array initializer of ITRC peripheral base addresses */ - #define ITRC_BASE_ADDRS { ITRC0_BASE } - /** Array initializer of ITRC peripheral base pointers */ - #define ITRC_BASE_PTRS { ITRC0 } - /** Array initializer of ITRC peripheral base addresses */ - #define ITRC_BASE_ADDRS_NS { ITRC0_BASE_NS } - /** Array initializer of ITRC peripheral base pointers */ - #define ITRC_BASE_PTRS_NS { ITRC0_NS } -#else - /** Peripheral ITRC0 base address */ - #define ITRC0_BASE (0x4000F000u) - /** Peripheral ITRC0 base pointer */ - #define ITRC0 ((ITRC_Type *)ITRC0_BASE) - /** Array initializer of ITRC peripheral base addresses */ - #define ITRC_BASE_ADDRS { ITRC0_BASE } - /** Array initializer of ITRC peripheral base pointers */ - #define ITRC_BASE_PTRS { ITRC0 } -#endif - -/*! - * @} - */ /* end of group ITRC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPDAC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPDAC_Peripheral_Access_Layer LPDAC Peripheral Access Layer - * @{ - */ - -/** LPDAC - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version Identifier Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __O uint32_t DATA; /**< Data Register, offset: 0x8 */ - __IO uint32_t GCR; /**< Global Control Register, offset: 0xC */ - __IO uint32_t FCR; /**< DAC FIFO Control Register, offset: 0x10 */ - __I uint32_t FPR; /**< DAC FIFO Pointer Register, offset: 0x14 */ - __IO uint32_t FSR; /**< FIFO Status Register, offset: 0x18 */ - __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x1C */ - __IO uint32_t DER; /**< DMA Enable Register, offset: 0x20 */ - __IO uint32_t RCR; /**< Reset Control Register, offset: 0x24 */ - __O uint32_t TCR; /**< Trigger Control Register, offset: 0x28 */ - __IO uint32_t PCR; /**< Periodic Trigger Control Register, offset: 0x2C */ -} LPDAC_Type; - -/* ---------------------------------------------------------------------------- - -- LPDAC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPDAC_Register_Masks LPDAC Register Masks - * @{ - */ - -/*! @name VERID - Version Identifier Register */ -/*! @{ */ - -#define LPDAC_VERID_FEATURE_MASK (0xFFFFU) -#define LPDAC_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Identification Number - */ -#define LPDAC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_FEATURE_SHIFT)) & LPDAC_VERID_FEATURE_MASK) - -#define LPDAC_VERID_MINOR_MASK (0xFF0000U) -#define LPDAC_VERID_MINOR_SHIFT (16U) -/*! MINOR - Minor version number - */ -#define LPDAC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MINOR_SHIFT)) & LPDAC_VERID_MINOR_MASK) - -#define LPDAC_VERID_MAJOR_MASK (0xFF000000U) -#define LPDAC_VERID_MAJOR_SHIFT (24U) -/*! MAJOR - Major version number - */ -#define LPDAC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MAJOR_SHIFT)) & LPDAC_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ - -#define LPDAC_PARAM_FIFOSZ_MASK (0x7U) -#define LPDAC_PARAM_FIFOSZ_SHIFT (0U) -/*! FIFOSZ - FIFO size - * 0b000..Reserved - * 0b001..FIFO depth is 4 - * 0b010..FIFO depth is 8 - * 0b011..FIFO depth is 16 - * 0b100..FIFO depth is 32 - * 0b101..FIFO depth is 64 - * 0b110..FIFO depth is 128 - * 0b111..FIFO depth is 256 - */ -#define LPDAC_PARAM_FIFOSZ(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_PARAM_FIFOSZ_SHIFT)) & LPDAC_PARAM_FIFOSZ_MASK) -/*! @} */ - -/*! @name DATA - Data Register */ -/*! @{ */ - -#define LPDAC_DATA_DATA_MASK (0xFFFU) -#define LPDAC_DATA_DATA_SHIFT (0U) -/*! DATA - FIFO entry or Buffer entry - */ -#define LPDAC_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_DATA_DATA_SHIFT)) & LPDAC_DATA_DATA_MASK) -/*! @} */ - -/*! @name GCR - Global Control Register */ -/*! @{ */ - -#define LPDAC_GCR_DACEN_MASK (0x1U) -#define LPDAC_GCR_DACEN_SHIFT (0U) -/*! DACEN - DAC Enable - * 0b0..The DAC system is disabled. - * 0b1..The DAC system is enabled. - */ -#define LPDAC_GCR_DACEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACEN_SHIFT)) & LPDAC_GCR_DACEN_MASK) - -#define LPDAC_GCR_DACRFS_MASK (0x6U) -#define LPDAC_GCR_DACRFS_SHIFT (1U) -/*! DACRFS - DAC Reference Select - * 0b00..The DAC selects VREFH1 as the reference voltage. - * 0b01..The DAC selects VREFH2 as the reference voltage. - * 0b10..The DAC selects VREFH3 as the reference voltage. - * 0b11..Reserved. - */ -#define LPDAC_GCR_DACRFS(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACRFS_SHIFT)) & LPDAC_GCR_DACRFS_MASK) - -#define LPDAC_GCR_FIFOEN_MASK (0x8U) -#define LPDAC_GCR_FIFOEN_SHIFT (3U) -/*! FIFOEN - FIFO Enable - * 0b0..FIFO mode is disabled and buffer mode is enabled. Any data written to DATA[DATA] goes to buffer then goes to conversion. - * 0b1..FIFO mode is enabled. Data will be first read from FIFO to buffer then goes to conversion - */ -#define LPDAC_GCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_FIFOEN_SHIFT)) & LPDAC_GCR_FIFOEN_MASK) - -#define LPDAC_GCR_SWMD_MASK (0x10U) -#define LPDAC_GCR_SWMD_SHIFT (4U) -/*! SWMD - Swing Back Mode - * 0b0..Swing back mode disable - * 0b1..Swing back mode enable - */ -#define LPDAC_GCR_SWMD(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_SWMD_SHIFT)) & LPDAC_GCR_SWMD_MASK) - -#define LPDAC_GCR_TRGSEL_MASK (0x20U) -#define LPDAC_GCR_TRGSEL_SHIFT (5U) -/*! TRGSEL - DAC Trigger Select - * 0b0..The DAC hardware trigger is selected. - * 0b1..The DAC software trigger is selected. - */ -#define LPDAC_GCR_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_TRGSEL_SHIFT)) & LPDAC_GCR_TRGSEL_MASK) - -#define LPDAC_GCR_PTGEN_MASK (0x40U) -#define LPDAC_GCR_PTGEN_SHIFT (6U) -/*! PTGEN - DAC periodic trigger mode enable - * 0b0..DAC periodic trigger mode is disabled. - * 0b1..DAC periodic trigger mode is enabled. - */ -#define LPDAC_GCR_PTGEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_PTGEN_SHIFT)) & LPDAC_GCR_PTGEN_MASK) - -#define LPDAC_GCR_LATCH_CYC_MASK (0xF00U) -#define LPDAC_GCR_LATCH_CYC_SHIFT (8U) -/*! LATCH_CYC - RCLK cycles before data latch - * 0b0000..Sync time is 1 RCLK cycle, RCLK <= 25MHz - * 0b0001..Sync time is 2 RCLK cycles, 25MHz < RCLK <= 50MHz - * 0b0010..Sync time is 3 RCLK cycles, 50MHz < RCLK <= 75MHz - * 0b0011..Sync time is 4 RCLK cycles, 75MHz < RCLK <= 100MHz - * 0b0100..Sync time is 5 RCLK cycles, 100MHz < RCLK <= 125MHz - * 0b0101..Sync time is 6 RCLK cycles, 125MHz < RCLK <= 150MHz - * 0b0110..Sync time is 7 RCLK cycles, 150MHz < RCLK <= 175MHz - * 0b0111..Sync time is 8 RCLK cycles, 175MHz < RCLK <= 200MHz - * 0b1000..Sync time is 9 RCLK cycles, 200MHz < RCLK <= 225MHz - * 0b1001..Sync time is 10 RCLK cycles, 225MHz < RCLK <= 250MHz - * 0b1010..Sync time is 11 RCLK cycles, 250MHz < RCLK <= 275MHz - * 0b1011..Sync time is 12 RCLK cycles, 275MHz < RCLK <= 300MHz - * 0b1100..Sync time is 13 RCLK cycles, 300MHz < RCLK <= 325MHz - * 0b1101..Sync time is 14 RCLK cycles, 325MHz < RCLK <= 350MHz - * 0b1110..Sync time is 15 RCLK cycles, 350MHz < RCLK <= 375MHz - * 0b1111..Sync time is 16 RCLK cycles, 375MHz < RCLK <= 400MHz - */ -#define LPDAC_GCR_LATCH_CYC(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_LATCH_CYC_SHIFT)) & LPDAC_GCR_LATCH_CYC_MASK) - -#define LPDAC_GCR_BUF_EN_MASK (0x20000U) -#define LPDAC_GCR_BUF_EN_SHIFT (17U) -/*! BUF_EN - Buffer Enable - * 0b0..Opamp is not used as buffer - * 0b1..Opamp is used as buffer - */ -#define LPDAC_GCR_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_BUF_EN_SHIFT)) & LPDAC_GCR_BUF_EN_MASK) - -#define LPDAC_GCR_IREF_PTAT_EXT_SEL_MASK (0x100000U) -#define LPDAC_GCR_IREF_PTAT_EXT_SEL_SHIFT (20U) -/*! IREF_PTAT_EXT_SEL - Internal PTAT Current Reference Select - * 0b0..Internal PTAT Current Reference not selected - * 0b1..Internal PTAT Current Reference selected - */ -#define LPDAC_GCR_IREF_PTAT_EXT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_IREF_PTAT_EXT_SEL_SHIFT)) & LPDAC_GCR_IREF_PTAT_EXT_SEL_MASK) - -#define LPDAC_GCR_IREF_ZTC_EXT_SEL_MASK (0x200000U) -#define LPDAC_GCR_IREF_ZTC_EXT_SEL_SHIFT (21U) -/*! IREF_ZTC_EXT_SEL - Internal ZTC Current Reference Select - * 0b0..Internal ZTC Current Reference not selected - * 0b1..Internal ZTC Current Reference selected - */ -#define LPDAC_GCR_IREF_ZTC_EXT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_IREF_ZTC_EXT_SEL_SHIFT)) & LPDAC_GCR_IREF_ZTC_EXT_SEL_MASK) - -#define LPDAC_GCR_BUF_SPD_CTRL_MASK (0x800000U) -#define LPDAC_GCR_BUF_SPD_CTRL_SHIFT (23U) -/*! BUF_SPD_CTRL - OPAMP as buffer, speed control signal - * 0b0..Lower low power mode - * 0b1..Low power mode - */ -#define LPDAC_GCR_BUF_SPD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_BUF_SPD_CTRL_SHIFT)) & LPDAC_GCR_BUF_SPD_CTRL_MASK) -/*! @} */ - -/*! @name FCR - DAC FIFO Control Register */ -/*! @{ */ - -#define LPDAC_FCR_WML_MASK (0xFU) -#define LPDAC_FCR_WML_SHIFT (0U) -/*! WML - Watermark Level - */ -#define LPDAC_FCR_WML(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FCR_WML_SHIFT)) & LPDAC_FCR_WML_MASK) -/*! @} */ - -/*! @name FPR - DAC FIFO Pointer Register */ -/*! @{ */ - -#define LPDAC_FPR_FIFO_RPT_MASK (0xFU) -#define LPDAC_FPR_FIFO_RPT_SHIFT (0U) -/*! FIFO_RPT - FIFO Read Pointer - */ -#define LPDAC_FPR_FIFO_RPT(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_RPT_SHIFT)) & LPDAC_FPR_FIFO_RPT_MASK) - -#define LPDAC_FPR_FIFO_WPT_MASK (0xF0000U) -#define LPDAC_FPR_FIFO_WPT_SHIFT (16U) -/*! FIFO_WPT - FIFO Write Pointer - */ -#define LPDAC_FPR_FIFO_WPT(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_WPT_SHIFT)) & LPDAC_FPR_FIFO_WPT_MASK) -/*! @} */ - -/*! @name FSR - FIFO Status Register */ -/*! @{ */ - -#define LPDAC_FSR_FULL_MASK (0x1U) -#define LPDAC_FSR_FULL_SHIFT (0U) -/*! FULL - FIFO Full Flag - * 0b0..FIFO is not full - * 0b1..FIFO is full - */ -#define LPDAC_FSR_FULL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_FULL_SHIFT)) & LPDAC_FSR_FULL_MASK) - -#define LPDAC_FSR_EMPTY_MASK (0x2U) -#define LPDAC_FSR_EMPTY_SHIFT (1U) -/*! EMPTY - FIFO Empty Flag - * 0b0..FIFO is not empty - * 0b1..FIFO is empty - */ -#define LPDAC_FSR_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_EMPTY_SHIFT)) & LPDAC_FSR_EMPTY_MASK) - -#define LPDAC_FSR_WM_MASK (0x4U) -#define LPDAC_FSR_WM_SHIFT (2U) -/*! WM - FIFO Watermark Status Flag - * 0b0..Data in FIFO is more than watermark level - * 0b1..Data in FIFO is less than or equal to watermark level - */ -#define LPDAC_FSR_WM(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_WM_SHIFT)) & LPDAC_FSR_WM_MASK) - -#define LPDAC_FSR_SWBK_MASK (0x8U) -#define LPDAC_FSR_SWBK_SHIFT (3U) -/*! SWBK - Swing Back One Cycle Complete Flag - * 0b0..No swing back cycle has completed since the last time the flag was cleared. - * 0b1..At least one swing back cycle has occurred since the last time the flag was cleared. - */ -#define LPDAC_FSR_SWBK(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_SWBK_SHIFT)) & LPDAC_FSR_SWBK_MASK) - -#define LPDAC_FSR_OF_MASK (0x40U) -#define LPDAC_FSR_OF_SHIFT (6U) -/*! OF - FIFO Overflow Flag - * 0b0..No overflow has occurred since the last time the flag was cleared. - * 0b1..At least one FIFO overflow has occurred since the last time the flag was cleared. - */ -#define LPDAC_FSR_OF(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_OF_SHIFT)) & LPDAC_FSR_OF_MASK) - -#define LPDAC_FSR_UF_MASK (0x80U) -#define LPDAC_FSR_UF_SHIFT (7U) -/*! UF - FIFO Underflow Flag - * 0b0..No underflow has occurred since the last time the flag was cleared. - * 0b1..At least one trigger underflow has occurred since the last time the flag was cleared. - */ -#define LPDAC_FSR_UF(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_UF_SHIFT)) & LPDAC_FSR_UF_MASK) - -#define LPDAC_FSR_PTGCOCO_MASK (0x100U) -#define LPDAC_FSR_PTGCOCO_SHIFT (8U) -/*! PTGCOCO - Period trigger mode conversion complete flag - * 0b0..PTG mode conversion is not completed or not started. - * 0b1..PTG mode conversion is completed. - */ -#define LPDAC_FSR_PTGCOCO(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_PTGCOCO_SHIFT)) & LPDAC_FSR_PTGCOCO_MASK) -/*! @} */ - -/*! @name IER - Interrupt Enable Register */ -/*! @{ */ - -#define LPDAC_IER_FULL_IE_MASK (0x1U) -#define LPDAC_IER_FULL_IE_SHIFT (0U) -/*! FULL_IE - FIFO Full Interrupt Enable - * 0b0..FIFO Full interrupt is disabled. - * 0b1..FIFO Full interrupt is enabled. - */ -#define LPDAC_IER_FULL_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_FULL_IE_SHIFT)) & LPDAC_IER_FULL_IE_MASK) - -#define LPDAC_IER_EMPTY_IE_MASK (0x2U) -#define LPDAC_IER_EMPTY_IE_SHIFT (1U) -/*! EMPTY_IE - FIFO Empty Interrupt Enable - * 0b0..FIFO Empty interrupt is disabled. - * 0b1..FIFO Empty interrupt is enabled. - */ -#define LPDAC_IER_EMPTY_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_EMPTY_IE_SHIFT)) & LPDAC_IER_EMPTY_IE_MASK) - -#define LPDAC_IER_WM_IE_MASK (0x4U) -#define LPDAC_IER_WM_IE_SHIFT (2U) -/*! WM_IE - FIFO Watermark Interrupt Enable - * 0b0..Watermark interrupt is disabled. - * 0b1..Watermark interrupt is enabled. - */ -#define LPDAC_IER_WM_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_WM_IE_SHIFT)) & LPDAC_IER_WM_IE_MASK) - -#define LPDAC_IER_SWBK_IE_MASK (0x8U) -#define LPDAC_IER_SWBK_IE_SHIFT (3U) -/*! SWBK_IE - Swing back One Cycle Complete Interrupt Enable - * 0b0..Swing back one time complete interrupt is disabled. - * 0b1..Swing back one time complete interrupt is enabled. - */ -#define LPDAC_IER_SWBK_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_SWBK_IE_SHIFT)) & LPDAC_IER_SWBK_IE_MASK) - -#define LPDAC_IER_OF_IE_MASK (0x40U) -#define LPDAC_IER_OF_IE_SHIFT (6U) -/*! OF_IE - FIFO Overflow Interrupt Enable - * 0b0..Overflow interrupt is disabled - * 0b1..Overflow interrupt is enabled. - */ -#define LPDAC_IER_OF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_OF_IE_SHIFT)) & LPDAC_IER_OF_IE_MASK) - -#define LPDAC_IER_UF_IE_MASK (0x80U) -#define LPDAC_IER_UF_IE_SHIFT (7U) -/*! UF_IE - FIFO Underflow Interrupt Enable - * 0b0..Underflow interrupt is disabled. - * 0b1..Underflow interrupt is enabled. - */ -#define LPDAC_IER_UF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_UF_IE_SHIFT)) & LPDAC_IER_UF_IE_MASK) - -#define LPDAC_IER_PTGCOCO_IE_MASK (0x100U) -#define LPDAC_IER_PTGCOCO_IE_SHIFT (8U) -/*! PTGCOCO_IE - PTG mode conversion complete interrupt enable - * 0b0..PTG mode conversion complete interrupt is disabled. - * 0b1..PTG mode conversion complete interrupt is enabled. - */ -#define LPDAC_IER_PTGCOCO_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_PTGCOCO_IE_SHIFT)) & LPDAC_IER_PTGCOCO_IE_MASK) -/*! @} */ - -/*! @name DER - DMA Enable Register */ -/*! @{ */ - -#define LPDAC_DER_EMPTY_DMAEN_MASK (0x2U) -#define LPDAC_DER_EMPTY_DMAEN_SHIFT (1U) -/*! EMPTY_DMAEN - FIFO Empty DMA Enable - * 0b0..FIFO Empty DMA request is disabled. - * 0b1..FIFO Empty DMA request is enabled. - */ -#define LPDAC_DER_EMPTY_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_EMPTY_DMAEN_SHIFT)) & LPDAC_DER_EMPTY_DMAEN_MASK) - -#define LPDAC_DER_WM_DMAEN_MASK (0x4U) -#define LPDAC_DER_WM_DMAEN_SHIFT (2U) -/*! WM_DMAEN - FIFO Watermark DMA Enable - * 0b0..Watermark DMA request is disabled. - * 0b1..Watermark DMA request is enabled. - */ -#define LPDAC_DER_WM_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_WM_DMAEN_SHIFT)) & LPDAC_DER_WM_DMAEN_MASK) -/*! @} */ - -/*! @name RCR - Reset Control Register */ -/*! @{ */ - -#define LPDAC_RCR_SWRST_MASK (0x1U) -#define LPDAC_RCR_SWRST_SHIFT (0U) -/*! SWRST - Software Reset - * 0b0..No effect - * 0b1..Software reset - */ -#define LPDAC_RCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_SWRST_SHIFT)) & LPDAC_RCR_SWRST_MASK) - -#define LPDAC_RCR_FIFORST_MASK (0x2U) -#define LPDAC_RCR_FIFORST_SHIFT (1U) -/*! FIFORST - FIFO Reset - * 0b0..No effect - * 0b1..FIFO reset - */ -#define LPDAC_RCR_FIFORST(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_FIFORST_SHIFT)) & LPDAC_RCR_FIFORST_MASK) -/*! @} */ - -/*! @name TCR - Trigger Control Register */ -/*! @{ */ - -#define LPDAC_TCR_SWTRG_MASK (0x1U) -#define LPDAC_TCR_SWTRG_SHIFT (0U) -/*! SWTRG - Software Trigger - * 0b0..The DAC soft trigger is not valid. - * 0b1..The DAC soft trigger is valid. - */ -#define LPDAC_TCR_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_TCR_SWTRG_SHIFT)) & LPDAC_TCR_SWTRG_MASK) -/*! @} */ - -/*! @name PCR - Periodic Trigger Control Register */ -/*! @{ */ - -#define LPDAC_PCR_PTG_NUM_MASK (0xFFFFU) -#define LPDAC_PCR_PTG_NUM_SHIFT (0U) -/*! PTG_NUM - Periodic trigger number - */ -#define LPDAC_PCR_PTG_NUM(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_PCR_PTG_NUM_SHIFT)) & LPDAC_PCR_PTG_NUM_MASK) - -#define LPDAC_PCR_PTG_PERIOD_MASK (0xFFFF0000U) -#define LPDAC_PCR_PTG_PERIOD_SHIFT (16U) -/*! PTG_PERIOD - Periodic trigger period width - */ -#define LPDAC_PCR_PTG_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_PCR_PTG_PERIOD_SHIFT)) & LPDAC_PCR_PTG_PERIOD_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group LPDAC_Register_Masks */ - - -/* LPDAC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral DAC0 base address */ - #define DAC0_BASE (0x500B2000u) - /** Peripheral DAC0 base address */ - #define DAC0_BASE_NS (0x400B2000u) - /** Peripheral DAC0 base pointer */ - #define DAC0 ((LPDAC_Type *)DAC0_BASE) - /** Peripheral DAC0 base pointer */ - #define DAC0_NS ((LPDAC_Type *)DAC0_BASE_NS) - /** Peripheral DAC1 base address */ - #define DAC1_BASE (0x500B6000u) - /** Peripheral DAC1 base address */ - #define DAC1_BASE_NS (0x400B6000u) - /** Peripheral DAC1 base pointer */ - #define DAC1 ((LPDAC_Type *)DAC1_BASE) - /** Peripheral DAC1 base pointer */ - #define DAC1_NS ((LPDAC_Type *)DAC1_BASE_NS) - /** Peripheral DAC2 base address */ - #define DAC2_BASE (0x500B9000u) - /** Peripheral DAC2 base address */ - #define DAC2_BASE_NS (0x400B9000u) - /** Peripheral DAC2 base pointer */ - #define DAC2 ((LPDAC_Type *)DAC2_BASE) - /** Peripheral DAC2 base pointer */ - #define DAC2_NS ((LPDAC_Type *)DAC2_BASE_NS) - /** Array initializer of LPDAC peripheral base addresses */ - #define LPDAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE, DAC2_BASE } - /** Array initializer of LPDAC peripheral base pointers */ - #define LPDAC_BASE_PTRS { DAC0, DAC1, DAC2 } - /** Array initializer of LPDAC peripheral base addresses */ - #define LPDAC_BASE_ADDRS_NS { DAC0_BASE_NS, DAC1_BASE_NS, DAC2_BASE_NS } - /** Array initializer of LPDAC peripheral base pointers */ - #define LPDAC_BASE_PTRS_NS { DAC0_NS, DAC1_NS, DAC2_NS } -#else - /** Peripheral DAC0 base address */ - #define DAC0_BASE (0x400B2000u) - /** Peripheral DAC0 base pointer */ - #define DAC0 ((LPDAC_Type *)DAC0_BASE) - /** Peripheral DAC1 base address */ - #define DAC1_BASE (0x400B6000u) - /** Peripheral DAC1 base pointer */ - #define DAC1 ((LPDAC_Type *)DAC1_BASE) - /** Peripheral DAC2 base address */ - #define DAC2_BASE (0x400B9000u) - /** Peripheral DAC2 base pointer */ - #define DAC2 ((LPDAC_Type *)DAC2_BASE) - /** Array initializer of LPDAC peripheral base addresses */ - #define LPDAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE, DAC2_BASE } - /** Array initializer of LPDAC peripheral base pointers */ - #define LPDAC_BASE_PTRS { DAC0, DAC1, DAC2 } -#endif -/** Interrupt vectors for the LPDAC peripheral type */ -#define LPDAC_IRQS { DAC0_IRQn, DAC1_IRQn, DAC2_IRQn } - -/*! - * @} - */ /* end of group LPDAC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MRT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer - * @{ - */ - -/** MRT - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x10 */ - __IO uint32_t INTVAL; /**< Time Interval Value, array offset: 0x0, array step: 0x10 */ - __I uint32_t TIMER; /**< Timer, array offset: 0x4, array step: 0x10 */ - __IO uint32_t CTRL; /**< Control, array offset: 0x8, array step: 0x10 */ - __IO uint32_t STAT; /**< Status, array offset: 0xC, array step: 0x10 */ - } CHANNEL[4]; - uint8_t RESERVED_0[176]; - __IO uint32_t MODCFG; /**< Module Configuration, offset: 0xF0 */ - __I uint32_t IDLE_CH; /**< Idle Channel, offset: 0xF4 */ - __IO uint32_t IRQ_FLAG; /**< Global Interrupt Flag, offset: 0xF8 */ - __I uint32_t ID_CODE; /**< Multi-Rate Timer ID code, offset: 0xFC */ -} MRT_Type; - -/* ---------------------------------------------------------------------------- - -- MRT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Register_Masks MRT Register Masks - * @{ - */ - -/*! @name CHANNEL_INTVAL - Time Interval Value */ -/*! @{ */ - -#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) -/*! IVALUE - Time interval load value. - */ -#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) - -#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) -#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) -/*! LOAD - Determines how the timer interval value (IVALUE -1) is loaded into the TIMER n register. - * 0b0..No force load. - * 0b1..Force load. T - */ -#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_INTVAL */ -#define MRT_CHANNEL_INTVAL_COUNT (4U) - -/*! @name CHANNEL_TIMER - Timer */ -/*! @{ */ - -#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) -/*! VALUE - Holds the current timer value of the down-counter. - */ -#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_TIMER */ -#define MRT_CHANNEL_TIMER_COUNT (4U) - -/*! @name CHANNEL_CTRL - Control */ -/*! @{ */ - -#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) -#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) -/*! INTEN - Enable the TIMER n interrupt. - * 0b0..Disabled. TIMER n interrupt is disabled. - * 0b1..Enabled. TIMER n interrupt is enabled. - */ -#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) - -#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) -#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) -/*! MODE - Selects the timer mode - * 0b00..Repeat interrupt mode - * 0b01..One-shot interrupt mode - * 0b10..One-shot stall mode - * 0b11..Reserved - */ -#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_CTRL */ -#define MRT_CHANNEL_CTRL_COUNT (4U) - -/*! @name CHANNEL_STAT - Status */ -/*! @{ */ - -#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) -#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) -/*! INTFLAG - Monitors the interrupt flag - * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. - * 0b1..Pending interrupt. - */ -#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) - -#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) -#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) -/*! RUN - Indicates the state of TIMER n. RUN bit is read-only. - * 0b0..Idle state. TIMER n has stopped. - * 0b1..Running. TIMER n is running. - */ -#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) - -#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) -#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) -/*! INUSE - Channel-In-Use flag - * 0b0..This timer channel is not in use. - * 0b1..This timer channel is in use. Writing a 1 to this bit clears the status. - */ -#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_STAT */ -#define MRT_CHANNEL_STAT_COUNT (4U) - -/*! @name MODCFG - Module Configuration */ -/*! @{ */ - -#define MRT_MODCFG_NOC_MASK (0xFU) -#define MRT_MODCFG_NOC_SHIFT (0U) -/*! NOC - Number Of Channels: identifies the number of channels in this MRT. (Minus 1 encoded) - */ -#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) - -#define MRT_MODCFG_NOB_MASK (0x1F0U) -#define MRT_MODCFG_NOB_SHIFT (4U) -/*! NOB - Number Of Bits: identifies the number of timer bits in this MRT. (24 bits on this device) - */ -#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) - -#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) -#define MRT_MODCFG_MULTITASK_SHIFT (31U) -/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. - * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. - * 0b1..Multi-task mode - */ -#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) -/*! @} */ - -/*! @name IDLE_CH - Idle Channel */ -/*! @{ */ - -#define MRT_IDLE_CH_CHAN_MASK (0xF0U) -#define MRT_IDLE_CH_CHAN_SHIFT (4U) -/*! CHAN - Idle channel. - */ -#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) -/*! @} */ - -/*! @name IRQ_FLAG - Global Interrupt Flag */ -/*! @{ */ - -#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) -#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) -/*! GFLAG0 - Monitors the interrupt flag of TIMER0. - * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. - * 0b1..Pending interrupt - */ -#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) - -#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) -#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) -/*! GFLAG1 - Monitors the interrupt flag of TIMER1, and acts similarly to channel 0. - */ -#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) - -#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) -#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) -/*! GFLAG2 - Monitors the interrupt flag of TIMER2, and acts similarly to channel 0. - */ -#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) - -#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) -#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) -/*! GFLAG3 - Monitors the interrupt flag of TIMER3, and acts similarly to channel 0. - */ -#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) -/*! @} */ - -/*! @name ID_CODE - Multi-Rate Timer ID code */ -/*! @{ */ - -#define MRT_ID_CODE_ID_CODE_MASK (0xFFFFFFFFU) -#define MRT_ID_CODE_ID_CODE_SHIFT (0U) -/*! ID_CODE - Multi-Rate Timer ID code - */ -#define MRT_ID_CODE_ID_CODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_ID_CODE_ID_CODE_SHIFT)) & MRT_ID_CODE_ID_CODE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MRT_Register_Masks */ - - -/* MRT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral MRT0 base address */ - #define MRT0_BASE (0x5000D000u) - /** Peripheral MRT0 base address */ - #define MRT0_BASE_NS (0x4000D000u) - /** Peripheral MRT0 base pointer */ - #define MRT0 ((MRT_Type *)MRT0_BASE) - /** Peripheral MRT0 base pointer */ - #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS { MRT0_BASE } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS { MRT0 } - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS_NS { MRT0_NS } -#else - /** Peripheral MRT0 base address */ - #define MRT0_BASE (0x4000D000u) - /** Peripheral MRT0 base pointer */ - #define MRT0 ((MRT_Type *)MRT0_BASE) - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS { MRT0_BASE } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS { MRT0 } -#endif -/** Interrupt vectors for the MRT peripheral type */ -#define MRT_IRQS { MRT0_IRQn } - -/*! - * @} - */ /* end of group MRT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- OPAMP Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OPAMP_Peripheral_Access_Layer OPAMP Peripheral Access Layer - * @{ - */ - -/** OPAMP - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t OPAMP_CTR; /**< OPAMP control register, offset: 0x8 */ -} OPAMP_Type; - -/* ---------------------------------------------------------------------------- - -- OPAMP Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OPAMP_Register_Masks OPAMP Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ - -#define OPAMP_VERID_FEATURE_MASK (0xFFFFU) -#define OPAMP_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Specification Number - */ -#define OPAMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_FEATURE_SHIFT)) & OPAMP_VERID_FEATURE_MASK) - -#define OPAMP_VERID_MINOR_MASK (0xFF0000U) -#define OPAMP_VERID_MINOR_SHIFT (16U) -/*! MINOR - Minor Version Number - */ -#define OPAMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_MINOR_SHIFT)) & OPAMP_VERID_MINOR_MASK) - -#define OPAMP_VERID_MAJOR_MASK (0xFF000000U) -#define OPAMP_VERID_MAJOR_SHIFT (24U) -/*! MAJOR - Major Version Number - */ -#define OPAMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_MAJOR_SHIFT)) & OPAMP_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ - -#define OPAMP_PARAM_PGA_FUNCTION_MASK (0x1U) -#define OPAMP_PARAM_PGA_FUNCTION_SHIFT (0U) -/*! PGA_FUNCTION - PGA Function Option - * 0b0..Core amplifier is enabled. - * 0b1..PGA function is enabled. - */ -#define OPAMP_PARAM_PGA_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_PARAM_PGA_FUNCTION_SHIFT)) & OPAMP_PARAM_PGA_FUNCTION_MASK) -/*! @} */ - -/*! @name OPAMP_CTR - OPAMP control register */ -/*! @{ */ - -#define OPAMP_OPAMP_CTR_EN_MASK (0x1U) -#define OPAMP_OPAMP_CTR_EN_SHIFT (0U) -/*! EN - OPAMP Enable - * 0b0..OPAMP is disabled - * 0b1..OPAMP is enabled - */ -#define OPAMP_OPAMP_CTR_EN(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_EN_SHIFT)) & OPAMP_OPAMP_CTR_EN_MASK) - -#define OPAMP_OPAMP_CTR_MODE_MASK (0x2U) -#define OPAMP_OPAMP_CTR_MODE_SHIFT (1U) -/*! MODE - Mode Selection - * 0b0..Low noise mode. - * 0b1..High speed mode. - */ -#define OPAMP_OPAMP_CTR_MODE(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_MODE_SHIFT)) & OPAMP_OPAMP_CTR_MODE_MASK) - -#define OPAMP_OPAMP_CTR_BIASC_MASK (0xCU) -#define OPAMP_OPAMP_CTR_BIASC_SHIFT (2U) -/*! BIASC - Bias Current Trim Selection - * 0b00..Default. - * 0b01..Increase current. - * 0b10..Decrease current. - * 0b11..Further decrease current. - */ -#define OPAMP_OPAMP_CTR_BIASC(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_BIASC_SHIFT)) & OPAMP_OPAMP_CTR_BIASC_MASK) - -#define OPAMP_OPAMP_CTR_INTREF_MASK (0x30U) -#define OPAMP_OPAMP_CTR_INTREF_SHIFT (4U) -/*! INTREF - Internal Reference Voltage Selection - * 0b00..Select vdda/2. - * 0b01..Select vdda_3v. - * 0b10..Select vssa_3v. - * 0b11..Not allowed. - */ -#define OPAMP_OPAMP_CTR_INTREF(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_INTREF_SHIFT)) & OPAMP_OPAMP_CTR_INTREF_MASK) - -#define OPAMP_OPAMP_CTR_ADCSW_MASK (0x10000U) -#define OPAMP_OPAMP_CTR_ADCSW_SHIFT (16U) -/*! ADCSW - ADC Channel Switch - */ -#define OPAMP_OPAMP_CTR_ADCSW(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_ADCSW_SHIFT)) & OPAMP_OPAMP_CTR_ADCSW_MASK) - -#define OPAMP_OPAMP_CTR_PREF_MASK (0x60000U) -#define OPAMP_OPAMP_CTR_PREF_SHIFT (17U) -/*! PREF - Positive Reference Voltage Selection - * 0b00..Select vrefh3. - * 0b01..Select vrefh0. - * 0b10..Select vrefh1. - * 0b11..Reserved. - */ -#define OPAMP_OPAMP_CTR_PREF(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_PREF_SHIFT)) & OPAMP_OPAMP_CTR_PREF_MASK) - -#define OPAMP_OPAMP_CTR_PGAIN_MASK (0x700000U) -#define OPAMP_OPAMP_CTR_PGAIN_SHIFT (20U) -/*! PGAIN - Positive PGA Selection. - * 0b000..Reserved. - * 0b001..Inverting gain application 2X. - * 0b010..Inverting gain application 3X. - * 0b011..Inverting gain application 5X. - * 0b100..Inverting gain application 9X. - * 0b101..Inverting gain application 17X. - * 0b110..Inverting gain application 34X. - * 0b111..Inverting gain application 65X. - */ -#define OPAMP_OPAMP_CTR_PGAIN(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_PGAIN_SHIFT)) & OPAMP_OPAMP_CTR_PGAIN_MASK) - -#define OPAMP_OPAMP_CTR_NGAIN_MASK (0x7000000U) -#define OPAMP_OPAMP_CTR_NGAIN_SHIFT (24U) -/*! NGAIN - Negative PGA selection - * 0b000..Buffer. - * 0b001..Inverting gain application -1X. - * 0b010..Inverting gain application -2X. - * 0b011..Inverting gain application -4X. - * 0b100..Inverting gain application -8X. - * 0b101..Inverting gain application -16X. - * 0b110..Inverting gain application -33X. - * 0b111..Inverting gain application -64X. - */ -#define OPAMP_OPAMP_CTR_NGAIN(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_NGAIN_SHIFT)) & OPAMP_OPAMP_CTR_NGAIN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group OPAMP_Register_Masks */ - - -/* OPAMP - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral OPAMP0 base address */ - #define OPAMP0_BASE (0x500B4000u) - /** Peripheral OPAMP0 base address */ - #define OPAMP0_BASE_NS (0x400B4000u) - /** Peripheral OPAMP0 base pointer */ - #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) - /** Peripheral OPAMP0 base pointer */ - #define OPAMP0_NS ((OPAMP_Type *)OPAMP0_BASE_NS) - /** Peripheral OPAMP1 base address */ - #define OPAMP1_BASE (0x500B8000u) - /** Peripheral OPAMP1 base address */ - #define OPAMP1_BASE_NS (0x400B8000u) - /** Peripheral OPAMP1 base pointer */ - #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) - /** Peripheral OPAMP1 base pointer */ - #define OPAMP1_NS ((OPAMP_Type *)OPAMP1_BASE_NS) - /** Peripheral OPAMP2 base address */ - #define OPAMP2_BASE (0x500BB000u) - /** Peripheral OPAMP2 base address */ - #define OPAMP2_BASE_NS (0x400BB000u) - /** Peripheral OPAMP2 base pointer */ - #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) - /** Peripheral OPAMP2 base pointer */ - #define OPAMP2_NS ((OPAMP_Type *)OPAMP2_BASE_NS) - /** Array initializer of OPAMP peripheral base addresses */ - #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } - /** Array initializer of OPAMP peripheral base pointers */ - #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } - /** Array initializer of OPAMP peripheral base addresses */ - #define OPAMP_BASE_ADDRS_NS { OPAMP0_BASE_NS, OPAMP1_BASE_NS, OPAMP2_BASE_NS } - /** Array initializer of OPAMP peripheral base pointers */ - #define OPAMP_BASE_PTRS_NS { OPAMP0_NS, OPAMP1_NS, OPAMP2_NS } -#else - /** Peripheral OPAMP0 base address */ - #define OPAMP0_BASE (0x400B4000u) - /** Peripheral OPAMP0 base pointer */ - #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) - /** Peripheral OPAMP1 base address */ - #define OPAMP1_BASE (0x400B8000u) - /** Peripheral OPAMP1 base pointer */ - #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) - /** Peripheral OPAMP2 base address */ - #define OPAMP2_BASE (0x400BB000u) - /** Peripheral OPAMP2 base pointer */ - #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) - /** Array initializer of OPAMP peripheral base addresses */ - #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } - /** Array initializer of OPAMP peripheral base pointers */ - #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } -#endif - -/*! - * @} - */ /* end of group OPAMP_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- OSTIMER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer - * @{ - */ - -/** OSTIMER - Register Layout Typedef */ -typedef struct { - __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */ - __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */ - __I uint32_t CAPTURE_L; /**< Local Capture Low Register for CPU, offset: 0x8 */ - __I uint32_t CAPTURE_H; /**< Local Capture High Register for CPU, offset: 0xC */ - __IO uint32_t MATCH_L; /**< Local Match Low Register for CPU, offset: 0x10 */ - __IO uint32_t MATCH_H; /**< Local Match High Register for CPU, offset: 0x14 */ - uint8_t RESERVED_0[4]; - __IO uint32_t OSEVENT_CTRL; /**< OS Event Timer Control Register for CPU, offset: 0x1C */ -} OSTIMER_Type; - -/* ---------------------------------------------------------------------------- - -- OSTIMER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks - * @{ - */ - -/*! @name EVTIMERL - EVTIMER Low Register */ -/*! @{ */ - -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) -/*! EVTIMER_COUNT_VALUE - EVTimer Count value - */ -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) -/*! @} */ - -/*! @name EVTIMERH - EVTIMER High Register */ -/*! @{ */ - -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) -/*! EVTIMER_COUNT_VALUE - EVTimer Count value - */ -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) -/*! @} */ - -/*! @name CAPTURE_L - Local Capture Low Register for CPU */ -/*! @{ */ - -#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U) -/*! CAPTURE_VALUE - EVTimer Capture value - */ -#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK) -/*! @} */ - -/*! @name CAPTURE_H - Local Capture High Register for CPU */ -/*! @{ */ - -#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U) -/*! CAPTURE_VALUE - EVTimer Capture value - */ -#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK) -/*! @} */ - -/*! @name MATCH_L - Local Match Low Register for CPU */ -/*! @{ */ - -#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U) -/*! MATCH_VALUE - EVTimer Match value - */ -#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK) -/*! @} */ - -/*! @name MATCH_H - Local Match High Register for CPU */ -/*! @{ */ - -#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U) -/*! MATCH_VALUE - EVTimer Match value - */ -#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK) -/*! @} */ - -/*! @name OSEVENT_CTRL - OS Event Timer Control Register for CPU */ -/*! @{ */ - -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) -/*! OSTIMER_INTRFLAG - Interrupt Flag - */ -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) - -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) -/*! OSTIMER_INTENA - Interrupt/Wake-up Request - * 0b0..Interrupt/wake-up requests due to the OSTIMER_INTR flag are blocked. - * 0b1..An interrupt/wake-up request to the domain processor will be asserted when the OSTIMER_INTR flag is set. - */ -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) - -#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U) -#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U) -/*! MATCH_WR_RDY - EVTimer Match Write Ready - */ -#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group OSTIMER_Register_Masks */ - - -/* OSTIMER - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral OSTIMER0 base address */ - #define OSTIMER0_BASE (0x5002D000u) - /** Peripheral OSTIMER0 base address */ - #define OSTIMER0_BASE_NS (0x4002D000u) - /** Peripheral OSTIMER0 base pointer */ - #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) - /** Peripheral OSTIMER0 base pointer */ - #define OSTIMER0_NS ((OSTIMER_Type *)OSTIMER0_BASE_NS) - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS { OSTIMER0 } - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS_NS { OSTIMER0_BASE_NS } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS_NS { OSTIMER0_NS } -#else - /** Peripheral OSTIMER0 base address */ - #define OSTIMER0_BASE (0x4002D000u) - /** Peripheral OSTIMER0 base pointer */ - #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS { OSTIMER0 } -#endif -/** Interrupt vectors for the OSTIMER peripheral type */ -#define OSTIMER_IRQS { OS_EVENT_IRQn } - -/*! - * @} - */ /* end of group OSTIMER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer - * @{ - */ - -/** PINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t ISEL; /**< Pin Interrupt Mode, offset: 0x0 */ - __IO uint32_t IENR; /**< Pin Interrupt Level or Rising Edge Interrupt Enable, offset: 0x4 */ - __O uint32_t SIENR; /**< Pin Interrupt Level or Rising Edge Interrupt Set, offset: 0x8 */ - __IO uint32_t CIENR; /**< Pin Interrupt Level (Rising Edge Interrupt) Clear, offset: 0xC */ - __IO uint32_t IENF; /**< Pin Interrupt Active Level or Falling Edge Interrupt Enable, offset: 0x10 */ - __O uint32_t SIENF; /**< Pin Interrupt Active Level or Falling Edge Interrupt Set, offset: 0x14 */ - __O uint32_t CIENF; /**< Pin Interrupt Active Level or Falling Edge Interrupt Clear, offset: 0x18 */ - __IO uint32_t RISE; /**< Pin Interrupt Rising Edge, offset: 0x1C */ - __IO uint32_t FALL; /**< Pin Interrupt Falling Edge, offset: 0x20 */ - __IO uint32_t IST; /**< Pin Interrupt Status, offset: 0x24 */ - __IO uint32_t PMCTRL; /**< Pattern Match Interrupt Control, offset: 0x28 */ - __IO uint32_t PMSRC; /**< Pattern Match Interrupt Bit-Slice Source, offset: 0x2C */ - __IO uint32_t PMCFG; /**< Pattern Match Interrupt Bit Slice Configuration, offset: 0x30 */ -} PINT_Type; - -/* ---------------------------------------------------------------------------- - -- PINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Register_Masks PINT Register Masks - * @{ - */ - -/*! @name ISEL - Pin Interrupt Mode */ -/*! @{ */ - -#define PINT_ISEL_PMODE_MASK (0xFFU) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ -#define PINT_ISEL_PMODE_SHIFT (0U) -/*! PMODE - Interrupt mode - * 0b00000000..Edge-sensitive - * 0b00000001..Level-sensitive - */ -#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ -/*! @} */ - -/*! @name IENR - Pin Interrupt Level or Rising Edge Interrupt Enable */ -/*! @{ */ - -#define PINT_IENR_ENRL_MASK (0xFFU) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ -#define PINT_IENR_ENRL_SHIFT (0U) -/*! ENRL - Enable Interrupt - * 0b00000000..Disable rising edge or level interrupt - * 0b00000001..Enable rising edge or level interrupt - */ -#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ -/*! @} */ - -/*! @name SIENR - Pin Interrupt Level or Rising Edge Interrupt Set */ -/*! @{ */ - -#define PINT_SIENR_SETENRL_MASK (0xFFU) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ -#define PINT_SIENR_SETENRL_SHIFT (0U) -/*! SETENRL - Set bits in the IENR - * 0b00000000..No operation - * 0b00000001..Enable rising edge or level interrupt - */ -#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ -/*! @} */ - -/*! @name CIENR - Pin Interrupt Level (Rising Edge Interrupt) Clear */ -/*! @{ */ - -#define PINT_CIENR_CENRL_MASK (0xFFU) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ -#define PINT_CIENR_CENRL_SHIFT (0U) -/*! CENRL - Clear bits in the IENR - * 0b00000000..No operation - * 0b00000001..Disable rising edge or level interrupt - */ -#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ -/*! @} */ - -/*! @name IENF - Pin Interrupt Active Level or Falling Edge Interrupt Enable */ -/*! @{ */ - -#define PINT_IENF_ENAF_MASK (0xFFU) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ -#define PINT_IENF_ENAF_SHIFT (0U) -/*! ENAF - Enable Interrupt - * 0b00000000..Disable falling edge interrupt or set active interrupt level LOW - * 0b00000001..Enable falling edge interrupt enabled or set active interrupt level HIGH - */ -#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ -/*! @} */ - -/*! @name SIENF - Pin Interrupt Active Level or Falling Edge Interrupt Set */ -/*! @{ */ - -#define PINT_SIENF_SETENAF_MASK (0xFFU) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ -#define PINT_SIENF_SETENAF_SHIFT (0U) -/*! SETENAF - Set bits in the IENF - * 0b00000000..No operation - * 0b00000001..Select HIGH-active interrupt or enable falling edge interrupt - */ -#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ -/*! @} */ - -/*! @name CIENF - Pin Interrupt Active Level or Falling Edge Interrupt Clear */ -/*! @{ */ - -#define PINT_CIENF_CENAF_MASK (0xFFU) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ -#define PINT_CIENF_CENAF_SHIFT (0U) -/*! CENAF - Clear bits in the IENF - * 0b00000000..No operation - * 0b00000001..LOW-active interrupt selected or falling edge interrupt disabled - */ -#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ -/*! @} */ - -/*! @name RISE - Pin Interrupt Rising Edge */ -/*! @{ */ - -#define PINT_RISE_RDET_MASK (0xFFU) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ -#define PINT_RISE_RDET_SHIFT (0U) -/*! RDET - Rising edge detect - * 0b00000000..Read 0- No rising edge has been detected on this pin since Reset or the last time a one was written to this bit, Write 0- no operation - * 0b00000001..Read 1- a rising edge has been detected since Reset or the last time a one was written to this - * bit, Write 1- clear rising edge detection for this pin - */ -#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ -/*! @} */ - -/*! @name FALL - Pin Interrupt Falling Edge */ -/*! @{ */ - -#define PINT_FALL_FDET_MASK (0xFFU) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ -#define PINT_FALL_FDET_SHIFT (0U) -/*! FDET - Falling edge detect - * 0b00000000..Read 0- No falling edge has been detected on this pin since Reset or the last time a one was written to this bit, Write 0- no operation - * 0b00000001..Read 1- a falling edge has been detected since Reset or the last time a one was written to this - * bit, Write 1- clear falling edge detection for this bit - */ -#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ -/*! @} */ - -/*! @name IST - Pin Interrupt Status */ -/*! @{ */ - -#define PINT_IST_PSTAT_MASK (0xFFU) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ -#define PINT_IST_PSTAT_SHIFT (0U) -/*! PSTAT - Pin interrupt status - * 0b00000000..Read 0- interrupt is not being requested for this pin, Write 0- no operation. - * 0b00000001..Read 1- interrupt is being requested for this pin, Write 1 (edge-sensitive)- clear rising- and - * falling-edge detection for this pin, Write 1 (level-sensitive)- switch the active level for this pin - * (in the IENF register). - */ -#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ -/*! @} */ - -/*! @name PMCTRL - Pattern Match Interrupt Control */ -/*! @{ */ - -#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) -#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) -/*! SEL_PMATCH - Specifies whether the pin interrupts are controlled by the pin interrupt function or by the pattern match function. - * 0b0..Pin interrupt- interrupts are driven in response to the standard pin interrupt function. - * 0b1..Pattern match- interrupts are driven in response to pattern matches. - */ -#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) - -#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) -#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) -/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output, when the specified boolean expression evaluates to true. - * 0b0..Disabled- RXEV output to the CPU is disabled. - * 0b1..Enabled- RXEV output to the CPU is enabled. - */ -#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) - -#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) -#define PINT_PMCTRL_PMAT_SHIFT (24U) -/*! PMAT - Pattern Matches - * 0b00000001..The corresponding product term is matched by the current state of the appropriate inputs. - */ -#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) -/*! @} */ - -/*! @name PMSRC - Pattern Match Interrupt Bit-Slice Source */ -/*! @{ */ - -#define PINT_PMSRC_SRC0_MASK (0x700U) -#define PINT_PMSRC_SRC0_SHIFT (8U) -/*! SRC0 - Selects the input source for bit slice 0 - * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n. - * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n. - * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n. - * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n. - * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n. - * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n. - * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n. - * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n. - */ -#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) - -#define PINT_PMSRC_SRC1_MASK (0x3800U) -#define PINT_PMSRC_SRC1_SHIFT (11U) -/*! SRC1 - Selects the input source for bit slice 1 - * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n. - * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n. - * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n. - * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n. - * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n. - * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n. - * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n. - * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n. - */ -#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) - -#define PINT_PMSRC_SRC2_MASK (0x1C000U) -#define PINT_PMSRC_SRC2_SHIFT (14U) -/*! SRC2 - Selects the input source for bit slice 2 - * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n. - * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n. - * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n. - * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n. - * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n. - * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n. - * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n. - * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n. - */ -#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) - -#define PINT_PMSRC_SRC3_MASK (0xE0000U) -#define PINT_PMSRC_SRC3_SHIFT (17U) -/*! SRC3 - Selects the input source for bit slice 3 - * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n. - * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n. - * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n. - * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n. - * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n. - * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n. - * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n. - * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n. - */ -#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) - -#define PINT_PMSRC_SRC4_MASK (0x700000U) -#define PINT_PMSRC_SRC4_SHIFT (20U) -/*! SRC4 - Selects the input source for bit slice 4 - * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n. - * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n. - * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n. - * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n. - * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n. - * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n. - * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n. - * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n. - */ -#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) - -#define PINT_PMSRC_SRC5_MASK (0x3800000U) -#define PINT_PMSRC_SRC5_SHIFT (23U) -/*! SRC5 - Selects the input source for bit slice 5 - * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n. - * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n. - * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n. - * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n. - * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n. - * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n. - * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n. - * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n. - */ -#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) - -#define PINT_PMSRC_SRC6_MASK (0x1C000000U) -#define PINT_PMSRC_SRC6_SHIFT (26U) -/*! SRC6 - Selects the input source for bit slice 6 - * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n. - * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n. - * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n. - * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n. - * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n. - * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n. - * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n. - * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n. - */ -#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) - -#define PINT_PMSRC_SRC7_MASK (0xE0000000U) -#define PINT_PMSRC_SRC7_SHIFT (29U) -/*! SRC7 - Selects the input source for bit slice 7 - * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n. - * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n. - * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n. - * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n. - * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n. - * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n. - * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n. - * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n. - */ -#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) -/*! @} */ - -/*! @name PMCFG - Pattern Match Interrupt Bit Slice Configuration */ -/*! @{ */ - -#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) -#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) -/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. - * 0b0..No effect. Slice 0 is not an endpoint. - * 0b1..Endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) - -#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) -#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) -/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. - * 0b0..No effect. Slice 1 is not an endpoint. - * 0b1..Endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) - -#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) -#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) -/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. - * 0b0..No effect. Slice 2 is not an endpoint. - * 0b1..Endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) - -#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) -#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) -/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. - * 0b0..No effect. Slice 3 is not an endpoint. - * 0b1..Endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) - -#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) -#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) -/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. - * 0b0..No effect. Slice 4 is not an endpoint. - * 0b1..Endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) - -#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) -#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) -/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. - * 0b0..No effect. Slice 5 is not an endpoint. - * 0b1..Endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) - -#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) -#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) -/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. - * 0b0..No effect. Slice 6 is not an endpoint. - * 0b1..Endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) - -#define PINT_PMCFG_CFG0_MASK (0x700U) -#define PINT_PMCFG_CFG0_SHIFT (8U) -/*! CFG0 - Specifies the match contribution condition for bit slice 0. - * 0b000..Constant HIGH - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This match condition is only cleared when the - * PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This match condition is only cleared when the - * PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This match condition - * is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge - * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is - * cleared after 1 clock cycle. - */ -#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) - -#define PINT_PMCFG_CFG1_MASK (0x3800U) -#define PINT_PMCFG_CFG1_SHIFT (11U) -/*! CFG1 - Specifies the match contribution condition for bit slice 1. - * 0b000..Constant HIGH - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This match condition is only cleared when the - * PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This match condition is only cleared when the - * PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This match condition - * is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge - * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is - * cleared after 1 clock cycle. - */ -#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) - -#define PINT_PMCFG_CFG2_MASK (0x1C000U) -#define PINT_PMCFG_CFG2_SHIFT (14U) -/*! CFG2 - Specifies the match contribution condition for bit slice 2. - * 0b000..Constant HIGH - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This match condition is only cleared when the - * PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This match condition is only cleared when the - * PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This match condition - * is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge - * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is - * cleared after 1 clock cycle. - */ -#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) - -#define PINT_PMCFG_CFG3_MASK (0xE0000U) -#define PINT_PMCFG_CFG3_SHIFT (17U) -/*! CFG3 - Specifies the match contribution condition for bit slice 3. - * 0b000..Constant HIGH - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This match condition is only cleared when the - * PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This match condition is only cleared when the - * PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This match condition - * is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge - * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is - * cleared after 1 clock cycle. - */ -#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) - -#define PINT_PMCFG_CFG4_MASK (0x700000U) -#define PINT_PMCFG_CFG4_SHIFT (20U) -/*! CFG4 - Specifies the match contribution condition for bit slice 4. - * 0b000..Constant HIGH - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This match condition is only cleared when the - * PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This match condition is only cleared when the - * PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This match condition - * is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge - * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is - * cleared after 1 clock cycle. - */ -#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) - -#define PINT_PMCFG_CFG5_MASK (0x3800000U) -#define PINT_PMCFG_CFG5_SHIFT (23U) -/*! CFG5 - Specifies the match contribution condition for bit slice 5. - * 0b000..Constant HIGH - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This match condition is only cleared when the - * PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This match condition is only cleared when the - * PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This match condition - * is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge - * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is - * cleared after 1 clock cycle. - */ -#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) - -#define PINT_PMCFG_CFG6_MASK (0x1C000000U) -#define PINT_PMCFG_CFG6_SHIFT (26U) -/*! CFG6 - Specifies the match contribution condition for bit slice 6. - * 0b000..Constant HIGH - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This match condition is only cleared when the - * PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This match condition is only cleared when the - * PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This match condition - * is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge - * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is - * cleared after 1 clock cycle. - */ -#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) - -#define PINT_PMCFG_CFG7_MASK (0xE0000000U) -#define PINT_PMCFG_CFG7_SHIFT (29U) -/*! CFG7 - Specifies the match contribution condition for bit slice 7. - * 0b000..Constant HIGH - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This match condition is only cleared when the - * PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This match condition is only cleared when the - * PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This match condition - * is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge - * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is - * cleared after 1 clock cycle. - */ -#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PINT_Register_Masks */ - - -/* PINT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PINT base address */ - #define PINT_BASE (0x50004000u) - /** Peripheral PINT base address */ - #define PINT_BASE_NS (0x40004000u) - /** Peripheral PINT base pointer */ - #define PINT ((PINT_Type *)PINT_BASE) - /** Peripheral PINT base pointer */ - #define PINT_NS ((PINT_Type *)PINT_BASE_NS) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE (0x50005000u) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE_NS (0x40005000u) - /** Peripheral SECPINT base pointer */ - #define SECPINT ((PINT_Type *)SECPINT_BASE) - /** Peripheral SECPINT base pointer */ - #define SECPINT_NS ((PINT_Type *)SECPINT_BASE_NS) - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS { PINT, SECPINT } - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS_NS { PINT_BASE_NS, SECPINT_BASE_NS } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS_NS { PINT_NS, SECPINT_NS } -#else - /** Peripheral PINT base address */ - #define PINT_BASE (0x40004000u) - /** Peripheral PINT base pointer */ - #define PINT ((PINT_Type *)PINT_BASE) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE (0x40005000u) - /** Peripheral SECPINT base pointer */ - #define SECPINT ((PINT_Type *)SECPINT_BASE) - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS { PINT, SECPINT } -#endif -/** Interrupt vectors for the PINT peripheral type */ -#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn } - -/*! - * @} - */ /* end of group PINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PKC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PKC_Peripheral_Access_Layer PKC Peripheral Access Layer - * @{ - */ - -/** PKC - Register Layout Typedef */ -typedef struct { - __I uint32_t PKC_STATUS; /**< Status register, offset: 0x0 */ - __IO uint32_t PKC_CTRL; /**< Control register, offset: 0x4 */ - __IO uint32_t PKC_CFG; /**< Configuration register, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t PKC_MODE1; /**< Mode register, parameter set 1, offset: 0x10 */ - __IO uint32_t PKC_XYPTR1; /**< X+Y pointer register, parameter set 1, offset: 0x14 */ - __IO uint32_t PKC_ZRPTR1; /**< Z+R pointer register, parameter set 1, offset: 0x18 */ - __IO uint32_t PKC_LEN1; /**< Length register, parameter set 1, offset: 0x1C */ - __IO uint32_t PKC_MODE2; /**< Mode register, parameter set 2, offset: 0x20 */ - __IO uint32_t PKC_XYPTR2; /**< X+Y pointer register, parameter set 2, offset: 0x24 */ - __IO uint32_t PKC_ZRPTR2; /**< Z+R pointer register, parameter set 2, offset: 0x28 */ - __IO uint32_t PKC_LEN2; /**< Length register, parameter set 2, offset: 0x2C */ - uint8_t RESERVED_1[16]; - __IO uint32_t PKC_UPTR; /**< Universal pointer FUP program, offset: 0x40 */ - __IO uint32_t PKC_UPTRT; /**< Universal pointer FUP table, offset: 0x44 */ - __IO uint32_t PKC_ULEN; /**< Universal pointer length, offset: 0x48 */ - uint8_t RESERVED_2[4]; - __IO uint32_t PKC_MCDATA; /**< MC pattern data interface, offset: 0x50 */ - uint8_t RESERVED_3[12]; - __I uint32_t PKC_VERSION; /**< PKC version register, offset: 0x60 */ - uint8_t RESERVED_4[3916]; - __O uint32_t PKC_SOFT_RST; /**< Software reset, offset: 0xFB0 */ - uint8_t RESERVED_5[12]; - __I uint32_t PKC_ACCESS_ERR; /**< Access Error, offset: 0xFC0 */ - __O uint32_t PKC_ACCESS_ERR_CLR; /**< Clear Access Error, offset: 0xFC4 */ - uint8_t RESERVED_6[16]; - __O uint32_t PKC_INT_CLR_ENABLE; /**< Interrupt enable clear, offset: 0xFD8 */ - __O uint32_t PKC_INT_SET_ENABLE; /**< Interrupt enable set, offset: 0xFDC */ - __I uint32_t PKC_INT_STATUS; /**< Interrupt status, offset: 0xFE0 */ - __I uint32_t PKC_INT_ENABLE; /**< Interrupt enable, offset: 0xFE4 */ - __O uint32_t PKC_INT_CLR_STATUS; /**< Interrupt status clear, offset: 0xFE8 */ - __O uint32_t PKC_INT_SET_STATUS; /**< Interrupt status set, offset: 0xFEC */ - uint8_t RESERVED_7[12]; - __I uint32_t PKC_MODULE_ID; /**< Module ID, offset: 0xFFC */ -} PKC_Type; - -/* ---------------------------------------------------------------------------- - -- PKC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PKC_Register_Masks PKC Register Masks - * @{ - */ - -/*! @name PKC_STATUS - Status register */ -/*! @{ */ - -#define PKC_PKC_STATUS_activ_MASK (0x1U) -#define PKC_PKC_STATUS_activ_SHIFT (0U) -/*! activ - PKC active: ACTIV=1 signals that a calculation is in progress or about to start. At the - * end of a calculation ACTIV is automatically reset to logic 0 in case no further GO bit is set. - * If the next PKC operation has been started by setting a GO bit during a calculation, ACTIV - * remains high. ACTIV is always '1' in case PKC_STATUS.GOANY is set. ACTIV is always '0' in case - * PKC_CTRL_RESET is set. - */ -#define PKC_PKC_STATUS_activ(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_activ_SHIFT)) & PKC_PKC_STATUS_activ_MASK) - -#define PKC_PKC_STATUS_carry_MASK (0x2U) -#define PKC_PKC_STATUS_carry_SHIFT (1U) -/*! carry - Carry overflow flag: CARRY is set by the PKC at the end of a calculation in case - */ -#define PKC_PKC_STATUS_carry(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_carry_SHIFT)) & PKC_PKC_STATUS_carry_MASK) - -#define PKC_PKC_STATUS_zero_MASK (0x4U) -#define PKC_PKC_STATUS_zero_SHIFT (2U) -/*! zero - Zero result flag: ZERO is set by the PKC at the end of a calculation in case the result - * of the calculation is equal zero. ZERO is updated for each PKC calculation mode, except for - * MUL1 (opcode 0x20) and MUL1_GF2 (opcode 0x24). - */ -#define PKC_PKC_STATUS_zero(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_zero_SHIFT)) & PKC_PKC_STATUS_zero_MASK) - -#define PKC_PKC_STATUS_goany_MASK (0x8U) -#define PKC_PKC_STATUS_goany_SHIFT (3U) -/*! goany - Combined GO status flag: GOANY is set in case either PKC_CTRL.GOD1, GOD2, GOM1, GOM2 or - * GOU is set. The 1-to-0 transition of GOANY indicates that a calculation has been started and - * that a new GO bit can be set. If GOANY is cleared also all PKC_STATUS.LOCKED bits are cleared - * to indicate that the parameter set can be updated. GOANY is always '0' in case PKC_CTRL.RESET - * is set. - */ -#define PKC_PKC_STATUS_goany(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_goany_SHIFT)) & PKC_PKC_STATUS_goany_MASK) - -#define PKC_PKC_STATUS_reserved4_MASK (0x10U) -#define PKC_PKC_STATUS_reserved4_SHIFT (4U) -/*! reserved4 - reserved - */ -#define PKC_PKC_STATUS_reserved4(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_reserved4_SHIFT)) & PKC_PKC_STATUS_reserved4_MASK) - -#define PKC_PKC_STATUS_locked_MASK (0x60U) -#define PKC_PKC_STATUS_locked_SHIFT (5U) -/*! locked - Parameter set locked: Indicates if parameter set is locked due to a pending calculation start or can be overwritten. - */ -#define PKC_PKC_STATUS_locked(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_locked_SHIFT)) & PKC_PKC_STATUS_locked_MASK) - -#define PKC_PKC_STATUS_reserved31_MASK (0xFFFFFF80U) -#define PKC_PKC_STATUS_reserved31_SHIFT (7U) -/*! reserved31 - reserved - */ -#define PKC_PKC_STATUS_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_reserved31_SHIFT)) & PKC_PKC_STATUS_reserved31_MASK) -/*! @} */ - -/*! @name PKC_CTRL - Control register */ -/*! @{ */ - -#define PKC_PKC_CTRL_reset_MASK (0x1U) -#define PKC_PKC_CTRL_reset_SHIFT (0U) -/*! reset - PKC reset control bit: RESET=1 enforces the PKC's reset state during which a calculation - * cannot be started and by which any ongoing calculation process is stopped. RESET can be - * set/cleared by the CPU in order to switch between PKC reset and calculation enable. RESET=1 is the - * default state after a chip reset. - */ -#define PKC_PKC_CTRL_reset(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_reset_SHIFT)) & PKC_PKC_CTRL_reset_MASK) - -#define PKC_PKC_CTRL_stop_MASK (0x2U) -#define PKC_PKC_CTRL_stop_SHIFT (1U) -/*! stop - Freeze PKC calculation: STOP=1 freezes all PKC activity incl. RAM accesses and reduces - * the PKC power consumption to its minimum. The difference compared to the reset of the PKC is - * that a stopped calculation can be continued when STOP is released (reset to '0') again. The - * status flags are not affected by the STOP control bit. - */ -#define PKC_PKC_CTRL_stop(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_stop_SHIFT)) & PKC_PKC_CTRL_stop_MASK) - -#define PKC_PKC_CTRL_god1_MASK (0x4U) -#define PKC_PKC_CTRL_god1_SHIFT (2U) -/*! god1 - Control bit to start direct operation using parameter set 1: If GOD1 is set PKC will - * start a direct / layer0 operation using parameter set 1 (PKC_MODE1, PKC_XYPTR1, PKC_ZRPTR1, - * PKC_LEN1). - */ -#define PKC_PKC_CTRL_god1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_god1_SHIFT)) & PKC_PKC_CTRL_god1_MASK) - -#define PKC_PKC_CTRL_god2_MASK (0x8U) -#define PKC_PKC_CTRL_god2_SHIFT (3U) -/*! god2 - Control bit to start direct operation using parameter set 2: If GOD2 is set PKC will - * start a direct / layer0 operation using parameter set 2 (PKC_MODE2, PKC_XYPTR2, PKC_ZRPTR2, - * PKC_LEN2). - */ -#define PKC_PKC_CTRL_god2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_god2_SHIFT)) & PKC_PKC_CTRL_god2_MASK) - -#define PKC_PKC_CTRL_gom1_MASK (0x10U) -#define PKC_PKC_CTRL_gom1_SHIFT (4U) -/*! gom1 - Control bit to start MC pattern using parameter set 1: If GOM1 is set PKC will start a MC - * pattern / layer1 operation using parameter set 1 (PKC_MODE1, PKC_XYPTR1, PKC_ZRPTR1, - * PKC_LEN1). - */ -#define PKC_PKC_CTRL_gom1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_gom1_SHIFT)) & PKC_PKC_CTRL_gom1_MASK) - -#define PKC_PKC_CTRL_gom2_MASK (0x20U) -#define PKC_PKC_CTRL_gom2_SHIFT (5U) -/*! gom2 - Control bit to start MC pattern using parameter set 2: If GOM2 is set PKC will start a MC - * pattern / layer1 operation using parameter set 2 (PKC_MODE2, PKC_XYPTR2, PKC_ZRPTR2, - * PKC_LEN2). - */ -#define PKC_PKC_CTRL_gom2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_gom2_SHIFT)) & PKC_PKC_CTRL_gom2_MASK) - -#define PKC_PKC_CTRL_gou_MASK (0x40U) -#define PKC_PKC_CTRL_gou_SHIFT (6U) -/*! gou - Control bit to start pipe operation: If GOU is set PKC will start the pipe / layer2 - * operation (parameter fetch & calculation) described in section 'PKC Universal Pointer Fetch - * Operation'. - */ -#define PKC_PKC_CTRL_gou(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_gou_SHIFT)) & PKC_PKC_CTRL_gou_MASK) - -#define PKC_PKC_CTRL_gf2conv_MASK (0x80U) -#define PKC_PKC_CTRL_gf2conv_SHIFT (7U) -/*! gf2conv - Convert to GF2 calculation modes: If GF2CONV is set operations are mapped to their GF(2) equivalent operation modes. - */ -#define PKC_PKC_CTRL_gf2conv(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_gf2conv_SHIFT)) & PKC_PKC_CTRL_gf2conv_MASK) - -#define PKC_PKC_CTRL_clrcache_MASK (0x100U) -#define PKC_PKC_CTRL_clrcache_SHIFT (8U) -/*! clrcache - Clear universal pointer cache: Invalidates the cache such that all previously fetched - * parameters are withdrawn and have to be fetched again via DMA accesses. - */ -#define PKC_PKC_CTRL_clrcache(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_clrcache_SHIFT)) & PKC_PKC_CTRL_clrcache_MASK) - -#define PKC_PKC_CTRL_cache_en_MASK (0x200U) -#define PKC_PKC_CTRL_cache_en_SHIFT (9U) -/*! cache_en - Enable universal pointer cache: If CACHE_EN=1 the cache for the universal pointer - * parameters is enabled. In case a parameter value is found in the cache (from a previous fetch) no - * DMA access is triggered. As such the amount of DMA accesses for the parameter fetch vary - * between 0 and 4. To further optimize the cache utilization not used parameters, e.g. XPTR for a - * plain addition (opcode 0x0A), could be defined equal to a used one (e.g. equal YPTR or RPTR) or - * a previously fetched parameter. - */ -#define PKC_PKC_CTRL_cache_en(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_cache_en_SHIFT)) & PKC_PKC_CTRL_cache_en_MASK) - -#define PKC_PKC_CTRL_redmul_MASK (0xC00U) -#define PKC_PKC_CTRL_redmul_SHIFT (10U) -/*! redmul - Reduced multiplier mode: REDMUL defines the operand width processed by the PKC coprocessor. - * 0b00..full size mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008 - * 0b01..RFU Error Generated if selected - * 0b10..64-bit mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008 - * 0b11..RFU Error Generated if selected - */ -#define PKC_PKC_CTRL_redmul(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_redmul_SHIFT)) & PKC_PKC_CTRL_redmul_MASK) - -#define PKC_PKC_CTRL_reserved31_MASK (0xFFFFF000U) -#define PKC_PKC_CTRL_reserved31_SHIFT (12U) -/*! reserved31 - reserved - */ -#define PKC_PKC_CTRL_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_reserved31_SHIFT)) & PKC_PKC_CTRL_reserved31_MASK) -/*! @} */ - -/*! @name PKC_CFG - Configuration register */ -/*! @{ */ - -#define PKC_PKC_CFG_idleop_MASK (0x1U) -#define PKC_PKC_CFG_idleop_SHIFT (0U) -/*! idleop - Idle operation feature not available in this version (flag is don't care). - */ -#define PKC_PKC_CFG_idleop(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_idleop_SHIFT)) & PKC_PKC_CFG_idleop_MASK) - -#define PKC_PKC_CFG_rfu1_MASK (0x2U) -#define PKC_PKC_CFG_rfu1_SHIFT (1U) -/*! rfu1 - RFU - */ -#define PKC_PKC_CFG_rfu1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_rfu1_SHIFT)) & PKC_PKC_CFG_rfu1_MASK) - -#define PKC_PKC_CFG_rfu2_MASK (0x4U) -#define PKC_PKC_CFG_rfu2_SHIFT (2U) -/*! rfu2 - RFU - */ -#define PKC_PKC_CFG_rfu2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_rfu2_SHIFT)) & PKC_PKC_CFG_rfu2_MASK) - -#define PKC_PKC_CFG_clkrnd_MASK (0x8U) -#define PKC_PKC_CFG_clkrnd_SHIFT (3U) -/*! clkrnd - Clock randomization feature not available in this version (flag is don't care). - */ -#define PKC_PKC_CFG_clkrnd(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_clkrnd_SHIFT)) & PKC_PKC_CFG_clkrnd_MASK) - -#define PKC_PKC_CFG_redmulnoise_MASK (0x10U) -#define PKC_PKC_CFG_redmulnoise_SHIFT (4U) -/*! redmulnoise - Noise in reduced multiplier mode feature not available in this version (flag is don't care). - */ -#define PKC_PKC_CFG_redmulnoise(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_redmulnoise_SHIFT)) & PKC_PKC_CFG_redmulnoise_MASK) - -#define PKC_PKC_CFG_rnddly_MASK (0xE0U) -#define PKC_PKC_CFG_rnddly_SHIFT (5U) -/*! rnddly - Random delay feature not available in this version (flag is don't care). - */ -#define PKC_PKC_CFG_rnddly(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_rnddly_SHIFT)) & PKC_PKC_CFG_rnddly_MASK) - -#define PKC_PKC_CFG_sbxnoise_MASK (0x100U) -#define PKC_PKC_CFG_sbxnoise_SHIFT (8U) -/*! sbxnoise - Noise feature not available in this version (flag is don't care). - */ -#define PKC_PKC_CFG_sbxnoise(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_sbxnoise_SHIFT)) & PKC_PKC_CFG_sbxnoise_MASK) - -#define PKC_PKC_CFG_alpnoise_MASK (0x200U) -#define PKC_PKC_CFG_alpnoise_SHIFT (9U) -/*! alpnoise - Noise feature not available in this version (flag is don't care). - */ -#define PKC_PKC_CFG_alpnoise(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_alpnoise_SHIFT)) & PKC_PKC_CFG_alpnoise_MASK) - -#define PKC_PKC_CFG_fmulnoise_MASK (0x400U) -#define PKC_PKC_CFG_fmulnoise_SHIFT (10U) -/*! fmulnoise - Noise feature not available in this version (flag is don't care). - */ -#define PKC_PKC_CFG_fmulnoise(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_fmulnoise_SHIFT)) & PKC_PKC_CFG_fmulnoise_MASK) - -#define PKC_PKC_CFG_reserved31_MASK (0xFFFFF800U) -#define PKC_PKC_CFG_reserved31_SHIFT (11U) -/*! reserved31 - reserved - */ -#define PKC_PKC_CFG_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_reserved31_SHIFT)) & PKC_PKC_CFG_reserved31_MASK) -/*! @} */ - -/*! @name PKC_MODE1 - Mode register, parameter set 1 */ -/*! @{ */ - -#define PKC_PKC_MODE1_mode_MASK (0xFFU) -#define PKC_PKC_MODE1_mode_SHIFT (0U) -/*! mode - Calculation Mode / MC Start address: - */ -#define PKC_PKC_MODE1_mode(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE1_mode_SHIFT)) & PKC_PKC_MODE1_mode_MASK) - -#define PKC_PKC_MODE1_reserved31_MASK (0xFFFFFF00U) -#define PKC_PKC_MODE1_reserved31_SHIFT (8U) -/*! reserved31 - reserved - */ -#define PKC_PKC_MODE1_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE1_reserved31_SHIFT)) & PKC_PKC_MODE1_reserved31_MASK) -/*! @} */ - -/*! @name PKC_XYPTR1 - X+Y pointer register, parameter set 1 */ -/*! @{ */ - -#define PKC_PKC_XYPTR1_xptr_MASK (0xFFFFU) -#define PKC_PKC_XYPTR1_xptr_SHIFT (0U) -/*! xptr - Start address of X operand in PKCRAM with byte granularity: Least significant bits are - * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on - * available PKCRAM size. - */ -#define PKC_PKC_XYPTR1_xptr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_xptr_SHIFT)) & PKC_PKC_XYPTR1_xptr_MASK) - -#define PKC_PKC_XYPTR1_yptr_MASK (0xFFFF0000U) -#define PKC_PKC_XYPTR1_yptr_SHIFT (16U) -/*! yptr - Start address of Y operand in PKCRAM with byte granularity: Least significant bits are - * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on - * available PKCRAM size. - */ -#define PKC_PKC_XYPTR1_yptr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_yptr_SHIFT)) & PKC_PKC_XYPTR1_yptr_MASK) -/*! @} */ - -/*! @name PKC_ZRPTR1 - Z+R pointer register, parameter set 1 */ -/*! @{ */ - -#define PKC_PKC_ZRPTR1_zptr_MASK (0xFFFFU) -#define PKC_PKC_ZRPTR1_zptr_SHIFT (0U) -/*! zptr - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST: - */ -#define PKC_PKC_ZRPTR1_zptr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_zptr_SHIFT)) & PKC_PKC_ZRPTR1_zptr_MASK) - -#define PKC_PKC_ZRPTR1_rptr_MASK (0xFFFF0000U) -#define PKC_PKC_ZRPTR1_rptr_SHIFT (16U) -/*! rptr - Start address of R result in PKCRAM with byte granularity: Least significant bits are - * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on - * available PKCRAM size. - */ -#define PKC_PKC_ZRPTR1_rptr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_rptr_SHIFT)) & PKC_PKC_ZRPTR1_rptr_MASK) -/*! @} */ - -/*! @name PKC_LEN1 - Length register, parameter set 1 */ -/*! @{ */ - -#define PKC_PKC_LEN1_len_MASK (0xFFFFU) -#define PKC_PKC_LEN1_len_SHIFT (0U) -/*! len - Operand length: LEN defines the length of the operands and the result in bytes. The length - * of Y, Z and R depend furthermore on the selected calculation mode. - */ -#define PKC_PKC_LEN1_len(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_len_SHIFT)) & PKC_PKC_LEN1_len_MASK) - -#define PKC_PKC_LEN1_mclen_MASK (0xFFFF0000U) -#define PKC_PKC_LEN1_mclen_SHIFT (16U) -/*! mclen - Loop counter for microcode pattern: MCLEN defines the length of the loop counter that - * can be used in layer1 calculation mode, e.g. in MC opcode DecrTBNZ. For the hardcoded MC - * patterns Modular Multiplication (MC start address 0x00), Plain Multiplication (0x13), Plain - * Multiplication with Addition (0x1D) and Modular Reduction (0x33) MCLEN defines the length of the X - * operand in bytes. - */ -#define PKC_PKC_LEN1_mclen(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_mclen_SHIFT)) & PKC_PKC_LEN1_mclen_MASK) -/*! @} */ - -/*! @name PKC_MODE2 - Mode register, parameter set 2 */ -/*! @{ */ - -#define PKC_PKC_MODE2_mode_MASK (0xFFU) -#define PKC_PKC_MODE2_mode_SHIFT (0U) -/*! mode - Calculation Mode / MC Start address: - */ -#define PKC_PKC_MODE2_mode(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE2_mode_SHIFT)) & PKC_PKC_MODE2_mode_MASK) - -#define PKC_PKC_MODE2_reserved31_MASK (0xFFFFFF00U) -#define PKC_PKC_MODE2_reserved31_SHIFT (8U) -/*! reserved31 - reserved - */ -#define PKC_PKC_MODE2_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE2_reserved31_SHIFT)) & PKC_PKC_MODE2_reserved31_MASK) -/*! @} */ - -/*! @name PKC_XYPTR2 - X+Y pointer register, parameter set 2 */ -/*! @{ */ - -#define PKC_PKC_XYPTR2_xptr_MASK (0xFFFFU) -#define PKC_PKC_XYPTR2_xptr_SHIFT (0U) -/*! xptr - Start address of X operand in PKCRAM with byte granularity: Least significant bits are - * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on - * available PKCRAM size. - */ -#define PKC_PKC_XYPTR2_xptr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_xptr_SHIFT)) & PKC_PKC_XYPTR2_xptr_MASK) - -#define PKC_PKC_XYPTR2_yptr_MASK (0xFFFF0000U) -#define PKC_PKC_XYPTR2_yptr_SHIFT (16U) -/*! yptr - Start address of Y operand in PKCRAM with byte granularity: Least significant bits are - * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on - * available PKCRAM size. - */ -#define PKC_PKC_XYPTR2_yptr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_yptr_SHIFT)) & PKC_PKC_XYPTR2_yptr_MASK) -/*! @} */ - -/*! @name PKC_ZRPTR2 - Z+R pointer register, parameter set 2 */ -/*! @{ */ - -#define PKC_PKC_ZRPTR2_zptr_MASK (0xFFFFU) -#define PKC_PKC_ZRPTR2_zptr_SHIFT (0U) -/*! zptr - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST: - */ -#define PKC_PKC_ZRPTR2_zptr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_zptr_SHIFT)) & PKC_PKC_ZRPTR2_zptr_MASK) - -#define PKC_PKC_ZRPTR2_rptr_MASK (0xFFFF0000U) -#define PKC_PKC_ZRPTR2_rptr_SHIFT (16U) -/*! rptr - Start address of R result in PKCRAM with byte granularity: Least significant bits are - * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on - * available PKCRAM size. - */ -#define PKC_PKC_ZRPTR2_rptr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_rptr_SHIFT)) & PKC_PKC_ZRPTR2_rptr_MASK) -/*! @} */ - -/*! @name PKC_LEN2 - Length register, parameter set 2 */ -/*! @{ */ - -#define PKC_PKC_LEN2_len_MASK (0xFFFFU) -#define PKC_PKC_LEN2_len_SHIFT (0U) -/*! len - Operand length: LEN defines the length of the operands and the result in bytes. The length - * of Y, Z and R depend furthermore on the selected calculation mode. - */ -#define PKC_PKC_LEN2_len(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_len_SHIFT)) & PKC_PKC_LEN2_len_MASK) - -#define PKC_PKC_LEN2_mclen_MASK (0xFFFF0000U) -#define PKC_PKC_LEN2_mclen_SHIFT (16U) -/*! mclen - Loop counter for microcode pattern: MCLEN defines the length of the loop counter that - * can be used in layer1 calculation mode, e.g. in MC opcode DecrTBNZ. For the hardcoded MC - * patterns Modular Multiplication (MC start address 0x00) - */ -#define PKC_PKC_LEN2_mclen(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_mclen_SHIFT)) & PKC_PKC_LEN2_mclen_MASK) -/*! @} */ - -/*! @name PKC_UPTR - Universal pointer FUP program */ -/*! @{ */ - -#define PKC_PKC_UPTR_ptr_MASK (0xFFFFFFFFU) -#define PKC_PKC_UPTR_ptr_SHIFT (0U) -/*! ptr - Pointer to start address of PKC FUP program: PKC_UPTR needs to be defined before starting - * a universal pointer PKC calculation (layer2) via PKC_CTRL.GOU. The pointer address needs to be - * valid and the memory space the pointer addresses needs to be enabled for PKC access by the - * system. Otherwise a security alarm is triggered (PKC_ACCESS_ERR.AHB is set). - */ -#define PKC_PKC_UPTR_ptr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTR_ptr_SHIFT)) & PKC_PKC_UPTR_ptr_MASK) -/*! @} */ - -/*! @name PKC_UPTRT - Universal pointer FUP table */ -/*! @{ */ - -#define PKC_PKC_UPTRT_ptr_MASK (0xFFFFFFFFU) -#define PKC_PKC_UPTRT_ptr_SHIFT (0U) -/*! ptr - Pointer to start address of PKC FUP table: PKC_UPTRT needs to be defined before starting a - * universal pointer PKC calculation (layer2) via PKC_CTRL.GOU. The pointer address needs to be - * valid and the memory space the pointer addresses needs to be enabled for PKC access by the - * system. Otherwise a security alarm is triggered (PKC_ACCESS_ERR.AHB is set). - */ -#define PKC_PKC_UPTRT_ptr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTRT_ptr_SHIFT)) & PKC_PKC_UPTRT_ptr_MASK) -/*! @} */ - -/*! @name PKC_ULEN - Universal pointer length */ -/*! @{ */ - -#define PKC_PKC_ULEN_len_MASK (0xFFU) -#define PKC_PKC_ULEN_len_SHIFT (0U) -/*! len - Length of universal pointer calculation: PKC_ULEN defines how many FUP program entries - * shall be processed for one layer2 calculation started via PKC_CTRL.GOU. The FUP program entries - * include layer0 calculations, layer1 calculations and CRC entries for FUP program integrity - * protection. - */ -#define PKC_PKC_ULEN_len(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ULEN_len_SHIFT)) & PKC_PKC_ULEN_len_MASK) - -#define PKC_PKC_ULEN_reserved31_MASK (0xFFFFFF00U) -#define PKC_PKC_ULEN_reserved31_SHIFT (8U) -/*! reserved31 - reserved - */ -#define PKC_PKC_ULEN_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ULEN_reserved31_SHIFT)) & PKC_PKC_ULEN_reserved31_MASK) -/*! @} */ - -/*! @name PKC_MCDATA - MC pattern data interface */ -/*! @{ */ - -#define PKC_PKC_MCDATA_mcdata_MASK (0xFFFFFFFFU) -#define PKC_PKC_MCDATA_mcdata_SHIFT (0U) -/*! mcdata - Microcode read/write data: This IP version does not support flexible MC patterns (only - * hard coded ones). Any read or write access to PKC_MCDATA triggers a security alarm - * (PKC_ACCESS_ERR.CTRL is set). - */ -#define PKC_PKC_MCDATA_mcdata(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MCDATA_mcdata_SHIFT)) & PKC_PKC_MCDATA_mcdata_MASK) -/*! @} */ - -/*! @name PKC_VERSION - PKC version register */ -/*! @{ */ - -#define PKC_PKC_VERSION_mulsize_MASK (0x3U) -#define PKC_PKC_VERSION_mulsize_SHIFT (0U) -/*! mulsize - native multiplier size and operand granularity - * 0b01..32-bit multiplier - * 0b10..64-bit multiplier - * 0b11..128-bit multiplier - */ -#define PKC_PKC_VERSION_mulsize(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_mulsize_SHIFT)) & PKC_PKC_VERSION_mulsize_MASK) - -#define PKC_PKC_VERSION_mcavail_MASK (0x4U) -#define PKC_PKC_VERSION_mcavail_SHIFT (2U) -/*! mcavail - MC feature (layer1 calculation) is available - */ -#define PKC_PKC_VERSION_mcavail(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_mcavail_SHIFT)) & PKC_PKC_VERSION_mcavail_MASK) - -#define PKC_PKC_VERSION_upavail_MASK (0x8U) -#define PKC_PKC_VERSION_upavail_SHIFT (3U) -/*! upavail - UP feature (layer2 calculation) is available - */ -#define PKC_PKC_VERSION_upavail(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_upavail_SHIFT)) & PKC_PKC_VERSION_upavail_MASK) - -#define PKC_PKC_VERSION_upcacheavail_MASK (0x10U) -#define PKC_PKC_VERSION_upcacheavail_SHIFT (4U) -/*! upcacheavail - UP cache is available - */ -#define PKC_PKC_VERSION_upcacheavail(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_upcacheavail_SHIFT)) & PKC_PKC_VERSION_upcacheavail_MASK) - -#define PKC_PKC_VERSION_gf2avail_MASK (0x20U) -#define PKC_PKC_VERSION_gf2avail_SHIFT (5U) -/*! gf2avail - GF2 calculation modes are available - */ -#define PKC_PKC_VERSION_gf2avail(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_gf2avail_SHIFT)) & PKC_PKC_VERSION_gf2avail_MASK) - -#define PKC_PKC_VERSION_paramnum_MASK (0xC0U) -#define PKC_PKC_VERSION_paramnum_SHIFT (6U) -/*! paramnum - Number of parameter sets for real calculation - */ -#define PKC_PKC_VERSION_paramnum(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_paramnum_SHIFT)) & PKC_PKC_VERSION_paramnum_MASK) - -#define PKC_PKC_VERSION_sbx0avail_MASK (0x100U) -#define PKC_PKC_VERSION_sbx0avail_SHIFT (8U) -/*! sbx0avail - SBX0 operation is available - */ -#define PKC_PKC_VERSION_sbx0avail(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_sbx0avail_SHIFT)) & PKC_PKC_VERSION_sbx0avail_MASK) - -#define PKC_PKC_VERSION_sbx1avail_MASK (0x200U) -#define PKC_PKC_VERSION_sbx1avail_SHIFT (9U) -/*! sbx1avail - SBX1 operation is available - */ -#define PKC_PKC_VERSION_sbx1avail(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_sbx1avail_SHIFT)) & PKC_PKC_VERSION_sbx1avail_MASK) - -#define PKC_PKC_VERSION_sbx2avail_MASK (0x400U) -#define PKC_PKC_VERSION_sbx2avail_SHIFT (10U) -/*! sbx2avail - SBX2 operation is available - */ -#define PKC_PKC_VERSION_sbx2avail(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_sbx2avail_SHIFT)) & PKC_PKC_VERSION_sbx2avail_MASK) - -#define PKC_PKC_VERSION_sbx3avail_MASK (0x800U) -#define PKC_PKC_VERSION_sbx3avail_SHIFT (11U) -/*! sbx3avail - SBX3 operation is available - */ -#define PKC_PKC_VERSION_sbx3avail(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_sbx3avail_SHIFT)) & PKC_PKC_VERSION_sbx3avail_MASK) - -#define PKC_PKC_VERSION_mcreconf_size_MASK (0xFF000U) -#define PKC_PKC_VERSION_mcreconf_size_SHIFT (12U) -/*! mcreconf_size - Size of reconfigurable MC table in bytes - */ -#define PKC_PKC_VERSION_mcreconf_size(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_mcreconf_size_SHIFT)) & PKC_PKC_VERSION_mcreconf_size_MASK) - -#define PKC_PKC_VERSION_reserved31_MASK (0xFFF00000U) -#define PKC_PKC_VERSION_reserved31_SHIFT (20U) -/*! reserved31 - reserved - */ -#define PKC_PKC_VERSION_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_reserved31_SHIFT)) & PKC_PKC_VERSION_reserved31_MASK) -/*! @} */ - -/*! @name PKC_SOFT_RST - Software reset */ -/*! @{ */ - -#define PKC_PKC_SOFT_RST_soft_rst_MASK (0x1U) -#define PKC_PKC_SOFT_RST_soft_rst_SHIFT (0U) -/*! soft_rst - Write 1 to reset module (0 has no effect). All running and pending PKC calculation - * are stopped. All PKC SFRs are reset except PKC_ACCESS_ERR. - */ -#define PKC_PKC_SOFT_RST_soft_rst(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_SOFT_RST_soft_rst_SHIFT)) & PKC_PKC_SOFT_RST_soft_rst_MASK) - -#define PKC_PKC_SOFT_RST_reserved31_MASK (0xFFFFFFFEU) -#define PKC_PKC_SOFT_RST_reserved31_SHIFT (1U) -/*! reserved31 - reserved - */ -#define PKC_PKC_SOFT_RST_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_SOFT_RST_reserved31_SHIFT)) & PKC_PKC_SOFT_RST_reserved31_MASK) -/*! @} */ - -/*! @name PKC_ACCESS_ERR - Access Error */ -/*! @{ */ - -#define PKC_PKC_ACCESS_ERR_apb_notav_MASK (0x1U) -#define PKC_PKC_ACCESS_ERR_apb_notav_SHIFT (0U) -/*! apb_notav - APB Error: address not available - */ -#define PKC_PKC_ACCESS_ERR_apb_notav(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_apb_notav_SHIFT)) & PKC_PKC_ACCESS_ERR_apb_notav_MASK) - -#define PKC_PKC_ACCESS_ERR_apb_wrgmd_MASK (0x2U) -#define PKC_PKC_ACCESS_ERR_apb_wrgmd_SHIFT (1U) -/*! apb_wrgmd - APB Error: Wrong access mode - */ -#define PKC_PKC_ACCESS_ERR_apb_wrgmd(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_apb_wrgmd_SHIFT)) & PKC_PKC_ACCESS_ERR_apb_wrgmd_MASK) - -#define PKC_PKC_ACCESS_ERR_reserved3_MASK (0xCU) -#define PKC_PKC_ACCESS_ERR_reserved3_SHIFT (2U) -/*! reserved3 - reserved for future erors on APB I/F - */ -#define PKC_PKC_ACCESS_ERR_reserved3(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_reserved3_SHIFT)) & PKC_PKC_ACCESS_ERR_reserved3_MASK) - -#define PKC_PKC_ACCESS_ERR_apb_master_MASK (0xF0U) -#define PKC_PKC_ACCESS_ERR_apb_master_SHIFT (4U) -/*! apb_master - APB Master that triggered first APB error (APB_WRGMD or APB_NOTAV) - */ -#define PKC_PKC_ACCESS_ERR_apb_master(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_apb_master_SHIFT)) & PKC_PKC_ACCESS_ERR_apb_master_MASK) - -#define PKC_PKC_ACCESS_ERR_reserved9_MASK (0x300U) -#define PKC_PKC_ACCESS_ERR_reserved9_SHIFT (8U) -/*! reserved9 - reserved for future erors on AHB I/F Layer2 Only - */ -#define PKC_PKC_ACCESS_ERR_reserved9(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_reserved9_SHIFT)) & PKC_PKC_ACCESS_ERR_reserved9_MASK) - -#define PKC_PKC_ACCESS_ERR_ahb_MASK (0x400U) -#define PKC_PKC_ACCESS_ERR_ahb_SHIFT (10U) -/*! ahb - AHB Error: invalid AHB access Layer2 Only - */ -#define PKC_PKC_ACCESS_ERR_ahb(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_ahb_SHIFT)) & PKC_PKC_ACCESS_ERR_ahb_MASK) - -#define PKC_PKC_ACCESS_ERR_reserved15_MASK (0xF800U) -#define PKC_PKC_ACCESS_ERR_reserved15_SHIFT (11U) -/*! reserved15 - reserved for future erors on AHB I/F Layer2 Only - */ -#define PKC_PKC_ACCESS_ERR_reserved15(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_reserved15_SHIFT)) & PKC_PKC_ACCESS_ERR_reserved15_MASK) - -#define PKC_PKC_ACCESS_ERR_pkcc_MASK (0x10000U) -#define PKC_PKC_ACCESS_ERR_pkcc_SHIFT (16U) -/*! pkcc - Error in PKC coprocessor kernel - */ -#define PKC_PKC_ACCESS_ERR_pkcc(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_pkcc_SHIFT)) & PKC_PKC_ACCESS_ERR_pkcc_MASK) - -#define PKC_PKC_ACCESS_ERR_fdet_MASK (0x20000U) -#define PKC_PKC_ACCESS_ERR_fdet_SHIFT (17U) -/*! fdet - Error due to error detection circuitry - */ -#define PKC_PKC_ACCESS_ERR_fdet(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_fdet_SHIFT)) & PKC_PKC_ACCESS_ERR_fdet_MASK) - -#define PKC_PKC_ACCESS_ERR_ctrl_MASK (0x40000U) -#define PKC_PKC_ACCESS_ERR_ctrl_SHIFT (18U) -/*! ctrl - Error in PKC software control - */ -#define PKC_PKC_ACCESS_ERR_ctrl(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_ctrl_SHIFT)) & PKC_PKC_ACCESS_ERR_ctrl_MASK) - -#define PKC_PKC_ACCESS_ERR_ucrc_MASK (0x80000U) -#define PKC_PKC_ACCESS_ERR_ucrc_SHIFT (19U) -/*! ucrc - Error in layer2 CRC check - */ -#define PKC_PKC_ACCESS_ERR_ucrc(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_ucrc_SHIFT)) & PKC_PKC_ACCESS_ERR_ucrc_MASK) - -#define PKC_PKC_ACCESS_ERR_reserved20_MASK (0x100000U) -#define PKC_PKC_ACCESS_ERR_reserved20_SHIFT (20U) -/*! reserved20 - reserved - */ -#define PKC_PKC_ACCESS_ERR_reserved20(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_reserved20_SHIFT)) & PKC_PKC_ACCESS_ERR_reserved20_MASK) - -#define PKC_PKC_ACCESS_ERR_reserved31_MASK (0xFFE00000U) -#define PKC_PKC_ACCESS_ERR_reserved31_SHIFT (21U) -/*! reserved31 - reserved for more block errors - */ -#define PKC_PKC_ACCESS_ERR_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_reserved31_SHIFT)) & PKC_PKC_ACCESS_ERR_reserved31_MASK) -/*! @} */ - -/*! @name PKC_ACCESS_ERR_CLR - Clear Access Error */ -/*! @{ */ - -#define PKC_PKC_ACCESS_ERR_CLR_err_clr_MASK (0x1U) -#define PKC_PKC_ACCESS_ERR_CLR_err_clr_SHIFT (0U) -/*! err_clr - Write 1 to reset PKC_ACCESS_ERR SFR. - */ -#define PKC_PKC_ACCESS_ERR_CLR_err_clr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CLR_err_clr_SHIFT)) & PKC_PKC_ACCESS_ERR_CLR_err_clr_MASK) - -#define PKC_PKC_ACCESS_ERR_CLR_reserved31_MASK (0xFFFFFFFEU) -#define PKC_PKC_ACCESS_ERR_CLR_reserved31_SHIFT (1U) -/*! reserved31 - reserved - */ -#define PKC_PKC_ACCESS_ERR_CLR_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CLR_reserved31_SHIFT)) & PKC_PKC_ACCESS_ERR_CLR_reserved31_MASK) -/*! @} */ - -/*! @name PKC_INT_CLR_ENABLE - Interrupt enable clear */ -/*! @{ */ - -#define PKC_PKC_INT_CLR_ENABLE_en_pdone_MASK (0x1U) -#define PKC_PKC_INT_CLR_ENABLE_en_pdone_SHIFT (0U) -/*! en_pdone - Write to clear PDONE interrupt enable flag (PKC_INT_ENABLE.EN_PDONE=0). - */ -#define PKC_PKC_INT_CLR_ENABLE_en_pdone(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_en_pdone_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_en_pdone_MASK) - -#define PKC_PKC_INT_CLR_ENABLE_reserved1_MASK (0x2U) -#define PKC_PKC_INT_CLR_ENABLE_reserved1_SHIFT (1U) -/*! reserved1 - reserved - */ -#define PKC_PKC_INT_CLR_ENABLE_reserved1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_reserved1_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_reserved1_MASK) - -#define PKC_PKC_INT_CLR_ENABLE_reserved31_MASK (0xFFFFFFFCU) -#define PKC_PKC_INT_CLR_ENABLE_reserved31_SHIFT (2U) -/*! reserved31 - reserved - */ -#define PKC_PKC_INT_CLR_ENABLE_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_reserved31_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_reserved31_MASK) -/*! @} */ - -/*! @name PKC_INT_SET_ENABLE - Interrupt enable set */ -/*! @{ */ - -#define PKC_PKC_INT_SET_ENABLE_en_pdone_MASK (0x1U) -#define PKC_PKC_INT_SET_ENABLE_en_pdone_SHIFT (0U) -/*! en_pdone - Write to set PDONE interrupt enable flag (PKC_INT_ENABLE.EN_PDONE=1). - */ -#define PKC_PKC_INT_SET_ENABLE_en_pdone(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_en_pdone_SHIFT)) & PKC_PKC_INT_SET_ENABLE_en_pdone_MASK) - -#define PKC_PKC_INT_SET_ENABLE_reserved1_MASK (0x2U) -#define PKC_PKC_INT_SET_ENABLE_reserved1_SHIFT (1U) -/*! reserved1 - reserved - */ -#define PKC_PKC_INT_SET_ENABLE_reserved1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_reserved1_SHIFT)) & PKC_PKC_INT_SET_ENABLE_reserved1_MASK) - -#define PKC_PKC_INT_SET_ENABLE_reserved31_MASK (0xFFFFFFFCU) -#define PKC_PKC_INT_SET_ENABLE_reserved31_SHIFT (2U) -/*! reserved31 - reserved - */ -#define PKC_PKC_INT_SET_ENABLE_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_reserved31_SHIFT)) & PKC_PKC_INT_SET_ENABLE_reserved31_MASK) -/*! @} */ - -/*! @name PKC_INT_STATUS - Interrupt status */ -/*! @{ */ - -#define PKC_PKC_INT_STATUS_int_pdone_MASK (0x1U) -#define PKC_PKC_INT_STATUS_int_pdone_SHIFT (0U) -/*! int_pdone - End-of-computation status flag: INT_PDONE is set after EACH single PKC layer0 or - * layer1 calculation. In case of a universal pointer calculation (layer2) INT_PDONE is set at the - * end of the pipe calculation when PKC_ULEN has been decremented to zero and the final PKC - * calculation has completed. - */ -#define PKC_PKC_INT_STATUS_int_pdone(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_int_pdone_SHIFT)) & PKC_PKC_INT_STATUS_int_pdone_MASK) - -#define PKC_PKC_INT_STATUS_reserved1_MASK (0x2U) -#define PKC_PKC_INT_STATUS_reserved1_SHIFT (1U) -/*! reserved1 - reserved - */ -#define PKC_PKC_INT_STATUS_reserved1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_reserved1_SHIFT)) & PKC_PKC_INT_STATUS_reserved1_MASK) - -#define PKC_PKC_INT_STATUS_reserved31_MASK (0xFFFFFFFCU) -#define PKC_PKC_INT_STATUS_reserved31_SHIFT (2U) -/*! reserved31 - reserved - */ -#define PKC_PKC_INT_STATUS_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_reserved31_SHIFT)) & PKC_PKC_INT_STATUS_reserved31_MASK) -/*! @} */ - -/*! @name PKC_INT_ENABLE - Interrupt enable */ -/*! @{ */ - -#define PKC_PKC_INT_ENABLE_en_pdone_MASK (0x1U) -#define PKC_PKC_INT_ENABLE_en_pdone_SHIFT (0U) -/*! en_pdone - PDONE interrupt enable flag: If EN_PDONE=1 an interrupt is triggered every time - * PKC_INT_STATUS.INT_PDONE is set. Otherwise the interrupt generation is suppressed. - */ -#define PKC_PKC_INT_ENABLE_en_pdone(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_en_pdone_SHIFT)) & PKC_PKC_INT_ENABLE_en_pdone_MASK) - -#define PKC_PKC_INT_ENABLE_reserved1_MASK (0x2U) -#define PKC_PKC_INT_ENABLE_reserved1_SHIFT (1U) -/*! reserved1 - reserved - */ -#define PKC_PKC_INT_ENABLE_reserved1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_reserved1_SHIFT)) & PKC_PKC_INT_ENABLE_reserved1_MASK) - -#define PKC_PKC_INT_ENABLE_reserved31_MASK (0xFFFFFFFCU) -#define PKC_PKC_INT_ENABLE_reserved31_SHIFT (2U) -/*! reserved31 - reserved - */ -#define PKC_PKC_INT_ENABLE_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_reserved31_SHIFT)) & PKC_PKC_INT_ENABLE_reserved31_MASK) -/*! @} */ - -/*! @name PKC_INT_CLR_STATUS - Interrupt status clear */ -/*! @{ */ - -#define PKC_PKC_INT_CLR_STATUS_int_pdone_MASK (0x1U) -#define PKC_PKC_INT_CLR_STATUS_int_pdone_SHIFT (0U) -/*! int_pdone - Write to clear End-of-computation status flag (PKC_INT_STATUS.INT_PDONE=0). - */ -#define PKC_PKC_INT_CLR_STATUS_int_pdone(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_int_pdone_SHIFT)) & PKC_PKC_INT_CLR_STATUS_int_pdone_MASK) - -#define PKC_PKC_INT_CLR_STATUS_reserved1_MASK (0x2U) -#define PKC_PKC_INT_CLR_STATUS_reserved1_SHIFT (1U) -/*! reserved1 - reserved - */ -#define PKC_PKC_INT_CLR_STATUS_reserved1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_reserved1_SHIFT)) & PKC_PKC_INT_CLR_STATUS_reserved1_MASK) - -#define PKC_PKC_INT_CLR_STATUS_reserved31_MASK (0xFFFFFFFCU) -#define PKC_PKC_INT_CLR_STATUS_reserved31_SHIFT (2U) -/*! reserved31 - reserved - */ -#define PKC_PKC_INT_CLR_STATUS_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_reserved31_SHIFT)) & PKC_PKC_INT_CLR_STATUS_reserved31_MASK) -/*! @} */ - -/*! @name PKC_INT_SET_STATUS - Interrupt status set */ -/*! @{ */ - -#define PKC_PKC_INT_SET_STATUS_int_pdone_MASK (0x1U) -#define PKC_PKC_INT_SET_STATUS_int_pdone_SHIFT (0U) -/*! int_pdone - Write to set End-of-computation status flag (PKC_INT_STATUS.INT_PDONE=1) to trigger - * a PKC interrupt via software, e.g. for debug purposes. - */ -#define PKC_PKC_INT_SET_STATUS_int_pdone(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_int_pdone_SHIFT)) & PKC_PKC_INT_SET_STATUS_int_pdone_MASK) - -#define PKC_PKC_INT_SET_STATUS_reserved1_MASK (0x2U) -#define PKC_PKC_INT_SET_STATUS_reserved1_SHIFT (1U) -/*! reserved1 - reserved - */ -#define PKC_PKC_INT_SET_STATUS_reserved1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_reserved1_SHIFT)) & PKC_PKC_INT_SET_STATUS_reserved1_MASK) - -#define PKC_PKC_INT_SET_STATUS_reserved31_MASK (0xFFFFFFFCU) -#define PKC_PKC_INT_SET_STATUS_reserved31_SHIFT (2U) -/*! reserved31 - reserved - */ -#define PKC_PKC_INT_SET_STATUS_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_reserved31_SHIFT)) & PKC_PKC_INT_SET_STATUS_reserved31_MASK) -/*! @} */ - -/*! @name PKC_MODULE_ID - Module ID */ -/*! @{ */ - -#define PKC_PKC_MODULE_ID_size_MASK (0xFFU) -#define PKC_PKC_MODULE_ID_size_SHIFT (0U) -/*! size - Address space of the IP - */ -#define PKC_PKC_MODULE_ID_size(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_size_SHIFT)) & PKC_PKC_MODULE_ID_size_MASK) - -#define PKC_PKC_MODULE_ID_minor_rev_MASK (0xF00U) -#define PKC_PKC_MODULE_ID_minor_rev_SHIFT (8U) -/*! minor_rev - Minor revision - */ -#define PKC_PKC_MODULE_ID_minor_rev(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_minor_rev_SHIFT)) & PKC_PKC_MODULE_ID_minor_rev_MASK) - -#define PKC_PKC_MODULE_ID_major_rev_MASK (0xF000U) -#define PKC_PKC_MODULE_ID_major_rev_SHIFT (12U) -/*! major_rev - Major revision - */ -#define PKC_PKC_MODULE_ID_major_rev(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_major_rev_SHIFT)) & PKC_PKC_MODULE_ID_major_rev_MASK) - -#define PKC_PKC_MODULE_ID_id_MASK (0xFFFF0000U) -#define PKC_PKC_MODULE_ID_id_SHIFT (16U) -/*! id - Module ID - */ -#define PKC_PKC_MODULE_ID_id(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_id_SHIFT)) & PKC_PKC_MODULE_ID_id_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PKC_Register_Masks */ - - -/* PKC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PKC base address */ - #define PKC_BASE (0x5002F000u) - /** Peripheral PKC base address */ - #define PKC_BASE_NS (0x4002F000u) - /** Peripheral PKC base pointer */ - #define PKC ((PKC_Type *)PKC_BASE) - /** Peripheral PKC base pointer */ - #define PKC_NS ((PKC_Type *)PKC_BASE_NS) - /** Array initializer of PKC peripheral base addresses */ - #define PKC_BASE_ADDRS { PKC_BASE } - /** Array initializer of PKC peripheral base pointers */ - #define PKC_BASE_PTRS { PKC } - /** Array initializer of PKC peripheral base addresses */ - #define PKC_BASE_ADDRS_NS { PKC_BASE_NS } - /** Array initializer of PKC peripheral base pointers */ - #define PKC_BASE_PTRS_NS { PKC_NS } -#else - /** Peripheral PKC base address */ - #define PKC_BASE (0x4002F000u) - /** Peripheral PKC base pointer */ - #define PKC ((PKC_Type *)PKC_BASE) - /** Array initializer of PKC peripheral base addresses */ - #define PKC_BASE_ADDRS { PKC_BASE } - /** Array initializer of PKC peripheral base pointers */ - #define PKC_BASE_PTRS { PKC } -#endif - -/*! - * @} - */ /* end of group PKC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer - * @{ - */ - -/** PMC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Power Management Control [Reset by: PoR, Pin Reset, Software Reset and BoDs reset], offset: 0x0 */ - __I uint32_t STATUS; /**< Power Management Controller FSM (Finite State Machines) status, offset: 0x4 */ - __IO uint32_t RESETCTRL; /**< Reset Control, offset: 0x8 */ - __IO uint32_t RESETCAUSE; /**< Reset Cause, offset: 0xC */ - __IO uint32_t DCDC0; /**< DCDC (first) control, offset: 0x10 */ - __IO uint32_t DCDC1; /**< DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x14 */ - uint8_t RESERVED_0[4]; - __IO uint32_t LDOPMU; /**< Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x1C */ - __IO uint32_t LDOMEM; /**< Memories LDO control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x20 */ - __IO uint32_t LDOCORE0; /**< LDO CORE (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x24 */ - __IO uint32_t LDOFLASHNV; /**< Flash High Voltage LDO control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x28 */ - __IO uint32_t LDOEFUSEPROG; /**< eFUSE (One Time Programmable Memory) Programming LDO control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x2C */ - __IO uint32_t BODVDDMAIN; /**< VDDMAIN Brown Out Dectector control, offset: 0x30 */ - uint8_t RESERVED_1[4]; - __IO uint32_t BODCORE; /**< Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x38 */ - uint8_t RESERVED_2[4]; - __IO uint32_t REFFASTWKUP; /**< Analog References fast wake-up Control register [Reset by: PoR], offset: 0x40 */ - uint8_t RESERVED_3[8]; - __IO uint32_t XTAL32K; /**< 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x4C */ - __IO uint32_t COMP; /**< Analog Comparator control, offset: 0x50 */ - uint8_t RESERVED_4[12]; - __O uint32_t CMD; /**< DCDC and LDOCORE power state (enable/disable) control., offset: 0x60 */ - __IO uint32_t WAKEUPIOCTRL; /**< Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset], offset: 0x64 */ - __IO uint32_t WAKEIOCAUSE; /**< Wake-up I/O source, offset: 0x68 */ - __IO uint32_t LIFECYCLESTATE; /**< Life Cycle State as configured in the OTP, offset: 0x6C */ - __I uint32_t STATUSPWR; /**< Power status from various analog modules (DCDC, LDO, etc), offset: 0x70 */ - __IO uint32_t STATUSCLK; /**< Clock status, offset: 0x74 */ - uint8_t RESERVED_5[8]; - __IO uint32_t AOREG0; /**< Always-on 0, offset: 0x80 */ - __IO uint32_t AOREG1; /**< Always-on 1, offset: 0x84 */ - uint8_t RESERVED_6[8]; - __IO uint32_t MISCCTRL; /**< Miscellaneous Control Register for PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x90 */ - uint8_t RESERVED_7[4]; - __IO uint32_t RTCOSC32K; /**< 32 KHz clocks source control, offset: 0x98 */ - __IO uint32_t OSEVENTTIMER; /**< OS Event Timer control, offset: 0x9C */ - __IO uint32_t PDSLEEPCFG1; /**< Controls the power to various modules during Low Power modes - DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xA0 */ - __IO uint32_t TIMEOUTEVENTS; /**< Record time-out errors that might occur at different stages during IC power up, offset: 0xA4 */ - uint8_t RESERVED_8[8]; - __IO uint32_t PDSLEEPCFG0; /**< Controls the power to various modules during Low Power modes - DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xB0 */ - __IO uint32_t SRAMRETCTRL; /**< Controls all SRAM instances power down modes during Low Power modes [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xB4 */ - __IO uint32_t PDRUNCFG0; /**< Power configuration 0, offset: 0xB8 */ - __IO uint32_t PDRUNCFG1; /**< Power configuration 1, offset: 0xBC */ - __O uint32_t PDRUNCFGSET0; /**< Power configuration set 0, offset: 0xC0 */ - __O uint32_t PDRUNCFGSET1; /**< Power configuration set 1, offset: 0xC4 */ - __O uint32_t PDRUNCFGCLR0; /**< Power configuration clear 0, offset: 0xC8 */ - __O uint32_t PDRUNCFGCLR1; /**< Power configuration clear 1, offset: 0xCC */ - uint8_t RESERVED_9[4]; - __IO uint32_t SRAMCTRL; /**< All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xD4 */ - __IO uint32_t SRAMCTRL0; /**< RAM_X0, and RAM_00 to RAM_30 power modes controls [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] When [LS, LSDEL, DSB, DSBDEL] is: 0011 : Normal Mode 1111 : Light sleep mode 0100 : Deep-sleep mode 1100 : Shut down Mode, offset: 0xD8 */ - __IO uint32_t SRAMCTRL1; /**< RAM_40 to RAM_43 power modes controls [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] When [LS, LSDEL, DSB, DSBDEL] is: 0011 : Normal Mode 1111 : Light sleep mode 0100 : Deep-sleep mode 1100 : Shut down Mode, offset: 0xDC */ -} PMC_Type; - -/* ---------------------------------------------------------------------------- - -- PMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Register_Masks PMC Register Masks - * @{ - */ - -/*! @name CTRL - Power Management Control [Reset by: PoR, Pin Reset, Software Reset and BoDs reset] */ -/*! @{ */ - -#define PMC_CTRL_LPMODE_MASK (0x3U) -#define PMC_CTRL_LPMODE_SHIFT (0U) -/*! LPMODE - Power Mode Control. - * 0b00..ACTIVE power mode. - * 0b01..DEEP-SLEEP low power mode. - * 0b10..POWER-DOWN low power mode. - * 0b11..DEEP-POWER-DOWN low power mode. - */ -#define PMC_CTRL_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_LPMODE_SHIFT)) & PMC_CTRL_LPMODE_MASK) - -#define PMC_CTRL_SELCLOCK_MASK (0x4U) -#define PMC_CTRL_SELCLOCK_SHIFT (2U) -/*! SELCLOCK - Select the Power Management Controller (PMC) functional clock : - * 0b0..1 MHz Free Running Oscillator. - * 0b1..12 MHz Free Running Oscillator. - */ -#define PMC_CTRL_SELCLOCK(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_SELCLOCK_SHIFT)) & PMC_CTRL_SELCLOCK_MASK) - -#define PMC_CTRL_SELMEMSUPPLY_MASK (0x8U) -#define PMC_CTRL_SELMEMSUPPLY_SHIFT (3U) -/*! SELMEMSUPPLY - Select Memories supply source in DEEP-SLEEP low power mode: Note: in POWER-DOWN - * and DEEP-POWER-DOWN, memories are always supplied by LDO_MEM. - * 0b0..Memories are supplied by LDO_MEM in 'DEEP-SLEEP' low power mode. - * 0b1..Memories are supplied by DCDC/LDO_CORE in 'DEEP-SLEEP' low power mode. - */ -#define PMC_CTRL_SELMEMSUPPLY(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_SELMEMSUPPLY_SHIFT)) & PMC_CTRL_SELMEMSUPPLY_MASK) - -#define PMC_CTRL_SELCORESUPPLYWK_MASK (0x10U) -#define PMC_CTRL_SELCORESUPPLYWK_SHIFT (4U) -/*! SELCORESUPPLYWK - Select Core Logic supply source when waking up from DEEP-SLEEP and POWER-DOWN low power modes : - * 0b0..Core Logic is supplied by DCDC Converter. - * 0b1..Core Logic is supplied by LDO CORE (configured in High Power mode). - */ -#define PMC_CTRL_SELCORESUPPLYWK(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_SELCORESUPPLYWK_SHIFT)) & PMC_CTRL_SELCORESUPPLYWK_MASK) - -#define PMC_CTRL_DEEPSLEEPCORESUPPLY_MASK (0x60U) -#define PMC_CTRL_DEEPSLEEPCORESUPPLY_SHIFT (5U) -/*! DEEPSLEEPCORESUPPLY - Select Core Logic supply source during DEEP-SLEEP low power mode : - * 0b00..LDO CORE in Low Power Mode. - * 0b01..LDO CORE in High Power Mode. - * 0b10..DCDC Converter. - */ -#define PMC_CTRL_DEEPSLEEPCORESUPPLY(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_DEEPSLEEPCORESUPPLY_SHIFT)) & PMC_CTRL_DEEPSLEEPCORESUPPLY_MASK) -/*! @} */ - -/*! @name STATUS - Power Management Controller FSM (Finite State Machines) status */ -/*! @{ */ - -#define PMC_STATUS_BOOTMODE_MASK (0xC0000U) -#define PMC_STATUS_BOOTMODE_SHIFT (18U) -/*! BOOTMODE - Latest IC Boot cause:. - * 0b00..Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset). - * 0b01..Latest IC boot was from DEEP-SLEEP low power mode. - * 0b10..Latest IC boot was from POWER-DOWN low power mode. - * 0b11..Latest IC boot was from DEEP-POWER-DOWN low power mode. - */ -#define PMC_STATUS_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_BOOTMODE_SHIFT)) & PMC_STATUS_BOOTMODE_MASK) - -#define PMC_STATUS_FSMDCDCENABLE_MASK (0x100000U) -#define PMC_STATUS_FSMDCDCENABLE_SHIFT (20U) -/*! FSMDCDCENABLE - Indicates the power status of the DCDC (enabled or disabled) as driven by the Hardware Finite State Machines (FSM). - * 0b0..DCDC is currently disabled by the Hardware Finite State Machine (FSM). - * 0b1..DCDC is currently enabled by the Hardware Finite State Machine (FSM). - */ -#define PMC_STATUS_FSMDCDCENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMDCDCENABLE_SHIFT)) & PMC_STATUS_FSMDCDCENABLE_MASK) - -#define PMC_STATUS_FSMLDOCOREHPENABLE_MASK (0x200000U) -#define PMC_STATUS_FSMLDOCOREHPENABLE_SHIFT (21U) -/*! FSMLDOCOREHPENABLE - Indicates the power status of the LDO CORE High Power Mode (enabled or - * disabled) as driven by the Hardware Finite State Machines (FSM). - * 0b0..LDO CORE High Power Mode is currently disabled by the Hardware Finite State Machine (FSM). - * 0b1..LDO CORE High Power Mode is currently enabled by the Hardware Finite State Machine (FSM). - */ -#define PMC_STATUS_FSMLDOCOREHPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMLDOCOREHPENABLE_SHIFT)) & PMC_STATUS_FSMLDOCOREHPENABLE_MASK) - -#define PMC_STATUS_FSMLDOCORELPENABLE_MASK (0x400000U) -#define PMC_STATUS_FSMLDOCORELPENABLE_SHIFT (22U) -/*! FSMLDOCORELPENABLE - Indicates the power status of the LDO CORE Low Power Mode (enabled or - * disabled) as driven by the Hardware Finite State Machines (FSM). - * 0b0..LDO CORE Low Power Mode is currently disabled by the Hardware Finite State Machine (FSM). - * 0b1..LDO CORE Low Power Mode is currently enabled by the Hardware Finite State Machine (FSM). - */ -#define PMC_STATUS_FSMLDOCORELPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMLDOCORELPENABLE_SHIFT)) & PMC_STATUS_FSMLDOCORELPENABLE_MASK) - -#define PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK (0x800000U) -#define PMC_STATUS_FSMLDOCOREEXPTMRENABLE_SHIFT (23U) -/*! FSMLDOCOREEXPTMRENABLE - Indicates the status of the LDO CORE Exponential Timer (enabled or - * disabled) as driven by the Hardware Finite State Machines (FSM). - */ -#define PMC_STATUS_FSMLDOCOREEXPTMRENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMLDOCOREEXPTMRENABLE_SHIFT)) & PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK) -/*! @} */ - -/*! @name RESETCTRL - Reset Control */ -/*! @{ */ - -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U) -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U) -/*! DPDWAKEUPRESETENABLE - Wake-up from DEEP-POWER-DOWN reset event (either from wake up I/O or RTC or OS Event Timer). - * 0b0..Reset event from DEEP-POWER-DOWN mode is disabled. - * 0b1..Reset event from DEEP-POWER-DOWN mode is enabled. - */ -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK) - -#define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U) -#define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U) -/*! SWRRESETENABLE - Software reset enable. - * 0b0..Software reset is disabled. - * 0b1..Software reset is enabled. - */ -#define PMC_RESETCTRL_SWRRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK) - -#define PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_MASK (0x30U) -#define PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_SHIFT (4U) -/*! BODVDDMAINRESETENA_SECURE - BOD_VDDMAIN reset enabled. - * 0b10..BOD_VDDMAIN reset is disabled. - * 0b01..And any other value than b10: BOD_VDDMAIN reset is enabled. - */ -#define PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_SHIFT)) & PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_MASK) - -#define PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK (0xC0U) -#define PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT (6U) -/*! BODCORERESETENA_SECURE - BOD_CORE reset enabled. - * 0b10..BODCORE reset is disabled. - * 0b01..And any other value than b10: BOD_CORE reset is enabled. - */ -#define PMC_RESETCTRL_BODCORERESETENA_SECURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT)) & PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK) - -#define PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_DP_MASK (0x30000000U) -#define PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_DP_SHIFT (28U) -/*! BODVDDMAINRESETENA_SECURE_DP - BOD_VDDMAIN reset enabled. - * 0b10..BOD_VDDMAIN reset is disabled. - * 0b01..And any other value than b10: BOD_VDDMAIN reset is enabled. - */ -#define PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_DP(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_DP_SHIFT)) & PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_DP_MASK) - -#define PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK (0xC0000000U) -#define PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT (30U) -/*! BODCORERESETENA_SECURE_DP - BOD_CORE reset enable. - * 0b10..BOD_CORE reset is disabled. - * 0b01..And any other value than b10: BOD_CORE reset is enabled. - */ -#define PMC_RESETCTRL_BODCORERESETENA_SECURE_DP(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT)) & PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK) -/*! @} */ - -/*! @name RESETCAUSE - Reset Cause */ -/*! @{ */ - -#define PMC_RESETCAUSE_POR_MASK (0x1U) -#define PMC_RESETCAUSE_POR_SHIFT (0U) -/*! POR - 1 : The last chip reset was caused by a Power On Reset. Write '1' to clear this bit. - */ -#define PMC_RESETCAUSE_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_POR_SHIFT)) & PMC_RESETCAUSE_POR_MASK) - -#define PMC_RESETCAUSE_PADRESET_MASK (0x2U) -#define PMC_RESETCAUSE_PADRESET_SHIFT (1U) -/*! PADRESET - 1 : The last chip reset was caused by a Pin Reset. Write '1' to clear this bit. - */ -#define PMC_RESETCAUSE_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_PADRESET_SHIFT)) & PMC_RESETCAUSE_PADRESET_MASK) - -#define PMC_RESETCAUSE_BODRESET_MASK (0x4U) -#define PMC_RESETCAUSE_BODRESET_SHIFT (2U) -/*! BODRESET - 1 : The last chip reset was caused by a Brown Out Detector (BoD), either BOD_VDDMAIN - * or BOD_CORE. Write '1' to clear this bit. - */ -#define PMC_RESETCAUSE_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_BODRESET_SHIFT)) & PMC_RESETCAUSE_BODRESET_MASK) - -#define PMC_RESETCAUSE_SYSTEMRESET_MASK (0x8U) -#define PMC_RESETCAUSE_SYSTEMRESET_SHIFT (3U) -/*! SYSTEMRESET - 1 : The last chip reset was caused by a System Reset requested by the ARM CPU. Write '1' to clear this bit. - */ -#define PMC_RESETCAUSE_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_SYSTEMRESET_SHIFT)) & PMC_RESETCAUSE_SYSTEMRESET_MASK) - -#define PMC_RESETCAUSE_WDTRESET_MASK (0x10U) -#define PMC_RESETCAUSE_WDTRESET_SHIFT (4U) -/*! WDTRESET - 1 : The last chip reset was caused by the Watchdog Timer. Write '1' to clear this bit. - */ -#define PMC_RESETCAUSE_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_WDTRESET_SHIFT)) & PMC_RESETCAUSE_WDTRESET_MASK) - -#define PMC_RESETCAUSE_SWRRESET_MASK (0x20U) -#define PMC_RESETCAUSE_SWRRESET_SHIFT (5U) -/*! SWRRESET - 1 : The last chip reset was caused by a Software. Write '1' to clear this bit. - */ -#define PMC_RESETCAUSE_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_SWRRESET_SHIFT)) & PMC_RESETCAUSE_SWRRESET_MASK) - -#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO_MASK (0x40U) -#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO_SHIFT (6U) -/*! DPDRESET_WAKEUPIO - 1 : A Wake-up I/O reset event occured during DEEP-POWER-DOWN mode. Write '1' to clear this bit. - */ -#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_WAKEUPIO_SHIFT)) & PMC_RESETCAUSE_DPDRESET_WAKEUPIO_MASK) - -#define PMC_RESETCAUSE_DPDRESET_RTC_MASK (0x80U) -#define PMC_RESETCAUSE_DPDRESET_RTC_SHIFT (7U) -/*! DPDRESET_RTC - 1 : A RTC (either RTC Alarm or RTC wake up) reset event occured during - * DEEP-POWER-DOWN mode. Write '1' to clear this bit. - */ -#define PMC_RESETCAUSE_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_RTC_SHIFT)) & PMC_RESETCAUSE_DPDRESET_RTC_MASK) - -#define PMC_RESETCAUSE_DPDRESET_OSTIMER_MASK (0x100U) -#define PMC_RESETCAUSE_DPDRESET_OSTIMER_SHIFT (8U) -/*! DPDRESET_OSTIMER - 1 : A OS Event Timer reset event occured during DEEP-POWER-DOWN mode. Write '1' to clear this bit. - */ -#define PMC_RESETCAUSE_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_OSTIMER_SHIFT)) & PMC_RESETCAUSE_DPDRESET_OSTIMER_MASK) - -#define PMC_RESETCAUSE_CDOGRESET_MASK (0x200U) -#define PMC_RESETCAUSE_CDOGRESET_SHIFT (9U) -/*! CDOGRESET - 1 : The last chip reset was caused by the code Watchdog. Write '1' to clear this bit. - */ -#define PMC_RESETCAUSE_CDOGRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_CDOGRESET_SHIFT)) & PMC_RESETCAUSE_CDOGRESET_MASK) - -#define PMC_RESETCAUSE_DPD_EVENTS_ORDER_MASK (0x1C00U) -#define PMC_RESETCAUSE_DPD_EVENTS_ORDER_SHIFT (10U) -/*! DPD_EVENTS_ORDER - In DEEP-POWER-DOWN mode, indicates which reset event occured first between - * DPDRESET_WAKEUPIO, DPDRESET_RTC and DPDRESET_OSTIMER. Write 'b001' to clear these bit field. - * 0b000..No event - * 0b001..WAKEUPIO - * 0b010..RTC - * 0b011..Both WAKEUPIO and RTC events occured at the same time (less than 1 nano-second from each other) - * 0b100..OSTIMER - * 0b101..Both WAKEUPIO and OSTIMER events occured at the same time (less than 1 nano-second from each other) - * 0b110..Both RTC and OSTIMER events occured at the same time (less than 1 nano-second from each other) - * 0b111..WAKEUPIO, RTC and OSTIMER events occured at the same time (less than 1 nano-second from each other) - */ -#define PMC_RESETCAUSE_DPD_EVENTS_ORDER(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPD_EVENTS_ORDER_SHIFT)) & PMC_RESETCAUSE_DPD_EVENTS_ORDER_MASK) -/*! @} */ - -/*! @name DCDC0 - DCDC (first) control */ -/*! @{ */ - -#define PMC_DCDC0_RC_MASK (0x3FU) -#define PMC_DCDC0_RC_SHIFT (0U) -/*! RC - Constant On-Time calibration. - */ -#define PMC_DCDC0_RC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_RC_SHIFT)) & PMC_DCDC0_RC_MASK) - -#define PMC_DCDC0_ICOMP_MASK (0xC0U) -#define PMC_DCDC0_ICOMP_SHIFT (6U) -/*! ICOMP - Select the type of ZCD comparator. - */ -#define PMC_DCDC0_ICOMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICOMP_SHIFT)) & PMC_DCDC0_ICOMP_MASK) - -#define PMC_DCDC0_ISEL_MASK (0x300U) -#define PMC_DCDC0_ISEL_SHIFT (8U) -/*! ISEL - Alter Internal biasing currents. - */ -#define PMC_DCDC0_ISEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ISEL_SHIFT)) & PMC_DCDC0_ISEL_MASK) - -#define PMC_DCDC0_ICENABLE_MASK (0x400U) -#define PMC_DCDC0_ICENABLE_SHIFT (10U) -/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD. - */ -#define PMC_DCDC0_ICENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICENABLE_SHIFT)) & PMC_DCDC0_ICENABLE_MASK) - -#define PMC_DCDC0_TMOS_MASK (0xF800U) -#define PMC_DCDC0_TMOS_SHIFT (11U) -/*! TMOS - One-shot generator reference current trimming signal. - */ -#define PMC_DCDC0_TMOS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_TMOS_SHIFT)) & PMC_DCDC0_TMOS_MASK) - -#define PMC_DCDC0_DISABLEISENSE_MASK (0x10000U) -#define PMC_DCDC0_DISABLEISENSE_SHIFT (16U) -/*! DISABLEISENSE - Disable Current sensing. - */ -#define PMC_DCDC0_DISABLEISENSE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_DISABLEISENSE_SHIFT)) & PMC_DCDC0_DISABLEISENSE_MASK) - -#define PMC_DCDC0_VOUT_MASK (0x1E0000U) -#define PMC_DCDC0_VOUT_SHIFT (17U) -/*! VOUT - Set output regulation voltage. - * 0b0000..0.95 V. - * 0b0001..0.975 V. - * 0b0010..1 V. - * 0b0011..1.025 V. - * 0b0100..1.05 V. - * 0b0101..1.075 V. - * 0b0110..1.1 V. - * 0b0111..1.125 V. - * 0b1000..1.15 V. - * 0b1001..1.175 V. - * 0b1010..1.2 V. - */ -#define PMC_DCDC0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_SHIFT)) & PMC_DCDC0_VOUT_MASK) - -#define PMC_DCDC0_SLICINGENABLE_MASK (0x200000U) -#define PMC_DCDC0_SLICINGENABLE_SHIFT (21U) -/*! SLICINGENABLE - Enable staggered switching of power switches. - */ -#define PMC_DCDC0_SLICINGENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_SLICINGENABLE_SHIFT)) & PMC_DCDC0_SLICINGENABLE_MASK) - -#define PMC_DCDC0_INDUCTORCLAMPENABLE_MASK (0x400000U) -#define PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT (22U) -/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. - */ -#define PMC_DCDC0_INDUCTORCLAMPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT)) & PMC_DCDC0_INDUCTORCLAMPENABLE_MASK) - -#define PMC_DCDC0_VOUT_PWD_MASK (0x7800000U) -#define PMC_DCDC0_VOUT_PWD_SHIFT (23U) -/*! VOUT_PWD - Set output regulation voltage during Deep Sleep. - */ -#define PMC_DCDC0_VOUT_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_PWD_SHIFT)) & PMC_DCDC0_VOUT_PWD_MASK) -/*! @} */ - -/*! @name DCDC1 - DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_DCDC1_RTRIMOFFET_MASK (0xFU) -#define PMC_DCDC1_RTRIMOFFET_SHIFT (0U) -/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator. - */ -#define PMC_DCDC1_RTRIMOFFET(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RTRIMOFFET_SHIFT)) & PMC_DCDC1_RTRIMOFFET_MASK) - -#define PMC_DCDC1_RSENSETRIM_MASK (0xF0U) -#define PMC_DCDC1_RSENSETRIM_SHIFT (4U) -/*! RSENSETRIM - Adjust Max inductor peak current limiting. - */ -#define PMC_DCDC1_RSENSETRIM(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RSENSETRIM_SHIFT)) & PMC_DCDC1_RSENSETRIM_MASK) - -#define PMC_DCDC1_DTESTENABLE_MASK (0x100U) -#define PMC_DCDC1_DTESTENABLE_SHIFT (8U) -/*! DTESTENABLE - Enable Digital test signals. - */ -#define PMC_DCDC1_DTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTENABLE_SHIFT)) & PMC_DCDC1_DTESTENABLE_MASK) - -#define PMC_DCDC1_SETCURVE_MASK (0x600U) -#define PMC_DCDC1_SETCURVE_SHIFT (9U) -/*! SETCURVE - Bandgap calibration parameter. - */ -#define PMC_DCDC1_SETCURVE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETCURVE_SHIFT)) & PMC_DCDC1_SETCURVE_MASK) - -#define PMC_DCDC1_SETDC_MASK (0x7800U) -#define PMC_DCDC1_SETDC_SHIFT (11U) -/*! SETDC - Bandgap calibration parameter. - */ -#define PMC_DCDC1_SETDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETDC_SHIFT)) & PMC_DCDC1_SETDC_MASK) - -#define PMC_DCDC1_DTESTSEL_MASK (0x38000U) -#define PMC_DCDC1_DTESTSEL_SHIFT (15U) -/*! DTESTSEL - Select the output signal for test. - */ -#define PMC_DCDC1_DTESTSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTSEL_SHIFT)) & PMC_DCDC1_DTESTSEL_MASK) - -#define PMC_DCDC1_ISCALEENABLE_MASK (0x40000U) -#define PMC_DCDC1_ISCALEENABLE_SHIFT (18U) -/*! ISCALEENABLE - Modify COT behavior. - */ -#define PMC_DCDC1_ISCALEENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_ISCALEENABLE_SHIFT)) & PMC_DCDC1_ISCALEENABLE_MASK) - -#define PMC_DCDC1_FORCEBYPASS_MASK (0x80000U) -#define PMC_DCDC1_FORCEBYPASS_SHIFT (19U) -/*! FORCEBYPASS - Force bypass mode. - */ -#define PMC_DCDC1_FORCEBYPASS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEBYPASS_SHIFT)) & PMC_DCDC1_FORCEBYPASS_MASK) - -#define PMC_DCDC1_TRIMAUTOCOT_MASK (0xF00000U) -#define PMC_DCDC1_TRIMAUTOCOT_SHIFT (20U) -/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. - */ -#define PMC_DCDC1_TRIMAUTOCOT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TRIMAUTOCOT_SHIFT)) & PMC_DCDC1_TRIMAUTOCOT_MASK) - -#define PMC_DCDC1_FORCEFULLCYCLE_MASK (0x1000000U) -#define PMC_DCDC1_FORCEFULLCYCLE_SHIFT (24U) -/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. - */ -#define PMC_DCDC1_FORCEFULLCYCLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEFULLCYCLE_SHIFT)) & PMC_DCDC1_FORCEFULLCYCLE_MASK) - -#define PMC_DCDC1_LCENABLE_MASK (0x2000000U) -#define PMC_DCDC1_LCENABLE_SHIFT (25U) -/*! LCENABLE - Change the range of the peak detector of current inside the inductor. - */ -#define PMC_DCDC1_LCENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_LCENABLE_SHIFT)) & PMC_DCDC1_LCENABLE_MASK) - -#define PMC_DCDC1_TOFF_MASK (0x7C000000U) -#define PMC_DCDC1_TOFF_SHIFT (26U) -/*! TOFF - Constant Off-Time calibration input. - */ -#define PMC_DCDC1_TOFF(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFF_SHIFT)) & PMC_DCDC1_TOFF_MASK) - -#define PMC_DCDC1_TOFFENABLE_MASK (0x80000000U) -#define PMC_DCDC1_TOFFENABLE_SHIFT (31U) -/*! TOFFENABLE - Enable Constant Off-Time feature. - */ -#define PMC_DCDC1_TOFFENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFFENABLE_SHIFT)) & PMC_DCDC1_TOFFENABLE_MASK) -/*! @} */ - -/*! @name LDOPMU - Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_LDOPMU_VADJ_MASK (0x1FU) -#define PMC_LDOPMU_VADJ_SHIFT (0U) -/*! VADJ - Sets the Always-On domain LDO output level. - * 0b00000..1.22 V. - * 0b00001..0.7 V. - * 0b00010..0.725 V. - * 0b00011..0.75 V. - * 0b00100..0.775 V. - * 0b00101..0.8 V. - * 0b00110..0.825 V. - * 0b00111..0.85 V. - * 0b01000..0.875 V. - * 0b01001..0.9 V. - * 0b01010..0.96 V. - * 0b01011..0.97 V. - * 0b01100..0.98 V. - * 0b01101..0.99 V. - * 0b01110..1 V. - * 0b01111..1.01 V. - * 0b10000..1.02 V. - * 0b10001..1.03 V. - * 0b10010..1.04 V. - * 0b10011..1.05 V. - * 0b10100..1.06 V. - * 0b10101..1.07 V. - * 0b10110..1.08 V. - * 0b10111..1.09 V. - * 0b11000..1.1 V. - * 0b11001..1.11 V. - * 0b11010..1.12 V. - * 0b11011..1.13 V. - * 0b11100..1.14 V. - * 0b11101..1.15 V. - * 0b11110..1.16 V. - * 0b11111..1.22 V. - */ -#define PMC_LDOPMU_VADJ(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_SHIFT)) & PMC_LDOPMU_VADJ_MASK) - -#define PMC_LDOPMU_VADJ_PWD_MASK (0x3E0U) -#define PMC_LDOPMU_VADJ_PWD_SHIFT (5U) -/*! VADJ_PWD - Sets the Always-On domain LDO output level in all power down modes. - */ -#define PMC_LDOPMU_VADJ_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_PWD_SHIFT)) & PMC_LDOPMU_VADJ_PWD_MASK) - -#define PMC_LDOPMU_VADJ_BOOST_MASK (0x7C00U) -#define PMC_LDOPMU_VADJ_BOOST_SHIFT (10U) -/*! VADJ_BOOST - Sets the Always-On domain LDO Boost output level. - */ -#define PMC_LDOPMU_VADJ_BOOST(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_MASK) - -#define PMC_LDOPMU_VADJ_BOOST_PWD_MASK (0xF8000U) -#define PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT (15U) -/*! VADJ_BOOST_PWD - Sets the Always-On domain LDO Boost output level in all power down modes. - */ -#define PMC_LDOPMU_VADJ_BOOST_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_PWD_MASK) -/*! @} */ - -/*! @name LDOMEM - Memories LDO control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_LDOMEM_VADJ_MASK (0x1FU) -#define PMC_LDOMEM_VADJ_SHIFT (0U) -/*! VADJ - Sets the Memories LDO output level. - * 0b00000..1.22 V. - * 0b00001..0.7 V. - * 0b00010..0.725 V. - * 0b00011..0.75 V. - * 0b00100..0.775 V. - * 0b00101..0.8 V. - * 0b00110..0.825 V. - * 0b00111..0.85 V. - * 0b01000..0.875 V. - * 0b01001..0.9 V. - * 0b01010..0.96 V. - * 0b01011..0.97 V. - * 0b01100..0.98 V. - * 0b01101..0.99 V. - * 0b01110..1 V. - * 0b01111..1.01 V. - * 0b10000..1.02 V. - * 0b10001..1.03 V. - * 0b10010..1.04 V. - * 0b10011..1.05 V. - * 0b10100..1.06 V. - * 0b10101..1.07 V. - * 0b10110..1.08 V. - * 0b10111..1.09 V. - * 0b11000..1.1 V. - * 0b11001..1.11 V. - * 0b11010..1.12 V. - * 0b11011..1.13 V. - * 0b11100..1.14 V. - * 0b11101..1.15 V. - * 0b11110..1.16 V. - * 0b11111..1.22 V. - */ -#define PMC_LDOMEM_VADJ(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOMEM_VADJ_SHIFT)) & PMC_LDOMEM_VADJ_MASK) - -#define PMC_LDOMEM_VADJ_PWD_MASK (0x3E0U) -#define PMC_LDOMEM_VADJ_PWD_SHIFT (5U) -/*! VADJ_PWD - Sets the Memories LDO output level in all power down modes. - */ -#define PMC_LDOMEM_VADJ_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOMEM_VADJ_PWD_SHIFT)) & PMC_LDOMEM_VADJ_PWD_MASK) - -#define PMC_LDOMEM_VADJ_BOOST_MASK (0x7C00U) -#define PMC_LDOMEM_VADJ_BOOST_SHIFT (10U) -/*! VADJ_BOOST - Sets the Memories LDO Boost output level. - */ -#define PMC_LDOMEM_VADJ_BOOST(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOMEM_VADJ_BOOST_SHIFT)) & PMC_LDOMEM_VADJ_BOOST_MASK) - -#define PMC_LDOMEM_VADJ_BOOST_PWD_MASK (0xF8000U) -#define PMC_LDOMEM_VADJ_BOOST_PWD_SHIFT (15U) -/*! VADJ_BOOST_PWD - Sets the Memories LDO Boost output level in all power down modes. - */ -#define PMC_LDOMEM_VADJ_BOOST_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOMEM_VADJ_BOOST_PWD_SHIFT)) & PMC_LDOMEM_VADJ_BOOST_PWD_MASK) -/*! @} */ - -/*! @name LDOCORE0 - LDO CORE (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_LDOCORE0_LPREGREFSEL_MASK (0x60000U) -#define PMC_LDOCORE0_LPREGREFSEL_SHIFT (17U) -/*! LPREGREFSEL - Low Power regulation point select. - * 0b00..900 mV. - * 0b01..850 mV. - * 0b10..800 mV. - * 0b11..750 mV. - */ -#define PMC_LDOCORE0_LPREGREFSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOCORE0_LPREGREFSEL_SHIFT)) & PMC_LDOCORE0_LPREGREFSEL_MASK) - -#define PMC_LDOCORE0_REGREFTRIM_MASK (0x7F000000U) -#define PMC_LDOCORE0_REGREFTRIM_SHIFT (24U) -/*! REGREFTRIM - High Power regulation point select. - */ -#define PMC_LDOCORE0_REGREFTRIM(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOCORE0_REGREFTRIM_SHIFT)) & PMC_LDOCORE0_REGREFTRIM_MASK) -/*! @} */ - -/*! @name LDOFLASHNV - Flash High Voltage LDO control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_LDOFLASHNV_VADJ_MASK (0x7U) -#define PMC_LDOFLASHNV_VADJ_SHIFT (0U) -/*! VADJ - Sets the LDO output level. - * 0b000..1.650 V. - * 0b001..1.700 V. - * 0b010..1.750 V. - * 0b011..1.800 V. - * 0b100..1.850 V. - * 0b101..1.900 V. - * 0b110..1.950 V. - * 0b111..2.0 V. - */ -#define PMC_LDOFLASHNV_VADJ(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOFLASHNV_VADJ_SHIFT)) & PMC_LDOFLASHNV_VADJ_MASK) -/*! @} */ - -/*! @name LDOEFUSEPROG - eFUSE (One Time Programmable Memory) Programming LDO control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_LDOEFUSEPROG_VADJ_MASK (0x7U) -#define PMC_LDOEFUSEPROG_VADJ_SHIFT (0U) -/*! VADJ - Sets the LDO output level. - * 0b000..1.650 V. - * 0b001..1.700 V. - * 0b010..1.750 V. - * 0b011..1.800 V. - * 0b100..1.850 V. - * 0b101..1.900 V. - * 0b110..1.950 V. - * 0b111..2.0 V. - */ -#define PMC_LDOEFUSEPROG_VADJ(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOEFUSEPROG_VADJ_SHIFT)) & PMC_LDOEFUSEPROG_VADJ_MASK) -/*! @} */ - -/*! @name BODVDDMAIN - VDDMAIN Brown Out Dectector control */ -/*! @{ */ - -#define PMC_BODVDDMAIN_TRIGLVL_MASK (0x1FU) -#define PMC_BODVDDMAIN_TRIGLVL_SHIFT (0U) -/*! TRIGLVL - BoD trigger level. - * 0b00000..1.00 V. - * 0b00001..1.10 V. - * 0b00010..1.20 V. - * 0b00011..1.30 V. - * 0b00100..1.40 V. - * 0b00101..1.50 V. - * 0b00110..1.60 V. - * 0b00111..1.65 V. - * 0b01000..1.70 V. - * 0b01001..1.75 V. - * 0b01010..1.80 V. - * 0b01011..1.90 V. - * 0b01100..2.00 V. - * 0b01101..2.10 V. - * 0b01110..2.20 V. - * 0b01111..2.30 V. - * 0b10000..2.40 V. - * 0b10001..2.50 V. - * 0b10010..2.60 V. - * 0b10011..2.70 V. - * 0b10100..2.80 V. - * 0b10101..2.90 V. - * 0b10110..3.00 V. - * 0b10111..3.10 V. - * 0b11000..3.20 V. - * 0b11001..3.30 V. - * 0b11010..3.30 V. - * 0b11011..3.30 V. - * 0b11100..3.30 V. - * 0b11101..3.30 V. - * 0b11110..3.30 V. - * 0b11111..3.30 V. - */ -#define PMC_BODVDDMAIN_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVDDMAIN_TRIGLVL_SHIFT)) & PMC_BODVDDMAIN_TRIGLVL_MASK) - -#define PMC_BODVDDMAIN_HYST_MASK (0x60U) -#define PMC_BODVDDMAIN_HYST_SHIFT (5U) -/*! HYST - BoD Hysteresis control. - * 0b00..25 mV. - * 0b01..50 mV. - * 0b10..75 mV. - * 0b11..100 mV. - */ -#define PMC_BODVDDMAIN_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVDDMAIN_HYST_SHIFT)) & PMC_BODVDDMAIN_HYST_MASK) -/*! @} */ - -/*! @name BODCORE - Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_BODCORE_TRIGLVL_MASK (0x7U) -#define PMC_BODCORE_TRIGLVL_SHIFT (0U) -/*! TRIGLVL - BoD trigger level. - * 0b000..0.60 V. - * 0b001..0.65 V. - * 0b010..0.70 V. - * 0b011..0.75 V. - * 0b100..0.80 V. - * 0b101..0.85 V. - * 0b110..0.90 V. - * 0b111..0.95 V. - */ -#define PMC_BODCORE_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODCORE_TRIGLVL_SHIFT)) & PMC_BODCORE_TRIGLVL_MASK) - -#define PMC_BODCORE_HYST_MASK (0x30U) -#define PMC_BODCORE_HYST_SHIFT (4U) -/*! HYST - BOD_CORE Hysteresis control. - * 0b00..25 mV. - * 0b01..50 mV. - * 0b10..75 mV. - * 0b11..100 mV. - */ -#define PMC_BODCORE_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODCORE_HYST_SHIFT)) & PMC_BODCORE_HYST_MASK) -/*! @} */ - -/*! @name REFFASTWKUP - Analog References fast wake-up Control register [Reset by: PoR] */ -/*! @{ */ - -#define PMC_REFFASTWKUP_LPWKUP_MASK (0x1U) -#define PMC_REFFASTWKUP_LPWKUP_SHIFT (0U) -/*! LPWKUP - Analog References fast wake-up in case of wake-up from a low power mode (DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN): - * 0b0..Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode. - * 0b1..Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode. - */ -#define PMC_REFFASTWKUP_LPWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_LPWKUP_SHIFT)) & PMC_REFFASTWKUP_LPWKUP_MASK) - -#define PMC_REFFASTWKUP_HWWKUP_MASK (0x2U) -#define PMC_REFFASTWKUP_HWWKUP_SHIFT (1U) -/*! HWWKUP - Analog References fast wake-up in case of Hardware Pin reset: - * 0b0..Analog References fast wake-up feature is disabled in case of Hardware Pin reset. - * 0b1..Analog References fast wake-up feature is enabled in case of Hardware Pin reset. - */ -#define PMC_REFFASTWKUP_HWWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_HWWKUP_SHIFT)) & PMC_REFFASTWKUP_HWWKUP_MASK) -/*! @} */ - -/*! @name XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_XTAL32K_TEST_MASK (0x8U) -#define PMC_XTAL32K_TEST_SHIFT (3U) -/*! TEST - Oscillator Bypass Test Mode control. - * 0b0..Oscillation mode. - * 0b1..Bypass test mode is enabled. - */ -#define PMC_XTAL32K_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK) - -#define PMC_XTAL32K_CAPBANKIN_MASK (0x7F00U) -#define PMC_XTAL32K_CAPBANKIN_SHIFT (8U) -/*! CAPBANKIN - Capa bank setting input. - */ -#define PMC_XTAL32K_CAPBANKIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKIN_SHIFT)) & PMC_XTAL32K_CAPBANKIN_MASK) - -#define PMC_XTAL32K_CAPBANKOUT_MASK (0x3F8000U) -#define PMC_XTAL32K_CAPBANKOUT_SHIFT (15U) -/*! CAPBANKOUT - Capa bank setting output. - */ -#define PMC_XTAL32K_CAPBANKOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKOUT_SHIFT)) & PMC_XTAL32K_CAPBANKOUT_MASK) -/*! @} */ - -/*! @name COMP - Analog Comparator control */ -/*! @{ */ - -#define PMC_COMP_HYST_MASK (0x2U) -#define PMC_COMP_HYST_SHIFT (1U) -/*! HYST - Hysteris when hyst = '1'. - * 0b0..Hysteresis is disabled. - * 0b1..Hysteresis is enabled. - */ -#define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK) - -#define PMC_COMP_VREFINPUT_MASK (0x4U) -#define PMC_COMP_VREFINPUT_SHIFT (2U) -/*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). - * 0b0..Select internal VREF. - * 0b1..Select VDDA. - */ -#define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK) - -#define PMC_COMP_LOWPOWER_MASK (0x8U) -#define PMC_COMP_LOWPOWER_SHIFT (3U) -/*! LOWPOWER - Low power mode. - * 0b0..High speed mode. - * 0b1..Low power mode (Low speed). - */ -#define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK) - -#define PMC_COMP_PMUX_MASK (0x70U) -#define PMC_COMP_PMUX_SHIFT (4U) -/*! PMUX - Control word for P multiplexer:. - * 0b000..VREF (See field VREFINPUT). - * 0b001..Pin P0_0. - * 0b010..Pin P0_9. - * 0b011..Pin P0_18. - * 0b100..Pin P1_14. - * 0b101..Pin P2_23. - */ -#define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK) - -#define PMC_COMP_NMUX_MASK (0x380U) -#define PMC_COMP_NMUX_SHIFT (7U) -/*! NMUX - Control word for N multiplexer:. - * 0b000..VREF (See field VREFINPUT). - * 0b001..Pin P0_0. - * 0b010..Pin P0_9. - * 0b011..Pin P0_18. - * 0b100..Pin P1_14. - * 0b101..Pin P2_23. - */ -#define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK) - -#define PMC_COMP_VREF_MASK (0x7C00U) -#define PMC_COMP_VREF_SHIFT (10U) -/*! VREF - Control reference voltage step, per steps of (VREFINPUT/31). - */ -#define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK) - -#define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U) -#define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U) -/*! FILTERCGF_SAMPLEMODE - Control the filtering of the Analog Comparator output. - * 0b00..Bypass mode. - * 0b01..Filter 1 clock period. - * 0b10..Filter 2 clock period. - * 0b11..Filter 3 clock period. - */ -#define PMC_COMP_FILTERCGF_SAMPLEMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK) - -#define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U) -#define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U) -/*! FILTERCGF_CLKDIV - Filter Clock divider. - * 0b000..Filter clock period duration equals 1 Analog Comparator clock period. - * 0b001..Filter clock period duration equals 2 Analog Comparator clock period. - * 0b010..Filter clock period duration equals 4 Analog Comparator clock period. - * 0b011..Filter clock period duration equals 8 Analog Comparator clock period. - * 0b100..Filter clock period duration equals 16 Analog Comparator clock period. - * 0b101..Filter clock period duration equals 32 Analog Comparator clock period. - * 0b110..Filter clock period duration equals 64 Analog Comparator clock period. - * 0b111..Filter clock period duration equals 128 Analog Comparator clock period. - */ -#define PMC_COMP_FILTERCGF_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK) -/*! @} */ - -/*! @name CMD - DCDC and LDOCORE power state (enable/disable) control. */ -/*! @{ */ - -#define PMC_CMD_DCDCENABLE_MASK (0x1U) -#define PMC_CMD_DCDCENABLE_SHIFT (0U) -/*! DCDCENABLE - Enable DCDC (self clearing bit). - * 0b0..No effect. - * 0b1..Enable DCDC. Automatically reset to '0' by the Hardware. - */ -#define PMC_CMD_DCDCENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CMD_DCDCENABLE_SHIFT)) & PMC_CMD_DCDCENABLE_MASK) - -#define PMC_CMD_DCDCDISABLE_MASK (0x2U) -#define PMC_CMD_DCDCDISABLE_SHIFT (1U) -/*! DCDCDISABLE - Disable DCDC (self clearing bit). - * 0b0..No effect. - * 0b1..Disbale DCDC. Automatically reset to '0' by the Hardware. - */ -#define PMC_CMD_DCDCDISABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CMD_DCDCDISABLE_SHIFT)) & PMC_CMD_DCDCDISABLE_MASK) - -#define PMC_CMD_LDOCOREHIGHPWRENABLE_MASK (0x4U) -#define PMC_CMD_LDOCOREHIGHPWRENABLE_SHIFT (2U) -/*! LDOCOREHIGHPWRENABLE - Enable LDO CORE High Power Mode (self clearing bit). - * 0b0..No effect. - * 0b1..Enable LDO CORE High Power Mode. Automatically reset to '0' by the Hardware. - */ -#define PMC_CMD_LDOCOREHIGHPWRENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CMD_LDOCOREHIGHPWRENABLE_SHIFT)) & PMC_CMD_LDOCOREHIGHPWRENABLE_MASK) - -#define PMC_CMD_LDOCOREHIGHPWRDISABLE_MASK (0x8U) -#define PMC_CMD_LDOCOREHIGHPWRDISABLE_SHIFT (3U) -/*! LDOCOREHIGHPWRDISABLE - Disable LDO CORE High Power Mode (self clearing bit). - * 0b0..No effect. - * 0b1..Disable LDO CORE High Power Mode. Automatically reset to '0' by the Hardware. - */ -#define PMC_CMD_LDOCOREHIGHPWRDISABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CMD_LDOCOREHIGHPWRDISABLE_SHIFT)) & PMC_CMD_LDOCOREHIGHPWRDISABLE_MASK) - -#define PMC_CMD_LDOCORELOWPWRENABLE_MASK (0x10U) -#define PMC_CMD_LDOCORELOWPWRENABLE_SHIFT (4U) -/*! LDOCORELOWPWRENABLE - Enable LDO CORE Low Power Mode (self clearing bit). - * 0b0..No effect. - * 0b1..Enable LDO CORE Low Power Mode. Automatically reset to '0' by the Hardware. - */ -#define PMC_CMD_LDOCORELOWPWRENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CMD_LDOCORELOWPWRENABLE_SHIFT)) & PMC_CMD_LDOCORELOWPWRENABLE_MASK) - -#define PMC_CMD_LDOCORELOWPWRDISABLE_MASK (0x20U) -#define PMC_CMD_LDOCORELOWPWRDISABLE_SHIFT (5U) -/*! LDOCORELOWPWRDISABLE - Disable LDO CORE Low Power Mode (self clearing bit). - * 0b0..No effect. - * 0b1..Disable LDO CORE Low Power Mode. Automatically reset to '0' by the Hardware. - */ -#define PMC_CMD_LDOCORELOWPWRDISABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CMD_LDOCORELOWPWRDISABLE_SHIFT)) & PMC_CMD_LDOCORELOWPWRDISABLE_MASK) -/*! @} */ - -/*! @name WAKEUPIOCTRL - Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] */ -/*! @{ */ - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK (0x1U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT (0U) -/*! RISINGEDGEWAKEUP0 - Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disabled. - * 0b1..Rising edge detection is enabled. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK (0x2U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT (1U) -/*! FALLINGEDGEWAKEUP0 - Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disabled. - * 0b1..Falling edge detection is enabled. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK) - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK (0x4U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT (2U) -/*! RISINGEDGEWAKEUP1 - Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disabled. - * 0b1..Rising edge detection is enabled. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK (0x8U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT (3U) -/*! FALLINGEDGEWAKEUP1 - Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disabled. - * 0b1..Falling edge detection is enabled. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK) - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK (0x10U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT (4U) -/*! RISINGEDGEWAKEUP2 - Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disabled. - * 0b1..Rising edge detection is enabled. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK (0x20U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT (5U) -/*! FALLINGEDGEWAKEUP2 - Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disabled. - * 0b1..Falling edge detection is enabled. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK) - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK (0x40U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT (6U) -/*! RISINGEDGEWAKEUP3 - Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes: - * 0b0..Rising edge detection is disabled. - * 0b1..Rising edge detection is enabled. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK (0x80U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT (7U) -/*! FALLINGEDGEWAKEUP3 - Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes: - * 0b0..Falling edge detection is disabled. - * 0b1..Falling edge detection is enabled. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK) - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP4_MASK (0x100U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP4_SHIFT (8U) -/*! RISINGEDGEWAKEUP4 - Enable / disable detection of rising edge events on Wake Up 4 pin in Deep Power Down modes: - * 0b0..Rising edge detection is disabled. - * 0b1..Rising edge detection is enabled. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP4(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP4_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP4_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP4_MASK (0x200U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP4_SHIFT (9U) -/*! FALLINGEDGEWAKEUP4 - Enable / disable detection of falling edge events on Wake Up 4 pin in Deep Power Down modes: - * 0b0..Falling edge detection is disabled. - * 0b1..Falling edge detection is enabled. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP4(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP4_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP4_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_MASK (0xC00U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_SHIFT (10U) -/*! MODEWAKEUPIOPAD0 - Selects function mode (on-chip pull-up/pull-down resistor control). - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_MASK (0x3000U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_SHIFT (12U) -/*! MODEWAKEUPIOPAD1 - Selects function mode (on-chip pull-up/pull-down resistor control). - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_MASK (0xC000U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_SHIFT (14U) -/*! MODEWAKEUPIOPAD2 - Selects function mode (on-chip pull-up/pull-down resistor control). - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_MASK (0x30000U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_SHIFT (16U) -/*! MODEWAKEUPIOPAD3 - Selects function mode (on-chip pull-up/pull-down resistor control). - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD4_MASK (0xC0000U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD4_SHIFT (18U) -/*! MODEWAKEUPIOPAD4 - Selects function mode (on-chip pull-up/pull-down resistor control). - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD4(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD4_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD4_MASK) - -#define PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK (0x100000U) -#define PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_SHIFT (20U) -/*! WAKEUPIO_ENABLE_CTRL - Enable WAKEUP IO PAD control from MODEWAKEUPIOPAD (bits 10 to 19). - * 0b0..WAKEUP IO PAD mode control comes from IOCON. - * 0b1..WAKEUP IO PAD mode control comes from MODEWAKEUPIOPAD (bits 10 to 19). - */ -#define PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_SHIFT)) & PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK) - -#define PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_MASK (0x200000U) -#define PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_SHIFT (21U) -/*! WAKEUPIO_RSTN - WAKEUP IO event detector reset control. - * 0b0..Bloc is reset. - * 0b1..Bloc is not reset. - */ -#define PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_SHIFT)) & PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_MASK) -/*! @} */ - -/*! @name WAKEIOCAUSE - Wake-up I/O source */ -/*! @{ */ - -#define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U) -#define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U) -/*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0. - */ -#define PMC_WAKEIOCAUSE_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK) - -#define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U) -#define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U) -/*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1. - */ -#define PMC_WAKEIOCAUSE_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK) - -#define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U) -#define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U) -/*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2. - */ -#define PMC_WAKEIOCAUSE_WAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK) - -#define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U) -#define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U) -/*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 3. - */ -#define PMC_WAKEIOCAUSE_WAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK) - -#define PMC_WAKEIOCAUSE_WAKEUP4_MASK (0x10U) -#define PMC_WAKEIOCAUSE_WAKEUP4_SHIFT (4U) -/*! WAKEUP4 - Allows to identify Wake up I/O 4 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 4. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 4. - */ -#define PMC_WAKEIOCAUSE_WAKEUP4(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP4_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP4_MASK) - -#define PMC_WAKEIOCAUSE_WAKEUPIO_EVENTS_ORDER_MASK (0x3E0U) -#define PMC_WAKEIOCAUSE_WAKEUPIO_EVENTS_ORDER_SHIFT (5U) -/*! WAKEUPIO_EVENTS_ORDER - In DEEP-POWER-DOWN mode, indicates which wake up I/O event occured first when several wake up I/Os are enabled. - * 0b00000..None - * 0b00001..Wake up I/O 0 - * 0b00010..Wake up I/O 1 - * 0b00100..Wake up I/O 2 - * 0b01000..Wake up I/O 3 - * 0b10000..Wake up I/O 4 - */ -#define PMC_WAKEIOCAUSE_WAKEUPIO_EVENTS_ORDER(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUPIO_EVENTS_ORDER_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUPIO_EVENTS_ORDER_MASK) -/*! @} */ - -/*! @name LIFECYCLESTATE - Life Cycle State as configured in the OTP */ -/*! @{ */ - -#define PMC_LIFECYCLESTATE_LC_MASK (0xFFU) -#define PMC_LIFECYCLESTATE_LC_SHIFT (0U) -/*! LC - Life Cycle state - */ -#define PMC_LIFECYCLESTATE_LC(x) (((uint32_t)(((uint32_t)(x)) << PMC_LIFECYCLESTATE_LC_SHIFT)) & PMC_LIFECYCLESTATE_LC_MASK) -/*! @} */ - -/*! @name STATUSPWR - Power status from various analog modules (DCDC, LDO, etc) */ -/*! @{ */ - -#define PMC_STATUSPWR_DCDCPWROK_MASK (0x1U) -#define PMC_STATUSPWR_DCDCPWROK_SHIFT (0U) -/*! DCDCPWROK - DCDC converter power OK. - */ -#define PMC_STATUSPWR_DCDCPWROK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSPWR_DCDCPWROK_SHIFT)) & PMC_STATUSPWR_DCDCPWROK_MASK) - -#define PMC_STATUSPWR_LDOCOREPWROK_MASK (0x10U) -#define PMC_STATUSPWR_LDOCOREPWROK_SHIFT (4U) -/*! LDOCOREPWROK - CORE LDO power OK. - */ -#define PMC_STATUSPWR_LDOCOREPWROK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSPWR_LDOCOREPWROK_SHIFT)) & PMC_STATUSPWR_LDOCOREPWROK_MASK) -/*! @} */ - -/*! @name STATUSCLK - Clock status */ -/*! @{ */ - -#define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U) -#define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U) -/*! XTAL32KOK - XTAL oscillator 32 K OK signal. - */ -#define PMC_STATUSCLK_XTAL32KOK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK) - -#define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U) -#define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U) -/*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. - * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared. - * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared. - */ -#define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK) -/*! @} */ - -/*! @name AOREG0 - Always-on 0 */ -/*! @{ */ - -#define PMC_AOREG0_DATA_15_0_MASK (0xFFFFU) -#define PMC_AOREG0_DATA_15_0_SHIFT (0U) -/*! DATA_15_0 - General purpose always on domain data storage. - */ -#define PMC_AOREG0_DATA_15_0(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG0_DATA_15_0_SHIFT)) & PMC_AOREG0_DATA_15_0_MASK) -/*! @} */ - -/*! @name AOREG1 - Always-on 1 */ -/*! @{ */ - -#define PMC_AOREG1_POR_MASK (0x10U) -#define PMC_AOREG1_POR_SHIFT (4U) -/*! POR - The last chip reset was caused by a Power On Reset. - */ -#define PMC_AOREG1_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_POR_SHIFT)) & PMC_AOREG1_POR_MASK) - -#define PMC_AOREG1_PADRESET_MASK (0x20U) -#define PMC_AOREG1_PADRESET_SHIFT (5U) -/*! PADRESET - The last chip reset was caused by a Pin Reset. - */ -#define PMC_AOREG1_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_PADRESET_SHIFT)) & PMC_AOREG1_PADRESET_MASK) - -#define PMC_AOREG1_BODRESET_MASK (0x40U) -#define PMC_AOREG1_BODRESET_SHIFT (6U) -/*! BODRESET - The last chip reset was caused by a Brown Out Detector (BoD), either BOD_VDDMAIN or BOD_CORE. - */ -#define PMC_AOREG1_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BODRESET_SHIFT)) & PMC_AOREG1_BODRESET_MASK) - -#define PMC_AOREG1_SYSTEMRESET_MASK (0x80U) -#define PMC_AOREG1_SYSTEMRESET_SHIFT (7U) -/*! SYSTEMRESET - The last chip reset was caused by a System Reset requested by the ARM CPU. - */ -#define PMC_AOREG1_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SYSTEMRESET_SHIFT)) & PMC_AOREG1_SYSTEMRESET_MASK) - -#define PMC_AOREG1_WDTRESET_MASK (0x100U) -#define PMC_AOREG1_WDTRESET_SHIFT (8U) -/*! WDTRESET - The last chip reset was caused by the Watchdog Timer. - */ -#define PMC_AOREG1_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_WDTRESET_SHIFT)) & PMC_AOREG1_WDTRESET_MASK) - -#define PMC_AOREG1_SWRRESET_MASK (0x200U) -#define PMC_AOREG1_SWRRESET_SHIFT (9U) -/*! SWRRESET - The last chip reset was caused by a Software event. - */ -#define PMC_AOREG1_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SWRRESET_SHIFT)) & PMC_AOREG1_SWRRESET_MASK) - -#define PMC_AOREG1_DPDRESET_WAKEUPIO_MASK (0x400U) -#define PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT (10U) -/*! DPDRESET_WAKEUPIO - A Wake-up I/O reset event occured during DEEP-POWER-DOWN mode. - */ -#define PMC_AOREG1_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT)) & PMC_AOREG1_DPDRESET_WAKEUPIO_MASK) - -#define PMC_AOREG1_DPDRESET_RTC_MASK (0x800U) -#define PMC_AOREG1_DPDRESET_RTC_SHIFT (11U) -/*! DPDRESET_RTC - A RTC event occured during DEEP-POWER-DOWN mode. - */ -#define PMC_AOREG1_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_RTC_SHIFT)) & PMC_AOREG1_DPDRESET_RTC_MASK) - -#define PMC_AOREG1_DPDRESET_OSTIMER_MASK (0x1000U) -#define PMC_AOREG1_DPDRESET_OSTIMER_SHIFT (12U) -/*! DPDRESET_OSTIMER - An OS Timer event occured during a DEEP-POWER-DOWN mode. - */ -#define PMC_AOREG1_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_OSTIMER_SHIFT)) & PMC_AOREG1_DPDRESET_OSTIMER_MASK) - -#define PMC_AOREG1_CDOGRESET_MASK (0x2000U) -#define PMC_AOREG1_CDOGRESET_SHIFT (13U) -/*! CDOGRESET - The last chip reset was caused by the code Watchdog. - */ -#define PMC_AOREG1_CDOGRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_CDOGRESET_SHIFT)) & PMC_AOREG1_CDOGRESET_MASK) - -#define PMC_AOREG1_DPD_EVENTS_ORDER_MASK (0x1C000U) -#define PMC_AOREG1_DPD_EVENTS_ORDER_SHIFT (14U) -/*! DPD_EVENTS_ORDER - In DEEP-POWER-DOWN mode, indicates which reset event occured first, between a - * wake up I/O event (in DEEP-POWER-DOWN), a RTC event (in DEEP-POWER-DOWN) and a OS Timer event - * (in DEEP-POWER-DOWN). May be usefull when several reset events are enabled during - * DEEP-POWER-DOWN. - * 0b000..No event - * 0b001..WAKEUPIO - * 0b010..RTC - * 0b011..Both WAKEUPIO and RTC events occured at the same time (the 2 events occured within 1 nano-second of each other) - * 0b100..OSTIMER - * 0b101..Both WAKEUPIO and OSTIMER events occured at the same time (the 2 events occured within 1 nano-second of each other) - * 0b110..Both RTC and OSTIMER events occured at the same time (the 2 events occured within 1 nano-second of each other) - * 0b111..WAKEUPIO, RTC and OSTIMER events occured at the same time (the 3 events occured within 1 nano-second of each other) - */ -#define PMC_AOREG1_DPD_EVENTS_ORDER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPD_EVENTS_ORDER_SHIFT)) & PMC_AOREG1_DPD_EVENTS_ORDER_MASK) - -#define PMC_AOREG1_BOOTERRORCOUNTER_MASK (0xF000000U) -#define PMC_AOREG1_BOOTERRORCOUNTER_SHIFT (24U) -/*! BOOTERRORCOUNTER - ROM Boot Fatal Error Counter. - */ -#define PMC_AOREG1_BOOTERRORCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BOOTERRORCOUNTER_SHIFT)) & PMC_AOREG1_BOOTERRORCOUNTER_MASK) -/*! @} */ - -/*! @name MISCCTRL - Miscellaneous Control Register for PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_MISCCTRL_VREF_ISO_MASK (0x10000U) -#define PMC_MISCCTRL_VREF_ISO_SHIFT (16U) -/*! VREF_ISO - VREF isolation control. - * 0b0..VREF module isolation is disabled. - * 0b1..VREF module isolation is enabled. - */ -#define PMC_MISCCTRL_VREF_ISO(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_VREF_ISO_SHIFT)) & PMC_MISCCTRL_VREF_ISO_MASK) -/*! @} */ - -/*! @name RTCOSC32K - 32 KHz clocks source control */ -/*! @{ */ - -#define PMC_RTCOSC32K_SEL_MASK (0x1U) -#define PMC_RTCOSC32K_SEL_SHIFT (0U) -/*! SEL - Select the 32K oscillator to be used in for the RTC, the OS Event Timer and the rest of - * the SoC (either XTAL32KHz or FRO32KHz) . - * 0b0..FRO 32 KHz. - * 0b1..XTAL 32KHz. - */ -#define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK) -/*! @} */ - -/*! @name OSEVENTTIMER - OS Event Timer control */ -/*! @{ */ - -#define PMC_OSEVENTTIMER_SOFTRESET_MASK (0x1U) -#define PMC_OSEVENTTIMER_SOFTRESET_SHIFT (0U) -/*! SOFTRESET - Active high reset. - */ -#define PMC_OSEVENTTIMER_SOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSEVENTTIMER_SOFTRESET_SHIFT)) & PMC_OSEVENTTIMER_SOFTRESET_MASK) - -#define PMC_OSEVENTTIMER_CLOCKENABLE_MASK (0x2U) -#define PMC_OSEVENTTIMER_CLOCKENABLE_SHIFT (1U) -/*! CLOCKENABLE - Enable OSTIMER 32 KHz clock. - */ -#define PMC_OSEVENTTIMER_CLOCKENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSEVENTTIMER_CLOCKENABLE_SHIFT)) & PMC_OSEVENTTIMER_CLOCKENABLE_MASK) - -#define PMC_OSEVENTTIMER_DPDWAKEUPENABLE_MASK (0x4U) -#define PMC_OSEVENTTIMER_DPDWAKEUPENABLE_SHIFT (2U) -/*! DPDWAKEUPENABLE - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode). - */ -#define PMC_OSEVENTTIMER_DPDWAKEUPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSEVENTTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSEVENTTIMER_DPDWAKEUPENABLE_MASK) - -#define PMC_OSEVENTTIMER_SELCLOCK_MASK (0x18U) -#define PMC_OSEVENTTIMER_SELCLOCK_SHIFT (3U) -/*! SELCLOCK - Select OS Event Timer Clock source - * 0b00..32-KHz Free Running Oscillator (FRO) - * 0b01..32-KHz Crystal Oscillator (XTAL) - * 0b10..1-MHz FRO - * 0b11..System Bus clock - */ -#define PMC_OSEVENTTIMER_SELCLOCK(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSEVENTTIMER_SELCLOCK_SHIFT)) & PMC_OSEVENTTIMER_SELCLOCK_MASK) -/*! @} */ - -/*! @name PDSLEEPCFG1 - Controls the power to various modules during Low Power modes - DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ -/*! @{ */ - -#define PMC_PDSLEEPCFG1_PDEN_CMPBIAS_MASK (0x1U) -#define PMC_PDSLEEPCFG1_PDEN_CMPBIAS_SHIFT (0U) -/*! PDEN_CMPBIAS - Controls Comparators 1/2/3 Bias power during DEEP-SLEEP (always shut down during POWER-DOWN & DEEP-POWER-DOWN). - * 0b0..Analog Bias is powered on during low power mode. - * 0b1..Analog Bias is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG1_PDEN_CMPBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PDEN_CMPBIAS_SHIFT)) & PMC_PDSLEEPCFG1_PDEN_CMPBIAS_MASK) - -#define PMC_PDSLEEPCFG1_PDEN_HSCMP0_DAC_MASK (0x2U) -#define PMC_PDSLEEPCFG1_PDEN_HSCMP0_DAC_SHIFT (1U) -/*! PDEN_HSCMP0_DAC - Controls High Speed Comparator0 DAC power during DEEP-SLEEP (always shut down during POWER-DOWN & DEEP-POWER-DOWN). - * 0b0..High Speed Comparator0 DAC is powered on during low power mode. - * 0b1..High Speed Comparator0 DAC is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG1_PDEN_HSCMP0_DAC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PDEN_HSCMP0_DAC_SHIFT)) & PMC_PDSLEEPCFG1_PDEN_HSCMP0_DAC_MASK) - -#define PMC_PDSLEEPCFG1_PDEN_HSCMP1_DAC_MASK (0x4U) -#define PMC_PDSLEEPCFG1_PDEN_HSCMP1_DAC_SHIFT (2U) -/*! PDEN_HSCMP1_DAC - Controls High Speed Comparator1 DAC power during DEEP-SLEEP (always shut down during POWER-DOWN & DEEP-POWER-DOWN). - * 0b0..High Speed Comparator1 DAC is powered on during low power mode. - * 0b1..High Speed Comparator1 DAC is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG1_PDEN_HSCMP1_DAC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PDEN_HSCMP1_DAC_SHIFT)) & PMC_PDSLEEPCFG1_PDEN_HSCMP1_DAC_MASK) - -#define PMC_PDSLEEPCFG1_PDEN_HSCMP2_DAC_MASK (0x8U) -#define PMC_PDSLEEPCFG1_PDEN_HSCMP2_DAC_SHIFT (3U) -/*! PDEN_HSCMP2_DAC - Controls High Speed Comparator2 DAC power during DEEP-SLEEP (always shut down during POWER-DOWN & DEEP-POWER-DOWN). - * 0b0..High Speed Comparator2 DAC is powered on during low power mode. - * 0b1..High Speed Comparator2 DAC is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG1_PDEN_HSCMP2_DAC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PDEN_HSCMP2_DAC_SHIFT)) & PMC_PDSLEEPCFG1_PDEN_HSCMP2_DAC_MASK) - -#define PMC_PDSLEEPCFG1_PDEN_DAC0_MASK (0x10U) -#define PMC_PDSLEEPCFG1_PDEN_DAC0_SHIFT (4U) -/*! PDEN_DAC0 - Controls DAC0 power during DEEP-SLEEP & POWER-DOWN (always shut down during DEEP-POWER-DOWN). - * 0b0..DAC0 is powered on during low power mode. - * 0b1..DAC0 is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG1_PDEN_DAC0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PDEN_DAC0_SHIFT)) & PMC_PDSLEEPCFG1_PDEN_DAC0_MASK) - -#define PMC_PDSLEEPCFG1_PDEN_DAC1_MASK (0x20U) -#define PMC_PDSLEEPCFG1_PDEN_DAC1_SHIFT (5U) -/*! PDEN_DAC1 - Controls DAC1 power during DEEP-SLEEP & POWER-DOWN (always shut down during DEEP-POWER-DOWN). - * 0b0..DAC1 is powered on during low power mode. - * 0b1..DAC1 is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG1_PDEN_DAC1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PDEN_DAC1_SHIFT)) & PMC_PDSLEEPCFG1_PDEN_DAC1_MASK) - -#define PMC_PDSLEEPCFG1_PDEN_DAC2_MASK (0x40U) -#define PMC_PDSLEEPCFG1_PDEN_DAC2_SHIFT (6U) -/*! PDEN_DAC2 - Controls DAC2 power during DEEP-SLEEP & POWER-DOWN (always shut down during DEEP-POWER-DOWN). - * 0b0..DAC2 is powered on during low power mode. - * 0b1..DAC2 is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG1_PDEN_DAC2(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PDEN_DAC2_SHIFT)) & PMC_PDSLEEPCFG1_PDEN_DAC2_MASK) - -#define PMC_PDSLEEPCFG1_STOPEN_DAC0_MASK (0x80U) -#define PMC_PDSLEEPCFG1_STOPEN_DAC0_SHIFT (7U) -/*! STOPEN_DAC0 - Controls DAC0 Stop mode during DEEP-SLEEP & POWER-DOWN (DAC stop mode is always disabled in DEEP-POWER-DOWN). - * 0b0..DAC Stop Mode is disabled. - * 0b1..DAC Stop Mode is enabled. - */ -#define PMC_PDSLEEPCFG1_STOPEN_DAC0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_STOPEN_DAC0_SHIFT)) & PMC_PDSLEEPCFG1_STOPEN_DAC0_MASK) - -#define PMC_PDSLEEPCFG1_STOPEN_DAC1_MASK (0x100U) -#define PMC_PDSLEEPCFG1_STOPEN_DAC1_SHIFT (8U) -/*! STOPEN_DAC1 - Controls DAC1 Stop mode during DEEP-SLEEP & POWER-DOWN (DAC stop mode is always disabled in DEEP-POWER-DOWN). - * 0b0..DAC Stop Mode is disabled. - * 0b1..DAC Stop Mode is enabled. - */ -#define PMC_PDSLEEPCFG1_STOPEN_DAC1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_STOPEN_DAC1_SHIFT)) & PMC_PDSLEEPCFG1_STOPEN_DAC1_MASK) - -#define PMC_PDSLEEPCFG1_STOPEN_DAC2_MASK (0x200U) -#define PMC_PDSLEEPCFG1_STOPEN_DAC2_SHIFT (9U) -/*! STOPEN_DAC2 - Controls DAC2 Stop mode during DEEP-SLEEP & POWER-DOWN (DAC stop mode is always disabled in DEEP-POWER-DOWN). - * 0b0..DAC Stop Mode is disabled. - * 0b1..DAC Stop Mode is enabled. - */ -#define PMC_PDSLEEPCFG1_STOPEN_DAC2(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_STOPEN_DAC2_SHIFT)) & PMC_PDSLEEPCFG1_STOPEN_DAC2_MASK) -/*! @} */ - -/*! @name TIMEOUTEVENTS - Record time-out errors that might occur at different stages during IC power up */ -/*! @{ */ - -#define PMC_TIMEOUTEVENTS_PWUP_DCDC_OK_MASK (0x1U) -#define PMC_TIMEOUTEVENTS_PWUP_DCDC_OK_SHIFT (0U) -/*! PWUP_DCDC_OK - 1: a time out event occured during power up when waiting for DCDC to become functional. - */ -#define PMC_TIMEOUTEVENTS_PWUP_DCDC_OK(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PWUP_DCDC_OK_SHIFT)) & PMC_TIMEOUTEVENTS_PWUP_DCDC_OK_MASK) - -#define PMC_TIMEOUTEVENTS_PWUP_LDOFLASHNV_OK_MASK (0x2U) -#define PMC_TIMEOUTEVENTS_PWUP_LDOFLASHNV_OK_SHIFT (1U) -/*! PWUP_LDOFLASHNV_OK - 1: a time out event occured during power up when waiting for LDO Flash NV to become functional. - */ -#define PMC_TIMEOUTEVENTS_PWUP_LDOFLASHNV_OK(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PWUP_LDOFLASHNV_OK_SHIFT)) & PMC_TIMEOUTEVENTS_PWUP_LDOFLASHNV_OK_MASK) - -#define PMC_TIMEOUTEVENTS_PWUP_SRAM_WAKEUP_MASK (0x4U) -#define PMC_TIMEOUTEVENTS_PWUP_SRAM_WAKEUP_SHIFT (2U) -/*! PWUP_SRAM_WAKEUP - 1: a time out event occured during power up when waiting for SRAM to become functional. - */ -#define PMC_TIMEOUTEVENTS_PWUP_SRAM_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PWUP_SRAM_WAKEUP_SHIFT)) & PMC_TIMEOUTEVENTS_PWUP_SRAM_WAKEUP_MASK) - -#define PMC_TIMEOUTEVENTS_PWUP_FLASHINIT_DONE_MASK (0x8U) -#define PMC_TIMEOUTEVENTS_PWUP_FLASHINIT_DONE_SHIFT (3U) -/*! PWUP_FLASHINIT_DONE - 1: a time out event occured during power up when waiting for Flash initialization. - */ -#define PMC_TIMEOUTEVENTS_PWUP_FLASHINIT_DONE(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PWUP_FLASHINIT_DONE_SHIFT)) & PMC_TIMEOUTEVENTS_PWUP_FLASHINIT_DONE_MASK) - -#define PMC_TIMEOUTEVENTS_DSLP_LDOFLASH_SRAM_OFF_MASK (0x10U) -#define PMC_TIMEOUTEVENTS_DSLP_LDOFLASH_SRAM_OFF_SHIFT (4U) -/*! DSLP_LDOFLASH_SRAM_OFF - 1: a time out event occured during deep sleep when waiting for LDO Flash NV or SRAM shut off. - */ -#define PMC_TIMEOUTEVENTS_DSLP_LDOFLASH_SRAM_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_DSLP_LDOFLASH_SRAM_OFF_SHIFT)) & PMC_TIMEOUTEVENTS_DSLP_LDOFLASH_SRAM_OFF_MASK) - -#define PMC_TIMEOUTEVENTS_DSLP_DCDC_OK_MASK (0x20U) -#define PMC_TIMEOUTEVENTS_DSLP_DCDC_OK_SHIFT (5U) -/*! DSLP_DCDC_OK - 1: a time out event occured during deep sleep when waiting for DCDC to become functional. - */ -#define PMC_TIMEOUTEVENTS_DSLP_DCDC_OK(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_DSLP_DCDC_OK_SHIFT)) & PMC_TIMEOUTEVENTS_DSLP_DCDC_OK_MASK) - -#define PMC_TIMEOUTEVENTS_DSLP_LDOFLASHNV_OK_MASK (0x40U) -#define PMC_TIMEOUTEVENTS_DSLP_LDOFLASHNV_OK_SHIFT (6U) -/*! DSLP_LDOFLASHNV_OK - 1: a time out event occured during deep sleep when waiting for LDO Flash NV to become functional. - */ -#define PMC_TIMEOUTEVENTS_DSLP_LDOFLASHNV_OK(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_DSLP_LDOFLASHNV_OK_SHIFT)) & PMC_TIMEOUTEVENTS_DSLP_LDOFLASHNV_OK_MASK) - -#define PMC_TIMEOUTEVENTS_DSLP_SRAM_WAKEUP_MASK (0x80U) -#define PMC_TIMEOUTEVENTS_DSLP_SRAM_WAKEUP_SHIFT (7U) -/*! DSLP_SRAM_WAKEUP - 1: a time out event occured during deep sleep when waiting for SRAM to become functional. - */ -#define PMC_TIMEOUTEVENTS_DSLP_SRAM_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_DSLP_SRAM_WAKEUP_SHIFT)) & PMC_TIMEOUTEVENTS_DSLP_SRAM_WAKEUP_MASK) - -#define PMC_TIMEOUTEVENTS_PDWN_LDOFLASH_SRAM_OFF_MASK (0x100U) -#define PMC_TIMEOUTEVENTS_PDWN_LDOFLASH_SRAM_OFF_SHIFT (8U) -/*! PDWN_LDOFLASH_SRAM_OFF - 1: a time out event occured during power down when waiting for for LDO Flash NV or SRAM shut off. - */ -#define PMC_TIMEOUTEVENTS_PDWN_LDOFLASH_SRAM_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PDWN_LDOFLASH_SRAM_OFF_SHIFT)) & PMC_TIMEOUTEVENTS_PDWN_LDOFLASH_SRAM_OFF_MASK) - -#define PMC_TIMEOUTEVENTS_PDWN_DCDC_BODVDDMAIN_OK_MASK (0x200U) -#define PMC_TIMEOUTEVENTS_PDWN_DCDC_BODVDDMAIN_OK_SHIFT (9U) -/*! PDWN_DCDC_BODVDDMAIN_OK - 1: a time out event occured during power down when waiting for DCDC or BOD_VDDMAIN to become functional. - */ -#define PMC_TIMEOUTEVENTS_PDWN_DCDC_BODVDDMAIN_OK(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PDWN_DCDC_BODVDDMAIN_OK_SHIFT)) & PMC_TIMEOUTEVENTS_PDWN_DCDC_BODVDDMAIN_OK_MASK) - -#define PMC_TIMEOUTEVENTS_PDWN_LDOFLASHNV_OK_MASK (0x400U) -#define PMC_TIMEOUTEVENTS_PDWN_LDOFLASHNV_OK_SHIFT (10U) -/*! PDWN_LDOFLASHNV_OK - 1: a time out event occured during power down when waiting for LDO Flash NV to become functional. - */ -#define PMC_TIMEOUTEVENTS_PDWN_LDOFLASHNV_OK(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PDWN_LDOFLASHNV_OK_SHIFT)) & PMC_TIMEOUTEVENTS_PDWN_LDOFLASHNV_OK_MASK) - -#define PMC_TIMEOUTEVENTS_PDWN_SRAM_WAKEUP_MASK (0x800U) -#define PMC_TIMEOUTEVENTS_PDWN_SRAM_WAKEUP_SHIFT (11U) -/*! PDWN_SRAM_WAKEUP - 1: a time out event occured during power down when waiting for SRAM to become functional. - */ -#define PMC_TIMEOUTEVENTS_PDWN_SRAM_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PDWN_SRAM_WAKEUP_SHIFT)) & PMC_TIMEOUTEVENTS_PDWN_SRAM_WAKEUP_MASK) - -#define PMC_TIMEOUTEVENTS_PDWN_FLASHINIT_DONE_MASK (0x1000U) -#define PMC_TIMEOUTEVENTS_PDWN_FLASHINIT_DONE_SHIFT (12U) -/*! PDWN_FLASHINIT_DONE - 1: a time out event occured during power down when waiting for Flash initialization. - */ -#define PMC_TIMEOUTEVENTS_PDWN_FLASHINIT_DONE(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PDWN_FLASHINIT_DONE_SHIFT)) & PMC_TIMEOUTEVENTS_PDWN_FLASHINIT_DONE_MASK) -/*! @} */ - -/*! @name PDSLEEPCFG0 - Controls the power to various modules during Low Power modes - DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ -/*! @{ */ - -#define PMC_PDSLEEPCFG0_PDEN_BIAS_MASK (0x2U) -#define PMC_PDSLEEPCFG0_PDEN_BIAS_SHIFT (1U) -/*! PDEN_BIAS - Controls Analog Bias power during DEEP-SLEEP and POWER-DOWN (always shut down during DEEP-POWER-DOWN). - * 0b0..Analog Bias is powered on during low power mode. - * 0b1..Analog Bias is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BIAS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BIAS_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_BODCORE_MASK (0x4U) -#define PMC_PDSLEEPCFG0_PDEN_BODCORE_SHIFT (2U) -/*! PDEN_BODCORE - Controls Core Logic BoD power during DEEP-SLEEP and POWER-DOWN (always shut down during DEEP-POWER-DOWN). - * 0b0..BOD_CORE is powered on during low power mode. - * 0b1..BOD_CORE is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_BODCORE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BODCORE_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BODCORE_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_BODVDDMAIN_MASK (0x8U) -#define PMC_PDSLEEPCFG0_PDEN_BODVDDMAIN_SHIFT (3U) -/*! PDEN_BODVDDMAIN - Controls BOD_VDDMAIN power during DEEP-SLEEP and POWER-DOWN (always shut down during DEEP-POWER-DOWN). - * 0b0..BOD_VDDMAIN is powered on during low power mode. - * 0b1..BOD_VDDMAIN is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_BODVDDMAIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BODVDDMAIN_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BODVDDMAIN_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_FRO1M_MASK (0x10U) -#define PMC_PDSLEEPCFG0_PDEN_FRO1M_SHIFT (4U) -/*! PDEN_FRO1M - Controls 1 MHz Free Running Oscillator power during DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN. - * 0b0..FRO 1MHz is powered on during low power mode. - * 0b1..FRO 1MHz is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_FRO1M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO1M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO1M_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_FRO192M_MASK (0x20U) -#define PMC_PDSLEEPCFG0_PDEN_FRO192M_SHIFT (5U) -/*! PDEN_FRO192M - Controls 192MHz Free Running Oscillator power during DEEP-SLEEP (always shut down - * during POWER-DOWN and DEEP-POWER-DOWN). - * 0b0..FRO 192 MHz is powered on during low power mode. - * 0b1..FRO 192 MHz is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_FRO192M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO192M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO192M_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_FRO32K_MASK (0x40U) -#define PMC_PDSLEEPCFG0_PDEN_FRO32K_SHIFT (6U) -/*! PDEN_FRO32K - Controls power during DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN. - * 0b0..FRO 32 KHz is powered on during low power mode. - * 0b1..FRO 32 KHz is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO32K_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_XTAL32K_MASK (0x80U) -#define PMC_PDSLEEPCFG0_PDEN_XTAL32K_SHIFT (7U) -/*! PDEN_XTAL32K - Controls crystal 32 KHz power during DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN. - * 0b0..crystal 32 KHz is powered on during low power mode. - * 0b1..crystal 32 KHz is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_XTAL32K_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_XTALHF_MASK (0x100U) -#define PMC_PDSLEEPCFG0_PDEN_XTALHF_SHIFT (8U) -/*! PDEN_XTALHF - Controls high speed crystal power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). - * 0b0..High speed crystal is powered on during low power mode. - * 0b1..High speed crystal is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_XTALHF(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_XTALHF_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_XTALHF_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_PLL0_MASK (0x200U) -#define PMC_PDSLEEPCFG0_PDEN_PLL0_SHIFT (9U) -/*! PDEN_PLL0 - Controls System PLL (also refered as PLL0) power during DEEP-SLEEP (always shut down - * during POWER-DOWN and DEEP-POWER-DOWN). - * 0b0..System PLL (also refered as PLL0) is powered on during low power mode. - * 0b1..System PLL (also refered as PLL0) is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL0_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL0_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_PLL1_MASK (0x400U) -#define PMC_PDSLEEPCFG0_PDEN_PLL1_SHIFT (10U) -/*! PDEN_PLL1 - Controls USB PLL (also refered as PLL1) power during DEEP-SLEEP (always shut down - * during POWER-DOWN and DEEP-POWER-DOWN). - * 0b0..USB PLL (also refered as PLL1) is powered on during low power mode. - * 0b1..USB PLL (also refered as PLL1) is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL1_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL1_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY_MASK (0x800U) -#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY_SHIFT (11U) -/*! PDEN_USBFSPHY - Controls USB Full Speed phy power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). - * 0b0..USB Full Speed phy is powered on during low power mode. - * 0b1..USB Full Speed phy is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_USBFSPHY_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_COMP_MASK (0x2000U) -#define PMC_PDSLEEPCFG0_PDEN_COMP_SHIFT (13U) -/*! PDEN_COMP - Controls Analog Comparator power during DEEP-SLEEP and POWER-DOWN (always shut down during DEEP-POWER-DOWN). - * 0b0..Analog Comparator is powered on during low power mode. - * 0b1..Analog Comparator is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_COMP_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_COMP_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_LDOMEM_MASK (0x10000U) -#define PMC_PDSLEEPCFG0_PDEN_LDOMEM_SHIFT (16U) -/*! PDEN_LDOMEM - Controls Memories LDO power during DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN. - * 0b0..Memories LDO is powered on during low power mode. - * 0b1..Memories LDO is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDOMEM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOMEM_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOMEM_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_LDOEFUSEPROG_MASK (0x40000U) -#define PMC_PDSLEEPCFG0_PDEN_LDOEFUSEPROG_SHIFT (18U) -/*! PDEN_LDOEFUSEPROG - Controls USB high speed LDO power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). - * 0b0..USB high speed LDO is powered on during low power mode. - * 0b1..USB high speed LDO is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDOEFUSEPROG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOEFUSEPROG_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOEFUSEPROG_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_LDOXTALHF_MASK (0x100000U) -#define PMC_PDSLEEPCFG0_PDEN_LDOXTALHF_SHIFT (20U) -/*! PDEN_LDOXTALHF - Controls High speed crystal LDO power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). - * 0b0..High speed crystal LDO is powered on during low power mode. - * 0b1..High speed crystal LDO is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDOXTALHF(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOXTALHF_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOXTALHF_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_MASK (0x200000U) -#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_SHIFT (21U) -/*! PDEN_LDOFLASHNV - Controls Flash NV (high voltage) LDO power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). - * 0b0..Flash NV (high voltage) is powered on during low power mode. - * 0b1..Flash NV (high voltage) is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) -#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_SHIFT (23U) -/*! PDEN_PLL0_SSCG - Controls PLL0 Spread Sprectrum module power during DEEP-SLEEP (PLL0 Spread - * Spectrum is always shut down during POWER-DOWN and DEEP-POWER-DOWN). - * 0b0..PLL0 Spread Sprectrum module is powered on during low power mode. - * 0b1..PLL0 Spread Sprectrum module is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_ROM_MASK (0x1000000U) -#define PMC_PDSLEEPCFG0_PDEN_ROM_SHIFT (24U) -/*! PDEN_ROM - Controls ROM power during DEEP-SLEEP (ROM is always shut down during POWER-DOWN and DEEP-POWER-DOWN). - * 0b0..ROM is powered on during low power mode. - * 0b1..ROM is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_ROM_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_ROM_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_HSCMP0_MASK (0x2000000U) -#define PMC_PDSLEEPCFG0_PDEN_HSCMP0_SHIFT (25U) -/*! PDEN_HSCMP0 - Controls High Speed Comparator0 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). - * 0b0..High Speed Comparator is powered on during low power mode. - * 0b1..High Speed Comparator is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_HSCMP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_HSCMP0_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_HSCMP0_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_HSCMP1_MASK (0x4000000U) -#define PMC_PDSLEEPCFG0_PDEN_HSCMP1_SHIFT (26U) -/*! PDEN_HSCMP1 - Controls High Speed Comparator1 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). - * 0b0..High Speed Comparator is powered on during low power mode. - * 0b1..High Speed Comparator is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_HSCMP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_HSCMP1_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_HSCMP1_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_HSCMP2_MASK (0x8000000U) -#define PMC_PDSLEEPCFG0_PDEN_HSCMP2_SHIFT (27U) -/*! PDEN_HSCMP2 - Controls High Speed Comparator2 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). - * 0b0..High Speed Comparator is powered on during low power mode. - * 0b1..High Speed Comparator is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_HSCMP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_HSCMP2_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_HSCMP2_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_OPAMP0_MASK (0x10000000U) -#define PMC_PDSLEEPCFG0_PDEN_OPAMP0_SHIFT (28U) -/*! PDEN_OPAMP0 - Controls Operational Amplifier0 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). - * 0b0..Operational Amplifier is powered on during low power mode. - * 0b1..Operational Amplifier is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_OPAMP0_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_OPAMP0_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_OPAMP1_MASK (0x20000000U) -#define PMC_PDSLEEPCFG0_PDEN_OPAMP1_SHIFT (29U) -/*! PDEN_OPAMP1 - Controls Operational Amplifier1 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). - * 0b0..Operational Amplifier is powered on during low power mode. - * 0b1..Operational Amplifier is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_OPAMP1_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_OPAMP1_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_OPAMP2_MASK (0x40000000U) -#define PMC_PDSLEEPCFG0_PDEN_OPAMP2_SHIFT (30U) -/*! PDEN_OPAMP2 - Controls Operational Amplifier2 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). - * 0b0..Operational Amplifier is powered on during low power mode. - * 0b1..Operational Amplifier is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_OPAMP2_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_OPAMP2_MASK) - -#define PMC_PDSLEEPCFG0_PDEN_VREF_MASK (0x80000000U) -#define PMC_PDSLEEPCFG0_PDEN_VREF_SHIFT (31U) -/*! PDEN_VREF - Controls VREF power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). - * 0b0..VREF is powered on during low power mode. - * 0b1..VREF is powered off during low power mode. - */ -#define PMC_PDSLEEPCFG0_PDEN_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_VREF_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_VREF_MASK) -/*! @} */ - -/*! @name SRAMRETCTRL - Controls all SRAM instances power down modes during Low Power modes [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ -/*! @{ */ - -#define PMC_SRAMRETCTRL_RETEN_RAM_X0_MASK (0x1U) -#define PMC_SRAMRETCTRL_RETEN_RAM_X0_SHIFT (0U) -/*! RETEN_RAM_X0 - Controls RAM_X0 power down modes during low power modes. - * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is - * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM - * instance is in 'Shutdown mode' (In this mode there is no data retention). - * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). - */ -#define PMC_SRAMRETCTRL_RETEN_RAM_X0(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_X0_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_X0_MASK) - -#define PMC_SRAMRETCTRL_RETEN_RAM_00_MASK (0x2U) -#define PMC_SRAMRETCTRL_RETEN_RAM_00_SHIFT (1U) -/*! RETEN_RAM_00 - Controls RAM_00 power down modes during low power modes. - * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is - * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM - * instance is in 'Shutdown mode' (In this mode there is no data retention). - * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). - */ -#define PMC_SRAMRETCTRL_RETEN_RAM_00(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_00_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_00_MASK) - -#define PMC_SRAMRETCTRL_RETEN_RAM_01_MASK (0x4U) -#define PMC_SRAMRETCTRL_RETEN_RAM_01_SHIFT (2U) -/*! RETEN_RAM_01 - Controls RAM_01 power down modes during low power modes. - * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is - * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM - * instance is in 'Shutdown mode' (In this mode there is no data retention). - * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). - */ -#define PMC_SRAMRETCTRL_RETEN_RAM_01(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_01_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_01_MASK) - -#define PMC_SRAMRETCTRL_RETEN_RAM_02_MASK (0x8U) -#define PMC_SRAMRETCTRL_RETEN_RAM_02_SHIFT (3U) -/*! RETEN_RAM_02 - Controls RAM_02 power down modes during low power modes. - * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is - * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM - * instance is in 'Shutdown mode' (In this mode there is no data retention). - * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). - */ -#define PMC_SRAMRETCTRL_RETEN_RAM_02(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_02_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_02_MASK) - -#define PMC_SRAMRETCTRL_RETEN_RAM_03_MASK (0x10U) -#define PMC_SRAMRETCTRL_RETEN_RAM_03_SHIFT (4U) -/*! RETEN_RAM_03 - Controls RAM_03 power down modes during low power modes. - * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is - * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM - * instance is in 'Shutdown mode' (In this mode there is no data retention). - * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). - */ -#define PMC_SRAMRETCTRL_RETEN_RAM_03(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_03_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_03_MASK) - -#define PMC_SRAMRETCTRL_RETEN_RAM_10_MASK (0x20U) -#define PMC_SRAMRETCTRL_RETEN_RAM_10_SHIFT (5U) -/*! RETEN_RAM_10 - Controls RAM_10 power down modes during low power modes. - * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, whatever it is - * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM - * instance is in 'Shutdown mode' (In this mode there is no data retention). - * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). - */ -#define PMC_SRAMRETCTRL_RETEN_RAM_10(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_10_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_10_MASK) - -#define PMC_SRAMRETCTRL_RETEN_RAM_20_MASK (0x40U) -#define PMC_SRAMRETCTRL_RETEN_RAM_20_SHIFT (6U) -/*! RETEN_RAM_20 - Controls RAM_20 power down modes during low power modes. - * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, whatever it is - * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM - * instance is in 'Shutdown mode' (In this mode there is no data retention). - * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). - */ -#define PMC_SRAMRETCTRL_RETEN_RAM_20(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_20_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_20_MASK) - -#define PMC_SRAMRETCTRL_RETEN_RAM_30_MASK (0x80U) -#define PMC_SRAMRETCTRL_RETEN_RAM_30_SHIFT (7U) -/*! RETEN_RAM_30 - Controls RAM_30 power down modes during low power modes. - * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, whatever it is - * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM - * instance is in 'Shutdown mode' (In this mode there is no data retention). - * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). - */ -#define PMC_SRAMRETCTRL_RETEN_RAM_30(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_30_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_30_MASK) - -#define PMC_SRAMRETCTRL_RETEN_RAM_40_MASK (0x100U) -#define PMC_SRAMRETCTRL_RETEN_RAM_40_SHIFT (8U) -/*! RETEN_RAM_40 - Controls RAM_40 power down modes during low power modes. - * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is - * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM - * instance is in 'Shutdown mode' (In this mode there is no data retention). - * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). - */ -#define PMC_SRAMRETCTRL_RETEN_RAM_40(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_40_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_40_MASK) - -#define PMC_SRAMRETCTRL_RETEN_RAM_41_MASK (0x200U) -#define PMC_SRAMRETCTRL_RETEN_RAM_41_SHIFT (9U) -/*! RETEN_RAM_41 - Controls RAM_41 power down modes during low power modes. - * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is - * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM - * instance is in 'Shutdown mode' (In this mode there is no data retention). - * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). - */ -#define PMC_SRAMRETCTRL_RETEN_RAM_41(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_41_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_41_MASK) - -#define PMC_SRAMRETCTRL_RETEN_RAM_42_MASK (0x400U) -#define PMC_SRAMRETCTRL_RETEN_RAM_42_SHIFT (10U) -/*! RETEN_RAM_42 - Controls RAM_42 power down modes during low power modes. - * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is - * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM - * instance is in 'Shutdown mode' (In this mode there is no data retention). - * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). - */ -#define PMC_SRAMRETCTRL_RETEN_RAM_42(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_42_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_42_MASK) - -#define PMC_SRAMRETCTRL_RETEN_RAM_43_MASK (0x800U) -#define PMC_SRAMRETCTRL_RETEN_RAM_43_SHIFT (11U) -/*! RETEN_RAM_43 - Controls RAM_43 power down modes during low power modes. - * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is - * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM - * instance is in 'Shutdown mode' (In this mode there is no data retention). - * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). - */ -#define PMC_SRAMRETCTRL_RETEN_RAM_43(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_43_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_43_MASK) - -#define PMC_SRAMRETCTRL_RETEN_RAM_FLASHLPCACHE_MASK (0x1000U) -#define PMC_SRAMRETCTRL_RETEN_RAM_FLASHLPCACHE_SHIFT (12U) -/*! RETEN_RAM_FLASHLPCACHE - Controls Embedded Flash Cache SRAM power down modes during low power modes. - */ -#define PMC_SRAMRETCTRL_RETEN_RAM_FLASHLPCACHE(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_FLASHLPCACHE_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_FLASHLPCACHE_MASK) - -#define PMC_SRAMRETCTRL_RETEN_RAM_FLEXSPILPCACHE_MASK (0x2000U) -#define PMC_SRAMRETCTRL_RETEN_RAM_FLEXSPILPCACHE_SHIFT (13U) -/*! RETEN_RAM_FLEXSPILPCACHE - Controls FlexSPI Cache SRAM power down modes during low power modes. - */ -#define PMC_SRAMRETCTRL_RETEN_RAM_FLEXSPILPCACHE(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_FLEXSPILPCACHE_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_FLEXSPILPCACHE_MASK) - -#define PMC_SRAMRETCTRL_RETEN_H2PREG_FLEXSPI_MASK (0x4000U) -#define PMC_SRAMRETCTRL_RETEN_H2PREG_FLEXSPI_SHIFT (14U) -/*! RETEN_H2PREG_FLEXSPI - Controls FlexSPI Dual Port Register Files power down modes during deep - * sleep. In power-down and deep power-down modes, FlexSPI Dual Port Register Files are always - * shutoff. - * 0b0..DEEP-SLEEP: all FlexSPI dual port register files keep the configuration they had before entering - * DEEP-SLEEP. POWER-DOWN and DEEP-POWER-DOWN: all FlexSPI dual port register instances are shut off (In this mode - * there is no data retention). - * 0b1..DEEP-SLEEP: all FlexSPI Dual Port egister files are in 'Power Down' mode (In this mode there is data - * retention). POWER-DOWN and DEEP-POWER-DOWN: all FlexSPI dual port register instances are shut off (In this - * mode there is no data retention). - */ -#define PMC_SRAMRETCTRL_RETEN_H2PREG_FLEXSPI(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_H2PREG_FLEXSPI_SHIFT)) & PMC_SRAMRETCTRL_RETEN_H2PREG_FLEXSPI_MASK) -/*! @} */ - -/*! @name PDRUNCFG0 - Power configuration 0 */ -/*! @{ */ - -#define PMC_PDRUNCFG0_PDEN_DCDC_MASK (0x1U) -#define PMC_PDRUNCFG0_PDEN_DCDC_SHIFT (0U) -/*! PDEN_DCDC - Controls power to Bulk DCDC Converter. - * 0b0..DCDC is powered. - * 0b1..DCDC is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_DCDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_DCDC_SHIFT)) & PMC_PDRUNCFG0_PDEN_DCDC_MASK) - -#define PMC_PDRUNCFG0_PDEN_BIAS_MASK (0x2U) -#define PMC_PDRUNCFG0_PDEN_BIAS_SHIFT (1U) -/*! PDEN_BIAS - Controls power to . - * 0b0..Analog Bias is powered. - * 0b1..Analog Bias is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_BIAS_MASK) - -#define PMC_PDRUNCFG0_PDEN_BODCORE_MASK (0x4U) -#define PMC_PDRUNCFG0_PDEN_BODCORE_SHIFT (2U) -/*! PDEN_BODCORE - Controls power to Core Brown Out Detector (BOD_CORE). - * 0b0..BOD_CORE is powered. - * 0b1..BOD_CORE is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_BODCORE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODCORE_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODCORE_MASK) - -#define PMC_PDRUNCFG0_PDEN_BODVDDMAIN_MASK (0x8U) -#define PMC_PDRUNCFG0_PDEN_BODVDDMAIN_SHIFT (3U) -/*! PDEN_BODVDDMAIN - Controls power to VDDMAIN Brown Out Detector (BOD_VDDMAIN). - * 0b0..BOD_VDDMAIN is powered. - * 0b1..BOD_VDDMAIN is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_BODVDDMAIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVDDMAIN_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVDDMAIN_MASK) - -#define PMC_PDRUNCFG0_PDEN_FRO192M_MASK (0x20U) -#define PMC_PDRUNCFG0_PDEN_FRO192M_SHIFT (5U) -/*! PDEN_FRO192M - Controls power to the Free Running Oscillator (FRO) 192 MHz; The 12MHz, 48 MHz - * and 96 MHz clocks are derived from this FRO. - * 0b0..FRO 192MHz is powered. - * 0b1..FRO 192MHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_FRO192M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO192M_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) - -#define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U) -#define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U) -/*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. - * 0b0..FRO32KHz is powered. - * 0b1..FRO32KHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK) - -#define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U) -#define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U) -/*! PDEN_XTAL32K - Controls power to crystal 32 KHz. - * 0b0..Crystal 32KHz is powered. - * 0b1..Crystal 32KHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK) - -#define PMC_PDRUNCFG0_PDEN_XTALHF_MASK (0x100U) -#define PMC_PDRUNCFG0_PDEN_XTALHF_SHIFT (8U) -/*! PDEN_XTALHF - Controls power to high speed crystal. - * 0b0..High speed crystal is powered. - * 0b1..High speed crystal is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_XTALHF(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTALHF_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTALHF_MASK) - -#define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U) -#define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U) -/*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). - * 0b0..PLL0 is powered. - * 0b1..PLL0 is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK) - -#define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U) -#define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U) -/*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1). - * 0b0..PLL1 is powered. - * 0b1..PLL1 is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK) - -#define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK (0x800U) -#define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT (11U) -/*! PDEN_USBFSPHY - Controls power to USB Full Speed phy. - * 0b0..USB Full Speed phy is powered. - * 0b1..USB Full Speed phy is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK) - -#define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U) -#define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U) -/*! PDEN_COMP - Controls power to Analog Comparator. - * 0b0..Analog Comparator is powered. - * 0b1..Analog Comparator is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK) - -#define PMC_PDRUNCFG0_PDEN_LDOMEM_MASK (0x10000U) -#define PMC_PDRUNCFG0_PDEN_LDOMEM_SHIFT (16U) -/*! PDEN_LDOMEM - Controls power to Memories LDO. - * 0b0..Memories LDO is powered. - * 0b1..Memories LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOMEM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOMEM_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOMEM_MASK) - -#define PMC_PDRUNCFG0_PDEN_LDOEFUSEPROG_MASK (0x40000U) -#define PMC_PDRUNCFG0_PDEN_LDOEFUSEPROG_SHIFT (18U) -/*! PDEN_LDOEFUSEPROG - Controls power to eFUSE Programming LDO. - * 0b0..USB high speed LDO is powered. - * 0b1..USB high speed LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOEFUSEPROG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOEFUSEPROG_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOEFUSEPROG_MASK) - -#define PMC_PDRUNCFG0_PDEN_LDOXTALHF_MASK (0x100000U) -#define PMC_PDRUNCFG0_PDEN_LDOXTALHF_SHIFT (20U) -/*! PDEN_LDOXTALHF - Controls power to high speed crystal LDO. - * 0b0..High speed crystal LDO is powered. - * 0b1..High speed crystal LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOXTALHF(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXTALHF_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXTALHF_MASK) - -#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV_MASK (0x200000U) -#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV_SHIFT (21U) -/*! PDEN_LDOFLASHNV - Controls power to Flasn NV (high voltage) LDO. - * 0b0..Flash NV LDO is powered. - * 0b1..Flash NV LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOFLASHNV_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOFLASHNV_MASK) - -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U) -/*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. - * 0b0..PLL0 Sread spectrum module is powered. - * 0b1..PLL0 Sread spectrum module is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) - -#define PMC_PDRUNCFG0_PDEN_HSCMP0_MASK (0x2000000U) -#define PMC_PDRUNCFG0_PDEN_HSCMP0_SHIFT (25U) -/*! PDEN_HSCMP0 - Controls power to High Speed Comparator0 - * 0b0..High Speed Comparator0 is powered on. - * 0b1..High Speed Comparator0 is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_HSCMP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_HSCMP0_SHIFT)) & PMC_PDRUNCFG0_PDEN_HSCMP0_MASK) - -#define PMC_PDRUNCFG0_PDEN_HSCMP1_MASK (0x4000000U) -#define PMC_PDRUNCFG0_PDEN_HSCMP1_SHIFT (26U) -/*! PDEN_HSCMP1 - Controls power to High Speed Comparator1 - * 0b0..High Speed Comparator1 is powered on - * 0b1..High Speed Comparator1 is powered down - */ -#define PMC_PDRUNCFG0_PDEN_HSCMP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_HSCMP1_SHIFT)) & PMC_PDRUNCFG0_PDEN_HSCMP1_MASK) - -#define PMC_PDRUNCFG0_PDEN_HSCMP2_MASK (0x8000000U) -#define PMC_PDRUNCFG0_PDEN_HSCMP2_SHIFT (27U) -/*! PDEN_HSCMP2 - Controls power to High Speed Comparator2 - * 0b0..High Speed Comparator2 is powered on - * 0b1..High Speed Comparator2 is powered down - */ -#define PMC_PDRUNCFG0_PDEN_HSCMP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_HSCMP2_SHIFT)) & PMC_PDRUNCFG0_PDEN_HSCMP2_MASK) - -#define PMC_PDRUNCFG0_PDEN_OPAMP0_MASK (0x10000000U) -#define PMC_PDRUNCFG0_PDEN_OPAMP0_SHIFT (28U) -/*! PDEN_OPAMP0 - Controls power to Operational Amplifier0 - * 0b0..Operational Amplifier0 is powered on. - * 0b1..Operational Amplifier0 is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_OPAMP0_SHIFT)) & PMC_PDRUNCFG0_PDEN_OPAMP0_MASK) - -#define PMC_PDRUNCFG0_PDEN_OPAMP1_MASK (0x20000000U) -#define PMC_PDRUNCFG0_PDEN_OPAMP1_SHIFT (29U) -/*! PDEN_OPAMP1 - Controls power to Operational Amplifier1 - * 0b0..Operational Amplifier1 is powered on - * 0b1..Operational Amplifier1 is powered down - */ -#define PMC_PDRUNCFG0_PDEN_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_OPAMP1_SHIFT)) & PMC_PDRUNCFG0_PDEN_OPAMP1_MASK) - -#define PMC_PDRUNCFG0_PDEN_OPAMP2_MASK (0x40000000U) -#define PMC_PDRUNCFG0_PDEN_OPAMP2_SHIFT (30U) -/*! PDEN_OPAMP2 - Controls power to Operational Amplifier2 - * 0b0..Operational Amplifier2 is powered on - * 0b1..Operational Amplifier2 is powered down - */ -#define PMC_PDRUNCFG0_PDEN_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_OPAMP2_SHIFT)) & PMC_PDRUNCFG0_PDEN_OPAMP2_MASK) - -#define PMC_PDRUNCFG0_PDEN_VREF_MASK (0x80000000U) -#define PMC_PDRUNCFG0_PDEN_VREF_SHIFT (31U) -/*! PDEN_VREF - Controls power to VREF module - * 0b0..VREF is powered on. - * 0b1..VREF is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_VREF_SHIFT)) & PMC_PDRUNCFG0_PDEN_VREF_MASK) -/*! @} */ - -/*! @name PDRUNCFG1 - Power configuration 1 */ -/*! @{ */ - -#define PMC_PDRUNCFG1_PDEN_CMPBIAS_MASK (0x1U) -#define PMC_PDRUNCFG1_PDEN_CMPBIAS_SHIFT (0U) -/*! PDEN_CMPBIAS - Controls power of Comparators 1/2/3 bias. - * 0b0..Comparators 1/2/3 bias is powered. - * 0b1..Comparators 1/2/3 bias is powered down. - */ -#define PMC_PDRUNCFG1_PDEN_CMPBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PDEN_CMPBIAS_SHIFT)) & PMC_PDRUNCFG1_PDEN_CMPBIAS_MASK) - -#define PMC_PDRUNCFG1_PDEN_HSCMP0_DAC_MASK (0x2U) -#define PMC_PDRUNCFG1_PDEN_HSCMP0_DAC_SHIFT (1U) -/*! PDEN_HSCMP0_DAC - Controls power to High Speed Comparator0 DAC. - * 0b0..High Speed Comparator0 DAC is powered. - * 0b1..High Speed Comparator0 DAC is powered down. - */ -#define PMC_PDRUNCFG1_PDEN_HSCMP0_DAC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PDEN_HSCMP0_DAC_SHIFT)) & PMC_PDRUNCFG1_PDEN_HSCMP0_DAC_MASK) - -#define PMC_PDRUNCFG1_PDEN_HSCMP1_DAC_MASK (0x4U) -#define PMC_PDRUNCFG1_PDEN_HSCMP1_DAC_SHIFT (2U) -/*! PDEN_HSCMP1_DAC - Controls power to High Speed Comparator1 DAC. - * 0b0..High Speed Comparator1 DAC is powered. - * 0b1..High Speed Comparator1 DAC is powered down. - */ -#define PMC_PDRUNCFG1_PDEN_HSCMP1_DAC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PDEN_HSCMP1_DAC_SHIFT)) & PMC_PDRUNCFG1_PDEN_HSCMP1_DAC_MASK) - -#define PMC_PDRUNCFG1_PDEN_HSCMP2_DAC_MASK (0x8U) -#define PMC_PDRUNCFG1_PDEN_HSCMP2_DAC_SHIFT (3U) -/*! PDEN_HSCMP2_DAC - Controls power to High Speed Comparator2 DAC. - * 0b0..High Speed Comparator2 DAC is powered. - * 0b1..High Speed Comparator2 DAC is powered down. - */ -#define PMC_PDRUNCFG1_PDEN_HSCMP2_DAC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PDEN_HSCMP2_DAC_SHIFT)) & PMC_PDRUNCFG1_PDEN_HSCMP2_DAC_MASK) - -#define PMC_PDRUNCFG1_PDEN_DAC0_MASK (0x10U) -#define PMC_PDRUNCFG1_PDEN_DAC0_SHIFT (4U) -/*! PDEN_DAC0 - Controls power to DAC0. - * 0b0..DAC0 is powered. - * 0b1..DAC0 is powered down. - */ -#define PMC_PDRUNCFG1_PDEN_DAC0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PDEN_DAC0_SHIFT)) & PMC_PDRUNCFG1_PDEN_DAC0_MASK) - -#define PMC_PDRUNCFG1_PDEN_DAC1_MASK (0x20U) -#define PMC_PDRUNCFG1_PDEN_DAC1_SHIFT (5U) -/*! PDEN_DAC1 - Controls power to DAC1. - * 0b0..DAC1 is powered. - * 0b1..DAC1 is powered down. - */ -#define PMC_PDRUNCFG1_PDEN_DAC1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PDEN_DAC1_SHIFT)) & PMC_PDRUNCFG1_PDEN_DAC1_MASK) - -#define PMC_PDRUNCFG1_PDEN_DAC2_MASK (0x40U) -#define PMC_PDRUNCFG1_PDEN_DAC2_SHIFT (6U) -/*! PDEN_DAC2 - Controls power to DAC2. - * 0b0..DAC2 is powered. - * 0b1..DAC2 is powered down. - */ -#define PMC_PDRUNCFG1_PDEN_DAC2(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PDEN_DAC2_SHIFT)) & PMC_PDRUNCFG1_PDEN_DAC2_MASK) - -#define PMC_PDRUNCFG1_STOPEN_DAC0_MASK (0x80U) -#define PMC_PDRUNCFG1_STOPEN_DAC0_SHIFT (7U) -/*! STOPEN_DAC0 - Controls DAC0 Stop mode. - * 0b0..DAC0 Stop mode is disabled. - * 0b1..DAC0 Stop mode is enabled. - */ -#define PMC_PDRUNCFG1_STOPEN_DAC0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_STOPEN_DAC0_SHIFT)) & PMC_PDRUNCFG1_STOPEN_DAC0_MASK) - -#define PMC_PDRUNCFG1_STOPEN_DAC1_MASK (0x100U) -#define PMC_PDRUNCFG1_STOPEN_DAC1_SHIFT (8U) -/*! STOPEN_DAC1 - Controls DAC1 Stop mode. - * 0b0..DAC1 Stop mode is disabled. - * 0b1..DAC1 Stop mode is enabled. - */ -#define PMC_PDRUNCFG1_STOPEN_DAC1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_STOPEN_DAC1_SHIFT)) & PMC_PDRUNCFG1_STOPEN_DAC1_MASK) - -#define PMC_PDRUNCFG1_STOPEN_DAC2_MASK (0x200U) -#define PMC_PDRUNCFG1_STOPEN_DAC2_SHIFT (9U) -/*! STOPEN_DAC2 - Controls DAC2 Stop mode. - * 0b0..DAC2 Stop mode is disabled. - * 0b1..DAC2 Stop mode is enabled. - */ -#define PMC_PDRUNCFG1_STOPEN_DAC2(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_STOPEN_DAC2_SHIFT)) & PMC_PDRUNCFG1_STOPEN_DAC2_MASK) -/*! @} */ - -/*! @name PDRUNCFGSET0 - Power configuration set 0 */ -/*! @{ */ - -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU) -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U) -/*! PDRUNCFGSET0 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. - */ -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK) -/*! @} */ - -/*! @name PDRUNCFGSET1 - Power configuration set 1 */ -/*! @{ */ - -#define PMC_PDRUNCFGSET1_PDRUNCFGSET1_MASK (0x3FFU) -#define PMC_PDRUNCFGSET1_PDRUNCFGSET1_SHIFT (0U) -/*! PDRUNCFGSET1 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. - */ -#define PMC_PDRUNCFGSET1_PDRUNCFGSET1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET1_PDRUNCFGSET1_SHIFT)) & PMC_PDRUNCFGSET1_PDRUNCFGSET1_MASK) -/*! @} */ - -/*! @name PDRUNCFGCLR0 - Power configuration clear 0 */ -/*! @{ */ - -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU) -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U) -/*! PDRUNCFGCLR0 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. - */ -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK) -/*! @} */ - -/*! @name PDRUNCFGCLR1 - Power configuration clear 1 */ -/*! @{ */ - -#define PMC_PDRUNCFGCLR1_PDRUNCFGCLR1_MASK (0x3FFU) -#define PMC_PDRUNCFGCLR1_PDRUNCFGCLR1_SHIFT (0U) -/*! PDRUNCFGCLR1 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. - */ -#define PMC_PDRUNCFGCLR1_PDRUNCFGCLR1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR1_PDRUNCFGCLR1_SHIFT)) & PMC_PDRUNCFGCLR1_PDRUNCFGCLR1_MASK) -/*! @} */ - -/*! @name SRAMCTRL - All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ -/*! @{ */ - -#define PMC_SRAMCTRL_SMB_MASK (0x3U) -#define PMC_SRAMCTRL_SMB_SHIFT (0U) -/*! SMB - Source Biasing voltage. - * 0b00..Low leakage. - * 0b01..Medium leakage. - * 0b10..Highest leakage. - * 0b11..Disable. - */ -#define PMC_SRAMCTRL_SMB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_SMB_SHIFT)) & PMC_SRAMCTRL_SMB_MASK) -/*! @} */ - -/*! @name SRAMCTRL0 - RAM_X0, and RAM_00 to RAM_30 power modes controls [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] When [LS, LSDEL, DSB, DSBDEL] is: 0011 : Normal Mode 1111 : Light sleep mode 0100 : Deep-sleep mode 1100 : Shut down Mode */ -/*! @{ */ - -#define PMC_SRAMCTRL0_RAM_X0_LS_MASK (0x1U) -#define PMC_SRAMCTRL0_RAM_X0_LS_SHIFT (0U) -/*! RAM_X0_LS - RAM_X0 Light Sleep mode. - */ -#define PMC_SRAMCTRL0_RAM_X0_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_X0_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_X0_LS_MASK) - -#define PMC_SRAMCTRL0_RAM_X0_DSB_MASK (0x2U) -#define PMC_SRAMCTRL0_RAM_X0_DSB_SHIFT (1U) -/*! RAM_X0_DSB - RAM_X0 Deep sleep mode. - */ -#define PMC_SRAMCTRL0_RAM_X0_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_X0_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_X0_DSB_MASK) - -#define PMC_SRAMCTRL0_RAM_X0_DSBDEL_MASK (0x4U) -#define PMC_SRAMCTRL0_RAM_X0_DSBDEL_SHIFT (2U) -/*! RAM_X0_DSBDEL - RAM_X0 Deep sleep delayed. - */ -#define PMC_SRAMCTRL0_RAM_X0_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_X0_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_X0_DSBDEL_MASK) - -#define PMC_SRAMCTRL0_RAM_X0_LSDEL_MASK (0x8U) -#define PMC_SRAMCTRL0_RAM_X0_LSDEL_SHIFT (3U) -/*! RAM_X0_LSDEL - RAM_X0 Sleep mode disable. - */ -#define PMC_SRAMCTRL0_RAM_X0_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_X0_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_X0_LSDEL_MASK) - -#define PMC_SRAMCTRL0_RAM_00_LS_MASK (0x10U) -#define PMC_SRAMCTRL0_RAM_00_LS_SHIFT (4U) -/*! RAM_00_LS - RAM_00 Light Sleep mode. - */ -#define PMC_SRAMCTRL0_RAM_00_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_00_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_00_LS_MASK) - -#define PMC_SRAMCTRL0_RAM_00_DSB_MASK (0x20U) -#define PMC_SRAMCTRL0_RAM_00_DSB_SHIFT (5U) -/*! RAM_00_DSB - RAM_00 Deep sleep mode. - */ -#define PMC_SRAMCTRL0_RAM_00_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_00_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_00_DSB_MASK) - -#define PMC_SRAMCTRL0_RAM_00_DSBDEL_MASK (0x40U) -#define PMC_SRAMCTRL0_RAM_00_DSBDEL_SHIFT (6U) -/*! RAM_00_DSBDEL - RAM_00 Deep sleep delayed. - */ -#define PMC_SRAMCTRL0_RAM_00_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_00_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_00_DSBDEL_MASK) - -#define PMC_SRAMCTRL0_RAM_00_LSDEL_MASK (0x80U) -#define PMC_SRAMCTRL0_RAM_00_LSDEL_SHIFT (7U) -/*! RAM_00_LSDEL - RAM_00 Sleep mode disable. - */ -#define PMC_SRAMCTRL0_RAM_00_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_00_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_00_LSDEL_MASK) - -#define PMC_SRAMCTRL0_RAM_01_LS_MASK (0x100U) -#define PMC_SRAMCTRL0_RAM_01_LS_SHIFT (8U) -/*! RAM_01_LS - RAM_01 Light Sleep mode. - */ -#define PMC_SRAMCTRL0_RAM_01_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_01_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_01_LS_MASK) - -#define PMC_SRAMCTRL0_RAM_01_DSB_MASK (0x200U) -#define PMC_SRAMCTRL0_RAM_01_DSB_SHIFT (9U) -/*! RAM_01_DSB - RAM_01 Deep sleep mode. - */ -#define PMC_SRAMCTRL0_RAM_01_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_01_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_01_DSB_MASK) - -#define PMC_SRAMCTRL0_RAM_01_DSBDEL_MASK (0x400U) -#define PMC_SRAMCTRL0_RAM_01_DSBDEL_SHIFT (10U) -/*! RAM_01_DSBDEL - RAM_01 Deep sleep delayed. - */ -#define PMC_SRAMCTRL0_RAM_01_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_01_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_01_DSBDEL_MASK) - -#define PMC_SRAMCTRL0_RAM_01_LSDEL_MASK (0x800U) -#define PMC_SRAMCTRL0_RAM_01_LSDEL_SHIFT (11U) -/*! RAM_01_LSDEL - RAM_01 Sleep mode disable. - */ -#define PMC_SRAMCTRL0_RAM_01_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_01_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_01_LSDEL_MASK) - -#define PMC_SRAMCTRL0_RAM_02_LS_MASK (0x1000U) -#define PMC_SRAMCTRL0_RAM_02_LS_SHIFT (12U) -/*! RAM_02_LS - RAM_02 Light Sleep mode. - */ -#define PMC_SRAMCTRL0_RAM_02_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_02_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_02_LS_MASK) - -#define PMC_SRAMCTRL0_RAM_02_DSB_MASK (0x2000U) -#define PMC_SRAMCTRL0_RAM_02_DSB_SHIFT (13U) -/*! RAM_02_DSB - RAM_02 Deep sleep mode. - */ -#define PMC_SRAMCTRL0_RAM_02_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_02_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_02_DSB_MASK) - -#define PMC_SRAMCTRL0_RAM_02_DSBDEL_MASK (0x4000U) -#define PMC_SRAMCTRL0_RAM_02_DSBDEL_SHIFT (14U) -/*! RAM_02_DSBDEL - RAM_02 Deep sleep delayed. - */ -#define PMC_SRAMCTRL0_RAM_02_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_02_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_02_DSBDEL_MASK) - -#define PMC_SRAMCTRL0_RAM_02_LSDEL_MASK (0x8000U) -#define PMC_SRAMCTRL0_RAM_02_LSDEL_SHIFT (15U) -/*! RAM_02_LSDEL - RAM_02 Sleep mode disable. - */ -#define PMC_SRAMCTRL0_RAM_02_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_02_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_02_LSDEL_MASK) - -#define PMC_SRAMCTRL0_RAM_03_LS_MASK (0x10000U) -#define PMC_SRAMCTRL0_RAM_03_LS_SHIFT (16U) -/*! RAM_03_LS - RAM_03 Light Sleep mode. - */ -#define PMC_SRAMCTRL0_RAM_03_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_03_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_03_LS_MASK) - -#define PMC_SRAMCTRL0_RAM_03_DSB_MASK (0x20000U) -#define PMC_SRAMCTRL0_RAM_03_DSB_SHIFT (17U) -/*! RAM_03_DSB - RAM_03 Deep sleep mode. - */ -#define PMC_SRAMCTRL0_RAM_03_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_03_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_03_DSB_MASK) - -#define PMC_SRAMCTRL0_RAM_03_DSBDEL_MASK (0x40000U) -#define PMC_SRAMCTRL0_RAM_03_DSBDEL_SHIFT (18U) -/*! RAM_03_DSBDEL - RAM_03 Deep sleep delayed. - */ -#define PMC_SRAMCTRL0_RAM_03_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_03_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_03_DSBDEL_MASK) - -#define PMC_SRAMCTRL0_RAM_03_LSDEL_MASK (0x80000U) -#define PMC_SRAMCTRL0_RAM_03_LSDEL_SHIFT (19U) -/*! RAM_03_LSDEL - RAM_03 Sleep mode disable. - */ -#define PMC_SRAMCTRL0_RAM_03_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_03_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_03_LSDEL_MASK) - -#define PMC_SRAMCTRL0_RAM_10_LS_MASK (0x100000U) -#define PMC_SRAMCTRL0_RAM_10_LS_SHIFT (20U) -/*! RAM_10_LS - RAM_10 Light Sleep mode. - */ -#define PMC_SRAMCTRL0_RAM_10_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_10_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_10_LS_MASK) - -#define PMC_SRAMCTRL0_RAM_10_DSB_MASK (0x200000U) -#define PMC_SRAMCTRL0_RAM_10_DSB_SHIFT (21U) -/*! RAM_10_DSB - RAM_10 Deep sleep mode. - */ -#define PMC_SRAMCTRL0_RAM_10_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_10_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_10_DSB_MASK) - -#define PMC_SRAMCTRL0_RAM_10_DSBDEL_MASK (0x400000U) -#define PMC_SRAMCTRL0_RAM_10_DSBDEL_SHIFT (22U) -/*! RAM_10_DSBDEL - RAM_10 Deep sleep delayed. - */ -#define PMC_SRAMCTRL0_RAM_10_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_10_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_10_DSBDEL_MASK) - -#define PMC_SRAMCTRL0_RAM_10_LSDEL_MASK (0x800000U) -#define PMC_SRAMCTRL0_RAM_10_LSDEL_SHIFT (23U) -/*! RAM_10_LSDEL - RAM_10 Sleep mode disable. - */ -#define PMC_SRAMCTRL0_RAM_10_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_10_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_10_LSDEL_MASK) - -#define PMC_SRAMCTRL0_RAM_20_LS_MASK (0x1000000U) -#define PMC_SRAMCTRL0_RAM_20_LS_SHIFT (24U) -/*! RAM_20_LS - RAM_20 Light Sleep mode. - */ -#define PMC_SRAMCTRL0_RAM_20_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_20_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_20_LS_MASK) - -#define PMC_SRAMCTRL0_RAM_20_DSB_MASK (0x2000000U) -#define PMC_SRAMCTRL0_RAM_20_DSB_SHIFT (25U) -/*! RAM_20_DSB - RAM_20 Deep sleep mode. - */ -#define PMC_SRAMCTRL0_RAM_20_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_20_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_20_DSB_MASK) - -#define PMC_SRAMCTRL0_RAM_20_DSBDEL_MASK (0x4000000U) -#define PMC_SRAMCTRL0_RAM_20_DSBDEL_SHIFT (26U) -/*! RAM_20_DSBDEL - RAM_20 Deep sleep delayed. - */ -#define PMC_SRAMCTRL0_RAM_20_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_20_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_20_DSBDEL_MASK) - -#define PMC_SRAMCTRL0_RAM_20_LSDEL_MASK (0x8000000U) -#define PMC_SRAMCTRL0_RAM_20_LSDEL_SHIFT (27U) -/*! RAM_20_LSDEL - RAM_20 Sleep mode disable. - */ -#define PMC_SRAMCTRL0_RAM_20_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_20_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_20_LSDEL_MASK) - -#define PMC_SRAMCTRL0_RAM_30_LS_MASK (0x10000000U) -#define PMC_SRAMCTRL0_RAM_30_LS_SHIFT (28U) -/*! RAM_30_LS - RAM_30 Light Sleep mode. - */ -#define PMC_SRAMCTRL0_RAM_30_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_30_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_30_LS_MASK) - -#define PMC_SRAMCTRL0_RAM_30_DSB_MASK (0x20000000U) -#define PMC_SRAMCTRL0_RAM_30_DSB_SHIFT (29U) -/*! RAM_30_DSB - RAM_30 Deep sleep mode. - */ -#define PMC_SRAMCTRL0_RAM_30_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_30_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_30_DSB_MASK) - -#define PMC_SRAMCTRL0_RAM_30_DSBDEL_MASK (0x40000000U) -#define PMC_SRAMCTRL0_RAM_30_DSBDEL_SHIFT (30U) -/*! RAM_30_DSBDEL - RAM_30 Deep sleep delayed. - */ -#define PMC_SRAMCTRL0_RAM_30_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_30_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_30_DSBDEL_MASK) - -#define PMC_SRAMCTRL0_RAM_30_LSDEL_MASK (0x80000000U) -#define PMC_SRAMCTRL0_RAM_30_LSDEL_SHIFT (31U) -/*! RAM_30_LSDEL - RAM_30 Light Sleep mode delayed. - */ -#define PMC_SRAMCTRL0_RAM_30_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_30_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_30_LSDEL_MASK) -/*! @} */ - -/*! @name SRAMCTRL1 - RAM_40 to RAM_43 power modes controls [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] When [LS, LSDEL, DSB, DSBDEL] is: 0011 : Normal Mode 1111 : Light sleep mode 0100 : Deep-sleep mode 1100 : Shut down Mode */ -/*! @{ */ - -#define PMC_SRAMCTRL1_RAM_40_LS_MASK (0x1U) -#define PMC_SRAMCTRL1_RAM_40_LS_SHIFT (0U) -/*! RAM_40_LS - RAM_40 Light Sleep mode. - */ -#define PMC_SRAMCTRL1_RAM_40_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_40_LS_SHIFT)) & PMC_SRAMCTRL1_RAM_40_LS_MASK) - -#define PMC_SRAMCTRL1_RAM_40_DSB_MASK (0x2U) -#define PMC_SRAMCTRL1_RAM_40_DSB_SHIFT (1U) -/*! RAM_40_DSB - RAM_40 Deep sleep mode. - */ -#define PMC_SRAMCTRL1_RAM_40_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_40_DSB_SHIFT)) & PMC_SRAMCTRL1_RAM_40_DSB_MASK) - -#define PMC_SRAMCTRL1_RAM_40_DSBDEL_MASK (0x4U) -#define PMC_SRAMCTRL1_RAM_40_DSBDEL_SHIFT (2U) -/*! RAM_40_DSBDEL - RAM_40 Deep sleep delayed. - */ -#define PMC_SRAMCTRL1_RAM_40_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_40_DSBDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_40_DSBDEL_MASK) - -#define PMC_SRAMCTRL1_RAM_40_LSDEL_MASK (0x8U) -#define PMC_SRAMCTRL1_RAM_40_LSDEL_SHIFT (3U) -/*! RAM_40_LSDEL - RAM_40 Sleep mode disable. - */ -#define PMC_SRAMCTRL1_RAM_40_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_40_LSDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_40_LSDEL_MASK) - -#define PMC_SRAMCTRL1_RAM_41_LS_MASK (0x10U) -#define PMC_SRAMCTRL1_RAM_41_LS_SHIFT (4U) -/*! RAM_41_LS - RAM_41 Light Sleep mode. - */ -#define PMC_SRAMCTRL1_RAM_41_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_41_LS_SHIFT)) & PMC_SRAMCTRL1_RAM_41_LS_MASK) - -#define PMC_SRAMCTRL1_RAM_41_DSB_MASK (0x20U) -#define PMC_SRAMCTRL1_RAM_41_DSB_SHIFT (5U) -/*! RAM_41_DSB - RAM_41 Deep sleep mode. - */ -#define PMC_SRAMCTRL1_RAM_41_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_41_DSB_SHIFT)) & PMC_SRAMCTRL1_RAM_41_DSB_MASK) - -#define PMC_SRAMCTRL1_RAM_41_DSBDEL_MASK (0x40U) -#define PMC_SRAMCTRL1_RAM_41_DSBDEL_SHIFT (6U) -/*! RAM_41_DSBDEL - RAM_41 Deep sleep delayed. - */ -#define PMC_SRAMCTRL1_RAM_41_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_41_DSBDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_41_DSBDEL_MASK) - -#define PMC_SRAMCTRL1_RAM_41_LSDEL_MASK (0x80U) -#define PMC_SRAMCTRL1_RAM_41_LSDEL_SHIFT (7U) -/*! RAM_41_LSDEL - RAM_41 Sleep mode disable. - */ -#define PMC_SRAMCTRL1_RAM_41_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_41_LSDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_41_LSDEL_MASK) - -#define PMC_SRAMCTRL1_RAM_42_LS_MASK (0x100U) -#define PMC_SRAMCTRL1_RAM_42_LS_SHIFT (8U) -/*! RAM_42_LS - RAM_42 Light Sleep mode. - */ -#define PMC_SRAMCTRL1_RAM_42_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_42_LS_SHIFT)) & PMC_SRAMCTRL1_RAM_42_LS_MASK) - -#define PMC_SRAMCTRL1_RAM_42_DSB_MASK (0x200U) -#define PMC_SRAMCTRL1_RAM_42_DSB_SHIFT (9U) -/*! RAM_42_DSB - RAM_42 Deep sleep mode. - */ -#define PMC_SRAMCTRL1_RAM_42_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_42_DSB_SHIFT)) & PMC_SRAMCTRL1_RAM_42_DSB_MASK) - -#define PMC_SRAMCTRL1_RAM_42_DSBDEL_MASK (0x400U) -#define PMC_SRAMCTRL1_RAM_42_DSBDEL_SHIFT (10U) -/*! RAM_42_DSBDEL - RAM_42 Deep sleep delayed. - */ -#define PMC_SRAMCTRL1_RAM_42_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_42_DSBDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_42_DSBDEL_MASK) - -#define PMC_SRAMCTRL1_RAM_42_LSDEL_MASK (0x800U) -#define PMC_SRAMCTRL1_RAM_42_LSDEL_SHIFT (11U) -/*! RAM_42_LSDEL - RAM_42 Sleep mode disable. - */ -#define PMC_SRAMCTRL1_RAM_42_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_42_LSDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_42_LSDEL_MASK) - -#define PMC_SRAMCTRL1_RAM_43_LS_MASK (0x1000U) -#define PMC_SRAMCTRL1_RAM_43_LS_SHIFT (12U) -/*! RAM_43_LS - RAM_43 Light Sleep mode. - */ -#define PMC_SRAMCTRL1_RAM_43_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_43_LS_SHIFT)) & PMC_SRAMCTRL1_RAM_43_LS_MASK) - -#define PMC_SRAMCTRL1_RAM_43_DSB_MASK (0x2000U) -#define PMC_SRAMCTRL1_RAM_43_DSB_SHIFT (13U) -/*! RAM_43_DSB - RAM_43 Deep sleep mode. - */ -#define PMC_SRAMCTRL1_RAM_43_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_43_DSB_SHIFT)) & PMC_SRAMCTRL1_RAM_43_DSB_MASK) - -#define PMC_SRAMCTRL1_RAM_43_DSBDEL_MASK (0x4000U) -#define PMC_SRAMCTRL1_RAM_43_DSBDEL_SHIFT (14U) -/*! RAM_43_DSBDEL - RAM_43 Deep sleep delayed. - */ -#define PMC_SRAMCTRL1_RAM_43_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_43_DSBDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_43_DSBDEL_MASK) - -#define PMC_SRAMCTRL1_RAM_43_LSDEL_MASK (0x8000U) -#define PMC_SRAMCTRL1_RAM_43_LSDEL_SHIFT (15U) -/*! RAM_43_LSDEL - RAM_43 Sleep mode disable. - */ -#define PMC_SRAMCTRL1_RAM_43_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_43_LSDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_43_LSDEL_MASK) - -#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LS_MASK (0x10000U) -#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LS_SHIFT (16U) -/*! RAM_FLASHLPCACHE_LS - Flash Cache RAM Light Sleep mode. - */ -#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LS_SHIFT)) & PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LS_MASK) - -#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSB_MASK (0x20000U) -#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSB_SHIFT (17U) -/*! RAM_FLASHLPCACHE_DSB - Flash Cache RAM Deep sleep mode. - */ -#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSB_SHIFT)) & PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSB_MASK) - -#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSBDEL_MASK (0x40000U) -#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSBDEL_SHIFT (18U) -/*! RAM_FLASHLPCACHE_DSBDEL - Flash Cache RAM Deep sleep delayed. - */ -#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSBDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSBDEL_MASK) - -#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LSDEL_MASK (0x80000U) -#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LSDEL_SHIFT (19U) -/*! RAM_FLASHLPCACHE_LSDEL - Flash Cache RAM Sleep mode disable. - */ -#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LSDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LSDEL_MASK) - -#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LS_MASK (0x100000U) -#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LS_SHIFT (20U) -/*! RAM_FLEXSPILPCACHE_LS - Flex SPI Cache RAM Light Sleep mode. - */ -#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LS_SHIFT)) & PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LS_MASK) - -#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSB_MASK (0x200000U) -#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSB_SHIFT (21U) -/*! RAM_FLEXSPILPCACHE_DSB - Flex SPI Cache RAM Deep sleep mode. - */ -#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSB_SHIFT)) & PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSB_MASK) - -#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSBDEL_MASK (0x400000U) -#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSBDEL_SHIFT (22U) -/*! RAM_FLEXSPILPCACHE_DSBDEL - Flex SPI Cache RAM Deep sleep delayed. - */ -#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSBDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSBDEL_MASK) - -#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LSDEL_MASK (0x800000U) -#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LSDEL_SHIFT (23U) -/*! RAM_FLEXSPILPCACHE_LSDEL - Flex SPI Cache RAM Sleep mode disable. - */ -#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LSDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LSDEL_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PMC_Register_Masks */ - - -/* PMC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PMC base address */ - #define PMC_BASE (0x50020000u) - /** Peripheral PMC base address */ - #define PMC_BASE_NS (0x40020000u) - /** Peripheral PMC base pointer */ - #define PMC ((PMC_Type *)PMC_BASE) - /** Peripheral PMC base pointer */ - #define PMC_NS ((PMC_Type *)PMC_BASE_NS) - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS { PMC_BASE } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS { PMC } - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS_NS { PMC_BASE_NS } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS_NS { PMC_NS } -#else - /** Peripheral PMC base address */ - #define PMC_BASE (0x40020000u) - /** Peripheral PMC base pointer */ - #define PMC ((PMC_Type *)PMC_BASE) - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS { PMC_BASE } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS { PMC } -#endif - -/*! - * @} - */ /* end of group PMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- POWERQUAD Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup POWERQUAD_Peripheral_Access_Layer POWERQUAD Peripheral Access Layer - * @{ - */ - -/** POWERQUAD - Register Layout Typedef */ -typedef struct { - __IO uint32_t OUTBASE; /**< Output Base, offset: 0x0 */ - __IO uint32_t OUTFORMAT; /**< Output Format, offset: 0x4 */ - __IO uint32_t TMPBASE; /**< Temporary Base, offset: 0x8 */ - __IO uint32_t TMPFORMAT; /**< Temporary Format, offset: 0xC */ - __IO uint32_t INABASE; /**< Input A Base, offset: 0x10 */ - __IO uint32_t INAFORMAT; /**< Input A Format, offset: 0x14 */ - __IO uint32_t INBBASE; /**< Input B Base, offset: 0x18 */ - __IO uint32_t INBFORMAT; /**< Input B Format, offset: 0x1C */ - uint8_t RESERVED_0[224]; - __IO uint32_t CONTROL; /**< Control, offset: 0x100 */ - __IO uint32_t LENGTH; /**< Length, offset: 0x104 */ - __IO uint32_t CPPRE; /**< Coprocessor Pre-scale, offset: 0x108 */ - __IO uint32_t MISC; /**< Miscellaneous, offset: 0x10C */ - __IO uint32_t CURSORY; /**< Cursory, offset: 0x110 */ - uint8_t RESERVED_1[108]; - __IO uint32_t CORDIC_X; /**< Cordic input X, offset: 0x180 */ - __IO uint32_t CORDIC_Y; /**< Cordic Input Y, offset: 0x184 */ - __IO uint32_t CORDIC_Z; /**< Cordic Input Z, offset: 0x188 */ - __IO uint32_t ERRSTAT; /**< Error Status, offset: 0x18C */ - __IO uint32_t INTREN; /**< Interrupt Enable, offset: 0x190 */ - __IO uint32_t EVENTEN; /**< Event Enable, offset: 0x194 */ - __IO uint32_t INTRSTAT; /**< Interrupt Status, offset: 0x198 */ - uint8_t RESERVED_2[100]; - __IO uint32_t GPREG[16]; /**< General Purpose Register Bank n, array offset: 0x200, array step: 0x4 */ - __IO uint32_t COMPREG[8]; /**< Compute Register Bank n, array offset: 0x240, array step: 0x4 */ -} POWERQUAD_Type; - -/* ---------------------------------------------------------------------------- - -- POWERQUAD Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup POWERQUAD_Register_Masks POWERQUAD Register Masks - * @{ - */ - -/*! @name OUTBASE - Output Base */ -/*! @{ */ - -#define POWERQUAD_OUTBASE_OUTBASE_MASK (0xFFFFFFFFU) -#define POWERQUAD_OUTBASE_OUTBASE_SHIFT (0U) -/*! OUTBASE - Base address register for the output region - */ -#define POWERQUAD_OUTBASE_OUTBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK) -/*! @} */ - -/*! @name OUTFORMAT - Output Format */ -/*! @{ */ - -#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK (0x3U) -#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT (0U) -/*! OUT_FORMATINT - Output Internal Format - */ -#define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK) - -#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK (0x30U) -#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT (4U) -/*! OUT_FORMATEXT - Output External Format - */ -#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK) - -#define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK (0xFF00U) -#define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT (8U) -/*! OUT_SCALER - Output Scaler Value - */ -#define POWERQUAD_OUTFORMAT_OUT_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK) -/*! @} */ - -/*! @name TMPBASE - Temporary Base */ -/*! @{ */ - -#define POWERQUAD_TMPBASE_TMPBASE_MASK (0xFFFFFFFFU) -#define POWERQUAD_TMPBASE_TMPBASE_SHIFT (0U) -/*! TMPBASE - Base address register for the temporary region - */ -#define POWERQUAD_TMPBASE_TMPBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK) -/*! @} */ - -/*! @name TMPFORMAT - Temporary Format */ -/*! @{ */ - -#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK (0x3U) -#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT (0U) -/*! TMP_FORMATINT - Temporary Internal Format - */ -#define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK) - -#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK (0x30U) -#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT (4U) -/*! TMP_FORMATEXT - Temporary External Format - */ -#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK) - -#define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK (0xFF00U) -#define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT (8U) -/*! TMP_SCALER - Temporary Scaler Value - */ -#define POWERQUAD_TMPFORMAT_TMP_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK) -/*! @} */ - -/*! @name INABASE - Input A Base */ -/*! @{ */ - -#define POWERQUAD_INABASE_INABASE_MASK (0xFFFFFFFFU) -#define POWERQUAD_INABASE_INABASE_SHIFT (0U) -/*! INABASE - Input A Base - */ -#define POWERQUAD_INABASE_INABASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK) -/*! @} */ - -/*! @name INAFORMAT - Input A Format */ -/*! @{ */ - -#define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK (0x3U) -#define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT (0U) -/*! INA_FORMATINT - Input A Internal Format - */ -#define POWERQUAD_INAFORMAT_INA_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK) - -#define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK (0x30U) -#define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT (4U) -/*! INA_FORMATEXT - Input A External Format - */ -#define POWERQUAD_INAFORMAT_INA_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK) - -#define POWERQUAD_INAFORMAT_INA_SCALER_MASK (0xFF00U) -#define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT (8U) -/*! INA_SCALER - Input A Scaler Value - */ -#define POWERQUAD_INAFORMAT_INA_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK) -/*! @} */ - -/*! @name INBBASE - Input B Base */ -/*! @{ */ - -#define POWERQUAD_INBBASE_INBBASE_MASK (0xFFFFFFFFU) -#define POWERQUAD_INBBASE_INBBASE_SHIFT (0U) -/*! INBBASE - Input B Base - */ -#define POWERQUAD_INBBASE_INBBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK) -/*! @} */ - -/*! @name INBFORMAT - Input B Format */ -/*! @{ */ - -#define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK (0x3U) -#define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT (0U) -/*! INB_FORMATINT - Input B Internal Format - */ -#define POWERQUAD_INBFORMAT_INB_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK) - -#define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK (0x30U) -#define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT (4U) -/*! INB_FORMATEXT - Input B External Format - */ -#define POWERQUAD_INBFORMAT_INB_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK) - -#define POWERQUAD_INBFORMAT_INB_SCALER_MASK (0xFF00U) -#define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT (8U) -/*! INB_SCALER - Input B Scaler Value - */ -#define POWERQUAD_INBFORMAT_INB_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK) -/*! @} */ - -/*! @name CONTROL - Control */ -/*! @{ */ - -#define POWERQUAD_CONTROL_DECODE_OPCODE_MASK (0xFU) -#define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT (0U) -/*! DECODE_OPCODE - Decode Opcode - */ -#define POWERQUAD_CONTROL_DECODE_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK) - -#define POWERQUAD_CONTROL_DECODE_MACHINE_MASK (0xF0U) -#define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT (4U) -/*! DECODE_MACHINE - Decode Machine - */ -#define POWERQUAD_CONTROL_DECODE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK) - -#define POWERQUAD_CONTROL_INST_BUSY_MASK (0x80000000U) -#define POWERQUAD_CONTROL_INST_BUSY_SHIFT (31U) -/*! INST_BUSY - Instruction Busy - */ -#define POWERQUAD_CONTROL_INST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK) -/*! @} */ - -/*! @name LENGTH - Length */ -/*! @{ */ - -#define POWERQUAD_LENGTH_INST_LENGTH_MASK (0xFFFFFFFFU) -#define POWERQUAD_LENGTH_INST_LENGTH_SHIFT (0U) -/*! INST_LENGTH - Instruction Length - */ -#define POWERQUAD_LENGTH_INST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK) -/*! @} */ - -/*! @name CPPRE - Coprocessor Pre-scale */ -/*! @{ */ - -#define POWERQUAD_CPPRE_CPPRE_IN_MASK (0xFFU) -#define POWERQUAD_CPPRE_CPPRE_IN_SHIFT (0U) -/*! CPPRE_IN - Input - */ -#define POWERQUAD_CPPRE_CPPRE_IN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK) - -#define POWERQUAD_CPPRE_CPPRE_OUT_MASK (0xFF00U) -#define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT (8U) -/*! CPPRE_OUT - Output - */ -#define POWERQUAD_CPPRE_CPPRE_OUT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK) - -#define POWERQUAD_CPPRE_CPPRE_SAT_MASK (0x10000U) -#define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT (16U) -/*! CPPRE_SAT - Saturation - * 0b0..No saturation - * 0b1..Forces sub-32 bit saturation - */ -#define POWERQUAD_CPPRE_CPPRE_SAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK) - -#define POWERQUAD_CPPRE_CPPRE_SAT8_MASK (0x20000U) -#define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT (17U) -/*! CPPRE_SAT8 - Saturation 8 - * 0b0..8 bits - * 0b1..16 bits - */ -#define POWERQUAD_CPPRE_CPPRE_SAT8(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK) -/*! @} */ - -/*! @name MISC - Miscellaneous */ -/*! @{ */ - -#define POWERQUAD_MISC_INST_MISC_MASK (0xFFFFFFFFU) -#define POWERQUAD_MISC_INST_MISC_SHIFT (0U) -/*! INST_MISC - For Matrix : Used for scaling factor - */ -#define POWERQUAD_MISC_INST_MISC(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK) -/*! @} */ - -/*! @name CURSORY - Cursory */ -/*! @{ */ - -#define POWERQUAD_CURSORY_CURSORY_MASK (0x1U) -#define POWERQUAD_CURSORY_CURSORY_SHIFT (0U) -/*! CURSORY - Cursory Mode - * 0b0..Disable Cursory mode - * 0b1..Enable Cursory Mode - */ -#define POWERQUAD_CURSORY_CURSORY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK) -/*! @} */ - -/*! @name CORDIC_X - Cordic input X */ -/*! @{ */ - -#define POWERQUAD_CORDIC_X_CORDIC_X_MASK (0xFFFFFFFFU) -#define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT (0U) -/*! CORDIC_X - Cordic Input x - */ -#define POWERQUAD_CORDIC_X_CORDIC_X(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK) -/*! @} */ - -/*! @name CORDIC_Y - Cordic Input Y */ -/*! @{ */ - -#define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK (0xFFFFFFFFU) -#define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT (0U) -/*! CORDIC_Y - Cordic Input y - */ -#define POWERQUAD_CORDIC_Y_CORDIC_Y(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK) -/*! @} */ - -/*! @name CORDIC_Z - Cordic Input Z */ -/*! @{ */ - -#define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK (0xFFFFFFFFU) -#define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT (0U) -/*! CORDIC_Z - Cordic Input z - */ -#define POWERQUAD_CORDIC_Z_CORDIC_Z(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK) -/*! @} */ - -/*! @name ERRSTAT - Error Status */ -/*! @{ */ - -#define POWERQUAD_ERRSTAT_OVERFLOW_MASK (0x1U) -#define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT (0U) -/*! OVERFLOW - Floating Point Overflow - * 0b0..No Error - * 0b1..Error on Floating Point Overflow - */ -#define POWERQUAD_ERRSTAT_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK) - -#define POWERQUAD_ERRSTAT_NAN_MASK (0x2U) -#define POWERQUAD_ERRSTAT_NAN_SHIFT (1U) -/*! NAN - Floating Point NaN - * 0b0..No Error - * 0b1..Error on Floating Point NaN - */ -#define POWERQUAD_ERRSTAT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK) - -#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK (0x4U) -#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT (2U) -/*! FIXEDOVERFLOW - Fixed Point Overflow - * 0b0..No Error - * 0b1..Error on Fixed Point Overflow - */ -#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK) - -#define POWERQUAD_ERRSTAT_UNDERFLOW_MASK (0x8U) -#define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT (3U) -/*! UNDERFLOW - Underflow - * 0b0..No Error - * 0b1..Error on Underflow - */ -#define POWERQUAD_ERRSTAT_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK) - -#define POWERQUAD_ERRSTAT_BUSERROR_MASK (0x10U) -#define POWERQUAD_ERRSTAT_BUSERROR_SHIFT (4U) -/*! BUSERROR - Bus Error - * 0b0..No Error - * 0b1..Error on Bus - */ -#define POWERQUAD_ERRSTAT_BUSERROR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK) -/*! @} */ - -/*! @name INTREN - Interrupt Enable */ -/*! @{ */ - -#define POWERQUAD_INTREN_INTR_OFLOW_MASK (0x1U) -#define POWERQUAD_INTREN_INTR_OFLOW_SHIFT (0U) -/*! INTR_OFLOW - Interrupt Floating Point Overflow - * 0b0..Disable - * 0b1..Enable interrupt on floating point overflow - */ -#define POWERQUAD_INTREN_INTR_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK) - -#define POWERQUAD_INTREN_INTR_NAN_MASK (0x2U) -#define POWERQUAD_INTREN_INTR_NAN_SHIFT (1U) -/*! INTR_NAN - Interrupt Floating Point NaN - * 0b0..Disable - * 0b1..Enable interrupt on floating point NaN - */ -#define POWERQUAD_INTREN_INTR_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK) - -#define POWERQUAD_INTREN_INTR_FIXED_MASK (0x4U) -#define POWERQUAD_INTREN_INTR_FIXED_SHIFT (2U) -/*! INTR_FIXED - Interrupt on Fixed Point Overflow - * 0b0..Disable - * 0b1..Enable interrupt on fixed point overflow - */ -#define POWERQUAD_INTREN_INTR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK) - -#define POWERQUAD_INTREN_INTR_UFLOW_MASK (0x8U) -#define POWERQUAD_INTREN_INTR_UFLOW_SHIFT (3U) -/*! INTR_UFLOW - Interrupt on Subnormal Truncation - * 0b0..Disable - * 0b1..Enable interrupt on subnormal truncation - */ -#define POWERQUAD_INTREN_INTR_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK) - -#define POWERQUAD_INTREN_INTR_BERR_MASK (0x10U) -#define POWERQUAD_INTREN_INTR_BERR_SHIFT (4U) -/*! INTR_BERR - Interrupt on AHBM Bus Error - * 0b0..Disable - * 0b1..Enable interrupt on AHBM Bus Error - */ -#define POWERQUAD_INTREN_INTR_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK) - -#define POWERQUAD_INTREN_INTR_COMP_MASK (0x80U) -#define POWERQUAD_INTREN_INTR_COMP_SHIFT (7U) -/*! INTR_COMP - Interrupt on Instruction Completion - * 0b0..Disable - * 0b1..Enable interrupt on instruction completion - */ -#define POWERQUAD_INTREN_INTR_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK) -/*! @} */ - -/*! @name EVENTEN - Event Enable */ -/*! @{ */ - -#define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK (0x1U) -#define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT (0U) -/*! EVENT_OFLOW - Event Trigger on Floating Point Overflow - * 0b0..Disable - * 0b1..Enable event trigger on Floating point overflow - */ -#define POWERQUAD_EVENTEN_EVENT_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK) - -#define POWERQUAD_EVENTEN_EVENT_NAN_MASK (0x2U) -#define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT (1U) -/*! EVENT_NAN - Event Trigger on Floating Point NaN - * 0b0..Disable - * 0b1..Enable event trigger on floating point NaN - */ -#define POWERQUAD_EVENTEN_EVENT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK) - -#define POWERQUAD_EVENTEN_EVENT_FIXED_MASK (0x4U) -#define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT (2U) -/*! EVENT_FIXED - Event Trigger on Fixed Point Overflow - * 0b0..Disable - * 0b1..Enable event trigger on fixed point overflow - */ -#define POWERQUAD_EVENTEN_EVENT_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK) - -#define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK (0x8U) -#define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT (3U) -/*! EVENT_UFLOW - Event Trigger on Subnormal Truncation - * 0b0..Disable - * 0b1..Enable event trigger on subnormal truncation - */ -#define POWERQUAD_EVENTEN_EVENT_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK) - -#define POWERQUAD_EVENTEN_EVENT_BERR_MASK (0x10U) -#define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT (4U) -/*! EVENT_BERR - Event Trigger on AHBM Bus Error - * 0b0..Disable - * 0b1..Enable event trigger on AHBM bus error - */ -#define POWERQUAD_EVENTEN_EVENT_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK) - -#define POWERQUAD_EVENTEN_EVENT_COMP_MASK (0x80U) -#define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT (7U) -/*! EVENT_COMP - Event Trigger on Instruction Completion - * 0b0..Disable - * 0b1..Enable event trigger on instruction completion - */ -#define POWERQUAD_EVENTEN_EVENT_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK) -/*! @} */ - -/*! @name INTRSTAT - Interrupt Status */ -/*! @{ */ - -#define POWERQUAD_INTRSTAT_INTR_STAT_MASK (0x1U) -#define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT (0U) -/*! INTR_STAT - Interrupt Status - * 0b0..No new interrupt - * 0b1..Interrupt captured - */ -#define POWERQUAD_INTRSTAT_INTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK) -/*! @} */ - -/*! @name GPREG - General Purpose Register Bank n */ -/*! @{ */ - -#define POWERQUAD_GPREG_GPREG_MASK (0xFFFFFFFFU) -#define POWERQUAD_GPREG_GPREG_SHIFT (0U) -/*! GPREG - General Purpose Register Bank - */ -#define POWERQUAD_GPREG_GPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK) -/*! @} */ - -/* The count of POWERQUAD_GPREG */ -#define POWERQUAD_GPREG_COUNT (16U) - -/*! @name COMPREGS_COMPREG - Compute Register Bank n */ -/*! @{ */ - -#define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK (0xFFFFFFFFU) -#define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U) -/*! COMPREG - Compute Register Bank - */ -#define POWERQUAD_COMPREGS_COMPREG_COMPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK) -/*! @} */ - -/* The count of POWERQUAD_COMPREGS_COMPREG */ -#define POWERQUAD_COMPREGS_COMPREG_COUNT (8U) - - -/*! - * @} - */ /* end of group POWERQUAD_Register_Masks */ - - -/* POWERQUAD - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral POWERQUAD base address */ - #define POWERQUAD_BASE (0x500A6000u) - /** Peripheral POWERQUAD base address */ - #define POWERQUAD_BASE_NS (0x400A6000u) - /** Peripheral POWERQUAD base pointer */ - #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) - /** Peripheral POWERQUAD base pointer */ - #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) - /** Array initializer of POWERQUAD peripheral base addresses */ - #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } - /** Array initializer of POWERQUAD peripheral base pointers */ - #define POWERQUAD_BASE_PTRS { POWERQUAD } - /** Array initializer of POWERQUAD peripheral base addresses */ - #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } - /** Array initializer of POWERQUAD peripheral base pointers */ - #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } -#else - /** Peripheral POWERQUAD base address */ - #define POWERQUAD_BASE (0x400A6000u) - /** Peripheral POWERQUAD base pointer */ - #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) - /** Array initializer of POWERQUAD peripheral base addresses */ - #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } - /** Array initializer of POWERQUAD peripheral base pointers */ - #define POWERQUAD_BASE_PTRS { POWERQUAD } -#endif -/** Interrupt vectors for the POWERQUAD peripheral type */ -#define POWERQUAD_IRQS { POWERQUAD_IRQn } - -/*! - * @} - */ /* end of group POWERQUAD_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PRINCE Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PRINCE_Peripheral_Access_Layer PRINCE Peripheral Access Layer - * @{ - */ - -/** PRINCE - Register Layout Typedef */ -typedef struct { - __IO uint32_t ENC_ENABLE; /**< Encryption Enable register, offset: 0x0 */ - __O uint32_t MASK_LSB; /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */ - __O uint32_t MASK_MSB; /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */ - __IO uint32_t LOCK; /**< Lock register, offset: 0xC */ - __O uint32_t IV_LSB0; /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */ - __O uint32_t IV_MSB0; /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */ - __IO uint32_t BASE_ADDR0; /**< Base Address for region 0 register, offset: 0x18 */ - __IO uint32_t SR_ENABLE0; /**< Sub-Region Enable register for region 0, offset: 0x1C */ - __O uint32_t IV_LSB1; /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */ - __O uint32_t IV_MSB1; /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */ - __IO uint32_t BASE_ADDR1; /**< Base Address for region 1 register, offset: 0x28 */ - __IO uint32_t SR_ENABLE1; /**< Sub-Region Enable register for region 1, offset: 0x2C */ - __O uint32_t IV_LSB2; /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */ - __O uint32_t IV_MSB2; /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */ - __IO uint32_t BASE_ADDR2; /**< Base Address for region 2 register, offset: 0x38 */ - __IO uint32_t SR_ENABLE2; /**< Sub-Region Enable register for region 2, offset: 0x3C */ - uint8_t RESERVED_0[80]; - __IO uint32_t ERR; /**< Error status register, offset: 0x90 */ - uint8_t RESERVED_1[108]; - __IO uint32_t SR_XOM[3]; /**< XOM enable for sub region 0..XOM enable for sub region 2, array offset: 0x100, array step: 0x4 */ -} PRINCE_Type; - -/* ---------------------------------------------------------------------------- - -- PRINCE Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PRINCE_Register_Masks PRINCE Register Masks - * @{ - */ - -/*! @name ENC_ENABLE - Encryption Enable register */ -/*! @{ */ - -#define PRINCE_ENC_ENABLE_EN_MASK (0x1U) -#define PRINCE_ENC_ENABLE_EN_SHIFT (0U) -/*! EN - Enables PRINCE encryption for flash programming. - * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled. - * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled. Reading of PRINCE-encrypted flash regions is disabled. - */ -#define PRINCE_ENC_ENABLE_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK) -/*! @} */ - -/*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */ -/*! @{ */ - -#define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU) -#define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U) -/*! MASKVAL - Value of the 32 Least Significant Bits of the 64-bit data mask. - */ -#define PRINCE_MASK_LSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK) -/*! @} */ - -/*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */ -/*! @{ */ - -#define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU) -#define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U) -/*! MASKVAL - Value of the 32 Most Significant Bits of the 64-bit data mask. - */ -#define PRINCE_MASK_MSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK) -/*! @} */ - -/*! @name LOCK - Lock register */ -/*! @{ */ - -#define PRINCE_LOCK_LOCKREG0_MASK (0x1U) -#define PRINCE_LOCK_LOCKREG0_SHIFT (0U) -/*! LOCKREG0 - Lock Region 0 registers. - * 0b0..Disabled. IV_LSB0, IV_MSB0, and SR_ENABLE0 are writable. - * 0b1..Enabled. IV_LSB0, IV_MSB0, and SR_ENABLE0 are not writable. - */ -#define PRINCE_LOCK_LOCKREG0(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK) - -#define PRINCE_LOCK_LOCKREG1_MASK (0x2U) -#define PRINCE_LOCK_LOCKREG1_SHIFT (1U) -/*! LOCKREG1 - Lock Region 1 registers. - * 0b0..Disabled. IV_LSB1, IV_MSB1, and SR_ENABLE1 are writable. - * 0b1..Enabled. IV_LSB1, IV_MSB1, and SR_ENABLE1 are not writable. - */ -#define PRINCE_LOCK_LOCKREG1(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK) - -#define PRINCE_LOCK_LOCKREG2_MASK (0x4U) -#define PRINCE_LOCK_LOCKREG2_SHIFT (2U) -/*! LOCKREG2 - Lock Region 2 registers. - * 0b0..Disabled. IV_LSB2, IV_MSB2, and SR_ENABLE2 are writable. - * 0b1..Enabled. IV_LSB2, IV_MSB2, and SR_ENABLE2 are not writable. - */ -#define PRINCE_LOCK_LOCKREG2(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK) - -#define PRINCE_LOCK_LOCKMASK_MASK (0x100U) -#define PRINCE_LOCK_LOCKMASK_SHIFT (8U) -/*! LOCKMASK - Lock the Mask registers. - * 0b0..Disabled. MASK_LSB, and MASK_MSB are writable. - * 0b1..Enabled. MASK_LSB, and MASK_MSB are not writable. - */ -#define PRINCE_LOCK_LOCKMASK(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK) -/*! @} */ - -/*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB0_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_LSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB0_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_MSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR0 - Base Address for region 0 register */ -/*! @{ */ - -#define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U) -/*! ADDR_FIXED - Fixed portion of the base address of region 0. - */ -#define PRINCE_BASE_ADDR0_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK) - -#define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U) -/*! ADDR_PRG - Programmable portion of the base address of region 0. - */ -#define PRINCE_BASE_ADDR0_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */ -/*! @{ */ - -#define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE0_EN_SHIFT (0U) -/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0. - * 0b00000000000000000000000000000000..Encryption disabled for the corresponding sub-region. - * 0b00000000000000000000000000000001..Encryption enabled for the corresponding sub-region. - */ -#define PRINCE_SR_ENABLE0_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK) -/*! @} */ - -/*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB1_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_LSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB1_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_MSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR1 - Base Address for region 1 register */ -/*! @{ */ - -#define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U) -/*! ADDR_FIXED - Fixed portion of the base address of region 1. - */ -#define PRINCE_BASE_ADDR1_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK) - -#define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U) -/*! ADDR_PRG - Programmable portion of the base address of region 1. - */ -#define PRINCE_BASE_ADDR1_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */ -/*! @{ */ - -#define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE1_EN_SHIFT (0U) -/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1. - * 0b00000000000000000000000000000000..Encryption disabled for the corresponding sub-region. - * 0b00000000000000000000000000000001..Encryption enabled for the corresponding sub-region. - */ -#define PRINCE_SR_ENABLE1_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK) -/*! @} */ - -/*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB2_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_LSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB2_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_MSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR2 - Base Address for region 2 register */ -/*! @{ */ - -#define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U) -/*! ADDR_FIXED - Fixed portion of the base address of region 2. - */ -#define PRINCE_BASE_ADDR2_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK) - -#define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U) -/*! ADDR_PRG - Programmable portion of the base address of region 2. - */ -#define PRINCE_BASE_ADDR2_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */ -/*! @{ */ - -#define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE2_EN_SHIFT (0U) -/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2. - * 0b00000000000000000000000000000000..Encryption disabled for the corresponding sub-region. - * 0b00000000000000000000000000000001..Encryption enabled for the corresponding sub-region. - */ -#define PRINCE_SR_ENABLE2_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK) -/*! @} */ - -/*! @name ERR - Error status register */ -/*! @{ */ - -#define PRINCE_ERR_ERRSTAT_MASK (0x1U) -#define PRINCE_ERR_ERRSTAT_SHIFT (0U) -/*! ERRSTAT - PRINCE Error Status. This bit is write-1 to clear. - * 0b0..No PRINCE error. - * 0b1..Error. A read of a PRINCE-encrypted region was attempted while ENC_ENABLE[EN]=1. - */ -#define PRINCE_ERR_ERRSTAT(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ERR_ERRSTAT_SHIFT)) & PRINCE_ERR_ERRSTAT_MASK) -/*! @} */ - -/*! @name SR_XOMX_SR_XOM - XOM enable for sub region 0..XOM enable for sub region 2 */ -/*! @{ */ - -#define PRINCE_SR_XOMX_SR_XOM_XOM_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_XOMX_SR_XOM_XOM_EN_SHIFT (0U) -/*! XOM_EN - XOM enable - * 0b00000000000000000000000000000000..A 0 in bit n means that decryption of data associated with sub-region n is done for both data and code read transactions. - * 0b00000000000000000000000000000001..A 1 in bit n means that decryption of data associated with sub-region n is done for code fetch transactions only. - */ -#define PRINCE_SR_XOMX_SR_XOM_XOM_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_XOMX_SR_XOM_XOM_EN_SHIFT)) & PRINCE_SR_XOMX_SR_XOM_XOM_EN_MASK) -/*! @} */ - -/* The count of PRINCE_SR_XOMX_SR_XOM */ -#define PRINCE_SR_XOMX_SR_XOM_COUNT (3U) - - -/*! - * @} - */ /* end of group PRINCE_Register_Masks */ - - -/* PRINCE - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PRINCE0 base address */ - #define PRINCE0_BASE (0x50035000u) - /** Peripheral PRINCE0 base address */ - #define PRINCE0_BASE_NS (0x40035000u) - /** Peripheral PRINCE0 base pointer */ - #define PRINCE0 ((PRINCE_Type *)PRINCE0_BASE) - /** Peripheral PRINCE0 base pointer */ - #define PRINCE0_NS ((PRINCE_Type *)PRINCE0_BASE_NS) - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS { PRINCE0_BASE } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS { PRINCE0 } - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS_NS { PRINCE0_BASE_NS } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS_NS { PRINCE0_NS } -#else - /** Peripheral PRINCE0 base address */ - #define PRINCE0_BASE (0x40035000u) - /** Peripheral PRINCE0 base pointer */ - #define PRINCE0 ((PRINCE_Type *)PRINCE0_BASE) - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS { PRINCE0_BASE } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS { PRINCE0 } -#endif - -/*! - * @} - */ /* end of group PRINCE_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PUF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer - * @{ - */ - -/** PUF - Register Layout Typedef */ -typedef struct { - __IO uint32_t CR; /**< Control, offset: 0x0 */ - __I uint32_t ORR; /**< Operation Result, offset: 0x4 */ - __IO uint32_t SR; /**< Status, offset: 0x8 */ - __I uint32_t AR; /**< Allow, offset: 0xC */ - __IO uint32_t IER; /**< Interrupt Enable, offset: 0x10 */ - __IO uint32_t IMR; /**< Interrupt Mask, offset: 0x14 */ - __IO uint32_t ISR; /**< Interrupt Status, offset: 0x18 */ - uint8_t RESERVED_0[4]; - __IO uint32_t KEY_DEST; /**< Key Destination, offset: 0x20 */ - uint8_t RESERVED_1[124]; - __O uint32_t DIR; /**< Data Input, offset: 0xA0 */ - uint8_t RESERVED_2[4]; - __I uint32_t DOR; /**< Data Output, offset: 0xA8 */ - uint8_t RESERVED_3[20]; - __IO uint32_t MISC; /**< Miscellaneous, offset: 0xC0 */ - uint8_t RESERVED_4[12]; - __IO uint32_t IF_SR; /**< Interface Status, offset: 0xD0 */ - uint8_t RESERVED_5[8]; - __I uint32_t PSR; /**< PUF Score, offset: 0xDC */ - __I uint32_t HW_RUC0; /**< Hardware Restrict User Context 0, offset: 0xE0 */ - __I uint32_t HW_RUC1; /**< Hardware Restrict User Context 1, offset: 0xE4 */ - uint8_t RESERVED_6[12]; - __I uint32_t HW_INFO; /**< Hardware Information, offset: 0xF4 */ - __I uint32_t HW_ID; /**< Hardware Identifier, offset: 0xF8 */ - __I uint32_t HW_VER; /**< Hardware Version, offset: 0xFC */ - __IO uint32_t CONFIG; /**< PUF command blocking configuration, offset: 0x100 */ - __IO uint32_t SEC_LOCK; /**< Lock the security level of PUF block until key generate, wrap or unwrap operation is completed., offset: 0x104 */ - __IO uint32_t APP_CTX_MASK; /**< Application defined context mask, offset: 0x108 */ - uint8_t RESERVED_7[500]; - __IO uint32_t SRAM_CFG; /**< SRAM Configuration, offset: 0x300 */ - __I uint32_t SRAM_STATUS; /**< Status, offset: 0x304 */ - uint8_t RESERVED_8[208]; - __O uint32_t SRAM_INT_CLR_ENABLE; /**< Interrupt Enable Clear, offset: 0x3D8 */ - __O uint32_t SRAM_INT_SET_ENABLE; /**< Interrupt Enable Set, offset: 0x3DC */ - __I uint32_t SRAM_INT_STATUS; /**< Interrupt Status, offset: 0x3E0 */ - __I uint32_t SRAM_INT_ENABLE; /**< Interrupt Enable, offset: 0x3E4 */ - __O uint32_t SRAM_INT_CLR_STATUS; /**< Interrupt Status Clear, offset: 0x3E8 */ - __O uint32_t SRAM_INT_SET_STATUS; /**< Interrupt Status set, offset: 0x3EC */ -} PUF_Type; - -/* ---------------------------------------------------------------------------- - -- PUF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_Register_Masks PUF Register Masks - * @{ - */ - -/*! @name CR - Control */ -/*! @{ */ - -#define PUF_CR_ZEROIZE_MASK (0x1U) -#define PUF_CR_ZEROIZE_SHIFT (0U) -/*! ZEROIZE - Begin Zeroize operation - */ -#define PUF_CR_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_ZEROIZE_SHIFT)) & PUF_CR_ZEROIZE_MASK) - -#define PUF_CR_ENROLL_MASK (0x2U) -#define PUF_CR_ENROLL_SHIFT (1U) -/*! ENROLL - Begin Enroll operation - */ -#define PUF_CR_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_ENROLL_SHIFT)) & PUF_CR_ENROLL_MASK) - -#define PUF_CR_START_MASK (0x4U) -#define PUF_CR_START_SHIFT (2U) -/*! START - Begin Start operation - */ -#define PUF_CR_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_START_SHIFT)) & PUF_CR_START_MASK) - -#define PUF_CR_STOP_MASK (0x20U) -#define PUF_CR_STOP_SHIFT (5U) -/*! STOP - Begin Stop operation - */ -#define PUF_CR_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_STOP_SHIFT)) & PUF_CR_STOP_MASK) - -#define PUF_CR_GET_KEY_MASK (0x40U) -#define PUF_CR_GET_KEY_SHIFT (6U) -/*! GET_KEY - Begin Get Key operation - */ -#define PUF_CR_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_GET_KEY_SHIFT)) & PUF_CR_GET_KEY_MASK) - -#define PUF_CR_UNWRAP_MASK (0x80U) -#define PUF_CR_UNWRAP_SHIFT (7U) -/*! UNWRAP - Begin Unwrap operation - */ -#define PUF_CR_UNWRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_UNWRAP_SHIFT)) & PUF_CR_UNWRAP_MASK) - -#define PUF_CR_WRAP_GENERATED_RANDOM_MASK (0x100U) -#define PUF_CR_WRAP_GENERATED_RANDOM_SHIFT (8U) -/*! WRAP_GENERATED_RANDOM - Begin Wrap Generated Random operation - */ -#define PUF_CR_WRAP_GENERATED_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_WRAP_GENERATED_RANDOM_SHIFT)) & PUF_CR_WRAP_GENERATED_RANDOM_MASK) - -#define PUF_CR_WRAP_MASK (0x200U) -#define PUF_CR_WRAP_SHIFT (9U) -/*! WRAP - Begin Wrap operation - */ -#define PUF_CR_WRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_WRAP_SHIFT)) & PUF_CR_WRAP_MASK) - -#define PUF_CR_GENERATE_RANDOM_MASK (0x8000U) -#define PUF_CR_GENERATE_RANDOM_SHIFT (15U) -/*! GENERATE_RANDOM - Begin Generate Random operation - */ -#define PUF_CR_GENERATE_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_GENERATE_RANDOM_SHIFT)) & PUF_CR_GENERATE_RANDOM_MASK) - -#define PUF_CR_TEST_PUF_MASK (0x80000000U) -#define PUF_CR_TEST_PUF_SHIFT (31U) -/*! TEST_PUF - Begin Test PUF operation - */ -#define PUF_CR_TEST_PUF(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_TEST_PUF_SHIFT)) & PUF_CR_TEST_PUF_MASK) -/*! @} */ - -/*! @name ORR - Operation Result */ -/*! @{ */ - -#define PUF_ORR_RESULT_CODE_MASK (0xFFU) -#define PUF_ORR_RESULT_CODE_SHIFT (0U) -/*! RESULT_CODE - Result code of last operation - * 0b00000000..Last operation was successful or operation is in progress. - * 0b11110000..Provided AC is not for the current product/version. - * 0b11110001..AC in the second phase is not for the current product/version. - * 0b11110010..Provided AC is corrupted. - * 0b11110011..AC in the second phase is corrupted. - * 0b11110100..Authentication of the provided AC failed. - * 0b11110101..Authentication of the provided AC failed in the second phase. - * 0b11110110..SRAM PUF quality verification fails. - * 0b11110111..Incorrect or unsupported context is provided. - * 0b11111000..A data destination was set that is not allowed according to other settings and the current PUF state. - * 0b11111111..PUF SRAM access has failed. - */ -#define PUF_ORR_RESULT_CODE(x) (((uint32_t)(((uint32_t)(x)) << PUF_ORR_RESULT_CODE_SHIFT)) & PUF_ORR_RESULT_CODE_MASK) - -#define PUF_ORR_LAST_OPERATION_MASK (0xFF000000U) -#define PUF_ORR_LAST_OPERATION_SHIFT (24U) -/*! LAST_OPERATION - Number of last operation - * 0b00000000..Operation is in progress. - * 0b00000001..Last operation was Enroll. - * 0b00000010..Last operation was Start. - * 0b00000101..Last operation was Stop. - * 0b00000110..Last operation was Get Key. - * 0b00000111..Last operation was Unwrap. - * 0b00001000..Last operation was Wrap Generated Random. - * 0b00001001..Last operation was Wrap. - * 0b00001111..Last operation was Generate Random. - * 0b00011110..Last operation was Test Memory. - * 0b00011111..Last operation was Test PUF. - * 0b00100000..Last operation was Initialization. - * 0b00101111..Last operation was Zeroize. - */ -#define PUF_ORR_LAST_OPERATION(x) (((uint32_t)(((uint32_t)(x)) << PUF_ORR_LAST_OPERATION_SHIFT)) & PUF_ORR_LAST_OPERATION_MASK) -/*! @} */ - -/*! @name SR - Status */ -/*! @{ */ - -#define PUF_SR_BUSY_MASK (0x1U) -#define PUF_SR_BUSY_SHIFT (0U) -/*! BUSY - Operation is in progress - */ -#define PUF_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_BUSY_SHIFT)) & PUF_SR_BUSY_MASK) - -#define PUF_SR_OK_MASK (0x2U) -#define PUF_SR_OK_SHIFT (1U) -/*! OK - Last operation was successful - */ -#define PUF_SR_OK(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_OK_SHIFT)) & PUF_SR_OK_MASK) - -#define PUF_SR_ERROR_MASK (0x4U) -#define PUF_SR_ERROR_SHIFT (2U) -/*! ERROR - Last operation failed - */ -#define PUF_SR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_ERROR_SHIFT)) & PUF_SR_ERROR_MASK) - -#define PUF_SR_ZEROIZED_MASK (0x8U) -#define PUF_SR_ZEROIZED_SHIFT (3U) -/*! ZEROIZED - Zeroized or Locked state - */ -#define PUF_SR_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_ZEROIZED_SHIFT)) & PUF_SR_ZEROIZED_MASK) - -#define PUF_SR_REJECTED_MASK (0x10U) -#define PUF_SR_REJECTED_SHIFT (4U) -/*! REJECTED - Operation rejected - */ -#define PUF_SR_REJECTED(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_REJECTED_SHIFT)) & PUF_SR_REJECTED_MASK) - -#define PUF_SR_DI_REQUEST_MASK (0x20U) -#define PUF_SR_DI_REQUEST_SHIFT (5U) -/*! DI_REQUEST - Request for data in transfer via the DIR register - */ -#define PUF_SR_DI_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_DI_REQUEST_SHIFT)) & PUF_SR_DI_REQUEST_MASK) - -#define PUF_SR_DO_REQUEST_MASK (0x40U) -#define PUF_SR_DO_REQUEST_SHIFT (6U) -/*! DO_REQUEST - Request for data out transfer via the DOR register - */ -#define PUF_SR_DO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_DO_REQUEST_SHIFT)) & PUF_SR_DO_REQUEST_MASK) -/*! @} */ - -/*! @name AR - Allow */ -/*! @{ */ - -#define PUF_AR_ALLOW_ENROLL_MASK (0x2U) -#define PUF_AR_ALLOW_ENROLL_SHIFT (1U) -/*! ALLOW_ENROLL - Enroll operation - * 0b0..Enroll operation is not allowed - * 0b1..Enroll operation is allowed - */ -#define PUF_AR_ALLOW_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_ENROLL_SHIFT)) & PUF_AR_ALLOW_ENROLL_MASK) - -#define PUF_AR_ALLOW_START_MASK (0x4U) -#define PUF_AR_ALLOW_START_SHIFT (2U) -/*! ALLOW_START - Start operation - * 0b0..Start operation is not allowed - * 0b1..Start operation is allowed - */ -#define PUF_AR_ALLOW_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_START_SHIFT)) & PUF_AR_ALLOW_START_MASK) - -#define PUF_AR_ALLOW_STOP_MASK (0x20U) -#define PUF_AR_ALLOW_STOP_SHIFT (5U) -/*! ALLOW_STOP - Stop operation - * 0b1..Stop operation is allowed - * 0b0..Stop operation is not allowed - */ -#define PUF_AR_ALLOW_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_STOP_SHIFT)) & PUF_AR_ALLOW_STOP_MASK) - -#define PUF_AR_ALLOW_GET_KEY_MASK (0x40U) -#define PUF_AR_ALLOW_GET_KEY_SHIFT (6U) -/*! ALLOW_GET_KEY - Get Key operation - * 0b0..Get Key operation is not allowed - * 0b1..Get Key operation is allowed - */ -#define PUF_AR_ALLOW_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_GET_KEY_SHIFT)) & PUF_AR_ALLOW_GET_KEY_MASK) - -#define PUF_AR_ALLOW_UNWRAP_MASK (0x80U) -#define PUF_AR_ALLOW_UNWRAP_SHIFT (7U) -/*! ALLOW_UNWRAP - Unwrap operation - * 0b0..Unwrap operation is not allowed - * 0b1..Unwrap operation is allowed - */ -#define PUF_AR_ALLOW_UNWRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_UNWRAP_SHIFT)) & PUF_AR_ALLOW_UNWRAP_MASK) - -#define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_MASK (0x100U) -#define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_SHIFT (8U) -/*! ALLOW_WRAP_GENERATED_RANDOM - Wrap Generated Random operation - * 0b0..Wrap Generated Random operation is not allowed - * 0b1..Wrap Generated Random operation is allowed - */ -#define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_SHIFT)) & PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_MASK) - -#define PUF_AR_ALLOW_WRAP_MASK (0x200U) -#define PUF_AR_ALLOW_WRAP_SHIFT (9U) -/*! ALLOW_WRAP - Wrap operation - * 0b0..Wrap operation is not allowed - * 0b1..Wrap operation is allowed - */ -#define PUF_AR_ALLOW_WRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_WRAP_SHIFT)) & PUF_AR_ALLOW_WRAP_MASK) - -#define PUF_AR_ALLOW_GENERATE_RANDOM_MASK (0x8000U) -#define PUF_AR_ALLOW_GENERATE_RANDOM_SHIFT (15U) -/*! ALLOW_GENERATE_RANDOM - Generate Random operation - * 0b0..Generate Random operation is not allowed - * 0b1..Generate Random operation is allowed - */ -#define PUF_AR_ALLOW_GENERATE_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_GENERATE_RANDOM_SHIFT)) & PUF_AR_ALLOW_GENERATE_RANDOM_MASK) - -#define PUF_AR_ALLOW_TEST_PUF_MASK (0x80000000U) -#define PUF_AR_ALLOW_TEST_PUF_SHIFT (31U) -/*! ALLOW_TEST_PUF - Test PUF operation - * 0b0..Test PUF operation is not allowed - * 0b1..Test PUF operation is allowed - */ -#define PUF_AR_ALLOW_TEST_PUF(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_TEST_PUF_SHIFT)) & PUF_AR_ALLOW_TEST_PUF_MASK) -/*! @} */ - -/*! @name IER - Interrupt Enable */ -/*! @{ */ - -#define PUF_IER_INT_EN_MASK (0x1U) -#define PUF_IER_INT_EN_SHIFT (0U) -/*! INT_EN - Interrupt enable - * 0b0..Disables all PUF interrupts - * 0b1..Enables all PUF interrupts that are enabled in the Interrupt Mask register - */ -#define PUF_IER_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PUF_IER_INT_EN_SHIFT)) & PUF_IER_INT_EN_MASK) -/*! @} */ - -/*! @name IMR - Interrupt Mask */ -/*! @{ */ - -#define PUF_IMR_INT_EN_BUSY_MASK (0x1U) -#define PUF_IMR_INT_EN_BUSY_SHIFT (0U) -/*! INT_EN_BUSY - Enable busy interrupt - */ -#define PUF_IMR_INT_EN_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_BUSY_SHIFT)) & PUF_IMR_INT_EN_BUSY_MASK) - -#define PUF_IMR_INT_EN_OK_MASK (0x2U) -#define PUF_IMR_INT_EN_OK_SHIFT (1U) -/*! INT_EN_OK - Enable ok interrupt - */ -#define PUF_IMR_INT_EN_OK(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_OK_SHIFT)) & PUF_IMR_INT_EN_OK_MASK) - -#define PUF_IMR_INT_EN_ERROR_MASK (0x4U) -#define PUF_IMR_INT_EN_ERROR_SHIFT (2U) -/*! INT_EN_ERROR - Enable error interrupt - */ -#define PUF_IMR_INT_EN_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_ERROR_SHIFT)) & PUF_IMR_INT_EN_ERROR_MASK) - -#define PUF_IMR_INT_EN_ZEROIZED_MASK (0x8U) -#define PUF_IMR_INT_EN_ZEROIZED_SHIFT (3U) -/*! INT_EN_ZEROIZED - Enable zeroized interrupt - */ -#define PUF_IMR_INT_EN_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_ZEROIZED_SHIFT)) & PUF_IMR_INT_EN_ZEROIZED_MASK) - -#define PUF_IMR_INT_EN_REJECTED_MASK (0x10U) -#define PUF_IMR_INT_EN_REJECTED_SHIFT (4U) -/*! INT_EN_REJECTED - Enable rejected interrupt - */ -#define PUF_IMR_INT_EN_REJECTED(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_REJECTED_SHIFT)) & PUF_IMR_INT_EN_REJECTED_MASK) - -#define PUF_IMR_INT_EN_DI_REQUEST_MASK (0x20U) -#define PUF_IMR_INT_EN_DI_REQUEST_SHIFT (5U) -/*! INT_EN_DI_REQUEST - Enable data in request interrupt - */ -#define PUF_IMR_INT_EN_DI_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_DI_REQUEST_SHIFT)) & PUF_IMR_INT_EN_DI_REQUEST_MASK) - -#define PUF_IMR_INT_EN_DO_REQUEST_MASK (0x40U) -#define PUF_IMR_INT_EN_DO_REQUEST_SHIFT (6U) -/*! INT_EN_DO_REQUEST - Enable data out request interrupt - */ -#define PUF_IMR_INT_EN_DO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_DO_REQUEST_SHIFT)) & PUF_IMR_INT_EN_DO_REQUEST_MASK) -/*! @} */ - -/*! @name ISR - Interrupt Status */ -/*! @{ */ - -#define PUF_ISR_INT_BUSY_MASK (0x1U) -#define PUF_ISR_INT_BUSY_SHIFT (0U) -/*! INT_BUSY - Negative edge occurred on busy, which means that an operation has completed - */ -#define PUF_ISR_INT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_BUSY_SHIFT)) & PUF_ISR_INT_BUSY_MASK) - -#define PUF_ISR_INT_OK_MASK (0x2U) -#define PUF_ISR_INT_OK_SHIFT (1U) -/*! INT_OK - Positive edge occurred on ok, which means that an operation successfully completed - */ -#define PUF_ISR_INT_OK(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_OK_SHIFT)) & PUF_ISR_INT_OK_MASK) - -#define PUF_ISR_INT_ERROR_MASK (0x4U) -#define PUF_ISR_INT_ERROR_SHIFT (2U) -/*! INT_ERROR - Positive edge occurred on error, which means that an operation has failed - */ -#define PUF_ISR_INT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_ERROR_SHIFT)) & PUF_ISR_INT_ERROR_MASK) - -#define PUF_ISR_INT_ZEROIZED_MASK (0x8U) -#define PUF_ISR_INT_ZEROIZED_SHIFT (3U) -/*! INT_ZEROIZED - Positive edge occurred on zeroized, which means that PUF has moved to the Zeroized or Locked state - */ -#define PUF_ISR_INT_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_ZEROIZED_SHIFT)) & PUF_ISR_INT_ZEROIZED_MASK) - -#define PUF_ISR_INT_REJECTED_MASK (0x10U) -#define PUF_ISR_INT_REJECTED_SHIFT (4U) -/*! INT_REJECTED - Positive edge occurred on rejected, which means that a command was rejected - */ -#define PUF_ISR_INT_REJECTED(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_REJECTED_SHIFT)) & PUF_ISR_INT_REJECTED_MASK) - -#define PUF_ISR_INT_DI_REQUEST_MASK (0x20U) -#define PUF_ISR_INT_DI_REQUEST_SHIFT (5U) -/*! INT_DI_REQUEST - Positive edge occurred on di_request, which means that a data in transfer is requested via the DIR register - */ -#define PUF_ISR_INT_DI_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_DI_REQUEST_SHIFT)) & PUF_ISR_INT_DI_REQUEST_MASK) - -#define PUF_ISR_INT_DO_REQUEST_MASK (0x40U) -#define PUF_ISR_INT_DO_REQUEST_SHIFT (6U) -/*! INT_DO_REQUEST - Positive edge occurred on do_request, which means that a data out transfer is requested via the DOR register - */ -#define PUF_ISR_INT_DO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_DO_REQUEST_SHIFT)) & PUF_ISR_INT_DO_REQUEST_MASK) -/*! @} */ - -/*! @name KEY_DEST - Key Destination */ -/*! @{ */ - -#define PUF_KEY_DEST_DEST_DOR_MASK (0x1U) -#define PUF_KEY_DEST_DEST_DOR_SHIFT (0U) -/*! DEST_DOR - Key will be made available via the DOR register - */ -#define PUF_KEY_DEST_DEST_DOR(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEY_DEST_DEST_DOR_SHIFT)) & PUF_KEY_DEST_DEST_DOR_MASK) - -#define PUF_KEY_DEST_DEST_KO_MASK (0x2U) -#define PUF_KEY_DEST_DEST_KO_SHIFT (1U) -/*! DEST_KO - Key will be made available via the KO interface - */ -#define PUF_KEY_DEST_DEST_KO(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEY_DEST_DEST_KO_SHIFT)) & PUF_KEY_DEST_DEST_KO_MASK) -/*! @} */ - -/*! @name DIR - Data Input */ -/*! @{ */ - -#define PUF_DIR_DI_MASK (0xFFFFFFFFU) -#define PUF_DIR_DI_SHIFT (0U) -/*! DI - Input data to PUF - */ -#define PUF_DIR_DI(x) (((uint32_t)(((uint32_t)(x)) << PUF_DIR_DI_SHIFT)) & PUF_DIR_DI_MASK) -/*! @} */ - -/*! @name DOR - Data Output */ -/*! @{ */ - -#define PUF_DOR_DO_MASK (0xFFFFFFFFU) -#define PUF_DOR_DO_SHIFT (0U) -/*! DO - Output data from PUF - */ -#define PUF_DOR_DO(x) (((uint32_t)(((uint32_t)(x)) << PUF_DOR_DO_SHIFT)) & PUF_DOR_DO_MASK) -/*! @} */ - -/*! @name MISC - Miscellaneous */ -/*! @{ */ - -#define PUF_MISC_DATA_ENDIANNESS_MASK (0x1U) -#define PUF_MISC_DATA_ENDIANNESS_SHIFT (0U) -/*! DATA_ENDIANNESS - Defines the endianness of data in DIR and DOR: - * 0b0..Little endian - * 0b1..Big endian (default) - */ -#define PUF_MISC_DATA_ENDIANNESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_MISC_DATA_ENDIANNESS_SHIFT)) & PUF_MISC_DATA_ENDIANNESS_MASK) -/*! @} */ - -/*! @name IF_SR - Interface Status */ -/*! @{ */ - -#define PUF_IF_SR_APB_ERROR_MASK (0x1U) -#define PUF_IF_SR_APB_ERROR_SHIFT (0U) -/*! APB_ERROR - An APB error occurred - */ -#define PUF_IF_SR_APB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IF_SR_APB_ERROR_SHIFT)) & PUF_IF_SR_APB_ERROR_MASK) -/*! @} */ - -/*! @name PSR - PUF Score */ -/*! @{ */ - -#define PUF_PSR_PUF_SCORE_MASK (0xFU) -#define PUF_PSR_PUF_SCORE_SHIFT (0U) -/*! PUF_SCORE - PUF score obtained during the last Test PUF, Enroll or Start operation - */ -#define PUF_PSR_PUF_SCORE(x) (((uint32_t)(((uint32_t)(x)) << PUF_PSR_PUF_SCORE_SHIFT)) & PUF_PSR_PUF_SCORE_MASK) -/*! @} */ - -/*! @name HW_RUC0 - Hardware Restrict User Context 0 */ -/*! @{ */ - -#define PUF_HW_RUC0_LC_STATE_MASK (0xFFU) -#define PUF_HW_RUC0_LC_STATE_SHIFT (0U) -/*! LC_STATE - Life cycle state based restrictions - * 0b00000011..OEM Develop - * 0b00000111..OEM Develop 2 - * 0b00001111..OEM In-field - * 0b00011111..OEM Field return - * 0b00111111..NXP Field Return/Failure Analysis - * 0b11001111..In-field Locked - * 0b11111111..Bricked - */ -#define PUF_HW_RUC0_LC_STATE(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_LC_STATE_SHIFT)) & PUF_HW_RUC0_LC_STATE_MASK) - -#define PUF_HW_RUC0_BOOT_STATE_MASK (0xFFFF00U) -#define PUF_HW_RUC0_BOOT_STATE_SHIFT (8U) -/*! BOOT_STATE - Temporal boot state - */ -#define PUF_HW_RUC0_BOOT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_BOOT_STATE_SHIFT)) & PUF_HW_RUC0_BOOT_STATE_MASK) - -#define PUF_HW_RUC0_CPU0_DEBUG_MASK (0x1000000U) -#define PUF_HW_RUC0_CPU0_DEBUG_SHIFT (24U) -/*! CPU0_DEBUG - Disable key access when debugger is attached to CPU0 after power-up - */ -#define PUF_HW_RUC0_CPU0_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_CPU0_DEBUG_SHIFT)) & PUF_HW_RUC0_CPU0_DEBUG_MASK) - -#define PUF_HW_RUC0_RUC026_MASK (0x4000000U) -#define PUF_HW_RUC0_RUC026_SHIFT (26U) -/*! RUC026 - Restrict user context 0 - * 0b0..Bit can be used - * 0b1..Bit cannot be used - */ -#define PUF_HW_RUC0_RUC026(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_RUC026_SHIFT)) & PUF_HW_RUC0_RUC026_MASK) - -#define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) -#define PUF_HW_RUC0_ACCESS_LEVEL_SHIFT (28U) -/*! ACCESS_LEVEL - Restrict the key access based on TrustZone security level - */ -#define PUF_HW_RUC0_ACCESS_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK) -/*! @} */ - -/*! @name HW_RUC1 - Hardware Restrict User Context 1 */ -/*! @{ */ - -#define PUF_HW_RUC1_APP_CTX_MASK (0xFFFFFFFFU) -#define PUF_HW_RUC1_APP_CTX_SHIFT (0U) -/*! APP_CTX - Application customizable context - */ -#define PUF_HW_RUC1_APP_CTX(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC1_APP_CTX_SHIFT)) & PUF_HW_RUC1_APP_CTX_MASK) -/*! @} */ - -/*! @name HW_INFO - Hardware Information */ -/*! @{ */ - -#define PUF_HW_INFO_CONFIG_BIST_MASK (0x400000U) -#define PUF_HW_INFO_CONFIG_BIST_SHIFT (22U) -/*! CONFIG_BIST - BIST configuration - * 0b0..BIST is not included - * 0b1..BIST is included - */ -#define PUF_HW_INFO_CONFIG_BIST(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_BIST_SHIFT)) & PUF_HW_INFO_CONFIG_BIST_MASK) - -#define PUF_HW_INFO_CONFIG_WRAP_MASK (0x1000000U) -#define PUF_HW_INFO_CONFIG_WRAP_SHIFT (24U) -/*! CONFIG_WRAP - Wrap configuration - * 0b0..Wrap is not included - * 0b1..Wrap is included - */ -#define PUF_HW_INFO_CONFIG_WRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_WRAP_SHIFT)) & PUF_HW_INFO_CONFIG_WRAP_MASK) - -#define PUF_HW_INFO_CONFIG_TYPE_MASK (0xF0000000U) -#define PUF_HW_INFO_CONFIG_TYPE_SHIFT (28U) -/*! CONFIG_TYPE - PUF configuration - * 0b0001..PUF configuration is Safe. - * 0b0010..PUF configuration is Plus. - */ -#define PUF_HW_INFO_CONFIG_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_TYPE_SHIFT)) & PUF_HW_INFO_CONFIG_TYPE_MASK) -/*! @} */ - -/*! @name HW_ID - Hardware Identifier */ -/*! @{ */ - -#define PUF_HW_ID_HW_ID_MASK (0xFFFFFFFFU) -#define PUF_HW_ID_HW_ID_SHIFT (0U) -/*! HW_ID - Hardware identifier - */ -#define PUF_HW_ID_HW_ID(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_ID_HW_ID_SHIFT)) & PUF_HW_ID_HW_ID_MASK) -/*! @} */ - -/*! @name HW_VER - Hardware Version */ -/*! @{ */ - -#define PUF_HW_VER_HW_REV_MASK (0xFFU) -#define PUF_HW_VER_HW_REV_SHIFT (0U) -/*! HW_REV - Hardware version, patch part - */ -#define PUF_HW_VER_HW_REV(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_REV_SHIFT)) & PUF_HW_VER_HW_REV_MASK) - -#define PUF_HW_VER_HW_VERSION_MINOR_MASK (0xFF00U) -#define PUF_HW_VER_HW_VERSION_MINOR_SHIFT (8U) -/*! HW_VERSION_MINOR - Hardware version, minor part - */ -#define PUF_HW_VER_HW_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_VERSION_MINOR_SHIFT)) & PUF_HW_VER_HW_VERSION_MINOR_MASK) - -#define PUF_HW_VER_HW_VERSION_MAJOR_MASK (0xFF0000U) -#define PUF_HW_VER_HW_VERSION_MAJOR_SHIFT (16U) -/*! HW_VERSION_MAJOR - Hardware version, major part - */ -#define PUF_HW_VER_HW_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_VERSION_MAJOR_SHIFT)) & PUF_HW_VER_HW_VERSION_MAJOR_MASK) -/*! @} */ - -/*! @name CONFIG - PUF command blocking configuration */ -/*! @{ */ - -#define PUF_CONFIG_DIS_PUF_ENROLL_MASK (0x2U) -#define PUF_CONFIG_DIS_PUF_ENROLL_SHIFT (1U) -/*! DIS_PUF_ENROLL - Disable PUF enroll command - */ -#define PUF_CONFIG_DIS_PUF_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_ENROLL_SHIFT)) & PUF_CONFIG_DIS_PUF_ENROLL_MASK) - -#define PUF_CONFIG_DIS_PUF_START_MASK (0x4U) -#define PUF_CONFIG_DIS_PUF_START_SHIFT (2U) -/*! DIS_PUF_START - Disable PUF start command - */ -#define PUF_CONFIG_DIS_PUF_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_START_SHIFT)) & PUF_CONFIG_DIS_PUF_START_MASK) - -#define PUF_CONFIG_DIS_PUF_STOP_MASK (0x20U) -#define PUF_CONFIG_DIS_PUF_STOP_SHIFT (5U) -/*! DIS_PUF_STOP - Disable PUF stop command - */ -#define PUF_CONFIG_DIS_PUF_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_STOP_SHIFT)) & PUF_CONFIG_DIS_PUF_STOP_MASK) - -#define PUF_CONFIG_DIS_PUF_GET_KEY_MASK (0x40U) -#define PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT (6U) -/*! DIS_PUF_GET_KEY - Disable PUF get key command - */ -#define PUF_CONFIG_DIS_PUF_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GET_KEY_MASK) - -#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK (0x80U) -#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT (7U) -/*! DIS_PUF_UNWRAP_KEY - Disable PUF unwrap key command - */ -#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK) - -#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK (0x100U) -#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT (8U) -/*! DIS_PUF_GEN_WRAP_KEY - Disable PUF generate and wrap key command - */ -#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK) - -#define PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK (0x200U) -#define PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT (9U) -/*! DIS_PUF_WRAP_KEY - Disable PUF wrap key command - */ -#define PUF_CONFIG_DIS_PUF_WRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK) - -#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK (0x8000U) -#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT (15U) -/*! DIS_PUF_GEN_RANDOM_NUMBER - Disable PUF generate and wrap key command - */ -#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK) - -#define PUF_CONFIG_DIS_PUF_TEST_MASK (0x80000000U) -#define PUF_CONFIG_DIS_PUF_TEST_SHIFT (31U) -/*! DIS_PUF_TEST - Disable PUF test command - */ -#define PUF_CONFIG_DIS_PUF_TEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_TEST_SHIFT)) & PUF_CONFIG_DIS_PUF_TEST_MASK) -/*! @} */ - -/*! @name SEC_LOCK - Lock the security level of PUF block until key generate, wrap or unwrap operation is completed. */ -/*! @{ */ - -#define PUF_SEC_LOCK_SEC_LEVEL_MASK (0x3U) -#define PUF_SEC_LOCK_SEC_LEVEL_SHIFT (0U) -/*! SEC_LEVEL - Disable PUF enroll command - * 0b00..Nonsecure user - * 0b00..Nonsecure privilege - * 0b00..Secure user - * 0b00..Secure privilege - */ -#define PUF_SEC_LOCK_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_SEC_LEVEL_MASK) - -#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK (0xCU) -#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT (2U) -/*! ANTI_POLE_SEC_LEVEL - Anti-pole of security level - */ -#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK) - -#define PUF_SEC_LOCK_PATTERN_MASK (0xFFF0U) -#define PUF_SEC_LOCK_PATTERN_SHIFT (4U) -/*! PATTERN - Pattern - */ -#define PUF_SEC_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_PATTERN_SHIFT)) & PUF_SEC_LOCK_PATTERN_MASK) -/*! @} */ - -/*! @name APP_CTX_MASK - Application defined context mask */ -/*! @{ */ - -#define PUF_APP_CTX_MASK_APP_CTX_MASK_MASK (0xFFFFFFFFU) -#define PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT (0U) -/*! APP_CTX_MASK - Application defined context - */ -#define PUF_APP_CTX_MASK_APP_CTX_MASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT)) & PUF_APP_CTX_MASK_APP_CTX_MASK_MASK) -/*! @} */ - -/*! @name SRAM_CFG - SRAM Configuration */ -/*! @{ */ - -#define PUF_SRAM_CFG_ENABLE_MASK (0x1U) -#define PUF_SRAM_CFG_ENABLE_SHIFT (0U) -/*! ENABLE - PUF SRAM Controller activation - * 0b1..Enabled - * 0b1..Disabled - */ -#define PUF_SRAM_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CFG_ENABLE_SHIFT)) & PUF_SRAM_CFG_ENABLE_MASK) - -#define PUF_SRAM_CFG_CKGATING_MASK (0x4U) -#define PUF_SRAM_CFG_CKGATING_SHIFT (2U) -/*! CKGATING - PUF SRAM Clock Gating control - * 0b1..Enabled - * 0b1..Disabled - */ -#define PUF_SRAM_CFG_CKGATING(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CFG_CKGATING_SHIFT)) & PUF_SRAM_CFG_CKGATING_MASK) -/*! @} */ - -/*! @name SRAM_STATUS - Status */ -/*! @{ */ - -#define PUF_SRAM_STATUS_READY_MASK (0x1U) -#define PUF_SRAM_STATUS_READY_SHIFT (0U) -/*! READY - PUF SRAM Controller State - */ -#define PUF_SRAM_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_STATUS_READY_SHIFT)) & PUF_SRAM_STATUS_READY_MASK) -/*! @} */ - -/*! @name SRAM_INT_CLR_ENABLE - Interrupt Enable Clear */ -/*! @{ */ - -#define PUF_SRAM_INT_CLR_ENABLE_READY_MASK (0x1U) -#define PUF_SRAM_INT_CLR_ENABLE_READY_SHIFT (0U) -/*! READY - READY Interrupt Enable clear - */ -#define PUF_SRAM_INT_CLR_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_CLR_ENABLE_READY_MASK) - -#define PUF_SRAM_INT_CLR_ENABLE_APB_ERR_MASK (0x2U) -#define PUF_SRAM_INT_CLR_ENABLE_APB_ERR_SHIFT (1U) -/*! APB_ERR - APB_ERR Interrupt Enable clear - */ -#define PUF_SRAM_INT_CLR_ENABLE_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_INT_CLR_ENABLE_APB_ERR_MASK) -/*! @} */ - -/*! @name SRAM_INT_SET_ENABLE - Interrupt Enable Set */ -/*! @{ */ - -#define PUF_SRAM_INT_SET_ENABLE_READY_MASK (0x1U) -#define PUF_SRAM_INT_SET_ENABLE_READY_SHIFT (0U) -/*! READY - READY Interrupt Enable set - */ -#define PUF_SRAM_INT_SET_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_READY_MASK) - -#define PUF_SRAM_INT_SET_ENABLE_APB_ERR_MASK (0x2U) -#define PUF_SRAM_INT_SET_ENABLE_APB_ERR_SHIFT (1U) -/*! APB_ERR - APB_ERR Interrupt Enable set - */ -#define PUF_SRAM_INT_SET_ENABLE_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_APB_ERR_MASK) -/*! @} */ - -/*! @name SRAM_INT_STATUS - Interrupt Status */ -/*! @{ */ - -#define PUF_SRAM_INT_STATUS_READY_MASK (0x1U) -#define PUF_SRAM_INT_STATUS_READY_SHIFT (0U) -/*! READY - READY Interrupt Status - */ -#define PUF_SRAM_INT_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_STATUS_READY_SHIFT)) & PUF_SRAM_INT_STATUS_READY_MASK) - -#define PUF_SRAM_INT_STATUS_APB_ERR_MASK (0x2U) -#define PUF_SRAM_INT_STATUS_APB_ERR_SHIFT (1U) -/*! APB_ERR - APB_ERR Interrupt Status - */ -#define PUF_SRAM_INT_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_STATUS_APB_ERR_MASK) -/*! @} */ - -/*! @name SRAM_INT_ENABLE - Interrupt Enable */ -/*! @{ */ - -#define PUF_SRAM_INT_ENABLE_READY_MASK (0x1U) -#define PUF_SRAM_INT_ENABLE_READY_SHIFT (0U) -/*! READY - READY Interrupt Enable - * 0b1..Enabled - * 0b1..Disabled - */ -#define PUF_SRAM_INT_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_ENABLE_READY_MASK) - -#define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_MASK (0x2U) -#define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_SHIFT (1U) -/*! SRAM_APB_ERR - APB_ERR Interrupt Enable - * 0b1..Enabled - * 0b1..Disabled - */ -#define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_SHIFT)) & PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_MASK) -/*! @} */ - -/*! @name SRAM_INT_CLR_STATUS - Interrupt Status Clear */ -/*! @{ */ - -#define PUF_SRAM_INT_CLR_STATUS_READY_MASK (0x1U) -#define PUF_SRAM_INT_CLR_STATUS_READY_SHIFT (0U) -/*! READY - READY Interrupt Status clear - */ -#define PUF_SRAM_INT_CLR_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_STATUS_READY_SHIFT)) & PUF_SRAM_INT_CLR_STATUS_READY_MASK) - -#define PUF_SRAM_INT_CLR_STATUS_APB_ERR_MASK (0x2U) -#define PUF_SRAM_INT_CLR_STATUS_APB_ERR_SHIFT (1U) -/*! APB_ERR - APB_ERR Interrupt Status Clear - */ -#define PUF_SRAM_INT_CLR_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_CLR_STATUS_APB_ERR_MASK) -/*! @} */ - -/*! @name SRAM_INT_SET_STATUS - Interrupt Status set */ -/*! @{ */ - -#define PUF_SRAM_INT_SET_STATUS_READY_MASK (0x1U) -#define PUF_SRAM_INT_SET_STATUS_READY_SHIFT (0U) -/*! READY - READY Interrupt Status set - */ -#define PUF_SRAM_INT_SET_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_STATUS_READY_SHIFT)) & PUF_SRAM_INT_SET_STATUS_READY_MASK) - -#define PUF_SRAM_INT_SET_STATUS_APB_ERR_MASK (0x2U) -#define PUF_SRAM_INT_SET_STATUS_APB_ERR_SHIFT (1U) -/*! APB_ERR - APB_ERR Interrupt Status Set - */ -#define PUF_SRAM_INT_SET_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_SET_STATUS_APB_ERR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PUF_Register_Masks */ - - -/* PUF - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PUF base address 0 */ - #define PUF_BASE_0 (0x5003A000u) - /** Peripheral PUF base address 0 */ - #define PUF_BASE_0_NS (0x4003A000u) - /** Peripheral PUF base address 1 */ - #define PUF_BASE_1 (0x5003B000u) - /** Peripheral PUF base address 1 */ - #define PUF_BASE_1_NS (0x4003B000u) - /** Peripheral PUF base address 2 */ - #define PUF_BASE_2 (0x5003C000u) - /** Peripheral PUF base address 2 */ - #define PUF_BASE_2_NS (0x4003C000u) - /** Peripheral PUF base address 3 */ - #define PUF_BASE_3 (0x5003D000u) - /** Peripheral PUF base address 3 */ - #define PUF_BASE_3_NS (0x4003D000u) - /** Peripheral PUF base pointer 0 */ - #define PUF_ALIAS_0 ((PUF_Type *)PUF_BASE_0) - /** Peripheral PUF base pointer 0 */ - #define PUF_ALIAS_0_NS ((PUF_Type *)PUF_BASE_0_NS) - /** Peripheral PUF base pointer 1 */ - #define PUF_ALIAS_1 ((PUF_Type *)PUF_BASE_1) - /** Peripheral PUF base pointer 1 */ - #define PUF_ALIAS_1_NS ((PUF_Type *)PUF_BASE_1_NS) - /** Peripheral PUF base pointer 2 */ - #define PUF_ALIAS_2 ((PUF_Type *)PUF_BASE_2) - /** Peripheral PUF base pointer 2 */ - #define PUF_ALIAS_2_NS ((PUF_Type *)PUF_BASE_2_NS) - /** Peripheral PUF base pointer 3 */ - #define PUF_ALIAS_3 ((PUF_Type *)PUF_BASE_3) - /** Peripheral PUF base pointer 3 */ - #define PUF_ALIAS_3_NS ((PUF_Type *)PUF_BASE_3_NS) - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS_0 { PUF_BASE_0 } - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS_1 { PUF_BASE_1 } - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS_2 { PUF_BASE_2 } - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS_3 { PUF_BASE_3 } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS_0 { PUF_ALIAS_0 } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS_1 { PUF_ALIAS_1 } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS_2 { PUF_ALIAS_2 } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS_3 { PUF_ALIAS_3 } - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS_0_NS { PUF_BASE_0_NS } - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS_1_NS { PUF_BASE_1_NS } - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS_2_NS { PUF_BASE_2_NS } - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS_3_NS { PUF_BASE_3_NS } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS_0_NS { PUF_ALIAS_0_NS } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS_1_NS { PUF_ALIAS_1_NS } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS_2_NS { PUF_ALIAS_2_NS } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS_3_NS { PUF_ALIAS_3_NS } -#else - /** Peripheral PUF base address 0 */ - #define PUF_BASE_0 (0x4003A000u) - /** Peripheral PUF base address 1 */ - #define PUF_BASE_1 (0x4003B000u) - /** Peripheral PUF base address 2 */ - #define PUF_BASE_2 (0x4003C000u) - /** Peripheral PUF base address 3 */ - #define PUF_BASE_3 (0x4003D000u) - /** Peripheral PUF base pointer 0 */ - #define PUF_ALIAS_0 ((PUF_Type *)PUF_BASE_0) - /** Peripheral PUF base pointer 1 */ - #define PUF_ALIAS_1 ((PUF_Type *)PUF_BASE_1) - /** Peripheral PUF base pointer 2 */ - #define PUF_ALIAS_2 ((PUF_Type *)PUF_BASE_2) - /** Peripheral PUF base pointer 3 */ - #define PUF_ALIAS_3 ((PUF_Type *)PUF_BASE_3) - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS_0 { PUF_BASE_0 } - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS_1 { PUF_BASE_1 } - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS_2 { PUF_BASE_2 } - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS_3 { PUF_BASE_3 } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS_0 { PUF_ALIAS_0 } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS_1 { PUF_ALIAS_1 } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS_2 { PUF_ALIAS_2 } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS_3 { PUF_ALIAS_3 } -#endif -/** Interrupt vectors for the PUF peripheral type */ -#define PUF_IRQS { PUF_IRQn } - -/*! - * @} - */ /* end of group PUF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PWM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer - * @{ - */ - -/** PWM - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x60 */ - __I uint16_t CNT; /**< Counter Register, array offset: 0x0, array step: 0x60 */ - __IO uint16_t INIT; /**< Initial Count Register, array offset: 0x2, array step: 0x60 */ - __IO uint16_t CTRL2; /**< Control 2 Register, array offset: 0x4, array step: 0x60 */ - __IO uint16_t CTRL; /**< Control Register, array offset: 0x6, array step: 0x60 */ - uint8_t RESERVED_0[2]; - __IO uint16_t VAL0; /**< Value Register 0, array offset: 0xA, array step: 0x60 */ - __IO uint16_t FRACVAL1; /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */ - __IO uint16_t VAL1; /**< Value Register 1, array offset: 0xE, array step: 0x60 */ - __IO uint16_t FRACVAL2; /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */ - __IO uint16_t VAL2; /**< Value Register 2, array offset: 0x12, array step: 0x60 */ - __IO uint16_t FRACVAL3; /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */ - __IO uint16_t VAL3; /**< Value Register 3, array offset: 0x16, array step: 0x60 */ - __IO uint16_t FRACVAL4; /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */ - __IO uint16_t VAL4; /**< Value Register 4, array offset: 0x1A, array step: 0x60 */ - __IO uint16_t FRACVAL5; /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */ - __IO uint16_t VAL5; /**< Value Register 5, array offset: 0x1E, array step: 0x60 */ - __IO uint16_t FRCTRL; /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */ - __IO uint16_t OCTRL; /**< Output Control Register, array offset: 0x22, array step: 0x60 */ - __IO uint16_t STS; /**< Status Register, array offset: 0x24, array step: 0x60 */ - __IO uint16_t INTEN; /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */ - __IO uint16_t DMAEN; /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */ - __IO uint16_t TCTRL; /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */ - __IO uint16_t DISMAP[1]; /**< Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2 */ - uint8_t RESERVED_1[2]; - __IO uint16_t DTCNT0; /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */ - __IO uint16_t DTCNT1; /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */ - __IO uint16_t CAPTCTRLA; /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */ - __IO uint16_t CAPTCOMPA; /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */ - __IO uint16_t CAPTCTRLB; /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */ - __IO uint16_t CAPTCOMPB; /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */ - __IO uint16_t CAPTCTRLX; /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */ - __IO uint16_t CAPTCOMPX; /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */ - __I uint16_t CVAL0; /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */ - __I uint16_t CVAL0CYC; /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */ - __I uint16_t CVAL1; /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */ - __I uint16_t CVAL1CYC; /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */ - __I uint16_t CVAL2; /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */ - __I uint16_t CVAL2CYC; /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */ - __I uint16_t CVAL3; /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */ - __I uint16_t CVAL3CYC; /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */ - __I uint16_t CVAL4; /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */ - __I uint16_t CVAL4CYC; /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */ - __I uint16_t CVAL5; /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */ - __I uint16_t CVAL5CYC; /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */ - __IO uint16_t PHASEDLY; /**< Phase Delay Register, array offset: 0x58, array step: 0x60 */ - __IO uint16_t CAPTFILTA; /**< Capture PWMA Input Filter Register, array offset: 0x5A, array step: 0x60 */ - __IO uint16_t CAPTFILTB; /**< Capture PWMB Input Filter Register, array offset: 0x5C, array step: 0x60 */ - __IO uint16_t CAPTFILTX; /**< Capture PWMX Input Filter Register, array offset: 0x5E, array step: 0x60 */ - } SM[4]; - __IO uint16_t OUTEN; /**< Output Enable Register, offset: 0x180 */ - __IO uint16_t MASK; /**< Mask Register, offset: 0x182 */ - __IO uint16_t SWCOUT; /**< Software Controlled Output Register, offset: 0x184 */ - __IO uint16_t DTSRCSEL; /**< PWM Source Select Register, offset: 0x186 */ - __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ - __IO uint16_t MCTRL2; /**< Master Control 2 Register, offset: 0x18A */ - __IO uint16_t FCTRL; /**< Fault Control Register, offset: 0x18C */ - __IO uint16_t FSTS; /**< Fault Status Register, offset: 0x18E */ - __IO uint16_t FFILT; /**< Fault Filter Register, offset: 0x190 */ - __IO uint16_t FTST; /**< Fault Test Register, offset: 0x192 */ - __IO uint16_t FCTRL2; /**< Fault Control 2 Register, offset: 0x194 */ -} PWM_Type; - -/* ---------------------------------------------------------------------------- - -- PWM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PWM_Register_Masks PWM Register Masks - * @{ - */ - -/*! @name CNT - Counter Register */ -/*! @{ */ - -#define PWM_CNT_CNT_MASK (0xFFFFU) -#define PWM_CNT_CNT_SHIFT (0U) -/*! CNT - Counter Register Bits - */ -#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK) -/*! @} */ - -/* The count of PWM_CNT */ -#define PWM_CNT_COUNT (4U) - -/*! @name INIT - Initial Count Register */ -/*! @{ */ - -#define PWM_INIT_INIT_MASK (0xFFFFU) -#define PWM_INIT_INIT_SHIFT (0U) -/*! INIT - Initial Count Register Bits - */ -#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK) -/*! @} */ - -/* The count of PWM_INIT */ -#define PWM_INIT_COUNT (4U) - -/*! @name CTRL2 - Control 2 Register */ -/*! @{ */ - -#define PWM_CTRL2_CLK_SEL_MASK (0x3U) -#define PWM_CTRL2_CLK_SEL_SHIFT (0U) -/*! CLK_SEL - Clock Source Select - * 0b00..The IPBus clock is used as the clock for the local prescaler and counter. - * 0b01..EXT_CLK is used as the clock for the local prescaler and counter. - * 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This - * setting should not be used in submodule 0 as it will force the clock to logic 0. - * 0b11..reserved - */ -#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK) - -#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U) -#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U) -/*! RELOAD_SEL - Reload Source Select - * 0b0..The local RELOAD signal is used to reload registers. - * 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used - * in submodule 0 as it will force the RELOAD signal to logic 0. - */ -#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK) - -#define PWM_CTRL2_FORCE_SEL_MASK (0x38U) -#define PWM_CTRL2_FORCE_SEL_SHIFT (3U) -/*! FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. - * 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates. - * 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in - * submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. - * 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK. - * 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should - * not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. - * 0b100..The local sync signal from this submodule is used to force updates. - * 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in - * submodule0 as it will hold the FORCE OUTPUT signal to logic 0. - * 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates. - * 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates. - */ -#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK) - -#define PWM_CTRL2_FORCE_MASK (0x40U) -#define PWM_CTRL2_FORCE_SHIFT (6U) -/*! FORCE - Force Initialization - */ -#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK) - -#define PWM_CTRL2_FRCEN_MASK (0x80U) -#define PWM_CTRL2_FRCEN_SHIFT (7U) -/*! FRCEN - FRCEN - * 0b0..Initialization from a FORCE_OUT is disabled. - * 0b1..Initialization from a FORCE_OUT is enabled. - */ -#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK) - -#define PWM_CTRL2_INIT_SEL_MASK (0x300U) -#define PWM_CTRL2_INIT_SEL_SHIFT (8U) -/*! INIT_SEL - Initialization Control Select - * 0b00..Local sync (PWM_X) causes initialization. - * 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as - * it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master - * reload occurs. - * 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it - * will force the INIT signal to logic 0. - * 0b11..EXT_SYNC causes initialization. - */ -#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK) - -#define PWM_CTRL2_PWMX_INIT_MASK (0x400U) -#define PWM_CTRL2_PWMX_INIT_SHIFT (10U) -/*! PWMX_INIT - PWM_X Initial Value - */ -#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK) - -#define PWM_CTRL2_PWM45_INIT_MASK (0x800U) -#define PWM_CTRL2_PWM45_INIT_SHIFT (11U) -/*! PWM45_INIT - PWM45 Initial Value - */ -#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK) - -#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U) -#define PWM_CTRL2_PWM23_INIT_SHIFT (12U) -/*! PWM23_INIT - PWM23 Initial Value - */ -#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK) - -#define PWM_CTRL2_INDEP_MASK (0x2000U) -#define PWM_CTRL2_INDEP_SHIFT (13U) -/*! INDEP - Independent or Complementary Pair Operation - * 0b0..PWM_A and PWM_B form a complementary PWM pair. - * 0b1..PWM_A and PWM_B outputs are independent PWMs. - */ -#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK) - -#define PWM_CTRL2_WAITEN_MASK (0x4000U) -#define PWM_CTRL2_WAITEN_SHIFT (14U) -/*! WAITEN - Sleep Enable - */ -#define PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK) - -#define PWM_CTRL2_DBGEN_MASK (0x8000U) -#define PWM_CTRL2_DBGEN_SHIFT (15U) -/*! DBGEN - Debug Enable - */ -#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK) -/*! @} */ - -/* The count of PWM_CTRL2 */ -#define PWM_CTRL2_COUNT (4U) - -/*! @name CTRL - Control Register */ -/*! @{ */ - -#define PWM_CTRL_DBLEN_MASK (0x1U) -#define PWM_CTRL_DBLEN_SHIFT (0U) -/*! DBLEN - Double Switching Enable - * 0b0..Double switching disabled. - * 0b1..Double switching enabled. - */ -#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK) - -#define PWM_CTRL_DBLX_MASK (0x2U) -#define PWM_CTRL_DBLX_SHIFT (1U) -/*! DBLX - PWMX Double Switching Enable - * 0b0..PWMX double pulse disabled. - * 0b1..PWMX double pulse enabled. - */ -#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK) - -#define PWM_CTRL_LDMOD_MASK (0x4U) -#define PWM_CTRL_LDMOD_SHIFT (2U) -/*! LDMOD - Load Mode Select - * 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. - * 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. - * In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. - */ -#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK) - -#define PWM_CTRL_SPLIT_MASK (0x8U) -#define PWM_CTRL_SPLIT_SHIFT (3U) -/*! SPLIT - Split the DBLPWM signal to PWMA and PWMB - * 0b0..DBLPWM is not split. PWMA and PWMB each have double pulses. - * 0b1..DBLPWM is split to PWMA and PWMB. - */ -#define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK) - -#define PWM_CTRL_PRSC_MASK (0x70U) -#define PWM_CTRL_PRSC_SHIFT (4U) -/*! PRSC - Prescaler - * 0b000..Prescaler 1 - * 0b001..Prescaler 2 - * 0b010..Prescaler 4 - * 0b011..Prescaler 8 - * 0b100..Prescaler 16 - * 0b101..Prescaler 32 - * 0b110..Prescaler 64 - * 0b111..Prescaler 128 - */ -#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK) - -#define PWM_CTRL_COMPMODE_MASK (0x80U) -#define PWM_CTRL_COMPMODE_SHIFT (7U) -/*! COMPMODE - Compare Mode - * 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges - * are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA - * output that is high at the end of a period will maintain this state until a match with VAL3 clears the - * output in the following period. - * 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This - * means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register - * values. This implies that a PWMA output that is high at the end of a period could go low at the start of the - * next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. - */ -#define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK) - -#define PWM_CTRL_DT_MASK (0x300U) -#define PWM_CTRL_DT_SHIFT (8U) -/*! DT - Deadtime - */ -#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK) - -#define PWM_CTRL_FULL_MASK (0x400U) -#define PWM_CTRL_FULL_SHIFT (10U) -/*! FULL - Full Cycle Reload - * 0b0..Full-cycle reloads disabled. - * 0b1..Full-cycle reloads enabled. - */ -#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK) - -#define PWM_CTRL_HALF_MASK (0x800U) -#define PWM_CTRL_HALF_SHIFT (11U) -/*! HALF - Half Cycle Reload - * 0b0..Half-cycle reloads disabled. - * 0b1..Half-cycle reloads enabled. - */ -#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK) - -#define PWM_CTRL_LDFQ_MASK (0xF000U) -#define PWM_CTRL_LDFQ_SHIFT (12U) -/*! LDFQ - Load Frequency - * 0b0000..Every PWM opportunity - * 0b0001..Every 2 PWM opportunities - * 0b0010..Every 3 PWM opportunities - * 0b0011..Every 4 PWM opportunities - * 0b0100..Every 5 PWM opportunities - * 0b0101..Every 6 PWM opportunities - * 0b0110..Every 7 PWM opportunities - * 0b0111..Every 8 PWM opportunities - * 0b1000..Every 9 PWM opportunities - * 0b1001..Every 10 PWM opportunities - * 0b1010..Every 11 PWM opportunities - * 0b1011..Every 12 PWM opportunities - * 0b1100..Every 13 PWM opportunities - * 0b1101..Every 14 PWM opportunities - * 0b1110..Every 15 PWM opportunities - * 0b1111..Every 16 PWM opportunities - */ -#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK) -/*! @} */ - -/* The count of PWM_CTRL */ -#define PWM_CTRL_COUNT (4U) - -/*! @name VAL0 - Value Register 0 */ -/*! @{ */ - -#define PWM_VAL0_VAL0_MASK (0xFFFFU) -#define PWM_VAL0_VAL0_SHIFT (0U) -/*! VAL0 - Value Register 0 - */ -#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK) -/*! @} */ - -/* The count of PWM_VAL0 */ -#define PWM_VAL0_COUNT (4U) - -/*! @name FRACVAL1 - Fractional Value Register 1 */ -/*! @{ */ - -#define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U) -#define PWM_FRACVAL1_FRACVAL1_SHIFT (11U) -/*! FRACVAL1 - Fractional Value 1 Register - */ -#define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK) -/*! @} */ - -/* The count of PWM_FRACVAL1 */ -#define PWM_FRACVAL1_COUNT (4U) - -/*! @name VAL1 - Value Register 1 */ -/*! @{ */ - -#define PWM_VAL1_VAL1_MASK (0xFFFFU) -#define PWM_VAL1_VAL1_SHIFT (0U) -/*! VAL1 - Value Register 1 - */ -#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK) -/*! @} */ - -/* The count of PWM_VAL1 */ -#define PWM_VAL1_COUNT (4U) - -/*! @name FRACVAL2 - Fractional Value Register 2 */ -/*! @{ */ - -#define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U) -#define PWM_FRACVAL2_FRACVAL2_SHIFT (11U) -/*! FRACVAL2 - Fractional Value 2 - */ -#define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK) -/*! @} */ - -/* The count of PWM_FRACVAL2 */ -#define PWM_FRACVAL2_COUNT (4U) - -/*! @name VAL2 - Value Register 2 */ -/*! @{ */ - -#define PWM_VAL2_VAL2_MASK (0xFFFFU) -#define PWM_VAL2_VAL2_SHIFT (0U) -/*! VAL2 - Value Register 2 - */ -#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK) -/*! @} */ - -/* The count of PWM_VAL2 */ -#define PWM_VAL2_COUNT (4U) - -/*! @name FRACVAL3 - Fractional Value Register 3 */ -/*! @{ */ - -#define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U) -#define PWM_FRACVAL3_FRACVAL3_SHIFT (11U) -/*! FRACVAL3 - Fractional Value 3 - */ -#define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK) -/*! @} */ - -/* The count of PWM_FRACVAL3 */ -#define PWM_FRACVAL3_COUNT (4U) - -/*! @name VAL3 - Value Register 3 */ -/*! @{ */ - -#define PWM_VAL3_VAL3_MASK (0xFFFFU) -#define PWM_VAL3_VAL3_SHIFT (0U) -/*! VAL3 - Value Register 3 - */ -#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK) -/*! @} */ - -/* The count of PWM_VAL3 */ -#define PWM_VAL3_COUNT (4U) - -/*! @name FRACVAL4 - Fractional Value Register 4 */ -/*! @{ */ - -#define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U) -#define PWM_FRACVAL4_FRACVAL4_SHIFT (11U) -/*! FRACVAL4 - Fractional Value 4 - */ -#define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK) -/*! @} */ - -/* The count of PWM_FRACVAL4 */ -#define PWM_FRACVAL4_COUNT (4U) - -/*! @name VAL4 - Value Register 4 */ -/*! @{ */ - -#define PWM_VAL4_VAL4_MASK (0xFFFFU) -#define PWM_VAL4_VAL4_SHIFT (0U) -/*! VAL4 - Value Register 4 - */ -#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK) -/*! @} */ - -/* The count of PWM_VAL4 */ -#define PWM_VAL4_COUNT (4U) - -/*! @name FRACVAL5 - Fractional Value Register 5 */ -/*! @{ */ - -#define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U) -#define PWM_FRACVAL5_FRACVAL5_SHIFT (11U) -/*! FRACVAL5 - Fractional Value 5 - */ -#define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK) -/*! @} */ - -/* The count of PWM_FRACVAL5 */ -#define PWM_FRACVAL5_COUNT (4U) - -/*! @name VAL5 - Value Register 5 */ -/*! @{ */ - -#define PWM_VAL5_VAL5_MASK (0xFFFFU) -#define PWM_VAL5_VAL5_SHIFT (0U) -/*! VAL5 - Value Register 5 - */ -#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK) -/*! @} */ - -/* The count of PWM_VAL5 */ -#define PWM_VAL5_COUNT (4U) - -/*! @name FRCTRL - Fractional Control Register */ -/*! @{ */ - -#define PWM_FRCTRL_FRAC1_EN_MASK (0x2U) -#define PWM_FRCTRL_FRAC1_EN_SHIFT (1U) -/*! FRAC1_EN - Fractional Cycle PWM Period Enable - * 0b0..Disable fractional cycle length for the PWM period. - * 0b1..Enable fractional cycle length for the PWM period. - */ -#define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK) - -#define PWM_FRCTRL_FRAC23_EN_MASK (0x4U) -#define PWM_FRCTRL_FRAC23_EN_SHIFT (2U) -/*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A - * 0b0..Disable fractional cycle placement for PWM_A. - * 0b1..Enable fractional cycle placement for PWM_A. - */ -#define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK) - -#define PWM_FRCTRL_FRAC45_EN_MASK (0x10U) -#define PWM_FRCTRL_FRAC45_EN_SHIFT (4U) -/*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B - * 0b0..Disable fractional cycle placement for PWM_B. - * 0b1..Enable fractional cycle placement for PWM_B. - */ -#define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK) - -#define PWM_FRCTRL_TEST_MASK (0x8000U) -#define PWM_FRCTRL_TEST_SHIFT (15U) -/*! TEST - Test Status Bit - */ -#define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK) -/*! @} */ - -/* The count of PWM_FRCTRL */ -#define PWM_FRCTRL_COUNT (4U) - -/*! @name OCTRL - Output Control Register */ -/*! @{ */ - -#define PWM_OCTRL_PWMXFS_MASK (0x3U) -#define PWM_OCTRL_PWMXFS_SHIFT (0U) -/*! PWMXFS - PWM_X Fault State - * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. - * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. - * 0b10, 0b11..Output is tristated. - */ -#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK) - -#define PWM_OCTRL_PWMBFS_MASK (0xCU) -#define PWM_OCTRL_PWMBFS_SHIFT (2U) -/*! PWMBFS - PWM_B Fault State - * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. - * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. - * 0b10, 0b11..Output is tristated. - */ -#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK) - -#define PWM_OCTRL_PWMAFS_MASK (0x30U) -#define PWM_OCTRL_PWMAFS_SHIFT (4U) -/*! PWMAFS - PWM_A Fault State - * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. - * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. - * 0b10, 0b11..Output is tristated. - */ -#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK) - -#define PWM_OCTRL_POLX_MASK (0x100U) -#define PWM_OCTRL_POLX_SHIFT (8U) -/*! POLX - PWM_X Output Polarity - * 0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. - * 0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. - */ -#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK) - -#define PWM_OCTRL_POLB_MASK (0x200U) -#define PWM_OCTRL_POLB_SHIFT (9U) -/*! POLB - PWM_B Output Polarity - * 0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. - * 0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. - */ -#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK) - -#define PWM_OCTRL_POLA_MASK (0x400U) -#define PWM_OCTRL_POLA_SHIFT (10U) -/*! POLA - PWM_A Output Polarity - * 0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. - * 0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. - */ -#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK) - -#define PWM_OCTRL_PWMX_IN_MASK (0x2000U) -#define PWM_OCTRL_PWMX_IN_SHIFT (13U) -/*! PWMX_IN - PWM_X Input - */ -#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK) - -#define PWM_OCTRL_PWMB_IN_MASK (0x4000U) -#define PWM_OCTRL_PWMB_IN_SHIFT (14U) -/*! PWMB_IN - PWM_B Input - */ -#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK) - -#define PWM_OCTRL_PWMA_IN_MASK (0x8000U) -#define PWM_OCTRL_PWMA_IN_SHIFT (15U) -/*! PWMA_IN - PWM_A Input - */ -#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK) -/*! @} */ - -/* The count of PWM_OCTRL */ -#define PWM_OCTRL_COUNT (4U) - -/*! @name STS - Status Register */ -/*! @{ */ - -#define PWM_STS_CMPF_MASK (0x3FU) -#define PWM_STS_CMPF_SHIFT (0U) -/*! CMPF - Compare Flags - * 0b000000..No compare event has occurred for a particular VALx value. - * 0b000001..A compare event has occurred for a particular VALx value. - */ -#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK) - -#define PWM_STS_CFX0_MASK (0x40U) -#define PWM_STS_CFX0_SHIFT (6U) -/*! CFX0 - Capture Flag X0 - */ -#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK) - -#define PWM_STS_CFX1_MASK (0x80U) -#define PWM_STS_CFX1_SHIFT (7U) -/*! CFX1 - Capture Flag X1 - */ -#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK) - -#define PWM_STS_CFB0_MASK (0x100U) -#define PWM_STS_CFB0_SHIFT (8U) -/*! CFB0 - Capture Flag B0 - */ -#define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK) - -#define PWM_STS_CFB1_MASK (0x200U) -#define PWM_STS_CFB1_SHIFT (9U) -/*! CFB1 - Capture Flag B1 - */ -#define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK) - -#define PWM_STS_CFA0_MASK (0x400U) -#define PWM_STS_CFA0_SHIFT (10U) -/*! CFA0 - Capture Flag A0 - */ -#define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK) - -#define PWM_STS_CFA1_MASK (0x800U) -#define PWM_STS_CFA1_SHIFT (11U) -/*! CFA1 - Capture Flag A1 - */ -#define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK) - -#define PWM_STS_RF_MASK (0x1000U) -#define PWM_STS_RF_SHIFT (12U) -/*! RF - Reload Flag - * 0b0..No new reload cycle since last STS[RF] clearing - * 0b1..New reload cycle since last STS[RF] clearing - */ -#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK) - -#define PWM_STS_REF_MASK (0x2000U) -#define PWM_STS_REF_SHIFT (13U) -/*! REF - Reload Error Flag - * 0b0..No reload error occurred. - * 0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. - */ -#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK) - -#define PWM_STS_RUF_MASK (0x4000U) -#define PWM_STS_RUF_SHIFT (14U) -/*! RUF - Registers Updated Flag - * 0b0..No register update has occurred since last reload. - * 0b1..At least one of the double buffered registers has been updated since the last reload. - */ -#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK) -/*! @} */ - -/* The count of PWM_STS */ -#define PWM_STS_COUNT (4U) - -/*! @name INTEN - Interrupt Enable Register */ -/*! @{ */ - -#define PWM_INTEN_CMPIE_MASK (0x3FU) -#define PWM_INTEN_CMPIE_SHIFT (0U) -/*! CMPIE - Compare Interrupt Enables - * 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request. - * 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request. - */ -#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) - -#define PWM_INTEN_CX0IE_MASK (0x40U) -#define PWM_INTEN_CX0IE_SHIFT (6U) -/*! CX0IE - Capture X 0 Interrupt Enable - * 0b0..Interrupt request disabled for STS[CFX0]. - * 0b1..Interrupt request enabled for STS[CFX0]. - */ -#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) - -#define PWM_INTEN_CX1IE_MASK (0x80U) -#define PWM_INTEN_CX1IE_SHIFT (7U) -/*! CX1IE - Capture X 1 Interrupt Enable - * 0b0..Interrupt request disabled for STS[CFX1]. - * 0b1..Interrupt request enabled for STS[CFX1]. - */ -#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) - -#define PWM_INTEN_CB0IE_MASK (0x100U) -#define PWM_INTEN_CB0IE_SHIFT (8U) -/*! CB0IE - Capture B 0 Interrupt Enable - * 0b0..Interrupt request disabled for STS[CFB0]. - * 0b1..Interrupt request enabled for STS[CFB0]. - */ -#define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) - -#define PWM_INTEN_CB1IE_MASK (0x200U) -#define PWM_INTEN_CB1IE_SHIFT (9U) -/*! CB1IE - Capture B 1 Interrupt Enable - * 0b0..Interrupt request disabled for STS[CFB1]. - * 0b1..Interrupt request enabled for STS[CFB1]. - */ -#define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) - -#define PWM_INTEN_CA0IE_MASK (0x400U) -#define PWM_INTEN_CA0IE_SHIFT (10U) -/*! CA0IE - Capture A 0 Interrupt Enable - * 0b0..Interrupt request disabled for STS[CFA0]. - * 0b1..Interrupt request enabled for STS[CFA0]. - */ -#define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) - -#define PWM_INTEN_CA1IE_MASK (0x800U) -#define PWM_INTEN_CA1IE_SHIFT (11U) -/*! CA1IE - Capture A 1 Interrupt Enable - * 0b0..Interrupt request disabled for STS[CFA1]. - * 0b1..Interrupt request enabled for STS[CFA1]. - */ -#define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) - -#define PWM_INTEN_RIE_MASK (0x1000U) -#define PWM_INTEN_RIE_SHIFT (12U) -/*! RIE - Reload Interrupt Enable - * 0b0..STS[RF] CPU interrupt requests disabled - * 0b1..STS[RF] CPU interrupt requests enabled - */ -#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) - -#define PWM_INTEN_REIE_MASK (0x2000U) -#define PWM_INTEN_REIE_SHIFT (13U) -/*! REIE - Reload Error Interrupt Enable - * 0b0..STS[REF] CPU interrupt requests disabled - * 0b1..STS[REF] CPU interrupt requests enabled - */ -#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) -/*! @} */ - -/* The count of PWM_INTEN */ -#define PWM_INTEN_COUNT (4U) - -/*! @name DMAEN - DMA Enable Register */ -/*! @{ */ - -#define PWM_DMAEN_CX0DE_MASK (0x1U) -#define PWM_DMAEN_CX0DE_SHIFT (0U) -/*! CX0DE - Capture X0 FIFO DMA Enable - */ -#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK) - -#define PWM_DMAEN_CX1DE_MASK (0x2U) -#define PWM_DMAEN_CX1DE_SHIFT (1U) -/*! CX1DE - Capture X1 FIFO DMA Enable - */ -#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK) - -#define PWM_DMAEN_CB0DE_MASK (0x4U) -#define PWM_DMAEN_CB0DE_SHIFT (2U) -/*! CB0DE - Capture B0 FIFO DMA Enable - */ -#define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK) - -#define PWM_DMAEN_CB1DE_MASK (0x8U) -#define PWM_DMAEN_CB1DE_SHIFT (3U) -/*! CB1DE - Capture B1 FIFO DMA Enable - */ -#define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK) - -#define PWM_DMAEN_CA0DE_MASK (0x10U) -#define PWM_DMAEN_CA0DE_SHIFT (4U) -/*! CA0DE - Capture A0 FIFO DMA Enable - */ -#define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK) - -#define PWM_DMAEN_CA1DE_MASK (0x20U) -#define PWM_DMAEN_CA1DE_SHIFT (5U) -/*! CA1DE - Capture A1 FIFO DMA Enable - */ -#define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK) - -#define PWM_DMAEN_CAPTDE_MASK (0xC0U) -#define PWM_DMAEN_CAPTDE_SHIFT (6U) -/*! CAPTDE - Capture DMA Enable Source Select - * 0b00..Read DMA requests disabled. - * 0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], - * DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to - * which watermark(s) the DMA request is sensitive. - * 0b10..A local sync (VAL1 matches counter) sets the read DMA request. - * 0b11..A local reload (STS[RF] being set) sets the read DMA request. - */ -#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK) - -#define PWM_DMAEN_FAND_MASK (0x100U) -#define PWM_DMAEN_FAND_SHIFT (8U) -/*! FAND - FIFO Watermark AND Control - * 0b0..Selected FIFO watermarks are OR'ed together. - * 0b1..Selected FIFO watermarks are AND'ed together. - */ -#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK) - -#define PWM_DMAEN_VALDE_MASK (0x200U) -#define PWM_DMAEN_VALDE_SHIFT (9U) -/*! VALDE - Value Registers DMA Enable - * 0b0..DMA write requests disabled - * 0b1..Enabled - */ -#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK) -/*! @} */ - -/* The count of PWM_DMAEN */ -#define PWM_DMAEN_COUNT (4U) - -/*! @name TCTRL - Output Trigger Control Register */ -/*! @{ */ - -#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU) -#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U) -/*! OUT_TRIG_EN - Output Trigger Enables - * 0bxxxxx1..PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value. - * 0bxxxx1x..PWM_OUT_TRIG1 will set when the counter value matches the VAL1 value. - * 0bxxx1xx..PWM_OUT_TRIG0 will set when the counter value matches the VAL2 value. - * 0bxx1xxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL3 value. - * 0bx1xxxx..PWM_OUT_TRIG0 will set when the counter value matches the VAL4 value. - * 0b1xxxxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL5 value. - */ -#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK) - -#define PWM_TCTRL_TRGFRQ_MASK (0x1000U) -#define PWM_TCTRL_TRGFRQ_SHIFT (12U) -/*! TRGFRQ - Trigger frequency - * 0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. - * 0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM - * is not reloaded every period due to CTRL[LDFQ] being non-zero. - */ -#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK) - -#define PWM_TCTRL_PWBOT1_MASK (0x4000U) -#define PWM_TCTRL_PWBOT1_SHIFT (14U) -/*! PWBOT1 - Mux Output Trigger 1 Source Select - * 0b0..Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port. - * 0b1..Route the PWMB output to the PWM_MUX_TRIG1 port. - */ -#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK) - -#define PWM_TCTRL_PWAOT0_MASK (0x8000U) -#define PWM_TCTRL_PWAOT0_SHIFT (15U) -/*! PWAOT0 - Mux Output Trigger 0 Source Select - * 0b0..Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port. - * 0b1..Route the PWMA output to the PWM_MUX_TRIG0 port. - */ -#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK) -/*! @} */ - -/* The count of PWM_TCTRL */ -#define PWM_TCTRL_COUNT (4U) - -/*! @name DISMAP - Fault Disable Mapping Register 0 */ -/*! @{ */ - -#define PWM_DISMAP_DIS0A_MASK (0xFU) -#define PWM_DISMAP_DIS0A_SHIFT (0U) -/*! DIS0A - PWM_A Fault Disable Mask 0 - */ -#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK) - -#define PWM_DISMAP_DIS0B_MASK (0xF0U) -#define PWM_DISMAP_DIS0B_SHIFT (4U) -/*! DIS0B - PWM_B Fault Disable Mask 0 - */ -#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK) - -#define PWM_DISMAP_DIS0X_MASK (0xF00U) -#define PWM_DISMAP_DIS0X_SHIFT (8U) -/*! DIS0X - PWM_X Fault Disable Mask 0 - */ -#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK) -/*! @} */ - -/* The count of PWM_DISMAP */ -#define PWM_DISMAP_COUNT (4U) - -/* The count of PWM_DISMAP */ -#define PWM_DISMAP_COUNT2 (1U) - -/*! @name DTCNT0 - Deadtime Count Register 0 */ -/*! @{ */ - -#define PWM_DTCNT0_DTCNT0_MASK (0x7FFU) -#define PWM_DTCNT0_DTCNT0_SHIFT (0U) -/*! DTCNT0 - Deadtime Count Register 0 - */ -#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK) -/*! @} */ - -/* The count of PWM_DTCNT0 */ -#define PWM_DTCNT0_COUNT (4U) - -/*! @name DTCNT1 - Deadtime Count Register 1 */ -/*! @{ */ - -#define PWM_DTCNT1_DTCNT1_MASK (0x7FFU) -#define PWM_DTCNT1_DTCNT1_SHIFT (0U) -/*! DTCNT1 - Deadtime Count Register 1 - */ -#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK) -/*! @} */ - -/* The count of PWM_DTCNT1 */ -#define PWM_DTCNT1_COUNT (4U) - -/*! @name CAPTCTRLA - Capture Control A Register */ -/*! @{ */ - -#define PWM_CAPTCTRLA_ARMA_MASK (0x1U) -#define PWM_CAPTCTRLA_ARMA_SHIFT (0U) -/*! ARMA - Arm A - * 0b0..Input capture operation is disabled. - * 0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. - */ -#define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK) - -#define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U) -#define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U) -/*! ONESHOTA - One Shot Mode A - * 0b0..Free Running - * 0b1..One Shot - */ -#define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK) - -#define PWM_CAPTCTRLA_EDGA0_MASK (0xCU) -#define PWM_CAPTCTRLA_EDGA0_SHIFT (2U) -/*! EDGA0 - Edge A 0 - * 0b00..Disabled - * 0b01..Capture falling edges - * 0b10..Capture rising edges - * 0b11..Capture any edge - */ -#define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK) - -#define PWM_CAPTCTRLA_EDGA1_MASK (0x30U) -#define PWM_CAPTCTRLA_EDGA1_SHIFT (4U) -/*! EDGA1 - Edge A 1 - * 0b00..Disabled - * 0b01..Capture falling edges - * 0b10..Capture rising edges - * 0b11..Capture any edge - */ -#define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK) - -#define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U) -#define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U) -/*! INP_SELA - Input Select A - * 0b0..Raw PWM_A input signal selected as source. - * 0b1..Edge Counter - */ -#define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK) - -#define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U) -#define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U) -/*! EDGCNTA_EN - Edge Counter A Enable - * 0b0..Edge counter disabled and held in reset - * 0b1..Edge counter enabled - */ -#define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK) - -#define PWM_CAPTCTRLA_CFAWM_MASK (0x300U) -#define PWM_CAPTCTRLA_CFAWM_SHIFT (8U) -/*! CFAWM - Capture A FIFOs Water Mark - */ -#define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK) - -#define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U) -#define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U) -/*! CA0CNT - Capture A0 FIFO Word Count - */ -#define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK) - -#define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U) -#define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U) -/*! CA1CNT - Capture A1 FIFO Word Count - */ -#define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK) -/*! @} */ - -/* The count of PWM_CAPTCTRLA */ -#define PWM_CAPTCTRLA_COUNT (4U) - -/*! @name CAPTCOMPA - Capture Compare A Register */ -/*! @{ */ - -#define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU) -#define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U) -/*! EDGCMPA - Edge Compare A - */ -#define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK) - -#define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U) -#define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U) -/*! EDGCNTA - Edge Counter A - */ -#define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK) -/*! @} */ - -/* The count of PWM_CAPTCOMPA */ -#define PWM_CAPTCOMPA_COUNT (4U) - -/*! @name CAPTCTRLB - Capture Control B Register */ -/*! @{ */ - -#define PWM_CAPTCTRLB_ARMB_MASK (0x1U) -#define PWM_CAPTCTRLB_ARMB_SHIFT (0U) -/*! ARMB - Arm B - * 0b0..Input capture operation is disabled. - * 0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. - */ -#define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK) - -#define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U) -#define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U) -/*! ONESHOTB - One Shot Mode B - * 0b0..Free Running - * 0b1..One Shot - */ -#define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK) - -#define PWM_CAPTCTRLB_EDGB0_MASK (0xCU) -#define PWM_CAPTCTRLB_EDGB0_SHIFT (2U) -/*! EDGB0 - Edge B 0 - * 0b00..Disabled - * 0b01..Capture falling edges - * 0b10..Capture rising edges - * 0b11..Capture any edge - */ -#define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK) - -#define PWM_CAPTCTRLB_EDGB1_MASK (0x30U) -#define PWM_CAPTCTRLB_EDGB1_SHIFT (4U) -/*! EDGB1 - Edge B 1 - * 0b00..Disabled - * 0b01..Capture falling edges - * 0b10..Capture rising edges - * 0b11..Capture any edge - */ -#define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK) - -#define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U) -#define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U) -/*! INP_SELB - Input Select B - * 0b0..Raw PWM_B input signal selected as source. - * 0b1..Edge Counter - */ -#define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK) - -#define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U) -#define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U) -/*! EDGCNTB_EN - Edge Counter B Enable - * 0b0..Edge counter disabled and held in reset - * 0b1..Edge counter enabled - */ -#define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK) - -#define PWM_CAPTCTRLB_CFBWM_MASK (0x300U) -#define PWM_CAPTCTRLB_CFBWM_SHIFT (8U) -/*! CFBWM - Capture B FIFOs Water Mark - */ -#define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK) - -#define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U) -#define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U) -/*! CB0CNT - Capture B0 FIFO Word Count - */ -#define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK) - -#define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U) -#define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U) -/*! CB1CNT - Capture B1 FIFO Word Count - */ -#define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK) -/*! @} */ - -/* The count of PWM_CAPTCTRLB */ -#define PWM_CAPTCTRLB_COUNT (4U) - -/*! @name CAPTCOMPB - Capture Compare B Register */ -/*! @{ */ - -#define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU) -#define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U) -/*! EDGCMPB - Edge Compare B - */ -#define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK) - -#define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U) -#define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U) -/*! EDGCNTB - Edge Counter B - */ -#define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK) -/*! @} */ - -/* The count of PWM_CAPTCOMPB */ -#define PWM_CAPTCOMPB_COUNT (4U) - -/*! @name CAPTCTRLX - Capture Control X Register */ -/*! @{ */ - -#define PWM_CAPTCTRLX_ARMX_MASK (0x1U) -#define PWM_CAPTCTRLX_ARMX_SHIFT (0U) -/*! ARMX - Arm X - * 0b0..Input capture operation is disabled. - * 0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. - */ -#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) - -#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U) -#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U) -/*! ONESHOTX - One Shot Mode Aux - * 0b0..Free Running - * 0b1..One Shot - */ -#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK) - -#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU) -#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U) -/*! EDGX0 - Edge X 0 - * 0b00..Disabled - * 0b01..Capture falling edges - * 0b10..Capture rising edges - * 0b11..Capture any edge - */ -#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK) - -#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U) -#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U) -/*! EDGX1 - Edge X 1 - * 0b00..Disabled - * 0b01..Capture falling edges - * 0b10..Capture rising edges - * 0b11..Capture any edge - */ -#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK) - -#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U) -#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U) -/*! INP_SELX - Input Select X - * 0b0..Raw PWM_X input signal selected as source. - * 0b1..Edge Counter - */ -#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK) - -#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U) -#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U) -/*! EDGCNTX_EN - Edge Counter X Enable - * 0b0..Edge counter disabled and held in reset - * 0b1..Edge counter enabled - */ -#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK) - -#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U) -#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U) -/*! CFXWM - Capture X FIFOs Water Mark - */ -#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK) - -#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U) -#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U) -/*! CX0CNT - Capture X0 FIFO Word Count - */ -#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK) - -#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U) -#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U) -/*! CX1CNT - Capture X1 FIFO Word Count - */ -#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK) -/*! @} */ - -/* The count of PWM_CAPTCTRLX */ -#define PWM_CAPTCTRLX_COUNT (4U) - -/*! @name CAPTCOMPX - Capture Compare X Register */ -/*! @{ */ - -#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU) -#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U) -/*! EDGCMPX - Edge Compare X - */ -#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK) - -#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U) -#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U) -/*! EDGCNTX - Edge Counter X - */ -#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK) -/*! @} */ - -/* The count of PWM_CAPTCOMPX */ -#define PWM_CAPTCOMPX_COUNT (4U) - -/*! @name CVAL0 - Capture Value 0 Register */ -/*! @{ */ - -#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU) -#define PWM_CVAL0_CAPTVAL0_SHIFT (0U) -/*! CAPTVAL0 - CAPTVAL0 - */ -#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK) -/*! @} */ - -/* The count of PWM_CVAL0 */ -#define PWM_CVAL0_COUNT (4U) - -/*! @name CVAL0CYC - Capture Value 0 Cycle Register */ -/*! @{ */ - -#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU) -#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U) -/*! CVAL0CYC - CVAL0CYC - */ -#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK) -/*! @} */ - -/* The count of PWM_CVAL0CYC */ -#define PWM_CVAL0CYC_COUNT (4U) - -/*! @name CVAL1 - Capture Value 1 Register */ -/*! @{ */ - -#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU) -#define PWM_CVAL1_CAPTVAL1_SHIFT (0U) -/*! CAPTVAL1 - CAPTVAL1 - */ -#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK) -/*! @} */ - -/* The count of PWM_CVAL1 */ -#define PWM_CVAL1_COUNT (4U) - -/*! @name CVAL1CYC - Capture Value 1 Cycle Register */ -/*! @{ */ - -#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU) -#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U) -/*! CVAL1CYC - CVAL1CYC - */ -#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK) -/*! @} */ - -/* The count of PWM_CVAL1CYC */ -#define PWM_CVAL1CYC_COUNT (4U) - -/*! @name CVAL2 - Capture Value 2 Register */ -/*! @{ */ - -#define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU) -#define PWM_CVAL2_CAPTVAL2_SHIFT (0U) -/*! CAPTVAL2 - CAPTVAL2 - */ -#define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK) -/*! @} */ - -/* The count of PWM_CVAL2 */ -#define PWM_CVAL2_COUNT (4U) - -/*! @name CVAL2CYC - Capture Value 2 Cycle Register */ -/*! @{ */ - -#define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU) -#define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U) -/*! CVAL2CYC - CVAL2CYC - */ -#define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK) -/*! @} */ - -/* The count of PWM_CVAL2CYC */ -#define PWM_CVAL2CYC_COUNT (4U) - -/*! @name CVAL3 - Capture Value 3 Register */ -/*! @{ */ - -#define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU) -#define PWM_CVAL3_CAPTVAL3_SHIFT (0U) -/*! CAPTVAL3 - CAPTVAL3 - */ -#define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK) -/*! @} */ - -/* The count of PWM_CVAL3 */ -#define PWM_CVAL3_COUNT (4U) - -/*! @name CVAL3CYC - Capture Value 3 Cycle Register */ -/*! @{ */ - -#define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU) -#define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U) -/*! CVAL3CYC - CVAL3CYC - */ -#define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK) -/*! @} */ - -/* The count of PWM_CVAL3CYC */ -#define PWM_CVAL3CYC_COUNT (4U) - -/*! @name CVAL4 - Capture Value 4 Register */ -/*! @{ */ - -#define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU) -#define PWM_CVAL4_CAPTVAL4_SHIFT (0U) -/*! CAPTVAL4 - CAPTVAL4 - */ -#define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK) -/*! @} */ - -/* The count of PWM_CVAL4 */ -#define PWM_CVAL4_COUNT (4U) - -/*! @name CVAL4CYC - Capture Value 4 Cycle Register */ -/*! @{ */ - -#define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU) -#define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U) -/*! CVAL4CYC - CVAL4CYC - */ -#define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK) -/*! @} */ - -/* The count of PWM_CVAL4CYC */ -#define PWM_CVAL4CYC_COUNT (4U) - -/*! @name CVAL5 - Capture Value 5 Register */ -/*! @{ */ - -#define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU) -#define PWM_CVAL5_CAPTVAL5_SHIFT (0U) -/*! CAPTVAL5 - CAPTVAL5 - */ -#define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK) -/*! @} */ - -/* The count of PWM_CVAL5 */ -#define PWM_CVAL5_COUNT (4U) - -/*! @name CVAL5CYC - Capture Value 5 Cycle Register */ -/*! @{ */ - -#define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU) -#define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U) -/*! CVAL5CYC - CVAL5CYC - */ -#define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK) -/*! @} */ - -/* The count of PWM_CVAL5CYC */ -#define PWM_CVAL5CYC_COUNT (4U) - -/*! @name PHASEDLY - Phase Delay Register */ -/*! @{ */ - -#define PWM_PHASEDLY_PHASEDLY_MASK (0xFFFFU) -#define PWM_PHASEDLY_PHASEDLY_SHIFT (0U) -/*! PHASEDLY - Initial Count Register Bits - */ -#define PWM_PHASEDLY_PHASEDLY(x) (((uint16_t)(((uint16_t)(x)) << PWM_PHASEDLY_PHASEDLY_SHIFT)) & PWM_PHASEDLY_PHASEDLY_MASK) -/*! @} */ - -/* The count of PWM_PHASEDLY */ -#define PWM_PHASEDLY_COUNT (4U) - -/*! @name CAPTFILTA - Capture PWMA Input Filter Register */ -/*! @{ */ - -#define PWM_CAPTFILTA_CAPTA_FILT_PER_MASK (0xFFU) -#define PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT (0U) -/*! CAPTA_FILT_PER - Fault Filter Period - */ -#define PWM_CAPTFILTA_CAPTA_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_PER_MASK) - -#define PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK (0x700U) -#define PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT (8U) -/*! CAPTA_FILT_CNT - Fault Filter Count - */ -#define PWM_CAPTFILTA_CAPTA_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK) -/*! @} */ - -/* The count of PWM_CAPTFILTA */ -#define PWM_CAPTFILTA_COUNT (4U) - -/*! @name CAPTFILTB - Capture PWMB Input Filter Register */ -/*! @{ */ - -#define PWM_CAPTFILTB_CAPTB_FILT_PER_MASK (0xFFU) -#define PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT (0U) -/*! CAPTB_FILT_PER - Fault Filter Period - */ -#define PWM_CAPTFILTB_CAPTB_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_PER_MASK) - -#define PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK (0x700U) -#define PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT (8U) -/*! CAPTB_FILT_CNT - Fault Filter Count - */ -#define PWM_CAPTFILTB_CAPTB_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK) -/*! @} */ - -/* The count of PWM_CAPTFILTB */ -#define PWM_CAPTFILTB_COUNT (4U) - -/*! @name CAPTFILTX - Capture PWMX Input Filter Register */ -/*! @{ */ - -#define PWM_CAPTFILTX_CAPTX_FILT_PER_MASK (0xFFU) -#define PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT (0U) -/*! CAPTX_FILT_PER - Fault Filter Period - */ -#define PWM_CAPTFILTX_CAPTX_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_PER_MASK) - -#define PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK (0x700U) -#define PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT (8U) -/*! CAPTX_FILT_CNT - Fault Filter Count - */ -#define PWM_CAPTFILTX_CAPTX_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK) -/*! @} */ - -/* The count of PWM_CAPTFILTX */ -#define PWM_CAPTFILTX_COUNT (4U) - -/*! @name OUTEN - Output Enable Register */ -/*! @{ */ - -#define PWM_OUTEN_PWMX_EN_MASK (0xFU) -#define PWM_OUTEN_PWMX_EN_SHIFT (0U) -/*! PWMX_EN - PWM_X Output Enables - * 0b0000..PWM_X output disabled. - * 0b0001..PWM_X output enabled. - */ -#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) - -#define PWM_OUTEN_PWMB_EN_MASK (0xF0U) -#define PWM_OUTEN_PWMB_EN_SHIFT (4U) -/*! PWMB_EN - PWM_B Output Enables - * 0b0000..PWM_B output disabled. - * 0b0001..PWM_B output enabled. - */ -#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK) - -#define PWM_OUTEN_PWMA_EN_MASK (0xF00U) -#define PWM_OUTEN_PWMA_EN_SHIFT (8U) -/*! PWMA_EN - PWM_A Output Enables - * 0b0000..PWM_A output disabled. - * 0b0001..PWM_A output enabled. - */ -#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK) -/*! @} */ - -/*! @name MASK - Mask Register */ -/*! @{ */ - -#define PWM_MASK_MASKX_MASK (0xFU) -#define PWM_MASK_MASKX_SHIFT (0U) -/*! MASKX - PWM_X Masks - * 0b0000..PWM_X output normal. - * 0b0001..PWM_X output masked. - */ -#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) - -#define PWM_MASK_MASKB_MASK (0xF0U) -#define PWM_MASK_MASKB_SHIFT (4U) -/*! MASKB - PWM_B Masks - * 0b0000..PWM_B output normal. - * 0b0001..PWM_B output masked. - */ -#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK) - -#define PWM_MASK_MASKA_MASK (0xF00U) -#define PWM_MASK_MASKA_SHIFT (8U) -/*! MASKA - PWM_A Masks - * 0b0000..PWM_A output normal. - * 0b0001..PWM_A output masked. - */ -#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK) - -#define PWM_MASK_UPDATE_MASK_MASK (0xF000U) -#define PWM_MASK_UPDATE_MASK_SHIFT (12U) -/*! UPDATE_MASK - Update Mask Bits Immediately - * 0b0000..Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule. - * 0b0001..Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit. - */ -#define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK) -/*! @} */ - -/*! @name SWCOUT - Software Controlled Output Register */ -/*! @{ */ - -#define PWM_SWCOUT_SM0OUT45_MASK (0x1U) -#define PWM_SWCOUT_SM0OUT45_SHIFT (0U) -/*! SM0OUT45 - Submodule 0 Software Controlled Output 45 - * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. - * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. - */ -#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK) - -#define PWM_SWCOUT_SM0OUT23_MASK (0x2U) -#define PWM_SWCOUT_SM0OUT23_SHIFT (1U) -/*! SM0OUT23 - Submodule 0 Software Controlled Output 23 - * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. - * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. - */ -#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK) - -#define PWM_SWCOUT_SM1OUT45_MASK (0x4U) -#define PWM_SWCOUT_SM1OUT45_SHIFT (2U) -/*! SM1OUT45 - Submodule 1 Software Controlled Output 45 - * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. - * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. - */ -#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK) - -#define PWM_SWCOUT_SM1OUT23_MASK (0x8U) -#define PWM_SWCOUT_SM1OUT23_SHIFT (3U) -/*! SM1OUT23 - Submodule 1 Software Controlled Output 23 - * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. - * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. - */ -#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK) - -#define PWM_SWCOUT_SM2OUT45_MASK (0x10U) -#define PWM_SWCOUT_SM2OUT45_SHIFT (4U) -/*! SM2OUT45 - Submodule 2 Software Controlled Output 45 - * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. - * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. - */ -#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK) - -#define PWM_SWCOUT_SM2OUT23_MASK (0x20U) -#define PWM_SWCOUT_SM2OUT23_SHIFT (5U) -/*! SM2OUT23 - Submodule 2 Software Controlled Output 23 - * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. - * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. - */ -#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK) - -#define PWM_SWCOUT_SM3OUT45_MASK (0x40U) -#define PWM_SWCOUT_SM3OUT45_SHIFT (6U) -/*! SM3OUT45 - Submodule 3 Software Controlled Output 45 - * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. - * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. - */ -#define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK) - -#define PWM_SWCOUT_SM3OUT23_MASK (0x80U) -#define PWM_SWCOUT_SM3OUT23_SHIFT (7U) -/*! SM3OUT23 - Submodule 3 Software Controlled Output 23 - * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. - * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. - */ -#define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK) -/*! @} */ - -/*! @name DTSRCSEL - PWM Source Select Register */ -/*! @{ */ - -#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U) -#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U) -/*! SM0SEL45 - Submodule 0 PWM45 Control Select - * 0b00..Generated SM0PWM45 signal is used by the deadtime logic. - * 0b01..Inverted generated SM0PWM45 signal is used by the deadtime logic. - * 0b10..SWCOUT[SM0OUT45] is used by the deadtime logic. - * 0b11..PWM0_EXTB signal is used by the deadtime logic. - */ -#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) - -#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU) -#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U) -/*! SM0SEL23 - Submodule 0 PWM23 Control Select - * 0b00..Generated SM0PWM23 signal is used by the deadtime logic. - * 0b01..Inverted generated SM0PWM23 signal is used by the deadtime logic. - * 0b10..SWCOUT[SM0OUT23] is used by the deadtime logic. - * 0b11..PWM0_EXTA signal is used by the deadtime logic. - */ -#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK) - -#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U) -#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U) -/*! SM1SEL45 - Submodule 1 PWM45 Control Select - * 0b00..Generated SM1PWM45 signal is used by the deadtime logic. - * 0b01..Inverted generated SM1PWM45 signal is used by the deadtime logic. - * 0b10..SWCOUT[SM1OUT45] is used by the deadtime logic. - * 0b11..PWM1_EXTB signal is used by the deadtime logic. - */ -#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK) - -#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U) -#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U) -/*! SM1SEL23 - Submodule 1 PWM23 Control Select - * 0b00..Generated SM1PWM23 signal is used by the deadtime logic. - * 0b01..Inverted generated SM1PWM23 signal is used by the deadtime logic. - * 0b10..SWCOUT[SM1OUT23] is used by the deadtime logic. - * 0b11..PWM1_EXTA signal is used by the deadtime logic. - */ -#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK) - -#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U) -#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U) -/*! SM2SEL45 - Submodule 2 PWM45 Control Select - * 0b00..Generated SM2PWM45 signal is used by the deadtime logic. - * 0b01..Inverted generated SM2PWM45 signal is used by the deadtime logic. - * 0b10..SWCOUT[SM2OUT45] is used by the deadtime logic. - * 0b11..PWM2_EXTB signal is used by the deadtime logic. - */ -#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK) - -#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U) -#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U) -/*! SM2SEL23 - Submodule 2 PWM23 Control Select - * 0b00..Generated SM2PWM23 signal is used by the deadtime logic. - * 0b01..Inverted generated SM2PWM23 signal is used by the deadtime logic. - * 0b10..SWCOUT[SM2OUT23] is used by the deadtime logic. - * 0b11..PWM2_EXTA signal is used by the deadtime logic. - */ -#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK) - -#define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U) -#define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U) -/*! SM3SEL45 - Submodule 3 PWM45 Control Select - * 0b00..Generated SM3PWM45 signal is used by the deadtime logic. - * 0b01..Inverted generated SM3PWM45 signal is used by the deadtime logic. - * 0b10..SWCOUT[SM3OUT45] is used by the deadtime logic. - * 0b11..PWM3_EXTB signal is used by the deadtime logic. - */ -#define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK) - -#define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U) -#define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U) -/*! SM3SEL23 - Submodule 3 PWM23 Control Select - * 0b00..Generated SM3PWM23 signal is used by the deadtime logic. - * 0b01..Inverted generated SM3PWM23 signal is used by the deadtime logic. - * 0b10..SWCOUT[SM3OUT23] is used by the deadtime logic. - * 0b11..PWM3_EXTA signal is used by the deadtime logic. - */ -#define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK) -/*! @} */ - -/*! @name MCTRL - Master Control Register */ -/*! @{ */ - -#define PWM_MCTRL_LDOK_MASK (0xFU) -#define PWM_MCTRL_LDOK_SHIFT (0U) -/*! LDOK - Load Okay - * 0b0000..Do not load new values. - * 0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule. - */ -#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK) - -#define PWM_MCTRL_CLDOK_MASK (0xF0U) -#define PWM_MCTRL_CLDOK_SHIFT (4U) -/*! CLDOK - Clear Load Okay - */ -#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK) - -#define PWM_MCTRL_RUN_MASK (0xF00U) -#define PWM_MCTRL_RUN_SHIFT (8U) -/*! RUN - Run - * 0b0000..PWM counter is stopped, but PWM outputs will hold the current state. - * 0b0001..PWM counter is started in the corresponding submodule. - */ -#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK) - -#define PWM_MCTRL_IPOL_MASK (0xF000U) -#define PWM_MCTRL_IPOL_SHIFT (12U) -/*! IPOL - Current Polarity - * 0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule. - * 0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule. - */ -#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK) -/*! @} */ - -/*! @name MCTRL2 - Master Control 2 Register */ -/*! @{ */ - -#define PWM_MCTRL2_MONPLL_MASK (0x3U) -#define PWM_MCTRL2_MONPLL_SHIFT (0U) -/*! MONPLL - Monitor PLL State - * 0b00..Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. - * 0b01..Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. - * 0b10..Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock - * will be controlled by software. These bits are write protected until the next reset. - * 0b11..Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL - * encounters problems. These bits are write protected until the next reset. - */ -#define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK) -/*! @} */ - -/*! @name FCTRL - Fault Control Register */ -/*! @{ */ - -#define PWM_FCTRL_FIE_MASK (0xFU) -#define PWM_FCTRL_FIE_SHIFT (0U) -/*! FIE - Fault Interrupt Enables - * 0b0000..FAULTx CPU interrupt requests disabled. - * 0b0001..FAULTx CPU interrupt requests enabled. - */ -#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK) - -#define PWM_FCTRL_FSAFE_MASK (0xF0U) -#define PWM_FCTRL_FSAFE_SHIFT (4U) -/*! FSAFE - Fault Safety Mode - * 0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the - * start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard - * to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set then the fault condition cannot be - * cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input - * signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in - * DISMAPn). - * 0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and - * FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and - * FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared. - */ -#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK) - -#define PWM_FCTRL_FAUTO_MASK (0xF00U) -#define PWM_FCTRL_FAUTO_SHIFT (8U) -/*! FAUTO - Automatic Fault Clearing - * 0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear - * at the start of a half cycle or full cycle depending the states of FSTS[FHALF] and FSTS[FFULL]. If - * neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by - * FCTRL[FSAFE]. - * 0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at - * the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without - * regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition - * cannot be cleared. - */ -#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK) - -#define PWM_FCTRL_FLVL_MASK (0xF000U) -#define PWM_FCTRL_FLVL_SHIFT (12U) -/*! FLVL - Fault Level - * 0b0000..A logic 0 on the fault input indicates a fault condition. - * 0b0001..A logic 1 on the fault input indicates a fault condition. - */ -#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK) -/*! @} */ - -/*! @name FSTS - Fault Status Register */ -/*! @{ */ - -#define PWM_FSTS_FFLAG_MASK (0xFU) -#define PWM_FSTS_FFLAG_SHIFT (0U) -/*! FFLAG - Fault Flags - * 0b0000..No fault on the FAULTx pin. - * 0b0001..Fault on the FAULTx pin. - */ -#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK) - -#define PWM_FSTS_FFULL_MASK (0xF0U) -#define PWM_FSTS_FFULL_SHIFT (4U) -/*! FFULL - Full Cycle - * 0b0000..PWM outputs are not re-enabled at the start of a full cycle - * 0b0001..PWM outputs are re-enabled at the start of a full cycle - */ -#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK) - -#define PWM_FSTS_FFPIN_MASK (0xF00U) -#define PWM_FSTS_FFPIN_SHIFT (8U) -/*! FFPIN - Filtered Fault Pins - */ -#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK) - -#define PWM_FSTS_FHALF_MASK (0xF000U) -#define PWM_FSTS_FHALF_SHIFT (12U) -/*! FHALF - Half Cycle Fault Recovery - * 0b0000..PWM outputs are not re-enabled at the start of a half cycle. - * 0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). - */ -#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK) -/*! @} */ - -/*! @name FFILT - Fault Filter Register */ -/*! @{ */ - -#define PWM_FFILT_FILT_PER_MASK (0xFFU) -#define PWM_FFILT_FILT_PER_SHIFT (0U) -/*! FILT_PER - Fault Filter Period - */ -#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK) - -#define PWM_FFILT_FILT_CNT_MASK (0x700U) -#define PWM_FFILT_FILT_CNT_SHIFT (8U) -/*! FILT_CNT - Fault Filter Count - */ -#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK) - -#define PWM_FFILT_GSTR_MASK (0x8000U) -#define PWM_FFILT_GSTR_SHIFT (15U) -/*! GSTR - Fault Glitch Stretch Enable - * 0b0..Fault input glitch stretching is disabled. - * 0b1..Input fault signals will be stretched to at least 2 IPBus clock cycles. - */ -#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK) -/*! @} */ - -/*! @name FTST - Fault Test Register */ -/*! @{ */ - -#define PWM_FTST_FTEST_MASK (0x1U) -#define PWM_FTST_FTEST_SHIFT (0U) -/*! FTEST - Fault Test - * 0b0..No fault - * 0b1..Cause a simulated fault - */ -#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK) -/*! @} */ - -/*! @name FCTRL2 - Fault Control 2 Register */ -/*! @{ */ - -#define PWM_FCTRL2_NOCOMB_MASK (0xFU) -#define PWM_FCTRL2_NOCOMB_SHIFT (0U) -/*! NOCOMB - No Combinational Path From Fault Input To PWM Output - * 0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined - * with the filtered and latched fault signals to disable the PWM outputs. - * 0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered - * and latched fault signals are used to disable the PWM outputs. - */ -#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PWM_Register_Masks */ - - -/* PWM - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PWM0 base address */ - #define PWM0_BASE (0x500C3000u) - /** Peripheral PWM0 base address */ - #define PWM0_BASE_NS (0x400C3000u) - /** Peripheral PWM0 base pointer */ - #define PWM0 ((PWM_Type *)PWM0_BASE) - /** Peripheral PWM0 base pointer */ - #define PWM0_NS ((PWM_Type *)PWM0_BASE_NS) - /** Peripheral PWM1 base address */ - #define PWM1_BASE (0x500C5000u) - /** Peripheral PWM1 base address */ - #define PWM1_BASE_NS (0x400C5000u) - /** Peripheral PWM1 base pointer */ - #define PWM1 ((PWM_Type *)PWM1_BASE) - /** Peripheral PWM1 base pointer */ - #define PWM1_NS ((PWM_Type *)PWM1_BASE_NS) - /** Array initializer of PWM peripheral base addresses */ - #define PWM_BASE_ADDRS { PWM0_BASE, PWM1_BASE } - /** Array initializer of PWM peripheral base pointers */ - #define PWM_BASE_PTRS { PWM0, PWM1 } - /** Array initializer of PWM peripheral base addresses */ - #define PWM_BASE_ADDRS_NS { PWM0_BASE_NS, PWM1_BASE_NS } - /** Array initializer of PWM peripheral base pointers */ - #define PWM_BASE_PTRS_NS { PWM0_NS, PWM1_NS } -#else - /** Peripheral PWM0 base address */ - #define PWM0_BASE (0x400C3000u) - /** Peripheral PWM0 base pointer */ - #define PWM0 ((PWM_Type *)PWM0_BASE) - /** Peripheral PWM1 base address */ - #define PWM1_BASE (0x400C5000u) - /** Peripheral PWM1 base pointer */ - #define PWM1 ((PWM_Type *)PWM1_BASE) - /** Array initializer of PWM peripheral base addresses */ - #define PWM_BASE_ADDRS { PWM0_BASE, PWM1_BASE } - /** Array initializer of PWM peripheral base pointers */ - #define PWM_BASE_PTRS { PWM0, PWM1 } -#endif -/** Interrupt vectors for the PWM peripheral type */ -#define PWM_CMP_IRQS { { FLEXPWM0_COMPARE0_IRQn, FLEXPWM0_COMPARE1_IRQn, FLEXPWM0_COMPARE2_IRQn, FLEXPWM0_COMPARE3_IRQn }, { FLEXPWM1_COMPARE0_IRQn, FLEXPWM1_COMPARE1_IRQn, FLEXPWM1_COMPARE2_IRQn, FLEXPWM1_COMPARE3_IRQn } } -#define PWM_RELOAD_IRQS { { FLEXPWM0_RELOAD0_IRQn, FLEXPWM0_RELOAD1_IRQn, FLEXPWM0_RELOAD2_IRQn, FLEXPWM0_RELOAD3_IRQn }, { FLEXPWM1_RELOAD0_IRQn, FLEXPWM1_RELOAD1_IRQn, FLEXPWM1_RELOAD2_IRQn, FLEXPWM1_RELOAD3_IRQn } } -#define PWM_CAPTURE_IRQS { { FLEXPWM0_CAPTURE_IRQn, FLEXPWM0_CAPTURE_IRQn, FLEXPWM0_CAPTURE_IRQn, FLEXPWM0_CAPTURE_IRQn }, { FLEXPWM1_CAPTURE_IRQn, FLEXPWM1_CAPTURE_IRQn, FLEXPWM1_CAPTURE_IRQn, FLEXPWM1_CAPTURE_IRQn } } -#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn, FLEXPWM1_FAULT_IRQn } - -/*! - * @} - */ /* end of group PWM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RTC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer - * @{ - */ - -/** RTC - Register Layout Typedef */ -typedef struct { - __IO uint16_t YEARMON; /**< Year and Month Counters, offset: 0x0 */ - __IO uint16_t DAYS; /**< Days and Day-of-Week Counters, offset: 0x2 */ - __IO uint16_t HOURMIN; /**< Hours and Minutes Counters, offset: 0x4 */ - __IO uint16_t SECONDS; /**< Seconds Counters, offset: 0x6 */ - __IO uint16_t ALM_YEARMON; /**< Year and Months Alarm, offset: 0x8 */ - __IO uint16_t ALM_DAYS; /**< Days Alarm, offset: 0xA */ - __IO uint16_t ALM_HOURMIN; /**< Hours and Minutes Alarm, offset: 0xC */ - __IO uint16_t ALM_SECONDS; /**< Seconds Alarm, offset: 0xE */ - __IO uint16_t CTRL; /**< Control, offset: 0x10 */ - __IO uint16_t STATUS; /**< Status, offset: 0x12 */ - __IO uint16_t ISR; /**< Interrupt Status, offset: 0x14 */ - __IO uint16_t IER; /**< Interrupt Enable, offset: 0x16 */ - uint8_t RESERVED_0[8]; - __IO uint16_t GP_DATA_REG; /**< General Purpose Data, offset: 0x20 */ - __IO uint16_t DST_HOUR; /**< Daylight Saving Hour, offset: 0x22 */ - __IO uint16_t DST_MONTH; /**< Daylight Saving Month, offset: 0x24 */ - __IO uint16_t DST_DAY; /**< Daylight Saving Day, offset: 0x26 */ - __IO uint16_t COMPEN; /**< Compensation, offset: 0x28 */ - uint8_t RESERVED_1[4]; - __IO uint16_t TAMPER_QSCR; /**< Tamper Queue Status and Control, offset: 0x2E */ - uint8_t RESERVED_2[2]; - __IO uint16_t TAMPER_SCR; /**< Tamper Status and Control, offset: 0x32 */ - __IO uint16_t FILTER01_CFG; /**< Tamper 01 Filter Configuration, offset: 0x34 */ - __IO uint16_t FILTER23_CFG; /**< Tamper 23 Filter Configuration, offset: 0x36 */ - uint8_t RESERVED_3[8]; - __I uint16_t TAMPER_QUEUE; /**< Tamper Queue, offset: 0x40 */ - __IO uint16_t CTRL2; /**< Control 2, offset: 0x42 */ - uint8_t RESERVED_4[1980]; - __IO uint32_t SUBSECOND_CTRL; /**< Sub-second control, offset: 0x800 */ - __I uint32_t SUBSECOND_CNT; /**< Sub-second counter, offset: 0x804 */ - uint8_t RESERVED_5[1016]; - __IO uint32_t WAKE_TIMER_CTRL; /**< Wake timer control, offset: 0xC00 */ - uint8_t RESERVED_6[8]; - __IO uint32_t WAKE_TIMER_CNT; /**< Wake timer counter, offset: 0xC0C */ -} RTC_Type; - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/*! @name YEARMON - Year and Month Counters */ -/*! @{ */ - -#define RTC_YEARMON_MON_CNT_MASK (0xFU) -#define RTC_YEARMON_MON_CNT_SHIFT (0U) -/*! MON_CNT - Month Counter - * 0b0000, 0b1101, 0b1110, 0b1111..Illegal Value - * 0b0001..January - * 0b0010..February - * 0b0011..March - * 0b0100..April - * 0b0101..May - * 0b0110..June - * 0b0111..July - * 0b1000..August - * 0b1001..September - * 0b1010..October - * 0b1011..November - * 0b1100..December - */ -#define RTC_YEARMON_MON_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_YEARMON_MON_CNT_SHIFT)) & RTC_YEARMON_MON_CNT_MASK) - -#define RTC_YEARMON_YROFST_MASK (0xFF00U) -#define RTC_YEARMON_YROFST_SHIFT (8U) -/*! YROFST - Year Offset Count Value - */ -#define RTC_YEARMON_YROFST(x) (((uint16_t)(((uint16_t)(x)) << RTC_YEARMON_YROFST_SHIFT)) & RTC_YEARMON_YROFST_MASK) -/*! @} */ - -/*! @name DAYS - Days and Day-of-Week Counters */ -/*! @{ */ - -#define RTC_DAYS_DAY_CNT_MASK (0x1FU) -#define RTC_DAYS_DAY_CNT_SHIFT (0U) -/*! DAY_CNT - Days Counter Value - */ -#define RTC_DAYS_DAY_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_DAYS_DAY_CNT_SHIFT)) & RTC_DAYS_DAY_CNT_MASK) - -#define RTC_DAYS_DOW_MASK (0x700U) -#define RTC_DAYS_DOW_SHIFT (8U) -/*! DOW - Day of Week Counter Value - * 0b000..Sunday - * 0b001..Monday - * 0b010..Tuesday - * 0b011..Wednesday - * 0b100..Thursday - * 0b101..Friday - * 0b110..Saturday - * 0b111.. - */ -#define RTC_DAYS_DOW(x) (((uint16_t)(((uint16_t)(x)) << RTC_DAYS_DOW_SHIFT)) & RTC_DAYS_DOW_MASK) -/*! @} */ - -/*! @name HOURMIN - Hours and Minutes Counters */ -/*! @{ */ - -#define RTC_HOURMIN_MIN_CNT_MASK (0x3FU) -#define RTC_HOURMIN_MIN_CNT_SHIFT (0U) -/*! MIN_CNT - Minutes Counter Value - */ -#define RTC_HOURMIN_MIN_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_HOURMIN_MIN_CNT_SHIFT)) & RTC_HOURMIN_MIN_CNT_MASK) - -#define RTC_HOURMIN_HOUR_CNT_MASK (0x1F00U) -#define RTC_HOURMIN_HOUR_CNT_SHIFT (8U) -/*! HOUR_CNT - Hours Counter Value - */ -#define RTC_HOURMIN_HOUR_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_HOURMIN_HOUR_CNT_SHIFT)) & RTC_HOURMIN_HOUR_CNT_MASK) -/*! @} */ - -/*! @name SECONDS - Seconds Counters */ -/*! @{ */ - -#define RTC_SECONDS_SEC_CNT_MASK (0x3FU) -#define RTC_SECONDS_SEC_CNT_SHIFT (0U) -/*! SEC_CNT - Seconds Counter Value - */ -#define RTC_SECONDS_SEC_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_SECONDS_SEC_CNT_SHIFT)) & RTC_SECONDS_SEC_CNT_MASK) -/*! @} */ - -/*! @name ALM_YEARMON - Year and Months Alarm */ -/*! @{ */ - -#define RTC_ALM_YEARMON_ALM_MON_MASK (0xFU) -#define RTC_ALM_YEARMON_ALM_MON_SHIFT (0U) -/*! ALM_MON - Months Value for Alarm - */ -#define RTC_ALM_YEARMON_ALM_MON(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_YEARMON_ALM_MON_SHIFT)) & RTC_ALM_YEARMON_ALM_MON_MASK) - -#define RTC_ALM_YEARMON_ALM_YEAR_MASK (0xFF00U) -#define RTC_ALM_YEARMON_ALM_YEAR_SHIFT (8U) -/*! ALM_YEAR - Year Value for Alarm - */ -#define RTC_ALM_YEARMON_ALM_YEAR(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_YEARMON_ALM_YEAR_SHIFT)) & RTC_ALM_YEARMON_ALM_YEAR_MASK) -/*! @} */ - -/*! @name ALM_DAYS - Days Alarm */ -/*! @{ */ - -#define RTC_ALM_DAYS_ALM_DAY_MASK (0x1FU) -#define RTC_ALM_DAYS_ALM_DAY_SHIFT (0U) -/*! ALM_DAY - Days Value for Alarm - */ -#define RTC_ALM_DAYS_ALM_DAY(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_DAYS_ALM_DAY_SHIFT)) & RTC_ALM_DAYS_ALM_DAY_MASK) -/*! @} */ - -/*! @name ALM_HOURMIN - Hours and Minutes Alarm */ -/*! @{ */ - -#define RTC_ALM_HOURMIN_ALM_MIN_MASK (0x3FU) -#define RTC_ALM_HOURMIN_ALM_MIN_SHIFT (0U) -/*! ALM_MIN - Minutes Value for Alarm - */ -#define RTC_ALM_HOURMIN_ALM_MIN(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_HOURMIN_ALM_MIN_SHIFT)) & RTC_ALM_HOURMIN_ALM_MIN_MASK) - -#define RTC_ALM_HOURMIN_ALM_HOUR_MASK (0x1F00U) -#define RTC_ALM_HOURMIN_ALM_HOUR_SHIFT (8U) -/*! ALM_HOUR - Hours Value for Alarm - */ -#define RTC_ALM_HOURMIN_ALM_HOUR(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_HOURMIN_ALM_HOUR_SHIFT)) & RTC_ALM_HOURMIN_ALM_HOUR_MASK) -/*! @} */ - -/*! @name ALM_SECONDS - Seconds Alarm */ -/*! @{ */ - -#define RTC_ALM_SECONDS_ALM_SEC_MASK (0x3FU) -#define RTC_ALM_SECONDS_ALM_SEC_SHIFT (0U) -/*! ALM_SEC - Seconds Alarm Value - */ -#define RTC_ALM_SECONDS_ALM_SEC(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_ALM_SEC_SHIFT)) & RTC_ALM_SECONDS_ALM_SEC_MASK) - -#define RTC_ALM_SECONDS_DEC_SEC_MASK (0x100U) -#define RTC_ALM_SECONDS_DEC_SEC_SHIFT (8U) -/*! DEC_SEC - Decrement Seconds Counter by 1. - */ -#define RTC_ALM_SECONDS_DEC_SEC(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_DEC_SEC_SHIFT)) & RTC_ALM_SECONDS_DEC_SEC_MASK) - -#define RTC_ALM_SECONDS_INC_SEC_MASK (0x200U) -#define RTC_ALM_SECONDS_INC_SEC_SHIFT (9U) -/*! INC_SEC - Increment Seconds Counter by 1. - */ -#define RTC_ALM_SECONDS_INC_SEC(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_INC_SEC_SHIFT)) & RTC_ALM_SECONDS_INC_SEC_MASK) -/*! @} */ - -/*! @name CTRL - Control */ -/*! @{ */ - -#define RTC_CTRL_FINEEN_MASK (0x1U) -#define RTC_CTRL_FINEEN_SHIFT (0U) -/*! FINEEN - Fine Compensation Enable - * 0b1..Fine compensation is enabled. - * 0b0..Fine compensation is disabled - */ -#define RTC_CTRL_FINEEN(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_FINEEN_SHIFT)) & RTC_CTRL_FINEEN_MASK) - -#define RTC_CTRL_COMP_EN_MASK (0x2U) -#define RTC_CTRL_COMP_EN_SHIFT (1U) -/*! COMP_EN - Compensation Enable - * 0b0..Coarse Compensation is disabled. - * 0b1..Coarse Compensation is enabled. - */ -#define RTC_CTRL_COMP_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_COMP_EN_SHIFT)) & RTC_CTRL_COMP_EN_MASK) - -#define RTC_CTRL_ALM_MATCH_MASK (0xCU) -#define RTC_CTRL_ALM_MATCH_SHIFT (2U) -/*! ALM_MATCH - Alarm Match - * 0b00..Only Seconds, Minutes, and Hours matched. - * 0b01..Only Seconds, Minutes, Hours, and Days matched. - * 0b10..Only Seconds, Minutes, Hours, Days, and Months matched. - * 0b11..Only Seconds, Minutes, Hours, Days, Months, and Year (offset) matched. - */ -#define RTC_CTRL_ALM_MATCH(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_ALM_MATCH_SHIFT)) & RTC_CTRL_ALM_MATCH_MASK) - -#define RTC_CTRL_TIMER_STB_MASK_MASK (0x10U) -#define RTC_CTRL_TIMER_STB_MASK_SHIFT (4U) -/*! TIMER_STB_MASK - Sampling Timer Clocks Mask - * 0b1..Sampling clocks are gated in standby mode - * 0b0..Sampling clocks are not gated when in standby mode - */ -#define RTC_CTRL_TIMER_STB_MASK(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_TIMER_STB_MASK_SHIFT)) & RTC_CTRL_TIMER_STB_MASK_MASK) - -#define RTC_CTRL_DST_EN_MASK (0x40U) -#define RTC_CTRL_DST_EN_SHIFT (6U) -/*! DST_EN - Daylight Saving Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define RTC_CTRL_DST_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_DST_EN_SHIFT)) & RTC_CTRL_DST_EN_MASK) - -#define RTC_CTRL_SWR_MASK (0x100U) -#define RTC_CTRL_SWR_SHIFT (8U) -/*! SWR - Software Reset - * 0b0..Software Reset cleared - * 0b1..Software Reset asserted - */ -#define RTC_CTRL_SWR(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_SWR_SHIFT)) & RTC_CTRL_SWR_MASK) - -#define RTC_CTRL_CLKOUT_MASK (0x6000U) -#define RTC_CTRL_CLKOUT_SHIFT (13U) -/*! CLKOUT - RTC Clock Output Selection - * 0b00..No Output Clock - * 0b01..Fine 1 Hz Clock with both precise edges - * 0b10..32.768 kHz Clock - * 0b11..Coarse 1 Hz Clock with both precise edges - */ -#define RTC_CTRL_CLKOUT(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_CLKOUT_SHIFT)) & RTC_CTRL_CLKOUT_MASK) -/*! @} */ - -/*! @name STATUS - Status */ -/*! @{ */ - -#define RTC_STATUS_INVAL_BIT_MASK (0x1U) -#define RTC_STATUS_INVAL_BIT_SHIFT (0U) -/*! INVAL_BIT - Invalidate CPU Read/Write Access - * 0b0..Time /Date Counters can be read/written. Time /Date is valid. - * 0b1..Time /Date Counter values are changing or Time /Date is invalid and cannot be read or written. - */ -#define RTC_STATUS_INVAL_BIT(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_INVAL_BIT_SHIFT)) & RTC_STATUS_INVAL_BIT_MASK) - -#define RTC_STATUS_WRITE_PROT_EN_MASK (0x2U) -#define RTC_STATUS_WRITE_PROT_EN_SHIFT (1U) -/*! WRITE_PROT_EN - Write Protect Enable Status - * 0b0..Registers are unlocked and can be accessed. - * 0b1..Registers are locked and in read-only mode. - */ -#define RTC_STATUS_WRITE_PROT_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_WRITE_PROT_EN_SHIFT)) & RTC_STATUS_WRITE_PROT_EN_MASK) - -#define RTC_STATUS_CPU_LOW_VOLT_MASK (0x4U) -#define RTC_STATUS_CPU_LOW_VOLT_SHIFT (2U) -/*! CPU_LOW_VOLT - CPU Low Voltage Warning Status - * 0b0..CPU in Normal Operating Voltage. - * 0b1..CPU Voltage is below Normal Operating Voltage. RTC Registers in read-only mode. - */ -#define RTC_STATUS_CPU_LOW_VOLT(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CPU_LOW_VOLT_SHIFT)) & RTC_STATUS_CPU_LOW_VOLT_MASK) - -#define RTC_STATUS_RST_SRC_MASK (0x8U) -#define RTC_STATUS_RST_SRC_SHIFT (3U) -/*! RST_SRC - Reset Source - * 0b0..Standby Mode Exit - * 0b1..Power-On Reset - */ -#define RTC_STATUS_RST_SRC(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_RST_SRC_SHIFT)) & RTC_STATUS_RST_SRC_MASK) - -#define RTC_STATUS_CMP_INT_MASK (0x20U) -#define RTC_STATUS_CMP_INT_SHIFT (5U) -/*! CMP_INT - Compensation Interval - */ -#define RTC_STATUS_CMP_INT(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CMP_INT_SHIFT)) & RTC_STATUS_CMP_INT_MASK) - -#define RTC_STATUS_WE_MASK (0xC0U) -#define RTC_STATUS_WE_SHIFT (6U) -/*! WE - Write Enable - * 0b10..Enable Write Protection - Registers are locked. - * 0b00, 0b01, 0b11, 0b10..Disable Write Protection - Registers are unlocked. - */ -#define RTC_STATUS_WE(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_WE_SHIFT)) & RTC_STATUS_WE_MASK) - -#define RTC_STATUS_BUS_ERR_MASK (0x100U) -#define RTC_STATUS_BUS_ERR_SHIFT (8U) -/*! BUS_ERR - Bus Error - * 0b0..Read and Write accesses are normal. - * 0b1..Read or Write accesses occurred when INVAL_BIT was asserted. - */ -#define RTC_STATUS_BUS_ERR(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_BUS_ERR_SHIFT)) & RTC_STATUS_BUS_ERR_MASK) - -#define RTC_STATUS_CMP_DONE_MASK (0x800U) -#define RTC_STATUS_CMP_DONE_SHIFT (11U) -/*! CMP_DONE - Compensation Done - * 0b0..Compensation busy or not enabled - * 0b1..Compensation completed - */ -#define RTC_STATUS_CMP_DONE(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CMP_DONE_SHIFT)) & RTC_STATUS_CMP_DONE_MASK) -/*! @} */ - -/*! @name ISR - Interrupt Status */ -/*! @{ */ - -#define RTC_ISR_TAMPER_IS_MASK (0x1U) -#define RTC_ISR_TAMPER_IS_SHIFT (0U) -/*! TAMPER_IS - Tamper Interrupt Status - * 0b0..Interrupt is de-asserted. - * 0b1..Interrupt is asserted (Default on reset) . - */ -#define RTC_ISR_TAMPER_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_TAMPER_IS_SHIFT)) & RTC_ISR_TAMPER_IS_MASK) - -#define RTC_ISR_ALM_IS_MASK (0x4U) -#define RTC_ISR_ALM_IS_SHIFT (2U) -/*! ALM_IS - Alarm Interrupt Status - * 0b0..Interrupt is de-asserted. - * 0b1..Interrupt is asserted. - */ -#define RTC_ISR_ALM_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_ALM_IS_SHIFT)) & RTC_ISR_ALM_IS_MASK) - -#define RTC_ISR_DAY_IS_MASK (0x8U) -#define RTC_ISR_DAY_IS_SHIFT (3U) -/*! DAY_IS - Days Interrupt Status - * 0b0..Interrupt is de-asserted. - * 0b1..Interrupt is asserted. - */ -#define RTC_ISR_DAY_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_DAY_IS_SHIFT)) & RTC_ISR_DAY_IS_MASK) - -#define RTC_ISR_HOUR_IS_MASK (0x10U) -#define RTC_ISR_HOUR_IS_SHIFT (4U) -/*! HOUR_IS - Hours Interrupt Status - * 0b0..Interrupt is de-asserted. - * 0b1..Interrupt is asserted. - */ -#define RTC_ISR_HOUR_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_HOUR_IS_SHIFT)) & RTC_ISR_HOUR_IS_MASK) - -#define RTC_ISR_MIN_IS_MASK (0x20U) -#define RTC_ISR_MIN_IS_SHIFT (5U) -/*! MIN_IS - Minutes Interrupt Status - * 0b0..Interrupt is de-asserted. - * 0b1..Interrupt is asserted. - */ -#define RTC_ISR_MIN_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_MIN_IS_SHIFT)) & RTC_ISR_MIN_IS_MASK) - -#define RTC_ISR_IS_1HZ_MASK (0x40U) -#define RTC_ISR_IS_1HZ_SHIFT (6U) -/*! IS_1HZ - 1 Hz Interval Interrupt Status - * 0b0..Interrupt is de-asserted. - * 0b1..Interrupt is asserted. - */ -#define RTC_ISR_IS_1HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_1HZ_SHIFT)) & RTC_ISR_IS_1HZ_MASK) - -#define RTC_ISR_IS_2HZ_MASK (0x80U) -#define RTC_ISR_IS_2HZ_SHIFT (7U) -/*! IS_2HZ - 2 Hz Interval Interrupt Status - * 0b0..Interrupt is de-asserted. - * 0b1..Interrupt is asserted. - */ -#define RTC_ISR_IS_2HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_2HZ_SHIFT)) & RTC_ISR_IS_2HZ_MASK) - -#define RTC_ISR_IS_4HZ_MASK (0x100U) -#define RTC_ISR_IS_4HZ_SHIFT (8U) -/*! IS_4HZ - 4 Hz Interval Interrupt Status - * 0b0..Interrupt is de-asserted. - * 0b1..Interrupt is asserted. - */ -#define RTC_ISR_IS_4HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_4HZ_SHIFT)) & RTC_ISR_IS_4HZ_MASK) - -#define RTC_ISR_IS_8HZ_MASK (0x200U) -#define RTC_ISR_IS_8HZ_SHIFT (9U) -/*! IS_8HZ - 8 Hz Interval Interrupt Status - * 0b0..Interrupt is de-asserted. - * 0b1..Interrupt is asserted. - */ -#define RTC_ISR_IS_8HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_8HZ_SHIFT)) & RTC_ISR_IS_8HZ_MASK) - -#define RTC_ISR_IS_16HZ_MASK (0x400U) -#define RTC_ISR_IS_16HZ_SHIFT (10U) -/*! IS_16HZ - 16 Hz Interval Interrupt Status - * 0b0..Interrupt is de-asserted. - * 0b1..Interrupt is asserted. - */ -#define RTC_ISR_IS_16HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_16HZ_SHIFT)) & RTC_ISR_IS_16HZ_MASK) - -#define RTC_ISR_IS_32HZ_MASK (0x800U) -#define RTC_ISR_IS_32HZ_SHIFT (11U) -/*! IS_32HZ - 32 Hz Interval Interrupt Status - * 0b0..Interrupt is de-asserted. - * 0b1..Interrupt is asserted. - */ -#define RTC_ISR_IS_32HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_32HZ_SHIFT)) & RTC_ISR_IS_32HZ_MASK) - -#define RTC_ISR_IS_64HZ_MASK (0x1000U) -#define RTC_ISR_IS_64HZ_SHIFT (12U) -/*! IS_64HZ - 64 Hz Interval Interrupt Status - * 0b0..Interrupt is de-asserted. - * 0b1..Interrupt is asserted. - */ -#define RTC_ISR_IS_64HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_64HZ_SHIFT)) & RTC_ISR_IS_64HZ_MASK) - -#define RTC_ISR_IS_128HZ_MASK (0x2000U) -#define RTC_ISR_IS_128HZ_SHIFT (13U) -/*! IS_128HZ - 128 Hz Interval Interrupt Status - * 0b0..Interrupt is de-asserted. - * 0b1..Interrupt is asserted. - */ -#define RTC_ISR_IS_128HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_128HZ_SHIFT)) & RTC_ISR_IS_128HZ_MASK) - -#define RTC_ISR_IS_256HZ_MASK (0x4000U) -#define RTC_ISR_IS_256HZ_SHIFT (14U) -/*! IS_256HZ - 256 Hz Interval Interrupt Status - * 0b0..Interrupt is de-asserted. - * 0b1..Interrupt is asserted. - */ -#define RTC_ISR_IS_256HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_256HZ_SHIFT)) & RTC_ISR_IS_256HZ_MASK) - -#define RTC_ISR_IS_512HZ_MASK (0x8000U) -#define RTC_ISR_IS_512HZ_SHIFT (15U) -/*! IS_512HZ - 512 Hz Interval Interrupt Status - * 0b0..Interrupt is de-asserted. - * 0b1..Interrupt is asserted. - */ -#define RTC_ISR_IS_512HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_512HZ_SHIFT)) & RTC_ISR_IS_512HZ_MASK) -/*! @} */ - -/*! @name IER - Interrupt Enable */ -/*! @{ */ - -#define RTC_IER_TAMPER_IE_MASK (0x1U) -#define RTC_IER_TAMPER_IE_SHIFT (0U) -/*! TAMPER_IE - Tamper Interrupt Enable - * 0b0..Interrupt is disabled. - * 0b1..Interrupt is enabled (Default on reset). - */ -#define RTC_IER_TAMPER_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_TAMPER_IE_SHIFT)) & RTC_IER_TAMPER_IE_MASK) - -#define RTC_IER_ALM_IE_MASK (0x4U) -#define RTC_IER_ALM_IE_SHIFT (2U) -/*! ALM_IE - Alarm Interrupt Enable - * 0b0..Interrupt is disabled. - * 0b1..Interrupt is enabled. - */ -#define RTC_IER_ALM_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_ALM_IE_SHIFT)) & RTC_IER_ALM_IE_MASK) - -#define RTC_IER_DAY_IE_MASK (0x8U) -#define RTC_IER_DAY_IE_SHIFT (3U) -/*! DAY_IE - Days Interrupt Enable - * 0b0..Interrupt is disabled. - * 0b1..Interrupt is enabled. - */ -#define RTC_IER_DAY_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_DAY_IE_SHIFT)) & RTC_IER_DAY_IE_MASK) - -#define RTC_IER_HOUR_IE_MASK (0x10U) -#define RTC_IER_HOUR_IE_SHIFT (4U) -/*! HOUR_IE - Hours Interrupt Enable - * 0b0..Interrupt is disabled. - * 0b1..Interrupt is enabled. - */ -#define RTC_IER_HOUR_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_HOUR_IE_SHIFT)) & RTC_IER_HOUR_IE_MASK) - -#define RTC_IER_MIN_IE_MASK (0x20U) -#define RTC_IER_MIN_IE_SHIFT (5U) -/*! MIN_IE - Minutes Interrupt Enable - * 0b0..Interrupt is disabled. - * 0b1..Interrupt is enabled. - */ -#define RTC_IER_MIN_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_MIN_IE_SHIFT)) & RTC_IER_MIN_IE_MASK) - -#define RTC_IER_IE_1HZ_MASK (0x40U) -#define RTC_IER_IE_1HZ_SHIFT (6U) -/*! IE_1HZ - 1 Hz Interval Interrupt Enable - * 0b0..Interrupt is disabled. - * 0b1..Interrupt is enabled. - */ -#define RTC_IER_IE_1HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_1HZ_SHIFT)) & RTC_IER_IE_1HZ_MASK) - -#define RTC_IER_IE_2HZ_MASK (0x80U) -#define RTC_IER_IE_2HZ_SHIFT (7U) -/*! IE_2HZ - 2 Hz Interval Interrupt Enable - * 0b0..Interrupt is disabled. - * 0b1..Interrupt is enabled. - */ -#define RTC_IER_IE_2HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_2HZ_SHIFT)) & RTC_IER_IE_2HZ_MASK) - -#define RTC_IER_IE_4HZ_MASK (0x100U) -#define RTC_IER_IE_4HZ_SHIFT (8U) -/*! IE_4HZ - 4 Hz Interval Interrupt Enable - * 0b0..Interrupt is disabled. - * 0b1..Interrupt is enabled. - */ -#define RTC_IER_IE_4HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_4HZ_SHIFT)) & RTC_IER_IE_4HZ_MASK) - -#define RTC_IER_IE_8HZ_MASK (0x200U) -#define RTC_IER_IE_8HZ_SHIFT (9U) -/*! IE_8HZ - 8 Hz Interval Interrupt Enable - * 0b0..Interrupt is disabled. - * 0b1..Interrupt is enabled. - */ -#define RTC_IER_IE_8HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_8HZ_SHIFT)) & RTC_IER_IE_8HZ_MASK) - -#define RTC_IER_IE_16HZ_MASK (0x400U) -#define RTC_IER_IE_16HZ_SHIFT (10U) -/*! IE_16HZ - 16 Hz Interval Interrupt Enable - * 0b0..Interrupt is disabled. - * 0b1..Interrupt is enabled. - */ -#define RTC_IER_IE_16HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_16HZ_SHIFT)) & RTC_IER_IE_16HZ_MASK) - -#define RTC_IER_IE_32HZ_MASK (0x800U) -#define RTC_IER_IE_32HZ_SHIFT (11U) -/*! IE_32HZ - 32 Hz Interval Interrupt Enable - * 0b0..Interrupt is disabled. - * 0b1..Interrupt is enabled. - */ -#define RTC_IER_IE_32HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_32HZ_SHIFT)) & RTC_IER_IE_32HZ_MASK) - -#define RTC_IER_IE_64HZ_MASK (0x1000U) -#define RTC_IER_IE_64HZ_SHIFT (12U) -/*! IE_64HZ - 64 Hz Interval Interrupt Enable - * 0b0..Interrupt is disabled. - * 0b1..Interrupt is enabled. - */ -#define RTC_IER_IE_64HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_64HZ_SHIFT)) & RTC_IER_IE_64HZ_MASK) - -#define RTC_IER_IE_128HZ_MASK (0x2000U) -#define RTC_IER_IE_128HZ_SHIFT (13U) -/*! IE_128HZ - 128 Hz Interval Interrupt Enable - * 0b0..Interrupt is disabled. - * 0b1..Interrupt is enabled. - */ -#define RTC_IER_IE_128HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_128HZ_SHIFT)) & RTC_IER_IE_128HZ_MASK) - -#define RTC_IER_IE_256HZ_MASK (0x4000U) -#define RTC_IER_IE_256HZ_SHIFT (14U) -/*! IE_256HZ - 256 Hz Interval Interrupt Enable - * 0b0..Interrupt is disabled. - * 0b1..Interrupt is enabled. - */ -#define RTC_IER_IE_256HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_256HZ_SHIFT)) & RTC_IER_IE_256HZ_MASK) - -#define RTC_IER_IE_512HZ_MASK (0x8000U) -#define RTC_IER_IE_512HZ_SHIFT (15U) -/*! IE_512HZ - 512 Hz Interval Interrupt Enable - * 0b0..Interrupt is disabled. - * 0b1..Interrupt is enabled. - */ -#define RTC_IER_IE_512HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_512HZ_SHIFT)) & RTC_IER_IE_512HZ_MASK) -/*! @} */ - -/*! @name GP_DATA_REG - General Purpose Data */ -/*! @{ */ - -#define RTC_GP_DATA_REG_CFG0_MASK (0x1U) -#define RTC_GP_DATA_REG_CFG0_SHIFT (0U) -/*! CFG0 - CFGn - */ -#define RTC_GP_DATA_REG_CFG0(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG0_SHIFT)) & RTC_GP_DATA_REG_CFG0_MASK) - -#define RTC_GP_DATA_REG_CFG1_MASK (0x2U) -#define RTC_GP_DATA_REG_CFG1_SHIFT (1U) -/*! CFG1 - CFGn - */ -#define RTC_GP_DATA_REG_CFG1(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG1_SHIFT)) & RTC_GP_DATA_REG_CFG1_MASK) - -#define RTC_GP_DATA_REG_CFG2_MASK (0x4U) -#define RTC_GP_DATA_REG_CFG2_SHIFT (2U) -/*! CFG2 - CFGn - */ -#define RTC_GP_DATA_REG_CFG2(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG2_SHIFT)) & RTC_GP_DATA_REG_CFG2_MASK) - -#define RTC_GP_DATA_REG_CFG3_MASK (0x8U) -#define RTC_GP_DATA_REG_CFG3_SHIFT (3U) -/*! CFG3 - CFGn - */ -#define RTC_GP_DATA_REG_CFG3(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG3_SHIFT)) & RTC_GP_DATA_REG_CFG3_MASK) - -#define RTC_GP_DATA_REG_CFG4_MASK (0x10U) -#define RTC_GP_DATA_REG_CFG4_SHIFT (4U) -/*! CFG4 - CFGn - */ -#define RTC_GP_DATA_REG_CFG4(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG4_SHIFT)) & RTC_GP_DATA_REG_CFG4_MASK) - -#define RTC_GP_DATA_REG_CFG5_MASK (0x20U) -#define RTC_GP_DATA_REG_CFG5_SHIFT (5U) -/*! CFG5 - CFGn - */ -#define RTC_GP_DATA_REG_CFG5(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG5_SHIFT)) & RTC_GP_DATA_REG_CFG5_MASK) - -#define RTC_GP_DATA_REG_CFG6_MASK (0x40U) -#define RTC_GP_DATA_REG_CFG6_SHIFT (6U) -/*! CFG6 - CFGn - */ -#define RTC_GP_DATA_REG_CFG6(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG6_SHIFT)) & RTC_GP_DATA_REG_CFG6_MASK) - -#define RTC_GP_DATA_REG_CFG7_MASK (0x80U) -#define RTC_GP_DATA_REG_CFG7_SHIFT (7U) -/*! CFG7 - CFGn - */ -#define RTC_GP_DATA_REG_CFG7(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG7_SHIFT)) & RTC_GP_DATA_REG_CFG7_MASK) - -#define RTC_GP_DATA_REG_CFG8_MASK (0x100U) -#define RTC_GP_DATA_REG_CFG8_SHIFT (8U) -/*! CFG8 - CFGn - */ -#define RTC_GP_DATA_REG_CFG8(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG8_SHIFT)) & RTC_GP_DATA_REG_CFG8_MASK) - -#define RTC_GP_DATA_REG_CFG9_MASK (0x200U) -#define RTC_GP_DATA_REG_CFG9_SHIFT (9U) -/*! CFG9 - CFGn - */ -#define RTC_GP_DATA_REG_CFG9(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG9_SHIFT)) & RTC_GP_DATA_REG_CFG9_MASK) - -#define RTC_GP_DATA_REG_CFG10_MASK (0x400U) -#define RTC_GP_DATA_REG_CFG10_SHIFT (10U) -/*! CFG10 - CFGn - */ -#define RTC_GP_DATA_REG_CFG10(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG10_SHIFT)) & RTC_GP_DATA_REG_CFG10_MASK) - -#define RTC_GP_DATA_REG_CFG11_MASK (0x800U) -#define RTC_GP_DATA_REG_CFG11_SHIFT (11U) -/*! CFG11 - CFGn - */ -#define RTC_GP_DATA_REG_CFG11(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG11_SHIFT)) & RTC_GP_DATA_REG_CFG11_MASK) - -#define RTC_GP_DATA_REG_CFG12_MASK (0x1000U) -#define RTC_GP_DATA_REG_CFG12_SHIFT (12U) -/*! CFG12 - CFGn - */ -#define RTC_GP_DATA_REG_CFG12(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG12_SHIFT)) & RTC_GP_DATA_REG_CFG12_MASK) - -#define RTC_GP_DATA_REG_CFG13_MASK (0x2000U) -#define RTC_GP_DATA_REG_CFG13_SHIFT (13U) -/*! CFG13 - CFGn - */ -#define RTC_GP_DATA_REG_CFG13(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG13_SHIFT)) & RTC_GP_DATA_REG_CFG13_MASK) - -#define RTC_GP_DATA_REG_CFG14_MASK (0x4000U) -#define RTC_GP_DATA_REG_CFG14_SHIFT (14U) -/*! CFG14 - CFGn - */ -#define RTC_GP_DATA_REG_CFG14(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG14_SHIFT)) & RTC_GP_DATA_REG_CFG14_MASK) - -#define RTC_GP_DATA_REG_CFG15_MASK (0x8000U) -#define RTC_GP_DATA_REG_CFG15_SHIFT (15U) -/*! CFG15 - CFGn - */ -#define RTC_GP_DATA_REG_CFG15(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG15_SHIFT)) & RTC_GP_DATA_REG_CFG15_MASK) -/*! @} */ - -/*! @name DST_HOUR - Daylight Saving Hour */ -/*! @{ */ - -#define RTC_DST_HOUR_DST_END_HOUR_MASK (0x1FU) -#define RTC_DST_HOUR_DST_END_HOUR_SHIFT (0U) -/*! DST_END_HOUR - Daylight Saving Time (DST) Hours End Value - */ -#define RTC_DST_HOUR_DST_END_HOUR(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_HOUR_DST_END_HOUR_SHIFT)) & RTC_DST_HOUR_DST_END_HOUR_MASK) - -#define RTC_DST_HOUR_DST_START_HOUR_MASK (0x1F00U) -#define RTC_DST_HOUR_DST_START_HOUR_SHIFT (8U) -/*! DST_START_HOUR - Daylight Saving Time (DST) Hours Start Value - */ -#define RTC_DST_HOUR_DST_START_HOUR(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_HOUR_DST_START_HOUR_SHIFT)) & RTC_DST_HOUR_DST_START_HOUR_MASK) -/*! @} */ - -/*! @name DST_MONTH - Daylight Saving Month */ -/*! @{ */ - -#define RTC_DST_MONTH_DST_END_MONTH_MASK (0xFU) -#define RTC_DST_MONTH_DST_END_MONTH_SHIFT (0U) -/*! DST_END_MONTH - Daylight Saving Time (DST) Month End Value - */ -#define RTC_DST_MONTH_DST_END_MONTH(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_MONTH_DST_END_MONTH_SHIFT)) & RTC_DST_MONTH_DST_END_MONTH_MASK) - -#define RTC_DST_MONTH_DST_START_MONTH_MASK (0xF00U) -#define RTC_DST_MONTH_DST_START_MONTH_SHIFT (8U) -/*! DST_START_MONTH - Daylight Saving Time (DST) Month Start Value - */ -#define RTC_DST_MONTH_DST_START_MONTH(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_MONTH_DST_START_MONTH_SHIFT)) & RTC_DST_MONTH_DST_START_MONTH_MASK) -/*! @} */ - -/*! @name DST_DAY - Daylight Saving Day */ -/*! @{ */ - -#define RTC_DST_DAY_DST_END_DAY_MASK (0x1FU) -#define RTC_DST_DAY_DST_END_DAY_SHIFT (0U) -/*! DST_END_DAY - Daylight Saving Time (DST) Day End Value - */ -#define RTC_DST_DAY_DST_END_DAY(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_DAY_DST_END_DAY_SHIFT)) & RTC_DST_DAY_DST_END_DAY_MASK) - -#define RTC_DST_DAY_DST_START_DAY_MASK (0x1F00U) -#define RTC_DST_DAY_DST_START_DAY_SHIFT (8U) -/*! DST_START_DAY - Daylight Saving Time (DST) Day Start Value - */ -#define RTC_DST_DAY_DST_START_DAY(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_DAY_DST_START_DAY_SHIFT)) & RTC_DST_DAY_DST_START_DAY_MASK) -/*! @} */ - -/*! @name COMPEN - Compensation */ -/*! @{ */ - -#define RTC_COMPEN_COMPEN_VAL_MASK (0xFFFFU) -#define RTC_COMPEN_COMPEN_VAL_SHIFT (0U) -/*! COMPEN_VAL - Compensation Value - */ -#define RTC_COMPEN_COMPEN_VAL(x) (((uint16_t)(((uint16_t)(x)) << RTC_COMPEN_COMPEN_VAL_SHIFT)) & RTC_COMPEN_COMPEN_VAL_MASK) -/*! @} */ - -/*! @name TAMPER_QSCR - Tamper Queue Status and Control */ -/*! @{ */ - -#define RTC_TAMPER_QSCR_Q_FULL_MASK (0x1U) -#define RTC_TAMPER_QSCR_Q_FULL_SHIFT (0U) -/*! Q_FULL - Q_FULL - * 0b1..The tamper queue is full. - * 0b0..The tamper queue is not full. - */ -#define RTC_TAMPER_QSCR_Q_FULL(x) (((uint16_t)(((uint16_t)(x)) << RTC_TAMPER_QSCR_Q_FULL_SHIFT)) & RTC_TAMPER_QSCR_Q_FULL_MASK) - -#define RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK (0x2U) -#define RTC_TAMPER_QSCR_Q_FULL_INT_EN_SHIFT (1U) -/*! Q_FULL_INT_EN - Q_FULL_INT_EN - * 0b1..Queue full interrupt is enabled. - * 0b0..Queue full interrupt is disabled. - */ -#define RTC_TAMPER_QSCR_Q_FULL_INT_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_TAMPER_QSCR_Q_FULL_INT_EN_SHIFT)) & RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK) - -#define RTC_TAMPER_QSCR_Q_CLEAR_MASK (0x4U) -#define RTC_TAMPER_QSCR_Q_CLEAR_SHIFT (2U) -/*! Q_CLEAR - Q_CLEAR - */ -#define RTC_TAMPER_QSCR_Q_CLEAR(x) (((uint16_t)(((uint16_t)(x)) << RTC_TAMPER_QSCR_Q_CLEAR_SHIFT)) & RTC_TAMPER_QSCR_Q_CLEAR_MASK) -/*! @} */ - -/*! @name TAMPER_SCR - Tamper Status and Control */ -/*! @{ */ - -#define RTC_TAMPER_SCR_TMPR_EN_MASK (0xFU) -#define RTC_TAMPER_SCR_TMPR_EN_SHIFT (0U) -/*! TMPR_EN - Tamper Control - * 0b0000..Tamper Status reporting disabled. - * 0b0001..Tamper Status reporting enabled. - */ -#define RTC_TAMPER_SCR_TMPR_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_TAMPER_SCR_TMPR_EN_SHIFT)) & RTC_TAMPER_SCR_TMPR_EN_MASK) - -#define RTC_TAMPER_SCR_TMPR_STS_MASK (0xF00U) -#define RTC_TAMPER_SCR_TMPR_STS_SHIFT (8U) -/*! TMPR_STS - Tamper Status - * 0b0000..No Tamper Detected - * 0b0001..Tamper Event Detected - */ -#define RTC_TAMPER_SCR_TMPR_STS(x) (((uint16_t)(((uint16_t)(x)) << RTC_TAMPER_SCR_TMPR_STS_SHIFT)) & RTC_TAMPER_SCR_TMPR_STS_MASK) -/*! @} */ - -/*! @name FILTER01_CFG - Tamper 01 Filter Configuration */ -/*! @{ */ - -#define RTC_FILTER01_CFG_FIL_DUR1_MASK (0xFU) -#define RTC_FILTER01_CFG_FIL_DUR1_SHIFT (0U) -/*! FIL_DUR1 - Tamper Detect Bit 1 Filter Duration - * 0b0000..Filtering operation disabled. - * 0b0001-0b1111..Number of tamper filter clock cycles to be counted when tamper is asserted. - */ -#define RTC_FILTER01_CFG_FIL_DUR1(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_FIL_DUR1_SHIFT)) & RTC_FILTER01_CFG_FIL_DUR1_MASK) - -#define RTC_FILTER01_CFG_CLK_SEL1_MASK (0x70U) -#define RTC_FILTER01_CFG_CLK_SEL1_SHIFT (4U) -/*! CLK_SEL1 - Tamper Filter 1 Clock Select - * 0b000..32 kHz clock - * 0b001..512 Hz clock - * 0b010..128 Hz clock - * 0b011..64 Hz clock - * 0b100..16 Hz clock - * 0b101..8 Hz clock - * 0b110..4 Hz clock - * 0b111..2 Hz clock - */ -#define RTC_FILTER01_CFG_CLK_SEL1(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_CLK_SEL1_SHIFT)) & RTC_FILTER01_CFG_CLK_SEL1_MASK) - -#define RTC_FILTER01_CFG_POL1_MASK (0x80U) -#define RTC_FILTER01_CFG_POL1_SHIFT (7U) -/*! POL1 - Tamper Detect Input Bit 1 Polarity Control - * 0b0..Tamper detect input bit 1 is active high. - * 0b1..Tamper detect input bit 1 is active low. - */ -#define RTC_FILTER01_CFG_POL1(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_POL1_SHIFT)) & RTC_FILTER01_CFG_POL1_MASK) - -#define RTC_FILTER01_CFG_FIL_DUR0_MASK (0xF00U) -#define RTC_FILTER01_CFG_FIL_DUR0_SHIFT (8U) -/*! FIL_DUR0 - Tamper Detect Bit 0 Filter Duration - * 0b0000..Filtering operation disabled. - * 0b0001-0b1111..Number of tamper filter clock cycles to be counted when tamper is asserted. - */ -#define RTC_FILTER01_CFG_FIL_DUR0(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_FIL_DUR0_SHIFT)) & RTC_FILTER01_CFG_FIL_DUR0_MASK) - -#define RTC_FILTER01_CFG_CLK_SEL0_MASK (0x7000U) -#define RTC_FILTER01_CFG_CLK_SEL0_SHIFT (12U) -/*! CLK_SEL0 - Tamper Filter 0 Clock Select - * 0b000..32 kHz clock - * 0b001..512 Hz clock - * 0b010..128 Hz clock - * 0b011..64 Hz clock - * 0b100..16 Hz clock - * 0b101..8 Hz clock - * 0b110..4 Hz clock - * 0b111..2 Hz clock - */ -#define RTC_FILTER01_CFG_CLK_SEL0(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_CLK_SEL0_SHIFT)) & RTC_FILTER01_CFG_CLK_SEL0_MASK) - -#define RTC_FILTER01_CFG_POL0_MASK (0x8000U) -#define RTC_FILTER01_CFG_POL0_SHIFT (15U) -/*! POL0 - Tamper Detect Input Bit 0 Polarity Control - * 0b0..Tamper detect input bit 0 is active high. - * 0b1..Tamper detect input bit 0 is active low. - */ -#define RTC_FILTER01_CFG_POL0(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_POL0_SHIFT)) & RTC_FILTER01_CFG_POL0_MASK) -/*! @} */ - -/*! @name FILTER23_CFG - Tamper 23 Filter Configuration */ -/*! @{ */ - -#define RTC_FILTER23_CFG_FIL_DUR3_MASK (0xFU) -#define RTC_FILTER23_CFG_FIL_DUR3_SHIFT (0U) -/*! FIL_DUR3 - Tamper Detect Bit 3 Filter Duration - * 0b0000..Filtering operation disabled. - * 0b0001-0b1111..Number of tamper filter clock cycles to be counted when tamper is asserted. - */ -#define RTC_FILTER23_CFG_FIL_DUR3(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER23_CFG_FIL_DUR3_SHIFT)) & RTC_FILTER23_CFG_FIL_DUR3_MASK) - -#define RTC_FILTER23_CFG_CLK_SEL3_MASK (0x70U) -#define RTC_FILTER23_CFG_CLK_SEL3_SHIFT (4U) -/*! CLK_SEL3 - Tamper Filter 3 Clock Select - * 0b000..32 kHz clock - * 0b001..512 Hz clock - * 0b010..128 Hz clock - * 0b011..64 Hz clock - * 0b100..16 Hz clock - * 0b101..8 Hz clock - * 0b110..4 Hz clock - * 0b111..2 Hz clock - */ -#define RTC_FILTER23_CFG_CLK_SEL3(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER23_CFG_CLK_SEL3_SHIFT)) & RTC_FILTER23_CFG_CLK_SEL3_MASK) - -#define RTC_FILTER23_CFG_POL3_MASK (0x80U) -#define RTC_FILTER23_CFG_POL3_SHIFT (7U) -/*! POL3 - Tamper Detect Input Bit 3 Polarity Control - * 0b0..Tamper detect input bit 3 is active high. - * 0b1..Tamper detect input bit 3 is active low. - */ -#define RTC_FILTER23_CFG_POL3(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER23_CFG_POL3_SHIFT)) & RTC_FILTER23_CFG_POL3_MASK) - -#define RTC_FILTER23_CFG_FIL_DUR2_MASK (0xF00U) -#define RTC_FILTER23_CFG_FIL_DUR2_SHIFT (8U) -/*! FIL_DUR2 - Tamper Detect Bit 2 Filter Duration - * 0b0000..Filtering operation disabled. - * 0b0001-0b1111..Number of tamper filter clock cycles to be counted when tamper is asserted. - */ -#define RTC_FILTER23_CFG_FIL_DUR2(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER23_CFG_FIL_DUR2_SHIFT)) & RTC_FILTER23_CFG_FIL_DUR2_MASK) - -#define RTC_FILTER23_CFG_CLK_SEL2_MASK (0x7000U) -#define RTC_FILTER23_CFG_CLK_SEL2_SHIFT (12U) -/*! CLK_SEL2 - Tamper Filter 2 Clock Select - * 0b000..32 kHz clock - * 0b001..512 Hz clock - * 0b010..128 Hz clock - * 0b011..64 Hz clock - * 0b100..16 Hz clock - * 0b101..8 Hz clock - * 0b110..4 Hz clock - * 0b111..2 Hz clock - */ -#define RTC_FILTER23_CFG_CLK_SEL2(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER23_CFG_CLK_SEL2_SHIFT)) & RTC_FILTER23_CFG_CLK_SEL2_MASK) - -#define RTC_FILTER23_CFG_POL2_MASK (0x8000U) -#define RTC_FILTER23_CFG_POL2_SHIFT (15U) -/*! POL2 - Tamper Detect Input Bit 2 Polarity Control - * 0b0..Tamper detect input bit 2 is active high. - * 0b1..Tamper detect input bit 2 is active low. - */ -#define RTC_FILTER23_CFG_POL2(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER23_CFG_POL2_SHIFT)) & RTC_FILTER23_CFG_POL2_MASK) -/*! @} */ - -/*! @name TAMPER_QUEUE - Tamper Queue */ -/*! @{ */ - -#define RTC_TAMPER_QUEUE_TAMPER_DATA_MASK (0xFFFFU) -#define RTC_TAMPER_QUEUE_TAMPER_DATA_SHIFT (0U) -/*! TAMPER_DATA - Tamper type stamp and pin number information register - */ -#define RTC_TAMPER_QUEUE_TAMPER_DATA(x) (((uint16_t)(((uint16_t)(x)) << RTC_TAMPER_QUEUE_TAMPER_DATA_SHIFT)) & RTC_TAMPER_QUEUE_TAMPER_DATA_MASK) -/*! @} */ - -/*! @name CTRL2 - Control 2 */ -/*! @{ */ - -#define RTC_CTRL2_TAMP_CFG_OVER_MASK (0x1U) -#define RTC_CTRL2_TAMP_CFG_OVER_SHIFT (0U) -/*! TAMP_CFG_OVER - Tamper Configuration Over - * 0b0..Tamper filter processing disabled. - * 0b1..Tamper filter processing enabled. - */ -#define RTC_CTRL2_TAMP_CFG_OVER(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL2_TAMP_CFG_OVER_SHIFT)) & RTC_CTRL2_TAMP_CFG_OVER_MASK) -/*! @} */ - -/*! @name SUBSECOND_CTRL - Sub-second control */ -/*! @{ */ - -#define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK (0x1U) -#define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_SHIFT (0U) -/*! SUB_SECOND_CNT_EN - Sub-second counter enable bit - * 0b0..Disabled. - * 0b1..Enabled. - */ -#define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_SHIFT)) & RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK) -/*! @} */ - -/*! @name SUBSECOND_CNT - Sub-second counter */ -/*! @{ */ - -#define RTC_SUBSECOND_CNT_SUBSECOND_CNT_MASK (0xFFFFU) -#define RTC_SUBSECOND_CNT_SUBSECOND_CNT_SHIFT (0U) -/*! SUBSECOND_CNT - Current sub-second counter value - */ -#define RTC_SUBSECOND_CNT_SUBSECOND_CNT(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSECOND_CNT_SUBSECOND_CNT_SHIFT)) & RTC_SUBSECOND_CNT_SUBSECOND_CNT_MASK) -/*! @} */ - -/*! @name WAKE_TIMER_CTRL - Wake timer control */ -/*! @{ */ - -#define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK (0x2U) -#define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT (1U) -/*! WAKE_FLAG - Wake timer status flag - * 0b0..Wake timer has not timed out. - * 0b1..Wake timer has timed out. - */ -#define RTC_WAKE_TIMER_CTRL_WAKE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT)) & RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK) - -#define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK (0x4U) -#define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT (2U) -/*! CLR_WAKE_TIMER - Clear wake timer - * 0b0..No effect. - * 0b1..Clears the wake counter and halt operation until a new count value is loaded. - */ -#define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT)) & RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK) - -#define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK (0x10U) -#define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT (4U) -/*! OSC_DIV_ENA - Enable the 5-bit clock divider to divide down the 32Khz input clock to generate - * the 1Khz clock source for the wake timer. - * 0b0..Disabled. - * 0b1..Enabled. - */ -#define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT)) & RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK) - -#define RTC_WAKE_TIMER_CTRL_INTR_EN_MASK (0x20U) -#define RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT (5U) -/*! INTR_EN - Enable interrupt when WAKE_FLAG is set. - * 0b0..Disabled. - * 0b1..Enabled. - */ -#define RTC_WAKE_TIMER_CTRL_INTR_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT)) & RTC_WAKE_TIMER_CTRL_INTR_EN_MASK) -/*! @} */ - -/*! @name WAKE_TIMER_CNT - Wake timer counter */ -/*! @{ */ - -#define RTC_WAKE_TIMER_CNT_WAKE_CNT_MASK (0xFFFFFFFFU) -#define RTC_WAKE_TIMER_CNT_WAKE_CNT_SHIFT (0U) -/*! WAKE_CNT - Wake counter - */ -#define RTC_WAKE_TIMER_CNT_WAKE_CNT(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CNT_WAKE_CNT_SHIFT)) & RTC_WAKE_TIMER_CNT_WAKE_CNT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group RTC_Register_Masks */ - - -/* RTC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral RTC base address */ - #define RTC_BASE (0x5002C000u) - /** Peripheral RTC base address */ - #define RTC_BASE_NS (0x4002C000u) - /** Peripheral RTC base pointer */ - #define RTC ((RTC_Type *)RTC_BASE) - /** Peripheral RTC base pointer */ - #define RTC_NS ((RTC_Type *)RTC_BASE_NS) - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS { RTC_BASE } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS { RTC } - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS_NS { RTC_BASE_NS } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS_NS { RTC_NS } -#else - /** Peripheral RTC base address */ - #define RTC_BASE (0x4002C000u) - /** Peripheral RTC base pointer */ - #define RTC ((RTC_Type *)RTC_BASE) - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS { RTC_BASE } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS { RTC } -#endif -/** Interrupt vectors for the RTC peripheral type */ -#define RTC_IRQS { RTC_IRQn } - -/*! - * @} - */ /* end of group RTC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SCT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer - * @{ - */ - -/** SCT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CONFIG; /**< SCTimer Configuration, offset: 0x0 */ - union { /* offset: 0x4 */ - struct { /* offset: 0x4 */ - __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */ - __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */ - } CTRL_ACCESS16BIT; - __IO uint32_t CTRL; /**< SCT Control, offset: 0x4 */ - }; - union { /* offset: 0x8 */ - struct { /* offset: 0x8 */ - __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */ - __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */ - } LIMIT_ACCESS16BIT; - __IO uint32_t LIMIT; /**< SCT Limit Event Select, offset: 0x8 */ - }; - union { /* offset: 0xC */ - struct { /* offset: 0xC */ - __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */ - __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */ - } HALT_ACCESS16BIT; - __IO uint32_t HALT; /**< Halt Event Select, offset: 0xC */ - }; - union { /* offset: 0x10 */ - struct { /* offset: 0x10 */ - __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */ - __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */ - } STOP_ACCESS16BIT; - __IO uint32_t STOP; /**< Stop Event Select, offset: 0x10 */ - }; - union { /* offset: 0x14 */ - struct { /* offset: 0x14 */ - __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */ - __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */ - } START_ACCESS16BIT; - __IO uint32_t START; /**< Start Event Select, offset: 0x14 */ - }; - __IO uint32_t DITHER; /**< Dither Condition, offset: 0x18 */ - uint8_t RESERVED_0[36]; - union { /* offset: 0x40 */ - struct { /* offset: 0x40 */ - __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */ - __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */ - } COUNT_ACCESS16BIT; - __IO uint32_t COUNT; /**< Counter, offset: 0x40 */ - }; - union { /* offset: 0x44 */ - struct { /* offset: 0x44 */ - __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */ - __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */ - } STATE_ACCESS16BIT; - __IO uint32_t STATE; /**< State, offset: 0x44 */ - }; - __I uint32_t INPUT; /**< Input, offset: 0x48 */ - union { /* offset: 0x4C */ - struct { /* offset: 0x4C */ - __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */ - __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */ - } REGMODE_ACCESS16BIT; - __IO uint32_t REGMODE; /**< Match/Capture Mode, offset: 0x4C */ - }; - __IO uint32_t OUTPUT; /**< Output, offset: 0x50 */ - __IO uint32_t OUTPUTDIRCTRL; /**< Output Counter Direction Control, offset: 0x54 */ - __IO uint32_t RES; /**< Output Conflict Resolution, offset: 0x58 */ - __IO uint32_t DMAREQ0; /**< DMA Request 0, offset: 0x5C */ - __IO uint32_t DMAREQ1; /**< DMA Request 1, offset: 0x60 */ - uint8_t RESERVED_1[140]; - __IO uint32_t EVEN; /**< Event Interrupt Enable, offset: 0xF0 */ - __IO uint32_t EVFLAG; /**< Event Flag, offset: 0xF4 */ - __IO uint32_t CONEN; /**< Conflict Interrupt Enable, offset: 0xF8 */ - __IO uint32_t CONFLAG; /**< Conflict Flag, offset: 0xFC */ - union { /* offset: 0x100 */ - union { /* offset: 0x100, array step: 0x4 */ - struct { /* offset: 0x100, array step: 0x4 */ - __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */ - __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */ - } CAP_ACCESS16BIT[16]; - __IO uint32_t CAP[16]; /**< Capture Value, array offset: 0x100, array step: 0x4 */ - }; - union { /* offset: 0x100, array step: 0x4 */ - struct { /* offset: 0x100, array step: 0x4 */ - __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */ - __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */ - } MATCH_ACCESS16BIT[16]; - __IO uint32_t MATCH[16]; /**< Match Value, array offset: 0x100, array step: 0x4 */ - }; - }; - __IO uint32_t FRACMAT[6]; /**< Fractional Match, array offset: 0x140, array step: 0x4 */ - uint8_t RESERVED_2[168]; - union { /* offset: 0x200 */ - union { /* offset: 0x200, array step: 0x4 */ - struct { /* offset: 0x200, array step: 0x4 */ - __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */ - __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */ - } CAPCTRL_ACCESS16BIT[16]; - __IO uint32_t CAPCTRL[16]; /**< Capture Control, array offset: 0x200, array step: 0x4 */ - }; - union { /* offset: 0x200, array step: 0x4 */ - struct { /* offset: 0x200, array step: 0x4 */ - __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */ - __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */ - } MATCHREL_ACCESS16BIT[16]; - __IO uint32_t MATCHREL[16]; /**< Match Reload Value, array offset: 0x200, array step: 0x4 */ - }; - }; - __IO uint32_t FRACMATREL[6]; /**< Fractional Match Reload, array offset: 0x240, array step: 0x4 */ - uint8_t RESERVED_3[168]; - struct { /* offset: 0x300, array step: 0x8 */ - __IO uint32_t STATE; /**< Event n State, array offset: 0x300, array step: 0x8 */ - __IO uint32_t CTRL; /**< Event n Control, array offset: 0x304, array step: 0x8 */ - } EV[16]; - uint8_t RESERVED_4[384]; - struct { /* offset: 0x500, array step: 0x8 */ - __IO uint32_t SET; /**< Output n Set, array offset: 0x500, array step: 0x8 */ - __IO uint32_t CLR; /**< Output n Clear, array offset: 0x504, array step: 0x8 */ - } OUT[10]; -} SCT_Type; - -/* ---------------------------------------------------------------------------- - -- SCT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Register_Masks SCT Register Masks - * @{ - */ - -/*! @name CONFIG - SCTimer Configuration */ -/*! @{ */ - -#define SCT_CONFIG_UNIFY_MASK (0x1U) -#define SCT_CONFIG_UNIFY_SHIFT (0U) -/*! UNIFY - SCT Operation - * 0b0..Dual counter. The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. - * 0b1..Unified counter. The SCT operates as a unified 32-bit counter. - */ -#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) - -#define SCT_CONFIG_CLKMODE_MASK (0x6U) -#define SCT_CONFIG_CLKMODE_SHIFT (1U) -/*! CLKMODE - SCT Clock Mode - * 0b00..System Clock Mode. The system clock clocks the entire SCT module including all counters and counter prescalers. - * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are - * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The - * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the - * high-performance, sampled-clock mode. - * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including all - * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the - * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. - * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL - * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system - * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than - * the system clock. - */ -#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) - -#define SCT_CONFIG_CKSEL_MASK (0x78U) -#define SCT_CONFIG_CKSEL_SHIFT (3U) -/*! CKSEL - SCT Clock Select. The specific functionality of the designated input/edge is dependent - * on the CLKMODE bit selection in this register. - * 0b0000..Rising edges on input 0 - * 0b0001..Falling edges on input 0 - * 0b0010..Rising edges on input 1 - * 0b0011..Falling edges on input 1 - * 0b0100..Rising edges on input 2 - * 0b0101..Falling edges on input 2 - * 0b0110..Rising edges on input 3 - * 0b0111..Falling edges on input 3 - * 0b1000..Rising edges on input 4 - * 0b1001..Falling edges on input 4 - * 0b1010..Rising edges on input 5 - * 0b1011..Falling edges on input 5 - * 0b1100..Rising edges on input 6 - * 0b1101..Falling edges on input 6 - * 0b1110..Rising edges on input 7 - * 0b1111..Falling edges on input 7 - */ -#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) - -#define SCT_CONFIG_NORELOAD_L_MASK (0x80U) -#define SCT_CONFIG_NORELOAD_L_SHIFT (7U) -/*! NORELOAD_L - No Reload Lower Match - * 0b0..Reload. The default setting. - * 0b1..No Reload. Prevents the lower match registers from being reloaded from their respective reload registers. - */ -#define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK) - -#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) -#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) -/*! NORELOAD_H - No Reload Higher Match - * 0b0..Reload. The default setting. - * 0b1..No Reload. Prevents the higher match registers from being reloaded from their respective reload registers. - */ -#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) - -#define SCT_CONFIG_INSYNC_MASK (0x1FE00U) -#define SCT_CONFIG_INSYNC_SHIFT (9U) -/*! INSYNC - Input Synchronization - */ -#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) - -#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) -#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) -/*! AUTOLIMIT_L - Auto Limit Lower - * 0b0..Disable. - * 0b1..Enable. A match on match register 0 is the LIMIT condition. No need to define an associated event. - */ -#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) - -#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) -#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) -/*! AUTOLIMIT_H - Auto Limit Higher - * 0b0..Disable. - * 0b1..Enable. A match on match register 0 is the LIMIT condition. No need to define an associated event. - */ -#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) -/*! @} */ - -/*! @name CTRLL - SCT_CTRLL register */ -/*! @{ */ - -#define SCT_CTRLL_DOWN_L_MASK (0x1U) -#define SCT_CTRLL_DOWN_L_SHIFT (0U) -/*! DOWN_L - Down Counter Low - * 0b0..Up. The L or unified counter is counting up. - * 0b1..Down. The L or unified counter is counting down. - */ -#define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK) - -#define SCT_CTRLL_STOP_L_MASK (0x2U) -#define SCT_CTRLL_STOP_L_SHIFT (1U) -/*! STOP_L - Stop Counter Low - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK) - -#define SCT_CTRLL_HALT_L_MASK (0x4U) -#define SCT_CTRLL_HALT_L_SHIFT (2U) -/*! HALT_L - Halt Counter Low - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK) - -#define SCT_CTRLL_CLRCTR_L_MASK (0x8U) -#define SCT_CTRLL_CLRCTR_L_SHIFT (3U) -/*! CLRCTR_L - Clear Counter Low - */ -#define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK) - -#define SCT_CTRLL_BIDIR_L_MASK (0x10U) -#define SCT_CTRLL_BIDIR_L_SHIFT (4U) -/*! BIDIR_L - Bidirectional Select Low - * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. - * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK) - -#define SCT_CTRLL_PRE_L_MASK (0x1FE0U) -#define SCT_CTRLL_PRE_L_SHIFT (5U) -/*! PRE_L - Prescaler for Low Counter - */ -#define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK) -/*! @} */ - -/*! @name CTRLH - SCT_CTRLH register */ -/*! @{ */ - -#define SCT_CTRLH_DOWN_H_MASK (0x1U) -#define SCT_CTRLH_DOWN_H_SHIFT (0U) -/*! DOWN_H - Down Counter High - * 0b0..Up. The H counter is counting up. - * 0b1..Down. The H counter is counting down. - */ -#define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK) - -#define SCT_CTRLH_STOP_H_MASK (0x2U) -#define SCT_CTRLH_STOP_H_SHIFT (1U) -/*! STOP_H - Stop Counter High - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK) - -#define SCT_CTRLH_HALT_H_MASK (0x4U) -#define SCT_CTRLH_HALT_H_SHIFT (2U) -/*! HALT_H - Halt Counter High - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK) - -#define SCT_CTRLH_CLRCTR_H_MASK (0x8U) -#define SCT_CTRLH_CLRCTR_H_SHIFT (3U) -/*! CLRCTR_H - Clear Counter High - */ -#define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK) - -#define SCT_CTRLH_BIDIR_H_MASK (0x10U) -#define SCT_CTRLH_BIDIR_H_SHIFT (4U) -/*! BIDIR_H - Bidirectional Select High - * 0b0..Up. The H counter counts up to its limit condition, then is cleared to zero. - * 0b1..Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK) - -#define SCT_CTRLH_PRE_H_MASK (0x1FE0U) -#define SCT_CTRLH_PRE_H_SHIFT (5U) -/*! PRE_H - Prescaler for High Counter - */ -#define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK) -/*! @} */ - -/*! @name CTRL - SCT Control */ -/*! @{ */ - -#define SCT_CTRL_DOWN_L_MASK (0x1U) -#define SCT_CTRL_DOWN_L_SHIFT (0U) -/*! DOWN_L - Down Counter Low - * 0b0..Up. The L or unified counter is counting up. - * 0b1..Down. The L or unified counter is counting down. - */ -#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) - -#define SCT_CTRL_STOP_L_MASK (0x2U) -#define SCT_CTRL_STOP_L_SHIFT (1U) -/*! STOP_L - Stop Counter Low - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) - -#define SCT_CTRL_HALT_L_MASK (0x4U) -#define SCT_CTRL_HALT_L_SHIFT (2U) -/*! HALT_L - Halt Counter Low - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) - -#define SCT_CTRL_CLRCTR_L_MASK (0x8U) -#define SCT_CTRL_CLRCTR_L_SHIFT (3U) -/*! CLRCTR_L - Clear Counter Low - */ -#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) - -#define SCT_CTRL_BIDIR_L_MASK (0x10U) -#define SCT_CTRL_BIDIR_L_SHIFT (4U) -/*! BIDIR_L - Bidirectional Select Low - * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. - * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) - -#define SCT_CTRL_PRE_L_MASK (0x1FE0U) -#define SCT_CTRL_PRE_L_SHIFT (5U) -/*! PRE_L - Prescaler for Low Counter - */ -#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) - -#define SCT_CTRL_DOWN_H_MASK (0x10000U) -#define SCT_CTRL_DOWN_H_SHIFT (16U) -/*! DOWN_H - Down Counter High - * 0b0..Up. The H counter is counting up. - * 0b1..Down. The H counter is counting down. - */ -#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) - -#define SCT_CTRL_STOP_H_MASK (0x20000U) -#define SCT_CTRL_STOP_H_SHIFT (17U) -/*! STOP_H - Stop Counter High - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) - -#define SCT_CTRL_HALT_H_MASK (0x40000U) -#define SCT_CTRL_HALT_H_SHIFT (18U) -/*! HALT_H - Halt Counter High - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) - -#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) -#define SCT_CTRL_CLRCTR_H_SHIFT (19U) -/*! CLRCTR_H - Clear Counter High - */ -#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) - -#define SCT_CTRL_BIDIR_H_MASK (0x100000U) -#define SCT_CTRL_BIDIR_H_SHIFT (20U) -/*! BIDIR_H - Bidirectional Select High - * 0b0..Up. The H counter counts up to its limit condition, then is cleared to zero. - * 0b1..Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) - -#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) -#define SCT_CTRL_PRE_H_SHIFT (21U) -/*! PRE_H - Prescaler for High Counter - */ -#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) -/*! @} */ - -/*! @name LIMITL - SCT_LIMITL register */ -/*! @{ */ - -#define SCT_LIMITL_LIMITL_MASK (0xFFFFU) -#define SCT_LIMITL_LIMITL_SHIFT (0U) -#define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK) -/*! @} */ - -/*! @name LIMITH - SCT_LIMITH register */ -/*! @{ */ - -#define SCT_LIMITH_LIMITH_MASK (0xFFFFU) -#define SCT_LIMITH_LIMITH_SHIFT (0U) -#define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK) -/*! @} */ - -/*! @name LIMIT - SCT Limit Event Select */ -/*! @{ */ - -#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) -#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) -/*! LIMMSK_L - Limit Event Counter Low - */ -#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) - -#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) -#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) -/*! LIMMSK_H - Limit Event Counter High - */ -#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) -/*! @} */ - -/*! @name HALTL - SCT_HALTL register */ -/*! @{ */ - -#define SCT_HALTL_HALTL_MASK (0xFFFFU) -#define SCT_HALTL_HALTL_SHIFT (0U) -#define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK) -/*! @} */ - -/*! @name HALTH - SCT_HALTH register */ -/*! @{ */ - -#define SCT_HALTH_HALTH_MASK (0xFFFFU) -#define SCT_HALTH_HALTH_SHIFT (0U) -#define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK) -/*! @} */ - -/*! @name HALT - Halt Event Select */ -/*! @{ */ - -#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) -#define SCT_HALT_HALTMSK_L_SHIFT (0U) -/*! HALTMSK_L - Halt Event Low - */ -#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) - -#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) -#define SCT_HALT_HALTMSK_H_SHIFT (16U) -/*! HALTMSK_H - Halt Event High - */ -#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) -/*! @} */ - -/*! @name STOPL - SCT_STOPL register */ -/*! @{ */ - -#define SCT_STOPL_STOPL_MASK (0xFFFFU) -#define SCT_STOPL_STOPL_SHIFT (0U) -#define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK) -/*! @} */ - -/*! @name STOPH - SCT_STOPH register */ -/*! @{ */ - -#define SCT_STOPH_STOPH_MASK (0xFFFFU) -#define SCT_STOPH_STOPH_SHIFT (0U) -#define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK) -/*! @} */ - -/*! @name STOP - Stop Event Select */ -/*! @{ */ - -#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) -#define SCT_STOP_STOPMSK_L_SHIFT (0U) -/*! STOPMSK_L - Stop Event Low - */ -#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) - -#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) -#define SCT_STOP_STOPMSK_H_SHIFT (16U) -/*! STOPMSK_H - Stop Event High - */ -#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) -/*! @} */ - -/*! @name STARTL - SCT_STARTL register */ -/*! @{ */ - -#define SCT_STARTL_STARTL_MASK (0xFFFFU) -#define SCT_STARTL_STARTL_SHIFT (0U) -#define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK) -/*! @} */ - -/*! @name STARTH - SCT_STARTH register */ -/*! @{ */ - -#define SCT_STARTH_STARTH_MASK (0xFFFFU) -#define SCT_STARTH_STARTH_SHIFT (0U) -#define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK) -/*! @} */ - -/*! @name START - Start Event Select */ -/*! @{ */ - -#define SCT_START_STARTMSK_L_MASK (0xFFFFU) -#define SCT_START_STARTMSK_L_SHIFT (0U) -/*! STARTMSK_L - If bit n is one, event n clears the CTRL[STOP_L] = 0 (event 0 = bit 0, event 1 = - * bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) - -#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) -#define SCT_START_STARTMSK_H_SHIFT (16U) -/*! STARTMSK_H - If bit n is one, event n clears the CTRL[STOP_H] = 0 (event 0 = bit 16, event 1 = - * bit 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) -/*! @} */ - -/*! @name DITHER - Dither Condition */ -/*! @{ */ - -#define SCT_DITHER_DITHER_L_MASK (0xFFFFU) -#define SCT_DITHER_DITHER_L_SHIFT (0U) -/*! DITHER_L - If bit n is one, event n clears the CTRL[STOP_L] = 0 (event 0 = bit 0, event 1 = bit - * 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_DITHER_DITHER_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_DITHER_DITHER_L_SHIFT)) & SCT_DITHER_DITHER_L_MASK) - -#define SCT_DITHER_DITHER_H_MASK (0xFFFF0000U) -#define SCT_DITHER_DITHER_H_SHIFT (16U) -/*! DITHER_H - If bit n is one, event n clears the CTRL[STOP_H] = 0 (event 0 = bit 16, event 1 = bit - * 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_DITHER_DITHER_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_DITHER_DITHER_H_SHIFT)) & SCT_DITHER_DITHER_H_MASK) -/*! @} */ - -/*! @name COUNTL - SCT_COUNTL register */ -/*! @{ */ - -#define SCT_COUNTL_COUNTL_MASK (0xFFFFU) -#define SCT_COUNTL_COUNTL_SHIFT (0U) -#define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK) -/*! @} */ - -/*! @name COUNTH - SCT_COUNTH register */ -/*! @{ */ - -#define SCT_COUNTH_COUNTH_MASK (0xFFFFU) -#define SCT_COUNTH_COUNTH_SHIFT (0U) -#define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK) -/*! @} */ - -/*! @name COUNT - Counter */ -/*! @{ */ - -#define SCT_COUNT_CTR_L_MASK (0xFFFFU) -#define SCT_COUNT_CTR_L_SHIFT (0U) -/*! CTR_L - Counter Low - */ -#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) - -#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) -#define SCT_COUNT_CTR_H_SHIFT (16U) -/*! CTR_H - Counter High - */ -#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) -/*! @} */ - -/*! @name STATEL - SCT_STATEL register */ -/*! @{ */ - -#define SCT_STATEL_STATEL_MASK (0xFFFFU) -#define SCT_STATEL_STATEL_SHIFT (0U) -#define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK) -/*! @} */ - -/*! @name STATEH - SCT_STATEH register */ -/*! @{ */ - -#define SCT_STATEH_STATEH_MASK (0xFFFFU) -#define SCT_STATEH_STATEH_SHIFT (0U) -#define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK) -/*! @} */ - -/*! @name STATE - State */ -/*! @{ */ - -#define SCT_STATE_STATE_L_MASK (0x1FU) -#define SCT_STATE_STATE_L_SHIFT (0U) -/*! STATE_L - State variable - */ -#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) - -#define SCT_STATE_STATE_H_MASK (0x1F0000U) -#define SCT_STATE_STATE_H_SHIFT (16U) -/*! STATE_H - State variable - */ -#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) -/*! @} */ - -/*! @name INPUT - Input */ -/*! @{ */ - -#define SCT_INPUT_AIN0_MASK (0x1U) -#define SCT_INPUT_AIN0_SHIFT (0U) -/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) - -#define SCT_INPUT_AIN1_MASK (0x2U) -#define SCT_INPUT_AIN1_SHIFT (1U) -/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) - -#define SCT_INPUT_AIN2_MASK (0x4U) -#define SCT_INPUT_AIN2_SHIFT (2U) -/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) - -#define SCT_INPUT_AIN3_MASK (0x8U) -#define SCT_INPUT_AIN3_SHIFT (3U) -/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) - -#define SCT_INPUT_AIN4_MASK (0x10U) -#define SCT_INPUT_AIN4_SHIFT (4U) -/*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) - -#define SCT_INPUT_AIN5_MASK (0x20U) -#define SCT_INPUT_AIN5_SHIFT (5U) -/*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) - -#define SCT_INPUT_AIN6_MASK (0x40U) -#define SCT_INPUT_AIN6_SHIFT (6U) -/*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) - -#define SCT_INPUT_AIN7_MASK (0x80U) -#define SCT_INPUT_AIN7_SHIFT (7U) -/*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) - -#define SCT_INPUT_AIN8_MASK (0x100U) -#define SCT_INPUT_AIN8_SHIFT (8U) -/*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) - -#define SCT_INPUT_AIN9_MASK (0x200U) -#define SCT_INPUT_AIN9_SHIFT (9U) -/*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) - -#define SCT_INPUT_AIN10_MASK (0x400U) -#define SCT_INPUT_AIN10_SHIFT (10U) -/*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) - -#define SCT_INPUT_AIN11_MASK (0x800U) -#define SCT_INPUT_AIN11_SHIFT (11U) -/*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) - -#define SCT_INPUT_AIN12_MASK (0x1000U) -#define SCT_INPUT_AIN12_SHIFT (12U) -/*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) - -#define SCT_INPUT_AIN13_MASK (0x2000U) -#define SCT_INPUT_AIN13_SHIFT (13U) -/*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) - -#define SCT_INPUT_AIN14_MASK (0x4000U) -#define SCT_INPUT_AIN14_SHIFT (14U) -/*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) - -#define SCT_INPUT_AIN15_MASK (0x8000U) -#define SCT_INPUT_AIN15_SHIFT (15U) -/*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) - -#define SCT_INPUT_SIN0_MASK (0x10000U) -#define SCT_INPUT_SIN0_SHIFT (16U) -/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) - -#define SCT_INPUT_SIN1_MASK (0x20000U) -#define SCT_INPUT_SIN1_SHIFT (17U) -/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) - -#define SCT_INPUT_SIN2_MASK (0x40000U) -#define SCT_INPUT_SIN2_SHIFT (18U) -/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) - -#define SCT_INPUT_SIN3_MASK (0x80000U) -#define SCT_INPUT_SIN3_SHIFT (19U) -/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) - -#define SCT_INPUT_SIN4_MASK (0x100000U) -#define SCT_INPUT_SIN4_SHIFT (20U) -/*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) - -#define SCT_INPUT_SIN5_MASK (0x200000U) -#define SCT_INPUT_SIN5_SHIFT (21U) -/*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) - -#define SCT_INPUT_SIN6_MASK (0x400000U) -#define SCT_INPUT_SIN6_SHIFT (22U) -/*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) - -#define SCT_INPUT_SIN7_MASK (0x800000U) -#define SCT_INPUT_SIN7_SHIFT (23U) -/*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) - -#define SCT_INPUT_SIN8_MASK (0x1000000U) -#define SCT_INPUT_SIN8_SHIFT (24U) -/*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) - -#define SCT_INPUT_SIN9_MASK (0x2000000U) -#define SCT_INPUT_SIN9_SHIFT (25U) -/*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) - -#define SCT_INPUT_SIN10_MASK (0x4000000U) -#define SCT_INPUT_SIN10_SHIFT (26U) -/*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) - -#define SCT_INPUT_SIN11_MASK (0x8000000U) -#define SCT_INPUT_SIN11_SHIFT (27U) -/*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) - -#define SCT_INPUT_SIN12_MASK (0x10000000U) -#define SCT_INPUT_SIN12_SHIFT (28U) -/*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) - -#define SCT_INPUT_SIN13_MASK (0x20000000U) -#define SCT_INPUT_SIN13_SHIFT (29U) -/*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) - -#define SCT_INPUT_SIN14_MASK (0x40000000U) -#define SCT_INPUT_SIN14_SHIFT (30U) -/*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) - -#define SCT_INPUT_SIN15_MASK (0x80000000U) -#define SCT_INPUT_SIN15_SHIFT (31U) -/*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) -/*! @} */ - -/*! @name REGMODEL - SCT_REGMODEL register */ -/*! @{ */ - -#define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU) -#define SCT_REGMODEL_REGMODEL_SHIFT (0U) -/*! REGMODEL - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK) - -#define SCT_REGMODEL_REGMOD_L_MASK (0xFFFFU) -#define SCT_REGMODEL_REGMOD_L_SHIFT (0U) -#define SCT_REGMODEL_REGMOD_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMOD_L_SHIFT)) & SCT_REGMODEL_REGMOD_L_MASK) - -#define SCT_REGMODEL_REGMOD_H_MASK (0xFFFF0000U) -#define SCT_REGMODEL_REGMOD_H_SHIFT (16U) -#define SCT_REGMODEL_REGMOD_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMOD_H_SHIFT)) & SCT_REGMODEL_REGMOD_H_MASK) -/*! @} */ - -/*! @name REGMODEH - SCT_REGMODEH register */ -/*! @{ */ - -#define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU) -#define SCT_REGMODEH_REGMODEH_SHIFT (0U) -/*! REGMODEH - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK) - -#define SCT_REGMODEH_REGMOD_L_MASK (0xFFFFU) -#define SCT_REGMODEH_REGMOD_L_SHIFT (0U) -#define SCT_REGMODEH_REGMOD_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMOD_L_SHIFT)) & SCT_REGMODEH_REGMOD_L_MASK) - -#define SCT_REGMODEH_REGMOD_H_MASK (0xFFFF0000U) -#define SCT_REGMODEH_REGMOD_H_SHIFT (16U) -#define SCT_REGMODEH_REGMOD_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMOD_H_SHIFT)) & SCT_REGMODEH_REGMOD_H_MASK) -/*! @} */ - -/*! @name REGMODE - Match/Capture Mode */ -/*! @{ */ - -#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) -#define SCT_REGMODE_REGMOD_L_SHIFT (0U) -#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) - -#define SCT_REGMODE_REGMOD_L0_MASK (0x1U) -#define SCT_REGMODE_REGMOD_L0_SHIFT (0U) -/*! REGMOD_L0 - Register Mode Low n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_L0(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L0_SHIFT)) & SCT_REGMODE_REGMOD_L0_MASK) - -#define SCT_REGMODE_REGMOD_L1_MASK (0x2U) -#define SCT_REGMODE_REGMOD_L1_SHIFT (1U) -/*! REGMOD_L1 - Register Mode Low n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_L1(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L1_SHIFT)) & SCT_REGMODE_REGMOD_L1_MASK) - -#define SCT_REGMODE_REGMOD_L2_MASK (0x4U) -#define SCT_REGMODE_REGMOD_L2_SHIFT (2U) -/*! REGMOD_L2 - Register Mode Low n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_L2(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L2_SHIFT)) & SCT_REGMODE_REGMOD_L2_MASK) - -#define SCT_REGMODE_REGMOD_L3_MASK (0x8U) -#define SCT_REGMODE_REGMOD_L3_SHIFT (3U) -/*! REGMOD_L3 - Register Mode Low n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_L3(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L3_SHIFT)) & SCT_REGMODE_REGMOD_L3_MASK) - -#define SCT_REGMODE_REGMOD_L4_MASK (0x10U) -#define SCT_REGMODE_REGMOD_L4_SHIFT (4U) -/*! REGMOD_L4 - Register Mode Low n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_L4(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L4_SHIFT)) & SCT_REGMODE_REGMOD_L4_MASK) - -#define SCT_REGMODE_REGMOD_L5_MASK (0x20U) -#define SCT_REGMODE_REGMOD_L5_SHIFT (5U) -/*! REGMOD_L5 - Register Mode Low n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_L5(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L5_SHIFT)) & SCT_REGMODE_REGMOD_L5_MASK) - -#define SCT_REGMODE_REGMOD_L6_MASK (0x40U) -#define SCT_REGMODE_REGMOD_L6_SHIFT (6U) -/*! REGMOD_L6 - Register Mode Low n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_L6(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L6_SHIFT)) & SCT_REGMODE_REGMOD_L6_MASK) - -#define SCT_REGMODE_REGMOD_L7_MASK (0x80U) -#define SCT_REGMODE_REGMOD_L7_SHIFT (7U) -/*! REGMOD_L7 - Register Mode Low n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_L7(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L7_SHIFT)) & SCT_REGMODE_REGMOD_L7_MASK) - -#define SCT_REGMODE_REGMOD_L8_MASK (0x100U) -#define SCT_REGMODE_REGMOD_L8_SHIFT (8U) -/*! REGMOD_L8 - Register Mode Low n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_L8(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L8_SHIFT)) & SCT_REGMODE_REGMOD_L8_MASK) - -#define SCT_REGMODE_REGMOD_L9_MASK (0x200U) -#define SCT_REGMODE_REGMOD_L9_SHIFT (9U) -/*! REGMOD_L9 - Register Mode Low n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_L9(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L9_SHIFT)) & SCT_REGMODE_REGMOD_L9_MASK) - -#define SCT_REGMODE_REGMOD_L10_MASK (0x400U) -#define SCT_REGMODE_REGMOD_L10_SHIFT (10U) -/*! REGMOD_L10 - Register Mode Low n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_L10(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L10_SHIFT)) & SCT_REGMODE_REGMOD_L10_MASK) - -#define SCT_REGMODE_REGMOD_L11_MASK (0x800U) -#define SCT_REGMODE_REGMOD_L11_SHIFT (11U) -/*! REGMOD_L11 - Register Mode Low n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_L11(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L11_SHIFT)) & SCT_REGMODE_REGMOD_L11_MASK) - -#define SCT_REGMODE_REGMOD_L12_MASK (0x1000U) -#define SCT_REGMODE_REGMOD_L12_SHIFT (12U) -/*! REGMOD_L12 - Register Mode Low n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_L12(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L12_SHIFT)) & SCT_REGMODE_REGMOD_L12_MASK) - -#define SCT_REGMODE_REGMOD_L13_MASK (0x2000U) -#define SCT_REGMODE_REGMOD_L13_SHIFT (13U) -/*! REGMOD_L13 - Register Mode Low n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_L13(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L13_SHIFT)) & SCT_REGMODE_REGMOD_L13_MASK) - -#define SCT_REGMODE_REGMOD_L14_MASK (0x4000U) -#define SCT_REGMODE_REGMOD_L14_SHIFT (14U) -/*! REGMOD_L14 - Register Mode Low n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_L14(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L14_SHIFT)) & SCT_REGMODE_REGMOD_L14_MASK) - -#define SCT_REGMODE_REGMOD_L15_MASK (0x8000U) -#define SCT_REGMODE_REGMOD_L15_SHIFT (15U) -/*! REGMOD_L15 - Register Mode Low n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_L15(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L15_SHIFT)) & SCT_REGMODE_REGMOD_L15_MASK) - -#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) -#define SCT_REGMODE_REGMOD_H_SHIFT (16U) -#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) - -#define SCT_REGMODE_REGMOD_H0_MASK (0x10000U) -#define SCT_REGMODE_REGMOD_H0_SHIFT (16U) -/*! REGMOD_H0 - Register Mode High n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_H0(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H0_SHIFT)) & SCT_REGMODE_REGMOD_H0_MASK) - -#define SCT_REGMODE_REGMOD_H1_MASK (0x20000U) -#define SCT_REGMODE_REGMOD_H1_SHIFT (17U) -/*! REGMOD_H1 - Register Mode High n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_H1(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H1_SHIFT)) & SCT_REGMODE_REGMOD_H1_MASK) - -#define SCT_REGMODE_REGMOD_H2_MASK (0x40000U) -#define SCT_REGMODE_REGMOD_H2_SHIFT (18U) -/*! REGMOD_H2 - Register Mode High n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_H2(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H2_SHIFT)) & SCT_REGMODE_REGMOD_H2_MASK) - -#define SCT_REGMODE_REGMOD_H3_MASK (0x80000U) -#define SCT_REGMODE_REGMOD_H3_SHIFT (19U) -/*! REGMOD_H3 - Register Mode High n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_H3(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H3_SHIFT)) & SCT_REGMODE_REGMOD_H3_MASK) - -#define SCT_REGMODE_REGMOD_H4_MASK (0x100000U) -#define SCT_REGMODE_REGMOD_H4_SHIFT (20U) -/*! REGMOD_H4 - Register Mode High n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_H4(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H4_SHIFT)) & SCT_REGMODE_REGMOD_H4_MASK) - -#define SCT_REGMODE_REGMOD_H5_MASK (0x200000U) -#define SCT_REGMODE_REGMOD_H5_SHIFT (21U) -/*! REGMOD_H5 - Register Mode High n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_H5(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H5_SHIFT)) & SCT_REGMODE_REGMOD_H5_MASK) - -#define SCT_REGMODE_REGMOD_H6_MASK (0x400000U) -#define SCT_REGMODE_REGMOD_H6_SHIFT (22U) -/*! REGMOD_H6 - Register Mode High n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_H6(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H6_SHIFT)) & SCT_REGMODE_REGMOD_H6_MASK) - -#define SCT_REGMODE_REGMOD_H7_MASK (0x800000U) -#define SCT_REGMODE_REGMOD_H7_SHIFT (23U) -/*! REGMOD_H7 - Register Mode High n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_H7(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H7_SHIFT)) & SCT_REGMODE_REGMOD_H7_MASK) - -#define SCT_REGMODE_REGMOD_H8_MASK (0x1000000U) -#define SCT_REGMODE_REGMOD_H8_SHIFT (24U) -/*! REGMOD_H8 - Register Mode High n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_H8(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H8_SHIFT)) & SCT_REGMODE_REGMOD_H8_MASK) - -#define SCT_REGMODE_REGMOD_H9_MASK (0x2000000U) -#define SCT_REGMODE_REGMOD_H9_SHIFT (25U) -/*! REGMOD_H9 - Register Mode High n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_H9(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H9_SHIFT)) & SCT_REGMODE_REGMOD_H9_MASK) - -#define SCT_REGMODE_REGMOD_H10_MASK (0x4000000U) -#define SCT_REGMODE_REGMOD_H10_SHIFT (26U) -/*! REGMOD_H10 - Register Mode High n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_H10(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H10_SHIFT)) & SCT_REGMODE_REGMOD_H10_MASK) - -#define SCT_REGMODE_REGMOD_H11_MASK (0x8000000U) -#define SCT_REGMODE_REGMOD_H11_SHIFT (27U) -/*! REGMOD_H11 - Register Mode High n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_H11(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H11_SHIFT)) & SCT_REGMODE_REGMOD_H11_MASK) - -#define SCT_REGMODE_REGMOD_H12_MASK (0x10000000U) -#define SCT_REGMODE_REGMOD_H12_SHIFT (28U) -/*! REGMOD_H12 - Register Mode High n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_H12(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H12_SHIFT)) & SCT_REGMODE_REGMOD_H12_MASK) - -#define SCT_REGMODE_REGMOD_H13_MASK (0x20000000U) -#define SCT_REGMODE_REGMOD_H13_SHIFT (29U) -/*! REGMOD_H13 - Register Mode High n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_H13(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H13_SHIFT)) & SCT_REGMODE_REGMOD_H13_MASK) - -#define SCT_REGMODE_REGMOD_H14_MASK (0x40000000U) -#define SCT_REGMODE_REGMOD_H14_SHIFT (30U) -/*! REGMOD_H14 - Register Mode High n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_H14(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H14_SHIFT)) & SCT_REGMODE_REGMOD_H14_MASK) - -#define SCT_REGMODE_REGMOD_H15_MASK (0x80000000U) -#define SCT_REGMODE_REGMOD_H15_SHIFT (31U) -/*! REGMOD_H15 - Register Mode High n - * 0b0..Match. Register n operates as a match register - * 0b1..Capture. Register n operates as a capture register - */ -#define SCT_REGMODE_REGMOD_H15(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H15_SHIFT)) & SCT_REGMODE_REGMOD_H15_MASK) -/*! @} */ - -/*! @name OUTPUT - Output */ -/*! @{ */ - -#define SCT_OUTPUT_OUT0_MASK (0x1U) -#define SCT_OUTPUT_OUT0_SHIFT (0U) -/*! OUT0 - Output n - * 0b0..Writing a 0 forces the corresponding output low - * 0b1..Writing a 1 forces the corresponding output high - */ -#define SCT_OUTPUT_OUT0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT0_SHIFT)) & SCT_OUTPUT_OUT0_MASK) - -#define SCT_OUTPUT_OUT1_MASK (0x2U) -#define SCT_OUTPUT_OUT1_SHIFT (1U) -/*! OUT1 - Output n - * 0b0..Writing a 0 forces the corresponding output low - * 0b1..Writing a 1 forces the corresponding output high - */ -#define SCT_OUTPUT_OUT1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT1_SHIFT)) & SCT_OUTPUT_OUT1_MASK) - -#define SCT_OUTPUT_OUT2_MASK (0x4U) -#define SCT_OUTPUT_OUT2_SHIFT (2U) -/*! OUT2 - Output n - * 0b0..Writing a 0 forces the corresponding output low - * 0b1..Writing a 1 forces the corresponding output high - */ -#define SCT_OUTPUT_OUT2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT2_SHIFT)) & SCT_OUTPUT_OUT2_MASK) - -#define SCT_OUTPUT_OUT3_MASK (0x8U) -#define SCT_OUTPUT_OUT3_SHIFT (3U) -/*! OUT3 - Output n - * 0b0..Writing a 0 forces the corresponding output low - * 0b1..Writing a 1 forces the corresponding output high - */ -#define SCT_OUTPUT_OUT3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT3_SHIFT)) & SCT_OUTPUT_OUT3_MASK) - -#define SCT_OUTPUT_OUT4_MASK (0x10U) -#define SCT_OUTPUT_OUT4_SHIFT (4U) -/*! OUT4 - Output n - * 0b0..Writing a 0 forces the corresponding output low - * 0b1..Writing a 1 forces the corresponding output high - */ -#define SCT_OUTPUT_OUT4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT4_SHIFT)) & SCT_OUTPUT_OUT4_MASK) - -#define SCT_OUTPUT_OUT5_MASK (0x20U) -#define SCT_OUTPUT_OUT5_SHIFT (5U) -/*! OUT5 - Output n - * 0b0..Writing a 0 forces the corresponding output low - * 0b1..Writing a 1 forces the corresponding output high - */ -#define SCT_OUTPUT_OUT5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT5_SHIFT)) & SCT_OUTPUT_OUT5_MASK) - -#define SCT_OUTPUT_OUT6_MASK (0x40U) -#define SCT_OUTPUT_OUT6_SHIFT (6U) -/*! OUT6 - Output n - * 0b0..Writing a 0 forces the corresponding output low - * 0b1..Writing a 1 forces the corresponding output high - */ -#define SCT_OUTPUT_OUT6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT6_SHIFT)) & SCT_OUTPUT_OUT6_MASK) - -#define SCT_OUTPUT_OUT7_MASK (0x80U) -#define SCT_OUTPUT_OUT7_SHIFT (7U) -/*! OUT7 - Output n - * 0b0..Writing a 0 forces the corresponding output low - * 0b1..Writing a 1 forces the corresponding output high - */ -#define SCT_OUTPUT_OUT7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT7_SHIFT)) & SCT_OUTPUT_OUT7_MASK) - -#define SCT_OUTPUT_OUT8_MASK (0x100U) -#define SCT_OUTPUT_OUT8_SHIFT (8U) -/*! OUT8 - Output n - * 0b0..Writing a 0 forces the corresponding output low - * 0b1..Writing a 1 forces the corresponding output high - */ -#define SCT_OUTPUT_OUT8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT8_SHIFT)) & SCT_OUTPUT_OUT8_MASK) - -#define SCT_OUTPUT_OUT9_MASK (0x200U) -#define SCT_OUTPUT_OUT9_SHIFT (9U) -/*! OUT9 - Output n - * 0b0..Writing a 0 forces the corresponding output low - * 0b1..Writing a 1 forces the corresponding output high - */ -#define SCT_OUTPUT_OUT9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT9_SHIFT)) & SCT_OUTPUT_OUT9_MASK) -/*! @} */ - -/*! @name OUTPUTDIRCTRL - Output Counter Direction Control */ -/*! @{ */ - -#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) -#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) -/*! SETCLR0 - Set/Clear Operation on Output n - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - * 0b11..Reserved. Do not program this value. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) -#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) -/*! SETCLR1 - Set/Clear Operation on Output n - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - * 0b11..Reserved. Do not program this value. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) -#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) -/*! SETCLR2 - Set/Clear Operation on Output n - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - * 0b11..Reserved. Do not program this value. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) -#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) -/*! SETCLR3 - Set/Clear Operation on Output n - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - * 0b11..Reserved. Do not program this value. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) -#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) -/*! SETCLR4 - Set/Clear Operation on Output n - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - * 0b11..Reserved. Do not program this value. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) -#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) -/*! SETCLR5 - Set/Clear Operation on Output n - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - * 0b11..Reserved. Do not program this value. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) -#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) -/*! SETCLR6 - Set/Clear Operation on Output n - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - * 0b11..Reserved. Do not program this value. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) -#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) -/*! SETCLR7 - Set/Clear Operation on Output n - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - * 0b11..Reserved. Do not program this value. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) -#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) -/*! SETCLR8 - Set/Clear Operation on Output n - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - * 0b11..Reserved. Do not program this value. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) -#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) -/*! SETCLR9 - Set/Clear Operation on Output n - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - * 0b11..Reserved. Do not program this value. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) -/*! @} */ - -/*! @name RES - Output Conflict Resolution */ -/*! @{ */ - -#define SCT_RES_O0RES_MASK (0x3U) -#define SCT_RES_O0RES_SHIFT (0U) -/*! O0RES - Effect of simultaneous set and clear on output n - * 0b00..No change - * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field) - * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field) - * 0b11..Toggle output - */ -#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) - -#define SCT_RES_O1RES_MASK (0xCU) -#define SCT_RES_O1RES_SHIFT (2U) -/*! O1RES - Effect of simultaneous set and clear on output n - * 0b00..No change - * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field) - * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field) - * 0b11..Toggle output - */ -#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) - -#define SCT_RES_O2RES_MASK (0x30U) -#define SCT_RES_O2RES_SHIFT (4U) -/*! O2RES - Effect of simultaneous set and clear on output n - * 0b00..No change - * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field) - * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field) - * 0b11..Toggle output - */ -#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) - -#define SCT_RES_O3RES_MASK (0xC0U) -#define SCT_RES_O3RES_SHIFT (6U) -/*! O3RES - Effect of simultaneous set and clear on output n - * 0b00..No change - * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field) - * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field) - * 0b11..Toggle output - */ -#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) - -#define SCT_RES_O4RES_MASK (0x300U) -#define SCT_RES_O4RES_SHIFT (8U) -/*! O4RES - Effect of simultaneous set and clear on output n - * 0b00..No change - * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field) - * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field) - * 0b11..Toggle output - */ -#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) - -#define SCT_RES_O5RES_MASK (0xC00U) -#define SCT_RES_O5RES_SHIFT (10U) -/*! O5RES - Effect of simultaneous set and clear on output n - * 0b00..No change - * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field) - * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field) - * 0b11..Toggle output - */ -#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) - -#define SCT_RES_O6RES_MASK (0x3000U) -#define SCT_RES_O6RES_SHIFT (12U) -/*! O6RES - Effect of simultaneous set and clear on output n - * 0b00..No change - * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field) - * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field) - * 0b11..Toggle output - */ -#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) - -#define SCT_RES_O7RES_MASK (0xC000U) -#define SCT_RES_O7RES_SHIFT (14U) -/*! O7RES - Effect of simultaneous set and clear on output n - * 0b00..No change - * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field) - * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field) - * 0b11..Toggle output - */ -#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) - -#define SCT_RES_O8RES_MASK (0x30000U) -#define SCT_RES_O8RES_SHIFT (16U) -/*! O8RES - Effect of simultaneous set and clear on output n - * 0b00..No change - * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field) - * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field) - * 0b11..Toggle output - */ -#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) - -#define SCT_RES_O9RES_MASK (0xC0000U) -#define SCT_RES_O9RES_SHIFT (18U) -/*! O9RES - Effect of simultaneous set and clear on output n - * 0b00..No change - * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field) - * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field) - * 0b11..Toggle output - */ -#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) -/*! @} */ - -/*! @name DMAREQ0 - DMA Request 0 */ -/*! @{ */ - -#define SCT_DMAREQ0_DEV_0_MASK (0x1U) -#define SCT_DMAREQ0_DEV_0_SHIFT (0U) -/*! DEV_0 - DMA Request Event n - */ -#define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK) - -#define SCT_DMAREQ0_DEV_1_MASK (0x2U) -#define SCT_DMAREQ0_DEV_1_SHIFT (1U) -/*! DEV_1 - DMA Request Event n - */ -#define SCT_DMAREQ0_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_1_SHIFT)) & SCT_DMAREQ0_DEV_1_MASK) - -#define SCT_DMAREQ0_DEV_2_MASK (0x4U) -#define SCT_DMAREQ0_DEV_2_SHIFT (2U) -/*! DEV_2 - DMA Request Event n - */ -#define SCT_DMAREQ0_DEV_2(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_2_SHIFT)) & SCT_DMAREQ0_DEV_2_MASK) - -#define SCT_DMAREQ0_DEV_3_MASK (0x8U) -#define SCT_DMAREQ0_DEV_3_SHIFT (3U) -/*! DEV_3 - DMA Request Event n - */ -#define SCT_DMAREQ0_DEV_3(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_3_SHIFT)) & SCT_DMAREQ0_DEV_3_MASK) - -#define SCT_DMAREQ0_DEV_4_MASK (0x10U) -#define SCT_DMAREQ0_DEV_4_SHIFT (4U) -/*! DEV_4 - DMA Request Event n - */ -#define SCT_DMAREQ0_DEV_4(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_4_SHIFT)) & SCT_DMAREQ0_DEV_4_MASK) - -#define SCT_DMAREQ0_DEV_5_MASK (0x20U) -#define SCT_DMAREQ0_DEV_5_SHIFT (5U) -/*! DEV_5 - DMA Request Event n - */ -#define SCT_DMAREQ0_DEV_5(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_5_SHIFT)) & SCT_DMAREQ0_DEV_5_MASK) - -#define SCT_DMAREQ0_DEV_6_MASK (0x40U) -#define SCT_DMAREQ0_DEV_6_SHIFT (6U) -/*! DEV_6 - DMA Request Event n - */ -#define SCT_DMAREQ0_DEV_6(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_6_SHIFT)) & SCT_DMAREQ0_DEV_6_MASK) - -#define SCT_DMAREQ0_DEV_7_MASK (0x80U) -#define SCT_DMAREQ0_DEV_7_SHIFT (7U) -/*! DEV_7 - DMA Request Event n - */ -#define SCT_DMAREQ0_DEV_7(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_7_SHIFT)) & SCT_DMAREQ0_DEV_7_MASK) - -#define SCT_DMAREQ0_DEV_8_MASK (0x100U) -#define SCT_DMAREQ0_DEV_8_SHIFT (8U) -/*! DEV_8 - DMA Request Event n - */ -#define SCT_DMAREQ0_DEV_8(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_8_SHIFT)) & SCT_DMAREQ0_DEV_8_MASK) - -#define SCT_DMAREQ0_DEV_9_MASK (0x200U) -#define SCT_DMAREQ0_DEV_9_SHIFT (9U) -/*! DEV_9 - DMA Request Event n - */ -#define SCT_DMAREQ0_DEV_9(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_9_SHIFT)) & SCT_DMAREQ0_DEV_9_MASK) - -#define SCT_DMAREQ0_DEV_10_MASK (0x400U) -#define SCT_DMAREQ0_DEV_10_SHIFT (10U) -/*! DEV_10 - DMA Request Event n - */ -#define SCT_DMAREQ0_DEV_10(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_10_SHIFT)) & SCT_DMAREQ0_DEV_10_MASK) - -#define SCT_DMAREQ0_DEV_11_MASK (0x800U) -#define SCT_DMAREQ0_DEV_11_SHIFT (11U) -/*! DEV_11 - DMA Request Event n - */ -#define SCT_DMAREQ0_DEV_11(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_11_SHIFT)) & SCT_DMAREQ0_DEV_11_MASK) - -#define SCT_DMAREQ0_DEV_12_MASK (0x1000U) -#define SCT_DMAREQ0_DEV_12_SHIFT (12U) -/*! DEV_12 - DMA Request Event n - */ -#define SCT_DMAREQ0_DEV_12(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_12_SHIFT)) & SCT_DMAREQ0_DEV_12_MASK) - -#define SCT_DMAREQ0_DEV_13_MASK (0x2000U) -#define SCT_DMAREQ0_DEV_13_SHIFT (13U) -/*! DEV_13 - DMA Request Event n - */ -#define SCT_DMAREQ0_DEV_13(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_13_SHIFT)) & SCT_DMAREQ0_DEV_13_MASK) - -#define SCT_DMAREQ0_DEV_14_MASK (0x4000U) -#define SCT_DMAREQ0_DEV_14_SHIFT (14U) -/*! DEV_14 - DMA Request Event n - */ -#define SCT_DMAREQ0_DEV_14(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_14_SHIFT)) & SCT_DMAREQ0_DEV_14_MASK) - -#define SCT_DMAREQ0_DEV_15_MASK (0x8000U) -#define SCT_DMAREQ0_DEV_15_SHIFT (15U) -/*! DEV_15 - DMA Request Event n - */ -#define SCT_DMAREQ0_DEV_15(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_15_SHIFT)) & SCT_DMAREQ0_DEV_15_MASK) - -#define SCT_DMAREQ0_DRL0_MASK (0x40000000U) -#define SCT_DMAREQ0_DRL0_SHIFT (30U) -/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. - */ -#define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK) - -#define SCT_DMAREQ0_DRQ0_MASK (0x80000000U) -#define SCT_DMAREQ0_DRQ0_SHIFT (31U) -/*! DRQ0 - DMA Request 0 State - */ -#define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK) -/*! @} */ - -/*! @name DMAREQ1 - DMA Request 1 */ -/*! @{ */ - -#define SCT_DMAREQ1_DEV_0_MASK (0x1U) -#define SCT_DMAREQ1_DEV_0_SHIFT (0U) -/*! DEV_0 - DMA Request Event n - */ -#define SCT_DMAREQ1_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_0_SHIFT)) & SCT_DMAREQ1_DEV_0_MASK) - -#define SCT_DMAREQ1_DEV_1_MASK (0x2U) -#define SCT_DMAREQ1_DEV_1_SHIFT (1U) -/*! DEV_1 - DMA Request Event n - */ -#define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK) - -#define SCT_DMAREQ1_DEV_2_MASK (0x4U) -#define SCT_DMAREQ1_DEV_2_SHIFT (2U) -/*! DEV_2 - DMA Request Event n - */ -#define SCT_DMAREQ1_DEV_2(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_2_SHIFT)) & SCT_DMAREQ1_DEV_2_MASK) - -#define SCT_DMAREQ1_DEV_3_MASK (0x8U) -#define SCT_DMAREQ1_DEV_3_SHIFT (3U) -/*! DEV_3 - DMA Request Event n - */ -#define SCT_DMAREQ1_DEV_3(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_3_SHIFT)) & SCT_DMAREQ1_DEV_3_MASK) - -#define SCT_DMAREQ1_DEV_4_MASK (0x10U) -#define SCT_DMAREQ1_DEV_4_SHIFT (4U) -/*! DEV_4 - DMA Request Event n - */ -#define SCT_DMAREQ1_DEV_4(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_4_SHIFT)) & SCT_DMAREQ1_DEV_4_MASK) - -#define SCT_DMAREQ1_DEV_5_MASK (0x20U) -#define SCT_DMAREQ1_DEV_5_SHIFT (5U) -/*! DEV_5 - DMA Request Event n - */ -#define SCT_DMAREQ1_DEV_5(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_5_SHIFT)) & SCT_DMAREQ1_DEV_5_MASK) - -#define SCT_DMAREQ1_DEV_6_MASK (0x40U) -#define SCT_DMAREQ1_DEV_6_SHIFT (6U) -/*! DEV_6 - DMA Request Event n - */ -#define SCT_DMAREQ1_DEV_6(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_6_SHIFT)) & SCT_DMAREQ1_DEV_6_MASK) - -#define SCT_DMAREQ1_DEV_7_MASK (0x80U) -#define SCT_DMAREQ1_DEV_7_SHIFT (7U) -/*! DEV_7 - DMA Request Event n - */ -#define SCT_DMAREQ1_DEV_7(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_7_SHIFT)) & SCT_DMAREQ1_DEV_7_MASK) - -#define SCT_DMAREQ1_DEV_8_MASK (0x100U) -#define SCT_DMAREQ1_DEV_8_SHIFT (8U) -/*! DEV_8 - DMA Request Event n - */ -#define SCT_DMAREQ1_DEV_8(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_8_SHIFT)) & SCT_DMAREQ1_DEV_8_MASK) - -#define SCT_DMAREQ1_DEV_9_MASK (0x200U) -#define SCT_DMAREQ1_DEV_9_SHIFT (9U) -/*! DEV_9 - DMA Request Event n - */ -#define SCT_DMAREQ1_DEV_9(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_9_SHIFT)) & SCT_DMAREQ1_DEV_9_MASK) - -#define SCT_DMAREQ1_DEV_10_MASK (0x400U) -#define SCT_DMAREQ1_DEV_10_SHIFT (10U) -/*! DEV_10 - DMA Request Event n - */ -#define SCT_DMAREQ1_DEV_10(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_10_SHIFT)) & SCT_DMAREQ1_DEV_10_MASK) - -#define SCT_DMAREQ1_DEV_11_MASK (0x800U) -#define SCT_DMAREQ1_DEV_11_SHIFT (11U) -/*! DEV_11 - DMA Request Event n - */ -#define SCT_DMAREQ1_DEV_11(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_11_SHIFT)) & SCT_DMAREQ1_DEV_11_MASK) - -#define SCT_DMAREQ1_DEV_12_MASK (0x1000U) -#define SCT_DMAREQ1_DEV_12_SHIFT (12U) -/*! DEV_12 - DMA Request Event n - */ -#define SCT_DMAREQ1_DEV_12(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_12_SHIFT)) & SCT_DMAREQ1_DEV_12_MASK) - -#define SCT_DMAREQ1_DEV_13_MASK (0x2000U) -#define SCT_DMAREQ1_DEV_13_SHIFT (13U) -/*! DEV_13 - DMA Request Event n - */ -#define SCT_DMAREQ1_DEV_13(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_13_SHIFT)) & SCT_DMAREQ1_DEV_13_MASK) - -#define SCT_DMAREQ1_DEV_14_MASK (0x4000U) -#define SCT_DMAREQ1_DEV_14_SHIFT (14U) -/*! DEV_14 - DMA Request Event n - */ -#define SCT_DMAREQ1_DEV_14(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_14_SHIFT)) & SCT_DMAREQ1_DEV_14_MASK) - -#define SCT_DMAREQ1_DEV_15_MASK (0x8000U) -#define SCT_DMAREQ1_DEV_15_SHIFT (15U) -/*! DEV_15 - DMA Request Event n - */ -#define SCT_DMAREQ1_DEV_15(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_15_SHIFT)) & SCT_DMAREQ1_DEV_15_MASK) - -#define SCT_DMAREQ1_DRL1_MASK (0x40000000U) -#define SCT_DMAREQ1_DRL1_SHIFT (30U) -/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. - */ -#define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK) - -#define SCT_DMAREQ1_DRQ1_MASK (0x80000000U) -#define SCT_DMAREQ1_DRQ1_SHIFT (31U) -/*! DRQ1 - DMA Request 1 State - */ -#define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK) -/*! @} */ - -/*! @name EVEN - Event Interrupt Enable */ -/*! @{ */ - -#define SCT_EVEN_IEN0_MASK (0x1U) -#define SCT_EVEN_IEN0_SHIFT (0U) -/*! IEN0 - Event Interrupt Enable n - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_EVEN_IEN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN0_SHIFT)) & SCT_EVEN_IEN0_MASK) - -#define SCT_EVEN_IEN1_MASK (0x2U) -#define SCT_EVEN_IEN1_SHIFT (1U) -/*! IEN1 - Event Interrupt Enable n - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_EVEN_IEN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN1_SHIFT)) & SCT_EVEN_IEN1_MASK) - -#define SCT_EVEN_IEN2_MASK (0x4U) -#define SCT_EVEN_IEN2_SHIFT (2U) -/*! IEN2 - Event Interrupt Enable n - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_EVEN_IEN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN2_SHIFT)) & SCT_EVEN_IEN2_MASK) - -#define SCT_EVEN_IEN3_MASK (0x8U) -#define SCT_EVEN_IEN3_SHIFT (3U) -/*! IEN3 - Event Interrupt Enable n - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_EVEN_IEN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN3_SHIFT)) & SCT_EVEN_IEN3_MASK) - -#define SCT_EVEN_IEN4_MASK (0x10U) -#define SCT_EVEN_IEN4_SHIFT (4U) -/*! IEN4 - Event Interrupt Enable n - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_EVEN_IEN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN4_SHIFT)) & SCT_EVEN_IEN4_MASK) - -#define SCT_EVEN_IEN5_MASK (0x20U) -#define SCT_EVEN_IEN5_SHIFT (5U) -/*! IEN5 - Event Interrupt Enable n - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_EVEN_IEN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN5_SHIFT)) & SCT_EVEN_IEN5_MASK) - -#define SCT_EVEN_IEN6_MASK (0x40U) -#define SCT_EVEN_IEN6_SHIFT (6U) -/*! IEN6 - Event Interrupt Enable n - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_EVEN_IEN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN6_SHIFT)) & SCT_EVEN_IEN6_MASK) - -#define SCT_EVEN_IEN7_MASK (0x80U) -#define SCT_EVEN_IEN7_SHIFT (7U) -/*! IEN7 - Event Interrupt Enable n - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_EVEN_IEN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN7_SHIFT)) & SCT_EVEN_IEN7_MASK) - -#define SCT_EVEN_IEN8_MASK (0x100U) -#define SCT_EVEN_IEN8_SHIFT (8U) -/*! IEN8 - Event Interrupt Enable n - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_EVEN_IEN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN8_SHIFT)) & SCT_EVEN_IEN8_MASK) - -#define SCT_EVEN_IEN9_MASK (0x200U) -#define SCT_EVEN_IEN9_SHIFT (9U) -/*! IEN9 - Event Interrupt Enable n - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_EVEN_IEN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN9_SHIFT)) & SCT_EVEN_IEN9_MASK) - -#define SCT_EVEN_IEN10_MASK (0x400U) -#define SCT_EVEN_IEN10_SHIFT (10U) -/*! IEN10 - Event Interrupt Enable n - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_EVEN_IEN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN10_SHIFT)) & SCT_EVEN_IEN10_MASK) - -#define SCT_EVEN_IEN11_MASK (0x800U) -#define SCT_EVEN_IEN11_SHIFT (11U) -/*! IEN11 - Event Interrupt Enable n - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_EVEN_IEN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN11_SHIFT)) & SCT_EVEN_IEN11_MASK) - -#define SCT_EVEN_IEN12_MASK (0x1000U) -#define SCT_EVEN_IEN12_SHIFT (12U) -/*! IEN12 - Event Interrupt Enable n - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_EVEN_IEN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN12_SHIFT)) & SCT_EVEN_IEN12_MASK) - -#define SCT_EVEN_IEN13_MASK (0x2000U) -#define SCT_EVEN_IEN13_SHIFT (13U) -/*! IEN13 - Event Interrupt Enable n - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_EVEN_IEN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN13_SHIFT)) & SCT_EVEN_IEN13_MASK) - -#define SCT_EVEN_IEN14_MASK (0x4000U) -#define SCT_EVEN_IEN14_SHIFT (14U) -/*! IEN14 - Event Interrupt Enable n - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_EVEN_IEN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN14_SHIFT)) & SCT_EVEN_IEN14_MASK) - -#define SCT_EVEN_IEN15_MASK (0x8000U) -#define SCT_EVEN_IEN15_SHIFT (15U) -/*! IEN15 - Event Interrupt Enable n - * 0b0..Disable - * 0b1..Enable - */ -#define SCT_EVEN_IEN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN15_SHIFT)) & SCT_EVEN_IEN15_MASK) -/*! @} */ - -/*! @name EVFLAG - Event Flag */ -/*! @{ */ - -#define SCT_EVFLAG_FLAG0_MASK (0x1U) -#define SCT_EVFLAG_FLAG0_SHIFT (0U) -/*! FLAG0 - Event Flag n - * 0b0..No Flag - * 0b1..Event n Flag - */ -#define SCT_EVFLAG_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG0_SHIFT)) & SCT_EVFLAG_FLAG0_MASK) - -#define SCT_EVFLAG_FLAG1_MASK (0x2U) -#define SCT_EVFLAG_FLAG1_SHIFT (1U) -/*! FLAG1 - Event Flag n - * 0b0..No Flag - * 0b1..Event n Flag - */ -#define SCT_EVFLAG_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG1_SHIFT)) & SCT_EVFLAG_FLAG1_MASK) - -#define SCT_EVFLAG_FLAG2_MASK (0x4U) -#define SCT_EVFLAG_FLAG2_SHIFT (2U) -/*! FLAG2 - Event Flag n - * 0b0..No Flag - * 0b1..Event n Flag - */ -#define SCT_EVFLAG_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG2_SHIFT)) & SCT_EVFLAG_FLAG2_MASK) - -#define SCT_EVFLAG_FLAG3_MASK (0x8U) -#define SCT_EVFLAG_FLAG3_SHIFT (3U) -/*! FLAG3 - Event Flag n - * 0b0..No Flag - * 0b1..Event n Flag - */ -#define SCT_EVFLAG_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG3_SHIFT)) & SCT_EVFLAG_FLAG3_MASK) - -#define SCT_EVFLAG_FLAG4_MASK (0x10U) -#define SCT_EVFLAG_FLAG4_SHIFT (4U) -/*! FLAG4 - Event Flag n - * 0b0..No Flag - * 0b1..Event n Flag - */ -#define SCT_EVFLAG_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG4_SHIFT)) & SCT_EVFLAG_FLAG4_MASK) - -#define SCT_EVFLAG_FLAG5_MASK (0x20U) -#define SCT_EVFLAG_FLAG5_SHIFT (5U) -/*! FLAG5 - Event Flag n - * 0b0..No Flag - * 0b1..Event n Flag - */ -#define SCT_EVFLAG_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG5_SHIFT)) & SCT_EVFLAG_FLAG5_MASK) - -#define SCT_EVFLAG_FLAG6_MASK (0x40U) -#define SCT_EVFLAG_FLAG6_SHIFT (6U) -/*! FLAG6 - Event Flag n - * 0b0..No Flag - * 0b1..Event n Flag - */ -#define SCT_EVFLAG_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG6_SHIFT)) & SCT_EVFLAG_FLAG6_MASK) - -#define SCT_EVFLAG_FLAG7_MASK (0x80U) -#define SCT_EVFLAG_FLAG7_SHIFT (7U) -/*! FLAG7 - Event Flag n - * 0b0..No Flag - * 0b1..Event n Flag - */ -#define SCT_EVFLAG_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG7_SHIFT)) & SCT_EVFLAG_FLAG7_MASK) - -#define SCT_EVFLAG_FLAG8_MASK (0x100U) -#define SCT_EVFLAG_FLAG8_SHIFT (8U) -/*! FLAG8 - Event Flag n - * 0b0..No Flag - * 0b1..Event n Flag - */ -#define SCT_EVFLAG_FLAG8(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG8_SHIFT)) & SCT_EVFLAG_FLAG8_MASK) - -#define SCT_EVFLAG_FLAG9_MASK (0x200U) -#define SCT_EVFLAG_FLAG9_SHIFT (9U) -/*! FLAG9 - Event Flag n - * 0b0..No Flag - * 0b1..Event n Flag - */ -#define SCT_EVFLAG_FLAG9(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG9_SHIFT)) & SCT_EVFLAG_FLAG9_MASK) - -#define SCT_EVFLAG_FLAG10_MASK (0x400U) -#define SCT_EVFLAG_FLAG10_SHIFT (10U) -/*! FLAG10 - Event Flag n - * 0b0..No Flag - * 0b1..Event n Flag - */ -#define SCT_EVFLAG_FLAG10(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG10_SHIFT)) & SCT_EVFLAG_FLAG10_MASK) - -#define SCT_EVFLAG_FLAG11_MASK (0x800U) -#define SCT_EVFLAG_FLAG11_SHIFT (11U) -/*! FLAG11 - Event Flag n - * 0b0..No Flag - * 0b1..Event n Flag - */ -#define SCT_EVFLAG_FLAG11(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG11_SHIFT)) & SCT_EVFLAG_FLAG11_MASK) - -#define SCT_EVFLAG_FLAG12_MASK (0x1000U) -#define SCT_EVFLAG_FLAG12_SHIFT (12U) -/*! FLAG12 - Event Flag n - * 0b0..No Flag - * 0b1..Event n Flag - */ -#define SCT_EVFLAG_FLAG12(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG12_SHIFT)) & SCT_EVFLAG_FLAG12_MASK) - -#define SCT_EVFLAG_FLAG13_MASK (0x2000U) -#define SCT_EVFLAG_FLAG13_SHIFT (13U) -/*! FLAG13 - Event Flag n - * 0b0..No Flag - * 0b1..Event n Flag - */ -#define SCT_EVFLAG_FLAG13(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG13_SHIFT)) & SCT_EVFLAG_FLAG13_MASK) - -#define SCT_EVFLAG_FLAG14_MASK (0x4000U) -#define SCT_EVFLAG_FLAG14_SHIFT (14U) -/*! FLAG14 - Event Flag n - * 0b0..No Flag - * 0b1..Event n Flag - */ -#define SCT_EVFLAG_FLAG14(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG14_SHIFT)) & SCT_EVFLAG_FLAG14_MASK) - -#define SCT_EVFLAG_FLAG15_MASK (0x8000U) -#define SCT_EVFLAG_FLAG15_SHIFT (15U) -/*! FLAG15 - Event Flag n - * 0b0..No Flag - * 0b1..Event n Flag - */ -#define SCT_EVFLAG_FLAG15(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG15_SHIFT)) & SCT_EVFLAG_FLAG15_MASK) -/*! @} */ - -/*! @name CONEN - Conflict Interrupt Enable */ -/*! @{ */ - -#define SCT_CONEN_NCEN0_MASK (0x1U) -#define SCT_CONEN_NCEN0_SHIFT (0U) -/*! NCEN0 - No Change Conflict Event/Interrupt Enable - * 0b0..No interrupt - * 0b1..Interrupt - */ -#define SCT_CONEN_NCEN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN0_SHIFT)) & SCT_CONEN_NCEN0_MASK) - -#define SCT_CONEN_NCEN1_MASK (0x2U) -#define SCT_CONEN_NCEN1_SHIFT (1U) -/*! NCEN1 - No Change Conflict Event/Interrupt Enable - * 0b0..No interrupt - * 0b1..Interrupt - */ -#define SCT_CONEN_NCEN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN1_SHIFT)) & SCT_CONEN_NCEN1_MASK) - -#define SCT_CONEN_NCEN2_MASK (0x4U) -#define SCT_CONEN_NCEN2_SHIFT (2U) -/*! NCEN2 - No Change Conflict Event/Interrupt Enable - * 0b0..No interrupt - * 0b1..Interrupt - */ -#define SCT_CONEN_NCEN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN2_SHIFT)) & SCT_CONEN_NCEN2_MASK) - -#define SCT_CONEN_NCEN3_MASK (0x8U) -#define SCT_CONEN_NCEN3_SHIFT (3U) -/*! NCEN3 - No Change Conflict Event/Interrupt Enable - * 0b0..No interrupt - * 0b1..Interrupt - */ -#define SCT_CONEN_NCEN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN3_SHIFT)) & SCT_CONEN_NCEN3_MASK) - -#define SCT_CONEN_NCEN4_MASK (0x10U) -#define SCT_CONEN_NCEN4_SHIFT (4U) -/*! NCEN4 - No Change Conflict Event/Interrupt Enable - * 0b0..No interrupt - * 0b1..Interrupt - */ -#define SCT_CONEN_NCEN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN4_SHIFT)) & SCT_CONEN_NCEN4_MASK) - -#define SCT_CONEN_NCEN5_MASK (0x20U) -#define SCT_CONEN_NCEN5_SHIFT (5U) -/*! NCEN5 - No Change Conflict Event/Interrupt Enable - * 0b0..No interrupt - * 0b1..Interrupt - */ -#define SCT_CONEN_NCEN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN5_SHIFT)) & SCT_CONEN_NCEN5_MASK) - -#define SCT_CONEN_NCEN6_MASK (0x40U) -#define SCT_CONEN_NCEN6_SHIFT (6U) -/*! NCEN6 - No Change Conflict Event/Interrupt Enable - * 0b0..No interrupt - * 0b1..Interrupt - */ -#define SCT_CONEN_NCEN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN6_SHIFT)) & SCT_CONEN_NCEN6_MASK) - -#define SCT_CONEN_NCEN7_MASK (0x80U) -#define SCT_CONEN_NCEN7_SHIFT (7U) -/*! NCEN7 - No Change Conflict Event/Interrupt Enable - * 0b0..No interrupt - * 0b1..Interrupt - */ -#define SCT_CONEN_NCEN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN7_SHIFT)) & SCT_CONEN_NCEN7_MASK) - -#define SCT_CONEN_NCEN8_MASK (0x100U) -#define SCT_CONEN_NCEN8_SHIFT (8U) -/*! NCEN8 - No Change Conflict Event/Interrupt Enable - * 0b0..No interrupt - * 0b1..Interrupt - */ -#define SCT_CONEN_NCEN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN8_SHIFT)) & SCT_CONEN_NCEN8_MASK) - -#define SCT_CONEN_NCEN9_MASK (0x200U) -#define SCT_CONEN_NCEN9_SHIFT (9U) -/*! NCEN9 - No Change Conflict Event/Interrupt Enable - * 0b0..No interrupt - * 0b1..Interrupt - */ -#define SCT_CONEN_NCEN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN9_SHIFT)) & SCT_CONEN_NCEN9_MASK) -/*! @} */ - -/*! @name CONFLAG - Conflict Flag */ -/*! @{ */ - -#define SCT_CONFLAG_NCFLAG0_MASK (0x1U) -#define SCT_CONFLAG_NCFLAG0_SHIFT (0U) -/*! NCFLAG0 - No Change Conflict Event Flag - * 0b0..No Conflict Event - * 0b1..A No Change Conflict Event occured - */ -#define SCT_CONFLAG_NCFLAG0(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG0_SHIFT)) & SCT_CONFLAG_NCFLAG0_MASK) - -#define SCT_CONFLAG_NCFLAG1_MASK (0x2U) -#define SCT_CONFLAG_NCFLAG1_SHIFT (1U) -/*! NCFLAG1 - No Change Conflict Event Flag - * 0b0..No Conflict Event - * 0b1..A No Change Conflict Event occured - */ -#define SCT_CONFLAG_NCFLAG1(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG1_SHIFT)) & SCT_CONFLAG_NCFLAG1_MASK) - -#define SCT_CONFLAG_NCFLAG2_MASK (0x4U) -#define SCT_CONFLAG_NCFLAG2_SHIFT (2U) -/*! NCFLAG2 - No Change Conflict Event Flag - * 0b0..No Conflict Event - * 0b1..A No Change Conflict Event occured - */ -#define SCT_CONFLAG_NCFLAG2(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG2_SHIFT)) & SCT_CONFLAG_NCFLAG2_MASK) - -#define SCT_CONFLAG_NCFLAG3_MASK (0x8U) -#define SCT_CONFLAG_NCFLAG3_SHIFT (3U) -/*! NCFLAG3 - No Change Conflict Event Flag - * 0b0..No Conflict Event - * 0b1..A No Change Conflict Event occured - */ -#define SCT_CONFLAG_NCFLAG3(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG3_SHIFT)) & SCT_CONFLAG_NCFLAG3_MASK) - -#define SCT_CONFLAG_NCFLAG4_MASK (0x10U) -#define SCT_CONFLAG_NCFLAG4_SHIFT (4U) -/*! NCFLAG4 - No Change Conflict Event Flag - * 0b0..No Conflict Event - * 0b1..A No Change Conflict Event occured - */ -#define SCT_CONFLAG_NCFLAG4(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG4_SHIFT)) & SCT_CONFLAG_NCFLAG4_MASK) - -#define SCT_CONFLAG_NCFLAG5_MASK (0x20U) -#define SCT_CONFLAG_NCFLAG5_SHIFT (5U) -/*! NCFLAG5 - No Change Conflict Event Flag - * 0b0..No Conflict Event - * 0b1..A No Change Conflict Event occured - */ -#define SCT_CONFLAG_NCFLAG5(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG5_SHIFT)) & SCT_CONFLAG_NCFLAG5_MASK) - -#define SCT_CONFLAG_NCFLAG6_MASK (0x40U) -#define SCT_CONFLAG_NCFLAG6_SHIFT (6U) -/*! NCFLAG6 - No Change Conflict Event Flag - * 0b0..No Conflict Event - * 0b1..A No Change Conflict Event occured - */ -#define SCT_CONFLAG_NCFLAG6(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG6_SHIFT)) & SCT_CONFLAG_NCFLAG6_MASK) - -#define SCT_CONFLAG_NCFLAG7_MASK (0x80U) -#define SCT_CONFLAG_NCFLAG7_SHIFT (7U) -/*! NCFLAG7 - No Change Conflict Event Flag - * 0b0..No Conflict Event - * 0b1..A No Change Conflict Event occured - */ -#define SCT_CONFLAG_NCFLAG7(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG7_SHIFT)) & SCT_CONFLAG_NCFLAG7_MASK) - -#define SCT_CONFLAG_NCFLAG8_MASK (0x100U) -#define SCT_CONFLAG_NCFLAG8_SHIFT (8U) -/*! NCFLAG8 - No Change Conflict Event Flag - * 0b0..No Conflict Event - * 0b1..A No Change Conflict Event occured - */ -#define SCT_CONFLAG_NCFLAG8(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG8_SHIFT)) & SCT_CONFLAG_NCFLAG8_MASK) - -#define SCT_CONFLAG_NCFLAG9_MASK (0x200U) -#define SCT_CONFLAG_NCFLAG9_SHIFT (9U) -/*! NCFLAG9 - No Change Conflict Event Flag - * 0b0..No Conflict Event - * 0b1..A No Change Conflict Event occured - */ -#define SCT_CONFLAG_NCFLAG9(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG9_SHIFT)) & SCT_CONFLAG_NCFLAG9_MASK) - -#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) -#define SCT_CONFLAG_BUSERRL_SHIFT (30U) -/*! BUSERRL - Bus Error Low/Unified - */ -#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) - -#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) -#define SCT_CONFLAG_BUSERRH_SHIFT (31U) -/*! BUSERRH - Bus Error High - */ -#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) -/*! @} */ - -/*! @name CAPL - SCT_CAPL register */ -/*! @{ */ - -#define SCT_CAPL_CAPL_MASK (0xFFFFU) -#define SCT_CAPL_CAPL_SHIFT (0U) -#define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK) -/*! @} */ - -/* The count of SCT_CAPL */ -#define SCT_CAPL_COUNT (16U) - -/*! @name CAPH - SCT_CAPH register */ -/*! @{ */ - -#define SCT_CAPH_CAPH_MASK (0xFFFFU) -#define SCT_CAPH_CAPH_SHIFT (0U) -#define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK) -/*! @} */ - -/* The count of SCT_CAPH */ -#define SCT_CAPH_COUNT (16U) - -/*! @name CAP - Capture Value */ -/*! @{ */ - -#define SCT_CAP_CAPn_L_MASK (0xFFFFU) -#define SCT_CAP_CAPn_L_SHIFT (0U) -/*! CAPn_L - Capture n Low - */ -#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK) - -#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U) -#define SCT_CAP_CAPn_H_SHIFT (16U) -/*! CAPn_H - Capture n High - */ -#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK) -/*! @} */ - -/* The count of SCT_CAP */ -#define SCT_CAP_COUNT (16U) - -/*! @name MATCHL - SCT_MATCHL register */ -/*! @{ */ - -#define SCT_MATCHL_MATCHL_MASK (0xFFFFU) -#define SCT_MATCHL_MATCHL_SHIFT (0U) -#define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK) -/*! @} */ - -/* The count of SCT_MATCHL */ -#define SCT_MATCHL_COUNT (16U) - -/*! @name MATCHH - SCT_MATCHH register */ -/*! @{ */ - -#define SCT_MATCHH_MATCHH_MASK (0xFFFFU) -#define SCT_MATCHH_MATCHH_SHIFT (0U) -#define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK) -/*! @} */ - -/* The count of SCT_MATCHH */ -#define SCT_MATCHH_COUNT (16U) - -/*! @name MATCH - Match Value */ -/*! @{ */ - -#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU) -#define SCT_MATCH_MATCHn_L_SHIFT (0U) -/*! MATCHn_L - Match n Low - */ -#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK) - -#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U) -#define SCT_MATCH_MATCHn_H_SHIFT (16U) -/*! MATCHn_H - Match n High - */ -#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK) -/*! @} */ - -/* The count of SCT_MATCH */ -#define SCT_MATCH_COUNT (16U) - -/*! @name FRACMAT - Fractional Match */ -/*! @{ */ - -#define SCT_FRACMAT_FRACMAT_L_MASK (0xFU) -#define SCT_FRACMAT_FRACMAT_L_SHIFT (0U) -/*! FRACMAT_L - Fractional Match Low - */ -#define SCT_FRACMAT_FRACMAT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_FRACMAT_FRACMAT_L_SHIFT)) & SCT_FRACMAT_FRACMAT_L_MASK) - -#define SCT_FRACMAT_FRACMAT_H_MASK (0xF0000U) -#define SCT_FRACMAT_FRACMAT_H_SHIFT (16U) -/*! FRACMAT_H - Fractional Match High - */ -#define SCT_FRACMAT_FRACMAT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_FRACMAT_FRACMAT_H_SHIFT)) & SCT_FRACMAT_FRACMAT_H_MASK) -/*! @} */ - -/* The count of SCT_FRACMAT */ -#define SCT_FRACMAT_COUNT (6U) - -/*! @name CAPCTRLL - SCT_CAPCTRLL register */ -/*! @{ */ - -#define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU) -#define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U) -#define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK) -/*! @} */ - -/* The count of SCT_CAPCTRLL */ -#define SCT_CAPCTRLL_COUNT (16U) - -/*! @name CAPCTRLH - SCT_CAPCTRLH register */ -/*! @{ */ - -#define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU) -#define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U) -#define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK) -/*! @} */ - -/* The count of SCT_CAPCTRLH */ -#define SCT_CAPCTRLH_COUNT (16U) - -/*! @name SCTCAPCTRL_CAPCTRL - Capture Control */ -/*! @{ */ - -#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_MASK (0xFFFFU) -#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_SHIFT (0U) -/*! CAPCONn_L - Capture Control n Low - */ -#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_MASK) - -#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) -#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_SHIFT (16U) -/*! CAPCONn_H - Capture Control n High - */ -#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_MASK) -/*! @} */ - -/* The count of SCT_SCTCAPCTRL_CAPCTRL */ -#define SCT_SCTCAPCTRL_CAPCTRL_COUNT (16U) - -/*! @name MATCHRELL - SCT_MATCHRELL register */ -/*! @{ */ - -#define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU) -#define SCT_MATCHRELL_MATCHRELL_SHIFT (0U) -#define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK) -/*! @} */ - -/* The count of SCT_MATCHRELL */ -#define SCT_MATCHRELL_COUNT (16U) - -/*! @name MATCHRELH - SCT_MATCHRELH register */ -/*! @{ */ - -#define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU) -#define SCT_MATCHRELH_MATCHRELH_SHIFT (0U) -#define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK) -/*! @} */ - -/* The count of SCT_MATCHRELH */ -#define SCT_MATCHRELH_COUNT (16U) - -/*! @name MATCHREL - Match Reload Value */ -/*! @{ */ - -#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU) -#define SCT_MATCHREL_RELOADn_L_SHIFT (0U) -/*! RELOADn_L - Reload n Low - */ -#define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK) - -#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U) -#define SCT_MATCHREL_RELOADn_H_SHIFT (16U) -/*! RELOADn_H - Reload n High - */ -#define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK) -/*! @} */ - -/* The count of SCT_MATCHREL */ -#define SCT_MATCHREL_COUNT (16U) - -/*! @name FRACMATREL - Fractional Match Reload */ -/*! @{ */ - -#define SCT_FRACMATREL_FRACMAT_L_MASK (0xFU) -#define SCT_FRACMATREL_FRACMAT_L_SHIFT (0U) -/*! FRACMAT_L - Reload Fractional Match Low - */ -#define SCT_FRACMATREL_FRACMAT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_FRACMATREL_FRACMAT_L_SHIFT)) & SCT_FRACMATREL_FRACMAT_L_MASK) - -#define SCT_FRACMATREL_RELFRAC_H_MASK (0xF0000U) -#define SCT_FRACMATREL_RELFRAC_H_SHIFT (16U) -/*! RELFRAC_H - Reload Fractional Match High - */ -#define SCT_FRACMATREL_RELFRAC_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_FRACMATREL_RELFRAC_H_SHIFT)) & SCT_FRACMATREL_RELFRAC_H_MASK) -/*! @} */ - -/* The count of SCT_FRACMATREL */ -#define SCT_FRACMATREL_COUNT (6U) - -/*! @name EV_STATE - Event n State */ -/*! @{ */ - -#define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFFFFFU) -#define SCT_EV_STATE_STATEMSKn_SHIFT (0U) -/*! STATEMSKn - Event State Mask n - */ -#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK) -/*! @} */ - -/* The count of SCT_EV_STATE */ -#define SCT_EV_STATE_COUNT (16U) - -/*! @name EV_CTRL - Event n Control */ -/*! @{ */ - -#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU) -#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U) -/*! MATCHSEL - Match Select - */ -#define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK) - -#define SCT_EV_CTRL_HEVENT_MASK (0x10U) -#define SCT_EV_CTRL_HEVENT_SHIFT (4U) -/*! HEVENT - High Event - * 0b0..Low Counter - * 0b1..High Counter - */ -#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK) - -#define SCT_EV_CTRL_OUTSEL_MASK (0x20U) -#define SCT_EV_CTRL_OUTSEL_SHIFT (5U) -/*! OUTSEL - Input/Output Select - * 0b0..Selects the inputs selected by IOSEL. - * 0b1..Selects the outputs selected by IOSEL. - */ -#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK) - -#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U) -#define SCT_EV_CTRL_IOSEL_SHIFT (6U) -/*! IOSEL - Input/Output Signal Select - */ -#define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK) - -#define SCT_EV_CTRL_IOCOND_MASK (0xC00U) -#define SCT_EV_CTRL_IOCOND_SHIFT (10U) -/*! IOCOND - Input/Output Condition - * 0b00..Low - * 0b01..Rise - * 0b10..Fall - * 0b11..High - */ -#define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK) - -#define SCT_EV_CTRL_COMBMODE_MASK (0x3000U) -#define SCT_EV_CTRL_COMBMODE_SHIFT (12U) -/*! COMBMODE - Combination Mode - * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. - * 0b01..MATCH. Uses the specified match only. - * 0b10..IO. Uses the specified I/O condition only. - * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. - */ -#define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK) - -#define SCT_EV_CTRL_STATELD_MASK (0x4000U) -#define SCT_EV_CTRL_STATELD_SHIFT (14U) -/*! STATELD - State Load - * 0b0..Add. STATEV value is added into STATE (the carry-out is ignored). - * 0b1..Load. STATEV value is loaded into STATE. - */ -#define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK) - -#define SCT_EV_CTRL_STATEV_MASK (0xF8000U) -#define SCT_EV_CTRL_STATEV_SHIFT (15U) -/*! STATEV - State Value - */ -#define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK) - -#define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U) -#define SCT_EV_CTRL_MATCHMEM_SHIFT (20U) -/*! MATCHMEM - Match Mem - */ -#define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK) - -#define SCT_EV_CTRL_DIRECTION_MASK (0x600000U) -#define SCT_EV_CTRL_DIRECTION_SHIFT (21U) -/*! DIRECTION - Direction - * 0b00..Direction independent. This event is triggered regardless of the count direction. - * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. - * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. - * 0b11..Reserved - */ -#define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK) -/*! @} */ - -/* The count of SCT_EV_CTRL */ -#define SCT_EV_CTRL_COUNT (16U) - -/*! @name OUT_SET - Output n Set */ -/*! @{ */ - -#define SCT_OUT_SET_SET_MASK (0xFFFFU) -#define SCT_OUT_SET_SET_SHIFT (0U) -/*! SET - Set - */ -#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) -/*! @} */ - -/* The count of SCT_OUT_SET */ -#define SCT_OUT_SET_COUNT (10U) - -/*! @name OUT_CLR - Output n Clear */ -/*! @{ */ - -#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) -#define SCT_OUT_CLR_CLR_SHIFT (0U) -/*! CLR - Clear - */ -#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) -/*! @} */ - -/* The count of SCT_OUT_CLR */ -#define SCT_OUT_CLR_COUNT (10U) - - -/*! - * @} - */ /* end of group SCT_Register_Masks */ - - -/* SCT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SCT0 base address */ - #define SCT0_BASE (0x50085000u) - /** Peripheral SCT0 base address */ - #define SCT0_BASE_NS (0x40085000u) - /** Peripheral SCT0 base pointer */ - #define SCT0 ((SCT_Type *)SCT0_BASE) - /** Peripheral SCT0 base pointer */ - #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS { SCT0_BASE } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS { SCT0 } - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS_NS { SCT0_NS } -#else - /** Peripheral SCT0 base address */ - #define SCT0_BASE (0x40085000u) - /** Peripheral SCT0 base pointer */ - #define SCT0 ((SCT_Type *)SCT0_BASE) - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS { SCT0_BASE } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS { SCT0 } -#endif -/** Interrupt vectors for the SCT peripheral type */ -#define SCT_IRQS { SCT0_IRQn } - -/*! - * @} - */ /* end of group SCT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SECTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SECTRL_Peripheral_Access_Layer SECTRL Peripheral Access Layer - * @{ - */ - -/** SECTRL - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[16]; - __IO uint32_t FLASH_MEM_RULE; /**< Flash Memory Rule, offset: 0x10 */ - uint8_t RESERVED_1[12]; - __IO uint32_t ROM_MEM_RULE[4]; /**< ROM Memory Rule, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_2[16]; - __IO uint32_t RAMX_MEM_RULE0; /**< RAMX Memory Rule 0, offset: 0x40 */ - uint8_t RESERVED_3[28]; - __IO uint32_t FLEXSPI0_REGION0_MEM_RULE[4]; /**< FLEXSPI0 Region 0 Memory Rule, array offset: 0x60, array step: 0x4 */ - struct { /* offset: 0x70, array step: 0x10 */ - __IO uint32_t FLEXSPI0_REGION_MEM_RULE0; /**< FLEXSPI0 Region 1 Memory Rule 0..FLEXSPI0 Region 4 Memory Rule 0, array offset: 0x70, array step: 0x10 */ - uint8_t RESERVED_0[12]; - } FLEXSPI0_REGION1_4_MEM_RULE[4]; - uint8_t RESERVED_4[16]; - __IO uint32_t RAM00_MEM_RULE0; /**< SRAM0 Partition 0 Memory Rule, offset: 0xC0 */ - uint8_t RESERVED_5[28]; - __IO uint32_t RAM10_MEM_RULE0; /**< SRAM1 Partition 0 Memory Rule, offset: 0xE0 */ - uint8_t RESERVED_6[28]; - __IO uint32_t RAM20_MEM_RULE0; /**< SRAM2 Partition 0 Memory Rule, offset: 0x100 */ - uint8_t RESERVED_7[28]; - __IO uint32_t RAM30_MEM_RULE0; /**< SRAM Partition 0 Memory Rule, offset: 0x120 */ - uint8_t RESERVED_8[28]; - __IO uint32_t RAM40_MEM_RULE0; /**< SRAM4 Partition 0 Memory Rule, offset: 0x140 */ - uint8_t RESERVED_9[28]; - __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE0; /**< APB Bridge Group 0 Memory Rule 0, offset: 0x160 */ - __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE1; /**< APB Bridge Group 0 Memory Rule 1, offset: 0x164 */ - __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE2; /**< APB Bridge Group 0 Rule 2, offset: 0x168 */ - __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE3; /**< APB Bridge Group 0 Memory Rule 3, offset: 0x16C */ - __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE0; /**< APB Bridge Group 1 Memory Rule 0, offset: 0x170 */ - __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE1; /**< APB Bridge Group 1 Memory Rule 1, offset: 0x174 */ - __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE2; /**< APB Bridge Group 1 Memory Rule 2, offset: 0x178 */ - __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE3; /**< APB Bridge Group 1 Memory Rule 3, offset: 0x17C */ - uint8_t RESERVED_10[16]; - __IO uint32_t AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0; /**< AHB Peripheral 0 Slave Port9 Rule 0, offset: 0x190 */ - __IO uint32_t AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1; /**< AHB Peripheral 0 Slave Port 9 Rule 1, offset: 0x194 */ - uint8_t RESERVED_11[8]; - __IO uint32_t AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0; /**< AHB Peripheral 1 Slave Port 10 Slave Rule 0, offset: 0x1A0 */ - uint8_t RESERVED_12[12]; - __IO uint32_t AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0; /**< AHB Peripheral 2 Slave Port 11 Slave Rule 0, offset: 0x1B0 */ - uint8_t RESERVED_13[12]; - __IO uint32_t AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0; /**< AHB Secure Control Peripheral Memory Rule 0, offset: 0x1C0 */ - uint8_t RESERVED_14[28]; - __IO uint32_t AIPS_BRIDGE_GROUP0_RULE0; /**< AIPS Bridge Group 0 Rule 0, offset: 0x1E0 */ - __IO uint32_t AIPS_BRIDGE_GROUP0_RULE1; /**< AIPS Bridge Group 0 Rule 1, offset: 0x1E4 */ - uint8_t RESERVED_15[24]; - __IO uint32_t AIPS_BRIDGE_GROUP1_RULE0; /**< AIPS Bridge Group 1 Rule 0, offset: 0x200 */ - __IO uint32_t AIPS_BRIDGE_GROUP1_RULE1; /**< AIPS Bridge Group 1 Rule 1, offset: 0x204 */ - uint8_t RESERVED_16[3064]; - __I uint32_t SEC_VIO_ADDR[32]; /**< Security Violation Address, array offset: 0xE00, array step: 0x4 */ - __I uint32_t SEC_VIO_MISC_INFO[32]; /**< Security Violation Miscellaneous Information at Address, array offset: 0xE80, array step: 0x4 */ - __IO uint32_t SEC_VIO_INFO_VALID; /**< Security Violation Info Validity for Address, offset: 0xF00 */ - uint8_t RESERVED_17[124]; - __IO uint32_t SEC_GPIO_MASK[3]; /**< GPIO Mask for Port 0..GPIO Mask for Port 2, array offset: 0xF80, array step: 0x4 */ - __IO uint32_t SEC_GPIO_MASK3; /**< GPIO Mask for Port 3, offset: 0xF8C */ - uint8_t RESERVED_18[44]; - __IO uint32_t SEC_GP_REG_LOCK; /**< Secure Mask Lock, offset: 0xFBC */ - uint8_t RESERVED_19[16]; - __IO uint32_t MASTER_SEC_LEVEL; /**< Master Secure Level, offset: 0xFD0 */ - __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< Master Secure Level, offset: 0xFD4 */ - uint8_t RESERVED_20[20]; - __IO uint32_t CM33_LOCK_REG[3]; /**< Miscellaneous CPU0 Control Signals, array offset: 0xFEC, array step: 0x4 */ - __IO uint32_t MISC_CTRL_DP_REG; /**< Secure Control Duplicate, offset: 0xFF8 */ - __IO uint32_t MISC_CTRL_REG; /**< Secure Control, offset: 0xFFC */ -} SECTRL_Type; - -/* ---------------------------------------------------------------------------- - -- SECTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SECTRL_Register_Masks SECTRL Register Masks - * @{ - */ - -/*! @name FLASH_MEM_RULE - Flash Memory Rule */ -/*! @{ */ - -#define SECTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) -#define SECTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - Rule 0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE0_MASK) - -#define SECTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) -#define SECTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - Rule 1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE1_MASK) - -#define SECTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) -#define SECTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - Rule 2 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE2_MASK) - -#define SECTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) -#define SECTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - Rule 3 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE3_MASK) - -#define SECTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) -#define SECTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - Rule 4 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE4_MASK) - -#define SECTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) -#define SECTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - Rule 5 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE5_MASK) - -#define SECTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) -#define SECTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - Rule 6 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE6_MASK) - -#define SECTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) -#define SECTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - Rule 7 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE7_MASK) -/*! @} */ - -/*! @name ROM_MEM_RULE - ROM Memory Rule */ -/*! @{ */ - -#define SECTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) -#define SECTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - Rule 0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE0_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE0_MASK) - -#define SECTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) -#define SECTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - Rule 1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE1_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE1_MASK) - -#define SECTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) -#define SECTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - Rule 2 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE2_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE2_MASK) - -#define SECTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) -#define SECTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - Rule 3 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE3_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE3_MASK) - -#define SECTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) -#define SECTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - Rule 4 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE4_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE4_MASK) - -#define SECTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) -#define SECTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - Rule 5 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE5_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE5_MASK) - -#define SECTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) -#define SECTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - Rule 6 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE6_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE6_MASK) - -#define SECTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) -#define SECTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - Rule 7 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE7_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of SECTRL_ROM_MEM_RULE */ -#define SECTRL_ROM_MEM_RULE_COUNT (4U) - -/*! @name RAMX_MEM_RULE0 - RAMX Memory Rule 0 */ -/*! @{ */ - -#define SECTRL_RAMX_MEM_RULE0_RULE0_MASK (0x3U) -#define SECTRL_RAMX_MEM_RULE0_RULE0_SHIFT (0U) -/*! RULE0 - Rule 0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAMX_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAMX_MEM_RULE0_RULE0_SHIFT)) & SECTRL_RAMX_MEM_RULE0_RULE0_MASK) - -#define SECTRL_RAMX_MEM_RULE0_RULE1_MASK (0x30U) -#define SECTRL_RAMX_MEM_RULE0_RULE1_SHIFT (4U) -/*! RULE1 - Rule 1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAMX_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAMX_MEM_RULE0_RULE1_SHIFT)) & SECTRL_RAMX_MEM_RULE0_RULE1_MASK) - -#define SECTRL_RAMX_MEM_RULE0_RULE2_MASK (0x300U) -#define SECTRL_RAMX_MEM_RULE0_RULE2_SHIFT (8U) -/*! RULE2 - Rule 2 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAMX_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAMX_MEM_RULE0_RULE2_SHIFT)) & SECTRL_RAMX_MEM_RULE0_RULE2_MASK) - -#define SECTRL_RAMX_MEM_RULE0_RULE3_MASK (0x3000U) -#define SECTRL_RAMX_MEM_RULE0_RULE3_SHIFT (12U) -/*! RULE3 - Rule 3 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAMX_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAMX_MEM_RULE0_RULE3_SHIFT)) & SECTRL_RAMX_MEM_RULE0_RULE3_MASK) -/*! @} */ - -/*! @name FLEXSPI0_REGION0_MEM_RULE - FLEXSPI0 Region 0 Memory Rule */ -/*! @{ */ - -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE0_MASK (0x3U) -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - Rule 0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE0_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE0_MASK) - -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE1_MASK (0x30U) -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - Rule 1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE1_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE1_MASK) - -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE2_MASK (0x300U) -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - Rule 2 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE2_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE2_MASK) - -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE3_MASK (0x3000U) -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - Rule 3 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE3_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE3_MASK) - -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE4_MASK (0x30000U) -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - Rule 4 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE4_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE4_MASK) - -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE5_MASK (0x300000U) -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - Rule 5 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE5_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE5_MASK) - -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE6_MASK (0x3000000U) -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - Rule 6 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE6_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE6_MASK) - -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE7_MASK (0x30000000U) -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - Rule 7 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE7_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of SECTRL_FLEXSPI0_REGION0_MEM_RULE */ -#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_COUNT (4U) - -/*! @name FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0 - FLEXSPI0 Region 1 Memory Rule 0..FLEXSPI0 Region 4 Memory Rule 0 */ -/*! @{ */ - -#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_MASK (0x3U) -#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_SHIFT (0U) -/*! RULE0 - Rule 0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_SHIFT)) & SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_MASK) - -#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_MASK (0x30U) -#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_SHIFT (4U) -/*! RULE1 - Rule 1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_SHIFT)) & SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_MASK) - -#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_MASK (0x300U) -#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_SHIFT (8U) -/*! RULE2 - Rule 2 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_SHIFT)) & SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_MASK) - -#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_MASK (0x3000U) -#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_SHIFT (12U) -/*! RULE3 - Rule 3 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_SHIFT)) & SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_MASK) -/*! @} */ - -/* The count of SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0 */ -#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_COUNT (4U) - -/*! @name RAM00_MEM_RULE0 - SRAM0 Partition 0 Memory Rule */ -/*! @{ */ - -#define SECTRL_RAM00_MEM_RULE0_RULE0_MASK (0x3U) -#define SECTRL_RAM00_MEM_RULE0_RULE0_SHIFT (0U) -/*! RULE0 - Rule 0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAM00_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM00_MEM_RULE0_RULE0_SHIFT)) & SECTRL_RAM00_MEM_RULE0_RULE0_MASK) - -#define SECTRL_RAM00_MEM_RULE0_RULE1_MASK (0x30U) -#define SECTRL_RAM00_MEM_RULE0_RULE1_SHIFT (4U) -/*! RULE1 - Rule 1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAM00_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM00_MEM_RULE0_RULE1_SHIFT)) & SECTRL_RAM00_MEM_RULE0_RULE1_MASK) - -#define SECTRL_RAM00_MEM_RULE0_RULE2_MASK (0x300U) -#define SECTRL_RAM00_MEM_RULE0_RULE2_SHIFT (8U) -/*! RULE2 - Rule 2 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAM00_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM00_MEM_RULE0_RULE2_SHIFT)) & SECTRL_RAM00_MEM_RULE0_RULE2_MASK) - -#define SECTRL_RAM00_MEM_RULE0_RULE3_MASK (0x3000U) -#define SECTRL_RAM00_MEM_RULE0_RULE3_SHIFT (12U) -/*! RULE3 - Rule 3 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAM00_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM00_MEM_RULE0_RULE3_SHIFT)) & SECTRL_RAM00_MEM_RULE0_RULE3_MASK) -/*! @} */ - -/*! @name RAM10_MEM_RULE0 - SRAM1 Partition 0 Memory Rule */ -/*! @{ */ - -#define SECTRL_RAM10_MEM_RULE0_RULE0_MASK (0x3U) -#define SECTRL_RAM10_MEM_RULE0_RULE0_SHIFT (0U) -/*! RULE0 - Rule 0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAM10_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM10_MEM_RULE0_RULE0_SHIFT)) & SECTRL_RAM10_MEM_RULE0_RULE0_MASK) - -#define SECTRL_RAM10_MEM_RULE0_RULE1_MASK (0x30U) -#define SECTRL_RAM10_MEM_RULE0_RULE1_SHIFT (4U) -/*! RULE1 - Rule 1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAM10_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM10_MEM_RULE0_RULE1_SHIFT)) & SECTRL_RAM10_MEM_RULE0_RULE1_MASK) - -#define SECTRL_RAM10_MEM_RULE0_RULE2_MASK (0x300U) -#define SECTRL_RAM10_MEM_RULE0_RULE2_SHIFT (8U) -/*! RULE2 - Rule 2 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAM10_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM10_MEM_RULE0_RULE2_SHIFT)) & SECTRL_RAM10_MEM_RULE0_RULE2_MASK) - -#define SECTRL_RAM10_MEM_RULE0_RULE3_MASK (0x3000U) -#define SECTRL_RAM10_MEM_RULE0_RULE3_SHIFT (12U) -/*! RULE3 - Rule 3 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAM10_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM10_MEM_RULE0_RULE3_SHIFT)) & SECTRL_RAM10_MEM_RULE0_RULE3_MASK) -/*! @} */ - -/*! @name RAM20_MEM_RULE0 - SRAM2 Partition 0 Memory Rule */ -/*! @{ */ - -#define SECTRL_RAM20_MEM_RULE0_RULE0_MASK (0x3U) -#define SECTRL_RAM20_MEM_RULE0_RULE0_SHIFT (0U) -/*! RULE0 - Rule 0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAM20_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM20_MEM_RULE0_RULE0_SHIFT)) & SECTRL_RAM20_MEM_RULE0_RULE0_MASK) - -#define SECTRL_RAM20_MEM_RULE0_RULE1_MASK (0x30U) -#define SECTRL_RAM20_MEM_RULE0_RULE1_SHIFT (4U) -/*! RULE1 - Rule 1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAM20_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM20_MEM_RULE0_RULE1_SHIFT)) & SECTRL_RAM20_MEM_RULE0_RULE1_MASK) - -#define SECTRL_RAM20_MEM_RULE0_RULE2_MASK (0x300U) -#define SECTRL_RAM20_MEM_RULE0_RULE2_SHIFT (8U) -/*! RULE2 - Rule 2 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAM20_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM20_MEM_RULE0_RULE2_SHIFT)) & SECTRL_RAM20_MEM_RULE0_RULE2_MASK) - -#define SECTRL_RAM20_MEM_RULE0_RULE3_MASK (0x3000U) -#define SECTRL_RAM20_MEM_RULE0_RULE3_SHIFT (12U) -/*! RULE3 - Rule 3 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAM20_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM20_MEM_RULE0_RULE3_SHIFT)) & SECTRL_RAM20_MEM_RULE0_RULE3_MASK) -/*! @} */ - -/*! @name RAM30_MEM_RULE0 - SRAM Partition 0 Memory Rule */ -/*! @{ */ - -#define SECTRL_RAM30_MEM_RULE0_RULE0_MASK (0x3U) -#define SECTRL_RAM30_MEM_RULE0_RULE0_SHIFT (0U) -/*! RULE0 - Rule 0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAM30_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM30_MEM_RULE0_RULE0_SHIFT)) & SECTRL_RAM30_MEM_RULE0_RULE0_MASK) - -#define SECTRL_RAM30_MEM_RULE0_RULE1_MASK (0x30U) -#define SECTRL_RAM30_MEM_RULE0_RULE1_SHIFT (4U) -/*! RULE1 - Rule 1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAM30_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM30_MEM_RULE0_RULE1_SHIFT)) & SECTRL_RAM30_MEM_RULE0_RULE1_MASK) - -#define SECTRL_RAM30_MEM_RULE0_RULE2_MASK (0x300U) -#define SECTRL_RAM30_MEM_RULE0_RULE2_SHIFT (8U) -/*! RULE2 - Rule 2 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAM30_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM30_MEM_RULE0_RULE2_SHIFT)) & SECTRL_RAM30_MEM_RULE0_RULE2_MASK) - -#define SECTRL_RAM30_MEM_RULE0_RULE3_MASK (0x3000U) -#define SECTRL_RAM30_MEM_RULE0_RULE3_SHIFT (12U) -/*! RULE3 - Rule 3 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAM30_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM30_MEM_RULE0_RULE3_SHIFT)) & SECTRL_RAM30_MEM_RULE0_RULE3_MASK) -/*! @} */ - -/*! @name RAM40_MEM_RULE0 - SRAM4 Partition 0 Memory Rule */ -/*! @{ */ - -#define SECTRL_RAM40_MEM_RULE0_RULE0_MASK (0x3U) -#define SECTRL_RAM40_MEM_RULE0_RULE0_SHIFT (0U) -/*! RULE0 - Rule 0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAM40_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM40_MEM_RULE0_RULE0_SHIFT)) & SECTRL_RAM40_MEM_RULE0_RULE0_MASK) - -#define SECTRL_RAM40_MEM_RULE0_RULE1_MASK (0x30U) -#define SECTRL_RAM40_MEM_RULE0_RULE1_SHIFT (4U) -/*! RULE1 - Rule 1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAM40_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM40_MEM_RULE0_RULE1_SHIFT)) & SECTRL_RAM40_MEM_RULE0_RULE1_MASK) - -#define SECTRL_RAM40_MEM_RULE0_RULE2_MASK (0x300U) -#define SECTRL_RAM40_MEM_RULE0_RULE2_SHIFT (8U) -/*! RULE2 - Rule 2 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAM40_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM40_MEM_RULE0_RULE2_SHIFT)) & SECTRL_RAM40_MEM_RULE0_RULE2_MASK) - -#define SECTRL_RAM40_MEM_RULE0_RULE3_MASK (0x3000U) -#define SECTRL_RAM40_MEM_RULE0_RULE3_SHIFT (12U) -/*! RULE3 - Rule 3 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_RAM40_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM40_MEM_RULE0_RULE3_SHIFT)) & SECTRL_RAM40_MEM_RULE0_RULE3_MASK) -/*! @} */ - -/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE0 - APB Bridge Group 0 Memory Rule 0 */ -/*! @{ */ - -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_MASK (0x3U) -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_SHIFT (0U) -/*! SYSCON - SYSCON - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_IOCON_MASK (0x30U) -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_IOCON_SHIFT (4U) -/*! IOCON - IOCON - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_IOCON_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_IOCON_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO0_MASK (0x300U) -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO0_SHIFT (8U) -/*! GPIO0 - GPIO0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO0_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO1_MASK (0x3000U) -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO1_SHIFT (12U) -/*! GPIO1 - GPIO1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO1_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO1_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_MASK (0x30000U) -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_SHIFT (16U) -/*! PINT0 - PINT0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT1_MASK (0x300000U) -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT1_SHIFT (20U) -/*! PINT1 - Rule 5 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT1_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT1_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GINT1_MASK (0x3000000U) -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GINT1_SHIFT (24U) -/*! GINT1 - GINT1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GINT1_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GINT1_MASK) -/*! @} */ - -/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE1 - APB Bridge Group 0 Memory Rule 1 */ -/*! @{ */ - -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_MASK (0x3U) -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_SHIFT (0U) -/*! CTIMER0 - CTIMER0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_MASK (0x30U) -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_SHIFT (4U) -/*! CTIMER1 - CTIMER 1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_WWDT0_MASK (0x30000U) -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_WWDT0_SHIFT (16U) -/*! WWDT0 - WWDT0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_WWDT0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_WWDT0_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MRT_MASK (0x300000U) -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MRT_SHIFT (20U) -/*! MRT - MRT0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MRT_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MRT_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MICRO_TICK_MASK (0x3000000U) -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MICRO_TICK_SHIFT (24U) -/*! MICRO_TICK - MICRO_TICK - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MICRO_TICK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MICRO_TICK_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MICRO_TICK_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_ITRC_MASK (0x30000000U) -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_ITRC_SHIFT (28U) -/*! ITRC - ITRC - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_ITRC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_ITRC_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_ITRC_MASK) -/*! @} */ - -/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE2 - APB Bridge Group 0 Rule 2 */ -/*! @{ */ - -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_ANALOG_CTRL_MASK (0x3000U) -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_ANALOG_CTRL_SHIFT (12U) -/*! ANALOG_CTRL - Rule 0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_ANALOG_CTRL_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_ANALOG_CTRL_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_eFUSE_MASK (0x300000U) -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_eFUSE_SHIFT (20U) -/*! eFUSE - Rule 1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_eFUSE(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_eFUSE_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_eFUSE_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_I3C0_MASK (0x3000000U) -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_I3C0_SHIFT (24U) -/*! I3C0 - I3C0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_I3C0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_I3C0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_I3C0_MASK) -/*! @} */ - -/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE3 - APB Bridge Group 0 Memory Rule 3 */ -/*! @{ */ - -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE3_EZH_MASK (0x300000U) -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE3_EZH_SHIFT (20U) -/*! EZH - EZH - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE3_EZH(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE3_EZH_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE3_EZH_MASK) -/*! @} */ - -/*! @name APB_PERIPHERAL_GROUP1_MEM_RULE0 - APB Bridge Group 1 Memory Rule 0 */ -/*! @{ */ - -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_PMC_MASK (0x3U) -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_PMC_SHIFT (0U) -/*! PMC - PMC - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_PMC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_PMC_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_PMC_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SYSCTL_I2S_MASK (0x3000U) -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SYSCTL_I2S_SHIFT (12U) -/*! SYSCTL_I2S - SYSCTL(I2S Pin Sharing) - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SYSCTL_I2S(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SYSCTL_I2S_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SYSCTL_I2S_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SPI_MSFT_MASK (0x30000U) -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SPI_MSFT_SHIFT (16U) -/*! SPI_MSFT - Rule 3 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SPI_MSFT(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SPI_MSFT_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SPI_MSFT_MASK) -/*! @} */ - -/*! @name APB_PERIPHERAL_GROUP1_MEM_RULE1 - APB Bridge Group 1 Memory Rule 1 */ -/*! @{ */ - -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER2_MASK (0x3U) -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER2_SHIFT (0U) -/*! CTIMER2 - CTIMER2 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER2_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER2_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER3_MASK (0x30U) -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER3_SHIFT (4U) -/*! CTIMER3 - CTIMER3 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER3_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER3_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER4_MASK (0x300U) -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER4_SHIFT (8U) -/*! CTIMER4 - CTIMER4 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER4_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER4_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_RTC_MASK (0x30000U) -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_RTC_SHIFT (16U) -/*! RTC - RTC - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_RTC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_RTC_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_RTC_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_OS_EVENT_TIMER_MASK (0x300000U) -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_OS_EVENT_TIMER_SHIFT (20U) -/*! OS_EVENT_TIMER - OS_EVENT_TIMER - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_OS_EVENT_TIMER(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_OS_EVENT_TIMER_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_OS_EVENT_TIMER_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CACHE64_POLSEL_MASK (0x3000000U) -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CACHE64_POLSEL_SHIFT (24U) -/*! CACHE64_POLSEL - CACHE64_POLSEL - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CACHE64_POLSEL(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CACHE64_POLSEL_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CACHE64_POLSEL_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_MASK (0x30000000U) -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_SHIFT (28U) -/*! PKC - PKC - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_MASK) -/*! @} */ - -/*! @name APB_PERIPHERAL_GROUP1_MEM_RULE2 - APB Bridge Group 1 Memory Rule 2 */ -/*! @{ */ - -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS0_MASK (0x3U) -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS0_SHIFT (0U) -/*! CSSV2MINI_ALIAS0 - CSSV2MINI ALIAS0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS0_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS1_MASK (0x30U) -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS1_SHIFT (4U) -/*! CSSV2MINI_ALIAS1 - CSSV2MINI ALIAS1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS1_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS1_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS2_MASK (0x300U) -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS2_SHIFT (8U) -/*! CSSV2MINI_ALIAS2 - CSSV2MINI ALIAS2 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS2_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS2_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS3_MASK (0x3000U) -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS3_SHIFT (12U) -/*! CSSV2MINI_ALIAS3 - CSSV2MINI ALIAS3 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS3_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS3_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_FLASH_CONTROLLER_MASK (0x30000U) -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_FLASH_CONTROLLER_SHIFT (16U) -/*! FLASH_CONTROLLER - Flash controller - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_FLASH_CONTROLLER(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_FLASH_CONTROLLER_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_FLASH_CONTROLLER_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_PRINCE0_MASK (0x300000U) -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_PRINCE0_SHIFT (20U) -/*! PRINCE0 - PRINCE0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_PRINCE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_PRINCE0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_PRINCE0_MASK) -/*! @} */ - -/*! @name APB_PERIPHERAL_GROUP1_MEM_RULE3 - APB Bridge Group 1 Memory Rule 3 */ -/*! @{ */ - -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS0_MASK (0x300U) -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS0_SHIFT (8U) -/*! PUF_ALIAS0 - PUF_ALIAS0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS0_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS1_MASK (0x3000U) -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS1_SHIFT (12U) -/*! PUF_ALIAS1 - PUF_ALIAS0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS1_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS1_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS2_MASK (0x30000U) -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS2_SHIFT (16U) -/*! PUF_ALIAS2 - PUF_ALIAS2 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS2_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS2_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS3_MASK (0x300000U) -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS3_SHIFT (20U) -/*! PUF_ALIAS3 - PUF_ALIAS3 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS3_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS3_MASK) - -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_ROM_MASK (0x3000000U) -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_ROM_SHIFT (24U) -/*! ROM - ROM - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_ROM(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_ROM_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_ROM_MASK) -/*! @} */ - -/*! @name AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0 - AHB Peripheral 0 Slave Port9 Rule 0 */ -/*! @{ */ - -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_DMA0_MASK (0x3U) -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_DMA0_SHIFT (0U) -/*! DMA0 - DMA0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_DMA0_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_DMA0_MASK) - -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_USB_FSD_MASK (0x30U) -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_USB_FSD_SHIFT (4U) -/*! USB_FSD - USB FSD - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_USB_FSD(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_USB_FSD_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_USB_FSD_MASK) - -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_SCTIMER_MASK (0x300U) -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_SCTIMER_SHIFT (8U) -/*! SCTIMER - SCTIMER - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_SCTIMER(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_SCTIMER_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_SCTIMER_MASK) - -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM0_MASK (0x3000U) -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM0_SHIFT (12U) -/*! FLEXCOMM0 - FLEXCOMM 0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM0_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM0_MASK) - -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM1_MASK (0x30000U) -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM1_SHIFT (16U) -/*! FLEXCOMM1 - FLEXCOMM 1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM1_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM1_MASK) - -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM2_MASK (0x300000U) -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM2_SHIFT (20U) -/*! FLEXCOMM2 - FLEXCOMM 2 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM2_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM2_MASK) - -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM3_MASK (0x3000000U) -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM3_SHIFT (24U) -/*! FLEXCOMM3 - FLEXCOMM 3 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM3_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM3_MASK) - -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM4_MASK (0x30000000U) -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM4_SHIFT (28U) -/*! FLEXCOMM4 - FLEXCOMM4 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM4_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM4_MASK) -/*! @} */ - -/*! @name AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1 - AHB Peripheral 0 Slave Port 9 Rule 1 */ -/*! @{ */ - -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_MAILBOX_MASK (0x3U) -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_MAILBOX_SHIFT (0U) -/*! MAILBOX - MAILBOX - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_MAILBOX_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_MAILBOX_MASK) - -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_GPIO_MASK (0x30U) -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_GPIO_SHIFT (4U) -/*! GPIO - GPIO - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_GPIO(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_GPIO_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_GPIO_MASK) -/*! @} */ - -/*! @name AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0 - AHB Peripheral 1 Slave Port 10 Slave Rule 0 */ -/*! @{ */ - -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DMIC0_MASK (0x3U) -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DMIC0_SHIFT (0U) -/*! DMIC0 - DMIC0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DMIC0_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DMIC0_MASK) - -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_CRC_MASK (0x30U) -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_CRC_SHIFT (4U) -/*! CRC - CRC - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_CRC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_CRC_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_CRC_MASK) - -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM5_MASK (0x300U) -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM5_SHIFT (8U) -/*! FLEXCOMM5 - FLEXCOMM 5 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM5_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM5_MASK) - -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM6_MASK (0x3000U) -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM6_SHIFT (12U) -/*! FLEXCOMM6 - FLEXCOMM 6 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM6_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM6_MASK) - -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM7_MASK (0x30000U) -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM7_SHIFT (16U) -/*! FLEXCOMM7 - FLEXCOMM 7 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM7_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM7_MASK) - -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DEBUG_MAILBOX_MASK (0x300000U) -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DEBUG_MAILBOX_SHIFT (20U) -/*! DEBUG_MAILBOX - FLEXCOMM 7 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DEBUG_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DEBUG_MAILBOX_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DEBUG_MAILBOX_MASK) - -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_MCAN_MASK (0x3000000U) -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_MCAN_SHIFT (24U) -/*! MCAN - FLEXCOMM 14 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_MCAN(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_MCAN_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_MCAN_MASK) - -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_HS_LSPI_MASK (0x30000000U) -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_HS_LSPI_SHIFT (28U) -/*! HS_LSPI - FLEXCOMM 15 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_HS_LSPI_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_HS_LSPI_MASK) -/*! @} */ - -/*! @name AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0 - AHB Peripheral 2 Slave Port 11 Slave Rule 0 */ -/*! @{ */ - -#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_ADC_MASK (0x3U) -#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_ADC_SHIFT (0U) -/*! ADC - ADC - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_ADC_SHIFT)) & SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_ADC_MASK) - -#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_CDOG_MASK (0x30U) -#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_CDOG_SHIFT (4U) -/*! CDOG - Code Watch Dog timer - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_CDOG(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_CDOG_SHIFT)) & SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_CDOG_MASK) - -#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_USB_FS_HOST_MASK (0x300U) -#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_USB_FS_HOST_SHIFT (8U) -/*! USB_FS_HOST - USB FS HOST - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_USB_FS_HOST(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_USB_FS_HOST_SHIFT)) & SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_USB_FS_HOST_MASK) - -#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_POWERQUAD_MASK (0x3000U) -#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_POWERQUAD_SHIFT (12U) -/*! POWERQUAD - POWERQUAD - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_POWERQUAD(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_POWERQUAD_SHIFT)) & SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_POWERQUAD_MASK) - -#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_DMA1_MASK (0x30000U) -#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_DMA1_SHIFT (16U) -/*! DMA1 - DMA1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_DMA1_SHIFT)) & SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_DMA1_MASK) - -#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_SECGPIO_MASK (0x300000U) -#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_SECGPIO_SHIFT (20U) -/*! SECGPIO - SECGPIO - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_SECGPIO(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_SECGPIO_SHIFT)) & SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_SECGPIO_MASK) - -#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_AHB_SECURE_MASK (0x3000000U) -#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_AHB_SECURE_SHIFT (24U) -/*! AHB_SECURE - AHB_SECURE - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_AHB_SECURE(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_AHB_SECURE_SHIFT)) & SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_AHB_SECURE_MASK) -/*! @} */ - -/*! @name AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0 - AHB Secure Control Peripheral Memory Rule 0 */ -/*! @{ */ - -#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE0_MASK (0x3U) -#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE0_SHIFT (0U) -/*! RULE0 - Rule 0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE0_SHIFT)) & SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE0_MASK) - -#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE1_MASK (0x30U) -#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE1_SHIFT (4U) -/*! RULE1 - Rule 1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE1_SHIFT)) & SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE1_MASK) - -#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE2_MASK (0x300U) -#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE2_SHIFT (8U) -/*! RULE2 - Rule 2 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE2_SHIFT)) & SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE2_MASK) - -#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE3_MASK (0x3000U) -#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE3_SHIFT (12U) -/*! RULE3 - Rule 3 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE3_SHIFT)) & SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE3_MASK) -/*! @} */ - -/*! @name AIPS_BRIDGE_GROUP0_RULE0 - AIPS Bridge Group 0 Rule 0 */ -/*! @{ */ - -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_ADC1_MASK (0x30U) -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_ADC1_SHIFT (4U) -/*! ADC1 - ADC1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE0_ADC1_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE0_ADC1_MASK) - -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC0_MASK (0x300U) -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC0_SHIFT (8U) -/*! DAC0 - DAC0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC0_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC0_MASK) - -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP0_MASK (0x3000U) -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP0_SHIFT (12U) -/*! HSCOMP0 - HSCOMP0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP0_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP0_MASK) - -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_OPAMP0_MASK (0x30000U) -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_OPAMP0_SHIFT (16U) -/*! OPAMP0 - OPAMP0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE0_OPAMP0_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE0_OPAMP0_MASK) - -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_VREF_MASK (0x300000U) -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_VREF_SHIFT (20U) -/*! VREF - VREF - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_VREF(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE0_VREF_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE0_VREF_MASK) - -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC1_MASK (0x3000000U) -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC1_SHIFT (24U) -/*! DAC1 - DAC1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC1_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC1_MASK) - -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP1_MASK (0x30000000U) -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP1_SHIFT (28U) -/*! HSCOMP1 - HSCOMP1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP1_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP1_MASK) -/*! @} */ - -/*! @name AIPS_BRIDGE_GROUP0_RULE1 - AIPS Bridge Group 0 Rule 1 */ -/*! @{ */ - -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP1_MASK (0x3U) -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP1_SHIFT (0U) -/*! OPAMP1 - OPAMP1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP1_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP1_MASK) - -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_DAC2_MASK (0x30U) -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_DAC2_SHIFT (4U) -/*! DAC2 - DAC2 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_DAC2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE1_DAC2_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE1_DAC2_MASK) - -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_HSCOMP2_MASK (0x300U) -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_HSCOMP2_SHIFT (8U) -/*! HSCOMP2 - HSCOMP2 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_HSCOMP2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE1_HSCOMP2_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE1_HSCOMP2_MASK) - -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP2_MASK (0x3000U) -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP2_SHIFT (12U) -/*! OPAMP2 - OPAMP2 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP2_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP2_MASK) -/*! @} */ - -/*! @name AIPS_BRIDGE_GROUP1_RULE0 - AIPS Bridge Group 1 Rule 0 */ -/*! @{ */ - -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI0_MASK (0x3U) -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI0_SHIFT (0U) -/*! FLEXSPI0 - FLEXSPI0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI0_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI0_MASK) - -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_CMX_MASK (0x30U) -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_CMX_SHIFT (4U) -/*! FLEXSPI_CMX - FLEXSPI_CMX - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_CMX(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_CMX_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_CMX_MASK) - -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_LPCAC_MASK (0x300U) -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_LPCAC_SHIFT (8U) -/*! LPCAC - LPCAC - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_LPCAC_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_LPCAC_MASK) - -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXPWM0_MASK (0x3000U) -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXPWM0_SHIFT (12U) -/*! FLEXPWM0 - FLEXPWM0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXPWM0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXPWM0_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXPWM0_MASK) - -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC0_MASK (0x30000U) -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC0_SHIFT (16U) -/*! ENC0 - FLEXSPI0 Registers - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC0_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC0_MASK) - -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_PWM1_MASK (0x300000U) -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_PWM1_SHIFT (20U) -/*! FLEXSPI_PWM1 - FLEXSPI_PWM1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_PWM1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_PWM1_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_PWM1_MASK) - -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC1_MASK (0x3000000U) -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC1_SHIFT (24U) -/*! ENC1 - ENC1 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC1_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC1_MASK) - -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_AOI0_MASK (0x30000000U) -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_AOI0_SHIFT (28U) -/*! AOI0 - AOI0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_AOI0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_AOI0_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_AOI0_MASK) -/*! @} */ - -/*! @name AIPS_BRIDGE_GROUP1_RULE1 - AIPS Bridge Group 1 Rule 1 */ -/*! @{ */ - -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE1_AOI1_MASK (0x3U) -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE1_AOI1_SHIFT (0U) -/*! AOI1 - RNG (Random Number Generator) - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define SECTRL_AIPS_BRIDGE_GROUP1_RULE1_AOI1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE1_AOI1_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE1_AOI1_MASK) -/*! @} */ - -/*! @name SEC_VIO_ADDRN_SEC_VIO_ADDR - Security Violation Address */ -/*! @{ */ - -#define SECTRL_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_INFO_WRITE_MASK (0xFFFFFFFFU) -#define SECTRL_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_INFO_WRITE_SHIFT (0U) -/*! SEC_VIO_INFO_WRITE - Security violation access read/write indicator - */ -#define SECTRL_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_INFO_WRITE_SHIFT)) & SECTRL_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_INFO_WRITE_MASK) -/*! @} */ - -/* The count of SECTRL_SEC_VIO_ADDRN_SEC_VIO_ADDR */ -#define SECTRL_SEC_VIO_ADDRN_SEC_VIO_ADDR_COUNT (32U) - -/*! @name SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO - Security Violation Miscellaneous Information at Address */ -/*! @{ */ - -#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) -#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) -/*! SEC_VIO_INFO_WRITE - Security violation access read/write indicator - * 0b0..Read access - * 0b1..Write access - */ -#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) - -#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) -#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) -/*! SEC_VIO_INFO_DATA_ACCESS - Security Violation Info Data Access - * 0b0..Code - * 0b1..Data - */ -#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) - -#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) -#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) -/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - Security Violation Info Master Security Level - */ -#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) - -#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U) -#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) -/*! SEC_VIO_INFO_MASTER - Security violation master number - * 0b0000..M33 Code - * 0b0001..M33 System - * 0b0010..DMA0 - * 0b0011..DMA1 - * 0b0100..USBFS Device - * 0b0101..USBFS Host - * 0b0110..EZH Instruction - * 0b0111..EZH Data - * 0b1000..CSSV2 - * 0b1001..MCAN - * 0b1010..PKC M0 - * 0b1011..GPU - * 0b1100..DSP Data - * 0b1101..DSP Instruction - * 0b1110..Reserved - * 0b1111..Reserved - */ -#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) -/*! @} */ - -/* The count of SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO */ -#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_COUNT (32U) - -/*! @name SEC_VIO_INFO_VALID - Security Violation Info Validity for Address */ -/*! @{ */ - -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) -/*! VIO_INFO_VALID0 - Violation information valid flag for AHB port 0 - * 0b0..Not valid - * 0b1..Valid - */ -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) - -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) -/*! VIO_INFO_VALID1 - Violation information valid flag for AHB port 1 - * 0b0..Not valid - * 0b1..Valid - */ -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) - -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) -/*! VIO_INFO_VALID2 - Violation information valid flag for AHB port 2 - * 0b0..Not valid - * 0b1..Valid - */ -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) - -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) -/*! VIO_INFO_VALID3 - Violation information valid flag for AHB port 3 - * 0b0..Not valid - * 0b1..Valid - */ -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) - -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) -/*! VIO_INFO_VALID4 - Violation information valid flag for AHB port 4 - * 0b0..Not valid - * 0b1..Valid - */ -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) - -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) -/*! VIO_INFO_VALID5 - Violation information valid flag for AHB port 5 - * 0b0..Not valid - * 0b1..Valid - */ -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) - -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) -/*! VIO_INFO_VALID6 - Violation information valid flag for AHB port 6 - * 0b0..Not valid - * 0b1..Valid - */ -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) - -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) -/*! VIO_INFO_VALID7 - Violation information valid flag for AHB port 7 - * 0b0..Not valid - * 0b1..Valid - */ -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) - -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) -/*! VIO_INFO_VALID8 - Violation information valid flag for AHB port 8 - * 0b0..Not valid - * 0b1..Valid - */ -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) - -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) -/*! VIO_INFO_VALID9 - Violation information valid flag for AHB port 9 - * 0b0..Not valid - * 0b1..Valid - */ -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) - -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U) -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U) -/*! VIO_INFO_VALID10 - Violation information valid flag for AHB port 10 - * 0b0..Not valid - * 0b1..Valid - */ -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK) - -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U) -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U) -/*! VIO_INFO_VALID11 - Violation information valid flag for AHB port 11 - * 0b0..Not valid - * 0b1..Valid - */ -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK) - -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK (0x1000U) -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT (12U) -/*! VIO_INFO_VALID12 - Violation information valid flag for AHB port 12 - * 0b0..Not valid - * 0b1..Valid - */ -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK) - -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK (0x2000U) -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT (13U) -/*! VIO_INFO_VALID13 - Violation information valid flag for AHB port 13 - * 0b0..Not valid - * 0b1..Valid - */ -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK) - -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK (0x4000U) -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT (14U) -/*! VIO_INFO_VALID14 - Violation information valid flag for AHB port 14 - * 0b0..Not valid - * 0b1..Valid - */ -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK) - -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK (0x8000U) -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT (15U) -/*! VIO_INFO_VALID15 - Violation information valid flag for AHB port 15 - * 0b0..Not valid - * 0b1..Valid - */ -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK) - -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK (0x10000U) -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT (16U) -/*! VIO_INFO_VALID16 - Violation information valid flag for AHB port 16 - * 0b0..Not valid - * 0b1..Valid - */ -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK) - -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK (0x20000U) -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT (17U) -/*! VIO_INFO_VALID17 - Violation information valid flag for AHB port 17 - * 0b0..Not valid - * 0b1..Valid - */ -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK) - -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK (0x40000U) -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT (18U) -/*! VIO_INFO_VALID18 - Violation information valid flag for AHB port 18 - * 0b0..Not valid - * 0b1..Valid - */ -#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK) -/*! @} */ - -/*! @name SEC_GPIO_MASKN_SEC_GPIO_MASK - GPIO Mask for Port 0..GPIO Mask for Port 2 */ -/*! @{ */ - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_MASK (0x1U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_SHIFT (0U) -/*! PIO0_PIN0_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_MASK (0x1U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_SHIFT (0U) -/*! PIO1_PIN0_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN0_SEC_MASK_MASK (0x1U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN0_SEC_MASK_SHIFT (0U) -/*! PIO2_PIN0_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN0_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN0_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_MASK (0x2U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_SHIFT (1U) -/*! PIO0_PIN1_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_MASK (0x2U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_SHIFT (1U) -/*! PIO1_PIN1_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN1_SEC_MASK_MASK (0x2U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN1_SEC_MASK_SHIFT (1U) -/*! PIO2_PIN1_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN1_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN1_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_MASK (0x4U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_SHIFT (2U) -/*! PIO0_PIN2_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_MASK (0x4U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_SHIFT (2U) -/*! PIO1_PIN2_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN2_SEC_MASK_MASK (0x4U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN2_SEC_MASK_SHIFT (2U) -/*! PIO2_PIN2_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN2_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN2_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_MASK (0x8U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_SHIFT (3U) -/*! PIO0_PIN3_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_MASK (0x8U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_SHIFT (3U) -/*! PIO1_PIN3_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN3_SEC_MASK_MASK (0x8U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN3_SEC_MASK_SHIFT (3U) -/*! PIO2_PIN3_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN3_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN3_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_MASK (0x10U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_SHIFT (4U) -/*! PIO0_PIN4_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_MASK (0x10U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_SHIFT (4U) -/*! PIO1_PIN4_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN4_SEC_MASK_MASK (0x10U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN4_SEC_MASK_SHIFT (4U) -/*! PIO2_PIN4_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN4_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN4_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_MASK (0x20U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_SHIFT (5U) -/*! PIO0_PIN5_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_MASK (0x20U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_SHIFT (5U) -/*! PIO1_PIN5_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN5_SEC_MASK_MASK (0x20U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN5_SEC_MASK_SHIFT (5U) -/*! PIO2_PIN5_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN5_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN5_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_MASK (0x40U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_SHIFT (6U) -/*! PIO0_PIN6_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_MASK (0x40U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_SHIFT (6U) -/*! PIO1_PIN6_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN6_SEC_MASK_MASK (0x40U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN6_SEC_MASK_SHIFT (6U) -/*! PIO2_PIN6_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN6_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN6_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_MASK (0x80U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_SHIFT (7U) -/*! PIO0_PIN7_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_MASK (0x80U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_SHIFT (7U) -/*! PIO1_PIN7_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN7_SEC_MASK_MASK (0x80U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN7_SEC_MASK_SHIFT (7U) -/*! PIO2_PIN7_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN7_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN7_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_MASK (0x100U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_SHIFT (8U) -/*! PIO0_PIN8_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_MASK (0x100U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_SHIFT (8U) -/*! PIO1_PIN8_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN8_SEC_MASK_MASK (0x100U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN8_SEC_MASK_SHIFT (8U) -/*! PIO2_PIN8_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN8_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN8_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_MASK (0x200U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_SHIFT (9U) -/*! PIO0_PIN9_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_MASK (0x200U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_SHIFT (9U) -/*! PIO1_PIN9_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN9_SEC_MASK_MASK (0x200U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN9_SEC_MASK_SHIFT (9U) -/*! PIO2_PIN9_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN9_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN9_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_MASK (0x400U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_SHIFT (10U) -/*! PIO0_PIN10_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_MASK (0x400U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_SHIFT (10U) -/*! PIO1_PIN10_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN10_SEC_MASK_MASK (0x400U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN10_SEC_MASK_SHIFT (10U) -/*! PIO2_PIN10_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN10_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN10_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_MASK (0x800U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_SHIFT (11U) -/*! PIO0_PIN11_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_MASK (0x800U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_SHIFT (11U) -/*! PIO1_PIN11_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN11_SEC_MASK_MASK (0x800U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN11_SEC_MASK_SHIFT (11U) -/*! PIO2_PIN11_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN11_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN11_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_MASK (0x1000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_SHIFT (12U) -/*! PIO0_PIN12_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_MASK (0x1000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_SHIFT (12U) -/*! PIO1_PIN12_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN12_SEC_MASK_MASK (0x1000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN12_SEC_MASK_SHIFT (12U) -/*! PIO2_PIN12_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN12_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN12_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_MASK (0x2000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_SHIFT (13U) -/*! PIO0_PIN13_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_MASK (0x2000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_SHIFT (13U) -/*! PIO1_PIN13_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN13_SEC_MASK_MASK (0x2000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN13_SEC_MASK_SHIFT (13U) -/*! PIO2_PIN13_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN13_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN13_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_MASK (0x4000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_SHIFT (14U) -/*! PIO0_PIN14_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_MASK (0x4000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_SHIFT (14U) -/*! PIO1_PIN14_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN14_SEC_MASK_MASK (0x4000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN14_SEC_MASK_SHIFT (14U) -/*! PIO2_PIN14_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN14_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN14_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_MASK (0x8000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_SHIFT (15U) -/*! PIO0_PIN15_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_MASK (0x8000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_SHIFT (15U) -/*! PIO1_PIN15_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN15_SEC_MASK_MASK (0x8000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN15_SEC_MASK_SHIFT (15U) -/*! PIO2_PIN15_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN15_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN15_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_MASK (0x10000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_SHIFT (16U) -/*! PIO0_PIN16_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_MASK (0x10000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_SHIFT (16U) -/*! PIO1_PIN16_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN16_SEC_MASK_MASK (0x10000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN16_SEC_MASK_SHIFT (16U) -/*! PIO2_PIN16_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN16_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN16_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_MASK (0x20000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_SHIFT (17U) -/*! PIO0_PIN17_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_MASK (0x20000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_SHIFT (17U) -/*! PIO1_PIN17_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN17_SEC_MASK_MASK (0x20000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN17_SEC_MASK_SHIFT (17U) -/*! PIO2_PIN17_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN17_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN17_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_MASK (0x40000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_SHIFT (18U) -/*! PIO0_PIN18_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_MASK (0x40000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_SHIFT (18U) -/*! PIO1_PIN18_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN18_SEC_MASK_MASK (0x40000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN18_SEC_MASK_SHIFT (18U) -/*! PIO2_PIN18_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN18_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN18_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_MASK (0x80000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_SHIFT (19U) -/*! PIO0_PIN19_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_MASK (0x80000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_SHIFT (19U) -/*! PIO1_PIN19_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN19_SEC_MASK_MASK (0x80000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN19_SEC_MASK_SHIFT (19U) -/*! PIO2_PIN19_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN19_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN19_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_MASK (0x100000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_SHIFT (20U) -/*! PIO0_PIN20_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_MASK (0x100000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_SHIFT (20U) -/*! PIO1_PIN20_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN20_SEC_MASK_MASK (0x100000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN20_SEC_MASK_SHIFT (20U) -/*! PIO2_PIN20_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN20_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN20_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_MASK (0x200000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_SHIFT (21U) -/*! PIO0_PIN21_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_MASK (0x200000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_SHIFT (21U) -/*! PIO1_PIN21_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN21_SEC_MASK_MASK (0x200000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN21_SEC_MASK_SHIFT (21U) -/*! PIO2_PIN21_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN21_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN21_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_MASK (0x400000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_SHIFT (22U) -/*! PIO0_PIN22_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_MASK (0x400000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_SHIFT (22U) -/*! PIO1_PIN22_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN22_SEC_MASK_MASK (0x400000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN22_SEC_MASK_SHIFT (22U) -/*! PIO2_PIN22_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN22_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN22_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_MASK (0x800000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_SHIFT (23U) -/*! PIO0_PIN23_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_MASK (0x800000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_SHIFT (23U) -/*! PIO1_PIN23_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN23_SEC_MASK_MASK (0x800000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN23_SEC_MASK_SHIFT (23U) -/*! PIO2_PIN23_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN23_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN23_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_SHIFT (24U) -/*! PIO0_PIN24_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_SHIFT (24U) -/*! PIO1_PIN24_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN24_SEC_MASK_MASK (0x1000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN24_SEC_MASK_SHIFT (24U) -/*! PIO2_PIN24_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN24_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN24_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_SHIFT (25U) -/*! PIO0_PIN25_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_SHIFT (25U) -/*! PIO1_PIN25_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN25_SEC_MASK_MASK (0x2000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN25_SEC_MASK_SHIFT (25U) -/*! PIO2_PIN25_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN25_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN25_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_SHIFT (26U) -/*! PIO0_PIN26_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_SHIFT (26U) -/*! PIO1_PIN26_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN26_SEC_MASK_MASK (0x4000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN26_SEC_MASK_SHIFT (26U) -/*! PIO2_PIN26_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN26_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN26_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_SHIFT (27U) -/*! PIO0_PIN27_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_SHIFT (27U) -/*! PIO1_PIN27_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN27_SEC_MASK_MASK (0x8000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN27_SEC_MASK_SHIFT (27U) -/*! PIO2_PIN27_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN27_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN27_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_SHIFT (28U) -/*! PIO0_PIN28_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_SHIFT (28U) -/*! PIO1_PIN28_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN28_SEC_MASK_MASK (0x10000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN28_SEC_MASK_SHIFT (28U) -/*! PIO2_PIN28_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN28_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN28_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_SHIFT (29U) -/*! PIO0_PIN29_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_SHIFT (29U) -/*! PIO1_PIN29_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN29_SEC_MASK_MASK (0x20000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN29_SEC_MASK_SHIFT (29U) -/*! PIO2_PIN29_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN29_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN29_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_SHIFT (30U) -/*! PIO0_PIN30_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_SHIFT (30U) -/*! PIO1_PIN30_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN30_SEC_MASK_MASK (0x40000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN30_SEC_MASK_SHIFT (30U) -/*! PIO2_PIN30_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN30_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN30_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_SHIFT (31U) -/*! PIO0_PIN31_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_SHIFT (31U) -/*! PIO1_PIN31_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN31_SEC_MASK_MASK (0x80000000U) -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN31_SEC_MASK_SHIFT (31U) -/*! PIO2_PIN31_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN31_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN31_SEC_MASK_MASK) -/*! @} */ - -/* The count of SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK */ -#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_COUNT (3U) - -/*! @name SEC_GPIO_MASK3 - GPIO Mask for Port 3 */ -/*! @{ */ - -#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_MASK (0x1U) -#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_SHIFT (0U) -/*! PIO3_PIN0_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_MASK (0x2U) -#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_SHIFT (1U) -/*! PIO3_PIN1_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_MASK (0x4U) -#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_SHIFT (2U) -/*! PIO3_PIN2_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_MASK (0x8U) -#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_SHIFT (3U) -/*! PIO3_PIN3_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_MASK (0x10U) -#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_SHIFT (4U) -/*! PIO3_PIN4_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_MASK (0x20U) -#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_SHIFT (5U) -/*! PIO3_PIN5_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_MASK) - -#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN6_SEC_MASK_MASK (0x40U) -#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN6_SEC_MASK_SHIFT (6U) -/*! PIO3_PIN6_SEC_MASK - Mask bit - * 0b0..Masked - * 0b1..Not masked - */ -#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASK3_PIO3_PIN6_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASK3_PIO3_PIN6_SEC_MASK_MASK) -/*! @} */ - -/*! @name SEC_GP_REG_LOCK - Secure Mask Lock */ -/*! @{ */ - -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) -/*! SEC_GPIO_MASK0_LOCK - Secure GPIO _MASK0 Lock - * 0b00..Reserved - * 0b01..SEC_GPIO_MASK0 cannot be written - * 0b10..SEC_GPIO_MASK0 can be written - * 0b11..Reserved - */ -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK_MASK) - -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) -/*! SEC_GPIO_MASK1_LOCK - Secure GPIO _MASK1 Lock - * 0b00..Reserved - * 0b01..SEC_GPIO_MASK1 cannot be written - * 0b10..SEC_GPIO_MASK1 can be written - * 0b11..Reserved - */ -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK_MASK) - -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK2_LOCK_MASK (0x30U) -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK2_LOCK_SHIFT (4U) -/*! SEC_GPIO_MASK2_LOCK - Secure GPIO _MASK2 Lock - * 0b00..Reserved - * 0b01..SEC_GPIO_MASK2 cannot be written - * 0b10..SEC_GPIO_MASK2 can be written - * 0b11..Reserved - */ -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK2_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK2_LOCK_MASK) - -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK3_LOCK_MASK (0xC0U) -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK3_LOCK_SHIFT (6U) -/*! SEC_GPIO_MASK3_LOCK - Secure GPIO _MASK3 Lock - * 0b00..Reserved - * 0b01..SEC_GPIO_MASK3 cannot be written - * 0b10..SEC_GPIO_MASK3 can be written - * 0b11..Reserved - */ -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK3_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK3_LOCK_MASK) - -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK4_LOCK_MASK (0x300U) -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK4_LOCK_SHIFT (8U) -/*! SEC_GPIO_MASK4_LOCK - SEC_GPIO_MASK4 Lock - * 0b00..Reserved - * 0b01..SEC_GPIO_MASK4_LOCK cannot be written - * 0b10..SEC_GPIO_MASK4_LOCK can be written - * 0b11..Reserved - */ -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK4_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK4_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK4_LOCK_MASK) - -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK5_LOCK_MASK (0xC00U) -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK5_LOCK_SHIFT (10U) -/*! SEC_GPIO_MASK5_LOCK - SEC_GPIO_MASK5 Lock - * 0b00..Reserved - * 0b01..SEC_GPIO_MASK5 cannot be written - * 0b10..SEC_GPIO_MASK5 can be written - * 0b11..Reserved - */ -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK5_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK5_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK5_LOCK_MASK) - -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK6_LOCK_MASK (0x3000U) -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK6_LOCK_SHIFT (12U) -/*! SEC_GPIO_MASK6_LOCK - SEC_GPIO_MASK6 Lock - * 0b00..Reserved - * 0b01..SEC_GPIO_MASK6 cannot be written - * 0b10..SEC_GPIO_MASK6 can be written - * 0b11..Reserved - */ -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK6_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK6_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK6_LOCK_MASK) - -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK7_LOCK_MASK (0xC000U) -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK7_LOCK_SHIFT (14U) -/*! SEC_GPIO_MASK7_LOCK - SEC_GPIO_MASK7 Lock - * 0b00..Reserved - * 0b01..SEC_GPIO_MASK7 cannot be written - * 0b10..SEC_GPIO_MASK7 can be written - * 0b11..Reserved - */ -#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK7_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK7_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK7_LOCK_MASK) - -#define SECTRL_SEC_GP_REG_LOCK_SEC_DSP_INT_MASK_LOCK_MASK (0x30000U) -#define SECTRL_SEC_GP_REG_LOCK_SEC_DSP_INT_MASK_LOCK_SHIFT (16U) -/*! SEC_DSP_INT_MASK_LOCK - SEC_DSP_INT_MASK Lock - * 0b00..Reserved - * 0b01..SEC_DSP_INT_MASK cannot be written - * 0b10..SEC_DSP_INT_MASK can be written - * 0b11..Reserved - */ -#define SECTRL_SEC_GP_REG_LOCK_SEC_DSP_INT_MASK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_DSP_INT_MASK_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_DSP_INT_MASK_LOCK_MASK) -/*! @} */ - -/*! @name MASTER_SEC_LEVEL - Master Secure Level */ -/*! @{ */ - -#define SECTRL_MASTER_SEC_LEVEL_DMA0_MASK (0x30U) -#define SECTRL_MASTER_SEC_LEVEL_DMA0_SHIFT (4U) -/*! DMA0 - DMA0 - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_LEVEL_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_DMA0_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_DMA0_MASK) - -#define SECTRL_MASTER_SEC_LEVEL_DMA1_MASK (0xC0U) -#define SECTRL_MASTER_SEC_LEVEL_DMA1_SHIFT (6U) -/*! DMA1 - DMA1 - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_LEVEL_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_DMA1_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_DMA1_MASK) - -#define SECTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U) -#define SECTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U) -/*! USBFSD - USBFS Device - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_USBFSD_MASK) - -#define SECTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00U) -#define SECTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (10U) -/*! USBFSH - USBFS Host - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_USBFSH_MASK) - -#define SECTRL_MASTER_SEC_LEVEL_EZH_D_MASK (0x3000U) -#define SECTRL_MASTER_SEC_LEVEL_EZH_D_SHIFT (12U) -/*! EZH_D - EZH Data - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_LEVEL_EZH_D(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_EZH_D_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_EZH_D_MASK) - -#define SECTRL_MASTER_SEC_LEVEL_EZH_I_MASK (0xC000U) -#define SECTRL_MASTER_SEC_LEVEL_EZH_I_SHIFT (14U) -/*! EZH_I - EZH Instruction - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_LEVEL_EZH_I(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_EZH_I_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_EZH_I_MASK) - -#define SECTRL_MASTER_SEC_LEVEL_MCAN_MASK (0xC0000U) -#define SECTRL_MASTER_SEC_LEVEL_MCAN_SHIFT (18U) -/*! MCAN - MCAN - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_LEVEL_MCAN(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_MCAN_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_MCAN_MASK) - -#define SECTRL_MASTER_SEC_LEVEL_POWERQUAD_MASK (0x300000U) -#define SECTRL_MASTER_SEC_LEVEL_POWERQUAD_SHIFT (20U) -/*! POWERQUAD - POWERQUAD - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_LEVEL_POWERQUAD(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_POWERQUAD_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_POWERQUAD_MASK) - -#define SECTRL_MASTER_SEC_LEVEL_PKC_MASK (0xC00000U) -#define SECTRL_MASTER_SEC_LEVEL_PKC_SHIFT (22U) -/*! PKC - PKC - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_LEVEL_PKC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_PKC_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_PKC_MASK) - -#define SECTRL_MASTER_SEC_LEVEL_DSP_D_MASK (0x3000000U) -#define SECTRL_MASTER_SEC_LEVEL_DSP_D_SHIFT (24U) -/*! DSP_D - DSP Data - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_LEVEL_DSP_D(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_DSP_D_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_DSP_D_MASK) - -#define SECTRL_MASTER_SEC_LEVEL_DSP_I_MASK (0xC000000U) -#define SECTRL_MASTER_SEC_LEVEL_DSP_I_SHIFT (26U) -/*! DSP_I - DSP Instruction - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_LEVEL_DSP_I(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_DSP_I_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_DSP_I_MASK) - -#define SECTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) -#define SECTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) -/*! MASTER_SEC_LEVEL_LOCK - Master Security Level Lock - * 0b00..Reserved - * 0b01..Lock writing to this register, including these (MASTER_SEC_LEVEL_LOCK) bits - * 0b10..This register can be written - * 0b11..Reserved - */ -#define SECTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) -/*! @} */ - -/*! @name MASTER_SEC_ANTI_POL_REG - Master Secure Level */ -/*! @{ */ - -#define SECTRL_MASTER_SEC_ANTI_POL_REG_DMA0_MASK (0x30U) -#define SECTRL_MASTER_SEC_ANTI_POL_REG_DMA0_SHIFT (4U) -/*! DMA0 - DMA0 - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_ANTI_POL_REG_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_DMA0_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_DMA0_MASK) - -#define SECTRL_MASTER_SEC_ANTI_POL_REG_DMA1_MASK (0xC0U) -#define SECTRL_MASTER_SEC_ANTI_POL_REG_DMA1_SHIFT (6U) -/*! DMA1 - DMA1 - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_ANTI_POL_REG_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_DMA1_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_DMA1_MASK) - -#define SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U) -#define SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U) -/*! USBFSD - USBFS Device - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK) - -#define SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00U) -#define SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (10U) -/*! USBFSH - USBFS Host - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK) - -#define SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_MASK (0x3000U) -#define SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_SHIFT (12U) -/*! EZH_D - EZH Data - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_D(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_MASK) - -#define SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_MASK (0xC000U) -#define SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_SHIFT (14U) -/*! EZH_I - EZH Instruction - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_I(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_MASK) - -#define SECTRL_MASTER_SEC_ANTI_POL_REG_MCAN_MASK (0xC0000U) -#define SECTRL_MASTER_SEC_ANTI_POL_REG_MCAN_SHIFT (18U) -/*! MCAN - MCAN - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_ANTI_POL_REG_MCAN(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_MCAN_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_MCAN_MASK) - -#define SECTRL_MASTER_SEC_ANTI_POL_REG_POWERQUAD_MASK (0x300000U) -#define SECTRL_MASTER_SEC_ANTI_POL_REG_POWERQUAD_SHIFT (20U) -/*! POWERQUAD - POWERQUAD - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_ANTI_POL_REG_POWERQUAD(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_POWERQUAD_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_POWERQUAD_MASK) - -#define SECTRL_MASTER_SEC_ANTI_POL_REG_PKC_MASK (0xC00000U) -#define SECTRL_MASTER_SEC_ANTI_POL_REG_PKC_SHIFT (22U) -/*! PKC - PKC - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_ANTI_POL_REG_PKC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_PKC_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_PKC_MASK) - -#define SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_D_MASK (0x3000000U) -#define SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_D_SHIFT (24U) -/*! DSP_D - DSP Data - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_D(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_D_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_D_MASK) - -#define SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_I_MASK (0xC000000U) -#define SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_I_SHIFT (26U) -/*! DSP_I - DSP Instruction - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_I(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_I_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_I_MASK) - -#define SECTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) -#define SECTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) -/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - Master Security Level Antipole Lock - * 0b00..Reserved - * 0b01..Lock writing to this register, including these (MASTER_SEC_LEVEL_ANTIPOL_LOCK) bits - * 0b10..This register can be written - * 0b11..Reserved - */ -#define SECTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) -/*! @} */ - -/*! @name CM33_LOCK_REGN_CM33_LOCK_REG - Miscellaneous CPU0 Control Signals */ -/*! @{ */ - -#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) -#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) -/*! LOCK_NS_VTOR - LOCK_NS_VTOR - * 0b00..Reserved - * 0b01..CM33 (CPU0) LOCKNSVTOR is 1 - * 0b10..CM33 (CPU0) LOCKNSVTOR is 0 - * 0b11..Reserved - */ -#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_VTOR_MASK) - -#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) -#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) -/*! LOCK_NS_MPU - LOCK_NS_MPU - * 0b00..Reserved - * 0b01..CM33 (CPU0) LOCK_NS_MPU is 1 - * 0b10..CM33 (CPU0) LOCK_NS_MPU is 0 - * 0b11..Reserved - */ -#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT)) & SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_MPU_MASK) - -#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) -#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) -/*! LOCK_S_VTAIRCR - LOCK_S_VTAIRCR - * 0b00..Reserved - * 0b01..CM33 (CPU0) LOCK_S_VTAIRCR is 1 - * 0b10..CM33 (CPU0) LOCK_S_VTAIRCR is 0 - * 0b11..Reserved - */ -#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK) - -#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) -#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_MPU_SHIFT (6U) -/*! LOCK_S_MPU - LOCK_S_MPU - * 0b00..Reserved - * 0b01..CM33 (CPU0) LOCK_S_MPU is 1 - * 0b10..CM33 (CPU0) LOCK_S_MPU is 0 - * 0b11..Reserved - */ -#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_MPU_SHIFT)) & SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_MPU_MASK) - -#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_SAU_MASK (0x300U) -#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_SAU_SHIFT (8U) -/*! LOCK_SAU - LOCK_SAU - * 0b00..Reserved - * 0b01..CM33 (CPU0) LOCK_SAU is 1 - * 0b10..CM33 (CPU0) LOCK_SAU is 0 - * 0b11..Reserved - */ -#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_SAU_SHIFT)) & SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_SAU_MASK) - -#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK (0xC0000000U) -#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT (30U) -/*! CM33_LOCK_REG_LOCK - CM33_LOCK_REG_LOCK - * 0b00..Reserved - * 0b01..CM33_LOCK_REG_LOCK is 1 - * 0b10..CM33_LOCK_REG_LOCK is 0 - * 0b11..Reserved - */ -#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_CM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT)) & SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK) -/*! @} */ - -/* The count of SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG */ -#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_COUNT (3U) - -/*! @name MISC_CTRL_DP_REG - Secure Control Duplicate */ -/*! @{ */ - -#define SECTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) -#define SECTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) -/*! WRITE_LOCK - Write Lock - * 0b00..Reserved - * 0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed - * 0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed - * 0b11..Reserved - */ -#define SECTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & SECTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) - -#define SECTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) -#define SECTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) -/*! ENABLE_SECURE_CHECKING - Enable Secure Checking - * 0b00..Reserved - * 0b01..Enabled (restrictive mode) - * 0b10..Disabled - * 0b11..Reserved - */ -#define SECTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & SECTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) - -#define SECTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) -#define SECTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) -/*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking - * 0b00..Reserved - * 0b01..Enabled (restrictive mode) - * 0b10..Disabled - * 0b11..Reserved - */ -#define SECTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & SECTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) - -#define SECTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) -#define SECTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) -/*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking - * 0b00..Reserved - * 0b01..Enabled (restrictive mode) - * 0b10..Disabled - * 0b11..Reserved - */ -#define SECTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & SECTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) - -#define SECTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) -#define SECTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) -/*! DISABLE_VIOLATION_ABORT - Disable Violation Abort - * 0b00..Reserved - * 0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq - * (interrupt request) will still be asserted and serviced by ISR. - * 0b10..The violation detected by the secure checker will cause an abort. - * 0b11..Reserved - */ -#define SECTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & SECTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) - -#define SECTRL_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK (0xC00U) -#define SECTRL_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT (10U) -/*! DISABLE_STRICT_MODE - Disable Strict Mode - * 0b00..AHB master in strict mode - * 0b01..AHB master in tier mode. Can read and write to memories at same or below level. - * 0b10..AHB master in strict mode - * 0b11..AHB master in strict mode - */ -#define SECTRL_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT)) & SECTRL_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK) - -#define SECTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) -#define SECTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) -/*! IDAU_ALL_NS - IDAU All Non-Secure - * 0b00..Reserved - * 0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory. - * 0b10..IDAU is enabled (restrictive mode) - * 0b11..Reserved - */ -#define SECTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & SECTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) -/*! @} */ - -/*! @name MISC_CTRL_REG - Secure Control */ -/*! @{ */ - -#define SECTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) -#define SECTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) -/*! WRITE_LOCK - Write Lock - * 0b00..Reserved - * 0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed - * 0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed - * 0b11..Reserved - */ -#define SECTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & SECTRL_MISC_CTRL_REG_WRITE_LOCK_MASK) - -#define SECTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) -#define SECTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) -/*! ENABLE_SECURE_CHECKING - Enable Secure Checking - * 0b00..Reserved - * 0b01..Enabled (restrictive mode) - * 0b10..Disabled - * 0b11..Reserved - */ -#define SECTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & SECTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) - -#define SECTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) -#define SECTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) -/*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking - * 0b00..Reserved - * 0b01..Enabled (restrictive mode) - * 0b10..Disabled - * 0b11..Reserved - */ -#define SECTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & SECTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) - -#define SECTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) -#define SECTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) -/*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking - * 0b00..Reserved - * 0b01..Enabled (restrictive mode) - * 0b10..Disabled - * 0b11..Reserved - */ -#define SECTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & SECTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) - -#define SECTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) -#define SECTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) -/*! DISABLE_VIOLATION_ABORT - Disable Violation Abort - * 0b00..Reserved - * 0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq - * (interrupt request) will still be asserted and serviced by ISR. - * 0b10..The violation detected by the secure checker will cause an abort. - * 0b11..Reserved - */ -#define SECTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & SECTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) - -#define SECTRL_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK (0xC00U) -#define SECTRL_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT (10U) -/*! DISABLE_STRICT_MODE - Disable Strict Mode - * 0b00..AHB master in strict mode - * 0b01..AHB master in tier mode. Can read and write to memories at same or below level. - * 0b10..AHB master in strict mode - * 0b11..AHB master in strict mode - */ -#define SECTRL_MISC_CTRL_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT)) & SECTRL_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK) - -#define SECTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) -#define SECTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) -/*! IDAU_ALL_NS - IDAU All Non-Secure - * 0b00..Reserved - * 0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory. - * 0b10..IDAU is enabled (restrictive mode) - * 0b11..Reserved - */ -#define SECTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & SECTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SECTRL_Register_Masks */ - - -/* SECTRL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SECTRL0 base address */ - #define SECTRL0_BASE (0x500AC000u) - /** Peripheral SECTRL0 base address */ - #define SECTRL0_BASE_NS (0x400AC000u) - /** Peripheral SECTRL0 base pointer */ - #define SECTRL0 ((SECTRL_Type *)SECTRL0_BASE) - /** Peripheral SECTRL0 base pointer */ - #define SECTRL0_NS ((SECTRL_Type *)SECTRL0_BASE_NS) - /** Array initializer of SECTRL peripheral base addresses */ - #define SECTRL_BASE_ADDRS { SECTRL0_BASE } - /** Array initializer of SECTRL peripheral base pointers */ - #define SECTRL_BASE_PTRS { SECTRL0 } - /** Array initializer of SECTRL peripheral base addresses */ - #define SECTRL_BASE_ADDRS_NS { SECTRL0_BASE_NS } - /** Array initializer of SECTRL peripheral base pointers */ - #define SECTRL_BASE_PTRS_NS { SECTRL0_NS } -#else - /** Peripheral SECTRL0 base address */ - #define SECTRL0_BASE (0x400AC000u) - /** Peripheral SECTRL0 base pointer */ - #define SECTRL0 ((SECTRL_Type *)SECTRL0_BASE) - /** Array initializer of SECTRL peripheral base addresses */ - #define SECTRL_BASE_ADDRS { SECTRL0_BASE } - /** Array initializer of SECTRL peripheral base pointers */ - #define SECTRL_BASE_PTRS { SECTRL0 } -#endif - -/*! - * @} - */ /* end of group SECTRL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer - * @{ - */ - -/** SPI - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[1024]; - __IO uint32_t CFG; /**< Configuration Register, offset: 0x400 */ - __IO uint32_t DLY; /**< Delay Register, offset: 0x404 */ - __IO uint32_t STAT; /**< Status Register, offset: 0x408 */ - __IO uint32_t INTENSET; /**< Interrupt Enable Register, offset: 0x40C */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear Register, offset: 0x410 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< Clock Divider Register, offset: 0x424 */ - __I uint32_t INTSTAT; /**< Interrupt Status Register, offset: 0x428 */ - uint8_t RESERVED_2[2516]; - __IO uint32_t FIFOCFG; /**< FIFO Configuration Register, offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO Status Register, offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO Trigger Register, offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO Interrupt Enable Register, offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO Interrupt Enable Clear Register, offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO Interrupt Status Register, offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __O uint32_t FIFOWR; /**< FIFO Write Data Register, offset: 0xE20 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORD; /**< FIFO Read Data Register, offset: 0xE30 */ - uint8_t RESERVED_6[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO Data Read with no FIFO Pop Register, offset: 0xE40 */ - uint8_t RESERVED_7[4]; - __I uint32_t FIFOSIZE; /**< FIFO Size Register, offset: 0xE48 */ - __IO uint32_t FIFORXTIMEOUTCFG; /**< FIFO Receive Timeout Configuration, offset: 0xE4C */ - __I uint32_t FIFORXTIMEOUTCNT; /**< FIFO Receive Timeout Counter, offset: 0xE50 */ - uint8_t RESERVED_8[424]; - __I uint32_t ID; /**< Peripheral Identification Register, offset: 0xFFC */ -} SPI_Type; - -/* ---------------------------------------------------------------------------- - -- SPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Register_Masks SPI Register Masks - * @{ - */ - -/*! @name CFG - Configuration Register */ -/*! @{ */ - -#define SPI_CFG_ENABLE_MASK (0x1U) -#define SPI_CFG_ENABLE_SHIFT (0U) -/*! ENABLE - SPI Enable - * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. - * 0b1..Enabled. The SPI is enabled for operation. - */ -#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) - -#define SPI_CFG_MASTER_MASK (0x4U) -#define SPI_CFG_MASTER_SHIFT (2U) -/*! MASTER - Master Mode Select - * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs; MISO is an output. - * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs; MISO is an input. - */ -#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) - -#define SPI_CFG_LSBF_MASK (0x8U) -#define SPI_CFG_LSBF_SHIFT (3U) -/*! LSBF - LSB First Mode Enable - * 0b0..Standard. Data is transmitted and received in standard MSB-first order. - * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). - */ -#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) - -#define SPI_CFG_CPHA_MASK (0x10U) -#define SPI_CFG_CPHA_SHIFT (4U) -/*! CPHA - Clock Phase Select - * 0b0..Change - * 0b1..Capture - */ -#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) - -#define SPI_CFG_CPOL_MASK (0x20U) -#define SPI_CFG_CPOL_SHIFT (5U) -/*! CPOL - Clock Polarity Select - * 0b0..Low. The rest state of the clock (between transfers) is low. - * 0b1..High. The rest state of the clock (between transfers) is high. - */ -#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) - -#define SPI_CFG_LOOP_MASK (0x80U) -#define SPI_CFG_LOOP_SHIFT (7U) -/*! LOOP - Loopback Mode Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) - -#define SPI_CFG_SPOL0_MASK (0x100U) -#define SPI_CFG_SPOL0_SHIFT (8U) -/*! SPOL0 - SSEL0 Polarity Select - * 0b0..Low. The SSEL0 pin is active low. - * 0b1..High. The SSEL0 pin is active high. - */ -#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) - -#define SPI_CFG_SPOL1_MASK (0x200U) -#define SPI_CFG_SPOL1_SHIFT (9U) -/*! SPOL1 - SSEL1 Polarity Select - * 0b0..Low. The SSEL1 pin is active low. - * 0b1..High. The SSEL1 pin is active high. - */ -#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) - -#define SPI_CFG_SPOL2_MASK (0x400U) -#define SPI_CFG_SPOL2_SHIFT (10U) -/*! SPOL2 - SSEL2 Polarity Select - * 0b0..Low. The SSEL2 pin is active low. - * 0b1..High. The SSEL2 pin is active high. - */ -#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) - -#define SPI_CFG_SPOL3_MASK (0x800U) -#define SPI_CFG_SPOL3_SHIFT (11U) -/*! SPOL3 - SSEL3 Polarity Select - * 0b0..Low. The SSEL3 pin is active low. - * 0b1..High. The SSEL3 pin is active high. - */ -#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) -/*! @} */ - -/*! @name DLY - Delay Register */ -/*! @{ */ - -#define SPI_DLY_PRE_DELAY_MASK (0xFU) -#define SPI_DLY_PRE_DELAY_SHIFT (0U) -/*! PRE_DELAY - Pre-Delay - * 0b0000..No additional time is inserted - * 0b0001..1 SPI clock time is inserted - * 0b0010..2 SPI clock times are inserted - * 0b1111..15 SPI clock times are inserted - */ -#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) - -#define SPI_DLY_POST_DELAY_MASK (0xF0U) -#define SPI_DLY_POST_DELAY_SHIFT (4U) -/*! POST_DELAY - Post-Delay - * 0b0000..No additional time is inserted - * 0b0001..1 SPI clock time is inserted - * 0b0010..2 SPI clock times are inserted - * 0b1111..15 SPI clock times are inserted - */ -#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) - -#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) -#define SPI_DLY_FRAME_DELAY_SHIFT (8U) -/*! FRAME_DELAY - Frame Delay - * 0b0000..No additional time is inserted - * 0b0001..1 SPI clock time is inserted - * 0b0010..2 SPI clock times are inserted - * 0b1111..15 SPI clock times are inserted - */ -#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) - -#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) -#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) -/*! TRANSFER_DELAY - Transfer Delay - * 0b0000..The minimum time that SSEL is deasserted is 1 SPI clock time (zero-added time) - * 0b0001..The minimum time that SSEL is deasserted is 2 SPI clock times - * 0b0010..The minimum time that SSEL is deasserted is 3 SPI clock times - * 0b1111..The minimum time that SSEL is deasserted is 16 SPI clock times - */ -#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) -/*! @} */ - -/*! @name STAT - Status Register */ -/*! @{ */ - -#define SPI_STAT_SSA_MASK (0x10U) -#define SPI_STAT_SSA_SHIFT (4U) -/*! SSA - Slave Select Assert - */ -#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) - -#define SPI_STAT_SSD_MASK (0x20U) -#define SPI_STAT_SSD_SHIFT (5U) -/*! SSD - Slave Select Deassert - */ -#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) - -#define SPI_STAT_STALLED_MASK (0x40U) -#define SPI_STAT_STALLED_SHIFT (6U) -/*! STALLED - Stalled Status Flag - */ -#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) - -#define SPI_STAT_ENDTRANSFER_MASK (0x80U) -#define SPI_STAT_ENDTRANSFER_SHIFT (7U) -/*! ENDTRANSFER - End Transfer Control - */ -#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) - -#define SPI_STAT_MSTIDLE_MASK (0x100U) -#define SPI_STAT_MSTIDLE_SHIFT (8U) -/*! MSTIDLE - Master Idle Status Flag - */ -#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable Register */ -/*! @{ */ - -#define SPI_INTENSET_SSAEN_MASK (0x10U) -#define SPI_INTENSET_SSAEN_SHIFT (4U) -/*! SSAEN - Slave Select Assert Interrupt Enable - * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. - * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. - */ -#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) - -#define SPI_INTENSET_SSDEN_MASK (0x20U) -#define SPI_INTENSET_SSDEN_SHIFT (5U) -/*! SSDEN - Slave Select Deassert Interrupt Enable - * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. - * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. - */ -#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) - -#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) -#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) -/*! MSTIDLEEN - Master Idle Interrupt Enable - * 0b0..No interrupt will be generated when the SPI master function is idle. - * 0b1..An interrupt will be generated when the SPI master function is fully idle. - */ -#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear Register */ -/*! @{ */ - -#define SPI_INTENCLR_SSAEN_MASK (0x10U) -#define SPI_INTENCLR_SSAEN_SHIFT (4U) -/*! SSAEN - Slave Select Assert Interrupt Enable - * 0b0..No effect - * 0b1..Clear the Slave Select Assert Interrupt Enable bit (INTENSET[SSAEN]) - */ -#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) - -#define SPI_INTENCLR_SSDEN_MASK (0x20U) -#define SPI_INTENCLR_SSDEN_SHIFT (5U) -/*! SSDEN - Slave Select Deassert Interrupt Enable - * 0b0..No effect - * 0b1..Clear the Slave Select Deassert Interrupt Enable bit (INTENSET[SSDEN]) - */ -#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) - -#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) -#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) -/*! MSTIDLE - Master Idle Interrupt Enable - * 0b0..No effect - * 0b1..Clear the Master Idle Interrupt Enable bit (INTENSET[MSTIDLE]) - */ -#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) -/*! @} */ - -/*! @name DIV - Clock Divider Register */ -/*! @{ */ - -#define SPI_DIV_DIVVAL_MASK (0xFFFFU) -#define SPI_DIV_DIVVAL_SHIFT (0U) -/*! DIVVAL - Rate Divider Value - */ -#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt Status Register */ -/*! @{ */ - -#define SPI_INTSTAT_SSA_MASK (0x10U) -#define SPI_INTSTAT_SSA_SHIFT (4U) -/*! SSA - Slave Select Assert Interrupt - * 0b0..Disabled - * 0b1..Enabled - */ -#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) - -#define SPI_INTSTAT_SSD_MASK (0x20U) -#define SPI_INTSTAT_SSD_SHIFT (5U) -/*! SSD - Slave Select Deassert Interrupt - * 0b0..Disabled - * 0b1..Enabled - */ -#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) - -#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) -#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) -/*! MSTIDLE - Master Idle Status Flag Interrupt - * 0b0..Disabled - * 0b1..Enabled - */ -#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO Configuration Register */ -/*! @{ */ - -#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) -#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the Transmit FIFO - * 0b0..The transmit FIFO is not enabled - * 0b1..The transmit FIFO is enabled - */ -#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) - -#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) -#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the Receive FIFO - * 0b0..The receive FIFO is not enabled - * 0b1..The receive FIFO is enabled - */ -#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) - -#define SPI_FIFOCFG_SIZE_MASK (0x30U) -#define SPI_FIFOCFG_SIZE_SHIFT (4U) -/*! SIZE - FIFO Size Configuration - * 0b00..FIFO is configured as 16 entries of 8 bits. - * 0b01..FIFO is configured as 8 entries of 16 bits. - * 0b10..Not used - * 0b11..Not used - */ -#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) - -#define SPI_FIFOCFG_DMATX_MASK (0x1000U) -#define SPI_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA Configuration for Transmit - * 0b0..DMA is not used for the transmit function - * 0b1..Issues DMA request for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) - -#define SPI_FIFOCFG_DMARX_MASK (0x2000U) -#define SPI_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA Configuration for Receive - * 0b0..DMA is not used for the receive function. - * 0b1..Issues a DMA request for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) - -#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) -#define SPI_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for Transmit FIFO Level - * 0b0..Only enabled interrupts will wake up the device form reduced power modes - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in - * FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) - -#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) -#define SPI_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for Receive FIFO Level - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by - * FIFOTRIG[RXLVL], even when the RXLVL interrupt is not enabled. - */ -#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) - -#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) -/*! EMPTYTX - Empty Command for the Transmit FIFO - * 0b0..No effect - * 0b1..The TX FIFO is emptied - */ -#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) - -#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) -/*! EMPTYRX - Empty Command for the Receive FIFO - * 0b0..No effect - * 0b1..The RX FIFO is emptied - */ -#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) - -#define SPI_FIFOCFG_POPDBG_MASK (0x40000U) -#define SPI_FIFOCFG_POPDBG_SHIFT (18U) -/*! POPDBG - Pop FIFO for Debug Reads - * 0b0..Debug reads of the FIFO do not pop the FIFO - * 0b1..A debug read will cause the FIFO to pop - */ -#define SPI_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO Status Register */ -/*! @{ */ - -#define SPI_FIFOSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO Error - * 0b0..A transmit FIFO error has not occurred. - * 0b1..A transmit FIFO error has occurred. This error could be an overflow caused by pushing data into a full - * FIFO, or by an underflow if the FIFO is empty when data is needed. - */ -#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) - -#define SPI_FIFOSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO Error - * 0b0..A receive FIFO overflow has not occurred - * 0b1..A receive FIFO overflow has occurred, caused by software or DMA not emptying the FIFO fast enough - */ -#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) - -#define SPI_FIFOSTAT_PERINT_MASK (0x8U) -#define SPI_FIFOSTAT_PERINT_SHIFT (3U) -/*! PERINT - Peripheral Interrupt - * 0b0..The peripheral function has not asserted an interrupt - * 0b1..Indicates that the peripheral function has asserted an interrupt. More information can be found by - * reading the peripheral's status register (STAT). - */ -#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) - -#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) -/*! TXEMPTY - Transmit FIFO Empty - * 0b0..The transmit FIFO is not empty - * 0b1..The transmit FIFO is empty, although the peripheral may still be processing the last piece of data. - */ -#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) - -#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) -/*! TXNOTFULL - Transmit FIFO is Not Full - * 0b0..The transmit FIFO is full and another write would cause it to overflow - * 0b1..The transmit FIFO is not full, so more data can be written - */ -#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) - -#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -/*! RXNOTEMPTY - Receive FIFO is Not Empty - * 0b0..When 0, the receive FIFO is empty - * 0b1..When 1, the receive FIFO is not empty, so data can be read - */ -#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) - -#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) -#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) -/*! RXFULL - Receive FIFO is Full - * 0b0..The receive FIFO is not full - * 0b1..The receive FIFO is full. To prevent the peripheral from causing an overflow, data should be read out. - */ -#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) - -#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO Current Level - */ -#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) - -#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO Current Level - */ -#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) - -#define SPI_FIFOSTAT_RXTIMEOUT_MASK (0x1000000U) -#define SPI_FIFOSTAT_RXTIMEOUT_SHIFT (24U) -/*! RXTIMEOUT - Receive FIFO Timeout - * 0b0..RX FIFO on - * 0b1..RX FIFO has timed out, based on the timeout configuration in the FIFORXTIMEOUTCFG register. - */ -#define SPI_FIFOSTAT_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXTIMEOUT_SHIFT)) & SPI_FIFOSTAT_RXTIMEOUT_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO Trigger Register */ -/*! @{ */ - -#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO Level Trigger Enable - * 0b0..Transmit FIFO level does not generate a FIFO level trigger - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the FIFOTRIG[TXLVL] field. - */ -#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) - -#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO Level Trigger Enable - * 0b0..Receive FIFO level does not generate a FIFO level trigger - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the FIFOTRIG[RXLVL] field. - */ -#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) - -#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) -#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO Level Trigger Point - * 0b0000..Trigger when the TX FIFO becomes empty - * 0b0001..Trigger when the TX FIFO level decreases to 1 entry - * 0b1111..Trigger when the TX FIFO level decreases to 15 entries (is no longer full) - */ -#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) - -#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO Level Trigger Point - * 0b0000..Trigger when the RX FIFO has received 1 entry (is no longer empty) - * 0b0001..Trigger when the RX FIFO has received 2 entries - * 0b1111..Trigger when the RX FIFO has received 16 entries (has become full) - */ -#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO Interrupt Enable Register */ -/*! @{ */ - -#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) -#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - TX Error Interrupt Enable - * 0b0..No interrupt will be generated for a transmit error - * 0b1..An interrupt will be generated when a transmit error occurs - */ -#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) - -#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) -#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Receive Error Interrupt Enable - * 0b0..No interrupt will be generated for a receive error - * 0b1..An interrupt will be generated when a receive error occurs - */ -#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) - -#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO Level Interrupt Enable - * 0b0..No interrupt will be generated based on the TX FIFO level - * 0b1..If FIFOTRIG[TXLVLENA]=1, then an interrupt will be generated when the TX FIFO level decreases to the level specified by FIFOTRIG[TXLVL] - */ -#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) - -#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO Level Interrupt Enable - * 0b0..No interrupt will be generated based on the RX FIFO level - * 0b1..If FIFOTRIG[RXLVLENA]=1, then an interrupt will be generated when the RX FIFO level increases to the level specified by FIFOTRIG[RXLVL] - */ -#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) - -#define SPI_FIFOINTENSET_RXTIMEOUT_MASK (0x1000000U) -#define SPI_FIFOINTENSET_RXTIMEOUT_SHIFT (24U) -/*! RXTIMEOUT - Receive Timeout - * 0b0..No RX interrupt will be generated. - * 0b1..Asserts RX interrupt if RX FIFO Timeout event occurs. - */ -#define SPI_FIFOINTENSET_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXTIMEOUT_SHIFT)) & SPI_FIFOINTENSET_RXTIMEOUT_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO Interrupt Enable Clear Register */ -/*! @{ */ - -#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) -#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) -/*! TXERR - TX Error Interrupt Enable - * 0b0..No effect - * 0b1..Clear the TX Error Interrupt Enable bit FIFOINTENSET[TXERR] - */ -#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) - -#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) -#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) -/*! RXERR - Receive Error Interrupt Enable - * 0b0..No effect - * 0b1..Clear the Receive Error Interrupt Enable bit FIFOINTENSET[RXERR] - */ -#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) - -#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO Level Interrupt Enable - * 0b0..No effect - * 0b1..Clear the Transmit FIFO Level Interrupt Enable bit FIFOINTENSET[TXLVL] - */ -#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) - -#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO Level Interrupt Enable - * 0b0..No effect - * 0b1..Clear the Receive FIFO Level Interrupt Enable bit FIFOINTENSET[RXLVL] - */ -#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) - -#define SPI_FIFOINTENCLR_RXTIMEOUT_MASK (0x1000000U) -#define SPI_FIFOINTENCLR_RXTIMEOUT_SHIFT (24U) -/*! RXTIMEOUT - Receive Timeout - * 0b0..No effect - * 0b1..Clear the interrupt - */ -#define SPI_FIFOINTENCLR_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXTIMEOUT_SHIFT)) & SPI_FIFOINTENCLR_RXTIMEOUT_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO Interrupt Status Register */ -/*! @{ */ - -#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO Error Interrupt Status - * 0b0..Not pending - * 0b1..Pending - */ -#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) - -#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO Error Interrupt Status - * 0b0..Not pending - * 0b1..Pending - */ -#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) - -#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO Level Interrupt Status - * 0b0..Not pending - * 0b1..Pending - */ -#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) - -#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO Level Interrupt Status - * 0b0..Not pending - * 0b1..Pending - */ -#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) - -#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) -#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) -/*! PERINT - Peripheral Interrupt Status - * 0b0..Not pending - * 0b1..Pending - */ -#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) - -#define SPI_FIFOINTSTAT_RXTIMEOUT_MASK (0x1000000U) -#define SPI_FIFOINTSTAT_RXTIMEOUT_SHIFT (24U) -/*! RXTIMEOUT - Receive Timeout Status - * 0b0..Not pending - * 0b1..Pending - */ -#define SPI_FIFOINTSTAT_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXTIMEOUT_SHIFT)) & SPI_FIFOINTSTAT_RXTIMEOUT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO Write Data Register */ -/*! @{ */ - -#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) -#define SPI_FIFOWR_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit Data to the FIFO - */ -#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) - -#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) -#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) -/*! TXSSEL0_N - Transmit Slave Select 0 - * 0b0..SSEL0 is asserted - * 0b1..SSEL0 is not asserted - */ -#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) - -#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) -#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) -/*! TXSSEL1_N - Transmit Slave Select 1 - * 0b0..SSEL1 is asserted - * 0b1..SSEL1 is not asserted - */ -#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) - -#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) -#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) -/*! TXSSEL2_N - Transmit Slave Select 2 - * 0b0..SSEL2 is asserted - * 0b1..SSEL2 is not asserted - */ -#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) - -#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) -#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) -/*! TXSSEL3_N - Transmit Slave Select 3 - * 0b0..SSEL3 is asserted - * 0b1..SSEL3 is not asserted - */ -#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) - -#define SPI_FIFOWR_EOT_MASK (0x100000U) -#define SPI_FIFOWR_EOT_SHIFT (20U) -/*! EOT - End of Transfer - * 0b0..SSEL is not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. - * 0b1..SSEL is deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. - */ -#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) - -#define SPI_FIFOWR_EOF_MASK (0x200000U) -#define SPI_FIFOWR_EOF_SHIFT (21U) -/*! EOF - End of Frame - * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame. - * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be - * inserted before subsequent data is transmitted. - */ -#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) - -#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) -#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) -/*! RXIGNORE - Receive Ignore - * 0b0..Read received data. Received data must be read, to allow transmission to proceed. SPI transmit will halt - * when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not - * read before new data is received. - * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received - * data. No receiver flags are generated. - */ -#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) - -#define SPI_FIFOWR_TXIGNORE_MASK (0x800000U) -#define SPI_FIFOWR_TXIGNORE_SHIFT (23U) -/*! TXIGNORE - Transmit Ignore - * 0b0..Write transmit data - * 0b1..Ignore transmit data - */ -#define SPI_FIFOWR_TXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXIGNORE_SHIFT)) & SPI_FIFOWR_TXIGNORE_MASK) - -#define SPI_FIFOWR_LEN_MASK (0xF000000U) -#define SPI_FIFOWR_LEN_SHIFT (24U) -/*! LEN - Data Length - * 0b0000..Reserved - * 0b0001..Reserved - * 0b0010..Reserved - * 0b0011..Data transfer is 4 bits in length - * 0b0100..Data transfer is 5 bits in length - * 0b1111..Data transfer is 16 bits in length - */ -#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO Read Data Register */ -/*! @{ */ - -#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORD_RXDATA_SHIFT (0U) -/*! RXDATA - Received Data from the FIFO - */ -#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) - -#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) -/*! RXSSEL0_N - Slave Select 0 for Receive - * 0b0..Slave Select 0 is active - * 0b1..Slave Select 0 is not active - */ -#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) - -#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) -/*! RXSSEL1_N - Slave Select 1 for Receive - * 0b0..Slave Select 1 is active - * 0b1..Slave Select 1 is not active - */ -#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) - -#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) -/*! RXSSEL2_N - Slave Select 2 for Receive - * 0b0..Slave Select 2 is active - * 0b1..Slave Select 2 is not active - */ -#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) - -#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) -/*! RXSSEL3_N - Slave Select 3 for Receive - * 0b0..Slave Select 3 is active - * 0b1..Slave Select 3 is not active - */ -#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) - -#define SPI_FIFORD_SOT_MASK (0x100000U) -#define SPI_FIFORD_SOT_SHIFT (20U) -/*! SOT - Start of Transfer Flag - * 0b0..This is not the 1st data after the SSELs went from deasserted to asserted - * 0b1..This is the 1st data after the SSELs went from deasserted to asserted (i.e., any previous transfer has - * ended). This information can be used to identify the 1st piece of data in cases where the transfer length is - * greater than 16 bits. - */ -#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO Data Read with no FIFO Pop Register */ -/*! @{ */ - -#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received Data from the FIFO - */ -#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) -/*! RXSSEL0_N - Slave Select 0 for Receive - * 0b0..Not selected - * 0b1..Selected - */ -#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) -/*! RXSSEL1_N - Slave Select 1 for Receive - * 0b0..Not selected - * 0b1..Selected - */ -#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) -/*! RXSSEL2_N - Slave Select 2 for Receive - * 0b0..Not selected - * 0b1..Selected - */ -#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) -/*! RXSSEL3_N - Slave Select 3 for Receive - * 0b0..Not selected - * 0b1..Selected - */ -#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) - -#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) -#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) -/*! SOT - Start of Transfer Flag - * 0b0..Not active - * 0b1..Active - */ -#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) -/*! @} */ - -/*! @name FIFOSIZE - FIFO Size Register */ -/*! @{ */ - -#define SPI_FIFOSIZE_FIFOSIZE_MASK (0x1FU) -#define SPI_FIFOSIZE_FIFOSIZE_SHIFT (0U) -/*! FIFOSIZE - FIFO Size - */ -#define SPI_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSIZE_FIFOSIZE_SHIFT)) & SPI_FIFOSIZE_FIFOSIZE_MASK) -/*! @} */ - -/*! @name FIFORXTIMEOUTCFG - FIFO Receive Timeout Configuration */ -/*! @{ */ - -#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK (0xFFU) -#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT (0U) -/*! RXTIMEOUT_PRESCALER - Receive Timeout Counter Clock Prescaler - */ -#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT)) & SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK) - -#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK (0xFFFF00U) -#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT (8U) -/*! RXTIMEOUT_VALUE - Receive Timeout Value - */ -#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT)) & SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK) - -#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK (0x1000000U) -#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT (24U) -/*! RXTIMEOUT_EN - Receive Timeout Enable - * 0b0..Disable RX FIFO timeout - * 0b1..Enable RX FIFO timeout - */ -#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_EN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT)) & SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK) - -#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK (0x2000000U) -#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT (25U) -/*! RXTIMEOUT_COW - Receive Timeout Continue On Write - * 0b0..RX FIFO timeout counter is reset every time data is transferred from the peripheral into the RX FIFO. - * 0b1..RX FIFO timeout counter is not reset every time data is transferred from the peripheral into the RX FIFO. - */ -#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COW(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT)) & SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK) - -#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK (0x4000000U) -#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT (26U) -/*! RXTIMEOUT_COE - Receive Timeout Continue On Empty - * 0b0..RX FIFO timeout counter is reset when the RX FIFO becomes empty. - * 0b1..RX FIFO timeout counter is not reset when the RX FIFO becomes empty. - */ -#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT)) & SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK) -/*! @} */ - -/*! @name FIFORXTIMEOUTCNT - FIFO Receive Timeout Counter */ -/*! @{ */ - -#define SPI_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK (0xFFFFU) -#define SPI_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT (0U) -/*! RXTIMEOUT_CNT - Current RX FIFO timeout counter value - */ -#define SPI_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT)) & SPI_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK) -/*! @} */ - -/*! @name ID - Peripheral Identification Register */ -/*! @{ */ - -#define SPI_ID_APERTURE_MASK (0xFFU) -#define SPI_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture - */ -#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) - -#define SPI_ID_MINOR_REV_MASK (0xF00U) -#define SPI_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation - */ -#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) - -#define SPI_ID_MAJOR_REV_MASK (0xF000U) -#define SPI_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation - */ -#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) - -#define SPI_ID_ID_MASK (0xFFFF0000U) -#define SPI_ID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function - */ -#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SPI_Register_Masks */ - - -/* SPI - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SPI0 base address */ - #define SPI0_BASE (0x50086000u) - /** Peripheral SPI0 base address */ - #define SPI0_BASE_NS (0x40086000u) - /** Peripheral SPI0 base pointer */ - #define SPI0 ((SPI_Type *)SPI0_BASE) - /** Peripheral SPI0 base pointer */ - #define SPI0_NS ((SPI_Type *)SPI0_BASE_NS) - /** Peripheral SPI1 base address */ - #define SPI1_BASE (0x50087000u) - /** Peripheral SPI1 base address */ - #define SPI1_BASE_NS (0x40087000u) - /** Peripheral SPI1 base pointer */ - #define SPI1 ((SPI_Type *)SPI1_BASE) - /** Peripheral SPI1 base pointer */ - #define SPI1_NS ((SPI_Type *)SPI1_BASE_NS) - /** Peripheral SPI2 base address */ - #define SPI2_BASE (0x50088000u) - /** Peripheral SPI2 base address */ - #define SPI2_BASE_NS (0x40088000u) - /** Peripheral SPI2 base pointer */ - #define SPI2 ((SPI_Type *)SPI2_BASE) - /** Peripheral SPI2 base pointer */ - #define SPI2_NS ((SPI_Type *)SPI2_BASE_NS) - /** Peripheral SPI3 base address */ - #define SPI3_BASE (0x50089000u) - /** Peripheral SPI3 base address */ - #define SPI3_BASE_NS (0x40089000u) - /** Peripheral SPI3 base pointer */ - #define SPI3 ((SPI_Type *)SPI3_BASE) - /** Peripheral SPI3 base pointer */ - #define SPI3_NS ((SPI_Type *)SPI3_BASE_NS) - /** Peripheral SPI4 base address */ - #define SPI4_BASE (0x5008A000u) - /** Peripheral SPI4 base address */ - #define SPI4_BASE_NS (0x4008A000u) - /** Peripheral SPI4 base pointer */ - #define SPI4 ((SPI_Type *)SPI4_BASE) - /** Peripheral SPI4 base pointer */ - #define SPI4_NS ((SPI_Type *)SPI4_BASE_NS) - /** Peripheral SPI5 base address */ - #define SPI5_BASE (0x50096000u) - /** Peripheral SPI5 base address */ - #define SPI5_BASE_NS (0x40096000u) - /** Peripheral SPI5 base pointer */ - #define SPI5 ((SPI_Type *)SPI5_BASE) - /** Peripheral SPI5 base pointer */ - #define SPI5_NS ((SPI_Type *)SPI5_BASE_NS) - /** Peripheral SPI6 base address */ - #define SPI6_BASE (0x50097000u) - /** Peripheral SPI6 base address */ - #define SPI6_BASE_NS (0x40097000u) - /** Peripheral SPI6 base pointer */ - #define SPI6 ((SPI_Type *)SPI6_BASE) - /** Peripheral SPI6 base pointer */ - #define SPI6_NS ((SPI_Type *)SPI6_BASE_NS) - /** Peripheral SPI7 base address */ - #define SPI7_BASE (0x50098000u) - /** Peripheral SPI7 base address */ - #define SPI7_BASE_NS (0x40098000u) - /** Peripheral SPI7 base pointer */ - #define SPI7 ((SPI_Type *)SPI7_BASE) - /** Peripheral SPI7 base pointer */ - #define SPI7_NS ((SPI_Type *)SPI7_BASE_NS) - /** Peripheral SPI8 base address */ - #define SPI8_BASE (0x5009F000u) - /** Peripheral SPI8 base address */ - #define SPI8_BASE_NS (0x4009F000u) - /** Peripheral SPI8 base pointer */ - #define SPI8 ((SPI_Type *)SPI8_BASE) - /** Peripheral SPI8 base pointer */ - #define SPI8_NS ((SPI_Type *)SPI8_BASE_NS) - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS_NS { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS_NS { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS } -#else - /** Peripheral SPI0 base address */ - #define SPI0_BASE (0x40086000u) - /** Peripheral SPI0 base pointer */ - #define SPI0 ((SPI_Type *)SPI0_BASE) - /** Peripheral SPI1 base address */ - #define SPI1_BASE (0x40087000u) - /** Peripheral SPI1 base pointer */ - #define SPI1 ((SPI_Type *)SPI1_BASE) - /** Peripheral SPI2 base address */ - #define SPI2_BASE (0x40088000u) - /** Peripheral SPI2 base pointer */ - #define SPI2 ((SPI_Type *)SPI2_BASE) - /** Peripheral SPI3 base address */ - #define SPI3_BASE (0x40089000u) - /** Peripheral SPI3 base pointer */ - #define SPI3 ((SPI_Type *)SPI3_BASE) - /** Peripheral SPI4 base address */ - #define SPI4_BASE (0x4008A000u) - /** Peripheral SPI4 base pointer */ - #define SPI4 ((SPI_Type *)SPI4_BASE) - /** Peripheral SPI5 base address */ - #define SPI5_BASE (0x40096000u) - /** Peripheral SPI5 base pointer */ - #define SPI5 ((SPI_Type *)SPI5_BASE) - /** Peripheral SPI6 base address */ - #define SPI6_BASE (0x40097000u) - /** Peripheral SPI6 base pointer */ - #define SPI6 ((SPI_Type *)SPI6_BASE) - /** Peripheral SPI7 base address */ - #define SPI7_BASE (0x40098000u) - /** Peripheral SPI7 base pointer */ - #define SPI7 ((SPI_Type *)SPI7_BASE) - /** Peripheral SPI8 base address */ - #define SPI8_BASE (0x4009F000u) - /** Peripheral SPI8 base pointer */ - #define SPI8 ((SPI_Type *)SPI8_BASE) - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } -#endif -/** Interrupt vectors for the SPI peripheral type */ -#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } - -/*! - * @} - */ /* end of group SPI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPI_FILTER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_FILTER_Peripheral_Access_Layer SPI_FILTER Peripheral Access Layer - * @{ - */ - -/** SPI_FILTER - Register Layout Typedef */ -typedef struct { - __IO uint32_t CR; /**< Control, offset: 0x0 */ - __I uint32_t ISR; /**< Interrupt Register, offset: 0x4 */ - __IO uint32_t IMR; /**< Interrupt Mask Register, offset: 0x8 */ - __I uint32_t SR; /**< Status Register, offset: 0xC */ - __IO uint32_t TCR; /**< Test Control Register, offset: 0x10 */ - __IO uint32_t P0FAR1; /**< Port 0 filter address region 1, offset: 0x14 */ - __IO uint32_t P0FAR2; /**< Port 0 filter address region 2, offset: 0x18 */ - __IO uint32_t P0FAR3; /**< Port 0 filter address region 3, offset: 0x1C */ - __IO uint32_t P1FAR1; /**< Port 1 filter address region 1, offset: 0x20 */ - __IO uint32_t P1FAR2; /**< Port 1 filter address region 2, offset: 0x24 */ - __IO uint32_t P1FAR3; /**< Port 1 filter address region 3, offset: 0x28 */ - uint8_t RESERVED_0[4]; - __I uint32_t VER; /**< Version, offset: 0x30 */ - uint8_t RESERVED_1[12]; - __IO uint32_t POPCODE0; /**< Programmable OP-Code0, offset: 0x40 */ - __IO uint32_t POPCODE1; /**< Programmable OP-Code1, offset: 0x44 */ - __IO uint32_t POPCODE2; /**< Programmable OP-Code2, offset: 0x48 */ - __IO uint32_t POPCODE3; /**< Programmable OP-Code3, offset: 0x4C */ - __IO uint32_t POPCODE4; /**< Programmable OP-Code4, offset: 0x50 */ - __I uint32_t P0BOC; /**< P0 Blocked Op Code, offset: 0x54 */ - __I uint32_t P1BOC; /**< P1 Blocked Op Code, offset: 0x58 */ - __IO uint32_t P0MAM; /**< Port 0 Max Address Mask, offset: 0x5C */ - __IO uint32_t P1MAM; /**< Port 1 Max Address Mask, offset: 0x60 */ -} SPI_FILTER_Type; - -/* ---------------------------------------------------------------------------- - -- SPI_FILTER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_FILTER_Register_Masks SPI_FILTER Register Masks - * @{ - */ - -/*! @name CR - Control */ -/*! @{ */ - -#define SPI_FILTER_CR_P1_ACT_SEL_MASK (0x10000U) -#define SPI_FILTER_CR_P1_ACT_SEL_SHIFT (16U) -/*! P1_ACT_SEL - Active Chip Select for P1 filter - * 0b0..Sets CS0 as the read location for the firmware image and sets CS1 as the write location for the FW image. - * 0b1..Sets CS1 as the read location for the firmware image and sets CS0 as the write location for the FW image. - */ -#define SPI_FILTER_CR_P1_ACT_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P1_ACT_SEL_SHIFT)) & SPI_FILTER_CR_P1_ACT_SEL_MASK) - -#define SPI_FILTER_CR_P1_BYTE_SEL_MASK (0x20000U) -#define SPI_FILTER_CR_P1_BYTE_SEL_SHIFT (17U) -/*! P1_BYTE_SEL - Address Byte Select Mode for P1 - * 0b0..Sets the filter to 4-byte address mode - * 0b1..Sets the filter to 3-byte address mode - */ -#define SPI_FILTER_CR_P1_BYTE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P1_BYTE_SEL_SHIFT)) & SPI_FILTER_CR_P1_BYTE_SEL_MASK) - -#define SPI_FILTER_CR_P1_BYTE_SEL_MD_MASK (0x40000U) -#define SPI_FILTER_CR_P1_BYTE_SEL_MD_SHIFT (18U) -/*! P1_BYTE_SEL_MD - Address Byte Select Mode for P1 - * 0b0..Normal Operation. The Address byte mode is determined by the Op Code Command - * 0b1..Sets the Byte Mode to 3-byte and gives control of the function to the P1_BYTE_SEL in the P1 Filter - * Control Register. In this mode, any changes to P1_BYTE_SEL are latched and the internal state of P1_BYTE_SEL - * will retain this value when P1_BYTE_SEL_MD is cleared - */ -#define SPI_FILTER_CR_P1_BYTE_SEL_MD(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P1_BYTE_SEL_MD_SHIFT)) & SPI_FILTER_CR_P1_BYTE_SEL_MD_MASK) - -#define SPI_FILTER_CR_P1_DIRTY_CLR_MASK (0x80000U) -#define SPI_FILTER_CR_P1_DIRTY_CLR_SHIFT (19U) -/*! P1_DIRTY_CLR - Clear dirty state for P1 - */ -#define SPI_FILTER_CR_P1_DIRTY_CLR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P1_DIRTY_CLR_SHIFT)) & SPI_FILTER_CR_P1_DIRTY_CLR_MASK) - -#define SPI_FILTER_CR_P1_FLT_EN_MASK (0x100000U) -#define SPI_FILTER_CR_P1_FLT_EN_SHIFT (20U) -/*! P1_FLT_EN - Filter Enable bit for P1 filter - * 0b0..Filter Disabled. All CS Disable outputs are asserted so that host access to the flash devices is - * disabled. CS# inputs to the filter are disabled so that the filter state machine is locked in its current state. - * All register controls remain functional. - * 0b1..Filter Enabled. CS# inputs to the filter are enabled and the filter state machine controls the CS disable - * outputs. This bit takes priority over the P1_BYP_EN bit in the Test Control Register. Setting this bit - * will enable filtering and will enable communication to flash devices regardless of the state of P1_BYP_EN. - * All other register controls remain functional while filtering is enabled. - */ -#define SPI_FILTER_CR_P1_FLT_EN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P1_FLT_EN_SHIFT)) & SPI_FILTER_CR_P1_FLT_EN_MASK) - -#define SPI_FILTER_CR_P1_FLASH_MD_MASK (0x200000U) -#define SPI_FILTER_CR_P1_FLASH_MD_SHIFT (21U) -/*! P1_FLASH_MD - Flash Mode Select for P1 - * 0b0..Dual Flash Mode. Supports two separate physical flash devices as described in Section 3.1 - * 0b1..Single Flash Mode. Supports a single physical flash device as described in Section 3.2. Note that all - * Chip Erase Op Codes are blocked when in this mode. - */ -#define SPI_FILTER_CR_P1_FLASH_MD(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P1_FLASH_MD_SHIFT)) & SPI_FILTER_CR_P1_FLASH_MD_MASK) - -#define SPI_FILTER_CR_P0_ACT_SEL_MASK (0x1000000U) -#define SPI_FILTER_CR_P0_ACT_SEL_SHIFT (24U) -/*! P0_ACT_SEL - Active Chip Select for P0 filter - * 0b0..Sets CS0 as the read location for the firmware image and sets CS1 as the write location for the FW image. - * 0b1..Sets CS1 as the read location for the firmware image and sets CS0 as the write location for the FW image. - */ -#define SPI_FILTER_CR_P0_ACT_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P0_ACT_SEL_SHIFT)) & SPI_FILTER_CR_P0_ACT_SEL_MASK) - -#define SPI_FILTER_CR_P0_BYTE_SEL_MASK (0x2000000U) -#define SPI_FILTER_CR_P0_BYTE_SEL_SHIFT (25U) -/*! P0_BYTE_SEL - Address Byte Select for P0 filter - * 0b0..Sets the filter to 3-byte address mode - * 0b1..Sets the filter to 4-byte address mode - */ -#define SPI_FILTER_CR_P0_BYTE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P0_BYTE_SEL_SHIFT)) & SPI_FILTER_CR_P0_BYTE_SEL_MASK) - -#define SPI_FILTER_CR_P0_BYTE_SEL_MD_MASK (0x4000000U) -#define SPI_FILTER_CR_P0_BYTE_SEL_MD_SHIFT (26U) -/*! P0_BYTE_SEL_MD - Address Byte Select Mode for P0 filter - * 0b0..Normal Operation. The Address byte mode is determined by the Op Code Command - * 0b1..Sets the Byte Mode to 3-byte and gives control of the function to the P0_BYTE_SEL in the P0 Filter - * Control Register. In this mode, any changes to P0_BYTE_SEL are latched and the internal state of BYTE_SEL will - * retain this value when P0_BYTE_SEL_MD is cleared. - */ -#define SPI_FILTER_CR_P0_BYTE_SEL_MD(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P0_BYTE_SEL_MD_SHIFT)) & SPI_FILTER_CR_P0_BYTE_SEL_MD_MASK) - -#define SPI_FILTER_CR_P0_DIRTY_CLR_MASK (0x8000000U) -#define SPI_FILTER_CR_P0_DIRTY_CLR_SHIFT (27U) -/*! P0_DIRTY_CLR - Clear dirty state for P0 - */ -#define SPI_FILTER_CR_P0_DIRTY_CLR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P0_DIRTY_CLR_SHIFT)) & SPI_FILTER_CR_P0_DIRTY_CLR_MASK) - -#define SPI_FILTER_CR_P0_FLT_EN_MASK (0x10000000U) -#define SPI_FILTER_CR_P0_FLT_EN_SHIFT (28U) -/*! P0_FLT_EN - Filter Enable bit for P0 - * 0b0..Filter Enabled. CS# inputs to the filter are enabled and the filter state machine controls the CS disable - * outputs. CS# inputs to the filter are enabled so that the filter state machine is active. All other - * register controls are functional. - * 0b1..Filter Disabled. All CS Disable outputs are asserted so that host access to the flash devices is - * disabled. CS# inputs to the filter are disabled so that the filter state machine is locked in its current state. - * All other register controls can be accessed, but have no impact on the functionality of the filter while - * the filter is disabled. - */ -#define SPI_FILTER_CR_P0_FLT_EN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P0_FLT_EN_SHIFT)) & SPI_FILTER_CR_P0_FLT_EN_MASK) - -#define SPI_FILTER_CR_P0_FLASH_MD_MASK (0x20000000U) -#define SPI_FILTER_CR_P0_FLASH_MD_SHIFT (29U) -/*! P0_FLASH_MD - Flash Mode Select for P0 - * 0b0..Dual Flash Mode. Supports two separate physical flash devices as described in Section 3.1 - * 0b1..Single Flash Mode. Supports a single physical flash device as described in Section 3.2. Note that all - * Chip Erase Op Codes are blocked when in this mode. - */ -#define SPI_FILTER_CR_P0_FLASH_MD(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P0_FLASH_MD_SHIFT)) & SPI_FILTER_CR_P0_FLASH_MD_MASK) -/*! @} */ - -/*! @name ISR - Interrupt Register */ -/*! @{ */ - -#define SPI_FILTER_ISR_P0_DIRTY_INT_MASK (0x1000000U) -#define SPI_FILTER_ISR_P0_DIRTY_INT_SHIFT (24U) -/*! P0_DIRTY_INT - * 0b0..Indicates that a write has occurred to the FW Code region of the inactive Flash and that flash is now considered corrupt - * 0b1..Indicates normal operation - */ -#define SPI_FILTER_ISR_P0_DIRTY_INT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P0_DIRTY_INT_SHIFT)) & SPI_FILTER_ISR_P0_DIRTY_INT_MASK) - -#define SPI_FILTER_ISR_P1_DIRTY_INT_MASK (0x2000000U) -#define SPI_FILTER_ISR_P1_DIRTY_INT_SHIFT (25U) -/*! P1_DIRTY_INT - * 0b0..Indicates normal operation - * 0b1..indicates that a write has occurred to the FW Code region of the inactive Flash and that flash is now considered corrupt - */ -#define SPI_FILTER_ISR_P1_DIRTY_INT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P1_DIRTY_INT_SHIFT)) & SPI_FILTER_ISR_P1_DIRTY_INT_MASK) - -#define SPI_FILTER_ISR_P0_BLK_INT_MASK (0x4000000U) -#define SPI_FILTER_ISR_P0_BLK_INT_SHIFT (26U) -/*! P0_BLK_INT - * 0b0..Indicates normal operation - * 0b1..Indicates that a blocked opcode has been detected - */ -#define SPI_FILTER_ISR_P0_BLK_INT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P0_BLK_INT_SHIFT)) & SPI_FILTER_ISR_P0_BLK_INT_MASK) - -#define SPI_FILTER_ISR_P1_BLK_INT_MASK (0x8000000U) -#define SPI_FILTER_ISR_P1_BLK_INT_SHIFT (27U) -/*! P1_BLK_INT - * 0b0..Indicates normal operation - * 0b1..Indicates that a blocked opcode has been detected - */ -#define SPI_FILTER_ISR_P1_BLK_INT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P1_BLK_INT_SHIFT)) & SPI_FILTER_ISR_P1_BLK_INT_MASK) - -#define SPI_FILTER_ISR_P0_BYTEMODE_INT_MASK (0x10000000U) -#define SPI_FILTER_ISR_P0_BYTEMODE_INT_SHIFT (28U) -/*! P0_BYTEMODE_INT - * 0b0..Indicates normal operation - * 0b1..Indicates that a Bytemode change has been detected (OpCode E9 or B7) - */ -#define SPI_FILTER_ISR_P0_BYTEMODE_INT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P0_BYTEMODE_INT_SHIFT)) & SPI_FILTER_ISR_P0_BYTEMODE_INT_MASK) - -#define SPI_FILTER_ISR_P1_BYTEMODE_INT_MASK (0x20000000U) -#define SPI_FILTER_ISR_P1_BYTEMODE_INT_SHIFT (29U) -/*! P1_BYTEMODE_INT - * 0b0..Indicates normal operation - * 0b1..Indicates that a Bytemode change has been detected (OpCode E9 or B7) - */ -#define SPI_FILTER_ISR_P1_BYTEMODE_INT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P1_BYTEMODE_INT_SHIFT)) & SPI_FILTER_ISR_P1_BYTEMODE_INT_MASK) - -#define SPI_FILTER_ISR_P0_F8_INT_MASK (0x40000000U) -#define SPI_FILTER_ISR_P0_F8_INT_SHIFT (30U) -/*! P0_F8_INT - * 0b0..Indicates normal operation - * 0b1..Indicates an F8 command has been detected - */ -#define SPI_FILTER_ISR_P0_F8_INT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P0_F8_INT_SHIFT)) & SPI_FILTER_ISR_P0_F8_INT_MASK) - -#define SPI_FILTER_ISR_P1_F8_INT_MASK (0x80000000U) -#define SPI_FILTER_ISR_P1_F8_INT_SHIFT (31U) -/*! P1_F8_INT - * 0b0..Indicates normal operation - * 0b1..Indicates an F8 command has been detected - */ -#define SPI_FILTER_ISR_P1_F8_INT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P1_F8_INT_SHIFT)) & SPI_FILTER_ISR_P1_F8_INT_MASK) -/*! @} */ - -/*! @name IMR - Interrupt Mask Register */ -/*! @{ */ - -#define SPI_FILTER_IMR_P0_DIRTY_MASK_MASK (0x1000000U) -#define SPI_FILTER_IMR_P0_DIRTY_MASK_SHIFT (24U) -/*! P0_DIRTY_MASK - Mask bit for P0_DIRTY_INT - * 0b0..Indicates P0_DIRTY_INT interrupt is disabled. - * 0b1..Indicates P0_DIRTY_INT interrupt is enabled. - */ -#define SPI_FILTER_IMR_P0_DIRTY_MASK(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P0_DIRTY_MASK_SHIFT)) & SPI_FILTER_IMR_P0_DIRTY_MASK_MASK) - -#define SPI_FILTER_IMR_P1_DIRTY_MASK_MASK (0x2000000U) -#define SPI_FILTER_IMR_P1_DIRTY_MASK_SHIFT (25U) -/*! P1_DIRTY_MASK - Mask bit for P1_DIRTY_INT - * 0b0..Indicates normal operation. P1_DIRTY_INT interrupt is enabled. - * 0b1..Indicates P1_DIRTY_INT interrupt is disabled. - */ -#define SPI_FILTER_IMR_P1_DIRTY_MASK(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P1_DIRTY_MASK_SHIFT)) & SPI_FILTER_IMR_P1_DIRTY_MASK_MASK) - -#define SPI_FILTER_IMR_P0_BLK_MASK_MASK (0x4000000U) -#define SPI_FILTER_IMR_P0_BLK_MASK_SHIFT (26U) -/*! P0_BLK_MASK - Mask bit for P0_BLK_MASK - * 0b0..Indicates P0_BLK_MASK is enabled. - * 0b1..Indicates P0_BLK_MASK is disabled. - */ -#define SPI_FILTER_IMR_P0_BLK_MASK(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P0_BLK_MASK_SHIFT)) & SPI_FILTER_IMR_P0_BLK_MASK_MASK) - -#define SPI_FILTER_IMR_P1_BLK_MASK_MASK (0x8000000U) -#define SPI_FILTER_IMR_P1_BLK_MASK_SHIFT (27U) -/*! P1_BLK_MASK - Mask bit for P1_BLK_MASK - * 0b0..Indicates P1_BLK_MASK is enabled. - * 0b1..Indicates P1_BLK_MASK is disabled. - */ -#define SPI_FILTER_IMR_P1_BLK_MASK(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P1_BLK_MASK_SHIFT)) & SPI_FILTER_IMR_P1_BLK_MASK_MASK) - -#define SPI_FILTER_IMR_P0_BYTEMODE_MASK_MASK (0x10000000U) -#define SPI_FILTER_IMR_P0_BYTEMODE_MASK_SHIFT (28U) -/*! P0_BYTEMODE_MASK - Mask bit for P0_BYTEMODE_MASK - * 0b0..Indicates P0_BYTEMODE_MASK is enabled. - * 0b1..Indicates P0_BYTEMODE_MASK is disabled. - */ -#define SPI_FILTER_IMR_P0_BYTEMODE_MASK(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P0_BYTEMODE_MASK_SHIFT)) & SPI_FILTER_IMR_P0_BYTEMODE_MASK_MASK) - -#define SPI_FILTER_IMR_P1_BYTEMODE_MASK_MASK (0x20000000U) -#define SPI_FILTER_IMR_P1_BYTEMODE_MASK_SHIFT (29U) -/*! P1_BYTEMODE_MASK - Mask bit for P1_BYTEMODE_MASK - * 0b0..Indicates P1_BYTEMODE_MASK is enabled. - * 0b1..Indicates P1_BYTEMODE_MASK is disabled. - */ -#define SPI_FILTER_IMR_P1_BYTEMODE_MASK(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P1_BYTEMODE_MASK_SHIFT)) & SPI_FILTER_IMR_P1_BYTEMODE_MASK_MASK) - -#define SPI_FILTER_IMR_P0_F8_MASK_MASK (0x40000000U) -#define SPI_FILTER_IMR_P0_F8_MASK_SHIFT (30U) -/*! P0_F8_MASK - Mask bit for P0_F8_MASK - * 0b0..Indicates P0_F8_MASK is enabled. - * 0b1..Indicates P0_F8_MASK is disabled. - */ -#define SPI_FILTER_IMR_P0_F8_MASK(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P0_F8_MASK_SHIFT)) & SPI_FILTER_IMR_P0_F8_MASK_MASK) - -#define SPI_FILTER_IMR_P1_F8_MASK_MASK (0x80000000U) -#define SPI_FILTER_IMR_P1_F8_MASK_SHIFT (31U) -/*! P1_F8_MASK - Mask bit for P1_F8_MASK - * 0b0..Indicates P1_F8_MASK is enabled. - * 0b1..Indicates P1_F8_MASK is disabled. - */ -#define SPI_FILTER_IMR_P1_F8_MASK(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P1_F8_MASK_SHIFT)) & SPI_FILTER_IMR_P1_F8_MASK_MASK) -/*! @} */ - -/*! @name SR - Status Register */ -/*! @{ */ - -#define SPI_FILTER_SR_P1_DIRTY_MASK (0x10000U) -#define SPI_FILTER_SR_P1_DIRTY_SHIFT (16U) -/*! P1_DIRTY - * 0b1..Indicates that a write to the inactive Flash has been detected and the state of the flash should be considered "dirty". - * 0b1..Indicates normal operation. No Writes have been directed to the inactive Flash - */ -#define SPI_FILTER_SR_P1_DIRTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_SR_P1_DIRTY_SHIFT)) & SPI_FILTER_SR_P1_DIRTY_MASK) - -#define SPI_FILTER_SR_P1_BYTE_MODE_MASK (0x20000U) -#define SPI_FILTER_SR_P1_BYTE_MODE_SHIFT (17U) -/*! P1_BYTE_MODE - * 0b0..3-Byte Address Mode - * 0b1..4-Byte Address Mode - */ -#define SPI_FILTER_SR_P1_BYTE_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_SR_P1_BYTE_MODE_SHIFT)) & SPI_FILTER_SR_P1_BYTE_MODE_MASK) - -#define SPI_FILTER_SR_P0_DIRTY_MASK (0x1000000U) -#define SPI_FILTER_SR_P0_DIRTY_SHIFT (24U) -/*! P0_DIRTY - * 0b0..Indicates normal operation. No Writes have been directed to the inactive Flash - * 0b1..Indicates that a write to the inactive Flash has been detected and the state of the flash should be considered "dirty". - */ -#define SPI_FILTER_SR_P0_DIRTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_SR_P0_DIRTY_SHIFT)) & SPI_FILTER_SR_P0_DIRTY_MASK) - -#define SPI_FILTER_SR_P0_BYTE_MODE_MASK (0x2000000U) -#define SPI_FILTER_SR_P0_BYTE_MODE_SHIFT (25U) -/*! P0_BYTE_MODE - * 0b0..3-Byte Address Mode - * 0b1..4-Byte Address Mode - */ -#define SPI_FILTER_SR_P0_BYTE_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_SR_P0_BYTE_MODE_SHIFT)) & SPI_FILTER_SR_P0_BYTE_MODE_MASK) -/*! @} */ - -/*! @name TCR - Test Control Register */ -/*! @{ */ - -#define SPI_FILTER_TCR_P0_BYP_SEL_MASK (0x10000U) -#define SPI_FILTER_TCR_P0_BYP_SEL_SHIFT (16U) -/*! P0_BYP_SEL - * 0b0..CS0 - * 0b1..CS1 - */ -#define SPI_FILTER_TCR_P0_BYP_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_TCR_P0_BYP_SEL_SHIFT)) & SPI_FILTER_TCR_P0_BYP_SEL_MASK) - -#define SPI_FILTER_TCR_P0_BYP_EN_MASK (0x20000U) -#define SPI_FILTER_TCR_P0_BYP_EN_SHIFT (17U) -/*! P0_BYP_EN - * 0b0..Filter Bypass Disabled - * 0b1..Filter Bypass Enabled - */ -#define SPI_FILTER_TCR_P0_BYP_EN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_TCR_P0_BYP_EN_SHIFT)) & SPI_FILTER_TCR_P0_BYP_EN_MASK) - -#define SPI_FILTER_TCR_P1_BYP_SEL_MASK (0x40000U) -#define SPI_FILTER_TCR_P1_BYP_SEL_SHIFT (18U) -/*! P1_BYP_SEL - * 0b0..CS0 - * 0b1..CS1 - */ -#define SPI_FILTER_TCR_P1_BYP_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_TCR_P1_BYP_SEL_SHIFT)) & SPI_FILTER_TCR_P1_BYP_SEL_MASK) - -#define SPI_FILTER_TCR_P1_BYP_EN_MASK (0x80000U) -#define SPI_FILTER_TCR_P1_BYP_EN_SHIFT (19U) -/*! P1_BYP_EN - * 0b0..Filter Bypass Disabled - * 0b1..Filter Bypass Enabled - */ -#define SPI_FILTER_TCR_P1_BYP_EN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_TCR_P1_BYP_EN_SHIFT)) & SPI_FILTER_TCR_P1_BYP_EN_MASK) - -#define SPI_FILTER_TCR_P0_MFG_ID_MASK (0xF000000U) -#define SPI_FILTER_TCR_P0_MFG_ID_SHIFT (24U) -/*! P0_MFG_ID - Sets the Flash memory manufacturer - * 0b0010..Micron - * 0b0001..Windbond - * 0b0000..Macronix - */ -#define SPI_FILTER_TCR_P0_MFG_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_TCR_P0_MFG_ID_SHIFT)) & SPI_FILTER_TCR_P0_MFG_ID_MASK) - -#define SPI_FILTER_TCR_P1_MFG_ID_MASK (0xF0000000U) -#define SPI_FILTER_TCR_P1_MFG_ID_SHIFT (28U) -/*! P1_MFG_ID - Sets the Flash memory manufacturer - * 0b0010..Micron - * 0b0001..Windbond - * 0b0000..Macronix - */ -#define SPI_FILTER_TCR_P1_MFG_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_TCR_P1_MFG_ID_SHIFT)) & SPI_FILTER_TCR_P1_MFG_ID_MASK) -/*! @} */ - -/*! @name P0FAR1 - Port 0 filter address region 1 */ -/*! @{ */ - -#define SPI_FILTER_P0FAR1_ADDRESS_LOWER_LSBS_MASK (0xFFU) -#define SPI_FILTER_P0FAR1_ADDRESS_LOWER_LSBS_SHIFT (0U) -/*! ADDRESS_LOWER_LSBS - Address Lower LSBs - */ -#define SPI_FILTER_P0FAR1_ADDRESS_LOWER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR1_ADDRESS_LOWER_LSBS_SHIFT)) & SPI_FILTER_P0FAR1_ADDRESS_LOWER_LSBS_MASK) - -#define SPI_FILTER_P0FAR1_ADDRESS_LOWER_MSBS_MASK (0xFF00U) -#define SPI_FILTER_P0FAR1_ADDRESS_LOWER_MSBS_SHIFT (8U) -/*! ADDRESS_LOWER_MSBS - Address Lower MSBs - */ -#define SPI_FILTER_P0FAR1_ADDRESS_LOWER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR1_ADDRESS_LOWER_MSBS_SHIFT)) & SPI_FILTER_P0FAR1_ADDRESS_LOWER_MSBS_MASK) - -#define SPI_FILTER_P0FAR1_ADDRESS_UPPER_LSBS_MASK (0xFF0000U) -#define SPI_FILTER_P0FAR1_ADDRESS_UPPER_LSBS_SHIFT (16U) -/*! ADDRESS_UPPER_LSBS - Address Upper LSBs - */ -#define SPI_FILTER_P0FAR1_ADDRESS_UPPER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR1_ADDRESS_UPPER_LSBS_SHIFT)) & SPI_FILTER_P0FAR1_ADDRESS_UPPER_LSBS_MASK) - -#define SPI_FILTER_P0FAR1_ADDRESS_UPPER_MSBS_MASK (0xFF000000U) -#define SPI_FILTER_P0FAR1_ADDRESS_UPPER_MSBS_SHIFT (24U) -/*! ADDRESS_UPPER_MSBS - Address Upper MSBs - */ -#define SPI_FILTER_P0FAR1_ADDRESS_UPPER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR1_ADDRESS_UPPER_MSBS_SHIFT)) & SPI_FILTER_P0FAR1_ADDRESS_UPPER_MSBS_MASK) -/*! @} */ - -/*! @name P0FAR2 - Port 0 filter address region 2 */ -/*! @{ */ - -#define SPI_FILTER_P0FAR2_ADDRESS_LOWER_LSBS_MASK (0xFFU) -#define SPI_FILTER_P0FAR2_ADDRESS_LOWER_LSBS_SHIFT (0U) -/*! ADDRESS_LOWER_LSBS - Address Lower LSBs - */ -#define SPI_FILTER_P0FAR2_ADDRESS_LOWER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR2_ADDRESS_LOWER_LSBS_SHIFT)) & SPI_FILTER_P0FAR2_ADDRESS_LOWER_LSBS_MASK) - -#define SPI_FILTER_P0FAR2_ADDRESS_LOWER_MSBS_MASK (0xFF00U) -#define SPI_FILTER_P0FAR2_ADDRESS_LOWER_MSBS_SHIFT (8U) -/*! ADDRESS_LOWER_MSBS - Address Lower MSBs - */ -#define SPI_FILTER_P0FAR2_ADDRESS_LOWER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR2_ADDRESS_LOWER_MSBS_SHIFT)) & SPI_FILTER_P0FAR2_ADDRESS_LOWER_MSBS_MASK) - -#define SPI_FILTER_P0FAR2_ADDRESS_UPPER_LSBS_MASK (0xFF0000U) -#define SPI_FILTER_P0FAR2_ADDRESS_UPPER_LSBS_SHIFT (16U) -/*! ADDRESS_UPPER_LSBS - Address Upper LSBs - */ -#define SPI_FILTER_P0FAR2_ADDRESS_UPPER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR2_ADDRESS_UPPER_LSBS_SHIFT)) & SPI_FILTER_P0FAR2_ADDRESS_UPPER_LSBS_MASK) - -#define SPI_FILTER_P0FAR2_ADDRESS_UPPER_MSBS_MASK (0xFF000000U) -#define SPI_FILTER_P0FAR2_ADDRESS_UPPER_MSBS_SHIFT (24U) -/*! ADDRESS_UPPER_MSBS - Address Upper MSBs - */ -#define SPI_FILTER_P0FAR2_ADDRESS_UPPER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR2_ADDRESS_UPPER_MSBS_SHIFT)) & SPI_FILTER_P0FAR2_ADDRESS_UPPER_MSBS_MASK) -/*! @} */ - -/*! @name P0FAR3 - Port 0 filter address region 3 */ -/*! @{ */ - -#define SPI_FILTER_P0FAR3_ADDRESS_LOWER_LSBS_MASK (0xFFU) -#define SPI_FILTER_P0FAR3_ADDRESS_LOWER_LSBS_SHIFT (0U) -/*! ADDRESS_LOWER_LSBS - Address Lower LSBs - */ -#define SPI_FILTER_P0FAR3_ADDRESS_LOWER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR3_ADDRESS_LOWER_LSBS_SHIFT)) & SPI_FILTER_P0FAR3_ADDRESS_LOWER_LSBS_MASK) - -#define SPI_FILTER_P0FAR3_ADDRESS_LOWER_MSBS_MASK (0xFF00U) -#define SPI_FILTER_P0FAR3_ADDRESS_LOWER_MSBS_SHIFT (8U) -/*! ADDRESS_LOWER_MSBS - Address Lower MSBs - */ -#define SPI_FILTER_P0FAR3_ADDRESS_LOWER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR3_ADDRESS_LOWER_MSBS_SHIFT)) & SPI_FILTER_P0FAR3_ADDRESS_LOWER_MSBS_MASK) - -#define SPI_FILTER_P0FAR3_ADDRESS_UPPER_LSBS_MASK (0xFF0000U) -#define SPI_FILTER_P0FAR3_ADDRESS_UPPER_LSBS_SHIFT (16U) -/*! ADDRESS_UPPER_LSBS - Address Upper LSBs - */ -#define SPI_FILTER_P0FAR3_ADDRESS_UPPER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR3_ADDRESS_UPPER_LSBS_SHIFT)) & SPI_FILTER_P0FAR3_ADDRESS_UPPER_LSBS_MASK) - -#define SPI_FILTER_P0FAR3_ADDRESS_UPPER_MSBS_MASK (0xFF000000U) -#define SPI_FILTER_P0FAR3_ADDRESS_UPPER_MSBS_SHIFT (24U) -/*! ADDRESS_UPPER_MSBS - Address Upper MSBs - */ -#define SPI_FILTER_P0FAR3_ADDRESS_UPPER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR3_ADDRESS_UPPER_MSBS_SHIFT)) & SPI_FILTER_P0FAR3_ADDRESS_UPPER_MSBS_MASK) -/*! @} */ - -/*! @name P1FAR1 - Port 1 filter address region 1 */ -/*! @{ */ - -#define SPI_FILTER_P1FAR1_ADDRESS_LOWER_LSBS_MASK (0xFFU) -#define SPI_FILTER_P1FAR1_ADDRESS_LOWER_LSBS_SHIFT (0U) -/*! ADDRESS_LOWER_LSBS - Address Lower LSBs - */ -#define SPI_FILTER_P1FAR1_ADDRESS_LOWER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR1_ADDRESS_LOWER_LSBS_SHIFT)) & SPI_FILTER_P1FAR1_ADDRESS_LOWER_LSBS_MASK) - -#define SPI_FILTER_P1FAR1_ADDRESS_LOWER_MSBS_MASK (0xFF00U) -#define SPI_FILTER_P1FAR1_ADDRESS_LOWER_MSBS_SHIFT (8U) -/*! ADDRESS_LOWER_MSBS - Address Lower MSBs - */ -#define SPI_FILTER_P1FAR1_ADDRESS_LOWER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR1_ADDRESS_LOWER_MSBS_SHIFT)) & SPI_FILTER_P1FAR1_ADDRESS_LOWER_MSBS_MASK) - -#define SPI_FILTER_P1FAR1_ADDRESS_UPPER_LSBS_MASK (0xFF0000U) -#define SPI_FILTER_P1FAR1_ADDRESS_UPPER_LSBS_SHIFT (16U) -/*! ADDRESS_UPPER_LSBS - Address Upper LSBs - */ -#define SPI_FILTER_P1FAR1_ADDRESS_UPPER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR1_ADDRESS_UPPER_LSBS_SHIFT)) & SPI_FILTER_P1FAR1_ADDRESS_UPPER_LSBS_MASK) - -#define SPI_FILTER_P1FAR1_ADDRESS_UPPER_MSBS_MASK (0xFF000000U) -#define SPI_FILTER_P1FAR1_ADDRESS_UPPER_MSBS_SHIFT (24U) -/*! ADDRESS_UPPER_MSBS - Address Upper MSBs - */ -#define SPI_FILTER_P1FAR1_ADDRESS_UPPER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR1_ADDRESS_UPPER_MSBS_SHIFT)) & SPI_FILTER_P1FAR1_ADDRESS_UPPER_MSBS_MASK) -/*! @} */ - -/*! @name P1FAR2 - Port 1 filter address region 2 */ -/*! @{ */ - -#define SPI_FILTER_P1FAR2_ADDRESS_LOWER_LSBS_MASK (0xFFU) -#define SPI_FILTER_P1FAR2_ADDRESS_LOWER_LSBS_SHIFT (0U) -/*! ADDRESS_LOWER_LSBS - Address Lower LSBs - */ -#define SPI_FILTER_P1FAR2_ADDRESS_LOWER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR2_ADDRESS_LOWER_LSBS_SHIFT)) & SPI_FILTER_P1FAR2_ADDRESS_LOWER_LSBS_MASK) - -#define SPI_FILTER_P1FAR2_ADDRESS_LOWER_MSBS_MASK (0xFF00U) -#define SPI_FILTER_P1FAR2_ADDRESS_LOWER_MSBS_SHIFT (8U) -/*! ADDRESS_LOWER_MSBS - Address Lower MSBs - */ -#define SPI_FILTER_P1FAR2_ADDRESS_LOWER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR2_ADDRESS_LOWER_MSBS_SHIFT)) & SPI_FILTER_P1FAR2_ADDRESS_LOWER_MSBS_MASK) - -#define SPI_FILTER_P1FAR2_ADDRESS_UPPER_LSBS_MASK (0xFF0000U) -#define SPI_FILTER_P1FAR2_ADDRESS_UPPER_LSBS_SHIFT (16U) -/*! ADDRESS_UPPER_LSBS - Address Upper LSBs - */ -#define SPI_FILTER_P1FAR2_ADDRESS_UPPER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR2_ADDRESS_UPPER_LSBS_SHIFT)) & SPI_FILTER_P1FAR2_ADDRESS_UPPER_LSBS_MASK) - -#define SPI_FILTER_P1FAR2_ADDRESS_UPPER_MSBS_MASK (0xFF000000U) -#define SPI_FILTER_P1FAR2_ADDRESS_UPPER_MSBS_SHIFT (24U) -/*! ADDRESS_UPPER_MSBS - Address Upper MSBs - */ -#define SPI_FILTER_P1FAR2_ADDRESS_UPPER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR2_ADDRESS_UPPER_MSBS_SHIFT)) & SPI_FILTER_P1FAR2_ADDRESS_UPPER_MSBS_MASK) -/*! @} */ - -/*! @name P1FAR3 - Port 1 filter address region 3 */ -/*! @{ */ - -#define SPI_FILTER_P1FAR3_ADDRESS_LOWER_LSBS_MASK (0xFFU) -#define SPI_FILTER_P1FAR3_ADDRESS_LOWER_LSBS_SHIFT (0U) -/*! ADDRESS_LOWER_LSBS - Address Lower LSBs - */ -#define SPI_FILTER_P1FAR3_ADDRESS_LOWER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR3_ADDRESS_LOWER_LSBS_SHIFT)) & SPI_FILTER_P1FAR3_ADDRESS_LOWER_LSBS_MASK) - -#define SPI_FILTER_P1FAR3_ADDRESS_LOWER_MSBS_MASK (0xFF00U) -#define SPI_FILTER_P1FAR3_ADDRESS_LOWER_MSBS_SHIFT (8U) -/*! ADDRESS_LOWER_MSBS - Address Lower MSBs - */ -#define SPI_FILTER_P1FAR3_ADDRESS_LOWER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR3_ADDRESS_LOWER_MSBS_SHIFT)) & SPI_FILTER_P1FAR3_ADDRESS_LOWER_MSBS_MASK) - -#define SPI_FILTER_P1FAR3_ADDRESS_UPPER_LSBS_MASK (0xFF0000U) -#define SPI_FILTER_P1FAR3_ADDRESS_UPPER_LSBS_SHIFT (16U) -/*! ADDRESS_UPPER_LSBS - Address Upper LSBs - */ -#define SPI_FILTER_P1FAR3_ADDRESS_UPPER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR3_ADDRESS_UPPER_LSBS_SHIFT)) & SPI_FILTER_P1FAR3_ADDRESS_UPPER_LSBS_MASK) - -#define SPI_FILTER_P1FAR3_ADDRESS_UPPER_MSBS_MASK (0xFF000000U) -#define SPI_FILTER_P1FAR3_ADDRESS_UPPER_MSBS_SHIFT (24U) -/*! ADDRESS_UPPER_MSBS - Address Upper MSBs - */ -#define SPI_FILTER_P1FAR3_ADDRESS_UPPER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR3_ADDRESS_UPPER_MSBS_SHIFT)) & SPI_FILTER_P1FAR3_ADDRESS_UPPER_MSBS_MASK) -/*! @} */ - -/*! @name VER - Version */ -/*! @{ */ - -#define SPI_FILTER_VER_MINOR_REVISION_MASK (0xF000000U) -#define SPI_FILTER_VER_MINOR_REVISION_SHIFT (24U) -/*! MINOR_REVISION - Minor revision - */ -#define SPI_FILTER_VER_MINOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_VER_MINOR_REVISION_SHIFT)) & SPI_FILTER_VER_MINOR_REVISION_MASK) - -#define SPI_FILTER_VER_MAJOR_REVISION_MASK (0xF0000000U) -#define SPI_FILTER_VER_MAJOR_REVISION_SHIFT (28U) -/*! MAJOR_REVISION - Major Revision - */ -#define SPI_FILTER_VER_MAJOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_VER_MAJOR_REVISION_SHIFT)) & SPI_FILTER_VER_MAJOR_REVISION_MASK) -/*! @} */ - -/*! @name POPCODE0 - Programmable OP-Code0 */ -/*! @{ */ - -#define SPI_FILTER_POPCODE0_FILTER_STATE0_MASK (0x1F0000U) -#define SPI_FILTER_POPCODE0_FILTER_STATE0_SHIFT (16U) -/*! FILTER_STATE0 - Programmable Filter state 0 - */ -#define SPI_FILTER_POPCODE0_FILTER_STATE0(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE0_FILTER_STATE0_SHIFT)) & SPI_FILTER_POPCODE0_FILTER_STATE0_MASK) - -#define SPI_FILTER_POPCODE0_FILTER_BIT0_MASK (0x200000U) -#define SPI_FILTER_POPCODE0_FILTER_BIT0_SHIFT (21U) -/*! FILTER_BIT0 - * 0b0..Filter after 7th bit for all Commands Op Codes that need to be filtered. - * 0b1..Filter after 8th bit for all Read/Write Op Codes that are filtered based on the address. - */ -#define SPI_FILTER_POPCODE0_FILTER_BIT0(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE0_FILTER_BIT0_SHIFT)) & SPI_FILTER_POPCODE0_FILTER_BIT0_MASK) - -#define SPI_FILTER_POPCODE0_PRG_OPCODE0_MASK (0xFF000000U) -#define SPI_FILTER_POPCODE0_PRG_OPCODE0_SHIFT (24U) -/*! PRG_OPCODE0 - Programmable OP Code 0 - */ -#define SPI_FILTER_POPCODE0_PRG_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE0_PRG_OPCODE0_SHIFT)) & SPI_FILTER_POPCODE0_PRG_OPCODE0_MASK) -/*! @} */ - -/*! @name POPCODE1 - Programmable OP-Code1 */ -/*! @{ */ - -#define SPI_FILTER_POPCODE1_FILTER_STATE1_MASK (0x1F0000U) -#define SPI_FILTER_POPCODE1_FILTER_STATE1_SHIFT (16U) -/*! FILTER_STATE1 - Programmable Filter state 1 - */ -#define SPI_FILTER_POPCODE1_FILTER_STATE1(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE1_FILTER_STATE1_SHIFT)) & SPI_FILTER_POPCODE1_FILTER_STATE1_MASK) - -#define SPI_FILTER_POPCODE1_FILTER_BIT1_MASK (0x200000U) -#define SPI_FILTER_POPCODE1_FILTER_BIT1_SHIFT (21U) -/*! FILTER_BIT1 - * 0b0..Filter after 7th bit for all Commands Op Codes that need to be filtered. - * 0b1..Filter after 8th bit for all Read/Write Op Codes that are filtered based on the address. - */ -#define SPI_FILTER_POPCODE1_FILTER_BIT1(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE1_FILTER_BIT1_SHIFT)) & SPI_FILTER_POPCODE1_FILTER_BIT1_MASK) - -#define SPI_FILTER_POPCODE1_PRG_OPCODE1_MASK (0xFF000000U) -#define SPI_FILTER_POPCODE1_PRG_OPCODE1_SHIFT (24U) -/*! PRG_OPCODE1 - Programmable OP Code 1 - */ -#define SPI_FILTER_POPCODE1_PRG_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE1_PRG_OPCODE1_SHIFT)) & SPI_FILTER_POPCODE1_PRG_OPCODE1_MASK) -/*! @} */ - -/*! @name POPCODE2 - Programmable OP-Code2 */ -/*! @{ */ - -#define SPI_FILTER_POPCODE2_FILTER_STATE2_MASK (0x1F0000U) -#define SPI_FILTER_POPCODE2_FILTER_STATE2_SHIFT (16U) -/*! FILTER_STATE2 - Programmable Filter state 2 - */ -#define SPI_FILTER_POPCODE2_FILTER_STATE2(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE2_FILTER_STATE2_SHIFT)) & SPI_FILTER_POPCODE2_FILTER_STATE2_MASK) - -#define SPI_FILTER_POPCODE2_FILTER_BIT2_MASK (0x200000U) -#define SPI_FILTER_POPCODE2_FILTER_BIT2_SHIFT (21U) -/*! FILTER_BIT2 - * 0b0..Filter after 7th bit for all Commands Op Codes that need to be filtered. - * 0b1..Filter after 8th bit for all Read/Write Op Codes that are filtered based on the address. - */ -#define SPI_FILTER_POPCODE2_FILTER_BIT2(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE2_FILTER_BIT2_SHIFT)) & SPI_FILTER_POPCODE2_FILTER_BIT2_MASK) - -#define SPI_FILTER_POPCODE2_PRG_OPCODE2_MASK (0xFF000000U) -#define SPI_FILTER_POPCODE2_PRG_OPCODE2_SHIFT (24U) -/*! PRG_OPCODE2 - Programmable OP Code 0 - */ -#define SPI_FILTER_POPCODE2_PRG_OPCODE2(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE2_PRG_OPCODE2_SHIFT)) & SPI_FILTER_POPCODE2_PRG_OPCODE2_MASK) -/*! @} */ - -/*! @name POPCODE3 - Programmable OP-Code3 */ -/*! @{ */ - -#define SPI_FILTER_POPCODE3_FILTER_STATE3_MASK (0x1F0000U) -#define SPI_FILTER_POPCODE3_FILTER_STATE3_SHIFT (16U) -/*! FILTER_STATE3 - Programmable Filter state 3 - */ -#define SPI_FILTER_POPCODE3_FILTER_STATE3(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE3_FILTER_STATE3_SHIFT)) & SPI_FILTER_POPCODE3_FILTER_STATE3_MASK) - -#define SPI_FILTER_POPCODE3_FILTER_BIT3_MASK (0x200000U) -#define SPI_FILTER_POPCODE3_FILTER_BIT3_SHIFT (21U) -/*! FILTER_BIT3 - * 0b0..Filter after 7th bit for all Commands Op Codes that need to be filtered. - * 0b1..Filter after 8th bit for all Read/Write Op Codes that are filtered based on the address. - */ -#define SPI_FILTER_POPCODE3_FILTER_BIT3(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE3_FILTER_BIT3_SHIFT)) & SPI_FILTER_POPCODE3_FILTER_BIT3_MASK) - -#define SPI_FILTER_POPCODE3_PRG_OPCODE3_MASK (0xFF000000U) -#define SPI_FILTER_POPCODE3_PRG_OPCODE3_SHIFT (24U) -/*! PRG_OPCODE3 - Programmable OP Code 3 - */ -#define SPI_FILTER_POPCODE3_PRG_OPCODE3(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE3_PRG_OPCODE3_SHIFT)) & SPI_FILTER_POPCODE3_PRG_OPCODE3_MASK) -/*! @} */ - -/*! @name POPCODE4 - Programmable OP-Code4 */ -/*! @{ */ - -#define SPI_FILTER_POPCODE4_FILTER_STATE4_MASK (0x1F0000U) -#define SPI_FILTER_POPCODE4_FILTER_STATE4_SHIFT (16U) -/*! FILTER_STATE4 - Programmable Filter state 4 - */ -#define SPI_FILTER_POPCODE4_FILTER_STATE4(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE4_FILTER_STATE4_SHIFT)) & SPI_FILTER_POPCODE4_FILTER_STATE4_MASK) - -#define SPI_FILTER_POPCODE4_FILTER_BIT4_MASK (0x200000U) -#define SPI_FILTER_POPCODE4_FILTER_BIT4_SHIFT (21U) -/*! FILTER_BIT4 - * 0b0..Filter after 7th bit for all Commands Op Codes that need to be filtered. - * 0b1..Filter after 8th bit for all Read/Write Op Codes that are filtered based on the address. - */ -#define SPI_FILTER_POPCODE4_FILTER_BIT4(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE4_FILTER_BIT4_SHIFT)) & SPI_FILTER_POPCODE4_FILTER_BIT4_MASK) - -#define SPI_FILTER_POPCODE4_PRG_OPCODE4_MASK (0xFF000000U) -#define SPI_FILTER_POPCODE4_PRG_OPCODE4_SHIFT (24U) -/*! PRG_OPCODE4 - Programmable OP Code 4 - */ -#define SPI_FILTER_POPCODE4_PRG_OPCODE4(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE4_PRG_OPCODE4_SHIFT)) & SPI_FILTER_POPCODE4_PRG_OPCODE4_MASK) -/*! @} */ - -/*! @name P0BOC - P0 Blocked Op Code */ -/*! @{ */ - -#define SPI_FILTER_P0BOC_P0BOC_MASK (0xFF000000U) -#define SPI_FILTER_P0BOC_P0BOC_SHIFT (24U) -/*! P0BOC - Port 0 Blocked Op Code - */ -#define SPI_FILTER_P0BOC_P0BOC(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0BOC_P0BOC_SHIFT)) & SPI_FILTER_P0BOC_P0BOC_MASK) -/*! @} */ - -/*! @name P1BOC - P1 Blocked Op Code */ -/*! @{ */ - -#define SPI_FILTER_P1BOC_P1BOC_MASK (0xFF000000U) -#define SPI_FILTER_P1BOC_P1BOC_SHIFT (24U) -/*! P1BOC - Port 1 Blocked Op Code - */ -#define SPI_FILTER_P1BOC_P1BOC(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1BOC_P1BOC_SHIFT)) & SPI_FILTER_P1BOC_P1BOC_MASK) -/*! @} */ - -/*! @name P0MAM - Port 0 Max Address Mask */ -/*! @{ */ - -#define SPI_FILTER_P0MAM_P0MAML_MASK (0xFF0000U) -#define SPI_FILTER_P0MAM_P0MAML_SHIFT (16U) -/*! P0MAML - Port 0 Max Address Mask LSB - */ -#define SPI_FILTER_P0MAM_P0MAML(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0MAM_P0MAML_SHIFT)) & SPI_FILTER_P0MAM_P0MAML_MASK) - -#define SPI_FILTER_P0MAM_P0MAMM_MASK (0xFF000000U) -#define SPI_FILTER_P0MAM_P0MAMM_SHIFT (24U) -/*! P0MAMM - Port 0 Max Address Mask MSB - */ -#define SPI_FILTER_P0MAM_P0MAMM(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0MAM_P0MAMM_SHIFT)) & SPI_FILTER_P0MAM_P0MAMM_MASK) -/*! @} */ - -/*! @name P1MAM - Port 1 Max Address Mask */ -/*! @{ */ - -#define SPI_FILTER_P1MAM_P1MAML_MASK (0xFF0000U) -#define SPI_FILTER_P1MAM_P1MAML_SHIFT (16U) -/*! P1MAML - Port 1 Max Address Mask LSB - */ -#define SPI_FILTER_P1MAM_P1MAML(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1MAM_P1MAML_SHIFT)) & SPI_FILTER_P1MAM_P1MAML_MASK) - -#define SPI_FILTER_P1MAM_P1MAMM_MASK (0xFF000000U) -#define SPI_FILTER_P1MAM_P1MAMM_SHIFT (24U) -/*! P1MAMM - Port 1 Max Address Mask MSB - */ -#define SPI_FILTER_P1MAM_P1MAMM(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1MAM_P1MAMM_SHIFT)) & SPI_FILTER_P1MAM_P1MAMM_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SPI_FILTER_Register_Masks */ - - -/* SPI_FILTER - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SPI_FILTER base address */ - #define SPI_FILTER_BASE (0x50024000u) - /** Peripheral SPI_FILTER base address */ - #define SPI_FILTER_BASE_NS (0x40024000u) - /** Peripheral SPI_FILTER base pointer */ - #define SPI_FILTER ((SPI_FILTER_Type *)SPI_FILTER_BASE) - /** Peripheral SPI_FILTER base pointer */ - #define SPI_FILTER_NS ((SPI_FILTER_Type *)SPI_FILTER_BASE_NS) - /** Array initializer of SPI_FILTER peripheral base addresses */ - #define SPI_FILTER_BASE_ADDRS { SPI_FILTER_BASE } - /** Array initializer of SPI_FILTER peripheral base pointers */ - #define SPI_FILTER_BASE_PTRS { SPI_FILTER } - /** Array initializer of SPI_FILTER peripheral base addresses */ - #define SPI_FILTER_BASE_ADDRS_NS { SPI_FILTER_BASE_NS } - /** Array initializer of SPI_FILTER peripheral base pointers */ - #define SPI_FILTER_BASE_PTRS_NS { SPI_FILTER_NS } -#else - /** Peripheral SPI_FILTER base address */ - #define SPI_FILTER_BASE (0x40024000u) - /** Peripheral SPI_FILTER base pointer */ - #define SPI_FILTER ((SPI_FILTER_Type *)SPI_FILTER_BASE) - /** Array initializer of SPI_FILTER peripheral base addresses */ - #define SPI_FILTER_BASE_ADDRS { SPI_FILTER_BASE } - /** Array initializer of SPI_FILTER peripheral base pointers */ - #define SPI_FILTER_BASE_PTRS { SPI_FILTER } -#endif - -/*! - * @} - */ /* end of group SPI_FILTER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SYSCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer - * @{ - */ - -/** SYSCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t MEMORYREMAP; /**< Memory Remap Control, offset: 0x0 */ - uint8_t RESERVED_0[12]; - __IO uint32_t AHBMATPRIO; /**< AHB Matrix priority control, offset: 0x10 */ - __IO uint32_t AHBMATPRIO1; /**< AHB Matrix priority control, offset: 0x14 */ - uint8_t RESERVED_1[32]; - __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */ - __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */ - uint8_t RESERVED_2[8]; - __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ - uint8_t RESERVED_3[180]; - __IO uint32_t PRESETCTRL0; /**< Peripheral reset control 0, offset: 0x100 */ - __IO uint32_t PRESETCTRL1; /**< Peripheral reset control 1, offset: 0x104 */ - __IO uint32_t PRESETCTRL2; /**< Peripheral reset control 2, offset: 0x108 */ - __IO uint32_t PRESETCTRL3; /**< Peripheral reset control 3, offset: 0x10C */ - uint8_t RESERVED_4[16]; - __O uint32_t PRESETCTRLSET[4]; /**< Peripheral reset control set n, array offset: 0x120, array step: 0x4 */ - uint8_t RESERVED_5[16]; - __O uint32_t PRESETCTRLCLR[4]; /**< Peripheral reset control clear n, array offset: 0x140, array step: 0x4 */ - uint8_t RESERVED_6[16]; - __O uint32_t SWR_RESET; /**< Software Reset, offset: 0x160 */ - uint8_t RESERVED_7[156]; - __IO uint32_t AHBCLKCTRL0; /**< AHB Clock control 0, offset: 0x200 */ - __IO uint32_t AHBCLKCTRL1; /**< AHB Clock control 1, offset: 0x204 */ - __IO uint32_t AHBCLKCTRL2; /**< AHB Clock control 2, offset: 0x208 */ - __IO uint32_t AHBCLKCTRL3; /**< AHB Clock Control 3, offset: 0x20C */ - uint8_t RESERVED_8[16]; - __IO uint32_t AHBCLKCTRLSET[4]; /**< AHB Clock Control Set, array offset: 0x220, array step: 0x4 */ - uint8_t RESERVED_9[16]; - __IO uint32_t AHBCLKCTRLCLR[4]; /**< AHB Clock Control Clear, array offset: 0x240, array step: 0x4 */ - uint8_t RESERVED_10[16]; - __IO uint32_t SYSTICKCLKSEL0; /**< System Tick Timer for CPU0 source select, offset: 0x260 */ - uint8_t RESERVED_11[4]; - __IO uint32_t TRACECLKSEL; /**< Trace clock source select, offset: 0x268 */ - __IO uint32_t CTIMERCLKSEL[5]; /**< CTimer 0 clock source select..CTimer 4 clock source select, array offset: 0x26C, array step: 0x4 */ - __IO uint32_t MAINCLKSELA; /**< Main clock source select A, offset: 0x280 */ - __IO uint32_t MAINCLKSELB; /**< Main clock source select B, offset: 0x284 */ - __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0x288 */ - uint8_t RESERVED_12[4]; - __IO uint32_t PLL0CLKSEL; /**< PLL0 clock source select, offset: 0x290 */ - __IO uint32_t PLL1CLKSEL; /**< PLL1 clock source select, offset: 0x294 */ - uint8_t RESERVED_13[8]; - __IO uint32_t CANCLKSEL; /**< CAN clock source select, offset: 0x2A0 */ - __IO uint32_t ADC0CLKSEL; /**< ADC0 clock source select, offset: 0x2A4 */ - __IO uint32_t USB0CLKSEL; /**< FS USB clock source select, offset: 0x2A8 */ - uint8_t RESERVED_14[4]; - __IO uint32_t FCCLKSEL[8]; /**< Flexcomm 0 clock source select for Fractional Rate Divider..Flexcomm 7 clock source select for Fractional Rate Divider, array offset: 0x2B0, array step: 0x4 */ - __IO uint32_t HSSPICLKSEL; /**< HS SPI clock source select, offset: 0x2D0 */ - uint8_t RESERVED_15[12]; - __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ - uint8_t RESERVED_16[12]; - __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ - uint8_t RESERVED_17[12]; - __IO uint32_t SYSTICKCLKDIV[1]; /**< System Tick Timer divider for CPU0, array offset: 0x300, array step: 0x4 */ - uint8_t RESERVED_18[4]; - __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */ - __IO uint32_t CANCLKDIV; /**< CAN clock divider, offset: 0x30C */ - uint8_t RESERVED_19[16]; - __IO uint32_t FRGCTRL[8]; /**< Fractional rate divider for flexcomm 0..Fractional rate divider for flexcomm 7, array offset: 0x320, array step: 0x4 */ - uint8_t RESERVED_20[64]; - __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */ - __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ - __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */ - __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */ - uint8_t RESERVED_21[4]; - __IO uint32_t ADC0CLKDIV; /**< ADC0 clock divider, offset: 0x394 */ - __IO uint32_t USB0CLKDIV; /**< USB0-FS Clock divider, offset: 0x398 */ - uint8_t RESERVED_22[16]; - __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ - uint8_t RESERVED_23[4]; - __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ - uint8_t RESERVED_24[12]; - __IO uint32_t PLLCLKDIV; /**< PLL clock divider, offset: 0x3C4 */ - uint8_t RESERVED_25[8]; - __IO uint32_t CTIMERCLKDIV[5]; /**< CTimer 0 clock divider..CTimer 4 clock divider, array offset: 0x3D0, array step: 0x4 */ - uint8_t RESERVED_26[24]; - __IO uint32_t CLKUNLOCK; /**< Clock configuration unlock, offset: 0x3FC */ - __IO uint32_t FMCCR; /**< FMC configuration, offset: 0x400 */ - __IO uint32_t ROMCR; /**< ROM wait state, offset: 0x404 */ - uint8_t RESERVED_27[4]; - __IO uint32_t USB0NEEDCLKCTRL; /**< USB0-FS need clock control, offset: 0x40C */ - __I uint32_t USB0NEEDCLKSTAT; /**< USB0-FS need clock status, offset: 0x410 */ - __IO uint32_t EZHINT; /**< EZH interrupt hijack, offset: 0x414 */ - uint8_t RESERVED_28[4]; - __O uint32_t FMCFLUSH; /**< FMC flush control, offset: 0x41C */ - __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */ - uint8_t RESERVED_29[64]; - __IO uint32_t ADC1CLKSEL; /**< ADC1 clock source select, offset: 0x464 */ - __IO uint32_t ADC1CLKDIV; /**< ADC1 clock divider, offset: 0x468 */ - uint8_t RESERVED_30[4]; - __IO uint32_t RAM_INTERLEAVE; /**< Control RAM interleave integration, offset: 0x470 */ - uint8_t RESERVED_31[28]; - struct { /* offset: 0x490, array step: 0x8 */ - __IO uint32_t CLKSEL; /**< DAC0 functional clock selection..DAC2 functional clock selection, array offset: 0x490, array step: 0x8 */ - __IO uint32_t CLKDIV; /**< DAC0 functional clock divider..DAC2 functional clock divider, array offset: 0x494, array step: 0x8 */ - } DAC[3]; - __IO uint32_t FLEXSPICLKSEL; /**< FLEXSPI clock selection, offset: 0x4A8 */ - __IO uint32_t FLEXSPICLKDIV; /**< FLEXSPI clock divider, offset: 0x4AC */ - __IO uint32_t CDPA_ENABLE; /**< Enable protection, offset: 0x4B0 */ - __IO uint32_t CDPA_ENABLE_DP; /**< Enable protection duplicate, offset: 0x4B4 */ - __IO uint32_t CDPA_CONFIG; /**< CDPA base address, offset: 0x4B8 */ - uint8_t RESERVED_32[20]; - __IO uint32_t FLASH_HIDING_LOCKOUT_ADDR; /**< Flash hiding lockout address, offset: 0x4D0 */ - __IO uint32_t FLASH_HIDING_BASE_ADDR; /**< Flash hiding base address, offset: 0x4D4 */ - __IO uint32_t FLASH_HIDING_BASE_DP_ADDR; /**< Flash hiding base DP address, offset: 0x4D8 */ - __IO uint32_t FLASH_HIDING_SIZE_ADDR; /**< Hiding size address, offset: 0x4DC */ - __IO uint32_t FLASH_HIDING_SIZE_DP_ADDR; /**< Hiding size DP address, offset: 0x4E0 */ - uint8_t RESERVED_33[72]; - __IO uint32_t PLLCLKDIVSEL; /**< PLL clock divider clock selection, offset: 0x52C */ - __IO uint32_t I3CFCLKSEL; /**< I3C functional clock selection, offset: 0x530 */ - __IO uint32_t I3CFCLKSTCSEL; /**< I3C FCLK_STC clock selection, offset: 0x534 */ - __IO uint32_t I3CFCLKSTCDIV; /**< I3C FCLK_STC clock divider, offset: 0x538 */ - __IO uint32_t I3CFCLKSDIV; /**< I3C FCLKS clock divider, offset: 0x53C */ - __IO uint32_t I3CFCLKDIV; /**< I3C FCLK divider, offset: 0x540 */ - __IO uint32_t I3CFCLKSSEL; /**< I3C FCLK_S selection, offset: 0x544 */ - __IO uint32_t DMICFCLKSEL; /**< DMIC clock selection, offset: 0x548 */ - __IO uint32_t DMICFCLKDIV; /**< DMIC clock division, offset: 0x54C */ - uint8_t RESERVED_34[16]; - __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */ - __I uint32_t PLL1STAT; /**< PLL1 550m status, offset: 0x564 */ - __IO uint32_t PLL1NDEC; /**< PLL1 550m N divider, offset: 0x568 */ - __IO uint32_t PLL1MDEC; /**< PLL1 550m M divider, offset: 0x56C */ - __IO uint32_t PLL1PDEC; /**< PLL1 550m P divider, offset: 0x570 */ - uint8_t RESERVED_35[12]; - __IO uint32_t PLL0CTRL; /**< PLL0 550m control, offset: 0x580 */ - __I uint32_t PLL0STAT; /**< PLL0 550m status, offset: 0x584 */ - __IO uint32_t PLL0NDEC; /**< PLL0 550m N divider, offset: 0x588 */ - __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */ - __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum control 0, offset: 0x590 */ - __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum control 1, offset: 0x594 */ - uint8_t RESERVED_36[56]; - __IO uint32_t DAC_ISO_CTRL; /**< DAC Isolation Control, offset: 0x5D0 */ - uint8_t RESERVED_37[172]; - __IO uint32_t STARTER[4]; /**< Start logic wake-up enable, array offset: 0x680, array step: 0x4 */ - uint8_t RESERVED_38[16]; - __IO uint32_t STARTERSET[4]; /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */ - uint8_t RESERVED_39[16]; - __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTER, array offset: 0x6C0, array step: 0x4 */ - uint8_t RESERVED_40[60]; - __IO uint32_t FUNCRETENTIONCTRL; /**< Functional retention control, offset: 0x704 */ - uint8_t RESERVED_41[120]; - __IO uint32_t HARDWARESLEEP; /**< Hardware Sleep control, offset: 0x780 */ - uint8_t RESERVED_42[136]; - __I uint32_t CPUSTAT; /**< CPU Status, offset: 0x80C */ - uint8_t RESERVED_43[20]; - __IO uint32_t LPCAC_CTRL; /**< LPCAC control, offset: 0x824 */ - uint8_t RESERVED_44[4]; - __IO uint32_t FC32KCLKSEL; /**< Flexcomm 32K clock select, offset: 0x82C */ - __IO uint32_t FRGCLKSEL[8]; /**< FRG Clock Source Select, array offset: 0x830, array step: 0x4 */ - __IO uint32_t FLEXCOMMCLKDIV[8]; /**< Flexcomm clock divider, array offset: 0x850, array step: 0x4 */ - uint8_t RESERVED_45[280]; - __IO uint32_t CSS_TEMPORAL_STATE; /**< CSS temporal state, offset: 0x988 */ - __IO uint32_t CSS_KDF_MASK; /**< Key derivation function mask, offset: 0x98C */ - __IO uint32_t CSS_FEATURE0; /**< CSS command feature, offset: 0x990 */ - __IO uint32_t CSS_FEATURE1; /**< CSS command feature, offset: 0x994 */ - __IO uint32_t CSS_FEATURE0_DP; /**< CSS command feature - duplicate version, offset: 0x998 */ - __IO uint32_t CSS_FEATURE1_DP; /**< CSS command feature - duplicate version, offset: 0x99C */ - uint8_t RESERVED_46[4]; - __IO uint32_t CSS_BOOT_RETRY_CNT; /**< CSS boot retry counter, offset: 0x9A4 */ - uint8_t RESERVED_47[8]; - __IO uint32_t CSS_CLK_CTRL; /**< CSS clock control, offset: 0x9B0 */ - __O uint32_t CSS_CLK_CTRL_SET; /**< CSS clock control set, offset: 0x9B4 */ - __O uint32_t CSS_CLK_CTRL_CLR; /**< CSS clock control clear, offset: 0x9B8 */ - __IO uint32_t CSS_CLK_SEL; /**< CSS clock select, offset: 0x9BC */ - uint8_t RESERVED_48[16]; - __I uint32_t CSS_AS_CFG0; /**< CSS AS configuration, offset: 0x9D0 */ - __I uint32_t CSS_AS_CFG1; /**< CSS AS configuration1, offset: 0x9D4 */ - __I uint32_t CSS_AS_CFG2; /**< CSS AS configuration2, offset: 0x9D8 */ - uint8_t RESERVED_49[4]; - __I uint32_t CSS_AS_ST0; /**< CSS AS state register, offset: 0x9E0 */ - __I uint32_t CSS_AS_ST1; /**< CSS AS state1, offset: 0x9E4 */ - __I uint32_t CSS_AS_ST2; /**< CSS AS state2, offset: 0x9E8 */ - uint8_t RESERVED_50[4]; - __I uint32_t CSS_AS_FLAG0; /**< CSS AS flag0, offset: 0x9F0 */ - uint8_t RESERVED_51[36]; - __IO uint32_t CLOCK_CTRL; /**< Clock Control, offset: 0xA18 */ - uint8_t RESERVED_52[244]; - __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */ - __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */ - uint8_t RESERVED_53[748]; - __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */ - __IO uint32_t GPIOPSYNC; /**< GPIO Synchronization, offset: 0xE08 */ - uint8_t RESERVED_54[24]; - __IO uint32_t AUTOCLKGATEOVERRIDE1; /**< Control automatic clock gating, offset: 0xE24 */ - uint8_t RESERVED_55[8]; - __IO uint32_t ENABLE_MEM_PARITY_ECC_CHECK; /**< Memory parity ECC enable, offset: 0xE30 */ - __I uint32_t MEM_PARITY_ECC_ERROR_FLAG; /**< Memory parity ECC error flag, offset: 0xE34 */ - __IO uint32_t PWM0SUBCTL; /**< PWM0 submodule control, offset: 0xE38 */ - __IO uint32_t PWM1SUBCTL; /**< PWM1 submodule control, offset: 0xE3C */ - __IO uint32_t CTIMERGLOBALSTARTEN; /**< CTIMER global start enable, offset: 0xE40 */ - uint8_t RESERVED_56[348]; - __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security, offset: 0xFA0 */ - __IO uint32_t DEBUG_FEATURES; /**< Cortex debug features control, offset: 0xFA4 */ - __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex debug features control (duplicate), offset: 0xFA8 */ - uint8_t RESERVED_57[8]; - __IO uint32_t SWD_ACCESS_CPU[1]; /**< CPU0 Software Debug Access, array offset: 0xFB4, array step: 0x4 */ - uint8_t RESERVED_58[8]; - __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug authentication BEACON, offset: 0xFC0 */ - __IO uint32_t SWD_ACCESS_DSP; /**< DSP Software Debug Access, offset: 0xFC4 */ - uint8_t RESERVED_59[44]; - uint32_t DEVICE_TYPE; /**< Device type, offset: 0xFF4 */ - __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ - __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */ -} SYSCON_Type; - -/* ---------------------------------------------------------------------------- - -- SYSCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Register_Masks SYSCON Register Masks - * @{ - */ - -/*! @name MEMORYREMAP - Memory Remap Control */ -/*! @{ */ - -#define SYSCON_MEMORYREMAP_MAP_MASK (0x3U) -#define SYSCON_MEMORYREMAP_MAP_SHIFT (0U) -/*! MAP - Select the location of the vector table: - * 0b00..Vector Table in ROM. - * 0b01..Vector Table in RAM. - * 0b1x..Vector Table in Flash. - */ -#define SYSCON_MEMORYREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK) -/*! @} */ - -/*! @name AHBMATPRIO - AHB Matrix priority control */ -/*! @{ */ - -#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK (0x3U) -#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT (0U) -/*! PRI_CPU0_CBUS - CPU0 C-AHB bus. - */ -#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK (0xCU) -#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT (2U) -/*! PRI_CPU0_SBUS - CPU0 S-AHB bus. - */ -#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_USB_FSD_MASK (0x300U) -#define SYSCON_AHBMATPRIO_PRI_USB_FSD_SHIFT (8U) -/*! PRI_USB_FSD - USB0-FS Device.(USB0) - */ -#define SYSCON_AHBMATPRIO_PRI_USB_FSD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FSD_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FSD_MASK) - -#define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0xC00U) -#define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (10U) -/*! PRI_SDMA0 - DMA0 controller priority. - */ -#define SYSCON_AHBMATPRIO_PRI_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK) - -#define SYSCON_AHBMATPRIO_PRI_EZH_B_D_MASK (0x3000U) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_D_SHIFT (12U) -/*! PRI_EZH_B_D - EZH B data bus. - */ -#define SYSCON_AHBMATPRIO_PRI_EZH_B_D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_EZH_B_D_SHIFT)) & SYSCON_AHBMATPRIO_PRI_EZH_B_D_MASK) - -#define SYSCON_AHBMATPRIO_PRI_EZH_B_I_MASK (0xC000U) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_I_SHIFT (14U) -/*! PRI_EZH_B_I - EZH B instruction bus. - */ -#define SYSCON_AHBMATPRIO_PRI_EZH_B_I(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_EZH_B_I_SHIFT)) & SYSCON_AHBMATPRIO_PRI_EZH_B_I_MASK) - -#define SYSCON_AHBMATPRIO_PRI_PQ_MASK (0xC0000U) -#define SYSCON_AHBMATPRIO_PRI_PQ_SHIFT (18U) -/*! PRI_PQ - PQ (HW Accelerator). - */ -#define SYSCON_AHBMATPRIO_PRI_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PQ_MASK) - -#define SYSCON_AHBMATPRIO_PRI_CSSV2_MASK (0x300000U) -#define SYSCON_AHBMATPRIO_PRI_CSSV2_SHIFT (20U) -/*! PRI_CSSV2 - CSSV2 - */ -#define SYSCON_AHBMATPRIO_PRI_CSSV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CSSV2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CSSV2_MASK) - -#define SYSCON_AHBMATPRIO_PRI_USB_FS_MASK (0xC00000U) -#define SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT (22U) -/*! PRI_USB_FS - USB-FS host - */ -#define SYSCON_AHBMATPRIO_PRI_USB_FS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0x3000000U) -#define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (24U) -/*! PRI_SDMA1 - DMA1 controller priority. - */ -#define SYSCON_AHBMATPRIO_PRI_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK) - -#define SYSCON_AHBMATPRIO_PRI_MCAN_MASK (0xC000000U) -#define SYSCON_AHBMATPRIO_PRI_MCAN_SHIFT (26U) -/*! PRI_MCAN - MCAN - */ -#define SYSCON_AHBMATPRIO_PRI_MCAN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN_MASK) - -#define SYSCON_AHBMATPRIO_PKC_MASK (0xC0000000U) -#define SYSCON_AHBMATPRIO_PKC_SHIFT (30U) -/*! PKC - PKC - */ -#define SYSCON_AHBMATPRIO_PKC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PKC_SHIFT)) & SYSCON_AHBMATPRIO_PKC_MASK) -/*! @} */ - -/*! @name AHBMATPRIO1 - AHB Matrix priority control */ -/*! @{ */ - -#define SYSCON_AHBMATPRIO1_DSP_D_MASK (0xCU) -#define SYSCON_AHBMATPRIO1_DSP_D_SHIFT (2U) -/*! DSP_D - DSP D bus - */ -#define SYSCON_AHBMATPRIO1_DSP_D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO1_DSP_D_SHIFT)) & SYSCON_AHBMATPRIO1_DSP_D_MASK) - -#define SYSCON_AHBMATPRIO1_DSP_I_MASK (0x30U) -#define SYSCON_AHBMATPRIO1_DSP_I_SHIFT (4U) -/*! DSP_I - DSP I bus - */ -#define SYSCON_AHBMATPRIO1_DSP_I(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO1_DSP_I_SHIFT)) & SYSCON_AHBMATPRIO1_DSP_I_MASK) -/*! @} */ - -/*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */ -/*! @{ */ - -#define SYSCON_CPU0STCKCAL_TENMS_MASK (0xFFFFFFU) -#define SYSCON_CPU0STCKCAL_TENMS_SHIFT (0U) -/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value - * reads as zero, the calibration value is not known. - */ -#define SYSCON_CPU0STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK) - -#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) -/*! SKEW - Indicates whether the TENMS value is exact: - * 0b0..TENMS value is exact - * 0b1..TENMS value is inexact, or not given - */ -#define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) - -#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) -/*! NOREF - Indicates whether the device provides a reference clock to the processor - * 0b0..Reference clock provided - * 0b1..No reference clock provided - */ -#define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */ -/*! @{ */ - -#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) -#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) -/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the - * value reads as zero, the calibration value is not known. - */ -#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) - -#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) -/*! SKEW - Indicates whether the TENMS value is exact: - * 0b0..TENMS value is exact - * 0b1..TENMS value is inexact, or not given - */ -#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) - -#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) -/*! NOREF - Indicates whether the device provides a reference clock to the processor: - * 0b0..Reference clock provided - * 0b1..No reference clock provided - */ -#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name NMISRC - NMI Source Select */ -/*! @{ */ - -#define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU) -#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) -/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0. - */ -#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) - -#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) -#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) -/*! NMIENCPU0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. - */ -#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) -/*! @} */ - -/*! @name PRESETCTRL0 - Peripheral reset control 0 */ -/*! @{ */ - -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U) -/*! SRAM_CTRL1_RST - SRAM Controller 1 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK) - -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U) -/*! SRAM_CTRL2_RST - SRAM Controller 2 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK) - -#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK (0x20U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT (5U) -/*! SRAM_CTRL3_RST - SRAM Controller 3 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK) - -#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK (0x40U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT (6U) -/*! SRAM_CTRL4_RST - SRAM Controller 4 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK) - -#define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U) -/*! FLASH_RST - Flash controller reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK) - -#define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U) -/*! FMC_RST - FMC controller reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK) - -#define SYSCON_PRESETCTRL0_FLEXSPI_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL0_FLEXSPI_RST_SHIFT (10U) -/*! FLEXSPI_RST - FLEXSPI reset control - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_FLEXSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLEXSPI_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLEXSPI_RST_MASK) - -#define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U) -/*! IOCON_RST - I/O controller reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK) - -#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U) -/*! GPIO0_RST - GPIO0 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) - -#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U) -/*! GPIO1_RST - GPIO1 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) - -#define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (16U) -/*! GPIO2_RST - GPIO2 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK) - -#define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (17U) -/*! GPIO3_RST - GPIO3 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK) - -#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U) -/*! PINT_RST - Pin interrupt (PINT) reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) - -#define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U) -/*! GINT_RST - Group interrupt (GINT) reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK) - -#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U) -#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U) -/*! DMA0_RST - DMA0 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) - -#define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U) -#define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U) -/*! CRCGEN_RST - CRCGEN reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_CRCGEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK) - -#define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U) -/*! WWDT_RST - Watchdog Timer reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK) - -#define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U) -#define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U) -/*! RTC_RST - Real Time Clock (RTC) reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK) - -#define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U) -#define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U) -/*! MAILBOX_RST - Inter CPU communication Mailbox reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK) - -#define SYSCON_PRESETCTRL0_ADC0_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL0_ADC0_RST_SHIFT (27U) -/*! ADC0_RST - ADC0 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC0_RST_MASK) - -#define SYSCON_PRESETCTRL0_ADC1_RST_MASK (0x10000000U) -#define SYSCON_PRESETCTRL0_ADC1_RST_SHIFT (28U) -/*! ADC1_RST - ADC1 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_ADC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC1_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC1_RST_MASK) - -#define SYSCON_PRESETCTRL0_DAC0_RST_MASK (0x20000000U) -#define SYSCON_PRESETCTRL0_DAC0_RST_SHIFT (29U) -/*! DAC0_RST - DAC0 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL0_DAC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DAC0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DAC0_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRL1 - Peripheral reset control 1 */ -/*! @{ */ - -#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) -#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) -/*! MRT_RST - MRT reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) - -#define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT (1U) -/*! OSTIMER_RST - OS Event Timer reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL1_OSTIMER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK) - -#define SYSCON_PRESETCTRL1_SCT_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL1_SCT_RST_SHIFT (2U) -/*! SCT_RST - SCT reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL1_SCT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT_RST_MASK) - -#define SYSCON_PRESETCTRL1_CAN_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL1_CAN_RST_SHIFT (7U) -/*! CAN_RST - CAN reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL1_CAN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_CAN_RST_SHIFT)) & SYSCON_PRESETCTRL1_CAN_RST_MASK) - -#define SYSCON_PRESETCTRL1_UTICK_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT (10U) -/*! UTICK_RST - UTICK reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL1_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) -/*! FC0_RST - FC0 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) -#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) -/*! FC1_RST - FC1 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) -/*! FC2_RST - FC2 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) -/*! FC3_RST - FC3 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) -/*! FC4_RST - FC4 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) -/*! FC5_RST - FC5 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) -/*! FC6_RST - FC6 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) -/*! FC7_RST - FC7 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) - -#define SYSCON_PRESETCTRL1_DMIC_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL1_DMIC_RST_SHIFT (19U) -/*! DMIC_RST - DMIC reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL1_DMIC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_DMIC_RST_SHIFT)) & SYSCON_PRESETCTRL1_DMIC_RST_MASK) - -#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) -/*! TIMER2_RST - Timer 2 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) - -#define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK (0x2000000U) -#define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT (25U) -/*! USB0_DEV_RST - USB0-FS DEV reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL1_USB0_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK) - -#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) -#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) -/*! TIMER0_RST - Timer 0 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) - -#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) -/*! TIMER1_RST - Timer 1 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) - -#define SYSCON_PRESETCTRL1_EZHA_RST_MASK (0x40000000U) -#define SYSCON_PRESETCTRL1_EZHA_RST_SHIFT (30U) -/*! EZHA_RST - EZH a reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL1_EZHA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EZHA_RST_SHIFT)) & SYSCON_PRESETCTRL1_EZHA_RST_MASK) - -#define SYSCON_PRESETCTRL1_EZHB_RST_MASK (0x80000000U) -#define SYSCON_PRESETCTRL1_EZHB_RST_SHIFT (31U) -/*! EZHB_RST - EZH b reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL1_EZHB_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EZHB_RST_SHIFT)) & SYSCON_PRESETCTRL1_EZHB_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRL2 - Peripheral reset control 2 */ -/*! @{ */ - -#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) -/*! DMA1_RST - DMA1 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) - -#define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U) -/*! COMP_RST - Analog comparator reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL2_COMP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK) - -#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) -/*! FREQME_RST - Frequency meter reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) - -#define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U) -/*! RNG_RST - RNG reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL2_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK) - -#define SYSCON_PRESETCTRL2_SYSCTL_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT (15U) -/*! SYSCTL_RST - SYSCTL Block reset. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL2_SYSCTL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT)) & SYSCON_PRESETCTRL2_SYSCTL_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT (16U) -/*! USB0_HOSTM_RST - USB0-FS Host Master reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT (17U) -/*! USB0_HOSTS_RST - USB0-FS Host Slave reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK) - -#define SYSCON_PRESETCTRL2_CSS_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL2_CSS_RST_SHIFT (18U) -/*! CSS_RST - CSS reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL2_CSS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CSS_RST_SHIFT)) & SYSCON_PRESETCTRL2_CSS_RST_MASK) - -#define SYSCON_PRESETCTRL2_PQ_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL2_PQ_RST_SHIFT (19U) -/*! PQ_RST - Power Quad reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL2_PQ_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK) - -#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) -#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) -/*! TIMER3_RST - Timer 3 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) - -#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) -/*! TIMER4_RST - Timer 4 reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) - -#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) -#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) -/*! PUF_RST - PUF reset control reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) - -#define SYSCON_PRESETCTRL2_PKC_RST_MASK (0x1000000U) -#define SYSCON_PRESETCTRL2_PKC_RST_SHIFT (24U) -/*! PKC_RST - PKC reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset.g - */ -#define SYSCON_PRESETCTRL2_PKC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PKC_RST_SHIFT)) & SYSCON_PRESETCTRL2_PKC_RST_MASK) - -#define SYSCON_PRESETCTRL2_ANACTRL_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL2_ANACTRL_RST_SHIFT (27U) -/*! ANACTRL_RST - Analog control reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL2_ANACTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANACTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANACTRL_RST_MASK) - -#define SYSCON_PRESETCTRL2_HS_SPI_RST_MASK (0x10000000U) -#define SYSCON_PRESETCTRL2_HS_SPI_RST_SHIFT (28U) -/*! HS_SPI_RST - HS SPI reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL2_HS_SPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_SPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_SPI_RST_MASK) - -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U) -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U) -/*! GPIO_SEC_RST - GPIO secure reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK) - -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U) -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U) -/*! GPIO_SEC_INT_RST - GPIO secure int reset control. - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRL3 - Peripheral reset control 3 */ -/*! @{ */ - -#define SYSCON_PRESETCTRL3_I3C0_RST_MASK (0x1U) -#define SYSCON_PRESETCTRL3_I3C0_RST_SHIFT (0U) -/*! I3C0_RST - I3C reset control - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL3_I3C0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_I3C0_RST_SHIFT)) & SYSCON_PRESETCTRL3_I3C0_RST_MASK) - -#define SYSCON_PRESETCTRL3_ENC0_RST_MASK (0x8U) -#define SYSCON_PRESETCTRL3_ENC0_RST_SHIFT (3U) -/*! ENC0_RST - ENC0 reset control - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL3_ENC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_ENC0_RST_SHIFT)) & SYSCON_PRESETCTRL3_ENC0_RST_MASK) - -#define SYSCON_PRESETCTRL3_ENC1_RST_MASK (0x10U) -#define SYSCON_PRESETCTRL3_ENC1_RST_SHIFT (4U) -/*! ENC1_RST - ENC1 reset control - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL3_ENC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_ENC1_RST_SHIFT)) & SYSCON_PRESETCTRL3_ENC1_RST_MASK) - -#define SYSCON_PRESETCTRL3_PWM0_RST_MASK (0x20U) -#define SYSCON_PRESETCTRL3_PWM0_RST_SHIFT (5U) -/*! PWM0_RST - PWM0 reset control - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL3_PWM0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_PWM0_RST_SHIFT)) & SYSCON_PRESETCTRL3_PWM0_RST_MASK) - -#define SYSCON_PRESETCTRL3_PWM1_RST_MASK (0x40U) -#define SYSCON_PRESETCTRL3_PWM1_RST_SHIFT (6U) -/*! PWM1_RST - PWM1 reset control - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL3_PWM1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_PWM1_RST_SHIFT)) & SYSCON_PRESETCTRL3_PWM1_RST_MASK) - -#define SYSCON_PRESETCTRL3_AOI0_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL3_AOI0_RST_SHIFT (7U) -/*! AOI0_RST - AOI0 reset control - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL3_AOI0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_AOI0_RST_SHIFT)) & SYSCON_PRESETCTRL3_AOI0_RST_MASK) - -#define SYSCON_PRESETCTRL3_AOI1_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL3_AOI1_RST_SHIFT (8U) -/*! AOI1_RST - AOI1 reset control - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL3_AOI1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_AOI1_RST_SHIFT)) & SYSCON_PRESETCTRL3_AOI1_RST_MASK) - -#define SYSCON_PRESETCTRL3_FTM0_RST_MASK (0x200U) -#define SYSCON_PRESETCTRL3_FTM0_RST_SHIFT (9U) -/*! FTM0_RST - FTM0 reset control - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL3_FTM0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_FTM0_RST_SHIFT)) & SYSCON_PRESETCTRL3_FTM0_RST_MASK) - -#define SYSCON_PRESETCTRL3_DAC1_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL3_DAC1_RST_SHIFT (10U) -/*! DAC1_RST - DAC1 reset control - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL3_DAC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_DAC1_RST_SHIFT)) & SYSCON_PRESETCTRL3_DAC1_RST_MASK) - -#define SYSCON_PRESETCTRL3_DAC2_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL3_DAC2_RST_SHIFT (11U) -/*! DAC2_RST - DAC2 reset control - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL3_DAC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_DAC2_RST_SHIFT)) & SYSCON_PRESETCTRL3_DAC2_RST_MASK) - -#define SYSCON_PRESETCTRL3_OPAMP0_RST_MASK (0x1000U) -#define SYSCON_PRESETCTRL3_OPAMP0_RST_SHIFT (12U) -/*! OPAMP0_RST - OPAMP0 reset control - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL3_OPAMP0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_OPAMP0_RST_SHIFT)) & SYSCON_PRESETCTRL3_OPAMP0_RST_MASK) - -#define SYSCON_PRESETCTRL3_OPAMP1_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL3_OPAMP1_RST_SHIFT (13U) -/*! OPAMP1_RST - OPAMP1 reset control - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL3_OPAMP1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_OPAMP1_RST_SHIFT)) & SYSCON_PRESETCTRL3_OPAMP1_RST_MASK) - -#define SYSCON_PRESETCTRL3_OPAMP2_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL3_OPAMP2_RST_SHIFT (14U) -/*! OPAMP2_RST - OPAMP2 reset control - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL3_OPAMP2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_OPAMP2_RST_SHIFT)) & SYSCON_PRESETCTRL3_OPAMP2_RST_MASK) - -#define SYSCON_PRESETCTRL3_HSCMP0_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL3_HSCMP0_RST_SHIFT (15U) -/*! HSCMP0_RST - HSCMP0 reset control - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL3_HSCMP0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_HSCMP0_RST_SHIFT)) & SYSCON_PRESETCTRL3_HSCMP0_RST_MASK) - -#define SYSCON_PRESETCTRL3_HSCMP1_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL3_HSCMP1_RST_SHIFT (16U) -/*! HSCMP1_RST - HSCMP1 reset control - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL3_HSCMP1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_HSCMP1_RST_SHIFT)) & SYSCON_PRESETCTRL3_HSCMP1_RST_MASK) - -#define SYSCON_PRESETCTRL3_HSCMP2_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL3_HSCMP2_RST_SHIFT (17U) -/*! HSCMP2_RST - HSCMP2 reset control - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL3_HSCMP2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_HSCMP2_RST_SHIFT)) & SYSCON_PRESETCTRL3_HSCMP2_RST_MASK) - -#define SYSCON_PRESETCTRL3_VREF_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL3_VREF_RST_SHIFT (18U) -/*! VREF_RST - VREF reset control - * 0b1..Block is reset. - * 0b0..Block is not reset. - */ -#define SYSCON_PRESETCTRL3_VREF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_VREF_RST_SHIFT)) & SYSCON_PRESETCTRL3_VREF_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRLSET - Peripheral reset control set n */ -/*! @{ */ - -#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) - -#define SYSCON_PRESETCTRLSET_DATA_L_MASK (0x7FFU) -#define SYSCON_PRESETCTRLSET_DATA_L_SHIFT (0U) -/*! DATA_L - Data array value - */ -#define SYSCON_PRESETCTRLSET_DATA_L(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_L_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_L_MASK) - -#define SYSCON_PRESETCTRLSET_DATA_U_MASK (0xFFFFF000U) -#define SYSCON_PRESETCTRLSET_DATA_U_SHIFT (12U) -/*! DATA_U - Data array value - */ -#define SYSCON_PRESETCTRLSET_DATA_U(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_U_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_U_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLSET */ -#define SYSCON_PRESETCTRLSET_COUNT (4U) - -/*! @name PRESETCTRLCLR - Peripheral reset control clear n */ -/*! @{ */ - -#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) - -#define SYSCON_PRESETCTRLCLR_DATA_L_MASK (0x7FFU) -#define SYSCON_PRESETCTRLCLR_DATA_L_SHIFT (0U) -/*! DATA_L - Data array value - */ -#define SYSCON_PRESETCTRLCLR_DATA_L(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_L_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_L_MASK) - -#define SYSCON_PRESETCTRLCLR_DATA_U_MASK (0xFFFFF000U) -#define SYSCON_PRESETCTRLCLR_DATA_U_SHIFT (12U) -/*! DATA_U - Data array value - */ -#define SYSCON_PRESETCTRLCLR_DATA_U(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_U_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_U_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLCLR */ -#define SYSCON_PRESETCTRLCLR_COUNT (4U) - -/*! @name SWR_RESET - Software Reset */ -/*! @{ */ - -#define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU) -#define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U) -/*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset. - */ -#define SYSCON_SWR_RESET_SWR_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL0 - AHB Clock control 0 */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) -#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) -/*! ROM - Enables the clock for the ROM. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) - -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U) -/*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK) - -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U) -/*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK) - -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK (0x20U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT (5U) -/*! SRAM_CTRL3 - Enables the clock for the SRAM Controller 3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK) - -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK (0x40U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT (6U) -/*! SRAM_CTRL4 - Enables the clock for the SRAM Controller 4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK) - -#define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U) -#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U) -/*! FLASH - Enables the clock for the Flash controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK) - -#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U) -#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U) -/*! FMC - Enables the clock for the FMC controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) - -#define SYSCON_AHBCLKCTRL0_FLEXSPI_MASK (0x400U) -#define SYSCON_AHBCLKCTRL0_FLEXSPI_SHIFT (10U) -/*! FLEXSPI - Enables the clock for the Flexspi. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_FLEXSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLEXSPI_SHIFT)) & SYSCON_AHBCLKCTRL0_FLEXSPI_MASK) - -#define SYSCON_AHBCLKCTRL0_MUX_MASK (0x800U) -#define SYSCON_AHBCLKCTRL0_MUX_SHIFT (11U) -/*! MUX - Enables the clock for the Input Mux. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_MUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK) - -#define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U) -/*! IOCON - Enables the clock for the I/O controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK) - -#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U) -/*! GPIO0 - Enables the clock for the GPIO0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) - -#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U) -/*! GPIO1 - Enables the clock for the GPIO1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) - -#define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (16U) -/*! GPIO2 - Enables the clock for the GPIO2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK) - -#define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (17U) -/*! GPIO3 - Enables the clock for the GPIO3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK) - -#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U) -/*! PINT - Enables the clock for the Pin interrupt (PINT). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) - -#define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U) -/*! GINT - Enables the clock for the Group interrupt (GINT). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK) - -#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U) -#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U) -/*! DMA0 - Enables the clock for the DMA0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) - -#define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U) -#define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U) -/*! CRCGEN - Enables the clock for the CRCGEN. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK) - -#define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U) -/*! WWDT - Enables the clock for the Watchdog Timer. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK) - -#define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U) -#define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U) -/*! RTC - Enables the clock for the Real Time Clock (RTC). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK) - -#define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U) -/*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK) - -#define SYSCON_AHBCLKCTRL0_ADC0_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL0_ADC0_SHIFT (27U) -/*! ADC0 - Enables the clock for ADC0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC0_MASK) - -#define SYSCON_AHBCLKCTRL0_ADC1_MASK (0x10000000U) -#define SYSCON_AHBCLKCTRL0_ADC1_SHIFT (28U) -/*! ADC1 - Enables the clock for ADC1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC1_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC1_MASK) - -#define SYSCON_AHBCLKCTRL0_DAC0_MASK (0x20000000U) -#define SYSCON_AHBCLKCTRL0_DAC0_SHIFT (29U) -/*! DAC0 - Enables the clock for DAC0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DAC0_SHIFT)) & SYSCON_AHBCLKCTRL0_DAC0_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL1 - AHB Clock control 1 */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) -#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) -/*! MRT - Enables the clock for the MRT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) - -#define SYSCON_AHBCLKCTRL1_OSTIMER_MASK (0x2U) -#define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT (1U) -/*! OSTIMER - Enables the clock for the OS Event Timer. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK) - -#define SYSCON_AHBCLKCTRL1_SCT_MASK (0x4U) -#define SYSCON_AHBCLKCTRL1_SCT_SHIFT (2U) -/*! SCT - Enables the clock for the SCT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_SCT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT_MASK) - -#define SYSCON_AHBCLKCTRL1_CAN_MASK (0x80U) -#define SYSCON_AHBCLKCTRL1_CAN_SHIFT (7U) -/*! CAN - Enables the clock for the CAN. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_CAN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_CAN_SHIFT)) & SYSCON_AHBCLKCTRL1_CAN_MASK) - -#define SYSCON_AHBCLKCTRL1_UTICK_MASK (0x400U) -#define SYSCON_AHBCLKCTRL1_UTICK_SHIFT (10U) -/*! UTICK - Enables the clock for the UTICK. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK) - -#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) -#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) -/*! FC0 - Enables the clock for the FC0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) - -#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) -#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) -/*! FC1 - Enables the clock for the FC1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) - -#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) -/*! FC2 - Enables the clock for the FC2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) - -#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) -/*! FC3 - Enables the clock for the FC3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) - -#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) -/*! FC4 - Enables the clock for the FC4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) - -#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) -/*! FC5 - Enables the clock for the FC5. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) - -#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) -/*! FC6 - Enables the clock for the FC6. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) - -#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) -/*! FC7 - Enables the clock for the FC7. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) - -#define SYSCON_AHBCLKCTRL1_DMIC_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL1_DMIC_SHIFT (19U) -/*! DMIC - Enables the clock for DMIC. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_DMIC_SHIFT)) & SYSCON_AHBCLKCTRL1_DMIC_MASK) - -#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) -/*! TIMER2 - Enables the clock for the Timer 2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) - -#define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK (0x2000000U) -#define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT (25U) -/*! USB0_DEV - Enables the clock for the USB0-FS device. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_USB0_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK) - -#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) -/*! TIMER0 - Enables the clock for the Timer 0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) - -#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) -/*! TIMER1 - Enables the clock for the Timer 1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) - -#define SYSCON_AHBCLKCTRL1_EZHA_MASK (0x40000000U) -#define SYSCON_AHBCLKCTRL1_EZHA_SHIFT (30U) -/*! EZHA - Enables the clock for the EZH a. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_EZHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EZHA_SHIFT)) & SYSCON_AHBCLKCTRL1_EZHA_MASK) - -#define SYSCON_AHBCLKCTRL1_EZHB_MASK (0x80000000U) -#define SYSCON_AHBCLKCTRL1_EZHB_SHIFT (31U) -/*! EZHB - Enables the clock for the EZH b. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_EZHB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EZHB_SHIFT)) & SYSCON_AHBCLKCTRL1_EZHB_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL2 - AHB Clock control 2 */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) -#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) -/*! DMA1 - Enables the clock for the DMA1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) - -#define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U) -#define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U) -/*! COMP - Enables the clock for the Analog comparator. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK) - -#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) -#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) -/*! FREQME - Enables the clock for the Frequency meter. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) - -#define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U) -/*! RNG - Enables the clock for the RNG. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK) - -#define SYSCON_AHBCLKCTRL2_PMUX1_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL2_PMUX1_SHIFT (14U) -/*! PMUX1 - Enables the clock for Peripheral Input Mux 1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PMUX1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PMUX1_SHIFT)) & SYSCON_AHBCLKCTRL2_PMUX1_MASK) - -#define SYSCON_AHBCLKCTRL2_SYSCTL_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT (15U) -/*! SYSCTL - SYSCTL block clock. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_SYSCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT)) & SYSCON_AHBCLKCTRL2_SYSCTL_MASK) - -#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT (16U) -/*! USB0_HOSTM - Enables the clock for the USB0-FS Host Master. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK) - -#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT (17U) -/*! USB0_HOSTS - Enables the clock for the USB0-FS Host Slave. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK) - -#define SYSCON_AHBCLKCTRL2_CSS_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL2_CSS_SHIFT (18U) -/*! CSS - Enables the clock for CSS. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_CSS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CSS_SHIFT)) & SYSCON_AHBCLKCTRL2_CSS_MASK) - -#define SYSCON_AHBCLKCTRL2_PQ_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL2_PQ_SHIFT (19U) -/*! PQ - Enables the clock for the Power Quad. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK) - -#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) -#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) -/*! TIMER3 - Enables the clock for the Timer 3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) - -#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) -/*! TIMER4 - Enables the clock for the Timer 4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) - -#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) -#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) -/*! PUF - Enables the clock for the PUF reset control. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) - -#define SYSCON_AHBCLKCTRL2_PKC_MASK (0x1000000U) -#define SYSCON_AHBCLKCTRL2_PKC_SHIFT (24U) -/*! PKC - Enables the clock for the PKC. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PKC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PKC_SHIFT)) & SYSCON_AHBCLKCTRL2_PKC_MASK) - -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U) -/*! ANALOG_CTRL - Enables the clock for the Analog Controller block. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK) - -#define SYSCON_AHBCLKCTRL2_HS_SPI_MASK (0x10000000U) -#define SYSCON_AHBCLKCTRL2_HS_SPI_SHIFT (28U) -/*! HS_SPI - Enables the clock for the HS SPI. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_HS_SPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_SPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_SPI_MASK) - -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U) -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U) -/*! GPIO_SEC - Enables the clock for the GPIO secure. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK) - -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U) -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U) -/*! GPIO_SEC_INT - Enables the clock for the GPIO secure int. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL3 - AHB Clock Control 3 */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRL3_I3C0_MASK (0x1U) -#define SYSCON_AHBCLKCTRL3_I3C0_SHIFT (0U) -/*! I3C0 - Enables the clock for I3C0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL3_I3C0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_I3C0_SHIFT)) & SYSCON_AHBCLKCTRL3_I3C0_MASK) - -#define SYSCON_AHBCLKCTRL3_ENC0_MASK (0x8U) -#define SYSCON_AHBCLKCTRL3_ENC0_SHIFT (3U) -/*! ENC0 - Enables the clock for ENC0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL3_ENC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_ENC0_SHIFT)) & SYSCON_AHBCLKCTRL3_ENC0_MASK) - -#define SYSCON_AHBCLKCTRL3_ENC1_MASK (0x10U) -#define SYSCON_AHBCLKCTRL3_ENC1_SHIFT (4U) -/*! ENC1 - Enables the clock for ENC1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL3_ENC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_ENC1_SHIFT)) & SYSCON_AHBCLKCTRL3_ENC1_MASK) - -#define SYSCON_AHBCLKCTRL3_PWM0_MASK (0x20U) -#define SYSCON_AHBCLKCTRL3_PWM0_SHIFT (5U) -/*! PWM0 - Enables the clock for PWM0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL3_PWM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_PWM0_SHIFT)) & SYSCON_AHBCLKCTRL3_PWM0_MASK) - -#define SYSCON_AHBCLKCTRL3_PWM1_MASK (0x40U) -#define SYSCON_AHBCLKCTRL3_PWM1_SHIFT (6U) -/*! PWM1 - Enables the clock for PWM1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL3_PWM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_PWM1_SHIFT)) & SYSCON_AHBCLKCTRL3_PWM1_MASK) - -#define SYSCON_AHBCLKCTRL3_AOI0_MASK (0x80U) -#define SYSCON_AHBCLKCTRL3_AOI0_SHIFT (7U) -/*! AOI0 - Enables the clock for AOI0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL3_AOI0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_AOI0_SHIFT)) & SYSCON_AHBCLKCTRL3_AOI0_MASK) - -#define SYSCON_AHBCLKCTRL3_AOI1_MASK (0x100U) -#define SYSCON_AHBCLKCTRL3_AOI1_SHIFT (8U) -/*! AOI1 - Enables the clock for AOI1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL3_AOI1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_AOI1_SHIFT)) & SYSCON_AHBCLKCTRL3_AOI1_MASK) - -#define SYSCON_AHBCLKCTRL3_FTM0_MASK (0x200U) -#define SYSCON_AHBCLKCTRL3_FTM0_SHIFT (9U) -/*! FTM0 - Enables the clock for FTM0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL3_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_FTM0_SHIFT)) & SYSCON_AHBCLKCTRL3_FTM0_MASK) - -#define SYSCON_AHBCLKCTRL3_DAC1_MASK (0x400U) -#define SYSCON_AHBCLKCTRL3_DAC1_SHIFT (10U) -/*! DAC1 - Enables the clock for DAC1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL3_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_DAC1_SHIFT)) & SYSCON_AHBCLKCTRL3_DAC1_MASK) - -#define SYSCON_AHBCLKCTRL3_DAC2_MASK (0x800U) -#define SYSCON_AHBCLKCTRL3_DAC2_SHIFT (11U) -/*! DAC2 - Enables the clock for DAC2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL3_DAC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_DAC2_SHIFT)) & SYSCON_AHBCLKCTRL3_DAC2_MASK) - -#define SYSCON_AHBCLKCTRL3_OPAMP0_MASK (0x1000U) -#define SYSCON_AHBCLKCTRL3_OPAMP0_SHIFT (12U) -/*! OPAMP0 - Enables the clock for OPAMP0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL3_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_OPAMP0_SHIFT)) & SYSCON_AHBCLKCTRL3_OPAMP0_MASK) - -#define SYSCON_AHBCLKCTRL3_OPAMP1_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL3_OPAMP1_SHIFT (13U) -/*! OPAMP1 - Enables the clock for OPAMP1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL3_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_OPAMP1_SHIFT)) & SYSCON_AHBCLKCTRL3_OPAMP1_MASK) - -#define SYSCON_AHBCLKCTRL3_OPAMP2_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL3_OPAMP2_SHIFT (14U) -/*! OPAMP2 - Enables the clock for OPAMP2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL3_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_OPAMP2_SHIFT)) & SYSCON_AHBCLKCTRL3_OPAMP2_MASK) - -#define SYSCON_AHBCLKCTRL3_HSCMP0_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL3_HSCMP0_SHIFT (15U) -/*! HSCMP0 - Enables the clock for HSCMP0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL3_HSCMP0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_HSCMP0_SHIFT)) & SYSCON_AHBCLKCTRL3_HSCMP0_MASK) - -#define SYSCON_AHBCLKCTRL3_HSCMP1_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL3_HSCMP1_SHIFT (16U) -/*! HSCMP1 - Enables the clock for HSCMP1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL3_HSCMP1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_HSCMP1_SHIFT)) & SYSCON_AHBCLKCTRL3_HSCMP1_MASK) - -#define SYSCON_AHBCLKCTRL3_HSCMP2_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL3_HSCMP2_SHIFT (17U) -/*! HSCMP2 - Enables the clock for HSCMP2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL3_HSCMP2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_HSCMP2_SHIFT)) & SYSCON_AHBCLKCTRL3_HSCMP2_MASK) - -#define SYSCON_AHBCLKCTRL3_VREF_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL3_VREF_SHIFT (18U) -/*! VREF - Enables the clock for VREF. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL3_VREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_VREF_SHIFT)) & SYSCON_AHBCLKCTRL3_VREF_MASK) -/*! @} */ - -/*! @name AHBCLKCTRLSET - AHB Clock Control Set */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLSET */ -#define SYSCON_AHBCLKCTRLSET_COUNT (4U) - -/*! @name AHBCLKCTRLCLR - AHB Clock Control Clear */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLCLR */ -#define SYSCON_AHBCLKCTRLCLR_COUNT (4U) - -/*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) -/*! SEL - System Tick Timer for CPU0 source select. - * 0b000..System Tick 0 divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name TRACECLKSEL - Trace clock source select */ -/*! @{ */ - -#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) -#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) -/*! SEL - Trace clock source select. - * 0b000..Trace divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL - CTimer 0 clock source select..CTimer 4 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL_SEL_SHIFT (0U) -/*! SEL - CTimer 4 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..PLL1 clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL_SEL_MASK) -/*! @} */ - -/* The count of SYSCON_CTIMERCLKSEL */ -#define SYSCON_CTIMERCLKSEL_COUNT (5U) - -/*! @name MAINCLKSELA - Main clock source select A */ -/*! @{ */ - -#define SYSCON_MAINCLKSELA_SEL_MASK (0x7U) -#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) -/*! SEL - Main clock source select A - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..Reserved. - * 0b101..Reserved. - * 0b110..Reserved. - * 0b111..Reserved. - */ -#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) -/*! @} */ - -/*! @name MAINCLKSELB - Main clock source select B */ -/*! @{ */ - -#define SYSCON_MAINCLKSELB_SEL_MASK (0x7U) -#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) -/*! SEL - Main clock source select B - * 0b000..Use the source selected in MAINCLKSELA. - * 0b001..PLL0 clock. - * 0b010..PLL1 clock. - * 0b011..Oscillator 32 kHz clock. - * 0b100..Reserved. - * 0b101..Reserved. - * 0b110..Reserved. - * 0b111..Reserved. - */ -#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) -/*! @} */ - -/*! @name CLKOUTSEL - CLKOUT clock source select */ -/*! @{ */ - -#define SYSCON_CLKOUTSEL_SEL_MASK (0xFU) -#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) -/*! SEL - CLKOUT clock source select. - * 0b0000..Main clock. - * 0b0001..PLL0 clock. - * 0b0010..CLKIN clock. - * 0b0011..FRO 96 MHz clock. - * 0b0100..FRO 1MHz clock. - * 0b0101..PLL1 clock. - * 0b0110..Oscillator 32kHz clock. - * 0b0111..No clock. - * 0b1000..Reserved. - * 0b1001..Reserved. - * 0b1010..Reserved. - * 0b1011..Reserved. - * 0b1100..No clock. - * 0b1101..No clock. - * 0b1110..No clock. - * 0b1111..No clock. - */ -#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) -/*! @} */ - -/*! @name PLL0CLKSEL - PLL0 clock source select */ -/*! @{ */ - -#define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U) -#define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U) -/*! SEL - PLL0 clock source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..Oscillator 32kHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_PLL0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name PLL1CLKSEL - PLL1 clock source select */ -/*! @{ */ - -#define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U) -#define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U) -/*! SEL - PLL1 clock source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..Oscillator 32kHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_PLL1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name CANCLKSEL - CAN clock source select */ -/*! @{ */ - -#define SYSCON_CANCLKSEL_SEL_MASK (0x7U) -#define SYSCON_CANCLKSEL_SEL_SHIFT (0U) -/*! SEL - CAN clock source select. - * 0b000..CAN divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_CANCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKSEL_SEL_SHIFT)) & SYSCON_CANCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name ADC0CLKSEL - ADC0 clock source select */ -/*! @{ */ - -#define SYSCON_ADC0CLKSEL_SEL_MASK (0x7U) -#define SYSCON_ADC0CLKSEL_SEL_SHIFT (0U) -/*! SEL - ADC clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..FRO 96 MHz clock. - * 0b011..Reserved. - * 0b100..XO to ADC Clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_ADC0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKSEL_SEL_SHIFT)) & SYSCON_ADC0CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name USB0CLKSEL - FS USB clock source select */ -/*! @{ */ - -#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) -#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) -/*! SEL - FS USB clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..PLL1 clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL - Flexcomm 0 clock source select for Fractional Rate Divider..Flexcomm 7 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL_SEL_SHIFT (0U) -/*! SEL - Flexcomm 7 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL_SEL_SHIFT)) & SYSCON_FCCLKSEL_SEL_MASK) -/*! @} */ - -/* The count of SYSCON_FCCLKSEL */ -#define SYSCON_FCCLKSEL_COUNT (8U) - -/*! @name HSSPICLKSEL - HS SPI clock source select */ -/*! @{ */ - -#define SYSCON_HSSPICLKSEL_SEL_MASK (0x7U) -#define SYSCON_HSSPICLKSEL_SEL_SHIFT (0U) -/*! SEL - HS SPI clock source select. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..No clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_HSSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HSSPICLKSEL_SEL_SHIFT)) & SYSCON_HSSPICLKSEL_SEL_MASK) -/*! @} */ - -/*! @name MCLKCLKSEL - MCLK clock source select */ -/*! @{ */ - -#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) -#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) -/*! SEL - MCLK clock source select. - * 0b000..FRO 96 MHz clock. - * 0b001..PLL0 clock. - * 0b010..Reserved. - * 0b011..Reserved. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SCTCLKSEL - SCTimer/PWM clock source select */ -/*! @{ */ - -#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) -#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) -/*! SEL - SCTimer/PWM clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..CLKIN clock. - * 0b011..FRO 96 MHz clock. - * 0b100..PLL1 clock. - * 0b101..MCLK clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKDIV - System Tick Timer divider for CPU0 */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK) - -#define SYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK) - -#define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stopped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK) - -#define SYSCON_SYSTICKCLKDIV_UNSTAB_MASK (0x80000000U) -#define SYSCON_SYSTICKCLKDIV_UNSTAB_SHIFT (31U) -/*! UNSTAB - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SYSTICKCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_UNSTAB_SHIFT)) & SYSCON_SYSTICKCLKDIV_UNSTAB_MASK) -/*! @} */ - -/* The count of SYSCON_SYSTICKCLKDIV */ -#define SYSCON_SYSTICKCLKDIV_COUNT (1U) - -/*! @name TRACECLKDIV - TRACE clock divider */ -/*! @{ */ - -#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) -#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) - -#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) - -#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stopped. - * 0b0..Divider clock is running. - */ -#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) - -#define SYSCON_TRACECLKDIV_UNSTAB_MASK (0x80000000U) -#define SYSCON_TRACECLKDIV_UNSTAB_SHIFT (31U) -/*! UNSTAB - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_TRACECLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_UNSTAB_SHIFT)) & SYSCON_TRACECLKDIV_UNSTAB_MASK) -/*! @} */ - -/*! @name CANCLKDIV - CAN clock divider */ -/*! @{ */ - -#define SYSCON_CANCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_CANCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_CANCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_DIV_SHIFT)) & SYSCON_CANCLKDIV_DIV_MASK) - -#define SYSCON_CANCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_CANCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_CANCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_RESET_SHIFT)) & SYSCON_CANCLKDIV_RESET_MASK) - -#define SYSCON_CANCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_CANCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stopped. - * 0b0..Divider clock is running. - */ -#define SYSCON_CANCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_HALT_SHIFT)) & SYSCON_CANCLKDIV_HALT_MASK) - -#define SYSCON_CANCLKDIV_UNSTAB_MASK (0x80000000U) -#define SYSCON_CANCLKDIV_UNSTAB_SHIFT (31U) -/*! UNSTAB - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_CANCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_UNSTAB_SHIFT)) & SYSCON_CANCLKDIV_UNSTAB_MASK) -/*! @} */ - -/*! @name FRGCTRL - Fractional rate divider for flexcomm 0..Fractional rate divider for flexcomm 7 */ -/*! @{ */ - -#define SYSCON_FRGCTRL_DIV_MASK (0xFFU) -#define SYSCON_FRGCTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK) - -#define SYSCON_FRGCTRL_MULT_MASK (0xFF00U) -#define SYSCON_FRGCTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK) -/*! @} */ - -/* The count of SYSCON_FRGCTRL */ -#define SYSCON_FRGCTRL_COUNT (8U) - -/*! @name AHBCLKDIV - System clock divider */ -/*! @{ */ - -#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) - -#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) - -#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stopped. - * 0b0..Divider clock is running. - */ -#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) - -#define SYSCON_AHBCLKDIV_UNSTAB_MASK (0x80000000U) -#define SYSCON_AHBCLKDIV_UNSTAB_SHIFT (31U) -/*! UNSTAB - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_AHBCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_UNSTAB_SHIFT)) & SYSCON_AHBCLKDIV_UNSTAB_MASK) -/*! @} */ - -/*! @name CLKOUTDIV - CLKOUT clock divider */ -/*! @{ */ - -#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) -#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) - -#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) -#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) - -#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) -#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stopped. - * 0b0..Divider clock is running. - */ -#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) - -#define SYSCON_CLKOUTDIV_UNSTAB_MASK (0x80000000U) -#define SYSCON_CLKOUTDIV_UNSTAB_SHIFT (31U) -/*! UNSTAB - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_CLKOUTDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_UNSTAB_SHIFT)) & SYSCON_CLKOUTDIV_UNSTAB_MASK) -/*! @} */ - -/*! @name FROHFDIV - FRO_HF (96MHz) clock divider */ -/*! @{ */ - -#define SYSCON_FROHFDIV_DIV_MASK (0xFFU) -#define SYSCON_FROHFDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) - -#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U) -#define SYSCON_FROHFDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK) - -#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) -#define SYSCON_FROHFDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stopped. - * 0b0..Divider clock is running. - */ -#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) - -#define SYSCON_FROHFDIV_UNSTAB_MASK (0x80000000U) -#define SYSCON_FROHFDIV_UNSTAB_SHIFT (31U) -/*! UNSTAB - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_FROHFDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_UNSTAB_SHIFT)) & SYSCON_FROHFDIV_UNSTAB_MASK) -/*! @} */ - -/*! @name WDTCLKDIV - WDT clock divider */ -/*! @{ */ - -#define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU) -#define SYSCON_WDTCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_WDTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK) - -#define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_WDTCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_WDTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK) - -#define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_WDTCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stopped. - * 0b0..Divider clock is running. - */ -#define SYSCON_WDTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK) - -#define SYSCON_WDTCLKDIV_UNSTAB_MASK (0x80000000U) -#define SYSCON_WDTCLKDIV_UNSTAB_SHIFT (31U) -/*! UNSTAB - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_WDTCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_UNSTAB_SHIFT)) & SYSCON_WDTCLKDIV_UNSTAB_MASK) -/*! @} */ - -/*! @name ADC0CLKDIV - ADC0 clock divider */ -/*! @{ */ - -#define SYSCON_ADC0CLKDIV_DIV_MASK (0x7U) -#define SYSCON_ADC0CLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_ADC0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_DIV_SHIFT)) & SYSCON_ADC0CLKDIV_DIV_MASK) - -#define SYSCON_ADC0CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_ADC0CLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_ADC0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_RESET_SHIFT)) & SYSCON_ADC0CLKDIV_RESET_MASK) - -#define SYSCON_ADC0CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_ADC0CLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stopped. - * 0b0..Divider clock is running. - */ -#define SYSCON_ADC0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_HALT_SHIFT)) & SYSCON_ADC0CLKDIV_HALT_MASK) - -#define SYSCON_ADC0CLKDIV_UNSTAB_MASK (0x80000000U) -#define SYSCON_ADC0CLKDIV_UNSTAB_SHIFT (31U) -/*! UNSTAB - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_ADC0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_UNSTAB_SHIFT)) & SYSCON_ADC0CLKDIV_UNSTAB_MASK) -/*! @} */ - -/*! @name USB0CLKDIV - USB0-FS Clock divider */ -/*! @{ */ - -#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) -#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) - -#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) - -#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stopped. - * 0b0..Divider clock is running. - */ -#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) - -#define SYSCON_USB0CLKDIV_UNSTAB_MASK (0x80000000U) -#define SYSCON_USB0CLKDIV_UNSTAB_SHIFT (31U) -/*! UNSTAB - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_USB0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_UNSTAB_SHIFT)) & SYSCON_USB0CLKDIV_UNSTAB_MASK) -/*! @} */ - -/*! @name MCLKDIV - I2S MCLK clock divider */ -/*! @{ */ - -#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_MCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) - -#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_MCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) - -#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_MCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stopped. - * 0b0..Divider clock is running. - */ -#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) - -#define SYSCON_MCLKDIV_UNSTAB_MASK (0x80000000U) -#define SYSCON_MCLKDIV_UNSTAB_SHIFT (31U) -/*! UNSTAB - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_MCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_UNSTAB_SHIFT)) & SYSCON_MCLKDIV_UNSTAB_MASK) -/*! @} */ - -/*! @name SCTCLKDIV - SCT/PWM clock divider */ -/*! @{ */ - -#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) - -#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) - -#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stopped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) - -#define SYSCON_SCTCLKDIV_UNSTAB_MASK (0x80000000U) -#define SYSCON_SCTCLKDIV_UNSTAB_SHIFT (31U) -/*! UNSTAB - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SCTCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_UNSTAB_SHIFT)) & SYSCON_SCTCLKDIV_UNSTAB_MASK) -/*! @} */ - -/*! @name PLLCLKDIV - PLL clock divider */ -/*! @{ */ - -#define SYSCON_PLLCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_PLLCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_PLLCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_DIV_SHIFT)) & SYSCON_PLLCLKDIV_DIV_MASK) - -#define SYSCON_PLLCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_PLLCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_PLLCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_RESET_SHIFT)) & SYSCON_PLLCLKDIV_RESET_MASK) - -#define SYSCON_PLLCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_PLLCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stopped. - * 0b0..Divider clock is running. - */ -#define SYSCON_PLLCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_HALT_SHIFT)) & SYSCON_PLLCLKDIV_HALT_MASK) - -#define SYSCON_PLLCLKDIV_UNSTAB_MASK (0x80000000U) -#define SYSCON_PLLCLKDIV_UNSTAB_SHIFT (31U) -/*! UNSTAB - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_PLLCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_UNSTAB_SHIFT)) & SYSCON_PLLCLKDIV_UNSTAB_MASK) -/*! @} */ - -/*! @name CTIMERXCLKDIV_CTIMERCLKDIV - CTimer 0 clock divider..CTimer 4 clock divider */ -/*! @{ */ - -#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value - */ -#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_MASK) - -#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter - * 0b0..Divider is not reset - * 0b1..Divider is reset - */ -#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_MASK) - -#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter - * 0b0..Divider clock is running. - * 0b1..Divider clock has stopped. - */ -#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_MASK) - -#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_MASK (0x80000000U) -#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_SHIFT (31U) -/*! UNSTAB - Divider status flag - * 0b0..Stable divider clock. - * 0b1..Unstable clock frequency. - */ -#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_MASK) -/*! @} */ - -/* The count of SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV */ -#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_COUNT (5U) - -/*! @name CLKUNLOCK - Clock configuration unlock */ -/*! @{ */ - -#define SYSCON_CLKUNLOCK_UNLOCK_MASK (0xFFFFFFFFU) -#define SYSCON_CLKUNLOCK_UNLOCK_SHIFT (0U) -/*! UNLOCK - Control clock configuration registers access (for example, xxxDIV, xxxSEL). - * 0b00000000000000000000000000000001..Update all clock configuration. - * 0b00000000000000000000000000000000..All hardware clock configruration are freeze. - */ -#define SYSCON_CLKUNLOCK_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKUNLOCK_UNLOCK_SHIFT)) & SYSCON_CLKUNLOCK_UNLOCK_MASK) -/*! @} */ - -/*! @name FMCCR - FMC configuration */ -/*! @{ */ - -#define SYSCON_FMCCR_FETCHCFG_MASK (0x3U) -#define SYSCON_FMCCR_FETCHCFG_SHIFT (0U) -/*! FETCHCFG - Instruction fetch configuration. - * 0b00..Instruction fetches from flash are not buffered. - * 0b01..One buffer is used for all instruction fetches. - * 0b10..All buffers may be used for instruction fetches. - */ -#define SYSCON_FMCCR_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCFG_SHIFT)) & SYSCON_FMCCR_FETCHCFG_MASK) - -#define SYSCON_FMCCR_DATACFG_MASK (0xCU) -#define SYSCON_FMCCR_DATACFG_SHIFT (2U) -/*! DATACFG - Data read configuration. - * 0b00..Data accesses from flash are not buffered. - * 0b01..One buffer is used for all data accesses. - * 0b10..All buffers can be used for data accesses. - */ -#define SYSCON_FMCCR_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACFG_SHIFT)) & SYSCON_FMCCR_DATACFG_MASK) - -#define SYSCON_FMCCR_ACCEL_MASK (0x10U) -#define SYSCON_FMCCR_ACCEL_SHIFT (4U) -/*! ACCEL - Acceleration enable. - * 0b0..Flash acceleration is disabled. - * 0b1..Flash acceleration is enabled. - */ -#define SYSCON_FMCCR_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK) - -#define SYSCON_FMCCR_PREFEN_MASK (0x20U) -#define SYSCON_FMCCR_PREFEN_SHIFT (5U) -/*! PREFEN - Prefetch enable. - * 0b0..No instruction prefetch is performed. - * 0b1..Instruction prefetch is enabled. - */ -#define SYSCON_FMCCR_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK) - -#define SYSCON_FMCCR_PREFOVR_MASK (0x40U) -#define SYSCON_FMCCR_PREFOVR_SHIFT (6U) -/*! PREFOVR - Prefetch override. - * 0b0..Any previously initiated prefetch will be completed. - * 0b1..Any previously initiated prefetch will be aborted, and the next flash line following the current - * execution address will be prefetched if not already buffered. - */ -#define SYSCON_FMCCR_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK) - -#define SYSCON_FMCCR_FLASHTIM_MASK (0xF000U) -#define SYSCON_FMCCR_FLASHTIM_SHIFT (12U) -/*! FLASHTIM - Flash memory access time. - * 0b0000..1 system clock flash access time (for system clock rates up to 11 MHz). - * 0b0001..2 system clocks flash access time (for system clock rates up to 22 MHz). - * 0b0010..3 system clocks flash access time (for system clock rates up to 33 MHz). - * 0b0011..4 system clocks flash access time (for system clock rates up to 44 MHz). - * 0b0100..5 system clocks flash access time (for system clock rates up to 55 MHz). - * 0b0101..6 system clocks flash access time (for system clock rates up to 66 MHz). - * 0b0110..7 system clocks flash access time (for system clock rates up to 77 MHz). - * 0b0111..8 system clocks flash access time (for system clock rates up to 88 MHz). - * 0b1000..9 system clocks flash access time (for system clock rates up to 100 MHz). - * 0b1001..10 system clocks flash access time (for system clock rates up to 115 MHz). - * 0b1010..11 system clocks flash access time (for system clock rates up to 130 MHz). - * 0b1011..12 system clocks flash access time (for system clock rates up to 150 MHz). - */ -#define SYSCON_FMCCR_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FLASHTIM_SHIFT)) & SYSCON_FMCCR_FLASHTIM_MASK) - -#define SYSCON_FMCCR_ECCABORTEN_MASK (0x300000U) -#define SYSCON_FMCCR_ECCABORTEN_SHIFT (20U) -/*! ECCABORTEN - ECC error abort enable - */ -#define SYSCON_FMCCR_ECCABORTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ECCABORTEN_SHIFT)) & SYSCON_FMCCR_ECCABORTEN_MASK) - -#define SYSCON_FMCCR_CLKDIV_MASK (0xC000000U) -#define SYSCON_FMCCR_CLKDIV_SHIFT (26U) -/*! CLKDIV - CLKDIV; default value is 00. - * 0b00..1 division - * 0b01..2 division - * 0b10..3 division - * 0b11..4 division - */ -#define SYSCON_FMCCR_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_CLKDIV_SHIFT)) & SYSCON_FMCCR_CLKDIV_MASK) -/*! @} */ - -/*! @name ROMCR - ROM wait state */ -/*! @{ */ - -#define SYSCON_ROMCR_ROM_WAIT_MASK (0x1U) -#define SYSCON_ROMCR_ROM_WAIT_SHIFT (0U) -/*! ROM_WAIT - ROM waiting Arm core and other masters. - */ -#define SYSCON_ROMCR_ROM_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ROMCR_ROM_WAIT_SHIFT)) & SYSCON_ROMCR_ROM_WAIT_MASK) -/*! @} */ - -/*! @name USB0NEEDCLKCTRL - USB0-FS need clock control */ -/*! @{ */ - -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK (0x1U) -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT (0U) -/*! AP_FS_DEV_NEEDCLK - USB0-FS Device USB0_NEEDCLK signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. - */ -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK) - -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK (0x2U) -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT (1U) -/*! POL_FS_DEV_NEEDCLK - USB0-FS Device USB0_NEEDCLK polarity for triggering the USB0-FS wake-up interrupt:. - * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. - * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK) - -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK (0x4U) -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT (2U) -/*! AP_FS_HOST_NEEDCLK - USB0-FS Host USB0_NEEDCLK signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. - */ -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK) - -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK (0x8U) -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT (3U) -/*! POL_FS_HOST_NEEDCLK - USB0-FS Host USB0_NEEDCLK polarity for triggering the USB0-FS wake-up interrupt:. - * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. - * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK) -/*! @} */ - -/*! @name USB0NEEDCLKSTAT - USB0-FS need clock status */ -/*! @{ */ - -#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) -#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) -/*! DEV_NEEDCLK - USB0-FS Device USB0_NEEDCLK signal status:. - * 0b1..USB0-FS Device clock is high. - * 0b0..USB0-FS Device clock is low. - */ -#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK) - -#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) -#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) -/*! HOST_NEEDCLK - USB0-FS Host USB0_NEEDCLK signal status:. - * 0b1..USB0-FS Host clock is high. - * 0b0..USB0-FS Host clock is low. - */ -#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK) -/*! @} */ - -/*! @name EZHINT - EZH interrupt hijack */ -/*! @{ */ - -#define SYSCON_EZHINT_EZHINT_MASK (0xFFFFFFFFU) -#define SYSCON_EZHINT_EZHINT_SHIFT (0U) -/*! EZHINT - EZH interrupt hijack. - */ -#define SYSCON_EZHINT_EZHINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EZHINT_EZHINT_SHIFT)) & SYSCON_EZHINT_EZHINT_MASK) -/*! @} */ - -/*! @name FMCFLUSH - FMC flush control */ -/*! @{ */ - -#define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U) -#define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U) -/*! FLUSH - Flush control - * 0b1..Flush the FMC buffer contents. - * 0b0..No action. - */ -#define SYSCON_FMCFLUSH_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK) -/*! @} */ - -/*! @name MCLKIO - MCLK control */ -/*! @{ */ - -#define SYSCON_MCLKIO_MCLKIO_MASK (0x1U) -#define SYSCON_MCLKIO_MCLKIO_SHIFT (0U) -/*! MCLKIO - MCLK control. - * 0b0..input mode. - * 0b1..output mode. - */ -#define SYSCON_MCLKIO_MCLKIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK) -/*! @} */ - -/*! @name ADC1CLKSEL - ADC1 clock source select */ -/*! @{ */ - -#define SYSCON_ADC1CLKSEL_SEL_MASK (0x7U) -#define SYSCON_ADC1CLKSEL_SEL_SHIFT (0U) -/*! SEL - ADC clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..FRO 96 MHz clock. - * 0b011..Reserved. - * 0b100..XO to ADC clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_ADC1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKSEL_SEL_SHIFT)) & SYSCON_ADC1CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name ADC1CLKDIV - ADC1 clock divider */ -/*! @{ */ - -#define SYSCON_ADC1CLKDIV_DIV_MASK (0x7U) -#define SYSCON_ADC1CLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_ADC1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_DIV_SHIFT)) & SYSCON_ADC1CLKDIV_DIV_MASK) - -#define SYSCON_ADC1CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_ADC1CLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_ADC1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_RESET_SHIFT)) & SYSCON_ADC1CLKDIV_RESET_MASK) - -#define SYSCON_ADC1CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_ADC1CLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stopped. - * 0b0..Divider clock is running. - */ -#define SYSCON_ADC1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_HALT_SHIFT)) & SYSCON_ADC1CLKDIV_HALT_MASK) - -#define SYSCON_ADC1CLKDIV_UNSTAB_MASK (0x80000000U) -#define SYSCON_ADC1CLKDIV_UNSTAB_SHIFT (31U) -/*! UNSTAB - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_ADC1CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_UNSTAB_SHIFT)) & SYSCON_ADC1CLKDIV_UNSTAB_MASK) -/*! @} */ - -/*! @name RAM_INTERLEAVE - Control RAM interleave integration */ -/*! @{ */ - -#define SYSCON_RAM_INTERLEAVE_INTERLEAVE_MASK (0x1U) -#define SYSCON_RAM_INTERLEAVE_INTERLEAVE_SHIFT (0U) -/*! INTERLEAVE - Control RAM access for RAM_02 and RAM_03. - * 0b1..RAM access to RAM_02 and RAM_03 is interleaved. This setting is need for PKC L0 memory access. - * 0b0..RAM access to RAM_02 and RAM_03 is consecutive. - */ -#define SYSCON_RAM_INTERLEAVE_INTERLEAVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_INTERLEAVE_INTERLEAVE_SHIFT)) & SYSCON_RAM_INTERLEAVE_INTERLEAVE_MASK) -/*! @} */ - -/*! @name DAC_CLKSEL - DAC0 functional clock selection..DAC2 functional clock selection */ -/*! @{ */ - -#define SYSCON_DAC_CLKSEL_SEL_MASK (0x7U) -#define SYSCON_DAC_CLKSEL_SEL_SHIFT (0U) -/*! SEL - DAC clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO_HF. - * 0b100..FRO_12M. - * 0b101..PLL1 clock. - * 0b110..FRO_1M. - * 0b111..No clock. - */ -#define SYSCON_DAC_CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKSEL_SEL_SHIFT)) & SYSCON_DAC_CLKSEL_SEL_MASK) -/*! @} */ - -/* The count of SYSCON_DAC_CLKSEL */ -#define SYSCON_DAC_CLKSEL_COUNT (3U) - -/*! @name DAC_CLKDIV - DAC0 functional clock divider..DAC2 functional clock divider */ -/*! @{ */ - -#define SYSCON_DAC_CLKDIV_DIV_MASK (0x7U) -#define SYSCON_DAC_CLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_DAC_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKDIV_DIV_SHIFT)) & SYSCON_DAC_CLKDIV_DIV_MASK) - -#define SYSCON_DAC_CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_DAC_CLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_DAC_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKDIV_RESET_SHIFT)) & SYSCON_DAC_CLKDIV_RESET_MASK) - -#define SYSCON_DAC_CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_DAC_CLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stopped. - * 0b0..Divider clock is running. - */ -#define SYSCON_DAC_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKDIV_HALT_SHIFT)) & SYSCON_DAC_CLKDIV_HALT_MASK) - -#define SYSCON_DAC_CLKDIV_UNSTAB_MASK (0x80000000U) -#define SYSCON_DAC_CLKDIV_UNSTAB_SHIFT (31U) -/*! UNSTAB - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_DAC_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKDIV_UNSTAB_SHIFT)) & SYSCON_DAC_CLKDIV_UNSTAB_MASK) -/*! @} */ - -/* The count of SYSCON_DAC_CLKDIV */ -#define SYSCON_DAC_CLKDIV_COUNT (3U) - -/*! @name FLEXSPICLKSEL - FLEXSPI clock selection */ -/*! @{ */ - -#define SYSCON_FLEXSPICLKSEL_SEL_MASK (0xFU) -#define SYSCON_FLEXSPICLKSEL_SEL_SHIFT (0U) -/*! SEL - Flexspi clock select - * 0b0000..Main clock - * 0b0001..PLL0 clock - * 0b0010..No clock - * 0b0011..FRO_HF - * 0b0100..No clock - * 0b0101..PLL1 clock - * 0b0110..No clock - * 0b0111..No clock - * 0b1000..No clock - * 0b1001..No clock - * 0b1010..No clock - * 0b1011..No clock - * 0b1100..No clock - * 0b1101..No clock - * 0b1110..No clock - * 0b1111..No clock - */ -#define SYSCON_FLEXSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKSEL_SEL_SHIFT)) & SYSCON_FLEXSPICLKSEL_SEL_MASK) -/*! @} */ - -/*! @name FLEXSPICLKDIV - FLEXSPI clock divider */ -/*! @{ */ - -#define SYSCON_FLEXSPICLKDIV_DIV_MASK (0x7U) -#define SYSCON_FLEXSPICLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_FLEXSPICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKDIV_DIV_SHIFT)) & SYSCON_FLEXSPICLKDIV_DIV_MASK) - -#define SYSCON_FLEXSPICLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_FLEXSPICLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_FLEXSPICLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKDIV_RESET_SHIFT)) & SYSCON_FLEXSPICLKDIV_RESET_MASK) - -#define SYSCON_FLEXSPICLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_FLEXSPICLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stopped. - * 0b0..Divider clock is running. - */ -#define SYSCON_FLEXSPICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKDIV_HALT_SHIFT)) & SYSCON_FLEXSPICLKDIV_HALT_MASK) - -#define SYSCON_FLEXSPICLKDIV_UNSTAB_MASK (0x80000000U) -#define SYSCON_FLEXSPICLKDIV_UNSTAB_SHIFT (31U) -/*! UNSTAB - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_FLEXSPICLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXSPICLKDIV_UNSTAB_MASK) -/*! @} */ - -/*! @name CDPA_ENABLE - Enable protection */ -/*! @{ */ - -#define SYSCON_CDPA_ENABLE_CDPA_ENABLE_MASK (0x3U) -#define SYSCON_CDPA_ENABLE_CDPA_ENABLE_SHIFT (0U) -/*! CDPA_ENABLE - Enable control - */ -#define SYSCON_CDPA_ENABLE_CDPA_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CDPA_ENABLE_CDPA_ENABLE_SHIFT)) & SYSCON_CDPA_ENABLE_CDPA_ENABLE_MASK) -/*! @} */ - -/*! @name CDPA_ENABLE_DP - Enable protection duplicate */ -/*! @{ */ - -#define SYSCON_CDPA_ENABLE_DP_CDPA_ENABLE_DP_MASK (0x3U) -#define SYSCON_CDPA_ENABLE_DP_CDPA_ENABLE_DP_SHIFT (0U) -/*! CDPA_ENABLE_DP - Enable control - */ -#define SYSCON_CDPA_ENABLE_DP_CDPA_ENABLE_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CDPA_ENABLE_DP_CDPA_ENABLE_DP_SHIFT)) & SYSCON_CDPA_ENABLE_DP_CDPA_ENABLE_DP_MASK) -/*! @} */ - -/*! @name CDPA_CONFIG - CDPA base address */ -/*! @{ */ - -#define SYSCON_CDPA_CONFIG_CDPA_START_PAGE_MASK (0x1FFU) -#define SYSCON_CDPA_CONFIG_CDPA_START_PAGE_SHIFT (0U) -/*! CDPA_START_PAGE - Specifies the size of CDPA in number of pages. - */ -#define SYSCON_CDPA_CONFIG_CDPA_START_PAGE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CDPA_CONFIG_CDPA_START_PAGE_SHIFT)) & SYSCON_CDPA_CONFIG_CDPA_START_PAGE_MASK) -/*! @} */ - -/*! @name FLASH_HIDING_LOCKOUT_ADDR - Flash hiding lockout address */ -/*! @{ */ - -#define SYSCON_FLASH_HIDING_LOCKOUT_ADDR_flash_hiding_lockout_addr_MASK (0xFFFFFFFFU) -#define SYSCON_FLASH_HIDING_LOCKOUT_ADDR_flash_hiding_lockout_addr_SHIFT (0U) -/*! flash_hiding_lockout_addr - while flash hiding is disabled, register write is locked. - */ -#define SYSCON_FLASH_HIDING_LOCKOUT_ADDR_flash_hiding_lockout_addr(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASH_HIDING_LOCKOUT_ADDR_flash_hiding_lockout_addr_SHIFT)) & SYSCON_FLASH_HIDING_LOCKOUT_ADDR_flash_hiding_lockout_addr_MASK) -/*! @} */ - -/*! @name FLASH_HIDING_BASE_ADDR - Flash hiding base address */ -/*! @{ */ - -#define SYSCON_FLASH_HIDING_BASE_ADDR_flash_hiding_base_addr_MASK (0x3FFFFU) -#define SYSCON_FLASH_HIDING_BASE_ADDR_flash_hiding_base_addr_SHIFT (0U) -/*! flash_hiding_base_addr - Base address for flash hiding - */ -#define SYSCON_FLASH_HIDING_BASE_ADDR_flash_hiding_base_addr(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASH_HIDING_BASE_ADDR_flash_hiding_base_addr_SHIFT)) & SYSCON_FLASH_HIDING_BASE_ADDR_flash_hiding_base_addr_MASK) -/*! @} */ - -/*! @name FLASH_HIDING_BASE_DP_ADDR - Flash hiding base DP address */ -/*! @{ */ - -#define SYSCON_FLASH_HIDING_BASE_DP_ADDR_flash_hiding_base_addr_MASK (0x3FFFFU) -#define SYSCON_FLASH_HIDING_BASE_DP_ADDR_flash_hiding_base_addr_SHIFT (0U) -/*! flash_hiding_base_addr - Base address for flash hiding - */ -#define SYSCON_FLASH_HIDING_BASE_DP_ADDR_flash_hiding_base_addr(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASH_HIDING_BASE_DP_ADDR_flash_hiding_base_addr_SHIFT)) & SYSCON_FLASH_HIDING_BASE_DP_ADDR_flash_hiding_base_addr_MASK) -/*! @} */ - -/*! @name FLASH_HIDING_SIZE_ADDR - Hiding size address */ -/*! @{ */ - -#define SYSCON_FLASH_HIDING_SIZE_ADDR_flash_hiding_size_addr_MASK (0x3FFFFU) -#define SYSCON_FLASH_HIDING_SIZE_ADDR_flash_hiding_size_addr_SHIFT (0U) -/*! flash_hiding_size_addr - Size address for flash hiding - */ -#define SYSCON_FLASH_HIDING_SIZE_ADDR_flash_hiding_size_addr(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASH_HIDING_SIZE_ADDR_flash_hiding_size_addr_SHIFT)) & SYSCON_FLASH_HIDING_SIZE_ADDR_flash_hiding_size_addr_MASK) -/*! @} */ - -/*! @name FLASH_HIDING_SIZE_DP_ADDR - Hiding size DP address */ -/*! @{ */ - -#define SYSCON_FLASH_HIDING_SIZE_DP_ADDR_flash_hiding_size_dp_addr_MASK (0x3FFFFU) -#define SYSCON_FLASH_HIDING_SIZE_DP_ADDR_flash_hiding_size_dp_addr_SHIFT (0U) -/*! flash_hiding_size_dp_addr - Size address for flash hiding - */ -#define SYSCON_FLASH_HIDING_SIZE_DP_ADDR_flash_hiding_size_dp_addr(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASH_HIDING_SIZE_DP_ADDR_flash_hiding_size_dp_addr_SHIFT)) & SYSCON_FLASH_HIDING_SIZE_DP_ADDR_flash_hiding_size_dp_addr_MASK) -/*! @} */ - -/*! @name PLLCLKDIVSEL - PLL clock divider clock selection */ -/*! @{ */ - -#define SYSCON_PLLCLKDIVSEL_SEL_MASK (0x7U) -#define SYSCON_PLLCLKDIVSEL_SEL_SHIFT (0U) -/*! SEL - Flexspi clock select - * 0b000..PLL0 clock - * 0b001..PLL1 clock - * 0b010..No clock - * 0b011..No clock - * 0b100..No clock - * 0b101..No clock - * 0b110..No clock - * 0b111..No clock - */ -#define SYSCON_PLLCLKDIVSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIVSEL_SEL_SHIFT)) & SYSCON_PLLCLKDIVSEL_SEL_MASK) -/*! @} */ - -/*! @name I3CFCLKSEL - I3C functional clock selection */ -/*! @{ */ - -#define SYSCON_I3CFCLKSEL_SEL_MASK (0x7U) -#define SYSCON_I3CFCLKSEL_SEL_SHIFT (0U) -/*! SEL - I3C clock select - * 0b000..Main clock - * 0b001..FRO_HF_DIV - * 0b010..No clock - * 0b011..No clock - * 0b100..No clock - * 0b101..No clock - * 0b110..No clock - * 0b111..No clock - */ -#define SYSCON_I3CFCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSEL_SEL_SHIFT)) & SYSCON_I3CFCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name I3CFCLKSTCSEL - I3C FCLK_STC clock selection */ -/*! @{ */ - -#define SYSCON_I3CFCLKSTCSEL_SEL_MASK (0x7U) -#define SYSCON_I3CFCLKSTCSEL_SEL_SHIFT (0U) -/*! SEL - I3C FCLK_STC clock select - * 0b000..I3CFCLK - * 0b001..FRO_1M - * 0b010..No clock - * 0b011..No clock - * 0b100..No clock - * 0b101..No clock - * 0b110..No clock - * 0b111..No clock - */ -#define SYSCON_I3CFCLKSTCSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSTCSEL_SEL_SHIFT)) & SYSCON_I3CFCLKSTCSEL_SEL_MASK) -/*! @} */ - -/*! @name I3CFCLKSTCDIV - I3C FCLK_STC clock divider */ -/*! @{ */ - -#define SYSCON_I3CFCLKSTCDIV_DIV_MASK (0x7U) -#define SYSCON_I3CFCLKSTCDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_I3CFCLKSTCDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSTCDIV_DIV_SHIFT)) & SYSCON_I3CFCLKSTCDIV_DIV_MASK) - -#define SYSCON_I3CFCLKSTCDIV_RESET_MASK (0x20000000U) -#define SYSCON_I3CFCLKSTCDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_I3CFCLKSTCDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSTCDIV_RESET_SHIFT)) & SYSCON_I3CFCLKSTCDIV_RESET_MASK) - -#define SYSCON_I3CFCLKSTCDIV_HALT_MASK (0x40000000U) -#define SYSCON_I3CFCLKSTCDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stopped. - * 0b0..Divider clock is running. - */ -#define SYSCON_I3CFCLKSTCDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSTCDIV_HALT_SHIFT)) & SYSCON_I3CFCLKSTCDIV_HALT_MASK) - -#define SYSCON_I3CFCLKSTCDIV_UNSTAB_MASK (0x80000000U) -#define SYSCON_I3CFCLKSTCDIV_UNSTAB_SHIFT (31U) -/*! UNSTAB - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_I3CFCLKSTCDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSTCDIV_UNSTAB_SHIFT)) & SYSCON_I3CFCLKSTCDIV_UNSTAB_MASK) -/*! @} */ - -/*! @name I3CFCLKSDIV - I3C FCLKS clock divider */ -/*! @{ */ - -#define SYSCON_I3CFCLKSDIV_DIV_MASK (0x7U) -#define SYSCON_I3CFCLKSDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_I3CFCLKSDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSDIV_DIV_SHIFT)) & SYSCON_I3CFCLKSDIV_DIV_MASK) - -#define SYSCON_I3CFCLKSDIV_RESET_MASK (0x20000000U) -#define SYSCON_I3CFCLKSDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_I3CFCLKSDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSDIV_RESET_SHIFT)) & SYSCON_I3CFCLKSDIV_RESET_MASK) - -#define SYSCON_I3CFCLKSDIV_HALT_MASK (0x40000000U) -#define SYSCON_I3CFCLKSDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stopped. - * 0b0..Divider clock is running. - */ -#define SYSCON_I3CFCLKSDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSDIV_HALT_SHIFT)) & SYSCON_I3CFCLKSDIV_HALT_MASK) - -#define SYSCON_I3CFCLKSDIV_UNSTAB_MASK (0x80000000U) -#define SYSCON_I3CFCLKSDIV_UNSTAB_SHIFT (31U) -/*! UNSTAB - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_I3CFCLKSDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSDIV_UNSTAB_SHIFT)) & SYSCON_I3CFCLKSDIV_UNSTAB_MASK) -/*! @} */ - -/*! @name I3CFCLKDIV - I3C FCLK divider */ -/*! @{ */ - -#define SYSCON_I3CFCLKDIV_DIV_MASK (0x7U) -#define SYSCON_I3CFCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_I3CFCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKDIV_DIV_SHIFT)) & SYSCON_I3CFCLKDIV_DIV_MASK) - -#define SYSCON_I3CFCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_I3CFCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_I3CFCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKDIV_RESET_SHIFT)) & SYSCON_I3CFCLKDIV_RESET_MASK) - -#define SYSCON_I3CFCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_I3CFCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stopped. - * 0b0..Divider clock is running. - */ -#define SYSCON_I3CFCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKDIV_HALT_SHIFT)) & SYSCON_I3CFCLKDIV_HALT_MASK) - -#define SYSCON_I3CFCLKDIV_UNSTAB_MASK (0x80000000U) -#define SYSCON_I3CFCLKDIV_UNSTAB_SHIFT (31U) -/*! UNSTAB - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_I3CFCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKDIV_UNSTAB_SHIFT)) & SYSCON_I3CFCLKDIV_UNSTAB_MASK) -/*! @} */ - -/*! @name I3CFCLKSSEL - I3C FCLK_S selection */ -/*! @{ */ - -#define SYSCON_I3CFCLKSSEL_SEL_MASK (0x7U) -#define SYSCON_I3CFCLKSSEL_SEL_SHIFT (0U) -/*! SEL - I3C FCLK_S clock select - * 0b000..FRO_1M - * 0b001..No clock - * 0b010..No clock - * 0b011..No clock - * 0b100..No clock - * 0b101..No clock - * 0b110..No clock - * 0b111..No clock - */ -#define SYSCON_I3CFCLKSSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSSEL_SEL_SHIFT)) & SYSCON_I3CFCLKSSEL_SEL_MASK) -/*! @} */ - -/*! @name DMICFCLKSEL - DMIC clock selection */ -/*! @{ */ - -#define SYSCON_DMICFCLKSEL_SEL_MASK (0x7U) -#define SYSCON_DMICFCLKSEL_SEL_SHIFT (0U) -/*! SEL - DMIC clock select - * 0b000..Main clock - * 0b001..PLL0 clock - * 0b010..Clock in - * 0b011..FRO_HF - * 0b100..PLL1 clock - * 0b101..MCLK in - * 0b110..No clock - * 0b111..No clock - */ -#define SYSCON_DMICFCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICFCLKSEL_SEL_SHIFT)) & SYSCON_DMICFCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name DMICFCLKDIV - DMIC clock division */ -/*! @{ */ - -#define SYSCON_DMICFCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_DMICFCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_DMICFCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICFCLKDIV_DIV_SHIFT)) & SYSCON_DMICFCLKDIV_DIV_MASK) - -#define SYSCON_DMICFCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_DMICFCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_DMICFCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICFCLKDIV_RESET_SHIFT)) & SYSCON_DMICFCLKDIV_RESET_MASK) - -#define SYSCON_DMICFCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_DMICFCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stopped. - * 0b0..Divider clock is running. - */ -#define SYSCON_DMICFCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICFCLKDIV_HALT_SHIFT)) & SYSCON_DMICFCLKDIV_HALT_MASK) - -#define SYSCON_DMICFCLKDIV_UNSTAB_MASK (0x80000000U) -#define SYSCON_DMICFCLKDIV_UNSTAB_SHIFT (31U) -/*! UNSTAB - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_DMICFCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICFCLKDIV_UNSTAB_SHIFT)) & SYSCON_DMICFCLKDIV_UNSTAB_MASK) -/*! @} */ - -/*! @name PLL1CTRL - PLL1 550m control */ -/*! @{ */ - -#define SYSCON_PLL1CTRL_SELR_MASK (0xFU) -#define SYSCON_PLL1CTRL_SELR_SHIFT (0U) -/*! SELR - Bandwidth select R value. - */ -#define SYSCON_PLL1CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK) - -#define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U) -#define SYSCON_PLL1CTRL_SELI_SHIFT (4U) -/*! SELI - Bandwidth select I value. - */ -#define SYSCON_PLL1CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK) - -#define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U) -#define SYSCON_PLL1CTRL_SELP_SHIFT (10U) -/*! SELP - Bandwidth select P value. - */ -#define SYSCON_PLL1CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U) -#define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U) -/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - * 0b1..PLL input clock is sent directly to the PLL output. - * 0b0..use PLL. - */ -#define SYSCON_PLL1CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U) -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U) -/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - * 0b1..bypass of the divide-by-2 divider in the post-divider. - * 0b0..use the divide-by-2 divider in the post-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) - -#define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U) -#define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U) -/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. - */ -#define SYSCON_PLL1CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK) - -#define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U) -#define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U) -/*! BWDIRECT - control of the bandwidth of the PLL. - * 0b1..modify the bandwidth of the PLL directly. - * 0b0..the bandwidth is changed synchronously with the feedback-divider. - */ -#define SYSCON_PLL1CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U) -#define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U) -/*! BYPASSPREDIV - bypass of the pre-divider. - * 0b1..bypass of the pre-divider. - * 0b0..use the pre-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U) -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U) -/*! BYPASSPOSTDIV - bypass of the post-divider. - * 0b1..bypass of the post-divider. - * 0b0..use the post-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) - -#define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U) -#define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U) -/*! CLKEN - enable the output clock. - * 0b1..Enable the output clock. - * 0b0..Disable the output clock. - */ -#define SYSCON_PLL1CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK) - -#define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U) -#define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U) -/*! FRMEN - 1: free running mode. - */ -#define SYSCON_PLL1CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK) - -#define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U) -#define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U) -/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable. - */ -#define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK) - -#define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U) -#define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U) -/*! SKEWEN - Skew mode. - * 0b1..skewmode is enable. - * 0b0..skewmode is disable. - */ -#define SYSCON_PLL1CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK) -/*! @} */ - -/*! @name PLL1STAT - PLL1 550m status */ -/*! @{ */ - -#define SYSCON_PLL1STAT_LOCK_MASK (0x1U) -#define SYSCON_PLL1STAT_LOCK_SHIFT (0U) -/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. - */ -#define SYSCON_PLL1STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK) - -#define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U) -#define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U) -/*! PREDIVACK - pre-divider ratio change acknowledge. - */ -#define SYSCON_PLL1STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK) - -#define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U) -#define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U) -/*! FEEDDIVACK - feedback divider ratio change acknowledge. - */ -#define SYSCON_PLL1STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK) - -#define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U) -#define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U) -/*! POSTDIVACK - post-divider ratio change acknowledge. - */ -#define SYSCON_PLL1STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK) - -#define SYSCON_PLL1STAT_FRMDET_MASK (0x10U) -#define SYSCON_PLL1STAT_FRMDET_SHIFT (4U) -/*! FRMDET - free running detector output (active high). - */ -#define SYSCON_PLL1STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK) -/*! @} */ - -/*! @name PLL1NDEC - PLL1 550m N divider */ -/*! @{ */ - -#define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU) -#define SYSCON_PLL1NDEC_NDIV_SHIFT (0U) -/*! NDIV - pre-divider divider ratio (N-divider). - */ -#define SYSCON_PLL1NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK) - -#define SYSCON_PLL1NDEC_NREQ_MASK (0x100U) -#define SYSCON_PLL1NDEC_NREQ_SHIFT (8U) -/*! NREQ - pre-divider ratio change request. - */ -#define SYSCON_PLL1NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK) -/*! @} */ - -/*! @name PLL1MDEC - PLL1 550m M divider */ -/*! @{ */ - -#define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU) -#define SYSCON_PLL1MDEC_MDIV_SHIFT (0U) -/*! MDIV - feedback divider divider ratio (M-divider). - */ -#define SYSCON_PLL1MDEC_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK) - -#define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U) -#define SYSCON_PLL1MDEC_MREQ_SHIFT (16U) -/*! MREQ - feedback ratio change request. - */ -#define SYSCON_PLL1MDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK) -/*! @} */ - -/*! @name PLL1PDEC - PLL1 550m P divider */ -/*! @{ */ - -#define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU) -#define SYSCON_PLL1PDEC_PDIV_SHIFT (0U) -/*! PDIV - post-divider divider ratio (P-divider) - */ -#define SYSCON_PLL1PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK) - -#define SYSCON_PLL1PDEC_PREQ_MASK (0x20U) -#define SYSCON_PLL1PDEC_PREQ_SHIFT (5U) -/*! PREQ - feedback ratio change request. - */ -#define SYSCON_PLL1PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK) -/*! @} */ - -/*! @name PLL0CTRL - PLL0 550m control */ -/*! @{ */ - -#define SYSCON_PLL0CTRL_SELR_MASK (0xFU) -#define SYSCON_PLL0CTRL_SELR_SHIFT (0U) -/*! SELR - Bandwidth select R value. - */ -#define SYSCON_PLL0CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK) - -#define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U) -#define SYSCON_PLL0CTRL_SELI_SHIFT (4U) -/*! SELI - Bandwidth select I value. - */ -#define SYSCON_PLL0CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK) - -#define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U) -#define SYSCON_PLL0CTRL_SELP_SHIFT (10U) -/*! SELP - Bandwidth select P value. - */ -#define SYSCON_PLL0CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U) -#define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U) -/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - * 0b1..Bypass PLL input clock is sent directly to the PLL output. - * 0b0..use PLL. - */ -#define SYSCON_PLL0CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U) -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U) -/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - * 0b1..bypass of the divide-by-2 divider in the post-divider. - * 0b0..use the divide-by-2 divider in the post-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) - -#define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U) -#define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U) -/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. - */ -#define SYSCON_PLL0CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK) - -#define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U) -#define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U) -/*! BWDIRECT - Control of the bandwidth of the PLL. - * 0b1..modify the bandwidth of the PLL directly. - * 0b0..the bandwidth is changed synchronously with the feedback-divider. - */ -#define SYSCON_PLL0CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U) -#define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U) -/*! BYPASSPREDIV - bypass of the pre-divider. - * 0b1..bypass of the pre-divider. - * 0b0..use the pre-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U) -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U) -/*! BYPASSPOSTDIV - bypass of the post-divider. - * 0b1..bypass of the post-divider. - * 0b0..use the post-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) - -#define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U) -#define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U) -/*! CLKEN - enable the output clock. - * 0b1..enable the output clock. - * 0b0..disable the output clock. - */ -#define SYSCON_PLL0CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK) - -#define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U) -#define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U) -/*! FRMEN - free running mode. - * 0b1..free running mode is enable. - * 0b0..free running mode is disable. - */ -#define SYSCON_PLL0CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK) - -#define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U) -#define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U) -/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable. - */ -#define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK) - -#define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U) -#define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U) -/*! SKEWEN - skew mode. - * 0b1..skew mode is enable. - * 0b0..skew mode is disable. - */ -#define SYSCON_PLL0CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK) -/*! @} */ - -/*! @name PLL0STAT - PLL0 550m status */ -/*! @{ */ - -#define SYSCON_PLL0STAT_LOCK_MASK (0x1U) -#define SYSCON_PLL0STAT_LOCK_SHIFT (0U) -/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. - */ -#define SYSCON_PLL0STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK) - -#define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U) -#define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U) -/*! PREDIVACK - pre-divider ratio change acknowledge. - */ -#define SYSCON_PLL0STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK) - -#define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U) -#define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U) -/*! FEEDDIVACK - feedback divider ratio change acknowledge. - */ -#define SYSCON_PLL0STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK) - -#define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U) -#define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U) -/*! POSTDIVACK - post-divider ratio change acknowledge. - */ -#define SYSCON_PLL0STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK) - -#define SYSCON_PLL0STAT_FRMDET_MASK (0x10U) -#define SYSCON_PLL0STAT_FRMDET_SHIFT (4U) -/*! FRMDET - free running detector output (active high). - */ -#define SYSCON_PLL0STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK) -/*! @} */ - -/*! @name PLL0NDEC - PLL0 550m N divider */ -/*! @{ */ - -#define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU) -#define SYSCON_PLL0NDEC_NDIV_SHIFT (0U) -/*! NDIV - pre-divider divider ratio (N-divider). - */ -#define SYSCON_PLL0NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK) - -#define SYSCON_PLL0NDEC_NREQ_MASK (0x100U) -#define SYSCON_PLL0NDEC_NREQ_SHIFT (8U) -/*! NREQ - pre-divider ratio change request. - */ -#define SYSCON_PLL0NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK) -/*! @} */ - -/*! @name PLL0PDEC - PLL0 550m P divider */ -/*! @{ */ - -#define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU) -#define SYSCON_PLL0PDEC_PDIV_SHIFT (0U) -/*! PDIV - post-divider divider ratio (P-divider) - */ -#define SYSCON_PLL0PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK) - -#define SYSCON_PLL0PDEC_PREQ_MASK (0x20U) -#define SYSCON_PLL0PDEC_PREQ_SHIFT (5U) -/*! PREQ - feedback ratio change request. - */ -#define SYSCON_PLL0PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK) -/*! @} */ - -/*! @name PLL0SSCG0 - PLL0 Spread Spectrum control 0 */ -/*! @{ */ - -#define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU) -#define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U) -/*! MD_LBS - input word of the wrapper bit 31 to 0. - */ -#define SYSCON_PLL0SSCG0_MD_LBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK) -/*! @} */ - -/*! @name PLL0SSCG1 - PLL0 Spread Spectrum control 1 */ -/*! @{ */ - -#define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U) -#define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U) -/*! MD_MBS - input word of the wrapper bit 32. - */ -#define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK) - -#define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U) -#define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U) -/*! MD_REQ - md change request. - */ -#define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK) - -#define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) -#define SYSCON_PLL0SSCG1_MF_SHIFT (2U) -/*! MF - programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3. - */ -#define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK) - -#define SYSCON_PLL0SSCG1_MR_MASK (0xE0U) -#define SYSCON_PLL0SSCG1_MR_SHIFT (5U) -/*! MR - programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) - * mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1. - */ -#define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK) - -#define SYSCON_PLL0SSCG1_MC_MASK (0x300U) -#define SYSCON_PLL0SSCG1_MC_SHIFT (8U) -/*! MC - modulation waveform control Compensation for low pass filtering of the PLL to get a - * triangular modulation at the output of the PLL, giving a flat frequency spectrum. - */ -#define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK) - -#define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U) -#define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U) -/*! MDIV_EXT - to select an external mdiv value. - */ -#define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) - -#define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U) -#define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U) -/*! MREQ - to select an external mreq value. - */ -#define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK) - -#define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U) -#define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U) -/*! DITHER - dithering between two modulation frequencies in a random way or in a pseudo random way - * (white noise), in order to decrease the probability that the modulated waveform will occur - * with the same phase on a particular point on the screen. - */ -#define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK) - -#define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U) -#define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U) -/*! SEL_EXT - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext. - */ -#define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK) -/*! @} */ - -/*! @name DAC_ISO_CTRL - DAC Isolation Control */ -/*! @{ */ - -#define SYSCON_DAC_ISO_CTRL_DAC0_ISO_MASK (0x1U) -#define SYSCON_DAC_ISO_CTRL_DAC0_ISO_SHIFT (0U) -/*! DAC0_ISO - DAC0 Isolation - * 0b0..DAC0 isolation disabled - * 0b1..DAC0 isolation enabled - */ -#define SYSCON_DAC_ISO_CTRL_DAC0_ISO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_ISO_CTRL_DAC0_ISO_SHIFT)) & SYSCON_DAC_ISO_CTRL_DAC0_ISO_MASK) - -#define SYSCON_DAC_ISO_CTRL_DAC1_ISO_MASK (0x2U) -#define SYSCON_DAC_ISO_CTRL_DAC1_ISO_SHIFT (1U) -/*! DAC1_ISO - DAC1 Isolation - * 0b0..DAC1 isolation disabled - * 0b1..DAC1 isolation enabled - */ -#define SYSCON_DAC_ISO_CTRL_DAC1_ISO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_ISO_CTRL_DAC1_ISO_SHIFT)) & SYSCON_DAC_ISO_CTRL_DAC1_ISO_MASK) - -#define SYSCON_DAC_ISO_CTRL_DAC2_ISO_MASK (0x4U) -#define SYSCON_DAC_ISO_CTRL_DAC2_ISO_SHIFT (2U) -/*! DAC2_ISO - DAC2 Isolation - * 0b0..DAC2 isolation disabled - * 0b1..DAC2 isolation enabled - */ -#define SYSCON_DAC_ISO_CTRL_DAC2_ISO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_ISO_CTRL_DAC2_ISO_SHIFT)) & SYSCON_DAC_ISO_CTRL_DAC2_ISO_MASK) -/*! @} */ - -/*! @name STARTER - Start logic wake-up enable */ -/*! @{ */ - -#define SYSCON_STARTER_FLEXPWM1_COMPARE1_IRQ_MASK (0x1U) -#define SYSCON_STARTER_FLEXPWM1_COMPARE1_IRQ_SHIFT (0U) -/*! FLEXPWM1_COMPARE1_IRQ - FlexPWM1 compare interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM1_COMPARE1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_COMPARE1_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_COMPARE1_IRQ_MASK) - -#define SYSCON_STARTER_GPIO_INT04_MASK (0x1U) -#define SYSCON_STARTER_GPIO_INT04_SHIFT (0U) -/*! GPIO_INT04 - GPIO_INT04 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GPIO_INT04(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT04_SHIFT)) & SYSCON_STARTER_GPIO_INT04_MASK) - -#define SYSCON_STARTER_SYS_MASK (0x1U) -#define SYSCON_STARTER_SYS_SHIFT (0U) -/*! SYS - SYS interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SYS_SHIFT)) & SYSCON_STARTER_SYS_MASK) - -#define SYSCON_STARTER_CSS_IRQ1_MASK (0x2U) -#define SYSCON_STARTER_CSS_IRQ1_SHIFT (1U) -/*! CSS_IRQ1 - CSS_IRQ1 (Digital Glitch Detect) - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CSS_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CSS_IRQ1_SHIFT)) & SYSCON_STARTER_CSS_IRQ1_MASK) - -#define SYSCON_STARTER_FLEXPWM1_RELOAD1_IRQ_MASK (0x2U) -#define SYSCON_STARTER_FLEXPWM1_RELOAD1_IRQ_SHIFT (1U) -/*! FLEXPWM1_RELOAD1_IRQ - FlexPWM1 reload interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM1_RELOAD1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_RELOAD1_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_RELOAD1_IRQ_MASK) - -#define SYSCON_STARTER_GPIO_INT05_MASK (0x2U) -#define SYSCON_STARTER_GPIO_INT05_SHIFT (1U) -/*! GPIO_INT05 - GPIO_INT05 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GPIO_INT05(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT05_SHIFT)) & SYSCON_STARTER_GPIO_INT05_MASK) - -#define SYSCON_STARTER_SDMA0_MASK (0x2U) -#define SYSCON_STARTER_SDMA0_SHIFT (1U) -/*! SDMA0 - SDMA0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA0_SHIFT)) & SYSCON_STARTER_SDMA0_MASK) - -#define SYSCON_STARTER_FLEXPWM1_COMPARE2_IRQ_MASK (0x4U) -#define SYSCON_STARTER_FLEXPWM1_COMPARE2_IRQ_SHIFT (2U) -/*! FLEXPWM1_COMPARE2_IRQ - FlexPWM1 compare interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM1_COMPARE2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_COMPARE2_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_COMPARE2_IRQ_MASK) - -#define SYSCON_STARTER_GINT0_MASK (0x4U) -#define SYSCON_STARTER_GINT0_SHIFT (2U) -/*! GINT0 - GINT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK) - -#define SYSCON_STARTER_GPIO_INT06_MASK (0x4U) -#define SYSCON_STARTER_GPIO_INT06_SHIFT (2U) -/*! GPIO_INT06 - GPIO_INT06 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GPIO_INT06(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT06_SHIFT)) & SYSCON_STARTER_GPIO_INT06_MASK) - -#define SYSCON_STARTER_TAMPER_IRQ_MASK (0x4U) -#define SYSCON_STARTER_TAMPER_IRQ_SHIFT (2U) -/*! TAMPER_IRQ - Tamper interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_TAMPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_TAMPER_IRQ_SHIFT)) & SYSCON_STARTER_TAMPER_IRQ_MASK) - -#define SYSCON_STARTER_FLEXPWM1_RELOAD2_IRQ_MASK (0x8U) -#define SYSCON_STARTER_FLEXPWM1_RELOAD2_IRQ_SHIFT (3U) -/*! FLEXPWM1_RELOAD2_IRQ - FlexPWM1 reload interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM1_RELOAD2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_RELOAD2_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_RELOAD2_IRQ_MASK) - -#define SYSCON_STARTER_GINT1_MASK (0x8U) -#define SYSCON_STARTER_GINT1_SHIFT (3U) -/*! GINT1 - GINT1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK) - -#define SYSCON_STARTER_GPIO_INT07_MASK (0x8U) -#define SYSCON_STARTER_GPIO_INT07_SHIFT (3U) -/*! GPIO_INT07 - GPIO_INT07 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GPIO_INT07(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT07_SHIFT)) & SYSCON_STARTER_GPIO_INT07_MASK) - -#define SYSCON_STARTER_CTIMER2_MASK (0x10U) -#define SYSCON_STARTER_CTIMER2_SHIFT (4U) -/*! CTIMER2 - CTIMER2 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER2_SHIFT)) & SYSCON_STARTER_CTIMER2_MASK) - -#define SYSCON_STARTER_FLEXPWM1_COMPARE3_IRQ_MASK (0x10U) -#define SYSCON_STARTER_FLEXPWM1_COMPARE3_IRQ_SHIFT (4U) -/*! FLEXPWM1_COMPARE3_IRQ - FlexPWM1 compare interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM1_COMPARE3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_COMPARE3_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_COMPARE3_IRQ_MASK) - -#define SYSCON_STARTER_PIO_INT0_MASK (0x10U) -#define SYSCON_STARTER_PIO_INT0_SHIFT (4U) -/*! PIO_INT0 - PIO_INT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PIO_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT0_SHIFT)) & SYSCON_STARTER_PIO_INT0_MASK) - -#define SYSCON_STARTER_CTIMER4_MASK (0x20U) -#define SYSCON_STARTER_CTIMER4_SHIFT (5U) -/*! CTIMER4 - CTIMER4 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER4_SHIFT)) & SYSCON_STARTER_CTIMER4_MASK) - -#define SYSCON_STARTER_FLEXPWM1_RELOAD3_IRQ_MASK (0x20U) -#define SYSCON_STARTER_FLEXPWM1_RELOAD3_IRQ_SHIFT (5U) -/*! FLEXPWM1_RELOAD3_IRQ - FlexPWM1 reload interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM1_RELOAD3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_RELOAD3_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_RELOAD3_IRQ_MASK) - -#define SYSCON_STARTER_PIO_INT1_MASK (0x20U) -#define SYSCON_STARTER_PIO_INT1_SHIFT (5U) -/*! PIO_INT1 - PIO_INT1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PIO_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT1_SHIFT)) & SYSCON_STARTER_PIO_INT1_MASK) - -#define SYSCON_STARTER_ENCO_COMPARE_IRQ_MASK (0x40U) -#define SYSCON_STARTER_ENCO_COMPARE_IRQ_SHIFT (6U) -/*! ENCO_COMPARE_IRQ - ENC0 compare interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_ENCO_COMPARE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENCO_COMPARE_IRQ_SHIFT)) & SYSCON_STARTER_ENCO_COMPARE_IRQ_MASK) - -#define SYSCON_STARTER_OS_EVENT_MASK (0x40U) -#define SYSCON_STARTER_OS_EVENT_SHIFT (6U) -/*! OS_EVENT - OS_EVENT interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_OS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_OS_EVENT_SHIFT)) & SYSCON_STARTER_OS_EVENT_MASK) - -#define SYSCON_STARTER_PIO_INT2_MASK (0x40U) -#define SYSCON_STARTER_PIO_INT2_SHIFT (6U) -/*! PIO_INT2 - PIO_INT2 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PIO_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT2_SHIFT)) & SYSCON_STARTER_PIO_INT2_MASK) - -#define SYSCON_STARTER_ENCO_HOME_IRQ_MASK (0x80U) -#define SYSCON_STARTER_ENCO_HOME_IRQ_SHIFT (7U) -/*! ENCO_HOME_IRQ - ENC0 home interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_ENCO_HOME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENCO_HOME_IRQ_SHIFT)) & SYSCON_STARTER_ENCO_HOME_IRQ_MASK) - -#define SYSCON_STARTER_FLEXSPI_MASK (0x80U) -#define SYSCON_STARTER_FLEXSPI_SHIFT (7U) -/*! FLEXSPI - FLEXSPI interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXSPI_SHIFT)) & SYSCON_STARTER_FLEXSPI_MASK) - -#define SYSCON_STARTER_PIO_INT3_MASK (0x80U) -#define SYSCON_STARTER_PIO_INT3_SHIFT (7U) -/*! PIO_INT3 - PIO_INT3 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PIO_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT3_SHIFT)) & SYSCON_STARTER_PIO_INT3_MASK) - -#define SYSCON_STARTER_ENCO_WDG_IRQ_MASK (0x100U) -#define SYSCON_STARTER_ENCO_WDG_IRQ_SHIFT (8U) -/*! ENCO_WDG_IRQ - ENC0 WDOG interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_ENCO_WDG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENCO_WDG_IRQ_SHIFT)) & SYSCON_STARTER_ENCO_WDG_IRQ_MASK) - -#define SYSCON_STARTER_UTICK0_MASK (0x100U) -#define SYSCON_STARTER_UTICK0_SHIFT (8U) -/*! UTICK0 - UTICK0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK0_SHIFT)) & SYSCON_STARTER_UTICK0_MASK) - -#define SYSCON_STARTER_ENCO_IDX_IRQ_MASK (0x200U) -#define SYSCON_STARTER_ENCO_IDX_IRQ_SHIFT (9U) -/*! ENCO_IDX_IRQ - ENC0 IDX interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_ENCO_IDX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENCO_IDX_IRQ_SHIFT)) & SYSCON_STARTER_ENCO_IDX_IRQ_MASK) - -#define SYSCON_STARTER_MRT0_MASK (0x200U) -#define SYSCON_STARTER_MRT0_SHIFT (9U) -/*! MRT0 - MRT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT0_SHIFT)) & SYSCON_STARTER_MRT0_MASK) - -#define SYSCON_STARTER_CTIMER0_MASK (0x400U) -#define SYSCON_STARTER_CTIMER0_SHIFT (10U) -/*! CTIMER0 - CTIMER0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK) - -#define SYSCON_STARTER_DAC0_IRQ_MASK (0x400U) -#define SYSCON_STARTER_DAC0_IRQ_SHIFT (10U) -/*! DAC0_IRQ - DAC0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_DAC0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DAC0_IRQ_SHIFT)) & SYSCON_STARTER_DAC0_IRQ_MASK) - -#define SYSCON_STARTER_ENC1_COMPARE_IRQ_MASK (0x400U) -#define SYSCON_STARTER_ENC1_COMPARE_IRQ_SHIFT (10U) -/*! ENC1_COMPARE_IRQ - ENC1 compare interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_ENC1_COMPARE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENC1_COMPARE_IRQ_SHIFT)) & SYSCON_STARTER_ENC1_COMPARE_IRQ_MASK) - -#define SYSCON_STARTER_CAN0_IRQ0_MASK (0x800U) -#define SYSCON_STARTER_CAN0_IRQ0_SHIFT (11U) -/*! CAN0_IRQ0 - CAN0_IRQ0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CAN0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CAN0_IRQ0_SHIFT)) & SYSCON_STARTER_CAN0_IRQ0_MASK) - -#define SYSCON_STARTER_CTIMER1_MASK (0x800U) -#define SYSCON_STARTER_CTIMER1_SHIFT (11U) -/*! CTIMER1 - CTIMER1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK) - -#define SYSCON_STARTER_DAC1_IRQ_MASK (0x800U) -#define SYSCON_STARTER_DAC1_IRQ_SHIFT (11U) -/*! DAC1_IRQ - DAC1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_DAC1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DAC1_IRQ_SHIFT)) & SYSCON_STARTER_DAC1_IRQ_MASK) - -#define SYSCON_STARTER_ENC1_HOME_IRQ_MASK (0x800U) -#define SYSCON_STARTER_ENC1_HOME_IRQ_SHIFT (11U) -/*! ENC1_HOME_IRQ - ENC1 home interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_ENC1_HOME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENC1_HOME_IRQ_SHIFT)) & SYSCON_STARTER_ENC1_HOME_IRQ_MASK) - -#define SYSCON_STARTER_CAN0_IRQ1_MASK (0x1000U) -#define SYSCON_STARTER_CAN0_IRQ1_SHIFT (12U) -/*! CAN0_IRQ1 - CAN0_IRQ0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CAN0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CAN0_IRQ1_SHIFT)) & SYSCON_STARTER_CAN0_IRQ1_MASK) - -#define SYSCON_STARTER_DAC2_IRQ_MASK (0x1000U) -#define SYSCON_STARTER_DAC2_IRQ_SHIFT (12U) -/*! DAC2_IRQ - DAC2 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_DAC2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DAC2_IRQ_SHIFT)) & SYSCON_STARTER_DAC2_IRQ_MASK) - -#define SYSCON_STARTER_ENC1_WDG_IRQ_MASK (0x1000U) -#define SYSCON_STARTER_ENC1_WDG_IRQ_SHIFT (12U) -/*! ENC1_WDG_IRQ - ENC1 WDOG interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_ENC1_WDG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENC1_WDG_IRQ_SHIFT)) & SYSCON_STARTER_ENC1_WDG_IRQ_MASK) - -#define SYSCON_STARTER_SCT0_MASK (0x1000U) -#define SYSCON_STARTER_SCT0_SHIFT (12U) -/*! SCT0 - SCT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK) - -#define SYSCON_STARTER_CTIMER3_MASK (0x2000U) -#define SYSCON_STARTER_CTIMER3_SHIFT (13U) -/*! CTIMER3 - CTIMER3 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK) - -#define SYSCON_STARTER_ENC1_IDX_IRQ_MASK (0x2000U) -#define SYSCON_STARTER_ENC1_IDX_IRQ_SHIFT (13U) -/*! ENC1_IDX_IRQ - ENC1 IDX interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_ENC1_IDX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENC1_IDX_IRQ_SHIFT)) & SYSCON_STARTER_ENC1_IDX_IRQ_MASK) - -#define SYSCON_STARTER_HS_CMP0_IRQ_MASK (0x2000U) -#define SYSCON_STARTER_HS_CMP0_IRQ_SHIFT (13U) -/*! HS_CMP0_IRQ - HS_CMP0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_HS_CMP0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HS_CMP0_IRQ_SHIFT)) & SYSCON_STARTER_HS_CMP0_IRQ_MASK) - -#define SYSCON_STARTER_SPI_FILTER_MASK (0x2000U) -#define SYSCON_STARTER_SPI_FILTER_SHIFT (13U) -/*! SPI_FILTER - SPI_FILTER interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SPI_FILTER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SPI_FILTER_SHIFT)) & SYSCON_STARTER_SPI_FILTER_MASK) - -#define SYSCON_STARTER_FLEXINT0_MASK (0x4000U) -#define SYSCON_STARTER_FLEXINT0_SHIFT (14U) -/*! FLEXINT0 - FLEXINT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT0_SHIFT)) & SYSCON_STARTER_FLEXINT0_MASK) - -#define SYSCON_STARTER_HS_CMP1_IRQ_MASK (0x4000U) -#define SYSCON_STARTER_HS_CMP1_IRQ_SHIFT (14U) -/*! HS_CMP1_IRQ - HS_CMP1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_HS_CMP1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HS_CMP1_IRQ_SHIFT)) & SYSCON_STARTER_HS_CMP1_IRQ_MASK) - -#define SYSCON_STARTER_ITRC_IRQ_MASK (0x4000U) -#define SYSCON_STARTER_ITRC_IRQ_SHIFT (14U) -/*! ITRC_IRQ - ITRC interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_ITRC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ITRC_IRQ_SHIFT)) & SYSCON_STARTER_ITRC_IRQ_MASK) - -#define SYSCON_STARTER_FLEXINT1_MASK (0x8000U) -#define SYSCON_STARTER_FLEXINT1_SHIFT (15U) -/*! FLEXINT1 - FLEXINT1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT1_SHIFT)) & SYSCON_STARTER_FLEXINT1_MASK) - -#define SYSCON_STARTER_HS_CMP2_IRQ_MASK (0x8000U) -#define SYSCON_STARTER_HS_CMP2_IRQ_SHIFT (15U) -/*! HS_CMP2_IRQ - HS_CMP2 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_HS_CMP2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HS_CMP2_IRQ_SHIFT)) & SYSCON_STARTER_HS_CMP2_IRQ_MASK) - -#define SYSCON_STARTER_CSSV2_ERR_MASK (0x10000U) -#define SYSCON_STARTER_CSSV2_ERR_SHIFT (16U) -/*! CSSV2_ERR - CSSv2 error interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CSSV2_ERR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CSSV2_ERR_SHIFT)) & SYSCON_STARTER_CSSV2_ERR_MASK) - -#define SYSCON_STARTER_FLEXINT2_MASK (0x10000U) -#define SYSCON_STARTER_FLEXINT2_SHIFT (16U) -/*! FLEXINT2 - FLEXINT2 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT2_SHIFT)) & SYSCON_STARTER_FLEXINT2_MASK) - -#define SYSCON_STARTER_FLEXPWM0_CAPTURE_IRQ_MASK (0x10000U) -#define SYSCON_STARTER_FLEXPWM0_CAPTURE_IRQ_SHIFT (16U) -/*! FLEXPWM0_CAPTURE_IRQ - FlexPWM0 capture interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM0_CAPTURE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_CAPTURE_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_CAPTURE_IRQ_MASK) - -#define SYSCON_STARTER_FLEXINT3_MASK (0x20000U) -#define SYSCON_STARTER_FLEXINT3_SHIFT (17U) -/*! FLEXINT3 - FLEXINT3 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT3_SHIFT)) & SYSCON_STARTER_FLEXINT3_MASK) - -#define SYSCON_STARTER_FLEXPWM0_FAULT_IRQ_MASK (0x20000U) -#define SYSCON_STARTER_FLEXPWM0_FAULT_IRQ_SHIFT (17U) -/*! FLEXPWM0_FAULT_IRQ - FlexPWM0 fault interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM0_FAULT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_FAULT_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_FAULT_IRQ_MASK) - -#define SYSCON_STARTER_PKC_ERR_IRQ_MASK (0x20000U) -#define SYSCON_STARTER_PKC_ERR_IRQ_SHIFT (17U) -/*! PKC_ERR_IRQ - PKC error interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PKC_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PKC_ERR_IRQ_SHIFT)) & SYSCON_STARTER_PKC_ERR_IRQ_MASK) - -#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK (0x20000U) -#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT (17U) -/*! SEC_HYPERVISOR_CALL - SEC_HYPERVISOR_CALL interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SEC_HYPERVISOR_CALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT)) & SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK) - -#define SYSCON_STARTER_FLEXINT4_MASK (0x40000U) -#define SYSCON_STARTER_FLEXINT4_SHIFT (18U) -/*! FLEXINT4 - FLEXINT4 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT4_SHIFT)) & SYSCON_STARTER_FLEXINT4_MASK) - -#define SYSCON_STARTER_FLEXPWM0_RELOAD_ERR_IRQ_MASK (0x40000U) -#define SYSCON_STARTER_FLEXPWM0_RELOAD_ERR_IRQ_SHIFT (18U) -/*! FLEXPWM0_RELOAD_ERR_IRQ - FlexPWM0 reload error interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM0_RELOAD_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_RELOAD_ERR_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_RELOAD_ERR_IRQ_MASK) - -#define SYSCON_STARTER_PVTVF0_AMBER_IRQ_MASK (0x40000U) -#define SYSCON_STARTER_PVTVF0_AMBER_IRQ_SHIFT (18U) -/*! PVTVF0_AMBER_IRQ - PVTVF0 amber interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PVTVF0_AMBER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PVTVF0_AMBER_IRQ_SHIFT)) & SYSCON_STARTER_PVTVF0_AMBER_IRQ_MASK) - -#define SYSCON_STARTER_SEC_GPIO_INT00_MASK (0x40000U) -#define SYSCON_STARTER_SEC_GPIO_INT00_SHIFT (18U) -/*! SEC_GPIO_INT00 - SEC_GPIO_INT00 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SEC_GPIO_INT00(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT00_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT00_MASK) - -#define SYSCON_STARTER_FLEXINT5_MASK (0x80000U) -#define SYSCON_STARTER_FLEXINT5_SHIFT (19U) -/*! FLEXINT5 - FLEXINT5 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT5_SHIFT)) & SYSCON_STARTER_FLEXINT5_MASK) - -#define SYSCON_STARTER_FLEXPWM0_COMPARE0_IRQ_MASK (0x80000U) -#define SYSCON_STARTER_FLEXPWM0_COMPARE0_IRQ_SHIFT (19U) -/*! FLEXPWM0_COMPARE0_IRQ - FlexPWM0 compare interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM0_COMPARE0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_COMPARE0_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_COMPARE0_IRQ_MASK) - -#define SYSCON_STARTER_PVTVF0_RED_IRQ_MASK (0x80000U) -#define SYSCON_STARTER_PVTVF0_RED_IRQ_SHIFT (19U) -/*! PVTVF0_RED_IRQ - PVTVF0 red interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PVTVF0_RED_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PVTVF0_RED_IRQ_SHIFT)) & SYSCON_STARTER_PVTVF0_RED_IRQ_MASK) - -#define SYSCON_STARTER_SEC_GPIO_INT01_MASK (0x80000U) -#define SYSCON_STARTER_SEC_GPIO_INT01_SHIFT (19U) -/*! SEC_GPIO_INT01 - SEC_GPIO_INT01 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SEC_GPIO_INT01(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT01_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT01_MASK) - -#define SYSCON_STARTER_FLEXINT6_MASK (0x100000U) -#define SYSCON_STARTER_FLEXINT6_SHIFT (20U) -/*! FLEXINT6 - FLEXINT6 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT6_SHIFT)) & SYSCON_STARTER_FLEXINT6_MASK) - -#define SYSCON_STARTER_FLEXPWM0_RELOAD0_IRQ_MASK (0x100000U) -#define SYSCON_STARTER_FLEXPWM0_RELOAD0_IRQ_SHIFT (20U) -/*! FLEXPWM0_RELOAD0_IRQ - FlexPWM0 reload interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM0_RELOAD0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_RELOAD0_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_RELOAD0_IRQ_MASK) - -#define SYSCON_STARTER_FREQ_ME_PLUS_MASK (0x100000U) -#define SYSCON_STARTER_FREQ_ME_PLUS_SHIFT (20U) -/*! FREQ_ME_PLUS - FREQME interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FREQ_ME_PLUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FREQ_ME_PLUS_SHIFT)) & SYSCON_STARTER_FREQ_ME_PLUS_MASK) - -#define SYSCON_STARTER_PVTVF1_AMBER_IRQ_MASK (0x100000U) -#define SYSCON_STARTER_PVTVF1_AMBER_IRQ_SHIFT (20U) -/*! PVTVF1_AMBER_IRQ - PVTVF1 amber interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PVTVF1_AMBER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PVTVF1_AMBER_IRQ_SHIFT)) & SYSCON_STARTER_PVTVF1_AMBER_IRQ_MASK) - -#define SYSCON_STARTER_FLEXINT7_MASK (0x200000U) -#define SYSCON_STARTER_FLEXINT7_SHIFT (21U) -/*! FLEXINT7 - FLEXINT7 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT7_SHIFT)) & SYSCON_STARTER_FLEXINT7_MASK) - -#define SYSCON_STARTER_FLEXPWM0_COMPARE1_IRQ_MASK (0x200000U) -#define SYSCON_STARTER_FLEXPWM0_COMPARE1_IRQ_SHIFT (21U) -/*! FLEXPWM0_COMPARE1_IRQ - FlexPWM0 compare interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM0_COMPARE1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_COMPARE1_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_COMPARE1_IRQ_MASK) - -#define SYSCON_STARTER_PVTVF1_RED_IRQ_MASK (0x200000U) -#define SYSCON_STARTER_PVTVF1_RED_IRQ_SHIFT (21U) -/*! PVTVF1_RED_IRQ - PVTVF1 red interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PVTVF1_RED_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PVTVF1_RED_IRQ_SHIFT)) & SYSCON_STARTER_PVTVF1_RED_IRQ_MASK) - -#define SYSCON_STARTER_SEC_VIO_MASK (0x200000U) -#define SYSCON_STARTER_SEC_VIO_SHIFT (21U) -/*! SEC_VIO - SEC_VIO interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_VIO_SHIFT)) & SYSCON_STARTER_SEC_VIO_MASK) - -#define SYSCON_STARTER_ADC0_MASK (0x400000U) -#define SYSCON_STARTER_ADC0_SHIFT (22U) -/*! ADC0 - ADC0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SHIFT)) & SYSCON_STARTER_ADC0_MASK) - -#define SYSCON_STARTER_FLEXPWM0_RELOAD1_IRQ_MASK (0x400000U) -#define SYSCON_STARTER_FLEXPWM0_RELOAD1_IRQ_SHIFT (22U) -/*! FLEXPWM0_RELOAD1_IRQ - FlexPWM0 reload interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM0_RELOAD1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_RELOAD1_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_RELOAD1_IRQ_MASK) - -#define SYSCON_STARTER_SHA_MASK (0x400000U) -#define SYSCON_STARTER_SHA_SHIFT (22U) -/*! SHA - SHA interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SHA_SHIFT)) & SYSCON_STARTER_SHA_MASK) - -#define SYSCON_STARTER_ADC1_MASK (0x800000U) -#define SYSCON_STARTER_ADC1_SHIFT (23U) -/*! ADC1 - ADC1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC1_SHIFT)) & SYSCON_STARTER_ADC1_MASK) - -#define SYSCON_STARTER_FLEXPWM0_COMPARE2_IRQ_MASK (0x800000U) -#define SYSCON_STARTER_FLEXPWM0_COMPARE2_IRQ_SHIFT (23U) -/*! FLEXPWM0_COMPARE2_IRQ - FlexPWM0 compare interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM0_COMPARE2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_COMPARE2_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_COMPARE2_IRQ_MASK) - -#define SYSCON_STARTER_PKC_MASK (0x800000U) -#define SYSCON_STARTER_PKC_SHIFT (23U) -/*! PKC - PKC interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PKC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PKC_SHIFT)) & SYSCON_STARTER_PKC_MASK) - -#define SYSCON_STARTER_ACMP_OVR_MASK (0x1000000U) -#define SYSCON_STARTER_ACMP_OVR_SHIFT (24U) -/*! ACMP_OVR - ACMP_OVR interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_ACMP_OVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ACMP_OVR_SHIFT)) & SYSCON_STARTER_ACMP_OVR_MASK) - -#define SYSCON_STARTER_FLEXPWM0_RELOAD2_IRQ_MASK (0x1000000U) -#define SYSCON_STARTER_FLEXPWM0_RELOAD2_IRQ_SHIFT (24U) -/*! FLEXPWM0_RELOAD2_IRQ - FlexPWM0 reload interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM0_RELOAD2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_RELOAD2_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_RELOAD2_IRQ_MASK) - -#define SYSCON_STARTER_QDDKEY_MASK (0x1000000U) -#define SYSCON_STARTER_QDDKEY_SHIFT (24U) -/*! QDDKEY - QDDKEY interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_QDDKEY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_QDDKEY_SHIFT)) & SYSCON_STARTER_QDDKEY_MASK) - -#define SYSCON_STARTER_DMIC_MASK (0x2000000U) -#define SYSCON_STARTER_DMIC_SHIFT (25U) -/*! DMIC - DMIC interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMIC_SHIFT)) & SYSCON_STARTER_DMIC_MASK) - -#define SYSCON_STARTER_FLEXPWM0_COMPARE3_IRQ_MASK (0x2000000U) -#define SYSCON_STARTER_FLEXPWM0_COMPARE3_IRQ_SHIFT (25U) -/*! FLEXPWM0_COMPARE3_IRQ - FlexPWM0 compare interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM0_COMPARE3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_COMPARE3_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_COMPARE3_IRQ_MASK) - -#define SYSCON_STARTER_PQ_MASK (0x2000000U) -#define SYSCON_STARTER_PQ_SHIFT (25U) -/*! PQ - PQ interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PQ_SHIFT)) & SYSCON_STARTER_PQ_MASK) - -#define SYSCON_STARTER_FLEXPWM0_RELOAD3_IRQ_MASK (0x4000000U) -#define SYSCON_STARTER_FLEXPWM0_RELOAD3_IRQ_SHIFT (26U) -/*! FLEXPWM0_RELOAD3_IRQ - FlexPWM0 reload interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM0_RELOAD3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_RELOAD3_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_RELOAD3_IRQ_MASK) - -#define SYSCON_STARTER_SDMA1_MASK (0x4000000U) -#define SYSCON_STARTER_SDMA1_SHIFT (26U) -/*! SDMA1 - SDMA1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA1_SHIFT)) & SYSCON_STARTER_SDMA1_MASK) - -#define SYSCON_STARTER_FLEXPWM1_CAPTURE_IRQ_MASK (0x8000000U) -#define SYSCON_STARTER_FLEXPWM1_CAPTURE_IRQ_SHIFT (27U) -/*! FLEXPWM1_CAPTURE_IRQ - FlexPWM1 capture interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM1_CAPTURE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_CAPTURE_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_CAPTURE_IRQ_MASK) - -#define SYSCON_STARTER_SPI_HS_MASK (0x8000000U) -#define SYSCON_STARTER_SPI_HS_SHIFT (27U) -/*! SPI_HS - SPI_HS interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SPI_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SPI_HS_SHIFT)) & SYSCON_STARTER_SPI_HS_MASK) - -#define SYSCON_STARTER_USB0_NEEDCLK_MASK (0x8000000U) -#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT (27U) -/*! USB0_NEEDCLK - USB0_NEEDCLK interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK) - -#define SYSCON_STARTER_CODE_WDG0_MASK (0x10000000U) -#define SYSCON_STARTER_CODE_WDG0_SHIFT (28U) -/*! CODE_WDG0 - CODE WDG0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CODE_WDG0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CODE_WDG0_SHIFT)) & SYSCON_STARTER_CODE_WDG0_MASK) - -#define SYSCON_STARTER_FLEXPWM1_FAULT_IRQ_MASK (0x10000000U) -#define SYSCON_STARTER_FLEXPWM1_FAULT_IRQ_SHIFT (28U) -/*! FLEXPWM1_FAULT_IRQ - FlexPWM1 fault interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM1_FAULT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_FAULT_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_FAULT_IRQ_MASK) - -#define SYSCON_STARTER_USB0_MASK (0x10000000U) -#define SYSCON_STARTER_USB0_SHIFT (28U) -/*! USB0 - USB0-FS interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK) - -#define SYSCON_STARTER_FLEXPWM1_RELOAD_ERR_IRQ_MASK (0x20000000U) -#define SYSCON_STARTER_FLEXPWM1_RELOAD_ERR_IRQ_SHIFT (29U) -/*! FLEXPWM1_RELOAD_ERR_IRQ - FlexPWM1 reload error interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM1_RELOAD_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_RELOAD_ERR_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_RELOAD_ERR_IRQ_MASK) - -#define SYSCON_STARTER_RTC_LITE0_MASK (0x20000000U) -#define SYSCON_STARTER_RTC_LITE0_SHIFT (29U) -/*! RTC_LITE0 - RTC_LITE0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_RTC_LITE0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_LITE0_SHIFT)) & SYSCON_STARTER_RTC_LITE0_MASK) - -#define SYSCON_STARTER_EZH_ARCH_B0_MASK (0x40000000U) -#define SYSCON_STARTER_EZH_ARCH_B0_SHIFT (30U) -/*! EZH_ARCH_B0 - EZH_ARCH_B0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_EZH_ARCH_B0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_EZH_ARCH_B0_SHIFT)) & SYSCON_STARTER_EZH_ARCH_B0_MASK) - -#define SYSCON_STARTER_FLEXPWM1_COMPARE0_IRQ_MASK (0x40000000U) -#define SYSCON_STARTER_FLEXPWM1_COMPARE0_IRQ_SHIFT (30U) -/*! FLEXPWM1_COMPARE0_IRQ - FlexPWM1 compare interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM1_COMPARE0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_COMPARE0_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_COMPARE0_IRQ_MASK) - -#define SYSCON_STARTER_I3C0_MASK (0x40000000U) -#define SYSCON_STARTER_I3C0_SHIFT (30U) -/*! I3C0 - I3C0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_I3C0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_I3C0_SHIFT)) & SYSCON_STARTER_I3C0_MASK) - -#define SYSCON_STARTER_FLEXPWM1_RELOAD0_IRQ_MASK (0x80000000U) -#define SYSCON_STARTER_FLEXPWM1_RELOAD0_IRQ_SHIFT (31U) -/*! FLEXPWM1_RELOAD0_IRQ - FlexPWM1 reload interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXPWM1_RELOAD0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_RELOAD0_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_RELOAD0_IRQ_MASK) - -#define SYSCON_STARTER_WAKEUP_MAILBOX0_MASK (0x80000000U) -#define SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT (31U) -/*! WAKEUP_MAILBOX0 - WAKEUP_MAILBOX0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_WAKEUP_MAILBOX0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT)) & SYSCON_STARTER_WAKEUP_MAILBOX0_MASK) -/*! @} */ - -/* The count of SYSCON_STARTER */ -#define SYSCON_STARTER_COUNT (4U) - -/*! @name STARTERSET - Set bits in STARTER */ -/*! @{ */ - -#define SYSCON_STARTERSET_FLEXPWM1_COMPARE1_SET_MASK (0x1U) -#define SYSCON_STARTERSET_FLEXPWM1_COMPARE1_SET_SHIFT (0U) -/*! FLEXPWM1_COMPARE1_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. - */ -#define SYSCON_STARTERSET_FLEXPWM1_COMPARE1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_COMPARE1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_COMPARE1_SET_MASK) - -#define SYSCON_STARTERSET_GPIO_INT04_SET_MASK (0x1U) -#define SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT (0U) -/*! GPIO_INT04_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERSET_GPIO_INT04_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT04_SET_MASK) - -#define SYSCON_STARTERSET_SYS_SET_MASK (0x1U) -#define SYSCON_STARTERSET_SYS_SET_SHIFT (0U) -/*! SYS_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_SYS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SYS_SET_SHIFT)) & SYSCON_STARTERSET_SYS_SET_MASK) - -#define SYSCON_STARTERSET_CSS_SET_MASK (0x2U) -#define SYSCON_STARTERSET_CSS_SET_SHIFT (1U) -/*! CSS_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_CSS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CSS_SET_SHIFT)) & SYSCON_STARTERSET_CSS_SET_MASK) - -#define SYSCON_STARTERSET_FLEXPWM1_RELOAD1_SET_MASK (0x2U) -#define SYSCON_STARTERSET_FLEXPWM1_RELOAD1_SET_SHIFT (1U) -/*! FLEXPWM1_RELOAD1_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. - */ -#define SYSCON_STARTERSET_FLEXPWM1_RELOAD1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_RELOAD1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_RELOAD1_SET_MASK) - -#define SYSCON_STARTERSET_GPIO_INT05_SET_MASK (0x2U) -#define SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT (1U) -/*! GPIO_INT05_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERSET_GPIO_INT05_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT05_SET_MASK) - -#define SYSCON_STARTERSET_SDMA0_SET_MASK (0x2U) -#define SYSCON_STARTERSET_SDMA0_SET_SHIFT (1U) -/*! SDMA0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_SDMA0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA0_SET_SHIFT)) & SYSCON_STARTERSET_SDMA0_SET_MASK) - -#define SYSCON_STARTERSET_FLEXPWM1_COMPARE2_SET_MASK (0x4U) -#define SYSCON_STARTERSET_FLEXPWM1_COMPARE2_SET_SHIFT (2U) -/*! FLEXPWM1_COMPARE2_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. - */ -#define SYSCON_STARTERSET_FLEXPWM1_COMPARE2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_COMPARE2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_COMPARE2_SET_MASK) - -#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK (0x4U) -#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT (2U) -/*! GPIO_GLOBALINT0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK) - -#define SYSCON_STARTERSET_GPIO_INT06_SET_MASK (0x4U) -#define SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT (2U) -/*! GPIO_INT06_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERSET_GPIO_INT06_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT06_SET_MASK) - -#define SYSCON_STARTERSET_TAMPER_SET_MASK (0x4U) -#define SYSCON_STARTERSET_TAMPER_SET_SHIFT (2U) -/*! TAMPER_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_TAMPER_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_TAMPER_SET_SHIFT)) & SYSCON_STARTERSET_TAMPER_SET_MASK) - -#define SYSCON_STARTERSET_FLEXPWM1_RELOAD2_SET_MASK (0x8U) -#define SYSCON_STARTERSET_FLEXPWM1_RELOAD2_SET_SHIFT (3U) -/*! FLEXPWM1_RELOAD2_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. - */ -#define SYSCON_STARTERSET_FLEXPWM1_RELOAD2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_RELOAD2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_RELOAD2_SET_MASK) - -#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK (0x8U) -#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT (3U) -/*! GPIO_GLOBALINT1_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK) - -#define SYSCON_STARTERSET_GPIO_INT07_SET_MASK (0x8U) -#define SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT (3U) -/*! GPIO_INT07_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERSET_GPIO_INT07_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT07_SET_MASK) - -#define SYSCON_STARTERSET_CTIMER2_SET_MASK (0x10U) -#define SYSCON_STARTERSET_CTIMER2_SET_SHIFT (4U) -/*! CTIMER2_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERSET_CTIMER2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER2_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER2_SET_MASK) - -#define SYSCON_STARTERSET_FLEXPWM1_COMPARE3_SET_MASK (0x10U) -#define SYSCON_STARTERSET_FLEXPWM1_COMPARE3_SET_SHIFT (4U) -/*! FLEXPWM1_COMPARE3_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. - */ -#define SYSCON_STARTERSET_FLEXPWM1_COMPARE3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_COMPARE3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_COMPARE3_SET_MASK) - -#define SYSCON_STARTERSET_GPIO_INT00_SET_MASK (0x10U) -#define SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT (4U) -/*! GPIO_INT00_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_GPIO_INT00_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT00_SET_MASK) - -#define SYSCON_STARTERSET_CTIMER4_SET_MASK (0x20U) -#define SYSCON_STARTERSET_CTIMER4_SET_SHIFT (5U) -/*! CTIMER4_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERSET_CTIMER4_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER4_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER4_SET_MASK) - -#define SYSCON_STARTERSET_FLEXPWM1_RELOAD3_SET_MASK (0x20U) -#define SYSCON_STARTERSET_FLEXPWM1_RELOAD3_SET_SHIFT (5U) -/*! FLEXPWM1_RELOAD3_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. - */ -#define SYSCON_STARTERSET_FLEXPWM1_RELOAD3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_RELOAD3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_RELOAD3_SET_MASK) - -#define SYSCON_STARTERSET_GPIO_INT01_SET_MASK (0x20U) -#define SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT (5U) -/*! GPIO_INT01_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_GPIO_INT01_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT01_SET_MASK) - -#define SYSCON_STARTERSET_ENC0_COMPARE_SET_MASK (0x40U) -#define SYSCON_STARTERSET_ENC0_COMPARE_SET_SHIFT (6U) -/*! ENC0_COMPARE_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. - */ -#define SYSCON_STARTERSET_ENC0_COMPARE_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC0_COMPARE_SET_SHIFT)) & SYSCON_STARTERSET_ENC0_COMPARE_SET_MASK) - -#define SYSCON_STARTERSET_GPIO_INT02_SET_MASK (0x40U) -#define SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT (6U) -/*! GPIO_INT02_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_GPIO_INT02_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT02_SET_MASK) - -#define SYSCON_STARTERSET_OS_EVENT_SET_MASK (0x40U) -#define SYSCON_STARTERSET_OS_EVENT_SET_SHIFT (6U) -/*! OS_EVENT_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERSET_OS_EVENT_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_OS_EVENT_SET_SHIFT)) & SYSCON_STARTERSET_OS_EVENT_SET_MASK) - -#define SYSCON_STARTERSET_ENC0_HOME_SET_MASK (0x80U) -#define SYSCON_STARTERSET_ENC0_HOME_SET_SHIFT (7U) -/*! ENC0_HOME_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. - */ -#define SYSCON_STARTERSET_ENC0_HOME_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC0_HOME_SET_SHIFT)) & SYSCON_STARTERSET_ENC0_HOME_SET_MASK) - -#define SYSCON_STARTERSET_GPIO_INT03_SET_MASK (0x80U) -#define SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT (7U) -/*! GPIO_INT03_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_GPIO_INT03_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT03_SET_MASK) - -#define SYSCON_STARTERSET_ENC0_WDG_SET_MASK (0x100U) -#define SYSCON_STARTERSET_ENC0_WDG_SET_SHIFT (8U) -/*! ENC0_WDG_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. - */ -#define SYSCON_STARTERSET_ENC0_WDG_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC0_WDG_SET_SHIFT)) & SYSCON_STARTERSET_ENC0_WDG_SET_MASK) - -#define SYSCON_STARTERSET_UTICK0_SET_MASK (0x100U) -#define SYSCON_STARTERSET_UTICK0_SET_SHIFT (8U) -/*! UTICK0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_UTICK0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_UTICK0_SET_SHIFT)) & SYSCON_STARTERSET_UTICK0_SET_MASK) - -#define SYSCON_STARTERSET_ENC0_IDX_SET_MASK (0x200U) -#define SYSCON_STARTERSET_ENC0_IDX_SET_SHIFT (9U) -/*! ENC0_IDX_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. - */ -#define SYSCON_STARTERSET_ENC0_IDX_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC0_IDX_SET_SHIFT)) & SYSCON_STARTERSET_ENC0_IDX_SET_MASK) - -#define SYSCON_STARTERSET_MRT0_SET_MASK (0x200U) -#define SYSCON_STARTERSET_MRT0_SET_SHIFT (9U) -/*! MRT0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_MRT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_MRT0_SET_SHIFT)) & SYSCON_STARTERSET_MRT0_SET_MASK) - -#define SYSCON_STARTERSET_CTIMER0_SET_MASK (0x400U) -#define SYSCON_STARTERSET_CTIMER0_SET_SHIFT (10U) -/*! CTIMER0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_CTIMER0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER0_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER0_SET_MASK) - -#define SYSCON_STARTERSET_DAC0_SET_MASK (0x400U) -#define SYSCON_STARTERSET_DAC0_SET_SHIFT (10U) -/*! DAC0_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_DAC0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_DAC0_SET_SHIFT)) & SYSCON_STARTERSET_DAC0_SET_MASK) - -#define SYSCON_STARTERSET_ENC1_COMPARE_SET_MASK (0x400U) -#define SYSCON_STARTERSET_ENC1_COMPARE_SET_SHIFT (10U) -/*! ENC1_COMPARE_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. - */ -#define SYSCON_STARTERSET_ENC1_COMPARE_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC1_COMPARE_SET_SHIFT)) & SYSCON_STARTERSET_ENC1_COMPARE_SET_MASK) - -#define SYSCON_STARTERSET_CTIMER1_SET_MASK (0x800U) -#define SYSCON_STARTERSET_CTIMER1_SET_SHIFT (11U) -/*! CTIMER1_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_CTIMER1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER1_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER1_SET_MASK) - -#define SYSCON_STARTERSET_DAC1_SET_MASK (0x800U) -#define SYSCON_STARTERSET_DAC1_SET_SHIFT (11U) -/*! DAC1_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_DAC1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_DAC1_SET_SHIFT)) & SYSCON_STARTERSET_DAC1_SET_MASK) - -#define SYSCON_STARTERSET_ENC1_HOME_SET_MASK (0x800U) -#define SYSCON_STARTERSET_ENC1_HOME_SET_SHIFT (11U) -/*! ENC1_HOME_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. - */ -#define SYSCON_STARTERSET_ENC1_HOME_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC1_HOME_SET_SHIFT)) & SYSCON_STARTERSET_ENC1_HOME_SET_MASK) - -#define SYSCON_STARTERSET_DAC2_SET_MASK (0x1000U) -#define SYSCON_STARTERSET_DAC2_SET_SHIFT (12U) -/*! DAC2_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_DAC2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_DAC2_SET_SHIFT)) & SYSCON_STARTERSET_DAC2_SET_MASK) - -#define SYSCON_STARTERSET_ENC1_WDG_SET_MASK (0x1000U) -#define SYSCON_STARTERSET_ENC1_WDG_SET_SHIFT (12U) -/*! ENC1_WDG_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. - */ -#define SYSCON_STARTERSET_ENC1_WDG_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC1_WDG_SET_SHIFT)) & SYSCON_STARTERSET_ENC1_WDG_SET_MASK) - -#define SYSCON_STARTERSET_SCT0_SET_MASK (0x1000U) -#define SYSCON_STARTERSET_SCT0_SET_SHIFT (12U) -/*! SCT0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_SCT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SCT0_SET_SHIFT)) & SYSCON_STARTERSET_SCT0_SET_MASK) - -#define SYSCON_STARTERSET_CTIMER3_SET_MASK (0x2000U) -#define SYSCON_STARTERSET_CTIMER3_SET_SHIFT (13U) -/*! CTIMER3_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_CTIMER3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER3_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER3_SET_MASK) - -#define SYSCON_STARTERSET_ENC1_IDX_SET_MASK (0x2000U) -#define SYSCON_STARTERSET_ENC1_IDX_SET_SHIFT (13U) -/*! ENC1_IDX_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. - */ -#define SYSCON_STARTERSET_ENC1_IDX_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC1_IDX_SET_SHIFT)) & SYSCON_STARTERSET_ENC1_IDX_SET_MASK) - -#define SYSCON_STARTERSET_HS_CMP0_SET_MASK (0x2000U) -#define SYSCON_STARTERSET_HS_CMP0_SET_SHIFT (13U) -/*! HS_CMP0_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_HS_CMP0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_HS_CMP0_SET_SHIFT)) & SYSCON_STARTERSET_HS_CMP0_SET_MASK) - -#define SYSCON_STARTERSET_FLEXINT0_SET_MASK (0x4000U) -#define SYSCON_STARTERSET_FLEXINT0_SET_SHIFT (14U) -/*! FLEXINT0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_FLEXINT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT0_SET_MASK) - -#define SYSCON_STARTERSET_HS_CMP1_SET_MASK (0x4000U) -#define SYSCON_STARTERSET_HS_CMP1_SET_SHIFT (14U) -/*! HS_CMP1_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_HS_CMP1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_HS_CMP1_SET_SHIFT)) & SYSCON_STARTERSET_HS_CMP1_SET_MASK) - -#define SYSCON_STARTERSET_ITRC_SET_MASK (0x4000U) -#define SYSCON_STARTERSET_ITRC_SET_SHIFT (14U) -/*! ITRC_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. - */ -#define SYSCON_STARTERSET_ITRC_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ITRC_SET_SHIFT)) & SYSCON_STARTERSET_ITRC_SET_MASK) - -#define SYSCON_STARTERSET_FLEXINT1_SET_MASK (0x8000U) -#define SYSCON_STARTERSET_FLEXINT1_SET_SHIFT (15U) -/*! FLEXINT1_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_FLEXINT1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT1_SET_MASK) - -#define SYSCON_STARTERSET_HS_CMP2_SET_MASK (0x8000U) -#define SYSCON_STARTERSET_HS_CMP2_SET_SHIFT (15U) -/*! HS_CMP2_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_HS_CMP2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_HS_CMP2_SET_SHIFT)) & SYSCON_STARTERSET_HS_CMP2_SET_MASK) - -#define SYSCON_STARTERSET_CSSV2_ERR_SET_MASK (0x10000U) -#define SYSCON_STARTERSET_CSSV2_ERR_SET_SHIFT (16U) -/*! CSSV2_ERR_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. - */ -#define SYSCON_STARTERSET_CSSV2_ERR_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CSSV2_ERR_SET_SHIFT)) & SYSCON_STARTERSET_CSSV2_ERR_SET_MASK) - -#define SYSCON_STARTERSET_FLEXINT2_SET_MASK (0x10000U) -#define SYSCON_STARTERSET_FLEXINT2_SET_SHIFT (16U) -/*! FLEXINT2_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_FLEXINT2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT2_SET_MASK) - -#define SYSCON_STARTERSET_FLEXPWM0_CAPTURE_SET_MASK (0x10000U) -#define SYSCON_STARTERSET_FLEXPWM0_CAPTURE_SET_SHIFT (16U) -/*! FLEXPWM0_CAPTURE_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_FLEXPWM0_CAPTURE_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_CAPTURE_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_CAPTURE_SET_MASK) - -#define SYSCON_STARTERSET_FLEXINT3_SET_MASK (0x20000U) -#define SYSCON_STARTERSET_FLEXINT3_SET_SHIFT (17U) -/*! FLEXINT3_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_FLEXINT3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT3_SET_MASK) - -#define SYSCON_STARTERSET_FLEXPWM0_FAULT_SET_MASK (0x20000U) -#define SYSCON_STARTERSET_FLEXPWM0_FAULT_SET_SHIFT (17U) -/*! FLEXPWM0_FAULT_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_FLEXPWM0_FAULT_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_FAULT_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_FAULT_SET_MASK) - -#define SYSCON_STARTERSET_PKC_ERR_SET_MASK (0x20000U) -#define SYSCON_STARTERSET_PKC_ERR_SET_SHIFT (17U) -/*! PKC_ERR_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. - */ -#define SYSCON_STARTERSET_PKC_ERR_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PKC_ERR_SET_SHIFT)) & SYSCON_STARTERSET_PKC_ERR_SET_MASK) - -#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK (0x20000U) -#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT (17U) -/*! SEC_HYPERVISOR_CALL_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT)) & SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK) - -#define SYSCON_STARTERSET_FLEXINT4_SET_MASK (0x40000U) -#define SYSCON_STARTERSET_FLEXINT4_SET_SHIFT (18U) -/*! FLEXINT4_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_FLEXINT4_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT4_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT4_SET_MASK) - -#define SYSCON_STARTERSET_FLEXPWM0_RELOAD_ERROR_SET_MASK (0x40000U) -#define SYSCON_STARTERSET_FLEXPWM0_RELOAD_ERROR_SET_SHIFT (18U) -/*! FLEXPWM0_RELOAD_ERROR_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_FLEXPWM0_RELOAD_ERROR_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_RELOAD_ERROR_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_RELOAD_ERROR_SET_MASK) - -#define SYSCON_STARTERSET_PVTVF0_AMBER_SET_MASK (0x40000U) -#define SYSCON_STARTERSET_PVTVF0_AMBER_SET_SHIFT (18U) -/*! PVTVF0_AMBER_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. - */ -#define SYSCON_STARTERSET_PVTVF0_AMBER_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PVTVF0_AMBER_SET_SHIFT)) & SYSCON_STARTERSET_PVTVF0_AMBER_SET_MASK) - -#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK (0x40000U) -#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT (18U) -/*! SEC_GPIO_INT00_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK) - -#define SYSCON_STARTERSET_FLEXINT5_SET_MASK (0x80000U) -#define SYSCON_STARTERSET_FLEXINT5_SET_SHIFT (19U) -/*! FLEXINT5_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_FLEXINT5_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT5_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT5_SET_MASK) - -#define SYSCON_STARTERSET_FLEXPWM0_COMPARE0_SET_MASK (0x80000U) -#define SYSCON_STARTERSET_FLEXPWM0_COMPARE0_SET_SHIFT (19U) -/*! FLEXPWM0_COMPARE0_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_FLEXPWM0_COMPARE0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_COMPARE0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_COMPARE0_SET_MASK) - -#define SYSCON_STARTERSET_PVTVF0_RED_SET_MASK (0x80000U) -#define SYSCON_STARTERSET_PVTVF0_RED_SET_SHIFT (19U) -/*! PVTVF0_RED_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. - */ -#define SYSCON_STARTERSET_PVTVF0_RED_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PVTVF0_RED_SET_SHIFT)) & SYSCON_STARTERSET_PVTVF0_RED_SET_MASK) - -#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK (0x80000U) -#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT (19U) -/*! SEC_GPIO_INT01_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK) - -#define SYSCON_STARTERSET_FLEXINT6_SET_MASK (0x100000U) -#define SYSCON_STARTERSET_FLEXINT6_SET_SHIFT (20U) -/*! FLEXINT6_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_FLEXINT6_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT6_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT6_SET_MASK) - -#define SYSCON_STARTERSET_FLEXPWM0_RELOAD0_SET_MASK (0x100000U) -#define SYSCON_STARTERSET_FLEXPWM0_RELOAD0_SET_SHIFT (20U) -/*! FLEXPWM0_RELOAD0_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_FLEXPWM0_RELOAD0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_RELOAD0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_RELOAD0_SET_MASK) - -#define SYSCON_STARTERSET_PVTVF1_AMBER_SET_MASK (0x100000U) -#define SYSCON_STARTERSET_PVTVF1_AMBER_SET_SHIFT (20U) -/*! PVTVF1_AMBER_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. - */ -#define SYSCON_STARTERSET_PVTVF1_AMBER_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PVTVF1_AMBER_SET_SHIFT)) & SYSCON_STARTERSET_PVTVF1_AMBER_SET_MASK) - -#define SYSCON_STARTERSET_FLEXINT7_SET_MASK (0x200000U) -#define SYSCON_STARTERSET_FLEXINT7_SET_SHIFT (21U) -/*! FLEXINT7_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_FLEXINT7_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT7_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT7_SET_MASK) - -#define SYSCON_STARTERSET_FLEXPWM0_COMPARE1_SET_MASK (0x200000U) -#define SYSCON_STARTERSET_FLEXPWM0_COMPARE1_SET_SHIFT (21U) -/*! FLEXPWM0_COMPARE1_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_FLEXPWM0_COMPARE1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_COMPARE1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_COMPARE1_SET_MASK) - -#define SYSCON_STARTERSET_PVTVF1_RED_SET_MASK (0x200000U) -#define SYSCON_STARTERSET_PVTVF1_RED_SET_SHIFT (21U) -/*! PVTVF1_RED_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. - */ -#define SYSCON_STARTERSET_PVTVF1_RED_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PVTVF1_RED_SET_SHIFT)) & SYSCON_STARTERSET_PVTVF1_RED_SET_MASK) - -#define SYSCON_STARTERSET_ADC0_SET_MASK (0x400000U) -#define SYSCON_STARTERSET_ADC0_SET_SHIFT (22U) -/*! ADC0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_ADC0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_SET_MASK) - -#define SYSCON_STARTERSET_FLEXPWM0_RELOAD1_SET_MASK (0x400000U) -#define SYSCON_STARTERSET_FLEXPWM0_RELOAD1_SET_SHIFT (22U) -/*! FLEXPWM0_RELOAD1_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_FLEXPWM0_RELOAD1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_RELOAD1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_RELOAD1_SET_MASK) - -#define SYSCON_STARTERSET_FLEXPWM0_COMPARE2_SET_MASK (0x800000U) -#define SYSCON_STARTERSET_FLEXPWM0_COMPARE2_SET_SHIFT (23U) -/*! FLEXPWM0_COMPARE2_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_FLEXPWM0_COMPARE2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_COMPARE2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_COMPARE2_SET_MASK) - -#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK (0x1000000U) -#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT (24U) -/*! ADC0_THCMP_OVR_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK) - -#define SYSCON_STARTERSET_FLEXPWM0_RELOAD2_SET_MASK (0x1000000U) -#define SYSCON_STARTERSET_FLEXPWM0_RELOAD2_SET_SHIFT (24U) -/*! FLEXPWM0_RELOAD2_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_FLEXPWM0_RELOAD2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_RELOAD2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_RELOAD2_SET_MASK) - -#define SYSCON_STARTERSET_QDDKEY_SET_MASK (0x1000000U) -#define SYSCON_STARTERSET_QDDKEY_SET_SHIFT (24U) -/*! QDDKEY_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERSET_QDDKEY_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_QDDKEY_SET_SHIFT)) & SYSCON_STARTERSET_QDDKEY_SET_MASK) - -#define SYSCON_STARTERSET_FLEXPWM0_COMPARE3_SET_MASK (0x2000000U) -#define SYSCON_STARTERSET_FLEXPWM0_COMPARE3_SET_SHIFT (25U) -/*! FLEXPWM0_COMPARE3_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_FLEXPWM0_COMPARE3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_COMPARE3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_COMPARE3_SET_MASK) - -#define SYSCON_STARTERSET_PQ_SET_MASK (0x2000000U) -#define SYSCON_STARTERSET_PQ_SET_SHIFT (25U) -/*! PQ_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERSET_PQ_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PQ_SET_SHIFT)) & SYSCON_STARTERSET_PQ_SET_MASK) - -#define SYSCON_STARTERSET_FLEXPWM0_RELOAD3_SET_MASK (0x4000000U) -#define SYSCON_STARTERSET_FLEXPWM0_RELOAD3_SET_SHIFT (26U) -/*! FLEXPWM0_RELOAD3_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_FLEXPWM0_RELOAD3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_RELOAD3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_RELOAD3_SET_MASK) - -#define SYSCON_STARTERSET_SDMA1_SET_MASK (0x4000000U) -#define SYSCON_STARTERSET_SDMA1_SET_SHIFT (26U) -/*! SDMA1_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERSET_SDMA1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA1_SET_SHIFT)) & SYSCON_STARTERSET_SDMA1_SET_MASK) - -#define SYSCON_STARTERSET_FLEXPWM1_CAPTURE_SET_MASK (0x8000000U) -#define SYSCON_STARTERSET_FLEXPWM1_CAPTURE_SET_SHIFT (27U) -/*! FLEXPWM1_CAPTURE_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_FLEXPWM1_CAPTURE_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_CAPTURE_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_CAPTURE_SET_MASK) - -#define SYSCON_STARTERSET_SPI_HS_SET_MASK (0x8000000U) -#define SYSCON_STARTERSET_SPI_HS_SET_SHIFT (27U) -/*! SPI_HS_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERSET_SPI_HS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SPI_HS_SET_SHIFT)) & SYSCON_STARTERSET_SPI_HS_SET_MASK) - -#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK (0x8000000U) -#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT (27U) -/*! USB0_NEEDCLK_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_USB0_NEEDCLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT)) & SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK) - -#define SYSCON_STARTERSET_FLEXPWM1_FAULT_SET_MASK (0x10000000U) -#define SYSCON_STARTERSET_FLEXPWM1_FAULT_SET_SHIFT (28U) -/*! FLEXPWM1_FAULT_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_FLEXPWM1_FAULT_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_FAULT_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_FAULT_SET_MASK) - -#define SYSCON_STARTERSET_USB0_SET_MASK (0x10000000U) -#define SYSCON_STARTERSET_USB0_SET_SHIFT (28U) -/*! USB0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_USB0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_SET_SHIFT)) & SYSCON_STARTERSET_USB0_SET_MASK) - -#define SYSCON_STARTERSET_FLEXPWM1_RELOAD_ERROR_SET_MASK (0x20000000U) -#define SYSCON_STARTERSET_FLEXPWM1_RELOAD_ERROR_SET_SHIFT (29U) -/*! FLEXPWM1_RELOAD_ERROR_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_FLEXPWM1_RELOAD_ERROR_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_RELOAD_ERROR_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_RELOAD_ERROR_SET_MASK) - -#define SYSCON_STARTERSET_RTC_LITE0_SET_MASK (0x20000000U) -#define SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT (29U) -/*! RTC_LITE0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_RTC_LITE0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT)) & SYSCON_STARTERSET_RTC_LITE0_SET_MASK) - -#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK (0x40000000U) -#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT (30U) -/*! EZH_ARCH_B0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_EZH_ARCH_B0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT)) & SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK) - -#define SYSCON_STARTERSET_FLEXPWM1_COMPARE0_SET_MASK (0x40000000U) -#define SYSCON_STARTERSET_FLEXPWM1_COMPARE0_SET_SHIFT (30U) -/*! FLEXPWM1_COMPARE0_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_FLEXPWM1_COMPARE0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_COMPARE0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_COMPARE0_SET_MASK) - -#define SYSCON_STARTERSET_FLEXPWM1_RELOAD0_SET_MASK (0x80000000U) -#define SYSCON_STARTERSET_FLEXPWM1_RELOAD0_SET_SHIFT (31U) -/*! FLEXPWM1_RELOAD0_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. - */ -#define SYSCON_STARTERSET_FLEXPWM1_RELOAD0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_RELOAD0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_RELOAD0_SET_MASK) - -#define SYSCON_STARTERSET_WAKEUPPADS_SET_MASK (0x80000000U) -#define SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT (31U) -/*! WAKEUPPADS_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERSET_WAKEUPPADS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUPPADS_SET_MASK) - -#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK (0x80000000U) -#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT (31U) -/*! WAKEUP_MAILBOX0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK) -/*! @} */ - -/* The count of SYSCON_STARTERSET */ -#define SYSCON_STARTERSET_COUNT (4U) - -/*! @name STARTERCLR - Clear bits in STARTER */ -/*! @{ */ - -#define SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK (0x1U) -#define SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT (0U) -/*! GPIO_INT04_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERCLR_GPIO_INT04_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK) - -#define SYSCON_STARTERCLR_SYS_CLR_MASK (0x1U) -#define SYSCON_STARTERCLR_SYS_CLR_SHIFT (0U) -/*! SYS_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_SYS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SYS_CLR_SHIFT)) & SYSCON_STARTERCLR_SYS_CLR_MASK) - -#define SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK (0x2U) -#define SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT (1U) -/*! GPIO_INT05_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERCLR_GPIO_INT05_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK) - -#define SYSCON_STARTERCLR_SDMA0_CLR_MASK (0x2U) -#define SYSCON_STARTERCLR_SDMA0_CLR_SHIFT (1U) -/*! SDMA0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_SDMA0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA0_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA0_CLR_MASK) - -#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK (0x4U) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT (2U) -/*! GPIO_GLOBALINT0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK) - -#define SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK (0x4U) -#define SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT (2U) -/*! GPIO_INT06_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERCLR_GPIO_INT06_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK) - -#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK (0x8U) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT (3U) -/*! GPIO_GLOBALINT1_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK) - -#define SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK (0x8U) -#define SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT (3U) -/*! GPIO_INT07_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERCLR_GPIO_INT07_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK) - -#define SYSCON_STARTERCLR_CTIMER2_CLR_MASK (0x10U) -#define SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT (4U) -/*! CTIMER2_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERCLR_CTIMER2_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER2_CLR_MASK) - -#define SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK (0x10U) -#define SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT (4U) -/*! GPIO_INT00_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_GPIO_INT00_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK) - -#define SYSCON_STARTERCLR_CTIMER4_CLR_MASK (0x20U) -#define SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT (5U) -/*! CTIMER4_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERCLR_CTIMER4_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER4_CLR_MASK) - -#define SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK (0x20U) -#define SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT (5U) -/*! GPIO_INT01_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_GPIO_INT01_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK) - -#define SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK (0x40U) -#define SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT (6U) -/*! GPIO_INT02_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_GPIO_INT02_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK) - -#define SYSCON_STARTERCLR_OS_EVENT_CLR_MASK (0x40U) -#define SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT (6U) -/*! OS_EVENT_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERCLR_OS_EVENT_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT)) & SYSCON_STARTERCLR_OS_EVENT_CLR_MASK) - -#define SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK (0x80U) -#define SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT (7U) -/*! GPIO_INT03_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_GPIO_INT03_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK) - -#define SYSCON_STARTERCLR_UTICK0_CLR_MASK (0x100U) -#define SYSCON_STARTERCLR_UTICK0_CLR_SHIFT (8U) -/*! UTICK0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_UTICK0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_UTICK0_CLR_SHIFT)) & SYSCON_STARTERCLR_UTICK0_CLR_MASK) - -#define SYSCON_STARTERCLR_MRT0_CLR_MASK (0x200U) -#define SYSCON_STARTERCLR_MRT0_CLR_SHIFT (9U) -/*! MRT0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_MRT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_MRT0_CLR_SHIFT)) & SYSCON_STARTERCLR_MRT0_CLR_MASK) - -#define SYSCON_STARTERCLR_CTIMER0_CLR_MASK (0x400U) -#define SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT (10U) -/*! CTIMER0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_CTIMER0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER0_CLR_MASK) - -#define SYSCON_STARTERCLR_CTIMER1_CLR_MASK (0x800U) -#define SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT (11U) -/*! CTIMER1_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_CTIMER1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER1_CLR_MASK) - -#define SYSCON_STARTERCLR_SCT0_CLR_MASK (0x1000U) -#define SYSCON_STARTERCLR_SCT0_CLR_SHIFT (12U) -/*! SCT0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_SCT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SCT0_CLR_SHIFT)) & SYSCON_STARTERCLR_SCT0_CLR_MASK) - -#define SYSCON_STARTERCLR_CTIMER3_CLR_MASK (0x2000U) -#define SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT (13U) -/*! CTIMER3_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_CTIMER3_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER3_CLR_MASK) - -#define SYSCON_STARTERCLR_FLEXINT0_CLR_MASK (0x4000U) -#define SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT (14U) -/*! FLEXINT0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_FLEXINT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT0_CLR_MASK) - -#define SYSCON_STARTERCLR_FLEXINT1_CLR_MASK (0x8000U) -#define SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT (15U) -/*! FLEXINT1_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_FLEXINT1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT1_CLR_MASK) - -#define SYSCON_STARTERCLR_FLEXINT2_CLR_MASK (0x10000U) -#define SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT (16U) -/*! FLEXINT2_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_FLEXINT2_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT2_CLR_MASK) - -#define SYSCON_STARTERCLR_FLEXINT3_CLR_MASK (0x20000U) -#define SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT (17U) -/*! FLEXINT3_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_FLEXINT3_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT3_CLR_MASK) - -#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK (0x20000U) -#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT (17U) -/*! SEC_HYPERVISOR_CALL_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK) - -#define SYSCON_STARTERCLR_FLEXINT4_CLR_MASK (0x40000U) -#define SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT (18U) -/*! FLEXINT4_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_FLEXINT4_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT4_CLR_MASK) - -#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK (0x40000U) -#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT (18U) -/*! SEC_GPIO_INT00_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK) - -#define SYSCON_STARTERCLR_FLEXINT5_CLR_MASK (0x80000U) -#define SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT (19U) -/*! FLEXINT5_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_FLEXINT5_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT5_CLR_MASK) - -#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK (0x80000U) -#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT (19U) -/*! SEC_GPIO_INT01_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK) - -#define SYSCON_STARTERCLR_FLEXINT6_CLR_MASK (0x100000U) -#define SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT (20U) -/*! FLEXINT6_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_FLEXINT6_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT6_CLR_MASK) - -#define SYSCON_STARTERCLR_FLEXINT7_CLR_MASK (0x200000U) -#define SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT (21U) -/*! FLEXINT7_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_FLEXINT7_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT7_CLR_MASK) - -#define SYSCON_STARTERCLR_ADC0_CLR_MASK (0x400000U) -#define SYSCON_STARTERCLR_ADC0_CLR_SHIFT (22U) -/*! ADC0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_ADC0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_CLR_MASK) - -#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK (0x1000000U) -#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT (24U) -/*! ADC0_THCMP_OVR_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK) - -#define SYSCON_STARTERCLR_QDDKEY_CLR_MASK (0x1000000U) -#define SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT (24U) -/*! QDDKEY_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERCLR_QDDKEY_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT)) & SYSCON_STARTERCLR_QDDKEY_CLR_MASK) - -#define SYSCON_STARTERCLR_PQ_CLR_MASK (0x2000000U) -#define SYSCON_STARTERCLR_PQ_CLR_SHIFT (25U) -/*! PQ_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERCLR_PQ_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_PQ_CLR_SHIFT)) & SYSCON_STARTERCLR_PQ_CLR_MASK) - -#define SYSCON_STARTERCLR_SDMA1_CLR_MASK (0x4000000U) -#define SYSCON_STARTERCLR_SDMA1_CLR_SHIFT (26U) -/*! SDMA1_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERCLR_SDMA1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA1_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA1_CLR_MASK) - -#define SYSCON_STARTERCLR_SPI_HS_CLR_MASK (0x8000000U) -#define SYSCON_STARTERCLR_SPI_HS_CLR_SHIFT (27U) -/*! SPI_HS_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERCLR_SPI_HS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SPI_HS_CLR_SHIFT)) & SYSCON_STARTERCLR_SPI_HS_CLR_MASK) - -#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK (0x8000000U) -#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT (27U) -/*! USB0_NEEDCLK_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK) - -#define SYSCON_STARTERCLR_USB0_CLR_MASK (0x10000000U) -#define SYSCON_STARTERCLR_USB0_CLR_SHIFT (28U) -/*! USB0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_USB0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_CLR_MASK) - -#define SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK (0x20000000U) -#define SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT (29U) -/*! RTC_LITE0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_RTC_LITE0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT)) & SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK) - -#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK (0x40000000U) -#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT (30U) -/*! EZH_ARCH_B0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT)) & SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK) - -#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK (0x80000000U) -#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT (31U) -/*! WAKEUPPADS_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - */ -#define SYSCON_STARTERCLR_WAKEUPPADS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK) - -#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK (0x80000000U) -#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT (31U) -/*! WAKEUP_MAILBOX0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - */ -#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK) -/*! @} */ - -/* The count of SYSCON_STARTERCLR */ -#define SYSCON_STARTERCLR_COUNT (2U) - -/*! @name FUNCRETENTIONCTRL - Functional retention control */ -/*! @{ */ - -#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK (0x1U) -#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT (0U) -/*! FUNCRETENA - functional retention in power down only. - * 0b1..enable functional retention. - * 0b0..disable functional retention. - */ -#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK) - -#define SYSCON_FUNCRETENTIONCTRL_RET_START_MASK (0x3FFEU) -#define SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT (1U) -/*! RET_START - Start address divided by 4 inside SRAMX bank. - */ -#define SYSCON_FUNCRETENTIONCTRL_RET_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_START_MASK) - -#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK (0xFFC000U) -#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT (14U) -/*! RET_LENTH - lenth of Scan chains to save. - */ -#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) -/*! @} */ - -/*! @name HARDWARESLEEP - Hardware Sleep control */ -/*! @{ */ - -#define SYSCON_HARDWARESLEEP_FORCED_MASK (0x1U) -#define SYSCON_HARDWARESLEEP_FORCED_SHIFT (0U) -/*! FORCED - Force peripheral clocking to stay on during Deep Sleep and Power-down modes. - */ -#define SYSCON_HARDWARESLEEP_FORCED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_FORCED_SHIFT)) & SYSCON_HARDWARESLEEP_FORCED_MASK) - -#define SYSCON_HARDWARESLEEP_PERIPHERALS_MASK (0x2U) -#define SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT (1U) -/*! PERIPHERALS - Wake for Flexcomms. - */ -#define SYSCON_HARDWARESLEEP_PERIPHERALS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT)) & SYSCON_HARDWARESLEEP_PERIPHERALS_MASK) - -#define SYSCON_HARDWARESLEEP_DMIC_MASK (0x4U) -#define SYSCON_HARDWARESLEEP_DMIC_SHIFT (2U) -/*! DMIC - Wake for DMIC. - */ -#define SYSCON_HARDWARESLEEP_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_DMIC_SHIFT)) & SYSCON_HARDWARESLEEP_DMIC_MASK) - -#define SYSCON_HARDWARESLEEP_SDMA0_MASK (0x8U) -#define SYSCON_HARDWARESLEEP_SDMA0_SHIFT (3U) -/*! SDMA0 - Wake for DMA0. - */ -#define SYSCON_HARDWARESLEEP_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA0_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA0_MASK) - -#define SYSCON_HARDWARESLEEP_SDMA1_MASK (0x20U) -#define SYSCON_HARDWARESLEEP_SDMA1_SHIFT (5U) -/*! SDMA1 - Wake for DMA1. - */ -#define SYSCON_HARDWARESLEEP_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA1_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA1_MASK) - -#define SYSCON_HARDWARESLEEP_DAC_MASK (0x40U) -#define SYSCON_HARDWARESLEEP_DAC_SHIFT (6U) -/*! DAC - Wake for DAC0/1/2. - */ -#define SYSCON_HARDWARESLEEP_DAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_DAC_SHIFT)) & SYSCON_HARDWARESLEEP_DAC_MASK) - -#define SYSCON_HARDWARESLEEP_HW_ENABLE_FRO192M_MASK (0x80000000U) -#define SYSCON_HARDWARESLEEP_HW_ENABLE_FRO192M_SHIFT (31U) -/*! HW_ENABLE_FRO192M - Set this bit if FRO192M is diabled. - */ -#define SYSCON_HARDWARESLEEP_HW_ENABLE_FRO192M(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_HW_ENABLE_FRO192M_SHIFT)) & SYSCON_HARDWARESLEEP_HW_ENABLE_FRO192M_MASK) -/*! @} */ - -/*! @name CPUSTAT - CPU Status */ -/*! @{ */ - -#define SYSCON_CPUSTAT_CPU0SLEEPING_MASK (0x1U) -#define SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT (0U) -/*! CPU0SLEEPING - The CPU0 sleeping state. - * 0b1..the CPU is sleeping. - * 0b0..the CPU is not sleeping. - */ -#define SYSCON_CPUSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPUSTAT_CPU0SLEEPING_MASK) - -#define SYSCON_CPUSTAT_CPU0LOCKUP_MASK (0x4U) -#define SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT (2U) -/*! CPU0LOCKUP - The CPU0 lockup state. - * 0b1..the CPU is in lockup. - * 0b0..the CPU is not in lockup. - */ -#define SYSCON_CPUSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPUSTAT_CPU0LOCKUP_MASK) -/*! @} */ - -/*! @name LPCAC_CTRL - LPCAC control */ -/*! @{ */ - -#define SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK (0x1U) -#define SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT (0U) -/*! DIS_LPCAC - Disable/enable cache function. Default value is 1. - * 0b0..Enable - * 0b1..Disable - */ -#define SYSCON_LPCAC_CTRL_DIS_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK) - -#define SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK (0x2U) -#define SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT (1U) -/*! CLR_LPCAC - Clear cache function. Default value is 0. - * 0b0..Unclear cache - * 0b1..Clear cache - */ -#define SYSCON_LPCAC_CTRL_CLR_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK) - -#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK (0x4U) -#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT (2U) -/*! FRC_NO_ALLOC - Force no allocation. Default value is 0. - * 0b0..Force allocation - * 0b1..Force no allocation - */ -#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT)) & SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK) - -#define SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK (0x8U) -#define SYSCON_LPCAC_CTRL_PARITY_MISS_EN_SHIFT (3U) -/*! PARITY_MISS_EN - Enable parity miss. Default value is 0. - * 0b0..Disable - * 0b1..Enable parity, miss on parity error - */ -#define SYSCON_LPCAC_CTRL_PARITY_MISS_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_PARITY_MISS_EN_SHIFT)) & SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK) -/*! @} */ - -/*! @name FC32KCLKSEL - Flexcomm 32K clock select */ -/*! @{ */ - -#define SYSCON_FC32KCLKSEL_FC32KCLKSEL_MASK (0x1U) -#define SYSCON_FC32KCLKSEL_FC32KCLKSEL_SHIFT (0U) -/*! FC32KCLKSEL - Flexcomm 32K clock select - * 0b0..FRO32K - * 0b1..XTAL 32K - */ -#define SYSCON_FC32KCLKSEL_FC32KCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FC32KCLKSEL_FC32KCLKSEL_SHIFT)) & SYSCON_FC32KCLKSEL_FC32KCLKSEL_MASK) -/*! @} */ - -/*! @name FRGCLKSEL - FRG Clock Source Select */ -/*! @{ */ - -#define SYSCON_FRGCLKSEL_FRG_SRC_SEL_MASK (0x7U) -#define SYSCON_FRGCLKSEL_FRG_SRC_SEL_SHIFT (0U) -/*! FRG_SRC_SEL - FRG clock source select - * 0b000..main clock - * 0b001..PLL clock - * 0b010..fro_div_hf - * 0b011..None - * 0b100..None - * 0b101..None - * 0b110..None - * 0b111..None - */ -#define SYSCON_FRGCLKSEL_FRG_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_FRG_SRC_SEL_SHIFT)) & SYSCON_FRGCLKSEL_FRG_SRC_SEL_MASK) -/*! @} */ - -/* The count of SYSCON_FRGCLKSEL */ -#define SYSCON_FRGCLKSEL_COUNT (8U) - -/*! @name FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV - Flexcomm clock divider */ -/*! @{ */ - -#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value: - */ -#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_MASK) - -#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_SHIFT (29U) -/*! RESET - Reset - * 0b0..Divider is not reset - * 0b1..Divider is reset - */ -#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_MASK) - -#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_SHIFT (30U) -/*! HALT - Reset - * 0b0..Divider clock is running - * 0b1..Divider clock has stopped - */ -#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_MASK) - -#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Reset - * 0b0..Divider clock is stable - * 0b1..Clock frequency is not stable - */ -#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_REQFLAG_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_REQFLAG_MASK) -/*! @} */ - -/* The count of SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV */ -#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_COUNT (8U) - -/*! @name CSS_TEMPORAL_STATE - CSS temporal state */ -/*! @{ */ - -#define SYSCON_CSS_TEMPORAL_STATE_TEMPORAL_STATE_MASK (0xFU) -#define SYSCON_CSS_TEMPORAL_STATE_TEMPORAL_STATE_SHIFT (0U) -/*! TEMPORAL_STATE - Temporal state - */ -#define SYSCON_CSS_TEMPORAL_STATE_TEMPORAL_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_TEMPORAL_STATE_TEMPORAL_STATE_SHIFT)) & SYSCON_CSS_TEMPORAL_STATE_TEMPORAL_STATE_MASK) -/*! @} */ - -/*! @name CSS_KDF_MASK - Key derivation function mask */ -/*! @{ */ - -#define SYSCON_CSS_KDF_MASK_KDF_MASK_MASK (0xFFFFFFFFU) -#define SYSCON_CSS_KDF_MASK_KDF_MASK_SHIFT (0U) -/*! KDF_MASK - Key derivation function mask. - */ -#define SYSCON_CSS_KDF_MASK_KDF_MASK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_KDF_MASK_KDF_MASK_SHIFT)) & SYSCON_CSS_KDF_MASK_KDF_MASK_MASK) -/*! @} */ - -/*! @name CSS_FEATURE0 - CSS command feature */ -/*! @{ */ - -#define SYSCON_CSS_FEATURE0_CIPHER_MASK (0x3U) -#define SYSCON_CSS_FEATURE0_CIPHER_SHIFT (0U) -/*! CIPHER - Enables CIPHER command. - */ -#define SYSCON_CSS_FEATURE0_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_CIPHER_SHIFT)) & SYSCON_CSS_FEATURE0_CIPHER_MASK) - -#define SYSCON_CSS_FEATURE0_AUTH_CIPHER_MASK (0xCU) -#define SYSCON_CSS_FEATURE0_AUTH_CIPHER_SHIFT (2U) -/*! AUTH_CIPHER - Enables AUTH_CIPHER command. - */ -#define SYSCON_CSS_FEATURE0_AUTH_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_AUTH_CIPHER_SHIFT)) & SYSCON_CSS_FEATURE0_AUTH_CIPHER_MASK) - -#define SYSCON_CSS_FEATURE0_ECSIGN_MASK (0x300U) -#define SYSCON_CSS_FEATURE0_ECSIGN_SHIFT (8U) -/*! ECSIGN - Enables ECSIGN command. - */ -#define SYSCON_CSS_FEATURE0_ECSIGN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_ECSIGN_SHIFT)) & SYSCON_CSS_FEATURE0_ECSIGN_MASK) - -#define SYSCON_CSS_FEATURE0_ECVFY_MASK (0xC00U) -#define SYSCON_CSS_FEATURE0_ECVFY_SHIFT (10U) -/*! ECVFY - Enables ECVFY command. - */ -#define SYSCON_CSS_FEATURE0_ECVFY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_ECVFY_SHIFT)) & SYSCON_CSS_FEATURE0_ECVFY_MASK) - -#define SYSCON_CSS_FEATURE0_ECKXCH_MASK (0x3000U) -#define SYSCON_CSS_FEATURE0_ECKXCH_SHIFT (12U) -/*! ECKXCH - Enables ECKXCH command. - */ -#define SYSCON_CSS_FEATURE0_ECKXCH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_ECKXCH_SHIFT)) & SYSCON_CSS_FEATURE0_ECKXCH_MASK) - -#define SYSCON_CSS_FEATURE0_KEYGEN_MASK (0x30000U) -#define SYSCON_CSS_FEATURE0_KEYGEN_SHIFT (16U) -/*! KEYGEN - Enables KEYGEN command. - */ -#define SYSCON_CSS_FEATURE0_KEYGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_KEYGEN_SHIFT)) & SYSCON_CSS_FEATURE0_KEYGEN_MASK) - -#define SYSCON_CSS_FEATURE0_KEYIN_MASK (0xC0000U) -#define SYSCON_CSS_FEATURE0_KEYIN_SHIFT (18U) -/*! KEYIN - Enables KEYIN command. - */ -#define SYSCON_CSS_FEATURE0_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_KEYIN_SHIFT)) & SYSCON_CSS_FEATURE0_KEYIN_MASK) - -#define SYSCON_CSS_FEATURE0_KEYOUT_MASK (0x300000U) -#define SYSCON_CSS_FEATURE0_KEYOUT_SHIFT (20U) -/*! KEYOUT - Enables KEYOUT command. - */ -#define SYSCON_CSS_FEATURE0_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_KEYOUT_SHIFT)) & SYSCON_CSS_FEATURE0_KEYOUT_MASK) - -#define SYSCON_CSS_FEATURE0_KDELETE_MASK (0xC00000U) -#define SYSCON_CSS_FEATURE0_KDELETE_SHIFT (22U) -/*! KDELETE - Enables KDELETE command. - */ -#define SYSCON_CSS_FEATURE0_KDELETE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_KDELETE_SHIFT)) & SYSCON_CSS_FEATURE0_KDELETE_MASK) -/*! @} */ - -/*! @name CSS_FEATURE1 - CSS command feature */ -/*! @{ */ - -#define SYSCON_CSS_FEATURE1_CKDF_MASK (0x3U) -#define SYSCON_CSS_FEATURE1_CKDF_SHIFT (0U) -/*! CKDF - Enables CKDF command. - */ -#define SYSCON_CSS_FEATURE1_CKDF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_CKDF_SHIFT)) & SYSCON_CSS_FEATURE1_CKDF_MASK) - -#define SYSCON_CSS_FEATURE1_HKDF_MASK (0xCU) -#define SYSCON_CSS_FEATURE1_HKDF_SHIFT (2U) -/*! HKDF - Enables HKDF command. - */ -#define SYSCON_CSS_FEATURE1_HKDF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_HKDF_SHIFT)) & SYSCON_CSS_FEATURE1_HKDF_MASK) - -#define SYSCON_CSS_FEATURE1_TLS_INIT_MASK (0x30U) -#define SYSCON_CSS_FEATURE1_TLS_INIT_SHIFT (4U) -/*! TLS_INIT - Enables TLS_INIT command. - */ -#define SYSCON_CSS_FEATURE1_TLS_INIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_TLS_INIT_SHIFT)) & SYSCON_CSS_FEATURE1_TLS_INIT_MASK) - -#define SYSCON_CSS_FEATURE1_HASH_MASK (0x300U) -#define SYSCON_CSS_FEATURE1_HASH_SHIFT (8U) -/*! HASH - Enables HASH command. - */ -#define SYSCON_CSS_FEATURE1_HASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_HASH_SHIFT)) & SYSCON_CSS_FEATURE1_HASH_MASK) - -#define SYSCON_CSS_FEATURE1_HMAC_MASK (0xC00U) -#define SYSCON_CSS_FEATURE1_HMAC_SHIFT (10U) -/*! HMAC - Enables HMAC command. - */ -#define SYSCON_CSS_FEATURE1_HMAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_HMAC_SHIFT)) & SYSCON_CSS_FEATURE1_HMAC_MASK) - -#define SYSCON_CSS_FEATURE1_CMAC_MASK (0x3000U) -#define SYSCON_CSS_FEATURE1_CMAC_SHIFT (12U) -/*! CMAC - Enables CMAC command. - */ -#define SYSCON_CSS_FEATURE1_CMAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_CMAC_SHIFT)) & SYSCON_CSS_FEATURE1_CMAC_MASK) - -#define SYSCON_CSS_FEATURE1_DRBG_REQ_MASK (0x30000U) -#define SYSCON_CSS_FEATURE1_DRBG_REQ_SHIFT (16U) -/*! DRBG_REQ - Enables DRBG_REQ command. - */ -#define SYSCON_CSS_FEATURE1_DRBG_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DRBG_REQ_SHIFT)) & SYSCON_CSS_FEATURE1_DRBG_REQ_MASK) - -#define SYSCON_CSS_FEATURE1_DRBG_TEST_MASK (0xC0000U) -#define SYSCON_CSS_FEATURE1_DRBG_TEST_SHIFT (18U) -/*! DRBG_TEST - Enables DRBG_TEST command. - */ -#define SYSCON_CSS_FEATURE1_DRBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DRBG_TEST_SHIFT)) & SYSCON_CSS_FEATURE1_DRBG_TEST_MASK) - -#define SYSCON_CSS_FEATURE1_DTRNG_CFG_LOAD_MASK (0x3000000U) -#define SYSCON_CSS_FEATURE1_DTRNG_CFG_LOAD_SHIFT (24U) -/*! DTRNG_CFG_LOAD - Enables DTRNG_CFG_LOAD command. - */ -#define SYSCON_CSS_FEATURE1_DTRNG_CFG_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DTRNG_CFG_LOAD_SHIFT)) & SYSCON_CSS_FEATURE1_DTRNG_CFG_LOAD_MASK) - -#define SYSCON_CSS_FEATURE1_DTRNG_EVAL_MASK (0xC000000U) -#define SYSCON_CSS_FEATURE1_DTRNG_EVAL_SHIFT (26U) -/*! DTRNG_EVAL - Enables DTRNG_EVAL command. - */ -#define SYSCON_CSS_FEATURE1_DTRNG_EVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DTRNG_EVAL_SHIFT)) & SYSCON_CSS_FEATURE1_DTRNG_EVAL_MASK) - -#define SYSCON_CSS_FEATURE1_GDET_CFG_LOAD_MASK (0x30000000U) -#define SYSCON_CSS_FEATURE1_GDET_CFG_LOAD_SHIFT (28U) -/*! GDET_CFG_LOAD - Enables GDET_CFG_LOAD command. - */ -#define SYSCON_CSS_FEATURE1_GDET_CFG_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_GDET_CFG_LOAD_SHIFT)) & SYSCON_CSS_FEATURE1_GDET_CFG_LOAD_MASK) -/*! @} */ - -/*! @name CSS_FEATURE0_DP - CSS command feature - duplicate version */ -/*! @{ */ - -#define SYSCON_CSS_FEATURE0_DP_CIPHER_MASK (0x3U) -#define SYSCON_CSS_FEATURE0_DP_CIPHER_SHIFT (0U) -/*! CIPHER - Enables CIPHER command. - */ -#define SYSCON_CSS_FEATURE0_DP_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_CIPHER_SHIFT)) & SYSCON_CSS_FEATURE0_DP_CIPHER_MASK) - -#define SYSCON_CSS_FEATURE0_DP_AUTH_CIPHER_MASK (0xCU) -#define SYSCON_CSS_FEATURE0_DP_AUTH_CIPHER_SHIFT (2U) -/*! AUTH_CIPHER - Enables AUTH_CIPHER command. - */ -#define SYSCON_CSS_FEATURE0_DP_AUTH_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_AUTH_CIPHER_SHIFT)) & SYSCON_CSS_FEATURE0_DP_AUTH_CIPHER_MASK) - -#define SYSCON_CSS_FEATURE0_DP_ECSIGN_MASK (0x300U) -#define SYSCON_CSS_FEATURE0_DP_ECSIGN_SHIFT (8U) -/*! ECSIGN - Enables ECSIGN command. - */ -#define SYSCON_CSS_FEATURE0_DP_ECSIGN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_ECSIGN_SHIFT)) & SYSCON_CSS_FEATURE0_DP_ECSIGN_MASK) - -#define SYSCON_CSS_FEATURE0_DP_ECVFY_MASK (0xC00U) -#define SYSCON_CSS_FEATURE0_DP_ECVFY_SHIFT (10U) -/*! ECVFY - Enables ECSIGN command. - */ -#define SYSCON_CSS_FEATURE0_DP_ECVFY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_ECVFY_SHIFT)) & SYSCON_CSS_FEATURE0_DP_ECVFY_MASK) - -#define SYSCON_CSS_FEATURE0_DP_ECKXCH_MASK (0x3000U) -#define SYSCON_CSS_FEATURE0_DP_ECKXCH_SHIFT (12U) -/*! ECKXCH - Enables ECSIGN command. - */ -#define SYSCON_CSS_FEATURE0_DP_ECKXCH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_ECKXCH_SHIFT)) & SYSCON_CSS_FEATURE0_DP_ECKXCH_MASK) - -#define SYSCON_CSS_FEATURE0_DP_KEYGEN_MASK (0x30000U) -#define SYSCON_CSS_FEATURE0_DP_KEYGEN_SHIFT (16U) -/*! KEYGEN - Enables KEYGEN command. - */ -#define SYSCON_CSS_FEATURE0_DP_KEYGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_KEYGEN_SHIFT)) & SYSCON_CSS_FEATURE0_DP_KEYGEN_MASK) - -#define SYSCON_CSS_FEATURE0_DP_KEYIN_MASK (0xC0000U) -#define SYSCON_CSS_FEATURE0_DP_KEYIN_SHIFT (18U) -/*! KEYIN - Enables KEYIN command. - */ -#define SYSCON_CSS_FEATURE0_DP_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_KEYIN_SHIFT)) & SYSCON_CSS_FEATURE0_DP_KEYIN_MASK) - -#define SYSCON_CSS_FEATURE0_DP_KEYOUT_MASK (0x300000U) -#define SYSCON_CSS_FEATURE0_DP_KEYOUT_SHIFT (20U) -/*! KEYOUT - Enables KEYOUT command. - */ -#define SYSCON_CSS_FEATURE0_DP_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_KEYOUT_SHIFT)) & SYSCON_CSS_FEATURE0_DP_KEYOUT_MASK) - -#define SYSCON_CSS_FEATURE0_DP_KDELETE_MASK (0xC00000U) -#define SYSCON_CSS_FEATURE0_DP_KDELETE_SHIFT (22U) -/*! KDELETE - Enables KDELETE command. - */ -#define SYSCON_CSS_FEATURE0_DP_KDELETE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_KDELETE_SHIFT)) & SYSCON_CSS_FEATURE0_DP_KDELETE_MASK) -/*! @} */ - -/*! @name CSS_FEATURE1_DP - CSS command feature - duplicate version */ -/*! @{ */ - -#define SYSCON_CSS_FEATURE1_DP_CKDF_MASK (0x3U) -#define SYSCON_CSS_FEATURE1_DP_CKDF_SHIFT (0U) -/*! CKDF - Enables CKDF command. - */ -#define SYSCON_CSS_FEATURE1_DP_CKDF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_CKDF_SHIFT)) & SYSCON_CSS_FEATURE1_DP_CKDF_MASK) - -#define SYSCON_CSS_FEATURE1_DP_HKDF_MASK (0xCU) -#define SYSCON_CSS_FEATURE1_DP_HKDF_SHIFT (2U) -/*! HKDF - Enables HKDF command. - */ -#define SYSCON_CSS_FEATURE1_DP_HKDF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_HKDF_SHIFT)) & SYSCON_CSS_FEATURE1_DP_HKDF_MASK) - -#define SYSCON_CSS_FEATURE1_DP_TLS_INIT_MASK (0x30U) -#define SYSCON_CSS_FEATURE1_DP_TLS_INIT_SHIFT (4U) -/*! TLS_INIT - Enables TLS_INIT command. - */ -#define SYSCON_CSS_FEATURE1_DP_TLS_INIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_TLS_INIT_SHIFT)) & SYSCON_CSS_FEATURE1_DP_TLS_INIT_MASK) - -#define SYSCON_CSS_FEATURE1_DP_HASH_MASK (0x300U) -#define SYSCON_CSS_FEATURE1_DP_HASH_SHIFT (8U) -/*! HASH - Enables HASH command. - */ -#define SYSCON_CSS_FEATURE1_DP_HASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_HASH_SHIFT)) & SYSCON_CSS_FEATURE1_DP_HASH_MASK) - -#define SYSCON_CSS_FEATURE1_DP_HMAC_MASK (0xC00U) -#define SYSCON_CSS_FEATURE1_DP_HMAC_SHIFT (10U) -/*! HMAC - Enables HMAC command. - */ -#define SYSCON_CSS_FEATURE1_DP_HMAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_HMAC_SHIFT)) & SYSCON_CSS_FEATURE1_DP_HMAC_MASK) - -#define SYSCON_CSS_FEATURE1_DP_CMAC_MASK (0x3000U) -#define SYSCON_CSS_FEATURE1_DP_CMAC_SHIFT (12U) -/*! CMAC - Enables CMAC command. - */ -#define SYSCON_CSS_FEATURE1_DP_CMAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_CMAC_SHIFT)) & SYSCON_CSS_FEATURE1_DP_CMAC_MASK) - -#define SYSCON_CSS_FEATURE1_DP_DRBG_REQ_MASK (0x30000U) -#define SYSCON_CSS_FEATURE1_DP_DRBG_REQ_SHIFT (16U) -/*! DRBG_REQ - Enables DRBG_REQ command. - */ -#define SYSCON_CSS_FEATURE1_DP_DRBG_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_DRBG_REQ_SHIFT)) & SYSCON_CSS_FEATURE1_DP_DRBG_REQ_MASK) - -#define SYSCON_CSS_FEATURE1_DP_DRBG_TEST_MASK (0xC0000U) -#define SYSCON_CSS_FEATURE1_DP_DRBG_TEST_SHIFT (18U) -/*! DRBG_TEST - Enables DRBG_TEST command. - */ -#define SYSCON_CSS_FEATURE1_DP_DRBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_DRBG_TEST_SHIFT)) & SYSCON_CSS_FEATURE1_DP_DRBG_TEST_MASK) - -#define SYSCON_CSS_FEATURE1_DP_DTRNG_CFG_LOAD_MASK (0x3000000U) -#define SYSCON_CSS_FEATURE1_DP_DTRNG_CFG_LOAD_SHIFT (24U) -/*! DTRNG_CFG_LOAD - Enables DTRNG_CFG_LOAD command. - */ -#define SYSCON_CSS_FEATURE1_DP_DTRNG_CFG_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_DTRNG_CFG_LOAD_SHIFT)) & SYSCON_CSS_FEATURE1_DP_DTRNG_CFG_LOAD_MASK) - -#define SYSCON_CSS_FEATURE1_DP_DTRNG_EVAL_MASK (0xC000000U) -#define SYSCON_CSS_FEATURE1_DP_DTRNG_EVAL_SHIFT (26U) -/*! DTRNG_EVAL - Enables DTRNG_EVAL command. - */ -#define SYSCON_CSS_FEATURE1_DP_DTRNG_EVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_DTRNG_EVAL_SHIFT)) & SYSCON_CSS_FEATURE1_DP_DTRNG_EVAL_MASK) - -#define SYSCON_CSS_FEATURE1_DP_GDET_CFG_LOAD_MASK (0x30000000U) -#define SYSCON_CSS_FEATURE1_DP_GDET_CFG_LOAD_SHIFT (28U) -/*! GDET_CFG_LOAD - Enables GDET_CFG_LOAD command. - */ -#define SYSCON_CSS_FEATURE1_DP_GDET_CFG_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_GDET_CFG_LOAD_SHIFT)) & SYSCON_CSS_FEATURE1_DP_GDET_CFG_LOAD_MASK) -/*! @} */ - -/*! @name CSS_BOOT_RETRY_CNT - CSS boot retry counter */ -/*! @{ */ - -#define SYSCON_CSS_BOOT_RETRY_CNT_BOOT_RETRY_CNT_MASK (0xFFFFFFFFU) -#define SYSCON_CSS_BOOT_RETRY_CNT_BOOT_RETRY_CNT_SHIFT (0U) -/*! BOOT_RETRY_CNT - Boot retry counter bit. - */ -#define SYSCON_CSS_BOOT_RETRY_CNT_BOOT_RETRY_CNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_BOOT_RETRY_CNT_BOOT_RETRY_CNT_SHIFT)) & SYSCON_CSS_BOOT_RETRY_CNT_BOOT_RETRY_CNT_MASK) -/*! @} */ - -/*! @name CSS_CLK_CTRL - CSS clock control */ -/*! @{ */ - -#define SYSCON_CSS_CLK_CTRL_GDET_REFCLK_EN_MASK (0x1U) -#define SYSCON_CSS_CLK_CTRL_GDET_REFCLK_EN_SHIFT (0U) -/*! GDET_REFCLK_EN - GDET reference clock enable bit. - */ -#define SYSCON_CSS_CLK_CTRL_GDET_REFCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_CLK_CTRL_GDET_REFCLK_EN_SHIFT)) & SYSCON_CSS_CLK_CTRL_GDET_REFCLK_EN_MASK) - -#define SYSCON_CSS_CLK_CTRL_DTRNG_REFCLK_EN_MASK (0x2U) -#define SYSCON_CSS_CLK_CTRL_DTRNG_REFCLK_EN_SHIFT (1U) -/*! DTRNG_REFCLK_EN - DTRNG reference clock enable bit. - */ -#define SYSCON_CSS_CLK_CTRL_DTRNG_REFCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_CLK_CTRL_DTRNG_REFCLK_EN_SHIFT)) & SYSCON_CSS_CLK_CTRL_DTRNG_REFCLK_EN_MASK) -/*! @} */ - -/*! @name CSS_CLK_CTRL_SET - CSS clock control set */ -/*! @{ */ - -#define SYSCON_CSS_CLK_CTRL_SET_GDET_REFCLK_EN_SET_MASK (0x1U) -#define SYSCON_CSS_CLK_CTRL_SET_GDET_REFCLK_EN_SET_SHIFT (0U) -/*! GDET_REFCLK_EN_SET - GDET reference clock enable set bit. - */ -#define SYSCON_CSS_CLK_CTRL_SET_GDET_REFCLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_CLK_CTRL_SET_GDET_REFCLK_EN_SET_SHIFT)) & SYSCON_CSS_CLK_CTRL_SET_GDET_REFCLK_EN_SET_MASK) - -#define SYSCON_CSS_CLK_CTRL_SET_DTRNG_REFCLK_EN_SET_MASK (0x2U) -#define SYSCON_CSS_CLK_CTRL_SET_DTRNG_REFCLK_EN_SET_SHIFT (1U) -/*! DTRNG_REFCLK_EN_SET - DTRNG reference clock enable set bit. - */ -#define SYSCON_CSS_CLK_CTRL_SET_DTRNG_REFCLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_CLK_CTRL_SET_DTRNG_REFCLK_EN_SET_SHIFT)) & SYSCON_CSS_CLK_CTRL_SET_DTRNG_REFCLK_EN_SET_MASK) -/*! @} */ - -/*! @name CSS_CLK_CTRL_CLR - CSS clock control clear */ -/*! @{ */ - -#define SYSCON_CSS_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_MASK (0x1U) -#define SYSCON_CSS_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_SHIFT (0U) -/*! GDET_REFCLK_EN_CLR - GDET reference clock enable clear bit. - */ -#define SYSCON_CSS_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_SHIFT)) & SYSCON_CSS_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_MASK) - -#define SYSCON_CSS_CLK_CTRL_CLR_DTRNG_REFCLK_EN_CLR_MASK (0x2U) -#define SYSCON_CSS_CLK_CTRL_CLR_DTRNG_REFCLK_EN_CLR_SHIFT (1U) -/*! DTRNG_REFCLK_EN_CLR - DTRNG reference clock enable clear bit. - */ -#define SYSCON_CSS_CLK_CTRL_CLR_DTRNG_REFCLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_CLK_CTRL_CLR_DTRNG_REFCLK_EN_CLR_SHIFT)) & SYSCON_CSS_CLK_CTRL_CLR_DTRNG_REFCLK_EN_CLR_MASK) -/*! @} */ - -/*! @name CSS_CLK_SEL - CSS clock select */ -/*! @{ */ - -#define SYSCON_CSS_CLK_SEL_GDET_REFCLK_SEL_MASK (0x3U) -#define SYSCON_CSS_CLK_SEL_GDET_REFCLK_SEL_SHIFT (0U) -/*! GDET_REFCLK_SEL - GDET reference clock select bit. - */ -#define SYSCON_CSS_CLK_SEL_GDET_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_CLK_SEL_GDET_REFCLK_SEL_SHIFT)) & SYSCON_CSS_CLK_SEL_GDET_REFCLK_SEL_MASK) -/*! @} */ - -/*! @name CSS_AS_CFG0 - CSS AS configuration */ -/*! @{ */ - -#define SYSCON_CSS_AS_CFG0_CFG_LC_STATE_MASK (0xFFU) -#define SYSCON_CSS_AS_CFG0_CFG_LC_STATE_SHIFT (0U) -/*! CFG_LC_STATE - LC state configuration bit. - */ -#define SYSCON_CSS_AS_CFG0_CFG_LC_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_LC_STATE_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_LC_STATE_MASK) - -#define SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_RESET_ENABLED_MASK (0x100U) -#define SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_RESET_ENABLED_SHIFT (8U) -/*! CFG_BOD_VDDMAIN_RESET_ENABLED - When BOD VDDMAIN analog detector is turned on and BOD VDDMAIN reset is enabled, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_RESET_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_RESET_ENABLED_MASK) - -#define SYSCON_CSS_AS_CFG0_CFG_BOD_CORE_RESET_ENABLED_MASK (0x200U) -#define SYSCON_CSS_AS_CFG0_CFG_BOD_CORE_RESET_ENABLED_SHIFT (9U) -/*! CFG_BOD_CORE_RESET_ENABLED - When BOD CORE analog detector is turned on and BOD CORE reset is enabled, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG0_CFG_BOD_CORE_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_BOD_CORE_RESET_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_BOD_CORE_RESET_ENABLED_MASK) - -#define SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_IRQ_ENABLED_MASK (0x400U) -#define SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_IRQ_ENABLED_SHIFT (10U) -/*! CFG_BOD_VDDMAIN_IRQ_ENABLED - When BOD VDDMAIN analog detector is turned on and BOD VDDMAIN IRQ is enabled, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_IRQ_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_IRQ_ENABLED_MASK) - -#define SYSCON_CSS_AS_CFG0_CFG_WDT_ENABLED_MASK (0x1000U) -#define SYSCON_CSS_AS_CFG0_CFG_WDT_ENABLED_SHIFT (12U) -/*! CFG_WDT_ENABLED - When WatchDog Timer is activated, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG0_CFG_WDT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_WDT_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_WDT_ENABLED_MASK) - -#define SYSCON_CSS_AS_CFG0_CFG_CWDT_ENABLED_MASK (0x2000U) -#define SYSCON_CSS_AS_CFG0_CFG_CWDT_ENABLED_SHIFT (13U) -/*! CFG_CWDT_ENABLED - When Code WatchDog Timer is activated, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG0_CFG_CWDT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_CWDT_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_CWDT_ENABLED_MASK) - -#define SYSCON_CSS_AS_CFG0_CFG_CSS_GDET_ENABLED_MASK (0x8000U) -#define SYSCON_CSS_AS_CFG0_CFG_CSS_GDET_ENABLED_SHIFT (15U) -/*! CFG_CSS_GDET_ENABLED - When CSS GDET is enabled, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG0_CFG_CSS_GDET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_CSS_GDET_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_CSS_GDET_ENABLED_MASK) - -#define SYSCON_CSS_AS_CFG0_CFG_ANA_GDET_ENABLED_MASK (0x10000U) -#define SYSCON_CSS_AS_CFG0_CFG_ANA_GDET_ENABLED_SHIFT (16U) -/*! CFG_ANA_GDET_ENABLED - When ANALOG GDET is enabled, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG0_CFG_ANA_GDET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_ANA_GDET_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_ANA_GDET_ENABLED_MASK) - -#define SYSCON_CSS_AS_CFG0_CFG_TAMPER_DET_ENABLED_MASK (0x20000U) -#define SYSCON_CSS_AS_CFG0_CFG_TAMPER_DET_ENABLED_SHIFT (17U) -/*! CFG_TAMPER_DET_ENABLED - When tamper detector is enabled in RTC, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG0_CFG_TAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_TAMPER_DET_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_TAMPER_DET_ENABLED_MASK) - -#define SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_MASK (0x40000U) -#define SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_SHIFT (18U) -/*! CFG_FLASH_IS_REMAPPED - When FLASHREMAP_OFFSET register (0x4000_0448) is not equal to 0x0000_0000, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_MASK) - -#define SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_DP_MASK (0x80000U) -#define SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_DP_SHIFT (19U) -/*! CFG_FLASH_IS_REMAPPED_DP - When FLASHREMAP_OFFSET_DP register (0x4000_044C) is not equal to 0x0000_0000, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_DP_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_DP_MASK) - -#define SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK0_ENABLE_MASK (0xF00000U) -#define SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK0_ENABLE_SHIFT (20U) -/*! CFG_FLASH_BANK0_ENABLE - The state of FLASHBANK_ENABLE0 register (0x4000_0450) reflects to this register as below. - */ -#define SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK0_ENABLE_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK0_ENABLE_MASK) - -#define SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK1_ENABLE_MASK (0xF000000U) -#define SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK1_ENABLE_SHIFT (24U) -/*! CFG_FLASH_BANK1_ENABLE - The state of FLASHBANK_ENABLE1 register (0x4000_0454) reflects to this register as below: - */ -#define SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK1_ENABLE_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK1_ENABLE_MASK) - -#define SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_ENROLL_MASK (0x10000000U) -#define SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_ENROLL_SHIFT (28U) -/*! CFG_QK_DISABLE_ENROLL - When CONFIG[DIS_PUF_ENROLL] bit is set 1, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_ENROLL_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_ENROLL_MASK) - -#define SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_WRAP_MASK (0x20000000U) -#define SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_WRAP_SHIFT (29U) -/*! CFG_QK_DISABLE_WRAP - When CONFIG[DIS_PUF_WRAP_KEY] bit is set 1, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_WRAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_WRAP_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_WRAP_MASK) -/*! @} */ - -/*! @name CSS_AS_CFG1 - CSS AS configuration1 */ -/*! @{ */ - -#define SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_MASK (0x2U) -#define SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_SHIFT (1U) -/*! CFG_SEC_DIS_STRICT_MODE - When "CFG_SEC_ENA_SEC_CHK" indicates state 0 or when - * "DISABLE_STRICT_MODE" bits in "MISC_CTRL_REG" and "MISC_CTRL_DP_REG" on AHB secure controller, both bits are - * equal to 01, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_MASK) - -#define SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_MASK (0x4U) -#define SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_SHIFT (2U) -/*! CFG_SEC_DIS_VIOL_ABORT - When "DISABLE_VIOLATION_ABORT" bits in "MISC_CTRL_REG" and - * "MISC_CTRL_DP_REG" on AHB secure controller, both bits are not equal to 10, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_MASK) - -#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_MASK (0x8U) -#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_SHIFT (3U) -/*! CFG_SEC_ENA_NS_PRIV_CHK - When "ENABLE_NS_PRIV_CHECK" bits in "MISC_CTRL_REG" and - * "MISC_CTRL_DP_REG" on AHB secure controller, both bits are not equal to 10, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_MASK) - -#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_MASK (0x10U) -#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_SHIFT (4U) -/*! CFG_SEC_ENA_S_PRIV_CHK - When "ENABLE_S_PRIV_CHECK" bits in "MISC_CTRL_REG" and - * "MISC_CTRL_DP_REG" on AHB secure controller, both bits are not equal to 10, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_MASK) - -#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_MASK (0x20U) -#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_SHIFT (5U) -/*! CFG_SEC_ENA_SEC_CHK - When "ENABLE_SECURE_CHECKING" bits in "MISC_CTRL_REG" and - * "MISC_CTRL_DP_REG" on AHB secure controller, both bits are not equal to 10, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_SEC_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_MASK) - -#define SYSCON_CSS_AS_CFG1_CFG_SEC_IDAU_ALLNS_MASK (0x40U) -#define SYSCON_CSS_AS_CFG1_CFG_SEC_IDAU_ALLNS_SHIFT (6U) -/*! CFG_SEC_IDAU_ALLNS - When "IDAU_ALL_NS" bits in "MISC_CTRL_REG" and "MISC_CTRL_DP_REG" on AHB - * secure controller, both bits are equal to 01, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG1_CFG_SEC_IDAU_ALLNS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_IDAU_ALLNS_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_IDAU_ALLNS_MASK) - -#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_MASK (0x100U) -#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_SHIFT (8U) -/*! CFG_SEC_LOCK_NS_MPU - When "LOCK_NS_MPU" bits in "CPU0_LOCK_REG" on AHB secure controller are not equal to 10, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_MASK) - -#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_MASK (0x200U) -#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_SHIFT (9U) -/*! CFG_SEC_LOCK_NS_VTOR - When "LOCK_NS_VTOR" bits in "CPU0_LOCK_REG" on AHB secure controller are not equal to 10, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_MASK) - -#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_MPU_MASK (0x400U) -#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_MPU_SHIFT (10U) -/*! CFG_SEC_LOCK_S_MPU - When "LOCK_S_MPU" bits in "CPU0_LOCK_REG" on AHB secure controller are not equal to 10, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_MPU_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_MPU_MASK) - -#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_MASK (0x800U) -#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_SHIFT (11U) -/*! CFG_SEC_LOCK_S_VTAIRCR - When "LOCK_S_VTAIRCR" bits in "CPU0_LOCK_REG" on AHB secure controller are not equal to 10, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_MASK) - -#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_SAU_MASK (0x1000U) -#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_SAU_SHIFT (12U) -/*! CFG_SEC_LOCK_SAU - When "LOCK_SAU" bits in "CPU0_LOCK_REG" on AHB secure controller are not equal to 10, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_SAU_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_SAU_MASK) -/*! @} */ - -/*! @name CSS_AS_CFG2 - CSS AS configuration2 */ -/*! @{ */ - -#define SYSCON_CSS_AS_CFG2_CFG_CSS_CMD_EN_MASK (0xFFFFFFFFU) -#define SYSCON_CSS_AS_CFG2_CFG_CSS_CMD_EN_SHIFT (0U) -/*! CFG_CSS_CMD_EN - CSS configuration command enable bit. - */ -#define SYSCON_CSS_AS_CFG2_CFG_CSS_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG2_CFG_CSS_CMD_EN_SHIFT)) & SYSCON_CSS_AS_CFG2_CFG_CSS_CMD_EN_MASK) -/*! @} */ - -/*! @name CSS_AS_ST0 - CSS AS state register */ -/*! @{ */ - -#define SYSCON_CSS_AS_ST0_ST_TEMPORAL_STATE_MASK (0xFU) -#define SYSCON_CSS_AS_ST0_ST_TEMPORAL_STATE_SHIFT (0U) -/*! ST_TEMPORAL_STATE - "TEMPORAL_STATE[3:0]" on "CSS_TEMPORAL_STATE" register reflects this register. - */ -#define SYSCON_CSS_AS_ST0_ST_TEMPORAL_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_TEMPORAL_STATE_SHIFT)) & SYSCON_CSS_AS_ST0_ST_TEMPORAL_STATE_MASK) - -#define SYSCON_CSS_AS_ST0_ST_CPU0_DBGEN_MASK (0x10U) -#define SYSCON_CSS_AS_ST0_ST_CPU0_DBGEN_SHIFT (4U) -/*! ST_CPU0_DBGEN - When CPU0 (CM33) "deben" input is state 1, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_ST0_ST_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_CPU0_DBGEN_SHIFT)) & SYSCON_CSS_AS_ST0_ST_CPU0_DBGEN_MASK) - -#define SYSCON_CSS_AS_ST0_ST_CPU0_NIDEN_MASK (0x20U) -#define SYSCON_CSS_AS_ST0_ST_CPU0_NIDEN_SHIFT (5U) -/*! ST_CPU0_NIDEN - When CPU0 (CM33) "niden" input is state 1, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_ST0_ST_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_CPU0_NIDEN_SHIFT)) & SYSCON_CSS_AS_ST0_ST_CPU0_NIDEN_MASK) - -#define SYSCON_CSS_AS_ST0_ST_CPU0_SPIDEN_MASK (0x40U) -#define SYSCON_CSS_AS_ST0_ST_CPU0_SPIDEN_SHIFT (6U) -/*! ST_CPU0_SPIDEN - When CPU0 (CM33) "spiden" input is state 1, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_ST0_ST_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_CPU0_SPIDEN_SHIFT)) & SYSCON_CSS_AS_ST0_ST_CPU0_SPIDEN_MASK) - -#define SYSCON_CSS_AS_ST0_ST_CPU0_SPNIDEN_MASK (0x80U) -#define SYSCON_CSS_AS_ST0_ST_CPU0_SPNIDEN_SHIFT (7U) -/*! ST_CPU0_SPNIDEN - When CPU0 (CM33) "spniden" input is state 1, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_ST0_ST_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_CPU0_SPNIDEN_SHIFT)) & SYSCON_CSS_AS_ST0_ST_CPU0_SPNIDEN_MASK) - -#define SYSCON_CSS_AS_ST0_ST_DAP_ENABLE_CPU0_MASK (0x400U) -#define SYSCON_CSS_AS_ST0_ST_DAP_ENABLE_CPU0_SHIFT (10U) -/*! ST_DAP_ENABLE_CPU0 - When DAP to AP0 for CPU0 (CM33) debug access is allowed, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_ST0_ST_DAP_ENABLE_CPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_DAP_ENABLE_CPU0_SHIFT)) & SYSCON_CSS_AS_ST0_ST_DAP_ENABLE_CPU0_MASK) - -#define SYSCON_CSS_AS_ST0_ST_CSS_DEBUG_EN_MASK (0x2000U) -#define SYSCON_CSS_AS_ST0_ST_CSS_DEBUG_EN_SHIFT (13U) -/*! ST_CSS_DEBUG_EN - When CSS uCode code fetch out of AHB for debug is enabled, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_ST0_ST_CSS_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_CSS_DEBUG_EN_SHIFT)) & SYSCON_CSS_AS_ST0_ST_CSS_DEBUG_EN_MASK) - -#define SYSCON_CSS_AS_ST0_ST_ALLOW_TEST_ACCESS_MASK (0x4000U) -#define SYSCON_CSS_AS_ST0_ST_ALLOW_TEST_ACCESS_SHIFT (14U) -/*! ST_ALLOW_TEST_ACCESS - When JTAG TAP access is allowed, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_ST0_ST_ALLOW_TEST_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_ALLOW_TEST_ACCESS_SHIFT)) & SYSCON_CSS_AS_ST0_ST_ALLOW_TEST_ACCESS_MASK) - -#define SYSCON_CSS_AS_ST0_ST_XO32K_FAILED_MASK (0x8000U) -#define SYSCON_CSS_AS_ST0_ST_XO32K_FAILED_SHIFT (15U) -/*! ST_XO32K_FAILED - When XO32K oscillation fail flag is state 1 in PMC register block, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_ST0_ST_XO32K_FAILED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_XO32K_FAILED_SHIFT)) & SYSCON_CSS_AS_ST0_ST_XO32K_FAILED_MASK) -/*! @} */ - -/*! @name CSS_AS_ST1 - CSS AS state1 */ -/*! @{ */ - -#define SYSCON_CSS_AS_ST1_ST_QK_PUF_SCORE_MASK (0xFU) -#define SYSCON_CSS_AS_ST1_ST_QK_PUF_SCORE_SHIFT (0U) -/*! ST_QK_PUF_SCORE - These register bits indicate the state of "qk_puf_score[3:0]" outputs from QK PUF block. - */ -#define SYSCON_CSS_AS_ST1_ST_QK_PUF_SCORE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST1_ST_QK_PUF_SCORE_SHIFT)) & SYSCON_CSS_AS_ST1_ST_QK_PUF_SCORE_MASK) - -#define SYSCON_CSS_AS_ST1_ST_QK_ZEROIZED_MASK (0x10U) -#define SYSCON_CSS_AS_ST1_ST_QK_ZEROIZED_SHIFT (4U) -/*! ST_QK_ZEROIZED - This register bit indicates the state of "qk_zeroized" output from QK PUF block. - */ -#define SYSCON_CSS_AS_ST1_ST_QK_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST1_ST_QK_ZEROIZED_SHIFT)) & SYSCON_CSS_AS_ST1_ST_QK_ZEROIZED_MASK) - -#define SYSCON_CSS_AS_ST1_ST_MAIN_CLK_IS_EXT_MASK (0x20U) -#define SYSCON_CSS_AS_ST1_ST_MAIN_CLK_IS_EXT_SHIFT (5U) -/*! ST_MAIN_CLK_IS_EXT - When MAIN_CLK is running from external clock source either XO32M, XO32K or GPIO CLKIN, this bit indicates state 1. - */ -#define SYSCON_CSS_AS_ST1_ST_MAIN_CLK_IS_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST1_ST_MAIN_CLK_IS_EXT_SHIFT)) & SYSCON_CSS_AS_ST1_ST_MAIN_CLK_IS_EXT_MASK) - -#define SYSCON_CSS_AS_ST1_ST_DCDC_VOUT_MASK (0x3C0U) -#define SYSCON_CSS_AS_ST1_ST_DCDC_VOUT_SHIFT (6U) -/*! ST_DCDC_VOUT - VOUT[3:0] setting on DCDC0 register in PMC block will reflect to this register. - */ -#define SYSCON_CSS_AS_ST1_ST_DCDC_VOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST1_ST_DCDC_VOUT_SHIFT)) & SYSCON_CSS_AS_ST1_ST_DCDC_VOUT_MASK) - -#define SYSCON_CSS_AS_ST1_ST_BOOT_MODE_MASK (0xC00U) -#define SYSCON_CSS_AS_ST1_ST_BOOT_MODE_SHIFT (10U) -/*! ST_BOOT_MODE - BOOTMODE[1:0] status on STATUS register in PMC block will reflect to this register. - */ -#define SYSCON_CSS_AS_ST1_ST_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST1_ST_BOOT_MODE_SHIFT)) & SYSCON_CSS_AS_ST1_ST_BOOT_MODE_MASK) - -#define SYSCON_CSS_AS_ST1_ST_BOOT_RETRY_CNT_MASK (0xF000U) -#define SYSCON_CSS_AS_ST1_ST_BOOT_RETRY_CNT_SHIFT (12U) -/*! ST_BOOT_RETRY_CNT - "BOOT_RETRY_CNT[3:0]" on "CSS_BOOT_RETRY_CNT" register reflects this register. - */ -#define SYSCON_CSS_AS_ST1_ST_BOOT_RETRY_CNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST1_ST_BOOT_RETRY_CNT_SHIFT)) & SYSCON_CSS_AS_ST1_ST_BOOT_RETRY_CNT_MASK) -/*! @} */ - -/*! @name CSS_AS_ST2 - CSS AS state2 */ -/*! @{ */ - -#define SYSCON_CSS_AS_ST2_CSS_AS_ST2_MASK (0xFFFFFFFFU) -#define SYSCON_CSS_AS_ST2_CSS_AS_ST2_SHIFT (0U) -/*! CSS_AS_ST2 - "BOOT_STATE[31:0]" on "CSS_BOOT_STATE" register reflects this register. - */ -#define SYSCON_CSS_AS_ST2_CSS_AS_ST2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST2_CSS_AS_ST2_SHIFT)) & SYSCON_CSS_AS_ST2_CSS_AS_ST2_MASK) -/*! @} */ - -/*! @name CSS_AS_FLAG0 - CSS AS flag0 */ -/*! @{ */ - -#define SYSCON_CSS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_MASK (0x1U) -#define SYSCON_CSS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_SHIFT (0U) -/*! FLAG_AP_ENABLE_CPU0 - This flag bit is set 1 when DAP enables AP0 for CPU0 (CM33) debug access. The register is cleared 0 by PMC reset event. - */ -#define SYSCON_CSS_AS_FLAG0_FLAG_AP_ENABLE_CPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_MASK) - -#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_RESET_OCCURED_MASK (0x10U) -#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_RESET_OCCURED_SHIFT (4U) -/*! FLAG_BOD_VDDMAIN_RESET_OCCURED - This flag bit is set 1 when BOD VDDMAIN reset is enabled and - * BOD VDDMAIN analog detector is tripped. This register is cleared 0 by AO domain POR. - */ -#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_RESET_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_RESET_OCCURED_MASK) - -#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_RESET_OCCURED_MASK (0x20U) -#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_RESET_OCCURED_SHIFT (5U) -/*! FLAG_BOD_CORE_RESET_OCCURED - This flag bit is set 1 when BOD CORE reset is enabled and BOD CORE - * analog detector is tripped. This register is cleared 0 by AO domain POR. - */ -#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_RESET_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_RESET_OCCURED_MASK) - -#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_IRQ_OCCURED_MASK (0x40U) -#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_IRQ_OCCURED_SHIFT (6U) -/*! FLAG_BOD_VDDMAIN_IRQ_OCCURED - This flag bit is set 1 when BOD VDDMAIN IRQ is enabled and BOD - * VDDMAIN analog detector is tripped. This register is cleared 0 by PMC reset event. - */ -#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_IRQ_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_IRQ_OCCURED_MASK) - -#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_IRQ_OCCURED_MASK (0x80U) -#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_IRQ_OCCURED_SHIFT (7U) -/*! FLAG_BOD_CORE_IRQ_OCCURED - This flag bit is set 1 when BOD CORE IRQ is enabled and BOD CORE - * analog detector is tripped. This register is cleared 0 by PMC reset event. - */ -#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_IRQ_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_IRQ_OCCURED_MASK) - -#define SYSCON_CSS_AS_FLAG0_FLAG_WDT_RESET_OCCURED_MASK (0x100U) -#define SYSCON_CSS_AS_FLAG0_FLAG_WDT_RESET_OCCURED_SHIFT (8U) -/*! FLAG_WDT_RESET_OCCURED - This flag bit is set 1 when WatchDog Timer reset is enabled and reset - * event is triggered. This register is cleared 0 by AO domain POR. - */ -#define SYSCON_CSS_AS_FLAG0_FLAG_WDT_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_WDT_RESET_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_WDT_RESET_OCCURED_MASK) - -#define SYSCON_CSS_AS_FLAG0_FLAG_CWDT_RESET_OCCURED_MASK (0x200U) -#define SYSCON_CSS_AS_FLAG0_FLAG_CWDT_RESET_OCCURED_SHIFT (9U) -/*! FLAG_CWDT_RESET_OCCURED - This flag bit is set 1 when Code WatchDog Timer reset is enabled and - * reset event is triggered. This register is cleared 0 by AO domain POR. - */ -#define SYSCON_CSS_AS_FLAG0_FLAG_CWDT_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_CWDT_RESET_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_CWDT_RESET_OCCURED_MASK) - -#define SYSCON_CSS_AS_FLAG0_FLAG_WDT_IRQ_OCCURED_MASK (0x400U) -#define SYSCON_CSS_AS_FLAG0_FLAG_WDT_IRQ_OCCURED_SHIFT (10U) -/*! FLAG_WDT_IRQ_OCCURED - This flag register is set 1 when WatchDog Timer IRQ is enabled and IRQ - * event is triggered. This register is cleared 0 by PMC reset event. - */ -#define SYSCON_CSS_AS_FLAG0_FLAG_WDT_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_WDT_IRQ_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_WDT_IRQ_OCCURED_MASK) - -#define SYSCON_CSS_AS_FLAG0_FLAG_CWDT_IRQ_OCCURED_MASK (0x800U) -#define SYSCON_CSS_AS_FLAG0_FLAG_CWDT_IRQ_OCCURED_SHIFT (11U) -/*! FLAG_CWDT_IRQ_OCCURED - This flag bit is set 1 when Code WatchDog Timer IRQ is enabled and IRQ - * event is triggered. This register is cleared 0 by PMC reset event. - */ -#define SYSCON_CSS_AS_FLAG0_FLAG_CWDT_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_CWDT_IRQ_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_CWDT_IRQ_OCCURED_MASK) - -#define SYSCON_CSS_AS_FLAG0_FLAG_QK_ERROR_MASK (0x1000U) -#define SYSCON_CSS_AS_FLAG0_FLAG_QK_ERROR_SHIFT (12U) -/*! FLAG_QK_ERROR - This flag bit is set 1 when QK_ERROR is flagged from QK PUF block. This register is cleared 0 by PMC reset event. - */ -#define SYSCON_CSS_AS_FLAG0_FLAG_QK_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_QK_ERROR_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_QK_ERROR_MASK) - -#define SYSCON_CSS_AS_FLAG0_FLAG_CSS_GLITCH_DETECTED_MASK (0x2000U) -#define SYSCON_CSS_AS_FLAG0_FLAG_CSS_GLITCH_DETECTED_SHIFT (13U) -/*! FLAG_CSS_GLITCH_DETECTED - This flag bit is set 1 when GDET error is flagged from CSS. This register is cleared 0 by PMC reset event. - */ -#define SYSCON_CSS_AS_FLAG0_FLAG_CSS_GLITCH_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_CSS_GLITCH_DETECTED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_CSS_GLITCH_DETECTED_MASK) - -#define SYSCON_CSS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_MASK (0x4000U) -#define SYSCON_CSS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_SHIFT (14U) -/*! FLAG_ANA_GLITCH_DETECTED - This flag bit is set 1 when ANALOG GDET error is flagged in SYSCON block. This register is cleared 0 by PMC reset event. - */ -#define SYSCON_CSS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_MASK) - -#define SYSCON_CSS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_MASK (0x8000U) -#define SYSCON_CSS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_SHIFT (15U) -/*! FLAG_TAMPER_EVENT_DETECTED - This flag bit is set 1 when tamper event is flagged from RTC. This - * register is cleared 0 by AO domain POR or by PMC reset event, if ranmpr detection event is - * cleared by software. - */ -#define SYSCON_CSS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_MASK) - -#define SYSCON_CSS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_MASK (0x10000U) -#define SYSCON_CSS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_SHIFT (16U) -/*! FLAG_FLASH_ECC_INVALID - This flag bit is set 1 when FLASH controller indicates ECC error. This register is cleared 0 by PMC reset event. - */ -#define SYSCON_CSS_AS_FLAG0_FLAG_FLASH_ECC_INVALID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_MASK) - -#define SYSCON_CSS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_MASK (0x20000U) -#define SYSCON_CSS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_SHIFT (17U) -/*! FLAG_SEC_VIOL_IRQ_OCURRED - This flag bit is set 1 when security violation is indicated from FLASH sub-system or AHB bus matrix. - */ -#define SYSCON_CSS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_MASK) - -#define SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_MASK (0x40000U) -#define SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_SHIFT (18U) -/*! FLAG_CPU0_NS_C_ACC_OCCURED - This flag bit is set 1 when CPU0 (CM33) makes non-secure code - * transactions. This register is cleared 0 by PMC reset event. - */ -#define SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_MASK) - -#define SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_MASK (0x80000U) -#define SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_SHIFT (19U) -/*! FLAG_CPU0_NS_D_ACC_OCCURED - This flag register is set 1 when CPU0 (CM33) makes non-secure data - * transactions. This register is cleared 0 by PMC reset event. - */ -#define SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_MASK) -/*! @} */ - -/*! @name CLOCK_CTRL - Clock Control */ -/*! @{ */ - -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U) -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U) -/*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U) -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U) -/*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U) -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U) -/*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U) -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U) -/*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) -#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) -/*! CLKIN_ENA - Enable clock_in clock for clock module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) -/*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U) -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U) -/*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U) -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U) -/*! XO_CAL_CLK_ENA - Enable clock for crystal oscillator calibration - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK) -/*! @} */ - -/*! @name COMP_INT_CTRL - Comparator Interrupt control */ -/*! @{ */ - -#define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U) -#define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U) -/*! INT_ENABLE - Analog Comparator interrupt enable control:. - * 0b1..interrupt enable. - * 0b0..interrupt disable. - */ -#define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK) - -#define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U) -#define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U) -/*! INT_CLEAR - Analog Comparator interrupt clear. - * 0b0..No effect. - * 0b1..Clear the interrupt. Self-cleared bit. - */ -#define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK) - -#define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU) -#define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U) -/*! INT_CTRL - Comparator interrupt type selector:. - * 0b000..The analog comparator interrupt edge sensitive is disabled. - * 0b010..analog comparator interrupt is rising edge sensitive. - * 0b100..analog comparator interrupt is falling edge sensitive. - * 0b110..analog comparator interrupt is rising and falling edge sensitive. - * 0b001..The analog comparator interrupt level sensitive is disabled. - * 0b011..Analog Comparator interrupt is high level sensitive. - * 0b101..Analog Comparator interrupt is low level sensitive. - * 0b111..The analog comparator interrupt level sensitive is disabled. - */ -#define SYSCON_COMP_INT_CTRL_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK) - -#define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U) -#define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U) -/*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. - * 0b0..Select Analog Comparator filtered output as input for interrupt detection. - * 0b1..Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when - * Analog comparator is used as wake up source in Power down mode. - */ -#define SYSCON_COMP_INT_CTRL_INT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK) -/*! @} */ - -/*! @name COMP_INT_STATUS - Comparator Interrupt status */ -/*! @{ */ - -#define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U) -#define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U) -/*! STATUS - Interrupt status BEFORE Interrupt Enable. - * 0b0..No interrupt pending. - * 0b1..Interrupt pending. - */ -#define SYSCON_COMP_INT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK) - -#define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U) -#define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U) -/*! INT_STATUS - Interrupt status AFTER Interrupt Enable. - * 0b0..no interrupt pending. - * 0b1..interrupt pending. - */ -#define SYSCON_COMP_INT_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) - -#define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U) -#define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U) -/*! VAL - comparator analog output. - * 0b1..P+ is greater than P-. - * 0b0..P+ is smaller than P-. - */ -#define SYSCON_COMP_INT_STATUS_VAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK) -/*! @} */ - -/*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */ -/*! @{ */ - -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U) -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U) -/*! ROM - Control automatic clock gating of ROM controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_MASK (0x2U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_SHIFT (1U) -/*! RAMX - Control automatic clock gating of RAMX controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_MASK (0x4U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_SHIFT (2U) -/*! RAM0 - Control automatic clock gating of RAM0 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_MASK (0x8U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_SHIFT (3U) -/*! RAM1 - Control automatic clock gating of RAM1 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_MASK (0x10U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_SHIFT (4U) -/*! RAM2 - Control automatic clock gating of RAM2 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_MASK (0x20U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_SHIFT (5U) -/*! RAM3 - Control automatic clock gating of RAM3 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM3_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM3_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_MASK (0x40U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_SHIFT (6U) -/*! RAM4 - Control automatic clock gating of RAM4 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM4_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM4_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U) -/*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U) -/*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U) -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U) -/*! CRCGEN - Control automatic clock gating of CRCGEN controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U) -/*! SDMA0 - Control automatic clock gating of DMA0 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U) -/*! SDMA1 - Control automatic clock gating of DMA1 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK (0x4000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT (14U) -/*! USB0 - Control automatic clock gating of USB controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U) -/*! SYSCON - Control automatic clock gating of synchronous system controller registers bank. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U) -/*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. - * 0b1100000011011110..Bit Fields 0 - 15 of this register are updated - * 0b0000000000000000..Bit Fields 0 - 15 of this register are not updated - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK) -/*! @} */ - -/*! @name GPIOPSYNC - GPIO Synchronization */ -/*! @{ */ - -#define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U) -#define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U) -/*! PSYNC - Enable bypass of the first stage of synchronization inside GPIO_INT module. - * 0b1..Bypass of the first stage of synchronization inside GPIO_INT module. - * 0b0..Use the first stage of synchronization inside GPIO_INT module. - */ -#define SYSCON_GPIOPSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK) -/*! @} */ - -/*! @name AUTOCLKGATEOVERRIDE1 - Control automatic clock gating */ -/*! @{ */ - -#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC0_MASK (0x1U) -#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC0_SHIFT (0U) -/*! DAC0 - DAC0 - */ -#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_DAC0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_DAC0_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC1_MASK (0x2U) -#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC1_SHIFT (1U) -/*! DAC1 - DAC1 - */ -#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_DAC1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_DAC1_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC2_MASK (0x4U) -#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC2_SHIFT (2U) -/*! DAC2 - DAC2 - */ -#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_DAC2_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_DAC2_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP0_MASK (0x8U) -#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP0_SHIFT (3U) -/*! OPAMP0 - OPAMP0 - */ -#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP0_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP1_MASK (0x10U) -#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP1_SHIFT (4U) -/*! OPAMP1 - OPAMP1 - */ -#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP1_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP2_MASK (0x20U) -#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP2_SHIFT (5U) -/*! OPAMP2 - OPAMP2 - */ -#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP2_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP2_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP0_MASK (0x40U) -#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP0_SHIFT (6U) -/*! HSCMP0 - HSCMP0 - */ -#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP0_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP1_MASK (0x80U) -#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP1_SHIFT (7U) -/*! HSCMP1 - HSCMP0 - */ -#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP1_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP2_MASK (0x100U) -#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP2_SHIFT (8U) -/*! HSCMP2 - HSCMP2 - */ -#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP2_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP2_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE1_VREF_MASK (0x200U) -#define SYSCON_AUTOCLKGATEOVERRIDE1_VREF_SHIFT (9U) -/*! VREF - VREF - */ -#define SYSCON_AUTOCLKGATEOVERRIDE1_VREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_VREF_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_VREF_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE1_PWM0_MASK (0x400U) -#define SYSCON_AUTOCLKGATEOVERRIDE1_PWM0_SHIFT (10U) -/*! PWM0 - PWM0 - */ -#define SYSCON_AUTOCLKGATEOVERRIDE1_PWM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_PWM0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_PWM0_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE1_PWM1_MASK (0x800U) -#define SYSCON_AUTOCLKGATEOVERRIDE1_PWM1_SHIFT (11U) -/*! PWM1 - PWM1 - */ -#define SYSCON_AUTOCLKGATEOVERRIDE1_PWM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_PWM1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_PWM1_MASK) -/*! @} */ - -/*! @name ENABLE_MEM_PARITY_ECC_CHECK - Memory parity ECC enable */ -/*! @{ */ - -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx_MASK (0x1U) -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx_SHIFT (0U) -/*! ENABLE_RAMx - Enable RAMx parity error check - * 0b0..Disabled - * 0b1..Enabled - */ -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx_MASK) - -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM00_MASK (0x2U) -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM00_SHIFT (1U) -/*! ENABLE_RAM00 - Enable RAM00 parity error check - * 0b0..Disabled - * 0b1..Enabled - */ -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM00(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM00_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM00_MASK) - -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM01_MASK (0x4U) -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM01_SHIFT (2U) -/*! ENABLE_RAM01 - Enable RAM01 parity error check - * 0b0..Disabled - * 0b1..Enabled - */ -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM01(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM01_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM01_MASK) - -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx02_MASK (0x8U) -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx02_SHIFT (3U) -/*! ENABLE_RAMx02 - Enable RAMx02 parity error check - * 0b0..Disabled - * 0b1..Enabled - */ -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx02(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx02_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx02_MASK) - -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM03_MASK (0x10U) -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM03_SHIFT (4U) -/*! ENABLE_RAM03 - Enable RAM03 parity error check - * 0b0..Disabled - * 0b1..Enabled - */ -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM03(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM03_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM03_MASK) - -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_MBIT_MASK (0x20U) -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_MBIT_SHIFT (5U) -/*! ENABLE_RAM1_MBIT - Enable RAM1 ECC mbit error check - * 0b0..Disabled - * 0b1..Enabled - */ -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_MBIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_MBIT_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_MBIT_MASK) - -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_SBIT_MASK (0x40U) -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_SBIT_SHIFT (6U) -/*! ENABLE_RAM1_SBIT - Enable RAM1 ECC sbit error check - * 0b0..Disabled - * 0b1..Enabled - */ -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_SBIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_SBIT_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_SBIT_MASK) - -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM2_MASK (0x80U) -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM2_SHIFT (7U) -/*! ENABLE_RAM2 - Enable RAM2 parity error check - * 0b0..Disabled - * 0b1..Enabled - */ -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM2_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM2_MASK) - -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM3_MASK (0x100U) -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM3_SHIFT (8U) -/*! ENABLE_RAM3 - Enable RAM3 parity error check - * 0b0..Disabled - * 0b1..Enabled - */ -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM3_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM3_MASK) - -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM40_MASK (0x200U) -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM40_SHIFT (9U) -/*! ENABLE_RAM40 - Enable RAM40 parity error check - * 0b0..Disabled - * 0b1..Enabled - */ -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM40(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM40_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM40_MASK) - -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM41_MASK (0x400U) -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM41_SHIFT (10U) -/*! ENABLE_RAM41 - Enable RAM41 parity error check - * 0b0..Disabled - * 0b1..Enabled - */ -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM41(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM41_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM41_MASK) - -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM42_MASK (0x800U) -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM42_SHIFT (11U) -/*! ENABLE_RAM42 - Enable RAM42 parity error check - * 0b0..Disabled - * 0b1..Enabled - */ -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM42(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM42_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM42_MASK) - -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM43_MASK (0x1000U) -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM43_SHIFT (12U) -/*! ENABLE_RAM43 - Enable RAM43 parity error check - * 0b0..Disabled - * 0b1..Enabled - */ -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM43(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM43_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM43_MASK) - -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMX_PARITY_ERROR_INTEN_MASK (0x100000U) -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMX_PARITY_ERROR_INTEN_SHIFT (20U) -/*! RAMX_PARITY_ERROR_INTEN - Interrupt enable for RAMX parity error - * 0b0..Disable. - * 0b1..Enable RAM error interrupt when RAMX parity error status flag is set. - */ -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMX_PARITY_ERROR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMX_PARITY_ERROR_INTEN_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMX_PARITY_ERROR_INTEN_MASK) - -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMA_PARITY_ERROR_INTEN_MASK (0x200000U) -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMA_PARITY_ERROR_INTEN_SHIFT (21U) -/*! RAMA_PARITY_ERROR_INTEN - Interrupt enable for RAMA parity error - * 0b0..Disable. - * 0b1..Enable RAM error interrupt when RAMA parity error status flag is set. - */ -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMA_PARITY_ERROR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMA_PARITY_ERROR_INTEN_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMA_PARITY_ERROR_INTEN_MASK) - -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_MBIT_ERROR_INTEN_MASK (0x400000U) -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_MBIT_ERROR_INTEN_SHIFT (22U) -/*! RAMB_ECC_MBIT_ERROR_INTEN - Interrupt enable for RAMB ECC mbit_err - * 0b0..Disable. - * 0b1..Enable RAM error interrupt when RAMB ECC mbit_err status flag is set. - */ -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_MBIT_ERROR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_MBIT_ERROR_INTEN_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_MBIT_ERROR_INTEN_MASK) - -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_SBIT_ERROR_INTEN_MASK (0x800000U) -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_SBIT_ERROR_INTEN_SHIFT (23U) -/*! RAMB_ECC_SBIT_ERROR_INTEN - Interrupt enable for RAMB ECC sbit_err - * 0b0..Disable. - * 0b1..Enable RAM error interrupt when RAMB ECC sbit_err status flag is set. - */ -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_SBIT_ERROR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_SBIT_ERROR_INTEN_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_SBIT_ERROR_INTEN_MASK) - -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMC_PARITY_ERROR_INTEN_MASK (0x1000000U) -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMC_PARITY_ERROR_INTEN_SHIFT (24U) -/*! RAMC_PARITY_ERROR_INTEN - Interrupt enable for RAMC parity error - * 0b0..Disable. - * 0b1..Enable RAM error interrupt when RAMC parity error status flag is set. - */ -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMC_PARITY_ERROR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMC_PARITY_ERROR_INTEN_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMC_PARITY_ERROR_INTEN_MASK) - -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMD_PARITY_ERROR_INTEN_MASK (0x2000000U) -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMD_PARITY_ERROR_INTEN_SHIFT (25U) -/*! RAMD_PARITY_ERROR_INTEN - Interrupt enable for RAMD parity error - * 0b0..Disable. - * 0b1..Enable RAM error interrupt when RAMD parity error status flag is set. - */ -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMD_PARITY_ERROR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMD_PARITY_ERROR_INTEN_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMD_PARITY_ERROR_INTEN_MASK) - -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAME_PARITY_ERROR_INTEN_MASK (0x4000000U) -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAME_PARITY_ERROR_INTEN_SHIFT (26U) -/*! RAME_PARITY_ERROR_INTEN - Interrupt enable for RAME parity error - * 0b0..Disable. - * 0b1..Enable RAM error interrupt when RAME parity error status flag is set. - */ -#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAME_PARITY_ERROR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAME_PARITY_ERROR_INTEN_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAME_PARITY_ERROR_INTEN_MASK) -/*! @} */ - -/*! @name MEM_PARITY_ECC_ERROR_FLAG - Memory parity ECC error flag */ -/*! @{ */ - -#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAMX_PARITY_ERROR_MASK (0x1U) -#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAMX_PARITY_ERROR_SHIFT (0U) -/*! RAMX_PARITY_ERROR - RAMx parity error detected - * 0b0..No error detected - * 0b1..Error detected - */ -#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAMX_PARITY_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAMX_PARITY_ERROR_SHIFT)) & SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAMX_PARITY_ERROR_MASK) - -#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM0_PARITY_ERROR_MASK (0x2U) -#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM0_PARITY_ERROR_SHIFT (1U) -/*! RAM0_PARITY_ERROR - RAM0 parity error detected - * 0b0..No error detected - * 0b1..Error detected - */ -#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM0_PARITY_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM0_PARITY_ERROR_SHIFT)) & SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM0_PARITY_ERROR_MASK) - -#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_MBIT_ERROR_MASK (0x4U) -#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_MBIT_ERROR_SHIFT (2U) -/*! RAM1_ECC_MBIT_ERROR - RAM1 ECC mbit error detected - * 0b0..No error detected - * 0b1..Error detected - */ -#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_MBIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_MBIT_ERROR_SHIFT)) & SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_MBIT_ERROR_MASK) - -#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_SBIT_ERROR_MASK (0x8U) -#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_SBIT_ERROR_SHIFT (3U) -/*! RAM1_ECC_SBIT_ERROR - RAM1 ECC sbit error detected - * 0b0..No error detected - * 0b1..Error detected - */ -#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_SBIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_SBIT_ERROR_SHIFT)) & SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_SBIT_ERROR_MASK) - -#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM2_PARITY_ERROR_MASK (0x10U) -#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM2_PARITY_ERROR_SHIFT (4U) -/*! RAM2_PARITY_ERROR - RAM2 parity error detected - * 0b0..No error detected - * 0b1..Error detected - */ -#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM2_PARITY_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM2_PARITY_ERROR_SHIFT)) & SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM2_PARITY_ERROR_MASK) - -#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM3_PARITY_ERROR_MASK (0x20U) -#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM3_PARITY_ERROR_SHIFT (5U) -/*! RAM3_PARITY_ERROR - RAM3 parity error detected - * 0b0..No error detected - * 0b1..Error detected - */ -#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM3_PARITY_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM3_PARITY_ERROR_SHIFT)) & SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM3_PARITY_ERROR_MASK) - -#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM4_PARITY_ERROR_MASK (0x40U) -#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM4_PARITY_ERROR_SHIFT (6U) -/*! RAM4_PARITY_ERROR - RAM4 parity error detected - * 0b0..No error detected - * 0b1..Error detected - */ -#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM4_PARITY_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM4_PARITY_ERROR_SHIFT)) & SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM4_PARITY_ERROR_MASK) -/*! @} */ - -/*! @name PWM0SUBCTL - PWM0 submodule control */ -/*! @{ */ - -#define SYSCON_PWM0SUBCTL_CLK0_EN_MASK (0x1U) -#define SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT (0U) -/*! CLK0_EN - PWM0 SUB Clock0 enable - */ -#define SYSCON_PWM0SUBCTL_CLK0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK0_EN_MASK) - -#define SYSCON_PWM0SUBCTL_CLK1_EN_MASK (0x2U) -#define SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT (1U) -/*! CLK1_EN - PWM0 SUB Clock1 enable - */ -#define SYSCON_PWM0SUBCTL_CLK1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK1_EN_MASK) - -#define SYSCON_PWM0SUBCTL_CLK2_EN_MASK (0x4U) -#define SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT (2U) -/*! CLK2_EN - PWM0 SUB Clock2 enable - */ -#define SYSCON_PWM0SUBCTL_CLK2_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK2_EN_MASK) - -#define SYSCON_PWM0SUBCTL_CLK3_EN_MASK (0x8U) -#define SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT (3U) -/*! CLK3_EN - PWM0 SUB Clock3 enable - */ -#define SYSCON_PWM0SUBCTL_CLK3_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK3_EN_MASK) - -#define SYSCON_PWM0SUBCTL_DMAVALM0_MASK (0x1000U) -#define SYSCON_PWM0SUBCTL_DMAVALM0_SHIFT (12U) -/*! DMAVALM0 - PWM0 submodule 0 DMA Compare Value Done Mask - */ -#define SYSCON_PWM0SUBCTL_DMAVALM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM0_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM0_MASK) - -#define SYSCON_PWM0SUBCTL_DMAVALM1_MASK (0x2000U) -#define SYSCON_PWM0SUBCTL_DMAVALM1_SHIFT (13U) -/*! DMAVALM1 - PWM0 submodule 1 DMA Compare Value Done Mask - */ -#define SYSCON_PWM0SUBCTL_DMAVALM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM1_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM1_MASK) - -#define SYSCON_PWM0SUBCTL_DMAVALM2_MASK (0x4000U) -#define SYSCON_PWM0SUBCTL_DMAVALM2_SHIFT (14U) -/*! DMAVALM2 - PWM0 submodule 2 DMA Compare Value Done Mask - */ -#define SYSCON_PWM0SUBCTL_DMAVALM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM2_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM2_MASK) - -#define SYSCON_PWM0SUBCTL_DMAVALM3_MASK (0x8000U) -#define SYSCON_PWM0SUBCTL_DMAVALM3_SHIFT (15U) -/*! DMAVALM3 - PWM0 submodule 3 DMA Compare Value Done Mask - */ -#define SYSCON_PWM0SUBCTL_DMAVALM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM3_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM3_MASK) -/*! @} */ - -/*! @name PWM1SUBCTL - PWM1 submodule control */ -/*! @{ */ - -#define SYSCON_PWM1SUBCTL_CLK0_EN_MASK (0x1U) -#define SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT (0U) -/*! CLK0_EN - PWM1 SUB Clock0 enable - */ -#define SYSCON_PWM1SUBCTL_CLK0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK0_EN_MASK) - -#define SYSCON_PWM1SUBCTL_CLK1_EN_MASK (0x2U) -#define SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT (1U) -/*! CLK1_EN - PWM1 SUB Clock1 enable - */ -#define SYSCON_PWM1SUBCTL_CLK1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK1_EN_MASK) - -#define SYSCON_PWM1SUBCTL_CLK2_EN_MASK (0x4U) -#define SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT (2U) -/*! CLK2_EN - PWM1 SUB Clock2 enable - */ -#define SYSCON_PWM1SUBCTL_CLK2_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK2_EN_MASK) - -#define SYSCON_PWM1SUBCTL_CLK3_EN_MASK (0x8U) -#define SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT (3U) -/*! CLK3_EN - PWM1 SUB Clock3 enable - */ -#define SYSCON_PWM1SUBCTL_CLK3_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK3_EN_MASK) - -#define SYSCON_PWM1SUBCTL_DMAVALM0_MASK (0x1000U) -#define SYSCON_PWM1SUBCTL_DMAVALM0_SHIFT (12U) -/*! DMAVALM0 - PWM1 submodule 0 DMA Compare Value Done Mask - */ -#define SYSCON_PWM1SUBCTL_DMAVALM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM0_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM0_MASK) - -#define SYSCON_PWM1SUBCTL_DMAVALM1_MASK (0x2000U) -#define SYSCON_PWM1SUBCTL_DMAVALM1_SHIFT (13U) -/*! DMAVALM1 - PWM1 submodule 1 DMA Compare Value Done Mask - */ -#define SYSCON_PWM1SUBCTL_DMAVALM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM1_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM1_MASK) - -#define SYSCON_PWM1SUBCTL_DMAVALM2_MASK (0x4000U) -#define SYSCON_PWM1SUBCTL_DMAVALM2_SHIFT (14U) -/*! DMAVALM2 - PWM1 submodule 2 DMA Compare Value Done Mask - */ -#define SYSCON_PWM1SUBCTL_DMAVALM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM2_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM2_MASK) - -#define SYSCON_PWM1SUBCTL_DMAVALM3_MASK (0x8000U) -#define SYSCON_PWM1SUBCTL_DMAVALM3_SHIFT (15U) -/*! DMAVALM3 - PWM1 submodule 3 DMA Compare Value Done Mask - */ -#define SYSCON_PWM1SUBCTL_DMAVALM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM3_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM3_MASK) -/*! @} */ - -/*! @name CTIMERGLOBALSTARTEN - CTIMER global start enable */ -/*! @{ */ - -#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK (0x1U) -#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT (0U) -/*! CTIMER0_CLK_EN - CTIMER0 function clock enable - */ -#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK) - -#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK (0x2U) -#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT (1U) -/*! CTIMER1_CLK_EN - CTIMER1 function clock enable - */ -#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK) - -#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK (0x4U) -#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT (2U) -/*! CTIMER2_CLK_EN - CTIMER2 function clock enable - */ -#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK) - -#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK (0x8U) -#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT (3U) -/*! CTIMER3_CLK_EN - CTIMER3 function clock enable - */ -#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK) - -#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK (0x10U) -#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT (4U) -/*! CTIMER4_CLK_EN - CTIMER4 function clock enable - */ -#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK) -/*! @} */ - -/*! @name DEBUG_LOCK_EN - Control write access to security */ -/*! @{ */ - -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) -/*! LOCK_ALL - Control write access to security registers. - * 0b1010..1010: Enable write access to all registers. - * 0b0000..Any other value than b1010: disable write access to all registers. - */ -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) -/*! @} */ - -/*! @name DEBUG_FEATURES - Cortex debug features control */ -/*! @{ */ - -#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) -#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) -/*! CPU0_DBGEN - CPU0 Invasive Debug Control - * 0b01..Disable debug - * 0b10..Enable debug - */ -#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) -#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) -/*! CPU0_NIDEN - CPU0 Non Invasive Debug Control - * 0b01..Disable debug - * 0b10..Enable debug - */ -#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK (0x30U) -#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (4U) -/*! CPU0_SPIDEN - CPU0 Secure Privileged Invasive Debug Control - * 0b01..Disable debug - * 0b10..Enable debug - */ -#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0xC0U) -#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U) -/*! CPU0_SPNIDEN - CPU0 Secure Privileged Non Invasive Debug Control - * 0b01..Disable debug - * 0b10..Enable debug - */ -#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK) -/*! @} */ - -/*! @name DEBUG_FEATURES_DP - Cortex debug features control (duplicate) */ -/*! @{ */ - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) -/*! CPU0_DBGEN - CPU0 Invasive Debug Control - * 0b01..Disable debug - * 0b10..Enable debug - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) -/*! CPU0_NIDEN - CPU0 Non Invasive Debug Control - * 0b01..Disable debug - * 0b10..Enable debug - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U) -/*! CPU0_SPIDEN - CPU0 Secure Privileged Invasive Debug Control - * 0b01..Disable debug - * 0b10..Enable debug - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U) -/*! CPU0_SPNIDEN - CPU0 Secure Privileged Non Invasive Debug Control - * 0b01..Disable debug - * 0b10..Enable debug - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK) -/*! @} */ - -/*! @name SWD_ACCESS_CPU - CPU0 Software Debug Access */ -/*! @{ */ - -#define SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) -#define SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT (0U) -/*! SEC_CODE - CPU0 SWD-AP: 0x12345678. - * 0b00010010001101000101011001111000..Value to write to enable CPU0 SWD access. Reading back register will be read as 0xA. - * 0b00000000000000000000000000000000..CPU0 DAP is not allowed. Reading back register will be read as 0x5. - */ -#define SYSCON_SWD_ACCESS_CPU_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK) -/*! @} */ - -/* The count of SYSCON_SWD_ACCESS_CPU */ -#define SYSCON_SWD_ACCESS_CPU_COUNT (1U) - -/*! @name DEBUG_AUTH_BEACON - Debug authentication BEACON */ -/*! @{ */ - -#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) -#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) -/*! BEACON - Set by the debug authentication code in ROM to pass the debug beacons (Credential - * Beacon and Authentication Beacon) to application code. - */ -#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) -/*! @} */ - -/*! @name SWD_ACCESS_DSP - DSP Software Debug Access */ -/*! @{ */ - -#define SYSCON_SWD_ACCESS_DSP_SEC_CODE_MASK (0xFFFFFFFFU) -#define SYSCON_SWD_ACCESS_DSP_SEC_CODE_SHIFT (0U) -/*! SEC_CODE - DSP SWD-AP: 0x12345678. - * 0b00010010001101000101011001111000..Value to write to enable DSP SWD access. Reading back register will be read as 0xA. - * 0b00000000000000000000000000000000..DSP DAP is not allowed. Reading back register will be read as 0x5. - */ -#define SYSCON_SWD_ACCESS_DSP_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_DSP_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_DSP_SEC_CODE_MASK) -/*! @} */ - -/*! @name DEVICE_ID0 - Device ID */ -/*! @{ */ - -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) -/*! ROM_REV_MINOR - ROM revision. - */ -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) -/*! @} */ - -/*! @name DIEID - Chip revision ID and Number */ -/*! @{ */ - -#define SYSCON_DIEID_REV_ID_MASK (0xFU) -#define SYSCON_DIEID_REV_ID_SHIFT (0U) -/*! REV_ID - Chip Metal Revision ID. - */ -#define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK) - -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U) -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U) -/*! MCO_NUM_IN_DIE_ID - Chip Number 0x426B. - */ -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SYSCON_Register_Masks */ - - -/* SYSCON - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SYSCON base address */ - #define SYSCON_BASE (0x50000000u) - /** Peripheral SYSCON base address */ - #define SYSCON_BASE_NS (0x40000000u) - /** Peripheral SYSCON base pointer */ - #define SYSCON ((SYSCON_Type *)SYSCON_BASE) - /** Peripheral SYSCON base pointer */ - #define SYSCON_NS ((SYSCON_Type *)SYSCON_BASE_NS) - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS { SYSCON_BASE } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS { SYSCON } - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS_NS { SYSCON_BASE_NS } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS_NS { SYSCON_NS } -#else - /** Peripheral SYSCON base address */ - #define SYSCON_BASE (0x40000000u) - /** Peripheral SYSCON base pointer */ - #define SYSCON ((SYSCON_Type *)SYSCON_BASE) - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS { SYSCON_BASE } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS { SYSCON } -#endif - -/*! - * @} - */ /* end of group SYSCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SYSCTL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCTL_Peripheral_Access_Layer SYSCTL Peripheral Access Layer - * @{ - */ - -/** SYSCTL - Register Layout Typedef */ -typedef struct { - __IO uint32_t UPDATELCKOUT; /**< Write Lock Out, offset: 0x0 */ - uint8_t RESERVED_0[60]; - __IO uint32_t FCCTRLSEL[8]; /**< Shared Signal Select for Flexcomm 0..Shared Signal Select for Flexcomm 7, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_1[32]; - __IO uint32_t SHAREDCTRLSET[2]; /**< Shared Signal Set 0..Shared Signal Set 1, array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_2[248]; - __IO uint32_t CODE_GRAY_LSB; /**< Gray Code LSB Input, offset: 0x180 */ - __IO uint32_t CODE_GRAY_MSB; /**< Gray Code MSB Input, offset: 0x184 */ - __I uint32_t CODE_BIN_LSB; /**< Binary Code LSB Input, offset: 0x188 */ - __I uint32_t CODE_BIN_MSB; /**< Binary Code MSB Input, offset: 0x18C */ -} SYSCTL_Type; - -/* ---------------------------------------------------------------------------- - -- SYSCTL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCTL_Register_Masks SYSCTL Register Masks - * @{ - */ - -/*! @name UPDATELCKOUT - Write Lock Out */ -/*! @{ */ - -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U) -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U) -/*! UPDATELCKOUT - Lock Out - * 0b0..Normal Mode: Allow writes to all registers. - * 0b1..Protected Mode: Do not allow writes to all registers except UPDATELCKOUT. - */ -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK) -/*! @} */ - -/*! @name FCCTRLSEL - Shared Signal Select for Flexcomm 0..Shared Signal Select for Flexcomm 7 */ -/*! @{ */ - -#define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U) -#define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U) -/*! SCKINSEL - SCK Input Select - * 0b00..Selects the dedicated FCn_SCK signal - * 0b01..Selects from shared signal set 0 (SHAREDCTRLSET0) - * 0b10..Selects from shared signal set 1 (SHAREDCTRLSET1) - * 0b11..Reserved - */ -#define SYSCTL_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK) - -#define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U) -#define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U) -/*! WSINSEL - WS Input Select - * 0b00..Selects the dedicated FCn_TXD_SCL_MISO_WS signal - * 0b01..Selects from shared signal set 0 (SHAREDCTRLSET0) - * 0b10..Selects from shared signal set 1 (SHAREDCTRLSET1) - * 0b11..Reserved - */ -#define SYSCTL_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK) - -#define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U) -#define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U) -/*! DATAINSEL - DATA Input Select - * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA input - * 0b01..Selects from shared signal set 0 (SHAREDCTRLSET0) - * 0b10..Selects from shared signal set 1 (SHAREDCTRLSET1) - * 0b11..Reserved - */ -#define SYSCTL_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK) - -#define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U) -#define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U) -/*! DATAOUTSEL - DATA Output Select - * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA output - * 0b01..Selects from shared signal set 0 (SHAREDCTRLSET0) - * 0b10..Selects from shared signal set 1 (SHAREDCTRLSET1) - * 0b11..Reserved - */ -#define SYSCTL_FCCTRLSEL_DATAOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK) -/*! @} */ - -/* The count of SYSCTL_FCCTRLSEL */ -#define SYSCTL_FCCTRLSEL_COUNT (8U) - -/*! @name SHAREDCTRLSET - Shared Signal Set 0..Shared Signal Set 1 */ -/*! @{ */ - -#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U) -#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U) -/*! SHAREDSCKSEL - SCK Source Select - * 0b000..Flexcomm 0 - * 0b001..Flexcomm 1 - * 0b010..Flexcomm 2 - * 0b011..Reserved - * 0b100..Flexcomm 4 - * 0b101..Flexcomm 5 - * 0b110..Flexcomm 6 - * 0b111..Flexcomm 7 - */ -#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK) - -#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U) -#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U) -/*! SHAREDWSSEL - WS Source Select - * 0b000..Flexcomm 0 - * 0b001..Flexcomm 1 - * 0b010..Flexcomm 2 - * 0b011..Reserved - * 0b100..Flexcomm 4 - * 0b101..Flexcomm 5 - * 0b110..Flexcomm 6 - * 0b111..Flexcomm 7 - */ -#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK) - -#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U) -#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U) -/*! SHAREDDATASEL - DATA Input Source Select - * 0b000..Flexcomm 0 - * 0b001..Flexcomm 1 - * 0b010..Flexcomm 2 - * 0b011..Reserved - * 0b100..Flexcomm 4 - * 0b101..Flexcomm 5 - * 0b110..Flexcomm 6 - * 0b111..Flexcomm 7 - */ -#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U) -#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U) -/*! FC0DATAOUTEN - DATAOUT Enable for Flexcomm 0 - * 0b0..Does not contribute - * 0b1..Contributes - */ -#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U) -#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U) -/*! FC1DATAOUTEN - DATAOUT Enable for Flexcomm 1 - * 0b0..Does not contribute - * 0b1..Contributes - */ -#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK (0x40000U) -#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT (18U) -/*! FC2DATAOUTEN - DATAOUT Enable for Flexcomm 2 - * 0b0..Does not contribute - * 0b1..Contributes - */ -#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U) -#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U) -/*! FC4DATAOUTEN - DATAOUT Enable for Flexcomm 4 - * 0b0..Does not contribute - * 0b1..Contributes - */ -#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U) -#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U) -/*! FC5DATAOUTEN - DATAOUT Enable for Flexcomm 5 - * 0b0..Does not contribute - * 0b1..Contributes - */ -#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U) -#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U) -/*! FC6DATAOUTEN - DATAOUT Enable for Flexcomm 6 - * 0b0..Does not contribute - * 0b1..Contributes - */ -#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U) -#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U) -/*! FC7DATAOUTEN - DATAOUT Enable for Flexcomm 7 - * 0b0..Does not contribute - * 0b1..Contributes - */ -#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK) -/*! @} */ - -/* The count of SYSCTL_SHAREDCTRLSET */ -#define SYSCTL_SHAREDCTRLSET_COUNT (2U) - -/*! @name CODE_GRAY_LSB - Gray Code LSB Input */ -/*! @{ */ - -#define SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_MASK (0xFFFFFFFFU) -#define SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_SHIFT (0U) -/*! CODE_GRAY_LSB - Gray code (least-significant) - */ -#define SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_SHIFT)) & SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_MASK) -/*! @} */ - -/*! @name CODE_GRAY_MSB - Gray Code MSB Input */ -/*! @{ */ - -#define SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_MASK (0x3FFU) -#define SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_SHIFT (0U) -/*! CODE_GRAY_MSB - Gray code (most-significant) - */ -#define SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_SHIFT)) & SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_MASK) -/*! @} */ - -/*! @name CODE_BIN_LSB - Binary Code LSB Input */ -/*! @{ */ - -#define SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_MASK (0xFFFFFFFFU) -#define SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_SHIFT (0U) -/*! CODE_BIN_LSB - Binary converted code (least-significant) - */ -#define SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_SHIFT)) & SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_MASK) -/*! @} */ - -/*! @name CODE_BIN_MSB - Binary Code MSB Input */ -/*! @{ */ - -#define SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_MASK (0x3FFU) -#define SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_SHIFT (0U) -/*! CODE_BIN_MSB - Binary converted code (most-significant) - */ -#define SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_SHIFT)) & SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SYSCTL_Register_Masks */ - - -/* SYSCTL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE (0x50023000u) - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE_NS (0x40023000u) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL_NS ((SYSCTL_Type *)SYSCTL_BASE_NS) - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS { SYSCTL } - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS_NS { SYSCTL_BASE_NS } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS_NS { SYSCTL_NS } -#else - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE (0x40023000u) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS { SYSCTL } -#endif - -/*! - * @} - */ /* end of group SYSCTL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USART Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer - * @{ - */ - -/** USART - Register Layout Typedef */ -typedef struct { - __IO uint32_t CFG; /**< USART Configuration, offset: 0x0 */ - __IO uint32_t CTL; /**< USART Control, offset: 0x4 */ - __IO uint32_t STAT; /**< USART Status, offset: 0x8 */ - __IO uint32_t INTENSET; /**< Interrupt Enable Read and Set for USART (not FIFO) Status, offset: 0xC */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear, offset: 0x10 */ - uint8_t RESERVED_0[12]; - __IO uint32_t BRG; /**< Baud Rate Generator, offset: 0x20 */ - __I uint32_t INTSTAT; /**< Interrupt Status, offset: 0x24 */ - __IO uint32_t OSR; /**< Oversample Selection Register for Asynchronous Communication, offset: 0x28 */ - __IO uint32_t ADDR; /**< Address Register for Automatic Address Matching, offset: 0x2C */ - uint8_t RESERVED_1[3536]; - __IO uint32_t FIFOCFG; /**< FIFO Configuration, offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO Status, offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO Trigger Settings for Interrupt and DMA Request, offset: 0xE08 */ - uint8_t RESERVED_2[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO Interrupt Enable, offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO Interrupt Enable Clear, offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO Interrupt Status, offset: 0xE18 */ - uint8_t RESERVED_3[4]; - __O uint32_t FIFOWR; /**< FIFO Write Data, offset: 0xE20 */ - uint8_t RESERVED_4[12]; - __I uint32_t FIFORD; /**< FIFO Read Data, offset: 0xE30 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO Data Read with No FIFO Pop, offset: 0xE40 */ - uint8_t RESERVED_6[4]; - __I uint32_t FIFOSIZE; /**< FIFO Size, offset: 0xE48 */ - __IO uint32_t FIFORXTIMEOUTCFG; /**< FIFO Receive Timeout Configuration, offset: 0xE4C */ - __I uint32_t FIFORXTIMEOUTCNT; /**< FIFO Receive Timeout Counter, offset: 0xE50 */ - uint8_t RESERVED_7[424]; - __I uint32_t ID; /**< Peripheral Identification, offset: 0xFFC */ -} USART_Type; - -/* ---------------------------------------------------------------------------- - -- USART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Register_Masks USART Register Masks - * @{ - */ - -/*! @name CFG - USART Configuration */ -/*! @{ */ - -#define USART_CFG_ENABLE_MASK (0x1U) -#define USART_CFG_ENABLE_SHIFT (0U) -/*! ENABLE - USART Enable - * 0b0..Disabled - * 0b1..Enabled. The USART is enabled for operation. - */ -#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) - -#define USART_CFG_DATALEN_MASK (0xCU) -#define USART_CFG_DATALEN_SHIFT (2U) -/*! DATALEN - Data Length. Selects the data size for the USART. - * 0b00..7 bit data length - * 0b01..8 bit data length - * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET[CTL]. - * 0b11..Reserved - */ -#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) - -#define USART_CFG_PARITYSEL_MASK (0x30U) -#define USART_CFG_PARITYSEL_SHIFT (4U) -/*! PARITYSEL - Parity Select. Selects what type of parity is used by the USART. - * 0b00..No parity - * 0b01..Reserved - * 0b10..Even parity - * 0b11..Odd parity - */ -#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) - -#define USART_CFG_STOPLEN_MASK (0x40U) -#define USART_CFG_STOPLEN_SHIFT (6U) -/*! STOPLEN - Stop Length - * 0b0..1 stop bit - * 0b1..2 stop bits. This setting should be used only for asynchronous communication. - */ -#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) - -#define USART_CFG_MODE32K_MASK (0x80U) -#define USART_CFG_MODE32K_SHIFT (7U) -/*! MODE32K - Mode 32 kHz - * 0b0..Disabled. USART uses standard clocking. - * 0b1..Enabled - */ -#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) - -#define USART_CFG_LINMODE_MASK (0x100U) -#define USART_CFG_LINMODE_SHIFT (8U) -/*! LINMODE - LIN Break Mode Enable - * 0b0..Disabled. Break detect and generate is configured for normal operation. - * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. - */ -#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) - -#define USART_CFG_CTSEN_MASK (0x200U) -#define USART_CFG_CTSEN_SHIFT (9U) -/*! CTSEN - CTS Enable - * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. - * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. - */ -#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) - -#define USART_CFG_SYNCEN_MASK (0x800U) -#define USART_CFG_SYNCEN_SHIFT (11U) -/*! SYNCEN - Synchronous Enable. Selects synchronous or asynchronous operation. - * 0b0..Asynchronous mode - * 0b1..Synchronous mode - */ -#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) - -#define USART_CFG_CLKPOL_MASK (0x1000U) -#define USART_CFG_CLKPOL_SHIFT (12U) -/*! CLKPOL - Clock Polarity - * 0b0..Falling edge. RXD is sampled on the falling edge of SCLK. - * 0b1..Rising edge. RXD is sampled on the rising edge of SCLK. - */ -#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) - -#define USART_CFG_SYNCMST_MASK (0x4000U) -#define USART_CFG_SYNCMST_SHIFT (14U) -/*! SYNCMST - Synchronous mode Master Select - * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. - * 0b1..Master. When synchronous mode is enabled, the USART is a master. - */ -#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) - -#define USART_CFG_LOOP_MASK (0x8000U) -#define USART_CFG_LOOP_SHIFT (15U) -/*! LOOP - Loopback Mode - * 0b0..Normal operation - * 0b1..Loopback mode - */ -#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) - -#define USART_CFG_OETA_MASK (0x40000U) -#define USART_CFG_OETA_SHIFT (18U) -/*! OETA - Output Enable Turnaround Time Enable for RS-485 Operation. - * 0b0..Disabled - * 0b1..Enabled - */ -#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) - -#define USART_CFG_AUTOADDR_MASK (0x80000U) -#define USART_CFG_AUTOADDR_SHIFT (19U) -/*! AUTOADDR - Automatic Address Matching Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) - -#define USART_CFG_OESEL_MASK (0x100000U) -#define USART_CFG_OESEL_SHIFT (20U) -/*! OESEL - Output Enable Select - * 0b0..Standard. The RTS signal is used as the standard flow control function. - * 0b1..RS-485. The RTS signal is configured to provide an output enable signal to control an RS-485 transceiver. - */ -#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) - -#define USART_CFG_OEPOL_MASK (0x200000U) -#define USART_CFG_OEPOL_SHIFT (21U) -/*! OEPOL - Output Enable Polarity - * 0b0..Low. If selected by OESEL, the output enable is active low. - * 0b1..High. If selected by OESEL, the output enable is active high. - */ -#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) - -#define USART_CFG_RXPOL_MASK (0x400000U) -#define USART_CFG_RXPOL_SHIFT (22U) -/*! RXPOL - Receive Data Polarity - * 0b0..Standard - * 0b1..Inverted - */ -#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) - -#define USART_CFG_TXPOL_MASK (0x800000U) -#define USART_CFG_TXPOL_SHIFT (23U) -/*! TXPOL - Transmit data polarity - * 0b0..Standard - * 0b1..Inverted - */ -#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) -/*! @} */ - -/*! @name CTL - USART Control */ -/*! @{ */ - -#define USART_CTL_TXBRKEN_MASK (0x2U) -#define USART_CTL_TXBRKEN_SHIFT (1U) -/*! TXBRKEN - Break Enable - * 0b0..Normal operation - * 0b1..Continuous break - */ -#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) - -#define USART_CTL_ADDRDET_MASK (0x4U) -#define USART_CTL_ADDRDET_SHIFT (2U) -/*! ADDRDET - Enable Address Detect Mode - * 0b0..Disabled. The USART presents all incoming data. - * 0b1..Enabled - */ -#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) - -#define USART_CTL_TXDIS_MASK (0x40U) -#define USART_CTL_TXDIS_SHIFT (6U) -/*! TXDIS - Transmit Disable - * 0b0..Not disabled. USART transmitter is not disabled. - * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This - * feature can be used to facilitate software flow control. - */ -#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) - -#define USART_CTL_CC_MASK (0x100U) -#define USART_CTL_CC_SHIFT (8U) -/*! CC - Continuous Clock Generation - * 0b0..Clock on character - * 0b1..Continuous clock - */ -#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) - -#define USART_CTL_CLRCCONRX_MASK (0x200U) -#define USART_CTL_CLRCCONRX_SHIFT (9U) -/*! CLRCCONRX - Clear Continuous Clock - * 0b0..No effect. No effect on the CC bit. - * 0b1..Auto-clear - */ -#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) - -#define USART_CTL_AUTOBAUD_MASK (0x10000U) -#define USART_CTL_AUTOBAUD_SHIFT (16U) -/*! AUTOBAUD - Autobaud Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) -/*! @} */ - -/*! @name STAT - USART Status */ -/*! @{ */ - -#define USART_STAT_RXIDLE_MASK (0x2U) -#define USART_STAT_RXIDLE_SHIFT (1U) -/*! RXIDLE - Receiver Idle - * 0b0..The receiver is currently receiving data. - * 0b1..The receiver is not currently receiving data. - */ -#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) - -#define USART_STAT_TXIDLE_MASK (0x8U) -#define USART_STAT_TXIDLE_SHIFT (3U) -/*! TXIDLE - Transmitter Idle - * 0b0..The transmitter is currently sending data. - * 0b1..The transmitter is not currently sending data. - */ -#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) - -#define USART_STAT_CTS_MASK (0x10U) -#define USART_STAT_CTS_SHIFT (4U) -/*! CTS - CTS value - */ -#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) - -#define USART_STAT_DELTACTS_MASK (0x20U) -#define USART_STAT_DELTACTS_SHIFT (5U) -/*! DELTACTS - Delta CTS - */ -#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) - -#define USART_STAT_TXDISSTAT_MASK (0x40U) -#define USART_STAT_TXDISSTAT_SHIFT (6U) -/*! TXDISSTAT - Transmitter Disabled Status Flag - * 0b0..Not Idle. Indicates that the USART transmitter is NOT fully idle after being disabled. - * 0b1..Idle. Indicates that the USART transmitter is fully idle after being disabled (CTL[TXDIS] = 1). - */ -#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) - -#define USART_STAT_RXBRK_MASK (0x400U) -#define USART_STAT_RXBRK_SHIFT (10U) -/*! RXBRK - Received Break - */ -#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) - -#define USART_STAT_DELTARXBRK_MASK (0x800U) -#define USART_STAT_DELTARXBRK_SHIFT (11U) -/*! DELTARXBRK - Delta Received Break - */ -#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) - -#define USART_STAT_START_MASK (0x1000U) -#define USART_STAT_START_SHIFT (12U) -/*! START - Start - */ -#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) - -#define USART_STAT_FRAMERRINT_MASK (0x2000U) -#define USART_STAT_FRAMERRINT_SHIFT (13U) -/*! FRAMERRINT - Framing Error Interrupt Flag - */ -#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) - -#define USART_STAT_PARITYERRINT_MASK (0x4000U) -#define USART_STAT_PARITYERRINT_SHIFT (14U) -/*! PARITYERRINT - Parity Error Interrupt Flag - */ -#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) - -#define USART_STAT_RXNOISEINT_MASK (0x8000U) -#define USART_STAT_RXNOISEINT_SHIFT (15U) -/*! RXNOISEINT - Received Noise Interrupt Flag - */ -#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) - -#define USART_STAT_ABERR_MASK (0x10000U) -#define USART_STAT_ABERR_SHIFT (16U) -/*! ABERR - Auto Baud Error - */ -#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable Read and Set for USART (not FIFO) Status */ -/*! @{ */ - -#define USART_INTENSET_TXIDLEEN_MASK (0x8U) -#define USART_INTENSET_TXIDLEEN_SHIFT (3U) -/*! TXIDLEEN - Transmit Idle Flag - * 0b1..Enables an interrupt when the transmitter becomes idle (STAT[TXIDLE] = 1). - */ -#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) - -#define USART_INTENSET_DELTACTSEN_MASK (0x20U) -#define USART_INTENSET_DELTACTSEN_SHIFT (5U) -/*! DELTACTSEN - Delta CTS Input Flag - * 0b1..Enables an interrupt when there is a change in the state of the CTS input. - */ -#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) - -#define USART_INTENSET_TXDISEN_MASK (0x40U) -#define USART_INTENSET_TXDISEN_SHIFT (6U) -/*! TXDISEN - Transmit Disabled Flag - * 0b1..Enables an interrupt when the transmitter is fully disabled as indicated by the STAT[TXDISINT] flag. See - * the description of the STAT[TXDISINT] flag. - */ -#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) - -#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) -#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) -/*! DELTARXBRKEN - Delta Receive Break Enable - * 0b1..Enable - */ -#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) - -#define USART_INTENSET_STARTEN_MASK (0x1000U) -#define USART_INTENSET_STARTEN_SHIFT (12U) -/*! STARTEN - Start Enable - * 0b1..Enables an interrupt when a received start bit has been detected. - */ -#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) - -#define USART_INTENSET_FRAMERREN_MASK (0x2000U) -#define USART_INTENSET_FRAMERREN_SHIFT (13U) -/*! FRAMERREN - Frame Error Enable - * 0b1..Enables an interrupt when a framing error has been detected. - */ -#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) - -#define USART_INTENSET_PARITYERREN_MASK (0x4000U) -#define USART_INTENSET_PARITYERREN_SHIFT (14U) -/*! PARITYERREN - Parity Error Enble - * 0b1..Enables an interrupt when a parity error has been detected. - */ -#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) - -#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) -#define USART_INTENSET_RXNOISEEN_SHIFT (15U) -/*! RXNOISEEN - Receive Noise Enable - * 0b1..Enables an interrupt when noise is detected. See the description of the CTL[RXNOISEINT] bit. - */ -#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) - -#define USART_INTENSET_ABERREN_MASK (0x10000U) -#define USART_INTENSET_ABERREN_SHIFT (16U) -/*! ABERREN - Auto Baud Error Enable - * 0b1..Enables an interrupt when an auto baud error occurs. - */ -#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear */ -/*! @{ */ - -#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) -#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) -/*! TXIDLECLR - Transmit Idle Clear - */ -#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) - -#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) -#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) -/*! DELTACTSCLR - Delta CTS Clear - */ -#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) - -#define USART_INTENCLR_TXDISCLR_MASK (0x40U) -#define USART_INTENCLR_TXDISCLR_SHIFT (6U) -/*! TXDISCLR - Transmit Disable Clear - */ -#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) - -#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) -#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) -/*! DELTARXBRKCLR - Delta Receive Break Clear - */ -#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) - -#define USART_INTENCLR_STARTCLR_MASK (0x1000U) -#define USART_INTENCLR_STARTCLR_SHIFT (12U) -/*! STARTCLR - Start Clear - */ -#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) - -#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) -#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) -/*! FRAMERRCLR - Frame Error Clear - */ -#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) - -#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) -#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) -/*! PARITYERRCLR - Parity Error Clear - */ -#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) - -#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) -#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) -/*! RXNOISECLR - Receive Noise Clear - */ -#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) - -#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) -#define USART_INTENCLR_ABERRCLR_SHIFT (16U) -/*! ABERRCLR - Auto Baud Error Clear - */ -#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) -/*! @} */ - -/*! @name BRG - Baud Rate Generator */ -/*! @{ */ - -#define USART_BRG_BRGVAL_MASK (0xFFFFU) -#define USART_BRG_BRGVAL_SHIFT (0U) -/*! BRGVAL - Baud Rate Generator Value - * 0b0000000000000000..FCLK is used directly by the USART function. - * 0b0000000000000001..FCLK is divided by 2 before use by the USART function. - * 0b0000000000000010..FCLK is divided by 3 before use by the USART function. - * 0b1111111111111111..FCLK is divided by 65,536 before use by the USART function. - */ -#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt Status */ -/*! @{ */ - -#define USART_INTSTAT_TXIDLE_MASK (0x8U) -#define USART_INTSTAT_TXIDLE_SHIFT (3U) -/*! TXIDLE - Transmitter Idle Flag - */ -#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) - -#define USART_INTSTAT_DELTACTS_MASK (0x20U) -#define USART_INTSTAT_DELTACTS_SHIFT (5U) -/*! DELTACTS - Delta CTS Change Flag - */ -#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) - -#define USART_INTSTAT_TXDISINT_MASK (0x40U) -#define USART_INTSTAT_TXDISINT_SHIFT (6U) -/*! TXDISINT - Transmitter Disabled Interrupt Flag - */ -#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) - -#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) -#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) -/*! DELTARXBRK - Delta Receiver Break Change Flag - */ -#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) - -#define USART_INTSTAT_START_MASK (0x1000U) -#define USART_INTSTAT_START_SHIFT (12U) -/*! START - Start Detected on Receiver Flag - */ -#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) - -#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) -#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) -/*! FRAMERRINT - Framing Error Interrupt Flag - */ -#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) - -#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) -#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) -/*! PARITYERRINT - Parity Error Interrupt Flag - */ -#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) - -#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) -#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) -/*! RXNOISEINT - Received Noise Interrupt Flag - */ -#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) - -#define USART_INTSTAT_ABERRINT_MASK (0x10000U) -#define USART_INTSTAT_ABERRINT_SHIFT (16U) -/*! ABERRINT - Auto Baud Error Interrupt Flag - */ -#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) -/*! @} */ - -/*! @name OSR - Oversample Selection Register for Asynchronous Communication */ -/*! @{ */ - -#define USART_OSR_OSRVAL_MASK (0xFU) -#define USART_OSR_OSRVAL_SHIFT (0U) -/*! OSRVAL - Oversample Selection Value - * 0b0000..Not supported - * 0b0001..Not supported - * 0b0010..Not supported - * 0b0011..Not supported - * 0b0100..5 function clocks are used to transmit and receive each data bit. - * 0b0101..6 function clocks are used to transmit and receive each data bit. - * 0b1111..16 function clocks are used to transmit and receive each data bit. - */ -#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) -/*! @} */ - -/*! @name ADDR - Address Register for Automatic Address Matching */ -/*! @{ */ - -#define USART_ADDR_ADDRESS_MASK (0xFFU) -#define USART_ADDR_ADDRESS_SHIFT (0U) -/*! ADDRESS - Address - */ -#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO Configuration */ -/*! @{ */ - -#define USART_FIFOCFG_ENABLETX_MASK (0x1U) -#define USART_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the Transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) - -#define USART_FIFOCFG_ENABLERX_MASK (0x2U) -#define USART_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the Receive FIFO - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) - -#define USART_FIFOCFG_SIZE_MASK (0x30U) -#define USART_FIFOCFG_SIZE_SHIFT (4U) -/*! SIZE - FIFO Size Configuration - * 0b00..FIFO is configured as 16 entries of 8 bits. - * 0b01..Not used - * 0b10..Not used - * 0b11..Not used - */ -#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) - -#define USART_FIFOCFG_DMATX_MASK (0x1000U) -#define USART_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA Configuration for Transmit - * 0b0..DMA is not used for the transmit function. - * 0b1..Triggers DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) - -#define USART_FIFOCFG_DMARX_MASK (0x2000U) -#define USART_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA Configuration for Receive - * 0b0..DMA is not used for the receive function. - * 0b1..Triggers DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) - -#define USART_FIFOCFG_WAKETX_MASK (0x4000U) -#define USART_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for Transmit FIFO Level - * 0b0..Only enabled interrupts will wake up the device from low power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by - * FIFOTRIG[TXLVL], even when the TXLVL interrupt is not enabled. - */ -#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) - -#define USART_FIFOCFG_WAKERX_MASK (0x8000U) -#define USART_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for Receive FIFO Level - * 0b0..Only enabled interrupts will wake up the device from low power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by - * FIFOTRIG[RXLVL], even when the RXLVL interrupt is not enabled. - */ -#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) - -#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) -/*! EMPTYTX - Empty Command for the Transmit FIFO - * 0b0..No effect - * 0b1..The TX FIFO is emptied. - */ -#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) - -#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) -/*! EMPTYRX - Empty Command for the Receive FIFO - * 0b0..No effect - * 0b1..The RX FIFO is emptied. - */ -#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) - -#define USART_FIFOCFG_POPDBG_MASK (0x40000U) -#define USART_FIFOCFG_POPDBG_SHIFT (18U) -/*! POPDBG - Pop FIFO for Debug Reads - * 0b0..Debug reads of the FIFO do not pop the FIFO. - * 0b1..A debug read will cause the FIFO to pop. - */ -#define USART_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO Status */ -/*! @{ */ - -#define USART_FIFOSTAT_TXERR_MASK (0x1U) -#define USART_FIFOSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO Error - * 0b0..A transmit FIFO error has not occurred. - * 0b1..A transmit FIFO error has occurred. This error could be an overflow caused by pushing data into a full - * FIFO, or by an underflow if the FIFO is empty when data is needed. - */ -#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) - -#define USART_FIFOSTAT_RXERR_MASK (0x2U) -#define USART_FIFOSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO Error - * 0b0..A receive FIFO overflow has not occurred - * 0b1..A receive FIFO overflow has occurred, caused by software or DMA not emptying the FIFO fast enough - */ -#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) - -#define USART_FIFOSTAT_PERINT_MASK (0x8U) -#define USART_FIFOSTAT_PERINT_SHIFT (3U) -/*! PERINT - Peripheral Interrupt - * 0b0..No Peripheral Interrupt - * 0b1..Peripheral Interrupt - */ -#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) - -#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) -/*! TXEMPTY - Transmit FIFO Empty - * 0b0..The transmit FIFO is not empty. - * 0b1..The transmit FIFO is empty, although the peripheral may still be processing the last piece of data. - */ -#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) - -#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) -/*! TXNOTFULL - Transmit FIFO is Not Full - * 0b0..The transmit FIFO is full and another write would cause it to overflow. - * 0b1..The transmit FIFO is not full, so more data can be written. - */ -#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) - -#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -/*! RXNOTEMPTY - Receive FIFO is Not Empty - * 0b0..The receive FIFO is empty. - * 0b1..The receive FIFO is not empty, so data can be read. - */ -#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) - -#define USART_FIFOSTAT_RXFULL_MASK (0x80U) -#define USART_FIFOSTAT_RXFULL_SHIFT (7U) -/*! RXFULL - Receive FIFO is Full - * 0b0..The receive FIFO is not full. - * 0b1..The receive FIFO is full. - */ -#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) - -#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define USART_FIFOSTAT_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO Current Level - */ -#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) - -#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define USART_FIFOSTAT_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO Current Level - */ -#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) - -#define USART_FIFOSTAT_RXTIMEOUT_MASK (0x1000000U) -#define USART_FIFOSTAT_RXTIMEOUT_SHIFT (24U) -/*! RXTIMEOUT - Receive FIFO Timeout - * 0b0..RX FIFO on - * 0b1..RX FIFO has timed out, based on the timeout configuration in the FIFORXTIMEOUTCFG register. - */ -#define USART_FIFOSTAT_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXTIMEOUT_SHIFT)) & USART_FIFOSTAT_RXTIMEOUT_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO Trigger Settings for Interrupt and DMA Request */ -/*! @{ */ - -#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO Level Trigger Enable. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..A trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field. - */ -#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) - -#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO Level Trigger Enable - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field. - */ -#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) - -#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) -#define USART_FIFOTRIG_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO Level Trigger Point - * 0b0000..Trigger when the TX FIFO becomes empty - * 0b0001..Trigger when the TX FIFO level decreases to 1 entry - * 0b1111..Trigger when the TX FIFO level decreases to 15 entries (is no longer full) - */ -#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) - -#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define USART_FIFOTRIG_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO Level Trigger Point - * 0b0000..Trigger when the RX FIFO has received 1 entry (is no longer empty) - * 0b0001..Trigger when the RX FIFO has received 2 entries - * 0b1111..Trigger when the RX FIFO has received 16 entries (has become full) - */ -#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO Interrupt Enable */ -/*! @{ */ - -#define USART_FIFOINTENSET_TXERR_MASK (0x1U) -#define USART_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Transmit Error Interrupt Enable - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) - -#define USART_FIFOINTENSET_RXERR_MASK (0x2U) -#define USART_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Receive Error Interrupt Enable - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) - -#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) -#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO Level Interrupt Enable - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If FIFOTRIG[TXLVLENA] = 1, then an interrupt will be generated when the TX FIFO level decreases to the level specified by FIFOTRIG[TXLVL] - */ -#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) - -#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) -#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO Level Interrupt Enable - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If FIFOTRIG[RXLVLENA] = 1, an interrupt will be generated when the when the RX FIFO level increases to - * the level specified by FIFOTRIG[RXLVL]. - */ -#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) - -#define USART_FIFOINTENSET_RXTIMEOUT_MASK (0x1000000U) -#define USART_FIFOINTENSET_RXTIMEOUT_SHIFT (24U) -/*! RXTIMEOUT - Receive Timeout - * 0b0..No RX interrupt will be generated. - * 0b1..Asserts RX interrupt if RX FIFO Timeout event occurs. - */ -#define USART_FIFOINTENSET_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXTIMEOUT_SHIFT)) & USART_FIFOINTENSET_RXTIMEOUT_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO Interrupt Enable Clear */ -/*! @{ */ - -#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) -#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) -/*! TXERR - Transmit Error Interrupt Enable - * 0b0..No effect - * 0b1..Clear the interrupt - */ -#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) - -#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) -#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) -/*! RXERR - Receive Error Interrupt Enable - * 0b0..No effect - * 0b1..Clear the interrupt - */ -#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) - -#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO Level Interrupt Enable - * 0b0..No effect - * 0b1..Clear the interrupt - */ -#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) - -#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO Level Interrupt Enable - * 0b0..No effect - * 0b1..Clear the interrupt - */ -#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) - -#define USART_FIFOINTENCLR_RXTIMEOUT_MASK (0x1000000U) -#define USART_FIFOINTENCLR_RXTIMEOUT_SHIFT (24U) -/*! RXTIMEOUT - Receive Timeout - * 0b0..No effect - * 0b1..Clear the interrupt - */ -#define USART_FIFOINTENCLR_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXTIMEOUT_SHIFT)) & USART_FIFOINTENCLR_RXTIMEOUT_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO Interrupt Status */ -/*! @{ */ - -#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) -#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO Error Interrupt Status - * 0b0..Not pending - * 0b1..Pending - */ -#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) - -#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) -#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO Error Interrupt Status - * 0b0..Not pending - * 0b1..Pending - */ -#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) - -#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO Level Interrupt Status - * 0b0..Not pending - * 0b1..Pending - */ -#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) - -#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO Level Interrupt Status - * 0b0..Not pending - * 0b1..Pending - */ -#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) - -#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) -#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) -/*! PERINT - Peripheral Interrupt Status - * 0b0..Not pending - * 0b1..Pending - */ -#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) - -#define USART_FIFOINTSTAT_RXTIMEOUT_MASK (0x1000000U) -#define USART_FIFOINTSTAT_RXTIMEOUT_SHIFT (24U) -/*! RXTIMEOUT - Receive Timeout Status - * 0b0..Not pending - * 0b1..Pending - */ -#define USART_FIFOINTSTAT_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXTIMEOUT_SHIFT)) & USART_FIFOINTSTAT_RXTIMEOUT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO Write Data */ -/*! @{ */ - -#define USART_FIFOWR_TXDATA_MASK (0x1FFU) -#define USART_FIFOWR_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit data to the FIFO - */ -#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO Read Data */ -/*! @{ */ - -#define USART_FIFORD_RXDATA_MASK (0x1FFU) -#define USART_FIFORD_RXDATA_SHIFT (0U) -/*! RXDATA - Received Data from the FIFO - */ -#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) - -#define USART_FIFORD_FRAMERR_MASK (0x2000U) -#define USART_FIFORD_FRAMERR_SHIFT (13U) -/*! FRAMERR - Framing Error Status Flag - */ -#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) - -#define USART_FIFORD_PARITYERR_MASK (0x4000U) -#define USART_FIFORD_PARITYERR_SHIFT (14U) -/*! PARITYERR - Parity Error Status Flag - */ -#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) - -#define USART_FIFORD_RXNOISE_MASK (0x8000U) -#define USART_FIFORD_RXNOISE_SHIFT (15U) -/*! RXNOISE - Received Noise Flag - */ -#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO Data Read with No FIFO Pop */ -/*! @{ */ - -#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) -#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received Data from the FIFO - */ -#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) - -#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) -#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) -/*! FRAMERR - Framing Error Status Flag - */ -#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) - -#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) -#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) -/*! PARITYERR - Parity Error Status Flag - */ -#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) - -#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) -#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) -/*! RXNOISE - Received Noise Flag - */ -#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) -/*! @} */ - -/*! @name FIFOSIZE - FIFO Size */ -/*! @{ */ - -#define USART_FIFOSIZE_FIFOSIZE_MASK (0x1FU) -#define USART_FIFOSIZE_FIFOSIZE_SHIFT (0U) -/*! FIFOSIZE - FIFO Size - */ -#define USART_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSIZE_FIFOSIZE_SHIFT)) & USART_FIFOSIZE_FIFOSIZE_MASK) -/*! @} */ - -/*! @name FIFORXTIMEOUTCFG - FIFO Receive Timeout Configuration */ -/*! @{ */ - -#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK (0xFFU) -#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT (0U) -/*! RXTIMEOUT_PRESCALER - Receive Timeout Counter Clock Prescaler - */ -#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT)) & USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK) - -#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK (0xFFFF00U) -#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT (8U) -/*! RXTIMEOUT_VALUE - Receive Timeout Value - */ -#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT)) & USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK) - -#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK (0x1000000U) -#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT (24U) -/*! RXTIMEOUT_EN - Receive Timeout Enable - * 0b0..Disable RX FIFO timeout - * 0b1..Enable RX FIFO timeout - */ -#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT)) & USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK) - -#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK (0x2000000U) -#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT (25U) -/*! RXTIMEOUT_COW - Receive Timeout Continue On Write - * 0b0..RX FIFO timeout counter is reset every time data is transferred from the peripheral into the RX FIFO. - * 0b1..RX FIFO timeout counter is not reset every time data is transferred from the peripheral into the RX FIFO. - */ -#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT)) & USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK) - -#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK (0x4000000U) -#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT (26U) -/*! RXTIMEOUT_COE - Receive Timeout Continue On Empty - * 0b0..RX FIFO timeout counter is reset when the RX FIFO becomes empty. - * 0b1..RX FIFO timeout counter is not reset when the RX FIFO becomes empty. - */ -#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT)) & USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK) -/*! @} */ - -/*! @name FIFORXTIMEOUTCNT - FIFO Receive Timeout Counter */ -/*! @{ */ - -#define USART_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK (0xFFFFU) -#define USART_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT (0U) -/*! RXTIMEOUT_CNT - Current RX FIFO timeout counter value - */ -#define USART_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT)) & USART_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK) -/*! @} */ - -/*! @name ID - Peripheral Identification */ -/*! @{ */ - -#define USART_ID_APERTURE_MASK (0xFFU) -#define USART_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture - */ -#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) - -#define USART_ID_MINOR_REV_MASK (0xF00U) -#define USART_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation - */ -#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) - -#define USART_ID_MAJOR_REV_MASK (0xF000U) -#define USART_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation - */ -#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) - -#define USART_ID_ID_MASK (0xFFFF0000U) -#define USART_ID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function - */ -#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USART_Register_Masks */ - - -/* USART - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USART0 base address */ - #define USART0_BASE (0x50086000u) - /** Peripheral USART0 base address */ - #define USART0_BASE_NS (0x40086000u) - /** Peripheral USART0 base pointer */ - #define USART0 ((USART_Type *)USART0_BASE) - /** Peripheral USART0 base pointer */ - #define USART0_NS ((USART_Type *)USART0_BASE_NS) - /** Peripheral USART1 base address */ - #define USART1_BASE (0x50087000u) - /** Peripheral USART1 base address */ - #define USART1_BASE_NS (0x40087000u) - /** Peripheral USART1 base pointer */ - #define USART1 ((USART_Type *)USART1_BASE) - /** Peripheral USART1 base pointer */ - #define USART1_NS ((USART_Type *)USART1_BASE_NS) - /** Peripheral USART2 base address */ - #define USART2_BASE (0x50088000u) - /** Peripheral USART2 base address */ - #define USART2_BASE_NS (0x40088000u) - /** Peripheral USART2 base pointer */ - #define USART2 ((USART_Type *)USART2_BASE) - /** Peripheral USART2 base pointer */ - #define USART2_NS ((USART_Type *)USART2_BASE_NS) - /** Peripheral USART3 base address */ - #define USART3_BASE (0x50089000u) - /** Peripheral USART3 base address */ - #define USART3_BASE_NS (0x40089000u) - /** Peripheral USART3 base pointer */ - #define USART3 ((USART_Type *)USART3_BASE) - /** Peripheral USART3 base pointer */ - #define USART3_NS ((USART_Type *)USART3_BASE_NS) - /** Peripheral USART4 base address */ - #define USART4_BASE (0x5008A000u) - /** Peripheral USART4 base address */ - #define USART4_BASE_NS (0x4008A000u) - /** Peripheral USART4 base pointer */ - #define USART4 ((USART_Type *)USART4_BASE) - /** Peripheral USART4 base pointer */ - #define USART4_NS ((USART_Type *)USART4_BASE_NS) - /** Peripheral USART5 base address */ - #define USART5_BASE (0x50096000u) - /** Peripheral USART5 base address */ - #define USART5_BASE_NS (0x40096000u) - /** Peripheral USART5 base pointer */ - #define USART5 ((USART_Type *)USART5_BASE) - /** Peripheral USART5 base pointer */ - #define USART5_NS ((USART_Type *)USART5_BASE_NS) - /** Peripheral USART6 base address */ - #define USART6_BASE (0x50097000u) - /** Peripheral USART6 base address */ - #define USART6_BASE_NS (0x40097000u) - /** Peripheral USART6 base pointer */ - #define USART6 ((USART_Type *)USART6_BASE) - /** Peripheral USART6 base pointer */ - #define USART6_NS ((USART_Type *)USART6_BASE_NS) - /** Peripheral USART7 base address */ - #define USART7_BASE (0x50098000u) - /** Peripheral USART7 base address */ - #define USART7_BASE_NS (0x40098000u) - /** Peripheral USART7 base pointer */ - #define USART7 ((USART_Type *)USART7_BASE) - /** Peripheral USART7 base pointer */ - #define USART7_NS ((USART_Type *)USART7_BASE_NS) - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS_NS { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS_NS { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS } -#else - /** Peripheral USART0 base address */ - #define USART0_BASE (0x40086000u) - /** Peripheral USART0 base pointer */ - #define USART0 ((USART_Type *)USART0_BASE) - /** Peripheral USART1 base address */ - #define USART1_BASE (0x40087000u) - /** Peripheral USART1 base pointer */ - #define USART1 ((USART_Type *)USART1_BASE) - /** Peripheral USART2 base address */ - #define USART2_BASE (0x40088000u) - /** Peripheral USART2 base pointer */ - #define USART2 ((USART_Type *)USART2_BASE) - /** Peripheral USART3 base address */ - #define USART3_BASE (0x40089000u) - /** Peripheral USART3 base pointer */ - #define USART3 ((USART_Type *)USART3_BASE) - /** Peripheral USART4 base address */ - #define USART4_BASE (0x4008A000u) - /** Peripheral USART4 base pointer */ - #define USART4 ((USART_Type *)USART4_BASE) - /** Peripheral USART5 base address */ - #define USART5_BASE (0x40096000u) - /** Peripheral USART5 base pointer */ - #define USART5 ((USART_Type *)USART5_BASE) - /** Peripheral USART6 base address */ - #define USART6_BASE (0x40097000u) - /** Peripheral USART6 base pointer */ - #define USART6 ((USART_Type *)USART6_BASE) - /** Peripheral USART7 base address */ - #define USART7_BASE (0x40098000u) - /** Peripheral USART7 base pointer */ - #define USART7 ((USART_Type *)USART7_BASE) - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } -#endif -/** Interrupt vectors for the USART peripheral type */ -#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group USART_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer - * @{ - */ - -/** USB - Register Layout Typedef */ -typedef struct { - __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status, offset: 0x0 */ - __IO uint32_t INFO; /**< USB Info, offset: 0x4 */ - __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ - __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ - __IO uint32_t LPM; /**< USB Link Power Management, offset: 0x10 */ - __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ - __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ - __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration, offset: 0x1C */ - __IO uint32_t INTSTAT; /**< USB interrupt status, offset: 0x20 */ - __IO uint32_t INTEN; /**< USB interrupt enable, offset: 0x24 */ - __IO uint32_t INTSETSTAT; /**< USB set interrupt status, offset: 0x28 */ - uint8_t RESERVED_0[8]; - __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle, offset: 0x34 */ -} USB_Type; - -/* ---------------------------------------------------------------------------- - -- USB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Register_Masks USB Register Masks - * @{ - */ - -/*! @name DEVCMDSTAT - USB Device Command/Status */ -/*! @{ */ - -#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) -#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) -/*! DEV_ADDR - USB device address - */ -#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) - -#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) -#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) -/*! DEV_EN - USB device enable - */ -#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) - -#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) -#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) -/*! SETUP - SETUP token received - */ -#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) - -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) -/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: - * 0b0..USB_NEEDCLK has normal function. - * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. - */ -#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) - -#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) -#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) -/*! LPM_SUP - LPM Support - * 0b0..LPM not supported. - * 0b1..LPM supported. - */ -#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) - -#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) -#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) -/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) - -#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) -#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) -/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) - -#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) -#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) -/*! INTONNAK_CO - Interrupt on NAK for control OUT EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) - -#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) -#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) -/*! INTONNAK_CI - Interrupt on NAK for control IN EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) - -#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) -#define USB_DEVCMDSTAT_DCON_SHIFT (16U) -/*! DCON - Device status - connect - */ -#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) - -#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) -#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) -/*! DSUS - Device status - suspend - */ -#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) - -#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) -#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) -/*! LPM_SUS - Device status - LPM Suspend - */ -#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) - -#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) -#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) -/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host - */ -#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) - -#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) -#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) -/*! DCON_C - Device status - connect change - */ -#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) - -#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) -#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) -/*! DSUS_C - Device status - suspend change - */ -#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) - -#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) -#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) -/*! DRES_C - Device status - reset change - */ -#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) - -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) -/*! @} */ - -/*! @name INFO - USB Info */ -/*! @{ */ - -#define USB_INFO_FRAME_NR_MASK (0x7FFU) -#define USB_INFO_FRAME_NR_SHIFT (0U) -/*! FRAME_NR - Frame number - */ -#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) - -#define USB_INFO_ERR_CODE_MASK (0x7800U) -#define USB_INFO_ERR_CODE_SHIFT (11U) -/*! ERR_CODE - The error code which last occurred: - * 0b0000..No error - * 0b0001..PID encoding error - * 0b0010..PID unknown - * 0b0011..Packet unexpected - * 0b0100..Token CRC error - * 0b0101..Data CRC error - * 0b0110..Time out - * 0b0111..Babble - * 0b1000..Truncated EOP - * 0b1001..Sent/Received NAK - * 0b1010..Sent Stall - * 0b1011..Overrun - * 0b1100..Sent empty packet - * 0b1101..Bitstuff error - * 0b1110..Sync error - * 0b1111..Wrong data toggle - */ -#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) - -#define USB_INFO_MINREV_MASK (0xFF0000U) -#define USB_INFO_MINREV_SHIFT (16U) -/*! MINREV - Minor Revision. - */ -#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK) - -#define USB_INFO_MAJREV_MASK (0xFF000000U) -#define USB_INFO_MAJREV_SHIFT (24U) -/*! MAJREV - Major Revision. - */ -#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK) -/*! @} */ - -/*! @name EPLISTSTART - USB EP Command/Status List start address */ -/*! @{ */ - -#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) -#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) -/*! EP_LIST - Start address of the USB EP Command/Status List. - */ -#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) -/*! @} */ - -/*! @name DATABUFSTART - USB Data buffer start address */ -/*! @{ */ - -#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) -#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) -/*! DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located. - */ -#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) -/*! @} */ - -/*! @name LPM - USB Link Power Management */ -/*! @{ */ - -#define USB_LPM_HIRD_HW_MASK (0xFU) -#define USB_LPM_HIRD_HW_SHIFT (0U) -/*! HIRD_HW - Host Initiated Resume Duration - hardware - */ -#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) - -#define USB_LPM_HIRD_SW_MASK (0xF0U) -#define USB_LPM_HIRD_SW_SHIFT (4U) -/*! HIRD_SW - Host Initiated Resume Duration - software - */ -#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) - -#define USB_LPM_DATA_PENDING_MASK (0x100U) -#define USB_LPM_DATA_PENDING_SHIFT (8U) -/*! DATA_PENDING - Data pending - */ -#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) -/*! @} */ - -/*! @name EPSKIP - USB Endpoint skip */ -/*! @{ */ - -#define USB_EPSKIP_SKIP_MASK (0xFFFU) -#define USB_EPSKIP_SKIP_SHIFT (0U) -/*! SKIP - Endpoint skip - */ -#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) -/*! @} */ - -/*! @name EPINUSE - USB Endpoint Buffer in use */ -/*! @{ */ - -#define USB_EPINUSE_BUF_MASK (0xFFCU) -#define USB_EPINUSE_BUF_SHIFT (2U) -/*! BUF - Buffer in use - * 0b0000000000..Hardware is accessing buffer 0 - * 0b0000000001..Hardware is accessing buffer 1 - */ -#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) -/*! @} */ - -/*! @name EPBUFCFG - USB Endpoint Buffer Configuration */ -/*! @{ */ - -#define USB_EPBUFCFG_BUF_SB_MASK (0xFFCU) -#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) -/*! BUF_SB - Buffer usage - * 0b0000000000..Single-buffer - * 0b0000000001..Double-buffer - */ -#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) -/*! @} */ - -/*! @name INTSTAT - USB interrupt status */ -/*! @{ */ - -#define USB_INTSTAT_EP0OUT_MASK (0x1U) -#define USB_INTSTAT_EP0OUT_SHIFT (0U) -/*! EP0OUT - Control EP0 OUT direction - */ -#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) - -#define USB_INTSTAT_EP0IN_MASK (0x2U) -#define USB_INTSTAT_EP0IN_SHIFT (1U) -/*! EP0IN - Control EP0 IN direction - */ -#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) - -#define USB_INTSTAT_EP1OUT_MASK (0x4U) -#define USB_INTSTAT_EP1OUT_SHIFT (2U) -/*! EP1OUT - EP1 OUT direction - */ -#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) - -#define USB_INTSTAT_EP1IN_MASK (0x8U) -#define USB_INTSTAT_EP1IN_SHIFT (3U) -/*! EP1IN - EP1 IN direction - */ -#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) - -#define USB_INTSTAT_EP2OUT_MASK (0x10U) -#define USB_INTSTAT_EP2OUT_SHIFT (4U) -/*! EP2OUT - EP2 OUT direction - */ -#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) - -#define USB_INTSTAT_EP2IN_MASK (0x20U) -#define USB_INTSTAT_EP2IN_SHIFT (5U) -/*! EP2IN - EP2 IN direction - */ -#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) - -#define USB_INTSTAT_EP3OUT_MASK (0x40U) -#define USB_INTSTAT_EP3OUT_SHIFT (6U) -/*! EP3OUT - EP3 OUT direction - */ -#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) - -#define USB_INTSTAT_EP3IN_MASK (0x80U) -#define USB_INTSTAT_EP3IN_SHIFT (7U) -/*! EP3IN - EP3 IN direction - */ -#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) - -#define USB_INTSTAT_EP4OUT_MASK (0x100U) -#define USB_INTSTAT_EP4OUT_SHIFT (8U) -/*! EP4OUT - EP4 OUT direction - */ -#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) - -#define USB_INTSTAT_EP4IN_MASK (0x200U) -#define USB_INTSTAT_EP4IN_SHIFT (9U) -/*! EP4IN - EP4 IN direction - */ -#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) - -#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) -#define USB_INTSTAT_FRAME_INT_SHIFT (30U) -/*! FRAME_INT - Frame interrupt - */ -#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) - -#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) -#define USB_INTSTAT_DEV_INT_SHIFT (31U) -/*! DEV_INT - Device status interrupt - */ -#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) -/*! @} */ - -/*! @name INTEN - USB interrupt enable */ -/*! @{ */ - -#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) -#define USB_INTEN_EP_INT_EN_SHIFT (0U) -/*! EP_INT_EN - End point interrupt enable - */ -#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) - -#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) -#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) -/*! FRAME_INT_EN - Frame interrupt enable - */ -#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) - -#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) -#define USB_INTEN_DEV_INT_EN_SHIFT (31U) -/*! DEV_INT_EN - Device interrupt enable - */ -#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) -/*! @} */ - -/*! @name INTSETSTAT - USB set interrupt status */ -/*! @{ */ - -#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) -#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) -/*! EP_SET_INT - End point set interrupt - */ -#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) - -#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) -#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) -/*! FRAME_SET_INT - Frame set interrupt - */ -#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) - -#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) -#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) -/*! DEV_SET_INT - Device set interrupt - */ -#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) -/*! @} */ - -/*! @name EPTOGGLE - USB Endpoint toggle */ -/*! @{ */ - -#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) -#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) -/*! TOGGLE - Endpoint data toggle - */ -#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USB_Register_Masks */ - - -/* USB - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USB0 base address */ - #define USB0_BASE (0x50084000u) - /** Peripheral USB0 base address */ - #define USB0_BASE_NS (0x40084000u) - /** Peripheral USB0 base pointer */ - #define USB0 ((USB_Type *)USB0_BASE) - /** Peripheral USB0 base pointer */ - #define USB0_NS ((USB_Type *)USB0_BASE_NS) - /** Array initializer of USB peripheral base addresses */ - #define USB_BASE_ADDRS { USB0_BASE } - /** Array initializer of USB peripheral base pointers */ - #define USB_BASE_PTRS { USB0 } - /** Array initializer of USB peripheral base addresses */ - #define USB_BASE_ADDRS_NS { USB0_BASE_NS } - /** Array initializer of USB peripheral base pointers */ - #define USB_BASE_PTRS_NS { USB0_NS } -#else - /** Peripheral USB0 base address */ - #define USB0_BASE (0x40084000u) - /** Peripheral USB0 base pointer */ - #define USB0 ((USB_Type *)USB0_BASE) - /** Array initializer of USB peripheral base addresses */ - #define USB_BASE_ADDRS { USB0_BASE } - /** Array initializer of USB peripheral base pointers */ - #define USB_BASE_PTRS { USB0 } -#endif -/** Interrupt vectors for the USB peripheral type */ -#define USB_IRQS { USB0_IRQn } -#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBFSH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer - * @{ - */ - -/** USBFSH - Register Layout Typedef */ -typedef struct { - __I uint32_t HCREVISION; /**< Host controller revision, offset: 0x0 */ - __IO uint32_t HCCONTROL; /**< Host controller control, offset: 0x4 */ - __IO uint32_t HCCOMMANDSTATUS; /**< Host controller command status, offset: 0x8 */ - __IO uint32_t HCINTERRUPTSTATUS; /**< Host controller interrupt status, offset: 0xC */ - __IO uint32_t HCINTERRUPTENABLE; /**< Host Controller interrupt enable, offset: 0x10 */ - __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt., offset: 0x14 */ - __IO uint32_t HCHCCA; /**< Host controller communication area, offset: 0x18 */ - __I uint32_t HCPERIODCURRENTED; /**< Host controller period current endpoint descriptor, offset: 0x1C */ - __IO uint32_t HCCONTROLHEADED; /**< Host controller control head endpoint descriptor, offset: 0x20 */ - __IO uint32_t HCCONTROLCURRENTED; /**< Host controller control current endpoint descriptor, offset: 0x24 */ - __IO uint32_t HCBULKHEADED; /**< Host controller bulk head endpoint descriptor, offset: 0x28 */ - __IO uint32_t HCBULKCURRENTED; /**< Host controller bulk current endpoint descriptor, offset: 0x2C */ - __I uint32_t HCDONEHEAD; /**< Host controller done head, offset: 0x30 */ - __IO uint32_t HCFMINTERVAL; /**< Host controller frame interval, offset: 0x34 */ - __I uint32_t HCFMREMAINING; /**< Host controller frame remaining, offset: 0x38 */ - __I uint32_t HCFMNUMBER; /**< Host controller frame number, offset: 0x3C */ - __IO uint32_t HCPERIODICSTART; /**< Host controller periodic start, offset: 0x40 */ - __IO uint32_t HCLSTHRESHOLD; /**< Host controller low speed threshold, offset: 0x44 */ - __IO uint32_t HCRHDESCRIPTORA; /**< Host controller root hub descriptor A, offset: 0x48 */ - __IO uint32_t HCRHDESCRIPTORB; /**< Host controller root hub descriptor B, offset: 0x4C */ - __IO uint32_t HCRHSTATUS; /**< , offset: 0x50 */ - __IO uint32_t HCRHPORTSTATUS; /**< Host controller root hub port status, offset: 0x54 */ - uint8_t RESERVED_0[4]; - __IO uint32_t PORTMODE; /**< Port Mode, offset: 0x5C */ -} USBFSH_Type; - -/* ---------------------------------------------------------------------------- - -- USBFSH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBFSH_Register_Masks USBFSH Register Masks - * @{ - */ - -/*! @name HCREVISION - Host controller revision */ -/*! @{ */ - -#define USBFSH_HCREVISION_REV_MASK (0xFFU) -#define USBFSH_HCREVISION_REV_SHIFT (0U) -/*! REV - Revision - */ -#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK) -/*! @} */ - -/*! @name HCCONTROL - Host controller control */ -/*! @{ */ - -#define USBFSH_HCCONTROL_CBSR_MASK (0x3U) -#define USBFSH_HCCONTROL_CBSR_SHIFT (0U) -/*! CBSR - ControlBulkServiceRatio. - */ -#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK) - -#define USBFSH_HCCONTROL_PLE_MASK (0x4U) -#define USBFSH_HCCONTROL_PLE_SHIFT (2U) -/*! PLE - PeriodicListEnable. - */ -#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK) - -#define USBFSH_HCCONTROL_IE_MASK (0x8U) -#define USBFSH_HCCONTROL_IE_SHIFT (3U) -/*! IE - IsochronousEnable. - */ -#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK) - -#define USBFSH_HCCONTROL_CLE_MASK (0x10U) -#define USBFSH_HCCONTROL_CLE_SHIFT (4U) -/*! CLE - ControlListEnable. - */ -#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK) - -#define USBFSH_HCCONTROL_BLE_MASK (0x20U) -#define USBFSH_HCCONTROL_BLE_SHIFT (5U) -/*! BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. - */ -#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK) - -#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U) -#define USBFSH_HCCONTROL_HCFS_SHIFT (6U) -/*! HCFS - HostControllerFunctionalState - * 0b00..USBRESET - * 0b01..USBRESUME - * 0b10..USBOPERATIONAL - * 0b11..USBSUSPEND - */ -#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK) - -#define USBFSH_HCCONTROL_IR_MASK (0x100U) -#define USBFSH_HCCONTROL_IR_SHIFT (8U) -/*! IR - InterruptRouting - */ -#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK) - -#define USBFSH_HCCONTROL_RWC_MASK (0x200U) -#define USBFSH_HCCONTROL_RWC_SHIFT (9U) -/*! RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling. - */ -#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK) - -#define USBFSH_HCCONTROL_RWE_MASK (0x400U) -#define USBFSH_HCCONTROL_RWE_SHIFT (10U) -/*! RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature - * upon the detection of upstream resume signaling. - */ -#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK) -/*! @} */ - -/*! @name HCCOMMANDSTATUS - Host controller command status */ -/*! @{ */ - -#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U) -#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U) -/*! HCR - HostControllerReset - */ -#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK) - -#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U) -#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U) -/*! CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. - */ -#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK) - -#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U) -#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U) -/*! BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. - */ -#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK) - -#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U) -#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U) -/*! OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC. - */ -#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK) - -#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U) -#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U) -/*! SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error. - */ -#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK) -/*! @} */ - -/*! @name HCINTERRUPTSTATUS - Host controller interrupt status */ -/*! @{ */ - -#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U) -/*! SO - SchedulingOverrun - */ -#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U) -/*! WDH - WritebackDoneHead - */ -#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U) -/*! SF - StartofFrame - */ -#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U) -/*! RD - ResumeDetected - */ -#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U) -/*! UE - UnrecoverableError - */ -#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U) -/*! FNO - FrameNumberOverflow - */ -#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U) -/*! RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any - * of HcRhPortStatus[NumberofDownstreamPort] has changed. - */ -#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U) -#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U) -/*! OC - OwnershipChange - */ -#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK) -/*! @} */ - -/*! @name HCINTERRUPTENABLE - Host Controller interrupt enable */ -/*! @{ */ - -#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U) -/*! SO - Scheduling Overrun interrupt. - * 0b0..No effect - * 0b1..Enables interrupt - */ -#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK) - -#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U) -/*! WDH - HcDoneHead Writeback interrupt. - * 0b0..No effect - * 0b1..Enables interrupt - */ -#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK) - -#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U) -/*! SF - Start of Frame interrupt. - * 0b0..No effect - * 0b1..Enables interrupt - */ -#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK) - -#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U) -/*! RD - Resume Detect interrupt. - * 0b0..No effect - * 0b1..Enables interrupt - */ -#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK) - -#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U) -/*! UE - Unrecoverable Error interrupt. - * 0b0..No effect - * 0b1..Enables interrupt - */ -#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK) - -#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U) -/*! FNO - Frame Number Overflow interrupt. - * 0b0..No effect - * 0b1..Enables interrupt - */ -#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK) - -#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U) -/*! RHSC - Root Hub Status Change interrupt. - * 0b0..No effect - * 0b1..Enables interrupt - */ -#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK) - -#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U) -#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U) -/*! OC - Ownership Change interrupt. - * 0b0..No effect - * 0b1..Enables interrupt - */ -#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK) - -#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U) -#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U) -/*! MIE - Master Interrupt Enable. - */ -#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK) -/*! @} */ - -/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt. */ -/*! @{ */ - -#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U) -/*! SO - Scheduling Overrun interrupt. - * 0b0..No effect - * 0b1..Disables interrupt - */ -#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U) -/*! WDH - HcDoneHead Writeback interrupt. - * 0b0..No effect - * 0b1..Disables interrupt - */ -#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U) -/*! SF - Start of Frame interrupt. - * 0b0..No effect - * 0b1..Disables interrupt - */ -#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U) -/*! RD - Resume Detect interrupt. - * 0b0..No effect - * 0b1..Disables interrupt - */ -#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U) -/*! UE - Unrecoverable Error interrupt. - * 0b0..No effect - * 0b1..Disables interrupt - */ -#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U) -/*! FNO - Frame Number Overflow interrupt. - * 0b0..No effect - * 0b1..Disables interrupt - */ -#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U) -/*! RHSC - Root Hub Status Change interrupt. - * 0b0..No effect - * 0b1..Disables interrupt - */ -#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U) -#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U) -/*! OC - Ownership Change interrupt. - * 0b0..No effect - * 0b1..Disables interrupt - */ -#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U) -#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U) -/*! MIE - A 0 written to this field is ignored by HC. - * 0b0..No effect - * 0b1..Disables interrupt - */ -#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK) -/*! @} */ - -/*! @name HCHCCA - Host controller communication area */ -/*! @{ */ - -#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U) -#define USBFSH_HCHCCA_HCCA_SHIFT (8U) -/*! HCCA - Host Controller Communication Area - */ -#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK) -/*! @} */ - -/*! @name HCPERIODCURRENTED - Host controller period current endpoint descriptor */ -/*! @{ */ - -#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U) -/*! PCED - The content of this register is updated by HC after a periodic ED is processed. - */ -#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK) -/*! @} */ - -/*! @name HCCONTROLHEADED - Host controller control head endpoint descriptor */ -/*! @{ */ - -#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U) -#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U) -/*! CHED - HC traverses the Control list starting with the HcControlHeadED pointer. - */ -#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK) -/*! @} */ - -/*! @name HCCONTROLCURRENTED - Host controller control current endpoint descriptor */ -/*! @{ */ - -#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U) -/*! CCED - ControlCurrentED - */ -#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK) -/*! @} */ - -/*! @name HCBULKHEADED - Host controller bulk head endpoint descriptor */ -/*! @{ */ - -#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U) -#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U) -/*! BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer. - */ -#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK) -/*! @} */ - -/*! @name HCBULKCURRENTED - Host controller bulk current endpoint descriptor */ -/*! @{ */ - -#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U) -/*! BCED - BulkCurrentED - */ -#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK) -/*! @} */ - -/*! @name HCDONEHEAD - Host controller done head */ -/*! @{ */ - -#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U) -#define USBFSH_HCDONEHEAD_DH_SHIFT (4U) -/*! DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. - */ -#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK) -/*! @} */ - -/*! @name HCFMINTERVAL - Host controller frame interval */ -/*! @{ */ - -#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU) -#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U) -/*! FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times. - */ -#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK) - -#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U) -#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U) -/*! FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data - * Packet Counter at the beginning of each frame. - */ -#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK) - -#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U) -#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U) -/*! FIT - FrameIntervalToggle - */ -#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK) -/*! @} */ - -/*! @name HCFMREMAINING - Host controller frame remaining */ -/*! @{ */ - -#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU) -#define USBFSH_HCFMREMAINING_FR_SHIFT (0U) -/*! FR - FrameRemaining - */ -#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK) - -#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U) -#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U) -/*! FRT - FrameRemainingToggle - */ -#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK) -/*! @} */ - -/*! @name HCFMNUMBER - Host controller frame number */ -/*! @{ */ - -#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU) -#define USBFSH_HCFMNUMBER_FN_SHIFT (0U) -/*! FN - FrameNumber - */ -#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK) -/*! @} */ - -/*! @name HCPERIODICSTART - Host controller periodic start */ -/*! @{ */ - -#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU) -#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U) -/*! PS - PeriodicStart - */ -#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK) -/*! @} */ - -/*! @name HCLSTHRESHOLD - Host controller low speed threshold */ -/*! @{ */ - -#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU) -#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U) -/*! LST - LSThreshold - */ -#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK) -/*! @} */ - -/*! @name HCRHDESCRIPTORA - Host controller root hub descriptor A */ -/*! @{ */ - -#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU) -#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U) -/*! NDP - NumberDownstreamPorts - */ -#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK) - -#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U) -#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U) -/*! PSM - PowerSwitchingMode - * 0b0..All ports are powered at the same time - * 0b1..Each port is powered individually. - */ -#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK) - -#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U) -#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U) -/*! NPS - NoPowerSwitching - * 0b0..Ports are power switched - * 0b1..Ports are always powered on when the host controller is powered on - */ -#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK) - -#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U) -#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U) -/*! DT - DeviceType - */ -#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK) - -#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U) -#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U) -/*! OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported. - * 0b0..Over-current status is reported collectively for all downstream ports - * 0b1..Over-current status is reported on a per-port basis - */ -#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK) - -#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U) -#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U) -/*! NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported. - * 0b0..Over-current status is reported collectively for all downstream ports - * 0b1..No overcurrent protection supported - */ -#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK) - -#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U) -#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U) -/*! POTPGT - PowerOnToPowerGoodTime - */ -#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK) -/*! @} */ - -/*! @name HCRHDESCRIPTORB - Host controller root hub descriptor B */ -/*! @{ */ - -#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU) -#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U) -/*! DR - DeviceRemovable - */ -#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK) - -#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U) -#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U) -/*! PPCM - PortPowerControlMask - */ -#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK) -/*! @} */ - -/*! @name HCRHSTATUS - */ -/*! @{ */ - -#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U) -#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U) -/*! LPS - (read) LocalPowerStatus (write) ClearGlobalPower - */ -#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK) - -#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U) -#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U) -/*! OCI - OverCurrentIndicator - */ -#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK) - -#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U) -#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U) -/*! DRWE - (read) DeviceRemoteWakeupEnable (Write) SetRemoteWakeupEnable - * 0b0..ConnectStatusChange is not a remote wakeup event - * 0b1..ConnectStatusChange is a remote wakeup event - */ -#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK) - -#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U) -#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U) -/*! LPSC - (read) LocalPowerStatusChange(Write) SetGlobalPower . - */ -#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK) - -#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U) -#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U) -/*! OCIC - OverCurrentIndicatorChange - */ -#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK) - -#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U) -#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U) -/*! CRWE - (write) ClearRemoteWakeupEnable . - */ -#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK) -/*! @} */ - -/*! @name HCRHPORTSTATUS - Host controller root hub port status */ -/*! @{ */ - -#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U) -#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U) -/*! CCS - CurrentConnectStatus - * 0b0..Device is not connected - * 0b1..Device is connected - */ -#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK) - -#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U) -#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U) -/*! PES - (Read)PortEnableStatus - * 0b0..Port is disabled - * 0b1..Port is enabled - */ -#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK) - -#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U) -#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U) -/*! PSS - (Read) PortSuspendStatus - * 0b0..Port is not suspended - * 0b1..Port is suspended - */ -#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK) - -#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U) -#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U) -/*! POCI - (read) PortOverCurrentIndicator - * 0b0..Overcurrent condition is not detected - * 0b1..Overcurrent condition is detected - */ -#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK) - -#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U) -#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U) -/*! PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. - * 0b0..Port reset signal is not active - * 0b1..Port reset signal is active - */ -#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK) - -#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U) -#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U) -/*! PPS - (read) PortPowerStatus - * 0b0..Port power is off - * 0b1..Port power is on - */ -#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK) - -#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U) -#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U) -/*! LSDA - (read) LowSpeedDeviceAttached - * 0b0..Full speed device is attached - * 0b1..Low speed device is attached - */ -#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK) - -#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U) -#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U) -/*! CSC - ConnectStatusChange - * 0b0..CurrentConnectStatus has not changed - * 0b1..CurrentConnectStatus has changed - */ -#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK) - -#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U) -#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U) -/*! PESC - PortEnableStatusChange - * 0b0..PortEnableStatus has not changed - * 0b1..PortEnableStatus has changed - */ -#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK) - -#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U) -#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U) -/*! PSSC - PortSuspendStatusChange - * 0b0..Resume sequence is not complete - * 0b1..Resume sequence is complete - */ -#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK) - -#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U) -#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U) -/*! OCIC - PortOverCurrentIndicatorChange - * 0b0..PortOverCurrentIndicator has not changed - * 0b1..PortOverCurrentIndicator has changed - */ -#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK) - -#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U) -#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U) -/*! PRSC - PortResetStatusChange - * 0b0..Port reset is not complete - * 0b1..Port reset is complete - */ -#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK) -/*! @} */ - -/*! @name PORTMODE - Port Mode */ -/*! @{ */ - -#define USBFSH_PORTMODE_ID_MASK (0x1U) -#define USBFSH_PORTMODE_ID_SHIFT (0U) -/*! ID - Port ID pin value. - */ -#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK) - -#define USBFSH_PORTMODE_ID_EN_MASK (0x100U) -#define USBFSH_PORTMODE_ID_EN_SHIFT (8U) -/*! ID_EN - Port ID pin pull-up enable. - */ -#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK) - -#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) -#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U) -/*! DEV_ENABLE - Device Enable - * 0b0..Device - * 0b1..Host - */ -#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBFSH_Register_Masks */ - - -/* USBFSH - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USBFSH base address */ - #define USBFSH_BASE (0x500A2000u) - /** Peripheral USBFSH base address */ - #define USBFSH_BASE_NS (0x400A2000u) - /** Peripheral USBFSH base pointer */ - #define USBFSH ((USBFSH_Type *)USBFSH_BASE) - /** Peripheral USBFSH base pointer */ - #define USBFSH_NS ((USBFSH_Type *)USBFSH_BASE_NS) - /** Array initializer of USBFSH peripheral base addresses */ - #define USBFSH_BASE_ADDRS { USBFSH_BASE } - /** Array initializer of USBFSH peripheral base pointers */ - #define USBFSH_BASE_PTRS { USBFSH } - /** Array initializer of USBFSH peripheral base addresses */ - #define USBFSH_BASE_ADDRS_NS { USBFSH_BASE_NS } - /** Array initializer of USBFSH peripheral base pointers */ - #define USBFSH_BASE_PTRS_NS { USBFSH_NS } -#else - /** Peripheral USBFSH base address */ - #define USBFSH_BASE (0x400A2000u) - /** Peripheral USBFSH base pointer */ - #define USBFSH ((USBFSH_Type *)USBFSH_BASE) - /** Array initializer of USBFSH peripheral base addresses */ - #define USBFSH_BASE_ADDRS { USBFSH_BASE } - /** Array initializer of USBFSH peripheral base pointers */ - #define USBFSH_BASE_PTRS { USBFSH } -#endif -/** Interrupt vectors for the USBFSH peripheral type */ -#define USBFSH_IRQS { USB0_IRQn } -#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBFSH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- UTICK Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer - * @{ - */ - -/** UTICK - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control, offset: 0x0 */ - __IO uint32_t STAT; /**< Status, offset: 0x4 */ - __IO uint32_t CFG; /**< Capture Configuration, offset: 0x8 */ - __O uint32_t CAPCLR; /**< Capture Clear, offset: 0xC */ - __I uint32_t CAP[4]; /**< Capture, array offset: 0x10, array step: 0x4 */ -} UTICK_Type; - -/* ---------------------------------------------------------------------------- - -- UTICK Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Register_Masks UTICK Register Masks - * @{ - */ - -/*! @name CTRL - Control */ -/*! @{ */ - -#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) -#define UTICK_CTRL_DELAYVAL_SHIFT (0U) -/*! DELAYVAL - Tick interval - */ -#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) - -#define UTICK_CTRL_REPEAT_MASK (0x80000000U) -#define UTICK_CTRL_REPEAT_SHIFT (31U) -/*! REPEAT - Repeat delay - * 0b0..One-time delay - * 0b1..Delay repeats continuously - */ -#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) -/*! @} */ - -/*! @name STAT - Status */ -/*! @{ */ - -#define UTICK_STAT_INTR_MASK (0x1U) -#define UTICK_STAT_INTR_SHIFT (0U) -/*! INTR - Interrupt flag - * 0b0..No interrupt is pending - * 0b1..An interrupt is pending - */ -#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) - -#define UTICK_STAT_ACTIVE_MASK (0x2U) -#define UTICK_STAT_ACTIVE_SHIFT (1U) -/*! ACTIVE - Timer active flag - * 0b0..The Micro-Tick Timer is not active (stopped) - * 0b1..The Micro-Tick Timer is currently active - */ -#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) -/*! @} */ - -/*! @name CFG - Capture Configuration */ -/*! @{ */ - -#define UTICK_CFG_CAPEN0_MASK (0x1U) -#define UTICK_CFG_CAPEN0_SHIFT (0U) -/*! CAPEN0 - Enable Capture 0 - * 0b0..Disabled - * 0b1..Enabled - */ -#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) - -#define UTICK_CFG_CAPEN1_MASK (0x2U) -#define UTICK_CFG_CAPEN1_SHIFT (1U) -/*! CAPEN1 - Enable Capture 1 - * 0b0..Disabled - * 0b1..Enabled - */ -#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) - -#define UTICK_CFG_CAPEN2_MASK (0x4U) -#define UTICK_CFG_CAPEN2_SHIFT (2U) -/*! CAPEN2 - Enable Capture 2 - * 0b0..Disabled - * 0b1..Enabled - */ -#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) - -#define UTICK_CFG_CAPEN3_MASK (0x8U) -#define UTICK_CFG_CAPEN3_SHIFT (3U) -/*! CAPEN3 - Enable Capture 3 - * 0b0..Disabled - * 0b1..Enabled - */ -#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) - -#define UTICK_CFG_CAPPOL0_MASK (0x100U) -#define UTICK_CFG_CAPPOL0_SHIFT (8U) -/*! CAPPOL0 - Capture Polarity 0 - * 0b0..Positive edge capture - * 0b1..Negative edge capture - */ -#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) - -#define UTICK_CFG_CAPPOL1_MASK (0x200U) -#define UTICK_CFG_CAPPOL1_SHIFT (9U) -/*! CAPPOL1 - Capture Polarity 1 - * 0b0..Positive edge capture - * 0b1..Negative edge capture - */ -#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) - -#define UTICK_CFG_CAPPOL2_MASK (0x400U) -#define UTICK_CFG_CAPPOL2_SHIFT (10U) -/*! CAPPOL2 - Capture Polarity 2 - * 0b0..Positive edge capture - * 0b1..Negative edge capture - */ -#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) - -#define UTICK_CFG_CAPPOL3_MASK (0x800U) -#define UTICK_CFG_CAPPOL3_SHIFT (11U) -/*! CAPPOL3 - Capture Polarity 3 - * 0b0..Positive edge capture - * 0b1..Negative edge capture - */ -#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) -/*! @} */ - -/*! @name CAPCLR - Capture Clear */ -/*! @{ */ - -#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) -#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) -/*! CAPCLR0 - Clear capture 0 - * 0b0..Does nothing - * 0b1..Write 1 to clear the CAP0 register value - */ -#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) - -#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) -#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) -/*! CAPCLR1 - Clear capture 1 - * 0b0..Does nothing - * 0b1..Write 1 to clear the CAP1 register value - */ -#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) - -#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) -#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) -/*! CAPCLR2 - Clear capture 2 - * 0b0..Does nothing - * 0b1..Write 1 to clear the CAP2 register value - */ -#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) - -#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) -#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) -/*! CAPCLR3 - Clear capture 3 - * 0b0..Does nothing - * 0b1..Write 1 to clear the CAP3 register value - */ -#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) -/*! @} */ - -/*! @name CAP - Capture */ -/*! @{ */ - -#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) -#define UTICK_CAP_CAP_VALUE_SHIFT (0U) -/*! CAP_VALUE - Captured value for the related capture event - */ -#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) - -#define UTICK_CAP_VALID_MASK (0x80000000U) -#define UTICK_CAP_VALID_SHIFT (31U) -/*! VALID - Captured value is valid - * 0b0..A valid value has been not been captured - * 0b1..A valid value has been captured, based on a transition of the related UTICK_CAPn pin - */ -#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) -/*! @} */ - -/* The count of UTICK_CAP */ -#define UTICK_CAP_COUNT (4U) - - -/*! - * @} - */ /* end of group UTICK_Register_Masks */ - - -/* UTICK - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE (0x5000E000u) - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE_NS (0x4000E000u) - /** Peripheral UTICK0 base pointer */ - #define UTICK0 ((UTICK_Type *)UTICK0_BASE) - /** Peripheral UTICK0 base pointer */ - #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS { UTICK0_BASE } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS { UTICK0 } - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS_NS { UTICK0_NS } -#else - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE (0x4000E000u) - /** Peripheral UTICK0 base pointer */ - #define UTICK0 ((UTICK_Type *)UTICK0_BASE) - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS { UTICK0_BASE } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS { UTICK0 } -#endif -/** Interrupt vectors for the UTICK peripheral type */ -#define UTICK_IRQS { UTICK0_IRQn } - -/*! - * @} - */ /* end of group UTICK_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- VREF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer - * @{ - */ - -/** VREF - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< VREF Version ID, offset: 0x0 */ - uint32_t PARAM; /**< VREF Parameter, offset: 0x4 */ - __IO uint32_t CSR; /**< VREF Control and Status Register, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t UTRIM; /**< VREF User Trim, offset: 0x10 */ - uint8_t RESERVED_1[8]; - __IO uint32_t TEST_UNLOCK; /**< Unlock test registers, offset: 0x1C */ - uint8_t RESERVED_2[4]; - __IO uint32_t TRIM0; /**< VREF Test Trim 0, offset: 0x24 */ - __IO uint32_t TRIM1; /**< VREF Test Trim 1, offset: 0x28 */ -} VREF_Type; - -/* ---------------------------------------------------------------------------- - -- VREF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup VREF_Register_Masks VREF Register Masks - * @{ - */ - -/*! @name VERID - VREF Version ID */ -/*! @{ */ - -#define VREF_VERID_FEATURE_MASK (0xFFFFU) -#define VREF_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - FEATURE - */ -#define VREF_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << VREF_VERID_FEATURE_SHIFT)) & VREF_VERID_FEATURE_MASK) - -#define VREF_VERID_MINOR_MASK (0xFF0000U) -#define VREF_VERID_MINOR_SHIFT (16U) -/*! MINOR - MINOR - */ -#define VREF_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << VREF_VERID_MINOR_SHIFT)) & VREF_VERID_MINOR_MASK) - -#define VREF_VERID_MAJOR_MASK (0xFF000000U) -#define VREF_VERID_MAJOR_SHIFT (24U) -/*! MAJOR - MAJOR - */ -#define VREF_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << VREF_VERID_MAJOR_SHIFT)) & VREF_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name CSR - VREF Control and Status Register */ -/*! @{ */ - -#define VREF_CSR_HCBGEN_MASK (0x1U) -#define VREF_CSR_HCBGEN_SHIFT (0U) -/*! HCBGEN - HC Bandgap enabled - * 0b0..HC Bandgap is disabled - * 0b1..HC Bandgap is enabled - */ -#define VREF_CSR_HCBGEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_HCBGEN_SHIFT)) & VREF_CSR_HCBGEN_MASK) - -#define VREF_CSR_LPBGEN_MASK (0x2U) -#define VREF_CSR_LPBGEN_SHIFT (1U) -/*! LPBGEN - Low Power Bandgap enable - * 0b0..LP Bandgap is disabled - * 0b1..LP Bandgap is enabled - */ -#define VREF_CSR_LPBGEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_LPBGEN_SHIFT)) & VREF_CSR_LPBGEN_MASK) - -#define VREF_CSR_LPBG_BUF_EN_MASK (0x4U) -#define VREF_CSR_LPBG_BUF_EN_SHIFT (2U) -/*! LPBG_BUF_EN - * 0b0..disable - * 0b1..enable - */ -#define VREF_CSR_LPBG_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_LPBG_BUF_EN_SHIFT)) & VREF_CSR_LPBG_BUF_EN_MASK) - -#define VREF_CSR_CHOPEN_MASK (0x8U) -#define VREF_CSR_CHOPEN_SHIFT (3U) -/*! CHOPEN - Chop oscillator enable. When set, the internal chopping operation is enabled and the - * internal analog offset will be minimized. - * 0b0..Chop oscillator is disabled. - * 0b1..Chop oscillator is enabled. - */ -#define VREF_CSR_CHOPEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_CHOPEN_SHIFT)) & VREF_CSR_CHOPEN_MASK) - -#define VREF_CSR_ICOMPEN_MASK (0x10U) -#define VREF_CSR_ICOMPEN_SHIFT (4U) -/*! ICOMPEN - Second order curvature compensation enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define VREF_CSR_ICOMPEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_ICOMPEN_SHIFT)) & VREF_CSR_ICOMPEN_MASK) - -#define VREF_CSR_REGEN_MASK (0x20U) -#define VREF_CSR_REGEN_SHIFT (5U) -/*! REGEN - Regulator enable - * 0b0..Internal 1.75 V regulator is disabled. - * 0b1..Internal 1.75 V regulator is enabled. - */ -#define VREF_CSR_REGEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REGEN_SHIFT)) & VREF_CSR_REGEN_MASK) - -#define VREF_CSR_REFCHSELN_EN_MASK (0x40U) -#define VREF_CSR_REFCHSELN_EN_SHIFT (6U) -/*! REFCHSELN_EN - * 0b0..disable - * 0b1..enable - */ -#define VREF_CSR_REFCHSELN_EN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REFCHSELN_EN_SHIFT)) & VREF_CSR_REFCHSELN_EN_MASK) - -#define VREF_CSR_REFCHSELP_EN_MASK (0x80U) -#define VREF_CSR_REFCHSELP_EN_SHIFT (7U) -/*! REFCHSELP_EN - * 0b0..disable - * 0b1..enable - */ -#define VREF_CSR_REFCHSELP_EN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REFCHSELP_EN_SHIFT)) & VREF_CSR_REFCHSELP_EN_MASK) - -#define VREF_CSR_VRSEL_MASK (0x300U) -#define VREF_CSR_VRSEL_SHIFT (8U) -/*! VRSEL - * 0b00..Internal bandgap - * 0b01..Low power buffered 1v - * 0b10..Buffer 2.1v output - */ -#define VREF_CSR_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_VRSEL_SHIFT)) & VREF_CSR_VRSEL_MASK) - -#define VREF_CSR_REFL_GRD_SEL_MASK (0x400U) -#define VREF_CSR_REFL_GRD_SEL_SHIFT (10U) -/*! REFL_GRD_SEL - * 0b0..vrefl_3v - * 0b1..vssa - */ -#define VREF_CSR_REFL_GRD_SEL(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REFL_GRD_SEL_SHIFT)) & VREF_CSR_REFL_GRD_SEL_MASK) - -#define VREF_CSR_HI_PWR_LV_MASK (0x800U) -#define VREF_CSR_HI_PWR_LV_SHIFT (11U) -#define VREF_CSR_HI_PWR_LV(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_HI_PWR_LV_SHIFT)) & VREF_CSR_HI_PWR_LV_MASK) - -#define VREF_CSR_BUF21EN_MASK (0x10000U) -#define VREF_CSR_BUF21EN_SHIFT (16U) -/*! Buf21EN - Internal buf21 Enable - * 0b0..buf21 is disabled - * 0b1..buf21 is enabled - */ -#define VREF_CSR_BUF21EN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_BUF21EN_SHIFT)) & VREF_CSR_BUF21EN_MASK) - -#define VREF_CSR_VREFST_MASK (0x80000000U) -#define VREF_CSR_VREFST_SHIFT (31U) -/*! VREFST - Internal HC Voltage Reference stable - * 0b0..The module is disabled or not stable. - * 0b1..The module is stable. - */ -#define VREF_CSR_VREFST(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_VREFST_SHIFT)) & VREF_CSR_VREFST_MASK) -/*! @} */ - -/*! @name UTRIM - VREF User Trim */ -/*! @{ */ - -#define VREF_UTRIM_TRIM2V1_MASK (0xFU) -#define VREF_UTRIM_TRIM2V1_SHIFT (0U) -/*! TRIM2V1 - VREF 2.1V Trim Bits - */ -#define VREF_UTRIM_TRIM2V1(x) (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_TRIM2V1_SHIFT)) & VREF_UTRIM_TRIM2V1_MASK) - -#define VREF_UTRIM_VREFTRIM_MASK (0x3F00U) -#define VREF_UTRIM_VREFTRIM_SHIFT (8U) -/*! VREFTRIM - VREF Trim bits - */ -#define VREF_UTRIM_VREFTRIM(x) (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_VREFTRIM_SHIFT)) & VREF_UTRIM_VREFTRIM_MASK) -/*! @} */ - -/*! @name TEST_UNLOCK - Unlock test registers */ -/*! @{ */ - -#define VREF_TEST_UNLOCK_TEST_UNLOCK_MASK (0x1U) -#define VREF_TEST_UNLOCK_TEST_UNLOCK_SHIFT (0U) -/*! test_unlock - Test_unlock status bit - * 0b0..Lock read/write into test register - * 0b1..Unlock read/write into test register - */ -#define VREF_TEST_UNLOCK_TEST_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << VREF_TEST_UNLOCK_TEST_UNLOCK_SHIFT)) & VREF_TEST_UNLOCK_TEST_UNLOCK_MASK) - -#define VREF_TEST_UNLOCK_TEST_UNLOCK_VALUE_MASK (0xFFFEU) -#define VREF_TEST_UNLOCK_TEST_UNLOCK_VALUE_SHIFT (1U) -/*! test_unlock_value - Test unlock value - */ -#define VREF_TEST_UNLOCK_TEST_UNLOCK_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VREF_TEST_UNLOCK_TEST_UNLOCK_VALUE_SHIFT)) & VREF_TEST_UNLOCK_TEST_UNLOCK_VALUE_MASK) -/*! @} */ - -/*! @name TRIM0 - VREF Test Trim 0 */ -/*! @{ */ - -#define VREF_TRIM0_COMPLSB_MASK (0x7U) -#define VREF_TRIM0_COMPLSB_SHIFT (0U) -/*! COMPLSB - COMPLSB - */ -#define VREF_TRIM0_COMPLSB(x) (((uint32_t)(((uint32_t)(x)) << VREF_TRIM0_COMPLSB_SHIFT)) & VREF_TRIM0_COMPLSB_MASK) - -#define VREF_TRIM0_COMPMSB_MASK (0xE0U) -#define VREF_TRIM0_COMPMSB_SHIFT (5U) -/*! COMPMSB - COMPMSB - */ -#define VREF_TRIM0_COMPMSB(x) (((uint32_t)(((uint32_t)(x)) << VREF_TRIM0_COMPMSB_SHIFT)) & VREF_TRIM0_COMPMSB_MASK) - -#define VREF_TRIM0_BPLSB_MASK (0xF00U) -#define VREF_TRIM0_BPLSB_SHIFT (8U) -/*! BPLSB - BPLSB - */ -#define VREF_TRIM0_BPLSB(x) (((uint32_t)(((uint32_t)(x)) << VREF_TRIM0_BPLSB_SHIFT)) & VREF_TRIM0_BPLSB_MASK) - -#define VREF_TRIM0_BPMSB_MASK (0xE000U) -#define VREF_TRIM0_BPMSB_SHIFT (13U) -/*! BPMSB - BPMSB - */ -#define VREF_TRIM0_BPMSB(x) (((uint32_t)(((uint32_t)(x)) << VREF_TRIM0_BPMSB_SHIFT)) & VREF_TRIM0_BPMSB_MASK) - -#define VREF_TRIM0_CHOPOSCTRIM_MASK (0xF0000U) -#define VREF_TRIM0_CHOPOSCTRIM_SHIFT (16U) -/*! CHOPOSCTRIM - CHOPOSCTRIM - */ -#define VREF_TRIM0_CHOPOSCTRIM(x) (((uint32_t)(((uint32_t)(x)) << VREF_TRIM0_CHOPOSCTRIM_SHIFT)) & VREF_TRIM0_CHOPOSCTRIM_MASK) - -#define VREF_TRIM0_P7_TRIM_MASK (0xF000000U) -#define VREF_TRIM0_P7_TRIM_SHIFT (24U) -/*! P7_TRIM - P7_TRIM - * 0b0000..VREF 2.1V is enabled - * 0b0001..VREF 2.1V is disabled - */ -#define VREF_TRIM0_P7_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VREF_TRIM0_P7_TRIM_SHIFT)) & VREF_TRIM0_P7_TRIM_MASK) - -#define VREF_TRIM0_FLIP_MASK (0x80000000U) -#define VREF_TRIM0_FLIP_SHIFT (31U) -/*! FLIP - Amplifier Polarity - */ -#define VREF_TRIM0_FLIP(x) (((uint32_t)(((uint32_t)(x)) << VREF_TRIM0_FLIP_SHIFT)) & VREF_TRIM0_FLIP_MASK) -/*! @} */ - -/*! @name TRIM1 - VREF Test Trim 1 */ -/*! @{ */ - -#define VREF_TRIM1_LP_VTRIM_MASK (0x1FU) -#define VREF_TRIM1_LP_VTRIM_SHIFT (0U) -/*! LP_VTRIM - LP Bandgap Voltage Trim - */ -#define VREF_TRIM1_LP_VTRIM(x) (((uint32_t)(((uint32_t)(x)) << VREF_TRIM1_LP_VTRIM_SHIFT)) & VREF_TRIM1_LP_VTRIM_MASK) - -#define VREF_TRIM1_LP_TCTRIM_MASK (0x700U) -#define VREF_TRIM1_LP_TCTRIM_SHIFT (8U) -/*! LP_TCTRIM - LP_TCTRIM - */ -#define VREF_TRIM1_LP_TCTRIM(x) (((uint32_t)(((uint32_t)(x)) << VREF_TRIM1_LP_TCTRIM_SHIFT)) & VREF_TRIM1_LP_TCTRIM_MASK) - -#define VREF_TRIM1_IREF_TRIM_MASK (0x70000U) -#define VREF_TRIM1_IREF_TRIM_SHIFT (16U) -/*! IREF_TRIM - IREF_TRIM - */ -#define VREF_TRIM1_IREF_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VREF_TRIM1_IREF_TRIM_SHIFT)) & VREF_TRIM1_IREF_TRIM_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group VREF_Register_Masks */ - - -/* VREF - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral VREF base address */ - #define VREF_BASE (0x500B5000u) - /** Peripheral VREF base address */ - #define VREF_BASE_NS (0x400B5000u) - /** Peripheral VREF base pointer */ - #define VREF ((VREF_Type *)VREF_BASE) - /** Peripheral VREF base pointer */ - #define VREF_NS ((VREF_Type *)VREF_BASE_NS) - /** Array initializer of VREF peripheral base addresses */ - #define VREF_BASE_ADDRS { VREF_BASE } - /** Array initializer of VREF peripheral base pointers */ - #define VREF_BASE_PTRS { VREF } - /** Array initializer of VREF peripheral base addresses */ - #define VREF_BASE_ADDRS_NS { VREF_BASE_NS } - /** Array initializer of VREF peripheral base pointers */ - #define VREF_BASE_PTRS_NS { VREF_NS } -#else - /** Peripheral VREF base address */ - #define VREF_BASE (0x400B5000u) - /** Peripheral VREF base pointer */ - #define VREF ((VREF_Type *)VREF_BASE) - /** Array initializer of VREF peripheral base addresses */ - #define VREF_BASE_ADDRS { VREF_BASE } - /** Array initializer of VREF peripheral base pointers */ - #define VREF_BASE_PTRS { VREF } -#endif - -/*! - * @} - */ /* end of group VREF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- WWDT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer - * @{ - */ - -/** WWDT - Register Layout Typedef */ -typedef struct { - __IO uint32_t MOD; /**< Mode, offset: 0x0 */ - __IO uint32_t TC; /**< Timer Constant, offset: 0x4 */ - __O uint32_t FEED; /**< Feed Sequence, offset: 0x8 */ - __I uint32_t TV; /**< Timer Value, offset: 0xC */ - uint8_t RESERVED_0[4]; - __IO uint32_t WARNINT; /**< Warning Interrupt Compare Value, offset: 0x14 */ - __IO uint32_t WINDOW; /**< Window Compare Value, offset: 0x18 */ -} WWDT_Type; - -/* ---------------------------------------------------------------------------- - -- WWDT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Register_Masks WWDT Register Masks - * @{ - */ - -/*! @name MOD - Mode */ -/*! @{ */ - -#define WWDT_MOD_WDEN_MASK (0x1U) -#define WWDT_MOD_WDEN_SHIFT (0U) -/*! WDEN - Watchdog Enable - * 0b0..Stop. The Watchdog timer is stopped. - * 0b1..Run. The Watchdog timer is running. - */ -#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) - -#define WWDT_MOD_WDRESET_MASK (0x2U) -#define WWDT_MOD_WDRESET_SHIFT (1U) -/*! WDRESET - Watchdog Reset Enable - * 0b0..Interrupt. A Watchdog timeout will not cause a chip reset. - * 0b1..Reset. A Watchdog timeout will cause a chip reset. - */ -#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) - -#define WWDT_MOD_WDTOF_MASK (0x4U) -#define WWDT_MOD_WDTOF_SHIFT (2U) -/*! WDTOF - Watchdog Timeout Flag - * 0b0..Clear. - * 0b1..Reset. Causes a chip reset if WDRESET = 1. - */ -#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) - -#define WWDT_MOD_WDINT_MASK (0x8U) -#define WWDT_MOD_WDINT_SHIFT (3U) -/*! WDINT - Warning Interrupt Flag - * 0b0..No flag. - * 0b1..Flag. The Watchdog interrupt flag is set when the Watchdog counter is no longer greater than the value specified by WARNINT. - */ -#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) - -#define WWDT_MOD_WDPROTECT_MASK (0x10U) -#define WWDT_MOD_WDPROTECT_SHIFT (4U) -/*! WDPROTECT - Watchdog Update Mode - * 0b0..Flexible - * 0b1..Threshold - */ -#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) - -#define WWDT_MOD_LOCK_MASK (0x20U) -#define WWDT_MOD_LOCK_SHIFT (5U) -/*! LOCK - Lock - * 0b0..No Lock - * 0b1..Lock - */ -#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) -/*! @} */ - -/*! @name TC - Timer Constant */ -/*! @{ */ - -#define WWDT_TC_COUNT_MASK (0xFFFFFFU) -#define WWDT_TC_COUNT_SHIFT (0U) -/*! COUNT - Watchdog Timeout Value - */ -#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) -/*! @} */ - -/*! @name FEED - Feed Sequence */ -/*! @{ */ - -#define WWDT_FEED_FEED_MASK (0xFFU) -#define WWDT_FEED_FEED_SHIFT (0U) -/*! FEED - Feed Value - */ -#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) -/*! @} */ - -/*! @name TV - Timer Value */ -/*! @{ */ - -#define WWDT_TV_COUNT_MASK (0xFFFFFFU) -#define WWDT_TV_COUNT_SHIFT (0U) -/*! COUNT - Counter Timer Value - */ -#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) -/*! @} */ - -/*! @name WARNINT - Warning Interrupt Compare Value */ -/*! @{ */ - -#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) -#define WWDT_WARNINT_WARNINT_SHIFT (0U) -/*! WARNINT - Watchdog Warning Interrupt Compare Value - */ -#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) -/*! @} */ - -/*! @name WINDOW - Window Compare Value */ -/*! @{ */ - -#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) -#define WWDT_WINDOW_WINDOW_SHIFT (0U) -/*! WINDOW - Watchdog Window Value. - */ -#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group WWDT_Register_Masks */ - - -/* WWDT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral WWDT base address */ - #define WWDT_BASE (0x5000C000u) - /** Peripheral WWDT base address */ - #define WWDT_BASE_NS (0x4000C000u) - /** Peripheral WWDT base pointer */ - #define WWDT ((WWDT_Type *)WWDT_BASE) - /** Peripheral WWDT base pointer */ - #define WWDT_NS ((WWDT_Type *)WWDT_BASE_NS) - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS { WWDT_BASE } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS { WWDT } - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS_NS { WWDT_BASE_NS } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS_NS { WWDT_NS } -#else - /** Peripheral WWDT base address */ - #define WWDT_BASE (0x4000C000u) - /** Peripheral WWDT base pointer */ - #define WWDT ((WWDT_Type *)WWDT_BASE) - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS { WWDT_BASE } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS { WWDT } -#endif -/** Interrupt vectors for the WWDT peripheral type */ -#define WWDT_IRQS { WDT_BOD_IRQn } - -/*! - * @} - */ /* end of group WWDT_Peripheral_Access_Layer */ - - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop - #else - #pragma pop - #endif -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -/*! - * @} - */ /* end of group Peripheral_access_layer */ - - -/* ---------------------------------------------------------------------------- - -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - * @{ - */ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang system_header - #endif -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma system_include -#endif - -/** - * @brief Mask and left-shift a bit field value for use in a register bit range. - * @param field Name of the register bit field. - * @param value Value of the bit field. - * @return Masked and shifted value. - */ -#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) -/** - * @brief Mask and right-shift a register value to extract a bit field value. - * @param field Name of the register bit field. - * @param value Value of the register. - * @return Masked and shifted bit field value. - */ -#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) - -/*! - * @} - */ /* end of group Bit_Field_Generic_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SDK Compatibility - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDK_Compatibility_Symbols SDK Compatibility - * @{ - */ - -/** AHB Secure Control */ -#if defined(SECTRL0) - #define AHB_SECURE_CTRL SECTRL0 -#endif - - -/*! - * @} - */ /* end of group SDK_Compatibility_Symbols */ - - -#endif /* _LPC55S36_H_ */ - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/LPC55S36_features.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/LPC55S36_features.h deleted file mode 100644 index 3107d843947..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/LPC55S36_features.h +++ /dev/null @@ -1,624 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.1, 2021-08-04 -** Build: b220118 -** -** Abstract: -** Chip specific module features. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2021-04-12) -** Initial version based on RM DraftF -** - rev. 1.1 (2021-08-04) -** Initial version based on RM DraftG -** -** ################################################################### -*/ - -#ifndef _LPC55S36_FEATURES_H_ -#define _LPC55S36_FEATURES_H_ - -/* SOC module features */ - -#if defined(CPU_LPC55S36JBD100) - /* @brief AOI availability on the SoC. */ - #define FSL_FEATURE_SOC_AOI_COUNT (2) - /* @brief CACHE64_CTRL availability on the SoC. */ - #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) - /* @brief CACHE64_POLSEL availability on the SoC. */ - #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) - /* @brief LPC_CAN availability on the SoC. */ - #define FSL_FEATURE_SOC_LPC_CAN_COUNT (1) - /* @brief CRC availability on the SoC. */ - #define FSL_FEATURE_SOC_CRC_COUNT (1) - /* @brief CTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_CTIMER_COUNT (5) - /* @brief CDOG availability on the SoC. */ - #define FSL_FEATURE_SOC_CDOG_COUNT (1) - /* @brief DMA availability on the SoC. */ - #define FSL_FEATURE_SOC_DMA_COUNT (2) - /* @brief DMIC availability on the SoC. */ - #define FSL_FEATURE_SOC_DMIC_COUNT (1) - /* @brief ENC availability on the SoC. */ - #define FSL_FEATURE_SOC_ENC_COUNT (2) - /* @brief FLASH availability on the SoC. */ - #define FSL_FEATURE_SOC_FLASH_COUNT (1) - /* @brief FLEXCOMM availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) - /* @brief FLEXSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) - /* @brief FREQME availability on the SoC. */ - #define FSL_FEATURE_SOC_FREQME_COUNT (1) - /* @brief GINT availability on the SoC. */ - #define FSL_FEATURE_SOC_GINT_COUNT (2) - /* @brief GPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_GPIO_COUNT (1) - /* @brief SECGPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_SECGPIO_COUNT (1) - /* @brief I2C availability on the SoC. */ - #define FSL_FEATURE_SOC_I2C_COUNT (8) - /* @brief I3C availability on the SoC. */ - #define FSL_FEATURE_SOC_I3C_COUNT (1) - /* @brief I2S availability on the SoC. */ - #define FSL_FEATURE_SOC_I2S_COUNT (8) - /* @brief INPUTMUX availability on the SoC. */ - #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) - /* @brief IOCON availability on the SoC. */ - #define FSL_FEATURE_SOC_IOCON_COUNT (1) - /* @brief LPADC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPADC_COUNT (2) - /* @brief LPCMP availability on the SoC. */ - #define FSL_FEATURE_SOC_LPCMP_COUNT (3) - /* @brief LPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPDAC_COUNT (3) - /* @brief MAILBOX availability on the SoC. */ - #define FSL_FEATURE_SOC_MAILBOX_COUNT (1) - /* @brief MRT availability on the SoC. */ - #define FSL_FEATURE_SOC_MRT_COUNT (1) - /* @brief OPAMP availability on the SoC. */ - #define FSL_FEATURE_SOC_OPAMP_COUNT (3) - /* @brief OSTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) - /* @brief PINT availability on the SoC. */ - #define FSL_FEATURE_SOC_PINT_COUNT (1) - /* @brief SECPINT availability on the SoC. */ - #define FSL_FEATURE_SOC_SECPINT_COUNT (1) - /* @brief PMC availability on the SoC. */ - #define FSL_FEATURE_SOC_PMC_COUNT (1) - /* @brief POWERQUAD availability on the SoC. */ - #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) - /* @brief PWM availability on the SoC. */ - #define FSL_FEATURE_SOC_PWM_COUNT (2) - /* @brief PUF availability on the SoC. */ - #define FSL_FEATURE_SOC_PUF_COUNT (1) - /* @brief RTC availability on the SoC. */ - #define FSL_FEATURE_SOC_RTC_COUNT (2) - /* @brief SCT availability on the SoC. */ - #define FSL_FEATURE_SOC_SCT_COUNT (1) - /* @brief SPI availability on the SoC. */ - #define FSL_FEATURE_SOC_SPI_COUNT (9) - /* @brief SYSCON availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSCON_COUNT (1) - /* @brief USART availability on the SoC. */ - #define FSL_FEATURE_SOC_USART_COUNT (8) - /* @brief USB availability on the SoC. */ - #define FSL_FEATURE_SOC_USB_COUNT (1) - /* @brief USBFSH availability on the SoC. */ - #define FSL_FEATURE_SOC_USBFSH_COUNT (1) - /* @brief UTICK availability on the SoC. */ - #define FSL_FEATURE_SOC_UTICK_COUNT (1) - /* @brief VREF availability on the SoC. */ - #define FSL_FEATURE_SOC_VREF_COUNT (1) - /* @brief WWDT availability on the SoC. */ - #define FSL_FEATURE_SOC_WWDT_COUNT (1) -#elif defined(CPU_LPC55S36JHI48) - /* @brief AOI availability on the SoC. */ - #define FSL_FEATURE_SOC_AOI_COUNT (2) - /* @brief CACHE64_CTRL availability on the SoC. */ - #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) - /* @brief CACHE64_POLSEL availability on the SoC. */ - #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) - /* @brief LPC_CAN availability on the SoC. */ - #define FSL_FEATURE_SOC_LPC_CAN_COUNT (1) - /* @brief CRC availability on the SoC. */ - #define FSL_FEATURE_SOC_CRC_COUNT (1) - /* @brief CTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_CTIMER_COUNT (5) - /* @brief CDOG availability on the SoC. */ - #define FSL_FEATURE_SOC_CDOG_COUNT (1) - /* @brief DMA availability on the SoC. */ - #define FSL_FEATURE_SOC_DMA_COUNT (2) - /* @brief DMIC availability on the SoC. */ - #define FSL_FEATURE_SOC_DMIC_COUNT (1) - /* @brief ENC availability on the SoC. */ - #define FSL_FEATURE_SOC_ENC_COUNT (2) - /* @brief FLASH availability on the SoC. */ - #define FSL_FEATURE_SOC_FLASH_COUNT (1) - /* @brief FLEXCOMM availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) - /* @brief FLEXSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) - /* @brief FREQME availability on the SoC. */ - #define FSL_FEATURE_SOC_FREQME_COUNT (1) - /* @brief GINT availability on the SoC. */ - #define FSL_FEATURE_SOC_GINT_COUNT (2) - /* @brief GPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_GPIO_COUNT (1) - /* @brief SECGPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_SECGPIO_COUNT (1) - /* @brief I2C availability on the SoC. */ - #define FSL_FEATURE_SOC_I2C_COUNT (8) - /* @brief I3C availability on the SoC. */ - #define FSL_FEATURE_SOC_I3C_COUNT (1) - /* @brief I2S availability on the SoC. */ - #define FSL_FEATURE_SOC_I2S_COUNT (8) - /* @brief INPUTMUX availability on the SoC. */ - #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) - /* @brief IOCON availability on the SoC. */ - #define FSL_FEATURE_SOC_IOCON_COUNT (1) - /* @brief LPADC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPADC_COUNT (2) - /* @brief LPCMP availability on the SoC. */ - #define FSL_FEATURE_SOC_LPCMP_COUNT (3) - /* @brief LPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPDAC_COUNT (3) - /* @brief MAILBOX availability on the SoC. */ - #define FSL_FEATURE_SOC_MAILBOX_COUNT (1) - /* @brief MRT availability on the SoC. */ - #define FSL_FEATURE_SOC_MRT_COUNT (1) - /* @brief OPAMP availability on the SoC. */ - #define FSL_FEATURE_SOC_OPAMP_COUNT (3) - /* @brief OSTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) - /* @brief PINT availability on the SoC. */ - #define FSL_FEATURE_SOC_PINT_COUNT (1) - /* @brief SECPINT availability on the SoC. */ - #define FSL_FEATURE_SOC_SECPINT_COUNT (1) - /* @brief PMC availability on the SoC. */ - #define FSL_FEATURE_SOC_PMC_COUNT (1) - /* @brief POWERQUAD availability on the SoC. */ - #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) - /* @brief PWM availability on the SoC. */ - #define FSL_FEATURE_SOC_PWM_COUNT (2) - /* @brief PUF availability on the SoC. */ - #define FSL_FEATURE_SOC_PUF_COUNT (1) - /* @brief RTC availability on the SoC. */ - #define FSL_FEATURE_SOC_RTC_COUNT (2) - /* @brief SCT availability on the SoC. */ - #define FSL_FEATURE_SOC_SCT_COUNT (1) - /* @brief SPI availability on the SoC. */ - #define FSL_FEATURE_SOC_SPI_COUNT (9) - /* @brief SYSCON availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSCON_COUNT (1) - /* @brief USART availability on the SoC. */ - #define FSL_FEATURE_SOC_USART_COUNT (8) - /* @brief UTICK availability on the SoC. */ - #define FSL_FEATURE_SOC_UTICK_COUNT (1) - /* @brief VREF availability on the SoC. */ - #define FSL_FEATURE_SOC_VREF_COUNT (1) - /* @brief WWDT availability on the SoC. */ - #define FSL_FEATURE_SOC_WWDT_COUNT (1) -#endif - -/* LPADC module features */ - -/* @brief FIFO availability on the SoC. */ -#define FSL_FEATURE_LPADC_FIFO_COUNT (2) -/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) -/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) -/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) -/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) -/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) -/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) -/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) -/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) -/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) -/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) -/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) -/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) -/* @brief Has calibration (bitfield CFG[CALOFS]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) -/* @brief Has offset trim (register OFSTRIM). */ -#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) -/* @brief Has trigger status (register TSTAT). */ -#define FSL_FEATURE_LPADC_HAS_TSTAT (1) -/* @brief Has internal temperature sensor. */ -#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) -/* @brief Temperature sensor parameter A (slope). */ -#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (768.0f) -/* @brief Temperature sensor parameter B (offset). */ -#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (292.7f) -/* @brief Temperature sensor parameter Alpha. */ -#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (9.7f) -/* @brief Temperature sensor need calibration. */ -#define FSL_FEATURE_LPADC_TEMP_NEED_CALIBRATION (1) -/* @brief the address of temperature sensor parameter A (slope) in Flash. */ -#define FSL_FEATURE_FLASH_NMPA_TEMP_SLOPE_ADDRS (0x3FD28U) -/* @brief the address of temperature sensor parameter B (offset) in Flash. */ -#define FSL_FEATURE_FLASH_NMPA_TEMP_OFFSET_ADDRS (0x3FD2CU) -/* @brief the buffer size of temperature sensor. */ -#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) - -/* ANACTRL module features */ - -/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ -#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) -/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ -#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (1) -/* @brief Has FREQ_ME_CTRL reigster. */ -#define FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL (1) -/* @brief Has auxiliary bias(register AUX_BIAS). */ -#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (0) -/* @brief ANACTRL control VDDMAIN. */ -#define FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN (1) - -/* AOI module features */ - -/* @brief Maximum value of input mux. */ -#define FSL_FEATURE_AOI_MODULE_INPUTS (4) -/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ -#define FSL_FEATURE_AOI_EVENT_COUNT (4) - -/* CACHE64_CTRL module features */ - -/* @brief Cache Line size in byte. */ -#define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32) - -/* CACHE64_POLSEL module features */ - -/* No feature definitions */ - -/* CAN module features */ - -/* @brief Support CANFD or not */ -#define FSL_FEATURE_CAN_SUPPORT_CANFD (1) - -/* CRC module features */ - -/* @brief Has data register with name CRC */ -#define FSL_FEATURE_CRC_HAS_CRC_REG (0) - -/* CTIMER module features */ - -/* No feature definitions */ - -/* LPDAC module features */ - -/* @brief FIFO size. */ -#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) -/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ -#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) -/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ -#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) -/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ -#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) -/* @brief VREF source number. */ -#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) -/* @brief Has internal reference current options. */ -#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) - -/* DMA module features */ - -/* @brief Number of channels */ -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) \ - (((x) == DMA0) ? (52) : \ - (((x) == DMA1) ? (16) : (-1))) -/* @brief Max channels */ -#define FSL_FEATURE_DMA_MAX_CHANNELS (52) -/* @brief All channels */ -#define FSL_FEATURE_DMA_ALL_CHANNELS (68U) -/* @brief Align size of DMA0 descriptor */ -#define FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE (1024) -/* @brief Align size of DMA1 descriptor */ -#define FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE (256) -/* @brief Align size of DMA descriptor */ -#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn(x) \ - (((x) == DMA0) ? (1024) : \ - (((x) == DMA1) ? (256) : (-1))) -/* @brief DMA head link descriptor table align size */ -#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) - -/* DMIC module features */ - -/* @brief Number of channels */ -#define FSL_FEATURE_DMIC_CHANNEL_NUM (2) -/* @brief DMIC channel FIFO register support sign extended */ -#define FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND (1) -/* @brief DMIC has no IOCFG register */ -#define FSL_FEATURE_DMIC_HAS_NO_IOCFG (1) -/* @brief DMIC has decimator reset function */ -#define FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC (1) -/* @brief DMIC has global channel synchronization function */ -#define FSL_FEATURE_DMIC_HAS_GLOBAL_SYNC_FUNC (1) - -/* FLEXCOMM module features */ - -/* @brief FLEXCOMM0 USART INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) -/* @brief FLEXCOMM0 SPI INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) -/* @brief FLEXCOMM0 I2C INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) -/* @brief FLEXCOMM0 I2S INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) -/* @brief FLEXCOMM1 USART INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) -/* @brief FLEXCOMM1 SPI INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) -/* @brief FLEXCOMM1 I2C INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) -/* @brief FLEXCOMM1 I2S INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) -/* @brief FLEXCOMM2 USART INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) -/* @brief FLEXCOMM2 SPI INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) -/* @brief FLEXCOMM2 I2C INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) -/* @brief FLEXCOMM2 I2S INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) -/* @brief FLEXCOMM3 USART INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) -/* @brief FLEXCOMM3 SPI INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) -/* @brief FLEXCOMM3 I2C INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) -/* @brief FLEXCOMM3 I2S INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) -/* @brief FLEXCOMM4 USART INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) -/* @brief FLEXCOMM4 SPI INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) -/* @brief FLEXCOMM4 I2C INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) -/* @brief FLEXCOMM4 I2S INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) -/* @brief FLEXCOMM5 USART INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) -/* @brief FLEXCOMM5 SPI INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) -/* @brief FLEXCOMM5 I2C INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) -/* @brief FLEXCOMM5 I2S INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) -/* @brief FLEXCOMM6 USART INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) -/* @brief FLEXCOMM6 SPI INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) -/* @brief FLEXCOMM6 I2C INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) -/* @brief FLEXCOMM6 I2S INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) -/* @brief FLEXCOMM7 USART INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) -/* @brief FLEXCOMM7 SPI INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) -/* @brief FLEXCOMM7 I2C INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) -/* @brief FLEXCOMM7 I2S INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) -/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ -#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) -/* @brief I2S has DMIC interconnection */ -#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \ - (((x) == FLEXCOMM0) ? (0) : \ - (((x) == FLEXCOMM1) ? (0) : \ - (((x) == FLEXCOMM2) ? (0) : \ - (((x) == FLEXCOMM3) ? (0) : \ - (((x) == FLEXCOMM4) ? (0) : \ - (((x) == FLEXCOMM5) ? (0) : \ - (((x) == FLEXCOMM6) ? (0) : \ - (((x) == FLEXCOMM7) ? (1) : \ - (((x) == FLEXCOMM8) ? (0) : (-1)))))))))) -/* @brief I2S support dual channel transfer */ -#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn(x) \ - (((x) == FLEXCOMM0) ? (0) : \ - (((x) == FLEXCOMM1) ? (0) : \ - (((x) == FLEXCOMM2) ? (0) : \ - (((x) == FLEXCOMM3) ? (0) : \ - (((x) == FLEXCOMM4) ? (0) : \ - (((x) == FLEXCOMM5) ? (0) : \ - (((x) == FLEXCOMM6) ? (1) : \ - (((x) == FLEXCOMM7) ? (1) : \ - (((x) == FLEXCOMM8) ? (0) : (-1)))))))))) - -/* FLEXSPI module features */ - -/* @brief FlexSPI AHB buffer count */ -#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) -/* @brief FlexSPI has no MCR0 ARDFEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) -/* @brief FlexSPI has no MCR0 ATDFEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) -/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) -/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) -/* @brief FlexSPI has no IPCR1 IPAREN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_IPCR1_IPAREN (1) -/* @brief FlexSPI has no AHBCR APAREN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_AHBCR_APAREN (1) -/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (1) -/* @brief FlexSPI has no FLSHCR4 WMENB bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (1) -/* @brief FlexSPI has no STS2 BSLVLOCK bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (1) -/* @brief FlexSPI has no STS2 BREFLOCK bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (1) -/* @brief FlexSPI supports Port A only, do not support Port B. */ -#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (1) -/* @brief FlexSPI LUTKEY is read only. */ -#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (1) - -/* I2S module features */ - -/* @brief I2S support dual channel transfer. */ -#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) -/* @brief I2S has DMIC interconnection. */ -#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (1) - -/* I3C module features */ - -/* @brief Has TERM bitfile in MERRWARN reigster. */ -#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (1) - -/* INPUTMUX module features */ - -/* @brief Number of channels */ -#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) -/* @brief Inputmux has channel mux control */ -#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) - -/* IOCON module features */ - -/* @brief Func bit field width */ -#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) - -/* MRT module features */ - -/* @brief number of channels. */ -#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) - -/* PINT module features */ - -/* @brief Number of connected outputs */ -#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) -/* @brief Number of connected outputs */ -#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) - -/* PMC module features */ - -/* @brief UTICK does not support PD configure. */ -#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) -/* @brief WDT OSC does not support PD configure. */ -#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) - -/* POWERQUAD module features */ - -/* @brief Sine and Cossine fix errata */ -#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1) - -/* PUF module features */ - -/* @brief the shift status value */ -#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) - -/* PWM module features */ - -/* @brief If (e)FlexPWM has module A channels (outputs). */ -#define FSL_FEATURE_PWM_HAS_CHANNELA (1) -/* @brief If (e)FlexPWM has module B channels (outputs). */ -#define FSL_FEATURE_PWM_HAS_CHANNELB (1) -/* @brief If (e)FlexPWM has module X channels (outputs). */ -#define FSL_FEATURE_PWM_HAS_CHANNELX (1) -/* @brief If (e)FlexPWM has fractional feature. */ -#define FSL_FEATURE_PWM_HAS_FRACTIONAL (1) -/* @brief If (e)FlexPWM has mux trigger source select bit field. */ -#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) -/* @brief Number of submodules in each (e)FlexPWM module. */ -#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U) -/* @brief Number of fault channel in each (e)FlexPWM module. */ -#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) - -/* RTC module features */ - -/* @brief Has Tamper Direction Register support. */ -#define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0) -/* @brief Has Tamper Queue Status and Control Register support. */ -#define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (1) -/* @brief Has RTC subsystem. */ -#define FSL_FEATURE_RTC_HAS_SUBSYSTEM (1) -/* @brief Has Reset in system level. */ -#define FSL_FEATURE_RTC_HAS_RESET (1) -/* @brief Has RTC Tamper 23 Filter Configuration Register support. */ -#define FSL_FEATURE_RTC_HAS_FILTER23_CFG (1) -/* @brief Has WAKEUP_MODE bitfile in CTRL2 reigster. */ -#define FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE (1) - -/* SCT module features */ - -/* @brief Number of events */ -#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) -/* @brief Number of states */ -#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) -/* @brief Number of match capture */ -#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) -/* @brief Number of outputs */ -#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) - -/* SECPINT module features */ - -/* @brief Number of connected outputs */ -#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) - -/* SYSCON module features */ - -/* @brief Flash page size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) -/* @brief Flash sector size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) -/* @brief Flash size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (251904) - -/* SYSCTL module features */ - -/* @brief SYSCTRL has Code Gray feature. */ -#define FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY (1) - -/* USB module features */ - -#if defined(CPU_LPC55S36JBD100) - /* @brief USB version */ - #define FSL_FEATURE_USB_VERSION (200) - /* @brief Number of the endpoint in USB FS */ - #define FSL_FEATURE_USB_EP_NUM (5) -#endif /* defined(CPU_LPC55S36JBD100) */ - -/* USBFSH module features */ - -#if defined(CPU_LPC55S36JBD100) - /* @brief USBFSH version */ - #define FSL_FEATURE_USBFSH_VERSION (200) -#endif /* defined(CPU_LPC55S36JBD100) */ - -/* VREF module features */ - -/* @brief Has chop oscillator (bit TRM[CHOPEN]) */ -#define FSL_FEATURE_VREF_HAS_CHOP_OSC (0) -/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ -#define FSL_FEATURE_VREF_HAS_COMPENSATION (0) -/* @brief If high/low buffer mode supported */ -#define FSL_FEATURE_VREF_MODE_LV_TYPE (0) -/* @brief Module has also low reference (registers VREFL/VREFH) */ -#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) -/* @brief Has VREF_TRM4. */ -#define FSL_FEATURE_VREF_HAS_TRM4 (0) - -/* WWDT module features */ - -/* No feature definitions */ - -#endif /* _LPC55S36_FEATURES_H_ */ - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_256.FLM b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_256.FLM deleted file mode 100644 index a2d5023499b..00000000000 Binary files a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_256.FLM and /dev/null differ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_FLEXSPI.FLM b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_FLEXSPI.FLM deleted file mode 100644 index 5e1761e5449..00000000000 Binary files a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_FLEXSPI.FLM and /dev/null differ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_FLEXSPI_S.FLM b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_FLEXSPI_S.FLM deleted file mode 100644 index a98a90d28e8..00000000000 Binary files a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_FLEXSPI_S.FLM and /dev/null differ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_S_256.FLM b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_S_256.FLM deleted file mode 100644 index a1c8df323a3..00000000000 Binary files a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_S_256.FLM and /dev/null differ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC55S36_flash.scf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC55S36_flash.scf deleted file mode 100644 index 7e54ddd6c45..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC55S36_flash.scf +++ /dev/null @@ -1,88 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c -/* -** ################################################################### -** Processors: LPC55S36JBD100 -** LPC55S36JHI48 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 -** Version: rev. 1.1, 2021-08-04 -** Build: b210913 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#if (defined(__pkc__)) - #define retention_RAMsize 0x00004000 /* SRAM A(16K) reserved for pkc */ -#elif (defined(__power_down__)) - #define retention_RAMsize 0x00000604 /* The first 0x604 bytes reserved to CPU retention for power down mode */ -#else - #define retention_RAMsize 0x00000000 -#endif - -#if (defined(__powerquad__)) - #define powerquad_RAMsize 0x00004000 /* SRAM E(16K) reserved for powerquad */ -#else - #define powerquad_RAMsize 0x00000000 -#endif - -#define m_interrupts_start 0x00000000 -#define m_interrupts_size 0x00000400 - -#define m_text_start 0x00000400 -#define m_text_size 0x0003D400 - -#define m_data_start 0x20000000 + retention_RAMsize -#define m_data_size 0x0001C000 - retention_RAMsize - powerquad_RAMsize - -#define m_sramx_start 0x04000000 -#define m_sramx_size 0x00004000 - -LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region - - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC55S36_ram.scf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC55S36_ram.scf deleted file mode 100644 index 5ef0aa1795c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC55S36_ram.scf +++ /dev/null @@ -1,84 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c -/* -** ################################################################### -** Processors: LPC55S36JBD100 -** LPC55S36JHI48 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 -** Version: rev. 1.1, 2021-08-04 -** Build: b210913 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#if (defined(__pkc__)) - #define retention_RAMsize 0x00004000 /* SRAM A(16K) reserved for pkc */ -#elif (defined(__power_down__)) - #define retention_RAMsize 0x00000604 /* The first 0x604 bytes reserved to CPU retention for power down mode */ -#else - #define retention_RAMsize 0x00000000 -#endif - -#if (defined(__powerquad__)) - #define powerquad_RAMsize 0x00004000 /* SRAM E(16K) reserved for powerquad */ -#else - #define powerquad_RAMsize 0x00000000 -#endif - -#define m_interrupts_start 0x20000000 + retention_RAMsize -#define m_interrupts_size 0x00000400 - -#define m_text_start 0x20000400 + retention_RAMsize -#define m_text_size 0x0001BC00 - retention_RAMsize - powerquad_RAMsize - -#define m_data_start 0x04000000 -#define m_data_size 0x00004000 - -LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region - - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC55xx.dbgconf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC55xx.dbgconf deleted file mode 100644 index a59776c1989..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC55xx.dbgconf +++ /dev/null @@ -1,18 +0,0 @@ -// <<< Use Configuration Wizard in Context Menu >>> - -// SWO pin -// The SWO (Serial Wire Output) pin optionally provides data from the ITM -// for an external debug tool to evaluate. -// <0=> PIO0_10 -// <1=> PIO0_8 -SWO_Pin = 0; -// - -// Debug Configuration -// StopAfterBootloader Stop after Bootloader -// -Dbg_CR = 0x00000001; -// - - -// <<< end of configuration section >>> diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/startup_LPC55S36.S b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/startup_LPC55S36.S deleted file mode 100644 index 154a194ae12..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/startup_LPC55S36.S +++ /dev/null @@ -1,1461 +0,0 @@ -/* --------------------------------------------------------------------------------------- - * @file: startup_LPC55S36.s - * @purpose: CMSIS Cortex-M33 Core Device Startup File for the LPC55S36 - * @version: 1.1 - * @date: 2021-8-4 - * ---------------------------------------------------------------------------------------*/ -/* - * Copyright 1997-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - - .syntax unified - .arch armv8-m.main - .eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */ - - .section .isr_vector, "a" - .align 2 - .globl __Vectors - -__Vectors: - .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long MemManage_Handler /* MPU Fault Handler*/ - .long BusFault_Handler /* Bus Fault Handler*/ - .long UsageFault_Handler /* Usage Fault Handler*/ - .long SecureFault_Handler /* Secure Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long DebugMon_Handler /* Debug Monitor Handler*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts*/ - .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ - .long DMA0_IRQHandler /* DMA0 controller */ - .long GINT0_IRQHandler /* GPIO group 0 */ - .long GINT1_IRQHandler /* GPIO group 1 */ - .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - .long UTICK0_IRQHandler /* Micro-tick Timer */ - .long MRT0_IRQHandler /* Multi-rate timer */ - .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ - .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ - .long SCT0_IRQHandler /* SCTimer/PWM */ - .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ - .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long ADC0_IRQHandler /* ADC0 */ - .long ADC1_IRQHandler /* ADC1 */ - .long ACMP_IRQHandler /* ACMP interrupts */ - .long DMIC_IRQHandler /* Digital microphone and DMIC subsystem */ - .long HWVAD0_IRQHandler /* Hardware Voice Activity Detector */ - .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ - .long USB0_IRQHandler /* USB device */ - .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ - .long EZH_ARCH_B0_IRQHandler /* EZH interrupt */ - .long WAKEUP_IRQHandler /* Wakeup interrupt */ - .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ - .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ - .long OS_EVENT_IRQHandler /* OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ - .long FlexSPI0_IRQHandler /* FlexSPI interrupt */ - .long Reserved56_IRQHandler /* Reserved interrupt */ - .long Reserved57_IRQHandler /* Reserved interrupt */ - .long Reserved58_IRQHandler /* Reserved interrupt */ - .long CAN0_IRQ0_IRQHandler /* CAN0 interrupt0 */ - .long CAN0_IRQ1_IRQHandler /* CAN0 interrupt1 */ - .long SPI_FILTER_IRQHandler /* SPI Filter interrupt */ - .long Reserved62_IRQHandler /* Reserved interrupt */ - .long Reserved63_IRQHandler /* Reserved interrupt */ - .long Reserved64_IRQHandler /* Reserved interrupt */ - .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ - .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT00 interrupt */ - .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT01 interrupt */ - .long Freqme_IRQHandler /* frequency measure interrupt */ - .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ - .long SHA_IRQHandler /* SHA interrupt */ - .long PKC_IRQHandler /* CASPER interrupt */ - .long PUF_IRQHandler /* PUF interrupt */ - .long POWERQUAD_IRQHandler /* PowerQuad interrupt */ - .long DMA1_IRQHandler /* DMA1 interrupt */ - .long FLEXCOMM8_IRQHandler /* LSPI_HS interrupt */ - .long CDOG_IRQHandler /* CodeWDG interrupt */ - .long Reserved77_IRQHandler /* Reserved interrupt */ - .long I3C0_IRQHandler /* I3C interrupt */ - .long Reserved79_IRQHandler /* Reserved interrupt */ - .long Reserved80_IRQHandler /* Reserved interrupt */ - .long CSS_IRQ1_IRQHandler /* CSS_IRQ1 */ - .long Tamper_IRQHandler /* Tamper */ - .long Analog_Glitch_IRQHandler /* Analog_Glitch */ - .long Reserved84_IRQHandler /* Reserved interrupt */ - .long Reserved85_IRQHandler /* Reserved interrupt */ - .long Reserved86_IRQHandler /* Reserved interrupt */ - .long Reserved87_IRQHandler /* Reserved interrupt */ - .long Reserved88_IRQHandler /* Reserved interrupt */ - .long Reserved89_IRQHandler /* Reserved interrupt */ - .long DAC0_IRQHandler /* dac0 interrupt */ - .long DAC1_IRQHandler /* dac1 interrupt */ - .long DAC2_IRQHandler /* dac2 interrupt */ - .long HSCMP0_IRQHandler /* hscmp0 interrupt */ - .long HSCMP1_IRQHandler /* hscmp1 interrupt */ - .long HSCMP2_IRQHandler /* hscmp2 interrupt */ - .long FLEXPWM0_CAPTURE_IRQHandler /* flexpwm0_capture interrupt */ - .long FLEXPWM0_FAULT_IRQHandler /* flexpwm0_fault interrupt */ - .long FLEXPWM0_RELOAD_ERROR_IRQHandler /* flexpwm0_reload_error interrupt */ - .long FLEXPWM0_COMPARE0_IRQHandler /* flexpwm0_compare0 interrupt */ - .long FLEXPWM0_RELOAD0_IRQHandler /* flexpwm0_reload0 interrupt */ - .long FLEXPWM0_COMPARE1_IRQHandler /* flexpwm0_compare1 interrupt */ - .long FLEXPWM0_RELOAD1_IRQHandler /* flexpwm0_reload1 interrupt */ - .long FLEXPWM0_COMPARE2_IRQHandler /* flexpwm0_compare2 interrupt */ - .long FLEXPWM0_RELOAD2_IRQHandler /* flexpwm0_reload2 interrupt */ - .long FLEXPWM0_COMPARE3_IRQHandler /* flexpwm0_compare3 interrupt */ - .long FLEXPWM0_RELOAD3_IRQHandler /* flexpwm0_reload3 interrupt */ - .long FLEXPWM1_CAPTURE_IRQHandler /* flexpwm1_capture interrupt */ - .long FLEXPWM1_FAULT_IRQHandler /* flexpwm1_fault interrupt */ - .long FLEXPWM1_RELOAD_ERROR_IRQHandler /* flexpwm1_reload_error interrupt */ - .long FLEXPWM1_COMPARE0_IRQHandler /* flexpwm1_compare0 interrupt */ - .long FLEXPWM1_RELOAD0_IRQHandler /* flexpwm1_reload0 interrupt */ - .long FLEXPWM1_COMPARE1_IRQHandler /* flexpwm1_compare1 interrupt */ - .long FLEXPWM1_RELOAD1_IRQHandler /* flexpwm1_reload1 interrupt */ - .long FLEXPWM1_COMPARE2_IRQHandler /* flexpwm1_compare2 interrupt */ - .long FLEXPWM1_RELOAD2_IRQHandler /* flexpwm1_reload2 interrupt */ - .long FLEXPWM1_COMPARE3_IRQHandler /* flexpwm1_compare3 interrupt */ - .long FLEXPWM1_RELOAD3_IRQHandler /* flexpwm1_reload3 interrupt */ - .long ENC0_COMPARE_IRQHandler /* enc0_compare interrupt */ - .long ENC0_HOME_IRQHandler /* enc0_home interrupt */ - .long ENC0_WDG_IRQHandler /* enc0_wdg interrupt */ - .long ENC0_IDX_IRQHandler /* enc0_idx interrupt */ - .long ENC1_COMPARE_IRQHandler /* enc1_compare interrupt */ - .long ENC1_HOME_IRQHandler /* enc1_home interrupt */ - .long ENC1_WDG_IRQHandler /* enc1_wdg interrupt */ - .long ENC1_IDX_IRQHandler /* enc1_idx interrupt */ - .long ITRC0_IRQHandler /* itrc0 interrupt */ - .long Reserved127_IRQHandler /* Reserved interrupt */ - .long CSSV2_ERR_IRQHandler /* cssv2_err interrupt */ - .long PKC_ERR_IRQHandler /* pkc_err interrupt */ - .long Reserved130_IRQHandler /* Reserved interrupt */ - .long Reserved131_IRQHandler /* Reserved interrupt */ - .long Reserved132_IRQHandler /* Reserved interrupt */ - .long Reserved133_IRQHandler /* Reserved interrupt */ - .long FLASH_IRQHandler /* flash interrupt */ - .long RAM_PARITY_ECC_ERR_IRQHandler /* ram_parity_ecc_err interrupt */ - .size __Vectors, . - __Vectors - - .text - .thumb - -/* Reset Handler */ - .thumb_func - .align 2 - .weak Reset_Handler - .type Reset_Handler, %function - -Reset_Handler: - cpsid i /* Mask interrupts */ - .equ VTOR, 0xE000ED08 - ldr r0, =VTOR - ldr r1, =__Vectors - str r1, [r0] - ldr r2, [r1] - msr msp, r2 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Base - msr msplim, r0 - ldr r0,=SystemInit - blx r0 - cpsie i /* Unmask interrupts */ - ldr r0,=__main - bx r0 - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - .align 1 - .thumb_func - .weak WDT_BOD_IRQHandler - .type WDT_BOD_IRQHandler, %function -WDT_BOD_IRQHandler: - ldr r0,=WDT_BOD_DriverIRQHandler - bx r0 - .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler - - .align 1 - .thumb_func - .weak DMA0_IRQHandler - .type DMA0_IRQHandler, %function -DMA0_IRQHandler: - ldr r0,=DMA0_DriverIRQHandler - bx r0 - .size DMA0_IRQHandler, . - DMA0_IRQHandler - - .align 1 - .thumb_func - .weak GINT0_IRQHandler - .type GINT0_IRQHandler, %function -GINT0_IRQHandler: - ldr r0,=GINT0_DriverIRQHandler - bx r0 - .size GINT0_IRQHandler, . - GINT0_IRQHandler - - .align 1 - .thumb_func - .weak GINT1_IRQHandler - .type GINT1_IRQHandler, %function -GINT1_IRQHandler: - ldr r0,=GINT1_DriverIRQHandler - bx r0 - .size GINT1_IRQHandler, . - GINT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT0_IRQHandler - .type PIN_INT0_IRQHandler, %function -PIN_INT0_IRQHandler: - ldr r0,=PIN_INT0_DriverIRQHandler - bx r0 - .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT1_IRQHandler - .type PIN_INT1_IRQHandler, %function -PIN_INT1_IRQHandler: - ldr r0,=PIN_INT1_DriverIRQHandler - bx r0 - .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT2_IRQHandler - .type PIN_INT2_IRQHandler, %function -PIN_INT2_IRQHandler: - ldr r0,=PIN_INT2_DriverIRQHandler - bx r0 - .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT3_IRQHandler - .type PIN_INT3_IRQHandler, %function -PIN_INT3_IRQHandler: - ldr r0,=PIN_INT3_DriverIRQHandler - bx r0 - .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler - - .align 1 - .thumb_func - .weak UTICK0_IRQHandler - .type UTICK0_IRQHandler, %function -UTICK0_IRQHandler: - ldr r0,=UTICK0_DriverIRQHandler - bx r0 - .size UTICK0_IRQHandler, . - UTICK0_IRQHandler - - .align 1 - .thumb_func - .weak MRT0_IRQHandler - .type MRT0_IRQHandler, %function -MRT0_IRQHandler: - ldr r0,=MRT0_DriverIRQHandler - bx r0 - .size MRT0_IRQHandler, . - MRT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER0_IRQHandler - .type CTIMER0_IRQHandler, %function -CTIMER0_IRQHandler: - ldr r0,=CTIMER0_DriverIRQHandler - bx r0 - .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER1_IRQHandler - .type CTIMER1_IRQHandler, %function -CTIMER1_IRQHandler: - ldr r0,=CTIMER1_DriverIRQHandler - bx r0 - .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler - - .align 1 - .thumb_func - .weak SCT0_IRQHandler - .type SCT0_IRQHandler, %function -SCT0_IRQHandler: - ldr r0,=SCT0_DriverIRQHandler - bx r0 - .size SCT0_IRQHandler, . - SCT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER3_IRQHandler - .type CTIMER3_IRQHandler, %function -CTIMER3_IRQHandler: - ldr r0,=CTIMER3_DriverIRQHandler - bx r0 - .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM0_IRQHandler - .type FLEXCOMM0_IRQHandler, %function -FLEXCOMM0_IRQHandler: - ldr r0,=FLEXCOMM0_DriverIRQHandler - bx r0 - .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM1_IRQHandler - .type FLEXCOMM1_IRQHandler, %function -FLEXCOMM1_IRQHandler: - ldr r0,=FLEXCOMM1_DriverIRQHandler - bx r0 - .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM2_IRQHandler - .type FLEXCOMM2_IRQHandler, %function -FLEXCOMM2_IRQHandler: - ldr r0,=FLEXCOMM2_DriverIRQHandler - bx r0 - .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM3_IRQHandler - .type FLEXCOMM3_IRQHandler, %function -FLEXCOMM3_IRQHandler: - ldr r0,=FLEXCOMM3_DriverIRQHandler - bx r0 - .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM4_IRQHandler - .type FLEXCOMM4_IRQHandler, %function -FLEXCOMM4_IRQHandler: - ldr r0,=FLEXCOMM4_DriverIRQHandler - bx r0 - .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM5_IRQHandler - .type FLEXCOMM5_IRQHandler, %function -FLEXCOMM5_IRQHandler: - ldr r0,=FLEXCOMM5_DriverIRQHandler - bx r0 - .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM6_IRQHandler - .type FLEXCOMM6_IRQHandler, %function -FLEXCOMM6_IRQHandler: - ldr r0,=FLEXCOMM6_DriverIRQHandler - bx r0 - .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM7_IRQHandler - .type FLEXCOMM7_IRQHandler, %function -FLEXCOMM7_IRQHandler: - ldr r0,=FLEXCOMM7_DriverIRQHandler - bx r0 - .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_IRQHandler - .type ADC0_IRQHandler, %function -ADC0_IRQHandler: - ldr r0,=ADC0_DriverIRQHandler - bx r0 - .size ADC0_IRQHandler, . - ADC0_IRQHandler - - .align 1 - .thumb_func - .weak ADC1_IRQHandler - .type ADC1_IRQHandler, %function -ADC1_IRQHandler: - ldr r0,=ADC1_DriverIRQHandler - bx r0 - .size ADC1_IRQHandler, . - ADC1_IRQHandler - - .align 1 - .thumb_func - .weak ACMP_IRQHandler - .type ACMP_IRQHandler, %function -ACMP_IRQHandler: - ldr r0,=ACMP_DriverIRQHandler - bx r0 - .size ACMP_IRQHandler, . - ACMP_IRQHandler - - .align 1 - .thumb_func - .weak DMIC_IRQHandler - .type DMIC_IRQHandler, %function -DMIC_IRQHandler: - ldr r0,=DMIC_DriverIRQHandler - bx r0 - .size DMIC_IRQHandler, . - DMIC_IRQHandler - - .align 1 - .thumb_func - .weak HWVAD0_IRQHandler - .type HWVAD0_IRQHandler, %function -HWVAD0_IRQHandler: - ldr r0,=HWVAD0_DriverIRQHandler - bx r0 - .size HWVAD0_IRQHandler, . - HWVAD0_IRQHandler - - .align 1 - .thumb_func - .weak USB0_NEEDCLK_IRQHandler - .type USB0_NEEDCLK_IRQHandler, %function -USB0_NEEDCLK_IRQHandler: - ldr r0,=USB0_NEEDCLK_DriverIRQHandler - bx r0 - .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak USB0_IRQHandler - .type USB0_IRQHandler, %function -USB0_IRQHandler: - ldr r0,=USB0_DriverIRQHandler - bx r0 - .size USB0_IRQHandler, . - USB0_IRQHandler - - .align 1 - .thumb_func - .weak RTC_IRQHandler - .type RTC_IRQHandler, %function -RTC_IRQHandler: - ldr r0,=RTC_DriverIRQHandler - bx r0 - .size RTC_IRQHandler, . - RTC_IRQHandler - - .align 1 - .thumb_func - .weak EZH_ARCH_B0_IRQHandler - .type EZH_ARCH_B0_IRQHandler, %function -EZH_ARCH_B0_IRQHandler: - ldr r0,=EZH_ARCH_B0_DriverIRQHandler - bx r0 - .size EZH_ARCH_B0_IRQHandler, . - EZH_ARCH_B0_IRQHandler - - .align 1 - .thumb_func - .weak WAKEUP_IRQHandler - .type WAKEUP_IRQHandler, %function -WAKEUP_IRQHandler: - ldr r0,=WAKEUP_DriverIRQHandler - bx r0 - .size WAKEUP_IRQHandler, . - WAKEUP_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT4_IRQHandler - .type PIN_INT4_IRQHandler, %function -PIN_INT4_IRQHandler: - ldr r0,=PIN_INT4_DriverIRQHandler - bx r0 - .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT5_IRQHandler - .type PIN_INT5_IRQHandler, %function -PIN_INT5_IRQHandler: - ldr r0,=PIN_INT5_DriverIRQHandler - bx r0 - .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT6_IRQHandler - .type PIN_INT6_IRQHandler, %function -PIN_INT6_IRQHandler: - ldr r0,=PIN_INT6_DriverIRQHandler - bx r0 - .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT7_IRQHandler - .type PIN_INT7_IRQHandler, %function -PIN_INT7_IRQHandler: - ldr r0,=PIN_INT7_DriverIRQHandler - bx r0 - .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER2_IRQHandler - .type CTIMER2_IRQHandler, %function -CTIMER2_IRQHandler: - ldr r0,=CTIMER2_DriverIRQHandler - bx r0 - .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER4_IRQHandler - .type CTIMER4_IRQHandler, %function -CTIMER4_IRQHandler: - ldr r0,=CTIMER4_DriverIRQHandler - bx r0 - .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler - - .align 1 - .thumb_func - .weak OS_EVENT_IRQHandler - .type OS_EVENT_IRQHandler, %function -OS_EVENT_IRQHandler: - ldr r0,=OS_EVENT_DriverIRQHandler - bx r0 - .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler - - .align 1 - .thumb_func - .weak FlexSPI0_IRQHandler - .type FlexSPI0_IRQHandler, %function -FlexSPI0_IRQHandler: - ldr r0,=FlexSPI0_DriverIRQHandler - bx r0 - .size FlexSPI0_IRQHandler, . - FlexSPI0_IRQHandler - - .align 1 - .thumb_func - .weak Reserved56_IRQHandler - .type Reserved56_IRQHandler, %function -Reserved56_IRQHandler: - ldr r0,=Reserved56_DriverIRQHandler - bx r0 - .size Reserved56_IRQHandler, . - Reserved56_IRQHandler - - .align 1 - .thumb_func - .weak Reserved57_IRQHandler - .type Reserved57_IRQHandler, %function -Reserved57_IRQHandler: - ldr r0,=Reserved57_DriverIRQHandler - bx r0 - .size Reserved57_IRQHandler, . - Reserved57_IRQHandler - - .align 1 - .thumb_func - .weak Reserved58_IRQHandler - .type Reserved58_IRQHandler, %function -Reserved58_IRQHandler: - ldr r0,=Reserved58_DriverIRQHandler - bx r0 - .size Reserved58_IRQHandler, . - Reserved58_IRQHandler - - .align 1 - .thumb_func - .weak CAN0_IRQ0_IRQHandler - .type CAN0_IRQ0_IRQHandler, %function -CAN0_IRQ0_IRQHandler: - ldr r0,=CAN0_IRQ0_DriverIRQHandler - bx r0 - .size CAN0_IRQ0_IRQHandler, . - CAN0_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak CAN0_IRQ1_IRQHandler - .type CAN0_IRQ1_IRQHandler, %function -CAN0_IRQ1_IRQHandler: - ldr r0,=CAN0_IRQ1_DriverIRQHandler - bx r0 - .size CAN0_IRQ1_IRQHandler, . - CAN0_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak SPI_FILTER_IRQHandler - .type SPI_FILTER_IRQHandler, %function -SPI_FILTER_IRQHandler: - ldr r0,=SPI_FILTER_DriverIRQHandler - bx r0 - .size SPI_FILTER_IRQHandler, . - SPI_FILTER_IRQHandler - - .align 1 - .thumb_func - .weak Reserved62_IRQHandler - .type Reserved62_IRQHandler, %function -Reserved62_IRQHandler: - ldr r0,=Reserved62_DriverIRQHandler - bx r0 - .size Reserved62_IRQHandler, . - Reserved62_IRQHandler - - .align 1 - .thumb_func - .weak Reserved63_IRQHandler - .type Reserved63_IRQHandler, %function -Reserved63_IRQHandler: - ldr r0,=Reserved63_DriverIRQHandler - bx r0 - .size Reserved63_IRQHandler, . - Reserved63_IRQHandler - - .align 1 - .thumb_func - .weak Reserved64_IRQHandler - .type Reserved64_IRQHandler, %function -Reserved64_IRQHandler: - ldr r0,=Reserved64_DriverIRQHandler - bx r0 - .size Reserved64_IRQHandler, . - Reserved64_IRQHandler - - .align 1 - .thumb_func - .weak SEC_HYPERVISOR_CALL_IRQHandler - .type SEC_HYPERVISOR_CALL_IRQHandler, %function -SEC_HYPERVISOR_CALL_IRQHandler: - ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler - bx r0 - .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ0_IRQHandler - .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function -SEC_GPIO_INT0_IRQ0_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ1_IRQHandler - .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function -SEC_GPIO_INT0_IRQ1_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak Freqme_IRQHandler - .type Freqme_IRQHandler, %function -Freqme_IRQHandler: - ldr r0,=Freqme_DriverIRQHandler - bx r0 - .size Freqme_IRQHandler, . - Freqme_IRQHandler - - .align 1 - .thumb_func - .weak SEC_VIO_IRQHandler - .type SEC_VIO_IRQHandler, %function -SEC_VIO_IRQHandler: - ldr r0,=SEC_VIO_DriverIRQHandler - bx r0 - .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler - - .align 1 - .thumb_func - .weak SHA_IRQHandler - .type SHA_IRQHandler, %function -SHA_IRQHandler: - ldr r0,=SHA_DriverIRQHandler - bx r0 - .size SHA_IRQHandler, . - SHA_IRQHandler - - .align 1 - .thumb_func - .weak PKC_IRQHandler - .type PKC_IRQHandler, %function -PKC_IRQHandler: - ldr r0,=PKC_DriverIRQHandler - bx r0 - .size PKC_IRQHandler, . - PKC_IRQHandler - - .align 1 - .thumb_func - .weak PUF_IRQHandler - .type PUF_IRQHandler, %function -PUF_IRQHandler: - ldr r0,=PUF_DriverIRQHandler - bx r0 - .size PUF_IRQHandler, . - PUF_IRQHandler - - .align 1 - .thumb_func - .weak POWERQUAD_IRQHandler - .type POWERQUAD_IRQHandler, %function -POWERQUAD_IRQHandler: - ldr r0,=POWERQUAD_DriverIRQHandler - bx r0 - .size POWERQUAD_IRQHandler, . - POWERQUAD_IRQHandler - - .align 1 - .thumb_func - .weak DMA1_IRQHandler - .type DMA1_IRQHandler, %function -DMA1_IRQHandler: - ldr r0,=DMA1_DriverIRQHandler - bx r0 - .size DMA1_IRQHandler, . - DMA1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM8_IRQHandler - .type FLEXCOMM8_IRQHandler, %function -FLEXCOMM8_IRQHandler: - ldr r0,=FLEXCOMM8_DriverIRQHandler - bx r0 - .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler - - .align 1 - .thumb_func - .weak CDOG_IRQHandler - .type CDOG_IRQHandler, %function -CDOG_IRQHandler: - ldr r0,=CDOG_DriverIRQHandler - bx r0 - .size CDOG_IRQHandler, . - CDOG_IRQHandler - - .align 1 - .thumb_func - .weak Reserved77_IRQHandler - .type Reserved77_IRQHandler, %function -Reserved77_IRQHandler: - ldr r0,=Reserved77_DriverIRQHandler - bx r0 - .size Reserved77_IRQHandler, . - Reserved77_IRQHandler - - .align 1 - .thumb_func - .weak I3C0_IRQHandler - .type I3C0_IRQHandler, %function -I3C0_IRQHandler: - ldr r0,=I3C0_DriverIRQHandler - bx r0 - .size I3C0_IRQHandler, . - I3C0_IRQHandler - - .align 1 - .thumb_func - .weak Reserved79_IRQHandler - .type Reserved79_IRQHandler, %function -Reserved79_IRQHandler: - ldr r0,=Reserved79_DriverIRQHandler - bx r0 - .size Reserved79_IRQHandler, . - Reserved79_IRQHandler - - .align 1 - .thumb_func - .weak Reserved80_IRQHandler - .type Reserved80_IRQHandler, %function -Reserved80_IRQHandler: - ldr r0,=Reserved80_DriverIRQHandler - bx r0 - .size Reserved80_IRQHandler, . - Reserved80_IRQHandler - - .align 1 - .thumb_func - .weak CSS_IRQ1_IRQHandler - .type CSS_IRQ1_IRQHandler, %function -CSS_IRQ1_IRQHandler: - ldr r0,=CSS_IRQ1_DriverIRQHandler - bx r0 - .size CSS_IRQ1_IRQHandler, . - CSS_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak Tamper_IRQHandler - .type Tamper_IRQHandler, %function -Tamper_IRQHandler: - ldr r0,=Tamper_DriverIRQHandler - bx r0 - .size Tamper_IRQHandler, . - Tamper_IRQHandler - - .align 1 - .thumb_func - .weak Analog_Glitch_IRQHandler - .type Analog_Glitch_IRQHandler, %function -Analog_Glitch_IRQHandler: - ldr r0,=Analog_Glitch_DriverIRQHandler - bx r0 - .size Analog_Glitch_IRQHandler, . - Analog_Glitch_IRQHandler - - .align 1 - .thumb_func - .weak Reserved84_IRQHandler - .type Reserved84_IRQHandler, %function -Reserved84_IRQHandler: - ldr r0,=Reserved84_DriverIRQHandler - bx r0 - .size Reserved84_IRQHandler, . - Reserved84_IRQHandler - - .align 1 - .thumb_func - .weak Reserved85_IRQHandler - .type Reserved85_IRQHandler, %function -Reserved85_IRQHandler: - ldr r0,=Reserved85_DriverIRQHandler - bx r0 - .size Reserved85_IRQHandler, . - Reserved85_IRQHandler - - .align 1 - .thumb_func - .weak Reserved86_IRQHandler - .type Reserved86_IRQHandler, %function -Reserved86_IRQHandler: - ldr r0,=Reserved86_DriverIRQHandler - bx r0 - .size Reserved86_IRQHandler, . - Reserved86_IRQHandler - - .align 1 - .thumb_func - .weak Reserved87_IRQHandler - .type Reserved87_IRQHandler, %function -Reserved87_IRQHandler: - ldr r0,=Reserved87_DriverIRQHandler - bx r0 - .size Reserved87_IRQHandler, . - Reserved87_IRQHandler - - .align 1 - .thumb_func - .weak Reserved88_IRQHandler - .type Reserved88_IRQHandler, %function -Reserved88_IRQHandler: - ldr r0,=Reserved88_DriverIRQHandler - bx r0 - .size Reserved88_IRQHandler, . - Reserved88_IRQHandler - - .align 1 - .thumb_func - .weak Reserved89_IRQHandler - .type Reserved89_IRQHandler, %function -Reserved89_IRQHandler: - ldr r0,=Reserved89_DriverIRQHandler - bx r0 - .size Reserved89_IRQHandler, . - Reserved89_IRQHandler - - .align 1 - .thumb_func - .weak DAC0_IRQHandler - .type DAC0_IRQHandler, %function -DAC0_IRQHandler: - ldr r0,=DAC0_DriverIRQHandler - bx r0 - .size DAC0_IRQHandler, . - DAC0_IRQHandler - - .align 1 - .thumb_func - .weak DAC1_IRQHandler - .type DAC1_IRQHandler, %function -DAC1_IRQHandler: - ldr r0,=DAC1_DriverIRQHandler - bx r0 - .size DAC1_IRQHandler, . - DAC1_IRQHandler - - .align 1 - .thumb_func - .weak DAC2_IRQHandler - .type DAC2_IRQHandler, %function -DAC2_IRQHandler: - ldr r0,=DAC2_DriverIRQHandler - bx r0 - .size DAC2_IRQHandler, . - DAC2_IRQHandler - - .align 1 - .thumb_func - .weak HSCMP0_IRQHandler - .type HSCMP0_IRQHandler, %function -HSCMP0_IRQHandler: - ldr r0,=HSCMP0_DriverIRQHandler - bx r0 - .size HSCMP0_IRQHandler, . - HSCMP0_IRQHandler - - .align 1 - .thumb_func - .weak HSCMP1_IRQHandler - .type HSCMP1_IRQHandler, %function -HSCMP1_IRQHandler: - ldr r0,=HSCMP1_DriverIRQHandler - bx r0 - .size HSCMP1_IRQHandler, . - HSCMP1_IRQHandler - - .align 1 - .thumb_func - .weak HSCMP2_IRQHandler - .type HSCMP2_IRQHandler, %function -HSCMP2_IRQHandler: - ldr r0,=HSCMP2_DriverIRQHandler - bx r0 - .size HSCMP2_IRQHandler, . - HSCMP2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_CAPTURE_IRQHandler - .type FLEXPWM0_CAPTURE_IRQHandler, %function -FLEXPWM0_CAPTURE_IRQHandler: - ldr r0,=FLEXPWM0_CAPTURE_DriverIRQHandler - bx r0 - .size FLEXPWM0_CAPTURE_IRQHandler, . - FLEXPWM0_CAPTURE_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_FAULT_IRQHandler - .type FLEXPWM0_FAULT_IRQHandler, %function -FLEXPWM0_FAULT_IRQHandler: - ldr r0,=FLEXPWM0_FAULT_DriverIRQHandler - bx r0 - .size FLEXPWM0_FAULT_IRQHandler, . - FLEXPWM0_FAULT_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_RELOAD_ERROR_IRQHandler - .type FLEXPWM0_RELOAD_ERROR_IRQHandler, %function -FLEXPWM0_RELOAD_ERROR_IRQHandler: - ldr r0,=FLEXPWM0_RELOAD_ERROR_DriverIRQHandler - bx r0 - .size FLEXPWM0_RELOAD_ERROR_IRQHandler, . - FLEXPWM0_RELOAD_ERROR_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_COMPARE0_IRQHandler - .type FLEXPWM0_COMPARE0_IRQHandler, %function -FLEXPWM0_COMPARE0_IRQHandler: - ldr r0,=FLEXPWM0_COMPARE0_DriverIRQHandler - bx r0 - .size FLEXPWM0_COMPARE0_IRQHandler, . - FLEXPWM0_COMPARE0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_RELOAD0_IRQHandler - .type FLEXPWM0_RELOAD0_IRQHandler, %function -FLEXPWM0_RELOAD0_IRQHandler: - ldr r0,=FLEXPWM0_RELOAD0_DriverIRQHandler - bx r0 - .size FLEXPWM0_RELOAD0_IRQHandler, . - FLEXPWM0_RELOAD0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_COMPARE1_IRQHandler - .type FLEXPWM0_COMPARE1_IRQHandler, %function -FLEXPWM0_COMPARE1_IRQHandler: - ldr r0,=FLEXPWM0_COMPARE1_DriverIRQHandler - bx r0 - .size FLEXPWM0_COMPARE1_IRQHandler, . - FLEXPWM0_COMPARE1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_RELOAD1_IRQHandler - .type FLEXPWM0_RELOAD1_IRQHandler, %function -FLEXPWM0_RELOAD1_IRQHandler: - ldr r0,=FLEXPWM0_RELOAD1_DriverIRQHandler - bx r0 - .size FLEXPWM0_RELOAD1_IRQHandler, . - FLEXPWM0_RELOAD1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_COMPARE2_IRQHandler - .type FLEXPWM0_COMPARE2_IRQHandler, %function -FLEXPWM0_COMPARE2_IRQHandler: - ldr r0,=FLEXPWM0_COMPARE2_DriverIRQHandler - bx r0 - .size FLEXPWM0_COMPARE2_IRQHandler, . - FLEXPWM0_COMPARE2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_RELOAD2_IRQHandler - .type FLEXPWM0_RELOAD2_IRQHandler, %function -FLEXPWM0_RELOAD2_IRQHandler: - ldr r0,=FLEXPWM0_RELOAD2_DriverIRQHandler - bx r0 - .size FLEXPWM0_RELOAD2_IRQHandler, . - FLEXPWM0_RELOAD2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_COMPARE3_IRQHandler - .type FLEXPWM0_COMPARE3_IRQHandler, %function -FLEXPWM0_COMPARE3_IRQHandler: - ldr r0,=FLEXPWM0_COMPARE3_DriverIRQHandler - bx r0 - .size FLEXPWM0_COMPARE3_IRQHandler, . - FLEXPWM0_COMPARE3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_RELOAD3_IRQHandler - .type FLEXPWM0_RELOAD3_IRQHandler, %function -FLEXPWM0_RELOAD3_IRQHandler: - ldr r0,=FLEXPWM0_RELOAD3_DriverIRQHandler - bx r0 - .size FLEXPWM0_RELOAD3_IRQHandler, . - FLEXPWM0_RELOAD3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_CAPTURE_IRQHandler - .type FLEXPWM1_CAPTURE_IRQHandler, %function -FLEXPWM1_CAPTURE_IRQHandler: - ldr r0,=FLEXPWM1_CAPTURE_DriverIRQHandler - bx r0 - .size FLEXPWM1_CAPTURE_IRQHandler, . - FLEXPWM1_CAPTURE_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_FAULT_IRQHandler - .type FLEXPWM1_FAULT_IRQHandler, %function -FLEXPWM1_FAULT_IRQHandler: - ldr r0,=FLEXPWM1_FAULT_DriverIRQHandler - bx r0 - .size FLEXPWM1_FAULT_IRQHandler, . - FLEXPWM1_FAULT_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_RELOAD_ERROR_IRQHandler - .type FLEXPWM1_RELOAD_ERROR_IRQHandler, %function -FLEXPWM1_RELOAD_ERROR_IRQHandler: - ldr r0,=FLEXPWM1_RELOAD_ERROR_DriverIRQHandler - bx r0 - .size FLEXPWM1_RELOAD_ERROR_IRQHandler, . - FLEXPWM1_RELOAD_ERROR_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_COMPARE0_IRQHandler - .type FLEXPWM1_COMPARE0_IRQHandler, %function -FLEXPWM1_COMPARE0_IRQHandler: - ldr r0,=FLEXPWM1_COMPARE0_DriverIRQHandler - bx r0 - .size FLEXPWM1_COMPARE0_IRQHandler, . - FLEXPWM1_COMPARE0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_RELOAD0_IRQHandler - .type FLEXPWM1_RELOAD0_IRQHandler, %function -FLEXPWM1_RELOAD0_IRQHandler: - ldr r0,=FLEXPWM1_RELOAD0_DriverIRQHandler - bx r0 - .size FLEXPWM1_RELOAD0_IRQHandler, . - FLEXPWM1_RELOAD0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_COMPARE1_IRQHandler - .type FLEXPWM1_COMPARE1_IRQHandler, %function -FLEXPWM1_COMPARE1_IRQHandler: - ldr r0,=FLEXPWM1_COMPARE1_DriverIRQHandler - bx r0 - .size FLEXPWM1_COMPARE1_IRQHandler, . - FLEXPWM1_COMPARE1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_RELOAD1_IRQHandler - .type FLEXPWM1_RELOAD1_IRQHandler, %function -FLEXPWM1_RELOAD1_IRQHandler: - ldr r0,=FLEXPWM1_RELOAD1_DriverIRQHandler - bx r0 - .size FLEXPWM1_RELOAD1_IRQHandler, . - FLEXPWM1_RELOAD1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_COMPARE2_IRQHandler - .type FLEXPWM1_COMPARE2_IRQHandler, %function -FLEXPWM1_COMPARE2_IRQHandler: - ldr r0,=FLEXPWM1_COMPARE2_DriverIRQHandler - bx r0 - .size FLEXPWM1_COMPARE2_IRQHandler, . - FLEXPWM1_COMPARE2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_RELOAD2_IRQHandler - .type FLEXPWM1_RELOAD2_IRQHandler, %function -FLEXPWM1_RELOAD2_IRQHandler: - ldr r0,=FLEXPWM1_RELOAD2_DriverIRQHandler - bx r0 - .size FLEXPWM1_RELOAD2_IRQHandler, . - FLEXPWM1_RELOAD2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_COMPARE3_IRQHandler - .type FLEXPWM1_COMPARE3_IRQHandler, %function -FLEXPWM1_COMPARE3_IRQHandler: - ldr r0,=FLEXPWM1_COMPARE3_DriverIRQHandler - bx r0 - .size FLEXPWM1_COMPARE3_IRQHandler, . - FLEXPWM1_COMPARE3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_RELOAD3_IRQHandler - .type FLEXPWM1_RELOAD3_IRQHandler, %function -FLEXPWM1_RELOAD3_IRQHandler: - ldr r0,=FLEXPWM1_RELOAD3_DriverIRQHandler - bx r0 - .size FLEXPWM1_RELOAD3_IRQHandler, . - FLEXPWM1_RELOAD3_IRQHandler - - .align 1 - .thumb_func - .weak ENC0_COMPARE_IRQHandler - .type ENC0_COMPARE_IRQHandler, %function -ENC0_COMPARE_IRQHandler: - ldr r0,=ENC0_COMPARE_DriverIRQHandler - bx r0 - .size ENC0_COMPARE_IRQHandler, . - ENC0_COMPARE_IRQHandler - - .align 1 - .thumb_func - .weak ENC0_HOME_IRQHandler - .type ENC0_HOME_IRQHandler, %function -ENC0_HOME_IRQHandler: - ldr r0,=ENC0_HOME_DriverIRQHandler - bx r0 - .size ENC0_HOME_IRQHandler, . - ENC0_HOME_IRQHandler - - .align 1 - .thumb_func - .weak ENC0_WDG_IRQHandler - .type ENC0_WDG_IRQHandler, %function -ENC0_WDG_IRQHandler: - ldr r0,=ENC0_WDG_DriverIRQHandler - bx r0 - .size ENC0_WDG_IRQHandler, . - ENC0_WDG_IRQHandler - - .align 1 - .thumb_func - .weak ENC0_IDX_IRQHandler - .type ENC0_IDX_IRQHandler, %function -ENC0_IDX_IRQHandler: - ldr r0,=ENC0_IDX_DriverIRQHandler - bx r0 - .size ENC0_IDX_IRQHandler, . - ENC0_IDX_IRQHandler - - .align 1 - .thumb_func - .weak ENC1_COMPARE_IRQHandler - .type ENC1_COMPARE_IRQHandler, %function -ENC1_COMPARE_IRQHandler: - ldr r0,=ENC1_COMPARE_DriverIRQHandler - bx r0 - .size ENC1_COMPARE_IRQHandler, . - ENC1_COMPARE_IRQHandler - - .align 1 - .thumb_func - .weak ENC1_HOME_IRQHandler - .type ENC1_HOME_IRQHandler, %function -ENC1_HOME_IRQHandler: - ldr r0,=ENC1_HOME_DriverIRQHandler - bx r0 - .size ENC1_HOME_IRQHandler, . - ENC1_HOME_IRQHandler - - .align 1 - .thumb_func - .weak ENC1_WDG_IRQHandler - .type ENC1_WDG_IRQHandler, %function -ENC1_WDG_IRQHandler: - ldr r0,=ENC1_WDG_DriverIRQHandler - bx r0 - .size ENC1_WDG_IRQHandler, . - ENC1_WDG_IRQHandler - - .align 1 - .thumb_func - .weak ENC1_IDX_IRQHandler - .type ENC1_IDX_IRQHandler, %function -ENC1_IDX_IRQHandler: - ldr r0,=ENC1_IDX_DriverIRQHandler - bx r0 - .size ENC1_IDX_IRQHandler, . - ENC1_IDX_IRQHandler - - .align 1 - .thumb_func - .weak ITRC0_IRQHandler - .type ITRC0_IRQHandler, %function -ITRC0_IRQHandler: - ldr r0,=ITRC0_DriverIRQHandler - bx r0 - .size ITRC0_IRQHandler, . - ITRC0_IRQHandler - - .align 1 - .thumb_func - .weak Reserved127_IRQHandler - .type Reserved127_IRQHandler, %function -Reserved127_IRQHandler: - ldr r0,=Reserved127_DriverIRQHandler - bx r0 - .size Reserved127_IRQHandler, . - Reserved127_IRQHandler - - .align 1 - .thumb_func - .weak CSSV2_ERR_IRQHandler - .type CSSV2_ERR_IRQHandler, %function -CSSV2_ERR_IRQHandler: - ldr r0,=CSSV2_ERR_DriverIRQHandler - bx r0 - .size CSSV2_ERR_IRQHandler, . - CSSV2_ERR_IRQHandler - - .align 1 - .thumb_func - .weak PKC_ERR_IRQHandler - .type PKC_ERR_IRQHandler, %function -PKC_ERR_IRQHandler: - ldr r0,=PKC_ERR_DriverIRQHandler - bx r0 - .size PKC_ERR_IRQHandler, . - PKC_ERR_IRQHandler - - .align 1 - .thumb_func - .weak Reserved130_IRQHandler - .type Reserved130_IRQHandler, %function -Reserved130_IRQHandler: - ldr r0,=Reserved130_DriverIRQHandler - bx r0 - .size Reserved130_IRQHandler, . - Reserved130_IRQHandler - - .align 1 - .thumb_func - .weak Reserved131_IRQHandler - .type Reserved131_IRQHandler, %function -Reserved131_IRQHandler: - ldr r0,=Reserved131_DriverIRQHandler - bx r0 - .size Reserved131_IRQHandler, . - Reserved131_IRQHandler - - .align 1 - .thumb_func - .weak Reserved132_IRQHandler - .type Reserved132_IRQHandler, %function -Reserved132_IRQHandler: - ldr r0,=Reserved132_DriverIRQHandler - bx r0 - .size Reserved132_IRQHandler, . - Reserved132_IRQHandler - - .align 1 - .thumb_func - .weak Reserved133_IRQHandler - .type Reserved133_IRQHandler, %function -Reserved133_IRQHandler: - ldr r0,=Reserved133_DriverIRQHandler - bx r0 - .size Reserved133_IRQHandler, . - Reserved133_IRQHandler - - .align 1 - .thumb_func - .weak FLASH_IRQHandler - .type FLASH_IRQHandler, %function -FLASH_IRQHandler: - ldr r0,=FLASH_DriverIRQHandler - bx r0 - .size FLASH_IRQHandler, . - FLASH_IRQHandler - - .align 1 - .thumb_func - .weak RAM_PARITY_ECC_ERR_IRQHandler - .type RAM_PARITY_ECC_ERR_IRQHandler, %function -RAM_PARITY_ECC_ERR_IRQHandler: - ldr r0,=RAM_PARITY_ECC_ERR_DriverIRQHandler - bx r0 - .size RAM_PARITY_ECC_ERR_IRQHandler, . - RAM_PARITY_ECC_ERR_IRQHandler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm -/* Exception Handlers */ - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SecureFault_Handler - def_irq_handler DebugMon_Handler - def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ - def_irq_handler DMA0_DriverIRQHandler /* DMA0 controller */ - def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */ - def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */ - def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */ - def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */ - def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */ - def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */ - def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */ - def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */ - def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler ADC0_DriverIRQHandler /* ADC0 */ - def_irq_handler ADC1_DriverIRQHandler /* ADC1 */ - def_irq_handler ACMP_DriverIRQHandler /* ACMP interrupts */ - def_irq_handler DMIC_DriverIRQHandler /* Digital microphone and DMIC subsystem */ - def_irq_handler HWVAD0_DriverIRQHandler /* Hardware Voice Activity Detector */ - def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */ - def_irq_handler USB0_DriverIRQHandler /* USB device */ - def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */ - def_irq_handler EZH_ARCH_B0_DriverIRQHandler /* EZH interrupt */ - def_irq_handler WAKEUP_DriverIRQHandler /* Wakeup interrupt */ - def_irq_handler PIN_INT4_DriverIRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - def_irq_handler PIN_INT5_DriverIRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - def_irq_handler PIN_INT6_DriverIRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - def_irq_handler PIN_INT7_DriverIRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - def_irq_handler CTIMER2_DriverIRQHandler /* Standard counter/timer CTIMER2 */ - def_irq_handler CTIMER4_DriverIRQHandler /* Standard counter/timer CTIMER4 */ - def_irq_handler OS_EVENT_DriverIRQHandler /* OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ - def_irq_handler FlexSPI0_DriverIRQHandler /* FlexSPI interrupt */ - def_irq_handler Reserved56_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved57_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved58_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler CAN0_IRQ0_DriverIRQHandler /* CAN0 interrupt0 */ - def_irq_handler CAN0_IRQ1_DriverIRQHandler /* CAN0 interrupt1 */ - def_irq_handler SPI_FILTER_DriverIRQHandler /* SPI Filter interrupt */ - def_irq_handler Reserved62_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved63_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved64_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler /* SEC_HYPERVISOR_CALL interrupt */ - def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler /* SEC_GPIO_INT00 interrupt */ - def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler /* SEC_GPIO_INT01 interrupt */ - def_irq_handler Freqme_DriverIRQHandler /* frequency measure interrupt */ - def_irq_handler SEC_VIO_DriverIRQHandler /* SEC_VIO interrupt */ - def_irq_handler SHA_DriverIRQHandler /* SHA interrupt */ - def_irq_handler PKC_DriverIRQHandler /* CASPER interrupt */ - def_irq_handler PUF_DriverIRQHandler /* PUF interrupt */ - def_irq_handler POWERQUAD_DriverIRQHandler /* PowerQuad interrupt */ - def_irq_handler DMA1_DriverIRQHandler /* DMA1 interrupt */ - def_irq_handler FLEXCOMM8_DriverIRQHandler /* LSPI_HS interrupt */ - def_irq_handler CDOG_DriverIRQHandler /* CodeWDG interrupt */ - def_irq_handler Reserved77_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler I3C0_DriverIRQHandler /* I3C interrupt */ - def_irq_handler Reserved79_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved80_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler CSS_IRQ1_DriverIRQHandler /* CSS_IRQ1 */ - def_irq_handler Tamper_DriverIRQHandler /* Tamper */ - def_irq_handler Analog_Glitch_DriverIRQHandler /* Analog_Glitch */ - def_irq_handler Reserved84_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved85_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved86_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved87_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved88_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved89_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler DAC0_DriverIRQHandler /* dac0 interrupt */ - def_irq_handler DAC1_DriverIRQHandler /* dac1 interrupt */ - def_irq_handler DAC2_DriverIRQHandler /* dac2 interrupt */ - def_irq_handler HSCMP0_DriverIRQHandler /* hscmp0 interrupt */ - def_irq_handler HSCMP1_DriverIRQHandler /* hscmp1 interrupt */ - def_irq_handler HSCMP2_DriverIRQHandler /* hscmp2 interrupt */ - def_irq_handler FLEXPWM0_CAPTURE_DriverIRQHandler /* flexpwm0_capture interrupt */ - def_irq_handler FLEXPWM0_FAULT_DriverIRQHandler /* flexpwm0_fault interrupt */ - def_irq_handler FLEXPWM0_RELOAD_ERROR_DriverIRQHandler /* flexpwm0_reload_error interrupt */ - def_irq_handler FLEXPWM0_COMPARE0_DriverIRQHandler /* flexpwm0_compare0 interrupt */ - def_irq_handler FLEXPWM0_RELOAD0_DriverIRQHandler /* flexpwm0_reload0 interrupt */ - def_irq_handler FLEXPWM0_COMPARE1_DriverIRQHandler /* flexpwm0_compare1 interrupt */ - def_irq_handler FLEXPWM0_RELOAD1_DriverIRQHandler /* flexpwm0_reload1 interrupt */ - def_irq_handler FLEXPWM0_COMPARE2_DriverIRQHandler /* flexpwm0_compare2 interrupt */ - def_irq_handler FLEXPWM0_RELOAD2_DriverIRQHandler /* flexpwm0_reload2 interrupt */ - def_irq_handler FLEXPWM0_COMPARE3_DriverIRQHandler /* flexpwm0_compare3 interrupt */ - def_irq_handler FLEXPWM0_RELOAD3_DriverIRQHandler /* flexpwm0_reload3 interrupt */ - def_irq_handler FLEXPWM1_CAPTURE_DriverIRQHandler /* flexpwm1_capture interrupt */ - def_irq_handler FLEXPWM1_FAULT_DriverIRQHandler /* flexpwm1_fault interrupt */ - def_irq_handler FLEXPWM1_RELOAD_ERROR_DriverIRQHandler /* flexpwm1_reload_error interrupt */ - def_irq_handler FLEXPWM1_COMPARE0_DriverIRQHandler /* flexpwm1_compare0 interrupt */ - def_irq_handler FLEXPWM1_RELOAD0_DriverIRQHandler /* flexpwm1_reload0 interrupt */ - def_irq_handler FLEXPWM1_COMPARE1_DriverIRQHandler /* flexpwm1_compare1 interrupt */ - def_irq_handler FLEXPWM1_RELOAD1_DriverIRQHandler /* flexpwm1_reload1 interrupt */ - def_irq_handler FLEXPWM1_COMPARE2_DriverIRQHandler /* flexpwm1_compare2 interrupt */ - def_irq_handler FLEXPWM1_RELOAD2_DriverIRQHandler /* flexpwm1_reload2 interrupt */ - def_irq_handler FLEXPWM1_COMPARE3_DriverIRQHandler /* flexpwm1_compare3 interrupt */ - def_irq_handler FLEXPWM1_RELOAD3_DriverIRQHandler /* flexpwm1_reload3 interrupt */ - def_irq_handler ENC0_COMPARE_DriverIRQHandler /* enc0_compare interrupt */ - def_irq_handler ENC0_HOME_DriverIRQHandler /* enc0_home interrupt */ - def_irq_handler ENC0_WDG_DriverIRQHandler /* enc0_wdg interrupt */ - def_irq_handler ENC0_IDX_DriverIRQHandler /* enc0_idx interrupt */ - def_irq_handler ENC1_COMPARE_DriverIRQHandler /* enc1_compare interrupt */ - def_irq_handler ENC1_HOME_DriverIRQHandler /* enc1_home interrupt */ - def_irq_handler ENC1_WDG_DriverIRQHandler /* enc1_wdg interrupt */ - def_irq_handler ENC1_IDX_DriverIRQHandler /* enc1_idx interrupt */ - def_irq_handler ITRC0_DriverIRQHandler /* itrc0 interrupt */ - def_irq_handler Reserved127_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler CSSV2_ERR_DriverIRQHandler /* cssv2_err interrupt */ - def_irq_handler PKC_ERR_DriverIRQHandler /* pkc_err interrupt */ - def_irq_handler Reserved130_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved131_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved132_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved133_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler FLASH_DriverIRQHandler /* flash interrupt */ - def_irq_handler RAM_PARITY_ECC_ERR_DriverIRQHandler /* ram_parity_ecc_err interrupt */ - - .end diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/fsl_flash.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/fsl_flash.h deleted file mode 100644 index 9e387ff1840..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/fsl_flash.h +++ /dev/null @@ -1,624 +0,0 @@ -/* - * Copyright 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _FSL_FLASH_H_ -#define _FSL_FLASH_H_ - -#include "fsl_common.h" -/*! - * @addtogroup flash_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! - * @name Flash version - * @{ - */ -/*! @brief Constructs the version number for drivers. */ -#if !defined(MAKE_VERSION) -#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) -#endif - -/*! @brief Flash driver version for SDK*/ -#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(1, 0, 1)) /*!< Version 1.0.1. */ - -/*! @brief Flash driver version for ROM*/ -enum _flash_driver_version_constants -{ - kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ - kFLASH_DriverVersionMajor = 1, /*!< Major flash driver version.*/ - kFLASH_DriverVersionMinor = 0, /*!< Minor flash driver version.*/ - kFLASH_DriverVersionBugfix = 1 /*!< Bugfix for flash driver version.*/ -}; -/*@}*/ - -/*! - * @name Flash driver support feature - * @{ - */ -/*! @brief IAP driver support non-block erase function */ -#define FSL_SUPPORT_ERASE_SECTOR_NON_BLOCKING 1U - -#define FSL_FEATURE_SYSCON_HAS_FLASH_HIDING 1U - -#define FSL_FEATURE_SYSCON_HAS_CDPA 1U -/*@}*/ - -/*! - * @name Flash status - * @{ - */ -/*! @brief Flash driver status group. */ -#if defined(kStatusGroup_FlashDriver) -#define kStatusGroupGeneric kStatusGroup_Generic -#define kStatusGroupFlashDriver kStatusGroup_FlashDriver -#elif defined(kStatusGroup_FLASHIAP) -#define kStatusGroupGeneric kStatusGroup_Generic -#define kStatusGroupFlashDriver kStatusGroup_FLASH -#else -#define kStatusGroupGeneric 0 -#define kStatusGroupFlashDriver 1 -#endif - -/*! @brief Constructs a status code value from a group and a code number. */ -#if !defined(MAKE_STATUS) -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) -#endif - -/*! - * @brief Flash driver status codes. - */ -enum -{ - kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ - kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ - kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ - kStatus_FLASH_AlignmentError = - MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ - kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ - kStatus_FLASH_AccessError = - MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ - kStatus_FLASH_ProtectionViolation = MAKE_STATUS( - kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ - kStatus_FLASH_CommandFailure = - MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ - kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ - kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/ - kStatus_FLASH_RegionExecuteOnly = - MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/ - kStatus_FLASH_ExecuteInRamFunctionNotReady = - MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/ - - kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Flash API is not supported.*/ - kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< The flash property is read-only.*/ - kStatus_FLASH_InvalidPropertyValue = - MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< The flash property value is out of range.*/ - kStatus_FLASH_InvalidSpeculationOption = - MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< The option of flash prefetch speculation is invalid.*/ - kStatus_FLASH_EccError = MAKE_STATUS(kStatusGroupFlashDriver, - 0x10), /*!< A correctable or uncorrectable error during command execution. */ - kStatus_FLASH_CompareError = - MAKE_STATUS(kStatusGroupFlashDriver, 0x11), /*!< Destination and source memory contents do not match. */ - kStatus_FLASH_RegulationLoss = MAKE_STATUS(kStatusGroupFlashDriver, 0x12), /*!< A loss of regulation during read. */ - kStatus_FLASH_InvalidWaitStateCycles = - MAKE_STATUS(kStatusGroupFlashDriver, 0x13), /*!< The wait state cycle set to r/w mode is invalid. */ - - kStatus_FLASH_OutOfDateCfpaPage = - MAKE_STATUS(kStatusGroupFlashDriver, 0x20), /*!< CFPA page version is out of date. */ - kStatus_FLASH_BlankIfrPageData = MAKE_STATUS(kStatusGroupFlashDriver, 0x21), /*!< Blank page cannnot be read. */ - kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce = - MAKE_STATUS(kStatusGroupFlashDriver, 0x22), /*!< Encrypted flash subregions are not erased at once. */ - kStatus_FLASH_ProgramVerificationNotAllowed = MAKE_STATUS( - kStatusGroupFlashDriver, 0x23), /*!< Program verification is not allowed when the encryption is enabled. */ - kStatus_FLASH_HashCheckError = - MAKE_STATUS(kStatusGroupFlashDriver, 0x24), /*!< Hash check of page data is failed. */ - kStatus_FLASH_SealedFfrRegion = MAKE_STATUS(kStatusGroupFlashDriver, 0x25), /*!< The FFR region is sealed. */ - kStatus_FLASH_FfrRegionWriteBroken = MAKE_STATUS( - kStatusGroupFlashDriver, 0x26), /*!< The FFR Spec region is not allowed to be written discontinuously. */ - kStatus_FLASH_NmpaAccessNotAllowed = - MAKE_STATUS(kStatusGroupFlashDriver, 0x27), /*!< The NMPA region is not allowed to be read/written/erased. */ - kStatus_FLASH_CmpaCfgDirectEraseNotAllowed = - MAKE_STATUS(kStatusGroupFlashDriver, 0x28), /*!< The CMPA Cfg region is not allowed to be erased directly. */ - kStatus_FLASH_FfrBankIsLocked = MAKE_STATUS(kStatusGroupFlashDriver, 0x29), /*!< The FFR bank region is locked. */ - kStatus_FLASH_CfpaScratchPageInvalid = - MAKE_STATUS(kStatusGroupFlashDriver, 0x30), /*!< CFPA Scratch Page is invalid*/ - kStatus_FLASH_CfpaVersionRollbackDisallowed = - MAKE_STATUS(kStatusGroupFlashDriver, 0x31), /*!< CFPA version rollback is not allowed */ - kStatus_FLASH_ReadHidingAreaDisallowed = - MAKE_STATUS(kStatusGroupFlashDriver, 0x32), /*!< Flash hiding read is not allowed */ - kStatus_FLASH_ModifyProtectedAreaDisallowed = - MAKE_STATUS(kStatusGroupFlashDriver, 0x33), /*!< Flash firewall page locked erase and program are not allowed */ - kStatus_FLASH_CommandOperationInProgress = MAKE_STATUS( - kStatusGroupFlashDriver, 0x34), /*!< The flash state is busy, indicate that a flash command in progress. */ -}; -/*@}*/ - -/*! - * @name Flash API key - * @{ - */ -/*! @brief Constructs the four character code for the Flash driver API key. */ -#if !defined(FOUR_CHAR_CODE) -#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) -#endif - -/*! - * @brief Enumeration for Flash driver API keys. - * - * @note The resulting value is built with a byte order such that the string - * being readable in expected order when viewed in a hex editor, if the value - * is treated as a 32-bit little endian value. - */ -enum _flash_driver_api_keys -{ - kFLASH_ApiEraseKey = FOUR_CHAR_CODE('l', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ -}; -/*@}*/ - -/*! - * @brief Enumeration for various flash properties. - */ -typedef enum _flash_property_tag -{ - kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ - kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ - kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ - kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ - kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ - - kFLASH_PropertyPflashPageSize = 0x30U, /*!< Pflash page size property.*/ - kFLASH_PropertyPflashSystemFreq = 0x31U, /*!< System Frequency System Frequency.*/ - - kFLASH_PropertyFfrSectorSize = 0x40U, /*!< FFR sector size property.*/ - kFLASH_PropertyFfrTotalSize = 0x41U, /*!< FFR total size property.*/ - kFLASH_PropertyFfrBlockBaseAddr = 0x42U, /*!< FFR block base address property.*/ - kFLASH_PropertyFfrPageSize = 0x43U, /*!< FFR page size property.*/ -} flash_property_tag_t; - -/*! - * @brief Enumeration for flash max pages to erase. - */ -enum _flash_max_erase_page_value -{ - kFLASH_MaxPagesToErase = 100U /*!< The max value in pages to erase. */ -}; - -/*! - * @brief Enumeration for flash alignment property. - */ -enum _flash_alignment_property -{ - kFLASH_AlignementUnitVerifyErase = 4U, /*!< The alignment unit in bytes used for verify erase operation.*/ - kFLASH_AlignementUnitProgram = 512U, /*!< The alignment unit in bytes used for program operation.*/ - /*kFLASH_AlignementUnitVerifyProgram = 4U,*/ /*!< The alignment unit in bytes used for verify program operation.*/ - kFLASH_AlignementUnitSingleWordRead = 16U /*!< The alignment unit in bytes used for SingleWordRead command.*/ -}; - -/*! - * @brief Enumeration for flash read ecc option - */ -enum _flash_read_ecc_option -{ - kFLASH_ReadWithEccOn = 0U, /*! ECC is on */ - kFLASH_ReadWithEccOff = 1U /*! ECC is off */ -}; - -/*! - * @brief Enumeration for flash read margin option - */ -enum _flash_read_margin_option -{ - kFLASH_ReadMarginNormal = 0U, /*!< Normal read */ - kFLASH_ReadMarginVsProgram = 1U, /*!< Margin vs. program */ - kFLASH_ReadMarginVsErase = 2U, /*!< Margin vs. erase */ - kFLASH_ReadMarginIllegalBitCombination = 3U /*!< Illegal bit combination */ -}; - -/*! - * @brief Enumeration for flash read dmacc option - */ -enum _flash_read_dmacc_option -{ - kFLASH_ReadDmaccDisabled = 0U, /*!< Memory word */ - kFLASH_ReadDmaccEnabled = 1U /*!< DMACC word */ -}; - -/*! - * @brief Enumeration for flash ramp control option - */ -enum _flash_ramp_control_option -{ - kFLASH_RampControlDivisionFactorReserved = 0U, /*!< Reserved */ - kFLASH_RampControlDivisionFactor256 = 1U, /*!< clk48mhz / 256 = 187.5KHz */ - kFLASH_RampControlDivisionFactor128 = 2U, /*!< clk48mhz / 128 = 375KHz */ - kFLASH_RampControlDivisionFactor64 = 3U /*!< clk48mhz / 64 = 750KHz */ -}; - -/*! @brief Flash ECC log info. */ -typedef struct _flash_ecc_log -{ - uint32_t firstEccEventAddress; - uint32_t eccErrorCount; - uint32_t eccCorrectionCount; - uint32_t reserved; -} flash_ecc_log_t; - -/*! @brief Flash controller paramter config. */ -typedef struct _flash_mode_config -{ - uint32_t sysFreqInMHz; - /* ReadSingleWord parameter. */ - struct - { - uint8_t readWithEccOff : 1; - uint8_t readMarginLevel : 2; - uint8_t readDmaccWord : 1; - uint8_t reserved0 : 4; - uint8_t reserved1[3]; - } readSingleWord; - /* SetWriteMode parameter. */ - struct - { - uint8_t programRampControl; - uint8_t eraseRampControl; - uint8_t reserved[2]; - } setWriteMode; - /* SetReadMode parameter. */ - struct - { - uint16_t readInterfaceTimingTrim; - uint16_t readControllerTimingTrim; - uint8_t readWaitStates; - uint8_t reserved[3]; - } setReadMode; -} flash_mode_config_t; - -/*! @brief Flash controller paramter config. */ -typedef struct _flash_ffr_config -{ - uint32_t ffrBlockBase; - uint32_t ffrTotalSize; - uint32_t ffrPageSize; - uint32_t cfpaPageVersion; - uint32_t cfpaPageOffset; -} flash_ffr_config_t; - -/*! @brief Flash driver state information. - * - * An instance of this structure is allocated by the user of the flash driver and - * passed into each of the driver APIs. - */ -typedef struct -{ - uint32_t PFlashBlockBase; /*!< A base address of the first PFlash block */ - uint32_t PFlashTotalSize; /*!< The size of the combined PFlash block. */ - uint32_t PFlashBlockCount; /*!< A number of PFlash blocks. */ - uint32_t PFlashPageSize; /*!< The size in bytes of a page of PFlash. */ - uint32_t PFlashSectorSize; /*!< The size in bytes of a sector of PFlash. */ - flash_ffr_config_t ffrConfig; - flash_mode_config_t modeConfig; - uint32_t *nbootCtx; - bool useAhbRead; -} flash_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization - * @{ - */ - -/*! - * @brief Initializes the global flash properties structure members. - * - * This function checks and initializes the Flash module for the other Flash APIs. - * - * @param config Pointer to the storage for the driver runtime state. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. - */ -status_t FLASH_Init(flash_config_t *config); - -/*@}*/ - -/*! - * @name Erasing - * @{ - */ - -/*! - * @brief Erases the flash sectors encompassed by parameters passed into function. - * - * This function erases the appropriate number of flash sectors based on the - * desired start address and length. - * - * @param config The pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be erased. - * NOTE: The start address need to be 4 Bytes-aligned. - * - * @param lengthInBytes The length, given in bytes need be 4 Bytes-aligned. - * - * @param key The value used to validate all flash erase APIs. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_AddressError The address is out of range. - * @retval #kStatus_FLASH_EraseKeyError The API erase key is invalid. - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. - */ -status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - -/*! - * @brief Non-blocking Erases the flash sectors encompassed by parameters passed into function. - * - * This is a non-blocking function, which returns right away. - * This function erases the appropriate number of flash sectors based on the desired start - * address and length, and get the command execute status from the "FLASH_GetCommandState". - * - * @param config The pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be erased. - * NOTE: The start address need be 4 Bytes-aligned. - * - * @param lengthInBytes The length, given in bytes need be 4 Bytes-aligned. - * - * @param key The value used to validate all flash erase APIs. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_AddressError The address is out of range. - * @retval #kStatus_FLASH_EraseKeyError The API erase key is invalid. - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed - */ -status_t FLASH_EraseNonBlocking(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - -/*@}*/ - -/*! - * @name Programming - * @{ - */ - -/*! - * @brief Programs flash with data at locations passed in through parameters. - * - * This function programs the flash memory with the desired data for a given - * flash area as determined by the start address and the length. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be programmed. Must be - * word-aligned. - * @param src A pointer to the source buffer of data that is to be programmed - * into the flash. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be programmed. Must be word-aligned. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); - -/*! - * @name Reading - * @{ - */ - -/*! - * @brief Reads flash at locations passed in through parameters. - * - * This function read the flash memory from a given flash area as determined - * by the start address and the length. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be read. - * @param dest A pointer to the dest buffer of data that is to be read - * from the flash. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be read. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); - -/*@}*/ - -/*! - * @name Verification - * @{ - */ - -/*! - * @brief Verifies an erasure of the desired flash area at a specified margin level. - * - * This function checks the appropriate number of flash sectors based on - * the desired start address and length to check whether the flash is erased - * to the specified read margin level. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be verified. - * The start address does not need to be sector-aligned but must be word-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be verified. Must be word-aligned. - * @param margin Read margin choice. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); - -/*! - * @brief Verifies programming of the desired flash area at a specified margin level. - * - * This function verifies the data programed in the flash memory using the - * Flash Program Check Command and compares it to the expected data for a given - * flash area as determined by the start address and length. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be verified. Must be word-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be verified. Must be word-aligned. - * @param expectedData A pointer to the expected data that is to be - * verified against. - * @param margin Read margin choice. - * @param failedAddress A pointer to the returned failing address. - * @param failedData A pointer to the returned failing data. Some derivatives do - * not include failed data as part of the FCCOBx registers. In this - * case, zeros are returned upon failure. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_VerifyProgram(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - -/*@}*/ - -/*! - * @name Properties - * @{ - */ - -/*! - * @brief Returns the desired flash property. - * - * @param config A pointer to the storage for the driver runtime state. - * @param whichProperty The desired property from the list of properties in - * enum flash_property_tag_t - * @param value A pointer to the value returned for the desired flash property. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_UnknownProperty An unknown property tag. - */ -status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); - -/*@}*/ - -/*! - * @name flash status - * @{ - */ -#if defined(FSL_FEATURE_SYSCON_HAS_FLASH_HIDING) && (FSL_FEATURE_SYSCON_HAS_FLASH_HIDING == 1) -/*! - * @brief Validates the given address range is loaded in the flash hiding region. - * - * @param config A pointer to the storage for the driver runtime state. - * @param startAddress The start address of the desired flash memory to be verified. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be verified. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed. - */ -status_t FLASH_IsFlashAreaReadable(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); -#endif - -#if defined(FSL_FEATURE_SYSCON_HAS_CDPA) && (FSL_FEATURE_SYSCON_HAS_CDPA == 1) -/*! - * @brief Validates the given address range is loaded in the Flash firewall page locked region. - * - * @param config A pointer to the storage for the driver runtime state. - * @param startAddress The start address of the desired flash memory to be verified. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be verified. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash hiding read is not allowed. - */ -status_t FLASH_IsFlashAreaModifiable(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); -#endif - -/*@}*/ - -/*! - * @name command status - * @{ - */ -/*! - * @brief Get flash command execute status. - * - * This function is used to obtain the status after the command "FLASH_EraseNonBlocking" is executed. - * - * @param config A pointer to the storage for the driver runtime state. - * - * @retval #kStatus_FLASH_CommandOperationInProgress Indicate that a flash command in progress. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. - * @retval #kStatus_FLASH_Success API was executed successfully. - */ -status_t FLASH_GetCommandState(flash_config_t *config); - -/*@}*/ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FLASH_FLASH_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/fsl_flash_ffr.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/fsl_flash_ffr.h deleted file mode 100644 index 67d4296d70d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/fsl_flash_ffr.h +++ /dev/null @@ -1,568 +0,0 @@ -/* - * Copyright 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _FSL_FLASH_FFR_H_ -#define _FSL_FLASH_FFR_H_ - -#include "fsl_flash.h" - -/*! - * @addtogroup flash_ffr_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Alignment(down) utility. */ -#if !defined(ALIGN_DOWN) -#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) -#endif - -/*! @brief Alignment(up) utility. */ -#if !defined(ALIGN_UP) -#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) -#endif - -#define FLASH_FFR_MAX_PAGE_SIZE (512U) -#define FLASH_FFR_HASH_DIGEST_SIZE (32U) -#define FLASH_FFR_IV_CODE_SIZE (52U) - -enum flash_ffr_page_offset -{ - kFfrPageOffset_CFPA = 0U, /*!< Customer In-Field programmed area*/ - kFfrPageOffset_CFPA_Scratch = 0U, /*!< CFPA Scratch page */ - kFfrPageOffset_CFPA_CfgPing = 1U, /*!< CFPA Configuration area (Ping page)*/ - kFfrPageOffset_CFPA_CfgPong = 2U, /*!< Same as CFPA page (Pong page)*/ - -#if defined(LPC55S36_SERIES) - kFfrPageOffset_CMPA = 3U, /*!< Customer Manufacturing programmed area*/ - kFfrPageOffset_CMPA_Cfg = 3U, /*!< CMPA Configuration area (Part of CMPA)*/ - kFfrPageOffset_CMPA_Csr_Key = 4U, /*!< Customer Key Store Area (Part of CMPA)*/ - - kFfrPageOffset_NMPA_Key = 5U, /*!< Key Store area (Part of NMPA)*/ - kFfrPageOffset_NMPA = 5U, /*!< NXP Manufacturing programmed area*/ - kFfrPageOffset_NMPA_Romcp = 8U, /*!< ROM patch area (Part of NMPA)*/ - kFfrPageOffset_NMPA_Repair = 10U, /*!< Repair area (Part of NMPA)*/ - kFfrPageOffset_NMPA_Cfg = 16U, /*!< NMPA configuration area (Part of NMPA)*/ - kFfrPageOffset_NMPA_End = 17U, /*!< Reserved (Part of NMPA)*/ -#else - kFfrPageOffset_CMPA = 3U, /*!< Customer Manufacturing programmed area*/ - kFfrPageOffset_CMPA_Cfg = 3U, /*!< CMPA Configuration area (Part of CMPA)*/ - kFfrPageOffset_CMPA_Key = 4U, /*!< Key Store area (Part of CMPA)*/ - - kFfrPageOffset_NMPA = 7U, /*!< NXP Manufacturing programmed area*/ - kFfrPageOffset_NMPA_Romcp = 7U, /*!< ROM patch area (Part of NMPA)*/ - kFfrPageOffset_NMPA_Repair = 9U, /*!< Repair area (Part of NMPA)*/ - kFfrPageOffset_NMPA_Cfg = 15U, /*!< NMPA configuration area (Part of NMPA)*/ - kFfrPageOffset_NMPA_End = 16U, /*!< Reserved (Part of NMPA)*/ -#endif - -}; - -enum flash_ffr_page_num -{ - kFfrPageNum_CFPA = 3U, /*!< Customer In-Field programmed area*/ -#if defined(LPC55S36_SERIES) - kFfrPageNum_CMPA = 2U, /*!< Customer Manufacturing programmed area*/ -#else - kFfrPageNum_CMPA = 4U, /*!< Customer Manufacturing programmed area*/ -#endif - kFfrPageNum_NMPA = 13U, /*!< NXP Manufacturing programmed area*/ - - kFfrPageNum_CMPA_Cfg = 1U, - kFfrPageNum_NMPA_Romcp = 2U, - - kFfrPageNum_SpecArea = kFfrPageNum_CFPA + kFfrPageNum_CMPA, - kFfrPageNum_Total = (kFfrPageNum_CFPA + kFfrPageNum_CMPA + kFfrPageNum_NMPA), -}; - -enum flash_ffr_block_size -{ - kFfrBlockSize_Key = 52U, -#if defined(LPC55S36_SERIES) - kFfrBlockSize_ActivationCode = 996U, -#else - kFfrBlockSize_ActivationCode = 1192U, -#endif -}; - -enum cfpa_cfg_cmpa_prog_status -{ - kFfrCmpaProgStatus_Idle = 0x0U, - kFfrCmpaProgStatus_InProgress = 0x5CC55AA5U, -}; - -typedef enum -{ - kFfrCmpaProgProcess_Pre = 0x0U, - kFfrCmpaProgProcess_Post = 0xFFFFFFFFU, -} cmpa_prog_process_t; - -typedef struct -{ - uint32_t header; /*!< [0x000-0x003] */ - uint32_t version; /*!< [0x004-0x007] */ - uint32_t secureFwVersion; /*!< [0x008-0x00b] */ - uint32_t nsFwVersion; /*!< [0x00c-0x00f] */ - uint32_t imageKeyRevoke; /*!< [0x010-0x013] */ - uint32_t ivPrince[3]; /*!< [0x014-0x01f] */ - uint32_t ivIped[4]; /*!< [0x020-0x02f] */ - uint32_t custCtr[8]; /*!< [0x030-0x03f] */ - uint32_t rotkhRevoke; /*!< [0x018-0x01b] */ - uint32_t vendorUsage; /*!< [0x050-0x053] */ - uint32_t dcfgNsPin; /*!< [0x058-0x05b] */ - uint32_t dcfgNsDflt; /*!< [0x05c-0x05f] */ - uint32_t enableFaMode; /*!< [0x060-0x063] */ - uint32_t cmpaProgInProgress; /*!< [0x064-0x067] */ - uint32_t imageCmacUpdateEn; /*!< [0x068-0x06b] */ - uint32_t cfpaVersion; /*!< [0x06c-0x06f] */ - uint32_t img0Cmac[4]; /*!< [0x070-0x07f] */ - uint32_t img1Cmac[4]; /*!< [0x080-0x08f] */ - uint8_t reserved2[348]; /*!< [0x090-0x1eb] */ - uint32_t cfpaCrc; /*!< [0x1eb-0x1ef] */ - uint32_t cfpaCmac[4]; /*!< [0x1f0-0x1ff] */ -} cfpa_cfg_info_t; - -#define FFR_BOOTCFG_USBSPEED_SHIFT (9U) -#define FFR_BOOTCFG_USBSPEED_MASK (0x3u << FFR_BOOTCFG_USBSPEED_SHIFT) -#define FFR_BOOTCFG_USBSPEED_NMPASEL0 (0x0U) -#define FFR_BOOTCFG_USBSPEED_FS (0x1U) -#define FFR_BOOTCFG_USBSPEED_HS (0x2U) -#define FFR_BOOTCFG_USBSPEED_NMPASEL3 (0x3U) - -#define FFR_BOOTCFG_BOOTSPEED_MASK (0x18U) -#define FFR_BOOTCFG_BOOTSPEED_SHIFT (7U) -#define FFR_BOOTCFG_BOOTSPEED_NMPASEL (0x0U) -#define FFR_BOOTCFG_BOOTSPEED_48MHZ (0x1U) -#define FFR_BOOTCFG_BOOTSPEED_96MHZ (0x2U) - -#define FFR_USBID_VENDORID_MASK (0xFFFFU) -#define FFR_USBID_VENDORID_SHIFT (0U) -#define FFR_USBID_PRODUCTID_MASK (0xFFFF0000U) -#define FFR_USBID_PRODUCTID_SHIFT (16U) - -#define FFR_IMAGE0_CMAC_UPDATE_MASK (0x1U) -#define FFR_IMAGE1_CMAC_UPDATE_MASK (0x2U) - -typedef struct -{ - uint32_t bootCfg; /*!< [0x000-0x003] */ - uint32_t spiFlashCanCfg; /*!< [0x004-0x007] */ - struct - { - uint16_t vid; - uint16_t pid; - } usbId; /*!< [0x008-0x00b] */ - uint32_t sdioCfg; /*!< [0x00c-0x00f] */ - uint32_t dcfgPin; /*!< [0x010-0x013] */ - uint32_t dcfgDflt; /*!< [0x014-0x017] */ - uint32_t dapVendorUsage; /*!< [0x018-0x01b] */ - uint32_t secureBootCfg; /*!< [0x01c-0x01f] */ - uint32_t princeBaseAddr; /*!< [0x020-0x023] */ - uint32_t princeSr[3]; /*!< [0x024-0x02f] */ - uint32_t xtal32kCapBankTrim; /*!< [0x030-0x033] */ - uint32_t xtal16mCapBankTrim; /*!< [0x034-0x037] */ - uint32_t flashRemapSize; /*!< [0x038-0x03b] */ - uint32_t flashRemapOffset; /*!< [0x03c-0x03f] */ - uint32_t princeXom[3]; /*!< [0x040-0x04b] */ - uint32_t rokthUsage; /*!< [0x04c-0x04f] */ - uint32_t rotkh[12]; /*!< [0x050-0x07f] */ - uint32_t flexspiCfg0; /*!< [0x080-0x083] */ - uint32_t flexspiCfg1; /*!< [0x084-0x087] */ - uint8_t reserved1[8]; /*!< [0x088-0x08f] */ - struct - { - uint32_t ipedStartAddr; /*!< [0x090-0x093] */ - uint32_t ipedEndAddr; /*!< [0x094-0x097] */ - } ipedRegions[4]; - - uint8_t reserved2[320]; /*!< [0x0b0-0x1ef] */ - uint32_t cmpaCmac[4]; /*!< [0x1f0-0x1ff] */ -} cmpa_cfg_info_t; - -typedef struct -{ - uint32_t header; - uint8_t reserved[4]; -} cmpa_key_store_header_t; - -#define FFR_SYSTEM_SPEED_CODE_MASK (0x3U) -#define FFR_SYSTEM_SPEED_CODE_SHIFT (0U) -#define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ (0x0U) -#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_24MHZ (0x1U) -#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_48MHZ (0x2U) -#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_96MHZ (0x3U) - -#define FFR_USBCFG_USBSPEED_HS (0x0U) -#define FFR_USBCFG_USBSPEED_FS (0x1U) -#define FFR_USBCFG_USBSPEED_NO (0x2U) - -#define FFR_MCAN_BAUDRATE_MASK (0xF0000U) -#define FFR_MCAN_BAUDRATE_SHIFT (16U) - -#define FFR_PERIPHERALCFG_PERI_MASK (0x7FFFFFFFU) -#define FFR_PERIPHERALCFG_PERI_SHIFT (0U) -#define FFR_PERIPHERALCFG_COREEN_MASK (0x10000000U) -#define FFR_PERIPHERALCFG_COREEN_SHIFT (31U) - -#define FFR_PUF_SRAM_CONFIG_MASK (0x3FFFF07) -#define FFR_PUF_SRAM_CONFIG_MASK_SHIFT (0U) -#define FFR_PUF_SRAM_VALID_MASK (0x1U) -#define FFR_PUF_SRAM_VALID_SHIFT (0U) -#define FFR_PUF_SRAM_MODE_MASK (0x2U) -#define FFR_PUF_SRAM_MODE_SHIFT (1U) -#define FFR_PUF_SRAM_CKGATING_MASK (0x4U) -#define FFR_PUF_SRAM_CKGATING_SHIFT (2U) -#define FFR_PUF_SRAM_SMB_MASK (0x300U) -#define FFR_PUF_SRAM_SMB_SHIFT (8U) -#define FFR_PUF_SRAM_RM_MASK (0x1C00U) -#define FFR_PUF_SRAM_RM_SHIFT (10U) -#define FFR_PUF_SRAM_WM_MASK (0xE000U) -#define FFR_PUF_SRAM_WM_SHIFT (13U) -#define FFR_PUF_SRAM_WRME_MASK (0x10000U) -#define FFR_PUF_SRAM_WRME_SHIFT (16U) -#define FFR_PUF_SRAM_RAEN_MASK (0x20000U) -#define FFR_PUF_SRAM_RAEN_SHIFT (17U) -#define FFR_PUF_SRAM_RAM_MASK (0x3C0000U) -#define FFR_PUF_SRAM_RAM_SHIFT (18U) -#define FFR_PUF_SRAM_WAEN_MASK (0x400000U) -#define FFR_PUF_SRAM_WAEN_SHIFT (22U) -#define FFR_PUF_SRAM_WAM_MASK (0x1800000U) -#define FFR_PUF_SRAM_WAM_SHIFT (23U) -#define FFR_PUF_SRAM_STBP_MASK (0x2000000U) -#define FFR_PUF_SRAM_STBP_SHIFT (25U) - -typedef struct -{ - uint32_t fro32kCfg; /*!< [0x000-0x003] */ - uint32_t puf_cfg; /*!< [0x004-0x007] */ - uint32_t bod; /*!< [0x008-0x00b] */ - uint32_t trim; /*!< [0x00c-0x00f] */ - uint32_t deviceID; /*!< [0x010-0x03f] */ - uint32_t peripheralCfg; /*!< [0x014-0x017] */ - uint32_t dcdPowerProFileLOW[2]; /*!< [0x018-0x01f] */ - uint32_t deviceType; /*!< [0x020-0x023] */ - uint32_t ldo_ao; /*!< [0x024-0x027] */ - uint32_t gdetDelayCfg; /*!< [0x028-0x02b] */ - uint32_t gdetMargin; /*!< [0x02c-0x02f] */ - uint32_t gdetTrim1; /*!< [0x030-0x033] */ - uint32_t gdetEanble1; /*!< [0x034-0x037] */ - uint32_t gdetCtrl1; /*!< [0x038-0x03b] */ - uint32_t gdetUpdateTimer; /*!< [0x03c-0x03f] */ - uint32_t GpoDataChecksum[4]; /*!< [0x040-0x04f] */ - uint32_t finalTestBatchId[4]; /*!< [0x050-0x05f] */ - uint32_t ecidBackup[4]; /*!< [0x060-0x06f] */ - uint32_t uuid[4]; /*!< [0x070-0x07f] */ - uint32_t reserved1[7]; /*!< [0x080-0x09b] */ - struct - { - uint8_t xo32mReadyTimeoutInMs; - uint8_t usbSpeed; - uint8_t reserved[2]; - } usbCfg; /*!< [0x09c-0x09f] */ - uint32_t reserved2[80]; /*!< [0x0a0-0x1df] */ - uint8_t cmac[16]; /*!< [0x1e0-0x1ef] */ - uint32_t pageChecksum[4]; /*!< [0x1f0-0x1ff] */ -} nmpa_cfg_info_t; - -typedef struct -{ - uint8_t reserved[1][FLASH_FFR_MAX_PAGE_SIZE]; -} ffr_key_store_t; - -typedef enum -{ - kFFR_KeyTypeSbkek = 0x00U, - kFFR_KeyTypeUser = 0x01U, - kFFR_KeyTypeUds = 0x02U, - kFFR_KeyTypePrinceRegion0 = 0x03U, - kFFR_KeyTypePrinceRegion1 = 0x04U, - kFFR_KeyTypePrinceRegion2 = 0x05U, -} ffr_key_type_t; - -typedef enum -{ - kFFR_BankTypeBank0_NMPA = 0x00U, - kFFR_BankTypeBank1_CMPA = 0x01U, - kFFR_BankTypeBank2_CFPA = 0x02U -} ffr_bank_type_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name FFR APIs - * @{ - */ - -/*! - * @brief Initializes the global FFR properties structure members. - * - * @param config A pointer to the storage for the driver runtime state. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - */ -status_t FFR_Init(flash_config_t *config); - -/*! - * @brief Enable firewall for all flash banks. - * - * CFPA, CMPA, and NMPA flash areas region will be locked, After this function executed; - * Unless the board is reset again. - * - * @param config A pointer to the storage for the driver runtime state. - * - * @retval #kStatus_FLASH_Success An invalid argument is provided. - */ -status_t FFR_Lock(flash_config_t *config); - -/*! - * @brief Initialize the Security Library for FFR driver. - * - * @param config A pointer to the storage for the driver runtime state. - * @param context A pointer to the storage for the nboot data. - * - * @retval #kStatus_FLASH_Success An invalid argument is provided. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - */ -status_t FFR_SecLibInit(flash_config_t *config, uint32_t *context); - -status_t FFR_GetCustKeystoreData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - -/*! - * @brief APIs to access CFPA pages - * - * This routine will erase CFPA and program the CFPA page with passed data. - * - * @param config A pointer to the storage for the driver runtime state. - * - * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CFPA. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_FfrBankIsLocked The FFR bank region is locked. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed - * @retval #kStatus_FLASH_CfpaScratchPageInvalid CFPA Scratch Page is invalid - * @retval #kStatus_FLASH_CfpaVersionRollbackDisallowed CFPA version rollback is not allowed - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline - * @retval #kStatus_FLASH_EraseKeyError API erase key is invalid. - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed - * @retval #kStatus_FLASH_FfrBankIsLocked The CFPA was locked. - * @retval #kStatus_FLASH_OutOfDateCfpaPage It is not newest CFPA page. - * @retval #kStatus_FLASH_CommandFailure access error. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. - */ -status_t FFR_CustomerPagesInit(flash_config_t *config); - -/*! - * @brief APIs to access CFPA pages - * - * This routine will erase CFPA and program the CFPA page with passed data. - * - * @param config A pointer to the storage for the driver runtime state. - * @param page_data A pointer to the source buffer of data that is to be programmed - * into the CFPA. - * @param valid_len The length, given in bytes, to be programmed. - * - * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CFPA. - * @retval #kStatus_FLASH_SizeError Error size - * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_FfrBankIsLocked The CFPA was locked. - * @retval #kStatus_FLASH_OutOfDateCfpaPage It is not newest CFPA page. - * @retval #kStatus_FLASH_CommandFailure access error. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. - */ -status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); - -/*! - * @brief APIs to access CFPA pages - * - * Generic read function, used by customer to read data stored in 'Customer In-field Page'. - * - * @param config A pointer to the storage for the driver runtime state. - * @param pData A pointer to the dest buffer of data that is to be read from 'Customer In-field Page'. - * @param offset An offset from the 'Customer In-field Page' start address. - * @param len The length, given in bytes, to be read. - * - * @retval #kStatus_FLASH_Success Get data from 'Customer In-field Page'. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed - * @retval #kStatus_FLASH_CommandFailure access error. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. - */ -status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - -/*! - * @brief APIs to access CMPA pages - * - * This routine will erase "customer factory page" and program the page with passed data. - * If 'seal_part' parameter is TRUE then the routine will compute SHA256 hash of - * the page contents and then programs the pages. - * 1.During development customer code uses this API with 'seal_part' set to FALSE. - * 2.During manufacturing this parameter should be set to TRUE to seal the part - * from further modifications - * 3.This routine checks if the page is sealed or not. A page is said to be sealed if - * the SHA256 value in the page has non-zero value. On boot ROM locks the firewall for - * the region if hash is programmed anyways. So, write/erase commands will fail eventually. - * - * @param config A pointer to the storage for the driver runtime state. - * @param page_data A pointer to the source buffer of data that is to be programmed - * into the "customer factory page". - * @param seal_part Set fasle for During development customer code. - * - * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CMPA. - * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. - * @retval #kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_EraseKeyError API erase key is invalid. - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed - * @retval #kStatus_Fail Generic status for Fail. - * @retval #kStatus_FLASH_CommandFailure access error. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. - */ -status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part); - -/*! - * @brief APIs to access CMPA page - * - * Read data stored in 'Customer Factory CFG Page'. - * - * @param config A pointer to the storage for the driver runtime state. - * @param pData A pointer to the dest buffer of data that is to be read - * from the Customer Factory CFG Page. - * @param offset Address offset relative to the CMPA area. - * @param len The length, given in bytes to be read. - * - * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. - * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @retval #kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_CommandFailure access error. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. - * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed - */ -status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - -/*! - * @brief The API is used for getting the customer key store data from the customer key store region(0x3e400 ¨C 0x3e600), - * and the API should be called after the FLASH_Init and FFR_Init. - * - * @param config A pointer to the storage for the driver runtime state. - * @param pData A pointer to the dest buffer of data that is to be read - * from the Customer Factory CFG Page. - * @param offset Address offset relative to the CMPA area. - * @param len The length, given in bytes to be read. - * - * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. - * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. - * @retval #kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_AddressError Address is out of range - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed - * @retval #kStatus_FLASH_CommandFailure access error. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. - */ -status_t FFR_GetCustKeystoreData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - -/*! - * @brief This routine writes the 3 pages allocated for Key store data. - * - * @param config A pointer to the storage for the driver runtime state. - * @param pKeyStore A pointer to the source buffer of data that is to be programmed - * into the "Key store". - * - * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. - * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_CommandFailure access error. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. - * @retval #kStatus_FLASH_SealedFfrRegion The FFR region is sealed. - * @retval #kStatus_FLASH_FfrBankIsLocked The FFR bank region is locked. - * @retval #kStatus_FLASH_AddressError Address is out of range - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed - */ -status_t FFR_CustKeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore); - -/*! - * @brief APIs to access CMPA page - * - * 1.SW should use this API routine to get the UUID of the chip. - * 2.Calling routine should pass a pointer to buffer which can hold 128-bit value. - * - * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. - * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed - * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported - * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. - */ -status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid); - -/*! - * @brief This routine writes the 3 pages allocated for Key store data, - * - * 1.Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state. - * 2.Optional routines to set individual data members (activation code, key codes etc) to construct - * the key store structure in RAM before committing it to IFR/FFR. - * - * @param config A pointer to the storage for the driver runtime state. - * @param pKeyStore A Pointer to the 3 pages allocated for Key store data. - * that will be written to 'customer factory page'. - * - * @retval #kStatus_FLASH_Success The key were programed successfully into FFR. - * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. - * @retval #kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_CommandFailure access error. - * @retval #kStatus_FLASH_SealedFfrRegion The FFR region is sealed. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range - * @retval #kStatus_FLASH_EraseKeyError API erase key is invalid. - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported - * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. - */ -status_t FFR_CustKeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore); - -/*@}*/ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /*! _FSL_FLASH_FFR_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/fsl_flexspi_nor_flash.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/fsl_flexspi_nor_flash.h deleted file mode 100644 index e5fc3740cb5..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/fsl_flexspi_nor_flash.h +++ /dev/null @@ -1,709 +0,0 @@ -/* - * Copyright 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _FSL_FLEXSPI_NOR_FLASH_H__ -#define _FSL_FLEXSPI_NOR_FLASH_H__ - -#include "fsl_common.h" -/*! - * @addtogroup flexspi_nor_flash_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 0 /*!< FLEXSPI Feature related definitions */ - -#define FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ - (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ - FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - -#define CMD_SDR 0x01U -#define CMD_DDR 0x21U -#define RADDR_SDR 0x02U -#define RADDR_DDR 0x22U -#define CADDR_SDR 0x03U -#define CADDR_DDR 0x23U -#define MODE1_SDR 0x04U -#define MODE1_DDR 0x24U -#define MODE2_SDR 0x05U -#define MODE2_DDR 0x25U -#define MODE4_SDR 0x06U -#define MODE4_DDR 0x26U -#define MODE8_SDR 0x07U -#define MODE8_DDR 0x27U -#define WRITE_SDR 0x08U -#define WRITE_DDR 0x28U -#define READ_SDR 0x09U -#define READ_DDR 0x29U -#define LEARN_SDR 0x0AU -#define LEARN_DDR 0x2AU -#define DATSZ_SDR 0x0BU -#define DATSZ_DDR 0x2BU -#define DUMMY_SDR 0x0CU -#define DUMMY_DDR 0x2CU -#define DUMMY_RWDS_SDR 0x0DU -#define DUMMY_RWDS_DDR 0x2DU -#define JMP_ON_CS 0x1FU -#define FLEXSPI_STOP 0U - -#define FLEXSPI_1PAD 0U -#define FLEXSPI_2PAD 1U -#define FLEXSPI_4PAD 2U -#define FLEXSPI_8PAD 3U - -/*! - * @brief NOR LUT sequence index used for default LUT assignment - * NOTE: - * The will take effect if the lut sequences are not customized. - */ -#define NOR_CMD_LUT_SEQ_IDX_READ 0U /*!< READ LUT sequence id in lookupTable stored in config block */ -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1U /*!< Read Status LUT sequence id in lookupTable stored in config block */ -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ - 2U /*!< Read status DPI/QPI/OPI sequence id in lookupTable stored in config block */ -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 3U /*!< Write Enable sequence id in lookupTable stored in config block */ -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ - 4U /*!< Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block */ -#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5U /*!< Erase Sector sequence id in lookupTable stored in config block */ -#define NOR_CMD_LUT_SEQ_IDX_READID 7U -#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8U /*!< Erase Block sequence id in lookupTable stored in config block */ -#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 9U /*!< Program sequence id in lookupTable stored in config block */ -#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11U /*!< Chip Erase sequence in lookupTable id stored in config block */ -#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13U /*!< Read SFDP sequence in lookupTable id stored in config block */ -#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ - 14U /*!< Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block */ -#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ - 15U /*!< Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk */ - -/*! @brief FLEXSPI status group numbers. */ -enum _flexspi_status_groups -{ - kStatusROMGroup_FLEXSPI = 60, /*!< Group number for ROM FLEXSPI status codes. */ - kStatusROMGroup_FLEXSPINOR = 201, /*!< ROM FLEXSPI NOR status group number.*/ -}; - -/*! @brief FLEXSPI NOR status */ -enum _flexspi_nor_status -{ - kStatus_FLEXSPINOR_ProgramFail = - MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 0), /*!< Status for Page programming failure */ - kStatus_FLEXSPINOR_EraseSectorFail = - MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 1), /*!< Status for Sector Erase failure */ - kStatus_FLEXSPINOR_EraseAllFail = MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 2), /*!< Status for Chip Erase failure */ - kStatus_FLEXSPINOR_WaitTimeout = MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 3), /*!< Status for timeout */ - kStatus_FlexSPINOR_NotSupported = MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 4), // Status for PageSize overflow */ - kStatus_FlexSPINOR_WriteAlignmentError = - MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 5), /*!< Status for Alignement error */ - kStatus_FlexSPINOR_CommandFailure = - MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 6), /*!< Status for Erase/Program Verify Error */ - kStatus_FlexSPINOR_SFDP_NotFound = MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 7), /*!< Status for SFDP read failure */ - kStatus_FLEXSPINOR_Unsupported_SFDP_Version = - MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 8), /*!< Status for Unrecognized SFDP version */ - kStatus_FLEXSPINOR_Flash_NotFound = - MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 9), /*!< Status for Flash detection failure */ - kStatus_FLEXSPINOR_DTRRead_DummyProbeFailed = - MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 10), /*!< Status for DDR Read dummy probe failure */ - - kStatus_FLEXSPI_SequenceExecutionTimeout = - MAKE_STATUS(kStatusROMGroup_FLEXSPI, 0), /*!< Status for Sequence Execution timeout */ - kStatus_FLEXSPI_InvalidSequence = MAKE_STATUS(kStatusROMGroup_FLEXSPI, 1), /*!< Status for Invalid Sequence */ - kStatus_FLEXSPI_DeviceTimeout = MAKE_STATUS(kStatusROMGroup_FLEXSPI, 2), /*!< Status for Device timeout */ - -}; - -/*! @brief Configure the device_type of "serial_nor_config_option_t" structure */ -enum -{ - kSerialNorCfgOption_Tag = 0x0cU, - kSerialNorCfgOption_DeviceType_ReadSFDP_SDR = 0U, - kSerialNorCfgOption_DeviceType_ReadSFDP_DDR = 1U, - kSerialNorCfgOption_DeviceType_HyperFLASH1V8 = 2U, - kSerialNorCfgOption_DeviceType_HyperFLASH3V0 = 3U, - kSerialNorCfgOption_DeviceType_MacronixOctalDDR = 4U, - kSerialNorCfgOption_DeviceType_MacronixOctalSDR = 5U, - kSerialNorCfgOption_DeviceType_MicronOctalDDR = 6U, - kSerialNorCfgOption_DeviceType_MicronOctalSDR = 7U, - kSerialNorCfgOption_DeviceType_AdestoOctalDDR = 8U, - kSerialNorCfgOption_DeviceType_AdestoOctalSDR = 9U, -}; - -/*! @brief Configure the quad_mode_setting of "serial_nor_config_option_t" structure */ -enum -{ - kSerialNorQuadMode_NotConfig = 0U, - kSerialNorQuadMode_StatusReg1_Bit6 = 1U, - kSerialNorQuadMode_StatusReg2_Bit1 = 2U, - kSerialNorQuadMode_StatusReg2_Bit7 = 3U, - kSerialNorQuadMode_StatusReg2_Bit1_0x31 = 4U, -}; - -/*! @brief FLEXSPI NOR Octal mode */ -enum -{ - kSerialNorOctaldMode_NoOctalEnableBit = 0U, - kSerialNorOctaldMode_HasOctalEnableBit = 1U, -}; - -/*! @brief miscellaneous mode */ -enum -{ - kSerialNorEnhanceMode_Disabled = 0U, - kSerialNorEnhanceMode_0_4_4_Mode = 1U, - kSerialNorEnhanceMode_0_8_8_Mode = 2U, - kSerialNorEnhanceMode_DataOrderSwapped = 3U, - kSerialNorEnhanceMode_2ndPinMux = 4U, - kSerialNorEnhanceMode_InternalLoopback = 5U, - kSerialNorEnhanceMode_SpiMode = 6U, - kSerialNorEnhanceMode_ExtDqs = 8U, -}; - -/*! @brief FLEXSPI NOR reset logic options */ -enum -{ - kFlashResetLogic_Disabled = 0U, - kFlashResetLogic_ResetPin = 1U, - kFlashResetLogic_JedecHwReset = 2U, -}; - -/*! @brief Configure the flash_connection of "serial_nor_config_option_t" structure */ -enum -{ - kSerialNorConnection_SinglePortA, - kSerialNorConnection_Parallel, - kSerialNorConnection_SinglePortB, - kSerialNorConnection_BothPorts -}; - -/*! @brief - * FLEXSPI ROOT clock soruce related definitions - */ -enum -{ - kFLEXSPIClkSrc_MainClk = 0U, - kFLEXSPIClkSrc_Pll0 = 1U, - kFLEXSPIClkSrc_FroHf = 3U, - kFLEXSPIClkSrc_Pll1 = 5U, -}; - -/*! @brief Restore sequence options - * Configure the restore_sequence of "flash_run_context_t" structure - */ -enum -{ - kRestoreSequence_None = 0U, - kRestoreSequence_HW_Reset = 1U, - kRestoreSequence_QPI_4_0xFFs = 2U, - kRestoreSequence_QPI_Mode_0x00 = 3U, - kRestoreSequence_8QPI_FF = 4U, - kRestoreSequence_Send_F0 = 5U, - kRestoreSequence_Send_66_99 = 6U, - kRestoreSequence_Send_6699_9966 = 7U, - kRestoreSequence_Send_06_FF = 8U, /*!< Adesto EcoXIP */ - kRestoreSequence_QPI_5_0xFFs = 9U, - kRestoreSequence_Send_QPI_8_0xFFs = 10U, - kRestoreSequence_Wakeup_0xAB = 11U, - kRestoreSequence_Wakeup_0xAB_54 = 12U, -}; - -/*! @brief Port mode options*/ -enum -{ - kFlashInstMode_ExtendedSpi = 0x00U, - kFlashInstMode_0_4_4_SDR = 0x01U, - kFlashInstMode_0_4_4_DDR = 0x02U, - kFlashInstMode_DPI_SDR = 0x21U, - kFlashInstMode_DPI_DDR = 0x22U, - kFlashInstMode_QPI_SDR = 0x41U, - kFlashInstMode_QPI_DDR = 0x42U, - kFlashInstMode_OPI_SDR = 0x81U, - kFlashInstMode_OPI_DDR = 0x82U, -}; - -/*! - * @name Support for init FLEXSPI NOR configuration - * @{ - */ -/*! @brief Flash Pad Definitions */ -enum -{ - kSerialFlash_1Pad = 1U, - kSerialFlash_2Pads = 2U, - kSerialFlash_4Pads = 4U, - kSerialFlash_8Pads = 8U, -}; - -/*! @brief FLEXSPI clock configuration type */ -enum -{ - kFLEXSPIClk_SDR, /*!< Clock configure for SDR mode */ - kFLEXSPIClk_DDR, /*!< Clock configurat for DDR mode */ -}; - -/*! @brief FLEXSPI Read Sample Clock Source definition */ -enum _flexspi_read_sample_clk -{ - kFLEXSPIReadSampleClk_LoopbackInternally = 0U, - kFLEXSPIReadSampleClk_LoopbackFromDqsPad = 1U, - kFLEXSPIReadSampleClk_LoopbackFromSckPad = 2U, - kFLEXSPIReadSampleClk_ExternalInputFromDqsPad = 3U, -}; - -/*! @brief Flash Type Definition */ -enum -{ - kFLEXSPIDeviceType_SerialNOR = 1U, /*!< Flash device is Serial NOR */ -}; - -/*! @brief Flash Configuration Command Type */ -enum -{ - kDeviceConfigCmdType_Generic, /*!< Generic command, for example: configure dummy cycles, drive strength, etc */ - kDeviceConfigCmdType_QuadEnable, /*!< Quad Enable command */ - kDeviceConfigCmdType_Spi2Xpi, /*!< Switch from SPI to DPI/QPI/OPI mode */ - kDeviceConfigCmdType_Xpi2Spi, /*!< Switch from DPI/QPI/OPI to SPI mode */ - kDeviceConfigCmdType_Spi2NoCmd, /*!< Switch to 0-4-4/0-8-8 mode */ - kDeviceConfigCmdType_Reset, /*!< Reset device command */ -}; - -/*! @brief Defintions for FLEXSPI Serial Clock Frequency */ -enum _flexspi_serial_clk_freq -{ - kFLEXSPISerialClk_NoChange = 0U, - kFLEXSPISerialClk_30MHz = 1U, - kFLEXSPISerialClk_50MHz = 2U, - kFLEXSPISerialClk_60MHz = 3U, - kFLEXSPISerialClk_75MHz = 4U, - kFLEXSPISerialClk_80MHz = 5U, - kFLEXSPISerialClk_100MHz = 6U, - kFLEXSPISerialClk_133MHz = 7U, - kFLEXSPISerialClk_166MHz = 8U, -}; - -/*! @brief Misc feature bit definitions */ -enum -{ - kFLEXSPIMiscOffset_DiffClkEnable = 0U, /*!< Bit for Differential clock enable */ - kFLEXSPIMiscOffset_Ck2Enable = 1U, /*!< Bit for CK2 enable */ - kFLEXSPIMiscOffset_ParallelEnable = 2U, /*!< Bit for Parallel mode enable */ - kFLEXSPIMiscOffset_WordAddressableEnable = 3U, /*!< Bit for Word Addressable enable */ - kFLEXSPIMiscOffset_SafeConfigFreqEnable = 4U, /*!< Bit for Safe Configuration Frequency enable */ - kFLEXSPIMiscOffset_PadSettingOverrideEnable = 5U, /*!< Bit for Pad setting override enable */ - kFLEXSPIMiscOffset_DdrModeEnable = 6U, /*!< Bit for DDR clock confiuration indication. */ - kFLEXSPIMiscOffset_UseValidTimeForAllFreq = 7U, /*!< Bit for DLLCR settings under all modes */ -}; - -/*@}*/ - -/*! @brief Manufacturer ID */ -enum -{ - kSerialFlash_ISSI_ManufacturerID = 0x9DU, /*!< Manufacturer ID of the ISSI serial flash */ - kSerialFlash_Adesto_ManufacturerID = 0x1FU, /*!< Manufacturer ID of the Adesto Technologies serial flash*/ - kSerialFlash_Winbond_ManufacturerID = 0xEFU, /*!< Manufacturer ID of the Winbond serial flash */ - kSerialFlash_Cypress_ManufacturerID = 0x01U, /*!< Manufacturer ID for Cypress */ -}; - -/*! @brief - * Serial NOR configuration option - */ -typedef struct _serial_nor_config_option -{ - union - { - struct - { - uint32_t max_freq : 4; /*!< Maximum supported Frequency */ - uint32_t misc_mode : 4; /*!< miscellaneous mode */ - uint32_t quad_mode_setting : 4; /*!< Quad mode setting */ - uint32_t cmd_pads : 4; /*!< Command pads */ - uint32_t query_pads : 4; /*!< SFDP read pads */ - uint32_t device_type : 4; /*!< Device type */ - uint32_t option_size : 4; /*!< Option size, in terms of uint32_t, size = (option_size + 1) * 4 */ - uint32_t tag : 4; /*!< Tag, must be 0x0E */ - } B; - uint32_t U; - } option0; - - union - { - struct - { - uint32_t dummy_cycles : 8; /*!< Dummy cycles before read */ - uint32_t status_override : 8; /*!< Override status register value during device mode configuration */ - uint32_t pinmux_group : 4; /*!< The pinmux group selection */ - uint32_t dqs_pinmux_group : 4; /*!< The DQS Pinmux Group Selection */ - uint32_t drive_strength : 4; /*!< The Drive Strength of FLEXSPI Pads */ - uint32_t flash_connection : 4; /*!< Flash connection option: 0 - Single Flash connected to port A, 1 - */ - /*!< Parallel mode, 2 - Single Flash connected to Port B */ - } B; - uint32_t U; - } option1; - -} serial_nor_config_option_t; - -typedef union -{ - struct - { - uint8_t por_mode; - uint8_t current_mode; - uint8_t exit_no_cmd_sequence; - uint8_t restore_sequence; - } B; - uint32_t U; -} flash_run_context_t; - -/*! @brief - * FLEXSPI LUT Sequence structure - */ -typedef struct _lut_sequence -{ - uint8_t seqNum; /*!< Sequence Number, valid number: 1-16 */ - uint8_t seqId; /*!< Sequence Index, valid number: 0-15 */ - uint16_t reserved; -} flexspi_lut_seq_t; - -typedef struct -{ - uint8_t time_100ps; /*!< Data valid time, in terms of 100ps */ - uint8_t delay_cells; /*!< Data valid time, in terms of delay cells */ -} flexspi_dll_time_t; - -/*! @brief - * FLEXSPI Memory Configuration Block - */ -typedef struct _FlexSPIConfig -{ - uint32_t tag; /*!< [0x000-0x003] Tag, fixed value 0x42464346UL */ - uint32_t version; /*!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */ - uint32_t reserved0; /*!< [0x008-0x00b] Reserved for future use */ - uint8_t readSampleClkSrc; /*!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */ - uint8_t csHoldTime; /*!< [0x00d-0x00d] CS hold time, default value: 3 */ - uint8_t csSetupTime; /*!< [0x00e-0x00e] CS setup time, default value: 3 */ - uint8_t columnAddressWidth; /*!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For - Serial NAND, need to refer to datasheet */ - uint8_t deviceModeCfgEnable; /*!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */ - uint8_t deviceModeType; /*!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, - Generic configuration, etc. */ - uint16_t waitTimeCfgCommands; /*!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for - DPI/QPI/OPI switch or reset command */ - flexspi_lut_seq_t deviceModeSeq; /*!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt - sequence number, [31:16] Reserved */ - uint32_t deviceModeArg; /*!< [0x018-0x01b] Argument/Parameter for device configuration */ - uint8_t configCmdEnable; /*!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable */ - uint8_t configModeType[3]; /*!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */ - flexspi_lut_seq_t - configCmdSeqs[3]; /*!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq */ - uint32_t reserved1; /*!< [0x02c-0x02f] Reserved for future use */ - uint32_t configCmdArgs[3]; /*!< [0x030-0x03b] Arguments/Parameters for device Configuration commands */ - uint32_t reserved2; /*!< [0x03c-0x03f] Reserved for future use */ - uint32_t controllerMiscOption; /*!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more - details */ - uint8_t deviceType; /*!< [0x044-0x044] Device Type: See Flash Type Definition for more details */ - uint8_t sflashPadType; /*!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */ - uint8_t serialClkFreq; /*!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot - Chapter for more details */ - uint8_t lutCustomSeqEnable; /*!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot - be done using 1 LUT sequence, currently, only applicable to HyperFLASH */ - uint32_t reserved3[2]; /*!< [0x048-0x04f] Reserved for future use */ - uint32_t sflashA1Size; /*!< [0x050-0x053] Size of Flash connected to A1 */ - uint32_t sflashA2Size; /*!< [0x054-0x057] Size of Flash connected to A2 */ - uint32_t sflashB1Size; /*!< [0x058-0x05b] Size of Flash connected to B1 */ - uint32_t sflashB2Size; /*!< [0x05c-0x05f] Size of Flash connected to B2 */ - uint32_t csPadSettingOverride; /*!< [0x060-0x063] CS pad setting override value */ - uint32_t sclkPadSettingOverride; /*!< [0x064-0x067] SCK pad setting override value */ - uint32_t dataPadSettingOverride; /*!< [0x068-0x06b] data pad setting override value */ - uint32_t dqsPadSettingOverride; /*!< [0x06c-0x06f] DQS pad setting override value */ - uint32_t timeoutInMs; /*!< [0x070-0x073] Timeout threshold for read status command */ - uint32_t commandInterval; /*!< [0x074-0x077] CS deselect interval between two commands */ - flexspi_dll_time_t dataValidTime[2]; /*!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B */ - uint16_t busyOffset; /*!< [0x07c-0x07d] Busy offset, valid value: 0-31 */ - uint16_t busyBitPolarity; /*!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - - busy flag is 0 when flash device is busy */ - uint32_t lookupTable[64]; /*!< [0x080-0x17f] Lookup table holds Flash command sequences */ - flexspi_lut_seq_t lutCustomSeq[12]; /*!< [0x180-0x1af] Customizable LUT Sequences */ - uint32_t dll0CrVal; //!> [0x1b0-0x1b3] Customizable DLL0CR setting */ - uint32_t dll1CrVal; //!> [0x1b4-0x1b7] Customizable DLL1CR setting */ - uint32_t reserved4[2]; /*!< [0x1b8-0x1bf] Reserved for future use */ -} flexspi_mem_config_t; - -/*! @brief - * Serial NOR configuration block - */ -typedef struct _flexspi_nor_config -{ - flexspi_mem_config_t memConfig; /*!< Common memory configuration info via FLEXSPI */ - uint32_t pageSize; /*!< Page size of Serial NOR */ - uint32_t sectorSize; /*!< Sector size of Serial NOR */ - uint8_t ipcmdSerialClkFreq; /*!< Clock frequency for IP command */ - uint8_t isUniformBlockSize; /*!< Sector/Block size is the same */ - uint8_t isDataOrderSwapped; /*!< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) */ - uint8_t reserved0[1]; /*!< Reserved for future use */ - uint8_t serialNorType; /*!< Serial NOR Flash type: 0/1/2/3 */ - uint8_t needExitNoCmdMode; /*!< Need to exit NoCmd mode before other IP command */ - uint8_t halfClkForNonReadCmd; /*!< Half the Serial Clock for non-read command: true/false */ - uint8_t needRestoreNoCmdMode; /*!< Need to Restore NoCmd mode after IP commmand execution */ - uint32_t blockSize; /*!< Block size */ - uint32_t flashStateCtx; /*!< Flash State Context */ - uint32_t reserve2[10]; /*!< Reserved for future use */ -} flexspi_nor_config_t; - -typedef enum _flexspi_operation -{ - kFLEXSPIOperation_Command, /*!< FLEXSPI operation: Only command, both TX and RX buffer are ignored. */ - kFLEXSPIOperation_Config, /*!< FLEXSPI operation: Configure device mode, the TX FIFO size is fixed in LUT. */ - kFLEXSPIOperation_Write, /*!< FLEXSPI operation: Write, only TX buffer is effective */ - kFLEXSPIOperation_Read, /*!< FLEXSPI operation: Read, only Rx Buffer is effective. */ - kFLEXSPIOperation_End = kFLEXSPIOperation_Read, -} flexspi_operation_t; - -/*! @brief FLEXSPI Transfer Context */ -typedef struct _flexspi_xfer -{ - flexspi_operation_t operation; /*!< FLEXSPI operation */ - uint32_t baseAddress; /*!< FLEXSPI operation base address */ - uint32_t seqId; /*!< Sequence Id */ - uint32_t seqNum; /*!< Sequence Number */ - bool isParallelModeEnable; /*!< Is a parallel transfer */ - uint32_t *txBuffer; /*!< Tx buffer */ - uint32_t txSize; /*!< Tx size in bytes */ - uint32_t *rxBuffer; /*!< Rx buffer */ - uint32_t rxSize; /*!< Rx size in bytes */ -} flexspi_xfer_t; - -/*! @brief - * FLEXSPI Clock Type - */ -typedef enum -{ - kFlexSpiClock_CoreClock, /*!< ARM Core Clock */ - kFlexSpiClock_AhbClock, /*!< AHB clock */ - kFlexSpiClock_SerialRootClock, /*!< Serial Root Clock */ - kFlexSpiClock_IpgClock, /*!< IPG clock */ -} flexspi_clock_type_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @brief Initialize Serial NOR devices via FLEXSPI - * - * This function checks and initializes the FLEXSPI module for the other FLEXSPI APIs. - * - * @param instance storage the instance of FLEXSPI. - * @param config A pointer to the storage for the driver runtime state. - * - * @retval #kStatus_Success Api was executed succesfuly. - * @retval #kStatus_InvalidArgument A invalid argument is provided. - * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. - * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. - * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout - */ -status_t FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config); - -/*! - * @brief Program data to Serial NOR via FLEXSPI. - * - * This function programs the NOR flash memory with the dest address for a given - * flash area as determined by the dst address and the length. - * - * @param instance storage the instance of FLEXSPI. - * @param config A pointer to the storage for the driver runtime state. - * @param dst_addr A pointer to the desired flash memory to be programmed. - * NOTE: - * It is recommended that use page aligned access; - * If the dst_addr is not aligned to page,the driver automatically - * aligns address down with the page address. - * @param src A pointer to the source buffer of data that is to be programmed - * into the NOR flash. - * - * @retval #kStatus_Success Api was executed succesfuly. - * @retval #kStatus_InvalidArgument A invalid argument is provided. - * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. - * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. - * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout - */ -status_t FLEXSPI_NorFlash_ProgramPage(uint32_t instance, - flexspi_nor_config_t *config, - uint32_t dstAddr, - const uint32_t *src); - -/*! - * @brief Erase all the Serial NOR devices connected on FLEXSPI. - * - * @param instance storage the instance of FLEXSPI. - * @param config A pointer to the storage for the driver runtime state. - * - * @retval #kStatus_Success Api was executed succesfuly. - * @retval #kStatus_InvalidArgument A invalid argument is provided. - * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. - * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. - * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout - */ -status_t FLEXSPI_NorFlash_EraseAll(uint32_t instance, flexspi_nor_config_t *config); - -/*! - * @brief Erase one sector specified by address - * - * This function erases one of NOR flash sectors based on the desired address. - * - * @param instance storage the index of FLEXSPI. - * @param config A pointer to the storage for the driver runtime state. - * @param address The start address of the desired NOR flash memory to be erased. - * NOTE: - * It is recommended that use sector-aligned access nor device; - * If dstAddr is not aligned with the sector,The driver automatically - * aligns address down with the sector address. - * - * @retval #kStatus_Success Api was executed succesfuly. - * @retval #kStatus_InvalidArgument A invalid argument is provided. - * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. - * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. - * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout - */ -status_t FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); - -/*! - * @brief Erase one block specified by address - * - * This function erases one block of NOR flash based on the desired address. - * - * @param instance storage the index of FLEXSPI. - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired NOR flash memory to be erased. - * NOTE: - * It is recommended that use block-aligned access nor device; - * If dstAddr is not aligned with the block,The driver automatically - * aligns address down with the block address. - * - * @retval #kStatus_Success Api was executed succesfuly. - * @retval #kStatus_InvalidArgument A invalid argument is provided. - * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. - * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. - * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout - */ -status_t FLEXSPI_NorFlash_Erase_Block(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); - -/*! - * @brief Get FLEXSPI NOR Configuration Block based on specified option. - * - * @param instance storage the instance of FLEXSPI. - * @param config A pointer to the storage for the driver runtime state. - * @param option A pointer to the storage Serial NOR Configuration Option Context. - * - * @retval #kStatus_Success Api was executed succesfuly. - * @retval #kStatus_InvalidArgument A invalid argument is provided. - * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. - * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. - * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout - */ -status_t FLEXSPI_NorFlash_GetConfig(uint32_t instance, - flexspi_nor_config_t *config, - serial_nor_config_option_t *option); - -/*! - * @brief Erase Flash Region specified by address and length - * - * This function erases the appropriate number of flash sectors based on the - * desired start address and length. - * - * @param instance storage the index of FLEXSPI. - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired NOR flash memory to be erased. - * NOTE: - * It is recommended that use sector-aligned access nor device; - * If dstAddr is not aligned with the sector,the driver automatically - * aligns address down with the sector address. - * @param length The length, given in bytes to be erased. - * NOTE: - * It is recommended that use sector-aligned access nor device; - * If length is not aligned with the sector,the driver automatically - * aligns up with the sector. - * @retval #kStatus_Success Api was executed succesfuly. - * @retval #kStatus_InvalidArgument A invalid argument is provided. - * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. - * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. - * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout - */ -status_t FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length); - -/*! - * @brief Read data from Serial NOR via FLEXSPI. - * - * This function read the NOR flash memory with the start address for a given - * flash area as determined by the dst address and the length. - * - * @param instance storage the instance of FLEXSPI. - * @param config A pointer to the storage for the driver runtime state. - * @param dst A pointer to the dest buffer of data that is to be read from the NOR flash. - * NOTE: - * It is recommended that use page aligned access; - * If the dstAddr is not aligned to page,the driver automatically - * aligns address down with the page address. - * @param start The start address of the desired NOR flash memory to be read. - * @param lengthInBytes The length, given in bytes to be read. - * - * @retval #kStatus_Success Api was executed succesfuly. - * @retval #kStatus_InvalidArgument A invalid argument is provided. - * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. - * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. - * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout - */ -status_t FLEXSPI_NorFlash_Read( - uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes); - -/*! - * @brief FLEXSPI command - * - * This function is used to perform the command write sequence to the NOR device. - * - * @param instance storage the index of FLEXSPI. - * @param xfer A pointer to the storage FLEXSPI Transfer Context. - * - * @retval kStatus_Success Api was executed succesfuly. - * @retval kStatus_InvalidArgument A invalid argument is provided. - * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. - * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. - */ -status_t FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer); - -/*! - * @brief Configure FLEXSPI Lookup table - * - * @param instance storage the index of FLEXSPI. - * @param seqIndex storage the sequence Id. - * @param lutBase A pointer to the look-up-table for command sequences. - * @param seqNumber storage sequence number. - * - * @retval kStatus_Success Api was executed succesfuly. - * @retval kStatus_InvalidArgument A invalid argument is provided. - * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. - * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. - */ -status_t FLEXSPI_NorFlash_UpdateLut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t seqNumber); - -/*! - * @brief Set the clock source for FLEXSPI NOR - * - * @param clockSource Clock source for FLEXSPI NOR. See to "_flexspi_nor_clock_source". - * - * @retval #kStatus_Success Api was executed succesfuly. - * @retval #kStatus_InvalidArgument A invalid argument is provided. - */ -status_t FLEXSPI_NorFlash_SetClockSource(uint32_t clockSource); - -#ifdef __cplusplus -} -#endif - -#endif /*! _FSL_FLEXSPI_NOR_FLASH_H__ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/src/fsl_flash.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/src/fsl_flash.c deleted file mode 100644 index 74ee539e537..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/src/fsl_flash.c +++ /dev/null @@ -1,511 +0,0 @@ -/* - * Copyright 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "fsl_flash.h" -#include "fsl_flash_ffr.h" -#include "fsl_flexspi_nor_flash.h" - -/*! @brief Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.niobe4analog_iap" -#endif - -#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1302FC00U) - -/*! - * @name flash, ffr, flexspi nor flash Structure - * @{ - */ - -typedef union functionCommandOption -{ - uint32_t commandAddr; - status_t (*isFlashAreaReadable)(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); - status_t (*isFlashAreaModifiable)(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); -} function_command_option_t; - -/*! - * @brief Structure of version property. - * - * @ingroup bl_core - */ -typedef union StandardVersion -{ - struct - { - uint8_t bugfix; /*!< bugfix version [7:0] */ - uint8_t minor; /*!< minor version [15:8] */ - uint8_t major; /*!< major version [23:16] */ - char name; /*!< name [31:24] */ - }; - uint32_t version; /*!< combined version numbers */ -} standard_version_t; - -/*! @brief Interface for the flash driver.*/ -typedef struct FlashDriverInterface -{ - standard_version_t version; /*!< flash driver API version number. */ - /* Flash driver */ - status_t (*flash_init)(flash_config_t *config); - status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); - status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); - status_t (*flash_verify_program)(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); - - status_t (*flash_erase_with_checker)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - status_t (*flash_program_with_checker)(flash_config_t *config, - uint32_t start, - uint8_t *src, - uint32_t lengthInBytes); - status_t (*flash_verify_program_with_checker)(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - /*!< Flash FFR driver */ - status_t (*ffr_init)(flash_config_t *config); - status_t (*ffr_lock)(flash_config_t *config); - status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); - status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); - status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - status_t (*ffr_cust_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); - status_t reserved0; - status_t reserved1; - status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); - status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - status_t (*flash_read)(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); - status_t (*ffr_seclib_init)(flash_config_t *config, uint32_t *context); - status_t (*flash_get_cust_keystore)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - status_t (*flash_erase_non_blocking)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - status_t (*flash_get_command_state)(flash_config_t *config); -} flash_driver_interface_t; - -/*! @brief FLEXSPI Flash driver API Interface */ -typedef struct -{ - uint32_t version; - status_t (*init)(uint32_t instance, flexspi_nor_config_t *config); - status_t (*page_program)(uint32_t instance, flexspi_nor_config_t *config, uint32_t dstAddr, const uint32_t *src); - status_t (*erase_all)(uint32_t instance, flexspi_nor_config_t *config); - status_t (*erase)(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length); - status_t (*erase_sector)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); - status_t (*erase_block)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); - status_t (*get_config)(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option); - status_t (*read)(uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes); - status_t (*xfer)(uint32_t instance, flexspi_xfer_t *xfer); - status_t (*update_lut)(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq); - status_t (*set_clock_source)(uint32_t clockSrc); - void (*config_clock)(uint32_t instance, uint32_t freqOption, uint32_t sampleClkMode); -} flexspi_nor_flash_driver_t; - -/*! @}*/ - -/*! - * @brief Root of the bootloader API tree. - * - * An instance of this struct resides in read-only memory in the bootloader. It - * provides a user application access to APIs exported by the bootloader. - * - * @note The order of existing fields must not be changed. - */ -typedef struct BootloaderTree -{ - void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing.*/ - standard_version_t version; /*!< Bootloader version number.*/ - const char *copyright; /*!< Copyright string.*/ - const uint32_t reserved0; /*!< reserved*/ - const flash_driver_interface_t *flashDriver; /*!< Internal Flash driver API.*/ - const uint32_t reserved1[5]; /*!< reserved*/ - const uint32_t nbootDriver; /*!< Please refer to "fsl_nboot.h" */ - const flexspi_nor_flash_driver_t *flexspiNorDriver; /*!< FlexSPI NOR FLASH Driver API.*/ - const uint32_t reserved2; /*!< reserved*/ - const uint32_t memoryInterface; /*!< Please refer to "fsl_mem_interface.h" */ -} bootloader_tree_t; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/******************************************************************************** - * Internal Flash driver API - *******************************************************************************/ -/*! - * @brief Initializes the global flash properties structure members. - * - * This function checks and initializes the Flash module for the other Flash APIs. - */ -status_t FLASH_Init(flash_config_t *config) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_init(config); -} - -/*! - * @brief Erases the flash sectors encompassed by parameters passed into function. - * - * This function erases the appropriate number of flash sectors based on the - * desired start address and length. - */ -status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_erase(config, start, lengthInBytes, key); -} - -status_t FLASH_EraseNonBlocking(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_erase_non_blocking(config, start, lengthInBytes, key); - -} - -/*! - * @brief Programs flash with data at locations passed in through parameters. - * - * This function programs the flash memory with the desired data for a given - * flash area as determined by the start address and the length. - */ -status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_program(config, start, src, lengthInBytes); -} - -/*! - * @brief Verifies an erasure of the desired flash area at a specified margin level. - * - * This function checks the appropriate number of flash sectors based on - * the desired start address and length to check whether the flash is erased - * to the specified read margin level. - */ -status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_verify_erase(config, start, lengthInBytes); -} - -/*! - * @brief Reads flash at locations passed in through parameters. - * - * This function read the flash memory from a given flash area as determined - * by the start address and the length. - */ -status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_read(config, start, dest, lengthInBytes); -} - -/*! - * @brief Verifies programming of the desired flash area at a specified margin level. - * - * This function verifies the data programed in the flash memory using the - * Flash Program Check Command and compares it to the expected data for a given - * flash area as determined by the start address and length. - */ -status_t FLASH_VerifyProgram(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_verify_program(config, start, lengthInBytes, expectedData, - failedAddress, failedData); -} - -/*! - * @brief Returns the desired flash property. - */ -status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_get_property(config, whichProperty, value); -} - -#if defined(BL_FEATURE_HAS_BUS_CRYPTO_ENGINE) && BL_FEATURE_HAS_BUS_CRYPTO_ENGINE -status_t FLASH_ErasePrologue(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_erase_with_checker(config, start, lengthInBytes, key); -} - -status_t FLASH_ProgramPrologue(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_program_with_checker(config, start, src, lengthInBytes); -} - -status_t FLASH_VerifyProgramPrologue(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_verify_program_with_checker( - config, start, lengthInBytes, expectedData, failedAddress, failedData); -} - -#endif // BL_FEATURE_HAS_BUS_CRYPTO_ENGINE - -#if defined(FSL_FEATURE_SYSCON_HAS_FLASH_HIDING) && (FSL_FEATURE_SYSCON_HAS_FLASH_HIDING == 1) -/*! - * @brief Validates the given address range is loaded in the flash hiding region. - */ -status_t FLASH_IsFlashAreaReadable(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes) -{ - function_command_option_t runCmdFuncOption; - runCmdFuncOption.commandAddr = 0x13028c41U; /*!< get the flash erase api location adress in rom */ - return runCmdFuncOption.isFlashAreaReadable(config, startAddress, lengthInBytes); -} -#endif - -#if defined(FSL_FEATURE_SYSCON_HAS_CDPA) && (FSL_FEATURE_SYSCON_HAS_CDPA == 1) -/*! - * @brief Validates the given address range is loaded in the Flash firewall page locked region. - */ -status_t FLASH_IsFlashAreaModifiable(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes) -{ - function_command_option_t runCmdFuncOption; - runCmdFuncOption.commandAddr = 0x13028ca1U; /*!< get the flash erase api location adress in rom */ - return runCmdFuncOption.isFlashAreaModifiable(config, startAddress, lengthInBytes); -} -#endif - -/*! - * @brief Get flash command execute status. - */ -status_t FLASH_GetCommandState(flash_config_t *config) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_get_command_state(config); -} - -/******************************************************************************** - * fsl iap ffr CODE - *******************************************************************************/ - -/*! - * @brief Initializes the global FFR properties structure members. - */ -status_t FFR_Init(flash_config_t *config) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_init(config); -} - -/*! - * @brief Enable firewall for all flash banks. - */ -status_t FFR_Lock(flash_config_t *config) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_lock(config); -} - -/*! - * @brief APIs to access CMPA pages; - * This routine will erase "customer factory page" and program the page with passed data. - */ -status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_cust_factory_page_write(config, page_data, seal_part); -} - -/*! - * @brief See fsl_iap_ffr.h for documentation of this function. - */ -status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_get_uuid(config, uuid); -} - -/*! - * @brief APIs to access CMPA pages - * Read data stored in 'Customer Factory CFG Page'. - */ -status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_get_customer_data(config, pData, offset, len); -} - -/*! - * @brief This routine writes the 3 pages allocated for Key store data. - */ -status_t FFR_CustKeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_cust_keystore_write(config, pKeyStore); -} - -/*! - * @brief APIs to access CFPA pages - * This routine will erase CFPA and program the CFPA page with passed data. - */ -status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_infield_page_write(config, page_data, valid_len); -} - -/*! - * @brief APIs to access CFPA pages - * Generic read function, used by customer to read data stored in 'Customer In-field Page'. - */ -status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_get_customer_infield_data(config, pData, offset, len); -} - -/*! - * @brief Initialize the Security Library for FFR driver - */ -status_t FFR_SecLibInit(flash_config_t *config, uint32_t *context) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_seclib_init(config, context); -} - -/*! - * @brief The API is used for getting the customer key store data from the customer key store region(0x3e400 ¨C 0x3e600), - * and the API should be called after the FLASH_Init and FFR_Init. - */ -status_t FFR_GetCustKeystoreData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_get_cust_keystore(config, pData, offset, len); -} - -/******************************************************************************** - * FlexSPI NOR FLASH Driver API - *******************************************************************************/ -/*! - * @brief Initialize Serial NOR devices via FLEXSPI. - */ -status_t FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->init(instance, config); -} - -/*! - * @brief Program data to Serial NOR via FlexSPI - */ -status_t FLEXSPI_NorFlash_ProgramPage(uint32_t instance, - flexspi_nor_config_t *config, - uint32_t dstAddr, - const uint32_t *src) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->page_program(instance, config, dstAddr, src); -} - -/*! - * @brief Erase all the Serial NOR devices connected on FlexSPI - */ -status_t FLEXSPI_NorFlash_EraseAll(uint32_t instance, flexspi_nor_config_t *config) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->erase_all(instance, config); -} - -/*! - * @brief Erase Flash Region specified by address and length - */ -status_t FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->erase(instance, config, start, length); -} - -/*! - * @brief Erase one sector specified by address - */ -status_t FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t address) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->erase_sector(instance, config, address); -} - -/*! - * @brief Erase one block specified by address - */ -status_t FLEXSPI_NorFlash_EraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t address) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->erase_block(instance, config, address); -} - -/*! - * @brief Get FlexSPI NOR Configuration Block based on specified option - */ -status_t FLEXSPI_NorFlash_GetConfig(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->get_config(instance, config, option); -} - -/*! - * @brief Read data from Serial NOR - */ -status_t FLEXSPI_NorFlash_Read( - uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->read(instance, config, dst, start, bytes); -} - -/*! - * @brief Perform FlexSPI command - */ -status_t FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->xfer(instance, xfer); -} - -/*! - * @brief Configure FlexSPI Lookup table - */ -status_t FLEXSPI_NorFlash_UpdateLut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->update_lut(instance, seqIndex, lutBase, numberOfSeq); -} - -/*! - * @brief Set flexspi clock source - */ -status_t FLEXSPI_NorFlash_SetClockSource(uint32_t clockSource) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->set_clock_source(clockSource); -} - -/*! - * @brief config flexspi clock - */ -void FLEXSPI_NorFlash_ConfigClock(uint32_t instance, uint32_t freqOption, uint32_t sampleClkMode) -{ - assert(BOOTLOADER_API_TREE_POINTER); - BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->config_clock(instance, freqOption, sampleClkMode); -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_anactrl.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_anactrl.c deleted file mode 100644 index 68175b880a3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_anactrl.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright 2018-2021, NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_anactrl.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.anactrl" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for ANACTRL module. - * - * @param base ANACTRL peripheral base address - */ -static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to ANACTRL bases for each instance. */ -static ANACTRL_Type *const s_anactrlBases[] = ANACTRL_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to ANACTRL clocks for each instance. */ -static const clock_ip_name_t s_anactrlClocks[] = ANALOGCTRL_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! - * brief Get the ANACTRL instance from peripheral base address. - * - * param base ANACTRL peripheral base address. - * return ANACTRL instance. - */ -static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_anactrlBases); instance++) - { - if (s_anactrlBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_anactrlBases)); - - return instance; -} - -/*! - * brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function. - * - * param base ANACTRL peripheral base address. - */ -void ANACTRL_Init(ANACTRL_Type *base) -{ - assert(NULL != base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock for ANACTRL instance. */ - CLOCK_EnableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function. - * - * param base ANACTRL peripheral base address. - */ -void ANACTRL_Deinit(ANACTRL_Type *base) -{ - assert(NULL != base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock for ANACTRL instance. */ - CLOCK_DisableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock output - * and enable/disable 96MHZ clock output. - * - * param base ANACTRL peripheral base address. - * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure. - */ -void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32 = base->FRO192M_CTRL; - - tmp32 &= ~(ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK); - - if (config->enable12MHzClk) - { - tmp32 |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK; - } - if (config->enable96MHzClk) - { - tmp32 |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; - } - - base->FRO192M_CTRL |= tmp32; -} - -/*! - * brief Gets the default configuration of FRO192M. - * The default values are: - * code - config->enable12MHzClk = true; - config->enable96MHzClk = false; - endcode - * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure. - */ -void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enable12MHzClk = true; - config->enable96MHzClk = false; -} - -/*! - * brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU - * system, and so on. - * - * param base ANACTRL peripheral base address. - * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure. - */ -void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32 = base->XO32M_CTRL; - - tmp32 &= ~(ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK | ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK); - - /* Set XO32M CTRL. */ -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) - tmp32 &= ~ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; - if (config->enablePllUsbOutput) - { - tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; - } -#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ - - if (config->enableACBufferBypass) - { - tmp32 |= ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; - } - - if (config->enableSysCLkOutput) - { - tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; - } - base->XO32M_CTRL = tmp32; - -#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) - if (config->enableADCOutput) - { - base->DUMMY_CTRL |= ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK; - } - else - { - base->DUMMY_CTRL &= ~ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK; - } -#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ -} - -/*! - * brief Gets the default configuration of XO32M. - * The default values are: - * code - config->enableSysCLkOutput = false; - config->enableACBufferBypass = false; - endcode - * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure. - */ -void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) - config->enablePllUsbOutput = false; -#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ - config->enableSysCLkOutput = false; - config->enableACBufferBypass = false; -#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) - config->enableADCOutput = true; -#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ -} - -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) -/*! - * brief Measures the frequency of the target clock source. - * - * This function measures target frequency according to a accurate reference frequency.The formula is: - * Ftarget = (CAPVAL * Freference) / ((1<= 2U); - - uint32_t targetClkFreq = 0U; - uint32_t capval = 0U; - - /* Init a measurement cycle. */ - base->FREQ_ME_CTRL = ANACTRL_FREQ_ME_CTRL_PROG_MASK + ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(scale); - while (ANACTRL_FREQ_ME_CTRL_PROG_MASK == (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_PROG_MASK)) - { - } - - /* Calculate the target clock frequency. */ - capval = (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK); - targetClkFreq = (capval * refClkFreq) / ((1UL << scale) - 1UL); - - return targetClkFreq; -} -#endif /* FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_anactrl.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_anactrl.h deleted file mode 100644 index 4ca845b5a9a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_anactrl.h +++ /dev/null @@ -1,377 +0,0 @@ -/* - * Copyright 2018-2021, NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __FSL_ANACTRL_H__ -#define __FSL_ANACTRL_H__ - -#include "fsl_common.h" - -/*! - * @addtogroup anactrl - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief ANACTRL driver version. */ -#define FSL_ANACTRL_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*!< Version 2.3.0. */` - -/*! - * @brief ANACTRL interrupt flags - */ -enum _anactrl_interrupt_flags -{ -#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) - kANACTRL_BodVDDMainFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_MASK, /*!< BOD VDDMAIN Interrupt status - before Interrupt Enable. */ - kANACTRL_BodVDDMainInterruptFlag = - ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_MASK, /*!< BOD VDDMAIN Interrupt status - after Interrupt Enable. */ - kANACTRL_BodVDDMainPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_MASK, /*!< Current value of BOD VDDMAIN - power status output. */ -#else - kANACTRL_BodVbatFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK, /*!< BOD VBAT Interrupt status before - Interrupt Enable. */ - kANACTRL_BodVbatInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK, /*!< BOD VBAT Interrupt status - after Interrupt Enable. */ - kANACTRL_BodVbatPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK, /*!< Current value of BOD VBAT power - status output. */ -#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */ - kANACTRL_BodCoreFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK, /*!< BOD CORE Interrupt status before - Interrupt Enable. */ - kANACTRL_BodCoreInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK, /*!< BOD CORE Interrupt status - after Interrupt Enable. */ - kANACTRL_BodCorePowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK, /*!< Current value of BOD CORE power - status output. */ - kANACTRL_DcdcFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK, /*!< DCDC Interrupt status before - Interrupt Enable. */ - kANACTRL_DcdcInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK, /*!< DCDC Interrupt status after - Interrupt Enable. */ - kANACTRL_DcdcPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK, /*!< Current value of DCDC power - status output. */ -}; - -/*! - * @brief ANACTRL interrupt control - */ -enum _anactrl_interrupt -{ -#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) - kANACTRL_BodVDDMainInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_MASK, /*!< BOD VDDMAIN - interrupt control. */ -#else - kANACTRL_BodVbatInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK, /*!< BOD VBAT interrupt - control. */ -#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */ - kANACTRL_BodCoreInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK, /*!< BOD CORE interrupt - control. */ - kANACTRL_DcdcInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK, /*!< DCDC interrupt control. */ -}; - -/*! - * @brief ANACTRL status flags - */ -enum _anactrl_flags -{ - kANACTRL_FlashPowerDownFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK, /*!< Flash power-down status. */ - kANACTRL_FlashInitErrorFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK, /*!< Flash initialization - error status. */ -}; - -/*! - * @brief ANACTRL FRO192M and XO32M status flags - */ -enum _anactrl_osc_flags -{ - kANACTRL_OutputClkValidFlag = ANACTRL_FRO192M_STATUS_CLK_VALID_MASK, /*!< Output clock valid signal. */ - kANACTRL_CCOThresholdVoltageFlag = ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK, /*!< CCO threshold voltage detector - output (signal vcco_ok). */ - kANACTRL_XO32MOutputReadyFlag = ANACTRL_XO32M_STATUS_XO_READY_MASK << 16U, /*!< Indicates XO out - frequency statibilty. */ -}; - -/*! - * @brief Configuration for FRO192M - * - * This structure holds the configuration settings for the on-chip high-speed Free Running Oscillator. To initialize - * this structure to reasonable defaults, call the ANACTRL_GetDefaultFro192MConfig() function and pass a - * pointer to your config structure instance. - */ -typedef struct _anactrl_fro192M_config -{ - bool enable12MHzClk; /*!< Enable 12MHz clock. */ - bool enable96MHzClk; /*!< Enable 96MHz clock. */ -} anactrl_fro192M_config_t; - -/*! - * @brief Configuration for XO32M - * - * This structure holds the configuration settings for the 32 MHz crystal oscillator. To initialize this - * structure to reasonable defaults, call the ANACTRL_GetDefaultXo32MConfig() function and pass a - * pointer to your config structure instance. - */ -typedef struct _anactrl_xo32M_config -{ - bool enableACBufferBypass; /*!< Enable XO AC buffer bypass in pll and top level. */ -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) - bool enablePllUsbOutput; /*!< Enable XO 32 MHz output to USB HS PLL. */ -#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ - bool enableSysCLkOutput; /*!< Enable XO 32 MHz output to CPU system, SCT, and CLKOUT */ -#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) - bool enableADCOutput; /*!< Enable High speed crystal oscillator output to ADC. */ -#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ -} anactrl_xo32M_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function. - * - * @param base ANACTRL peripheral base address. - */ -void ANACTRL_Init(ANACTRL_Type *base); - -/*! - * @brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function. - * - * @param base ANACTRL peripheral base address. - */ -void ANACTRL_Deinit(ANACTRL_Type *base); -/* @} */ - -/*! - * @name Set oscillators - * @{ - */ - -/*! - * @brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock - * output and enable/disable 96MHZ clock output. - * - * @param base ANACTRL peripheral base address. - * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure. - */ -void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config); - -/*! - * @brief Gets the default configuration of FRO192M. - * The default values are: - * @code - config->enable12MHzClk = true; - config->enable96MHzClk = false; - @endcode - * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure. - */ -void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config); - -/*! - * @brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU - * system, and so on. - * - * @param base ANACTRL peripheral base address. - * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure. - */ -void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config); - -/*! - * @brief Gets the default configuration of XO32M. - * The default values are: - * @code - config->enableSysCLkOutput = false; - config->enableACBufferBypass = false; - @endcode - * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure. - */ -void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config); - -/* @} */ - -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) -/*! - * @name Measure Frequency - * @{ - */ - -/*! - * @brief Measures the frequency of the target clock source. - * - * This function measures target frequency according to a accurate reference frequency.The formula is: - * Ftarget = (CAPVAL * Freference) / ((1<BOD_DCDC_INT_CTRL |= (0x15U & mask); -} - -/*! - * @brief Disables the ANACTRL interrupts. - * - * @param base ANACTRL peripheral base address. - * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration. - */ -static inline void ANACTRL_DisableInterrupts(ANACTRL_Type *base, uint32_t mask) -{ - base->BOD_DCDC_INT_CTRL &= ~(0x15U & mask); -} - -/*! - * @brief Clears the ANACTRL interrupts. - * - * @param base ANACTRL peripheral base address. - * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration. - */ -static inline void ANACTRL_ClearInterrupts(ANACTRL_Type *base, uint32_t mask) -{ - base->BOD_DCDC_INT_CTRL |= (uint32_t)(mask << 1UL); -} -/* @} */ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets ANACTRL status flags. - * - * This function gets Analog control status flags. The flags are returned as the logical - * OR value of the enumerators @ref _anactrl_flags. To check for a specific status, - * compare the return value with enumerators in the @ref _anactrl_flags. - * For example, to check whether the flash is in power down mode: - * @code - * if (kANACTRL_FlashPowerDownFlag & ANACTRL_ANACTRL_GetStatusFlags(ANACTRL)) - * { - * ... - * } - * @endcode - * - * @param base ANACTRL peripheral base address. - * @return ANACTRL status flags which are given in the enumerators in the @ref _anactrl_flags. - */ -static inline uint32_t ANACTRL_GetStatusFlags(ANACTRL_Type *base) -{ - return base->ANALOG_CTRL_STATUS; -} - -/*! - * @brief Gets ANACTRL oscillators status flags. - * - * This function gets Anactrl oscillators status flags. The flags are returned as the logical - * OR value of the enumerators @ref _anactrl_osc_flags. To check for a specific status, - * compare the return value with enumerators in the @ref _anactrl_osc_flags. - * For example, to check whether the FRO192M clock output is valid: - * @code - * if (kANACTRL_OutputClkValidFlag & ANACTRL_ANACTRL_GetOscStatusFlags(ANACTRL)) - * { - * ... - * } - * @endcode - * - * @param base ANACTRL peripheral base address. - * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags. - */ -static inline uint32_t ANACTRL_GetOscStatusFlags(ANACTRL_Type *base) -{ - return (base->FRO192M_STATUS & 0xFFU) | ((base->XO32M_STATUS & 0xFFU) << 16U); -} - -/*! - * @brief Gets ANACTRL interrupt status flags. - * - * This function gets Anactrl interrupt status flags. The flags are returned as the logical - * OR value of the enumerators @ref _anactrl_interrupt_flags. To check for a specific status, - * compare the return value with enumerators in the @ref _anactrl_interrupt_flags. - * For example, to check whether the VBAT voltage level is above the threshold: - * @code - * if (kANACTRL_BodVbatPowerFlag & ANACTRL_ANACTRL_GetInterruptStatusFlags(ANACTRL)) - * { - * ... - * } - * @endcode - * - * @param base ANACTRL peripheral base address. - * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags. - */ -static inline uint32_t ANACTRL_GetInterruptStatusFlags(ANACTRL_Type *base) -{ - return base->BOD_DCDC_INT_STATUS & 0x1FFU; -} -/* @} */ - -#if (defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) && (FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG == 1U)) -/*! - * @brief Aux_Bias Control Interfaces - * @{ - */ - -/*! - * @brief Enables/disabless 1V reference voltage buffer. - * - * @param base ANACTRL peripheral base address. - * @param enable Used to enable or disable 1V reference voltage buffer. - */ -static inline void ANACTRL_EnableVref1V(ANACTRL_Type *base, bool enable) -{ - if (enable) - { - base->AUX_BIAS |= ANACTRL_AUX_BIAS_VREF1VENABLE_MASK; - } - else - { - base->AUX_BIAS &= ~ANACTRL_AUX_BIAS_VREF1VENABLE_MASK; - } -} - -/* @} */ -#endif /* defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) */ - -#if defined(__cplusplus) -} -#endif - -/* @}*/ - -#endif /* __FSL_ANACTRL_H__ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_aoi.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_aoi.c deleted file mode 100644 index a8f1f29ddb4..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_aoi.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_aoi.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.aoi" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to aoi bases for each instance. */ -static AOI_Type *const s_aoiBases[] = AOI_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to aoi clocks for each instance. */ -static const clock_ip_name_t s_aoiClocks[] = AOI_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for AOI module. - * - * @param base AOI peripheral base address - * - * @return The AOI instance - */ -static uint32_t AOI_GetInstance(AOI_Type *base); -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t AOI_GetInstance(AOI_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_aoiBases); instance++) - { - if (s_aoiBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_aoiBases)); - - return instance; -} - -/*! - * brief Initializes an AOI instance for operation. - * - * This function un-gates the AOI clock. - * - * param base AOI peripheral address. - */ -void AOI_Init(AOI_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock gate from clock manager. */ - CLOCK_EnableClock(s_aoiClocks[AOI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Deinitializes an AOI instance for operation. - * - * This function shutdowns AOI module. - * - * param base AOI peripheral address. - */ -void AOI_Deinit(AOI_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock gate from clock manager */ - CLOCK_DisableClock(s_aoiClocks[AOI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Gets the Boolean evaluation associated. - * - * This function returns the Boolean evaluation associated. - * - * Example: - code - aoi_event_config_t demoEventLogicStruct; - - AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct); - endcode - * - * param base AOI peripheral address. - * param event Index of the event which will be set of type aoi_event_t. - * param config Selected input configuration . - */ -void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config) -{ - assert((uint32_t)event < (uint32_t)FSL_FEATURE_AOI_EVENT_COUNT); - assert(config != NULL); - - uint16_t value; - uint16_t temp; - /* Read BFCRT01 register at event index. */ - value = base->BFCRT[event].BFCRT01; - - temp = (value & AOI_BFCRT01_PT0_AC_MASK) >> AOI_BFCRT01_PT0_AC_SHIFT; - config->PT0AC = (aoi_input_config_t)temp; - temp = (value & AOI_BFCRT01_PT0_BC_MASK) >> AOI_BFCRT01_PT0_BC_SHIFT; - config->PT0BC = (aoi_input_config_t)temp; - temp = (value & AOI_BFCRT01_PT0_CC_MASK) >> AOI_BFCRT01_PT0_CC_SHIFT; - config->PT0CC = (aoi_input_config_t)temp; - temp = (value & AOI_BFCRT01_PT0_DC_MASK) >> AOI_BFCRT01_PT0_DC_SHIFT; - config->PT0DC = (aoi_input_config_t)temp; - - temp = (value & AOI_BFCRT01_PT1_AC_MASK) >> AOI_BFCRT01_PT1_AC_SHIFT; - config->PT1AC = (aoi_input_config_t)temp; - temp = (value & AOI_BFCRT01_PT1_BC_MASK) >> AOI_BFCRT01_PT1_BC_SHIFT; - config->PT1BC = (aoi_input_config_t)temp; - temp = (value & AOI_BFCRT01_PT1_CC_MASK) >> AOI_BFCRT01_PT1_CC_SHIFT; - config->PT1CC = (aoi_input_config_t)temp; - temp = (value & AOI_BFCRT01_PT1_DC_MASK) >> AOI_BFCRT01_PT1_DC_SHIFT; - config->PT1DC = (aoi_input_config_t)temp; - - /* Read BFCRT23 register at event index. */ - value = base->BFCRT[event].BFCRT23; - - temp = (value & AOI_BFCRT23_PT2_AC_MASK) >> AOI_BFCRT23_PT2_AC_SHIFT; - config->PT2AC = (aoi_input_config_t)temp; - temp = (value & AOI_BFCRT23_PT2_BC_MASK) >> AOI_BFCRT23_PT2_BC_SHIFT; - config->PT2BC = (aoi_input_config_t)temp; - temp = (value & AOI_BFCRT23_PT2_CC_MASK) >> AOI_BFCRT23_PT2_CC_SHIFT; - config->PT2CC = (aoi_input_config_t)temp; - temp = (value & AOI_BFCRT23_PT2_DC_MASK) >> AOI_BFCRT23_PT2_DC_SHIFT; - config->PT2DC = (aoi_input_config_t)temp; - - temp = (value & AOI_BFCRT23_PT3_AC_MASK) >> AOI_BFCRT23_PT3_AC_SHIFT; - config->PT3AC = (aoi_input_config_t)temp; - temp = (value & AOI_BFCRT23_PT3_BC_MASK) >> AOI_BFCRT23_PT3_BC_SHIFT; - config->PT3BC = (aoi_input_config_t)temp; - temp = (value & AOI_BFCRT23_PT3_CC_MASK) >> AOI_BFCRT23_PT3_CC_SHIFT; - config->PT3CC = (aoi_input_config_t)temp; - temp = (value & AOI_BFCRT23_PT3_DC_MASK) >> AOI_BFCRT23_PT3_DC_SHIFT; - config->PT3DC = (aoi_input_config_t)temp; -} - -/*! - * brief Configures an AOI event. - * - * This function configures an AOI event according - * to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D) - * of all product terms (0, 1, 2, and 3) of a desired event. - * - * Example: - code - aoi_event_config_t demoEventLogicStruct; - - demoEventLogicStruct.PT0AC = kAOI_InvInputSignal; - demoEventLogicStruct.PT0BC = kAOI_InputSignal; - demoEventLogicStruct.PT0CC = kAOI_LogicOne; - demoEventLogicStruct.PT0DC = kAOI_LogicOne; - - demoEventLogicStruct.PT1AC = kAOI_LogicZero; - demoEventLogicStruct.PT1BC = kAOI_LogicOne; - demoEventLogicStruct.PT1CC = kAOI_LogicOne; - demoEventLogicStruct.PT1DC = kAOI_LogicOne; - - demoEventLogicStruct.PT2AC = kAOI_LogicZero; - demoEventLogicStruct.PT2BC = kAOI_LogicOne; - demoEventLogicStruct.PT2CC = kAOI_LogicOne; - demoEventLogicStruct.PT2DC = kAOI_LogicOne; - - demoEventLogicStruct.PT3AC = kAOI_LogicZero; - demoEventLogicStruct.PT3BC = kAOI_LogicOne; - demoEventLogicStruct.PT3CC = kAOI_LogicOne; - demoEventLogicStruct.PT3DC = kAOI_LogicOne; - - AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct); - endcode - * - * param base AOI peripheral address. - * param event Event which will be configured of type aoi_event_t. - * param eventConfig Pointer to type aoi_event_config_t structure. The user is responsible for - * filling out the members of this structure and passing the pointer to this function. - */ -void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig) -{ - assert(eventConfig != NULL); - assert((uint32_t)event < (uint32_t)FSL_FEATURE_AOI_EVENT_COUNT); - - uint16_t value; - /* Calculate value to configure product term 0, 1 */ - value = AOI_BFCRT01_PT0_AC(eventConfig->PT0AC) | AOI_BFCRT01_PT0_BC(eventConfig->PT0BC) | - AOI_BFCRT01_PT0_CC(eventConfig->PT0CC) | AOI_BFCRT01_PT0_DC(eventConfig->PT0DC) | - AOI_BFCRT01_PT1_AC(eventConfig->PT1AC) | AOI_BFCRT01_PT1_BC(eventConfig->PT1BC) | - AOI_BFCRT01_PT1_CC(eventConfig->PT1CC) | AOI_BFCRT01_PT1_DC(eventConfig->PT1DC); - /* Write value to register */ - base->BFCRT[event].BFCRT01 = value; - - /* Reset and calculate value to configure product term 2, 3 */ - value = AOI_BFCRT23_PT2_AC(eventConfig->PT2AC) | AOI_BFCRT23_PT2_BC(eventConfig->PT2BC) | - AOI_BFCRT23_PT2_CC(eventConfig->PT2CC) | AOI_BFCRT23_PT2_DC(eventConfig->PT2DC) | - AOI_BFCRT23_PT3_AC(eventConfig->PT3AC) | AOI_BFCRT23_PT3_BC(eventConfig->PT3BC) | - AOI_BFCRT23_PT3_CC(eventConfig->PT3CC) | AOI_BFCRT23_PT3_DC(eventConfig->PT3DC); - /* Write value to register */ - base->BFCRT[event].BFCRT23 = value; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_aoi.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_aoi.h deleted file mode 100644 index 6d905b9d643..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_aoi.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_AOI_H_ -#define _FSL_AOI_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup aoi - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#ifndef AOI -#define AOI AOI0 /*!< AOI peripheral address */ -#endif - -/*! @name Driver version */ -/*@{*/ -#define FSL_AOI_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ -/*@}*/ - -/*! - * @brief AOI input configurations. - * - * The selection item represents the Boolean evaluations. - */ -typedef enum _aoi_input_config -{ - kAOI_LogicZero = 0x0U, /*!< Forces the input to logical zero. */ - kAOI_InputSignal = 0x1U, /*!< Passes the input signal. */ - kAOI_InvInputSignal = 0x2U, /*!< Inverts the input signal. */ - kAOI_LogicOne = 0x3U /*!< Forces the input to logical one. */ -} aoi_input_config_t; - -/*! - * @brief AOI event indexes, where an event is the collection of the four product - * terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D). - */ -typedef enum _aoi_event -{ - kAOI_Event0 = 0x0U, /*!< Event 0 index */ - kAOI_Event1 = 0x1U, /*!< Event 1 index */ - kAOI_Event2 = 0x2U, /*!< Event 2 index */ - kAOI_Event3 = 0x3U /*!< Event 3 index */ -} aoi_event_t; - -/*! - * @brief AOI event configuration structure - * - * Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make - * whole event configuration. - */ -typedef struct _aoi_event_config -{ - aoi_input_config_t PT0AC; /*!< Product term 0 input A */ - aoi_input_config_t PT0BC; /*!< Product term 0 input B */ - aoi_input_config_t PT0CC; /*!< Product term 0 input C */ - aoi_input_config_t PT0DC; /*!< Product term 0 input D */ - aoi_input_config_t PT1AC; /*!< Product term 1 input A */ - aoi_input_config_t PT1BC; /*!< Product term 1 input B */ - aoi_input_config_t PT1CC; /*!< Product term 1 input C */ - aoi_input_config_t PT1DC; /*!< Product term 1 input D */ - aoi_input_config_t PT2AC; /*!< Product term 2 input A */ - aoi_input_config_t PT2BC; /*!< Product term 2 input B */ - aoi_input_config_t PT2CC; /*!< Product term 2 input C */ - aoi_input_config_t PT2DC; /*!< Product term 2 input D */ - aoi_input_config_t PT3AC; /*!< Product term 3 input A */ - aoi_input_config_t PT3BC; /*!< Product term 3 input B */ - aoi_input_config_t PT3CC; /*!< Product term 3 input C */ - aoi_input_config_t PT3DC; /*!< Product term 3 input D */ -} aoi_event_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @name AOI Initialization - * @{ - */ - -/*! - * @brief Initializes an AOI instance for operation. - * - * This function un-gates the AOI clock. - * - * @param base AOI peripheral address. - */ -void AOI_Init(AOI_Type *base); - -/*! - * @brief Deinitializes an AOI instance for operation. - * - * This function shutdowns AOI module. - * - * @param base AOI peripheral address. - */ -void AOI_Deinit(AOI_Type *base); - -/*@}*/ - -/*! - * @name AOI Get Set Operation - * @{ - */ - -/*! - * @brief Gets the Boolean evaluation associated. - * - * This function returns the Boolean evaluation associated. - * - * Example: - @code - aoi_event_config_t demoEventLogicStruct; - - AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct); - @endcode - * - * @param base AOI peripheral address. - * @param event Index of the event which will be set of type aoi_event_t. - * @param config Selected input configuration . - */ -void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config); - -/*! - * @brief Configures an AOI event. - * - * This function configures an AOI event according - * to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D) - * of all product terms (0, 1, 2, and 3) of a desired event. - * - * Example: - @code - aoi_event_config_t demoEventLogicStruct; - - demoEventLogicStruct.PT0AC = kAOI_InvInputSignal; - demoEventLogicStruct.PT0BC = kAOI_InputSignal; - demoEventLogicStruct.PT0CC = kAOI_LogicOne; - demoEventLogicStruct.PT0DC = kAOI_LogicOne; - - demoEventLogicStruct.PT1AC = kAOI_LogicZero; - demoEventLogicStruct.PT1BC = kAOI_LogicOne; - demoEventLogicStruct.PT1CC = kAOI_LogicOne; - demoEventLogicStruct.PT1DC = kAOI_LogicOne; - - demoEventLogicStruct.PT2AC = kAOI_LogicZero; - demoEventLogicStruct.PT2BC = kAOI_LogicOne; - demoEventLogicStruct.PT2CC = kAOI_LogicOne; - demoEventLogicStruct.PT2DC = kAOI_LogicOne; - - demoEventLogicStruct.PT3AC = kAOI_LogicZero; - demoEventLogicStruct.PT3BC = kAOI_LogicOne; - demoEventLogicStruct.PT3CC = kAOI_LogicOne; - demoEventLogicStruct.PT3DC = kAOI_LogicOne; - - AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct); - @endcode - * - * @param base AOI peripheral address. - * @param event Event which will be configured of type aoi_event_t. - * @param eventConfig Pointer to type aoi_event_config_t structure. The user is responsible for - * filling out the members of this structure and passing the pointer to this function. - */ -void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*@}*/ - -/*!* @} */ - -#endif /* _FSL_AOI_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache.c deleted file mode 100644 index 6fbd07f753f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache.c +++ /dev/null @@ -1,372 +0,0 @@ -/* - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_cache.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.cache_cache64" -#endif - -#if (FSL_FEATURE_SOC_CACHE64_CTRL_COUNT > 0) -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of CACHE64_CTRL peripheral base address. */ -static CACHE64_CTRL_Type *const s_cache64ctrlBases[] = CACHE64_CTRL_BASE_PTRS; -/* Array of CACHE64_POLSEL peripheral base address. */ -static CACHE64_POLSEL_Type *const s_cache64polselBases[] = CACHE64_POLSEL_BASE_PTRS; - -/* Array of CACHE64 physical memory base address. */ -static uint32_t const s_cache64PhymemBases[] = CACHE64_CTRL_PHYMEM_BASES; -/* Array of CACHE64 physical memory size. */ -static uint32_t const s_cache64PhymemSizes[] = CACHE64_CTRL_PHYMEM_SIZES; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of CACHE64_CTRL clock name. */ -static const clock_ip_name_t s_cache64Clocks[] = CACHE64_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! - * brief Returns an instance number given periphearl base address. - * - * param base The peripheral base address. - * return CACHE64_POLSEL instance number starting from 0. - */ -uint32_t CACHE64_GetInstance(CACHE64_POLSEL_Type *base) -{ - uint32_t i; - - for (i = 0; i < ARRAY_SIZE(s_cache64polselBases); i++) - { - if (base == s_cache64polselBases[i]) - { - break; - } - } - - assert(i < ARRAY_SIZE(s_cache64polselBases)); - - return i; -} -/*! - * brief Returns an instance number given physical memory address. - * - * param address The physical memory address. - * return CACHE64_CTRL instance number starting from 0. - */ -uint32_t CACHE64_GetInstanceByAddr(uint32_t address) -{ - uint32_t i; - - for (i = 0; i < ARRAY_SIZE(s_cache64ctrlBases); i++) - { - if ((address >= s_cache64PhymemBases[i]) && (address < s_cache64PhymemBases[i] + s_cache64PhymemSizes[i])) - { - break; - } - } - - return i; -} - -/*! - * @brief Initializes an CACHE64 instance with the user configuration structure. - * - * This function configures the CACHE64 module with user-defined settings. Call the CACHE64_GetDefaultConfig() function - * to configure the configuration structure and get the default configuration. - * - * @param base CACHE64_POLSEL peripheral base address. - * @param config Pointer to a user-defined configuration structure. - * @retval kStatus_Success CACHE64 initialize succeed - */ -status_t CACHE64_Init(CACHE64_POLSEL_Type *base, const cache64_config_t *config) -{ - volatile uint32_t *topReg = &base->REG0_TOP; - uint32_t i; - uint32_t polsel = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - uint32_t instance = CACHE64_GetInstance(base); - - /* Enable CACHE64 clock */ - CLOCK_EnableClock(s_cache64Clocks[instance]); -#endif - - for (i = 0; i < CACHE64_REGION_NUM - 1U; i++) - { - assert((config->boundaryAddr[i] & (CACHE64_REGION_ALIGNMENT - 1U)) == 0U); - ((volatile uint32_t *)topReg)[i] = config->boundaryAddr[i] >= CACHE64_REGION_ALIGNMENT ? - config->boundaryAddr[i] - CACHE64_REGION_ALIGNMENT : - 0U; - } - - for (i = 0; i < CACHE64_REGION_NUM; i++) - { - polsel |= (((uint32_t)config->policy[i]) << (2U * i)); - } - base->POLSEL = polsel; - - return kStatus_Success; -} - -/*! - * @brief Gets the default configuration structure. - * - * This function initializes the CACHE64 configuration structure to a default value. The default - * values are first region covers whole cacheable area, and policy set to write back. - * - * @param config Pointer to a configuration structure. - */ -void CACHE64_GetDefaultConfig(cache64_config_t *config) -{ - (void)memset(config, 0, sizeof(cache64_config_t)); - - config->boundaryAddr[0] = s_cache64PhymemSizes[0]; - config->policy[0] = kCACHE64_PolicyWriteBack; -} - -/*! - * brief Enables the cache. - * - */ -void CACHE64_EnableCache(CACHE64_CTRL_Type *base) -{ - /* First, invalidate the entire cache. */ - CACHE64_InvalidateCache(base); - - /* Now enable the cache. */ - base->CCR |= CACHE64_CTRL_CCR_ENCACHE_MASK; -} - -/*! - * brief Disables the cache. - * - */ -void CACHE64_DisableCache(CACHE64_CTRL_Type *base) -{ - /* First, push any modified contents. */ - CACHE64_CleanCache(base); - - /* Now disable the cache. */ - base->CCR &= ~CACHE64_CTRL_CCR_ENCACHE_MASK; -} - -/*! - * brief Invalidates the cache. - * - */ -void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base) -{ - /* Invalidate all lines in both ways and initiate the cache command. */ - base->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; - - /* Wait until the cache command completes. */ - while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) - { - } - - /* As a precaution clear the bits to avoid inadvertently re-running this command. */ - base->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK); -} - -/*! - * brief Invalidates cache by range. - * - * param address The physical address of cache. - * param size_byte size of the memory to be invalidated. - * note Address and size should be aligned to "L1CODCACHE_LINESIZE_BYTE". - * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if - * startAddr is not aligned. For the size_byte, application should make sure the - * alignment or make sure the right operation order if the size_byte is not aligned. - */ -void CACHE64_InvalidateCacheByRange(uint32_t address, uint32_t size_byte) -{ - uint32_t endAddr = address + size_byte; - uint32_t pccReg = 0; - /* Align address to cache line size. */ - uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U); - uint32_t instance = CACHE64_GetInstanceByAddr(address); - uint32_t endLim; - CACHE64_CTRL_Type *base; - - if (instance >= ARRAY_SIZE(s_cache64ctrlBases)) - { - return; - } - base = s_cache64ctrlBases[instance]; - endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance]; - endAddr = endAddr > endLim ? endLim : endAddr; - - /* Set the invalidate by line command and use the physical address. */ - pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(1) | CACHE64_CTRL_CLCR_LADSEL_MASK; - base->CLCR = pccReg; - - while (startAddr < endAddr) - { - /* Set the address and initiate the command. */ - base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK; - - /* Wait until the cache command completes. */ - while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U) - { - } - startAddr += (uint32_t)CACHE64_LINESIZE_BYTE; - } -} - -/*! - * brief Cleans the cache. - * - */ -void CACHE64_CleanCache(CACHE64_CTRL_Type *base) -{ - /* Enable the to push all modified lines. */ - base->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_GO_MASK; - - /* Wait until the cache command completes. */ - while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) - { - } - - /* As a precaution clear the bits to avoid inadvertently re-running this command. */ - base->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK); -} - -/*! - * brief Cleans cache by range. - * - * param address The physical address of cache. - * param size_byte size of the memory to be cleaned. - * note Address and size should be aligned to "CACHE64_LINESIZE_BYTE". - * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if - * startAddr is not aligned. For the size_byte, application should make sure the - * alignment or make sure the right operation order if the size_byte is not aligned. - */ -void CACHE64_CleanCacheByRange(uint32_t address, uint32_t size_byte) -{ - uint32_t endAddr = address + size_byte; - uint32_t pccReg = 0; - /* Align address to cache line size. */ - uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U); - uint32_t instance = CACHE64_GetInstanceByAddr(address); - uint32_t endLim; - CACHE64_CTRL_Type *base; - - if (instance >= ARRAY_SIZE(s_cache64ctrlBases)) - { - return; - } - base = s_cache64ctrlBases[instance]; - endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance]; - endAddr = endAddr > endLim ? endLim : endAddr; - - /* Set the push by line command. */ - pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(2) | CACHE64_CTRL_CLCR_LADSEL_MASK; - base->CLCR = pccReg; - - while (startAddr < endAddr) - { - /* Set the address and initiate the command. */ - base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK; - - /* Wait until the cache command completes. */ - while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U) - { - } - startAddr += (uint32_t)CACHE64_LINESIZE_BYTE; - } -} - -/*! - * brief Cleans and invalidates the cache. - * - */ -void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base) -{ - /* Push and invalidate all. */ - base->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK | - CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; - - /* Wait until the cache command completes. */ - while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) - { - } - - /* As a precaution clear the bits to avoid inadvertently re-running this command. */ - base->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK | - CACHE64_CTRL_CCR_INVW1_MASK); -} - -/*! - * brief Cleans and invalidate cache by range. - * - * param address The physical address of cache. - * param size_byte size of the memory to be Cleaned and Invalidated. - * note Address and size should be aligned to "CACHE64_LINESIZE_BYTE". - * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if - * startAddr is not aligned. For the size_byte, application should make sure the - * alignment or make sure the right operation order if the size_byte is not aligned. - */ -void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte) -{ - uint32_t endAddr = address + size_byte; - uint32_t pccReg = 0; - /* Align address to cache line size. */ - uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U); - uint32_t instance = CACHE64_GetInstanceByAddr(address); - uint32_t endLim; - CACHE64_CTRL_Type *base; - - if (instance >= ARRAY_SIZE(s_cache64ctrlBases)) - { - return; - } - base = s_cache64ctrlBases[instance]; - endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance]; - endAddr = endAddr > endLim ? endLim : endAddr; - - /* Set the push by line command. */ - pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(3) | CACHE64_CTRL_CLCR_LADSEL_MASK; - base->CLCR = pccReg; - - while (startAddr < endAddr) - { - /* Set the address and initiate the command. */ - base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK; - - /* Wait until the cache command completes. */ - while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U) - { - } - startAddr += (uint32_t)CACHE64_LINESIZE_BYTE; - } -} - -/*! - * brief Enable the cache write buffer. - * - */ -void CACHE64_EnableWriteBuffer(CACHE64_CTRL_Type *base, bool enable) -{ - if (enable) - { - base->CCR |= CACHE64_CTRL_CCR_ENWRBUF_MASK; - } - else - { - base->CCR &= ~CACHE64_CTRL_CCR_ENWRBUF_MASK; - } -} - -#endif /* FSL_FEATURE_SOC_CACHE64_CTRL_COUNT > 0 */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache.h deleted file mode 100644 index 3e708ae4546..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache.h +++ /dev/null @@ -1,267 +0,0 @@ -/* - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CACHE_H_ -#define _FSL_CACHE_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup cache64 - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief cache driver version 2.0.4. */ -#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) -/*@}*/ - -/*! @brief cache line size. */ -#define CACHE64_LINESIZE_BYTE (FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE) -/*! @brief cache region number. */ -#define CACHE64_REGION_NUM (3U) -/*! @brief cache region alignment. */ -#define CACHE64_REGION_ALIGNMENT (0x400U) - -/*! @brief Level 2 cache controller way size. */ -typedef enum _cache64_policy -{ - kCACHE64_PolicyNonCacheable = 0, /*!< Non-cacheable */ - kCACHE64_PolicyWriteThrough = 1, /*!< Write through */ - kCACHE64_PolicyWriteBack = 2, /*!< Write back */ -} cache64_policy_t; - -/*! @brief CACHE64 configuration structure. */ -typedef struct _cache64_config -{ - /*!< The cache controller can divide whole memory into 3 regions. - * Boundary address is the FlexSPI internal address (start from 0) instead of system - * address (start from FlexSPI AMBA base) to split adjacent regions and must be 1KB - * aligned. The boundary address itself locates in upper region. */ - uint32_t boundaryAddr[CACHE64_REGION_NUM - 1]; - /*!< Cacheable policy for each region. */ - cache64_policy_t policy[CACHE64_REGION_NUM]; -} cache64_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name cache control for cache64 - *@{ - */ - -/*! - * @brief Returns an instance number given periphearl base address. - * - * @param base The peripheral base address. - * @return CACHE64_POLSEL instance number starting from 0. - */ -uint32_t CACHE64_GetInstance(CACHE64_POLSEL_Type *base); - -/*! - * brief Returns an instance number given physical memory address. - * - * param address The physical memory address. - * @return CACHE64_CTRL instance number starting from 0. - */ -uint32_t CACHE64_GetInstanceByAddr(uint32_t address); - -/*! - * @brief Initializes an CACHE64 instance with the user configuration structure. - * - * This function configures the CACHE64 module with user-defined settings. Call the CACHE64_GetDefaultConfig() function - * to configure the configuration structure and get the default configuration. - * - * @param base CACHE64_POLSEL peripheral base address. - * @param config Pointer to a user-defined configuration structure. - * @retval kStatus_Success CACHE64 initialize succeed - */ -status_t CACHE64_Init(CACHE64_POLSEL_Type *base, const cache64_config_t *config); - -/*! - * @brief Gets the default configuration structure. - * - * This function initializes the CACHE64 configuration structure to a default value. The default - * values are first region covers whole cacheable area, and policy set to write back. - * - * @param config Pointer to a configuration structure. - */ -void CACHE64_GetDefaultConfig(cache64_config_t *config); - -/*! - * @brief Enables the cache. - * - * @param base CACHE64_CTRL peripheral base address. - * - */ -void CACHE64_EnableCache(CACHE64_CTRL_Type *base); - -/*! - * @brief Disables the cache. - * - * @param base CACHE64_CTRL peripheral base address. - * - */ -void CACHE64_DisableCache(CACHE64_CTRL_Type *base); - -/*! - * @brief Invalidates the cache. - * - * @param base CACHE64_CTRL peripheral base address. - * - */ -void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base); - -/*! - * @brief Invalidates cache by range. - * - * @param address The physical address of cache. - * @param size_byte size of the memory to be invalidated. - * @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE". - * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if - * startAddr is not aligned. For the size_byte, application should make sure the - * alignment or make sure the right operation order if the size_byte is not aligned. - */ -void CACHE64_InvalidateCacheByRange(uint32_t address, uint32_t size_byte); - -/*! - * @brief Cleans the cache. - * - * @param base CACHE64_CTRL peripheral base address. - * - */ -void CACHE64_CleanCache(CACHE64_CTRL_Type *base); - -/*! - * @brief Cleans cache by range. - * - * @param address The physical address of cache. - * @param size_byte size of the memory to be cleaned. - * @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE". - * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if - * startAddr is not aligned. For the size_byte, application should make sure the - * alignment or make sure the right operation order if the size_byte is not aligned. - */ -void CACHE64_CleanCacheByRange(uint32_t address, uint32_t size_byte); - -/*! - * @brief Cleans and invalidates the cache. - * - * @param base CACHE64_CTRL peripheral base address. - * - */ -void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base); - -/*! - * @brief Cleans and invalidate cache by range. - * - * @param address The physical address of cache. - * @param size_byte size of the memory to be Cleaned and Invalidated. - * @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE". - * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if - * startAddr is not aligned. For the size_byte, application should make sure the - * alignment or make sure the right operation order if the size_byte is not aligned. - */ -void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte); - -/*! - * @brief Enables/disables the write buffer. - * - * @param base CACHE64_CTRL peripheral base address. - * @param enable The enable or disable flag. - * true - enable the write buffer. - * false - disable the write buffer. - */ -void CACHE64_EnableWriteBuffer(CACHE64_CTRL_Type *base, bool enable); - -/*@}*/ - -/*! - * @name Unified Cache Control for all caches - *@{ - */ - -/*! - * @brief Invalidates instruction cache by range. - * - * @param address The physical address. - * @param size_byte size of the memory to be invalidated. - * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit - * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line - * size if startAddr is not aligned. For the size_byte, application should make sure the - * alignment or make sure the right operation order if the size_byte is not aligned. - */ -static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) -{ - CACHE64_InvalidateCacheByRange(address, size_byte); -} - -/*! - * @brief Invalidates data cache by range. - * - * @param address The physical address. - * @param size_byte size of the memory to be invalidated. - * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit - * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line - * size if startAddr is not aligned. For the size_byte, application should make sure the - * alignment or make sure the right operation order if the size_byte is not aligned. - */ -static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) -{ - CACHE64_InvalidateCacheByRange(address, size_byte); -} - -/*! - * @brief Clean data cache by range. - * - * @param address The physical address. - * @param size_byte size of the memory to be cleaned. - * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit - * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line - * size if startAddr is not aligned. For the size_byte, application should make sure the - * alignment or make sure the right operation order if the size_byte is not aligned. - */ -static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte) -{ - CACHE64_CleanCacheByRange(address, size_byte); -} - -/*! - * @brief Cleans and Invalidates data cache by range. - * - * @param address The physical address. - * @param size_byte size of the memory to be Cleaned and Invalidated. - * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit - * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line - * size if startAddr is not aligned. For the size_byte, application should make sure the - * alignment or make sure the right operation order if the size_byte is not aligned. - */ -static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte) -{ - CACHE64_CleanInvalidateCacheByRange(address, size_byte); -} - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_CACHE_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache_n4a.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache_n4a.c deleted file mode 100644 index 376cbea6110..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache_n4a.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_cache_n4a.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.cache_lpcac" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache_n4a.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache_n4a.h deleted file mode 100644 index 61f763be8a6..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache_n4a.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_CACHE_H_ -#define _FSL_CACHE_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup cache_lpcac - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief cache driver version */ -#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name cache control for the L1 low power cache controller - *@{ - */ - -/*! - * @brief Enables the processor code bus cache. - * - */ -static inline void L1CACHE_EnableCodeCache(void) -{ - SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; -} - -/*! - * @brief Disables the processor code bus cache. - * - */ -static inline void L1CACHE_DisableCodeCache(void) -{ - SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; -} - -/*! - * @brief Clears cache. - * - */ -static inline void L1CACHE_InvalidateCodeCache(void) -{ - SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK; -} - -/*! - * @brief Enables allocation. - * - */ -static inline void L1CACHE_EnableAllocation(void) -{ - SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK; -} - -/*! - * @brief Disables allocation. - * - */ -static inline void L1CACHE_DisableAllocation(void) -{ - SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK; -} - -/*! - * @brief Enables parity. - * - */ -static inline void L1CACHE_EnableParity(void) -{ - SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK; -} - -/*! - * @brief Disable parity. - * - */ -static inline void L1CACHE_DisableParity(void) -{ - SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK; -} - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_CACHE_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cdog.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cdog.c deleted file mode 100644 index e06c1b6274e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cdog.c +++ /dev/null @@ -1,310 +0,0 @@ -/* - * Copyright 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_cdog.h" - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.cdog" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Sets the default configuration of CDOG - * - * This function initialize CDOG config structure to default values. - * - * param conf CDOG configuration structure - */ -void CDOG_GetDefaultConfig(cdog_config_t *conf) -{ - /* Default configuration after reset */ - conf->lock = (uint8_t)kCDOG_LockCtrl_Unlock; /* Lock control */ - conf->timeout = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Timeout control */ - conf->miscompare = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Miscompare control */ - conf->sequence = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Sequence control */ - conf->state = (uint8_t)kCDOG_FaultCtrl_NoAction; /* State control */ - conf->address = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Address control */ - conf->irq_pause = (uint8_t)kCDOG_IrqPauseCtrl_Run; /* IRQ pause control */ - conf->debug_halt = (uint8_t)kCDOG_DebugHaltCtrl_Run; /* Debug halt control */ - return; -} - -/*! - * brief Sets secure counter and instruction timer values - * - * This function sets value in RELOAD and START registers for instruction timer. - * - * param base CDOG peripheral base address - * param reload reload value - * param start start value - */ -void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start) -{ - base->RELOAD = reload; - base->START = start; -} - -/*! - * brief Stops secure counter and instruction timer - * - * This function stops instruction timer and secure counter. - * This also change state of CDOG to IDLE. - * - * param base CDOG peripheral base address - * param stop expected value which will be compared with value of secure counter - */ -void CDOG_Stop(CDOG_Type *base, uint32_t stop) -{ - base->STOP = stop; -} - -/*! - * brief Sets secure counter and instruction timer values - * - * This function sets value in STOP, RELOAD and START registers - * for instruction timer and secure counter. - * - * param base CDOG peripheral base address - * param stop expected value which will be compared with value of secure counter - * param reload reload value for instruction timer - * param start start value for secure timer - */ -void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start) -{ - base->STOP = stop; - base->RELOAD = reload; - base->START = start; -} - -/*! - * brief Add value to secure counter - * - * This function add specified value to secure counter. - * - * param base CDOG peripheral base address. - * param add Value to be added. - */ -void CDOG_Add(CDOG_Type *base, uint32_t add) -{ - base->ADD = (secure_counter_t)add; -} - -/*! - * brief Add 1 to secure counter - * - * This function add 1 to secure counter. - * - * param base CDOG peripheral base address. - * param add Value to be added. - */ -void CDOG_Add1(CDOG_Type *base) -{ - base->ADD1 = (secure_counter_t)0x1U; -} - -/*! - * brief Add 16 to secure counter - * - * This function add 16 to secure counter. - * - * param base CDOG peripheral base address. - * param add Value to be added. - */ -void CDOG_Add16(CDOG_Type *base) -{ - base->ADD16 = (secure_counter_t)0x1U; -} - -/*! - * brief Add 256 to secure counter - * - * This function add 256 to secure counter. - * - * param base CDOG peripheral base address. - * param add Value to be added. - */ -void CDOG_Add256(CDOG_Type *base) -{ - base->ADD256 = (secure_counter_t)0x1U; -} - -/*! - * brief Substract value to secure counter - * - * This function substract specified value to secure counter. - * - * param base CDOG peripheral base address. - * param sub Value to be substracted. - */ -void CDOG_Sub(CDOG_Type *base, uint32_t sub) -{ - base->SUB = (secure_counter_t)sub; -} - -/*! - * brief Substract 1 from secure counter - * - * This function substract specified 1 from secure counter. - * - * param base CDOG peripheral base address. - */ -void CDOG_Sub1(CDOG_Type *base) -{ - base->SUB1 = (secure_counter_t)0x1U; -} - -/*! - * brief Substract 16 from secure counter - * - * This function substract specified 16 from secure counter. - * - * param base CDOG peripheral base address. - */ -void CDOG_Sub16(CDOG_Type *base) -{ - base->SUB16 = (secure_counter_t)0x1U; -} - -/*! - * brief Substract 256 from secure counter - * - * This function substract specified 256 from secure counter. - * - * param base CDOG peripheral base address. - */ -void CDOG_Sub256(CDOG_Type *base) -{ - base->SUB256 = (secure_counter_t)0x1U; -} - -/*! - * brief Checks secure counter. - * - * This function compares stop value with secure counter value - * by writting to RELOAD refister. - * - * param base CDOG peripheral base address - * param check expected (stop) value. - */ -void CDOG_Check(CDOG_Type *base, uint32_t check) -{ - base->RESTART = check; -} - -/*! - * brief Set the CDOG persistent word. - * - * param base CDOG peripheral base address. - * param value The value to be written. - */ -void CDOG_WritePersistent(CDOG_Type *base, uint32_t value) -{ - base->PERSISTENT = value; -} - -/*! - * brief Get the CDOG persistent word. - * - * param base CDOG peripheral base address. - * return The persistent word. - */ -uint32_t CDOG_ReadPersistent(CDOG_Type *base) -{ - return base->PERSISTENT; -} - -/*! - * brief Initialize CDOG - * - * This function initializes CDOG block and setting. - * - * param base CDOG peripheral base address - * param conf CDOG configuration structure - * return Status of the init operation - */ -status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf) -{ - /* Ungate clock to CDOG engine and reset it */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Cdog); -#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET) - RESET_PeripheralReset(kCDOG_RST_SHIFT_RSTn); -#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */ - - if (base->CONTROL == 0x0U) - { - /* CDOG is not in IDLE mode, which may be cause after SW reset. */ - /* Writing to CONTROL register will trigger fault. */ - return kStatus_Fail; - } - - /* Clear pending errors, otherwise the device will reset */ - /* itself immediately after enable Code Watchdog */ - if ((uint32_t)kCDOG_LockCtrl_Lock == - ((base->CONTROL & CDOG_CONTROL_LOCK_CTRL_MASK) >> CDOG_CONTROL_LOCK_CTRL_SHIFT)) - - { - CDOG->FLAGS = CDOG_FLAGS_TO_FLAG(1U) | CDOG_FLAGS_MISCOM_FLAG(1U) | CDOG_FLAGS_SEQ_FLAG(1U) | - CDOG_FLAGS_CNT_FLAG(1U) | CDOG_FLAGS_STATE_FLAG(1U) | CDOG_FLAGS_ADDR_FLAG(1U) | - CDOG_FLAGS_POR_FLAG(1U); - } - else - { - CDOG->FLAGS = CDOG_FLAGS_TO_FLAG(0U) | CDOG_FLAGS_MISCOM_FLAG(0U) | CDOG_FLAGS_SEQ_FLAG(0U) | - CDOG_FLAGS_CNT_FLAG(0U) | CDOG_FLAGS_STATE_FLAG(0U) | CDOG_FLAGS_ADDR_FLAG(0U) | - CDOG_FLAGS_POR_FLAG(0U); - } - - base->CONTROL = - CDOG_CONTROL_TIMEOUT_CTRL(conf->timeout) | /* Action if the timeout event is triggered */ - CDOG_CONTROL_MISCOMPARE_CTRL(conf->miscompare) | /* Action if the miscompare error event is triggered */ - CDOG_CONTROL_SEQUENCE_CTRL(conf->sequence) | /* Action if the sequence error event is triggered */ - CDOG_CONTROL_STATE_CTRL(conf->state) | /* Action if the state error event is triggered */ - CDOG_CONTROL_ADDRESS_CTRL(conf->address) | /* Action if the address error event is triggered */ - CDOG_CONTROL_IRQ_PAUSE(conf->irq_pause) | /* Pause running during interrupts setup */ - CDOG_CONTROL_DEBUG_HALT_CTRL( - conf->debug_halt) | /* Halt CDOG timer during debug so we have chance to debug code */ - CDOG_CONTROL_LOCK_CTRL(conf->lock); /* Lock control register */ - - NVIC_EnableIRQ(CDOG_IRQn); - - return kStatus_Success; -} - -/*! - * brief Deinitialize CDOG - * - * This function stops CDOG secure counter. - * - * param base CDOG peripheral base address - */ -void CDOG_Deinit(CDOG_Type *base) -{ - NVIC_DisableIRQ(CDOG_IRQn); - -#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET) - RESET_SetPeripheralReset(kCDOG_RST_SHIFT_RSTn); -#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Cdog); -#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cdog.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cdog.h deleted file mode 100644 index b93c8dbdfe7..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cdog.h +++ /dev/null @@ -1,325 +0,0 @@ -/* - * Copyright 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_CDOG_H_ -#define _FSL_CDOG_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup CDOG - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Defines CDOG driver version 2.1.1. - * - * Change log: - * - Version 2.1.1 - * - Remove bit CONTROL[CONTROL_CTRL] - * - Version 2.1.0 - * - Rename CWT to CDOG - * - Version 2.0.2 - * - Fix MISRA-2012 issues - * - Version 2.0.1 - * - Fix doxygen issues - * - Version 2.0.0 - * - initial version - */ -#define FSL_CDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) -/*@}*/ - -typedef struct -{ - uint8_t lock : 2; - uint8_t timeout : 3; - uint8_t miscompare : 3; - uint8_t sequence : 3; - uint8_t state : 3; - uint8_t address : 3; - uint8_t reserved : 8; - uint8_t irq_pause : 2; - uint8_t debug_halt : 2; -} cdog_config_t; - -enum __cdog_debug_Action_ctrl_enum -{ - kCDOG_DebugHaltCtrl_Run = 0x1, - kCDOG_DebugHaltCtrl_Pause = 0x2, -}; - -enum __cdog_irq_pause_ctrl_enum -{ - kCDOG_IrqPauseCtrl_Run = 0x1, - kCDOG_IrqPauseCtrl_Pause = 0x2, -}; - -enum __cdog_fault_ctrl_enum -{ - kCDOG_FaultCtrl_EnableReset = 0x1U, - kCDOG_FaultCtrl_EnableInterrupt = 0x2U, - kCDOG_FaultCtrl_NoAction = 0x4U, -}; - -enum __code_lock_ctrl_enum -{ - kCDOG_LockCtrl_Lock = 0x1, - kCDOG_LockCtrl_Unlock = 0x2, -}; - -typedef uint32_t secure_counter_t; - -#define SC_ADD(add) \ - do \ - { \ - CDOG->ADD = (secure_counter_t)(add); \ - } while (0) - -#define SC_ADD1 \ - do \ - { \ - CDOG->ADD1 = (secure_counter_t)0x1U; \ - } while (0) - -#define SC_ADD16 \ - do \ - { \ - CDOG->ADD16 = (secure_counter_t)0x1U; \ - } while (0) - -#define SC_ADD256 \ - do \ - { \ - CDOG->ADD256 = (secure_counter_t)0x1U; \ - } while (0) - -#define SC_SUB(sub) \ - do \ - { \ - CDOG->SUB = (secure_counter_t)(sub); \ - } while (0) - -#define SC_SUB1 \ - do \ - { \ - CDOG->SUB1 = (secure_counter_t)0x1U; \ - } while (0) - -#define SC_SUB16 \ - do \ - { \ - CDOG->SUB16 = (secure_counter_t)0x1U; \ - } while (0) - -#define SC_SUB256 \ - do \ - { \ - CDOG->SUB256 = (secure_counter_t)0x1U; \ - } while (0) - -#define SC_CHECK(val) \ - do \ - { \ - CDOG->RESTART = (secure_counter_t)val; \ - } while (0) - -/******************************************************************************* - * API - *******************************************************************************/ - -extern void CDOG_DriverIRQHandler(void); - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name CDOG Functional Operation - * @{ - */ - -/*! - * @brief Initialize CDOG - * - * This function initializes CDOG block and setting. - * - * @param base CDOG peripheral base address - * @param conf CDOG configuration structure - * @return Status of the init operation - */ -status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf); - -/*! - * @brief Deinitialize CDOG - * - * This function deinitializes CDOG secure counter. - * - * @param base CDOG peripheral base address - */ -void CDOG_Deinit(CDOG_Type *base); - -/*! - * @brief Sets the default configuration of CDOG - * - * This function initialize CDOG config structure to default values. - * - * @param conf CDOG configuration structure - */ -void CDOG_GetDefaultConfig(cdog_config_t *conf); - -/*! - * @brief Stops secure counter and instruction timer - * - * This function stops instruction timer and secure counter. - * This also change state od CDOG to IDLE. - * - * @param base CDOG peripheral base address - * @param stop expected value which will be compared with value of secure counter - */ -void CDOG_Stop(CDOG_Type *base, uint32_t stop); - -/*! - * @brief Sets secure counter and instruction timer values - * - * This function sets value in RELOAD and START registers - * for instruction timer and secure counter - * - * @param base CDOG peripheral base address - * @param reload reload value - * @param start start value - */ -void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start); - -/*! - * @brief Checks secure counter. - * - * This function compares stop value in handler with secure counter value - * by writting to RELOAD refister. - * - * @param base CDOG peripheral base address - * @param check expected (stop) value - */ -void CDOG_Check(CDOG_Type *base, uint32_t check); - -/*! - * @brief Sets secure counter and instruction timer values - * - * This function sets value in STOP, RELOAD and START registers - * for instruction timer and secure counter. - * - * @param base CDOG peripheral base address - * @param stop expected value which will be compared with value of secure counter - * @param reload reload value for instruction timer - * @param start start value for secure timer - */ -void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start); - -/*! - * @brief Add value to secure counter - * - * This function add specified value to secure counter. - * - * @param base CDOG peripheral base address. - * @param add Value to be added. - */ -void CDOG_Add(CDOG_Type *base, uint32_t add); - -/*! - * @brief Add 1 to secure counter - * - * This function add 1 to secure counter. - * - * @param base CDOG peripheral base address. - */ -void CDOG_Add1(CDOG_Type *base); - -/*! - * @brief Add 16 to secure counter - * - * This function add 16 to secure counter. - * - * @param base CDOG peripheral base address. - */ -void CDOG_Add16(CDOG_Type *base); - -/*! - * @brief Add 256 to secure counter - * - * This function add 256 to secure counter. - * - * @param base CDOG peripheral base address. - */ -void CDOG_Add256(CDOG_Type *base); - -/*! - * brief Substract value to secure counter - * - * This function substract specified value to secure counter. - * - * param base CDOG peripheral base address. - * param sub Value to be substracted. - */ -void CDOG_Sub(CDOG_Type *base, uint32_t sub); - -/*! - * @brief Substract 1 from secure counter - * - * This function substract specified 1 from secure counter. - * - * @param base CDOG peripheral base address. - */ -void CDOG_Sub1(CDOG_Type *base); - -/*! - * @brief Substract 16 from secure counter - * - * This function substract specified 16 from secure counter. - * - * @param base CDOG peripheral base address. - */ -void CDOG_Sub16(CDOG_Type *base); - -/*! - * @brief Substract 256 from secure counter - * - * This function substract specified 256 from secure counter. - * - * @param base CDOG peripheral base address. - */ -void CDOG_Sub256(CDOG_Type *base); - -/*! - * @brief Set the CDOG persistent word. - * - * @param base CDOG peripheral base address. - * @param value The value to be written. - */ -void CDOG_WritePersistent(CDOG_Type *base, uint32_t value); - -/*! - * @brief Get the CDOG persistent word. - * - * @param base CDOG peripheral base address. - * @return The persistent word. - */ -uint32_t CDOG_ReadPersistent(CDOG_Type *base); - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ /* end of group cdog */ - -#endif /* _FSL_CDOG_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_clock.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_clock.c deleted file mode 100644 index 0e66bf5b601..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_clock.c +++ /dev/null @@ -1,2447 +0,0 @@ -/* - * Copyright 2017 - 2020 , NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_clock.h" -#include "fsl_power.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.clock" -#endif -#define NVALMAX (0x100U) -#define PVALMAX (0x20U) -#define MVALMAX (0x10000U) - -#define PLL_MAX_N_DIV 0x100U - -/*-------------------------------------------------------------------------- -!!! If required these #defines can be moved to chip library file -----------------------------------------------------------------------------*/ - -#define PLL_SSCG1_MDEC_VAL_P (10U) /* MDEC is in bits 25 downto 10 */ -#define PLL_SSCG1_MDEC_VAL_M (0xFFFFULL << PLL_SSCG1_MDEC_VAL_P) -#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */ -#define PLL_NDEC_VAL_M (0xFFUL << PLL_NDEC_VAL_P) -#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */ -#define PLL_PDEC_VAL_M (0x1FUL << PLL_PDEC_VAL_P) - -#define PLL_MIN_CCO_FREQ_MHZ (275000000U) -#define PLL_MAX_CCO_FREQ_MHZ (550000000U) -#define PLL_LOWER_IN_LIMIT (2000U) /*!< Minimum PLL input rate */ -#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */ -#define PLL_MIN_IN_SSMODE (3000000U) -#define PLL_MAX_IN_SSMODE \ - (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */ - -/* PLL NDEC reg */ -#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) -/* PLL PDEC reg */ -#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M) -/* SSCG control1 */ -#define PLL_SSCG1_MDEC_VAL_SET(value) (((uint64_t)(value) << PLL_SSCG1_MDEC_VAL_P) & PLL_SSCG1_MDEC_VAL_M) - -/* PLL0 SSCG control1 */ -#define PLL0_SSCG_MD_FRACT_P 0U -#define PLL0_SSCG_MD_INT_P 25U -#define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) -#define PLL0_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL0_SSCG_MD_INT_P) - -#define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_FRACT_M) -#define PLL0_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_INT_P) & PLL0_SSCG_MD_INT_M) - -/* Peripheral FLASH_NMPA base address */ -#define FLASH_NMPA_BASE (0x3FC00u) -/* Return values from Config (N-2) page of flash */ -#define GET_HFXO_TRIM() (*(uint32_t *)(FLASH_NMPA_BASE + 0xC0U)) // (0x3FCC0) -#define GET_32KXO_TRIM() (*(uint32_t *)(FLASH_NMPA_BASE + 0xC4U)) // (0x3FCC4) - -#define XO_SLAVE_EN (1) - -/* Saved value of PLL output rate, computed whenever needed to save run-time - computation on each call to retrive the PLL rate. */ -static uint32_t s_Pll0_Freq; -static uint32_t s_Pll1_Freq; - -/** External clock rate on the CLKIN pin in Hz. If not used, - set this to 0. Otherwise, set it to the exact rate in Hz this pin is - being driven at. */ -static uint32_t s_Ext_Clk_Freq = 16000000U; -static uint32_t s_I2S_Mclk_Freq = 0U; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ -static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); -/* Get predivider (N) from PLL0 NDEC setting */ -static uint32_t findPll0PreDiv(void); -/* Get predivider (N) from PLL1 NDEC setting */ -static uint32_t findPll1PreDiv(void); -/* Get postdivider (P) from PLL0 PDEC setting */ -static uint32_t findPll0PostDiv(void); -/* Get postdivider (P) from PLL1 PDEC setting. */ -static uint32_t findPll1PostDiv(void); -/* Get multiplier (M) from PLL0 MDEC and SSCG settings */ -static float findPll0MMult(void); -/* Get multiplier (M) from PLL1 MDEC. */ -static uint32_t findPll1MMult(void); -/* Get the greatest common divisor */ -static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); -/* Set PLL output based on desired output rate */ -static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS); -/* Update local PLL rate variable */ -static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup); -/* Update local PLL1 rate variable */ -static void CLOCK_GetPLL1OutFromSetupUpdate(pll_setup_t *pSetup); -/* Compensate for discontinuity in the capacitor banks */ -static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity); -/* Enables and sets LDO for High Frequency crystal oscillator */ -static void CLOCK_SetXtalHfLdo(void); - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Clock Selection for IP */ -/** - * brief Configure the clock selection muxes. - * param connection : Clock to be configured. - * return Nothing - */ -void CLOCK_AttachClk(clock_attach_id_t connection) -{ - uint16_t mux; - uint8_t sel; - uint16_t item; - uint32_t tmp32 = (uint32_t)connection; - uint32_t i; - volatile uint32_t *pClkSel; - - pClkSel = &(SYSCON->SYSTICKCLKSEL0); - - if (kNONE_to_NONE != connection) - { - for (i = 0U; i < 2U; i++) - { - if (tmp32 == 0U) - { - break; - } - item = (uint16_t)GET_ID_ITEM(tmp32); - if (item != 0U) - { - mux = (uint16_t)GET_ID_ITEM_MUX(item); - sel = (uint8_t)GET_ID_ITEM_SEL(item); - if (mux == CM_RTCOSC32KCLKSEL) - { - PMC->RTCOSC32K = (PMC->RTCOSC32K & ~PMC_RTCOSC32K_SEL_MASK) | PMC_RTCOSC32K_SEL(sel); - } - else if (mux == CM_OSTIMERCLKSEL) - { - PMC->OSEVENTTIMER = - (PMC->OSEVENTTIMER & ~PMC_OSEVENTTIMER_SELCLOCK_MASK) | PMC_OSEVENTTIMER_SELCLOCK(sel); - } - else - { - ((volatile uint32_t *)pClkSel)[mux] = sel; - } - } - tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */ - } - } -} - -/* Return the actual clock attach id */ -/** - * brief Get the actual clock attach id. - * This fuction uses the offset in input attach id, then it reads the actual source value in - * the register and combine the offset to obtain an actual attach id. - * param attachId : Clock attach id to get. - * return Clock source value. - */ -clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId) -{ - uint16_t mux; - uint32_t actualSel; - uint32_t tmp32 = (uint32_t)attachId; - uint32_t i; - uint32_t actualAttachId = 0U; - uint32_t selector = GET_ID_SELECTOR(tmp32); - volatile uint32_t *pClkSel; - - pClkSel = &(SYSCON->SYSTICKCLKSEL0); - - if (kNONE_to_NONE == attachId) - { - return kNONE_to_NONE; - } - - for (i = 0U; i < 2U; i++) - { - mux = (uint16_t)GET_ID_ITEM_MUX(tmp32); - if (tmp32 != 0UL) - { - if (mux == CM_RTCOSC32KCLKSEL) - { - actualSel = ((PMC->RTCOSC32K) & PMC_RTCOSC32K_SEL_MASK) >> PMC_RTCOSC32K_SEL_SHIFT; - } - else if (mux == CM_OSTIMERCLKSEL) - { - actualSel = ((PMC->OSEVENTTIMER) & PMC_OSEVENTTIMER_SELCLOCK_MASK) >> PMC_OSEVENTTIMER_SELCLOCK_SHIFT; - } - else - { - actualSel = (uint32_t)((volatile uint32_t *)pClkSel)[mux]; - } - - /* Consider the combination of two registers */ - actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i); - } - tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */ - } - - actualAttachId |= selector; - - return (clock_attach_id_t)actualAttachId; -} - -/* Set IP Clock Divider */ -/** - * brief Setup peripheral clock dividers. - * param div_name : Clock divider name - * param divided_by_value: Value to be divided - * param reset : Whether to reset the divider counter. - * return Nothing - */ -void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) -{ - volatile uint32_t *pClkDiv; - - pClkDiv = &(SYSCON->SYSTICKCLKDIV[0]); - if ((div_name >= kCLOCK_DivFlexFrg0) && (div_name <= kCLOCK_DivFlexFrg7)) - { - /*!< Flexcomm Interface function clock = (clock selected via FCCLKSEL) / (1+ MULT /DIV), DIV = 0xFF */ - ((volatile uint32_t *)pClkDiv)[(uint16_t)div_name] = - SYSCON_FRGCTRL_DIV_MASK | SYSCON_FRGCTRL_MULT(divided_by_value); - } - else - { - if (reset) - { - ((volatile uint32_t *)pClkDiv)[(uint16_t)div_name] = 1UL << 29U; - } - if (divided_by_value == 0U) /*!< halt */ - { - ((volatile uint32_t *)pClkDiv)[(uint16_t)div_name] = 1UL << 30U; - } - else - { - ((volatile uint32_t *)pClkDiv)[(uint16_t)div_name] = (divided_by_value - 1U); - } - } -} - -/* Set FRO Clocking */ -/** - * brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). - * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is - * enabled. - * param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ) - * return returns success or fail status. - */ -status_t CLOCK_SetupFROClocking(uint32_t iFreq) -{ - if ((iFreq != 12000000U) && (iFreq != 96000000U)) - { - return kStatus_Fail; - } - /* Enable Analog Control module */ - SYSCON->PRESETCTRLCLR[2] = SYSCON_PRESETCTRL2_ANACTRL_RST_MASK; - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK; - - /* Initialize FRO192 trim */ - CLOCK_FroHfTrim(); - - /* Power up the FRO192M */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); - - if (iFreq == 96000000U) - { - ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(1); - } - /* always enable - else if (iFreq == 48000000U) - { - ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(1); - }*/ - else - { - ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(1); - } - return kStatus_Success; -} - -/* Set the FLASH wait states for the passed frequency */ -/** - * brief Set the flash wait states for the input freuqency. - * param iFreq: Input frequency - * return Nothing - */ -typedef struct -{ - uint32_t waitstate; - uint32_t freqMax; -} WaitStateInterval_t; - -/* clang-format off */ -/* Wait state if frequency is inferior to the one specified */ -static const WaitStateInterval_t IntervalList[] = { - {0, 11000000}, - {1, 22000000}, - {2, 33000000}, - {3, 44000000}, - {4, 55000000}, - {5, 66000000}, - {6, 77000000}, - {7, 88000000}, - {8, 100000000}, - {11, 130000000}, - {12, 150000000} /* Maximum allowed frequency (150 MHz) */ -}; -/* clang-format on */ - -void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz) -{ - /* Flash Controller & FMC internal number of Wait States (minus 1) */ - uint32_t num_wait_states = 15UL; /* Default to the maximum number of wait states */ - - for (size_t cnt = 0; cnt < (sizeof(IntervalList) / sizeof(WaitStateInterval_t)); cnt++) - { - if (system_freq_hz <= IntervalList[cnt].freqMax) - { - num_wait_states = IntervalList[cnt].waitstate; - break; - } - } - - FLASH->INTSTAT_CLR = 0xF; /* Clear all status flags */ - - FLASH->DATAW[0] = (FLASH->DATAW[0] & 0xFFFFFFF0UL) | (num_wait_states & 0xFUL); - - FLASH->CMD = 0x2; /* CMD_SET_READ_MODE */ - - /* Wait until the cmd is completed (without error) */ - while ((FLASH->INTSTAT & FLASH_INTSTAT_DONE_MASK) == 0UL) - { - } - - /* Adjust FMC waiting time cycles (num_wait_states) */ - SYSCON->FMCCR = (SYSCON->FMCCR & 0xFFFF0FFFUL) | ((num_wait_states & 0xFUL) << 12UL); -} - -/* Set EXT OSC Clk */ -/** - * brief Initialize the external osc clock to given frequency. - * param iFreq : Desired frequency (must be equal to exact rate in Hz) - * return returns success or fail status. - */ -status_t CLOCK_SetupExtClocking(uint32_t iFreq) -{ - if (iFreq >= 32000000U) - { - return kStatus_Fail; - } - /* Turn on power for crystal 32 MHz */ - POWER_DisablePD(kPDRUNCFG_PD_XTALHF); - POWER_DisablePD(kPDRUNCFG_PD_LDOXTALHF); - /* Enable clock_in clock for clock module. */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; - - s_Ext_Clk_Freq = iFreq; - return kStatus_Success; -} - -/* Set I2S MCLK Clk */ -/** - * brief Initialize the I2S MCLK clock to given frequency. - * param iFreq : Desired frequency (must be equal to exact rate in Hz) - * return returns success or fail status. - */ -status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq) -{ - s_I2S_Mclk_Freq = iFreq; - return kStatus_Success; -} - -/* Get CLOCK OUT Clk */ -/*! brief Return Frequency of ClockOut - * return Frequency of ClockOut - */ -uint32_t CLOCK_GetClockOutClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->CLKOUTSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - - case 2U: - freq = CLOCK_GetExtClkFreq(); - break; - - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - - case 5U: - freq = CLOCK_GetPll1OutFreq(); - break; - - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U); -} - -/* Get CAN Clk */ -/*! brief Return Frequency of Can Clock - * return Frequency of Can. - */ -uint32_t CLOCK_GetMCanClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->CANCLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CANCLKDIV & SYSCON_CANCLKDIV_DIV_MASK) + 1U); - break; - case 1U: - freq = CLOCK_GetFro1MFreq(); - break; - case 2U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq; -} - -/* Get ADC Clk */ -/*! brief Return Frequency of Adc Clock - * return Frequency of Adc. - */ -uint32_t CLOCK_GetAdcClkFreq(uint32_t id) -{ - uint32_t freq = 0U; - uint32_t div = 0U; - - switch ((id == 0) ? (SYSCON->ADC0CLKSEL) : (SYSCON->ADC1CLKSEL)) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 2U: - freq = CLOCK_GetFroHfFreq(); - break; - default: - freq = 0U; - break; - } - - div = ((id == 0) ? ((SYSCON->ADC0CLKDIV & SYSCON_ADC0CLKDIV_DIV_MASK) + 1U) : - ((SYSCON->ADC1CLKDIV & SYSCON_ADC1CLKDIV_DIV_MASK) + 1U)); - - return freq / div; -} - -/* Get USB0 Clk */ -/*! brief Return Frequency of Usb0 Clock - * return Frequency of Usb0 Clock. - */ -uint32_t CLOCK_GetUsb0ClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->USB0CLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 5U: - freq = CLOCK_GetPll1OutFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq / ((SYSCON->USB0CLKDIV & 0xffU) + 1U); -} - -/* Get MCLK Clk */ -/*! brief Return Frequency of MClk Clock - * return Frequency of MClk Clock. - */ -uint32_t CLOCK_GetMclkClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->MCLKCLKSEL) - { - case 0U: - freq = CLOCK_GetFroHfFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq / ((SYSCON->MCLKDIV & 0xffU) + 1U); -} - -/* Get SCTIMER Clk */ -/*! brief Return Frequency of SCTimer Clock - * return Frequency of SCTimer Clock. - */ -uint32_t CLOCK_GetSctClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->SCTCLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 2U: - freq = CLOCK_GetExtClkFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 4U: - freq = CLOCK_GetPll1OutFreq(); - break; - case 5U: - freq = CLOCK_GetI2SMClkFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq / ((SYSCON->SCTCLKDIV & 0xffU) + 1U); -} - -/* Get FRO 12M Clk */ -/*! brief Return Frequency of FRO 12MHz - * return Frequency of FRO 12MHz - */ -uint32_t CLOCK_GetFro12MFreq(void) -{ - return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; -} - -/* Get FRO 1M Clk */ -/*! brief Return Frequency of FRO 1MHz - * return Frequency of FRO 1MHz - */ -uint32_t CLOCK_GetFro1MFreq(void) -{ - return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; -} - -/* Get EXT OSC Clk */ -/*! brief Return Frequency of External Clock - * return Frequency of External Clock. If no external clock is used returns 0. - */ -uint32_t CLOCK_GetExtClkFreq(void) -{ - return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; -} - -/* Get WATCH DOG Clk */ -/*! brief Return Frequency of Watchdog - * return Frequency of Watchdog - */ -uint32_t CLOCK_GetWdtClkFreq(void) -{ - return CLOCK_GetFro1MFreq() / ((SYSCON->WDTCLKDIV & SYSCON_WDTCLKDIV_DIV_MASK) + 1U); -} - -/* Get HF FRO Clk */ -/*! brief Return Frequency of High-Freq output of FRO - * return Frequency of High-Freq output of FRO - */ -uint32_t CLOCK_GetFroHfFreq(void) -{ - return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; -} - -/* Get SYSTEM PLL Clk */ -/*! brief Return Frequency of PLL - * return Frequency of PLL - */ -uint32_t CLOCK_GetPll0OutFreq(void) -{ - return s_Pll0_Freq; -} - -/* Get USB PLL Clk */ -/*! brief Return Frequency of USB PLL - * return Frequency of PLL - */ -uint32_t CLOCK_GetPll1OutFreq(void) -{ - return s_Pll1_Freq; -} - -/* Get RTC OSC Clk */ -/*! brief Return Frequency of 32kHz osc - * return Frequency of 32kHz osc - */ -uint32_t CLOCK_GetOsc32KFreq(void) -{ - return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && - (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? - CLK_RTC_32K_CLK : - ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && - ((PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK) != 0UL)) ? - CLK_RTC_32K_CLK : - 0UL; -} - -/* Get Flexcomm 32K Clk */ -/*! brief Return Frequency of Flexcomm 32kHz - * return Frequency of Flexcomm 32kHz - */ -uint32_t CLOCK_GetFC32KFreq(void) -{ - return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && - (0UL == (SYSCON->FC32KCLKSEL & SYSCON_FC32KCLKSEL_FC32KCLKSEL_MASK))) ? - CLK_RTC_32K_CLK : - ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && - ((SYSCON->FC32KCLKSEL & SYSCON_FC32KCLKSEL_FC32KCLKSEL_MASK) != 0UL)) ? - CLK_RTC_32K_CLK : - 0UL; -} - -/* Get MAIN Clk */ -/*! brief Return Frequency of Core System - * return Frequency of Core System - */ -uint32_t CLOCK_GetCoreSysClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->MAINCLKSELB) - { - case 0U: - if (SYSCON->MAINCLKSELA == 0U) - { - freq = CLOCK_GetFro12MFreq(); - } - else if (SYSCON->MAINCLKSELA == 1U) - { - freq = CLOCK_GetExtClkFreq(); - } - else if (SYSCON->MAINCLKSELA == 2U) - { - freq = CLOCK_GetFro1MFreq(); - } - else if (SYSCON->MAINCLKSELA == 3U) - { - freq = CLOCK_GetFroHfFreq(); - } - else - { - /* Added comments to avoid the violation of MISRA C-2012 rule 15.7 */ - } - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 2U: - freq = CLOCK_GetPll1OutFreq(); - break; - - case 3U: - freq = CLOCK_GetOsc32KFreq(); - break; - - default: - freq = 0U; - break; - } - - return freq; -} - -/* Get I2S MCLK Clk */ -/*! brief Return Frequency of I2S MCLK Clock - * return Frequency of I2S MCLK Clock - */ -uint32_t CLOCK_GetI2SMClkFreq(void) -{ - return s_I2S_Mclk_Freq; -} - -/* Get PLLClkDiv Clk */ -uint32_t CLOCK_GetPllClkDivFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->PLLCLKDIVSEL) - { - case 0U: - freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLLCLKDIV & SYSCON_PLLCLKDIV_DIV_MASK) + 1U); - break; - case 1U: - freq = CLOCK_GetPll1OutFreq() / - ((SYSCON->PLLCLKDIV & SYSCON_PLLCLKDIV_DIV_MASK) + 1U); // register name should be checked - break; - default: - freq = 0U; - break; - } - /* todo: pll_clk_div = pll_clk/div*/ - return freq; -} - -/* Get FRG Clk */ -uint32_t CLOCK_GetFrgFreq(uint32_t id) -{ - uint32_t freq = 0U; - - switch (SYSCON->FRGCLKSEL[id]) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPllClkDivFreq(); - break; - case 2U: - freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); - break; - default: - freq = 0U; - break; - } - return (uint32_t)(((uint64_t)freq * (SYSCON_FRGCTRL_DIV_MASK + 1U)) / - ((SYSCON_FRGCTRL_DIV_MASK + 1U) + - ((SYSCON->FRGCTRL[id] & SYSCON_FRGCTRL_MULT_MASK) >> SYSCON_FRGCTRL_MULT_SHIFT))); -} - -/* Get FLEXCOMM Clk */ -uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) -{ - uint32_t freq = 0U; - - switch (SYSCON->FCCLKSEL[id]) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetFrgFreq(id); - break; - case 2U: - freq = CLOCK_GetFro12MFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); - break; - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - case 5U: - freq = CLOCK_GetI2SMClkFreq(); - break; - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq / ((SYSCON->FLEXCOMMCLKDIV[id] & 0xffU) + 1U); -} - -/* Get HS_LPSI Clk */ -uint32_t CLOCK_GetHsLspiClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->HSSPICLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLLCLKDIV & 0xffU) + 1U); - break; - case 2U: - freq = CLOCK_GetFro12MFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); - break; - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq; -} - -/* Get CTimer Clk */ -/*! brief Return Frequency of CTimer functional Clock - * return Frequency of CTimer functional Clock - */ -uint32_t CLOCK_GetCTimerClkFreq(uint32_t id) -{ - uint32_t freq = 0U; - - switch (SYSCON->CTIMERCLKSEL[id]) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 2U: - freq = CLOCK_GetPll1OutFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - case 5U: - freq = CLOCK_GetI2SMClkFreq(); - break; - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq / ((SYSCON->CTIMERCLKDIV[id] & 0xffU) + 1U); -} - -/* Get Systick Clk */ -/*! brief Return Frequency of SystickClock - * return Frequency of Systick Clock - */ -uint32_t CLOCK_GetSystickClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->SYSTICKCLKSEL0) - { - case 0U: - /*Niobe4mini just has one SYSTICKSEL and SYSTICKDIV register, Fix coverity problem in this way temporarily - */ - freq = CLOCK_GetCoreSysClkFreq() / (((SYSCON->SYSTICKCLKDIV[0]) & 0xffU) + 1U); - break; - case 1U: - freq = CLOCK_GetFro1MFreq(); - break; - case 2U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq; -} - -/* Get DAC Clk */ -/*! brief Return Frequency of DAC Clock - * return Frequency of DAC. - */ -uint32_t CLOCK_GetDacClkFreq(uint32_t id) -{ - uint32_t freq = 0U; - - switch (SYSCON->DAC[id].CLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 4U: - freq = CLOCK_GetFro12MFreq(); - break; - case 5U: - freq = CLOCK_GetPll1OutFreq(); - break; - case 6U: - freq = CLOCK_GetFro1MFreq(); - break; - default: - freq = 0U; - break; - } - - return freq / ((SYSCON->DAC[id].CLKDIV & SYSCON_DAC_CLKDIV_DIV_MASK) + 1U); -} - -/* Get FlexSpi Clk */ -/*! brief Return Frequency of FlexSpi clock - * return Frequency of FlexSpi Clock - */ -uint32_t CLOCK_GetFlexSpiClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->FLEXSPICLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 5U: - freq = CLOCK_GetPll1OutFreq(); - break; - case 7U: - freq = 0U; - break; - default: - freq = 0U; - break; - } - - return freq / ((SYSCON->FLEXSPICLKDIV & SYSCON_FLEXSPICLKDIV_DIV_MASK) + 1U); -} - -/* Get DMIC Clk */ -/*! brief Return Frequency of DMIC clock - * return Frequency of DMIC Clock - */ -uint32_t CLOCK_GetDmicClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->DMICFCLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 2U: - freq = CLOCK_GetExtClkFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 4U: - freq = CLOCK_GetPll1OutFreq(); - break; - case 5U: - freq = CLOCK_GetI2SMClkFreq(); - break; - default: - freq = 0U; - break; - } - - return freq / ((SYSCON->DMICFCLKDIV & SYSCON_DMICFCLKDIV_DIV_MASK) + 1U); -} - -/* Get I3C function Clk */ -/*! brief Return Frequency of I3C function clock - * return Frequency of I3C function Clock - */ -uint32_t CLOCK_GetI3cClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->I3CFCLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPllClkDivFreq(); - break; - default: - freq = 0U; - break; - } - - return freq / ((SYSCON->I3CFCLKDIV & SYSCON_I3CFCLKDIV_DIV_MASK) + 1U); -} - -/* Get I3C function slow TC Clk */ -/*! brief Return Frequency of I3C function Slow TC clock - * return Frequency of I3C function slow TC Clock - */ -uint32_t CLOCK_GetI3cSTCClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->I3CFCLKSTCSEL) - { - case 0U: - freq = CLOCK_GetI3cClkFreq(); - break; - case 1U: - freq = CLOCK_GetFro1MFreq(); - break; - default: - freq = 0U; - break; - } - - return freq / ((SYSCON->I3CFCLKSTCDIV & SYSCON_I3CFCLKSTCDIV_DIV_MASK) + 1U); -} - -/* Get I3C function slow Clk */ -/*! brief Return Frequency of I3C function Slow clock - * return Frequency of I3C function slow Clock - */ -uint32_t CLOCK_GetI3cSClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->I3CFCLKSSEL) - { - case 0U: - freq = CLOCK_GetFro1MFreq(); - break; - default: - freq = 0U; - break; - } - - return freq / ((SYSCON->I3CFCLKSDIV & SYSCON_I3CFCLKSDIV_DIV_MASK) + 1U); -} - -/* Get IP Clk */ -/*! brief Return Frequency of selected clock - * return Frequency of selected clock - */ -uint32_t CLOCK_GetFreq(clock_name_t clockName) -{ - uint32_t freq; - switch (clockName) - { - case kCLOCK_CoreSysClk: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case kCLOCK_BusClk: - freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); - break; - case kCLOCK_ClockOut: - freq = CLOCK_GetClockOutClkFreq(); - break; - case kCLOCK_Pll1Out: - freq = CLOCK_GetPll1OutFreq(); - break; - case kCLOCK_Mclk: - freq = CLOCK_GetMclkClkFreq(); - break; - case kCLOCK_FroHf: - freq = CLOCK_GetFroHfFreq(); - break; - case kCLOCK_Fro12M: - freq = CLOCK_GetFro12MFreq(); - break; - case kCLOCK_Fro1M: - freq = CLOCK_GetFro1MFreq(); - break; - case kCLOCK_ExtClk: - freq = CLOCK_GetExtClkFreq(); - break; - case kCLOCK_Pll0Out: - freq = CLOCK_GetPll0OutFreq(); - break; - case kCLOCK_FlexI2S: - freq = CLOCK_GetI2SMClkFreq(); - break; - default: - freq = 0U; - break; - } - return freq; -} - -/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ -static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) -{ - uint32_t seli, selp; - /* bandwidth: compute selP from Multiplier */ - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ - { - selp = (M >> 2U) + 1U; - if (selp >= 31U) - { - selp = 31U; - } - *pSelP = selp; - - if (M >= 8000UL) - { - seli = 1UL; - } - else if (M >= 122UL) - { - seli = (uint32_t)(8000UL / M); /*floor(8000/M) */ - } - else - { - seli = 2UL * ((uint32_t)(M / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ - } - - if (seli >= 63UL) - { - seli = 63UL; - } - *pSelI = seli; - - *pSelR = 0UL; - } - else - { - /* Note: If the spread spectrum mode, choose N to ensure 3 MHz < Fin/N < 5 MHz */ - *pSelP = 3U; - *pSelI = 4U; - *pSelR = 4U; - } -} - -/* Get predivider (N) from PLL0 NDEC setting */ -static uint32_t findPll0PreDiv(void) -{ - uint32_t preDiv = 1UL; - - /* Direct input is not used? */ - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) - { - preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; - if (preDiv == 0UL) - { - preDiv = 1UL; - } - } - return preDiv; -} - -/* Get predivider (N) from PLL1 NDEC setting */ -static uint32_t findPll1PreDiv(void) -{ - uint32_t preDiv = 1UL; - - /* Direct input is not used? */ - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) - { - preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; - if (preDiv == 0UL) - { - preDiv = 1UL; - } - } - return preDiv; -} - -/* Get postdivider (P) from PLL0 PDEC setting */ -static uint32_t findPll0PostDiv(void) -{ - uint32_t postDiv = 1UL; - - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) - { - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) - { - postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; - } - else - { - postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); - } - if (postDiv == 0UL) - { - postDiv = 2UL; - } - } - return postDiv; -} - -/* Get postdivider (P) from PLL1 PDEC setting. */ -static uint32_t findPll1PostDiv(void) -{ - uint32_t postDiv = 1UL; - - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0UL) - { - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) != 0UL) - { - postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK; - } - else - { - postDiv = 2UL * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK); - } - if (postDiv == 0UL) - { - postDiv = 2UL; - } - } - - return postDiv; -} - -/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ -static float findPll0MMult(void) -{ - float mMult = 1.0F; - float mMult_fract; - uint32_t mMult_int; - - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) - { - mMult = - (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); - } - else - { - mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); - mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL0_SSCG_MD_INT_P); - mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL0_SSCG_MD_FRACT_M) / - (float)(uint32_t)(1UL << PLL0_SSCG_MD_INT_P)); - mMult = (float)mMult_int + mMult_fract; - } - if (0ULL == ((uint64_t)mMult)) - { - mMult = 1.0F; - } - return mMult; -} - -/* Get multiplier (M) from PLL1 MDEC. */ -static uint32_t findPll1MMult(void) -{ - uint32_t mMult = 1UL; - - mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK; - - if (mMult == 0UL) - { - mMult = 1UL; - } - - return mMult; -} - -/* Find greatest common divisor between m and n */ -static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) -{ - uint32_t tmp; - - while (n != 0U) - { - tmp = n; - n = m % n; - m = tmp; - } - - return m; -} - -/* - * Set PLL0 output based on desired output rate. - * In this function, the it calculates the PLL0 setting for output frequency from input clock - * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. - * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. - */ -static pll_error_t CLOCK_GetPll0ConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) -{ - uint32_t nDivOutHz, fccoHz; - uint32_t pllPreDivider, pllMultiplier, pllPostDivider; - uint32_t pllDirectInput, pllDirectOutput; - uint32_t pllSelP, pllSelI, pllSelR, uplimoff; - - /* Baseline parameters (no input or output dividers) */ - pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ - pllPostDivider = 1U; /* 1 implies post-divider will be disabled */ - pllDirectOutput = 1U; - - /* Verify output rate parameter */ - if (foutHz > PLL_MAX_CCO_FREQ_MHZ) - { - /* Maximum PLL output with post divider=1 cannot go above this frequency */ - return kStatus_PLL_OutputTooHigh; - } - if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) - { - /* Minmum PLL output with maximum post divider cannot go below this frequency */ - return kStatus_PLL_OutputTooLow; - } - - /* If using SS mode, input clock needs to be between 3MHz and 20MHz */ - if (useSS) - { - /* Verify input rate parameter */ - if (finHz < PLL_MIN_IN_SSMODE) - { - /* Input clock into the PLL cannot be lower than this */ - return kStatus_PLL_InputTooLow; - } - /* PLL input in SS mode must be under 20MHz */ - if (finHz > (PLL_MAX_IN_SSMODE * NVALMAX)) - { - return kStatus_PLL_InputTooHigh; - } - } - else - { - /* Verify input rate parameter */ - if (finHz < PLL_LOWER_IN_LIMIT) - { - /* Input clock into the PLL cannot be lower than this */ - return kStatus_PLL_InputTooLow; - } - if (finHz > PLL_HIGHER_IN_LIMIT) - { - /* Input clock into the PLL cannot be higher than this */ - return kStatus_PLL_InputTooHigh; - } - } - - /* Find the optimal CCO frequency for the output and input that - will keep it inside the PLL CCO range. This may require - tweaking the post-divider for the PLL. */ - fccoHz = foutHz; - while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) - { - /* CCO output is less than minimum CCO range, so the CCO output - needs to be bumped up and the post-divider is used to bring - the PLL output back down. */ - pllPostDivider++; - if (pllPostDivider > PVALMAX) - { - return kStatus_PLL_OutsideIntLimit; - } - - /* Target CCO goes up, PLL output goes down */ - /* divide-by-2 divider in the post-divider is always work*/ - fccoHz = foutHz * (pllPostDivider * 2U); - pllDirectOutput = 0U; - } - - /* Determine if a pre-divider is needed to get the best frequency */ - if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) - { - uint32_t a = FindGreatestCommonDivisor(fccoHz, finHz); - - if (a > PLL_LOWER_IN_LIMIT) - { - a = finHz / a; - if ((a != 0U) && (a < PLL_MAX_N_DIV)) - { - pllPreDivider = a; - } - } - } - - /* Bypass pre-divider hardware if pre-divider is 1 */ - if (pllPreDivider > 1U) - { - pllDirectInput = 0U; - } - else - { - pllDirectInput = 1U; - } - - /* Determine PLL multipler */ - nDivOutHz = (finHz / pllPreDivider); - pllMultiplier = (fccoHz / nDivOutHz); - - /* Find optimal values for filter */ - if (useSS == false) - { - /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ - if ((nDivOutHz * ((pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) - { - pllMultiplier++; - } - - /* Setup filtering */ - pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR); - uplimoff = 0U; - - /* Get encoded value for M (mult) and use manual filter, disable SS mode */ - pSetup->pllsscg[1] = - (uint32_t)((PLL_SSCG1_MDEC_VAL_SET(pllMultiplier)) | (1UL << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)); - } - else - { - uint64_t fc; - - /* Filtering will be handled by SSC */ - pllSelR = 0UL; - pllSelI = 0UL; - pllSelP = 0UL; - uplimoff = 1U; - - /* The PLL multiplier will get very close and slightly under the - desired target frequency. A small fractional component can be - added to fine tune the frequency upwards to the target. */ - fc = ((uint64_t)(uint32_t)(fccoHz % nDivOutHz) << 25UL) / nDivOutHz; - - /* Set multiplier */ - pSetup->pllsscg[0] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) | PLL0_SSCG_MD_FRACT_SET((uint32_t)fc)); - pSetup->pllsscg[1] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) >> 32U); - } - - /* Get encoded values for N (prediv) and P (postdiv) */ - pSetup->pllndec = PLL_NDEC_VAL_SET(pllPreDivider); - pSetup->pllpdec = PLL_PDEC_VAL_SET(pllPostDivider); - - /* PLL control */ - pSetup->pllctrl = (pllSelR << SYSCON_PLL0CTRL_SELR_SHIFT) | /* Filter coefficient */ - (pllSelI << SYSCON_PLL0CTRL_SELI_SHIFT) | /* Filter coefficient */ - (pllSelP << SYSCON_PLL0CTRL_SELP_SHIFT) | /* Filter coefficient */ - (0UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT) | /* PLL bypass mode disabled */ - (uplimoff << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */ - (pllDirectInput << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */ - (pllDirectOutput << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT) | /* Bypass post-divider? */ - (1UL << SYSCON_PLL0CTRL_CLKEN_SHIFT); /* Ensure the PLL clock output */ - - return kStatus_PLL_Success; -} - -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) -/* Alloct the static buffer for cache. */ -static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; -static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; -static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; -static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; -static uint32_t s_PllSetupCacheIdx = 0U; -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - -/* - * Calculate the PLL setting values from input clock freq to output freq. - */ -static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) -{ - pll_error_t retErr; -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - uint32_t i; - - for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) - { - if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && (useSS == s_UseSSCache[i])) - { - /* Hit the target in cache buffer. */ - pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl; - pSetup->pllndec = s_PllSetupCacheStruct[i].pllndec; - pSetup->pllpdec = s_PllSetupCacheStruct[i].pllpdec; - pSetup->pllsscg[0] = s_PllSetupCacheStruct[i].pllsscg[0]; - pSetup->pllsscg[1] = s_PllSetupCacheStruct[i].pllsscg[1]; - retErr = kStatus_PLL_Success; - break; - } - } - - if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - { - return retErr; - } -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - - retErr = CLOCK_GetPll0ConfigInternal(finHz, foutHz, pSetup, useSS); - -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - /* Cache the most recent calulation result into buffer. */ - s_FinHzCache[s_PllSetupCacheIdx] = finHz; - s_FoutHzCache[s_PllSetupCacheIdx] = foutHz; - s_UseSSCache[s_PllSetupCacheIdx] = useSS; - - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndec = pSetup->pllndec; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdec = pSetup->pllpdec; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[0] = pSetup->pllsscg[0]; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[1] = pSetup->pllsscg[1]; - /* Update the index for next available buffer. */ - s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - - return retErr; -} - -/* Update local PLL rate variable */ -static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup) -{ - s_Pll0_Freq = CLOCK_GetPLL0OutFromSetup(pSetup); -} - -/* Update local PLL1 rate variable */ -static void CLOCK_GetPLL1OutFromSetupUpdate(pll_setup_t *pSetup) -{ - s_Pll1_Freq = CLOCK_GetPLL1OutFromSetup(pSetup); -} - -/* Return System PLL input clock rate */ -/*! brief Return PLL0 input clock rate - * return PLL0 input clock rate - */ -uint32_t CLOCK_GetPLL0InClockRate(void) -{ - uint32_t clkRate = 0U; - - switch ((SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK)) - { - case 0x00U: - clkRate = CLK_FRO_12MHZ; - break; - - case 0x01U: - clkRate = CLOCK_GetExtClkFreq(); - break; - - case 0x02U: - clkRate = CLOCK_GetFro1MFreq(); - break; - - case 0x03U: - clkRate = CLOCK_GetOsc32KFreq(); - break; - - default: - clkRate = 0U; - break; - } - - return clkRate; -} - -/* Return PLL1 input clock rate */ -uint32_t CLOCK_GetPLL1InClockRate(void) -{ - uint32_t clkRate = 0U; - - switch ((SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK)) - { - case 0x00U: - clkRate = CLK_FRO_12MHZ; - break; - - case 0x01U: - clkRate = CLOCK_GetExtClkFreq(); - break; - - case 0x02U: - clkRate = CLOCK_GetFro1MFreq(); - break; - - case 0x03U: - clkRate = CLOCK_GetOsc32KFreq(); - break; - - default: - clkRate = 0U; - break; - } - - return clkRate; -} - -/* Return PLL0 output clock rate from setup structure */ -/*! brief Return PLL0 output clock rate from setup structure - * param pSetup : Pointer to a PLL setup structure - * return PLL0 output clock rate the setup structure will generate - */ -uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup) -{ - uint32_t clkRate = 0; - uint32_t prediv, postdiv; - float workRate = 0.0F; - - /* Get the input clock frequency of PLL. */ - clkRate = CLOCK_GetPLL0InClockRate(); - - if (((pSetup->pllctrl & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && - ((pSetup->pllctrl & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && - ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && - ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) - { - prediv = findPll0PreDiv(); - postdiv = findPll0PostDiv(); - /* Adjust input clock */ - clkRate = clkRate / prediv; - /* MDEC used for rate */ - workRate = (float)clkRate * (float)findPll0MMult(); - workRate /= (float)postdiv; - } - - return (uint32_t)workRate; -} - -/* Return PLL1 output clock rate from setup structure */ -/*! brief Return PLL1 output clock rate from setup structure - * param pSetup : Pointer to a PLL setup structure - * return PLL0 output clock rate the setup structure will generate - */ -uint32_t CLOCK_GetPLL1OutFromSetup(pll_setup_t *pSetup) -{ - uint32_t clkRate = 0; - uint32_t prediv, postdiv; - uint32_t workRate = 0UL; - - /* Get the input clock frequency of PLL. */ - clkRate = CLOCK_GetPLL1InClockRate(); - - if (((pSetup->pllctrl & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0UL) && - ((pSetup->pllctrl & SYSCON_PLL1CTRL_CLKEN_MASK) != 0UL) && - ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0UL)) - { - prediv = findPll1PreDiv(); - postdiv = findPll1PostDiv(); - /* Adjust input clock */ - clkRate = clkRate / prediv; - /* MDEC used for rate */ - workRate = clkRate * findPll1MMult(); - workRate /= postdiv; - } - - return workRate; -} - -/* Set the current PLL0 Rate */ -/*! brief Store the current PLL rate - * param rate: Current rate of the PLL - * return Nothing - **/ -void CLOCK_SetStoredPLL0ClockRate(uint32_t rate) -{ - s_Pll0_Freq = rate; -} - -/* Return PLL0 output clock rate */ -/*! brief Return PLL0 output clock rate - * param recompute : Forces a PLL rate recomputation if true - * return PLL0 output clock rate - * note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetPLL0OutClockRate(bool recompute) -{ - pll_setup_t Setup; - uint32_t rate; - - if ((recompute) || (s_Pll0_Freq == 0U)) - { - Setup.pllctrl = SYSCON->PLL0CTRL; - Setup.pllndec = SYSCON->PLL0NDEC; - Setup.pllpdec = SYSCON->PLL0PDEC; - Setup.pllsscg[0] = SYSCON->PLL0SSCG0; - Setup.pllsscg[1] = SYSCON->PLL0SSCG1; - - CLOCK_GetPLL0OutFromSetupUpdate(&Setup); - } - - rate = s_Pll0_Freq; - - return rate; -} - -/*! brief Return PLL1 output clock rate - * param recompute : Forces a PLL rate recomputation if true - * return PLL1 output clock rate - * note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetPLL1OutClockRate(bool recompute) -{ - pll_setup_t Setup; - uint32_t rate; - - if ((recompute) || (s_Pll1_Freq == 0U)) - { - Setup.pllctrl = SYSCON->PLL1CTRL; - Setup.pllndec = SYSCON->PLL1NDEC; - Setup.pllpdec = SYSCON->PLL1PDEC; - Setup.pllmdec = SYSCON->PLL1MDEC; - CLOCK_GetPLL1OutFromSetupUpdate(&Setup); - } - - rate = s_Pll1_Freq; - - return rate; -} - -/* Set PLL0 output based on the passed PLL setup data */ -/*! brief Set PLL output based on the passed PLL setup data - * param pControl : Pointer to populated PLL control structure to generate setup with - * param pSetup : Pointer to PLL setup structure to be filled - * return PLL_ERROR_SUCCESS on success, or PLL setup error code - * note Actual frequency for setup may vary from the desired frequency based on the - * accuracy of input clocks, rounding, non-fractional PLL mode, etc. - */ -pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup) -{ - uint32_t inRate; - bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0UL); - - pll_error_t pllError; - - /* Determine input rate for the PLL */ - if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0UL) - { - inRate = pControl->inputRate; - } - else - { - inRate = CLOCK_GetPLL0InClockRate(); - } - - /* PLL flag options */ - pllError = CLOCK_GetPll0Config(inRate, pControl->desiredRate, pSetup, useSS); - if ((useSS) && (pllError == kStatus_PLL_Success)) - { - /* If using SS mode, then some tweaks are made to the generated setup */ - pSetup->pllsscg[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc; - if (pControl->mfDither) - { - pSetup->pllsscg[1] |= (1UL << SYSCON_PLL0SSCG1_DITHER_SHIFT); - } - } - - return pllError; -} - -/* Set PLL0 output from PLL setup structure */ -/*! brief Set PLL output from PLL setup structure (precise frequency) - * param pSetup : Pointer to populated PLL setup structure - * param flagcfg : Flag configuration for PLL config structure - * return PLL_ERROR_SUCCESS on success, or PLL setup error code - * note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg) -{ - uint32_t inRate, clkRate, prediv; - - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_PLL0); - POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); - - pSetup->flags = flagcfg; - - /* Write PLL setup data */ - SYSCON->PLL0CTRL = pSetup->pllctrl; - SYSCON->PLL0NDEC = pSetup->pllndec; - SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ - SYSCON->PLL0PDEC = pSetup->pllpdec; - SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ - SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; - SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; - SYSCON->PLL0SSCG1 = - pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT); /* latch */ - - POWER_DisablePD(kPDRUNCFG_PD_PLL0); - POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); - - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0UL) - { - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ - { - inRate = CLOCK_GetPLL0InClockRate(); - prediv = findPll0PreDiv(); - /* Adjust input clock */ - clkRate = inRate / prediv; - /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ - if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) - { - while (CLOCK_IsPLL0Locked() == false) - { - } - } - else - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval - to insure the PLL will be stable */ - } - } - else /* spread spectrum mode */ - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to - insure the PLL will be stable */ - } - } - - /* Update current programmed PLL rate var */ - CLOCK_GetPLL0OutFromSetupUpdate(pSetup); - - /* System voltage adjustment, occurs prior to setting main system clock */ - if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0UL) - { - POWER_SetVoltageForFreq(s_Pll0_Freq); - } - - return kStatus_PLL_Success; -} - -/* Setup PLL Frequency from pre-calculated value */ -/** - * brief Set PLL0 output from PLL setup structure (precise frequency) - * param pSetup : Pointer to populated PLL setup structure - * return kStatus_PLL_Success on success, or PLL setup error code - * note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup) -{ - uint32_t inRate, clkRate, prediv; - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_PLL0); - POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); - - /* Write PLL setup data */ - SYSCON->PLL0CTRL = pSetup->pllctrl; - SYSCON->PLL0NDEC = pSetup->pllndec; - SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ - SYSCON->PLL0PDEC = pSetup->pllpdec; - SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ - SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; - SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; - SYSCON->PLL0SSCG1 = - pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* latch */ - - POWER_DisablePD(kPDRUNCFG_PD_PLL0); - POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); - - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0UL) - { - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ - { - inRate = CLOCK_GetPLL0InClockRate(); - prediv = findPll0PreDiv(); - /* Adjust input clock */ - clkRate = inRate / prediv; - /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ - if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) - { - while (CLOCK_IsPLL0Locked() == false) - { - } - } - else - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval - to insure the PLL will be stable */ - } - } - else /* spread spectrum mode */ - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to - insure the PLL will be stable */ - } - } - - /* Update current programmed PLL rate var */ - s_Pll0_Freq = pSetup->pllRate; - - return kStatus_PLL_Success; -} - -/* Setup PLL1 Frequency from pre-calculated value */ -/** - * brief Set PLL1 output from PLL setup structure (precise frequency) - * param pSetup : Pointer to populated PLL setup structure - * return kStatus_PLL_Success on success, or PLL setup error code - * note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup) -{ - uint32_t inRate, clkRate, prediv; - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_PLL1); - - /* Write PLL setup data */ - SYSCON->PLL1CTRL = pSetup->pllctrl; - SYSCON->PLL1NDEC = pSetup->pllndec; - SYSCON->PLL1NDEC = pSetup->pllndec | (1UL << SYSCON_PLL1NDEC_NREQ_SHIFT); /* latch */ - SYSCON->PLL1PDEC = pSetup->pllpdec; - SYSCON->PLL1PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL1PDEC_PREQ_SHIFT); /* latch */ - SYSCON->PLL1MDEC = pSetup->pllmdec; - SYSCON->PLL1MDEC = pSetup->pllmdec | (1UL << SYSCON_PLL1MDEC_MREQ_SHIFT); /* latch */ - - POWER_DisablePD(kPDRUNCFG_PD_PLL1); - - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0UL) - { - inRate = CLOCK_GetPLL1InClockRate(); - prediv = findPll1PreDiv(); - /* Adjust input clock */ - clkRate = inRate / prediv; - /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ - if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) - { - while (CLOCK_IsPLL1Locked() == false) - { - } - } - else - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to - insure the PLL will be stable */ - } - } - - /* Update current programmed PLL rate var */ - s_Pll1_Freq = pSetup->pllRate; - - return kStatus_PLL_Success; -} - -/* Set PLL0 clock based on the input frequency and multiplier */ -/*! brief Set PLL0 output based on the multiplier and input frequency - * param multiply_by : multiplier - * param input_freq : Clock input frequency of the PLL - * return Nothing - * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this - * function does not disable or enable PLL power, wait for PLL lock, - * or adjust system voltages. These must be done in the application. - * The function will not alter any source clocks (ie, main systen clock) - * that may use the PLL, so these should be setup prior to and after - * exiting the function. - */ -void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq) -{ - uint32_t cco_freq = input_freq * multiply_by; - uint32_t pdec = 1U; - uint32_t selr; - uint32_t seli; - uint32_t selp; - uint32_t mdec, ndec; - - while (cco_freq < 275000000U) - { - multiply_by <<= 1U; /* double value in each iteration */ - pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */ - cco_freq = input_freq * multiply_by; - } - - selr = 0U; - - if (multiply_by >= 8000UL) - { - seli = 1UL; - } - else if (multiply_by >= 122UL) - { - seli = (uint32_t)(8000UL / multiply_by); /*floor(8000/M) */ - } - else - { - seli = 2UL * ((uint32_t)(multiply_by / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ - } - - if (seli >= 63U) - { - seli = 63U; - } - - { - selp = 31U; - } - - if (pdec > 1U) - { - pdec = pdec / 2U; /* Account for minus 1 encoding */ - /* Translate P value */ - } - - mdec = (uint32_t)PLL_SSCG1_MDEC_VAL_SET(multiply_by); - ndec = 0x1U; /* pre divide by 1 (hardcoded) */ - - SYSCON->PLL0CTRL = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_BYPASSPOSTDIV(0) | - SYSCON_PLL0CTRL_BYPASSPOSTDIV2(0) | (selr << SYSCON_PLL0CTRL_SELR_SHIFT) | - (seli << SYSCON_PLL0CTRL_SELI_SHIFT) | (selp << SYSCON_PLL0CTRL_SELP_SHIFT); - SYSCON->PLL0PDEC = pdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* set Pdec value and assert preq */ - SYSCON->PLL0NDEC = ndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* set Pdec value and assert preq */ - SYSCON->PLL0SSCG1 = - mdec | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* select non sscg MDEC value, assert mreq and select mdec value */ -} - -/* Enable USB DEVICE FULL SPEED clock */ -/*! brief Enable USB Device FS clock. - * param src : clock source - * param freq: clock frequency - * Enable USB Device Full Speed clock. - */ -bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq) -{ - bool ret = true; - - CLOCK_DisableClock(kCLOCK_Usbd0); - - if (kCLOCK_UsbfsSrcFro == src) - { - switch (freq) - { - case 96000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ - break; - - default: - ret = false; - break; - } - /* Turn ON FRO HF */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); - /* Enable FRO 96MHz output */ - ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; - /* Select FRO 96 or 48 MHz */ - CLOCK_AttachClk(kFRO_HF_to_USB0); - } - else - { - /*!< Configure XTAL32M */ - POWER_DisablePD(kPDRUNCFG_PD_XTALHF); /* Ensure XTAL32M is powered */ - POWER_DisablePD(kPDRUNCFG_PD_LDOXTALHF); /* Ensure XTAL32M is powered */ - (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ - - /*!< Set up PLL1 */ - POWER_DisablePD(kPDRUNCFG_PD_PLL1); - CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ - const pll_setup_t pll1Setup = { - .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U), - .pllndec = SYSCON_PLL1NDEC_NDIV(1U), - .pllpdec = SYSCON_PLL1PDEC_PDIV(5U), - .pllmdec = SYSCON_PLL1MDEC_MDIV(30U), - .pllRate = 48000000U, - .flags = PLL_SETUPFLAG_WAITLOCK}; - (void)CLOCK_SetPLL1Freq(&pll1Setup); - - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); - CLOCK_AttachClk(kPLL1_to_USB0); - SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - } - CLOCK_EnableClock(kCLOCK_Usbd0); - - return ret; -} - -/* Enable USB HOST FULL SPEED clock */ -/*! brief Enable USB HOST FS clock. - * param src : clock source - * param freq: clock frequency - * Enable USB HOST Full Speed clock. - */ -bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq) -{ - bool ret = true; - - if (kCLOCK_UsbfsSrcFro == src) - { - switch (freq) - { - case 96000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ - break; - - default: - ret = false; - break; - } - /* Turn ON FRO HF */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); - /* Enable FRO 96MHz output */ - ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; - /* Select FRO 96 MHz */ - CLOCK_AttachClk(kFRO_HF_to_USB0); - } - else - { - /*!< Configure XTAL32M */ - POWER_DisablePD(kPDRUNCFG_PD_XTALHF); /* Ensure XTAL32M is powered */ - POWER_DisablePD(kPDRUNCFG_PD_LDOXTALHF); /* Ensure XTAL32M is powered */ - (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ - - /*!< Set up PLL1 */ - POWER_DisablePD(kPDRUNCFG_PD_PLL1); - CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ - const pll_setup_t pll1Setup = { - .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U), - .pllndec = SYSCON_PLL1NDEC_NDIV(1U), - .pllpdec = SYSCON_PLL1PDEC_PDIV(5U), - .pllmdec = SYSCON_PLL1MDEC_MDIV(30U), - .pllRate = 48000000U, - .flags = PLL_SETUPFLAG_WAITLOCK}; - (void)CLOCK_SetPLL1Freq(&pll1Setup); - - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); - CLOCK_AttachClk(kPLL1_to_USB0); - SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - } - CLOCK_EnableClock(kCLOCK_Usbhmr0); - CLOCK_EnableClock(kCLOCK_Usbhsl0); - - return ret; -} - -/*! @brief Enable the OSTIMER 32k clock. - * @return Nothing - */ -void CLOCK_EnableOstimer32kClock(void) -{ - PMC->OSEVENTTIMER |= PMC_OSEVENTTIMER_CLOCKENABLE_MASK; -} - -/* Sets board-specific trim values for High Frequency crystal oscillator */ -/*! brief Sets board-specific trim values for High Frequency crystal oscillator. - * param pi32_hfXtalIecLoadpF_x100 : Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 - * param pi32_hfXtalPPcbParCappF_x100 : PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF - * becomes 120 - * param pi32_hfXtalNPcbParCappF_x100 : PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF - * becomes 120 - * return none - * note Following default Values can be used: - * pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 - * pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20 - * pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 - * Sets board-specific trim values for High Frequency crystal oscillator. - */ -void CLOCK_XtalHfCapabankTrim(int32_t pi32_hfXtalIecLoadpF_x100, - int32_t pi32_hfXtalPPcbParCappF_x100, - int32_t pi32_hfXtalNPcbParCappF_x100) -{ - uint32_t u32XOTrimValue; - uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF, u8XOSlave; - int32_t iaXin_x4, ibXin, iaXout_x4, ibXout; - int32_t iXOCapInpF_x100, iXOCapOutpF_x100; - uint8_t u8XOCapInCtrl, u8XOCapOutCtrl; - uint32_t u32RegVal; - - /* Enable and set LDO, if not already done */ - CLOCK_SetXtalHfLdo(); - /* Get Cal values from Flash */ - u32XOTrimValue = GET_HFXO_TRIM(); - /* Check validity and apply */ - if ((u32XOTrimValue & 1) && ((u32XOTrimValue >> 15) & 1)) - { - /* These fields are 7 bits, unsigned */ - u8IECXinCapCal6pF = (u32XOTrimValue >> 1) & 0x7f; - u8IECXinCapCal8pF = (u32XOTrimValue >> 8) & 0x7f; - u8IECXoutCapCal6pF = (u32XOTrimValue >> 16) & 0x7f; - u8IECXoutCapCal8pF = (u32XOTrimValue >> 23) & 0x7f; - /* This field is 1 bit */ - u8XOSlave = (u32XOTrimValue >> 30) & 0x1; - /* Linear fit coefficients calculation */ - iaXin_x4 = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF; - ibXin = (int)u8IECXinCapCal6pF - iaXin_x4 * 3; - iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF; - ibXout = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3; - } - else - { - iaXin_x4 = 20; // gain in LSB/pF - ibXin = -9; // offset in LSB - iaXout_x4 = 20; // gain in LSB/pF - ibXout = -13; // offset in LSB - u8XOSlave = 0; - } - /* In & out load cap calculation with derating */ - iXOCapInpF_x100 = - 2 * pi32_hfXtalIecLoadpF_x100 - pi32_hfXtalNPcbParCappF_x100 + 39 * (XO_SLAVE_EN - u8XOSlave) - 15; - iXOCapOutpF_x100 = 2 * pi32_hfXtalIecLoadpF_x100 - pi32_hfXtalPPcbParCappF_x100 - 21; - /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */ - u8XOCapInCtrl = (uint8_t)(((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400); - u8XOCapOutCtrl = (uint8_t)(((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400); - /* Read register and clear fields to be written */ - u32RegVal = ANACTRL->XO32M_CTRL; - u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); - /* Configuration of 32 MHz XO output buffers */ -#if (XO_SLAVE_EN == 0) - u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); -#else - u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; -#endif - /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */ - u32RegVal |= CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT; - u32RegVal |= CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT; - /* Write back to register */ - ANACTRL->XO32M_CTRL = u32RegVal; -} - -/* Sets board-specific trim values for 32kHz XTAL */ -/*! brief Sets board-specific trim values for 32kHz XTAL. - * param pi32_32kfXtalIecLoadpF_x100 : Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 - * param pi32_32kfXtalPPcbParCappF_x100 : PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF - * becomes 120 - * param pi32_32kfXtalNPcbParCappF_x100 : PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF - * becomes 120 - * return none - * note Following default Values can be used: - * pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 - * pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40 - * pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 - * Sets board-specific trim values for 32kHz XTAL. - */ -void CLOCK_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, - int32_t pi32_32kfXtalPPcbParCappF_x100, - int32_t pi32_32kfXtalNPcbParCappF_x100) -{ - uint32_t u32XOTrimValue; - uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF; - int32_t iaXin_x4, ibXin, iaXout_x4, ibXout; - int32_t iXOCapInpF_x100, iXOCapOutpF_x100; - uint8_t u8XOCapInCtrl, u8XOCapOutCtrl; - uint32_t u32RegVal; - /* Get Cal values from Flash */ - u32XOTrimValue = GET_32KXO_TRIM(); - /* check validity and apply */ - if ((u32XOTrimValue & 1) && ((u32XOTrimValue >> 15) & 1)) - { - /* These fields are 7 bits, unsigned */ - u8IECXinCapCal6pF = (u32XOTrimValue >> 1) & 0x7f; - u8IECXinCapCal8pF = (u32XOTrimValue >> 8) & 0x7f; - u8IECXoutCapCal6pF = (u32XOTrimValue >> 16) & 0x7f; - u8IECXoutCapCal8pF = (u32XOTrimValue >> 23) & 0x7f; - /* Linear fit coefficients calculation */ - iaXin_x4 = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF; - ibXin = (int)u8IECXinCapCal6pF - iaXin_x4 * 3; - iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF; - ibXout = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3; - } - else - { - iaXin_x4 = 16; // gain in LSB/pF - ibXin = 12; // offset in LSB - iaXout_x4 = 16; // gain in LSB/pF - ibXout = 11; // offset in LSB - } - - /* In & out load cap calculation with derating */ - iXOCapInpF_x100 = 2 * pi32_32kfXtalIecLoadpF_x100 - pi32_32kfXtalNPcbParCappF_x100 - 130; - iXOCapOutpF_x100 = 2 * pi32_32kfXtalIecLoadpF_x100 - pi32_32kfXtalPPcbParCappF_x100 - 41; - - /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */ - u8XOCapInCtrl = (uint8_t)(((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400); - u8XOCapOutCtrl = (uint8_t)(((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400); - - /* Read register and clear fields to be written */ - u32RegVal = PMC->XTAL32K; - u32RegVal &= ~(PMC_XTAL32K_CAPBANKIN_MASK | PMC_XTAL32K_CAPBANKOUT_MASK); - - /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */ - u32RegVal |= CLOCK_u8OscCapConvert(u8XOCapInCtrl, 23) << PMC_XTAL32K_CAPBANKIN_SHIFT; - u32RegVal |= CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 23) << PMC_XTAL32K_CAPBANKOUT_SHIFT; - - /* Write back to register */ - PMC->XTAL32K = u32RegVal; -} - -/* Enables and sets LDO for High Frequency crystal oscillator. */ -/*! brief Enables and sets LDO for High Frequency crystal oscillator. - * return none - * Sets Enables and sets LDO for High Frequency crystal oscillator. - */ -void CLOCK_SetXtalHfLdo(void) -{ - uint32_t temp; - const uint32_t u32Mask = - (ANACTRL_LDO_XO32M_VOUT_MASK | ANACTRL_LDO_XO32M_IBIAS_MASK | ANACTRL_LDO_XO32M_STABMODE_MASK); - - const uint32_t u32Value = - (ANACTRL_LDO_XO32M_VOUT(0x5) | ANACTRL_LDO_XO32M_IBIAS(0x2) | ANACTRL_LDO_XO32M_STABMODE(0x1)); - - /* Enable & set-up XTAL 32 MHz clock LDO */ - temp = ANACTRL->LDO_XO32M; - - if ((temp & u32Mask) != u32Value) - { - temp &= ~u32Mask; - - /* - * Enable the XTAL32M LDO - * Adjust the output voltage level, 0x5 for 1.1V - * Adjust the biasing current, 0x2 value - * Stability configuration, 0x1 default mode - */ - temp |= u32Value; - - ANACTRL->LDO_XO32M = temp; - - /* Delay for LDO to be up */ - // CLOCK_uDelay(20); - } - - /* Enable LDO XO32M */ - PMC->PDRUNCFGCLR0 = PMC_PDRUNCFG0_PDEN_LDOXTALHF_MASK; -} - -/** - * @brief - * @param - * @return - */ -static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity) -{ - /* Compensate for discontinuity in the capacitor banks */ - if (u8OscCap < 64) - { - if (u8OscCap >= u8CapBankDiscontinuity) - { - u8OscCap -= u8CapBankDiscontinuity; - } - else - { - u8OscCap = 0; - } - } - else - { - if (u8OscCap <= (127 - u8CapBankDiscontinuity)) - { - u8OscCap += u8CapBankDiscontinuity; - } - else - { - u8OscCap = 127; - } - } - return u8OscCap; -} - -/*! - * brief Initialize the trim value for FRO HF . - */ -void CLOCK_FroHfTrim(void) -{ - volatile unsigned int Fro192mCtrlEfuse = 0; - Fro192mCtrlEfuse = ANACTRL->FRO192M_CTRL; - ANACTRL->ANALOG_CTRL_CFG = ANACTRL->ANALOG_CTRL_CFG | ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK; - ANACTRL->FRO192M_CTRL = ANACTRL_FRO192M_CTRL_WRTRIM_MASK | Fro192mCtrlEfuse; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_clock.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_clock.h deleted file mode 100644 index 11e0d51f5d8..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_clock.h +++ /dev/null @@ -1,1579 +0,0 @@ -/* - * Copyright 2017 - 2021 , NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CLOCK_H_ -#define _FSL_CLOCK_H_ - -#include "fsl_common.h" - -/*! @addtogroup clock */ -/*! @{ */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CLOCK driver version 2.3.1. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) -/*@}*/ - -/*! @brief Configure whether driver controls clock - * - * When set to 0, peripheral drivers will enable clock in initialize function - * and disable clock in de-initialize function. When set to 1, peripheral - * driver will not control the clock, application could control the clock out of - * the driver. - * - * @note All drivers share this feature switcher. If it is set to 1, application - * should handle clock enable and disable for all drivers. - */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) -#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 -#endif - -/*! - * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. - * - * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function - * would cache the recent calulation and accelerate the execution to get the - * right settings. - */ -#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT -#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U -#endif - -/* Definition for delay API in clock driver, users can redefine it to the real application. */ -#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY -#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (100000000UL) -#endif - -/*! @brief Clock ip name array for ROM. */ -#define ROM_CLOCKS \ - { \ - kCLOCK_Rom \ - } -/*! @brief Clock ip name array for SRAM. */ -#define SRAM_CLOCKS \ - { \ - kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3, kCLOCK_Sram4 \ - } -/*! @brief Clock ip name array for FLASH. */ -#define FLASH_CLOCKS \ - { \ - kCLOCK_Flash \ - } -/*! @brief Clock ip name array for FMC. */ -#define FMC_CLOCKS \ - { \ - kCLOCK_Fmc \ - } -/*! @brief Clock ip name array for INPUTMUX. */ -#define INPUTMUX_CLOCKS \ - { \ - kCLOCK_InputMux \ - } -/*! @brief Clock ip name array for IOCON. */ -#define IOCON_CLOCKS \ - { \ - kCLOCK_Iocon \ - } -/*! @brief Clock ip name array for GPIO. */ -#define GPIO_CLOCKS \ - { \ - kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3 \ - } -/*! @brief Clock ip name array for PINT. */ -#define PINT_CLOCKS \ - { \ - kCLOCK_Pint \ - } -/*! @brief Clock ip name array for GINT. */ -#define GINT_CLOCKS \ - { \ - kCLOCK_Gint, kCLOCK_Gint \ - } -/*! @brief Clock ip name array for DMA. */ -#define DMA_CLOCKS \ - { \ - kCLOCK_Dma0, kCLOCK_Dma1 \ - } -/*! @brief Clock ip name array for CRC. */ -#define CRC_CLOCKS \ - { \ - kCLOCK_Crc0 \ - } -/*! @brief Clock ip name array for WWDT. */ -#define WWDT_CLOCKS \ - { \ - kCLOCK_Wwdt \ - } -/*! @brief Clock ip name array for RTC. */ -#define RTC_CLOCKS \ - { \ - kCLOCK_Rtc0 \ - } -/*! @brief Clock ip name array for Mailbox. */ -#define MAILBOX_CLOCKS \ - { \ - kCLOCK_Mailbox \ - } -/*! @brief Clock ip name array for LPADC. */ -#define LPADC_CLOCKS \ - { \ - kCLOCK_Adc0, kCLOCK_Adc1 \ - } -/*! @brief Clock ip name array for DAC. */ -#define LPDAC_CLOCKS \ - { \ - kCLOCK_Dac0, kCLOCK_Dac1, kCLOCK_Dac2 \ - } -/*! @brief Clock ip name array for MRT. */ -#define MRT_CLOCKS \ - { \ - kCLOCK_Mrt \ - } -/*! @brief Clock ip name array for OSTIMER. */ -#define OSTIMER_CLOCKS \ - { \ - kCLOCK_Ostimer \ - } -/*! @brief Clock ip name array for SCT0. */ -#define SCT_CLOCKS \ - { \ - kCLOCK_Sct \ - } -/*! @brief Clock ip name array for MCAN. */ -#define MCAN_CLOCKS \ - { \ - kCLOCK_Mcan \ - } -/*! @brief Clock ip name array for UTICK. */ -#define UTICK_CLOCKS \ - { \ - kCLOCK_Utick \ - } -/*! @brief Clock ip name array for FLEXCOMM. */ -#define FLEXCOMM_CLOCKS \ - { \ - kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \ - kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi \ - } -/*! @brief Clock ip name array for LPUART. */ -#define LPUART_CLOCKS \ - { \ - kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \ - kCLOCK_MinUart6, kCLOCK_MinUart7 \ - } - -/*! @brief Clock ip name array for BI2C. */ -#define BI2C_CLOCKS \ - { \ - kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \ - } -/*! @brief Clock ip name array for LSPI. */ -#define LPSPI_CLOCKS \ - { \ - kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \ - } -/*! @brief Clock ip name array for FLEXI2S. */ -#define FLEXI2S_CLOCKS \ - { \ - kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \ - kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \ - } -/*! @brief Clock ip name array for CTIMER. */ -#define CTIMER_CLOCKS \ - { \ - kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ - } -/*! @brief Clock ip name array for COMP */ -#define COMP_CLOCKS \ - { \ - kCLOCK_Comp \ - } -/*! @brief Clock ip name array for FREQME. */ -#define FREQME_CLOCKS \ - { \ - kCLOCK_Freqme \ - } -/*! @brief Clock ip name array for CDOG. */ -#define CDOG_CLOCKS \ - { \ - kCLOCK_Cdog \ - } -/*! @brief Clock ip name array for RNG. */ -#define RNG_CLOCKS \ - { \ - kCLOCK_Rng \ - } -/*! @brief Clock ip name array for USBHMR0. */ -#define USBHMR0_CLOCKS \ - { \ - kCLOCK_Usbhmr0 \ - } -/*! @brief Clock ip name array for USBHSL0. */ -#define USBHSL0_CLOCKS \ - { \ - kCLOCK_Usbhsl0 \ - } -/*! @brief Clock ip name array for ANALOGCTRL. */ -#define ANALOGCTRL_CLOCKS \ - { \ - kCLOCK_AnalogCtrl \ - } -/*! @brief Clock ip name array for HS_LSPI. */ -#define HS_LSPI_CLOCKS \ - { \ - kCLOCK_Hs_Lspi \ - } -/*! @brief Clock ip name array for GPIO_SEC. */ -#define GPIO_SEC_CLOCKS \ - { \ - kCLOCK_Gpio_Sec \ - } -/*! @brief Clock ip name array for GPIO_SEC_INT. */ -#define GPIO_SEC_INT_CLOCKS \ - { \ - kCLOCK_Gpio_Sec_Int \ - } -/*! @brief Clock ip name array for USBD. */ -#define USBD_CLOCKS \ - { \ - kCLOCK_Usbd0 \ - } -/*! @brief Clock ip name array for SYSCTL. */ -#define SYSCTL_CLOCKS \ - { \ - kCLOCK_Sysctl \ - } -/*! @brief Clock ip name array for DMIC. */ -#define DMIC_CLOCKS \ - { \ - kCLOCK_Dmic \ - } -/*! @brief Clock ip name array for PWM. */ -#define PWM_CLOCKS \ - { \ - {kCLOCK_Pwm0, kCLOCK_Pwm0, kCLOCK_Pwm0, kCLOCK_Pwm0}, \ - { \ - kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1 \ - } \ - } -/*! @brief Clock ip name array for ENC. */ -#define ENC_CLOCKS \ - { \ - kCLOCK_Enc0, kCLOCK_Enc1 \ - } -/*! @brief Clock ip name array for OPAMP. */ -#define OPAMP_CLOCKS \ - { \ - kCLOCK_Opamp0, kCLOCK_Opamp1, kCLOCK_Opamp2 \ - } -/*! @brief Clock ip name array for VREF. */ -#define VREF_CLOCKS \ - { \ - kCLOCK_Vref \ - } -/*! @brief Clock ip name array for FLEXSPI */ -#define FLEXSPI_CLOCKS \ - { \ - kCLOCK_Flexspi \ - } -/*! @brief Clock ip name array for Cache64 */ -#define CACHE64_CLOCKS \ - { \ - kCLOCK_Flexspi \ - } -/*! @brief Clock ip name array for I3C */ -#define I3C_CLOCKS \ - { \ - kCLOCK_I3c0 \ - } -/*! @brief Clock ip name array for HSCMP */ -#define HSCMP_CLOCKS \ - { \ - kCLOCK_Hscmp0, kCLOCK_Hscmp1, kCLOCK_Hscmp2 \ - } -/*! @brief Clock ip name array for PowerQuad. */ -#define POWERQUAD_CLOCKS \ - { \ - kCLOCK_PowerQuad \ - } -/*! @brief Clock ip name array for AOI. */ -#define AOI_CLOCKS \ - { \ - kCLOCK_Aoi0, kCLOCK_Aoi1 \ - } -/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ -/*------------------------------------------------------------------------------ - clock_ip_name_t definition: -------------------------------------------------------------------------------*/ - -#define CLK_GATE_REG_OFFSET_SHIFT 8U -#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U -#define CLK_GATE_BIT_SHIFT_SHIFT 0U -#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU - -#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ - ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ - (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) - -#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) -#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) - -#define AHB_CLK_CTRL0 0 -#define AHB_CLK_CTRL1 1 -#define AHB_CLK_CTRL2 2 -#define AHB_CLK_CTRL3 3 - -/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ -typedef enum _clock_ip_name -{ - kCLOCK_IpInvalid = 0U, /*!< Invalid IP name. */ - kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1U), /*!< Clock gate name: Rom. */ - - kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3U), /*!< Clock gate name: Sram1. */ - - kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4U), /*!< Clock gate name: Sram2. */ - - kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5U), /*!< Clock gate name: Sram3. */ - - kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6U), /*!< Clock gate name: Sram4. */ - - kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7U), /*!< Clock gate name: Flash. */ - - kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8U), /*!< Clock gate name: Fmc. */ - - kCLOCK_Flexspi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10U), /*!< Clock gate name: Flexspi. */ - - kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11U), /*!< Clock gate name: InputMux. */ - - kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13U), /*!< Clock gate name: Iocon. */ - - kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14U), /*!< Clock gate name: Gpio0. */ - - kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15U), /*!< Clock gate name: Gpio1. */ - - kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16U), /*!< Clock gate name: Gpio2. */ - - kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17U), /*!< Clock gate name: Gpio3. */ - - kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18U), /*!< Clock gate name: Pint. */ - - kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19U), /*!< Clock gate name: Gint. */ - - kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20U), /*!< Clock gate name: Dma0. */ - - kCLOCK_Crc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21U), /*!< Clock gate name: Crc. */ - - kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22U), /*!< Clock gate name: Wwdt. */ - - kCLOCK_Rtc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23U), /*!< Clock gate name: Rtc0. */ - - kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26U), /*!< Clock gate name: Mailbox. */ - - kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27U), /*!< Clock gate name: Adc0. */ - - kCLOCK_Adc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 28U), /*!< Clock gate name: Adc1. */ - - kCLOCK_Dac0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 29U), /*!< Clock gate name: Dac0. */ - - kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0U), /*!< Clock gate name: Mrt. */ - - kCLOCK_Ostimer = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1U), /*!< Clock gate name: Ostimer. */ - - kCLOCK_Sct = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2U), /*!< Clock gate name: Sct. */ - - kCLOCK_Mcan = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7U), /*!< Clock gate name: Mcan. */ - - kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10U), /*!< Clock gate name: Utick. */ - - kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11U), /*!< Clock gate name: FlexComm0. */ - - kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12U), /*!< Clock gate name: FlexComm1. */ - - kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13U), /*!< Clock gate name: FlexComm2. */ - - kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14U), /*!< Clock gate name: FlexComm3. */ - - kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15U), /*!< Clock gate name: FlexComm4. */ - - kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16U), /*!< Clock gate name: FlexComm5. */ - - kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17U), /*!< Clock gate name: FlexComm6. */ - - kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18U), /*!< Clock gate name: FlexComm7. */ - - kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: MinUart0. */ - - kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: MinUart1. */ - - kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: MinUart2. */ - - kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: MinUart3. */ - - kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: MinUart4. */ - - kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: MinUart5. */ - - kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: MinUart6. */ - - kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: MinUart7. */ - - kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LSpi0. */ - - kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LSpi1. */ - - kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LSpi2. */ - - kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LSpi3. */ - - kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LSpi4. */ - - kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LSpi5. */ - - kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LSpi6. */ - - kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LSpi7. */ - - kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: BI2c0. */ - - kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: BI2c1. */ - - kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: BI2c2. */ - - kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: BI2c3. */ - - kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: BI2c4. */ - - kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: BI2c5. */ - - kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: BI2c6. */ - - kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: BI2c7. */ - - kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexI2s0. */ - - kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexI2s1. */ - - kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexI2s2. */ - - kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexI2s3. */ - - kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexI2s4. */ - - kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexI2s5. */ - - kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexI2s6. */ - - kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexI2s7. */ - - kCLOCK_Dmic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19U), /*!< Clock gate name: Dmic. */ - - kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22U), /*!< Clock gate name: Timer2. */ - - kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25U), /*!< Clock gate name: Usbd0. */ - - kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26U), /*!< Clock gate name: Timer0. */ - - kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27U), /*!< Clock gate name: Timer1. */ - - kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1U), /*!< Clock gate name: Dma1. */ - - kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2U), /*!< Clock gate name: Comp. */ - - kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8U), /*!< Clock gate name: Freqme. */ - - kCLOCK_Cdog = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11U), /*!< Clock gate name: Cdog. */ - - kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13U), /*!< Clock gate name: Rng. */ - - kCLOCK_Pmux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14U), /*!< Clock gate name: Pmux1. */ - - kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15U), /*!< Clock gate name: Sysctl. */ - - kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16U), /*!< Clock gate name: Usbhmr0. */ - - kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17U), /*!< Clock gate name: Usbhsl0. */ - - kCLOCK_Css = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18U), /*!< Clock gate name: Css. */ - - kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19U), /*!< Clock gate name: PowerQuad. */ - - kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21U), /*!< Clock gate name: Timer3. */ - - kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22U), /*!< Clock gate name: Timer4. */ - - kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23U), /*!< Clock gate name: Puf. */ - - kCLOCK_Pkc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24U), /*!< Clock gate name: Pkc. */ - - kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27U), /*!< Clock gate name: AnalogCtrl. */ - - kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28U), /*!< Clock gate name: Lspi. */ - - kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29U), /*!< Clock gate name: Sec. */ - - kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30U), /*!< Clock gate name: Int. */ - - kCLOCK_I3c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 0U), /*!< Clock gate name: I3c0. */ - - kCLOCK_Enc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 3U), /*!< Clock gate name: Enc0. */ - - kCLOCK_Enc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 4U), /*!< Clock gate name: Enc1. */ - - kCLOCK_Pwm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 5U), /*!< Clock gate name: Pwm0. */ - - kCLOCK_Pwm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 6U), /*!< Clock gate name: Pwm1. */ - - kCLOCK_Aoi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 7U), /*!< Clock gate name: Aoi0. */ - - kCLOCK_Aoi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 8U), /*!< Clock gate name: Aoi1. */ - - kCLOCK_Ftm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 9U), /*!< Clock gate name: Ftm0. */ - - kCLOCK_Dac1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 10U), /*!< Clock gate name: Dac1. */ - - kCLOCK_Dac2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 11U), /*!< Clock gate name: Dac2. */ - - kCLOCK_Opamp0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 12U), /*!< Clock gate name: Opamp0. */ - - kCLOCK_Opamp1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 13U), /*!< Clock gate name: Opamp1. */ - - kCLOCK_Opamp2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 14U), /*!< Clock gate name: Opamp2. */ - - kCLOCK_Hscmp0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 15U), /*!< Clock gate name: Hscmp0. */ - - kCLOCK_Hscmp1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 16U), /*!< Clock gate name: Hscmp1. */ - - kCLOCK_Hscmp2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 17U), /*!< Clock gate name: Hscmp2. */ - - kCLOCK_Vref = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 18U) /*!< Clock gate name: Vref. */ - -} clock_ip_name_t; - -/*! @brief Peripherals clock source definition. */ -#define BUS_CLK kCLOCK_BusClk - -#define I2C0_CLK_SRC BUS_CLK - -/*! @brief Clock name used to get clock frequency. */ -typedef enum _clock_name -{ - kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ - kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ - kCLOCK_ClockOut, /*!< CLOCKOUT */ - kCLOCK_FroHf, /*!< FRO48/96 */ - kCLOCK_Pll1Out, /*!< PLL1 Output */ - kCLOCK_Mclk, /*!< MCLK */ - kCLOCK_Fro12M, /*!< FRO12M */ - kCLOCK_Fro1M, /*!< FRO1M */ - kCLOCK_ExtClk, /*!< External Clock */ - kCLOCK_Pll0Out, /*!< PLL0 Output */ - kCLOCK_PllClkDiv, /*!< PLLCLKDIV clock */ - kCLOCK_FlexI2S, /*!< FlexI2S clock */ -} clock_name_t; - -/*! @brief Clock Mux Switches - * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable - * starting from LSB upwards - * - * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* - * - */ - -#define CLK_ATTACH_ID(mux, sel, pos) \ - ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 12U) << ((uint32_t)(pos)*16U)) -#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U) -#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U)) - -#define GET_ID_ITEM(connection) ((connection)&0xFFFFU) -#define GET_ID_NEXT_ITEM(connection) ((connection) >> 16U) -#define GET_ID_ITEM_MUX(connection) (((uint16_t)connection) & 0xFFFU) -#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF000U) >> 12U) - 1U)) -#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) - -#define CM_SYSTICKCLKSEL0 (0) -#define CM_TRACECLKSEL (2) -#define CM_CTIMERCLKSEL0 (3) -#define CM_CTIMERCLKSEL1 (4) -#define CM_CTIMERCLKSEL2 (5) -#define CM_CTIMERCLKSEL3 (6) -#define CM_CTIMERCLKSEL4 (7) -#define CM_MAINCLKSELA (8) -#define CM_MAINCLKSELB (9) -#define CM_CLKOUTCLKSEL (10) -#define CM_PLL0CLKSEL (12) -#define CM_PLL1CLKSEL (13) -#define CM_MCANCLKSEL (16) -#define CM_ADC0CLKSEL (17) -#define CM_USB0CLKSEL (18) -#define CM_FXCOMCLKSEL0 (20) -#define CM_FXCOMCLKSEL1 (21) -#define CM_FXCOMCLKSEL2 (22) -#define CM_FXCOMCLKSEL3 (23) -#define CM_FXCOMCLKSEL4 (24) -#define CM_FXCOMCLKSEL5 (25) -#define CM_FXCOMCLKSEL6 (26) -#define CM_FXCOMCLKSEL7 (27) -#define CM_HSLSPICLKSEL (28) -#define CM_MCLKCLKSEL (32) -#define CM_SCTCLKSEL (36) - -#define CM_ADC1CLKSEL ((0x464 - 0x260) / 4) -#define CM_DAC0CLKSEL ((0x490 - 0x260) / 4) -#define CM_DAC1CLKSEL ((0x498 - 0x260) / 4) -#define CM_DAC2CLKSEL ((0x4A0 - 0x260) / 4) -#define CM_FLEXSPICLKSEL ((0x4A8 - 0x260) / 4) -#define CM_PLLCLKDIVSEL ((0x52C - 0x260) / 4) -#define CM_I3CFCLKSEL ((0x530 - 0x260) / 4) -#define CM_I3CFCLKSTCSEL ((0x534 - 0x260) / 4) -#define CM_I3CFCLKSSEL ((0x534 - 0x260) / 4) -#define CM_DMICFCLKSEL ((0x548 - 0x260) / 4) -#define CM_FC32KCLKSEL ((0x82C - 0x260) / 4) -#define CM_FRGCLKSEL0 ((0x830 - 0x260) / 4) -#define CM_FRGCLKSEL1 ((0x834 - 0x260) / 4) -#define CM_FRGCLKSEL2 ((0x838 - 0x260) / 4) -#define CM_FRGCLKSEL3 ((0x83C - 0x260) / 4) -#define CM_FRGCLKSEL4 ((0x840 - 0x260) / 4) -#define CM_FRGCLKSEL5 ((0x844 - 0x260) / 4) -#define CM_FRGCLKSEL6 ((0x848 - 0x260) / 4) -#define CM_FRGCLKSEL7 ((0x84C - 0x260) / 4) - -#define CM_OSTIMERCLKSEL (252U) -#define CM_RTCOSC32KCLKSEL (253U) - -typedef enum _clock_attach_id -{ - - kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO12M to MAIN_CLK. */ - kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach EXT_CLK to MAIN_CLK. */ - kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO1M to MAIN_CLK. */ - kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO_HF to MAIN_CLK. */ - kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0), /*!< Attach PLL0 to MAIN_CLK. */ - kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), /*!< Attach PLL1 to MAIN_CLK. */ - kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), /*!< Attach OSC32K to MAIN_CLK. */ - - kSYSTICK_DIV_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), /*!< Attach SYSTICK_DIV to SYSTICK0. */ - kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), /*!< Attach FRO1M to SYSTICK0. */ - kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), /*!< Attach OSC32K to SYSTICK0. */ - kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), /*!< Attach NONE to SYSTICK0. */ - - kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), /*!< Attach TRACE_DIV to TRACE. */ - kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), /*!< Attach FRO1M to TRACE. */ - kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), /*!< Attach OSC32K to TRACE. */ - kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), /*!< Attach NONE to TRACE. */ - - kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), /*!< Attach MAIN_CLK to CTIMER0. */ - kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), /*!< Attach PLL0 to CTIMER0. */ - kPLL1_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 2), /*!< Attach PLL1 to CTIMER0. */ - kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), /*!< Attach FRO_HF to CTIMER0. */ - kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), /*!< Attach FRO1M to CTIMER0. */ - kMCLK_IN_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), - kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), /*!< Attach OSC32K to CTIMER0. */ - kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7), /*!< Attach NONE to CTIMER0. */ - - kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), /*!< Attach MAIN_CLK to CTIMER1. */ - kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), /*!< Attach PLL0 to CTIMER1. */ - kPLL1_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 2), /*!< Attach PLL1 to CTIMER1. */ - kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), /*!< Attach FRO_HF to CTIMER1. */ - kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), /*!< Attach FRO1M to CTIMER1. */ - kMCLK_IN_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), /*!< Attach MCLK_IN to CTIMER1. */ - kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), /*!< Attach OSC32K to CTIMER1. */ - kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7), /*!< Attach NONE to CTIMER1. */ - - kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), /*!< Attach MAIN_CLK to CTIMER2. */ - kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), /*!< Attach PLL0 to CTIMER2. */ - kPLL1_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 2), /*!< Attach PLL1 to CTIMER2. */ - kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), /*!< Attach FRO_HF to CTIMER2. */ - kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), /*!< Attach FRO1M to CTIMER2. */ - kMCLK_IN_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), /*!< Attach MCLK_IN to CTIMER2. */ - kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), /*!< Attach OSC32K to CTIMER2. */ - kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7), /*!< Attach NONE to CTIMER2. */ - - kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), /*!< Attach MAIN_CLK to CTIMER3. */ - kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), /*!< Attach PLL0 to CTIMER3. */ - kPLL1_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 2), /*!< Attach PLL1 to CTIMER3. */ - kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), /*!< Attach FRO_HF to CTIMER3. */ - kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), /*!< Attach FRO1M to CTIMER3. */ - kMCLK_IN_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), /*!< Attach MCLK_IN to CTIMER3. */ - kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), /*!< Attach OSC32K to CTIMER3. */ - kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7), /*!< Attach NONE to CTIMER3. */ - - kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), /*!< Attach MAIN_CLK to CTIMER4. */ - kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), /*!< Attach PLL0 to CTIMER4. */ - kPLL1_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 2), /*!< Attach PLL1 to CTIMER4. */ - kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), /*!< Attach FRO_HF to CTIMER4. */ - kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), /*!< Attach FRO1M to CTIMER4. */ - kMCLK_IN_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), /*!< Attach MCLK_IN to CTIMER4. */ - kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), /*!< Attach OSC32K to CTIMER4. */ - kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7), /*!< Attach NONE to CTIMER4. */ - - kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Attach MAIN_CLK to CLKOUT. */ - kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Attach PLL0 to CLKOUT. */ - kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Attach EXT_CLK to CLKOUT. */ - kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Attach FRO_HF to CLKOUT. */ - kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Attach FRO1M to CLKOUT. */ - kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Attach PLL1 to CLKOUT. */ - kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Attach OSC32K to CLKOUT. */ - kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< Attach NONE to CLKOUT. */ - - kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0), /*!< Attach FRO12M to PLL0. */ - kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1), /*!< Attach EXT_CLK to PLL0. */ - kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2), /*!< Attach FRO1M to PLL0. */ - kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3), /*!< Attach OSC32K to PLL0. */ - kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7), /*!< Attach NONE to PLL0. */ - - kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0), /*!< Attach FRO12M to PLL1. */ - kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1), /*!< Attach EXT_CLK to PLL1. */ - kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2), /*!< Attach FRO1M to PLL1. */ - kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3), /*!< Attach OSC32K to PLL1. */ - kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7), /*!< Attach NONE to PLL1. */ - - kMCAN_DIV_to_MCAN = MUX_A(CM_MCANCLKSEL, 0), /*!< Attach MCAN_DIV to MCAN. */ - kFRO1M_to_MCAN = MUX_A(CM_MCANCLKSEL, 1), /*!< Attach FRO1M to MCAN. */ - kOSC32K_to_MCAN = MUX_A(CM_MCANCLKSEL, 2), /*!< Attach OSC32K to MCAN. */ - kNONE_to_MCAN = MUX_A(CM_MCANCLKSEL, 7), /*!< Attach NONE to MCAN. */ - - kMAIN_CLK_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 0), /*!< Attach MAIN_CLK to ADC0. */ - kPLL0_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 1), /*!< Attach PLL0 to ADC0. */ - kFRO_HF_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 2), /*!< Attach FRO_HF to ADC0. */ - kEXT_CLK_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 4), /*!< Attach XO to ADC0. */ - kNONE_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 7), /*!< Attach NONE to ADC0. */ - - kMAIN_CLK_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 0), /*!< Attach MAIN_CLK to ADC1. */ - kPLL0_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 1), /*!< Attach PLL0 to ADC1. */ - kFRO_HF_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 2), /*!< Attach FRO_HF to ADC1. */ - kNONE_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 7), /*!< Attach NONE to ADC1. */ - - kMAIN_CLK_to_USB0 = MUX_A(CM_USB0CLKSEL, 0), /*!< Attach MAIN_CLK to USB0. */ - kPLL0_to_USB0 = MUX_A(CM_USB0CLKSEL, 1), /*!< Attach PLL0 to USB0. */ - kFRO_HF_to_USB0 = MUX_A(CM_USB0CLKSEL, 3), /*!< Attach FRO_HF to USB0. */ - kPLL1_to_USB0 = MUX_A(CM_USB0CLKSEL, 5), /*!< Attach PLL1 to USB0. */ - kNONE_to_USB0 = MUX_A(CM_USB0CLKSEL, 7), /*!< Attach NONE to USB0. */ - - kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), /*!< Attach MAIN_CLK to FLEXCOMM0. */ - kMAIN_CLK_FRG0_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1) | MUX_B(CM_FRGCLKSEL0, 0, 0), /*!< Attach Main clock - to FlexComm0. */ - kPLL_CLK_DIV_FRG0_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1) | MUX_B(CM_FRGCLKSEL0, 1, 0), /*!< Attach PLL clock - DIV Frg to FlexComm0. */ - kFRO_HF_DIV_FRG0_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1) | MUX_B(CM_FRGCLKSEL0, 2, 0), /*!< Attach FRO HF DIV - FRG to FlexComm0. */ - kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), /*!< Attach FRO12M to FLEXCOMM0. */ - kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM0. */ - kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), /*!< Attach FRO1M to FLEXCOMM0. */ - kMCLK_IN_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5), /*!< Attach MCLK_IN to FLEXCOMM0. */ - kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6), /*!< Attach OSC32K to FLEXCOMM0. */ - kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */ - - kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), /*!< Attach MAIN_CLK to FLEXCOMM1. */ - kMAIN_CLK_FRG1_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1) | MUX_B(CM_FRGCLKSEL1, 0, 0), /*!< Attach Main clock - to FlexComm1. */ - kPLL_CLK_DIV_FRG1_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1) | MUX_B(CM_FRGCLKSEL1, 1, 0), /*!< Attach PLL clock - DIV Frg to FlexComm1. */ - kFRO_HF_DIV_FRG1_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1) | MUX_B(CM_FRGCLKSEL1, 2, 0), /*!< Attach FRO HF DIV - FRG to FlexComm1. */ - kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), /*!< Attach FRO12M to FLEXCOMM1. */ - kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM1. */ - kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), /*!< Attach FRO1M to FLEXCOMM1. */ - kMCLK_IN_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5), /*!< Attach MCLK_IN to FLEXCOMM1. */ - kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6), /*!< Attach OSC32K to FLEXCOMM1. */ - kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */ - - kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), /*!< Attach MAIN_CLK to FLEXCOMM2. */ - kMAIN_CLK_FRG2_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1) | MUX_B(CM_FRGCLKSEL2, 0, 0), /*!< Attach Main clock - to FlexComm2. */ - kPLL_CLK_DIV_FRG2_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1) | MUX_B(CM_FRGCLKSEL2, 1, 0), /*!< Attach PLL clock - DIV Frg to FlexComm2. */ - kFRO_HF_DIV_FRG2_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1) | MUX_B(CM_FRGCLKSEL2, 2, 0), /*!< Attach FRO HF DIV - FRG to FlexComm2. */ - kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), /*!< Attach FRO12M to FLEXCOMM2. */ - kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM2. */ - kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), /*!< Attach FRO1M to FLEXCOMM2. */ - kMCLK_IN_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5), /*!< Attach MCLK_IN to FLEXCOMM2. */ - kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6), /*!< Attach OSC32K to FLEXCOMM2. */ - kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */ - - kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), /*!< Attach MAIN_CLK to FLEXCOMM3. */ - kMAIN_CLK_FRG3_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1) | MUX_B(CM_FRGCLKSEL3, 0, 0), /*!< Attach Main clock - to FlexComm3. */ - kPLL_CLK_DIV_FRG3_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1) | MUX_B(CM_FRGCLKSEL3, 1, 0), /*!< Attach PLL clock - DIV Frg to FlexComm3. */ - kFRO_HF_DIV_FRG3_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1) | MUX_B(CM_FRGCLKSEL3, 2, 0), /*!< Attach FRO HF DIV - FRG to FlexComm3. */ - kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), /*!< Attach FRO12M to FLEXCOMM3. */ - kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM3. */ - kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), /*!< Attach FRO1M to FLEXCOMM3. */ - kMCLK_IN_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5), /*!< Attach MCLK_IN to FLEXCOMM3. */ - kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6), /*!< Attach OSC32K to FLEXCOMM3. */ - kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */ - - kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), /*!< Attach MAIN_CLK to FLEXCOMM4. */ - kMAIN_CLK_FRG4_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1) | MUX_B(CM_FRGCLKSEL4, 0, 0), /*!< Attach Main clock - to FlexComm4. */ - kPLL_CLK_DIV_FRG4_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1) | MUX_B(CM_FRGCLKSEL4, 1, 0), /*!< Attach PLL clock - DIV Frg to FlexComm4. */ - kFRO_HF_DIV_FRG4_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1) | MUX_B(CM_FRGCLKSEL4, 2, 0), /*!< Attach FRO HF DIV - FRG to FlexComm4. */ - kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), /*!< Attach FRO12M to FLEXCOMM4. */ - kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM4. */ - kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), /*!< Attach FRO1M to FLEXCOMM4. */ - kMCLK_IN_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5), /*!< Attach MCLK_IN to FLEXCOMM4. */ - kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6), /*!< Attach OSC32K to FLEXCOMM4. */ - kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */ - - kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), /*!< Attach MAIN_CLK to FLEXCOMM5. */ - kMAIN_CLK_FRG5_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1) | MUX_B(CM_FRGCLKSEL5, 0, 0), /*!< Attach Main clock - to FlexComm5. */ - kPLL_CLK_DIV_FRG5_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1) | MUX_B(CM_FRGCLKSEL5, 1, 0), /*!< Attach PLL clock - DIV Frg to FlexComm5. */ - kFRO_HF_DIV_FRG5_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1) | MUX_B(CM_FRGCLKSEL5, 2, 0), /*!< Attach FRO HF DIV - FRG to FlexComm5. */ - kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), /*!< Attach FRO12M to FLEXCOMM5. */ - kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM5. */ - kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), /*!< Attach FRO1M to FLEXCOMM5. */ - kMCLK_IN_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5), /*!< Attach MCLK_IN to FLEXCOMM5. */ - kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6), /*!< Attach OSC32K to FLEXCOMM5. */ - kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */ - - kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), /*!< Attach MAIN_CLK to FLEXCOMM6. */ - kMAIN_CLK_FRG6_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1) | MUX_B(CM_FRGCLKSEL6, 0, 0), /*!< Attach Main clock - to FlexComm6. */ - kPLL_CLK_DIV_FRG6_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1) | MUX_B(CM_FRGCLKSEL6, 1, 0), /*!< Attach PLL clock - DIV Frg to FlexComm6. */ - kFRO_HF_DIV_FRG6_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1) | MUX_B(CM_FRGCLKSEL6, 2, 0), /*!< Attach FRO HF DIV - FRG to FlexComm6. */ - kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), /*!< Attach FRO12M to FLEXCOMM6. */ - kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM6. */ - kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), /*!< Attach FRO1M to FLEXCOMM6. */ - kMCLK_IN_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5), /*!< Attach MCLK_IN to FLEXCOMM6. */ - kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6), /*!< Attach OSC32K to FLEXCOMM6. */ - kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */ - - kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), /*!< Attach MAIN_CLK to FLEXCOMM7. */ - kMAIN_CLK_FRG7_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1) | MUX_B(CM_FRGCLKSEL7, 0, 0), /*!< Attach Main clock - to FlexComm7. */ - kPLL_CLK_DIV_FRG7_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1) | MUX_B(CM_FRGCLKSEL7, 1, 0), /*!< Attach PLL clock - DIV Frg to FlexComm7. */ - kFRO_HF_DIV_FRG7_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1) | MUX_B(CM_FRGCLKSEL7, 2, 0), /*!< Attach PLL clock - DIV Frg to FlexComm7. */ - kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), /*!< Attach FRO12M to FLEXCOMM7. */ - kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM7. */ - kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), /*!< Attach FRO1M to FLEXCOMM7. */ - kMCLK_IN_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5), /*!< Attach MCLK_IN to FLEXCOMM7. */ - kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6), /*!< Attach OSC32K to FLEXCOMM7. */ - kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */ - - kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0), /*!< Attach MAIN_CLK to HSLSPI. */ - kPLL_CLK_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1), /*!< Attach PLL_CLK_DIV to HSLSPI. */ - kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2), /*!< Attach FRO12M to HSLSPI. */ - kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3), /*!< Attach FRO_HF_DIV to HSLSPI. */ - kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4), /*!< Attach FRO1M to HSLSPI. */ - kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6), /*!< Attach OSC32K to HSLSPI. */ - kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7), /*!< Attach NONE to HSLSPI. */ - - kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), /*!< Attach FRO_HF to MCLK. */ - kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), /*!< Attach PLL0 to MCLK. */ - kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), /*!< Attach NONE to MCLK. */ - - kMAIN_CLK_to_SCT = MUX_A(CM_SCTCLKSEL, 0), /*!< Attach MAIN_CLK to SCT. */ - kPLL0_to_SCT = MUX_A(CM_SCTCLKSEL, 1), /*!< Attach PLL0 to SCT. */ - kEXT_CLK_to_SCT = MUX_A(CM_SCTCLKSEL, 2), /*!< Attach EXT_CLK to SCT. */ - kFRO_HF_to_SCT = MUX_A(CM_SCTCLKSEL, 3), /*!< Attach FRO_HF to SCT. */ - kPLL1_to_SCT = MUX_A(CM_SCTCLKSEL, 4), /*!< Attach PLL1 to SCT. */ - kMCLK_IN_to_SCT = MUX_A(CM_SCTCLKSEL, 5), /*!< Attach MCLK_IN to SCT. */ - kNONE_to_SCT = MUX_A(CM_SCTCLKSEL, 7), /*!< Attach NONE to SCT. */ - - kMAIN_CLK_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 0), /*!< Attach MAIN_CLK to DAC0. */ - kPLL0_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 1), /*!< Attach PLL0 to DAC0. */ - kFRO_HF_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 3), /*!< Attach FRO_HF to DAC0. */ - kFRO12M_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 4), /*!< Attach FRO12M to DAC0. */ - kPLL1_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 5), /*!< Attach PLL1 to DAC0. */ - kFRO1M_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 6), /*!< Attach FRO1M to DAC0. */ - kNONE_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 7), /*!< Attach NONE to DAC0. */ - - kMAIN_CLK_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 0), /*!< Attach MAIN_CLK to DAC1. */ - kPLL0_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 1), /*!< Attach PLL0 to DAC1. */ - kFRO_HF_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 3), /*!< Attach FRO_HF to DAC1. */ - kFRO12M_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 4), /*!< Attach FRO12M to DAC1. */ - kPLL1_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 5), /*!< Attach PLL1 to DAC1. */ - kFRO1M_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 6), /*!< Attach FRO1M to DAC1. */ - kNONE_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 7), /*!< Attach NONE to DAC1. */ - - kMAIN_CLK_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 0), /*!< Attach MAIN_CLK to DAC2. */ - kPLL0_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 1), /*!< Attach PLL0 to DAC2. */ - kFRO_HF_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 3), /*!< Attach FRO_HF to DAC2. */ - kFRO12M_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 4), /*!< Attach FRO12M to DAC2. */ - kPLL1_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 5), /*!< Attach PLL1 to DAC2. */ - kFRO1M_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 6), /*!< Attach FRO1M to DAC2. */ - kNONE_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 7), /*!< Attach NONE to DAC2. */ - - kMAIN_CLK_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 0), /*!< Attach MAIN_CLK to FLEXSPI. */ - kPLL0_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 1), /*!< Attach PLL0 to FLEXSPI. */ - kFRO_HF_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 3), /*!< Attach FRO_HF to FLEXSPI. */ - kPLL1_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 5), /*!< Attach PLL1 to FLEXSPI. */ - kNONE_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 7), /*!< Attach NONE to FLEXSPI. */ - - kPLL0_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 0), /*!< Attach PLL0 to PLLCLKDIV. */ - kPLL1_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 1), /*!< Attach PLL1 to PLLCLKDIV. */ - kNONE_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 7), /*!< Attach NONE to PLLCLKDIV. */ - - kMAIN_CLK_to_I3CFCLK = MUX_A(CM_I3CFCLKSEL, 0), /*!< Attach MAIN_CLK to I3CFCLK. */ - kFRO_HF_DIV_to_I3CFCLK = MUX_A(CM_I3CFCLKSEL, 1), /*!< Attach FRO_HF_DIV to I3CFCLK. */ - kNONE_to_I3CFCLK = MUX_A(CM_I3CFCLKSEL, 7), /*!< Attach NONE to I3CFCLK. */ - - kI3CFCLKSEL_to_I3CFCLKSTC = MUX_A(CM_I3CFCLKSTCSEL, 0), /*!< Attach I3CFCLKSEL to I3CFCLKSTC. */ - kFRO1M_to_I3CFCLKSTC = MUX_A(CM_I3CFCLKSTCSEL, 1), /*!< Attach FRO1M to I3CFCLKSTC. */ - kNONE_to_I3CFCLKSTC = MUX_A(CM_I3CFCLKSTCSEL, 7), /*!< Attach NONE to I3CFCLKSTC. */ - - kMAIN_CLK_to_DMIC = MUX_A(CM_DMICFCLKSEL, 0), /*!< Attach MAIN_CLK to DMIC. */ - kPLL0_to_DMIC = MUX_A(CM_DMICFCLKSEL, 1), /*!< Attach PLL0 to DMIC. */ - kEXT_CLK_to_DMIC = MUX_A(CM_DMICFCLKSEL, 2), /*!< Attach EXT_CLK to DMIC. */ - kFRO_HF_to_DMIC = MUX_A(CM_DMICFCLKSEL, 3), /*!< Attach FRO_HF to DMIC. */ - kPLL1_to_DMIC = MUX_A(CM_DMICFCLKSEL, 2), /*!< Attach PLL1 to DMIC. */ - kMCLK_IN_to_DMIC = MUX_A(CM_DMICFCLKSEL, 5), /*!< Attach MCLK_IN to DMIC. */ - kNONE_to_DMIC = MUX_A(CM_DMICFCLKSEL, 7), /*!< Attach NONE to DMIC. */ - - kFRO32K_to_FCOSC32K = MUX_A(CM_FC32KCLKSEL, 0), /*!< Attach FRO32K to FCOSC32K. */ - kXTAL32K_to_FCOSC32K = MUX_A(CM_FC32KCLKSEL, 1), /*!< Attach XTAL32K to FCOSC32K. */ - kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0), /*!< Attach FRO32K to OSC32K. */ - kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1), /*!< Attach XTAL32K to OSC32K. */ - kFRO32K_to_FC32K = MUX_A(CM_FC32KCLKSEL, 0), /*!< Attach FRO32K to FC32K. */ - kXTAL32K_to_FC32K = MUX_A(CM_FC32KCLKSEL, 1), /*!< Attach XTAL32K to FC32K. */ - - kFRO32K_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 0), /*!< Attach FRO32K to OSTIMER. */ - kOSC32K_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 1), /*!< Attach OSC32K to OSTIMER. */ - kFRO1M_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 2), /*!< Attach FRO1M to OSTIMER. */ - kAHB_CLK_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 3), /*!< Attach AHB_CLK to OSTIMER. */ - - kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */ - -} clock_attach_id_t; - -/* Clock dividers */ -typedef enum _clock_div_name -{ - kCLOCK_DivSystickClk = (0), /*!< Systick Clock Divider. */ - kCLOCK_DivArmTrClkDiv = ((0x308 - 0x300) / 4), /*!< Trace Clock Divider. */ - kCLOCK_DivCanClk = ((0x30C - 0x300) / 4), /*!< Can Clock Divider. */ - kCLOCK_DivFlexFrg0 = ((0x320 - 0x300) / 4), /*!< FRGCTRL0 register. */ - kCLOCK_DivFlexFrg1 = ((0x324 - 0x300) / 4), /*!< FRGCTRL1 register. */ - kCLOCK_DivFlexFrg2 = ((0x328 - 0x300) / 4), /*!< FRGCTRL2 register. */ - kCLOCK_DivFlexFrg3 = ((0x32C - 0x300) / 4), /*!< FRGCTRL3 register. */ - kCLOCK_DivFlexFrg4 = ((0x330 - 0x300) / 4), /*!< FRGCTRL4 register. */ - kCLOCK_DivFlexFrg5 = ((0x334 - 0x300) / 4), /*!< FRGCTRL5 register. */ - kCLOCK_DivFlexFrg6 = ((0x338 - 0x300) / 4), /*!< FRGCTRL6 register. */ - kCLOCK_DivFlexFrg7 = ((0x33C - 0x300) / 4), /*!< FRGCTRL7 register. */ - kCLOCK_DivAhbClk = ((0x380 - 0x300) / 4), /*!< Ahb Clock Divider. */ - kCLOCK_DivClkOut = ((0x384 - 0x300) / 4), /*!< Clk Out Divider. */ - kCLOCK_DivFrohfClk = ((0x388 - 0x300) / 4), /*!< Frohf Divider. */ - kCLOCK_DivWdtClk = ((0x38C - 0x300) / 4), /*!< Wdt Clock Divider. */ - kCLOCK_DivAdc0Clk = ((0x394 - 0x300) / 4), /*!< Adc0 Clock Divider. */ - kCLOCK_DivUsb0Clk = ((0x398 - 0x300) / 4), /*!< Usb0 Clock Divider. */ - kCLOCK_DivMclk = ((0x3AC - 0x300) / 4), /*!< Mclk Divider. */ - kCLOCK_DivSctClk = ((0x3B4 - 0x300) / 4), /*!< Sct Clock Divider. */ - kCLOCK_DivPllClk = ((0x3C4 - 0x300) / 4), /*!< Pll0 Clock Divider. */ - kCLOCK_DivCtimer0Clk = ((0x3D0 - 0x300) / 4), /*!< Ctimer0 Clock Divider. */ - kCLOCK_DivCtimer1Clk = ((0x3D4 - 0x300) / 4), /*!< Ctimer1 Clock Divider. */ - kCLOCK_DivCtimer2Clk = ((0x3D8 - 0x300) / 4), /*!< Ctimer2 Clock Divider. */ - kCLOCK_DivCtimer3Clk = ((0x3DC - 0x300) / 4), /*!< Ctimer3 Clock Divider. */ - kCLOCK_DivCtimer4Clk = ((0x3E0 - 0x300) / 4), /*!< Ctimer4 Clock Divider. */ - kCLOCK_DivAdc1Clk = ((0x468 - 0x300) / 4), /*!< Adc1 Clock Divider. */ - kCLOCK_DivDac0Clk = ((0x494 - 0x300) / 4), /*!< Dac0 Clock Divider. */ - kCLOCK_DivDac1Clk = ((0x49C - 0x300) / 4), /*!< Dac1 Clock Divider. */ - kCLOCK_DivDac2Clk = ((0x4A4 - 0x300) / 4), /*!< Dac2 Clock Divider. */ - kCLOCK_DivFlexSpiClk = ((0x4AC - 0x300) / 4), /*!< Flex Spi Clock Divider. */ - kCLOCK_DivI3cFclkStc = ((0x538 - 0x300) / 4), /*!< I3c Fclk Stc Divider. */ - kCLOCK_DivI3cFclkS = ((0x53C - 0x300) / 4), /*!< I3c Fclk S Divider. */ - kCLOCK_DivI3cFclk = ((0x540 - 0x300) / 4), /*!< I3c Fclk Divider. */ - kCLOCK_DivDmicClk = ((0x54C - 0x300) / 4), /*!< Dmic Clock Divider. */ - kCLOCK_DivFlexcom0Clk = ((0x850 - 0x300) / 4), /*!< Flexcom0 Clock Divider. */ - kCLOCK_DivFlexcom1Clk = ((0x854 - 0x300) / 4), /*!< Flexcom1 Clock Divider. */ - kCLOCK_DivFlexcom2Clk = ((0x858 - 0x300) / 4), /*!< Flexcom2 Clock Divider. */ - kCLOCK_DivFlexcom3Clk = ((0x85C - 0x300) / 4), /*!< Flexcom3 Clock Divider. */ - kCLOCK_DivFlexcom4Clk = ((0x860 - 0x300) / 4), /*!< Flexcom4 Clock Divider. */ - kCLOCK_DivFlexcom5Clk = ((0x864 - 0x300) / 4), /*!< Flexcom5 Clock Divider. */ - kCLOCK_DivFlexcom6Clk = ((0x868 - 0x300) / 4), /*!< Flexcom6 Clock Divider. */ - kCLOCK_DivFlexcom7Clk = ((0x86C - 0x300) / 4), /*!< Flexcom7 Clock Divider. */ -} clock_div_name_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ -/** - * @brief Enable the clock for specific IP. - * @param clk : Clock to be enabled. - * @return Nothing - */ -static inline void CLOCK_EnableClock(clock_ip_name_t clk) -{ - uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); -} -/** - * @brief Disable the clock for specific IP. - * @param clk : Clock to be Disabled. - * @return Nothing - */ -static inline void CLOCK_DisableClock(clock_ip_name_t clk) -{ - uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); -} -/** - * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). - * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is - * enabled. - * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ) - * @return returns success or fail status. - */ -status_t CLOCK_SetupFROClocking(uint32_t iFreq); -/** - * @brief Set the flash wait states for the input freuqency. - * @param system_freq_hz : Input frequency - * @return Nothing - */ -void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz); -/** - * @brief Initialize the external osc clock to given frequency. - * @param iFreq : Desired frequency (must be equal to exact rate in Hz) - * @return returns success or fail status. - */ -status_t CLOCK_SetupExtClocking(uint32_t iFreq); -/** - * @brief Initialize the I2S MCLK clock to given frequency. - * @param iFreq : Desired frequency (must be equal to exact rate in Hz) - * @return returns success or fail status. - */ -status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq); -/** - * @brief Initialize the PLU CLKIN clock to given frequency. - * @param iFreq : Desired frequency (must be equal to exact rate in Hz) - * @return returns success or fail status. - */ -status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq); -/** - * @brief Configure the clock selection muxes. - * @param connection : Clock to be configured. - * @return Nothing - */ -void CLOCK_AttachClk(clock_attach_id_t connection); -/** - * @brief Get the actual clock attach id. - * This fuction uses the offset in input attach id, then it reads the actual source value in - * the register and combine the offset to obtain an actual attach id. - * @param attachId : Clock attach id to get. - * @return Clock source value. - */ -clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId); -/** - * @brief Setup peripheral clock dividers. - * @param div_name : Clock divider name - * @param divided_by_value: Value to be divided - * @param reset : Whether to reset the divider counter. - * @return Nothing - */ -void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset); -/*! @brief Return Frequency of selected clock - * @return Frequency of selected clock - */ -uint32_t CLOCK_GetFreq(clock_name_t clockName); -/*! @brief Return Frequency of FRO 12MHz - * @return Frequency of FRO 12MHz - */ -uint32_t CLOCK_GetFro12MFreq(void); -/*! @brief Return Frequency of FRO 1MHz - * @return Frequency of FRO 1MHz - */ -uint32_t CLOCK_GetFro1MFreq(void); -/*! @brief Return Frequency of ClockOut - * @return Frequency of ClockOut - */ -uint32_t CLOCK_GetClockOutClkFreq(void); -/*! @brief Return Frequency of Can Clock - * @return Frequency of Can. - */ -uint32_t CLOCK_GetMCanClkFreq(void); -/*! @brief Return Frequency of Adc Clock - * @return Frequency of Adc. - */ -uint32_t CLOCK_GetAdcClkFreq(uint32_t id); -/*! @brief Return Frequency of Usb0 Clock - * @return Frequency of Usb0 Clock. - */ -uint32_t CLOCK_GetUsb0ClkFreq(void); -/*! @brief Return Frequency of MClk Clock - * @return Frequency of MClk Clock. - */ -uint32_t CLOCK_GetMclkClkFreq(void); -/*! @brief Return Frequency of SCTimer Clock - * @return Frequency of SCTimer Clock. - */ -uint32_t CLOCK_GetSctClkFreq(void); -/*! @brief Return Frequency of External Clock - * @return Frequency of External Clock. If no external clock is used returns 0. - */ -uint32_t CLOCK_GetExtClkFreq(void); -/*! @brief Return Frequency of Watchdog - * @return Frequency of Watchdog - */ -uint32_t CLOCK_GetWdtClkFreq(void); -/*! @brief Return Frequency of High-Freq output of FRO - * @return Frequency of High-Freq output of FRO - */ -uint32_t CLOCK_GetFroHfFreq(void); -/*! @brief Return Frequency of PLL - * @return Frequency of PLL - */ -uint32_t CLOCK_GetPll0OutFreq(void); -/*! @brief Return Frequency of USB PLL - * @return Frequency of PLL - */ -uint32_t CLOCK_GetPll1OutFreq(void); -/*! @brief Return Frequency of PLL_CLK_DIV - * @return Frequency of PLL_CLK_DIV - */ -uint32_t CLOCK_GetPllClkDivFreq(void); -/*! @brief Return Frequency of 32kHz osc - * @return Frequency of 32kHz osc - */ -uint32_t CLOCK_GetOsc32KFreq(void); -/*! @brief Return Frequency of Flexcomm 32kHz osc - * @return Frequency of Flexcomm 32kHz osc - */ -uint32_t CLOCK_GetFC32KFreq(void); -/*! @brief Return Frequency of Core System - * @return Frequency of Core System - */ -uint32_t CLOCK_GetCoreSysClkFreq(void); -/*! @brief Return Frequency of I2S MCLK Clock - * @return Frequency of I2S MCLK Clock - */ -uint32_t CLOCK_GetI2SMClkFreq(void); -/*! @brief Return Frequency of FRG Clock - * @return Frequency of FRG Clock - */ -uint32_t CLOCK_GetFrgFreq(uint32_t id); -/*! @brief Return Frequency of FlexComm Clock - * @return Frequency of FlexComm Clock - */ -uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id); -/*! @brief Return Frequency of High speed SPI Clock - * @return Frequency of High speed SPI Clock - */ -uint32_t CLOCK_GetHsLspiClkFreq(void); -/*! @brief Return Frequency of CTimer functional Clock - * @return Frequency of CTimer functional Clock - */ -uint32_t CLOCK_GetCTimerClkFreq(uint32_t id); -/*! @brief Return Frequency of SystickClock - * @return Frequency of Systick Clock - */ -uint32_t CLOCK_GetSystickClkFreq(void); - -/*! @brief Return Frequency of FlexSPI - * @return Frequency of FlexSPI Clock - */ -uint32_t CLOCK_GetFlexSpiClkFreq(void); - -/*! @brief Return Frequency of DMIC - * @return Frequency of DMIC Clock - */ -uint32_t CLOCK_GetDmicClkFreq(void); - -/*! @brief Return Frequency of DAC Clock - * @return Frequency of DAC Clock - */ -uint32_t CLOCK_GetDacClkFreq(uint32_t id); -/*! @brief Return Frequency of I3C function slow TC Clock - * @return Frequency of I3C function slow TC Clock - */ -uint32_t CLOCK_GetI3cSTCClkFreq(void); -/*! @brief Return Frequency of I3C function slow Clock - * @return Frequency of I3C function slow Clock - */ -uint32_t CLOCK_GetI3cSClkFreq(void); -/*! @brief Return Frequency of I3C function Clock - * @return Frequency of I3C function Clock - */ -uint32_t CLOCK_GetI3cClkFreq(void); - -/*! @brief Return PLL0 input clock rate - * @return PLL0 input clock rate - */ -uint32_t CLOCK_GetPLL0InClockRate(void); - -/*! @brief Return PLL1 input clock rate - * @return PLL1 input clock rate - */ -uint32_t CLOCK_GetPLL1InClockRate(void); - -/*! @brief Return PLL0 output clock rate - * @param recompute : Forces a PLL rate recomputation if true - * @return PLL0 output clock rate - * @note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetPLL0OutClockRate(bool recompute); - -/*! @brief Return PLL1 output clock rate - * @param recompute : Forces a PLL rate recomputation if true - * @return PLL1 output clock rate - * @note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetPLL1OutClockRate(bool recompute); - -/*! @brief Enables and disables PLL0 bypass mode - * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass - * @return PLL0 output clock rate - */ -__STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass) -{ - if (bypass) - { - SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); - } - else - { - SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); - } -} - -/*! @brief Enables and disables PLL1 bypass mode - * @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass - * @return PLL1 output clock rate - */ -__STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass) -{ - if (bypass) - { - SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); - } - else - { - SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); - } -} - -/*! @brief Check if PLL is locked or not - * @return true if the PLL is locked, false if not locked - */ -__STATIC_INLINE bool CLOCK_IsPLL0Locked(void) -{ - return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0UL); -} - -/*! @brief Check if PLL1 is locked or not - * @return true if the PLL1 is locked, false if not locked - */ -__STATIC_INLINE bool CLOCK_IsPLL1Locked(void) -{ - return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0UL); -} - -/*! @brief Store the current PLL0 rate - * @param rate: Current rate of the PLL0 - * @return Nothing - **/ -void CLOCK_SetStoredPLL0ClockRate(uint32_t rate); - -/*! @brief PLL configuration structure flags for 'flags' field - * These flags control how the PLL configuration function sets up the PLL setup structure.
- * - * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the - * configuration structure must be assigned with the expected PLL frequency. If the - * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration - * function and the driver will determine the PLL rate from the currently selected - * PLL source. This flag might be used to configure the PLL input clock more accurately - * when using the WDT oscillator or a more dyanmic CLKIN source.
- * - * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the - * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider - * are not used.
- */ -#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */ -#define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U) -/*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */ - -/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency - * See (MF) field in the PLL0SSCG1 register in the UM. - */ -typedef enum _ss_progmodfm -{ - kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */ - kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */ - kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */ - kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */ - kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */ - kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */ - kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */ - kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */ -} ss_progmodfm_t; - -/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth - * See (MR) field in the PLL0SSCG1 register in the UM. - */ -typedef enum _ss_progmoddp -{ - kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */ - kSS_MR_K1 = (1 << 23), /*!< k = 1 */ - kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */ - kSS_MR_K2 = (3 << 23), /*!< k = 2 */ - kSS_MR_K3 = (4 << 23), /*!< k = 3 */ - kSS_MR_K4 = (5 << 23), /*!< k = 4 */ - kSS_MR_K6 = (6 << 23), /*!< k = 6 */ - kSS_MR_K8 = (7 << 23) /*!< k = 8 */ -} ss_progmoddp_t; - -/*! @brief PLL Spread Spectrum (SS) Modulation waveform control - * See (MC) field in the PLL0SSCG1 register in the UM.
- * Compensation for low pass filtering of the PLL to get a triangular - * modulation at the output of the PLL, giving a flat frequency spectrum. - */ -typedef enum _ss_modwvctrl -{ - kSS_MC_NOC = (0 << 26), /*!< no compensation */ - kSS_MC_RECC = (2 << 26), /*!< recommended setting */ - kSS_MC_MAXC = (3 << 26), /*!< max. compensation */ -} ss_modwvctrl_t; - -/*! @brief PLL configuration structure - * - * This structure can be used to configure the settings for a PLL - * setup structure. Fill in the desired configuration for the PLL - * and call the PLL setup function to fill in a PLL setup structure. - */ -typedef struct _pll_config -{ - uint32_t desiredRate; /*!< Desired PLL rate in Hz */ - uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */ - uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ - ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - ss_modwvctrl_t - ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ - bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - -} pll_config_t; - -/*! @brief PLL setup structure flags for 'flags' field - * These flags control how the PLL setup function sets up the PLL - */ -#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */ -#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ -#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */ -#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */ - -/*! @brief PLL0 setup structure - * This structure can be used to pre-build a PLL setup configuration - * at run-time and quickly set the PLL to the configuration. It can be - * populated with the PLL setup function. If powering up or waiting - * for PLL lock, the PLL input clock source should be configured prior - * to PLL setup. - */ -typedef struct _pll_setup -{ - uint32_t pllctrl; /*!< PLL control register PLL0CTRL */ - uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */ - uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */ - uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */ - uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/ - uint32_t pllRate; /*!< Acutal PLL rate */ - uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ -} pll_setup_t; - -/*! @brief PLL status definitions - */ -typedef enum _pll_error -{ - kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ - kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ - kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ - kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ - kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ - kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */ - kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */ - kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */ -} pll_error_t; - -/*! @brief USB FS clock source definition. */ -typedef enum _clock_usbfs_src -{ - kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 MHz. */ - kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, /*!< Use PLL0 output. */ - kCLOCK_UsbfsSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */ - kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, /*!< Use PLL1 clock. */ - - kCLOCK_UsbfsSrcNone = - SYSCON_USB0CLKSEL_SEL(7) /*!COMP & ~(PMC_COMP_LOWPOWER_MASK | PMC_COMP_HYST_MASK | PMC_COMP_FILTERCGF_CLKDIV_MASK | - PMC_COMP_FILTERCGF_SAMPLEMODE_MASK)); - - if (true == config->enableLowPower) - { - tmpReg |= PMC_COMP_LOWPOWER_MASK; - } - else - { - tmpReg &= ~PMC_COMP_LOWPOWER_MASK; - } - - if (true == config->enableHysteresis) - { - tmpReg |= PMC_COMP_HYST_MASK; - } - else - { - tmpReg &= ~PMC_COMP_HYST_MASK; - } - - tmpReg |= (PMC_COMP_FILTERCGF_CLKDIV(config->filterClockDivider) | - PMC_COMP_FILTERCGF_SAMPLEMODE(config->filterSampleMode)); - - PMC->COMP = tmpReg; -} - -/*! - * @brief CMP deinitialization. - * - * This function gates the clock for CMP module. - */ -void CMP_Deinit(void) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(kCLOCK_Comp); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Initializes the CMP user configuration structure. - * - * This function initializes the user configuration structure to these default values. - * @code - * config->enableHysteresis = true; - * config->enableLowPower = true; - * config->filterClockDivider = kCMP_FilterClockDivide1; - * config->filterSampleMode = kCMP_FilterSampleMode0; - * @endcode - * @param config Pointer to the configuration structure. - */ -void CMP_GetDefaultConfig(cmp_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enableHysteresis = true; - config->enableLowPower = true; - config->filterClockDivider = kCMP_FilterClockDivide1; - config->filterSampleMode = kCMP_FilterSampleMode0; -} - -/*! - * @brief Configures the VREFINPUT. - * - * @param config Pointer to the configuration structure. - */ -void CMP_SetVREF(const cmp_vref_config_t *config) -{ - assert(NULL != config); - assert(config->vrefValue < 32U); - - uint32_t tmpReg = PMC->COMP & ~(PMC_COMP_VREF_MASK | PMC_COMP_VREFINPUT_MASK); - - tmpReg |= PMC_COMP_VREFINPUT(config->vrefSource) | PMC_COMP_VREF(config->vrefValue); - - PMC->COMP = tmpReg; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cmp.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cmp.h deleted file mode 100644 index 1afdc972808..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cmp.h +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Copyright 2018-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __FSL_CMP_H_ -#define __FSL_CMP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup cmp_1 - * @{ - */ - -/****************************************************************************** - * Definitions. - *****************************************************************************/ -/*! @name Driver version */ -/*@{*/ -/*! @brief Driver version 2.2.1. */ -#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 1U)) -/*@}*/ - -/*! @brief CMP input mux for positive and negative sides. */ -enum _cmp_input_mux -{ - kCMP_InputVREF = 0U, /*!< Cmp input from VREF. */ - kCMP_Input1 = 1U, /*!< Cmp input source 1. */ - kCMP_Input2 = 2U, /*!< Cmp input source 2. */ - kCMP_Input3 = 3U, /*!< Cmp input source 3. */ - kCMP_Input4 = 4U, /*!< Cmp input source 4. */ - kCMP_Input5 = 5U, /*!< Cmp input source 5. */ -}; - -/*! @brief CMP interrupt type. */ -enum _cmp_interrupt_type -{ - kCMP_EdgeDisable = 0U, /*!< Disable edge interupt. */ - kCMP_EdgeRising = 2U, /*!< Interrupt on falling edge. */ - kCMP_EdgeFalling = 4U, /*!< Interrupt on rising edge. */ - kCMP_EdgeRisingFalling = 6U, /*!< Interrupt on both rising and falling edges. */ - - kCMP_LevelDisable = 1U, /*!< Disable level interupt. */ - kCMP_LevelHigh = 3U, /*!< Interrupt on high level. */ - kCMP_LevelLow = 5U, /*!< Interrupt on low level. */ -}; - -/*! @brief CMP Voltage Reference source. */ -typedef enum _cmp_vref_source -{ - KCMP_VREFSourceVDDA = 1U, /*!< Select VDDA as VREF. */ - KCMP_VREFSourceInternalVREF = 0U, /*!< Select internal VREF as VREF. */ -} cmp_vref_source_t; - -typedef struct _cmp_vref_config -{ - cmp_vref_source_t vrefSource; /*!< Reference voltage source. */ - uint8_t vrefValue; /*!< Reference voltage step. Available range is 0-31. Per step equals to VREFINPUT/31. */ -} cmp_vref_config_t; - -/*! @brief CMP Filter sample mode. */ -typedef enum _cmp_filtercgf_samplemode -{ - kCMP_FilterSampleMode0 = 0U, /*!< Bypass mode. Filtering is disabled. */ - kCMP_FilterSampleMode1 = 1U, /*!< Filter 1 clock period. */ - kCMP_FilterSampleMode2 = 2U, /*!< Filter 2 clock period. */ - kCMP_FilterSampleMode3 = 3U /*!< Filter 3 clock period. */ -} cmp_filtercgf_samplemode_t; - -/*! @brief CMP Filter clock divider. */ -typedef enum _cmp_filtercgf_clkdiv -{ - kCMP_FilterClockDivide1 = 0U, /*!< Filter clock period duration equals 1 analog comparator clock period. */ - kCMP_FilterClockDivide2 = 1U, /*!< Filter clock period duration equals 2 analog comparator clock period. */ - kCMP_FilterClockDivide4 = 2U, /*!< Filter clock period duration equals 4 analog comparator clock period. */ - kCMP_FilterClockDivide8 = 3U, /*!< Filter clock period duration equals 8 analog comparator clock period. */ - kCMP_FilterClockDivide16 = 4U, /*!< Filter clock period duration equals 16 analog comparator clock period. */ - kCMP_FilterClockDivide32 = 5U, /*!< Filter clock period duration equals 32 analog comparator clock period. */ - kCMP_FilterClockDivide64 = 6U /*!< Filter clock period duration equals 64 analog comparator clock period. */ -} cmp_filtercgf_clkdiv_t; - -/*! @brief CMP configuration structure. */ -typedef struct _cmp_config -{ - bool enableHysteresis; /*!< Enable hysteresis. */ - bool enableLowPower; /*!< Enable low power mode. */ - cmp_filtercgf_clkdiv_t filterClockDivider; /* Filter clock divider. Filter clock equals the Analog Comparator clock - divided by 2^FILTERCGF_CLKDIV. */ - cmp_filtercgf_samplemode_t - filterSampleMode; /* Filter sample mode. Control the filtering of the Analog Comparator output. */ -} cmp_config_t; - -/************************************************************************************************* - * API - ************************************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief CMP initialization. - * - * This function enables the CMP module and do necessary settings. - * - * @param config Pointer to the configuration structure. - */ -void CMP_Init(const cmp_config_t *config); - -/*! - * @brief CMP deinitialization. - * - * This function gates the clock for CMP module. - */ -void CMP_Deinit(void); - -/*! - * @brief Initializes the CMP user configuration structure. - * - * This function initializes the user configuration structure to these default values. - * @code - * config->enableHysteresis = true; - * config->enableLowPower = true; - * config->filterClockDivider = kCMP_FilterClockDivide1; - * config->filterSampleMode = kCMP_FilterSampleMode0; - * @endcode - * @param config Pointer to the configuration structure. - */ -void CMP_GetDefaultConfig(cmp_config_t *config); - -/* @} */ - -/*! - * @name Compare Interface - * @{ - */ - -/* - * @brief Set the input channels for the comparator. - * - * @param positiveChannel Positive side input channel number. See "_cmp_input_mux". - * @param negativeChannel Negative side input channel number. See "_cmp_input_mux". - */ -static inline void CMP_SetInputChannels(uint8_t positiveChannel, uint8_t negativeChannel) -{ - PMC->COMP &= ~(PMC_COMP_PMUX_MASK | PMC_COMP_NMUX_MASK); - PMC->COMP |= (PMC_COMP_PMUX(positiveChannel) | PMC_COMP_NMUX(negativeChannel)); -} - -/*! - * @brief Configures the VREFINPUT. - * - * @param config Pointer to the configuration structure. - */ -void CMP_SetVREF(const cmp_vref_config_t *config); - -/*! - * @brief Get CMP compare output. - * - * @return The output result. true: voltage on positive side is greater than negative side. - * false: voltage on positive side is lower than negative side. - */ -static inline bool CMP_GetOutput(void) -{ - return SYSCON_COMP_INT_STATUS_VAL_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_VAL_MASK); -} - -/* @} */ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief CMP enable interrupt. - * - * @param type CMP interrupt type. See "_cmp_interrupt_type". - */ -static inline void CMP_EnableInterrupt(uint32_t type) -{ - SYSCON->COMP_INT_CTRL |= (SYSCON_COMP_INT_CTRL_INT_CTRL(type) | SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK); -} - -/*! - * @brief CMP disable interrupt. - * - */ -static inline void CMP_DisableInterrupt(void) -{ - SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK; -} - -/*! - * @brief CMP clear interrupt. - * - */ -static inline void CMP_ClearInterrupt(void) -{ - SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK; -} - -/*! - * @brief Select which Analog comparator output (filtered or un-filtered) is used for interrupt detection. - * - * @param enable false: Select Analog Comparator raw output (unfiltered) as input for interrupt detection. - * true: Select Analog Comparator filtered output as input for interrupt detection. - * - * @note: When CMP is configured as the wakeup source in power down mode, this function must use the raw output as the - * interupt source, that is, call this function and set parameter enable to false. - */ -static inline void CMP_EnableFilteredInterruptSource(bool enable) -{ - if (enable) - { - SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; - } - else - { - SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; - } -} -/* @} */ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Get CMP interrupt status before interupt enable. - * - * @return Interrupt status. true: interrupt pending, - * false: no interrupt pending. - */ -static inline bool CMP_GetPreviousInterruptStatus(void) -{ - return SYSCON_COMP_INT_STATUS_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_STATUS_MASK); -} - -/*! - * @brief Get CMP interrupt status after interupt enable. - * - * @return Interrupt status. true: interrupt pending, - * false: no interrupt pending. - */ -static inline bool CMP_GetInterruptStatus(void) -{ - return SYSCON_COMP_INT_STATUS_INT_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK); -} -/* @} */ - -/*! - * @name Filter Interface - * @{ - */ - -/*! - * @brief CMP Filter Sample Config. - * - * This function allows the users to configure the sampling mode and clock divider of the CMP Filter. - * - * @param filterSampleMode CMP Select filter sample mode - * @param filterClockDivider CMP Set fileter clock divider - */ -static inline void CMP_FilterSampleConfig(cmp_filtercgf_samplemode_t filterSampleMode, - cmp_filtercgf_clkdiv_t filterClockDivider) -{ - uint32_t comp = PMC->COMP; - - comp &= ~(PMC_COMP_FILTERCGF_CLKDIV_MASK | PMC_COMP_FILTERCGF_SAMPLEMODE_MASK); - comp |= (((uint32_t)filterClockDivider << PMC_COMP_FILTERCGF_CLKDIV_SHIFT) | - ((uint32_t)filterSampleMode << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)); - - PMC->COMP = comp; -} -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ -#endif /* __FSL_CMP_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common.c deleted file mode 100644 index 8b17fc36684..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" - -#define SDK_MEM_MAGIC_NUMBER 12345U - -typedef struct _mem_align_control_block -{ - uint16_t identifier; /*!< Identifier for the memory control block. */ - uint16_t offset; /*!< offset from aligned address to real address */ -} mem_align_cb_t; - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.common" -#endif - -void *SDK_Malloc(size_t size, size_t alignbytes) -{ - mem_align_cb_t *p_cb = NULL; - uint32_t alignedsize; - - /* Check overflow. */ - alignedsize = SDK_SIZEALIGN(size, alignbytes); - if (alignedsize < size) - { - return NULL; - } - - if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t)) - { - return NULL; - } - - alignedsize += alignbytes + sizeof(mem_align_cb_t); - - union - { - void *pointer_value; - uint32_t unsigned_value; - } p_align_addr, p_addr; - - p_addr.pointer_value = malloc(alignedsize); - - if (p_addr.pointer_value == NULL) - { - return NULL; - } - - p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes); - - p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U); - p_cb->identifier = SDK_MEM_MAGIC_NUMBER; - p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value); - - return p_align_addr.pointer_value; -} - -void SDK_Free(void *ptr) -{ - union - { - void *pointer_value; - uint32_t unsigned_value; - } p_free; - p_free.pointer_value = ptr; - mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U); - - if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) - { - return; - } - - p_free.unsigned_value = p_free.unsigned_value - p_cb->offset; - - free(p_free.pointer_value); -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common.h deleted file mode 100644 index ff075086c8a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_COMMON_H_ -#define _FSL_COMMON_H_ - -#include -#include -#include -#include -#include - -#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__) -#include -#endif - -#include "fsl_device_registers.h" - -/*! - * @addtogroup ksdk_common - * @{ - */ - -/******************************************************************************* - * Configurations - ******************************************************************************/ - -/*! @brief Macro to use the default weak IRQ handler in drivers. */ -#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ -#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Construct a status code value from a group and code number. */ -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) - -/*! @brief Construct the version number for drivers. */ -#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) - -/*! @name Driver version */ -/*@{*/ -/*! @brief common driver version. */ -#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) -/*@}*/ - -/* Debug console type definition. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */ - -/*! @brief Status group numbers. */ -enum _status_groups -{ - kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ - kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ - kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ - kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ - kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ - kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ - kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ - kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ - kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ - kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ - kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ - kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ - kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ - kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ - kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ - kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ - kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ - kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ - kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ - kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ - kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ - kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ - kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ - kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ - kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ - kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ - kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ - kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ - kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ - kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ - kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ - kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ - kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ - kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ - kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ - kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ - kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ - kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ - kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ - kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ - kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ - kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ - kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ - kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ - kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ - kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ - kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ - kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ - kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ - kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ - kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ - kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ - kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ - kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ - kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ - kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ - kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ - kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ - kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ - kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ - kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ - kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ - kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ - kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ - kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ - kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ - kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ - kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ - kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ - kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ - kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ - kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ - kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ - kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/ - kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */ - kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */ - kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */ - - kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ - kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ - kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ - kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ - kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ - kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ - kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ - kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ - kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ - kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ - kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ - kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ - kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ - kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ - kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ - kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ - kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ - kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ - kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ - kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ - kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ - kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ - kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */ - kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */ - kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */ - kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */ - kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */ - kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */ - kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */ - kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */ - kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */ - kStatusGroup_IPED = 158, /*!< Group number for IPED status codes. */ - kStatusGroup_CSS_PKC = 159, /*!< Group number for CSS PKC status codes. */ -}; - -/*! \public - * @brief Generic status return codes. - */ -enum -{ - kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */ - kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */ - kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */ - kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */ - kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */ - kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */ - kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */ - kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */ -}; - -/*! @brief Type used for all status and error return values. */ -typedef int32_t status_t; - -/*! - * @name Min/max macros - * @{ - */ -#if !defined(MIN) -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) -#endif - -#if !defined(MAX) -#define MAX(a, b) (((a) > (b)) ? (a) : (b)) -#endif -/* @} */ - -/*! @brief Computes the number of elements in an array. */ -#if !defined(ARRAY_SIZE) -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) -#endif - -/*! @name UINT16_MAX/UINT32_MAX value */ -/* @{ */ -#if !defined(UINT16_MAX) -#define UINT16_MAX ((uint16_t)-1) -#endif - -#if !defined(UINT32_MAX) -#define UINT32_MAX ((uint32_t)-1) -#endif -/* @} */ - -/*! @name Suppress fallthrough warning macro */ -/* For switch case code block, if case section ends without "break;" statement, there wil be - fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. - To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each - case section which misses "break;"statement. - */ -/* @{ */ -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) -#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__ ((fallthrough)) -#else -#define SUPPRESS_FALL_THROUGH_WARNING() -#endif -/* @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Allocate memory with given alignment and aligned size. - * - * This is provided to support the dynamically allocated memory - * used in cache-able region. - * @param size The length required to malloc. - * @param alignbytes The alignment size. - * @retval The allocated memory. - */ -void *SDK_Malloc(size_t size, size_t alignbytes); - -/*! - * @brief Free memory. - * - * @param ptr The memory to be release. - */ -void SDK_Free(void *ptr); - -/*! -* @brief Delay at least for some time. -* Please note that, this API uses while loop for delay, different run-time environments make the time not precise, -* if precise delay count was needed, please implement a new delay function with hardware timer. -* -* @param delayTime_us Delay time in unit of microsecond. -* @param coreClock_Hz Core clock frequency with Hz. -*/ -void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#if (defined(__DSC__) && defined(__CW__)) -#include "fsl_common_dsc.h" -#elif defined(__XCC__) -#include "fsl_common_dsp.h" -#else -#include "fsl_common_arm.h" -#endif - -#endif /* _FSL_COMMON_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common_arm.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common_arm.c deleted file mode 100644 index e77a265ce43..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common_arm.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.common_arm" -#endif - -#ifndef __GIC_PRIO_BITS -#if defined(ENABLE_RAM_VECTOR_TABLE) -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) -{ -#ifdef __VECTOR_TABLE -#undef __VECTOR_TABLE -#endif - -/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) - extern uint32_t Image$$VECTOR_ROM$$Base[]; - extern uint32_t Image$$VECTOR_RAM$$Base[]; - extern uint32_t Image$$RW_m_data$$Base[]; - -#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base -#define __VECTOR_RAM Image$$VECTOR_RAM$$Base -#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) -#elif defined(__ICCARM__) - extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; -#elif defined(__GNUC__) - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; - extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; - uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); -#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ - uint32_t n; - uint32_t ret; - uint32_t irqMaskValue; - - irqMaskValue = DisableGlobalIRQ(); - if (SCB->VTOR != (uint32_t)__VECTOR_RAM) - { - /* Copy the vector table from ROM to RAM */ - for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) - { - __VECTOR_RAM[n] = __VECTOR_TABLE[n]; - } - /* Point the VTOR to the position of vector table */ - SCB->VTOR = (uint32_t)__VECTOR_RAM; - } - - ret = __VECTOR_RAM[(int32_t)irq + 16]; - /* make sure the __VECTOR_RAM is noncachable */ - __VECTOR_RAM[(int32_t)irq + 16] = irqHandler; - - EnableGlobalIRQ(irqMaskValue); - - return ret; -} -#endif /* ENABLE_RAM_VECTOR_TABLE. */ -#endif /* __GIC_PRIO_BITS. */ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - -/* - * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, - * powerlib should be used instead of these functions. - */ -#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) - -/* - * When the SYSCON STARTER registers are discontinuous, these functions are - * implemented in fsl_power.c. - */ -#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) - -void EnableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t intNumber = (uint32_t)interrupt; - - uint32_t index = 0; - - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERSET[index] = 1UL << intNumber; - (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */ -} - -void DisableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t intNumber = (uint32_t)interrupt; - - (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */ - uint32_t index = 0; - - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERCLR[index] = 1UL << intNumber; -} -#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ -#endif /* FSL_FEATURE_POWERLIB_EXTEND */ -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - -#if defined(SDK_DELAY_USE_DWT) && defined(DWT) -/* Use WDT. */ -static void enableCpuCycleCounter(void) -{ - /* Make sure the DWT trace fucntion is enabled. */ - if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) - { - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - } - - /* CYCCNT not supported on this device. */ - assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); - - /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */ - if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) - { - DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; - } -} - -static uint32_t getCpuCycleCount(void) -{ - return DWT->CYCCNT; -} -#else /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ -/* Use software loop. */ -#if defined(__CC_ARM) /* This macro is arm v5 specific */ -/* clang-format off */ -__ASM static void DelayLoop(uint32_t count) -{ -loop - SUBS R0, R0, #1 - CMP R0, #0 - BNE loop - BX LR -} -/* clang-format on */ -#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__) -/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler, - * use SUB and CMP here for compatibility */ -static void DelayLoop(uint32_t count) -{ - __ASM volatile(" MOV R0, %0" : : "r"(count)); - __ASM volatile( - "loop: \n" -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) - " SUB R0, R0, #1 \n" -#else - " SUBS R0, R0, #1 \n" -#endif - " CMP R0, #0 \n" - - " BNE loop \n" - : - : - : "r0"); -} -#endif /* defined(__CC_ARM) */ -#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ - -/*! - * @brief Delay at least for some time. - * Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have - * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and - * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports - * up to 4294967 in current code. If long time delay is needed, please implement a new delay function. - * - * @param delayTime_us Delay time in unit of microsecond. - * @param coreClock_Hz Core clock frequency with Hz. - */ -void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) -{ - uint64_t count; - - if (delayTime_us > 0U) - { - count = USEC_TO_COUNT(delayTime_us, coreClock_Hz); - - assert(count <= UINT32_MAX); - -#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */ - - enableCpuCycleCounter(); - /* Calculate the count ticks. */ - count += getCpuCycleCount(); - - if (count > UINT32_MAX) - { - count -= UINT32_MAX; - /* Wait for cyccnt overflow. */ - while (count < getCpuCycleCount()) - { - } - } - - /* Wait for cyccnt reach count value. */ - while (count > getCpuCycleCount()) - { - } -#else - /* Divide value may be different in various environment to ensure delay is precise. - * Every loop count includes three instructions, due to Cortex-M7 sometimes executes - * two instructions in one period, through test here set divide 1.5. Other M cores use - * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does - * not matter because other instructions outside while loop is enough to fill the time. - */ -#if (__CORTEX_M == 7) - count = count / 3U * 2U; -#else - count = count / 4U; -#endif - DelayLoop((uint32_t)count); -#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common_arm.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common_arm.h deleted file mode 100644 index 8b28aa88871..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common_arm.h +++ /dev/null @@ -1,660 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_COMMON_ARM_H_ -#define _FSL_COMMON_ARM_H_ - -/* - * For CMSIS pack RTE. - * CMSIS pack RTE generates "RTC_Components.h" which contains the statements - * of the related element for all selected software components. - */ -#ifdef _RTE_ -#include "RTE_Components.h" -#endif - -/*! - * @addtogroup ksdk_common - * @{ - */ - -/*! @name Atomic modification - * - * These macros are used for atomic access, such as read-modify-write - * to the peripheral registers. - * - * - SDK_ATOMIC_LOCAL_ADD - * - SDK_ATOMIC_LOCAL_SET - * - SDK_ATOMIC_LOCAL_CLEAR - * - SDK_ATOMIC_LOCAL_TOGGLE - * - SDK_ATOMIC_LOCAL_CLEAR_AND_SET - * - * Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr - * means the address of the peripheral register or variable you want to modify - * atomically, the parameter @c clearBits is the bits to clear, the parameter - * @c setBits it the bits to set. - * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this: - * - * @code - volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR; - - SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02); - @endcode - * - * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result, - * register bit1:bit0 = 0b10. - * - * @note For the platforms don't support exclusive load and store, these macros - * disable the global interrupt to pretect the modification. - * - * @note These macros only guarantee the local processor atomic operations. For - * the multi-processor devices, use hardware semaphore such as SEMA42 to - * guarantee exclusive access if necessary. - * - * @{ - */ - -/* clang-format off */ -#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) -/* clang-format on */ - -/* If the LDREX and STREX are supported, use them. */ -#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \ - do \ - { \ - (val) = __LDREXB(addr); \ - (ops); \ - } while (0UL != __STREXB((val), (addr))) - -#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \ - do \ - { \ - (val) = __LDREXH(addr); \ - (ops); \ - } while (0UL != __STREXH((val), (addr))) - -#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \ - do \ - { \ - (val) = __LDREXW(addr); \ - (ops); \ - } while (0UL != __STREXW((val), (addr))) - -static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val); -} - -static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val); -} - -static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val); -} - -static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val); -} - -static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val); -} - -static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val); -} - -static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits); -} - -static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits); -} - -static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits); -} - -static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits); -} - -static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits); -} - -static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits); -} - -static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits); -} - -static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits); -} - -static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits); -} - -static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); -} - -static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); -} - -static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); -} - -#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ - ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd1Byte((volatile uint8_t*)(volatile void*)(addr), (val)) : \ - ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t*)(volatile void*)(addr), (val)) : \ - _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void*)(addr), (val)))) - -#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ - ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet1Byte((volatile uint8_t*)(volatile void*)(addr), (bits)) : \ - ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t*)(volatile void*)(addr), (bits)) : \ - _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void*)(addr), (bits)))) - -#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ - ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalClear1Byte((volatile uint8_t*)(volatile void*)(addr), (bits)) : \ - ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalClear2Byte((volatile uint16_t*)(volatile void*)(addr), (bits)) : \ - _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void*)(addr), (bits)))) - -#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ - ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalToggle1Byte((volatile uint8_t*)(volatile void*)(addr), (bits)) : \ - ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalToggle2Byte((volatile uint16_t*)(volatile void*)(addr), (bits)) : \ - _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void*)(addr), (bits)))) - -#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ - ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t*)(volatile void*)(addr), (clearBits), (setBits)) : \ - ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t*)(volatile void*)(addr), (clearBits), (setBits)) : \ - _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void*)(addr), (clearBits), (setBits)))) -#else - -#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ - do { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) += (val); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ - do { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) |= (bits); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ - do { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) &= ~(bits); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ - do { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) ^= (bits); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ - do { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) = (*(addr) & ~(clearBits)) | (setBits); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#endif -/* @} */ - -/*! @name Timer utilities */ -/* @{ */ -/*! Macro to convert a microsecond period to raw count value */ -#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) -/*! Macro to convert a raw count value to microsecond */ -#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000000U / (clockFreqInHz)) - -/*! Macro to convert a millisecond period to raw count value */ -#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) -/*! Macro to convert a raw count value to millisecond */ -#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000U / (clockFreqInHz)) -/* @} */ - -/*! @name ISR exit barrier - * @{ - * - * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - * exception return operation might vector to incorrect interrupt. - * For Cortex-M7, if core speed much faster than peripheral register write speed, - * the peripheral interrupt flags may be still set after exiting ISR, this results to - * the same error similar with errata 83869. - */ -#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U)) -#define SDK_ISR_EXIT_BARRIER __DSB() -#else -#define SDK_ISR_EXIT_BARRIER -#endif - -/* @} */ - -/*! @name Alignment variable definition macros */ -/* @{ */ -#if (defined(__ICCARM__)) -/* - * Workaround to disable MISRA C message suppress warnings for IAR compiler. - * http:/ /supp.iar.com/Support/?note=24725 - */ -_Pragma("diag_suppress=Pm120") -#define SDK_PRAGMA(x) _Pragma(#x) -_Pragma("diag_error=Pm120") -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var -#elif defined(__GNUC__) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) -#else -#error Toolchain not supported -#endif - -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#endif - -/*! Macro to change a value to a given size aligned value */ -#define SDK_SIZEALIGN(var, alignbytes) \ - ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) -/* @} */ - -/*! @name Non-cacheable region definition macros */ -/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or - * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, - * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables - * will be initialized to zero in system startup. - */ -/* @{ */ - -#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) - -#if (defined(__ICCARM__)) -#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" -#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" - -#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var -#if(defined(__CC_ARM)) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var -#else -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var -#endif - -#elif(defined(__GNUC__)) -/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" - * in your projects to make sure the non-cacheable section variables will be initialized in system startup. - */ -#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) -#else -#error Toolchain not supported. -#endif - -#else - -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes) -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes) - -#endif - -/* @} */ - -/*! - * @name Time sensitive region - * @{ - */ -#if (defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) - -#if (defined(__ICCARM__)) -#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" -#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" -#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func -#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func -#elif(defined(__GNUC__)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func -#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func -#else -#error Toolchain not supported. -#endif /* defined(__ICCARM__) */ - -#else /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ - -#define AT_QUICKACCESS_SECTION_CODE(func) func -#define AT_QUICKACCESS_SECTION_DATA(func) func - -#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ -/* @} */ - -/*! @name Ram Function */ -#if (defined(__ICCARM__)) -#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" -#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func -#elif(defined(__GNUC__)) -#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func -#else -#error Toolchain not supported. -#endif /* defined(__ICCARM__) */ -/* @} */ - -#if defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) -void DefaultISR(void); -#endif - -/* - * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t - * defined in previous of this file. - */ -#include "fsl_clock.h" - -/* - * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral - */ -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) -#include "fsl_reset.h" -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief Enable specific interrupt. - * - * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt enabled successfully - * @retval kStatus_Fail Failed to enable the interrupt - */ -static inline status_t EnableIRQ(IRQn_Type interrupt) -{ - status_t status = kStatus_Success; - - if (NotAvail_IRQn == interrupt) - { - status = kStatus_Fail; - } - -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - status = kStatus_Fail; - } -#endif - - else - { -#if defined(__GIC_PRIO_BITS) - GIC_EnableIRQ(interrupt); -#else - NVIC_EnableIRQ(interrupt); -#endif - } - - return status; -} - -/*! - * @brief Disable specific interrupt. - * - * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt disabled successfully - * @retval kStatus_Fail Failed to disable the interrupt - */ -static inline status_t DisableIRQ(IRQn_Type interrupt) -{ - status_t status = kStatus_Success; - - if (NotAvail_IRQn == interrupt) - { - status = kStatus_Fail; - } - -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - status = kStatus_Fail; - } -#endif - - else - { -#if defined(__GIC_PRIO_BITS) - GIC_DisableIRQ(interrupt); -#else - NVIC_DisableIRQ(interrupt); -#endif - } - - return status; -} - -/*! - * @brief Disable the global IRQ - * - * Disable the global interrupt and return the current primask register. User is required to provided the primask - * register for the EnableGlobalIRQ(). - * - * @return Current primask value. - */ -static inline uint32_t DisableGlobalIRQ(void) -{ -#if defined(CPSR_I_Msk) - uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; - - __disable_irq(); - - return cpsr; -#else - uint32_t regPrimask = __get_PRIMASK(); - - __disable_irq(); - - return regPrimask; -#endif -} - -/*! - * @brief Enable the global IRQ - * - * Set the primask register with the provided primask value but not just enable the primask. The idea is for the - * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to - * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. - * - * @param primask value of primask register to be restored. The primask value is supposed to be provided by the - * DisableGlobalIRQ(). - */ -static inline void EnableGlobalIRQ(uint32_t primask) -{ -#if defined(CPSR_I_Msk) - __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); -#else - __set_PRIMASK(primask); -#endif -} - -#if defined(ENABLE_RAM_VECTOR_TABLE) -/*! - * @brief install IRQ handler - * - * @param irq IRQ number - * @param irqHandler IRQ handler address - * @return The old IRQ handler address - */ -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); -#endif /* ENABLE_RAM_VECTOR_TABLE. */ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - -/* - * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, - * powerlib should be used instead of these functions. - */ -#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) -/*! - * @brief Enable specific interrupt for wake-up from deep-sleep mode. - * - * Enable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). - * - * @param interrupt The IRQ number. - */ -void EnableDeepSleepIRQ(IRQn_Type interrupt); - -/*! - * @brief Disable specific interrupt for wake-up from deep-sleep mode. - * - * Disable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). - * - * @param interrupt The IRQ number. - */ -void DisableDeepSleepIRQ(IRQn_Type interrupt); -#endif /* FSL_FEATURE_POWERLIB_EXTEND */ -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @} */ - -#endif /* _FSL_COMMON_ARM_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_crc.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_crc.c deleted file mode 100644 index 037dd41689c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_crc.c +++ /dev/null @@ -1,322 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_crc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.crc" -#endif - -/*! @internal @brief Has data register with name CRC. */ -#if defined(FSL_FEATURE_CRC_HAS_CRC_REG) && FSL_FEATURE_CRC_HAS_CRC_REG -#define DATA CRC -#define DATALL CRCLL -#endif - -#if defined(CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT -/* @brief Default user configuration structure for CRC-16-CCITT */ -#define CRC_DRIVER_DEFAULT_POLYNOMIAL 0x1021U -/*< CRC-16-CCIT polynomial x**16 + x**12 + x**5 + x**0 */ -#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU -/*< Default initial checksum */ -#define CRC_DRIVER_DEFAULT_REFLECT_IN false -/*< Default is no transpose */ -#define CRC_DRIVER_DEFAULT_REFLECT_OUT false -/*< Default is transpose bytes */ -#define CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM false -/*< Default is without complement of CRC data register read data */ -#define CRC_DRIVER_DEFAULT_CRC_BITS kCrcBits16 -/*< Default is 16-bit CRC protocol */ -#define CRC_DRIVER_DEFAULT_CRC_RESULT kCrcFinalChecksum -/*< Default is resutl type is final checksum */ -#endif /* CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT */ - -/*! @brief CRC type of transpose of read write data */ -typedef enum _crc_transpose_type -{ - kCrcTransposeNone = 0U, /*! No transpose */ - kCrcTransposeBits = 1U, /*! Tranpose bits in bytes */ - kCrcTransposeBitsAndBytes = 2U, /*! Transpose bytes and bits in bytes */ - kCrcTransposeBytes = 3U, /*! Transpose bytes */ -} crc_transpose_type_t; - -/*! - * @brief CRC module configuration. - * - * This structure holds the configuration for the CRC module. - */ -typedef struct _crc_module_config -{ - uint32_t polynomial; /*!< CRC Polynomial, MSBit first.@n - Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */ - uint32_t seed; /*!< Starting checksum value */ - crc_transpose_type_t readTranspose; /*!< Type of transpose when reading CRC result. */ - crc_transpose_type_t writeTranspose; /*!< Type of transpose when writing CRC input data. */ - bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */ - crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ -} crc_module_config_t; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * @brief Returns transpose type for CRC protocol reflect in parameter. - * - * This functions helps to set writeTranspose member of crc_config_t structure. Reflect in is CRC protocol parameter. - * - * @param enable True or false for the selected CRC protocol Reflect In (refin) parameter. - */ -static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectIn(bool enable) -{ - return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeBytes); -} - -/*! - * @brief Returns transpose type for CRC protocol reflect out parameter. - * - * This functions helps to set readTranspose member of crc_config_t structure. Reflect out is CRC protocol parameter. - * - * @param enable True or false for the selected CRC protocol Reflect Out (refout) parameter. - */ -static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectOut(bool enable) -{ - return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeNone); -} - -/*! - * @brief Starts checksum computation. - * - * Configures the CRC module for the specified CRC protocol. @n - * Starts the checksum computation by writing the seed value - * - * @param base CRC peripheral address. - * @param config Pointer to protocol configuration structure. - */ -static void CRC_ConfigureAndStart(CRC_Type *base, const crc_module_config_t *config) -{ - uint32_t crcControl; - - /* pre-compute value for CRC control registger based on user configuraton without WAS field */ - crcControl = 0U | CRC_CTRL_TOT(config->writeTranspose) | CRC_CTRL_TOTR(config->readTranspose) | - CRC_CTRL_FXOR(config->complementChecksum) | CRC_CTRL_TCRC(config->crcBits); - - /* make sure the control register is clear - WAS is deasserted, and protocol is set */ - base->CTRL = crcControl; - - /* write polynomial register */ - base->GPOLY = config->polynomial; - - /* write pre-computed control register value along with WAS to start checksum computation */ - base->CTRL = crcControl | CRC_CTRL_WAS(true); - - /* write seed (initial checksum) */ - base->DATA = config->seed; - - /* deassert WAS by writing pre-computed CRC control register value */ - base->CTRL = crcControl; -} - -/*! - * @brief Starts final checksum computation. - * - * Configures the CRC module for the specified CRC protocol. @n - * Starts final checksum computation by writing the seed value. - * @note CRC_Get16bitResult() or CRC_Get32bitResult() return final checksum - * (output reflection and xor functions are applied). - * - * @param base CRC peripheral address. - * @param protocolConfig Pointer to protocol configuration structure. - */ -static void CRC_SetProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig) -{ - crc_module_config_t moduleConfig; - /* convert protocol to CRC peripheral module configuration, prepare for final checksum */ - moduleConfig.polynomial = protocolConfig->polynomial; - moduleConfig.seed = protocolConfig->seed; - moduleConfig.readTranspose = CRC_GetTransposeTypeFromReflectOut(protocolConfig->reflectOut); - moduleConfig.writeTranspose = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn); - moduleConfig.complementChecksum = protocolConfig->complementChecksum; - moduleConfig.crcBits = protocolConfig->crcBits; - - CRC_ConfigureAndStart(base, &moduleConfig); -} - -/*! - * @brief Starts intermediate checksum computation. - * - * Configures the CRC module for the specified CRC protocol. @n - * Starts intermediate checksum computation by writing the seed value. - * @note CRC_Get16bitResult() or CRC_Get32bitResult() return intermediate checksum (raw data register value). - * - * @param base CRC peripheral address. - * @param protocolConfig Pointer to protocol configuration structure. - */ -static void CRC_SetRawProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig) -{ - crc_module_config_t moduleConfig; - /* convert protocol to CRC peripheral module configuration, prepare for intermediate checksum */ - moduleConfig.polynomial = protocolConfig->polynomial; - moduleConfig.seed = protocolConfig->seed; - moduleConfig.readTranspose = - kCrcTransposeNone; /* intermediate checksum does no transpose of data register read value */ - moduleConfig.writeTranspose = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn); - moduleConfig.complementChecksum = false; /* intermediate checksum does no xor of data register read value */ - moduleConfig.crcBits = protocolConfig->crcBits; - - CRC_ConfigureAndStart(base, &moduleConfig); -} - -/*! - * brief Enables and configures the CRC peripheral module. - * - * This function enables the clock gate in the SIM module for the CRC peripheral. - * It also configures the CRC module and starts a checksum computation by writing the seed. - * - * param base CRC peripheral address. - * param config CRC module configuration structure. - */ -void CRC_Init(CRC_Type *base, const crc_config_t *config) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* ungate clock */ - CLOCK_EnableClock(kCLOCK_Crc0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* configure CRC module and write the seed */ - if (config->crcResult == kCrcFinalChecksum) - { - CRC_SetProtocolConfig(base, config); - } - else - { - CRC_SetRawProtocolConfig(base, config); - } -} - -/*! - * brief Loads default values to the CRC protocol configuration structure. - * - * Loads default values to the CRC protocol configuration structure. The default values are as follows. - * code - * config->polynomial = 0x1021; - * config->seed = 0xFFFF; - * config->reflectIn = false; - * config->reflectOut = false; - * config->complementChecksum = false; - * config->crcBits = kCrcBits16; - * config->crcResult = kCrcFinalChecksum; - * endcode - * - * param config CRC protocol configuration structure. - */ -void CRC_GetDefaultConfig(crc_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - static const crc_config_t crc16ccit = { - CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_SEED, - CRC_DRIVER_DEFAULT_REFLECT_IN, CRC_DRIVER_DEFAULT_REFLECT_OUT, - CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM, CRC_DRIVER_DEFAULT_CRC_BITS, - CRC_DRIVER_DEFAULT_CRC_RESULT, - }; - - *config = crc16ccit; -} - -/*! - * brief Writes data to the CRC module. - * - * Writes input data buffer bytes to the CRC data register. - * The configured type of transpose is applied. - * - * param base CRC peripheral address. - * param data Input data stream, MSByte in data[0]. - * param dataSize Size in bytes of the input data buffer. - */ -void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) -{ - const uint32_t *data32; - - /* 8-bit reads and writes till source address is aligned 4 bytes */ - while ((0U != dataSize) && (0U != ((uint32_t)data & 3U))) - { - base->ACCESS8BIT.DATALL = *data; - data++; - dataSize--; - } - - /* use 32-bit reads and writes as long as possible */ - data32 = (const uint32_t *)(uint32_t)data; - while (dataSize >= sizeof(uint32_t)) - { - base->DATA = *data32; - data32++; - dataSize -= sizeof(uint32_t); - } - - data = (const uint8_t *)data32; - - /* 8-bit reads and writes till end of data buffer */ - while (dataSize != 0U) - { - base->ACCESS8BIT.DATALL = *data; - data++; - dataSize--; - } -} - -/*! - * brief Reads the 32-bit checksum from the CRC module. - * - * Reads the CRC data register (either an intermediate or the final checksum). - * The configured type of transpose and complement is applied. - * - * param base CRC peripheral address. - * return An intermediate or the final 32-bit checksum, after configured transpose and complement operations. - */ -uint32_t CRC_Get32bitResult(CRC_Type *base) -{ - return base->DATA; -} - -/*! - * brief Reads a 16-bit checksum from the CRC module. - * - * Reads the CRC data register (either an intermediate or the final checksum). - * The configured type of transpose and complement is applied. - * - * param base CRC peripheral address. - * return An intermediate or the final 16-bit checksum, after configured transpose and complement operations. - */ -uint16_t CRC_Get16bitResult(CRC_Type *base) -{ - uint32_t retval; - uint32_t totr; /* type of transpose read bitfield */ - - retval = base->DATA; - totr = (base->CTRL & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT; - - /* check transpose type to get 16-bit out of 32-bit register */ - if (totr >= 2U) - { - /* transpose of bytes for read is set, the result CRC is in CRC_DATA[HU:HL] */ - retval &= 0xFFFF0000U; - retval = retval >> 16U; - } - else - { - /* no transpose of bytes for read, the result CRC is in CRC_DATA[LU:LL] */ - retval &= 0x0000FFFFU; - } - return (uint16_t)retval; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_crc.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_crc.h deleted file mode 100644 index 04270b83dc3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_crc.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CRC_H_ -#define _FSL_CRC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup crc - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CRC driver version. Version 2.0.3. - * - * Current version: 2.0.3 - * - * Change log: - * - * - Version 2.0.3 - * - Fix MISRA issues - * - * - Version 2.0.2 - * - Fix MISRA issues - * - * - Version 2.0.1 - * - move DATA and DATALL macro definition from header file to source file - */ -#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ - -#ifndef CRC_DRIVER_CUSTOM_DEFAULTS -/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */ -#define CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT 1 -#endif - -/*! @brief CRC bit width */ -typedef enum _crc_bits -{ - kCrcBits16 = 0U, /*!< Generate 16-bit CRC code */ - kCrcBits32 = 1U /*!< Generate 32-bit CRC code */ -} crc_bits_t; - -/*! @brief CRC result type */ -typedef enum _crc_result -{ - kCrcFinalChecksum = 0U, /*!< CRC data register read value is the final checksum. - Reflect out and final xor protocol features are applied. */ - kCrcIntermediateChecksum = 1U /*!< CRC data register read value is intermediate checksum (raw value). - Reflect out and final xor protocol feature are not applied. - Intermediate checksum can be used as a seed for CRC_Init() - to continue adding data to this checksum. */ -} crc_result_t; - -/*! - * @brief CRC protocol configuration. - * - * This structure holds the configuration for the CRC protocol. - * - */ -typedef struct _crc_config -{ - uint32_t polynomial; /*!< CRC Polynomial, MSBit first. - Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */ - uint32_t seed; /*!< Starting checksum value */ - bool reflectIn; /*!< Reflect bits on input. */ - bool reflectOut; /*!< Reflect bits on output. */ - bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */ - crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ - crc_result_t crcResult; /*!< Selects final or intermediate checksum return from CRC_Get16bitResult() or - CRC_Get32bitResult() */ -} crc_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Enables and configures the CRC peripheral module. - * - * This function enables the clock gate in the SIM module for the CRC peripheral. - * It also configures the CRC module and starts a checksum computation by writing the seed. - * - * @param base CRC peripheral address. - * @param config CRC module configuration structure. - */ -void CRC_Init(CRC_Type *base, const crc_config_t *config); - -/*! - * @brief Disables the CRC peripheral module. - * - * This function disables the clock gate in the SIM module for the CRC peripheral. - * - * @param base CRC peripheral address. - */ -static inline void CRC_Deinit(CRC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* gate clock */ - CLOCK_DisableClock(kCLOCK_Crc0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Loads default values to the CRC protocol configuration structure. - * - * Loads default values to the CRC protocol configuration structure. The default values are as follows. - * @code - * config->polynomial = 0x1021; - * config->seed = 0xFFFF; - * config->reflectIn = false; - * config->reflectOut = false; - * config->complementChecksum = false; - * config->crcBits = kCrcBits16; - * config->crcResult = kCrcFinalChecksum; - * @endcode - * - * @param config CRC protocol configuration structure. - */ -void CRC_GetDefaultConfig(crc_config_t *config); - -/*! - * @brief Writes data to the CRC module. - * - * Writes input data buffer bytes to the CRC data register. - * The configured type of transpose is applied. - * - * @param base CRC peripheral address. - * @param data Input data stream, MSByte in data[0]. - * @param dataSize Size in bytes of the input data buffer. - */ -void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize); - -/*! - * @brief Reads the 32-bit checksum from the CRC module. - * - * Reads the CRC data register (either an intermediate or the final checksum). - * The configured type of transpose and complement is applied. - * - * @param base CRC peripheral address. - * @return An intermediate or the final 32-bit checksum, after configured transpose and complement operations. - */ -uint32_t CRC_Get32bitResult(CRC_Type *base); - -/*! - * @brief Reads a 16-bit checksum from the CRC module. - * - * Reads the CRC data register (either an intermediate or the final checksum). - * The configured type of transpose and complement is applied. - * - * @param base CRC peripheral address. - * @return An intermediate or the final 16-bit checksum, after configured transpose and complement operations. - */ -uint16_t CRC_Get16bitResult(CRC_Type *base); - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_CRC_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ctimer.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ctimer.c deleted file mode 100644 index d15e5b66a99..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ctimer.c +++ /dev/null @@ -1,577 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_ctimer.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.ctimer" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base Ctimer peripheral base address - * - * @return The Timer instance - */ -static uint32_t CTIMER_GetInstance(CTIMER_Type *base); - -/*! - * @brief CTIMER generic IRQ handle function. - * - * @param index FlexCAN peripheral instance index. - */ -static void CTIMER_GenericIRQHandler(uint32_t index); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to Timer bases for each instance. */ -static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to Timer clocks for each instance. */ -static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET -/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N; -#else -/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; -#endif -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/*! @brief Pointers real ISRs installed by drivers for each instance. */ -static ctimer_callback_t *s_ctimerCallback[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = {0}; - -/*! @brief Callback type installed by drivers for each instance. */ -static ctimer_callback_type_t ctimerCallbackType[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = { - kCTIMER_SingleCallback}; - -/*! @brief Array to map timer instance to IRQ number. */ -static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t CTIMER_GetInstance(CTIMER_Type *base) -{ - uint32_t instance; - uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ctimerArrayCount; instance++) - { - if (s_ctimerBases[instance] == base) - { - break; - } - } - - assert(instance < ctimerArrayCount); - - return instance; -} - -/*! - * brief Ungates the clock and configures the peripheral for basic operation. - * - * note This API should be called at the beginning of the application before using the driver. - * - * param base Ctimer peripheral base address - * param config Pointer to the user configuration structure. - */ -void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) -{ - assert(config != NULL); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the timer clock*/ - CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -/* Reset the module. */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) - RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]); -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/* Setup the cimer mode and count select */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input); -#endif - /* Setup the timer prescale value */ - base->PR = CTIMER_PR_PRVAL(config->prescale); -} - -/*! - * brief Gates the timer clock. - * - * param base Ctimer peripheral base address - */ -void CTIMER_Deinit(CTIMER_Type *base) -{ - uint32_t index = CTIMER_GetInstance(base); - /* Stop the timer */ - base->TCR &= ~CTIMER_TCR_CEN_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the timer clock*/ - CLOCK_DisableClock(s_ctimerClocks[index]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Disable IRQ at NVIC Level */ - (void)DisableIRQ(s_ctimerIRQ[index]); -} - -/*! - * brief Fills in the timers configuration structure with the default settings. - * - * The default values are: - * code - * config->mode = kCTIMER_TimerMode; - * config->input = kCTIMER_Capture_0; - * config->prescale = 0; - * endcode - * param config Pointer to the user configuration structure. - */ -void CTIMER_GetDefaultConfig(ctimer_config_t *config) -{ - assert(config != NULL); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* Run as a timer */ - config->mode = kCTIMER_TimerMode; - /* This field is ignored when mode is timer */ - config->input = kCTIMER_Capture_0; - /* Timer counter is incremented on every APB bus clock */ - config->prescale = 0; -} - -/*! - * brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function can manually assign the specified channel to set the PWM cycle. - * - * note When setting PWM output from multiple output pins, all should use the same PWM - * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. - * - * param base Ctimer peripheral base address - * param pwmPeriodChannel Specify the channel to control the PWM period - * param matchChannel Match pin to be used to output the PWM signal - * param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 - * param pwmFreq_Hz PWM signal frequency in Hz - * param srcClock_Hz Timer counter clock in Hz - * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt will be generated. - * - * return kStatus_Success on success - * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM cycle - */ -status_t CTIMER_SetupPwm(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - bool enableInt) -{ - assert(pwmFreq_Hz > 0U); - - uint32_t reg; - uint32_t period, pulsePeriod = 0; - uint32_t timerClock = srcClock_Hz / (base->PR + 1U); - uint32_t index = CTIMER_GetInstance(base); - - if (matchChannel == pwmPeriodChannel) - { - return kStatus_Fail; - } - - /* Enable PWM mode on the channel */ - base->PWMC |= (1UL << (uint32_t)matchChannel); - - /* Clear the stop, reset and interrupt bits for this channel */ - reg = base->MCR; - reg &= - ~(((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK)) - << ((uint32_t)matchChannel * 3U)); - - /* If call back function is valid then enable match interrupt for the channel */ - if (enableInt) - { - reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); - } - - /* Reset the counter when match on channel 3 */ - reg |= CTIMER_MCR_MR3R_MASK; - - base->MCR = reg; - - /* Calculate PWM period match value */ - period = (timerClock / pwmFreq_Hz) - 1U; - - /* Calculate pulse width match value */ - if (dutyCyclePercent == 0U) - { - pulsePeriod = period + 1U; - } - else - { - pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; - } - - /* Specified channel pwmPeriodChannel will define the PWM period */ - base->MR[pwmPeriodChannel] = period; - - /* This will define the PWM pulse period */ - base->MR[matchChannel] = pulsePeriod; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); - /* If call back function is valid then enable interrupt and update the call back function */ - if (enableInt) - { - (void)EnableIRQ(s_ctimerIRQ[index]); - } - - return kStatus_Success; -} - -/*! - * brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function can manually assign the specified channel to set the PWM cycle. - * - * note When setting PWM output from multiple output pins, all should use the same PWM - * period - * - * param base Ctimer peripheral base address - * param pwmPeriodChannel Specify the channel to control the PWM period - * param matchChannel Match pin to be used to output the PWM signal - * param pwmPeriod PWM period match value - * param pulsePeriod Pulse width match value - * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt will be generated. - * - * return kStatus_Success on success - * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM period - */ -status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint32_t pwmPeriod, - uint32_t pulsePeriod, - bool enableInt) -{ -/* Some CTimers only have 16bits , so the value is limited*/ -#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B - assert(!((FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32) && (pulsePeriod > 0xFFFFU))); -#endif - - uint32_t reg; - uint32_t index = CTIMER_GetInstance(base); - - if (matchChannel == pwmPeriodChannel) - { - return kStatus_Fail; - } - - /* Enable PWM mode on PWM pulse channel */ - base->PWMC |= (1UL << (uint32_t)matchChannel); - - /* Clear the stop, reset and interrupt bits for PWM pulse channel */ - reg = base->MCR; - reg &= - ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) - << ((uint32_t)matchChannel * 3U)); - - /* If call back function is valid then enable match interrupt for PWM pulse channel */ - if (enableInt) - { - reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); - } - - /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ - reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); - - base->MCR = reg; - - /* Specified channel pwmPeriodChannel will define the PWM period */ - base->MR[pwmPeriodChannel] = pwmPeriod; - - /* This will define the PWM pulse period */ - base->MR[matchChannel] = pulsePeriod; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); - /* If call back function is valid then enable interrupt and update the call back function */ - if (enableInt) - { - (void)EnableIRQ(s_ctimerIRQ[index]); - } - - return kStatus_Success; -} - -/*! - * brief Updates the duty cycle of an active PWM signal. - * - * note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. - * This function can manually assign the specified channel to set the PWM cycle. - * - * param base Ctimer peripheral base address - * param pwmPeriodChannel Specify the channel to control the PWM period - * param matchChannel Match pin to be used to output the PWM signal - * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 - */ -void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent) -{ - uint32_t pulsePeriod = 0, period; - - /* Specified channel pwmPeriodChannel defines the PWM period */ - period = base->MR[pwmPeriodChannel]; - - /* For 0% dutycyle, make pulse period greater than period so the event will never occur */ - if (dutyCyclePercent == 0U) - { - pulsePeriod = period + 1U; - } - else - { - pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; - } - - /* Update dutycycle */ - base->MR[matchChannel] = pulsePeriod; -} - -/*! - * brief Setup the match register. - * - * User configuration is used to setup the match value and action to be taken when a match occurs. - * - * param base Ctimer peripheral base address - * param matchChannel Match register to configure - * param config Pointer to the match configuration structure - */ -void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config) -{ -/* Some CTimers only have 16bits , so the value is limited*/ -#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B - assert(!(FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32 && config->matchValue > 0xFFFFU)); -#endif - uint32_t reg; - uint32_t index = CTIMER_GetInstance(base); - - /* Set the counter operation when a match on this channel occurs */ - reg = base->MCR; - reg &= - ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) - << ((uint32_t)matchChannel * 3U)); - reg |= ((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)matchChannel * 3U))); - reg |= ((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)matchChannel * 3U))); - reg |= ((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); - base->MCR = reg; - - reg = base->EMR; - /* Set the match output operation when a match on this channel occurs */ - reg &= ~(((uint32_t)CTIMER_EMR_EMC0_MASK) << ((uint32_t)matchChannel * 2U)); - reg |= ((uint32_t)config->outControl) << (CTIMER_EMR_EMC0_SHIFT + ((uint32_t)matchChannel * 2U)); - - /* Set the initial state of the EM bit/output */ - reg &= ~(((uint32_t)CTIMER_EMR_EM0_MASK) << (uint32_t)matchChannel); - reg |= ((uint32_t)config->outPinInitState) << (uint32_t)matchChannel; - base->EMR = reg; - - /* Set the match value */ - base->MR[matchChannel] = config->matchValue; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); - /* If interrupt is enabled then enable interrupt and update the call back function */ - if (config->enableInterrupt) - { - (void)EnableIRQ(s_ctimerIRQ[index]); - } -} - -/*! - * brief Get the status of output match. - * - * This function gets the status of output MAT, whether or not this output is connected to a pin. - * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - * - * param base Ctimer peripheral base address - * param matchChannel External match channel, user can obtain the status of multiple match channels - * at the same time by using the logic of "|" - * enumeration ::ctimer_external_match_t - * return The mask of external match channel status flags. Users need to use the - * _ctimer_external_match type to decode the return variables. - */ -uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel) -{ - return (base->EMR & matchChannel); -} - -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) -/*! - * brief Setup the capture. - * - * param base Ctimer peripheral base address - * param capture Capture channel to configure - * param edge Edge on the channel that will trigger a capture - * param enableInt Flag to enable channel interrupts, if enabled then the registered call back - * is called upon capture - */ -void CTIMER_SetupCapture(CTIMER_Type *base, - ctimer_capture_channel_t capture, - ctimer_capture_edge_t edge, - bool enableInt) -{ - uint32_t reg = base->CCR; - uint32_t index = CTIMER_GetInstance(base); - - /* Set the capture edge */ - reg &= ~((uint32_t)((uint32_t)CTIMER_CCR_CAP0RE_MASK | (uint32_t)CTIMER_CCR_CAP0FE_MASK | - (uint32_t)CTIMER_CCR_CAP0I_MASK) - << ((uint32_t)capture * 3U)); - reg |= ((uint32_t)edge) << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U)); - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, (((uint32_t)kCTIMER_Capture0Flag) << (uint32_t)capture)); - /* If call back function is valid then enable capture interrupt for the channel and update the call back function */ - if (enableInt) - { - reg |= ((uint32_t)CTIMER_CCR_CAP0I_MASK) << ((uint32_t)capture * 3U); - (void)EnableIRQ(s_ctimerIRQ[index]); - } - base->CCR = reg; -} -#endif - -/*! - * brief Register callback. - * - * param base Ctimer peripheral base address - * param cb_func callback function - * param cb_type callback function type, singular or multiple - */ -void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type) -{ - uint32_t index = CTIMER_GetInstance(base); - s_ctimerCallback[index] = cb_func; - ctimerCallbackType[index] = cb_type; -} - -/*! - * brief CTIMER generic IRQ handle function. - * - * param index FlexCAN peripheral instance index. - */ -static void CTIMER_GenericIRQHandler(uint32_t index) -{ - uint32_t int_stat, i, mask; - /* Get Interrupt status flags */ - int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]); - /* Clear the status flags that were set */ - CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat); - if (ctimerCallbackType[index] == kCTIMER_SingleCallback) - { - if (s_ctimerCallback[index][0] != NULL) - { - s_ctimerCallback[index][0](int_stat); - } - } - else - { -#if defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE - for (i = 0; i <= CTIMER_IR_MR3INT_SHIFT; i++) -#else -#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT - for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) -#else -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) - for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) -#else - for (i = 0; i <= CTIMER_IR_CR1INT_SHIFT; i++) -#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ -#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ -#endif - { - mask = 0x01UL << i; - /* For each status flag bit that was set call the callback function if it is valid */ - if (((int_stat & mask) != 0U) && (s_ctimerCallback[index][i] != NULL)) - { - s_ctimerCallback[index][i](int_stat); - } - } - } - SDK_ISR_EXIT_BARRIER; -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(CTIMER0) -void CTIMER0_DriverIRQHandler(void); -void CTIMER0_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(0); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CTIMER1) -void CTIMER1_DriverIRQHandler(void); -void CTIMER1_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(1); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CTIMER2) -void CTIMER2_DriverIRQHandler(void); -void CTIMER2_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(2); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CTIMER3) -void CTIMER3_DriverIRQHandler(void); -void CTIMER3_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(3); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CTIMER4) -void CTIMER4_DriverIRQHandler(void); -void CTIMER4_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(4); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ctimer.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ctimer.h deleted file mode 100644 index e3a7d922a2b..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ctimer.h +++ /dev/null @@ -1,533 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_CTIMER_H_ -#define _FSL_CTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup ctimer - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1 */ -/*@}*/ - -/*! @brief List of Timer capture channels */ -typedef enum _ctimer_capture_channel -{ - kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ - kCTIMER_Capture_1, /*!< Timer capture channel 1 */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - kCTIMER_Capture_2, /*!< Timer capture channel 2 */ -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - kCTIMER_Capture_3 /*!< Timer capture channel 3 */ -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ -} ctimer_capture_channel_t; - -/*! @brief List of capture edge options */ -typedef enum _ctimer_capture_edge -{ - kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */ - kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */ - kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */ -} ctimer_capture_edge_t; - -/*! @brief List of Timer match registers */ -typedef enum _ctimer_match -{ - kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */ - kCTIMER_Match_1, /*!< Timer match register 1 */ - kCTIMER_Match_2, /*!< Timer match register 2 */ - kCTIMER_Match_3 /*!< Timer match register 3 */ -} ctimer_match_t; - -/*! @brief List of external match */ -typedef enum _ctimer_external_match -{ - kCTIMER_External_Match_0 = (1U << 0), /*!< External match 0 */ - kCTIMER_External_Match_1 = (1U << 1), /*!< External match 1 */ - kCTIMER_External_Match_2 = (1U << 2), /*!< External match 2 */ - kCTIMER_External_Match_3 = (1U << 3) /*!< External match 3 */ -} ctimer_external_match_t; - -/*! @brief List of output control options */ -typedef enum _ctimer_match_output_control -{ - kCTIMER_Output_NoAction = 0U, /*!< No action is taken */ - kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */ - kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */ - kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */ -} ctimer_match_output_control_t; - -/*! @brief List of Timer modes */ -typedef enum _ctimer_timer_mode -{ - kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */ - kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */ - kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */ - kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */ -} ctimer_timer_mode_t; - -/*! @brief List of Timer interrupts */ -typedef enum _ctimer_interrupt_enable -{ - kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ - kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ - kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ - kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ - kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ -#endif -} ctimer_interrupt_enable_t; - -/*! @brief List of Timer flags */ -typedef enum _ctimer_status_flags -{ - kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ - kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ - kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ - kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ - kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) - kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ -#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ -#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT - kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ -#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ -#endif -} ctimer_status_flags_t; - -typedef void (*ctimer_callback_t)(uint32_t flags); - -/*! @brief Callback type when registering for a callback. When registering a callback - * an array of function pointers is passed the size could be 1 or 8, the callback - * type will tell that. - */ -typedef enum -{ - kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. - based on the status flags different channels needs to be handled differently */ - kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. - for both match/capture */ -} ctimer_callback_type_t; - -/*! - * @brief Match configuration - * - * This structure holds the configuration settings for each match register. - */ -typedef struct _ctimer_match_config -{ - uint32_t matchValue; /*!< This is stored in the match register */ - bool enableCounterReset; /*!< true: Match will reset the counter - false: Match will not reser the counter */ - bool enableCounterStop; /*!< true: Match will stop the counter - false: Match will not stop the counter */ - ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */ - bool outPinInitState; /*!< Initial value of the EM bit/output */ - bool enableInterrupt; /*!< true: Generate interrupt upon match - false: Do not generate interrupt on match */ - -} ctimer_match_config_t; - -/*! - * @brief Timer configuration structure - * - * This structure holds the configuration settings for the Timer peripheral. To initialize this - * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a - * pointer to the configuration structure instance. - * - * The configuration structure can be made constant so as to reside in flash. - */ -typedef struct _ctimer_config -{ - ctimer_timer_mode_t mode; /*!< Timer mode */ - ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer - modes that rely on this input signal to increment TC */ - uint32_t prescale; /*!< Prescale value */ -} ctimer_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application before using the driver. - * - * @param base Ctimer peripheral base address - * @param config Pointer to the user configuration structure. - */ -void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config); - -/*! - * @brief Gates the timer clock. - * - * @param base Ctimer peripheral base address - */ -void CTIMER_Deinit(CTIMER_Type *base); - -/*! - * @brief Fills in the timers configuration structure with the default settings. - * - * The default values are: - * @code - * config->mode = kCTIMER_TimerMode; - * config->input = kCTIMER_Capture_0; - * config->prescale = 0; - * @endcode - * @param config Pointer to the user configuration structure. - */ -void CTIMER_GetDefaultConfig(ctimer_config_t *config); - -/*! @}*/ - -/*! - * @name PWM setup operations - * @{ - */ - -/*! - * @brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function can manually assign the specified channel to set the PWM cycle. - * - * @note When setting PWM output from multiple output pins, all should use the same PWM - * period - * - * @param base Ctimer peripheral base address - * @param pwmPeriodChannel Specify the channel to control the PWM period - * @param matchChannel Match pin to be used to output the PWM signal - * @param pwmPeriod PWM period match value - * @param pulsePeriod Pulse width match value - * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt will be generated. - */ -status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint32_t pwmPeriod, - uint32_t pulsePeriod, - bool enableInt); - -/*! - * @brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function can manually assign the specified channel to set the PWM cycle. - * - * @note When setting PWM output from multiple output pins, all should use the same PWM - * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. - * - * @param base Ctimer peripheral base address - * @param pwmPeriodChannel Specify the channel to control the PWM period - * @param matchChannel Match pin to be used to output the PWM signal - * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz Timer counter clock in Hz - * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt will be generated. - */ -status_t CTIMER_SetupPwm(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - bool enableInt); - -/*! - * @brief Updates the pulse period of an active PWM signal. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match pin to be used to output the PWM signal - * @param pulsePeriod New PWM pulse width match value - */ -static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod) -{ - /* Update PWM pulse period match value */ - base->MR[matchChannel] = pulsePeriod; -} - -/*! - * @brief Updates the duty cycle of an active PWM signal. - * - * @note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. - * This function can manually assign the specified channel to set the PWM cycle. - * - * @param base Ctimer peripheral base address - * @param pwmPeriodChannel Specify the channel to control the PWM period - * @param matchChannel Match pin to be used to output the PWM signal - * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 - */ -void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent); - -/*! @}*/ - -/*! - * @brief Setup the match register. - * - * User configuration is used to setup the match value and action to be taken when a match occurs. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match register to configure - * @param config Pointer to the match configuration structure - */ -void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config); - -/*! - * @brief Get the status of output match. - * - * This function gets the status of output MAT, whether or not this output is connected to a pin. - * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - * - * @param base Ctimer peripheral base address - * @param matchChannel External match channel, user can obtain the status of multiple match channels - * at the same time by using the logic of "|" - * enumeration ::ctimer_external_match_t - * @return The mask of external match channel status flags. Users need to use the - * _ctimer_external_match type to decode the return variables. - */ -uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel); - -/*! - * @brief Setup the capture. - * - * @param base Ctimer peripheral base address - * @param capture Capture channel to configure - * @param edge Edge on the channel that will trigger a capture - * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back - * is called upon capture - */ -void CTIMER_SetupCapture(CTIMER_Type *base, - ctimer_capture_channel_t capture, - ctimer_capture_edge_t edge, - bool enableInt); - -/*! - * @brief Get the timer count value from TC register. - * - * @param base Ctimer peripheral base address. - * @return return the timer count value. - */ -static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base) -{ - return (base->TC); -} - -/*! - * @brief Register callback. - * - * @param base Ctimer peripheral base address - * @param cb_func callback function - * @param cb_type callback function type, singular or multiple - */ -void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type); - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected Timer interrupts. - * - * @param base Ctimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) -{ - /* Enable match interrupts */ - base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); - -/* Enable capture interrupts */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - | CTIMER_CCR_CAP2I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - ); -#endif -} - -/*! - * @brief Disables the selected Timer interrupts. - * - * @param base Ctimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) -{ - /* Disable match interrupts */ - base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK)); - -/* Disable capture interrupts */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - | CTIMER_CCR_CAP2I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - )); -#endif -} - -/*! - * @brief Gets the enabled Timer interrupts. - * - * @param base Ctimer peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) -{ - uint32_t enabledIntrs = 0; - - /* Get all the match interrupts enabled */ - enabledIntrs = - base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); - -/* Get all the capture interrupts enabled */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - | CTIMER_CCR_CAP2I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - ); -#endif - - return enabledIntrs; -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the Timer status flags. - * - * @param base Ctimer peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::ctimer_status_flags_t - */ -static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base) -{ - return base->IR; -} - -/*! - * @brief Clears the Timer status flags. - * - * @param base Ctimer peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::ctimer_status_flags_t - */ -static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask) -{ - base->IR = mask; -} - -/*! @}*/ - -/*! - * @name Counter Start and Stop - * @{ - */ - -/*! - * @brief Starts the Timer counter. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_StartTimer(CTIMER_Type *base) -{ - base->TCR |= CTIMER_TCR_CEN_MASK; -} - -/*! - * @brief Stops the Timer counter. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_StopTimer(CTIMER_Type *base) -{ - base->TCR &= ~CTIMER_TCR_CEN_MASK; -} - -/*! @}*/ - -/*! - * @brief Reset the counter. - * - * The timer counter and prescale counter are reset on the next positive edge of the APB clock. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_Reset(CTIMER_Type *base) -{ - base->TCR |= CTIMER_TCR_CRST_MASK; - base->TCR &= ~CTIMER_TCR_CRST_MASK; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_CTIMER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dac.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dac.c deleted file mode 100644 index 63ebc8c5683..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dac.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_dac.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.dac_1" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for DAC module. - * - * @param base DAC peripheral base address - */ -static uint32_t DAC_GetInstance(LPDAC_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to DAC bases for each instance. */ -static LPDAC_Type *const s_dacBases[] = LPDAC_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to DAC clocks for each instance. */ -static const clock_ip_name_t s_dacClocks[] = LPDAC_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t DAC_GetInstance(LPDAC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_dacBases); instance++) - { - if (s_dacBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_dacBases)); - - return instance; -} - -/*! - * brief Initialize the DAC module with common configuartion. - * - * The clock will be enabled in this function. - * - * param base DAC peripheral base address. - * param config Pointer to configuration structure. - */ -void DAC_Init(LPDAC_Type *base, const dac_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32 = 0U; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(s_dacClocks[DAC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the logic. */ - DAC_SetReset(base, kDAC_ResetLogic); - DAC_ClearReset(base, kDAC_ResetLogic); - - /* Reset the FIFO. */ - DAC_SetReset(base, kDAC_ResetFIFO); - DAC_ClearReset(base, kDAC_ResetFIFO); - - /* Configuration. */ - if (kDAC_FIFOTriggerBySoftwareMode == config->fifoTriggerMode) - { - tmp32 |= LPDAC_GCR_TRGSEL_MASK; /* Software trigger. */ - } - switch (config->fifoWorkMode) - { - case kDAC_FIFOWorkAsNormalMode: /* Normal FIFO. */ - tmp32 |= LPDAC_GCR_FIFOEN_MASK; - break; - case kDAC_FIFOWorkAsSwingMode: - tmp32 |= LPDAC_GCR_FIFOEN_MASK | LPDAC_GCR_SWMD_MASK; /* Enable swing mode. */ - break; -#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE - case kDAC_FIFOWorkAsPeriodTriggerMode: - tmp32 |= LPDAC_GCR_FIFOEN_MASK | LPDAC_GCR_PTGEN_MASK; /* Enable period trigger mode. */ - /* Set trigger number and width. */ - base->PCR = - LPDAC_PCR_PTG_NUM(config->periodicTriggerNumber) | LPDAC_PCR_PTG_PERIOD(config->periodicTriggerWidth); - break; - case kDAC_FIFOWorkAsPeriodTriggerAndSwingMode: - tmp32 |= LPDAC_GCR_FIFOEN_MASK | LPDAC_GCR_PTGEN_MASK | LPDAC_GCR_SWMD_MASK; - /* Set trigger number and width. */ - base->PCR = - LPDAC_PCR_PTG_NUM(config->periodicTriggerNumber) | LPDAC_PCR_PTG_PERIOD(config->periodicTriggerWidth); - break; -#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */ - default: /* kDAC_FIFODisabled. */ - break; - } - -#if defined(FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG) && FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG - if (config->enableExternalTriggerSource) - { - tmp32 |= LPDAC_GCR_RCV_TRG_MASK; /* Use trigger source from another DAC. */ - } -#endif /* FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG */ -#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL - if (false == config->enableLowerLowPowerMode) - { - tmp32 |= LPDAC_GCR_BUF_SPD_CTRL_MASK; /* Enable low power. */ - } -#else - if (config->enableLowPowerMode) - { - tmp32 |= LPDAC_GCR_LPEN_MASK; /* Enable low power. */ - } -#endif /* LPDAC_GCR_BUF_SPD_CTRL_MASK */ - -#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN - tmp32 |= LPDAC_GCR_BUF_EN_MASK; /* Opamp is used as buffer. */ -#endif /* FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN */ -#if defined(FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC) && FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC - /* Configure DAC sync cycles. */ - tmp32 |= LPDAC_GCR_LATCH_CYC(config->syncTime); -#endif /* FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC */ -#if defined(FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT) && FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT - tmp32 |= config->referenceCurrentSource; -#endif /* FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT */ - /* Set reference voltage source. */ - tmp32 |= LPDAC_GCR_DACRFS(config->referenceVoltageSource); - - base->GCR = tmp32; - base->FCR = LPDAC_FCR_WML(config->fifoWatermarkLevel); - - /* Now, the DAC is disabled. It needs to be enabled in application. */ -} - -/*! - * brief Get the default settings for initialization's configuration. - * - * This function initializes the user configuration structure to a default value. The default values are: - * code - * config->fifoWatermarkLevel = 0U; - * config->fifoTriggerMode = kDAC_FIFOTriggerByHardwareMode; - * config->fifoWorkMode = kDAC_FIFODisabled; - * config->enableLowPowerMode = false; - * config->referenceVoltageSource = kDAC_ReferenceVoltageSourceAlt1; - * endcode - * - * param config Pointer to configuration structure. - * param - */ -void DAC_GetDefaultConfig(dac_config_t *config) -{ - assert(config != NULL); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->fifoWatermarkLevel = 0U; - config->fifoTriggerMode = kDAC_FIFOTriggerByHardwareMode; - config->fifoWorkMode = kDAC_FIFODisabled; - -#if defined(FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG) && FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG - config->enableExternalTriggerSource = false; -#endif /* FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG */ -#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL - config->enableLowerLowPowerMode = true; -#else - config->enableLowPowerMode = false; -#endif /* FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL */ -#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE - config->periodicTriggerNumber = 0UL; - config->periodicTriggerWidth = 0UL; -#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */ -#if defined(FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC) && FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC - /* Configure DAC sync cycles. */ - config->syncTime = 1U; -#endif /* FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC */ -#if defined(FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT) && FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT - config->referenceCurrentSource = kDAC_ReferenceCurrentSourcePtat; -#endif /* FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT */ - config->referenceVoltageSource = kDAC_ReferenceVoltageSourceAlt1; -} - -/*! - * brief De-initialize the DAC module. - * - * The clock will be disabled in this function. - * - * param base DAC peripheral base address. - * param - */ -void DAC_Deinit(LPDAC_Type *base) -{ - /* Disable the module. */ - DAC_Enable(base, false); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(s_dacClocks[DAC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dac.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dac.h deleted file mode 100644 index 3241e08cb61..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dac.h +++ /dev/null @@ -1,442 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_DAC_H_ -#define _FSL_DAC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup dac - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief DAC driver version 2.1.0. */ -#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) -/*@}*/ - -/*! - * @brief DAC reset control. - */ -enum -{ - kDAC_ResetFIFO = LPDAC_RCR_FIFORST_MASK, /*!< Resets the FIFO pointers and flags. */ - kDAC_ResetLogic = LPDAC_RCR_SWRST_MASK, /*!< Resets all DAC registers and internal logic. */ -}; - -/*! - * @brief DAC interrupts. - */ -enum -{ - kDAC_FIFOFullInterruptEnable = LPDAC_IER_FULL_IE_MASK, /*!< FIFO full interrupt enable. */ - kDAC_FIFOEmptyInterruptEnable = LPDAC_IER_EMPTY_IE_MASK, /*!< FIFO empty interrupt enable. */ - kDAC_FIFOWatermarkInterruptEnable = LPDAC_IER_WM_IE_MASK, /*!< FIFO watermark interrupt enable. */ - kDAC_SwingBackInterruptEnable = LPDAC_IER_SWBK_IE_MASK, /*!< Swing back one cycle complete interrupt enable. */ - kDAC_FIFOOverflowInterruptEnable = LPDAC_IER_OF_IE_MASK, /*!< FIFO overflow interrupt enable. */ - kDAC_FIFOUnderflowInterruptEnable = LPDAC_IER_UF_IE_MASK, /*!< FIFO underflow interrupt enable. */ -#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE - kDAC_PeriodTriggerCompleteInterruptEnable = - LPDAC_IER_PTGCOCO_IE_MASK, /*!< Period trigger mode conversion complete interrupt enable */ -#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */ -}; - -/*! - * @brief DAC DMA switchers. - */ -enum -{ - kDAC_FIFOEmptyDMAEnable = LPDAC_DER_EMPTY_DMAEN_MASK, /*!< FIFO empty DMA enable. */ - kDAC_FIFOWatermarkDMAEnable = LPDAC_DER_WM_DMAEN_MASK, /*!< FIFO watermark DMA enable. */ -}; - -/*! - * @brief DAC status flags. - */ -enum -{ - kDAC_FIFOUnderflowFlag = LPDAC_FSR_UF_MASK, /*!< This flag means that there is a new trigger after the buffer is -empty. The FIFO read pointer will not -increase in this case and the data sent to DAC analog conversion will not changed. This flag is cleared by writing a 1 -to it. */ - - kDAC_FIFOOverflowFlag = - LPDAC_FSR_OF_MASK, /*!< This flag indicates that data is intended to write into FIFO after the -buffer is full. The writer pointer will -not increase in this case. The extra data will not be written into the FIFO. This flag is cleared by writing a 1 to it. -*/ - - kDAC_FIFOSwingBackFlag = LPDAC_FSR_SWBK_MASK, /*!< This flag indicates that the DAC has completed one period of -conversion in swing back mode. It means -that the read pointer has increased to the top (write pointer) once and then decreased to zero once. For -example, after three data is written to FIFO, the writer pointer is now 3. Then, if continually triggered, the -read pointer will swing like: 0-1-2-1-0-1-2-, and so on. After the fourth trigger, the flag is set. This flag is -cleared by writing a 1 to it. */ - - kDAC_FIFOWatermarkFlag = LPDAC_FSR_WM_MASK, /*!< This field is set if the remaining data in FIFO is less than or - equal to the setting value of wartermark. By writing data into FIFO by DMA or CPU, this flag is - cleared automatically when the data in FIFO is more than the setting value of watermark. */ - - kDAC_FIFOEmptyFlag = LPDAC_FSR_EMPTY_MASK, /*!< FIFO empty flag. */ - kDAC_FIFOFullFlag = LPDAC_FSR_FULL_MASK, /*!< FIFO full flag. */ -#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE - kDAC_PeriodTriggerCompleteFlag = LPDAC_FSR_PTGCOCO_MASK, /*!< Period trigger mode conversion complete flag. */ -#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */ -}; - -/*! - * @brief DAC FIFO trigger mode. - */ -typedef enum _dac_fifo_trigger_mode -{ - kDAC_FIFOTriggerByHardwareMode = 0U, /*!< Buffer would be triggered by hardware. */ - kDAC_FIFOTriggerBySoftwareMode = 1U, /*!< Buffer would be triggered by software. */ -} dac_fifo_trigger_mode_t; - -/*! - * @brief DAC FIFO work mode. - */ -typedef enum _dac_fifo_work_mode -{ - kDAC_FIFODisabled = 0U, /*!< FIFO mode is disabled and buffer mode is enabled. Any data written to DATA[DATA] goes - to buffer then goes to conversion. */ - kDAC_FIFOWorkAsNormalMode = 1U, /*!< FIFO mode is enabled. Data will be first read from FIFO to buffer then goes to - conversion. */ - kDAC_FIFOWorkAsSwingMode = 2U, /*!< In swing mode, the read pointer swings between the writer pointer and zero. That - is, the trigger increases the read pointer till reach the writer pointer and - decreases the read pointer till zero, and so on. The FIFO empty/full/watermark - flag will not update during swing back mode. */ -#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE - kDAC_FIFOWorkAsPeriodTriggerMode = - 3U, /*!< In periodic trigger mode, user only needs to send the first trigger. Then after every [PTG_PERIOD+1] - RCLK cycles, DAC will be automatically triggered by internal trigger. There will be [PTG_NUM] internal - triggers, thus in total [PTG_NUM+1] conversions including the first trigger sent by user. User can - terminate the current conversion queue by clearing the GCR[PTGEN] bit. Then, after the current conversion - is completed, the conversion is terminated and the PTGCOCO flag is set. If PCR[PTG_NUM] is set to zero, - there will be infinite triggers following the first hardware/software trigger, until the GCR[PTGEN] is - cleared by software. In any case, the conversion can be terminated by FIFORST/SWRST. */ - kDAC_FIFOWorkAsPeriodTriggerAndSwingMode = 4U, /*!< Periodically trigger DAC and swing back. */ -#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */ -} dac_fifo_work_mode_t; - -/*! - * @brief DAC reference voltage source. - */ -typedef enum _dac_reference_voltage_source -{ -#if defined(FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC) && (FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC == 3) - kDAC_ReferenceVoltageSourceAlt1 = 0U, /*!< The DAC selects VDD_ANA as the reference voltage. */ - kDAC_ReferenceVoltageSourceAlt2 = 1U, /*!< The DAC selects VREF_OUT as the reference voltage. */ - kDAC_ReferenceVoltageSourceAlt3 = 2U, /*!< THe DAC selects VREFH as the reference voltage. */ -#else - kDAC_ReferenceVoltageSourceAlt1 = 0U, /*!< The DAC selects VREFH_INT as the reference voltage. */ - kDAC_ReferenceVoltageSourceAlt2 = 1U, /*!< The DAC selects VREFH_EXT as the reference voltage. */ -#endif /* FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC */ -} dac_reference_voltage_source_t; - -#if defined(FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT) && FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT -/* - * @brief DAC internal reference current source - */ -typedef enum _dac_reference_current_source -{ - kDAC_ReferenceCurrentSourcePtat = LPDAC_GCR_IREF_PTAT_EXT_SEL_MASK, /* Internal PTAT Current Reference selected */ - kDAC_ReferenceCurrentSourceZtc = LPDAC_GCR_IREF_ZTC_EXT_SEL_MASK, /* Internal ZTC Current Reference selected */ -} dac_reference_current_source_t; -#endif /* FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT */ - -/*! - * @brief DAC configuration structure. - */ -typedef struct _dac_config -{ - uint32_t fifoWatermarkLevel; /*!< FIFO's watermark, the max value can be the hardware FIFO size. */ - dac_fifo_trigger_mode_t fifoTriggerMode; /*!< Select the trigger mode for FIFO. */ - dac_fifo_work_mode_t fifoWorkMode; /*!< Select the work mode for FIFO. */ -#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN - bool enableOpampBuffer; /*!< Opamp is used as buffer. */ -#endif /* FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN */ -#if defined(FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG) && FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG - bool enableExternalTriggerSource; /* DAC uses another DAC's hardware/software trigger as its trigger source. */ -#endif /* FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG */ -#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL - bool enableLowerLowPowerMode; /*!< Enable the lower low power mode. */ -#else - bool enableLowPowerMode; /*!< Enable the low power mode. */ -#endif /* FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL */ -#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE - uint32_t periodicTriggerNumber; /*!< There will be 'periodicTriggerNumber' internal triggers following the first - hardware/software trigger. So there will be 'periodicTriggerNumber + 1' - conversions in total. If set to zero, there will be infinite triggers following - the first hw/sw trigger, until the GCR[PTGEN] is cleared. */ - uint32_t periodicTriggerWidth; /*!< Control the periodic trigger frequency. There will be 'periodicTriggerWidth + 1' - RCLK cycles between each periodic trigger. The periodic trigger frequency should - be configured to not larger than the analog conversion speed. */ -#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */ -#if defined(FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC) && FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC - uint32_t syncTime; /*!< RCLK cycles before data latch. accessible range is 0-15. It is used to configure the DAC - sync cycles which is helpful to reduce glitch on the output. The sync time is (LATCH_CYC+1) - RCLK cycles. User should configure this register according to the RCLK frequency. The - recommended sync time is at least 40ns.*/ -#endif /* FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC */ -#if defined(FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT) && FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT - dac_reference_current_source_t referenceCurrentSource; /*!< Select the internal reference current source. */ -#endif /* FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT */ - dac_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */ -} dac_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and de-initialization - * @{ - */ - -/*! - * @brief Initialize the DAC module with common configuartion. - * - * The clock will be enabled in this function. - * - * @param base DAC peripheral base address. - * @param config Pointer to configuration structure. - */ -void DAC_Init(LPDAC_Type *base, const dac_config_t *config); - -/*! - * @brief Get the default settings for initialization's configuration. - * - * This function initializes the user configuration structure to a default value. The default values are: - * @code - * config->fifoWatermarkLevel = 0U; - * config->fifoTriggerMode = kDAC_FIFOTriggerByHardwareMode; - * config->fifoWorkMode = kDAC_FIFODisabled; - * config->enableLowPowerMode = false; - * config->referenceVoltageSource = kDAC_ReferenceVoltageSourceAlt1; - * @endcode - * - * @param config Pointer to configuration structure. - */ -void DAC_GetDefaultConfig(dac_config_t *config); - -/*! - * @brief De-initialize the DAC module. - * - * The clock will be disabled in this function. - * - * @param base DAC peripheral base address. - */ -void DAC_Deinit(LPDAC_Type *base); - -/*! - * @brief Assert the reset control to part hardware. - * - * This function is to assert the reset control to part hardware. Responding part hardware would remain reset untill - * cleared by software. - * - * @param base DAC peripheral base address. - * @param mask The reset control mask, see to _dac_reset_control_t. - */ -static inline void DAC_SetReset(LPDAC_Type *base, uint32_t mask) -{ - base->RCR |= mask; -} - -/*! - * @brief Clear the reset control to part hardware. - * - * This function is to clear the reset control to part hardware. Responding part hardware would work after the reset - * control is cleared by software. - * - * @param base DAC peripheral base address. - * @param mask The reset control mask, see to _dac_reset_control_t. - */ -static inline void DAC_ClearReset(LPDAC_Type *base, uint32_t mask) -{ - base->RCR &= ~mask; -} - -/*! - * @brief Enable the DAC hardware system or not. - * - * This function is to start the Programmable Reference Generator operation or not. - * - * @param base DAC peripheral base address. - * @param enable Assertion of indicated event. - */ -static inline void DAC_Enable(LPDAC_Type *base, bool enable) -{ - if (enable) - { - base->GCR |= LPDAC_GCR_DACEN_MASK; - } - else - { - base->GCR &= ~LPDAC_GCR_DACEN_MASK; - } -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enable the interrupts. - * - * @param base DAC peripheral base address. - * @param mask Mask value of indicated interrupt events. See to _dac_interrupt_enable. - */ -static inline void DAC_EnableInterrupts(LPDAC_Type *base, uint32_t mask) -{ - base->IER |= mask; -} - -/*! - * @brief Disable the interrupts. - * - * @param base DAC peripheral base address. - * @param mask Mask value of indicated interrupt events. See to _dac_interrupt_enable. - */ -static inline void DAC_DisableInterrupts(LPDAC_Type *base, uint32_t mask) -{ - base->IER &= ~mask; -} - -/* @} */ - -/*! - * @name DMA control - * @{ - */ - -/*! - * @brief Enable the DMA switchers or not. - * - * @param base DAC peripheral base address. - * @param mask Mask value of indicated DMA requeset. See to _dac_dma_enable. - * @param enable Enable the DMA or not. - */ -static inline void DAC_EnableDMA(LPDAC_Type *base, uint32_t mask, bool enable) -{ - if (enable) - { - base->DER |= mask; - } - else - { - base->DER &= ~mask; - } -} - -/* @} */ - -/*! - * @name Status flags - * @{ - */ - -/*! - * @brief Get status flags of DAC module. - * - * @param base DAC peripheral base address. - * @return Mask value of status flags. See to _dac_status_flags. - */ -static inline uint32_t DAC_GetStatusFlags(LPDAC_Type *base) -{ - return base->FSR; -} - -/*! - * @brief Clear status flags of DAC module. - * - * @param base DAC peripheral base address. - * @param flags Mask value of status flags to be cleared. See to _dac_status_flags. - */ -static inline void DAC_ClearStatusFlags(LPDAC_Type *base, uint32_t flags) -{ - base->FSR = flags; -} - -/* @} */ - -/*! - * @name Functional feature - * @{ - */ - -/*! - * @brief Set data into the entry of FIFO buffer. - * - * @param base DAC peripheral base address. - * @param value Setting value into FIFO buffer. - */ -static inline void DAC_SetData(LPDAC_Type *base, uint32_t value) -{ - base->DATA = LPDAC_DATA_DATA(value); -} - -/*! - * @brief Get the value of the FIFO write pointer. - * - * @param base DAC peripheral base address. - * @return Current value of the FIFO write pointer. - */ - -static inline uint32_t DAC_GetFIFOWritePointer(LPDAC_Type *base) -{ - return (LPDAC_FPR_FIFO_WPT_MASK & base->FPR) >> LPDAC_FPR_FIFO_WPT_SHIFT; -} - -/*! - * @brief Get the value of the FIFO read pointer. - * - * @param base DAC peripheral base address. - * @return Current value of the FIFO read pointer. - */ - -static inline uint32_t DAC_GetFIFOReadPointer(LPDAC_Type *base) -{ - return (LPDAC_FPR_FIFO_RPT_MASK & base->FPR) >> LPDAC_FPR_FIFO_RPT_SHIFT; -} - -/*! - * @brief Do software trigger to FIFO when in software mode. - * - * @param base DAC peripheral base address. - */ - -static inline void DAC_DoSoftwareTriggerFIFO(LPDAC_Type *base) -{ - base->TCR = LPDAC_TCR_SWTRG_MASK; -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ -#endif /* _FSL_DAC12_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dma.c deleted file mode 100644 index c0664e4b5c7..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dma.c +++ /dev/null @@ -1,1074 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_dma.h" -#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) -#include "fsl_memory.h" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_dma" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for DMA. - * - * @param base DMA peripheral base address. - */ -static uint32_t DMA_GetInstance(DMA_Type *base); - -/*! - * @brief Get virtual channel number. - * - * @param base DMA peripheral base address. - */ -static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map DMA instance number to base pointer. */ -static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map DMA instance number to clock name. */ -static const clock_ip_name_t s_dmaClockName[] = DMA_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET) -/*! @brief Pointers to DMA resets for each instance. */ -static const reset_ip_name_t s_dmaResets[] = DMA_RSTS_N; -#endif /*! @brief Array to map DMA instance number to IRQ number. */ -static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS; - -/*! @brief Pointers to transfer handle for each DMA channel. */ -static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_ALL_CHANNELS]; - -/*! @brief DMA driver internal descriptor table */ -#ifdef FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE -SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE); -#else -#if (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) -AT_NONCACHEABLE_SECTION_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -#else -SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -#endif /* (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) */ -#endif /* FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE */ - -#if defined(DMA1) -#ifdef FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE -SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE); -#else -#if (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) -AT_NONCACHEABLE_SECTION_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -#else -SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -#endif /* (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) */ -#endif /* FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE */ -static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0, s_dma_descriptor_table1}; -#else -static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0}; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t DMA_GetInstance(DMA_Type *base) -{ - uint32_t instance; - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++) - { - if (s_dmaBases[instance] == base) - { - break; - } - } - assert(instance < ARRAY_SIZE(s_dmaBases)); - - return instance; -} - -static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base) -{ - uint32_t startChannel = 0, instance = 0; - uint32_t i = 0; - - instance = DMA_GetInstance(base); - - /* Compute start channel */ - for (i = 0; i < instance; i++) - { - startChannel += (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(s_dmaBases[i]); - } - - return startChannel; -} - -/*! - * brief Initializes DMA peripheral. - * - * This function enable the DMA clock, set descriptor table and - * enable DMA peripheral. - * - * param base DMA peripheral base address. - */ -void DMA_Init(DMA_Type *base) -{ - uint32_t instance = DMA_GetInstance(base); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* enable dma clock gate */ - CLOCK_EnableClock(s_dmaClockName[DMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET) - /* Reset the DMA module */ - RESET_PeripheralReset(s_dmaResets[DMA_GetInstance(base)]); -#endif - /* set descriptor table */ -#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) - base->SRAMBASE = MEMORY_ConvertMemoryMapAddress((uint32_t)s_dma_descriptor_table[instance], kMEMORY_Local2DMA); -#else - base->SRAMBASE = (uint32_t)s_dma_descriptor_table[instance]; -#endif - /* enable dma peripheral */ - base->CTRL |= DMA_CTRL_ENABLE_MASK; -} - -/*! - * brief Deinitializes DMA peripheral. - * - * This function gates the DMA clock. - * - * param base DMA peripheral base address. - */ -void DMA_Deinit(DMA_Type *base) -{ - /* Disable DMA peripheral */ - base->CTRL &= ~(DMA_CTRL_ENABLE_MASK); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(s_dmaClockName[DMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Set trigger settings of DMA channel. - * deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig. - * - * param base DMA peripheral base address. - * param channel DMA channel number. - * param trigger trigger configuration. - */ -void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger) -{ - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); - assert((channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)) && (NULL != trigger)); - - uint32_t tmpReg = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | - DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | - DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK); - tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); - tmpReg |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); - base->CHANNEL[channel].CFG = tmpReg; -} - -/*! - * brief Gets the remaining bytes of the current DMA descriptor transfer. - * - * param base DMA peripheral base address. - * param channel DMA channel number. - * return The number of bytes which have not been transferred yet. - */ -uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) -{ - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); - assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - - /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes - * impossible to distinguish between: - * - transfer finishes (represented by value '0x3FF') - * - and remaining 1024 bytes to transfer (value 0x3FF) - * for all descriptor in chain, except the last one. - * If you decide to use this function, please use 1023 transfers as maximal value */ - - /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */ - if ((!DMA_ChannelIsActive(base, channel)) && - (0x3FFUL == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> - DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))) - { - return 0UL; - } - - return ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> - DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + - 1UL; -} - -/* Verify and convert dma_xfercfg_t to XFERCFG register */ -static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr) -{ - assert(xfercfg != NULL); - /* check source increment */ - assert((xfercfg->srcInc <= (uint8_t)kDMA_AddressInterleave4xWidth) && - (xfercfg->dstInc <= (uint8_t)kDMA_AddressInterleave4xWidth)); - /* check data width */ - assert(xfercfg->byteWidth <= (uint8_t)kDMA_Transfer32BitWidth); - /* check transfer count */ - assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT); - - uint32_t xfer = 0; - - /* set valid flag - descriptor is ready now */ - xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid); - /* set reload - allow link to next descriptor */ - xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload); - /* set swtrig flag - start transfer */ - xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig); - /* set transfer count */ - xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig); - /* set INTA */ - xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA); - /* set INTB */ - xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB); - /* set data width */ - xfer |= DMA_CHANNEL_XFERCFG_WIDTH(xfercfg->byteWidth == 4U ? 2U : xfercfg->byteWidth - 1UL); - /* set source increment value */ - xfer |= DMA_CHANNEL_XFERCFG_SRCINC( - (xfercfg->srcInc == (uint8_t)kDMA_AddressInterleave4xWidth) ? (xfercfg->srcInc - 1UL) : xfercfg->srcInc); - /* set destination increment value */ - xfer |= DMA_CHANNEL_XFERCFG_DSTINC( - (xfercfg->dstInc == (uint8_t)kDMA_AddressInterleave4xWidth) ? (xfercfg->dstInc - 1UL) : xfercfg->dstInc); - /* set transfer count */ - xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1UL); - - /* store xferCFG */ - *xfercfg_addr = xfer; -} - -/*! - * brief setup dma descriptor - * Note: This function do not support configure wrap descriptor. - * param desc DMA descriptor address. - * param xfercfg Transfer configuration for DMA descriptor. - * param srcStartAddr Start address of source address. - * param dstStartAddr Start address of destination address. - * param nextDesc Address of next descriptor in chain. - */ -void DMA_SetupDescriptor( - dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) -{ - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - -#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) - srcStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)srcStartAddr, kMEMORY_Local2DMA); - dstStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)dstStartAddr, kMEMORY_Local2DMA); - nextDesc = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)nextDesc, kMEMORY_Local2DMA); -#endif - - uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; - - width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT; - srcInc = (xfercfg & DMA_CHANNEL_XFERCFG_SRCINC_MASK) >> DMA_CHANNEL_XFERCFG_SRCINC_SHIFT; - dstInc = (xfercfg & DMA_CHANNEL_XFERCFG_DSTINC_MASK) >> DMA_CHANNEL_XFERCFG_DSTINC_SHIFT; - transferCount = ((xfercfg & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1U; - - /* covert register value to actual value */ - if (width == 2U) - { - width = kDMA_Transfer32BitWidth; - } - else - { - width += 1U; - } - - /* - * Transfers of 16 bit width require an address alignment to a multiple of 2 bytes. - * Transfers of 32 bit width require an address alignment to a multiple of 4 bytes. - * Transfers of 8 bit width can be at any address - */ - if (((NULL != srcStartAddr) && (0UL == ((uint32_t)(uint32_t *)srcStartAddr) % width)) && - ((NULL != dstStartAddr) && (0UL == ((uint32_t)(uint32_t *)dstStartAddr) % width))) - { - if (srcInc == 3U) - { - srcInc = kDMA_AddressInterleave4xWidth; - } - - if (dstInc == 3U) - { - dstInc = kDMA_AddressInterleave4xWidth; - } - - desc->xfercfg = xfercfg; - desc->srcEndAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); - desc->dstEndAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); - desc->linkToNextDesc = nextDesc; - } - else - { - /* if address alignment not satisfy the requirement, reset the descriptor to make sure DMA generate error */ - desc->xfercfg = 0U; - desc->srcEndAddr = NULL; - desc->dstEndAddr = NULL; - } -} - -/*! - * brief setup dma channel descriptor - * Note: This function support configure wrap descriptor. - * param desc DMA descriptor address. - * param xfercfg Transfer configuration for DMA descriptor. - * param srcStartAddr Start address of source address. - * param dstStartAddr Start address of destination address. - * param nextDesc Address of next descriptor in chain. - * param wrapType burst wrap type. - * param burstSize burst size, reference _dma_burst_size. - */ -void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, - uint32_t xfercfg, - void *srcStartAddr, - void *dstStartAddr, - void *nextDesc, - dma_burst_wrap_t wrapType, - uint32_t burstSize) -{ - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - -#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) - srcStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)srcStartAddr, kMEMORY_Local2DMA); - dstStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)dstStartAddr, kMEMORY_Local2DMA); - nextDesc = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)nextDesc, kMEMORY_Local2DMA); -#endif - - uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; - - width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT; - srcInc = (xfercfg & DMA_CHANNEL_XFERCFG_SRCINC_MASK) >> DMA_CHANNEL_XFERCFG_SRCINC_SHIFT; - dstInc = (xfercfg & DMA_CHANNEL_XFERCFG_DSTINC_MASK) >> DMA_CHANNEL_XFERCFG_DSTINC_SHIFT; - transferCount = ((xfercfg & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1U; - - /* covert register value to actual value */ - if (width == 2U) - { - width = kDMA_Transfer32BitWidth; - } - else - { - width += 1U; - } - - /* - * Transfers of 16 bit width require an address alignment to a multiple of 2 bytes. - * Transfers of 32 bit width require an address alignment to a multiple of 4 bytes. - * Transfers of 8 bit width can be at any address - */ - if (((NULL != srcStartAddr) && (0UL == ((uint32_t)(uint32_t *)srcStartAddr) % width)) && - ((NULL != dstStartAddr) && (0UL == ((uint32_t)(uint32_t *)dstStartAddr) % width))) - { - if (srcInc == 3U) - { - srcInc = kDMA_AddressInterleave4xWidth; - } - - if (dstInc == 3U) - { - dstInc = kDMA_AddressInterleave4xWidth; - } - - desc->xfercfg = xfercfg; - - if (wrapType == kDMA_NoWrap) - { - desc->srcEndAddr = - DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); - desc->dstEndAddr = - DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); - } - /* for the wrap transfer, the destination address should be determined by the burstSize/width/interleave size */ - if (wrapType == kDMA_SrcWrap) - { - desc->srcEndAddr = - (uint32_t *)((uint32_t)(uint32_t *)srcStartAddr + ((1UL << burstSize) - 1UL) * width * srcInc); - desc->dstEndAddr = - DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); - } - if (wrapType == kDMA_DstWrap) - { - desc->srcEndAddr = - DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); - desc->dstEndAddr = - (uint32_t *)((uint32_t)(uint32_t *)dstStartAddr + ((1UL << burstSize) - 1UL) * width * dstInc); - } - if (wrapType == kDMA_SrcAndDstWrap) - { - desc->srcEndAddr = - (uint32_t *)(((uint32_t)(uint32_t *)srcStartAddr) + ((1UL << burstSize) - 1UL) * width * srcInc); - desc->dstEndAddr = - (uint32_t *)(((uint32_t)(uint32_t *)dstStartAddr) + ((1UL << burstSize) - 1UL) * width * dstInc); - } - - desc->linkToNextDesc = nextDesc; - } - else - { - /* if address alignment not satisfy the requirement, reset the descriptor to make sure DMA generate error */ - desc->xfercfg = 0U; - desc->srcEndAddr = NULL; - desc->dstEndAddr = NULL; - } -} - -/*! - * brief Create application specific DMA descriptor - * to be used in a chain in transfer - * deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor - * param desc DMA descriptor address. - * param xfercfg Transfer configuration for DMA descriptor. - * param srcAddr Address of last item to transmit - * param dstAddr Address of last item to receive. - * param nextDesc Address of next descriptor in chain. - */ -void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc) -{ - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - assert((NULL != srcAddr) && (0UL == ((uint32_t)(uint32_t *)srcAddr) % xfercfg->byteWidth)); - assert((NULL != dstAddr) && (0UL == ((uint32_t)(uint32_t *)dstAddr) % xfercfg->byteWidth)); - - uint32_t xfercfg_reg = 0; - - DMA_SetupXferCFG(xfercfg, &xfercfg_reg); - - /* Set descriptor structure */ - DMA_SetupDescriptor(desc, xfercfg_reg, srcAddr, dstAddr, nextDesc); -} - -/*! - * brief Abort running transfer by handle. - * - * This function aborts DMA transfer specified by handle. - * - * param handle DMA handle pointer. - */ -void DMA_AbortTransfer(dma_handle_t *handle) -{ - assert(NULL != handle); - - DMA_DisableChannel(handle->base, handle->channel); - while ((DMA_COMMON_CONST_REG_GET(handle->base, handle->channel, BUSY) & - (1UL << DMA_CHANNEL_INDEX(handle->base, handle->channel))) != 0UL) - { - } - DMA_COMMON_REG_GET(handle->base, handle->channel, ABORT) |= 1UL << DMA_CHANNEL_INDEX(handle->base, handle->channel); - DMA_EnableChannel(handle->base, handle->channel); -} - -/*! - * brief Creates the DMA handle. - * - * This function is called if using transaction API for DMA. This function - * initializes the internal state of DMA handle. - * - * param handle DMA handle pointer. The DMA handle stores callback function and - * parameters. - * param base DMA peripheral base address. - * param channel DMA channel number. - */ -void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel) -{ - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); - assert((NULL != handle) && (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - - uint32_t dmaInstance; - uint32_t startChannel = 0; - /* base address is invalid DMA instance */ - dmaInstance = DMA_GetInstance(base); - startChannel = DMA_GetVirtualStartChannel(base); - - (void)memset(handle, 0, sizeof(*handle)); - handle->base = base; - handle->channel = (uint8_t)channel; - s_DMAHandle[startChannel + channel] = handle; - /* Enable NVIC interrupt */ - (void)EnableIRQ(s_dmaIRQNumber[dmaInstance]); - /* Enable channel interrupt */ - DMA_EnableChannelInterrupts(handle->base, channel); -} - -/*! - * brief Installs a callback function for the DMA transfer. - * - * This callback is called in DMA IRQ handler. Use the callback to do something after - * the current major loop transfer completes. - * - * param handle DMA handle pointer. - * param callback DMA callback function pointer. - * param userData Parameter for callback function. - */ -void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData) -{ - assert(handle != NULL); - - handle->callback = callback; - handle->userData = userData; -} - -/*! - * brief Prepares the DMA transfer structure. - * deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer and - * DMA_PrepareChannelXfer. - * This function prepares the transfer configuration structure according to the user input. - * - * param config The user configuration structure of type dma_transfer_t. - * param srcAddr DMA transfer source address. - * param dstAddr DMA transfer destination address. - * param byteWidth DMA transfer destination address width(bytes). - * param transferBytes DMA transfer bytes to be transferred. - * param type DMA transfer type. - * param nextDesc Chain custom descriptor to transfer. - * note The data address and the data width must be consistent. For example, if the SRC - * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in - * source address error(SAE). - */ -void DMA_PrepareTransfer(dma_transfer_config_t *config, - void *srcAddr, - void *dstAddr, - uint32_t byteWidth, - uint32_t transferBytes, - dma_transfer_type_t type, - void *nextDesc) -{ - uint32_t xfer_count; - assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr)); - assert((byteWidth == 1UL) || (byteWidth == 2UL) || (byteWidth == 4UL)); - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - - /* check max */ - xfer_count = transferBytes / byteWidth; - assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0UL == transferBytes % byteWidth)); - - (void)memset(config, 0, sizeof(*config)); - - if (type == kDMA_MemoryToMemory) - { - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 1; - config->isPeriph = false; - } - - else if (type == kDMA_PeripheralToMemory) - { - /* Peripheral register - source doesn't increment */ - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 1; - config->isPeriph = true; - } - else if (type == kDMA_MemoryToPeripheral) - { - /* Peripheral register - destination doesn't increment */ - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - } - /* kDMA_StaticToStatic */ - else - { - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - } - - config->dstAddr = (uint8_t *)dstAddr; - config->srcAddr = (uint8_t *)srcAddr; - config->nextDesc = (uint8_t *)nextDesc; - config->xfercfg.transferCount = (uint16_t)xfer_count; - config->xfercfg.byteWidth = (uint8_t)byteWidth; - config->xfercfg.intA = true; - config->xfercfg.reload = nextDesc != NULL; - config->xfercfg.valid = true; -} - -/*! - * brief set channel config. - * - * This function provide a interface to configure channel configuration reisters. - * - * param base DMA base address. - * param channel DMA channel number. - * param config channel configurations structure. - */ -void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph) -{ - assert(channel < (uint32_t)FSL_FEATURE_DMA_MAX_CHANNELS); - - uint32_t tmpReg = DMA_CHANNEL_CFG_PERIPHREQEN_MASK; - - if (trigger != NULL) - { - tmpReg |= DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | - DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | - DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK; - } - - tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); - - if (trigger != NULL) - { - tmpReg |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); - } - - tmpReg |= DMA_CHANNEL_CFG_PERIPHREQEN(isPeriph); - - base->CHANNEL[channel].CFG = tmpReg; -} - -/*! - * brief Prepare channel transfer configurations. - * - * This function used to prepare channel transfer configurations. - * - * param config Pointer to DMA channel transfer configuration structure. - * param srcStartAddr source start address. - * param dstStartAddr destination start address. - * param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * param type transfer type. - * param trigger DMA channel trigger configurations. - * param nextDesc address of next descriptor. - */ -void DMA_PrepareChannelTransfer(dma_channel_config_t *config, - void *srcStartAddr, - void *dstStartAddr, - uint32_t xferCfg, - dma_transfer_type_t type, - dma_channel_trigger_t *trigger, - void *nextDesc) -{ - assert((NULL != config) && (NULL != srcStartAddr) && (NULL != dstStartAddr)); - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - - /* check max */ - (void)memset(config, 0, sizeof(*config)); - - if (type == kDMA_MemoryToMemory) - { - config->isPeriph = false; - } - else if (type == kDMA_PeripheralToMemory) - { - config->isPeriph = true; - } - else if (type == kDMA_MemoryToPeripheral) - { - config->isPeriph = true; - } - /* kDMA_StaticToStatic */ - else - { - config->isPeriph = true; - } - - config->dstStartAddr = (uint8_t *)dstStartAddr; - config->srcStartAddr = (uint8_t *)srcStartAddr; - config->nextDesc = (uint8_t *)nextDesc; - config->trigger = trigger; - config->xferCfg = xferCfg; -} - -/*! - * brief load channel transfer decriptor. - * - * This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA - * transfer, the head descriptor table is defined in DMA driver, it is useful for the case: - * 1. for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly - * and then call this api to load the configured descriptor to driver descriptor table. code DMA_Init(DMA0); - * DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL); - * DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL); - * DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc); - * DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL); - * while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL)) - * {} - * endcode - * - * param base DMA base address. - * param channel DMA channel. - * param descriptor configured DMA descriptor. - */ -void DMA_LoadChannelDescriptor(DMA_Type *base, uint32_t channel, dma_descriptor_t *descriptor) -{ - assert(NULL != descriptor); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); - assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - - uint32_t instance = DMA_GetInstance(base); - dma_descriptor_t *channelDescriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][channel]); - - channelDescriptor->xfercfg = descriptor->xfercfg; - channelDescriptor->srcEndAddr = descriptor->srcEndAddr; - channelDescriptor->dstEndAddr = descriptor->dstEndAddr; - channelDescriptor->linkToNextDesc = descriptor->linkToNextDesc; - - /* Set channel XFERCFG register according first channel descriptor. */ - base->CHANNEL[channel].XFERCFG = descriptor->xfercfg; -} - -/*! - * brief Install DMA descriptor memory. - * - * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong - * transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has - * a default DMA descriptor buffer, but it support one DMA descriptor for one channel only. - * User should be take care about the address of DMA descriptor pool which required align with 512BYTE. - * - * param handle Pointer to DMA channel transfer handle. - * param addr DMA descriptor address - * param num DMA descriptor number. - */ -void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr) -{ - assert(addr != NULL); - -#if defined FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn - assert((((uint32_t)(uint32_t *)addr) & ((uint32_t)FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn(base) - 1UL)) == 0U); -#else - assert((((uint32_t)(uint32_t *)addr) & ((uint32_t)FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0U); -#endif - /* reconfigure the DMA descriptor base address */ - base->SRAMBASE = (uint32_t)(uint32_t *)addr; -} - -/*! - * brief Submit channel transfer paramter directly. - * - * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table - * is defined in DMA driver, it is useful for the case: - * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used - for it. - * code - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, - bytes), srcStartAddr, dstStartAddr, NULL); - DMA_StartTransfer(handle) - * endcode - * - * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is - required, then application should prepare - * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc2); - DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, NULL); - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, - bytes), srcStartAddr, dstStartAddr, nextDesc0); - DMA_StartTransfer(handle); - * endcode - * - * param handle Pointer to DMA handle. - * param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * param srcStartAddr source start address. - * param dstStartAddr destination start address. - * param nextDesc address of next descriptor. - */ -void DMA_SubmitChannelTransferParameter( - dma_handle_t *handle, uint32_t xferCfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) -{ - assert((NULL != srcStartAddr) && (NULL != dstStartAddr)); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); - assert(handle->channel < (uint8_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - - uint32_t instance = DMA_GetInstance(handle->base); - dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); - - DMA_SetupDescriptor(descriptor, xferCfg, srcStartAddr, dstStartAddr, nextDesc); - - /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = xferCfg; -} - -/*! - * brief Submit channel descriptor. - * - * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table - is defined in - * DMA driver, this functiono is typical for the ping pong case: - * - * 1. for the ping pong case, application should responsible for the descriptor, for example, application should - * prepare two descriptor table with macro. - * code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc0); - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelDescriptor(handle, nextDesc0); - DMA_StartTransfer(handle); - * endcode - * - * param handle Pointer to DMA handle. - * param descriptor descriptor to submit. - */ -void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descriptor) -{ - assert((NULL != handle) && (NULL != descriptor)); - - DMA_LoadChannelDescriptor(handle->base, handle->channel, descriptor); -} - -/*! - * brief Submits the DMA channel transfer request. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * It is used for the case: - * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used - for it. - * code - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,NULL); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * endcode - * - * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is - required, then application should prepare - * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc2); - DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, NULL); - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * endcode - * - * 3. for the ping pong case, application should responsible for link descriptor, for example, application should - prepare - * two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc0); - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * endcode - * param handle DMA handle pointer. - * param config Pointer to DMA transfer configuration structure. - * retval kStatus_DMA_Success It means submit transfer request succeed. - * retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config) -{ - assert((NULL != handle) && (NULL != config)); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); - assert(handle->channel < (uint8_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - uint32_t instance = DMA_GetInstance(handle->base); - dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); - - /* Previous transfer has not finished */ - if (DMA_ChannelIsActive(handle->base, handle->channel)) - { - return kStatus_DMA_Busy; - } - - /* setup channgel trigger configurations */ - DMA_SetChannelConfig(handle->base, handle->channel, config->trigger, config->isPeriph); - - DMA_SetupChannelDescriptor( - descriptor, config->xferCfg, config->srcStartAddr, config->dstStartAddr, config->nextDesc, - config->trigger == NULL ? kDMA_NoWrap : config->trigger->wrap, - (config->trigger == NULL ? (uint32_t)kDMA_BurstSize1 : - ((uint32_t)config->trigger->burst & (DMA_CHANNEL_CFG_BURSTPOWER_MASK)) >> - DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)); - - /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = config->xferCfg; - - return kStatus_Success; -} - -/*! - * brief Submits the DMA transfer request. - * deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * - * param handle DMA handle pointer. - * param config Pointer to DMA transfer configuration structure. - * retval kStatus_DMA_Success It means submit transfer request succeed. - * retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) -{ - assert((NULL != handle) && (NULL != config)); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); - assert(handle->channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - - uint32_t instance = DMA_GetInstance(handle->base); - dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); - - /* Previous transfer has not finished */ - if (DMA_ChannelIsActive(handle->base, handle->channel)) - { - return kStatus_DMA_Busy; - } - - /* enable/disable peripheral request */ - if (config->isPeriph) - { - DMA_EnableChannelPeriphRq(handle->base, handle->channel); - } - else - { - DMA_DisableChannelPeriphRq(handle->base, handle->channel); - } - - DMA_CreateDescriptor(descriptor, &config->xfercfg, config->srcAddr, config->dstAddr, config->nextDesc); - /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = descriptor->xfercfg; - - return kStatus_Success; -} - -/*! - * brief DMA start transfer. - * - * This function enables the channel request. User can call this function after submitting the transfer request - * It will trigger transfer start with software trigger only when hardware trigger is not used. - * - * param handle DMA handle pointer. - */ -void DMA_StartTransfer(dma_handle_t *handle) -{ - assert(NULL != handle); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); - - uint32_t channel = handle->channel; - assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - - /* enable channel */ - DMA_EnableChannel(handle->base, channel); - - /* Do software trigger only when HW trigger is not enabled. */ - if ((handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK) == 0U) - { - handle->base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; - } -} - -void DMA_IRQHandle(DMA_Type *base) -{ - dma_handle_t *handle; - uint8_t channel_index; - uint32_t startChannel = DMA_GetVirtualStartChannel(base); - uint32_t i = 0; - - /* Find channels that have completed transfer */ - for (i = 0; i < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base); i++) - { - handle = s_DMAHandle[i + startChannel]; - /* Handle is not present */ - if (NULL == handle) - { - continue; - } - channel_index = DMA_CHANNEL_INDEX(base, handle->channel); - /* Channel uses INTA flag */ - if ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTA) & (1UL << channel_index)) != 0UL) - { - /* Clear INTA flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, INTA, (1UL << channel_index)); - if (handle->callback != NULL) - { - (handle->callback)(handle, handle->userData, true, kDMA_IntA); - } - } - /* Channel uses INTB flag */ - if ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTB) & (1UL << channel_index)) != 0UL) - { - /* Clear INTB flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, INTB, (1UL << channel_index)); - if (handle->callback != NULL) - { - (handle->callback)(handle, handle->userData, true, kDMA_IntB); - } - } - /* Error flag */ - if ((DMA_COMMON_REG_GET(handle->base, handle->channel, ERRINT) & (1UL << channel_index)) != 0UL) - { - /* Clear error flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, ERRINT, (1UL << channel_index)); - if (handle->callback != NULL) - { - (handle->callback)(handle, handle->userData, false, kDMA_IntError); - } - } - } -} - -void DMA0_DriverIRQHandler(void); -void DMA0_DriverIRQHandler(void) -{ - DMA_IRQHandle(DMA0); - SDK_ISR_EXIT_BARRIER; -} - -#if defined(DMA1) -void DMA1_DriverIRQHandler(void); -void DMA1_DriverIRQHandler(void) -{ - DMA_IRQHandle(DMA1); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dma.h deleted file mode 100644 index c6a7c1a209f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dma.h +++ /dev/null @@ -1,892 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_DMA_H_ -#define _FSL_DMA_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup dma - * @{ - */ - -/*! @file */ -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief DMA driver version */ -#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 3)) /*!< Version 2.4.3. */ -/*@}*/ - -/*! @brief DMA max transfer size */ -#define DMA_MAX_TRANSFER_COUNT 0x400U -/*! @brief DMA channel numbers */ -#if defined FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_MAX_CHANNELS FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_ALL_CHANNELS (FSL_FEATURE_DMA_NUMBER_OF_CHANNELS * FSL_FEATURE_SOC_DMA_COUNT) -#endif -/*! @brief DMA head link descriptor table align size */ -#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) -/*! @brief DMA head descriptor table allocate macro - * To simplify user interface, this macro will help allocate descriptor memory, - * user just need to provide the name and the number for the allocate descriptor. - * - * @param name Allocate decriptor name. - * @param number Number of descriptor to be allocated. - */ -#define DMA_ALLOCATE_HEAD_DESCRIPTORS(name, number) \ - SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE) -/*! @brief DMA head descriptor table allocate macro at noncacheable section - * To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, - * user just need to provide the name and the number for the allocate descriptor. - * - * @param name Allocate decriptor name. - * @param number Number of descriptor to be allocated. - */ -#define DMA_ALLOCATE_HEAD_DESCRIPTORS_AT_NONCACHEABLE(name, number) \ - AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE) -/*! @brief DMA link descriptor table allocate macro - * To simplify user interface, this macro will help allocate descriptor memory, - * user just need to provide the name and the number for the allocate descriptor. - * - * @param name Allocate decriptor name. - * @param number Number of descriptor to be allocated. - */ -#define DMA_ALLOCATE_LINK_DESCRIPTORS(name, number) \ - SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE) -/*! @brief DMA link descriptor table allocate macro at noncacheable section - * To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, - * user just need to provide the name and the number for the allocate descriptor. - * - * @param name Allocate decriptor name. - * @param number Number of descriptor to be allocated. - */ -#define DMA_ALLOCATE_LINK_DESCRIPTORS_AT_NONCACHEABLE(name, number) \ - AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE) -/*! @brief DMA transfer buffer address need to align with the transfer width */ -#define DMA_ALLOCATE_DATA_TRANSFER_BUFFER(name, width) SDK_ALIGN(name, width) -/* Channel group consists of 32 channels. channel_group = 0 */ -#define DMA_CHANNEL_GROUP(channel) (0U) -/* Channel index in channel group. channel_index = (channel % (channel number per instance)) */ -#define DMA_CHANNEL_INDEX(base, channel) (((uint8_t)(channel)) % FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)) -/*! @brief DMA linked descriptor address algin size */ -#define DMA_COMMON_REG_GET(base, channel, reg) \ - (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) -#define DMA_COMMON_CONST_REG_GET(base, channel, reg) \ - (((volatile const uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) -#define DMA_COMMON_REG_SET(base, channel, reg, value) \ - (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)] = (value)) - -/*! @brief DMA descriptor end address calculate - * @param start start address - * @param inc address interleave size - * @param bytes transfer bytes - * @param width transfer width - */ -#define DMA_DESCRIPTOR_END_ADDRESS(start, inc, bytes, width) \ - ((uint32_t *)((uint32_t)(start) + (inc) * (bytes) - (inc) * (width))) - -/*! @brief DMA channel transfer configurations macro - * @param reload true is reload link descriptor after current exhaust, false is not - * @param clrTrig true is clear trigger status, wait software trigger, false is not - * @param intA enable interruptA - * @param intB enable interruptB - * @param width transfer width - * @param srcInc source address interleave size - * @param dstInc destination address interleave size - * @param bytes transfer bytes - */ -#define DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes) \ - DMA_CHANNEL_XFERCFG_CFGVALID_MASK | DMA_CHANNEL_XFERCFG_RELOAD(reload) | DMA_CHANNEL_XFERCFG_CLRTRIG(clrTrig) | \ - DMA_CHANNEL_XFERCFG_SETINTA(intA) | DMA_CHANNEL_XFERCFG_SETINTB(intB) | \ - DMA_CHANNEL_XFERCFG_WIDTH(width == 4UL ? 2UL : (width - 1UL)) | \ - DMA_CHANNEL_XFERCFG_SRCINC(srcInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (srcInc - 1UL) : srcInc) | \ - DMA_CHANNEL_XFERCFG_DSTINC(dstInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (dstInc - 1UL) : dstInc) | \ - DMA_CHANNEL_XFERCFG_XFERCOUNT(bytes / width - 1UL) - -/*! @brief _dma_transfer_status DMA transfer status */ -enum -{ - kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the - transfer request. */ -}; - -/*! @brief _dma_addr_interleave_size dma address interleave size */ -enum -{ - kDMA_AddressInterleave0xWidth = 0U, /*!< dma source/destination address no interleave */ - kDMA_AddressInterleave1xWidth = 1U, /*!< dma source/destination address interleave 1xwidth */ - kDMA_AddressInterleave2xWidth = 2U, /*!< dma source/destination address interleave 2xwidth */ - kDMA_AddressInterleave4xWidth = 4U, /*!< dma source/destination address interleave 3xwidth */ -}; - -/*! @brief _dma_transfer_width dma transfer width */ -enum -{ - kDMA_Transfer8BitWidth = 1U, /*!< dma channel transfer bit width is 8 bit */ - kDMA_Transfer16BitWidth = 2U, /*!< dma channel transfer bit width is 16 bit */ - kDMA_Transfer32BitWidth = 4U, /*!< dma channel transfer bit width is 32 bit */ -}; - -/*! @brief DMA descriptor structure */ -typedef struct _dma_descriptor -{ - volatile uint32_t xfercfg; /*!< Transfer configuration */ - void *srcEndAddr; /*!< Last source address of DMA transfer */ - void *dstEndAddr; /*!< Last destination address of DMA transfer */ - void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */ -} dma_descriptor_t; - -/*! @brief DMA transfer configuration */ -typedef struct _dma_xfercfg -{ - bool valid; /*!< Descriptor is ready to transfer */ - bool reload; /*!< Reload channel configuration register after - current descriptor is exhausted */ - bool swtrig; /*!< Perform software trigger. Transfer if fired - when 'valid' is set */ - bool clrtrig; /*!< Clear trigger */ - bool intA; /*!< Raises IRQ when transfer is done and set IRQA status register flag */ - bool intB; /*!< Raises IRQ when transfer is done and set IRQB status register flag */ - uint8_t byteWidth; /*!< Byte width of data to transfer */ - uint8_t srcInc; /*!< Increment source address by 'srcInc' x 'byteWidth' */ - uint8_t dstInc; /*!< Increment destination address by 'dstInc' x 'byteWidth' */ - uint16_t transferCount; /*!< Number of transfers */ -} dma_xfercfg_t; - -/*! @brief DMA channel priority */ -typedef enum _dma_priority -{ - kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */ - kDMA_ChannelPriority1, /*!< Channel priority 1 */ - kDMA_ChannelPriority2, /*!< Channel priority 2 */ - kDMA_ChannelPriority3, /*!< Channel priority 3 */ - kDMA_ChannelPriority4, /*!< Channel priority 4 */ - kDMA_ChannelPriority5, /*!< Channel priority 5 */ - kDMA_ChannelPriority6, /*!< Channel priority 6 */ - kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */ -} dma_priority_t; - -/*! @brief DMA interrupt flags */ -typedef enum _dma_int -{ - kDMA_IntA, /*!< DMA interrupt flag A */ - kDMA_IntB, /*!< DMA interrupt flag B */ - kDMA_IntError, /*!< DMA interrupt flag error */ -} dma_irq_t; - -/*! @brief DMA trigger type*/ -typedef enum _dma_trigger_type -{ - kDMA_NoTrigger = 0, /*!< Trigger is disabled */ - kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */ - kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | - DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */ - kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */ - kDMA_RisingEdgeTrigger = - DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */ -} dma_trigger_type_t; - -/*! @brief _dma_burst_size DMA burst size*/ -enum -{ - kDMA_BurstSize1 = 0U, /*!< burst size 1 transfer */ - kDMA_BurstSize2 = 1U, /*!< burst size 2 transfer */ - kDMA_BurstSize4 = 2U, /*!< burst size 4 transfer */ - kDMA_BurstSize8 = 3U, /*!< burst size 8 transfer */ - kDMA_BurstSize16 = 4U, /*!< burst size 16 transfer */ - kDMA_BurstSize32 = 5U, /*!< burst size 32 transfer */ - kDMA_BurstSize64 = 6U, /*!< burst size 64 transfer */ - kDMA_BurstSize128 = 7U, /*!< burst size 128 transfer */ - kDMA_BurstSize256 = 8U, /*!< burst size 256 transfer */ - kDMA_BurstSize512 = 9U, /*!< burst size 512 transfer */ - kDMA_BurstSize1024 = 10U, /*!< burst size 1024 transfer */ -}; - -/*! @brief DMA trigger burst */ -typedef enum _dma_trigger_burst -{ - kDMA_SingleTransfer = 0, /*!< Single transfer */ - kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */ - kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */ - kDMA_EdgeBurstTransfer2 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */ - kDMA_EdgeBurstTransfer4 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */ - kDMA_EdgeBurstTransfer8 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */ - kDMA_EdgeBurstTransfer16 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */ - kDMA_EdgeBurstTransfer32 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */ - kDMA_EdgeBurstTransfer64 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */ - kDMA_EdgeBurstTransfer128 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */ - kDMA_EdgeBurstTransfer256 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */ - kDMA_EdgeBurstTransfer512 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */ - kDMA_EdgeBurstTransfer1024 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */ -} dma_trigger_burst_t; - -/*! @brief DMA burst wrapping */ -typedef enum _dma_burst_wrap -{ - kDMA_NoWrap = 0, /*!< Wrapping is disabled */ - kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */ - kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */ - kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | - DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */ -} dma_burst_wrap_t; - -/*! @brief DMA transfer type */ -typedef enum _dma_transfer_type -{ - kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */ - kDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory (increment only destination) */ - kDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral (increment only source)*/ - kDMA_StaticToStatic, /*!< Peripheral to static memory (do not increment source or destination) */ -} dma_transfer_type_t; - -/*! @brief DMA channel trigger */ -typedef struct _dma_channel_trigger -{ - dma_trigger_type_t type; /*!< Select hardware trigger as edge triggered or level triggered. */ - dma_trigger_burst_t burst; /*!< Select whether hardware triggers cause a single or burst transfer. */ - dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */ -} dma_channel_trigger_t; - -/*! @brief DMA channel trigger */ -typedef struct _dma_channel_config -{ - void *srcStartAddr; /*!< Source data address */ - void *dstStartAddr; /*!< Destination data address */ - void *nextDesc; /*!< Chain custom descriptor */ - uint32_t xferCfg; /*!< channel transfer configurations */ - dma_channel_trigger_t *trigger; /*!< DMA trigger type */ - bool isPeriph; /*!< select the request type */ -} dma_channel_config_t; - -/*! @brief DMA transfer configuration */ -typedef struct _dma_transfer_config -{ - uint8_t *srcAddr; /*!< Source data address */ - uint8_t *dstAddr; /*!< Destination data address */ - uint8_t *nextDesc; /*!< Chain custom descriptor */ - dma_xfercfg_t xfercfg; /*!< Transfer options */ - bool isPeriph; /*!< DMA transfer is driven by peripheral */ -} dma_transfer_config_t; - -/*! @brief Callback for DMA */ -struct _dma_handle; - -/*! @brief Define Callback function for DMA. */ -typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode); - -/*! @brief DMA transfer handle structure */ -typedef struct _dma_handle -{ - dma_callback callback; /*!< Callback function. Invoked when transfer - of descriptor with interrupt flag finishes */ - void *userData; /*!< Callback function parameter */ - DMA_Type *base; /*!< DMA peripheral base address */ - uint8_t channel; /*!< DMA channel number */ -} dma_handle_t; - -/******************************************************************************* - * APIs - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name DMA initialization and De-initialization - * @{ - */ - -/*! - * @brief Initializes DMA peripheral. - * - * This function enable the DMA clock, set descriptor table and - * enable DMA peripheral. - * - * @param base DMA peripheral base address. - */ -void DMA_Init(DMA_Type *base); - -/*! - * @brief Deinitializes DMA peripheral. - * - * This function gates the DMA clock. - * - * @param base DMA peripheral base address. - */ -void DMA_Deinit(DMA_Type *base); - -/*! - * @brief Install DMA descriptor memory. - * - * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong - * transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has - * a default DMA descriptor buffer, but it support one DMA descriptor for one channel only. - * - * @param base DMA base address. - * @param addr DMA descriptor address - */ -void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr); - -/* @} */ - -/*! - * @name DMA Channel Operation - * @{ - */ - -/*! - * @brief Return whether DMA channel is processing transfer - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return True for active state, false otherwise. - */ -static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - - return (DMA_COMMON_CONST_REG_GET(base, channel, ACTIVE) & (1UL << DMA_CHANNEL_INDEX(base, channel))) != 0UL; -} - -/*! - * @brief Return whether DMA channel is busy - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return True for busy state, false otherwise. - */ -static inline bool DMA_ChannelIsBusy(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - - return (DMA_COMMON_CONST_REG_GET(base, channel, BUSY) & (1UL << DMA_CHANNEL_INDEX(base, channel))) != 0UL; -} - -/*! - * @brief Enables the interrupt source for the DMA transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - DMA_COMMON_REG_GET(base, channel, INTENSET) |= 1UL << DMA_CHANNEL_INDEX(base, channel); -} - -/*! - * @brief Disables the interrupt source for the DMA transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - DMA_COMMON_REG_GET(base, channel, INTENCLR) |= 1UL << DMA_CHANNEL_INDEX(base, channel); -} - -/*! - * @brief Enable DMA channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - DMA_COMMON_REG_GET(base, channel, ENABLESET) |= 1UL << DMA_CHANNEL_INDEX(base, channel); -} - -/*! - * @brief Disable DMA channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - DMA_COMMON_REG_GET(base, channel, ENABLECLR) |= 1UL << DMA_CHANNEL_INDEX(base, channel); -} - -/*! - * @brief Set PERIPHREQEN of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK; -} - -/*! - * @brief Get PERIPHREQEN value of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return True for enabled PeriphRq, false for disabled. - */ -static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK; -} - -/*! - * @brief Set trigger settings of DMA channel. - * @deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param trigger trigger configuration. - */ -void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger); - -/*! - * @brief set channel config. - * - * This function provide a interface to configure channel configuration reisters. - * - * @param base DMA base address. - * @param channel DMA channel number. - * @param trigger channel configurations structure. - * @param isPeriph true is periph request, false is not. - */ -void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph); - -/*! - * @brief Gets the remaining bytes of the current DMA descriptor transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return The number of bytes which have not been transferred yet. - */ -uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel); - -/*! - * @brief Set priority of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param priority Channel priority value. - */ -static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - base->CHANNEL[channel].CFG = - (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority); -} - -/*! - * @brief Get priority of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return Channel priority value. - */ -static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - return (dma_priority_t)(uint8_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> - DMA_CHANNEL_CFG_CHPRIORITY_SHIFT); -} - -/*! - * @brief Set channel configuration valid. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_SetChannelConfigValid(DMA_Type *base, uint32_t channel) -{ - base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_CFGVALID_MASK; -} - -/*! - * @brief Do software trigger for the channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DoChannelSoftwareTrigger(DMA_Type *base, uint32_t channel) -{ - base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; -} - -/*! - * @brief Load channel transfer configurations. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param xfer transfer configurations. - */ -static inline void DMA_LoadChannelTransferConfig(DMA_Type *base, uint32_t channel, uint32_t xfer) -{ - base->CHANNEL[channel].XFERCFG = xfer; -} - -/*! - * @brief Create application specific DMA descriptor - * to be used in a chain in transfer - * @deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor. - * @param desc DMA descriptor address. - * @param xfercfg Transfer configuration for DMA descriptor. - * @param srcAddr Address of last item to transmit - * @param dstAddr Address of last item to receive. - * @param nextDesc Address of next descriptor in chain. - */ -void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc); - -/*! - * @brief setup dma descriptor - * - * Note: This function do not support configure wrap descriptor. - * - * @param desc DMA descriptor address. - * @param xfercfg Transfer configuration for DMA descriptor. - * @param srcStartAddr Start address of source address. - * @param dstStartAddr Start address of destination address. - * @param nextDesc Address of next descriptor in chain. - */ -void DMA_SetupDescriptor( - dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc); - -/*! - * @brief setup dma channel descriptor - * - * Note: This function support configure wrap descriptor. - * - * @param desc DMA descriptor address. - * @param xfercfg Transfer configuration for DMA descriptor. - * @param srcStartAddr Start address of source address. - * @param dstStartAddr Start address of destination address. - * @param nextDesc Address of next descriptor in chain. - * @param wrapType burst wrap type. - * @param burstSize burst size, reference _dma_burst_size. - */ -void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, - uint32_t xfercfg, - void *srcStartAddr, - void *dstStartAddr, - void *nextDesc, - dma_burst_wrap_t wrapType, - uint32_t burstSize); - -/*! - * @brief load channel transfer decriptor. - * - * This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA - * transfer, the head descriptor table is defined in DMA driver, it is useful for the case: - * 1. for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly - * and then call this api to load the configured descriptor to driver descriptor table. - * @code - * DMA_Init(DMA0); - * DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL); - * DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL); - * DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc); - * DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL); - * while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL)) - * {} - * @endcode - * - * @param base DMA base address. - * @param channel DMA channel. - * @param descriptor configured DMA descriptor. - */ -void DMA_LoadChannelDescriptor(DMA_Type *base, uint32_t channel, dma_descriptor_t *descriptor); - -/* @} */ - -/*! - * @name DMA Transactional Operation - * @{ - */ - -/*! - * @brief Abort running transfer by handle. - * - * This function aborts DMA transfer specified by handle. - * - * @param handle DMA handle pointer. - */ -void DMA_AbortTransfer(dma_handle_t *handle); - -/*! - * @brief Creates the DMA handle. - * - * This function is called if using transaction API for DMA. This function - * initializes the internal state of DMA handle. - * - * @param handle DMA handle pointer. The DMA handle stores callback function and - * parameters. - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel); - -/*! - * @brief Installs a callback function for the DMA transfer. - * - * This callback is called in DMA IRQ handler. Use the callback to do something after - * the current major loop transfer completes. - * - * @param handle DMA handle pointer. - * @param callback DMA callback function pointer. - * @param userData Parameter for callback function. - */ -void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData); - -/*! - * @brief Prepares the DMA transfer structure. - * @deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer. - * This function prepares the transfer configuration structure according to the user input. - * - * @param config The user configuration structure of type dma_transfer_t. - * @param srcAddr DMA transfer source address. - * @param dstAddr DMA transfer destination address. - * @param byteWidth DMA transfer destination address width(bytes). - * @param transferBytes DMA transfer bytes to be transferred. - * @param type DMA transfer type. - * @param nextDesc Chain custom descriptor to transfer. - * @note The data address and the data width must be consistent. For example, if the SRC - * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in - * source address error(SAE). - */ -void DMA_PrepareTransfer(dma_transfer_config_t *config, - void *srcAddr, - void *dstAddr, - uint32_t byteWidth, - uint32_t transferBytes, - dma_transfer_type_t type, - void *nextDesc); - -/*! - * @brief Prepare channel transfer configurations. - * - * This function used to prepare channel transfer configurations. - * - * @param config Pointer to DMA channel transfer configuration structure. - * @param srcStartAddr source start address. - * @param dstStartAddr destination start address. - * @param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * @param type transfer type. - * @param trigger DMA channel trigger configurations. - * @param nextDesc address of next descriptor. - */ -void DMA_PrepareChannelTransfer(dma_channel_config_t *config, - void *srcStartAddr, - void *dstStartAddr, - uint32_t xferCfg, - dma_transfer_type_t type, - dma_channel_trigger_t *trigger, - void *nextDesc); - -/*! - * @brief Submits the DMA transfer request. - * @deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * - * @param handle DMA handle pointer. - * @param config Pointer to DMA transfer configuration structure. - * @retval kStatus_DMA_Success It means submit transfer request succeed. - * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config); - -/*! - * @brief Submit channel transfer paramter directly. - * - * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table - * is defined in DMA driver, it is useful for the case: - * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used - for it. - * @code - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, - bytes), srcStartAddr, dstStartAddr, NULL); - DMA_StartTransfer(handle) - * @endcode - * - * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is - required, then application should prepare - * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * @code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc2); - DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, NULL); - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, - bytes), srcStartAddr, dstStartAddr, nextDesc0); - DMA_StartTransfer(handle); - * @endcode - * - * @param handle Pointer to DMA handle. - * @param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * @param srcStartAddr source start address. - * @param dstStartAddr destination start address. - * @param nextDesc address of next descriptor. - */ -void DMA_SubmitChannelTransferParameter( - dma_handle_t *handle, uint32_t xferCfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc); - -/*! - * @brief Submit channel descriptor. - * - * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table - is defined in - * DMA driver, this functiono is typical for the ping pong case: - * - * 1. for the ping pong case, application should responsible for the descriptor, for example, application should - * prepare two descriptor table with macro. - * @code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc0); - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelDescriptor(handle, nextDesc0); - DMA_StartTransfer(handle); - * @endcode - * - * @param handle Pointer to DMA handle. - * @param descriptor descriptor to submit. - */ -void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descriptor); - -/*! - * @brief Submits the DMA channel transfer request. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * It is used for the case: - * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used - for it. - * @code - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,NULL); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * @endcode - * - * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is - required, then application should prepare - * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * @code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc2); - DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, NULL); - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * @endcode - * - * 3. for the ping pong case, application should responsible for link descriptor, for example, application should - prepare - * two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * @code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc0); - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * @endcode - * @param handle DMA handle pointer. - * @param config Pointer to DMA transfer configuration structure. - * @retval kStatus_DMA_Success It means submit transfer request succeed. - * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config); - -/*! - * @brief DMA start transfer. - * - * This function enables the channel request. User can call this function after submitting the transfer request - * It will trigger transfer start with software trigger only when hardware trigger is not used. - * - * @param handle DMA handle pointer. - */ -void DMA_StartTransfer(dma_handle_t *handle); - -/*! - * @brief DMA IRQ handler for descriptor transfer complete. - * - * This function clears the channel major interrupt flag and call - * the callback function if it is not NULL. - * - * @param base DMA base address. - */ -void DMA_IRQHandle(DMA_Type *base); - -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/* @} */ - -#endif /*_FSL_DMA_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic.c deleted file mode 100644 index 5782d85195b..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic.c +++ /dev/null @@ -1,390 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_dmic.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.dmic" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* Array of DMIC peripheral base address. */ -static DMIC_Type *const s_dmicBases[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of DMIC clock name. */ -static const clock_ip_name_t s_dmicClock[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/* Array of DMIC IRQ number. */ -static const IRQn_Type s_dmicIRQ[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_IRQS; - -/*! @brief Callback function array for DMIC(s). */ -static dmic_callback_t s_dmicCallback[FSL_FEATURE_SOC_DMIC_COUNT]; - -/* Array of HWVAD IRQ number. */ -static const IRQn_Type s_dmicHwvadIRQ[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_HWVAD_IRQS; - -/*! @brief Callback function array for HWVAD(s). */ -static dmic_hwvad_callback_t s_dmicHwvadCallback[FSL_FEATURE_SOC_DMIC_COUNT]; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get the DMIC instance from peripheral base address. - * - * @param base DMIC peripheral base address. - * @return DMIC instance. - */ -/*! - * brief Get the DMIC instance from peripheral base address. - * - * param base DMIC peripheral base address. - * return DMIC instance. - */ -uint32_t DMIC_GetInstance(DMIC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_dmicBases); instance++) - { - if (s_dmicBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_dmicBases)); - - return instance; -} - -/*! - * brief Turns DMIC Clock on - * param base : DMIC base - * return Nothing - */ -void DMIC_Init(DMIC_Type *base) -{ - assert(base != NULL); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(s_dmicClock[DMIC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kDMIC_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - - /* reset FIFO configuration */ - base->CHANNEL[0].FIFO_CTRL = 0U; - base->CHANNEL[1].FIFO_CTRL = 0U; -#if defined(FSL_FEATURE_DMIC_CHANNEL_NUM) && (FSL_FEATURE_DMIC_CHANNEL_NUM == 8U) - base->CHANNEL[3].FIFO_CTRL = 0U; - base->CHANNEL[4].FIFO_CTRL = 0U; - base->CHANNEL[5].FIFO_CTRL = 0U; - base->CHANNEL[6].FIFO_CTRL = 0U; - base->CHANNEL[7].FIFO_CTRL = 0U; -#endif -} - -/*! - * brief Turns DMIC Clock off - * param base : DMIC base - * return Nothing - */ -void DMIC_DeInit(DMIC_Type *base) -{ - assert(base != NULL); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(s_dmicClock[DMIC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -#if !(defined(FSL_FEATURE_DMIC_HAS_NO_IOCFG) && FSL_FEATURE_DMIC_HAS_NO_IOCFG) -/*! - * brief Configure DMIC io - * @deprecated Do not use this function. It has been superceded by @ref DMIC_SetIOCFG - * param base : The base address of DMIC interface - * param config : DMIC io configuration - * return Nothing - */ -void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config) -{ - base->IOCFG = (uint32_t)config; -} -#endif - -/*! - * brief Set DMIC operating mode - * deprecated Do not use this function. It has been superceded by @ref - * DMIC_EnableChannelInterrupt/DMIC_EnableChannelDma - * param base : The base address of DMIC interface - * param mode : DMIC mode - * return Nothing - */ -void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode) -{ - if (mode == kDMIC_OperationModeInterrupt) - { - /* Enable DMIC interrupt. */ - base->CHANNEL[0].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN(1); - base->CHANNEL[1].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN(1); - } - if (mode == kDMIC_OperationModeDma) - { - /* enable DMA request*/ - base->CHANNEL[0].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN(1); - base->CHANNEL[1].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN(1); - } -} - -/*! - * brief Configure DMIC channel - * - * param base : The base address of DMIC interface - * param channel : DMIC channel - * param side : stereo_side_t, choice of left or right - * param channel_config : Channel configuration - * return Nothing - */ -void DMIC_ConfigChannel(DMIC_Type *base, - dmic_channel_t channel, - stereo_side_t side, - dmic_channel_config_t *channel_config) -{ - base->CHANNEL[channel].DIVHFCLK = (uint32_t)channel_config->divhfclk; - base->CHANNEL[channel].OSR = channel_config->osr; - base->CHANNEL[channel].GAINSHIFT = (uint32_t)channel_config->gainshft; - base->CHANNEL[channel].PREAC2FSCOEF = (uint32_t)channel_config->preac2coef; - base->CHANNEL[channel].PREAC4FSCOEF = (uint32_t)channel_config->preac4coef; - base->CHANNEL[channel].PHY_CTRL = - DMIC_CHANNEL_PHY_CTRL_PHY_FALL(side) | DMIC_CHANNEL_PHY_CTRL_PHY_HALF(channel_config->sample_rate); - base->CHANNEL[channel].DC_CTRL = DMIC_CHANNEL_DC_CTRL_DCPOLE(channel_config->dc_cut_level) | - DMIC_CHANNEL_DC_CTRL_DCGAIN(channel_config->post_dc_gain_reduce) | - DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(channel_config->saturate16bit); - -#if defined(FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND) && (FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND) - base->CHANNEL[channel].DC_CTRL |= DMIC_CHANNEL_DC_CTRL_SIGNEXTEND(channel_config->enableSignExtend); -#endif -} - -/*! - * brief Configure DMIC channel - * param base : The base address of DMIC interface - * param channel : DMIC channel - * param dc_cut_level : dc_removal_t, Cut off Frequency - * param post_dc_gain_reduce : Fine g!y!9 - * param saturate16bit : If selects 16-bit saturation. - */ -void DMIC_CfgChannelDc(DMIC_Type *base, - dmic_channel_t channel, - dc_removal_t dc_cut_level, - uint32_t post_dc_gain_reduce, - bool saturate16bit) -{ - base->CHANNEL[channel].DC_CTRL = DMIC_CHANNEL_DC_CTRL_DCPOLE(dc_cut_level) | - DMIC_CHANNEL_DC_CTRL_DCGAIN(post_dc_gain_reduce) | - DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(saturate16bit); -} - -/*! - * brief Configure Clock scaling - * param base : The base address of DMIC interface - * param use2fs : clock scaling - * return Nothing - */ -void DMIC_Use2fs(DMIC_Type *base, bool use2fs) -{ - base->USE2FS = (use2fs) ? 0x1UL : 0x0UL; -} - -/*! - * brief Enable a particualr channel - * param base : The base address of DMIC interface - * param channelmask : Channel selection - * return Nothing - */ -void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask) -{ - base->CHANEN |= channelmask; -} - -/*! - * brief Configure fifo settings for DMIC channel - * param base : The base address of DMIC interface - * param channel : DMIC channel - * param trig_level : FIFO trigger level - * param enable : FIFO level - * param resetn : FIFO reset - * return Nothing - */ -void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn) -{ - base->CHANNEL[channel].FIFO_CTRL = - ((base->CHANNEL[channel].FIFO_CTRL & (DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK | DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)) | - DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(trig_level) | DMIC_CHANNEL_FIFO_CTRL_ENABLE(enable) | - DMIC_CHANNEL_FIFO_CTRL_RESETN(resetn)); -} - -#if defined(FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC) && FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC -/*! - * brief DMIC channel Decimator reset - * param base : The base address of DMIC interface - * param channelMask : DMIC channel mask, reference _dmic_channel_mask - * param reset : true is reset decimator, false is release decimator. - */ -void DMIC_ResetChannelDecimator(DMIC_Type *base, uint32_t channelMask, bool reset) -{ - uint32_t decReset = 0U; - - if ((channelMask & ((uint32_t)kDMIC_EnableChannel1 | (uint32_t)kDMIC_EnableChannel0)) != 0U) - { - decReset |= 1U; - } -#if defined(FSL_FEATURE_DMIC_CHANNEL_NUM) && (FSL_FEATURE_DMIC_CHANNEL_NUM == 8U) - if ((channelMask & ((uint32_t)kDMIC_EnableChannel3 | (uint32_t)kDMIC_EnableChannel2)) != 0U) - { - decReset |= 2U; - } - - if ((channelMask & ((uint32_t)kDMIC_EnableChannel5 | (uint32_t)kDMIC_EnableChannel4)) != 0U) - { - decReset |= 4U; - } - - if ((channelMask & ((uint32_t)kDMIC_EnableChannel7 | (uint32_t)kDMIC_EnableChannel6)) != 0U) - { - decReset |= 8U; - } -#endif - - if (reset) - { - base->DECRESET |= decReset; - } - else - { - base->DECRESET &= ~decReset; - } -} -#endif - -/*! - * brief Enable callback. - - * This function enables the interrupt for the selected DMIC peripheral. - * The callback function is not enabled until this function is called. - * - * param base Base address of the DMIC peripheral. - * param cb callback Pointer to store callback function. - * retval None. - */ -void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb) -{ - uint32_t instance; - - instance = DMIC_GetInstance(base); - NVIC_ClearPendingIRQ(s_dmicIRQ[instance]); - /* Save callback pointer */ - s_dmicCallback[instance] = cb; - (void)EnableIRQ(s_dmicIRQ[instance]); -} - -/*! - * brief Disable callback. - - * This function disables the interrupt for the selected DMIC peripheral. - * - * param base Base address of the DMIC peripheral. - * param cb callback Pointer to store callback function.. - * retval None. - */ -void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb) -{ - uint32_t instance; - - instance = DMIC_GetInstance(base); - (void)DisableIRQ(s_dmicIRQ[instance]); - s_dmicCallback[instance] = NULL; - NVIC_ClearPendingIRQ(s_dmicIRQ[instance]); -} - -/*! - * brief Enable hwvad callback. - - * This function enables the hwvad interrupt for the selected DMIC peripheral. - * The callback function is not enabled until this function is called. - * - * param base Base address of the DMIC peripheral. - * param vadcb callback Pointer to store callback function. - * retval None. - */ -void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb) -{ - uint32_t instance; - - instance = DMIC_GetInstance(base); - NVIC_ClearPendingIRQ(s_dmicHwvadIRQ[instance]); - /* Save callback pointer */ - s_dmicHwvadCallback[instance] = vadcb; - (void)EnableIRQ(s_dmicHwvadIRQ[instance]); -} - -/*! - * brief Disable callback. - - * This function disables the hwvad interrupt for the selected DMIC peripheral. - * - * param base Base address of the DMIC peripheral. - * param vadcb callback Pointer to store callback function.. - * retval None. - */ -void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb) -{ - uint32_t instance; - - instance = DMIC_GetInstance(base); - (void)DisableIRQ(s_dmicHwvadIRQ[instance]); - s_dmicHwvadCallback[instance] = NULL; - NVIC_ClearPendingIRQ(s_dmicHwvadIRQ[instance]); -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(DMIC0) -/*DMIC0 IRQ handler */ -void DMIC0_DriverIRQHandler(void); -void DMIC0_DriverIRQHandler(void) -{ - if (s_dmicCallback[0] != NULL) - { - s_dmicCallback[0](); - } - SDK_ISR_EXIT_BARRIER; -} -/*DMIC0 HWVAD IRQ handler */ -void HWVAD0_DriverIRQHandler(void); -void HWVAD0_DriverIRQHandler(void) -{ - if (s_dmicHwvadCallback[0] != NULL) - { - s_dmicHwvadCallback[0](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic.h deleted file mode 100644 index 46811c67379..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic.h +++ /dev/null @@ -1,629 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_DMIC_H_ -#define _FSL_DMIC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup dmic_driver - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @name DMIC version - * @{ - */ - -/*! @brief DMIC driver version 2.3.0. */ -#define FSL_DMIC_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) -/*@}*/ - -/*! @brief _dmic_status DMIC transfer status.*/ -enum -{ - kStatus_DMIC_Busy = MAKE_STATUS(kStatusGroup_DMIC, 0), /*!< DMIC is busy */ - kStatus_DMIC_Idle = MAKE_STATUS(kStatusGroup_DMIC, 1), /*!< DMIC is idle */ - kStatus_DMIC_OverRunError = MAKE_STATUS(kStatusGroup_DMIC, 2), /*!< DMIC over run Error */ - kStatus_DMIC_UnderRunError = MAKE_STATUS(kStatusGroup_DMIC, 3), /*!< DMIC under run Error */ -}; - -/*! @brief DMIC different operation modes. */ -typedef enum _operation_mode -{ - kDMIC_OperationModeInterrupt = 1U, /*!< Interrupt mode */ - kDMIC_OperationModeDma = 2U, /*!< DMA mode */ -} operation_mode_t; - -/*! @brief DMIC left/right values. */ -typedef enum _stereo_side -{ - kDMIC_Left = 0U, /*!< Left Stereo channel */ - kDMIC_Right = 1U, /*!< Right Stereo channel */ -} stereo_side_t; - -/*! @brief DMIC Clock pre-divider values. */ -typedef enum -{ - kDMIC_PdmDiv1 = 0U, /*!< DMIC pre-divider set in divide by 1 */ - kDMIC_PdmDiv2 = 1U, /*!< DMIC pre-divider set in divide by 2 */ - kDMIC_PdmDiv3 = 2U, /*!< DMIC pre-divider set in divide by 3 */ - kDMIC_PdmDiv4 = 3U, /*!< DMIC pre-divider set in divide by 4 */ - kDMIC_PdmDiv6 = 4U, /*!< DMIC pre-divider set in divide by 6 */ - kDMIC_PdmDiv8 = 5U, /*!< DMIC pre-divider set in divide by 8 */ - kDMIC_PdmDiv12 = 6U, /*!< DMIC pre-divider set in divide by 12 */ - kDMIC_PdmDiv16 = 7U, /*!< DMIC pre-divider set in divide by 16*/ - kDMIC_PdmDiv24 = 8U, /*!< DMIC pre-divider set in divide by 24*/ - kDMIC_PdmDiv32 = 9U, /*!< DMIC pre-divider set in divide by 32 */ - kDMIC_PdmDiv48 = 10U, /*!< DMIC pre-divider set in divide by 48 */ - kDMIC_PdmDiv64 = 11U, /*!< DMIC pre-divider set in divide by 64*/ - kDMIC_PdmDiv96 = 12U, /*!< DMIC pre-divider set in divide by 96*/ - kDMIC_PdmDiv128 = 13U, /*!< DMIC pre-divider set in divide by 128 */ -} pdm_div_t; - -/*! @brief Pre-emphasis Filter coefficient value for 2FS and 4FS modes. */ -typedef enum _compensation -{ - kDMIC_CompValueZero = 0U, /*!< Compensation 0 */ - kDMIC_CompValueNegativePoint16 = 1U, /*!< Compensation -0.16 */ - kDMIC_CompValueNegativePoint15 = 2U, /*!< Compensation -0.15 */ - kDMIC_CompValueNegativePoint13 = 3U, /*!< Compensation -0.13 */ -} compensation_t; - -/*! @brief DMIC DC filter control values. */ -typedef enum _dc_removal -{ - kDMIC_DcNoRemove = 0U, /*!< Flat response no filter */ - kDMIC_DcCut155 = 1U, /*!< Cut off Frequency is 155 Hz */ - kDMIC_DcCut78 = 2U, /*!< Cut off Frequency is 78 Hz */ - kDMIC_DcCut39 = 3U, /*!< Cut off Frequency is 39 Hz */ -} dc_removal_t; - -#if !(defined(FSL_FEATURE_DMIC_HAS_NO_IOCFG) && FSL_FEATURE_DMIC_HAS_NO_IOCFG) -/*! @brief DMIC IO configiration. */ -typedef enum _dmic_io -{ - kDMIC_PdmDual = 0, /*!< Two separate pairs of PDM wires */ - kDMIC_PdmStereo = 4, /*!< Stereo data0 */ - -#if !(defined(FSL_FEATURE_DMIC_IO_HAS_NO_BYPASS) && (FSL_FEATURE_DMIC_IO_HAS_NO_BYPASS)) - kDMIC_PdmBypass = 3, /*!< Clk Bypass clocks both channels */ - kDMIC_PdmBypassClk0 = 1, /*!< Clk Bypass clocks only channel0 */ - kDMIC_PdmBypassClk1 = 2, /*!< Clk Bypas clocks only channel1 */ -#endif - -#if defined(FSL_FEATURE_DMIC_IO_HAS_STEREO_2_4_6) && (FSL_FEATURE_DMIC_IO_HAS_STEREO_2_4_6) - kDMIC_PdmStereo2 = 8, /*!< Stereo data2 */ - kDMIC_PdmStereo4 = 16, /*!< Stereo data4 */ - kDMIC_PdmStereo6 = 32, /*!< Stereo data6 */ -#endif -} dmic_io_t; -#endif - -/*! @brief DMIC Channel number. */ -typedef enum _dmic_channel -{ - kDMIC_Channel0 = 0U, /*!< DMIC channel 0 */ - kDMIC_Channel1 = 1U, /*!< DMIC channel 1 */ -#if defined(FSL_FEATURE_DMIC_CHANNEL_NUM) && (FSL_FEATURE_DMIC_CHANNEL_NUM == 8U) - kDMIC_Channel2 = 2U, /*!< DMIC channel 2 */ - kDMIC_Channel3 = 3U, /*!< DMIC channel 3 */ - kDMIC_Channel4 = 4U, /*!< DMIC channel 4 */ - kDMIC_Channel5 = 5U, /*!< DMIC channel 5 */ - kDMIC_Channel6 = 6U, /*!< DMIC channel 6 */ - kDMIC_Channel7 = 7U, /*!< DMIC channel 7 */ -#endif -} dmic_channel_t; - -/*! @brief _dmic_channel_mask DMIC Channel mask. */ -enum -{ - kDMIC_EnableChannel0 = 1 << 0U, /*!< DMIC channel 0 mask */ - kDMIC_EnableChannel1 = 1 << 1U, /*!< DMIC channel 1 mask */ -#if defined(FSL_FEATURE_DMIC_CHANNEL_NUM) && (FSL_FEATURE_DMIC_CHANNEL_NUM == 8U) - kDMIC_EnableChannel2 = 1 << 2U, /*!< DMIC channel 2 mask */ - kDMIC_EnableChannel3 = 1 << 3U, /*!< DMIC channel 3 mask */ - kDMIC_EnableChannel4 = 1 << 4U, /*!< DMIC channel 4 mask */ - kDMIC_EnableChannel5 = 1 << 5U, /*!< DMIC channel 5 mask */ - kDMIC_EnableChannel6 = 1 << 6U, /*!< DMIC channel 6 mask */ - kDMIC_EnableChannel7 = 1 << 7U, /*!< DMIC channel 7 mask */ -#endif -}; - -/*! @brief DMIC and decimator sample rates. */ -typedef enum _dmic_phy_sample_rate -{ - kDMIC_PhyFullSpeed = 0U, /*!< Decimator gets one sample per each chosen clock edge of PDM interface */ - kDMIC_PhyHalfSpeed = 1U, /*!< PDM clock to Microphone is halved, decimator receives each sample twice */ -} dmic_phy_sample_rate_t; - -/*! @brief DMIC Channel configuration structure. */ -typedef struct _dmic_channel_config -{ - pdm_div_t divhfclk; /*!< DMIC Clock pre-divider values */ - uint32_t osr; /*!< oversampling rate(CIC decimation rate) for PCM */ - int32_t gainshft; /*!< 4FS PCM data gain control */ - compensation_t preac2coef; /*!< Pre-emphasis Filter coefficient value for 2FS */ - compensation_t preac4coef; /*!< Pre-emphasis Filter coefficient value for 4FS */ - dc_removal_t dc_cut_level; /*!< DMIC DC filter control values. */ - uint32_t post_dc_gain_reduce; /*!< Fine gain adjustment in the form of a number of bits to downshift */ - dmic_phy_sample_rate_t sample_rate; /*!< DMIC and decimator sample rates */ - bool saturate16bit; /*!< Selects 16-bit saturation. 0 means results roll over if out range and do not saturate. - 1 means if the result overflows, it saturates at 0xFFFF for positive overflow and - 0x8000 for negative overflow.*/ -#if defined(FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND) && (FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND) - bool enableSignExtend; /*!< sign extend feature which allows processing of 24bit audio data on 32bit machine */ -#endif -} dmic_channel_config_t; - -/*! @brief DMIC Callback function. */ -typedef void (*dmic_callback_t)(void); - -/*! @brief HWVAD Callback function. */ -typedef void (*dmic_hwvad_callback_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Get the DMIC instance from peripheral base address. - * - * @param base DMIC peripheral base address. - * @return DMIC instance. - */ -uint32_t DMIC_GetInstance(DMIC_Type *base); - -/*! - * @brief Turns DMIC Clock on - * @param base : DMIC base - * @return Nothing - */ -void DMIC_Init(DMIC_Type *base); - -/*! - * @brief Turns DMIC Clock off - * @param base : DMIC base - * @return Nothing - */ -void DMIC_DeInit(DMIC_Type *base); - -#if !(defined(FSL_FEATURE_DMIC_HAS_NO_IOCFG) && FSL_FEATURE_DMIC_HAS_NO_IOCFG) -/*! - * @brief Configure DMIC io - * @deprecated Do not use this function. It has been superceded by @ref DMIC_SetIOCFG - * @param base : The base address of DMIC interface - * @param config : DMIC io configuration - * @return Nothing - */ -void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config); - -/*! - * @brief Stereo PDM select. - * @param base : The base address of DMIC interface - * @param sel : Reference dmic_io_t, can be a single or combination value of dmic_io_t. - * @return Nothing - */ -static inline void DMIC_SetIOCFG(DMIC_Type *base, uint32_t sel) -{ - base->IOCFG = sel; -} -#endif - -/*! - * @brief Set DMIC operating mode - * @deprecated Do not use this function. It has been superceded by - * @ref DMIC_EnableChannelInterrupt, @ref DMIC_EnableChannelDma. - * @param base : The base address of DMIC interface - * @param mode : DMIC mode - * @return Nothing - */ -void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode); - -/*! - * @brief Configure Clock scaling - * @param base : The base address of DMIC interface - * @param use2fs : clock scaling - * @return Nothing - */ -void DMIC_Use2fs(DMIC_Type *base, bool use2fs); - -/*! @} */ - -/*! - * @name Channel configuration - * @{ - */ - -/*! - * @brief Configure DMIC channel - * @param base : The base address of DMIC interface - * @param channel : DMIC channel - * @param dc_cut_level : dc_removal_t, Cut off Frequency - * @param post_dc_gain_reduce : Fine gain adjustment in the form of a number of bits to downshift. - * @param saturate16bit : If selects 16-bit saturation. - */ -void DMIC_CfgChannelDc(DMIC_Type *base, - dmic_channel_t channel, - dc_removal_t dc_cut_level, - uint32_t post_dc_gain_reduce, - bool saturate16bit); - -#if defined(FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND) && (FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND) -/*! - * @brief Enbale channel sign extend which allows processing of 24bit audio data on 32bit machines. - * @param base : The base address of DMIC interface - * @param channel : DMIC channel - * @param enable : true is enable sign extend, false is disable sign extend - */ -static inline void DMIC_EnableChannelSignExtend(DMIC_Type *base, dmic_channel_t channel, bool enable) -{ - if (enable) - { - base->CHANNEL[channel].DC_CTRL |= DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_MASK; - } - else - { - base->CHANNEL[channel].DC_CTRL &= ~DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_MASK; - } -} -#endif - -/*! - * @brief Configure DMIC channel - * - * @param base : The base address of DMIC interface - * @param channel : DMIC channel - * @param side : stereo_side_t, choice of left or right - * @param channel_config : Channel configuration - * @return Nothing - */ -void DMIC_ConfigChannel(DMIC_Type *base, - dmic_channel_t channel, - stereo_side_t side, - dmic_channel_config_t *channel_config); - -/*! - * @brief Enable a particualr channel - * @param base : The base address of DMIC interface - * @param channelmask reference _dmic_channel_mask - * @return Nothing - */ -void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask); - -/*! - * @brief Configure fifo settings for DMIC channel - * @param base : The base address of DMIC interface - * @param channel : DMIC channel - * @param trig_level : FIFO trigger level - * @param enable : FIFO level - * @param resetn : FIFO reset - * @return Nothing - */ -void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn); - -/*! - * @brief Enable a particualr channel interrupt request. - * @param base : The base address of DMIC interface - * @param channel : Channel selection - * @param enable : true is enable, false is disable - */ -static inline void DMIC_EnableChannelInterrupt(DMIC_Type *base, dmic_channel_t channel, bool enable) -{ - if (enable) - { - base->CHANNEL[channel].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK; - } - else - { - base->CHANNEL[channel].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK; - } -} - -/*! - * @brief Enable a particualr channel dma request. - * @param base : The base address of DMIC interface - * @param channel : Channel selection - * @param enable : true is enable, false is disable - */ -static inline void DMIC_EnableChannelDma(DMIC_Type *base, dmic_channel_t channel, bool enable) -{ - if (enable) - { - base->CHANNEL[channel].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK; - } - else - { - base->CHANNEL[channel].FIFO_CTRL &= DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK; - } -} - -/*! - * @brief Enable a particualr channel fifo. - * @param base : The base address of DMIC interface - * @param channel : Channel selection - * @param enable : true is enable, false is disable - */ -static inline void DMIC_EnableChannelFifo(DMIC_Type *base, dmic_channel_t channel, bool enable) -{ - if (enable) - { - base->CHANNEL[channel].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK; - } - else - { - base->CHANNEL[channel].FIFO_CTRL &= DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK; - } -} - -/*! - * @brief Channel fifo reset. - * @param base : The base address of DMIC interface - * @param channel : Channel selection - */ -static inline void DMIC_DoFifoReset(DMIC_Type *base, dmic_channel_t channel) -{ - /* reset FIFO */ - base->CHANNEL[channel].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK; - /* normal operation */ - base->CHANNEL[channel].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK; -} - -/*! - * @brief Get FIFO status - * @param base : The base address of DMIC interface - * @param channel : DMIC channel - * @return FIFO status - */ -static inline uint32_t DMIC_FifoGetStatus(DMIC_Type *base, uint32_t channel) -{ - return base->CHANNEL[channel].FIFO_STATUS; -} - -/*! - * @brief Clear FIFO status - * @param base : The base address of DMIC interface - * @param channel : DMIC channel - * @param mask : Bits to be cleared - * @return FIFO status - */ -static inline void DMIC_FifoClearStatus(DMIC_Type *base, uint32_t channel, uint32_t mask) -{ - base->CHANNEL[channel].FIFO_STATUS = mask; -} - -/*! - * @brief Get FIFO data - * @param base : The base address of DMIC interface - * @param channel : DMIC channel - * @return FIFO data - */ -static inline uint32_t DMIC_FifoGetData(DMIC_Type *base, uint32_t channel) -{ - return base->CHANNEL[channel].FIFO_DATA; -} - -/*! - * @brief Get FIFO address - * @param base : The base address of DMIC interface - * @param channel : DMIC channel - * @return FIFO data - */ -static inline uint32_t DMIC_FifoGetAddress(DMIC_Type *base, uint32_t channel) -{ - return (uint32_t)(&(base->CHANNEL[channel].FIFO_DATA)); -} - -#if defined(FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC) && FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC -/*! - * @brief DMIC channel Decimator reset - * @param base : The base address of DMIC interface - * @param channelMask : DMIC channel mask, reference _dmic_channel_mask - * @param reset : true is reset decimator, false is release decimator. - */ -void DMIC_ResetChannelDecimator(DMIC_Type *base, uint32_t channelMask, bool reset); -#endif - -#if defined(FSL_FEATURE_DMIC_HAS_GLOBAL_SYNC_FUNC) && FSL_FEATURE_DMIC_HAS_GLOBAL_SYNC_FUNC -/*! - * @brief Enable DMIC channel global sync function. - * @param base : The base address of DMIC interface - * @param channelMask : DMIC channel mask, reference _dmic_channel_mask - * @param syncCounter :sync counter will trigger a pulse whenever count reaches CCOUNTVAL. If CCOUNTVAL is set to 0, - * there will be a pulse on every cycle - */ -static inline void DMIC_EnableChannelGlobalSync(DMIC_Type *base, uint32_t channelMask, uint32_t syncCounter) -{ - base->GLOBAL_COUNT_VAL = syncCounter; - base->GLOBAL_SYNC_EN = channelMask; -} - -/*! - * @brief Disbale DMIC channel global sync function. - * @param base : The base address of DMIC interface - * @param channelMask : DMIC channel mask, reference _dmic_channel_mask - */ -static inline void DMIC_DisableChannelGlobalSync(DMIC_Type *base, uint32_t channelMask) -{ - base->GLOBAL_SYNC_EN &= ~channelMask; -} -#endif - -/*! @} */ - -/*! - * @name Register callback. - * @{ - */ - -/*! - * @brief Enable callback. - - * This function enables the interrupt for the selected DMIC peripheral. - * The callback function is not enabled until this function is called. - * - * @param base Base address of the DMIC peripheral. - * @param cb callback Pointer to store callback function. - * @retval None. - */ -void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb); - -/*! - * @brief Disable callback. - - * This function disables the interrupt for the selected DMIC peripheral. - * - * @param base Base address of the DMIC peripheral. - * @param cb callback Pointer to store callback function.. - * @retval None. - */ -void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb); -/*! @} */ - -/*! - * @name HWVAD - * @{ - */ - -/*! - * @brief Sets the gain value for the noise estimator. - * - * @param base DMIC base pointer - * @param value gain value for the noise estimator. - * @retval None. - */ -static inline void DMIC_SetGainNoiseEstHwvad(DMIC_Type *base, uint32_t value) -{ - assert(NULL != base); - base->HWVADTHGN = value & 0xFUL; -} - -/*! - * @brief Sets the gain value for the signal estimator. - * - * @param base DMIC base pointer - * @param value gain value for the signal estimator. - * @retval None. - */ -static inline void DMIC_SetGainSignalEstHwvad(DMIC_Type *base, uint32_t value) -{ - assert(NULL != base); - base->HWVADTHGS = value & 0xFUL; -} - -/*! - * @brief Sets the hwvad filter cutoff frequency parameter. - * - * @param base DMIC base pointer - * @param value cut off frequency value. - * @retval None. - */ -static inline void DMIC_SetFilterCtrlHwvad(DMIC_Type *base, uint32_t value) -{ - assert(NULL != base); - base->HWVADHPFS = value & 0x3UL; -} - -/*! - * @brief Sets the input gain of hwvad. - * - * @param base DMIC base pointer - * @param value input gain value for hwvad. - * @retval None. - */ -static inline void DMIC_SetInputGainHwvad(DMIC_Type *base, uint32_t value) -{ - assert(NULL != base); - base->HWVADGAIN = value & 0xFUL; -} - -/*! - * @brief Clears hwvad internal interrupt flag. - * - * @param base DMIC base pointer - * @param st10 bit value. - * @retval None. - */ -static inline void DMIC_CtrlClrIntrHwvad(DMIC_Type *base, bool st10) -{ - assert(NULL != base); - base->HWVADST10 = (st10) ? 0x1UL : 0x0UL; -} - -/*! - * @brief Resets hwvad filters. - * - * @param base DMIC base pointer - * @param rstt Reset bit value. - * @retval None. - */ -static inline void DMIC_FilterResetHwvad(DMIC_Type *base, bool rstt) -{ - assert(NULL != base); - base->HWVADRSTT = (rstt) ? 0x1UL : 0x0UL; -} - -/*! - * @brief Gets the value from output of the filter z7. - * - * @param base DMIC base pointer - * @retval output of filter z7. - */ -static inline uint16_t DMIC_GetNoiseEnvlpEst(DMIC_Type *base) -{ - assert(NULL != base); - return (uint16_t)(base->HWVADLOWZ & 0xFFFFU); -} - -/*! - * @brief Enable hwvad callback. - - * This function enables the hwvad interrupt for the selected DMIC peripheral. - * The callback function is not enabled until this function is called. - * - * @param base Base address of the DMIC peripheral. - * @param vadcb callback Pointer to store callback function. - * @retval None. - */ -void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb); - -/*! - * @brief Disable callback. - - * This function disables the hwvad interrupt for the selected DMIC peripheral. - * - * @param base Base address of the DMIC peripheral. - * @param vadcb callback Pointer to store callback function.. - * @retval None. - */ -void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb); - -/*! @} */ - -#ifdef __cplusplus -} -#endif - -/*! @}*/ - -#endif /* __FSL_DMIC_H */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic_dma.c deleted file mode 100644 index 72dbfa6dbaa..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic_dma.c +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_dmic_dma.h" -#include "fsl_dmic.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.dmic_dma" -#endif - -/*! @brief _dmic_dma_states_t DMIC transfer state, which is used for DMIC transactiaonl APIs' internal state. */ -enum -{ - kDMIC_Idle = 0x0, /*!< DMIC is idle state */ - kDMIC_Busy /*!< DMIC is busy tranferring data. */ -}; -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ********************************************************************************/ - -static void DMIC_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode) -{ - assert(handle != NULL); - assert(param != NULL); - - dmic_dma_handle_t *dmicHandle = (dmic_dma_handle_t *)param; - - /* if no link transfer, dmic status set to IDLE. */ - if (dmicHandle->desLink == NULL) - { - dmicHandle->state = kDMIC_Idle; - } - - if (dmicHandle->callback != NULL) - { - dmicHandle->callback(dmicHandle->base, dmicHandle, kStatus_DMIC_Idle, dmicHandle->userData); - } -} - -/*! - * brief Install DMA descriptor memory. - * - * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong - * transfer which will request more than one DMA descriptor memory space. - * User should be take care about the address of DMA descriptor pool which required align with 512BYTE. - * - * param handle Pointer to DMA channel transfer handle. - * param linkAddr DMA link descriptor address. - * param num DMA link descriptor number. - */ -void DMIC_InstallDMADescriptorMemory(dmic_dma_handle_t *handle, void *linkAddr, size_t linkNum) -{ - assert(handle != NULL); - - handle->desLink = (dma_descriptor_t *)linkAddr; - handle->linkNum = linkNum; -} - -/*! - * brief Initializes the DMIC handle which is used in transactional functions. - * param base DMIC peripheral base address. - * param handle Pointer to dmic_dma_handle_t structure. - * param callback Callback function. - * param userData User data. - * param rxDmaHandle User-requested DMA handle for RX DMA transfer. - */ -status_t DMIC_TransferCreateHandleDMA(DMIC_Type *base, - dmic_dma_handle_t *handle, - dmic_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *rxDmaHandle) -{ - assert(NULL != base); - assert(NULL != handle); - assert(NULL != rxDmaHandle); - - (void)memset(handle, 0, sizeof(*handle)); - - handle->callback = callback; - handle->userData = userData; - handle->rxDmaHandle = rxDmaHandle; - - /* Set DMIC state to idle */ - handle->state = kDMIC_Idle; - /* register callback. */ - DMA_SetCallback(rxDmaHandle, DMIC_TransferReceiveDMACallback, handle); - - return kStatus_Success; -} - -/*! - * brief Receives data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * param base USART peripheral base address. - * param handle Pointer to usart_dma_handle_t structure. - * param xfer DMIC DMA transfer structure. See #dmic_transfer_t. - * param dmic_channel DMIC start channel number - * retval kStatus_Success - */ -status_t DMIC_TransferReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle, dmic_transfer_t *xfer, uint32_t channel) -{ - assert(handle != NULL); - assert(handle->rxDmaHandle != NULL); - assert(xfer != NULL); - - dma_channel_config_t transferConfig = {0U}; - uint32_t srcAddr = (uint32_t)&base->CHANNEL[channel].FIFO_DATA; - uint32_t desNum = 0U; - dma_descriptor_t *linkDesc = (handle->desLink != NULL) ? &(handle->desLink[desNum + 1U]) : NULL; - dmic_transfer_t *currentTransfer = xfer->linkTransfer; - bool loopEnd = false, intA = true; - uint32_t interleaveWidth = kDMA_AddressInterleave0xWidth; - - if ((xfer->linkTransfer != NULL) && (handle->desLink == NULL)) - { - return kStatus_InvalidArgument; - } - - if (handle->state == (uint8_t)kDMIC_Busy) - { - return kStatus_DMIC_Busy; - } - - while (currentTransfer != NULL) - { - /* set up linked descriptor */ - DMA_SetupDescriptor(&handle->desLink[desNum], - DMA_CHANNEL_XFER(currentTransfer->linkTransfer != NULL ? 1UL : 0UL, 0UL, intA, !intA, - currentTransfer->dataWidth, interleaveWidth, - currentTransfer->dataAddrInterleaveSize, currentTransfer->dataSize), - (uint32_t *)srcAddr, currentTransfer->data, linkDesc); - - intA = intA == true ? false : true; - /* break for wrap transfer */ - if (loopEnd) - { - break; - } - - if (++desNum == handle->linkNum) - { - return kStatus_Fail; - } - - linkDesc = &handle->desLink[desNum + 1U]; - - currentTransfer = currentTransfer->linkTransfer; - /* if current transfer need wrap, then create one more descriptor, since the first descriptor cannot be used - * anymore, this is - * the limitation of the DMA module - */ - if (currentTransfer == xfer) - { - linkDesc = handle->desLink; /* point to the first one */ - loopEnd = true; - continue; - } - } - /* transferSize make sense to non link transfer only */ - handle->transferSize += xfer->dataSize; - - /* code to keep compatibility for the case that not use link transfer */ - if ((xfer->dataWidth != (uint8_t)kDMA_Transfer16BitWidth) && (xfer->dataWidth != (uint8_t)kDMA_Transfer32BitWidth)) - { - xfer->dataWidth = kDMA_Transfer16BitWidth; /* use 16bit width as default value */ - } - /* code to keep compatibility for the case that not use link transfer*/ - if ((xfer->dataAddrInterleaveSize == (uint8_t)kDMA_AddressInterleave0xWidth) || - (xfer->dataAddrInterleaveSize > (uint8_t)kDMA_AddressInterleave4xWidth)) - { - xfer->dataAddrInterleaveSize = kDMA_AddressInterleave1xWidth; /* use interleave1Xwidth as default value. */ - } - - /* prepare channel tranfer */ - DMA_PrepareChannelTransfer( - &transferConfig, (uint32_t *)srcAddr, xfer->data, - DMA_CHANNEL_XFER(xfer->linkTransfer == NULL ? 0UL : 1UL, 0UL, intA, !intA, xfer->dataWidth, interleaveWidth, - xfer->dataAddrInterleaveSize, xfer->dataSize), - kDMA_PeripheralToMemory, NULL, handle->desLink); - /* Submit transfer. */ - if (DMA_SubmitChannelTransfer(handle->rxDmaHandle, &transferConfig) == kStatus_DMA_Busy) - { - return kStatus_DMIC_Busy; - } - - /* enable channel */ - DMIC_EnableChannnel(DMIC0, 1UL << channel); - /* enable dmic channel dma request */ - DMIC_EnableChannelDma(DMIC0, (dmic_channel_t)channel, true); - - /* start transfer */ - DMA_StartTransfer(handle->rxDmaHandle); - - handle->state = kDMIC_Busy; - - return kStatus_Success; -} - -/*! - * brief Aborts the received data using DMA. - * - * This function aborts the received data using DMA. - * - * param base DMIC peripheral base address - * param handle Pointer to dmic_dma_handle_t structure - */ -void DMIC_TransferAbortReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle) -{ - assert(NULL != handle); - assert(NULL != handle->rxDmaHandle); - - /* Stop transfer. */ - DMA_AbortTransfer(handle->rxDmaHandle); - handle->state = kDMIC_Idle; -} - -/*! - * brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * Note: Do not trying to use this api to get the number of received bytes, it make no sense to link transfer. - * param base DMIC peripheral base address. - * param handle DMIC handle pointer. - * param count Receive bytes count. - * retval kStatus_NoTransferInProgress No receive in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter count; - */ -status_t DMIC_TransferGetReceiveCountDMA(DMIC_Type *base, dmic_dma_handle_t *handle, uint32_t *count) -{ - assert(handle != NULL); - assert(handle->rxDmaHandle != NULL); - assert(count != NULL); - - if ((uint8_t)kDMIC_Idle == handle->state) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->transferSize - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); - - return kStatus_Success; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic_dma.h deleted file mode 100644 index 40c05bac16d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic_dma.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_DMIC_DMA_H_ -#define _FSL_DMIC_DMA_H_ - -#include "fsl_common.h" -#include "fsl_dma.h" - -/*! - * @addtogroup dmic_dma_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @name DMIC DMA version - * @{ - */ - -/*! @brief DMIC DMA driver version 2.3.0 */ -#define FSL_DMIC_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) -/*@}*/ - -/*! @brief DMIC transfer structure. */ -typedef struct _dmic_transfer -{ - void *data; /*!< The buffer of data to be transfer.*/ - uint8_t dataWidth; /*!< DMIC support 16bit/32bit */ - size_t dataSize; /*!< The byte count to be transfer. */ - uint8_t dataAddrInterleaveSize; /*!< destination address interleave size */ - - struct _dmic_transfer *linkTransfer; /*!< use to support link transfer */ -} dmic_transfer_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _dmic_dma_handle dmic_dma_handle_t; - -/*! @brief DMIC transfer callback function. */ -typedef void (*dmic_dma_transfer_callback_t)(DMIC_Type *base, - dmic_dma_handle_t *handle, - status_t status, - void *userData); - -/*! - * @brief DMIC DMA handle - */ -struct _dmic_dma_handle -{ - DMIC_Type *base; /*!< DMIC peripheral base address. */ - dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ - dmic_dma_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< DMIC callback function parameter.*/ - size_t transferSize; /*!< Size of the data to receive. */ - volatile uint8_t state; /*!< Internal state of DMIC DMA transfer */ - - dma_descriptor_t *desLink; /*!< descriptor pool pointer */ - size_t linkNum; /*!< number of descriptor in descriptors pool */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name DMA transactional - * @{ - */ - -/*! - * @brief Initializes the DMIC handle which is used in transactional functions. - * @param base DMIC peripheral base address. - * @param handle Pointer to dmic_dma_handle_t structure. - * @param callback Callback function. - * @param userData User data. - * @param rxDmaHandle User-requested DMA handle for RX DMA transfer. - */ -status_t DMIC_TransferCreateHandleDMA(DMIC_Type *base, - dmic_dma_handle_t *handle, - dmic_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *rxDmaHandle); - -/*! - * @brief Receives data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * @param base USART peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param xfer DMIC DMA transfer structure. See #dmic_transfer_t. - * @param channel DMIC start channel number. - * @retval kStatus_Success - */ -status_t DMIC_TransferReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle, dmic_transfer_t *xfer, uint32_t channel); - -/*! - * @brief Aborts the received data using DMA. - * - * This function aborts the received data using DMA. - * - * @param base DMIC peripheral base address - * @param handle Pointer to dmic_dma_handle_t structure - */ -void DMIC_TransferAbortReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base DMIC peripheral base address. - * @param handle DMIC handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter count; - */ -status_t DMIC_TransferGetReceiveCountDMA(DMIC_Type *base, dmic_dma_handle_t *handle, uint32_t *count); - -/*! - * @brief Install DMA descriptor memory. - * - * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong - * transfer which will request more than one DMA descriptor memory space, it should be called after - * DMIC_TransferCreateHandleDMA. - * User should be take care about the address of DMA descriptor pool which required align with 16BYTE at least. - * - * @param handle Pointer to DMA channel transfer handle. - * @param linkAddr DMA link descriptor address. - * @param linkNum DMA link descriptor number. - */ -void DMIC_InstallDMADescriptorMemory(dmic_dma_handle_t *handle, void *linkAddr, size_t linkNum); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_DMIC_DMA_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_enc.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_enc.c deleted file mode 100644 index 8117df13320..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_enc.c +++ /dev/null @@ -1,593 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_enc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.enc" -#endif - -#define ENC_CTRL_W1C_FLAGS (ENC_CTRL_HIRQ_MASK | ENC_CTRL_XIRQ_MASK | ENC_CTRL_DIRQ_MASK | ENC_CTRL_CMPIRQ_MASK) -#define ENC_CTRL2_W1C_FLAGS (ENC_CTRL2_SABIRQ_MASK | ENC_CTRL2_ROIRQ_MASK | ENC_CTRL2_RUIRQ_MASK) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for ENC module. - * - * @param base ENC peripheral base address - */ -static uint32_t ENC_GetInstance(ENC_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to ENC bases for each instance. */ -static ENC_Type *const s_encBases[] = ENC_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to ENC clocks for each instance. */ -static const clock_ip_name_t s_encClocks[] = ENC_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t ENC_GetInstance(ENC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_encBases); instance++) - { - if (s_encBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_encBases)); - - return instance; -} - -/*! - * brief Initialization for the ENC module. - * - * This function is to make the initialization for the ENC module. It should be called firstly before any operation to - * the ENC with the operations like: - * - Enable the clock for ENC module. - * - Configure the ENC's working attributes. - * - * param base ENC peripheral base address. - * param config Pointer to configuration structure. See to "enc_config_t". - */ -void ENC_Init(ENC_Type *base, const enc_config_t *config) -{ - assert(NULL != config); - - uint16_t tmp16; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(s_encClocks[ENC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* ENC_CTRL. */ - tmp16 = base->CTRL & (uint16_t)(~(ENC_CTRL_W1C_FLAGS | ENC_CTRL_HIP_MASK | ENC_CTRL_HNE_MASK | ENC_CTRL_REV_MASK | - ENC_CTRL_PH1_MASK | ENC_CTRL_XIP_MASK | ENC_CTRL_XNE_MASK | ENC_CTRL_WDE_MASK)); - /* For HOME trigger. */ - if (kENC_HOMETriggerDisabled != config->HOMETriggerMode) - { - tmp16 |= ENC_CTRL_HIP_MASK; - if (kENC_HOMETriggerOnFallingEdge == config->HOMETriggerMode) - { - tmp16 |= ENC_CTRL_HNE_MASK; - } - } - /* For encoder work mode. */ - if (config->enableReverseDirection) - { - tmp16 |= ENC_CTRL_REV_MASK; - } - if (kENC_DecoderWorkAsSignalPhaseCountMode == config->decoderWorkMode) - { - tmp16 |= ENC_CTRL_PH1_MASK; - } - /* For INDEX trigger. */ - if (kENC_INDEXTriggerDisabled != config->INDEXTriggerMode) - { - tmp16 |= ENC_CTRL_XIP_MASK; - if (kENC_INDEXTriggerOnFallingEdge == config->INDEXTriggerMode) - { - tmp16 |= ENC_CTRL_XNE_MASK; - } - } - /* Watchdog. */ - if (config->enableWatchdog) - { - tmp16 |= ENC_CTRL_WDE_MASK; - base->WTR = config->watchdogTimeoutValue; /* WDOG can be only available when the feature is enabled. */ - } - base->CTRL = tmp16; - - /* ENC_FILT. */ - base->FILT = ENC_FILT_FILT_CNT(config->filterCount) | ENC_FILT_FILT_PER(config->filterSamplePeriod); - - /* ENC_CTRL2. */ - tmp16 = base->CTRL2 & (uint16_t)(~(ENC_CTRL2_W1C_FLAGS | ENC_CTRL2_OUTCTL_MASK | ENC_CTRL2_REVMOD_MASK | - ENC_CTRL2_MOD_MASK | ENC_CTRL2_UPDPOS_MASK | ENC_CTRL2_UPDHLD_MASK)); - if (kENC_POSMATCHOnReadingAnyPositionCounter == config->positionMatchMode) - { - tmp16 |= ENC_CTRL2_OUTCTL_MASK; - } - if (kENC_RevolutionCountOnRollOverModulus == config->revolutionCountCondition) - { - tmp16 |= ENC_CTRL2_REVMOD_MASK; - } - if (config->enableModuloCountMode) - { - tmp16 |= ENC_CTRL2_MOD_MASK; - /* Set modulus value. */ - base->UMOD = (uint16_t)(config->positionModulusValue >> 16U); /* Upper 16 bits. */ - base->LMOD = (uint16_t)(config->positionModulusValue); /* Lower 16 bits. */ - } - if (config->enableTRIGGERClearPositionCounter) - { - tmp16 |= ENC_CTRL2_UPDPOS_MASK; - } - if (config->enableTRIGGERClearHoldPositionCounter) - { - tmp16 |= ENC_CTRL2_UPDHLD_MASK; - } - base->CTRL2 = tmp16; - - /* ENC_UCOMP & ENC_LCOMP. */ - base->UCOMP = (uint16_t)(config->positionCompareValue >> 16U); /* Upper 16 bits. */ - base->LCOMP = (uint16_t)(config->positionCompareValue); /* Lower 16 bits. */ - - /* ENC_UINIT & ENC_LINIT. */ - base->UINIT = (uint16_t)(config->positionInitialValue >> 16U); /* Upper 16 bits. */ - base->LINIT = (uint16_t)(config->positionInitialValue); /* Lower 16 bits. */ -} - -/*! - * brief De-initialization for the ENC module. - * - * This function is to make the de-initialization for the ENC module. It could be called when ENC is no longer used with - * the operations like: - * - Disable the clock for ENC module. - * - * param base ENC peripheral base address. - */ -void ENC_Deinit(ENC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(s_encClocks[ENC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Get an available pre-defined settings for ENC's configuration. - * - * This function initializes the ENC configuration structure with an available settings, the default value are: - * code - * config->enableReverseDirection = false; - * config->decoderWorkMode = kENC_DecoderWorkAsNormalMode; - * config->HOMETriggerMode = kENC_HOMETriggerDisabled; - * config->INDEXTriggerMode = kENC_INDEXTriggerDisabled; - * config->enableTRIGGERClearPositionCounter = false; - * config->enableTRIGGERClearHoldPositionCounter = false; - * config->enableWatchdog = false; - * config->watchdogTimeoutValue = 0U; - * config->filterCount = 0U; - * config->filterSamplePeriod = 0U; - * config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue; - * config->positionCompareValue = 0xFFFFFFFFU; - * config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse; - * config->enableModuloCountMode = false; - * config->positionModulusValue = 0U; - * config->positionInitialValue = 0U; - * endcode - * param config Pointer to a variable of configuration structure. See to "enc_config_t". - */ -void ENC_GetDefaultConfig(enc_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enableReverseDirection = false; - config->decoderWorkMode = kENC_DecoderWorkAsNormalMode; - config->HOMETriggerMode = kENC_HOMETriggerDisabled; - config->INDEXTriggerMode = kENC_INDEXTriggerDisabled; - config->enableTRIGGERClearPositionCounter = false; - config->enableTRIGGERClearHoldPositionCounter = false; - config->enableWatchdog = false; - config->watchdogTimeoutValue = 0U; - config->filterCount = 0U; - config->filterSamplePeriod = 0U; - config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue; - config->positionCompareValue = 0xFFFFFFFFU; - config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse; - config->enableModuloCountMode = false; - config->positionModulusValue = 0U; - config->positionInitialValue = 0U; -} - -/*! - * brief Load the initial position value to position counter. - * - * This function is to transfer the initial position value (UINIT and LINIT) contents to position counter (UPOS and - * LPOS), so that to provide the consistent operation the position counter registers. - * - * param base ENC peripheral base address. - */ -void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base) -{ - uint16_t tmp16 = base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS); - - tmp16 |= ENC_CTRL_SWIP_MASK; /* Write 1 to trigger the command for loading initial position value. */ - base->CTRL = tmp16; -} - -/*! - * brief Enable and configure the self test function. - * - * This function is to enable and configuration the self test function. It controls and sets the frequency of a - * quadrature signal generator. It provides a quadrature test signal to the inputs of the quadrature decoder module. - * It is a factory test feature; however, it may be useful to customers' software development and testing. - * - * param base ENC peripheral base address. - * param config Pointer to configuration structure. See to "enc_self_test_config_t". Pass "NULL" to disable. - */ -void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config) -{ - uint16_t tmp16 = 0U; - - if (NULL == config) /* Pass "NULL" to disable the feature. */ - { - tmp16 = 0U; - } - else - { - tmp16 = ENC_TST_TEN_MASK | ENC_TST_TCE_MASK | ENC_TST_TEST_PERIOD(config->signalPeriod) | - ENC_TST_TEST_COUNT(config->signalCount); - if (kENC_SelfTestDirectionNegative == config->signalDirection) - { - tmp16 |= ENC_TST_QDN_MASK; - } - } - - base->TST = tmp16; -} - -/*! - * brief Enable watchdog for ENC module. - * - * param base ENC peripheral base address - * param enable Enables or disables the watchdog - */ -void ENC_EnableWatchdog(ENC_Type *base, bool enable) -{ - uint16_t tmp16 = base->CTRL & (uint16_t)(~(ENC_CTRL_W1C_FLAGS | ENC_CTRL_WDE_MASK)); - - if (enable) - { - tmp16 |= ENC_CTRL_WDE_MASK; - } - base->CTRL = tmp16; -} - -/*! - * brief Get the status flags. - * - * param base ENC peripheral base address. - * - * return Mask value of status flags. For available mask, see to "_enc_status_flags". - */ -uint32_t ENC_GetStatusFlags(ENC_Type *base) -{ - uint32_t ret32 = 0U; - - /* ENC_CTRL. */ - if (0U != (ENC_CTRL_HIRQ_MASK & base->CTRL)) - { - ret32 |= (uint32_t)kENC_HOMETransitionFlag; - } - if (0U != (ENC_CTRL_XIRQ_MASK & base->CTRL)) - { - ret32 |= (uint32_t)kENC_INDEXPulseFlag; - } - if (0U != (ENC_CTRL_DIRQ_MASK & base->CTRL)) - { - ret32 |= (uint32_t)kENC_WatchdogTimeoutFlag; - } - if (0U != (ENC_CTRL_CMPIRQ_MASK & base->CTRL)) - { - ret32 |= (uint32_t)kENC_PositionCompareFlag; - } - - /* ENC_CTRL2. */ - if (0U != (ENC_CTRL2_SABIRQ_MASK & base->CTRL2)) - { - ret32 |= (uint32_t)kENC_SimultBothPhaseChangeFlag; - } - if (0U != (ENC_CTRL2_ROIRQ_MASK & base->CTRL2)) - { - ret32 |= (uint32_t)kENC_PositionRollOverFlag; - } - if (0U != (ENC_CTRL2_RUIRQ_MASK & base->CTRL2)) - { - ret32 |= (uint32_t)kENC_PositionRollUnderFlag; - } - if (0U != (ENC_CTRL2_DIR_MASK & base->CTRL2)) - { - ret32 |= (uint32_t)kENC_LastCountDirectionFlag; - } - - return ret32; -} - -/*! - * brief Clear the status flags. - * - * param base ENC peripheral base address. - * param mask Mask value of status flags to be cleared. For available mask, see to "_enc_status_flags". - */ -void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask) -{ - uint32_t tmp16 = 0U; - - /* ENC_CTRL. */ - if (0U != ((uint32_t)kENC_HOMETransitionFlag & mask)) - { - tmp16 |= ENC_CTRL_HIRQ_MASK; - } - if (0U != ((uint32_t)kENC_INDEXPulseFlag & mask)) - { - tmp16 |= ENC_CTRL_XIRQ_MASK; - } - if (0U != ((uint32_t)kENC_WatchdogTimeoutFlag & mask)) - { - tmp16 |= ENC_CTRL_DIRQ_MASK; - } - if (0U != ((uint32_t)kENC_PositionCompareFlag & mask)) - { - tmp16 |= ENC_CTRL_CMPIRQ_MASK; - } - if (0U != tmp16) - { - base->CTRL = (uint16_t)(((uint32_t)base->CTRL & (~ENC_CTRL_W1C_FLAGS)) | tmp16); - } - - /* ENC_CTRL2. */ - tmp16 = 0U; - if (0U != ((uint32_t)kENC_SimultBothPhaseChangeFlag & mask)) - { - tmp16 |= ENC_CTRL2_SABIRQ_MASK; - } - if (0U != ((uint32_t)kENC_PositionRollOverFlag & mask)) - { - tmp16 |= ENC_CTRL2_ROIRQ_MASK; - } - if (0U != ((uint32_t)kENC_PositionRollUnderFlag & mask)) - { - tmp16 |= ENC_CTRL2_RUIRQ_MASK; - } - if (0U != tmp16) - { - base->CTRL2 = (uint16_t)(((uint32_t)base->CTRL2 & (~ENC_CTRL2_W1C_FLAGS)) | tmp16); - } -} - -/*! - * brief Enable the interrupts. - * - * param base ENC peripheral base address. - * param mask Mask value of interrupts to be enabled. For available mask, see to "_enc_interrupt_enable". - */ -void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask) -{ - uint32_t tmp16 = 0U; - - /* ENC_CTRL. */ - if (0U != ((uint32_t)kENC_HOMETransitionInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL_HIE_MASK; - } - if (0U != ((uint32_t)kENC_INDEXPulseInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL_XIE_MASK; - } - if (0U != ((uint32_t)kENC_WatchdogTimeoutInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL_DIE_MASK; - } - if (0U != ((uint32_t)kENC_PositionCompareInerruptEnable & mask)) - { - tmp16 |= ENC_CTRL_CMPIE_MASK; - } - if (tmp16 != 0U) - { - base->CTRL = (uint16_t)(((uint32_t)base->CTRL & (~ENC_CTRL_W1C_FLAGS)) | tmp16); - } - /* ENC_CTRL2. */ - tmp16 = 0U; - if (0U != ((uint32_t)kENC_SimultBothPhaseChangeInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL2_SABIE_MASK; - } - if (0U != ((uint32_t)kENC_PositionRollOverInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL2_ROIE_MASK; - } - if (0U != ((uint32_t)kENC_PositionRollUnderInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL2_RUIE_MASK; - } - if (tmp16 != 0U) - { - base->CTRL2 = (uint16_t)(((uint32_t)base->CTRL2 & (~ENC_CTRL2_W1C_FLAGS)) | tmp16); - } -} - -/*! - * brief Disable the interrupts. - * - * param base ENC peripheral base address. - * param mask Mask value of interrupts to be disabled. For available mask, see to "_enc_interrupt_enable". - */ -void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask) -{ - uint16_t tmp16 = 0U; - - /* ENC_CTRL. */ - if (0U != ((uint32_t)kENC_HOMETransitionInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL_HIE_MASK; - } - if (0U != ((uint32_t)kENC_INDEXPulseInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL_XIE_MASK; - } - if (0U != ((uint32_t)kENC_WatchdogTimeoutInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL_DIE_MASK; - } - if (0U != ((uint32_t)kENC_PositionCompareInerruptEnable & mask)) - { - tmp16 |= ENC_CTRL_CMPIE_MASK; - } - if (0U != tmp16) - { - base->CTRL = (uint16_t)(base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS)) & (uint16_t)(~tmp16); - } - /* ENC_CTRL2. */ - tmp16 = 0U; - if (0U != ((uint32_t)kENC_SimultBothPhaseChangeInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL2_SABIE_MASK; - } - if (0U != ((uint32_t)kENC_PositionRollOverInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL2_ROIE_MASK; - } - if (0U != ((uint32_t)kENC_PositionRollUnderInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL2_RUIE_MASK; - } - if (tmp16 != 0U) - { - base->CTRL2 = (uint16_t)(base->CTRL2 & (uint16_t)(~ENC_CTRL2_W1C_FLAGS)) & (uint16_t)(~tmp16); - } -} - -/*! - * brief Get the enabled interrupts' flags. - * - * param base ENC peripheral base address. - * - * return Mask value of enabled interrupts. - */ -uint32_t ENC_GetEnabledInterrupts(ENC_Type *base) -{ - uint32_t ret32 = 0U; - - /* ENC_CTRL. */ - if (0U != (ENC_CTRL_HIE_MASK & base->CTRL)) - { - ret32 |= (uint32_t)kENC_HOMETransitionInterruptEnable; - } - if (0U != (ENC_CTRL_XIE_MASK & base->CTRL)) - { - ret32 |= (uint32_t)kENC_INDEXPulseInterruptEnable; - } - if (0U != (ENC_CTRL_DIE_MASK & base->CTRL)) - { - ret32 |= (uint32_t)kENC_WatchdogTimeoutInterruptEnable; - } - if (0U != (ENC_CTRL_CMPIE_MASK & base->CTRL)) - { - ret32 |= (uint32_t)kENC_PositionCompareInerruptEnable; - } - /* ENC_CTRL2. */ - if (0U != (ENC_CTRL2_SABIE_MASK & base->CTRL2)) - { - ret32 |= (uint32_t)kENC_SimultBothPhaseChangeInterruptEnable; - } - if (0U != (ENC_CTRL2_ROIE_MASK & base->CTRL2)) - { - ret32 |= (uint32_t)kENC_PositionRollOverInterruptEnable; - } - if (0U != (ENC_CTRL2_RUIE_MASK & base->CTRL2)) - { - ret32 |= (uint32_t)kENC_PositionRollUnderInterruptEnable; - } - return ret32; -} - -/*! - * brief Set initial position value for ENC module. - * - * param base ENC peripheral base address - * param value Positive initial value - */ -void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value) -{ - base->UINIT = (uint16_t)(value >> 16U); /* Set upper 16 bits. */ - base->LINIT = (uint16_t)(value); /* Set lower 16 bits. */ -} - -/*! - * brief Get the current position counter's value. - * - * param base ENC peripheral base address. - * - * return Current position counter's value. - */ -uint32_t ENC_GetPositionValue(ENC_Type *base) -{ - uint32_t ret32; - - ret32 = base->UPOS; /* Get upper 16 bits and make a snapshot. */ - ret32 <<= 16U; - ret32 |= base->LPOSH; /* Get lower 16 bits from hold register. */ - - return ret32; -} - -/*! - * brief Get the hold position counter's value. - * - * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold - * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to - * be attained. - * - * param base ENC peripheral base address. - * - * return Hold position counter's value. - */ -uint32_t ENC_GetHoldPositionValue(ENC_Type *base) -{ - uint32_t ret32; - - ret32 = base->UPOSH; /* Get upper 16 bits and make a snapshot. */ - ret32 <<= 16U; - ret32 |= base->LPOSH; /* Get lower 16 bits from hold register. */ - - return ret32; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_enc.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_enc.h deleted file mode 100644 index 07c49307b00..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_enc.h +++ /dev/null @@ -1,458 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_ENC_H_ -#define _FSL_ENC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup enc - * @{ - */ -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define FSL_ENC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) - -/*! - * @brief Interrupt enable/disable mask. - */ -enum _enc_interrupt_enable -{ - kENC_HOMETransitionInterruptEnable = (1U << 0U), /*!< HOME interrupt enable. */ - kENC_INDEXPulseInterruptEnable = (1U << 1U), /*!< INDEX pulse interrupt enable. */ - kENC_WatchdogTimeoutInterruptEnable = (1U << 2U), /*!< Watchdog timeout interrupt enable. */ - kENC_PositionCompareInerruptEnable = (1U << 3U), /*!< Position compare interrupt enable. */ - kENC_SimultBothPhaseChangeInterruptEnable = - (1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt enable. */ - kENC_PositionRollOverInterruptEnable = (1U << 5U), /*!< Roll-over interrupt enable. */ - kENC_PositionRollUnderInterruptEnable = (1U << 6U), /*!< Roll-under interrupt enable. */ -}; - -/*! - * @brief Status flag mask. - * - * These flags indicate the counter's events. - */ -enum _enc_status_flags -{ - kENC_HOMETransitionFlag = (1U << 0U), /*!< HOME signal transition interrupt request. */ - kENC_INDEXPulseFlag = (1U << 1U), /*!< INDEX Pulse Interrupt Request. */ - kENC_WatchdogTimeoutFlag = (1U << 2U), /*!< Watchdog timeout interrupt request. */ - kENC_PositionCompareFlag = (1U << 3U), /*!< Position compare interrupt request. */ - kENC_SimultBothPhaseChangeFlag = (1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt request. */ - kENC_PositionRollOverFlag = (1U << 5U), /*!< Roll-over interrupt request. */ - kENC_PositionRollUnderFlag = (1U << 6U), /*!< Roll-under interrupt request. */ - kENC_LastCountDirectionFlag = (1U << 7U), /*!< Last count was in the up direction, or the down direction. */ -}; - -/*! - * @brief Signal status flag mask. - * - * These flags indicate the counter's signal. - */ -enum _enc_signal_status_flags -{ - kENC_RawHOMEStatusFlag = ENC_IMR_HOME_MASK, /*!< Raw HOME input. */ - kENC_RawINDEXStatusFlag = ENC_IMR_INDEX_MASK, /*!< Raw INDEX input. */ - kENC_RawPHBStatusFlag = ENC_IMR_PHB_MASK, /*!< Raw PHASEB input. */ - kENC_RawPHAEXStatusFlag = ENC_IMR_PHA_MASK, /*!< Raw PHASEA input. */ - kENC_FilteredHOMEStatusFlag = ENC_IMR_FHOM_MASK, /*!< The filtered version of HOME input. */ - kENC_FilteredINDEXStatusFlag = ENC_IMR_FIND_MASK, /*!< The filtered version of INDEX input. */ - kENC_FilteredPHBStatusFlag = ENC_IMR_FPHB_MASK, /*!< The filtered version of PHASEB input. */ - kENC_FilteredPHAStatusFlag = ENC_IMR_FPHA_MASK, /*!< The filtered version of PHASEA input. */ -}; - -/*! - * @brief Define HOME signal's trigger mode. - * - * The ENC would count the trigger from HOME signal line. - */ -typedef enum _enc_home_trigger_mode -{ - kENC_HOMETriggerDisabled = 0U, /*!< HOME signal's trigger is disabled. */ - kENC_HOMETriggerOnRisingEdge, /*!< Use positive going edge-to-trigger initialization of position counters. */ - kENC_HOMETriggerOnFallingEdge, /*!< Use negative going edge-to-trigger initialization of position counters. */ -} enc_home_trigger_mode_t; - -/*! - * @brief Define INDEX signal's trigger mode. - * - * The ENC would count the trigger from INDEX signal line. - */ -typedef enum _enc_index_trigger_mode -{ - kENC_INDEXTriggerDisabled = 0U, /*!< INDEX signal's trigger is disabled. */ - kENC_INDEXTriggerOnRisingEdge, /*!< Use positive going edge-to-trigger initialization of position counters. */ - kENC_INDEXTriggerOnFallingEdge, /*!< Use negative going edge-to-trigger initialization of position counters. */ -} enc_index_trigger_mode_t; - -/*! - * @brief Define type for decoder work mode. - * - * The normal work mode uses the standard quadrature decoder with PHASEA and PHASEB. When in signal phase count mode, - * a positive transition of the PHASEA input generates a count signal while the PHASEB input and the reverse direction - * control the counter direction. If the reverse direction is not enabled, PHASEB = 0 means counting up and PHASEB = 1 - * means counting down. Otherwise, the direction is reversed. - */ -typedef enum _enc_decoder_work_mode -{ - kENC_DecoderWorkAsNormalMode = 0U, /*!< Use standard quadrature decoder with PHASEA and PHASEB. */ - kENC_DecoderWorkAsSignalPhaseCountMode, /*!< PHASEA input generates a count signal while PHASEB input control the - direction. */ -} enc_decoder_work_mode_t; - -/*! - * @brief Define type for the condition of POSMATCH pulses. - */ -typedef enum _enc_position_match_mode -{ - kENC_POSMATCHOnPositionCounterEqualToComapreValue = 0U, /*!< POSMATCH pulses when a match occurs between the - position counters (POS) and the compare value (COMP). */ - kENC_POSMATCHOnReadingAnyPositionCounter, /*!< POSMATCH pulses when any position counter register is read. */ -} enc_position_match_mode_t; - -/*! - * @brief Define type for determining how the revolution counter (REV) is incremented/decremented. - */ -typedef enum _enc_revolution_count_condition -{ - kENC_RevolutionCountOnINDEXPulse = 0U, /*!< Use INDEX pulse to increment/decrement revolution counter. */ - kENC_RevolutionCountOnRollOverModulus, /*!< Use modulus counting roll-over/under to increment/decrement revolution - counter. */ -} enc_revolution_count_condition_t; - -/*! - * @brief Define type for direction of self test generated signal. - */ -typedef enum _enc_self_test_direction -{ - kENC_SelfTestDirectionPositive = 0U, /*!< Self test generates the signal in positive direction. */ - kENC_SelfTestDirectionNegative, /*!< Self test generates the signal in negative direction. */ -} enc_self_test_direction_t; - -/*! - * @brief Define user configuration structure for ENC module. - */ -typedef struct _enc_config -{ - /* Basic counter. */ - bool enableReverseDirection; /*!< Enable reverse direction counting. */ - enc_decoder_work_mode_t decoderWorkMode; /*!< Enable signal phase count mode. */ - - /* Signal detection. */ - enc_home_trigger_mode_t HOMETriggerMode; /*!< Enable HOME to initialize position counters. */ - enc_index_trigger_mode_t INDEXTriggerMode; /*!< Enable INDEX to initialize position counters. */ - bool enableTRIGGERClearPositionCounter; /*!< Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER, or not. */ - bool enableTRIGGERClearHoldPositionCounter; /*!< Enable update of hold registers on rising edge of TRIGGER, or not. - */ - - /* Watchdog. */ - bool enableWatchdog; /*!< Enable the watchdog to detect if the target is moving or not. */ - uint16_t watchdogTimeoutValue; /*!< Watchdog timeout count value. It stores the timeout count for the quadrature - decoder module watchdog timer. This field is only available when - "enableWatchdog" = true. The available value is a 16-bit unsigned number.*/ - - /* Filter for PHASEA, PHASEB, INDEX and HOME. */ - uint16_t filterCount; /*!< Input Filter Sample Count. This value should be chosen to reduce the probability of - noisy samples causing an incorrect transition to be recognized. The value represent the - number of consecutive samples that must agree prior to the input filter accepting an - input transition. A value of 0x0 represents 3 samples. A value of 0x7 represents 10 - samples. The Available range is 0 - 7.*/ - uint16_t filterSamplePeriod; /*!< Input Filter Sample Period. This value should be set such that the sampling period - is larger than the period of the expected noise. This value represents the - sampling period (in IPBus clock cycles) of the decoder input signals. - The available range is 0 - 255. */ - - /* Position compare. */ - enc_position_match_mode_t positionMatchMode; /*!< The condition of POSMATCH pulses. */ - uint32_t positionCompareValue; /*!< Position compare value. The available value is a 32-bit number.*/ - - /* Modulus counting. */ - enc_revolution_count_condition_t revolutionCountCondition; /*!< Revolution Counter Modulus Enable. */ - bool enableModuloCountMode; /*!< Enable Modulo Counting. */ - uint32_t positionModulusValue; /*!< Position modulus value. This value would be available only when - "enableModuloCountMode" = true. The available value is a 32-bit number. */ - uint32_t positionInitialValue; /*!< Position initial value. The available value is a 32-bit number. */ -} enc_config_t; - -/*! - * @brief Define configuration structure for self test module. - * - * The self test module provides a quadrature test signal to the inputs of the quadrature decoder module. - * This is a factory test feature. It is also useful to customers' software development and testing. - */ -typedef struct _enc_self_test_config -{ - enc_self_test_direction_t signalDirection; /*!< Direction of self test generated signal. */ - uint16_t signalCount; /*!< Hold the number of quadrature advances to generate. The available range is 0 - 255.*/ - uint16_t signalPeriod; /*!< Hold the period of quadrature phase in IPBus clock cycles. - The available range is 0 - 31. */ -} enc_self_test_config_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @name Initialization and De-initialization - * @{ - */ - -/*! - * @brief Initialization for the ENC module. - * - * This function is to make the initialization for the ENC module. It should be called firstly before any operation to - * the ENC with the operations like: - * - Enable the clock for ENC module. - * - Configure the ENC's working attributes. - * - * @param base ENC peripheral base address. - * @param config Pointer to configuration structure. See to "enc_config_t". - */ -void ENC_Init(ENC_Type *base, const enc_config_t *config); - -/*! - * @brief De-initialization for the ENC module. - * - * This function is to make the de-initialization for the ENC module. It could be called when ENC is no longer used with - * the operations like: - * - Disable the clock for ENC module. - * - * @param base ENC peripheral base address. - */ -void ENC_Deinit(ENC_Type *base); - -/*! - * @brief Get an available pre-defined settings for ENC's configuration. - * - * This function initializes the ENC configuration structure with an available settings, the default value are: - * @code - * config->enableReverseDirection = false; - * config->decoderWorkMode = kENC_DecoderWorkAsNormalMode; - * config->HOMETriggerMode = kENC_HOMETriggerDisabled; - * config->INDEXTriggerMode = kENC_INDEXTriggerDisabled; - * config->enableTRIGGERClearPositionCounter = false; - * config->enableTRIGGERClearHoldPositionCounter = false; - * config->enableWatchdog = false; - * config->watchdogTimeoutValue = 0U; - * config->filterCount = 0U; - * config->filterSamplePeriod = 0U; - * config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue; - * config->positionCompareValue = 0xFFFFFFFFU; - * config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse; - * config->enableModuloCountMode = false; - * config->positionModulusValue = 0U; - * config->positionInitialValue = 0U; - * @endcode - * @param config Pointer to a variable of configuration structure. See to "enc_config_t". - */ -void ENC_GetDefaultConfig(enc_config_t *config); - -/*! - * @brief Load the initial position value to position counter. - * - * This function is to transfer the initial position value (UINIT and LINIT) contents to position counter (UPOS and - * LPOS), so that to provide the consistent operation the position counter registers. - * - * @param base ENC peripheral base address. - */ -void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base); - -/*! - * @brief Enable and configure the self test function. - * - * This function is to enable and configuration the self test function. It controls and sets the frequency of a - * quadrature signal generator. It provides a quadrature test signal to the inputs of the quadrature decoder module. - * It is a factory test feature; however, it may be useful to customers' software development and testing. - * - * @param base ENC peripheral base address. - * @param config Pointer to configuration structure. See to "enc_self_test_config_t". Pass "NULL" to disable. - */ -void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config); - -/*! - * @brief Enable watchdog for ENC module. - * - * @param base ENC peripheral base address - * @param enable Enables or disables the watchdog - */ -void ENC_EnableWatchdog(ENC_Type *base, bool enable); - -/*! - * @brief Set initial position value for ENC module. - * - * @param base ENC peripheral base address - * @param value Positive initial value - */ -void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value); - -/* @} */ - -/*! - * @name Status - * @{ - */ -/*! - * @brief Get the status flags. - * - * @param base ENC peripheral base address. - * - * @return Mask value of status flags. For available mask, see to "_enc_status_flags". - */ -uint32_t ENC_GetStatusFlags(ENC_Type *base); - -/*! - * @brief Clear the status flags. - * - * @param base ENC peripheral base address. - * @param mask Mask value of status flags to be cleared. For available mask, see to "_enc_status_flags". - */ -void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask); - -/*! - * @brief Get the signals' real-time status. - * - * @param base ENC peripheral base address. - * - * @return Mask value of signals' real-time status. For available mask, see to "_enc_signal_status_flags" - */ -static inline uint16_t ENC_GetSignalStatusFlags(ENC_Type *base) -{ - return base->IMR; -} -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enable the interrupts. - * - * @param base ENC peripheral base address. - * @param mask Mask value of interrupts to be enabled. For available mask, see to "_enc_interrupt_enable". - */ -void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask); - -/*! - * @brief Disable the interrupts. - * - * @param base ENC peripheral base address. - * @param mask Mask value of interrupts to be disabled. For available mask, see to "_enc_interrupt_enable". - */ -void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask); - -/*! - * @brief Get the enabled interrupts' flags. - * - * @param base ENC peripheral base address. - * - * @return Mask value of enabled interrupts. - */ -uint32_t ENC_GetEnabledInterrupts(ENC_Type *base); - -/* @} */ - -/*! - * @name Value Operation - * @{ - */ - -/*! - * @brief Get the current position counter's value. - * - * @param base ENC peripheral base address. - * - * @return Current position counter's value. - */ -uint32_t ENC_GetPositionValue(ENC_Type *base); - -/*! - * @brief Get the hold position counter's value. - * - * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold - * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to - * be attained. - * - * @param base ENC peripheral base address. - * - * @return Hold position counter's value. - */ -uint32_t ENC_GetHoldPositionValue(ENC_Type *base); - -/*! - * @brief Get the position difference counter's value. - * - * @param base ENC peripheral base address. - * - * @return The position difference counter's value. - */ -static inline uint16_t ENC_GetPositionDifferenceValue(ENC_Type *base) -{ - return base->POSD; -} - -/*! - * @brief Get the hold position difference counter's value. - * - * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold - * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to - * be attained. - * - * @param base ENC peripheral base address. - * - * @return Hold position difference counter's value. - */ -static inline uint16_t ENC_GetHoldPositionDifferenceValue(ENC_Type *base) -{ - return base->POSDH; -} - -/*! - * @brief Get the position revolution counter's value. - * - * @param base ENC peripheral base address. - * - * @return The position revolution counter's value. - */ -static inline uint16_t ENC_GetRevolutionValue(ENC_Type *base) -{ - return base->REV; -} -/*! - * @brief Get the hold position revolution counter's value. - * - * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold - * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to - * be attained. - * - * @param base ENC peripheral base address. - * - * @return Hold position revolution counter's value. - */ -static inline uint16_t ENC_GetHoldRevolutionValue(ENC_Type *base) -{ - return base->REVH; -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/* @} */ - -#endif /* _FSL_ENC_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexcomm.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexcomm.c deleted file mode 100644 index 7a21a1ce0ea..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexcomm.c +++ /dev/null @@ -1,412 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm" -#endif - -/*! - * @brief Used for conversion between `void*` and `uint32_t`. - */ -typedef union pvoid_to_u32 -{ - void *pvoid; - uint32_t u32; -} pvoid_to_u32_t; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! @brief Set the FLEXCOMM mode . */ -static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock); - -/*! @brief check whether flexcomm supports peripheral type */ -static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map FLEXCOMM instance number to base address. */ -static const uint32_t s_flexcommBaseAddrs[] = FLEXCOMM_BASE_ADDRS; - -/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ -static flexcomm_irq_handler_t s_flexcommIrqHandler[ARRAY_SIZE(s_flexcommBaseAddrs)]; - -/*! @brief Pointers to handles for each instance to provide context to interrupt routines */ -static void *s_flexcommHandle[ARRAY_SIZE(s_flexcommBaseAddrs)]; - -/*! @brief Array to map FLEXCOMM instance number to IRQ number. */ -IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief IDs of clock for each FLEXCOMM module */ -static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) -/*! @brief Pointers to FLEXCOMM resets for each instance. */ -static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* check whether flexcomm supports peripheral type */ -static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph) -{ - if (periph == FLEXCOMM_PERIPH_NONE) - { - return true; - } - else if (periph <= FLEXCOMM_PERIPH_I2S_TX) - { - return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false; - } - else if (periph == FLEXCOMM_PERIPH_I2S_RX) - { - return (base->PSELID & (1U << 7U)) > (uint32_t)0U ? true : false; - } - else - { - return false; - } -} - -/* Get the index corresponding to the FLEXCOMM */ -/*! brief Returns instance number for FLEXCOMM module with given base address. */ -uint32_t FLEXCOMM_GetInstance(void *base) -{ - uint32_t i; - pvoid_to_u32_t BaseAddr; - BaseAddr.pvoid = base; - - for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++) - { - if (BaseAddr.u32 == s_flexcommBaseAddrs[i]) - { - break; - } - } - - assert(i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT); - return i; -} - -/* Changes FLEXCOMM mode */ -static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock) -{ - /* Check whether peripheral type is present */ - if (!FLEXCOMM_PeripheralIsPresent(base, periph)) - { - return kStatus_OutOfRange; - } - - /* Flexcomm is locked to different peripheral type than expected */ - if (((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) != 0U) && - ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph)) - { - return kStatus_Fail; - } - - /* Check if we are asked to lock */ - if (lock != 0) - { - base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK; - } - else - { - base->PSELID = (uint32_t)periph; - } - - return kStatus_Success; -} - -/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ -status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) -{ - uint32_t idx = FLEXCOMM_GetInstance(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the peripheral clock */ - CLOCK_EnableClock(s_flexcommClocks[idx]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) - /* Reset the FLEXCOMM module */ - RESET_PeripheralReset(s_flexcommResets[idx]); -#endif - - /* Set the FLEXCOMM to given peripheral */ - return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0); -} - -/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM - * mode */ -void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(base); - - /* Clear handler first to avoid execution of the handler with wrong handle */ - s_flexcommIrqHandler[instance] = NULL; - s_flexcommHandle[instance] = flexcommHandle; - s_flexcommIrqHandler[instance] = handler; - SDK_ISR_EXIT_BARRIER; -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(FLEXCOMM0) -void FLEXCOMM0_DriverIRQHandler(void); -void FLEXCOMM0_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM0); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM1) -void FLEXCOMM1_DriverIRQHandler(void); -void FLEXCOMM1_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM1); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM2) -void FLEXCOMM2_DriverIRQHandler(void); -void FLEXCOMM2_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM2); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM3) -void FLEXCOMM3_DriverIRQHandler(void); -void FLEXCOMM3_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM3); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM4) -void FLEXCOMM4_DriverIRQHandler(void); -void FLEXCOMM4_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM4); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} - -#endif - -#if defined(FLEXCOMM5) -void FLEXCOMM5_DriverIRQHandler(void); -void FLEXCOMM5_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM5); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM6) -void FLEXCOMM6_DriverIRQHandler(void); -void FLEXCOMM6_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM6); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM7) -void FLEXCOMM7_DriverIRQHandler(void); -void FLEXCOMM7_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM7); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM8) -void FLEXCOMM8_DriverIRQHandler(void); -void FLEXCOMM8_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM8); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM9) -void FLEXCOMM9_DriverIRQHandler(void); -void FLEXCOMM9_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM9); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM10) -void FLEXCOMM10_DriverIRQHandler(void); -void FLEXCOMM10_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM10); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM11) -void FLEXCOMM11_DriverIRQHandler(void); -void FLEXCOMM11_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM11); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM12) -void FLEXCOMM12_DriverIRQHandler(void); -void FLEXCOMM12_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM12); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM13) -void FLEXCOMM13_DriverIRQHandler(void); -void FLEXCOMM13_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM13); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM14) -void FLEXCOMM14_DriverIRQHandler(void); -void FLEXCOMM14_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM14); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM15) -void FLEXCOMM15_DriverIRQHandler(void); -void FLEXCOMM15_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM15); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM16) -void FLEXCOMM16_DriverIRQHandler(void); -void FLEXCOMM16_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM16); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexcomm.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexcomm.h deleted file mode 100644 index f96086fdecc..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexcomm.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_FLEXCOMM_H_ -#define _FSL_FLEXCOMM_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup flexcomm_driver - * @{ - */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FlexCOMM driver version 2.0.2. */ -#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -/*! @brief FLEXCOMM peripheral modes. */ -typedef enum -{ - FLEXCOMM_PERIPH_NONE, /*!< No peripheral */ - FLEXCOMM_PERIPH_USART, /*!< USART peripheral */ - FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */ - FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */ - FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */ - FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */ -} FLEXCOMM_PERIPH_T; - -/*! @brief Typedef for interrupt handler. */ -typedef void (*flexcomm_irq_handler_t)(void *base, void *handle); - -/*! @brief Array with IRQ number for each FLEXCOMM module. */ -extern IRQn_Type const kFlexcommIrqs[]; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @brief Returns instance number for FLEXCOMM module with given base address. */ -uint32_t FLEXCOMM_GetInstance(void *base); - -/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ -status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph); - -/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM - * mode */ -void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle); - -#if defined(__cplusplus) -} -#endif - -/*@}*/ - -#endif /* _FSL_FLEXCOMM_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi.c deleted file mode 100644 index 7964163917f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi.c +++ /dev/null @@ -1,1180 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_flexspi.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexspi" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define FREQ_1MHz (1000000UL) -#define FLEXSPI_DLLCR_DEFAULT (0x100UL) -#define FLEXSPI_LUT_KEY_VAL (0x5AF05AF0UL) - -enum -{ - kFLEXSPI_DelayCellUnitMin = 75, /* 75ps. */ - kFLEXSPI_DelayCellUnitMax = 225, /* 225ps. */ -}; - -enum -{ - kFLEXSPI_FlashASampleClockSlaveDelayLocked = - FLEXSPI_STS2_ASLVLOCK_MASK, /* Flash A sample clock slave delay line locked. */ - kFLEXSPI_FlashASampleClockRefDelayLocked = - FLEXSPI_STS2_AREFLOCK_MASK, /* Flash A sample clock reference delay line locked. */ -#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK)) - kFLEXSPI_FlashBSampleClockSlaveDelayLocked = - FLEXSPI_STS2_BSLVLOCK_MASK, /* Flash B sample clock slave delay line locked. */ -#endif -#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK)) - kFLEXSPI_FlashBSampleClockRefDelayLocked = - FLEXSPI_STS2_BREFLOCK_MASK, /* Flash B sample clock reference delay line locked. */ -#endif -}; - -/*! @brief Common sets of flags used by the driver, _flexspi_flag_constants. */ -enum -{ - /*! IRQ sources enabled by the non-blocking transactional API. */ - kIrqFlags = kFLEXSPI_IpTxFifoWatermarkEmptyFlag | kFLEXSPI_IpRxFifoWatermarkAvailableFlag | - kFLEXSPI_SequenceExecutionTimeoutFlag | kFLEXSPI_IpCommandSequenceErrorFlag | - kFLEXSPI_IpCommandGrantTimeoutFlag | kFLEXSPI_IpCommandExecutionDoneFlag, - - /*! Errors to check for. */ - kErrorFlags = kFLEXSPI_SequenceExecutionTimeoutFlag | kFLEXSPI_IpCommandSequenceErrorFlag | - kFLEXSPI_IpCommandGrantTimeoutFlag, -}; - -/* FLEXSPI transfer state, _flexspi_transfer_state. */ -enum -{ - kFLEXSPI_Idle = 0x0U, /*!< Transfer is done. */ - kFLEXSPI_BusyWrite = 0x1U, /*!< FLEXSPI is busy write transfer. */ - kFLEXSPI_BusyRead = 0x2U, /*!< FLEXSPI is busy write transfer. */ -}; - -/*! @brief Typedef for interrupt handler. */ -typedef void (*flexspi_isr_t)(FLEXSPI_Type *base, flexspi_handle_t *handle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -static void FLEXSPI_Memset(void *src, uint8_t value, size_t length); - -/*! - * @brief Calculate flash A/B sample clock DLL. - * - * @param base FLEXSPI base pointer. - * @param config Flash configuration parameters. - */ -static uint32_t FLEXSPI_CalculateDll(FLEXSPI_Type *base, flexspi_device_config_t *config); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to flexspi bases for each instance. */ -static FLEXSPI_Type *const s_flexspiBases[] = FLEXSPI_BASE_PTRS; - -/*! @brief Pointers to flexspi IRQ number for each instance. */ -static const IRQn_Type s_flexspiIrqs[] = FLEXSPI_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Clock name array */ -static const clock_ip_name_t s_flexspiClock[] = FLEXSPI_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ -/*! @brief Pointers to flexspi handles for each instance. */ -static flexspi_handle_t *s_flexspiHandle[ARRAY_SIZE(s_flexspiBases)]; -#endif - -#if defined(FSL_FEATURE_FLEXSPI_HAS_RESET) && FSL_FEATURE_FLEXSPI_HAS_RESET -/*! @brief Pointers to FLEXSPI resets for each instance. */ -static const reset_ip_name_t s_flexspiResets[] = FLEXSPI_RSTS; -#endif - -#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ -/*! @brief Pointer to flexspi IRQ handler. */ -static flexspi_isr_t s_flexspiIsr; -#endif -/******************************************************************************* - * Code - ******************************************************************************/ -/* To avoid compiler opitimizing this API into memset() in library. */ -#if defined(__ICCARM__) -#pragma optimize = none -#endif /* defined(__ICCARM__) */ -static void FLEXSPI_Memset(void *src, uint8_t value, size_t length) -{ - assert(src != NULL); - uint8_t *p = src; - - for (uint32_t i = 0U; i < length; i++) - { - *p = value; - p++; - } -} - -uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_flexspiBases); instance++) - { - if (s_flexspiBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_flexspiBases)); - - return instance; -} - -static uint32_t FLEXSPI_CalculateDll(FLEXSPI_Type *base, flexspi_device_config_t *config) -{ - bool isUnifiedConfig = true; - uint32_t flexspiDllValue; - uint32_t dllValue; - uint32_t temp; -#if defined(FSL_FEATURE_FLEXSPI_DQS_DELAY_PS) && FSL_FEATURE_FLEXSPI_DQS_DELAY_PS - uint32_t internalDqsDelayPs = FSL_FEATURE_FLEXSPI_DQS_DELAY_PS; -#endif - uint32_t rxSampleClock = (base->MCR0 & FLEXSPI_MCR0_RXCLKSRC_MASK) >> FLEXSPI_MCR0_RXCLKSRC_SHIFT; - switch (rxSampleClock) - { - case (uint32_t)kFLEXSPI_ReadSampleClkLoopbackInternally: - case (uint32_t)kFLEXSPI_ReadSampleClkLoopbackFromDqsPad: - case (uint32_t)kFLEXSPI_ReadSampleClkLoopbackFromSckPad: - isUnifiedConfig = true; - break; - case (uint32_t)kFLEXSPI_ReadSampleClkExternalInputFromDqsPad: - if (config->isSck2Enabled) - { - isUnifiedConfig = true; - } - else - { - isUnifiedConfig = false; - } - break; - default: - assert(false); - break; - } - - if (isUnifiedConfig) - { - flexspiDllValue = FLEXSPI_DLLCR_DEFAULT; /* 1 fixed delay cells in DLL delay chain) */ - } - else - { - if (config->flexspiRootClk >= 100U * FREQ_1MHz) - { -#if defined(FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN) && FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN - /* DLLEN = 1, SLVDLYTARGET = 0x0, */ - flexspiDllValue = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(0x00); -#else - /* DLLEN = 1, SLVDLYTARGET = 0xF, */ - flexspiDllValue = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(0x0F); -#endif - } - else - { - temp = (uint32_t)config->dataValidTime * 1000U; /* Convert data valid time in ns to ps. */ - dllValue = temp / (uint32_t)kFLEXSPI_DelayCellUnitMin; - if (dllValue * (uint32_t)kFLEXSPI_DelayCellUnitMin < temp) - { - dllValue++; - } - flexspiDllValue = FLEXSPI_DLLCR_OVRDEN(1) | FLEXSPI_DLLCR_OVRDVAL(dllValue); - } - } - return flexspiDllValue; -} - -status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status) -{ - status_t result = kStatus_Success; - - /* Check for error. */ - status &= (uint32_t)kErrorFlags; - if (0U != status) - { - /* Select the correct error code.. */ - if (0U != (status & (uint32_t)kFLEXSPI_SequenceExecutionTimeoutFlag)) - { - result = kStatus_FLEXSPI_SequenceExecutionTimeout; - } - else if (0U != (status & (uint32_t)kFLEXSPI_IpCommandSequenceErrorFlag)) - { - result = kStatus_FLEXSPI_IpCommandSequenceError; - } - else if (0U != (status & (uint32_t)kFLEXSPI_IpCommandGrantTimeoutFlag)) - { - result = kStatus_FLEXSPI_IpCommandGrantTimeout; - } - else - { - assert(false); - } - - /* Clear the flags. */ - FLEXSPI_ClearInterruptStatusFlags(base, status); - - /* Reset fifos. These flags clear automatically. */ - base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; - base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; - } - - return result; -} - -/*! - * brief Initializes the FLEXSPI module and internal state. - * - * This function enables the clock for FLEXSPI and also configures the FLEXSPI with the - * input configure parameters. Users should call this function before any FLEXSPI operations. - * - * param base FLEXSPI peripheral base address. - * param config FLEXSPI configure structure. - */ -void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config) -{ - uint32_t configValue = 0; - uint8_t i = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the flexspi clock */ - (void)CLOCK_EnableClock(s_flexspiClock[FLEXSPI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if defined(FSL_FEATURE_FLEXSPI_HAS_RESET) && FSL_FEATURE_FLEXSPI_HAS_RESET - /* Reset the FLEXSPI module */ - RESET_PeripheralReset(s_flexspiResets[FLEXSPI_GetInstance(base)]); -#endif - - /* Reset peripheral before configuring it. */ - base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; - FLEXSPI_SoftwareReset(base); - - /* Configure MCR0 configuration items. */ - configValue = FLEXSPI_MCR0_RXCLKSRC(config->rxSampleClock) | FLEXSPI_MCR0_DOZEEN(config->enableDoze) | - FLEXSPI_MCR0_IPGRANTWAIT(config->ipGrantTimeoutCycle) | - FLEXSPI_MCR0_AHBGRANTWAIT(config->ahbConfig.ahbGrantTimeoutCycle) | - FLEXSPI_MCR0_SCKFREERUNEN(config->enableSckFreeRunning) | - FLEXSPI_MCR0_HSEN(config->enableHalfSpeedAccess) | -#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) - FLEXSPI_MCR0_COMBINATIONEN(config->enableCombination) | -#endif -#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) - FLEXSPI_MCR0_ATDFEN(config->ahbConfig.enableAHBWriteIpTxFifo) | -#endif -#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) - FLEXSPI_MCR0_ARDFEN(config->ahbConfig.enableAHBWriteIpRxFifo) | -#endif - FLEXSPI_MCR0_MDIS_MASK; - base->MCR0 = configValue; - - /* Configure MCR1 configurations. */ - configValue = - FLEXSPI_MCR1_SEQWAIT(config->seqTimeoutCycle) | FLEXSPI_MCR1_AHBBUSWAIT(config->ahbConfig.ahbBusTimeoutCycle); - base->MCR1 = configValue; - - /* Configure MCR2 configurations. */ - configValue = base->MCR2; - configValue &= ~(FLEXSPI_MCR2_RESUMEWAIT_MASK | -#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) - FLEXSPI_MCR2_SCKBDIFFOPT_MASK | -#endif - FLEXSPI_MCR2_SAMEDEVICEEN_MASK | FLEXSPI_MCR2_CLRAHBBUFOPT_MASK); - configValue |= FLEXSPI_MCR2_RESUMEWAIT(config->ahbConfig.resumeWaitCycle) | -#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) - FLEXSPI_MCR2_SCKBDIFFOPT(config->enableSckBDiffOpt) | -#endif - FLEXSPI_MCR2_SAMEDEVICEEN(config->enableSameConfigForAll) | - FLEXSPI_MCR2_CLRAHBBUFOPT(config->ahbConfig.enableClearAHBBufferOpt); - - base->MCR2 = configValue; - - /* Configure AHB control items. */ - configValue = base->AHBCR; - configValue &= ~(FLEXSPI_AHBCR_READADDROPT_MASK | FLEXSPI_AHBCR_PREFETCHEN_MASK | FLEXSPI_AHBCR_BUFFERABLEEN_MASK | - FLEXSPI_AHBCR_CACHABLEEN_MASK); - configValue |= FLEXSPI_AHBCR_READADDROPT(config->ahbConfig.enableReadAddressOpt) | - FLEXSPI_AHBCR_PREFETCHEN(config->ahbConfig.enableAHBPrefetch) | - FLEXSPI_AHBCR_BUFFERABLEEN(config->ahbConfig.enableAHBBufferable) | - FLEXSPI_AHBCR_CACHABLEEN(config->ahbConfig.enableAHBCachable); - base->AHBCR = configValue; - - /* Configure AHB rx buffers. */ - for (i = 0; i < (uint32_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++) - { - configValue = base->AHBRXBUFCR0[i]; - - configValue &= ~(FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK | FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK | - FLEXSPI_AHBRXBUFCR0_MSTRID_MASK | FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK); - configValue |= FLEXSPI_AHBRXBUFCR0_PREFETCHEN(config->ahbConfig.buffer[i].enablePrefetch) | - FLEXSPI_AHBRXBUFCR0_PRIORITY(config->ahbConfig.buffer[i].priority) | - FLEXSPI_AHBRXBUFCR0_MSTRID(config->ahbConfig.buffer[i].masterIndex) | - FLEXSPI_AHBRXBUFCR0_BUFSZ((uint32_t)config->ahbConfig.buffer[i].bufferSize / 8U); - base->AHBRXBUFCR0[i] = configValue; - } - - /* Configure IP Fifo watermarks. */ - base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXWMRK_MASK; - base->IPRXFCR |= FLEXSPI_IPRXFCR_RXWMRK((uint32_t)config->rxWatermark / 8U - 1U); - base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXWMRK_MASK; - base->IPTXFCR |= FLEXSPI_IPTXFCR_TXWMRK((uint32_t)config->txWatermark / 8U - 1U); - - /* Reset flash size on all ports */ - for (i = 0; i < (uint32_t)kFLEXSPI_PortCount; i++) - { - base->FLSHCR0[i] = 0; - } -} - -/*! - * brief Gets default settings for FLEXSPI. - * - * param config FLEXSPI configuration structure. - */ -void FLEXSPI_GetDefaultConfig(flexspi_config_t *config) -{ - /* Initializes the configure structure to zero. */ - FLEXSPI_Memset(config, 0, sizeof(*config)); - - config->rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally; - config->enableSckFreeRunning = false; -#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) - config->enableCombination = false; -#endif - config->enableDoze = true; - config->enableHalfSpeedAccess = false; -#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) - config->enableSckBDiffOpt = false; -#endif - config->enableSameConfigForAll = false; - config->seqTimeoutCycle = 0xFFFFU; - config->ipGrantTimeoutCycle = 0xFFU; - config->txWatermark = 8; - config->rxWatermark = 8; -#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) - config->ahbConfig.enableAHBWriteIpTxFifo = false; -#endif -#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) - config->ahbConfig.enableAHBWriteIpRxFifo = false; -#endif - config->ahbConfig.ahbGrantTimeoutCycle = 0xFFU; - config->ahbConfig.ahbBusTimeoutCycle = 0xFFFFU; - config->ahbConfig.resumeWaitCycle = 0x20U; - FLEXSPI_Memset(config->ahbConfig.buffer, 0, sizeof(config->ahbConfig.buffer)); - /* Use invalid master ID 0xF and buffer size 0 for the first several buffers. */ - for (uint8_t i = 0; i < ((uint8_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 2U); i++) - { - config->ahbConfig.buffer[i].enablePrefetch = true; /* Default enable AHB prefetch. */ - config->ahbConfig.buffer[i].masterIndex = 0xFU; /* Invalid master index which is not used, so will never hit. */ - config->ahbConfig.buffer[i].bufferSize = - 0; /* Default buffer size 0 for buffer0 to buffer(FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 3U)*/ - } - - for (uint8_t i = ((uint8_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 2U); - i < (uint8_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++) - { - config->ahbConfig.buffer[i].enablePrefetch = true; /* Default enable AHB prefetch. */ - config->ahbConfig.buffer[i].bufferSize = 256U; /* Default buffer size 256 bytes. */ - } - config->ahbConfig.enableClearAHBBufferOpt = false; - config->ahbConfig.enableReadAddressOpt = false; - config->ahbConfig.enableAHBPrefetch = false; - config->ahbConfig.enableAHBBufferable = false; - config->ahbConfig.enableAHBCachable = false; -} - -/*! - * brief Deinitializes the FLEXSPI module. - * - * Clears the FLEXSPI state and FLEXSPI module registers. - * param base FLEXSPI peripheral base address. - */ -void FLEXSPI_Deinit(FLEXSPI_Type *base) -{ - /* Reset peripheral. */ - FLEXSPI_SoftwareReset(base); -} - -/*! - * brief Update FLEXSPI DLL value depending on currently flexspi root clock. - * - * param base FLEXSPI peripheral base address. - * param config Flash configuration parameters. - * param port FLEXSPI Operation port. - */ -void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port) -{ - uint32_t configValue = 0; - uint32_t statusValue = 0; - uint8_t index = (uint8_t)port >> 1U; /* PortA with index 0, PortB with index 1. */ - - /* Wait for bus to be idle before changing flash configuration. */ - while (!FLEXSPI_GetBusIdleStatus(base)) - { - } - - /* Configure DLL. */ - configValue = FLEXSPI_CalculateDll(base, config); - base->DLLCR[index] = configValue; - - /* Exit stop mode. */ - base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; - - /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */ - if (index == 0U) - { - statusValue = - ((uint32_t)kFLEXSPI_FlashASampleClockSlaveDelayLocked | (uint32_t)kFLEXSPI_FlashASampleClockRefDelayLocked); - } -#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK)) - else - { - statusValue = - ((uint32_t)kFLEXSPI_FlashBSampleClockSlaveDelayLocked | (uint32_t)kFLEXSPI_FlashBSampleClockRefDelayLocked); - } -#endif - if (0U != (configValue & FLEXSPI_DLLCR_DLLEN_MASK)) - { - /* Wait slave delay line locked and slave reference delay line locked. */ - while ((base->STS2 & statusValue) != statusValue) - { - } - - /* Wait at least 100 NOPs*/ - for (uint8_t delay = 100U; delay > 0U; delay--) - { - __NOP(); - } - } -} - -/*! - * brief Configures the connected device parameter. - * - * This function configures the connected device relevant parameters, such as the size, command, and so on. - * The flash configuration value cannot have a default value. The user needs to configure it according to the - * connected device. - * - * param base FLEXSPI peripheral base address. - * param config Flash configuration parameters. - * param port FLEXSPI Operation port. - */ -void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port) -{ - uint32_t configValue = 0; - uint8_t index = (uint8_t)port >> 1U; /* PortA with index 0, PortB with index 1. */ - - /* Wait for bus to be idle before changing flash configuration. */ - while (!FLEXSPI_GetBusIdleStatus(base)) - { - } - - /* Configure flash size. */ - base->FLSHCR0[port] = config->flashSize; - - /* Configure flash parameters. */ - base->FLSHCR1[port] = FLEXSPI_FLSHCR1_CSINTERVAL(config->CSInterval) | - FLEXSPI_FLSHCR1_CSINTERVALUNIT(config->CSIntervalUnit) | - FLEXSPI_FLSHCR1_TCSH(config->CSHoldTime) | FLEXSPI_FLSHCR1_TCSS(config->CSSetupTime) | - FLEXSPI_FLSHCR1_CAS(config->columnspace) | FLEXSPI_FLSHCR1_WA(config->enableWordAddress); - - /* Configure AHB operation items. */ - configValue = base->FLSHCR2[port]; - - configValue &= ~(FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK | FLEXSPI_FLSHCR2_AWRWAIT_MASK | FLEXSPI_FLSHCR2_AWRSEQNUM_MASK | - FLEXSPI_FLSHCR2_AWRSEQID_MASK | FLEXSPI_FLSHCR2_ARDSEQNUM_MASK | FLEXSPI_FLSHCR2_ARDSEQID_MASK); - - configValue |= - FLEXSPI_FLSHCR2_AWRWAITUNIT(config->AHBWriteWaitUnit) | FLEXSPI_FLSHCR2_AWRWAIT(config->AHBWriteWaitInterval); - - if (config->AWRSeqNumber > 0U) - { - configValue |= FLEXSPI_FLSHCR2_AWRSEQID((uint32_t)config->AWRSeqIndex) | - FLEXSPI_FLSHCR2_AWRSEQNUM((uint32_t)config->AWRSeqNumber - 1U); - } - - if (config->ARDSeqNumber > 0U) - { - configValue |= FLEXSPI_FLSHCR2_ARDSEQID((uint32_t)config->ARDSeqIndex) | - FLEXSPI_FLSHCR2_ARDSEQNUM((uint32_t)config->ARDSeqNumber - 1U); - } - - base->FLSHCR2[port] = configValue; - - /* Configure DLL. */ - FLEXSPI_UpdateDllValue(base, config, port); - - /* Step into stop mode. */ - base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; - - /* Configure write mask. */ - if (config->enableWriteMask) - { - base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMOPT1_MASK; - } - else - { - base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMOPT1_MASK; - } - - if (index == 0U) /*PortA*/ - { - base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENA_MASK; - base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENA(config->enableWriteMask); - } -#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB)) && (FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB)) - else - { - base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENB_MASK; - base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENB(config->enableWriteMask); - } -#endif - - /* Exit stop mode. */ - base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; - - /* Wait for bus to be idle before use it access to external flash. */ - while (!FLEXSPI_GetBusIdleStatus(base)) - { - } -} - -/*! brief Updates the LUT table. - * - * param base FLEXSPI peripheral base address. - * param index From which index start to update. It could be any index of the LUT table, which - * also allows user to update command content inside a command. Each command consists of up to - * 8 instructions and occupy 4*32-bit memory. - * param cmd Command sequence array. - * param count Number of sequences. - */ -void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count) -{ - assert(index < 64U); - - uint32_t i = 0; - volatile uint32_t *lutBase; - - /* Wait for bus to be idle before changing flash configuration. */ - while (!FLEXSPI_GetBusIdleStatus(base)) - { - } - - /* Unlock LUT for update. */ -#if !((defined(FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO)) && (FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO)) - base->LUTKEY = FLEXSPI_LUT_KEY_VAL; -#endif - base->LUTCR = 0x02; - - lutBase = &base->LUT[index]; - for (i = 0; i < count; i++) - { - *lutBase++ = *cmd++; - } - - /* Lock LUT. */ -#if !((defined(FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO)) && (FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO)) - base->LUTKEY = FLEXSPI_LUT_KEY_VAL; -#endif - base->LUTCR = 0x01; -} - -/*! brief Update read sample clock source - * - * param base FLEXSPI peripheral base address. - * param clockSource clockSource of type #flexspi_read_sample_clock_t - */ -void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource) -{ - uint32_t mcr0Val; - - /* Wait for bus to be idle before changing flash configuration. */ - while (!FLEXSPI_GetBusIdleStatus(base)) - { - } - - mcr0Val = base->MCR0; - mcr0Val &= ~FLEXSPI_MCR0_RXCLKSRC_MASK; - mcr0Val |= FLEXSPI_MCR0_RXCLKSRC(clockSource); - base->MCR0 = mcr0Val; - - /* Reset peripheral. */ - FLEXSPI_SoftwareReset(base); -} - -/*! - * brief Sends a buffer of data bytes using blocking method. - * note This function blocks via polling until all bytes have been sent. - * param base FLEXSPI peripheral base address - * param buffer The data bytes to send - * param size The number of data bytes to send - * retval kStatus_Success write success without error - * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout - * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected - * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected - */ -status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) -{ - uint32_t txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1U; - uint32_t status; - status_t result = kStatus_Success; - uint32_t i = 0; - - /* Send data buffer */ - while (0U != size) - { - /* Wait until there is room in the fifo. This also checks for errors. */ - while (0U == ((status = base->INTR) & (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag)) - { - } - - result = FLEXSPI_CheckAndClearError(base, status); - - if (kStatus_Success != result) - { - return result; - } - - /* Write watermark level data into tx fifo . */ - if (size >= 8U * txWatermark) - { - for (i = 0U; i < 2U * txWatermark; i++) - { - base->TFDR[i] = *buffer++; - } - - size = size - 8U * txWatermark; - } - else - { - for (i = 0U; i < ((size + 3U) / 4U); i++) - { - base->TFDR[i] = *buffer++; - } - size = 0U; - } - - /* Push a watermark level data into IP TX FIFO. */ - base->INTR |= (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag; - } - - return result; -} - -/*! - * brief Receives a buffer of data bytes using a blocking method. - * note This function blocks via polling until all bytes have been sent. - * param base FLEXSPI peripheral base address - * param buffer The data bytes to send - * param size The number of data bytes to receive - * retval kStatus_Success read success without error - * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout - * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected - * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected - */ -status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) -{ - uint32_t rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1U; - uint32_t status; - status_t result = kStatus_Success; - uint32_t i = 0; - bool isReturn = false; - - /* Send data buffer */ - while (0U != size) - { - if (size >= 8U * rxWatermark) - { - /* Wait until there is room in the fifo. This also checks for errors. */ - while (0U == ((status = base->INTR) & (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag)) - { - result = FLEXSPI_CheckAndClearError(base, status); - - if (kStatus_Success != result) - { - isReturn = true; - break; - } - } - } - else - { - /* Wait fill level. This also checks for errors. */ - while (size > ((((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U)) - { - result = FLEXSPI_CheckAndClearError(base, base->INTR); - - if (kStatus_Success != result) - { - isReturn = true; - break; - } - } - } - - if (isReturn) - { - break; - } - - result = FLEXSPI_CheckAndClearError(base, base->INTR); - - if (kStatus_Success != result) - { - break; - } - - /* Read watermark level data from rx fifo . */ - if (size >= 8U * rxWatermark) - { - for (i = 0U; i < 2U * rxWatermark; i++) - { - *buffer++ = base->RFDR[i]; - } - - size = size - 8U * rxWatermark; - } - else - { - for (i = 0U; i < ((size + 3U) / 4U); i++) - { - *buffer++ = base->RFDR[i]; - } - size = 0; - } - - /* Pop out a watermark level datas from IP RX FIFO. */ - base->INTR |= (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag; - } - - return result; -} - -/*! - * brief Execute command to transfer a buffer data bytes using a blocking method. - * param base FLEXSPI peripheral base address - * param xfer pointer to the transfer structure. - * retval kStatus_Success command transfer success without error - * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout - * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected - * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected - */ -status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer) -{ - uint32_t configValue = 0; - status_t result = kStatus_Success; - - /* Clear sequence pointer before sending data to external devices. */ - base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK; - - /* Clear former pending status before start this transfer. */ - base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | - FLEXSPI_INTR_IPCMDGE_MASK; - - /* Configure base address. */ - base->IPCR0 = xfer->deviceAddress; - - /* Reset fifos. */ - base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; - base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; - - /* Configure data size. */ - if ((xfer->cmdType == kFLEXSPI_Read) || (xfer->cmdType == kFLEXSPI_Write) || (xfer->cmdType == kFLEXSPI_Config)) - { - configValue = FLEXSPI_IPCR1_IDATSZ(xfer->dataSize); - } - - /* Configure sequence ID. */ - configValue |= - FLEXSPI_IPCR1_ISEQID((uint32_t)xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM((uint32_t)xfer->SeqNumber - 1U); - base->IPCR1 = configValue; - - /* Start Transfer. */ - base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK; - - if ((xfer->cmdType == kFLEXSPI_Write) || (xfer->cmdType == kFLEXSPI_Config)) - { - result = FLEXSPI_WriteBlocking(base, xfer->data, xfer->dataSize); - } - else if (xfer->cmdType == kFLEXSPI_Read) - { - result = FLEXSPI_ReadBlocking(base, xfer->data, xfer->dataSize); - } - else - { - /* Empty else. */ - } - - /* Wait for bus to be idle before changing flash configuration. */ - while (!FLEXSPI_GetBusIdleStatus(base)) - { - } - - if (xfer->cmdType == kFLEXSPI_Command) - { - result = FLEXSPI_CheckAndClearError(base, base->INTR); - } - - return result; -} - -/*! - * brief Initializes the FLEXSPI handle which is used in transactional functions. - * - * param base FLEXSPI peripheral base address. - * param handle pointer to flexspi_handle_t structure to store the transfer state. - * param callback pointer to user callback function. - * param userData user parameter passed to the callback function. - */ -void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, - flexspi_handle_t *handle, - flexspi_transfer_callback_t callback, - void *userData) -{ - assert(NULL != handle); - - uint32_t instance = FLEXSPI_GetInstance(base); - - /* Zero handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Set callback and userData. */ - handle->completionCallback = callback; - handle->userData = userData; - -#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ - /* Save the context in global variables to support the double weak mechanism. */ - s_flexspiHandle[instance] = handle; - s_flexspiIsr = FLEXSPI_TransferHandleIRQ; -#endif - - /* Enable NVIC interrupt. */ - (void)EnableIRQ(s_flexspiIrqs[instance]); -} - -/*! - * brief Performs a interrupt non-blocking transfer on the FLEXSPI bus. - * - * note Calling the API returns immediately after transfer initiates. The user needs - * to call FLEXSPI_GetTransferCount to poll the transfer status to check whether - * the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer - * is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark level, or - * FLEXSPI could not read data properly. - * - * param base FLEXSPI peripheral base address. - * param handle pointer to flexspi_handle_t structure which stores the transfer state. - * param xfer pointer to flexspi_transfer_t structure. - * retval kStatus_Success Successfully start the data transmission. - * retval kStatus_FLEXSPI_Busy Previous transmission still not finished. - */ -status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer) -{ - uint32_t configValue = 0; - status_t result = kStatus_Success; - - assert(NULL != handle); - assert(NULL != xfer); - - /* Check if the I2C bus is idle - if not return busy status. */ - if (handle->state != (uint32_t)kFLEXSPI_Idle) - { - result = kStatus_FLEXSPI_Busy; - } - else - { - handle->data = xfer->data; - handle->dataSize = xfer->dataSize; - handle->transferTotalSize = xfer->dataSize; - handle->state = (xfer->cmdType == kFLEXSPI_Read) ? (uint32_t)kFLEXSPI_BusyRead : (uint32_t)kFLEXSPI_BusyWrite; - - /* Clear sequence pointer before sending data to external devices. */ - base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK; - - /* Clear former pending status before start this transfer. */ - base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | - FLEXSPI_INTR_IPCMDGE_MASK; - - /* Configure base address. */ - base->IPCR0 = xfer->deviceAddress; - - /* Reset fifos. */ - base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; - base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; - - /* Configure data size. */ - if ((xfer->cmdType == kFLEXSPI_Read) || (xfer->cmdType == kFLEXSPI_Write)) - { - configValue = FLEXSPI_IPCR1_IDATSZ(xfer->dataSize); - } - - /* Configure sequence ID. */ - configValue |= - FLEXSPI_IPCR1_ISEQID((uint32_t)xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM((uint32_t)xfer->SeqNumber - 1U); - base->IPCR1 = configValue; - - /* Start Transfer. */ - base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK; - - if (handle->state == (uint32_t)kFLEXSPI_BusyRead) - { - FLEXSPI_EnableInterrupts(base, (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag | - (uint32_t)kFLEXSPI_SequenceExecutionTimeoutFlag | - (uint32_t)kFLEXSPI_IpCommandSequenceErrorFlag | - (uint32_t)kFLEXSPI_IpCommandGrantTimeoutFlag | - (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag); - } - else - { - FLEXSPI_EnableInterrupts( - base, (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag | (uint32_t)kFLEXSPI_SequenceExecutionTimeoutFlag | - (uint32_t)kFLEXSPI_IpCommandSequenceErrorFlag | (uint32_t)kFLEXSPI_IpCommandGrantTimeoutFlag | - (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag); - } - } - - return result; -} - -/*! - * brief Gets the master transfer status during a interrupt non-blocking transfer. - * - * param base FLEXSPI peripheral base address. - * param handle pointer to flexspi_handle_t structure which stores the transfer state. - * param count Number of bytes transferred so far by the non-blocking transaction. - * retval kStatus_InvalidArgument count is Invalid. - * retval kStatus_Success Successfully return the count. - */ -status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count) -{ - assert(NULL != handle); - - status_t result = kStatus_Success; - - if (handle->state == (uint32_t)kFLEXSPI_Idle) - { - result = kStatus_NoTransferInProgress; - } - else - { - *count = handle->transferTotalSize - handle->dataSize; - } - - return result; -} - -/*! - * brief Aborts an interrupt non-blocking transfer early. - * - * note This API can be called at any time when an interrupt non-blocking transfer initiates - * to abort the transfer early. - * - * param base FLEXSPI peripheral base address. - * param handle pointer to flexspi_handle_t structure which stores the transfer state - */ -void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle) -{ - assert(NULL != handle); - - FLEXSPI_DisableInterrupts(base, (uint32_t)kIrqFlags); - handle->state = (uint32_t)kFLEXSPI_Idle; -} - -/*! - * brief Master interrupt handler. - * - * param base FLEXSPI peripheral base address. - * param handle pointer to flexspi_handle_t structure. - */ -void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle) -{ - uint32_t status; - status_t result; - uint32_t intEnableStatus; - uint32_t txWatermark; - uint32_t rxWatermark; - uint8_t i = 0; - - status = base->INTR; - intEnableStatus = base->INTEN; - - /* Check if interrupt is enabled and status is alerted. */ - if ((status & intEnableStatus) != 0U) - { - result = FLEXSPI_CheckAndClearError(base, status); - - if ((result != kStatus_Success) && (handle->completionCallback != NULL)) - { - FLEXSPI_TransferAbort(base, handle); - if (NULL != handle->completionCallback) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } - else - { - if ((0U != (status & (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag)) && - (handle->state == (uint32_t)kFLEXSPI_BusyRead)) - { - rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1U; - - /* Read watermark level data from rx fifo . */ - if (handle->dataSize >= 8U * rxWatermark) - { - /* Read watermark level data from rx fifo . */ - for (i = 0U; i < 2U * rxWatermark; i++) - { - *handle->data++ = base->RFDR[i]; - } - - handle->dataSize = handle->dataSize - 8U * rxWatermark; - } - else - { - for (i = 0; i < (handle->dataSize + 3U) / 4U; i++) - { - *handle->data++ = base->RFDR[i]; - } - handle->dataSize = 0; - } - /* Pop out a watermark level data from IP RX FIFO. */ - base->INTR |= (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag; - } - - if (0U != (status & (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag)) - { - base->INTR |= (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag; - - FLEXSPI_TransferAbort(base, handle); - - if (NULL != handle->completionCallback) - { - handle->completionCallback(base, handle, kStatus_Success, handle->userData); - } - } - - /* TX FIFO empty interrupt, push watermark level data into tx FIFO. */ - if ((0U != (status & (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag)) && - (handle->state == (uint32_t)kFLEXSPI_BusyWrite)) - { - if (0U != handle->dataSize) - { - txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1U; - /* Write watermark level data into tx fifo . */ - if (handle->dataSize >= 8U * txWatermark) - { - for (i = 0; i < 2U * txWatermark; i++) - { - base->TFDR[i] = *handle->data++; - } - - handle->dataSize = handle->dataSize - 8U * txWatermark; - } - else - { - for (i = 0; i < (handle->dataSize + 3U) / 4U; i++) - { - base->TFDR[i] = *handle->data++; - } - handle->dataSize = 0; - } - - /* Push a watermark level data into IP TX FIFO. */ - base->INTR |= (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag; - } - } - else - { - /* Empty else */ - } - } - } - else - { - /* Empty else */ - } -} - -#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ -#if defined(FLEXSPI) -void FLEXSPI_DriverIRQHandler(void); -void FLEXSPI_DriverIRQHandler(void) -{ - s_flexspiIsr(FLEXSPI, s_flexspiHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXSPI0) -void FLEXSPI0_DriverIRQHandler(void); -void FLEXSPI0_DriverIRQHandler(void) -{ - s_flexspiIsr(FLEXSPI0, s_flexspiHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif -#if defined(FLEXSPI1) -void FLEXSPI1_DriverIRQHandler(void); -void FLEXSPI1_DriverIRQHandler(void) -{ - s_flexspiIsr(FLEXSPI1, s_flexspiHandle[1]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(LSIO__FLEXSPI0) -void LSIO_OCTASPI0_INT_DriverIRQHandler(void); -void LSIO_OCTASPI0_INT_DriverIRQHandler(void) -{ - s_flexspiIsr(LSIO__FLEXSPI0, s_flexspiHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif -#if defined(LSIO__FLEXSPI1) -void LSIO_OCTASPI1_INT_DriverIRQHandler(void); -void LSIO_OCTASPI1_INT_DriverIRQHandler(void) -{ - s_flexspiIsr(LSIO__FLEXSPI1, s_flexspiHandle[1]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 - -void FLEXSPI0_FLEXSPI1_DriverIRQHandler(void); -void FLEXSPI0_FLEXSPI1_DriverIRQHandler(void) -{ - /* If handle is registered, treat the transfer function is enabled. */ - if (NULL != s_flexspiHandle[0]) - { - s_flexspiIsr(FLEXSPI0, s_flexspiHandle[0]); - } - if (NULL != s_flexspiHandle[1]) - { - s_flexspiIsr(FLEXSPI1, s_flexspiHandle[1]); - } -} -#endif - -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi.h deleted file mode 100644 index 5269d439daf..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi.h +++ /dev/null @@ -1,874 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __FSL_FLEXSPI_H_ -#define __FSL_FLEXSPI_H_ - -#include -#include "fsl_device_registers.h" -#include "fsl_common.h" - -/*! - * @addtogroup flexspi - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FLEXSPI driver version 2.3.5. */ -#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 6)) -/*@}*/ - -#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0) - -/*! @brief Formula to form FLEXSPI instructions in LUT table. */ -#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ - (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ - FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - -/*! @brief Status structure of FLEXSPI.*/ -enum -{ - kStatus_FLEXSPI_Busy = MAKE_STATUS(kStatusGroup_FLEXSPI, 0), /*!< FLEXSPI is busy */ - kStatus_FLEXSPI_SequenceExecutionTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 1), /*!< Sequence execution timeout - error occurred during FLEXSPI transfer. */ - kStatus_FLEXSPI_IpCommandSequenceError = MAKE_STATUS(kStatusGroup_FLEXSPI, 2), /*!< IP command Sequence execution - timeout error occurred during FLEXSPI transfer. */ - kStatus_FLEXSPI_IpCommandGrantTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 3), /*!< IP command grant timeout error - occurred during FLEXSPI transfer. */ -}; - -/*! @brief CMD definition of FLEXSPI, use to form LUT instruction, _flexspi_command. */ -enum -{ - kFLEXSPI_Command_STOP = 0x00U, /*!< Stop execution, deassert CS. */ - kFLEXSPI_Command_SDR = 0x01U, /*!< Transmit Command code to Flash, using SDR mode. */ - kFLEXSPI_Command_RADDR_SDR = 0x02U, /*!< Transmit Row Address to Flash, using SDR mode. */ - kFLEXSPI_Command_CADDR_SDR = 0x03U, /*!< Transmit Column Address to Flash, using SDR mode. */ - kFLEXSPI_Command_MODE1_SDR = 0x04U, /*!< Transmit 1-bit Mode bits to Flash, using SDR mode. */ - kFLEXSPI_Command_MODE2_SDR = 0x05U, /*!< Transmit 2-bit Mode bits to Flash, using SDR mode. */ - kFLEXSPI_Command_MODE4_SDR = 0x06U, /*!< Transmit 4-bit Mode bits to Flash, using SDR mode. */ - kFLEXSPI_Command_MODE8_SDR = 0x07U, /*!< Transmit 8-bit Mode bits to Flash, using SDR mode. */ - kFLEXSPI_Command_WRITE_SDR = 0x08U, /*!< Transmit Programming Data to Flash, using SDR mode. */ - kFLEXSPI_Command_READ_SDR = 0x09U, /*!< Receive Read Data from Flash, using SDR mode. */ - kFLEXSPI_Command_LEARN_SDR = 0x0AU, /*!< Receive Read Data or Preamble bit from Flash, SDR mode. */ - kFLEXSPI_Command_DATSZ_SDR = 0x0BU, /*!< Transmit Read/Program Data size (byte) to Flash, SDR mode. */ - kFLEXSPI_Command_DUMMY_SDR = 0x0CU, /*!< Leave data lines undriven by FlexSPI controller.*/ - kFLEXSPI_Command_DUMMY_RWDS_SDR = 0x0DU, /*!< Leave data lines undriven by FlexSPI controller, - dummy cycles decided by RWDS. */ - kFLEXSPI_Command_DDR = 0x21U, /*!< Transmit Command code to Flash, using DDR mode. */ - kFLEXSPI_Command_RADDR_DDR = 0x22U, /*!< Transmit Row Address to Flash, using DDR mode. */ - kFLEXSPI_Command_CADDR_DDR = 0x23U, /*!< Transmit Column Address to Flash, using DDR mode. */ - kFLEXSPI_Command_MODE1_DDR = 0x24U, /*!< Transmit 1-bit Mode bits to Flash, using DDR mode. */ - kFLEXSPI_Command_MODE2_DDR = 0x25U, /*!< Transmit 2-bit Mode bits to Flash, using DDR mode. */ - kFLEXSPI_Command_MODE4_DDR = 0x26U, /*!< Transmit 4-bit Mode bits to Flash, using DDR mode. */ - kFLEXSPI_Command_MODE8_DDR = 0x27U, /*!< Transmit 8-bit Mode bits to Flash, using DDR mode. */ - kFLEXSPI_Command_WRITE_DDR = 0x28U, /*!< Transmit Programming Data to Flash, using DDR mode. */ - kFLEXSPI_Command_READ_DDR = 0x29U, /*!< Receive Read Data from Flash, using DDR mode. */ - kFLEXSPI_Command_LEARN_DDR = 0x2AU, /*!< Receive Read Data or Preamble bit from Flash, DDR mode. */ - kFLEXSPI_Command_DATSZ_DDR = 0x2BU, /*!< Transmit Read/Program Data size (byte) to Flash, DDR mode. */ - kFLEXSPI_Command_DUMMY_DDR = 0x2CU, /*!< Leave data lines undriven by FlexSPI controller.*/ - kFLEXSPI_Command_DUMMY_RWDS_DDR = 0x2DU, /*!< Leave data lines undriven by FlexSPI controller, - dummy cycles decided by RWDS. */ - kFLEXSPI_Command_JUMP_ON_CS = 0x1FU, /*!< Stop execution, deassert CS and save operand[7:0] as the - instruction start pointer for next sequence */ -}; - -/*! @brief pad definition of FLEXSPI, use to form LUT instruction. */ -typedef enum _flexspi_pad -{ - kFLEXSPI_1PAD = 0x00U, /*!< Transmit command/address and transmit/receive data only through DATA0/DATA1. */ - kFLEXSPI_2PAD = 0x01U, /*!< Transmit command/address and transmit/receive data only through DATA[1:0]. */ - kFLEXSPI_4PAD = 0x02U, /*!< Transmit command/address and transmit/receive data only through DATA[3:0]. */ - kFLEXSPI_8PAD = 0x03U, /*!< Transmit command/address and transmit/receive data only through DATA[7:0]. */ -} flexspi_pad_t; - -/*! @brief FLEXSPI interrupt status flags.*/ -typedef enum _flexspi_flags -{ - kFLEXSPI_SequenceExecutionTimeoutFlag = FLEXSPI_INTEN_SEQTIMEOUTEN_MASK, /*!< Sequence execution timeout. */ -#if defined(FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN) && FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN - kFLEXSPI_AhbBusErrorFlag = FLEXSPI_INTEN_AHBBUSERROREN_MASK, /*!< AHB Bus error flag. */ -#else - kFLEXSPI_AhbBusTimeoutFlag = FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK, /*!< AHB Bus timeout. */ -#endif - kFLEXSPI_SckStoppedBecauseTxEmptyFlag = - FLEXSPI_INTEN_SCKSTOPBYWREN_MASK, /*!< SCK is stopped during command - sequence because Async TX FIFO empty. */ - kFLEXSPI_SckStoppedBecauseRxFullFlag = - FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK, /*!< SCK is stopped during command - sequence because Async RX FIFO full. */ -#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) - kFLEXSPI_DataLearningFailedFlag = FLEXSPI_INTEN_DATALEARNFAILEN_MASK, /*!< Data learning failed. */ -#endif - kFLEXSPI_IpTxFifoWatermarkEmptyFlag = FLEXSPI_INTEN_IPTXWEEN_MASK, /*!< IP TX FIFO WaterMark empty. */ - kFLEXSPI_IpRxFifoWatermarkAvailableFlag = FLEXSPI_INTEN_IPRXWAEN_MASK, /*!< IP RX FIFO WaterMark available. */ - kFLEXSPI_AhbCommandSequenceErrorFlag = - FLEXSPI_INTEN_AHBCMDERREN_MASK, /*!< AHB triggered Command Sequences Error. */ - kFLEXSPI_IpCommandSequenceErrorFlag = FLEXSPI_INTEN_IPCMDERREN_MASK, /*!< IP triggered Command Sequences Error. */ - kFLEXSPI_AhbCommandGrantTimeoutFlag = - FLEXSPI_INTEN_AHBCMDGEEN_MASK, /*!< AHB triggered Command Sequences Grant Timeout. */ - kFLEXSPI_IpCommandGrantTimeoutFlag = - FLEXSPI_INTEN_IPCMDGEEN_MASK, /*!< IP triggered Command Sequences Grant Timeout. */ - kFLEXSPI_IpCommandExecutionDoneFlag = - FLEXSPI_INTEN_IPCMDDONEEN_MASK, /*!< IP triggered Command Sequences Execution finished. */ - kFLEXSPI_AllInterruptFlags = 0xFFFU, /*!< All flags. */ -} flexspi_flags_t; - -/*! @brief FLEXSPI sample clock source selection for Flash Reading.*/ -typedef enum _flexspi_read_sample_clock -{ - kFLEXSPI_ReadSampleClkLoopbackInternally = 0x0U, /*!< Dummy Read strobe generated by FlexSPI Controller - and loopback internally. */ - kFLEXSPI_ReadSampleClkLoopbackFromDqsPad = 0x1U, /*!< Dummy Read strobe generated by FlexSPI Controller - and loopback from DQS pad. */ - kFLEXSPI_ReadSampleClkLoopbackFromSckPad = 0x2U, /*!< SCK output clock and loopback from SCK pad. */ - kFLEXSPI_ReadSampleClkExternalInputFromDqsPad = 0x3U, /*!< Flash provided Read strobe and input from DQS pad. */ -} flexspi_read_sample_clock_t; - -/*! @brief FLEXSPI interval unit for flash device select.*/ -typedef enum _flexspi_cs_interval_cycle_unit -{ - kFLEXSPI_CsIntervalUnit1SckCycle = 0x0U, /*!< Chip selection interval: CSINTERVAL * 1 serial clock cycle. */ - kFLEXSPI_CsIntervalUnit256SckCycle = 0x1U, /*!< Chip selection interval: CSINTERVAL * 256 serial clock cycle. */ -} flexspi_cs_interval_cycle_unit_t; - -/*! @brief FLEXSPI AHB wait interval unit for writing.*/ -typedef enum _flexspi_ahb_write_wait_unit -{ - kFLEXSPI_AhbWriteWaitUnit2AhbCycle = 0x0U, /*!< AWRWAIT unit is 2 ahb clock cycle. */ - kFLEXSPI_AhbWriteWaitUnit8AhbCycle = 0x1U, /*!< AWRWAIT unit is 8 ahb clock cycle. */ - kFLEXSPI_AhbWriteWaitUnit32AhbCycle = 0x2U, /*!< AWRWAIT unit is 32 ahb clock cycle. */ - kFLEXSPI_AhbWriteWaitUnit128AhbCycle = 0x3U, /*!< AWRWAIT unit is 128 ahb clock cycle. */ - kFLEXSPI_AhbWriteWaitUnit512AhbCycle = 0x4U, /*!< AWRWAIT unit is 512 ahb clock cycle. */ - kFLEXSPI_AhbWriteWaitUnit2048AhbCycle = 0x5U, /*!< AWRWAIT unit is 2048 ahb clock cycle. */ - kFLEXSPI_AhbWriteWaitUnit8192AhbCycle = 0x6U, /*!< AWRWAIT unit is 8192 ahb clock cycle. */ - kFLEXSPI_AhbWriteWaitUnit32768AhbCycle = 0x7U, /*!< AWRWAIT unit is 32768 ahb clock cycle. */ -} flexspi_ahb_write_wait_unit_t; - -/*! @brief Error Code when IP command Error detected.*/ -typedef enum _flexspi_ip_error_code -{ - kFLEXSPI_IpCmdErrorNoError = 0x0U, /*!< No error. */ - kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd = 0x2U, /*!< IP command with JMP_ON_CS instruction used. */ - kFLEXSPI_IpCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */ - kFLEXSPI_IpCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR - used in DDR sequence. */ - kFLEXSPI_IpCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR - used in SDR sequence. */ - kFLEXSPI_IpCmdErrorInvalidAddress = 0x6U, /*!< Flash access start address exceed the whole - flash address range (A1/A2/B1/B2). */ - kFLEXSPI_IpCmdErrorSequenceExecutionTimeout = 0xEU, /*!< Sequence execution timeout. */ - kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss = 0xFU, /*!< Flash boundary crossed. */ -} flexspi_ip_error_code_t; - -/*! @brief Error Code when AHB command Error detected.*/ -typedef enum _flexspi_ahb_error_code -{ - kFLEXSPI_AhbCmdErrorNoError = 0x0U, /*!< No error. */ - kFLEXSPI_AhbCmdErrorJumpOnCsInWriteCmd = 0x2U, /*!< AHB Write command with JMP_ON_CS instruction - used in the sequence. */ - kFLEXSPI_AhbCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */ - kFLEXSPI_AhbCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR used - in DDR sequence. */ - kFLEXSPI_AhbCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR - used in SDR sequence. */ - kFLEXSPI_AhbCmdSequenceExecutionTimeout = 0x6U, /*!< Sequence execution timeout. */ -} flexspi_ahb_error_code_t; - -/*! @brief FLEXSPI operation port select.*/ -typedef enum _flexspi_port -{ - kFLEXSPI_PortA1 = 0x0U, /*!< Access flash on A1 port. */ - kFLEXSPI_PortA2, /*!< Access flash on A2 port. */ -#if !((defined(FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB)) && (FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB)) - kFLEXSPI_PortB1, /*!< Access flash on B1 port. */ - kFLEXSPI_PortB2, /*!< Access flash on B2 port. */ -#endif - kFLEXSPI_PortCount -} flexspi_port_t; - -/*! @brief Trigger source of current command sequence granted by arbitrator.*/ -typedef enum _flexspi_arb_command_source -{ - kFLEXSPI_AhbReadCommand = 0x0U, - kFLEXSPI_AhbWriteCommand = 0x1U, - kFLEXSPI_IpCommand = 0x2U, - kFLEXSPI_SuspendedCommand = 0x3U, -} flexspi_arb_command_source_t; - -/*! @brief Command type. */ -typedef enum _flexspi_command_type -{ - kFLEXSPI_Command, /*!< FlexSPI operation: Only command, both TX and Rx buffer are ignored. */ - kFLEXSPI_Config, /*!< FlexSPI operation: Configure device mode, the TX fifo size is fixed in LUT. */ - kFLEXSPI_Read, /* /!< FlexSPI operation: Read, only Rx Buffer is effective. */ - kFLEXSPI_Write, /* /!< FlexSPI operation: Read, only Tx Buffer is effective. */ -} flexspi_command_type_t; - -typedef struct _flexspi_ahbBuffer_config -{ - uint8_t priority; /*!< This priority for AHB Master Read which this AHB RX Buffer is assigned. */ - uint8_t masterIndex; /*!< AHB Master ID the AHB RX Buffer is assigned. */ - uint16_t bufferSize; /*!< AHB buffer size in byte. */ - bool enablePrefetch; /*!< AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master, allows - prefetch disable/enable separately for each master. */ -} flexspi_ahbBuffer_config_t; - -/*! @brief FLEXSPI configuration structure. */ -typedef struct _flexspi_config -{ - flexspi_read_sample_clock_t rxSampleClock; /*!< Sample Clock source selection for Flash Reading. */ - bool enableSckFreeRunning; /*!< Enable/disable SCK output free-running. */ -#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) - bool enableCombination; /*!< Enable/disable combining PORT A and B Data Pins - (SIOA[3:0] and SIOB[3:0]) to support Flash Octal mode. */ -#endif - bool enableDoze; /*!< Enable/disable doze mode support. */ - bool enableHalfSpeedAccess; /*!< Enable/disable divide by 2 of the clock for half - speed commands. */ -#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) - bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock - output, when enable, Port B flash access is not available. */ -#endif - bool enableSameConfigForAll; /*!< Enable/disable same configuration for all connected devices - when enabled, same configuration in FLASHA1CRx is applied to all. */ - uint16_t seqTimeoutCycle; /*!< Timeout wait cycle for command sequence execution, - timeout after ahbGrantTimeoutCyle*1024 serial root clock cycles. */ - uint8_t ipGrantTimeoutCycle; /*!< Timeout wait cycle for IP command grant, timeout after - ipGrantTimeoutCycle*1024 AHB clock cycles. */ - uint8_t txWatermark; /*!< FLEXSPI IP transmit watermark value. */ - uint8_t rxWatermark; /*!< FLEXSPI receive watermark value. */ - struct - { -#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) - bool enableAHBWriteIpTxFifo; /*!< Enable AHB bus write access to IP TX FIFO. */ -#endif -#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) - bool enableAHBWriteIpRxFifo; /*!< Enable AHB bus write access to IP RX FIFO. */ -#endif - uint8_t ahbGrantTimeoutCycle; /*!< Timeout wait cycle for AHB command grant, - timeout after ahbGrantTimeoutCyle*1024 AHB clock cycles. */ - uint16_t ahbBusTimeoutCycle; /*!< Timeout wait cycle for AHB read/write access, - timeout after ahbBusTimeoutCycle*1024 AHB clock cycles. */ - uint8_t resumeWaitCycle; /*!< Wait cycle for idle state before suspended command sequence - resume, timeout after ahbBusTimeoutCycle AHB clock cycles. */ - flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer size. */ - bool enableClearAHBBufferOpt; /*!< Enable/disable automatically clean AHB RX Buffer and TX Buffer - when FLEXSPI returns STOP mode ACK. */ - bool enableReadAddressOpt; /*!< Enable/disable remove AHB read burst start address alignment limitation. - when enable, there is no AHB read burst start address alignment limitation. */ - bool enableAHBPrefetch; /*!< Enable/disable AHB read prefetch feature, when enabled, FLEXSPI - will fetch more data than current AHB burst. */ - bool enableAHBBufferable; /*!< Enable/disable AHB bufferable write access support, when enabled, - FLEXSPI return before waiting for command execution finished. */ - bool enableAHBCachable; /*!< Enable AHB bus cachable read access support. */ - } ahbConfig; -} flexspi_config_t; - -/*! @brief External device configuration items. */ -typedef struct _flexspi_device_config -{ - uint32_t flexspiRootClk; /*!< FLEXSPI serial root clock. */ - bool isSck2Enabled; /*!< FLEXSPI use SCK2. */ - uint32_t flashSize; /*!< Flash size in KByte. */ - flexspi_cs_interval_cycle_unit_t CSIntervalUnit; /*!< CS interval unit, 1 or 256 cycle. */ - uint16_t CSInterval; /*!< CS line assert interval, multiply CS interval unit to - get the CS line assert interval cycles. */ - uint8_t CSHoldTime; /*!< CS line hold time. */ - uint8_t CSSetupTime; /*!< CS line setup time. */ - uint8_t dataValidTime; /*!< Data valid time for external device. */ - uint8_t columnspace; /*!< Column space size. */ - bool enableWordAddress; /*!< If enable word address.*/ - uint8_t AWRSeqIndex; /*!< Sequence ID for AHB write command. */ - uint8_t AWRSeqNumber; /*!< Sequence number for AHB write command. */ - uint8_t ARDSeqIndex; /*!< Sequence ID for AHB read command. */ - uint8_t ARDSeqNumber; /*!< Sequence number for AHB read command. */ - flexspi_ahb_write_wait_unit_t AHBWriteWaitUnit; /*!< AHB write wait unit. */ - uint16_t AHBWriteWaitInterval; /*!< AHB write wait interval, multiply AHB write interval - unit to get the AHB write wait cycles. */ - bool enableWriteMask; /*!< Enable/Disable FLEXSPI drive DQS pin as write mask - when writing to external device. */ -} flexspi_device_config_t; - -/*! @brief Transfer structure for FLEXSPI. */ -typedef struct _flexspi_transfer -{ - uint32_t deviceAddress; /*!< Operation device address. */ - flexspi_port_t port; /*!< Operation port. */ - flexspi_command_type_t cmdType; /*!< Execution command type. */ - uint8_t seqIndex; /*!< Sequence ID for command. */ - uint8_t SeqNumber; /*!< Sequence number for command. */ - uint32_t *data; /*!< Data buffer. */ - size_t dataSize; /*!< Data size in bytes. */ -} flexspi_transfer_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _flexspi_handle flexspi_handle_t; - -/*! @brief FLEXSPI transfer callback function. */ -typedef void (*flexspi_transfer_callback_t)(FLEXSPI_Type *base, - flexspi_handle_t *handle, - status_t status, - void *userData); - -/*! @brief Transfer handle structure for FLEXSPI. */ -struct _flexspi_handle -{ - uint32_t state; /*!< Internal state for FLEXSPI transfer */ - uint32_t *data; /*!< Data buffer. */ - size_t dataSize; /*!< Remaining Data size in bytes. */ - size_t transferTotalSize; /*!< Total Data size in bytes. */ - flexspi_transfer_callback_t completionCallback; /*!< Callback for users while transfer finish or error occurred */ - void *userData; /*!< FLEXSPI callback function parameter.*/ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus. */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Get the instance number for FLEXSPI. - * - * @param base FLEXSPI base pointer. - */ -uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base); - -/*! - * @brief Check and clear IP command execution errors. - * - * @param base FLEXSPI base pointer. - * @param status interrupt status. - */ -status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status); - -/*! - * @brief Initializes the FLEXSPI module and internal state. - * - * This function enables the clock for FLEXSPI and also configures the FLEXSPI with the - * input configure parameters. Users should call this function before any FLEXSPI operations. - * - * @param base FLEXSPI peripheral base address. - * @param config FLEXSPI configure structure. - */ -void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config); - -/*! - * @brief Gets default settings for FLEXSPI. - * - * @param config FLEXSPI configuration structure. - */ -void FLEXSPI_GetDefaultConfig(flexspi_config_t *config); - -/*! - * @brief Deinitializes the FLEXSPI module. - * - * Clears the FLEXSPI state and FLEXSPI module registers. - * @param base FLEXSPI peripheral base address. - */ -void FLEXSPI_Deinit(FLEXSPI_Type *base); - -/*! - * @brief Update FLEXSPI DLL value depending on currently flexspi root clock. - * - * @param base FLEXSPI peripheral base address. - * @param config Flash configuration parameters. - * @param port FLEXSPI Operation port. - */ -void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port); - -/*! - * @brief Configures the connected device parameter. - * - * This function configures the connected device relevant parameters, such as the size, command, and so on. - * The flash configuration value cannot have a default value. The user needs to configure it according to the - * connected device. - * - * @param base FLEXSPI peripheral base address. - * @param config Flash configuration parameters. - * @param port FLEXSPI Operation port. - */ -void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port); - -/*! - * @brief Software reset for the FLEXSPI logic. - * - * This function sets the software reset flags for both AHB and buffer domain and - * resets both AHB buffer and also IP FIFOs. - * - * @param base FLEXSPI peripheral base address. - */ -static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base) -{ - base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; - while (0U != (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)) - { - } -} - -/*! - * @brief Enables or disables the FLEXSPI module. - * - * @param base FLEXSPI peripheral base address. - * @param enable True means enable FLEXSPI, false means disable. - */ -static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable) -{ - if (enable) - { - base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; - } - else - { - base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; - } -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ -/*! - * @brief Enables the FLEXSPI interrupts. - * - * @param base FLEXSPI peripheral base address. - * @param mask FLEXSPI interrupt source. - */ -static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask) -{ - base->INTEN |= mask; -} - -/*! - * @brief Disable the FLEXSPI interrupts. - * - * @param base FLEXSPI peripheral base address. - * @param mask FLEXSPI interrupt source. - */ -static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask) -{ - base->INTEN &= ~mask; -} - -/* @} */ - -/*! @name DMA control */ -/*@{*/ - -/*! - * @brief Enables or disables FLEXSPI IP Tx FIFO DMA requests. - * - * @param base FLEXSPI peripheral base address. - * @param enable Enable flag for transmit DMA request. Pass true for enable, false for disable. - */ -static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable) -{ - if (enable) - { - base->IPTXFCR |= FLEXSPI_IPTXFCR_TXDMAEN_MASK; - } - else - { - base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXDMAEN_MASK; - } -} - -/*! - * @brief Enables or disables FLEXSPI IP Rx FIFO DMA requests. - * - * @param base FLEXSPI peripheral base address. - * @param enable Enable flag for receive DMA request. Pass true for enable, false for disable. - */ -static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable) -{ - if (enable) - { - base->IPRXFCR |= FLEXSPI_IPRXFCR_RXDMAEN_MASK; - } - else - { - base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXDMAEN_MASK; - } -} - -/*! - * @brief Gets FLEXSPI IP tx fifo address for DMA transfer. - * - * @param base FLEXSPI peripheral base address. - * @retval The tx fifo address. - */ -static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base) -{ - return (uint32_t)&base->TFDR[0]; -} - -/*! - * @brief Gets FLEXSPI IP rx fifo address for DMA transfer. - * - * @param base FLEXSPI peripheral base address. - * @retval The rx fifo address. - */ -static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base) -{ - return (uint32_t)&base->RFDR[0]; -} - -/*@}*/ - -/*! @name FIFO control */ -/*@{*/ - -/*! @brief Clears the FLEXSPI IP FIFO logic. - * - * @param base FLEXSPI peripheral base address. - * @param txFifo Pass true to reset TX FIFO. - * @param rxFifo Pass true to reset RX FIFO. - */ -static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo) -{ - if (txFifo) - { - base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; - } - if (rxFifo) - { - base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; - } -} - -/*! - * @brief Gets the valid data entries in the FLEXSPI FIFOs. - * - * @param base FLEXSPI peripheral base address. - * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned. - * Pass NULL if this value is not required. - * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned. - * Pass NULL if this value is not required. - */ -static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount) -{ - if (NULL != txCount) - { - *txCount = (((base->IPTXFSTS) & FLEXSPI_IPTXFSTS_FILL_MASK) >> FLEXSPI_IPTXFSTS_FILL_SHIFT) * 8U; - } - if (NULL != rxCount) - { - *rxCount = (((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U; - } -} - -/*@}*/ - -/*! - * @name Status - * @{ - */ -/*! - * @brief Get the FLEXSPI interrupt status flags. - * - * @param base FLEXSPI peripheral base address. - * @retval interrupt status flag, use status flag to AND #flexspi_flags_t could get the related status. - */ -static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base) -{ - return base->INTR; -} - -/*! - * @brief Get the FLEXSPI interrupt status flags. - * - * @param base FLEXSPI peripheral base address. - * @param mask FLEXSPI interrupt source. - */ -static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask) -{ - base->INTR |= mask; -} - -#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) -/*! @brief Gets the sampling clock phase selection after Data Learning. - * - * @param base FLEXSPI peripheral base address. - * @param portAPhase Pointer to a uint8_t type variable to receive the selected clock phase on PORTA. - * @param portBPhase Pointer to a uint8_t type variable to receive the selected clock phase on PORTB. - */ -static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *portAPhase, uint8_t *portBPhase) -{ - if (portAPhase != NULL) - { - *portAPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEA_MASK) >> FLEXSPI_STS0_DATALEARNPHASEA_SHIFT); - } - -#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB)) - if (portBPhase != NULL) - { - *portBPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEB_MASK) >> FLEXSPI_STS0_DATALEARNPHASEB_SHIFT); - } -#endif -} -#endif - -/*! @brief Gets the trigger source of current command sequence granted by arbitrator. - * - * @param base FLEXSPI peripheral base address. - * @retval trigger source of current command sequence. - */ -static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base) -{ - return (flexspi_arb_command_source_t)( - (uint32_t)((base->STS0 & FLEXSPI_STS0_ARBCMDSRC_MASK) >> FLEXSPI_STS0_ARBCMDSRC_SHIFT)); -} - -/*! @brief Gets the error code when IP command error detected. - * - * @param base FLEXSPI peripheral base address. - * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected. - * @retval error code when IP command error detected. - */ -static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index) -{ - *index = (uint8_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRID_MASK) >> FLEXSPI_STS1_IPCMDERRID_SHIFT); - return (flexspi_ip_error_code_t)( - (uint32_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRCODE_MASK) >> FLEXSPI_STS1_IPCMDERRCODE_SHIFT)); -} - -/*! @brief Gets the error code when AHB command error detected. - * - * @param base FLEXSPI peripheral base address. - * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected. - * @retval error code when AHB command error detected. - */ -static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index) -{ - *index = (uint8_t)(base->STS1 & FLEXSPI_STS1_AHBCMDERRID_MASK) >> FLEXSPI_STS1_AHBCMDERRID_SHIFT; - return (flexspi_ahb_error_code_t)( - (uint32_t)((base->STS1 & FLEXSPI_STS1_AHBCMDERRCODE_MASK) >> FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)); -} - -/*! @brief Returns whether the bus is idle. - * - * @param base FLEXSPI peripheral base address. - * @retval true Bus is idle. - * @retval false Bus is busy. - */ -static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base) -{ - return (0U != (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK)) && (0U != (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)); -} -/*@}*/ - -/*! - * @name Bus Operations - * @{ - */ - -/*! @brief Update read sample clock source - * - * @param base FLEXSPI peripheral base address. - * @param clockSource clockSource of type #flexspi_read_sample_clock_t - */ -void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource); - -#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_IPCR1_IPAREN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_IPCR1_IPAREN)) -/*! @brief Enables/disables the FLEXSPI IP command parallel mode. - * - * @param base FLEXSPI peripheral base address. - * @param enable True means enable parallel mode, false means disable parallel mode. - */ -static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable) -{ - if (enable) - { - base->IPCR1 |= FLEXSPI_IPCR1_IPAREN_MASK; - } - else - { - base->IPCR1 &= ~FLEXSPI_IPCR1_IPAREN_MASK; - } -} -#endif - -#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_AHBCR_APAREN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_AHBCR_APAREN)) -/*! @brief Enables/disables the FLEXSPI AHB command parallel mode. - * - * @param base FLEXSPI peripheral base address. - * @param enable True means enable parallel mode, false means disable parallel mode. - */ -static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable) -{ - if (enable) - { - base->AHBCR |= FLEXSPI_AHBCR_APAREN_MASK; - } - else - { - base->AHBCR &= ~FLEXSPI_AHBCR_APAREN_MASK; - } -} -#endif - -/*! @brief Updates the LUT table. - * - * @param base FLEXSPI peripheral base address. - * @param index From which index start to update. It could be any index of the LUT table, which - * also allows user to update command content inside a command. Each command consists of up to - * 8 instructions and occupy 4*32-bit memory. - * @param cmd Command sequence array. - * @param count Number of sequences. - */ -void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count); - -/*! - * @brief Writes data into FIFO. - * - * @param base FLEXSPI peripheral base address - * @param data The data bytes to send - * @param fifoIndex Destination fifo index. - */ -static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex) -{ - base->TFDR[fifoIndex] = data; -} - -/*! - * @brief Receives data from data FIFO. - * - * @param base FLEXSPI peripheral base address - * @param fifoIndex Source fifo index. - * @return The data in the FIFO. - */ -static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex) -{ - return base->RFDR[fifoIndex]; -} - -/*! - * @brief Sends a buffer of data bytes using blocking method. - * @note This function blocks via polling until all bytes have been sent. - * @param base FLEXSPI peripheral base address - * @param buffer The data bytes to send - * @param size The number of data bytes to send - * @retval kStatus_Success write success without error - * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout - * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected - * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected - */ -status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size); - -/*! - * @brief Receives a buffer of data bytes using a blocking method. - * @note This function blocks via polling until all bytes have been sent. - * @param base FLEXSPI peripheral base address - * @param buffer The data bytes to send - * @param size The number of data bytes to receive - * @retval kStatus_Success read success without error - * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout - * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected - * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected - */ -status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size); - -/*! - * @brief Execute command to transfer a buffer data bytes using a blocking method. - * @param base FLEXSPI peripheral base address - * @param xfer pointer to the transfer structure. - * @retval kStatus_Success command transfer success without error - * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout - * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected - * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected - */ -status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer); -/*! @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the FLEXSPI handle which is used in transactional functions. - * - * @param base FLEXSPI peripheral base address. - * @param handle pointer to flexspi_handle_t structure to store the transfer state. - * @param callback pointer to user callback function. - * @param userData user parameter passed to the callback function. - */ -void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, - flexspi_handle_t *handle, - flexspi_transfer_callback_t callback, - void *userData); - -/*! - * @brief Performs a interrupt non-blocking transfer on the FLEXSPI bus. - * - * @note Calling the API returns immediately after transfer initiates. The user needs - * to call FLEXSPI_GetTransferCount to poll the transfer status to check whether - * the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer - * is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark level, or - * FLEXSPI could not read data properly. - * - * @param base FLEXSPI peripheral base address. - * @param handle pointer to flexspi_handle_t structure which stores the transfer state. - * @param xfer pointer to flexspi_transfer_t structure. - * @retval kStatus_Success Successfully start the data transmission. - * @retval kStatus_FLEXSPI_Busy Previous transmission still not finished. - */ -status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer); - -/*! - * @brief Gets the master transfer status during a interrupt non-blocking transfer. - * - * @param base FLEXSPI peripheral base address. - * @param handle pointer to flexspi_handle_t structure which stores the transfer state. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_InvalidArgument count is Invalid. - * @retval kStatus_Success Successfully return the count. - */ -status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count); - -/*! - * @brief Aborts an interrupt non-blocking transfer early. - * - * @note This API can be called at any time when an interrupt non-blocking transfer initiates - * to abort the transfer early. - * - * @param base FLEXSPI peripheral base address. - * @param handle pointer to flexspi_handle_t structure which stores the transfer state - */ -void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle); - -/*! - * @brief Master interrupt handler. - * - * @param base FLEXSPI peripheral base address. - * @param handle pointer to flexspi_handle_t structure. - */ -void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle); -/*! @} */ - -#if defined(__cplusplus) -} -#endif /*_cplusplus. */ -/*@}*/ - -#endif /* __FSL_FLEXSPI_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi_dma.c deleted file mode 100644 index 7a06f6fc540..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi_dma.c +++ /dev/null @@ -1,646 +0,0 @@ -/* - * Copyright 2019-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_flexspi_dma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexspi_dma" -#endif - -/* FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE) ? \ - FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE : \ - FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE) -#endif -#if defined(__ICCARM__) -#pragma data_alignment = FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE -static dma_descriptor_t s_flexspiDes[FLEXSPI_DMA_DES_COUNT]; -#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) -__attribute__(( - aligned(FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE))) static dma_descriptor_t s_flexspiDes[FLEXSPI_DMA_DES_COUNT]; -#elif defined(__GNUC__) -__attribute__(( - aligned(FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE))) static dma_descriptor_t s_flexspiDes[FLEXSPI_DMA_DES_COUNT]; -#endif -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief FLEXSPI DMA transfer finished callback function. - * - * This function is called when FLEXSPI DMA transfer finished. It disables the FLEXSPI - * TX/RX DMA request and sends status to FLEXSPI callback. - * - * @param handle The DMA handle. - * @param param Callback function parameter. - */ -static void FLEXSPI_TransferDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t tcds); - -/*! - * @brief FLEXSPI Write DMA data. - * - * This function is called in FLEXSPI DMA transfer. It configures Write DMA and prepare DMA data transfer. - * - * @param base FLEXSPI peripheral base address. - * @param handle The DMA handle. - * @param data pointer to data buffer which stores the transmit data - * @param dataSize size for transmit data buffer . - */ -static status_t FLEXSPI_WriteDataDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle, uint32_t *data, size_t dataSize); - -/*! - * @brief FLEXSPI Read DMA data. - * - * This function is called in FLEXSPI DMA transfer. It configures Read DMA and prepare DMA data transfer. - * - * @param base FLEXSPI peripheral base address. - * @param handle The DMA handle. - * @param data pointer to data buffer which stores the receive data - * @param dataSize size for receive data buffer . - */ -static status_t FLEXSPI_ReadDataDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle, uint32_t *data, size_t dataSize); -/******************************************************************************* - * Code - ******************************************************************************/ -#if !(defined(FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES) && FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES) -static uint8_t FLEXSPI_CalculatePower(uint8_t value) -{ - uint8_t power = 0; - while (value >> 1 != 0U) - { - power++; - value = value >> 1; - } - - return power; -} -#endif - -static void FLEXSPI_TransferDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) -{ - flexspi_dma_private_handle_t *flexspiPrivateHandle = (flexspi_dma_private_handle_t *)param; - - /* Avoid warning for unused parameters. */ - handle = handle; - tcds = tcds; - - if (transferDone) - { - /* Wait for bus idle. */ - while (!FLEXSPI_GetBusIdleStatus(flexspiPrivateHandle->base)) - { - } - /* Disable transfer. */ - FLEXSPI_TransferAbortDMA(flexspiPrivateHandle->base, flexspiPrivateHandle->handle); - - if (flexspiPrivateHandle->handle->completionCallback != NULL) - { - flexspiPrivateHandle->handle->completionCallback(flexspiPrivateHandle->base, flexspiPrivateHandle->handle, - kStatus_Success, flexspiPrivateHandle->handle->userData); - } - } -} - -static status_t FLEXSPI_WriteDataDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle, uint32_t *data, size_t dataSize) -{ - void *txFifoBase = (void *)(uint32_t *)FLEXSPI_GetTxFifoAddress(base); - void *nextDesc = NULL; - dma_channel_trigger_t dmaTxTriggerConfig; - dma_channel_config_t txChannelConfig; - uint32_t bytesPerDes; - uint8_t desCount; - uint8_t remains; - uint32_t srcInc; - uint32_t dstInc; - - /* Source address interleave size */ - srcInc = kDMA_AddressInterleave1xWidth; - /* Destination address interleave size */ - dstInc = kDMA_AddressInterleave1xWidth; - - /* Check the xfer->data start address follows the alignment */ - if (((uint32_t)data & ((uint32_t)handle->nsize - 1U)) != 0U) - { - return kStatus_InvalidArgument; - } - - handle->count = - 8U * ((uint8_t)(((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1U)); - - /* Check the handle->count is power of 2 */ - if (((handle->count) & (handle->count - 1U)) != 0U) - { - return kStatus_InvalidArgument; - } - -#if defined(FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES) && FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES - if (dataSize < handle->count) - { - handle->nsize = kFLEXPSI_DMAnSize1Bytes; - handle->nbytes = (uint8_t)dataSize; - } - else - { - /* Store the initially configured dma minor byte transfer count into the FLEXSPI handle */ - handle->nbytes = handle->count; - } - - handle->transferSize = dataSize; - dmaTxTriggerConfig.burst = kDMA_SingleTransfer; - dmaTxTriggerConfig.type = kDMA_HighLevelTrigger; - dmaTxTriggerConfig.wrap = kDMA_NoWrap; - - /* Configure linked descriptors to start FLEXSPI Tx DMA transfer to provide software workaround for - ERRATA FLEXSPI.1: Using FLEXSPI register interface, TX buffer fill / RX buffer drain by DMA with a - single DMA descriptor cannot be performed. */ - desCount = (uint8_t)(dataSize / (uint32_t)handle->nbytes); - bytesPerDes = handle->nbytes; - remains = (uint8_t)(dataSize - (uint32_t)desCount * (uint32_t)handle->nbytes); - if (remains > 0U) - { - uint32_t width = (uint32_t)kFLEXPSI_DMAnSize1Bytes; - DMA_SetupDescriptor(&s_flexspiDes[desCount - 1U], - DMA_CHANNEL_XFER(false, true, true, false, width, srcInc, dstInc, remains), - (void *)(uint64_t *)((uint32_t)data + desCount * bytesPerDes), txFifoBase, NULL); - nextDesc = &s_flexspiDes[desCount - 1U]; - } - - remains = (uint8_t)bytesPerDes; -#else - uint32_t dmaTriggerBurst; - dmaTxTriggerConfig.type = kDMA_RisingEdgeTrigger; - bytesPerDes = dataSize; - - if (dataSize < handle->count) - { - handle->nsize = kFLEXPSI_DMAnSize1Bytes; - handle->nbytes = (uint8_t)(dataSize / (uint32_t)handle->nsize); - dmaTxTriggerConfig.wrap = kDMA_NoWrap; - - /* Check the handle->nbytes is power of 2 */ - if (((handle->nbytes) & (handle->nbytes - 1U)) != 0U) - { - handle->nbytes = 2U * ((handle->nbytes) & (handle->nbytes - 1U)); - } - - desCount = 1U; - } - else - { - dmaTxTriggerConfig.wrap = kDMA_DstWrap; - remains = (uint8_t)(dataSize % (uint32_t)handle->count); - if (remains == 0U) - { - desCount = 1U; - } - else - { - desCount = 2U; - bytesPerDes = dataSize - remains; - if ((remains & 3U) == 0U) - { - handle->nsize = kFLEXPSI_DMAnSize4Bytes; - } - else if ((remains & 1U) == 0U) - { - handle->nsize = kFLEXPSI_DMAnSize2Bytes; - } - else - { - handle->nsize = kFLEXPSI_DMAnSize1Bytes; - } - } - /* Store the initially configured dma minor byte transfer count into the FLEXSPI handle */ - handle->nbytes = handle->count / (uint8_t)handle->nsize; - - /* Check if dataSize exceeds the maximum transfer count supported by the driver. */ - if ((dataSize - handle->count + 1U) / ((uint32_t)handle->nsize) > 1024U) - { - return kStatus_InvalidArgument; - } - } - - /* xfer->dataSize needs to be larger than 1 due to hardware limitation */ - if (dataSize / (uint8_t)handle->nsize == 1U) - { - return kStatus_InvalidArgument; - } - - dmaTriggerBurst = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(FLEXSPI_CalculatePower(handle->nbytes)); - dmaTxTriggerConfig.burst = (dma_trigger_burst_t)dmaTriggerBurst; - handle->transferSize = dataSize; -#endif - - for (uint8_t i = desCount - 1U; i > 0U; i--) - { - DMA_SetupDescriptor(&s_flexspiDes[i - 1U], - DMA_CHANNEL_XFER((nextDesc == NULL) ? false : true, true, (nextDesc == NULL) ? true : false, - false, (uint32_t)handle->nsize, srcInc, dstInc, remains), - (void *)(uint64_t *)((uint32_t)data + i * bytesPerDes), txFifoBase, nextDesc); - nextDesc = &s_flexspiDes[i - 1U]; - } - - DMA_PrepareChannelTransfer( - &txChannelConfig, (void *)data, txFifoBase, - DMA_CHANNEL_XFER((nextDesc == NULL) ? false : true, true, (nextDesc == NULL) ? true : false, false, - (uint32_t)handle->nsize, srcInc, dstInc, bytesPerDes), - kDMA_MemoryToMemory, &dmaTxTriggerConfig, nextDesc); - - (void)DMA_SubmitChannelTransfer(handle->txDmaHandle, &txChannelConfig); - - DMA_SetCallback(handle->txDmaHandle, FLEXSPI_TransferDMACallback, &s_dmaPrivateHandle[FLEXSPI_GetInstance(base)]); - DMA_StartTransfer(handle->txDmaHandle); - - /* Enable FLEXSPI TX DMA. */ - FLEXSPI_EnableTxDMA(base, true); - - /* Start Transfer. */ - base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK; - - return kStatus_Success; -} - -static status_t FLEXSPI_ReadDataDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle, uint32_t *data, size_t dataSize) -{ - dma_channel_trigger_t dmaRxTriggerConfig; - void *rxFifoBase = (void *)(uint32_t *)FLEXSPI_GetRxFifoAddress(base); - void *nextDesc = NULL; - dma_channel_config_t rxChannelConfig; - uint32_t bytesPerDes; - uint8_t remains; - uint8_t desCount; - uint32_t srcInc; - uint32_t dstInc; - - /* Source address interleave size */ - srcInc = kDMA_AddressInterleave1xWidth; - /* Destination address interleave size */ - dstInc = kDMA_AddressInterleave1xWidth; - - handle->count = - 8U * (uint8_t)(((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1U); - - /* Check the watermark is power of 2U */ - if ((handle->count & (handle->count - 1U)) != 0U) - { - return kStatus_InvalidArgument; - } - -#if defined(FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES) && FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES - if (dataSize < handle->count) - { - handle->nsize = kFLEXPSI_DMAnSize1Bytes; - handle->nbytes = (uint8_t)dataSize; - } - else - { - /* Store the initially configured dma minor byte transfer count into the FLEXSPI handle */ - handle->nbytes = handle->count; - } - - dmaRxTriggerConfig.burst = kDMA_SingleTransfer; - dmaRxTriggerConfig.type = kDMA_HighLevelTrigger; - dmaRxTriggerConfig.wrap = kDMA_NoWrap; - - /* Configure linked descriptors to start FLEXSPI Tx DMA transfer to provide software workaround for - ERRATA FLEXSPI.1: Using FLEXSPI register interface, TX buffer fill / RX buffer drain by DMA with a - single DMA descriptor cannot be performed. */ - desCount = (uint8_t)(dataSize / (uint32_t)handle->nbytes); - bytesPerDes = handle->nbytes; - remains = (uint8_t)(dataSize - (uint32_t)desCount * (uint32_t)handle->nbytes); - - if (remains > 0U) - { - uint32_t width = (uint32_t)kFLEXPSI_DMAnSize1Bytes; - DMA_SetupDescriptor(&s_flexspiDes[desCount - 1U], - DMA_CHANNEL_XFER(false, true, true, false, width, srcInc, dstInc, remains), rxFifoBase, - (void *)(uint64_t *)((uint32_t)data + desCount * bytesPerDes), NULL); - nextDesc = &s_flexspiDes[desCount - 1U]; - } - remains = (uint8_t)bytesPerDes; - -#else - uint32_t dmaTriggerBurst; - dmaRxTriggerConfig.type = kDMA_RisingEdgeTrigger; - bytesPerDes = dataSize; - - if (dataSize < handle->count) - { - handle->nsize = kFLEXPSI_DMAnSize1Bytes; - handle->nbytes = (uint8_t)(dataSize / (uint32_t)handle->nsize); - dmaRxTriggerConfig.wrap = kDMA_NoWrap; - /* Check the handle->nbytes is power of 2 */ - if (((handle->nbytes) & (handle->nbytes - 1U)) != 0U) - { - handle->nbytes = 2U * ((handle->nbytes) & (handle->nbytes - 1U)); - } - desCount = 1U; - } - else - { - dmaRxTriggerConfig.wrap = kDMA_SrcWrap; - remains = (uint8_t)(dataSize % (uint32_t)handle->count); - if (remains == 0U) - { - desCount = 1U; - } - else - { - desCount = 2U; - bytesPerDes = dataSize - remains; - if ((remains & 3U) == 0U) - { - handle->nsize = kFLEXPSI_DMAnSize4Bytes; - } - else if ((remains & 1U) == 0U) - { - handle->nsize = kFLEXPSI_DMAnSize2Bytes; - } - else - { - handle->nsize = kFLEXPSI_DMAnSize1Bytes; - } - } - /* Store the initially configured dma minor byte transfer count into the FLEXSPI handle */ - handle->nbytes = handle->count / (uint8_t)handle->nsize; - - /* Check dataSize exceeds the maximum transfer count supported by the driver. */ - if ((dataSize - handle->count + 1U) / ((uint32_t)handle->nsize) > 1024U) - { - return kStatus_InvalidArgument; - } - } - - dmaTriggerBurst = - DMA_CHANNEL_CFG_TRIGBURST(1U) | DMA_CHANNEL_CFG_BURSTPOWER(FLEXSPI_CalculatePower(handle->nbytes)); - dmaRxTriggerConfig.burst = (dma_trigger_burst_t)(dmaTriggerBurst); -#endif - - for (uint8_t i = desCount - 1U; i > 0U; i--) - { - DMA_SetupDescriptor(&s_flexspiDes[i - 1U], - DMA_CHANNEL_XFER((nextDesc == NULL) ? false : true, true, (nextDesc == NULL) ? true : false, - false, (uint32_t)handle->nsize, srcInc, dstInc, remains), - rxFifoBase, (void *)(uint64_t *)((uint32_t)data + i * bytesPerDes), nextDesc); - nextDesc = &s_flexspiDes[i - 1U]; - } - - DMA_PrepareChannelTransfer( - &rxChannelConfig, rxFifoBase, (void *)data, - DMA_CHANNEL_XFER((nextDesc == NULL) ? false : true, true, (nextDesc == NULL) ? true : false, false, - (uint32_t)handle->nsize, srcInc, dstInc, bytesPerDes), - kDMA_MemoryToMemory, &dmaRxTriggerConfig, nextDesc); - - (void)DMA_SubmitChannelTransfer(handle->rxDmaHandle, &rxChannelConfig); - - DMA_SetCallback(handle->rxDmaHandle, FLEXSPI_TransferDMACallback, &s_dmaPrivateHandle[FLEXSPI_GetInstance(base)]); - DMA_StartTransfer(handle->rxDmaHandle); - - /* Enable FLEXSPI RX DMA. */ - FLEXSPI_EnableRxDMA(base, true); - - /* Start Transfer. */ - base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK; - - return kStatus_Success; -} - -/*! - * brief Initializes the FLEXSPI handle for transfer which is used in transactional functions and set the callback. - * - * param base FLEXSPI peripheral base address - * param handle Pointer to flexspi_dma_handle_t structure - * param callback FLEXSPI callback, NULL means no callback. - * param userData User callback function data. - * param txDmaHandle User requested DMA handle for TX DMA transfer. - * param rxDmaHandle User requested DMA handle for RX DMA transfer. - */ -void FLEXSPI_TransferCreateHandleDMA(FLEXSPI_Type *base, - flexspi_dma_handle_t *handle, - flexspi_dma_callback_t callback, - void *userData, - dma_handle_t *txDmaHandle, - dma_handle_t *rxDmaHandle) -{ - assert(handle); - - uint32_t instance = FLEXSPI_GetInstance(base); - - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - (void)memset(handle, 0, sizeof(*handle)); - - handle->state = kFLEXSPI_Idle; - handle->txDmaHandle = txDmaHandle; - handle->rxDmaHandle = rxDmaHandle; - handle->nsize = kFLEXPSI_DMAnSize4Bytes; - - handle->completionCallback = callback; - handle->userData = userData; -} - -/*! - * brief Update FLEXSPI DMA transfer source data transfer size(SSIZE) and destination data transfer size(DSIZE). - * - * param base FLEXSPI peripheral base address - * param handle Pointer to flexspi_dma_handle_t structure - * param nsize FLEXSPI DMA transfer data transfer size(SSIZE/DSIZE), by default the size is - * kFLEXPSI_DMAnSize1Bytes(one byte). - * see flexspi_dma_transfer_nsize_t . - */ -void FLEXSPI_TransferUpdateSizeDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle, flexspi_dma_transfer_nsize_t nsize) -{ - handle->nsize = nsize; -} - -/*! - * brief Transfers FLEXSPI data using an dma non-blocking method. - * - * This function writes/receives data to/from the FLEXSPI transmit/receive FIFO. This function is non-blocking. - * param base FLEXSPI peripheral base address. - * param handle Pointer to flexspi_dma_handle_t structure - * param xfer FLEXSPI transfer structure. - * retval kStatus_FLEXSPI_Busy FLEXSPI is busy transfer. - * retval kStatus_InvalidArgument The watermark configuration is invalid, the watermark should be power of - 2 to do successfully DMA transfer. - * retval kStatus_Success FLEXSPI successfully start dma transfer. - */ -status_t FLEXSPI_TransferDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle, flexspi_transfer_t *xfer) -{ - uint32_t configValue = 0; - status_t result = kStatus_Success; - - assert(handle); - assert(xfer); - - /* Check if the FLEXSPI bus is idle - if not return busy status. */ - if (handle->state != (uint32_t)kFLEXSPI_Idle) - { - result = kStatus_FLEXSPI_Busy; - } - else - { - handle->transferSize = xfer->dataSize; - - /* Clear sequence pointer before sending data to external devices. */ - base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK; - - /* Clear former pending status before start this transfer. */ - base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | - FLEXSPI_INTR_IPCMDGE_MASK; - - /* Configure base address. */ - base->IPCR0 = xfer->deviceAddress; - - /* Reset fifos. */ - base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; - base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; - - /* Configure data size. */ - if ((xfer->cmdType == kFLEXSPI_Read) || (xfer->cmdType == kFLEXSPI_Write)) - { - configValue = FLEXSPI_IPCR1_IDATSZ(xfer->dataSize); - } - - /* Configure sequence ID. */ - configValue |= FLEXSPI_IPCR1_ISEQID(xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM((uint32_t)xfer->SeqNumber - 1U); - base->IPCR1 = configValue; - - if ((xfer->cmdType == kFLEXSPI_Write) || (xfer->cmdType == kFLEXSPI_Config)) - { - handle->state = kFLEXSPI_Busy; - result = FLEXSPI_WriteDataDMA(base, handle, xfer->data, xfer->dataSize); - } - else if (xfer->cmdType == kFLEXSPI_Read) - { - handle->state = kFLEXSPI_Busy; - result = FLEXSPI_ReadDataDMA(base, handle, xfer->data, xfer->dataSize); - } - else - { - /* Start Transfer. */ - base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK; - /* Wait for bus idle. */ - while (!FLEXSPI_GetBusIdleStatus(base)) - { - } - result = FLEXSPI_CheckAndClearError(base, base->INTR); - - handle->state = kFLEXSPI_Idle; - - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } - } - - return result; -} - -/*! - * brief Aborts the transfer data using dma. - * - * This function aborts the transfer data using dma. - * - * param base FLEXSPI peripheral base address. - * param handle Pointer to flexspi_dma_handle_t structure - */ -void FLEXSPI_TransferAbortDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle) -{ - assert(handle != NULL); - - if ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXDMAEN_MASK) != 0x00U) - { - FLEXSPI_EnableTxDMA(base, false); - DMA_AbortTransfer(handle->txDmaHandle); - } - - if ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXDMAEN_MASK) != 0x00U) - { - FLEXSPI_EnableRxDMA(base, false); - DMA_AbortTransfer(handle->rxDmaHandle); - } - - handle->state = kFLEXSPI_Idle; -} - -status_t FLEXSPI_TransferGetTransferCountDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle, size_t *count) -{ - assert(handle); - assert(count); - - status_t result = kStatus_Success; - - if (handle->state != (uint32_t)kFLEXSPI_Busy) - { - result = kStatus_NoTransferInProgress; - } - else - { - if ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXDMAEN_MASK) != 0x00U) - { - *count = - (handle->transferSize - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel)); - } - else if ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXDMAEN_MASK) != 0x00U) - { - *count = - (handle->transferSize - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel)); - } - else - { - ; /* Intentional empty for MISRA C-2012 rule 15.7. */ - } - } - - return result; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi_dma.h deleted file mode 100644 index 7ad6ba7a8a8..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi_dma.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright 2019-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_FLEXSPI_DMA_H_ -#define _FSL_FLEXSPI_DMA_H_ - -#include "fsl_flexspi.h" -#include "fsl_dma.h" - -/*! - * @addtogroup flexspi_dma - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FLEXSPI DMA driver version. */ -#define FSL_FLEXSPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 5)) -/*@}*/ - -typedef struct _flexspi_dma_handle flexspi_dma_handle_t; - -/*! @brief FLEXSPI dma transfer callback function for finish and error */ -typedef void (*flexspi_dma_callback_t)(FLEXSPI_Type *base, - flexspi_dma_handle_t *handle, - status_t status, - void *userData); - -/*! @brief dma transfer configuration */ -typedef enum _flexspi_dma_ntransfer_size -{ - kFLEXPSI_DMAnSize1Bytes = 0x1U, /*!< Source/Destination data transfer size is 1 byte every time */ - kFLEXPSI_DMAnSize2Bytes = 0x2U, /*!< Source/Destination data transfer size is 2 bytes every time */ - kFLEXPSI_DMAnSize4Bytes = 0x4U, /*!< Source/Destination data transfer size is 4 bytes every time */ -} flexspi_dma_transfer_nsize_t; - -/*! @brief FLEXSPI DMA transfer handle, users should not touch the content of the handle.*/ -struct _flexspi_dma_handle -{ - dma_handle_t *txDmaHandle; /*!< dma handler for FLEXSPI Tx. */ - dma_handle_t *rxDmaHandle; /*!< dma handler for FLEXSPI Rx. */ - size_t transferSize; /*!< Bytes need to transfer. */ - flexspi_dma_transfer_nsize_t nsize; /*!< dma SSIZE/DSIZE in each transfer. */ - uint8_t nbytes; /*!< dma minor byte transfer count initially configured. */ - uint8_t count; /*!< The transfer data count in a DMA request. */ - uint32_t state; /*!< Internal state for FLEXSPI dma transfer. */ - flexspi_dma_callback_t completionCallback; /*!< A callback function called after the dma transfer is finished. */ - void *userData; /*!< User callback parameter */ -}; - -/******************************************************************************* - * APIs - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name FLEXSPI dma Transactional - * @{ - */ - -/*! - * @brief Initializes the FLEXSPI handle for transfer which is used in transactional functions and set the callback. - * - * @param base FLEXSPI peripheral base address - * @param handle Pointer to flexspi_dma_handle_t structure - * @param callback FLEXSPI callback, NULL means no callback. - * @param userData User callback function data. - * @param txDmaHandle User requested DMA handle for TX DMA transfer. - * @param rxDmaHandle User requested DMA handle for RX DMA transfer. - */ -void FLEXSPI_TransferCreateHandleDMA(FLEXSPI_Type *base, - flexspi_dma_handle_t *handle, - flexspi_dma_callback_t callback, - void *userData, - dma_handle_t *txDmaHandle, - dma_handle_t *rxDmaHandle); - -/*! - * @brief Update FLEXSPI DMA transfer source data transfer size(SSIZE) and destination data transfer size(DSIZE). - * - * @param base FLEXSPI peripheral base address - * @param handle Pointer to flexspi_dma_handle_t structure - * @param nsize FLEXSPI DMA transfer data transfer size(SSIZE/DSIZE), by default the size is - * kFLEXPSI_DMAnSize1Bytes(one byte). - * @see flexspi_dma_transfer_nsize_t . - */ -void FLEXSPI_TransferUpdateSizeDMA(FLEXSPI_Type *base, - flexspi_dma_handle_t *handle, - flexspi_dma_transfer_nsize_t nsize); - -/*! - * @brief Transfers FLEXSPI data using an dma non-blocking method. - * - * This function writes/receives data to/from the FLEXSPI transmit/receive FIFO. This function is non-blocking. - * @param base FLEXSPI peripheral base address. - * @param handle Pointer to flexspi_dma_handle_t structure - * @param xfer FLEXSPI transfer structure. - * @retval kStatus_FLEXSPI_Busy FLEXSPI is busy transfer. - * @retval kStatus_InvalidArgument The watermark configuration is invalid, the watermark should be power of - 2 to do successfully DMA transfer. - * @retval kStatus_Success FLEXSPI successfully start dma transfer. - */ -status_t FLEXSPI_TransferDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle, flexspi_transfer_t *xfer); - -/*! - * @brief Aborts the transfer data using dma. - * - * This function aborts the transfer data using dma. - * - * @param base FLEXSPI peripheral base address. - * @param handle Pointer to flexspi_dma_handle_t structure - */ -void FLEXSPI_TransferAbortDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle); - -/*! - * @brief Gets the transferred counts of transfer. - * - * @param base FLEXSPI peripheral base address. - * @param handle Pointer to flexspi_dma_handle_t structure. - * @param count Bytes transfer. - * @retval kStatus_Success Succeed get the transfer count. - * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. - */ -status_t FLEXSPI_TransferGetTransferCountDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle, size_t *count); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/* @} */ - -#endif /* _FSL_FLEXSPI_DMA_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_freqme.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_freqme.c deleted file mode 100644 index 709bc80f2f0..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_freqme.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright 2021 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_freqme.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_freqme" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -static uint32_t FREQME_GetInstance(FREQME_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Array to map freqme instance number to base address. */ -static FREQME_Type *const s_freqmeBases[] = FREQME_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to FREQME clocks for each instance. */ -static const clock_ip_name_t s_freqmeClocks[] = FREQME_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t FREQME_GetInstance(FREQME_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0U; instance < ARRAY_SIZE(s_freqmeBases); instance++) - { - if (s_freqmeBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_freqmeBases)); - - return instance; -} - -/*! - * brief Initialize freqme module, set operate mode, operate mode attribute and initialize measurement cycle. - * - * param base FREQME peripheral base address. - * param config The pointer to module basic configuration, please refer to freq_measure_config_t. - */ -void FREQME_Init(FREQME_Type *base, const freq_measure_config_t *config) -{ - assert(config); - - uint32_t tmp32 = 0UL; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable FREQME clock. */ - CLOCK_EnableClock(s_freqmeClocks[FREQME_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - if (config->startMeasurement) - { - tmp32 |= FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_MASK; - } - tmp32 |= FREQME_FREQMECTRL_W_CONTINUOUS_MODE_EN(config->enableContinuousMode) | - FREQME_FREQMECTRL_W_PULSE_MODE(config->operateMode); - if (config->operateMode == kFREQME_FreqMeasurementMode) - { - tmp32 |= FREQME_FREQMECTRL_W_REF_SCALE(config->operateModeAttribute.refClkScaleFactor); - } - else - { - tmp32 |= FREQME_FREQMECTRL_W_PULSE_POL(config->operateModeAttribute.pulsePolarity); - } - - base->FREQMECTRL_W = tmp32; -} - -/*! - * brief Get default configuration. - * - * code - * config->operateMode = kFREQME_FreqMeasurementMode; - * config->operateModeAttribute.refClkScaleFactor = 0U; - * config->enableContinuousMode = false; - * config->startMeasurement = false; - * endcode - * - * param config The pointer to module basic configuration, please refer to freq_measure_config_t. - */ -void FREQME_GetDefaultConfig(freq_measure_config_t *config) -{ - assert(config); - - (void)memset(config, 0, sizeof(*config)); - - config->operateMode = kFREQME_FreqMeasurementMode; - config->operateModeAttribute.refClkScaleFactor = 0U; - config->enableContinuousMode = false; - config->startMeasurement = false; -} - -/*! - * brief Calculate the frequency of selected target clock. - * - * note The formula: Ftarget = (RESULT - 2) * Freference / 2 ^ REF_SCALE. - * - * note This function only useful when the operate mode is selected as frequency measurement mode. - * - * param base FREQME peripheral base address. - * param refClkFrequency The frequency of reference clock. - * return The frequency of target clock, if the output result is 0, please check the module's operate mode. - */ -uint32_t FREQME_CalculateTargetClkFreq(FREQME_Type *base, uint32_t refClkFrequency) -{ - uint64_t measureResult = 0ULL; - uint32_t targetFreq = 0ULL; - uint64_t tmp64 = 0ULL; - - while ((base->FREQMECTRL_R & FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_MASK) != 0UL) - { - } - - if (!FREQME_CheckOperateMode(base)) - { - measureResult = (uint64_t)(base->FREQMECTRL_R & FREQME_FREQMECTRL_R_RESULT_MASK); - tmp64 = (measureResult - 2ULL) * (uint64_t)refClkFrequency; - targetFreq = (uint32_t)(tmp64 / (1UL << (uint32_t)FREQME_GetReferenceClkScaleValue(base))); - } - - return targetFreq; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_freqme.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_freqme.h deleted file mode 100644 index dae1c2b81ee..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_freqme.h +++ /dev/null @@ -1,440 +0,0 @@ -/* - * Copyright 2021 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_FREQME_ -#define _FSL_FREQME_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_freqme - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FREQME driver version 2.0.0. */ -#define FSL_FREQME_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! - * @brief The enumeration of interrupt status flags. - * @anchor _freqme_interrupt_status_flags - */ -enum _freqme_interrupt_status_flags -{ - kFREQME_UnderflowInterruptStatusFlag = FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK, /*!< Indicate the measurement is - just done and the result is less - than minimun value. */ - kFREQME_OverflowInterruptStatusFlag = FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK, /*!< Indicate the measurement is - just done and the result is greater - than maximum value. */ - kFREQME_ReadyInterruptStatusFlag = FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK, /*!< Indicate the measurement is - just done and the result is ready to - read. */ - kFREQME_AllInterruptStatusFlags = FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | - FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK, /*!< All interrupt - status flags. */ -}; - -/*! - * @brief The enumeration of interrupts, including underflow interrupt, overflow interrupt, - * and result ready interrupt. - * @anchor _freqme_interrupt_enable - */ -enum _freqme_interrupt_enable -{ - kFREQME_UnderflowInterruptEnable = FREQME_FREQMECTRL_W_LT_MIN_INT_EN_MASK, /*!< Enable interrupt when the result is - less than minimum value. */ - kFREQME_OverflowInterruptEnable = FREQME_FREQMECTRL_W_GT_MAX_INT_EN_MASK, /*!< Enable interrupt when the result is - greater than maximum value. */ - kFREQME_ReadyInterruptEnable = FREQME_FREQMECTRL_W_RESULT_READY_INT_EN_MASK, /*!< Enable interrupt when a - measurement completes and the result - is ready. */ -}; - -/*! - * @brief FREQME module operate mode enumeration, including frequency measurement mode - * and pulse width measurement mode. - */ -typedef enum _freqme_operate_mode -{ - kFREQME_FreqMeasurementMode = 0U, /*!< The module works in the frequency measurement mode. */ - kFREOME_PulseWidthMeasurementMode, /*!< The module works in the pulse width measurement mode. */ -} freqme_operate_mode_t; - -/*! - * @brief The enumeration of pulse polarity. - */ -typedef enum _freqme_pulse_polarity -{ - kFREQME_PulseHighPeriod = 0U, /*!< Select high period of the reference clock. */ - kFREQME_PulseLowPeriod, /*!< Select low period of the reference clock. */ -} freqme_pulse_polarity_t; - -/*! - * @brief The union of operate mode attribute. - * @note If the operate mode is selected as frequency measurement mode the member \b refClkScaleFactor should be used, - * if the operate mode is selected as pulse width measurement mode the member \b pulsePolarity should be used. - */ -typedef union _freqme_mode_attribute -{ - uint8_t refClkScaleFactor; /*!< Only useful in frequency measurement operate mode, - used to set the reference clock counter scaling factor. */ - freqme_pulse_polarity_t pulsePolarity; /*!< Only Useful in pulse width measurement operate mode, - used to set period polarity. */ -} freqme_mode_attribute_t; - -/*! - * @brief The structure of freqme module basic configuration, - * including operate mode, operate mode attribute and so on. - */ -typedef struct _freq_measure_config -{ - freqme_operate_mode_t operateMode; /*!< Select operate mode, please refer to @ref freqme_operate_mode_t. */ - freqme_mode_attribute_t operateModeAttribute; /*!< Used to set the attribute of the selected operate mode, if - the operate mode is selected as @ref kFREQME_FreqMeasurementMode - set freqme_mode_attribute_t::refClkScaleFactor, if operate mode is - selected as @ref kFREOME_PulseWidthMeasurementMode, please set - freqme_mode_attribute_t::pulsePolarity. */ - - bool enableContinuousMode; /*!< Enable/disable continuous mode, if continuous mode is enable, - the measurement is performed continuously and the result for the - last completed measurement is available in the result register. */ - bool startMeasurement; -} freq_measure_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Basic Control APIs - * @{ - */ -/*! - * @brief Initialize freqme module, set operate mode, operate mode attribute and initialize measurement cycle. - * - * @param base FREQME peripheral base address. - * @param config The pointer to module basic configuration, please refer to @ref freq_measure_config_t. - */ -void FREQME_Init(FREQME_Type *base, const freq_measure_config_t *config); - -/*! - * @brief Get default configuration. - * - * @code - * config->operateMode = kFREQME_FreqMeasurementMode; - * config->operateModeAttribute.refClkScaleFactor = 0U; - * config->enableContinuousMode = false; - * config->startMeasurement = false; - * @endcode - * - * @param config The pointer to module basic configuration, please refer to @ref freq_measure_config_t. - */ -void FREQME_GetDefaultConfig(freq_measure_config_t *config); - -/*! - * @brief Start frequency or pulse width measurement process. - * - * @param base FREQME peripheral base address. - */ -static inline void FREQME_StartMeasurementCycle(FREQME_Type *base) -{ - uint32_t tmp32; - - tmp32 = base->FREQMECTRLSTAT; - tmp32 &= ~(FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_MEASURE_IN_PROGRESS_MASK | - FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK); - tmp32 |= FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_MASK; - base->FREQMECTRL_W = tmp32; -} - -/*! - * @brief Force the termination of any measurement cycle currently in progress and resets RESULT or just reset - * RESULT if the module in idle state. - * - * @param base FREQME peripheral base address. - */ -static inline void FREQME_TerminateMeasurementCycle(FREQME_Type *base) -{ - uint32_t tmp32; - - tmp32 = base->FREQMECTRLSTAT; - tmp32 &= ~(FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_MEASURE_IN_PROGRESS_MASK | - FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK); - base->FREQMECTRL_W = tmp32; -} - -/*! - * @brief Enable/disable Continuous mode. - * - * @param base FREQME peripheral base address. - * @param enable Used to enable/disable continuous mode, - * - \b true Enable Continuous mode. - * - \b false Disable Continuous mode. - */ -static inline void FREQME_EnableContinuousMode(FREQME_Type *base, bool enable) -{ - uint32_t tmp32; - - tmp32 = base->FREQMECTRLSTAT; - tmp32 &= ~(FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_CONTINUOUS_MODE_EN_MASK | - FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK); - if (enable) - { - tmp32 |= FREQME_FREQMECTRL_W_CONTINUOUS_MODE_EN_MASK; - } - - base->FREQMECTRL_W = tmp32; -} - -/*! - * @brief Check whether continuous mode is enabled. - * - * @param base FREQME peripheral base address. - * @retval True Continuous mode is enabled, the measurement is performed continuously. - * @retval False Continuous mode is disabled. - */ -static inline bool FREQME_CheckContinuousMode(FREQME_Type *base) -{ - return (bool)((base->FREQMECTRLSTAT & FREQME_FREQMECTRLSTAT_CONTINUOUS_MODE_EN_MASK) != 0UL); -} - -/*! - * @brief Set operate mode of freqme module. - * - * @param base FREQME peripheral base address. - * @param operateMode The operate mode to be set, please refer to @ref freqme_operate_mode_t. - */ -static inline void FREQME_SetOperateMode(FREQME_Type *base, freqme_operate_mode_t operateMode) -{ - uint32_t tmp32; - - tmp32 = base->FREQMECTRLSTAT; - tmp32 &= ~(FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_PULSE_MODE_MASK | - FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK); - if (operateMode == kFREOME_PulseWidthMeasurementMode) - { - tmp32 |= FREQME_FREQMECTRL_W_PULSE_MODE_MASK; - } - - base->FREQMECTRL_W = tmp32; -} - -/*! - * @brief Check module's operate mode. - * - * @param base FREQME peripheral base address. - * @retval True Pulse width measurement mode. - * @retval False Frequency measurement mode. - */ -static inline bool FREQME_CheckOperateMode(FREQME_Type *base) -{ - return (bool)((base->FREQMECTRLSTAT & FREQME_FREQMECTRLSTAT_PULSE_MODE_MASK) != 0UL); -} - -/*! - * @brief Set the minimum expected value for the measurement result. - * - * @param base FREQME peripheral base address. - * @param minValue The minimum value to set, please note that this value is 31 bits width. - */ -static inline void FREQME_SetMinExpectedValue(FREQME_Type *base, uint32_t minValue) -{ - base->FREQMEMIN = minValue; -} - -/*! - * @brief Set the maximum expected value for the measurement result. - * - * @param base FREQME peripheral base address. - * @param maxValue The maximum value to set, please note that this value is 31 bits width. - */ -static inline void FREQME_SetMaxExpectedValue(FREQME_Type *base, uint32_t maxValue) -{ - base->FREQMEMAX = maxValue; -} - -/*! @} */ - -/*! - * @name Frequency Measurement Mode Control APIs - * @{ - */ - -/*! - * @brief Calculate the frequency of selected target clock。 - * - * @note The formula: Ftarget = (RESULT - 2) * Freference / 2 ^ REF_SCALE. - * - * @note This function only useful when the operate mode is selected as frequency measurement mode. - * - * @param base FREQME peripheral base address. - * @param refClkFrequency The frequency of reference clock. - * @return The frequency of target clock the unit is Hz, if the output result is 0, please check the module's - * operate mode. - */ -uint32_t FREQME_CalculateTargetClkFreq(FREQME_Type *base, uint32_t refClkFrequency); - -/*! - * @brief Get reference clock scaling factor. - * - * @param base FREQME peripheral base address. - * @return Reference clock scaling factor, the reference count cycle is 2 ^ ref_scale. - */ -static inline uint8_t FREQME_GetReferenceClkScaleValue(FREQME_Type *base) -{ - return (uint8_t)(base->FREQMECTRLSTAT & FREQME_FREQMECTRLSTAT_REF_SCALE_MASK); -} - -/*! @} */ - -/*! - * @name Pulse Width Measurement Mode Control APIs - * @{ - */ - -/*! - * @brief Set pulse polarity when operate mode is selected as Pulse Width Measurement mode. - * - * @param base FREQME peripheral base address. - * @param pulsePolarity The pulse polarity to be set, please refer to @ref freqme_pulse_polarity_t. - */ -static inline void FREQME_SetPulsePolarity(FREQME_Type *base, freqme_pulse_polarity_t pulsePolarity) -{ - uint32_t tmp32; - - tmp32 = base->FREQMECTRLSTAT; - tmp32 &= ~(FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_PULSE_POL_MASK | - FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK); - - if (pulsePolarity != kFREQME_PulseHighPeriod) - { - tmp32 |= FREQME_FREQMECTRL_W_PULSE_POL_MASK; - } - - base->FREQMECTRL_W = tmp32; -} - -/*! - * @brief Check pulse polarity when the operate mode is selected as pulse width measurement mode. - * - * @param base FREQME peripheral base address. - * @retval True Low period. - * @retval False High period. - */ -static inline bool FREQME_CheckPulsePolarity(FREQME_Type *base) -{ - return (bool)((base->FREQMECTRLSTAT & FREQME_FREQMECTRLSTAT_PULSE_POL_MASK) != 0UL); -} - -/*! - * @brief Get measurement result, if operate mode is selected as pulse width measurement mode this function can - * be used to calculate pulse width. - * - * @note Pulse width = counter result / Frequency of target clock. - * - * @param base FREQME peripheral base address. - * @return Measurement result. - */ -static inline uint32_t FREQME_GetMeasurementResult(FREQME_Type *base) -{ - return base->FREQMECTRL_R & FREQME_FREQMECTRL_R_RESULT_MASK; -} - -/*! @} */ - -/*! - * @name Status Control APIs - * @{ - */ - -/*! - * @brief Get interrupt status flags, such as overflow interrupt status flag, - * underflow interrupt status flag, and so on. - * - * @param base FREQME peripheral base address. - * @return Current interrupt status flags, should be the OR'ed value of @ref _freqme_interrupt_status_flags. - */ -static inline uint32_t FREQME_GetInterruptStatusFlags(FREQME_Type *base) -{ - return (base->FREQMECTRLSTAT & kFREQME_AllInterruptStatusFlags); -} - -/*! - * @brief Clear interrupt status flags. - * - * @param base FREQME peripheral base address. - * @param statusFlags The combination of interrupt status flags to clear, - * should be the OR'ed value of @ref _freqme_interrupt_status_flags. - */ -static inline void FREQME_ClearInterruptStatusFlags(FREQME_Type *base, uint32_t statusFlags) -{ - base->FREQMECTRLSTAT |= statusFlags; -} - -/*! @} */ - -/*! - * @name Interrupt Control APIs - * @{ - */ - -/*! - * @brief Enable interrupts, such as result ready interrupt, overflow interrupt and so on. - * - * @param base FREQME peripheral base address. - * @param masks The mask of interrupts to enable, should be the OR'ed value of @ref _freqme_interrupt_enable. - */ -static inline void FREQME_EnableInterrupts(FREQME_Type *base, uint32_t masks) -{ - uint32_t tmp32; - - tmp32 = base->FREQMECTRLSTAT; - tmp32 &= ~(FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_LT_MIN_INT_EN_MASK | - FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | FREQME_FREQMECTRLSTAT_GT_MAX_INT_EN_MASK | - FREQME_FREQMECTRLSTAT_RESULT_READY_INT_EN_MASK | FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK); - - tmp32 |= masks; - base->FREQMECTRL_W = tmp32; -} - -/*! - * @brief Disable interrupts, such as result ready interrupt, overflow interrupt and so on. - * - * @param base FREQME peripheral base address. - * @param masks The mask of interrupts to disable, should be the OR'ed value of @ref _freqme_interrupt_enable. - */ -static inline void FREQME_DisableInterrupts(FREQME_Type *base, uint32_t masks) -{ - uint32_t tmp32; - - tmp32 = base->FREQMECTRLSTAT; - tmp32 &= ~(FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | - FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK | masks); - - base->FREQMECTRL_W = tmp32; -} - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ -#endif /* __FSL_FREQME_H__ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_fro_calib.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_fro_calib.h deleted file mode 100644 index 9662444a526..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_fro_calib.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2017, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_FRO_CALIB_H_ -#define _FSL_FRO_CALIB_H_ - -#include "fsl_common.h" -#include "fsl_device_registers.h" -#include - -/*! - * @addtogroup power - * @{ - */ -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FRO_CALIB driver version 1.0.0. */ -#define FSL_FRO_CALIB_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) -/*@}*/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.fro_calib" -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Returns the version of the FRO Calibration library */ -unsigned int fro_calib_Get_Lib_Ver(void); - -/* ctimer instance */ -/* ctimer clock frquency in KHz */ -void Chip_TIMER_Instance_Freq(CTIMER_Type *base, unsigned int ctimerFreq); - -/* USB_SOF_Event */ -/* Application software should be written to make sure the USB_SOF_EVENT() is */ -/* being called with lower interrupt latency for calibration to work properly */ -void USB_SOF_Event(void); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* _FSL_FRO_CALIB_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gint.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gint.c deleted file mode 100644 index 9dc2e5eff0d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gint.c +++ /dev/null @@ -1,372 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_gint.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.gint" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to GINT bases for each instance. */ -static GINT_Type *const s_gintBases[FSL_FEATURE_SOC_GINT_COUNT] = GINT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Clocks for each instance. */ -static const clock_ip_name_t s_gintClocks[FSL_FEATURE_SOC_GINT_COUNT] = GINT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -/*! @brief Resets for each instance. */ -static const reset_ip_name_t s_gintResets[FSL_FEATURE_SOC_GINT_COUNT] = GINT_RSTS; -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/* @brief Irq number for each instance */ -static const IRQn_Type s_gintIRQ[FSL_FEATURE_SOC_GINT_COUNT] = GINT_IRQS; - -/*! @brief Callback function array for GINT(s). */ -static gint_cb_t s_gintCallback[FSL_FEATURE_SOC_GINT_COUNT]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t GINT_GetInstance(GINT_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_gintBases); instance++) - { - if (s_gintBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_gintBases)); - - return instance; -} - -/*! - * brief Initialize GINT peripheral. - - * This function initializes the GINT peripheral and enables the clock. - * - * param base Base address of the GINT peripheral. - * - * retval None. - */ -void GINT_Init(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - s_gintCallback[instance] = NULL; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the peripheral clock */ - CLOCK_EnableClock(s_gintClocks[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_gintResets[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -} - -/*! - * brief Setup GINT peripheral control parameters. - - * This function sets the control parameters of GINT peripheral. - * - * param base Base address of the GINT peripheral. - * param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. - * param trig Controls if the enabled inputs are level or edge sensitive based on polarity. - * param callback This function is called when configured group interrupt is generated. - * - * retval None. - */ -void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - base->CTRL = (GINT_CTRL_COMB(comb) | GINT_CTRL_TRIG(trig)); - - /* Save callback pointer */ - s_gintCallback[instance] = callback; -} - -/*! - * brief Get GINT peripheral control parameters. - - * This function returns the control parameters of GINT peripheral. - * - * param base Base address of the GINT peripheral. - * param comb Pointer to store combine input value. - * param trig Pointer to store trigger value. - * param callback Pointer to store callback function. - * - * retval None. - */ -void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback) -{ - uint32_t instance; - uint32_t combValue; - uint32_t trigValue; - - instance = GINT_GetInstance(base); - - combValue = (base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT; - *comb = (gint_comb_t)combValue; - trigValue = (base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT; - *trig = (gint_trig_t)trigValue; - *callback = s_gintCallback[instance]; -} - -/*! - * brief Configure GINT peripheral pins. - - * This function enables and controls the polarity of enabled pin(s) of a given port. - * - * param base Base address of the GINT peripheral. - * param port Port number. - * param polarityMask Each bit position selects the polarity of the corresponding enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * param enableMask Each bit position selects if the corresponding pin is enabled or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * retval None. - */ -void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask) -{ - base->PORT_POL[port] = polarityMask; - base->PORT_ENA[port] = enableMask; -} - -/*! - * brief Get GINT peripheral pin configuration. - - * This function returns the pin configuration of a given port. - * - * param base Base address of the GINT peripheral. - * param port Port number. - * param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding - enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled - or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * retval None. - */ -void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask) -{ - *polarityMask = base->PORT_POL[port]; - *enableMask = base->PORT_ENA[port]; -} - -/*! - * brief Enable callback. - - * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * param base Base address of the GINT peripheral. - * - * retval None. - */ -void GINT_EnableCallback(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - /* If GINT is configured in "AND" mode a spurious interrupt is generated. - Clear status and pending interrupt before enabling the irq in NVIC. */ - GINT_ClrStatus(base); - NVIC_ClearPendingIRQ(s_gintIRQ[instance]); - (void)EnableIRQ(s_gintIRQ[instance]); -} - -/*! - * brief Disable callback. - - * This function disables the interrupt for the selected GINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * param base Base address of the peripheral. - * - * retval None. - */ -void GINT_DisableCallback(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - (void)DisableIRQ(s_gintIRQ[instance]); - GINT_ClrStatus(base); - NVIC_ClearPendingIRQ(s_gintIRQ[instance]); -} - -/*! - * brief Deinitialize GINT peripheral. - - * This function disables the GINT clock. - * - * param base Base address of the GINT peripheral. - * - * retval None. - */ -void GINT_Deinit(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - /* Cleanup */ - GINT_DisableCallback(base); - s_gintCallback[instance] = NULL; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_gintResets[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the peripheral clock */ - CLOCK_DisableClock(s_gintClocks[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(GINT0) -void GINT0_DriverIRQHandler(void); -void GINT0_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[0]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[0] != NULL) - { - s_gintCallback[0](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT1) -void GINT1_DriverIRQHandler(void); -void GINT1_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[1]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[1] != NULL) - { - s_gintCallback[1](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT2) -void GINT2_DriverIRQHandler(void); -void GINT2_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[2]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[2] != NULL) - { - s_gintCallback[2](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT3) -void GINT3_DriverIRQHandler(void); -void GINT3_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[3]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[3] != NULL) - { - s_gintCallback[3](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT4) -void GINT4_DriverIRQHandler(void); -void GINT4_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[4]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[4] != NULL) - { - s_gintCallback[4](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT5) -void GINT5_DriverIRQHandler(void); -void GINT5_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[5]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[5] != NULL) - { - s_gintCallback[5](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT6) -void GINT6_DriverIRQHandler(void); -void GINT6_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[6]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[6] != NULL) - { - s_gintCallback[6](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT7) -void GINT7_DriverIRQHandler(void); -void GINT7_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[7]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[7] != NULL) - { - s_gintCallback[7](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gint.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gint.h deleted file mode 100644 index adc301a9e0d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gint.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_GINT_H_ -#define _FSL_GINT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup gint_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3. */ -/*@}*/ - -/*! @brief GINT combine inputs type */ -typedef enum _gint_comb -{ - kGINT_CombineOr = 0U, /*!< A grouped interrupt is generated when any one of the enabled inputs is active */ - kGINT_CombineAnd = 1U /*!< A grouped interrupt is generated when all enabled inputs are active */ -} gint_comb_t; - -/*! @brief GINT trigger type */ -typedef enum _gint_trig -{ - kGINT_TrigEdge = 0U, /*!< Edge triggered based on polarity */ - kGINT_TrigLevel = 1U /*!< Level triggered based on polarity */ -} gint_trig_t; - -/* @brief GINT port type */ -typedef enum _gint_port -{ - kGINT_Port0 = 0U, - kGINT_Port1 = 1U, -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 2U) - kGINT_Port2 = 2U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 3U) - kGINT_Port3 = 3U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 4U) - kGINT_Port4 = 4U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 5U) - kGINT_Port5 = 5U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 6U) - kGINT_Port6 = 6U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 7U) - kGINT_Port7 = 7U, -#endif -} gint_port_t; - -/*! @brief GINT Callback function. */ -typedef void (*gint_cb_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize GINT peripheral. - - * This function initializes the GINT peripheral and enables the clock. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_Init(GINT_Type *base); - -/*! - * @brief Setup GINT peripheral control parameters. - - * This function sets the control parameters of GINT peripheral. - * - * @param base Base address of the GINT peripheral. - * @param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. - * @param trig Controls if the enabled inputs are level or edge sensitive based on polarity. - * @param callback This function is called when configured group interrupt is generated. - * - * @retval None. - */ -void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback); - -/*! - * @brief Get GINT peripheral control parameters. - - * This function returns the control parameters of GINT peripheral. - * - * @param base Base address of the GINT peripheral. - * @param comb Pointer to store combine input value. - * @param trig Pointer to store trigger value. - * @param callback Pointer to store callback function. - * - * @retval None. - */ -void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback); - -/*! - * @brief Configure GINT peripheral pins. - - * This function enables and controls the polarity of enabled pin(s) of a given port. - * - * @param base Base address of the GINT peripheral. - * @param port Port number. - * @param polarityMask Each bit position selects the polarity of the corresponding enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * @param enableMask Each bit position selects if the corresponding pin is enabled or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * @retval None. - */ -void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask); - -/*! - * @brief Get GINT peripheral pin configuration. - - * This function returns the pin configuration of a given port. - * - * @param base Base address of the GINT peripheral. - * @param port Port number. - * @param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding - enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * @param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled - or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * @retval None. - */ -void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask); - -/*! - * @brief Enable callback. - - * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_EnableCallback(GINT_Type *base); - -/*! - * @brief Disable callback. - - * This function disables the interrupt for the selected GINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * @param base Base address of the peripheral. - * - * @retval None. - */ -void GINT_DisableCallback(GINT_Type *base); - -/*! - * @brief Clear GINT status. - - * This function clears the GINT status bit. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -static inline void GINT_ClrStatus(GINT_Type *base) -{ - base->CTRL |= GINT_CTRL_INT_MASK; -} - -/*! - * @brief Get GINT status. - - * This function returns the GINT status. - * - * @param base Base address of the GINT peripheral. - * - * @retval status = 0 No group interrupt request. = 1 Group interrupt request active. - */ -static inline uint32_t GINT_GetStatus(GINT_Type *base) -{ - return (base->CTRL & GINT_CTRL_INT_MASK); -} - -/*! - * @brief Deinitialize GINT peripheral. - - * This function disables the GINT clock. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_Deinit(GINT_Type *base); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_GINT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gpio.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gpio.c deleted file mode 100644 index be100d5e9e3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gpio.c +++ /dev/null @@ -1,317 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_gpio.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map FGPIO instance number to clock name. */ -static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) -/*! @brief Pointers to GPIO resets for each instance. */ -static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N; -#endif -/******************************************************************************* - * Prototypes - ************ ******************************************************************/ -/*! - * @brief Enable GPIO port clock. - * - * @param base GPIO peripheral base pointer. - * @param port GPIO port number. - */ -static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port); - -/******************************************************************************* - * Code - ******************************************************************************/ -static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - assert(port < ARRAY_SIZE(s_gpioClockName)); - - /* Upgate the GPIO clock */ - CLOCK_EnableClock(s_gpioClockName[port]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Initializes the GPIO peripheral. - * - * This function ungates the GPIO clock. - * - * param base GPIO peripheral base pointer. - * param port GPIO port number. - */ -void GPIO_PortInit(GPIO_Type *base, uint32_t port) -{ - GPIO_EnablePortClock(base, port); - -#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) - /* Reset the GPIO module */ - RESET_PeripheralReset(s_gpioResets[port]); -#endif -} - -/*! - * brief Initializes a GPIO pin used by the board. - * - * To initialize the GPIO, define a pin configuration, either input or output, in the user file. - * Then, call the GPIO_PinInit() function. - * - * This is an example to define an input pin or output pin configuration: - * code - * Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * endcode - * - * param base GPIO peripheral base pointer(Typically GPIO) - * param port GPIO port number - * param pin GPIO pin number - * param config GPIO pin configuration pointer - */ -void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) -{ - GPIO_EnablePortClock(base, port); - - if (config->pinDirection == kGPIO_DigitalInput) - { -#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) - base->DIRCLR[port] = 1UL << pin; -#else - base->DIR[port] &= ~(1UL << pin); -#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ - } - else - { - /* Set default output value */ - if (config->outputLogic == 0U) - { - base->CLR[port] = (1UL << pin); - } - else - { - base->SET[port] = (1UL << pin); - } -/* Set pin direction */ -#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) - base->DIRSET[port] = 1UL << pin; -#else - base->DIR[port] |= 1UL << pin; -#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ - } -} - -#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT -/*! - * @brief Set the configuration of pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param pin GPIO pin number. - * @param config GPIO pin interrupt configuration.. - */ -void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config) -{ - base->INTEDG[port] = (base->INTEDG[port] & ~(1UL << pin)) | ((uint32_t)config->mode << pin); - - base->INTPOL[port] = (base->INTPOL[port] & ~(1UL << pin)) | ((uint32_t)config->polarity << pin); -} - -/*! - * @brief Enables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] | mask; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] | mask; - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Disables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] & ~mask; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] & ~mask; - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Clears multiple pins interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTSTATA[port] = mask; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTSTATB[port] = mask; - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @ Read port interrupt status. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param index GPIO interrupt number. - * @retval masked GPIO status value - */ -uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index) -{ - uint32_t status = 0U; - - if ((uint32_t)kGPIO_InterruptA == index) - { - status = base->INTSTATA[port]; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - status = base->INTSTATB[port]; - } - else - { - /*Should not enter here*/ - } - return status; -} - -/*! - * @brief Enables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] | (1UL << pin); - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] | (1UL << pin); - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Disables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] & ~(1UL << pin); - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] & ~(1UL << pin); - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Clears the specific pin interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTSTATA[port] = 1UL << pin; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTSTATB[port] = 1UL << pin; - } - else - { - /*Should not enter here*/ - } -} -#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gpio.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gpio.h deleted file mode 100644 index 50a33f89208..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gpio.h +++ /dev/null @@ -1,364 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _LPC_GPIO_H_ -#define _LPC_GPIO_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_gpio - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPC GPIO driver version. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 7)) -/*@}*/ - -/*! @brief LPC GPIO direction definition */ -typedef enum _gpio_pin_direction -{ - kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ - kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ -} gpio_pin_direction_t; - -/*! - * @brief The GPIO pin configuration structure. - * - * Every pin can only be configured as either output pin or input pin at a time. - * If configured as a input pin, then leave the outputConfig unused. - */ -typedef struct _gpio_pin_config -{ - gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ - /* Output configurations, please ignore if configured as a input one */ - uint8_t outputLogic; /*!< Set default output logic, no use in input */ -} gpio_pin_config_t; - -#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT) -#define GPIO_PIN_INT_LEVEL 0x00U -#define GPIO_PIN_INT_EDGE 0x01U - -#define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U -#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U - -/*! @brief GPIO Pin Interrupt enable mode */ -typedef enum _gpio_pin_enable_mode -{ - kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */ - kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE /*!< Generate Pin Interrupt on edge mode */ -} gpio_pin_enable_mode_t; - -/*! @brief GPIO Pin Interrupt enable polarity */ -typedef enum _gpio_pin_enable_polarity -{ - kGPIO_PinIntEnableHighOrRise = - PINT_PIN_INT_HIGH_OR_RISE_TRIGGER, /*!< Generate Pin Interrupt on high level or rising edge */ - kGPIO_PinIntEnableLowOrFall = - PINT_PIN_INT_LOW_OR_FALL_TRIGGER /*!< Generate Pin Interrupt on low level or falling edge */ -} gpio_pin_enable_polarity_t; - -/*! @brief LPC GPIO interrupt index definition */ -typedef enum _gpio_interrupt_index -{ - kGPIO_InterruptA = 0U, /*!< Set current pin as interrupt A*/ - kGPIO_InterruptB = 1U, /*!< Set current pin as interrupt B*/ -} gpio_interrupt_index_t; - -/*! @brief Configures the interrupt generation condition. */ -typedef struct _gpio_interrupt_config -{ - uint8_t mode; /* The trigger mode of GPIO interrupts */ - uint8_t polarity; /* The polarity of GPIO interrupts */ -} gpio_interrupt_config_t; -#endif - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @name GPIO Configuration */ -/*@{*/ - -/*! - * @brief Initializes the GPIO peripheral. - * - * This function ungates the GPIO clock. - * - * @param base GPIO peripheral base pointer. - * @param port GPIO port number. - */ -void GPIO_PortInit(GPIO_Type *base, uint32_t port); - -/*! - * @brief Initializes a GPIO pin used by the board. - * - * To initialize the GPIO, define a pin configuration, either input or output, in the user file. - * Then, call the GPIO_PinInit() function. - * - * This is an example to define an input pin or output pin configuration: - * @code - * Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * @endcode - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @param config GPIO pin configuration pointer - */ -void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config); - -/*@}*/ - -/*! @name GPIO Output Operations */ -/*@{*/ - -/*! - * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @param output GPIO pin output logic level. - * - 0: corresponding pin output low-logic level. - * - 1: corresponding pin output high-logic level. - */ -static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) -{ - base->B[port][pin] = output; -} - -/*@}*/ -/*! @name GPIO Input Operations */ -/*@{*/ - -/*! - * @brief Reads the current input value of the GPIO PIN. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @retval GPIO port input value - * - 0: corresponding pin input low-logic level. - * - 1: corresponding pin input high-logic level. - */ -static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) -{ - return (uint32_t)base->B[port][pin]; -} - -/*@}*/ - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 1. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->SET[port] = mask; -} - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 0. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->CLR[port] = mask; -} - -/*! - * @brief Reverses current output logic of the multiple GPIO pins. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->NOT[port] = mask; -} - -/*@}*/ - -/*! - * @brief Reads the current input value of the whole GPIO port. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - */ -static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port) -{ - return (uint32_t)base->PIN[port]; -} - -/*@}*/ -/*! @name GPIO Mask Operations */ -/*@{*/ - -/*! - * @brief Sets port mask, 0 - enable pin, 1 - disable pin. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->MASK[port] = mask; -} - -/*! - * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param output GPIO port output value. - */ -static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output) -{ - base->MPIN[port] = output; -} - -/*! - * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be - * affected. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @retval masked GPIO port value - */ -static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) -{ - return (uint32_t)base->MPIN[port]; -} - -#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT -/*! - * @brief Set the configuration of pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param pin GPIO pin number. - * @param config GPIO pin interrupt configuration.. - */ -void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config); - -/*! - * @brief Enables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); - -/*! - * @brief Disables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); - -/*! - * @brief Clears pin interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); - -/*! - * @ Read port interrupt status. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param index GPIO interrupt number. - * @retval masked GPIO status value - */ -uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index); - -/*! - * @brief Enables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); - -/*! - * @brief Disables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); - -/*! - * @brief Clears the specific pin interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); - -#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* _LPC_GPIO_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_hscmp.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_hscmp.c deleted file mode 100644 index 5fa11bca85f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_hscmp.c +++ /dev/null @@ -1,237 +0,0 @@ -/* - * Copyright 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_hscmp.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.hscmp" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -#if defined(HSCMP_CLOCKS) -/*! - * @brief Get instance number for HSCMP module. - * - * @param base HSCMP peripheral base address - */ -static uint32_t HSCMP_GetInstance(HSCMP_Type *base); -#endif /* HSCMP_CLOCKS */ - -/******************************************************************************* - * Variables - ******************************************************************************/ -#if defined(HSCMP_CLOCKS) -/*! @brief Pointers to HSCMP bases for each instance. */ -static HSCMP_Type *const s_hscmpBases[] = HSCMP_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to HSCMP clocks for each instance. */ -static const clock_ip_name_t s_hscmpClocks[] = HSCMP_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#endif /* HSCMP_CLOCKS */ - -/******************************************************************************* - * Codes - ******************************************************************************/ -#if defined(HSCMP_CLOCKS) -static uint32_t HSCMP_GetInstance(HSCMP_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_hscmpBases); instance++) - { - if (s_hscmpBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_hscmpBases)); - - return instance; -} -#endif /* HSCMP_CLOCKS */ - -/*! - * brief Initialize the HSCMP - * - * This function initializes the HSCMP module. The operations included are: - * - Enabling the clock for HSCMP module. - * - Configuring the comparator. - * - Enabling the HSCMP module. - * Note: For some devices, multiple HSCMP instance share the same clock gate. In this case, to enable the clock for - * any instance enables all the HSCMPs. Check the chip reference manual for the clock assignment of the HSCMP. - * - * param base HSCMP peripheral base address. - * param config Pointer to "hscmp_config_t" structure. - */ -void HSCMP_Init(HSCMP_Type *base, const hscmp_config_t *config) -{ - assert(config != NULL); - - uint32_t tmp32; - -#if defined(HSCMP_CLOCKS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(s_hscmpClocks[HSCMP_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#endif /* HSCMP_CLOCKS */ - - /* Configure. */ - HSCMP_Enable(base, false); - /* CCR0 register. */ - if (config->enableStopMode) - { - base->CCR0 |= HSCMP_CCR0_CMP_STOP_EN_MASK; - } - else - { - base->CCR0 &= ~HSCMP_CCR0_CMP_STOP_EN_MASK; - } - /* CCR1 register. */ - tmp32 = base->CCR1 & ~(HSCMP_CCR1_COUT_PEN_MASK | HSCMP_CCR1_COUT_SEL_MASK | HSCMP_CCR1_COUT_INV_MASK); - if (config->enableOutputPin) - { - tmp32 |= HSCMP_CCR1_COUT_PEN_MASK; - } - if (config->useUnfilteredOutput) - { - tmp32 |= HSCMP_CCR1_COUT_SEL_MASK; - } - if (config->enableInvertOutput) - { - tmp32 |= HSCMP_CCR1_COUT_INV_MASK; - } - base->CCR1 = tmp32; - /* CCR2 register. */ - tmp32 = base->CCR2 & ~(HSCMP_CCR2_HYSTCTR_MASK | HSCMP_CCR2_CMP_NPMD_MASK | HSCMP_CCR2_CMP_HPMD_MASK); - tmp32 |= HSCMP_CCR2_HYSTCTR(config->hysteresisMode); - tmp32 |= ((uint32_t)(config->powerMode) << HSCMP_CCR2_CMP_HPMD_SHIFT); - base->CCR2 = tmp32; - - HSCMP_Enable(base, true); /* Enable the HSCMP module. */ -} - -/*! - * brief De-initializes the HSCMP module. - * - * This function de-initializes the HSCMP module. The operations included are: - * - Disabling the HSCMP module. - * - Disabling the clock for HSCMP module. - * - * This function disables the clock for the HSCMP. - * Note: For some devices, multiple HSCMP instance shares the same clock gate. In this case, before disabling the - * clock for the HSCMP, ensure that all the HSCMP instances are not used. - * - * param base HSCMP peripheral base address. - */ -void HSCMP_Deinit(HSCMP_Type *base) -{ - /* Disable the HSCMP module. */ - HSCMP_Enable(base, false); -#if defined(HSCMP_CLOCKS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(s_hscmpClocks[HSCMP_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#endif /* HSCMP_CLOCKS */ -} - -/*! - * brief Gets an available pre-defined settings for the comparator's configuration. - * - * This function initializes the comparator configuration structure to these default values: - * code - * config->enableStopMode = false; - * config->enableOutputPin = false; - * config->useUnfilteredOutput = false; - * config->enableInvertOutput = false; - * config->hysteresisMode = kHSCMP_HysteresisLevel0; - * config->powerMode = kHSCMP_LowSpeedPowerMode; - * endcode - * param config Pointer to "hscmp_config_t" structure. - */ -void HSCMP_GetDefaultConfig(hscmp_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enableStopMode = false; - config->enableOutputPin = false; - config->useUnfilteredOutput = false; - config->enableInvertOutput = false; - config->hysteresisMode = kHSCMP_HysteresisLevel0; - config->powerMode = kHSCMP_LowSpeedPowerMode; -} - -/*! - * brief Select the input channels for HSCMP. This function determines which input - * is selected for the negative and positive mux. - * - * param base HSCMP peripheral base address. - * param positiveChannel Positive side input channel number. Available range is 0-7. - * param negativeChannel Negative side input channel number. Available range is 0-7. - */ -void HSCMP_SetInputChannels(HSCMP_Type *base, uint32_t positiveChannel, uint32_t negativeChannel) -{ - uint32_t tmp32; - - tmp32 = base->CCR2 & ~(HSCMP_CCR2_PSEL_MASK | HSCMP_CCR2_MSEL_MASK); - tmp32 |= HSCMP_CCR2_PSEL(positiveChannel) | HSCMP_CCR2_MSEL(negativeChannel); - base->CCR2 = tmp32; -} - -/*! - * brief Configures the filter. - * - * param base HSCMP peripheral base address. - * param config Pointer to "hscmp_filter_config_t" structure. - */ -void HSCMP_SetFilterConfig(HSCMP_Type *base, const hscmp_filter_config_t *config) -{ - assert(config != NULL); - - uint32_t tmp32; - - tmp32 = base->CCR1 & ~(HSCMP_CCR1_FILT_PER_MASK | HSCMP_CCR1_FILT_CNT_MASK | HSCMP_CCR1_SAMPLE_EN_MASK); - if (config->enableSample) - { - tmp32 |= HSCMP_CCR1_SAMPLE_EN_MASK; - } - tmp32 |= HSCMP_CCR1_FILT_PER(config->filterSamplePeriod) | HSCMP_CCR1_FILT_CNT(config->filterSampleCount); - base->CCR1 = tmp32; -} - -/*! - * brief Configure the internal DAC module. - * - * param base HSCMP peripheral base address. - * param config Pointer to "hscmp_dac_config_t" structure. If config is "NULL", disable internal DAC. - */ -void HSCMP_SetDACConfig(HSCMP_Type *base, const hscmp_dac_config_t *config) -{ - uint32_t tmp32; - if (config == NULL) - { - tmp32 = 0U; /* Disable internal DAC. */ - } - else - { - tmp32 = HSCMP_DCR_VRSEL(config->referenceVoltageSource) | HSCMP_DCR_DAC_DATA(config->DACValue); - if (config->enableLowPowerMode) - { - tmp32 |= HSCMP_DCR_DAC_HPMD_MASK; - } - tmp32 |= HSCMP_DCR_DAC_EN_MASK; - } - base->DCR = tmp32; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_hscmp.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_hscmp.h deleted file mode 100644 index 37d9cd1754c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_hscmp.h +++ /dev/null @@ -1,302 +0,0 @@ -/* - * Copyright 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_HSCMP_H_ -#define _FSL_HSCMP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup hscmp - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief HSCMP driver version 2.0.3. */ -#define FSL_HSCMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ - -/*! - * @brief HSCMP status falgs mask. - */ -enum _hscmp_status_flags -{ - kHSCMP_OutputRisingEventFlag = HSCMP_CSR_CFR_MASK, /*!< Rising-edge on the comparison output has occurred. */ - kHSCMP_OutputFallingEventFlag = HSCMP_CSR_CFF_MASK, /*!< Falling-edge on the comparison output has occurred. */ - kHSCMP_OutputAssertEventFlag = HSCMP_CSR_COUT_MASK, /*!< Return the current value of the analog comparator output. - The flag does not support W1C. */ -}; - -/*! - * @brief HSCMP interrupt enable/disable mask. - */ -enum _hscmp_interrupt_enable -{ - kHSCMP_OutputRisingInterruptEnable = HSCMP_IER_CFR_IE_MASK, /*!< Comparator interrupt enable rising. */ - kHSCMP_OutputFallingInterruptEnable = HSCMP_IER_CFF_IE_MASK, /*!< Comparator interrupt enable falling. */ -}; -/*! - * @brief HSCMP hysteresis mode. See chip data sheet to get the actual hystersis - * value with each level - */ -typedef enum _hscmp_hysteresis_mode -{ - kHSCMP_HysteresisLevel0 = 0U, /*!< The hard block output has level 0 hysteresis internally. */ - kHSCMP_HysteresisLevel1 = 1U, /*!< The hard block output has level 1 hysteresis internally. */ - kHSCMP_HysteresisLevel2 = 2U, /*!< The hard block output has level 2 hysteresis internally. */ - kHSCMP_HysteresisLevel3 = 3U, /*!< The hard block output has level 3 hysteresis internally. */ -} hscmp_hysteresis_mode_t; - -/*! - * @brief HSCMP nano mode. - */ -typedef enum _hscmp_power_mode -{ - kHSCMP_LowSpeedPowerMode = 0U, /*!< Low speed comparison mode is selected. */ - kHSCMP_HighSpeedPowerMode = 1U, /*!< High speed comparison mode is selected. */ - kHSCMP_NanoPowerMode = 2U, /*!< Nano power comparator is enabled. */ -} hscmp_power_mode_t; - -/*! - * @brief Internal DAC reference voltage source. - */ -typedef enum _hscmp_dac_reference_voltage_source -{ - kHSCMP_VrefSourceVin1 = 0U, /*!< vrefh_int is selected as resistor ladder network supply reference Vin. */ - kHSCMP_VrefSourceVin2 = 1U, /*!< vrefh_ext is selected as resistor ladder network supply reference Vin. */ -} hscmp_dac_reference_voltage_source_t; - -/*! - * @brief Configure the filter. - */ -typedef struct _hscmp_filter_config -{ - bool enableSample; /*!< Decide whether to use the external SAMPLE as a sampling clock input. */ - uint8_t filterSampleCount; /*!< Filter Sample Count. Available range is 1-7; 0 disables the filter. */ - uint8_t filterSamplePeriod; /*!< Filter Sample Period. The divider to the bus clock. Available range is 0-255. The - sampling clock must be at least 4 times slower than the system clock to the comparator. - So if enableSample is "false", filterSamplePeriod should be set greater than 4.*/ -} hscmp_filter_config_t; - -/*! - * @brief configure the internal DAC. - */ -typedef struct _hscmp_dac_config -{ - bool enableLowPowerMode; /*!< Decide whether to enable DAC low power mode. */ - hscmp_dac_reference_voltage_source_t referenceVoltageSource; /*!< Internal DAC supply voltage reference source. */ - uint8_t DACValue; /*!< Value for the DAC Output Voltage. Available range is 0-63.*/ -} hscmp_dac_config_t; - -/*! - * @brief Configures the comparator. - */ -typedef struct _hscmp_config -{ - bool enableStopMode; /*!< Decide whether to enable the comparator when in STOP modes. */ - bool enableOutputPin; /*!< Decide whether to enable the comparator is available in selected pin. */ - bool useUnfilteredOutput; /*!< Decide whether to use unfiltered output. */ - bool enableInvertOutput; /*!< Decide whether to inverts the comparator output. */ - hscmp_hysteresis_mode_t hysteresisMode; /*!< HSCMP hysteresis mode. */ - hscmp_power_mode_t powerMode; /*!< HSCMP power mode. */ -} hscmp_config_t; -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @name Initialization - * @{ - */ - -/*! - * @brief Initialize the HSCMP - * - * This function initializes the HSCMP module. The operations included are: - * - Enabling the clock for HSCMP module. - * - Configuring the comparator. - * - Enabling the HSCMP module. - * Note: For some devices, multiple HSCMP instance share the same clock gate. In this case, to enable the clock for - * any instance enables all the HSCMPs. Check the chip reference manual for the clock assignment of the HSCMP. - * - * @param base HSCMP peripheral base address. - * @param config Pointer to "hscmp_config_t" structure. - */ -void HSCMP_Init(HSCMP_Type *base, const hscmp_config_t *config); - -/*! - * @brief De-initializes the HSCMP module. - * - * This function de-initializes the HSCMP module. The operations included are: - * - Disabling the HSCMP module. - * - Disabling the clock for HSCMP module. - * - * This function disables the clock for the HSCMP. - * Note: For some devices, multiple HSCMP instance shares the same clock gate. In this case, before disabling the - * clock for the HSCMP, ensure that all the HSCMP instances are not used. - * - * @param base HSCMP peripheral base address. - */ -void HSCMP_Deinit(HSCMP_Type *base); - -/*! - * @brief Gets an available pre-defined settings for the comparator's configuration. - * - * This function initializes the comparator configuration structure to these default values: - * @code - * config->enableStopMode = false; - * config->enableOutputPin = false; - * config->useUnfilteredOutput = false; - * config->enableInvertOutput = false; - * config->hysteresisMode = kHSCMP_HysteresisLevel0; - * config->powerMode = kHSCMP_LowSpeedPowerMode; - * @endcode - * @param config Pointer to "hscmp_config_t" structure. - */ -void HSCMP_GetDefaultConfig(hscmp_config_t *config); - -/*! - * @brief Enable/Disable HSCMP module. - * - * @param base HSCMP peripheral base address. - * @param enable "true" means enable the module, and "false" means disable the module. - */ -static inline void HSCMP_Enable(HSCMP_Type *base, bool enable) -{ - if (enable) - { - base->CCR0 |= HSCMP_CCR0_CMP_EN_MASK; - } - else - { - base->CCR0 &= ~HSCMP_CCR0_CMP_EN_MASK; - } -} - -/*! - * @brief Select the input channels for HSCMP. This function determines which input - * is selected for the negative and positive mux. - * - * @param base HSCMP peripheral base address. - * @param positiveChannel Positive side input channel number. Available range is 0-7. - * @param negativeChannel Negative side input channel number. Available range is 0-7. - */ -void HSCMP_SetInputChannels(HSCMP_Type *base, uint32_t positiveChannel, uint32_t negativeChannel); - -/*! - * @brief Enables/disables the DMA request for rising/falling events. - * Normally, the HSCMP generates a CPU interrupt if there is a rising/falling event. When - * DMA support is enabled and the rising/falling interrupt is enabled , the rising/falling - * event forces a DMA transfer request rather than a CPU interrupt instead. - * - * @param base HSCMP peripheral base address. - * @param enable "true" means enable DMA support, and "false" means disable DMA support. - */ -static inline void HSCMP_EnableDMA(HSCMP_Type *base, bool enable) -{ - if (enable) - { - base->CCR1 |= HSCMP_CCR1_DMA_EN_MASK; - } - else - { - base->CCR1 &= ~HSCMP_CCR1_DMA_EN_MASK; - } -} - -/*! - * @brief Enable/Disable window mode.When any windowed mode is active, COUTA is clocked by - * the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. - * The optionally inverted comparator output COUT_RAW is sampled on every bus clock - * when WINDOW=1 to generate COUTA. - * - * @param base HSCMP peripheral base address. - * @param enable "true" means enable window mode, and "false" means disable window mode. - */ -static inline void HSCMP_EnableWindowMode(HSCMP_Type *base, bool enable) -{ - if (enable) - { - base->CCR1 |= HSCMP_CCR1_WINDOW_EN_MASK; - } - else - { - base->CCR1 &= ~HSCMP_CCR1_WINDOW_EN_MASK; - } -} - -/*! - * @brief Configures the filter. - * - * @param base HSCMP peripheral base address. - * @param config Pointer to "hscmp_filter_config_t" structure. - */ -void HSCMP_SetFilterConfig(HSCMP_Type *base, const hscmp_filter_config_t *config); - -/*! - * @brief Configure the internal DAC module. - * - * @param base HSCMP peripheral base address. - * @param config Pointer to "hscmp_dac_config_t" structure. If config is "NULL", disable internal DAC. - */ -void HSCMP_SetDACConfig(HSCMP_Type *base, const hscmp_dac_config_t *config); - -/*! - * @brief Enable the interrupts. - * - * @param base HSCMP peripheral base address. - * @param mask Mask value for interrupts. See "_hscmp_interrupt_enable". - */ -static inline void HSCMP_EnableInterrupts(HSCMP_Type *base, uint32_t mask) -{ - base->IER |= mask; -} - -/*! - * @brief Disable the interrupts. - * - * @param base HSCMP peripheral base address. - * @param mask Mask value for interrupts. See "_hscmp_interrupt_enable". - */ -static inline void HSCMP_DisableInterrupts(HSCMP_Type *base, uint32_t mask) -{ - base->IER &= ~mask; -} - -/*! - * @brief Get the HSCMP status flags. - * - * @param base HSCMP peripheral base address. - * - * @return Mask value for the asserted flags. See "_hscmp_status_flags". - */ -static inline uint32_t HSCMP_GetStatusFlags(HSCMP_Type *base) -{ - return base->CSR; -} - -/*! - * @brief Clear the HSCMP status flags - * - * @param base HSCMP peripheral base address. - * @param mask Mask value for the flags. See "_hscmp_status_flags". - */ -static inline void HSCMP_ClearStatusFlags(HSCMP_Type *base, uint32_t mask) -{ - base->CSR = mask; -} - -/*@}*/ - -/*@}*/ - -#endif /* _FSL_HSCMP_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c.c deleted file mode 100644 index b26dbe75bdc..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c.c +++ /dev/null @@ -1,2085 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_i2c.h" -#include "fsl_flexcomm.h" -#include -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c" -#endif - -/*! @brief Common sets of flags used by the driver's transactional layer internally. */ -enum _i2c_flag_constants -{ - kI2C_MasterIrqFlags = I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | - I2C_INTSTAT_EVENTTIMEOUT_MASK | I2C_INTSTAT_SCLTIMEOUT_MASK, - kI2C_SlaveIrqFlags = I2C_INTSTAT_SLVPENDING_MASK | I2C_INTSTAT_SLVDESEL_MASK, -}; - -/*! - * @brief Used for conversion from `flexcomm_irq_handler_t` to `flexcomm_i2c_master_irq_handler_t` and - * `flexcomm_i2c_slave_irq_handler_t`. - */ -typedef union i2c_to_flexcomm -{ - flexcomm_i2c_master_irq_handler_t i2c_master_handler; - flexcomm_i2c_slave_irq_handler_t i2c_slave_handler; - flexcomm_irq_handler_t flexcomm_handler; -} i2c_to_flexcomm_t; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Waits for Master Pending status bit to set and check for bus error status. - * - * @param base The I2C peripheral base address. - * @return Bus status. - */ -static status_t I2C_PendingStatusWait(I2C_Type *base); - -/*! - * @brief Prepares the transfer state machine and fills in the command buffer. - * @param base The I2C peripheral base address. - * @param handle Master nonblocking driver handle. - * @param xfer The I2C transfer configuration structure. - */ -static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Resets the slave hardware state machine. - * According to documentation, after disabling slave to rest the slave hardware state machine, the register - * configuration remains unchanged. - * @param base The I2C peripheral base address. - */ -static void I2C_SlaveInternalStateMachineReset(I2C_Type *base); - -/*! - * @brief Compute CLKDIV - * - * This function computes CLKDIV value according to the given bus speed and Flexcomm source clock frequency. - * This setting is used by hardware during slave clock stretching. - * - * @param base The I2C peripheral base address. - * @return status of the operation - */ -static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal); - -/*! - * @brief Poll wait for the SLVPENDING flag. - * - * Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register. - * - * @param base The I2C peripheral base address. - * @return status register at time the SLVPENDING bit is read as set - */ -static uint32_t I2C_SlavePollPending(I2C_Type *base); - -/*! - * @brief Invoke event from I2C_SlaveTransferHandleIRQ(). - * - * Sets the event type to transfer structure and invokes the event callback, if it has been - * enabled by eventMask. - * - * @param base The I2C peripheral base address. - * @param handle The I2C slave handle for non-blocking APIs. - * @param event The I2C slave event to invoke. - */ -static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event); - -/*! - * @brief Handle slave address match event. - * - * Called by Slave interrupt routine to ACK or NACK the matched address. - * It also determines master direction (read or write). - * - * @param base The I2C peripheral base address. - * @return true if the matched address is ACK'ed - * @return false if the matched address is NACK'ed - */ -static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle); - -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. - * @param txData Data to be transmitted to master in response to master read from slave requests. NULL if slave RX only. - * @param txSize Size of txData buffer in bytes. - * @param rxData Data where received data from master will be stored in response to master write to slave requests. NULL - * if slave TX only. - * @param rxSize Size of rxData buffer in bytes. - * @retval #kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, - i2c_slave_handle_t *handle, - const void *txData, - size_t txSize, - void *rxData, - size_t rxSize, - uint32_t eventMask); - -/*! - * @brief Execute master transfer software state machine until FIFOs are exhausted. - * - * For master transmit, the states would be kStartState->kTransmitSubaddrState->kTransmitDataState->kStopState - * For master receive, the states would be kStartState->kTransmitSubaddrState->kStartState->kReceiveDataState-> - * kWaitForCompletionState - * - * @param handle Master nonblocking driver handle. - * @param[out] isDone Set to true if the transfer has completed. - * @retval #kStatus_Success - * @retval #kStatus_I2C_ArbitrationLost - * @retval #kStatus_I2C_Nak - */ -static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone); - -/*! - * @brief Checks the slave response to master's start signal. - * - * @param base I2C peripheral base address. - * @retval kStatus_Success Successfully complete the data transmission. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStataus_I2C_Nak Transfer error, receive NAK during addressing. - */ -static status_t I2C_MasterCheckStartResponse(I2C_Type *base); -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map i2c instance number to base address. */ -static const uint32_t s_i2cBaseAddrs[FSL_FEATURE_SOC_I2C_COUNT] = I2C_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_i2cIRQ[] = I2C_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * param base The I2C peripheral base address. - * return I2C instance number starting from 0. - */ -uint32_t I2C_GetInstance(I2C_Type *base) -{ - uint32_t i; - for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_I2C_COUNT; i++) - { - if ((uint32_t)base == s_i2cBaseAddrs[i]) - { - break; - } - } - assert(i < (uint32_t)FSL_FEATURE_SOC_I2C_COUNT); - return i; -} - -/*! - * brief Provides a default configuration for the I2C master peripheral. - * - * This function provides the following default configuration for the I2C master peripheral: - * code - * masterConfig->enableMaster = true; - * masterConfig->baudRate_Bps = 100000U; - * masterConfig->enableTimeout = false; - * endcode - * - * After calling this function, you can override any settings in order to customize the configuration, - * prior to initializing the master driver with I2C_MasterInit(). - * - * param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. - */ -void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) -{ - /* Initializes the configure structure to zero. */ - (void)memset(masterConfig, 0, sizeof(*masterConfig)); - - masterConfig->enableMaster = true; - masterConfig->baudRate_Bps = 100000U; - masterConfig->enableTimeout = false; - masterConfig->timeout_Ms = 35; -} - -/*! - * brief Initializes the I2C master peripheral. - * - * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user - * provided configuration. A software reset is performed prior to configuration. - * - * param base The I2C peripheral base address. - * param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of - * defaults - * that you can override. - * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, - * filter widths, and timeout periods. - */ -void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) -{ - (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); - I2C_MasterEnable(base, masterConfig->enableMaster); - I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); - I2C_MasterSetTimeoutValue(base, masterConfig->timeout_Ms, srcClock_Hz); -} - -/*! - * brief Deinitializes the I2C master peripheral. - * - * This function disables the I2C master peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * param base The I2C peripheral base address. - */ -void I2C_MasterDeinit(I2C_Type *base) -{ - I2C_MasterEnable(base, false); -} - -/*! - * brief Gets the I2C status flags. - * - * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit - * in the return value is set if the flag is asserted. - * - * param base The I2C peripheral base address. - * return State of the status flags: - * - 1: related status flag is set. - * - 0: related status flag is not set. - * see ref _i2c_status_flags, ref _i2c_master_status_flags and ref _i2c_slave_status_flags. - */ -uint32_t I2C_GetStatusFlags(I2C_Type *base) -{ - uint32_t statusMask = base->STAT; - if ((statusMask & (uint32_t)I2C_STAT_MSTSTATE_MASK) == 0UL) - { - statusMask |= (uint32_t)kI2C_MasterIdleFlag; - } - if (((statusMask & (uint32_t)I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == 3UL) - { - statusMask = (statusMask & ~(uint32_t)I2C_STAT_MSTSTATE_MASK) | (uint32_t)kI2C_MasterAddrNackFlag; - } - if ((statusMask & (uint32_t)I2C_STAT_SLVSTATE_MASK) == 0UL) - { - statusMask |= (uint32_t)kI2C_SlaveAddressedFlag; - } - if ((statusMask & (uint32_t)I2C_STAT_SLVIDX_MASK) == 0UL) - { - statusMask |= (uint32_t)kI2C_SlaveAddress0MatchFlag; - } - if (((statusMask & (uint32_t)I2C_STAT_SLVIDX_MASK) >> I2C_STAT_SLVIDX_SHIFT) == 3UL) - { - statusMask = (statusMask & ~(uint32_t)I2C_STAT_SLVIDX_MASK) | (uint32_t)kI2C_SlaveAddress3MatchFlag; - } - return statusMask; -} - -/*! - * brief Sets the I2C bus frequency for master transactions. - * - * The I2C master is automatically disabled and re-enabled as necessary to configure the baud - * rate. Do not call this function during a transfer, or the transfer is aborted. - * - * param base The I2C peripheral base address. - * param srcClock_Hz I2C functional clock frequency in Hertz. - * param baudRate_Bps Requested bus frequency in bits per second. - */ -void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) -{ - uint32_t scl, divider; - uint32_t mindivider; - uint32_t err, best_err; - uint32_t best_scl = 0U; - uint32_t best_div = 0U; - -#if defined(FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) && (FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) - /* - * RFT1717/RFT1437: workaround for hardware bug when using DMA - * I2C peripheral clock frequency has to be fixed at 8MHz - * source clock is 32MHz or 48MHz so divider is a round integer value - */ - best_div = srcClock_Hz / 8000000U; - best_scl = 8000000U / baudRate_Bps; - - if ((8000000U / best_scl - baudRate_Bps) > (baudRate_Bps - (8000000U / (best_scl + 1U)))) - { - best_scl = best_scl + 1U; - } - - /* - * Fallback to usual baudrate computation method, when: - * 1.Master SCL frequency does not fit in workaround range, - * 2.User's setting of baudRate_Bps is 400kHz while the clock frequency after divval is larger than 2MHz - */ - if ((best_scl > 18U) || ((best_scl < 4U)) || ((baudRate_Bps == 400000U) && (srcClock_Hz / best_div > 2000000U))) - { -#endif /*FSL_FEATURE_I2C_PREPCLKFRG_8MHZ*/ - - /* Calculate the minimal divider value to make sure the clock frequency after divval is not larger than 2MHz */ - /* This is required in RM in order to generate 400kHz baudrate */ - mindivider = ((srcClock_Hz * 10U) / 2000000U + 5U) / 10U; - /* If the scl value with current mindivider is smaller than 4, which is the minimal value register can achieve, - update mindivider */ - if ((srcClock_Hz / mindivider / baudRate_Bps) < 4U) - { - mindivider = srcClock_Hz / 4U / baudRate_Bps; - } - /* Calculate the ideal div and scl value*/ - best_err = 0U; - for (divider = mindivider; divider <= 0x10000U; divider++) - { - /* Calculte ideal scl value, round up the value */ - scl = ((srcClock_Hz * 10U) / (divider * baudRate_Bps) + 5U) / 10U; - - /* adjust it if it is out of range */ - scl = (scl > 18U) ? 18U : scl; - - /* calculate error */ - err = srcClock_Hz - (baudRate_Bps * scl * divider); - if ((err < best_err) || (best_err == 0U)) - { - best_div = divider; - best_scl = scl; - best_err = err; - } - - if ((err == 0U) || (scl <= 4U)) - { - /* either exact value was found - or scl is at its min (it would be even smaller in the next iteration for sure) */ - break; - } - } -#if defined(FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) && (FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) - } -#endif /*FSL_FEATURE_I2C_PREPCLKFRG_8MHZ*/ - base->CLKDIV = I2C_CLKDIV_DIVVAL(best_div - 1U); - if (best_scl % 2U == 0U) - { - base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl / 2U - 2U) | I2C_MSTTIME_MSTSCLHIGH(best_scl / 2U - 2U); - } - else - { - base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl / 2U - 1U) | I2C_MSTTIME_MSTSCLHIGH(best_scl / 2U - 2U); - } -} - -/*! - * brief Sets the I2C bus timeout value. - * - * If the SCL signal remains low or bus does not have event longer than the timeout value, kI2C_SclTimeoutFlag or - * kI2C_EventTimeoutFlag is set. This can indicete the bus is held by slave or any fault occurs to the I2C module. - * - * param base The I2C peripheral base address. - * param timeout_Ms Timeout value in millisecond. - * param srcClock_Hz I2C functional clock frequency in Hertz. - */ -void I2C_MasterSetTimeoutValue(I2C_Type *base, uint8_t timeout_Ms, uint32_t srcClock_Hz) -{ - assert((timeout_Ms != 0U) && (srcClock_Hz != 0U)); - - /* The low 4 bits of the timout reister TIMEOUT is hard-wired to be 1, so the the time out value is always 16 times - the I2C functional clock, we only need to calculate the high bits. */ - uint32_t timeoutValue = ((uint32_t)timeout_Ms * srcClock_Hz / 16UL / 100UL + 5UL) / 10UL; - if (timeoutValue > 0x1000UL) - { - timeoutValue = 0x1000UL; - } - timeoutValue = ((timeoutValue - 1UL) << 4UL) | 0xFUL; - base->TIMEOUT = timeoutValue; -} - -static status_t I2C_PendingStatusWait(I2C_Type *base) -{ - status_t result = kStatus_Success; - uint32_t status; - -#if I2C_RETRY_TIMES != 0U - uint32_t waitTimes = I2C_RETRY_TIMES; -#endif - - do - { - status = I2C_GetStatusFlags(base); - if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) - { - result = kStatus_I2C_EventTimeout; - } - if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) - { - result = kStatus_I2C_SclLowTimeout; - } -#if defined(FSL_FEATURE_I2C_TIMEOUT_RECOVERY) && FSL_FEATURE_I2C_TIMEOUT_RECOVERY - if (result != kStatus_Success) - { - I2C_MasterEnable(base, false); - I2C_MasterEnable(base, true); - break; - } -#endif -#if I2C_RETRY_TIMES != 0U - waitTimes--; - } while (((status & (uint32_t)kI2C_MasterPendingFlag) == 0U) && (waitTimes != 0U)); - - if (waitTimes == 0U) - { -#if defined(FSL_FEATURE_I2C_TIMEOUT_RECOVERY) && FSL_FEATURE_I2C_TIMEOUT_RECOVERY - I2C_MasterEnable(base, false); - I2C_MasterEnable(base, true); -#endif - return (uint32_t)kStatus_I2C_Timeout; - } -#else - } while ((status & (uint32_t)kI2C_MasterPendingFlag) == 0U); -#endif - - if ((status & (uint32_t)kI2C_MasterArbitrationLostFlag) != 0U) - { - result = kStatus_I2C_ArbitrationLost; - } - - if ((status & (uint32_t)kI2C_MasterStartStopErrorFlag) != 0U) - { - result = kStatus_I2C_StartStopError; - } - - /* Clear controller state. */ - I2C_ClearStatusFlags( - base, (uint32_t)kI2C_MasterAllClearFlags | (uint32_t)kI2C_EventTimeoutFlag | (uint32_t)kI2C_SclTimeoutFlag); - - return result; -} - -/*! - * brief Sends a START on the I2C bus. - * - * This function is used to initiate a new master mode transfer by sending the START signal. - * The slave address is sent following the I2C START signal. - * - * param base I2C peripheral base pointer - * param address 7-bit slave device address. - * param direction Master transfer directions(transmit/receive). - * retval kStatus_Success Successfully send the start signal. - * retval kStatus_I2C_Busy Current bus is busy. - */ -status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) -{ - status_t result; - result = I2C_PendingStatusWait(base); - if (result != kStatus_Success) - { - return result; - } - - /* Write Address and RW bit to data register */ - base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1U); - /* Start the transfer */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - - return kStatus_Success; -} - -/*! - * brief Sends a STOP signal on the I2C bus. - * - * retval kStatus_Success Successfully send the stop signal. - * retval kStatus_I2C_Timeout Send stop signal failed, timeout. - */ -status_t I2C_MasterStop(I2C_Type *base) -{ - status_t result = I2C_PendingStatusWait(base); - if (result != kStatus_Success) - { - return result; - } - - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - return kStatus_Success; -} - -/*! - * brief Performs a polling send transfer on the I2C bus. - * - * Sends up to a txSize number of bytes to the previously addressed slave device. The slave may - * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this - * function returns #kStatus_I2C_Nak. - * - * param base The I2C peripheral base address. - * param txBuff The pointer to the data to be transferred. - * param txSize The length in bytes of the data to be transferred. - * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * retval kStatus_Success Data was sent successfully. - * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags) -{ - uint32_t master_state; - status_t err; - - const uint8_t *buf = (const uint8_t *)txBuff; - - assert(txBuff != NULL); - - err = kStatus_Success; - while (txSize != 0U) - { - err = I2C_PendingStatusWait(base); - - if (err != kStatus_Success) - { - return err; - } - - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - switch (master_state) - { - case I2C_STAT_MSTCODE_TXREADY: - /* ready to send next byte */ - base->MSTDAT = *buf++; - txSize--; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - break; - - case I2C_STAT_MSTCODE_NACKADR: - case I2C_STAT_MSTCODE_NACKDAT: - err = kStatus_I2C_Nak; - /* Issue nack signal when nacked by slave. */ - (void)I2C_MasterStop(base); - break; - - default: - /* unexpected state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - if (err != kStatus_Success) - { - return err; - } - } - - err = I2C_PendingStatusWait(base); - - if (err != kStatus_Success) - { - return err; - } - -#if !I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK - /* Check nack signal. If master is nacked by slave of the last byte, return kStatus_I2C_Nak. */ - if (((base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == (uint32_t)I2C_STAT_MSTCODE_NACKDAT) - { - (void)I2C_MasterStop(base); - return kStatus_I2C_Nak; - } -#endif - - if (0U == (flags & (uint32_t)kI2C_TransferNoStopFlag)) - { - /* Initiate stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - err = I2C_PendingStatusWait(base); - if (err != kStatus_Success) - { - return err; - } - } - - return kStatus_Success; -} - -/*! - * brief Performs a polling receive transfer on the I2C bus. - * - * param base The I2C peripheral base address. - * param rxBuff The pointer to the data to be transferred. - * param rxSize The length in bytes of the data to be transferred. - * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * retval kStatus_Success Data was received successfully. - * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags) -{ - uint32_t master_state; - status_t err; - - uint8_t *buf = (uint8_t *)(rxBuff); - - assert(rxBuff != NULL); - - err = kStatus_Success; - while (rxSize != 0U) - { - err = I2C_PendingStatusWait(base); - - if (err != kStatus_Success) - { - return err; - } - - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - switch (master_state) - { - case I2C_STAT_MSTCODE_RXREADY: - /* ready to send next byte */ - *(buf++) = (uint8_t)base->MSTDAT; - if (--rxSize != 0U) - { - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - } - else - { - if ((flags & (uint32_t)kI2C_TransferNoStopFlag) == 0U) - { - /* initiate NAK and stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - err = I2C_PendingStatusWait(base); - } - } - break; - - case I2C_STAT_MSTCODE_NACKADR: - case I2C_STAT_MSTCODE_NACKDAT: - /* slave nacked the last byte */ - err = kStatus_I2C_Nak; - break; - - default: - /* unexpected state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - if (err != kStatus_Success) - { - return err; - } - } - - return kStatus_Success; -} - -static status_t I2C_MasterCheckStartResponse(I2C_Type *base) -{ - /* Wait for start signal to be transmitted. */ - status_t result = I2C_PendingStatusWait(base); - - if (result != kStatus_Success) - { - return result; - } - - if (((base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == I2C_STAT_MSTCODE_NACKADR) - { - (void)I2C_MasterStop(base); - return kStatus_I2C_Addr_Nak; - } - return kStatus_Success; -} - -/*! - * brief Performs a master polling transfer on the I2C bus. - * - * note The API does not return until the transfer succeeds or fails due - * to arbitration lost or receiving a NAK. - * - * param base I2C peripheral base address. - * param xfer Pointer to the transfer structure. - * retval kStatus_Success Successfully complete the data transmission. - * retval kStatus_I2C_Busy Previous transmission still not finished. - * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - * retval kStataus_I2C_Addr_Nak Transfer error, receive NAK during addressing. - */ -status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) -{ - status_t result = kStatus_Success; - uint32_t subaddress; - uint8_t subaddrBuf[4]; - i2c_direction_t direction; - int i; - - assert(xfer != NULL); - - /* If start signal is requested, send start signal. */ - if (0U == (xfer->flags & (uint32_t)kI2C_TransferNoStartFlag)) - { - direction = (xfer->subaddressSize != 0U) ? kI2C_Write : xfer->direction; - result = I2C_MasterStart(base, xfer->slaveAddress, direction); - if (result == kStatus_Success) - { - result = I2C_MasterCheckStartResponse(base); - if (result != kStatus_Success) - { - return result; - } - if ((xfer->subaddressSize) != 0U) - { - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) - { - subaddrBuf[i] = (uint8_t)subaddress & 0xffU; - subaddress >>= 8; - } - /* Send subaddress. */ - result = - I2C_MasterWriteBlocking(base, subaddrBuf, xfer->subaddressSize, (uint32_t)kI2C_TransferNoStopFlag); - if (result != kStatus_Success) - { - if (result == kStatus_I2C_Nak) - { - (void)I2C_MasterStop(base); - return kStatus_I2C_Addr_Nak; - } - } - else if (xfer->direction == kI2C_Read) - { - result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction); - if (result == kStatus_Success) - { - result = I2C_MasterCheckStartResponse(base); - if (result != kStatus_Success) - { - return result; - } - } - } - else - { - /* Empty else block to avoid MISRA 14.1 violation. */ - } - } - } - } - - if (result == kStatus_Success) - { - if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0U)) - { - /* Transmit data. */ - result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); - } - else - { - if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0U)) - { - /* Receive Data. */ - result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags); - } - } - } - - if (result == kStatus_I2C_Nak) - { - (void)I2C_MasterStop(base); - } - - return result; -} - -/*! - * brief Creates a new handle for the I2C master non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. - * - * param base The I2C peripheral base address. - * param[out] handle Pointer to the I2C master driver handle. - * param callback User provided pointer to the asynchronous callback function. - * param userData User provided pointer to the application callback data. - */ -void I2C_MasterTransferCreateHandle(I2C_Type *base, - i2c_master_handle_t *handle, - i2c_master_transfer_callback_t callback, - void *userData) -{ - assert(handle != NULL); - - uint32_t instance; - i2c_to_flexcomm_t handler; - handler.i2c_master_handler = I2C_MasterTransferHandleIRQ; - - /* Clear out the handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Save base and instance. */ - handle->completionCallback = callback; - handle->userData = userData; - - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - (void)EnableIRQ(s_i2cIRQ[instance]); -} - -/*! - * brief Performs a non-blocking transaction on the I2C bus. - * - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - * param xfer The pointer to the transfer descriptor. - * retval kStatus_Success The transaction was started successfully. - * retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking - * transaction is already in progress. - */ -status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) -{ - status_t result; - - assert(handle != NULL); - assert(xfer != NULL); - assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); - - /* Return busy if another transaction is in progress. */ - if (handle->state != (uint8_t)kIdleState) - { - return kStatus_I2C_Busy; - } - - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - - /* Prepare transfer state machine. */ - result = I2C_InitTransferStateMachine(base, handle, xfer); - - /* Clear error flags. */ - I2C_ClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Enable I2C internal IRQ sources. */ - I2C_EnableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - - return result; -} - -/*! - * brief Returns number of bytes transferred so far. - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - * param[out] count Number of bytes transferred so far by the non-blocking transaction. - * retval kStatus_Success - * retval #kStatus_I2C_Busy - */ -status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state == (uint8_t)kIdleState) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* There is no necessity to disable interrupts as we read a single integer value */ - *count = handle->transferCount; - return kStatus_Success; -} - -/*! - * brief Terminates a non-blocking I2C master transmission early. - * - * note It is not safe to call this function from an IRQ handler that has a higher priority than the - * I2C peripheral's IRQ priority. - * - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - * retval kStatus_Success A transaction was successfully aborted. - * retval #kStatus_I2C_Timeout Timeout during polling for flags. - */ -status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) -{ - status_t result = kStatus_Success; - uint32_t master_state; - - if (handle->state != (uint8_t)kIdleState) - { - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - - /* Wait until module is ready */ - result = I2C_PendingStatusWait(base); - - if (result != kStatus_Success) - { - handle->state = (uint8_t)kIdleState; - return result; - } - - /* Get the state of the I2C module */ - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if (master_state != (uint32_t)I2C_STAT_MSTCODE_IDLE) - { - /* Send a stop command to finalize the transfer. */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - - /* Wait until the STOP is completed */ - result = I2C_PendingStatusWait(base); - - if (result != kStatus_Success) - { - handle->state = (uint8_t)kIdleState; - return result; - } - } - - /* Reset handle. */ - handle->state = (uint8_t)kIdleState; - handle->checkAddrNack = false; - } - return kStatus_Success; -} - -static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) -{ - struct _i2c_master_transfer *transfer; - - handle->transfer = *xfer; - transfer = &(handle->transfer); - - handle->transferCount = 0; - handle->remainingBytes = transfer->dataSize; - handle->buf = (uint8_t *)transfer->data; - handle->remainingSubaddr = 0; - handle->checkAddrNack = false; - - if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) - { - /* Start condition shall be ommited, switch directly to next phase */ - if (transfer->dataSize == 0U) - { - handle->state = (uint8_t)kStopState; - } - else if (handle->transfer.direction == kI2C_Write) - { - handle->state = (uint8_t)kTransmitDataState; - } - else if (handle->transfer.direction == kI2C_Read) - { - handle->state = (uint8_t)kReceiveDataBeginState; - } - else - { - return kStatus_I2C_InvalidParameter; - } - } - else - { - if (transfer->subaddressSize != 0U) - { - int i; - uint32_t subaddress; - - if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) - { - return kStatus_I2C_InvalidParameter; - } - - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) - { - handle->subaddrBuf[i] = (uint8_t)subaddress & 0xffU; - subaddress >>= 8; - } - handle->remainingSubaddr = transfer->subaddressSize; - } - handle->state = (uint8_t)kStartState; - handle->checkAddrNack = true; - } - - return kStatus_Success; -} - -static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) -{ - uint32_t status; - uint32_t master_state; - struct _i2c_master_transfer *transfer; - status_t err; - - transfer = &(handle->transfer); - bool ignoreNak = ((handle->state == (uint8_t)kWaitForCompletionState) && (handle->remainingBytes == 0U)) -#if I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK - /* If master is nacked by slave after the last byte during transmit, ignore the nack. */ - || ((handle->state == (uint8_t)kStopState) && (handle->remainingBytes == 0U)) -#endif - ; - - *isDone = false; - - status = I2C_GetStatusFlags(base); - - if ((status & I2C_STAT_MSTARBLOSS_MASK) != 0U) - { - I2C_ClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); - return kStatus_I2C_ArbitrationLost; - } - - if ((status & I2C_STAT_MSTSTSTPERR_MASK) != 0U) - { - I2C_ClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); - return kStatus_I2C_StartStopError; - } - - /* Event timeout happens when the time since last bus event has been longer than the time specified by TIMEOUT - register. eg: Start signal fails to generate, no error status is set and transfer hangs if glitch on bus happens - before, the timeout status can be used to avoid the transfer hangs indefinitely. */ - if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) - { - I2C_ClearStatusFlags(base, (uint32_t)kI2C_EventTimeoutFlag); - return kStatus_I2C_EventTimeout; - } - - /* SCL timeout happens when the slave is holding the SCL line low and the time has been longer than the time - specified by TIMEOUT register. */ - if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) - { - I2C_ClearStatusFlags(base, (uint32_t)kI2C_SclTimeoutFlag); - return kStatus_I2C_SclLowTimeout; - } - - if ((status & I2C_STAT_MSTPENDING_MASK) == 0U) - { - return kStatus_I2C_Busy; - } - - /* Get the hardware state of the I2C module */ - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - if (((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || - (master_state == (uint32_t)I2C_STAT_MSTCODE_NACKDAT)) && - (ignoreNak != true)) - { - /* Slave NACKed last byte, issue stop and return error */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = (uint8_t)kWaitForCompletionState; - /* If master is nacked during slave probe or during sending subaddress, return kStatus_I2C_ADDR_Nak. */ - if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (handle->checkAddrNack)) - { - return kStatus_I2C_Addr_Nak; - } - else /* Otherwise just return kStatus_I2C_Nak */ - { - return kStatus_I2C_Nak; - } - } - - err = kStatus_Success; - switch (handle->state) - { - case (uint8_t)kStartState: - if (handle->remainingSubaddr != 0U) - { - /* Subaddress takes precedence over the data transfer, direction is always "write" in this case */ - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1U; - handle->state = (uint8_t)kTransmitSubaddrState; - } - else if (transfer->direction == kI2C_Write) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = (handle->remainingBytes != 0U) ? (uint8_t)kTransmitDataState : (uint8_t)kStopState; - } - else - { - base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; - handle->state = (handle->remainingBytes != 0U) ? (uint8_t)kReceiveDataState : (uint8_t)kStopState; - } - /* Send start condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - break; - - case (uint8_t)kTransmitSubaddrState: - if (master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) - { - return kStatus_I2C_UnexpectedState; - } - /* Most significant subaddress byte comes first */ - base->MSTDAT = handle->subaddrBuf[handle->transfer.subaddressSize - handle->remainingSubaddr]; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - if (--(handle->remainingSubaddr) != 0U) - { - /* There are still subaddress bytes to be transmitted */ - break; - } - if (handle->remainingBytes != 0U) - { - /* There is data to be transferred, if there is write to read turnaround it is necessary to perform - * repeated start */ - handle->state = (transfer->direction == kI2C_Read) ? (uint8_t)kStartState : (uint8_t)kTransmitDataState; - } - else - { - /* No more data, schedule stop condition */ - handle->state = (uint8_t)kStopState; - } - break; - - case (uint8_t)kTransmitDataState: - handle->checkAddrNack = false; - if (master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) - { - return kStatus_I2C_UnexpectedState; - } - base->MSTDAT = *(handle->buf)++; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - if (--handle->remainingBytes == 0U) - { - /* No more data, schedule stop condition */ - handle->state = (uint8_t)kStopState; - } - handle->transferCount++; - break; - - case (uint8_t)kReceiveDataBeginState: - handle->checkAddrNack = false; - if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) - { - return kStatus_I2C_UnexpectedState; - } - (void)base->MSTDAT; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - handle->state = (uint8_t)kReceiveDataState; - break; - - case (uint8_t)kReceiveDataState: - handle->checkAddrNack = false; - if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) - { - return kStatus_I2C_UnexpectedState; - } - *(handle->buf)++ = (uint8_t)base->MSTDAT; - if (--handle->remainingBytes != 0U) - { - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - } - else - { - /* No more data expected, issue NACK and STOP right away */ - if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStopFlag)) - { - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - } - handle->state = (uint8_t)kWaitForCompletionState; - } - handle->transferCount++; - break; - - case (uint8_t)kStopState: - handle->checkAddrNack = false; - if ((transfer->flags & (uint32_t)kI2C_TransferNoStopFlag) != 0U) - { - /* Stop condition is omitted, we are done */ - *isDone = true; - handle->state = (uint8_t)kIdleState; - break; - } - /* Send stop condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = (uint8_t)kWaitForCompletionState; - break; - - case (uint8_t)kWaitForCompletionState: - *isDone = true; - handle->state = (uint8_t)kIdleState; - break; - - case (uint8_t)kIdleState: - default: - /* State machine shall not be invoked again once it enters the idle state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - return err; -} - -/*! - * brief Reusable routine to handle master interrupts. - * note This function does not need to be called unless you are reimplementing the - * nonblocking API's interrupt handler routines to add special functionality. - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - */ -void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle) -{ - bool isDone; - status_t result; - - /* Don't do anything if we don't have a valid handle. */ - if (NULL == handle) - { - return; - } - - result = I2C_RunTransferStateMachine(base, handle, &isDone); - - if ((result != kStatus_Success) || isDone) - { - /* Restore handle to idle state. */ - handle->state = (uint8_t)kIdleState; - - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - - /* Invoke callback. */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } -} - -static void I2C_SlaveInternalStateMachineReset(I2C_Type *base) -{ - I2C_SlaveEnable(base, false); /* clear SLVEN Slave enable bit */ -} - -static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal) -{ - uint32_t dataSetupTime_ns; - - switch ((uint8_t)(busSpeed)) - { - case (uint8_t)kI2C_SlaveStandardMode: - dataSetupTime_ns = 250U; - break; - - case (uint8_t)kI2C_SlaveFastMode: - dataSetupTime_ns = 100U; - break; - - case (uint8_t)kI2C_SlaveFastModePlus: - dataSetupTime_ns = 50U; - break; - - case (uint8_t)kI2C_SlaveHsMode: - dataSetupTime_ns = 10U; - break; - - default: - dataSetupTime_ns = 0U; - break; - } - - if (0U == dataSetupTime_ns) - { - return kStatus_InvalidArgument; - } - - /* divVal = (sourceClock_Hz / 1000000) * (dataSetupTime_ns / 1000) */ - *divVal = srcClock_Hz / 1000U; - *divVal = (*divVal) * dataSetupTime_ns; - *divVal = (*divVal) / 1000000U; - - if ((*divVal) > I2C_CLKDIV_DIVVAL_MASK) - { - *divVal = I2C_CLKDIV_DIVVAL_MASK; - } - - return kStatus_Success; -} - -static uint32_t I2C_SlavePollPending(I2C_Type *base) -{ - uint32_t stat; - -#if I2C_RETRY_TIMES != 0U - uint32_t waitTimes = I2C_RETRY_TIMES; -#endif - do - { - stat = base->STAT; -#if I2C_RETRY_TIMES != 0U - waitTimes--; - } while ((0U == (stat & I2C_STAT_SLVPENDING_MASK)) && (waitTimes != 0U)); - - if (waitTimes == 0U) - { - return (uint32_t)kStatus_I2C_Timeout; - } -#else - } while (0U == (stat & I2C_STAT_SLVPENDING_MASK)); -#endif - - return stat; -} - -static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event) -{ - uint32_t eventMask = handle->transfer.eventMask; - handle->transfer.event = event; - if (((handle->callback) != NULL) && ((eventMask & (uint32_t)event) != 0U)) - { - handle->callback(base, &handle->transfer, handle->userData); - - size_t txSize = handle->transfer.txSize; - size_t rxSize = handle->transfer.rxSize; - /* if after event callback we have data buffer (callback func has added new data), keep transfer busy */ - if (false == handle->isBusy) - { - if (((handle->transfer.txData != NULL) && (txSize != 0U)) || - ((handle->transfer.rxData != NULL) && (rxSize != 0U))) - { - handle->isBusy = true; - } - } - - /* Clear the transferred count now that we have a new buffer. */ - if ((event == kI2C_SlaveReceiveEvent) || (event == kI2C_SlaveTransmitEvent)) - { - handle->transfer.transferredCount = 0; - } - } -} - -static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle) -{ - uint8_t addressByte0; - size_t txSize; - size_t rxSize; - - addressByte0 = (uint8_t)base->SLVDAT; - - /* store the matched address */ - handle->transfer.receivedAddress = addressByte0; - - /* R/nW */ - if ((addressByte0 & 1U) != 0U) - { - txSize = handle->transfer.txSize; - /* if we have no data in this transfer, call callback to get new */ - if ((handle->transfer.txData == NULL) || (txSize == 0U)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); - } - - txSize = handle->transfer.txSize; - /* NACK if we have no data in this transfer. */ - if ((handle->transfer.txData == NULL) || (txSize == 0U)) - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - return false; - } - - /* master wants to read, so slave transmit is next state */ - handle->slaveFsm = kI2C_SlaveFsmTransmit; - } - else - { - rxSize = handle->transfer.rxSize; - /* if we have no receive buffer in this transfer, call callback to get new */ - if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); - } - - rxSize = handle->transfer.rxSize; - /* NACK if we have no data in this transfer */ - if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - return false; - } - - /* master wants write, so slave receive is next state */ - handle->slaveFsm = kI2C_SlaveFsmReceive; - } - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - return true; -} - -static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, - i2c_slave_handle_t *handle, - const void *txData, - size_t txSize, - void *rxData, - size_t rxSize, - uint32_t eventMask) -{ - assert(handle != NULL); - - status_t status; - status = kStatus_Success; - - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); - - /* Return busy if another transaction is in progress. */ - if (handle->isBusy) - { - status = kStatus_I2C_Busy; - } - - /* Save transfer into handle. */ - handle->transfer.txData = (const uint8_t *)txData; - handle->transfer.txSize = txSize; - handle->transfer.rxData = (uint8_t *)rxData; - handle->transfer.rxSize = rxSize; - handle->transfer.transferredCount = 0; - handle->transfer.eventMask = eventMask | (uint32_t)kI2C_SlaveTransmitEvent | (uint32_t)kI2C_SlaveReceiveEvent; - handle->isBusy = true; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* Clear w1c flags. */ - base->STAT |= 0u; - - /* Enable I2C internal IRQ sources. */ - I2C_EnableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); - - return status; -} - -/*! - * brief Starts accepting master read from slave requests. - * - * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * param base The I2C peripheral base address. - * param transfer Pointer to #i2c_slave_transfer_t structure. - * param txData Pointer to data to send to master. - * param txSize Size of txData in bytes. - * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * retval kStatus_Success Slave transfers were successfully started. - * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetSendBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, txData, txSize, NULL, 0u, eventMask); -} - -/*! - * brief Starts accepting master write to slave requests. - * - * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * param base The I2C peripheral base address. - * param transfer Pointer to #i2c_slave_transfer_t structure. - * param rxData Pointer to data to store data from master. - * param rxSize Size of rxData in bytes. - * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * retval kStatus_Success Slave transfers were successfully started. - * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetReceiveBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, NULL, 0u, rxData, rxSize, eventMask); -} - -/*! - * brief Configures Slave Address n register. - * - * This function writes new value to Slave Address register. - * - * param base The I2C peripheral base address. - * param addressRegister The module supports multiple address registers. The parameter determines which one shall be - * changed. - * param address The slave address to be stored to the address register for matching. - * param addressDisable Disable matching of the specified address register. - */ -void I2C_SlaveSetAddress(I2C_Type *base, - i2c_slave_address_register_t addressRegister, - uint8_t address, - bool addressDisable) -{ - base->SLVADR[addressRegister] = I2C_SLVADR_SLVADR(address) | I2C_SLVADR_SADISABLE(addressDisable); -} - -/*! - * brief Provides a default configuration for the I2C slave peripheral. - * - * This function provides the following default configuration for the I2C slave peripheral: - * code - * slaveConfig->enableSlave = true; - * slaveConfig->address0.disable = false; - * slaveConfig->address0.address = 0u; - * slaveConfig->address1.disable = true; - * slaveConfig->address2.disable = true; - * slaveConfig->address3.disable = true; - * slaveConfig->busSpeed = kI2C_SlaveStandardMode; - * endcode - * - * After calling this function, override any settings to customize the configuration, - * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the a - * address0.address member of the configuration structure with the desired slave address. - * - * param[out] slaveConfig User provided configuration structure that is set to default values. Refer to - * #i2c_slave_config_t. - */ -void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) -{ - assert(slaveConfig != NULL); - - i2c_slave_config_t mySlaveConfig = {0}; - - /* default config enables slave address 0 match to general I2C call address zero */ - mySlaveConfig.enableSlave = true; - mySlaveConfig.address1.addressDisable = true; - mySlaveConfig.address2.addressDisable = true; - mySlaveConfig.address3.addressDisable = true; - - *slaveConfig = mySlaveConfig; -} - -/*! - * brief Initializes the I2C slave peripheral. - * - * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user - * provided configuration. - * - * param base The I2C peripheral base address. - * param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults - * that you can override. - * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide - * enough - * data setup time for master when slave stretches the clock. - */ -status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz) -{ - status_t status; - uint32_t divVal = 0; - - /* configure data setup time used when slave stretches clock */ - status = I2C_SlaveDivVal(srcClock_Hz, slaveConfig->busSpeed, &divVal); - if (kStatus_Success != status) - { - return status; - } - - (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); - - /* I2C Clock Divider register */ - base->CLKDIV = divVal; - - /* set Slave address */ - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister0, slaveConfig->address0.address, - slaveConfig->address0.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister1, slaveConfig->address1.address, - slaveConfig->address1.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister2, slaveConfig->address2.address, - slaveConfig->address2.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister3, slaveConfig->address3.address, - slaveConfig->address3.addressDisable); - - /* set Slave address 0 qual */ - base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(slaveConfig->qualMode) | I2C_SLVQUAL0_SLVQUAL0(slaveConfig->qualAddress); - - /* set Slave enable */ - base->CFG = I2C_CFG_SLVEN(slaveConfig->enableSlave); - - return status; -} - -/*! - * brief Deinitializes the I2C slave peripheral. - * - * This function disables the I2C slave peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * param base The I2C peripheral base address. - */ -void I2C_SlaveDeinit(I2C_Type *base) -{ - I2C_SlaveEnable(base, false); -} - -/*! - * brief Performs a polling send transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * param base The I2C peripheral base address. - * param txBuff The pointer to the data to be transferred. - * param txSize The length in bytes of the data to be transferred. - * return kStatus_Success Data has been sent. - * return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). - */ -status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) -{ - const uint8_t *buf = txBuff; - uint32_t stat; - bool slaveAddress; - bool slaveTransmit; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - - /* Get slave machine state */ - slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); - slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_TX); - - /* in I2C_SlaveSend() it shall be either slaveAddress or slaveTransmit */ - if (!(slaveAddress || slaveTransmit)) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - if (slaveAddress) - { - /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - - /* send bytes up to txSize */ - while (txSize != 0U) - { - slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_TX); - - if (!slaveTransmit) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - /* Write 8 bits of data to the SLVDAT register */ - base->SLVDAT = I2C_SLVDAT_DATA(*buf); - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* advance counters and pointers for next data */ - buf++; - txSize--; - - if (txSize != 0U) - { - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - } - - return kStatus_Success; -} - -/*! - * brief Performs a polling receive transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * param base The I2C peripheral base address. - * param rxBuff The pointer to the data to be transferred. - * param rxSize The length in bytes of the data to be transferred. - * return kStatus_Success Data has been received. - * return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). - */ -status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) -{ - uint8_t *buf = rxBuff; - uint32_t stat; - bool slaveAddress; - bool slaveReceive; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - - /* Get slave machine state */ - slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); - slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_RX); - - /* in I2C_SlaveReceive() it shall be either slaveAddress or slaveReceive */ - if (!(slaveAddress || slaveReceive)) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - if (slaveAddress) - { - /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - - /* receive bytes up to rxSize */ - while (rxSize != 0U) - { - slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_RX); - - if (!slaveReceive) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - /* Read 8 bits of data from the SLVDAT register */ - *buf = (uint8_t)base->SLVDAT; - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* advance counters and pointers for next data */ - buf++; - rxSize--; - - if (rxSize != 0U) - { - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - } - - return kStatus_Success; -} - -/*! - * brief Creates a new handle for the I2C slave non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. - * - * param base The I2C peripheral base address. - * param[out] handle Pointer to the I2C slave driver handle. - * param callback User provided pointer to the asynchronous callback function. - * param userData User provided pointer to the application callback data. - */ -void I2C_SlaveTransferCreateHandle(I2C_Type *base, - i2c_slave_handle_t *handle, - i2c_slave_transfer_callback_t callback, - void *userData) -{ - assert(handle != NULL); - - uint32_t instance; - i2c_to_flexcomm_t handler; - handler.i2c_slave_handler = I2C_SlaveTransferHandleIRQ; - - /* Clear out the handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Save base and instance. */ - handle->callback = callback; - handle->userData = userData; - - /* initialize fsm */ - handle->slaveFsm = kI2C_SlaveFsmAddressMatch; - - /* store pointer to handle into transfer struct */ - handle->transfer.handle = handle; - - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); - (void)EnableIRQ(s_i2cIRQ[instance]); -} - -/*! - * brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. - * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. - * - * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * param base The I2C peripheral base address. - * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * retval kStatus_Success Slave transfers were successfully started. - * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, handle, NULL, 0u, NULL, 0u, eventMask); -} - -/*! - * brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. - * - * param base I2C base pointer. - * param handle pointer to i2c_slave_handle_t structure. - * param count Number of bytes transferred so far by the non-blocking transaction. - * retval kStatus_InvalidArgument count is Invalid. - * retval kStatus_Success Successfully return the count. - */ -status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (!handle->isBusy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* For an active transfer, just return the count from the handle. */ - *count = handle->transfer.transferredCount; - - return kStatus_Success; -} - -/*! - * brief Aborts the slave non-blocking transfers. - * note This API could be called at any time to stop slave for handling the bus events. - * param base The I2C peripheral base address. - * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * retval kStatus_Success - * retval #kStatus_I2C_Idle - */ -void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) -{ - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); - - /* Set the SLVEN bit to 0 in the CFG register. */ - I2C_SlaveEnable(base, false); - - handle->isBusy = false; - handle->transfer.txSize = 0U; - handle->transfer.rxSize = 0U; -} - -/*! - * brief Reusable routine to handle slave interrupts. - * note This function does not need to be called unless you are reimplementing the - * non blocking API's interrupt handler routines to add special functionality. - * param base The I2C peripheral base address. - * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - */ -void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle) -{ - uint32_t i2cStatus = base->STAT; - uint8_t tmpdata; - size_t txSize; - size_t rxSize; - - if ((i2cStatus & I2C_STAT_SLVDESEL_MASK) != 0U) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveDeselectedEvent); - I2C_SlaveClearStatusFlags(base, I2C_STAT_SLVDESEL_MASK); - } - - /* SLVPENDING flag is cleared by writing I2C_SLVCTL_SLVCONTINUE_MASK to SLVCTL register */ - if ((i2cStatus & I2C_STAT_SLVPENDING_MASK) != 0U) - { - bool slaveAddress = - (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); - - if (slaveAddress) - { - (void)I2C_SlaveAddressIRQ(base, handle); - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveAddressMatchEvent); - } - else - { - switch (handle->slaveFsm) - { - case kI2C_SlaveFsmReceive: - { - bool slaveReceive = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == - (uint32_t)I2C_STAT_SLVST_RX); - - if (slaveReceive) - { - rxSize = handle->transfer.rxSize; - /* if we have no receive buffer in this transfer, call callback to get new */ - if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); - } - - rxSize = handle->transfer.rxSize; - /* receive a byte */ - if ((handle->transfer.rxData != NULL) && (rxSize != 0U)) - { - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - tmpdata = (uint8_t)base->SLVDAT; - *(handle->transfer.rxData) = tmpdata; - (handle->transfer.rxSize)--; - (handle->transfer.rxData)++; - (handle->transfer.transferredCount)++; - } - - rxSize = handle->transfer.rxSize; - txSize = handle->transfer.txSize; - /* is this last transaction for this transfer? allow next transaction */ - if ((0U == rxSize) && (0U == txSize)) - { - handle->isBusy = false; - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); - } - } - else - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - } - } - break; - - case kI2C_SlaveFsmTransmit: - { - bool slaveTransmit = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == - (uint32_t)I2C_STAT_SLVST_TX); - - if (slaveTransmit) - { - txSize = handle->transfer.txSize; - /* if we have no data in this transfer, call callback to get new */ - if ((handle->transfer.txData == NULL) || (txSize == 0U)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); - } - - txSize = handle->transfer.txSize; - /* transmit a byte */ - if ((handle->transfer.txData != NULL) && (txSize != 0U)) - { - base->SLVDAT = *(handle->transfer.txData); - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - (handle->transfer.txSize)--; - (handle->transfer.txData)++; - (handle->transfer.transferredCount)++; - } - - rxSize = handle->transfer.rxSize; - txSize = handle->transfer.txSize; - /* is this last transaction for this transfer? allow next transaction */ - if ((0U == rxSize) && (0U == txSize)) - { - handle->isBusy = false; - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); - } - } - else - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - } - } - break; - - default: - /* incorrect state, slv_abort()? */ - break; - } - } - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c.h deleted file mode 100644 index b521a1ad756..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c.h +++ /dev/null @@ -1,1148 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2C_H_ -#define _FSL_I2C_H_ - -#include -#include "fsl_device_registers.h" -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define I2C_CFG_MASK 0x1f - -/*! - * @addtogroup i2c_driver - * @{ - */ - -/*! @file */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2C driver version. */ -#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) -/*@}*/ - -/*! @brief Retry times for waiting flag. */ -#ifndef I2C_RETRY_TIMES -#define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ -#endif - -/*! @brief Whether to ignore the nack signal of the last byte during master transmit. */ -#ifndef I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK -#define I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK \ - 1U /* Define to one means master ignores the last byte's nack and considers the transfer successful. */ -#endif - -/* definitions for MSTCODE bits in I2C Status register STAT */ -#define I2C_STAT_MSTCODE_IDLE (0U) /*!< Master Idle State Code */ -#define I2C_STAT_MSTCODE_RXREADY (1U) /*!< Master Receive Ready State Code */ -#define I2C_STAT_MSTCODE_TXREADY (2U) /*!< Master Transmit Ready State Code */ -#define I2C_STAT_MSTCODE_NACKADR (3U) /*!< Master NACK by slave on address State Code */ -#define I2C_STAT_MSTCODE_NACKDAT (4U) /*!< Master NACK by slave on data State Code */ - -/* definitions for SLVSTATE bits in I2C Status register STAT */ -#define I2C_STAT_SLVST_ADDR (0) -#define I2C_STAT_SLVST_RX (1) -#define I2C_STAT_SLVST_TX (2) - -/*! @brief I2C status return codes. */ -enum -{ - kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 0), /*!< The master is already performing a transfer. */ - kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 1), /*!< The slave driver is idle. */ - kStatus_I2C_Nak = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 2), /*!< The slave device sent a NAK in response to a byte. */ - kStatus_I2C_InvalidParameter = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 3), /*!< Unable to proceed due to invalid parameter. */ - kStatus_I2C_BitError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 4), /*!< Transferred bit was not seen on the bus. */ - kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 5), /*!< Arbitration lost error. */ - kStatus_I2C_NoTransferInProgress = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 6), /*!< Attempt to abort a transfer when one is not in progress. */ - kStatus_I2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */ - kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8), /*!< Start and stop error. */ - kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9), /*!< Unexpected state. */ - kStatus_I2C_Timeout = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, - 10), /*!< Timeout when waiting for I2C master/slave pending status to set to continue transfer. */ - kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 11), /*!< NAK received for Address */ - kStatus_I2C_EventTimeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 12), /*!< Timeout waiting for bus event. */ - kStatus_I2C_SclLowTimeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 13), /*!< Timeout SCL signal remains low. */ -}; - -/*! @} */ - -/*! - * @addtogroup i2c_driver - * @{ - */ - -/*! - * @brief I2C status flags. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -enum _i2c_status_flags -{ - kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. bit 0 */ - kI2C_MasterArbitrationLostFlag = - I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus. bit 4*/ - kI2C_MasterStartStopErrorFlag = - I2C_STAT_MSTSTSTPERR_MASK, /*!< There was an error during start or stop phase of the transaction. bit 6 */ - kI2C_MasterIdleFlag = 1UL << 5U, /*!< The I2C master idle status. bit 5 */ - kI2C_MasterRxReadyFlag = 1UL << I2C_STAT_MSTSTATE_SHIFT, /*!< The I2C master rx ready status. bit 1 */ - kI2C_MasterTxReadyFlag = 1UL << (I2C_STAT_MSTSTATE_SHIFT + 1U), /*!< The I2C master tx ready status. bit 2 */ - kI2C_MasterAddrNackFlag = 1UL << 7U, /*!< The I2C master address nack status. bit 7 */ - kI2C_MasterDataNackFlag = 1UL << (I2C_STAT_MSTSTATE_SHIFT + 2U), /*!< The I2C master data nack status. bit 3 */ - kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. bit 8 */ - kI2C_SlaveNotStretching = I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 - = yes, 1 = no). bit 11 */ - kI2C_SlaveSelected = - I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. bit 14 */ - kI2C_SaveDeselected = I2C_STAT_SLVDESEL_MASK, /*!< Indicates that slave was previously deselected (deselect event - took place, w1c). bit 15 */ - kI2C_SlaveAddressedFlag = 1UL << 22U, /*!< One of the I2C slave's 4 addresses is matched. bit 22 */ - kI2C_SlaveReceiveFlag = 1UL << I2C_STAT_SLVSTATE_SHIFT, /*!< Slave receive data available. bit 9 */ - kI2C_SlaveTransmitFlag = 1UL << (I2C_STAT_SLVSTATE_SHIFT + 1U), /*!< Slave data can be transmitted. bit 10 */ - kI2C_SlaveAddress0MatchFlag = 1UL << 20U, /*!< Slave address0 match. bit 20 */ - kI2C_SlaveAddress1MatchFlag = 1UL << I2C_STAT_SLVIDX_SHIFT, /*!< Slave address1 match. bit 12 */ - kI2C_SlaveAddress2MatchFlag = 1UL << (I2C_STAT_SLVIDX_SHIFT + 1U), /*!< Slave address2 match. bit 13 */ - kI2C_SlaveAddress3MatchFlag = 1UL << 21U, /*!< Slave address3 match. bit 21 */ - kI2C_MonitorReadyFlag = I2C_STAT_MONRDY_MASK, /*!< The I2C monitor ready interrupt. bit 16 */ - kI2C_MonitorOverflowFlag = I2C_STAT_MONOV_MASK, /*!< The monitor data overrun interrupt. bit 17 */ - kI2C_MonitorActiveFlag = I2C_STAT_MONACTIVE_MASK, /*!< The monitor is active. bit 18 */ - kI2C_MonitorIdleFlag = I2C_STAT_MONIDLE_MASK, /*!< The monitor idle interrupt. bit 19 */ - kI2C_EventTimeoutFlag = I2C_STAT_EVENTTIMEOUT_MASK, /*!< The bus event timeout interrupt. bit 24 */ - kI2C_SclTimeoutFlag = I2C_STAT_SCLTIMEOUT_MASK, /*!< The SCL timeout interrupt. bit 25 */ - - /* All master flags that can be cleared by software */ - kI2C_MasterAllClearFlags = kI2C_MasterArbitrationLostFlag | kI2C_MasterStartStopErrorFlag, - /* All slave flags that can be cleared by software */ - kI2C_SlaveAllClearFlags = kI2C_SaveDeselected, - /* All common flags that can be cleared by software */ - kI2C_CommonAllClearFlags = - kI2C_MonitorOverflowFlag | kI2C_MonitorIdleFlag | kI2C_EventTimeoutFlag | kI2C_SclTimeoutFlag, -}; - -/*! - * @brief I2C interrupt enable. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -enum _i2c_interrupt_enable -{ - kI2C_MasterPendingInterruptEnable = - I2C_STAT_MSTPENDING_MASK, /*!< The I2C master communication pending interrupt. */ - kI2C_MasterArbitrationLostInterruptEnable = - I2C_STAT_MSTARBLOSS_MASK, /*!< The I2C master arbitration lost interrupt. */ - kI2C_MasterStartStopErrorInterruptEnable = - I2C_STAT_MSTSTSTPERR_MASK, /*!< The I2C master start/stop timing error interrupt. */ - kI2C_SlavePendingInterruptEnable = I2C_STAT_SLVPENDING_MASK, /*!< The I2C slave communication pending interrupt. */ - kI2C_SlaveNotStretchingInterruptEnable = - I2C_STAT_SLVNOTSTR_MASK, /*!< The I2C slave not streching interrupt, deep-sleep mode can be entered only when - this interrupt occurs. */ - kI2C_SlaveDeselectedInterruptEnable = I2C_STAT_SLVDESEL_MASK, /*!< The I2C slave deselection interrupt. */ - kI2C_MonitorReadyInterruptEnable = I2C_STAT_MONRDY_MASK, /*!< The I2C monitor ready interrupt. */ - kI2C_MonitorOverflowInterruptEnable = I2C_STAT_MONOV_MASK, /*!< The monitor data overrun interrupt. */ - kI2C_MonitorIdleInterruptEnable = I2C_STAT_MONIDLE_MASK, /*!< The monitor idle interrupt. */ - kI2C_EventTimeoutInterruptEnable = I2C_STAT_EVENTTIMEOUT_MASK, /*!< The bus event timeout interrupt. */ - kI2C_SclTimeoutInterruptEnable = I2C_STAT_SCLTIMEOUT_MASK, /*!< The SCL timeout interrupt. */ - - /* All master interrupt sources */ - kI2C_MasterAllInterruptEnable = kI2C_MasterPendingInterruptEnable | kI2C_MasterArbitrationLostInterruptEnable | - kI2C_MasterStartStopErrorInterruptEnable, - /* All slave interrupt sources */ - kI2C_SlaveAllInterruptEnable = - kI2C_SlavePendingInterruptEnable | kI2C_SlaveNotStretchingInterruptEnable | kI2C_SlaveDeselectedInterruptEnable, - /* All common interrupt sources */ - kI2C_CommonAllInterruptEnable = kI2C_MonitorReadyInterruptEnable | kI2C_MonitorOverflowInterruptEnable | - kI2C_MonitorIdleInterruptEnable | kI2C_EventTimeoutInterruptEnable | - kI2C_SclTimeoutInterruptEnable, -}; -/*! @} */ - -/*! - * @addtogroup i2c_master_driver - * @{ - */ - -/*! @brief Direction of master and slave transfers. */ -typedef enum _i2c_direction -{ - kI2C_Write = 0U, /*!< Master transmit. */ - kI2C_Read = 1U /*!< Master receive. */ -} i2c_direction_t; - -/*! - * @brief Structure with settings to initialize the I2C master module. - * - * This structure holds configuration settings for the I2C peripheral. To initialize this - * structure to reasonable defaults, call the I2C_MasterGetDefaultConfig() function and - * pass a pointer to your configuration structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _i2c_master_config -{ - bool enableMaster; /*!< Whether to enable master mode. */ - uint32_t baudRate_Bps; /*!< Desired baud rate in bits per second. */ - bool enableTimeout; /*!< Enable internal timeout function. */ - uint8_t timeout_Ms; /*!< Event timeout and SCL low timeout value. */ -} i2c_master_config_t; - -/* Forward declaration of the transfer descriptor and handle typedefs. */ -/*! @brief I2C master transfer typedef */ -typedef struct _i2c_master_transfer i2c_master_transfer_t; - -/*! @brief I2C master handle typedef */ -typedef struct _i2c_master_handle i2c_master_handle_t; - -/*! - * @brief Master completion callback function pointer type. - * - * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use - * in the call to I2C_MasterTransferCreateHandle(). - * - * @param base The I2C peripheral base address. - * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, - i2c_master_handle_t *handle, - status_t completionStatus, - void *userData); - -/*! - * @brief Transfer option flags. - * - * @note These enumerations are intended to be OR'd together to form a bit mask of options for - * the #_i2c_master_transfer::flags field. - */ -enum _i2c_master_transfer_flags -{ - kI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ - kI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ - kI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ - kI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ -}; - -/*! @brief States for the state machine used by transactional APIs. */ -enum _i2c_transfer_states -{ - kIdleState = 0, - kTransmitSubaddrState, - kTransmitDataState, - kReceiveDataBeginState, - kReceiveDataState, - kReceiveLastDataState, - kStartState, - kStopState, - kWaitForCompletionState -}; - -/*! - * @brief Non-blocking transfer descriptor structure. - * - * This structure is used to pass transaction parameters to the I2C_MasterTransferNonBlocking() API. - */ -struct _i2c_master_transfer -{ - uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i2c_master_transfer_flags for available - options. Set to 0 or #kI2C_TransferDefaultFlag for normal transfers. */ - uint8_t slaveAddress; /*!< The 7-bit slave address. */ - i2c_direction_t direction; /*!< Either #kI2C_Read or #kI2C_Write. */ - uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ - size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ - void *data; /*!< Pointer to data to transfer. */ - size_t dataSize; /*!< Number of bytes to transfer. */ -}; - -/*! - * @brief Driver handle for master non-blocking APIs. - * @note The contents of this structure are private and subject to change. - */ -struct _i2c_master_handle -{ - uint8_t state; /*!< Transfer state machine current state. */ - uint32_t transferCount; /*!< Indicates progress of the transfer */ - uint32_t remainingBytes; /*!< Remaining byte count in current state. */ - uint8_t *buf; /*!< Buffer pointer for current state. */ - uint32_t remainingSubaddr; - uint8_t subaddrBuf[4]; - bool checkAddrNack; /*!< Whether to check the nack signal is detected during addressing. */ - i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ - i2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ - void *userData; /*!< Application data passed to callback. */ -}; - -/*! @} */ - -/*! - * @addtogroup i2c_slave_driver - * @{ - */ -/*! @brief I2C slave address register. */ -typedef enum _i2c_slave_address_register -{ - kI2C_SlaveAddressRegister0 = 0U, /*!< Slave Address 0 register. */ - kI2C_SlaveAddressRegister1 = 1U, /*!< Slave Address 1 register. */ - kI2C_SlaveAddressRegister2 = 2U, /*!< Slave Address 2 register. */ - kI2C_SlaveAddressRegister3 = 3U, /*!< Slave Address 3 register. */ -} i2c_slave_address_register_t; - -/*! @brief Data structure with 7-bit Slave address and Slave address disable. */ -typedef struct _i2c_slave_address -{ - uint8_t address; /*!< 7-bit Slave address SLVADR. */ - bool addressDisable; /*!< Slave address disable SADISABLE. */ -} i2c_slave_address_t; - -/*! @brief I2C slave address match options. */ -typedef enum _i2c_slave_address_qual_mode -{ - kI2C_QualModeMask = 0U, /*!< The SLVQUAL0 field (qualAddress) is used as a logical mask for matching address0. */ - kI2C_QualModeExtend = - 1U, /*!< The SLVQUAL0 (qualAddress) field is used to extend address 0 matching in a range of addresses. */ -} i2c_slave_address_qual_mode_t; - -/*! @brief I2C slave bus speed options. */ -typedef enum _i2c_slave_bus_speed -{ - kI2C_SlaveStandardMode = 0U, - kI2C_SlaveFastMode = 1U, - kI2C_SlaveFastModePlus = 2U, - kI2C_SlaveHsMode = 3U, -} i2c_slave_bus_speed_t; - -/*! - * @brief Structure with settings to initialize the I2C slave module. - * - * This structure holds configuration settings for the I2C slave peripheral. To initialize this - * structure to reasonable defaults, call the I2C_SlaveGetDefaultConfig() function and - * pass a pointer to your configuration structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _i2c_slave_config -{ - i2c_slave_address_t address0; /*!< Slave's 7-bit address and disable. */ - i2c_slave_address_t address1; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_t address2; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_t address3; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_qual_mode_t qualMode; /*!< Qualify mode for slave address 0. */ - uint8_t qualAddress; /*!< Slave address qualifier for address 0. */ - i2c_slave_bus_speed_t - busSpeed; /*!< Slave bus speed mode. If the slave function stretches SCL to allow for software response, it must - provide sufficient data setup time to the master before releasing the stretched clock. - This is accomplished by inserting one clock time of CLKDIV at that point. - The #busSpeed value is used to configure CLKDIV - such that one clock time is greater than the tSU;DAT value noted - in the I2C bus specification for the I2C mode that is being used. - If the #busSpeed mode is unknown at compile time, use the longest data setup time - kI2C_SlaveStandardMode (250 ns) */ - bool enableSlave; /*!< Enable slave mode. */ -} i2c_slave_config_t; - -/*! - * @brief Set of events sent to the callback for non blocking slave transfers. - * - * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together - * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable. - * Then, when the slave callback is invoked, it is passed the current event through its @a transfer - * parameter. - * - * @note These enumerations are meant to be OR'd together to form a bit mask of events. - */ -typedef enum _i2c_slave_transfer_event -{ - kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ - kI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit - (slave-transmitter role). */ - kI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received - data (slave-receiver role). */ - kI2C_SlaveCompletionEvent = 0x20U, /*!< All data in the active transfer have been consumed. */ - kI2C_SlaveDeselectedEvent = - 0x40U, /*!< The slave function has become deselected (SLVSEL flag changing from 1 to 0. */ - - /*! Bit mask of all available events. */ - kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | - kI2C_SlaveCompletionEvent | kI2C_SlaveDeselectedEvent, -} i2c_slave_transfer_event_t; - -/*! @brief I2C slave handle typedef. */ -typedef struct _i2c_slave_handle i2c_slave_handle_t; - -/*! @brief I2C slave transfer structure */ -typedef struct _i2c_slave_transfer -{ - i2c_slave_handle_t *handle; /*!< Pointer to handle that contains this transfer. */ - i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ - uint8_t receivedAddress; /*!< Matching address send by master. 7-bits plus R/nW bit0 */ - uint32_t eventMask; /*!< Mask of enabled events. */ - uint8_t *rxData; /*!< Transfer buffer for receive data */ - const uint8_t *txData; /*!< Transfer buffer for transmit data */ - size_t txSize; /*!< Transfer size */ - size_t rxSize; /*!< Transfer size */ - size_t transferredCount; /*!< Number of bytes transferred during this transfer. */ - status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for - #kI2C_SlaveCompletionEvent. */ -} i2c_slave_transfer_t; - -/*! - * @brief Slave event callback function pointer type. - * - * This callback is used only for the slave non-blocking transfer API. To install a callback, - * use the I2C_SlaveSetCallback() function after you have created a handle. - * - * @param base Base address for the I2C instance on which the event occurred. - * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *userData); - -/*! - * @brief I2C slave software finite state machine states. - */ -typedef enum _i2c_slave_fsm -{ - kI2C_SlaveFsmAddressMatch = 0u, - kI2C_SlaveFsmReceive = 2u, - kI2C_SlaveFsmTransmit = 3u, -} i2c_slave_fsm_t; - -/*! - * @brief I2C slave handle structure. - * @note The contents of this structure are private and subject to change. - */ -struct _i2c_slave_handle -{ - volatile i2c_slave_transfer_t transfer; /*!< I2C slave transfer. */ - volatile bool isBusy; /*!< Whether transfer is busy. */ - volatile i2c_slave_fsm_t slaveFsm; /*!< slave transfer state machine. */ - i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ - void *userData; /*!< Callback parameter passed to callback. */ -}; - -/*! @brief Typedef for master interrupt handler. */ -typedef void (*flexcomm_i2c_master_irq_handler_t)(I2C_Type *base, i2c_master_handle_t *handle); - -/*! @brief Typedef for slave interrupt handler. */ -typedef void (*flexcomm_i2c_slave_irq_handler_t)(I2C_Type *base, i2c_slave_handle_t *handle); -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup i2c_master_driver - * @{ - */ - -/*! @name Initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the I2C master peripheral. - * - * This function provides the following default configuration for the I2C master peripheral: - * @code - * masterConfig->enableMaster = true; - * masterConfig->baudRate_Bps = 100000U; - * masterConfig->enableTimeout = false; - * @endcode - * - * After calling this function, you can override any settings in order to customize the configuration, - * prior to initializing the master driver with I2C_MasterInit(). - * - * @param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. - */ -void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); - -/*! - * @brief Initializes the I2C master peripheral. - * - * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user - * provided configuration. A software reset is performed prior to configuration. - * - * @param base The I2C peripheral base address. - * @param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of - * defaults - * that you can override. - * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, - * filter widths, and timeout periods. - */ -void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes the I2C master peripheral. - * - * This function disables the I2C master peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -void I2C_MasterDeinit(I2C_Type *base); - -/*! - * @brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * @param base The I2C peripheral base address. - * @return I2C instance number starting from 0. - */ -uint32_t I2C_GetInstance(I2C_Type *base); - -/*! - * @brief Performs a software reset. - * - * Restores the I2C master peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -static inline void I2C_MasterReset(I2C_Type *base) -{ -} - -/*! - * @brief Enables or disables the I2C module as master. - * - * @param base The I2C peripheral base address. - * @param enable Pass true to enable or false to disable the specified I2C as master. - */ -static inline void I2C_MasterEnable(I2C_Type *base, bool enable) -{ - if (enable) - { - base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK; - } - else - { - base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK; - } -} - -/*@}*/ - -/*! @name Status */ -/*@{*/ -/*! - * @brief Gets the I2C status flags. - * - * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit - * in the return value is set if the flag is asserted. - * - * @param base The I2C peripheral base address. - * @return State of the status flags: - * - 1: related status flag is set. - * - 0: related status flag is not set. - * @see @ref _i2c_status_flags. - */ -uint32_t I2C_GetStatusFlags(I2C_Type *base); - -/*! - * @brief Clears the I2C status flag state. - * - * Refer to kI2C_CommonAllClearStatusFlags, kI2C_MasterAllClearStatusFlags and kI2C_SlaveAllClearStatusFlags to see - * the clearable flags. Attempts to clear other flags has no effect. - * - * @param base The I2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of the members in - * kI2C_CommonAllClearStatusFlags, kI2C_MasterAllClearStatusFlags and kI2C_SlaveAllClearStatusFlags. You may pass - * the result of a previous call to I2C_GetStatusFlags(). - * @see #_i2c_status_flags, _i2c_master_status_flags and _i2c_slave_status_flags. - */ -static inline void I2C_ClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - /* Only deal with the clearable flags */ - statusMask &= - ((uint32_t)kI2C_CommonAllClearFlags | (uint32_t)kI2C_MasterAllClearFlags | (uint32_t)kI2C_SlaveAllClearFlags); - base->STAT = statusMask; -} - -/*! - * @brief Clears the I2C master status flag state. - * @deprecated Do not use this function. It has been superceded by @ref I2C_ClearStatusFlags - * The following status register flags can be cleared: - * - #kI2C_MasterArbitrationLostFlag - * - #kI2C_MasterStartStopErrorFlag - * - * Attempts to clear other flags has no effect. - * - * @param base The I2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * #_i2c_status_flags enumerators OR'd together. You may pass the result of a previous call to - * I2C_GetStatusFlags(). - * @see _i2c_status_flags. - */ -static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - /* Allow clearing just master status flags */ - base->STAT = statusMask & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); -} - -/*@}*/ - -/*! @name Interrupts */ -/*@{*/ - -/*! - * @brief Enables the I2C interrupt requests. - * - * @param base The I2C peripheral base address. - * @param interruptMask Bit mask of interrupts to enable. See #_i2c_interrupt_enable for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2C_EnableInterrupts(I2C_Type *base, uint32_t interruptMask) -{ - base->INTENSET = interruptMask; -} - -/*! - * @brief Disables the I2C interrupt requests. - * - * @param base The I2C peripheral base address. - * @param interruptMask Bit mask of interrupts to disable. See #_i2c_interrupt_enable for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2C_DisableInterrupts(I2C_Type *base, uint32_t interruptMask) -{ - base->INTENCLR = interruptMask; -} - -/*! - * @brief Returns the set of currently enabled I2C interrupt requests. - * - * @param base The I2C peripheral base address. - * @return A bitmask composed of #_i2c_interrupt_enable enumerators OR'd together to indicate the - * set of enabled interrupts. - */ -static inline uint32_t I2C_GetEnabledInterrupts(I2C_Type *base) -{ - return base->INTSTAT; -} - -/*@}*/ - -/*! @name Bus operations */ -/*@{*/ - -/*! - * @brief Sets the I2C bus frequency for master transactions. - * - * The I2C master is automatically disabled and re-enabled as necessary to configure the baud - * rate. Do not call this function during a transfer, or the transfer is aborted. - * - * @param base The I2C peripheral base address. - * @param srcClock_Hz I2C functional clock frequency in Hertz. - * @param baudRate_Bps Requested bus frequency in bits per second. - */ -void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Sets the I2C bus timeout value. - * - * If the SCL signal remains low or bus does not have event longer than the timeout value, kI2C_SclTimeoutFlag or - * kI2C_EventTimeoutFlag is set. This can indicete the bus is held by slave or any fault occurs to the I2C module. - * - * @param base The I2C peripheral base address. - * @param timeout_Ms Timeout value in millisecond. - * @param srcClock_Hz I2C functional clock frequency in Hertz. - */ -void I2C_MasterSetTimeoutValue(I2C_Type *base, uint8_t timeout_Ms, uint32_t srcClock_Hz); - -/*! - * @brief Returns whether the bus is idle. - * - * Requires the master mode to be enabled. - * - * @param base The I2C peripheral base address. - * @retval true Bus is busy. - * @retval false Bus is idle. - */ -static inline bool I2C_MasterGetBusIdleState(I2C_Type *base) -{ - /* True if MSTPENDING flag is set and MSTSTATE is zero == idle */ - return ((base->STAT & (I2C_STAT_MSTPENDING_MASK | I2C_STAT_MSTSTATE_MASK)) == I2C_STAT_MSTPENDING_MASK); -} - -/*! - * @brief Sends a START on the I2C bus. - * - * This function is used to initiate a new master mode transfer by sending the START signal. - * The slave address is sent following the I2C START signal. - * - * @param base I2C peripheral base pointer - * @param address 7-bit slave device address. - * @param direction Master transfer directions(transmit/receive). - * @retval kStatus_Success Successfully send the start signal. - * @retval kStatus_I2C_Busy Current bus is busy. - */ -status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); - -/*! - * @brief Sends a STOP signal on the I2C bus. - * - * @retval kStatus_Success Successfully send the stop signal. - * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. - */ -status_t I2C_MasterStop(I2C_Type *base); - -/*! - * @brief Sends a REPEATED START on the I2C bus. - * - * @param base I2C peripheral base pointer - * @param address 7-bit slave device address. - * @param direction Master transfer directions(transmit/receive). - * @retval kStatus_Success Successfully send the start signal. - * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. - */ -static inline status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) -{ - return I2C_MasterStart(base, address, direction); -} - -/*! - * @brief Performs a polling send transfer on the I2C bus. - * - * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may - * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this - * function returns #kStatus_I2C_Nak. - * - * @param base The I2C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * @retval kStatus_Success Data was sent successfully. - * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags); - -/*! - * @brief Performs a polling receive transfer on the I2C bus. - * - * @param base The I2C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * @retval kStatus_Success Data was received successfully. - * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags); - -/*! - * @brief Performs a master polling transfer on the I2C bus. - * - * @note The API does not return until the transfer succeeds or fails due - * to arbitration lost or receiving a NAK. - * - * @param base I2C peripheral base address. - * @param xfer Pointer to the transfer structure. - * @retval kStatus_Success Successfully complete the data transmission. - * @retval kStatus_I2C_Busy Previous transmission still not finished. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - * @retval kStataus_I2C_Addr_Nak Transfer error, receive NAK during addressing. - */ -status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); - -/*@}*/ - -/*! @name Non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the I2C master non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. - * - * @param base The I2C peripheral base address. - * @param[out] handle Pointer to the I2C master driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void I2C_MasterTransferCreateHandle(I2C_Type *base, - i2c_master_handle_t *handle, - i2c_master_transfer_callback_t callback, - void *userData); - -/*! - * @brief Performs a non-blocking transaction on the I2C bus. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @param xfer The pointer to the transfer descriptor. - * @retval kStatus_Success The transaction was started successfully. - * @retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking - * transaction is already in progress. - */ -status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Returns number of bytes transferred so far. - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @param[out] count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_Success - * @retval #kStatus_I2C_Busy - */ -status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); - -/*! - * @brief Terminates a non-blocking I2C master transmission early. - * - * @note It is not safe to call this function from an IRQ handler that has a higher priority than the - * I2C peripheral's IRQ priority. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @retval kStatus_Success A transaction was successfully aborted. - * @retval #kStatus_I2C_Timeout Timeout during polling for flags. - */ -status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); - -/*@}*/ - -/*! @name IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle master interrupts. - * @note This function does not need to be called unless you are reimplementing the - * nonblocking API's interrupt handler routines to add special functionality. - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - */ -void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle); - -/*@}*/ - -/*! @} */ /* end of i2c_master_driver */ - -/*! - * @addtogroup i2c_slave_driver - * @{ - */ - -/*! @name Slave initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the I2C slave peripheral. - * - * This function provides the following default configuration for the I2C slave peripheral: - * @code - * slaveConfig->enableSlave = true; - * slaveConfig->address0.disable = false; - * slaveConfig->address0.address = 0u; - * slaveConfig->address1.disable = true; - * slaveConfig->address2.disable = true; - * slaveConfig->address3.disable = true; - * slaveConfig->busSpeed = kI2C_SlaveStandardMode; - * @endcode - * - * After calling this function, override any settings to customize the configuration, - * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the @a - * address0.address member of the configuration structure with the desired slave address. - * - * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to - * #i2c_slave_config_t. - */ -void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); - -/*! - * @brief Initializes the I2C slave peripheral. - * - * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user - * provided configuration. - * - * @param base The I2C peripheral base address. - * @param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults - * that you can override. - * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide - * enough - * data setup time for master when slave stretches the clock. - */ -status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz); - -/*! - * @brief Configures Slave Address n register. - * - * This function writes new value to Slave Address register. - * - * @param base The I2C peripheral base address. - * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be - * changed. - * @param address The slave address to be stored to the address register for matching. - * @param addressDisable Disable matching of the specified address register. - */ -void I2C_SlaveSetAddress(I2C_Type *base, - i2c_slave_address_register_t addressRegister, - uint8_t address, - bool addressDisable); - -/*! - * @brief Deinitializes the I2C slave peripheral. - * - * This function disables the I2C slave peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -void I2C_SlaveDeinit(I2C_Type *base); - -/*! - * @brief Enables or disables the I2C module as slave. - * - * @param base The I2C peripheral base address. - * @param enable True to enable or flase to disable. - */ -static inline void I2C_SlaveEnable(I2C_Type *base, bool enable) -{ - /* Set or clear the SLVEN bit in the CFG register. */ - base->CFG = I2C_CFG_SLVEN(enable); -} - -/*@}*/ /* end of Slave initialization and deinitialization */ - -/*! @name Slave status */ -/*@{*/ - -/*! - * @brief Clears the I2C status flag state. - * - * The following status register flags can be cleared: - * - slave deselected flag - * - * Attempts to clear other flags has no effect. - * - * @param base The I2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * _i2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to - * I2C_SlaveGetStatusFlags(). - * @see _i2c_slave_flags. - */ -static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - /* Allow clearing just slave status flags */ - base->STAT = statusMask & I2C_STAT_SLVDESEL_MASK; -} - -/*@}*/ /* end of Slave status */ - -/*! @name Slave bus operations */ -/*@{*/ - -/*! - * @brief Performs a polling send transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * @param base The I2C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @return kStatus_Success Data has been sent. - * @return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). - */ -status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); - -/*! - * @brief Performs a polling receive transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * @param base The I2C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @return kStatus_Success Data has been received. - * @return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). - */ -status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); - -/*@}*/ /* end of Slave bus operations */ - -/*! @name Slave non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the I2C slave non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. - * - * @param base The I2C peripheral base address. - * @param[out] handle Pointer to the I2C slave driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void I2C_SlaveTransferCreateHandle(I2C_Type *base, - i2c_slave_handle_t *handle, - i2c_slave_transfer_callback_t callback, - void *userData); - -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. - * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); - -/*! - * @brief Starts accepting master read from slave requests. - * - * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param transfer Pointer to #i2c_slave_transfer_t structure. - * @param txData Pointer to data to send to master. - * @param txSize Size of txData in bytes. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetSendBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask); - -/*! - * @brief Starts accepting master write to slave requests. - * - * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param transfer Pointer to #i2c_slave_transfer_t structure. - * @param rxData Pointer to data to store data from master. - * @param rxSize Size of rxData in bytes. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetReceiveBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask); - -/*! - * @brief Returns the slave address sent by the I2C master. - * - * This function should only be called from the address match event callback #kI2C_SlaveAddressMatchEvent. - * - * @param base The I2C peripheral base address. - * @param transfer The I2C slave transfer. - * @return The 8-bit address matched by the I2C slave. Bit 0 contains the R/w direction bit, and - * the 7-bit slave address is in the upper 7 bits. - */ -static inline uint32_t I2C_SlaveGetReceivedAddress(I2C_Type *base, volatile i2c_slave_transfer_t *transfer) -{ - return transfer->receivedAddress; -} - -/*! - * @brief Aborts the slave non-blocking transfers. - * @note This API could be called at any time to stop slave for handling the bus events. - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * @retval kStatus_Success - * @retval #kStatus_I2C_Idle - */ -void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); - -/*! - * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_slave_handle_t structure. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_InvalidArgument count is Invalid. - * @retval kStatus_Success Successfully return the count. - */ -status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); - -/*@}*/ /* end of Slave non-blocking */ - -/*! @name Slave IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle slave interrupts. - * @note This function does not need to be called unless you are reimplementing the - * non blocking API's interrupt handler routines to add special functionality. - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - */ -void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle); - -/*@}*/ /* end of Slave IRQ handler */ - -/*! @} */ /* end of i2c_slave_driver */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2C_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c_dma.c deleted file mode 100644 index 45d47e59073..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c_dma.c +++ /dev/null @@ -1,652 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_i2c_dma.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c_dma" -#endif - -/*transfer = *xfer; - transfer = &(handle->transfer); - - handle->transferCount = 0U; - handle->remainingBytesDMA = 0U; - handle->buf = (uint8_t *)transfer->data; - handle->remainingSubaddr = 0U; - - if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) - { - handle->checkAddrNack = false; - /* Start condition shall not be ommited, switch directly to next phase */ - if (transfer->dataSize == 0U) - { - handle->state = (uint8_t)kStopState; - } - else if (handle->transfer.direction == kI2C_Write) - { - handle->state = (uint8_t)kTransmitDataState; - } - else if (handle->transfer.direction == kI2C_Read) - { - handle->state = (xfer->dataSize == 1U) ? (uint8_t)kReceiveLastDataState : (uint8_t)kReceiveDataState; - } - else - { - return kStatus_I2C_InvalidParameter; - } - } - else - { - if (transfer->subaddressSize != 0U) - { - int i; - uint32_t subaddress; - - if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) - { - return kStatus_I2C_InvalidParameter; - } - - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) - { - handle->subaddrBuf[i] = (uint8_t)subaddress & 0xffU; - subaddress >>= 8; - } - handle->remainingSubaddr = transfer->subaddressSize; - } - - handle->state = (uint8_t)kStartState; - handle->checkAddrNack = true; - } - - return kStatus_Success; -} - -static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - uint32_t transfer_size; - dma_transfer_config_t xferConfig; - uint32_t address; - address = (uint32_t)&base->MSTDAT; - - /* Update transfer count */ - int32_t count = handle->buf - (uint8_t *)handle->transfer.data; - assert(count >= 0); - handle->transferCount = (uint32_t)count; - - /* Check if there is anything to be transferred at all */ - if (handle->remainingBytesDMA == 0U) - { - /* No data to be transferrred, disable DMA */ - base->MSTCTL = 0; - return; - } - - /* Calculate transfer size */ - transfer_size = handle->remainingBytesDMA; - if (transfer_size > (uint32_t)I2C_MAX_DMA_TRANSFER_COUNT) - { - transfer_size = (uint32_t)I2C_MAX_DMA_TRANSFER_COUNT; - } - - switch (handle->transfer.direction) - { - case kI2C_Write: - DMA_PrepareTransfer(&xferConfig, handle->buf, (uint32_t *)address, sizeof(uint8_t), transfer_size, - kDMA_MemoryToPeripheral, NULL); - break; - - case kI2C_Read: - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, handle->buf, sizeof(uint8_t), transfer_size, - kDMA_PeripheralToMemory, NULL); - break; - - default: - /* This should never happen */ - assert(0); - break; - } - - (void)DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - DMA_StartTransfer(handle->dmaHandle); - - handle->remainingBytesDMA -= transfer_size; - handle->buf += transfer_size; - handle->checkAddrNack = false; -} - -static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone) -{ - uint32_t status; - uint32_t master_state; - struct _i2c_master_transfer *transfer; - dma_transfer_config_t xferConfig; - status_t err; - uint32_t start_flag = 0U; - uint32_t address; - address = (uint32_t)&base->MSTDAT; - - transfer = &(handle->transfer); - - *isDone = false; - - status = I2C_GetStatusFlags(base); - - if ((status & (uint32_t)I2C_STAT_MSTARBLOSS_MASK) != 0U) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_ArbitrationLost; - } - - if ((status & (uint32_t)I2C_STAT_MSTSTSTPERR_MASK) != 0U) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_StartStopError; - } - - /* Event timeout happens when the time since last bus event has been longer than the time specified by TIMEOUT - register. eg: Start signal fails to generate, no error status is set and transfer hangs if glitch on bus happens - before, the timeout status can be used to avoid the transfer hangs indefinitely. */ - if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) - { - I2C_ClearStatusFlags(base, (uint32_t)kI2C_EventTimeoutFlag); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_EventTimeout; - } - - /* SCL timeout happens when the slave is holding the SCL line low and the time has been longer than the time - specified by TIMEOUT register. */ - if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) - { - I2C_ClearStatusFlags(base, (uint32_t)kI2C_SclTimeoutFlag); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_SclLowTimeout; - } - - if ((status & (uint32_t)I2C_STAT_MSTPENDING_MASK) == 0U) - { - return kStatus_I2C_Busy; - } - - /* Get the state of the I2C module */ - master_state = (base->STAT & (uint32_t)I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (master_state == (uint32_t)I2C_STAT_MSTCODE_NACKDAT)) - { - /* Slave NACKed last byte, issue stop and return error */ - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = (uint8_t)kWaitForCompletionState; - if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (handle->checkAddrNack == true)) - { - return kStatus_I2C_Addr_Nak; - } - else - { - return kStatus_I2C_Nak; - } - } - - err = kStatus_Success; - - if (handle->state == (uint8_t)kStartState) - { - /* set start flag for later use */ - start_flag = I2C_MSTCTL_MSTSTART_MASK; - - if (handle->remainingSubaddr != 0U) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = (uint8_t)kTransmitSubaddrState; - } - else if (transfer->direction == kI2C_Write) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - if (transfer->dataSize == 0U) - { - /* No data to be transferred, initiate start and schedule stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - handle->state = (uint8_t)kStopState; - return err; - } - handle->state = (uint8_t)kTransmitDataState; - } - else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0U)) - { - base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; - if (transfer->dataSize == 1U) - { - /* The very last byte is always received by means of SW */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - handle->state = (uint8_t)kReceiveLastDataState; - return err; - } - handle->state = (uint8_t)kReceiveDataState; - } - else - { - handle->state = (uint8_t)kIdleState; - err = kStatus_I2C_UnexpectedState; - return err; - } - } - - switch (handle->state) - { - case (uint8_t)kTransmitSubaddrState: - if ((master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) && (0U == start_flag)) - { - return kStatus_I2C_UnexpectedState; - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - - /* Prepare and submit DMA transfer. */ - DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (uint32_t *)address, sizeof(uint8_t), - handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL); - (void)DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - DMA_StartTransfer(handle->dmaHandle); - handle->remainingSubaddr = 0; - if (transfer->dataSize != 0U) - { - /* There is data to be transferred, if there is write to read turnaround it is necessary to perform - * repeated start */ - handle->state = (transfer->direction == kI2C_Read) ? (uint8_t)kStartState : (uint8_t)kTransmitDataState; - } - else - { - /* No more data, schedule stop condition */ - handle->state = (uint8_t)kStopState; - } - break; - - case (uint8_t)kTransmitDataState: - if ((master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) && (0U == start_flag)) - { - return kStatus_I2C_UnexpectedState; - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - handle->remainingBytesDMA = handle->transfer.dataSize; - - I2C_RunDMATransfer(base, handle); - - /* Schedule stop condition */ - handle->state = (uint8_t)kStopState; - handle->checkAddrNack = false; - break; - - case (uint8_t)kReceiveDataState: - if ((master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) && (0U == start_flag)) - { - if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStartFlag)) - { - return kStatus_I2C_UnexpectedState; - } - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - handle->remainingBytesDMA = handle->transfer.dataSize - 1U; - - if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) - { - /* Read the master data register to avoid the data be read again */ - (void)base->MSTDAT; - } - I2C_RunDMATransfer(base, handle); - - /* Schedule reception of last data byte */ - handle->state = (uint8_t)kReceiveLastDataState; - handle->checkAddrNack = false; - break; - - case (uint8_t)kReceiveLastDataState: - if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) - { - return kStatus_I2C_UnexpectedState; - } - - ((uint8_t *)transfer->data)[transfer->dataSize - 1U] = (uint8_t)base->MSTDAT; - handle->transferCount++; - - /* No more data expected, issue NACK and STOP right away */ - if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStopFlag)) - { - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - } - handle->state = (uint8_t)kWaitForCompletionState; - break; - - case (uint8_t)kStopState: - if ((transfer->flags & (uint32_t)kI2C_TransferNoStopFlag) != 0U) - { - /* Stop condition is omitted, we are done */ - *isDone = true; - handle->state = (uint8_t)kIdleState; - break; - } - /* Send stop condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = (uint8_t)kWaitForCompletionState; - break; - - case (uint8_t)kWaitForCompletionState: - *isDone = true; - handle->state = (uint8_t)kIdleState; - break; - - case (uint8_t)kStartState: - case (uint8_t)kIdleState: - default: - /* State machine shall not be invoked again once it enters the idle state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - return err; -} - -static void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - bool isDone; - status_t result; - - /* Don't do anything if we don't have a valid handle. */ - if (NULL == handle) - { - return; - } - - result = I2C_RunTransferStateMachineDMA(base, handle, &isDone); - - if ((result != kStatus_Success) || isDone) - { - /* Restore handle to idle state. */ - handle->state = (uint8_t)kIdleState; - - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | - I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); - - /* Invoke callback. */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } -} - -static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) -{ - i2c_master_dma_private_handle_t *dmaPrivateHandle; - - /* Don't do anything if we don't have a valid handle. */ - if (NULL == handle) - { - return; - } - - dmaPrivateHandle = (i2c_master_dma_private_handle_t *)userData; - I2C_RunDMATransfer(dmaPrivateHandle->base, dmaPrivateHandle->handle); -} - -/*! - * brief Init the I2C handle which is used in transactional functions - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - * param callback pointer to user callback function - * param userData user param passed to the callback function - * param dmaHandle DMA handle pointer - */ -void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, - i2c_master_dma_handle_t *handle, - i2c_master_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *dmaHandle) -{ - assert(handle != NULL); - assert(dmaHandle != NULL); - - uint32_t instance; - i2c_dma_to_flexcomm_t handler; - handler.i2c_dma_master_handler = I2C_MasterTransferDMAHandleIRQ; - - /* Zero handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Set the user callback and userData. */ - handle->completionCallback = callback; - handle->userData = userData; - - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | - I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); - (void)EnableIRQ(s_i2cIRQ[instance]); - - /* Set the handle for DMA. */ - handle->dmaHandle = dmaHandle; - - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - DMA_SetCallback(dmaHandle, I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]); -} - -/*! - * brief Performs a master dma non-blocking transfer on the I2C bus - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - * param xfer pointer to transfer structure of i2c_master_transfer_t - * retval kStatus_Success Sucessully complete the data transmission. - * retval kStatus_I2C_Busy Previous transmission still not finished. - * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. - */ -status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer) -{ - status_t result; - - assert(handle != NULL); - assert(xfer != NULL); - assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); - - /* Return busy if another transaction is in progress. */ - if (handle->state != (uint8_t)kIdleState) - { - return kStatus_I2C_Busy; - } - - /* Prepare transfer state machine. */ - result = I2C_InitTransferStateMachineDMA(base, handle, xfer); - - /* Clear error flags. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Enable I2C internal IRQ sources */ - /* Enable arbitration lost interrupt, start/stop error interrupt and master pending interrupt. - The master pending flag is not set during dma transfer. */ - I2C_EnableInterrupts(base, I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | - I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); - - return result; -} - -/*! - * brief Get master transfer status during a dma non-blocking transfer - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - * param count Number of bytes transferred so far by the non-blocking transaction. - */ -status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state == (uint8_t)kIdleState) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* There is no necessity to disable interrupts as we read a single integer value */ - *count = handle->transferCount; - return kStatus_Success; -} - -/*! - * brief Abort a master dma non-blocking transfer in a early time - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - */ -void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - uint32_t status; - uint32_t master_state; - - if (handle->state != (uint8_t)kIdleState) - { - DMA_AbortTransfer(handle->dmaHandle); - - /* Disable DMA */ - base->MSTCTL = 0; - - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | - I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); - - /* Wait until module is ready */ - do - { - status = I2C_GetStatusFlags(base); - } while ((status & (uint8_t)I2C_STAT_MSTPENDING_MASK) == 0U); - - /* Clear controller state. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Get the state of the I2C module */ - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if (master_state != (uint32_t)I2C_STAT_MSTCODE_IDLE) - { - /* Send a stop command to finalize the transfer. */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - - /* Wait until module is ready */ - do - { - status = I2C_GetStatusFlags(base); - } while ((status & (uint32_t)I2C_STAT_MSTPENDING_MASK) == 0U); - - /* Clear controller state. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - } - - /* Reset the state to idle. */ - handle->state = (uint8_t)kIdleState; - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c_dma.h deleted file mode 100644 index 07899f9c7c9..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c_dma.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2C_DMA_H_ -#define _FSL_I2C_DMA_H_ - -#include "fsl_i2c.h" -#include "fsl_dma.h" - -/*! - * @addtogroup i2c_dma_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2C DMA driver version. */ -#define FSL_I2C_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) -/*@}*/ - -/*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */ -#define I2C_MAX_DMA_TRANSFER_COUNT 1024 - -/*! @brief I2C master dma handle typedef. */ -typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t; - -/*! @brief I2C master dma transfer callback typedef. */ -typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base, - i2c_master_dma_handle_t *handle, - status_t status, - void *userData); - -/*! @brief Typedef for master dma handler. */ -typedef void (*flexcomm_i2c_dma_master_irq_handler_t)(I2C_Type *base, i2c_master_dma_handle_t *handle); - -/*! @brief I2C master dma transfer structure. */ -struct _i2c_master_dma_handle -{ - uint8_t state; /*!< Transfer state machine current state. */ - uint32_t transferCount; /*!< Indicates progress of the transfer */ - uint32_t remainingBytesDMA; /*!< Remaining byte count to be transferred using DMA. */ - uint8_t *buf; /*!< Buffer pointer for current state. */ - uint32_t remainingSubaddr; - uint8_t subaddrBuf[4]; - bool checkAddrNack; /*!< Whether to check the nack signal is detected during addressing. */ - dma_handle_t *dmaHandle; /*!< The DMA handler used. */ - i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ - i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */ - void *userData; /*!< Callback parameter passed to callback function. */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus. */ - -/*! - * @name I2C Block DMA Transfer Operation - * @{ - */ - -/*! - * @brief Init the I2C handle which is used in transactional functions - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param callback pointer to user callback function - * @param userData user param passed to the callback function - * @param dmaHandle DMA handle pointer - */ -void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, - i2c_master_dma_handle_t *handle, - i2c_master_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *dmaHandle); - -/*! - * @brief Performs a master dma non-blocking transfer on the I2C bus - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param xfer pointer to transfer structure of i2c_master_transfer_t - * @retval kStatus_Success Sucessully complete the data transmission. - * @retval kStatus_I2C_Busy Previous transmission still not finished. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. - */ -status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Get master transfer status during a dma non-blocking transfer - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param count Number of bytes transferred so far by the non-blocking transaction. - */ -status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count); - -/*! - * @brief Abort a master dma non-blocking transfer in a early time - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - */ -void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle); - -/* @} */ -#if defined(__cplusplus) -} -#endif /*_cplusplus. */ -/*@}*/ -#endif /*_FSL_I2C_DMA_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s.c deleted file mode 100644 index 28a36b3ce6f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s.c +++ /dev/null @@ -1,1163 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_i2s.h" -#include "fsl_flexcomm.h" -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s" -#endif - -/* TODO - absent in device header files, should be there */ -#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) -#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) -#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) -#define I2S_FIFOCFG_PACK48_MASK (0x8U) -#define I2S_FIFOCFG_PACK48_SHIFT (3U) -#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) - -/*! @brief _i2s_state I2S states. */ -enum -{ - kI2S_StateIdle = 0x0, /*!< Not performing transfer */ - kI2S_StateTx, /*!< Performing transmit */ - kI2S_StateTxWaitToWriteDummyData, /*!< Wait on FIFO in order to write final dummy data there */ - kI2S_StateTxWaitForEmptyFifo, /*!< Wait for FIFO to be flushed */ - kI2S_StateRx, /*!< Performing receive */ -}; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -static void I2S_Config(I2S_Type *base, const i2s_config_t *config); -static void I2S_TxEnable(I2S_Type *base, bool enable); -static void I2S_RxEnable(I2S_Type *base, bool enable); -static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map i2c instance number to base address. */ -static const uint32_t s_i2sBaseAddrs[] = I2S_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_i2sIRQ[] = I2S_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! - * @brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * @param base The I2S peripheral base address. - * @return I2S instance number starting from 0. - */ -static uint32_t I2S_GetInstance(I2S_Type *base) -{ - uint32_t i; - for (i = 0; i < (uint32_t)ARRAY_SIZE(s_i2sBaseAddrs); i++) - { - if ((uint32_t)base == s_i2sBaseAddrs[i]) - { - return i; - } - } - assert(false); - return 0; -} - -/*! - * brief Transmitter bit clock rate configurations. - * - * param base SAI base pointer. - * param sourceClockHz, bit clock source frequency. - * param sampleRate audio data sample rate. - * param bitWidth, audio data bitWidth. - * param channelNumbers, audio channel numbers. - */ -void I2S_SetBitClockRate( - I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers) -{ - uint32_t bitClockDivider = sourceClockHz / sampleRate / bitWidth / channelNumbers; - - assert(bitClockDivider >= 1U); - base->DIV = I2S_DIV_DIV(bitClockDivider - 1U); -} - -/*! - * brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S transmission using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_TxGetDefaultConfig(). - * - * note This API should be called at the beginning of the application to use - * the I2S driver. - * - * param base I2S base pointer. - * param config pointer to I2S configuration structure. - */ -void I2S_TxInit(I2S_Type *base, const i2s_config_t *config) -{ - uint32_t cfg = 0U; - uint32_t trig = 0U; - - (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_TX); - I2S_Config(base, config); - - /* Configure FIFO */ - - cfg |= I2S_FIFOCFG_ENABLETX(1U); /* enable TX FIFO */ - cfg |= I2S_FIFOCFG_EMPTYTX(1U); /* empty TX FIFO */ - cfg |= I2S_FIFOCFG_TXI2SE0(config->txEmptyZero); /* transmit zero when buffer becomes empty or last item */ - cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ - trig |= I2S_FIFOTRIG_TXLVLENA(1U); /* enable TX FIFO trigger */ - trig |= I2S_FIFOTRIG_TXLVL(config->watermark); /* set TX FIFO trigger level */ - - base->FIFOCFG = cfg; - base->FIFOTRIG = trig; -} - -/*! - * brief Initializes the FLEXCOMM peripheral for I2S receive functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S receive using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_RxGetDefaultConfig(). - * - * note This API should be called at the beginning of the application to use - * the I2S driver. - * - * param base I2S base pointer. - * param config pointer to I2S configuration structure. - */ -void I2S_RxInit(I2S_Type *base, const i2s_config_t *config) -{ - uint32_t cfg = 0U; - uint32_t trig = 0U; - - (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_RX); - I2S_Config(base, config); - - /* Configure FIFO */ - - cfg |= I2S_FIFOCFG_ENABLERX(1U); /* enable RX FIFO */ - cfg |= I2S_FIFOCFG_EMPTYRX(1U); /* empty RX FIFO */ - cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ - trig |= I2S_FIFOTRIG_RXLVLENA(1U); /* enable RX FIFO trigger */ - trig |= I2S_FIFOTRIG_RXLVL(config->watermark); /* set RX FIFO trigger level */ - - base->FIFOCFG = cfg; - base->FIFOTRIG = trig; -} - -/*! - * brief Sets the I2S Tx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_TxInit(). - * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified - * before calling I2S_TxInit(). - * Example: - code - i2s_config_t config; - I2S_TxGetDefaultConfig(&config); - endcode - * - * Default values: - * code - * config->masterSlave = kI2S_MasterSlaveNormalMaster; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = true; - * config->pack48 = false; - * endcode - * - * param config pointer to I2S configuration structure. - */ -void I2S_TxGetDefaultConfig(i2s_config_t *config) -{ - config->masterSlave = kI2S_MasterSlaveNormalMaster; - config->mode = kI2S_ModeI2sClassic; - config->rightLow = false; - config->leftJust = false; -#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) - config->pdmData = false; -#endif - config->sckPol = false; - config->wsPol = false; - config->divider = 1U; - config->oneChannel = false; - config->dataLength = 16U; - config->frameLength = 32U; - config->position = 0U; - config->watermark = 4U; - config->txEmptyZero = true; - config->pack48 = false; -} - -/*! - * brief Sets the I2S Rx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_RxInit(). - * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified - * before calling I2S_RxInit(). - * Example: - code - i2s_config_t config; - I2S_RxGetDefaultConfig(&config); - endcode - * - * Default values: - * code - * config->masterSlave = kI2S_MasterSlaveNormalSlave; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = false; - * config->pack48 = false; - * endcode - * - * param config pointer to I2S configuration structure. - */ -void I2S_RxGetDefaultConfig(i2s_config_t *config) -{ - config->masterSlave = kI2S_MasterSlaveNormalSlave; - config->mode = kI2S_ModeI2sClassic; - config->rightLow = false; - config->leftJust = false; -#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) - config->pdmData = false; -#endif - config->sckPol = false; - config->wsPol = false; - config->divider = 1U; - config->oneChannel = false; - config->dataLength = 16U; - config->frameLength = 32U; - config->position = 0U; - config->watermark = 4U; - config->txEmptyZero = false; - config->pack48 = false; -} - -static void I2S_Config(I2S_Type *base, const i2s_config_t *config) -{ - assert(config != NULL); - - uint32_t cfg1 = 0U; - uint32_t cfg2 = 0U; - - /* set master/slave configuration */ - cfg1 |= I2S_CFG1_MSTSLVCFG(config->masterSlave); - - /* set I2S mode */ - cfg1 |= I2S_CFG1_MODE(config->mode); - - /* set right low (channel swap) */ - cfg1 |= I2S_CFG1_RIGHTLOW(config->rightLow); - - /* set data justification */ - cfg1 |= I2S_CFG1_LEFTJUST(config->leftJust); - -#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) - if (FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn((FLEXCOMM_Type *)(uint32_t)base) > 0) - { - /* set source to PDM dmic */ - cfg1 |= I2S_CFG1_PDMDATA(config->pdmData); - } -#endif - - /* set SCLK polarity */ - cfg1 |= I2S_CFG1_SCK_POL(config->sckPol); - - /* set WS polarity */ - cfg1 |= I2S_CFG1_WS_POL(config->wsPol); - - /* set mono mode */ - cfg1 |= I2S_CFG1_ONECHANNEL(config->oneChannel); - - /* set data length */ - cfg1 |= I2S_CFG1_DATALEN(config->dataLength - 1UL); - - /* set frame length */ - cfg2 |= I2S_CFG2_FRAMELEN(config->frameLength - 1UL); - - /* set data position of this channel pair within the frame */ - cfg2 |= I2S_CFG2_POSITION(config->position); - - /* write to registers */ - base->CFG1 = cfg1; - base->CFG2 = cfg2; - - /* set the clock divider */ - base->DIV = I2S_DIV_DIV(config->divider - 1UL); -} - -/*! - * brief De-initializes the I2S peripheral. - * - * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit - * or I2S_RxInit is called to enable the clock. - * - * param base I2S base pointer. - */ -void I2S_Deinit(I2S_Type *base) -{ - /* TODO gate FLEXCOMM clock via FLEXCOMM driver */ -} - -static void I2S_TxEnable(I2S_Type *base, bool enable) -{ - if (enable) - { - I2S_Enable(base); - I2S_EnableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); - } - else - { - I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); - I2S_Disable(base); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - } -} - -static void I2S_RxEnable(I2S_Type *base, bool enable) -{ - if (enable) - { - I2S_Enable(base); - I2S_EnableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); - } - else - { - I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); - I2S_Disable(base); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - } -} - -static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer) -{ - assert(transfer->data != NULL); - - if (transfer->data == NULL) - { - return kStatus_InvalidArgument; - } - - assert(transfer->dataSize > 0U); - if (transfer->dataSize <= 0U) - { - return kStatus_InvalidArgument; - } - - if (handle->dataLength == 4U) - { - /* No alignment and data length requirements */ - } - else if ((handle->dataLength >= 5U) && (handle->dataLength <= 8U)) - { - assert((((uint32_t)transfer->data) % 2U) == 0U); - if ((((uint32_t)transfer->data) % 2U) != 0U) - { - /* Data not 2-bytes aligned */ - return kStatus_InvalidArgument; - } - - assert((transfer->dataSize % 2U) == 0U); - if ((transfer->dataSize % 2U) != 0U) - { - /* Data not in pairs of left/right channel bytes */ - return kStatus_InvalidArgument; - } - } - else if ((handle->dataLength >= 9U) && (handle->dataLength <= 16U)) - { - assert((((uint32_t)transfer->data) % 4U) == 0U); - if ((((uint32_t)transfer->data) % 4U) != 0U) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - - assert((transfer->dataSize % 4U) == 0U); - if ((transfer->dataSize % 4U) != 0U) - { - /* Data lenght not multiply of 4 */ - return kStatus_InvalidArgument; - } - } - else if ((handle->dataLength >= 17U) && (handle->dataLength <= 24U)) - { - assert((transfer->dataSize % 6U) == 0U); - if ((transfer->dataSize % 6U) != 0U) - { - /* Data lenght not multiply of 6 */ - return kStatus_InvalidArgument; - } - - assert(!((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U))); - if ((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U)) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - } - else /* if (handle->dataLength >= 25U) */ - { - assert((((uint32_t)transfer->data) % 4U) == 0U); - if ((((uint32_t)transfer->data) % 4U) != 0U) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - - if (handle->oneChannel) - { - assert((transfer->dataSize % 4U) == 0U); - if ((transfer->dataSize % 4U) != 0U) - { - /* Data lenght not multiply of 4 */ - return kStatus_InvalidArgument; - } - } - else - { - assert((transfer->dataSize % 8U) == 0U); - if ((transfer->dataSize % 8U) != 0U) - { - /* Data lenght not multiply of 8 */ - return kStatus_InvalidArgument; - } - } - } - - return kStatus_Success; -} - -#if (defined(FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) && FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) -/*! - * brief Enables I2S secondary channel. - * - * param base I2S base pointer. - * param channel seondary channel channel number, reference _i2s_secondary_channel. - * param oneChannel true is treated as single channel, functionality left channel for this pair. - * param position define the location within the frame of the data, should not bigger than 0x1FFU. - */ -void I2S_EnableSecondaryChannel(I2S_Type *base, uint32_t channel, bool oneChannel, uint32_t position) -{ - assert(channel <= (uint32_t)kI2S_SecondaryChannel3); -#if defined FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn - assert(FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn((FLEXCOMM_Type *)(uint32_t)base) == 1); -#endif - - uint32_t pcfg1 = base->SECCHANNEL[channel].PCFG1; - uint32_t pcfg2 = base->SECCHANNEL[channel].PCFG2; - - pcfg1 &= ~I2S_CFG1_ONECHANNEL_MASK; - pcfg1 |= I2S_CFG1_MAINENABLE_MASK | I2S_CFG1_ONECHANNEL(oneChannel); - - pcfg2 &= ~I2S_CFG2_POSITION_MASK; - pcfg2 |= I2S_CFG2_POSITION(position); - - base->SECCHANNEL[channel].PCFG1 = pcfg1; - base->SECCHANNEL[channel].PCFG2 = pcfg2; -} -#endif - -/*! - * brief Initializes handle for transfer of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) -{ - assert(handle != NULL); - - uint32_t instance; - - /* Clear out the handle */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2S_GetInstance(base); - - /* Save callback and user data */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Remember some items set previously by configuration */ - handle->watermark = (uint8_t)((base->FIFOTRIG & I2S_FIFOTRIG_TXLVL_MASK) >> I2S_FIFOTRIG_TXLVL_SHIFT); - handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT) != 0U ? true : false; - handle->dataLength = (uint8_t)((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; - handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT) != 0u ? true : false; - - handle->useFifo48H = false; - - /* Register IRQ handling */ - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_TxHandleIRQ, handle); - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); - (void)EnableIRQ(s_i2sIRQ[instance]); -} - -/*! - * brief Begins or queue sending of the given data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) -{ - assert(handle != NULL); - - status_t result; - - if (handle == NULL) - { - return kStatus_InvalidArgument; - } - - result = I2S_ValidateBuffer(handle, &transfer); - if (result != kStatus_Success) - { - return result; - } - - if (handle->i2sQueue[handle->queueUser].dataSize != 0UL) - { - /* Previously prepared buffers not processed yet */ - return kStatus_I2S_Busy; - } - - handle->state = (uint32_t)kI2S_StateTx; - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_TXLVL_MASK)) | I2S_FIFOTRIG_TXLVL(handle->watermark); - I2S_TxEnable(base, true); - - return kStatus_Success; -} - -/*! - * brief Aborts sending of data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle) -{ - assert(handle != NULL); - - /* Disable I2S operation and interrupts */ - I2S_TxEnable(base, false); - - /* Reset state */ - handle->state = (uint32_t)kI2S_StateIdle; - - /* Clear transfer queue */ - (void)memset((void *)&handle->i2sQueue, 0, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); - handle->queueDriver = 0U; - handle->queueUser = 0U; -} - -/*! - * brief Initializes handle for reception of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) -{ - assert(handle != NULL); - - uint32_t instance; - - /* Clear out the handle */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2S_GetInstance(base); - - /* Save callback and user data */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Remember some items set previously by configuration */ - handle->watermark = (uint8_t)((base->FIFOTRIG & I2S_FIFOTRIG_RXLVL_MASK) >> I2S_FIFOTRIG_RXLVL_SHIFT); - handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT) != 0UL ? true : false; - handle->dataLength = (uint8_t)((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; - handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT) != 0UL ? true : false; - - handle->useFifo48H = false; - - /* Register IRQ handling */ - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_RxHandleIRQ, handle); - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); - - (void)EnableIRQ(s_i2sIRQ[instance]); -} - -/*! - * brief Begins or queue reception of data into given buffer. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. - */ -status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) -{ - assert(handle != NULL); - - status_t result; - - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - result = I2S_ValidateBuffer(handle, &transfer); - if (result != kStatus_Success) - { - return result; - } - - if (handle->i2sQueue[handle->queueUser].dataSize != 0UL) - { - /* Previously prepared buffers not processed yet */ - return kStatus_I2S_Busy; - } - - handle->state = (uint32_t)kI2S_StateRx; - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_RXLVL_MASK)) | I2S_FIFOTRIG_RXLVL(handle->watermark); - I2S_RxEnable(base, true); - - return kStatus_Success; -} - -/*! - * brief Aborts receiving of data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle) -{ - assert(handle != NULL); - - /* Disable I2S operation and interrupts */ - I2S_RxEnable(base, false); - - /* Reset state */ - handle->state = (uint32_t)kI2S_StateIdle; - - /* Clear transfer queue */ - (void)memset((void *)&handle->i2sQueue, 0, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); - handle->queueDriver = 0U; - handle->queueUser = 0U; -} - -/*! - * brief Returns number of bytes transferred so far. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param[out] count number of bytes transferred so far by the non-blocking transaction. - * - * retval kStatus_Success - * retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - assert(count != NULL); - - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - if (handle->state == (uint32_t)kI2S_StateIdle) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->transferCount; - - return kStatus_Success; -} - -/*! - * brief Returns number of buffer underruns or overruns. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param[out] count number of transmit errors encountered so far by the non-blocking transaction. - * - * retval kStatus_Success - * retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - assert(count != NULL); - - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - if (handle->state == (uint32_t)kI2S_StateIdle) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->errorCount; - - return kStatus_Success; -} - -/*! - * brief Invoked from interrupt handler when transmit FIFO level decreases. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) -{ - uint32_t intstat = base->FIFOINTSTAT; - uint32_t data; - uint8_t queueDriverIndex = handle->queueDriver; - uint32_t dataAddr = (uint32_t)handle->i2sQueue[queueDriverIndex].data; - uint32_t dataSize = handle->i2sQueue[queueDriverIndex].dataSize; - - if ((intstat & I2S_FIFOINTSTAT_TXERR_MASK) != 0UL) - { - handle->errorCount++; - - /* Clear TX error interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_TXERR(1U); - } - - if ((intstat & I2S_FIFOINTSTAT_TXLVL_MASK) != 0UL) - { - if (handle->state == (uint32_t)kI2S_StateTx) - { - /* Send data */ - - while (((base->FIFOSTAT & I2S_FIFOSTAT_TXNOTFULL_MASK) != 0UL) && (dataSize > 0U)) - { - /* Write output data */ - if (handle->dataLength == 4U) - { - data = *((uint8_t *)dataAddr); - base->FIFOWR = ((data & 0xF0U) << 12U) | (data & 0xFU); - dataAddr++; - handle->transferCount++; - dataSize--; - } - else if (handle->dataLength <= 8U) - { - data = *((volatile uint16_t *)dataAddr); - if (handle->oneChannel) - { - base->FIFOWR = (data & 0xFFU); - dataAddr += sizeof(uint8_t); - handle->transferCount += sizeof(uint8_t); - dataSize -= sizeof(uint8_t); - } - else - { - base->FIFOWR = ((data & 0xFF00U) << 8U) | (data & 0xFFU); - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - } - else if (handle->dataLength <= 16U) - { - data = *((volatile uint32_t *)(dataAddr)); - if (handle->oneChannel) - { - base->FIFOWR = data & 0xFFFFU; - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - else - { - base->FIFOWR = data; - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - } - else if (handle->dataLength <= 24U) - { - if (handle->pack48) - { - if (handle->useFifo48H) - { - base->FIFOWR48H = *((volatile uint16_t *)(dataAddr)); - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - handle->useFifo48H = false; - } - else - { - base->FIFOWR = *((volatile uint32_t *)(dataAddr)); - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - handle->useFifo48H = true; - } - } - else - { - data = (uint32_t)(*(uint8_t *)(dataAddr++)); - data |= ((uint32_t)(*(uint8_t *)(dataAddr++))) << 8U; - data |= ((uint32_t)(*(uint8_t *)(dataAddr++))) << 16U; - if ((handle->useFifo48H) && (handle->oneChannel == false)) - { - base->FIFOWR48H = data; - handle->useFifo48H = false; - } - else - { - base->FIFOWR = data; - handle->useFifo48H = true; - } - handle->transferCount += 3U; - dataSize -= 3U; - } - } - else /* if (handle->dataLength <= 32U) */ - { - base->FIFOWR = *((volatile uint32_t *)(dataAddr)); - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - - if (dataSize == 0U) - { - handle->i2sQueue[queueDriverIndex].dataSize = 0U; - /* Actual data buffer sent out, switch to a next one */ - handle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; - - /* Notify user */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); - } - - /* Check if the next buffer contains anything to send */ - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* Everything has been written to FIFO */ - handle->state = kI2S_StateTxWaitToWriteDummyData; - break; - } - } - else - { - handle->i2sQueue[queueDriverIndex].dataSize = dataSize; - handle->i2sQueue[queueDriverIndex].data = (uint8_t *)dataAddr; - } - } - } - else if (handle->state == (uint32_t)kI2S_StateTxWaitToWriteDummyData) - { - /* Write dummy data */ - if ((handle->dataLength > 16U) && (handle->dataLength < 25U)) - { - if (handle->useFifo48H) - { - base->FIFOWR48H = 0U; - handle->useFifo48H = false; - } - else - { - base->FIFOWR = 0U; - base->FIFOWR48H = 0U; - } - } - else - { - base->FIFOWR = 0U; - } - - /* Next time invoke this handler when FIFO becomes empty (TX level 0) */ - base->FIFOTRIG &= ~I2S_FIFOTRIG_TXLVL_MASK; - handle->state = (uint32_t)kI2S_StateTxWaitForEmptyFifo; - } - else if (handle->state == (uint32_t)kI2S_StateTxWaitForEmptyFifo) - { - /* FIFO, including additional dummy data, has been emptied now, - * all relevant data should have been output from peripheral */ - - /* Stop transfer */ - I2S_Disable(base); - I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - - /* Reset state */ - handle->state = (uint32_t)kI2S_StateIdle; - - /* Notify user */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); - } - } - else - { - /* Do nothing */ - } - - /* Clear TX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_TXLVL(1U); - } -} - -/*! - * brief Invoked from interrupt handler when receive FIFO level decreases. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) -{ - uint32_t intstat = base->FIFOINTSTAT; - uint32_t data; - uint8_t queueDriverIndex = handle->queueDriver; - uint32_t dataAddr = (uint32_t)handle->i2sQueue[queueDriverIndex].data; - uint32_t dataSize = handle->i2sQueue[queueDriverIndex].dataSize; - - if ((intstat & I2S_FIFOINTSTAT_RXERR_MASK) != 0UL) - { - handle->errorCount++; - - /* Clear RX error interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXERR(1U); - } - - if ((intstat & I2S_FIFOINTSTAT_RXLVL_MASK) != 0UL) - { - while (((base->FIFOSTAT & I2S_FIFOSTAT_RXNOTEMPTY_MASK) != 0UL) && (dataSize > 0U)) - { - /* Read input data */ - if (handle->dataLength == 4U) - { - data = base->FIFORD; - *((uint8_t *)dataAddr) = (uint8_t)(((data & 0x000F0000U) >> 12U) | (data & 0x0000000FU)); - dataAddr++; - handle->transferCount++; - dataSize--; - } - else if (handle->dataLength <= 8U) - { - data = base->FIFORD; - - if (handle->oneChannel) - { - *((volatile uint8_t *)dataAddr) = (uint8_t)(data & 0xFFU); - dataAddr += sizeof(uint8_t); - handle->transferCount += sizeof(uint8_t); - dataSize -= sizeof(uint8_t); - } - else - { - *((volatile uint16_t *)dataAddr) = (uint16_t)(((data >> 8U) & 0xFF00U) | (data & 0xFFU)); - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - } - else if (handle->dataLength <= 16U) - { - data = base->FIFORD; - - if (handle->oneChannel) - { - *((volatile uint16_t *)dataAddr) = (uint16_t)(data & 0xFFFFU); - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - else - { - *((volatile uint32_t *)dataAddr) = data; - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - } - else if (handle->dataLength <= 24U) - { - if (handle->pack48) - { - if (handle->useFifo48H) - { - data = base->FIFORD48H; - handle->useFifo48H = false; - - *((volatile uint16_t *)dataAddr) = (uint16_t)data; - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - else - { - data = base->FIFORD; - handle->useFifo48H = true; - - *((volatile uint32_t *)dataAddr) = data; - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - } - else - { - if (handle->useFifo48H) - { - data = base->FIFORD48H; - handle->useFifo48H = false; - } - else - { - data = base->FIFORD; - handle->useFifo48H = true; - } - - *(uint8_t *)(dataAddr++) = (uint8_t)(data & 0xFFU); - *(uint8_t *)(dataAddr++) = (uint8_t)((data >> 8U) & 0xFFU); - *(uint8_t *)(dataAddr++) = (uint8_t)((data >> 16U) & 0xFFU); - handle->transferCount += 3U; - dataSize -= 3U; - } - } - else /* if (handle->dataLength <= 32U) */ - { - data = base->FIFORD; - *((volatile uint32_t *)dataAddr) = data; - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - - if (dataSize == 0U) - { - handle->i2sQueue[queueDriverIndex].dataSize = 0U; - /* Actual data buffer filled with input data, switch to a next one */ - handle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; - - /* Notify user */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); - } - - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* No other buffer prepared to receive data into */ - - /* Disable I2S operation and interrupts */ - I2S_Disable(base); - I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - - /* Reset state */ - handle->state = (uint32_t)kI2S_StateIdle; - - /* Notify user */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); - } - - /* Clear RX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); - - return; - } - } - else - { - handle->i2sQueue[queueDriverIndex].dataSize = dataSize; - handle->i2sQueue[queueDriverIndex].data = (uint8_t *)dataAddr; - } - } - - /* Clear RX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s.h deleted file mode 100644 index dd93f9d08ab..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s.h +++ /dev/null @@ -1,505 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2S_H_ -#define _FSL_I2S_H_ - -#include "fsl_device_registers.h" -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup i2s_driver - * @{ - */ - -/*! @file */ - -/*! @name Driver version */ -/*@{*/ - -/*! @brief I2S driver version 2.2.2. */ -#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) -/*@}*/ - -#ifndef I2S_NUM_BUFFERS - -/*! @brief Number of buffers . */ -#define I2S_NUM_BUFFERS (4U) - -#endif - -/*! @brief _i2s_status I2S status codes. */ -enum -{ - kStatus_I2S_BufferComplete = - MAKE_STATUS(kStatusGroup_I2S, 0), /*!< Transfer from/into a single buffer has completed */ - kStatus_I2S_Done = MAKE_STATUS(kStatusGroup_I2S, 1), /*!< All buffers transfers have completed */ - kStatus_I2S_Busy = - MAKE_STATUS(kStatusGroup_I2S, 2), /*!< Already performing a transfer and cannot queue another buffer */ -}; - -/*! - * @brief I2S flags. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -typedef enum _i2s_flags -{ - kI2S_TxErrorFlag = I2S_FIFOINTENSET_TXERR_MASK, /*!< TX error interrupt */ - kI2S_TxLevelFlag = I2S_FIFOINTENSET_TXLVL_MASK, /*!< TX level interrupt */ - kI2S_RxErrorFlag = I2S_FIFOINTENSET_RXERR_MASK, /*!< RX error interrupt */ - kI2S_RxLevelFlag = I2S_FIFOINTENSET_RXLVL_MASK /*!< RX level interrupt */ -} i2s_flags_t; - -/*! @brief Master / slave mode. */ -typedef enum _i2s_master_slave -{ - kI2S_MasterSlaveNormalSlave = 0x0, /*!< Normal slave */ - kI2S_MasterSlaveWsSyncMaster = 0x1, /*!< WS synchronized master */ - kI2S_MasterSlaveExtSckMaster = 0x2, /*!< Master using existing SCK */ - kI2S_MasterSlaveNormalMaster = 0x3 /*!< Normal master */ -} i2s_master_slave_t; - -/*! @brief I2S mode. */ -typedef enum _i2s_mode -{ - kI2S_ModeI2sClassic = 0x0, /*!< I2S classic mode */ - kI2S_ModeDspWs50 = 0x1, /*!< DSP mode, WS having 50% duty cycle */ - kI2S_ModeDspWsShort = 0x2, /*!< DSP mode, WS having one clock long pulse */ - kI2S_ModeDspWsLong = 0x3 /*!< DSP mode, WS having one data slot long pulse */ -} i2s_mode_t; - -/*! @brief _i2s_secondary_channel I2S secondary channel. */ -enum -{ - kI2S_SecondaryChannel1 = 0U, /*!< secondary channel 1 */ - kI2S_SecondaryChannel2 = 1U, /*!< secondary channel 2 */ - kI2S_SecondaryChannel3 = 2U, /*!< secondary channel 3 */ -}; - -/*! @brief I2S configuration structure. */ -typedef struct _i2s_config -{ - i2s_master_slave_t masterSlave; /*!< Master / slave configuration */ - i2s_mode_t mode; /*!< I2S mode */ - bool rightLow; /*!< Right channel data in low portion of FIFO */ - bool leftJust; /*!< Left justify data in FIFO */ -#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) - bool pdmData; /*!< Data source is the D-Mic subsystem */ -#endif - bool sckPol; /*!< SCK polarity */ - bool wsPol; /*!< WS polarity */ - uint16_t divider; /*!< Flexcomm function clock divider (1 - 4096) */ - bool oneChannel; /*!< true mono, false stereo */ - uint8_t dataLength; /*!< Data length (4 - 32) */ - uint16_t frameLength; /*!< Frame width (4 - 512) */ - uint16_t position; /*!< Data position in the frame */ - uint8_t watermark; /*!< FIFO trigger level */ - bool txEmptyZero; /*!< Transmit zero when buffer becomes empty or last item */ - bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit - values) */ -} i2s_config_t; - -/*! @brief Buffer to transfer from or receive audio data into. */ -typedef struct _i2s_transfer -{ - uint8_t *data; /*!< Pointer to data buffer. */ - size_t dataSize; /*!< Buffer size in bytes. */ -} i2s_transfer_t; - -/*! @brief Transactional state of the intialized transfer or receive I2S operation. */ -typedef struct _i2s_handle i2s_handle_t; - -/*! - * @brief Callback function invoked from transactional API - * on completion of a single buffer transfer. - * - * @param base I2S base pointer. - * @param handle pointer to I2S transaction. - * @param completionStatus status of the transaction. - * @param userData optional pointer to user arguments data. - */ -typedef void (*i2s_transfer_callback_t)(I2S_Type *base, - i2s_handle_t *handle, - status_t completionStatus, - void *userData); - -/*! @brief Members not to be accessed / modified outside of the driver. */ -struct _i2s_handle -{ - volatile uint32_t state; /*!< State of transfer */ - i2s_transfer_callback_t completionCallback; /*!< Callback function pointer */ - void *userData; /*!< Application data passed to callback */ - bool oneChannel; /*!< true mono, false stereo */ - uint8_t dataLength; /*!< Data length (4 - 32) */ - bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit - values) */ - uint8_t watermark; /*!< FIFO trigger level */ - bool useFifo48H; /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */ - - volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ - volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ - volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ - volatile uint32_t errorCount; /*!< Number of buffer underruns/overruns */ - volatile uint32_t transferCount; /*!< Number of bytes transferred */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S transmission using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_TxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the I2S driver. - * - * @param base I2S base pointer. - * @param config pointer to I2S configuration structure. - */ -void I2S_TxInit(I2S_Type *base, const i2s_config_t *config); - -/*! - * @brief Initializes the FLEXCOMM peripheral for I2S receive functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S receive using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_RxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the I2S driver. - * - * @param base I2S base pointer. - * @param config pointer to I2S configuration structure. - */ -void I2S_RxInit(I2S_Type *base, const i2s_config_t *config); - -/*! - * @brief Sets the I2S Tx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_TxInit(). - * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified - * before calling I2S_TxInit(). - * Example: - @code - i2s_config_t config; - I2S_TxGetDefaultConfig(&config); - @endcode - * - * Default values: - * @code - * config->masterSlave = kI2S_MasterSlaveNormalMaster; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = true; - * config->pack48 = false; - * @endcode - * - * @param config pointer to I2S configuration structure. - */ -void I2S_TxGetDefaultConfig(i2s_config_t *config); - -/*! - * @brief Sets the I2S Rx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_RxInit(). - * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified - * before calling I2S_RxInit(). - * Example: - @code - i2s_config_t config; - I2S_RxGetDefaultConfig(&config); - @endcode - * - * Default values: - * @code - * config->masterSlave = kI2S_MasterSlaveNormalSlave; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = false; - * config->pack48 = false; - * @endcode - * - * @param config pointer to I2S configuration structure. - */ -void I2S_RxGetDefaultConfig(i2s_config_t *config); - -/*! - * @brief De-initializes the I2S peripheral. - * - * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit - * or I2S_RxInit is called to enable the clock. - * - * @param base I2S base pointer. - */ -void I2S_Deinit(I2S_Type *base); - -/*! - * @brief Transmitter/Receiver bit clock rate configurations. - * - * @param base SAI base pointer. - * @param sourceClockHz bit clock source frequency. - * @param sampleRate audio data sample rate. - * @param bitWidth audio data bitWidth. - * @param channelNumbers audio channel numbers. - */ -void I2S_SetBitClockRate( - I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers); - -/*! @} */ - -/*! - * @name Non-blocking API - * @{ - */ - -/*! - * @brief Initializes handle for transfer of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); - -/*! - * @brief Begins or queue sending of the given data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts sending of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Initializes handle for reception of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); - -/*! - * @brief Begins or queue reception of data into given buffer. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. - */ -status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts receiving of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Returns number of bytes transferred so far. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param[out] count number of bytes transferred so far by the non-blocking transaction. - * - * @retval kStatus_Success - * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); - -/*! - * @brief Returns number of buffer underruns or overruns. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param[out] count number of transmit errors encountered so far by the non-blocking transaction. - * - * @retval kStatus_Success - * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); - -/*! @} */ - -/*! - * @name Enable / disable - * @{ - */ - -/*! - * @brief Enables I2S operation. - * - * @param base I2S base pointer. - */ -static inline void I2S_Enable(I2S_Type *base) -{ - base->CFG1 |= I2S_CFG1_MAINENABLE(1U); -} - -#if (defined(FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) && FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) -/*! - * @brief Enables I2S secondary channel. - * - * @param base I2S base pointer. - * @param channel seondary channel channel number, reference _i2s_secondary_channel. - * @param oneChannel true is treated as single channel, functionality left channel for this pair. - * @param position define the location within the frame of the data, should not bigger than 0x1FFU. - */ -void I2S_EnableSecondaryChannel(I2S_Type *base, uint32_t channel, bool oneChannel, uint32_t position); - -/*! - * @brief Disables I2S secondary channel. - * - * @param base I2S base pointer. - * @param channel seondary channel channel number, reference _i2s_secondary_channel. - */ -static inline void I2S_DisableSecondaryChannel(I2S_Type *base, uint32_t channel) -{ -#if defined FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn - assert(FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn((FLEXCOMM_Type *)(uint32_t)base) == 1); -#endif - - base->SECCHANNEL[channel].PCFG1 &= ~I2S_CFG1_MAINENABLE_MASK; -} -#endif -/*! - * @brief Disables I2S operation. - * - * @param base I2S base pointer. - */ -static inline void I2S_Disable(I2S_Type *base) -{ - base->CFG1 &= (~I2S_CFG1_MAINENABLE(1U)); -} - -/*! @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables I2S FIFO interrupts. - * - * @param base I2S base pointer. - * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2S_EnableInterrupts(I2S_Type *base, uint32_t interruptMask) -{ - base->FIFOINTENSET = interruptMask; -} - -/*! - * @brief Disables I2S FIFO interrupts. - * - * @param base I2S base pointer. - * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2S_DisableInterrupts(I2S_Type *base, uint32_t interruptMask) -{ - base->FIFOINTENCLR = interruptMask; -} - -/*! - * @brief Returns the set of currently enabled I2S FIFO interrupts. - * - * @param base I2S base pointer. - * - * @return A bitmask composed of #i2s_flags_t enumerators OR'd together - * to indicate the set of enabled interrupts. - */ -static inline uint32_t I2S_GetEnabledInterrupts(I2S_Type *base) -{ - return base->FIFOINTENSET; -} - -/*! - * @brief Invoked from interrupt handler when transmit FIFO level decreases. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Invoked from interrupt handler when receive FIFO level decreases. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); - -/*! @} */ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2S_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s_dma.c deleted file mode 100644 index eb5e430eb63..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s_dma.c +++ /dev/null @@ -1,647 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_dma.h" -#include "fsl_i2s_dma.h" -#include "fsl_flexcomm.h" -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s_dma" -#endif - -#define DMA_MAX_TRANSFER_BYTES (DMA_MAX_TRANSFER_COUNT * sizeof(uint32_t)) -#define DMA_DESCRIPTORS (2U) - -/*i2sQueue[handle->queueUser].dataSize != 0UL) - { - /* Previously prepared buffers not processed yet, reject request */ - return kStatus_I2S_Busy; - } - - /* Enqueue data */ - privateHandle->descriptorQueue[handle->queueUser].data = transfer.data; - privateHandle->descriptorQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - return kStatus_Success; -} - -static uint32_t I2S_GetInstance(I2S_Type *base) -{ - uint32_t i; - - for (i = 0U; i < ARRAY_SIZE(s_I2sBaseAddrs); i++) - { - if ((uint32_t)base == s_I2sBaseAddrs[i]) - { - return i; - } - } - - assert(false); - return 0U; -} - -static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle) -{ - DMA_DisableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); -} - -static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle) -{ - if (handle->state != (uint32_t)kI2S_DmaStateIdle) - { - DMA_EnableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); - } -} - -/*! - * brief Initializes handle for transfer of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param dmaHandle pointer to dma handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData) -{ - assert(handle != NULL); - assert(dmaHandle != NULL); - - uint32_t instance = I2S_GetInstance(base); - i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - - (void)memset(handle, 0, sizeof(*handle)); - handle->state = (uint32_t)kI2S_DmaStateIdle; - handle->dmaHandle = dmaHandle; - handle->completionCallback = callback; - handle->userData = userData; - - handle->bytesPerFrame = (uint8_t)((((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U) / 8U); - /* if one channel is disabled, bytesPerFrame should be 4U, user should pay attention that when data length is - * shorter than 16, the data format: left data put in 0-15 bit and right data should put in 16-31 - */ - if (((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) == 0U)) - { - handle->bytesPerFrame = 4U; - } - /* since DMA do not support 24bit transfer width, use 32bit instead */ - if (handle->bytesPerFrame == 3U) - { - handle->bytesPerFrame = 4U; - } - - (void)memset(privateHandle, 0, sizeof(*privateHandle)); - privateHandle->base = base; - privateHandle->handle = handle; - - DMA_SetCallback(dmaHandle, I2S_DMACallback, privateHandle); -} - -/*! - * brief Begins or queue sending of the given data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) -{ - status_t status; - - I2S_DisableDMAInterrupts(handle); - - /* Enqueue transfer buffer */ - status = I2S_EnqueueUserBuffer(base, handle, transfer); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - - /* Initialize DMA transfer */ - if (handle->state == (uint32_t)kI2S_DmaStateIdle) - { - handle->state = (uint32_t)kI2S_DmaStateTx; - status = I2S_StartTransferDMA(base, handle); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - } - - I2S_AddTransferDMA(base, handle); - I2S_EnableDMAInterrupts(handle); - - return kStatus_Success; -} - -/*! - * brief Aborts transfer of data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - assert(handle != NULL); - assert(handle->dmaHandle != NULL); - - uint32_t instance = I2S_GetInstance(base); - i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - - I2S_DisableDMAInterrupts(handle); - - /* Abort operation */ - DMA_AbortTransfer(handle->dmaHandle); - - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - /* Wait until all transmitted data get out of FIFO */ - while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) - { - } - /* The last piece of valid data can be still being transmitted from I2S at this moment */ - - /* Write additional data to FIFO */ - base->FIFOWR = 0U; - while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) - { - } - /* At this moment the additional data are out of FIFO, starting being transmitted. - * This means the preceding valid data has been just transmitted and we can stop I2S. */ - I2S_TxEnableDMA(base, false); - } - else - { - I2S_RxEnableDMA(base, false); - } - - I2S_Disable(base); - - /* Reset state */ - handle->state = (uint32_t)kI2S_DmaStateIdle; - - /* Clear transfer queue */ - (void)memset((void *)&(handle->i2sQueue), 0, sizeof(handle->i2sQueue)); - handle->queueDriver = 0U; - handle->queueUser = 0U; - - /* Clear internal state */ - (void)memset((void *)&(privateHandle->descriptorQueue), 0, sizeof(privateHandle->descriptorQueue)); - (void)memset((void *)&(privateHandle->enqueuedBytes), 0, sizeof(privateHandle->enqueuedBytes)); - privateHandle->enqueuedBytesStart = 0U; - privateHandle->enqueuedBytesEnd = 0U; - privateHandle->dmaDescriptorsUsed = 0U; - privateHandle->descriptor = 0U; - privateHandle->queueDescriptor = 0U; - privateHandle->intA = false; -} - -/*! - * brief Initializes handle for reception of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param dmaHandle pointer to dma handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData) -{ - I2S_TxTransferCreateHandleDMA(base, handle, dmaHandle, callback, userData); -} - -/*! - * brief Begins or queue reception of data into given buffer. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with buffers - * which are not full. - */ -status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) -{ - status_t status; - - I2S_DisableDMAInterrupts(handle); - - /* Enqueue transfer buffer */ - status = I2S_EnqueueUserBuffer(base, handle, transfer); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - - /* Initialize DMA transfer */ - if (handle->state == (uint32_t)kI2S_DmaStateIdle) - { - handle->state = (uint32_t)kI2S_DmaStateRx; - status = I2S_StartTransferDMA(base, handle); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - } - - I2S_AddTransferDMA(base, handle); - I2S_EnableDMAInterrupts(handle); - - return kStatus_Success; -} - -static void I2S_TxEnableDMA(I2S_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= I2S_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= (~I2S_FIFOCFG_DMATX_MASK); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - } -} - -static void I2S_RxEnableDMA(I2S_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= I2S_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= (~I2S_FIFOCFG_DMARX_MASK); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - } -} - -static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer) -{ - assert(transfer != NULL); - - uint16_t transferBytes; - - if (transfer->dataSize >= (2UL * DMA_MAX_TRANSFER_BYTES)) - { - transferBytes = DMA_MAX_TRANSFER_BYTES; - } - else if (transfer->dataSize > DMA_MAX_TRANSFER_BYTES) - { - transferBytes = (uint16_t)(transfer->dataSize / 2U); - if ((transferBytes % 4U) != 0U) - { - transferBytes -= (transferBytes % 4U); - } - } - else - { - transferBytes = (uint16_t)transfer->dataSize; - } - - return transferBytes; -} - -static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - uint32_t instance = I2S_GetInstance(base); - i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - volatile i2s_transfer_t *transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); - uint16_t transferBytes = I2S_GetTransferBytes(transfer); - uint32_t i = 0U; - uint32_t xferConfig = 0U; - uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; - - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - srcAddr = (uint32_t *)(uint32_t)transfer->data; - destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); - srcInc = 1U; - destInc = 0UL; - } - else - { - srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); - destAddr = (uint32_t *)(uint32_t)transfer->data; - srcInc = 0U; - destInc = 1UL; - } - /* Initial descriptor is stored in another place in memory, but treat it as another descriptor for simplicity */ - privateHandle->dmaDescriptorsUsed = 1U; - privateHandle->intA = false; - - /* submit transfer parameter directly */ - xferConfig = DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 1UL, handle->bytesPerFrame, srcInc, destInc, (uint32_t)transferBytes); - - DMA_SubmitChannelTransferParameter(handle->dmaHandle, xferConfig, srcAddr, destAddr, - (void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U])); - - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; - privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; - - transfer->dataSize -= transferBytes; - transfer->data = (uint8_t *)((uint32_t)transfer->data + transferBytes); - - if (transfer->dataSize == 0U) - { - transfer->data = NULL; - privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; - } - - /* Link the DMA descriptors for the case when no additional transfer is queued before the initial one finishes - * The configuration for the DMA dummy descriptor make no sense to tx or rx transfer, since it will be overwritten - * when another transfer request comes before the previous finished. - * To make sure the audio data transfer continuously, application must request another transfer by call - * I2S_RxTransferReceiveDMA or I2S_TxTransferSendDMA before previous transfer finished. - */ - for (i = 0; i < DMA_DESCRIPTORS; i++) - { - /* DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 0UL, sizeof(uint32_t), 0U, 0U, 8U) = 0x10203UL */ - DMA_SetupDescriptor( - &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + i]), 0x10203UL, - ((handle->state == (uint32_t)kI2S_DmaStateTx) ? &s_DummyBufferTx : (uint32_t *)(uint32_t)(&(base->FIFORD))), - ((handle->state == (uint32_t)kI2S_DmaStateTx) ? (uint32_t *)(uint32_t)(&(base->FIFOWR)) : &s_DummyBufferRx), - &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + ((i + 1U) % DMA_DESCRIPTORS)])); - } - - /* Submit and start initial DMA transfer */ - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - I2S_TxEnableDMA(base, true); - } - else - { - I2S_RxEnableDMA(base, true); - } - /* enable I2S peripheral request and put the channel into triggered status */ - DMA_EnableChannelPeriphRq(handle->dmaHandle->base, handle->dmaHandle->channel); - DMA_StartTransfer(handle->dmaHandle); - - I2S_Enable(base); - - return kStatus_Success; -} - -static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - volatile i2s_transfer_t *transfer; - uint16_t transferBytes; - uint32_t instance; - i2s_dma_private_handle_t *privateHandle; - dma_descriptor_t *descriptor; - dma_descriptor_t *nextDescriptor; - uint32_t xferConfig = 0U; - bool intA = false; - uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; - - instance = I2S_GetInstance(base); - privateHandle = &(s_DmaPrivateHandle[instance]); - - while (privateHandle->dmaDescriptorsUsed < DMA_DESCRIPTORS) - { - transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); - intA = privateHandle->intA; - if (transfer->dataSize == 0U) - { - /* Nothing to be added */ - return; - } - - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - srcAddr = (uint32_t *)(uint32_t)transfer->data; - destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); - srcInc = 1U; - destInc = 0UL; - } - else - { - srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); - destAddr = (uint32_t *)(uint32_t)transfer->data; - srcInc = 0U; - destInc = 1UL; - } - - /* Determine currently configured descriptor and the other which it will link to */ - descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); - privateHandle->descriptor = (privateHandle->descriptor + 1U) % DMA_DESCRIPTORS; - nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); - - transferBytes = I2S_GetTransferBytes(transfer); - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; - privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; - - xferConfig = - DMA_CHANNEL_XFER(1UL, 0UL, !intA, intA, handle->bytesPerFrame, srcInc, destInc, (uint32_t)transferBytes); - - DMA_SetupDescriptor(descriptor, xferConfig, srcAddr, destAddr, nextDescriptor); - - /* Advance internal state */ - privateHandle->dmaDescriptorsUsed++; - privateHandle->intA = !privateHandle->intA; - - transfer->dataSize -= transferBytes; - transfer->data += transferBytes; - if (transfer->dataSize == 0U) - { - transfer->data = NULL; - privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; - } - } -} - -/*! - * brief Invoked from DMA interrupt handler. - * - * param handle pointer to DMA handle structure. - * param userData argument for user callback. - * param transferDone if transfer was done. - * param tcds - */ -void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds) -{ - i2s_dma_private_handle_t *privateHandle = (i2s_dma_private_handle_t *)userData; - i2s_dma_handle_t *i2sHandle = privateHandle->handle; - I2S_Type *base = privateHandle->base; - uint8_t queueDriverIndex = i2sHandle->queueDriver; - uint32_t enqueueBytes = privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart]; - uint32_t queueDataAddr = (uint32_t)i2sHandle->i2sQueue[queueDriverIndex].data; - - if ((!transferDone) || (i2sHandle->state == (uint32_t)kI2S_DmaStateIdle)) - { - return; - } - - if (privateHandle->dmaDescriptorsUsed > 0U) - { - /* Finished descriptor, decrease amount of data to be processed */ - - i2sHandle->i2sQueue[queueDriverIndex].dataSize -= enqueueBytes; - i2sHandle->i2sQueue[queueDriverIndex].data = (uint8_t *)(queueDataAddr + enqueueBytes); - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] = 0U; - privateHandle->enqueuedBytesStart = (privateHandle->enqueuedBytesStart + 1U) % DMA_DESCRIPTORS; - privateHandle->dmaDescriptorsUsed--; - } - - if (i2sHandle->i2sQueue[queueDriverIndex].dataSize == 0U) - { - /* Entire user buffer sent or received - advance to next one */ - i2sHandle->i2sQueue[queueDriverIndex].data = NULL; - i2sHandle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; - /* Notify user about buffer completion */ - if (i2sHandle->completionCallback != NULL) - { - (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_BufferComplete, i2sHandle->userData); - } - } - /* check next buffer queue is avaliable or not */ - if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U) - { - /* All user buffers processed */ - I2S_TransferAbortDMA(base, i2sHandle); - } - else - { - /* Enqueue another user buffer to DMA if it could not be done when in I2S_Rx/TxTransferSendDMA */ - I2S_AddTransferDMA(base, i2sHandle); - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s_dma.h deleted file mode 100644 index 469e1f8ede1..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s_dma.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2S_DMA_H_ -#define _FSL_I2S_DMA_H_ - -#include "fsl_device_registers.h" -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -#include "fsl_dma.h" -#include "fsl_i2s.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup i2s_dma_driver - * @{ - */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2S DMA driver version 2.2.2. */ -#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) -/*@}*/ - -/*! @brief Members not to be accessed / modified outside of the driver. */ -typedef struct _i2s_dma_handle i2s_dma_handle_t; - -/*! - * @brief Callback function invoked from DMA API on completion. - * - * @param base I2S base pointer. - * @param handle pointer to I2S transaction. - * @param completionStatus status of the transaction. - * @param userData optional pointer to user arguments data. - */ -typedef void (*i2s_dma_transfer_callback_t)(I2S_Type *base, - i2s_dma_handle_t *handle, - status_t completionStatus, - void *userData); -/*! @brief i2s dma handle */ -struct _i2s_dma_handle -{ - uint32_t state; /*!< Internal state of I2S DMA transfer */ - uint8_t bytesPerFrame; /*!< bytes per frame */ - i2s_dma_transfer_callback_t completionCallback; /*!< Callback function pointer */ - void *userData; /*!< Application data passed to callback */ - dma_handle_t *dmaHandle; /*!< DMA handle */ - volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ - volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ - volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! @} */ - -/*! - * @name DMA API - * @{ - */ - -/*! - * @brief Initializes handle for transfer of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param dmaHandle pointer to dma handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData); - -/*! - * @brief Begins or queue sending of the given data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts transfer of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle); - -/*! - * @brief Initializes handle for reception of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param dmaHandle pointer to dma handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData); - -/*! - * @brief Begins or queue reception of data into given buffer. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers - * which are not full. - */ -status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Invoked from DMA interrupt handler. - * - * @param handle pointer to DMA handle structure. - * @param userData argument for user callback. - * @param transferDone if transfer was done. - * @param tcds - */ -void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds); - -/*! @} */ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2S_DMA_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i3c.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i3c.c deleted file mode 100644 index 257db3ed26c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i3c.c +++ /dev/null @@ -1,2823 +0,0 @@ -/* - * Copyright 2018-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_i3c.h" -#include -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.i3c" -#endif - -#define I3C_BROADCASE_ADDR (0x7EU) - -#define NSEC_PER_SEC (1000000000UL) -#define FSL_I3C_ERROR_RATE_MAX (10U) -#define FSL_I3C_PPBAUD_DIV_MAX ((I3C_MCONFIG_PPBAUD_MASK >> I3C_MCONFIG_PPBAUD_SHIFT) + 1U) -#define FSL_I3C_ODBAUD_DIV_MAX ((I3C_MCONFIG_ODBAUD_MASK >> I3C_MCONFIG_ODBAUD_SHIFT) + 1U) -#define FSL_I3C_I2CBAUD_DIV_MAX (((I3C_MCONFIG_I2CBAUD_MASK >> I3C_MCONFIG_I2CBAUD_SHIFT) + 1U) / 2U) - -/*! @brief Common sets of flags used by the driver. */ -enum _i3c_flag_constants -{ - /*! All flags which are cleared by the driver upon starting a transfer. */ - kMasterClearFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag | - kI3C_MasterArbitrationWonFlag | kI3C_MasterSlave2MasterFlag | kI3C_MasterErrorFlag, - - /*! IRQ sources enabled by the non-blocking transactional API. */ - kMasterIrqFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag | - kI3C_MasterRxReadyFlag /* | kI3C_MasterTxReadyFlag */ | kI3C_MasterArbitrationWonFlag | - kI3C_MasterErrorFlag | kI3C_MasterSlave2MasterFlag, - - /*! Errors to check for. */ - kMasterErrorFlags = kI3C_MasterErrorNackFlag | kI3C_MasterErrorWriteAbortFlag | -#if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) - kI3C_MasterErrorTermFlag | -#endif - kI3C_MasterErrorParityFlag | kI3C_MasterErrorCrcFlag | kI3C_MasterErrorReadFlag | - kI3C_MasterErrorWriteFlag | kI3C_MasterErrorMsgFlag | kI3C_MasterErrorInvalidReqFlag | - kI3C_MasterErrorTimeoutFlag, - /*! All flags which are cleared by the driver upon starting a transfer. */ - kSlaveClearFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag | kI3C_SlaveBusStopFlag, - - /*! IRQ sources enabled by the non-blocking transactional API. */ - kSlaveIrqFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag | kI3C_SlaveBusStopFlag | kI3C_SlaveRxReadyFlag | - kI3C_SlaveDynamicAddrChangedFlag | kI3C_SlaveReceivedCCCFlag | kI3C_SlaveErrorFlag | - kI3C_SlaveHDRCommandMatchFlag | kI3C_SlaveCCCHandledFlag | kI3C_SlaveEventSentFlag, - - /*! Errors to check for. */ - kSlaveErrorFlags = kI3C_SlaveErrorOverrunFlag | kI3C_SlaveErrorUnderrunFlag | kI3C_SlaveErrorUnderrunNakFlag | - kI3C_SlaveErrorTermFlag | kI3C_SlaveErrorInvalidStartFlag | kI3C_SlaveErrorSdrParityFlag | - kI3C_SlaveErrorHdrParityFlag | kI3C_SlaveErrorHdrCRCFlag | kI3C_SlaveErrorS0S1Flag | - kI3C_SlaveErrorOverreadFlag | kI3C_SlaveErrorOverwriteFlag, -}; - -/*! @brief States for the state machine used by transactional APIs. */ -enum _i3c_transfer_states -{ - kIdleState = 0, - kIBIWonState, - kSlaveStartState, - kSendCommandState, - kWaitRepeatedStartCompleteState, - kTransferDataState, - kStopState, - kWaitForCompletionState, -}; - -/*! @brief Typedef for slave interrupt handler. */ -typedef void (*i3c_slave_isr_t)(I3C_Type *base, i3c_slave_handle_t *handle); - -/*! - * @brief Used for conversion between `uint8_t*` and `uint32_t`. - */ -typedef union i3c_puint8_to_u32 -{ - uint8_t *puint8; - uint32_t u32; - const uint8_t *cpuint8; -} i3c_puint8_to_u32_t; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/* Not static so it can be used from fsl_i3c_dma.c. */ -static status_t I3C_MasterWaitForTxReady(I3C_Type *base, uint8_t byteCounts); -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map I3C instance number to base pointer. */ -static I3C_Type *const kI3cBases[] = I3C_BASE_PTRS; - -/*! @brief Array to map I3C instance number to IRQ number. */ -IRQn_Type const kI3cIrqs[] = I3C_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map I3C instance number to clock gate enum. */ -static clock_ip_name_t const kI3cClocks[] = I3C_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) -/*! @brief Pointers to I3C resets for each instance. */ -static const reset_ip_name_t kI3cResets[] = I3C_RSTS; -#endif - -static i3c_device_info_t devList[I3C_MAX_DEVCNT]; /*!< I3C slave record list */ - -/*! @brief Pointer to master IRQ handler for each instance. */ -i3c_master_isr_t s_i3cMasterIsr; - -/*! @brief Pointers to master handles for each instance. */ -void *s_i3cMasterHandle[ARRAY_SIZE(kI3cBases)]; - -/*! @brief Pointer to slave IRQ handler for each instance. */ -static i3c_slave_isr_t s_i3cSlaveIsr; - -/*! @brief Pointers to slave handles for each instance. */ -i3c_slave_handle_t *s_i3cSlaveHandle[ARRAY_SIZE(kI3cBases)]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * @brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * @param base The I3C peripheral base address. - * @return I3C instance number starting from 0. - */ -uint32_t I3C_GetInstance(I3C_Type *base) -{ - uint32_t instance; - for (instance = 0; instance < ARRAY_SIZE(kI3cBases); ++instance) - { - if (kI3cBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(kI3cBases)); - - return instance; -} - -/*! - * @brief Convert provided flags to status code, and clear any errors if present. - * @param base The I3C peripheral base address. - * @param status Current status flags value that will be checked. - * @retval #kStatus_Success - * @retval #kStatus_I3C_Nak - * @retval #kStatus_I3C_WriteAbort - * @retval #kStatus_I3C_Term - * @retval #kStatus_I3C_HdrParityError - * @retval #kStatus_I3C_CrcError - * @retval #kStatus_I3C_ReadFifoError - * @retval #kStatus_I3C_WriteFifoError - * @retval #kStatus_I3C_MsgError - * @retval #kStatus_I3C_InvalidReq - * @retval #kStatus_I3C_Timeout - */ -/* Not static so it can be used from fsl_i3c_edma.c. */ -status_t I3C_MasterCheckAndClearError(I3C_Type *base, uint32_t status) -{ - status_t result = kStatus_Success; - - /* Check for error. These errors cause a stop to automatically be sent. We must */ - /* clear the errors before a new transfer can start. */ - status &= (uint32_t)kMasterErrorFlags; - if (0UL != (status)) - { - /* Select the correct error code. Ordered by severity, with bus issues first. */ - if (0UL != (status & (uint32_t)kI3C_MasterErrorTimeoutFlag)) - { - result = kStatus_I3C_Timeout; - } - else if (0UL != (status & (uint32_t)kI3C_MasterErrorNackFlag)) - { - result = kStatus_I3C_Nak; - } - else if (0UL != (status & (uint32_t)kI3C_MasterErrorWriteAbortFlag)) - { - result = kStatus_I3C_WriteAbort; - } -#if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) - else if (0UL != (status & (uint32_t)kI3C_MasterErrorTermFlag)) - { - result = kStatus_I3C_Term; - } -#endif - else if (0UL != (status & (uint32_t)kI3C_MasterErrorParityFlag)) - { - result = kStatus_I3C_HdrParityError; - } - else if (0UL != (status & (uint32_t)kI3C_MasterErrorCrcFlag)) - { - result = kStatus_I3C_CrcError; - } - else if (0UL != (status & (uint32_t)kI3C_MasterErrorMsgFlag)) - { - result = kStatus_I3C_MsgError; - } - else if (0UL != (status & (uint32_t)kI3C_MasterErrorReadFlag)) - { - result = kStatus_I3C_ReadFifoError; - } - else if (0UL != (status & (uint32_t)kI3C_MasterErrorWriteFlag)) - { - result = kStatus_I3C_WriteFifoError; - } - else if (0UL != (status & (uint32_t)kI3C_MasterErrorInvalidReqFlag)) - { - result = kStatus_I3C_InvalidReq; - } - else - { - assert(false); - } - - /* Clear the flags. */ - I3C_MasterClearErrorStatusFlags(base, status); - - /* Reset fifos. These flags clear automatically. */ - base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; - } - - return result; -} - -static status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle) -{ - status_t result = kStatus_Success; - uint32_t status, errStatus; -#if I3C_RETRY_TIMES - uint32_t waitTimes = I3C_RETRY_TIMES; -#endif - -#if I3C_RETRY_TIMES - while ((result == kStatus_Success) && (--waitTimes)) -#else - while (result == kStatus_Success) -#endif - { - status = I3C_MasterGetStatusFlags(base); - errStatus = I3C_MasterGetErrorStatusFlags(base); - /* Check for error flags. */ - result = I3C_MasterCheckAndClearError(base, errStatus); - /* Check if the control finishes. */ - if (0UL != (status & (uint32_t)kI3C_MasterControlDoneFlag)) - { - I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterControlDoneFlag); - if (!waitIdle) - { - break; - } - } - /* kI3C_MasterControlDoneFlag only indicates ACK got, need to wait for SDA high. */ - if (waitIdle && I3C_MasterGetState(base) == kI3C_MasterStateIdle) - { - break; - } - } - -#if I3C_RETRY_TIMES - if (waitTimes == 0) - { - return kStatus_I3C_Timeout; - } -#endif - - return result; -} - -static status_t I3C_MasterWaitForTxReady(I3C_Type *base, uint8_t byteCounts) -{ - uint32_t errStatus; - status_t result; - size_t txCount; - size_t txFifoSize = - 2UL << ((base->SCAPABILITIES & I3C_SCAPABILITIES_FIFOTX_MASK) >> I3C_SCAPABILITIES_FIFOTX_SHIFT); - -#if I3C_RETRY_TIMES - uint32_t waitTimes = I3C_RETRY_TIMES; -#endif - do - { - /* Get the number of words in the tx fifo and compute empty slots. */ - I3C_MasterGetFifoCounts(base, NULL, &txCount); - txCount = txFifoSize - txCount; - - /* Check for error flags. */ - errStatus = I3C_MasterGetErrorStatusFlags(base); - result = I3C_MasterCheckAndClearError(base, errStatus); - if (kStatus_Success != result) - { - return result; - } -#if I3C_RETRY_TIMES - } while ((txCount < byteCounts) && (--waitTimes)); - - if (waitTimes == 0) - { - return kStatus_I3C_Timeout; - } -#else - } while (txCount < byteCounts); -#endif - - return kStatus_Success; -} - -static status_t I3C_MasterWaitForComplete(I3C_Type *base, bool waitIdle) -{ - uint32_t status, errStatus; - status_t result = kStatus_Success; -#if I3C_RETRY_TIMES - uint32_t waitTimes = I3C_RETRY_TIMES; -#endif - do - { - status = I3C_MasterGetStatusFlags(base); - errStatus = I3C_MasterGetErrorStatusFlags(base); - result = I3C_MasterCheckAndClearError(base, errStatus); -#if I3C_RETRY_TIMES - } while (((status & (uint32_t)kI3C_MasterCompleteFlag) != (uint32_t)kI3C_MasterCompleteFlag) && - (result == kStatus_Success) && --waitTimes); -#else - } while (((status & (uint32_t)kI3C_MasterCompleteFlag) != (uint32_t)kI3C_MasterCompleteFlag) && - (result == kStatus_Success)); -#endif - - I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterCompleteFlag); - -#if I3C_RETRY_TIMES - if (waitTimes == 0UL) - { - return kStatus_I3C_Timeout; - } -#endif - - if (waitIdle) - { -#if I3C_RETRY_TIMES - while ((I3C_MasterGetState(base) != kI3C_MasterStateIdle) && --waitTimes) -#else - while (I3C_MasterGetState(base) != kI3C_MasterStateIdle) -#endif - { - } - } - - return result; -} - -/*! - * @brief Convert provided flags to status code, and clear any errors if present. - * @param base The I3C peripheral base address. - * @param status Current status flags value that will be checked. - * @retval #kStatus_Success - * @retval #kStatus_I3C_OverrunError - * @retval #kStatus_I3C_UnderrunError - * @retval #kStatus_I3C_UnderrunNak - * @retval #kStatus_I3C_Term - * @retval #kStatus_I3C_InvalidStart - * @retval #kStatus_I3C_SdrParityError - * @retval #kStatus_I3C_HdrParityError - * @retval #kStatus_I3C_CrcError - * @retval #kStatus_I3C_S0S1Error - * @retval #kStatus_I3C_ReadFifoError - * @retval #kStatus_I3C_WriteFifoError - */ -static status_t I3C_SlaveCheckAndClearError(I3C_Type *base, uint32_t status) -{ - status_t result = kStatus_Success; - - /* Check for error. These errors cause a stop to automatically be sent. We must */ - /* clear the errors before a new transfer can start. */ - status &= (uint32_t)kSlaveErrorFlags; - if (0UL != status) - { - /* Select the correct error code. Ordered by severity, with bus issues first. */ - if (0UL != (status & (uint32_t)kI3C_SlaveErrorOverrunFlag)) - { - result = kStatus_I3C_OverrunError; - } - else if (0UL != (status & (uint32_t)kI3C_SlaveErrorUnderrunFlag)) - { - result = kStatus_I3C_UnderrunError; - } - else if (0UL != (status & (uint32_t)kI3C_SlaveErrorUnderrunNakFlag)) - { - result = kStatus_I3C_UnderrunNak; - } - else if (0UL != (status & (uint32_t)kI3C_SlaveErrorTermFlag)) - { - result = kStatus_I3C_Term; - } - else if (0UL != (status & (uint32_t)kI3C_SlaveErrorInvalidStartFlag)) - { - result = kStatus_I3C_InvalidStart; - } - else if (0UL != (status & (uint32_t)kI3C_SlaveErrorSdrParityFlag)) - { - result = kStatus_I3C_SdrParityError; - } - else if (0UL != (status & (uint32_t)kI3C_SlaveErrorHdrParityFlag)) - { - result = kStatus_I3C_HdrParityError; - } - else if (0UL != (status & (uint32_t)kI3C_SlaveErrorHdrCRCFlag)) - { - result = kStatus_I3C_CrcError; - } - else if (0UL != (status & (uint32_t)kI3C_SlaveErrorS0S1Flag)) - { - result = kStatus_I3C_S0S1Error; - } - else if (0UL != (status & (uint32_t)kI3C_SlaveErrorOverreadFlag)) - { - result = kStatus_I3C_ReadFifoError; - } - else if (0UL != (status & (uint32_t)kI3C_SlaveErrorOverwriteFlag)) - { - result = kStatus_I3C_WriteFifoError; - } - else - { - assert(false); - } - - /* Clear the flags. */ - I3C_SlaveClearErrorStatusFlags(base, status); - - /* Reset fifos. These flags clear automatically. */ - base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK; - } - - return result; -} - -static status_t I3C_SlaveWaitForTxReady(I3C_Type *base) -{ - uint32_t errStatus; - status_t result; - size_t txCount; - size_t txFifoSize = - 2UL << ((base->SCAPABILITIES & I3C_SCAPABILITIES_FIFOTX_MASK) >> I3C_SCAPABILITIES_FIFOTX_SHIFT); - -#if I3C_RETRY_TIMES - uint32_t waitTimes = I3C_RETRY_TIMES; -#endif - do - { - /* Get the number of words in the tx fifo and compute empty slots. */ - I3C_SlaveGetFifoCounts(base, NULL, &txCount); - txCount = txFifoSize - txCount; - - /* Check for error flags. */ - errStatus = I3C_SlaveGetErrorStatusFlags(base); - result = I3C_SlaveCheckAndClearError(base, errStatus); - if (kStatus_Success != result) - { - return result; - } -#if I3C_RETRY_TIMES - } while ((txCount == 0UL) && (--waitTimes)); - - if (waitTimes == 0) - { - return kStatus_I3C_Timeout; - } -#else - } while (txCount == 0UL); -#endif - - return kStatus_Success; -} - -static status_t I3C_MasterEmitStop(I3C_Type *base, bool waitIdle) -{ - status_t result = kStatus_Success; - - /* Return an error if the bus is not in transaction. */ - if (I3C_MasterGetState(base) != kI3C_MasterStateNormAct) - { - return kStatus_I3C_InvalidReq; - } - - /* Send the STOP signal */ - base->MCTRL = (base->MCTRL & ~(I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_RDTERM_MASK)) | - I3C_MCTRL_REQUEST(kI3C_RequestEmitStop); - - /* Wait for the stop operation finishes. */ - /* Also check for errors while waiting. */ - result = I3C_MasterWaitForCtrlDone(base, waitIdle); - - return result; -} - -static i3c_ibi_type_t I3C_GetIBIType(I3C_Type *base) -{ - uint32_t ibiValue = (base->MSTATUS & I3C_MSTATUS_IBITYPE_MASK) >> I3C_MSTATUS_IBITYPE_SHIFT; - i3c_ibi_type_t ibiType = kI3C_IbiNormal; - - switch (ibiValue) - { - case 3L: - ibiType = kI3C_IbiHotJoin; - break; - case 2L: - ibiType = kI3C_IbiMasterRequest; - break; - default: - ibiType = kI3C_IbiNormal; - break; - } - - return ibiType; -} - -static inline uint8_t I3C_GetIBIAddress(I3C_Type *base) -{ - return (uint8_t)((base->MSTATUS & I3C_MSTATUS_IBIADDR_MASK) >> I3C_MSTATUS_IBIADDR_SHIFT); -} -/*! - * @brief Make sure the bus isn't already busy. - * - * A busy bus is allowed if we are the one driving it. - * - * @param base The I3C peripheral base address. - * @retval #kStatus_Success - * @retval #kStatus_I3C_Busy - */ -/* Not static so it can be used from fsl_i3c_edma.c. */ -status_t I3C_CheckForBusyBus(I3C_Type *base) -{ - return (I3C_MasterGetBusIdleState(base) == true) ? kStatus_Success : kStatus_I3C_Busy; -} - -/* brief Provides a default configuration for the I3C peripheral. - * - */ -void I3C_GetDefaultConfig(i3c_config_t *config) -{ - assert(NULL != config); - - (void)memset(config, 0, sizeof(*config)); - - config->enableMaster = kI3C_MasterCapable; - config->disableTimeout = false; - config->hKeep = kI3C_MasterHighKeeperNone; - config->enableOpenDrainStop = true; - config->enableOpenDrainHigh = true; - config->baudRate_Hz.i2cBaud = 400000U; - config->baudRate_Hz.i3cPushPullBaud = 12500000U; - config->baudRate_Hz.i3cOpenDrainBaud = 2500000U; - config->masterDynamicAddress = 0x0AU; /* Default master dynamic address. */ - config->slowClock_Hz = 1000000U; /* Default slow timer clock 1MHz. */ - config->enableSlave = true; - config->vendorID = 0x11BU; - config->enableRandomPart = false; - config->partNumber = 0; - config->dcr = 0; /* Generic device. */ - config->bcr = 0; /* BCR[7:6]: device role, I3C slave(2b'00), BCR[5]: SDR Only / SDR and HDR Capable, SDR and HDR - Capable(1b'1), BCR[4]: Bridge Identifier, Not a bridge device(1b'0), BCR[3]: Offline Capable, - device is offline capable(1b'1), BCR[2]: IBI Payload, No data byte following(1b'0), BCR[1]: IBI - Request Capable, capable(1b'1), BCR[0]: Max Data Speed Limitation, has limitation(1b'1). */ - config->hdrMode = (uint8_t)kI3C_HDRModeDDR; - config->nakAllRequest = false; - config->ignoreS0S1Error = false; - config->offline = false; - config->matchSlaveStartStop = false; - config->maxWriteLength = 256U; - config->maxReadLength = 256U; -} - -/*! - * @brief Initializes the I3C peripheral. - * - */ -void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_Hz) -{ - uint32_t instance = I3C_GetInstance(base); - uint32_t configValue; - uint8_t matchCount; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate the clock. */ - CLOCK_EnableClock(kI3cClocks[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) - /* Reset the I3C module */ - RESET_PeripheralReset(kI3cResets[instance]); -#endif - - if ((config->masterDynamicAddress != 0U) && (config->enableMaster == kI3C_MasterOn)) - { - base->MDYNADDR &= ~I3C_MDYNADDR_DADDR_MASK; - base->MDYNADDR |= I3C_MDYNADDR_DADDR(config->masterDynamicAddress) | I3C_MDYNADDR_DAVALID_MASK; - } - - base->MCONFIG = I3C_MCONFIG_MSTENA(config->enableMaster) | I3C_MCONFIG_DISTO(config->disableTimeout) | - I3C_MCONFIG_HKEEP(config->hKeep) | I3C_MCONFIG_ODSTOP(config->enableOpenDrainStop) | - I3C_MCONFIG_ODHPP(config->enableOpenDrainHigh); - - I3C_MasterSetWatermarks(base, kI3C_TxTriggerUntilOneLessThanFull, kI3C_RxTriggerOnNotEmpty, true, true); - - I3C_MasterSetBaudRate(base, &config->baudRate_Hz, sourceClock_Hz); - - /* Caculate bus available condition match value for current slow clock, count value provides 1us.*/ - matchCount = (uint8_t)(config->slowClock_Hz / 1000000UL); - - configValue = base->SCONFIG; - - configValue &= ~(I3C_SCONFIG_SADDR_MASK | I3C_SCONFIG_BAMATCH_MASK | I3C_SCONFIG_OFFLINE_MASK | - I3C_SCONFIG_IDRAND_MASK | I3C_SCONFIG_DDROK_MASK | I3C_SCONFIG_S0IGNORE_MASK | - I3C_SCONFIG_MATCHSS_MASK | I3C_SCONFIG_NACK_MASK | I3C_SCONFIG_SLVENA_MASK); - configValue |= I3C_SCONFIG_SADDR(config->staticAddr) | I3C_SCONFIG_BAMATCH(matchCount) | - I3C_SCONFIG_OFFLINE(config->offline) | I3C_SCONFIG_IDRAND(config->enableRandomPart) | - I3C_SCONFIG_DDROK((0U != (config->hdrMode & (uint8_t)kI3C_HDRModeDDR)) ? 1U : 0U) | - I3C_SCONFIG_S0IGNORE(config->ignoreS0S1Error) | I3C_SCONFIG_MATCHSS(config->matchSlaveStartStop) | - I3C_SCONFIG_NACK(config->nakAllRequest) | I3C_SCONFIG_SLVENA(config->enableSlave); - - base->SVENDORID &= ~I3C_SVENDORID_VID_MASK; - base->SVENDORID |= I3C_SVENDORID_VID(config->vendorID); - - if (!config->enableRandomPart) - { - base->SIDPARTNO = config->partNumber; - } - - base->SIDEXT &= ~(I3C_SIDEXT_BCR_MASK | I3C_SIDEXT_DCR_MASK); - base->SIDEXT |= I3C_SIDEXT_BCR(config->bcr) | I3C_SIDEXT_DCR(config->dcr); - - base->SMAXLIMITS &= ~(I3C_SMAXLIMITS_MAXRD_MASK | I3C_SMAXLIMITS_MAXWR_MASK); - base->SMAXLIMITS |= (I3C_SMAXLIMITS_MAXRD(config->maxReadLength) | I3C_SMAXLIMITS_MAXWR(config->maxWriteLength)); - - base->SCONFIG = configValue; -} - -/*! - * brief Provides a default configuration for the I3C master peripheral. - * - * This function provides the following default configuration for the I3C master peripheral: - * code - * masterConfig->enableMaster = kI3C_MasterOn; - * masterConfig->disableTimeout = false; - * masterConfig->hKeep = kI3C_MasterHighKeeperNone; - * masterConfig->enableOpenDrainStop = true; - * masterConfig->enableOpenDrainHigh = true; - * masterConfig->baudRate_Hz = 100000U; - * masterConfig->busType = kI3C_TypeI2C; - * endcode - * - * After calling this function, you can override any settings in order to customize the configuration, - * prior to initializing the master driver with I3C_MasterInit(). - * - * param[out] masterConfig User provided configuration structure for default values. Refer to #i3c_master_config_t. - */ -void I3C_MasterGetDefaultConfig(i3c_master_config_t *masterConfig) -{ - masterConfig->enableMaster = kI3C_MasterOn; - masterConfig->disableTimeout = false; - masterConfig->hKeep = kI3C_MasterHighKeeperNone; - masterConfig->enableOpenDrainStop = true; - masterConfig->enableOpenDrainHigh = true; - masterConfig->baudRate_Hz.i2cBaud = 400000U; - masterConfig->baudRate_Hz.i3cPushPullBaud = 12500000U; - masterConfig->baudRate_Hz.i3cOpenDrainBaud = 2500000U; -} - -/*! - * brief Initializes the I3C master peripheral. - * - * This function enables the peripheral clock and initializes the I3C master peripheral as described by the user - * provided configuration. A software reset is performed prior to configuration. - * - * param base The I3C peripheral base address. - * param masterConfig User provided peripheral configuration. Use I3C_MasterGetDefaultConfig() to get a set of - * defaults that you can override. - * param sourceClock_Hz Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, - * filter widths, and timeout periods. - */ -void I3C_MasterInit(I3C_Type *base, const i3c_master_config_t *masterConfig, uint32_t sourceClock_Hz) -{ - uint32_t instance = I3C_GetInstance(base); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate the clock. */ - CLOCK_EnableClock(kI3cClocks[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) - /* Reset the I3C module */ - RESET_PeripheralReset(kI3cResets[instance]); -#endif - base->MCONFIG = I3C_MCONFIG_MSTENA(masterConfig->enableMaster) | I3C_MCONFIG_DISTO(masterConfig->disableTimeout) | - I3C_MCONFIG_HKEEP(masterConfig->hKeep) | I3C_MCONFIG_ODSTOP(masterConfig->enableOpenDrainStop) | - I3C_MCONFIG_ODHPP(masterConfig->enableOpenDrainHigh); - - I3C_MasterSetWatermarks(base, kI3C_TxTriggerUntilOneLessThanFull, kI3C_RxTriggerOnNotEmpty, true, true); - - I3C_MasterSetBaudRate(base, &masterConfig->baudRate_Hz, sourceClock_Hz); -} - -/*! - * @brief Gets the I3C master state. - * - * @param base The I3C peripheral base address. - * @return I3C master state. - */ -i3c_master_state_t I3C_MasterGetState(I3C_Type *base) -{ - uint32_t masterState = (base->MSTATUS & I3C_MSTATUS_STATE_MASK) >> I3C_MSTATUS_STATE_SHIFT; - i3c_master_state_t returnCode; - - switch (masterState) - { - case (uint32_t)kI3C_MasterStateIdle: - returnCode = kI3C_MasterStateIdle; - break; - case (uint32_t)kI3C_MasterStateSlvReq: - returnCode = kI3C_MasterStateSlvReq; - break; - case (uint32_t)kI3C_MasterStateMsgSdr: - returnCode = kI3C_MasterStateMsgSdr; - break; - case (uint32_t)kI3C_MasterStateNormAct: - returnCode = kI3C_MasterStateNormAct; - break; - case (uint32_t)kI3C_MasterStateDdr: - returnCode = kI3C_MasterStateDdr; - break; - case (uint32_t)kI3C_MasterStateDaa: - returnCode = kI3C_MasterStateDaa; - break; - case (uint32_t)kI3C_MasterStateIbiAck: - returnCode = kI3C_MasterStateIbiAck; - break; - case (uint32_t)kI3C_MasterStateIbiRcv: - returnCode = kI3C_MasterStateIbiRcv; - break; - default: - returnCode = kI3C_MasterStateIdle; - break; - } - - return returnCode; -} - -/*! - * brief Deinitializes the I3C master peripheral. - * - * This function disables the I3C master peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * param base The I3C peripheral base address. - */ -void I3C_MasterDeinit(I3C_Type *base) -{ - uint32_t idx = I3C_GetInstance(base); - -#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) - /* Reset the I3C module */ - RESET_PeripheralReset(kI3cResets[idx]); -#endif - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate clock. */ - CLOCK_DisableClock(kI3cClocks[idx]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset handle pointer. */ - s_i3cMasterHandle[idx] = NULL; -} - -static uint32_t I3C_CalcErrorRatio(uint32_t curFreq, uint32_t desiredFreq) -{ - if (curFreq > desiredFreq) - { - return (curFreq - desiredFreq) * 100UL / desiredFreq; - } - else - { - return (desiredFreq - curFreq) * 100UL / desiredFreq; - } -} - -/*! - * brief Sets the I3C bus frequency for master transactions. - * - * The I3C master is automatically disabled and re-enabled as necessary to configure the baud - * rate. Do not call this function during a transfer, or the transfer is aborted. - * - * param base The I3C peripheral base address. - * param baudRate_Hz Pointer to structure of requested bus frequency in Hertz. - * param sourceClock_Hz I3C functional clock frequency in Hertz. - */ -void I3C_MasterSetBaudRate(I3C_Type *base, const i3c_baudrate_hz_t *baudRate_Hz, uint32_t sourceClock_Hz) -{ - uint32_t div, freq; - uint32_t divEven, divOdd; - uint32_t ppBaud, odBaud, i2cBaud; - uint32_t errRate0, errRate1; - uint32_t i3cPPBaud_HZ = baudRate_Hz->i3cPushPullBaud; - uint32_t i3cPPBaudMax_HZ = i3cPPBaud_HZ / 10U + i3cPPBaud_HZ; /* max is 1.1*i3cPPBaud_HZ */ - uint32_t i3cODBaud_HZ = baudRate_Hz->i3cOpenDrainBaud; - uint32_t i3cODBaudMax_HZ = i3cODBaud_HZ / 10U + i3cODBaud_HZ; /* max is 1.1*i3cODBaud_HZ */ - uint32_t i2cBaud_HZ = baudRate_Hz->i2cBaud; - uint32_t i3cPPLow_Ns, i3cOdLow_Ns; - bool isODHigh = (0U != (base->MCONFIG & I3C_MCONFIG_ODHPP_MASK)) ? true : false; - - /* Find out the div to generate target freq */ - freq = sourceClock_Hz / 2UL; - /* ppFreq = FCLK / 2 / (PPBAUD + 1)), 0 <= PPBAUD <= 15 */ - /* We need PPBAUD generate 12.5MHz or so. */ - div = freq / i3cPPBaud_HZ; - div = (div == 0UL) ? 1UL : div; - if (freq / div > i3cPPBaudMax_HZ) - { - div++; - } - assert(div <= FSL_I3C_PPBAUD_DIV_MAX); - ppBaud = div - 1UL; - freq /= div; - - i3cPPLow_Ns = (uint32_t)(NSEC_PER_SEC / (2UL * freq)); - - /* We need ODBAUD generate 2.5MHz or so. */ - if (isODHigh) - { - /* odFreq = (2*freq) / (ODBAUD + 2), 1 <= ODBAUD <= 255 */ - div = (2UL * freq) / i3cODBaud_HZ; - div = div < 2UL ? 2UL : div; - if ((2UL * freq / div) > i3cODBaudMax_HZ) - { - div++; - } - odBaud = div - 2UL; - freq = (2UL * freq) / div; - } - else - { - /* odFreq = ppFreq / (ODBAUD + 1), 1 <= ODBAUD <= 255 */ - div = freq / i3cODBaud_HZ; - div = div < 1UL ? 1UL : div; - if (freq / div > i3cODBaudMax_HZ) - { - div++; - } - odBaud = div - 1UL; - freq /= div; - } - - i3cOdLow_Ns = (odBaud + 1UL) * i3cPPLow_Ns; - - /* i2cFreq = odFreq / (I2CBAUD + 1), 0 <= I2CBAUD <= 7 (I2CBAUD need << 1 in register) */ - /* i2cFreq = NSEC_PER_SEC / (I2CBAUD + 1)*i3cOdLow_Ns */ - divEven = (sourceClock_Hz / i2cBaud_HZ) / (2UL * (ppBaud + 1UL) * (odBaud + 1UL)); - divEven = divEven == 0UL ? 1UL : divEven; - errRate0 = I3C_CalcErrorRatio((uint32_t)(NSEC_PER_SEC / (2UL * divEven * i3cOdLow_Ns)), i2cBaud_HZ); - - divOdd = ((sourceClock_Hz / i2cBaud_HZ) / ((ppBaud + 1UL) * (odBaud + 1UL) - 1UL)) / 2UL; - divOdd = divOdd == 0UL ? 1UL : divOdd; - errRate1 = I3C_CalcErrorRatio((uint32_t)(NSEC_PER_SEC / ((2UL * divOdd + 1UL) * i3cOdLow_Ns)), i2cBaud_HZ); - - if (errRate0 < FSL_I3C_ERROR_RATE_MAX || errRate1 < FSL_I3C_ERROR_RATE_MAX) - { - /* Use this div */ - i2cBaud = errRate0 < errRate1 ? (divEven - 1UL) * 2UL : (divOdd - 1UL) * 2UL + 1UL; - } - else - { - /* Use div + 1, unless current freq is already lower than desired. */ - i2cBaud = freq / divEven < i2cBaud_HZ ? (divEven - 1UL) * 2UL : divEven * 2UL; - } - - base->MCONFIG = (base->MCONFIG & ~(I3C_MCONFIG_PPBAUD_MASK | I3C_MCONFIG_PPLOW_MASK | I3C_MCONFIG_ODBAUD_MASK | - I3C_MCONFIG_I2CBAUD_MASK)) | - I3C_MCONFIG_PPBAUD(ppBaud) | I3C_MCONFIG_ODBAUD(odBaud) | I3C_MCONFIG_I2CBAUD(i2cBaud); -} - -/*! - * brief Sends a START signal and slave address on the I2C/I3C bus. - * - * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure - * that another master is not occupying the bus. Then a START signal is transmitted, followed by the - * 7-bit address specified in the a address parameter. Note that this function does not actually wait - * until the START and address are successfully sent on the bus before returning. - * - * param base The I3C peripheral base address. - * param type The bus type to use in this transaction. - * param address 7-bit slave device address, in bits [6:0]. - * param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set - * the R/w bit (bit 0) in the transmitted slave address. - * retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. - * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. - */ -status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir) -{ - i3c_master_state_t masterState = I3C_MasterGetState(base); - bool checkDdrState = (type == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true; - if ((masterState != kI3C_MasterStateIdle) && (masterState != kI3C_MasterStateNormAct) && checkDdrState) - { - return kStatus_I3C_Busy; - } - - return I3C_MasterRepeatedStart(base, type, address, dir); -} - -/*! - * brief Sends a repeated START signal and slave address on the I2C/I3C bus. - * - * This function is used to send a Repeated START signal when a transfer is already in progress. Like - * I3C_MasterStart(), it also sends the specified 7-bit address. - * - * note This function exists primarily to maintain compatible APIs between I3C and I2C drivers, - * as well as to better document the intent of code that uses these APIs. - * - * param base The I3C peripheral base address. - * param type The bus type to use in this transaction. - * param address 7-bit slave device address, in bits [6:0]. - * param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set - * the R/w bit (bit 0) in the transmitted slave address. - * param rxSize if dir is #kI3C_Read, this assigns bytes to read. Otherwise set to 0. - * retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. - */ -status_t I3C_MasterRepeatedStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir) -{ - uint32_t mctrlVal; - - /* Clear all flags. */ - I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); - - /* Issue start command. */ - mctrlVal = base->MCTRL; - mctrlVal &= ~(I3C_MCTRL_TYPE_MASK | I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_ADDR_MASK | - I3C_MCTRL_RDTERM_MASK); - mctrlVal |= I3C_MCTRL_TYPE(type) | I3C_MCTRL_REQUEST(kI3C_RequestEmitStartAddr) | I3C_MCTRL_DIR(dir) | - I3C_MCTRL_ADDR(address); - - base->MCTRL = mctrlVal; - - return kStatus_Success; -} - -/*! - * brief Sends a repeated START signal and slave address on the I2C/I3C bus, receive size is also specified - * in the call. - * - * This function is used to send a Repeated START signal when a transfer is already in progress. Like - * I3C_MasterStart(), it also sends the specified 7-bit address. Call this API also configures the read - * terminate size for the following read transfer. For example, set the rxSize = 2, the following read transfer - * will be terminated after two bytes of data received. Write transfer will not be affected by the rxSize - * configuration. - * - * note This function exists primarily to maintain compatible APIs between I3C and I2C drivers, - * as well as to better document the intent of code that uses these APIs. - * - * param base The I3C peripheral base address. - * param type The bus type to use in this transaction. - * param address 7-bit slave device address, in bits [6:0]. - * param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set - * the R/w bit (bit 0) in the transmitted slave address. - * param rxSize Read terminate size for the followed read transfer, limit to 255 bytes. - * retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. - */ -status_t I3C_MasterRepeatedStartWithRxSize( - I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize) -{ - uint32_t mctrlVal; - - /* Clear all flags. */ - I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); - - /* Issue start command. */ - mctrlVal = base->MCTRL; - mctrlVal &= ~(I3C_MCTRL_TYPE_MASK | I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_ADDR_MASK | - I3C_MCTRL_RDTERM_MASK); - mctrlVal |= I3C_MCTRL_TYPE(type) | I3C_MCTRL_REQUEST(kI3C_RequestEmitStartAddr) | I3C_MCTRL_DIR(dir) | - I3C_MCTRL_ADDR(address) | I3C_MCTRL_RDTERM(rxSize); - - base->MCTRL = mctrlVal; - - return kStatus_Success; -} -/*! - * brief Sends a STOP signal on the I2C/I3C bus. - * - * This function does not return until the STOP signal is seen on the bus, or an error occurs. - * - * param base The I3C peripheral base address. - * retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. - * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. - * retval #kStatus_I3C_Nak The slave device sent a NAK in response to a byte. - * retval #kStatus_I3C_FifoError FIFO under run or overrun. - * retval #kStatus_I3C_ArbitrationLost Arbitration lost error. - * retval #kStatus_I3C_PinLowTimeout SCL or SDA were held low longer than the timeout. - */ -status_t I3C_MasterStop(I3C_Type *base) -{ - return I3C_MasterEmitStop(base, true); -} - -/*! - * brief I3C master emit request. - * - * param base The I3C peripheral base address. - * param masterReq I3C master request of type #i3c_bus_request_t - */ -void I3C_MasterEmitRequest(I3C_Type *base, i3c_bus_request_t masterReq) -{ - uint32_t mctrlReg = base->MCTRL; - mctrlReg &= ~I3C_MCTRL_REQUEST_MASK; - mctrlReg |= I3C_MCTRL_REQUEST(masterReq); - - base->MCTRL = mctrlReg; -} - -/*! - * brief I3C master register IBI rule. - * - * param base The I3C peripheral base address. - * param ibiRule Pointer to ibi rule description of type #i3c_register_ibi_addr_t - */ -void I3C_MasterRegisterIBI(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule) -{ - assert(NULL != ibiRule); - uint32_t ruleValue = I3C_MIBIRULES_MSB0_MASK; - - for (uint32_t count = 0; count < ARRAY_SIZE(ibiRule->address); count++) - { - ruleValue |= ((uint32_t)ibiRule->address[count]) << (count * I3C_MIBIRULES_ADDR1_SHIFT); - } - - ruleValue &= ~I3C_MIBIRULES_NOBYTE_MASK; - - if (!ibiRule->ibiHasPayload) - { - ruleValue |= I3C_MIBIRULES_NOBYTE_MASK; - } - - base->MIBIRULES = ruleValue; -} - -/*! - * brief I3C master get IBI rule. - * - * param base The I3C peripheral base address. - * param ibiRule Pointer to store the read out ibi rule description. - */ -void I3C_MasterGetIBIRules(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule) -{ - assert(NULL != ibiRule); - - uint32_t ruleValue = base->MIBIRULES; - - for (uint32_t count = 0; count < ARRAY_SIZE(ibiRule->address); count++) - { - ibiRule->address[count] = - (uint8_t)(ruleValue >> (count * I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK; - } - - ibiRule->ibiHasPayload = (0U == (ruleValue & I3C_MIBIRULES_NOBYTE_MASK)); -} - -/*! - * brief Performs a polling receive transfer on the I2C/I3C bus. - * - * param base The I3C peripheral base address. - * param rxBuff The pointer to the data to be transferred. - * param rxSize The length in bytes of the data to be transferred. - * param flags Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available options. - * retval #kStatus_Success Data was received successfully. - * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. - * retval #kStatus_I3C_Nak The slave device sent a NAK in response to a byte. - * retval #kStatus_I3C_FifoError FIFO under run or overrun. - * retval #kStatus_I3C_ArbitrationLost Arbitration lost error. - * retval #kStatus_I3C_PinLowTimeout SCL or SDA were held low longer than the timeout. - */ -status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags) -{ - status_t result = kStatus_Success; - uint32_t status; - bool completed = false; - uint8_t *buf; - - assert(NULL != rxBuff); - - /* Handle empty read. */ - if (rxSize == 0UL) - { - return kStatus_Success; - } - -#if I3C_RETRY_TIMES - uint32_t waitTimes = I3C_RETRY_TIMES; -#endif - - /* Receive data */ - buf = (uint8_t *)rxBuff; - - while ((rxSize != 0UL) || !completed) - { -#if I3C_RETRY_TIMES - if (--waitTimes == 0) - { - return kStatus_I3C_Timeout; - } -#endif - /* Check for errors. */ - result = I3C_MasterCheckAndClearError(base, I3C_MasterGetErrorStatusFlags(base)); - if (kStatus_Success != result) - { - return result; - } - - /* Check complete flag */ - if (!completed) - { - status = I3C_MasterGetStatusFlags(base) & (uint32_t)kI3C_MasterCompleteFlag; - if (0UL != status) - { - completed = true; - /* Clear complete flag */ - I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterCompleteFlag); - /* Send stop if needed */ - if ((flags & (uint32_t)kI3C_TransferNoStopFlag) == 0UL) - { - if (I3C_MasterGetState(base) == kI3C_MasterStateDdr) - { - I3C_MasterEmitRequest(base, kI3C_RequestForceExit); - } - else - { - result = I3C_MasterEmitStop(base, false); - } - if (kStatus_Success != result) - { - return result; - } - } - } - } - - /* Check RX data */ - if ((0UL != rxSize) && (0UL != (base->MDATACTRL & I3C_MDATACTRL_RXCOUNT_MASK))) - { - *buf++ = (uint8_t)(base->MRDATAB & I3C_MRDATAB_VALUE_MASK); - rxSize--; - if (rxSize == 1U) - { - base->MCTRL |= I3C_MCTRL_RDTERM(1U); - } - } - } - - /* Wait idle if stop is sent. */ - if ((flags & (uint32_t)kI3C_TransferNoStopFlag) == 0UL) - { -#if I3C_RETRY_TIMES - while ((I3C_MasterGetState(base) != kI3C_MasterStateIdle) && --waitTimes) -#else - while (I3C_MasterGetState(base) != kI3C_MasterStateIdle) -#endif - { - } - } - return result; -} - -/*! - * brief Performs a polling send transfer on the I2C/I3C bus. - * - * Sends up to a txSize number of bytes to the previously addressed slave device. The slave may - * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this - * function returns #kStatus_I3C_Nak. - * - * param base The I3C peripheral base address. - * param txBuff The pointer to the data to be transferred. - * param txSize The length in bytes of the data to be transferred. - * param flags Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available options. - * retval #kStatus_Success Data was sent successfully. - * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. - * retval #kStatus_I3C_Nak The slave device sent a NAK in response to a byte. - * retval #kStatus_I3C_FifoError FIFO under run or over run. - * retval #kStatus_I3C_ArbitrationLost Arbitration lost error. - * retval #kStatus_I3C_PinLowTimeout SCL or SDA were held low longer than the timeout. - */ -status_t I3C_MasterSend(I3C_Type *base, const void *txBuff, size_t txSize, uint32_t flags) -{ - i3c_puint8_to_u32_t buf; - buf.cpuint8 = (const uint8_t *)((const void *)txBuff); - status_t result = kStatus_Success; - bool enableWord = ((flags & (uint32_t)kI3C_TransferWordsFlag) == (uint32_t)kI3C_TransferWordsFlag) ? true : false; - uint8_t byteCounts = enableWord ? 2U : 1U; - - assert(NULL != txBuff); - if (enableWord) - { - assert(txSize % 2UL == 0UL); - } - - /* Send data buffer */ - while (0UL != txSize) - { - /* Wait until there is room in the fifo. This also checks for errors. */ - result = I3C_MasterWaitForTxReady(base, byteCounts); - if (kStatus_Success != result) - { - return result; - } - - /* Write byte into I3C master data register. */ - if (txSize > byteCounts) - { - if (enableWord) - { - base->MWDATAH = (uint32_t)buf.cpuint8[1] << 8UL | (uint32_t)buf.cpuint8[0]; - } - else - { - base->MWDATAB = *buf.cpuint8; - } - } - else - { - if (enableWord) - { - base->MWDATAHE = (uint32_t)buf.cpuint8[1] << 8UL | (uint32_t)buf.cpuint8[0]; - } - else - { - base->MWDATABE = *buf.cpuint8; - } - } - - buf.u32 = buf.u32 + byteCounts; - txSize = txSize - byteCounts; - } - - result = I3C_MasterWaitForComplete(base, false); - if ((result == kStatus_Success) && ((flags & (uint32_t)kI3C_TransferNoStopFlag) == 0UL)) - { - if (I3C_MasterGetState(base) == kI3C_MasterStateDdr) - { - I3C_MasterEmitRequest(base, kI3C_RequestForceExit); - } - else - { - result = I3C_MasterEmitStop(base, true); - } - } - - return result; -} -/*! - * brief Performs a DAA in the i3c bus - * - * param base The I3C peripheral base address. - * param addressList The pointer for address list which is used to do DAA. - * param count The address count in the address list. - * retval #kStatus_Success The transaction was started successfully. - * retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking - * transaction is already in progress. - */ -status_t I3C_MasterProcessDAA(I3C_Type *base, uint8_t *addressList, uint32_t count) -{ - status_t result = kStatus_Success; - uint32_t status; - uint32_t errStatus; - size_t rxCount; - uint8_t rxBuffer[8] = {0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU}; - uint8_t rxSize = 0; - uint32_t devCount = 0; - - /* Return an error if the bus is already in use not by us. */ - result = I3C_CheckForBusyBus(base); - if (kStatus_Success != result) - { - return result; - } - - /* Clear all flags. */ - I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); - I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); - - /* Disable I3C IRQ sources while we configure stuff. */ - uint32_t enabledInts = I3C_MasterGetEnabledInterrupts(base); - I3C_MasterDisableInterrupts(base, enabledInts); - - /* Emit process DAA */ - I3C_MasterEmitRequest(base, kI3C_RequestProcessDAA); - - do - { - do - { - status = I3C_MasterGetStatusFlags(base); - I3C_MasterGetFifoCounts(base, &rxCount, NULL); - - /* Check for error flags. */ - errStatus = I3C_MasterGetErrorStatusFlags(base); - result = I3C_MasterCheckAndClearError(base, errStatus); - if (kStatus_Success != result) - { - return result; - } - - if ((0UL != (status & (uint32_t)kI3C_MasterRxReadyFlag)) && (rxCount != 0U)) - { - rxBuffer[rxSize++] = (uint8_t)(base->MRDATAB & I3C_MRDATAB_VALUE_MASK); - } - } while ((status & (uint32_t)kI3C_MasterControlDoneFlag) != (uint32_t)kI3C_MasterControlDoneFlag); - - I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterControlDoneFlag); - - if ((I3C_MasterGetState(base) == kI3C_MasterStateDaa) && - (0UL != (I3C_MasterGetStatusFlags(base) & (uint32_t)kI3C_MasterBetweenFlag))) - { - rxSize = 0; - if ((devCount > (count - 1UL)) || ((devCount + 1UL) > I3C_MAX_DEVCNT)) - { - return kStatus_I3C_SlaveCountExceed; - } - - devList[devCount].dynamicAddr = *addressList++; - devList[devCount].vendorID = (((uint16_t)rxBuffer[0] << 8U | (uint16_t)rxBuffer[1]) & 0xFFFEU) >> 1U; - devList[devCount].partNumber = ((uint32_t)rxBuffer[2] << 24U | (uint32_t)rxBuffer[3] << 16U | - (uint32_t)rxBuffer[4] << 8U | (uint32_t)rxBuffer[5]); - devList[devCount].bcr = rxBuffer[6]; - devList[devCount].dcr = rxBuffer[7]; - base->MWDATAB = devList[devCount].dynamicAddr; - /* Emit process DAA again. */ - I3C_MasterEmitRequest(base, kI3C_RequestProcessDAA); - devCount++; - } - } while ((status & (uint32_t)kI3C_MasterCompleteFlag) != (uint32_t)kI3C_MasterCompleteFlag); - - I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); - /* Clear all flags. */ - I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); - - /* Enable I3C IRQ sources while we configure stuff. */ - I3C_MasterEnableInterrupts(base, enabledInts); - - return result; -} - -/*! - * brief Performs a master polling transfer on the I2C/I3C bus. - * - * note The API does not return until the transfer succeeds or fails due - * to error happens during transfer. - * - * param base The I3C peripheral base address. - * param transfer Pointer to the transfer structure. - * retval #kStatus_Success Data was received successfully. - * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. - * retval #kStatus_I3C_Nak The slave device sent a NAK in response to a byte. - * retval #kStatus_I3C_FifoError FIFO under run or overrun. - * retval #kStatus_I3C_ArbitrationLost Arbitration lost error. - * retval #kStatus_I3C_PinLowTimeout SCL or SDA were held low longer than the timeout. - */ -status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *transfer) -{ - assert(NULL != transfer); - assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); - - status_t result = kStatus_Success; - i3c_direction_t direction = transfer->direction; - i3c_master_state_t masterState = I3C_MasterGetState(base); - bool checkDdrState = false; - - /* Return an error if the bus is already in use not by us. */ - checkDdrState = (transfer->busType == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true; - - if ((masterState != kI3C_MasterStateIdle) && (masterState != kI3C_MasterStateNormAct) && checkDdrState) - { - return kStatus_I3C_Busy; - } - - /* Clear all flags. */ - I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); - /* Reset fifos. These flags clear automatically. */ - base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; - - /* Disable I3C IRQ sources while we configure stuff. */ - I3C_MasterDisableInterrupts(base, (uint32_t)kMasterIrqFlags); - - if (transfer->busType != kI3C_TypeI3CDdr) - { - direction = (0UL != transfer->subaddressSize) ? kI3C_Write : transfer->direction; - } - - if (0UL == (transfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) - { - result = I3C_MasterStart(base, transfer->busType, transfer->slaveAddress, direction); - /* Wait tx fifo empty. */ - size_t txCount = 0xFFUL; - - while (txCount != 0U) - { - I3C_MasterGetFifoCounts(base, NULL, &txCount); - } - - /* Check if device request wins arbitration. */ - if (0UL != (I3C_MasterGetStatusFlags(base) & (uint32_t)kI3C_MasterArbitrationWonFlag)) - { - /* Clear all flags. */ - I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); - /* Enable I3C IRQ sources. */ - I3C_MasterEnableInterrupts(base, (uint32_t)kMasterIrqFlags); - return kStatus_I3C_IBIWon; - } - } - - /* Subaddress, MSB first. */ - if (0U != transfer->subaddressSize) - { - uint32_t subaddressRemaining = transfer->subaddressSize; - while (0UL != subaddressRemaining--) - { - uint8_t subaddressByte = (uint8_t)((transfer->subaddress >> (8UL * subaddressRemaining)) & 0xFFUL); - - result = I3C_MasterWaitForTxReady(base, 1U); - - if ((0UL == subaddressRemaining) && ((transfer->direction == kI3C_Read) || (0UL == transfer->dataSize)) && - (transfer->busType != kI3C_TypeI3CDdr)) - { - base->MWDATABE = subaddressByte; - result = I3C_MasterWaitForComplete(base, false); - if (kStatus_Success != result) - { - if (result == kStatus_I3C_Nak) - { - (void)I3C_MasterEmitStop(base, true); - } - /* Clear all flags. */ - I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); - /* Enable I3C IRQ sources. */ - I3C_MasterEnableInterrupts(base, (uint32_t)kMasterIrqFlags); - return result; - } - } - else - { - base->MWDATAB = subaddressByte; - } - } - /* Need to send repeated start if switching directions to read. */ - if ((transfer->busType != kI3C_TypeI3CDdr) && (0UL != transfer->dataSize) && (transfer->direction == kI3C_Read)) - { - result = I3C_MasterRepeatedStart(base, transfer->busType, transfer->slaveAddress, kI3C_Read); - if (kStatus_Success != result) - { - /* Clear all flags. */ - I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); - /* Enable I3C IRQ sources. */ - I3C_MasterEnableInterrupts(base, (uint32_t)kMasterIrqFlags); - return result; - } - } - } - - /* Transmit data. */ - if ((transfer->direction == kI3C_Write) && (transfer->dataSize > 0UL)) - { - /* Send Data. */ - result = I3C_MasterSend(base, transfer->data, transfer->dataSize, transfer->flags); - } - /* Receive Data. */ - else if ((transfer->direction == kI3C_Read) && (transfer->dataSize > 0UL)) - { - if (transfer->dataSize == 1U) - { - base->MCTRL |= I3C_MCTRL_RDTERM(1U); - } - result = I3C_MasterReceive(base, transfer->data, transfer->dataSize, transfer->flags); - } - else - { - if ((transfer->flags & (uint32_t)kI3C_TransferNoStopFlag) == 0UL) - { - result = I3C_MasterEmitStop(base, true); - } - } - - /* Clear all flags. */ - I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); - /* Enable I3C IRQ sources. */ - I3C_MasterEnableInterrupts(base, (uint32_t)kMasterIrqFlags); - - return result; -} - -/*! - * brief Creates a new handle for the I3C master non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I3C_MasterTransferAbort() API shall be called. - * - * - * note The function also enables the NVIC IRQ for the input I3C. Need to notice - * that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to - * enable the associated INTMUX IRQ in application. - * - * param base The I3C peripheral base address. - * param[out] handle Pointer to the I3C master driver handle. - * param callback User provided pointer to the asynchronous callback function. - * param userData User provided pointer to the application callback data. - */ -void I3C_MasterTransferCreateHandle(I3C_Type *base, - i3c_master_handle_t *handle, - const i3c_master_transfer_callback_t *callback, - void *userData) -{ - uint32_t instance; - - assert(NULL != handle); - - /* Clear out the handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I3C_GetInstance(base); - - /* Save base and instance. */ - handle->callback = *callback; - handle->userData = userData; - - /* Save this handle for IRQ use. */ - s_i3cMasterHandle[instance] = handle; - - /* Set irq handler. */ - s_i3cMasterIsr = I3C_MasterTransferHandleIRQ; - - /* Clear all flags. */ - I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); - I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); - /* Reset fifos. These flags clear automatically. */ - base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; - - /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC. - In some cases the I3C IRQ is configured through INTMUX, user needs to enable - INTMUX IRQ in application code. */ - (void)EnableIRQ(kI3cIrqs[instance]); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I3C_MasterEnableInterrupts(base, (uint32_t)kMasterIrqFlags); -} - -static status_t I3C_RunTransferStateMachine(I3C_Type *base, i3c_master_handle_t *handle, bool *isDone) -{ - uint32_t status; - uint32_t errStatus; - status_t result = kStatus_Success; - i3c_master_transfer_t *xfer; - size_t txCount; - size_t rxCount; - size_t txFifoSize = - 2UL << ((base->SCAPABILITIES & I3C_SCAPABILITIES_FIFOTX_MASK) >> I3C_SCAPABILITIES_FIFOTX_SHIFT); - bool state_complete = false; - i3c_puint8_to_u32_t dataBuff; - - /* Set default isDone return value. */ - *isDone = false; - - /* Check for errors. */ - status = (uint32_t)I3C_MasterGetPendingInterrupts(base); - I3C_MasterClearStatusFlags(base, status); - - i3c_master_state_t masterState = I3C_MasterGetState(base); - errStatus = I3C_MasterGetErrorStatusFlags(base); - result = I3C_MasterCheckAndClearError(base, errStatus); - if (kStatus_Success != result) - { - return result; - } - - if (0UL != (status & (uint32_t)kI3C_MasterSlave2MasterFlag)) - { - if (handle->callback.slave2Master != NULL) - { - handle->callback.slave2Master(base, handle->userData); - } - } - - if ((0UL != (status & (uint32_t)kI3C_MasterSlaveStartFlag)) && (handle->transfer.busType != kI3C_TypeI2C)) - { - handle->state = (uint8_t)kSlaveStartState; - } - - if ((masterState == kI3C_MasterStateIbiRcv) || (masterState == kI3C_MasterStateIbiAck)) - { - handle->state = (uint8_t)kIBIWonState; - } - - if (handle->state == (uint8_t)kIdleState) - { - return result; - } - - /* Get pointer to private data. */ - xfer = &handle->transfer; - - /* Get fifo counts and compute room in tx fifo. */ - I3C_MasterGetFifoCounts(base, &rxCount, &txCount); - txCount = txFifoSize - txCount; - - while (!state_complete) - { - /* Execute the state. */ - switch (handle->state) - { - case (uint8_t)kSlaveStartState: - /* Emit start + 0x7E */ - I3C_MasterEmitRequest(base, kI3C_RequestAutoIbi); - handle->state = (uint8_t)kIBIWonState; - state_complete = true; - break; - - case (uint8_t)kIBIWonState: - if (masterState == kI3C_MasterStateIbiAck) - { - handle->ibiType = I3C_GetIBIType(base); - if (handle->callback.ibiCallback != NULL) - { - handle->callback.ibiCallback(base, handle, handle->ibiType, kI3C_IbiAckNackPending); - } - else - { - I3C_MasterEmitIBIResponse(base, kI3C_IbiRespNack); - } - } - - /* Make sure there is data in the rx fifo. */ - if (0UL != rxCount) - { - if ((handle->ibiBuff == NULL) && (handle->callback.ibiCallback != NULL)) - { - handle->callback.ibiCallback(base, handle, kI3C_IbiNormal, kI3C_IbiDataBuffNeed); - } - uint8_t tempData = (uint8_t)base->MRDATAB; - if (handle->ibiBuff != NULL) - { - handle->ibiBuff[handle->ibiPayloadSize++] = tempData; - } - rxCount--; - break; - } - else if (0UL != (status & (uint32_t)kI3C_MasterCompleteFlag)) - { - handle->ibiType = I3C_GetIBIType(base); - handle->ibiAddress = I3C_GetIBIAddress(base); - state_complete = true; - result = kStatus_I3C_IBIWon; - } - else - { - state_complete = true; - } - break; - - case (uint8_t)kSendCommandState: - { - I3C_MasterEnableInterrupts(base, (uint32_t)kI3C_MasterTxReadyFlag); - /* Make sure there is room in the tx fifo for the next command. */ - if (0UL == txCount--) - { - state_complete = true; - break; - } - if (xfer->subaddressSize > 1U) - { - xfer->subaddressSize--; - base->MWDATAB = (uint8_t)((xfer->subaddress) >> (8U * xfer->subaddressSize)); - } - else if (xfer->subaddressSize == 1U) - { - xfer->subaddressSize--; - - if ((xfer->direction == kI3C_Read) || (0UL == xfer->dataSize)) - { - base->MWDATABE = (uint8_t)((xfer->subaddress) >> (8U * xfer->subaddressSize)); - handle->state = (uint8_t)kWaitForCompletionState; - } - else - { - /* Next state, receive data begin. */ - handle->state = (uint8_t)kTransferDataState; - base->MWDATAB = (uint8_t)((xfer->subaddress) >> (8U * xfer->subaddressSize)); - } - - if ((xfer->busType != kI3C_TypeI3CDdr) && (xfer->direction == kI3C_Read)) - { - handle->state = (uint8_t)kWaitRepeatedStartCompleteState; - } - } - else - { - /* Eliminate misra 15.7*/ - } - break; - } - - case (uint8_t)kWaitRepeatedStartCompleteState: - /* We stay in this state until the master complete. */ - if (0UL != (status & (uint32_t)kI3C_MasterCompleteFlag)) - { - handle->state = (uint8_t)kTransferDataState; - I3C_MasterDisableInterrupts(base, (uint32_t)kI3C_MasterTxReadyFlag); - - if (handle->remainingBytes < 256U) - { - handle->isReadTerm = true; - result = I3C_MasterRepeatedStartWithRxSize(base, xfer->busType, xfer->slaveAddress, kI3C_Read, - (uint8_t)handle->remainingBytes); - } - else - { - result = I3C_MasterRepeatedStart(base, xfer->busType, xfer->slaveAddress, kI3C_Read); - } - } - - state_complete = true; - break; - - case (uint8_t)kTransferDataState: - - if (xfer->direction == kI3C_Write) - { - /* Make sure there is room in the tx fifo. */ - if (0UL == txCount--) - { - state_complete = true; - break; - } - - /* Put byte to send in fifo. */ - dataBuff.puint8 = (uint8_t *)xfer->data; - if (xfer->dataSize > 1U) - { - base->MWDATAB = *dataBuff.puint8; - } - else - { - base->MWDATABE = *dataBuff.puint8; - } - dataBuff.u32 = dataBuff.u32 + 1U; - xfer->dataSize--; - xfer->data = (void *)(dataBuff.puint8); - - /* Move to stop when the transfer is done. */ - if (--handle->remainingBytes == 0UL) - { - handle->state = (uint8_t)kWaitForCompletionState; - } - } - else - { - /* Make sure there is data in the rx fifo. */ - if (0UL == rxCount--) - { - state_complete = true; - break; - } - - /* Read byte from fifo. */ - dataBuff.puint8 = (uint8_t *)xfer->data; - *dataBuff.puint8 = (uint8_t)base->MRDATAB; - dataBuff.u32 = dataBuff.u32 + 1U; - xfer->data = (void *)(dataBuff.puint8); - - /* Move to stop when the transfer is done. */ - if (--handle->remainingBytes == 0UL) - { - handle->isReadTerm = false; - handle->state = (uint8_t)kWaitForCompletionState; - } - - if (!handle->isReadTerm && (handle->remainingBytes == 1UL)) - { - base->MCTRL |= I3C_MCTRL_RDTERM(1UL); - } - } - - break; - - case (uint8_t)kWaitForCompletionState: - /* We stay in this state until the maste complete. */ - if (0UL != (status & (uint32_t)kI3C_MasterCompleteFlag)) - { - handle->state = (uint8_t)kStopState; - } - else - { - state_complete = true; - } - - break; - - case (uint8_t)kStopState: - /* Only issue a stop transition if the caller requested it. */ - if (0UL == (xfer->flags & (uint32_t)kI3C_TransferNoStopFlag)) - { - /* Make sure there is room in the tx fifo for the stop command. */ - if (0UL == txCount--) - { - state_complete = true; - break; - } - if (xfer->busType == kI3C_TypeI3CDdr) - { - I3C_MasterEmitRequest(base, kI3C_RequestForceExit); - } - else - { - (void)I3C_MasterEmitStop(base, false); - } - } - *isDone = true; - state_complete = true; - break; - - default: - assert(false); - break; - } - } - return result; -} - -static status_t I3C_InitTransferStateMachine(I3C_Type *base, i3c_master_handle_t *handle) -{ - i3c_master_transfer_t *xfer = &handle->transfer; - status_t result = kStatus_Success; - i3c_direction_t direction = xfer->direction; - - if (xfer->busType != kI3C_TypeI3CDdr) - { - direction = (0UL != xfer->subaddressSize) ? kI3C_Write : xfer->direction; - } - - /* Handle no start option. */ - if (0U != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) - { - /* No need to send start flag, directly go to send command or data */ - if (xfer->subaddressSize > 0UL) - { - handle->state = (uint8_t)kSendCommandState; - } - else - { - if (direction == kI3C_Write) - { - /* Next state, send data. */ - handle->state = (uint8_t)kTransferDataState; - } - else - { - /* Only support write with no stop signal. */ - return kStatus_InvalidArgument; - } - } - I3C_MasterTransferHandleIRQ(base, handle); - return result; - } - /* If repeated start is requested, send repeated start. */ - else if (0U != (xfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag)) - { - result = I3C_MasterRepeatedStart(base, xfer->busType, xfer->slaveAddress, direction); - } - else /* For normal transfer, send start. */ - { - result = I3C_MasterStart(base, xfer->busType, xfer->slaveAddress, direction); - } - - if (xfer->subaddressSize > 0U) - { - handle->state = (uint8_t)kSendCommandState; - } - else - { - handle->state = (uint8_t)kTransferDataState; - } - - if ((handle->remainingBytes < 256U) && (direction == kI3C_Read)) - { - handle->isReadTerm = true; - base->MCTRL |= I3C_MCTRL_RDTERM(handle->remainingBytes); - } - - return result; -} - -/*! - * brief Performs a non-blocking transaction on the I2C/I3C bus. - * - * param base The I3C peripheral base address. - * param handle Pointer to the I3C master driver handle. - * param transfer The pointer to the transfer descriptor. - * retval #kStatus_Success The transaction was started successfully. - * retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking - * transaction is already in progress. - */ -status_t I3C_MasterTransferNonBlocking(I3C_Type *base, i3c_master_handle_t *handle, i3c_master_transfer_t *transfer) -{ - assert(NULL != handle); - assert(NULL != transfer); - assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); - i3c_master_state_t masterState = I3C_MasterGetState(base); - bool checkDdrState = false; - - /* Return busy if another transaction is in progress. */ - if (handle->state != (uint8_t)kIdleState) - { - return kStatus_I3C_Busy; - } - - /* Return an error if the bus is already in use not by us. */ - checkDdrState = (transfer->busType == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true; - if ((masterState != kI3C_MasterStateIdle) && (masterState != kI3C_MasterStateNormAct) && checkDdrState) - { - return kStatus_I3C_Busy; - } - - /* Disable I3C IRQ sources while we configure stuff. */ - I3C_MasterDisableInterrupts(base, (uint32_t)kMasterIrqFlags); - - /* Save transfer into handle. */ - handle->transfer = *transfer; - handle->remainingBytes = transfer->dataSize; - - /* Configure IBI response type. */ - base->MCTRL &= ~I3C_MCTRL_IBIRESP_MASK; - base->MCTRL |= I3C_MCTRL_IBIRESP(transfer->ibiResponse); - - /* Clear all flags. */ - I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); - I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); - /* Reset fifos. These flags clear automatically. */ - base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; - - /* Generate commands to send. */ - (void)I3C_InitTransferStateMachine(base, handle); - - /* Enable I3C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ - I3C_MasterEnableInterrupts(base, (uint32_t)kMasterIrqFlags); - - if (transfer->direction == kI3C_Write) - { - I3C_MasterEnableInterrupts(base, (uint32_t)kI3C_MasterTxReadyFlag); - } - - return kStatus_Success; -} - -/*! - * brief Returns number of bytes transferred so far. - * param base The I3C peripheral base address. - * param handle Pointer to the I3C master driver handle. - * param[out] count Number of bytes transferred so far by the non-blocking transaction. - * retval #kStatus_Success - * retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. - */ -status_t I3C_MasterTransferGetCount(I3C_Type *base, i3c_master_handle_t *handle, size_t *count) -{ - assert(NULL != handle); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state == (uint8_t)kIdleState) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - uint8_t state; - uint32_t remainingBytes; - uint32_t dataSize; - - /* Cache some fields with IRQs disabled. This ensures all field values */ - /* are synchronized with each other during an ongoing transfer. */ - uint32_t irqs = I3C_MasterGetEnabledInterrupts(base); - I3C_MasterDisableInterrupts(base, irqs); - state = handle->state; - remainingBytes = handle->remainingBytes; - dataSize = handle->transfer.dataSize; - I3C_MasterEnableInterrupts(base, irqs); - - /* Get transfer count based on current transfer state. */ - switch (state) - { - case (uint8_t)kIdleState: - case (uint8_t)kSendCommandState: - *count = 0; - break; - - case (uint8_t)kTransferDataState: - *count = dataSize - remainingBytes; - break; - - case (uint8_t)kStopState: - case (uint8_t)kWaitForCompletionState: - default: - *count = dataSize; - break; - } - - return kStatus_Success; -} - -/*! - * brief Terminates a non-blocking I3C master transmission early. - * - * note It is not safe to call this function from an IRQ handler that has a higher priority than the - * I3C peripheral's IRQ priority. - * - * param base The I3C peripheral base address. - * param handle Pointer to the I3C master driver handle. - * retval #kStatus_Success A transaction was successfully aborted. - * retval #kStatus_I3C_Idle There is not a non-blocking transaction currently in progress. - */ -void I3C_MasterTransferAbort(I3C_Type *base, i3c_master_handle_t *handle) -{ - if (handle->state != (uint8_t)kIdleState) - { - /* Disable internal IRQ enables. */ - I3C_MasterDisableInterrupts(base, (uint32_t)kMasterIrqFlags); - - /* Reset fifos. These flags clear automatically. */ - base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; - - /* Send a stop command to finalize the transfer. */ - (void)I3C_MasterStop(base); - - /* Reset handle. */ - handle->state = (uint8_t)kIdleState; - } -} - -/*! - * brief Reusable routine to handle master interrupts. - * note This function does not need to be called unless you are reimplementing the - * nonblocking API's interrupt handler routines to add special functionality. - * param base The I3C peripheral base address. - * param handle Pointer to the I3C master driver handle. - */ -void I3C_MasterTransferHandleIRQ(I3C_Type *base, i3c_master_handle_t *handle) -{ - bool isDone; - status_t result; - - /* Don't do anything if we don't have a valid handle. */ - if (NULL == handle) - { - return; - } - - result = I3C_RunTransferStateMachine(base, handle, &isDone); - - if (handle->state == (uint8_t)kIdleState) - { - I3C_MasterDisableInterrupts(base, (uint32_t)kI3C_MasterTxReadyFlag); - return; - } - - if (isDone || (result != kStatus_Success)) - { - /* XXX need to handle data that may be in rx fifo below watermark level? */ - - /* XXX handle error, terminate xfer */ - if ((result == kStatus_I3C_Nak) || (result == kStatus_I3C_IBIWon)) - { - (void)I3C_MasterEmitStop(base, false); - } - - /* Disable internal IRQ enables. */ - I3C_MasterDisableInterrupts(base, (uint32_t)kI3C_MasterTxReadyFlag); - - /* Set handle to idle state. */ - handle->state = (uint8_t)kIdleState; - - /* Invoke IBI user callback. */ - if ((result == kStatus_I3C_IBIWon) && (handle->callback.ibiCallback != NULL)) - { - handle->callback.ibiCallback(base, handle, handle->ibiType, kI3C_IbiReady); - handle->ibiPayloadSize = 0; - } - - /* Invoke callback. */ - if (NULL != handle->callback.transferComplete) - { - handle->callback.transferComplete(base, handle, result, handle->userData); - } - } -} - -/*! - * brief Provides a default configuration for the I3C slave peripheral. - * - * This function provides the following default configuration for the I3C slave peripheral: - * code - * slaveConfig->enableslave = true; - * endcode - * - * After calling this function, you can override any settings in order to customize the configuration, - * prior to initializing the slave driver with I3C_SlaveInit(). - * - * param[out] slaveConfig User provided configuration structure for default values. Refer to #i3c_slave_config_t. - */ -void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig) -{ - assert(NULL != slaveConfig); - - (void)memset(slaveConfig, 0, sizeof(*slaveConfig)); - - slaveConfig->enableSlave = true; - slaveConfig->isHotJoin = false; - slaveConfig->vendorID = 0x11BU; - slaveConfig->enableRandomPart = false; - slaveConfig->partNumber = 0; - slaveConfig->dcr = 0; /* Generic device. */ - slaveConfig->bcr = - 0; /* BCR[7:6]: device role, I3C slave(2b'00), BCR[5]: SDR Only / SDR and HDR Capable, SDR and HDR - Capable(1b'1), BCR[4]: Bridge Identifier, Not a bridge device(1b'0), BCR[3]: Offline Capable, device is - offline capable(1b'1), BCR[2]: IBI Payload, No data byte following(1b'0), BCR[1]: IBI Request Capable, - capable(1b'1), BCR[0]: Max Data Speed Limitation, has limitation(1b'1). */ - slaveConfig->hdrMode = (uint8_t)kI3C_HDRModeDDR; - slaveConfig->nakAllRequest = false; - slaveConfig->ignoreS0S1Error = true; - slaveConfig->offline = false; - slaveConfig->matchSlaveStartStop = false; - slaveConfig->maxWriteLength = 256U; - slaveConfig->maxReadLength = 256U; -} - -/*! - * brief Initializes the I3C slave peripheral. - * - * This function enables the peripheral clock and initializes the I3C slave peripheral as described by the user - * provided configuration. - * - * param base The I3C peripheral base address. - * param slaveConfig User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of - * defaults that you can override. - * param slowClock_Hz Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values. - */ -void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz) -{ - assert(NULL != slaveConfig); - assert(0UL != slowClock_Hz); - - uint32_t configValue = base->SCONFIG; - uint8_t matchCount; - uint32_t instance = I3C_GetInstance(base); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate the clock. */ - CLOCK_EnableClock(kI3cClocks[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) - /* Reset the I3C module */ - RESET_PeripheralReset(kI3cResets[instance]); -#endif - - /* Caculate bus available condition match value for current slow clock, count value provides 1us.*/ - matchCount = (uint8_t)(slowClock_Hz / 1000000UL); - - configValue &= ~(I3C_SCONFIG_SADDR_MASK | I3C_SCONFIG_BAMATCH_MASK | I3C_SCONFIG_OFFLINE_MASK | - I3C_SCONFIG_IDRAND_MASK | I3C_SCONFIG_DDROK_MASK | I3C_SCONFIG_S0IGNORE_MASK | - I3C_SCONFIG_MATCHSS_MASK | I3C_SCONFIG_NACK_MASK | I3C_SCONFIG_SLVENA_MASK); - configValue |= I3C_SCONFIG_SADDR(slaveConfig->staticAddr) | I3C_SCONFIG_BAMATCH(matchCount) | - I3C_SCONFIG_OFFLINE(slaveConfig->offline) | I3C_SCONFIG_IDRAND(slaveConfig->enableRandomPart) | - I3C_SCONFIG_DDROK((0U != (slaveConfig->hdrMode & (uint8_t)kI3C_HDRModeDDR)) ? 1U : 0U) | - I3C_SCONFIG_S0IGNORE(slaveConfig->ignoreS0S1Error) | - I3C_SCONFIG_MATCHSS(slaveConfig->matchSlaveStartStop) | - I3C_SCONFIG_NACK(slaveConfig->nakAllRequest) | I3C_SCONFIG_SLVENA(slaveConfig->enableSlave); - - base->SVENDORID &= ~I3C_SVENDORID_VID_MASK; - base->SVENDORID |= I3C_SVENDORID_VID(slaveConfig->vendorID); - - if (!slaveConfig->enableRandomPart) - { - base->SIDPARTNO = slaveConfig->partNumber; - } - - base->SIDEXT &= ~(I3C_SIDEXT_BCR_MASK | I3C_SIDEXT_DCR_MASK); - base->SIDEXT |= I3C_SIDEXT_BCR(slaveConfig->bcr) | I3C_SIDEXT_DCR(slaveConfig->dcr); - - base->SMAXLIMITS &= ~(I3C_SMAXLIMITS_MAXRD_MASK | I3C_SMAXLIMITS_MAXWR_MASK); - base->SMAXLIMITS |= - (I3C_SMAXLIMITS_MAXRD(slaveConfig->maxReadLength) | I3C_SMAXLIMITS_MAXWR(slaveConfig->maxWriteLength)); - - if (slaveConfig->isHotJoin) - { - I3C_SlaveRequestEvent(base, kI3C_SlaveEventHotJoinReq); - } - base->SCONFIG = configValue; -} - -/*! - * brief Deinitializes the I3C master peripheral. - * - * This function disables the I3C master peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * param base The I3C peripheral base address. - */ -void I3C_SlaveDeinit(I3C_Type *base) -{ - uint32_t idx = I3C_GetInstance(base); - -#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) - /* Reset the I3C module */ - RESET_PeripheralReset(kI3cResets[idx]); -#endif - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate clock. */ - CLOCK_DisableClock(kI3cClocks[idx]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset handle pointer */ - s_i3cSlaveHandle[idx] = NULL; -} - -/*! - * @brief Gets the I3C slave state. - * - * @param base The I3C peripheral base address. - * @return I3C slave activity state, refer #i3c_slave_activity_state_t. - */ -i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base) -{ - uint8_t activeState = (uint8_t)((base->SSTATUS & I3C_SSTATUS_ACTSTATE_MASK) >> I3C_SSTATUS_ACTSTATE_SHIFT); - i3c_slave_activity_state_t returnCode; - switch (activeState) - { - case (uint8_t)kI3C_SlaveNoLatency: - returnCode = kI3C_SlaveNoLatency; - break; - case (uint8_t)kI3C_SlaveLatency1Ms: - returnCode = kI3C_SlaveLatency1Ms; - break; - case (uint8_t)kI3C_SlaveLatency100Ms: - returnCode = kI3C_SlaveLatency100Ms; - break; - case (uint8_t)kI3C_SlaveLatency10S: - returnCode = kI3C_SlaveLatency10S; - break; - default: - returnCode = kI3C_SlaveNoLatency; - break; - } - - return returnCode; -} - -/*! - * brief I3C slave request event. - * - * param base The I3C peripheral base address. - * param event I3C slave event of type #i3c_slave_event_t - * param data IBI data if In-band interrupt has data, only applicable for event type #kI3C_SlaveEventIBI - */ -void I3C_SlaveRequestEvent(I3C_Type *base, i3c_slave_event_t event) -{ - uint32_t ctrlValue = base->SCTRL; - - ctrlValue &= ~I3C_SCTRL_EVENT_MASK; - ctrlValue |= I3C_SCTRL_EVENT(event); - - base->SCTRL = ctrlValue; -} - -/*! - * brief I3C slave request event. - * - * param base The I3C peripheral base address. - * param data IBI data pointer - * param dataSize IBI data length - */ -void I3C_SlaveRequestIBIWithData(I3C_Type *base, i3c_slave_handle_t *handle, uint8_t *data, size_t dataSize) -{ - uint32_t ctrlValue = base->SCTRL; - - ctrlValue &= ~(I3C_SCTRL_EVENT_MASK | I3C_SCTRL_IBIDATA_MASK); - ctrlValue |= I3C_SCTRL_EVENT(1U) | I3C_SCTRL_IBIDATA(*data); - - if (dataSize > 1U) - { - handle->ibiData = &data[1]; - handle->ibiDataSize = dataSize - 1U; - } - - base->SCTRL = ctrlValue; -} - -/*! - * brief Performs a polling send transfer on the I3C bus. - * - * param base The I3C peripheral base address. - * param txBuff The pointer to the data to be transferred. - * param txSize The length in bytes of the data to be transferred. - * return Error or success status returned by API. - */ -status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize) -{ - const uint8_t *buf = (const uint8_t *)((const void *)txBuff); - status_t result = kStatus_Success; - - assert(NULL != txBuff); - - /* Send data buffer */ - while (0UL != txSize--) - { - /* Wait until there is room in the fifo. This also checks for errors. */ - result = I3C_SlaveWaitForTxReady(base); - if (kStatus_Success != result) - { - return result; - } - - /* Write byte into I3C slave data register. */ - if (0UL != txSize) - { - base->SWDATAB = *buf++; - } - else - { - base->SWDATABE = *buf++; - } - } - - return result; -} - -/*! - * brief Performs a polling receive transfer on the I3C bus. - * - * param base The I3C peripheral base address. - * param rxBuff The pointer to the data to be transferred. - * param rxSize The length in bytes of the data to be transferred. - * return Error or success status returned by API. - */ -status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize) -{ - status_t result = kStatus_Success; - uint8_t *buf; - - assert(NULL != rxBuff); - - /* Handle empty read. */ - if (0UL == rxSize) - { - return kStatus_Success; - } - -#if I3C_RETRY_TIMES - uint32_t waitTimes = I3C_RETRY_TIMES; -#endif - - /* Receive data */ - buf = (uint8_t *)rxBuff; - while (0UL != rxSize) - { -#if I3C_RETRY_TIMES - if (--waitTimes == 0) - { - return kStatus_I3C_Timeout; - } -#endif - /* Check for errors. */ - result = I3C_SlaveCheckAndClearError(base, I3C_SlaveGetErrorStatusFlags(base)); - if (kStatus_Success != result) - { - return result; - } - - /* Check RX data */ - if (0UL != (base->SDATACTRL & I3C_SDATACTRL_RXCOUNT_MASK)) - { - *buf++ = (uint8_t)(base->SRDATAB & I3C_SRDATAB_DATA0_MASK); - rxSize--; - } - } - - return result; -} - -/*! - * brief Creates a new handle for the I3C slave non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I3C_SlaveTransferAbort() API shall be called. - * - * note The function also enables the NVIC IRQ for the input I3C. Need to notice - * that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to - * enable the associated INTMUX IRQ in application. - - * param base The I3C peripheral base address. - * param[out] handle Pointer to the I3C slave driver handle. - * param callback User provided pointer to the asynchronous callback function. - * param userData User provided pointer to the application callback data. - */ -void I3C_SlaveTransferCreateHandle(I3C_Type *base, - i3c_slave_handle_t *handle, - i3c_slave_transfer_callback_t callback, - void *userData) -{ - uint32_t instance; - - assert(NULL != handle); - - /* Clear out the handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I3C_GetInstance(base); - - /* Save base and instance. */ - handle->callback = callback; - handle->userData = userData; - - /* Save this handle for IRQ use. */ - s_i3cSlaveHandle[instance] = handle; - - /* Set irq handler. */ - s_i3cSlaveIsr = I3C_SlaveTransferHandleIRQ; - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I3C_SlaveDisableInterrupts(base, (uint32_t)kSlaveIrqFlags); - (void)EnableIRQ(kI3cIrqs[instance]); -} - -/*! - * brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I3C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I3C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to - * the OR'd combination of #i3c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI3C_SlaveTransmitEvent and #kI3C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI3C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * param base The I3C peripheral base address. - * param handle Pointer to #i3c_slave_handle_t structure which stores the transfer state. - * param eventMask Bit mask formed by OR'ing together #i3c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI3C_SlaveAllEvents to enable all events. - * - * retval #kStatus_Success Slave transfers were successfully started. - * retval #kStatus_I3C_Busy Slave transfers have already been started on this handle. - */ -status_t I3C_SlaveTransferNonBlocking(I3C_Type *base, i3c_slave_handle_t *handle, uint32_t eventMask) -{ - assert(NULL != handle); - - /* Return busy if another transaction is in progress. */ - if (handle->isBusy) - { - return kStatus_I3C_Busy; - } - - /* Disable I3C IRQ sources while we configure stuff. */ - I3C_SlaveDisableInterrupts(base, (uint32_t)kSlaveIrqFlags); - - /* Clear transfer in handle. */ - (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); - - /* Set up event mask. tx and rx are always enabled. */ - handle->eventMask = eventMask | (uint32_t)kI3C_SlaveTransmitEvent | (uint32_t)kI3C_SlaveReceiveEvent; - - /* Clear all flags. */ - I3C_SlaveClearStatusFlags(base, (uint32_t)kSlaveClearFlags); - - /* Enable I3C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ - I3C_SlaveEnableInterrupts(base, (uint32_t)kSlaveIrqFlags); - - return kStatus_Success; -} - -/*! - * brief Gets the slave transfer status during a non-blocking transfer. - * param base The I3C peripheral base address. - * param handle Pointer to i2c_slave_handle_t structure. - * param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not - * required. - * retval #kStatus_Success - * retval #kStatus_NoTransferInProgress - */ -status_t I3C_SlaveTransferGetCount(I3C_Type *base, i3c_slave_handle_t *handle, size_t *count) -{ - assert(NULL != handle); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (!handle->isBusy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* For an active transfer, just return the count from the handle. */ - *count = handle->transferredCount; - - return kStatus_Success; -} - -/*! - * brief Aborts the slave non-blocking transfers. - * note This API could be called at any time to stop slave for handling the bus events. - * param base The I3C peripheral base address. - * param handle Pointer to #i3c_slave_handle_t structure which stores the transfer state. - * retval #kStatus_Success - * retval #kStatus_I3C_Idle - */ -void I3C_SlaveTransferAbort(I3C_Type *base, i3c_slave_handle_t *handle) -{ - assert(NULL != handle); - - /* Return idle if no transaction is in progress. */ - if (handle->isBusy) - { - /* Disable I3C IRQ sources. */ - I3C_SlaveDisableInterrupts(base, (uint32_t)kSlaveIrqFlags); - - /* Reset transfer info. */ - (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); - - /* We're no longer busy. */ - handle->isBusy = false; - } -} - -/*! - * brief Reusable routine to handle slave interrupts. - * note This function does not need to be called unless you are reimplementing the - * non blocking API's interrupt handler routines to add special functionality. - * param base The I3C peripheral base address. - * param handle Pointer to #i3c_slave_handle_t structure which stores the transfer state. - */ -void I3C_SlaveTransferHandleIRQ(I3C_Type *base, i3c_slave_handle_t *handle) -{ - uint32_t flags; - uint32_t errFlags; - uint32_t pendingInts; - uint32_t enabledInts; - size_t rxCount; - size_t txCount; - size_t txFifoSize = - 2UL << ((base->SCAPABILITIES & I3C_SCAPABILITIES_FIFOTX_MASK) >> I3C_SCAPABILITIES_FIFOTX_SHIFT); - i3c_slave_transfer_t *xfer; - - /* Check for a valid handle in case of a spurious interrupt. */ - if (NULL == handle) - { - return; - } - - xfer = &handle->transfer; - - /* Get status flags. */ - flags = I3C_SlaveGetStatusFlags(base); - errFlags = I3C_SlaveGetErrorStatusFlags(base); - - pendingInts = I3C_SlaveGetPendingInterrupts(base); - enabledInts = I3C_SlaveGetEnabledInterrupts(base); - - if (0UL != (errFlags & (uint32_t)kSlaveErrorFlags)) - { - xfer->event = (uint32_t)kI3C_SlaveCompletionEvent; - xfer->completionStatus = I3C_SlaveCheckAndClearError(base, errFlags); - - if ((0UL != (handle->eventMask & (uint32_t)kI3C_SlaveCompletionEvent)) && (NULL != handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } - return; - } - - /* Clear status flags. */ - I3C_SlaveClearStatusFlags(base, flags); - - if (0UL != (flags & (uint32_t)kI3C_SlaveBusStartFlag)) - { - base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK; - xfer->txDataSize = 0; - I3C_SlaveEnableInterrupts(base, (uint32_t)kI3C_SlaveTxReadyFlag); - pendingInts |= (uint32_t)kI3C_SlaveTxReadyFlag; - } - - if (0UL != (flags & (uint32_t)kI3C_SlaveEventSentFlag)) - { - xfer->event = (uint32_t)kI3C_SlaveRequestSentEvent; - if (handle->ibiData != NULL) - { - size_t count = 0U; - while (count < handle->ibiDataSize) - { - base->SCTRL = (base->SCTRL & ~I3C_SCTRL_IBIDATA_MASK) | I3C_SCTRL_IBIDATA(handle->ibiData[count]) | - I3C_SCTRL_EVENT(1U); - count++; - } - } - - /* Reset IBI data buffer. */ - handle->ibiData = NULL; - - if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } - } - - if (0UL != (flags & (uint32_t)kI3C_SlaveReceivedCCCFlag)) - { - handle->isBusy = true; - xfer->event = (uint32_t)kI3C_SlaveReceivedCCCEvent; - if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } - } - - if (0UL != (flags & (uint32_t)kI3C_SlaveBusStopFlag)) - { - I3C_SlaveDisableInterrupts(base, (uint32_t)kI3C_SlaveTxReadyFlag); - pendingInts &= ~(uint32_t)kI3C_SlaveTxReadyFlag; - base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK; - if (handle->isBusy == true) - { - xfer->event = (uint32_t)kI3C_SlaveCompletionEvent; - xfer->completionStatus = kStatus_Success; - xfer->transferredCount = handle->transferredCount; - handle->isBusy = false; - - if (handle->wasTransmit) - { - /* Subtract one from the transmit count to offset the fact that I3C asserts the */ - /* tx flag before it sees the nack from the master-receiver, thus causing one more */ - /* count that the master actually receives. */ - --xfer->transferredCount; - handle->wasTransmit = false; - } - - if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } - - /* Clean up transfer info on completion, after the callback has been invoked. */ - (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); - } - else - { - return; - } - } - - if (0UL != (flags & (uint32_t)kI3C_SlaveMatchedFlag)) - { - xfer->event = (uint32_t)kI3C_SlaveAddressMatchEvent; - handle->isBusy = true; - if ((0UL != (handle->eventMask & (uint32_t)kI3C_SlaveAddressMatchEvent)) && (NULL != handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } - } - - /* Get fifo counts and compute room in tx fifo. */ - I3C_SlaveGetFifoCounts(base, &rxCount, &txCount); - txCount = txFifoSize - txCount; - - /* Handle transmit and receive. */ - if ((0UL != (flags & (uint32_t)kI3C_SlaveTxReadyFlag)) && (0UL != (pendingInts & (uint32_t)kI3C_SlaveTxReadyFlag))) - { - handle->wasTransmit = true; - - /* If we're out of data, invoke callback to get more. */ - if ((NULL == xfer->txData) || (0UL == xfer->txDataSize)) - { - xfer->event = (uint32_t)kI3C_SlaveTransmitEvent; - if (0UL != (flags & (uint32_t)kI3C_SlaveBusHDRModeFlag)) - { - xfer->event |= (uint32_t)kI3C_SlaveHDRCommandMatchEvent; - } - if (NULL != handle->callback) - { - handle->callback(base, xfer, handle->userData); - } - - /* Clear the transferred count now that we have a new buffer. */ - handle->transferredCount = 0; - } - - if ((NULL == xfer->txData) || (0UL == xfer->txDataSize)) - { - I3C_SlaveDisableInterrupts(base, (uint32_t)kI3C_SlaveTxReadyFlag); - pendingInts &= ~(uint32_t)kI3C_SlaveTxReadyFlag; - } - - /* Transmit a byte. */ - while ((xfer->txDataSize != 0UL) && (txCount != 0U)) - { - if (xfer->txDataSize > 1UL) - { - base->SWDATAB = *xfer->txData++; - } - else - { - base->SWDATABE = *xfer->txData++; - I3C_SlaveDisableInterrupts(base, (uint32_t)kI3C_SlaveTxReadyFlag); - } - --xfer->txDataSize; - ++handle->transferredCount; - txCount--; - } - } - if ((0UL != (flags & (uint32_t)kI3C_SlaveRxReadyFlag)) && (0UL != (enabledInts & (uint32_t)kI3C_SlaveRxReadyFlag))) - { - /* If we're out of room in the buffer, invoke callback to get another. */ - if ((NULL == xfer->rxData) || (0UL == xfer->rxDataSize)) - { - xfer->event = (uint32_t)kI3C_SlaveReceiveEvent; - if (0UL != (flags & (uint32_t)kI3C_SlaveBusHDRModeFlag)) - { - xfer->event |= (uint32_t)kI3C_SlaveHDRCommandMatchEvent; - } - if (NULL != handle->callback) - { - handle->callback(base, xfer, handle->userData); - } - handle->transferredCount = 0; - } - - /* Receive a byte. */ - if ((I3C_SlaveGetEnabledInterrupts(base) & (uint32_t)kI3C_SlaveRxReadyFlag) != 0U) - { - while ((rxCount != 0U) && ((xfer->rxData != NULL) && (xfer->rxDataSize != 0UL))) - { - *xfer->rxData++ = (uint8_t)base->SRDATAB; - --xfer->rxDataSize; - ++handle->transferredCount; - rxCount--; - } - } - } -} - -static void I3C_CommonIRQHandler(I3C_Type *base, uint32_t instance) -{ - /* Check for master IRQ. */ - if (((uint32_t)kI3C_MasterOn == (base->MCONFIG & I3C_MCONFIG_MSTENA_MASK)) && (NULL != s_i3cMasterIsr)) - { - /* Master mode. */ - s_i3cMasterIsr(base, s_i3cMasterHandle[instance]); - } - - /* Check for slave IRQ. */ - if ((I3C_SCONFIG_SLVENA_MASK == (base->SCONFIG & I3C_SCONFIG_SLVENA_MASK)) && (NULL != s_i3cSlaveIsr)) - { - /* Slave mode. */ - s_i3cSlaveIsr(base, s_i3cSlaveHandle[instance]); - } - SDK_ISR_EXIT_BARRIER; -} - -#if defined(I3C) -/* Implementation of I3C handler named in startup code. */ -void I3C0_DriverIRQHandler(void); -void I3C0_DriverIRQHandler(void) -{ - I3C_CommonIRQHandler(I3C, 0); -} -#endif - -#if defined(I3C0) -/* Implementation of I3C0 handler named in startup code. */ -void I3C0_DriverIRQHandler(void); -void I3C0_DriverIRQHandler(void) -{ - I3C_CommonIRQHandler(I3C0, 0); -} -#endif - -#if defined(I3C1) -/* Implementation of I3C1 handler named in startup code. */ -void I3C1_DriverIRQHandler(void); -void I3C1_DriverIRQHandler(void) -{ - I3C_CommonIRQHandler(I3C1, 1); -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i3c.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i3c.h deleted file mode 100644 index 560a02261d7..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i3c.h +++ /dev/null @@ -1,1752 +0,0 @@ -/* - * Copyright 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I3C_H_ -#define _FSL_I3C_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup i3c - * @{ - */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I3C driver version */ -#define FSL_I3C_DRIVER_VERSION (MAKE_VERSION(2, 5, 2)) -/*@}*/ - -/*! @brief Timeout times for waiting flag. */ -#ifndef I3C_RETRY_TIMES -#define I3C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ -#endif - -#define I3C_MAX_DEVCNT 10U - -#ifndef I3C_IBI_BUFF_SIZE -#define I3C_IBI_BUFF_SIZE 10U -#endif - -/*! @brief I3C status return codes. */ -enum -{ - kStatus_I3C_Busy = MAKE_STATUS(kStatusGroup_I3C, 0), /*!< The master is already performing a transfer. */ - kStatus_I3C_Idle = MAKE_STATUS(kStatusGroup_I3C, 1), /*!< The slave driver is idle. */ - kStatus_I3C_Nak = MAKE_STATUS(kStatusGroup_I3C, 2), /*!< The slave device sent a NAK in response to an address. */ - kStatus_I3C_WriteAbort = - MAKE_STATUS(kStatusGroup_I3C, 3), /*!< The slave device sent a NAK in response to a write. */ - kStatus_I3C_Term = MAKE_STATUS(kStatusGroup_I3C, 4), /*!< The master terminates slave read. */ - kStatus_I3C_HdrParityError = MAKE_STATUS(kStatusGroup_I3C, 5), /*!< Parity error from DDR read. */ - kStatus_I3C_CrcError = MAKE_STATUS(kStatusGroup_I3C, 6), /*!< CRC error from DDR read. */ - kStatus_I3C_ReadFifoError = MAKE_STATUS(kStatusGroup_I3C, 7), /*!< Read from M/SRDATAB register when FIFO empty. */ - kStatus_I3C_WriteFifoError = MAKE_STATUS(kStatusGroup_I3C, 8), /*!< Write to M/SWDATAB register when FIFO full. */ - kStatus_I3C_MsgError = - MAKE_STATUS(kStatusGroup_I3C, 9), /*!< Message SDR/DDR mismatch or read/write message in wrong state */ - kStatus_I3C_InvalidReq = MAKE_STATUS(kStatusGroup_I3C, 10), /*!< Invalid use of request. */ - kStatus_I3C_Timeout = MAKE_STATUS(kStatusGroup_I3C, 11), /*!< The module has stalled too long in a frame. */ - kStatus_I3C_SlaveCountExceed = - MAKE_STATUS(kStatusGroup_I3C, 12), /*!< The I3C slave count has exceed the definition in I3C_MAX_DEVCNT. */ - kStatus_I3C_IBIWon = MAKE_STATUS( - kStatusGroup_I3C, 13), /*!< The I3C slave event IBI or MR or HJ won the arbitration on a header address. */ - kStatus_I3C_OverrunError = MAKE_STATUS(kStatusGroup_I3C, 14), /*!< Slave internal from-bus buffer/FIFO overrun. */ - kStatus_I3C_UnderrunError = MAKE_STATUS(kStatusGroup_I3C, 15), /*!< Slave internal to-bus buffer/FIFO underrun */ - kStatus_I3C_UnderrunNak = - MAKE_STATUS(kStatusGroup_I3C, 16), /*!< Slave internal from-bus buffer/FIFO underrun and NACK error */ - kStatus_I3C_InvalidStart = MAKE_STATUS(kStatusGroup_I3C, 17), /*!< Slave invalid start flag */ - kStatus_I3C_SdrParityError = MAKE_STATUS(kStatusGroup_I3C, 18), /*!< SDR parity error */ - kStatus_I3C_S0S1Error = MAKE_STATUS(kStatusGroup_I3C, 19), /*!< S0 or S1 error */ -}; - -/*! @brief I3C HDR modes. */ -typedef enum _i3c_hdr_mode -{ - kI3C_HDRModeNone = 0x00U, /* Do not support HDR mode. */ - kI3C_HDRModeDDR = 0x01U, /* HDR-DDR Mode. */ - kI3C_HDRModeTSP = 0x02U, /* HDR-TSP Mode. */ - kI3C_HDRModeTSL = 0x04U, /* HDR-TSL Mode. */ -} i3c_hdr_mode_t; - -/*! @brief I3C device information. */ -typedef struct _i3c_device_info -{ - uint8_t dynamicAddr; /*!< Device dynamic address. */ - uint8_t staticAddr; /*!< Static address. */ - uint8_t dcr; /*!< Device characteristics register information. */ - uint8_t bcr; /*!< Bus characteristics register information. */ - uint16_t vendorID; /*!< Device vendor ID(manufacture ID). */ - uint32_t partNumber; /*!< Device part number info */ - uint16_t maxReadLength; /*!< Maximum read length. */ - uint16_t maxWriteLength; /*!< Maximum write length. */ - uint8_t hdrMode; /*!< Support hdr mode, could be OR logic in i3c_hdr_mode. */ -} i3c_device_info_t; - -/*! @} */ - -/*! - * @addtogroup i3c_master_driver - * @{ - */ - -/*! - * @brief I3C master peripheral flags. - * - * The following status register flags can be cleared: - * - #kI3C_MasterSlaveStartFlag - * - #kI3C_MasterControlDoneFlag - * - #kI3C_MasterCompleteFlag - * - #kI3C_MasterArbitrationWonFlag - * - #kI3C_MasterSlave2MasterFlag - * - * All flags except #kI3C_MasterBetweenFlag and #kI3C_MasterNackDetectFlag can be enabled as - * interrupts. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -enum _i3c_master_flags -{ - kI3C_MasterBetweenFlag = I3C_MSTATUS_BETWEEN_MASK, /*!< Between messages/DAAs flag */ - kI3C_MasterNackDetectFlag = I3C_MSTATUS_NACKED_MASK, /*!< NACK detected flag */ - kI3C_MasterSlaveStartFlag = I3C_MSTATUS_SLVSTART_MASK, /*!< Slave request start flag */ - kI3C_MasterControlDoneFlag = I3C_MSTATUS_MCTRLDONE_MASK, /*!< Master request complete flag */ - kI3C_MasterCompleteFlag = I3C_MSTATUS_COMPLETE_MASK, /*!< Transfer complete flag */ - kI3C_MasterRxReadyFlag = I3C_MSTATUS_RXPEND_MASK, /*!< Rx data ready in Rx buffer flag */ - kI3C_MasterTxReadyFlag = I3C_MSTATUS_TXNOTFULL_MASK, /*!< Tx buffer ready for Tx data flag */ - kI3C_MasterArbitrationWonFlag = I3C_MSTATUS_IBIWON_MASK, /*!< Header address won arbitration flag */ - kI3C_MasterErrorFlag = I3C_MSTATUS_ERRWARN_MASK, /*!< Error occurred flag */ - kI3C_MasterSlave2MasterFlag = I3C_MSTATUS_NOWMASTER_MASK, /*!< Switch from slave to master flag */ - kI3C_MasterClearFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag | - kI3C_MasterArbitrationWonFlag | kI3C_MasterSlave2MasterFlag | kI3C_MasterErrorFlag, -}; - -/*! - * @brief I3C master error flags to indicate the causes. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -enum _i3c_master_error_flags -{ - kI3C_MasterErrorNackFlag = I3C_MERRWARN_NACK_MASK, /*!< Slave NACKed the last address */ - kI3C_MasterErrorWriteAbortFlag = I3C_MERRWARN_WRABT_MASK, /*!< Slave NACKed the write data */ -#if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) - kI3C_MasterErrorTermFlag = I3C_MERRWARN_TERM_MASK, /*!< Master terminates slave read */ -#endif - kI3C_MasterErrorParityFlag = I3C_MERRWARN_HPAR_MASK, /*!< Parity error from DDR read */ - kI3C_MasterErrorCrcFlag = I3C_MERRWARN_HCRC_MASK, /*!< CRC error from DDR read */ - kI3C_MasterErrorReadFlag = I3C_MERRWARN_OREAD_MASK, /*!< Read from MRDATAB register when FIFO empty */ - kI3C_MasterErrorWriteFlag = I3C_MERRWARN_OWRITE_MASK, /*!< Write to MWDATAB register when FIFO full */ - kI3C_MasterErrorMsgFlag = I3C_MERRWARN_MSGERR_MASK, /*!< Message SDR/DDR mismatch or - read/write message in wrong state */ - kI3C_MasterErrorInvalidReqFlag = I3C_MERRWARN_INVREQ_MASK, /*!< Invalid use of request */ - kI3C_MasterErrorTimeoutFlag = I3C_MERRWARN_TIMEOUT_MASK, /*!< The module has stalled too long in a frame */ - kI3C_MasterAllErrorFlags = kI3C_MasterErrorNackFlag | kI3C_MasterErrorWriteAbortFlag | -#if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) - kI3C_MasterErrorTermFlag | -#endif - kI3C_MasterErrorParityFlag | kI3C_MasterErrorCrcFlag | kI3C_MasterErrorReadFlag | - kI3C_MasterErrorWriteFlag | kI3C_MasterErrorMsgFlag | kI3C_MasterErrorInvalidReqFlag | - kI3C_MasterErrorTimeoutFlag, /*!< All error flags */ -}; - -/*! @brief I3C working master state. */ -typedef enum _i3c_master_state -{ - kI3C_MasterStateIdle = 0U, /*!< Bus stopped. */ - kI3C_MasterStateSlvReq = 1U, /*!< Bus stopped but slave holding SDA low. */ - kI3C_MasterStateMsgSdr = 2U, /*!< In SDR Message mode from using MWMSG_SDR. */ - kI3C_MasterStateNormAct = 3U, /*!< In normal active SDR mode. */ - kI3C_MasterStateDdr = 4U, /*!< In DDR Message mode. */ - kI3C_MasterStateDaa = 5U, /*!< In ENTDAA mode. */ - kI3C_MasterStateIbiAck = 6U, /*!< Waiting on IBI ACK/NACK decision. */ - kI3C_MasterStateIbiRcv = 7U, /*!< receiving IBI. */ -} i3c_master_state_t; - -/*! @brief I3C master enable configuration. */ -typedef enum _i3c_master_enable -{ - kI3C_MasterOff = 0U, /*!< Master off. */ - kI3C_MasterOn = 1U, /*!< Master on. */ - kI3C_MasterCapable = 2U /*!< Master capable. */ -} i3c_master_enable_t; - -/*! @brief I3C high keeper configuration. */ -typedef enum _i3c_master_hkeep -{ - kI3C_MasterHighKeeperNone = 0U, /*!< Use PUR to hold SCL high. */ - kI3C_MasterHighKeeperWiredIn = 1U, /*!< Use pin_HK controls. */ - kI3C_MasterPassiveSDA = 2U, /*!< Hi-Z for Bus Free and hold SDA. */ - kI3C_MasterPassiveSDASCL = 3U /*!< Hi-Z both for Bus Free, and can Hi-Z SDA for hold. */ -} i3c_master_hkeep_t; - -/*! @brief Emits the requested operation when doing in pieces vs. by message. */ -typedef enum _i3c_bus_request -{ - kI3C_RequestNone = 0U, /*!< No request. */ - kI3C_RequestEmitStartAddr = 1U, /*!< Request to emit start and address on bus. */ - kI3C_RequestEmitStop = 2U, /*!< Request to emit stop on bus. */ - kI3C_RequestIbiAckNack = 3U, /*!< Manual IBI ACK or NACK. */ - kI3C_RequestProcessDAA = 4U, /*!< Process DAA. */ - kI3C_RequestForceExit = 6U, /*!< Request to force exit. */ - kI3C_RequestAutoIbi = 7U, /*!< Hold in stopped state, but Auto-emit START,7E. */ -} i3c_bus_request_t; - -/*! @brief Bus type with EmitStartAddr. */ -typedef enum _i3c_bus_type -{ - kI3C_TypeI3CSdr = 0U, /*!< SDR mode of I3C. */ - kI3C_TypeI2C = 1U, /*!< Standard i2c protocol. */ - kI3C_TypeI3CDdr = 2U, /*!< HDR-DDR mode of I3C. */ -} i3c_bus_type_t; - -/*! @brief IBI response. */ -typedef enum _i3c_ibi_response -{ - kI3C_IbiRespAck = 0U, /*!< ACK with no mandatory byte. */ - kI3C_IbiRespNack = 1U, /*!< NACK. */ - kI3C_IbiRespAckMandatory = 2U, /*!< ACK with mandatory byte. */ - kI3C_IbiRespManual = 3U, /*!< Reserved. */ -} i3c_ibi_response_t; - -/*! @brief IBI type. */ -typedef enum _i3c_ibi_type -{ - kI3C_IbiNormal = 0U, /*!< In-band interrupt. */ - kI3C_IbiHotJoin = 1U, /*!< slave hot join. */ - kI3C_IbiMasterRequest = 2U, /*!< slave master ship request. */ -} i3c_ibi_type_t; - -/*! @brief IBI state. */ -typedef enum _i3c_ibi_state -{ - kI3C_IbiReady = 0U, /*!< In-band interrupt ready state, ready for user to handle. */ - kI3C_IbiDataBuffNeed = 1U, /*!< In-band interrupt need data buffer for data receive. */ - kI3C_IbiAckNackPending = 2U, /*!< In-band interrupt Ack/Nack pending for decision. */ -} i3c_ibi_state_t; - -/*! @brief Direction of master and slave transfers. */ -typedef enum _i3c_direction -{ - kI3C_Write = 0U, /*!< Master transmit. */ - kI3C_Read = 1U /*!< Master receive. */ -} i3c_direction_t; - -/*! @brief Watermark of TX int/dma trigger level. */ -typedef enum _i3c_tx_trigger_level -{ - kI3C_TxTriggerOnEmpty = 0U, /*!< Trigger on empty. */ - kI3C_TxTriggerUntilOneQuarterOrLess = 1U, /*!< Trigger on 1/4 full or less. */ - kI3C_TxTriggerUntilOneHalfOrLess = 2U, /*!< Trigger on 1/2 full or less. */ - kI3C_TxTriggerUntilOneLessThanFull = 3U, /*!< Trigger on 1 less than full or less. */ -} i3c_tx_trigger_level_t; - -/*! @brief Watermark of RX int/dma trigger level. */ -typedef enum _i3c_rx_trigger_level -{ - kI3C_RxTriggerOnNotEmpty = 0U, /*!< Trigger on not empty. */ - kI3C_RxTriggerUntilOneQuarterOrMore = 1U, /*!< Trigger on 1/4 full or more. */ - kI3C_RxTriggerUntilOneHalfOrMore = 2U, /*!< Trigger on 1/2 full or more. */ - kI3C_RxTriggerUntilThreeQuarterOrMore = 3U, /*!< Trigger on 3/4 full or more. */ -} i3c_rx_trigger_level_t; - -/*! @brief Structure with setting master IBI rules and slave registry. */ -typedef struct _i3c_register_ibi_addr -{ - uint8_t address[5]; /*!< Address array for registry. */ - bool ibiHasPayload; /*!< Whether the address array has mandatory IBI byte. */ -} i3c_register_ibi_addr_t; - -/*! @brief Structure with I3C baudrate settings. */ -typedef struct _i3c_baudrate -{ - uint32_t i2cBaud; /*!< Desired I2C baud rate in Hertz. */ - uint32_t i3cPushPullBaud; /*!< Desired I3C push-pull baud rate in Hertz. */ - uint32_t i3cOpenDrainBaud; /*!< Desired I3C open-drain baud rate in Hertz. */ -} i3c_baudrate_hz_t; - -/*! - * @brief Structure with settings to initialize the I3C master module. - * - * This structure holds configuration settings for the I3C peripheral. To initialize this - * structure to reasonable defaults, call the I3C_MasterGetDefaultConfig() function and - * pass a pointer to your configuration structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _i3c_master_config -{ - i3c_master_enable_t enableMaster; /*!< Enable master mode. */ - bool disableTimeout; /*!< Whether to disable timeout to prevent the ERRWARN. */ - i3c_master_hkeep_t hKeep; /*!< High keeper mode setting. */ - bool enableOpenDrainStop; /*!< Whether to emit open-drain speed STOP. */ - bool enableOpenDrainHigh; /*!< Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. */ - i3c_baudrate_hz_t baudRate_Hz; /*!< Desired baud rate settings. */ -} i3c_master_config_t; - -/* Forward declaration of the transfer descriptor and handle typedefs. */ -typedef struct _i3c_master_transfer i3c_master_transfer_t; -typedef struct _i3c_master_handle i3c_master_handle_t; - -/*! @brief i3c master callback functions. */ -typedef struct _i3c_master_transfer_callback -{ - void (*slave2Master)(I3C_Type *base, void *userData); /*!< Transfer complete callback */ - void (*ibiCallback)(I3C_Type *base, - i3c_master_handle_t *handle, - i3c_ibi_type_t ibiType, - i3c_ibi_state_t ibiState); /*!< IBI event callback */ - void (*transferComplete)(I3C_Type *base, - i3c_master_handle_t *handle, - status_t completionStatus, - void *userData); /*!< Transfer complete callback */ -} i3c_master_transfer_callback_t; -/*! - * @brief Transfer option flags. - * - * @note These enumerations are intended to be OR'd together to form a bit mask of options for - * the #_i3c_master_transfer::flags field. - */ -enum _i3c_master_transfer_flags -{ - kI3C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ - kI3C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ - kI3C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ - kI3C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ - kI3C_TransferWordsFlag = 0x08U, /*!< Transfer in words, else transfer in bytes. */ -}; - -/*! - * @brief Non-blocking transfer descriptor structure. - * - * This structure is used to pass transaction parameters to the I3C_MasterTransferNonBlocking() API. - */ -struct _i3c_master_transfer -{ - uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available - options. Set to 0 or #kI3C_TransferDefaultFlag for normal transfers. */ - uint8_t slaveAddress; /*!< The 7-bit slave address. */ - i3c_direction_t direction; /*!< Either #kI3C_Read or #kI3C_Write. */ - uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ - size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ - void *data; /*!< Pointer to data to transfer. */ - size_t dataSize; /*!< Number of bytes to transfer. */ - i3c_bus_type_t busType; /*!< bus type. */ - i3c_ibi_response_t ibiResponse; /*!< ibi response during transfer. */ -}; - -/*! - * @brief Driver handle for master non-blocking APIs. - * @note The contents of this structure are private and subject to change. - */ -struct _i3c_master_handle -{ - uint8_t state; /*!< Transfer state machine current state. */ - uint32_t remainingBytes; /*!< Remaining byte count in current state. */ - bool isReadTerm; /*!< Is readterm configured. */ - i3c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ - uint8_t ibiAddress; /*!< Slave address which request IBI. */ - uint8_t *ibiBuff; /*!< Pointer to IBI buffer to keep ibi bytes. */ - size_t ibiPayloadSize; /*!< IBI payload size. */ - i3c_ibi_type_t ibiType; /*!< IBI type. */ - i3c_master_transfer_callback_t callback; /*!< Callback functions pointer. */ - void *userData; /*!< Application data passed to callback. */ -}; - -/*! @brief Typedef for master interrupt handler. */ -typedef void (*i3c_master_isr_t)(I3C_Type *base, i3c_master_handle_t *handle); - -/*! @} */ - -/*! - * @addtogroup i3c_slave_driver - * @{ - */ - -/*! - * @brief I3C slave peripheral flags. - * - * The following status register flags can be cleared: - * - #kI3C_SlaveBusStartFlag - * - #kI3C_SlaveMatchedFlag - * - #kI3C_SlaveBusStopFlag - * - * Only below flags can be enabled as interrupts. - * - #kI3C_SlaveBusStartFlag - * - #kI3C_SlaveMatchedFlag - * - #kI3C_SlaveBusStopFlag - * - #kI3C_SlaveRxReadyFlag - * - #kI3C_SlaveTxReadyFlag - * - #kI3C_SlaveDynamicAddrChangedFlag - * - #kI3C_SlaveReceivedCCCFlag - * - #kI3C_SlaveErrorFlag - * - #kI3C_SlaveHDRCommandMatchFlag - * - #kI3C_SlaveCCCHandledFlag - * - #kI3C_SlaveEventSentFlag - - * @note These enums are meant to be OR'd together to form a bit mask. - */ -enum _i3c_slave_flags -{ - kI3C_SlaveNotStopFlag = I3C_SSTATUS_STNOTSTOP_MASK, /*!< Slave status not stop flag */ - kI3C_SlaveMessageFlag = I3C_SSTATUS_STMSG_MASK, /*!< Slave status message, indicating slave is - listening to the bus traffic or responding */ - kI3C_SlaveRequiredReadFlag = I3C_SSTATUS_STREQRD_MASK, /*!< Slave status required, either is master doing SDR - read from slave, or is IBI pushing out. */ - kI3C_SlaveRequiredWriteFlag = I3C_SSTATUS_STREQWR_MASK, /*!< Slave status request write, master is doing SDR - write to slave, except slave in ENTDAA mode */ - kI3C_SlaveBusDAAFlag = I3C_SSTATUS_STDAA_MASK, /*!< I3C bus is in ENTDAA mode */ - kI3C_SlaveBusHDRModeFlag = I3C_SSTATUS_STHDR_MASK, /*!< I3C bus is in HDR mode */ - kI3C_SlaveBusStartFlag = I3C_SSTATUS_START_MASK, /*!< Start/Re-start event is seen since the bus was last cleared */ - kI3C_SlaveMatchedFlag = I3C_SSTATUS_MATCHED_MASK, /*!< Slave address(dynamic/static) matched since last cleared */ - kI3C_SlaveBusStopFlag = I3C_SSTATUS_STOP_MASK, /*!enableMaster = kI3C_MasterCapable; - * config->disableTimeout = false; - * config->hKeep = kI3C_MasterHighKeeperNone; - * config->enableOpenDrainStop = true; - * config->enableOpenDrainHigh = true; - * config->baudRate_Hz.i2cBaud = 400000U; - * config->baudRate_Hz.i3cPushPullBaud = 12500000U; - * config->baudRate_Hz.i3cOpenDrainBaud = 2500000U; - * config->masterDynamicAddress = 0x0AU; - * config->slowClock_Hz = 1000000U; - * config->enableSlave = true; - * config->vendorID = 0x11BU; - * config->enableRandomPart = false; - * config->partNumber = 0; - * config->dcr = 0; - * config->bcr = 0; - * config->hdrMode = (uint8_t)kI3C_HDRModeDDR; - * config->nakAllRequest = false; - * config->ignoreS0S1Error = false; - * config->offline = false; - * config->matchSlaveStartStop = false; - * @endcode - * - * After calling this function, you can override any settings in order to customize the configuration, - * prior to initializing the common I3C driver with I3C_Init(). - * - * @param[out] config User provided configuration structure for default values. Refer to #i3c_config_t. - */ -void I3C_GetDefaultConfig(i3c_config_t *config); - -/*! - * @brief Initializes the I3C peripheral. - * This function enables the peripheral clock and initializes the I3C peripheral as described by the user - * provided configuration. This will initialize both the master peripheral and slave peripheral so that I3C - * module could work as pure master, pure slave or secondary master, etc. - * A software reset is performed prior to configuration. - * - * @param base The I3C peripheral base address. - * @param config User provided peripheral configuration. Use I3C_GetDefaultConfig() to get a set of - * defaults that you can override. - * @param sourceClock_Hz Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, - * filter widths, and timeout periods. - */ -void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_Hz); - -/*! @} */ - -/*! - * @addtogroup i3c_master_driver - * @{ - */ - -/*! @name Initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the I3C master peripheral. - * - * This function provides the following default configuration for the I3C master peripheral: - * @code - * masterConfig->enableMaster = kI3C_MasterOn; - * masterConfig->disableTimeout = false; - * masterConfig->hKeep = kI3C_MasterHighKeeperNone; - * masterConfig->enableOpenDrainStop = true; - * masterConfig->enableOpenDrainHigh = true; - * masterConfig->baudRate_Hz = 100000U; - * masterConfig->busType = kI3C_TypeI2C; - * @endcode - * - * After calling this function, you can override any settings in order to customize the configuration, - * prior to initializing the master driver with I3C_MasterInit(). - * - * @param[out] masterConfig User provided configuration structure for default values. Refer to #i3c_master_config_t. - */ -void I3C_MasterGetDefaultConfig(i3c_master_config_t *masterConfig); - -/*! - * @brief Initializes the I3C master peripheral. - * - * This function enables the peripheral clock and initializes the I3C master peripheral as described by the user - * provided configuration. A software reset is performed prior to configuration. - * - * @param base The I3C peripheral base address. - * @param masterConfig User provided peripheral configuration. Use I3C_MasterGetDefaultConfig() to get a set of - * defaults that you can override. - * @param sourceClock_Hz Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, - * filter widths, and timeout periods. - */ -void I3C_MasterInit(I3C_Type *base, const i3c_master_config_t *masterConfig, uint32_t sourceClock_Hz); - -/*! - * @brief Deinitializes the I3C master peripheral. - * - * This function disables the I3C master peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * @param base The I3C peripheral base address. - */ -void I3C_MasterDeinit(I3C_Type *base); - -/* Not static so it can be used from fsl_i3c_dma.c. */ -status_t I3C_MasterCheckAndClearError(I3C_Type *base, uint32_t status); - -/* Not static so it can be used from fsl_i3c_dma.c. */ -status_t I3C_CheckForBusyBus(I3C_Type *base); - -/*! - * @brief Set I3C module master mode. - * - * @param base The I3C peripheral base address. - * @param enable Enable master mode. - */ -static inline void I3C_MasterEnable(I3C_Type *base, i3c_master_enable_t enable) -{ - base->MCONFIG = (base->MCONFIG & ~I3C_MCONFIG_MSTENA_MASK) | I3C_MCONFIG_MSTENA(enable); -} - -/*@}*/ - -/*! @name Status */ -/*@{*/ - -/*! - * @brief Gets the I3C master status flags. - * - * A bit mask with the state of all I3C master status flags is returned. For each flag, the corresponding bit - * in the return value is set if the flag is asserted. - * - * @param base The I3C peripheral base address. - * @return State of the status flags: - * - 1: related status flag is set. - * - 0: related status flag is not set. - * @see _i3c_master_flags - */ -static inline uint32_t I3C_MasterGetStatusFlags(I3C_Type *base) -{ - return base->MSTATUS & ~(I3C_MSTATUS_STATE_MASK | I3C_MSTATUS_IBITYPE_MASK); -} - -/*! - * @brief Clears the I3C master status flag state. - * - * The following status register flags can be cleared: - * - #kI3C_MasterSlaveStartFlag - * - #kI3C_MasterControlDoneFlag - * - #kI3C_MasterCompleteFlag - * - #kI3C_MasterArbitrationWonFlag - * - #kI3C_MasterSlave2MasterFlag - * - * Attempts to clear other flags has no effect. - * - * @param base The I3C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * #_i3c_master_flags enumerators OR'd together. You may pass the result of a previous call to - * I3C_MasterGetStatusFlags(). - * @see _i3c_master_flags. - */ -static inline void I3C_MasterClearStatusFlags(I3C_Type *base, uint32_t statusMask) -{ - base->MSTATUS = statusMask; -} - -/*! - * @brief Gets the I3C master error status flags. - * - * A bit mask with the state of all I3C master error status flags is returned. For each flag, the corresponding bit - * in the return value is set if the flag is asserted. - * - * @param base The I3C peripheral base address. - * @return State of the error status flags: - * - 1: related status flag is set. - * - 0: related status flag is not set. - * @see _i3c_master_error_flags - */ -static inline uint32_t I3C_MasterGetErrorStatusFlags(I3C_Type *base) -{ - return base->MERRWARN; -} - -/*! - * @brief Clears the I3C master error status flag state. - * - * @param base The I3C peripheral base address. - * @param statusMask A bitmask of error status flags that are to be cleared. The mask is composed of - * #_i3c_master_error_flags enumerators OR'd together. You may pass the result of a previous call to - * I3C_MasterGetStatusFlags(). - * @see _i3c_master_error_flags. - */ -static inline void I3C_MasterClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask) -{ - base->MERRWARN = statusMask; - while ((base->MERRWARN & statusMask) != 0U) - { - } -} - -/*! - * @brief Gets the I3C master state. - * - * @param base The I3C peripheral base address. - * @return I3C master state. - */ -i3c_master_state_t I3C_MasterGetState(I3C_Type *base); - -/*@}*/ - -/*! @name Interrupts */ -/*@{*/ - -/*! - * @brief Enables the I3C master interrupt requests. - * - * All flags except #kI3C_MasterBetweenFlag and #kI3C_MasterNackDetectFlag can be enabled as - * interrupts. - * - * @param base The I3C peripheral base address. - * @param interruptMask Bit mask of interrupts to enable. See #_i3c_master_flags for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I3C_MasterEnableInterrupts(I3C_Type *base, uint32_t interruptMask) -{ - base->MINTSET |= interruptMask; -} - -/*! - * @brief Disables the I3C master interrupt requests. - * - * All flags except #kI3C_MasterBetweenFlag and #kI3C_MasterNackDetectFlag can be enabled as - * interrupts. - * - * @param base The I3C peripheral base address. - * @param interruptMask Bit mask of interrupts to disable. See #_i3c_master_flags for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I3C_MasterDisableInterrupts(I3C_Type *base, uint32_t interruptMask) -{ - base->MINTCLR = interruptMask; -} - -/*! - * @brief Returns the set of currently enabled I3C master interrupt requests. - * - * @param base The I3C peripheral base address. - * @return A bitmask composed of #_i3c_master_flags enumerators OR'd together to indicate the - * set of enabled interrupts. - */ -static inline uint32_t I3C_MasterGetEnabledInterrupts(I3C_Type *base) -{ - return base->MINTSET; -} - -/*! - * @brief Returns the set of pending I3C master interrupt requests. - * - * @param base The I3C peripheral base address. - * @return A bitmask composed of #_i3c_master_flags enumerators OR'd together to indicate the - * set of pending interrupts. - */ -static inline uint32_t I3C_MasterGetPendingInterrupts(I3C_Type *base) -{ - return base->MINTMASKED; -} - -/*@}*/ - -/*! @name DMA control */ -/*@{*/ - -/*! - * @brief Enables or disables I3C master DMA requests. - * - * @param base The I3C peripheral base address. - * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable. - * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable. - * @param width DMA read/write unit in bytes. - */ -static inline void I3C_MasterEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width) -{ - assert(width <= 2U); - base->MDMACTRL = - I3C_MDMACTRL_DMAFB(enableRx ? 2U : 0U) | I3C_MDMACTRL_DMATB(enableTx ? 2U : 0U) | I3C_MDMACTRL_DMAWIDTH(width); -} - -/*! - * @brief Gets I3C master transmit data register address for DMA transfer. - * - * @param base The I3C peripheral base address. - * @param width DMA read/write unit in bytes. - * @return The I3C Master Transmit Data Register address. - */ -static inline uint32_t I3C_MasterGetTxFifoAddress(I3C_Type *base, uint32_t width) -{ - assert(width <= 2U); - return (uint32_t)((width == 2U) ? &base->MWDATAH : &base->MWDATAB); -} - -/*! - * @brief Gets I3C master receive data register address for DMA transfer. - * - * @param base The I3C peripheral base address. - * @param width DMA read/write unit in bytes. - * @return The I3C Master Receive Data Register address. - */ -static inline uint32_t I3C_MasterGetRxFifoAddress(I3C_Type *base, uint32_t width) -{ - assert(width <= 2U); - return (uint32_t)((width == 2U) ? &base->MRDATAH : &base->MRDATAB); -} - -/*@}*/ - -/*! @name FIFO control */ -/*@{*/ - -/*! - * @brief Sets the watermarks for I3C master FIFOs. - * - * @param base The I3C peripheral base address. - * @param txLvl Transmit FIFO watermark level. The #kI3C_MasterTxReadyFlag flag is set whenever - * the number of words in the transmit FIFO reaches @a txLvl. - * @param rxLvl Receive FIFO watermark level. The #kI3C_MasterRxReadyFlag flag is set whenever - * the number of words in the receive FIFO reaches @a rxLvl. - * @param flushTx true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged. - * @param flushRx true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged. - */ -static inline void I3C_MasterSetWatermarks( - I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx) -{ - base->MDATACTRL = I3C_MDATACTRL_UNLOCK_MASK | I3C_MDATACTRL_TXTRIG(txLvl) | I3C_MDATACTRL_RXTRIG(rxLvl) | - (flushTx ? I3C_MDATACTRL_FLUSHTB_MASK : 0U) | (flushRx ? I3C_MDATACTRL_FLUSHFB_MASK : 0U); -} - -/*! - * @brief Gets the current number of bytes in the I3C master FIFOs. - * - * @param base The I3C peripheral base address. - * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned. - * Pass NULL if this value is not required. - * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned. - * Pass NULL if this value is not required. - */ -static inline void I3C_MasterGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount) -{ - if (NULL != txCount) - { - *txCount = (base->MDATACTRL & I3C_MDATACTRL_TXCOUNT_MASK) >> I3C_MDATACTRL_TXCOUNT_SHIFT; - } - if (NULL != rxCount) - { - *rxCount = (base->MDATACTRL & I3C_MDATACTRL_RXCOUNT_MASK) >> I3C_MDATACTRL_RXCOUNT_SHIFT; - } -} - -/*@}*/ - -/*! @name Bus operations */ -/*@{*/ - -/*! - * @brief Sets the I3C bus frequency for master transactions. - * - * The I3C master is automatically disabled and re-enabled as necessary to configure the baud - * rate. Do not call this function during a transfer, or the transfer is aborted. - * - * @param base The I3C peripheral base address. - * @param baudRate_Hz Pointer to structure of requested bus frequency in Hertz. - * @param sourceClock_Hz I3C functional clock frequency in Hertz. - */ -void I3C_MasterSetBaudRate(I3C_Type *base, const i3c_baudrate_hz_t *baudRate_Hz, uint32_t sourceClock_Hz); - -/*! - * @brief Returns whether the bus is idle. - * - * Requires the master mode to be enabled. - * - * @param base The I3C peripheral base address. - * @retval true Bus is busy. - * @retval false Bus is idle. - */ -static inline bool I3C_MasterGetBusIdleState(I3C_Type *base) -{ - return ((base->MSTATUS & I3C_MSTATUS_STATE_MASK) == (uint32_t)kI3C_MasterStateIdle ? true : false); -} - -/*! - * @brief Sends a START signal and slave address on the I2C/I3C bus. - * - * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure - * that another master is not occupying the bus. Then a START signal is transmitted, followed by the - * 7-bit address specified in the @a address parameter. Note that this function does not actually wait - * until the START and address are successfully sent on the bus before returning. - * - * @param base The I3C peripheral base address. - * @param type The bus type to use in this transaction. - * @param address 7-bit slave device address, in bits [6:0]. - * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set - * the R/w bit (bit 0) in the transmitted slave address. - * @retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. - * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. - */ -status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir); - -/*! - * @brief Sends a repeated START signal and slave address on the I2C/I3C bus. - * - * This function is used to send a Repeated START signal when a transfer is already in progress. Like - * I3C_MasterStart(), it also sends the specified 7-bit address. - * - * @note This function exists primarily to maintain compatible APIs between I3C and I2C drivers, - * as well as to better document the intent of code that uses these APIs. - * - * @param base The I3C peripheral base address. - * @param type The bus type to use in this transaction. - * @param address 7-bit slave device address, in bits [6:0]. - * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set - * the R/w bit (bit 0) in the transmitted slave address. - * @retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. - */ -status_t I3C_MasterRepeatedStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir); - -/*! - * @brief Sends a repeated START signal and slave address on the I2C/I3C bus, receive size is also specified - * in the call. - * - * This function is used to send a Repeated START signal when a transfer is already in progress. Like - * I3C_MasterStart(), it also sends the specified 7-bit address. Call this API also configures the read - * terminate size for the following read transfer. For example, set the rxSize = 2, the following read transfer - * will be terminated after two bytes of data received. Write transfer will not be affected by the rxSize - * configuration. - * - * @note This function exists primarily to maintain compatible APIs between I3C and I2C drivers, - * as well as to better document the intent of code that uses these APIs. - * - * @param base The I3C peripheral base address. - * @param type The bus type to use in this transaction. - * @param address 7-bit slave device address, in bits [6:0]. - * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set - * the R/w bit (bit 0) in the transmitted slave address. - * @param rxSize Read terminate size for the followed read transfer, limit to 255 bytes. - * @retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. - */ -status_t I3C_MasterRepeatedStartWithRxSize( - I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize); - -/*! - * @brief Performs a polling send transfer on the I2C/I3C bus. - * - * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may - * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this - * function returns #kStatus_I3C_Nak. - * - * @param base The I3C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @param flags Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available options. - * @retval #kStatus_Success Data was sent successfully. - * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame. - * @retval #kStatus_I3C_Nak The slave device sent a NAK in response to an address. - * @retval #kStatus_I3C_WriteAbort The slave device sent a NAK in response to a write. - * @retval #kStatus_I3C_MsgError Message SDR/DDR mismatch or read/write message in wrong state. - * @retval #kStatus_I3C_WriteFifoError Write to M/SWDATAB register when FIFO full. - * @retval #kStatus_I3C_InvalidReq Invalid use of request. - */ -status_t I3C_MasterSend(I3C_Type *base, const void *txBuff, size_t txSize, uint32_t flags); - -/*! - * @brief Performs a polling receive transfer on the I2C/I3C bus. - * - * @param base The I3C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @param flags Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available options. - * @retval #kStatus_Success Data was received successfully. - * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame. - * @retval #kStatus_I3C_Term The master terminates slave read. - * @retval #kStatus_I3C_HdrParityError Parity error from DDR read. - * @retval #kStatus_I3C_CrcError CRC error from DDR read. - * @retval #kStatus_I3C_MsgError Message SDR/DDR mismatch or read/write message in wrong state. - * @retval #kStatus_I3C_ReadFifoError Read from M/SRDATAB register when FIFO empty. - * @retval #kStatus_I3C_InvalidReq Invalid use of request. - */ -status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags); - -/*! - * @brief Sends a STOP signal on the I2C/I3C bus. - * - * This function does not return until the STOP signal is seen on the bus, or an error occurs. - * - * @param base The I3C peripheral base address. - * @retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. - * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame. - * @retval #kStatus_I3C_InvalidReq Invalid use of request. - */ -status_t I3C_MasterStop(I3C_Type *base); - -/*! - * @brief I3C master emit request. - * - * @param base The I3C peripheral base address. - * @param masterReq I3C master request of type #i3c_bus_request_t - */ -void I3C_MasterEmitRequest(I3C_Type *base, i3c_bus_request_t masterReq); - -/*! - * @brief I3C master emit request. - * - * @param base The I3C peripheral base address. - * @param ibiResponse I3C master emit IBI response of type #i3c_ibi_response_t - */ -static inline void I3C_MasterEmitIBIResponse(I3C_Type *base, i3c_ibi_response_t ibiResponse) -{ - uint32_t ctrlVal = base->MCTRL; - ctrlVal &= ~(I3C_MCTRL_IBIRESP_MASK | I3C_MCTRL_REQUEST_MASK); - ctrlVal |= I3C_MCTRL_IBIRESP((uint32_t)ibiResponse) | I3C_MCTRL_REQUEST(kI3C_RequestIbiAckNack); - base->MCTRL = ctrlVal; -} - -/*! - * @brief I3C master register IBI rule. - * - * @param base The I3C peripheral base address. - * @param ibiRule Pointer to ibi rule description of type #i3c_register_ibi_addr_t - */ -void I3C_MasterRegisterIBI(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule); - -/*! - * @brief I3C master get IBI rule. - * - * @param base The I3C peripheral base address. - * @param ibiRule Pointer to store the read out ibi rule description. - */ -void I3C_MasterGetIBIRules(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule); - -/*! - * @brief Performs a DAA in the i3c bus - * - * @param base The I3C peripheral base address. - * @param addressList The pointer for address list which is used to do DAA. - * @param count The address count in the address list. - * @retval #kStatus_Success The transaction was started successfully. - * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking - * transaction is already in progress. - * @retval #kStatus_I3C_SlaveCountExceed The I3C slave count has exceed the definition in I3C_MAX_DEVCNT. - */ -status_t I3C_MasterProcessDAA(I3C_Type *base, uint8_t *addressList, uint32_t count); - -/*! - * @brief Performs a master polling transfer on the I2C/I3C bus. - * - * @note The API does not return until the transfer succeeds or fails due - * to error happens during transfer. - * - * @param base The I3C peripheral base address. - * @param transfer Pointer to the transfer structure. - * @retval #kStatus_Success Data was received successfully. - * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_I3C_IBIWon The I3C slave event IBI or MR or HJ won the arbitration on a header address. - * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame. - * @retval #kStatus_I3C_Nak The slave device sent a NAK in response to an address. - * @retval #kStatus_I3C_WriteAbort The slave device sent a NAK in response to a write. - * @retval #kStatus_I3C_Term The master terminates slave read. - * @retval #kStatus_I3C_HdrParityError Parity error from DDR read. - * @retval #kStatus_I3C_CrcError CRC error from DDR read. - * @retval #kStatus_I3C_MsgError Message SDR/DDR mismatch or read/write message in wrong state. - * @retval #kStatus_I3C_ReadFifoError Read from M/SRDATAB register when FIFO empty. - * @retval #kStatus_I3C_WriteFifoError Write to M/SWDATAB register when FIFO full. - * @retval #kStatus_I3C_InvalidReq Invalid use of request. - */ -status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *transfer); - -/*@}*/ - -/*! @name Non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the I3C master non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I3C_MasterTransferAbort() API shall be called. - * - * - * @note The function also enables the NVIC IRQ for the input I3C. Need to notice - * that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to - * enable the associated INTMUX IRQ in application. - * - * @param base The I3C peripheral base address. - * @param[out] handle Pointer to the I3C master driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void I3C_MasterTransferCreateHandle(I3C_Type *base, - i3c_master_handle_t *handle, - const i3c_master_transfer_callback_t *callback, - void *userData); - -/*! - * @brief Performs a non-blocking transaction on the I2C/I3C bus. - * - * @param base The I3C peripheral base address. - * @param handle Pointer to the I3C master driver handle. - * @param transfer The pointer to the transfer descriptor. - * @retval #kStatus_Success The transaction was started successfully. - * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking - * transaction is already in progress. - */ -status_t I3C_MasterTransferNonBlocking(I3C_Type *base, i3c_master_handle_t *handle, i3c_master_transfer_t *transfer); - -/*! - * @brief Returns number of bytes transferred so far. - * @param base The I3C peripheral base address. - * @param handle Pointer to the I3C master driver handle. - * @param[out] count Number of bytes transferred so far by the non-blocking transaction. - * @retval #kStatus_Success - * @retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. - */ -status_t I3C_MasterTransferGetCount(I3C_Type *base, i3c_master_handle_t *handle, size_t *count); - -/*! - * @brief Terminates a non-blocking I3C master transmission early. - * - * @note It is not safe to call this function from an IRQ handler that has a higher priority than the - * I3C peripheral's IRQ priority. - * - * @param base The I3C peripheral base address. - * @param handle Pointer to the I3C master driver handle. - * @retval #kStatus_Success A transaction was successfully aborted. - * @retval #kStatus_I3C_Idle There is not a non-blocking transaction currently in progress. - */ -void I3C_MasterTransferAbort(I3C_Type *base, i3c_master_handle_t *handle); - -/*@}*/ - -/*! @name IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle master interrupts. - * @note This function does not need to be called unless you are reimplementing the - * nonblocking API's interrupt handler routines to add special functionality. - * @param base The I3C peripheral base address. - * @param handle Pointer to the I3C master driver handle. - */ -void I3C_MasterTransferHandleIRQ(I3C_Type *base, i3c_master_handle_t *handle); - -/*@}*/ - -/*! @} */ - -/*! - * @addtogroup i3c_slave_driver - * @{ - */ - -/*! @name Initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the I3C slave peripheral. - * - * This function provides the following default configuration for the I3C slave peripheral: - * @code - * slaveConfig->enableslave = true; - * @endcode - * - * After calling this function, you can override any settings in order to customize the configuration, - * prior to initializing the slave driver with I3C_SlaveInit(). - * - * @param[out] slaveConfig User provided configuration structure for default values. Refer to #i3c_slave_config_t. - */ -void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig); - -/*! - * @brief Initializes the I3C slave peripheral. - * - * This function enables the peripheral clock and initializes the I3C slave peripheral as described by the user - * provided configuration. - * - * @param base The I3C peripheral base address. - * @param slaveConfig User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of - * defaults that you can override. - * @param slowClock_Hz Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values. - */ -void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz); - -/*! - * @brief Deinitializes the I3C slave peripheral. - * - * This function disables the I3C slave peripheral and gates the clock. - * - * @param base The I3C peripheral base address. - */ -void I3C_SlaveDeinit(I3C_Type *base); - -/*! - * @brief Enable/Disable Slave. - * - * @param base The I3C peripheral base address. - * @param isEnable Enable or disable. - */ -static inline void I3C_SlaveEnable(I3C_Type *base, bool isEnable) -{ - base->SCONFIG = (base->SCONFIG & ~I3C_SCONFIG_SLVENA_MASK) | I3C_SCONFIG_SLVENA(isEnable); -} - -/*@}*/ - -/*! @name Status */ -/*@{*/ - -/*! - * @brief Gets the I3C slave status flags. - * - * A bit mask with the state of all I3C slave status flags is returned. For each flag, the corresponding bit - * in the return value is set if the flag is asserted. - * - * @param base The I3C peripheral base address. - * @return State of the status flags: - * - 1: related status flag is set. - * - 0: related status flag is not set. - * @see _i3c_slave_flags - */ -static inline uint32_t I3C_SlaveGetStatusFlags(I3C_Type *base) -{ - return base->SSTATUS & ~(I3C_SSTATUS_EVDET_MASK | I3C_SSTATUS_ACTSTATE_MASK | I3C_SSTATUS_TIMECTRL_MASK); -} - -/*! - * @brief Clears the I3C slave status flag state. - * - * The following status register flags can be cleared: - * - #kI3C_SlaveBusStartFlag - * - #kI3C_SlaveMatchedFlag - * - #kI3C_SlaveBusStopFlag - * - * Attempts to clear other flags has no effect. - * - * @param base The I3C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * #_i3c_slave_flags enumerators OR'd together. You may pass the result of a previous call to - * I3C_SlaveGetStatusFlags(). - * @see _i3c_slave_flags. - */ -static inline void I3C_SlaveClearStatusFlags(I3C_Type *base, uint32_t statusMask) -{ - base->SSTATUS = statusMask; -} - -/*! - * @brief Gets the I3C slave error status flags. - * - * A bit mask with the state of all I3C slave error status flags is returned. For each flag, the corresponding bit - * in the return value is set if the flag is asserted. - * - * @param base The I3C peripheral base address. - * @return State of the error status flags: - * - 1: related status flag is set. - * - 0: related status flag is not set. - * @see _i3c_slave_error_flags - */ -static inline uint32_t I3C_SlaveGetErrorStatusFlags(I3C_Type *base) -{ - return base->SERRWARN; -} - -/*! - * @brief Clears the I3C slave error status flag state. - * - * @param base The I3C peripheral base address. - * @param statusMask A bitmask of error status flags that are to be cleared. The mask is composed of - * #_i3c_slave_error_flags enumerators OR'd together. You may pass the result of a previous call to - * I3C_SlaveGetErrorStatusFlags(). - * @see _i3c_slave_error_flags. - */ -static inline void I3C_SlaveClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask) -{ - base->SERRWARN = statusMask; -} - -/*! - * @brief Gets the I3C slave state. - * - * @param base The I3C peripheral base address. - * @return I3C slave activity state, refer #i3c_slave_activity_state_t. - */ -i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base); -/*@}*/ - -/*! @name Interrupts */ -/*@{*/ - -/*! - * @brief Enables the I3C slave interrupt requests. - * - * Only below flags can be enabled as interrupts. - * - #kI3C_SlaveBusStartFlag - * - #kI3C_SlaveMatchedFlag - * - #kI3C_SlaveBusStopFlag - * - #kI3C_SlaveRxReadyFlag - * - #kI3C_SlaveTxReadyFlag - * - #kI3C_SlaveDynamicAddrChangedFlag - * - #kI3C_SlaveReceivedCCCFlag - * - #kI3C_SlaveErrorFlag - * - #kI3C_SlaveHDRCommandMatchFlag - * - #kI3C_SlaveCCCHandledFlag - * - #kI3C_SlaveEventSentFlag - * - * @param base The I3C peripheral base address. - * @param interruptMask Bit mask of interrupts to enable. See #_i3c_slave_flags for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I3C_SlaveEnableInterrupts(I3C_Type *base, uint32_t interruptMask) -{ - base->SINTSET |= interruptMask; -} - -/*! - * @brief Disables the I3C slave interrupt requests. - * - * Only below flags can be disabled as interrupts. - * - #kI3C_SlaveBusStartFlag - * - #kI3C_SlaveMatchedFlag - * - #kI3C_SlaveBusStopFlag - * - #kI3C_SlaveRxReadyFlag - * - #kI3C_SlaveTxReadyFlag - * - #kI3C_SlaveDynamicAddrChangedFlag - * - #kI3C_SlaveReceivedCCCFlag - * - #kI3C_SlaveErrorFlag - * - #kI3C_SlaveHDRCommandMatchFlag - * - #kI3C_SlaveCCCHandledFlag - * - #kI3C_SlaveEventSentFlag - * - * @param base The I3C peripheral base address. - * @param interruptMask Bit mask of interrupts to disable. See #_i3c_slave_flags for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I3C_SlaveDisableInterrupts(I3C_Type *base, uint32_t interruptMask) -{ - base->SINTCLR = interruptMask; -} - -/*! - * @brief Returns the set of currently enabled I3C slave interrupt requests. - * - * @param base The I3C peripheral base address. - * @return A bitmask composed of #_i3c_slave_flags enumerators OR'd together to indicate the - * set of enabled interrupts. - */ -static inline uint32_t I3C_SlaveGetEnabledInterrupts(I3C_Type *base) -{ - return base->SINTSET; -} - -/*! - * @brief Returns the set of pending I3C slave interrupt requests. - * - * @param base The I3C peripheral base address. - * @return A bitmask composed of #_i3c_slave_flags enumerators OR'd together to indicate the - * set of pending interrupts. - */ -static inline uint32_t I3C_SlaveGetPendingInterrupts(I3C_Type *base) -{ - return base->SINTMASKED; -} - -/*@}*/ - -/*! @name DMA control */ -/*@{*/ - -/*! - * @brief Enables or disables I3C slave DMA requests. - * - * @param base The I3C peripheral base address. - * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable. - * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable. - * @param width DMA read/write unit in bytes. - */ -static inline void I3C_SlaveEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width) -{ - assert(width <= 2U); - base->SDMACTRL = - I3C_SDMACTRL_DMAFB(enableRx ? 2U : 0U) | I3C_SDMACTRL_DMATB(enableTx ? 2U : 0U) | I3C_SDMACTRL_DMAWIDTH(width); -} - -/*! - * @brief Gets I3C slave transmit data register address for DMA transfer. - * - * @param base The I3C peripheral base address. - * @param width DMA read/write unit in bytes. - * @return The I3C Slave Transmit Data Register address. - */ -static inline uint32_t I3C_SlaveGetTxFifoAddress(I3C_Type *base, uint32_t width) -{ - assert(width <= 2U); - return (uint32_t)((width == 2U) ? &base->SWDATAH : &base->SWDATAB); -} - -/*! - * @brief Gets I3C slave receive data register address for DMA transfer. - * - * @param base The I3C peripheral base address. - * @param width DMA read/write unit in bytes. - * @return The I3C Slave Receive Data Register address. - */ -static inline uint32_t I3C_SlaveGetRxFifoAddress(I3C_Type *base, uint32_t width) -{ - assert(width <= 2U); - return (uint32_t)((width == 2U) ? &base->SRDATAH : &base->SRDATAB); -} - -/*@}*/ - -/*! @name FIFO control */ -/*@{*/ - -/*! - * @brief Sets the watermarks for I3C slave FIFOs. - * - * @param base The I3C peripheral base address. - * @param txLvl Transmit FIFO watermark level. The #kI3C_SlaveTxReadyFlag flag is set whenever - * the number of words in the transmit FIFO reaches @a txLvl. - * @param rxLvl Receive FIFO watermark level. The #kI3C_SlaveRxReadyFlag flag is set whenever - * the number of words in the receive FIFO reaches @a rxLvl. - * @param flushTx true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged. - * @param flushRx true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged. - */ -static inline void I3C_SlaveSetWatermarks( - I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx) -{ - base->SDATACTRL = I3C_SDATACTRL_UNLOCK_MASK | I3C_SDATACTRL_TXTRIG(txLvl) | I3C_SDATACTRL_RXTRIG(rxLvl) | - (flushTx ? I3C_SDATACTRL_FLUSHTB_MASK : 0U) | (flushRx ? I3C_SDATACTRL_FLUSHFB_MASK : 0U); -} - -/*! - * @brief Gets the current number of bytes in the I3C slave FIFOs. - * - * @param base The I3C peripheral base address. - * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned. - * Pass NULL if this value is not required. - * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned. - * Pass NULL if this value is not required. - */ -static inline void I3C_SlaveGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount) -{ - if (NULL != txCount) - { - *txCount = (base->SDATACTRL & I3C_SDATACTRL_TXCOUNT_MASK) >> I3C_SDATACTRL_TXCOUNT_SHIFT; - } - if (NULL != rxCount) - { - *rxCount = (base->SDATACTRL & I3C_SDATACTRL_RXCOUNT_MASK) >> I3C_SDATACTRL_RXCOUNT_SHIFT; - } -} - -/*@}*/ - -/*! @name Bus operations */ -/*@{*/ - -/*! - * @brief I3C slave request event. - * - * @param base The I3C peripheral base address. - * @param event I3C slave event of type #i3c_slave_event_t - */ -void I3C_SlaveRequestEvent(I3C_Type *base, i3c_slave_event_t event); - -/*! - * @brief Performs a polling send transfer on the I3C bus. - * - * @param base The I3C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @return Error or success status returned by API. - */ -status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize); - -/*! - * @brief Performs a polling receive transfer on the I3C bus. - * - * @param base The I3C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @return Error or success status returned by API. - */ -status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize); - -/*@}*/ - -/*! @name Slave non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the I3C slave non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I3C_SlaveTransferAbort() API shall be called. - * - * @note The function also enables the NVIC IRQ for the input I3C. Need to notice - * that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to - * enable the associated INTMUX IRQ in application. - - * @param base The I3C peripheral base address. - * @param[out] handle Pointer to the I3C slave driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void I3C_SlaveTransferCreateHandle(I3C_Type *base, - i3c_slave_handle_t *handle, - i3c_slave_transfer_callback_t callback, - void *userData); - -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I3C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I3C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i3c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI3C_SlaveTransmitEvent and #kI3C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI3C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I3C peripheral base address. - * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state. - * @param eventMask Bit mask formed by OR'ing together #i3c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI3C_SlaveAllEvents to enable all events. - * - * @retval #kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I3C_Busy Slave transfers have already been started on this handle. - */ -status_t I3C_SlaveTransferNonBlocking(I3C_Type *base, i3c_slave_handle_t *handle, uint32_t eventMask); - -/*! - * @brief Gets the slave transfer status during a non-blocking transfer. - * @param base The I3C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure. - * @param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not - * required. - * @retval #kStatus_Success - * @retval #kStatus_NoTransferInProgress - */ -status_t I3C_SlaveTransferGetCount(I3C_Type *base, i3c_slave_handle_t *handle, size_t *count); - -/*! - * @brief Aborts the slave non-blocking transfers. - * @note This API could be called at any time to stop slave for handling the bus events. - * @param base The I3C peripheral base address. - * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state. - * @retval #kStatus_Success - * @retval #kStatus_I3C_Idle - */ -void I3C_SlaveTransferAbort(I3C_Type *base, i3c_slave_handle_t *handle); - -/*@}*/ - -/*! @name Slave IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle slave interrupts. - * @note This function does not need to be called unless you are reimplementing the - * non blocking API's interrupt handler routines to add special functionality. - * @param base The I3C peripheral base address. - * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state. - */ -void I3C_SlaveTransferHandleIRQ(I3C_Type *base, i3c_slave_handle_t *handle); - -/*! - * @brief I3C slave request IBI event with payload. - * - * @param base The I3C peripheral base address. - * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state. - * @param data Pointer to IBI data to be sent in the request. - * @param dataSize IBI data size. - */ -void I3C_SlaveRequestIBIWithData(I3C_Type *base, i3c_slave_handle_t *handle, uint8_t *data, size_t dataSize); -/*@}*/ -/*! @} */ -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I3C_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_inputmux.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_inputmux.c deleted file mode 100644 index 5ef935985fb..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_inputmux.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_inputmux.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.inputmux" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Initialize INPUTMUX peripheral. - - * This function enables the INPUTMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * - * retval None. - */ -void INPUTMUX_Init(INPUTMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE - CLOCK_EnableClock(kCLOCK_Sct); - CLOCK_EnableClock(kCLOCK_Dma); -#else - CLOCK_EnableClock(kCLOCK_InputMux); -#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Attaches a signal - * - * This function gates the INPUTPMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * param index Destination peripheral to attach the signal to. - * param connection Selects connection. - * - * retval None. - */ -void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection) -{ - uint32_t pmux_id; - uint32_t output_id; - - /* extract pmux to be used */ - pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT; - /* extract function number */ - output_id = ((uint32_t)(connection)) & ((1UL << PMUX_SHIFT) - 1U); - /* programm signal */ - *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4U)) = output_id; -} - -#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) -/*! - * brief Enable/disable a signal - * - * This function gates the INPUTPMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * param signal Enable signal register id and bit offset. - * param enable Selects enable or disable. - * - * retval None. - */ -void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable) -{ - uint32_t ena_id; - uint32_t ena_id_mask = (1UL << (32U - ENA_SHIFT)) - 1U; - uint32_t bit_offset; - -#if defined(FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX) && FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX - uint32_t chmux_offset; - uint32_t chmux_value; - - /* Only enable need to update channel mux */ - if (enable && ((((uint32_t)signal) & (1UL << CHMUX_AVL_SHIFT)) != 0U)) - { - chmux_offset = (((uint32_t)signal) >> CHMUX_OFF_SHIFT) & ((1UL << (CHMUX_AVL_SHIFT - CHMUX_OFF_SHIFT)) - 1UL); - chmux_value = (((uint32_t)signal) >> CHMUX_VAL_SHIFT) & ((1UL << (CHMUX_OFF_SHIFT - CHMUX_VAL_SHIFT)) - 1UL); - *(volatile uint32_t *)(((uint32_t)base) + chmux_offset) = chmux_value; - } - ena_id_mask = (1UL << (CHMUX_VAL_SHIFT - ENA_SHIFT)) - 1U; -#endif - /* extract enable register to be used */ - ena_id = (((uint32_t)signal) >> ENA_SHIFT) & ena_id_mask; - /* extract enable bit offset */ - bit_offset = ((uint32_t)signal) & ((1UL << ENA_SHIFT) - 1U); - /* set signal */ - if (enable) - { - *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1UL << bit_offset); - } - else - { - *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1UL << bit_offset); - } -} -#endif - -/*! - * brief Deinitialize INPUTMUX peripheral. - - * This function disables the INPUTMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * - * retval None. - */ -void INPUTMUX_Deinit(INPUTMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE - CLOCK_DisableClock(kCLOCK_Sct); - CLOCK_DisableClock(kCLOCK_Dma); -#else - CLOCK_DisableClock(kCLOCK_InputMux); -#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_inputmux.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_inputmux.h deleted file mode 100644 index ddb9e26c55f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_inputmux.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_INPUTMUX_H_ -#define _FSL_INPUTMUX_H_ - -#include "fsl_inputmux_connections.h" -#include "fsl_common.h" - -/*! - * @addtogroup inputmux_driver - * @{ - */ - -/*! @file */ -/*! @file fsl_inputmux_connections.h */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Group interrupt driver version for SDK */ -#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) -/*@}*/ - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @brief Initialize INPUTMUX peripheral. - - * This function enables the INPUTMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * - * @retval None. - */ -void INPUTMUX_Init(INPUTMUX_Type *base); - -/*! - * @brief Attaches a signal - * - * This function gates the INPUTPMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * @param index Destination peripheral to attach the signal to. - * @param connection Selects connection. - * - * @retval None. - */ -void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection); - -#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) -/*! - * @brief Enable/disable a signal - * - * This function gates the INPUTPMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * @param signal Enable signal register id and bit offset. - * @param enable Selects enable or disable. - * - * @retval None. - */ -void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable); -#endif - -/*! - * @brief Deinitialize INPUTMUX peripheral. - - * This function disables the INPUTMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * - * @retval None. - */ -void INPUTMUX_Deinit(INPUTMUX_Type *base); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_INPUTMUX_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_inputmux_connections.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_inputmux_connections.h deleted file mode 100644 index 4b6bcc93587..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_inputmux_connections.h +++ /dev/null @@ -1,2686 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_INPUTMUX_CONNECTIONS_ -#define _FSL_INPUTMUX_CONNECTIONS_ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" -#endif - -/*! - * @addtogroup inputmux_driver - * @{ - */ - -/*! - * @name Input multiplexing connections - * @{ - */ - -/*! @brief Periphinmux IDs */ -#define SCT0_INMUX0 0x00U -#define TIMER0CAPTSEL0 0x20U -#define TIMER0TRIGIN 0x30U -#define TIMER1CAPTSEL0 0x40U -#define TIMER1TRIGIN 0x50U -#define TIMER2CAPTSEL0 0x60U -#define TIMER2TRIGIN 0x70U -#define PINTSEL_PMUX_ID 0xC0U -#define PINTSEL0 0xC0U -#define DMA0_ITRIG_INMUX0 0xE0U -#define DMA0_OTRIG_INMUX0 0x160U -#define FREQMEAS_REF_REG 0x180U -#define FREQMEAS_TARGET_REG 0x184U -#define TIMER3CAPTSEL0 0x1A0U -#define TIMER3TRIGIN 0x1B0U -#define TIMER4CAPTSEL0 0x1C0U -#define TIMER4TRIGIN 0x1D0U -#define PINTSECSEL0 0x1E0U -#define DMA1_ITRIG_INMUX0 0x200U -#define DMA1_OTRIG_INMUX0 0x240U -#define HSCMP0_TRIGIN 0x260U -#define ADC0_TRIG0 0x280U -#define ADC1_TRIG0 0x2C0U -#define DAC0_TRIGIN 0x300U -#define DAC1_TRIGIN 0x320U -#define DAC2_TRIGIN 0x340U -#define ENC0TRIG 0x360U -#define ENC0HOME 0x364U -#define ENC0INDEX 0x368U -#define ENC0PHASEB 0x36CU -#define ENC0PHASEA 0x370U -#define ENC1TRIG 0x380U -#define ENC1HOME 0x384U -#define ENC1INDEX 0x388U -#define ENC1PHASEB 0x38CU -#define ENC1PHASEA 0x390U -#define PWM0_EXTSYNC0 0x3A0U -#define PWM0_EXTA0 0x3B0U -#define PWM0_EXTFORCETRIG 0x3C0U -#define PWM0_FAULT0 0x3C4U -#define PWM1_EXTSYNC0 0x3E0U -#define PWM1_EXTA0 0x3F0U -#define PWM1_EXTFORCETRIG 0x400U -#define PWM1_FAULT0 0x404U -#define PWM0_EXTCLKTRIG 0x420U -#define PWM1_EXTCLKTRIG 0x424U -#define AOI0_IN0 0x440U -#define AOI1_IN0 0x480U -#define AOI_EXT_TRIG0 0x4C0U -#define HSCMP1_TRIGIN 0x4E0U -#define HSCMP2_TRIGIN 0x500U -#define DMA0_ITRIG_INMUX_32 0x520U - -#define DMA0_REQ_EN0_ID 0x740U -#define DMA0_REQ_EN1_ID 0x744U -#define DMA1_REQ_EN_ID 0x760U -#define DMA0_ITRIG_EN0_ID 0x780U -#define DMA0_ITRIG_EN1_ID 0x784U -#define DMA1_ITRIG_EN_ID 0x7A0U -#define ENA_SHIFT 8U -#define PMUX_SHIFT 20U - -/*! @brief INPUTMUX connections type */ -typedef enum _inputmux_connection_t -{ - /*!< SCT0 INMUX. */ - kINPUTMUX_SctGpioInAToSct0 = 0U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpioInBToSct0 = 1U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpioInCToSct0 = 2U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpioInDToSct0 = 3U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpioInEToSct0 = 4U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpioInFToSct0 = 5U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpioInGToSct0 = 6U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpioInHToSct0 = 7U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToSct0 = 8U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToSct0 = 9U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToSct0 = 10U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToSct0 = 11U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToSct0 = 12U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Adc0IrqToSct0 = 13U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToSct0 = 14U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_CompOutToSct0 = 17U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedSck0ToSct0 = 18U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedSck1ToSct0 = 19U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToSct0 = 20U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToSct0 = 21U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_ArmTxevToSct0 = 22U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_DebugHaltedToSct0 = 23U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Adc1IrqToSct0 = 24U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Adc0tcomp0ToSct0 = 25U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Adc0tcomp1ToSct0 = 26U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Adc0tcomp2ToSct0 = 27U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Adc0tcomp3ToSct0 = 28U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Adc1tcomp0ToSct0 = 29U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Adc1tcomp1ToSct0 = 30U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Adc1tcomp2ToSct0 = 31U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Adc1tcomp3ToSct0 = 32U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToSct0 = 33U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToSct0 = 34U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToSct0 = 35U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig01ToSct0 = 36U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig01ToSct0 = 37U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig01ToSct0 = 38U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig01ToSct0 = 39U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig01ToSct0 = 40U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig01ToSct0 = 41U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig01ToSct0 = 42U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig01ToSct0 = 43U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToSct0 = 44U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToSct0 = 45U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToSct0 = 46U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToSct0 = 47U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToSct0 = 48U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToSct0 = 49U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToSct0 = 50U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToSct0 = 51U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToSct0 = 52U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToSct0 = 53U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Fc3SckToSct0 = 54U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Fc3RxdSdaMosiDataToSct0 = 55U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Fc3TxdSclMisoWsToSct0 = 55U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Fc3CtsDsaSsel0ToSct0 = 57U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_TmprOutToSct0 = 58U + (SCT0_INMUX0 << PMUX_SHIFT), - - /*!< TIMER0 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer0Captsel = 0U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer0Captsel = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer0Captsel = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer0Captsel = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Adc0IrqToTimer0Captsel = 25U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Adc1IrqToTimer0Captsel = 26U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToTimer0Captsel = 27U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToTimer0Captsel = 28U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToTimer0Captsel = 29U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig01ToTimer0Captsel = 30U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig01ToTimer0Captsel = 31U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig01ToTimer0Captsel = 32U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig01ToTimer0Captsel = 33U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig01ToTimer0Captsel = 34U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig01ToTimer0Captsel = 35U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig01ToTimer0Captsel = 36U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig01ToTimer0Captsel = 37U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToTimer0Captsel = 38U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToTimer0Captsel = 39U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToTimer0Captsel = 40U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToTimer0Captsel = 41U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToTimer0Captsel = 42U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToTimer0Captsel = 43U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToTimer0Captsel = 44U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToTimer0Captsel = 45U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToTimer0Captsel = 46U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToTimer0Captsel = 47U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_TmprOutToTimer0Captsel = 48U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - - /*!< TIMER0 Trigger. */ - kINPUTMUX_CtimerInp0ToTimer0Trigger = 0U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer0Trigger = 1U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer0Trigger = 2U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer0Trigger = 3U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer0Trigger = 4U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer0Trigger = 5U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer0Trigger = 6U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer0Trigger = 7U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer0Trigger = 8U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer0Trigger = 9U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer0Trigger = 10U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer0Trigger = 11U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer0Trigger = 12U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer0Trigger = 13U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer0Trigger = 14U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer0Trigger = 15U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer0Trigger = 16U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer0Trigger = 17U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer0Trigger = 18U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer0Trigger = 19U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer0Trigger = 20U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer0Trigger = 22U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer0Trigger = 23U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer0Trigger = 24U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc0IrqToTimer0Trigger = 25U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc1IrqToTimer0Trigger = 26U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToTimer0Trigger = 27U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToTimer0Trigger = 28U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToTimer0Trigger = 29U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig01ToTimer0Trigger = 30U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig01ToTimer0Trigger = 31U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig01ToTimer0Trigger = 32U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig01ToTimer0Trigger = 33U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig01ToTimer0Trigger = 34U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig01ToTimer0Trigger = 35U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig01ToTimer0Trigger = 36U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig01ToTimer0Trigger = 37U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToTimer0Trigger = 38U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToTimer0Trigger = 39U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToTimer0Trigger = 40U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToTimer0Trigger = 41U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToTimer0Trigger = 42U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToTimer0Trigger = 43U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToTimer0Trigger = 44U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToTimer0Trigger = 45U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToTimer0Trigger = 46U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToTimer0Trigger = 47U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_TmprOutToTimer0Trigger = 48U + (TIMER0TRIGIN << PMUX_SHIFT), - - /*!< TIMER1 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer1Captsel = 0U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer1Captsel = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer1Captsel = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer1Captsel = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Adc0IrqToTimer1Captsel = 25U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Adc1IrqToTimer1Captsel = 26U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToTimer1Captsel = 27U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToTimer1Captsel = 28U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToTimer1Captsel = 29U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig01ToTimer1Captsel = 30U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig01ToTimer1Captsel = 31U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig01ToTimer1Captsel = 32U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig01ToTimer1Captsel = 33U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig01ToTimer1Captsel = 34U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig01ToTimer1Captsel = 35U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig01ToTimer1Captsel = 36U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig01ToTimer1Captsel = 37U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToTimer1Captsel = 38U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToTimer1Captsel = 39U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToTimer1Captsel = 40U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToTimer1Captsel = 41U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToTimer1Captsel = 42U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToTimer1Captsel = 43U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToTimer1Captsel = 44U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToTimer1Captsel = 45U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToTimer1Captsel = 46U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToTimer1Captsel = 47U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_TmprOutToTimer1Captsel = 48U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - - /*!< TIMER1 Trigger. */ - kINPUTMUX_CtimerInp0ToTimer1Trigger = 0U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer1Trigger = 1U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer1Trigger = 2U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer1Trigger = 3U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer1Trigger = 4U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer1Trigger = 5U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer1Trigger = 6U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer1Trigger = 7U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer1Trigger = 8U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer1Trigger = 9U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer1Trigger = 10U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer1Trigger = 11U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer1Trigger = 12U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer1Trigger = 13U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer1Trigger = 14U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer1Trigger = 15U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer1Trigger = 16U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer1Trigger = 17U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer1Trigger = 18U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer1Trigger = 19U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer1Trigger = 20U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer1Trigger = 22U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer1Trigger = 23U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer1Trigger = 24U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc0IrqToTimer1Trigger = 25U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc1IrqToTimer1Trigger = 26U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToTimer1Trigger = 27U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToTimer1Trigger = 28U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToTimer1Trigger = 29U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig01ToTimer1Trigger = 30U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig01ToTimer1Trigger = 31U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig01ToTimer1Trigger = 32U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig01ToTimer1Trigger = 33U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig01ToTimer1Trigger = 34U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig01ToTimer1Trigger = 35U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig01ToTimer1Trigger = 36U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig01ToTimer1Trigger = 37U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToTimer1Trigger = 38U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToTimer1Trigger = 39U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToTimer1Trigger = 40U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToTimer1Trigger = 41U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToTimer1Trigger = 42U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToTimer1Trigger = 43U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToTimer1Trigger = 44U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToTimer1Trigger = 45U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToTimer1Trigger = 46U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToTimer1Trigger = 47U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_TmprOutToTimer1Trigger = 48U + (TIMER1TRIGIN << PMUX_SHIFT), - - /*!< TIMER2 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer2Captsel = 0U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer2Captsel = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer2Captsel = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer2Captsel = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Adc0IrqToTimer2Captsel = 25U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Adc1IrqToTimer2Captsel = 26U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToTimer2Captsel = 27U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToTimer2Captsel = 28U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToTimer2Captsel = 29U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig01ToTimer2Captsel = 30U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig01ToTimer2Captsel = 31U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig01ToTimer2Captsel = 32U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig01ToTimer2Captsel = 33U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig01ToTimer2Captsel = 34U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig01ToTimer2Captsel = 35U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig01ToTimer2Captsel = 36U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig01ToTimer2Captsel = 37U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToTimer2Captsel = 38U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToTimer2Captsel = 39U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToTimer2Captsel = 40U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToTimer2Captsel = 41U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToTimer2Captsel = 42U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToTimer2Captsel = 43U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToTimer2Captsel = 44U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToTimer2Captsel = 45U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToTimer2Captsel = 46U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToTimer2Captsel = 47U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_TmprOutToTimer2Captsel = 48U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - - /*!< TIMER2 Trigger. */ - kINPUTMUX_CtimerInp0ToTimer2Trigger = 0U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer2Trigger = 1U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer2Trigger = 2U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer2Trigger = 3U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer2Trigger = 4U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer2Trigger = 5U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer2Trigger = 6U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer2Trigger = 7U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer2Trigger = 8U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer2Trigger = 9U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer2Trigger = 10U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer2Trigger = 11U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer2Trigger = 12U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer2Trigger = 13U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer2Trigger = 14U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer2Trigger = 15U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer2Trigger = 16U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer2Trigger = 17U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer2Trigger = 18U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer2Trigger = 19U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer2Trigger = 20U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer2Trigger = 22U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer2Trigger = 23U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer2Trigger = 24U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc0IrqToTimer2Trigger = 25U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc1IrqToTimer2Trigger = 26U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToTimer2Trigger = 27U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToTimer2Trigger = 28U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToTimer2Trigger = 29U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig01ToTimer2Trigger = 30U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig01ToTimer2Trigger = 31U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig01ToTimer2Trigger = 32U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig01ToTimer2Trigger = 33U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig01ToTimer2Trigger = 34U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig01ToTimer2Trigger = 35U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig01ToTimer2Trigger = 36U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig01ToTimer2Trigger = 37U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToTimer2Trigger = 38U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToTimer2Trigger = 39U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToTimer2Trigger = 40U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToTimer2Trigger = 41U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToTimer2Trigger = 42U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToTimer2Trigger = 43U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToTimer2Trigger = 44U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToTimer2Trigger = 45U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToTimer2Trigger = 46U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToTimer2Trigger = 47U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_TmprOutToTimer2Trigger = 48U + (TIMER2TRIGIN << PMUX_SHIFT), - - /*!< Pin interrupt select. */ - kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL0 << PMUX_SHIFT), - - /*!< DMA0 Input trigger. */ - kINPUTMUX_FlexSpiRxToDma0 = 0U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_FlexSpiTxToDma0 = 1U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt0ToDma0 = 2U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt1ToDma0 = 3U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt2ToDma0 = 4U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt3ToDma0 = 5U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToDma0 = 6U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M1ToDma0 = 7U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToDma0 = 8U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M1ToDma0 = 9U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToDma0 = 10U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M1ToDma0 = 11U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToDma0 = 12U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M1ToDma0 = 13U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToDma0 = 14U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M1ToDma0 = 15U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_CompOutToDma0 = 16U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_OtrigAToDma0 = 17U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_OtrigBToDma0 = 18U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_OtrigCToDma0 = 19U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_OtrigDToDma0 = 20U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctDma0ToDma0 = 21U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctDma1ToDma0 = 22U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToDma0 = 23U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToDma0 = 24U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Hscmp0ToDma0 = 25U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Hscmp1ToDma0 = 26U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Hscmp2ToDma0 = 27U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToDma0 = 28U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToDma0 = 29U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToDma0 = 30U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToDma0 = 31U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToDma0 = 32U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToDma0 = 33U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToDma0 = 34U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToDma0 = 35U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_FlexPwm0ReqCapt0ToDma0 = 36U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_FlexPwm0ReqCapt1ToDma0 = 37U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_FlexPwm0ReqCapt2ToDma0 = 38U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_FlexPwm0ReqCapt3ToDma0 = 39U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_FlexPwm0ReqVal0ToDma0 = 40U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_FlexPwm0ReqVal1ToDma0 = 41U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_FlexPwm0ReqVal2ToDma0 = 42U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_FlexPwm0ReqVal3ToDma0 = 43U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_FlexPwm1ReqCapt0ToDma0 = 44U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_FlexPwm1ReqCapt1ToDma0 = 45U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_FlexPwm1ReqCapt2ToDma0 = 46U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_FlexPwm1ReqCapt3ToDma0 = 47U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_FlexPwm1ReqVal0ToDma0 = 48U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_FlexPwm1ReqVal1ToDma0 = 49U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_FlexPwm1ReqVal2ToDma0 = 50U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_FlexPwm1ReqVal3ToDma0 = 51U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_TmprOutToDma0 = 52U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - - /*!< DMA0 output trigger. */ - kINPUTMUX_Dma0FlexSpiRxTrigoutToTriginChannels = 0U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0FlexSpiTxTrigoutToTriginChannels = 1U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0PinInt0TrigoutToTriginChannels = 2U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0PinInt1TrigoutToTriginChannels = 3U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0PinInt2TrigoutToTriginChannels = 4U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0PinInt3TrigoutToTriginChannels = 5U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Ctimer0M0TrigoutToTriginChannels = 6U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Ctimer0M1TrigoutToTriginChannels = 7U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Ctimer1M0TrigoutToTriginChannels = 8U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Ctimer1M1TrigoutToTriginChannels = 9U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Ctimer2M0TrigoutToTriginChannels = 10U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Ctimer2M1TrigoutToTriginChannels = 11U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Ctimer3M0TrigoutToTriginChannels = 12U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Ctimer3M1TrigoutToTriginChannels = 13U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Ctimer4M0TrigoutToTriginChannels = 14U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Ctimer4M1TrigoutToTriginChannels = 15U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0CompOutTrigoutToTriginChannels = 16U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0OtrigATrigoutToTriginChannels = 17U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0OtrigBTrigoutToTriginChannels = 18U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0OtrigCTrigoutToTriginChannels = 19U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0OtrigDTrigoutToTriginChannels = 20U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0SctDma0TrigoutToTriginChannels = 21U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0SctDma1TrigoutToTriginChannels = 22U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Adc0Tcomp0TrigoutToTriginChannels = 23U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Adc1Tcomp0TrigoutToTriginChannels = 24U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Hscmp0TrigoutToTriginChannels = 25U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Hscmp1TrigoutToTriginChannels = 26U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Hscmp2TrigoutToTriginChannels = 27U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Aoi0Out0TrigoutToTriginChannels = 28U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Aoi0Out1TrigoutToTriginChannels = 29U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Aoi0Out2TrigoutToTriginChannels = 30U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Aoi0Out3TrigoutToTriginChannels = 31U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Aoi1Out0TrigoutToTriginChannels = 32U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Aoi1Out1TrigoutToTriginChannels = 33U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Aoi1Out2TrigoutToTriginChannels = 34U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Aoi1Out3TrigoutToTriginChannels = 35U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0FlexPwm0ReqCapt0TrigoutToTriginChannels = 36U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0FlexPwm0ReqCapt1TrigoutToTriginChannels = 37U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0FlexPwm0ReqCapt2TrigoutToTriginChannels = 38U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0FlexPwm0ReqCapt3TrigoutToTriginChannels = 39U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0FlexPwm0ReqVal0TrigoutToTriginChannels = 40U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0FlexPwm0ReqVal1TrigoutToTriginChannels = 41U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0FlexPwm0ReqVal2TrigoutToTriginChannels = 42U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0FlexPwm0ReqVal3TrigoutToTriginChannels = 43U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0FlexPwm1ReqCapt0TrigoutToTriginChannels = 44U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0FlexPwm1ReqCapt1TrigoutToTriginChannels = 45U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0FlexPwm1ReqCapt2TrigoutToTriginChannels = 46U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0FlexPwm1ReqCapt3TrigoutToTriginChannels = 47U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0FlexPwm1ReqVal0TrigoutToTriginChannels = 48U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0FlexPwm1ReqVal1TrigoutToTriginChannels = 49U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0FlexPwm1ReqVal2TrigoutToTriginChannels = 50U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0FlexPwm1ReqVal3TrigoutToTriginChannels = 51U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_TmprOutTrigoutToTriginChannels = 52U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - - /*!< Selection for frequency measurement reference clock. */ - kINPUTMUX_Xtal32MhzToFreqmeasRef = 0U + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_FroOsc12MhzToFreqmeasRef = 1u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_FroOsc96MhzToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_WdoscToFreqmeasRef = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_32KhzOscToFreqmeasRef = 4u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_MainSysClockToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClkAToFreqmeasRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClkBToFreqmeasRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToFreqmeasRef = 8u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToFreqmeasRef = 9u + (FREQMEAS_REF_REG << PMUX_SHIFT), - - /*!< Selection for frequency measurement target clock. */ - kINPUTMUX_Xtal32MhzToFreqmeasTarget = 0U + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_FroOsc12MhzToFreqmeasTarget = 1u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_FroOsc96MhzToFreqmeasTarget = 2u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_WdoscToFreqmeasTarget = 3u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_32KhzOscToFreqmeasTarget = 4u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_MainSysClockToFreqmeasTarget = 5u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClkAToFreqmeasTarget = 6u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClkBToFreqmeasTarget = 7u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToFreqmeasTarget = 8u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToFreqmeasTarget = 9u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - - /*!< TIMER3 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer3Captsel = 0U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer3Captsel = 17U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer3Captsel = 18U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer3Captsel = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Adc0IrqToTimer3Captsel = 25U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Adc1IrqToTimer3Captsel = 26U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToTimer3Captsel = 27U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToTimer3Captsel = 28U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToTimer3Captsel = 29U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig01ToTimer3Captsel = 30U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig01ToTimer3Captsel = 31U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig01ToTimer3Captsel = 32U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig01ToTimer3Captsel = 33U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig01ToTimer3Captsel = 34U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig01ToTimer3Captsel = 35U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig01ToTimer3Captsel = 36U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig01ToTimer3Captsel = 37U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToTimer3Captsel = 38U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToTimer3Captsel = 39U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToTimer3Captsel = 40U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToTimer3Captsel = 41U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToTimer3Captsel = 42U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToTimer3Captsel = 43U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToTimer3Captsel = 44U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToTimer3Captsel = 45U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToTimer3Captsel = 46U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToTimer3Captsel = 47U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_TmprOutToTimer3Captsel = 48U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - - /*!< TIMER3 Trigger. */ - kINPUTMUX_CtimerInp0ToTimer3Trigger = 0U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer3Trigger = 1U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer3Trigger = 2U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer3Trigger = 3U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer3Trigger = 4U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer3Trigger = 5U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer3Trigger = 6U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer3Trigger = 7U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer3Trigger = 8U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer3Trigger = 9U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer3Trigger = 10U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer3Trigger = 11U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer3Trigger = 12U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer3Trigger = 13U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer3Trigger = 14U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer3Trigger = 15U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer3Trigger = 16U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer3Trigger = 17U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer3Trigger = 18U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer3Trigger = 19U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer3Trigger = 20U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer3Trigger = 22U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer3Trigger = 23U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer3Trigger = 24U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc0IrqToTimer3Trigger = 25U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc1IrqToTimer3Trigger = 26U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToTimer3Trigger = 27U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToTimer3Trigger = 28U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToTimer3Trigger = 29U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig01ToTimer3Trigger = 30U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig01ToTimer3Trigger = 31U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig01ToTimer3Trigger = 32U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig01ToTimer3Trigger = 33U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig01ToTimer3Trigger = 34U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig01ToTimer3Trigger = 35U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig01ToTimer3Trigger = 36U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig01ToTimer3Trigger = 37U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToTimer3Trigger = 38U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToTimer3Trigger = 39U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToTimer3Trigger = 40U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToTimer3Trigger = 41U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToTimer3Trigger = 42U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToTimer3Trigger = 43U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToTimer3Trigger = 44U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToTimer3Trigger = 45U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToTimer3Trigger = 46U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToTimer3Trigger = 47U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_TmprOutToTimer3Trigger = 48U + (TIMER3TRIGIN << PMUX_SHIFT), - - /*!< Timer4 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer4Captsel = 0U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer4Captsel = 17U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer4Captsel = 18U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer4Captsel = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Adc0IrqToTimer4Captsel = 25U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Adc1IrqToTimer4Captsel = 26U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToTimer4Captsel = 27U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToTimer4Captsel = 28U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToTimer4Captsel = 29U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig01ToTimer4Captsel = 30U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig01ToTimer4Captsel = 31U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig01ToTimer4Captsel = 32U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig01ToTimer4Captsel = 33U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig01ToTimer4Captsel = 34U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig01ToTimer4Captsel = 35U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig01ToTimer4Captsel = 36U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig01ToTimer4Captsel = 37U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToTimer4Captsel = 38U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToTimer4Captsel = 39U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToTimer4Captsel = 40U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToTimer4Captsel = 41U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToTimer4Captsel = 42U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToTimer4Captsel = 43U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToTimer4Captsel = 44U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToTimer4Captsel = 45U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToTimer4Captsel = 46U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToTimer4Captsel = 47U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_TmprOutToTimer4Captsel = 48U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - - /*!< TIMER4 Trigger. */ - kINPUTMUX_CtimerInp0ToTimer4Trigger = 0U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer4Trigger = 1U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer4Trigger = 2U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer4Trigger = 3U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer4Trigger = 4U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer4Trigger = 5U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer4Trigger = 6U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer4Trigger = 7U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer4Trigger = 8U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer4Trigger = 9U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer4Trigger = 10U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer4Trigger = 11U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer4Trigger = 12U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer4Trigger = 13U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer4Trigger = 14U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer4Trigger = 15U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer4Trigger = 16U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer4Trigger = 17U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer4Trigger = 18U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer4Trigger = 19U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer4Trigger = 20U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer4Trigger = 22U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer4Trigger = 23U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer4Trigger = 24U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc0IrqToTimer4Trigger = 25U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc1IrqToTimer4Trigger = 26U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToTimer4Trigger = 27U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToTimer4Trigger = 28U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToTimer4Trigger = 29U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig01ToTimer4Trigger = 30U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig01ToTimer4Trigger = 31U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig01ToTimer4Trigger = 32U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig01ToTimer4Trigger = 33U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig01ToTimer4Trigger = 34U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig01ToTimer4Trigger = 35U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig01ToTimer4Trigger = 36U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig01ToTimer4Trigger = 37U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToTimer4Trigger = 38U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToTimer4Trigger = 39U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToTimer4Trigger = 40U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToTimer4Trigger = 41U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToTimer4Trigger = 42U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToTimer4Trigger = 43U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToTimer4Trigger = 44U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToTimer4Trigger = 45U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToTimer4Trigger = 46U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToTimer4Trigger = 47U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_TmprOutToTimer4Trigger = 48U + (TIMER4TRIGIN << PMUX_SHIFT), - - /*Pin interrupt secure select */ - kINPUTMUX_GpioPort0Pin0ToPintSecsel = 0U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin1ToPintSecsel = 1U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin2ToPintSecsel = 2U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin3ToPintSecsel = 3U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin4ToPintSecsel = 4U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin5ToPintSecsel = 5U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin6ToPintSecsel = 6U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin7ToPintSecsel = 7U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin8ToPintSecsel = 8U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin9ToPintSecsel = 9U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin10ToPintSecsel = 10U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin11ToPintSecsel = 11U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin12ToPintSecsel = 12U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin13ToPintSecsel = 13U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin14ToPintSecsel = 14U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin15ToPintSecsel = 15U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin16ToPintSecsel = 16U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin17ToPintSecsel = 17U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin18ToPintSecsel = 18U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin19ToPintSecsel = 19U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin20ToPintSecsel = 20U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin21ToPintSecsel = 21U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin22ToPintSecsel = 22U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin23ToPintSecsel = 23U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin24ToPintSecsel = 24U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin25ToPintSecsel = 25U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin26ToPintSecsel = 26U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin27ToPintSecsel = 27U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin28ToPintSecsel = 28U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin29ToPintSecsel = 29U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin30ToPintSecsel = 30U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin31ToPintSecsel = 31U + (PINTSECSEL0 << PMUX_SHIFT), - - /*!< DMA1 Input trigger. */ - kINPUTMUX_PinInt0ToDma1 = 0U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt1ToDma1 = 1U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt2ToDma1 = 2U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt3ToDma1 = 3U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToDma1 = 4U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M1ToDma1 = 5U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToDma1 = 6U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToDma1 = 7U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_OtrigAToDma1 = 8U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_OtrigBToDma1 = 9U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_OtrigCToDma1 = 10U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_OtrigDToDma1 = 11U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq0ToDma1 = 12U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq1ToDma1 = 13U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_FlexSpiRxToDma1 = 14U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_FlexSpiTxToDma1 = 15U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToDma1 = 16U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToDma1 = 17U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToDma1 = 18U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToDma1 = 19U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToDma1 = 20U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToDma1 = 21U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToDma1 = 22U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToDma1 = 23U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_TmprOutToDma1 = 24U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - - /*!< DMA1 output trigger. */ - kINPUTMUX_Dma1HsLspiRxTrigoutToTriginChannels = 2U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1HsLspiTxTrigoutToTriginChannels = 3U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcom0RxTrigoutToTriginChannels = 4U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcom0TxTrigoutToTriginChannels = 5U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcom1RxTrigoutToTriginChannels = 6U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcom1TxTrigoutToTriginChannels = 7U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcom3RxTrigoutToTriginChannels = 8U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcom3TxTrigoutToTriginChannels = 9U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Dmic0Ch0TrigoutToTriginChannels = 10U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Dmic0Ch1TrigoutToTriginChannels = 11U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1I3c0RxTrigoutToTriginChannels = 12U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1I3c0TxTrigoutToTriginChannels = 13U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - - /*!< HSCMP0 trigger. */ - kINPUTMUX_PinInt0ToHscmp0Trigger = 0U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_PinInt6ToHscmp0Trigger = 1U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_SctOut4ToHscmp0Trigger = 2U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_SctOut5ToHscmp0Trigger = 3U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_SctOut6ToHscmp0Trigger = 4U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToHscmp0Trigger = 5U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToHscmp0Trigger = 6U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToHscmp0Trigger = 7U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToHscmp0Trigger = 8U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToHscmp0Trigger = 9U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_ArmTxevToHscmp0Trigger = 11U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToHscmp0Trigger = 12U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToHscmp0Trigger = 13U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToHscmp0Trigger = 14U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig01ToHscmp0Trigger = 17U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig01ToHscmp0Trigger = 18U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig01ToHscmp0Trigger = 19U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig01ToHscmp0Trigger = 20U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig01ToHscmp0Trigger = 21U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig01ToHscmp0Trigger = 22U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig01ToHscmp0Trigger = 23U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig01ToHscmp0Trigger = 24U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToHscmp0Trigger = 25U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToHscmp0Trigger = 26U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToHscmp0Trigger = 27U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToHscmp0Trigger = 28U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToHscmp0Trigger = 29U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToHscmp0Trigger = 30U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToHscmp0Trigger = 31U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToHscmp0Trigger = 32U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToHscmp0Trigger = 33U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToHscmp0Trigger = 34U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToHscmp0Trigger = 35U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToHscmp0Trigger = 36U + (HSCMP0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToHscmp0Trigger = 37U + (HSCMP0_TRIGIN << PMUX_SHIFT), - - /*!< ADC0 trigger. */ - kINPUTMUX_PinInt0ToAdc0Trigger = 0U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_PinInt1ToAdc0Trigger = 1U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_SctOut4ToAdc0Trigger = 2U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_SctOut5ToAdc0Trigger = 3U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_SctOut9ToAdc0Trigger = 4U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToAdc0Trigger = 5U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToAdc0Trigger = 6U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToAdc0Trigger = 7U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M3ToAdc0Trigger = 8U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M3ToAdc0Trigger = 9U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_CompOutToAdc0Trigger = 10U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_ArmTxevToAdc0Trigger = 11U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToAdc0Trigger = 12U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToAdc0Trigger = 13U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToAdc0Trigger = 14U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToAdc0Trigger = 15U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToAdc0Trigger = 16U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToAdc0Trigger = 17U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToAdc0Trigger = 18U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToAdc0Trigger = 19U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToAdc0Trigger = 20U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToAdc0Trigger = 21U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToAdc0Trigger = 22U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToAdc0Trigger = 23U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig0ToAdc0Trigger = 24U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig1ToAdc0Trigger = 25U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig0ToAdc0Trigger = 26U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig1ToAdc0Trigger = 27U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig0ToAdc0Trigger = 28U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig1ToAdc0Trigger = 29U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig0ToAdc0Trigger = 30U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig1ToAdc0Trigger = 31U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig0ToAdc0Trigger = 32U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig1ToAdc0Trigger = 33U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig0ToAdc0Trigger = 34U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig1ToAdc0Trigger = 35U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig0ToAdc0Trigger = 36U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig1ToAdc0Trigger = 37U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig0ToAdc0Trigger = 38U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig1ToAdc0Trigger = 39U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToAdc0Trigger = 40U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToAdc0Trigger = 41U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToAdc0Trigger = 42U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToAdc0Trigger = 43U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToAdc0Trigger = 44U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToAdc0Trigger = 45U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToAdc0Trigger = 46U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToAdc0Trigger = 47U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToAdc0Trigger = 48U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToAdc0Trigger = 49U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToAdc0Trigger = 50U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToAdc0Trigger = 51U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToAdc0Trigger = 52U + (ADC0_TRIG0 << PMUX_SHIFT), - - /*!< ADC1 trigger. */ - kINPUTMUX_PinInt0ToAdc1Trigger = 0U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_PinInt2ToAdc1Trigger = 1U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_SctOut4ToAdc1Trigger = 2U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_SctOut5ToAdc1Trigger = 3U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_SctOut3ToAdc1Trigger = 4U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToAdc1Trigger = 5U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToAdc1Trigger = 6U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToAdc1Trigger = 7U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M2ToAdc1Trigger = 8U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M1ToAdc1Trigger = 9U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_CompOutToAdc1Trigger = 10U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_ArmTxevToAdc1Trigger = 11U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToAdc1Trigger = 12U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToAdc1Trigger = 13U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToAdc1Trigger = 14U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToAdc1Trigger = 15U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToAdc1Trigger = 16U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToAdc1Trigger = 17U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToAdc1Trigger = 18U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToAdc1Trigger = 19U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToAdc1Trigger = 20U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToAdc1Trigger = 21U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToAdc1Trigger = 22U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToAdc1Trigger = 23U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig0ToAdc1Trigger = 24U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig1ToAdc1Trigger = 25U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig0ToAdc1Trigger = 26U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig1ToAdc1Trigger = 27U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig0ToAdc1Trigger = 28U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig1ToAdc1Trigger = 29U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig0ToAdc1Trigger = 30U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig1ToAdc1Trigger = 31U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig0ToAdc1Trigger = 32U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig1ToAdc1Trigger = 33U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig0ToAdc1Trigger = 34U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig1ToAdc1Trigger = 35U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig0ToAdc1Trigger = 36U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig1ToAdc1Trigger = 37U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig0ToAdc1Trigger = 38U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig1ToAdc1Trigger = 39U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToAdc1Trigger = 40U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToAdc1Trigger = 41U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToAdc1Trigger = 42U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToAdc1Trigger = 43U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToAdc1Trigger = 44U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToAdc1Trigger = 45U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToAdc1Trigger = 46U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToAdc1Trigger = 47U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToAdc1Trigger = 48U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToAdc1Trigger = 49U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToAdc1Trigger = 50U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToAdc1Trigger = 51U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToAdc1Trigger = 52U + (ADC1_TRIG0 << PMUX_SHIFT), - - /*!< DAC0 trigger. */ - kINPUTMUX_PinInt0ToDac0Trigger = 0U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_PinInt3ToDac0Trigger = 1U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_SctOut4ToDac0Trigger = 2U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_SctOut5ToDac0Trigger = 3U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_SctOut0ToDac0Trigger = 4U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToDac0Trigger = 5U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToDac0Trigger = 6U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToDac0Trigger = 7U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToDac0Trigger = 8U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToDac0Trigger = 9U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_CompOutToDac0Trigger = 10U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_ArmTxevToDac0Trigger = 11U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToDac0Trigger = 12U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToDac0Trigger = 13U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToDac0Trigger = 14U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToDac0Trigger = 15U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToDac0Trigger = 16U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToDac0Trigger = 17U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToDac0Trigger = 18U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToDac0Trigger = 19U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToDac0Trigger = 20U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToDac0Trigger = 21U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToDac0Trigger = 22U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToDac0Trigger = 23U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToDac0Trigger = 24U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToDac0Trigger = 25U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToDac0Trigger = 26U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToDac0Trigger = 27U + (DAC0_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToDac0Trigger = 28U + (DAC0_TRIGIN << PMUX_SHIFT), - - /*!< DAC1 trigger. */ - kINPUTMUX_PinInt0ToDac1Trigger = 0U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_PinInt4ToDac1Trigger = 1U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_SctOut4ToDac1Trigger = 2U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_SctOut5ToDac1Trigger = 3U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_SctOut1ToDac1Trigger = 4U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToDac1Trigger = 5U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToDac1Trigger = 6U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToDac1Trigger = 7U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer2M1ToDac1Trigger = 8U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer3M1ToDac1Trigger = 9U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_CompOutToDac1Trigger = 10U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_ArmTxevToDac1Trigger = 11U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToDac1Trigger = 12U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToDac1Trigger = 13U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToDac1Trigger = 14U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToDac1Trigger = 15U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToDac1Trigger = 16U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToDac1Trigger = 17U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToDac1Trigger = 18U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToDac1Trigger = 19U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToDac1Trigger = 20U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToDac1Trigger = 21U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToDac1Trigger = 22U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToDac1Trigger = 23U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToDac1Trigger = 24U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToDac1Trigger = 25U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToDac1Trigger = 26U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToDac1Trigger = 27U + (DAC1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToDac1Trigger = 28U + (DAC1_TRIGIN << PMUX_SHIFT), - - /*!< DAC2 trigger. */ - kINPUTMUX_PinInt0ToDac2Trigger = 0U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_PinInt5ToDac2Trigger = 1U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_SctOut4ToDac2Trigger = 2U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_SctOut5ToDac2Trigger = 3U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_SctOut2ToDac2Trigger = 4U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToDac2Trigger = 5U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToDac2Trigger = 6U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToDac2Trigger = 7U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer2M2ToDac2Trigger = 8U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer3M2ToDac2Trigger = 9U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_CompOutToDac2Trigger = 10U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_ArmTxevToDac2Trigger = 11U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToDac2Trigger = 12U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToDac2Trigger = 13U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToDac2Trigger = 14U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToDac2Trigger = 15U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToDac2Trigger = 16U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToDac2Trigger = 17U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToDac2Trigger = 18U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToDac2Trigger = 19U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToDac2Trigger = 20U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToDac2Trigger = 21U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToDac2Trigger = 22U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToDac2Trigger = 23U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToDac2Trigger = 24U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToDac2Trigger = 25U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToDac2Trigger = 26U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToDac2Trigger = 27U + (DAC2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToDac2Trigger = 28U + (DAC2_TRIGIN << PMUX_SHIFT), - - /*!< ENC0 TRIG. */ - kINPUTMUX_PinInt0ToEnc0Trigger = 0U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_PinInt4ToEnc0Trigger = 1U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_SctOut4ToEnc0Trigger = 2U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_SctOut5ToEnc0Trigger = 3U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_SctOut1ToEnc0Trigger = 4U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToEnc0Trigger = 5U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToEnc0Trigger = 6U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToEnc0Trigger = 7U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToEnc0Trigger = 8U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToEnc0Trigger = 9U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_CompOutToEnc0Trigger = 10U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_ArmTxevToEnc0Trigger = 11U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToEnc0Trigger = 12U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToEnc0Trigger = 13U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToEnc0Trigger = 14U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToEnc0Trigger = 15U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToEnc0Trigger = 16U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToEnc0Trigger = 17U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToEnc0Trigger = 18U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToEnc0Trigger = 19U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToEnc0Trigger = 20U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToEnc0Trigger = 21U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToEnc0Trigger = 22U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToEnc0Trigger = 23U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig0ToEnc0Trigger = 24U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig1ToEnc0Trigger = 25U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig0ToEnc0Trigger = 26U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig1ToEnc0Trigger = 27U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig0ToEnc0Trigger = 28U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig1ToEnc0Trigger = 29U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig0ToEnc0Trigger = 30U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig1ToEnc0Trigger = 31U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToEnc0Trigger = 32U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToEnc0Trigger = 33U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToEnc0Trigger = 34U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToEnc0Trigger = 35U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToEnc0Trigger = 36U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToEnc0Trigger = 37U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToEnc0Trigger = 38U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToEnc0Trigger = 39U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToEnc0Trigger = 40U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToEnc0Trigger = 41U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToEnc0Trigger = 42U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToEnc0Trigger = 43U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToEnc0Trigger = 44U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToEnc0Trigger = 45U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn4ToEnc0Trigger = 46U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn5ToEnc0Trigger = 47U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn6ToEnc0Trigger = 48U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn7ToEnc0Trigger = 49U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn8ToEnc0Trigger = 50U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn9ToEnc0Trigger = 51U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToEnc0Trigger = 52U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToEnc0Trigger = 53U + (ENC0TRIG << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToEnc0Trigger = 54U + (ENC0TRIG << PMUX_SHIFT), - - /*!< ENC0 HOME. */ - kINPUTMUX_PinInt0ToEnc0Home = 0U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_PinInt4ToEnc0Home = 1U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_SctOut4ToEnc0Home = 2U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_SctOut5ToEnc0Home = 3U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_SctOut1ToEnc0Home = 4U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToEnc0Home = 5U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToEnc0Home = 6U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToEnc0Home = 7U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToEnc0Home = 8U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToEnc0Home = 9U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_CompOutToEnc0Home = 10U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_ArmTxevToEnc0Home = 11U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToEnc0Home = 12U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToEnc0Home = 13U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToEnc0Home = 14U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToEnc0Home = 15U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToEnc0Home = 16U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToEnc0Home = 17U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToEnc0Home = 18U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToEnc0Home = 19U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToEnc0Home = 20U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToEnc0Home = 21U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToEnc0Home = 22U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToEnc0Home = 23U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig0ToEnc0Home = 24U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig1ToEnc0Home = 25U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig0ToEnc0Home = 26U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig1ToEnc0Home = 27U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig0ToEnc0Home = 28U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig1ToEnc0Home = 29U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig0ToEnc0Home = 30U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig1ToEnc0Home = 31U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToEnc0Home = 32U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToEnc0Home = 33U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToEnc0Home = 34U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToEnc0Home = 35U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToEnc0Home = 36U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToEnc0Home = 37U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToEnc0Home = 38U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToEnc0Home = 39U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToEnc0Home = 40U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToEnc0Home = 41U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToEnc0Home = 42U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToEnc0Home = 43U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToEnc0Home = 44U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToEnc0Home = 45U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn4ToEnc0Home = 46U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn5ToEnc0Home = 47U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn6ToEnc0Home = 48U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn7ToEnc0Home = 49U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn8ToEnc0Home = 50U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn9ToEnc0Home = 51U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToEnc0Home = 52U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToEnc0Home = 53U + (ENC0HOME << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToEnc0Home = 54U + (ENC0HOME << PMUX_SHIFT), - - /*!< ENC0 INDEX. */ - kINPUTMUX_PinInt0ToEnc0Index = 0U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_PinInt4ToEnc0Index = 1U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_SctOut4ToEnc0Index = 2U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_SctOut5ToEnc0Index = 3U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_SctOut1ToEnc0Index = 4U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToEnc0Index = 5U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToEnc0Index = 6U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToEnc0Index = 7U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToEnc0Index = 8U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToEnc0Index = 9U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_CompOutToEnc0Index = 10U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_ArmTxevToEnc0Index = 11U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToEnc0Index = 12U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToEnc0Index = 13U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToEnc0Index = 14U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToEnc0Index = 15U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToEnc0Index = 16U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToEnc0Index = 17U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToEnc0Index = 18U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToEnc0Index = 19U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToEnc0Index = 20U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToEnc0Index = 21U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToEnc0Index = 22U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToEnc0Index = 23U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig0ToEnc0Index = 24U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig1ToEnc0Index = 25U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig0ToEnc0Index = 26U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig1ToEnc0Index = 27U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig0ToEnc0Index = 28U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig1ToEnc0Index = 29U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig0ToEnc0Index = 30U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig1ToEnc0Index = 31U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToEnc0Index = 32U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToEnc0Index = 33U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToEnc0Index = 34U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToEnc0Index = 35U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToEnc0Index = 36U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToEnc0Index = 37U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToEnc0Index = 38U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToEnc0Index = 39U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToEnc0Index = 40U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToEnc0Index = 41U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToEnc0Index = 42U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToEnc0Index = 43U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToEnc0Index = 44U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToEnc0Index = 45U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn4ToEnc0Index = 46U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn5ToEnc0Index = 47U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn6ToEnc0Index = 48U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn7ToEnc0Index = 49U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn8ToEnc0Index = 50U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn9ToEnc0Index = 51U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToEnc0Index = 52U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToEnc0Index = 53U + (ENC0INDEX << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToEnc0Index = 54U + (ENC0INDEX << PMUX_SHIFT), - - /*!< ENC0 PHASEB. */ - kINPUTMUX_PinInt0ToEnc0Phaseb = 0U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_PinInt4ToEnc0Phaseb = 1U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_SctOut4ToEnc0Phaseb = 2U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_SctOut5ToEnc0Phaseb = 3U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_SctOut1ToEnc0Phaseb = 4U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToEnc0Phaseb = 5U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToEnc0Phaseb = 6U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToEnc0Phaseb = 7U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToEnc0Phaseb = 8U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToEnc0Phaseb = 9U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_CompOutToEnc0Phaseb = 10U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_ArmTxevToEnc0Phaseb = 11U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToEnc0Phaseb = 12U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToEnc0Phaseb = 13U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToEnc0Phaseb = 14U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToEnc0Phaseb = 15U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToEnc0Phaseb = 16U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToEnc0Phaseb = 17U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToEnc0Phaseb = 18U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToEnc0Phaseb = 19U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToEnc0Phaseb = 20U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToEnc0Phaseb = 21U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToEnc0Phaseb = 22U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToEnc0Phaseb = 23U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig0ToEnc0Phaseb = 24U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig1ToEnc0Phaseb = 25U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig0ToEnc0Phaseb = 26U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig1ToEnc0Phaseb = 27U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig0ToEnc0Phaseb = 28U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig1ToEnc0Phaseb = 29U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig0ToEnc0Phaseb = 30U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig1ToEnc0Phaseb = 31U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToEnc0Phaseb = 32U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToEnc0Phaseb = 33U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToEnc0Phaseb = 34U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToEnc0Phaseb = 35U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToEnc0Phaseb = 36U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToEnc0Phaseb = 37U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToEnc0Phaseb = 38U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToEnc0Phaseb = 39U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToEnc0Phaseb = 40U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToEnc0Phaseb = 41U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToEnc0Phaseb = 42U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToEnc0Phaseb = 43U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToEnc0Phaseb = 44U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToEnc0Phaseb = 45U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn4ToEnc0Phaseb = 46U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn5ToEnc0Phaseb = 47U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn6ToEnc0Phaseb = 48U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn7ToEnc0Phaseb = 49U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn8ToEnc0Phaseb = 50U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn9ToEnc0Phaseb = 51U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToEnc0Phaseb = 52U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToEnc0Phaseb = 53U + (ENC0PHASEB << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToEnc0Phaseb = 54U + (ENC0PHASEB << PMUX_SHIFT), - - /*!< ENC0 PHASEA. */ - kINPUTMUX_PinInt0ToEnc0Phasea = 0U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_PinInt4ToEnc0Phasea = 1U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_SctOut4ToEnc0Phasea = 2U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_SctOut5ToEnc0Phasea = 3U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_SctOut1ToEnc0Phasea = 4U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToEnc0Phasea = 5U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToEnc0Phasea = 6U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToEnc0Phasea = 7U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToEnc0Phasea = 8U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToEnc0Phasea = 9U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_CompOutToEnc0Phasea = 10U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_ArmTxevToEnc0Phasea = 11U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToEnc0Phasea = 12U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToEnc0Phasea = 13U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToEnc0Phasea = 14U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToEnc0Phasea = 15U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToEnc0Phasea = 16U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToEnc0Phasea = 17U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToEnc0Phasea = 18U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToEnc0Phasea = 19U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToEnc0Phasea = 20U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToEnc0Phasea = 21U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToEnc0Phasea = 22U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToEnc0Phasea = 23U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig0ToEnc0Phasea = 24U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig1ToEnc0Phasea = 25U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig0ToEnc0Phasea = 26U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig1ToEnc0Phasea = 27U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig0ToEnc0Phasea = 28U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig1ToEnc0Phasea = 29U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig0ToEnc0Phasea = 30U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig1ToEnc0Phasea = 31U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToEnc0Phasea = 32U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToEnc0Phasea = 33U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToEnc0Phasea = 34U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToEnc0Phasea = 35U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToEnc0Phasea = 36U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToEnc0Phasea = 37U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToEnc0Phasea = 38U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToEnc0Phasea = 39U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToEnc0Phasea = 40U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToEnc0Phasea = 41U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToEnc0Phasea = 42U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToEnc0Phasea = 43U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToEnc0Phasea = 44U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToEnc0Phasea = 45U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn4ToEnc0Phasea = 46U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn5ToEnc0Phasea = 47U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn6ToEnc0Phasea = 48U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn7ToEnc0Phasea = 49U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn8ToEnc0Phasea = 50U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn9ToEnc0Phasea = 51U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToEnc0Phasea = 52U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToEnc0Phasea = 53U + (ENC0PHASEA << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToEnc0Phasea = 54U + (ENC0PHASEA << PMUX_SHIFT), - - /*!< ENC1 TRIG. */ - kINPUTMUX_PinInt0ToEnc1Trigger = 0U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_PinInt5ToEnc1Trigger = 1U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_SctOut4ToEnc1Trigger = 2U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_SctOut5ToEnc1Trigger = 3U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_SctOut7ToEnc1Trigger = 4U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToEnc1Trigger = 5U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToEnc1Trigger = 6U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToEnc1Trigger = 7U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M1ToEnc1Trigger = 8U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer3M1ToEnc1Trigger = 9U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_CompOutToEnc1Trigger = 10U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_ArmTxevToEnc1Trigger = 11U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToEnc1Trigger = 12U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToEnc1Trigger = 13U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToEnc1Trigger = 14U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToEnc1Trigger = 15U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToEnc1Trigger = 16U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToEnc1Trigger = 17U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToEnc1Trigger = 18U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToEnc1Trigger = 19U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToEnc1Trigger = 20U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToEnc1Trigger = 21U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToEnc1Trigger = 22U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToEnc1Trigger = 23U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig0ToEnc1Trigger = 24U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig1ToEnc1Trigger = 25U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig0ToEnc1Trigger = 26U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig1ToEnc1Trigger = 27U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig0ToEnc1Trigger = 28U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig1ToEnc1Trigger = 29U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig0ToEnc1Trigger = 30U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig1ToEnc1Trigger = 31U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToEnc1Trigger = 32U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToEnc1Trigger = 33U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToEnc1Trigger = 34U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToEnc1Trigger = 35U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToEnc1Trigger = 36U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToEnc1Trigger = 37U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToEnc1Trigger = 38U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToEnc1Trigger = 39U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToEnc1Trigger = 40U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToEnc1Trigger = 41U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToEnc1Trigger = 42U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToEnc1Trigger = 43U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToEnc1Trigger = 44U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToEnc1Trigger = 45U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn4ToEnc1Trigger = 46U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn5ToEnc1Trigger = 47U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn6ToEnc1Trigger = 48U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn7ToEnc1Trigger = 49U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn8ToEnc1Trigger = 50U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn9ToEnc1Trigger = 51U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToEnc1Trigger = 52U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToEnc1Trigger = 53U + (ENC1TRIG << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToEnc1Trigger = 54U + (ENC1TRIG << PMUX_SHIFT), - - /*!< ENC1 HOME. */ - kINPUTMUX_PinInt0ToEnc1Home = 0U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_PinInt5ToEnc1Home = 1U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_SctOut4ToEnc1Home = 2U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_SctOut5ToEnc1Home = 3U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_SctOut7ToEnc1Home = 4U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToEnc1Home = 5U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToEnc1Home = 6U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToEnc1Home = 7U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Ctimer1M1ToEnc1Home = 8U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Ctimer3M1ToEnc1Home = 9U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_CompOutToEnc1Home = 10U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_ArmTxevToEnc1Home = 11U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToEnc1Home = 12U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToEnc1Home = 13U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToEnc1Home = 14U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToEnc1Home = 15U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToEnc1Home = 16U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToEnc1Home = 17U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToEnc1Home = 18U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToEnc1Home = 19U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToEnc1Home = 20U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToEnc1Home = 21U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToEnc1Home = 22U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToEnc1Home = 23U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig0ToEnc1Home = 24U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig1ToEnc1Home = 25U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig0ToEnc1Home = 26U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig1ToEnc1Home = 27U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig0ToEnc1Home = 28U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig1ToEnc1Home = 29U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig0ToEnc1Home = 30U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig1ToEnc1Home = 31U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToEnc1Home = 32U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToEnc1Home = 33U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToEnc1Home = 34U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToEnc1Home = 35U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToEnc1Home = 36U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToEnc1Home = 37U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToEnc1Home = 38U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToEnc1Home = 39U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToEnc1Home = 40U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToEnc1Home = 41U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToEnc1Home = 42U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToEnc1Home = 43U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToEnc1Home = 44U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToEnc1Home = 45U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn4ToEnc1Home = 46U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn5ToEnc1Home = 47U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn6ToEnc1Home = 48U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn7ToEnc1Home = 49U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn8ToEnc1Home = 50U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn9ToEnc1Home = 51U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToEnc1Home = 52U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToEnc1Home = 53U + (ENC1HOME << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToEnc1Home = 54U + (ENC1HOME << PMUX_SHIFT), - - /*!< ENC1 INDEX. */ - kINPUTMUX_PinInt0ToEnc1Index = 0U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_PinInt5ToEnc1Index = 1U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_SctOut4ToEnc1Index = 2U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_SctOut5ToEnc1Index = 3U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_SctOut7ToEnc1Index = 4U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToEnc1Index = 5U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToEnc1Index = 6U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToEnc1Index = 7U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Ctimer1M1ToEnc1Index = 8U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Ctimer3M1ToEnc1Index = 9U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_CompOutToEnc1Index = 10U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_ArmTxevToEnc1Index = 11U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToEnc1Index = 12U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToEnc1Index = 13U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToEnc1Index = 14U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToEnc1Index = 15U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToEnc1Index = 16U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToEnc1Index = 17U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToEnc1Index = 18U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToEnc1Index = 19U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToEnc1Index = 20U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToEnc1Index = 21U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToEnc1Index = 22U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToEnc1Index = 23U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig0ToEnc1Index = 24U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig1ToEnc1Index = 25U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig0ToEnc1Index = 26U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig1ToEnc1Index = 27U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig0ToEnc1Index = 28U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig1ToEnc1Index = 29U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig0ToEnc1Index = 30U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig1ToEnc1Index = 31U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToEnc1Index = 32U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToEnc1Index = 33U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToEnc1Index = 34U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToEnc1Index = 35U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToEnc1Index = 36U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToEnc1Index = 37U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToEnc1Index = 38U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToEnc1Index = 39U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToEnc1Index = 40U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToEnc1Index = 41U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToEnc1Index = 42U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToEnc1Index = 43U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToEnc1Index = 44U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToEnc1Index = 45U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn4ToEnc1Index = 46U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn5ToEnc1Index = 47U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn6ToEnc1Index = 48U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn7ToEnc1Index = 49U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn8ToEnc1Index = 50U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn9ToEnc1Index = 51U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToEnc1Index = 52U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToEnc1Index = 53U + (ENC1INDEX << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToEnc1Index = 54U + (ENC1INDEX << PMUX_SHIFT), - - /*!< ENC1 PHASEB. */ - kINPUTMUX_PinInt0ToEnc1Phaseb = 0U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_PinInt5ToEnc1Phaseb = 1U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_SctOut4ToEnc1Phaseb = 2U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_SctOut5ToEnc1Phaseb = 3U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_SctOut7ToEnc1Phaseb = 4U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToEnc1Phaseb = 5U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToEnc1Phaseb = 6U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToEnc1Phaseb = 7U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Ctimer1M1ToEnc1Phaseb = 8U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Ctimer3M1ToEnc1Phaseb = 9U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_CompOutToEnc1Phaseb = 10U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_ArmTxevToEnc1Phaseb = 11U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToEnc1Phaseb = 12U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToEnc1Phaseb = 13U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToEnc1Phaseb = 14U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToEnc1Phaseb = 15U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToEnc1Phaseb = 16U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToEnc1Phaseb = 17U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToEnc1Phaseb = 18U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToEnc1Phaseb = 19U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToEnc1Phaseb = 20U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToEnc1Phaseb = 21U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToEnc1Phaseb = 22U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToEnc1Phaseb = 23U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig0ToEnc1Phaseb = 24U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig1ToEnc1Phaseb = 25U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig0ToEnc1Phaseb = 26U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig1ToEnc1Phaseb = 27U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig0ToEnc1Phaseb = 28U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig1ToEnc1Phaseb = 29U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig0ToEnc1Phaseb = 30U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig1ToEnc1Phaseb = 31U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToEnc1Phaseb = 32U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToEnc1Phaseb = 33U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToEnc1Phaseb = 34U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToEnc1Phaseb = 35U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToEnc1Phaseb = 36U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToEnc1Phaseb = 37U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToEnc1Phaseb = 38U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToEnc1Phaseb = 39U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToEnc1Phaseb = 40U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToEnc1Phaseb = 41U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToEnc1Phaseb = 42U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToEnc1Phaseb = 43U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToEnc1Phaseb = 44U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToEnc1Phaseb = 45U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn4ToEnc1Phaseb = 46U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn5ToEnc1Phaseb = 47U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn6ToEnc1Phaseb = 48U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn7ToEnc1Phaseb = 49U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn8ToEnc1Phaseb = 50U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn9ToEnc1Phaseb = 51U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToEnc1Phaseb = 52U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToEnc1Phaseb = 53U + (ENC1PHASEB << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToEnc1Phaseb = 54U + (ENC1PHASEB << PMUX_SHIFT), - - /*!< ENC1 PHASEA. */ - kINPUTMUX_PinInt0ToEnc1Phasea = 0U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_PinInt5ToEnc1Phasea = 1U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_SctOut4ToEnc1Phasea = 2U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_SctOut5ToEnc1Phasea = 3U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_SctOut7ToEnc1Phasea = 4U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToEnc1Phasea = 5U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToEnc1Phasea = 6U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToEnc1Phasea = 7U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Ctimer1M1ToEnc1Phasea = 8U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Ctimer3M1ToEnc1Phasea = 9U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_CompOutToEnc1Phasea = 10U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_ArmTxevToEnc1Phasea = 11U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToEnc1Phasea = 12U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToEnc1Phasea = 13U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToEnc1Phasea = 14U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToEnc1Phasea = 15U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToEnc1Phasea = 16U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToEnc1Phasea = 17U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToEnc1Phasea = 18U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToEnc1Phasea = 19U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToEnc1Phasea = 20U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToEnc1Phasea = 21U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToEnc1Phasea = 22U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToEnc1Phasea = 23U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig0ToEnc1Phasea = 24U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig1ToEnc1Phasea = 25U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig0ToEnc1Phasea = 26U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig1ToEnc1Phasea = 27U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig0ToEnc1Phasea = 28U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig1ToEnc1Phasea = 29U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig0ToEnc1Phasea = 30U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig1ToEnc1Phasea = 31U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToEnc1Phasea = 32U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToEnc1Phasea = 33U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToEnc1Phasea = 34U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToEnc1Phasea = 35U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToEnc1Phasea = 36U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToEnc1Phasea = 37U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToEnc1Phasea = 38U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToEnc1Phasea = 39U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToEnc1Phasea = 40U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToEnc1Phasea = 41U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToEnc1Phasea = 42U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToEnc1Phasea = 43U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToEnc1Phasea = 44U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToEnc1Phasea = 45U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn4ToEnc1Phasea = 46U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn5ToEnc1Phasea = 47U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn6ToEnc1Phasea = 48U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn7ToEnc1Phasea = 49U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn8ToEnc1Phasea = 50U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn9ToEnc1Phasea = 51U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToEnc1Phasea = 52U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToEnc1Phasea = 53U + (ENC1PHASEA << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToEnc1Phasea = 54U + (ENC1PHASEA << PMUX_SHIFT), - - /*!< PWM0 external synchronization trigger. */ - kINPUTMUX_PinInt0ToPwm0ExtSyncTrigger = 0U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_PinInt5ToPwm0ExtSyncTrigger = 1U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_SctOut4ToPwm0ExtSyncTrigger = 2U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_SctOut5ToPwm0ExtSyncTrigger = 3U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_SctOut2ToPwm0ExtSyncTrigger = 4U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToPwm0ExtSyncTrigger = 5U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToPwm0ExtSyncTrigger = 6U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToPwm0ExtSyncTrigger = 7U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToPwm0ExtSyncTrigger = 8U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToPwm0ExtSyncTrigger = 9U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_CompOutToPwm0ExtSyncTrigger = 10U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ArmTxevToPwm0ExtSyncTrigger = 11U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToPwm0ExtSyncTrigger = 12U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToPwm0ExtSyncTrigger = 13U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToPwm0ExtSyncTrigger = 14U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToPwm0ExtSyncTrigger = 15U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToPwm0ExtSyncTrigger = 16U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToPwm0ExtSyncTrigger = 17U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToPwm0ExtSyncTrigger = 18U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToPwm0ExtSyncTrigger = 19U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToPwm0ExtSyncTrigger = 20U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToPwm0ExtSyncTrigger = 21U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToPwm0ExtSyncTrigger = 22U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToPwm0ExtSyncTrigger = 23U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig0ToPwm0ExtSyncTrigger = 24U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig1ToPwm0ExtSyncTrigger = 25U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig0ToPwm0ExtSyncTrigger = 26U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig1ToPwm0ExtSyncTrigger = 27U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig0ToPwm0ExtSyncTrigger = 28U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig1ToPwm0ExtSyncTrigger = 29U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig0ToPwm0ExtSyncTrigger = 30U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig1ToPwm0ExtSyncTrigger = 31U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToPwm0ExtSyncTrigger = 32U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToPwm0ExtSyncTrigger = 33U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToPwm0ExtSyncTrigger = 34U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToPwm0ExtSyncTrigger = 35U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToPwm0ExtSyncTrigger = 36U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToPwm0ExtSyncTrigger = 37U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToPwm0ExtSyncTrigger = 38U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToPwm0ExtSyncTrigger = 39U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToPwm0ExtSyncTrigger = 40U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToPwm0ExtSyncTrigger = 41U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToPwm0ExtSyncTrigger = 42U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToPwm0ExtSyncTrigger = 43U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToPwm0ExtSyncTrigger = 44U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToPwm0ExtSyncTrigger = 45U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn4ToPwm0ExtSyncTrigger = 46U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn5ToPwm0ExtSyncTrigger = 47U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn6ToPwm0ExtSyncTrigger = 48U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn7ToPwm0ExtSyncTrigger = 49U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn8ToPwm0ExtSyncTrigger = 50U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn9ToPwm0ExtSyncTrigger = 51U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToPwm0ExtSyncTrigger = 52U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToPwm0ExtSyncTrigger = 53U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToPwm0ExtSyncTrigger = 54U + (PWM0_EXTSYNC0 << PMUX_SHIFT), - - /*!< PWM0 input trigger connections trigger. */ - kINPUTMUX_PinInt0ToPwm0ExtATrigger = 0U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_PinInt5ToPwm0ExtATrigger = 1U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_SctOut4ToPwm0ExtATrigger = 2U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_SctOut5ToPwm0ExtATrigger = 3U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_SctOut2ToPwm0ExtATrigger = 4U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToPwm0ExtATrigger = 5U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToPwm0ExtATrigger = 6U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToPwm0ExtATrigger = 7U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToPwm0ExtATrigger = 8U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToPwm0ExtATrigger = 9U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_CompOutToPwm0ExtATrigger = 10U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ArmTxevToPwm0ExtATrigger = 11U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToPwm0ExtATrigger = 12U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToPwm0ExtATrigger = 13U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToPwm0ExtATrigger = 14U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToPwm0ExtATrigger = 15U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToPwm0ExtATrigger = 16U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToPwm0ExtATrigger = 17U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToPwm0ExtATrigger = 18U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToPwm0ExtATrigger = 19U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToPwm0ExtATrigger = 20U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToPwm0ExtATrigger = 21U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToPwm0ExtATrigger = 22U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToPwm0ExtATrigger = 23U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig0ToPwm0ExtATrigger = 24U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig1ToPwm0ExtATrigger = 25U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig0ToPwm0ExtATrigger = 26U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig1ToPwm0ExtATrigger = 27U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig0ToPwm0ExtATrigger = 28U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig1ToPwm0ExtATrigger = 29U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig0ToPwm0ExtATrigger = 30U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig1ToPwm0ExtATrigger = 31U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToPwm0ExtATrigger = 32U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToPwm0ExtATrigger = 33U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToPwm0ExtATrigger = 34U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToPwm0ExtATrigger = 35U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToPwm0ExtATrigger = 36U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToPwm0ExtATrigger = 37U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToPwm0ExtATrigger = 38U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToPwm0ExtATrigger = 39U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToPwm0ExtATrigger = 40U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToPwm0ExtATrigger = 41U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToPwm0ExtATrigger = 42U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToPwm0ExtATrigger = 43U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToPwm0ExtATrigger = 44U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToPwm0ExtATrigger = 45U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn4ToPwm0ExtATrigger = 46U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn5ToPwm0ExtATrigger = 47U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn6ToPwm0ExtATrigger = 48U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn7ToPwm0ExtATrigger = 49U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn8ToPwm0ExtATrigger = 50U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn9ToPwm0ExtATrigger = 51U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToPwm0ExtATrigger = 52U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToPwm0ExtATrigger = 53U + (PWM0_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToPwm0ExtATrigger = 54U + (PWM0_EXTA0 << PMUX_SHIFT), - - /*!< PWM0 external force trigger connections trigger. */ - kINPUTMUX_PinInt0ToPwm0ExtForceTrigger = 0U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_PinInt5ToPwm0ExtForceTrigger = 1U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_SctOut4ToPwm0ExtForceTrigger = 2U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_SctOut5ToPwm0ExtForceTrigger = 3U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_SctOut2ToPwm0ExtForceTrigger = 4U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToPwm0ExtForceTrigger = 5U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToPwm0ExtForceTrigger = 6U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToPwm0ExtForceTrigger = 7U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToPwm0ExtForceTrigger = 8U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToPwm0ExtForceTrigger = 9U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_CompOutToPwm0ExtForceTrigger = 10U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ArmTxevToPwm0ExtForceTrigger = 11U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToPwm0ExtForceTrigger = 12U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToPwm0ExtForceTrigger = 13U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToPwm0ExtForceTrigger = 14U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToPwm0ExtForceTrigger = 15U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToPwm0ExtForceTrigger = 16U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToPwm0ExtForceTrigger = 17U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToPwm0ExtForceTrigger = 18U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToPwm0ExtForceTrigger = 19U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToPwm0ExtForceTrigger = 20U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToPwm0ExtForceTrigger = 21U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToPwm0ExtForceTrigger = 22U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToPwm0ExtForceTrigger = 23U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig0ToPwm0ExtForceTrigger = 24U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig1ToPwm0ExtForceTrigger = 25U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig0ToPwm0ExtForceTrigger = 26U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig1ToPwm0ExtForceTrigger = 27U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig0ToPwm0ExtForceTrigger = 28U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig1ToPwm0ExtForceTrigger = 29U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig0ToPwm0ExtForceTrigger = 30U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig1ToPwm0ExtForceTrigger = 31U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToPwm0ExtForceTrigger = 32U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToPwm0ExtForceTrigger = 33U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToPwm0ExtForceTrigger = 34U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToPwm0ExtForceTrigger = 35U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToPwm0ExtForceTrigger = 36U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToPwm0ExtForceTrigger = 37U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToPwm0ExtForceTrigger = 38U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToPwm0ExtForceTrigger = 39U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToPwm0ExtForceTrigger = 40U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToPwm0ExtForceTrigger = 41U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToPwm0ExtForceTrigger = 42U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToPwm0ExtForceTrigger = 43U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToPwm0ExtForceTrigger = 44U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToPwm0ExtForceTrigger = 45U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn4ToPwm0ExtForceTrigger = 46U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn5ToPwm0ExtForceTrigger = 47U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn6ToPwm0ExtForceTrigger = 48U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn7ToPwm0ExtForceTrigger = 49U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn8ToPwm0ExtForceTrigger = 50U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn9ToPwm0ExtForceTrigger = 51U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToPwm0ExtForceTrigger = 52U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToPwm0ExtForceTrigger = 53U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToPwm0ExtForceTrigger = 54U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), - - /*!< PWM0 fault input trigger connections trigger. */ - kINPUTMUX_PinInt0ToPwm0FaultTrigger = 0U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_PinInt5ToPwm0FaultTrigger = 1U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_SctOut4ToPwm0FaultTrigger = 2U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_SctOut5ToPwm0FaultTrigger = 3U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_SctOut2ToPwm0FaultTrigger = 4U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToPwm0FaultTrigger = 5U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToPwm0FaultTrigger = 6U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToPwm0FaultTrigger = 7U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToPwm0FaultTrigger = 8U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToPwm0FaultTrigger = 9U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_CompOutToPwm0FaultTrigger = 10U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ArmTxevToPwm0FaultTrigger = 11U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToPwm0FaultTrigger = 12U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToPwm0FaultTrigger = 13U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToPwm0FaultTrigger = 14U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToPwm0FaultTrigger = 15U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToPwm0FaultTrigger = 16U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToPwm0FaultTrigger = 17U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToPwm0FaultTrigger = 18U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToPwm0FaultTrigger = 19U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToPwm0FaultTrigger = 20U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToPwm0FaultTrigger = 21U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToPwm0FaultTrigger = 22U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToPwm0FaultTrigger = 23U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig0ToPwm0FaultTrigger = 24U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig1ToPwm0FaultTrigger = 25U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig0ToPwm0FaultTrigger = 26U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig1ToPwm0FaultTrigger = 27U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig0ToPwm0FaultTrigger = 28U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig1ToPwm0FaultTrigger = 29U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig0ToPwm0FaultTrigger = 30U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig1ToPwm0FaultTrigger = 31U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToPwm0FaultTrigger = 32U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToPwm0FaultTrigger = 33U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToPwm0FaultTrigger = 34U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToPwm0FaultTrigger = 35U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToPwm0FaultTrigger = 36U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToPwm0FaultTrigger = 37U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToPwm0FaultTrigger = 38U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToPwm0FaultTrigger = 39U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToPwm0FaultTrigger = 40U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToPwm0FaultTrigger = 41U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToPwm0FaultTrigger = 42U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToPwm0FaultTrigger = 43U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToPwm0FaultTrigger = 44U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToPwm0FaultTrigger = 45U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn4ToPwm0FaultTrigger = 46U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn5ToPwm0FaultTrigger = 47U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn6ToPwm0FaultTrigger = 48U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn7ToPwm0FaultTrigger = 49U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn8ToPwm0FaultTrigger = 50U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn9ToPwm0FaultTrigger = 51U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToPwm0FaultTrigger = 52U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToPwm0FaultTrigger = 53U + (PWM0_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToPwm0FaultTrigger = 54U + (PWM0_FAULT0 << PMUX_SHIFT), - - /*!< PWM0 extclk input trigger connections trigger. */ - kINPUTMUX_PinInt0ToPwm0ExtClkTrigger = 0U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_PinInt5ToPwm0ExtClkTrigger = 1U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_SctOut4ToPwm0ExtClkTrigger = 2U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_SctOut5ToPwm0ExtClkTrigger = 3U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_SctOut2ToPwm0ExtClkTrigger = 4U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToPwm0ExtClkTrigger = 5U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToPwm0ExtClkTrigger = 6U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToPwm0ExtClkTrigger = 7U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToPwm0ExtClkTrigger = 8U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToPwm0ExtClkTrigger = 9U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_CompOutToPwm0ExtClkTrigger = 10U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ArmTxevToPwm0ExtClkTrigger = 11U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToPwm0ExtClkTrigger = 12U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToPwm0ExtClkTrigger = 13U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToPwm0ExtClkTrigger = 14U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToPwm0ExtClkTrigger = 15U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToPwm0ExtClkTrigger = 16U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToPwm0ExtClkTrigger = 17U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToPwm0ExtClkTrigger = 18U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToPwm0ExtClkTrigger = 19U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToPwm0ExtClkTrigger = 20U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToPwm0ExtClkTrigger = 21U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToPwm0ExtClkTrigger = 22U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToPwm0ExtClkTrigger = 23U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig0ToPwm0ExtClkTrigger = 24U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig1ToPwm0ExtClkTrigger = 25U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig0ToPwm0ExtClkTrigger = 26U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig1ToPwm0ExtClkTrigger = 27U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig0ToPwm0ExtClkTrigger = 28U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig1ToPwm0ExtClkTrigger = 29U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig0ToPwm0ExtClkTrigger = 30U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig1ToPwm0ExtClkTrigger = 31U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToPwm0ExtClkTrigger = 32U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToPwm0ExtClkTrigger = 33U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToPwm0ExtClkTrigger = 34U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToPwm0ExtClkTrigger = 35U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToPwm0ExtClkTrigger = 36U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToPwm0ExtClkTrigger = 37U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToPwm0ExtClkTrigger = 38U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToPwm0ExtClkTrigger = 39U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToPwm0ExtClkTrigger = 40U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToPwm0ExtClkTrigger = 41U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToPwm0ExtClkTrigger = 42U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToPwm0ExtClkTrigger = 43U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToPwm0ExtClkTrigger = 44U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToPwm0ExtClkTrigger = 45U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn4ToPwm0ExtClkTrigger = 46U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn5ToPwm0ExtClkTrigger = 47U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn6ToPwm0ExtClkTrigger = 48U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn7ToPwm0ExtClkTrigger = 49U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn8ToPwm0ExtClkTrigger = 50U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn9ToPwm0ExtClkTrigger = 51U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToPwm0ExtClkTrigger = 52U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToPwm0ExtClkTrigger = 53U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToPwm0ExtClkTrigger = 54U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), - - /*!< PWM1 external synchronization trigger. */ - kINPUTMUX_PinInt0ToPwm1ExtSyncTrigger = 0U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_PinInt2ToPwm1ExtSyncTrigger = 1U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_SctOut4ToPwm1ExtSyncTrigger = 2U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_SctOut5ToPwm1ExtSyncTrigger = 3U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_SctOut3ToPwm1ExtSyncTrigger = 4U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToPwm1ExtSyncTrigger = 5U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToPwm1ExtSyncTrigger = 6U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToPwm1ExtSyncTrigger = 7U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M1ToPwm1ExtSyncTrigger = 8U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M1ToPwm1ExtSyncTrigger = 9U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_CompOutToPwm1ExtSyncTrigger = 10U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ArmTxevToPwm1ExtSyncTrigger = 11U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToPwm1ExtSyncTrigger = 12U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToPwm1ExtSyncTrigger = 13U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToPwm1ExtSyncTrigger = 14U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToPwm1ExtSyncTrigger = 15U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToPwm1ExtSyncTrigger = 16U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToPwm1ExtSyncTrigger = 17U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToPwm1ExtSyncTrigger = 18U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToPwm1ExtSyncTrigger = 19U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToPwm1ExtSyncTrigger = 20U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToPwm1ExtSyncTrigger = 21U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToPwm1ExtSyncTrigger = 22U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToPwm1ExtSyncTrigger = 23U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig0ToPwm1ExtSyncTrigger = 24U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig1ToPwm1ExtSyncTrigger = 25U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig0ToPwm1ExtSyncTrigger = 26U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig1ToPwm1ExtSyncTrigger = 27U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig0ToPwm1ExtSyncTrigger = 28U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig1ToPwm1ExtSyncTrigger = 29U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig0ToPwm1ExtSyncTrigger = 30U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig1ToPwm1ExtSyncTrigger = 31U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToPwm1ExtSyncTrigger = 32U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToPwm1ExtSyncTrigger = 33U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToPwm1ExtSyncTrigger = 34U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToPwm1ExtSyncTrigger = 35U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToPwm1ExtSyncTrigger = 36U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToPwm1ExtSyncTrigger = 37U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToPwm1ExtSyncTrigger = 38U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToPwm1ExtSyncTrigger = 39U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToPwm1ExtSyncTrigger = 40U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToPwm1ExtSyncTrigger = 41U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToPwm1ExtSyncTrigger = 42U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToPwm1ExtSyncTrigger = 43U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToPwm1ExtSyncTrigger = 44U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToPwm1ExtSyncTrigger = 45U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn4ToPwm1ExtSyncTrigger = 46U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn5ToPwm1ExtSyncTrigger = 47U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn6ToPwm1ExtSyncTrigger = 48U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn7ToPwm1ExtSyncTrigger = 49U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn8ToPwm1ExtSyncTrigger = 50U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn9ToPwm1ExtSyncTrigger = 51U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToPwm1ExtSyncTrigger = 52U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToPwm1ExtSyncTrigger = 53U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToPwm1ExtSyncTrigger = 54U + (PWM1_EXTSYNC0 << PMUX_SHIFT), - - /*!< PWM1 input trigger connections trigger. */ - kINPUTMUX_PinInt0ToPwm1ExtATrigger = 0U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_PinInt2ToPwm1ExtATrigger = 1U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_SctOut4ToPwm1ExtATrigger = 2U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_SctOut5ToPwm1ExtATrigger = 3U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_SctOut3ToPwm1ExtATrigger = 4U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToPwm1ExtATrigger = 5U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToPwm1ExtATrigger = 6U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToPwm1ExtATrigger = 7U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M1ToPwm1ExtATrigger = 8U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M1ToPwm1ExtATrigger = 9U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_CompOutToPwm1ExtATrigger = 10U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ArmTxevToPwm1ExtATrigger = 11U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToPwm1ExtATrigger = 12U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToPwm1ExtATrigger = 13U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToPwm1ExtATrigger = 14U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToPwm1ExtATrigger = 15U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToPwm1ExtATrigger = 16U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToPwm1ExtATrigger = 17U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToPwm1ExtATrigger = 18U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToPwm1ExtATrigger = 19U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToPwm1ExtATrigger = 20U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToPwm1ExtATrigger = 21U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToPwm1ExtATrigger = 22U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToPwm1ExtATrigger = 23U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig0ToPwm1ExtATrigger = 24U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig1ToPwm1ExtATrigger = 25U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig0ToPwm1ExtATrigger = 26U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig1ToPwm1ExtATrigger = 27U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig0ToPwm1ExtATrigger = 28U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig1ToPwm1ExtATrigger = 29U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig0ToPwm1ExtATrigger = 30U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig1ToPwm1ExtATrigger = 31U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToPwm1ExtATrigger = 32U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToPwm1ExtATrigger = 33U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToPwm1ExtATrigger = 34U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToPwm1ExtATrigger = 35U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToPwm1ExtATrigger = 36U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToPwm1ExtATrigger = 37U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToPwm1ExtATrigger = 38U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToPwm1ExtATrigger = 39U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToPwm1ExtATrigger = 40U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToPwm1ExtATrigger = 41U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToPwm1ExtATrigger = 42U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToPwm1ExtATrigger = 43U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToPwm1ExtATrigger = 44U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToPwm1ExtATrigger = 45U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn4ToPwm1ExtATrigger = 46U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn5ToPwm1ExtATrigger = 47U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn6ToPwm1ExtATrigger = 48U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn7ToPwm1ExtATrigger = 49U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn8ToPwm1ExtATrigger = 50U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn9ToPwm1ExtATrigger = 51U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToPwm1ExtATrigger = 52U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToPwm1ExtATrigger = 53U + (PWM1_EXTA0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToPwm1ExtATrigger = 54U + (PWM1_EXTA0 << PMUX_SHIFT), - - /*!< PWM1 external force trigger connections. */ - kINPUTMUX_PinInt0ToPwm1ExtForceTrigger = 0U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_PinInt2ToPwm1ExtForceTrigger = 1U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_SctOut4ToPwm1ExtForceTrigger = 2U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_SctOut5ToPwm1ExtForceTrigger = 3U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_SctOut3ToPwm1ExtForceTrigger = 4U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToPwm1ExtForceTrigger = 5U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToPwm1ExtForceTrigger = 6U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToPwm1ExtForceTrigger = 7U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer2M1ToPwm1ExtForceTrigger = 8U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer4M1ToPwm1ExtForceTrigger = 9U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_CompOutToPwm1ExtForceTrigger = 10U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ArmTxevToPwm1ExtForceTrigger = 11U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToPwm1ExtForceTrigger = 12U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToPwm1ExtForceTrigger = 13U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToPwm1ExtForceTrigger = 14U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToPwm1ExtForceTrigger = 15U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToPwm1ExtForceTrigger = 16U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToPwm1ExtForceTrigger = 17U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToPwm1ExtForceTrigger = 18U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToPwm1ExtForceTrigger = 19U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToPwm1ExtForceTrigger = 20U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToPwm1ExtForceTrigger = 21U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToPwm1ExtForceTrigger = 22U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToPwm1ExtForceTrigger = 23U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig0ToPwm1ExtForceTrigger = 24U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig1ToPwm1ExtForceTrigger = 25U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig0ToPwm1ExtForceTrigger = 26U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig1ToPwm1ExtForceTrigger = 27U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig0ToPwm1ExtForceTrigger = 28U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig1ToPwm1ExtForceTrigger = 29U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig0ToPwm1ExtForceTrigger = 30U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig1ToPwm1ExtForceTrigger = 31U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToPwm1ExtForceTrigger = 32U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToPwm1ExtForceTrigger = 33U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToPwm1ExtForceTrigger = 34U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToPwm1ExtForceTrigger = 35U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToPwm1ExtForceTrigger = 36U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToPwm1ExtForceTrigger = 37U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToPwm1ExtForceTrigger = 38U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToPwm1ExtForceTrigger = 39U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToPwm1ExtForceTrigger = 40U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToPwm1ExtForceTrigger = 41U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToPwm1ExtForceTrigger = 42U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToPwm1ExtForceTrigger = 43U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToPwm1ExtForceTrigger = 44U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToPwm1ExtForceTrigger = 45U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn4ToPwm1ExtForceTrigger = 46U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn5ToPwm1ExtForceTrigger = 47U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn6ToPwm1ExtForceTrigger = 48U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn7ToPwm1ExtForceTrigger = 49U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn8ToPwm1ExtForceTrigger = 50U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn9ToPwm1ExtForceTrigger = 51U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToPwm1ExtForceTrigger = 52U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToPwm1ExtForceTrigger = 53U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToPwm1ExtForceTrigger = 54U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), - - /*!< PWM1 fault input trigger connections trigger. */ - kINPUTMUX_PinInt0ToPwm1FaultTrigger = 0U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_PinInt2ToPwm1FaultTrigger = 1U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_SctOut4ToPwm1FaultTrigger = 2U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_SctOut5ToPwm1FaultTrigger = 3U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_SctOut3ToPwm1FaultTrigger = 4U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToPwm1FaultTrigger = 5U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToPwm1FaultTrigger = 6U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToPwm1FaultTrigger = 7U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M1ToPwm1FaultTrigger = 8U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M1ToPwm1FaultTrigger = 9U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_CompOutToPwm1FaultTrigger = 10U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ArmTxevToPwm1FaultTrigger = 11U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToPwm1FaultTrigger = 12U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToPwm1FaultTrigger = 13U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToPwm1FaultTrigger = 14U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToPwm1FaultTrigger = 15U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToPwm1FaultTrigger = 16U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToPwm1FaultTrigger = 17U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToPwm1FaultTrigger = 18U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToPwm1FaultTrigger = 19U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToPwm1FaultTrigger = 20U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToPwm1FaultTrigger = 21U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToPwm1FaultTrigger = 22U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToPwm1FaultTrigger = 23U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig0ToPwm1FaultTrigger = 24U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig1ToPwm1FaultTrigger = 25U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig0ToPwm1FaultTrigger = 26U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig1ToPwm1FaultTrigger = 27U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig0ToPwm1FaultTrigger = 28U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig1ToPwm1FaultTrigger = 29U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig0ToPwm1FaultTrigger = 30U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig1ToPwm1FaultTrigger = 31U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToPwm1FaultTrigger = 32U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToPwm1FaultTrigger = 33U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToPwm1FaultTrigger = 34U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToPwm1FaultTrigger = 35U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToPwm1FaultTrigger = 36U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToPwm1FaultTrigger = 37U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToPwm1FaultTrigger = 38U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToPwm1FaultTrigger = 39U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToPwm1FaultTrigger = 40U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToPwm1FaultTrigger = 41U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToPwm1FaultTrigger = 42U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToPwm1FaultTrigger = 43U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToPwm1FaultTrigger = 44U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToPwm1FaultTrigger = 45U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn4ToPwm1FaultTrigger = 46U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn5ToPwm1FaultTrigger = 47U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn6ToPwm1FaultTrigger = 48U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn7ToPwm1FaultTrigger = 49U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn8ToPwm1FaultTrigger = 50U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn9ToPwm1FaultTrigger = 51U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToPwm1FaultTrigger = 52U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToPwm1FaultTrigger = 53U + (PWM1_FAULT0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToPwm1FaultTrigger = 54U + (PWM1_FAULT0 << PMUX_SHIFT), - - /*!< PWM1 extclk input trigger connections trigger. */ - kINPUTMUX_PinInt0ToPwm1ExtClkTrigger = 0U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_PinInt2ToPwm1ExtClkTrigger = 1U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_SctOut4ToPwm1ExtClkTrigger = 2U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_SctOut5ToPwm1ExtClkTrigger = 3U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_SctOut3ToPwm1ExtClkTrigger = 4U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToPwm1ExtClkTrigger = 5U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToPwm1ExtClkTrigger = 6U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToPwm1ExtClkTrigger = 7U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer2M1ToPwm1ExtClkTrigger = 8U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Ctimer4M1ToPwm1ExtClkTrigger = 9U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_CompOutToPwm1ExtClkTrigger = 10U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ArmTxevToPwm1ExtClkTrigger = 11U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToPwm1ExtClkTrigger = 12U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToPwm1ExtClkTrigger = 13U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToPwm1ExtClkTrigger = 14U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToPwm1ExtClkTrigger = 15U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToPwm1ExtClkTrigger = 16U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToPwm1ExtClkTrigger = 17U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToPwm1ExtClkTrigger = 18U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToPwm1ExtClkTrigger = 19U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToPwm1ExtClkTrigger = 20U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToPwm1ExtClkTrigger = 21U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToPwm1ExtClkTrigger = 22U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToPwm1ExtClkTrigger = 23U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig0ToPwm1ExtClkTrigger = 24U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig1ToPwm1ExtClkTrigger = 25U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig0ToPwm1ExtClkTrigger = 26U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig1ToPwm1ExtClkTrigger = 27U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig0ToPwm1ExtClkTrigger = 28U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig1ToPwm1ExtClkTrigger = 29U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig0ToPwm1ExtClkTrigger = 30U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig1ToPwm1ExtClkTrigger = 31U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToPwm1ExtClkTrigger = 32U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToPwm1ExtClkTrigger = 33U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToPwm1ExtClkTrigger = 34U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToPwm1ExtClkTrigger = 35U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToPwm1ExtClkTrigger = 36U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToPwm1ExtClkTrigger = 37U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToPwm1ExtClkTrigger = 38U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToPwm1ExtClkTrigger = 39U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToPwm1ExtClkTrigger = 40U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToPwm1ExtClkTrigger = 41U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToPwm1ExtClkTrigger = 42U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToPwm1ExtClkTrigger = 43U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToPwm1ExtClkTrigger = 44U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToPwm1ExtClkTrigger = 45U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn4ToPwm1ExtClkTrigger = 46U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn5ToPwm1ExtClkTrigger = 47U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn6ToPwm1ExtClkTrigger = 48U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn7ToPwm1ExtClkTrigger = 49U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn8ToPwm1ExtClkTrigger = 50U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn9ToPwm1ExtClkTrigger = 51U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToPwm1ExtClkTrigger = 52U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToPwm1ExtClkTrigger = 53U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToPwm1ExtClkTrigger = 54U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), - - /*!< AOI0 trigger. */ - kINPUTMUX_PinInt0ToAoi0InTrigger = 0U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_PinInt1ToAoi0InTrigger = 1U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_SctOut0ToAoi0InTrigger = 2U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_SctOut1ToAoi0InTrigger = 3U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_SctOut2ToAoi0InTrigger = 4U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_SctOut3ToAoi0InTrigger = 5U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToAoi0InTrigger = 6U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToAoi0InTrigger = 7U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToAoi0InTrigger = 8U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M2ToAoi0InTrigger = 9U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M2ToAoi0InTrigger = 10U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M2ToAoi0InTrigger = 11U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_CompOutToAoi0InTrigger = 12U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToAoi0InTrigger = 13U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Adc0IrqToAoi0InTrigger = 14U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Adc1IrqToAoi0InTrigger = 15U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToAoi0InTrigger = 16U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToAoi0InTrigger = 17U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToAoi0InTrigger = 18U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToAoi0InTrigger = 19U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToAoi0InTrigger = 20U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToAoi0InTrigger = 21U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToAoi0InTrigger = 22U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToAoi0InTrigger = 23U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToAoi0InTrigger = 24U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToAoi0InTrigger = 25U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToAoi0InTrigger = 26U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig0ToAoi0InTrigger = 27U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig1ToAoi0InTrigger = 28U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig0ToAoi0InTrigger = 29U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig1ToAoi0InTrigger = 30U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig0ToAoi0InTrigger = 31U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig1ToAoi0InTrigger = 32U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig0ToAoi0InTrigger = 33U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig1ToAoi0InTrigger = 34U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig0ToAoi0InTrigger = 35U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig1ToAoi0InTrigger = 36U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig0ToAoi0InTrigger = 37U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig1ToAoi0InTrigger = 38U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig0ToAoi0InTrigger = 39U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig1ToAoi0InTrigger = 40U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig0ToAoi0InTrigger = 41U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig1ToAoi0InTrigger = 42U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToAoi0InTrigger = 43U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToAoi0InTrigger = 44U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToAoi0InTrigger = 45U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToAoi0InTrigger = 46U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToAoi0InTrigger = 47U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToAoi0InTrigger = 48U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToAoi0InTrigger = 51U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToAoi0InTrigger = 52U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToAoi0InTrigger = 53U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout3ToAoi0InTrigger = 54U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout4ToAoi0InTrigger = 55U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout5ToAoi0InTrigger = 56U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout6ToAoi0InTrigger = 57U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Dma1Trigout0ToAoi0InTrigger = 58U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Dma1Trigout1ToAoi0InTrigger = 59U + (AOI0_IN0 << PMUX_SHIFT), - kINPUTMUX_Dma1Trigout2ToAoi0InTrigger = 60U + (AOI0_IN0 << PMUX_SHIFT), - - /*!< AOI1 trigger. */ - kINPUTMUX_PinInt0ToAoi1InTrigger = 0U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_PinInt1ToAoi1InTrigger = 1U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_SctOut0ToAoi1InTrigger = 2U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_SctOut1ToAoi1InTrigger = 3U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_SctOut2ToAoi1InTrigger = 4U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_SctOut3ToAoi1InTrigger = 5U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToAoi1InTrigger = 6U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToAoi1InTrigger = 7U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToAoi1InTrigger = 8U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M2ToAoi1InTrigger = 9U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M2ToAoi1InTrigger = 10U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M2ToAoi1InTrigger = 11U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_CompOutToAoi1InTrigger = 12U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToAoi1InTrigger = 13U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Adc0IrqToAoi1InTrigger = 14U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Adc1IrqToAoi1InTrigger = 15U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToAoi1InTrigger = 16U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToAoi1InTrigger = 17U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToAoi1InTrigger = 18U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToAoi1InTrigger = 19U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToAoi1InTrigger = 20U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToAoi1InTrigger = 21U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToAoi1InTrigger = 22U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToAoi1InTrigger = 23U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Hscmp0OutToAoi1InTrigger = 24U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Hscmp1OutToAoi1InTrigger = 25U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Hscmp2OutToAoi1InTrigger = 26U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig0ToAoi1InTrigger = 27U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig1ToAoi1InTrigger = 28U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig0ToAoi1InTrigger = 29U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig1ToAoi1InTrigger = 30U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig0ToAoi1InTrigger = 31U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig1ToAoi1InTrigger = 32U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig0ToAoi1InTrigger = 33U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig1ToAoi1InTrigger = 34U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig0ToAoi1InTrigger = 35U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig1ToAoi1InTrigger = 36U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig0ToAoi1InTrigger = 37U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig1ToAoi1InTrigger = 38U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig0ToAoi1InTrigger = 39U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig1ToAoi1InTrigger = 40U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig0ToAoi1InTrigger = 41U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig1ToAoi1InTrigger = 42U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToAoi1InTrigger = 43U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToAoi1InTrigger = 44U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn0ToAoi1InTrigger = 45U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn1ToAoi1InTrigger = 46U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn2ToAoi1InTrigger = 47U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_ExtTrigIn3ToAoi1InTrigger = 48U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToAoi1InTrigger = 51U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToAoi1InTrigger = 52U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToAoi1InTrigger = 53U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout3ToAoi1InTrigger = 54U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout4ToAoi1InTrigger = 55U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout5ToAoi1InTrigger = 56U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout6ToAoi1InTrigger = 57U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Dma1Trigout0ToAoi1InTrigger = 58U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Dma1Trigout1ToAoi1InTrigger = 59U + (AOI1_IN0 << PMUX_SHIFT), - kINPUTMUX_Dma1Trigout2ToAoi1InTrigger = 60U + (AOI1_IN0 << PMUX_SHIFT), - - /*!< AOI External trigger. */ - kINPUTMUX_PinInt0ToAoiExtTrigger = 0U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_PinInt1ToAoiExtTrigger = 1U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Adc0IrqToAoiExtTrigger = 2U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Adc1IrqToAoiExtTrigger = 3U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToAoiExtTrigger = 4U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToAoiExtTrigger = 5U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig01ToAoiExtTrigger = 6U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig01ToAoiExtTrigger = 7U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig01ToAoiExtTrigger = 8U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig01ToAoiExtTrigger = 9U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig01ToAoiExtTrigger = 10U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig01ToAoiExtTrigger = 11U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig01ToAoiExtTrigger = 12U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig01ToAoiExtTrigger = 13U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToAoiExtTrigger = 14U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToAoiExtTrigger = 15U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToAoiExtTrigger = 16U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToAoiExtTrigger = 17U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToAoiExtTrigger = 18U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToAoiExtTrigger = 19U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToAoiExtTrigger = 20U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToAoiExtTrigger = 21U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToAoiExtTrigger = 22U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToAoiExtTrigger = 23U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - kINPUTMUX_TmprOutToAoiExtTrigger = 24U + (AOI_EXT_TRIG0 << PMUX_SHIFT), - - /*!< HSCMP1 trigger. */ - kINPUTMUX_PinInt0ToHscmp1Trigger = 0U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_PinInt7ToHscmp1Trigger = 1U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_SctOut4ToHscmp1Trigger = 2U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_SctOut5ToHscmp1Trigger = 3U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_SctOut7ToHscmp1Trigger = 4U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToHscmp1Trigger = 5U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToHscmp1Trigger = 6U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToHscmp1Trigger = 7U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer0M1ToHscmp1Trigger = 8U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer4M1ToHscmp1Trigger = 9U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_ArmTxevToHscmp1Trigger = 11U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToHscmp1Trigger = 12U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToHscmp1Trigger = 13U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToHscmp1Trigger = 14U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig01ToHscmp1Trigger = 17U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig01ToHscmp1Trigger = 18U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig01ToHscmp1Trigger = 19U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig01ToHscmp1Trigger = 20U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig01ToHscmp1Trigger = 21U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig01ToHscmp1Trigger = 22U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig01ToHscmp1Trigger = 23U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig01ToHscmp1Trigger = 24U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToHscmp1Trigger = 25U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToHscmp1Trigger = 26U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToHscmp1Trigger = 27U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToHscmp1Trigger = 28U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToHscmp1Trigger = 29U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToHscmp1Trigger = 30U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToHscmp1Trigger = 31U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToHscmp1Trigger = 32U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToHscmp1Trigger = 33U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToHscmp1Trigger = 34U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToHscmp1Trigger = 35U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToHscmp1Trigger = 36U + (HSCMP1_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToHscmp1Trigger = 37U + (HSCMP1_TRIGIN << PMUX_SHIFT), - - /*!< HSCMP2 trigger. */ - kINPUTMUX_PinInt0ToHscmp2Trigger = 0U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_PinInt4ToHscmp2Trigger = 1U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_SctOut4ToHscmp2Trigger = 2U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_SctOut5ToHscmp2Trigger = 3U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_SctOut8ToHscmp2Trigger = 4U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToHscmp2Trigger = 5U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToHscmp2Trigger = 6U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToHscmp2Trigger = 7U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer0M2ToHscmp2Trigger = 8U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Ctimer4M2ToHscmp2Trigger = 9U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_ArmTxevToHscmp2Trigger = 11U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToHscmp2Trigger = 12U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToHscmp2Trigger = 13U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToHscmp2Trigger = 14U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm0MuxTrig01ToHscmp2Trigger = 17U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm1MuxTrig01ToHscmp2Trigger = 18U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm2MuxTrig01ToHscmp2Trigger = 19U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3MuxTrig01ToHscmp2Trigger = 20U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm0MuxTrig01ToHscmp2Trigger = 21U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm1MuxTrig01ToHscmp2Trigger = 22U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm2MuxTrig01ToHscmp2Trigger = 23U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Pwm1Sm3MuxTrig01ToHscmp2Trigger = 24U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToHscmp2Trigger = 25U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToHscmp2Trigger = 26U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out0ToHscmp2Trigger = 27U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out1ToHscmp2Trigger = 28U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out2ToHscmp2Trigger = 29U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi0Out3ToHscmp2Trigger = 30U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out0ToHscmp2Trigger = 31U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out1ToHscmp2Trigger = 32U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out2ToHscmp2Trigger = 33U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Aoi1Out3ToHscmp2Trigger = 34U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout0ToHscmp2Trigger = 35U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout1ToHscmp2Trigger = 36U + (HSCMP2_TRIGIN << PMUX_SHIFT), - kINPUTMUX_Dma0Trigout2ToHscmp2Trigger = 37U + (HSCMP2_TRIGIN << PMUX_SHIFT), - -} inputmux_connection_t; - -/*! @brief INPUTMUX signal enable/disable type */ -typedef enum _inputmux_signal_t -{ - /*!< DMA0 REQ(DMA0_REQEN0) signal. */ - kINPUTMUX_FlexSpiRxToDmac0Ch0RequestEna = 0U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_FlexSpiTxToDmac0Ch1RequestEna = 1U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_PinInt0ToDmac0Ch2RequestEna = 2U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_PinInt1ToDmac0Ch3RequestEna = 3U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_PinInt2ToDmac0Ch4RequestEna = 4U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_PinInt3ToDmac0Ch5RequestEna = 5U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_Ctimer0M0ToDmac0Ch6RequestEna = 6U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_Ctimer0M1ToDmac0Ch7RequestEna = 7U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_Ctimer1M0ToDmac0Ch8RequestEna = 8U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_Ctimer1M1ToDmac0Ch9RequestEna = 9U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_Ctimer2M0ToDmac0Ch10RequestEna = 10U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_Ctimer2M1ToDmac0Ch11RequestEna = 11U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_Ctimer3M0ToDmac0Ch12RequestEna = 12U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_Ctimer3M1ToDmac0Ch13RequestEna = 13U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_Ctimer4M0ToDmac0Ch14RequestEna = 14U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_Ctimer4M1ToDmac0Ch15RequestEna = 15U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_CompOutToDmac0Ch16RequestEna = 16U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_OtrigAToDmac0Ch17RequestEna = 17U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_OtrigBToDmac0Ch18RequestEna = 18U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_OtrigCToDmac0Ch19RequestEna = 19U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_OtrigDToDmac0Ch20RequestEna = 20U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_SctDma0ToDmac0Ch21RequestEna = 21U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_SctDma1ToDmac0Ch22RequestEna = 22U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_Adc0Tcomp0ToDmac23Ch0RequestEna = 23U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_Adc1Tcomp0ToDmac24Ch0RequestEna = 24U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_Hscmp0ToDmac0Ch25RequestEna = 25U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_Hscmp1ToDmac0Ch26RequestEna = 26U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_Hscmp2ToDmac0Ch27RequestEna = 27U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_Aoi0Out0ToDmac0Ch28RequestEna = 28U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_Aoi0Out1ToDmac0Ch29RequestEna = 29U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_Aoi0Out2ToDmac0Ch30RequestEna = 30U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - kINPUTMUX_Aoi0Out3ToDmac0Ch31RequestEna = 31U + (DMA0_REQ_EN0_ID << ENA_SHIFT), - - /*!< DMA0 REQ(DMA0_REQEN0) signal. */ - kINPUTMUX_Aoi1Out0ToDmac0Ch32RequestEna = 0U + (DMA0_REQ_EN1_ID << ENA_SHIFT), - kINPUTMUX_Aoi1Out1ToDmac0Ch33RequestEna = 1U + (DMA0_REQ_EN1_ID << ENA_SHIFT), - kINPUTMUX_Aoi1Out2ToDmac0Ch34RequestEna = 2U + (DMA0_REQ_EN1_ID << ENA_SHIFT), - kINPUTMUX_Aoi1Out3ToDmac0Ch35RequestEna = 3U + (DMA0_REQ_EN1_ID << ENA_SHIFT), - kINPUTMUX_FlexPwm0ReqCapt0ToDmac0Ch36RequestEna = 4U + (DMA0_REQ_EN1_ID << ENA_SHIFT), - kINPUTMUX_FlexPwm0ReqCapt1ToDmac0Ch37RequestEna = 5U + (DMA0_REQ_EN1_ID << ENA_SHIFT), - kINPUTMUX_FlexPwm0ReqCapt2ToDmac0Ch38RequestEna = 6U + (DMA0_REQ_EN1_ID << ENA_SHIFT), - kINPUTMUX_FlexPwm0ReqCapt3ToDmac0Ch39RequestEna = 7U + (DMA0_REQ_EN1_ID << ENA_SHIFT), - kINPUTMUX_FlexPwm0ReqVal0ToDmac0Ch40RequestEna = 8U + (DMA0_REQ_EN1_ID << ENA_SHIFT), - kINPUTMUX_FlexPwm0ReqVal1ToDmac0Ch41RequestEna = 9U + (DMA0_REQ_EN1_ID << ENA_SHIFT), - kINPUTMUX_FlexPwm0ReqVal2ToDmac0Ch42RequestEna = 10U + (DMA0_REQ_EN1_ID << ENA_SHIFT), - kINPUTMUX_FlexPwm0ReqVal3ToDmac0Ch43RequestEna = 11U + (DMA0_REQ_EN1_ID << ENA_SHIFT), - kINPUTMUX_FlexPwm1ReqCapt0ToDmac0Ch44RequestEna = 12U + (DMA0_REQ_EN1_ID << ENA_SHIFT), - kINPUTMUX_FlexPwm1ReqCapt1ToDmac0Ch45RequestEna = 13U + (DMA0_REQ_EN1_ID << ENA_SHIFT), - kINPUTMUX_FlexPwm1ReqCapt2ToDmac0Ch46RequestEna = 14U + (DMA0_REQ_EN1_ID << ENA_SHIFT), - kINPUTMUX_FlexPwm1ReqCapt3ToDmac0Ch47RequestEna = 15U + (DMA0_REQ_EN1_ID << ENA_SHIFT), - kINPUTMUX_FlexPwm1ReqVal0ToDmac0Ch48RequestEna = 16U + (DMA0_REQ_EN1_ID << ENA_SHIFT), - kINPUTMUX_FlexPwm1ReqVal1ToDmac0Ch49RequestEna = 17U + (DMA0_REQ_EN1_ID << ENA_SHIFT), - kINPUTMUX_FlexPwm1ReqVal2ToDmac0Ch50RequestEna = 18U + (DMA0_REQ_EN1_ID << ENA_SHIFT), - kINPUTMUX_FlexPwm1ReqVal3ToDmac0Ch51RequestEna = 19U + (DMA0_REQ_EN1_ID << ENA_SHIFT), - kINPUTMUX_TmprOutToDmac0Ch52RequestEna = 20U + (DMA0_REQ_EN1_ID << ENA_SHIFT), - - /*!< DMA1 REQ(DMA1_REQEN) signal. */ - kINPUTMUX_HsLspiRxToDmac1Ch2RequestEna = 2U + (DMA1_REQ_EN_ID << ENA_SHIFT), - kINPUTMUX_HsLspiTxToDmac1Ch3RequestEna = 3U + (DMA1_REQ_EN_ID << ENA_SHIFT), - kINPUTMUX_Flexcom0RxToDmac1Ch4RequestEna = 4U + (DMA1_REQ_EN_ID << ENA_SHIFT), - kINPUTMUX_Flexcom0TxToDmac1Ch5RequestEna = 5U + (DMA1_REQ_EN_ID << ENA_SHIFT), - kINPUTMUX_Flexcom1RxToDmac1Ch6RequestEna = 6U + (DMA1_REQ_EN_ID << ENA_SHIFT), - kINPUTMUX_Flexcom1TxToDmac1Ch7RequestEna = 7U + (DMA1_REQ_EN_ID << ENA_SHIFT), - kINPUTMUX_Flexcom3RxToDmac1Ch8RequestEna = 8U + (DMA1_REQ_EN_ID << ENA_SHIFT), - kINPUTMUX_Flexcom3TxToDmac1Ch9RequestEna = 9U + (DMA1_REQ_EN_ID << ENA_SHIFT), - kINPUTMUX_Dmic0Ch0ToDmac1Ch10RequestEna = 10U + (DMA1_REQ_EN_ID << ENA_SHIFT), - kINPUTMUX_Dmic0Ch1ToDmac1Ch11RequestEna = 11U + (DMA1_REQ_EN_ID << ENA_SHIFT), - kINPUTMUX_I3c0RxToDmac1Ch12RequestEna = 12U + (DMA1_REQ_EN_ID << ENA_SHIFT), - kINPUTMUX_I3c0TxToDmac1Ch13RequestEna = 13U + (DMA1_REQ_EN_ID << ENA_SHIFT), - - /*!< DMA0 input trigger(DMA0_ITRIGEN0) source enable. */ - kINPUTMUX_Dmac0InputTriggerFlexSpiRxEna = 0U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerFlexSpiTxEna = 1U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerPinInt0Ena = 2U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerPinInt1Ena = 3U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerPinInt2Ena = 4U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerPinInt3Ena = 5U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer0M0Ena = 6U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer0M1Ena = 7U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer1M0Ena = 8U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer1M1Ena = 9U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer2M0Ena = 10U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer2M1Ena = 11U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer3M0Ena = 12U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer3M1Ena = 13U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer4M0Ena = 14U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer4M1Ena = 15U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCompOutEna = 16U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerOtrigAEna = 17U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerOtrigBEna = 18U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerOtrigCEna = 19U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerOtrigDEna = 20U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerSctDma0Ena = 21U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerSctDma1Ena = 22U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerAdc0Tcomp0Ena = 23U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerAdc1Tcomp0Ena = 24U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerHscmp0Ena = 25U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerHscmp1Ena = 26U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerHscmp2Ena = 27U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerAoi0Out0Ena = 28U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerAoi0Out1Ena = 29U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerAoi0Out2Ena = 30U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerAoi0Out3Ena = 31U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), - - /*!< DMA0 input trigger(DMA0_ITRIGEN1) source enable. */ - kINPUTMUX_Dmac0InputTriggerAoi1Out0Ena = 0U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerAoi1Out1Ena = 1U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerAoi1Out2Ena = 2U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerAoi1Out3Ena = 3U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerFlexPwm0ReqCapt0Ena = 4U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerFlexPwm0ReqCapt1Ena = 5U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerFlexPwm0ReqCapt2Ena = 6U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerFlexPwm0ReqCapt3Ena = 7U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerFlexPwm0ReqVal0Ena = 8U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerFlexPwm0ReqVal1Ena = 9U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerFlexPwm0ReqVal2Ena = 10U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerFlexPwm0ReqVal3Ena = 11U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerFlexPwm1ReqCapt0Ena = 12U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerFlexPwm1ReqCapt1Ena = 13U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerFlexPwm1ReqCapt2Ena = 14U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerFlexPwm1ReqCapt3Ena = 15U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerFlexPwm1ReqVal0Ena = 16U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerFlexPwm1ReqVal1Ena = 17U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerFlexPwm1ReqVal2Ena = 18U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerFlexPwm1ReqVal3Ena = 19U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerTmprOutEna = 20U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), - - /*!< DMA1 input trigger(DMA1_ITRIGEN) source enable. */ - kINPUTMUX_Dmac1InputTriggerHsLspiRxEna = 2U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerHsLspiTxEna = 3U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerFlexcom0RxEna = 4U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerFlexcom0TxEna = 5U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerFlexcom1RxEna = 6U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerFlexcom1TxEna = 7U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerFlexcom3RxEna = 8U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerFlexcom3TxEna = 9U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerDmic0Ch0Ena = 10U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerDmic0Ch1Ena = 11U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerI3c0RxEna = 12U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerI3c0TxEna = 13U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), -} inputmux_signal_t; - -/*@}*/ - -/*@}*/ - -#endif /* _FSL_INPUTMUX_CONNECTIONS_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_iocon.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_iocon.h deleted file mode 100644 index e705e91f66c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_iocon.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_IOCON_H_ -#define _FSL_IOCON_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_iocon - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon" -#endif - -/*! @name Driver version */ -/*@{*/ -/*! @brief IOCON driver version. */ -#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) -/*@}*/ - -/** - * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format - */ -typedef struct _iocon_group -{ - uint8_t port; /* Pin port */ - uint8_t pin; /* Pin number */ - uint8_t ionumber; /* IO number */ - uint16_t modefunc; /* Function and mode */ -} iocon_group_t; - -/** - * @brief IOCON function and mode selection definitions - * @note See the User Manual for specific modes and functions supported by the various pins. - */ -#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ -#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ -#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ -#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ -#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ -#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ -#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ -#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ -#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) -#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ -#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ -#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ -#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ -#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ -#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ -#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ -#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ -#endif /* FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH */ - -#if defined(IOCON_PIO_MODE_SHIFT) -#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ -#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ -#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ -#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ -#endif - -#if defined(IOCON_PIO_I2CSLEW_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_MODE (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ -#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */ -#endif - -#if defined(IOCON_PIO_EGP_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_MODE (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ -#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */ -#endif - -#if defined(IOCON_PIO_SLEW_SHIFT) -#define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ -#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ -#endif - -#if defined(IOCON_PIO_INVERT_SHIFT) -#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */ -#endif - -#if defined(IOCON_PIO_DIGIMODE_SHIFT) -#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */ -#define IOCON_DIGITAL_EN \ - (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */ -#endif - -#if defined(IOCON_PIO_FILTEROFF_SHIFT) -#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ -#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ -#endif - -#if defined(IOCON_PIO_I2CDRIVE_SHIFT) -#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ -#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ -#endif - -#if defined(IOCON_PIO_OD_SHIFT) -#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */ -#endif - -#if defined(IOCON_PIO_I2CFILTER_SHIFT) -#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ -#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */ -#endif - -#if defined(IOCON_PIO_ASW_SHIFT) -#define IOCON_AWS_EN (0x1 << IOCON_PIO_ASW_SHIFT) /*!< Enables analog switch function */ -#endif - -#if defined(IOCON_PIO_SSEL_SHIFT) -#define IOCON_SSEL_3V3 (0x0 << IOCON_PIO_SSEL_SHIFT) /*!< 3V3 signaling in I2C mode */ -#define IOCON_SSEL_1V8 (0x1 << IOCON_PIO_SSEL_SHIFT) /*!< 1V8 signaling in I2C mode */ -#endif - -#if defined(IOCON_PIO_ECS_SHIFT) -#define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */ -#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */ -#endif - -#if defined(IOCON_PIO_S_MODE_SHIFT) -#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ -#define IOCON_S_MODE_1CLK \ - (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_2CLK \ - (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_3CLK \ - (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ -#endif - -#if defined(IOCON_PIO_CLK_DIV_SHIFT) -#define IOCON_CLKDIV(div) \ - ((div) \ - << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ -#endif - -#if defined(__cplusplus) -extern "C" { -#endif - -#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) -/** - * @brief Sets I/O Control pin mux - * @param base : The base of IOCON peripheral on the chip - * @param ionumber : GPIO number to mux - * @param modefunc : OR'ed values of type IOCON_* - * @return Nothing - */ -__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc) -{ - base->PIO[ionumber] = modefunc; -} -#else -/** - * @brief Sets I/O Control pin mux - * @param base : The base of IOCON peripheral on the chip - * @param port : GPIO port to mux - * @param pin : GPIO pin to mux - * @param modefunc : OR'ed values of type IOCON_* - * @return Nothing - */ -__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc) -{ - base->PIO[port][pin] = modefunc; -} -#endif - -/** - * @brief Set all I/O Control pin muxing - * @param base : The base of IOCON peripheral on the chip - * @param pinArray : Pointer to array of pin mux selections - * @param arrayLength : Number of entries in pinArray - * @return Nothing - */ -__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength) -{ - uint32_t i; - - for (i = 0; i < arrayLength; i++) - { -#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) - IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc); -#else - IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc); -#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */ - } -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_IOCON_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_irtc.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_irtc.c deleted file mode 100644 index 8c194af9329..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_irtc.c +++ /dev/null @@ -1,655 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_irtc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.irtc" -#endif - -#define IRTC_BASE_YEAR (2112U) -#define YEAR_RANGE_START (1984U) /* Valid values for year range from -128 to 127; 2112 - 128 */ -#define YEAR_RANGE_END (2239U) /* Valid values for year range from -128 to 127; 2112 + 127 */ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Checks whether the date and time passed in is valid - * - * @param datetime Pointer to structure where the date and time details are stored - * - * @return Returns false if the date & time details are out of range; true if in range - */ -static bool IRTC_CheckDatetimeFormat(const irtc_datetime_t *datetime); - -/******************************************************************************* - * Code - ******************************************************************************/ -static bool IRTC_CheckDatetimeFormat(const irtc_datetime_t *datetime) -{ - assert(NULL != datetime); - - bool fgRet = true; - - /* Table of days in a month for a non leap year */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Check year, month, hour, minute, seconds */ - if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || - (datetime->month < 1U) || (datetime->weekDay >= 7U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || - (datetime->second >= 60U)) - { - /* If not correct then error*/ - fgRet = false; - } - else - { - /* Adjust the days in February for a leap year */ - if (((0U == (datetime->year & 3U)) && (0U != (datetime->year % 100U))) || (0U == (datetime->year % 400U))) - { - daysPerMonth[2] = 29U; - } - - /* Check the validity of the day */ - if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) - { - fgRet = false; - } - } - return fgRet; -} - -/*! - * brief Ungates the IRTC clock and configures the peripheral for basic operation. - * - * This function initiates a soft-reset of the IRTC module, this has not effect on DST, - * calendaring, standby time and tamper detect registers. - * - * note This API should be called at the beginning of the application using the IRTC driver. - * - * param base IRTC peripheral base address - * param config Pointer to user's IRTC config structure. - * - * return kStatus_Fail if we cannot disable register write protection - */ -status_t IRTC_Init(RTC_Type *base, const irtc_config_t *config) -{ - assert(NULL != config); - - uint16_t reg; - status_t status = kStatus_Success; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Rtc0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if defined(FSL_FEATURE_RTC_HAS_RESET) && FSL_FEATURE_RTC_HAS_RESET - RESET_PeripheralReset(kRTC_RST_SHIFT_RSTn); -#endif - - /* Unlock to allow register write operation */ - if (kStatus_Success == IRTC_SetWriteProtection(base, false)) - { - /* Issue a software reset */ - IRTC_Reset(base); - -#if !defined(FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) || (!FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) - /* Setup the wakeup pin select */ - if (config->wakeupSelect) - { - base->CTRL2 |= RTC_CTRL2_WAKEUP_MODE_MASK; - } - else - { - base->CTRL2 &= ~(uint16_t)RTC_CTRL2_WAKEUP_MODE_MASK; - } -#endif - /* Setup alarm match operation and sampling clock operation in standby mode */ - reg = base->CTRL; - reg &= ~((uint16_t)RTC_CTRL_TIMER_STB_MASK_MASK | (uint16_t)RTC_CTRL_ALM_MATCH_MASK); - reg |= (RTC_CTRL_TIMER_STB_MASK(config->timerStdMask) | RTC_CTRL_ALM_MATCH(config->alrmMatch)); - base->CTRL = reg; - } - else - { - status = kStatus_Fail; - } - - return status; -} - -/*! - * brief Fill in the IRTC config struct with the default settings - * - * The default values are: - * code - * config->wakeupSelect = true; - * config->timerStdMask = false; - * config->alrmMatch = kRTC_MatchSecMinHr; - * endcode - * param config Pointer to user's IRTC config structure. - */ -void IRTC_GetDefaultConfig(irtc_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - -#if !defined(FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) || (!FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) - /* Tamper pin 0 is used as a wakeup/hibernation pin */ - config->wakeupSelect = true; -#endif - - /* Sampling clock are not gated when in standby mode */ - config->timerStdMask = false; - - /* Only seconds, minutes and hours are matched when generating an alarm */ - config->alrmMatch = kRTC_MatchSecMinHr; -} - -/*! - * brief Sets the IRTC date and time according to the given time structure. - * - * The IRTC counter is started after the time is set. - * - * param base IRTC peripheral base address - * param datetime Pointer to structure where the date and time details to set are stored - * - * return kStatus_Success: success in setting the time and starting the IRTC - * kStatus_InvalidArgument: failure. An error occurs because the datetime format is incorrect. - */ -status_t IRTC_SetDatetime(RTC_Type *base, const irtc_datetime_t *datetime) -{ - assert(NULL != datetime); - - status_t status = kStatus_Success; - - /* Return error if the time provided is not valid */ - if (IRTC_CheckDatetimeFormat(datetime)) - { - /* The register stores the offset in years from the base year of 2112 */ - if (datetime->year < IRTC_BASE_YEAR) - { - /* Values for years less than the base year range from -128 to 1 */ - base->YEARMON = - RTC_YEARMON_YROFST(0x100U + datetime->year - IRTC_BASE_YEAR) | RTC_YEARMON_MON_CNT(datetime->month); - } - else - { - /* Values for years greater or equal to the base year range from 0 to 127 */ - base->YEARMON = RTC_YEARMON_YROFST(datetime->year - IRTC_BASE_YEAR) | RTC_YEARMON_MON_CNT(datetime->month); - } - /* Update the Day Count and Day of the week field */ - base->DAYS = RTC_DAYS_DOW(datetime->weekDay) | RTC_DAYS_DAY_CNT(datetime->day); - - /* Update hour and minute field */ - base->HOURMIN = RTC_HOURMIN_HOUR_CNT(datetime->hour) | RTC_HOURMIN_MIN_CNT(datetime->minute); - - /* Update the seconds register */ - base->SECONDS = RTC_SECONDS_SEC_CNT(datetime->second); - } - else - { - status = kStatus_InvalidArgument; - } - - return status; -} - -/*! - * brief Gets the IRTC time and stores it in the given time structure. - * - * param base IRTC peripheral base address - * param datetime Pointer to structure where the date and time details are stored. - */ -void IRTC_GetDatetime(RTC_Type *base, irtc_datetime_t *datetime) -{ - assert(NULL != datetime); - - uint16_t temp = base->YEARMON; - - datetime->year = - (uint16_t)IRTC_BASE_YEAR + (uint16_t)((int8_t)(uint8_t)((temp >> RTC_YEARMON_YROFST_SHIFT) & 0xFFU)); - datetime->month = (uint8_t)temp & RTC_YEARMON_MON_CNT_MASK; - - temp = base->DAYS; - datetime->weekDay = (uint8_t)((temp & RTC_DAYS_DOW_MASK) >> RTC_DAYS_DOW_SHIFT); - datetime->day = (uint8_t)temp & RTC_DAYS_DAY_CNT_MASK; - - temp = base->HOURMIN; - datetime->hour = (uint8_t)((temp & RTC_HOURMIN_HOUR_CNT_MASK) >> RTC_HOURMIN_HOUR_CNT_SHIFT); - datetime->minute = (uint8_t)temp & RTC_HOURMIN_MIN_CNT_MASK; - - datetime->second = (uint8_t)(base->SECONDS) & RTC_SECONDS_SEC_CNT_MASK; -} - -/*! - * brief Sets the IRTC alarm time - * - * param base RTC peripheral base address - * param alarmTime Pointer to structure where the alarm time is stored. - * - * note weekDay field of alarmTime is not used during alarm match and should be set to 0 - * - * return kStatus_Success: success in setting the alarm - * kStatus_InvalidArgument: error in setting the alarm. Error occurs because the alarm - * datetime format is incorrect. - */ -status_t IRTC_SetAlarm(RTC_Type *base, const irtc_datetime_t *alarmTime) -{ - assert(NULL != alarmTime); - - status_t status = kStatus_Success; - - /* Return error if the alarm time provided is not valid */ - if (IRTC_CheckDatetimeFormat(alarmTime)) - { - /* Set the alarm year */ - if (alarmTime->year < IRTC_BASE_YEAR) - { - base->ALM_YEARMON = RTC_ALM_YEARMON_ALM_YEAR(0x100U + alarmTime->year - IRTC_BASE_YEAR) | - RTC_ALM_YEARMON_ALM_MON(alarmTime->month); - } - else - { - base->ALM_YEARMON = - RTC_ALM_YEARMON_ALM_YEAR(alarmTime->year - IRTC_BASE_YEAR) | RTC_ALM_YEARMON_ALM_MON(alarmTime->month); - } - - /* Set the alarm day */ - base->ALM_DAYS = RTC_ALM_DAYS_ALM_DAY(alarmTime->day); - - /* Set the alarm hour and minute */ - base->ALM_HOURMIN = RTC_ALM_HOURMIN_ALM_HOUR(alarmTime->hour) | RTC_ALM_HOURMIN_ALM_MIN(alarmTime->minute); - - /* Set the alarm seconds */ - base->ALM_SECONDS = RTC_ALM_SECONDS_ALM_SEC(alarmTime->second); - } - else - { - status = kStatus_InvalidArgument; - } - - return status; -} - -/*! - * brief Returns the IRTC alarm time. - * - * param base RTC peripheral base address - * param datetime Pointer to structure where the alarm date and time details are stored. - */ -void IRTC_GetAlarm(RTC_Type *base, irtc_datetime_t *datetime) -{ - assert(NULL != datetime); - - uint16_t temp = base->ALM_YEARMON; - - datetime->year = - (uint16_t)IRTC_BASE_YEAR + (uint16_t)((int8_t)(uint8_t)((temp >> RTC_ALM_YEARMON_ALM_YEAR_SHIFT) & 0xFFU)); - datetime->month = (uint8_t)temp & RTC_ALM_YEARMON_ALM_MON_MASK; - - datetime->day = (uint8_t)(base->ALM_DAYS) & RTC_ALM_DAYS_ALM_DAY_MASK; - - temp = base->ALM_HOURMIN; - datetime->hour = (uint8_t)((temp & RTC_ALM_HOURMIN_ALM_HOUR_MASK) >> RTC_ALM_HOURMIN_ALM_HOUR_SHIFT); - datetime->minute = (uint8_t)temp & RTC_ALM_HOURMIN_ALM_MIN_MASK; - - datetime->second = (uint8_t)(base->ALM_SECONDS) & RTC_ALM_SECONDS_ALM_SEC_MASK; -} - -/*! - * brief Locks or unlocks IRTC registers for write access. - * - * note When the registers are unlocked, they remain in unlocked state for - * 2 seconds, after which they are locked automatically. After - * power-on-reset, the registers come out unlocked and they are locked - * automatically 15 seconds after power on. - * - * param base IRTC peripheral base address - * param lock true: Lock IRTC registers; false: Unlock IRTC registers. - * - * return kStatus_Success: if lock or unlock operation is successful - * kStatus_Fail: if lock or unlock operation fails even after multiple retry attempts - */ -status_t IRTC_SetWriteProtection(RTC_Type *base, bool lock) -{ - /* Retry before giving up */ - uint8_t repeatProtectSequence = 0xFFU; - status_t status = kStatus_Success; - - if (!lock) - { - /* Unlock IRTC registers */ - while ((0U != (base->STATUS & (uint16_t)RTC_STATUS_WRITE_PROT_EN_MASK)) && (0U != repeatProtectSequence)) - { - /* Access in 8-bit mode while storing the value */ - *(__IO uint8_t *)(&base->STATUS) = 0U; - *(__IO uint8_t *)(&base->STATUS) = 0x40U; - *(__IO uint8_t *)(&base->STATUS) = 0xC0U; - *(__IO uint8_t *)(&base->STATUS) = 0x80U; - repeatProtectSequence--; - } - } - else - { - /* Lock IRTC registers */ - while ((0U == ((base->STATUS & (uint16_t)RTC_STATUS_WRITE_PROT_EN_MASK) >> RTC_STATUS_WRITE_PROT_EN_SHIFT)) && - (0U != repeatProtectSequence)) - { - *(__IO uint8_t *)(&base->STATUS) = 0x80U; - repeatProtectSequence--; - } - } - - /* Lock/unlock was not successful even after trying 256 times */ - if (0U == repeatProtectSequence) - { - status = kStatus_Fail; - } - - return status; -} - -/*! - * brief Sets the IRTC daylight savings start and stop date and time. - * - * It also enables the daylight saving bit in the IRTC control register - * - * param base IRTC peripheral base address - * param datetime Pointer to a structure where the date and time details are stored. - */ -void IRTC_SetDaylightTime(RTC_Type *base, const irtc_daylight_time_t *datetime) -{ - assert(NULL != datetime); - - /* Disable daylight saving time */ - base->CTRL &= ~(uint16_t)RTC_CTRL_DST_EN_MASK; - - /* Set the daylight saving time start month and end month value */ - base->DST_MONTH = - RTC_DST_MONTH_DST_START_MONTH(datetime->startMonth) | RTC_DST_MONTH_DST_END_MONTH(datetime->endMonth); - - /* Set the daylight saving time start day and end day value */ - base->DST_DAY = RTC_DST_DAY_DST_START_DAY(datetime->startDay) | RTC_DST_DAY_DST_END_DAY(datetime->endDay); - - /* Set the daylight saving time start hour and end hour value */ - base->DST_HOUR = RTC_DST_HOUR_DST_START_HOUR(datetime->startHour) | RTC_DST_HOUR_DST_END_HOUR(datetime->endHour); - - /* Enable daylight saving time */ - base->CTRL |= RTC_CTRL_DST_EN_MASK; -} - -/*! - * brief Gets the IRTC daylight savings time and stores it in the given time structure. - * - * param base IRTC peripheral base address - * param datetime Pointer to a structure where the date and time details are stored. - */ -void IRTC_GetDaylightTime(RTC_Type *base, irtc_daylight_time_t *datetime) -{ - assert(NULL != datetime); - - uint16_t temp = base->DST_MONTH; - - /* Get the daylight savings time start and end month value */ - datetime->startMonth = - (uint8_t)((temp & RTC_DST_MONTH_DST_START_MONTH_MASK) >> RTC_DST_MONTH_DST_START_MONTH_SHIFT); - datetime->endMonth = (uint8_t)((temp & RTC_DST_MONTH_DST_END_MONTH_MASK) >> RTC_DST_MONTH_DST_END_MONTH_SHIFT); - - /* Get the daylight savings time start and end day value */ - temp = base->DST_DAY; - datetime->startDay = (uint8_t)((temp & RTC_DST_DAY_DST_START_DAY_MASK) >> RTC_DST_DAY_DST_START_DAY_SHIFT); - datetime->endDay = (uint8_t)((temp & RTC_DST_DAY_DST_END_DAY_MASK) >> RTC_DST_DAY_DST_END_DAY_SHIFT); - - /* Get the daylight savings time start and end hour value */ - temp = base->DST_HOUR; - datetime->startHour = (uint8_t)((temp & RTC_DST_HOUR_DST_START_HOUR_MASK) >> RTC_DST_HOUR_DST_START_HOUR_SHIFT); - datetime->endHour = (uint8_t)((temp & RTC_DST_HOUR_DST_END_HOUR_MASK) >> RTC_DST_HOUR_DST_END_HOUR_SHIFT); -} - -/*! - * brief Enables the coarse compensation and sets the value in the IRTC compensation register. - * - * param base IRTC peripheral base address - * param compensationValue Compensation value is a 2's complement value. - * param compensationInterval Compensation interval. - */ -void IRTC_SetCoarseCompensation(RTC_Type *base, uint8_t compensationValue, uint8_t compensationInterval) -{ - uint16_t reg; - - /* Set the compensation value and interval */ - base->COMPEN = (uint16_t)compensationValue | ((uint16_t)compensationInterval << 8U); - - /* Disable fine and enable coarse compensation */ - reg = base->CTRL; - reg &= ~(uint16_t)RTC_CTRL_FINEEN_MASK; - reg |= RTC_CTRL_COMP_EN_MASK; - base->CTRL = reg; -} - -/*! - * brief Enables the fine compensation and sets the value in the IRTC compensation register. - * - * param base The IRTC peripheral base address - * param integralValue Compensation integral value; twos complement value of the integer part - * param fractionValue Compensation fraction value expressed as number of clock cycles of a - * fixed 4.194304Mhz clock that have to be added. - * param accumulateFractional Flag indicating if we want to add to previous fractional part; - * true: Add to previously accumulated fractional part, - * false: Start afresh and overwrite current value - */ -void IRTC_SetFineCompensation(RTC_Type *base, uint8_t integralValue, uint8_t fractionValue, bool accumulateFractional) -{ - if (!accumulateFractional) - { - /* Disable compensation to clear previous accumulated fractional part */ - base->CTRL &= ~(((uint16_t)1U << RTC_CTRL_COMP_EN_SHIFT) | ((uint16_t)1U << RTC_CTRL_FINEEN_SHIFT)); - } - - /* Set the compensation fractional and integral parts */ - base->COMPEN = ((uint16_t)fractionValue & 0x7FU) | (((uint16_t)integralValue & 0xFU) << 12U); - /* Enable fine compensation */ - base->CTRL |= (RTC_CTRL_COMP_EN_MASK | RTC_CTRL_FINEEN_MASK); -} - -/*! - * brief This function allows configuring the four tamper inputs. - * - * The function configures the filter properties for the three external tampers. - * It also sets up active/passive and direction of the tamper bits, which are not available - * on all platforms. - * note This function programs the tamper filter parameters. The user must gate the 32K clock to - * the RTC before calling this function. It is assumed that the time and date are set after this - * and the tamper parameters do not require to be changed again later. - * - * param base The IRTC peripheral base address - * param tamperNumber The IRTC tamper input to configure - * param tamperConfig The IRTC tamper properties - */ -void IRTC_SetTamperParams(RTC_Type *base, irtc_tamper_pins_t tamperNumber, const irtc_tamper_config_t *tamperConfig) -{ - assert(NULL != tamperConfig); - - uint16_t reg = 0; - -#if defined(FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION) && (FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION) - reg = base->TAMPER_DIRECTION; - /* Set whether tamper pin is active or passive */ - if (tamperConfig->activePassive) - { - /* In case of active tamper, set the direction */ - reg |= (1U << tamperNumber); - if (tamperConfig->direction) - { - /* Tamper direction is output */ - reg |= (1U << (RTC_TAMPER_DIRECTION_I_O_TAMP_SHIFT + tamperNumber)); - } - else - { - /* Tamper direction is input */ - reg &= ~(1U << (RTC_TAMPER_DIRECTION_I_O_TAMP_SHIFT + tamperNumber)); - } - } - else - { - /* Passive tampers are input only and the direction bit is read only in this case */ - reg &= ~(1U << tamperNumber); - } - base->TAMPER_DIRECTION = reg; -#endif /* FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION */ - - /* Set the filter properties for the external tamper pins */ - switch (tamperNumber) - { - case kIRTC_Tamper_0: - /* Set the pin for Tamper 0 */ -#if !defined(FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) || (!FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) - base->CTRL2 &= ~(uint16_t)RTC_CTRL2_WAKEUP_MODE_MASK; -#endif - reg = base->FILTER01_CFG; - reg &= ~((uint16_t)RTC_FILTER01_CFG_POL0_MASK | (uint16_t)RTC_FILTER01_CFG_FIL_DUR0_MASK | - (uint16_t)RTC_FILTER01_CFG_CLK_SEL0_MASK); - reg |= (RTC_FILTER01_CFG_POL0(tamperConfig->pinPolarity) | - RTC_FILTER01_CFG_FIL_DUR0(tamperConfig->filterDuration) | - RTC_FILTER01_CFG_CLK_SEL0(tamperConfig->filterClk)); - base->FILTER01_CFG = reg; - break; - case kIRTC_Tamper_1: - reg = base->FILTER01_CFG; - reg &= ~((uint16_t)RTC_FILTER01_CFG_POL1_MASK | (uint16_t)RTC_FILTER01_CFG_FIL_DUR1_MASK | - (uint16_t)RTC_FILTER01_CFG_CLK_SEL1_MASK); - reg |= (RTC_FILTER01_CFG_POL1(tamperConfig->pinPolarity) | - RTC_FILTER01_CFG_FIL_DUR1(tamperConfig->filterDuration) | - RTC_FILTER01_CFG_CLK_SEL1(tamperConfig->filterClk)); - base->FILTER01_CFG = reg; - break; -#if defined(FSL_FEATURE_RTC_HAS_FILTER23_CFG) && FSL_FEATURE_RTC_HAS_FILTER23_CFG - case kIRTC_Tamper_2: - reg = base->FILTER23_CFG; - reg &= ~((uint16_t)RTC_FILTER23_CFG_POL2_MASK | (uint16_t)RTC_FILTER23_CFG_FIL_DUR2_MASK | - (uint16_t)RTC_FILTER23_CFG_CLK_SEL2_MASK); - reg |= (RTC_FILTER23_CFG_POL2(tamperConfig->pinPolarity) | - RTC_FILTER23_CFG_FIL_DUR2(tamperConfig->filterDuration) | - RTC_FILTER23_CFG_CLK_SEL2(tamperConfig->filterClk)); - base->FILTER23_CFG = reg; - break; - case kIRTC_Tamper_3: - reg = base->FILTER23_CFG; - reg &= ~((uint16_t)RTC_FILTER23_CFG_POL3_MASK | (uint16_t)RTC_FILTER23_CFG_FIL_DUR3_MASK | - (uint16_t)RTC_FILTER23_CFG_CLK_SEL3_MASK); - reg |= (RTC_FILTER23_CFG_POL3(tamperConfig->pinPolarity) | - RTC_FILTER23_CFG_FIL_DUR3(tamperConfig->filterDuration) | - RTC_FILTER23_CFG_CLK_SEL3(tamperConfig->filterClk)); - base->FILTER23_CFG = reg; - break; -#else - case kIRTC_Tamper_2: - reg = base->FILTER2_CFG; - reg &= ~((uint16_t)RTC_FILTER2_CFG_POL2_MASK | (uint16_t)RTC_FILTER2_CFG_FIL_DUR2_MASK | - (uint16_t)RTC_FILTER2_CFG_CLK_SEL2_MASK); - reg |= (RTC_FILTER2_CFG_POL2(tamperConfig->pinPolarity) | - RTC_FILTER2_CFG_FIL_DUR2(tamperConfig->filterDuration) | - RTC_FILTER2_CFG_CLK_SEL2(tamperConfig->filterClk)); - base->FILTER2_CFG = reg; - break; -#endif - - default: - /* Internal tamper, does not have filter configuration. */ - break; - } -} - -#if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && (FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) - -/*! - * brief This function reads the tamper timestamp and returns the associated tamper pin. - * - * The tamper timestamp has month, day, hour, minutes, and seconds. Ignore the year field as this - * information is not available in the tamper queue. The user should look at the RTC_YEARMON register - * for this because the expectation is that the queue is read at least once a year. - * Return the tamper pin number associated with the timestamp. - * - * param base The IRTC peripheral base address - * param tamperTimestamp The tamper timestamp - * - * return The tamper pin number - */ -uint8_t IRTC_ReadTamperQueue(RTC_Type *base, irtc_datetime_t *tamperTimestamp) -{ - assert(NULL != tamperTimestamp); - - /* Read the register 2 times to get a entry*/ - uint16_t temp1 = base->TAMPER_QUEUE; - uint16_t temp2 = base->TAMPER_QUEUE; - uint8_t tamperNum; - - /* - * Tamper queue does not store the year field as this value can be read from RTC_YEARMON. - * It is expected that the queue will be read at least once in a year. - */ - tamperTimestamp->year = 0; - /* From the first read; TAMPER_DATA[4:0] is the hour field */ - tamperTimestamp->hour = (uint8_t)temp1 & 0x1FU; - /* From the first read; TAMPER_DATA[9:5] is the day field */ - tamperTimestamp->day = (uint8_t)(temp1 >> 5U) & 0x1FU; - /* From the first read; TAMPER_DATA[13:10] is the month field */ - tamperTimestamp->month = (uint8_t)(temp1 >> 10U) & 0xFU; - - /* From the second read; TAMPER_DATA[5:0] is the seconds field */ - tamperTimestamp->second = (uint8_t)temp2 & 0x3FU; - /* From the second read; TAMPER_DATA[11:6] is the minutes field */ - tamperTimestamp->minute = (uint8_t)(temp2 >> 6U) & 0x3FU; - /* From the second read; TAMPER_DATA[14:12] is the tamper index */ - tamperNum = (uint8_t)(temp2 >> 12U) & 0x7U; - - return tamperNum; -} - -#endif /* FSL_FEATURE_RTC_HAS_TAMPER_QUEUE */ - -/*! - * brief Select which clock to output from RTC. - * - * Select which clock to output from RTC for other modules to use inside SoC, for example, - * RTC subsystem needs RTC to output 1HZ clock for sub-second counter. - * - * param base IRTC peripheral base address - * param cloOut select clock to use for output - */ -void IRTC_ConfigClockOut(RTC_Type *base, irtc_clockout_sel_t clkOut) -{ - uint16_t ctrlVal = base->CTRL; - - ctrlVal &= ~RTC_CTRL_CLKOUT_MASK; - - ctrlVal |= RTC_CTRL_CLKOUT((uint16_t)clkOut); - if (clkOut == kIRTC_ClkoutCoarse1Hz) - { - ctrlVal |= RTC_CTRL_COMP_EN_MASK; - } - else if (clkOut == kIRTC_ClkoutFine1Hz) - { - ctrlVal |= RTC_CTRL_FINEEN_MASK; - } - else - { - /* empty else */ - } - - base->CTRL = ctrlVal; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_irtc.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_irtc.h deleted file mode 100644 index 4f73f23894e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_irtc.h +++ /dev/null @@ -1,751 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_IRTC_H_ -#define _FSL_IRTC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup irtc - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_IRTC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version. */ -/*@}*/ - -/*! @brief IRTC filter clock source options. */ -typedef enum _irtc_filter_clock_source -{ - kIRTC_32K = 0x0U, /*!< Use 32 kHz clock source for the tamper filter.*/ - kIRTC_512 = 0x1U, /*!< Use 512 Hz clock source for the tamper filter.*/ - kIRTC_128 = 0x2U, /*!< Use 128 Hz clock source for the tamper filter.*/ - kIRTC_64 = 0x3U, /*!< Use 64 Hz clock source for the tamper filter.*/ - kIRTC_16 = 0x4U, /*!< Use 16 Hz clock source for the tamper filter.*/ - kIRTC_8 = 0x5U, /*!< Use 8 Hz clock source for the tamper filter.*/ - kIRTC_4 = 0x6U, /*!< Use 4 Hz clock source for the tamper filter.*/ - kIRTC_2 = 0x7U /*!< Use 2 Hz clock source for the tamper filter.*/ -} irtc_filter_clock_source_t; - -/*! @brief IRTC Tamper pins. */ -typedef enum _irtc_tamper_pins -{ - kIRTC_Tamper_0 = 0U, /*!< External Tamper 0 */ - kIRTC_Tamper_1, /*!< External Tamper 1 */ - kIRTC_Tamper_2, /*!< External Tamper 2 */ - kIRTC_Tamper_3 /*!< Internal tamper, does not have filter configuration */ -} irtc_tamper_pins_t; - -/*! @brief List of IRTC interrupts */ -typedef enum _irtc_interrupt_enable -{ - kIRTC_TamperInterruptEnable = RTC_IER_TAMPER_IE_MASK, /*!< Tamper Interrupt Enable */ - kIRTC_AlarmInterruptEnable = RTC_IER_ALM_IE_MASK, /*!< Alarm Interrupt Enable */ - kIRTC_DayInterruptEnable = RTC_IER_DAY_IE_MASK, /*!< Days Interrupt Enable */ - kIRTC_HourInterruptEnable = RTC_IER_HOUR_IE_MASK, /*!< Hours Interrupt Enable */ - kIRTC_MinInterruptEnable = RTC_IER_MIN_IE_MASK, /*!< Minutes Interrupt Enable */ - kIRTC_1hzInterruptEnable = RTC_IER_IE_1HZ_MASK, /*!< 1 Hz interval Interrupt Enable */ - kIRTC_2hzInterruptEnable = RTC_IER_IE_2HZ_MASK, /*!< 2 Hz interval Interrupt Enable */ - kIRTC_4hzInterruptEnable = RTC_IER_IE_4HZ_MASK, /*!< 4 Hz interval Interrupt Enable */ - kIRTC_8hzInterruptEnable = RTC_IER_IE_8HZ_MASK, /*!< 8 Hz interval Interrupt Enable */ - kIRTC_16hzInterruptEnable = RTC_IER_IE_16HZ_MASK, /*!< 16 Hz interval Interrupt Enable */ - kIRTC_32hzInterruptEnable = RTC_IER_IE_32HZ_MASK, /*!< 32 Hz interval Interrupt Enable */ - kIRTC_64hzInterruptEnable = RTC_IER_IE_64HZ_MASK, /*!< 64 Hz interval Interrupt Enable */ - kIRTC_128hzInterruptEnable = RTC_IER_IE_128HZ_MASK, /*!< 128 Hz interval Interrupt Enable */ - kIRTC_256hzInterruptEnable = RTC_IER_IE_256HZ_MASK, /*!< 256 Hz interval Interrupt Enable */ - kIRTC_512hzInterruptEnable = RTC_IER_IE_512HZ_MASK, /*!< 512 Hz interval Interrupt Enable */ -#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM - kIRTC_WakeTimerInterruptEnable = (RTC_WAKE_TIMER_CTRL_INTR_EN_MASK << 16U), /*!< Wake timer Interrupt Enable */ -#endif -#if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && FSL_FEATURE_RTC_HAS_TAMPER_QUEUE - kIRTC_TamperQueueFullInterruptEnable = - (RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK << 24U), /*!< Tamper queue full Interrupt Enable */ -#endif -} irtc_interrupt_enable_t; - -/*! @brief List of IRTC flags */ -typedef enum _irtc_status_flags -{ - kIRTC_TamperFlag = RTC_ISR_TAMPER_IS_MASK, /*!< Tamper Status flag*/ - kIRTC_AlarmFlag = RTC_ISR_ALM_IS_MASK, /*!< Alarm Status flag */ - kIRTC_DayFlag = RTC_ISR_DAY_IS_MASK, /*!< Days Status flag */ - kIRTC_HourFlag = RTC_ISR_HOUR_IS_MASK, /*!< Hour Status flag */ - kIRTC_MinFlag = RTC_ISR_MIN_IS_MASK, /*!< Minutes Status flag */ - kIRTC_1hzFlag = RTC_ISR_IS_1HZ_MASK, /*!< 1 Hz interval status flag */ - kIRTC_2hzFlag = RTC_ISR_IS_2HZ_MASK, /*!< 2 Hz interval status flag*/ - kIRTC_4hzFlag = RTC_ISR_IS_4HZ_MASK, /*!< 4 Hz interval status flag*/ - kIRTC_8hzFlag = RTC_ISR_IS_8HZ_MASK, /*!< 8 Hz interval status flag*/ - kIRTC_16hzFlag = RTC_ISR_IS_16HZ_MASK, /*!< 16 Hz interval status flag*/ - kIRTC_32hzFlag = RTC_ISR_IS_32HZ_MASK, /*!< 32 Hz interval status flag*/ - kIRTC_64hzFlag = RTC_ISR_IS_64HZ_MASK, /*!< 64 Hz interval status flag*/ - kIRTC_128hzFlag = RTC_ISR_IS_128HZ_MASK, /*!< 128 Hz interval status flag*/ - kIRTC_256hzFlag = RTC_ISR_IS_256HZ_MASK, /*!< 256 Hz interval status flag*/ - kIRTC_512hzFlag = RTC_ISR_IS_512HZ_MASK, /*!< 512 Hz interval status flag*/ - kIRTC_InvalidFlag = (RTC_STATUS_INVAL_BIT_MASK << 16U), /*!< Indicates if time/date counters are invalid */ - kIRTC_WriteProtFlag = (RTC_STATUS_WRITE_PROT_EN_MASK << 16U), /*!< Write protect enable status flag */ - kIRTC_CpuLowVoltFlag = (RTC_STATUS_CPU_LOW_VOLT_MASK << 16U), /*!< CPU low voltage warning flag */ - kIRTC_ResetSrcFlag = (RTC_STATUS_RST_SRC_MASK << 16U), /*!< Reset source flag */ - kIRTC_CmpIntFlag = (RTC_STATUS_CMP_INT_MASK << 16U), /*!< Compensation interval status flag */ - kIRTC_BusErrFlag = (RTC_STATUS_BUS_ERR_MASK << 16U), /*!< Bus error flag */ - kIRTC_CmpDoneFlag = (RTC_STATUS_CMP_DONE_MASK << 16U), /*!< Compensation done flag */ -#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM - kIRTC_WakeTimerFlag = (RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK << 28U) /*!< Wake timer status flag */ -#endif -} irtc_status_flags_t; - -/*! @brief IRTC alarm match options */ -typedef enum _irtc_alarm_match -{ - kRTC_MatchSecMinHr = 0U, /*!< Only match second, minute and hour */ - kRTC_MatchSecMinHrDay = 1U, /*!< Only match second, minute, hour and day */ - kRTC_MatchSecMinHrDayMnth = 2U, /*!< Only match second, minute, hour, day and month */ - kRTC_MatchSecMinHrDayMnthYr = 3U /*!< Only match second, minute, hour, day, month and year */ -} irtc_alarm_match_t; - -/*! @brief List of RTC Oscillator capacitor load settings */ -typedef enum _irtc_osc_cap_load -{ - kIRTC_Capacitor2p = (1U << 1U), /*!< 2pF capacitor load */ - kIRTC_Capacitor4p = (1U << 2U), /*!< 4pF capacitor load */ - kIRTC_Capacitor8p = (1U << 3U), /*!< 8pF capacitor load */ - kIRTC_Capacitor16p = (1U << 4U) /*!< 16pF capacitor load */ -} irtc_osc_cap_load_t; - -/*! @brief IRTC clockout select. */ -typedef enum _irtc_clockout_sel -{ - kIRTC_ClkoutNo = 0U, /*!< No clock out */ - kIRTC_ClkoutFine1Hz, /*!< clock out fine 1Hz */ - kIRTC_Clkout32kHz, /*!< clock out 32.768kHz */ - kIRTC_ClkoutCoarse1Hz /*!< clock out coarse 1Hz */ -} irtc_clockout_sel_t; - -/*! @brief Structure is used to hold the date and time */ -typedef struct _irtc_datetime -{ - uint16_t year; /*!< Range from 1984 to 2239.*/ - uint8_t month; /*!< Range from 1 to 12.*/ - uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ - uint8_t weekDay; /*!< Range from 0(Sunday) to 6(Saturday). */ - uint8_t hour; /*!< Range from 0 to 23.*/ - uint8_t minute; /*!< Range from 0 to 59.*/ - uint8_t second; /*!< Range from 0 to 59.*/ -} irtc_datetime_t; - -/*! @brief Structure is used to hold the daylight saving time */ -typedef struct _irtc_daylight_time -{ - uint8_t startMonth; /*!< Range from 1 to 12 */ - uint8_t endMonth; /*!< Range from 1 to 12 */ - uint8_t startDay; /*!< Range from 1 to 31 (depending on month) */ - uint8_t endDay; /*!< Range from 1 to 31 (depending on month) */ - uint8_t startHour; /*!< Range from 0 to 23 */ - uint8_t endHour; /*!< Range from 0 to 23 */ -} irtc_daylight_time_t; - -/*! @brief Structure is used to define the parameters to configure a RTC tamper event. */ -typedef struct _irtc_tamper_config -{ -#if FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION - bool activePassive; /*!< true: configure tamper as active; false: passive tamper */ - bool direction; /*!< true: configure tamper direction as output; false: configure as input; - this is only used if a tamper pin is defined as active */ -#endif - bool pinPolarity; /*!< true: tamper has active low polarity; - false: active high polarity */ - irtc_filter_clock_source_t filterClk; /*!< Clock source for the tamper filter */ - uint8_t filterDuration; /*!< Tamper filter duration.*/ -} irtc_tamper_config_t; - -/*! - * @brief RTC config structure - * - * This structure holds the configuration settings for the RTC peripheral. To initialize this - * structure to reasonable defaults, call the IRTC_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _irtc_config -{ -#if !defined(FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) || (!FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) - bool wakeupSelect; /*!< true: Tamper pin 0 is used to wakeup the chip; - false: Tamper pin 0 is used as the tamper pin */ -#endif - bool timerStdMask; /*!< true: Sampling clocks gated in standby mode; - false: Sampling clocks not gated */ - irtc_alarm_match_t alrmMatch; /*!< Pick one option from enumeration :: irtc_alarm_match_t */ -} irtc_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the IRTC clock and configures the peripheral for basic operation. - * - * This function initiates a soft-reset of the IRTC module, this has not effect on DST, - * calendaring, standby time and tamper detect registers. - * - * @note This API should be called at the beginning of the application using the IRTC driver. - * - * @param base IRTC peripheral base address - * @param config Pointer to user's IRTC config structure. - * - * @return kStatus_Fail if we cannot disable register write protection - */ -status_t IRTC_Init(RTC_Type *base, const irtc_config_t *config); - -/*! - * @brief Gate the IRTC clock - * - * @param base IRTC peripheral base address - */ -static inline void IRTC_Deinit(RTC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Rtc0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Fill in the IRTC config struct with the default settings - * - * The default values are: - * @code - * config->wakeupSelect = true; - * config->timerStdMask = false; - * config->alrmMatch = kRTC_MatchSecMinHr; - * @endcode - * @param config Pointer to user's IRTC config structure. - */ -void IRTC_GetDefaultConfig(irtc_config_t *config); - -/*! @}*/ - -/*! - * @name Current Time & Alarm - * @{ - */ - -/*! - * @brief Sets the IRTC date and time according to the given time structure. - * - * The IRTC counter is started after the time is set. - * - * @param base IRTC peripheral base address - * @param datetime Pointer to structure where the date and time details to set are stored - * - * @return kStatus_Success: success in setting the time and starting the IRTC - * kStatus_InvalidArgument: failure. An error occurs because the datetime format is incorrect. - */ -status_t IRTC_SetDatetime(RTC_Type *base, const irtc_datetime_t *datetime); - -/*! - * @brief Gets the IRTC time and stores it in the given time structure. - * - * @param base IRTC peripheral base address - * @param datetime Pointer to structure where the date and time details are stored. - */ -void IRTC_GetDatetime(RTC_Type *base, irtc_datetime_t *datetime); - -/*! - * @brief Sets the IRTC alarm time - * - * @param base RTC peripheral base address - * @param alarmTime Pointer to structure where the alarm time is stored. - * - * @note weekDay field of alarmTime is not used during alarm match and should be set to 0 - * - * @return kStatus_Success: success in setting the alarm - * kStatus_InvalidArgument: error in setting the alarm. Error occurs because the alarm - * datetime format is incorrect. - */ -status_t IRTC_SetAlarm(RTC_Type *base, const irtc_datetime_t *alarmTime); - -/*! - * @brief Returns the IRTC alarm time. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the alarm date and time details are stored. - */ -void IRTC_GetAlarm(RTC_Type *base, irtc_datetime_t *datetime); -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected IRTC interrupts. - * - * @param base IRTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::irtc_interrupt_enable_t - */ -static inline void IRTC_EnableInterrupts(RTC_Type *base, uint32_t mask) -{ - base->IER |= (uint16_t)mask; -#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM - if (0U != (mask & kIRTC_WakeTimerInterruptEnable)) - { - base->WAKE_TIMER_CTRL |= RTC_WAKE_TIMER_CTRL_INTR_EN_MASK; - } -#endif -#if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && FSL_FEATURE_RTC_HAS_TAMPER_QUEUE - if (0U != (mask & kIRTC_TamperQueueFullInterruptEnable)) - { - base->TAMPER_QSCR |= RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK; - } -#endif -} - -/*! - * @brief Disables the selected IRTC interrupts. - * - * @param base IRTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::irtc_interrupt_enable_t - */ -static inline void IRTC_DisableInterrupts(RTC_Type *base, uint32_t mask) -{ - base->IER &= ~(uint16_t)mask; -#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM - if (0U != (mask & kIRTC_WakeTimerInterruptEnable)) - { - base->WAKE_TIMER_CTRL &= ~RTC_WAKE_TIMER_CTRL_INTR_EN_MASK; - } -#endif -#if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && FSL_FEATURE_RTC_HAS_TAMPER_QUEUE - if (0U != (mask & kIRTC_TamperQueueFullInterruptEnable)) - { - base->TAMPER_QSCR &= ~RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK; - } -#endif -} - -/*! - * @brief Gets the enabled IRTC interrupts. - * - * @param base IRTC peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::irtc_interrupt_enable_t - */ -static inline uint32_t IRTC_GetEnabledInterrupts(RTC_Type *base) -{ - uint32_t intsEnabled = base->IER; -#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM - intsEnabled |= (base->WAKE_TIMER_CTRL & RTC_WAKE_TIMER_CTRL_INTR_EN_MASK) << 16U; -#endif -#if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && FSL_FEATURE_RTC_HAS_TAMPER_QUEUE - intsEnabled |= (base->TAMPER_QSCR & RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK) << 24U; -#endif - - return intsEnabled; -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the IRTC status flags - * - * @param base IRTC peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::irtc_status_flags_t - */ -static inline uint32_t IRTC_GetStatusFlags(RTC_Type *base) -{ -#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM - return (base->ISR | ((uint32_t)base->STATUS << 16U) | ((uint32_t)base->WAKE_TIMER_CTRL << 28U)); -#else - return (base->ISR | ((uint32_t)base->STATUS << 16U)); -#endif -} - -/*! - * @brief Clears the IRTC status flags. - * - * @param base IRTC peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::irtc_status_flags_t - */ -static inline void IRTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) -{ - base->ISR = (uint16_t)mask; - base->STATUS = (base->STATUS & ~((uint16_t)RTC_STATUS_BUS_ERR_MASK | (uint16_t)RTC_STATUS_CMP_DONE_MASK)) | - ((uint16_t)(mask >> 16U)); -#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM - if (0U != (mask & kIRTC_WakeTimerFlag)) - { - base->WAKE_TIMER_CTRL |= RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK; - } -#endif -} - -/*! @}*/ - -/*! - * @brief This function sets the specified capacitor configuration for the RTC oscillator. - * - * @param base IRTC peripheral base address - * @param capLoad Oscillator loads to enable. This is a logical OR of members of the - * enumeration ::irtc_osc_cap_load_t - */ -static inline void IRTC_SetOscCapLoad(RTC_Type *base, uint16_t capLoad) -{ - uint16_t reg = base->GP_DATA_REG; - - reg &= ~((uint16_t)kIRTC_Capacitor2p | (uint16_t)kIRTC_Capacitor4p | (uint16_t)kIRTC_Capacitor8p | - (uint16_t)kIRTC_Capacitor16p); - reg |= capLoad; - - base->GP_DATA_REG = reg; -} - -/*! - * @brief Locks or unlocks IRTC registers for write access. - * - * @note When the registers are unlocked, they remain in unlocked state for - * 2 seconds, after which they are locked automatically. After - * power-on-reset, the registers come out unlocked and they are locked - * automatically 15 seconds after power on. - * - * @param base IRTC peripheral base address - * @param lock true: Lock IRTC registers; false: Unlock IRTC registers. - * - * @return kStatus_Success: if lock or unlock operation is successful - * kStatus_Fail: if lock or unlock operation fails even after multiple retry attempts - */ -status_t IRTC_SetWriteProtection(RTC_Type *base, bool lock); - -/*! - * @brief Performs a software reset on the IRTC module. - * - * Clears contents of alarm, interrupt (status and enable except tamper interrupt enable bit) - * registers, STATUS[CMP_DONE] and STATUS[BUS_ERR]. This has no effect on DST, calendaring, standby time - * and tamper detect registers. - * - * @param base IRTC peripheral base address - */ -static inline void IRTC_Reset(RTC_Type *base) -{ - base->CTRL |= RTC_CTRL_SWR_MASK; -} - -/*! - * @brief Enable/disable 32 kHz RTC OSC clock during RTC register write - * - * @param base IRTC peripheral base address - * @param enable Enable/disable 32 kHz RTC OSC clock. - * - true: Enables the oscillator. - * - false: Disables the oscillator. - * - */ -static inline void IRTC_Enable32kClkDuringRegisterWrite(RTC_Type *base, bool enable) -{ - if (enable) - { - base->GP_DATA_REG &= ~RTC_GP_DATA_REG_CFG0_MASK; - } - else - { - base->GP_DATA_REG |= RTC_GP_DATA_REG_CFG0_MASK; - } -} - -/*! - * @brief Select which clock to output from RTC. - * - * Select which clock to output from RTC for other modules to use inside SoC, for example, - * RTC subsystem needs RTC to output 1HZ clock for sub-second counter. - * - * @param base IRTC peripheral base address - * @param cloOut select clock to use for output, - */ -void IRTC_ConfigClockOut(RTC_Type *base, irtc_clockout_sel_t clkOut); - -/*! - * @brief Gets the IRTC Tamper status flags - * - * @param base IRTC peripheral base address - * - * @return The Tamper status value. - */ -static inline uint8_t IRTC_GetTamperStatusFlag(RTC_Type *base) -{ - return (base->TAMPER_SCR & RTC_TAMPER_SCR_TMPR_STS_MASK) >> RTC_TAMPER_SCR_TMPR_STS_SHIFT; -} - -/*! - * @brief Gets the IRTC Tamper status flags - * - * @param base IRTC peripheral base address - * - */ -static inline void IRTC_ClearTamperStatusFlag(RTC_Type *base) -{ - /* Writing '1' to this field clears the tamper status.*/ - base->TAMPER_SCR |= RTC_TAMPER_SCR_TMPR_STS_MASK; -} - -/*! - * @brief Set tamper configuration over - * - * Note that this API is neeeded after call IRTC_SetTamperParams to configure tamper events to - * notify IRTC module that tamper configuration process is over. - * - * @param base IRTC peripheral base address - * - */ -static inline void IRTC_SetTamperConfigurationOver(RTC_Type *base) -{ - /* Set tamper configuration over.*/ - base->CTRL2 |= RTC_CTRL2_TAMP_CFG_OVER_MASK; -} - -/*! - * @name Daylight Savings Interface - * @{ - */ - -/*! - * @brief Sets the IRTC daylight savings start and stop date and time. - * - * It also enables the daylight saving bit in the IRTC control register - * - * @param base IRTC peripheral base address - * @param datetime Pointer to a structure where the date and time details are stored. - */ -void IRTC_SetDaylightTime(RTC_Type *base, const irtc_daylight_time_t *datetime); - -/*! - * @brief Gets the IRTC daylight savings time and stores it in the given time structure. - * - * @param base IRTC peripheral base address - * @param datetime Pointer to a structure where the date and time details are stored. - */ -void IRTC_GetDaylightTime(RTC_Type *base, irtc_daylight_time_t *datetime); - -/*! @}*/ - -/*! - * @name Time Compensation Interface - * @{ - */ - -/*! - * @brief Enables the coarse compensation and sets the value in the IRTC compensation register. - * - * @param base IRTC peripheral base address - * @param compensationValue Compensation value is a 2's complement value. - * @param compensationInterval Compensation interval. - */ -void IRTC_SetCoarseCompensation(RTC_Type *base, uint8_t compensationValue, uint8_t compensationInterval); - -/*! - * @brief Enables the fine compensation and sets the value in the IRTC compensation register. - * - * @param base The IRTC peripheral base address - * @param integralValue Compensation integral value; twos complement value of the integer part - * @param fractionValue Compensation fraction value expressed as number of clock cycles of a - * fixed 4.194304Mhz clock that have to be added. - * @param accumulateFractional Flag indicating if we want to add to previous fractional part; - * true: Add to previously accumulated fractional part, - * false: Start afresh and overwrite current value - */ -void IRTC_SetFineCompensation(RTC_Type *base, uint8_t integralValue, uint8_t fractionValue, bool accumulateFractional); - -/*! @}*/ - -/*! - * @name Tamper Interface - * @{ - */ - -/*! - * @brief This function allows configuring the four tamper inputs. - * - * The function configures the filter properties for the three external tampers. - * It also sets up active/passive and direction of the tamper bits, which are not available - * on all platforms. - * @note This function programs the tamper filter parameters. The user must gate the 32K clock to - * the RTC before calling this function. It is assumed that the time and date are set after this - * and the tamper parameters do not require to be changed again later. - * - * @param base The IRTC peripheral base address - * @param tamperNumber The IRTC tamper input to configure - * @param tamperConfig The IRTC tamper properties - */ -void IRTC_SetTamperParams(RTC_Type *base, irtc_tamper_pins_t tamperNumber, const irtc_tamper_config_t *tamperConfig); - -#if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && (FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) - -/*! - * @brief This function reads the tamper timestamp and returns the associated tamper pin. - * - * The tamper timestamp has month, day, hour, minutes, and seconds. Ignore the year field as this - * information is not available in the tamper queue. The user should look at the RTC_YEARMON register - * for this because the expectation is that the queue is read at least once a year. - * Return the tamper pin number associated with the timestamp. - * - * @param base The IRTC peripheral base address - * @param tamperTimestamp The tamper timestamp - * - * @return The tamper pin number - */ -uint8_t IRTC_ReadTamperQueue(RTC_Type *base, irtc_datetime_t *tamperTimestamp); - -/*! - * @brief Gets the IRTC Tamper queue full status - * - * @param base IRTC peripheral base address - * - * @retval true Tamper queue is full. - * @retval false Tamper queue is not full. - */ -static inline bool IRTC_GetTamperQueueFullStatus(RTC_Type *base) -{ - return ((0U != (base->TAMPER_SCR & RTC_TAMPER_QSCR_Q_FULL_MASK)) ? true : false); -} - -/*! - * @brief Clear the IRTC Tamper queue full status - * - * @param base IRTC peripheral base address - * - */ -static inline void IRTC_ClearTamperQueueFullStatus(RTC_Type *base) -{ - base->TAMPER_QSCR |= RTC_TAMPER_QSCR_Q_CLEAR_MASK; -} -#endif /* FSL_FEATURE_RTC_HAS_TAMPER_QUEUE */ - -/*! @}*/ - -#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM -/*! - * @name RTC subsystem Interface - * @{ - */ - -/*! - * @brief Enable the RTC wake-up timer. - * - * 1HZ clock out selected via call to API IRTC_ConfigClockOut in order for the subsecond - * counter to synchronize with the RTC_SECONDS counter. - * - * @param base RTC peripheral base address - * @param enable Use/Un-use the sub-second counter. - * - true: Use RTC wake-up timer at the same time. - * - false: Un-use RTC wake-up timer, RTC only use the normal seconds timer by default. - */ -static inline void IRTC_EnableSubsecondCounter(RTC_Type *base, bool enable) -{ - if (enable) - { - base->SUBSECOND_CTRL |= RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK; - } - else - { - base->SUBSECOND_CTRL &= ~RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK; - } -} - -/*! - * @brief Read the actual RTC sub-second COUNT value. - * - * @param base RTC peripheral base address - * - * @return The actual RTC sub-second COUNT value. - */ -static inline uint32_t IRTC_GetSubsecondCount(RTC_Type *base) -{ - uint32_t a, b; - - /* Follow the RF document to read the RTC default seconds timer (1HZ) counter value. */ - do - { - a = base->SUBSECOND_CNT; - b = base->SUBSECOND_CNT; - } while (a != b); - - return b; -} -/*! - * @brief Set countdown value to the RTC wake timer counter register. - * - * @param base RTC peripheral base address - * @param enable1kHzClk Enable 1kHz clock source for the wake timer, else use the 32kHz clock. - * @param wakeupValue The value to be loaded into the WAKE register in wake timer counter. - */ -static inline void IRTC_SetWakeupCount(RTC_Type *base, bool enable1kHzClk, uint32_t wakeupValue) -{ - /* Config whether enable the wakeup counter */ - uint32_t writeVal; - writeVal = base->WAKE_TIMER_CTRL; - base->WAKE_TIMER_CTRL = RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK; - - if (enable1kHzClk) - { - writeVal |= RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK; - } - else - { - writeVal &= ~RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK; - } - - base->WAKE_TIMER_CTRL = writeVal; - /* Set the start countdown value into the RTC WAKE register */ - base->WAKE_TIMER_CNT = wakeupValue; -} - -/*! - * @brief Read the actual value from the WAKE register value in RTC wake timer. - * - * @param base RTC peripheral base address - * - * @return The actual value of the WAKE register value in wake timer counter. - */ -static inline uint32_t IRTC_GetWakeupCount(RTC_Type *base) -{ - /* Read current wake-up countdown value */ - return base->WAKE_TIMER_CNT; -} - -/*! @}*/ -#endif - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_IRTC_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_itrc.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_itrc.c deleted file mode 100644 index af31f6c1842..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_itrc.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - * Copyright 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_itrc.h" - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.itrc" -#endif - -#define b11 0x3u -#define b10 0x2u -#define b01 0x1u - -/* Value used to trigger SW Events */ -#define SW_EVENT_VAL 0x5AA55AA5u - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * Weak implementation of ITRC IRQ, should be re-defined by user when using ITRC IRQ - */ -__WEAK void ITRC0_DriverIRQHandler(void) -{ - /* ITRC generates IRQ until corresponding bit in STATUS is cleared by calling - * ITRC_ClearStatus(ITRC,((uint32_t)kITRC_Irq) - */ -} - -/*! - * brief Clear ITRC status - * - * This function clears corresponding ITRC event or action in STATUS register. - * - * param base ITRC peripheral base address - * param word 32bit word represent corresponding event/action in STATUS register to be cleared (see - * ITRC_STATUS_INx/OUTx_STATUS) - * return kStatus_Success if success, kStatus_InvalidArgument otherwise - */ -status_t ITRC_ClearStatus(ITRC_Type *base, uint32_t word) -{ - /* If reserved/unused bits in STATUS register are set in 'word' parameter, return kStatus_InvalidArgument */ - if ((word & ~(IN_EVENTS_MASK | OUT_ACTIONS_MASK)) != 0u) - { - return kStatus_InvalidArgument; - } - - base->STATUS |= word; - - return kStatus_Success; -} - -/*! - * brief Clear all ITRC status - * - * This clears all event and action status. - * - * param base ITRC peripheral base address - * return Status of the ITRC - */ -status_t ITRC_ClearAllStatus(ITRC_Type *base) -{ - base->STATUS |= (IN_EVENTS_MASK | OUT_ACTIONS_MASK); - - return kStatus_Success; -} - -/*! - * brief Trigger ITRC SW Event 0 - * - * This funciton set SW_EVENT0 register with value !=0 which triggers ITRC SW Event 0. - * - * param base ITRC peripheral base address - */ -void ITRC_SetSWEvent0(ITRC_Type *base) -{ - base->SW_EVENT0 = SW_EVENT_VAL; -} - -/*! - * brief Trigger ITRC SW Event 1 - * - * This funciton set SW_EVENT1 register with value !=0 which triggers ITRC SW Event 1. - * - * param base ITRC peripheral base address - */ -void ITRC_SetSWEvent1(ITRC_Type *base) -{ - base->SW_EVENT1 = SW_EVENT_VAL; -} - -/*! - * brief Set ITRC Action to Event - * - * This function sets input Event signal to corresponding output Action response signal. - * - * param base ITRC peripheral base address - * param out ITRC OUT signal action - * param in ITRC IN signal event - * param lock if set locks INx_SEL configuration. This can be cleared only by PMC Core reset. - * param enable if set input Event will be selected for output Action, otherwise disable (if not already locked). - * return kStatus_Success if success, kStatus_InvalidArgument otherwise - */ -status_t ITRC_SetActionToEvent( - ITRC_Type *base, itrc_out_signals_t out, itrc_input_signals_t in, itrc_lock_t lock, itrc_enable_t enable) -{ - uint32_t sel0, sel1, index, select_AND_mask; - - /* prepare values for INx_SEL0/1 bit-field according to secure techniques and register behavior - * +------------+------------+------------------+---------------------------+ - * | INx_SEL0 | INx_SEL1 | Signal selected? | Writable field? | - * +------------+------------+------------------+---------------------------+ - * | 10 | 10 | No | Yes (default after reset) | - * | 01 | 10 | Yes | Yes | - * | don't care | !="10" | Yes | No | - * | 00 or 11 | don't care | Yes | No | - * +------------+------------+------------------+---------------------------+ - */ - if ((lock == kITRC_Unlock) && (enable == kITRC_Disable)) - { - sel0 = b10; - sel1 = b10; - } - else if ((lock == kITRC_Unlock) && (enable == kITRC_Enable)) - { - sel0 = b01; - sel1 = b10; - } - else - { - sel0 = b11; - sel1 = b11; - } - - /* Compute index for INx_SEL0/1 bit-field within OUTy_SEL0/1 registers */ - index = 2u * in; - /* Prepare AND mask to set INx_SEL0 accordingly */ - select_AND_mask = ~(b11 << index); - - /* Last possible index in OUTx_SELy registers is 30 */ - if (index > 30u) - { - return kStatus_InvalidArgument; - } - - switch (out) - { - case kITRC_Irq: - base->OUT0_SEL0 = (base->OUT0_SEL0 & select_AND_mask) | (sel0 << index); - base->OUT0_SEL1 |= sel1 << index; - break; - case kITRC_CssReset: - base->OUT1_SEL0 = (base->OUT1_SEL0 & select_AND_mask) | (sel0 << index); - base->OUT1_SEL1 |= sel1 << index; - break; - - case kITRC_PufZeroize: - base->OUT2_SEL0 = (base->OUT2_SEL0 & select_AND_mask) | (sel0 << index); - base->OUT2_SEL1 |= sel1 << index; - break; - - case kITRC_RamZeroize: - base->OUT3_SEL0 = (base->OUT3_SEL0 & select_AND_mask) | (sel0 << index); - base->OUT3_SEL1 |= sel1 << index; - break; - - case kITRC_ChipReset: - base->OUT4_SEL0 = (base->OUT4_SEL0 & select_AND_mask) | (sel0 << index); - base->OUT4_SEL1 |= sel1 << index; - break; - - case kITRC_TamperOut: - base->OUT5_SEL0 = (base->OUT5_SEL0 & select_AND_mask) | (sel0 << index); - base->OUT5_SEL1 |= sel1 << index; - break; - default: - /* This case shouldn't be reached. */ - return kStatus_InvalidArgument; - } - - return kStatus_Success; -} - -/*! - * brief Get ITRC Status - * - * This function returns ITRC register status. - * - * param base ITRC peripheral base address - * return Value of ITRC STATUS register - */ -status_t ITRC_GetStatus(ITRC_Type *base) -{ - return base->STATUS; -} - -/*! - * brief Initialize ITRC - * - * This function initializes ITRC by enabling IRQ. - * - * param base ITRC peripheral base address - * return Status of the init operation - */ -status_t ITRC_Init(ITRC_Type *base) -{ - NVIC_EnableIRQ(ITRC0_IRQn); - - return kStatus_Success; -} - -/*! - * brief Deinitialize ITRC - * - * This function just disable ITRC IRQ. - * - * param base ITRC peripheral base address - */ -void ITRC_Deinit(ITRC_Type *base) -{ - NVIC_DisableIRQ(ITRC0_IRQn); -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_itrc.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_itrc.h deleted file mode 100644 index 877134aa4d9..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_itrc.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Copyright 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_ITRC_H_ -#define _FSL_ITRC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup ITRC - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Defines ITRC driver version 2.1.0. - * - * Change log: - * - Version 2.1.0 - * - Make SYSCON glitch platform dependent - * - Version 2.0.0 - * - initial version - */ -#define FSL_ITRC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) -/*@}*/ - -typedef enum _itrc_input_signals -{ - kITRC_CssGlitch = 0U, - kITRC_RtcTamper = 1U, - kITRC_Cdog = 2U, - kITRC_BodVbat = 3u, - kITRC_BodVdd = 4u, - kITRC_Watchdog = 5u, - kITRC_FlashEcc = 6u, - kITRC_Ahb = 7u, - kITRC_CssErr = 8u, -#if defined(FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH) && (FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH > 0) - kITRC_SysconGlitch = 9u, -#endif - kITRC_Pkc = 10u, - kITRC_SwEvent1 = 14u, - kITRC_SwEvent2 = 15u -} itrc_input_signals_t; - -typedef enum _itrc_lock -{ - kITRC_Unlock = 0U, - kITRC_Lock = 1U, -} itrc_lock_t; - -typedef enum _itrc_enable -{ - kITRC_Enable = 0U, - kITRC_Disable = 1U, -} itrc_enable_t; - -typedef enum _itrc_out_signals -{ - kITRC_Irq = 16U, - kITRC_CssReset = 17U, - kITRC_PufZeroize = 18U, - kITRC_RamZeroize = 19u, - kITRC_ChipReset = 20u, - kITRC_TamperOut = 21u, -} itrc_out_signals_t; - -#if defined(FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH) && (FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH > 0) -#define IN_EVENTS_MASK \ - (ITRC_STATUS_IN0_STATUS_MASK | ITRC_STATUS_IN1_STATUS_MASK | ITRC_STATUS_IN2_STATUS_MASK | \ - ITRC_STATUS_IN3_STATUS_MASK | ITRC_STATUS_IN4_STATUS_MASK | ITRC_STATUS_IN5_STATUS_MASK | \ - ITRC_STATUS_IN6_STATUS_MASK | ITRC_STATUS_IN7_STATUS_MASK | ITRC_STATUS_IN8_STATUS_MASK | \ - ITRC_STATUS_IN9_STATUS_MASK | ITRC_STATUS_IN10_STATUS_MASK | ITRC_STATUS_IN14_STATUS_MASK | \ - ITRC_STATUS_IN15_STATUS_MASK) -#else -#define IN_EVENTS_MASK \ - (ITRC_STATUS_IN0_STATUS_MASK | ITRC_STATUS_IN1_STATUS_MASK | ITRC_STATUS_IN2_STATUS_MASK | \ - ITRC_STATUS_IN3_STATUS_MASK | ITRC_STATUS_IN4_STATUS_MASK | ITRC_STATUS_IN5_STATUS_MASK | \ - ITRC_STATUS_IN6_STATUS_MASK | ITRC_STATUS_IN7_STATUS_MASK | ITRC_STATUS_IN8_STATUS_MASK | \ - ITRC_STATUS_IN10_STATUS_MASK | ITRC_STATUS_IN14_STATUS_MASK | ITRC_STATUS_IN15_STATUS_MASK) -#endif /* FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH */ - -#define OUT_ACTIONS_MASK \ - (ITRC_STATUS_OUT0_STATUS_MASK | ITRC_STATUS_OUT1_STATUS_MASK | ITRC_STATUS_OUT2_STATUS_MASK | \ - ITRC_STATUS_OUT3_STATUS_MASK | ITRC_STATUS_OUT4_STATUS_MASK | ITRC_STATUS_OUT5_STATUS_MASK) - -#ifndef ITRC -#define ITRC ITRC0 -#endif - -/******************************************************************************* - * API - *******************************************************************************/ - -extern void ITRC0_DriverIRQHandler(void); - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name ITRC Functional Operation - * @{ - */ - -/*! - * @brief Set ITRC Action to Event - * - * This function sets input Event signal to corresponding output Action response signal. - * - * @param base ITRC peripheral base address - * @param out ITRC OUT signal action - * @param in ITRC IN signal event - * @param lock if set locks INx_SEL configuration. This can be cleared only by PMC Core reset. - * @param enable if set input Event will be selected for output Action, otherwise disable (if not already locked). - * @return kStatus_Success if success, kStatus_InvalidArgument otherwise - */ -status_t ITRC_SetActionToEvent( - ITRC_Type *base, itrc_out_signals_t out, itrc_input_signals_t in, itrc_lock_t lock, itrc_enable_t enable); - -/*! - * @brief Trigger ITRC SW Event 0 - * - * This funciton set SW_EVENT0 register with value !=0 which triggers ITRC SW Event 0. - * - * @param base ITRC peripheral base address - */ -void ITRC_SetSWEvent0(ITRC_Type *base); - -/*! - * @brief Trigger ITRC SW Event 1 - * - * This funciton set SW_EVENT1 register with value !=0 which triggers ITRC SW Event 1. - * - * @param base ITRC peripheral base address - */ -void ITRC_SetSWEvent1(ITRC_Type *base); - -/*! - * @brief Get ITRC Status - * - * This function returns ITRC register status. - * - * @param base ITRC peripheral base address - * @return Value of ITRC STATUS register - */ -status_t ITRC_GetStatus(ITRC_Type *base); - -/*! - * @brief Clear ITRC status - * - * This function clears corresponding ITRC event or action in STATUS register. - * - * @param base ITRC peripheral base address - * @param word 32bit word represent corresponding event/action in STATUS register to be cleared (see - * ITRC_STATUS_INx/OUTx_STATUS) - * @return kStatus_Success if success, kStatus_InvalidArgument otherwise - */ -status_t ITRC_ClearStatus(ITRC_Type *base, uint32_t word); - -/*! - * @brief Clear All ITRC status - * - * This function clears all event and action status. - * - * @param base ITRC peripheral base address - * @return kStatus_Success if success - */ -status_t ITRC_ClearAllStatus(ITRC_Type *base); - -/*! - * @brief Initialize ITRC - * - * This function initializes ITRC by enabling IRQ. - * - * @param base ITRC peripheral base address - * @param conf ITRC configuration structure - * @return Status of the init operation - */ -status_t ITRC_Init(ITRC_Type *base); - -/*! - * @brief Deinitialize ITRC - * - * This function deinitializes ITRC by disabling IRQ. - * - * @param base ITRC peripheral base address - */ -void ITRC_Deinit(ITRC_Type *base); - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ /* end of group itrc */ - -#endif /* _FSL_ITRC_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_lpadc.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_lpadc.c deleted file mode 100644 index 7835e6fc454..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_lpadc.c +++ /dev/null @@ -1,612 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_lpadc.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpadc" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for LPADC module. - * - * @param base LPADC peripheral base address - */ -static uint32_t LPADC_GetInstance(ADC_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to LPADC bases for each instance. */ -static ADC_Type *const s_lpadcBases[] = ADC_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to LPADC clocks for each instance. */ -static const clock_ip_name_t s_lpadcClocks[] = LPADC_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t LPADC_GetInstance(ADC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_lpadcBases); instance++) - { - if (s_lpadcBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_lpadcBases)); - - return instance; -} - -/*! - * brief Initializes the LPADC module. - * - * param base LPADC peripheral base address. - * param config Pointer to configuration structure. See "lpadc_config_t". - */ -void LPADC_Init(ADC_Type *base, const lpadc_config_t *config) -{ - /* Check if the pointer is available. */ - assert(config != NULL); - - uint32_t tmp32 = 0U; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock for LPADC instance. */ - (void)CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the module. */ - LPADC_DoResetConfig(base); -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - LPADC_DoResetFIFO0(base); - LPADC_DoResetFIFO1(base); -#else - LPADC_DoResetFIFO(base); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - - /* Disable the module before setting configuration. */ - LPADC_Enable(base, false); - - /* Configure the module generally. */ - if (config->enableInDozeMode) - { - base->CTRL &= ~ADC_CTRL_DOZEN_MASK; - } - else - { - base->CTRL |= ADC_CTRL_DOZEN_MASK; - } - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS - /* Set calibration average mode. */ - base->CTRL |= ADC_CTRL_CAL_AVGS(config->conversionAverageMode); -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - -/* ADCx_CFG. */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - if (config->enableInternalClock) - { - tmp32 |= ADC_CFG_ADCKEN_MASK; - } -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - if (config->enableVref1LowVoltage) - { - tmp32 |= ADC_CFG_VREF1RNG_MASK; - } -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - if (config->enableAnalogPreliminary) - { - tmp32 |= ADC_CFG_PWREN_MASK; - } - tmp32 |= ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */ - | ADC_CFG_REFSEL(config->referenceVoltageSource) /* Reference voltage. */ - | ADC_CFG_PWRSEL(config->powerLevelMode) /* Power configuration. */ - | ADC_CFG_TPRICTRL(config->triggerPriorityPolicy); /* Trigger priority policy. */ - base->CFG = tmp32; - - /* ADCx_PAUSE. */ - if (config->enableConvPause) - { - base->PAUSE = ADC_PAUSE_PAUSEEN_MASK | ADC_PAUSE_PAUSEDLY(config->convPauseDelay); - } - else - { - base->PAUSE = 0U; - } - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - /* ADCx_FCTRL0. */ - base->FCTRL[0] = ADC_FCTRL_FWMARK(config->FIFO0Watermark); - /* ADCx_FCTRL1. */ - base->FCTRL[1] = ADC_FCTRL_FWMARK(config->FIFO1Watermark); -#else - /* ADCx_FCTRL. */ - base->FCTRL = ADC_FCTRL_FWMARK(config->FIFOWatermark); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - - /* Enable the module after setting configuration. */ - LPADC_Enable(base, true); -} - -/*! - * brief Gets an available pre-defined settings for initial configuration. - * - * This function initializes the converter configuration structure with an available settings. The default values are: - * code - * config->enableInDozeMode = true; - * config->conversionAverageMode = kLPADC_ConversionAverage1; - * config->enableAnalogPreliminary = false; - * config->powerUpDelay = 0x80; - * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - * config->powerLevelMode = kLPADC_PowerLevelAlt1; - * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; - * config->enableConvPause = false; - * config->convPauseDelay = 0U; - * config->FIFO0Watermark = 0U; - * config->FIFO1Watermark = 0U; - * config->FIFOWatermark = 0U; - * endcode - * param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConfig(lpadc_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - config->enableInternalClock = false; -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - config->enableVref1LowVoltage = false; -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - config->enableInDozeMode = true; -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS - /* Set calibration average mode. */ - config->conversionAverageMode = kLPADC_ConversionAverage1; -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - config->enableAnalogPreliminary = false; - config->powerUpDelay = 0x80; - config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - config->powerLevelMode = kLPADC_PowerLevelAlt1; - config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; - config->enableConvPause = false; - config->convPauseDelay = 0U; -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - config->FIFO0Watermark = 0U; - config->FIFO1Watermark = 0U; -#else - config->FIFOWatermark = 0U; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ -} - -/*! - * brief De-initializes the LPADC module. - * - * param base LPADC peripheral base address. - */ -void LPADC_Deinit(ADC_Type *base) -{ - /* Disable the module. */ - LPADC_Enable(base, false); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the clock. */ - (void)CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * brief Get the result in conversion FIFOn. - * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. - * param index Result FIFO index. - * - * return Status whether FIFOn entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index) -{ - assert(result != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - tmp32 = base->RESFIFO[index]; - - if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) - { - return false; /* FIFO is empty. Discard any read from RESFIFO. */ - } - - result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; - result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; - result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; - result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); - - return true; -} -#else -/*! - * brief Get the result in conversion FIFO. - * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFO. - * - * return Status whether FIFO entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result) -{ - assert(result != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - tmp32 = base->RESFIFO; - - if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) - { - return false; /* FIFO is empty. Discard any read from RESFIFO. */ - } - - result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; - result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; - result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; - result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); - - return true; -} -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * brief Configure the conversion trigger source. - * - * Each programmable trigger can launch the conversion command in command buffer. - * - * param base LPADC peripheral base address. - * param triggerId ID for each trigger. Typically, the available value range is from 0. - * param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. - */ -void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config) -{ - assert(triggerId < ADC_TCTRL_COUNT); /* Check if the triggerId is available in this device. */ - assert(config != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - tmp32 = ADC_TCTRL_TCMD(config->targetCommandId) /* Trigger command select. */ - | ADC_TCTRL_TDLY(config->delayPower) /* Trigger delay select. */ - | ADC_TCTRL_TPRI(config->priority) /* Trigger priority setting. */ -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - | ADC_TCTRL_FIFO_SEL_A(config->channelAFIFOSelect) -#if !(defined(FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) && FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) - | ADC_TCTRL_FIFO_SEL_B(config->channelBFIFOSelect) -#endif /* FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - ; - if (config->enableHardwareTrigger) - { - tmp32 |= ADC_TCTRL_HTEN_MASK; - } - - base->TCTRL[triggerId] = tmp32; -} - -/*! - * brief Gets an available pre-defined settings for trigger's configuration. - * - * This function initializes the trigger's configuration structure with an available settings. The default values are: - * code - * config->commandIdSource = 0U; - * config->loopCountIndex = 0U; - * config->triggerIdSource = 0U; - * config->enableHardwareTrigger = false; - * config->channelAFIFOSelect = 0U; - * config->channelBFIFOSelect = 0U; - * endcode - * param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config) -{ - assert(config != NULL); /* Check if the input pointer is available. */ - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->targetCommandId = 0U; - config->delayPower = 0U; - config->priority = 0U; -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - config->channelAFIFOSelect = 0U; - config->channelBFIFOSelect = 0U; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - config->enableHardwareTrigger = false; -} - -/*! - * brief Configure conversion command. - * - * param base LPADC peripheral base address. - * param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. - * param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. - */ -void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config) -{ - assert(commandId < (ADC_CMDL_COUNT + 1U)); /* Check if the commandId is available on this device. */ - assert(config != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32 = 0; - - commandId--; /* The available command number are 1-15, while the index of register group are 0-14. */ - - /* ADCx_CMDL. */ - tmp32 = ADC_CMDL_ADCH(config->channelNumber); /* Channel number. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - tmp32 |= ADC_CMDL_CSCALE(config->sampleScaleMode); /* Full/Part scale input voltage. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE - tmp32 |= ADC_CMDL_CTYPE(config->sampleChannelMode); -#else - switch (config->sampleChannelMode) /* Sample input. */ - { - case kLPADC_SampleChannelSingleEndSideB: - tmp32 |= ADC_CMDL_ABSEL_MASK; - break; -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF - case kLPADC_SampleChannelDiffBothSideAB: - tmp32 |= ADC_CMDL_DIFF_MASK; - break; - case kLPADC_SampleChannelDiffBothSideBA: - tmp32 |= ADC_CMDL_ABSEL_MASK | ADC_CMDL_DIFF_MASK; - break; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_DIFF */ - default: /* kLPADC_SampleChannelSingleEndSideA. */ - break; - } -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - tmp32 |= ADC_CMDL_MODE(config->conversionResolutionMode); -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ - base->CMD[commandId].CMDL = tmp32; - - /* ADCx_CMDH. */ - tmp32 = ADC_CMDH_NEXT(config->chainedNextCommandNumber) /* Next Command Select. */ - | ADC_CMDH_LOOP(config->loopCount) /* Loop Count Select. */ - | ADC_CMDH_AVGS(config->hardwareAverageMode) /* Hardware Average Select. */ - | ADC_CMDH_STS(config->sampleTimeMode) /* Sample Time Select. */ - | ADC_CMDH_CMPEN(config->hardwareCompareMode); /* Hardware compare enable. */ -#if (defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) - if (config->enableWaitTrigger) - { - tmp32 |= ADC_CMDH_WAIT_TRIG_MASK; /* Wait trigger enable. */ - } -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ - - if (config->enableAutoChannelIncrement) - { - tmp32 |= ADC_CMDH_LWI_MASK; - } - base->CMD[commandId].CMDH = tmp32; - - /* Hardware compare settings. - * Not all Command Buffers have an associated Compare Value register. The compare function is only available on - * Command Buffers that have a corresponding Compare Value register. - */ - if (kLPADC_HardwareCompareDisabled != config->hardwareCompareMode) - { - /* Check if the hardware compare feature is available for indicated command buffer. */ - assert(commandId < ADC_CV_COUNT); - - /* Set CV register. */ - base->CV[commandId] = ADC_CV_CVH(config->hardwareCompareValueHigh) /* Compare value high. */ - | ADC_CV_CVL(config->hardwareCompareValueLow); /* Compare value low. */ - } -} - -/*! - * brief Gets an available pre-defined settings for conversion command's configuration. - * - * This function initializes the conversion command's configuration structure with an available settings. The default - * values are: - * code - * config->sampleScaleMode = kLPADC_SampleFullScale; - * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; - * config->channelNumber = 0U; - * config->chainedNextCmdNumber = 0U; - * config->enableAutoChannelIncrement = false; - * config->loopCount = 0U; - * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - * config->sampleTimeMode = kLPADC_SampleTimeADCK3; - * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - * config->hardwareCompareValueHigh = 0U; - * config->hardwareCompareValueLow = 0U; - * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; - * config->enableWaitTrigger = false; - * endcode - * param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config) -{ - assert(config != NULL); /* Check if the input pointer is available. */ - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - config->sampleScaleMode = kLPADC_SampleFullScale; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ - config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; - config->channelNumber = 0U; - config->chainedNextCommandNumber = 0U; /* No next command defined. */ - config->enableAutoChannelIncrement = false; - config->loopCount = 0U; - config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - config->sampleTimeMode = kLPADC_SampleTimeADCK3; - config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - config->hardwareCompareValueHigh = 0U; /* No used. */ - config->hardwareCompareValueLow = 0U; /* No used. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG - config->enableWaitTrigger = false; -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ -} - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS -/*! - * brief Enable the calibration function. - * - * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes - * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value - * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- - * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the - * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. - * - * param base LPADC peripheral base address. - * param enable switcher to the calibration function. - */ -void LPADC_EnableCalibration(ADC_Type *base, bool enable) -{ - LPADC_Enable(base, false); - if (enable) - { - base->CFG |= ADC_CFG_CALOFS_MASK; - } - else - { - base->CFG &= ~ADC_CFG_CALOFS_MASK; - } - LPADC_Enable(base, true); -} - -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! - * brief Do auto calibration. - * - * Calibration function should be executed before using converter in application. It used the software trigger and a - * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API - * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) - * -LPADC_SetConvTriggerConfig(...) - * - * param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base) -{ - assert(0u == LPADC_GetConvResultCount(base)); - - uint32_t mLpadcCMDL; - uint32_t mLpadcCMDH; - uint32_t mLpadcTrigger; - lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct; - lpadc_conv_command_config_t mLpadcCommandConfigStruct; - lpadc_conv_result_t mLpadcResultConfigStruct; - - /* Enable the calibration function. */ - LPADC_EnableCalibration(base, true); - - /* Keep the CMD and TRG state here and restore it later if the calibration completes.*/ - mLpadcCMDL = base->CMD[0].CMDL; /* CMD1L. */ - mLpadcCMDH = base->CMD[0].CMDH; /* CMD1H. */ - mLpadcTrigger = base->TCTRL[0]; /* Trigger0. */ - - /* Set trigger0 configuration - for software trigger. */ - LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct); - mLpadcTriggerConfigStruct.targetCommandId = 1U; /* CMD1 is executed. */ - LPADC_SetConvTriggerConfig(base, 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */ - - /* Set conversion CMD configuration. */ - LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct); - mLpadcCommandConfigStruct.hardwareAverageMode = kLPADC_HardwareAverageCount128; - LPADC_SetConvCommandConfig(base, 1U, &mLpadcCommandConfigStruct); /* Set CMD1 configuration. */ - - /* Do calibration. */ - LPADC_DoSoftwareTrigger(base, 1U); /* 1U is trigger0 mask. */ - while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct)) - { - } - /* The valid bits of data are bits 14:3 in the RESFIFO register. */ - LPADC_SetOffsetValue(base, (uint32_t)(mLpadcResultConfigStruct.convValue) >> 3UL); - /* Disable the calibration function. */ - LPADC_EnableCalibration(base, false); - - /* restore CMD and TRG registers. */ - base->CMD[0].CMDL = mLpadcCMDL; /* CMD1L. */ - base->CMD[0].CMDH = mLpadcCMDH; /* CMD1H. */ - base->TCTRL[0] = mLpadcTrigger; /* Trigger0. */ -} -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS -/*! - * brief Do offset calibration. - * - * param base LPADC peripheral base address. - */ -void LPADC_DoOffsetCalibration(ADC_Type *base) -{ - LPADC_EnableOffsetCalibration(base, true); - while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) - { - } -} - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ -/*! - * brief Do auto calibration. - * - * param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base) -{ - assert((0u == LPADC_GetConvResultCount(base, 0)) && (0u == LPADC_GetConvResultCount(base, 1))); - - uint32_t GCCa; - uint32_t GCCb; - uint32_t GCRa; - uint32_t GCRb; - - /* Request gain calibration. */ - base->CTRL |= ADC_CTRL_CAL_REQ_MASK; - while ((ADC_GCC_RDY_MASK != (base->GCC[0] & ADC_GCC_RDY_MASK)) || - (ADC_GCC_RDY_MASK != (base->GCC[1] & ADC_GCC_RDY_MASK))) - { - } - - /* Calculate gain offset. */ - GCCa = (base->GCC[0] & ADC_GCC_GAIN_CAL_MASK); - GCCb = (base->GCC[1] & ADC_GCC_GAIN_CAL_MASK); - GCRa = (uint16_t)((GCCa << 16U) / - (0x1FFFFU - GCCa)); /* Gain_CalA = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[0])) - 1. */ - GCRb = (uint16_t)((GCCb << 16U) / - (0x1FFFFU - GCCb)); /* Gain_CalB = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[1])) - 1. */ - base->GCR[0] = ADC_GCR_GCALR(GCRa); - base->GCR[1] = ADC_GCR_GCALR(GCRb); - - /* Indicate the values are valid. */ - base->GCR[0] |= ADC_GCR_RDY_MASK; - base->GCR[1] |= ADC_GCR_RDY_MASK; - - while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) - { - } -} -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_lpadc.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_lpadc.h deleted file mode 100644 index cc5429d69b5..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_lpadc.h +++ /dev/null @@ -1,928 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_LPADC_H_ -#define _FSL_LPADC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpadc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPADC driver version 2.4.0. */ -#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) -/*@}*/ - -/*! - * @brief Define the MACRO function to get command status from status value. - * - * The statusVal is the return value from LPADC_GetStatusFlags(). - */ -#define LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal) ((statusVal & ADC_STAT_CMDACT_MASK) >> ADC_STAT_CMDACT_SHIFT) - -/*! - * @brief Define the MACRO function to get trigger status from status value. - * - * The statusVal is the return value from LPADC_GetStatusFlags(). - */ -#define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT) - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Define hardware flags of the module. - */ -enum _lpadc_status_flags -{ - kLPADC_ResultFIFO0OverflowFlag = ADC_STAT_FOF0_MASK, /*!< Indicates that more data has been written to the Result - FIFO 0 than it can hold. */ - kLPADC_ResultFIFO0ReadyFlag = ADC_STAT_RDY0_MASK, /*!< Indicates when the number of valid datawords in the result - FIFO 0 is greater than the setting watermark level. */ - kLPADC_ResultFIFO1OverflowFlag = ADC_STAT_FOF1_MASK, /*!< Indicates that more data has been written to the Result - FIFO 1 than it can hold. */ - kLPADC_ResultFIFO1ReadyFlag = ADC_STAT_RDY1_MASK, /*!< Indicates when the number of valid datawords in the result - FIFO 1 is greater than the setting watermark level. */ -}; - -/*! - * @brief Define interrupt switchers of the module. - */ -enum _lpadc_interrupt_enable -{ - kLPADC_ResultFIFO0OverflowInterruptEnable = ADC_IE_FOFIE0_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF0 flag is asserted. */ - kLPADC_FIFO0WatermarkInterruptEnable = ADC_IE_FWMIE0_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY0 flag is asserted. */ - kLPADC_ResultFIFO1OverflowInterruptEnable = ADC_IE_FOFIE1_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF1 flag is asserted. */ - kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY1 flag is asserted. */ -}; -#else -/*! - * @brief Define hardware flags of the module. - */ -enum _lpadc_status_flags -{ - kLPADC_ResultFIFOOverflowFlag = ADC_STAT_FOF_MASK, /*!< Indicates that more data has been written to the Result FIFO - than it can hold. */ - kLPADC_ResultFIFOReadyFlag = ADC_STAT_RDY_MASK, /*!< Indicates when the number of valid datawords in the result FIFO - is greater than the setting watermark level. */ -}; - -/*! - * @brief Define interrupt switchers of the module. - */ -enum _lpadc_interrupt_enable -{ - kLPADC_ResultFIFOOverflowInterruptEnable = ADC_IE_FOFIE_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF flag is asserted. */ - kLPADC_FIFOWatermarkInterruptEnable = ADC_IE_FWMIE_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY flag is asserted. */ -}; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) -/*! - * @brief The enumerator of lpadc trigger status flags, including interrupted flags and completed flags. - */ -enum _lpadc_trigger_status_flags -{ - kLPADC_Trigger0InterruptedFlag = 1UL << 0UL, /*!< Trigger 0 is interrupted by a high priority exception. */ - kLPADC_Trigger1InterruptedFlag = 1UL << 1UL, /*!< Trigger 1 is interrupted by a high priority exception. */ - kLPADC_Trigger2InterruptedFlag = 1UL << 2UL, /*!< Trigger 2 is interrupted by a high priority exception. */ - kLPADC_Trigger3InterruptedFlag = 1UL << 3UL, /*!< Trigger 3 is interrupted by a high priority exception. */ - kLPADC_Trigger4InterruptedFlag = 1UL << 4UL, /*!< Trigger 4 is interrupted by a high priority exception. */ - kLPADC_Trigger5InterruptedFlag = 1UL << 5UL, /*!< Trigger 5 is interrupted by a high priority exception. */ - kLPADC_Trigger6InterruptedFlag = 1UL << 6UL, /*!< Trigger 6 is interrupted by a high priority exception. */ - kLPADC_Trigger7InterruptedFlag = 1UL << 7UL, /*!< Trigger 7 is interrupted by a high priority exception. */ - kLPADC_Trigger8InterruptedFlag = 1UL << 8UL, /*!< Trigger 8 is interrupted by a high priority exception. */ - kLPADC_Trigger9InterruptedFlag = 1UL << 9UL, /*!< Trigger 9 is interrupted by a high priority exception. */ - kLPADC_Trigger10InterruptedFlag = 1UL << 10UL, /*!< Trigger 10 is interrupted by a high priority exception. */ - kLPADC_Trigger11InterruptedFlag = 1UL << 11UL, /*!< Trigger 11 is interrupted by a high priority exception. */ - kLPADC_Trigger12InterruptedFlag = 1UL << 12UL, /*!< Trigger 12 is interrupted by a high priority exception. */ - kLPADC_Trigger13InterruptedFlag = 1UL << 13UL, /*!< Trigger 13 is interrupted by a high priority exception. */ - kLPADC_Trigger14InterruptedFlag = 1UL << 14UL, /*!< Trigger 14 is interrupted by a high priority exception. */ - kLPADC_Trigger15InterruptedFlag = 1UL << 15UL, /*!< Trigger 15 is interrupted by a high priority exception. */ - - kLPADC_Trigger0CompletedFlag = 1UL << 16UL, /*!< Trigger 0 is completed and - trigger 0 has enabled completion interrupts. */ - kLPADC_Trigger1CompletedFlag = 1UL << 17UL, /*!< Trigger 1 is completed and - trigger 1 has enabled completion interrupts. */ - kLPADC_Trigger2CompletedFlag = 1UL << 18UL, /*!< Trigger 2 is completed and - trigger 2 has enabled completion interrupts. */ - kLPADC_Trigger3CompletedFlag = 1UL << 19UL, /*!< Trigger 3 is completed and - trigger 3 has enabled completion interrupts. */ - kLPADC_Trigger4CompletedFlag = 1UL << 20UL, /*!< Trigger 4 is completed and - trigger 4 has enabled completion interrupts. */ - kLPADC_Trigger5CompletedFlag = 1UL << 21UL, /*!< Trigger 5 is completed and - trigger 5 has enabled completion interrupts. */ - kLPADC_Trigger6CompletedFlag = 1UL << 22UL, /*!< Trigger 6 is completed and - trigger 6 has enabled completion interrupts. */ - kLPADC_Trigger7CompletedFlag = 1UL << 23UL, /*!< Trigger 7 is completed and - trigger 7 has enabled completion interrupts. */ - kLPADC_Trigger8CompletedFlag = 1UL << 24UL, /*!< Trigger 8 is completed and - trigger 8 has enabled completion interrupts. */ - kLPADC_Trigger9CompletedFlag = 1UL << 25UL, /*!< Trigger 9 is completed and - trigger 9 has enabled completion interrupts. */ - kLPADC_Trigger10CompletedFlag = 1UL << 26UL, /*!< Trigger 10 is completed and - trigger 10 has enabled completion interrupts. */ - kLPADC_Trigger11CompletedFlag = 1UL << 27UL, /*!< Trigger 11 is completed and - trigger 11 has enabled completion interrupts. */ - kLPADC_Trigger12CompletedFlag = 1UL << 28UL, /*!< Trigger 12 is completed and - trigger 12 has enabled completion interrupts. */ - kLPADC_Trigger13CompletedFlag = 1UL << 29UL, /*!< Trigger 13 is completed and - trigger 13 has enabled completion interrupts. */ - kLPADC_Trigger14CompletedFlag = 1UL << 30UL, /*!< Trigger 14 is completed and - trigger 14 has enabled completion interrupts. */ - kLPADC_Trigger15CompletedFlag = 1UL << 31UL, /*!< Trigger 15 is completed and - trigger 15 has enabled completion interrupts. */ -}; -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ - -/*! - * @brief Define enumeration of sample scale mode. - * - * The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum - * possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the - * reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows - * conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode. - */ -typedef enum _lpadc_sample_scale_mode -{ - kLPADC_SamplePartScale = 0U, /*!< Use divided input voltage signal. (Factor of 30/64). */ - kLPADC_SampleFullScale = 1U, /*!< Full scale (Factor of 1). */ -} lpadc_sample_scale_mode_t; - -/*! - * @brief Define enumeration of channel sample mode. - * - * The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B. - */ -typedef enum _lpadc_sample_channel_mode -{ - kLPADC_SampleChannelSingleEndSideA = 0U, /*!< Single end mode, using side A. */ - kLPADC_SampleChannelSingleEndSideB = 1U, /*!< Single end mode, using side B. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF - kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minue side. */ - kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minue side. */ -#elif defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE - kLPADC_SampleChannelDiffBothSide = 2U, /*!< Differential mode, using A and B. */ - kLPADC_SampleChannelDualSingleEndBothSide = - 3U, /*!< Dual-Single-Ended Mode. Both A side and B side channels are converted independently. */ -#endif -} lpadc_sample_channel_mode_t; - -/*! - * @brief Define enumeration of hardware average selection. - * - * It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to - * capture temporary results while the averaging iterations are executed. - */ -typedef enum _lpadc_hardware_average_mode -{ - kLPADC_HardwareAverageCount1 = 0U, /*!< Single conversion. */ - kLPADC_HardwareAverageCount2 = 1U, /*!< 2 conversions averaged. */ - kLPADC_HardwareAverageCount4 = 2U, /*!< 4 conversions averaged. */ - kLPADC_HardwareAverageCount8 = 3U, /*!< 8 conversions averaged. */ - kLPADC_HardwareAverageCount16 = 4U, /*!< 16 conversions averaged. */ - kLPADC_HardwareAverageCount32 = 5U, /*!< 32 conversions averaged. */ - kLPADC_HardwareAverageCount64 = 6U, /*!< 64 conversions averaged. */ - kLPADC_HardwareAverageCount128 = 7U, /*!< 128 conversions averaged. */ -} lpadc_hardware_average_mode_t; - -/*! - * @brief Define enumeration of sample time selection. - * - * The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher - * impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption - * when command looping and sequencing is configured and high conversion rates are not required. - */ -typedef enum _lpadc_sample_time_mode -{ - kLPADC_SampleTimeADCK3 = 0U, /*!< 3 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK5 = 1U, /*!< 5 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK7 = 2U, /*!< 7 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK11 = 3U, /*!< 11 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK19 = 4U, /*!< 19 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK35 = 5U, /*!< 35 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK67 = 6U, /*!< 69 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK131 = 7U, /*!< 131 ADCK cycles total sample time. */ -} lpadc_sample_time_mode_t; - -/*! - * @brief Define enumeration of hardware compare mode. - * - * After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting - * guides operation of the automatic compare function to optionally only store when the compare operation is true. - * When compare is enabled, the conversion result is compared to the compare values. - */ -typedef enum _lpadc_hardware_compare_mode -{ - kLPADC_HardwareCompareDisabled = 0U, /*!< Compare disabled. */ - kLPADC_HardwareCompareStoreOnTrue = 2U, /*!< Compare enabled. Store on true. */ - kLPADC_HardwareCompareRepeatUntilTrue = 3U, /*!< Compare enabled. Repeat channel acquisition until true. */ -} lpadc_hardware_compare_mode_t; - -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE -/*! - * @brief Define enumeration of conversion resolution mode. - * - * Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to - * #lpadc_sample_channel_mode_t - */ -typedef enum _lpadc_conversion_resolution_mode -{ - kLPADC_ConversionResolutionStandard = 0U, /*!< Standard resolution. Single-ended 12-bit conversion, Differential - 13-bit conversion with 2’s complement output. */ - kLPADC_ConversionResolutionHigh = 1U, /*!< High resolution. Single-ended 16-bit conversion; Differential 16-bit - conversion with 2’s complement output. */ -} lpadc_conversion_resolution_mode_t; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS -/*! - * @brief Define enumeration of conversion averages mode. - * - * Configure the converion average number for auto-calibration. - */ -typedef enum _lpadc_conversion_average_mode -{ - kLPADC_ConversionAverage1 = 0U, /*!< Single conversion. */ - kLPADC_ConversionAverage2 = 1U, /*!< 2 conversions averaged. */ - kLPADC_ConversionAverage4 = 2U, /*!< 4 conversions averaged. */ - kLPADC_ConversionAverage8 = 3U, /*!< 8 conversions averaged. */ - kLPADC_ConversionAverage16 = 4U, /*!< 16 conversions averaged. */ - kLPADC_ConversionAverage32 = 5U, /*!< 32 conversions averaged. */ - kLPADC_ConversionAverage64 = 6U, /*!< 64 conversions averaged. */ - kLPADC_ConversionAverage128 = 7U, /*!< 128 conversions averaged. */ -} lpadc_conversion_average_mode_t; -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - -/*! - * @brief Define enumeration of reference voltage source. - * - * For detail information, need to check the SoC's specification. - */ -typedef enum _lpadc_reference_voltage_mode -{ - kLPADC_ReferenceVoltageAlt1 = 0U, /*!< Option 1 setting. */ - kLPADC_ReferenceVoltageAlt2 = 1U, /*!< Option 2 setting. */ - kLPADC_ReferenceVoltageAlt3 = 2U, /*!< Option 3 setting. */ -} lpadc_reference_voltage_source_t; - -/*! - * @brief Define enumeration of power configuration. - * - * Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be - * possible. Refer to the device data sheet for power and performance capabilities for each setting. - */ -typedef enum _lpadc_power_level_mode -{ - kLPADC_PowerLevelAlt1 = 0U, /*!< Lowest power setting. */ - kLPADC_PowerLevelAlt2 = 1U, /*!< Next lowest power setting. */ - kLPADC_PowerLevelAlt3 = 2U, /*!< ... */ - kLPADC_PowerLevelAlt4 = 3U, /*!< Highest power setting. */ -} lpadc_power_level_mode_t; - -/*! - * @brief Define enumeration of trigger priority policy. - * - * This selection controls how higher priority triggers are handled. - */ -typedef enum _lpadc_trigger_priority_policy -{ - kLPADC_TriggerPriorityPreemptImmediately = 0U, /*!< If a higher priority trigger is detected during command - processing, the current conversion is aborted and the new - command specified by the trigger is started. */ - kLPADC_TriggerPriorityPreemptSoftly = 1U, /*!< If a higher priority trigger is received during command processing, - the current conversion is completed (including averaging iterations - and compare function if enabled) and stored to the result FIFO - before the higher priority trigger/command is initiated. */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY) && FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY - kLPADC_TriggerPriorityPreemptSubsequently = 2U, /*!< If a higher priority trigger is received during command - processing, the current command will be completed (averaging, - looping, compare) before servicing the higher priority trigger. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY */ -} lpadc_trigger_priority_policy_t; - -/*! - * @brief LPADC global configuration. - * - * This structure would used to keep the settings for initialization. - */ -typedef struct -{ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock - selection logic at the chip level and is optionally used for the ADC clock source. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - bool enableVref1LowVoltage; /*!< If voltage reference option1 input is below 1.8V, it should be "true". - If voltage reference option1 input is above 1.8V, it should be "false". */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - bool enableInDozeMode; /*!< Control system transition to Stop and Wait power modes while ADC is converting. When - enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the - ADC will wait for the current averaging iteration/FIFO storage to complete before - acknowledging stop or wait mode entry. */ -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS - lpadc_conversion_average_mode_t conversionAverageMode; /*!< Auto-Calibration Averages. */ -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - bool enableAnalogPreliminary; /*!< ADC analog circuits are pre-enabled and ready to execute conversions without - startup delays(at the cost of higher DC current consumption). */ - uint32_t powerUpDelay; /*!< When the analog circuits are not pre-enabled, the ADC analog circuits are only powered - while the ADC is active and there is a counted delay defined by this field after an - initial trigger transitions the ADC from its Idle state to allow time for the analog - circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must - result in a longer delay than the analog startup time. */ - lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for - conversions.*/ - lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */ - lpadc_trigger_priority_policy_t triggerPriorityPolicy; /*!< Control how higher priority triggers are handled, see to - lpadc_trigger_priority_policy_mode_t. */ - bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during - command execution sequencing between LOOP iterations, between commands in a sequence, and - between conversions when command is executing in "Compare Until True" configuration. */ - uint32_t convPauseDelay; /*!< Controls the duration of pausing during command execution sequencing. The pause delay - is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing - function is enabled. The available value range is in 9-bit. */ -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - /* for FIFO0. */ - uint32_t FIFO0Watermark; /*!< FIFO0Watermark is a programmable threshold setting. When the number of datawords - stored in the ADC Result FIFO0 is greater than the value in this field, the ready flag - would be asserted to indicate stored data has reached the programmable threshold. */ - /* for FIFO1. */ - uint32_t FIFO1Watermark; /*!< FIFO1Watermark is a programmable threshold setting. When the number of datawords - stored in the ADC Result FIFO1 is greater than the value in this field, the ready flag - would be asserted to indicate stored data has reached the programmable threshold. */ -#else - /* for FIFO. */ - uint32_t FIFOWatermark; /*!< FIFOWatermark is a programmable threshold setting. When the number of datawords stored - in the ADC Result FIFO is greater than the value in this field, the ready flag would be - asserted to indicate stored data has reached the programmable threshold. */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ -} lpadc_config_t; - -/*! - * @brief Define structure to keep the configuration for conversion command. - */ -typedef struct -{ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ - lpadc_sample_channel_mode_t sampleChannelMode; /*!< Channel sample mode. */ - uint32_t channelNumber; /*!< Channel number, select the channel or channel pair. */ - uint32_t chainedNextCommandNumber; /*!< Selects the next command to be executed after this command completes. - 1-15 is available, 0 is to terminate the chain after this command. */ - bool enableAutoChannelIncrement; /*!< Loop with increment: when disabled, the "loopCount" field selects the number - of times the selected channel is converted consecutively; when enabled, the - "loopCount" field defines how many consecutive channels are converted as part - of the command execution. */ - uint32_t loopCount; /*!< Selects how many times this command executes before finish and transition to the next - command or Idle state. Command executes LOOP+1 times. 0-15 is available. */ - lpadc_hardware_average_mode_t hardwareAverageMode; /*!< Hardware average selection. */ - lpadc_sample_time_mode_t sampleTimeMode; /*!< Sample time selection. */ - - lpadc_hardware_compare_mode_t hardwareCompareMode; /*!< Hardware compare selection. */ - uint32_t hardwareCompareValueHigh; /*!< Compare Value High. The available value range is in 16-bit. */ - uint32_t hardwareCompareValueLow; /*!< Compare Value Low. The available value range is in 16-bit. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - lpadc_conversion_resolution_mode_t conversionResolutionMode; /*!< Conversion resolution mode. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG - bool enableWaitTrigger; /*!< Wait for trigger assertion before execution: when disabled, this command will be - automatically executed; when enabled, the active trigger must be asserted again before - executing this command. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ -} lpadc_conv_command_config_t; - -/*! - * @brief Define structure to keep the configuration for conversion trigger. - */ -typedef struct -{ - uint32_t targetCommandId; /*!< Select the command from command buffer to execute upon detect of the associated - trigger event. */ - uint32_t delayPower; /*!< Select the trigger delay duration to wait at the start of servicing a trigger event. - When this field is clear, then no delay is incurred. When this field is set to a non-zero - value, the duration for the delay is 2^delayPower ADCK cycles. The available value range - is 4-bit. */ - uint32_t priority; /*!< Sets the priority of the associated trigger source. If two or more triggers have the same - priority level setting, the lower order trigger event has the higher priority. The lower - value for this field is for the higher priority, the available value range is 1-bit. */ -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - uint8_t channelAFIFOSelect; /* SAR Result Destination For Channel A. */ - uint8_t channelBFIFOSelect; /* SAR Result Destination For Channel B. */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - bool enableHardwareTrigger; /*!< Enable hardware trigger source to initiate conversion on the rising edge of the - input trigger source or not. THe software trigger is always available. */ -} lpadc_conv_trigger_config_t; - -/*! - * @brief Define the structure to keep the conversion result. - */ -typedef struct -{ - uint32_t commandIdSource; /*!< Indicate the command buffer being executed that generated this result. */ - uint32_t loopCountIndex; /*!< Indicate the loop count value during command execution that generated this result. */ - uint32_t triggerIdSource; /*!< Indicate the trigger source that initiated a conversion and generated this result. */ - uint16_t convValue; /*!< Data result. */ -} lpadc_conv_result_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ -/*! - * @name Initialization & de-initialization. - * @{ - */ - -/*! - * @brief Initializes the LPADC module. - * - * @param base LPADC peripheral base address. - * @param config Pointer to configuration structure. See "lpadc_config_t". - */ -void LPADC_Init(ADC_Type *base, const lpadc_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for initial configuration. - * - * This function initializes the converter configuration structure with an available settings. The default values are: - * @code - * config->enableInDozeMode = true; - * config->enableAnalogPreliminary = false; - * config->powerUpDelay = 0x80; - * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - * config->powerLevelMode = kLPADC_PowerLevelAlt1; - * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; - * config->enableConvPause = false; - * config->convPauseDelay = 0U; - * config->FIFOWatermark = 0U; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConfig(lpadc_config_t *config); - -/*! - * @brief De-initializes the LPADC module. - * - * @param base LPADC peripheral base address. - */ -void LPADC_Deinit(ADC_Type *base); - -/*! - * @brief Switch on/off the LPADC module. - * - * @param base LPADC peripheral base address. - * @param enable switcher to the module. - */ -static inline void LPADC_Enable(ADC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= ADC_CTRL_ADCEN_MASK; - } - else - { - base->CTRL &= ~ADC_CTRL_ADCEN_MASK; - } -} - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Do reset the conversion FIFO0. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO0(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO0_MASK; -} - -/*! - * @brief Do reset the conversion FIFO1. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO1(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO1_MASK; -} -#else -/*! - * @brief Do reset the conversion FIFO. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO_MASK; -} -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * @brief Do reset the module's configuration. - * - * Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL). - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetConfig(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RST_MASK; - base->CTRL &= ~ADC_CTRL_RST_MASK; -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Get status flags. - * - * @param base LPADC peripheral base address. - * @return status flags' mask. See to #_lpadc_status_flags. - */ -static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base) -{ - return base->STAT; -} - -/*! - * @brief Clear status flags. - * - * Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for flags to be cleared. See to #_lpadc_status_flags. - */ -static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) -{ - base->STAT = mask; -} - -#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) -/*! - * @brief Get trigger status flags to indicate which trigger sequences have been completed or interrupted by a high - * priority trigger exception. - * - * @param base LPADC peripheral base address. - * @return The OR'ed value of @ref _lpadc_trigger_status_flags. - */ -static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base) -{ - return base->TSTAT; -} - -/*! - * @brief Clear trigger status flags. - * - * @param base LPADC peripheral base address. - * @param mask The mask of trigger status flags to be cleared, should be the - * OR'ed value of @ref _lpadc_trigger_status_flags. - */ -static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask) -{ - base->TSTAT = mask; -} -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enable interrupts. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. - */ -static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask) -{ - base->IE |= mask; -} - -/*! - * @brief Disable interrupts. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. - */ -static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask) -{ - base->IE &= ~mask; -} - -/*! - * @name DMA Control - * @{ - */ - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Switch on/off the DMA trigger for FIFO0 watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFO0WatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE0_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE0_MASK; - } -} - -/*! - * @brief Switch on/off the DMA trigger for FIFO1 watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFO1WatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE1_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE1_MASK; - } -} -#else -/*! - * @brief Switch on/off the DMA trigger for FIFO watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE_MASK; - } -} -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - /* @} */ - -/*! - * @name Trigger and conversion with FIFO. - * @{ - */ - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Get the count of result kept in conversion FIFOn. - * - * @param base LPADC peripheral base address. - * @param index Result FIFO index. - * @return The count of result kept in conversion FIFOn. - */ -static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index) -{ - return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL[index]) >> ADC_FCTRL_FCOUNT_SHIFT; -} - -/*! - * brief Get the result in conversion FIFOn. - * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. - * param index Result FIFO index. - * - * return Status whether FIFOn entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index); -#else -/*! - * @brief Get the count of result kept in conversion FIFO. - * - * @param base LPADC peripheral base address. - * @return The count of result kept in conversion FIFO. - */ -static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base) -{ - return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL) >> ADC_FCTRL_FCOUNT_SHIFT; -} - -/*! - * @brief Get the result in conversion FIFO. - * - * @param base LPADC peripheral base address. - * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. - * - * @return Status whether FIFO entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * @brief Configure the conversion trigger source. - * - * Each programmable trigger can launch the conversion command in command buffer. - * - * @param base LPADC peripheral base address. - * @param triggerId ID for each trigger. Typically, the available value range is from 0. - * @param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. - */ -void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for trigger's configuration. - * - * This function initializes the trigger's configuration structure with an available settings. The default values are: - * @code - * config->commandIdSource = 0U; - * config->loopCountIndex = 0U; - * config->triggerIdSource = 0U; - * config->enableHardwareTrigger = false; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config); - -/*! - * @brief Do software trigger to conversion command. - * - * @param base LPADC peripheral base address. - * @param triggerIdMask Mask value for software trigger indexes, which count from zero. - */ -static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask) -{ - /* Writes to ADCx_SWTRIG register are ignored while ADCx_CTRL[ADCEN] is clear. */ - base->SWTRIG = triggerIdMask; -} - -/*! - * @brief Configure conversion command. - * - * @param base LPADC peripheral base address. - * @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. - * @param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. - */ -void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for conversion command's configuration. - * - * This function initializes the conversion command's configuration structure with an available settings. The default - * values are: - * @code - * config->sampleScaleMode = kLPADC_SampleFullScale; - * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; - * config->channelNumber = 0U; - * config->chainedNextCmdNumber = 0U; - * config->enableAutoChannelIncrement = false; - * config->loopCount = 0U; - * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - * config->sampleTimeMode = kLPADC_SampleTimeADCK3; - * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - * config->hardwareCompareValueHigh = 0U; - * config->hardwareCompareValueLow = 0U; - * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; - * config->enableWaitTrigger = false; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config); - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS -/*! - * @brief Enable the calibration function. - * - * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes - * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value - * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- - * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the - * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. - * - * @param base LPADC peripheral base address. - * @param enable switcher to the calibration function. - */ -void LPADC_EnableCalibration(ADC_Type *base, bool enable); -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! - * @brief Set proper offset value to trim ADC. - * - * To minimize the offset during normal operation, software should read the conversion result from - * the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register. - * - * @param base LPADC peripheral base address. - * @param value Setting offset value. - */ -static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value) -{ - base->OFSTRIM = (value & ADC_OFSTRIM_OFSTRIM_MASK) >> ADC_OFSTRIM_OFSTRIM_SHIFT; -} - -/*! - * @brief Do auto calibration. - * - * Calibration function should be executed before using converter in application. It used the software trigger and a - * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API - * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) - * -LPADC_SetConvTriggerConfig(...) - * - * @param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base); -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! - * @brief Set proper offset value to trim ADC. - * - * Set the offset trim value for offset calibration manually. - * - * @param base LPADC peripheral base address. - * @param valueA Setting offset value A. - * @param valueB Setting offset value B. - * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. - */ -static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t valueA, uint32_t valueB) -{ - base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB); -} -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ - -/*! - * @brief Enable the offset calibration function. - * - * @param base LPADC peripheral base address. - * @param enable switcher to the calibration function. - */ -static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= ADC_CTRL_CALOFS_MASK; - } - else - { - base->CTRL &= ~ADC_CTRL_CALOFS_MASK; - } -} - -/*! - * @brief Do offset calibration. - * - * @param base LPADC peripheral base address. - */ -void LPADC_DoOffsetCalibration(ADC_Type *base); - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ -/*! - * brief Do auto calibration. - * - * param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base); -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ - -/* @} */ - -#if defined(__cplusplus) -} -#endif -/*! - * @} - */ -#endif /* _FSL_LPADC_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mcan.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mcan.c deleted file mode 100644 index 703417ab886..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mcan.c +++ /dev/null @@ -1,1700 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_mcan.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.mcan" -#endif - -/* According to CiA doc 1301 v1.0.0, specified data/nominal phase sample point postion for CAN FD at 80 MHz. */ -#define IDEAL_DATA_SP_1 (800U) -#define IDEAL_DATA_SP_2 (750U) -#define IDEAL_DATA_SP_3 (700U) -#define IDEAL_DATA_SP_4 (625U) -#define IDEAL_NOMINAL_SP (800U) - -/* According to CiA doc 301 v4.2.0 and previous version, specified sample point postion for classic CAN. */ -#define IDEAL_SP_LOW (750U) -#define IDEAL_SP_MID (800U) -#define IDEAL_SP_HIGH (875U) -#define IDEAL_SP_FACTOR (1000U) - -#define MAX_DSJW (CAN_DBTP_DSJW_MASK >> CAN_DBTP_DSJW_SHIFT) -#define MAX_DTSEG2 (CAN_DBTP_DTSEG2_MASK >> CAN_DBTP_DTSEG2_SHIFT) -#define MAX_DTSEG1 (CAN_DBTP_DTSEG1_MASK >> CAN_DBTP_DTSEG1_SHIFT) -#define MAX_DBRP (CAN_DBTP_DBRP_MASK >> CAN_DBTP_DBRP_SHIFT) - -#define MAX_NSJW (CAN_NBTP_NSJW_MASK >> CAN_NBTP_NSJW_SHIFT) -#define MAX_NTSEG2 (CAN_NBTP_NTSEG2_MASK >> CAN_NBTP_NTSEG2_SHIFT) -#define MAX_NTSEG1 (CAN_NBTP_NTSEG1_MASK >> CAN_NBTP_NTSEG1_SHIFT) -#define MAX_NBRP (CAN_NBTP_NBRP_MASK >> CAN_NBTP_NBRP_SHIFT) - -#define DBTP_MAX_TIME_QUANTA (1U + MAX_DTSEG2 + 1U + MAX_DTSEG1 + 1U) -#define DBTP_MIN_TIME_QUANTA (3U) -#define NBTP_MAX_TIME_QUANTA (1U + MAX_NTSEG2 + 1U + MAX_NTSEG1 + 1U) -#define NBTP_MIN_TIME_QUANTA (3U) - -#define MAX_TDCOFF (CAN_TDCR_TDCO_MASK >> CAN_TDCR_TDCO_SHIFT) - -#define MAX_CANFD_BAUDRATE (8000000U) -#define MAX_CAN_BAUDRATE (1000000U) - -/*! @brief MCAN Internal State. */ -enum _mcan_state -{ - kMCAN_StateIdle = 0x0, /*!< MB/RxFIFO idle.*/ - kMCAN_StateRxData = 0x1, /*!< MB receiving.*/ - kMCAN_StateRxRemote = 0x2, /*!< MB receiving remote reply.*/ - kMCAN_StateTxData = 0x3, /*!< MB transmitting.*/ - kMCAN_StateTxRemote = 0x4, /*!< MB transmitting remote request.*/ - kMCAN_StateRxFifo = 0x5, /*!< RxFIFO receiving.*/ -}; - -/* Typedef for interrupt handler. */ -typedef void (*mcan_isr_t)(CAN_Type *base, mcan_handle_t *handle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get the MCAN instance from peripheral base address. - * - * @param base MCAN peripheral base address. - * @return MCAN instance. - */ -static uint32_t MCAN_GetInstance(CAN_Type *base); - -/*! - * @brief Reset the MCAN instance. - * - * @param base MCAN peripheral base address. - */ -static void MCAN_Reset(CAN_Type *base); - -/*! - * @brief Calculates the segment values for a single bit time for classical CAN - * - * @param baudRate The data speed in bps - * @param tqNum Number of time quantas per bit, range in 4~385 - * @param pconfig Pointer to the MCAN timing configuration structure. - */ -static void MCAN_GetSegments(uint32_t baudRate, uint32_t tqNum, mcan_timing_config_t *pconfig); - -/*! - * @brief Set Baud Rate of MCAN. - * - * This function set the baud rate of MCAN. - * - * @param base MCAN peripheral base address. - * @param sourceClock_Hz Source Clock in Hz. - * @param baudRate_Bps Baud Rate in Bps. - * @param timingConfig MCAN timingConfig. - */ -static void MCAN_SetBaudRate(CAN_Type *base, - uint32_t sourceClock_Hz, - uint32_t baudRateA_Bps, - mcan_timing_config_t timingConfig); - -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) -/*! - * @brief Calculates the segment values for a single bit time for CANFD bus data baud Rate - * - * @param baudRate The canfd bus data speed in bps - * @param tqNum Number of time quanta per bit, range in 3 ~ 33 - * @param pconfig Pointer to the MCAN timing configuration structure. - */ -static void MCAN_FDGetSegments(uint32_t baudRateFD, uint32_t tqNum, mcan_timing_config_t *pconfig); - -/*! - * @brief Set Baud Rate of MCAN FD. - * - * This function set the baud rate of MCAN FD. - * - * @param base MCAN peripheral base address. - * @param sourceClock_Hz Source Clock in Hz. - * @param baudRateD_Bps Baud Rate in Bps. - * @param timingConfig MCAN timingConfig. - */ -static void MCAN_SetBaudRateFD(CAN_Type *base, - uint32_t sourceClock_Hz, - uint32_t baudRateD_Bps, - mcan_timing_config_t timingConfig); - -#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */ - -/*! - * @brief Get the element's address when read receive fifo 0. - * - * @param base MCAN peripheral base address. - * @return Address of the element in receive fifo 0. - */ -static uint32_t MCAN_GetRxFifo0ElementAddress(CAN_Type *base); - -/*! - * @brief Get the element's address when read receive fifo 1. - * - * @param base MCAN peripheral base address. - * @return Address of the element in receive fifo 1. - */ -static uint32_t MCAN_GetRxFifo1ElementAddress(CAN_Type *base); - -/*! - * @brief Get the element's address when read receive buffer. - * - * @param base MCAN peripheral base address. - * @param idx Number of the erceive buffer element. - * @return Address of the element in receive buffer. - */ -static uint32_t MCAN_GetRxBufferElementAddress(CAN_Type *base, uint8_t idx); - -/*! - * @brief Get the element's address when read transmit buffer. - * - * @param base MCAN peripheral base address. - * @param idx Number of the transmit buffer element. - * @return Address of the element in transmit buffer. - */ -static uint32_t MCAN_GetTxBufferElementAddress(CAN_Type *base, uint8_t idx); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of MCAN handle. */ -static mcan_handle_t *s_mcanHandle[FSL_FEATURE_SOC_LPC_CAN_COUNT]; - -/* Array of MCAN peripheral base address. */ -static CAN_Type *const s_mcanBases[] = CAN_BASE_PTRS; - -/* Array of MCAN IRQ number. */ -static const IRQn_Type s_mcanIRQ[][2] = CAN_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of MCAN clock name. */ -static const clock_ip_name_t s_mcanClock[] = MCAN_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_MCAN_HAS_NO_RESET) && FSL_FEATURE_MCAN_HAS_NO_RESET) -/*! @brief Pointers to MCAN resets for each instance. */ -static const reset_ip_name_t s_mcanResets[] = MCAN_RSTS; -#endif - -/* MCAN ISR for transactional APIs. */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -static mcan_isr_t s_mcanIsr = (mcan_isr_t)DefaultISR; -#else -static mcan_isr_t s_mcanIsr; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t MCAN_GetInstance(CAN_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_mcanBases); instance++) - { - if (s_mcanBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_mcanBases)); - - return instance; -} - -static void MCAN_Reset(CAN_Type *base) -{ - /* Set INIT bit. */ - base->CCCR |= CAN_CCCR_INIT_MASK; - /* Confirm the value has been accepted. */ - while (0U == (base->CCCR & CAN_CCCR_INIT_MASK)) - { - } - - /* Set CCE bit to have access to the protected configuration registers, - and clear some status registers. */ - base->CCCR |= CAN_CCCR_CCE_MASK; -} - -static void MCAN_SetBaudRate(CAN_Type *base, - uint32_t sourceClock_Hz, - uint32_t baudRateA_Bps, - mcan_timing_config_t timingConfig) -{ - /* MCAN timing setting formula: - * quantum = 1 + (NTSEG1 + 1) + (NTSEG2 + 1); - */ - uint32_t quantum = (1U + ((uint32_t)timingConfig.seg1 + 1U) + ((uint32_t)timingConfig.seg2 + 1U)); - uint32_t preDivA = baudRateA_Bps * quantum; - - /* Assertion: Source clock should greater than baud rate * quantum. */ - assert(preDivA <= sourceClock_Hz); - - if (0U == preDivA) - { - preDivA = 1U; - } - - preDivA = (sourceClock_Hz / preDivA) - 1U; - - /* Desired baud rate is too low. */ - if (preDivA > 0x1FFU) - { - preDivA = 0x1FFU; - } - - timingConfig.preDivider = (uint16_t)preDivA; - - /* Update actual timing characteristic. */ - MCAN_SetArbitrationTimingConfig(base, &timingConfig); -} - -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) -static void MCAN_SetBaudRateFD(CAN_Type *base, - uint32_t sourceClock_Hz, - uint32_t baudRateD_Bps, - mcan_timing_config_t timingConfig) -{ - /* MCAN timing setting formula: - * quantum = 1 + (NTSEG1 + 1) + (NTSEG2 + 1); - */ - uint32_t quantum = (1U + ((uint32_t)timingConfig.dataseg1 + 1U) + ((uint32_t)timingConfig.dataseg2 + 1U)); - uint32_t preDivD = baudRateD_Bps * quantum; - - /* Assertion: Source clock should greater than baud rate * quantum. */ - assert(preDivD <= sourceClock_Hz); - - if (0U == preDivD) - { - preDivD = 1U; - } - - preDivD = (sourceClock_Hz / preDivD) - 1U; - - /* Desired baud rate is too low. */ - if (preDivD > 0x1FU) - { - preDivD = 0x1FU; - } - - timingConfig.datapreDivider = (uint16_t)preDivD; - - /* Update actual timing characteristic. */ - MCAN_SetDataTimingConfig(base, &timingConfig); -} -#endif - -/*! - * brief Initializes an MCAN instance. - * - * This function initializes the MCAN module with user-defined settings. - * This example shows how to set up the mcan_config_t parameters and how - * to call the MCAN_Init function by passing in these parameters. - * code - * mcan_config_t config; - * config->baudRateA = 500000U; - * config->baudRateD = 1000000U; - * config->enableCanfdNormal = false; - * config->enableCanfdSwitch = false; - * config->enableLoopBackInt = false; - * config->enableLoopBackExt = false; - * config->enableBusMon = false; - * MCAN_Init(CANFD0, &config, 8000000UL); - * endcode - * - * param base MCAN peripheral base address. - * param config Pointer to the user-defined configuration structure. - * param sourceClock_Hz MCAN Protocol Engine clock source frequency in Hz. - */ -void MCAN_Init(CAN_Type *base, const mcan_config_t *config, uint32_t sourceClock_Hz) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable MCAN clock. */ - CLOCK_EnableClock(s_mcanClock[MCAN_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_MCAN_HAS_NO_RESET) && FSL_FEATURE_MCAN_HAS_NO_RESET) - /* Reset the MCAN module */ - RESET_PeripheralReset(s_mcanResets[MCAN_GetInstance(base)]); -#endif - - MCAN_Reset(base); - - if (config->enableLoopBackInt) - { - base->CCCR |= CAN_CCCR_TEST_MASK | CAN_CCCR_MON_MASK; - base->TEST |= CAN_TEST_LBCK_MASK; - } - if (config->enableLoopBackExt) - { - base->CCCR |= CAN_CCCR_TEST_MASK; - base->TEST |= CAN_TEST_LBCK_MASK; - } - if (config->enableBusMon) - { - base->CCCR |= CAN_CCCR_MON_MASK; - } - /* Set baud rate of arbitration phase. */ - MCAN_SetBaudRate(base, sourceClock_Hz, config->baudRateA, config->timingConfig); - -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) - if (config->enableCanfdNormal) - { - base->CCCR |= CAN_CCCR_FDOE_MASK; - } - if (config->enableCanfdSwitch) - { - /* Enable the CAN FD mode and Bit Rate Switch feature. */ - base->CCCR |= CAN_CCCR_FDOE_MASK | CAN_CCCR_BRSE_MASK; - /* Set baud rate of date phase when enable the CAN FD mode and Bit Rate Switch feature. */ - MCAN_SetBaudRateFD(base, sourceClock_Hz, config->baudRateD, config->timingConfig); - if (!config->enableLoopBackInt && !config->enableLoopBackExt) - { - /* Enable the Transceiver Delay Compensation. */ - base->DBTP |= CAN_DBTP_TDC_MASK; - /* Cleaning previous TDCO Setting. */ - base->TDCR &= ~CAN_TDCR_TDCO_MASK; - /* The TDC offset should be configured as shown in this equation : offset = (DTSEG1 + 2) * (DBRP + 1) */ - if (((uint32_t)config->timingConfig.dataseg1 + 2U) * (config->timingConfig.datapreDivider + 1U) < - MAX_TDCOFF) - { - base->TDCR |= CAN_TDCR_TDCO(((uint32_t)config->timingConfig.dataseg1 + 2U) * - (config->timingConfig.datapreDivider + 1U)); - } - else - { - /* Set the Transceiver Delay Compensation offset to max value. */ - base->TDCR |= CAN_TDCR_TDCO(MAX_TDCOFF); - } - } - } -#endif -} - -/*! - * brief Deinitializes an MCAN instance. - * - * This function deinitializes the MCAN module. - * - * param base MCAN peripheral base address. - */ -void MCAN_Deinit(CAN_Type *base) -{ - /* Reset all Register Contents. */ - MCAN_Reset(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable MCAN clock. */ - CLOCK_DisableClock(s_mcanClock[MCAN_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief MCAN enters normal mode. - * - * After initialization, INIT bit in CCCR register must be cleared to enter - * normal mode thus synchronizes to the CAN bus and ready for communication. - * - * param base MCAN peripheral base address. - */ -void MCAN_EnterNormalMode(CAN_Type *base) -{ - /* Reset INIT bit to enter normal mode. */ - base->CCCR &= ~CAN_CCCR_INIT_MASK; - while (0U != (base->CCCR & CAN_CCCR_INIT_MASK)) - { - } -} - -/*! - * brief Gets the default configuration structure. - * - * This function initializes the MCAN configuration structure to default values. The default - * values are as follows. - * config->baudRateA = 500000U; - * config->baudRateD = 1000000U; - * config->enableCanfdNormal = false; - * config->enableCanfdSwitch = false; - * config->enableLoopBackInt = false; - * config->enableLoopBackExt = false; - * config->enableBusMon = false; - * - * param config Pointer to the MCAN configuration structure. - */ -void MCAN_GetDefaultConfig(mcan_config_t *config) -{ - /* Assertion. */ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* Initialize MCAN Module config struct with default value. */ - config->baudRateA = 500000U; - config->baudRateD = 2000000U; - config->enableCanfdNormal = false; - config->enableCanfdSwitch = false; - config->enableLoopBackInt = false; - config->enableLoopBackExt = false; - config->enableBusMon = false; - /* Default protocol timing configuration, time quantum is 16. */ - config->timingConfig.seg1 = 0xAU; - config->timingConfig.seg2 = 0x3U; - config->timingConfig.rJumpwidth = 0x3U; -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) - config->timingConfig.dataseg1 = 0xAU; - config->timingConfig.dataseg2 = 0x3U; - config->timingConfig.datarJumpwidth = 0x3U; -#endif -} - -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) -/*! - * @brief Calculates the segment values for a single bit time for CANFD bus data baud Rate - * - * @param baudRate The canfd bus data speed in bps - * @param tqNum Number of time quanta per bit, range in 3 ~ 33 - * @param pconfig Pointer to the MCAN timing configuration structure. - */ -static void MCAN_FDGetSegments(uint32_t baudRateFD, uint32_t tqNum, mcan_timing_config_t *pconfig) -{ - uint32_t ideal_sp, seg1Temp; - - /* get ideal sample point. */ - if (baudRateFD <= 1000000U) - { - ideal_sp = IDEAL_DATA_SP_1; - } - else if (baudRateFD <= 2000000U) - { - ideal_sp = IDEAL_DATA_SP_2; - } - else if (baudRateFD <= 4000000U) - { - ideal_sp = IDEAL_DATA_SP_3; - } - else - { - ideal_sp = IDEAL_DATA_SP_4; - } - /* distribute time quanta. */ - pconfig->dataseg2 = (uint8_t)(tqNum - (tqNum * ideal_sp) / (uint32_t)IDEAL_SP_FACTOR - 1U); - - if (pconfig->dataseg2 > MAX_DTSEG2) - { - pconfig->dataseg2 = MAX_DTSEG2; - } - - seg1Temp = tqNum - pconfig->dataseg2 - 3U; - - if (seg1Temp > MAX_DTSEG1) - { - pconfig->dataseg2 = (uint8_t)(tqNum - MAX_DTSEG1 - 3U); - pconfig->dataseg1 = MAX_DTSEG1; - } - else - { - pconfig->dataseg1 = (uint8_t)seg1Temp; - } - - /* sjw is the minimum value of phaseSeg1 and phaseSeg2. */ - pconfig->datarJumpwidth = (pconfig->dataseg1 > pconfig->dataseg2) ? pconfig->dataseg2 : pconfig->dataseg1; - if (pconfig->datarJumpwidth > (uint8_t)MAX_DSJW) - { - pconfig->datarJumpwidth = (uint8_t)MAX_DSJW; - } -} - -/*! - * brief Calculates the improved timing values by specific bit rate for CAN FD nominal phase. - * - * This function use to calculates the CAN FD nominal phase timing values according to the given nominal phase bit rate. - * The calculation is based on the recommendation of the CiA 1301 v1.0.0 document. - * - * param baudRate The CAN FD nominal phase speed in bps defined by user, should be less than or equal to 1Mbps. - * param sourceClock_Hz The Source clock frequency in Hz. - * param pconfig Pointer to the MCAN timing configuration structure. - * - * return TRUE if timing configuration found, FALSE if failed to find configuration. - */ -static bool MCAN_CalculateImprovedNominalTimingValues(uint32_t baudRate, - uint32_t sourceClock_Hz, - mcan_timing_config_t *pconfig) -{ - uint32_t clk; /* the clock is tqNumb x baudRate. */ - uint32_t tqNum; /* Numbers of TQ. */ - uint32_t seg1Temp; - bool fgRet = false; - uint32_t spTemp = 1000U; - mcan_timing_config_t configTemp; - - /* Auto Improved Protocal timing for NBTP. */ - for (tqNum = NBTP_MAX_TIME_QUANTA; tqNum >= NBTP_MIN_TIME_QUANTA; tqNum--) - { - clk = baudRate * tqNum; - if (clk > sourceClock_Hz) - { - continue; /* tqNum too large, clk has been exceed sourceClock_Hz. */ - } - - if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) - { - continue; /* Non-supporting: the frequency of clock source is not divisible by target baud rate, the user - should change a divisible baud rate. */ - } - - configTemp.preDivider = (uint16_t)(sourceClock_Hz / clk - 1U); - if (configTemp.preDivider > MAX_NBRP) - { - break; /* The frequency of source clock is too large or the baud rate is too small, the pre-divider could - not handle it. */ - } - /* Calculates the best timing configuration under current tqNum. */ - configTemp.seg2 = (uint8_t)(tqNum - (tqNum * IDEAL_NOMINAL_SP) / (uint32_t)IDEAL_SP_FACTOR - 1U); - - if (configTemp.seg2 > MAX_NTSEG2) - { - configTemp.seg2 = MAX_NTSEG2; - } - - seg1Temp = tqNum - configTemp.seg2 - 3U; - - if (seg1Temp > MAX_NTSEG1) - { - configTemp.seg2 = (uint8_t)(tqNum - MAX_NTSEG1 - 3U); - configTemp.seg1 = MAX_NTSEG1; - } - else - { - configTemp.seg1 = (uint8_t)seg1Temp; - } - - /* sjw is the minimum value of phaseSeg1 and phaseSeg2. */ - configTemp.rJumpwidth = (configTemp.seg1 > configTemp.seg2) ? configTemp.seg2 : configTemp.seg1; - if (configTemp.rJumpwidth > (uint8_t)MAX_NSJW) - { - configTemp.rJumpwidth = (uint8_t)MAX_NSJW; - } - /* Determine whether the calculated timing configuration can get the optimal sampling point. */ - if (((((uint32_t)configTemp.seg2 + 1U) * 1000U) / tqNum) < spTemp) - { - spTemp = (((uint32_t)configTemp.seg2 + 1U) * 1000U) / tqNum; - pconfig->preDivider = configTemp.preDivider; - pconfig->rJumpwidth = configTemp.rJumpwidth; - pconfig->seg1 = configTemp.seg1; - pconfig->seg2 = configTemp.seg2; - } - fgRet = true; - } - return fgRet; -} -/*! - * brief Calculates the improved timing values by specific baudrates for CANFD - * - * param baudRate The CANFD bus control speed in bps defined by user - * param baudRateFD The CANFD bus data speed in bps defined by user - * param sourceClock_Hz The Source clock data speed in bps. - * param pconfig Pointer to the MCAN timing configuration structure. - * - * return TRUE if timing configuration found, FALSE if failed to find configuration - */ -bool MCAN_FDCalculateImprovedTimingValues(uint32_t baudRate, - uint32_t baudRateFD, - uint32_t sourceClock_Hz, - mcan_timing_config_t *pconfig) -{ - uint32_t clk; - uint32_t tqNum; /* Numbers of TQ. */ - bool fgRet = false; - uint16_t preDividerTemp = 1U; - /* observe baud rate maximums */ - assert(baudRate <= MAX_CAN_BAUDRATE); - assert(baudRateFD <= MAX_CANFD_BAUDRATE); - /* Data phase bit rate need greater or equal to nominal phase bit rate. */ - assert(baudRate <= baudRateFD); - - if (baudRate < baudRateFD) - { - /* To minimize errors when processing FD frames, try to get the same bit rate prescaler value for nominal phase - and data phase. */ - while (MCAN_CalculateImprovedNominalTimingValues(baudRate, sourceClock_Hz / preDividerTemp, pconfig)) - { - pconfig->datapreDivider = 0U; - for (tqNum = DBTP_MAX_TIME_QUANTA; tqNum >= DBTP_MIN_TIME_QUANTA; tqNum--) - { - clk = baudRateFD * tqNum; - if (clk > sourceClock_Hz) - { - continue; /* tqNumbrs too large, clk x tqNumbrs has been exceed sourceClock_Hz. */ - } - - if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) - { - continue; /* Non-supporting: the frequency of clock source is not divisible by target bit rate. */ - } - - pconfig->datapreDivider = (uint16_t)(sourceClock_Hz / clk - 1U); - - if (pconfig->datapreDivider > MAX_DBRP) - { - break; /* The frequency of source clock is too large or the bit rate is too small, the pre-divider - could not handle it. */ - } - - if (pconfig->datapreDivider < ((pconfig->preDivider + 1U) * preDividerTemp - 1U)) - { - continue; /* try to get the same bit rate prescaler value for nominal phase and data phase. */ - } - else if (pconfig->datapreDivider == ((pconfig->preDivider + 1U) * preDividerTemp - 1U)) - { - /* Calculates the best data phase timing configuration under current tqNum. */ - MCAN_FDGetSegments(baudRateFD, tqNum, pconfig); - fgRet = true; - break; - } - else - { - break; - } - } - - if (fgRet) - { - /* Find same bit rate prescaler (BRP) configuration in both nominal and data bit timing configurations. - */ - pconfig->preDivider = (pconfig->preDivider + 1U) * preDividerTemp - 1U; - break; - } - else - { - if ((pconfig->datapreDivider <= MAX_DBRP) && (pconfig->datapreDivider != 0U)) - { - /* Can't find same data bit rate prescaler (BRP) configuration under current nominal phase bit rate - prescaler, double the nominal phase bit rate prescaler and recalculate. */ - preDividerTemp++; - } - else - { - break; - } - } - } - } - else - { - if (MCAN_CalculateImprovedTimingValues(baudRate, sourceClock_Hz, pconfig)) - { - /* No need data phase timing configuration, data phase rate equal to nominal phase rate, user don't use Brs - feature. */ - pconfig->datapreDivider = 0U; - pconfig->datarJumpwidth = 0U; - pconfig->dataseg1 = 0U; - pconfig->dataseg2 = 0U; - fgRet = true; - } - } - - return fgRet; -} - -/*! - * brief Sets the MCAN protocol data phase timing characteristic. - * - * This function gives user settings to CAN bus timing characteristic. - * The function is for an experienced user. For less experienced users, call - * the MCAN_Init() and fill the baud rate field with a desired value. - * This provides the default data phase timing characteristics. - * - * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate - * set in MCAN_Init(). - * - * param base MCAN peripheral base address. - * param config Pointer to the timing configuration structure. - */ -void MCAN_SetDataTimingConfig(CAN_Type *base, const mcan_timing_config_t *config) -{ - /* Assertion. */ - assert(NULL != config); - - /* Cleaning previous Timing Setting. */ - base->DBTP &= ~(CAN_DBTP_DSJW_MASK | CAN_DBTP_DTSEG2_MASK | CAN_DBTP_DTSEG1_MASK | CAN_DBTP_DBRP_MASK); - - /* Updating Timing Setting according to configuration structure. */ - base->DBTP |= (CAN_DBTP_DBRP(config->datapreDivider) | CAN_DBTP_DSJW(config->datarJumpwidth) | - CAN_DBTP_DTSEG1(config->dataseg1) | CAN_DBTP_DTSEG2(config->dataseg2)); -} -#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */ - -/*! - * @brief Calculates the segment values for a single bit time for classical CAN - * - * @param baudRate The data speed in bps - * @param tqNum Number of time quantas per bit, range in 4~385 - * @param pconfig Pointer to the MCAN timing configuration structure. - */ -static void MCAN_GetSegments(uint32_t baudRate, uint32_t tqNum, mcan_timing_config_t *pconfig) -{ - uint32_t ideal_sp, seg1Temp; - - /* get ideal sample point. */ - if (baudRate >= 1000000U) - { - ideal_sp = IDEAL_SP_LOW; - } - else if (baudRate >= 800000U) - { - ideal_sp = IDEAL_SP_MID; - } - else - { - ideal_sp = IDEAL_SP_HIGH; - } - - /* distribute time quanta. */ - pconfig->seg2 = (uint8_t)(tqNum - (tqNum * ideal_sp) / (uint32_t)IDEAL_SP_FACTOR - 1U); - - if (pconfig->seg2 > MAX_NTSEG2) - { - pconfig->seg2 = MAX_NTSEG2; - } - - seg1Temp = tqNum - pconfig->seg2 - 3U; - - if (seg1Temp > MAX_NTSEG1) - { - pconfig->seg2 = (uint8_t)(tqNum - MAX_NTSEG1 - 3U); - pconfig->seg1 = MAX_NTSEG1; - } - else - { - pconfig->seg1 = (uint8_t)seg1Temp; - } - - /* sjw is the minimum value of phaseSeg1 and phaseSeg2. */ - pconfig->rJumpwidth = (pconfig->seg1 > pconfig->seg2) ? pconfig->seg2 : pconfig->seg1; - if (pconfig->rJumpwidth > (uint8_t)MAX_NSJW) - { - pconfig->rJumpwidth = (uint8_t)MAX_NSJW; - } -} - -/*! - * @brief Calculates the improved timing values by specific baudrates for classical CAN - * - * @param baudRate The classical CAN speed in bps defined by user - * @param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching - * @param pconfig Pointer to the MCAN timing configuration structure. - * - * @return TRUE if timing configuration found, FALSE if failed to find configuration - */ -bool MCAN_CalculateImprovedTimingValues(uint32_t baudRate, uint32_t sourceClock_Hz, mcan_timing_config_t *pconfig) -{ - uint32_t clk; /* the clock is tqNumb x baudRate. */ - uint32_t tqNum; /* Numbers of TQ. */ - bool fgRet = false; - uint32_t spTemp = 1000U; - mcan_timing_config_t configTemp = {0}; - /* observe baud rate maximums. */ - assert(baudRate <= MAX_CAN_BAUDRATE); - - /* Auto Improved Protocal timing for NBTP. */ - for (tqNum = NBTP_MAX_TIME_QUANTA; tqNum >= NBTP_MIN_TIME_QUANTA; tqNum--) - { - clk = baudRate * tqNum; - if (clk > sourceClock_Hz) - { - continue; /* tqNum too large, clk has been exceed sourceClock_Hz. */ - } - - if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) - { - continue; /* Non-supporting: the frequency of clock source is not divisible by target baud rate, the user - should change a divisible baud rate. */ - } - - configTemp.preDivider = (uint16_t)(sourceClock_Hz / clk - 1U); - if (configTemp.preDivider > MAX_NBRP) - { - break; /* The frequency of source clock is too large or the baud rate is too small, the pre-divider could - not handle it. */ - } - /* Calculates the best timing configuration under current tqNum. */ - MCAN_GetSegments(baudRate, tqNum, &configTemp); - /* Determine whether the calculated timing configuration can get the optimal sampling point. */ - if (((((uint32_t)configTemp.seg2 + 1U) * 1000U) / tqNum) < spTemp) - { - spTemp = (((uint32_t)configTemp.seg2 + 1U) * 1000U) / tqNum; - pconfig->preDivider = configTemp.preDivider; - pconfig->rJumpwidth = configTemp.rJumpwidth; - pconfig->seg1 = configTemp.seg1; - pconfig->seg2 = configTemp.seg2; - } - fgRet = true; - } - return fgRet; -} - -/*! - * brief Sets the MCAN protocol arbitration phase timing characteristic. - * - * This function gives user settings to CAN bus timing characteristic. - * The function is for an experienced user. For less experienced users, call - * the MCAN_Init() and fill the baud rate field with a desired value. - * This provides the default arbitration phase timing characteristics. - * - * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate - * set in MCAN_Init(). - * - * param base MCAN peripheral base address. - * param config Pointer to the timing configuration structure. - */ -void MCAN_SetArbitrationTimingConfig(CAN_Type *base, const mcan_timing_config_t *config) -{ - /* Assertion. */ - assert(NULL != config); - - /* Cleaning previous Timing Setting. */ - base->NBTP &= ~(CAN_NBTP_NSJW_MASK | CAN_NBTP_NTSEG2_MASK | CAN_NBTP_NTSEG1_MASK | CAN_NBTP_NBRP_MASK); - - /* Updating Timing Setting according to configuration structure. */ - base->NBTP |= (CAN_NBTP_NBRP(config->preDivider) | CAN_NBTP_NSJW(config->rJumpwidth) | - CAN_NBTP_NTSEG1(config->seg1) | CAN_NBTP_NTSEG2(config->seg2)); -} - -/*! - * brief Set filter configuration. - * - * This function sets remote and non masking frames in global filter configuration, - * also the start address, list size in standard/extended ID filter configuration. - * - * param base MCAN peripheral base address. - * param config The MCAN filter configuration. - */ -void MCAN_SetFilterConfig(CAN_Type *base, const mcan_frame_filter_config_t *config) -{ - /* Set global configuration of remote/nonmasking frames, set filter address and list size. */ - if (config->idFormat == kMCAN_FrameIDStandard) - { - base->GFC |= CAN_GFC_RRFS(config->remFrame) | CAN_GFC_ANFS(config->nmFrame); - base->SIDFC |= CAN_SIDFC_FLSSA(config->address >> CAN_SIDFC_FLSSA_SHIFT) | CAN_SIDFC_LSS(config->listSize); - } - else - { - base->GFC |= CAN_GFC_RRFE(config->remFrame) | CAN_GFC_ANFE(config->nmFrame); - base->XIDFC |= CAN_XIDFC_FLESA(config->address >> CAN_XIDFC_FLESA_SHIFT) | CAN_XIDFC_LSE(config->listSize); - } -} - -/*! - * brief Configures an MCAN receive fifo 0 buffer. - * - * This function sets start address, element size, watermark, operation mode - * and datafield size of the recieve fifo 0. - * - * param base MCAN peripheral base address. - * param config The receive fifo 0 configuration structure. - */ -void MCAN_SetRxFifo0Config(CAN_Type *base, const mcan_rx_fifo_config_t *config) -{ - /* Set Rx FIFO 0 start address, element size, watermark, operation mode. */ - base->RXF0C |= CAN_RXF0C_F0SA(config->address >> CAN_RXF0C_F0SA_SHIFT) | CAN_RXF0C_F0S(config->elementSize) | - CAN_RXF0C_F0WM(config->watermark) | CAN_RXF0C_F0OM(config->opmode); - /* Set Rx FIFO 0 data field size */ - base->RXESC |= CAN_RXESC_F0DS(config->datafieldSize); -} - -/*! - * brief Configures an MCAN receive fifo 1 buffer. - * - * This function sets start address, element size, watermark, operation mode - * and datafield size of the recieve fifo 1. - * - * param base MCAN peripheral base address. - * param config The receive fifo 1 configuration structure. - */ -void MCAN_SetRxFifo1Config(CAN_Type *base, const mcan_rx_fifo_config_t *config) -{ - /* Set Rx FIFO 1 start address, element size, watermark, operation mode. */ - base->RXF1C |= CAN_RXF1C_F1SA(config->address >> CAN_RXF1C_F1SA_SHIFT) | CAN_RXF1C_F1S(config->elementSize) | - CAN_RXF1C_F1WM(config->watermark) | CAN_RXF1C_F1OM(config->opmode); - /* Set Rx FIFO 1 data field size */ - base->RXESC |= CAN_RXESC_F1DS(config->datafieldSize); -} - -/*! - * brief Configures an MCAN receive buffer. - * - * This function sets start address and datafield size of the recieve buffer. - * - * param base MCAN peripheral base address. - * param config The receive buffer configuration structure. - */ -void MCAN_SetRxBufferConfig(CAN_Type *base, const mcan_rx_buffer_config_t *config) -{ - /* Set Rx Buffer start address. */ - base->RXBC |= CAN_RXBC_RBSA(config->address >> CAN_RXBC_RBSA_SHIFT); - /* Set Rx Buffer data field size */ - base->RXESC |= CAN_RXESC_RBDS(config->datafieldSize); -} - -/*! - * brief Configures an MCAN transmit event fifo. - * - * This function sets start address, element size, watermark of the transmit event fifo. - * - * param base MCAN peripheral base address. - * param config The transmit event fifo configuration structure. - */ -void MCAN_SetTxEventFifoConfig(CAN_Type *base, const mcan_tx_fifo_config_t *config) -{ - /* Set TX Event FIFO start address, element size, watermark. */ - base->TXEFC |= CAN_TXEFC_EFSA(config->address >> CAN_TXEFC_EFSA_SHIFT) | CAN_TXEFC_EFS(config->elementSize) | - CAN_TXEFC_EFWM(config->watermark); -} - -/*! - * brief Configures an MCAN transmit buffer. - * - * This function sets start address, element size, fifo/queue mode and datafield - * size of the transmit buffer. - * - * param base MCAN peripheral base address. - * param config The transmit buffer configuration structure. - */ -void MCAN_SetTxBufferConfig(CAN_Type *base, const mcan_tx_buffer_config_t *config) -{ - assert((config->dedicatedSize + config->fqSize) <= 32U); - - /* Set Tx Buffer start address, size, fifo/queue mode. */ - base->TXBC |= CAN_TXBC_TBSA(config->address >> CAN_TXBC_TBSA_SHIFT) | CAN_TXBC_NDTB(config->dedicatedSize) | - CAN_TXBC_TFQS(config->fqSize) | CAN_TXBC_TFQM(config->mode); - /* Set Tx Buffer data field size */ - base->TXESC |= CAN_TXESC_TBDS(config->datafieldSize); -} - -/*! - * brief Set standard message ID filter element configuration. - * - * param base MCAN peripheral base address. - * param config The MCAN filter configuration. - * param filter The MCAN standard message ID filter element configuration. - * param idx The standard message ID filter element index. - */ -void MCAN_SetSTDFilterElement(CAN_Type *base, - const mcan_frame_filter_config_t *config, - const mcan_std_filter_element_config_t *filter, - uint8_t idx) -{ - uint32_t *elementAddress = NULL; - elementAddress = (uint32_t *)(MCAN_GetMsgRAMBase(base) + config->address + idx * 4U); - (void)memcpy((void *)elementAddress, (const void *)filter, sizeof(mcan_std_filter_element_config_t)); -} - -/*! - * brief Set extended message ID filter element configuration. - * - * param base MCAN peripheral base address. - * param config The MCAN filter configuration. - * param filter The MCAN extended message ID filter element configuration. - * param idx The extended message ID filter element index. - */ -void MCAN_SetEXTFilterElement(CAN_Type *base, - const mcan_frame_filter_config_t *config, - const mcan_ext_filter_element_config_t *filter, - uint8_t idx) -{ - uint32_t *elementAddress = NULL; - elementAddress = (uint32_t *)(MCAN_GetMsgRAMBase(base) + config->address + idx * 8U); - (void)memcpy((void *)elementAddress, (const void *)filter, sizeof(mcan_ext_filter_element_config_t)); -} - -static uint32_t MCAN_GetRxFifo0ElementAddress(CAN_Type *base) -{ - uint32_t eSize; - uint32_t eAddress; - eSize = (base->RXESC & CAN_RXESC_F0DS_MASK) >> CAN_RXESC_F0DS_SHIFT; - if (eSize < 5U) - { - eSize += 4U; - } - else - { - eSize = eSize * 4U - 10U; - } - eAddress = base->RXF0C & CAN_RXF0C_F0SA_MASK; - eAddress += ((base->RXF0S & CAN_RXF0S_F0GI_MASK) >> CAN_RXF0S_F0GI_SHIFT) * eSize * 4U; - return eAddress; -} - -static uint32_t MCAN_GetRxFifo1ElementAddress(CAN_Type *base) -{ - uint32_t eSize; - uint32_t eAddress; - eSize = (base->RXESC & CAN_RXESC_F1DS_MASK) >> CAN_RXESC_F1DS_SHIFT; - if (eSize < 5U) - { - eSize += 4U; - } - else - { - eSize = eSize * 4U - 10U; - } - eAddress = base->RXF1C & CAN_RXF1C_F1SA_MASK; - eAddress += ((base->RXF1S & CAN_RXF1S_F1GI_MASK) >> CAN_RXF1S_F1GI_SHIFT) * eSize * 4U; - return eAddress; -} - -static uint32_t MCAN_GetRxBufferElementAddress(CAN_Type *base, uint8_t idx) -{ - assert(idx <= 63U); - uint32_t eSize; - eSize = (base->RXESC & CAN_RXESC_RBDS_MASK) >> CAN_RXESC_RBDS_SHIFT; - if (eSize < 5U) - { - eSize += 4U; - } - else - { - eSize = eSize * 4U - 10U; - } - return (base->RXBC & CAN_RXBC_RBSA_MASK) + idx * eSize * 4U; -} - -static uint32_t MCAN_GetTxBufferElementAddress(CAN_Type *base, uint8_t idx) -{ - assert(idx <= 31U); - uint32_t eSize; - eSize = (base->TXESC & CAN_TXESC_TBDS_MASK) >> CAN_TXESC_TBDS_SHIFT; - if (eSize < 5U) - { - eSize += 4U; - } - else - { - eSize = eSize * 4U - 10U; - } - return (base->TXBC & CAN_TXBC_TBSA_MASK) + idx * eSize * 4U; -} - -/*! - * brief Gets the Tx buffer request pending status. - * - * This function returns Tx Message Buffer transmission request pending status. - * - * param base MCAN peripheral base address. - * param idx The MCAN Tx Buffer index. - */ -uint32_t MCAN_IsTransmitRequestPending(CAN_Type *base, uint8_t idx) -{ - return (base->TXBRP & ((uint32_t)1U << idx)) >> (uint32_t)idx; -} - -/*! - * brief Gets the Tx buffer transmission occurred status. - * - * This function returns Tx Message Buffer transmission occurred status. - * - * param base MCAN peripheral base address. - * param idx The MCAN Tx Buffer index. - */ -uint32_t MCAN_IsTransmitOccurred(CAN_Type *base, uint8_t idx) -{ - return (base->TXBTO & ((uint32_t)1U << idx)) >> (uint32_t)idx; -} - -/*! - * brief Writes an MCAN Message to the Transmit Buffer. - * - * This function writes a CAN Message to the specified Transmit Message Buffer - * and changes the Message Buffer state to start CAN Message transmit. After - * that the function returns immediately. - * - * param base MCAN peripheral base address. - * param idx The MCAN Tx Buffer index. - * param pTxFrame Pointer to CAN message frame to be sent. - */ -status_t MCAN_WriteTxBuffer(CAN_Type *base, uint8_t idx, const mcan_tx_buffer_frame_t *pTxFrame) -{ - /* Assertion. */ - assert(NULL != pTxFrame); - - status_t status; - uint8_t *elementAddress = NULL; - uint8_t *elementPayloadAddress = NULL; - - if (0U == MCAN_IsTransmitRequestPending(base, idx)) - { - elementAddress = (uint8_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetTxBufferElementAddress(base, idx)); - elementPayloadAddress = (uint8_t *)((uint32_t)elementAddress + 8U); - - /* Write 2 words configuration field. */ - (void)memcpy(elementAddress, (const uint8_t *)pTxFrame, 8U); - /* Write data field. */ - (void)memcpy(elementPayloadAddress, pTxFrame->data, pTxFrame->size); - status = kStatus_Success; - } - else - { - status = kStatus_Fail; - } - - return status; -} - -/*! - * brief Reads an MCAN Message from Rx Buffer. - * - * This function reads a CAN message from the Rx Buffer in the Message RAM. - * - * param base MCAN peripheral base address. - * param idx The MCAN Rx Buffer index. - * param pRxFrame Pointer to CAN message frame structure for reception. - * retval kStatus_Success - Read Message from Rx Buffer successfully. - */ -status_t MCAN_ReadRxBuffer(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *pRxFrame) -{ - /* Assertion. */ - assert(NULL != pRxFrame); - - mcan_rx_buffer_frame_t *elementAddress = NULL; - uint32_t u4PayloadLength = (uint32_t)(pRxFrame->size) + 8U; - - elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxBufferElementAddress(base, idx)); - (void)memcpy((void *)pRxFrame, (void *)elementAddress, u4PayloadLength); - - return kStatus_Success; -} - -/*! - * brief Reads an MCAN Message from Rx FIFO. - * - * This function reads a CAN message from the Rx FIFO in the Message RAM. - * - * param base MCAN peripheral base address. - * param fifoBlock Rx FIFO block 0 or 1. - * param pRxFrame Pointer to CAN message frame structure for reception. - * retval kStatus_Success - Read Message from Rx FIFO successfully. - */ -status_t MCAN_ReadRxFifo(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *pRxFrame) -{ - /* Assertion. */ - assert((0U == fifoBlock) || (1U == fifoBlock)); - assert(NULL != pRxFrame); - - mcan_rx_buffer_frame_t *elementAddress = NULL; - if (0U == fifoBlock) - { - elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxFifo0ElementAddress(base)); - } - else - { - elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxFifo1ElementAddress(base)); - } - (void)memcpy(pRxFrame, elementAddress, 8U); - pRxFrame->data = (uint8_t *)((uint32_t)elementAddress + 8U); - /* Acknowledge the read. */ - if (0U == fifoBlock) - { - base->RXF0A = (base->RXF0S & CAN_RXF0S_F0GI_MASK) >> CAN_RXF0S_F0GI_SHIFT; - } - else - { - base->RXF1A = (base->RXF1S & CAN_RXF1S_F1GI_MASK) >> CAN_RXF1S_F1GI_SHIFT; - } - return kStatus_Success; -} - -/*! - * brief Performs a polling send transaction on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * param base MCAN peripheral base pointer. - * param idx The MCAN buffer index. - * param pTxFrame Pointer to CAN message frame to be sent. - * retval kStatus_Success - Write Tx Message Buffer Successfully. - * retval kStatus_Fail - Tx Message Buffer is currently in use. - */ -status_t MCAN_TransferSendBlocking(CAN_Type *base, uint8_t idx, mcan_tx_buffer_frame_t *pTxFrame) -{ - status_t status; - - if (kStatus_Success == MCAN_WriteTxBuffer(base, idx, pTxFrame)) - { - MCAN_TransmitAddRequest(base, idx); - - /* Wait until message sent out. */ - while (0U == MCAN_IsTransmitOccurred(base, idx)) - { - } - status = kStatus_Success; - } - else - { - status = kStatus_Fail; - } - - return status; -} - -/*! - * brief Performs a polling receive transaction on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * param base MCAN peripheral base pointer. - * param idx The MCAN buffer index. - * param pRxFrame Pointer to CAN message frame structure for reception. - * retval kStatus_Success - Read Rx Message Buffer Successfully. - * retval kStatus_Fail - No new message. - */ -status_t MCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *pRxFrame) -{ - assert(idx <= 63U); - - status_t status = kStatus_Success; - -#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) - uint32_t u4Retry = MCAN_RETRY_TIMES; -#endif - - while (!MCAN_GetRxBufferStatusFlag(base, idx)) - { -#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) - if (0U == u4Retry--) - { - status = kStatus_Fail; - } -#endif - } -#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) - if (kStatus_Success == status) -#endif - { - MCAN_ClearRxBufferStatusFlag(base, idx); - status = MCAN_ReadRxBuffer(base, idx, pRxFrame); - } - - return status; -} - -/*! - * brief Performs a polling receive transaction from Rx FIFO on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * param base MCAN peripheral base pointer. - * param fifoBlock Rx FIFO block, 0 or 1. - * param pRxFrame Pointer to CAN message frame structure for reception. - * retval kStatus_Success - Read Message from Rx FIFO successfully. - * retval kStatus_Fail - No new message in Rx FIFO. - */ -status_t MCAN_TransferReceiveFifoBlocking(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *pRxFrame) -{ - assert((0U == fifoBlock) || (1U == fifoBlock)); - - status_t status = kStatus_Success; - uint32_t maskCanIR; -#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) - uint32_t u4Retry = MCAN_RETRY_TIMES; -#endif - - maskCanIR = (0U == fifoBlock) ? CAN_IR_RF0N_MASK : CAN_IR_RF1N_MASK; - - while (0U == MCAN_GetStatusFlag(base, maskCanIR)) - { -#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) - if (0U == u4Retry--) - { - status = kStatus_Fail; - } -#endif - } - -#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) - if (kStatus_Success == status) -#endif - { - MCAN_ClearStatusFlag(base, maskCanIR); - status = MCAN_ReadRxFifo(base, fifoBlock, pRxFrame); - } - - return status; -} - -/*! - * brief Initializes the MCAN handle. - * - * This function initializes the MCAN handle, which can be used for other MCAN - * transactional APIs. Usually, for a specified MCAN instance, - * call this API once to get the initialized handle. - * - * param base MCAN peripheral base address. - * param handle MCAN handle pointer. - * param callback The callback function. - * param userData The parameter of the callback function. - */ -void MCAN_TransferCreateHandle(CAN_Type *base, mcan_handle_t *handle, mcan_transfer_callback_t callback, void *userData) -{ - assert(NULL != handle); - - uint8_t instance; - - /* Clean MCAN transfer handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Get instance from peripheral base address. */ - instance = (uint8_t)MCAN_GetInstance(base); - - /* Save the context in global variables to support the double weak mechanism. */ - s_mcanHandle[instance] = handle; - - /* Register Callback function. */ - handle->callback = callback; - handle->userData = userData; - - s_mcanIsr = MCAN_TransferHandleIRQ; - - /* We Enable Error & Status interrupt here, because this interrupt just - * report current status of MCAN module through Callback function. - * It is insignificance without a available callback function. - */ - if (handle->callback != NULL) - { - MCAN_EnableInterrupts(base, 0U, - (uint32_t)kMCAN_BusOffInterruptEnable | (uint32_t)kMCAN_ErrorInterruptEnable | - (uint32_t)kMCAN_WarningInterruptEnable); - } - else - { - MCAN_DisableInterrupts(base, (uint32_t)kMCAN_BusOffInterruptEnable | (uint32_t)kMCAN_ErrorInterruptEnable | - (uint32_t)kMCAN_WarningInterruptEnable); - } - - /* Enable interrupts in NVIC. */ - (void)EnableIRQ((IRQn_Type)(s_mcanIRQ[instance][0])); - (void)EnableIRQ((IRQn_Type)(s_mcanIRQ[instance][1])); -} - -/*! - * brief Sends a message using IRQ. - * - * This function sends a message using IRQ. This is a non-blocking function, which returns - * right away. When messages have been sent out, the send callback function is called. - * - * param base MCAN peripheral base address. - * param handle MCAN handle pointer. - * param xfer MCAN Buffer transfer structure. See the #mcan_buffer_transfer_t. - * retval kStatus_Success Start Tx Buffer sending process successfully. - * retval kStatus_Fail Write Tx Buffer failed. - * retval kStatus_MCAN_TxBusy Tx Buffer is in use. - */ -status_t MCAN_TransferSendNonBlocking(CAN_Type *base, mcan_handle_t *handle, mcan_buffer_transfer_t *xfer) -{ - /* Assertion. */ - assert(NULL != handle); - assert(NULL != xfer); - assert(xfer->bufferIdx <= 63U); - - status_t status; - - /* Check if Tx Buffer is idle. */ - if ((uint8_t)kMCAN_StateIdle == handle->bufferState[xfer->bufferIdx]) - { - handle->txbufferIdx = xfer->bufferIdx; - /* Distinguish transmit type. */ - if ((uint8_t)kMCAN_FrameTypeRemote == xfer->frame->xtd) - { - handle->bufferState[xfer->bufferIdx] = (uint8_t)kMCAN_StateTxRemote; - - /* Register user Frame buffer to receive remote Frame. */ - handle->bufferFrameBuf[xfer->bufferIdx] = xfer->frame; - } - else - { - handle->bufferState[xfer->bufferIdx] = (uint8_t)kMCAN_StateTxData; - } - - if (kStatus_Success == MCAN_WriteTxBuffer(base, xfer->bufferIdx, xfer->frame)) - { - /* Enable Buffer Interrupt. */ - MCAN_EnableTransmitBufferInterrupts(base, xfer->bufferIdx); - MCAN_EnableInterrupts(base, 0U, CAN_IE_TCE_MASK); - - MCAN_TransmitAddRequest(base, xfer->bufferIdx); - - status = kStatus_Success; - } - else - { - handle->bufferState[xfer->bufferIdx] = (uint8_t)kMCAN_StateIdle; - status = kStatus_Fail; - } - } - else - { - status = kStatus_MCAN_TxBusy; - } - - return status; -} - -/*! - * brief Receives a message from Rx FIFO using IRQ. - * - * This function receives a message using IRQ. This is a non-blocking function, which returns - * right away. When all messages have been received, the receive callback function is called. - * - * param base MCAN peripheral base address. - * param handle MCAN handle pointer. - * param fifoBlock Rx FIFO block, 0 or 1. - * param xfer MCAN Rx FIFO transfer structure. See the ref mcan_fifo_transfer_t. - * retval kStatus_Success - Start Rx FIFO receiving process successfully. - * retval kStatus_MCAN_RxFifo0Busy - Rx FIFO 0 is currently in use. - * retval kStatus_MCAN_RxFifo1Busy - Rx FIFO 1 is currently in use. - */ -status_t MCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, - uint8_t fifoBlock, - mcan_handle_t *handle, - mcan_fifo_transfer_t *xfer) -{ - /* Assertion. */ - assert((0U == fifoBlock) || (1U == fifoBlock)); - assert(NULL != handle); - assert(NULL != xfer); - - status_t status; - - /* Check if Message Buffer is idle. */ - if ((uint8_t)kMCAN_StateIdle == handle->rxFifoState) - { - handle->rxFifoState = (uint8_t)kMCAN_StateRxFifo; - - /* Register Message Buffer. */ - handle->rxFifoFrameBuf = xfer->frame; - - /* Enable FIFO Interrupt. */ - if (1U == fifoBlock) - { - MCAN_EnableInterrupts(base, 0U, CAN_IE_RF1NE_MASK); - } - else - { - MCAN_EnableInterrupts(base, 0U, CAN_IE_RF0NE_MASK); - } - status = kStatus_Success; - } - else - { - status = (1U == fifoBlock) ? kStatus_MCAN_RxFifo1Busy : kStatus_MCAN_RxFifo0Busy; - } - - return status; -} - -/*! - * brief Aborts the interrupt driven message send process. - * - * This function aborts the interrupt driven message send process. - * - * param base MCAN peripheral base address. - * param handle MCAN handle pointer. - * param bufferIdx The MCAN Buffer index. - */ -void MCAN_TransferAbortSend(CAN_Type *base, mcan_handle_t *handle, uint8_t bufferIdx) -{ - /* Assertion. */ - assert(NULL != handle); - assert(bufferIdx <= 63U); - - /* Disable Buffer Interrupt. */ - MCAN_DisableTransmitBufferInterrupts(base, bufferIdx); - MCAN_DisableInterrupts(base, CAN_IE_TCE_MASK); - - /* Cancel send request. */ - MCAN_TransmitCancelRequest(base, bufferIdx); - - /* Un-register handle. */ - handle->bufferFrameBuf[bufferIdx] = NULL; - - handle->bufferState[bufferIdx] = (uint8_t)kMCAN_StateIdle; -} - -/*! - * brief Aborts the interrupt driven message receive from Rx FIFO process. - * - * This function aborts the interrupt driven message receive from Rx FIFO process. - * - * param base MCAN peripheral base address. - * param fifoBlock MCAN Fifo block, 0 or 1. - * param handle MCAN handle pointer. - */ -void MCAN_TransferAbortReceiveFifo(CAN_Type *base, uint8_t fifoBlock, mcan_handle_t *handle) -{ - /* Assertion. */ - assert(NULL != handle); - assert((0U == fifoBlock) || (1U == fifoBlock)); - - /* Check if Rx FIFO is enabled. */ - if (1U == fifoBlock) - { - /* Disable Rx Message FIFO Interrupts. */ - MCAN_DisableInterrupts(base, CAN_IE_RF1NE_MASK); - } - else - { - MCAN_DisableInterrupts(base, CAN_IE_RF0NE_MASK); - } - /* Un-register handle. */ - handle->rxFifoFrameBuf = NULL; - - handle->rxFifoState = (uint8_t)kMCAN_StateIdle; -} - -/*! - * brief MCAN IRQ handle function. - * - * This function handles the MCAN Error, the Buffer, and the Rx FIFO IRQ request. - * - * param base MCAN peripheral base address. - * param handle MCAN handle pointer. - */ -void MCAN_TransferHandleIRQ(CAN_Type *base, mcan_handle_t *handle) -{ - /* Assertion. */ - assert(NULL != handle); - - status_t status = kStatus_MCAN_UnHandled; - uint32_t valueIR; - uint32_t result; - - /* Store Current MCAN Module Error and Status. */ - valueIR = base->IR; - - do - { - if (0U != (valueIR & ((uint32_t)kMCAN_ErrorWarningIntFlag | (uint32_t)kMCAN_ErrorPassiveIntFlag | - (uint32_t)kMCAN_BusOffIntFlag))) - { - /* Solve error. */ - result = (uint32_t)kMCAN_ErrorWarningIntFlag | (uint32_t)kMCAN_ErrorPassiveIntFlag | - (uint32_t)kMCAN_BusOffIntFlag; - status = kStatus_MCAN_ErrorStatus; - } - else if (0U != (valueIR & (uint32_t)kMCAN_TxTransmitCompleteFlag)) - { - /* Solve Tx interrupt. */ - result = (uint32_t)kMCAN_TxTransmitCompleteFlag; - status = kStatus_MCAN_TxIdle; - MCAN_TransferAbortSend(base, handle, handle->txbufferIdx); - } - else if (0U != (valueIR & (uint32_t)kMCAN_RxFifo0NewFlag)) - { - (void)MCAN_ReadRxFifo(base, 0U, handle->rxFifoFrameBuf); - result = (uint32_t)kMCAN_RxFifo0NewFlag; - status = kStatus_MCAN_RxFifo0Idle; - MCAN_TransferAbortReceiveFifo(base, 0U, handle); - } - else if (0U != (valueIR & (uint32_t)kMCAN_RxFifo0LostFlag)) - { - result = (uint32_t)kMCAN_RxFifo0LostFlag; - status = kStatus_MCAN_RxFifo0Lost; - } - else if (0U != (valueIR & (uint32_t)kMCAN_RxFifo1NewFlag)) - { - (void)MCAN_ReadRxFifo(base, 1U, handle->rxFifoFrameBuf); - result = (uint32_t)kMCAN_RxFifo1NewFlag; - status = kStatus_MCAN_RxFifo1Idle; - MCAN_TransferAbortReceiveFifo(base, 1U, handle); - } - else if (0U != (valueIR & (uint32_t)kMCAN_RxFifo1LostFlag)) - { - result = (uint32_t)kMCAN_RxFifo1LostFlag; - status = kStatus_MCAN_RxFifo0Lost; - } - else - { - /* Handle the interrupt flag unsupported in current version of MCAN driver. - * User can get these unsupported interrupt flags by callback function, - * we can clear directly in the handler to prevent endless loop. - */ - result = valueIR; - result &= ~((uint32_t)kMCAN_ErrorWarningIntFlag | (uint32_t)kMCAN_ErrorPassiveIntFlag | - (uint32_t)kMCAN_BusOffIntFlag | (uint32_t)kMCAN_TxTransmitCompleteFlag | - (uint32_t)kMCAN_RxFifo0NewFlag | (uint32_t)kMCAN_RxFifo0LostFlag | - (uint32_t)kMCAN_RxFifo1NewFlag | (uint32_t)kMCAN_RxFifo1LostFlag); - } - - /* Clear Error interrupt, resolved Rx FIFO, Tx Buffer IRQ and other unsupported interrupt flags. */ - MCAN_ClearStatusFlag(base, result); - - /* Calling Callback Function if has one. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, status, result, handle->userData); - } - - /* Reset return status */ - status = kStatus_MCAN_UnHandled; - - /* Store Current MCAN Module Error and Status. */ - valueIR = base->IR; - } while (0U != valueIR); -} - -#if defined(CAN0) -void CAN0_IRQ0_DriverIRQHandler(void); -void CAN0_IRQ0_DriverIRQHandler(void) -{ - assert(NULL != s_mcanHandle[0]); - - s_mcanIsr(CAN0, s_mcanHandle[0]); - SDK_ISR_EXIT_BARRIER; -} - -void CAN0_IRQ1_DriverIRQHandler(void); -void CAN0_IRQ1_DriverIRQHandler(void) -{ - assert(NULL != s_mcanHandle[0]); - - s_mcanIsr(CAN0, s_mcanHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CAN1) -void CAN1_IRQ0_DriverIRQHandler(void); -void CAN1_IRQ0_DriverIRQHandler(void) -{ - assert(NULL != s_mcanHandle[1]); - - s_mcanIsr(CAN1, s_mcanHandle[1]); - SDK_ISR_EXIT_BARRIER; -} - -void CAN1_IRQ1_DriverIRQHandler(void); -void CAN1_IRQ1_DriverIRQHandler(void) -{ - assert(NULL != s_mcanHandle[1]); - - s_mcanIsr(CAN1, s_mcanHandle[1]); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mcan.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mcan.h deleted file mode 100644 index 88080fb907d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mcan.h +++ /dev/null @@ -1,1032 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_MCAN_H_ -#define _FSL_MCAN_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup mcan - * @{ - */ - -/****************************************************************************** - * Definitions - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief MCAN driver version. */ -#define FSL_MCAN_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) -/*@}*/ - -#ifndef MCAN_RETRY_TIMES -/* Define to 0 by default means to retry infinitely until the flag is assert/de-assert. - * User can change the macro with their requirement by defined the MACRO. - */ -#define MCAN_RETRY_TIMES (0U) -#endif - -/*! @brief MCAN transfer status. */ -enum -{ - kStatus_MCAN_TxBusy = MAKE_STATUS(kStatusGroup_MCAN, 0), /*!< Tx Buffer is Busy. */ - kStatus_MCAN_TxIdle = MAKE_STATUS(kStatusGroup_MCAN, 1), /*!< Tx Buffer is Idle. */ - kStatus_MCAN_RxBusy = MAKE_STATUS(kStatusGroup_MCAN, 2), /*!< Rx Buffer is Busy. */ - kStatus_MCAN_RxIdle = MAKE_STATUS(kStatusGroup_MCAN, 3), /*!< Rx Buffer is Idle. */ - kStatus_MCAN_RxFifo0New = MAKE_STATUS(kStatusGroup_MCAN, 4), /*!< New message written to Rx FIFO 0. */ - kStatus_MCAN_RxFifo0Idle = MAKE_STATUS(kStatusGroup_MCAN, 5), /*!< Rx FIFO 0 is Idle. */ - kStatus_MCAN_RxFifo0Watermark = MAKE_STATUS(kStatusGroup_MCAN, 6), /*!< Rx FIFO 0 fill level reached watermark. */ - kStatus_MCAN_RxFifo0Full = MAKE_STATUS(kStatusGroup_MCAN, 7), /*!< Rx FIFO 0 full. */ - kStatus_MCAN_RxFifo0Lost = MAKE_STATUS(kStatusGroup_MCAN, 8), /*!< Rx FIFO 0 message lost. */ - kStatus_MCAN_RxFifo1New = MAKE_STATUS(kStatusGroup_MCAN, 9), /*!< New message written to Rx FIFO 1. */ - kStatus_MCAN_RxFifo1Idle = MAKE_STATUS(kStatusGroup_MCAN, 10), /*!< Rx FIFO 1 is Idle. */ - kStatus_MCAN_RxFifo1Watermark = MAKE_STATUS(kStatusGroup_MCAN, 11), /*!< Rx FIFO 1 fill level reached watermark. */ - kStatus_MCAN_RxFifo1Full = MAKE_STATUS(kStatusGroup_MCAN, 12), /*!< Rx FIFO 1 full. */ - kStatus_MCAN_RxFifo1Lost = MAKE_STATUS(kStatusGroup_MCAN, 13), /*!< Rx FIFO 1 message lost. */ - kStatus_MCAN_RxFifo0Busy = MAKE_STATUS(kStatusGroup_MCAN, 14), /*!< Rx FIFO 0 is busy. */ - kStatus_MCAN_RxFifo1Busy = MAKE_STATUS(kStatusGroup_MCAN, 15), /*!< Rx FIFO 1 is busy. */ - kStatus_MCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_MCAN, 16), /*!< MCAN Module Error and Status. */ - kStatus_MCAN_UnHandled = MAKE_STATUS(kStatusGroup_MCAN, 17), /*!< UnHadled Interrupt asserted. */ -}; - -/*! - * @brief MCAN status flags. - * - * This provides constants for the MCAN status flags for use in the MCAN functions. - * Note: The CPU read action clears MCAN_ErrorFlag, therefore user need to - * read MCAN_ErrorFlag and distinguish which error is occur using - * _mcan_error_flags enumerations. - */ -enum _mcan_flags -{ - kMCAN_AccesstoRsvdFlag = CAN_IR_ARA_MASK, /*!< CAN Synchronization Status. */ - kMCAN_ProtocolErrDIntFlag = CAN_IR_PED_MASK, /*!< Tx Warning Interrupt Flag. */ - kMCAN_ProtocolErrAIntFlag = CAN_IR_PEA_MASK, /*!< Rx Warning Interrupt Flag. */ - kMCAN_BusOffIntFlag = CAN_IR_BO_MASK, /*!< Tx Error Warning Status. */ - kMCAN_ErrorWarningIntFlag = CAN_IR_EW_MASK, /*!< Rx Error Warning Status. */ - kMCAN_ErrorPassiveIntFlag = CAN_IR_EP_MASK, /*!< Rx Error Warning Status. */ -}; - -/*! - * @brief MCAN Rx FIFO status flags. - * - * The MCAN Rx FIFO Status enumerations are used to determine the status of the - * Rx FIFO. - */ -enum _mcan_rx_fifo_flags -{ - kMCAN_RxFifo0NewFlag = CAN_IR_RF0N_MASK, /*!< Rx FIFO 0 new message flag. */ - kMCAN_RxFifo0WatermarkFlag = CAN_IR_RF0W_MASK, /*!< Rx FIFO 0 watermark reached flag. */ - kMCAN_RxFifo0FullFlag = CAN_IR_RF0F_MASK, /*!< Rx FIFO 0 full flag. */ - kMCAN_RxFifo0LostFlag = CAN_IR_RF0L_MASK, /*!< Rx FIFO 0 message lost flag. */ - kMCAN_RxFifo1NewFlag = CAN_IR_RF1N_MASK, /*!< Rx FIFO 0 new message flag. */ - kMCAN_RxFifo1WatermarkFlag = CAN_IR_RF1W_MASK, /*!< Rx FIFO 0 watermark reached flag. */ - kMCAN_RxFifo1FullFlag = CAN_IR_RF1F_MASK, /*!< Rx FIFO 0 full flag. */ - kMCAN_RxFifo1LostFlag = CAN_IR_RF1L_MASK, /*!< Rx FIFO 0 message lost flag. */ -}; - -/*! - * @brief MCAN Tx status flags. - * - * The MCAN Tx Status enumerations are used to determine the status of the - * Tx Buffer/Event FIFO. - */ -enum _mcan_tx_flags -{ - kMCAN_TxTransmitCompleteFlag = CAN_IR_TC_MASK, /*!< Transmission completed flag. */ - kMCAN_TxTransmitCancelFinishFlag = CAN_IR_TCF_MASK, /*!< Transmission cancellation finished flag. */ - kMCAN_TxEventFifoLostFlag = CAN_IR_TEFL_MASK, /*!< Tx Event FIFO element lost. */ - kMCAN_TxEventFifoFullFlag = CAN_IR_TEFF_MASK, /*!< Tx Event FIFO full. */ - kMCAN_TxEventFifoWatermarkFlag = CAN_IR_TEFW_MASK, /*!< Tx Event FIFO fill level reached watermark. */ - kMCAN_TxEventFifoNewFlag = CAN_IR_TEFN_MASK, /*!< Tx Handler wrote Tx Event FIFO element flag. */ - kMCAN_TxEventFifoEmptyFlag = CAN_IR_TFE_MASK, /*!< Tx FIFO empty flag. */ -}; - -/*! - * @brief MCAN interrupt configuration structure, default settings all disabled. - * - * This structure contains the settings for all of the MCAN Module interrupt configurations. - */ -enum _mcan_interrupt_enable -{ - kMCAN_BusOffInterruptEnable = CAN_IE_BOE_MASK, /*!< Bus Off interrupt. */ - kMCAN_ErrorInterruptEnable = CAN_IE_EPE_MASK, /*!< Error interrupt. */ - kMCAN_WarningInterruptEnable = CAN_IE_EWE_MASK, /*!< Rx Warning interrupt. */ -}; - -/*! @brief MCAN frame format. */ -typedef enum _mcan_frame_idformat -{ - kMCAN_FrameIDStandard = 0x0U, /*!< Standard frame format attribute. */ - kMCAN_FrameIDExtend = 0x1U, /*!< Extend frame format attribute. */ -} mcan_frame_idformat_t; - -/*! @brief MCAN frame type. */ -typedef enum _mcan_frame_type -{ - kMCAN_FrameTypeData = 0x0U, /*!< Data frame type attribute. */ - kMCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */ -} mcan_frame_type_t; - -/*! @brief MCAN frame datafield size. */ -typedef enum _mcan_bytes_in_datafield -{ - kMCAN_8ByteDatafield = 0x0U, /*!< 8 byte data field. */ - kMCAN_12ByteDatafield = 0x1U, /*!< 12 byte data field. */ - kMCAN_16ByteDatafield = 0x2U, /*!< 16 byte data field. */ - kMCAN_20ByteDatafield = 0x3U, /*!< 20 byte data field. */ - kMCAN_24ByteDatafield = 0x4U, /*!< 24 byte data field. */ - kMCAN_32ByteDatafield = 0x5U, /*!< 32 byte data field. */ - kMCAN_48ByteDatafield = 0x6U, /*!< 48 byte data field. */ - kMCAN_64ByteDatafield = 0x7U, /*!< 64 byte data field. */ -} mcan_bytes_in_datafield_t; - -#if defined(__CC_ARM) -#pragma anon_unions -#endif -/*! @brief MCAN Tx Buffer structure. */ -typedef struct _mcan_tx_buffer_frame -{ - struct - { - uint32_t id : 29; /*!< CAN Frame Identifier. */ - uint32_t rtr : 1; /*!< CAN Frame Type(DATA or REMOTE). */ - uint32_t xtd : 1; /*!< CAN Frame Type(STD or EXT). */ - uint32_t esi : 1; /*!< CAN Frame Error State Indicator. */ - }; - struct - { - uint32_t : 16; - uint32_t dlc : 4; /*!< Data Length Code 9 10 11 12 13 14 15 - Number of data bytes 12 16 20 24 32 48 64 */ - uint32_t brs : 1; /*!< Bit Rate Switch. */ - uint32_t fdf : 1; /*!< CAN FD format. */ - uint32_t : 1; /*!< Reserved. */ - uint32_t efc : 1; /*!< Event FIFO control. */ - uint32_t mm : 8; /*!< Message Marker. */ - }; - uint8_t *data; - uint8_t size; /*!< classical CAN is 8(bytes), FD is 12/64 such. */ -} mcan_tx_buffer_frame_t; - -/*! @brief MCAN Rx FIFO/Buffer structure. */ -typedef struct _mcan_rx_buffer_frame -{ - struct - { - uint32_t id : 29; /*!< CAN Frame Identifier. */ - uint32_t rtr : 1; /*!< CAN Frame Type(DATA or REMOTE). */ - uint32_t xtd : 1; /*!< CAN Frame Type(STD or EXT). */ - uint32_t esi : 1; /*!< CAN Frame Error State Indicator. */ - }; - struct - { - uint32_t rxts : 16; /*!< Rx Timestamp. */ - uint32_t dlc : 4; /*!< Data Length Code 9 10 11 12 13 14 15 - Number of data bytes 12 16 20 24 32 48 64 */ - uint32_t brs : 1; /*!< Bit Rate Switch. */ - uint32_t fdf : 1; /*!< CAN FD format. */ - uint32_t : 2; /*!< Reserved. */ - uint32_t fidx : 7; /*!< Filter Index. */ - uint32_t anmf : 1; /*!< Accepted Non-matching Frame. */ - }; - uint8_t *data; - uint8_t size; /*!< classical CAN is 8(bytes), FD is 12/64 such. */ -} mcan_rx_buffer_frame_t; - -/*! @brief MCAN Rx FIFO block number. */ -typedef enum _mcan_fifo_type -{ - kMCAN_Fifo0 = 0x0U, /*!< CAN Rx FIFO 0. */ - kMCAN_Fifo1 = 0x1U, /*!< CAN Rx FIFO 1. */ -} mcan_fifo_type_t; - -/*! @brief MCAN FIFO Operation Mode. */ -typedef enum _mcan_fifo_opmode_config -{ - kMCAN_FifoBlocking = 0x0U, /*!< FIFO blocking mode. */ - kMCAN_FifoOverwrite = 0x1U, /*!< FIFO overwrite mode. */ -} mcan_fifo_opmode_config_t; - -/*! @brief MCAN Tx FIFO/Queue Mode. */ -typedef enum _mcan_txmode_config -{ - kMCAN_txFifo = 0x0U, /*!< Tx FIFO operation. */ - kMCAN_txQueue = 0x1U, /*!< Tx Queue operation. */ -} mcan_txmode_config_t; - -/*! @brief MCAN remote frames treatment. */ -typedef enum _mcan_remote_frame_config -{ - kMCAN_filterFrame = 0x0U, /*!< Filter remote frames. */ - kMCAN_rejectFrame = 0x1U, /*!< Reject all remote frames. */ -} mcan_remote_frame_config_t; - -/*! @brief MCAN non-masking frames treatment. */ -typedef enum _mcan_nonmasking_frame_config -{ - kMCAN_acceptinFifo0 = 0x0U, /*!< Accept non-masking frames in Rx FIFO 0. */ - kMCAN_acceptinFifo1 = 0x1U, /*!< Accept non-masking frames in Rx FIFO 1. */ - kMCAN_reject0 = 0x2U, /*!< Reject non-masking frames. */ - kMCAN_reject1 = 0x3U, /*!< Reject non-masking frames. */ -} mcan_nonmasking_frame_config_t; - -/*! @brief MCAN Filter Element Configuration. */ -typedef enum _mcan_fec_config -{ - kMCAN_disable = 0x0U, /*!< Disable filter element. */ - kMCAN_storeinFifo0 = 0x1U, /*!< Store in Rx FIFO 0 if filter matches. */ - kMCAN_storeinFifo1 = 0x2U, /*!< Store in Rx FIFO 1 if filter matches. */ - kMCAN_reject = 0x3U, /*!< Reject ID if filter matches. */ - kMCAN_setprio = 0x4U, /*!< Set priority if filter matches. */ - kMCAN_setpriofifo0 = 0x5U, /*!< Set priority and store in FIFO 0 if filter matches. */ - kMCAN_setpriofifo1 = 0x6U, /*!< Set priority and store in FIFO 1 if filter matches. */ - kMCAN_storeinbuffer = 0x7U, /*!< Store into Rx Buffer or as debug message. */ -} mcan_fec_config_t; - -/*! @brief MCAN Rx FIFO configuration. */ -typedef struct _mcan_rx_fifo_config -{ - uint32_t address; /*!< FIFOn start address. */ - uint32_t elementSize; /*!< FIFOn element number. */ - uint32_t watermark; /*!< FIFOn watermark level. */ - mcan_fifo_opmode_config_t opmode; /*!< FIFOn blocking/overwrite mode. */ - mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */ -} mcan_rx_fifo_config_t; - -/*! @brief MCAN Rx Buffer configuration. */ -typedef struct _mcan_rx_buffer_config -{ - uint32_t address; /*!< Rx Buffer start address. */ - mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */ -} mcan_rx_buffer_config_t; - -/*! @brief MCAN Tx Event FIFO configuration. */ -typedef struct _mcan_tx_fifo_config -{ - uint32_t address; /*!< Event fifo start address. */ - uint32_t elementSize; /*!< FIFOn element number. */ - uint32_t watermark; /*!< FIFOn watermark level. */ -} mcan_tx_fifo_config_t; - -/*! @brief MCAN Tx Buffer configuration. */ -typedef struct _mcan_tx_buffer_config -{ - uint32_t address; /*!< Tx Buffers Start Address. */ - uint32_t dedicatedSize; /*!< Number of Dedicated Transmit Buffers. */ - uint32_t fqSize; /*!< Transmit FIFO/Queue Size. */ - mcan_txmode_config_t mode; /*!< Tx FIFO/Queue Mode.*/ - mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */ -} mcan_tx_buffer_config_t; - -/*! @brief MCAN Filter Type. */ -typedef enum _mcan_std_filter_type -{ - kMCAN_range = 0x0U, /*!< Range filter from SFID1 to SFID2. */ - kMCAN_dual = 0x1U, /*!< Dual ID filter for SFID1 or SFID2. */ - kMCAN_classic = 0x2U, /*!< Classic filter: SFID1 = filter, SFID2 = mask. */ - kMCAN_disableORrange2 = 0x3U, /*!< Filter element disabled for standard filter - or Range filter, XIDAM mask not applied for extended filter. */ -} mcan_filter_type_t; - -/*! @brief MCAN Standard Message ID Filter Element. */ -typedef struct _mcan_std_filter_element_config -{ - uint32_t sfid2 : 11; /*!< Standard Filter ID 2. */ - uint32_t : 5; /*!< Reserved. */ - uint32_t sfid1 : 11; /*!< Standard Filter ID 1. */ - uint32_t sfec : 3; /*!< Standard Filter Element Configuration. */ - uint32_t sft : 2; /*!< Standard Filter Type. */ -} mcan_std_filter_element_config_t; - -/*! @brief MCAN Extended Message ID Filter Element. */ -typedef struct _mcan_ext_filter_element_config -{ - uint32_t efid1 : 29; /*!< Extended Filter ID 1. */ - uint32_t efec : 3; /*!< Extended Filter Element Configuration. */ - uint32_t efid2 : 29; /*!< Extended Filter ID 2. */ - uint32_t : 1; /*!< Reserved. */ - uint32_t eft : 2; /*!< Extended Filter Type. */ -} mcan_ext_filter_element_config_t; - -/*! @brief MCAN Rx filter configuration. */ -typedef struct _mcan_frame_filter_config -{ - uint32_t address; /*!< Filter start address. */ - uint32_t listSize; /*!< Filter list size. */ - mcan_frame_idformat_t idFormat; /*!< Frame format. */ - mcan_remote_frame_config_t remFrame; /*!< Remote frame treatment. */ - mcan_nonmasking_frame_config_t nmFrame; /*!< Non-masking frame treatment. */ -} mcan_frame_filter_config_t; - -/*! @brief MCAN protocol timing characteristic configuration structure. */ -typedef struct _mcan_timing_config -{ - uint16_t preDivider; /*!< Nominal Clock Pre-scaler Division Factor. */ - uint8_t rJumpwidth; /*!< Nominal Re-sync Jump Width. */ - uint8_t seg1; /*!< Nominal Time Segment 1. */ - uint8_t seg2; /*!< Nominal Time Segment 2. */ -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) - uint16_t datapreDivider; /*!< Data Clock Pre-scaler Division Factor. */ - uint8_t datarJumpwidth; /*!< Data Re-sync Jump Width. */ - uint8_t dataseg1; /*!< Data Time Segment 1. */ - uint8_t dataseg2; /*!< Data Time Segment 2. */ -#endif -} mcan_timing_config_t; - -/*! @brief MCAN module configuration structure. */ -typedef struct _mcan_config -{ - uint32_t baudRateA; /*!< Baud rate of Arbitration phase in bps. */ - uint32_t baudRateD; /*!< Baud rate of Data phase in bps. */ - bool enableCanfdNormal; /*!< Enable or Disable CANFD normal. */ - bool enableCanfdSwitch; /*!< Enable or Disable CANFD with baudrate switch. */ - bool enableLoopBackInt; /*!< Enable or Disable Internal Back. */ - bool enableLoopBackExt; /*!< Enable or Disable External Loop Back. */ - bool enableBusMon; /*!< Enable or Disable Bus Monitoring Mode. */ - mcan_timing_config_t timingConfig; /*!< Protocol timing . */ -} mcan_config_t; - -/*! @brief MCAN Buffer transfer. */ -typedef struct _mcan_buffer_transfer -{ - mcan_tx_buffer_frame_t *frame; /*!< The buffer of CAN Message to be transfer. */ - uint8_t bufferIdx; /*!< The index of Message buffer used to transfer Message. */ -} mcan_buffer_transfer_t; - -/*! @brief MCAN Rx FIFO transfer. */ -typedef struct _mcan_fifo_transfer -{ - mcan_rx_buffer_frame_t *frame; /*!< The buffer of CAN Message to be received from Rx FIFO. */ -} mcan_fifo_transfer_t; - -/*! @brief MCAN handle structure definition. */ -typedef struct _mcan_handle mcan_handle_t; - -/*! @brief MCAN transfer callback function. - * - * The MCAN transfer callback returns a value from the underlying layer. - * If the status equals to kStatus_MCAN_ErrorStatus, the result parameter is the Content of - * MCAN status register which can be used to get the working status(or error status) of MCAN module. - * If the status equals to other MCAN Message Buffer transfer status, the result is the index of - * Message Buffer that generate transfer event. - * If the status equals to other MCAN Message Buffer transfer status, the result is meaningless and should be - * Ignored. - */ -typedef void (*mcan_transfer_callback_t)( - CAN_Type *base, mcan_handle_t *handle, status_t status, uint32_t result, void *userData); - -/*! @brief MCAN handle structure. */ -struct _mcan_handle -{ - mcan_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< MCAN callback function parameter.*/ - mcan_tx_buffer_frame_t *volatile bufferFrameBuf[64]; /*!< The buffer for received data from Buffers. */ - mcan_rx_buffer_frame_t *volatile rxFifoFrameBuf; /*!< The buffer for received data from Rx FIFO. */ - volatile uint8_t txbufferIdx; /*!< Message Buffer transfer state. */ - volatile uint8_t bufferState[64]; /*!< Message Buffer transfer state. */ - volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */ -}; - -/****************************************************************************** - * API - *****************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes an MCAN instance. - * - * This function initializes the MCAN module with user-defined settings. - * This example shows how to set up the mcan_config_t parameters and how - * to call the MCAN_Init function by passing in these parameters. - * @code - * mcan_config_t config; - * config->baudRateA = 500000U; - * config->baudRateD = 1000000U; - * config->enableCanfdNormal = false; - * config->enableCanfdSwitch = false; - * config->enableLoopBackInt = false; - * config->enableLoopBackExt = false; - * config->enableBusMon = false; - * MCAN_Init(CANFD0, &config, 8000000UL); - * @endcode - * - * @param base MCAN peripheral base address. - * @param config Pointer to the user-defined configuration structure. - * @param sourceClock_Hz MCAN Protocol Engine clock source frequency in Hz. - */ -void MCAN_Init(CAN_Type *base, const mcan_config_t *config, uint32_t sourceClock_Hz); - -/*! - * @brief Deinitializes an MCAN instance. - * - * This function deinitializes the MCAN module. - * - * @param base MCAN peripheral base address. - */ -void MCAN_Deinit(CAN_Type *base); - -/*! - * @brief Gets the default configuration structure. - * - * This function initializes the MCAN configuration structure to default values. The default - * values are as follows. - * config->baudRateA = 500000U; - * config->baudRateD = 1000000U; - * config->enableCanfdNormal = false; - * config->enableCanfdSwitch = false; - * config->enableLoopBackInt = false; - * config->enableLoopBackExt = false; - * config->enableBusMon = false; - * - * @param config Pointer to the MCAN configuration structure. - */ -void MCAN_GetDefaultConfig(mcan_config_t *config); - -/*! - * @brief MCAN enters normal mode. - * - * After initialization, INIT bit in CCCR register must be cleared to enter - * normal mode thus synchronizes to the CAN bus and ready for communication. - * - * @param base MCAN peripheral base address. - */ -void MCAN_EnterNormalMode(CAN_Type *base); - -/*! - * @name Configuration. - * @{ - */ - -/*! - * @brief Sets the MCAN Message RAM base address. - * - * This function sets the Message RAM base address. - * - * @param base MCAN peripheral base address. - * @param value Desired Message RAM base. - */ -static inline void MCAN_SetMsgRAMBase(CAN_Type *base, uint32_t value) -{ - assert(((value >= 0x20000000U) && (value <= 0x20027FFFU)) || ((value >= 0x04000000U) && (value <= 0x04007FFFU))); - - base->MRBA = CAN_MRBA_BA(value >> 16U); -} - -/*! - * @brief Gets the MCAN Message RAM base address. - * - * This function gets the Message RAM base address. - * - * @param base MCAN peripheral base address. - * @return Message RAM base address. - */ -static inline uint32_t MCAN_GetMsgRAMBase(CAN_Type *base) -{ - return base->MRBA; -} - -/*! - * @brief Calculates the improved timing values by specific baudrates for classical CAN - * - * @param baudRate The classical CAN speed in bps defined by user - * @param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching - * @param pconfig Pointer to the MCAN timing configuration structure. - * - * @return TRUE if timing configuration found, FALSE if failed to find configuration - */ -bool MCAN_CalculateImprovedTimingValues(uint32_t baudRate, uint32_t sourceClock_Hz, mcan_timing_config_t *pconfig); - -/*! - * @brief Sets the MCAN protocol arbitration phase timing characteristic. - * - * This function gives user settings to CAN bus timing characteristic. - * The function is for an experienced user. For less experienced users, call - * the MCAN_Init() and fill the baud rate field with a desired value. - * This provides the default arbitration phase timing characteristics. - * - * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate - * set in MCAN_Init(). - * - * @param base MCAN peripheral base address. - * @param config Pointer to the timing configuration structure. - */ -void MCAN_SetArbitrationTimingConfig(CAN_Type *base, const mcan_timing_config_t *config); - -#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) -/*! - * @brief Calculates the improved timing values by specific baudrates for CANFD - * - * @param baudRate The CANFD bus control speed in bps defined by user - * @param baudRateFD The CANFD bus data speed in bps defined by user - * @param sourceClock_Hz The Source clock data speed in bps. - * @param pconfig Pointer to the MCAN timing configuration structure. - * - * @return TRUE if timing configuration found, FALSE if failed to find configuration - */ -bool MCAN_FDCalculateImprovedTimingValues(uint32_t baudRate, - uint32_t baudRateFD, - uint32_t sourceClock_Hz, - mcan_timing_config_t *pconfig); -/*! - * @brief Sets the MCAN protocol data phase timing characteristic. - * - * This function gives user settings to CAN bus timing characteristic. - * The function is for an experienced user. For less experienced users, call - * the MCAN_Init() and fill the baud rate field with a desired value. - * This provides the default data phase timing characteristics. - * - * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate - * set in MCAN_Init(). - * - * @param base MCAN peripheral base address. - * @param config Pointer to the timing configuration structure. - */ -void MCAN_SetDataTimingConfig(CAN_Type *base, const mcan_timing_config_t *config); -#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */ - -/*! - * @brief Configures an MCAN receive fifo 0 buffer. - * - * This function sets start address, element size, watermark, operation mode - * and datafield size of the recieve fifo 0. - * - * @param base MCAN peripheral base address. - * @param config The receive fifo 0 configuration structure. - */ -void MCAN_SetRxFifo0Config(CAN_Type *base, const mcan_rx_fifo_config_t *config); - -/*! - * @brief Configures an MCAN receive fifo 1 buffer. - * - * This function sets start address, element size, watermark, operation mode - * and datafield size of the recieve fifo 1. - * - * @param base MCAN peripheral base address. - * @param config The receive fifo 1 configuration structure. - */ -void MCAN_SetRxFifo1Config(CAN_Type *base, const mcan_rx_fifo_config_t *config); - -/*! - * @brief Configures an MCAN receive buffer. - * - * This function sets start address and datafield size of the recieve buffer. - * - * @param base MCAN peripheral base address. - * @param config The receive buffer configuration structure. - */ -void MCAN_SetRxBufferConfig(CAN_Type *base, const mcan_rx_buffer_config_t *config); - -/*! - * @brief Configures an MCAN transmit event fifo. - * - * This function sets start address, element size, watermark of the transmit event fifo. - * - * @param base MCAN peripheral base address. - * @param config The transmit event fifo configuration structure. - */ -void MCAN_SetTxEventFifoConfig(CAN_Type *base, const mcan_tx_fifo_config_t *config); - -/*! - * @brief Configures an MCAN transmit buffer. - * - * This function sets start address, element size, fifo/queue mode and datafield - * size of the transmit buffer. - * - * @param base MCAN peripheral base address. - * @param config The transmit buffer configuration structure. - */ -void MCAN_SetTxBufferConfig(CAN_Type *base, const mcan_tx_buffer_config_t *config); - -/*! - * @brief Set filter configuration. - * - * This function sets remote and non masking frames in global filter configuration, - * also the start address, list size in standard/extended ID filter configuration. - * - * @param base MCAN peripheral base address. - * @param config The MCAN filter configuration. - */ -void MCAN_SetFilterConfig(CAN_Type *base, const mcan_frame_filter_config_t *config); - -/*! - * @brief Set standard message ID filter element configuration. - * - * @param base MCAN peripheral base address. - * @param config The MCAN filter configuration. - * @param filter The MCAN standard message ID filter element configuration. - * @param idx The standard message ID filter element index. - */ -void MCAN_SetSTDFilterElement(CAN_Type *base, - const mcan_frame_filter_config_t *config, - const mcan_std_filter_element_config_t *filter, - uint8_t idx); - -/*! - * @brief Set extended message ID filter element configuration. - * - * @param base MCAN peripheral base address. - * @param config The MCAN filter configuration. - * @param filter The MCAN extended message ID filter element configuration. - * @param idx The extended message ID filter element index. - */ -void MCAN_SetEXTFilterElement(CAN_Type *base, - const mcan_frame_filter_config_t *config, - const mcan_ext_filter_element_config_t *filter, - uint8_t idx); - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the MCAN module interrupt flags. - * - * This function gets all MCAN interrupt status flags. - * - * @param base MCAN peripheral base address. - * @param mask The ORed MCAN interrupt mask. - * @return MCAN status flags which are ORed. - */ -static inline uint32_t MCAN_GetStatusFlag(CAN_Type *base, uint32_t mask) -{ - return (base->IR & mask); -} - -/*! - * @brief Clears the MCAN module interrupt flags. - * - * This function clears MCAN interrupt status flags. - * - * @param base MCAN peripheral base address. - * @param mask The ORed MCAN interrupt mask. - */ -static inline void MCAN_ClearStatusFlag(CAN_Type *base, uint32_t mask) -{ - /* Write 1 to clear status flag, write 0 has no effect. */ - base->IR = mask; -} - -/*! - * @brief Gets the new data flag of specific Rx Buffer. - * - * This function gets new data flag of specific Rx Buffer. - * - * @param base MCAN peripheral base address. - * @param idx Rx Buffer index. - * @return Rx Buffer new data status flag. - */ -static inline bool MCAN_GetRxBufferStatusFlag(CAN_Type *base, uint8_t idx) -{ - assert(idx <= 63U); - - bool fgRet; - - if (idx <= 31U) - { - fgRet = (0U != (base->NDAT1 & ((uint32_t)1U << idx))); - } - else - { - fgRet = (0U != (base->NDAT2 & ((uint32_t)1U << (idx - 32U)))); - } - - return fgRet; -} - -/*! - * @brief Clears the new data flag of specific Rx Buffer. - * - * This function clears new data flag of specific Rx Buffer. - * - * @param base MCAN peripheral base address. - * @param idx Rx Buffer index. - */ -static inline void MCAN_ClearRxBufferStatusFlag(CAN_Type *base, uint8_t idx) -{ - assert(idx <= 63U); - - if (idx <= 31U) - { - base->NDAT1 &= ~((uint32_t)1U << idx); - } - else - { - base->NDAT2 &= ~((uint32_t)1U << (idx - 32U)); - } -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables MCAN interrupts according to the provided interrupt line and mask. - * - * This function enables the MCAN interrupts according to the provided interrupt line and mask. - * The mask is a logical OR of enumeration members. - * - * @param base MCAN peripheral base address. - * @param line Interrupt line number, 0 or 1. - * @param mask The interrupts to enable. - */ -static inline void MCAN_EnableInterrupts(CAN_Type *base, uint32_t line, uint32_t mask) -{ - base->ILE |= ((uint32_t)1U << line); - if (0U == line) - { - base->ILS &= ~mask; - } - else - { - base->ILS |= mask; - } - base->IE |= mask; -} - -/*! - * @brief Enables MCAN Tx Buffer interrupts according to the provided index. - * - * This function enables the MCAN Tx Buffer interrupts. - * - * @param base MCAN peripheral base address. - * @param idx Tx Buffer index. - */ -static inline void MCAN_EnableTransmitBufferInterrupts(CAN_Type *base, uint8_t idx) -{ - base->TXBTIE |= ((uint32_t)1U << idx); -} - -/*! - * @brief Disables MCAN Tx Buffer interrupts according to the provided index. - * - * This function disables the MCAN Tx Buffer interrupts. - * - * @param base MCAN peripheral base address. - * @param idx Tx Buffer index. - */ -static inline void MCAN_DisableTransmitBufferInterrupts(CAN_Type *base, uint8_t idx) -{ - base->TXBTIE &= (~((uint32_t)1U << idx)); -} - -/*! - * @brief Disables MCAN interrupts according to the provided mask. - * - * This function disables the MCAN interrupts according to the provided mask. - * The mask is a logical OR of enumeration members. - * - * @param base MCAN peripheral base address. - * @param mask The interrupts to disable. - */ -static inline void MCAN_DisableInterrupts(CAN_Type *base, uint32_t mask) -{ - base->IE &= ~mask; -} - -/* @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Gets the Tx buffer request pending status. - * - * This function returns Tx Message Buffer transmission request pending status. - * - * @param base MCAN peripheral base address. - * @param idx The MCAN Tx Buffer index. - */ -uint32_t MCAN_IsTransmitRequestPending(CAN_Type *base, uint8_t idx); - -/*! - * @brief Gets the Tx buffer transmission occurred status. - * - * This function returns Tx Message Buffer transmission occurred status. - * - * @param base MCAN peripheral base address. - * @param idx The MCAN Tx Buffer index. - */ -uint32_t MCAN_IsTransmitOccurred(CAN_Type *base, uint8_t idx); - -/*! - * @brief Writes an MCAN Message to the Transmit Buffer. - * - * This function writes a CAN Message to the specified Transmit Message Buffer - * and changes the Message Buffer state to start CAN Message transmit. After - * that the function returns immediately. - * - * @param base MCAN peripheral base address. - * @param idx The MCAN Tx Buffer index. - * @param pTxFrame Pointer to CAN message frame to be sent. - */ -status_t MCAN_WriteTxBuffer(CAN_Type *base, uint8_t idx, const mcan_tx_buffer_frame_t *pTxFrame); - -/*! - * @brief Reads an MCAN Message from Rx Buffer. - * - * This function reads a CAN message from the Rx Buffer in the Message RAM. - * - * @param base MCAN peripheral base address. - * @param idx The MCAN Rx Buffer index. - * @param pRxFrame Pointer to CAN message frame structure for reception. - * @retval kStatus_Success - Read Message from Rx Buffer successfully. - */ -status_t MCAN_ReadRxBuffer(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *pRxFrame); - -/*! - * @brief Reads an MCAN Message from Rx FIFO. - * - * This function reads a CAN message from the Rx FIFO in the Message RAM. - * - * @param base MCAN peripheral base address. - * @param fifoBlock Rx FIFO block 0 or 1. - * @param pRxFrame Pointer to CAN message frame structure for reception. - * @retval kStatus_Success - Read Message from Rx FIFO successfully. - */ -status_t MCAN_ReadRxFifo(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *pRxFrame); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Tx Buffer add request to send message out. - * - * This function add sending request to corresponding Tx Buffer. - * - * @param base MCAN peripheral base address. - * @param idx Tx Buffer index. - */ -static inline void MCAN_TransmitAddRequest(CAN_Type *base, uint8_t idx) -{ - base->TXBAR |= ((uint32_t)1U << idx); -} - -/*! - * @brief Tx Buffer cancel sending request. - * - * This function clears Tx buffer request pending bit. - * - * @param base MCAN peripheral base address. - * @param idx Tx Buffer index. - */ -static inline void MCAN_TransmitCancelRequest(CAN_Type *base, uint8_t idx) -{ - base->TXBCR |= ((uint32_t)1U << idx); -} - -/*! - * @brief Performs a polling send transaction on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * @param base MCAN peripheral base pointer. - * @param idx The MCAN buffer index. - * @param pTxFrame Pointer to CAN message frame to be sent. - * @retval kStatus_Success - Write Tx Message Buffer Successfully. - * @retval kStatus_Fail - Tx Message Buffer is currently in use. - */ -status_t MCAN_TransferSendBlocking(CAN_Type *base, uint8_t idx, mcan_tx_buffer_frame_t *pTxFrame); - -/*! - * @brief Performs a polling receive transaction on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * @param base MCAN peripheral base pointer. - * @param idx The MCAN buffer index. - * @param pRxFrame Pointer to CAN message frame structure for reception. - * @retval kStatus_Success - Read Rx Message Buffer Successfully. - * @retval kStatus_Fail - No new message. - */ -status_t MCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *pRxFrame); - -/*! - * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * @param base MCAN peripheral base pointer. - * @param fifoBlock Rx FIFO block, 0 or 1. - * @param pRxFrame Pointer to CAN message frame structure for reception. - * @retval kStatus_Success - Read Message from Rx FIFO successfully. - * @retval kStatus_Fail - No new message in Rx FIFO. - */ -status_t MCAN_TransferReceiveFifoBlocking(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *pRxFrame); - -/*! - * @brief Initializes the MCAN handle. - * - * This function initializes the MCAN handle, which can be used for other MCAN - * transactional APIs. Usually, for a specified MCAN instance, - * call this API once to get the initialized handle. - * - * @param base MCAN peripheral base address. - * @param handle MCAN handle pointer. - * @param callback The callback function. - * @param userData The parameter of the callback function. - */ -void MCAN_TransferCreateHandle(CAN_Type *base, - mcan_handle_t *handle, - mcan_transfer_callback_t callback, - void *userData); - -/*! - * @brief Sends a message using IRQ. - * - * This function sends a message using IRQ. This is a non-blocking function, which returns - * right away. When messages have been sent out, the send callback function is called. - * - * @param base MCAN peripheral base address. - * @param handle MCAN handle pointer. - * @param xfer MCAN Buffer transfer structure. See the #mcan_buffer_transfer_t. - * @retval kStatus_Success Start Tx Buffer sending process successfully. - * @retval kStatus_Fail Write Tx Buffer failed. - * @retval kStatus_MCAN_TxBusy Tx Buffer is in use. - */ -status_t MCAN_TransferSendNonBlocking(CAN_Type *base, mcan_handle_t *handle, mcan_buffer_transfer_t *xfer); - -/*! - * @brief Receives a message from Rx FIFO using IRQ. - * - * This function receives a message using IRQ. This is a non-blocking function, which returns - * right away. When all messages have been received, the receive callback function is called. - * - * @param base MCAN peripheral base address. - * @param handle MCAN handle pointer. - * @param fifoBlock Rx FIFO block, 0 or 1. - * @param xfer MCAN Rx FIFO transfer structure. See the @ref mcan_fifo_transfer_t. - * @retval kStatus_Success - Start Rx FIFO receiving process successfully. - * @retval kStatus_MCAN_RxFifo0Busy - Rx FIFO 0 is currently in use. - * @retval kStatus_MCAN_RxFifo1Busy - Rx FIFO 1 is currently in use. - */ -status_t MCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, - uint8_t fifoBlock, - mcan_handle_t *handle, - mcan_fifo_transfer_t *xfer); - -/*! - * @brief Aborts the interrupt driven message send process. - * - * This function aborts the interrupt driven message send process. - * - * @param base MCAN peripheral base address. - * @param handle MCAN handle pointer. - * @param bufferIdx The MCAN Buffer index. - */ -void MCAN_TransferAbortSend(CAN_Type *base, mcan_handle_t *handle, uint8_t bufferIdx); - -/*! - * @brief Aborts the interrupt driven message receive from Rx FIFO process. - * - * This function aborts the interrupt driven message receive from Rx FIFO process. - * - * @param base MCAN peripheral base address. - * @param fifoBlock MCAN Fifo block, 0 or 1. - * @param handle MCAN handle pointer. - */ -void MCAN_TransferAbortReceiveFifo(CAN_Type *base, uint8_t fifoBlock, mcan_handle_t *handle); - -/*! - * @brief MCAN IRQ handle function. - * - * This function handles the MCAN Error, the Buffer, and the Rx FIFO IRQ request. - * - * @param base MCAN peripheral base address. - * @param handle MCAN handle pointer. - */ -void MCAN_TransferHandleIRQ(CAN_Type *base, mcan_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_MCAN_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mrt.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mrt.c deleted file mode 100644 index d80e16de416..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mrt.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_mrt.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.mrt" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base Multi-Rate timer peripheral base address - * - * @return The MRT instance - */ -static uint32_t MRT_GetInstance(MRT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to MRT bases for each instance. */ -static MRT_Type *const s_mrtBases[] = MRT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to MRT clocks for each instance. */ -static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET -/*! @brief Pointers to MRT resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_mrtResets[] = MRT_RSTS_N; -#else -/*! @brief Pointers to MRT resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_mrtResets[] = MRT_RSTS; -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t MRT_GetInstance(MRT_Type *base) -{ - uint32_t instance; - uint32_t mrtArrayCount = (sizeof(s_mrtBases) / sizeof(s_mrtBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < mrtArrayCount; instance++) - { - if (s_mrtBases[instance] == base) - { - break; - } - } - - assert(instance < mrtArrayCount); - - return instance; -} - -/*! - * brief Ungates the MRT clock and configures the peripheral for basic operation. - * - * note This API should be called at the beginning of the application using the MRT driver. - * - * param base Multi-Rate timer peripheral base address - * param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in - * MODCFG reigster, param config is useless. - */ -void MRT_Init(MRT_Type *base, const mrt_config_t *config) -{ - assert(config != NULL); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate the MRT clock */ - CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) - /* Set timer operating mode */ - base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask); -#endif -} - -/*! - * brief Gate the MRT clock - * - * param base Multi-Rate timer peripheral base address - */ -void MRT_Deinit(MRT_Type *base) -{ - /* Stop all the timers */ - MRT_StopTimer(base, kMRT_Channel_0); - MRT_StopTimer(base, kMRT_Channel_1); -#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 2U) - MRT_StopTimer(base, kMRT_Channel_2); -#endif -#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 3U) - MRT_StopTimer(base, kMRT_Channel_3); -#endif - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the MRT clock*/ - CLOCK_DisableClock(s_mrtClocks[MRT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Used to update the timer period in units of count. - * - * The new value will be immediately loaded or will be loaded at the end of the current time - * interval. For one-shot interrupt mode the new value will be immediately loaded. - * - * note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * param base Multi-Rate timer peripheral base address - * param channel Timer channel number - * param count Timer period in units of ticks - * param immediateLoad true: Load the new value immediately into the TIMER register; - * false: Load the new value at the end of current timer interval - */ -void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - - uint32_t newValue = count; - if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == (uint8_t)kMRT_OneShotMode) || (immediateLoad)) - { - /* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */ - newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK; - } - - /* Update the timer interval value */ - base->CHANNEL[channel].INTVAL = newValue; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mrt.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mrt.h deleted file mode 100644 index 7829d984e20..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mrt.h +++ /dev/null @@ -1,366 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_MRT_H_ -#define _FSL_MRT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup mrt - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3 */ -/*@}*/ - -/*! @brief List of MRT channels */ -typedef enum _mrt_chnl -{ - kMRT_Channel_0 = 0U, /*!< MRT channel number 0*/ - kMRT_Channel_1, /*!< MRT channel number 1 */ - kMRT_Channel_2, /*!< MRT channel number 2 */ - kMRT_Channel_3 /*!< MRT channel number 3 */ -} mrt_chnl_t; - -/*! @brief List of MRT timer modes */ -typedef enum _mrt_timer_mode -{ - kMRT_RepeatMode = (0 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< Repeat Interrupt mode */ - kMRT_OneShotMode = (1 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< One-shot Interrupt mode */ - kMRT_OneShotStallMode = (2 << MRT_CHANNEL_CTRL_MODE_SHIFT) /*!< One-shot stall mode */ -} mrt_timer_mode_t; - -/*! @brief List of MRT interrupts */ -typedef enum _mrt_interrupt_enable -{ - kMRT_TimerInterruptEnable = MRT_CHANNEL_CTRL_INTEN_MASK /*!< Timer interrupt enable*/ -} mrt_interrupt_enable_t; - -/*! @brief List of MRT status flags */ -typedef enum _mrt_status_flags -{ - kMRT_TimerInterruptFlag = MRT_CHANNEL_STAT_INTFLAG_MASK, /*!< Timer interrupt flag */ - kMRT_TimerRunFlag = MRT_CHANNEL_STAT_RUN_MASK, /*!< Indicates state of the timer */ -} mrt_status_flags_t; - -/*! - * @brief MRT configuration structure - * - * This structure holds the configuration settings for the MRT peripheral. To initialize this - * structure to reasonable defaults, call the MRT_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _mrt_config -{ - bool enableMultiTask; /*!< true: Timers run in multi-task mode; false: Timers run in hardware status mode */ -} mrt_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the MRT clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the MRT driver. - * - * @param base Multi-Rate timer peripheral base address - * @param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in - * MODCFG reigster, param config is useless. - */ -void MRT_Init(MRT_Type *base, const mrt_config_t *config); - -/*! - * @brief Gate the MRT clock - * - * @param base Multi-Rate timer peripheral base address - */ -void MRT_Deinit(MRT_Type *base); - -/*! - * @brief Fill in the MRT config struct with the default settings - * - * The default values are: - * @code - * config->enableMultiTask = false; - * @endcode - * @param config Pointer to user's MRT config structure. - */ -static inline void MRT_GetDefaultConfig(mrt_config_t *config) -{ - assert(config != NULL); -#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) - /* Use hardware status operating mode */ - config->enableMultiTask = false; -#endif -} - -/*! - * @brief Sets up an MRT channel mode. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Channel that is being configured. - * @param mode Timer mode to use for the channel. - */ -static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - - uint32_t reg = base->CHANNEL[channel].CTRL; - - /* Clear old value */ - reg &= ~MRT_CHANNEL_CTRL_MODE_MASK; - /* Add the new mode */ - reg |= (uint32_t)mode; - - base->CHANNEL[channel].CTRL = reg; -} - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the MRT interrupt. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].CTRL |= mask; -} - -/*! - * @brief Disables the selected MRT interrupt. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to disable. This is a logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].CTRL &= ~mask; -} - -/*! - * @brief Gets the enabled MRT interrupts. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the MRT status flags - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::mrt_status_flags_t - */ -static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK)); -} - -/*! - * @brief Clears the MRT status flags. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::mrt_status_flags_t - */ -static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK); -} - -/*! @}*/ - -/*! - * @name Read and Write the timer period - * @{ - */ - -/*! - * @brief Used to update the timer period in units of count. - * - * The new value will be immediately loaded or will be loaded at the end of the current time - * interval. For one-shot interrupt mode the new value will be immediately loaded. - * - * @note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param count Timer period in units of ticks - * @param immediateLoad true: Load the new value immediately into the TIMER register; - * false: Load the new value at the end of current timer interval - */ -void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad); - -/*! - * @brief Reads the current timer counting value. - * - * This function returns the real-time timer counting value, in a range from 0 to a - * timer period. - * - * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return Current timer counting value in ticks - */ -static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - return base->CHANNEL[channel].TIMER; -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the timer counting. - * - * After calling this function, timers load period value, counts down to 0 and - * depending on the timer mode it will either load the respective start value again or stop. - * - * @note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - * @param count Timer period in units of ticks. Count can contain the LOAD bit, which control the force load feature. - */ -static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - assert((uint32_t)(count & ~MRT_CHANNEL_INTVAL_LOAD_MASK) <= (uint32_t)MRT_CHANNEL_INTVAL_IVALUE_MASK); - /* Write the timer interval value */ - base->CHANNEL[channel].INTVAL = count; -} - -/*! - * @brief Stops the timer counting. - * - * This function stops the timer from counting. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - */ -static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - /* Stop the timer immediately */ - base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK; -} - -/*! @}*/ - -/*! - * @name Get & release channel - * @{ - */ - -/*! - * @brief Find the available channel. - * - * This function returns the lowest available channel number. - * - * @param base Multi-Rate timer peripheral base address - */ -static inline uint32_t MRT_GetIdleChannel(MRT_Type *base) -{ - return base->IDLE_CH; -} - -#if !(defined(FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) && FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) -/*! - * @brief Release the channel when the timer is using the multi-task mode. - * - * In multi-task mode, the INUSE flags allow more control over when MRT channels are released for - * further use. The user can hold on to a channel acquired by calling MRT_GetIdleChannel() for as - * long as it is needed and release it by calling this function. This removes the need to ask for - * an available channel for every use. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - */ -static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - - uint32_t reg = base->CHANNEL[channel].STAT; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg = ~MRT_CHANNEL_STAT_INTFLAG_MASK; - reg |= MRT_CHANNEL_STAT_INUSE_MASK; - - base->CHANNEL[channel].STAT = reg; -} -#endif - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_MRT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_opamp.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_opamp.c deleted file mode 100644 index fc1f96e4167..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_opamp.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_opamp.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.opamp" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -static uint32_t OPAMP_GetInstance(OPAMP_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -static OPAMP_Type *const s_opampBases[] = OPAMP_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to OPAMP clocks for each instance. */ -static const clock_ip_name_t s_opampClocks[] = OPAMP_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t OPAMP_GetInstance(OPAMP_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0UL; instance < ARRAY_SIZE(s_opampBases); instance++) - { - if (s_opampBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_opampBases)); - - return instance; -} - -/*! - * brief Initialize OPAMP instance. - * - * param base OPAMP peripheral base address. - * param config The pointer to opamp_config_t. - */ -void OPAMP_Init(OPAMP_Type *base, const opamp_config_t *config) -{ - assert(config != NULL); - - uint32_t tmp32; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(s_opampClocks[OPAMP_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - tmp32 = base->OPAMP_CTR; - tmp32 &= ~(OPAMP_OPAMP_CTR_EN_MASK | OPAMP_OPAMP_CTR_MODE_MASK | OPAMP_OPAMP_CTR_BIASC_MASK | - OPAMP_OPAMP_CTR_INTREF_MASK | OPAMP_OPAMP_CTR_ADCSW_MASK | OPAMP_OPAMP_CTR_PREF_MASK | - OPAMP_OPAMP_CTR_PGAIN_MASK | OPAMP_OPAMP_CTR_NGAIN_MASK); - tmp32 |= OPAMP_OPAMP_CTR_EN(config->enable) | OPAMP_OPAMP_CTR_MODE(config->mode) | - OPAMP_OPAMP_CTR_BIASC(config->trimOption) | OPAMP_OPAMP_CTR_INTREF(config->intRefVoltage) | - OPAMP_OPAMP_CTR_ADCSW(config->enablePosADCSw) | OPAMP_OPAMP_CTR_PREF(config->posRefVoltage) | - OPAMP_OPAMP_CTR_PGAIN(config->posGain) | OPAMP_OPAMP_CTR_NGAIN(config->negGain); - base->OPAMP_CTR = tmp32; -} - -/*! - * brief De-initialize OPAMP instance. - * - * param base OPAMP peripheral base address. - */ -void OPAMP_Deinit(OPAMP_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(s_opampClocks[OPAMP_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Disable OPAMP instance. */ - base->OPAMP_CTR &= ~OPAMP_OPAMP_CTR_EN_MASK; -} - -/*! - * brief Get default configuration of OPAMP. - * - * code - * config->enable = false; - * config->mode = kOPAMP_LowNoiseMode; - * config->trimOption = kOPAMP_TrimOptionDefault; - * config->intRefVoltage = kOPAMP_IntRefVoltVddaDiv2; - * config->enablePosADCSw = false; - * config->posRefVoltage = kOPAMP_PosRefVoltVrefh3; - * config->posGain = kOPAMP_PosGainReserved; - * config->negGain = kOPAMP_NegGainBufferMode; - * endcode - * - * param config The pointer to opamp_config_t. - */ -void OPAMP_GetDefaultConfig(opamp_config_t *config) -{ - assert(config != NULL); - - config->enable = false; - config->mode = kOPAMP_LowNoiseMode; - config->trimOption = kOPAMP_TrimOptionDefault; - config->intRefVoltage = kOPAMP_IntRefVoltVddaDiv2; - - config->enablePosADCSw = false; - config->posRefVoltage = kOPAMP_PosRefVoltVrefh3; - config->posGain = kOPAMP_PosGainReserved; - - config->negGain = kOPAMP_NegGainBufferMode; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_opamp.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_opamp.h deleted file mode 100644 index 3a3ceaa731e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_opamp.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_OPAMP_H_ -#define _FSL_OPAMP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup opamp - * @{ - */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief OPAMP driver version. */ -#define FSL_OPAMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! - * @brief The enumeration of OPAMP mode, including low noise mode and high speed mode. - */ -typedef enum _opamp_mode -{ - kOPAMP_LowNoiseMode = 0U, /*!< Set opamp mode as low noise mode. */ - kOPAMP_HighSpeedMode, /*!< Set opamp mode as high speed mode. */ -} opamp_mode_t; - -/*! - * @brief The enumeration of bias current trim option. - */ -typedef enum _opamp_bias_current_trim_option -{ - kOPAMP_TrimOptionDefault = 0U, /*!< Default Bias current trim option. */ - kOPAMP_TrimOptionIncreaseCurrent, /*!< Trim option selected as increase current. */ - kOPAMP_TrimOptionDecreaseCurrent, /*!< Trim option selected as decrease current. */ - kOPAMP_TrimOptionFurtherDecreaseCurrent, /*!< Trim option selected as further decrease current. */ -} opamp_bias_current_trim_option_t; - -/*! - * @brief The enumeration of internal reference voltage. - */ -typedef enum _opamp_internal_ref_voltage -{ - kOPAMP_IntRefVoltVddaDiv2 = 0U, /*!< Internal reference voltage selected as Vdda/2. */ - kOPAMP_IntRefVoltVdda3V, /*!< Internal reference voltage selected as Vdda_3V. */ - kOPAMP_IntRefVoltVssa3V, /*!< Internal reference voltage selected as Vssa_3V. */ - kOPAMP_IntRefVoltNotAllowed, /*!< Internal reference voltage not allowed. */ -} opamp_internal_ref_voltage_t; - -/*! - * @brief The enumeration of positive reference voltage. - */ -typedef enum _opamp_positive_ref_voltage -{ - kOPAMP_PosRefVoltVrefh3 = 0U, /*!< Positive part reference voltage select Vrefh3, connected from DAC output. */ - kOPAMP_PosRefVoltVrefh0 = 1U, /*!< Positive part reference voltage select Vrefh0, connected from VDDA supply. */ - kOPAMP_PosRefVoltVrefh1 = 2U, /*!< Positive part reference voltage select Vrefh1, - connected from Voltage reference output. */ - kOPAMP_PosRefVoltReserved = 3U, /*!< Positive part reference voltage reserved. */ -} opamp_positive_ref_voltage_t; - -/*! - * @brief The enumeration of positive programmable gain. - */ -typedef enum _opamp_positive_gain -{ - kOPAMP_PosGainReserved = 0U, /*!< Positive Gain reserved. */ - kOPAMP_PosGainNonInvert1X, /*!< Positive non-inverting gain application 1X. */ - kOPAMP_PosGainNonInvert2X, /*!< Positive non-inverting gain application 2X. */ - kOPAMP_PosGainNonInvert4X, /*!< Positive non-inverting gain application 4X. */ - kOPAMP_PosGainNonInvert8X, /*!< Positive non-inverting gain application 8X. */ - kOPAMP_PosGainNonInvert16X, /*!< Positive non-inverting gain application 16X. */ - kOPAMP_PosGainNonInvert33X, /*!< Positive non-inverting gain application 33X. */ - kOPAMP_PosGainNonInvert64X, /*!< Positive non-inverting gain application 64X. */ -} opamp_positive_gain_t; - -/*! - * @brief The enumeration of negative programmable gain. - */ -typedef enum _opamp_negative_gain -{ - kOPAMP_NegGainBufferMode = 0U, /*!< Negative Buffer Mode. */ - kOPAMP_NegGainInvert1X, /*!< Negative inverting gain application -1X. */ - kOPAMP_NegGainInvert2X, /*!< Negative inverting gain application -2X. */ - kOPAMP_NegGainInvert4X, /*!< Negative inverting gain application -4X. */ - kOPAMP_NegGainInvert8X, /*!< Negative inverting gain application -8X. */ - kOPAMP_NegGainInvert16X, /*!< Negative inverting gain application -16X. */ - kOPAMP_NegGainInvert33X, /*!< Negative inverting gain application -33X. */ - kOPAMP_NegGainInvert64X, /*!< Negative inverting gain application -64X. */ -} opamp_negative_gain_t; - -/*! - * @brief OPAMP configuraion, including mode, internal reference voltage, positive gain, negative gain and so on. - */ -typedef struct _opamp_config -{ - bool enable; /*!< Enable/disable OPAMP. */ - opamp_mode_t mode; /*!< Opamp mode, available values are @ref kOPAMP_LowNoiseMode and @ref kOPAMP_HighSpeedMode. */ - opamp_bias_current_trim_option_t trimOption; /*!< Bias current trim option, please refer to - @ref opamp_bias_current_trim_option_t. */ - opamp_internal_ref_voltage_t intRefVoltage; /*!< Internal reference voltage, please refer to - @ref opamp_internal_ref_voltage_t. */ - - /* Positive part configuration. */ - bool enablePosADCSw; /*!< Positive part reference voltage switch to ADC channel or not. - - \b true Positive part reference voltage switch to ADC channel. - - \b false Positive part reference voltage do not switch to ADC channel. */ - opamp_positive_ref_voltage_t posRefVoltage; /*!< Positive part reference voltage, please refer - to @ref opamp_positive_ref_voltage_t. */ - opamp_positive_gain_t posGain; /*!< Positive part programmable gain, please refer - to @ref opamp_positive_gain_t. */ - - /* Negative part configuration. */ - opamp_negative_gain_t negGain; /*!< Negative part programmable gain, please refer - to @ref opamp_negative_gain_t. */ - -} opamp_config_t; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initialize OPAMP instance. - * - * @param base OPAMP peripheral base address. - * @param config The pointer to @ref opamp_config_t. - */ -void OPAMP_Init(OPAMP_Type *base, const opamp_config_t *config); - -/*! - * @brief De-initialize OPAMP instance. - * - * @param base OPAMP peripheral base address. - */ -void OPAMP_Deinit(OPAMP_Type *base); - -/*! - * @brief Get default configuration of OPAMP. - * - * @code - * config->enable = false; - * config->mode = kOPAMP_LowNoiseMode; - * config->trimOption = kOPAMP_TrimOptionDefault; - * config->intRefVoltage = kOPAMP_IntRefVoltVddaDiv2; - * config->enablePosADCSw = false; - * config->posRefVoltage = kOPAMP_PosRefVoltVrefh3; - * config->posGain = kOPAMP_PosGainReserved; - * config->negGain = kOPAMP_NegGainBufferMode; - * @endcode - * - * @param config The pointer to @ref opamp_config_t. - */ -void OPAMP_GetDefaultConfig(opamp_config_t *config); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_OPAMP_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ostimer.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ostimer.c deleted file mode 100644 index cfa28bafa23..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ostimer.c +++ /dev/null @@ -1,395 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_ostimer.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.ostimer" -#endif - -/* Typedef for interrupt handler. */ -typedef void (*ostimer_isr_t)(OSTIMER_Type *base, ostimer_callback_t cb); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base OSTIMER peripheral base address - * - * @return The OSTIMER instance - */ -static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base); - -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) -/* @brief Translate the value from gray-code to decimal by the Code Gray in SYSCTL. - * - * @param gray The gray value input. - * - * @return the decimal value. - */ -static uint64_t OSTIMER_GrayToDecimalbyCodeGray(uint64_t gray); -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ - -/* @brief Translate the value from gray-code to decimal. */ -/* - * @param gray The gray value input. - * - * @return the decimal value. - */ -static uint64_t OSTIMER_GrayToDecimal(uint64_t gray); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of OSTIMER handle. */ -static ostimer_callback_t s_ostimerHandle[FSL_FEATURE_SOC_OSTIMER_COUNT]; -/* Array of OSTIMER peripheral base address. */ -static OSTIMER_Type *const s_ostimerBases[] = OSTIMER_BASE_PTRS; -/* Array of OSTIMER IRQ number. */ -static const IRQn_Type s_ostimerIRQ[] = OSTIMER_IRQS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of OSTIMER clock name. */ -static const clock_ip_name_t s_ostimerClock[] = OSTIMER_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/* OSTIMER ISR for transactional APIs. */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -static ostimer_isr_t s_ostimerIsr = (ostimer_isr_t)DefaultISR; -#else -static ostimer_isr_t s_ostimerIsr; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* @brief Function for getting the instance number of OS timer. */ -static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_ostimerBases); instance++) - { - if (s_ostimerBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_ostimerBases)); - - return instance; -} - -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) -/* @brief Translate the value from gray-code to decimal by the Code Gray in SYSCTL. - * - * @param gray The gray value input. - * - * @return the decimal value. - */ -static uint64_t OSTIMER_GrayToDecimalbyCodeGray(uint64_t gray) -{ - uint64_t decOut; - - SYSCTL->CODE_GRAY_LSB = (uint32_t)(gray & 0xFFFFFFFFU); - SYSCTL->CODE_GRAY_MSB = (uint32_t)((gray >> 32U) & 0x3FFU); // limit to 42bits as OSevent timer - __NOP(); - decOut = ((uint64_t)(SYSCTL->CODE_BIN_MSB) & 0x3FFU) << 32U; - decOut |= (uint64_t)(SYSCTL->CODE_BIN_LSB); - - return decOut; -} -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ - -/* @brief Translate the value from gray-code to decimal. */ -/* - * @param gray The gray value input. - * - * @return the decimal value. - */ -static uint64_t OSTIMER_GrayToDecimal(uint64_t gray) -{ -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) - return OSTIMER_GrayToDecimalbyCodeGray(gray); -#else - uint64_t temp = gray; - while (temp != 0U) - { - temp >>= 1U; - gray ^= temp; - } - - return gray; -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ -} - -/* @brief Translate the value from decimal to gray-code. */ -static uint64_t OSTIMER_DecimalToGray(uint64_t dec) -{ - return (dec ^ (dec >> 1U)); -} - -/* @brief Enable the OSTIMER interrupt. - * - * After calling this function, the OSTIMER driver will enable/disable the IRQ and module interrupt enablement. - * - * @param base OSTIMER peripheral base address. - * @param enable enable/disable the IRQ and module interrupt enablement. - * - true: Disable the IRQ and module interrupt enablement. - * - false: Disable the IRQ and module interrupt enablement. - * @return none - */ -static void OSTIMER_EnableInterrupt(OSTIMER_Type *base, bool enable) -{ - assert(NULL != base); - - if (enable) - { - /* Enable the IRQ and module interrupt enablement. */ - (void)EnableIRQ(s_ostimerIRQ[OSTIMER_GetInstance(base)]); - base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; - } - else - { - /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ - (void)DisableIRQ(s_ostimerIRQ[OSTIMER_GetInstance(base)]); - base->OSEVENT_CTRL &= ~OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; /* Clear interrupt flag by writing 1. */ - } -} - -/*! - * @brief Initializes an OSTIMER by turning it's clock on. - * - */ -void OSTIMER_Init(OSTIMER_Type *base) -{ - assert(NULL != base); - - uint32_t instance = OSTIMER_GetInstance(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if !(defined(FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) && FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) - /* Enable the OSTIMER 32k clock in PMC module. */ - CLOCK_EnableOstimer32kClock(); -#endif - /* Enable clock for OSTIMER. */ - CLOCK_EnableClock(s_ostimerClock[instance]); -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) - CLOCK_EnableClock(kCLOCK_Sysctl); -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Deinitializes a OSTIMER instance. - * - * This function shuts down OSTIMER clock - * - * @param base OSTIMER peripheral base address. - */ -void OSTIMER_Deinit(OSTIMER_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable clock for OSTIMER. */ - CLOCK_DisableClock(s_ostimerClock[OSTIMER_GetInstance(base)]); -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) - CLOCK_DisableClock(kCLOCK_Sysctl); -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Get OSTIMER status Flags. - * - * This returns the status flag. - * Currently, only match interrupt flag can be got. - * - * @param base OSTIMER peripheral base address. - * @return status register value - */ -uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base) -{ - return base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK; -} - -/*! - * @brief Clear Status Interrupt Flags. - * - * This clears intr status flag. - * Currently, only match interrupt flag can be cleared. - * - * @param base OSTIMER peripheral base address. - * @param mask Clear bit mask. - * @return none - */ -void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask) -{ - base->OSEVENT_CTRL |= mask; -} - -/*! - * @brief Set the match raw value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. - * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is gray-code format) - * - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. - * @retval kStatus_Fail - Set match raw value fail. - */ -status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) -{ -#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK - uint64_t decValueTimer; -#endif - status_t status; - uint64_t tmp = count; - uint32_t instance = OSTIMER_GetInstance(base); - - /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ - OSTIMER_EnableInterrupt(base, false); - - s_ostimerIsr = OSTIMER_HandleIRQ; - s_ostimerHandle[instance] = cb; - - /* Set the match value. */ - base->MATCH_L = (uint32_t)tmp; - base->MATCH_H = (uint32_t)(tmp >> 32U); - -#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK - /* Workaround-2019-12-30: - * Since OSTimer's counter register is Gray-encoded, it would cost more time to write register. When EVTimer Match - * Write Ready bit is low, which means the previous match value has been updated successfully by that time, it is - * safe to reload (write) the Match Registers. Even if there is the RM comment that "In typical applications, it - * should not be necessary to test this bit", but we found the interruption would not be reported when the delta - * timer user added is smaller(IE: RT595 11us in 1MHz typical application) in release version." To prevent such - * issue from happening, we'd better wait for the match value to update successfully before enabling IRQ. - */ - while (0U != (base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)) - { - } - - /* After the WR_RDY bit became low, we need to check whether current time goes ahead of the match value we set. - * (1) If current timer value has gone ahead of the match value, the interrupt will not be reported before 64-bit - * timer value over flow. We need to check whether the interrupt flag has been set or not: if yes, we will enable - * interrupt and return success; if not, we will return fail directly. - * (2) If current timer value has not gone ahead of match value, we will enable interrupt and return success. - */ - decValueTimer = OSTIMER_GetCurrentTimerValue(base); - if ((decValueTimer >= OSTIMER_GrayToDecimal(tmp)) && - (0U == (base->OSEVENT_CTRL & (uint32_t)kOSTIMER_MatchInterruptFlag))) - { - status = kStatus_Fail; - } - else -#endif /* #ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK */ - { - /* Enable the module interrupt enablement. */ - OSTIMER_EnableInterrupt(base, true); - status = kStatus_Success; - } - - return status; -} - -/*! - * @brief Set the match value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code in - * API. ) - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @retval kStatus_Success - Set match value and enable interrupt Successfully. - * @retval kStatus_Fail - Set match value fail. - */ -status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) -{ - uint64_t tmp = OSTIMER_DecimalToGray(count); - - return OSTIMER_SetMatchRawValue(base, tmp, cb); -} - -/*! - * @brief Get current timer count value from OSTIMER. - * - * This function will get a decimal timer count value. - * The RAW value of timer count is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of OSTIMER which will formated to decimal value. - */ -uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = OSTIMER_GetCurrentTimerRawValue(base); - - return OSTIMER_GrayToDecimal(tmp); -} - -/*! - * @brief Get the capture value from OSTIMER. - * - * This function will get a capture decimal-value from OSTIMER. - * The RAW value of timer capture is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of capture register, data format is decimal. - */ -uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = OSTIMER_GetCaptureRawValue(base); - - return OSTIMER_GrayToDecimal(tmp); -} - -void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb) -{ - /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ - OSTIMER_EnableInterrupt(base, false); - - if (cb != NULL) - { - cb(); - } -} - -#if defined(OSTIMER0) -void OS_EVENT_DriverIRQHandler(void); -void OS_EVENT_DriverIRQHandler(void) -{ - s_ostimerIsr(OSTIMER0, s_ostimerHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(OSTIMER) -void OS_EVENT_DriverIRQHandler(void); -void OS_EVENT_DriverIRQHandler(void) -{ - s_ostimerIsr(OSTIMER, s_ostimerHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ostimer.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ostimer.h deleted file mode 100644 index c805ce31609..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ostimer.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_OSTIMER_H_ -#define _FSL_OSTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup ostimer - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief OSTIMER driver version. */ -#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) -/*@}*/ - -/*! - * @brief OSTIMER status flags. - */ -enum _ostimer_flags -{ - kOSTIMER_MatchInterruptFlag = (OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK), /*!< Match interrupt flag bit, sets if - the match value was reached. */ -}; - -/*! @brief ostimer callback function. */ -typedef void (*ostimer_callback_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes an OSTIMER by turning its bus clock on - * - */ -void OSTIMER_Init(OSTIMER_Type *base); - -/*! - * @brief Deinitializes a OSTIMER instance. - * - * This function shuts down OSTIMER bus clock - * - * @param base OSTIMER peripheral base address. - */ -void OSTIMER_Deinit(OSTIMER_Type *base); - -/*! - * @brief Get OSTIMER status Flags. - * - * This returns the status flag. - * Currently, only match interrupt flag can be got. - * - * @param base OSTIMER peripheral base address. - * @return status register value - */ -uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base); - -/*! - * @brief Clear Status Interrupt Flags. - * - * This clears intrrupt status flag. - * Currently, only match interrupt flag can be cleared. - * - * @param base OSTIMER peripheral base address. - * @param mask Clear bit mask. - * @return none - */ -void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask); - -/*! - * @brief Set the match raw value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. - * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is gray-code format) - * - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. - * @retval kStatus_Fail - Set match raw value fail. - */ -status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); - -/*! - * @brief Set the match value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central OS TIMER. - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code - * internally.) - * - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @retval kStatus_Success - Set match value and enable interrupt Successfully. - * @retval kStatus_Fail - Set match value fail. - */ -status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); - -/*! - * @brief Get current timer raw count value from OSTIMER. - * - * This function will get a gray code type timer count value from OS timer register. - * The raw value of timer count is gray code format. - * - * @param base OSTIMER peripheral base address. - * @return Raw value of OSTIMER, gray code format. - */ -static inline uint64_t OSTIMER_GetCurrentTimerRawValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = base->EVTIMERL; - tmp |= (uint64_t)(base->EVTIMERH) << 32U; - - return tmp; -} - -/*! - * @brief Get current timer count value from OSTIMER. - * - * This function will get a decimal timer count value. - * The RAW value of timer count is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of OSTIMER which will be formated to decimal value. - */ -uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base); - -/*! - * @brief Get the capture value from OSTIMER. - * - * This function will get a captured gray-code value from OSTIMER. - * The Raw value of timer capture is gray code format. - * - * @param base OSTIMER peripheral base address. - * @return Raw value of capture register, data format is gray code. - */ -static inline uint64_t OSTIMER_GetCaptureRawValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = base->CAPTURE_L; - tmp |= (uint64_t)(base->CAPTURE_H) << 32U; - - return tmp; -} - -/*! - * @brief Get the capture value from OSTIMER. - * - * This function will get a capture decimal-value from OSTIMER. - * The RAW value of timer capture is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of capture register, data format is decimal. - */ -uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base); - -/*! - * @brief OS timer interrupt Service Handler. - * - * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request - * in OSTIMER_SetMatchValue()). - * if no user callback is scheduled, the interrupt will simply be cleared. - * - * @param base OS timer peripheral base address. - * @param cb callback scheduled for this instance of OS timer - * @return none - */ -void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb); -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_OSTIMER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pint.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pint.c deleted file mode 100644 index f658b7990df..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pint.c +++ /dev/null @@ -1,968 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_pint.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.pint" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -/*! @brief Irq number array */ -static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS + - FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; - -/*! @brief Callback function array for SECPINT(s). */ -static pint_cb_t s_secpintCallback[FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS]; -#else -/*! @brief Irq number array */ -static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - -/*! @brief Callback function array for PINT(s). */ -static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Initialize PINT peripheral. - - * This function initializes the PINT peripheral and enables the clock. - * - * param base Base address of the PINT peripheral. - * - * retval None. - */ -void PINT_Init(PINT_Type *base) -{ - uint32_t i; - uint32_t pmcfg = 0; - uint8_t pintcount = 0; - assert(base != NULL); - - if (base == PINT) - { - pintcount = FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; - /* clear PINT callback array*/ - for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_pintCallback[i] = NULL; - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - pintcount = FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; - /* clear SECPINT callback array*/ - for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_secpintCallback[i] = NULL; - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - - /* Disable all bit slices for pint*/ - for (i = 0; i < pintcount; i++) - { - pmcfg = pmcfg | ((uint32_t)kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U))); - } - -#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_GpioInt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) - - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio_Sec); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - -#else - - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Pint); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } - else - { - /* if need config SECURE PINT device,then enable secure pint interrupt clock */ -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio_Sec_Int); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } -#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ - - /* Disable all pattern match bit slices */ - base->PMCFG = pmcfg; -} - -/*! - * brief Configure PINT peripheral pin interrupt. - - * This function configures a given pin interrupt. - * - * param base Base address of the PINT peripheral. - * param intr Pin interrupt. - * param enable Selects detection logic. - * param callback Callback. - * - * retval None. - */ -void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback) -{ - assert(base != NULL); - - /* Clear Rise and Fall flags first */ - PINT_PinInterruptClrRiseFlag(base, intr); - PINT_PinInterruptClrFallFlag(base, intr); - - /* Security PINT uses additional callback array */ - if (base == PINT) - { - s_pintCallback[intr] = callback; - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - s_secpintCallback[intr] = callback; -#endif - } - - /* select level or edge sensitive */ - base->ISEL = (base->ISEL & ~(1UL << (uint32_t)intr)) | - ((((uint32_t)enable & PINT_PIN_INT_LEVEL) != 0U) ? (1UL << (uint32_t)intr) : 0U); - - /* enable rising or level interrupt */ - if (((unsigned)enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE)) != 0U) - { - base->SIENR = 1UL << (uint32_t)intr; - } - else - { - base->CIENR = 1UL << (uint32_t)intr; - } - - /* Enable falling or select high level */ - if (((unsigned)enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL) != 0U) - { - base->SIENF = 1UL << (uint32_t)intr; - } - else - { - base->CIENF = 1UL << (uint32_t)intr; - } -} - -/*! - * brief Get PINT peripheral pin interrupt configuration. - - * This function returns the configuration of a given pin interrupt. - * - * param base Base address of the PINT peripheral. - * param pintr Pin interrupt. - * param enable Pointer to store the detection logic. - * param callback Callback. - * - * retval None. - */ -void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback) -{ - uint32_t mask; - bool level; - - assert(base != NULL); - - *enable = kPINT_PinIntEnableNone; - level = false; - - mask = 1UL << (uint32_t)pintr; - if ((base->ISEL & mask) != 0U) - { - /* Pin interrupt is level sensitive */ - level = true; - } - - if ((base->IENR & mask) != 0U) - { - if (level) - { - /* Level interrupt is enabled */ - *enable = kPINT_PinIntEnableLowLevel; - } - else - { - /* Rising edge interrupt */ - *enable = kPINT_PinIntEnableRiseEdge; - } - } - - if ((base->IENF & mask) != 0U) - { - if (level) - { - /* Level interrupt is active high */ - *enable = kPINT_PinIntEnableHighLevel; - } - else - { - /* Either falling or both edge */ - if (*enable == kPINT_PinIntEnableRiseEdge) - { - /* Rising and faling edge */ - *enable = kPINT_PinIntEnableBothEdges; - } - else - { - /* Falling edge */ - *enable = kPINT_PinIntEnableFallEdge; - } - } - } - - /* Security PINT uses additional callback array */ - if (base == PINT) - { - *callback = s_pintCallback[pintr]; - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - *callback = s_secpintCallback[pintr]; -#endif - } -} - -/*! - * brief Configure PINT pattern match. - - * This function configures a given pattern match bit slice. - * - * param base Base address of the PINT peripheral. - * param bslice Pattern match bit slice number. - * param cfg Pointer to bit slice configuration. - * - * retval None. - */ -void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) -{ - uint32_t src_shift; - uint32_t cfg_shift; - uint32_t pmcfg; - uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; - uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; - - assert(base != NULL); - - src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); - cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); - - /* Input source selection for selected bit slice */ - base->PMSRC = (base->PMSRC & ~(tmp_src_shift << src_shift)) | ((uint32_t)(cfg->bs_src) << src_shift); - - /* Bit slice configuration */ - pmcfg = base->PMCFG; - pmcfg = (pmcfg & ~(tmp_cfg_shift << cfg_shift)) | ((uint32_t)(cfg->bs_cfg) << cfg_shift); - - /* If end point is true, enable the bits */ - if ((uint32_t)bslice != 7UL) - { - if (cfg->end_point) - { - pmcfg |= (1UL << (uint32_t)bslice); - } - else - { - pmcfg &= ~(1UL << (uint32_t)bslice); - } - } - - base->PMCFG = pmcfg; - - /* Save callback pointer */ - if (base == PINT) - { - if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) - { - s_pintCallback[bslice] = cfg->callback; - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - { - s_secpintCallback[bslice] = cfg->callback; - } -#endif - } -} - -/*! - * brief Get PINT pattern match configuration. - - * This function returns the configuration of a given pattern match bit slice. - * - * param base Base address of the PINT peripheral. - * param bslice Pattern match bit slice number. - * param cfg Pointer to bit slice configuration. - * - * retval None. - */ -void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) -{ - uint32_t src_shift; - uint32_t cfg_shift; - uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; - uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; - - assert(base != NULL); - - src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); - cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); - - cfg->bs_src = (pint_pmatch_input_src_t)(uint32_t)((base->PMSRC & (tmp_src_shift << src_shift)) >> src_shift); - cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)(uint32_t)((base->PMCFG & (tmp_cfg_shift << cfg_shift)) >> cfg_shift); - - if ((uint32_t)bslice == 7U) - { - cfg->end_point = true; - } - else - { - cfg->end_point = (((base->PMCFG & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice) != 0U) ? true : false; - } - - if (base == PINT) - { - if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) - { - cfg->callback = s_pintCallback[bslice]; - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - { - cfg->callback = s_secpintCallback[bslice]; - } -#endif - } -} - -/*! - * brief Reset pattern match detection logic. - - * This function resets the pattern match detection logic if any of the product term is matching. - * - * param base Base address of the PINT peripheral. - * - * retval pmstatus Each bit position indicates the match status of corresponding bit slice. - * = 0 Match was detected. = 1 Match was not detected. - */ -uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base) -{ - uint32_t pmctrl; - uint32_t pmstatus; - uint32_t pmsrc; - - pmctrl = base->PMCTRL; - pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT; - if (pmstatus != 0UL) - { - /* Reset Pattern match engine detection logic */ - pmsrc = base->PMSRC; - base->PMSRC = pmsrc; - } - return (pmstatus); -} - -/*! - * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. - - * This function clears the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr) -{ - uint32_t pinIntMode = base->ISEL & (1UL << (uint32_t)pintr); - uint32_t pinIntStatus = base->IST & (1UL << (uint32_t)pintr); - - /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ - if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) - { - base->IST = (1UL << (uint32_t)pintr); - } -} - -/*! - * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. - - * This function clears the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_PinInterruptClrStatusAll(PINT_Type *base) -{ - uint32_t pinIntMode = 0; - uint32_t pinIntStatus = 0; - uint32_t pinIntCount = 0; - uint32_t mask = 0; - uint32_t i; - - if (base == PINT) - { - pinIntCount = (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - pinIntCount = (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - - for (i = 0; i < pinIntCount; i++) - { - pinIntMode = base->ISEL & (1UL << i); - pinIntStatus = base->IST & (1UL << i); - - /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ - if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) - { - mask |= 1UL << i; - } - } - - base->IST = mask; -} - -/*! - * brief Enable callback. - - * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * param base Base address of the PINT peripheral. - * - * retval None. - */ -void PINT_EnableCallback(PINT_Type *base) -{ - uint32_t i; - - assert(base != NULL); - - if (base == PINT) - { - for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i]); - (void)EnableIRQ(s_pintIRQ[i]); - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - (void)EnableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } -} - -/*! - * brief enable callback by pin index. - - * This function enables callback by pin index instead of enabling all pins. - * - * param base Base address of the peripheral. - * param pinIdx pin index. - * - * retval None. - */ -void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) -{ - assert(base != NULL); - - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); - -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - /* Get the right security pint irq index in array */ - if (base == SECPINT) - { - pintIdx = - (pint_pin_int_t)(uint32_t)((uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS); - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - - NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); - (void)EnableIRQ(s_pintIRQ[pintIdx]); -} - -/*! - * brief Disable callback. - - * This function disables the interrupt for the selected PINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * param base Base address of the peripheral. - * - * retval None. - */ -void PINT_DisableCallback(PINT_Type *base) -{ - uint32_t i; - - assert(base != NULL); - - if (base == PINT) - { - for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - (void)DisableIRQ(s_pintIRQ[i]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i]); - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - (void)DisableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } -} - -/*! - * brief disable callback by pin index. - - * This function disables callback by pin index instead of disabling all pins. - * - * param base Base address of the peripheral. - * param pinIdx pin index. - * - * retval None. - */ -void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) -{ - assert(base != NULL); - - if (base == PINT) - { - (void)DisableIRQ(s_pintIRQ[pintIdx]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); - NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - (void)DisableIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); - NVIC_ClearPendingIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); -#endif - } -} - -/*! - * brief Deinitialize PINT peripheral. - - * This function disables the PINT clock. - * - * param base Base address of the PINT peripheral. - * - * retval None. - */ -void PINT_Deinit(PINT_Type *base) -{ - uint32_t i; - - assert(base != NULL); - - /* Cleanup */ - PINT_DisableCallback(base); - if (base == PINT) - { - /* clear PINT callback array*/ - for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_pintCallback[i] = NULL; - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - /* clear SECPINT callback array */ - for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_secpintCallback[i] = NULL; - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - -#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_GpioInt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) - - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio_Sec); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - -#else - - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Pint); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } - else - { - /* if need config SECURE PINT device,then enable secure pint interrupt clock */ -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio_Sec_Int); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } -#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ -} -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -/* IRQ handler functions overloading weak symbols in the startup */ -void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void); -void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void) -{ - uint32_t pmstatus = 0; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); - /* Call user function */ - if (s_secpintCallback[kPINT_SecPinInt0] != NULL) - { - s_secpintCallback[kPINT_SecPinInt0](kPINT_SecPinInt0, pmstatus); - } - if ((SECPINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt0); - } - SDK_ISR_EXIT_BARRIER; -} - -#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) -/* IRQ handler functions overloading weak symbols in the startup */ -void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void); -void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); - /* Call user function */ - if (s_secpintCallback[kPINT_SecPinInt1] != NULL) - { - s_secpintCallback[kPINT_SecPinInt1](kPINT_SecPinInt1, pmstatus); - } - if ((SECPINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt1); - } - SDK_ISR_EXIT_BARRIER; -} -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - -/* IRQ handler functions overloading weak symbols in the startup */ -void PIN_INT0_DriverIRQHandler(void); -void PIN_INT0_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt0] != NULL) - { - s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus); - } - if ((PINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); - } - SDK_ISR_EXIT_BARRIER; -} - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) -void PIN_INT1_DriverIRQHandler(void); -void PIN_INT1_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt1] != NULL) - { - s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus); - } - if ((PINT->ISEL & 0x2U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) -void PIN_INT2_DriverIRQHandler(void); -void PIN_INT2_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt2] != NULL) - { - s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus); - } - if ((PINT->ISEL & 0x4U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) -void PIN_INT3_DriverIRQHandler(void); -void PIN_INT3_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt3] != NULL) - { - s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus); - } - if ((PINT->ISEL & 0x8U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) -void PIN_INT4_DriverIRQHandler(void); -void PIN_INT4_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt4] != NULL) - { - s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus); - } - if ((PINT->ISEL & 0x10U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT5_DAC1_IRQHandler(void) -#else -void PIN_INT5_DriverIRQHandler(void); -void PIN_INT5_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt5] != NULL) - { - s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus); - } - if ((PINT->ISEL & 0x20U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT6_USART3_IRQHandler(void) -#else -void PIN_INT6_DriverIRQHandler(void); -void PIN_INT6_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt6] != NULL) - { - s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus); - } - if ((PINT->ISEL & 0x40U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT7_USART4_IRQHandler(void) -#else -void PIN_INT7_DriverIRQHandler(void); -void PIN_INT7_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt7] != NULL) - { - s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus); - } - if ((PINT->ISEL & 0x80U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7); - } - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pint.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pint.h deleted file mode 100644 index d56458f3b15..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pint.h +++ /dev/null @@ -1,581 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_PINT_H_ -#define _FSL_PINT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup pint_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 1, 8)) /*!< Version 2.1.8 */ -/*@}*/ - -/* Number of interrupt line supported by PINT */ -#define PINT_PIN_INT_COUNT 8U - -/* Number of interrupt line supported by SECURE PINT */ -#define SEC_PINT_PIN_INT_COUNT 2U - -/* Number of input sources supported by PINT */ -#define PINT_INPUT_COUNT 8U - -/* PININT Bit slice source register bits */ -#define PININT_BITSLICE_SRC_START 8U -#define PININT_BITSLICE_SRC_MASK 7U - -/* PININT Bit slice configuration register bits */ -#define PININT_BITSLICE_CFG_START 8U -#define PININT_BITSLICE_CFG_MASK 7U -#define PININT_BITSLICE_ENDP_MASK 7U - -#define PINT_PIN_INT_LEVEL 0x10U -#define PINT_PIN_INT_EDGE 0x00U -#define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U -#define PINT_PIN_INT_RISE 0x01U -#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE) -#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) -#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) -#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL) -#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) - -/*! @brief PINT Pin Interrupt enable type */ -typedef enum _pint_pin_enable -{ - kPINT_PinIntEnableNone = 0U, /*!< Do not generate Pin Interrupt */ - kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE, /*!< Generate Pin Interrupt on rising edge */ - kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE, /*!< Generate Pin Interrupt on falling edge */ - kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */ - kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL, /*!< Generate Pin Interrupt on low level */ - kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */ -} pint_pin_enable_t; - -/*! @brief PINT Pin Interrupt type */ -typedef enum _pint_int -{ - kPINT_PinInt0 = 0U, /*!< Pin Interrupt 0 */ -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_PinInt1 = 1U, /*!< Pin Interrupt 1 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) - kPINT_PinInt2 = 2U, /*!< Pin Interrupt 2 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) - kPINT_PinInt3 = 3U, /*!< Pin Interrupt 3 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) - kPINT_PinInt4 = 4U, /*!< Pin Interrupt 4 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) - kPINT_PinInt5 = 5U, /*!< Pin Interrupt 5 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) - kPINT_PinInt6 = 6U, /*!< Pin Interrupt 6 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) - kPINT_PinInt7 = 7U, /*!< Pin Interrupt 7 */ -#endif -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) - kPINT_SecPinInt0 = 0U, /*!< Secure Pin Interrupt 0 */ -#endif -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_SecPinInt1 = 1U, /*!< Secure Pin Interrupt 1 */ -#endif -} pint_pin_int_t; - -/*! @brief PINT Pattern Match bit slice input source type */ -typedef enum _pint_pmatch_input_src -{ - kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */ - kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */ - kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */ - kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */ - kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */ - kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */ - kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */ - kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */ - kPINT_SecPatternMatchInp0Src = 0U, /*!< Input source 0 */ - kPINT_SecPatternMatchInp1Src = 1U, /*!< Input source 1 */ -} pint_pmatch_input_src_t; - -/*! @brief PINT Pattern Match bit slice type */ -typedef enum _pint_pmatch_bslice -{ - kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) - kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) - kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) - kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) - kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) - kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) - kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */ -#endif -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) - kPINT_SecPatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ -#endif -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_SecPatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ -#endif -} pint_pmatch_bslice_t; - -/*! @brief PINT Pattern Match configuration type */ -typedef enum _pint_pmatch_bslice_cfg -{ - kPINT_PatternMatchAlways = 0U, /*!< Always Contributes to product term match */ - kPINT_PatternMatchStickyRise = 1U, /*!< Sticky Rising edge */ - kPINT_PatternMatchStickyFall = 2U, /*!< Sticky Falling edge */ - kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */ - kPINT_PatternMatchHigh = 4U, /*!< High level */ - kPINT_PatternMatchLow = 5U, /*!< Low level */ - kPINT_PatternMatchNever = 6U, /*!< Never contributes to product term match */ - kPINT_PatternMatchBothEdges = 7U, /*!< Either rising or falling edge */ -} pint_pmatch_bslice_cfg_t; - -/*! @brief PINT Callback function. */ -typedef void (*pint_cb_t)(pint_pin_int_t pintr, uint32_t pmatch_status); - -typedef struct _pint_pmatch_cfg -{ - pint_pmatch_input_src_t bs_src; - pint_pmatch_bslice_cfg_t bs_cfg; - bool end_point; - pint_cb_t callback; -} pint_pmatch_cfg_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize PINT peripheral. - - * This function initializes the PINT peripheral and enables the clock. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_Init(PINT_Type *base); - -/*! - * @brief Configure PINT peripheral pin interrupt. - - * This function configures a given pin interrupt. - * - * @param base Base address of the PINT peripheral. - * @param intr Pin interrupt. - * @param enable Selects detection logic. - * @param callback Callback. - * - * @retval None. - */ -void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback); - -/*! - * @brief Get PINT peripheral pin interrupt configuration. - - * This function returns the configuration of a given pin interrupt. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * @param enable Pointer to store the detection logic. - * @param callback Callback. - * - * @retval None. - */ -void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback); - -/*! - * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. - - * This function clears the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr); - -/*! - * @brief Get Selected pin interrupt status. - - * This function returns the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval status = 0 No pin interrupt request. = 1 Selected Pin interrupt request active. - */ -static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->IST & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. - - * This function clears the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_PinInterruptClrStatusAll(PINT_Type *base); - -/*! - * @brief Get all pin interrupts status. - - * This function returns the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval status Each bit position indicates the status of corresponding pin interrupt. - * = 0 No pin interrupt request. = 1 Pin interrupt request active. - */ -static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base) -{ - return (base->IST); -} - -/*! - * @brief Clear Selected pin interrupt fall flag. - - * This function clears the selected pin interrupt fall flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - base->FALL = (1UL << (uint32_t)pintr); -} - -/*! - * @brief Get selected pin interrupt fall flag. - - * This function returns the selected pin interrupt fall flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval flag = 0 Falling edge has not been detected. = 1 Falling edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->FALL & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupt fall flags. - - * This function clears the fall flag for all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base) -{ - base->FALL = PINT_FALL_FDET_MASK; -} - -/*! - * @brief Get all pin interrupt fall flags. - - * This function returns the fall flag of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval flags Each bit position indicates the falling edge detection of the corresponding pin interrupt. - * 0 Falling edge has not been detected. = 1 Falling edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base) -{ - return (base->FALL); -} - -/*! - * @brief Clear Selected pin interrupt rise flag. - - * This function clears the selected pin interrupt rise flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - base->RISE = (1UL << (uint32_t)pintr); -} - -/*! - * @brief Get selected pin interrupt rise flag. - - * This function returns the selected pin interrupt rise flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval flag = 0 Rising edge has not been detected. = 1 Rising edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->RISE & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupt rise flags. - - * This function clears the rise flag for all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base) -{ - base->RISE = PINT_RISE_RDET_MASK; -} - -/*! - * @brief Get all pin interrupt rise flags. - - * This function returns the rise flag of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval flags Each bit position indicates the rising edge detection of the corresponding pin interrupt. - * 0 Rising edge has not been detected. = 1 Rising edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base) -{ - return (base->RISE); -} - -/*! - * @brief Configure PINT pattern match. - - * This function configures a given pattern match bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * @param cfg Pointer to bit slice configuration. - * - * @retval None. - */ -void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); - -/*! - * @brief Get PINT pattern match configuration. - - * This function returns the configuration of a given pattern match bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * @param cfg Pointer to bit slice configuration. - * - * @retval None. - */ -void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); - -/*! - * @brief Get pattern match bit slice status. - - * This function returns the status of selected bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * - * @retval status = 0 Match has not been detected. = 1 Match has been detected. - */ -static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_bslice_t bslice) -{ - return ((base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT) & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice; -} - -/*! - * @brief Get status of all pattern match bit slices. - - * This function returns the status of all bit slices. - * - * @param base Base address of the PINT peripheral. - * - * @retval status Each bit position indicates the match status of corresponding bit slice. - * = 0 Match has not been detected. = 1 Match has been detected. - */ -static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base) -{ - return base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT; -} - -/*! - * @brief Reset pattern match detection logic. - - * This function resets the pattern match detection logic if any of the product term is matching. - * - * @param base Base address of the PINT peripheral. - * - * @retval pmstatus Each bit position indicates the match status of corresponding bit slice. - * = 0 Match was detected. = 1 Match was not detected. - */ -uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base); - -/*! - * @brief Enable pattern match function. - - * This function enables the pattern match function. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchEnable(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) | PINT_PMCTRL_SEL_PMATCH_MASK; -} - -/*! - * @brief Disable pattern match function. - - * This function disables the pattern match function. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchDisable(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) & ~PINT_PMCTRL_SEL_PMATCH_MASK; -} - -/*! - * @brief Enable RXEV output. - - * This function enables the pattern match RXEV output. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) | PINT_PMCTRL_ENA_RXEV_MASK; -} - -/*! - * @brief Disable RXEV output. - - * This function disables the pattern match RXEV output. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) & ~PINT_PMCTRL_ENA_RXEV_MASK; -} - -/*! - * @brief Enable callback. - - * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_EnableCallback(PINT_Type *base); - -/*! - * @brief Disable callback. - - * This function disables the interrupt for the selected PINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * @param base Base address of the peripheral. - * - * @retval None. - */ -void PINT_DisableCallback(PINT_Type *base); - -/*! - * @brief Deinitialize PINT peripheral. - - * This function disables the PINT clock. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_Deinit(PINT_Type *base); - -/*! - * @brief enable callback by pin index. - - * This function enables callback by pin index instead of enabling all pins. - * - * @param base Base address of the peripheral. - * @param pintIdx pin index. - * - * @retval None. - */ -void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); - -/*! - * @brief disable callback by pin index. - - * This function disables callback by pin index instead of disabling all pins. - * - * @param base Base address of the peripheral. - * @param pintIdx pin index. - * - * @retval None. - */ -void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_PINT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_power.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_power.c deleted file mode 100644 index 4ae4f9b6874..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_power.c +++ /dev/null @@ -1,3107 +0,0 @@ -/* - * Copyright 2020, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include -#include "fsl_common.h" -#include "fsl_power.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.power" -#endif - -/* NOTE: These registers are handled by the SDK. The user should not modify the source code. Changes to the source code - * can cause application failure. NXP is not responsible for any change to the code and is not obligated to provide - * support. */ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/** - * @brief LDO_FLASH_NV & LDO_EFUSE_PROG voltage settings - */ -typedef enum _v_ldo_flashnv_ldo_efuse -{ - V_LDO_1P650 = 0, /*!< 1.65 V */ - V_LDO_1P700 = 1, /*!< 1.7 V */ - V_LDO_1P750 = 2, /*!< 1.75 V */ - V_LDO_1P800 = 3, /*!< 1.8 V */ - V_LDO_1P850 = 4, /*!< 1.85 V */ - V_LDO_1P900 = 5, /*!< 1.9 V */ - V_LDO_1P950 = 6, /*!< 1.95 V */ - V_LDO_2P000 = 7 /*!< 2.0 V */ -} v_ldo_flashnv_ldo_efuse_t; - -/** - * @brief Always On and Memories LDO voltage settings - */ -typedef enum _v_ao -{ - // V_AO_1P220 1.22 = 0, /*!< 1.22 V */ - V_AO_0P700 = 1, /*!< 0.7 V */ - V_AO_0P725 = 2, /*!< 0.725 V */ - V_AO_0P750 = 3, /*!< 0.75 V */ - V_AO_0P775 = 4, /*!< 0.775 V */ - V_AO_0P800 = 5, /*!< 0.8 V */ - V_AO_0P825 = 6, /*!< 0.825 V */ - V_AO_0P850 = 7, /*!< 0.85 V */ - V_AO_0P875 = 8, /*!< 0.875 V */ - V_AO_0P900 = 9, /*!< 0.9 V */ - V_AO_0P960 = 10, /*!< 0.96 V */ - V_AO_0P970 = 11, /*!< 0.97 V */ - V_AO_0P980 = 12, /*!< 0.98 V */ - V_AO_0P990 = 13, /*!< 0.99 V */ - V_AO_1P000 = 14, /*!< 1 V */ - V_AO_1P010 = 15, /*!< 1.01 V */ - V_AO_1P020 = 16, /*!< 1.02 V */ - V_AO_1P030 = 17, /*!< 1.03 V */ - V_AO_1P040 = 18, /*!< 1.04 V */ - V_AO_1P050 = 19, /*!< 1.05 V */ - V_AO_1P060 = 20, /*!< 1.06 V */ - V_AO_1P070 = 21, /*!< 1.07 V */ - V_AO_1P080 = 22, /*!< 1.08 V */ - V_AO_1P090 = 23, /*!< 1.09 V */ - V_AO_1P100 = 24, /*!< 1.1 V */ - V_AO_1P110 = 25, /*!< 1.11 V */ - V_AO_1P120 = 26, /*!< 1.12 V */ - V_AO_1P130 = 27, /*!< 1.13 V */ - V_AO_1P140 = 28, /*!< 1.14 V */ - V_AO_1P150 = 29, /*!< 1.15 V */ - V_AO_1P160 = 30, /*!< 1.16 V */ - V_AO_1P220 = 31 /*!< 1.22 V */ -} v_ao_t; - -/** - * @brief DCDC voltage settings - */ -typedef enum _v_dcdc -{ - V_DCDC_0P950 = 0, /*!< 0.95 V */ - V_DCDC_0P975 = 1, /*!< 0.975 V */ - V_DCDC_1P000 = 2, /*!< 1 V */ - V_DCDC_1P025 = 3, /*!< 1.025 V */ - V_DCDC_1P050 = 4, /*!< 1.050 V */ - V_DCDC_1P075 = 5, /*!< 1.075 V */ - V_DCDC_1P100 = 6, /*!< 1.1 V */ - V_DCDC_1P125 = 7, /*!< 1.125 V */ - V_DCDC_1P150 = 8, /*!< 1.150 V */ - V_DCDC_1P175 = 9, /*!< 1.175 V */ - V_DCDC_1P200 = 10 /*!< 1.2 V */ -} v_dcdc_t; - -/** - * @brief LDO_CORE High Power Mode voltage settings - */ -typedef enum _v_ldocore_hp -{ - V_LDOCORE_HP_1P373 = 0, /*!< 1.373 V */ - V_LDOCORE_HP_1P365 = 1, /*!< 1.365 V */ - V_LDOCORE_HP_1P359 = 2, /*!< 1.359 V */ - V_LDOCORE_HP_1P352 = 3, /*!< 1.352 V */ - V_LDOCORE_HP_1P345 = 4, /*!< 1.345 V */ - V_LDOCORE_HP_1P339 = 5, /*!< 1.339 V */ - V_LDOCORE_HP_1P332 = 6, /*!< 1.332 V */ - V_LDOCORE_HP_1P325 = 7, /*!< 1.325 V */ - V_LDOCORE_HP_1P318 = 8, /*!< 1.318 V */ - V_LDOCORE_HP_1P311 = 9, /*!< 1.311 V */ - V_LDOCORE_HP_1P305 = 10, /*!< 1.305 V */ - V_LDOCORE_HP_1P298 = 11, /*!< 1.298 V */ - V_LDOCORE_HP_1P291 = 12, /*!< 1.291 V */ - V_LDOCORE_HP_1P285 = 13, /*!< 1.285 V */ - V_LDOCORE_HP_1P278 = 14, /*!< 1.278 V */ - V_LDOCORE_HP_1P271 = 15, /*!< 1.271 V */ - V_LDOCORE_HP_1P264 = 16, /*!< 1.264 V */ - V_LDOCORE_HP_1P258 = 17, /*!< 1.258 V */ - V_LDOCORE_HP_1P251 = 18, /*!< 1.251 V */ - V_LDOCORE_HP_1P244 = 19, /*!< 1.244 V */ - V_LDOCORE_HP_1P237 = 20, /*!< 1.237 V */ - V_LDOCORE_HP_1P231 = 21, /*!< 1.231 V */ - V_LDOCORE_HP_1P224 = 22, /*!< 1.224 V */ - V_LDOCORE_HP_1P217 = 23, /*!< 1.217 V */ - V_LDOCORE_HP_1P210 = 24, /*!< 1.21 V */ - V_LDOCORE_HP_1P204 = 25, /*!< 1.204 V */ - V_LDOCORE_HP_1P197 = 26, /*!< 1.197 V */ - V_LDOCORE_HP_1P190 = 27, /*!< 1.19 V */ - V_LDOCORE_HP_1P183 = 28, /*!< 1.183 V */ - V_LDOCORE_HP_1P177 = 29, /*!< 1.177 V */ - V_LDOCORE_HP_1P169 = 30, /*!< 1.169 V */ - V_LDOCORE_HP_1P163 = 31, /*!< 1.163 V */ - V_LDOCORE_HP_1P156 = 32, /*!< 1.156 V */ - V_LDOCORE_HP_1P149 = 33, /*!< 1.149 V */ - V_LDOCORE_HP_1P143 = 34, /*!< 1.143 V */ - V_LDOCORE_HP_1P136 = 35, /*!< 1.136 V */ - V_LDOCORE_HP_1P129 = 36, /*!< 1.129 V */ - V_LDOCORE_HP_1P122 = 37, /*!< 1.122 V */ - V_LDOCORE_HP_1P116 = 38, /*!< 1.116 V */ - V_LDOCORE_HP_1P109 = 39, /*!< 1.109 V */ - V_LDOCORE_HP_1P102 = 40, /*!< 1.102 V */ - V_LDOCORE_HP_1P095 = 41, /*!< 1.095 V */ - V_LDOCORE_HP_1P088 = 42, /*!< 1.088 V */ - V_LDOCORE_HP_1P082 = 43, /*!< 1.082 V */ - V_LDOCORE_HP_1P075 = 44, /*!< 1.075 V */ - V_LDOCORE_HP_1P068 = 45, /*!< 1.068 V */ - V_LDOCORE_HP_1P062 = 46, /*!< 1.062 V */ - V_LDOCORE_HP_1P055 = 47, /*!< 1.055 V */ - V_LDOCORE_HP_1P048 = 48, /*!< 1.048 V */ - V_LDOCORE_HP_1P041 = 49, /*!< 1.041 V */ - V_LDOCORE_HP_1P034 = 50, /*!< 1.034 V */ - V_LDOCORE_HP_1P027 = 51, /*!< 1.027 V */ - V_LDOCORE_HP_1P021 = 52, /*!< 1.021 V */ - V_LDOCORE_HP_1P014 = 53, /*!< 1.014 V */ - V_LDOCORE_HP_1P007 = 54, /*!< 1.007 V */ - V_LDOCORE_HP_1P001 = 55, /*!< 1.001 V */ - V_LDOCORE_HP_0P993 = 56, /*!< 0.9937 V */ - V_LDOCORE_HP_0P987 = 57, /*!< 0.987 V */ - V_LDOCORE_HP_0P980 = 58, /*!< 0.9802 V */ - V_LDOCORE_HP_0P973 = 59, /*!< 0.9731 V */ - V_LDOCORE_HP_0P966 = 60, /*!< 0.9666 V */ - V_LDOCORE_HP_0P959 = 61, /*!< 0.9598 V */ - V_LDOCORE_HP_0P953 = 62, /*!< 0.9532 V */ - V_LDOCORE_HP_0P946 = 63, /*!< 0.946 V */ - V_LDOCORE_HP_0P939 = 64, /*!< 0.9398 V */ - V_LDOCORE_HP_0P932 = 65, /*!< 0.9327 V */ - V_LDOCORE_HP_0P926 = 66, /*!< 0.9262 V */ - V_LDOCORE_HP_0P919 = 67, /*!< 0.9199 V */ - V_LDOCORE_HP_0P913 = 68, /*!< 0.9135 V */ - V_LDOCORE_HP_0P907 = 69, /*!< 0.9071 V */ - V_LDOCORE_HP_0P901 = 70, /*!< 0.9012 V */ - V_LDOCORE_HP_0P895 = 71, /*!< 0.8953 V */ - V_LDOCORE_HP_0P889 = 72, /*!< 0.8895 V */ - V_LDOCORE_HP_0P883 = 73, /*!< 0.8837 V */ - V_LDOCORE_HP_0P877 = 74, /*!< 0.8779 V */ - V_LDOCORE_HP_0P871 = 75, /*!< 0.8719 V */ - V_LDOCORE_HP_0P865 = 76, /*!< 0.8658 V */ - V_LDOCORE_HP_0P859 = 77, /*!< 0.8596 V */ - V_LDOCORE_HP_0P853 = 78, /*!< 0.8537 V */ - V_LDOCORE_HP_0P847 = 79, /*!< 0.8474 V */ - V_LDOCORE_HP_0P841 = 80, /*!< 0.8413 V */ - V_LDOCORE_HP_0P835 = 81, /*!< 0.835 V */ - V_LDOCORE_HP_0P828 = 82, /*!< 0.8288 V */ - V_LDOCORE_HP_0P822 = 83, /*!< 0.8221 V */ - V_LDOCORE_HP_0P815 = 84, /*!< 0.8158 V */ - V_LDOCORE_HP_0P809 = 85, /*!< 0.8094 V */ - V_LDOCORE_HP_0P802 = 86, /*!< 0.8026 V */ - V_LDOCORE_HP_0P795 = 87, /*!< 0.7959 V */ - V_LDOCORE_HP_0P789 = 88, /*!< 0.7893 V */ - V_LDOCORE_HP_0P782 = 89, /*!< 0.7823 V */ - V_LDOCORE_HP_0P775 = 90, /*!< 0.7756 V */ - V_LDOCORE_HP_0P768 = 91, /*!< 0.7688 V */ - V_LDOCORE_HP_0P762 = 92, /*!< 0.7623 V */ - V_LDOCORE_HP_0P755 = 93, /*!< 0.7558 V */ - V_LDOCORE_HP_0P749 = 94, /*!< 0.749 V */ - V_LDOCORE_HP_0P742 = 95, /*!< 0.7421 V */ - V_LDOCORE_HP_0P735 = 96, /*!< 0.7354 V */ - V_LDOCORE_HP_0P728 = 97, /*!< 0.7284 V */ - V_LDOCORE_HP_0P722 = 98, /*!< 0.722 V */ - V_LDOCORE_HP_0P715 = 99 /*!< 0.715 V */ - // V_LDOCORE_HP_0P715 = 100, /*!< 0.7148 V */ - // V_LDOCORE_HP_0P715 = 101, /*!< 0.7148 V */ - // V_LDOCORE_HP_0P715 = 102, /*!< 0.7151 V */ - // V_LDOCORE_HP_0P715 = 103, /*!< 0.7147 V */ - // V_LDOCORE_HP_0P715 = 104, /*!< 0.7147 V */ - // V_LDOCORE_HP_0P715 = 105, /*!< 0.715 V */ - // V_LDOCORE_HP_0P715 = 106, /*!< 0.7147 V */ - // V_LDOCORE_HP_0P715 = 107, /*!< 0.715 V */ - // V_LDOCORE_HP_0P715 = 108, /*!< 0.7152 V */ - // V_LDOCORE_HP_0P715 = 109, /*!< 0.7148 V */ - // V_LDOCORE_HP_0P715 = 110, /*!< 0.715 V */ - // V_LDOCORE_HP_0P715 = 111, /*!< 0.7151 V */ - // V_LDOCORE_HP_0P715 = 112, /*!< 0.7153 V */ - // V_LDOCORE_HP_0P715 = 113, /*!< 0.7152 V */ - // V_LDOCORE_HP_0P715 = 114, /*!< 0.7149 V */ - // V_LDOCORE_HP_0P715 = 115, /*!< 0.7154 V */ - // V_LDOCORE_HP_0P715 = 116, /*!< 0.7152 V */ - // V_LDOCORE_HP_0P715 = 117, /*!< 0.7154 V */ - // V_LDOCORE_HP_0P715 = 118, /*!< 0.7147 V */ - // V_LDOCORE_HP_0P715 = 119, /*!< 0.7152 V */ - // V_LDOCORE_HP_0P715 = 120, /*!< 0.7149 V */ - // V_LDOCORE_HP_0P715 = 121, /*!< 0.7151 V */ - // V_LDOCORE_HP_0P715 = 122, /*!< 0.7152 V */ - // V_LDOCORE_HP_0P715 = 123, /*!< 0.7153 V */ - // V_LDOCORE_HP_0P715 = 124, /*!< 0.7149 V */ - // V_LDOCORE_HP_0P715 = 125, /*!< 0.7154 V */ - // V_LDOCORE_HP_0P715 = 126, /*!< 0.7153 V */ - // V_LDOCORE_HP_0P715 = 127, /*!< 0.7154 V */ -} v_ldocore_hp_t; - -/** - * @brief LDO_CORE Low Power Mode voltage settings - */ -typedef enum _v_ldocore_lp -{ - V_LDOCORE_LP_0P750 = 3, /*!< 0.75 V */ - V_LDOCORE_LP_0P800 = 2, /*!< 0.8 V */ - V_LDOCORE_LP_0P850 = 1, /*!< 0.85 V */ - V_LDOCORE_LP_0P900 = 0 /*!< 0.9 V */ -} v_ldocore_lp_t; - -/** - * @brief System Power Mode settings - */ -typedef enum _v_system_power_profile -{ - V_SYSTEM_POWER_PROFILE_LOW = 0UL, /*!< For system below or equal to 100 MHz */ - V_SYSTEM_POWER_PROFILE_MEDIUM = 1UL, /*!< For system frequencies in ]100 MHz - 150 MHz] */ - V_SYSTEM_POWER_PROFILE_HIGH = 2UL, /*!< For system above 150 MHz */ -} v_system_power_profile_t; - -/** - * @brief Manufacturing Process Corners - */ -typedef enum -{ - PROCESS_CORNER_SSS, /**< Slow Corner Process */ - PROCESS_CORNER_NNN, /**< Nominal Corner Process */ - PROCESS_CORNER_FFF, /**< Fast Corner Process */ - PROCESS_CORNER_OTHERS, /**< SFN, SNF, NFS, Poly Res ... Corner Process */ -} lowpower_process_corner_enum; - -/** @brief Low Power main structure */ -typedef struct -{ - __IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */ - __IO uint32_t PDCTRL[2]; /*!< Power Down control : controls power of various modules - in the different Low power modes, including ROM */ - __IO uint32_t SRAMRETCTRL; /*!< Power Down control : controls power SRAM instances - in the different Low power modes */ - __IO uint32_t CPURETCTRL; /*!< CPU0 retention control : controls CPU retention parameters in POWER DOWN modes */ - __IO uint64_t VOLTAGE; /*!< Voltage control in Low Power Modes */ - __IO uint32_t WAKEUPSRC[4]; /*!< Wake up sources control for sleepcon */ - __IO uint32_t WAKEUPINT[4]; /*!< Wake up sources control for ARM */ - __IO uint32_t HWWAKE; /*!< Interrupt that can postpone power down modes - in case an interrupt is pending when the processor request deepsleep */ - __IO uint32_t WAKEUPIOSRC; /*!< Wake up I/O sources in DEEP POWER-DOWN mode */ -} LPC_LOWPOWER_T; - -#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) -/** - * @brief NMPA related Registers - */ -#define FLASH_NMPA_BOD_LDOCORE (*((volatile unsigned int *)(0x3FC08))) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY0 (*((volatile unsigned int *)(0x3FC18))) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY1 (*((volatile unsigned int *)(0x3FC1C))) -#define FLASH_NMPA_LDO_AO (*((volatile unsigned int *)(0x3FC24))) -#define FLASH_NMPA_LDO_MEM (*((volatile unsigned int *)(0x3FD60))) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY0 (*((volatile unsigned int *)(0x3FCB0))) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY1 (*((volatile unsigned int *)(0x3FCB4))) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY0 (*((volatile unsigned int *)(0x3FCB8))) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY1 (*((volatile unsigned int *)(0x3FCBC))) -#define FLASH_NMPA_PVT_MONITOR_0_RINGO (*((volatile unsigned int *)(0x3FCE0))) -#define FLASH_NMPA_PVT_MONITOR_1_RINGO (*((volatile unsigned int *)(0x3FCF0))) - -/** - * @brief NMPA related masks - */ - -#define FLASH_NMPA_BOD_LDOCORE_REGREF_1P8V_OFFSET_SHIFT (24U) -#define FLASH_NMPA_BOD_LDOCORE_REGREF_1P8V_OFFSET_MASK (0xFF000000U) -#define FLASH_NMPA_LDO_AO_VADJ_ACTIVE_SHIFT (0U) -#define FLASH_NMPA_LDO_AO_VADJ_ACTIVE_MASK (0xFFU) -#endif - -/** - * @brief CSS related Registers - */ -#define CSSV2_STATUS_REG (*((volatile unsigned int *)(0x40030000))) -#define CSSV2_CTRL_REG (*((volatile unsigned int *)(0x40030004))) -#define SYSCON_CSS_CLK_CTRL_REG (*((volatile unsigned int *)(0x400009B0))) -#define SYSCON_CSS_CLK_CTRL_SET_REG (*((volatile unsigned int *)(0x400009B4))) -#define SYSCON_CSS_CLK_CTRL_CLR_REG (*((volatile unsigned int *)(0x400009B8))) - -/** - * @brief Wake-up I/O positions - */ -/*!< wake-up 0 */ -#define WAKEUPIO_0_PORT (1UL) -#define WAKEUPIO_0_PINS (1UL) -/*!< wake-up 1 */ -#define WAKEUPIO_1_PORT (0UL) -#define WAKEUPIO_1_PINS (28UL) -/*!< wake-up 2 */ -#define WAKEUPIO_2_PORT (1UL) -#define WAKEUPIO_2_PINS (18UL) -/*!< wake-up 3 */ -#define WAKEUPIO_3_PORT (1UL) -#define WAKEUPIO_3_PINS (30UL) -/*!< wake-up 4 */ -#define WAKEUPIO_4_PORT (0UL) -#define WAKEUPIO_4_PINS (26UL) - -/** - * @brief SRAM Low Power Modes - */ -#define LOWPOWER_SRAM_LPMODE_MASK (0xFUL) -#define LOWPOWER_SRAM_LPMODE_ACTIVE (0x6UL) /*!< SRAM functional mode */ -#define LOWPOWER_SRAM_LPMODE_SLEEP (0xFUL) /*!< SRAM Sleep mode (Data retention, fast wake up) */ -#define LOWPOWER_SRAM_LPMODE_DEEPSLEEP (0x8UL) /*!< SRAM Deep Sleep mode (Data retention, slow wake up) */ -#define LOWPOWER_SRAM_LPMODE_SHUTDOWN (0x9UL) /*!< SRAM Shut Down mode (no data retention) */ -#define LOWPOWER_SRAM_LPMODE_POWERUP (0xAUL) /*!< SRAM is powering up */ - -/** - * @brief SoC Low Power modes - */ -#define LOWPOWER_CFG_LPMODE_INDEX 0 -#define LOWPOWER_CFG_LPMODE_MASK (0x3UL << LOWPOWER_CFG_LPMODE_INDEX) -#define LOWPOWER_CFG_SELCLOCK_INDEX 2 -#define LOWPOWER_CFG_SELCLOCK_MASK (0x1UL << LOWPOWER_CFG_SELCLOCK_INDEX) -#define LOWPOWER_CFG_SELMEMSUPPLY_INDEX 3 -#define LOWPOWER_CFG_SELMEMSUPPLY_MASK (0x1UL << LOWPOWER_CFG_SELMEMSUPPLY_INDEX) -#define LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX 4 -#define LOWPOWER_CFG_MEMLOWPOWERMODE_MASK (0x1UL << LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX) -#define LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX 5 -#define LOWPOWER_CFG_LDODEEPSLEEPREF_MASK (0x1UL << LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX) - -#define LOWPOWER_CFG_LPMODE_ACTIVE 0 /*!< ACTIVE mode */ -#define LOWPOWER_CFG_LPMODE_DEEPSLEEP 1 /*!< DEEP-SLEEP mode */ -#define LOWPOWER_CFG_LPMODE_POWERDOWN 2 /*!< POWER-DOWN mode */ -#define LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN 3 /*!< DEEP POWER-DOWN mode */ -#define LOWPOWER_CFG_LPMODE_SLEEP 4 /*!< SLEEP mode */ - -#define LOWPOWER_CFG_SELCLOCK_1MHZ 0 /*!< The 1 MHz clock is used during the configuration of the PMC */ -#define LOWPOWER_CFG_SELCLOCK_12MHZ \ - 1 /*!< The 12 MHz clock is used during the configuration of the PMC (to speed up PMC configuration process)*/ - -#define LOWPOWER_CFG_SELMEMSUPPLY_LDOMEM 0 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_MEM */ -#define LOWPOWER_CFG_SELMEMSUPPLY_LDODEEPSLEEP \ - 1 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_DEEP_SLEEP (or DCDC) */ - -#define LOWPOWER_CFG_MEMLOWPOWERMODE_SOURCEBIASING \ - 0 /*!< All SRAM instances use "Source Biasing" as low power mode technic (it is recommended to set LDO_MEM as high \ - as possible -- 1.1V typical -- during low power mode) */ -#define LOWPOWER_CFG_MEMLOWPOWERMODE_VOLTAGESCALING \ - 1 /*!< All SRAM instances use "Voltage Scaling" as low power mode technic (it is recommended to set LDO_MEM as low \ - as possible -- down to 0.7V -- during low power mode) */ - -/** - * @brief LDO Voltage control in Low Power Modes - */ -#define LOWPOWER_VOLTAGE_LDO_PMU_INDEX 0 -#define LOWPOWER_VOLTAGE_LDO_PMU_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) -#define LOWPOWER_VOLTAGE_LDO_MEM_INDEX 5 -#define LOWPOWER_VOLTAGE_LDO_MEM_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) -#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX 10 -#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) -#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX 15 -#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) - -/* CPU Retention Control*/ -#define LOWPOWER_CPURETCTRL_ENA_INDEX 0 -#define LOWPOWER_CPURETCTRL_ENA_MASK (0x1UL << LOWPOWER_CPURETCTRL_ENA_INDEX) -#define LOWPOWER_CPURETCTRL_MEMBASE_INDEX 1 -#define LOWPOWER_CPURETCTRL_MEMBASE_MASK (0x1FFF << LOWPOWER_CPURETCTRL_MEMBASE_INDEX) -#define LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX 14 -#define LOWPOWER_CPURETCTRL_RETDATALENGTH_MASK (0x3FFUL << LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX) - -/** - * @brief SRAM Power Control Registers Code - */ -// LSDEL DSBDEL DSB LS -#define SRAM_PWR_MODE_ACT_CODE (0x6UL) // Active | 0 1 1 0 -#define SRAM_PWR_MODE_LS_CODE (0xFUL) // Light Sleep | 1 1 1 1 -#define SRAM_PWR_MODE_DS_CODE (0x8UL) // Deep Sleep | 1 0 0 0 -#define SRAM_PWR_MODE_SD_CODE (0x9UL) // Shut Down | 1 0 0 1 -#define SRAM_PWR_MODE_MPU_CODE (0xEUL) // Matrix Power Up | 1 1 1 0 -#define SRAM_PWR_MODE_FPU_CODE (0xAUL) // Full Power Up | 1 0 1 0 - -/** - * @brief System voltage setting - */ -// All 3 DCDC_POWER_PROFILE_* constants below have been updated after chip characterization on ATE -#define DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ \ - (100000000UL) /* Maximum System Frequency allowed with DCDC Power Profile LOW */ -#define DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ \ - (135000000UL) /* Maximum System Frequency allowed with DCDC Power Profile MEDIUM */ -#define DCDC_POWER_PROFILE_HIGH_MAX_FREQ_HZ \ - (150000000UL) /* Maximum System Frequency allowed with DCDC Power Profile HIGH */ - -/** - * @brief Manufacturing Process Parameters - */ -// All 3 PROCESS_* constants below have been updated after chip characterization on ATE -#define PROCESS_NNN_AVG_HZ (14900000UL) /* Average Ring Oscillator value for Nominal (NNN) Manufacturing Process */ -#define PROCESS_NNN_STD_HZ \ - (515000UL) /* Standard Deviation Ring Oscillator value for Nominal (NNN) Manufacturing Process */ -#define PROCESS_NNN_LIMITS \ - (2UL) /* Nominal (NNN) Manufacturing Process Ring Oscillator values limit (with respect to the Average value) */ - -#define PROCESS_NNN_MIN_HZ \ - (PROCESS_NNN_AVG_HZ - \ - (PROCESS_NNN_LIMITS * \ - PROCESS_NNN_STD_HZ)) /* Minimum Ring Oscillator value for Nominal (NNN) Manufacturing Process */ - -#define PROCESS_NNN_MAX_HZ \ - (PROCESS_NNN_AVG_HZ + \ - (PROCESS_NNN_LIMITS * \ - PROCESS_NNN_STD_HZ)) /* Maximum Ring OScillator value for Nominal (NNN) Manufacturing Process */ - -// All 9 VOLTAGE_* constants below have been updated after chip characterization on ATE -#define VOLTAGE_SSS_LOW_MV (1075UL) /* Voltage Settings for : Process=SSS, DCDC Power Profile=LOW */ -#define VOLTAGE_SSS_MED_MV (1175UL) /* Voltage Settings for : Process=SSS, DCDC Power Profile=MEDIUM */ -#define VOLTAGE_SSS_HIG_MV (1200UL) /* Voltage Settings for : Process=SSS, DCDC Power Profile=HIGH */ - -#define VOLTAGE_NNN_LOW_MV (1025UL) /* Voltage Settings for : Process=NNN, DCDC Power Profile=LOW */ -#define VOLTAGE_NNN_MED_MV (1100UL) /* Voltage Settings for : Process=NNN, DCDC Power Profile=MEDIUM */ -#define VOLTAGE_NNN_HIG_MV (1150UL) /* Voltage Settings for : Process=NNN, DCDC Power Profile=HIGH */ - -#define VOLTAGE_FFF_LOW_MV (1025UL) /* Voltage Settings for : Process=FFF, DCDC Power Profile=LOW */ -#define VOLTAGE_FFF_MED_MV (1100UL) /* Voltage Settings for : Process=FFF, DCDC Power Profile=MEDIUM */ -#define VOLTAGE_FFF_HIG_MV (1150UL) /* Voltage Settings for : Process=FFF, DCDC Power Profile=HIGH */ - -/******************************************************************************* - * Codes - ******************************************************************************/ - -/******************************************************************************* - * LOCAL FUNCTIONS PROTOTYPES - ******************************************************************************/ -static void POWER_WaitLDOCoreInit(void); -static void POWER_SRAMPowerUpDelay(void); -static void POWER_PowerCycleCpu(void); -static void POWER_SetLowPowerMode(LPC_LOWPOWER_T *p_lowpower_cfg); -static uint32_t POWER_WakeUpIOCtrl(uint32_t p_wakeup_io_ctrl); -static uint32_t POWER_SetLdoAoLdoMemVoltage(uint32_t p_lp_mode); -static void POWER_SetSystemPowerProfile(v_system_power_profile_t power_profile); -static void POWER_SetVoltageForProcess(v_system_power_profile_t power_profile); -static lowpower_process_corner_enum POWER_GetPartProcessCorner(void); -static void POWER_SetSystemVoltage(uint32_t system_voltage_mv); -static void POWER_SetSystemClock12MHZ(void); -static void POWER_SRAMSetRegister(power_sram_index_t sram_index, uint32_t power_mode); -static void POWER_SRAMActiveToLightSleep(power_sram_index_t sram_index); -static void POWER_SRAMActiveToDeepSleep(power_sram_index_t sram_index); -static void POWER_SRAMActiveToShutDown(power_sram_index_t sram_index); -static void POWER_SRAMLightSleepToActive(power_sram_index_t sram_index); -static void POWER_SRAMDeepSleepToActive(power_sram_index_t sram_index); -static void POWER_SRAMShutDownToActive(power_sram_index_t sram_index); - -/** - * brief SoC Power Management Controller initialization - * return power_status_t - */ -power_status_t POWER_PowerInit(void) -{ - // To speed up PMC configuration, change PMC clock from 1 MHz to 12 MHz. - // Set Power Mode to "ACTIVE" (required specially when waking up from DEEP POWER-DOWN) - PMC->CTRL = (PMC->CTRL | PMC_CTRL_SELCLOCK_MASK) & (~PMC_CTRL_LPMODE_MASK); - - // Check that no time out occured during the hardware wake-up process - if (PMC->TIMEOUTEVENTS != 0) - { - // A least 1 time-out error occured. - return kPOWER_Status_Fail; - } - - // Set up wake-up IO pad control source : IOCON ((WAKEUPIO_ENABLE = 0) - PMC->WAKEUPIOCTRL &= ~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK; - - // Set LDO_FLASHNV output voltage - PMC->LDOFLASHNV = (PMC->LDOFLASHNV & (~PMC_LDOFLASHNV_VADJ_MASK)) | PMC_LDOFLASHNV_VADJ(V_LDO_1P850); - - // Set LDO_EFUSE_PROG output voltage - PMC->LDOEFUSEPROG = (PMC->LDOEFUSEPROG & (~PMC_LDOEFUSEPROG_VADJ_MASK)) | PMC_LDOEFUSEPROG_VADJ(V_LDO_1P850); - - // Configure the voltage level of LDO CORE Low Power mode (TODO :: :: Temporarily set to 0.9V; target is 0.8 V)*/ - PMC->LDOCORE0 = (PMC->LDOCORE0 & (~PMC_LDOCORE0_LPREGREFSEL_MASK)) | PMC_LDOCORE0_LPREGREFSEL(V_LDOCORE_LP_0P900); - - // SRAM uses Voltage Scaling in all Low Power modes - PMC->SRAMCTRL = (PMC->SRAMCTRL & (~PMC_SRAMCTRL_SMB_MASK)) | PMC_SRAMCTRL_SMB(3); - - // Enable Analog References fast wake-up in case of wake-up from all low power modes and Hardware Pin reset - PMC->REFFASTWKUP = PMC->REFFASTWKUP | PMC_REFFASTWKUP_LPWKUP_MASK | PMC_REFFASTWKUP_HWWKUP_MASK; - - // Enable FRO192MHz shut-off glitch suppression. - // TODO :: :: Check the Power Consumption Impact of this setting during DEEP-SLEEP and POWER-DOWN. - // (Supposed to be 1 to 2uA in typical conditions). If the impe - // - ANACTRL->OSC_TESTBUS = 0x1; - - return kPOWER_Status_Success; -} - -/** - * brief - * return power_status_t - */ -power_status_t POWER_SetCorePowerSource(power_core_pwr_source_t pwr_source) -{ - uint32_t pmc_reg_data; - - switch (pwr_source) - { - case kPOWER_CoreSrcDCDC: - { - // Enable DCDC (1st step) - PMC->CMD = PMC_CMD_DCDCENABLE_MASK; - - // Wait until DCDC is enabled - while ((PMC->STATUSPWR & PMC_STATUSPWR_DCDCPWROK_MASK) == 0) - ; - - // Disable LDO Core Low Power Mode (2nd step) - PMC->CMD = PMC_CMD_LDOCORELOWPWRDISABLE_MASK; - - // Disable LDO Core High Power Mode (3rd step) - PMC->CMD = PMC_CMD_LDOCOREHIGHPWRDISABLE_MASK; - - // Check PMC Finite State Machines status - pmc_reg_data = PMC->STATUS & (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREHPENABLE_MASK | - PMC_STATUS_FSMLDOCORELPENABLE_MASK | PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK); - if (pmc_reg_data != (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK)) - { - // Error : only DCDC and LDO CORE Exponential Timer must both be enabled. - return (kPOWER_Status_Fail); - } - } - break; - - case kPOWER_CoreSrcLDOCoreHP: - { - // Enable LDO Core High Power Mode (1st step) - PMC->CMD = PMC_CMD_LDOCOREHIGHPWRENABLE_MASK; - - // Note: Once LDO_CORE High Power Mode has been enabled, - // at least 2us are required before one can reliabily sample - // the LDO Low Voltage Detectore Output. - POWER_WaitLDOCoreInit(); - - // Wait until LDO CORE High Power is enabled - while ((PMC->STATUSPWR & PMC_STATUSPWR_LDOCOREPWROK_MASK) == 0) - ; - - // Disable DCDC (2nd step) - PMC->CMD = PMC_CMD_DCDCDISABLE_MASK; - - // Disable LDO Core Low Power Mode (3rd step) - PMC->CMD = PMC_CMD_LDOCORELOWPWRDISABLE_MASK; - - // Check PMC Finite State Machines status - pmc_reg_data = PMC->STATUS & (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREHPENABLE_MASK | - PMC_STATUS_FSMLDOCORELPENABLE_MASK | PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK); - if (pmc_reg_data != PMC_STATUS_FSMLDOCOREHPENABLE_MASK) - { - // Error : only LDO CORE High Power mode must both be enabled. - return (kPOWER_Status_Fail); - } - } - break; - - case kPOWER_CoreSrcLDOCoreLP: - { - // Enable LDO Core Low Power Mode (1st step) - PMC->CMD = PMC_CMD_LDOCORELOWPWRENABLE_MASK; - - // Disable LDO Core High Power Mode (2nd step) - PMC->CMD = PMC_CMD_LDOCOREHIGHPWRDISABLE_MASK; - - // Disable DCDC (3rd step) - PMC->CMD = PMC_CMD_DCDCDISABLE_MASK; - - // Check PMC Finite State Machines status - pmc_reg_data = PMC->STATUS & (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREHPENABLE_MASK | - PMC_STATUS_FSMLDOCORELPENABLE_MASK | PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK); - if (pmc_reg_data != (PMC_STATUS_FSMLDOCORELPENABLE_MASK | PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK)) - { - // Error : only LDO CORE Low Power mode and LDO CORE Exponential Timer must both be enabled. - return (kPOWER_Status_Fail); - } - } - break; - - case kPOWER_CoreSrcExternal: - { - // Disable LDO Core Low Power Mode (1st step) - PMC->CMD = PMC_CMD_LDOCORELOWPWRDISABLE_MASK; - - // Disable LDO Core High Power Mode (2nd step) - PMC->CMD = PMC_CMD_LDOCOREHIGHPWRDISABLE_MASK; - - // Disable DCDC (3rd step) - PMC->CMD = PMC_CMD_DCDCDISABLE_MASK; - - // Check PMC Finite State Machines status - pmc_reg_data = PMC->STATUS & (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREHPENABLE_MASK | - PMC_STATUS_FSMLDOCORELPENABLE_MASK | PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK); - if (pmc_reg_data != 0) - { - // Error : All power sources must be disabled. - return (kPOWER_Status_Fail); - } - } - break; - - default: // Not supported - return (kPOWER_Status_Fail); - - } // End switch (pwr_source) - - return (kPOWER_Status_Success); -} - -/** - * brief - * @param : - * return power_core_pwr_source_t - */ -power_core_pwr_source_t POWER_GetCorePowerSource(void) -{ - uint32_t reg_status, reg_statuspwr; - - reg_status = PMC->STATUS; - reg_statuspwr = PMC->STATUSPWR; - - if ((reg_statuspwr & PMC_STATUSPWR_DCDCPWROK_MASK) && (reg_status & PMC_STATUS_FSMDCDCENABLE_MASK)) - { - /* DCDC */ - return (kPOWER_CoreSrcDCDC); - } - else - { - if ((reg_statuspwr & PMC_STATUSPWR_LDOCOREPWROK_MASK) && (reg_status & PMC_STATUS_FSMLDOCOREHPENABLE_MASK)) - { - /* LDO_CORE High Power Mode */ - return (kPOWER_CoreSrcLDOCoreHP); - } - else - { - if (reg_status & PMC_STATUS_FSMLDOCORELPENABLE_MASK) - { - /* LDO_CORE Low Power Mode */ - return (kPOWER_CoreSrcLDOCoreLP); - } - else - { - /* External */ - return (kPOWER_CoreSrcExternal); - } - } - } -} - -/** - * brief - * return nothing - */ -power_status_t POWER_CorePowerSourceControl(power_core_pwr_source_t pwr_source, power_core_pwr_state_t pwr_state) -{ - switch (pwr_source) - { - case kPOWER_CoreSrcDCDC: - { - if (pwr_state == kPOWER_CorePwrEnable) - { - // Enable DCDC - PMC->CMD = PMC_CMD_DCDCENABLE_MASK; - - // Wait until DCDC is enabled - while ((PMC->STATUSPWR & PMC_STATUSPWR_DCDCPWROK_MASK) == 0) - ; - - // Check PMC Finite State Machines status - if ((PMC->STATUS & PMC_STATUS_FSMDCDCENABLE_MASK) == 0) - { - // Error : DCDC not enabled. - return (kPOWER_Status_Fail); - } - } - else - { - // Disable DCDC - PMC->CMD = PMC_CMD_DCDCDISABLE_MASK; - - // Check PMC Finite State Machines status - if ((PMC->STATUS & PMC_STATUS_FSMDCDCENABLE_MASK) != 0) - { - // Error : DCDC is enabled. - return (kPOWER_Status_Fail); - } - } - } - break; - - case kPOWER_CoreSrcLDOCoreHP: - { - if (pwr_state == kPOWER_CorePwrEnable) - { - // Enable LDO Core High Power Mode - PMC->CMD = PMC_CMD_LDOCOREHIGHPWRENABLE_MASK; - - // Note: Once LDO_CORE High Power Mode has been enabled, - // at least 2us are required before one can reliabily sample - // the LDO Low Voltage Detector Output. - POWER_WaitLDOCoreInit(); - - // Wait until LDO CORE High Power is enabled - while ((PMC->STATUSPWR & PMC_STATUSPWR_LDOCOREPWROK_MASK) == 0) - ; - - // Check PMC Finite State Machines status - if ((PMC->STATUS & PMC_STATUS_FSMLDOCOREHPENABLE_MASK) == 0) - { - // Error : LDO CORE High Power mode is not enabled. - return (kPOWER_Status_Fail); - } - } - else - { - // Disable LDO Core High Power Mode - PMC->CMD = PMC_CMD_LDOCOREHIGHPWRDISABLE_MASK; - - // Check PMC Finite State Machines status - if ((PMC->STATUS & PMC_STATUS_FSMLDOCOREHPENABLE_MASK) != 0) - { - // Error : LDO CORE High Power mode is enabled. - return (kPOWER_Status_Fail); - } - } - } - break; - - case kPOWER_CoreSrcLDOCoreLP: - { - if (pwr_state == kPOWER_CorePwrEnable) - { - // Enable LDO Core Low Power Mode (1st step) - PMC->CMD = PMC_CMD_LDOCORELOWPWRENABLE_MASK; - - // Check PMC Finite State Machines status - if ((PMC->STATUS & (PMC_STATUS_FSMLDOCORELPENABLE_MASK | PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK)) != - (PMC_STATUS_FSMLDOCORELPENABLE_MASK | PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK)) - { - // Error : LDO CORE Low Power mode is not enabled. - return (kPOWER_Status_Fail); - } - } - else - { - // Disable LDO Core Low Power Mode - PMC->CMD = PMC_CMD_LDOCORELOWPWRDISABLE_MASK; - - // Check PMC Finite State Machines status - if ((PMC->STATUS & (PMC_STATUS_FSMLDOCORELPENABLE_MASK | PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK)) != 0) - { - // Error : LDO CORE Low Power mode is enabled. - return (kPOWER_Status_Fail); - } - } - } - break; - - default: // Not supported - return (kPOWER_Status_Fail); - - } // End switch (pwr_source) - - return (kPOWER_Status_Success); -} - -/** - * brief - * return - */ -power_sram_pwr_mode_t POWER_GetSRAMPowerMode(power_sram_index_t sram_index) -{ - power_sram_pwr_mode_t pwr_mode; - uint32_t state; - uint32_t sram_ctrl_0 = PMC->SRAMCTRL0; - uint32_t sram_ctrl_1 = PMC->SRAMCTRL1; - - switch (sram_index) - { - case kPOWER_SRAM_IDX_RAM_X0: - { - state = (sram_ctrl_0 >> PMC_SRAMCTRL0_RAM_X0_LS_SHIFT) & 0xF; - break; - } - - case kPOWER_SRAM_IDX_RAM_00: - { - state = (sram_ctrl_0 >> PMC_SRAMCTRL0_RAM_00_LS_SHIFT) & 0xF; - break; - } - - case kPOWER_SRAM_IDX_RAM_01: - { - state = (sram_ctrl_0 >> PMC_SRAMCTRL0_RAM_01_LS_SHIFT) & 0xF; - break; - } - - case kPOWER_SRAM_IDX_RAM_02: - { - state = (sram_ctrl_0 >> PMC_SRAMCTRL0_RAM_02_LS_SHIFT) & 0xF; - break; - } - - case kPOWER_SRAM_IDX_RAM_03: - { - state = (sram_ctrl_0 >> PMC_SRAMCTRL0_RAM_03_LS_SHIFT) & 0xF; - break; - } - - case kPOWER_SRAM_IDX_RAM_10: - { - state = (sram_ctrl_0 >> PMC_SRAMCTRL0_RAM_10_LS_SHIFT) & 0xF; - break; - } - - case kPOWER_SRAM_IDX_RAM_20: - { - state = (sram_ctrl_0 >> PMC_SRAMCTRL0_RAM_20_LS_SHIFT) & 0xF; - break; - } - - case kPOWER_SRAM_IDX_RAM_30: - { - state = (sram_ctrl_0 >> PMC_SRAMCTRL0_RAM_30_LS_SHIFT) & 0xF; - break; - } - - case kPOWER_SRAM_IDX_RAM_40: - { - state = (sram_ctrl_1 >> PMC_SRAMCTRL1_RAM_40_LS_SHIFT) & 0xF; - break; - } - - case kPOWER_SRAM_IDX_RAM_41: - { - state = (sram_ctrl_1 >> PMC_SRAMCTRL1_RAM_41_LS_SHIFT) & 0xF; - break; - } - - case kPOWER_SRAM_IDX_RAM_42: - { - state = (sram_ctrl_1 >> PMC_SRAMCTRL1_RAM_42_LS_SHIFT) & 0xF; - break; - } - - case kPOWER_SRAM_IDX_RAM_43: - { - state = (sram_ctrl_1 >> PMC_SRAMCTRL1_RAM_43_LS_SHIFT) & 0xF; - break; - } - - default: - // Error - state = 0x6; // Active. - } - - switch (state) - { - case 0x6: - pwr_mode = kPOWER_SRAMPwrActive; - break; - - case 0xF: - pwr_mode = kPOWER_SRAMPwrLightSleep; - break; - - case 0x8: - pwr_mode = kPOWER_SRAMPwrDeepSleep; - break; - - case 0x9: - pwr_mode = kPOWER_SRAMPwrShutDown; - break; - - default: - pwr_mode = kPOWER_SRAMPwrActive; - } - - return (pwr_mode); -} - -/** - * brief - * return - */ -power_status_t POWER_SRAMPowerModeControl(power_sram_bit_t sram_inst, power_sram_pwr_mode_t pwr_mode) -{ - power_sram_pwr_mode_t current_pwr_mode; - power_sram_index_t sram_index = kPOWER_SRAM_IDX_RAM_X0; - - sram_inst = (power_sram_bit_t)((uint32_t)sram_inst & 0x3FFF); /* Only SRAM from RAM_X0 to RAM_F3 */ - while ((uint32_t)sram_inst != 0) - { - // There is a least 1 SRAM instance to be processed - if ((uint32_t)sram_inst & 0x1) - { - // Get current SRAM state - current_pwr_mode = POWER_GetSRAMPowerMode(sram_index); - - // The SRAM instance Power state must be updated - switch (current_pwr_mode) - { - case kPOWER_SRAMPwrActive: - { // Active - switch (pwr_mode) - { - case kPOWER_SRAMPwrActive: - { // Active ---> Active : there is nothing to do. - break; - } - - case kPOWER_SRAMPwrLightSleep: - { // Active ---> Light Sleep - POWER_SRAMActiveToLightSleep(sram_index); - break; - } - - case kPOWER_SRAMPwrDeepSleep: - { // Active ---> Deep Sleep - POWER_SRAMActiveToDeepSleep(sram_index); - break; - } - - case kPOWER_SRAMPwrShutDown: - { // Active ---> Shut Down - POWER_SRAMActiveToShutDown(sram_index); - break; - } - - default: - // Do nothing. - ; - } // switch( pwr_mode ) - - break; - } - - case kPOWER_SRAMPwrLightSleep: - { // Light Sleep - switch (pwr_mode) - { - case kPOWER_SRAMPwrActive: - { // Light Sleep ---> Active - POWER_SRAMLightSleepToActive(sram_index); - break; - } - - case kPOWER_SRAMPwrLightSleep: - { // Light Sleep ---> Light Sleep : there is nothing to do. - break; - } - - default: - // Light Sleep ---> Shut Down : FORBIDDEN (error) - // Light Sleep ---> Deep Sleep : FORBIDDEN (error) - return (kPOWER_Status_Fail); - } // switch( pwr_mode ) - - break; - } - - case kPOWER_SRAMPwrDeepSleep: - { // Deep Sleep - switch (pwr_mode) - { - case kPOWER_SRAMPwrActive: - { // Deep Sleep ---> Active - POWER_SRAMDeepSleepToActive(sram_index); - break; - } - - case kPOWER_SRAMPwrDeepSleep: - { // Deep Sleep ---> Deep Sleep : there is nothing to do. - break; - } - - default: - // Deep Sleep ---> Shut Down : FORBIDDEN (error) - // Deep Sleep ---> Light Sleep : FORBIDDEN (error) - return (kPOWER_Status_Fail); - } // switch( pwr_mode ) - - break; - } - - case kPOWER_SRAMPwrShutDown: - { // Shutdown - switch (pwr_mode) - { - case kPOWER_SRAMPwrActive: - { // Shutdown ---> Active - POWER_SRAMShutDownToActive(sram_index); - break; - } - - case kPOWER_SRAMPwrShutDown: - { // Shutdown ---> Shut Down : there is nothing to do. - break; - } - - default: - // Shutdown ---> Deep Sleep : FORBIDDEN (error) - // Shutdown ---> Light Sleep : FORBIDDEN (error) - return (kPOWER_Status_Fail); - } // switch( pwr_mode ) - - break; - } - - default: - // Do nothing - ; - } // switch( current_pwr_mode ) - } // if ( (uint32_t)sram_inst & 0x1 ) - - // Move to next SRAM index - sram_inst = (power_sram_bit_t)((uint32_t)sram_inst >> 1); - sram_index = (power_sram_index_t)((uint32_t)sram_index + 1); - } // while ((uint32_t)sram_inst != 0 ) - - return (kPOWER_Status_Success); -} - -/** - * @brief Configures and enters in SLEEP low power mode - * @return Nothing - */ -void POWER_EnterSleep(void) -{ - uint32_t pmsk; - pmsk = __get_PRIMASK(); /* Save CORTEX-M33 interrupt configuration */ - __disable_irq(); /* Disable all interrupts */ - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; /* CORTEX-M33 uses "Sleep" mode */ - __WFI(); /* CORTEX-M33 enters "Sleep" mode */ - __set_PRIMASK(pmsk); /* Restore CORTEX-M33 interrupt configuration (after wake up) */ -} - -/** - * brief PMC Deep Sleep function call - * return nothing - */ -void POWER_EnterDeepSleep(uint32_t exclude_from_pd[2], - uint32_t sram_retention_ctrl, - uint32_t wakeup_interrupts[4], - uint32_t hardware_wake_ctrl) -{ - LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ - uint32_t pmc_reset_ctrl; - - /* Clear Low Power Mode configuration variable */ - memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); - - /* Configure Low Power Mode configuration variable */ - lv_low_power_mode_cfg.CFG = LOWPOWER_CFG_LPMODE_DEEPSLEEP << LOWPOWER_CFG_LPMODE_INDEX; /* DEEPSLEEP mode */ - - /* Make sure LDO MEM & Analog references will stay powered, Shut down ROM & LDO Flash NV */ - lv_low_power_mode_cfg.PDCTRL[0] = - (~exclude_from_pd[0] & ~kPDRUNCFG_PD_LDOMEM & ~kPDRUNCFG_PD_BIAS) | kPDRUNCFG_PD_ROM | kPDRUNCFG_PD_LDOFLASHNV; - lv_low_power_mode_cfg.PDCTRL[1] = ~exclude_from_pd[1]; - - // Voltage control in DeepSleep Low Power Modes - lv_low_power_mode_cfg.VOLTAGE = POWER_SetLdoAoLdoMemVoltage(LOWPOWER_CFG_LPMODE_DEEPSLEEP); - - // SRAM retention control during DEEP-SLEEP - lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl & kPOWER_SRAM_DSLP_MASK; - - /* Interrupts that allow DMA transfers with Flexcomm without waking up the Processor */ - if (hardware_wake_ctrl & (LOWPOWER_HWWAKE_PERIPHERALS | LOWPOWER_HWWAKE_DMIC | LOWPOWER_HWWAKE_SDMA0 | - LOWPOWER_HWWAKE_SDMA1 | LOWPOWER_HWWAKE_DAC)) - { - lv_low_power_mode_cfg.HWWAKE = (hardware_wake_ctrl & ~LOWPOWER_HWWAKE_FORCED) | LOWPOWER_HWWAKE_ENABLE_FRO192M; - } - - // @NOTE Niobe4mini: update with new BOD reset enable management - pmc_reset_ctrl = PMC->RESETCTRL; - if ((pmc_reset_ctrl & (PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK | PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK)) == - ((0x1 << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT) | (0x1 << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT))) - { - /* BoD CORE reset is activated, so make sure BoD Core and Biasing won't be shutdown */ - lv_low_power_mode_cfg.PDCTRL[0] &= ~kPDRUNCFG_PD_BODCORE & ~kPDRUNCFG_PD_BIAS; - } - - if ((pmc_reset_ctrl & - (PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_MASK | PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_DP_MASK)) == - ((0x1 << PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_SHIFT) | - (0x1 << PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_DP_SHIFT))) - { - /* BoD VDDMAIN reset is activated, so make sure BoD VDDMAIN and Biasing won't be shutdown */ - lv_low_power_mode_cfg.PDCTRL[0] &= ~kPDRUNCFG_PD_BODVDDMAIN & ~kPDRUNCFG_PD_BIAS; - } - - /* CPU Wake up & Interrupt sources control */ - lv_low_power_mode_cfg.WAKEUPSRC[0] = lv_low_power_mode_cfg.WAKEUPINT[0] = wakeup_interrupts[0]; - lv_low_power_mode_cfg.WAKEUPSRC[1] = lv_low_power_mode_cfg.WAKEUPINT[1] = wakeup_interrupts[1]; - lv_low_power_mode_cfg.WAKEUPSRC[2] = lv_low_power_mode_cfg.WAKEUPINT[2] = wakeup_interrupts[2]; - lv_low_power_mode_cfg.WAKEUPSRC[3] = lv_low_power_mode_cfg.WAKEUPINT[3] = wakeup_interrupts[3]; - - /* Enter low power mode */ - POWER_SetLowPowerMode(&lv_low_power_mode_cfg); -} - -/** - * brief PMC power Down function call - * return nothing - */ -void POWER_EnterPowerDown(uint32_t exclude_from_pd[1], - uint32_t sram_retention_ctrl, - uint32_t wakeup_interrupts[4], - uint32_t cpu_retention_addr) -{ - LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ - - // Clear Low Power Mode configuration variable - memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); - - // Configure Low Power Mode configuration variable : POWER DOWN mode - lv_low_power_mode_cfg.CFG = LOWPOWER_CFG_LPMODE_POWERDOWN << LOWPOWER_CFG_LPMODE_INDEX; - - // Only FRO32K, XTAL32K, FRO1M, COMP, BIAS and VREF can stay powered during POWERDOWN. - // LDO_MEM is enabled (because at least 1 SRAM instance will be required - for CPU state retention -) - lv_low_power_mode_cfg.PDCTRL[0] = ~(exclude_from_pd[0] | kPDRUNCFG_PD_LDOMEM); - lv_low_power_mode_cfg.PDCTRL[1] = 0xFFFFFFFF; - - // Force Bias activation if Analog Comparator is required, otherwise, disable it. - if ((lv_low_power_mode_cfg.PDCTRL[0] & kPDRUNCFG_PD_COMP) == 0) - { - // Analog Comparator is required du ring power-down: Enable Biasing - lv_low_power_mode_cfg.PDCTRL[0] = lv_low_power_mode_cfg.PDCTRL[0] & (~kPDRUNCFG_PD_BIAS); - } - else - { - // Analog Comparator is not required du ring power-down: Disable Biasing - lv_low_power_mode_cfg.PDCTRL[0] = lv_low_power_mode_cfg.PDCTRL[0] | kPDRUNCFG_PD_BIAS; - } - -// SRAM retention control during POWER-DOWN - -// Depending on where the user wants to locate the CPU state retention data, -// the associated SRAM instance will be automatically put in retention mode. -// The boundaries are defined in such a way that the area where the CPU state -// will be retained does not cross any SRAM instance boundary. -// Per hardware design, 1540 bytes are necessary to store the whole CPU state -#define RAM_00_CPU_RET_ADDR_MIN 0x20000000UL // RAM_00 start address -#define RAM_00_CPU_RET_ADDR_MAX 0x200009FCUL // RAM_00 start address + 1540 - 1 -#define RAM_01_CPU_RET_ADDR_MIN 0x20001000UL // RAM_01 start address -#define RAM_01_CPU_RET_ADDR_MAX 0x200019FCUL // RAM_01 start address + 1540 - 1 -#define RAM_02_CPU_RET_ADDR_MIN 0x20002000UL // RAM_02 start address -#define RAM_02_CPU_RET_ADDR_MAX 0x200029FCUL // RAM_02 start address + 1540 - 1 -#define RAM_03_CPU_RET_ADDR_MIN 0x20003000UL // RAM_03 start address -#define RAM_03_CPU_RET_ADDR_MAX 0x200039FCUL // RAM_03 start address + 1540 - 1 - - if ((cpu_retention_addr >= RAM_00_CPU_RET_ADDR_MIN) && (cpu_retention_addr <= RAM_00_CPU_RET_ADDR_MAX)) - { - // Inside RAM_00 - sram_retention_ctrl |= kPOWER_SRAM_RAM_00; - } - else - { - if ((cpu_retention_addr >= RAM_01_CPU_RET_ADDR_MIN) && (cpu_retention_addr <= RAM_01_CPU_RET_ADDR_MAX)) - { - // Inside RAM_01 - sram_retention_ctrl |= kPOWER_SRAM_RAM_01; - } - else - { - if ((cpu_retention_addr >= RAM_02_CPU_RET_ADDR_MIN) && (cpu_retention_addr <= RAM_02_CPU_RET_ADDR_MAX)) - { - // Inside RAM_02 - sram_retention_ctrl |= kPOWER_SRAM_RAM_02; - } - else - { - if ((cpu_retention_addr >= RAM_03_CPU_RET_ADDR_MIN) && (cpu_retention_addr <= RAM_03_CPU_RET_ADDR_MAX)) - { - // Inside RAM_03 - sram_retention_ctrl |= kPOWER_SRAM_RAM_03; - } - else - { - // Error! Therefore, we locate the retention area in RAM_00 - cpu_retention_addr = 0x20000000UL; - sram_retention_ctrl |= kPOWER_SRAM_RAM_00; - } - } - } - } - - lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl & kPOWER_SRAM_PDWN_MASK; - - // Voltage control in Low Power Modes - // The Memories Voltage settings below are for voltage scaling - lv_low_power_mode_cfg.VOLTAGE = POWER_SetLdoAoLdoMemVoltage(LOWPOWER_CFG_LPMODE_POWERDOWN); - - /* CPU0 retention Address */ - lv_low_power_mode_cfg.CPURETCTRL = ((cpu_retention_addr >> 1) | LOWPOWER_CPURETCTRL_ENA_MASK) & - (LOWPOWER_CPURETCTRL_MEMBASE_MASK | LOWPOWER_CPURETCTRL_ENA_MASK); - - /* CPU Wake up & Interrupt sources control */ - lv_low_power_mode_cfg.WAKEUPSRC[0] = lv_low_power_mode_cfg.WAKEUPINT[0] = - wakeup_interrupts[0] & (WAKEUP_GPIO_GLOBALINT0 | WAKEUP_GPIO_GLOBALINT1 | WAKEUP_FLEXCOMM3 | WAKEUP_ACMP | - WAKEUP_RTC_ALARM_WAKEUP | WAKEUP_WAKEUP_MAILBOX); - lv_low_power_mode_cfg.WAKEUPSRC[1] = lv_low_power_mode_cfg.WAKEUPINT[1] = - wakeup_interrupts[1] & WAKEUP_OS_EVENT_TIMER; - lv_low_power_mode_cfg.WAKEUPSRC[2] = lv_low_power_mode_cfg.WAKEUPINT[2] = 0UL; - lv_low_power_mode_cfg.WAKEUPSRC[3] = lv_low_power_mode_cfg.WAKEUPINT[3] = wakeup_interrupts[3] & WAKEUP_ITRC; - - /* Enter low power mode */ - POWER_SetLowPowerMode(&lv_low_power_mode_cfg); -} - -/** - * brief PMC Deep Power-Down function call - * return nothing - */ -void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd[1], - uint32_t sram_retention_ctrl, - uint32_t wakeup_interrupts[2], - uint32_t wakeup_io_ctrl) -{ - LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ - - // Clear Low Power Mode configuration variable - memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); - - // Configure Low Power Mode configuration variable : DEEP POWER-DOWN mode - lv_low_power_mode_cfg.CFG = LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN << LOWPOWER_CFG_LPMODE_INDEX; - - // Note: only FRO32K, XTAL32K, FRO1M and LDO_MEM can stay powered during DEEP POWER-DOWN - lv_low_power_mode_cfg.PDCTRL[0] = ~exclude_from_pd[0]; - lv_low_power_mode_cfg.PDCTRL[1] = 0xFFFFFFFF; - - // SRAM retention control during DEEP POWER-DOWN - // RAM_X0, RAM_02 and RAM_03 excluded: they are used by ROM Boot code - sram_retention_ctrl = sram_retention_ctrl & kPOWER_SRAM_DPWD_MASK; - lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; - - // Sanity check: if retention is required for any SRAM instance other than RAM_00, make sure LDO MEM will stay - // powered */ - if ((sram_retention_ctrl & (~kPOWER_SRAM_RAM_00)) != 0) - { - // SRAM retention is required : enable LDO_MEM - lv_low_power_mode_cfg.PDCTRL[0] &= ~kPDRUNCFG_PD_LDOMEM; - } - else - { - // No SRAM retention required : disable LDO_MEM - lv_low_power_mode_cfg.PDCTRL[0] |= kPDRUNCFG_PD_LDOMEM; - } - - // Voltage control in Low Power Modes - // The Memories Voltage settings below are for voltage scaling - lv_low_power_mode_cfg.VOLTAGE = POWER_SetLdoAoLdoMemVoltage(LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN); - - // Wake up sources control - lv_low_power_mode_cfg.WAKEUPSRC[0] = lv_low_power_mode_cfg.WAKEUPINT[0] = - wakeup_interrupts[0] & - WAKEUP_RTC_ALARM_WAKEUP; /* CPU Wake up sources control : only WAKEUP_RTC_LITE_ALARM_WAKEUP */ - lv_low_power_mode_cfg.WAKEUPSRC[1] = lv_low_power_mode_cfg.WAKEUPINT[1] = - wakeup_interrupts[1] & WAKEUP_OS_EVENT_TIMER; /* CPU Wake up sources control : only WAKEUP_OS_EVENT_TIMER */ - lv_low_power_mode_cfg.WAKEUPSRC[2] = lv_low_power_mode_cfg.WAKEUPINT[2] = 0UL; - lv_low_power_mode_cfg.WAKEUPSRC[3] = lv_low_power_mode_cfg.WAKEUPINT[3] = 0UL; - - /* Wake up I/O sources */ - lv_low_power_mode_cfg.WAKEUPIOSRC = POWER_WakeUpIOCtrl(wakeup_io_ctrl); - - /* Enter low power mode */ - POWER_SetLowPowerMode(&lv_low_power_mode_cfg); - - /*** We'll reach this point ONLY and ONLY if the DEEPPOWERDOWN has not been taken (for instance because an RTC or - * OSTIMER interrupt is pending) ***/ -} - -/** - * @brief Configures the 5 wake-up pins to wake up the part in DEEP-SLEEP and POWER-DOWN low power modes. - * @param wakeup_io_cfg_src : for all wake-up pins : indicates if the config is from IOCON or from PMC. - * @param wakeup_io_ctrl: the 5 wake-up pins configurations (see "LOWPOWER_WAKEUPIOSRC_*" #defines) - - * @return Nothing - * - * !!! IMPORTANT NOTES : - * 1 - To be called just before POWER_EnterDeepSleep() or POWER_EnterPowerDown(). - */ -/** - * brief PMC Deep Power-Down function call - * return nothing - */ -void POWER_SetWakeUpPins(uint32_t wakeup_io_cfg_src, uint32_t wakeup_io_ctrl) -{ - if (wakeup_io_cfg_src == LOWPOWER_WAKEUPIO_CFG_SRC_IOCON) - { - /* All wake-up pins controls are coming from IOCON */ - - wakeup_io_ctrl = wakeup_io_ctrl | LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK | - LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK | LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK | - LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK | - LOWPOWER_WAKEUPIO_PIO4_DISABLEPULLUPDOWN_MASK; /* Make sure IOCON is not modified inside - POWER_WakeUpIOCtrl */ - - PMC->WAKEUPIOCTRL = POWER_WakeUpIOCtrl(wakeup_io_ctrl) & (~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK); - } - else - { - /* All wake-up pins controls are coming from PMC */ - PMC->WAKEUPIOCTRL = POWER_WakeUpIOCtrl(wakeup_io_ctrl) | PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK; - } - - /* Release Wake up I/O reset (WAKEUPIO_RSTN = 1)*/ - PMC->WAKEUPIOCTRL |= PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_MASK; -} - -void POWER_GetWakeUpCause(power_reset_cause_t *reset_cause, - power_boot_mode_t *boot_mode, - power_wakeup_pin_t *wakeup_pin_cause) -{ - uint32_t reset_cause_reg; - uint32_t boot_mode_reg; - uint32_t wakeupio_cause_reg; - - boot_mode_reg = (PMC->STATUS & PMC_STATUS_BOOTMODE_MASK) >> PMC_STATUS_BOOTMODE_SHIFT; - - switch (boot_mode_reg) - { - case 1: - /* DEEP-SLEEP */ - *boot_mode = kBOOT_MODE_LP_DEEP_SLEEP; - break; - case 2: - /* POWER-DOWN */ - *boot_mode = kBOOT_MODE_LP_POWER_DOWN; - break; - case 3: - /* DEEP-POWER-DOWN */ - *boot_mode = kBOOT_MODE_LP_DEEP_POWER_DOWN; - break; - default: - /* All non Low Power Mode wake-up */ - *boot_mode = kBOOT_MODE_POWER_UP; - } - - wakeupio_cause_reg = PMC->WAKEIOCAUSE; - - if (boot_mode_reg == 0) - { - /* POWER-UP: Power On Reset, Pin reset, Brown Out Detectors, Software Reset: - * PMC has been reset, so wake up pin event not expected to have happened. */ - *wakeup_pin_cause = kWAKEUP_PIN_NONE; - } - else - { - switch (((wakeupio_cause_reg & PMC_WAKEIOCAUSE_WAKEUPIO_EVENTS_ORDER_MASK) >> - PMC_WAKEIOCAUSE_WAKEUPIO_EVENTS_ORDER_SHIFT)) - { - case 0x0: - *wakeup_pin_cause = kWAKEUP_PIN_NONE; - break; - case 0x1: - *wakeup_pin_cause = kWAKEUP_PIN_0; - break; - case 0x2: - *wakeup_pin_cause = kWAKEUP_PIN_1; - break; - case 0x4: - *wakeup_pin_cause = kWAKEUP_PIN_2; - break; - case 0x8: - *wakeup_pin_cause = kWAKEUP_PIN_3; - break; - case 0x10: - *wakeup_pin_cause = kWAKEUP_PIN_4; - break; - default: - /* Mutiple */ - *wakeup_pin_cause = kWAKEUP_PIN_MULTIPLE; - break; - } - } - - reset_cause_reg = PMC->AOREG1; - - /* - * Prioritize interrupts source with respect to how critical they are. - */ - if (reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK) - { /* Code Watchdog Reset */ - *reset_cause = kRESET_CAUSE_CDOGRESET; - } - else - { - if (reset_cause_reg & PMC_AOREG1_WDTRESET_MASK) - { /* Watchdog Timer Reset */ - *reset_cause = kRESET_CAUSE_WDTRESET; - } - else - { - if (reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK) - { /* ARM System Reset */ - *reset_cause = kRESET_CAUSE_ARMSYSTEMRESET; - } - else - { - if (boot_mode_reg != 3) /* POWER-UP: Power On Reset, Pin reset, Brown Out Detectors, Software Reset, - DEEP-SLEEP and POWER-DOWN */ - { - /* - * Prioritise Reset causes, starting from the strongest (Power On Reset) - */ - if (reset_cause_reg & PMC_AOREG1_POR_MASK) - { /* Power On Reset */ - *reset_cause = kRESET_CAUSE_POR; - } - else - { - if (reset_cause_reg & PMC_AOREG1_BODRESET_MASK) - { /* Brown-out Detector reset (either BODVBAT or BODCORE) */ - *reset_cause = kRESET_CAUSE_BODRESET; - } - else - { - if (reset_cause_reg & PMC_AOREG1_PADRESET_MASK) - { /* Hardware Pin Reset */ - *reset_cause = kRESET_CAUSE_PADRESET; - } - else - { - if (reset_cause_reg & PMC_AOREG1_SWRRESET_MASK) - { /* Software triggered Reset */ - *reset_cause = kRESET_CAUSE_SWRRESET; - } - else - { /* Unknown Reset Cause (shall never occur) */ - *reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC; - } - } - } - } - } - else /* boot_mode_reg == 3 : DEEP-POWER-DOWN */ - { - switch (((reset_cause_reg & PMC_AOREG1_DPD_EVENTS_ORDER_MASK) >> PMC_AOREG1_DPD_EVENTS_ORDER_SHIFT)) - { - case 1: - *reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO; - break; - case 2: - *reset_cause = kRESET_CAUSE_DPDRESET_RTC; - break; - case 3: - *reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC; - break; - case 4: - *reset_cause = kRESET_CAUSE_DPDRESET_OSTIMER; - break; - case 5: - *reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER; - break; - case 6: - *reset_cause = kRESET_CAUSE_DPDRESET_RTC_OSTIMER; - break; - case 7: - *reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER; - break; - default: - /* Unknown Reset Cause (shall not occur) */ - *reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC; - break; - } - } // if ( boot_mode != 3 ) - - } // if ( reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK ) - - } // if ( reset_cause_reg & PMC_AOREG1_WDTRESET_MASK ) - - } // if ( reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK ) -} - -/** - * @brief Described in fsl_common.h - * @param - * @return - */ -void POWER_SetVoltageForFreq(uint32_t system_freq_hz) -{ - if (system_freq_hz <= DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ) - { - /* [0 Hz - DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz] */ - POWER_SetSystemPowerProfile(V_SYSTEM_POWER_PROFILE_LOW); - POWER_SetVoltageForProcess(V_SYSTEM_POWER_PROFILE_LOW); - } - else - { - if (system_freq_hz <= DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ) - { - /* ]DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz - DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz] */ - POWER_SetSystemPowerProfile(V_SYSTEM_POWER_PROFILE_MEDIUM); - POWER_SetVoltageForProcess(V_SYSTEM_POWER_PROFILE_MEDIUM); - } - else - { - /* > DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz */ - POWER_SetSystemPowerProfile(V_SYSTEM_POWER_PROFILE_HIGH); - POWER_SetVoltageForProcess(V_SYSTEM_POWER_PROFILE_HIGH); - } - } -} - -/** - * @brief Wait at least 2us. - * @param None - * @return Nothing - */ - -static void POWER_WaitLDOCoreInit(void) -{ - /* - * Note: Once LDO_CORE High Power Mode has been enabled, - * at least 2us are required before one can reliabily sample - * the LDO Low Voltage Detectore Output. - * The PMC clock being 12 MHz, with at least 5 dummy read - * operations, it is guaranteed by design that, whatever the - * System/CPU clock frequency (up to 200 MHz). - */ - - volatile uint32_t reg_data; - for (uint32_t i = 0; i < 5; i++) - reg_data = PMC->STATUSPWR; /* Dummy Read */ - (void)reg_data; -} - -/** - * @brief Wait at least 2us. - * @param None - * @return Nothing - */ - -static void POWER_SRAMPowerUpDelay(void) -{ - /* - * Note: Wait about 1 us - * The PMC clock being 12 MHz, with at least 3 dummy read - * operations, it is guaranteed by design that when this , - * function is called, at least 1 us will elapse, - * whatever the System/CPU clock frequency (up to 200 MHz). - */ - - volatile uint32_t reg_data; - for (uint32_t i = 0; i < 3; i++) - reg_data = PMC->STATUSPWR; /* Dummy Read */ - (void)reg_data; -} - -/** - * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event - * @param None - * @return Nothing - */ - -static void POWER_PowerCycleCpu(void) -{ - /* Switch System Clock to FRO12Mhz (the configuration before calling this function will not be restored back) */ - POWER_SetSystemClock12MHZ(); - - /* Configure the Cortex-M33 in Deep Sleep mode */ - SCB->SCR = SCB->SCR | SCB_SCR_SLEEPDEEP_Msk; - - /* Enter in low power mode */ - __WFI(); - - /* Configure the Cortex-M33 in Active mode */ - SCB->SCR = SCB->SCR & (~SCB_SCR_SLEEPDEEP_Msk); -}; - -/** - * @brief Configures and enters in low power mode - * @param : p_lowpower_cfg - * @return Nothing - */ -static void POWER_SetLowPowerMode(LPC_LOWPOWER_T *p_lowpower_cfg) -{ - uint32_t i, primask, reg_data; - uint32_t cpu0_nmi_enable; - uint32_t cpu0_int_enable[4]; - uint32_t analog_ctrl_regs[7]; /* To store Analog Controller Registers */ - uint32_t vref_regs[4]; /* To store VREF Registers */ - uint32_t fmccr_reg; /* FMC Configuration Register */ - - /* Save FMC configuration */ - fmccr_reg = SYSCON->FMCCR; - - cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ - SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ - - // Save the configuration of the CPU interrupt enable Registers (because they are overwritten in - // POWER_SetLowPowerMode) - for (i = 0; i < 4; i++) - { - cpu0_int_enable[i] = NVIC->ISER[i]; - } - - uint32_t low_power_mode = (p_lowpower_cfg->CFG & LOWPOWER_CFG_LPMODE_MASK) >> LOWPOWER_CFG_LPMODE_INDEX; - - /* Set the Low power mode.*/ - PMC->CTRL = (PMC->CTRL & (~PMC_CTRL_LPMODE_MASK)) | PMC_CTRL_LPMODE(low_power_mode); - - /* SRAM in Retention modes */ - PMC->SRAMRETCTRL = p_lowpower_cfg->SRAMRETCTRL; - - /* Configure the voltage level of the Always On domain, Memories LDO */ - PMC->LDOPMU = (PMC->LDOPMU & (~PMC_LDOPMU_VADJ_PWD_MASK) & (~PMC_LDOPMU_VADJ_BOOST_PWD_MASK)) | - PMC_LDOPMU_VADJ_PWD((p_lowpower_cfg->VOLTAGE & LOWPOWER_VOLTAGE_LDO_PMU_MASK) >> - LOWPOWER_VOLTAGE_LDO_PMU_INDEX) | - PMC_LDOPMU_VADJ_BOOST_PWD((p_lowpower_cfg->VOLTAGE & LOWPOWER_VOLTAGE_LDO_PMU_BOOST_MASK) >> - LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX); - - PMC->LDOMEM = (PMC->LDOMEM & (~PMC_LDOMEM_VADJ_PWD_MASK) & (~PMC_LDOMEM_VADJ_BOOST_PWD_MASK)) | - PMC_LDOMEM_VADJ_PWD((p_lowpower_cfg->VOLTAGE & LOWPOWER_VOLTAGE_LDO_MEM_MASK) >> - LOWPOWER_VOLTAGE_LDO_MEM_INDEX) | - PMC_LDOMEM_VADJ_BOOST_PWD((p_lowpower_cfg->VOLTAGE & LOWPOWER_VOLTAGE_LDO_MEM_BOOST_MASK) >> - LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX); - - /* - * Enable wake up interrupt. - * Rational : we enable each interrupt (NVIC->ISER) that can wake up the CPU here (before the __disable_irq() - * below): Hence, if an interrupt was pending and not treated before (for any reason), the CPU will jump to that - * interrupt handler before trying to enter the low power mode. - * VERY IMPORTANT : Also, any interrupt set in NVIC->ISER, even though __disable_irq(), will make the CPU - * go out of the Deep Sleep mode. - */ - for (i = 0; i < 4; i++) - { - NVIC->ISER[i] = p_lowpower_cfg->WAKEUPINT[i]; /* Enable wake-up interrupt */ - SYSCON->STARTER[i] = p_lowpower_cfg->WAKEUPSRC[i]; /* Enable wake-up sources */ - } - - /* Save the configuration of the Priority Mask Register */ - primask = __get_PRIMASK(); - - switch (low_power_mode) - { - case LOWPOWER_CFG_LPMODE_DEEPSLEEP: - { - /* DEEP SLEEP power mode */ - - uint32_t bod_core_trglvl; /* BoD Core trigger level */ - uint32_t css_ctrl, syscon_css_clk_ctrl, syscon_css_clk_pclk_hclk; - uint32_t syscon_autoclkgateoverride_reg; /* AUTOCLKGATEOVERRIDE Configuration Register */ - - /* Analog Modules to be shut off */ - PMC->PDSLEEPCFG0 = p_lowpower_cfg->PDCTRL[0]; - PMC->PDSLEEPCFG1 = p_lowpower_cfg->PDCTRL[1]; - - /* Saving AUTOCLKGATEOVERRIDE register*/ - syscon_autoclkgateoverride_reg = SYSCON->AUTOCLKGATEOVERRIDE; - - /* DMA transactions with Flexcomm during DEEP SLEEP */ - SYSCON->HARDWARESLEEP = p_lowpower_cfg->HWWAKE; - /* Enable autoclockgating on SDMA0 and SDMA1 during DeepSleep*/ - SYSCON->AUTOCLKGATEOVERRIDE = - 0xC0DE0000 | (syscon_autoclkgateoverride_reg & - (~(SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK | SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK))); - - /* Make sure DEEP POWER DOWN reset is disabled */ - PMC->RESETCTRL = PMC->RESETCTRL & (~PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK); - - /* Adjust BoD Core Trip point . Currently set to 700 mV. TODO :: :: Check this value. */ - reg_data = PMC->BODCORE; - bod_core_trglvl = (reg_data & PMC_BODCORE_TRIGLVL_MASK) >> PMC_BODCORE_TRIGLVL_SHIFT; - PMC->BODCORE = (reg_data & (~PMC_BODCORE_TRIGLVL_MASK)) | PMC_BODCORE_TRIGLVL(kPOWER_BodCoreLevel700mv); - - // CSSV2 - { - syscon_css_clk_ctrl = SYSCON_CSS_CLK_CTRL_REG & (1U << 1); - - css_ctrl = 0U; - -#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) - syscon_css_clk_pclk_hclk = SYSCON->AHBCLKCTRL2 & (1U << 18); - /* Check if CSS is NOT in reset AND is clocked and enable, to avoid deadlock situations or a hardfault - */ - if (((SYSCON->PRESETCTRL2 & 0x40000U) == 0) && syscon_css_clk_pclk_hclk && (CSSV2_CTRL_REG & 0x1)) -#else - syscon_css_clk_pclk_hclk = SYSCON->AHBCLKCTRL[2] & (1U << 18); - /* Check if CSS is NOT in reset AND is clocked and enable, to avoid deadlock situations or a hardfault - */ - if (((SYSCON->PRESETCTRL[2] & 0x40000U) == 0) && syscon_css_clk_pclk_hclk && (CSSV2_CTRL_REG & 0x1)) -#endif - { - css_ctrl = CSSV2_CTRL_REG; - - /* Wait until CSS is in idle state (CSS_STATUS_BUSY_MASK) */ - while (CSSV2_STATUS_REG & 0x1) - ; - - /* Disable CSS */ - CSSV2_CTRL_REG = CSSV2_CTRL_REG & 0xFFFFFFFE; - - /* Swicth off i_css_clk/pclk/hclk */ - SYSCON->AHBCLKCTRLCLR[2] = (1U << 18); - } - - /* Switch off DTRNG clocks */ - SYSCON_CSS_CLK_CTRL_CLR_REG = (1U << 1); - } - - /* Disable all IRQs */ - __disable_irq(); - - /* - * - Switch PMC clock to 1 MHz, - * - Set LDO_MEM as SRAM supply source during DEEP-SLEEP, - * - Set LDO_CORE Low Power mode as Core supply source during DEEP-SLEEP, - * - Select Core Logic supply source when waking up from DEEP-SLEEP. - */ - reg_data = PMC->CTRL & (~PMC_CTRL_SELCLOCK_MASK) & (~PMC_CTRL_DEEPSLEEPCORESUPPLY_MASK) & - (~PMC_CTRL_SELMEMSUPPLY_MASK); - if (POWER_GetCorePowerSource() == kPOWER_CoreSrcDCDC) - { - /* Core Logic is supplied by DCDC Converter when waking up from DEEP-SLEEP */ - PMC->CTRL = reg_data & (~PMC_CTRL_SELCORESUPPLYWK_MASK); - } - else - { - /* Core Logic is supplied by LDO CORE (configured in High Power mode) when waking up from DEEP-SLEEP */ - PMC->CTRL = reg_data | PMC_CTRL_SELCORESUPPLYWK_MASK; - } - - /* _WFI() */ - POWER_PowerCycleCpu(); - - /* Switch PMC clock to 12 MHz and Configure the PMC in ACTIVE mode */ - PMC->CTRL = (PMC->CTRL & (~PMC_CTRL_LPMODE_MASK)) | PMC_CTRL_SELCLOCK_MASK | - PMC_CTRL_LPMODE(LOWPOWER_CFG_LPMODE_ACTIVE); - - /* Restore BoD Core Trip point. */ - PMC->BODCORE = (PMC->BODCORE & (~PMC_BODCORE_TRIGLVL_MASK)) | PMC_BODCORE_TRIGLVL(bod_core_trglvl); - - // CSSV2 - { - /* Restore i_css_clk/pclk/hclk */ - SYSCON->AHBCLKCTRLSET[2] = syscon_css_clk_pclk_hclk; - - /* Restore DTRNG clocks */ - SYSCON_CSS_CLK_CTRL_SET_REG = syscon_css_clk_ctrl; - -/* Check if CSS is NOT in reset AND is clocked, to avoid deadlock situations */ -#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) - if (((SYSCON->PRESETCTRL2 & 0x40000U) == 0) && syscon_css_clk_pclk_hclk && (css_ctrl & 0x1)) -#else - if (((SYSCON->PRESETCTRL[2] & 0x40000U) == 0) && syscon_css_clk_pclk_hclk && (css_ctrl & 0x1)) -#endif - { - /* Restore CSS */ - CSSV2_CTRL_REG = css_ctrl; - - /* Wait until CSS is in idle state */ - while (CSSV2_STATUS_REG & 0x1) - ; - } - } - - /* Restore AUTOCLKGATEOVERRIDE register*/ - SYSCON->AUTOCLKGATEOVERRIDE = 0xC0DE0000 | syscon_autoclkgateoverride_reg; - - /* Reset Sleep Postpone configuration */ - SYSCON->HARDWARESLEEP = 0; - - break; - } - - case LOWPOWER_CFG_LPMODE_POWERDOWN: - { - uint32_t lpcac_ctrl_reg; - uint32_t vref_rst_state; - uint32_t vref_clk_state; - uint32_t syscon_ahbclk_reg_0; - uint32_t syscon_css_clk_ctrl, syscon_css_clk_pclk_hclk; - - /* POWER DOWN power mode */ - power_core_pwr_source_t core_supply_source; - - /* Only FRO32K, XTAL32K, FRO1M, COMP, BIAS, LDO_MEM and can VREF stay powered during POWERDOWN */ - PMC->PDSLEEPCFG0 = - p_lowpower_cfg->PDCTRL[0] | - (0xFFFFFFFF & (~(kPDRUNCFG_PD_FRO1M | kPDRUNCFG_PD_FRO32K | kPDRUNCFG_PD_XTAL32K | kPDRUNCFG_PD_COMP | - kPDRUNCFG_PD_BIAS | kPDRUNCFG_PD_LDOMEM | kPDRUNCFG_PD_VREF))); - PMC->PDSLEEPCFG1 = p_lowpower_cfg->PDCTRL[1]; - - /* Make sure DEEP POWER DOWN reset is disabled */ - PMC->RESETCTRL = PMC->RESETCTRL & (~PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK); - -/* Enable VREF Module (reset & clock) */ -#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) - vref_rst_state = (SYSCON->PRESETCTRL3) & SYSCON_PRESETCTRL3_VREF_RST_MASK; - vref_clk_state = (SYSCON->AHBCLKCTRL3) & SYSCON_AHBCLKCTRL3_VREF_MASK; - SYSCON->PRESETCTRLCLR[3] = SYSCON_PRESETCTRL3_VREF_RST_MASK; - SYSCON->AHBCLKCTRLSET[3] = SYSCON_AHBCLKCTRL3_VREF_MASK; -#else - vref_rst_state = (*(uint32_t *)(((uint32_t *)SYSCON->RESERVED_5))) & 0x40000UL; - vref_clk_state = (*(uint32_t *)(((uint32_t *)SYSCON->RESERVED_9))) & 0x40000UL; - *(uint32_t *)(((uint32_t *)SYSCON->RESERVED_7)) = 0x40000UL; - *(uint32_t *)(((uint32_t *)SYSCON->RESERVED_10)) = 0x40000UL; -#endif - - /* Save VREF Module User Configuration ... */ - vref_regs[0] = VREF->CSR; - vref_regs[1] = VREF->UTRIM; - /* Save VREF Module Factory Trimmings ... */ - VREF->TEST_UNLOCK = 0x5AA5UL << 1; /* TEST_UNLOCK. Required before writting TRIM0 & TRIM1 */ - vref_regs[2] = VREF->TRIM0; - vref_regs[3] = VREF->TRIM1; - - /* ... then enable VREF Module isolation */ - PMC->MISCCTRL = PMC->MISCCTRL | PMC_MISCCTRL_VREF_ISO_MASK; - - // CSSV2 - { - syscon_css_clk_ctrl = SYSCON_CSS_CLK_CTRL_REG & (1U << 1); -#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) - syscon_css_clk_pclk_hclk = SYSCON->AHBCLKCTRL2 & (1U << 18); -#else - syscon_css_clk_pclk_hclk = SYSCON->AHBCLKCTRL[2] & (1U << 18); -#endif - - /* Switch off DTRNG clocks */ - SYSCON_CSS_CLK_CTRL_CLR_REG = (1U << 1); - - /* Swicth off i_css_clk/pclk/hclk */ - SYSCON->AHBCLKCTRLCLR[2] = (1U << 18); - } - - /* CPU0 Retention */ - SYSCON->FUNCRETENTIONCTRL = - (SYSCON->FUNCRETENTIONCTRL & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) | p_lowpower_cfg->CPURETCTRL; - - /* Disable all IRQs */ - __disable_irq(); - - /* - * From here : - * 1 - If an interrupt that is enable occurs, the _WFI instruction will not be executed and we won't enter - * in POWER DOWN. 2 - If an interrupt that is not enable occurs, there is no consequence neither on the - * execution of the low power mode nor on the behaviour of the CPU. - */ - - /* Switch PMC clock to 1 MHz and select LDO CORE (configured in High Power mode) as Core Logic supply source - * when waking up from POWER-DOWN */ - PMC->CTRL = (PMC->CTRL & (~PMC_CTRL_SELCLOCK_MASK)) | PMC_CTRL_SELCORESUPPLYWK_MASK; - - /* Save user Core Supply Source configuration */ - core_supply_source = POWER_GetCorePowerSource(); - - /* Store Analog Controller Registers */ - analog_ctrl_regs[0] = ANACTRL->FRO192M_CTRL; - analog_ctrl_regs[1] = ANACTRL->ANALOG_CTRL_CFG; - analog_ctrl_regs[2] = ANACTRL->ADC_CTRL; - analog_ctrl_regs[3] = ANACTRL->XO32M_CTRL; - analog_ctrl_regs[4] = ANACTRL->BOD_DCDC_INT_CTRL; - analog_ctrl_regs[5] = ANACTRL->LDO_XO32M; - analog_ctrl_regs[6] = ANACTRL->OSC_TESTBUS; - - /* Save Flash Cache settings, then disable and clear it */ - lpcac_ctrl_reg = SYSCON->LPCAC_CTRL; - SYSCON->LPCAC_CTRL = 0x3; /* dis_lpcac = '1', clr_lpcac = '1' */ - -/* Save ROM clock setting, then enable it. - * It is important to have the ROM clock running before entering - * POWER-DOWN for the following two reasons: - * 1 - In case of POWER-DOWN with CPU state retention (which is the only - * option currently offered to the user), some flip-flops that depend - on this clock need to be saved. - * 2 - In case of POWER-DOWN without CPU state retention (which is a - * hardware feature that is NOT offered to the user for the time being) - * CPU reboot cannot occur if ROM clock has been shut down. - */ -#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) - syscon_ahbclk_reg_0 = SYSCON->AHBCLKCTRL0; - SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_ROM_MASK; /* Enable the clock for ROM */ -#else - syscon_ahbclk_reg_0 = SYSCON->AHBCLKCTRL[0]; - SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_ROM_MASK; /* Enable the clock for ROM */ -#endif - - /* _WFI() */ - POWER_PowerCycleCpu(); - -/* Restore ROM clock setting */ -#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) - SYSCON->AHBCLKCTRL0 = syscon_ahbclk_reg_0; -#else - SYSCON->AHBCLKCTRL[0] = syscon_ahbclk_reg_0; -#endif - /* Restore Flash Cache settings */ - SYSCON->LPCAC_CTRL = lpcac_ctrl_reg; - - /* Switch PMC clock to 12 MHz and Configure the PMC in ACTIVE mode */ - PMC->CTRL = (PMC->CTRL & (~PMC_CTRL_LPMODE_MASK)) | PMC_CTRL_SELCLOCK_MASK | - PMC_CTRL_LPMODE(LOWPOWER_CFG_LPMODE_ACTIVE); - -#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) - { - /* Restore i_css_clk/pclk/hclk */ - SYSCON->AHBCLKCTRLSET[2] = syscon_css_clk_pclk_hclk; - - /* Restore DTRNG clocks */ - SYSCON_CSS_CLK_CTRL_SET_REG = syscon_css_clk_ctrl; - } -#endif - - /* Restore Analog Controller Registers */ - ANACTRL->FRO192M_CTRL = analog_ctrl_regs[0] | ANACTRL_FRO192M_CTRL_WRTRIM_MASK; - ANACTRL->ANALOG_CTRL_CFG = analog_ctrl_regs[1]; - ANACTRL->ADC_CTRL = analog_ctrl_regs[2]; - ANACTRL->XO32M_CTRL = analog_ctrl_regs[3]; - ANACTRL->BOD_DCDC_INT_CTRL = analog_ctrl_regs[4]; - ANACTRL->LDO_XO32M = analog_ctrl_regs[5]; - ANACTRL->OSC_TESTBUS = analog_ctrl_regs[6]; - - /* Restore VREF Module Factory Trimmings ... */ - VREF->TEST_UNLOCK = 0x5AA5UL << 1; /* TEST_UNLOCK. Required before writting TRIM0 & TRIM1 */ - VREF->TRIM0 = vref_regs[2]; - VREF->TRIM1 = vref_regs[3]; - /* ... then restore VREF Module User Configuration */ - VREF->CSR = vref_regs[0]; - VREF->UTRIM = vref_regs[1]; - -/* Restore VREF module reset and clock state */ -#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) - SYSCON->PRESETCTRL3 = (SYSCON->PRESETCTRL3 & (~SYSCON_PRESETCTRL3_VREF_RST_MASK)) | vref_rst_state; - SYSCON->AHBCLKCTRL3 = (SYSCON->AHBCLKCTRL3 & (~SYSCON_AHBCLKCTRL3_VREF_MASK)) | vref_clk_state; -#else - *(uint32_t *)(((uint32_t *)SYSCON->RESERVED_5)) = - ((*(uint32_t *)(((uint32_t *)SYSCON->RESERVED_5))) & (~0x40000UL)) | vref_rst_state; - *(uint32_t *)(((uint32_t *)SYSCON->RESERVED_9)) = - ((*(uint32_t *)(((uint32_t *)SYSCON->RESERVED_9))) & (~0x40000UL)) | vref_clk_state; -#endif - - /* Disable VREF Module isolation ... */ - PMC->MISCCTRL = PMC->MISCCTRL & (~PMC_MISCCTRL_VREF_ISO_MASK); - - /* After wake up from Power-down, the Core supply source is LDO CORE */ - /* So restore the user configuration if necessary */ - if (core_supply_source == kPOWER_CoreSrcDCDC) - { - /* Restore DCDC Converter as Core Logic supply source */ - /* NOTE: PMC must be set in ACTIVE mode first before doing this switching to DCDC */ - (void)POWER_SetCorePowerSource(kPOWER_CoreSrcDCDC); - } - - break; - } - - case LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN: - { - /* DEEP-POWER-DOWN power mode */ - - /* Configure wake-up by I/O : - * - Set up wake-up IO pad control source : PMC WAKEUPIOCTRL (WAKEUPIO_ENABLE = 1) - * - Reset Wake-up I/O Edge Detectors & Cause (WAKEUPIO_RSTN = 0) - */ - PMC->WAKEUPIOCTRL = p_lowpower_cfg->WAKEUPIOSRC | PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK; - - /* Release Wake up I/O reset (WAKEUPIO_RSTN = 1)*/ - PMC->WAKEUPIOCTRL |= PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_MASK; - - /* Only FRO1M, FRO32K, XTAL32K and LDOMEM can stay powered during DEEP POWER-DOWN */ - PMC->PDSLEEPCFG0 = - p_lowpower_cfg->PDCTRL[0] | (0xFFFFFFFF & (~(kPDRUNCFG_PD_FRO1M | kPDRUNCFG_PD_FRO32K | - kPDRUNCFG_PD_XTAL32K | kPDRUNCFG_PD_LDOMEM))); - PMC->PDSLEEPCFG1 = p_lowpower_cfg->PDCTRL[1]; - - /* Disable all IRQs */ - __disable_irq(); - - /* - * From here : - * 1 - If an interrupt that is enabled occurs, the _WFI instruction will not be executed and we won't enter - * in POWER DOWN. 2 - If an interrupt that is not enabled occurs, there is no consequence neither on the - * execution of the low power mode nor on the behaviour of the CPU. - */ - - /* clear all Reset causes */ - PMC->RESETCAUSE = 0xFFFFFFFF; - - /* Enable DEEP POWER-DOWN reset */ - PMC->RESETCTRL |= PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK; - - /* Switch PMC clock to 1 MHz */ - PMC->CTRL = PMC->CTRL & (~PMC_CTRL_SELCLOCK_MASK); - - /* _WFI() */ - POWER_PowerCycleCpu(); - - /*** We should never reach this point, unless the Low Power cycle has been cancelled somehow. ***/ - /* Switch PMC clock to 12 MHz and Configure the PMC in ACTIVE mode */ - PMC->CTRL = (PMC->CTRL & (~PMC_CTRL_LPMODE_MASK)) | PMC_CTRL_SELCLOCK_MASK | - PMC_CTRL_LPMODE(LOWPOWER_CFG_LPMODE_ACTIVE); - - break; - } - - default: - { - /* Error */ - } - } // End switch( low_power_mode ) - - /* Restore FMC Configuration */ - SYSCON->FMCCR = SYSCON->FMCCR | (fmccr_reg & SYSCON_FMCCR_PREFEN_MASK); - - /* - * Restore the configuration of the Priority Mask Register. - * Rational : if the interrupts were enable before entering the Low power mode, they will be re-enabled, - * if they were disabled, they will stay disabled. - */ - __set_PRIMASK(primask); - - /* Restore the configuration of the NMI Register */ - SYSCON->NMISRC |= cpu0_nmi_enable; - - /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the - * low power API */ - for (i = 0; i < 4; i++) - { - NVIC->ISER[i] = cpu0_int_enable[i]; - } -} - -/** - * @brief Configures and enters in low power mode - * @param : p_lowpower_cfg - * @return Nothing - */ -static uint32_t POWER_WakeUpIOCtrl(uint32_t p_wakeup_io_ctrl) -{ - uint32_t wake_up_type; - uint32_t wakeup_io_ctrl_reg = 0; - -// Enable IOCON -#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) - SYSCON->PRESETCTRLCLR[0] = SYSCON_PRESETCTRL0_IOCON_RST_MASK; - SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_IOCON_MASK; -#else - SYSCON->PRESETCTRLCLR[0] = SYSCON_PRESETCTRL_IOCON_RST_MASK; - SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_IOCON_MASK; -#endif - - /* Configure Pull up & Pull down based on the required wake-up edge */ - - /* Wake-up I/O 0 */ - wake_up_type = - (p_wakeup_io_ctrl & (PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK | PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK)) >> - LOWPOWER_WAKEUPIOSRC_PIO0_INDEX; - wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO0_INDEX); - if ((wake_up_type == LOWPOWER_WAKEUPIOSRC_RISING) || (wake_up_type == LOWPOWER_WAKEUPIOSRC_RISING_FALLING)) - { - /* Rising edge and both rising and falling edges */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK) == 0) - { - /* Internal pull up / pull down are not disabled by the user, so use them */ - IOCON->PIO[WAKEUPIO_0_PORT][WAKEUPIO_0_PINS] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ - wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); - } - } - else - { - if (wake_up_type == LOWPOWER_WAKEUPIOSRC_FALLING) - { - /* Falling edge only */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK) == 0) - { - /* Internal pull up / pull down are not disabled by the user, so use them */ - IOCON->PIO[WAKEUPIO_0_PORT][WAKEUPIO_0_PINS] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ - wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); - } - } - else - { - /* Wake-up I/O is disabled : set pull-up/pull-down as required by the user */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK) != 0) - { - /* Wake-up I/O is configured as Plain Input */ - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; - wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-up or pull-down */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK) != 0) - { - /* Wake-up I/O is configured as pull-up */ - wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-down */ - wakeup_io_ctrl_reg |= - (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); - } - } - } - } - - /* Wake-up I/O 1 */ - wake_up_type = - (p_wakeup_io_ctrl & (PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK | PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK)) >> - LOWPOWER_WAKEUPIOSRC_PIO1_INDEX; - wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO1_INDEX); - if ((wake_up_type == LOWPOWER_WAKEUPIOSRC_RISING) || (wake_up_type == LOWPOWER_WAKEUPIOSRC_RISING_FALLING)) - { - /* Rising edge and both rising and falling edges */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK) == 0) - { - /* Internal pull up / pull down are not disabled by the user, so use them */ - IOCON->PIO[WAKEUPIO_1_PORT][WAKEUPIO_1_PINS] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ - wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); - } - } - else - { - if (wake_up_type == LOWPOWER_WAKEUPIOSRC_FALLING) - { - /* Falling edge only */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK) == 0) - { - /* Internal pull up / pull down are not disabled by the user, so use them */ - IOCON->PIO[WAKEUPIO_1_PORT][WAKEUPIO_1_PINS] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ - wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); - } - } - else - { - /* Wake-up I/O is disabled : set it as required by the user */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK) != 0) - { - /* Wake-up I/O is configured as Plain Input */ - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; - wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-up or pull-down */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK) != 0) - { - /* Wake-up I/O is configured as pull-up */ - wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-down */ - wakeup_io_ctrl_reg |= - (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); - } - } - } - } - - /* Wake-up I/O 2 */ - wake_up_type = - (p_wakeup_io_ctrl & (PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK | PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK)) >> - LOWPOWER_WAKEUPIOSRC_PIO2_INDEX; - wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO2_INDEX); - if ((wake_up_type == LOWPOWER_WAKEUPIOSRC_RISING) || (wake_up_type == LOWPOWER_WAKEUPIOSRC_RISING_FALLING)) - { - /* Rising edge and both rising and falling edges */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK) == 0) - { - /* Internal pull up / pull down are not disabled by the user, so use them */ - IOCON->PIO[WAKEUPIO_2_PORT][WAKEUPIO_2_PINS] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ - wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); - } - } - else - { - if (wake_up_type == LOWPOWER_WAKEUPIOSRC_FALLING) - { - /* Falling edge only */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK) == 0) - { - /* Internal pull up / pull down are not disabled by the user, so use them */ - IOCON->PIO[WAKEUPIO_2_PORT][WAKEUPIO_2_PINS] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ - wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); - } - } - else - { - /* Wake-up I/O is disabled : set it as required by the user */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK) != 0) - { - /* Wake-up I/O is configured as Plain Input */ - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; - wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-up or pull-down */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK) != 0) - { - /* Wake-up I/O is configured as pull-up */ - wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-down */ - wakeup_io_ctrl_reg |= - (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); - } - } - } - } - - /* Wake-up I/O 3 */ - wake_up_type = - (p_wakeup_io_ctrl & (PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK | PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK)) >> - LOWPOWER_WAKEUPIOSRC_PIO3_INDEX; - wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO3_INDEX); - if ((wake_up_type == LOWPOWER_WAKEUPIOSRC_RISING) || (wake_up_type == LOWPOWER_WAKEUPIOSRC_RISING_FALLING)) - { - /* Rising edge and both rising and falling edges */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK) == 0) - { - /* Internal pull up / pull down are not disabled by the user, so use them */ - IOCON->PIO[WAKEUPIO_3_PORT][WAKEUPIO_3_PINS] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ - wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); - } - } - else - { - if (wake_up_type == LOWPOWER_WAKEUPIOSRC_FALLING) - { - /* Falling edge only */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK) == 0) - { - /* Internal pull up / pull down are not disabled by the user, so use them */ - IOCON->PIO[WAKEUPIO_3_PORT][WAKEUPIO_3_PINS] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ - wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); - } - } - else - { - /* Wake-up I/O is disabled : set it as required by the user */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK) != 0) - { - /* Wake-up I/O is configured as Plain Input */ - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; - wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-up or pull-down */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK) != 0) - { - /* Wake-up I/O is configured as pull-up */ - wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-down */ - wakeup_io_ctrl_reg |= - (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); - } - } - } - } - - /* Wake-up I/O 4 */ - wake_up_type = - (p_wakeup_io_ctrl & (PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP4_MASK | PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP4_MASK)) >> - LOWPOWER_WAKEUPIOSRC_PIO4_INDEX; - wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO4_INDEX); - if ((wake_up_type == LOWPOWER_WAKEUPIOSRC_RISING) || (wake_up_type == LOWPOWER_WAKEUPIOSRC_RISING_FALLING)) - { - /* Rising edge and both rising and falling edges */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO4_DISABLEPULLUPDOWN_MASK) == 0) - { - /* Internal pull up / pull down are not disabled by the user, so use them */ - IOCON->PIO[WAKEUPIO_4_PORT][WAKEUPIO_4_PINS] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ - wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO4MODE_INDEX); - } - } - else - { - if (wake_up_type == LOWPOWER_WAKEUPIOSRC_FALLING) - { - /* Falling edge only */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO4_DISABLEPULLUPDOWN_MASK) == 0) - { - /* Internal pull up / pull down are not disabled by the user, so use them */ - IOCON->PIO[WAKEUPIO_4_PORT][WAKEUPIO_4_PINS] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ - wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO4MODE_INDEX); - } - } - else - { - /* Wake-up I/O is disabled : set it as required by the user */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO4_DISABLEPULLUPDOWN_MASK) != 0) - { - /* Wake-up I/O is configured as Plain Input */ - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO4_PULLUPDOWN_MASK; - wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO4MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-up or pull-down */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO4_PULLUPDOWN_MASK) != 0) - { - /* Wake-up I/O is configured as pull-up */ - wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO4MODE_INDEX); - } - else - { - /* Wake-up I/O is configured as pull-down */ - wakeup_io_ctrl_reg |= - (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO4MODE_INDEX); - } - } - } - } - - return (wakeup_io_ctrl_reg); -} - -static uint32_t POWER_SetLdoAoLdoMemVoltage(uint32_t p_lp_mode) -{ - uint32_t voltage = 0; - uint32_t ldo_ao_trim = 0; - uint32_t ldo_mem_trim = 0; - uint32_t lv_v_ldo_pmu, lv_v_ldo_pmu_boost; - uint32_t lv_v_ldo_mem, lv_v_ldo_mem_boost; - -#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) - ldo_ao_trim = FLASH_NMPA_LDO_AO; - ldo_mem_trim = FLASH_NMPA_LDO_MEM; -#endif - - switch (p_lp_mode) - { - case LOWPOWER_CFG_LPMODE_DEEPSLEEP: - { - if ((ldo_ao_trim & 0x80000000) != 0) - { - /* Apply settings coming from Flash */ - lv_v_ldo_pmu = (ldo_ao_trim >> 8) & 0x1F; - lv_v_ldo_pmu_boost = (ldo_ao_trim >> 13) & 0x1F; - } - else - { - /* Apply default settings */ - lv_v_ldo_pmu = V_AO_0P900; - lv_v_ldo_pmu_boost = V_AO_0P850; - } - } - break; - - case LOWPOWER_CFG_LPMODE_POWERDOWN: - { - if ((ldo_ao_trim & 0x80000000) != 0) - { - /* Apply settings coming from Flash */ - lv_v_ldo_pmu = (ldo_ao_trim >> 18) & 0x1F; - lv_v_ldo_pmu_boost = (ldo_ao_trim >> 23) & 0x1F; - } - else - { - /* Apply default settings */ - lv_v_ldo_pmu = V_AO_0P800; - lv_v_ldo_pmu_boost = V_AO_0P750; - } - } - break; - - case LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN: - { - if ((ldo_ao_trim & 0x80000000) != 0) - { - /* Apply settings coming from Flash */ - lv_v_ldo_pmu = (ldo_ao_trim >> 18) & 0x1F; - lv_v_ldo_pmu_boost = (ldo_ao_trim >> 23) & 0x1F; - } - else - { - /* Apply default settings */ - lv_v_ldo_pmu = V_AO_0P800; - lv_v_ldo_pmu_boost = V_AO_0P750; - } - } - break; - - default: - /* We should never reach this point */ - lv_v_ldo_pmu = V_AO_1P100; - lv_v_ldo_pmu_boost = V_AO_1P050; - } - - if ((ldo_mem_trim & 0x80000000) != 0) - { - /* Apply settings coming from Flash */ - lv_v_ldo_mem = ldo_mem_trim & 0x1F; - lv_v_ldo_mem_boost = (ldo_mem_trim >> 8) & 0x1F; - } - else - { - /* Apply default settings */ - lv_v_ldo_mem = V_AO_0P750; /* Set to 0.75V (voltage Scaling) */ - lv_v_ldo_mem_boost = V_AO_0P700; /* Set to 0.7V (voltage Scaling) */ - } - - /* The Memories Voltage settings below are for voltage scaling */ - voltage = (lv_v_ldo_pmu << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) | - (lv_v_ldo_pmu_boost << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) | - (lv_v_ldo_mem << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) | - (lv_v_ldo_mem_boost << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX); - - return (voltage); -} - -/** - * @brief Configures System Power Profile - * @param power_profile : Low/Medium/High - * @return Nothing - */ -static void POWER_SetSystemPowerProfile(v_system_power_profile_t power_profile) -{ - uint32_t dcdcTrimValue0 = 0; - uint32_t dcdcTrimValue1 = 0; - - switch (power_profile) - { - case V_SYSTEM_POWER_PROFILE_MEDIUM: - /* Medium */ - -#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) - dcdcTrimValue0 = FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY0; - dcdcTrimValue1 = FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY1; -#endif - - if (dcdcTrimValue0 & 0x1) - { - /* DCDC Trimmings in Flash are valid */ - dcdcTrimValue0 = dcdcTrimValue0 >> 1; - PMC->DCDC0 = dcdcTrimValue0; - PMC->DCDC1 = dcdcTrimValue1; - } - else - { - /* DCDC Trimmings in Flash are not valid. - * Set a default value */ - PMC->DCDC0 = 0x0220ACF1 >> 1; - PMC->DCDC1 = 0x01D05C78; - } - - break; - - case V_SYSTEM_POWER_PROFILE_HIGH: -/* High */ -#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) - dcdcTrimValue0 = FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY0; - dcdcTrimValue1 = FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY1; -#endif - - if (dcdcTrimValue0 & 0x1) - { - /* DCDC Trimmings in Flash are valid */ - dcdcTrimValue0 = dcdcTrimValue0 >> 1; - PMC->DCDC0 = dcdcTrimValue0; - PMC->DCDC1 = dcdcTrimValue1; - } - else - { - /* DCDC Trimmings in Flash are not valid. - * Set a default value */ - PMC->DCDC0 = 0x0228ACF9 >> 1; - PMC->DCDC1 = 0x01E05C68; - } - - break; - - default: -/* Low */ -#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) - dcdcTrimValue0 = FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY0; - dcdcTrimValue1 = FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY1; -#endif - - if (dcdcTrimValue0 & 0x1) - { - /* DCDC Trimmings in Flash are valid */ - dcdcTrimValue0 = dcdcTrimValue0 >> 1; - PMC->DCDC0 = dcdcTrimValue0; - PMC->DCDC1 = dcdcTrimValue1; - } - else - { - /* DCDC Trimmings in Flash are not valid. - * Set a default value */ - PMC->DCDC0 = 0x0210CCFD >> 1; - PMC->DCDC1 = 0x01C05C98; - } - } -} - -/** - * @brief Configures System Power Profile - * @param power_profile : Low/Medium/High - * @return Nothing - */ -static void POWER_SetVoltageForProcess(v_system_power_profile_t power_profile) -{ - /* Get Sample Process Corner */ - lowpower_process_corner_enum part_process_corner = POWER_GetPartProcessCorner(); - - switch (part_process_corner) - { - case PROCESS_CORNER_SSS: - /* Slow Corner */ - { - switch (power_profile) - { - case V_SYSTEM_POWER_PROFILE_MEDIUM: - /* Medium */ - POWER_SetSystemVoltage(VOLTAGE_SSS_MED_MV); - break; - - case V_SYSTEM_POWER_PROFILE_HIGH: - /* High */ - POWER_SetSystemVoltage(VOLTAGE_SSS_HIG_MV); - break; - - default: - /* V_SYSTEM_POWER_PROFILE_LOW */ - POWER_SetSystemVoltage(VOLTAGE_SSS_LOW_MV); - } // switch(power_profile) - } - break; - - case PROCESS_CORNER_FFF: - /* Fast Corner */ - { - switch (power_profile) - { - case V_SYSTEM_POWER_PROFILE_MEDIUM: - /* Medium */ - POWER_SetSystemVoltage(VOLTAGE_FFF_MED_MV); - break; - - case V_SYSTEM_POWER_PROFILE_HIGH: - /* High */ - POWER_SetSystemVoltage(VOLTAGE_FFF_HIG_MV); - break; - - default: - /* V_SYSTEM_POWER_PROFILE_LOW */ - POWER_SetSystemVoltage(VOLTAGE_FFF_LOW_MV); - } // switch(power_profile) - } - break; - - default: - /* Nominal (NNN) and all others Process Corners : assume Nominal Corner */ - { - switch (power_profile) - { - case V_SYSTEM_POWER_PROFILE_MEDIUM: - /* Medium */ - POWER_SetSystemVoltage(VOLTAGE_NNN_MED_MV); - break; - - case V_SYSTEM_POWER_PROFILE_HIGH: - /* High */ - POWER_SetSystemVoltage(VOLTAGE_NNN_HIG_MV); - break; - - default: - /* V_SYSTEM_POWER_PROFILE_LOW */ - POWER_SetSystemVoltage(VOLTAGE_NNN_LOW_MV); - } // switch(power_profile) - } - } // switch(part_process_corner) -} - -/** - * @brief - * @param - * @return - */ -static lowpower_process_corner_enum POWER_GetPartProcessCorner(void) -{ - lowpower_process_corner_enum part_process_corner; - uint32_t pvt_ringo_hz; - uint32_t pvt_ringo_0 = 0; - uint32_t pvt_ringo_1 = 0; - -#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) - pvt_ringo_0 = FLASH_NMPA_PVT_MONITOR_0_RINGO; - pvt_ringo_1 = FLASH_NMPA_PVT_MONITOR_1_RINGO; -#endif - - /* - * Check that the PVT Monitors Trimmings in flash are valid. - * Note : On Customer Samples, PVT Trimmings in flash will ALWAYS be valid, - * so that in the SDK, the check below could be skipped (but NOT the right shift operation) - */ - if (pvt_ringo_0 & 0x1) - { - /* PVT Trimmings in Flash are valid */ - pvt_ringo_0 = pvt_ringo_0 >> 1; - } - else - { - /* PVT Trimmings in Flash are NOT valid (average value assumed) */ - pvt_ringo_0 = PROCESS_NNN_AVG_HZ; - } - - if (pvt_ringo_1 & 0x1) - { - /* PVT Trimmings in Flash are valid */ - pvt_ringo_1 = pvt_ringo_1 >> 1; - } - else - { - /* PVT Trimmings in Flash are NOT valid (average value assumed) */ - pvt_ringo_1 = PROCESS_NNN_AVG_HZ; - } - - /* - * There are 2 Ring Oscillators in the System. - * We consider the worst case scenario by choosing - * the minimum of the 2 Ring Oscillators values - * as the final value to determine the Process Corner. - */ - if (pvt_ringo_1 <= pvt_ringo_0) - { - pvt_ringo_hz = pvt_ringo_1; - } - else - { - pvt_ringo_hz = pvt_ringo_0; - } - - /* - * Determine the process corner based on the value of the Ring Oscillator frequency - */ - if (pvt_ringo_hz <= PROCESS_NNN_MIN_HZ) - { - /* SSS Process Corner */ - part_process_corner = PROCESS_CORNER_SSS; - } - else - { - if (pvt_ringo_hz <= PROCESS_NNN_MAX_HZ) - { - /* NNN Process Corner */ - part_process_corner = PROCESS_CORNER_NNN; - } - else - { - /* FFF Process Corner */ - part_process_corner = PROCESS_CORNER_FFF; - } - } - - return (part_process_corner); -} - -/** - * @brief - * @param - * @return - */ -static void POWER_SetSystemVoltage(uint32_t system_voltage_mv) -{ - /* - * Set system voltage - */ - uint32_t lv_ldo_ao = V_AO_1P100; /* */ - uint32_t lv_ldo_ao_boost = V_AO_1P150; /* */ - uint32_t lv_dcdc = V_DCDC_1P100; /* */ - uint32_t lv_ldo_core = V_LDOCORE_HP_1P102; /* */ - - /* - * Because DCDC has less code than LD_AO, we first determine the - * optimum DCDC settings, then we find the closest possible settings - * for LDO_AO, knowing that we want both settings to be as close as possible - * (ideally, they shall be equal). - */ - - if (system_voltage_mv <= 950) - { - lv_dcdc = V_DCDC_0P950; - lv_ldo_ao = V_AO_0P960; - lv_ldo_ao_boost = V_AO_1P010; - lv_ldo_core = V_LDOCORE_HP_0P953; - } - else if (system_voltage_mv <= 975) - { - lv_dcdc = V_DCDC_0P975; - lv_ldo_ao = V_AO_0P980; - lv_ldo_ao_boost = V_AO_1P030; - lv_ldo_core = V_LDOCORE_HP_0P980; - } - else if (system_voltage_mv <= 1000) - { - lv_dcdc = V_DCDC_1P000; - lv_ldo_ao = V_AO_1P000; - lv_ldo_ao_boost = V_AO_1P050; - lv_ldo_core = V_LDOCORE_HP_1P001; - } - else if (system_voltage_mv <= 1025) - { - lv_dcdc = V_DCDC_1P025; - lv_ldo_ao = V_AO_1P030; - lv_ldo_ao_boost = V_AO_1P080; - lv_ldo_core = V_LDOCORE_HP_1P027; - } - else if (system_voltage_mv <= 1050) - { - lv_dcdc = V_DCDC_1P050; - lv_ldo_ao = V_AO_1P060; - lv_ldo_ao_boost = V_AO_1P110; - lv_ldo_core = V_LDOCORE_HP_1P055; - } - else if (system_voltage_mv <= 1075) - { - lv_dcdc = V_DCDC_1P075; - lv_ldo_ao = V_AO_1P080; - lv_ldo_ao_boost = V_AO_1P130; - lv_ldo_core = V_LDOCORE_HP_1P075; - } - else if (system_voltage_mv <= 1100) - { - lv_dcdc = V_DCDC_1P100; - lv_ldo_ao = V_AO_1P100; - lv_ldo_ao_boost = V_AO_1P150; - lv_ldo_core = V_LDOCORE_HP_1P102; - } - else if (system_voltage_mv <= 1125) - { - lv_dcdc = V_DCDC_1P125; - lv_ldo_ao = V_AO_1P130; - lv_ldo_ao_boost = V_AO_1P160; - lv_ldo_core = V_LDOCORE_HP_1P027; - } - else if (system_voltage_mv <= 1150) - { - lv_dcdc = V_DCDC_1P150; - lv_ldo_ao = V_AO_1P160; - lv_ldo_ao_boost = V_AO_1P220; - lv_ldo_core = V_LDOCORE_HP_1P156; - } - else if (system_voltage_mv <= 1175) - { - lv_dcdc = V_DCDC_1P175; - lv_ldo_ao = V_AO_1P160; - lv_ldo_ao_boost = V_AO_1P220; - lv_ldo_core = V_LDOCORE_HP_1P177; - } - else - { - lv_dcdc = V_DCDC_1P200; - lv_ldo_ao = V_AO_1P220; - lv_ldo_ao_boost = V_AO_1P220; - lv_ldo_core = V_LDOCORE_HP_1P204; - } - -/* Set up LDO Always-On voltages */ -#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) - /* Apply LDO_AO Trimmings */ - { - int8_t ldo_ao_offset; - int32_t lv_ldo_ao_signed; - - ldo_ao_offset = - (int8_t)((FLASH_NMPA_LDO_AO & FLASH_NMPA_LDO_AO_VADJ_ACTIVE_MASK) >> FLASH_NMPA_LDO_AO_VADJ_ACTIVE_SHIFT); - lv_ldo_ao_signed = (int32_t)((int32_t)lv_ldo_ao + (int32_t)ldo_ao_offset); - - if (lv_ldo_ao_signed < (int32_t)V_AO_0P960) - { - lv_ldo_ao = V_AO_0P960; - } - else - { - if (lv_ldo_ao_signed > (int32_t)V_AO_1P220) - { - lv_ldo_ao = V_AO_1P220; - } - else - { - lv_ldo_ao = (uint32_t)lv_ldo_ao_signed; - } - } - } -// Note: In ACTIVE mode, the LDO BOOST mode is always enabled. -// Therefore, the value of the "lv_ldo_ao_boost" does not really matter. -// For that reason, we do not recompuete it here. -#endif - PMC->LDOPMU = (PMC->LDOPMU & (~PMC_LDOPMU_VADJ_MASK) & (~PMC_LDOPMU_VADJ_BOOST_MASK)) | PMC_LDOPMU_VADJ(lv_ldo_ao) | - PMC_LDOPMU_VADJ_BOOST(lv_ldo_ao_boost); - - /* Set up DCDC voltage */ - PMC->DCDC0 = (PMC->DCDC0 & (~PMC_DCDC0_VOUT_MASK)) | PMC_DCDC0_VOUT(lv_dcdc); - -/* Set up LDO_CORE voltage */ -#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) - /* Apply LDO_CORE Trimmings */ - { - int8_t ldo_core_regref_offset; - int32_t lv_ldo_core_signed; - - ldo_core_regref_offset = (int8_t)((FLASH_NMPA_BOD_LDOCORE & FLASH_NMPA_BOD_LDOCORE_REGREF_1P8V_OFFSET_MASK) >> - FLASH_NMPA_BOD_LDOCORE_REGREF_1P8V_OFFSET_SHIFT); - lv_ldo_core_signed = (int32_t)((int32_t)lv_ldo_core + (int32_t)ldo_core_regref_offset); - - if (lv_ldo_core_signed < (int32_t)V_LDOCORE_HP_1P204) - { - lv_ldo_core = V_LDOCORE_HP_1P204; - } - else - { - if (lv_ldo_core_signed > (int32_t)V_LDOCORE_HP_0P953) - { - lv_ldo_core = V_LDOCORE_HP_0P953; - } - else - { - lv_ldo_core = (uint32_t)lv_ldo_core_signed; - } - } - } -#endif - PMC->LDOCORE0 = (PMC->LDOCORE0 & (~PMC_LDOCORE0_REGREFTRIM_MASK)) | PMC_LDOCORE0_REGREFTRIM(lv_ldo_core); -} - -/** - * brief - * return - */ -static void POWER_SRAMSetRegister(power_sram_index_t sram_index, uint32_t power_mode) -{ - switch (sram_index) - { - case kPOWER_SRAM_IDX_RAM_X0: - { - PMC->SRAMCTRL0 = (PMC->SRAMCTRL0 & (~(0xFUL << PMC_SRAMCTRL0_RAM_X0_LS_SHIFT))) | - (power_mode << PMC_SRAMCTRL0_RAM_X0_LS_SHIFT); - break; - } - - case kPOWER_SRAM_IDX_RAM_00: - { - PMC->SRAMCTRL0 = (PMC->SRAMCTRL0 & (~(0xFUL << PMC_SRAMCTRL0_RAM_00_LS_SHIFT))) | - (power_mode << PMC_SRAMCTRL0_RAM_00_LS_SHIFT); - break; - } - - case kPOWER_SRAM_IDX_RAM_01: - { - PMC->SRAMCTRL0 = (PMC->SRAMCTRL0 & (~(0xFUL << PMC_SRAMCTRL0_RAM_01_LS_SHIFT))) | - (power_mode << PMC_SRAMCTRL0_RAM_01_LS_SHIFT); - break; - } - - case kPOWER_SRAM_IDX_RAM_02: - { - PMC->SRAMCTRL0 = (PMC->SRAMCTRL0 & (~(0xFUL << PMC_SRAMCTRL0_RAM_02_LS_SHIFT))) | - (power_mode << PMC_SRAMCTRL0_RAM_02_LS_SHIFT); - break; - } - - case kPOWER_SRAM_IDX_RAM_03: - { - PMC->SRAMCTRL0 = (PMC->SRAMCTRL0 & (~(0xFUL << PMC_SRAMCTRL0_RAM_03_LS_SHIFT))) | - (power_mode << PMC_SRAMCTRL0_RAM_03_LS_SHIFT); - break; - } - - case kPOWER_SRAM_IDX_RAM_10: - { - PMC->SRAMCTRL0 = (PMC->SRAMCTRL0 & (~(0xFUL << PMC_SRAMCTRL0_RAM_10_LS_SHIFT))) | - (power_mode << PMC_SRAMCTRL0_RAM_10_LS_SHIFT); - break; - } - - case kPOWER_SRAM_IDX_RAM_20: - { - PMC->SRAMCTRL0 = (PMC->SRAMCTRL0 & (~(0xFUL << PMC_SRAMCTRL0_RAM_20_LS_SHIFT))) | - (power_mode << PMC_SRAMCTRL0_RAM_20_LS_SHIFT); - break; - } - - case kPOWER_SRAM_IDX_RAM_30: - { - PMC->SRAMCTRL0 = (PMC->SRAMCTRL0 & (~(0xFUL << PMC_SRAMCTRL0_RAM_30_LS_SHIFT))) | - (power_mode << PMC_SRAMCTRL0_RAM_30_LS_SHIFT); - break; - } - - case kPOWER_SRAM_IDX_RAM_40: - { - PMC->SRAMCTRL1 = (PMC->SRAMCTRL1 & (~(0xFUL << PMC_SRAMCTRL1_RAM_40_LS_SHIFT))) | - (power_mode << PMC_SRAMCTRL1_RAM_40_LS_SHIFT); - break; - } - - case kPOWER_SRAM_IDX_RAM_41: - { - PMC->SRAMCTRL1 = (PMC->SRAMCTRL1 & (~(0xFUL << PMC_SRAMCTRL1_RAM_41_LS_SHIFT))) | - (power_mode << PMC_SRAMCTRL1_RAM_41_LS_SHIFT); - break; - } - - case kPOWER_SRAM_IDX_RAM_42: - { - PMC->SRAMCTRL1 = (PMC->SRAMCTRL1 & (~(0xFUL << PMC_SRAMCTRL1_RAM_42_LS_SHIFT))) | - (power_mode << PMC_SRAMCTRL1_RAM_42_LS_SHIFT); - break; - } - - case kPOWER_SRAM_IDX_RAM_43: - { - PMC->SRAMCTRL1 = (PMC->SRAMCTRL1 & (~(0xFUL << PMC_SRAMCTRL1_RAM_43_LS_SHIFT))) | - (power_mode << PMC_SRAMCTRL1_RAM_43_LS_SHIFT); - break; - } - - case kPOWER_SRAM_IDX_FLASHCACHE: - { - PMC->SRAMCTRL1 = (PMC->SRAMCTRL1 & (~(0xFUL << PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LS_SHIFT))) | - (power_mode << PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LS_SHIFT); - break; - } - - case kPOWER_SRAM_IDX_FLEXSPICACHE: - { - PMC->SRAMCTRL1 = (PMC->SRAMCTRL1 & (~(0xFUL << PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LS_SHIFT))) | - (power_mode << PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LS_SHIFT); - break; - } - - default: - // Error - ; - } -} - -/** - * brief - * return - */ -static void POWER_SRAMActiveToLightSleep(power_sram_index_t sram_index) -{ - POWER_SRAMSetRegister(sram_index, SRAM_PWR_MODE_LS_CODE); -} - -/** - * brief - * return - */ -static void POWER_SRAMActiveToDeepSleep(power_sram_index_t sram_index) -{ - POWER_SRAMSetRegister(sram_index, SRAM_PWR_MODE_DS_CODE); -} - -/** - * brief - * return - */ -static void POWER_SRAMActiveToShutDown(power_sram_index_t sram_index) -{ - POWER_SRAMSetRegister(sram_index, SRAM_PWR_MODE_SD_CODE); -} - -/** - * brief - * return - */ -static void POWER_SRAMLightSleepToActive(power_sram_index_t sram_index) -{ - POWER_SRAMSetRegister(sram_index, SRAM_PWR_MODE_MPU_CODE); - // Wait at least 944.90 ns (worst case, from gf40rfnv_nxp_ehlvsram_008192x032bw4c04_mh_pt_m7) - POWER_SRAMPowerUpDelay(); // wait about 1 us - POWER_SRAMSetRegister(sram_index, SRAM_PWR_MODE_ACT_CODE); -} - -/** - * brief - * return - */ -static void POWER_SRAMDeepSleepToActive(power_sram_index_t sram_index) -{ - POWER_SRAMSetRegister(sram_index, SRAM_PWR_MODE_FPU_CODE); - // Wait at least 707.30 ns (worst case, from gf40rfnv_nxp_ehlvsram_008192x032bw4c04_mh_pt_m7) - POWER_SRAMPowerUpDelay(); // wait about 1 us - POWER_SRAMSetRegister(sram_index, SRAM_PWR_MODE_ACT_CODE); -} - -/** - * brief - * return - */ -static void POWER_SRAMShutDownToActive(power_sram_index_t sram_index) -{ - POWER_SRAMSetRegister(sram_index, SRAM_PWR_MODE_FPU_CODE); - // Wait at least 382.80 ns (worst case, from gf40rfnv_nxp_ehlvsram_008192x032bw4c04_mh_pt_m7) - POWER_SRAMPowerUpDelay(); // wait about 1 us - POWER_SRAMSetRegister(sram_index, SRAM_PWR_MODE_ACT_CODE); -} - -/** - * brief - * return - */ -static void POWER_SetSystemClock12MHZ(void) -{ - if ((SYSCON->MAINCLKSELA != 0) || (SYSCON->MAINCLKSELB != 0) || - ((SYSCON->AHBCLKDIV & SYSCON_AHBCLKDIV_DIV_MASK) != 0)) - { - /* The System is NOT running at 12 MHz: so switch the system on 12 MHz clock */ - /* IMPORTANT NOTE : The assumption here is that before calling any Low Power API - * the system will be running at a frequency higher or equal to 12 MHz. - */ - uint32_t flash_int_enable_reg; - uint32_t num_wait_states = 1; /* Default to the maximum number of wait states */ - - /* Switch main clock to FRO12MHz ( the order of the 5 settings below is critical) */ - SYSCON->MAINCLKSELA = SYSCON_MAINCLKSELA_SEL(0); /* Main clock A source select : FRO 12 MHz clock */ - SYSCON->MAINCLKSELB = SYSCON_MAINCLKSELB_SEL(0); /* Main clock B source select : Main Clock A */ - SYSCON->AHBCLKDIV = SYSCON_AHBCLKDIV_DIV(0); /* Main clock divided by 1 */ - -/* Adjust FMC waiting time cycles (num_wait_states) and disable PREFETCH - * NOTE : PREFETCH disable MUST BE DONE BEFORE the flash command below. - */ -#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) - SYSCON->FMCCR = (SYSCON->FMCCR & (~SYSCON_FMCCR_FLASHTIM_MASK) & (~SYSCON_FMCCR_PREFEN_MASK)) | - SYSCON_FMCCR_FLASHTIM(num_wait_states); - /* Adjust Flash Controller waiting time */ - flash_int_enable_reg = FLASH->INTEN; /* Save INT_ENABLE register. */ - FLASH->INTEN_CLR = 0x1F; /* Disable all interrupt */ - FLASH->INTSTAT_CLR = 0x1F; /* Clear all status flags */ -#else - SYSCON->FMCCR = (SYSCON->FMCCR & (~SYSCON_FMCCR_FMCTIM_MASK) & (~SYSCON_FMCCR_PREFEN_MASK)) | - SYSCON_FMCCR_FMCTIM(num_wait_states); - /* Adjust Flash Controller waiting time */ - flash_int_enable_reg = FLASH->INT_ENABLE; /* Save INT_ENABLE register. */ - FLASH->INT_CLR_ENABLE = 0x1F; /* Disable all interrupt */ - FLASH->INT_CLR_STATUS = 0x1F; /* Clear all status flags */ -#endif - - FLASH->DATAW[0] = num_wait_states; - FLASH->CMD = 0x2; /* CMD_SET_READ_MODE */ - -#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) - /* Wait until the cmd is completed (without error) */ - while (!(FLASH->INTSTAT & FLASH_INTSTAT_DONE_MASK)) - ; - FLASH->INTSTAT_CLR = 0x1F; /* Clear all status flags, then ... */ - FLASH->INTEN_SET = flash_int_enable_reg; /* ... restore INT_ENABLE register. */ -#else - /* Wait until the cmd is completed (without error) */ - while (!(FLASH->INT_STATUS & FLASH_INT_STATUS_DONE_MASK)) - ; - FLASH->INT_CLR_STATUS = 0x1F; /* Clear all status flags, then ... */ - FLASH->INT_SET_ENABLE = flash_int_enable_reg; /* ... restore INT_ENABLE register. */ -#endif - - POWER_SetSystemPowerProfile( - V_SYSTEM_POWER_PROFILE_LOW); /* Align DCDC/LDO_CORE Power profile with the 12 MHz frequency */ - } - else - { - /* The System is already running at 12 MHz: so disable FMC PREFETCH feature only */ - SYSCON->FMCCR = SYSCON->FMCCR & (~SYSCON_FMCCR_PREFEN_MASK); - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_power.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_power.h deleted file mode 100644 index bba93821bb7..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_power.h +++ /dev/null @@ -1,751 +0,0 @@ -/* - * Copyright 2020, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_POWER_H_ -#define _FSL_POWER_H_ - -#include -#include "fsl_common.h" -#include "fsl_device_registers.h" - -/*! - * @addtogroup power - * @{ - */ -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief power driver version 1.0.0. */ -#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) -/*@}*/ - -/** - * @brief Low Power Modes configuration - */ -typedef enum _power_mode_config -{ - kPmu_Sleep = 0U, - kPmu_Deep_Sleep = 1U, - kPmu_PowerDown = 2U, - kPmu_Deep_PowerDown = 3U, -} power_mode_cfg_t; - -/** - * @brief Device Reset Causes - */ -typedef enum _power_reset_cause -{ - kRESET_CAUSE_POR = 0UL, /*!< Power On Reset */ - kRESET_CAUSE_PADRESET = 1UL, /*!< Hardware Pin Reset */ - kRESET_CAUSE_BODRESET = 2UL, /*!< Brown-out Detector reset (either BODVBAT or BODCORE) */ - kRESET_CAUSE_ARMSYSTEMRESET = 3UL, /*!< ARM System Reset */ - kRESET_CAUSE_WDTRESET = 4UL, /*!< Watchdog Timer Reset */ - kRESET_CAUSE_SWRRESET = 5UL, /*!< Software Reset */ - kRESET_CAUSE_CDOGRESET = 6UL, /*!< Code Watchdog Reset */ - /* Reset causes in DEEP-POWER-DOWN low power mode */ - kRESET_CAUSE_DPDRESET_WAKEUPIO = 7UL, /*!< Any of the 5 wake-up pins */ - kRESET_CAUSE_DPDRESET_RTC = 8UL, /*!< Real Time Clock (RTC) */ - kRESET_CAUSE_DPDRESET_OSTIMER = 9UL, /*!< OS Event Timer (OSTIMER) */ - kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC = - 10UL, /*!< Any of the 5 wake-up pins and RTC (the 2 events occured within 1 nano-second of each other) */ - kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER = - 11UL, /*!< Any of the 5 wake-up pins and OSTIMER (the 2 events occured within 1 nano-second of each other) */ - kRESET_CAUSE_DPDRESET_RTC_OSTIMER = - 12UL, /*!< Real Time Clock or OS Event Timer (the 2 events occured within 1 nano-second of each other) */ - kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER = 13UL, /*!< Any of the 5 wake-up pins or RTC or OS Event Timer (the 3 - events occured within 1 nano-second of each other) */ - /* Miscallenous */ - kRESET_CAUSE_NOT_RELEVANT = - 14UL, /*!< No reset cause (for example, this code is used when waking up from DEEP-SLEEP low power mode) */ - kRESET_CAUSE_NOT_DETERMINISTIC = 15UL, /*!< Unknown Reset Cause. Should be treated like "Hardware Pin Reset" from an - application point of view. */ -} power_reset_cause_t; - -/** - * @brief Device Boot Modes - */ -typedef enum _power_boot_mode -{ - kBOOT_MODE_POWER_UP = - 0UL, /*!< All non Low Power Mode wake up (Power On Reset, Pin Reset, BoD Reset, ARM System Reset ... ) */ - kBOOT_MODE_LP_DEEP_SLEEP = 1UL, /*!< Wake up from DEEP-SLEEP Low Power mode */ - kBOOT_MODE_LP_POWER_DOWN = 2UL, /*!< Wake up from POWER-DOWN Low Power mode */ - kBOOT_MODE_LP_DEEP_POWER_DOWN = 4UL, /*!< Wake up from DEEP-POWER-DOWN Low Power mode */ -} power_boot_mode_t; - -/** - * @brief Device wake up pins events - */ -typedef enum _power_wakeup_pin_t -{ - kWAKEUP_PIN_NONE = 0UL, /*!< No wake up pin event */ - kWAKEUP_PIN_0 = (1UL << 0), /*!< Wake up pin 0 event */ - kWAKEUP_PIN_1 = (1UL << 1), /*!< Wake up pin 1 event */ - kWAKEUP_PIN_2 = (1UL << 2), /*!< Wake up pin 2 event */ - kWAKEUP_PIN_3 = (1UL << 3), /*!< Wake up pin 3 event */ - kWAKEUP_PIN_4 = (1UL << 4), /*!< Wake up pin 4 event */ - kWAKEUP_PIN_MULTIPLE = 0x1FUL, /*!< More than 1 wake up pins events occured (within 1 nano-second of each other) */ -} power_wakeup_pin_t; - -/** - * @brief analog components power modes control during low power modes - */ -typedef enum _power_pd_bit -{ - /* Power Down Vector 0 */ - kPDRUNCFG_PD_DCDC = (1UL << 0), - kPDRUNCFG_PD_BIAS = (1UL << 1), - kPDRUNCFG_PD_BODCORE = (1UL << 2), - kPDRUNCFG_PD_BODVDDMAIN = (1UL << 3), - kPDRUNCFG_PD_FRO1M = (1UL << 4), - kPDRUNCFG_PD_FRO192M = (1UL << 5), - kPDRUNCFG_PD_FRO32K = (1UL << 6), - kPDRUNCFG_PD_XTAL32K = (1UL << 7), - kPDRUNCFG_PD_XTALHF = (1UL << 8), - kPDRUNCFG_PD_PLL0 = (1UL << 9), - kPDRUNCFG_PD_PLL1 = (1UL << 10), - kPDRUNCFG_PD_USBFSPHY = (1UL << 11), - // kPDRUNCFG_PD_ = (1UL << 12), /*!< RESERVED */ - kPDRUNCFG_PD_COMP = (1UL << 13), - // kPDRUNCFG_PD_ = (1UL << 14), /*!< RESERVED */ - // kPDRUNCFG_PD_ = (1UL << 15), /*!< RESERVED */ - kPDRUNCFG_PD_LDOMEM = (1UL << 16), - // kPDRUNCFG_PD_ = (1UL << 17), /*!< RESERVED */ - kPDRUNCFG_PD_LDOEFUSEPROG = (1UL << 18), - // kPDRUNCFG_PD_ = (1UL << 19), /*!< RESERVED */ - kPDRUNCFG_PD_LDOXTALHF = (1UL << 20), - kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21), - // kPDRUNCFG_PD_ = (1UL << 22), /*!< RESERVED */ - kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23), - kPDRUNCFG_PD_ROM = (1UL << 24), - kPDRUNCFG_PD_HSCMP0 = (1UL << 25), - kPDRUNCFG_PD_HSCMP1 = (1UL << 26), - kPDRUNCFG_PD_HSCMP2 = (1UL << 27), - kPDRUNCFG_PD_OPAMP0 = (1UL << 28), - kPDRUNCFG_PD_OPAMP1 = (1UL << 29), - kPDRUNCFG_PD_OPAMP2 = (1UL << 30), - kPDRUNCFG_PD_VREF = (1UL << 31), - - /* Power Down Vector 1 */ - kPDRUNCFG_PD_CMPBIAS = (1UL << 0) | (1UL << 31), - kPDRUNCFG_PD_HSCMP0_DAC = (1UL << 1) | (1UL << 31), - kPDRUNCFG_PD_HSCMP1_DAC = (1UL << 2) | (1UL << 31), - kPDRUNCFG_PD_HSCMP2_DAC = (1UL << 3) | (1UL << 31), - kPDRUNCFG_PD_DAC0 = (1UL << 4) | (1UL << 31), - kPDRUNCFG_PD_DAC1 = (1UL << 5) | (1UL << 31), - kPDRUNCFG_PD_DAC2 = (1UL << 6) | (1UL << 31), - kPDRUNCFG_STOP_DAC0 = (1UL << 7) | (1UL << 31), - kPDRUNCFG_STOP_DAC1 = (1UL << 8) | (1UL << 31), - kPDRUNCFG_STOP_DAC2 = (1UL << 9) | (1UL << 31), - - /* - This enum member has no practical meaning,it is used to avoid MISRA issue, - user should not trying to use it. - */ - kPDRUNCFG_ForceUnsigned = 0x80000000U, -} pd_bit_t; - -/** - * @brief SRAM instances bit masks - */ -typedef enum _power_sram_bit -{ - kPOWER_SRAM_RAM_X0 = (1UL << 0), /*!< RAM_X0 */ - kPOWER_SRAM_RAM_00 = (1UL << 1), /*!< RAM_00 */ - kPOWER_SRAM_RAM_01 = (1UL << 2), /*!< RAM_01 */ - kPOWER_SRAM_RAM_02 = (1UL << 3), /*!< RAM_02 */ - kPOWER_SRAM_RAM_03 = (1UL << 4), /*!< RAM_03 */ - kPOWER_SRAM_RAM_10 = (1UL << 5), /*!< RAM_10 */ - kPOWER_SRAM_RAM_20 = (1UL << 6), /*!< RAM_20 */ - kPOWER_SRAM_RAM_30 = (1UL << 7), /*!< RAM_30 */ - kPOWER_SRAM_RAM_40 = (1UL << 8), /*!< RAM_40 */ - kPOWER_SRAM_RAM_41 = (1UL << 9), /*!< RAM_41 */ - kPOWER_SRAM_RAM_42 = (1UL << 10), /*!< RAM_42 */ - kPOWER_SRAM_RAM_43 = (1UL << 11), /*!< RAM_43 */ - kPOWER_SRAM_FLASHCACHE = (1UL << 12), /*!< Reserved. Flash Cache SRAM instance */ - kPOWER_SRAM_FLEXSPICACHE = (1UL << 13), /*!< Reserved. FlexSPI Cache SRAM instance */ - kPOWER_SRAM_FLEXSPIH2PREG = (1UL << 14), /*!< Reserved. FlexSPI Dual Port Register Files instances */ - - kPOWER_SRAM_DSLP_MASK = 0x7FFFUL, /*!< Reserved. DEEP-SLEEP SRAM instances */ - kPOWER_SRAM_PDWN_MASK = 0xFFFUL, /*!< Reserved. POWER-DOWN SRAM instances */ - -#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) - kPOWER_SRAM_DPWD_MASK = 0xFE6UL, /*!< Reserved. DEEP-POWER-DOWN SRAM instances (RAM_X0, RAM_02 and RAM_03 excluded: - they are used by ROM Boot code) */ -#else - kPOWER_SRAM_DPWD_MASK = 0xF3FUL, /*!< Reserved. DEEP-POWER-DOWN SRAM instances (RAM_20 & RAM_30 excluded).*/ -#endif - - /* - This enum member has no practical meaning,it is used to avoid MISRA issue, - user should not trying to use it. - */ - kPOWER_SRAM_ForceUnsigned = 0x80000000U, -} power_sram_bit_t; - -/** - * @brief SRAM instances indexes - */ -typedef enum _power_sram_index -{ - kPOWER_SRAM_IDX_RAM_X0 = 0UL, /*!< RAM_X0 */ - kPOWER_SRAM_IDX_RAM_00 = 1UL, /*!< RAM_00 */ - kPOWER_SRAM_IDX_RAM_01 = 2UL, /*!< RAM_01 */ - kPOWER_SRAM_IDX_RAM_02 = 3UL, /*!< RAM_02 */ - kPOWER_SRAM_IDX_RAM_03 = 4UL, /*!< RAM_03 */ - kPOWER_SRAM_IDX_RAM_10 = 5UL, /*!< RAM_10 */ - kPOWER_SRAM_IDX_RAM_20 = 6UL, /*!< RAM_20 */ - kPOWER_SRAM_IDX_RAM_30 = 7UL, /*!< RAM_30 */ - kPOWER_SRAM_IDX_RAM_40 = 8UL, /*!< RAM_40 */ - kPOWER_SRAM_IDX_RAM_41 = 9UL, /*!< RAM_41 */ - kPOWER_SRAM_IDX_RAM_42 = 10UL, /*!< RAM_42 */ - kPOWER_SRAM_IDX_RAM_43 = 11UL, /*!< RAM_43 */ - kPOWER_SRAM_IDX_FLASHCACHE = 12UL, /*!< Reserved. Flash Cache SRAM instance */ - kPOWER_SRAM_IDX_FLEXSPICACHE = 13UL, /*!< Reserved. FlexSPI Cache SRAM instance */ - kPOWER_SRAM_IDX_FLEXSPIH2PREG = 14UL, /*!< Reserved. FlexSPI Dual Port Register Files instances */ -} power_sram_index_t; - -/*@brief SRAM Power Mode */ -typedef enum _power_sram_pwr_mode -{ - kPOWER_SRAMPwrActive = 0U, /*!< Active */ - kPOWER_SRAMPwrLightSleep = 1U, /*!< RESERVED, DO NOT USE (Light Sleep) */ - kPOWER_SRAMPwrDeepSleep = 2U, /*!< Deep Sleep : SRAM content retained */ - kPOWER_SRAMPwrShutDown = 3U, /*!< Shutdown: SRAM content lost */ -} power_sram_pwr_mode_t; - -/*@brief BOD VDDMAIN level */ -typedef enum _power_bod_vddmain_level -{ - kPOWER_BodVddmainLevel1000mv = 0, /*!< VDDMAIN Brown out detector level 1V */ - kPOWER_BodVddmainLevel1100mv = 1, /*!< VDDMAIN Brown out detector level 1.1V */ - kPOWER_BodVddmainLevel1200mv = 2, /*!< VDDMAIN Brown out detector level 1.2V */ - kPOWER_BodVddmainLevel1300mv = 3, /*!< VDDMAIN Brown out detector level 1.3V */ - kPOWER_BodVddmainLevel1400mv = 4, /*!< VDDMAIN Brown out detector level 1.4V */ - kPOWER_BodVddmainLevel1500mv = 5, /*!< VDDMAIN Brown out detector level 1.5V */ - kPOWER_BodVddmainLevel1600mv = 6, /*!< VDDMAIN Brown out detector level 1.6V */ - kPOWER_BodVddmainLevel1650mv = 7, /*!< VDDMAIN Brown out detector level 1.65V */ - kPOWER_BodVddmainLevel1700mv = 8, /*!< VDDMAIN Brown out detector level 1.7V */ - kPOWER_BodVddmainLevel1750mv = 9, /*!< VDDMAIN Brown out detector level 1.75V */ - kPOWER_BodVddmainLevel1800mv = 10, /*!< VDDMAIN Brown out detector level 1.8V */ - kPOWER_BodVddmainLevel1900mv = 11, /*!< VDDMAIN Brown out detector level 1.9V */ - kPOWER_BodVddmainLevel2000mv = 12, /*!< VDDMAIN Brown out detector level 2V */ - kPOWER_BodVddmainLevel2100mv = 13, /*!< VDDMAIN Brown out detector level 2.1V */ - kPOWER_BodVddmainLevel2200mv = 14, /*!< VDDMAIN Brown out detector level 2.2V */ - kPOWER_BodVddmainLevel2300mv = 15, /*!< VDDMAIN Brown out detector level 2.3V */ - kPOWER_BodVddmainLevel2400mv = 16, /*!< VDDMAIN Brown out detector level 2.4V */ - kPOWER_BodVddmainLevel2500mv = 17, /*!< VDDMAIN Brown out detector level 2.5V */ - kPOWER_BodVddmainLevel2600mv = 18, /*!< VDDMAIN Brown out detector level 2.6V */ - kPOWER_BodVddmainLevel2700mv = 19, /*!< VDDMAIN Brown out detector level 2.7V */ - kPOWER_BodVddmainLevel2800mv = 20, /*!< VDDMAIN Brown out detector level 2.80 V */ - kPOWER_BodVddmainLevel2900mv = 21, /*!< VDDMAIN Brown out detector level 2.9V */ - kPOWER_BodVddmainLevel3000mv = 22, /*!< VDDMAIN Brown out detector level 3.0V */ - kPOWER_BodVddmainLevel3100mv = 23, /*!< VDDMAIN Brown out detector level 3.1V */ - kPOWER_BodVddmainLevel3200mv = 24, /*!< VDDMAIN Brown out detector level 3.2V */ - kPOWER_BodVddmainLevel3300mv = 25, /*!< VDDMAIN Brown out detector level 3.3V */ -} power_bod_vddmain_level_t; - -/*@brief BOD core level */ -typedef enum _power_bod_core_level -{ - kPOWER_BodCoreLevel600mv = 0, /*!< core Brown out detector level 600mV */ - kPOWER_BodCoreLevel650mv = 1, /*!< core Brown out detector level 650mV */ - kPOWER_BodCoreLevel700mv = 2, /*!< core Brown out detector level 700mV */ - kPOWER_BodCoreLevel750mv = 3, /*!< core Brown out detector level 750mV */ - kPOWER_BodCoreLevel800mv = 4, /*!< core Brown out detector level 800mV */ - kPOWER_BodCoreLevel850mv = 5, /*!< core Brown out detector level 850mV */ - kPOWER_BodCoreLevel900mv = 6, /*!< core Brown out detector level 900mV */ - kPOWER_BodCoreLevel950mv = 7, /*!< core Brown out detector level 950mV */ -} power_bod_core_level_t; - -/*@brief BODs (VDDMAIN & Core) Hysteresis control */ -typedef enum _power_bod_hyst -{ - kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */ - kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */ - kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */ - kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */ -} power_bod_hyst_t; - -/*@brief Core Power Source */ -typedef enum _power_core_pwr_source -{ - kPOWER_CoreSrcDCDC = 0U, /*!< DCDC */ - kPOWER_CoreSrcLDOCoreHP = 1U, /*!< LDO Core High Power Mode */ - kPOWER_CoreSrcLDOCoreLP = 2U, /*!< LDO Core Low Power Mode (DO NOT USE : Reserved for test purposes) */ - kPOWER_CoreSrcExternal = 3U, /*!< External (DO NOT USE : Reserved for test purposes) */ -} power_core_pwr_source_t; - -/*@brief Core Regulators Power State */ -typedef enum _power_core_pwr_state -{ - kPOWER_CorePwrDisable = 0U, /*!< Disable */ - kPOWER_CorePwrEnable = 1U, /*!< Enable */ -} power_core_pwr_state_t; - -/*@brief Generic Power Library APIs Status codes */ -typedef enum _power_status -{ - kPOWER_Status_Success = 0U, /*!< OK */ - kPOWER_Status_Fail = 1U, /*!< Generic error code */ -} power_status_t; - -/** - * @brief Low Power Modes Wake up sources - */ -/* Wake up source vector 0 */ -#define WAKEUP_SYS (1UL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/ -#define WAKEUP_SDMA0 (1UL << 1) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_GLOBALINT0 (1UL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_GPIO_GLOBALINT1 (1UL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_GPIO_INT0_0 (1UL << 4) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_1 (1UL << 5) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_2 (1UL << 6) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_3 (1UL << 7) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_UTICK (1UL << 8) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_MRT (1UL << 9) /*!< [SLEEP, ] */ -#define WAKEUP_CTIMER0 (1UL << 10) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CTIMER1 (1UL << 11) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SCT (1UL << 12) /*!< [SLEEP, ] */ -#define WAKEUP_CTIMER3 (1UL << 13) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM0 (1UL << 14) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM1 (1UL << 15) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM2 (1UL << 16) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM3 (1UL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_FLEXCOMM4 (1UL << 18) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM5 (1UL << 19) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM6 (1UL << 20) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM7 (1UL << 21) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_ADC0 (1UL << 22) /*!< [SLEEP, ] */ -#define WAKEUP_ADC1 (1UL << 23) /*!< [SLEEP, ] */ -#define WAKEUP_ACMP (1UL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_DMIC (1UL << 25) /*!< [SLEEP, ] */ -#define WAKEUP_HWVAD (1UL << 26) /*!< [SLEEP, DEEP SLEEP, ] */ -#define WAKEUP_USB0_NEEDCLK (1UL << 27) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_USB0 (1UL << 28) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_RTC_ALARM_WAKEUP (1UL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ -#define WAKEUP_EZH_ARCH_B (1UL << 30) /*!< [SLEEP, ] */ -#define WAKEUP_WAKEUP_MAILBOX (1UL << 31) /*!< [SLEEP, DEEP SLEEP, ] */ - -/* Wake up source vector 1 */ -#define WAKEUP_GPIO_INT0_4 (1UL << 0) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_5 (1UL << 1) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_6 (1UL << 2) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_7 (1UL << 3) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CTIMER2 (1UL << 4) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CTIMER4 (1UL << 5) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_OS_EVENT_TIMER (1UL << 6) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ -#define WAKEUP_FLEXSPI (1UL << 7) /*!< [SLEEP, ] */ -// reserved (1UL << 8) -// reserved (1UL << 9) -// reserved (1UL << 10) -#define WAKEUP_CAN0_0 (1UL << 11) /*!< [SLEEP, ] */ -#define WAKEUP_CAN0_1 (1UL << 12) /*!< [SLEEP, ] */ -#define WAKEUP_SPIFILTER (1UL << 13) /*!< [SLEEP, ] */ -// reserved (1UL << 14) -// reserved (1UL << 15) -// reserved (1UL << 16) -#define WAKEUP_SEC_HYPERVISOR_CALL (1UL << 17) /*!< [SLEEP, ] */ -#define WAKEUP_SEC_GPIO_INT0_0 (1UL << 18) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SEC_GPIO_INT0_1 (1UL << 19) /*!< [SLEEP, DEEP SLEEP ] */ -// reserved (1UL << 20) -#define WAKEUP_SEC_VIO (1UL << 21) /*!< [SLEEP, ] */ -#define WAKEUP_CSS_IRQ0 (1UL << 22) /*!< [SLEEP, ] */ -#define WAKEUP_PKC (1UL << 23) /*!< [SLEEP, ] */ -#define WAKEUP_PUF (1UL << 24) /*!< [SLEEP, ] */ -#define WAKEUP_PQ (1UL << 25) /*!< [SLEEP, ] */ -#define WAKEUP_SDMA1 (1UL << 26) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_LSPI_HS (1UL << 27) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CODE_WDG (1UL << 28) /*!< [SLEEP, ] */ -// reserved (1UL << 29) -#define WAKEUP_I3C (1UL << 30) /*!< [SLEEP, DEEP SLEEP ] */ -// reserved (1UL << 31) - -/* Wake up source vector 2 */ -#define WAKEUP_NEUTRON (1UL << 0) /*!< [SLEEP, ] */ -#define WAKEUP_CSS_IRQ1 (1UL << 1) /*!< [SLEEP, ] */ -// reserved (1UL << 2) -#define WAKEUP_ANA_GLITCH_DETECT (1UL << 3) -// reserved (1UL << 4) -// reserved (1UL << 5) -// reserved (1UL << 6) -// reserved (1UL << 7) -// reserved (1UL << 8) -// reserved (1UL << 9) -#define WAKEUP_DAC0 (1UL << 10) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_DAC1 (1UL << 11) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_DAC2 (1UL << 12) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_HS_COMP0 (1UL << 13) /*!< [SLEEP, ] */ -#define WAKEUP_HS_COMP1 (1UL << 14) /*!< [SLEEP, ] */ -#define WAKEUP_HS_COMP2 (1UL << 15) /*!< [SLEEP, ] */ -#define WAKEUP_FLEXPWM0_CAPTURE (1UL << 16) /*!< [SLEEP, ] */ -#define WAKEUP_FLEXPWM0_FAULT (1UL << 17) /*!< [SLEEP, ] */ -#define WAKEUP_FLEXPWM0_RELOAD_ERROR (1UL << 18) /*!< [SLEEP, ] */ -#define WAKEUP_FLEXPWM0_COMPARE0 (1UL << 19) /*!< [SLEEP, ] */ -#define WAKEUP_FLEXPWM0_RELOAD0 (1UL << 20) /*!< [SLEEP, ] */ -#define WAKEUP_FLEXPWM0_COMPARE1 (1UL << 21) /*!< [SLEEP, ] */ -#define WAKEUP_FLEXPWM0_RELOAD1 (1UL << 22) /*!< [SLEEP, ] */ -#define WAKEUP_FLEXPWM0_COMPARE2 (1UL << 23) /*!< [SLEEP, ] */ -#define WAKEUP_FLEXPWM0_RELOAD2 (1UL << 24) /*!< [SLEEP, ] */ -#define WAKEUP_FLEXPWM0_COMPARE3 (1UL << 25) /*!< [SLEEP, ] */ -#define WAKEUP_FLEXPWM0_RELOAD3 (1UL << 26) /*!< [SLEEP, ] */ -#define WAKEUP_FLEXPWM1_CAPTURE (1UL << 27) /*!< [SLEEP, ] */ -#define WAKEUP_FLEXPWM1_FAULT (1UL << 28) /*!< [SLEEP, ] */ -#define WAKEUP_FLEXPWM1_RELOAD_ERROR (1UL << 29) /*!< [SLEEP, ] */ -#define WAKEUP_FLEXPWM1_COMPARE0 (1UL << 30) /*!< [SLEEP, ] */ -#define WAKEUP_FLEXPWM1_RELOAD0 (1UL << 31) /*!< [SLEEP, ] */ - -/* Wake up source vector 3 */ -#define WAKEUP_FLEXPWM1_COMPARE1 (1UL << 0) /*!< [SLEEP, ] */ -#define WAKEUP_FLEXPWM1_RELOAD1 (1UL << 1) /*!< [SLEEP, ] */ -#define WAKEUP_FLEXPWM1_COMPARE2 (1UL << 2) /*!< [SLEEP, ] */ -#define WAKEUP_FLEXPWM1_RELOAD2 (1UL << 3) /*!< [SLEEP, ] */ -#define WAKEUP_FLEXPWM1_COMPARE3 (1UL << 4) /*!< [SLEEP, ] */ -#define WAKEUP_FLEXPWM1_RELOAD3 (1UL << 5) /*!< [SLEEP, ] */ -#define WAKEUP_ENC0_COMPARE (1UL << 6) /*!< [SLEEP, ] */ -#define WAKEUP_ENC0_HOME (1UL << 7) /*!< [SLEEP, ] */ -#define WAKEUP_ENC0_WDG (1UL << 8) /*!< [SLEEP, ] */ -#define WAKEUP_ENC0_IDX (1UL << 9) /*!< [SLEEP, ] */ -#define WAKEUP_ENC1_COMPARE (1UL << 10) /*!< [SLEEP, ] */ -#define WAKEUP_ENC1_HOME (1UL << 11) /*!< [SLEEP, ] */ -#define WAKEUP_ENC1_WDG (1UL << 12) /*!< [SLEEP, ] */ -#define WAKEUP_ENC1_IDX (1UL << 13) /*!< [SLEEP, ] */ -#define WAKEUP_ITRC (1UL << 14) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_CF_DSP24L_IRQ0 (1UL << 15) /*!< [SLEEP, ] */ -#define WAKEUP_CF_DSP24L_IRQ1 (1UL << 16) /*!< [SLEEP, ] */ -#define WAKEUP_FTM0 (1UL << 17) /*!< [SLEEP, ] */ -// reserved (1UL << 18) -// reserved (1UL << 19) -// reserved (1UL << 20) -// reserved (1UL << 21) -// reserved (1UL << 22) -// reserved (1UL << 23) -// reserved (1UL << 24) -// reserved (1UL << 25) -// reserved (1UL << 26) -// reserved (1UL << 27) -// reserved (1UL << 28) -// reserved (1UL << 29) -// reserved (1UL << 30) -// reserved (1UL << 31) - -/** - * @brief Sleep Postpone (DEEP-SLEEP) - */ -#define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */ -#define LOWPOWER_HWWAKE_PERIPHERALS \ - (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause \ - peripheral clocking to wake up temporarily while the related status is asserted */ -#define LOWPOWER_HWWAKE_DMIC \ - (1UL << 2) /*!< Wake for DMIC. DMIC being busy will cause peripheral clocking to remain running until DMIC \ - completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ -#define LOWPOWER_HWWAKE_SDMA0 \ - (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA \ - completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS or LOWPOWER_HWWAKE_DAC */ -#define LOWPOWER_HWWAKE_SDMA1 \ - (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA \ - completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS or LOWPOWER_HWWAKE_DAC */ -#define LOWPOWER_HWWAKE_DAC \ - (1UL << 6) /*!< Wake for DAC0, DAC1, DAC2. Any DAC0/1/2 FIFO reaching the level specified by the configuration \ - will generate an asynchronous SDMA0 request, and SDMA0 will wake up the bus \ - clock temporarily to transfer data to DAC0/1/2.*/ -#define LOWPOWER_HWWAKE_ENABLE_FRO192M \ - (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of \ - LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0, LOWPOWER_HWWAKE_SDMA1 or LOWPOWER_HWWAKE_DAC is \ - set */ - -/** - * @brief CPU State retention (POWER-DOWN) - */ -#define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */ -#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */ - -/** - * @brief Wake up I/O sources (DEEP POWER-DOWN) - */ -#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */ -#define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */ -#define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */ -#define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */ -#define LOWPOWER_WAKEUPIOSRC_PIO4_INDEX 8 /*!< Pin P0(26) */ - -#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */ -#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */ -#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */ -#define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */ - -#define LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX 10 /*!< Pin P1( 1) */ -#define LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX 12 /*!< Pin P0(28) */ -#define LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX 14 /*!< Pin P1(18) */ -#define LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX 16 /*!< Pin P1(30) */ -#define LOWPOWER_WAKEUPIOSRC_PIO4MODE_INDEX 18 /*!< Pin P0(26) */ - -#define LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN 0 /*!< Wake up Pad is plain input */ -#define LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN 1 /*!< Wake up Pad is pull-down */ -#define LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP 2 /*!< Wake up Pad is pull-up */ -#define LOWPOWER_WAKEUPIOSRC_IO_MODE_REPEATER 3 /*!< Wake up Pad is in repeater */ - -#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX \ - 20 /*!< Wake-up I/O 0 pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX \ - 21 /*!< Wake-up I/O 1 pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX \ - 22 /*!< Wake-up I/O 2 pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX \ - 23 /*!< Wake-up I/O 3 pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO4_DISABLEPULLUPDOWN_INDEX \ - 24 /*!< Wake-up I/O 4 pull-up/down disable/enable control index */ - -#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down disable/enable mask */ -#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down disable/enable mask */ -#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down disable/enable mask */ -#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down disable/enable mask */ -#define LOWPOWER_WAKEUPIO_PIO4_DISABLEPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO4_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 4 pull-up/down disable/enable mask */ - -#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX 25 /*!< Wake-up I/O 0 pull-up/down configuration index */ -#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX 26 /*!< Wake-up I/O 1 pull-up/down configuration index */ -#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX 27 /*!< Wake-up I/O 2 pull-up/down configuration index */ -#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX 28 /*!< Wake-up I/O 3 pull-up/down configuration index */ -#define LOWPOWER_WAKEUPIO_PIO4_PULLUPDOWN_INDEX 29 /*!< Wake-up I/O 4 pull-up/down configuration index */ - -#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down mask */ -#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down mask */ -#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down mask */ -#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down mask */ -#define LOWPOWER_WAKEUPIO_PIO4_PULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO4_PULLUPDOWN_INDEX) /*!< Wake-up I/O 4 pull-up/down mask */ - -#define LOWPOWER_WAKEUPIO_PULLDOWN 0 /*!< Select pull-down */ -#define LOWPOWER_WAKEUPIO_PULLUP 1 /*!< Select pull-up */ - -#define LOWPOWER_WAKEUPIO_CFG_SRC_IOCON \ - 0 /*!< Wake-up pins configuration (in/out, pull up/down plain input ...) is coming from IOCON (valid for \ - DEEP-SLEEP and POWER-DOWN) */ -#define LOWPOWER_WAKEUPIO_CFG_SRC_PMC \ - 1 /*!< Wake-up pins configuration (in/out, pull up/down plain input ...) is coming from PMC and set up via \ - the second parameter (wakeup_io_ctrl) of POWER_SetWakeUpPins API (valid for DEEP-SLEEP and POWER-DOWN) */ - -#ifdef __cplusplus -extern "C" { -#endif -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral - * - * @param en peripheral for which to enable the PDRUNCFG bit - * @return none - */ -static inline void POWER_EnablePD(pd_bit_t en) -{ - if (((en & (1UL << 31)) != 0UL) && (en != (1UL << 31))) - { - /* PDRUNCFGSET1 */ - PMC->PDRUNCFGSET1 = (uint32_t)(en & ~(1UL << 31)); - } - else - { - /* PDRUNCFGSET0 */ - PMC->PDRUNCFGSET0 = (uint32_t)en; - } -} - -/*! - * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral - * - * @param en peripheral for which to disable the PDRUNCFG bit - * @return none - */ -static inline void POWER_DisablePD(pd_bit_t en) -{ - if (((en & (1UL << 31)) != 0UL) && (en != (1UL << 31))) - { - /* PDRUNCFGCLR1 */ - PMC->PDRUNCFGCLR1 = (uint32_t)(en & ~(1UL << 31)); - } - else - { - /* PDRUNCFGCLR0 */ - PMC->PDRUNCFGCLR0 = (uint32_t)en; - } -} - -/** - * @brief SoC Power Management Controller initialization - * @return power_status_t - */ -power_status_t POWER_PowerInit(void); - -/** - * @brief Selects the core logic supply source - * @param pwr_source : Defines which regulator will be used to power the part core logic (internally) - * @return power_status_t - */ -power_status_t POWER_SetCorePowerSource(power_core_pwr_source_t pwr_source); - -/** - * @brief Returns the current core logic supply source. - * @return power_core_pwr_source_t - */ -power_core_pwr_source_t POWER_GetCorePowerSource(void); - -/** - * @brief Allows to control the state (enabled or disabled) of the core logic internal regulators (DCDC, LDO_CORE) - * @param pwr_source : Defines which regulator will be enabled or disabled - * @param pwr_state : Defines the state of the internal regulator indicated by pwr_source - * @return power_status_t - */ -power_status_t POWER_CorePowerSourceControl(power_core_pwr_source_t pwr_source, power_core_pwr_state_t pwr_state); - -/** - * @brief Allows to configure SRAM instances (low) power modes when the part is in ACTIVE mode. - * @param sram_inst : Defines the SRAM instance(s) to be configured. - * @param pwr_mode : Defines the SRAM low power mode to be applied to all SRAM instances given by sram_inst - * @return power_status_t - */ -power_status_t POWER_SRAMPowerModeControl(power_sram_bit_t sram_inst, power_sram_pwr_mode_t pwr_mode); - -/** - * @brief - * @param p_sram_index : - * @return power_sram_pwr_mode_t - */ -power_sram_pwr_mode_t POWER_GetSRAMPowerMode(power_sram_index_t sram_index); - -/** - * @brief Configures and enters in SLEEP low power mode - * @return Nothing - */ -void POWER_EnterSleep(void); - -/** - * @brief Configures and enters in DEEP-SLEEP low power mode - * @param exclude_from_pd: defines which analog peripherals shall NOT be powered down (it is a 2 x 32-bit vectors, - aligned with "pd_bit_t" definition) - * @param sram_retention_ctrl:defines which SRAM instances will be put in "retention" mode during deep-sleep (aligned - with "power_sram_bit_t" definition) - * @param wakeup_interrupts: defines which peripheral interrupts can be a wake-up source during deep-sleep (it is a 4 - x 32-bit vectors, aligned with "WAKEUP_" #defines) - * @param hardware_wake_ctrl: configure DMA services during deep-sleep without waking up entire device (see - "LOWPOWER_HWWAKE_*" #defines). - - * @return Nothing - * - * !!! IMPORTANT NOTES : - * 1 - CPU & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. - */ -void POWER_EnterDeepSleep(uint32_t exclude_from_pd[2], - uint32_t sram_retention_ctrl, - uint32_t wakeup_interrupts[4], - uint32_t hardware_wake_ctrl); - -/** - * @brief Configures and enters in POWERDOWN low power mode - * @param exclude_from_pd: defines which analog peripherals shall NOT be powered down (it is a 1 x 32-bit vector, - aligned with "pd_bit_t" definition) - * @param sram_retention_ctrl:defines which SRAM instances will be put in "retention" mode during power-down (aligned - with "power_sram_bit_t" definition) - * @param wakeup_interrupts: defines which peripheral interrupts can be a wake-up source during power-down (it is a 2 - x 32-bit vectors, aligned with "WAKEUP_" #defines) - * @param cpu_retention_addr: Must be: - - Word aligned (address ending by 0x0, 0x4, 0x8 and 0xC). - - Between 0x2000_0000 and 0x2000_09FC (inside RAM_00) or - - Between 0x2000_1000 and 0x2000_19FC (inside RAM_01) or - - Between 0x2000_2000 and 0x2000_29FC (inside RAM_02) or - - Between 0x2000_3000 and 0x2000_39FC (inside RAM_03) - - The CPU state will be stored in SRAM from "cpu_retention_addr" to "cpu_retention_addr + 1540". - Therefore, any data present in this area before calling the function will be lost. - - * @return Nothing - * - * !!! IMPORTANT NOTES : - * 1 - CPU0 & System Clock frequency is switched to FRO12MHz and is NOT restored back by the API. - * 2 - It is the responsability of the user to make sure that SRAM instance containing the application - * software stack and variables WILL BE preserved during low power (via parameter "sram_retention_ctrl") - */ -void POWER_EnterPowerDown(uint32_t exclude_from_pd[1], - uint32_t sram_retention_ctrl, - uint32_t wakeup_interrupts[4], - uint32_t cpu_retention_addr); - -/** - * @brief Configures and enters in DEEPPOWERDOWN low power mode - * @param exclude_from_pd: defines which analog peripherals shall NOT be powered down (it is a 1 x 32-bit vector, - aligned with "pd_bit_t" definition) - * @param sram_retention_ctrl: defines which SRAM instances will be put in "retention" mode during deep power-down - (aligned with "power_sram_bit_t" definition) - * @param wakeup_interrupts: defines which peripheral interrupts can be a wake-up source during deep power-down (it is - a 2 x 32-bit vectors, aligned with "WAKEUP_" #defines) - * @param wakeup_io_ctrl: configure the 5 wake-up pins that can wake-up the part from deep power-down mode (see - "LOWPOWER_WAKEUPIOSRC_*" #defines) - - * @return Nothing - * - * !!! IMPORTANT NOTES : - * 1 - CPU0 & System Clock frequency is switched to FRO12MHz and is NOT restored back by the API. - * 2 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip - reset) - */ -void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd[1], - uint32_t sram_retention_ctrl, - uint32_t wakeup_interrupts[2], - uint32_t wakeup_io_ctrl); - -/** - * @brief Configures the 5 wake-up pins to wake up the part in DEEP-SLEEP and POWER-DOWN low power modes. - * @param wakeup_io_cfg_src : for all wake-up pins : indicates if the config is from IOCON (0) or from PMC (1). - * @param wakeup_io_ctrl: the 5 wake-up pins configurations (see "LOWPOWER_WAKEUPIOSRC_*" #defines) - - * @return Nothing - * - * !!! IMPORTANT NOTES : - * 1 - To be called just before POWER_EnterDeepSleep() or POWER_EnterPowerDown(). - */ -void POWER_SetWakeUpPins(uint32_t wakeup_io_cfg_src, uint32_t wakeup_io_ctrl); - -/** - * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes. - * @param reset_cause : the device reset cause, according to the definition of power_reset_cause_t type. - * @param boot_mode : the device boot mode, according to the definition of power_boot_mode_t type. - * @param wakeup_pin_cause: the wake-up pin sources, according to the definition of power_wakeup_pin_t type. - - * @return Nothing - * - */ -void POWER_GetWakeUpCause(power_reset_cause_t *reset_cause, - power_boot_mode_t *boot_mode, - power_wakeup_pin_t *wakeup_pin_cause); - -/** - * @brief Configures the device internal power control settings - * @param system_freq_hz: operating frequency required (in Hertz). - * @return Nothing - * - * prepare on-chip power regulators (DC-DC Converter / Core and Always-on - * Low Drop-Out regulators) to deliver the amount of power needed for the - * requested performance level, as defined by the CPU operating frequency. - */ -void POWER_SetVoltageForFreq(uint32_t system_freq_hz); - -#ifdef __cplusplus -} -#endif - -#endif /* _FSL_POWER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_puf_v3.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_puf_v3.c deleted file mode 100644 index d5c457a553e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_puf_v3.c +++ /dev/null @@ -1,929 +0,0 @@ -/* - * Copyright 2020 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#include "fsl_puf_v3.h" -#include "fsl_clock.h" -#include "fsl_reset.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.puf_v3" -#endif - -#define kPUF_OperationInProgress (0x0u) -#define kPUF_Enroll (0x1u) -#define kPUF_Start (0x2u) -#define kPUF_Stop (0x5u) -#define kPUF_GetKey (0x6u) -#define kPUF_Unwrap (0x7u) -#define kPUF_WrapGeneratedRandom (0x8u) -#define kPUF_Wrap (0x9u) -#define kPUF_GenerateRandom (0xfu) -#define kPUF_Test (0x1fu) -#define kPUF_Init (0x20u) -#define kPUF_Zeroize (0x2fu) -typedef uint32_t puf_last_operation_t; - -#define PUF_KEY_OPERATION_CONTEXT_TYPE (0x10 << 16) -#define PUF_CONTEXT_GENERIC_KEY_TYPE (0x0u) -#define PUF_CONTEXT_KEY_LEN_MASK (0x1fffu) - -/******************************************************************************* - * Code - ******************************************************************************/ - -static status_t puf_waitForInit(PUF_Type *base) -{ - status_t status = kStatus_Fail; - - /* wait until status register reads non-zero. All zero is not valid. It should be BUSY or OK or ERROR */ - while (0u == base->SR) - { - } - - /* wait if busy */ - while ((base->SR & PUF_SR_BUSY_MASK) != 0u) - { - } - - /* return status */ - if (base->SR & (PUF_SR_OK_MASK | PUF_SR_ERROR_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -static void puf_powerOn(PUF_Type *base, puf_config_t *conf) -{ - /* Power On PUF SRAM */ - base->SRAM_CFG = 0x1u; - while (0u == (PUF_SRAM_STATUS_READY_MASK & base->SRAM_STATUS)) - { - } -} - -static status_t puf_powerCycle(PUF_Type *base, puf_config_t *conf) -{ - /* Power off */ - base->SRAM_CFG = 0x0u; - - /* Reset PUF and reenable power to PUF SRAM */ - RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); - puf_powerOn(base, conf); - - return kStatus_Success; -} - -static status_t puf_makeStatus(PUF_Type *base, puf_last_operation_t operation) -{ - uint32_t result; - status_t status = kStatus_Fail; - - if (((base->ORR & PUF_ORR_LAST_OPERATION_MASK) >> PUF_ORR_LAST_OPERATION_SHIFT) == operation) - { - result = (base->ORR & PUF_ORR_RESULT_CODE_MASK); - if ((result == kPUF_ResultOK) && (0u == (base->SR & PUF_SR_ERROR_MASK))) - { - status = kStatus_Success; - } - else - { - status = MAKE_STATUS(kStatusGroup_PUF, result); - } - } - - return status; -} - -/*! - * brief Sets the default configuration of PUF - * - * This function initialize PUF config structure to default values. - * - * @param conf PUF configuration structure - */ -void PUF_GetDefaultConfig(puf_config_t *conf) -{ - /* Default configuration after reset */ - conf->dataEndianness = kPUF_EndianBig; - conf->CKGATING = 0U; -} - -/*! - * brief Initialize PUF - * - * This function enables power to PUF block and waits until the block initializes. - * - * @param conf PUF configuration structure - * @return Status of the init operation - */ -status_t PUF_Init(PUF_Type *base, puf_config_t *conf) -{ - status_t status = kStatus_Fail; - - /* Enable PUF clock */ - CLOCK_EnableClock(kCLOCK_Puf); - /* Reset PUF */ - RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); - - /* Set configuration from SRAM */ - base->SRAM_CFG |= PUF_SRAM_CFG_CKGATING(conf->CKGATING); - - /* Enable power to PUF SRAM */ - puf_powerOn(base, conf); - - /* Wait for peripheral to become ready */ - status = puf_waitForInit(base); - - /* In case of error or enroll & start not allowed, do power-cycle */ - if ((status != kStatus_Success) || ((PUF_AR_ALLOW_ENROLL_MASK | PUF_AR_ALLOW_START_MASK) != - (base->AR & (PUF_AR_ALLOW_ENROLL_MASK | PUF_AR_ALLOW_START_MASK)))) - { - puf_powerCycle(base, conf); - status = puf_waitForInit(base); - } - - if (kStatus_Success == status) - { - /* Set data endianness */ - base->MISC = PUF_MISC_DATA_ENDIANNESS(conf->dataEndianness); - - /* get status */ - status = puf_makeStatus(base, kPUF_Init); - } - - return status; -} - -/*! - * brief Denitialize PUF - * - * This function disables power to PUF SRAM and peripheral clock. - * - * @param base PUF peripheral base address - * @param conf PUF configuration structure - */ -void PUF_Deinit(PUF_Type *base, puf_config_t *conf) -{ - base->SRAM_CFG = 0x0u; - - RESET_SetPeripheralReset(kPUF_RST_SHIFT_RSTn); - CLOCK_DisableClock(kCLOCK_Puf); -} - -/*! - * brief Enroll PUF - * - * This function derives a digital fingerprint, generates the corresponding Activation Code (AC) - * and returns it to be stored in an NVM or a file. This step needs to be - * performed only once for each device. This function may be permanently disallowed by a fuse. - * - * @param base PUF peripheral base address - * @param[out] activationCode Word aligned address of the resulting activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 996 bytes. - * @param score Value of the PUF Score that was obtained during the enroll operation. - * @return Status of enroll operation. - */ -status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize, uint8_t *score) -{ - status_t status = kStatus_Fail; - uint32_t *activationCodeAligned = NULL; - register uint32_t temp32 = 0; - - /* check that activation code buffer size is at least 996 bytes */ - if (activationCodeSize < PUF_ACTIVATION_CODE_SIZE) - { - return kStatus_InvalidArgument; - } - - /* only work with aligned and valid activationCode */ - if ((0x3u & (uintptr_t)activationCode) || (activationCode == NULL)) - { - return kStatus_InvalidArgument; - } - - activationCodeAligned = (uint32_t *)(uintptr_t)activationCode; - - /* check if ENROLL is allowed */ - if (0x0u == (base->AR & PUF_AR_ALLOW_ENROLL_MASK)) - { - return kStatus_PUF_OperationNotAllowed; - } - - /* begin */ - base->CR = PUF_CR_ENROLL_MASK; - - /* wait till command is accepted */ - while (0u != (base->CR & PUF_CR_ENROLL_MASK)) - { - } - - /* read out AC */ - while (0u != (base->SR & PUF_SR_BUSY_MASK)) - { - if (0u != (PUF_SR_DO_REQUEST_MASK & base->SR)) - { - temp32 = base->DOR; - if (activationCodeSize >= sizeof(uint32_t)) - { - *activationCodeAligned = temp32; - activationCodeAligned++; - activationCodeSize -= sizeof(uint32_t); - } - } - } - - /* In case of success fill in score */ - if ((0u != (base->SR & PUF_SR_OK_MASK)) && (score != NULL)) - { - *score = (uint8_t)(base->PSR & PUF_PSR_PUF_SCORE_MASK); - } - - /* get status */ - status = puf_makeStatus(base, kPUF_Enroll); - - return status; -} - -/*! - * brief Start PUF - * - * The Activation Code generated during the Enroll operation is used to - * reconstruct the digital fingerprint. This needs to be done after every power-up - * and reset. - * - * @param base PUF peripheral base address - * @param[in] activationCode Word aligned address of the input activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 996 bytes. - * @param score Value of the PUF Score that was obtained during the start operation. - * return Status of start operation. - */ -status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize, uint8_t *score) -{ - status_t status = kStatus_Fail; - const uint32_t *activationCodeAligned = NULL; - register uint32_t temp32 = 0; - - /* check that activation code size is at least 996 bytes */ - if (activationCodeSize < PUF_ACTIVATION_CODE_SIZE) - { - return kStatus_InvalidArgument; - } - - /* Set activationCodeSize to 996 bytes */ - activationCodeSize = PUF_ACTIVATION_CODE_SIZE; - - /* only work with aligned activationCode */ - if (0x3u & (uintptr_t)activationCode) - { - return kStatus_InvalidArgument; - } - - activationCodeAligned = (const uint32_t *)(uintptr_t)activationCode; - - /* check if START is allowed */ - if (0x0u == (base->AR & PUF_AR_ALLOW_START_MASK)) - { - return kStatus_PUF_OperationNotAllowed; - } - - /* begin */ - base->CR = PUF_CR_START_MASK; - - /* wait till command is accepted */ - while (0u != (base->CR & PUF_CR_START_MASK)) - { - } - - /* while busy send AC */ - while (0u != (base->SR & PUF_SR_BUSY_MASK)) - { - if (0u != (PUF_SR_DI_REQUEST_MASK & base->SR)) - { - if (activationCodeSize >= sizeof(uint32_t)) - { - temp32 = *activationCodeAligned; - activationCodeAligned++; - activationCodeSize -= sizeof(uint32_t); - } - /* Send AC again */ - else - { - activationCodeAligned = (const uint32_t *)(uintptr_t)activationCode; - temp32 = *activationCodeAligned; - activationCodeAligned++; - activationCodeSize = PUF_ACTIVATION_CODE_SIZE - sizeof(uint32_t); - } - base->DIR = temp32; - } - } - - /* In case of success fill in score */ - if ((0u != (base->SR & PUF_SR_OK_MASK)) && (score != NULL)) - { - *score = (uint8_t)(base->PSR & PUF_PSR_PUF_SCORE_MASK); - } - - /* get status */ - status = puf_makeStatus(base, kPUF_Start); - - return status; -} - -/*! - * brief Stop PUF - * - * The Stop operation removes all key material from PUF flipflops and PUF SRAM, and sets - * PUF to the Stopped state. - * - * @param base PUF peripheral base address - * @return Status of stop operation. - */ -status_t PUF_Stop(PUF_Type *base) -{ - status_t status = kStatus_Fail; - - /* check if STOP is allowed */ - if (0x0u == (base->AR & PUF_AR_ALLOW_STOP_MASK)) - { - return kStatus_PUF_OperationNotAllowed; - } - - /* begin */ - base->CR = PUF_CR_STOP_MASK; - - /* wait till command is accepted */ - while (0u != (base->CR & PUF_CR_STOP_MASK)) - { - } - - /* wait while busy */ - while (0u != (base->SR & PUF_SR_BUSY_MASK)) - { - } - - /* get status */ - status = puf_makeStatus(base, kPUF_Stop); - - return status; -} - -/*! - * brief PUF Get Key - * - * The Get Key operation derives a key from the intrinsic PUF key and externally provided context. - * - * @param base PUF peripheral base address - * @param keyCtx PUF key context struct - * @param keyDest output destination of the derived PUF key - * @param[out] key Word aligned address of output key (only used when kPUF_KeyDestRegister). - * @param keySize Size of the derived key in bytes. - * @return Status of get key operation. - */ -status_t PUF_GetKey(PUF_Type *base, puf_key_ctx_t *keyCtx, puf_key_dest_t keyDest, uint8_t *key, size_t keySize) -{ - uint8_t idx = 0; - uint32_t *keyAligned = NULL; - uint32_t context[4] = {0}; - status_t status = kStatus_Fail; - - /* check if GET KEY is allowed */ - if (0x0u == (base->AR & PUF_AR_ALLOW_GET_KEY_MASK)) - { - return kStatus_PUF_OperationNotAllowed; - } - - /* check for key context */ - if (keyCtx == NULL) - { - return kStatus_InvalidArgument; - } - - /* check for valid key destination */ - if (((keyDest == kPUF_KeyDestRegister) && (key == NULL)) || (keyDest == kPUF_KeyDestInvalid)) - { - return kStatus_InvalidArgument; - } - - /* check for valid key size. */ - /* must be 8byte multiple */ - if (keySize & 0x7u) - { - return kStatus_InvalidArgument; - } - /* if keySize > 128bytes, it must be equal to 256bytes or 384bytes or 512bytes */ - else if ((keySize > 128u) && !((keySize == 256u) || (keySize == 384u) || (keySize == 512u))) - { - return kStatus_InvalidArgument; - } - - /* only work with aligned key */ - if (0x3u & (uintptr_t)key) - { - return kStatus_InvalidArgument; - } - - keyAligned = (uint32_t *)(uintptr_t)key; - - /* fill in key context */ - context[0] = PUF_KEY_OPERATION_CONTEXT_TYPE | ((keySize * 8u) & PUF_CONTEXT_KEY_LEN_MASK); - context[1] = PUF_CONTEXT_GENERIC_KEY_TYPE | (keyCtx->keyScopeStarted << 8u) | keyCtx->keyScopeEnrolled; - context[2] = keyCtx->userCtx0; - context[3] = keyCtx->userCtx1; - - /* set key destination */ - base->KEY_DEST = keyDest; - - /* begin */ - base->CR = PUF_CR_GET_KEY_MASK; - - /* wait till command is accepted */ - while (0u != (base->CR & PUF_CR_GET_KEY_MASK)) - { - } - - /* send context and read output data while busy */ - while (0 != (base->SR & PUF_SR_BUSY_MASK)) - { - if ((0 != (PUF_SR_DI_REQUEST_MASK & base->SR)) && (idx < 4u)) - { - base->DIR = context[idx]; - idx++; - } - - if ((0 != (PUF_SR_DO_REQUEST_MASK & base->SR)) && (kPUF_KeyDestRegister == keyDest)) - { - if (keySize >= sizeof(uint32_t)) - { - *keyAligned = base->DOR; - keyAligned++; - keySize -= sizeof(uint32_t); - } - } - } - - /* get status */ - status = puf_makeStatus(base, kPUF_GetKey); - - return status; -} - -/*! - * brief PUF Wrap generated random - * - * The Wrap Generated Random operation wraps a random key into a Key Code (KC). - * - * @param base PUF peripheral base address - * @param keyCtx PUF key context struct - * @param keySize Size of the key to be generated in bytes. - * @param[out] keyCode Word aligned address of the resulting key code. - * @param keyCodeSize Size of the output keycode in bytes. - * @return Status of wrap generated random operation. - */ -status_t PUF_WrapGeneratedRandom( - PUF_Type *base, puf_key_ctx_t *keyCtx, size_t keySize, uint8_t *keyCode, size_t keyCodeSize) -{ - uint8_t idx = 0; - uint32_t *keyCodeAligned = NULL; - uint32_t context[4] = {0}; - status_t status = kStatus_Fail; - - /* check if WRAP GENERATED RANDOM is allowed */ - if (0x0u == (base->AR & PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_MASK)) - { - return kStatus_PUF_OperationNotAllowed; - } - - /* check for valid key context and keyCode buffer */ - if ((keyCtx == NULL) || (keyCode == NULL)) - { - return kStatus_InvalidArgument; - } - - /* check for valid key size. */ - /* must be 8byte multiple */ - if (keySize & 0x7u) - { - return kStatus_InvalidArgument; - } - /* if keySize > 128bytes, it must be equal to 256bytes or 384bytes or 512bytes */ - else if ((keySize > 128u) && !((keySize == 256u) || (keySize == 384u) || (keySize == 512u))) - { - return kStatus_InvalidArgument; - } - - /* check that keyCodeSize is correct for given keySize */ - if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize)) - { - return kStatus_InvalidArgument; - } - - /* only work with aligned key code */ - if (0x3u & (uintptr_t)keyCode) - { - return kStatus_InvalidArgument; - } - - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - - /* fill in key context */ - context[0] = PUF_KEY_OPERATION_CONTEXT_TYPE | ((keySize * 8u) & 0x1FFF); - context[1] = PUF_CONTEXT_GENERIC_KEY_TYPE | (keyCtx->keyScopeStarted << 8u) | keyCtx->keyScopeEnrolled; - context[2] = keyCtx->userCtx0; - context[3] = keyCtx->userCtx1; - - /* begin */ - base->CR = PUF_CR_WRAP_GENERATED_RANDOM_MASK; - - /* wait till command is accepted */ - while (0u != (base->CR & PUF_CR_WRAP_GENERATED_RANDOM_MASK)) - { - } - - /* send context and read output data while busy */ - while (0u != (base->SR & PUF_SR_BUSY_MASK)) - { - if ((0u != (PUF_SR_DI_REQUEST_MASK & base->SR)) && (idx < 4u)) - { - base->DIR = context[idx]; - idx++; - } - - if (0u != (PUF_SR_DO_REQUEST_MASK & base->SR)) - { - if (keyCodeSize >= sizeof(uint32_t)) - { - *keyCodeAligned = base->DOR; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - } - } - - /* get status */ - status = puf_makeStatus(base, kPUF_WrapGeneratedRandom); - - return status; -} - -/*! - * brief PUF Wrap user key - * - * The Wrap operation wraps a user defined key into a Key Code (KC). - * - * @param base PUF peripheral base address - * @param keyCtx PUF key context struct. - * @param userKey Word aligned address of input user key. - * @param userKeySize Size of the key to be wrapped in bytes. - * @param[out] keyCode Word aligned address of the resulting key code. - * @param keyCodeSize Size of the output keycode in bytes. - * @return Status of wrap operation. - */ -status_t PUF_Wrap( - PUF_Type *base, puf_key_ctx_t *keyCtx, uint8_t *userKey, size_t userKeySize, uint8_t *keyCode, size_t keyCodeSize) -{ - uint8_t ctxIdx = 0; - uint32_t *userKeyAligned = NULL; - uint32_t *keyCodeAligned = NULL; - uint32_t context[4] = {0}; - status_t status = kStatus_Fail; - - /* check if WRAP is allowed */ - if (0x0u == (base->AR & PUF_AR_ALLOW_WRAP_MASK)) - { - return kStatus_PUF_OperationNotAllowed; - } - - /* check for valid keyCtx and keyCode pointers */ - if ((keyCtx == NULL) || (keyCode == NULL)) - { - return kStatus_InvalidArgument; - } - - /* check for valid userKey size. */ - /* must be 8byte multiple */ - if (userKeySize & 0x7u) - { - return kStatus_InvalidArgument; - } - /* if userKeySize > 128bytes, it must be equal to 256bytes or 384bytes or 512bytes */ - else if ((userKeySize > 128u) && !((userKeySize == 256u) || (userKeySize == 384u) || (userKeySize == 512u))) - { - return kStatus_InvalidArgument; - } - - /* check that keyCodeSize is correct for given userKeySize */ - if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize)) - { - return kStatus_InvalidArgument; - } - - /* only work with aligned userKey and key code */ - if ((0x3u & (uintptr_t)userKey) || (0x3u & (uintptr_t)keyCode)) - { - return kStatus_InvalidArgument; - } - - userKeyAligned = (uint32_t *)(uintptr_t)userKey; - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - - /* fill in key context */ - context[0] = PUF_KEY_OPERATION_CONTEXT_TYPE | ((userKeySize * 8u) & 0x1FFF); - context[1] = PUF_CONTEXT_GENERIC_KEY_TYPE | (keyCtx->keyScopeStarted << 8u) | keyCtx->keyScopeEnrolled; - context[2] = keyCtx->userCtx0; - context[3] = keyCtx->userCtx1; - - /* begin */ - base->CR = PUF_CR_WRAP_MASK; - - /* wait till command is accepted */ - while (0u != (base->CR & PUF_CR_WRAP_MASK)) - { - } - - /* send context and read output data while busy */ - while (0u != (base->SR & PUF_SR_BUSY_MASK)) - { - if (0u != (PUF_SR_DI_REQUEST_MASK & base->SR)) - { - /* send context first */ - if (ctxIdx < 4u) - { - base->DIR = context[ctxIdx]; - ctxIdx++; - } - /* send userKey */ - else - { - base->DIR = *userKeyAligned; - userKeyAligned++; - } - } - - if (0u != (PUF_SR_DO_REQUEST_MASK & base->SR)) - { - if (keyCodeSize >= sizeof(uint32_t)) - { - *keyCodeAligned = base->DOR; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - } - } - - /* get status */ - status = puf_makeStatus(base, kPUF_Wrap); - - return status; -} - -/*! - * brief PUF Unwrap user key - * - * The unwrap operation unwraps the key from a previously created Key Code (KC) - * - * @param base PUF peripheral base address - * @param keyDest output destination of the unwraped PUF key - * @param[in] keyCode Word aligned address of the input key code. - * @param keyCodeSize Size of the input keycode in bytes. - * @param key Word aligned address of output key (only used when kPUF_KeyDestRegister). - * @param keySize Size of the key to be generated in bytes. - * @return Status of unwrap operation. - */ -status_t PUF_Unwrap( - PUF_Type *base, puf_key_dest_t keyDest, uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize) -{ - uint32_t *keyAligned = NULL; - uint32_t *keyCodeAligned = NULL; - status_t status = kStatus_Fail; - - /* check if UNWRAP is allowed */ - if (0x0u == (base->AR & PUF_AR_ALLOW_UNWRAP_MASK)) - { - return kStatus_PUF_OperationNotAllowed; - } - - /* check for valid key destination */ - if (((keyDest == kPUF_KeyDestRegister) && (key == NULL)) || (keyDest == kPUF_KeyDestInvalid)) - { - return kStatus_InvalidArgument; - } - - /* only work with aligned key and key code */ - if ((0x3u & (uintptr_t)key) || (0x3u & (uintptr_t)keyCode)) - { - return kStatus_InvalidArgument; - } - - keyAligned = (uint32_t *)(uintptr_t)key; - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - - /* set key destination */ - base->KEY_DEST = keyDest; - - /* begin */ - base->CR = PUF_CR_UNWRAP_MASK; - - /* wait till command is accepted */ - while (0u != (base->CR & PUF_CR_UNWRAP_MASK)) - { - } - - /* send context and read output data while busy */ - while (0u != (base->SR & PUF_SR_BUSY_MASK)) - { - if (0u != (PUF_SR_DI_REQUEST_MASK & base->SR)) - { - if (keyCodeSize >= sizeof(uint32_t)) - { - base->DIR = *keyCodeAligned; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - } - - if (0u != (PUF_SR_DO_REQUEST_MASK & base->SR)) - { - if (keySize >= sizeof(uint32_t)) - { - *keyAligned = base->DOR; - keyAligned++; - keySize -= sizeof(uint32_t); - } - } - } - - /* get status */ - status = puf_makeStatus(base, kPUF_Unwrap); - - return status; -} - -/*! - * brief Generate Random - * - * The Generate Random operation outputs the requested amount of random data as specified in a - * provided context. - * - * @param base PUF peripheral base address - * @param size Size of random data to be genarated in bytes. - * @return Status of generate random operation. - */ -status_t PUF_GenerateRandom(PUF_Type *base, uint8_t *data, size_t size) -{ - uint32_t context; - uint32_t *dataAligned = NULL; - status_t status = kStatus_Fail; - - if (data == NULL) - { - return kStatus_InvalidArgument; - } - - /* check if Generate random is allowed */ - if (0u == (base->AR & PUF_AR_ALLOW_GENERATE_RANDOM_MASK)) - { - return kStatus_PUF_OperationNotAllowed; - } - - /* check for valid size. */ - /* must be 8byte multiple */ - if (size & 0x7u) - { - return kStatus_InvalidArgument; - } - /* if size > 128bytes, it must be equal to 256bytes or 384bytes or 512bytes */ - else if ((size > 128u) && !((size == 256u) || (size == 384u) || (size == 512u))) - { - return kStatus_InvalidArgument; - } - - /* only work with aligned data buffer */ - if (0x3u & (uintptr_t)data) - { - return kStatus_InvalidArgument; - } - - /* Configure context */ - context = ((size * 8u) & 0x1FFFu); - - dataAligned = (uint32_t *)(uintptr_t)data; - - /* begin */ - base->CR = PUF_CR_GENERATE_RANDOM_MASK; - - /* wait till command is accepted */ - while (0u != (base->CR & PUF_CR_GENERATE_RANDOM_MASK)) - { - } - - /* send context and read output data while busy */ - while (0u != (base->SR & PUF_SR_BUSY_MASK)) - { - if (0u != (PUF_SR_DI_REQUEST_MASK & base->SR)) - { - base->DIR = context; - } - - if (0u != (PUF_SR_DO_REQUEST_MASK & base->SR)) - { - *dataAligned = base->DOR; - dataAligned++; - } - } - - /* get status */ - status = puf_makeStatus(base, kPUF_GenerateRandom); - - return status; -} - -/*! - * brief Zeroize PUF - * - * This function clears all PUF internal logic and puts the PUF to zeroized state. - * - * @param base PUF peripheral base address - * @return Status of the zeroize operation. - */ -status_t PUF_Zeroize(PUF_Type *base) -{ - status_t status = kStatus_Fail; - - /* zeroize command is always allowed */ - base->CR = PUF_CR_ZEROIZE_MASK; - - /* wait till command is accepted */ - while (0u != (base->CR & PUF_CR_ZEROIZE_MASK)) - { - } - - /* wait while busy */ - while (0u != (base->SR & PUF_SR_BUSY_MASK)) - { - } - - /* check status */ - if (((PUF_SR_ZEROIZED_MASK | PUF_SR_OK_MASK) == base->SR) && (0u == base->AR)) - { - status = puf_makeStatus(base, kPUF_Zeroize); - } - - return status; -} - -/*! - * brief Test PUF - * - * With the Test PUF operation, diagnostics about the PUF quality is collected and presented in a PUF - * score. - * - * @param base PUF peripheral base address - * @param score Value of the PUF Score that was obtained during the enroll operation. - * @return Status of the test operation. - */ -status_t PUF_Test(PUF_Type *base, uint8_t *score) -{ - status_t status = kStatus_Fail; - - /* check if TEST is allowed */ - if (0x0u == (base->AR & PUF_AR_ALLOW_TEST_PUF_MASK)) - { - return kStatus_PUF_OperationNotAllowed; - } - - /* begin */ - base->CR = PUF_CR_TEST_PUF_MASK; - - /* wait till command is accepted */ - while (0u != (base->CR & PUF_CR_TEST_PUF_MASK)) - { - } - - /* wait while busy */ - while (0u != (base->SR & PUF_SR_BUSY_MASK)) - { - } - - /* In case of success fill in score */ - if ((0u != (base->SR & PUF_SR_OK_MASK)) && (score != NULL)) - { - *score = (uint8_t)(base->PSR & PUF_PSR_PUF_SCORE_MASK); - } - - /* Check status */ - status = puf_makeStatus(base, kPUF_Test); - - return status; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_puf_v3.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_puf_v3.h deleted file mode 100644 index f360447f47b..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_puf_v3.h +++ /dev/null @@ -1,286 +0,0 @@ -/* - * Copyright 2017-2018 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PUF_V3_H_ -#define _PUF_V3_H_ - -#include -#include - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! - * @addtogroup puf_v3_driver - * @{ - */ -/*! @name Driver version */ -/*@{*/ -/*! @brief PUFv3 driver version. Version 2.0.0. - * - * Current version: 2.0.0 - * - * Change log: - * - 2.0.0 - * - Initial version. - */ -#define FSL_PUF_V3_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -#define kPUF_EndianLittle (0x0u) -#define kPUF_EndianBig (0x1u) -typedef uint32_t puf_endianness_t; - -#define kPUF_KeyDestRegister (0x1u) -#define kPUF_KeyDestKeyBus (0x2u) -#define kPUF_KeyDestInvalid (0x3u) -typedef uint32_t puf_key_dest_t; - -#define kPUF_KeyAllowRegister (0x1u) -#define kPUF_KeyAllowKeyBus (0x2u) -#define kPUF_KeyAllowAll (0x3u) -typedef uint32_t puf_key_scope_t; - -#define kPUF_ResultOK (0x0u) -#define kPUF_AcNotForThisProductPhase1 (0xf0u) -#define kPUF_AcNotForThisProductPhase2 (0xf1u) -#define kPUF_AcCorruptedPhase1 (0xf2u) -#define kPUF_AcCorruptedPhase2 (0xf3u) -#define kPUF_AcAuthFailedPhase1 (0xf4u) -#define kPUF_AcAuthFailedPhase2 (0xf5u) -#define kPUF_QualityVerificationFail (0xf6u) -#define kPUF_ContextIncorrect (0xf7u) -#define kPUF_DestinationNotAllowed (0xf8u) -#define kPUF_Failure (0xFFu) -typedef uint32_t puf_result_code_t; - -typedef struct -{ - puf_endianness_t dataEndianness; - uint8_t CKGATING; -} puf_config_t; - -typedef struct -{ - puf_key_scope_t keyScopeStarted; - puf_key_scope_t keyScopeEnrolled; - uint32_t userCtx0; - uint32_t userCtx1; -} puf_key_ctx_t; - -#define PUF_ACTIVATION_CODE_SIZE 996 -#define PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(x) ((0x34u + x) + 0x10u * (x / 0x32u)) - -enum _puf_status -{ - kStatus_PUF_OperationNotAllowed = MAKE_STATUS(kStatusGroup_PUF, 0xA5), - kStatus_PUF_AcNotForThisProductPhase1 = MAKE_STATUS(kStatusGroup_PUF, kPUF_AcNotForThisProductPhase1), - kStatus_PUF_AcNotForThisProductPhase2 = MAKE_STATUS(kStatusGroup_PUF, kPUF_AcNotForThisProductPhase2), - kStatus_PUF_AcCorruptedPhase1 = MAKE_STATUS(kStatusGroup_PUF, kPUF_AcCorruptedPhase1), - kStatus_PUF_AcCorruptedPhase2 = MAKE_STATUS(kStatusGroup_PUF, kPUF_AcCorruptedPhase2), - kStatus_PUF_AcAuthFailedPhase1 = MAKE_STATUS(kStatusGroup_PUF, kPUF_AcAuthFailedPhase1), - kStatus_PUF_NBOOT_AcAuthFailedPhase2 = MAKE_STATUS(kStatusGroup_PUF, kPUF_AcAuthFailedPhase2), - kStatus_PUF_QualityVerificationFail = MAKE_STATUS(kStatusGroup_PUF, kPUF_QualityVerificationFail), - kStatus_PUF_ContextIncorrect = MAKE_STATUS(kStatusGroup_PUF, kPUF_ContextIncorrect), - kStatus_PUF_DestinationNotAllowed = MAKE_STATUS(kStatusGroup_PUF, kPUF_DestinationNotAllowed), - kStatus_PUF_Failure = MAKE_STATUS(kStatusGroup_PUF, kPUF_Failure), -}; - -/******************************************************************************* - * API - *******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * brief Sets the default configuration of PUF - * - * This function initialize PUF config structure to default values. - * - * @param conf PUF configuration structure - */ -void PUF_GetDefaultConfig(puf_config_t *conf); - -/*! - * brief Initialize PUF - * - * This function enables power to PUF block and waits until the block initializes. - * - * @param conf PUF configuration structure - * @return Status of the init operation - */ -status_t PUF_Init(PUF_Type *base, puf_config_t *conf); - -/*! - * brief Denitialize PUF - * - * This function disables power to PUF SRAM and peripheral clock. - * - * @param base PUF peripheral base address - * @param conf PUF configuration structure - */ -void PUF_Deinit(PUF_Type *base, puf_config_t *conf); - -/*! - * brief Enroll PUF - * - * This function derives a digital fingerprint, generates the corresponding Activation Code (AC) - * and returns it to be stored in an NVM or a file. This step needs to be - * performed only once for each device. This function may be permanently disallowed by a fuse. - * - * @param base PUF peripheral base address - * @param[out] activationCode Word aligned address of the resulting activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 996 bytes. - * @param score Value of the PUF Score that was obtained during the enroll operation. - * @return Status of enroll operation. - */ -status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize, uint8_t *score); - -/*! - * brief Start PUF - * - * The Activation Code generated during the Enroll operation is used to - * reconstruct the digital fingerprint. This needs to be done after every power-up - * and reset. - * - * @param base PUF peripheral base address - * @param[in] activationCode Word aligned address of the input activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 996 bytes. - * @param score Value of the PUF Score that was obtained during the start operation. - * return Status of start operation. - */ -status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize, uint8_t *score); - -/*! - * brief Stop PUF - * - * The Stop operation removes all key material from PUF flipflops and PUF SRAM, and sets - * PUF to the Stopped state. - * - * @param base PUF peripheral base address - * @return Status of stop operation. - */ -status_t PUF_Stop(PUF_Type *base); - -/*! - * brief PUF Get Key - * - * The Get Key operation derives a key from the intrinsic PUF key and externally provided context. - * - * @param base PUF peripheral base address - * @param keyCtx PUF key context struct - * @param keyDest output destination of the derived PUF key - * @param[out] key Word aligned address of output key (only used when kPUF_KeyDestRegister). - * @param keySize Size of the derived key in bytes. - * @return Status of get key operation. - */ -status_t PUF_GetKey(PUF_Type *base, puf_key_ctx_t *keyCtx, puf_key_dest_t keyDest, uint8_t *key, size_t keySize); - -/*! - * brief PUF Wrap generated random - * - * The Wrap Generated Random operation wraps a random key into a Key Code (KC). - * - * @param base PUF peripheral base address - * @param keyCtx PUF key context struct - * @param keySize Size of the key to be generated in bytes. - * @param[out] keyCode Word aligned address of the resulting key code. - * @param keyCodeSize Size of the output keycode in bytes. - * @return Status of wrap generated random operation. - */ -status_t PUF_WrapGeneratedRandom( - PUF_Type *base, puf_key_ctx_t *keyCtx, size_t keySize, uint8_t *keyCode, size_t keyCodeSize); - -/*! - * brief PUF Wrap user key - * - * The Wrap operation wraps a user defined key into a Key Code (KC). - * - * @param base PUF peripheral base address - * @param keyCtx PUF key context struct. - * @param userKey Word aligned address of input user key. - * @param userKeySize Size of the key to be wrapped in bytes. - * @param[out] keyCode Word aligned address of the resulting key code. - * @param keyCodeSize Size of the output keycode in bytes. - * @return Status of wrap operation. - */ -status_t PUF_Wrap( - PUF_Type *base, puf_key_ctx_t *keyCtx, uint8_t *userKey, size_t userKeySize, uint8_t *keyCode, size_t keyCodeSize); - -/*! - * brief PUF Unwrap user key - * - * The unwrap operation unwraps the key from a previously created Key Code (KC) - * - * @param base PUF peripheral base address - * @param keyDest output destination of the unwraped PUF key - * @param[in] keyCode Word aligned address of the input key code. - * @param keyCodeSize Size of the input keycode in bytes. - * @param key Word aligned address of output key (only used when kPUF_KeyDestRegister). - * @param keySize Size of the key to be generated in bytes. - * @return Status of unwrap operation. - */ -status_t PUF_Unwrap( - PUF_Type *base, puf_key_dest_t keyDest, uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize); - -/*! - * brief Generate Random - * - * The Generate Random operation outputs the requested amount of random data as specified in a - * provided context. - * - * @param base PUF peripheral base address - * @param size Size of random data to be genarated in bytes. - * @return Status of generate random operation. - */ -status_t PUF_GenerateRandom(PUF_Type *base, uint8_t *data, size_t size); - -/*! - * brief Zeroize PUF - * - * This function clears all PUF internal logic and puts the PUF to zeroized state. - * - * @param base PUF peripheral base address - * @return Status of the zeroize operation. - */ -status_t PUF_Zeroize(PUF_Type *base); - -/*! - * brief Test PUF - * - * With the Test PUF operation, diagnostics about the PUF quality is collected and presented in a PUF - * score. - * - * @param base PUF peripheral base address - * @param score Value of the PUF Score that was obtained during the enroll operation. - * @return Status of the test operation. - */ -status_t PUF_Test(PUF_Type *base, uint8_t *score); - -/*! - * @brief Blocks specified PUF commands - * - * This function blocks PUF commands specified by mask parameter. - * - * @param base PUF peripheral base address - * @param score Value of the PUF Score that was obtained during the enroll operation. - * @return Status of the test operation. - */ -static inline void PUF_BlockCommand(PUF_Type *base, uint32_t mask) -{ - base->CONFIG |= mask; -} - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -#endif /* _PUF_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pwm.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pwm.c deleted file mode 100644 index d16fe3a1391..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pwm.c +++ /dev/null @@ -1,935 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_pwm.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.pwm" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get the instance from the base address - * - * @param base PWM peripheral base address - * - * @return The PWM module instance - */ -static uint32_t PWM_GetInstance(PWM_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to PWM bases for each instance. */ -static PWM_Type *const s_pwmBases[] = PWM_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to PWM clocks for each PWM submodule. */ -static const clock_ip_name_t s_pwmClocks[][FSL_FEATURE_PWM_SUBMODULE_COUNT] = PWM_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Complement the variable of type uint16_t as needed - * - * This function can complement the variable of type uint16_t as needed.For example, - * need to ask for the opposite of a positive integer. - * - * param value Parameters of type uint16_t - */ -static inline uint16_t PWM_GetComplementU16(uint16_t value) -{ - return (~value + 1U); -} - -static inline uint16_t dutyCycleToReloadValue(uint8_t dutyCyclePercent) -{ - /* Rounding calculations to improve the accuracy of reloadValue */ - return ((65535U * dutyCyclePercent) + 50U) / 100U; -} - -static uint32_t PWM_GetInstance(PWM_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_pwmBases); instance++) - { - if (s_pwmBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_pwmBases)); - - return instance; -} - -/*! - * brief Ungates the PWM submodule clock and configures the peripheral for basic operation. - * - * note This API should be called at the beginning of the application using the PWM driver. - * - * param base PWM peripheral base address - * param subModule PWM submodule to configure - * param config Pointer to user's PWM config structure. - * - * return kStatus_Success means success; else failed. - */ -status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config) -{ - assert(config); - - uint16_t reg; - - /* Source clock for submodule 0 cannot be itself */ - if ((config->clockSource == kPWM_Submodule0Clock) && (subModule == kPWM_Module_0)) - { - return kStatus_Fail; - } - - /* Reload source select clock for submodule 0 cannot be master reload */ - if ((config->reloadSelect == kPWM_MasterReload) && (subModule == kPWM_Module_0)) - { - return kStatus_Fail; - } - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate the PWM submodule clock*/ - CLOCK_EnableClock(s_pwmClocks[PWM_GetInstance(base)][subModule]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Clear the fault status flags */ - base->FSTS |= PWM_FSTS_FFLAG_MASK; - - reg = base->SM[subModule].CTRL2; - - /* Setup the submodule clock-source, control source of the INIT signal, - * source of the force output signal, operation in debug & wait modes and reload source select - */ - reg &= ~(uint16_t)(PWM_CTRL2_CLK_SEL_MASK | PWM_CTRL2_FORCE_SEL_MASK | PWM_CTRL2_INIT_SEL_MASK | - PWM_CTRL2_INDEP_MASK | PWM_CTRL2_WAITEN_MASK | PWM_CTRL2_DBGEN_MASK | PWM_CTRL2_RELOAD_SEL_MASK); - reg |= (PWM_CTRL2_CLK_SEL(config->clockSource) | PWM_CTRL2_FORCE_SEL(config->forceTrigger) | - PWM_CTRL2_INIT_SEL(config->initializationControl) | PWM_CTRL2_DBGEN(config->enableDebugMode) | - PWM_CTRL2_WAITEN(config->enableWait) | PWM_CTRL2_RELOAD_SEL(config->reloadSelect)); - - /* Setup PWM A & B to be independent or a complementary-pair */ - switch (config->pairOperation) - { - case kPWM_Independent: - reg |= PWM_CTRL2_INDEP_MASK; - break; - case kPWM_ComplementaryPwmA: - base->MCTRL &= ~((uint16_t)1U << (PWM_MCTRL_IPOL_SHIFT + (uint16_t)subModule)); - break; - case kPWM_ComplementaryPwmB: - base->MCTRL |= ((uint16_t)1U << (PWM_MCTRL_IPOL_SHIFT + (uint16_t)subModule)); - break; - default: - assert(false); - break; - } - base->SM[subModule].CTRL2 = reg; - - reg = base->SM[subModule].CTRL; - - /* Setup the clock prescale, load mode and frequency */ - reg &= ~(uint16_t)(PWM_CTRL_PRSC_MASK | PWM_CTRL_LDFQ_MASK | PWM_CTRL_LDMOD_MASK); - reg |= (PWM_CTRL_PRSC(config->prescale) | PWM_CTRL_LDFQ(config->reloadFrequency)); - - /* Setup register reload logic */ - switch (config->reloadLogic) - { - case kPWM_ReloadImmediate: - reg |= PWM_CTRL_LDMOD_MASK; - break; - case kPWM_ReloadPwmHalfCycle: - reg |= PWM_CTRL_HALF_MASK; - reg &= (uint16_t)(~PWM_CTRL_FULL_MASK); - break; - case kPWM_ReloadPwmFullCycle: - reg &= (uint16_t)(~PWM_CTRL_HALF_MASK); - reg |= PWM_CTRL_FULL_MASK; - break; - case kPWM_ReloadPwmHalfAndFullCycle: - reg |= PWM_CTRL_HALF_MASK; - reg |= PWM_CTRL_FULL_MASK; - break; - default: - assert(false); - break; - } - base->SM[subModule].CTRL = reg; - - /* Issue a Force trigger event when configured to trigger locally */ - if (config->forceTrigger == kPWM_Force_Local) - { - base->SM[subModule].CTRL2 |= PWM_CTRL2_FORCE(1U); - } - - return kStatus_Success; -} - -/*! - * brief Gate the PWM submodule clock - * - * param base PWM peripheral base address - * param subModule PWM submodule to deinitialize - */ -void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule) -{ - /* Stop the submodule */ - base->MCTRL &= ~((uint16_t)1U << (PWM_MCTRL_RUN_SHIFT + (uint16_t)subModule)); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the PWM submodule clock*/ - CLOCK_DisableClock(s_pwmClocks[PWM_GetInstance(base)][subModule]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Fill in the PWM config struct with the default settings - * - * The default values are: - * code - * config->enableDebugMode = false; - * config->enableWait = false; - * config->reloadSelect = kPWM_LocalReload; - * config->clockSource = kPWM_BusClock; - * config->prescale = kPWM_Prescale_Divide_1; - * config->initializationControl = kPWM_Initialize_LocalSync; - * config->forceTrigger = kPWM_Force_Local; - * config->reloadFrequency = kPWM_LoadEveryOportunity; - * config->reloadLogic = kPWM_ReloadImmediate; - * config->pairOperation = kPWM_Independent; - * endcode - * param config Pointer to user's PWM config structure. - */ -void PWM_GetDefaultConfig(pwm_config_t *config) -{ - assert(config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* PWM is paused in debug mode */ - config->enableDebugMode = false; - /* PWM is paused in wait mode */ - config->enableWait = false; - /* PWM module uses the local reload signal to reload registers */ - config->reloadSelect = kPWM_LocalReload; - /* Use the IP Bus clock as source clock for the PWM submodule */ - config->clockSource = kPWM_BusClock; - /* Clock source prescale is set to divide by 1*/ - config->prescale = kPWM_Prescale_Divide_1; - /* Local sync causes initialization */ - config->initializationControl = kPWM_Initialize_LocalSync; - /* The local force signal, CTRL2[FORCE], from the submodule is used to force updates */ - config->forceTrigger = kPWM_Force_Local; - /* PWM reload frequency, reload opportunity is PWM half cycle or full cycle. - * This field is not used in Immediate reload mode - */ - config->reloadFrequency = kPWM_LoadEveryOportunity; - /* Buffered-registers get loaded with new values as soon as LDOK bit is set */ - config->reloadLogic = kPWM_ReloadImmediate; - /* PWM A & PWM B operate as 2 independent channels */ - config->pairOperation = kPWM_Independent; -} - -/*! - * brief Sets up the PWM signals for a PWM submodule. - * - * The function initializes the submodule according to the parameters passed in by the user. The function - * also sets up the value compare registers to match the PWM signal requirements. - * If the dead time insertion logic is enabled, the pulse period is reduced by the - * dead time period specified by the user. - * - * param base PWM peripheral base address - * param subModule PWM submodule to configure - * param chnlParams Array of PWM channel parameters to configure the channel(s) - * param numOfChnls Number of channels to configure, this should be the size of the array passed in. - * Array size should not be more than 2 as each submodule has 2 pins to output PWM - * param mode PWM operation mode, options available in enumeration ::pwm_mode_t - * param pwmFreq_Hz PWM signal frequency in Hz - * param srcClock_Hz PWM main counter clock in Hz. - * - * return Returns kStatusFail if there was error setting up the signal; kStatusSuccess otherwise - */ -status_t PWM_SetupPwm(PWM_Type *base, - pwm_submodule_t subModule, - const pwm_signal_param_t *chnlParams, - uint8_t numOfChnls, - pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz) -{ - assert(chnlParams); - assert(pwmFreq_Hz); - assert(numOfChnls); - assert(srcClock_Hz); - - uint32_t pwmClock; - uint16_t pulseCnt = 0, pwmHighPulse = 0; - uint16_t modulo = 0; - uint8_t i, polarityShift = 0, outputEnableShift = 0; - - if (numOfChnls > 2U) - { - /* Each submodule has 2 signals; PWM A & PWM B */ - return kStatus_Fail; - } - - /* Divide the clock by the prescale value */ - pwmClock = (srcClock_Hz / (1UL << ((base->SM[subModule].CTRL & PWM_CTRL_PRSC_MASK) >> PWM_CTRL_PRSC_SHIFT))); - pulseCnt = (uint16_t)(pwmClock / pwmFreq_Hz); - - /* Setup each PWM channel */ - for (i = 0; i < numOfChnls; i++) - { - /* Calculate pulse width */ - pwmHighPulse = (pulseCnt * chnlParams->dutyCyclePercent) / 100U; - - /* Setup the different match registers to generate the PWM signal */ - switch (mode) - { - case kPWM_SignedCenterAligned: - /* Setup the PWM period for a signed center aligned signal */ - if (i == 0U) - { - modulo = (pulseCnt >> 1U); - /* Indicates the start of the PWM period */ - base->SM[subModule].INIT = PWM_GetComplementU16(modulo); - /* Indicates the center value */ - base->SM[subModule].VAL0 = 0; - /* Indicates the end of the PWM period */ - /* The change during the end to start of the PWM period requires a count time */ - base->SM[subModule].VAL1 = modulo - 1U; - } - - /* Setup the PWM dutycycle */ - if (chnlParams->pwmChannel == kPWM_PwmA) - { - base->SM[subModule].VAL2 = PWM_GetComplementU16(pwmHighPulse / 2U); - base->SM[subModule].VAL3 = (pwmHighPulse / 2U); - } - else - { - base->SM[subModule].VAL4 = PWM_GetComplementU16(pwmHighPulse / 2U); - base->SM[subModule].VAL5 = (pwmHighPulse / 2U); - } - break; - case kPWM_CenterAligned: - /* Setup the PWM period for an unsigned center aligned signal */ - /* Indicates the start of the PWM period */ - if (i == 0U) - { - base->SM[subModule].INIT = 0; - /* Indicates the center value */ - base->SM[subModule].VAL0 = (pulseCnt / 2U); - /* Indicates the end of the PWM period */ - /* The change during the end to start of the PWM period requires a count time */ - base->SM[subModule].VAL1 = pulseCnt - 1U; - } - - /* Setup the PWM dutycycle */ - if (chnlParams->pwmChannel == kPWM_PwmA) - { - base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2U); - base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2U); - } - else - { - base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2U); - base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2U); - } - break; - case kPWM_SignedEdgeAligned: - /* Setup the PWM period for a signed edge aligned signal */ - if (i == 0U) - { - modulo = (pulseCnt >> 1U); - /* Indicates the start of the PWM period */ - base->SM[subModule].INIT = PWM_GetComplementU16(modulo); - /* Indicates the center value */ - base->SM[subModule].VAL0 = 0; - /* Indicates the end of the PWM period */ - /* The change during the end to start of the PWM period requires a count time */ - base->SM[subModule].VAL1 = modulo - 1U; - } - - /* Setup the PWM dutycycle */ - if (chnlParams->pwmChannel == kPWM_PwmA) - { - base->SM[subModule].VAL2 = PWM_GetComplementU16(modulo); - base->SM[subModule].VAL3 = PWM_GetComplementU16(modulo) + pwmHighPulse; - } - else - { - base->SM[subModule].VAL4 = PWM_GetComplementU16(modulo); - base->SM[subModule].VAL5 = PWM_GetComplementU16(modulo) + pwmHighPulse; - } - break; - case kPWM_EdgeAligned: - /* Setup the PWM period for a unsigned edge aligned signal */ - /* Indicates the start of the PWM period */ - if (i == 0U) - { - base->SM[subModule].INIT = 0; - /* Indicates the center value */ - base->SM[subModule].VAL0 = (pulseCnt / 2U); - /* Indicates the end of the PWM period */ - /* The change during the end to start of the PWM period requires a count time */ - base->SM[subModule].VAL1 = pulseCnt - 1U; - } - - /* Setup the PWM dutycycle */ - if (chnlParams->pwmChannel == kPWM_PwmA) - { - base->SM[subModule].VAL2 = 0; - base->SM[subModule].VAL3 = pwmHighPulse; - } - else - { - base->SM[subModule].VAL4 = 0; - base->SM[subModule].VAL5 = pwmHighPulse; - } - break; - default: - assert(false); - break; - } - /* Setup register shift values based on the channel being configured. - * Also setup the deadtime value - */ - if (chnlParams->pwmChannel == kPWM_PwmA) - { - polarityShift = PWM_OCTRL_POLA_SHIFT; - outputEnableShift = PWM_OUTEN_PWMA_EN_SHIFT; - base->SM[subModule].DTCNT0 = PWM_DTCNT0_DTCNT0(chnlParams->deadtimeValue); - } - else - { - polarityShift = PWM_OCTRL_POLB_SHIFT; - outputEnableShift = PWM_OUTEN_PWMB_EN_SHIFT; - base->SM[subModule].DTCNT1 = PWM_DTCNT1_DTCNT1(chnlParams->deadtimeValue); - } - - /* Set PWM output fault status */ - switch (chnlParams->pwmChannel) - { - case kPWM_PwmA: - base->SM[subModule].OCTRL &= ~((uint16_t)PWM_OCTRL_PWMAFS_MASK); - base->SM[subModule].OCTRL |= (((uint16_t)(chnlParams->faultState) << (uint16_t)PWM_OCTRL_PWMAFS_SHIFT) & - (uint16_t)PWM_OCTRL_PWMAFS_MASK); - break; - case kPWM_PwmB: - base->SM[subModule].OCTRL &= ~((uint16_t)PWM_OCTRL_PWMBFS_MASK); - base->SM[subModule].OCTRL |= (((uint16_t)(chnlParams->faultState) << (uint16_t)PWM_OCTRL_PWMBFS_SHIFT) & - (uint16_t)PWM_OCTRL_PWMBFS_MASK); - break; - case kPWM_PwmX: - base->SM[subModule].OCTRL &= ~((uint16_t)PWM_OCTRL_PWMXFS_MASK); - base->SM[subModule].OCTRL |= (((uint16_t)(chnlParams->faultState) << (uint16_t)PWM_OCTRL_PWMXFS_SHIFT) & - (uint16_t)PWM_OCTRL_PWMXFS_MASK); - break; - default: - assert(false); - break; - } - - /* Setup signal active level */ - if ((bool)chnlParams->level == kPWM_HighTrue) - { - base->SM[subModule].OCTRL &= ~((uint16_t)1U << (uint16_t)polarityShift); - } - else - { - base->SM[subModule].OCTRL |= ((uint16_t)1U << (uint16_t)polarityShift); - } - /* Enable PWM output */ - base->OUTEN |= ((uint16_t)1U << ((uint16_t)outputEnableShift + (uint16_t)subModule)); - - /* Get the next channel parameters */ - chnlParams++; - } - - return kStatus_Success; -} - -/*! - * brief Updates the PWM signal's dutycycle. - * - * The function updates the PWM dutycyle to the new value that is passed in. - * If the dead time insertion logic is enabled then the pulse period is reduced by the - * dead time period specified by the user. - * - * param base PWM peripheral base address - * param subModule PWM submodule to configure - * param pwmSignal Signal (PWM A or PWM B) to update - * param currPwmMode The current PWM mode set during PWM setup - * param dutyCyclePercent New PWM pulse width, value should be between 0 to 100 - * 0=inactive signal(0% duty cycle)... - * 100=active signal (100% duty cycle) - */ -void PWM_UpdatePwmDutycycle(PWM_Type *base, - pwm_submodule_t subModule, - pwm_channels_t pwmSignal, - pwm_mode_t currPwmMode, - uint8_t dutyCyclePercent) -{ - assert(dutyCyclePercent <= 100U); - assert((uint16_t)pwmSignal < 2U); - uint16_t reloadValue = dutyCycleToReloadValue(dutyCyclePercent); - - PWM_UpdatePwmDutycycleHighAccuracy(base, subModule, pwmSignal, currPwmMode, reloadValue); -} - -/*! - * brief Updates the PWM signal's dutycycle with 16-bit accuracy. - * - * The function updates the PWM dutycyle to the new value that is passed in. - * If the dead time insertion logic is enabled then the pulse period is reduced by the - * dead time period specified by the user. - * - * param base PWM peripheral base address - * param subModule PWM submodule to configure - * param pwmSignal Signal (PWM A or PWM B) to update - * param currPwmMode The current PWM mode set during PWM setup - * param dutyCycle New PWM pulse width, value should be between 0 to 65535 - * 0=inactive signal(0% duty cycle)... - * 65535=active signal (100% duty cycle) - */ -void PWM_UpdatePwmDutycycleHighAccuracy( - PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t dutyCycle) -{ - assert((uint16_t)pwmSignal < 2U); - uint16_t pulseCnt = 0, pwmHighPulse = 0; - uint16_t modulo = 0; - - switch (currPwmMode) - { - case kPWM_SignedCenterAligned: - modulo = base->SM[subModule].VAL1 + 1U; - pulseCnt = modulo * 2U; - /* Calculate pulse width */ - pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; - - /* Setup the PWM dutycycle */ - if (pwmSignal == kPWM_PwmA) - { - base->SM[subModule].VAL2 = PWM_GetComplementU16(pwmHighPulse / 2U); - base->SM[subModule].VAL3 = (pwmHighPulse / 2U); - } - else - { - base->SM[subModule].VAL4 = PWM_GetComplementU16(pwmHighPulse / 2U); - base->SM[subModule].VAL5 = (pwmHighPulse / 2U); - } - break; - case kPWM_CenterAligned: - pulseCnt = base->SM[subModule].VAL1 + 1U; - /* Calculate pulse width */ - pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; - - /* Setup the PWM dutycycle */ - if (pwmSignal == kPWM_PwmA) - { - base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2U); - base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2U); - } - else - { - base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2U); - base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2U); - } - break; - case kPWM_SignedEdgeAligned: - modulo = base->SM[subModule].VAL1 + 1U; - pulseCnt = modulo * 2U; - /* Calculate pulse width */ - pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; - - /* Setup the PWM dutycycle */ - if (pwmSignal == kPWM_PwmA) - { - base->SM[subModule].VAL2 = PWM_GetComplementU16(modulo); - base->SM[subModule].VAL3 = PWM_GetComplementU16(modulo) + pwmHighPulse; - } - else - { - base->SM[subModule].VAL4 = PWM_GetComplementU16(modulo); - base->SM[subModule].VAL5 = PWM_GetComplementU16(modulo) + pwmHighPulse; - } - break; - case kPWM_EdgeAligned: - pulseCnt = base->SM[subModule].VAL1 + 1U; - /* Calculate pulse width */ - pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; - - /* Setup the PWM dutycycle */ - if (pwmSignal == kPWM_PwmA) - { - base->SM[subModule].VAL2 = 0; - base->SM[subModule].VAL3 = pwmHighPulse; - } - else - { - base->SM[subModule].VAL4 = 0; - base->SM[subModule].VAL5 = pwmHighPulse; - } - break; - default: - assert(false); - break; - } -} - -/*! - * brief Sets up the PWM input capture - * - * Each PWM submodule has 3 pins that can be configured for use as input capture pins. This function - * sets up the capture parameters for each pin and enables the pin for input capture operation. - * - * param base PWM peripheral base address - * param subModule PWM submodule to configure - * param pwmChannel Channel in the submodule to setup - * param inputCaptureParams Parameters passed in to set up the input pin - */ -void PWM_SetupInputCapture(PWM_Type *base, - pwm_submodule_t subModule, - pwm_channels_t pwmChannel, - const pwm_input_capture_param_t *inputCaptureParams) -{ - uint16_t reg = 0; - switch (pwmChannel) - { - case kPWM_PwmA: - /* Setup the capture paramters for PWM A pin */ - reg = (PWM_CAPTCTRLA_INP_SELA(inputCaptureParams->captureInputSel) | - PWM_CAPTCTRLA_EDGA0(inputCaptureParams->edge0) | PWM_CAPTCTRLA_EDGA1(inputCaptureParams->edge1) | - PWM_CAPTCTRLA_ONESHOTA(inputCaptureParams->enableOneShotCapture) | - PWM_CAPTCTRLA_CFAWM(inputCaptureParams->fifoWatermark)); - /* Enable the edge counter if using the output edge counter */ - if (inputCaptureParams->captureInputSel) - { - reg |= PWM_CAPTCTRLA_EDGCNTA_EN_MASK; - } - /* Enable input capture operation */ - reg |= PWM_CAPTCTRLA_ARMA_MASK; - - base->SM[subModule].CAPTCTRLA = reg; - - /* Setup the compare value when using the edge counter as source */ - base->SM[subModule].CAPTCOMPA = PWM_CAPTCOMPA_EDGCMPA(inputCaptureParams->edgeCompareValue); - /* Setup PWM A pin for input capture */ - base->OUTEN &= ~((uint16_t)1U << (PWM_OUTEN_PWMA_EN_SHIFT + (uint16_t)subModule)); - break; - case kPWM_PwmB: - /* Setup the capture paramters for PWM B pin */ - reg = (PWM_CAPTCTRLB_INP_SELB(inputCaptureParams->captureInputSel) | - PWM_CAPTCTRLB_EDGB0(inputCaptureParams->edge0) | PWM_CAPTCTRLB_EDGB1(inputCaptureParams->edge1) | - PWM_CAPTCTRLB_ONESHOTB(inputCaptureParams->enableOneShotCapture) | - PWM_CAPTCTRLB_CFBWM(inputCaptureParams->fifoWatermark)); - /* Enable the edge counter if using the output edge counter */ - if (inputCaptureParams->captureInputSel) - { - reg |= PWM_CAPTCTRLB_EDGCNTB_EN_MASK; - } - /* Enable input capture operation */ - reg |= PWM_CAPTCTRLB_ARMB_MASK; - - base->SM[subModule].CAPTCTRLB = reg; - - /* Setup the compare value when using the edge counter as source */ - base->SM[subModule].CAPTCOMPB = PWM_CAPTCOMPB_EDGCMPB(inputCaptureParams->edgeCompareValue); - /* Setup PWM B pin for input capture */ - base->OUTEN &= ~((uint16_t)1U << (PWM_OUTEN_PWMB_EN_SHIFT + (uint16_t)subModule)); - break; - case kPWM_PwmX: - reg = (PWM_CAPTCTRLX_INP_SELX(inputCaptureParams->captureInputSel) | - PWM_CAPTCTRLX_EDGX0(inputCaptureParams->edge0) | PWM_CAPTCTRLX_EDGX1(inputCaptureParams->edge1) | - PWM_CAPTCTRLX_ONESHOTX(inputCaptureParams->enableOneShotCapture) | - PWM_CAPTCTRLX_CFXWM(inputCaptureParams->fifoWatermark)); - /* Enable the edge counter if using the output edge counter */ - if (inputCaptureParams->captureInputSel) - { - reg |= PWM_CAPTCTRLX_EDGCNTX_EN_MASK; - } - /* Enable input capture operation */ - reg |= PWM_CAPTCTRLX_ARMX_MASK; - - base->SM[subModule].CAPTCTRLX = reg; - - /* Setup the compare value when using the edge counter as source */ - base->SM[subModule].CAPTCOMPX = PWM_CAPTCOMPX_EDGCMPX(inputCaptureParams->edgeCompareValue); - /* Setup PWM X pin for input capture */ - base->OUTEN &= ~((uint16_t)1U << (PWM_OUTEN_PWMX_EN_SHIFT + (uint16_t)subModule)); - break; - default: - assert(false); - break; - } -} - -/*! - * @brief Sets up the PWM fault input filter. - * - * @param base PWM peripheral base address - * @param faultInputFilterParams Parameters passed in to set up the fault input filter. - */ -void PWM_SetupFaultInputFilter(PWM_Type *base, const pwm_fault_input_filter_param_t *faultInputFilterParams) -{ - assert(NULL != faultInputFilterParams); - - /* When changing values for fault period from a non-zero value, first write a value of 0 to clear the filter. */ - if (0U != (base->FFILT & PWM_FFILT_FILT_PER_MASK)) - { - base->FFILT &= ~(uint16_t)(PWM_FFILT_FILT_PER_MASK); - } - - base->FFILT = (uint16_t)(PWM_FFILT_FILT_PER(faultInputFilterParams->faultFilterPeriod) | - PWM_FFILT_FILT_CNT(faultInputFilterParams->faultFilterCount) | - PWM_FFILT_GSTR(faultInputFilterParams->faultGlitchStretch ? 1U : 0U)); -} - -/*! - * brief Sets up the PWM fault protection. - * - * PWM has 4 fault inputs. - * - * param base PWM peripheral base address - * param faultNum PWM fault to configure. - * param faultParams Pointer to the PWM fault config structure - */ -void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams) -{ - assert(faultParams); - uint16_t reg; - - reg = base->FCTRL; - /* Set the faults level-settting */ - if (faultParams->faultLevel) - { - reg |= ((uint16_t)1U << (PWM_FCTRL_FLVL_SHIFT + (uint16_t)faultNum)); - } - else - { - reg &= ~((uint16_t)1U << (PWM_FCTRL_FLVL_SHIFT + (uint16_t)faultNum)); - } - /* Set the fault clearing mode */ - if ((uint16_t)faultParams->faultClearingMode != 0U) - { - /* Use manual fault clearing */ - reg &= ~((uint16_t)1U << (PWM_FCTRL_FAUTO_SHIFT + (uint16_t)faultNum)); - if (faultParams->faultClearingMode == kPWM_ManualSafety) - { - /* Use manual fault clearing with safety mode enabled */ - reg |= ((uint16_t)1U << (PWM_FCTRL_FSAFE_SHIFT + (uint16_t)faultNum)); - } - else - { - /* Use manual fault clearing with safety mode disabled */ - reg &= ~((uint16_t)1U << (PWM_FCTRL_FSAFE_SHIFT + (uint16_t)faultNum)); - } - } - else - { - /* Use automatic fault clearing */ - reg |= ((uint16_t)1U << (PWM_FCTRL_FAUTO_SHIFT + (uint16_t)faultNum)); - } - base->FCTRL = reg; - - /* Set the combinational path option */ - if (faultParams->enableCombinationalPath) - { - /* Combinational path from the fault input to the PWM output is available */ - base->FCTRL2 &= ~((uint16_t)1U << (uint16_t)faultNum); - } - else - { - /* No combinational path available, only fault filter & latch signal can disable PWM output */ - base->FCTRL2 |= ((uint16_t)1U << (uint16_t)faultNum); - } - - /* Initially clear both recovery modes */ - reg = base->FSTS; - reg &= ~(((uint16_t)1U << (PWM_FSTS_FFULL_SHIFT + (uint16_t)faultNum)) | - ((uint16_t)1U << (PWM_FSTS_FHALF_SHIFT + (uint16_t)faultNum))); - /* Setup fault recovery */ - switch (faultParams->recoverMode) - { - case kPWM_NoRecovery: - break; - case kPWM_RecoverHalfCycle: - reg |= ((uint16_t)1U << (PWM_FSTS_FHALF_SHIFT + (uint16_t)faultNum)); - break; - case kPWM_RecoverFullCycle: - reg |= ((uint16_t)1U << (PWM_FSTS_FFULL_SHIFT + (uint16_t)faultNum)); - break; - case kPWM_RecoverHalfAndFullCycle: - reg |= ((uint16_t)1U << (PWM_FSTS_FHALF_SHIFT + (uint16_t)faultNum)); - reg |= ((uint16_t)1U << (PWM_FSTS_FFULL_SHIFT + (uint16_t)faultNum)); - break; - default: - assert(false); - break; - } - base->FSTS = reg; -} - -/*! - * brief Fill in the PWM fault config struct with the default settings - * - * The default values are: - * code - * config->faultClearingMode = kPWM_Automatic; - * config->faultLevel = false; - * config->enableCombinationalPath = true; - * config->recoverMode = kPWM_NoRecovery; - * endcode - * param config Pointer to user's PWM fault config structure. - */ -void PWM_FaultDefaultConfig(pwm_fault_param_t *config) -{ - assert(config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* PWM uses automatic fault clear mode */ - config->faultClearingMode = kPWM_Automatic; - /* PWM fault level is set to logic 0 */ - config->faultLevel = false; - /* Combinational Path from fault input is enabled */ - config->enableCombinationalPath = true; - /* PWM output will stay inactive when recovering from a fault */ - config->recoverMode = kPWM_NoRecovery; -} - -/*! - * brief Selects the signal to output on a PWM pin when a FORCE_OUT signal is asserted. - * - * The user specifies which channel to configure by supplying the submodule number and whether - * to modify PWM A or PWM B within that submodule. - * - * param base PWM peripheral base address - * param subModule PWM submodule to configure - * param pwmChannel Channel to configure - * param mode Signal to output when a FORCE_OUT is triggered - */ -void PWM_SetupForceSignal(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_force_signal_t mode) - -{ - uint16_t shift; - uint16_t reg; - - /* DTSRCSEL register has 4 bits per submodule; 2 bits for PWM A and 2 bits for PWM B */ - shift = ((uint16_t)subModule * 4U) + ((uint16_t)pwmChannel * 2U); - - /* Setup the signal to be passed upon occurrence of a FORCE_OUT signal */ - reg = base->DTSRCSEL; - reg &= ~((uint16_t)0x3U << shift); - reg |= (uint16_t)((uint16_t)mode << shift); - base->DTSRCSEL = reg; -} - -/*! - * brief Enables the selected PWM interrupts - * - * param base PWM peripheral base address - * param subModule PWM submodule to configure - * param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::pwm_interrupt_enable_t - */ -void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) -{ - /* Upper 16 bits are for related to the submodule */ - base->SM[subModule].INTEN |= ((uint16_t)mask & 0xFFFFU); - /* Fault related interrupts */ - base->FCTRL |= ((uint16_t)(mask >> 16U) & PWM_FCTRL_FIE_MASK); -} - -/*! - * brief Disables the selected PWM interrupts - * - * param base PWM peripheral base address - * param subModule PWM submodule to configure - * param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::pwm_interrupt_enable_t - */ -void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) -{ - base->SM[subModule].INTEN &= ~((uint16_t)mask & 0xFFFFU); - base->FCTRL &= ~((uint16_t)(mask >> 16U) & PWM_FCTRL_FIE_MASK); -} - -/*! - * brief Gets the enabled PWM interrupts - * - * param base PWM peripheral base address - * param subModule PWM submodule to configure - * - * return The enabled interrupts. This is the logical OR of members of the - * enumeration ::pwm_interrupt_enable_t - */ -uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule) -{ - uint32_t enabledInterrupts; - - enabledInterrupts = base->SM[subModule].INTEN; - enabledInterrupts |= (((uint32_t)base->FCTRL & PWM_FCTRL_FIE_MASK) << 16UL); - return enabledInterrupts; -} - -/*! - * brief Gets the PWM status flags - * - * param base PWM peripheral base address - * param subModule PWM submodule to configure - * - * return The status flags. This is the logical OR of members of the - * enumeration ::pwm_status_flags_t - */ -uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule) -{ - uint32_t statusFlags; - - statusFlags = base->SM[subModule].STS; - statusFlags |= (((uint32_t)base->FSTS & PWM_FSTS_FFLAG_MASK) << 16UL); - - return statusFlags; -} - -/*! - * brief Clears the PWM status flags - * - * param base PWM peripheral base address - * param subModule PWM submodule to configure - * param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::pwm_status_flags_t - */ -void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) -{ - uint16_t reg; - - base->SM[subModule].STS = ((uint16_t)mask & 0xFFFFU); - reg = base->FSTS; - /* Clear the fault flags and set only the ones we wish to clear as the fault flags are cleared - * by writing a login one - */ - reg &= ~(uint16_t)(PWM_FSTS_FFLAG_MASK); - reg |= (uint16_t)((mask >> 16U) & PWM_FSTS_FFLAG_MASK); - base->FSTS = reg; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pwm.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pwm.h deleted file mode 100644 index 081abf1521c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pwm.h +++ /dev/null @@ -1,987 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_PWM_H_ -#define _FSL_PWM_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup pwm_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_PWM_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1 */ -/*@}*/ - -/*! Number of bits per submodule for software output control */ -#define PWM_SUBMODULE_SWCONTROL_WIDTH 2 - -/*! @brief List of PWM submodules */ -typedef enum _pwm_submodule -{ - kPWM_Module_0 = 0U, /*!< Submodule 0 */ - kPWM_Module_1, /*!< Submodule 1 */ - kPWM_Module_2, /*!< Submodule 2 */ - kPWM_Module_3 /*!< Submodule 3 */ -} pwm_submodule_t; - -/*! @brief List of PWM channels in each module */ -typedef enum _pwm_channels -{ - kPWM_PwmB = 0U, - kPWM_PwmA, - kPWM_PwmX -} pwm_channels_t; - -/*! @brief List of PWM value registers */ -typedef enum _pwm_value_register -{ - kPWM_ValueRegister_0 = 0U, /*!< PWM Value0 register */ - kPWM_ValueRegister_1, /*!< PWM Value1 register */ - kPWM_ValueRegister_2, /*!< PWM Value2 register */ - kPWM_ValueRegister_3, /*!< PWM Value3 register */ - kPWM_ValueRegister_4, /*!< PWM Value4 register */ - kPWM_ValueRegister_5 /*!< PWM Value5 register */ -} pwm_value_register_t; - -/*! @brief List of PWM value registers mask */ -enum _pwm_value_register_mask -{ - kPWM_ValueRegisterMask_0 = (1U << 0), /*!< PWM Value0 register mask */ - kPWM_ValueRegisterMask_1 = (1U << 1), /*!< PWM Value1 register mask */ - kPWM_ValueRegisterMask_2 = (1U << 2), /*!< PWM Value2 register mask */ - kPWM_ValueRegisterMask_3 = (1U << 3), /*!< PWM Value3 register mask */ - kPWM_ValueRegisterMask_4 = (1U << 4), /*!< PWM Value4 register mask */ - kPWM_ValueRegisterMask_5 = (1U << 5) /*!< PWM Value5 register mask */ -}; - -/*! @brief PWM clock source selection.*/ -typedef enum _pwm_clock_source -{ - kPWM_BusClock = 0U, /*!< The IPBus clock is used as the clock */ - kPWM_ExternalClock, /*!< EXT_CLK is used as the clock */ - kPWM_Submodule0Clock /*!< Clock of the submodule 0 (AUX_CLK) is used as the source clock */ -} pwm_clock_source_t; - -/*! @brief PWM prescaler factor selection for clock source*/ -typedef enum _pwm_clock_prescale -{ - kPWM_Prescale_Divide_1 = 0U, /*!< PWM clock frequency = fclk/1 */ - kPWM_Prescale_Divide_2, /*!< PWM clock frequency = fclk/2 */ - kPWM_Prescale_Divide_4, /*!< PWM clock frequency = fclk/4 */ - kPWM_Prescale_Divide_8, /*!< PWM clock frequency = fclk/8 */ - kPWM_Prescale_Divide_16, /*!< PWM clock frequency = fclk/16 */ - kPWM_Prescale_Divide_32, /*!< PWM clock frequency = fclk/32 */ - kPWM_Prescale_Divide_64, /*!< PWM clock frequency = fclk/64 */ - kPWM_Prescale_Divide_128 /*!< PWM clock frequency = fclk/128 */ -} pwm_clock_prescale_t; - -/*! @brief Options that can trigger a PWM FORCE_OUT */ -typedef enum _pwm_force_output_trigger -{ - kPWM_Force_Local = 0U, /*!< The local force signal, CTRL2[FORCE], from the submodule is used to force updates */ - kPWM_Force_Master, /*!< The master force signal from submodule 0 is used to force updates */ - kPWM_Force_LocalReload, /*!< The local reload signal from this submodule is used to force updates without regard to - the state of LDOK */ - kPWM_Force_MasterReload, /*!< The master reload signal from submodule 0 is used to force updates if LDOK is set */ - kPWM_Force_LocalSync, /*!< The local sync signal from this submodule is used to force updates */ - kPWM_Force_MasterSync, /*!< The master sync signal from submodule0 is used to force updates */ - kPWM_Force_External, /*!< The external force signal, EXT_FORCE, from outside the PWM module causes updates */ - kPWM_Force_ExternalSync /*!< The external sync signal, EXT_SYNC, from outside the PWM module causes updates */ -} pwm_force_output_trigger_t; - -/*! @brief PWM counter initialization options */ -typedef enum _pwm_init_source -{ - kPWM_Initialize_LocalSync = 0U, /*!< Local sync causes initialization */ - kPWM_Initialize_MasterReload, /*!< Master reload from submodule 0 causes initialization */ - kPWM_Initialize_MasterSync, /*!< Master sync from submodule 0 causes initialization */ - kPWM_Initialize_ExtSync /*!< EXT_SYNC causes initialization */ -} pwm_init_source_t; - -/*! @brief PWM load frequency selection */ -typedef enum _pwm_load_frequency -{ - kPWM_LoadEveryOportunity = 0U, /*!< Every PWM opportunity */ - kPWM_LoadEvery2Oportunity, /*!< Every 2 PWM opportunities */ - kPWM_LoadEvery3Oportunity, /*!< Every 3 PWM opportunities */ - kPWM_LoadEvery4Oportunity, /*!< Every 4 PWM opportunities */ - kPWM_LoadEvery5Oportunity, /*!< Every 5 PWM opportunities */ - kPWM_LoadEvery6Oportunity, /*!< Every 6 PWM opportunities */ - kPWM_LoadEvery7Oportunity, /*!< Every 7 PWM opportunities */ - kPWM_LoadEvery8Oportunity, /*!< Every 8 PWM opportunities */ - kPWM_LoadEvery9Oportunity, /*!< Every 9 PWM opportunities */ - kPWM_LoadEvery10Oportunity, /*!< Every 10 PWM opportunities */ - kPWM_LoadEvery11Oportunity, /*!< Every 11 PWM opportunities */ - kPWM_LoadEvery12Oportunity, /*!< Every 12 PWM opportunities */ - kPWM_LoadEvery13Oportunity, /*!< Every 13 PWM opportunities */ - kPWM_LoadEvery14Oportunity, /*!< Every 14 PWM opportunities */ - kPWM_LoadEvery15Oportunity, /*!< Every 15 PWM opportunities */ - kPWM_LoadEvery16Oportunity /*!< Every 16 PWM opportunities */ -} pwm_load_frequency_t; - -/*! @brief List of PWM fault selections */ -typedef enum _pwm_fault_input -{ - kPWM_Fault_0 = 0U, /*!< Fault 0 input pin */ - kPWM_Fault_1, /*!< Fault 1 input pin */ - kPWM_Fault_2, /*!< Fault 2 input pin */ - kPWM_Fault_3 /*!< Fault 3 input pin */ -} pwm_fault_input_t; - -/*! @brief List of PWM fault disable mapping selections */ -typedef enum _pwm_fault_disable -{ - kPWM_FaultDisable_0 = (1U << 0), /*!< Fault 0 disable mapping */ - kPWM_FaultDisable_1 = (1U << 1), /*!< Fault 1 disable mapping */ - kPWM_FaultDisable_2 = (1U << 2), /*!< Fault 2 disable mapping */ - kPWM_FaultDisable_3 = (1U << 3) /*!< Fault 3 disable mapping */ -} pwm_fault_disable_t; - -/*! @brief List of PWM fault channels */ -typedef enum _pwm_fault_channels -{ - kPWM_faultchannel_0 = 0U, - kPWM_faultchannel_1 -} pwm_fault_channels_t; - -/*! @brief PWM capture edge select */ -typedef enum _pwm_input_capture_edge -{ - kPWM_Disable = 0U, /*!< Disabled */ - kPWM_FallingEdge, /*!< Capture on falling edge only */ - kPWM_RisingEdge, /*!< Capture on rising edge only */ - kPWM_RiseAndFallEdge /*!< Capture on rising or falling edge */ -} pwm_input_capture_edge_t; - -/*! @brief PWM output options when a FORCE_OUT signal is asserted */ -typedef enum _pwm_force_signal -{ - kPWM_UsePwm = 0U, /*!< Generated PWM signal is used by the deadtime logic.*/ - kPWM_InvertedPwm, /*!< Inverted PWM signal is used by the deadtime logic.*/ - kPWM_SoftwareControl, /*!< Software controlled value is used by the deadtime logic. */ - kPWM_UseExternal /*!< PWM_EXTA signal is used by the deadtime logic. */ -} pwm_force_signal_t; - -/*! @brief Options available for the PWM A & B pair operation */ -typedef enum _pwm_chnl_pair_operation -{ - kPWM_Independent = 0U, /*!< PWM A & PWM B operate as 2 independent channels */ - kPWM_ComplementaryPwmA, /*!< PWM A & PWM B are complementary channels, PWM A generates the signal */ - kPWM_ComplementaryPwmB /*!< PWM A & PWM B are complementary channels, PWM B generates the signal */ -} pwm_chnl_pair_operation_t; - -/*! @brief Options available on how to load the buffered-registers with new values */ -typedef enum _pwm_register_reload -{ - kPWM_ReloadImmediate = 0U, /*!< Buffered-registers get loaded with new values as soon as LDOK bit is set */ - kPWM_ReloadPwmHalfCycle, /*!< Registers loaded on a PWM half cycle */ - kPWM_ReloadPwmFullCycle, /*!< Registers loaded on a PWM full cycle */ - kPWM_ReloadPwmHalfAndFullCycle /*!< Registers loaded on a PWM half & full cycle */ -} pwm_register_reload_t; - -/*! @brief Options available on how to re-enable the PWM output when recovering from a fault */ -typedef enum _pwm_fault_recovery_mode -{ - kPWM_NoRecovery = 0U, /*!< PWM output will stay inactive */ - kPWM_RecoverHalfCycle, /*!< PWM output re-enabled at the first half cycle */ - kPWM_RecoverFullCycle, /*!< PWM output re-enabled at the first full cycle */ - kPWM_RecoverHalfAndFullCycle /*!< PWM output re-enabled at the first half or full cycle */ -} pwm_fault_recovery_mode_t; - -/*! @brief List of PWM interrupt options */ -typedef enum _pwm_interrupt_enable -{ - kPWM_CompareVal0InterruptEnable = (1U << 0), /*!< PWM VAL0 compare interrupt */ - kPWM_CompareVal1InterruptEnable = (1U << 1), /*!< PWM VAL1 compare interrupt */ - kPWM_CompareVal2InterruptEnable = (1U << 2), /*!< PWM VAL2 compare interrupt */ - kPWM_CompareVal3InterruptEnable = (1U << 3), /*!< PWM VAL3 compare interrupt */ - kPWM_CompareVal4InterruptEnable = (1U << 4), /*!< PWM VAL4 compare interrupt */ - kPWM_CompareVal5InterruptEnable = (1U << 5), /*!< PWM VAL5 compare interrupt */ - kPWM_CaptureX0InterruptEnable = (1U << 6), /*!< PWM capture X0 interrupt */ - kPWM_CaptureX1InterruptEnable = (1U << 7), /*!< PWM capture X1 interrupt */ - kPWM_CaptureB0InterruptEnable = (1U << 8), /*!< PWM capture B0 interrupt */ - kPWM_CaptureB1InterruptEnable = (1U << 9), /*!< PWM capture B1 interrupt */ - kPWM_CaptureA0InterruptEnable = (1U << 10), /*!< PWM capture A0 interrupt */ - kPWM_CaptureA1InterruptEnable = (1U << 11), /*!< PWM capture A1 interrupt */ - kPWM_ReloadInterruptEnable = (1U << 12), /*!< PWM reload interrupt */ - kPWM_ReloadErrorInterruptEnable = (1U << 13), /*!< PWM reload error interrupt */ - kPWM_Fault0InterruptEnable = (1U << 16), /*!< PWM fault 0 interrupt */ - kPWM_Fault1InterruptEnable = (1U << 17), /*!< PWM fault 1 interrupt */ - kPWM_Fault2InterruptEnable = (1U << 18), /*!< PWM fault 2 interrupt */ - kPWM_Fault3InterruptEnable = (1U << 19) /*!< PWM fault 3 interrupt */ -} pwm_interrupt_enable_t; - -/*! @brief List of PWM status flags */ -typedef enum _pwm_status_flags -{ - kPWM_CompareVal0Flag = (1U << 0), /*!< PWM VAL0 compare flag */ - kPWM_CompareVal1Flag = (1U << 1), /*!< PWM VAL1 compare flag */ - kPWM_CompareVal2Flag = (1U << 2), /*!< PWM VAL2 compare flag */ - kPWM_CompareVal3Flag = (1U << 3), /*!< PWM VAL3 compare flag */ - kPWM_CompareVal4Flag = (1U << 4), /*!< PWM VAL4 compare flag */ - kPWM_CompareVal5Flag = (1U << 5), /*!< PWM VAL5 compare flag */ - kPWM_CaptureX0Flag = (1U << 6), /*!< PWM capture X0 flag */ - kPWM_CaptureX1Flag = (1U << 7), /*!< PWM capture X1 flag */ - kPWM_CaptureB0Flag = (1U << 8), /*!< PWM capture B0 flag */ - kPWM_CaptureB1Flag = (1U << 9), /*!< PWM capture B1 flag */ - kPWM_CaptureA0Flag = (1U << 10), /*!< PWM capture A0 flag */ - kPWM_CaptureA1Flag = (1U << 11), /*!< PWM capture A1 flag */ - kPWM_ReloadFlag = (1U << 12), /*!< PWM reload flag */ - kPWM_ReloadErrorFlag = (1U << 13), /*!< PWM reload error flag */ - kPWM_RegUpdatedFlag = (1U << 14), /*!< PWM registers updated flag */ - kPWM_Fault0Flag = (1U << 16), /*!< PWM fault 0 flag */ - kPWM_Fault1Flag = (1U << 17), /*!< PWM fault 1 flag */ - kPWM_Fault2Flag = (1U << 18), /*!< PWM fault 2 flag */ - kPWM_Fault3Flag = (1U << 19) /*!< PWM fault 3 flag */ -} pwm_status_flags_t; - -/*! @brief List of PWM DMA options */ -typedef enum _pwm_dma_enable -{ - kPWM_CaptureX0DMAEnable = (1U << 0), /*!< PWM capture X0 DMA */ - kPWM_CaptureX1DMAEnable = (1U << 1), /*!< PWM capture X1 DMA */ - kPWM_CaptureB0DMAEnable = (1U << 2), /*!< PWM capture B0 DMA */ - kPWM_CaptureB1DMAEnable = (1U << 3), /*!< PWM capture B1 DMA */ - kPWM_CaptureA0DMAEnable = (1U << 4), /*!< PWM capture A0 DMA */ - kPWM_CaptureA1DMAEnable = (1U << 5) /*!< PWM capture A1 DMA */ -} pwm_dma_enable_t; - -/*! @brief List of PWM capture DMA enable source select */ -typedef enum _pwm_dma_source_select -{ - kPWM_DMARequestDisable = 0U, /*!< Read DMA requests disabled */ - kPWM_DMAWatermarksEnable, /*!< Exceeding a FIFO watermark sets the DMA read request */ - kPWM_DMALocalSync, /*!< A local sync (VAL1 matches counter) sets the read DMA request */ - kPWM_DMALocalReload /*!< A local reload (STS[RF] being set) sets the read DMA request */ -} pwm_dma_source_select_t; - -/*! @brief PWM FIFO Watermark AND Control */ -typedef enum _pwm_watermark_control -{ - kPWM_FIFOWatermarksOR = 0U, /*!< Selected FIFO watermarks are OR'ed together */ - kPWM_FIFOWatermarksAND /*!< Selected FIFO watermarks are AND'ed together */ -} pwm_watermark_control_t; - -/*! @brief PWM operation mode */ -typedef enum _pwm_mode -{ - kPWM_SignedCenterAligned = 0U, /*!< Signed center-aligned */ - kPWM_CenterAligned, /*!< Unsigned cente-aligned */ - kPWM_SignedEdgeAligned, /*!< Signed edge-aligned */ - kPWM_EdgeAligned /*!< Unsigned edge-aligned */ -} pwm_mode_t; - -/*! @brief PWM output pulse mode, high-true or low-true */ -typedef enum _pwm_level_select -{ - kPWM_HighTrue = 0U, /*!< High level represents "on" or "active" state */ - kPWM_LowTrue /*!< Low level represents "on" or "active" state */ -} pwm_level_select_t; - -/*! @brief PWM output fault status */ -typedef enum _pwm_fault_state -{ - kPWM_PwmFaultState0 = - 0U, /*!< Output is forced to logic 0 state prior to consideration of output polarity control. */ - kPWM_PwmFaultState1, /*!< Output is forced to logic 1 state prior to consideration of output polarity control. */ - kPWM_PwmFaultState2, /*!< Output is tristated. */ - kPWM_PwmFaultState3 /*!< Output is tristated. */ -} pwm_fault_state_t; - -/*! @brief PWM reload source select */ -typedef enum _pwm_reload_source_select -{ - kPWM_LocalReload = 0U, /*!< The local reload signal is used to reload registers */ - kPWM_MasterReload /*!< The master reload signal (from submodule 0) is used to reload */ -} pwm_reload_source_select_t; - -/*! @brief PWM fault clearing options */ -typedef enum _pwm_fault_clear -{ - kPWM_Automatic = 0U, /*!< Automatic fault clearing */ - kPWM_ManualNormal, /*!< Manual fault clearing with no fault safety mode */ - kPWM_ManualSafety /*!< Manual fault clearing with fault safety mode */ -} pwm_fault_clear_t; - -/*! @brief Options for submodule master control operation */ -typedef enum _pwm_module_control -{ - kPWM_Control_Module_0 = (1U << 0), /*!< Control submodule 0's start/stop,buffer reload operation */ - kPWM_Control_Module_1 = (1U << 1), /*!< Control submodule 1's start/stop,buffer reload operation */ - kPWM_Control_Module_2 = (1U << 2), /*!< Control submodule 2's start/stop,buffer reload operation */ - kPWM_Control_Module_3 = (1U << 3) /*!< Control submodule 3's start/stop,buffer reload operation */ -} pwm_module_control_t; - -/*! @brief Structure for the user to define the PWM signal characteristics */ -typedef struct _pwm_signal_param -{ - pwm_channels_t pwmChannel; /*!< PWM channel being configured; PWM A or PWM B */ - uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 - 0=inactive signal(0% duty cycle)... - 100=always active signal (100% duty cycle)*/ - pwm_level_select_t level; /*!< PWM output active level select */ - uint16_t deadtimeValue; /*!< The deadtime value; only used if channel pair is operating in complementary mode */ - pwm_fault_state_t faultState; /*!< PWM output fault status */ -} pwm_signal_param_t; - -/*! - * @brief PWM config structure - * - * This structure holds the configuration settings for the PWM peripheral. To initialize this - * structure to reasonable defaults, call the PWM_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _pwm_config -{ - bool enableDebugMode; /*!< true: PWM continues to run in debug mode; - false: PWM is paused in debug mode */ - bool enableWait; /*!< true: PWM continues to run in WAIT mode; - false: PWM is paused in WAIT mode */ - pwm_init_source_t initializationControl; /*!< Option to initialize the counter */ - pwm_clock_source_t clockSource; /*!< Clock source for the counter */ - pwm_clock_prescale_t prescale; /*!< Pre-scaler to divide down the clock */ - pwm_chnl_pair_operation_t pairOperation; /*!< Channel pair in indepedent or complementary mode */ - pwm_register_reload_t reloadLogic; /*!< PWM Reload logic setup */ - pwm_reload_source_select_t reloadSelect; /*!< Reload source select */ - pwm_load_frequency_t reloadFrequency; /*!< Specifies when to reload, used when user's choice - is not immediate reload */ - pwm_force_output_trigger_t forceTrigger; /*!< Specify which signal will trigger a FORCE_OUT */ -} pwm_config_t; - -/*! @brief Structure for the user to configure the fault input filter. */ -typedef struct _pwm_fault_input_filter_param -{ - uint8_t faultFilterCount; /*!< Fault filter count */ - uint8_t faultFilterPeriod; /*!< Fault filter period;value of 0 will bypass the filter */ - bool faultGlitchStretch; /*!< Fault Glitch Stretch Enable: A logic 1 means that input - fault signals will be stretched to at least 2 IPBus clock cycles */ -} pwm_fault_input_filter_param_t; - -/*! @brief Structure is used to hold the parameters to configure a PWM fault */ -typedef struct _pwm_fault_param -{ - pwm_fault_clear_t faultClearingMode; /*!< Fault clearing mode to use */ - bool faultLevel; /*!< true: Logic 1 indicates fault; - false: Logic 0 indicates fault */ - bool enableCombinationalPath; /*!< true: Combinational Path from fault input is enabled; - false: No combination path is available */ - pwm_fault_recovery_mode_t recoverMode; /*!< Specify when to re-enable the PWM output */ -} pwm_fault_param_t; - -/*! - * @brief Structure is used to hold parameters to configure the capture capability of a signal pin - */ -typedef struct _pwm_input_capture_param -{ - bool captureInputSel; /*!< true: Use the edge counter signal as source - false: Use the raw input signal from the pin as source */ - uint8_t edgeCompareValue; /*!< Compare value, used only if edge counter is used as source */ - pwm_input_capture_edge_t edge0; /*!< Specify which edge causes a capture for input circuitry 0 */ - pwm_input_capture_edge_t edge1; /*!< Specify which edge causes a capture for input circuitry 1 */ - bool enableOneShotCapture; /*!< true: Use one-shot capture mode; - false: Use free-running capture mode */ - uint8_t fifoWatermark; /*!< Watermark level for capture FIFO. The capture flags in - the status register will set if the word count in the FIFO - is greater than this watermark level */ -} pwm_input_capture_param_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the PWM submodule clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the PWM driver. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param config Pointer to user's PWM config structure. - * - * @return kStatus_Success means success; else failed. - */ -status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config); - -/*! - * @brief Gate the PWM submodule clock - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to deinitialize - */ -void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule); - -/*! - * @brief Fill in the PWM config struct with the default settings - * - * The default values are: - * @code - * config->enableDebugMode = false; - * config->enableWait = false; - * config->reloadSelect = kPWM_LocalReload; - * config->clockSource = kPWM_BusClock; - * config->prescale = kPWM_Prescale_Divide_1; - * config->initializationControl = kPWM_Initialize_LocalSync; - * config->forceTrigger = kPWM_Force_Local; - * config->reloadFrequency = kPWM_LoadEveryOportunity; - * config->reloadLogic = kPWM_ReloadImmediate; - * config->pairOperation = kPWM_Independent; - * @endcode - * @param config Pointer to user's PWM config structure. - */ -void PWM_GetDefaultConfig(pwm_config_t *config); - -/*! @}*/ - -/*! - * @name Module PWM output - * @{ - */ -/*! - * @brief Sets up the PWM signals for a PWM submodule. - * - * The function initializes the submodule according to the parameters passed in by the user. The function - * also sets up the value compare registers to match the PWM signal requirements. - * If the dead time insertion logic is enabled, the pulse period is reduced by the - * dead time period specified by the user. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param chnlParams Array of PWM channel parameters to configure the channel(s) - * @param numOfChnls Number of channels to configure, this should be the size of the array passed in. - * Array size should not be more than 2 as each submodule has 2 pins to output PWM - * @param mode PWM operation mode, options available in enumeration ::pwm_mode_t - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz PWM main counter clock in Hz. - * - * @return Returns kStatusFail if there was error setting up the signal; kStatusSuccess otherwise - */ -status_t PWM_SetupPwm(PWM_Type *base, - pwm_submodule_t subModule, - const pwm_signal_param_t *chnlParams, - uint8_t numOfChnls, - pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz); - -/*! - * @brief Updates the PWM signal's dutycycle. - * - * The function updates the PWM dutycyle to the new value that is passed in. - * If the dead time insertion logic is enabled then the pulse period is reduced by the - * dead time period specified by the user. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param pwmSignal Signal (PWM A or PWM B) to update - * @param currPwmMode The current PWM mode set during PWM setup - * @param dutyCyclePercent New PWM pulse width, value should be between 0 to 100 - * 0=inactive signal(0% duty cycle)... - * 100=active signal (100% duty cycle) - */ -void PWM_UpdatePwmDutycycle(PWM_Type *base, - pwm_submodule_t subModule, - pwm_channels_t pwmSignal, - pwm_mode_t currPwmMode, - uint8_t dutyCyclePercent); - -/*! - * @brief Updates the PWM signal's dutycycle with 16-bit accuracy. - * - * The function updates the PWM dutycyle to the new value that is passed in. - * If the dead time insertion logic is enabled then the pulse period is reduced by the - * dead time period specified by the user. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param pwmSignal Signal (PWM A or PWM B) to update - * @param currPwmMode The current PWM mode set during PWM setup - * @param dutyCycle New PWM pulse width, value should be between 0 to 65535 - * 0=inactive signal(0% duty cycle)... - * 65535=active signal (100% duty cycle) - */ -void PWM_UpdatePwmDutycycleHighAccuracy( - PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t dutyCycle); - -/*! @}*/ - -/*! - * @brief Sets up the PWM input capture - * - * Each PWM submodule has 3 pins that can be configured for use as input capture pins. This function - * sets up the capture parameters for each pin and enables the pin for input capture operation. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param pwmChannel Channel in the submodule to setup - * @param inputCaptureParams Parameters passed in to set up the input pin - */ -void PWM_SetupInputCapture(PWM_Type *base, - pwm_submodule_t subModule, - pwm_channels_t pwmChannel, - const pwm_input_capture_param_t *inputCaptureParams); - -/*! - * @brief Sets up the PWM fault input filter. - * - * @param base PWM peripheral base address - * @param faultInputFilterParams Parameters passed in to set up the fault input filter. - */ -void PWM_SetupFaultInputFilter(PWM_Type *base, const pwm_fault_input_filter_param_t *faultInputFilterParams); - -/*! - * @brief Sets up the PWM fault protection. - * - * PWM has 4 fault inputs. - * - * @param base PWM peripheral base address - * @param faultNum PWM fault to configure. - * @param faultParams Pointer to the PWM fault config structure - */ -void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams); - -/*! - * @brief Fill in the PWM fault config struct with the default settings - * - * The default values are: - * @code - * config->faultClearingMode = kPWM_Automatic; - * config->faultLevel = false; - * config->enableCombinationalPath = true; - * config->recoverMode = kPWM_NoRecovery; - * @endcode - * @param config Pointer to user's PWM fault config structure. - */ -void PWM_FaultDefaultConfig(pwm_fault_param_t *config); - -/*! - * @brief Selects the signal to output on a PWM pin when a FORCE_OUT signal is asserted. - * - * The user specifies which channel to configure by supplying the submodule number and whether - * to modify PWM A or PWM B within that submodule. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param pwmChannel Channel to configure - * @param mode Signal to output when a FORCE_OUT is triggered - */ -void PWM_SetupForceSignal(PWM_Type *base, - pwm_submodule_t subModule, - pwm_channels_t pwmChannel, - pwm_force_signal_t mode); - -/*! - * @name Interrupts Interface - * @{ - */ - -/*! - * @brief Enables the selected PWM interrupts - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::pwm_interrupt_enable_t - */ -void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask); - -/*! - * @brief Disables the selected PWM interrupts - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::pwm_interrupt_enable_t - */ -void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask); - -/*! - * @brief Gets the enabled PWM interrupts - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::pwm_interrupt_enable_t - */ -uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule); - -/*! @}*/ - -/*! - * @name DMA Interface - * @{ - */ - -/*! - * @brief Capture DMA Enable Source Select. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param pwm_watermark_control PWM FIFO watermark and control - */ -static inline void PWM_DMAFIFOWatermarkControl(PWM_Type *base, - pwm_submodule_t subModule, - pwm_watermark_control_t pwm_watermark_control) -{ - uint16_t reg = base->SM[subModule].DMAEN; - if (pwm_watermark_control == kPWM_FIFOWatermarksOR) - { - reg &= ~((uint16_t)PWM_DMAEN_FAND_MASK); - } - else - { - reg |= ((uint16_t)PWM_DMAEN_FAND_MASK); - } - base->SM[subModule].DMAEN = reg; -} - -/*! - * @brief Capture DMA Enable Source Select. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param pwm_dma_source_select PWM capture DMA enable source select - */ -static inline void PWM_DMACaptureSourceSelect(PWM_Type *base, - pwm_submodule_t subModule, - pwm_dma_source_select_t pwm_dma_source_select) -{ - uint16_t reg = base->SM[subModule].DMAEN; - - reg &= ~((uint16_t)PWM_DMAEN_CAPTDE_MASK); - reg |= (((uint16_t)pwm_dma_source_select << (uint16_t)PWM_DMAEN_CAPTDE_SHIFT) & (uint16_t)PWM_DMAEN_CAPTDE_MASK); - - base->SM[subModule].DMAEN = reg; -} - -/*! - * @brief Enables or disables the selected PWM DMA Capture read request. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param mask The DMA to enable or disable. This is a logical OR of members of the - * enumeration ::pwm_dma_enable_t - * @param activate true: Enable DMA read request; false: Disable DMA read request - */ -static inline void PWM_EnableDMACapture(PWM_Type *base, pwm_submodule_t subModule, uint16_t mask, bool activate) -{ - uint16_t reg = base->SM[subModule].DMAEN; - if (activate) - { - reg |= (uint16_t)(mask); - } - else - { - reg &= ~((uint16_t)(mask)); - } - base->SM[subModule].DMAEN = reg; -} - -/*! - * @brief Enables or disables the PWM DMA write request. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param activate true: Enable DMA write request; false: Disable DMA write request - */ -static inline void PWM_EnableDMAWrite(PWM_Type *base, pwm_submodule_t subModule, bool activate) -{ - uint16_t reg = base->SM[subModule].DMAEN; - if (activate) - { - reg |= ((uint16_t)PWM_DMAEN_VALDE_MASK); - } - else - { - reg &= ~((uint16_t)PWM_DMAEN_VALDE_MASK); - } - base->SM[subModule].DMAEN = reg; -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the PWM status flags - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::pwm_status_flags_t - */ -uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule); - -/*! - * @brief Clears the PWM status flags - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::pwm_status_flags_t - */ -void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask); - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the PWM counter for a single or multiple submodules. - * - * Sets the Run bit which enables the clocks to the PWM submodule. This function can start multiple - * submodules at the same time. - * - * @param base PWM peripheral base address - * @param subModulesToStart PWM submodules to start. This is a logical OR of members of the - * enumeration ::pwm_module_control_t - */ -static inline void PWM_StartTimer(PWM_Type *base, uint8_t subModulesToStart) -{ - base->MCTRL |= PWM_MCTRL_RUN(subModulesToStart); -} - -/*! - * @brief Stops the PWM counter for a single or multiple submodules. - * - * Clears the Run bit which resets the submodule's counter. This function can stop multiple - * submodules at the same time. - * - * @param base PWM peripheral base address - * @param subModulesToStop PWM submodules to stop. This is a logical OR of members of the - * enumeration ::pwm_module_control_t - */ -static inline void PWM_StopTimer(PWM_Type *base, uint8_t subModulesToStop) -{ - base->MCTRL &= ~(PWM_MCTRL_RUN(subModulesToStop)); -} - -/*! @}*/ - -/*! - * @brief Enables or disables the PWM output trigger. - * - * This function allows the user to enable or disable the PWM trigger. The PWM has 2 triggers. Trigger 0 - * is activated when the counter matches VAL 0, VAL 2, or VAL 4 register. Trigger 1 is activated - * when the counter matches VAL 1, VAL 3, or VAL 5 register. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param valueRegister Value register that will activate the trigger - * @param activate true: Enable the trigger; false: Disable the trigger - */ -static inline void PWM_OutputTriggerEnable(PWM_Type *base, - pwm_submodule_t subModule, - pwm_value_register_t valueRegister, - bool activate) -{ - if (activate) - { - base->SM[subModule].TCTRL |= ((uint16_t)1U << (uint16_t)valueRegister); - } - else - { - base->SM[subModule].TCTRL &= ~((uint16_t)1U << (uint16_t)valueRegister); - } -} - -/*! - * @brief Enables the PWM output trigger. - * - * This function allows the user to enable one or more (VAL0-5) PWM trigger. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param valueRegisterMask Value register mask that will activate one or more (VAL0-5) trigger - * enumeration ::_pwm_value_register_mask - */ -static inline void PWM_ActivateOutputTrigger(PWM_Type *base, pwm_submodule_t subModule, uint16_t valueRegisterMask) -{ - base->SM[subModule].TCTRL |= (PWM_TCTRL_OUT_TRIG_EN_MASK & (valueRegisterMask)); -} - -/*! - * @brief Disables the PWM output trigger. - * - * This function allows the user to disables one or more (VAL0-5) PWM trigger. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param valueRegisterMask Value register mask that will Deactivate one or more (VAL0-5) trigger - * enumeration ::_pwm_value_register_mask - */ -static inline void PWM_DeactivateOutputTrigger(PWM_Type *base, pwm_submodule_t subModule, uint16_t valueRegisterMask) -{ - base->SM[subModule].TCTRL &= ~(PWM_TCTRL_OUT_TRIG_EN_MASK & (valueRegisterMask)); -} - -/*! - * @brief Sets the software control output for a pin to high or low. - * - * The user specifies which channel to modify by supplying the submodule number and whether - * to modify PWM A or PWM B within that submodule. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param pwmChannel Channel to configure - * @param value true: Supply a logic 1, false: Supply a logic 0. - */ -static inline void PWM_SetupSwCtrlOut(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, bool value) -{ - if (value) - { - base->SWCOUT |= - ((uint16_t)1U << (((uint16_t)subModule * (uint16_t)PWM_SUBMODULE_SWCONTROL_WIDTH) + (uint16_t)pwmChannel)); - } - else - { - base->SWCOUT &= - ~((uint16_t)1U << (((uint16_t)subModule * (uint16_t)PWM_SUBMODULE_SWCONTROL_WIDTH) + (uint16_t)pwmChannel)); - } -} - -/*! - * @brief Sets or clears the PWM LDOK bit on a single or multiple submodules - * - * Set LDOK bit to load buffered values into CTRL[PRSC] and the INIT, FRACVAL and VAL registers. The - * values are loaded immediately if kPWM_ReloadImmediate option was choosen during config. Else the - * values are loaded at the next PWM reload point. - * This function can issue the load command to multiple submodules at the same time. - * - * @param base PWM peripheral base address - * @param subModulesToUpdate PWM submodules to update with buffered values. This is a logical OR of - * members of the enumeration ::pwm_module_control_t - * @param value true: Set LDOK bit for the submodule list; false: Clear LDOK bit - */ -static inline void PWM_SetPwmLdok(PWM_Type *base, uint8_t subModulesToUpdate, bool value) -{ - if (value) - { - base->MCTRL |= PWM_MCTRL_LDOK(subModulesToUpdate); - } - else - { - base->MCTRL |= PWM_MCTRL_CLDOK(subModulesToUpdate); - } -} - -/*! - * @brief Set PWM output fault status - * - * These bits determine the fault state for the PWM_A output in fault conditions - * and STOP mode. It may also define the output state in WAIT and DEBUG modes - * depending on the settings of CTRL2[WAITEN] and CTRL2[DBGEN]. - * This function can update PWM output fault status. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param pwmChannel Channel to configure - * @param faultState PWM output fault status - */ -static inline void PWM_SetPwmFaultState(PWM_Type *base, - pwm_submodule_t subModule, - pwm_channels_t pwmChannel, - pwm_fault_state_t faultState) -{ - uint16_t reg = base->SM[subModule].OCTRL; - switch (pwmChannel) - { - case kPWM_PwmA: - reg &= ~((uint16_t)PWM_OCTRL_PWMAFS_MASK); - reg |= (((uint16_t)faultState << (uint16_t)PWM_OCTRL_PWMAFS_SHIFT) & (uint16_t)PWM_OCTRL_PWMAFS_MASK); - break; - case kPWM_PwmB: - reg &= ~((uint16_t)PWM_OCTRL_PWMBFS_MASK); - reg |= (((uint16_t)faultState << (uint16_t)PWM_OCTRL_PWMBFS_SHIFT) & (uint16_t)PWM_OCTRL_PWMBFS_MASK); - break; - case kPWM_PwmX: - reg &= ~((uint16_t)PWM_OCTRL_PWMXFS_MASK); - reg |= (((uint16_t)faultState << (uint16_t)PWM_OCTRL_PWMXFS_SHIFT) & (uint16_t)PWM_OCTRL_PWMXFS_MASK); - break; - default: - assert(false); - break; - } - base->SM[subModule].OCTRL = reg; -} - -/*! - * @brief Set PWM fault disable mapping - * - * Each of the four bits of this read/write field is one-to-one associated - * with the four FAULTx inputs of fault channel 0/1. The PWM output will be turned - * off if there is a logic 1 on an FAULTx input and a 1 in the corresponding - * bit of this field. A reset sets all bits in this field. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param pwmChannel PWM channel to configure - * @param pwm_fault_channels PWM fault channel to configure - * @param value Fault disable mapping mask value - * enumeration ::pwm_fault_disable_t - */ -static inline void PWM_SetupFaultDisableMap(PWM_Type *base, - pwm_submodule_t subModule, - pwm_channels_t pwmChannel, - pwm_fault_channels_t pwm_fault_channels, - uint16_t value) -{ - uint16_t reg = base->SM[subModule].DISMAP[pwm_fault_channels]; - switch (pwmChannel) - { - case kPWM_PwmA: - reg &= ~((uint16_t)PWM_DISMAP_DIS0A_MASK); - reg |= (((uint16_t)(value) << (uint16_t)PWM_DISMAP_DIS0A_SHIFT) & (uint16_t)PWM_DISMAP_DIS0A_MASK); - break; - case kPWM_PwmB: - reg &= ~((uint16_t)PWM_DISMAP_DIS0B_MASK); - reg |= (((uint16_t)(value) << (uint16_t)PWM_DISMAP_DIS0B_SHIFT) & (uint16_t)PWM_DISMAP_DIS0B_MASK); - break; - case kPWM_PwmX: - reg &= ~((uint16_t)PWM_DISMAP_DIS0X_MASK); - reg |= (((uint16_t)(value) << (uint16_t)PWM_DISMAP_DIS0X_SHIFT) & (uint16_t)PWM_DISMAP_DIS0X_MASK); - break; - default: - assert(false); - break; - } - base->SM[subModule].DISMAP[pwm_fault_channels] = reg; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_PWM_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_reset.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_reset.c deleted file mode 100644 index 411cdf3c048..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_reset.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#include "fsl_reset.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.reset" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - -/*! - * brief Assert reset to peripheral. - * - * Asserts reset signal to specified peripheral module. - * - * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_SetPeripheralReset(reset_ip_name_t peripheral) -{ - const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; - const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); - const uint32_t bitMask = 1UL << bitPos; - uint32_t volatile *pointPresetCtrl = &SYSCON->PRESETCTRL0; - - assert(bitPos < 32u); - - /* reset register is in SYSCON */ - /* set bit */ - SYSCON->PRESETCTRLSET[regIndex] = bitMask; - /* wait until it reads 0b1 */ - while (0u == (pointPresetCtrl[regIndex] & bitMask)) - { - } -} - -/*! - * brief Clear reset to peripheral. - * - * Clears reset signal to specified peripheral module, allows it to operate. - * - * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) -{ - const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; - const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); - const uint32_t bitMask = 1UL << bitPos; - uint32_t volatile *pointPresetCtrl = &SYSCON->PRESETCTRL0; - - assert(bitPos < 32u); - - /* reset register is in SYSCON */ - - /* clear bit */ - SYSCON->PRESETCTRLCLR[regIndex] = bitMask; - /* wait until it reads 0b0 */ - while (bitMask == (pointPresetCtrl[regIndex] & bitMask)) - { - } -} - -/*! - * brief Reset peripheral module. - * - * Reset peripheral module. - * - * param peripheral Peripheral to reset. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_PeripheralReset(reset_ip_name_t peripheral) -{ - RESET_SetPeripheralReset(peripheral); - RESET_ClearPeripheralReset(peripheral); -} - -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_reset.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_reset.h deleted file mode 100644 index 4363f678ed3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_reset.h +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_RESET_H_ -#define _FSL_RESET_H_ - -#include -#include -#include -#include -#include "fsl_device_registers.h" - -/*! - * @addtogroup reset - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief reset driver version 2.0.0. */ -#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! - * @brief Enumeration for peripheral reset control bits - * - * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers - */ -typedef enum _SYSCON_RSTn -{ - kROM_RST_SHIFT_RSTn = (0 | (1U)), /**< ROM reset control .*/ - kSRAM_CTRL1_RST_SHIFT_RSTn = (0 | (3U)), /**< SRAM Controller 1 reset control .*/ - kSRAM_CTRL2_RST_SHIFT_RSTn = (0 | (4U)), /**< SRAM Controller 2 reset control .*/ - kSRAM_CTRL3_RST_SHIFT_RSTn = (0 | (5U)), /**< SRAM Controller 3 reset control .*/ - kSRAM_CTRL4_RST_SHIFT_RSTn = (0 | (6U)), /**< SRAM Controller 4 reset control .*/ - kFLASH_RST_SHIFT_RSTn = (0 | (7U)), /**< FLASH reset control .*/ - kFMC_RST_SHIFT_RSTn = (0 | (8U)), /**< FMC reset control .*/ - kFLEXSPI_RST_SHIFT_RSTn = (0 | (10U)), /**< FLEXSPI reset control .*/ - kMUX_RST_SHIFT_RSTn = (0 | (11U)), /**< MUX reset control .*/ - kIOCON_RST_SHIFT_RSTn = (0 | (13U)), /**< IOCON reset control .*/ - kGPIO0_RST_SHIFT_RSTn = (0 | (14U)), /**< GPIO0 reset control .*/ - kGPIO1_RST_SHIFT_RSTn = (0 | (15U)), /**< GPIO1 reset control .*/ - kGPIO2_RST_SHIFT_RSTn = (0 | (16U)), /**< GPIO2 reset control .*/ - kGPIO3_RST_SHIFT_RSTn = (0 | (17U)), /**< GPIO3 reset control .*/ - kPINT_RST_SHIFT_RSTn = (0 | (18U)), /**< PINT reset control .*/ - kGINT_RST_SHIFT_RSTn = (0 | (19U)), /**< GINT reset control .*/ - kDMA0_RST_SHIFT_RSTn = (0 | (20U)), /**< DMA0 reset control .*/ - kCRC_RST_SHIFT_RSTn = (0 | (21U)), /**< CRC reset control .*/ - kWWDT_RST_SHIFT_RSTn = (0 | (22U)), /**< WWDT reset control .*/ - kRTC_RST_SHIFT_RSTn = (0 | (23U)), /**< RTC reset control .*/ - kMAILBOX_RST_SHIFT_RSTn = (0 | (26U)), /**< MAILBOX reset control .*/ - kADC0_RST_SHIFT_RSTn = (0 | (27U)), /**< ADC0 reset control .*/ - kADC1_RST_SHIFT_RSTn = (0 | (28U)), /**< ADC1 reset control .*/ - kDAC0_RST_SHIFT_RSTn = (0 | (29U)), /**< DAC0 reset control .*/ - - kMRT_RST_SHIFT_RSTn = (0x10000 | (0U)), /**< MRT reset control .*/ - kOSTIMER_RST_SHIFT_RSTn = (0x10000 | (1U)), /**< OSTIMER reset control .*/ - kSCT_RST_SHIFT_RSTn = (0x10000 | (2U)), /**< SCT reset control .*/ - kMCAN_RST_SHIFT_RSTn = (0x10000 | (7U)), /**< MCAN reset control .*/ - kUTICK_RST_SHIFT_RSTn = (0x10000 | (10U)), /**< UTICK reset control .*/ - kFC0_RST_SHIFT_RSTn = (0x10000 | (11U)), /**< FC0 reset control .*/ - kFC1_RST_SHIFT_RSTn = (0x10000 | (12U)), /**< FC1 reset control .*/ - kFC2_RST_SHIFT_RSTn = (0x10000 | (13U)), /**< FC2 reset control .*/ - kFC3_RST_SHIFT_RSTn = (0x10000 | (14U)), /**< FC3 reset control .*/ - kFC4_RST_SHIFT_RSTn = (0x10000 | (15U)), /**< FC4 reset control .*/ - kFC5_RST_SHIFT_RSTn = (0x10000 | (16U)), /**< FC5 reset control .*/ - kFC6_RST_SHIFT_RSTn = (0x10000 | (17U)), /**< FC6 reset control .*/ - kFC7_RST_SHIFT_RSTn = (0x10000 | (18U)), /**< FC7 reset control .*/ - kDMIC_RST_SHIFT_RSTn = (0x10000 | (19U)), /**< DMIC reset control .*/ - kCTIMER2_RST_SHIFT_RSTn = (0x10000 | (22U)), /**< TIMER2 reset control .*/ - kUSB0_DEV_RST_SHIFT_RSTn = (0x10000 | (25U)), /**< USB0_DEV reset control .*/ - kCTIMER0_RST_SHIFT_RSTn = (0x10000 | (26U)), /**< TIMER0 reset control .*/ - kCTIMER1_RST_SHIFT_RSTn = (0x10000 | (27U)), /**< TIMER1 reset control .*/ - - kDMA1_RST_SHIFT_RSTn = (0x20000 | (1U)), /**< DMA1 reset control .*/ - kCMP_RST_SHIFT_RSTn = (0x20000 | (2U)), /**< CMP reset control .*/ - kFREQME_RST_SHIFT_RSTn = (0x20000 | (8U)), /**< FREQME reset control .*/ - kCDOG_RST_SHIFT_RSTn = (0x20000 | (11U)), /**< Code Watchdog reset control */ - kRNG_RST_SHIFT_RSTn = (0x20000 | (13U)), /**< RNG reset control .*/ - kSYSCTL_RST_SHIFT_RSTn = (0x20000 | (15U)), /**< SYSCTL reset control .*/ - kUSB0HMR_RST_SHIFT_RSTn = (0x20000 | (16U)), /**< USB0HMR reset control */ - kUSB0HSL_RST_SHIFT_RSTn = (0x20000 | (17U)), /**< USB0HSL reset control */ - kCSS_RST_SHIFT_RSTn = (0x20000 | (18U)), /**< CSS reset control .*/ - kPOWERQUAD_RST_SHIFT_RSTn = (0x20000 | (19U)), /**< PowerQuad reset control .*/ - kCTIMER3_RST_SHIFT_RSTn = (0x20000 | (21U)), /**< TIMER3 reset control .*/ - kCTIMER4_RST_SHIFT_RSTn = (0x20000 | (22U)), /**< TIMER4 reset control .*/ - kPUF_RST_SHIFT_RSTn = (0x20000 | (23U)), /**< PUF reset control */ - kPKC_RST_SHIFT_RSTn = (0x20000 | (24U)), /**< PKC reset control .*/ - kANACTRL_RST_SHIFT_RSTn = (0x20000 | (27U)), /**< ANACTRL reset control .*/ - kHSLSPI_RST_SHIFT_RSTn = (0x20000 | (28U)), /**< HS LSPI reset control */ - kGPIOSEC_RST_SHIFT_RSTn = (0x20000 | (29U)), /**< GPIO_SEC reset control .*/ - kGPIOSECINT_RST_SHIFT_RSTn = (0x20000 | (30U)), /**< GPIO secure int reset control .*/ - - kI3C0_RST_SHIFT_RSTn = (0x30000 | (0U)), /**< I3C0 reset control .*/ - kENC0_RST_SHIFT_RSTn = (0x30000 | (3U)), /**< ENC0 reset control .*/ - kENC1_RST_SHIFT_RSTn = (0x30000 | (4U)), /**< ENC1 reset control .*/ - kPWM0_RST_SHIFT_RSTn = (0x30000 | (5U)), /**< PWM0 reset control .*/ - kPWM1_RST_SHIFT_RSTn = (0x30000 | (6U)), /**< PWM1 reset control .*/ - kAOI0_RST_SHIFT_RSTn = (0x30000 | (7U)), /**< AOI0 reset control .*/ - kAOI1_RST_SHIFT_RSTn = (0x30000 | (8U)), /**< AOI1 reset control .*/ - kFTM0_RST_SHIFT_RSTn = (0x30000 | (9U)), /**< FTM0 reset control .*/ - kDAC1_RST_SHIFT_RSTn = (0x30000 | (10U)), /**< DAC1 reset control .*/ - kDAC2_RST_SHIFT_RSTn = (0x30000 | (11U)), /**< DAC2 reset control .*/ - kOPAMP0_RST_SHIFT_RSTn = (0x30000 | (12U)), /**< OPAMP0 reset control .*/ - kOPAMP1_RST_SHIFT_RSTn = (0x30000 | (13U)), /**< OPAMP1 reset control .*/ - kOPAMP2_RST_SHIFT_RSTn = (0x30000 | (14U)), /**< OPAMP2 reset control .*/ - kHSCMP0_RST_SHIFT_RSTn = (0x30000 | (15U)), /**< HSCMP0 reset control .*/ - kHSCMP1_RST_SHIFT_RSTn = (0x30000 | (16U)), /**< HSCMP1 reset control .*/ - kHSCMP2_RST_SHIFT_RSTn = (0x30000 | (17U)), /**< HSCMP2 reset control .*/ - kVREF_RST_SHIFT_RSTn = (0x30000 | (18U)), /**< VREF reset control .*/ -} SYSCON_RSTn_t; - -/** Array initializers with peripheral reset bits **/ -#define ADC_RSTS \ - { \ - kADC0_RST_SHIFT_RSTn, kADC1_RST_SHIFT_RSTn \ - } /* Reset bits for ADC peripheral */ -#define MCAN_RSTS \ - { \ - kMCAN_RST_SHIFT_RSTn \ - } /* Reset bits for CAN peripheral */ -#define CRC_RSTS \ - { \ - kCRC_RST_SHIFT_RSTn \ - } /* Reset bits for CRC peripheral */ -#define CTIMER_RSTS \ - { \ - kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \ - kCTIMER4_RST_SHIFT_RSTn \ - } /* Reset bits for CTIMER peripheral */ -#define DMA_RSTS_N \ - { \ - kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \ - } /* Reset bits for DMA peripheral */ - -#define FLEXCOMM_RSTS \ - { \ - kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ - kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kHSLSPI_RST_SHIFT_RSTn \ - } /* Reset bits for FLEXCOMM peripheral */ -#define GINT_RSTS \ - { \ - kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ - } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ -#define GPIO_RSTS_N \ - { \ - kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn \ - } /* Reset bits for GPIO peripheral */ -#define INPUTMUX_RSTS \ - { \ - kMUX_RST_SHIFT_RSTn \ - } /* Reset bits for INPUTMUX peripheral */ -#define IOCON_RSTS \ - { \ - kIOCON_RST_SHIFT_RSTn \ - } /* Reset bits for IOCON peripheral */ -#define FLASH_RSTS \ - { \ - kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ - } /* Reset bits for Flash peripheral */ -#define MRT_RSTS \ - { \ - kMRT_RST_SHIFT_RSTn \ - } /* Reset bits for MRT peripheral */ -#define PINT_RSTS \ - { \ - kPINT_RST_SHIFT_RSTn, kGPIO_SEC_INT_RST_SHIFT_RSTn \ - } /* Reset bits for PINT peripheral */ -#define CDOG_RSTS \ - { \ - kCDOG_RST_SHIFT_RSTn \ - } /* Reset bits for CDOG peripheral */ -#define RNG_RSTS \ - { \ - kRNG_RST_SHIFT_RSTn \ - } /* Reset bits for RNG peripheral */ -#define SCT_RSTS \ - { \ - kSCT_RST_SHIFT_RSTn \ - } /* Reset bits for SCT peripheral */ -#define USB0D_RST \ - { \ - kUSB0_DEV_RST_SHIFT_RSTn \ - } /* Reset bits for USB0D peripheral */ -#define USB0HMR_RST \ - { \ - kUSB0HMR_RST_SHIFT_RSTn \ - } /* Reset bits for USB0HMR peripheral */ -#define USB0HSL_RST \ - { \ - kUSB0HSL_RST_SHIFT_RSTn \ - } /* Reset bits for USB0HSL peripheral */ -#define UTICK_RSTS \ - { \ - kUTICK_RST_SHIFT_RSTn \ - } /* Reset bits for UTICK peripheral */ -#define WWDT_RSTS \ - { \ - kWWDT_RST_SHIFT_RSTn \ - } /* Reset bits for WWDT peripheral */ -#define OSTIMER_RSTS \ - { \ - kOSTIMER_RST_SHIFT_RSTn \ - } /* Reset bits for OSTIMER peripheral */ -#define I3C_RSTS \ - { \ - kI3C0_RST_SHIFT_RSTn \ - } /* Reset bits for I3C peripheral */ -#define ENC_RSTS \ - { \ - kENC0_RST_SHIFT_RSTn, kENC1_RST_SHIFT_RSTn \ - } /* Reset bits for ENC peripheral */ -#define PWM_RSTS \ - { \ - kPWM0_RST_SHIFT_RSTn, kPWM1_RST_SHIFT_RSTn \ - } /* Reset bits for PWM peripheral */ -#define AOI_RSTS \ - { \ - kAOI0_RST_SHIFT_RSTn, kAOI1_RST_SHIFT_RSTn \ - } /* Reset bits for AOI peripheral */ -#define DAC_RSTS \ - { \ - kDAC0_RST_SHIFT_RSTn, kDAC1_RST_SHIFT_RSTn \ - } /* Reset bits for DAC peripheral */ -#define OPAMP_RSTS \ - { \ - kOPAMP0_RST_SHIFT_RSTn, kOPAMP1_RST_SHIFT_RSTn, kOPAMP2_RST_SHIFT_RSTn \ - } /* Reset bits for OPAMP peripheral */ -#define HSCMP_RSTS \ - { \ - kHSCMP0_RST_SHIFT_RSTn, kHSCMP1_RST_SHIFT_RSTn, kHSCMP2_RST_SHIFT_RSTn \ - } /* Reset bits for HSCMP peripheral */ -#define POWERQUAD_RSTS \ - { \ - kPOWERQUAD_RST_SHIFT_RSTn \ - } /* Reset bits for Powerquad peripheral */ -typedef SYSCON_RSTn_t reset_ip_name_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Assert reset to peripheral. - * - * Asserts reset signal to specified peripheral module. - * - * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_SetPeripheralReset(reset_ip_name_t peripheral); - -/*! - * @brief Clear reset to peripheral. - * - * Clears reset signal to specified peripheral module, allows it to operate. - * - * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); - -/*! - * @brief Reset peripheral module. - * - * Reset peripheral module. - * - * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_PeripheralReset(reset_ip_name_t peripheral); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_RESET_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sctimer.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sctimer.c deleted file mode 100644 index 5ed3445ad58..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sctimer.c +++ /dev/null @@ -1,803 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sctimer.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.sctimer" -#endif - -/*! @brief Typedef for interrupt handler. */ -typedef void (*sctimer_isr_t)(SCT_Type *base); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base SCTimer peripheral base address - * - * @return The SCTimer instance - */ -static uint32_t SCTIMER_GetInstance(SCT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to SCT bases for each instance. */ -static SCT_Type *const s_sctBases[] = SCT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to SCT clocks for each instance. */ -static const clock_ip_name_t s_sctClocks[] = SCT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET -/*! @brief Pointers to SCT resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_sctResets[] = SCT_RSTS_N; -#else -/*! @brief Pointers to SCT resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_sctResets[] = SCT_RSTS; -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/*!< @brief SCTimer event Callback function. */ -static sctimer_event_callback_t s_eventCallback[FSL_FEATURE_SCT_NUMBER_OF_EVENTS]; - -/*!< @brief Keep track of SCTimer event number */ -static uint32_t s_currentEvent; - -/*!< @brief Keep track of SCTimer state number */ -static uint32_t s_currentState; - -/*!< @brief Keep track of SCTimer unify 32-bit or low 16-bit match/capture register number. */ -static uint32_t s_currentMatch; -/*!< @brief Keep track of SCTimer high 16-bit match/capture register number. */ -static uint32_t s_currentMatchhigh; - -/*! @brief Pointer to SCTimer IRQ handler */ -static sctimer_isr_t s_sctimerIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t SCTIMER_GetInstance(SCT_Type *base) -{ - uint32_t instance; - uint32_t sctArrayCount = (sizeof(s_sctBases) / sizeof(s_sctBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < sctArrayCount; instance++) - { - if (s_sctBases[instance] == base) - { - break; - } - } - - assert(instance < sctArrayCount); - - return instance; -} - -/*! - * brief Ungates the SCTimer clock and configures the peripheral for basic operation. - * - * note This API should be called at the beginning of the application using the SCTimer driver. - * - * param base SCTimer peripheral base address - * param config Pointer to the user configuration structure. - * - * return kStatus_Success indicates success; Else indicates failure. - */ -status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config) -{ - assert(NULL != config); - - uint32_t i; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the SCTimer clock*/ - CLOCK_EnableClock(s_sctClocks[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_sctResets[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - - /* Setup the counter operation. For Current Driver interface SCTIMER_Init don't know detail - * frequency of input clock, but User know it. So the INSYNC have to set by user level. */ - base->CONFIG = SCT_CONFIG_CKSEL(config->clockSelect) | SCT_CONFIG_CLKMODE(config->clockMode) | - SCT_CONFIG_UNIFY(config->enableCounterUnify) | SCT_CONFIG_INSYNC(config->inputsync); - - /* Write to the control register, keep the counters halted. */ - base->CTRL = - SCT_CTRL_BIDIR_L(config->enableBidirection_l) | SCT_CTRL_PRE_L(config->prescale_l) | SCT_CTRL_HALT_L_MASK; - /* Clear the counter after changing the PRE value. */ - base->CTRL |= SCT_CTRL_CLRCTR_L_MASK; - - if (!(config->enableCounterUnify)) - { - base->CTRL |= - SCT_CTRL_BIDIR_H(config->enableBidirection_h) | SCT_CTRL_PRE_H(config->prescale_h) | SCT_CTRL_HALT_H_MASK; - base->CTRL |= SCT_CTRL_CLRCTR_H_MASK; - } - - /* Initial state of channel output */ - base->OUTPUT = config->outInitState; - - /* Clear the global variables */ - s_currentEvent = 0U; - s_currentState = 0U; - s_currentMatch = 0U; - s_currentMatchhigh = 0U; - - /* Clear the callback array */ - for (i = 0; i < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) - { - s_eventCallback[i] = NULL; - } - - /* Save interrupt handler */ - s_sctimerIsr = SCTIMER_EventHandleIRQ; - - return kStatus_Success; -} - -/*! - * brief Gates the SCTimer clock. - * - * param base SCTimer peripheral base address - */ -void SCTIMER_Deinit(SCT_Type *base) -{ - /* Halt the counters */ - base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the SCTimer clock*/ - CLOCK_DisableClock(s_sctClocks[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Fills in the SCTimer configuration structure with the default settings. - * - * The default values are: - * code - * config->enableCounterUnify = true; - * config->clockMode = kSCTIMER_System_ClockMode; - * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - * config->enableBidirection_l = false; - * config->enableBidirection_h = false; - * config->prescale_l = 0U; - * config->prescale_h = 0U; - * config->outInitState = 0U; - * config->inputsync = 0xFU; - * endcode - * param config Pointer to the user configuration structure. - */ -void SCTIMER_GetDefaultConfig(sctimer_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* SCT operates as a unified 32-bit counter */ - config->enableCounterUnify = true; - /* System clock clocks the entire SCT module */ - config->clockMode = kSCTIMER_System_ClockMode; - /* This is used only by certain clock modes */ - config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - /* Up count mode only for the unified counter */ - config->enableBidirection_l = false; - /* Up count mode only for Counte_H */ - config->enableBidirection_h = false; - /* Prescale factor of 1 */ - config->prescale_l = 0U; - /* Prescale factor of 1 for Counter_H*/ - config->prescale_h = 0U; - /* Clear outputs */ - config->outInitState = 0U; - /* Default value is 0xFU, it can be clear as 0 when speical conditions met. - * Condition can be clear as 0: (for all Clock Modes): - * (1) The corresponding input is already synchronous to the SCTimer/PWM clock. - * (2) The SCTimer/PWM clock frequency does not exceed 100 MHz. - * Note: The SCTimer/PWM clock is the bus/system clock for CKMODE 0-2 or asynchronous input - * clock for CKMODE3. - * Another condition can be clear as 0: (for CKMODE2 only) - * (1) The corresponding input is synchronous to the designated CKMODE2 input clock. - * (2) The CKMODE2 input clock frequency is less than one-third the frequency of the bus/system clock. - * Default value set as 0U, input0~input3 are set as bypasses. */ - config->inputsync = 0xFU; -} - -/*! - * brief Configures the PWM signal parameters. - * - * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This - * function will create 2 events; one of the events will trigger on match with the pulse value - * and the other will trigger when the counter matches the PWM period. The PWM period event is - * also used as a limit event to reset the counter or change direction. Both events are enabled - * for the same state. The state number can be retrieved by calling the function - * SCTIMER_GetCurrentStateNumber(). - * The counter is set to operate as one 32-bit counter (unify bit is set to 1). - * The counter operates in bi-directional mode when generating a center-aligned PWM. - * - * note When setting PWM output from multiple output pins, they all should use the same PWM mode - * i.e all PWM's should be either edge-aligned or center-aligned. - * When using this API, the PWM signal frequency of all the initialized channels must be the same. - * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the - * API's pwmFreq_Hz. - * - * param base SCTimer peripheral base address - * param pwmParams PWM parameters to configure the output - * param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t - * param pwmFreq_Hz PWM signal frequency in Hz - * param srcClock_Hz SCTimer counter clock in Hz - * param event Pointer to a variable where the PWM period event number is stored - * - * return kStatus_Success on success - * kStatus_Fail If we have hit the limit in terms of number of events created or if - * an incorrect PWM dutycylce is passed in. - */ -status_t SCTIMER_SetupPwm(SCT_Type *base, - const sctimer_pwm_signal_param_t *pwmParams, - sctimer_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - uint32_t *event) -{ - assert(NULL != pwmParams); - assert(0U != srcClock_Hz); - assert(0U != pwmFreq_Hz); - assert((uint32_t)pwmParams->output < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - - /* If we do not have enough events available (this function will create two events), - * the function will return fail. - */ - status_t status = kStatus_Fail; - status_t status2; - uint32_t period, pulsePeriod = 0; - uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1U); - uint32_t periodEvent = 0, pulseEvent = 0; - uint32_t reg; - - if ((s_currentEvent + 2U) <= (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS) - { - /* Use bi-directional mode for center-aligned PWM */ - if (mode == kSCTIMER_CenterAlignedPwm) - { - base->CTRL |= SCT_CTRL_BIDIR_L_MASK; - } - - /* Calculate PWM period match value */ - if (mode == kSCTIMER_EdgeAlignedPwm) - { - period = (sctClock / pwmFreq_Hz) - 1U; - } - else - { - period = sctClock / (pwmFreq_Hz * 2U); - } - - /* Calculate pulse width and period match value: - * For EdgeAlignedPwm, "pulsePeriod = 0" results in 0% dutycyle, "pulsePeriod = period - 1U" results in 100% - * dutycyle. For CenterAlignedPwm, , "pulsePeriod = 0" results in 0% dutycyle, "pulsePeriod = period + 2U" - * results in 100% dutycyle. - */ - - pulsePeriod = (uint32_t)(((uint64_t)period * pwmParams->dutyCyclePercent) / 100U); - - if (pwmParams->dutyCyclePercent >= 100U) - { - if (mode == kSCTIMER_EdgeAlignedPwm) - { - pulsePeriod = period + 2U; - } - else - { - pulsePeriod = period - 1U; - } - } - - /* Schedule an event when we reach the PWM period */ - status = - SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, period, 0, kSCTIMER_Counter_U, &periodEvent); - - /* Schedule an event when we reach the pulse width */ - status2 = SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, pulsePeriod, 0, kSCTIMER_Counter_U, - &pulseEvent); - - if ((kStatus_Success == status) && (kStatus_Success == status2)) - { - /* Reset the counter when we reach the PWM period */ - SCTIMER_SetupCounterLimitAction(base, kSCTIMER_Counter_U, periodEvent); - - /* Return the period event to the user */ - *event = periodEvent; - - /* For high-true level */ - if ((uint32_t)pwmParams->level == (uint32_t)kSCTIMER_HighTrue) - { - /* Set the initial output level to low which is the inactive state */ - base->OUTPUT &= ~(1UL << (uint32_t)pwmParams->output); - - if (mode == kSCTIMER_EdgeAlignedPwm) - { - /* Set the output when we reach the PWM period */ - SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, periodEvent); - /* Clear the output when we reach the PWM pulse value */ - SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, pulseEvent); - } - else - { - /* Clear the output when we reach the PWM pulse event */ - SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, pulseEvent); - /* Reverse output when down counting */ - reg = base->OUTPUTDIRCTRL; - reg &= ~((uint32_t)SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2U * (uint32_t)pwmParams->output)); - reg |= (1UL << (2U * (uint32_t)pwmParams->output)); - base->OUTPUTDIRCTRL = reg; - } - } - /* For low-true level */ - else - { - /* Set the initial output level to high which is the inactive state */ - base->OUTPUT |= (1UL << (uint32_t)pwmParams->output); - - if (mode == kSCTIMER_EdgeAlignedPwm) - { - /* Clear the output when we reach the PWM period */ - SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, periodEvent); - /* Set the output when we reach the PWM pulse value */ - SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, pulseEvent); - } - else - { - /* Set the output when we reach the PWM pulse event */ - SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, pulseEvent); - /* Reverse output when down counting */ - reg = base->OUTPUTDIRCTRL; - reg &= ~((uint32_t)SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2U * (uint32_t)pwmParams->output)); - reg |= (1UL << (2U * (uint32_t)pwmParams->output)); - base->OUTPUTDIRCTRL = reg; - } - } - } - else - { - status = kStatus_Fail; - } - } - - return status; -} - -/*! - * brief Updates the duty cycle of an active PWM signal. - * - * Before calling this function, the counter is set to operate as one 32-bit counter (unify bit is set to 1). - * - * param base SCTimer peripheral base address - * param output The output to configure - * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 - * param event Event number associated with this PWM signal. This was returned to the user by the - * function SCTIMER_SetupPwm(). - */ -void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event) - -{ - assert(dutyCyclePercent <= 100U); - assert((uint32_t)output < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - - uint32_t periodMatchReg, pulseMatchReg; - uint32_t pulsePeriod = 0, period; - - /* Retrieve the match register number for the PWM period */ - periodMatchReg = base->EV[event].CTRL & SCT_EV_CTRL_MATCHSEL_MASK; - - /* Retrieve the match register number for the PWM pulse period */ - pulseMatchReg = base->EV[event + 1U].CTRL & SCT_EV_CTRL_MATCHSEL_MASK; - - period = base->MATCH[periodMatchReg]; - - /* Calculate pulse width and period match value: - * For EdgeAlignedPwm, "pulsePeriod = 0" results in 0% dutycyle, "pulsePeriod = period - 1U" results in 100% - * dutycyle. For CenterAlignedPwm, , "pulsePeriod = 0" results in 0% dutycyle, "pulsePeriod = period + 2U" - * results in 100% dutycyle. - */ - pulsePeriod = (uint32_t)(((uint64_t)period * dutyCyclePercent) / 100U); - - if (dutyCyclePercent == 100U) - { - if (0U == (base->CTRL & SCT_CTRL_BIDIR_L_MASK)) - { - pulsePeriod = period + 2U; - } - else - { - pulsePeriod = period - 1U; - } - } - - /* Stop the counter before updating match register */ - SCTIMER_StopTimer(base, (uint32_t)kSCTIMER_Counter_U); - - /* Update dutycycle */ - base->MATCH[pulseMatchReg] = SCT_MATCH_MATCHn_L(pulsePeriod); - base->MATCHREL[pulseMatchReg] = SCT_MATCHREL_RELOADn_L(pulsePeriod); - - /* Restart the counter */ - SCTIMER_StartTimer(base, (uint32_t)kSCTIMER_Counter_U); -} - -/*! - * brief Create an event that is triggered on a match or IO and schedule in current state. - * - * This function will configure an event using the options provided by the user. If the event type uses - * the counter match, then the function will set the user provided match value into a match register - * and put this match register number into the event control register. - * The event is enabled for the current state and the event number is increased by one at the end. - * The function returns the event number; this event number can be used to configure actions to be - * done when this event is triggered. - * - * param base SCTimer peripheral base address - * param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t - * param matchValue The match value that will be programmed to a match register - * param whichIO The input or output that will be involved in event triggering. This field - * is ignored if the event type is "match only" - * param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * param event Pointer to a variable where the new event number is stored - * - * return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of events created or - if we have reached the limit in terms of number of match registers - */ -status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, - sctimer_event_t howToMonitor, - uint32_t matchValue, - uint32_t whichIO, - sctimer_counter_t whichCounter, - uint32_t *event) -{ - uint32_t combMode = (((uint32_t)howToMonitor & SCT_EV_CTRL_COMBMODE_MASK) >> SCT_EV_CTRL_COMBMODE_SHIFT); - uint32_t currentCtrlVal = (uint32_t)howToMonitor; - status_t status = kStatus_Success; - - if (s_currentEvent < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS) - { - if (2U == combMode) - { - base->EV[s_currentEvent].CTRL = currentCtrlVal | SCT_EV_CTRL_IOSEL(whichIO); - } - else - { - if ((0U == combMode) || (3U == combMode)) - { - currentCtrlVal |= SCT_EV_CTRL_IOSEL(whichIO); - } - - if ((kSCTIMER_Counter_L == whichCounter) && (0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) - { - if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatch); - - /* Use Counter_L bits if user wants to setup the Low counter */ - base->MATCH_ACCESS16BIT[s_currentMatch].MATCHL = (uint16_t)matchValue; - base->MATCHREL_ACCESS16BIT[s_currentMatch].MATCHRELL = (uint16_t)matchValue; - base->EV[s_currentEvent].CTRL = currentCtrlVal; - - /* Increment the match register number */ - s_currentMatch++; - } - else - { - /* An error would occur if we have hit the limit in terms of number of match registers */ - status = kStatus_Fail; - } - } - else if ((kSCTIMER_Counter_H == whichCounter) && (0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) - { - if (s_currentMatchhigh < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatchhigh); - - /* Use Counter_H bits if user wants to setup the High counter */ - currentCtrlVal |= SCT_EV_CTRL_HEVENT(1U); - base->MATCH_ACCESS16BIT[s_currentMatchhigh].MATCHH = (uint16_t)matchValue; - base->MATCHREL_ACCESS16BIT[s_currentMatchhigh].MATCHRELH = (uint16_t)matchValue; - - base->EV[s_currentEvent].CTRL = currentCtrlVal; - /* Increment the match register number */ - s_currentMatchhigh++; - } - else - { - /* An error would occur if we have hit the limit in terms of number of match registers */ - status = kStatus_Fail; - } - } - else if ((kSCTIMER_Counter_U == whichCounter) && (0U != (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) - { - if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - /* Use Counter_L bits if counter is operating in 32-bit mode */ - currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatch); - - base->MATCH[s_currentMatch] = matchValue; - base->MATCHREL[s_currentMatch] = matchValue; - base->EV[s_currentEvent].CTRL = currentCtrlVal; - - /* Increment the match register number */ - s_currentMatch++; - } - else - { - /* An error would occur if we have hit the limit in terms of number of match registers */ - status = kStatus_Fail; - } - } - else - { - /* The used counter must match the CONFIG[UNIFY] bit selection */ - status = kStatus_Fail; - } - } - - if (kStatus_Success == status) - { - /* Enable the event in the current state */ - base->EV[s_currentEvent].STATE = (1UL << s_currentState); - - /* Return the event number */ - *event = s_currentEvent; - - /* Increment the event number */ - s_currentEvent++; - } - } - else - { - /* An error would occur if we have hit the limit in terms of number of events created */ - status = kStatus_Fail; - } - - return status; -} - -/*! - * brief Enable an event in the current state. - * - * This function will allow the event passed in to trigger in the current state. The event must - * be created earlier by either calling the function SCTIMER_SetupPwm() or function - * SCTIMER_CreateAndScheduleEvent() . - * - * param base SCTimer peripheral base address - * param event Event number to enable in the current state - * - */ -void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event) -{ - /* Enable event in the current state */ - base->EV[event].STATE |= (1UL << s_currentState); -} - -/*! - * brief Increase the state by 1 - * - * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new - * state. - * - * param base SCTimer peripheral base address - * - * return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of states used - - */ -status_t SCTIMER_IncreaseState(SCT_Type *base) -{ - status_t status = kStatus_Success; - - /* Return an error if we have hit the limit in terms of states used */ - if (s_currentState >= (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES) - { - status = kStatus_Fail; - } - else - { - s_currentState++; - } - - return status; -} - -/*! - * brief Provides the current state - * - * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). - * - * param base SCTimer peripheral base address - * - * return The current state - */ -uint32_t SCTIMER_GetCurrentState(SCT_Type *base) -{ - return s_currentState; -} - -/*! - * brief Toggle the output level. - * - * This change in the output level is triggered by the event number that is passed in by the user. - * - * param base SCTimer peripheral base address - * param whichIO The output to toggle - * param event Event number that will trigger the output change - */ -void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - uint32_t reg; - - /* Set the same event to set and clear the output */ - base->OUT[whichIO].CLR |= (1UL << event); - base->OUT[whichIO].SET |= (1UL << event); - - /* Set the conflict resolution to toggle output */ - reg = base->RES; - reg &= ~(((uint32_t)SCT_RES_O0RES_MASK) << (2U * whichIO)); - reg |= ((uint32_t)(kSCTIMER_ResolveToggle)) << (2U * whichIO); - base->RES = reg; -} - -/*! - * brief Setup capture of the counter value on trigger of a selected event - * - * param base SCTimer peripheral base address - * param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * param captureRegister Pointer to a variable where the capture register number will be returned. User - * can read the captured value from this register when the specified event is triggered. - * param event Event number that will trigger the capture - * - * return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of match/capture registers available - */ -status_t SCTIMER_SetupCaptureAction(SCT_Type *base, - sctimer_counter_t whichCounter, - uint32_t *captureRegister, - uint32_t event) -{ - status_t status; - - if ((kSCTIMER_Counter_L == whichCounter) || (kSCTIMER_Counter_U == whichCounter)) - { - if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - /* Set the bit to enable event */ - base->CAPCTRL_ACCESS16BIT[s_currentMatch].CAPCTRLL |= SCT_CAPCTRLL_CAPCTRLL(1UL << event); - - /* Set this resource to be a capture rather than match */ - base->REGMODE_ACCESS16BIT.REGMODEL |= SCT_REGMODEL_REGMODEL(1UL << s_currentMatch); - - /* Return the match register number */ - *captureRegister = s_currentMatch; - - /* Increase the match register number */ - s_currentMatch++; - - status = kStatus_Success; - } - else - { - /* Return an error if we have hit the limit in terms of number of capture/match registers used */ - status = kStatus_Fail; - } - } - else - { - if (s_currentMatchhigh < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - /* Set bit to enable event */ - base->CAPCTRL_ACCESS16BIT[s_currentMatchhigh].CAPCTRLH |= SCT_CAPCTRLL_CAPCTRLL(1UL << event); - - /* Set this resource to be a capture rather than match */ - base->REGMODE_ACCESS16BIT.REGMODEH |= SCT_REGMODEL_REGMODEL(1UL << s_currentMatchhigh); - - /* Return the match register number */ - *captureRegister = s_currentMatchhigh; - - /* Increase the match register number */ - s_currentMatchhigh++; - - status = kStatus_Success; - } - else - { - /* Return an error if we have hit the limit in terms of number of capture/match registers used */ - status = kStatus_Fail; - } - } - - return status; -} - -/*! - * brief Receive noticification when the event trigger an interrupt. - * - * If the interrupt for the event is enabled by the user, then a callback can be registered - * which will be invoked when the event is triggered - * - * param base SCTimer peripheral base address - * param event Event number that will trigger the interrupt - * param callback Function to invoke when the event is triggered - */ - -void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event) -{ - s_eventCallback[event] = callback; -} - -/*! - * brief SCTimer interrupt handler. - * - * param base SCTimer peripheral base address. - */ -void SCTIMER_EventHandleIRQ(SCT_Type *base) -{ - uint32_t eventFlag = SCT0->EVFLAG; - /* Only clear the flags whose interrupt field is enabled */ - uint32_t clearFlag = (eventFlag & SCT0->EVEN); - uint32_t mask = eventFlag; - uint32_t i; - - /* Invoke the callback for certain events */ - for (i = 0; i < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) - { - if ((mask & 0x1U) != 0U) - { - if (s_eventCallback[i] != NULL) - { - s_eventCallback[i](); - } - } - mask >>= 1UL; - - if (0U == mask) - { - /* All events have been handled. */ - break; - } - } - - /* Clear event interrupt flag */ - SCT0->EVFLAG = clearFlag; -} - -void SCT0_DriverIRQHandler(void); -void SCT0_DriverIRQHandler(void) -{ - s_sctimerIsr(SCT0); - SDK_ISR_EXIT_BARRIER; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sctimer.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sctimer.h deleted file mode 100644 index 01ccdd90772..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sctimer.h +++ /dev/null @@ -1,1258 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SCTIMER_H_ -#define _FSL_SCTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup sctimer - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) /*!< Version */ -/*@}*/ - -#ifndef SCT_EV_STATE_STATEMSKn -#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(x) & (1UL << FSL_FEATURE_SCT_NUMBER_OF_STATES) - 1UL)) -#endif - -/*! @brief SCTimer PWM operation modes */ -typedef enum _sctimer_pwm_mode -{ - kSCTIMER_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */ - kSCTIMER_CenterAlignedPwm /*!< Center-aligned PWM */ -} sctimer_pwm_mode_t; - -/*! @brief SCTimer counters type. */ -typedef enum _sctimer_counter -{ - kSCTIMER_Counter_L = (1U << 0), /*!< 16-bit Low counter. */ - kSCTIMER_Counter_H = (1U << 1), /*!< 16-bit High counter. */ - kSCTIMER_Counter_U = (1U << 2), /*!< 32-bit Unified counter. */ -} sctimer_counter_t; - -/*! @brief List of SCTimer input pins */ -typedef enum _sctimer_input -{ - kSCTIMER_Input_0 = 0U, /*!< SCTIMER input 0 */ - kSCTIMER_Input_1, /*!< SCTIMER input 1 */ - kSCTIMER_Input_2, /*!< SCTIMER input 2 */ - kSCTIMER_Input_3, /*!< SCTIMER input 3 */ - kSCTIMER_Input_4, /*!< SCTIMER input 4 */ - kSCTIMER_Input_5, /*!< SCTIMER input 5 */ - kSCTIMER_Input_6, /*!< SCTIMER input 6 */ - kSCTIMER_Input_7 /*!< SCTIMER input 7 */ -} sctimer_input_t; - -/*! @brief List of SCTimer output pins */ -typedef enum _sctimer_out -{ - kSCTIMER_Out_0 = 0U, /*!< SCTIMER output 0*/ - kSCTIMER_Out_1, /*!< SCTIMER output 1 */ - kSCTIMER_Out_2, /*!< SCTIMER output 2 */ - kSCTIMER_Out_3, /*!< SCTIMER output 3 */ - kSCTIMER_Out_4, /*!< SCTIMER output 4 */ - kSCTIMER_Out_5, /*!< SCTIMER output 5 */ - kSCTIMER_Out_6, /*!< SCTIMER output 6 */ - kSCTIMER_Out_7, /*!< SCTIMER output 7 */ - kSCTIMER_Out_8, /*!< SCTIMER output 8 */ - kSCTIMER_Out_9 /*!< SCTIMER output 9 */ -} sctimer_out_t; - -/*! @brief SCTimer PWM output pulse mode: high-true, low-true or no output */ -typedef enum _sctimer_pwm_level_select -{ - kSCTIMER_LowTrue = 0U, /*!< Low true pulses */ - kSCTIMER_HighTrue /*!< High true pulses */ -} sctimer_pwm_level_select_t; - -/*! @brief Options to configure a SCTimer PWM signal */ -typedef struct _sctimer_pwm_signal_param -{ - sctimer_out_t output; /*!< The output pin to use to generate the PWM signal */ - sctimer_pwm_level_select_t level; /*!< PWM output active level select. */ - uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 - 0 = always inactive signal (0% duty cycle) - 100 = always active signal (100% duty cycle).*/ -} sctimer_pwm_signal_param_t; - -/*! @brief SCTimer clock mode options */ -typedef enum _sctimer_clock_mode -{ - kSCTIMER_System_ClockMode = 0U, /*!< System Clock Mode */ - kSCTIMER_Sampled_ClockMode, /*!< Sampled System Clock Mode */ - kSCTIMER_Input_ClockMode, /*!< SCT Input Clock Mode */ - kSCTIMER_Asynchronous_ClockMode /*!< Asynchronous Mode */ -} sctimer_clock_mode_t; - -/*! @brief SCTimer clock select options */ -typedef enum _sctimer_clock_select -{ - kSCTIMER_Clock_On_Rise_Input_0 = 0U, /*!< Rising edges on input 0 */ - kSCTIMER_Clock_On_Fall_Input_0, /*!< Falling edges on input 0 */ - kSCTIMER_Clock_On_Rise_Input_1, /*!< Rising edges on input 1 */ - kSCTIMER_Clock_On_Fall_Input_1, /*!< Falling edges on input 1 */ - kSCTIMER_Clock_On_Rise_Input_2, /*!< Rising edges on input 2 */ - kSCTIMER_Clock_On_Fall_Input_2, /*!< Falling edges on input 2 */ - kSCTIMER_Clock_On_Rise_Input_3, /*!< Rising edges on input 3 */ - kSCTIMER_Clock_On_Fall_Input_3, /*!< Falling edges on input 3 */ - kSCTIMER_Clock_On_Rise_Input_4, /*!< Rising edges on input 4 */ - kSCTIMER_Clock_On_Fall_Input_4, /*!< Falling edges on input 4 */ - kSCTIMER_Clock_On_Rise_Input_5, /*!< Rising edges on input 5 */ - kSCTIMER_Clock_On_Fall_Input_5, /*!< Falling edges on input 5 */ - kSCTIMER_Clock_On_Rise_Input_6, /*!< Rising edges on input 6 */ - kSCTIMER_Clock_On_Fall_Input_6, /*!< Falling edges on input 6 */ - kSCTIMER_Clock_On_Rise_Input_7, /*!< Rising edges on input 7 */ - kSCTIMER_Clock_On_Fall_Input_7 /*!< Falling edges on input 7 */ -} sctimer_clock_select_t; - -/*! - * @brief SCTimer output conflict resolution options. - * - * Specifies what action should be taken if multiple events dictate that a given output should be - * both set and cleared at the same time - */ -typedef enum _sctimer_conflict_resolution -{ - kSCTIMER_ResolveNone = 0U, /*!< No change */ - kSCTIMER_ResolveSet, /*!< Set output */ - kSCTIMER_ResolveClear, /*!< Clear output */ - kSCTIMER_ResolveToggle /*!< Toggle output */ -} sctimer_conflict_resolution_t; - -/*! @brief List of SCTimer event generation active direction when the counters are operating in BIDIR mode. */ -typedef enum _sctimer_event_active_direction -{ - kSCTIMER_ActiveIndependent = 0U, /*!< This event is triggered regardless of the count direction. */ - kSCTIMER_ActiveInCountUp, /*!< This event is triggered only during up-counting when BIDIR = 1. */ - kSCTIMER_ActiveInCountDown /*!< This event is triggered only during down-counting when BIDIR = 1. */ -} sctimer_event_active_direction_t; - -/*! @brief List of SCTimer event types */ -typedef enum _sctimer_event -{ - kSCTIMER_InputLowOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_MatchEventOnly = - (1 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_InputLowEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_InputLowAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT) -} sctimer_event_t; - -/*! @brief SCTimer callback typedef. */ -typedef void (*sctimer_event_callback_t)(void); - -/*! @brief List of SCTimer interrupts */ -typedef enum _sctimer_interrupt_enable -{ - kSCTIMER_Event0InterruptEnable = (1U << 0), /*!< Event 0 interrupt */ - kSCTIMER_Event1InterruptEnable = (1U << 1), /*!< Event 1 interrupt */ - kSCTIMER_Event2InterruptEnable = (1U << 2), /*!< Event 2 interrupt */ - kSCTIMER_Event3InterruptEnable = (1U << 3), /*!< Event 3 interrupt */ - kSCTIMER_Event4InterruptEnable = (1U << 4), /*!< Event 4 interrupt */ - kSCTIMER_Event5InterruptEnable = (1U << 5), /*!< Event 5 interrupt */ - kSCTIMER_Event6InterruptEnable = (1U << 6), /*!< Event 6 interrupt */ - kSCTIMER_Event7InterruptEnable = (1U << 7), /*!< Event 7 interrupt */ - kSCTIMER_Event8InterruptEnable = (1U << 8), /*!< Event 8 interrupt */ - kSCTIMER_Event9InterruptEnable = (1U << 9), /*!< Event 9 interrupt */ - kSCTIMER_Event10InterruptEnable = (1U << 10), /*!< Event 10 interrupt */ - kSCTIMER_Event11InterruptEnable = (1U << 11), /*!< Event 11 interrupt */ - kSCTIMER_Event12InterruptEnable = (1U << 12), /*!< Event 12 interrupt */ -} sctimer_interrupt_enable_t; - -/*! @brief List of SCTimer flags */ -typedef enum _sctimer_status_flags -{ - kSCTIMER_Event0Flag = (1U << 0), /*!< Event 0 Flag */ - kSCTIMER_Event1Flag = (1U << 1), /*!< Event 1 Flag */ - kSCTIMER_Event2Flag = (1U << 2), /*!< Event 2 Flag */ - kSCTIMER_Event3Flag = (1U << 3), /*!< Event 3 Flag */ - kSCTIMER_Event4Flag = (1U << 4), /*!< Event 4 Flag */ - kSCTIMER_Event5Flag = (1U << 5), /*!< Event 5 Flag */ - kSCTIMER_Event6Flag = (1U << 6), /*!< Event 6 Flag */ - kSCTIMER_Event7Flag = (1U << 7), /*!< Event 7 Flag */ - kSCTIMER_Event8Flag = (1U << 8), /*!< Event 8 Flag */ - kSCTIMER_Event9Flag = (1U << 9), /*!< Event 9 Flag */ - kSCTIMER_Event10Flag = (1U << 10), /*!< Event 10 Flag */ - kSCTIMER_Event11Flag = (1U << 11), /*!< Event 11 Flag */ - kSCTIMER_Event12Flag = (1U << 12), /*!< Event 12 Flag */ - kSCTIMER_BusErrorLFlag = - (1U << SCT_CONFLAG_BUSERRL_SHIFT), /*!< Bus error due to write when L counter was not halted */ - kSCTIMER_BusErrorHFlag = - (int)(1U << SCT_CONFLAG_BUSERRH_SHIFT) /*!< Bus error due to write when H counter was not halted */ -} sctimer_status_flags_t; - -/*! - * @brief SCTimer configuration structure - * - * This structure holds the configuration settings for the SCTimer peripheral. To initialize this - * structure to reasonable defaults, call the SCTMR_GetDefaultConfig() function and pass a - * pointer to the configuration structure instance. - * - * The configuration structure can be made constant so as to reside in flash. - */ -typedef struct _sctimer_config -{ - bool enableCounterUnify; /*!< true: SCT operates as a unified 32-bit counter; - false: SCT operates as two 16-bit counters. - User can use the 16-bit low counter and the 16-bit high counters at the - same time; for Hardware limit, user can not use unified 32-bit counter - and any 16-bit low/high counter at the same time. */ - sctimer_clock_mode_t clockMode; /*!< SCT clock mode value */ - sctimer_clock_select_t clockSelect; /*!< SCT clock select value */ - bool enableBidirection_l; /*!< true: Up-down count mode for the L or unified counter - false: Up count mode only for the L or unified counter */ - bool enableBidirection_h; /*!< true: Up-down count mode for the H or unified counter - false: Up count mode only for the H or unified counter. - This field is used only if the enableCounterUnify is set - to false */ - uint8_t prescale_l; /*!< Prescale value to produce the L or unified counter clock */ - uint8_t prescale_h; /*!< Prescale value to produce the H counter clock. - This field is used only if the enableCounterUnify is set - to false */ - uint8_t outInitState; /*!< Defines the initial output value */ - uint8_t inputsync; /*!< SCT INSYNC value, INSYNC field in the CONFIG register, from bit9 to bit 16. - it is used to define synchronization for input N: - bit 9 = input 0 - bit 10 = input 1 - bit 11 = input 2 - bit 12 = input 3 - All other bits are reserved (bit13 ~bit 16). - How User to set the the value for the member inputsync. - IE: delay for input0, and input 1, bypasses for input 2 and input 3 - MACRO definition in user level. - \#define INPUTSYNC0 (0U) - \#define INPUTSYNC1 (1U) - \#define INPUTSYNC2 (2U) - \#define INPUTSYNC3 (3U) - User Code. - sctimerInfo.inputsync = (1 << INPUTSYNC2) | (1 << INPUTSYNC3); */ -} sctimer_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the SCTimer clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the SCTimer driver. - * - * @param base SCTimer peripheral base address - * @param config Pointer to the user configuration structure. - * - * @return kStatus_Success indicates success; Else indicates failure. - */ -status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config); - -/*! - * @brief Gates the SCTimer clock. - * - * @param base SCTimer peripheral base address - */ -void SCTIMER_Deinit(SCT_Type *base); - -/*! - * @brief Fills in the SCTimer configuration structure with the default settings. - * - * The default values are: - * @code - * config->enableCounterUnify = true; - * config->clockMode = kSCTIMER_System_ClockMode; - * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - * config->enableBidirection_l = false; - * config->enableBidirection_h = false; - * config->prescale_l = 0U; - * config->prescale_h = 0U; - * config->outInitState = 0U; - * config->inputsync = 0xFU; - * @endcode - * @param config Pointer to the user configuration structure. - */ -void SCTIMER_GetDefaultConfig(sctimer_config_t *config); - -/*! @}*/ - -/*! - * @name PWM setup operations - * @{ - */ - -/*! - * @brief Configures the PWM signal parameters. - * - * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This - * function will create 2 events; one of the events will trigger on match with the pulse value - * and the other will trigger when the counter matches the PWM period. The PWM period event is - * also used as a limit event to reset the counter or change direction. Both events are enabled - * for the same state. The state number can be retrieved by calling the function - * SCTIMER_GetCurrentStateNumber(). - * The counter is set to operate as one 32-bit counter (unify bit is set to 1). - * The counter operates in bi-directional mode when generating a center-aligned PWM. - * - * @note When setting PWM output from multiple output pins, they all should use the same PWM mode - * i.e all PWM's should be either edge-aligned or center-aligned. - * When using this API, the PWM signal frequency of all the initialized channels must be the same. - * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the - * API's pwmFreq_Hz. - * - * @param base SCTimer peripheral base address - * @param pwmParams PWM parameters to configure the output - * @param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz SCTimer counter clock in Hz - * @param event Pointer to a variable where the PWM period event number is stored - * - * @return kStatus_Success on success - * kStatus_Fail If we have hit the limit in terms of number of events created or if - * an incorrect PWM dutycylce is passed in. - */ -status_t SCTIMER_SetupPwm(SCT_Type *base, - const sctimer_pwm_signal_param_t *pwmParams, - sctimer_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - uint32_t *event); - -/*! - * @brief Updates the duty cycle of an active PWM signal. - * - * Before calling this function, the counter is set to operate as one 32-bit counter (unify bit is set to 1). - * - * @param base SCTimer peripheral base address - * @param output The output to configure - * @param dutyCyclePercent New PWM pulse width; the value should be between 1 to 100 - * @param event Event number associated with this PWM signal. This was returned to the user by the - * function SCTIMER_SetupPwm(). - */ -void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event); - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline void SCTIMER_EnableInterrupts(SCT_Type *base, uint32_t mask) -{ - base->EVEN |= mask; -} - -/*! - * @brief Disables the selected SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline void SCTIMER_DisableInterrupts(SCT_Type *base, uint32_t mask) -{ - base->EVEN &= ~mask; -} - -/*! - * @brief Gets the enabled SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline uint32_t SCTIMER_GetEnabledInterrupts(SCT_Type *base) -{ - return (base->EVEN & 0xFFFFU); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the SCTimer status flags. - * - * @param base SCTimer peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::sctimer_status_flags_t - */ -static inline uint32_t SCTIMER_GetStatusFlags(SCT_Type *base) -{ - uint32_t statusFlags = 0; - - /* Add the recorded events */ - statusFlags = (base->EVFLAG & 0xFFFFU); - - /* Add bus error flags */ - statusFlags |= (base->CONFLAG & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); - - return statusFlags; -} - -/*! - * @brief Clears the SCTimer status flags. - * - * @param base SCTimer peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::sctimer_status_flags_t - */ -static inline void SCTIMER_ClearStatusFlags(SCT_Type *base, uint32_t mask) -{ - /* Write to the flag registers */ - base->EVFLAG = (mask & 0xFFFFU); - base->CONFLAG = (mask & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); -} - -/*! @}*/ - -/*! - * @name Counter Start and Stop - * @{ - */ - -/*! - * @brief Starts the SCTimer counter. - * - * @note In 16-bit mode, we can enable both Counter_L and Counter_H, In 32-bit mode, we only can select Counter_U. - * - * @param base SCTimer peripheral base address - * @param countertoStart The SCTimer counters to enable. This is a logical OR of members of the - * enumeration ::sctimer_counter_t. - */ -static inline void SCTIMER_StartTimer(SCT_Type *base, uint32_t countertoStart) -{ - switch (countertoStart) - { - case (uint32_t)kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_L bit when user wants to start the Low counter */ - base->CTRL_ACCESS16BIT.CTRLL &= ~((uint16_t)SCT_CTRLL_HALT_L_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_H bit when user wants to start the High counter */ - base->CTRL_ACCESS16BIT.CTRLH &= ~((uint16_t)SCT_CTRLH_HALT_H_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_L | (uint32_t)kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_L/HALT_H bit when user wants to H counter and L counter at same time */ - base->CTRL &= ~(SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_L bit when the counter is operating in 32-bit mode (unify counter). */ - base->CTRL &= ~(SCT_CTRL_HALT_L_MASK); - break; - - default: - /* Counter_L/Counter_H can't work together with Counter_U. */ - assert(false); - break; - } -} - -/*! - * @brief Halts the SCTimer counter. - * - * @param base SCTimer peripheral base address - * @param countertoStop The SCTimer counters to stop. This is a logical OR of members of the - * enumeration ::sctimer_counter_t. - */ -static inline void SCTIMER_StopTimer(SCT_Type *base, uint32_t countertoStop) -{ - switch (countertoStop) - { - case (uint32_t)kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Set HALT_L bit when user wants to start the Low counter */ - base->CTRL_ACCESS16BIT.CTRLL |= (SCT_CTRLL_HALT_L_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Set HALT_H bit when user wants to start the High counter */ - base->CTRL_ACCESS16BIT.CTRLH |= (SCT_CTRLH_HALT_H_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_L | (uint32_t)kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_L/HALT_H bit when user wants to H counter and L counter at same time */ - base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Set HALT_L bit when the counter is operating in 32-bit mode (unify counter). */ - base->CTRL |= (SCT_CTRL_HALT_L_MASK); - break; - - default: - /* Counter_L/Counter_H can't work together with Counter_U. */ - assert(false); - break; - } -} - -/*! @}*/ - -/*! - * @name Functions to create a new event and manage the state logic - * @{ - */ - -/*! - * @brief Create an event that is triggered on a match or IO and schedule in current state. - * - * This function will configure an event using the options provided by the user. If the event type uses - * the counter match, then the function will set the user provided match value into a match register - * and put this match register number into the event control register. - * The event is enabled for the current state and the event number is increased by one at the end. - * The function returns the event number; this event number can be used to configure actions to be - * done when this event is triggered. - * - * @param base SCTimer peripheral base address - * @param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t - * @param matchValue The match value that will be programmed to a match register - * @param whichIO The input or output that will be involved in event triggering. This field - * is ignored if the event type is "match only" - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Pointer to a variable where the new event number is stored - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of events created or - if we have reached the limit in terms of number of match registers - */ -status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, - sctimer_event_t howToMonitor, - uint32_t matchValue, - uint32_t whichIO, - sctimer_counter_t whichCounter, - uint32_t *event); - -/*! - * @brief Enable an event in the current state. - * - * This function will allow the event passed in to trigger in the current state. The event must - * be created earlier by either calling the function SCTIMER_SetupPwm() or function - * SCTIMER_CreateAndScheduleEvent() . - * - * @param base SCTimer peripheral base address - * @param event Event number to enable in the current state - * - */ -void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event); - -/*! - * @brief Increase the state by 1 - * - * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new - * state. - * - * @param base SCTimer peripheral base address - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of states used - - */ -status_t SCTIMER_IncreaseState(SCT_Type *base); - -/*! - * @brief Provides the current state - * - * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). - * - * @param base SCTimer peripheral base address - * - * @return The current state - */ -uint32_t SCTIMER_GetCurrentState(SCT_Type *base); - -/*! - * @brief Set the counter current state. - * - * The function is to set the state variable bit field of STATE register. Writing to the STATE_L, STATE_H, or unified - * register is only allowed when the corresponding counter is halted (HALT bits are set to 1 in the CTRL register). - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param state The counter current state number (only support range from 0~31). - */ -static inline void SCTIMER_SetCounterState(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t state) -{ - /* SCT only support 0 ~ FSL_FEATURE_SCT_NUMBER_OF_STATES state value. */ - assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); - - SCTIMER_StopTimer(base, (uint32_t)whichCounter); - - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_L bits when user wants to setup the Low counter */ - base->STATE_ACCESS16BIT.STATEL = SCT_STATEL_STATEL(state); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_H bits when user wants to start the High counter */ - base->STATE_ACCESS16BIT.STATEH = SCT_STATEH_STATEH(state); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_L bits when counter is operating in 32-bit mode (unify counter). */ - base->STATE = SCT_STATE_STATE_L(state); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } - - SCTIMER_StartTimer(base, (uint32_t)whichCounter); -} - -/*! - * @brief Get the counter current state value. - * - * The function is to get the state variable bit field of STATE register. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @return The the counter current state value. - */ -static inline uint16_t SCTIMER_GetCounterState(SCT_Type *base, sctimer_counter_t whichCounter) -{ - uint16_t regs; - - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_L bits when user wants to setup the Low counter */ - regs = base->STATE_ACCESS16BIT.STATEL & SCT_STATEL_STATEL_MASK; - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_H bits when user wants to start the High counter */ - regs = base->STATE_ACCESS16BIT.STATEH & SCT_STATEH_STATEH_MASK; - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_L bits when counter is operating in 32-bit mode (unify counter). */ - regs = (uint16_t)(base->STATE & SCT_STATE_STATE_L_MASK); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } - - return regs; -} - -/*! @}*/ - -/*! - * @name Actions to take in response to an event - * @{ - */ - -/*! - * @brief Setup capture of the counter value on trigger of a selected event - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param captureRegister Pointer to a variable where the capture register number will be returned. User - * can read the captured value from this register when the specified event is triggered. - * @param event Event number that will trigger the capture - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of match/capture registers available - */ -status_t SCTIMER_SetupCaptureAction(SCT_Type *base, - sctimer_counter_t whichCounter, - uint32_t *captureRegister, - uint32_t event); - -/*! - * @brief Receive noticification when the event trigger an interrupt. - * - * If the interrupt for the event is enabled by the user, then a callback can be registered - * which will be invoked when the event is triggered - * - * @param base SCTimer peripheral base address - * @param event Event number that will trigger the interrupt - * @param callback Function to invoke when the event is triggered - */ - -void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event); - -/*! - * @brief Change the load method of transition to the specified state. - * - * Change the load method of transition, it will be triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param event Event number that will change the method to trigger the state transition - * @param fgLoad The method to load highest-numbered event occurring for that state to the STATE register. - * - true: Load the STATEV value to STATE when the event occurs to be the next state. - * - false: Add the STATEV value to STATE when the event occurs to be the next state. - */ -static inline void SCTIMER_SetupStateLdMethodAction(SCT_Type *base, uint32_t event, bool fgLoad) -{ - uint32_t reg = base->EV[event].CTRL; - - if (fgLoad) - { - /* Load the STATEV value to STATE when the event occurs to be the next state */ - reg |= SCT_EV_CTRL_STATELD_MASK; - } - else - { - /* Add the STATEV value to STATE when the event occurs to be the next state */ - reg &= ~SCT_EV_CTRL_STATELD_MASK; - } - - base->EV[event].CTRL = reg; -} - -/*! - * @brief Transition to the specified state with Load method. - * - * This transition will be triggered by the event number that is passed in by the user, the method decide how to load - * the highest-numbered event occurring for that state to the STATE register. - * - * @param base SCTimer peripheral base address - * @param nextState The next state SCTimer will transition to - * @param event Event number that will trigger the state transition - * @param fgLoad The method to load the highest-numbered event occurring for that state to the STATE register. - * - true: Load the STATEV value to STATE when the event occurs to be the next state. - * - false: Add the STATEV value to STATE when the event occurs to be the next state. - */ -static inline void SCTIMER_SetupNextStateActionwithLdMethod(SCT_Type *base, - uint32_t nextState, - uint32_t event, - bool fgLoad) -{ - uint32_t reg = base->EV[event].CTRL; - - reg &= ~(SCT_EV_CTRL_STATEV_MASK | SCT_EV_CTRL_STATELD_MASK); - - reg |= SCT_EV_CTRL_STATEV(nextState); - - if (fgLoad) - { - /* Load the STATEV value when the event occurs to be the next state */ - reg |= SCT_EV_CTRL_STATELD_MASK; - } - - base->EV[event].CTRL = reg; -} - -/*! - * @brief Transition to the specified state. - * @deprecated Do not use this function. It has been superceded by @ref SCTIMER_SetupNextStateActionwithLdMethod - * - * This transition will be triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param nextState The next state SCTimer will transition to - * @param event Event number that will trigger the state transition - */ -static inline void SCTIMER_SetupNextStateAction(SCT_Type *base, uint32_t nextState, uint32_t event) -{ - uint32_t reg = base->EV[event].CTRL; - - reg &= ~(SCT_EV_CTRL_STATEV_MASK); - /* Load the STATEV value when the event occurs to be the next state */ - reg |= SCT_EV_CTRL_STATEV(nextState) | SCT_EV_CTRL_STATELD_MASK; - - base->EV[event].CTRL = reg; -} - -/*! - * @brief Setup event active direction when the counters are operating in BIDIR mode. - * - * @param base SCTimer peripheral base address - * @param activeDirection Event generation active direction, see @ref sctimer_event_active_direction_t. - * @param event Event number that need setup the active direction. - */ -static inline void SCTIMER_SetupEventActiveDirection(SCT_Type *base, - sctimer_event_active_direction_t activeDirection, - uint32_t event) -{ - uint32_t reg = base->EV[event].CTRL; - - reg &= ~(SCT_EV_CTRL_DIRECTION_MASK); - - reg |= SCT_EV_CTRL_DIRECTION(activeDirection); - - base->EV[event].CTRL = reg; -} - -/*! - * @brief Set the Output. - * - * This output will be set when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to set - * @param event Event number that will trigger the output change - */ -static inline void SCTIMER_SetupOutputSetAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - base->OUT[whichIO].SET |= (1UL << event); -} - -/*! - * @brief Clear the Output. - * - * This output will be cleared when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to clear - * @param event Event number that will trigger the output change - */ -static inline void SCTIMER_SetupOutputClearAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - base->OUT[whichIO].CLR |= (1UL << event); -} - -/*! - * @brief Toggle the output level. - * - * This change in the output level is triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to toggle - * @param event Event number that will trigger the output change - */ -void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event); - -/*! - * @brief Limit the running counter. - * - * The counter is limited when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Event number that will trigger the counter to be limited - */ -static inline void SCTIMER_SetupCounterLimitAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->LIMIT_ACCESS16BIT.LIMITL |= SCT_LIMITL_LIMITL(1UL << event); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->LIMIT_ACCESS16BIT.LIMITH |= SCT_LIMITH_LIMITH(1UL << event); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->LIMIT |= SCT_LIMIT_LIMMSK_L(1UL << event); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } -} - -/*! - * @brief Stop the running counter. - * - * The counter is stopped when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Event number that will trigger the counter to be stopped - */ -static inline void SCTIMER_SetupCounterStopAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->STOP_ACCESS16BIT.STOPL |= SCT_STOPL_STOPL(1UL << event); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->STOP_ACCESS16BIT.STOPH |= SCT_STOPH_STOPH(1UL << event); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->STOP |= SCT_STOP_STOPMSK_L(1UL << event); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } -} - -/*! - * @brief Re-start the stopped counter. - * - * The counter will re-start when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Event number that will trigger the counter to re-start - */ -static inline void SCTIMER_SetupCounterStartAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->START_ACCESS16BIT.STARTL |= SCT_STARTL_STARTL(1UL << event); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->START_ACCESS16BIT.STARTH |= SCT_STARTH_STARTH(1UL << event); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->START |= SCT_START_STARTMSK_L(1UL << event); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } -} - -/*! - * @brief Halt the running counter. - * - * The counter is disabled (halted) when the event number that is passed in by the user is - * triggered. When the counter is halted, all further events are disabled. The HALT condition - * can only be removed by calling the SCTIMER_StartTimer() function. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Event number that will trigger the counter to be halted - */ -static inline void SCTIMER_SetupCounterHaltAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->HALT_ACCESS16BIT.HALTL |= SCT_HALTL_HALTL(1UL << event); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->HALT_ACCESS16BIT.HALTH |= SCT_HALTH_HALTH(1UL << event); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->HALT |= SCT_HALT_HALTMSK_L(1UL << event); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } -} - -#if !(defined(FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) && FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) -/*! - * @brief Generate a DMA request. - * - * DMA request will be triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param dmaNumber The DMA request to generate - * @param event Event number that will trigger the DMA request - */ -static inline void SCTIMER_SetupDmaTriggerAction(SCT_Type *base, uint32_t dmaNumber, uint32_t event) -{ - if (dmaNumber == 0U) - { - base->DMAREQ0 |= (1UL << event); - } - else - { - base->DMAREQ1 |= (1UL << event); - } -} -#endif /* FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST */ - -/*! - * @brief Set the value of counter. - * - * The function is to set the value of Count register, Writing to the COUNT_L, COUNT_H, or unified register - * is only allowed when the corresponding counter is halted (HALT bits are set to 1 in the CTRL register). - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param value the counter value update to the COUNT register. - */ -static inline void SCTIMER_SetCOUNTValue(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t value) -{ - SCTIMER_StopTimer(base, (uint32_t)whichCounter); - - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(value <= 0xFFFFU); - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->COUNT_ACCESS16BIT.COUNTL = (uint16_t)value; - break; - - case kSCTIMER_Counter_H: - assert(value <= 0xFFFFU); - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->COUNT_ACCESS16BIT.COUNTH = (uint16_t)value; - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->COUNT &= ~SCT_COUNT_CTR_L_MASK; - base->COUNT |= SCT_COUNT_CTR_L(value); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } - - SCTIMER_StartTimer(base, (uint32_t)whichCounter); -} - -/*! - * @brief Get the value of counter. - * - * The function is to read the value of Count register, software can read the counter registers at any time.. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @return The value of counter selected. - */ -static inline uint32_t SCTIMER_GetCOUNTValue(SCT_Type *base, sctimer_counter_t whichCounter) -{ - uint32_t value; - - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - value = base->COUNT_ACCESS16BIT.COUNTL; - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - value = base->COUNT_ACCESS16BIT.COUNTH; - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - value = base->COUNT; - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } - - return value; -} - -/*! - * @brief Set the state mask bit field of EV_STATE register. - * - * @param base SCTimer peripheral base address - * @param event The EV_STATE register be set. - * @param state The state value in which the event is enabled to occur. - */ -static inline void SCTIMER_SetEventInState(SCT_Type *base, uint32_t event, uint32_t state) -{ - assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); - assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); - - base->EV[event].STATE |= SCT_EV_STATE_STATEMSKn((uint32_t)1U << state); -} - -/*! - * @brief Clear the state mask bit field of EV_STATE register. - * - * @param base SCTimer peripheral base address - * @param event The EV_STATE register be clear. - * @param state The state value in which the event is disabled to occur. - */ -static inline void SCTIMER_ClearEventInState(SCT_Type *base, uint32_t event, uint32_t state) -{ - assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); - assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); - - base->EV[event].STATE &= ~SCT_EV_STATE_STATEMSKn((uint32_t)1U << state); -} - -/*! - * @brief Get the state mask bit field of EV_STATE register. - * - * @note This function is to check whether the event is enabled in a specific state. - * - * @param base SCTimer peripheral base address - * @param event The EV_STATE register be read. - * @param state The state value. - * - * @return The the state mask bit field of EV_STATE register. - * - true: The event is enable in state. - * - false: The event is disable in state. - */ -static inline bool SCTIMER_GetEventInState(SCT_Type *base, uint32_t event, uint32_t state) -{ - assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); - assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); - - return (0U != (base->EV[event].STATE & SCT_EV_STATE_STATEMSKn((uint32_t)1U << state))); -} - -/*! - * @brief SCTimer interrupt handler. - * - * @param base SCTimer peripheral base address. - */ -void SCTIMER_EventHandleIRQ(SCT_Type *base); - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_SCTIMER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi.c deleted file mode 100644 index 456361e6204..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi.c +++ /dev/null @@ -1,1072 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_spi.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi" -#endif - -/* Note: FIFOCFG[SIZE] has always value 1 = 8 items depth */ - -#if defined(FSL_FEATURE_SPI_FIFOSIZE_CFG) && (FSL_FEATURE_SPI_FIFOSIZE_CFG) -#define SPI_FIFO_DEPTH(base) 4 -#else -#define SPI_FIFO_DEPTH(base) ((((base)->FIFOCFG & SPI_FIFOCFG_SIZE_MASK) >> SPI_FIFOCFG_SIZE_SHIFT) << 3) -#endif /*FSL_FEATURE_SPI_FIFOSIZE_CFG*/ - -/* Convert transfer count to transfer bytes. dataWidth is a - * range <0,15>. Range <8,15> represents 2B transfer */ -#define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U)) -#define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U)) -#if defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) && (FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) -#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK)) -#else -#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK) | (SPI_CFG_SPOL3_MASK)) -#endif /*FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE*/ - -/*! - * @brief Used for conversion from `flexcomm_irq_handler_t` to `flexcomm_spi_master_irq_handler_t` and - * `flexcomm_spi_slave_irq_handler_t`. - */ -typedef union spi_to_flexcomm -{ - flexcomm_spi_master_irq_handler_t spi_master_handler; - flexcomm_spi_slave_irq_handler_t spi_slave_handler; - flexcomm_irq_handler_t flexcomm_handler; -} spi_to_flexcomm_t; - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief internal SPI config array */ -static spi_config_t g_configs[FSL_FEATURE_SOC_SPI_COUNT] = {(spi_data_width_t)0}; - -/*! @brief Array to map SPI instance number to base address. */ -static const uint32_t s_spiBaseAddrs[FSL_FEATURE_SOC_SPI_COUNT] = SPI_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_spiIRQ[] = SPI_IRQS; - -/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ -volatile uint8_t s_dummyData[FSL_FEATURE_SOC_SPI_COUNT] = {0}; -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Get the index corresponding to the FLEXCOMM */ -/*! brief Returns instance number for SPI peripheral base address. */ -uint32_t SPI_GetInstance(SPI_Type *base) -{ - uint32_t i; - - for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_SPI_COUNT; i++) - { - if ((uint32_t)base == s_spiBaseAddrs[i]) - { - break; - } - } - - assert(i < (uint32_t)FSL_FEATURE_SOC_SPI_COUNT); - return i; -} - -/*! - * brief Set up the dummy data. - * - * param base SPI peripheral address. - * param dummyData Data to be transferred when tx buffer is NULL. - */ -void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData) -{ - uint32_t instance = SPI_GetInstance(base); - s_dummyData[instance] = dummyData; -} - -/*! - * brief Returns the configurations. - * - * param base SPI peripheral address. - * return return configurations which contain datawidth and SSEL numbers. - * return data type is a pointer of spi_config_t. - */ -void *SPI_GetConfig(SPI_Type *base) -{ - uint32_t instance; - instance = SPI_GetInstance(base); - return &g_configs[instance]; -} - -/*! - * brief Sets the SPI master configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). - * User may use the initialized structure unchanged in SPI_MasterInit(), or modify - * some fields of the structure before calling SPI_MasterInit(). After calling this API, - * the master is ready to transfer. - * Example: - code - spi_master_config_t config; - SPI_MasterGetDefaultConfig(&config); - endcode - * - * param config pointer to master config structure - */ -void SPI_MasterGetDefaultConfig(spi_master_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enableLoopback = false; - config->enableMaster = true; - config->polarity = kSPI_ClockPolarityActiveHigh; - config->phase = kSPI_ClockPhaseFirstEdge; - config->direction = kSPI_MsbFirst; - config->baudRate_Bps = 500000U; - config->dataWidth = kSPI_Data8Bits; - config->sselNum = kSPI_Ssel0; - config->txWatermark = (uint8_t)kSPI_TxFifo0; - config->rxWatermark = (uint8_t)kSPI_RxFifo1; - config->sselPol = kSPI_SpolActiveAllLow; - config->delayConfig.preDelay = 0U; - config->delayConfig.postDelay = 0U; - config->delayConfig.frameDelay = 0U; - config->delayConfig.transferDelay = 0U; -} - -/*! - * brief Initializes the SPI with master configuration. - * - * The configuration structure can be filled by user from scratch, or be set with default - * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. - * Example - code - spi_master_config_t config = { - .baudRate_Bps = 400000, - ... - }; - SPI_MasterInit(SPI0, &config); - endcode - * - * param base SPI base pointer - * param config pointer to master configuration structure - * param srcClock_Hz Source clock frequency. - */ -status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz) -{ - status_t result = kStatus_Success; - uint32_t instance; - uint32_t tmpConfig; - - /* assert params */ - assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); - if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* initialize flexcomm to SPI mode */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); - if (kStatus_Success != result) - { - return result; - } - - /* set divider */ - result = SPI_MasterSetBaud(base, config->baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - - /* get instance number */ - instance = SPI_GetInstance(base); - - /* configure SPI mode */ - tmpConfig = base->CFG; - tmpConfig &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | - SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); - /* phase */ - tmpConfig |= SPI_CFG_CPHA(config->phase); - /* polarity */ - tmpConfig |= SPI_CFG_CPOL(config->polarity); - /* direction */ - tmpConfig |= SPI_CFG_LSBF(config->direction); - /* master mode */ - tmpConfig |= SPI_CFG_MASTER(1); - /* loopback */ - tmpConfig |= SPI_CFG_LOOP(config->enableLoopback); - /* configure active level for all CS */ - tmpConfig |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); - base->CFG = tmpConfig; - - /* store configuration */ - g_configs[instance].dataWidth = config->dataWidth; - g_configs[instance].sselNum = config->sselNum; - /* enable FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; - /* trigger level - empty txFIFO, one item in rxFIFO */ - tmpConfig = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); - tmpConfig |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable generating interrupts for FIFOTRIG levels */ - tmpConfig |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; - /* set FIFOTRIG */ - base->FIFOTRIG = tmpConfig; - - /* Set the delay configuration. */ - SPI_SetTransferDelay(base, &config->delayConfig); - /* Set the dummy data. */ - SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); - - SPI_Enable(base, config->enableMaster); - return kStatus_Success; -} - -/*! - * brief Sets the SPI slave configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). - * Modify some fields of the structure before calling SPI_SlaveInit(). - * Example: - code - spi_slave_config_t config; - SPI_SlaveGetDefaultConfig(&config); - endcode - * - * param config pointer to slave configuration structure - */ -void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enableSlave = true; - config->polarity = kSPI_ClockPolarityActiveHigh; - config->phase = kSPI_ClockPhaseFirstEdge; - config->direction = kSPI_MsbFirst; - config->dataWidth = kSPI_Data8Bits; - config->txWatermark = (uint8_t)kSPI_TxFifo0; - config->rxWatermark = (uint8_t)kSPI_RxFifo1; - config->sselPol = kSPI_SpolActiveAllLow; -} - -/*! - * brief Initializes the SPI with slave configuration. - * - * The configuration structure can be filled by user from scratch or be set with - * default values by SPI_SlaveGetDefaultConfig(). - * After calling this API, the slave is ready to transfer. - * Example - code - spi_slave_config_t config = { - .polarity = flexSPIClockPolarity_ActiveHigh; - .phase = flexSPIClockPhase_FirstEdge; - .direction = flexSPIMsbFirst; - ... - }; - SPI_SlaveInit(SPI0, &config); - endcode - * - * param base SPI base pointer - * param config pointer to slave configuration structure - */ -status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) -{ - status_t result = kStatus_Success; - uint32_t instance; - uint32_t tmpConfig; - - /* assert params */ - assert(!((NULL == base) || (NULL == config))); - if ((NULL == base) || (NULL == config)) - { - return kStatus_InvalidArgument; - } - /* configure flexcomm to SPI, enable clock gate */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); - if (kStatus_Success != result) - { - return result; - } - - instance = SPI_GetInstance(base); - - /* configure SPI mode */ - tmpConfig = base->CFG; - tmpConfig &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | - SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); - /* phase */ - tmpConfig |= SPI_CFG_CPHA(config->phase); - /* polarity */ - tmpConfig |= SPI_CFG_CPOL(config->polarity); - /* direction */ - tmpConfig |= SPI_CFG_LSBF(config->direction); - /* configure active level for all CS */ - tmpConfig |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); - base->CFG = tmpConfig; - - /* store configuration */ - g_configs[instance].dataWidth = config->dataWidth; - /* empty and enable FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; - /* trigger level - empty txFIFO, one item in rxFIFO */ - tmpConfig = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); - tmpConfig |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable generating interrupts for FIFOTRIG levels */ - tmpConfig |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; - /* set FIFOTRIG */ - base->FIFOTRIG = tmpConfig; - - SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); - - SPI_Enable(base, config->enableSlave); - return kStatus_Success; -} - -/*! - * brief De-initializes the SPI. - * - * Calling this API resets the SPI module, gates the SPI clock. - * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. - * - * param base SPI base pointer - */ -void SPI_Deinit(SPI_Type *base) -{ - /* Assert arguments */ - assert(NULL != base); - /* Disable interrupts, disable dma requests, disable peripheral */ - base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXERR_MASK | SPI_FIFOINTENCLR_RXERR_MASK | SPI_FIFOINTENCLR_TXLVL_MASK | - SPI_FIFOINTENCLR_RXLVL_MASK; - base->FIFOCFG &= ~(SPI_FIFOCFG_DMATX_MASK | SPI_FIFOCFG_DMARX_MASK); - base->CFG &= ~(SPI_CFG_ENABLE_MASK); -} - -/*! - * brief Enables the DMA request from SPI txFIFO. - * - * param base SPI base pointer - * param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableTxDMA(SPI_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= SPI_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= ~SPI_FIFOCFG_DMATX_MASK; - } -} - -/*! - * brief Enables the DMA request from SPI rxFIFO. - * - * param base SPI base pointer - * param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableRxDMA(SPI_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= SPI_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= ~SPI_FIFOCFG_DMARX_MASK; - } -} - -/*! - * brief Sets the baud rate for SPI transfer. This is only used in master. - * - * param base SPI base pointer - * param baudrate_Bps baud rate needed in Hz. - * param srcClock_Hz SPI source clock frequency in Hz. - */ -status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) -{ - uint32_t tmpDiv; - - /* assert params */ - assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))); - if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* calculate baudrate, round up the result */ - tmpDiv = ((srcClock_Hz * 10U) / baudrate_Bps + 5U) / 10U - 1U; - if (tmpDiv > 0xFFFFU) - { - return kStatus_SPI_BaudrateNotSupport; - } - base->DIV &= ~SPI_DIV_DIVVAL_MASK; - base->DIV |= SPI_DIV_DIVVAL(tmpDiv); - return kStatus_Success; -} - -/*! - * brief Writes a data into the SPI data register. - * - * param base SPI base pointer - * param data needs to be write. - * param configFlags transfer configuration options ref spi_xfer_option_t - */ -void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags) -{ - uint32_t control = 0U; - uint32_t instance; - - /* check params */ - assert(NULL != base); - /* get and check instance */ - instance = SPI_GetInstance(base); - - /* set data width */ - control |= (uint32_t)SPI_FIFOWR_LEN((g_configs[instance].dataWidth)); - /* set sssel */ - control |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL((uint32_t)(g_configs[instance].sselNum)))); - /* mask configFlags */ - control |= (configFlags & (uint32_t)SPI_FIFOWR_FLAGS_MASK); - /* control should not affect lower 16 bits */ - assert(0U == (control & 0xFFFFU)); - base->FIFOWR = data | control; -} - -/*! - * brief Initializes the SPI master handle. - * - * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * param base SPI peripheral base address. - * param handle SPI handle pointer. - * param callback Callback function. - * param userData User data. - */ -status_t SPI_MasterTransferCreateHandle(SPI_Type *base, - spi_master_handle_t *handle, - spi_master_callback_t callback, - void *userData) -{ - /* check 'base' */ - assert(NULL != base); - /* check 'handle' */ - assert(NULL != handle); - - uint32_t instance; - spi_to_flexcomm_t handler; - - /* get flexcomm instance by 'base' param */ - instance = SPI_GetInstance(base); - - (void)memset(handle, 0, sizeof(*handle)); - /* Initialize the handle */ - if ((base->CFG & SPI_CFG_MASTER_MASK) != 0U) - { - handler.spi_master_handler = SPI_MasterTransferHandleIRQ; - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - } - else - { - handler.spi_slave_handler = SPI_SlaveTransferHandleIRQ; - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - } - - handle->dataWidth = (uint8_t)(g_configs[instance].dataWidth); - /* in slave mode, the sselNum is not important */ - handle->sselNum = (uint8_t)(g_configs[instance].sselNum); - handle->txWatermark = (uint8_t)SPI_FIFOTRIG_TXLVL_GET(base); - handle->rxWatermark = (uint8_t)SPI_FIFOTRIG_RXLVL_GET(base); - handle->callback = callback; - handle->userData = userData; - - /* Enable SPI NVIC */ - (void)EnableIRQ(s_spiIRQ[instance]); - - return kStatus_Success; -} - -/*! - * brief Transfers a block of data using a polling method. - * - * param base SPI base pointer - * param xfer pointer to spi_xfer_config_t structure - * retval kStatus_Success Successfully start a transfer. - * retval kStatus_InvalidArgument Input argument is invalid. - * retval kStatus_SPI_Timeout The transfer timed out and was aborted. - */ -status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) -{ - uint32_t instance; - uint32_t tx_ctrl = 0U, last_ctrl = 0U; - uint32_t tmp32, rxRemainingBytes, txRemainingBytes, dataWidth; - uint32_t toReceiveCount = 0; - uint8_t *txData, *rxData; - uint32_t fifoDepth; -#if SPI_RETRY_TIMES - uint32_t waitTimes = SPI_RETRY_TIMES; -#endif - - /* check params */ - assert(!((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); - if ((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) - { - return kStatus_InvalidArgument; - } - - fifoDepth = SPI_FIFO_DEPTH(base); - txData = xfer->txData; - rxData = xfer->rxData; - txRemainingBytes = (txData != NULL) ? xfer->dataSize : 0U; - rxRemainingBytes = (rxData != NULL) ? xfer->dataSize : 0U; - - instance = SPI_GetInstance(base); - dataWidth = (uint32_t)(g_configs[instance].dataWidth); - - /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ - if ((dataWidth > (uint32_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U)) - { - return kStatus_InvalidArgument; - } - - /* clear tx/rx errors and empty FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - /* select slave to talk with */ - tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL((uint32_t)(g_configs[instance].sselNum)))); - /* set width of data - range asserted at entry */ - tx_ctrl |= SPI_FIFOWR_LEN(dataWidth); - /* delay for frames */ - tx_ctrl |= ((xfer->configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; - /* end of transfer */ - last_ctrl |= ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; - /* last index of loop */ - while ((txRemainingBytes != 0U) || (rxRemainingBytes != 0U) || (toReceiveCount != 0U)) - { -#if SPI_RETRY_TIMES - if (--waitTimes == 0U) - { - return kStatus_SPI_Timeout; - } -#endif - /* if rxFIFO is not empty */ - if ((base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) != 0U) - { - tmp32 = base->FIFORD; - /* rxBuffer is not empty */ - if (rxRemainingBytes != 0U) - { - *(rxData++) = (uint8_t)tmp32; - rxRemainingBytes--; - /* read 16 bits at once */ - if (dataWidth > 8U) - { - *(rxData++) = (uint8_t)(tmp32 >> 8); - rxRemainingBytes--; - } - } - /* decrease number of data expected to receive */ - toReceiveCount -= 1U; - } - /* transmit if txFIFO is not full and data to receive does not exceed FIFO depth */ - if (((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) != 0U) && (toReceiveCount < fifoDepth) && - ((txRemainingBytes != 0U) || (rxRemainingBytes >= SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1U)))) - { - /* txBuffer is not empty */ - if (txRemainingBytes != 0U) - { - tmp32 = *(txData++); - txRemainingBytes--; - /* write 16 bit at once */ - if (dataWidth > 8U) - { - tmp32 |= ((uint32_t)(*(txData++))) << 8U; - txRemainingBytes--; - } - if (txRemainingBytes == 0U) - { - tx_ctrl |= last_ctrl; - } - } - else - { - tmp32 = (uint32_t)s_dummyData[instance]; - tmp32 |= (uint32_t)s_dummyData[instance] << 8U; - /* last transfer */ - if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1U)) - { - tx_ctrl |= last_ctrl; - } - } - /* send data */ - tmp32 = tx_ctrl | tmp32; - base->FIFOWR = tmp32; - toReceiveCount += 1U; - } - } - /* wait if TX FIFO of previous transfer is not empty */ -#if SPI_RETRY_TIMES - waitTimes = SPI_RETRY_TIMES; - while ((0U == (base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) && (0U != --waitTimes)) -#else - while (0U == (base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) -#endif - { - } -#if SPI_RETRY_TIMES - if (waitTimes == 0U) - { - return kStatus_SPI_Timeout; - } -#endif - return kStatus_Success; -} - -/*! - * brief Performs a non-blocking SPI interrupt transfer. - * - * param base SPI peripheral base address. - * param handle pointer to spi_master_handle_t structure which stores the transfer state - * param xfer pointer to spi_xfer_config_t structure - * retval kStatus_Success Successfully start a transfer. - * retval kStatus_InvalidArgument Input argument is invalid. - * retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer) -{ - /* check params */ - assert( - !((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) - { - return kStatus_InvalidArgument; - } - - /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ - assert(!((handle->dataWidth > (uint8_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U))); - if ((handle->dataWidth > (uint8_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U)) - { - return kStatus_InvalidArgument; - } - - /* Check if SPI is busy */ - if (handle->state == (uint32_t)kStatus_SPI_Busy) - { - return kStatus_SPI_Busy; - } - - /* Set the handle information */ - handle->txData = xfer->txData; - handle->rxData = xfer->rxData; - /* set count */ - handle->txRemainingBytes = (xfer->txData != NULL) ? xfer->dataSize : 0U; - handle->rxRemainingBytes = (xfer->rxData != NULL) ? xfer->dataSize : 0U; - handle->totalByteCount = xfer->dataSize; - /* other options */ - handle->toReceiveCount = 0; - handle->configFlags = xfer->configFlags; - /* Set the SPI state to busy */ - handle->state = (uint32_t)kStatus_SPI_Busy; - /* clear FIFOs when transfer starts */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - /* enable generating txIRQ and rxIRQ, first transfer is fired by empty txFIFO */ - base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK; - return kStatus_Success; -} - -/*! - * brief Transfers a block of data using a polling method. - * - * This function will do a half-duplex transfer for SPI master, This is a blocking function, - * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, - * users can set transmit first or receive first. - * - * param base SPI base pointer - * param xfer pointer to spi_half_duplex_transfer_t structure - * return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer) -{ - assert(xfer != NULL); - - spi_transfer_t tempXfer = {0}; - status_t status; - - if (xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the pcs pin keep assert between transmit and receive. */ - if (xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); - } - else - { - tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; - } - - status = SPI_MasterTransferBlocking(base, &tempXfer); - - if (status != kStatus_Success) - { - return status; - } - - if (xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - /* SPI transfer blocking. */ - status = SPI_MasterTransferBlocking(base, &tempXfer); - - return status; -} - -/*! - * brief Performs a non-blocking SPI interrupt transfer. - * - * This function using polling way to do the first half transimission and using interrupts to - * do the second half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * param base SPI peripheral base address. - * param handle pointer to spi_master_handle_t structure which stores the transfer state - * param xfer pointer to spi_half_duplex_transfer_t structure - * return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, - spi_master_handle_t *handle, - spi_half_duplex_transfer_t *xfer) -{ - assert(xfer != NULL); - assert(handle != NULL); - spi_transfer_t tempXfer = {0}; - status_t status; - - if (xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the PCS pin keep assert between transmit and receive. */ - if (xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); - } - else - { - tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; - } - - status = SPI_MasterTransferBlocking(base, &tempXfer); - if (status != kStatus_Success) - { - return status; - } - - if (xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - status = SPI_MasterTransferNonBlocking(base, handle, &tempXfer); - - return status; -} - -/*! - * brief Gets the master transfer count. - * - * This function gets the master transfer count. - * - * param base SPI peripheral base address. - * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * param count The number of bytes transferred by using the non-blocking transaction. - * return status of status_t. - */ -status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count) -{ - assert(NULL != handle); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != (uint32_t)kStatus_SPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - *count = handle->totalByteCount - handle->rxRemainingBytes; - return kStatus_Success; -} - -/*! - * brief SPI master aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * param base SPI peripheral base address. - * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle) -{ - assert(NULL != handle); - - /* Disable interrupt requests*/ - base->FIFOINTENSET &= ~(SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK); - /* Empty FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - - handle->state = (uint32_t)kStatus_SPI_Idle; - handle->txRemainingBytes = 0U; - handle->rxRemainingBytes = 0U; -} - -static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *handle) -{ - uint32_t tx_ctrl = 0U, last_ctrl = 0U, tmp32; - bool loopContinue; - uint32_t fifoDepth; - /* Get flexcomm instance by 'base' param */ - uint32_t instance = SPI_GetInstance(base); - size_t txRemainingBytes; - size_t rxRemainingBytes; - uint8_t toReceiveCount; - - /* check params */ - assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData))); - - fifoDepth = SPI_FIFO_DEPTH(base); - /* select slave to talk with */ - tx_ctrl |= ((uint32_t)SPI_DEASSERT_ALL & (uint32_t)SPI_ASSERTNUM_SSEL(handle->sselNum)); - /* set width of data */ - tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth); - /* delay for frames */ - tx_ctrl |= ((handle->configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; - /* end of transfer */ - last_ctrl |= ((handle->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; - do - { - loopContinue = false; - - /* rxFIFO is not empty */ - if ((base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) != 0U) - { - tmp32 = base->FIFORD; - /* rxBuffer is not empty */ - if (handle->rxRemainingBytes != 0U) - { - /* low byte must go first */ - *(handle->rxData++) = (uint8_t)tmp32; - handle->rxRemainingBytes--; - /* read 16 bits at once */ - if (handle->dataWidth > (uint8_t)kSPI_Data8Bits) - { - *(handle->rxData++) = (uint8_t)(tmp32 >> 8); - handle->rxRemainingBytes--; - } - } - - /* decrease number of data expected to receive */ - handle->toReceiveCount -= 1; - loopContinue = true; - } - - /* - txFIFO is not full - * - we cannot cause rxFIFO overflow by sending more data than is the depth of FIFO - * - txBuffer is not empty or the next 'toReceiveCount' data can fit into rxBuffer - */ - txRemainingBytes = handle->txRemainingBytes; - rxRemainingBytes = handle->rxRemainingBytes; - toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; - if (((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) != 0U) && ((uint32_t)toReceiveCount < fifoDepth) && - ((txRemainingBytes != 0U) || - (rxRemainingBytes >= SPI_COUNT_TO_BYTES(handle->dataWidth, (uint32_t)toReceiveCount + 1U)))) - { - /* txBuffer is not empty */ - if ((txRemainingBytes != 0U) && (handle->txData != NULL)) - { - /* low byte must go first */ - tmp32 = *(handle->txData++); - handle->txRemainingBytes--; - txRemainingBytes = handle->txRemainingBytes; - /* write 16 bit at once */ - if (handle->dataWidth > (uint8_t)kSPI_Data8Bits) - { - tmp32 |= ((uint32_t)(*(handle->txData++))) << 8U; - handle->txRemainingBytes--; - txRemainingBytes = handle->txRemainingBytes; - } - /* last transfer */ - if (handle->txRemainingBytes == 0U) - { - tx_ctrl |= last_ctrl; - } - } - else - { - tmp32 = (uint32_t)s_dummyData[instance]; - tmp32 |= (uint32_t)s_dummyData[instance] << 8U; - /* last transfer */ - if (rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, (uint32_t)toReceiveCount + 1U)) - { - tx_ctrl |= last_ctrl; - } - } - /* send data */ - tmp32 = tx_ctrl | tmp32; - base->FIFOWR = tmp32; - /* increase number of expected data to receive */ - handle->toReceiveCount += 1; - toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; - loopContinue = true; - } - } while (loopContinue); -} - -/*! - * brief Interrupts the handler for the SPI. - * - * param base SPI peripheral base address. - * param handle pointer to spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle) -{ - assert((NULL != base) && (NULL != handle)); - size_t txRemainingBytes; - uint8_t toReceiveCount; - - /* IRQ behaviour: - * - first interrupt is triggered by empty txFIFO. The transfer function - * then tries empty rxFIFO and fill txFIFO interleaved that results to - * strategy to process as many items as possible. - * - the next IRQs can be: - * rxIRQ from nonempty rxFIFO which requires to empty rxFIFO. - * txIRQ from empty txFIFO which requires to refill txFIFO. - * - last interrupt is triggered by empty txFIFO. The last state is - * known by empty rxBuffer and txBuffer. If there is nothing to receive - * or send - both operations have been finished and interrupts can be - * disabled. - */ - - /* Data to send or read or expected to receive */ - if ((handle->txRemainingBytes != 0U) || (handle->rxRemainingBytes != 0U) || (handle->toReceiveCount != 0)) - { - /* Transmit or receive data */ - SPI_TransferHandleIRQInternal(base, handle); - /* No data to send or read or receive. Transfer ends. Set txTrigger to 0 level and - * enable txIRQ to confirm when txFIFO becomes empty */ - if ((0U == handle->txRemainingBytes) && (0U == handle->rxRemainingBytes) && (0 == handle->toReceiveCount)) - { - base->FIFOTRIG = base->FIFOTRIG & (~SPI_FIFOTRIG_TXLVL_MASK); - base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK; - } - else - { - uint32_t rxRemainingCount = SPI_BYTES_TO_COUNT(handle->dataWidth, handle->rxRemainingBytes); - /* If, there are no data to send or rxFIFO is already filled with necessary number of dummy data, - * disable txIRQ. From this point only rxIRQ is used to receive data without any transmission */ - toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; - if ((0U == handle->txRemainingBytes) && (rxRemainingCount <= toReceiveCount)) - { - base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXLVL_MASK; - } - /* Nothing to receive or transmit, but we still have pending data which are bellow rxLevel. - * Cannot clear rxFIFO, txFIFO might be still active */ - if (rxRemainingCount == 0U) - { - txRemainingBytes = handle->txRemainingBytes; - if ((txRemainingBytes == 0U) && (toReceiveCount != 0U) && - (toReceiveCount < SPI_FIFOTRIG_RXLVL_GET(base) + 1U)) - { - base->FIFOTRIG = (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | - SPI_FIFOTRIG_RXLVL((uint32_t)toReceiveCount - 1U); - } - } - else - { - /* Expected to receive less data than rxLevel value, we have to update rxLevel */ - if (rxRemainingCount < (SPI_FIFOTRIG_RXLVL_GET(base) + 1U)) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(rxRemainingCount - 1U); - } - } - } - } - else - { - /* Empty txFIFO is confirmed. Disable IRQs and restore triggers values */ - base->FIFOINTENCLR = SPI_FIFOINTENCLR_RXLVL_MASK | SPI_FIFOINTENCLR_TXLVL_MASK; - base->FIFOTRIG = (base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_RXLVL_MASK))) | - SPI_FIFOTRIG_RXLVL(handle->rxWatermark) | SPI_FIFOTRIG_TXLVL(handle->txWatermark); - /* set idle state and call user callback */ - handle->state = (uint32_t)kStatus_SPI_Idle; - if (handle->callback != NULL) - { - (handle->callback)(base, handle, handle->state, handle->userData); - } - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi.h deleted file mode 100644 index 2320e574cc9..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi.h +++ /dev/null @@ -1,746 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SPI_H_ -#define _FSL_SPI_H_ - -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/*! - * @addtogroup spi_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SPI driver version. */ -#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) -/*@}*/ - -/*! @brief Global variable for dummy data value setting. */ -extern volatile uint8_t s_dummyData[]; - -#ifndef SPI_DUMMYDATA -/*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */ -#define SPI_DUMMYDATA (0xFFU) -#endif - -/*! @brief Retry times for waiting flag. */ -#ifndef SPI_RETRY_TIMES -#define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ -#endif - -#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFFUL) -#define SPI_CTRLMASK (0xFFFF0000U) - -#define SPI_ASSERTNUM_SSEL(n) ((~(1UL << ((n) + 16UL))) & 0xF0000UL) -#define SPI_DEASSERTNUM_SSEL(n) (1UL << ((n) + 16UL)) -#define SPI_DEASSERT_ALL (0xF0000UL) - -#define SPI_FIFOWR_FLAGS_MASK (~(SPI_DEASSERT_ALL | SPI_FIFOWR_TXDATA_MASK | SPI_FIFOWR_LEN_MASK)) - -#define SPI_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_TXLVL_MASK) >> SPI_FIFOTRIG_TXLVL_SHIFT) -#define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT) - -/*! @brief SPI transfer option.*/ -typedef enum _spi_xfer_option -{ - kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), /*!< A delay may be inserted, defined in the DLY register.*/ - kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< SSEL will be deasserted at the end of a transfer */ -} spi_xfer_option_t; - -/*! @brief SPI data shifter direction options.*/ -typedef enum _spi_shift_direction -{ - kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */ - kSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. */ -} spi_shift_direction_t; - -/*! @brief SPI clock polarity configuration.*/ -typedef enum _spi_clock_polarity -{ - kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */ - kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */ -} spi_clock_polarity_t; - -/*! @brief SPI clock phase configuration.*/ -typedef enum _spi_clock_phase -{ - kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first - * cycle of a data transfer. */ - kSPI_ClockPhaseSecondEdge /*!< First edge on SCK occurs at the start of the - * first cycle of a data transfer. */ -} spi_clock_phase_t; - -/*! @brief txFIFO watermark values */ -typedef enum _spi_txfifo_watermark -{ - kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */ - kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */ - kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */ - kSPI_TxFifo3 = 3, /*!< SPI tx watermark at 3 items */ - kSPI_TxFifo4 = 4, /*!< SPI tx watermark at 4 items */ - kSPI_TxFifo5 = 5, /*!< SPI tx watermark at 5 items */ - kSPI_TxFifo6 = 6, /*!< SPI tx watermark at 6 items */ - kSPI_TxFifo7 = 7, /*!< SPI tx watermark at 7 items */ -} spi_txfifo_watermark_t; - -/*! @brief rxFIFO watermark values */ -typedef enum _spi_rxfifo_watermark -{ - kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */ - kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */ - kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */ - kSPI_RxFifo4 = 3, /*!< SPI rx watermark at 4 items */ - kSPI_RxFifo5 = 4, /*!< SPI rx watermark at 5 items */ - kSPI_RxFifo6 = 5, /*!< SPI rx watermark at 6 items */ - kSPI_RxFifo7 = 6, /*!< SPI rx watermark at 7 items */ - kSPI_RxFifo8 = 7, /*!< SPI rx watermark at 8 items */ -} spi_rxfifo_watermark_t; - -/*! @brief Transfer data width */ -typedef enum _spi_data_width -{ - kSPI_Data4Bits = 3, /*!< 4 bits data width */ - kSPI_Data5Bits = 4, /*!< 5 bits data width */ - kSPI_Data6Bits = 5, /*!< 6 bits data width */ - kSPI_Data7Bits = 6, /*!< 7 bits data width */ - kSPI_Data8Bits = 7, /*!< 8 bits data width */ - kSPI_Data9Bits = 8, /*!< 9 bits data width */ - kSPI_Data10Bits = 9, /*!< 10 bits data width */ - kSPI_Data11Bits = 10, /*!< 11 bits data width */ - kSPI_Data12Bits = 11, /*!< 12 bits data width */ - kSPI_Data13Bits = 12, /*!< 13 bits data width */ - kSPI_Data14Bits = 13, /*!< 14 bits data width */ - kSPI_Data15Bits = 14, /*!< 15 bits data width */ - kSPI_Data16Bits = 15, /*!< 16 bits data width */ -} spi_data_width_t; - -/*! @brief Slave select */ -typedef enum _spi_ssel -{ - kSPI_Ssel0 = 0, /*!< Slave select 0 */ - kSPI_Ssel1 = 1, /*!< Slave select 1 */ - kSPI_Ssel2 = 2, /*!< Slave select 2 */ - kSPI_Ssel3 = 3, /*!< Slave select 3 */ -} spi_ssel_t; - -/*! @brief ssel polarity */ -typedef enum _spi_spol -{ - kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0(1), - kSPI_Spol1ActiveHigh = SPI_CFG_SPOL1(1), - kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2(1), -#if defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) && (FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) - kSPI_SpolActiveAllHigh = (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh), -#else - kSPI_Spol3ActiveHigh = SPI_CFG_SPOL3(1), - kSPI_SpolActiveAllHigh = - (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh | kSPI_Spol3ActiveHigh), -#endif - kSPI_SpolActiveAllLow = 0, -} spi_spol_t; - -/*! - * @brief SPI delay time configure structure. - * Note: - * The DLY register controls several programmable delays related to SPI signalling, - * it stands for how many SPI clock time will be inserted. - * The maxinun value of these delay time is 15. - */ -typedef struct _spi_delay_config -{ - uint8_t preDelay; /*!< Delay between SSEL assertion and the beginning of transfer. */ - uint8_t postDelay; /*!< Delay between the end of transfer and SSEL deassertion. */ - uint8_t frameDelay; /*!< Delay between frame to frame. */ - uint8_t transferDelay; /*!< Delay between transfer to transfer. */ -} spi_delay_config_t; - -/*! @brief SPI master user configure structure.*/ -typedef struct _spi_master_config -{ - bool enableLoopback; /*!< Enable loopback for test purpose */ - bool enableMaster; /*!< Enable SPI at initialization time */ - spi_clock_polarity_t polarity; /*!< Clock polarity */ - spi_clock_phase_t phase; /*!< Clock phase */ - spi_shift_direction_t direction; /*!< MSB or LSB */ - uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */ - spi_data_width_t dataWidth; /*!< Width of the data */ - spi_ssel_t sselNum; /*!< Slave select number */ - spi_spol_t sselPol; /*!< Configure active CS polarity */ - uint8_t txWatermark; /*!< txFIFO watermark */ - uint8_t rxWatermark; /*!< rxFIFO watermark */ - spi_delay_config_t delayConfig; /*!< Delay configuration. */ -} spi_master_config_t; - -/*! @brief SPI slave user configure structure.*/ -typedef struct _spi_slave_config -{ - bool enableSlave; /*!< Enable SPI at initialization time */ - spi_clock_polarity_t polarity; /*!< Clock polarity */ - spi_clock_phase_t phase; /*!< Clock phase */ - spi_shift_direction_t direction; /*!< MSB or LSB */ - spi_data_width_t dataWidth; /*!< Width of the data */ - spi_spol_t sselPol; /*!< Configure active CS polarity */ - uint8_t txWatermark; /*!< txFIFO watermark */ - uint8_t rxWatermark; /*!< rxFIFO watermark */ -} spi_slave_config_t; - -/*! @brief SPI transfer status.*/ -enum -{ - kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0), /*!< SPI bus is busy */ - kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1), /*!< SPI is idle */ - kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI error */ - kStatus_SPI_BaudrateNotSupport = - MAKE_STATUS(kStatusGroup_LPC_SPI, 3), /*!< Baudrate is not support in current clock source */ - kStatus_SPI_Timeout = MAKE_STATUS(kStatusGroup_LPC_SPI, 4) /*!< SPI timeout polling status flags. */ -}; - -/*! @brief SPI interrupt sources.*/ -enum _spi_interrupt_enable -{ - kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, /*!< Rx level interrupt */ - kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, /*!< Tx level interrupt */ -}; - -/*! @brief SPI status flags.*/ -enum _spi_statusflags -{ - kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK, /*!< txFifo is empty */ - kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK, /*!< txFifo is not full */ - kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, /*!< rxFIFO is not empty */ - kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK, /*!< rxFIFO is full */ -}; - -/*! @brief SPI transfer structure */ -typedef struct _spi_transfer -{ - uint8_t *txData; /*!< Send buffer */ - uint8_t *rxData; /*!< Receive buffer */ - uint32_t configFlags; /*!< Additional option to control transfer, @ref spi_xfer_option_t. */ - size_t dataSize; /*!< Transfer bytes */ -} spi_transfer_t; - -/*! @brief SPI half-duplex(master only) transfer structure */ -typedef struct _spi_half_duplex_transfer -{ - uint8_t *txData; /*!< Send buffer */ - uint8_t *rxData; /*!< Receive buffer */ - size_t txDataSize; /*!< Transfer bytes for transmit */ - size_t rxDataSize; /*!< Transfer bytes */ - uint32_t configFlags; /*!< Transfer configuration flags, @ref spi_xfer_option_t. */ - bool isPcsAssertInTransfer; /*!< If PCS pin keep assert between transmit and receive. true for assert and false for - deassert. */ - bool isTransmitFirst; /*!< True for transmit first and false for receive first. */ -} spi_half_duplex_transfer_t; - -/*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */ -typedef struct _spi_config -{ - spi_data_width_t dataWidth; - spi_ssel_t sselNum; -} spi_config_t; - -/*! @brief Master handle type */ -typedef struct _spi_master_handle spi_master_handle_t; - -/*! @brief Slave handle type */ -typedef spi_master_handle_t spi_slave_handle_t; - -/*! @brief SPI master callback for finished transmit */ -typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI slave callback for finished transmit */ -typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI transfer handle structure */ -struct _spi_master_handle -{ - uint8_t *volatile txData; /*!< Transfer buffer */ - uint8_t *volatile rxData; /*!< Receive buffer */ - volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */ - volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */ - volatile int8_t toReceiveCount; /*!< The number of data expected to receive in data width. Since the received count - and sent count should be the same to complete the transfer, if the sent count is - x and the received count is y, toReceiveCount is x-y. */ - size_t totalByteCount; /*!< A number of transfer bytes */ - volatile uint32_t state; /*!< SPI internal state */ - spi_master_callback_t callback; /*!< SPI callback */ - void *userData; /*!< Callback parameter */ - uint8_t dataWidth; /*!< Width of the data [Valid values: 1 to 16] */ - uint8_t sselNum; /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */ - uint32_t configFlags; /*!< Additional option to control transfer */ - uint8_t txWatermark; /*!< txFIFO watermark */ - uint8_t rxWatermark; /*!< rxFIFO watermark */ -}; - -/*! @brief Typedef for master interrupt handler. */ -typedef void (*flexcomm_spi_master_irq_handler_t)(SPI_Type *base, spi_master_handle_t *handle); - -/*! @brief Typedef for slave interrupt handler. */ -typedef void (*flexcomm_spi_slave_irq_handler_t)(SPI_Type *base, spi_slave_handle_t *handle); -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @brief Returns instance number for SPI peripheral base address. */ -uint32_t SPI_GetInstance(SPI_Type *base); - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Sets the SPI master configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). - * User may use the initialized structure unchanged in SPI_MasterInit(), or modify - * some fields of the structure before calling SPI_MasterInit(). After calling this API, - * the master is ready to transfer. - * Example: - @code - spi_master_config_t config; - SPI_MasterGetDefaultConfig(&config); - @endcode - * - * @param config pointer to master config structure - */ -void SPI_MasterGetDefaultConfig(spi_master_config_t *config); - -/*! - * @brief Initializes the SPI with master configuration. - * - * The configuration structure can be filled by user from scratch, or be set with default - * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. - * Example - @code - spi_master_config_t config = { - .baudRate_Bps = 400000, - ... - }; - SPI_MasterInit(SPI0, &config); - @endcode - * - * @param base SPI base pointer - * @param config pointer to master configuration structure - * @param srcClock_Hz Source clock frequency. - */ -status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Sets the SPI slave configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). - * Modify some fields of the structure before calling SPI_SlaveInit(). - * Example: - @code - spi_slave_config_t config; - SPI_SlaveGetDefaultConfig(&config); - @endcode - * - * @param config pointer to slave configuration structure - */ -void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config); - -/*! - * @brief Initializes the SPI with slave configuration. - * - * The configuration structure can be filled by user from scratch or be set with - * default values by SPI_SlaveGetDefaultConfig(). - * After calling this API, the slave is ready to transfer. - * Example - @code - spi_slave_config_t config = { - .polarity = flexSPIClockPolarity_ActiveHigh; - .phase = flexSPIClockPhase_FirstEdge; - .direction = flexSPIMsbFirst; - ... - }; - SPI_SlaveInit(SPI0, &config); - @endcode - * - * @param base SPI base pointer - * @param config pointer to slave configuration structure - */ -status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config); - -/*! - * @brief De-initializes the SPI. - * - * Calling this API resets the SPI module, gates the SPI clock. - * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. - * - * @param base SPI base pointer - */ -void SPI_Deinit(SPI_Type *base); - -/*! - * @brief Enable or disable the SPI Master or Slave - * @param base SPI base pointer - * @param enable or disable ( true = enable, false = disable) - */ -static inline void SPI_Enable(SPI_Type *base, bool enable) -{ - if (enable) - { - base->CFG |= SPI_CFG_ENABLE_MASK; - } - else - { - base->CFG &= ~SPI_CFG_ENABLE_MASK; - } -} - -/*! @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the status flag. - * - * @param base SPI base pointer - * @return SPI Status, use status flag to AND @ref _spi_statusflags could get the related status. - */ -static inline uint32_t SPI_GetStatusFlags(SPI_Type *base) -{ - assert(NULL != base); - return base->FIFOSTAT; -} - -/*! @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the interrupt for the SPI. - * - * @param base SPI base pointer - * @param irqs SPI interrupt source. The parameter can be any combination of the following values: - * @arg kSPI_RxLvlIrq - * @arg kSPI_TxLvlIrq - */ -static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs) -{ - assert(NULL != base); - base->FIFOINTENSET = irqs; -} - -/*! - * @brief Disables the interrupt for the SPI. - * - * @param base SPI base pointer - * @param irqs SPI interrupt source. The parameter can be any combination of the following values: - * @arg kSPI_RxLvlIrq - * @arg kSPI_TxLvlIrq - */ -static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs) -{ - assert(NULL != base); - base->FIFOINTENCLR = irqs; -} - -/*! @} */ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Enables the DMA request from SPI txFIFO. - * - * @param base SPI base pointer - * @param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableTxDMA(SPI_Type *base, bool enable); - -/*! - * @brief Enables the DMA request from SPI rxFIFO. - * - * @param base SPI base pointer - * @param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableRxDMA(SPI_Type *base, bool enable); - -/*! @} */ - -/*! - * @name Bus Operations - * @{ - */ -/*! - * @brief Returns the configurations. - * - * @param base SPI peripheral address. - * @return return configurations which contain datawidth and SSEL numbers. - * return data type is a pointer of spi_config_t. - */ -void *SPI_GetConfig(SPI_Type *base); - -/*! - * @brief Sets the baud rate for SPI transfer. This is only used in master. - * - * @param base SPI base pointer - * @param baudrate_Bps baud rate needed in Hz. - * @param srcClock_Hz SPI source clock frequency in Hz. - */ -status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Writes a data into the SPI data register. - * - * @param base SPI base pointer - * @param data needs to be write. - * @param configFlags transfer configuration options @ref spi_xfer_option_t - */ -void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags); - -/*! - * @brief Gets a data from the SPI data register. - * - * @param base SPI base pointer - * @return Data in the register. - */ -static inline uint32_t SPI_ReadData(SPI_Type *base) -{ - assert(NULL != base); - return base->FIFORD; -} - -/*! - * @brief Set delay time for transfer. - * the delay uint is SPI clock time, maximum value is 0xF. - * @param base SPI base pointer - * @param config configuration for delay option @ref spi_delay_config_t. - */ -static inline void SPI_SetTransferDelay(SPI_Type *base, const spi_delay_config_t *config) -{ - assert(NULL != base); - assert(NULL != config); - base->DLY = (SPI_DLY_PRE_DELAY(config->preDelay) | SPI_DLY_POST_DELAY(config->postDelay) | - SPI_DLY_FRAME_DELAY(config->frameDelay) | SPI_DLY_TRANSFER_DELAY(config->transferDelay)); -} - -/*! - * @brief Set up the dummy data. - * - * @param base SPI peripheral address. - * @param dummyData Data to be transferred when tx buffer is NULL. - */ -void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData); - -/*! @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the SPI master handle. - * - * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback Callback function. - * @param userData User data. - */ -status_t SPI_MasterTransferCreateHandle(SPI_Type *base, - spi_master_handle_t *handle, - spi_master_callback_t callback, - void *userData); - -/*! - * @brief Transfers a block of data using a polling method. - * - * @param base SPI base pointer - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Timeout The transfer timed out and was aborted. - */ -status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer); - -/*! - * @brief Performs a non-blocking SPI interrupt transfer. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer); - -/*! - * @brief Transfers a block of data using a polling method. - * - * This function will do a half-duplex transfer for SPI master, This is a blocking function, - * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, - * users can set transmit first or receive first. - * - * @param base SPI base pointer - * @param xfer pointer to spi_half_duplex_transfer_t structure - * @return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer); - -/*! - * @brief Performs a non-blocking SPI interrupt transfer. - * - * This function using polling way to do the first half transimission and using interrupts to - * do the second half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_half_duplex_transfer_t structure - * @return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, - spi_master_handle_t *handle, - spi_half_duplex_transfer_t *xfer); - -/*! - * @brief Gets the master transfer count. - * - * This function gets the master transfer count. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * @param count The number of bytes transferred by using the non-blocking transaction. - * @return status of status_t. - */ -status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count); - -/*! - * @brief SPI master aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle); - -/*! - * @brief Interrupts the handler for the SPI. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle); - -/*! - * @brief Initializes the SPI slave handle. - * - * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback Callback function. - * @param userData User data. - */ -static inline status_t SPI_SlaveTransferCreateHandle(SPI_Type *base, - spi_slave_handle_t *handle, - spi_slave_callback_t callback, - void *userData) -{ - return SPI_MasterTransferCreateHandle(base, handle, callback, userData); -} - -/*! - * @brief Performs a non-blocking SPI slave interrupt transfer. - * - * @note The API returns immediately after the transfer initialization is finished. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer) -{ - return SPI_MasterTransferNonBlocking(base, handle, xfer); -} - -/*! - * @brief Gets the slave transfer count. - * - * This function gets the slave transfer count. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * @param count The number of bytes transferred by using the non-blocking transaction. - * @return status of status_t. - */ -static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count) -{ - return SPI_MasterTransferGetCount(base, (spi_master_handle_t *)handle, count); -} - -/*! - * @brief SPI slave aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state. - */ -static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle) -{ - SPI_MasterTransferAbort(base, (spi_master_handle_t *)handle); -} - -/*! - * @brief Interrupts a handler for the SPI slave. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_slave_handle_t structure which stores the transfer state - */ -static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle) -{ - SPI_MasterTransferHandleIRQ(base, handle); -} - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_SPI_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi_dma.c deleted file mode 100644 index 6182f9952e1..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi_dma.c +++ /dev/null @@ -1,568 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_spi_dma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi_dma" -#endif - -/*configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; - *fifowr |= ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; -} - -static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr) -{ - *fifowr |= ((uint32_t)SPI_DEASSERT_ALL & (~(uint32_t)SPI_DEASSERTNUM_SSEL((uint32_t)config->sselNum))); - /* set width of data - range asserted at entry */ - *fifowr |= SPI_FIFOWR_LEN(config->dataWidth); -} - -static void PrepareTxLastWord(spi_transfer_t *xfer, uint32_t *txLastWord, spi_config_t *config) -{ - if (config->dataWidth > kSPI_Data8Bits) - { - *txLastWord = (((uint32_t)xfer->txData[xfer->dataSize - 1U] << 8U) | (xfer->txData[xfer->dataSize - 2U])); - } - else - { - *txLastWord = xfer->txData[xfer->dataSize - 1U]; - } - XferToFifoWR(xfer, txLastWord); - SpiConfigToFifoWR(config, txLastWord); -} - -static void SPI_SetupDummy(SPI_Type *base, spi_dma_txdummy_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p) -{ - uint32_t instance = SPI_GetInstance(base); - uint32_t dummydata = (uint32_t)s_dummyData[instance]; - dummydata |= (uint32_t)s_dummyData[instance] << 8U; - - dummy->word = dummydata; - dummy->lastWord = dummydata; - - XferToFifoWR(xfer, &dummy->word); - XferToFifoWR(xfer, &dummy->lastWord); - SpiConfigToFifoWR(spi_config_p, &dummy->word); - SpiConfigToFifoWR(spi_config_p, &dummy->lastWord); - /* Clear the end of transfer bit for continue word transfer. */ - dummy->word &= (~(uint32_t)kSPI_FrameAssert); -} - -/*! - * brief Initialize the SPI master DMA handle. - * - * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * param base SPI peripheral base address. - * param handle SPI handle pointer. - * param callback User callback function called at the end of a transfer. - * param userData User data for callback. - * param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle) -{ - uint32_t instance; - - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } - /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - instance = SPI_GetInstance(base); - - (void)memset(handle, 0, sizeof(*handle)); - /* Set spi base to handle */ - handle->txHandle = txHandle; - handle->rxHandle = rxHandle; - handle->callback = callback; - handle->userData = userData; - - /* Set SPI state to idle */ - handle->state = (uint8_t)kSPI_Idle; - - /* Set handle to global state */ - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - /* Install callback for Tx dma channel */ - DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]); - DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]); - - return kStatus_Success; -} - -/*! - * brief Perform a non-blocking SPI transfer using DMA. - * - * note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * param base SPI peripheral base address. - * param handle SPI DMA handle pointer. - * param xfer Pointer to dma transfer structure. - * retval kStatus_Success Successfully start a transfer. - * retval kStatus_InvalidArgument Input argument is invalid. - * retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) -{ - assert(!((NULL == handle) || (NULL == xfer))); - - uint32_t instance; - status_t result = kStatus_Success; - spi_config_t *spi_config_p; - uint32_t address; - - if ((NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - - /* Byte size is zero. */ - if (xfer->dataSize == 0U) - { - return kStatus_InvalidArgument; - } - /* cannot get instance from base address */ - instance = SPI_GetInstance(base); - - /* Check if the device is busy */ - if (handle->state == (uint8_t)kSPI_Busy) - { - return kStatus_SPI_Busy; - } - else - { - /* Clear FIFOs before transfer. */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - - dma_transfer_config_t xferConfig = {0}; - spi_config_p = (spi_config_t *)SPI_GetConfig(base); - - handle->state = (uint8_t)kSPI_Busy; - handle->transferSize = xfer->dataSize; - - /* receive */ - SPI_EnableRxDMA(base, true); - address = (uint32_t)&base->FIFORD; - if (xfer->rxData != NULL) - { - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, xfer->rxData, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_PeripheralToMemory, NULL); - } - else - { - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, &s_rxDummy, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_StaticToStatic, NULL); - } - (void)DMA_SubmitTransfer(handle->rxHandle, &xferConfig); - handle->rxInProgress = true; - DMA_StartTransfer(handle->rxHandle); - - /* transmit */ - SPI_EnableTxDMA(base, true); - address = (uint32_t)&base->FIFOWR; - if (xfer->txData != NULL) - { - if ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) - { - PrepareTxLastWord(xfer, &s_txLastWord[instance], spi_config_p); - } - /* If end of tranfer function is enabled and data transfer frame is bigger then 1, use dma - * descriptor to send the last data. - */ - if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2U) : (xfer->dataSize > 1U))) - { - dma_xfercfg_t tmp_xfercfg; - tmp_xfercfg.valid = true; - tmp_xfercfg.swtrig = true; - tmp_xfercfg.intA = true; - tmp_xfercfg.byteWidth = sizeof(uint32_t); - tmp_xfercfg.srcInc = 0; - tmp_xfercfg.dstInc = 0; - tmp_xfercfg.transferCount = 1; - tmp_xfercfg.reload = false; - tmp_xfercfg.clrtrig = false; - tmp_xfercfg.intB = false; - /* Create chained descriptor to transmit last word */ - DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txLastWord[instance], - (uint32_t *)address, NULL); - - DMA_PrepareTransfer( - &xferConfig, xfer->txData, (uint32_t *)address, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2U) : (xfer->dataSize - 1U)), - kDMA_MemoryToPeripheral, &s_spi_descriptor_table[instance]); - /* Disable interrupts for first descriptor to avoid calling callback twice. */ - xferConfig.xfercfg.intA = false; - xferConfig.xfercfg.intB = false; - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - else - { - DMA_PrepareTransfer( - &xferConfig, xfer->txData, (uint32_t *)address, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_MemoryToPeripheral, NULL); - (void)DMA_SubmitTransfer(handle->txHandle, &xferConfig); - } - } - else - { - /* Setup tx dummy data. */ - SPI_SetupDummy(base, &s_txDummy[instance], xfer, spi_config_p); - if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2U) : (xfer->dataSize > 1U))) - { - dma_xfercfg_t tmp_xfercfg; - tmp_xfercfg.valid = true; - tmp_xfercfg.swtrig = true; - tmp_xfercfg.intA = true; - tmp_xfercfg.byteWidth = sizeof(uint32_t); - tmp_xfercfg.srcInc = 0; - tmp_xfercfg.dstInc = 0; - tmp_xfercfg.transferCount = 1; - tmp_xfercfg.reload = false; - tmp_xfercfg.clrtrig = false; - tmp_xfercfg.intB = false; - /* Create chained descriptor to transmit last word */ - DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord, - (uint32_t *)address, NULL); - /* Use common API to setup first descriptor */ - DMA_PrepareTransfer( - &xferConfig, &s_txDummy[instance].word, (uint32_t *)address, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2U) : (xfer->dataSize - 1U)), - kDMA_StaticToStatic, &s_spi_descriptor_table[instance]); - /* Disable interrupts for first descriptor to avoid calling callback twice */ - xferConfig.xfercfg.intA = false; - xferConfig.xfercfg.intB = false; - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - else - { - DMA_PrepareTransfer( - &xferConfig, &s_txDummy[instance].word, (uint32_t *)address, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_StaticToStatic, NULL); - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - } - - handle->txInProgress = true; - uint32_t tmpData = 0U; - uint32_t writeAddress = (uint32_t) & (base->FIFOWR) + 2UL; - XferToFifoWR(xfer, &tmpData); - SpiConfigToFifoWR(spi_config_p, &tmpData); - - /* Setup the control info. - * Halfword writes to just the control bits (offset 0xE22) doesn't push anything into the FIFO. - * And the data access type of control bits must be uint16_t, byte writes or halfword writes to FIFOWR - * will push the data and the current control bits into the FIFO. - */ - if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize == 2U) : (xfer->dataSize == 1U))) - { - *(uint16_t *)writeAddress = (uint16_t)(tmpData >> 16U); - } - else - { - /* Clear the SPI_FIFOWR_EOT_MASK bit when data is not the last. */ - tmpData &= (~(uint32_t)kSPI_FrameAssert); - *(uint16_t *)writeAddress = (uint16_t)(tmpData >> 16U); - } - - DMA_StartTransfer(handle->txHandle); - } - - return result; -} - -/*! - * brief Transfers a block of data using a DMA method. - * - * This function using polling way to do the first half transimission and using DMA way to - * do the srcond half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * param base SPI base pointer - * param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. - * param transfer A pointer to the spi_half_duplex_transfer_t structure. - * return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer) -{ - assert((xfer != NULL) && (handle != NULL)); - spi_transfer_t tempXfer = {0}; - status_t status; - - if (xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the pcs pin keep assert between transmit and receive. */ - if (xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); - } - else - { - tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; - } - - status = SPI_MasterTransferBlocking(base, &tempXfer); - if (status != kStatus_Success) - { - return status; - } - - if (xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - status = SPI_MasterTransferDMA(base, handle, &tempXfer); - - return status; -} - -static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) -{ - spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; - spi_dma_handle_t *spiHandle = privHandle->handle; - SPI_Type *base = privHandle->base; - - /* change the state */ - spiHandle->rxInProgress = false; - - /* All finished, call the callback */ - if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) - { - spiHandle->state = (uint8_t)kSPI_Idle; - if (spiHandle->callback != NULL) - { - (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); - } - } -} - -static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) -{ - spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; - spi_dma_handle_t *spiHandle = privHandle->handle; - SPI_Type *base = privHandle->base; - - /* change the state */ - spiHandle->txInProgress = false; - - /* All finished, call the callback */ - if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) - { - spiHandle->state = (uint8_t)kSPI_Idle; - if (spiHandle->callback != NULL) - { - (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); - } - } -} - -/*! - * brief Abort a SPI transfer using DMA. - * - * param base SPI peripheral base address. - * param handle SPI DMA handle pointer. - */ -void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) -{ - assert(NULL != handle); - - /* Stop tx transfer first */ - DMA_AbortTransfer(handle->txHandle); - /* Then rx transfer */ - DMA_AbortTransfer(handle->rxHandle); - - /* Set the handle state */ - handle->txInProgress = false; - handle->rxInProgress = false; - handle->state = (uint8_t)kSPI_Idle; -} - -/*! - * brief Gets the master DMA transfer remaining bytes. - * - * This function gets the master DMA transfer remaining bytes. - * - * param base SPI peripheral base address. - * param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * param count A number of bytes transferred by the non-blocking transaction. - * return status of status_t. - */ -status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != (uint8_t)kSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - size_t bytes; - - bytes = DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel); - - *count = handle->transferSize - bytes; - - return kStatus_Success; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi_dma.h deleted file mode 100644 index 6adc6c86681..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi_dma.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SPI_DMA_H_ -#define _FSL_SPI_DMA_H_ - -#include "fsl_dma.h" -#include "fsl_spi.h" - -/*! - * @addtogroup spi_dma_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SPI DMA driver version 2.1.1. */ -#define FSL_SPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) -/*@}*/ - -typedef struct _spi_dma_handle spi_dma_handle_t; - -/*! @brief SPI DMA callback called at the end of transfer. */ -typedef void (*spi_dma_callback_t)(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI DMA transfer handle, users should not touch the content of the handle.*/ -struct _spi_dma_handle -{ - volatile bool txInProgress; /*!< Send transfer finished */ - volatile bool rxInProgress; /*!< Receive transfer finished */ - dma_handle_t *txHandle; /*!< DMA handler for SPI send */ - dma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ - uint8_t bytesPerFrame; /*!< Bytes in a frame for SPI transfer */ - spi_dma_callback_t callback; /*!< Callback for SPI DMA transfer */ - void *userData; /*!< User Data for SPI DMA callback */ - uint32_t state; /*!< Internal state of SPI DMA transfer */ - size_t transferSize; /*!< Bytes need to be transfer */ -}; - -/******************************************************************************* - * APIs - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name DMA Transactional - * @{ - */ - -/*! - * @brief Initialize the SPI master DMA handle. - * - * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback User callback function called at the end of a transfer. - * @param userData User data for callback. - * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle); - -/*! - * @brief Perform a non-blocking SPI transfer using DMA. - * - * @note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - * @param xfer Pointer to dma transfer structure. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer); - -/*! - * @brief Transfers a block of data using a DMA method. - * - * This function using polling way to do the first half transimission and using DMA way to - * do the srcond half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * @param base SPI base pointer - * @param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. - * @param xfer A pointer to the spi_half_duplex_transfer_t structure. - * @return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer); - -/*! - * @brief Initialize the SPI slave DMA handle. - * - * This function initializes the SPI slave DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback User callback function called at the end of a transfer. - * @param userData User data for callback. - * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -static inline status_t SPI_SlaveTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle) -{ - return SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle); -} - -/*! - * @brief Perform a non-blocking SPI transfer using DMA. - * - * @note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - * @param xfer Pointer to dma transfer structure. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -static inline status_t SPI_SlaveTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) -{ - return SPI_MasterTransferDMA(base, handle, xfer); -} - -/*! - * @brief Abort a SPI transfer using DMA. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - */ -void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle); - -/*! - * @brief Gets the master DMA transfer remaining bytes. - * - * This function gets the master DMA transfer remaining bytes. - * - * @param base SPI peripheral base address. - * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * @param count A number of bytes transferred by the non-blocking transaction. - * @return status of status_t. - */ -status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count); - -/*! - * @brief Abort a SPI transfer using DMA. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - */ -static inline void SPI_SlaveTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) -{ - SPI_MasterTransferAbortDMA(base, handle); -} - -/*! - * @brief Gets the slave DMA transfer remaining bytes. - * - * This function gets the slave DMA transfer remaining bytes. - * - * @param base SPI peripheral base address. - * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * @param count A number of bytes transferred by the non-blocking transaction. - * @return status of status_t. - */ -static inline status_t SPI_SlaveTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) -{ - return SPI_MasterTransferGetCountDMA(base, handle, count); -} - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_SPI_DMA_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sysctl.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sysctl.c deleted file mode 100644 index 1d0dd9ccf64..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sysctl.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sysctl.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.sysctl" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get the instance. - * - * @param base SYSCTL peripheral base address. - * @return Instance number. - */ -static uint32_t SYSCTL_GetInstance(SYSCTL_Type *base); - -/*! - * @brief Enable SYSCTL write protect - * - * @param base SYSCTL peripheral base address. - * @param regAddr register address - * @param value value to write. - */ -static void SYSCTL_UpdateRegister(SYSCTL_Type *base, volatile uint32_t *regAddr, uint32_t value); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief SYSCTL base address array name */ -static SYSCTL_Type *const s_sysctlBase[] = SYSCTL_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief SYSCTL clock array name */ -static const clock_ip_name_t s_sysctlClock[] = SYSCTL_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static void SYSCTL_UpdateRegister(SYSCTL_Type *base, volatile uint32_t *regAddr, uint32_t value) -{ - base->UPDATELCKOUT &= ~SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK; - *regAddr = value; - base->UPDATELCKOUT |= SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK; -} - -static uint32_t SYSCTL_GetInstance(SYSCTL_Type *base) -{ - uint8_t instance = 0; - - while ((instance < ARRAY_SIZE(s_sysctlBase)) && (s_sysctlBase[instance] != base)) - { - instance++; - } - - assert(instance < ARRAY_SIZE(s_sysctlBase)); - - return instance; -} - -/*! - * @brief SYSCTL initial - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Init(SYSCTL_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable SYSCTL clock. */ - CLOCK_EnableClock(s_sysctlClock[SYSCTL_GetInstance(base)]); -#endif -} - -/*! - * @brief SYSCTL deinit - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Deinit(SYSCTL_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable SYSCTL clock. */ - CLOCK_DisableClock(s_sysctlClock[SYSCTL_GetInstance(base)]); -#endif -} - -/*! - * @brief SYSCTL share set configure for separate signal - * - * @param base Base address of the SYSCTL peripheral - * @param flexCommIndex index of flexcomm,reference _sysctl_share_src - * @param setIndex share set for sck, reference _sysctl_share_set_index - * - */ -void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set) -{ - uint32_t tempReg = base->FCCTRLSEL[flexCommIndex]; - - tempReg &= ~((uint32_t)SYSCTL_FCCTRLSEL_SCKINSEL_MASK << (uint32_t)signal); - tempReg |= (set + 1U) << (uint32_t)signal; - - SYSCTL_UpdateRegister(base, &base->FCCTRLSEL[flexCommIndex], tempReg); -} - -/*! - * @brief SYSCTL share set configure for flexcomm - * - * @param base Base address of the SYSCTL peripheral. - * @param flexCommIndex index of flexcomm, reference _sysctl_share_src - * @param sckSet share set for sck,reference _sysctl_share_set_index - * @param wsSet share set for ws, reference _sysctl_share_set_index - * @param dataInSet share set for data in, reference _sysctl_share_set_index - * @param dataOutSet share set for data out, reference _sysctl_share_set_index - * - */ -void SYSCTL_SetFlexcommShareSet( - SYSCTL_Type *base, uint32_t flexCommIndex, uint32_t sckSet, uint32_t wsSet, uint32_t dataInSet, uint32_t dataOutSet) -{ - uint32_t tempReg = base->FCCTRLSEL[flexCommIndex]; - - tempReg &= ~(SYSCTL_FCCTRLSEL_SCKINSEL_MASK | SYSCTL_FCCTRLSEL_WSINSEL_MASK | SYSCTL_FCCTRLSEL_DATAINSEL_MASK | - SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK); - tempReg |= SYSCTL_FCCTRLSEL_SCKINSEL(sckSet + 1U) | SYSCTL_FCCTRLSEL_WSINSEL(wsSet + 1U) | - SYSCTL_FCCTRLSEL_DATAINSEL(dataInSet + 1U) | SYSCTL_FCCTRLSEL_DATAOUTSEL(dataOutSet + 1U); - - SYSCTL_UpdateRegister(base, &base->FCCTRLSEL[flexCommIndex], tempReg); -} - -/*! - * @brief SYSCTL share set source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param sckShareSrc sck source for this share set,reference _sysctl_share_src - * @param wsShareSrc ws source for this share set,reference _sysctl_share_src - * @param dataInShareSrc data in source for this share set,reference _sysctl_share_src - * @param dataOutShareSrc data out source for this share set,reference _sysctl_dataout_mask - * - */ -void SYSCTL_SetShareSetSrc(SYSCTL_Type *base, - uint32_t setIndex, - uint32_t sckShareSrc, - uint32_t wsShareSrc, - uint32_t dataInShareSrc, - uint32_t dataOutShareSrc) -{ - uint32_t tempReg = base->SHAREDCTRLSET[setIndex]; - - /* WS,SCK,DATA IN */ - tempReg &= ~(SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK | SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK | - SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK); - tempReg |= SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(sckShareSrc) | SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(wsShareSrc) | - SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(dataInShareSrc); - - /* data out */ - tempReg &= ~(SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK | SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK | - SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK | SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK | - SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK); - tempReg |= dataOutShareSrc; - - SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg); -} - -/*! - * @brief SYSCTL sck source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param sckShareSrc sck source fro this share set,reference _sysctl_share_src - * - */ -void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base, - uint32_t setIndex, - sysctl_sharedctrlset_signal_t signal, - uint32_t shareSrc) -{ - uint32_t tempReg = base->SHAREDCTRLSET[setIndex]; - - if (signal == kSYSCTL_SharedCtrlSignalDataOut) - { - tempReg |= 1UL << ((uint32_t)signal + shareSrc); - } - else - { - tempReg &= ~((uint32_t)SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK << (uint32_t)signal); - tempReg |= shareSrc << (uint32_t)signal; - } - - SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg); -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sysctl.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sysctl.h deleted file mode 100644 index 0a1be88469c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sysctl.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_SYSCTL_H_ -#define _FSL_SYSCTL_H_ - -#include "fsl_common.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup sysctl - * @{ - */ - -/*! @file */ -/*! @file fsl_sysctl.h */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Group sysctl driver version for SDK */ -#define FSL_SYSCTL_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) /*!< Version 2.0.5. */ -/*@}*/ - -/*! @brief SYSCTL share set*/ -enum _sysctl_share_set_index -{ - kSYSCTL_ShareSet0 = 0, /*!< share set 0 */ - kSYSCTL_ShareSet1 = 1, /*!< share set 1 */ -}; - -/*! @brief SYSCTL flexcomm signal */ -typedef enum _sysctl_fcctrlsel_signal -{ - kSYSCTL_FlexcommSignalSCK = SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT, /*!< SCK signal */ - kSYSCTL_FlexcommSignalWS = SYSCTL_FCCTRLSEL_WSINSEL_SHIFT, /*!< WS signal */ - kSYSCTL_FlexcommSignalDataIn = SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT, /*!< Data in signal */ - kSYSCTL_FlexcommSignalDataOut = SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT, /*!< Data out signal */ -} sysctl_fcctrlsel_signal_t; - -/*! @brief SYSCTL flexcomm index*/ -enum _sysctl_share_src -{ - kSYSCTL_Flexcomm0 = 0, /*!< share set 0 */ - kSYSCTL_Flexcomm1 = 1, /*!< share set 1 */ - kSYSCTL_Flexcomm2 = 2, /*!< share set 2 */ - kSYSCTL_Flexcomm4 = 4, /*!< share set 4 */ - kSYSCTL_Flexcomm5 = 5, /*!< share set 5 */ - kSYSCTL_Flexcomm6 = 6, /*!< share set 6 */ - kSYSCTL_Flexcomm7 = 7, /*!< share set 7 */ -}; - -/*! @brief SYSCTL shared data out mask */ -enum _sysctl_dataout_mask -{ - kSYSCTL_Flexcomm0DataOut = SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK, /*!< share set 0 */ - kSYSCTL_Flexcomm1DataOut = SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK, /*!< share set 1 */ - kSYSCTL_Flexcomm2DataOut = SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK, /*!< share set 2 */ - kSYSCTL_Flexcomm4DataOut = SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK, /*!< share set 4 */ - kSYSCTL_Flexcomm5DataOut = SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK, /*!< share set 5 */ - kSYSCTL_Flexcomm6DataOut = SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK, /*!< share set 6 */ - kSYSCTL_Flexcomm7DataOut = SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK, /*!< share set 7 */ -}; - -/*! @brief SYSCTL flexcomm signal */ -typedef enum _sysctl_sharedctrlset_signal -{ - kSYSCTL_SharedCtrlSignalSCK = SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT, /*!< SCK signal */ - kSYSCTL_SharedCtrlSignalWS = SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT, /*!< WS signal */ - kSYSCTL_SharedCtrlSignalDataIn = SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT, /*!< Data in signal */ - kSYSCTL_SharedCtrlSignalDataOut = SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT, /*!< Data out signal */ -} sysctl_sharedctrlset_signal_t; -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief SYSCTL initial - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Init(SYSCTL_Type *base); - -/*! - * @brief SYSCTL deinit - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Deinit(SYSCTL_Type *base); - -/* @} */ - -/*! - * @name SYSCTL share signal configure - * @{ - */ - -/*! - * @brief SYSCTL share set configure for flexcomm - * - * @param base Base address of the SYSCTL peripheral. - * @param flexCommIndex index of flexcomm, reference _sysctl_share_src - * @param sckSet share set for sck,reference _sysctl_share_set_index - * @param wsSet share set for ws, reference _sysctl_share_set_index - * @param dataInSet share set for data in, reference _sysctl_share_set_index - * @param dataOutSet share set for data out, reference _sysctl_dataout_mask - * - */ -void SYSCTL_SetFlexcommShareSet(SYSCTL_Type *base, - uint32_t flexCommIndex, - uint32_t sckSet, - uint32_t wsSet, - uint32_t dataInSet, - uint32_t dataOutSet); - -/*! - * @brief SYSCTL share set configure for separate signal - * - * @param base Base address of the SYSCTL peripheral - * @param flexCommIndex index of flexcomm,reference _sysctl_share_src - * @param signal FCCTRLSEL signal shift - * @param set share set for sck, reference _sysctl_share_set_index - * - */ -void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set); - -/*! - * @brief SYSCTL share set source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param sckShareSrc sck source for this share set,reference _sysctl_share_src - * @param wsShareSrc ws source for this share set,reference _sysctl_share_src - * @param dataInShareSrc data in source for this share set,reference _sysctl_share_src - * @param dataOutShareSrc data out source for this share set,reference _sysctl_dataout_mask - * - */ -void SYSCTL_SetShareSetSrc(SYSCTL_Type *base, - uint32_t setIndex, - uint32_t sckShareSrc, - uint32_t wsShareSrc, - uint32_t dataInShareSrc, - uint32_t dataOutShareSrc); - -/*! - * @brief SYSCTL sck source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param signal FCCTRLSEL signal shift - * @param shareSrc sck source fro this share set,reference _sysctl_share_src - * - */ -void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base, - uint32_t setIndex, - sysctl_sharedctrlset_signal_t signal, - uint32_t shareSrc); - -/* @} */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_SYSCTL_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart.c deleted file mode 100644 index 1bbf2358772..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart.c +++ /dev/null @@ -1,1160 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_usart.h" -#include "fsl_device_registers.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart" -#endif - -/*! - * @brief Used for conversion from `flexcomm_usart_irq_handler_t` to `flexcomm_irq_handler_t` - */ -typedef union usart_to_flexcomm -{ - flexcomm_usart_irq_handler_t usart_master_handler; - flexcomm_irq_handler_t flexcomm_handler; -} usart_to_flexcomm_t; - -enum -{ - kUSART_TxIdle, /* TX idle. */ - kUSART_TxBusy, /* TX busy. */ - kUSART_RxIdle, /* RX idle. */ - kUSART_RxBusy /* RX busy. */ -}; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief IRQ name array */ -static const IRQn_Type s_usartIRQ[] = USART_IRQS; - -/*! @brief Array to map USART instance number to base address. */ -static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Get the index corresponding to the USART */ -/*! brief Returns instance number for USART peripheral base address. */ -uint32_t USART_GetInstance(USART_Type *base) -{ - uint32_t i; - - for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT; i++) - { - if ((uint32_t)base == s_usartBaseAddrs[i]) - { - break; - } - } - - assert(i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT); - return i; -} - -/*! - * brief Get the length of received data in RX ring buffer. - * - * param handle USART handle pointer. - * return Length of received data in RX ring buffer. - */ -size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) -{ - size_t size; - - /* Check arguments */ - assert(NULL != handle); - uint16_t rxRingBufferHead = handle->rxRingBufferHead; - uint16_t rxRingBufferTail = handle->rxRingBufferTail; - - if (rxRingBufferTail > rxRingBufferHead) - { - size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail; - } - else - { - size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail; - } - return size; -} - -static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle) -{ - bool full; - - /* Check arguments */ - assert(NULL != handle); - - if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) - { - full = true; - } - else - { - full = false; - } - return full; -} - -/*! - * brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific USART handle. - * - * When the RX ring buffer is used, data received are stored into the ring buffer even when the - * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * - * note When using the RX ring buffer, one byte is reserved for internal use. In other - * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. - * param ringBufferSize size of the ring buffer. - */ -void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) -{ - /* Check arguments */ - assert(NULL != base); - assert(NULL != handle); - assert(NULL != ringBuffer); - - /* Setup the ringbuffer address */ - handle->rxRingBuffer = ringBuffer; - handle->rxRingBufferSize = ringBufferSize; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; - /* ring buffer is ready we can start receiving data */ - base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -} - -/*! - * brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) -{ - /* Check arguments */ - assert(NULL != base); - assert(NULL != handle); - - if (handle->rxState == (uint8_t)kUSART_RxIdle) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK; - } - handle->rxRingBuffer = NULL; - handle->rxRingBufferSize = 0U; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; -} - -/*! - * brief Initializes a USART instance with user configuration structure and peripheral clock. - * - * This function configures the USART module with the user-defined settings. The user can configure the configuration - * structure and also get the default configuration by using the USART_GetDefaultConfig() function. - * Example below shows how to use this API to configure USART. - * code - * usart_config_t usartConfig; - * usartConfig.baudRate_Bps = 115200U; - * usartConfig.parityMode = kUSART_ParityDisabled; - * usartConfig.stopBitCount = kUSART_OneStopBit; - * USART_Init(USART1, &usartConfig, 20000000U); - * endcode - * - * param base USART peripheral base address. - * param config Pointer to user-defined configuration structure. - * param srcClock_Hz USART clock source frequency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_InvalidArgument USART base address is not valid - * retval kStatus_Success Status USART initialize succeed - */ -status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz) -{ - int result; - - /* check arguments */ - assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); - if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* initialize flexcomm to USART mode */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART); - if (kStatus_Success != result) - { - return result; - } - - if (config->enableTx) - { - /* empty and enable txFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK; - /* setup trigger level */ - base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK); - base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark); - /* enable trigger interrupt */ - base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK; - } - - /* empty and enable rxFIFO */ - if (config->enableRx) - { - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK; - /* setup trigger level */ - base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK); - base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable trigger interrupt */ - base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK; - } - /* setup configuration and enable USART */ - base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | - USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | - USART_CFG_SYNCEN((uint32_t)config->syncMode >> 1) | USART_CFG_SYNCMST((uint8_t)config->syncMode) | - USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_MODE32K(config->enableMode32k) | - USART_CFG_CTSEN(config->enableHardwareFlowControl) | USART_CFG_ENABLE_MASK; - - /* Setup baudrate */ - if (config->enableMode32k) - { - if ((9600U % config->baudRate_Bps) == 0U) - { - base->BRG = 9600U / config->baudRate_Bps; - } - else - { - return kStatus_USART_BaudrateNotSupport; - } - } - else - { - result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - } - /* Setting continuous Clock configuration. used for synchronous mode. */ - USART_EnableContinuousSCLK(base, config->enableContinuousSCLK); - - return kStatus_Success; -} - -/*! - * brief Deinitializes a USART instance. - * - * This function waits for TX complete, disables TX and RX, and disables the USART clock. - * - * param base USART peripheral base address. - */ -void USART_Deinit(USART_Type *base) -{ - /* Check arguments */ - assert(NULL != base); - while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) - { - } - /* Disable interrupts, disable dma requests, disable peripheral */ - base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK | - USART_FIFOINTENCLR_RXLVL_MASK; - base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK); - base->CFG &= ~(USART_CFG_ENABLE_MASK); -} - -/*! - * brief Gets the default configuration structure. - * - * This function initializes the USART configuration structure to a default value. The default - * values are: - * usartConfig->baudRate_Bps = 115200U; - * usartConfig->parityMode = kUSART_ParityDisabled; - * usartConfig->stopBitCount = kUSART_OneStopBit; - * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; - * usartConfig->loopback = false; - * usartConfig->enableTx = false; - * usartConfig->enableRx = false; - * - * param config Pointer to configuration structure. - */ -void USART_GetDefaultConfig(usart_config_t *config) -{ - /* Check arguments */ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* Set always all members ! */ - config->baudRate_Bps = 115200U; - config->parityMode = kUSART_ParityDisabled; - config->stopBitCount = kUSART_OneStopBit; - config->bitCountPerChar = kUSART_8BitsPerChar; - config->loopback = false; - config->enableRx = false; - config->enableTx = false; - config->enableMode32k = false; - config->txWatermark = kUSART_TxFifo0; - config->rxWatermark = kUSART_RxFifo1; - config->syncMode = kUSART_SyncModeDisabled; - config->enableContinuousSCLK = false; - config->clockPolarity = kUSART_RxSampleOnFallingEdge; - config->enableHardwareFlowControl = false; -} - -/*! - * brief Sets the USART instance baud rate. - * - * This function configures the USART module baud rate. This function is used to update - * the USART module baud rate after the USART module is initialized by the USART_Init. - * code - * USART_SetBaudRate(USART1, 115200U, 20000000U); - * endcode - * - * param base USART peripheral base address. - * param baudrate_Bps USART baudrate to be set. - * param srcClock_Hz USART clock source frequency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_Success Set baudrate succeed. - * retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) -{ - uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1; - uint32_t osrval, brgval, diff, baudrate; - - /* check arguments */ - assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))); - if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* If synchronous master mode is enabled, only configure the BRG value. */ - if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U) - { - if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U) - { - brgval = srcClock_Hz / baudrate_Bps; - base->BRG = brgval - 1U; - } - } - else - { - /* - * Smaller values of OSR can make the sampling position within a data bit less accurate and may - * potentially cause more noise errors or incorrect data. - */ - for (osrval = best_osrval; osrval >= 8U; osrval--) - { - brgval = (((srcClock_Hz * 10U) / ((osrval + 1U) * baudrate_Bps)) - 5U) / 10U; - if (brgval > 0xFFFFU) - { - continue; - } - baudrate = srcClock_Hz / ((osrval + 1U) * (brgval + 1U)); - diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); - if (diff < best_diff) - { - best_diff = diff; - best_osrval = osrval; - best_brgval = brgval; - } - } - - /* Check to see if actual baud rate is within 3% of desired baud rate - * based on the best calculated OSR and BRG value */ - baudrate = srcClock_Hz / ((best_osrval + 1U) * (best_brgval + 1U)); - diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); - if (diff > ((baudrate_Bps / 100U) * 3U)) - { - return kStatus_USART_BaudrateNotSupport; - } - - /* value over range */ - if (best_brgval > 0xFFFFU) - { - return kStatus_USART_BaudrateNotSupport; - } - - base->OSR = best_osrval; - base->BRG = best_brgval; - } - - return kStatus_Success; -} - -/*! - * brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source. - * - * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator - * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting - * SYSCON_RTCOSCCTRL_EN bit to 1. - * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that - * 9600 can evenly divide, eg: 4800, 3200. - * - * param base USART peripheral base address. - * param baudRate_Bps USART baudrate to be set.. - * param enableMode32k true is 32k mode, false is normal mode. - * param srcClock_Hz USART clock source frequency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_Success Set baudrate succeed. - * retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz) -{ - status_t result = kStatus_Success; - base->CFG &= ~(USART_CFG_ENABLE_MASK); - if (enableMode32k) - { - base->CFG |= USART_CFG_MODE32K_MASK; - if ((9600U % baudRate_Bps) == 0U) - { - base->BRG = 9600U / baudRate_Bps - 1U; - } - else - { - return kStatus_USART_BaudrateNotSupport; - } - } - else - { - base->CFG &= ~(USART_CFG_MODE32K_MASK); - result = USART_SetBaudRate(base, baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - } - base->CFG |= USART_CFG_ENABLE_MASK; - return result; -} - -/*! - * brief Enable 9-bit data mode for USART. - * - * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user. - * - * param base USART peripheral base address. - * param enable true to enable, false to disable. - */ -void USART_Enable9bitMode(USART_Type *base, bool enable) -{ - assert(base != NULL); - - uint32_t temp = 0U; - - if (enable) - { - /* Set USART 9-bit mode, disable parity. */ - temp = base->CFG & ~((uint32_t)USART_CFG_DATALEN_MASK | (uint32_t)USART_CFG_PARITYSEL_MASK); - temp |= (uint32_t)USART_CFG_DATALEN(0x2U); - base->CFG = temp; - } - else - { - /* Set USART to 8-bit mode. */ - base->CFG &= ~((uint32_t)USART_CFG_DATALEN_MASK); - base->CFG |= (uint32_t)USART_CFG_DATALEN(0x1U); - } -} - -/*! - * brief Transmit an address frame in 9-bit data mode. - * - * param base USART peripheral base address. - * param address USART slave address. - */ -void USART_SendAddress(USART_Type *base, uint8_t address) -{ - assert(base != NULL); - base->FIFOWR = ((uint32_t)address | 0x100UL); -} - -/*! - * brief Writes to the TX register using a blocking method. - * - * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO - * to have room and writes data to the TX buffer. - * - * param base USART peripheral base address. - * param data Start address of the data to write. - * param length Size of the data to write. - * retval kStatus_USART_Timeout Transmission timed out and was aborted. - * retval kStatus_InvalidArgument Invalid argument. - * retval kStatus_Success Successfully wrote all data. - */ -status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) -{ - /* Check arguments */ - assert(!((NULL == base) || (NULL == data))); -#if UART_RETRY_TIMES - uint32_t waitTimes; -#endif - if ((NULL == base) || (NULL == data)) - { - return kStatus_InvalidArgument; - } - /* Check whether txFIFO is enabled */ - if (0U == (base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK)) - { - return kStatus_InvalidArgument; - } - for (; length > 0U; length--) - { - /* Loop until txFIFO get some space for new data */ -#if UART_RETRY_TIMES - waitTimes = UART_RETRY_TIMES; - while ((0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) && (--waitTimes != 0U)) -#else - while (0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) -#endif - { - } -#if UART_RETRY_TIMES - if (0U == waitTimes) - { - return kStatus_USART_Timeout; - } -#endif - base->FIFOWR = *data; - data++; - } - /* Wait to finish transfer */ -#if UART_RETRY_TIMES - waitTimes = UART_RETRY_TIMES; - while ((0U == (base->STAT & USART_STAT_TXIDLE_MASK)) && (--waitTimes != 0U)) -#else - while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) -#endif - { - } -#if UART_RETRY_TIMES - if (0U == waitTimes) - { - return kStatus_USART_Timeout; - } -#endif - return kStatus_Success; -} - -/*! - * brief Read RX data register using a blocking method. - * - * This function polls the RX register, waits for the RX register to be full or for RX FIFO to - * have data and read data from the TX register. - * - * param base USART peripheral base address. - * param data Start address of the buffer to store the received data. - * param length Size of the buffer. - * retval kStatus_USART_FramingError Receiver overrun happened while receiving data. - * retval kStatus_USART_ParityError Noise error happened while receiving data. - * retval kStatus_USART_NoiseError Framing error happened while receiving data. - * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. - * retval kStatus_USART_Timeout Transmission timed out and was aborted. - * retval kStatus_Success Successfully received all data. - */ -status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) -{ - uint32_t statusFlag; - status_t status = kStatus_Success; -#if UART_RETRY_TIMES - uint32_t waitTimes; -#endif - - /* check arguments */ - assert(!((NULL == base) || (NULL == data))); - if ((NULL == base) || (NULL == data)) - { - return kStatus_InvalidArgument; - } - - /* Check whether rxFIFO is enabled */ - if ((base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK) == 0U) - { - return kStatus_Fail; - } - for (; length > 0U; length--) - { - /* loop until rxFIFO have some data to read */ -#if UART_RETRY_TIMES - waitTimes = UART_RETRY_TIMES; - while (((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) && (--waitTimes != 0U)) -#else - while ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) -#endif - { - } -#if UART_RETRY_TIMES - if (waitTimes == 0U) - { - status = kStatus_USART_Timeout; - break; - } -#endif - /* check rxFIFO statusFlag */ - if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) - { - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; - status = kStatus_USART_RxError; - break; - } - /* check receive statusFlag */ - statusFlag = base->STAT; - /* Clear all status flags */ - base->STAT |= statusFlag; - if ((statusFlag & USART_STAT_PARITYERRINT_MASK) != 0U) - { - status = kStatus_USART_ParityError; - } - if ((statusFlag & USART_STAT_FRAMERRINT_MASK) != 0U) - { - status = kStatus_USART_FramingError; - } - if ((statusFlag & USART_STAT_RXNOISEINT_MASK) != 0U) - { - status = kStatus_USART_NoiseError; - } - - if (kStatus_Success == status) - { - *data = (uint8_t)base->FIFORD; - data++; - } - else - { - break; - } - } - return status; -} - -/*! - * brief Initializes the USART handle. - * - * This function initializes the USART handle which can be used for other USART - * transactional APIs. Usually, for a specified USART instance, - * call this API once to get the initialized handle. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param callback The callback function. - * param userData The parameter of the callback function. - */ -status_t USART_TransferCreateHandle(USART_Type *base, - usart_handle_t *handle, - usart_transfer_callback_t callback, - void *userData) -{ - /* Check 'base' */ - assert(!((NULL == base) || (NULL == handle))); - - uint32_t instance = 0; - usart_to_flexcomm_t handler; - handler.usart_master_handler = USART_TransferHandleIRQ; - - if ((NULL == base) || (NULL == handle)) - { - return kStatus_InvalidArgument; - } - - instance = USART_GetInstance(base); - - (void)memset(handle, 0, sizeof(*handle)); - /* Set the TX/RX state. */ - handle->rxState = (uint8_t)kUSART_RxIdle; - handle->txState = (uint8_t)kUSART_TxIdle; - /* Set the callback and user data. */ - handle->callback = callback; - handle->userData = userData; - handle->rxWatermark = (uint8_t)USART_FIFOTRIG_RXLVL_GET(base); - handle->txWatermark = (uint8_t)USART_FIFOTRIG_TXLVL_GET(base); - - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - - /* Enable interrupt in NVIC. */ - (void)EnableIRQ(s_usartIRQ[instance]); - - return kStatus_Success; -} - -/*! - * brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in the IRQ handler, the USART driver calls the callback - * function and passes the ref kStatus_USART_TxIdle as status parameter. - * - * note The kStatus_USART_TxIdle is passed to the upper layer when all data is written - * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, - * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART transfer structure. See #usart_transfer_t. - * retval kStatus_Success Successfully start the data transmission. - * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer) -{ - /* Check arguments */ - assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - /* Check xfer members */ - assert(!((0U == xfer->dataSize) || (NULL == xfer->txData))); - if ((0U == xfer->dataSize) || (NULL == xfer->txData)) - { - return kStatus_InvalidArgument; - } - - /* Return error if current TX busy. */ - if ((uint8_t)kUSART_TxBusy == handle->txState) - { - return kStatus_USART_TxBusy; - } - else - { - /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up the - * handle value. */ - uint32_t interruptMask = USART_GetEnabledInterrupts(base); - USART_DisableInterrupts(base, interruptMask); - handle->txData = xfer->txData; - handle->txDataSize = xfer->dataSize; - handle->txDataSizeAll = xfer->dataSize; - handle->txState = (uint8_t)kUSART_TxBusy; - /* Enable transmiter interrupt and the previously disabled interrupt. */ - USART_EnableInterrupts(base, interruptMask | (uint32_t)kUSART_TxLevelInterruptEnable); - } - return kStatus_Success; -} - -/*! - * brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out - * how many bytes are still not sent out. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) -{ - assert(NULL != handle); - - /* Disable interrupts */ - USART_DisableInterrupts(base, (uint32_t)kUSART_TxLevelInterruptEnable); - /* Empty txFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK; - - handle->txDataSize = 0U; - handle->txState = (uint8_t)kUSART_TxIdle; -} - -/*! - * brief Get the number of bytes that have been sent out to bus. - * - * This function gets the number of bytes that have been sent out to bus by interrupt method. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Send bytes count. - * retval kStatus_NoTransferInProgress No send in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != count); - - if ((uint8_t)kUSART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - handle->txDataSize - - ((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); - - return kStatus_Success; -} - -/*! - * brief Receives a buffer of data using an interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function, which - * returns without waiting for all data to be received. - * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and - * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in the ring buffer is not enough to read, the receive - * request is saved by the USART driver. When the new data arrives, the receive request - * is serviced first. When all data is received, the USART driver notifies the upper layer - * through a callback function and passes the status parameter ref kStatus_USART_RxIdle. - * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. - * The 5 bytes are copied to the xfer->data and this function returns with the - * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is - * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to the xfer->data. When all data is received, the upper layer is notified. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART transfer structure, see #usart_transfer_t. - * param receivedBytes Bytes received from the ring buffer directly. - * retval kStatus_Success Successfully queue the transfer into transmit queue. - * retval kStatus_USART_RxBusy Previous receive request is not finished. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveNonBlocking(USART_Type *base, - usart_handle_t *handle, - usart_transfer_t *xfer, - size_t *receivedBytes) -{ - uint32_t i; - /* How many bytes to copy from ring buffer to user memory. */ - size_t bytesToCopy = 0U; - /* How many bytes to receive. */ - size_t bytesToReceive; - /* How many bytes currently have received. */ - size_t bytesCurrentReceived; - uint32_t interruptMask = 0U; - - /* Check arguments */ - assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - /* Check xfer members */ - assert(!((0U == xfer->dataSize) || (NULL == xfer->rxData))); - if ((0U == xfer->dataSize) || (NULL == xfer->rxData)) - { - return kStatus_InvalidArgument; - } - - /* Enable address detect when address match is enabled. */ - if ((base->CFG & (uint32_t)USART_CFG_AUTOADDR_MASK) != 0U) - { - base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK; - } - - /* How to get data: - 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize - to uart handle, enable interrupt to store received data to xfer->data. When - all data received, trigger callback. - 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. - If there are enough data in ring buffer, copy them to xfer->data and return. - If there are not enough data in ring buffer, copy all of them to xfer->data, - save the xfer->data remained empty space to uart handle, receive data - to this empty space and trigger callback when finished. */ - if ((uint8_t)kUSART_RxBusy == handle->rxState) - { - return kStatus_USART_RxBusy; - } - else - { - bytesToReceive = xfer->dataSize; - bytesCurrentReceived = 0U; - /* If RX ring buffer is used. */ - if (handle->rxRingBuffer != NULL) - { - /* Disable IRQ, protect ring buffer. */ - interruptMask = USART_GetEnabledInterrupts(base); - USART_DisableInterrupts(base, interruptMask); - - /* How many bytes in RX ring buffer currently. */ - bytesToCopy = USART_TransferGetRxRingBufferLength(handle); - if (bytesToCopy != 0U) - { - bytesToCopy = MIN(bytesToReceive, bytesToCopy); - bytesToReceive -= bytesToCopy; - /* Copy data from ring buffer to user memory. */ - for (i = 0U; i < bytesToCopy; i++) - { - xfer->rxData[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; - /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ - if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - } - /* If ring buffer does not have enough data, still need to read more data. */ - if (bytesToReceive != 0U) - { - /* No data in ring buffer, save the request to UART handle. */ - handle->rxData = xfer->rxData + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = xfer->dataSize; - handle->rxState = (uint8_t)kUSART_RxBusy; - } - /* Re-enable IRQ. */ - USART_EnableInterrupts(base, interruptMask); - /* Call user callback since all data are received. */ - if (0U == bytesToReceive) - { - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); - } - } - } - /* Ring buffer not used. */ - else - { - /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up - * the handle value. */ - interruptMask = USART_GetEnabledInterrupts(base); - USART_DisableInterrupts(base, interruptMask); - handle->rxData = xfer->rxData + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = (uint8_t)kUSART_RxBusy; - - /* Enable RX interrupt. */ - base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK; - /* Re-enable IRQ. */ - USART_EnableInterrupts(base, interruptMask); - } - /* Return the how many bytes have read. */ - if (receivedBytes != NULL) - { - *receivedBytes = bytesCurrentReceived; - } - } - return kStatus_Success; -} - -/*! - * brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out - * how many bytes not received yet. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) -{ - assert(NULL != handle); - - /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ - if (NULL == handle->rxRingBuffer) - { - /* Disable interrupts */ - USART_DisableInterrupts(base, (uint32_t)kUSART_RxLevelInterruptEnable); - /* Empty rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - } - - handle->rxDataSize = 0U; - handle->rxState = (uint8_t)kUSART_RxIdle; -} - -/*! - * brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Receive bytes count. - * retval kStatus_NoTransferInProgress No receive in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != count); - - if ((uint8_t)kUSART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - handle->rxDataSize; - - return kStatus_Success; -} - -/*! - * brief USART IRQ handle function. - * - * This function handles the USART transmit and receive IRQ request. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) -{ - /* Check arguments */ - assert((NULL != base) && (NULL != handle)); - - bool receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); - bool sendEnabled = (handle->txDataSize != 0U); - uint8_t rxdata; - size_t tmpsize; - - /* If RX overrun. */ - if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) - { - /* Clear rx error state. */ - base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxError, handle->userData); - } - } - while ((receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) || - (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U))) - { - /* Receive data */ - if (receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) - { - /* Clear address detect when RXFIFO has data. */ - base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK; - /* Receive to app bufffer if app buffer is present */ - if (handle->rxDataSize != 0U) - { - rxdata = (uint8_t)base->FIFORD; - *handle->rxData = rxdata; - handle->rxDataSize--; - handle->rxData++; - receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); - if (0U == handle->rxDataSize) - { - if (NULL == handle->rxRingBuffer) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; - } - handle->rxState = (uint8_t)kUSART_RxIdle; - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); - } - } - } - /* Otherwise receive to ring buffer if ring buffer is present */ - else - { - if (handle->rxRingBuffer != NULL) - { - /* If RX ring buffer is full, trigger callback to notify over run. */ - if (USART_TransferIsRxRingBufferFull(handle)) - { - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData); - } - } - /* If ring buffer is still full after callback function, the oldest data is overridden. */ - if (USART_TransferIsRxRingBufferFull(handle)) - { - /* Increase handle->rxRingBufferTail to make room for new data. */ - if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - /* Read data. */ - rxdata = (uint8_t)base->FIFORD; - handle->rxRingBuffer[handle->rxRingBufferHead] = rxdata; - /* Increase handle->rxRingBufferHead. */ - if ((size_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferHead = 0U; - } - else - { - handle->rxRingBufferHead++; - } - } - } - } - /* Send data */ - if (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U)) - { - base->FIFOWR = *handle->txData; - handle->txDataSize--; - handle->txData++; - sendEnabled = handle->txDataSize != 0U; - if (!sendEnabled) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK; - - base->INTENSET = USART_INTENSET_TXIDLEEN_MASK; - } - } - } - - /* Tx idle and the interrupt is enabled. */ - if ((0U != (base->INTENSET & USART_INTENSET_TXIDLEEN_MASK)) && (0U != (base->INTSTAT & USART_INTSTAT_TXIDLE_MASK))) - { - /* Set txState to idle only when all data has been sent out to bus. */ - handle->txState = (uint8_t)kUSART_TxIdle; - /* Disable tx idle interrupt */ - base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK; - - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); - } - } - - /* ring buffer is not used */ - if (NULL == handle->rxRingBuffer) - { - tmpsize = handle->rxDataSize; - - /* restore if rx transfer ends and rxLevel is different from default value */ - if ((tmpsize == 0U) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark)) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark); - } - /* decrease level if rx transfer is bellow */ - if ((tmpsize != 0U) && (tmpsize < (USART_FIFOTRIG_RXLVL_GET(base) + 1U))) - { - base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(tmpsize - 1U)); - } - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart.h deleted file mode 100644 index 68467e7e209..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart.h +++ /dev/null @@ -1,866 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_USART_H_ -#define _FSL_USART_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup usart_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief USART driver version. */ -#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 5, 1)) -/*@}*/ - -#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT) -#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT) - -/*! @brief Retry times for waiting flag. */ -#ifndef UART_RETRY_TIMES -#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */ -#endif - -/*! @brief Error codes for the USART driver. */ -enum -{ - kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */ - kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */ - kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */ - kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */ - kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */ - kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */ - kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */ - kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */ - kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */ - kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */ - kStatus_USART_BaudrateNotSupport = - MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */ - kStatus_USART_Timeout = MAKE_STATUS(kStatusGroup_LPC_USART, 14), /*!< USART time out. */ -}; - -/*! @brief USART synchronous mode. */ -typedef enum _usart_sync_mode -{ - kUSART_SyncModeDisabled = 0x0U, /*!< Asynchronous mode. */ - kUSART_SyncModeSlave = 0x2U, /*!< Synchronous slave mode. */ - kUSART_SyncModeMaster = 0x3U, /*!< Synchronous master mode. */ -} usart_sync_mode_t; - -/*! @brief USART parity mode. */ -typedef enum _usart_parity_mode -{ - kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */ - kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ - kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ -} usart_parity_mode_t; - -/*! @brief USART stop bit count. */ -typedef enum _usart_stop_bit_count -{ - kUSART_OneStopBit = 0U, /*!< One stop bit */ - kUSART_TwoStopBit = 1U, /*!< Two stop bits */ -} usart_stop_bit_count_t; - -/*! @brief USART data size. */ -typedef enum _usart_data_len -{ - kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */ - kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */ -} usart_data_len_t; - -/*! @brief USART clock polarity configuration, used in sync mode.*/ -typedef enum _usart_clock_polarity -{ - kUSART_RxSampleOnFallingEdge = 0x0U, /*!< Un_RXD is sampled on the falling edge of SCLK. */ - kUSART_RxSampleOnRisingEdge = 0x1U, /*!< Un_RXD is sampled on the rising edge of SCLK. */ -} usart_clock_polarity_t; - -/*! @brief txFIFO watermark values */ -typedef enum _usart_txfifo_watermark -{ - kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */ - kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */ - kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */ - kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */ - kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */ - kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */ - kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */ - kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */ -} usart_txfifo_watermark_t; - -/*! @brief rxFIFO watermark values */ -typedef enum _usart_rxfifo_watermark -{ - kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */ - kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */ - kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */ - kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */ - kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */ - kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */ - kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */ - kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */ -} usart_rxfifo_watermark_t; - -/*! - * @brief USART interrupt configuration structure, default settings all disabled. - */ -enum _usart_interrupt_enable -{ - kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK), - kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK), - kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK), - kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK), -}; - -/*! - * @brief USART status flags. - * - * This provides constants for the USART status flags for use in the USART functions. - */ -enum _usart_flags -{ - kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */ - kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */ - kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */ - kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */ - kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */ - kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */ -}; - -/*! @brief USART configuration structure. */ -typedef struct _usart_config -{ - uint32_t baudRate_Bps; /*!< USART baud rate */ - usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ - usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ - usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */ - bool loopback; /*!< Enable peripheral loopback */ - bool enableRx; /*!< Enable RX */ - bool enableTx; /*!< Enable TX */ - bool enableContinuousSCLK; /*!< USART continuous Clock generation enable in synchronous master mode. */ - bool enableMode32k; /*!< USART uses 32 kHz clock from the RTC oscillator as the clock source. */ - bool enableHardwareFlowControl; /*!< Enable hardware control RTS/CTS */ - usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ - usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */ - usart_clock_polarity_t clockPolarity; /*!< Selects the clock polarity and sampling edge in synchronous mode. */ -} usart_config_t; - -/*! @brief USART transfer structure. */ -typedef struct _usart_transfer -{ - /* - * Use separate TX and RX data pointer, because TX data is const data. - * The member data is kept for backward compatibility. - */ - union - { - uint8_t *data; /*!< The buffer of data to be transfer.*/ - uint8_t *rxData; /*!< The buffer to receive data. */ - const uint8_t *txData; /*!< The buffer of data to be sent. */ - }; - size_t dataSize; /*!< The byte count to be transfer. */ -} usart_transfer_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _usart_handle usart_handle_t; - -/*! @brief USART transfer callback function. */ -typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData); - -/*! @brief USART handle structure. */ -struct _usart_handle -{ - const uint8_t *volatile txData; /*!< Address of remaining data to send. */ - volatile size_t txDataSize; /*!< Size of the remaining data to send. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ - volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - - uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ - size_t rxRingBufferSize; /*!< Size of the ring buffer. */ - volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ - volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ - - usart_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< USART callback function parameter.*/ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ - - uint8_t txWatermark; /*!< txFIFO watermark */ - uint8_t rxWatermark; /*!< rxFIFO watermark */ -}; - -/*! @brief Typedef for usart interrupt handler. */ -typedef void (*flexcomm_usart_irq_handler_t)(USART_Type *base, usart_handle_t *handle); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! @brief Returns instance number for USART peripheral base address. */ -uint32_t USART_GetInstance(USART_Type *base); - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes a USART instance with user configuration structure and peripheral clock. - * - * This function configures the USART module with the user-defined settings. The user can configure the configuration - * structure and also get the default configuration by using the USART_GetDefaultConfig() function. - * Example below shows how to use this API to configure USART. - * @code - * usart_config_t usartConfig; - * usartConfig.baudRate_Bps = 115200U; - * usartConfig.parityMode = kUSART_ParityDisabled; - * usartConfig.stopBitCount = kUSART_OneStopBit; - * USART_Init(USART1, &usartConfig, 20000000U); - * @endcode - * - * @param base USART peripheral base address. - * @param config Pointer to user-defined configuration structure. - * @param srcClock_Hz USART clock source frequency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_InvalidArgument USART base address is not valid - * @retval kStatus_Success Status USART initialize succeed - */ -status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes a USART instance. - * - * This function waits for TX complete, disables TX and RX, and disables the USART clock. - * - * @param base USART peripheral base address. - */ -void USART_Deinit(USART_Type *base); - -/*! - * @brief Gets the default configuration structure. - * - * This function initializes the USART configuration structure to a default value. The default - * values are: - * usartConfig->baudRate_Bps = 115200U; - * usartConfig->parityMode = kUSART_ParityDisabled; - * usartConfig->stopBitCount = kUSART_OneStopBit; - * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; - * usartConfig->loopback = false; - * usartConfig->enableTx = false; - * usartConfig->enableRx = false; - * - * @param config Pointer to configuration structure. - */ -void USART_GetDefaultConfig(usart_config_t *config); - -/*! - * @brief Sets the USART instance baud rate. - * - * This function configures the USART module baud rate. This function is used to update - * the USART module baud rate after the USART module is initialized by the USART_Init. - * @code - * USART_SetBaudRate(USART1, 115200U, 20000000U); - * @endcode - * - * @param base USART peripheral base address. - * @param baudrate_Bps USART baudrate to be set. - * @param srcClock_Hz USART clock source frequency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_Success Set baudrate succeed. - * @retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source - * - * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator - * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting - * SYSCON_RTCOSCCTRL_EN bit to 1. - * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that - * 9600 can evenly divide, eg: 4800, 3200. - * - * @param base USART peripheral base address. - * @param baudRate_Bps USART baudrate to be set.. - * @param enableMode32k true is 32k mode, false is normal mode. - * @param srcClock_Hz USART clock source frequency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_Success Set baudrate succeed. - * @retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz); - -/*! - * @brief Enable 9-bit data mode for USART. - * - * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user. - * - * @param base USART peripheral base address. - * @param enable true to enable, false to disable. - */ -void USART_Enable9bitMode(USART_Type *base, bool enable); - -/*! - * @brief Set the USART slave address. - * - * This function configures the address for USART module that works as slave in 9-bit data mode. When the address - * detection is enabled, the frame it receices with MSB being 1 is considered as an address frame, otherwise it is - * considered as data frame. Once the address frame matches slave's own addresses, this slave is addressed. This - * address frame and its following data frames are stored in the receive buffer, otherwise the frames will be discarded. - * To un-address a slave, just send an address frame with unmatched address. - * - * @note Any USART instance joined in the multi-slave system can work as slave. The position of the address mark is the - * same as the parity bit when parity is enabled for 8 bit and 9 bit data formats. - * - * @param base USART peripheral base address. - * @param address USART slave address. - */ -static inline void USART_SetMatchAddress(USART_Type *base, uint8_t address) -{ - /* Configure match address. */ - base->ADDR = (uint32_t)address; -} - -/*! - * @brief Enable the USART match address feature. - * - * @param base USART peripheral base address. - * @param match true to enable match address, false to disable. - */ -static inline void USART_EnableMatchAddress(USART_Type *base, bool match) -{ - /* Configure match address enable bit. */ - if (match) - { - base->CFG |= (uint32_t)USART_CFG_AUTOADDR_MASK; - base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK; - } - else - { - base->CFG &= ~(uint32_t)USART_CFG_AUTOADDR_MASK; - base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK; - } -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Get USART status flags. - * - * This function get all USART status flags, the flags are returned as the logical - * OR value of the enumerators @ref _usart_flags. To check a specific status, - * compare the return value with enumerators in @ref _usart_flags. - * For example, to check whether the TX is empty: - * @code - * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1)) - * { - * ... - * } - * @endcode - * - * @param base USART peripheral base address. - * @return USART status flags which are ORed by the enumerators in the _usart_flags. - */ -static inline uint32_t USART_GetStatusFlags(USART_Type *base) -{ - return base->FIFOSTAT; -} - -/*! - * @brief Clear USART status flags. - * - * This function clear supported USART status flags - * Flags that can be cleared or set are: - * kUSART_TxError - * kUSART_RxError - * For example: - * @code - * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError) - * @endcode - * - * @param base USART peripheral base address. - * @param mask status flags to be cleared. - */ -static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask) -{ - /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */ - base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK); -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables USART interrupts according to the provided mask. - * - * This function enables the USART interrupts according to the provided mask. The mask - * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. - * For example, to enable TX empty interrupt and RX full interrupt: - * @code - * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); - * @endcode - * - * @param base USART peripheral base address. - * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable. - */ -static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) -{ - base->FIFOINTENSET = mask & 0xFUL; -} - -/*! - * @brief Disables USART interrupts according to a provided mask. - * - * This function disables the USART interrupts according to a provided mask. The mask - * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. - * This example shows how to disable the TX empty interrupt and RX full interrupt: - * @code - * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); - * @endcode - * - * @param base USART peripheral base address. - * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable. - */ -static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) -{ - base->FIFOINTENCLR = mask & 0xFUL; -} - -/*! - * @brief Returns enabled USART interrupts. - * - * This function returns the enabled USART interrupts. - * - * @param base USART peripheral base address. - */ -static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base) -{ - return base->FIFOINTENSET; -} - -/*! - * @brief Enable DMA for Tx - */ -static inline void USART_EnableTxDMA(USART_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK); - } -} - -/*! - * @brief Enable DMA for Rx - */ -static inline void USART_EnableRxDMA(USART_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK); - } -} - -/*! - * @brief Enable CTS. - * This function will determine whether CTS is used for flow control. - * - * @param base USART peripheral base address. - * @param enable Enable CTS or not, true for enable and false for disable. - */ -static inline void USART_EnableCTS(USART_Type *base, bool enable) -{ - if (enable) - { - base->CFG |= USART_CFG_CTSEN_MASK; - } - else - { - base->CFG &= ~USART_CFG_CTSEN_MASK; - } -} - -/*! - * @brief Continuous Clock generation. - * By default, SCLK is only output while data is being transmitted in synchronous mode. - * Enable this funciton, SCLK will run continuously in synchronous mode, allowing - * characters to be received on Un_RxD independently from transmission on Un_TXD). - * - * @param base USART peripheral base address. - * @param enable Enable Continuous Clock generation mode or not, true for enable and false for disable. - */ -static inline void USART_EnableContinuousSCLK(USART_Type *base, bool enable) -{ - if (enable) - { - base->CTL |= USART_CTL_CC_MASK; - } - else - { - base->CTL &= ~USART_CTL_CC_MASK; - } -} - -/*! - * @brief Enable Continuous Clock generation bit auto clear. - * While enable this cuntion, the Continuous Clock bit is automatically cleared when a complete - * character has been received. This bit is cleared at the same time. - * - * @param base USART peripheral base address. - * @param enable Enable auto clear or not, true for enable and false for disable. - */ -static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable) -{ - if (enable) - { - base->CTL |= USART_CTL_CLRCCONRX_MASK; - } - else - { - base->CTL &= ~USART_CTL_CLRCCONRX_MASK; - } -} - -/*! - * @brief Sets the rx FIFO watermark. - * - * @param base USART peripheral base address. - * @param water Rx FIFO watermark. - */ -static inline void USART_SetRxFifoWatermark(USART_Type *base, uint8_t water) -{ - assert(water <= (USART_FIFOTRIG_RXLVL_MASK >> USART_FIFOTRIG_RXLVL_SHIFT)); - base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_RXLVL_MASK) | USART_FIFOTRIG_RXLVL(water); -} - -/*! - * @brief Sets the tx FIFO watermark. - * - * @param base USART peripheral base address. - * @param water Tx FIFO watermark. - */ -static inline void USART_SetTxFifoWatermark(USART_Type *base, uint8_t water) -{ - assert(water <= (USART_FIFOTRIG_TXLVL_MASK >> USART_FIFOTRIG_TXLVL_SHIFT)); - base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_TXLVL_MASK) | USART_FIFOTRIG_TXLVL(water); -} -/* @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Writes to the FIFOWR register. - * - * This function writes data to the txFIFO directly. The upper layer must ensure - * that txFIFO has space for data to write before calling this function. - * - * @param base USART peripheral base address. - * @param data The byte to write. - */ -static inline void USART_WriteByte(USART_Type *base, uint8_t data) -{ - base->FIFOWR = data; -} - -/*! - * @brief Reads the FIFORD register directly. - * - * This function reads data from the rxFIFO directly. The upper layer must - * ensure that the rxFIFO is not empty before calling this function. - * - * @param base USART peripheral base address. - * @return The byte read from USART data register. - */ -static inline uint8_t USART_ReadByte(USART_Type *base) -{ - return (uint8_t)base->FIFORD; -} - -/*! - * @brief Gets the rx FIFO data count. - * - * @param base USART peripheral base address. - * @return rx FIFO data count. - */ -static inline uint8_t USART_GetRxFifoCount(USART_Type *base) -{ - return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_RXLVL_MASK) >> USART_FIFOSTAT_RXLVL_SHIFT); -} - -/*! - * @brief Gets the tx FIFO data count. - * - * @param base USART peripheral base address. - * @return tx FIFO data count. - */ -static inline uint8_t USART_GetTxFifoCount(USART_Type *base) -{ - return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); -} - -/*! - * @brief Transmit an address frame in 9-bit data mode. - * - * @param base USART peripheral base address. - * @param address USART slave address. - */ -void USART_SendAddress(USART_Type *base, uint8_t address); - -/*! - * @brief Writes to the TX register using a blocking method. - * - * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO - * to have room and writes data to the TX buffer. - * - * @param base USART peripheral base address. - * @param data Start address of the data to write. - * @param length Size of the data to write. - * @retval kStatus_USART_Timeout Transmission timed out and was aborted. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_Success Successfully wrote all data. - */ -status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length); - -/*! - * @brief Read RX data register using a blocking method. - * - * This function polls the RX register, waits for the RX register to be full or for RX FIFO to - * have data and read data from the TX register. - * - * @param base USART peripheral base address. - * @param data Start address of the buffer to store the received data. - * @param length Size of the buffer. - * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data. - * @retval kStatus_USART_ParityError Noise error happened while receiving data. - * @retval kStatus_USART_NoiseError Framing error happened while receiving data. - * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. - * @retval kStatus_USART_Timeout Transmission timed out and was aborted. - * @retval kStatus_Success Successfully received all data. - */ -status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the USART handle. - * - * This function initializes the USART handle which can be used for other USART - * transactional APIs. Usually, for a specified USART instance, - * call this API once to get the initialized handle. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param callback The callback function. - * @param userData The parameter of the callback function. - */ -status_t USART_TransferCreateHandle(USART_Type *base, - usart_handle_t *handle, - usart_transfer_callback_t callback, - void *userData); - -/*! - * @brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in the IRQ handler, the USART driver calls the callback - * function and passes the @ref kStatus_USART_TxIdle as status parameter. - * - * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written - * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, - * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART transfer structure. See #usart_transfer_t. - * @retval kStatus_Success Successfully start the data transmission. - * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific USART handle. - * - * When the RX ring buffer is used, data received are stored into the ring buffer even when the - * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * - * @note When using the RX ring buffer, one byte is reserved for internal use. In other - * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. - * @param ringBufferSize size of the ring buffer. - */ -void USART_TransferStartRingBuffer(USART_Type *base, - usart_handle_t *handle, - uint8_t *ringBuffer, - size_t ringBufferSize); - -/*! - * @brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the length of received data in RX ring buffer. - * - * @param handle USART handle pointer. - * @return Length of received data in RX ring buffer. - */ -size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle); - -/*! - * @brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out - * how many bytes are still not sent out. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been sent out to bus. - * - * This function gets the number of bytes that have been sent out to bus by interrupt method. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Send bytes count. - * @retval kStatus_NoTransferInProgress No send in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); - -/*! - * @brief Receives a buffer of data using an interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function, which - * returns without waiting for all data to be received. - * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and - * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in the ring buffer is not enough to read, the receive - * request is saved by the USART driver. When the new data arrives, the receive request - * is serviced first. When all data is received, the USART driver notifies the upper layer - * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle. - * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. - * The 5 bytes are copied to the xfer->data and this function returns with the - * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is - * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to the xfer->data. When all data is received, the upper layer is notified. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART transfer structure, see #usart_transfer_t. - * @param receivedBytes Bytes received from the ring buffer directly. - * @retval kStatus_Success Successfully queue the transfer into transmit queue. - * @retval kStatus_USART_RxBusy Previous receive request is not finished. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveNonBlocking(USART_Type *base, - usart_handle_t *handle, - usart_transfer_t *xfer, - size_t *receivedBytes); - -/*! - * @brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out - * how many bytes not received yet. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); - -/*! - * @brief USART IRQ handle function. - * - * This function handles the USART transmit and receive IRQ request. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_USART_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart_dma.c deleted file mode 100644 index 60c2d5284c5..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart_dma.c +++ /dev/null @@ -1,392 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_usart.h" -#include "fsl_device_registers.h" -#include "fsl_dma.h" -#include "fsl_flexcomm.h" -#include "fsl_usart_dma.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_dma" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ -enum -{ - kUSART_TxIdle, /* TX idle. */ - kUSART_TxBusy, /* TX busy. */ - kUSART_RxIdle, /* RX idle. */ - kUSART_RxBusy /* RX busy. */ -}; - -/*! @brief Typedef for usart DMA interrupt handler. */ -typedef void (*flexcomm_usart_dma_irq_handler_t)(USART_Type *base, usart_dma_handle_t *handle); - -/*base, false); - - /* Enable tx idle interrupt */ - usartPrivateHandle->base->INTENSET = USART_INTENSET_TXIDLEEN_MASK; -} - -static void USART_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode) -{ - assert(handle != NULL); - assert(param != NULL); - - usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param; - - /* Disable UART RX DMA. */ - USART_EnableRxDMA(usartPrivateHandle->base, false); - - usartPrivateHandle->handle->rxState = (uint8_t)kUSART_RxIdle; - - if (usartPrivateHandle->handle->callback != NULL) - { - usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_RxIdle, - usartPrivateHandle->handle->userData); - } -} - -/*! - * brief Initializes the USART handle which is used in transactional functions. - * param base USART peripheral base address. - * param handle Pointer to usart_dma_handle_t structure. - * param callback Callback function. - * param userData User data. - * param txDmaHandle User-requested DMA handle for TX DMA transfer. - * param rxDmaHandle User-requested DMA handle for RX DMA transfer. - */ -status_t USART_TransferCreateHandleDMA(USART_Type *base, - usart_dma_handle_t *handle, - usart_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *txDmaHandle, - dma_handle_t *rxDmaHandle) -{ - uint32_t instance = 0; - - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } - /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - instance = USART_GetInstance(base); - - (void)memset(handle, 0, sizeof(*handle)); - /* assign 'base' and 'handle' */ - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - /* set tx/rx 'idle' state */ - handle->rxState = (uint8_t)kUSART_RxIdle; - handle->txState = (uint8_t)kUSART_TxIdle; - - handle->callback = callback; - handle->userData = userData; - - handle->rxDmaHandle = rxDmaHandle; - handle->txDmaHandle = txDmaHandle; - - /* Set USART_TransferDMAHandleIRQ as DMA IRQ handler */ - usart_dma_to_flexcomm_t handler; - handler.usart_dma_handler = USART_TransferDMAHandleIRQ; - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - /* Enable NVIC IRQ. */ - (void)EnableIRQ(s_usartIRQ[instance]); - - /* Configure TX. */ - if (txDmaHandle != NULL) - { - DMA_SetCallback(txDmaHandle, USART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]); - } - - /* Configure RX. */ - if (rxDmaHandle != NULL) - { - DMA_SetCallback(rxDmaHandle, USART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]); - } - - return kStatus_Success; -} - -/*! - * brief Sends data using DMA. - * - * This function sends data using DMA. This is a non-blocking function, which returns - * right away. When all data is sent, the send callback function is called. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART DMA transfer structure. See #usart_transfer_t. - * retval kStatus_Success if succeed, others failed. - * retval kStatus_USART_TxBusy Previous transfer on going. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) -{ - assert(handle != NULL); - assert(handle->txDmaHandle != NULL); - assert(xfer != NULL); - assert(xfer->data != NULL); - assert(xfer->dataSize != 0U); - - dma_transfer_config_t xferConfig; - status_t status; - uint32_t address = (uint32_t)&base->FIFOWR; - - /* If previous TX not finished. */ - if ((uint8_t)kUSART_TxBusy == handle->txState) - { - status = kStatus_USART_TxBusy; - } - else - { - handle->txState = (uint8_t)kUSART_TxBusy; - handle->txDataSizeAll = xfer->dataSize; - - /* Enable DMA request from txFIFO */ - USART_EnableTxDMA(base, true); - - /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, xfer->data, (uint32_t *)address, sizeof(uint8_t), xfer->dataSize, - kDMA_MemoryToPeripheral, NULL); - - /* Submit transfer. */ - (void)DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); - DMA_StartTransfer(handle->txDmaHandle); - - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Receives data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * param base USART peripheral base address. - * param handle Pointer to usart_dma_handle_t structure. - * param xfer USART DMA transfer structure. See #usart_transfer_t. - * retval kStatus_Success if succeed, others failed. - * retval kStatus_USART_RxBusy Previous transfer on going. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) -{ - assert(handle != NULL); - assert(handle->rxDmaHandle != NULL); - assert(xfer != NULL); - assert(xfer->data != NULL); - assert(xfer->dataSize != 0U); - - dma_transfer_config_t xferConfig; - status_t status; - uint32_t address = (uint32_t)&base->FIFORD; - - /* If previous RX not finished. */ - if ((uint8_t)kUSART_RxBusy == handle->rxState) - { - status = kStatus_USART_RxBusy; - } - else - { - handle->rxState = (uint8_t)kUSART_RxBusy; - handle->rxDataSizeAll = xfer->dataSize; - - /* Enable DMA request from rxFIFO */ - USART_EnableRxDMA(base, true); - - /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, xfer->data, sizeof(uint8_t), xfer->dataSize, - kDMA_PeripheralToMemory, NULL); - - /* Submit transfer. */ - (void)DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); - DMA_StartTransfer(handle->rxDmaHandle); - - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Aborts the sent data using DMA. - * - * This function aborts send data using DMA. - * - * param base USART peripheral base address - * param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle) -{ - assert(NULL != handle); - assert(NULL != handle->txDmaHandle); - - /* Stop transfer. */ - DMA_AbortTransfer(handle->txDmaHandle); - handle->txState = (uint8_t)kUSART_TxIdle; -} - -/*! - * brief Aborts the received data using DMA. - * - * This function aborts the received data using DMA. - * - * param base USART peripheral base address - * param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle) -{ - assert(NULL != handle); - assert(NULL != handle->rxDmaHandle); - - /* Stop transfer. */ - DMA_AbortTransfer(handle->rxDmaHandle); - handle->rxState = (uint8_t)kUSART_RxIdle; -} - -/*! - * brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Receive bytes count. - * retval kStatus_NoTransferInProgress No receive in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != handle->rxDmaHandle); - assert(NULL != count); - - if ((uint8_t)kUSART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); - - return kStatus_Success; -} - -/*! - * brief Get the number of bytes that have been sent. - * - * This function gets the number of bytes that have been sent. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Sent bytes count. - * retval kStatus_NoTransferInProgress No receive in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != handle->txDmaHandle); - assert(NULL != count); - - if ((uint8_t)kUSART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel); - - return kStatus_Success; -} - -void USART_TransferDMAHandleIRQ(USART_Type *base, usart_dma_handle_t *handle) -{ - /* Check arguments */ - assert((NULL != base) && (NULL != handle)); - - /* Tx idle interrupt happens means that all the tx data have been sent out to bus, set the tx state to idle */ - handle->txState = (uint8_t)kUSART_TxIdle; - - /* Disable tx idle interrupt */ - base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK; - - /* Invoke callback */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart_dma.h deleted file mode 100644 index 901ee115e88..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart_dma.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_USART_DMA_H_ -#define _FSL_USART_DMA_H_ - -#include "fsl_common.h" -#include "fsl_dma.h" -#include "fsl_usart.h" - -/*! - * @addtogroup usart_dma_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief USART dma driver version. */ -#define FSL_USART_DMA_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) -/*@}*/ - -/* Forward declaration of the handle typedef. */ -typedef struct _usart_dma_handle usart_dma_handle_t; - -/*! @brief UART transfer callback function. */ -typedef void (*usart_dma_transfer_callback_t)(USART_Type *base, - usart_dma_handle_t *handle, - status_t status, - void *userData); - -/*! - * @brief UART DMA handle - */ -struct _usart_dma_handle -{ - USART_Type *base; /*!< UART peripheral base address. */ - - usart_dma_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< UART callback function parameter.*/ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - - dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */ - dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name DMA transactional - * @{ - */ - -/*! - * @brief Initializes the USART handle which is used in transactional functions. - * @param base USART peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param callback Callback function. - * @param userData User data. - * @param txDmaHandle User-requested DMA handle for TX DMA transfer. - * @param rxDmaHandle User-requested DMA handle for RX DMA transfer. - */ -status_t USART_TransferCreateHandleDMA(USART_Type *base, - usart_dma_handle_t *handle, - usart_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *txDmaHandle, - dma_handle_t *rxDmaHandle); - -/*! - * @brief Sends data using DMA. - * - * This function sends data using DMA. This is a non-blocking function, which returns - * right away. When all data is sent, the send callback function is called. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART DMA transfer structure. See #usart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_USART_TxBusy Previous transfer on going. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Receives data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * @param base USART peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param xfer USART DMA transfer structure. See #usart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_USART_RxBusy Previous transfer on going. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Aborts the sent data using DMA. - * - * This function aborts send data using DMA. - * - * @param base USART peripheral base address - * @param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle); - -/*! - * @brief Aborts the received data using DMA. - * - * This function aborts the received data using DMA. - * - * @param base USART peripheral base address - * @param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); - -/*! - * @brief Get the number of bytes that have been sent. - * - * This function gets the number of bytes that have been sent. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Sent bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_USART_DMA_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_utick.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_utick.c deleted file mode 100644 index 208b34cf9df..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_utick.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_utick.h" -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG) -#include "fsl_power.h" -#endif -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.utick" -#endif - -/* Typedef for interrupt handler. */ -typedef void (*utick_isr_t)(UTICK_Type *base, utick_callback_t cb); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base UTICK peripheral base address - * - * @return The UTICK instance - */ -static uint32_t UTICK_GetInstance(UTICK_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of UTICK handle. */ -static utick_callback_t s_utickHandle[FSL_FEATURE_SOC_UTICK_COUNT]; -/* Array of UTICK peripheral base address. */ -static UTICK_Type *const s_utickBases[] = UTICK_BASE_PTRS; -/* Array of UTICK IRQ number. */ -static const IRQn_Type s_utickIRQ[] = UTICK_IRQS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of UTICK clock name. */ -static const clock_ip_name_t s_utickClock[] = UTICK_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) -/*! @brief Pointers to UTICK resets for each instance. */ -static const reset_ip_name_t s_utickResets[] = UTICK_RSTS; -#endif - -/* UTICK ISR for transactional APIs. */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -static utick_isr_t s_utickIsr = (utick_isr_t)DefaultISR; -#else -static utick_isr_t s_utickIsr; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t UTICK_GetInstance(UTICK_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_utickBases); instance++) - { - if (s_utickBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_utickBases)); - - return instance; -} - -/*! - * brief Starts UTICK. - * - * This function starts a repeat/onetime countdown with an optional callback - * - * param base UTICK peripheral base address. - * param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) - * return none - */ -void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb) -{ - uint32_t instance; - - /* Get instance from peripheral base address. */ - instance = UTICK_GetInstance(base); - - /* Save the handle in global variables to support the double weak mechanism. */ - s_utickHandle[instance] = cb; -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) && \ - !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)) - EnableDeepSleepIRQ(s_utickIRQ[instance]); -#else - (void)EnableIRQ(s_utickIRQ[instance]); -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT && !FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ - base->CTRL = count | UTICK_CTRL_REPEAT(mode); -} - -/*! - * brief Initializes an UTICK by turning its bus clock on - * - */ -void UTICK_Init(UTICK_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable utick clock */ - CLOCK_EnableClock(s_utickClock[UTICK_GetInstance(base)]); -#endif - -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) - RESET_PeripheralReset(s_utickResets[UTICK_GetInstance(base)]); -#endif - -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG) - /* Power up Watchdog oscillator*/ - POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC); -#endif - - s_utickIsr = UTICK_HandleIRQ; -} - -/*! - * brief Deinitializes a UTICK instance. - * - * This function shuts down Utick bus clock - * - * param base UTICK peripheral base address. - */ -void UTICK_Deinit(UTICK_Type *base) -{ - /* Turn off utick */ - base->CTRL = 0; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable utick clock */ - CLOCK_DisableClock(s_utickClock[UTICK_GetInstance(base)]); -#endif -} - -/*! - * brief Get Status Flags. - * - * This returns the status flag - * - * param base UTICK peripheral base address. - * return status register value - */ -uint32_t UTICK_GetStatusFlags(UTICK_Type *base) -{ - return (base->STAT); -} - -/*! - * brief Clear Status Interrupt Flags. - * - * This clears intr status flag - * - * param base UTICK peripheral base address. - * return none - */ -void UTICK_ClearStatusFlags(UTICK_Type *base) -{ - base->STAT = UTICK_STAT_INTR_MASK; -} - -/*! - * brief UTICK Interrupt Service Handler. - * - * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request - * in UTICK_SetTick()). - * if no user callback is scheduled, the interrupt will simply be cleared. - * - * param base UTICK peripheral base address. - * param cb callback scheduled for this instance of UTICK - * return none - */ -void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb) -{ - UTICK_ClearStatusFlags(base); - if (cb != NULL) - { - cb(); - } -} - -#if defined(UTICK0) -void UTICK0_DriverIRQHandler(void); -void UTICK0_DriverIRQHandler(void) -{ - s_utickIsr(UTICK0, s_utickHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif -#if defined(UTICK1) -void UTICK1_DriverIRQHandler(void); -void UTICK1_DriverIRQHandler(void) -{ - s_utickIsr(UTICK1, s_utickHandle[1]); - SDK_ISR_EXIT_BARRIER; -} -#endif -#if defined(UTICK2) -void UTICK2_DriverIRQHandler(void); -void UTICK2_DriverIRQHandler(void) -{ - s_utickIsr(UTICK2, s_utickHandle[2]); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_utick.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_utick.h deleted file mode 100644 index 800cde8ce25..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_utick.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_UTICK_H_ -#define _FSL_UTICK_H_ - -#include "fsl_common.h" -/*! - * @addtogroup utick - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief UTICK driver version 2.0.4. */ -#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) -/*@}*/ - -/*! @brief UTICK timer operational mode. */ -typedef enum _utick_mode -{ - kUTICK_Onetime = 0x0U, /*!< Trigger once*/ - kUTICK_Repeat = 0x1U, /*!< Trigger repeatedly */ -} utick_mode_t; - -/*! @brief UTICK callback function. */ -typedef void (*utick_callback_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes an UTICK by turning its bus clock on - * - */ -void UTICK_Init(UTICK_Type *base); - -/*! - * @brief Deinitializes a UTICK instance. - * - * This function shuts down Utick bus clock - * - * @param base UTICK peripheral base address. - */ -void UTICK_Deinit(UTICK_Type *base); -/*! - * @brief Get Status Flags. - * - * This returns the status flag - * - * @param base UTICK peripheral base address. - * @return status register value - */ -uint32_t UTICK_GetStatusFlags(UTICK_Type *base); -/*! - * @brief Clear Status Interrupt Flags. - * - * This clears intr status flag - * - * @param base UTICK peripheral base address. - * @return none - */ -void UTICK_ClearStatusFlags(UTICK_Type *base); - -/*! - * @brief Starts UTICK. - * - * This function starts a repeat/onetime countdown with an optional callback - * - * @param base UTICK peripheral base address. - * @param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * @param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * @param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) - * @return none - */ -void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb); -/*! - * @brief UTICK Interrupt Service Handler. - * - * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request - * in UTICK_SetTick()). - * if no user callback is scheduled, the interrupt will simply be cleared. - * - * @param base UTICK peripheral base address. - * @param cb callback scheduled for this instance of UTICK - * @return none - */ -void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_UTICK_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_vref.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_vref.c deleted file mode 100644 index d0ab8ebf3aa..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_vref.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * Copyright 2019-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_vref.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.vref_1" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Gets the instance from the base address - * - * @param base VREF peripheral base address - * - * @return The VREF instance - */ -static uint32_t VREF_GetInstance(VREF_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Pointers to VREF bases for each instance. */ -static VREF_Type *const s_vrefBases[] = VREF_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to VREF clocks for each instance. */ -static const clock_ip_name_t s_vrefClocks[] = VREF_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t VREF_GetInstance(VREF_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_vrefBases); instance++) - { - if (s_vrefBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_vrefBases)); - - return instance; -} - -/*! - * brief Enables the clock gate and configures the VREF module according to the configuration structure. - * - * This function must be called before calling all other VREF driver functions, read/write registers, and - * configurations with user-defined settings. The example below shows how to set up vref_config_t parameters - * and how to call the VREF_Init function by passing in these parameters. - * code - * vref_config_t vrefConfig; - * VREF_GetDefaultConfig(VREF, &vrefConfig); - * vrefConfig.bufferMode = kVREF_ModeHighPowerBuffer; - * VREF_Init(VREF, &vrefConfig); - * endcode - * - * param base VREF peripheral address. - * param config Pointer to the configuration structure. - */ -void VREF_Init(VREF_Type *base, const vref_config_t *config) -{ - assert(config != NULL); - - uint32_t tmp32 = 0UL; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate clock for VREF */ - CLOCK_EnableClock(s_vrefClocks[VREF_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Enable low power bandgap at first. */ - tmp32 = VREF_CSR_LPBGEN_MASK | VREF_CSR_LPBG_BUF_EN_MASK | VREF_CSR_VRSEL(config->vrefSel); - - /* Configure buffer mode. */ - switch (config->bufferMode) - { - case kVREF_ModeBandgapOnly: - break; - case kVREF_ModeLowPowerBuffer: - tmp32 |= VREF_CSR_BUF21EN_MASK; - break; - case kVREF_ModeHighPowerBuffer: - tmp32 |= (VREF_CSR_BUF21EN_MASK | VREF_CSR_HI_PWR_LV_MASK); - break; - default: - assert(false); - break; - } - - /* Enable internal voltage regulator */ - if (config->enableInternalVoltageRegulator) - { - /* Enable internal voltage regulator to provide the optimum VREF performance. */ - tmp32 |= VREF_CSR_REGEN_MASK | VREF_CSR_CHOPEN_MASK | VREF_CSR_ICOMPEN_MASK; - base->CSR = tmp32; - /* After enabling low power bandgap, delay 20 us. */ - SDK_DelayAtLeastUs(20U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - /* Enable high accurancy bandgap for vref output. */ - if (config->enableVrefOut) - { - base->CSR |= VREF_CSR_HCBGEN_MASK; - } - /* After enabling high accurancy bandgap, delay 400 us. */ - SDK_DelayAtLeastUs(400U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - } - else - { - /* Enable high accurancy bandgap for vref output. */ - if (config->enableVrefOut) - { - tmp32 |= VREF_CSR_HCBGEN_MASK; - base->CSR = tmp32; - /* Wait until internal voltage stable */ - while ((base->CSR & VREF_CSR_VREFST_MASK) == 0U) - { - } - } - else - { - base->CSR = tmp32; - } - } -} - -/*! - * brief Stops and disables the clock for the VREF module. - * - * This function should be called to shut down the module. - * This is an example. - * code - * vref_config_t vrefUserConfig; - * VREF_GetDefaultConfig(VREF, &vrefUserConfig); - * VREF_Init(VREF, &vrefUserConfig); - * ... - * VREF_Deinit(VREF); - * endcode - * - * param base VREF peripheral address. - */ -void VREF_Deinit(VREF_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate clock for VREF */ - CLOCK_DisableClock(s_vrefClocks[VREF_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Initializes the VREF configuration structure. - * - * This function initializes the VREF configuration structure to default values. - * This is an example. - * code - * config->bufferMode = kVREF_ModeHighPowerBuffer; - * config->enableInternalVoltageRegulator = true; - * config->enableVrefOut = true; - * config->vrefSel = kVREF_InternalBandgap; - * endcode - * - * param config Pointer to the initialization structure. - */ -void VREF_GetDefaultConfig(vref_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->bufferMode = kVREF_ModeHighPowerBuffer; - config->enableInternalVoltageRegulator = true; - config->enableVrefOut = true; - config->vrefSel = kVREF_InternalBandgap; -} - -/*! - * brief Sets a TRIM value for the accurate 1.0V bandgap output. - * - * This function sets a TRIM value for the reference voltage. It will trim the accurate 1.0V bandgap by 0.5mV each step. - * - * param base VREF peripheral address. - * param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)). - */ -void VREF_SetVrefTrimVal(VREF_Type *base, uint8_t trimValue) -{ - uint32_t tmp32 = base->UTRIM; - - tmp32 &= (~VREF_UTRIM_VREFTRIM_MASK); - tmp32 |= VREF_UTRIM_VREFTRIM(trimValue); - - base->UTRIM = tmp32; - - if (VREF_CSR_CHOPEN_MASK == (base->CSR & VREF_CSR_CHOPEN_MASK)) - { - /* After enabling high accurancy bandgap, delay 400 us. */ - SDK_DelayAtLeastUs(400U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - } - else - { - while ((base->CSR & VREF_CSR_VREFST_MASK) == 0U) - { - } - } -} - -/*! - * brief Sets a TRIM value for the accurate buffered VREF output. - * - * This function sets a TRIM value for the reference voltage. If buffer mode be set to other values (Buf21 - * enabled), it will trim the VREF_OUT by 0.1V each step from 1.0V to 2.1V. - * - * note When Buf21 is enabled, the value of UTRIM[TRIM2V1] should be ranged from 0b0000 to 0b1011 in order to trim the - * output voltage from 1.0V to 2.1V, other values will make the VREF_OUT to default value, 1.0V. - * - * param base VREF peripheral address. - * param trimValue Value of the trim register to set the output reference voltage (maximum 0xF (4-bit)). - */ -void VREF_SetTrim21Val(VREF_Type *base, uint8_t trim21Value) -{ - uint32_t tmp32 = base->UTRIM; - - if (VREF_CSR_BUF21EN_MASK == (base->CSR & VREF_CSR_BUF21EN_MASK)) - { - tmp32 &= (~VREF_UTRIM_TRIM2V1_MASK); - tmp32 |= VREF_UTRIM_TRIM2V1(trim21Value); - } - - base->UTRIM = tmp32; - - if (VREF_CSR_CHOPEN_MASK == (base->CSR & VREF_CSR_CHOPEN_MASK)) - { - /* After enabling high accurancy bandgap, delay 400 us. */ - SDK_DelayAtLeastUs(400U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - } - else - { - while ((base->CSR & VREF_CSR_VREFST_MASK) == 0U) - { - } - } -} - -/*! - * brief Reads the VREF trim value.. - * - * This function gets the TRIM value from the UTRIM register. It reads UTRIM[VREFTRIM] (13:8) - * - * param base VREF peripheral address. - * return 6-bit value of trim setting. - */ -uint8_t VREF_GetVrefTrimVal(VREF_Type *base) -{ - uint8_t trimValue; - - trimValue = (uint8_t)((base->UTRIM & VREF_UTRIM_VREFTRIM_MASK) >> VREF_UTRIM_VREFTRIM_SHIFT); - - return trimValue; -} - -/*! - * brief Reads the VREF 2.1V trim value.. - * - * This function gets the TRIM value from the UTRIM register. It reads UTRIM[TRIM2V1] (3:0), - * - * param base VREF peripheral address. - * return 4-bit value of trim setting. - */ -uint8_t VREF_GetTrim21Val(VREF_Type *base) -{ - uint8_t trimValue; - - trimValue = (uint8_t)((base->UTRIM & VREF_UTRIM_TRIM2V1_MASK) >> VREF_UTRIM_TRIM2V1_SHIFT); - - return trimValue; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_vref.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_vref.h deleted file mode 100644 index 51ff4bb9272..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_vref.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright 2019-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_VREF_H_ -#define _FSL_VREF_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup vref - * @{ - */ - -/****************************************************************************** - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_VREF_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ -/*@}*/ - -/*! @brief VREF buffer modes. */ -typedef enum _vref_buffer_mode -{ - kVREF_ModeBandgapOnly = 0U, /*!< Bandgap enabled/standby. */ - kVREF_ModeLowPowerBuffer = 1U, /*!< High-power buffer mode enabled */ - kVREF_ModeHighPowerBuffer = 2U /*!< Low-power buffer mode enabled */ -} vref_buffer_mode_t; - -/*! @brief Voltage reference selection. */ -typedef enum _vref_voltage_reference_sel -{ - kVREF_InternalBandgap = 0U, /*!< Internal bandgap. */ - kVREF_LowPowerBuffed1v = 1U, /*!< Low power buffered 1v. */ - kVREF_LowPowerBufferMode = 2U, /*!< Low-power buffer mode enabled. */ -} vref_voltage_reference_sel_t; - -/*! @brief The description structure for the VREF module. */ -typedef struct _vref_config -{ - vref_buffer_mode_t bufferMode; /*!< Buffer mode selection */ - bool enableInternalVoltageRegulator; /*!< Provide additional supply noise rejection. */ - bool enableVrefOut; /*!< Enable the VREF supply voltage on VREF_OUT. */ - vref_voltage_reference_sel_t vrefSel; /*!< Control voltage reference selection */ -} vref_config_t; - -/****************************************************************************** - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Enables the clock gate and configures the VREF module according to the configuration structure. - * - * This function must be called before calling all other VREF driver functions, read/write registers, and - * configurations with user-defined settings. The example below shows how to set up vref_config_t parameters - * and how to call the VREF_Init function by passing in these parameters. - * @code - * vref_config_t vrefConfig; - * VREF_GetDefaultConfig(VREF, &vrefConfig); - * vrefConfig.bufferMode = kVREF_ModeHighPowerBuffer; - * VREF_Init(VREF, &vrefConfig); - * @endcode - * - * @param base VREF peripheral address. - * @param config Pointer to the configuration structure. - */ -void VREF_Init(VREF_Type *base, const vref_config_t *config); - -/*! - * @brief Stops and disables the clock for the VREF module. - * - * This function should be called to shut down the module. - * This is an example. - * @code - * vref_config_t vrefUserConfig; - * VREF_GetDefaultConfig(VREF, &vrefUserConfig); - * VREF_Init(VREF, &vrefUserConfig); - * ... - * VREF_Deinit(VREF); - * @endcode - * - * @param base VREF peripheral address. - */ -void VREF_Deinit(VREF_Type *base); - -/*! - * @brief Initializes the VREF configuration structure. - * - * This function initializes the VREF configuration structure to default values. - * This is an example. - * @code - * config->bufferMode = kVREF_ModeHighPowerBuffer; - * config->enableInternalVoltageRegulator = true; - * config->enableVrefOut = true; - * config->vrefSel = kVREF_InternalBandgap; - * @endcode - * - * @param config Pointer to the initialization structure. - */ -void VREF_GetDefaultConfig(vref_config_t *config); - -/* @} */ - -/*! - * @name Trim functions - * @{ - */ - -/*! - * brief Sets a TRIM value for the accurate 1.0V bandgap output. - * - * This function sets a TRIM value for the reference voltage. It will trim the accurate 1.0V bandgap by 0.5mV each step. - * - * param base VREF peripheral address. - * param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)). - */ -void VREF_SetVrefTrimVal(VREF_Type *base, uint8_t trimValue); - -/*! - * brief Sets a TRIM value for the accurate buffered VREF output. - * - * This function sets a TRIM value for the reference voltage. If buffer mode be set to other values (Buf21 - * enabled), it will trim the VREF_OUT by 0.1V each step from 1.0V to 2.1V. - * - * note When Buf21 is enabled, the value of UTRIM[TRIM2V1] should be ranged from 0b0000 to 0b1011 in order to trim the - * output voltage from 1.0V to 2.1V, other values will make the VREF_OUT to default value, 1.0V. - * - * param base VREF peripheral address. - * param trimValue Value of the trim register to set the output reference voltage (maximum 0xF (4-bit)). - */ -void VREF_SetTrim21Val(VREF_Type *base, uint8_t trim21Value); - -/*! - * brief Reads the VREF trim value.. - * - * This function gets the TRIM value from the UTRIM register. It reads UTRIM[VREFTRIM] (13:8) - * - * param base VREF peripheral address. - * return 6-bit value of trim setting. - */ -uint8_t VREF_GetVrefTrimVal(VREF_Type *base); - -/*! - * brief Reads the VREF 2.1V trim value.. - * - * This function gets the TRIM value from the UTRIM register. It reads UTRIM[TRIM2V1] (3:0), - * - * param base VREF peripheral address. - * return 4-bit value of trim setting. - */ -uint8_t VREF_GetTrim21Val(VREF_Type *base); - -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_VREF_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_wwdt.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_wwdt.c deleted file mode 100644 index 6680148acf7..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_wwdt.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_wwdt.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.wwdt" -#endif - -#define FREQUENCY_3MHZ (3000000U) -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Gets the instance from the base address - * - * @param base WWDT peripheral base address - * - * @return The WWDT instance - */ -static uint32_t WWDT_GetInstance(WWDT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to WWDT bases for each instance. */ -static WWDT_Type *const s_wwdtBases[] = WWDT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to WWDT clocks for each instance. */ -static const clock_ip_name_t s_wwdtClocks[] = WWDT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) -/*! @brief Pointers to WWDT resets for each instance. */ -static const reset_ip_name_t s_wwdtResets[] = WWDT_RSTS; -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t WWDT_GetInstance(WWDT_Type *base) -{ - uint32_t instance; - uint32_t wwdtArrayCount = (sizeof(s_wwdtBases) / sizeof(s_wwdtBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < wwdtArrayCount; instance++) - { - if (s_wwdtBases[instance] == base) - { - break; - } - } - - assert(instance < wwdtArrayCount); - - return instance; -} - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Initializes WWDT configure structure. - * - * This function initializes the WWDT configure structure to default value. The default - * value are: - * code - * config->enableWwdt = true; - * config->enableWatchdogReset = false; - * config->enableWatchdogProtect = false; - * config->enableLockOscillator = false; - * config->windowValue = 0xFFFFFFU; - * config->timeoutValue = 0xFFFFFFU; - * config->warningValue = 0; - * endcode - * - * param config Pointer to WWDT config structure. - * see wwdt_config_t - */ -void WWDT_GetDefaultConfig(wwdt_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* Enable the watch dog */ - config->enableWwdt = true; - /* Disable the watchdog timeout reset */ - config->enableWatchdogReset = false; - /* Disable the watchdog protection for updating the timeout value */ - config->enableWatchdogProtect = false; -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) - /* Do not lock the watchdog oscillator */ - config->enableLockOscillator = false; -#endif - /* Windowing is not in effect */ - config->windowValue = 0xFFFFFFU; - /* Set the timeout value to the max */ - config->timeoutValue = 0xFFFFFFU; - /* No warning is provided */ - config->warningValue = 0; - /* Set clock frequency. */ - config->clockFreq_Hz = 0U; -} - -/*! - * brief Initializes the WWDT. - * - * This function initializes the WWDT. When called, the WWDT runs according to the configuration. - * - * Example: - * code - * wwdt_config_t config; - * WWDT_GetDefaultConfig(&config); - * config.timeoutValue = 0x7ffU; - * WWDT_Init(wwdt_base,&config); - * endcode - * - * param base WWDT peripheral base address - * param config The configuration of WWDT - */ -void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config) -{ - assert(NULL != config); - - uint32_t value = 0U; - uint32_t DelayUs = 0U; - uint32_t primaskValue = 0U; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the WWDT clock */ - CLOCK_EnableClock(s_wwdtClocks[WWDT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) - /* Reset the module. */ - RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]); -#endif - -#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) - /* PMC RESETCAUSE: set bit to clear it by write 1. */ - PMC->RESETCAUSE = PMC_RESETCAUSE_WDTRESET_MASK; - /* Enable the watchdog reset event to affect the system in the Power Management Controller */ - PMC->CTRL |= PMC_CTRL_WDTRESETENABLE_MASK; -#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ - -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) - value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) | - WWDT_MOD_LOCK(config->enableLockOscillator); -#else - value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset); -#endif - /* Clear legacy flag in the MOD register by software writing a "1" to this bit field.. */ - if (0U != (base->MOD & WWDT_MOD_WDINT_MASK)) - { - value |= WWDT_MOD_WDINT_MASK; - } - /* Set configuration */ - primaskValue = DisableGlobalIRQ(); - base->TC = WWDT_TC_COUNT(config->timeoutValue); - base->MOD = value; - base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue); - base->WARNINT = WWDT_WARNINT_WARNINT(config->warningValue); - /* Refreshes the WWDT timer. */ - base->FEED = WWDT_FIRST_WORD_OF_REFRESH; - base->FEED = WWDT_SECOND_WORD_OF_REFRESH; - EnableGlobalIRQ(primaskValue); - /* Read counter value to wait wwdt timer start*/ - if (config->enableWwdt) - { - while (base->TV == 0xFFUL) - { - } - } - - /* This WDPROTECT bit can be set once by software and is only cleared by a reset */ - if (config->enableWatchdogProtect && (0U == (base->MOD & WWDT_MOD_WDPROTECT_MASK))) - { - /* The config->clockFreq_Hz must be set in order to config the delay time. */ - assert(0U != config->clockFreq_Hz); - - /* Set the WDPROTECT bit after the Feed Sequence (0xAA, 0x55) with 3 WDCLK delay */ - DelayUs = FREQUENCY_3MHZ / config->clockFreq_Hz + 1U; - SDK_DelayAtLeastUs(DelayUs, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - - base->MOD |= WWDT_MOD_WDPROTECT(1U); - } -} - -/*! - * brief Shuts down the WWDT. - * - * This function shuts down the WWDT. - * - * param base WWDT peripheral base address - */ -void WWDT_Deinit(WWDT_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the WWDT clock */ - CLOCK_DisableClock(s_wwdtClocks[WWDT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Refreshes the WWDT timer. - * - * This function feeds the WWDT. - * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. - * - * param base WWDT peripheral base address - */ -void WWDT_Refresh(WWDT_Type *base) -{ - uint32_t primaskValue = 0U; - - /* Disable the global interrupt to protect refresh sequence */ - primaskValue = DisableGlobalIRQ(); - base->FEED = WWDT_FIRST_WORD_OF_REFRESH; - base->FEED = WWDT_SECOND_WORD_OF_REFRESH; - EnableGlobalIRQ(primaskValue); -} - -/*! - * brief Clear WWDT flag. - * - * This function clears WWDT status flag. - * - * Example for clearing warning flag: - * code - * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); - * endcode - * param base WWDT peripheral base address - * param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask) -{ - /* Clear the WDINT bit so that we don't accidentally clear it */ - uint32_t reg = (base->MOD & (~WWDT_MOD_WDINT_MASK)); - - /* Clear timeout by writing a zero */ - if (0U != (mask & (uint32_t)kWWDT_TimeoutFlag)) - { - reg &= ~WWDT_MOD_WDTOF_MASK; -#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) - /* PMC RESETCAUSE: set bit to clear it */ - PMC->RESETCAUSE = PMC_RESETCAUSE_WDTRESET_MASK; -#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ - } - - /* Clear warning interrupt flag by writing a one */ - if (0U != (mask & (uint32_t)kWWDT_WarningFlag)) - { - reg |= WWDT_MOD_WDINT_MASK; - } - - base->MOD = reg; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_wwdt.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_wwdt.h deleted file mode 100644 index 25462534966..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_wwdt.h +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_WWDT_H_ -#define _FSL_WWDT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup wwdt - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Defines WWDT driver version. */ -#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 1, 9)) -/*@}*/ - -/*! @name Refresh sequence */ -/*@{*/ -#define WWDT_FIRST_WORD_OF_REFRESH (0xAAU) /*!< First word of refresh sequence */ -#define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */ -/*@}*/ - -/*! @brief Describes WWDT configuration structure. */ -typedef struct _wwdt_config -{ - bool enableWwdt; /*!< Enables or disables WWDT */ - bool enableWatchdogReset; /*!< true: Watchdog timeout will cause a chip reset - false: Watchdog timeout will not cause a chip reset */ - bool enableWatchdogProtect; /*!< true: Enable watchdog protect i.e timeout value can only be - changed after counter is below warning & window values - false: Disable watchdog protect; timeout value can be changed - at any time */ -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) - bool enableLockOscillator; /*!< true: Disabling or powering down the watchdog oscillator is prevented - Once set, this bit can only be cleared by a reset - false: Do not lock oscillator */ -#endif - uint32_t windowValue; /*!< Window value, set this to 0xFFFFFF if windowing is not in effect */ - uint32_t timeoutValue; /*!< Timeout value */ - uint32_t warningValue; /*!< Watchdog time counter value that will generate a - warning interrupt. Set this to 0 for no warning */ - uint32_t clockFreq_Hz; /*!< Watchdog clock source frequency. */ -} wwdt_config_t; - -/*! - * @brief WWDT status flags. - * - * This structure contains the WWDT status flags for use in the WWDT functions. - */ -enum _wwdt_status_flags_t -{ - kWWDT_TimeoutFlag = WWDT_MOD_WDTOF_MASK, /*!< Time-out flag, set when the timer times out */ - kWWDT_WarningFlag = WWDT_MOD_WDINT_MASK /*!< Warning interrupt flag, set when timer is below the value WDWARNINT */ -}; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name WWDT Initialization and De-initialization - * @{ - */ - -/*! - * @brief Initializes WWDT configure structure. - * - * This function initializes the WWDT configure structure to default value. The default - * value are: - * @code - * config->enableWwdt = true; - * config->enableWatchdogReset = false; - * config->enableWatchdogProtect = false; - * config->enableLockOscillator = false; - * config->windowValue = 0xFFFFFFU; - * config->timeoutValue = 0xFFFFFFU; - * config->warningValue = 0; - * @endcode - * - * @param config Pointer to WWDT config structure. - * @see wwdt_config_t - */ -void WWDT_GetDefaultConfig(wwdt_config_t *config); - -/*! - * @brief Initializes the WWDT. - * - * This function initializes the WWDT. When called, the WWDT runs according to the configuration. - * - * Example: - * @code - * wwdt_config_t config; - * WWDT_GetDefaultConfig(&config); - * config.timeoutValue = 0x7ffU; - * WWDT_Init(wwdt_base,&config); - * @endcode - * - * @param base WWDT peripheral base address - * @param config The configuration of WWDT - */ -void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config); - -/*! - * @brief Shuts down the WWDT. - * - * This function shuts down the WWDT. - * - * @param base WWDT peripheral base address - */ -void WWDT_Deinit(WWDT_Type *base); - -/* @} */ - -/*! - * @name WWDT Functional Operation - * @{ - */ - -/*! - * @brief Enables the WWDT module. - * - * This function write value into WWDT_MOD register to enable the WWDT, it is a write-once bit; - * once this bit is set to one and a watchdog feed is performed, the watchdog timer will run - * permanently. - * - * @param base WWDT peripheral base address - */ -static inline void WWDT_Enable(WWDT_Type *base) -{ - base->MOD |= WWDT_MOD_WDEN_MASK; -} - -/*! - * @brief Disables the WWDT module. - * @deprecated Do not use this function. It will be deleted in next release version, for - * once the bit field of WDEN written with a 1, it can not be re-written with a 0. - * - * This function write value into WWDT_MOD register to disable the WWDT. - * - * @param base WWDT peripheral base address - */ -static inline void WWDT_Disable(WWDT_Type *base) -{ - base->MOD &= ~WWDT_MOD_WDEN_MASK; -} - -/*! - * @brief Gets all WWDT status flags. - * - * This function gets all status flags. - * - * Example for getting Timeout Flag: - * @code - * uint32_t status; - * status = WWDT_GetStatusFlags(wwdt_base) & kWWDT_TimeoutFlag; - * @endcode - * @param base WWDT peripheral base address - * @return The status flags. This is the logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -static inline uint32_t WWDT_GetStatusFlags(WWDT_Type *base) -{ -#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) - uint32_t status; - /* WDTOF is not set in case of WD reset - get info from PMC instead */ - status = (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); - if (PMC->RESETCAUSE & PMC_RESETCAUSE_WDTRESET_MASK) - { - status |= kWWDT_TimeoutFlag; - } - return status; -#else - return (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); -#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ -} - -/*! - * @brief Clear WWDT flag. - * - * This function clears WWDT status flag. - * - * Example for clearing warning flag: - * @code - * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); - * @endcode - * @param base WWDT peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask); - -/*! - * @brief Set the WWDT warning value. - * - * The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog - * interrupt. When the watchdog timer counter is no longer greater than the value defined by - * WARNINT, an interrupt will be generated after the subsequent WDCLK. - * - * @param base WWDT peripheral base address - * @param warningValue WWDT warning value. - */ -static inline void WWDT_SetWarningValue(WWDT_Type *base, uint32_t warningValue) -{ - base->WARNINT = WWDT_WARNINT_WARNINT(warningValue); -} - -/*! - * @brief Set the WWDT timeout value. - * - * This function sets the timeout value. Every time a feed sequence occurs the value in the TC - * register is loaded into the Watchdog timer. Writing a value below 0xFF will cause 0xFF to be - * loaded into the TC register. Thus the minimum time-out interval is TWDCLK*256*4. - * If enableWatchdogProtect flag is true in wwdt_config_t config structure, any attempt to change - * the timeout value before the watchdog counter is below the warning and window values - * will cause a watchdog reset and set the WDTOF flag. - * - * @param base WWDT peripheral base address - * @param timeoutCount WWDT timeout value, count of WWDT clock tick. - */ -static inline void WWDT_SetTimeoutValue(WWDT_Type *base, uint32_t timeoutCount) -{ - base->TC = WWDT_TC_COUNT(timeoutCount); -} - -/*! - * @brief Sets the WWDT window value. - * - * The WINDOW register determines the highest TV value allowed when a watchdog feed is performed. - * If a feed sequence occurs when timer value is greater than the value in WINDOW, a watchdog - * event will occur. To disable windowing, set windowValue to 0xFFFFFF (maximum possible timer - * value) so windowing is not in effect. - * - * @param base WWDT peripheral base address - * @param windowValue WWDT window value. - */ -static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue) -{ - base->WINDOW = WWDT_WINDOW_WINDOW(windowValue); -} - -/*! - * @brief Refreshes the WWDT timer. - * - * This function feeds the WWDT. - * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. - * - * @param base WWDT peripheral base address - */ -void WWDT_Refresh(WWDT_Type *base); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_WWDT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/fsl_mem_interface.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/fsl_mem_interface.h deleted file mode 100644 index 6d99e708fc6..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/fsl_mem_interface.h +++ /dev/null @@ -1,379 +0,0 @@ -/* - * Copyright 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_MEM_INTERFACE_H_ -#define _FSL_MEM_INTERFACE_H_ - -#include "fsl_sbloader.h" -#include "fsl_common.h" - -/*! - * @addtogroup memory_interface - * @{ - */ -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Bit mask for device ID. */ -#define DEVICE_ID_MASK (0xffU) -/*! @brief Bit position of device ID. */ -#define DEVICE_ID_SHIFT 0U -/*! @brief Bit mask for group ID. */ -#define GROUP_ID_MASK (0xf00U) -/*! @brief Bit position of group ID. */ -#define GROUP_ID_SHIFT 8U - -/*! @brief Construct a memory ID from a given group ID and device ID. */ -#define MAKE_MEMORYID(group, device) \ - ((((group) << GROUP_ID_SHIFT) & GROUP_ID_MASK) | (((device) << DEVICE_ID_SHIFT) & DEVICE_ID_MASK)) -/*! @brief Get group ID from a given memory ID. */ -#define GROUPID(memoryId) (((memoryId)&GROUP_ID_MASK) >> GROUP_ID_SHIFT) - -/*! @brief Get device ID from a given memory ID. */ -#define DEVICEID(memoryId) (((memoryId)&DEVICE_ID_MASK) >> DEVICE_ID_SHIFT) - -/*! @brief Memory group definition. */ -enum -{ - kMemoryGroup_Internal = 0U, /*!< Memory belongs internal 4G memory region. */ - kMemoryGroup_External = 1U, /*!< Memory belongs external memory region. */ -}; - -/*! @brief Memory device ID definition. */ -enum -{ - /* Memory ID bitfiled definition. - | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | - | Reserved | INT/EXT | Type | Sub-Type | - | | 0: INT | INT: | | - | | 1: EXT | 0: NorFlash0 | 0: Internal Flash(FTFX) | - | | | | 1: QSPI | - | | | | 4: IFR | - | | | | 5: LPC FFR | - | | | | 8: SEMC | - | | | | 9: FlexSPI | - | | | | others: Unused | - | | | | | - | | | 1: ExecuteOnlyRegion | 0: Internal Flash(FTFX) | - | | | | others: Unused | - | | | | | - | | | others: Unused | | - | | | | | - | | | EXT: | | - | | | 0: NandFlash | 0: SEMC | - | | | | 1: FlexSPI | - | | | | others: Unused | - | | | | | - | | | 1: NorFlash/EEPROM | 0: LPSPI | - | | | | 1: LPI2C | - | | | | others: Unused | - | | | | | - | | | 2: SD/SDHC/SDXC/MMC/eMMC | 0: uSDHC SD | - | | | | 1: uSDHC MMC | - | | | | others: Unused | - | | | others: Unused | | - - INT : Internal 4G memory, including internal memory modules, and XIP external memory modules. - EXT : Non-XIP external memory modules. - */ - kMemoryInternal = MAKE_MEMORYID(kMemoryGroup_Internal, 0U), /*!< Internal memory (include all on chip memory) */ - kMemoryQuadSpi0 = MAKE_MEMORYID(kMemoryGroup_Internal, 1U), /*!< Qsuad SPI memory 0 */ - kMemoryIFR0 = - MAKE_MEMORYID(kMemoryGroup_Internal, 4U), /*!< Nonvolatile information register 0. Only used by SB loader. */ - kMemoryFFR = MAKE_MEMORYID(kMemoryGroup_Internal, 5U), /*!< LPCc040hd flash FFR region. */ - kMemorySemcNor = MAKE_MEMORYID(kMemoryGroup_Internal, 8U), /*!< SEMC Nor memory */ - kMemoryFlexSpiNor = MAKE_MEMORYID(kMemoryGroup_Internal, 9U), /*!< Flex SPI Nor memory */ - kMemorySpifiNor = MAKE_MEMORYID(kMemoryGroup_Internal, 0xAU), /*!< SPIFI Nor memory */ - kMemoryFlashExecuteOnly = MAKE_MEMORYID(kMemoryGroup_Internal, 0x10U), /*!< Execute-only region on internal Flash */ - - kMemorySemcNand = MAKE_MEMORYID(kMemoryGroup_External, 0U), /*!< SEMC NAND memory */ - kMemorySpiNand = MAKE_MEMORYID(kMemoryGroup_External, 1U), /*!< SPI NAND memory */ - kMemorySpiNorEeprom = MAKE_MEMORYID(kMemoryGroup_External, 0x10U), /*!< SPI NOR/EEPROM memory */ - kMemoryI2cNorEeprom = MAKE_MEMORYID(kMemoryGroup_External, 0x11U), /*!< I2C NOR/EEPROM memory */ - kMemorySDCard = MAKE_MEMORYID(kMemoryGroup_External, 0x20U), /*!< eSD, SD, SDHC, SDXC memory Card */ - kMemoryMMCCard = MAKE_MEMORYID(kMemoryGroup_External, 0x21U), /*!< MMC, eMMC memory Card */ -}; - -/*! @brief Bootloader status group numbers. - * - * @ingroup bl_core - */ -enum -{ - kStatusGroup_Bootloader = 100, /*!< Bootloader status group number (100). */ - kStatusGroup_MemoryInterface = 102, /*!< Memory interface status group number (102). */ -}; - -/*! @brief Memory interface status codes. */ -enum -{ - kStatusMemoryRangeInvalid = MAKE_STATUS(kStatusGroup_MemoryInterface, 0), - kStatusMemoryReadFailed = MAKE_STATUS(kStatusGroup_MemoryInterface, 1), - kStatusMemoryWriteFailed = MAKE_STATUS(kStatusGroup_MemoryInterface, 2), - kStatusMemoryCumulativeWrite = MAKE_STATUS(kStatusGroup_MemoryInterface, 3), - kStatusMemoryAppOverlapWithExecuteOnlyRegion = MAKE_STATUS(kStatusGroup_MemoryInterface, 4), - kStatusMemoryNotConfigured = MAKE_STATUS(kStatusGroup_MemoryInterface, 5), - kStatusMemoryAlignmentError = MAKE_STATUS(kStatusGroup_MemoryInterface, 6), - kStatusMemoryVerifyFailed = MAKE_STATUS(kStatusGroup_MemoryInterface, 7), - kStatusMemoryWriteProtected = MAKE_STATUS(kStatusGroup_MemoryInterface, 8), - kStatusMemoryAddressError = MAKE_STATUS(kStatusGroup_MemoryInterface, 9), - kStatusMemoryBlankCheckFailed = MAKE_STATUS(kStatusGroup_MemoryInterface, 10), - kStatusMemoryBlankPageReadDisallowed = MAKE_STATUS(kStatusGroup_MemoryInterface, 11), - kStatusMemoryProtectedPageReadDisallowed = MAKE_STATUS(kStatusGroup_MemoryInterface, 12), - kStatusMemoryFfrSpecRegionWriteBroken = MAKE_STATUS(kStatusGroup_MemoryInterface, 13), - kStatusMemoryUnsupportedCommand = MAKE_STATUS(kStatusGroup_MemoryInterface, 14), -}; - -/*! @brief Bootloader status codes. */ -enum -{ - kStatus_UnknownCommand = MAKE_STATUS(kStatusGroup_Bootloader, 0), - kStatus_SecurityViolation = MAKE_STATUS(kStatusGroup_Bootloader, 1), - kStatus_AbortDataPhase = MAKE_STATUS(kStatusGroup_Bootloader, 2), - kStatus_Ping = MAKE_STATUS(kStatusGroup_Bootloader, 3), - kStatus_NoResponse = MAKE_STATUS(kStatusGroup_Bootloader, 4), - kStatus_NoResponseExpected = MAKE_STATUS(kStatusGroup_Bootloader, 5), - kStatus_CommandUnsupported = MAKE_STATUS(kStatusGroup_Bootloader, 6), -}; - -/*! - * @brief Interface to memory operations. - * - * This is the main abstract interface to all memory operations. - */ -typedef struct -{ - status_t (*init)(void); - status_t (*read)(uint32_t address, uint32_t length, uint8_t *buffer, uint32_t memoryId); - status_t (*write)(uint32_t address, uint32_t length, const uint8_t *buffer, uint32_t memoryId); - status_t (*fill)(uint32_t address, uint32_t length, uint32_t pattern); - status_t (*flush)(void); - status_t (*finalize)(void); - status_t (*erase)(uint32_t address, uint32_t length, uint32_t memoryId); -} memory_interface_t; - -/*! @brief Interface to memory operations for one region of memory. */ -typedef struct -{ - status_t (*init)(void); - status_t (*read)(uint32_t address, uint32_t length, uint8_t *buffer); - status_t (*write)(uint32_t address, uint32_t length, const uint8_t *buffer); - status_t (*fill)(uint32_t address, uint32_t length, uint32_t pattern); - status_t (*flush)(void); - status_t (*erase)(uint32_t address, uint32_t length); - status_t (*config)(uint32_t *buffer); - status_t (*erase_all)(void); -} memory_region_interface_t; - -//! @brief Structure of a memory map entry. -typedef struct -{ - uint32_t startAddress; - uint32_t endAddress; - uint32_t memoryProperty; - uint32_t memoryId; - const memory_region_interface_t *memoryInterface; -} memory_map_entry_t; - -/*! @brief Structure of version property. */ -typedef union StandardVersion -{ - struct - { - uint8_t bugfix; /*!< bugfix version [7:0] */ - uint8_t minor; /*!< minor version [15:8] */ - uint8_t major; /*!< major version [23:16] */ - char name; /*!< name [31:24] */ - }; - uint32_t version; /*!< combined version numbers */ -} standard_version_t; - -/*! @brief API initialization data structure */ -typedef struct kb_api_parameter_struct -{ - uint32_t allocStart; - uint32_t allocSize; -} kp_api_init_param_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -standard_version_t API_Version(void); - -/*! @brief Initialize the IAP API runtime environment */ -status_t API_Init(api_core_context_t *coreCtx, const kp_api_init_param_t *param); - -/*! @brief Deinitialize the IAP API runtime environment */ -status_t API_Deinit(api_core_context_t *coreCtx); - -/*! - * @brief Initialize memory interface. - * - * @retval #kStatus_Fail - * @retval #kStatus_Success - */ -status_t MEM_Init(api_core_context_t *coreCtx); - -/*! - * @brief Configure memory interface - * - * @param config A pointer to the storage for the driver runtime state. - * @param memoryId Indicates the index of the memory type. Please refer to "Memory group definition" - - * @retval #kStatus_Success - * @retval #kStatus_CommandUnsupported - * @retval #kStatus_InvalidArgument - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed - * @retval #kStatusMemoryRangeInvalid - * @retval #kStatus_Fail - * @retval #kStatus_OutOfRange - * @retval #kStatus_SPI_BaudrateNotSupport -*/ -status_t MEM_Config(api_core_context_t *coreCtx, uint32_t *config, uint32_t memoryId); - -/*! - * @brief Write memory. - * - * @param address The start address of the desired flash memory to be programmed. - For internal flash the address need to be 512bytes-aligned. - * @param length Number of bytes to be programmed. - * @param buffer A pointer to the source buffer of data that is to be programmed into the flash. - * @param memoryId Indicates the index of the memory type. Please refer to "Memory group definition" - * - * @retval #kStatus_Success - * @retval #kStatus_Fail - * @retval #kStatusMemoryRangeInvalid - * @retval #kStatus_CommandUnsupported - * @retval #kStatus_FLASH_AlignmentError - * @retval #kStatusMemoryCumulativeWrite - * @retval #kStatus_FLASH_InvalidArgument - * @retval #kStatus_FLASH_AddressError - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed - * @retval #kStatus_FLASH_CommandFailure - * @retval #kStatus_FLASH_CommandNotSupported - * @retval #kStatus_FLASH_EccError - * @retval #kStatus_FLASH_RegulationLoss - * @retval #kStatus_FLASH_Success - * @retval #kStatus_FLASH_ReadHidingAreaDisallowed - * @retval #kStatus_FLASH_CompareError - * @retval #kStatusMemoryNotConfigured - * @retval #kStatusMemoryVerifyFailed - */ -status_t MEM_Write( - api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, const uint8_t *buf, uint32_t memoryId); - -/*! - * @brief Fill memory with a word pattern. - * - * @param address The start address of the desired flash memory to be programmed. - * For internal flash the address need to be 512bytes-aligned. - * @param length Number of bytes to be programmed. - * @param pattern The data to be written into the specified memory area. - * - * @retval #kStatus_CommandUnsupported - * @retval #kStatus_Success - * @retval #kStatus_FLASH_AlignmentError - * @retval #kStatusMemoryCumulativeWrite - * @retval #kStatus_Fail - * @retval #kStatus_FLASH_InvalidArgument - * @retval #kStatus_FLASH_AddressError - * @retval #kStatus_FLASH_Success - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed - * @retval #kStatus_FLASH_CommandFailure - * @retval #kStatus_FLASH_CommandNotSupported - * @retval #kStatus_FLASH_EccError - * @retval #kStatus_FLASH_RegulationLoss - * @retval #kStatus_FLASH_ReadHidingAreaDisallowed - */ -status_t MEM_Fill( - api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, uint32_t pattern, uint32_t memoryId); - -/*! - * @brief Flush memory. - * - * @retval #kStatus_Success - * @retval #kStatus_Fail - * @retval #kStatusMemoryCumulativeWrite - * @retval #kStatus_FLASH_InvalidArgument - * @retval #kStatus_FLASH_AlignmentError - * @retval #kStatus_FLASH_Success - * @retval #kStatus_FLASH_AddressError - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed - * @retval #kStatus_FLASH_CommandFailure - * @retval #kStatus_FLASH_CommandNotSupported - * @retval #kStatus_FLASH_EccError - * @retval #kStatus_FLASH_RegulationLoss - * @retval #kStatus_FLASH_ReadHidingAreaDisallowed - * @retval #kStatusMemoryVerifyFailed - */ -status_t MEM_Flush(api_core_context_t *coreCtx); - -/*! - * @brief Erase memory. - * - * @param address The start address of the desired flash memory to be erased. - * @param length Number of bytes to be read. - * @param memoryId Indicates the index of the memory type. Please refer to "Memory group definition" - * - * @retval #kStatus_Success - * @retval #kStatusMemoryRangeInvalid - * @retval #kStatusMemoryAddressError - * @retval #kStatus_FLASH_InvalidArgument - * @retval #kStatus_FLASH_AlignmentError - * @retval #kStatus_FLASH_Success - * @retval #kStatus_FLASH_AddressError - * @retval #kStatus_FLASH_EraseKeyError - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed - * @retval #kStatus_Fail - * @retval #kStatus_FLASH_CommandFailure - * @retval #kStatus_FLASH_CommandNotSupported - * @retval #kStatus_FLASH_EccError - * @retval #kStatus_FLASH_RegulationLoss - * @retval #kStatusMemoryNotConfigured - * @retval #kStatusMemoryVerifyFailed - - */ -status_t MEM_Erase(api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, uint32_t memoryId); - -/*! - * @brief Erase entire memory based on memoryId - * - * @param memoryId Indicates the index of the memory type. Please refer to "Memory group definition" - * - * @retval #kStatus_Success - * @retval #kStatus_Fail - * @retval #kStatus_CommandUnsupported - * @retval #kStatus_FLASH_InvalidArgument - * @retval #kStatus_FLASH_AlignmentError - * @retval #kStatus_FLASH_Success - * @retval #kStatus_FLASH_AddressError - * @retval #kStatus_FLASH_EraseKeyError - * @retval #kStatus_FLASH_CommandFailure - * @retval #kStatus_FLASH_CommandNotSupported - * @retval #kStatus_FLASH_EccError - * @retval #kStatus_FLASH_RegulationLoss - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed - * @retval #kStatusMemoryVerifyFailed - * @retval #kStatusMemoryNotConfigured - * @retval #kStatus_InvalidArgument - */ -status_t MEM_EraseAll(api_core_context_t *coreCtx, uint32_t memoryId); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* _FSL_MEM_INTERFACE_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/fsl_sbloader.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/fsl_sbloader.h deleted file mode 100644 index cfcf2ceedea..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/fsl_sbloader.h +++ /dev/null @@ -1,373 +0,0 @@ -/* - * Copyright 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SBLOADER_H_ -#define _FSL_SBLOADER_H_ - -#include "fsl_flash.h" -#include "fsl_flexspi_nor_flash.h" -#include "fsl_sbloader_v3.h" -#include "fsl_common.h" -/*! - * @addtogroup sbloader - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Determines the version of SB loader implementation (1: sb1.0; 2: sb2.0; 3.1: sb3.1) */ -#define SB_FILE_MAJOR_VERSION (3) -#define SB_FILE_MINOR_VERSION (1) - -/*! @brief Bootloader status group numbers */ -#define kStatusGroup_SBLoader (101U) - -/*! @brief Contiguous RAM region count */ -#define RAM_REGION_COUNT (2U) - -/*! @brief Contiguous FLASH region count */ -#define FLASH_REGION_COUNT (1U) - -/*! @brief Contiguous FFR region count */ -#define FFR_REGION_COUNT (1U) - -/*! @brief Memory Interface count */ -#define MEM_INTERFACE_COUNT (4U) - -/*! @brief Contiguous FLEXSPINOR meomry count */ -#define FLEXSPINOR_REGION_COUNT (1U) - -/*! @brief SB loader status codes.*/ -enum -{ - kStatusRomLdrSectionOverrun = MAKE_STATUS(kStatusGroup_SBLoader, 0), - kStatusRomLdrSignature = MAKE_STATUS(kStatusGroup_SBLoader, 1), - kStatusRomLdrSectionLength = MAKE_STATUS(kStatusGroup_SBLoader, 2), - kStatusRomLdrUnencryptedOnly = MAKE_STATUS(kStatusGroup_SBLoader, 3), - kStatusRomLdrEOFReached = MAKE_STATUS(kStatusGroup_SBLoader, 4), - kStatusRomLdrChecksum = MAKE_STATUS(kStatusGroup_SBLoader, 5), - kStatusRomLdrCrc32Error = MAKE_STATUS(kStatusGroup_SBLoader, 6), - kStatusRomLdrUnknownCommand = MAKE_STATUS(kStatusGroup_SBLoader, 7), - kStatusRomLdrIdNotFound = MAKE_STATUS(kStatusGroup_SBLoader, 8), - kStatusRomLdrDataUnderrun = MAKE_STATUS(kStatusGroup_SBLoader, 9), - kStatusRomLdrJumpReturned = MAKE_STATUS(kStatusGroup_SBLoader, 10), - kStatusRomLdrCallFailed = MAKE_STATUS(kStatusGroup_SBLoader, 11), - kStatusRomLdrKeyNotFound = MAKE_STATUS(kStatusGroup_SBLoader, 12), - kStatusRomLdrSecureOnly = MAKE_STATUS(kStatusGroup_SBLoader, 13), - kStatusRomLdrResetReturned = MAKE_STATUS(kStatusGroup_SBLoader, 14), - - kStatusRomLdrRollbackBlocked = MAKE_STATUS(kStatusGroup_SBLoader, 15), - kStatusRomLdrInvalidSectionMacCount = MAKE_STATUS(kStatusGroup_SBLoader, 16), - kStatusRomLdrUnexpectedCommand = MAKE_STATUS(kStatusGroup_SBLoader, 17), - kStatusRomLdrBadSBKEK = MAKE_STATUS(kStatusGroup_SBLoader, 18), - kStatusRomLdrPendingJumpCommand = MAKE_STATUS(kStatusGroup_SBLoader, 19), -}; - -/*! - * @brief Defines the number of bytes in a cipher block (chunk). This is dictated by - * the encryption algorithm. - */ -#define BYTES_PER_CHUNK 16 - -#define SB_SECTION_COUNT_MAX 8 - -/*! @brief Boot image signature in 32-bit little-endian format "PMTS" */ -#define BOOT_SIGNATURE 0x504d5453 - -/*! @brief Boot image signature in 32-bit little-endian format "ltgs" */ -#define BOOT_SIGNATURE2 0x6c746773 - -/*! @brief These define file header flags */ -#define FFLG_DISPLAY_PROGRESS 0x0001 - -/*! @brief These define section header flags */ -#define SFLG_SECTION_BOOTABLE 0x0001 - -/*! @brief These define boot command flags */ -#define CFLG_LAST_TAG 0x01 - -/*! @brief ROM_ERASE_CMD flags */ -#define ROM_ERASE_ALL_MASK 0x01 -#define ROM_ERASE_ALL_UNSECURE_MASK 0x02 - -/*! @brief ROM_JUMP_CMD flags */ -#define ROM_JUMP_SP_MASK 0x02 - -/*! @brief Memory device id shift at sb command flags */ -#define ROM_MEM_DEVICE_ID_SHIFT 0x8 - -/*! @brief Memory device id mask */ -#define ROM_MEM_DEVICE_ID_MASK 0xff00 - -/*! @brief Memory group id shift at sb command flags */ -#define ROM_MEM_GROUP_ID_SHIFT 0x4 - -/*! @brief Memory group id flags mask */ -#define ROM_MEM_GROUP_ID_MASK 0xf0 - -/*! @brief ROM_PROG_CMD flags */ -#define ROM_PROG_8BYTE_MASK 0x01 - -/*! @brief These define the boot command tags */ -#define ROM_NOP_CMD 0x00 -#define ROM_TAG_CMD 0x01 -#define ROM_LOAD_CMD 0x02 -#define ROM_FILL_CMD 0x03 -#define ROM_JUMP_CMD 0x04 -#define ROM_CALL_CMD 0x05 -#define ROM_MODE_CMD 0x06 -#define ROM_ERASE_CMD 0x07 -#define ROM_RESET_CMD 0x08 -#define ROM_MEM_ENABLE_CMD 0x09 -#define ROM_PROG_CMD 0x0a -#define ROM_FW_VER_CHK 0x0b - -#if SB_FILE_MAJOR_VERSION == 2 -#define SBLOADER_CMD_SET_IN_ISP_MODE (SBLOADER_V2_CMD_SET_IN_ISP_MODE) -#define SBLOADER_CMD_SET_IN_REC_MODE (SBLOADER_V2_CMD_SET_IN_REC_MODE) -#elif SB_FILE_MAJOR_VERSION == 3 -#define SBLOADER_CMD_SET_IN_ISP_MODE (SBLOADER_V3_CMD_SET_IN_ISP_MODE) -#define SBLOADER_CMD_SET_IN_REC_MODE (SBLOADER_V3_CMD_SET_IN_REC_MODE) -#endif - -/*! @brief Plugin return codes */ -#define ROM_BOOT_SECTION_ID 1 -#define ROM_BOOT_IMAGE_ID 2 - -enum _fw_version_check_option -{ - kRomLdr_FwCheckOption_SecureVersion = 0x0U, - kRomLdr_FwCheckOption_NonSecureVersion = 0x1U, -}; - -typedef uint8_t chunk_t[BYTES_PER_CHUNK]; - -/*! @brief Boot command definition */ -typedef struct _boot_cmd -{ - uint8_t checksum; /*!< 8-bit checksum over command chunk */ - uint8_t tag; /*!< command tag (identifier) */ - uint16_t flags; /*!< command flags (modifier) */ - uint32_t address; /*!< address argument */ - uint32_t count; /*!< count argument */ - uint32_t data; /*!< data argument */ -} boot_cmd_t; - -/*! @brief Definition for boot image file header chunk 1 */ -typedef struct _boot_hdr1 -{ - uint32_t hash; /*!< last 32-bits of SHA-1 hash */ - uint32_t signature; /*!< must equal "STMP" */ - uint8_t major; /*!< major file format version */ - uint8_t minor; /*!< minor file format version */ - uint16_t fileFlags; /*!< global file flags */ - uint32_t fileChunks; /*!< total chunks in the file */ -} boot_hdr1_t; - -/*! @brief Definition for boot image file header chunk 2 */ -typedef struct _boot_hdr2 -{ - uint32_t bootOffset; /*!< chunk offset to the first boot section */ - uint32_t bootSectID; /*!< section ID of the first boot section */ - uint16_t keyCount; /*!< number of keys in the key dictionary */ - uint16_t keyOffset; /*!< chunk offset to the key dictionary */ - uint16_t hdrChunks; /*!< number of chunks in the header */ - uint16_t sectCount; /*!< number of sections in the image */ -} boot_hdr2_t; - -/*! @brief Provides forward reference to the loader context definition. */ -typedef struct _ldr_Context ldr_Context_t; - -/*! @brief Function pointer definition for all loader action functions. */ -typedef status_t (*pLdrFnc_t)(ldr_Context_t *); - -/*! @brief Jump command function pointer definition. */ -typedef status_t (*pJumpFnc_t)(uint32_t); - -/*! @brief Call command function pointer definition. */ -typedef status_t (*pCallFnc_t)(uint32_t, uint32_t *); - -/*! @brief State information for the CRC32 algorithm. */ -typedef struct Crc32Data -{ - uint32_t currentCrc; /*!< Current CRC value. */ - uint32_t byteCountCrc; /*!< Number of bytes processed. */ -} crc32_data_t; - -/*! @brief Loader context definition. */ -struct _ldr_Context -{ - pLdrFnc_t Action; /*!< pointer to loader action function */ - uint32_t fileChunks; /*!< chunks remaining in file */ - uint32_t sectChunks; /*!< chunks remaining in section */ - uint32_t bootSectChunks; /*!< number of chunks we need to complete the boot section */ - uint32_t receivedChunks; /*!< number of chunks we need to complete the boot section */ - uint16_t fileFlags; /*!< file header flags */ - uint16_t keyCount; /*!< number of keys in the key dictionary */ - uint32_t objectID; /*!< ID of the current boot section or image */ - crc32_data_t crc32; /*!< crc calculated over load command payload */ - uint8_t *src; /*!< source buffer address */ - chunk_t initVector; /*!< decryption initialization vector */ - chunk_t dek; /*!< chunk size DEK if the image is encrypted */ - chunk_t scratchPad; /*!< chunk size scratch pad area */ - boot_cmd_t bootCmd; /*!< current boot command */ - uint32_t skipCount; /*!< Number of chunks to skip */ - bool skipToEnd; /*!< true if skipping to end of file */ - - // extended for SB 2.0 - uint32_t nonce[4]; - uint32_t keyBlobBlock; - uint32_t keyBlobBlockCount; - uint8_t *keyBlobBuffer; - uint32_t offsetSignatureBytes; /*!< offset to signagure block header in bytesn */ - uint8_t *headerBuffer; -}; - -typedef struct soc_memory_map_struct -{ - struct - { - uint32_t start; - uint32_t end; - } ramRegions[RAM_REGION_COUNT]; - struct - { - uint32_t start; - uint32_t end; - } flashRegions[FLASH_REGION_COUNT]; - struct - { - uint32_t start; - uint32_t end; - } ffrRegions[FFR_REGION_COUNT]; - struct - { - uint32_t start; - uint32_t end; - } flexspiNorRegions[FLEXSPINOR_REGION_COUNT]; -} soc_mem_regions_t; - -typedef struct arena_context -{ - uint32_t start; - uint32_t end; - uint32_t nextAddr; -} arena_context_t; - -/*! @brief Memory region information table */ -typedef struct mem_region -{ - uint32_t start; - uint32_t end; -} mem_region_t; - -/*! @brief Memory Attribute Structure */ -typedef struct memory_attribute_struct -{ - uint32_t memId; - uint32_t regionCount; - mem_region_t *memRegions; - void *context; -} mem_attribute_t; - -/*! @brief Memory context structure */ -typedef struct memory_context_struct -{ - status_t (*flush)(mem_attribute_t *attr); - mem_attribute_t *attr; -} mem_context_t; - -/*! @brief Memory region interface structure */ -typedef struct api_memory_region_interface -{ - status_t (*init)(mem_attribute_t *attr); -#if ROM_API_HAS_FEATURE_MEM_READ - status_t (*read)(mem_attribute_t *attr, uint32_t addr, uint32_t leth, uint8_t *buf); -#endif - status_t (*write)(mem_attribute_t *attr, uint32_t addr, uint32_t len, const uint8_t *buf); - status_t (*fill)(mem_attribute_t *attr, uint32_t addr, uint32_t len, uint32_t pattern); - status_t (*flush)(mem_attribute_t *attr); - status_t (*erase)(mem_attribute_t *attr, uint32_t addr, uint32_t len); - status_t (*config)(mem_attribute_t *attr, uint32_t *buf); - status_t (*erase_all)(mem_attribute_t *attr); - status_t (*alloc_ctx)(arena_context_t *ctx, mem_attribute_t *attr, void *miscParams); -} api_memory_region_interface_t; - -/*! @brief Memory entry data structure */ -typedef struct memory_map_entry -{ - mem_attribute_t *memoryAttribute; - const api_memory_region_interface_t *memoryInterface; -} api_memory_map_entry_t; - -/*! @brief The API context structure */ -typedef struct api_core_context -{ - soc_mem_regions_t memRegions; - arena_context_t arenaCtx; - flash_config_t flashConfig; - flexspi_nor_config_t flexspinorCfg; - mem_context_t memCtx; - ldr_Context_v3_t *sbloaderCtx; - nboot_context_t *nbootCtx; - uint8_t *sharedBuf; - api_memory_map_entry_t memEntries[MEM_INTERFACE_COUNT]; -} api_core_context_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @brief Perform the Sbloader runtime environment initialization - * This API is used for initializing the sbloader state machine before calling - * the api_sbloader_pump. This API should be called after the iap_api_init API. - * - * @param ctx Pointer to IAP API core context structure. - * - * @retval #kStatus_Success Api was executed succesfuly. - */ -status_t Sbloader_Init(api_core_context_t *ctx); - -/*! - * @brief Handle the SB data stream - * This API is used for handling the secure binary(SB3.1 format) data stream, - * which is used for image update, lifecycle advancing, etc. - * This API should be called after the iap_api_init and api_sbloader_init APIs. - - * @param ctx Pointer to IAP API core context structure. - * @param data Pointer to source data that is the sb file buffer data. - * @param length The size of the process buffer data. - * - * @retval #kStatus_Success Api was executed succesfuly. - * @retval #kStatus_InvalidArgument An invalid argument is provided. - * @retval #kStatus_Fail API execution failed. - */ -status_t Sbloader_Pump(api_core_context_t *ctx, uint8_t *data, uint32_t length); - -/*! - * @brief Finish the sbloader handling - * The API is used for finalizing the sbloader operations. - * - * @param ctx Pointer to IAP API core context structure. - * - * @retval #kStatus_Success Api was executed succesfuly. - */ -status_t Sbloader_Finalize(api_core_context_t *ctx); - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_SBLOADER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/fsl_sbloader_v3.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/fsl_sbloader_v3.h deleted file mode 100644 index 292c9ac1ac3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/fsl_sbloader_v3.h +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_SBLOADER_V3_H_ -#define _FSL_SBLOADER_V3_H_ - -#include - -#include "fsl_nboot_hal.h" - -/*! @addtogroup sbloader */ -/*! @{ */ - -/******************************************************************************* - * Definitions - *****************************************************************************/ - -/*! - * @brief Defines the number of bytes in a cipher block (chunk). This is dictated by - * the encryption algorithm. - */ -#define SB3_BYTES_PER_CHUNK 16 - -typedef uint8_t chunk_v3_t[SB3_BYTES_PER_CHUNK]; - -typedef struct _ldr_buf ldr_buf_t; - -struct _ldr_buf -{ - chunk_v3_t data; - uint32_t fillPosition; -}; - -/*! @brief Provides forward reference to the loader context definition. */ -typedef struct _ldr_Context_v3 ldr_Context_v3_t; - -/*! @brief Function pointer definition for all loader action functions. */ -typedef status_t (*pLdrFnc_v3_t)(ldr_Context_v3_t *); - -/*! @brief sb3 section definitions */ -/*! @brief section type */ -typedef enum _sectionType -{ - kSectionNone = 0, /*!< end or invalid */ - kSectionDataRange = 1, - kSectionDiffUpdate = 2, - kSectionDDRConfig = 3, - kSectionRegister = 4, -} section_type_t; - -#define SB3_DATA_RANGE_HEADER_FLAGS_ERASE_MASK (0x1u) /*!< bit 0 */ -#define SB3_DATA_RANGE_HEADER_FLAGS_LOAD_MASK (0x2u) /*!< bit 1 */ - -/*! @brief section data range structure */ -typedef struct range_header -{ - uint32_t tag; - uint32_t startAddress; - uint32_t length; - uint32_t cmd; -} sb3_data_range_header_t; - -typedef struct range_header_expansion -{ - uint32_t memoryId; - uint32_t pad0; - uint32_t pad1; - uint32_t pad2; -} sb3_data_range_expansion_t; - -typedef struct copy_memory_expansion -{ - uint32_t destAddr; - uint32_t memoryIdFrom; - uint32_t memoryIdTo; - uint32_t pad; -} sb3_copy_memory_expansion_t; - -typedef struct copy -{ - sb3_data_range_header_t header; - sb3_copy_memory_expansion_t expansion; -} sb3_copy_memory_t; - -typedef struct load_keyblob -{ - uint32_t tag; - uint16_t offset; - uint16_t keyWrapId; - uint32_t length; - uint32_t cmd; -} sb3_load_keyblob_t; - -typedef struct fill_memory_expansion -{ - uint32_t pattern; /*!< word to be used as pattern */ - uint32_t pad0; - uint32_t pad1; - uint32_t pad2; -} sb3_fill_memory_expansion_t; - -typedef struct fill_memory -{ - sb3_data_range_header_t header; - sb3_fill_memory_expansion_t arg; -} sb3_fill_memory_t; - -typedef struct config_memory -{ - uint32_t tag; - uint32_t memoryId; - uint32_t address; /*!< address of config blob */ - uint32_t cmd; -} sb3_config_memory_t; - -enum -{ - kFwVerChk_Id_none = 0, - kFwVerChk_Id_nonsecure = 1, - kFwVerChk_Id_secure = 2, -}; - -typedef struct fw_ver_check -{ - uint32_t tag; - uint32_t version; - uint32_t id; - uint32_t cmd; -} sb3_fw_ver_check_t; - -/*! @brief sb3 DATA section header format */ -typedef struct section_header -{ - uint32_t sectionUid; - uint32_t sectionType; - uint32_t length; - uint32_t _pad; -} sb3_section_header_t; - -/*! @brief loader command enum */ -typedef enum _loader_command_sb3 -{ - kSB3_CmdInvalid = 0, - kSB3_CmdErase = 1, - kSB3_CmdLoad = 2, - kSB3_CmdExecute = 3, - kSB3_CmdCall = 4, - kSB3_CmdProgramFuse = 5, - kSB3_CmdProgramIFR = 6, - kSB3_CmdLoadCmac = 7, - kSB3_CmdCopy = 8, - kSB3_CmdLoadHashLocking = 9, - kSB3_CmdLoadKeyBlob = 10, - kSB3_CmdConfigMem = 11, - kSB3_CmdFillMem = 12, - kSB3_CmdFwVerCheck = 13, -} sb3_cmd_t; - -/*! @brief The all of the allowed command */ -#define SBLOADER_V3_CMD_SET_ALL \ - ((1u << kSB3_CmdErase) | (1u << kSB3_CmdLoad) | (1u << kSB3_CmdExecute) | (1u << kSB3_CmdCall) | \ - (1u << kSB3_CmdProgramFuse) | (1u << kSB3_CmdProgramIFR) | (1u << kSB3_CmdCopy) | (1u << kSB3_CmdLoadKeyBlob) | \ - (1u << kSB3_CmdConfigMem) | (1u << kSB3_CmdFillMem) | (1u << kSB3_CmdFwVerCheck)) -/*! @brief The allowed command set in ISP mode */ -#define SBLOADER_V3_CMD_SET_IN_ISP_MODE \ - ((1u << kSB3_CmdErase) | (1u << kSB3_CmdLoad) | (1u << kSB3_CmdExecute) | (1u << kSB3_CmdProgramFuse) | \ - (1u << kSB3_CmdProgramIFR) | (1u << kSB3_CmdCopy) | (1u << kSB3_CmdLoadKeyBlob) | (1u << kSB3_CmdConfigMem) | \ - (1u << kSB3_CmdFillMem) | (1u << kSB3_CmdFwVerCheck)) -/*! @brief The allowed command set in recovery mode */ -#define SBLOADER_V3_CMD_SET_IN_REC_MODE \ - ((1u << kSB3_CmdErase) | (1u << kSB3_CmdLoad) | (1u << kSB3_CmdExecute) | (1u << kSB3_CmdProgramFuse) | \ - (1u << kSB3_CmdProgramIFR) | (1u << kSB3_CmdCopy) | (1u << kSB3_CmdLoadKeyBlob) | (1u << kSB3_CmdConfigMem) | \ - (1u << kSB3_CmdFillMem) | (1u << kSB3_CmdFwVerCheck)) - -#define SB3_DATA_BUFFER_SIZE_IN_BYTE (MAX(128, NBOOT_KEY_BLOB_SIZE_IN_BYTE_MAX)) - -/*! @brief Memory region definition. */ -typedef struct -{ - uint32_t address; - uint32_t length; -} kb_region_t; - -/*! - * @brief Details of the operation to be performed by the ROM. - * - * The #kRomAuthenticateImage operation requires the entire signed image to be - * available to the application. - */ -typedef enum -{ - kRomAuthenticateImage = 1, /*!< Authenticate a signed image. */ - kRomLoadImage = 2, /*!< Load SB file. */ - kRomOperationCount = 3, -} kb_operation_t; - -typedef struct -{ - uint32_t profile; - uint32_t minBuildNumber; - uint32_t overrideSBBootSectionID; - uint32_t *userSBKEK; - uint32_t regionCount; - const kb_region_t *regions; -} kb_load_sb_t; - -typedef struct -{ - uint32_t profile; - uint32_t minBuildNumber; - uint32_t maxImageLength; - uint32_t *userRHK; -} kb_authenticate_t; - -typedef struct -{ - uint32_t version; /*!< Should be set to #kKbootApiVersion. */ - uint8_t *buffer; /*!< Caller-provided buffer used by Kboot. */ - uint32_t bufferLength; - kb_operation_t op; - union - { - kb_authenticate_t authenticate; /*!< Settings for #kKbootAuthenticate operation.*/ - kb_load_sb_t loadSB; /*!< Settings for #kKbootLoadSB operation.*/ - }; -} kb_options_t; - -/*! @brief Loader context definition. */ -struct _ldr_Context_v3 -{ - pLdrFnc_v3_t Action; /*!< pointer to loader action function */ - uint32_t block_size; /*!< size of each block in bytes */ - uint32_t block_data_size; /*!< data size in bytes (NBOOT_SB3_CHUNK_SIZE_IN_BYTES) */ - uint32_t block_data_total; /*!< data max size in bytes (block_size * data_size */ - uint32_t block_buffer_size; /*!< block0 and block size */ - uint32_t block_buffer_position; - uint8_t block_buffer[MAX(NBOOT_SB3_MANIFEST_MAX_SIZE_IN_BYTES, - NBOOT_SB3_BLOCK_MAX_SIZE_IN_BYTES)]; /*! will be used for both block0 and blockx */ - uint32_t processedBlocks; - - uint8_t data_block_offset; /*! data block offset in a block. */ - bool in_data_block; /*!< in progress of handling a data block within a block */ - uint8_t *data_block; - uint32_t data_block_position; - - bool in_data_section; /*!< in progress of handling a data section within a data block */ - uint32_t data_section_handled; - sb3_section_header_t data_section_header; - - bool in_data_range; /*!< in progress of handling a data range within a data section */ - uint32_t data_range_handled; - uint32_t data_range_gap; - sb3_data_range_header_t data_range_header; - bool has_data_range_expansion; - sb3_data_range_expansion_t data_range_expansion; - - uint32_t commandSet; /*!< support command set during sb file handling */ - - uint32_t data_position; - uint8_t data_buffer[SB3_DATA_BUFFER_SIZE_IN_BYTE]; /*!< temporary data buffer */ - - kb_options_t fromAPI; /*!< options from ROM API */ -}; - -/*! @} */ - -#endif /* _FSL_SBLOADER_V3_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/src/fsl_mem_interface.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/src/fsl_mem_interface.c deleted file mode 100644 index a863327e87e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/src/fsl_mem_interface.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_flash.h" -#include "fsl_flash_ffr.h" -#include "fsl_flexspi_nor_flash.h" -#include "fsl_mem_interface.h" - -/*! @brief Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.memInterface" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define API_INTERFACE ((api_core_interface_t *)0x1302fcb4U) - -/*! @brief IAP API Interface structure */ -typedef struct iap_api_interface_struct -{ - standard_version_t version; /*!< IAP API version number. */ - status_t (*api_init)(api_core_context_t *coreCtx, const kp_api_init_param_t *param); - status_t (*api_deinit)(api_core_context_t *coreCtx); - status_t (*mem_init)(api_core_context_t *ctx); - const uint32_t reserved; - status_t (*mem_write)(api_core_context_t *ctx, uint32_t addr, uint32_t len, const uint8_t *buf, uint32_t memoryId); - status_t (*mem_fill)(api_core_context_t *ctx, uint32_t addr, uint32_t len, uint32_t pattern, uint32_t memoryId); - status_t (*mem_flush)(api_core_context_t *ctx); - status_t (*mem_erase)(api_core_context_t *ctx, uint32_t addr, uint32_t len, uint32_t memoryId); - status_t (*mem_config)(api_core_context_t *ctx, uint32_t *buf, uint32_t memoryId); - status_t (*mem_erase_all)(api_core_context_t *ctx, uint32_t memoryId); - status_t (*sbloader_init)(api_core_context_t *ctx); - status_t (*sbloader_pump)(api_core_context_t *ctx, uint8_t *data, uint32_t length); - status_t (*sbloader_finalize)(api_core_context_t *ctx); -} api_core_interface_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -standard_version_t API_Version(void) -{ - assert(API_INTERFACE); - return API_INTERFACE->version; -} - -/*! @brief Initialize the IAP API runtime environment */ -status_t API_Init(api_core_context_t *coreCtx, const kp_api_init_param_t *param) -{ - assert(API_INTERFACE); - return API_INTERFACE->api_init(coreCtx, param); -} - -/*! @brief Deinitialize the IAP API runtime environment */ -status_t API_Deinit(api_core_context_t *coreCtx) -{ - assert(API_INTERFACE); - return API_INTERFACE->api_deinit(coreCtx); -} - -/*! @brief Intialize the memory interface of the IAP API */ -status_t MEM_Init(api_core_context_t *coreCtx) -{ - assert(API_INTERFACE); - return API_INTERFACE->mem_init(coreCtx); -} - -/*! @brief Perform the memory write operation */ -status_t MEM_Write( - api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, const uint8_t *buf, uint32_t memoryId) -{ - assert(API_INTERFACE); - return API_INTERFACE->mem_write(coreCtx, start, lengthInBytes, buf, memoryId); -} - -/*! @brief Perform the Fill operation */ -status_t MEM_Fill( - api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, uint32_t pattern, uint32_t memoryId) -{ - assert(API_INTERFACE); - return API_INTERFACE->mem_fill(coreCtx, start, lengthInBytes, pattern, memoryId); -} - -/*! @brief Perform the Memory erase operation */ -status_t MEM_Erase(api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, uint32_t memoryId) -{ - assert(API_INTERFACE); - return API_INTERFACE->mem_erase(coreCtx, start, lengthInBytes, memoryId); -} -/*! @brief Perform the full Memory erase operation */ -status_t MEM_EraseAll(api_core_context_t *coreCtx, uint32_t memoryId) -{ - assert(API_INTERFACE); - return API_INTERFACE->mem_erase_all(coreCtx, memoryId); -} - -/*! @brief Perform the Memory configuration operation */ -status_t MEM_Config(api_core_context_t *coreCtx, uint32_t *config, uint32_t memoryId) -{ - assert(API_INTERFACE); - return API_INTERFACE->mem_config(coreCtx, config, memoryId); -} - -/*! @brief Perform the Memory Flush operation */ -status_t MEM_Flush(api_core_context_t *coreCtx) -{ - assert(API_INTERFACE); - return API_INTERFACE->mem_flush(coreCtx); -} - -/*! @brief Perform the Sbloader runtime environment initialization */ -status_t Sbloader_Init(api_core_context_t *ctx) -{ - assert(API_INTERFACE); - return API_INTERFACE->sbloader_init(ctx); -} - -/*! @brief Handle the SB data stream */ -status_t Sbloader_Pump(api_core_context_t *ctx, uint8_t *data, uint32_t length) -{ - assert(API_INTERFACE); - return API_INTERFACE->sbloader_pump(ctx, data, length); -} -/*! @brief Finish the sbloader handling */ -status_t Sbloader_Finalize(api_core_context_t *ctx) -{ - assert(API_INTERFACE); - return API_INTERFACE->sbloader_finalize(ctx); -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/nboot/fsl_nboot.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/nboot/fsl_nboot.h deleted file mode 100644 index 64b50d793f1..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/nboot/fsl_nboot.h +++ /dev/null @@ -1,339 +0,0 @@ -/* - * Copyright 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_NBOOT_H_ -#define _FSL_NBOOT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup nboot - * @{ - */ -/******************************************************************************* - * Definitions - ******************************************************************************/ -/** @def NXPCLHASH_WA_SIZE_MAX - * @brief Define the max workarea size required for this component - */ -#define NXPCLHASH_WA_SIZE_MAX (128U+64U) -#define NBOOT_ROOT_CERT_COUNT (4U) -#define NXPCLCSS_HASH_RTF_OUTPUT_SIZE_HAL ((size_t) 32U) ///< Size of RTF appendix to hash output buffer, in bytes - -#define NBOOT_KEYINFO_WORDLEN (23U) -#define NBOOT_CONTEXT_BYTELEN (192U + NXPCLHASH_WA_SIZE_MAX) -#define NBOOT_CONTEXT_WORDLEN (NBOOT_CONTEXT_BYTELEN/sizeof(uint32_t)) -typedef int romapi_status_t; - -/*! - * @brief NBOOT type for the root key usage - * - * This type defines the NBOOT root key usage; - * any other value means the root key is not valid (treat as if revoked). - */ -#define kNBOOT_RootKeyUsage_DebugCA_ImageCA_FwCA_ImageKey_FwKey (0x0U) -#define kNBOOT_RootKeyUsage_DebugCA (0x1U) -#define kNBOOT_RootKeyUsage_ImageCA_FwCA (0x2U) -#define kNBOOT_RootKeyUsage_DebugCA_ImageCA_FwCA (0x3U) -#define kNBOOT_RootKeyUsage_ImageKey_FwKey (0x4U) -#define kNBOOT_RootKeyUsage_ImageKey (0x5U) -#define kNBOOT_RootKeyUsage_FwKey (0x6U) -#define kNBOOT_RootKeyUsage_Unused (0x7U) -typedef uint32_t nboot_root_key_usage_t; - -/*! - * @brief NBOOT type for the root key revocation - * - * This type defines the NBOOT root key revocation; - * any other value means the root key is revoked. - */ -#define kNBOOT_RootKey_Enabled (0xAAU) -#define kNBOOT_RootKey_Revoked (0xBBU) -typedef uint32_t nboot_root_key_revocation_t; - -/*! - * @brief NBOOT type specifying the elliptic curve to be used - * - * This type defines the elliptic curve type and length - */ -#define kNBOOT_RootKey_Ecdsa_P256 (0x0000FE01U) -#define kNBOOT_RootKey_Ecdsa_P384 (0x0000FD02U) -typedef uint32_t nboot_root_key_type_and_length_t; - -/*! @brief Enumeration for SoC Lifecycle. */ -#define nboot_lc_nxpBlank (0xFFFF0000U) -#define nboot_lc_nxpFab (0xFFFE0001U) -#define nboot_lc_nxpDev (0xFF0300FCU) -#define nboot_lc_nxpProvisioned (0xFFFC0003U) -#define nboot_lc_oemOpen (0xFFFC0003U) -#define nboot_lc_oemSecureWorld (0xFFF80007U) -#define nboot_lc_oemClosed (0xFFF0000FU) -#define nboot_lc_oemLocked (0xFF3000CFU) -#define nboot_lc_oemFieldReturn (0xFFE0001FU) -#define nboot_lc_nxpFieldReturn (0xFF80007FU) -#define nboot_lc_shredded (0xFF0000FFU) -typedef uint32_t nboot_soc_lifecycle_t; - -/*! @brief Type for nboot status codes */ -typedef uint32_t nboot_status_t; - -/*! @brief Type for nboot protected status codes */ -typedef uint64_t nboot_status_protected_t; - -/*! - * @brief nboot status codes. - */ -enum -{ - kStatus_NBOOT_Success = 0x5A5A5A5AU, /*!< Operation completed successfully. */ - kStatus_NBOOT_Fail = 0x5A5AA5A5U, /*!< Operation failed. */ - kStatus_NBOOT_InvalidArgument = 0x5A5AA5F0U, /*!< Invalid argument passed to the function. */ - kStatus_NBOOT_RequestTimeout = 0x5A5AA5E1U, /*!< Operation timed out. */ - kStatus_NBOOT_KeyNotLoaded = 0x5A5AA5E2U, /*!< The requested key is not loaded. */ - kStatus_NBOOT_AuthFail = 0x5A5AA5E4U, /*!< Authentication failed. */ - kStatus_NBOOT_OperationNotAvaialable = 0x5A5AA5E5U, /*!< Operation not available on this HW. */ - kStatus_NBOOT_KeyNotAvailable = 0x5A5AA5E6U, /*!< Key is not avaialble. */ - kStatus_NBOOT_IvCounterOverflow = 0x5A5AA5E7U, /*!< Overflow of IV counter (PRINCE/IPED). */ - kStatus_NBOOT_SelftestFail = 0x5A5AA5E8U, /*!< FIPS self-test failure. */ - kStatus_NBOOT_InvalidDataFormat = 0x5A5AA5E9U, /*!< Invalid data format for example antipole */ - kStatus_NBOOT_IskCertUserDataTooBig = 0x5A5AA5EAU, /*!< Size of User data in ISK certificate is greater than 96 bytes */ - kStatus_NBOOT_IskCertSignatureOffsetTooSmall = 0x5A5AA5EBU, /*!< Signature offset in ISK certificate is smaller than expected */ - kStatus_NBOOT_MemcpyFail =0x5A5A845AU, /*!< Unexpected error detected during nboot_memcpy() */ -}; - -/*! @brief Data structure holding secure counter value used by nboot library */ -typedef struct _nboot_secure_counter -{ - uint32_t sc; - uint32_t scAp; -} nboot_secure_counter_t; - -/*! - * @brief NBOOT context type - * - * This type defines the NBOOT context - * - */ -typedef struct _nboot_context -{ - uint32_t totalBlocks; /*!< holds number of SB3 blocks. Initialized by nboot_sb3_load_header(). */ - uint32_t processData; /*!< flag, initialized by nboot_sb3_load_header(). - SB3 related flag set by NBOOT in case the nboot_sb3_load_block() - provides plain data to output buffer (for processing by ROM SB3 loader */ - uint32_t timeout; /*!< timeout value for css operation. In case it is 0, infinite wait is performed */ - uint32_t keyinfo[NBOOT_KEYINFO_WORDLEN]; /*!< data for NBOOT key management. */ - uint32_t context[NBOOT_CONTEXT_WORDLEN]; /*!< work area for NBOOT lib. */ - uint32_t uuid[4]; /*!< holds UUID value from NMPA */ - uint32_t prngReadyFlag; /*!< flag, used by nboot_rng_generate_lq_random() to determine whether CSS is ready to generate rnd number */ - uint32_t multipartMacBuffer[1024/sizeof(uint32_t)]; - uint32_t oemShareValidFlag; /*!< flag, used during TP to determine whether valid oemShare was set by nboot_tp_isp_gen_oem_master_share() */ - uint32_t oemShare[4]; /*!< buffer to store OEM_SHARE computed by nxpCLTrustProv_nboot_isp_gen_oem_master_share() */ - nboot_secure_counter_t secureCounter; /*!< Secure counter used by nboot */ - uint32_t rtf[NXPCLCSS_HASH_RTF_OUTPUT_SIZE_HAL/sizeof(uint32_t)]; - uint32_t imageHash[48/sizeof(uint32_t)]; - uint32_t authStatus; -} nboot_context_t; - -/*! - * @brief NBOOT type for the root of trust parameters - * - * This type defines the NBOOT root of trust parameters - * - */ -typedef struct _nboot_rot_auth_parms -{ - /* trusted information originated from CFPA */ - nboot_root_key_revocation_t soc_rootKeyRevocation[NBOOT_ROOT_CERT_COUNT]; /*!< Provided by caller based on NVM information in CFPA: ROTKH_REVOKE */ - uint32_t soc_imageKeyRevocation; /*!< Provided by caller based on NVM information in CFPA: IMAGE_KEY_REVOKE */ - - /* trusted information originated from CMPA */ - uint32_t soc_rkh[12]; /*!< Provided by caller based on NVM information in CMPA: ROTKH (hash of hashes) */ - /*!< In case of kNBOOT_RootKey_Ecdsa_P384, sock_rkh[0..11] are used */ - /*!< In case of kNBOOT_RootKey_Ecdsa_P256, sock_rkh[0..7] are used */ - - uint32_t soc_numberOfRootKeys; /*!< unsigned int, between minimum = 1 and maximum = 4; */ - nboot_root_key_usage_t soc_rootKeyUsage[NBOOT_ROOT_CERT_COUNT]; /*!< CMPA */ - nboot_root_key_type_and_length_t soc_rootKeyTypeAndLength; /*!< static selection between ECDSA P-256 or ECDSA P-384 based root keys */ - - /* trusted information originated from OTP fuses */ - nboot_soc_lifecycle_t soc_lifecycle; -} nboot_rot_auth_parms_t; - -/*! - * @brief manifest loading parameters - * - * This type defines the NBOOT SB3.1 manifest loading parameters - * - */typedef struct _nboot_sb3_load_manifest_parms -{ - nboot_rot_auth_parms_t soc_RoTNVM; /*!< trusted information originated from CFPA and NMPA */ - uint32_t soc_trustedFirmwareVersion; /*!< Provided by caller based on NVM information in CFPA: Secure_FW_Version */ - uint8_t pckBlob[48]; -} nboot_sb3_load_manifest_parms_t; - -/*! - * @brief Data structure holding input arguments to POR secure boot (authentication) algorithm. - * Shall be read from SoC trusted NVM or SoC fuses. - */ -typedef struct _nboot_img_auth_ecdsa_parms -{ - nboot_rot_auth_parms_t soc_RoTNVM; /*!< trusted information originated from CFPA and NMPA */ - uint32_t soc_trustedFirmwareVersion; /*!< Provided by caller based on NVM information in CFPA: Secure_FW_Version */ -} nboot_img_auth_ecdsa_parms_t; - -/*! @brief Data structure holding input arguments for CMAC authentication */ -typedef struct _nboot_cmac_authenticate_parms -{ - uint32_t expectedMAC[4]; /*!< expected MAC result */ -} nboot_img_authenticate_cmac_parms_t; - -/*! - * @brief Boolean type for the NBOOT functions - * - * This type defines boolean values used by NBOOT functions that are not easily disturbed by Fault Attacks - */ -typedef enum _nboot_bool -{ - kNBOOT_TRUE = 0x3C5AC33CU, /*!< Value for TRUE. */ - kNBOOT_TRUE256 = 0x3C5AC35AU, /*!< Value for TRUE when P256 was used to sign the image. */ - kNBOOT_TRUE384 = 0x3C5AC3A5U, /*!< Value for TRUE when P384 was used to sign the image. */ - kNBOOT_FALSE = 0x5AA55AA5U, /*!< Value for FALSE. */ - kNBOOT_OperationAllowed = 0x3c5a33ccU, - kNBOOT_OperationDisallowed = 0x5aa5cc33U, -} nboot_bool_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @brief This API function is used to generate random number with specified length. - * - * @param output Pointer to random number buffer - * @param outputByteLen length of generated random number in bytes. Length has to be in range <1, 2^16> - * - * @retval #kStatus_NBOOT_InvalidArgument Invalid input parameters (Input pointers points to NULL or length is invalid) - * @retval #kStatus_NBOOT_Success Operation successfully finished - * @retval #kStatus_NBOOT_Fail Error occured during operation - */ -status_t NBOOT_GenerateRandom(uint8_t *output, size_t outputByteLen); - -/*! - * @brief The function is used for initializing of the nboot context data structure. - * It should be called prior to any other calls of nboot API. - * - * @param nbootCtx Pointer to nboot_context_t structure. - * - * @retval #kStatus_NBOOT_Success Operation successfully finished - * @retval #kStatus_NBOOT_Fail Error occured during operation -*/ -nboot_status_t NBOOT_ContextInit(nboot_context_t *context); - -/*! - * @brief The function is used to deinitialize nboot context data structure. - * Its contents are overwritten with random data so that any sensitive data does not remain in memory. - * - * @param context Pointer to nboot_context_t structure. - - * @retval #kStatus_NBOOT_Success Operation successfully finished - * @retval #kStatus_NBOOT_Fail Error occured during operation - */ -nboot_status_t NBOOT_ContextDeinit(nboot_context_t *context); - -/*! - * @brief Verify NBOOT SB3.1 manifest (header message) - * - * This function verifies the NBOOT SB3.1 manifest (header message), initializes - * the context and loads keys into the CSS key store so that they can be used by nboot_sb3_load_block - * function. The NBOOT context has to be initialized by the function nboot_context_init before calling - * this function. Please note that this API is intended to be used only by users who needs to split - * FW update process (loading of SB3.1 file) to partial steps to customize whole operation. - * For regular SB3.1 processing, please use API described in chapter ¡°SBloader APIs¡±. - * - * @param nbootCtx Pointer to nboot_context_t structure. - * @param manifest Pointer to the input manifest buffer - * @param params additional input parameters. Please refer to nboot_sb3_load_manifest_parms_t definition for details. - * - * @retval #kStatus_NBOOT_Success Operation successfully finished - * @retval #kStatus_NBOOT_Fail Error occured during operation - */ -nboot_status_protected_t NBOOT_Sb3LoadManifest(nboot_context_t *context, - uint32_t *manifest, - nboot_sb3_load_manifest_parms_t *parms); - -/*! - * @brief Verify NBOOT SB3.1 block - * - * This function verifies and decrypts an NBOOT SB3.1 block. Decryption is performed in-place. - * The NBOOT context has to be initialized by the function nboot_context_init before calling this function. - * Please note that this API is intended to be used only by users who needs to split FW update process - * (loading of SB3.1 file) to partial steps to customize whole operation. For regular SB3.1 processing, - * please use API described in chapter ¡°SBloader APIs¡±. - * - * @param context Pointer to nboot_context_t structure. - * @param block Pointer to the input SB3.1 data block - * - * @retval #kStatus_NBOOT_Success successfully finished - * @retval #kStatus_NBOOT_Fail occured during operation -*/ - nboot_status_protected_t NBOOT_Sb3LoadBlock(nboot_context_t *context, uint32_t *block); - -/*! - * @brief This function authenticates image with asymmetric cryptography. - * The NBOOT context has to be initialized by the function nboot_context_init - * before calling this function. - * - * @param context Pointer to nboot_context_t structure. - * @param imageStartAddress Pointer to start of the image in memory. - * @param isSignatureVerified Pointer to memory holding function call result. - * After the function returns, the value will be set to kNBOOT_TRUE when the image is authentic. - * Any other value means the authentication does not pass. - * - * @param parms Pointer to a data structure in trusted memory, holding input parameters for the algorithm. - * The data structure shall be correctly filled before the function call. - * - * @retval #kStatus_NBOOT_Success Operation successfully finished - * @retval #kStatus_NBOOT_Fail Returned in all other cases. Doesn't always mean invalid image, - * it could also mean transient error caused by short time environmental conditions. -*/ -nboot_status_protected_t NBOOT_ImgAuthenticateEcdsa(nboot_context_t *context, - uint8_t imageStartAddress[], - nboot_bool_t *isSignatureVerified, - nboot_img_auth_ecdsa_parms_t *parms); - -/*! - * @brief This function calculates the CMAC over the given image and compares it to the expected value. - * To be more resistant against SPA, it is recommended that imageStartAddress is word aligned. - * The NBOOT context has to be initialized by the nboot_context_init() before calling this function. - * - * @param context Pointer to nboot_context_t structure. - * @param imageStartAddress Pointer to start of the image in memory. - * @param isSignatureVerified Pointer to memory holding function call result. - After the function returns, the value will be set to - * @param parms Pointer to a data structure in trusted memory, holding the reference MAC. - The data structure shall be correctly filled before the function call. - * - * @retval kStatus_NBOOT_Success - * @retval kStatus_NBOOT_Fail - */ -nboot_status_protected_t NBOOT_ImgAuthenticateCmac(nboot_context_t *context, - uint8_t imageStartAddress[], - nboot_bool_t *isSignatureVerified, - nboot_img_authenticate_cmac_parms_t *parms); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* _FSL_NBOOT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/nboot/fsl_nboot_hal.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/nboot/fsl_nboot_hal.h deleted file mode 100644 index acd4701046b..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/nboot/fsl_nboot_hal.h +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_NBOOT_HAL_H_ -#define _FSL_NBOOT_HAL_H_ - -#include "fsl_nboot.h" - -/*! @addtogroup nbot_hal */ -/*! @{ */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief The size of the UUID. */ -#define NBOOT_UUID_SIZE_IN_WORD (4) -#define NBOOT_UUID_SIZE_IN_BYTE (NBOOT_UUID_SIZE_IN_WORD * 4) - -/*! @brief The size of the PUF activation code. */ -#define NBOOT_PUF_AC_SIZE_IN_BYTE (996) -/*! @brief The size of the PUF key code. */ -#define NBOOT_PUF_KC_SIZE_IN_BYTE (84) - -/*! @brief The size of the key store. */ -#define NBOOT_KEY_STORE_SIZE_IN_BYTE (NBOOT_PUF_AC_SIZE_IN_BYTE + 8) - -/*! @brief The size of the root of trust key table hash. */ -#define NBOOT_ROOT_ROTKH_SIZE_IN_WORD (12) -#define NBOOT_ROOT_ROTKH_SIZE_IN_BYTE (NBOOT_ROOT_ROTKH_SIZE_IN_WORD * 4) - -/*! @brief The size of the blob with Key Blob. */ -#define NBOOT_KEY_BLOB_SIZE_IN_BYTE_256 (32) -#define NBOOT_KEY_BLOB_SIZE_IN_BYTE_384 (48) -#define NBOOT_KEY_BLOB_SIZE_IN_BYTE_MAX (NBOOT_KEY_BLOB_SIZE_IN_BYTE_384) - -/*! @brief The mask of the value of the debug state . */ -#define NBOOT_DBG_AUTH_DBG_STATE_MASK (0x0000FFFFu) -/*! @brief The shift inverted value of the debug state. */ -#define NBOOT_DBG_AUTH_DBG_STATE_SHIFT (16) -/*! @brief The value with all debug feature disabled. */ -#define NBOOT_DBG_AUTH_DBG_STATE_ALL_DISABLED (0xFFFF0000u) - -#define NBOOT_ROOT_OF_TRUST_HASH_SIZE_IN_BYTES (48u) - -#define NBOOT_EC_COORDINATE_384_SIZE_IN_BYTES (48u) -#define NBOOT_EC_COORDINATE_MAX_SIZE NBOOT_EC_COORDINATE_384_SIZE_IN_BYTES - -/* SB3.1 */ -#define NBOOT_SB3_CHUNK_SIZE_IN_BYTES (256u) -#define NBOOT_SB3_BLOCK_HASH256_SIZE_IN_BYTES (32u) -#define NBOOT_SB3_BLOCK_HASH384_SIZE_IN_BYTES (48u) - -/*! - * @brief NBOOT type for a timestamp - * - * This type defines the NBOOT timestamp - * - */ -typedef uint32_t nboot_timestamp_t[2]; - -/*! - * @brief NBOOT SB3.1 header type - * - * This type defines the header used in the SB3.1 manifest - * - */ -typedef struct _nboot_sb3_header -{ - uint32_t magic; /*!< offset 0x00: Fixed 4-byte string of 'sbv3' without the trailing NULL */ - uint32_t formatVersion; /*!< offset 0x04: (major = 3, minor = 1); The format version determines the manifest - (block0) size. */ - uint32_t flags; /*!< offset 0x08: not defined yet, keep zero for future compatibility */ - uint32_t blockCount; /*!< offset 0x0C: Number of blocks not including the manifest (block0). */ - uint32_t - blockSize; /*!< offset 0x10: Size in bytes of data block (repeated blockCount times for SB3 data stream). */ - nboot_timestamp_t timeStamp; /*!< offset 0x14: 64-bit value used as key derivation data. */ - uint32_t firmwareVersion; /*!< offset 0x1c: Version number of the included firmware */ - uint32_t imageTotalLength; /*!< offset 0x20: Total manifest length in bytes, including signatures etc. */ - uint32_t imageType; /*!< offset 0x24: image type and flags */ - uint32_t certificateBlockOffset; /*!< offset 0x28: Offset from start of header block to the certificate block. */ - uint8_t description[16]; /*!< offset 0x32: This field provides description of the file. It is an arbitrary - string injected by the signing tool, which helps to identify the file. */ -} nboot_sb3_header_t; - -/*! - * @brief NBOOT type for the header of the certificate block - * - * This type defines the NBOOT header of the certificate block, it is part of the nboot_certificate_block_t - * - */ -typedef struct _nboot_certificate_header_block -{ - uint32_t magic; /*!< magic number. */ - uint32_t formatMajorMinorVersion; /*!< format major minor version */ - uint32_t certBlockSize; /*!< Size of the full certificate block */ -} nboot_certificate_header_block_t; - -typedef uint8_t nboot_ctrk_hash_t[NBOOT_ROOT_OF_TRUST_HASH_SIZE_IN_BYTES]; - -/*! - * @brief NBOOT type for the hash table - * - * This type defines the NBOOT hash table - * - */ -typedef struct _nboot_ctrk_hash_table -{ - nboot_ctrk_hash_t ctrkHashTable[NBOOT_ROOT_CERT_COUNT]; -} nboot_ctrk_hash_table_t; - -/*! - * @brief NBOOT type for an ECC coordinate - * - * This type defines the NBOOT ECC coordinate type - * - */ -typedef uint8_t - nboot_ecc_coordinate_t[NBOOT_EC_COORDINATE_MAX_SIZE]; /*!< ECC point coordinate, up to 384-bits. big endian. */ - -/*! - * @brief NBOOT type for an ECC point - * - * This type defines the NBOOT ECC point type - */ -typedef struct -{ - nboot_ecc_coordinate_t x; /*!< x portion of the ECDSA public key, up to 384-bits. big endian. */ - nboot_ecc_coordinate_t y; /*!< y portion of the ECDSA public key, up to 384-bits. big endian. */ -} nboot_ecdsa_public_key_t; - -/*! - * @brief NBOOT type for the root certificate block - * - * This type defines the NBOOT root certificate block, it is part of the nboot_certificate_block_t - */ -typedef struct _nboot_root_certificate_block -{ - uint32_t flags; /*!< root certificate flags */ - nboot_ctrk_hash_table_t ctrkHashTable; /*!< hash table */ - nboot_ecdsa_public_key_t rootPublicKey; /*!< root public key */ -} nboot_root_certificate_block_t; - -/*! - * @brief NBOOT type for an ECC signature - * - * This type defines the NBOOT ECC signature type - */ -typedef struct -{ - nboot_ecc_coordinate_t r; /*!< r portion of the ECDSA signature, up to 384-bits. big endian. */ - nboot_ecc_coordinate_t s; /*!< s portion of the ECDSA signature, up to 384-bits. big endian. */ -} nboot_ecdsa_signature_t; - -/*! - * @brief NBOOT type for the isk block - * - * This type defines the constant length part of an NBOOT isk block - */ -typedef struct -{ - uint32_t signatureOffset; /*!< Offset of signature in ISK block. */ - uint32_t constraints; /*!< Version number of signing certificate. */ - uint32_t iskFlags; /*!< Reserved for definiton of ISK certificate flags. */ - nboot_ecdsa_public_key_t - iskPubKey; /*!< Public key of signing certificate. Variable length; only used to determine start address*/ - nboot_ecdsa_public_key_t userData; /*!< Space for at lest one addition public key*/ - nboot_ecdsa_signature_t iskSign; /*!< ISK signature*/ -} nboot_isk_block_t; - -/*! - * @brief NBOOT type for the certificate block - * - * This type defines the constant length part of an NBOOT certificate block - */ -typedef struct _nboot_certificate_block -{ - nboot_certificate_header_block_t header; - nboot_root_certificate_block_t rootCertBlock; /*! Details of selected root certificate (root certificate which will - be used for ISK signing/SB3 header signing) */ - nboot_isk_block_t iskBlock; -} nboot_certificate_block_t; - -#define NBOOT_SB3_MANIFEST_MAX_SIZE_IN_BYTES \ - (sizeof(nboot_sb3_header_t) + NBOOT_SB3_BLOCK_HASH384_SIZE_IN_BYTES + sizeof(nboot_certificate_block_t) + \ - NBOOT_EC_COORDINATE_MAX_SIZE * 2) -#define NBOOT_SB3_BLOCK_MAX_SIZE_IN_BYTES \ - (4 /* blockNumber */ + NBOOT_SB3_BLOCK_HASH384_SIZE_IN_BYTES + NBOOT_SB3_CHUNK_SIZE_IN_BYTES) - -/*! @brief The size of the DICE certificate. */ -#define NBOOT_DICE_CSR_SIZE_IN_WORD (36) -#define NBOOT_DICE_CSR_SIZE_IN_BYTES (NBOOT_DICE_CSR_SIZE_IN_WORD * 4) - -/*! @brief The physical address to put the DICE certificate. */ -#define NBOOT_DICE_CSR_ADDRESS (0x30000000u) - -/*! @brief The offset for the PRCINE/IPED erase region return by nboot mem checker. */ -#define NBOOT_IPED_IV_OFFSET (3U) - -#define NBOOT_IMAGE_CMAC_UPDATE_NONE (0u) -#define NBOOT_IMAGE_CMAC_UPDATE_INDEX0 (1u) -#define NBOOT_IMAGE_CMAC_UPDATE_INDEX1 (2u) -#define NBOOT_IMAGE_CMAC_UPDATE_BOTH (3u) -#define NBOOT_IMAGE_CMAC_UPDATE_MASK (3u) - -#define NBOOT_CMPA_CMAC_UPDATE_MASK (0x1Cu) -#define NBOOT_CMPA_CMAC_UPDATE_SHIFT (0x2u) - -#define NBOOT_CMPA_UPDATE_CMAC_PFR (0x2u) -#define NBOOT_CMPA_UPDATE_CMAC_PFR_OTP_OEM_SECURE (0x3u) -#define NBOOT_CMPA_UPDATE_CMAC_PFR_OTP_OEM_CLOSE (0x5u) -#define NBOOT_CMPA_UPDATE_CMAC_PFR_OTP_OEM_LOCKED (0x6u) - -/*! @brief Algorithm used for nboot HASH operation */ -typedef enum _nboot_hash_algo_t -{ - kHASH_Sha1 = 1, /*!< SHA_1 */ - kHASH_Sha256 = 2, /*!< SHA_256 */ - kHASH_Sha512 = 3, /*!< SHA_512 */ - kHASH_Aes = 4, /*!< AES */ - kHASH_AesIcb = 5, /*!< AES_ICB */ -} nboot_hash_algo_t; - -/*! @} */ - -#endif /*_FSL_NBOOT_HAL_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/runbootloader/fsl_runbootloader.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/runbootloader/fsl_runbootloader.h deleted file mode 100644 index 104cfbb770c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/runbootloader/fsl_runbootloader.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_RUN_BOOTLOADER_H_ -#define _FSL_RUN_BOOTLOADER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup runbootloader - * @{ - */ -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* API prototype fields definition. -| 31 : 24 | 23 : 20 | 19 : 16 | 15 : 12 | 11 : 8 | 7 ： 0 | - | Tag | Boot mode | bootloader periphal| Instance | Image Index| Reserved | -| | | | Used For Boot mode 0| | | -| | 0: Passive mode | 0 - Auto detection | | | | -| | 1: ISP mode | 1 - USB-HID | | | | -| | | 2 - UART | | | | -| | | 3 - SPI | | | | -| | | 4 - I2C | | | | -| | | 5 - CAN | | | | -*/ - -typedef struct -{ - union - { - struct - { - uint32_t reserved : 8; - uint32_t boot_image_index : 4; - uint32_t instance : 4; - uint32_t boot_interface : 4; - uint32_t mode : 4; - uint32_t tag : 8; - } B; - uint32_t U; - } option; -} user_app_boot_invoke_option_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @brief Run the Bootloader API to force into the ISP mode base on the user arg - * - * @param arg Indicates API prototype fields definition. Refer to the above user_app_boot_invoke_option_t structure - */ -void bootloader_user_entry(void *arg); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* _FSL_RUN_BOOTLOADER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/runbootloader/src/fsl_runbootloader.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/runbootloader/src/fsl_runbootloader.c deleted file mode 100644 index 1cdee52af1c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/runbootloader/src/fsl_runbootloader.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_flash.h" -#include "fsl_flash_ffr.h" -#include "fsl_flexspi_nor_flash.h" -#include "fsl_runbootloader.h" - -/*! @brief Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.runBootloader" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1302FC00U) - -/*! - * @name flash, ffr, flexspi nor flash Structure - * @{ - */ - -typedef union functionCommandOption -{ - uint32_t commandAddr; - status_t (*isFlashAreaReadable)(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); - status_t (*isFlashAreaModifiable)(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); -} function_command_option_t; - -/*! - * @brief Structure of version property. - * - * @ingroup bl_core - */ -typedef union StandardVersion -{ - struct - { - uint8_t bugfix; /*!< bugfix version [7:0] */ - uint8_t minor; /*!< minor version [15:8] */ - uint8_t major; /*!< major version [23:16] */ - char name; /*!< name [31:24] */ - }; - uint32_t version; /*!< combined version numbers */ -} standard_version_t; - -/*! @brief Interface for the flash driver.*/ -typedef struct FlashDriverInterface -{ - standard_version_t version; /*!< flash driver API version number. */ - /* Flash driver */ - status_t (*flash_init)(flash_config_t *config); - status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); - status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); - status_t (*flash_verify_program)(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); - - status_t (*flash_erase_with_checker)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - status_t (*flash_program_with_checker)(flash_config_t *config, - uint32_t start, - uint8_t *src, - uint32_t lengthInBytes); - status_t (*flash_verify_program_with_checker)(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - /*!< Flash FFR driver */ - status_t (*ffr_init)(flash_config_t *config); - status_t (*ffr_lock)(flash_config_t *config); - status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); - status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); - status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - status_t (*ffr_cust_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); - status_t reserved0; - status_t reserved1; - status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); - status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - status_t (*flash_read)(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); - status_t (*ffr_seclib_init)(flash_config_t *config, uint32_t *context); - status_t (*flash_get_cust_keystore)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - status_t (*flash_erase_non_blocking)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - status_t (*flash_get_command_state)(flash_config_t *config); -} flash_driver_interface_t; - -/*! @brief FLEXSPI Flash driver API Interface */ -typedef struct -{ - uint32_t version; - status_t (*init)(uint32_t instance, flexspi_nor_config_t *config); - status_t (*page_program)(uint32_t instance, flexspi_nor_config_t *config, uint32_t dstAddr, const uint32_t *src); - status_t (*erase_all)(uint32_t instance, flexspi_nor_config_t *config); - status_t (*erase)(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length); - status_t (*erase_sector)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); - status_t (*erase_block)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); - status_t (*get_config)(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option); - status_t (*read)(uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes); - status_t (*xfer)(uint32_t instance, flexspi_xfer_t *xfer); - status_t (*update_lut)(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq); - status_t (*set_clock_source)(uint32_t clockSrc); - void (*config_clock)(uint32_t instance, uint32_t freqOption, uint32_t sampleClkMode); -} flexspi_nor_flash_driver_t; - -/*! @}*/ - -/*! - * @brief Root of the bootloader API tree. - * - * An instance of this struct resides in read-only memory in the bootloader. It - * provides a user application access to APIs exported by the bootloader. - * - * @note The order of existing fields must not be changed. - */ -typedef struct BootloaderTree -{ - void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing.*/ - standard_version_t version; /*!< Bootloader version number.*/ - const char *copyright; /*!< Copyright string.*/ - const uint32_t reserved0; /*!< reserved*/ - const flash_driver_interface_t *flashDriver; /*!< Internal Flash driver API.*/ - const uint32_t reserved1[5]; /*!< reserved*/ - const uint32_t nbootDriver; /*!< Please refer to "fsl_nboot.h" */ - const flexspi_nor_flash_driver_t *flexspiNorDriver; /*!< FlexSPI NOR FLASH Driver API.*/ - const uint32_t reserved2; /*!< reserved*/ - const uint32_t memoryInterface; /*!< Please refer to "fsl_mem_interface.h" */ -} bootloader_tree_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -void bootloader_user_entry(void *arg) -{ - assert(BOOTLOADER_API_TREE_POINTER); - BOOTLOADER_API_TREE_POINTER->runBootloader(arg); -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/fsl_device_registers.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/fsl_device_registers.h deleted file mode 100644 index e0c187e3787..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/fsl_device_registers.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __FSL_DEVICE_REGISTERS_H__ -#define __FSL_DEVICE_REGISTERS_H__ - -/* - * Include the cpu specific register header files. - * - * The CPU macro should be declared in the project or makefile. - */ -#if (defined(CPU_LPC55S36JBD100) || defined(CPU_LPC55S36JHI48)) - -#define LPC55S36_SERIES - -/* CMSIS-style register definitions */ -#include "LPC55S36.h" -/* CPU specific feature definitions */ -#include "LPC55S36_features.h" - -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_DEVICE_REGISTERS_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/gcc/LPC55S36_flash.ld b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/gcc/LPC55S36_flash.ld deleted file mode 100644 index bc23d2616f8..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/gcc/LPC55S36_flash.ld +++ /dev/null @@ -1,205 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S36JBD100 -** LPC55S36JHI48 -** -** Compiler: GNU C Compiler -** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 -** Version: rev. 1.1, 2021-08-04 -** Build: b210913 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; - -/* __pkc__ : SRAM A(16K) reserved for; pkc __power_down__ : The first 0x604 bytes reserved to CPU retention for power down mode */ -RETENTION_RAMSIZE = DEFINED(__pkc__) ? 0x00004000 : (DEFINED(__power_down__) ? 0x00000604 : 0x00000000); -POWERQUAD_RAMSIZE = DEFINED(__powerquad__) ? 0x00004000 : 0x00000000; /* SRAM E(16K) reserved for powerquad */ - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 - m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x0003D400 - m_data (RW) : ORIGIN = 0x20000000 + RETENTION_RAMSIZE, LENGTH = 0x0001C000 - RETENTION_RAMSIZE - POWERQUAD_RAMSIZE - m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00004000 -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into internal flash */ - .interrupts : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.ramfunc*) /* for functions in ram */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/gcc/LPC55S36_ram.ld b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/gcc/LPC55S36_ram.ld deleted file mode 100644 index c1b7ae88ac4..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/gcc/LPC55S36_ram.ld +++ /dev/null @@ -1,204 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S36JBD100 -** LPC55S36JHI48 -** -** Compiler: GNU C Compiler -** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 -** Version: rev. 1.1, 2021-08-04 -** Build: b210913 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; - -/* __pkc__ : SRAM A(16K) reserved for; pkc __power_down__ : The first 0x604 bytes reserved to CPU retention for power down mode */ -RETENTION_RAMSIZE = DEFINED(__pkc__) ? 0x00004000 : (DEFINED(__power_down__) ? 0x00000604 : 0x00000000); -POWERQUAD_RAMSIZE = DEFINED(__powerquad__) ? 0x00004000 : 0x0; /* SRAM E(16K) reserved for powerquad */ - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x20000000 + RETENTION_RAMSIZE, LENGTH = 0x00000400 - m_text (RX) : ORIGIN = 0x20000400 + RETENTION_RAMSIZE, LENGTH = 0x0001BC00 - RETENTION_RAMSIZE - POWERQUAD_RAMSIZE - m_data (RW) : ORIGIN = 0x04000000, LENGTH = 0x00004000 -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into internal flash */ - .interrupts : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.ramfunc*) /* for functions in ram */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/gcc/startup_LPC55S36.S b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/gcc/startup_LPC55S36.S deleted file mode 100644 index 2fa183c298d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/gcc/startup_LPC55S36.S +++ /dev/null @@ -1,1544 +0,0 @@ -/* --------------------------------------------------------------------------*/ -/* @file: startup_LPC55S36.s */ -/* @purpose: CMSIS Cortex-M33 Core Device Startup File */ -/* LPC55S36 */ -/* @version: 1.1 */ -/* @date: 2021-8-4 */ -/* --------------------------------------------------------------------------*/ -/* */ -/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2021 NXP */ -/* All rights reserved. */ -/* */ -/* SPDX-License-Identifier: BSD-3-Clause */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - - - .syntax unified - .arch armv8-m.main - - .section .isr_vector, "a" - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long MemManage_Handler /* MPU Fault Handler*/ - .long BusFault_Handler /* Bus Fault Handler*/ - .long UsageFault_Handler /* Usage Fault Handler*/ - .long SecureFault_Handler /* Secure Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long DebugMon_Handler /* Debug Monitor Handler*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts */ - .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ - .long DMA0_IRQHandler /* DMA0 controller */ - .long GINT0_IRQHandler /* GPIO group 0 */ - .long GINT1_IRQHandler /* GPIO group 1 */ - .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - .long UTICK0_IRQHandler /* Micro-tick Timer */ - .long MRT0_IRQHandler /* Multi-rate timer */ - .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ - .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ - .long SCT0_IRQHandler /* SCTimer/PWM */ - .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ - .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long ADC0_IRQHandler /* ADC0 */ - .long ADC1_IRQHandler /* ADC1 */ - .long ACMP_IRQHandler /* ACMP interrupts */ - .long DMIC_IRQHandler /* Digital microphone and DMIC subsystem */ - .long HWVAD0_IRQHandler /* Hardware Voice Activity Detector */ - .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ - .long USB0_IRQHandler /* USB device */ - .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ - .long EZH_ARCH_B0_IRQHandler /* EZH interrupt */ - .long WAKEUP_IRQHandler /* Wakeup interrupt */ - .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ - .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ - .long OS_EVENT_IRQHandler /* OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ - .long FlexSPI0_IRQHandler /* FlexSPI interrupt */ - .long Reserved56_IRQHandler /* Reserved interrupt */ - .long Reserved57_IRQHandler /* Reserved interrupt */ - .long Reserved58_IRQHandler /* Reserved interrupt */ - .long CAN0_IRQ0_IRQHandler /* CAN0 interrupt0 */ - .long CAN0_IRQ1_IRQHandler /* CAN0 interrupt1 */ - .long SPI_FILTER_IRQHandler /* SPI Filter interrupt */ - .long Reserved62_IRQHandler /* Reserved interrupt */ - .long Reserved63_IRQHandler /* Reserved interrupt */ - .long Reserved64_IRQHandler /* Reserved interrupt */ - .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ - .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT00 interrupt */ - .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT01 interrupt */ - .long Freqme_IRQHandler /* frequency measure interrupt */ - .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ - .long SHA_IRQHandler /* SHA interrupt */ - .long PKC_IRQHandler /* CASPER interrupt */ - .long PUF_IRQHandler /* PUF interrupt */ - .long POWERQUAD_IRQHandler /* PowerQuad interrupt */ - .long DMA1_IRQHandler /* DMA1 interrupt */ - .long FLEXCOMM8_IRQHandler /* LSPI_HS interrupt */ - .long CDOG_IRQHandler /* CodeWDG interrupt */ - .long Reserved77_IRQHandler /* Reserved interrupt */ - .long I3C0_IRQHandler /* I3C interrupt */ - .long Reserved79_IRQHandler /* Reserved interrupt */ - .long Reserved80_IRQHandler /* Reserved interrupt */ - .long CSS_IRQ1_IRQHandler /* CSS_IRQ1 */ - .long Tamper_IRQHandler /* Tamper */ - .long Analog_Glitch_IRQHandler /* Analog_Glitch */ - .long Reserved84_IRQHandler /* Reserved interrupt */ - .long Reserved85_IRQHandler /* Reserved interrupt */ - .long Reserved86_IRQHandler /* Reserved interrupt */ - .long Reserved87_IRQHandler /* Reserved interrupt */ - .long Reserved88_IRQHandler /* Reserved interrupt */ - .long Reserved89_IRQHandler /* Reserved interrupt */ - .long DAC0_IRQHandler /* dac0 interrupt */ - .long DAC1_IRQHandler /* dac1 interrupt */ - .long DAC2_IRQHandler /* dac2 interrupt */ - .long HSCMP0_IRQHandler /* hscmp0 interrupt */ - .long HSCMP1_IRQHandler /* hscmp1 interrupt */ - .long HSCMP2_IRQHandler /* hscmp2 interrupt */ - .long FLEXPWM0_CAPTURE_IRQHandler /* flexpwm0_capture interrupt */ - .long FLEXPWM0_FAULT_IRQHandler /* flexpwm0_fault interrupt */ - .long FLEXPWM0_RELOAD_ERROR_IRQHandler /* flexpwm0_reload_error interrupt */ - .long FLEXPWM0_COMPARE0_IRQHandler /* flexpwm0_compare0 interrupt */ - .long FLEXPWM0_RELOAD0_IRQHandler /* flexpwm0_reload0 interrupt */ - .long FLEXPWM0_COMPARE1_IRQHandler /* flexpwm0_compare1 interrupt */ - .long FLEXPWM0_RELOAD1_IRQHandler /* flexpwm0_reload1 interrupt */ - .long FLEXPWM0_COMPARE2_IRQHandler /* flexpwm0_compare2 interrupt */ - .long FLEXPWM0_RELOAD2_IRQHandler /* flexpwm0_reload2 interrupt */ - .long FLEXPWM0_COMPARE3_IRQHandler /* flexpwm0_compare3 interrupt */ - .long FLEXPWM0_RELOAD3_IRQHandler /* flexpwm0_reload3 interrupt */ - .long FLEXPWM1_CAPTURE_IRQHandler /* flexpwm1_capture interrupt */ - .long FLEXPWM1_FAULT_IRQHandler /* flexpwm1_fault interrupt */ - .long FLEXPWM1_RELOAD_ERROR_IRQHandler /* flexpwm1_reload_error interrupt */ - .long FLEXPWM1_COMPARE0_IRQHandler /* flexpwm1_compare0 interrupt */ - .long FLEXPWM1_RELOAD0_IRQHandler /* flexpwm1_reload0 interrupt */ - .long FLEXPWM1_COMPARE1_IRQHandler /* flexpwm1_compare1 interrupt */ - .long FLEXPWM1_RELOAD1_IRQHandler /* flexpwm1_reload1 interrupt */ - .long FLEXPWM1_COMPARE2_IRQHandler /* flexpwm1_compare2 interrupt */ - .long FLEXPWM1_RELOAD2_IRQHandler /* flexpwm1_reload2 interrupt */ - .long FLEXPWM1_COMPARE3_IRQHandler /* flexpwm1_compare3 interrupt */ - .long FLEXPWM1_RELOAD3_IRQHandler /* flexpwm1_reload3 interrupt */ - .long ENC0_COMPARE_IRQHandler /* enc0_compare interrupt */ - .long ENC0_HOME_IRQHandler /* enc0_home interrupt */ - .long ENC0_WDG_IRQHandler /* enc0_wdg interrupt */ - .long ENC0_IDX_IRQHandler /* enc0_idx interrupt */ - .long ENC1_COMPARE_IRQHandler /* enc1_compare interrupt */ - .long ENC1_HOME_IRQHandler /* enc1_home interrupt */ - .long ENC1_WDG_IRQHandler /* enc1_wdg interrupt */ - .long ENC1_IDX_IRQHandler /* enc1_idx interrupt */ - .long ITRC0_IRQHandler /* itrc0 interrupt */ - .long Reserved127_IRQHandler /* Reserved interrupt */ - .long CSSV2_ERR_IRQHandler /* cssv2_err interrupt */ - .long PKC_ERR_IRQHandler /* pkc_err interrupt */ - .long Reserved130_IRQHandler /* Reserved interrupt */ - .long Reserved131_IRQHandler /* Reserved interrupt */ - .long Reserved132_IRQHandler /* Reserved interrupt */ - .long Reserved133_IRQHandler /* Reserved interrupt */ - .long FLASH_IRQHandler /* flash interrupt */ - .long RAM_PARITY_ECC_ERR_IRQHandler /* ram_parity_ecc_err interrupt */ - - .size __Vectors, . - __Vectors - - .text - .thumb - -/* Reset Handler */ - .thumb_func - .align 2 - .globl Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - cpsid i /* Mask interrupts */ - .equ VTOR, 0xE000ED08 - ldr r0, =VTOR - ldr r1, =__Vectors - str r1, [r0] - ldr r2, [r1] - msr msp, r2 - ldr r0, =__StackLimit - msr msplim, r0 -#ifndef __NO_SYSTEM_INIT - ldr r0,=SystemInit - blx r0 -#endif -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -#if 1 -/* Here are two copies of loop implemenations. First one favors code size - * and the second one favors performance. Default uses the first one. - * Change to "#if 0" to use the second one */ -.LC0: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .LC0 -#else - subs r3, r2 - ble .LC1 -.LC0: - subs r3, #4 - ldr r0, [r1, r3] - str r0, [r2, r3] - bgt .LC0 -.LC1: -#endif - -#ifdef __STARTUP_CLEAR_BSS -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * Loop to zero out BSS section, which uses following symbols - * in linker script: - * __bss_start__: start of BSS section. Must align to 4 - * __bss_end__: end of BSS section. Must align to 4 - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.LC2: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC2 -#endif /* __STARTUP_CLEAR_BSS */ - -/* Add stack / heap initializaiton */ - movs r0, 0 - ldr r1, =__HeapBase - ldr r2, =__HeapLimit -.LC3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC3 - - ldr r1, =__StackLimit - ldr r2, =__StackTop -.LC4: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC4 -/*End of stack / heap initializaiton */ - cpsie i /* Unmask interrupts */ - -#ifndef __START -#define __START _start -#endif -#ifndef __ATOLLIC__ - ldr r0,=__START - blx r0 -#else - ldr r0,=__libc_init_array - blx r0 - ldr r0,=main - bx r0 -#endif - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - - .align 1 - .thumb_func - .weak WDT_BOD_IRQHandler - .type WDT_BOD_IRQHandler, %function -WDT_BOD_IRQHandler: - ldr r0,=WDT_BOD_DriverIRQHandler - bx r0 - .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler - - .align 1 - .thumb_func - .weak DMA0_IRQHandler - .type DMA0_IRQHandler, %function -DMA0_IRQHandler: - ldr r0,=DMA0_DriverIRQHandler - bx r0 - .size DMA0_IRQHandler, . - DMA0_IRQHandler - - .align 1 - .thumb_func - .weak GINT0_IRQHandler - .type GINT0_IRQHandler, %function -GINT0_IRQHandler: - ldr r0,=GINT0_DriverIRQHandler - bx r0 - .size GINT0_IRQHandler, . - GINT0_IRQHandler - - .align 1 - .thumb_func - .weak GINT1_IRQHandler - .type GINT1_IRQHandler, %function -GINT1_IRQHandler: - ldr r0,=GINT1_DriverIRQHandler - bx r0 - .size GINT1_IRQHandler, . - GINT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT0_IRQHandler - .type PIN_INT0_IRQHandler, %function -PIN_INT0_IRQHandler: - ldr r0,=PIN_INT0_DriverIRQHandler - bx r0 - .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT1_IRQHandler - .type PIN_INT1_IRQHandler, %function -PIN_INT1_IRQHandler: - ldr r0,=PIN_INT1_DriverIRQHandler - bx r0 - .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT2_IRQHandler - .type PIN_INT2_IRQHandler, %function -PIN_INT2_IRQHandler: - ldr r0,=PIN_INT2_DriverIRQHandler - bx r0 - .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT3_IRQHandler - .type PIN_INT3_IRQHandler, %function -PIN_INT3_IRQHandler: - ldr r0,=PIN_INT3_DriverIRQHandler - bx r0 - .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler - - .align 1 - .thumb_func - .weak UTICK0_IRQHandler - .type UTICK0_IRQHandler, %function -UTICK0_IRQHandler: - ldr r0,=UTICK0_DriverIRQHandler - bx r0 - .size UTICK0_IRQHandler, . - UTICK0_IRQHandler - - .align 1 - .thumb_func - .weak MRT0_IRQHandler - .type MRT0_IRQHandler, %function -MRT0_IRQHandler: - ldr r0,=MRT0_DriverIRQHandler - bx r0 - .size MRT0_IRQHandler, . - MRT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER0_IRQHandler - .type CTIMER0_IRQHandler, %function -CTIMER0_IRQHandler: - ldr r0,=CTIMER0_DriverIRQHandler - bx r0 - .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER1_IRQHandler - .type CTIMER1_IRQHandler, %function -CTIMER1_IRQHandler: - ldr r0,=CTIMER1_DriverIRQHandler - bx r0 - .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler - - .align 1 - .thumb_func - .weak SCT0_IRQHandler - .type SCT0_IRQHandler, %function -SCT0_IRQHandler: - ldr r0,=SCT0_DriverIRQHandler - bx r0 - .size SCT0_IRQHandler, . - SCT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER3_IRQHandler - .type CTIMER3_IRQHandler, %function -CTIMER3_IRQHandler: - ldr r0,=CTIMER3_DriverIRQHandler - bx r0 - .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM0_IRQHandler - .type FLEXCOMM0_IRQHandler, %function -FLEXCOMM0_IRQHandler: - ldr r0,=FLEXCOMM0_DriverIRQHandler - bx r0 - .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM1_IRQHandler - .type FLEXCOMM1_IRQHandler, %function -FLEXCOMM1_IRQHandler: - ldr r0,=FLEXCOMM1_DriverIRQHandler - bx r0 - .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM2_IRQHandler - .type FLEXCOMM2_IRQHandler, %function -FLEXCOMM2_IRQHandler: - ldr r0,=FLEXCOMM2_DriverIRQHandler - bx r0 - .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM3_IRQHandler - .type FLEXCOMM3_IRQHandler, %function -FLEXCOMM3_IRQHandler: - ldr r0,=FLEXCOMM3_DriverIRQHandler - bx r0 - .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM4_IRQHandler - .type FLEXCOMM4_IRQHandler, %function -FLEXCOMM4_IRQHandler: - ldr r0,=FLEXCOMM4_DriverIRQHandler - bx r0 - .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM5_IRQHandler - .type FLEXCOMM5_IRQHandler, %function -FLEXCOMM5_IRQHandler: - ldr r0,=FLEXCOMM5_DriverIRQHandler - bx r0 - .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM6_IRQHandler - .type FLEXCOMM6_IRQHandler, %function -FLEXCOMM6_IRQHandler: - ldr r0,=FLEXCOMM6_DriverIRQHandler - bx r0 - .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM7_IRQHandler - .type FLEXCOMM7_IRQHandler, %function -FLEXCOMM7_IRQHandler: - ldr r0,=FLEXCOMM7_DriverIRQHandler - bx r0 - .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_IRQHandler - .type ADC0_IRQHandler, %function -ADC0_IRQHandler: - ldr r0,=ADC0_DriverIRQHandler - bx r0 - .size ADC0_IRQHandler, . - ADC0_IRQHandler - - .align 1 - .thumb_func - .weak ADC1_IRQHandler - .type ADC1_IRQHandler, %function -ADC1_IRQHandler: - ldr r0,=ADC1_DriverIRQHandler - bx r0 - .size ADC1_IRQHandler, . - ADC1_IRQHandler - - .align 1 - .thumb_func - .weak ACMP_IRQHandler - .type ACMP_IRQHandler, %function -ACMP_IRQHandler: - ldr r0,=ACMP_DriverIRQHandler - bx r0 - .size ACMP_IRQHandler, . - ACMP_IRQHandler - - .align 1 - .thumb_func - .weak DMIC_IRQHandler - .type DMIC_IRQHandler, %function -DMIC_IRQHandler: - ldr r0,=DMIC_DriverIRQHandler - bx r0 - .size DMIC_IRQHandler, . - DMIC_IRQHandler - - .align 1 - .thumb_func - .weak HWVAD0_IRQHandler - .type HWVAD0_IRQHandler, %function -HWVAD0_IRQHandler: - ldr r0,=HWVAD0_DriverIRQHandler - bx r0 - .size HWVAD0_IRQHandler, . - HWVAD0_IRQHandler - - .align 1 - .thumb_func - .weak USB0_NEEDCLK_IRQHandler - .type USB0_NEEDCLK_IRQHandler, %function -USB0_NEEDCLK_IRQHandler: - ldr r0,=USB0_NEEDCLK_DriverIRQHandler - bx r0 - .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak USB0_IRQHandler - .type USB0_IRQHandler, %function -USB0_IRQHandler: - ldr r0,=USB0_DriverIRQHandler - bx r0 - .size USB0_IRQHandler, . - USB0_IRQHandler - - .align 1 - .thumb_func - .weak RTC_IRQHandler - .type RTC_IRQHandler, %function -RTC_IRQHandler: - ldr r0,=RTC_DriverIRQHandler - bx r0 - .size RTC_IRQHandler, . - RTC_IRQHandler - - .align 1 - .thumb_func - .weak EZH_ARCH_B0_IRQHandler - .type EZH_ARCH_B0_IRQHandler, %function -EZH_ARCH_B0_IRQHandler: - ldr r0,=EZH_ARCH_B0_DriverIRQHandler - bx r0 - .size EZH_ARCH_B0_IRQHandler, . - EZH_ARCH_B0_IRQHandler - - .align 1 - .thumb_func - .weak WAKEUP_IRQHandler - .type WAKEUP_IRQHandler, %function -WAKEUP_IRQHandler: - ldr r0,=WAKEUP_DriverIRQHandler - bx r0 - .size WAKEUP_IRQHandler, . - WAKEUP_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT4_IRQHandler - .type PIN_INT4_IRQHandler, %function -PIN_INT4_IRQHandler: - ldr r0,=PIN_INT4_DriverIRQHandler - bx r0 - .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT5_IRQHandler - .type PIN_INT5_IRQHandler, %function -PIN_INT5_IRQHandler: - ldr r0,=PIN_INT5_DriverIRQHandler - bx r0 - .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT6_IRQHandler - .type PIN_INT6_IRQHandler, %function -PIN_INT6_IRQHandler: - ldr r0,=PIN_INT6_DriverIRQHandler - bx r0 - .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT7_IRQHandler - .type PIN_INT7_IRQHandler, %function -PIN_INT7_IRQHandler: - ldr r0,=PIN_INT7_DriverIRQHandler - bx r0 - .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER2_IRQHandler - .type CTIMER2_IRQHandler, %function -CTIMER2_IRQHandler: - ldr r0,=CTIMER2_DriverIRQHandler - bx r0 - .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER4_IRQHandler - .type CTIMER4_IRQHandler, %function -CTIMER4_IRQHandler: - ldr r0,=CTIMER4_DriverIRQHandler - bx r0 - .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler - - .align 1 - .thumb_func - .weak OS_EVENT_IRQHandler - .type OS_EVENT_IRQHandler, %function -OS_EVENT_IRQHandler: - ldr r0,=OS_EVENT_DriverIRQHandler - bx r0 - .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler - - .align 1 - .thumb_func - .weak FlexSPI0_IRQHandler - .type FlexSPI0_IRQHandler, %function -FlexSPI0_IRQHandler: - ldr r0,=FlexSPI0_DriverIRQHandler - bx r0 - .size FlexSPI0_IRQHandler, . - FlexSPI0_IRQHandler - - .align 1 - .thumb_func - .weak Reserved56_IRQHandler - .type Reserved56_IRQHandler, %function -Reserved56_IRQHandler: - ldr r0,=Reserved56_DriverIRQHandler - bx r0 - .size Reserved56_IRQHandler, . - Reserved56_IRQHandler - - .align 1 - .thumb_func - .weak Reserved57_IRQHandler - .type Reserved57_IRQHandler, %function -Reserved57_IRQHandler: - ldr r0,=Reserved57_DriverIRQHandler - bx r0 - .size Reserved57_IRQHandler, . - Reserved57_IRQHandler - - .align 1 - .thumb_func - .weak Reserved58_IRQHandler - .type Reserved58_IRQHandler, %function -Reserved58_IRQHandler: - ldr r0,=Reserved58_DriverIRQHandler - bx r0 - .size Reserved58_IRQHandler, . - Reserved58_IRQHandler - - .align 1 - .thumb_func - .weak CAN0_IRQ0_IRQHandler - .type CAN0_IRQ0_IRQHandler, %function -CAN0_IRQ0_IRQHandler: - ldr r0,=CAN0_IRQ0_DriverIRQHandler - bx r0 - .size CAN0_IRQ0_IRQHandler, . - CAN0_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak CAN0_IRQ1_IRQHandler - .type CAN0_IRQ1_IRQHandler, %function -CAN0_IRQ1_IRQHandler: - ldr r0,=CAN0_IRQ1_DriverIRQHandler - bx r0 - .size CAN0_IRQ1_IRQHandler, . - CAN0_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak SPI_FILTER_IRQHandler - .type SPI_FILTER_IRQHandler, %function -SPI_FILTER_IRQHandler: - ldr r0,=SPI_FILTER_DriverIRQHandler - bx r0 - .size SPI_FILTER_IRQHandler, . - SPI_FILTER_IRQHandler - - .align 1 - .thumb_func - .weak Reserved62_IRQHandler - .type Reserved62_IRQHandler, %function -Reserved62_IRQHandler: - ldr r0,=Reserved62_DriverIRQHandler - bx r0 - .size Reserved62_IRQHandler, . - Reserved62_IRQHandler - - .align 1 - .thumb_func - .weak Reserved63_IRQHandler - .type Reserved63_IRQHandler, %function -Reserved63_IRQHandler: - ldr r0,=Reserved63_DriverIRQHandler - bx r0 - .size Reserved63_IRQHandler, . - Reserved63_IRQHandler - - .align 1 - .thumb_func - .weak Reserved64_IRQHandler - .type Reserved64_IRQHandler, %function -Reserved64_IRQHandler: - ldr r0,=Reserved64_DriverIRQHandler - bx r0 - .size Reserved64_IRQHandler, . - Reserved64_IRQHandler - - .align 1 - .thumb_func - .weak SEC_HYPERVISOR_CALL_IRQHandler - .type SEC_HYPERVISOR_CALL_IRQHandler, %function -SEC_HYPERVISOR_CALL_IRQHandler: - ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler - bx r0 - .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ0_IRQHandler - .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function -SEC_GPIO_INT0_IRQ0_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ1_IRQHandler - .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function -SEC_GPIO_INT0_IRQ1_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak Freqme_IRQHandler - .type Freqme_IRQHandler, %function -Freqme_IRQHandler: - ldr r0,=Freqme_DriverIRQHandler - bx r0 - .size Freqme_IRQHandler, . - Freqme_IRQHandler - - .align 1 - .thumb_func - .weak SEC_VIO_IRQHandler - .type SEC_VIO_IRQHandler, %function -SEC_VIO_IRQHandler: - ldr r0,=SEC_VIO_DriverIRQHandler - bx r0 - .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler - - .align 1 - .thumb_func - .weak SHA_IRQHandler - .type SHA_IRQHandler, %function -SHA_IRQHandler: - ldr r0,=SHA_DriverIRQHandler - bx r0 - .size SHA_IRQHandler, . - SHA_IRQHandler - - .align 1 - .thumb_func - .weak PKC_IRQHandler - .type PKC_IRQHandler, %function -PKC_IRQHandler: - ldr r0,=PKC_DriverIRQHandler - bx r0 - .size PKC_IRQHandler, . - PKC_IRQHandler - - .align 1 - .thumb_func - .weak PUF_IRQHandler - .type PUF_IRQHandler, %function -PUF_IRQHandler: - ldr r0,=PUF_DriverIRQHandler - bx r0 - .size PUF_IRQHandler, . - PUF_IRQHandler - - .align 1 - .thumb_func - .weak POWERQUAD_IRQHandler - .type POWERQUAD_IRQHandler, %function -POWERQUAD_IRQHandler: - ldr r0,=POWERQUAD_DriverIRQHandler - bx r0 - .size POWERQUAD_IRQHandler, . - POWERQUAD_IRQHandler - - .align 1 - .thumb_func - .weak DMA1_IRQHandler - .type DMA1_IRQHandler, %function -DMA1_IRQHandler: - ldr r0,=DMA1_DriverIRQHandler - bx r0 - .size DMA1_IRQHandler, . - DMA1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM8_IRQHandler - .type FLEXCOMM8_IRQHandler, %function -FLEXCOMM8_IRQHandler: - ldr r0,=FLEXCOMM8_DriverIRQHandler - bx r0 - .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler - - .align 1 - .thumb_func - .weak CDOG_IRQHandler - .type CDOG_IRQHandler, %function -CDOG_IRQHandler: - ldr r0,=CDOG_DriverIRQHandler - bx r0 - .size CDOG_IRQHandler, . - CDOG_IRQHandler - - .align 1 - .thumb_func - .weak Reserved77_IRQHandler - .type Reserved77_IRQHandler, %function -Reserved77_IRQHandler: - ldr r0,=Reserved77_DriverIRQHandler - bx r0 - .size Reserved77_IRQHandler, . - Reserved77_IRQHandler - - .align 1 - .thumb_func - .weak I3C0_IRQHandler - .type I3C0_IRQHandler, %function -I3C0_IRQHandler: - ldr r0,=I3C0_DriverIRQHandler - bx r0 - .size I3C0_IRQHandler, . - I3C0_IRQHandler - - .align 1 - .thumb_func - .weak Reserved79_IRQHandler - .type Reserved79_IRQHandler, %function -Reserved79_IRQHandler: - ldr r0,=Reserved79_DriverIRQHandler - bx r0 - .size Reserved79_IRQHandler, . - Reserved79_IRQHandler - - .align 1 - .thumb_func - .weak Reserved80_IRQHandler - .type Reserved80_IRQHandler, %function -Reserved80_IRQHandler: - ldr r0,=Reserved80_DriverIRQHandler - bx r0 - .size Reserved80_IRQHandler, . - Reserved80_IRQHandler - - .align 1 - .thumb_func - .weak CSS_IRQ1_IRQHandler - .type CSS_IRQ1_IRQHandler, %function -CSS_IRQ1_IRQHandler: - ldr r0,=CSS_IRQ1_DriverIRQHandler - bx r0 - .size CSS_IRQ1_IRQHandler, . - CSS_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak Tamper_IRQHandler - .type Tamper_IRQHandler, %function -Tamper_IRQHandler: - ldr r0,=Tamper_DriverIRQHandler - bx r0 - .size Tamper_IRQHandler, . - Tamper_IRQHandler - - .align 1 - .thumb_func - .weak Analog_Glitch_IRQHandler - .type Analog_Glitch_IRQHandler, %function -Analog_Glitch_IRQHandler: - ldr r0,=Analog_Glitch_DriverIRQHandler - bx r0 - .size Analog_Glitch_IRQHandler, . - Analog_Glitch_IRQHandler - - .align 1 - .thumb_func - .weak Reserved84_IRQHandler - .type Reserved84_IRQHandler, %function -Reserved84_IRQHandler: - ldr r0,=Reserved84_DriverIRQHandler - bx r0 - .size Reserved84_IRQHandler, . - Reserved84_IRQHandler - - .align 1 - .thumb_func - .weak Reserved85_IRQHandler - .type Reserved85_IRQHandler, %function -Reserved85_IRQHandler: - ldr r0,=Reserved85_DriverIRQHandler - bx r0 - .size Reserved85_IRQHandler, . - Reserved85_IRQHandler - - .align 1 - .thumb_func - .weak Reserved86_IRQHandler - .type Reserved86_IRQHandler, %function -Reserved86_IRQHandler: - ldr r0,=Reserved86_DriverIRQHandler - bx r0 - .size Reserved86_IRQHandler, . - Reserved86_IRQHandler - - .align 1 - .thumb_func - .weak Reserved87_IRQHandler - .type Reserved87_IRQHandler, %function -Reserved87_IRQHandler: - ldr r0,=Reserved87_DriverIRQHandler - bx r0 - .size Reserved87_IRQHandler, . - Reserved87_IRQHandler - - .align 1 - .thumb_func - .weak Reserved88_IRQHandler - .type Reserved88_IRQHandler, %function -Reserved88_IRQHandler: - ldr r0,=Reserved88_DriverIRQHandler - bx r0 - .size Reserved88_IRQHandler, . - Reserved88_IRQHandler - - .align 1 - .thumb_func - .weak Reserved89_IRQHandler - .type Reserved89_IRQHandler, %function -Reserved89_IRQHandler: - ldr r0,=Reserved89_DriverIRQHandler - bx r0 - .size Reserved89_IRQHandler, . - Reserved89_IRQHandler - - .align 1 - .thumb_func - .weak DAC0_IRQHandler - .type DAC0_IRQHandler, %function -DAC0_IRQHandler: - ldr r0,=DAC0_DriverIRQHandler - bx r0 - .size DAC0_IRQHandler, . - DAC0_IRQHandler - - .align 1 - .thumb_func - .weak DAC1_IRQHandler - .type DAC1_IRQHandler, %function -DAC1_IRQHandler: - ldr r0,=DAC1_DriverIRQHandler - bx r0 - .size DAC1_IRQHandler, . - DAC1_IRQHandler - - .align 1 - .thumb_func - .weak DAC2_IRQHandler - .type DAC2_IRQHandler, %function -DAC2_IRQHandler: - ldr r0,=DAC2_DriverIRQHandler - bx r0 - .size DAC2_IRQHandler, . - DAC2_IRQHandler - - .align 1 - .thumb_func - .weak HSCMP0_IRQHandler - .type HSCMP0_IRQHandler, %function -HSCMP0_IRQHandler: - ldr r0,=HSCMP0_DriverIRQHandler - bx r0 - .size HSCMP0_IRQHandler, . - HSCMP0_IRQHandler - - .align 1 - .thumb_func - .weak HSCMP1_IRQHandler - .type HSCMP1_IRQHandler, %function -HSCMP1_IRQHandler: - ldr r0,=HSCMP1_DriverIRQHandler - bx r0 - .size HSCMP1_IRQHandler, . - HSCMP1_IRQHandler - - .align 1 - .thumb_func - .weak HSCMP2_IRQHandler - .type HSCMP2_IRQHandler, %function -HSCMP2_IRQHandler: - ldr r0,=HSCMP2_DriverIRQHandler - bx r0 - .size HSCMP2_IRQHandler, . - HSCMP2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_CAPTURE_IRQHandler - .type FLEXPWM0_CAPTURE_IRQHandler, %function -FLEXPWM0_CAPTURE_IRQHandler: - ldr r0,=FLEXPWM0_CAPTURE_DriverIRQHandler - bx r0 - .size FLEXPWM0_CAPTURE_IRQHandler, . - FLEXPWM0_CAPTURE_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_FAULT_IRQHandler - .type FLEXPWM0_FAULT_IRQHandler, %function -FLEXPWM0_FAULT_IRQHandler: - ldr r0,=FLEXPWM0_FAULT_DriverIRQHandler - bx r0 - .size FLEXPWM0_FAULT_IRQHandler, . - FLEXPWM0_FAULT_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_RELOAD_ERROR_IRQHandler - .type FLEXPWM0_RELOAD_ERROR_IRQHandler, %function -FLEXPWM0_RELOAD_ERROR_IRQHandler: - ldr r0,=FLEXPWM0_RELOAD_ERROR_DriverIRQHandler - bx r0 - .size FLEXPWM0_RELOAD_ERROR_IRQHandler, . - FLEXPWM0_RELOAD_ERROR_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_COMPARE0_IRQHandler - .type FLEXPWM0_COMPARE0_IRQHandler, %function -FLEXPWM0_COMPARE0_IRQHandler: - ldr r0,=FLEXPWM0_COMPARE0_DriverIRQHandler - bx r0 - .size FLEXPWM0_COMPARE0_IRQHandler, . - FLEXPWM0_COMPARE0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_RELOAD0_IRQHandler - .type FLEXPWM0_RELOAD0_IRQHandler, %function -FLEXPWM0_RELOAD0_IRQHandler: - ldr r0,=FLEXPWM0_RELOAD0_DriverIRQHandler - bx r0 - .size FLEXPWM0_RELOAD0_IRQHandler, . - FLEXPWM0_RELOAD0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_COMPARE1_IRQHandler - .type FLEXPWM0_COMPARE1_IRQHandler, %function -FLEXPWM0_COMPARE1_IRQHandler: - ldr r0,=FLEXPWM0_COMPARE1_DriverIRQHandler - bx r0 - .size FLEXPWM0_COMPARE1_IRQHandler, . - FLEXPWM0_COMPARE1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_RELOAD1_IRQHandler - .type FLEXPWM0_RELOAD1_IRQHandler, %function -FLEXPWM0_RELOAD1_IRQHandler: - ldr r0,=FLEXPWM0_RELOAD1_DriverIRQHandler - bx r0 - .size FLEXPWM0_RELOAD1_IRQHandler, . - FLEXPWM0_RELOAD1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_COMPARE2_IRQHandler - .type FLEXPWM0_COMPARE2_IRQHandler, %function -FLEXPWM0_COMPARE2_IRQHandler: - ldr r0,=FLEXPWM0_COMPARE2_DriverIRQHandler - bx r0 - .size FLEXPWM0_COMPARE2_IRQHandler, . - FLEXPWM0_COMPARE2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_RELOAD2_IRQHandler - .type FLEXPWM0_RELOAD2_IRQHandler, %function -FLEXPWM0_RELOAD2_IRQHandler: - ldr r0,=FLEXPWM0_RELOAD2_DriverIRQHandler - bx r0 - .size FLEXPWM0_RELOAD2_IRQHandler, . - FLEXPWM0_RELOAD2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_COMPARE3_IRQHandler - .type FLEXPWM0_COMPARE3_IRQHandler, %function -FLEXPWM0_COMPARE3_IRQHandler: - ldr r0,=FLEXPWM0_COMPARE3_DriverIRQHandler - bx r0 - .size FLEXPWM0_COMPARE3_IRQHandler, . - FLEXPWM0_COMPARE3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM0_RELOAD3_IRQHandler - .type FLEXPWM0_RELOAD3_IRQHandler, %function -FLEXPWM0_RELOAD3_IRQHandler: - ldr r0,=FLEXPWM0_RELOAD3_DriverIRQHandler - bx r0 - .size FLEXPWM0_RELOAD3_IRQHandler, . - FLEXPWM0_RELOAD3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_CAPTURE_IRQHandler - .type FLEXPWM1_CAPTURE_IRQHandler, %function -FLEXPWM1_CAPTURE_IRQHandler: - ldr r0,=FLEXPWM1_CAPTURE_DriverIRQHandler - bx r0 - .size FLEXPWM1_CAPTURE_IRQHandler, . - FLEXPWM1_CAPTURE_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_FAULT_IRQHandler - .type FLEXPWM1_FAULT_IRQHandler, %function -FLEXPWM1_FAULT_IRQHandler: - ldr r0,=FLEXPWM1_FAULT_DriverIRQHandler - bx r0 - .size FLEXPWM1_FAULT_IRQHandler, . - FLEXPWM1_FAULT_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_RELOAD_ERROR_IRQHandler - .type FLEXPWM1_RELOAD_ERROR_IRQHandler, %function -FLEXPWM1_RELOAD_ERROR_IRQHandler: - ldr r0,=FLEXPWM1_RELOAD_ERROR_DriverIRQHandler - bx r0 - .size FLEXPWM1_RELOAD_ERROR_IRQHandler, . - FLEXPWM1_RELOAD_ERROR_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_COMPARE0_IRQHandler - .type FLEXPWM1_COMPARE0_IRQHandler, %function -FLEXPWM1_COMPARE0_IRQHandler: - ldr r0,=FLEXPWM1_COMPARE0_DriverIRQHandler - bx r0 - .size FLEXPWM1_COMPARE0_IRQHandler, . - FLEXPWM1_COMPARE0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_RELOAD0_IRQHandler - .type FLEXPWM1_RELOAD0_IRQHandler, %function -FLEXPWM1_RELOAD0_IRQHandler: - ldr r0,=FLEXPWM1_RELOAD0_DriverIRQHandler - bx r0 - .size FLEXPWM1_RELOAD0_IRQHandler, . - FLEXPWM1_RELOAD0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_COMPARE1_IRQHandler - .type FLEXPWM1_COMPARE1_IRQHandler, %function -FLEXPWM1_COMPARE1_IRQHandler: - ldr r0,=FLEXPWM1_COMPARE1_DriverIRQHandler - bx r0 - .size FLEXPWM1_COMPARE1_IRQHandler, . - FLEXPWM1_COMPARE1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_RELOAD1_IRQHandler - .type FLEXPWM1_RELOAD1_IRQHandler, %function -FLEXPWM1_RELOAD1_IRQHandler: - ldr r0,=FLEXPWM1_RELOAD1_DriverIRQHandler - bx r0 - .size FLEXPWM1_RELOAD1_IRQHandler, . - FLEXPWM1_RELOAD1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_COMPARE2_IRQHandler - .type FLEXPWM1_COMPARE2_IRQHandler, %function -FLEXPWM1_COMPARE2_IRQHandler: - ldr r0,=FLEXPWM1_COMPARE2_DriverIRQHandler - bx r0 - .size FLEXPWM1_COMPARE2_IRQHandler, . - FLEXPWM1_COMPARE2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_RELOAD2_IRQHandler - .type FLEXPWM1_RELOAD2_IRQHandler, %function -FLEXPWM1_RELOAD2_IRQHandler: - ldr r0,=FLEXPWM1_RELOAD2_DriverIRQHandler - bx r0 - .size FLEXPWM1_RELOAD2_IRQHandler, . - FLEXPWM1_RELOAD2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_COMPARE3_IRQHandler - .type FLEXPWM1_COMPARE3_IRQHandler, %function -FLEXPWM1_COMPARE3_IRQHandler: - ldr r0,=FLEXPWM1_COMPARE3_DriverIRQHandler - bx r0 - .size FLEXPWM1_COMPARE3_IRQHandler, . - FLEXPWM1_COMPARE3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXPWM1_RELOAD3_IRQHandler - .type FLEXPWM1_RELOAD3_IRQHandler, %function -FLEXPWM1_RELOAD3_IRQHandler: - ldr r0,=FLEXPWM1_RELOAD3_DriverIRQHandler - bx r0 - .size FLEXPWM1_RELOAD3_IRQHandler, . - FLEXPWM1_RELOAD3_IRQHandler - - .align 1 - .thumb_func - .weak ENC0_COMPARE_IRQHandler - .type ENC0_COMPARE_IRQHandler, %function -ENC0_COMPARE_IRQHandler: - ldr r0,=ENC0_COMPARE_DriverIRQHandler - bx r0 - .size ENC0_COMPARE_IRQHandler, . - ENC0_COMPARE_IRQHandler - - .align 1 - .thumb_func - .weak ENC0_HOME_IRQHandler - .type ENC0_HOME_IRQHandler, %function -ENC0_HOME_IRQHandler: - ldr r0,=ENC0_HOME_DriverIRQHandler - bx r0 - .size ENC0_HOME_IRQHandler, . - ENC0_HOME_IRQHandler - - .align 1 - .thumb_func - .weak ENC0_WDG_IRQHandler - .type ENC0_WDG_IRQHandler, %function -ENC0_WDG_IRQHandler: - ldr r0,=ENC0_WDG_DriverIRQHandler - bx r0 - .size ENC0_WDG_IRQHandler, . - ENC0_WDG_IRQHandler - - .align 1 - .thumb_func - .weak ENC0_IDX_IRQHandler - .type ENC0_IDX_IRQHandler, %function -ENC0_IDX_IRQHandler: - ldr r0,=ENC0_IDX_DriverIRQHandler - bx r0 - .size ENC0_IDX_IRQHandler, . - ENC0_IDX_IRQHandler - - .align 1 - .thumb_func - .weak ENC1_COMPARE_IRQHandler - .type ENC1_COMPARE_IRQHandler, %function -ENC1_COMPARE_IRQHandler: - ldr r0,=ENC1_COMPARE_DriverIRQHandler - bx r0 - .size ENC1_COMPARE_IRQHandler, . - ENC1_COMPARE_IRQHandler - - .align 1 - .thumb_func - .weak ENC1_HOME_IRQHandler - .type ENC1_HOME_IRQHandler, %function -ENC1_HOME_IRQHandler: - ldr r0,=ENC1_HOME_DriverIRQHandler - bx r0 - .size ENC1_HOME_IRQHandler, . - ENC1_HOME_IRQHandler - - .align 1 - .thumb_func - .weak ENC1_WDG_IRQHandler - .type ENC1_WDG_IRQHandler, %function -ENC1_WDG_IRQHandler: - ldr r0,=ENC1_WDG_DriverIRQHandler - bx r0 - .size ENC1_WDG_IRQHandler, . - ENC1_WDG_IRQHandler - - .align 1 - .thumb_func - .weak ENC1_IDX_IRQHandler - .type ENC1_IDX_IRQHandler, %function -ENC1_IDX_IRQHandler: - ldr r0,=ENC1_IDX_DriverIRQHandler - bx r0 - .size ENC1_IDX_IRQHandler, . - ENC1_IDX_IRQHandler - - .align 1 - .thumb_func - .weak ITRC0_IRQHandler - .type ITRC0_IRQHandler, %function -ITRC0_IRQHandler: - ldr r0,=ITRC0_DriverIRQHandler - bx r0 - .size ITRC0_IRQHandler, . - ITRC0_IRQHandler - - .align 1 - .thumb_func - .weak Reserved127_IRQHandler - .type Reserved127_IRQHandler, %function -Reserved127_IRQHandler: - ldr r0,=Reserved127_DriverIRQHandler - bx r0 - .size Reserved127_IRQHandler, . - Reserved127_IRQHandler - - .align 1 - .thumb_func - .weak CSSV2_ERR_IRQHandler - .type CSSV2_ERR_IRQHandler, %function -CSSV2_ERR_IRQHandler: - ldr r0,=CSSV2_ERR_DriverIRQHandler - bx r0 - .size CSSV2_ERR_IRQHandler, . - CSSV2_ERR_IRQHandler - - .align 1 - .thumb_func - .weak PKC_ERR_IRQHandler - .type PKC_ERR_IRQHandler, %function -PKC_ERR_IRQHandler: - ldr r0,=PKC_ERR_DriverIRQHandler - bx r0 - .size PKC_ERR_IRQHandler, . - PKC_ERR_IRQHandler - - .align 1 - .thumb_func - .weak Reserved130_IRQHandler - .type Reserved130_IRQHandler, %function -Reserved130_IRQHandler: - ldr r0,=Reserved130_DriverIRQHandler - bx r0 - .size Reserved130_IRQHandler, . - Reserved130_IRQHandler - - .align 1 - .thumb_func - .weak Reserved131_IRQHandler - .type Reserved131_IRQHandler, %function -Reserved131_IRQHandler: - ldr r0,=Reserved131_DriverIRQHandler - bx r0 - .size Reserved131_IRQHandler, . - Reserved131_IRQHandler - - .align 1 - .thumb_func - .weak Reserved132_IRQHandler - .type Reserved132_IRQHandler, %function -Reserved132_IRQHandler: - ldr r0,=Reserved132_DriverIRQHandler - bx r0 - .size Reserved132_IRQHandler, . - Reserved132_IRQHandler - - .align 1 - .thumb_func - .weak Reserved133_IRQHandler - .type Reserved133_IRQHandler, %function -Reserved133_IRQHandler: - ldr r0,=Reserved133_DriverIRQHandler - bx r0 - .size Reserved133_IRQHandler, . - Reserved133_IRQHandler - - .align 1 - .thumb_func - .weak FLASH_IRQHandler - .type FLASH_IRQHandler, %function -FLASH_IRQHandler: - ldr r0,=FLASH_DriverIRQHandler - bx r0 - .size FLASH_IRQHandler, . - FLASH_IRQHandler - - .align 1 - .thumb_func - .weak RAM_PARITY_ECC_ERR_IRQHandler - .type RAM_PARITY_ECC_ERR_IRQHandler, %function -RAM_PARITY_ECC_ERR_IRQHandler: - ldr r0,=RAM_PARITY_ECC_ERR_DriverIRQHandler - bx r0 - .size RAM_PARITY_ECC_ERR_IRQHandler, . - RAM_PARITY_ECC_ERR_IRQHandler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm -/* Exception Handlers */ - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SecureFault_Handler - def_irq_handler DebugMon_Handler - def_irq_handler WDT_BOD_DriverIRQHandler - def_irq_handler DMA0_DriverIRQHandler - def_irq_handler GINT0_DriverIRQHandler - def_irq_handler GINT1_DriverIRQHandler - def_irq_handler PIN_INT0_DriverIRQHandler - def_irq_handler PIN_INT1_DriverIRQHandler - def_irq_handler PIN_INT2_DriverIRQHandler - def_irq_handler PIN_INT3_DriverIRQHandler - def_irq_handler UTICK0_DriverIRQHandler - def_irq_handler MRT0_DriverIRQHandler - def_irq_handler CTIMER0_DriverIRQHandler - def_irq_handler CTIMER1_DriverIRQHandler - def_irq_handler SCT0_DriverIRQHandler - def_irq_handler CTIMER3_DriverIRQHandler - def_irq_handler FLEXCOMM0_DriverIRQHandler - def_irq_handler FLEXCOMM1_DriverIRQHandler - def_irq_handler FLEXCOMM2_DriverIRQHandler - def_irq_handler FLEXCOMM3_DriverIRQHandler - def_irq_handler FLEXCOMM4_DriverIRQHandler - def_irq_handler FLEXCOMM5_DriverIRQHandler - def_irq_handler FLEXCOMM6_DriverIRQHandler - def_irq_handler FLEXCOMM7_DriverIRQHandler - def_irq_handler ADC0_DriverIRQHandler - def_irq_handler ADC1_DriverIRQHandler - def_irq_handler ACMP_DriverIRQHandler - def_irq_handler DMIC_DriverIRQHandler - def_irq_handler HWVAD0_DriverIRQHandler - def_irq_handler USB0_NEEDCLK_DriverIRQHandler - def_irq_handler USB0_DriverIRQHandler - def_irq_handler RTC_DriverIRQHandler - def_irq_handler EZH_ARCH_B0_DriverIRQHandler - def_irq_handler WAKEUP_DriverIRQHandler - def_irq_handler PIN_INT4_DriverIRQHandler - def_irq_handler PIN_INT5_DriverIRQHandler - def_irq_handler PIN_INT6_DriverIRQHandler - def_irq_handler PIN_INT7_DriverIRQHandler - def_irq_handler CTIMER2_DriverIRQHandler - def_irq_handler CTIMER4_DriverIRQHandler - def_irq_handler OS_EVENT_DriverIRQHandler - def_irq_handler FlexSPI0_DriverIRQHandler - def_irq_handler Reserved56_DriverIRQHandler - def_irq_handler Reserved57_DriverIRQHandler - def_irq_handler Reserved58_DriverIRQHandler - def_irq_handler CAN0_IRQ0_DriverIRQHandler - def_irq_handler CAN0_IRQ1_DriverIRQHandler - def_irq_handler SPI_FILTER_DriverIRQHandler - def_irq_handler Reserved62_DriverIRQHandler - def_irq_handler Reserved63_DriverIRQHandler - def_irq_handler Reserved64_DriverIRQHandler - def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler - def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler - def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler - def_irq_handler Freqme_DriverIRQHandler - def_irq_handler SEC_VIO_DriverIRQHandler - def_irq_handler SHA_DriverIRQHandler - def_irq_handler PKC_DriverIRQHandler - def_irq_handler PUF_DriverIRQHandler - def_irq_handler POWERQUAD_DriverIRQHandler - def_irq_handler DMA1_DriverIRQHandler - def_irq_handler FLEXCOMM8_DriverIRQHandler - def_irq_handler CDOG_DriverIRQHandler - def_irq_handler Reserved77_DriverIRQHandler - def_irq_handler I3C0_DriverIRQHandler - def_irq_handler Reserved79_DriverIRQHandler - def_irq_handler Reserved80_DriverIRQHandler - def_irq_handler CSS_IRQ1_DriverIRQHandler - def_irq_handler Tamper_DriverIRQHandler - def_irq_handler Analog_Glitch_DriverIRQHandler - def_irq_handler Reserved84_DriverIRQHandler - def_irq_handler Reserved85_DriverIRQHandler - def_irq_handler Reserved86_DriverIRQHandler - def_irq_handler Reserved87_DriverIRQHandler - def_irq_handler Reserved88_DriverIRQHandler - def_irq_handler Reserved89_DriverIRQHandler - def_irq_handler DAC0_DriverIRQHandler - def_irq_handler DAC1_DriverIRQHandler - def_irq_handler DAC2_DriverIRQHandler - def_irq_handler HSCMP0_DriverIRQHandler - def_irq_handler HSCMP1_DriverIRQHandler - def_irq_handler HSCMP2_DriverIRQHandler - def_irq_handler FLEXPWM0_CAPTURE_DriverIRQHandler - def_irq_handler FLEXPWM0_FAULT_DriverIRQHandler - def_irq_handler FLEXPWM0_RELOAD_ERROR_DriverIRQHandler - def_irq_handler FLEXPWM0_COMPARE0_DriverIRQHandler - def_irq_handler FLEXPWM0_RELOAD0_DriverIRQHandler - def_irq_handler FLEXPWM0_COMPARE1_DriverIRQHandler - def_irq_handler FLEXPWM0_RELOAD1_DriverIRQHandler - def_irq_handler FLEXPWM0_COMPARE2_DriverIRQHandler - def_irq_handler FLEXPWM0_RELOAD2_DriverIRQHandler - def_irq_handler FLEXPWM0_COMPARE3_DriverIRQHandler - def_irq_handler FLEXPWM0_RELOAD3_DriverIRQHandler - def_irq_handler FLEXPWM1_CAPTURE_DriverIRQHandler - def_irq_handler FLEXPWM1_FAULT_DriverIRQHandler - def_irq_handler FLEXPWM1_RELOAD_ERROR_DriverIRQHandler - def_irq_handler FLEXPWM1_COMPARE0_DriverIRQHandler - def_irq_handler FLEXPWM1_RELOAD0_DriverIRQHandler - def_irq_handler FLEXPWM1_COMPARE1_DriverIRQHandler - def_irq_handler FLEXPWM1_RELOAD1_DriverIRQHandler - def_irq_handler FLEXPWM1_COMPARE2_DriverIRQHandler - def_irq_handler FLEXPWM1_RELOAD2_DriverIRQHandler - def_irq_handler FLEXPWM1_COMPARE3_DriverIRQHandler - def_irq_handler FLEXPWM1_RELOAD3_DriverIRQHandler - def_irq_handler ENC0_COMPARE_DriverIRQHandler - def_irq_handler ENC0_HOME_DriverIRQHandler - def_irq_handler ENC0_WDG_DriverIRQHandler - def_irq_handler ENC0_IDX_DriverIRQHandler - def_irq_handler ENC1_COMPARE_DriverIRQHandler - def_irq_handler ENC1_HOME_DriverIRQHandler - def_irq_handler ENC1_WDG_DriverIRQHandler - def_irq_handler ENC1_IDX_DriverIRQHandler - def_irq_handler ITRC0_DriverIRQHandler - def_irq_handler Reserved127_DriverIRQHandler - def_irq_handler CSSV2_ERR_DriverIRQHandler - def_irq_handler PKC_ERR_DriverIRQHandler - def_irq_handler Reserved130_DriverIRQHandler - def_irq_handler Reserved131_DriverIRQHandler - def_irq_handler Reserved132_DriverIRQHandler - def_irq_handler Reserved133_DriverIRQHandler - def_irq_handler FLASH_DriverIRQHandler - def_irq_handler RAM_PARITY_ECC_ERR_DriverIRQHandler - - .end diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/iar/LPC55S36_flash.icf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/iar/LPC55S36_flash.icf deleted file mode 100644 index 26a5faafe59..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/iar/LPC55S36_flash.icf +++ /dev/null @@ -1,103 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S36JBD100 -** LPC55S36JHI48 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 -** Version: rev. 1.1, 2021-08-04 -** Build: b210913 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -define symbol usb_bdt_size = 0x0; -/* Stack and Heap Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -if (isdefinedsymbol(__pkc__)) { - define symbol retention_RAMsize = 0x00004000; /* SRAM A(16K) reserved for pkc */ -} else if (isdefinedsymbol(__power_down__)) { - define symbol retention_RAMsize = 0x00000604; /* The first 0x604 bytes reserved to CPU retention for power down mode */ -} else { - define symbol retention_RAMsize = 0x00000000; -} - -if (isdefinedsymbol(__powerquad__)) { - define symbol powerquad_RAMsize = 0x00004000; /* SRAM E(16K) reserved for powerquad */ -} else { - define symbol powerquad_RAMsize = 0x00000000; -} - -define symbol m_interrupts_start = 0x00000000; -define symbol m_interrupts_end = 0x000003FF; - -define symbol m_text_start = 0x00000400; -define symbol m_text_end = 0x0003D7FF; - -define symbol m_data_start = 0x20000000 + retention_RAMsize; -define symbol m_data_end = 0x2001BFFF - powerquad_RAMsize; - -define symbol m_sramx_start = 0x04000000; -define symbol m_sramx_end = 0x04003FFF; - -define memory mem with size = 4G; - -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -if (isdefinedsymbol(__use_shmem__)) { - define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; -} - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - -initialize by copy { readwrite, section .textrw }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - /* Required in a multi-threaded application */ - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -if (isdefinedsymbol(__use_shmem__)) { - do not initialize { section rpmsg_sh_mem_section }; -} - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; - - - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/iar/LPC55S36_ram.icf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/iar/LPC55S36_ram.icf deleted file mode 100644 index 3c235631ab7..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/iar/LPC55S36_ram.icf +++ /dev/null @@ -1,100 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S36JBD100 -** LPC55S36JHI48 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 -** Version: rev. 1.1, 2021-08-04 -** Build: b210913 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -define symbol usb_bdt_size = 0x0; -/* Stack and Heap Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -if (isdefinedsymbol(__pkc__)) { - define symbol retention_RAMsize = 0x00004000; /* SRAM A(16K) reserved for pkc */ -} else if (isdefinedsymbol(__power_down__)) { - define symbol retention_RAMsize = 0x00000604; /* The first 0x604 bytes reserved to CPU retention for power down mode */ -} else { - define symbol retention_RAMsize = 0x00000000; -} - -if (isdefinedsymbol(__powerquad__)) { - define symbol powerquad_RAMsize = 0x00004000; /* SRAM E(16K) reserved for powerquad */ -} else { - define symbol powerquad_RAMsize = 0x00000000; -} - -define symbol m_interrupts_start = 0x20000000 + retention_RAMsize; -define symbol m_interrupts_end = 0x200003FF + retention_RAMsize; - -define symbol m_text_start = 0x20000400 + retention_RAMsize; -define symbol m_text_end = 0x2001BFFF - powerquad_RAMsize; - -define symbol m_data_start = 0x04000000; -define symbol m_data_end = 0x04003FFF; - -define memory mem with size = 4G; - -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -if (isdefinedsymbol(__use_shmem__)) { - define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; -} - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - -initialize by copy { readwrite, section .textrw }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - /* Required in a multi-threaded application */ - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -if (isdefinedsymbol(__use_shmem__)) { - do not initialize { section rpmsg_sh_mem_section }; -} - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; - - - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/iar/startup_LPC55S36.s b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/iar/startup_LPC55S36.s deleted file mode 100644 index 0672289d995..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/iar/startup_LPC55S36.s +++ /dev/null @@ -1,1115 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC55S36.s -; * @purpose: CMSIS Cortex-M33 Core Device Startup File -; * LPC55S36 -; * @version: 1.1 -; * @date: 2021-8-4 -; *---------------------------------------------------------------------------- -; * -; Copyright 1997-2016 Freescale Semiconductor, Inc. -; Copyright 2016-2021 NXP -; All rights reserved. -; -; SPDX-License-Identifier: BSD-3-Clause -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__iar_init$$done: ; The vector table is not needed - ; until after copy initialization is done - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD SecureFault_Handler - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt - DCD DMA0_IRQHandler ; DMA0 controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD ADC0_IRQHandler ; ADC0 - DCD ADC1_IRQHandler ; ADC1 - DCD ACMP_IRQHandler ; ACMP interrupts - DCD DMIC_IRQHandler ; Digital microphone and DMIC subsystem - DCD HWVAD0_IRQHandler ; Hardware Voice Activity Detector - DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt - DCD USB0_IRQHandler ; USB device - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD EZH_ARCH_B0_IRQHandler ; EZH interrupt - DCD WAKEUP_IRQHandler ; Wakeup interrupt - DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int - DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int - DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int - DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int - DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 - DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 - DCD OS_EVENT_IRQHandler ; OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts - DCD FlexSPI0_IRQHandler ; FlexSPI interrupt - DCD Reserved56_IRQHandler ; Reserved interrupt - DCD Reserved57_IRQHandler ; Reserved interrupt - DCD Reserved58_IRQHandler ; Reserved interrupt - DCD CAN0_IRQ0_IRQHandler ; CAN0 interrupt0 - DCD CAN0_IRQ1_IRQHandler ; CAN0 interrupt1 - DCD SPI_FILTER_IRQHandler ; SPI Filter interrupt - DCD Reserved62_IRQHandler ; Reserved interrupt - DCD Reserved63_IRQHandler ; Reserved interrupt - DCD Reserved64_IRQHandler ; Reserved interrupt - DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt - DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT00 interrupt - DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT01 interrupt - DCD Freqme_IRQHandler ; frequency measure interrupt - DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt - DCD SHA_IRQHandler ; SHA interrupt - DCD PKC_IRQHandler ; CASPER interrupt - DCD PUF_IRQHandler ; PUF interrupt - DCD POWERQUAD_IRQHandler ; PowerQuad interrupt - DCD DMA1_IRQHandler ; DMA1 interrupt - DCD FLEXCOMM8_IRQHandler ; LSPI_HS interrupt - DCD CDOG_IRQHandler ; CodeWDG interrupt - DCD Reserved77_IRQHandler ; Reserved interrupt - DCD I3C0_IRQHandler ; I3C interrupt - DCD Reserved79_IRQHandler ; Reserved interrupt - DCD Reserved80_IRQHandler ; Reserved interrupt - DCD CSS_IRQ1_IRQHandler ; CSS_IRQ1 - DCD Tamper_IRQHandler ; Tamper - DCD Analog_Glitch_IRQHandler ; Analog_Glitch - DCD Reserved84_IRQHandler ; Reserved interrupt - DCD Reserved85_IRQHandler ; Reserved interrupt - DCD Reserved86_IRQHandler ; Reserved interrupt - DCD Reserved87_IRQHandler ; Reserved interrupt - DCD Reserved88_IRQHandler ; Reserved interrupt - DCD Reserved89_IRQHandler ; Reserved interrupt - DCD DAC0_IRQHandler ; dac0 interrupt - DCD DAC1_IRQHandler ; dac1 interrupt - DCD DAC2_IRQHandler ; dac2 interrupt - DCD HSCMP0_IRQHandler ; hscmp0 interrupt - DCD HSCMP1_IRQHandler ; hscmp1 interrupt - DCD HSCMP2_IRQHandler ; hscmp2 interrupt - DCD FLEXPWM0_CAPTURE_IRQHandler ; flexpwm0_capture interrupt - DCD FLEXPWM0_FAULT_IRQHandler ; flexpwm0_fault interrupt - DCD FLEXPWM0_RELOAD_ERROR_IRQHandler ; flexpwm0_reload_error interrupt - DCD FLEXPWM0_COMPARE0_IRQHandler ; flexpwm0_compare0 interrupt - DCD FLEXPWM0_RELOAD0_IRQHandler ; flexpwm0_reload0 interrupt - DCD FLEXPWM0_COMPARE1_IRQHandler ; flexpwm0_compare1 interrupt - DCD FLEXPWM0_RELOAD1_IRQHandler ; flexpwm0_reload1 interrupt - DCD FLEXPWM0_COMPARE2_IRQHandler ; flexpwm0_compare2 interrupt - DCD FLEXPWM0_RELOAD2_IRQHandler ; flexpwm0_reload2 interrupt - DCD FLEXPWM0_COMPARE3_IRQHandler ; flexpwm0_compare3 interrupt - DCD FLEXPWM0_RELOAD3_IRQHandler ; flexpwm0_reload3 interrupt - DCD FLEXPWM1_CAPTURE_IRQHandler ; flexpwm1_capture interrupt - DCD FLEXPWM1_FAULT_IRQHandler ; flexpwm1_fault interrupt - DCD FLEXPWM1_RELOAD_ERROR_IRQHandler ; flexpwm1_reload_error interrupt - DCD FLEXPWM1_COMPARE0_IRQHandler ; flexpwm1_compare0 interrupt - DCD FLEXPWM1_RELOAD0_IRQHandler ; flexpwm1_reload0 interrupt - DCD FLEXPWM1_COMPARE1_IRQHandler ; flexpwm1_compare1 interrupt - DCD FLEXPWM1_RELOAD1_IRQHandler ; flexpwm1_reload1 interrupt - DCD FLEXPWM1_COMPARE2_IRQHandler ; flexpwm1_compare2 interrupt - DCD FLEXPWM1_RELOAD2_IRQHandler ; flexpwm1_reload2 interrupt - DCD FLEXPWM1_COMPARE3_IRQHandler ; flexpwm1_compare3 interrupt - DCD FLEXPWM1_RELOAD3_IRQHandler ; flexpwm1_reload3 interrupt - DCD ENC0_COMPARE_IRQHandler ; enc0_compare interrupt - DCD ENC0_HOME_IRQHandler ; enc0_home interrupt - DCD ENC0_WDG_IRQHandler ; enc0_wdg interrupt - DCD ENC0_IDX_IRQHandler ; enc0_idx interrupt - DCD ENC1_COMPARE_IRQHandler ; enc1_compare interrupt - DCD ENC1_HOME_IRQHandler ; enc1_home interrupt - DCD ENC1_WDG_IRQHandler ; enc1_wdg interrupt - DCD ENC1_IDX_IRQHandler ; enc1_idx interrupt - DCD ITRC0_IRQHandler ; itrc0 interrupt - DCD Reserved127_IRQHandler ; Reserved interrupt - DCD CSSV2_ERR_IRQHandler ; cssv2_err interrupt - DCD PKC_ERR_IRQHandler ; pkc_err interrupt - DCD Reserved130_IRQHandler ; Reserved interrupt - DCD Reserved131_IRQHandler ; Reserved interrupt - DCD Reserved132_IRQHandler ; Reserved interrupt - DCD Reserved133_IRQHandler ; Reserved interrupt - DCD FLASH_IRQHandler ; flash interrupt - DCD RAM_PARITY_ECC_ERR_IRQHandler ; ram_parity_ecc_err interrupt -__Vectors_End - - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__vector_table - STR R1, [R0] - LDR R2, [R1] - MSR MSP, R2 - LDR R0, =sfb(CSTACK) - MSR MSPLIM, R0 - CPSIE I ; Unmask interrupts - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SecureFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SecureFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK WDT_BOD_IRQHandler - PUBWEAK WDT_BOD_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -WDT_BOD_IRQHandler - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler - LDR R0, =DMA0_DriverIRQHandler - BX R0 - PUBWEAK GINT0_IRQHandler - PUBWEAK GINT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT0_IRQHandler - LDR R0, =GINT0_DriverIRQHandler - BX R0 - PUBWEAK GINT1_IRQHandler - PUBWEAK GINT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT1_IRQHandler - LDR R0, =GINT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT0_IRQHandler - PUBWEAK PIN_INT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT0_IRQHandler - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT1_IRQHandler - PUBWEAK PIN_INT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT1_IRQHandler - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT2_IRQHandler - PUBWEAK PIN_INT2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT2_IRQHandler - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT3_IRQHandler - PUBWEAK PIN_INT3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT3_IRQHandler - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - PUBWEAK UTICK0_IRQHandler - PUBWEAK UTICK0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UTICK0_IRQHandler - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - PUBWEAK MRT0_IRQHandler - PUBWEAK MRT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -MRT0_IRQHandler - LDR R0, =MRT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER0_IRQHandler - PUBWEAK CTIMER0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER0_IRQHandler - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER1_IRQHandler - PUBWEAK CTIMER1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER1_IRQHandler - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - PUBWEAK SCT0_IRQHandler - PUBWEAK SCT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SCT0_IRQHandler - LDR R0, =SCT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER3_IRQHandler - PUBWEAK CTIMER3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER3_IRQHandler - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM0_IRQHandler - PUBWEAK FLEXCOMM0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM0_IRQHandler - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM1_IRQHandler - PUBWEAK FLEXCOMM1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM1_IRQHandler - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM2_IRQHandler - PUBWEAK FLEXCOMM2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM2_IRQHandler - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM3_IRQHandler - PUBWEAK FLEXCOMM3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM3_IRQHandler - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM4_IRQHandler - PUBWEAK FLEXCOMM4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM4_IRQHandler - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM5_IRQHandler - PUBWEAK FLEXCOMM5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM5_IRQHandler - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM6_IRQHandler - PUBWEAK FLEXCOMM6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM6_IRQHandler - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM7_IRQHandler - PUBWEAK FLEXCOMM7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM7_IRQHandler - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - PUBWEAK ADC0_IRQHandler - PUBWEAK ADC0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_IRQHandler - LDR R0, =ADC0_DriverIRQHandler - BX R0 - PUBWEAK ADC1_IRQHandler - PUBWEAK ADC1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC1_IRQHandler - LDR R0, =ADC1_DriverIRQHandler - BX R0 - PUBWEAK ACMP_IRQHandler - PUBWEAK ACMP_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ACMP_IRQHandler - LDR R0, =ACMP_DriverIRQHandler - BX R0 - PUBWEAK DMIC_IRQHandler - PUBWEAK DMIC_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMIC_IRQHandler - LDR R0, =DMIC_DriverIRQHandler - BX R0 - PUBWEAK HWVAD0_IRQHandler - PUBWEAK HWVAD0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -HWVAD0_IRQHandler - LDR R0, =HWVAD0_DriverIRQHandler - BX R0 - PUBWEAK USB0_NEEDCLK_IRQHandler - PUBWEAK USB0_NEEDCLK_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_NEEDCLK_IRQHandler - LDR R0, =USB0_NEEDCLK_DriverIRQHandler - BX R0 - PUBWEAK USB0_IRQHandler - PUBWEAK USB0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_IRQHandler - LDR R0, =USB0_DriverIRQHandler - BX R0 - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -RTC_IRQHandler - LDR R0, =RTC_DriverIRQHandler - BX R0 - PUBWEAK EZH_ARCH_B0_IRQHandler - PUBWEAK EZH_ARCH_B0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -EZH_ARCH_B0_IRQHandler - LDR R0, =EZH_ARCH_B0_DriverIRQHandler - BX R0 - PUBWEAK WAKEUP_IRQHandler - PUBWEAK WAKEUP_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -WAKEUP_IRQHandler - LDR R0, =WAKEUP_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT4_IRQHandler - PUBWEAK PIN_INT4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT4_IRQHandler - LDR R0, =PIN_INT4_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT5_IRQHandler - PUBWEAK PIN_INT5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT5_IRQHandler - LDR R0, =PIN_INT5_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT6_IRQHandler - PUBWEAK PIN_INT6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT6_IRQHandler - LDR R0, =PIN_INT6_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT7_IRQHandler - PUBWEAK PIN_INT7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT7_IRQHandler - LDR R0, =PIN_INT7_DriverIRQHandler - BX R0 - PUBWEAK CTIMER2_IRQHandler - PUBWEAK CTIMER2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER2_IRQHandler - LDR R0, =CTIMER2_DriverIRQHandler - BX R0 - PUBWEAK CTIMER4_IRQHandler - PUBWEAK CTIMER4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER4_IRQHandler - LDR R0, =CTIMER4_DriverIRQHandler - BX R0 - PUBWEAK OS_EVENT_IRQHandler - PUBWEAK OS_EVENT_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -OS_EVENT_IRQHandler - LDR R0, =OS_EVENT_DriverIRQHandler - BX R0 - PUBWEAK FlexSPI0_IRQHandler - PUBWEAK FlexSPI0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FlexSPI0_IRQHandler - LDR R0, =FlexSPI0_DriverIRQHandler - BX R0 - PUBWEAK Reserved56_IRQHandler - PUBWEAK Reserved56_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved56_IRQHandler - LDR R0, =Reserved56_DriverIRQHandler - BX R0 - PUBWEAK Reserved57_IRQHandler - PUBWEAK Reserved57_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved57_IRQHandler - LDR R0, =Reserved57_DriverIRQHandler - BX R0 - PUBWEAK Reserved58_IRQHandler - PUBWEAK Reserved58_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved58_IRQHandler - LDR R0, =Reserved58_DriverIRQHandler - BX R0 - PUBWEAK CAN0_IRQ0_IRQHandler - PUBWEAK CAN0_IRQ0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CAN0_IRQ0_IRQHandler - LDR R0, =CAN0_IRQ0_DriverIRQHandler - BX R0 - PUBWEAK CAN0_IRQ1_IRQHandler - PUBWEAK CAN0_IRQ1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CAN0_IRQ1_IRQHandler - LDR R0, =CAN0_IRQ1_DriverIRQHandler - BX R0 - PUBWEAK SPI_FILTER_IRQHandler - PUBWEAK SPI_FILTER_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPI_FILTER_IRQHandler - LDR R0, =SPI_FILTER_DriverIRQHandler - BX R0 - PUBWEAK Reserved62_IRQHandler - PUBWEAK Reserved62_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved62_IRQHandler - LDR R0, =Reserved62_DriverIRQHandler - BX R0 - PUBWEAK Reserved63_IRQHandler - PUBWEAK Reserved63_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved63_IRQHandler - LDR R0, =Reserved63_DriverIRQHandler - BX R0 - PUBWEAK Reserved64_IRQHandler - PUBWEAK Reserved64_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved64_IRQHandler - LDR R0, =Reserved64_DriverIRQHandler - BX R0 - PUBWEAK SEC_HYPERVISOR_CALL_IRQHandler - PUBWEAK SEC_HYPERVISOR_CALL_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_HYPERVISOR_CALL_IRQHandler - LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler - BX R0 - PUBWEAK SEC_GPIO_INT0_IRQ0_IRQHandler - PUBWEAK SEC_GPIO_INT0_IRQ0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_GPIO_INT0_IRQ0_IRQHandler - LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler - BX R0 - PUBWEAK SEC_GPIO_INT0_IRQ1_IRQHandler - PUBWEAK SEC_GPIO_INT0_IRQ1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_GPIO_INT0_IRQ1_IRQHandler - LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler - BX R0 - PUBWEAK Freqme_IRQHandler - PUBWEAK Freqme_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Freqme_IRQHandler - LDR R0, =Freqme_DriverIRQHandler - BX R0 - PUBWEAK SEC_VIO_IRQHandler - PUBWEAK SEC_VIO_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_VIO_IRQHandler - LDR R0, =SEC_VIO_DriverIRQHandler - BX R0 - PUBWEAK SHA_IRQHandler - PUBWEAK SHA_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SHA_IRQHandler - LDR R0, =SHA_DriverIRQHandler - BX R0 - PUBWEAK PKC_IRQHandler - PUBWEAK PKC_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PKC_IRQHandler - LDR R0, =PKC_DriverIRQHandler - BX R0 - PUBWEAK PUF_IRQHandler - PUBWEAK PUF_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PUF_IRQHandler - LDR R0, =PUF_DriverIRQHandler - BX R0 - PUBWEAK POWERQUAD_IRQHandler - PUBWEAK POWERQUAD_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -POWERQUAD_IRQHandler - LDR R0, =POWERQUAD_DriverIRQHandler - BX R0 - PUBWEAK DMA1_IRQHandler - PUBWEAK DMA1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA1_IRQHandler - LDR R0, =DMA1_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM8_IRQHandler - PUBWEAK FLEXCOMM8_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM8_IRQHandler - LDR R0, =FLEXCOMM8_DriverIRQHandler - BX R0 - PUBWEAK CDOG_IRQHandler - PUBWEAK CDOG_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CDOG_IRQHandler - LDR R0, =CDOG_DriverIRQHandler - BX R0 - PUBWEAK Reserved77_IRQHandler - PUBWEAK Reserved77_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved77_IRQHandler - LDR R0, =Reserved77_DriverIRQHandler - BX R0 - PUBWEAK I3C0_IRQHandler - PUBWEAK I3C0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I3C0_IRQHandler - LDR R0, =I3C0_DriverIRQHandler - BX R0 - PUBWEAK Reserved79_IRQHandler - PUBWEAK Reserved79_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved79_IRQHandler - LDR R0, =Reserved79_DriverIRQHandler - BX R0 - PUBWEAK Reserved80_IRQHandler - PUBWEAK Reserved80_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved80_IRQHandler - LDR R0, =Reserved80_DriverIRQHandler - BX R0 - PUBWEAK CSS_IRQ1_IRQHandler - PUBWEAK CSS_IRQ1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CSS_IRQ1_IRQHandler - LDR R0, =CSS_IRQ1_DriverIRQHandler - BX R0 - PUBWEAK Tamper_IRQHandler - PUBWEAK Tamper_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Tamper_IRQHandler - LDR R0, =Tamper_DriverIRQHandler - BX R0 - PUBWEAK Analog_Glitch_IRQHandler - PUBWEAK Analog_Glitch_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Analog_Glitch_IRQHandler - LDR R0, =Analog_Glitch_DriverIRQHandler - BX R0 - PUBWEAK Reserved84_IRQHandler - PUBWEAK Reserved84_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved84_IRQHandler - LDR R0, =Reserved84_DriverIRQHandler - BX R0 - PUBWEAK Reserved85_IRQHandler - PUBWEAK Reserved85_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved85_IRQHandler - LDR R0, =Reserved85_DriverIRQHandler - BX R0 - PUBWEAK Reserved86_IRQHandler - PUBWEAK Reserved86_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved86_IRQHandler - LDR R0, =Reserved86_DriverIRQHandler - BX R0 - PUBWEAK Reserved87_IRQHandler - PUBWEAK Reserved87_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved87_IRQHandler - LDR R0, =Reserved87_DriverIRQHandler - BX R0 - PUBWEAK Reserved88_IRQHandler - PUBWEAK Reserved88_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved88_IRQHandler - LDR R0, =Reserved88_DriverIRQHandler - BX R0 - PUBWEAK Reserved89_IRQHandler - PUBWEAK Reserved89_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved89_IRQHandler - LDR R0, =Reserved89_DriverIRQHandler - BX R0 - PUBWEAK DAC0_IRQHandler - PUBWEAK DAC0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DAC0_IRQHandler - LDR R0, =DAC0_DriverIRQHandler - BX R0 - PUBWEAK DAC1_IRQHandler - PUBWEAK DAC1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DAC1_IRQHandler - LDR R0, =DAC1_DriverIRQHandler - BX R0 - PUBWEAK DAC2_IRQHandler - PUBWEAK DAC2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DAC2_IRQHandler - LDR R0, =DAC2_DriverIRQHandler - BX R0 - PUBWEAK HSCMP0_IRQHandler - PUBWEAK HSCMP0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -HSCMP0_IRQHandler - LDR R0, =HSCMP0_DriverIRQHandler - BX R0 - PUBWEAK HSCMP1_IRQHandler - PUBWEAK HSCMP1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -HSCMP1_IRQHandler - LDR R0, =HSCMP1_DriverIRQHandler - BX R0 - PUBWEAK HSCMP2_IRQHandler - PUBWEAK HSCMP2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -HSCMP2_IRQHandler - LDR R0, =HSCMP2_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM0_CAPTURE_IRQHandler - PUBWEAK FLEXPWM0_CAPTURE_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM0_CAPTURE_IRQHandler - LDR R0, =FLEXPWM0_CAPTURE_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM0_FAULT_IRQHandler - PUBWEAK FLEXPWM0_FAULT_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM0_FAULT_IRQHandler - LDR R0, =FLEXPWM0_FAULT_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM0_RELOAD_ERROR_IRQHandler - PUBWEAK FLEXPWM0_RELOAD_ERROR_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM0_RELOAD_ERROR_IRQHandler - LDR R0, =FLEXPWM0_RELOAD_ERROR_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM0_COMPARE0_IRQHandler - PUBWEAK FLEXPWM0_COMPARE0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM0_COMPARE0_IRQHandler - LDR R0, =FLEXPWM0_COMPARE0_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM0_RELOAD0_IRQHandler - PUBWEAK FLEXPWM0_RELOAD0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM0_RELOAD0_IRQHandler - LDR R0, =FLEXPWM0_RELOAD0_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM0_COMPARE1_IRQHandler - PUBWEAK FLEXPWM0_COMPARE1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM0_COMPARE1_IRQHandler - LDR R0, =FLEXPWM0_COMPARE1_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM0_RELOAD1_IRQHandler - PUBWEAK FLEXPWM0_RELOAD1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM0_RELOAD1_IRQHandler - LDR R0, =FLEXPWM0_RELOAD1_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM0_COMPARE2_IRQHandler - PUBWEAK FLEXPWM0_COMPARE2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM0_COMPARE2_IRQHandler - LDR R0, =FLEXPWM0_COMPARE2_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM0_RELOAD2_IRQHandler - PUBWEAK FLEXPWM0_RELOAD2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM0_RELOAD2_IRQHandler - LDR R0, =FLEXPWM0_RELOAD2_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM0_COMPARE3_IRQHandler - PUBWEAK FLEXPWM0_COMPARE3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM0_COMPARE3_IRQHandler - LDR R0, =FLEXPWM0_COMPARE3_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM0_RELOAD3_IRQHandler - PUBWEAK FLEXPWM0_RELOAD3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM0_RELOAD3_IRQHandler - LDR R0, =FLEXPWM0_RELOAD3_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM1_CAPTURE_IRQHandler - PUBWEAK FLEXPWM1_CAPTURE_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM1_CAPTURE_IRQHandler - LDR R0, =FLEXPWM1_CAPTURE_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM1_FAULT_IRQHandler - PUBWEAK FLEXPWM1_FAULT_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM1_FAULT_IRQHandler - LDR R0, =FLEXPWM1_FAULT_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM1_RELOAD_ERROR_IRQHandler - PUBWEAK FLEXPWM1_RELOAD_ERROR_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM1_RELOAD_ERROR_IRQHandler - LDR R0, =FLEXPWM1_RELOAD_ERROR_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM1_COMPARE0_IRQHandler - PUBWEAK FLEXPWM1_COMPARE0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM1_COMPARE0_IRQHandler - LDR R0, =FLEXPWM1_COMPARE0_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM1_RELOAD0_IRQHandler - PUBWEAK FLEXPWM1_RELOAD0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM1_RELOAD0_IRQHandler - LDR R0, =FLEXPWM1_RELOAD0_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM1_COMPARE1_IRQHandler - PUBWEAK FLEXPWM1_COMPARE1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM1_COMPARE1_IRQHandler - LDR R0, =FLEXPWM1_COMPARE1_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM1_RELOAD1_IRQHandler - PUBWEAK FLEXPWM1_RELOAD1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM1_RELOAD1_IRQHandler - LDR R0, =FLEXPWM1_RELOAD1_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM1_COMPARE2_IRQHandler - PUBWEAK FLEXPWM1_COMPARE2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM1_COMPARE2_IRQHandler - LDR R0, =FLEXPWM1_COMPARE2_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM1_RELOAD2_IRQHandler - PUBWEAK FLEXPWM1_RELOAD2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM1_RELOAD2_IRQHandler - LDR R0, =FLEXPWM1_RELOAD2_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM1_COMPARE3_IRQHandler - PUBWEAK FLEXPWM1_COMPARE3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM1_COMPARE3_IRQHandler - LDR R0, =FLEXPWM1_COMPARE3_DriverIRQHandler - BX R0 - PUBWEAK FLEXPWM1_RELOAD3_IRQHandler - PUBWEAK FLEXPWM1_RELOAD3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXPWM1_RELOAD3_IRQHandler - LDR R0, =FLEXPWM1_RELOAD3_DriverIRQHandler - BX R0 - PUBWEAK ENC0_COMPARE_IRQHandler - PUBWEAK ENC0_COMPARE_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ENC0_COMPARE_IRQHandler - LDR R0, =ENC0_COMPARE_DriverIRQHandler - BX R0 - PUBWEAK ENC0_HOME_IRQHandler - PUBWEAK ENC0_HOME_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ENC0_HOME_IRQHandler - LDR R0, =ENC0_HOME_DriverIRQHandler - BX R0 - PUBWEAK ENC0_WDG_IRQHandler - PUBWEAK ENC0_WDG_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ENC0_WDG_IRQHandler - LDR R0, =ENC0_WDG_DriverIRQHandler - BX R0 - PUBWEAK ENC0_IDX_IRQHandler - PUBWEAK ENC0_IDX_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ENC0_IDX_IRQHandler - LDR R0, =ENC0_IDX_DriverIRQHandler - BX R0 - PUBWEAK ENC1_COMPARE_IRQHandler - PUBWEAK ENC1_COMPARE_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ENC1_COMPARE_IRQHandler - LDR R0, =ENC1_COMPARE_DriverIRQHandler - BX R0 - PUBWEAK ENC1_HOME_IRQHandler - PUBWEAK ENC1_HOME_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ENC1_HOME_IRQHandler - LDR R0, =ENC1_HOME_DriverIRQHandler - BX R0 - PUBWEAK ENC1_WDG_IRQHandler - PUBWEAK ENC1_WDG_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ENC1_WDG_IRQHandler - LDR R0, =ENC1_WDG_DriverIRQHandler - BX R0 - PUBWEAK ENC1_IDX_IRQHandler - PUBWEAK ENC1_IDX_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ENC1_IDX_IRQHandler - LDR R0, =ENC1_IDX_DriverIRQHandler - BX R0 - PUBWEAK ITRC0_IRQHandler - PUBWEAK ITRC0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ITRC0_IRQHandler - LDR R0, =ITRC0_DriverIRQHandler - BX R0 - PUBWEAK Reserved127_IRQHandler - PUBWEAK Reserved127_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved127_IRQHandler - LDR R0, =Reserved127_DriverIRQHandler - BX R0 - PUBWEAK CSSV2_ERR_IRQHandler - PUBWEAK CSSV2_ERR_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CSSV2_ERR_IRQHandler - LDR R0, =CSSV2_ERR_DriverIRQHandler - BX R0 - PUBWEAK PKC_ERR_IRQHandler - PUBWEAK PKC_ERR_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PKC_ERR_IRQHandler - LDR R0, =PKC_ERR_DriverIRQHandler - BX R0 - PUBWEAK Reserved130_IRQHandler - PUBWEAK Reserved130_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved130_IRQHandler - LDR R0, =Reserved130_DriverIRQHandler - BX R0 - PUBWEAK Reserved131_IRQHandler - PUBWEAK Reserved131_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved131_IRQHandler - LDR R0, =Reserved131_DriverIRQHandler - BX R0 - PUBWEAK Reserved132_IRQHandler - PUBWEAK Reserved132_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved132_IRQHandler - LDR R0, =Reserved132_DriverIRQHandler - BX R0 - PUBWEAK Reserved133_IRQHandler - PUBWEAK Reserved133_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved133_IRQHandler - LDR R0, =Reserved133_DriverIRQHandler - BX R0 - PUBWEAK FLASH_IRQHandler - PUBWEAK FLASH_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLASH_IRQHandler - LDR R0, =FLASH_DriverIRQHandler - BX R0 - PUBWEAK RAM_PARITY_ECC_ERR_IRQHandler - PUBWEAK RAM_PARITY_ECC_ERR_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -RAM_PARITY_ECC_ERR_IRQHandler - LDR R0, =RAM_PARITY_ECC_ERR_DriverIRQHandler - BX R0 -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_DriverIRQHandler -ADC1_DriverIRQHandler -ACMP_DriverIRQHandler -DMIC_DriverIRQHandler -HWVAD0_DriverIRQHandler -USB0_NEEDCLK_DriverIRQHandler -USB0_DriverIRQHandler -RTC_DriverIRQHandler -EZH_ARCH_B0_DriverIRQHandler -WAKEUP_DriverIRQHandler -PIN_INT4_DriverIRQHandler -PIN_INT5_DriverIRQHandler -PIN_INT6_DriverIRQHandler -PIN_INT7_DriverIRQHandler -CTIMER2_DriverIRQHandler -CTIMER4_DriverIRQHandler -OS_EVENT_DriverIRQHandler -FlexSPI0_DriverIRQHandler -Reserved56_DriverIRQHandler -Reserved57_DriverIRQHandler -Reserved58_DriverIRQHandler -CAN0_IRQ0_DriverIRQHandler -CAN0_IRQ1_DriverIRQHandler -SPI_FILTER_DriverIRQHandler -Reserved62_DriverIRQHandler -Reserved63_DriverIRQHandler -Reserved64_DriverIRQHandler -SEC_HYPERVISOR_CALL_DriverIRQHandler -SEC_GPIO_INT0_IRQ0_DriverIRQHandler -SEC_GPIO_INT0_IRQ1_DriverIRQHandler -Freqme_DriverIRQHandler -SEC_VIO_DriverIRQHandler -SHA_DriverIRQHandler -PKC_DriverIRQHandler -PUF_DriverIRQHandler -POWERQUAD_DriverIRQHandler -DMA1_DriverIRQHandler -FLEXCOMM8_DriverIRQHandler -CDOG_DriverIRQHandler -Reserved77_DriverIRQHandler -I3C0_DriverIRQHandler -Reserved79_DriverIRQHandler -Reserved80_DriverIRQHandler -CSS_IRQ1_DriverIRQHandler -Tamper_DriverIRQHandler -Analog_Glitch_DriverIRQHandler -Reserved84_DriverIRQHandler -Reserved85_DriverIRQHandler -Reserved86_DriverIRQHandler -Reserved87_DriverIRQHandler -Reserved88_DriverIRQHandler -Reserved89_DriverIRQHandler -DAC0_DriverIRQHandler -DAC1_DriverIRQHandler -DAC2_DriverIRQHandler -HSCMP0_DriverIRQHandler -HSCMP1_DriverIRQHandler -HSCMP2_DriverIRQHandler -FLEXPWM0_CAPTURE_DriverIRQHandler -FLEXPWM0_FAULT_DriverIRQHandler -FLEXPWM0_RELOAD_ERROR_DriverIRQHandler -FLEXPWM0_COMPARE0_DriverIRQHandler -FLEXPWM0_RELOAD0_DriverIRQHandler -FLEXPWM0_COMPARE1_DriverIRQHandler -FLEXPWM0_RELOAD1_DriverIRQHandler -FLEXPWM0_COMPARE2_DriverIRQHandler -FLEXPWM0_RELOAD2_DriverIRQHandler -FLEXPWM0_COMPARE3_DriverIRQHandler -FLEXPWM0_RELOAD3_DriverIRQHandler -FLEXPWM1_CAPTURE_DriverIRQHandler -FLEXPWM1_FAULT_DriverIRQHandler -FLEXPWM1_RELOAD_ERROR_DriverIRQHandler -FLEXPWM1_COMPARE0_DriverIRQHandler -FLEXPWM1_RELOAD0_DriverIRQHandler -FLEXPWM1_COMPARE1_DriverIRQHandler -FLEXPWM1_RELOAD1_DriverIRQHandler -FLEXPWM1_COMPARE2_DriverIRQHandler -FLEXPWM1_RELOAD2_DriverIRQHandler -FLEXPWM1_COMPARE3_DriverIRQHandler -FLEXPWM1_RELOAD3_DriverIRQHandler -ENC0_COMPARE_DriverIRQHandler -ENC0_HOME_DriverIRQHandler -ENC0_WDG_DriverIRQHandler -ENC0_IDX_DriverIRQHandler -ENC1_COMPARE_DriverIRQHandler -ENC1_HOME_DriverIRQHandler -ENC1_WDG_DriverIRQHandler -ENC1_IDX_DriverIRQHandler -ITRC0_DriverIRQHandler -Reserved127_DriverIRQHandler -CSSV2_ERR_DriverIRQHandler -PKC_ERR_DriverIRQHandler -Reserved130_DriverIRQHandler -Reserved131_DriverIRQHandler -Reserved132_DriverIRQHandler -Reserved133_DriverIRQHandler -FLASH_DriverIRQHandler -RAM_PARITY_ECC_ERR_DriverIRQHandler -DefaultISR - B . - - END diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/system_LPC55S36.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/system_LPC55S36.c deleted file mode 100644 index ac2fee6e893..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/system_LPC55S36.c +++ /dev/null @@ -1,112 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S36JBD100 -** LPC55S36JHI48 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 -** Version: rev. 1.1, 2021-08-04 -** Build: b210806 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2021-04-12) -** Initial version based on RM DraftF -** - rev. 1.1 (2021-08-04) -** Initial version based on RM DraftG -** -** ################################################################### -*/ - -/*! - * @file LPC55S36 - * @version 1.1 - * @date 2021-08-04 - * @brief Device specific configuration file for LPC55S36 (implementation file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include -#include "fsl_device_registers.h" - - - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ - -__attribute__ ((weak)) void SystemInit (void) { -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ - #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ - - SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ - -#if defined(__MCUXPRESSO) - extern void(*const g_pfnVectors[]) (void); - SCB->VTOR = (uint32_t) &g_pfnVectors; -#else - extern void *__Vectors; - SCB->VTOR = (uint32_t) &__Vectors; -#endif - SYSCON->TRACECLKDIV = 0; -/* Optionally enable RAM banks that may be off by default at reset */ -#if !defined(DONT_ENABLE_DISABLED_RAMBANKS) - SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK - | SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK; -#endif -/* enable the flash cache LPCAC */ - SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; - - SystemInitHook(); -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate (void) { - -} - -/* ---------------------------------------------------------------------------- - -- SystemInitHook() - ---------------------------------------------------------------------------- */ - -__attribute__ ((weak)) void SystemInitHook (void) { - /* Void implementation of the weak function. */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/system_LPC55S36.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/system_LPC55S36.h deleted file mode 100644 index a00ade0b22f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/LPC55S36/system_LPC55S36.h +++ /dev/null @@ -1,111 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S36JBD100 -** LPC55S36JHI48 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 -** Version: rev. 1.1, 2021-08-04 -** Build: b210806 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2021-04-12) -** Initial version based on RM DraftF -** - rev. 1.1 (2021-08-04) -** Initial version based on RM DraftG -** -** ################################################################### -*/ - -/*! - * @file LPC55S36 - * @version 1.1 - * @date 2021-08-04 - * @brief Device specific configuration file for LPC55S36 (header file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef _SYSTEM_LPC55S36_H_ -#define _SYSTEM_LPC55S36_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ -#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ -#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ -#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ -#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ -#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ - - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -/** - * @brief SystemInit function hook. - * - * This weak function allows to call specific initialization code during the - * SystemInit() execution.This can be used when an application specific code needs - * to be called as close to the reset entry as possible (for example the Multicore - * Manager MCMGR_EarlyInit() function call). - * NOTE: No global r/w variables can be used in this hook function because the - * initialization of these variables happens after this function. - */ -void SystemInitHook (void); - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_LPC55S36_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/SConscript b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/SConscript deleted file mode 100644 index edc35e422b7..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S36/SConscript +++ /dev/null @@ -1,51 +0,0 @@ -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -path = [cwd + '/../CMSIS/Core/Include',cwd + '/components/codec', cwd + '/LPC55S36', cwd + '/LPC55S36/drivers', cwd + '/middleware/sdmmc/inc', cwd + '/middleware/sdmmc/port'] -src = Split(''' - LPC55S36/system_LPC55S36.c - ''') - -if rtconfig.PLATFORM in ['gcc']: - src += ['LPC55S36/gcc/startup_LPC55S36.S'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - src += ['LPC55S36/arm/startup_LPC55S36.s'] -elif rtconfig.PLATFORM in ['iccarm']: - src += ['LPC55S36/iar/startup_LPC55S36.s'] - -src += ['LPC55S36/drivers/fsl_anactrl.c'] -src += ['LPC55S36/drivers/fsl_clock.c'] -src += ['LPC55S36/drivers/fsl_cmp.c'] -src += ['LPC55S36/drivers/fsl_common.c'] -src += ['LPC55S36/drivers/fsl_common_arm.c'] -src += ['LPC55S36/drivers/fsl_crc.c'] -src += ['LPC55S36/drivers/fsl_ctimer.c'] -src += ['LPC55S36/drivers/fsl_flexcomm.c'] -src += ['LPC55S36/drivers/fsl_dma.c'] -src += ['LPC55S36/drivers/fsl_gint.c'] -src += ['LPC55S36/drivers/fsl_gpio.c'] -src += ['LPC55S36/drivers/fsl_i2c.c'] -src += ['LPC55S36/drivers/fsl_i2c_dma.c'] -src += ['LPC55S36/drivers/fsl_i2s.c'] -src += ['LPC55S36/drivers/fsl_i2s_dma.c'] -src += ['LPC55S36/drivers/fsl_inputmux.c'] -src += ['LPC55S36/drivers/fsl_lpadc.c'] -src += ['LPC55S36/drivers/fsl_mrt.c'] -src += ['LPC55S36/drivers/fsl_ostimer.c'] -src += ['LPC55S36/drivers/fsl_pint.c'] -src += ['LPC55S36/drivers/fsl_power.c'] -src += ['LPC55S36/drivers/fsl_reset.c'] -src += ['LPC55S36/drivers/fsl_sctimer.c'] -src += ['LPC55S36/drivers/fsl_spi.c'] -src += ['LPC55S36/drivers/fsl_spi_dma.c'] -src += ['LPC55S36/drivers/fsl_sysctl.c'] -src += ['LPC55S36/drivers/fsl_usart.c'] -src += ['LPC55S36/drivers/fsl_usart_dma.c'] -src += ['LPC55S36/drivers/fsl_utick.c'] -src += ['LPC55S36/drivers/fsl_wwdt.c'] - - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) - -Return('group') diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.h deleted file mode 100644 index 10871c87a0d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.h +++ /dev/null @@ -1,31239 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JBD64_cm33_core0 -** LPC55S69JEV98_cm33_core0 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b211009 -** -** Abstract: -** CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 -** -** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** - rev. 1.1 (2019-05-16) -** Initial A1 version based on v1.3UM -** -** ################################################################### -*/ - -/*! - * @file LPC55S69_cm33_core0.h - * @version 1.1 - * @date 2019-05-16 - * @brief CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 - * - * CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 - */ - -#ifndef _LPC55S69_CM33_CORE0_H_ -#define _LPC55S69_CM33_CORE0_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0001U - - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 76 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Auxiliary constants */ - NotAvail_IRQn = -128, /**< Not available device specific interrupt */ - - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ - - /* Device specific interrupts */ - WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */ - DMA0_IRQn = 1, /**< DMA0 controller */ - GINT0_IRQn = 2, /**< GPIO group 0 */ - GINT1_IRQn = 3, /**< GPIO group 1 */ - PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ - PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ - PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ - PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ - UTICK0_IRQn = 8, /**< Micro-tick Timer */ - MRT0_IRQn = 9, /**< Multi-rate timer */ - CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ - CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ - SCT0_IRQn = 12, /**< SCTimer/PWM */ - CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ - FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - ADC0_IRQn = 22, /**< ADC0 */ - Reserved39_IRQn = 23, /**< Reserved interrupt */ - ACMP_IRQn = 24, /**< ACMP interrupts */ - Reserved41_IRQn = 25, /**< Reserved interrupt */ - Reserved42_IRQn = 26, /**< Reserved interrupt */ - USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ - USB0_IRQn = 28, /**< USB device */ - RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ - Reserved46_IRQn = 30, /**< Reserved interrupt */ - MAILBOX_IRQn = 31, /**< WAKEUP,Mailbox interrupt (present on selected devices) */ - PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ - PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ - PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ - PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ - CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ - CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ - OS_EVENT_IRQn = 38, /**< OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ - Reserved55_IRQn = 39, /**< Reserved interrupt */ - Reserved56_IRQn = 40, /**< Reserved interrupt */ - Reserved57_IRQn = 41, /**< Reserved interrupt */ - SDIO_IRQn = 42, /**< SD/MMC */ - Reserved59_IRQn = 43, /**< Reserved interrupt */ - Reserved60_IRQn = 44, /**< Reserved interrupt */ - Reserved61_IRQn = 45, /**< Reserved interrupt */ - USB1_PHY_IRQn = 46, /**< USB1_PHY */ - USB1_IRQn = 47, /**< USB1 interrupt */ - USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ - SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */ - SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */ - SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */ - PLU_IRQn = 52, /**< PLU interrupt */ - SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */ - HASHCRYPT_IRQn = 54, /**< HASHCRYPT interrupt */ - CASER_IRQn = 55, /**< CASPER interrupt */ - PUF_IRQn = 56, /**< PUF interrupt */ - PQ_IRQn = 57, /**< PQ interrupt */ - DMA1_IRQn = 58, /**< DMA1 interrupt */ - FLEXCOMM8_IRQn = 59 /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M33 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration - * @{ - */ - -#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ -#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ -#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ -#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ - -#include "core_cm33.h" /* Core Peripheral Access Layer */ -#include "system_LPC55S69_cm33_core0.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Mapping Information - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Mapping_Information Mapping Information - * @{ - */ - -/** Mapping Information */ -/*! - * @addtogroup dma_request - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief Structure for the DMA hardware request - * - * Defines the structure for the DMA hardware request collections. The user can configure the - * hardware request to trigger the DMA transfer accordingly. The index - * of the hardware request varies according to the to SoC. - */ -typedef enum _dma_request_source -{ - kDma0RequestHashCrypt = 0U, /**< HashCrypt */ - kDma1RequestHashCrypt = 0U, /**< HashCrypt */ - kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ - kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ - kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ - kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ - kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ - kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ - kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ - kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ - kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ - kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ - kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ - kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ - kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ - kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ - kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ - kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ - kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ - kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ - kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */ - kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */ - kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */ - kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */ - kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */ - kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */ - kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */ - kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */ - kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */ - kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */ - kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */ - kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */ - kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */ -} dma_request_source_t; - -/* @} */ - - -/*! - * @} - */ /* end of group Mapping_Information */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #else - #pragma push - #pragma anon_unions - #endif -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ - __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ - __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ - __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ - __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ - __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ - uint8_t RESERVED_1[12]; - __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ - __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ - uint8_t RESERVED_2[4]; - __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ - uint8_t RESERVED_3[92]; - __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ - __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ - uint8_t RESERVED_4[8]; - __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ - __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ - struct { /* offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ - } CMD[15]; - uint8_t RESERVED_5[136]; - __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_6[240]; - __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ - uint8_t RESERVED_7[248]; - __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ - uint8_t RESERVED_8[124]; - __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */ - uint8_t RESERVED_9[2680]; - __IO uint32_t TST; /**< ADC Test Register, offset: 0xFFC */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ - -#define ADC_VERID_RES_MASK (0x1U) -#define ADC_VERID_RES_SHIFT (0U) -/*! RES - Resolution - * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. - * 0b1..Up to 16-bit differential/16-bit single ended resolution supported. - */ -#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) - -#define ADC_VERID_DIFFEN_MASK (0x2U) -#define ADC_VERID_DIFFEN_SHIFT (1U) -/*! DIFFEN - Differential Supported - * 0b0..Differential operation not supported. - * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented. - */ -#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) - -#define ADC_VERID_MVI_MASK (0x8U) -#define ADC_VERID_MVI_SHIFT (3U) -/*! MVI - Multi Vref Implemented - * 0b0..Single voltage reference high (VREFH) input supported. - * 0b1..Multiple voltage reference high (VREFH) inputs supported. - */ -#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) - -#define ADC_VERID_CSW_MASK (0x70U) -#define ADC_VERID_CSW_SHIFT (4U) -/*! CSW - Channel Scale Width - * 0b000..Channel scaling not supported. - * 0b001..Channel scaling supported. 1-bit CSCALE control field. - * 0b110..Channel scaling supported. 6-bit CSCALE control field. - */ -#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) - -#define ADC_VERID_VR1RNGI_MASK (0x100U) -#define ADC_VERID_VR1RNGI_SHIFT (8U) -/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented - * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. - * 0b1..Range control required. CFG[VREF1RNG] is implemented. - */ -#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) - -#define ADC_VERID_IADCKI_MASK (0x200U) -#define ADC_VERID_IADCKI_SHIFT (9U) -/*! IADCKI - Internal ADC Clock implemented - * 0b0..Internal clock source not implemented. - * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. - */ -#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) - -#define ADC_VERID_CALOFSI_MASK (0x400U) -#define ADC_VERID_CALOFSI_SHIFT (10U) -/*! CALOFSI - Calibration Function Implemented - * 0b0..Calibration Not Implemented. - * 0b1..Calibration Implemented. - */ -#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) - -#define ADC_VERID_NUM_SEC_MASK (0x800U) -#define ADC_VERID_NUM_SEC_SHIFT (11U) -/*! NUM_SEC - Number of Single Ended Outputs Supported - * 0b0..This design supports one single ended conversion at a time. - * 0b1..This design supports two simultanious single ended conversions. - */ -#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) - -#define ADC_VERID_NUM_FIFO_MASK (0x7000U) -#define ADC_VERID_NUM_FIFO_SHIFT (12U) -/*! NUM_FIFO - Number of FIFOs - * 0b000..N/A - * 0b001..This design supports one result FIFO. - * 0b010..This design supports two result FIFOs. - * 0b011..This design supports three result FIFOs. - * 0b100..This design supports four result FIFOs. - */ -#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) - -#define ADC_VERID_MINOR_MASK (0xFF0000U) -#define ADC_VERID_MINOR_SHIFT (16U) -/*! MINOR - Minor Version Number - */ -#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) - -#define ADC_VERID_MAJOR_MASK (0xFF000000U) -#define ADC_VERID_MAJOR_SHIFT (24U) -/*! MAJOR - Major Version Number - */ -#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ - -#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) -#define ADC_PARAM_TRIG_NUM_SHIFT (0U) -/*! TRIG_NUM - Trigger Number - */ -#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) - -#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) -#define ADC_PARAM_FIFOSIZE_SHIFT (8U) -/*! FIFOSIZE - Result FIFO Depth - * 0b00000001..Result FIFO depth = 1 dataword. - * 0b00000100..Result FIFO depth = 4 datawords. - * 0b00001000..Result FIFO depth = 8 datawords. - * 0b00010000..Result FIFO depth = 16 datawords. - * 0b00100000..Result FIFO depth = 32 datawords. - * 0b01000000..Result FIFO depth = 64 datawords. - */ -#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) - -#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) -#define ADC_PARAM_CV_NUM_SHIFT (16U) -/*! CV_NUM - Compare Value Number - */ -#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) - -#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) -#define ADC_PARAM_CMD_NUM_SHIFT (24U) -/*! CMD_NUM - Command Buffer Number - */ -#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) -/*! @} */ - -/*! @name CTRL - ADC Control Register */ -/*! @{ */ - -#define ADC_CTRL_ADCEN_MASK (0x1U) -#define ADC_CTRL_ADCEN_SHIFT (0U) -/*! ADCEN - ADC Enable - * 0b0..ADC is disabled. - * 0b1..ADC is enabled. - */ -#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) - -#define ADC_CTRL_RST_MASK (0x2U) -#define ADC_CTRL_RST_SHIFT (1U) -/*! RST - Software Reset - * 0b0..ADC logic is not reset. - * 0b1..ADC logic is reset. - */ -#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) - -#define ADC_CTRL_DOZEN_MASK (0x4U) -#define ADC_CTRL_DOZEN_SHIFT (2U) -/*! DOZEN - Doze Enable - * 0b0..ADC is enabled in Doze mode. - * 0b1..ADC is disabled in Doze mode. - */ -#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) - -#define ADC_CTRL_CAL_REQ_MASK (0x8U) -#define ADC_CTRL_CAL_REQ_SHIFT (3U) -/*! CAL_REQ - Auto-Calibration Request - * 0b0..No request for auto-calibration has been made. - * 0b1..A request for auto-calibration has been made - */ -#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) - -#define ADC_CTRL_CALOFS_MASK (0x10U) -#define ADC_CTRL_CALOFS_SHIFT (4U) -/*! CALOFS - Configure for offset calibration function - * 0b0..Calibration function disabled - * 0b1..Request for offset calibration function - */ -#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) - -#define ADC_CTRL_RSTFIFO0_MASK (0x100U) -#define ADC_CTRL_RSTFIFO0_SHIFT (8U) -/*! RSTFIFO0 - Reset FIFO 0 - * 0b0..No effect. - * 0b1..FIFO 0 is reset. - */ -#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) - -#define ADC_CTRL_RSTFIFO1_MASK (0x200U) -#define ADC_CTRL_RSTFIFO1_SHIFT (9U) -/*! RSTFIFO1 - Reset FIFO 1 - * 0b0..No effect. - * 0b1..FIFO 1 is reset. - */ -#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) - -#define ADC_CTRL_CAL_AVGS_MASK (0x70000U) -#define ADC_CTRL_CAL_AVGS_SHIFT (16U) -/*! CAL_AVGS - Auto-Calibration Averages - * 0b000..Single conversion. - * 0b001..2 conversions averaged. - * 0b010..4 conversions averaged. - * 0b011..8 conversions averaged. - * 0b100..16 conversions averaged. - * 0b101..32 conversions averaged. - * 0b110..64 conversions averaged. - * 0b111..128 conversions averaged. - */ -#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) -/*! @} */ - -/*! @name STAT - ADC Status Register */ -/*! @{ */ - -#define ADC_STAT_RDY0_MASK (0x1U) -#define ADC_STAT_RDY0_SHIFT (0U) -/*! RDY0 - Result FIFO 0 Ready Flag - * 0b0..Result FIFO 0 data level not above watermark level. - * 0b1..Result FIFO 0 holding data above watermark level. - */ -#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) - -#define ADC_STAT_FOF0_MASK (0x2U) -#define ADC_STAT_FOF0_SHIFT (1U) -/*! FOF0 - Result FIFO 0 Overflow Flag - * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) - -#define ADC_STAT_RDY1_MASK (0x4U) -#define ADC_STAT_RDY1_SHIFT (2U) -/*! RDY1 - Result FIFO1 Ready Flag - * 0b0..Result FIFO1 data level not above watermark level. - * 0b1..Result FIFO1 holding data above watermark level. - */ -#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) - -#define ADC_STAT_FOF1_MASK (0x8U) -#define ADC_STAT_FOF1_SHIFT (3U) -/*! FOF1 - Result FIFO1 Overflow Flag - * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) - -#define ADC_STAT_TEXC_INT_MASK (0x100U) -#define ADC_STAT_TEXC_INT_SHIFT (8U) -/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception - * 0b0..No trigger exceptions have occurred. - * 0b1..A trigger exception has occurred and is pending acknowledgement. - */ -#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) - -#define ADC_STAT_TCOMP_INT_MASK (0x200U) -#define ADC_STAT_TCOMP_INT_SHIFT (9U) -/*! TCOMP_INT - Interrupt Flag For Trigger Completion - * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. - * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. - */ -#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) - -#define ADC_STAT_CAL_RDY_MASK (0x400U) -#define ADC_STAT_CAL_RDY_SHIFT (10U) -/*! CAL_RDY - Calibration Ready - * 0b0..Calibration is incomplete or hasn't been ran. - * 0b1..The ADC is calibrated. - */ -#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) - -#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) -#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) -/*! ADC_ACTIVE - ADC Active - * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. - * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. - */ -#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) - -#define ADC_STAT_TRGACT_MASK (0xF0000U) -#define ADC_STAT_TRGACT_SHIFT (16U) -/*! TRGACT - Trigger Active - * 0b0000..Command (sequence) associated with Trigger 0 currently being executed. - * 0b0001..Command (sequence) associated with Trigger 1 currently being executed. - * 0b0010..Command (sequence) associated with Trigger 2 currently being executed. - * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed. - */ -#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) - -#define ADC_STAT_CMDACT_MASK (0xF000000U) -#define ADC_STAT_CMDACT_SHIFT (24U) -/*! CMDACT - Command Active - * 0b0000..No command is currently in progress. - * 0b0001..Command 1 currently being executed. - * 0b0010..Command 2 currently being executed. - * 0b0011-0b1111..Associated command number is currently being executed. - */ -#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) -/*! @} */ - -/*! @name IE - Interrupt Enable Register */ -/*! @{ */ - -#define ADC_IE_FWMIE0_MASK (0x1U) -#define ADC_IE_FWMIE0_SHIFT (0U) -/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable - * 0b0..FIFO 0 watermark interrupts are not enabled. - * 0b1..FIFO 0 watermark interrupts are enabled. - */ -#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) - -#define ADC_IE_FOFIE0_MASK (0x2U) -#define ADC_IE_FOFIE0_SHIFT (1U) -/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable - * 0b0..FIFO 0 overflow interrupts are not enabled. - * 0b1..FIFO 0 overflow interrupts are enabled. - */ -#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) - -#define ADC_IE_FWMIE1_MASK (0x4U) -#define ADC_IE_FWMIE1_SHIFT (2U) -/*! FWMIE1 - FIFO1 Watermark Interrupt Enable - * 0b0..FIFO1 watermark interrupts are not enabled. - * 0b1..FIFO1 watermark interrupts are enabled. - */ -#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) - -#define ADC_IE_FOFIE1_MASK (0x8U) -#define ADC_IE_FOFIE1_SHIFT (3U) -/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable - * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) - -#define ADC_IE_TEXC_IE_MASK (0x100U) -#define ADC_IE_TEXC_IE_SHIFT (8U) -/*! TEXC_IE - Trigger Exception Interrupt Enable - * 0b0..Trigger exception interrupts are disabled. - * 0b1..Trigger exception interrupts are enabled. - */ -#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) - -#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U) -#define ADC_IE_TCOMP_IE_SHIFT (16U) -/*! TCOMP_IE - Trigger Completion Interrupt Enable - * 0b0000000000000000..Trigger completion interrupts are disabled. - * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only. - * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only. - * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled. - * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source. - */ -#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) -/*! @} */ - -/*! @name DE - DMA Enable Register */ -/*! @{ */ - -#define ADC_DE_FWMDE0_MASK (0x1U) -#define ADC_DE_FWMDE0_SHIFT (0U) -/*! FWMDE0 - FIFO 0 Watermark DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) - -#define ADC_DE_FWMDE1_MASK (0x2U) -#define ADC_DE_FWMDE1_SHIFT (1U) -/*! FWMDE1 - FIFO1 Watermark DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) -/*! @} */ - -/*! @name CFG - ADC Configuration Register */ -/*! @{ */ - -#define ADC_CFG_TPRICTRL_MASK (0x3U) -#define ADC_CFG_TPRICTRL_SHIFT (0U) -/*! TPRICTRL - ADC trigger priority control - * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted - * and the new command specified by the trigger is started. - * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after - * after completing the current conversion. If averaging is enabled, the averaging loop will be completed. - * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. - * 0b10..If a higher priority trigger is received during command processing, the current command will be - * completed (averaging, looping, compare) before servicing the higher priority trigger. - * 0b11..RESERVED - */ -#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) - -#define ADC_CFG_PWRSEL_MASK (0x30U) -#define ADC_CFG_PWRSEL_SHIFT (4U) -/*! PWRSEL - Power Configuration Select - * 0b00..Lowest power setting. - * 0b01..Higher power setting than 0b0. - * 0b10..Higher power setting than 0b1. - * 0b11..Highest power setting. - */ -#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) - -#define ADC_CFG_REFSEL_MASK (0xC0U) -#define ADC_CFG_REFSEL_SHIFT (6U) -/*! REFSEL - Voltage Reference Selection - * 0b00..(Default) Option 1 setting. - * 0b01..Option 2 setting. - * 0b10..Option 3 setting. - * 0b11..Reserved - */ -#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) - -#define ADC_CFG_TRES_MASK (0x100U) -#define ADC_CFG_TRES_SHIFT (8U) -/*! TRES - Trigger Resume Enable - * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. - * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. - */ -#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) - -#define ADC_CFG_TCMDRES_MASK (0x200U) -#define ADC_CFG_TCMDRES_SHIFT (9U) -/*! TCMDRES - Trigger Command Resume - * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. - * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. - */ -#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) - -#define ADC_CFG_HPT_EXDI_MASK (0x400U) -#define ADC_CFG_HPT_EXDI_SHIFT (10U) -/*! HPT_EXDI - High Priority Trigger Exception Disable - * 0b0..High priority trigger exceptions are enabled. - * 0b1..High priority trigger exceptions are disabled. - */ -#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) - -#define ADC_CFG_PUDLY_MASK (0xFF0000U) -#define ADC_CFG_PUDLY_SHIFT (16U) -/*! PUDLY - Power Up Delay - */ -#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) - -#define ADC_CFG_PWREN_MASK (0x10000000U) -#define ADC_CFG_PWREN_SHIFT (28U) -/*! PWREN - ADC Analog Pre-Enable - * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. - * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost - * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN - * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. - * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be - * executed. - */ -#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) -/*! @} */ - -/*! @name PAUSE - ADC Pause Register */ -/*! @{ */ - -#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) -#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) -/*! PAUSEDLY - Pause Delay - */ -#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) - -#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) -#define ADC_PAUSE_PAUSEEN_SHIFT (31U) -/*! PAUSEEN - PAUSE Option Enable - * 0b0..Pause operation disabled - * 0b1..Pause operation enabled - */ -#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) -/*! @} */ - -/*! @name SWTRIG - Software Trigger Register */ -/*! @{ */ - -#define ADC_SWTRIG_SWT0_MASK (0x1U) -#define ADC_SWTRIG_SWT0_SHIFT (0U) -/*! SWT0 - Software trigger 0 event - * 0b0..No trigger 0 event generated. - * 0b1..Trigger 0 event generated. - */ -#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) - -#define ADC_SWTRIG_SWT1_MASK (0x2U) -#define ADC_SWTRIG_SWT1_SHIFT (1U) -/*! SWT1 - Software trigger 1 event - * 0b0..No trigger 1 event generated. - * 0b1..Trigger 1 event generated. - */ -#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) - -#define ADC_SWTRIG_SWT2_MASK (0x4U) -#define ADC_SWTRIG_SWT2_SHIFT (2U) -/*! SWT2 - Software trigger 2 event - * 0b0..No trigger 2 event generated. - * 0b1..Trigger 2 event generated. - */ -#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) - -#define ADC_SWTRIG_SWT3_MASK (0x8U) -#define ADC_SWTRIG_SWT3_SHIFT (3U) -/*! SWT3 - Software trigger 3 event - * 0b0..No trigger 3 event generated. - * 0b1..Trigger 3 event generated. - */ -#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) - -#define ADC_SWTRIG_SWT4_MASK (0x10U) -#define ADC_SWTRIG_SWT4_SHIFT (4U) -/*! SWT4 - Software trigger 4 event - * 0b0..No trigger 4 event generated. - * 0b1..Trigger 4 event generated. - */ -#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) - -#define ADC_SWTRIG_SWT5_MASK (0x20U) -#define ADC_SWTRIG_SWT5_SHIFT (5U) -/*! SWT5 - Software trigger 5 event - * 0b0..No trigger 5 event generated. - * 0b1..Trigger 5 event generated. - */ -#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) - -#define ADC_SWTRIG_SWT6_MASK (0x40U) -#define ADC_SWTRIG_SWT6_SHIFT (6U) -/*! SWT6 - Software trigger 6 event - * 0b0..No trigger 6 event generated. - * 0b1..Trigger 6 event generated. - */ -#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) - -#define ADC_SWTRIG_SWT7_MASK (0x80U) -#define ADC_SWTRIG_SWT7_SHIFT (7U) -/*! SWT7 - Software trigger 7 event - * 0b0..No trigger 7 event generated. - * 0b1..Trigger 7 event generated. - */ -#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) - -#define ADC_SWTRIG_SWT8_MASK (0x100U) -#define ADC_SWTRIG_SWT8_SHIFT (8U) -/*! SWT8 - Software trigger 8 event - * 0b0..No trigger 8 event generated. - * 0b1..Trigger 8 event generated. - */ -#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK) - -#define ADC_SWTRIG_SWT9_MASK (0x200U) -#define ADC_SWTRIG_SWT9_SHIFT (9U) -/*! SWT9 - Software trigger 9 event - * 0b0..No trigger 9 event generated. - * 0b1..Trigger 9 event generated. - */ -#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK) - -#define ADC_SWTRIG_SWT10_MASK (0x400U) -#define ADC_SWTRIG_SWT10_SHIFT (10U) -/*! SWT10 - Software trigger 10 event - * 0b0..No trigger 10 event generated. - * 0b1..Trigger 10 event generated. - */ -#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK) - -#define ADC_SWTRIG_SWT11_MASK (0x800U) -#define ADC_SWTRIG_SWT11_SHIFT (11U) -/*! SWT11 - Software trigger 11 event - * 0b0..No trigger 11 event generated. - * 0b1..Trigger 11 event generated. - */ -#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK) - -#define ADC_SWTRIG_SWT12_MASK (0x1000U) -#define ADC_SWTRIG_SWT12_SHIFT (12U) -/*! SWT12 - Software trigger 12 event - * 0b0..No trigger 12 event generated. - * 0b1..Trigger 12 event generated. - */ -#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK) - -#define ADC_SWTRIG_SWT13_MASK (0x2000U) -#define ADC_SWTRIG_SWT13_SHIFT (13U) -/*! SWT13 - Software trigger 13 event - * 0b0..No trigger 13 event generated. - * 0b1..Trigger 13 event generated. - */ -#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK) - -#define ADC_SWTRIG_SWT14_MASK (0x4000U) -#define ADC_SWTRIG_SWT14_SHIFT (14U) -/*! SWT14 - Software trigger 14 event - * 0b0..No trigger 14 event generated. - * 0b1..Trigger 14 event generated. - */ -#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK) - -#define ADC_SWTRIG_SWT15_MASK (0x8000U) -#define ADC_SWTRIG_SWT15_SHIFT (15U) -/*! SWT15 - Software trigger 15 event - * 0b0..No trigger 15 event generated. - * 0b1..Trigger 15 event generated. - */ -#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK) -/*! @} */ - -/*! @name TSTAT - Trigger Status Register */ -/*! @{ */ - -#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU) -#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) -/*! TEXC_NUM - Trigger Exception Number - * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. - * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception. - * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception. - * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception. - * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception. - */ -#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) - -#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U) -#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) -/*! TCOMP_FLAG - Trigger Completion Flag - * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled. - * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts. - * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts. - * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts. - * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. - */ -#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) -/*! @} */ - -/*! @name OFSTRIM - ADC Offset Trim Register */ -/*! @{ */ - -#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) -#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) -/*! OFSTRIM_A - Trim for offset - */ -#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) - -#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) -#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) -/*! OFSTRIM_B - Trim for offset - */ -#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) -/*! @} */ - -/*! @name TCTRL - Trigger Control Register */ -/*! @{ */ - -#define ADC_TCTRL_HTEN_MASK (0x1U) -#define ADC_TCTRL_HTEN_SHIFT (0U) -/*! HTEN - Trigger enable - * 0b0..Hardware trigger source disabled - * 0b1..Hardware trigger source enabled - */ -#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) - -#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) -#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) -/*! FIFO_SEL_A - SAR Result Destination For Channel A - * 0b0..Result written to FIFO 0 - * 0b1..Result written to FIFO 1 - */ -#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) - -#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) -#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) -/*! FIFO_SEL_B - SAR Result Destination For Channel B - * 0b0..Result written to FIFO 0 - * 0b1..Result written to FIFO 1 - */ -#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) - -#define ADC_TCTRL_TPRI_MASK (0xF00U) -#define ADC_TCTRL_TPRI_SHIFT (8U) -/*! TPRI - Trigger priority setting - * 0b0000..Set to highest priority, Level 1 - * 0b0001-0b1110..Set to corresponding priority level - * 0b1111..Set to lowest priority, Level 16 - */ -#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) - -#define ADC_TCTRL_RSYNC_MASK (0x8000U) -#define ADC_TCTRL_RSYNC_SHIFT (15U) -/*! RSYNC - Trigger Resync - */ -#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) - -#define ADC_TCTRL_TDLY_MASK (0xF0000U) -#define ADC_TCTRL_TDLY_SHIFT (16U) -/*! TDLY - Trigger delay select - */ -#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) - -#define ADC_TCTRL_TCMD_MASK (0xF000000U) -#define ADC_TCTRL_TCMD_SHIFT (24U) -/*! TCMD - Trigger command select - * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. - * 0b0001..CMD1 is executed - * 0b0010-0b1110..Corresponding CMD is executed - * 0b1111..CMD15 is executed - */ -#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) -/*! @} */ - -/* The count of ADC_TCTRL */ -#define ADC_TCTRL_COUNT (16U) - -/*! @name FCTRL - FIFO Control Register */ -/*! @{ */ - -#define ADC_FCTRL_FCOUNT_MASK (0x1FU) -#define ADC_FCTRL_FCOUNT_SHIFT (0U) -/*! FCOUNT - Result FIFO counter - */ -#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) - -#define ADC_FCTRL_FWMARK_MASK (0xF0000U) -#define ADC_FCTRL_FWMARK_SHIFT (16U) -/*! FWMARK - Watermark level selection - */ -#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) -/*! @} */ - -/* The count of ADC_FCTRL */ -#define ADC_FCTRL_COUNT (2U) - -/*! @name GCC - Gain Calibration Control */ -/*! @{ */ - -#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) -#define ADC_GCC_GAIN_CAL_SHIFT (0U) -/*! GAIN_CAL - Gain Calibration Value - */ -#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) - -#define ADC_GCC_RDY_MASK (0x1000000U) -#define ADC_GCC_RDY_SHIFT (24U) -/*! RDY - Gain Calibration Value Valid - * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. - * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. - */ -#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) -/*! @} */ - -/* The count of ADC_GCC */ -#define ADC_GCC_COUNT (2U) - -/*! @name GCR - Gain Calculation Result */ -/*! @{ */ - -#define ADC_GCR_GCALR_MASK (0xFFFFU) -#define ADC_GCR_GCALR_SHIFT (0U) -/*! GCALR - Gain Calculation Result - */ -#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) - -#define ADC_GCR_RDY_MASK (0x1000000U) -#define ADC_GCR_RDY_SHIFT (24U) -/*! RDY - Gain Calculation Ready - * 0b0..The gain offset calculation value is invalid. - * 0b1..The gain calibration value is valid. - */ -#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) -/*! @} */ - -/* The count of ADC_GCR */ -#define ADC_GCR_COUNT (2U) - -/*! @name CMDL - ADC Command Low Buffer Register */ -/*! @{ */ - -#define ADC_CMDL_ADCH_MASK (0x1FU) -#define ADC_CMDL_ADCH_SHIFT (0U) -/*! ADCH - Input channel select - * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. - * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. - * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. - * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. - * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. - * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. - */ -#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) - -#define ADC_CMDL_CTYPE_MASK (0x60U) -#define ADC_CMDL_CTYPE_SHIFT (5U) -/*! CTYPE - Conversion Type - * 0b00..Single-Ended Mode. Only A side channel is converted. - * 0b01..Single-Ended Mode. Only B side channel is converted. - * 0b10..Differential Mode. A-B. - * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - */ -#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) - -#define ADC_CMDL_MODE_MASK (0x80U) -#define ADC_CMDL_MODE_SHIFT (7U) -/*! MODE - Select resolution of conversions - * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - */ -#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) -/*! @} */ - -/* The count of ADC_CMDL */ -#define ADC_CMDL_COUNT (15U) - -/*! @name CMDH - ADC Command High Buffer Register */ -/*! @{ */ - -#define ADC_CMDH_CMPEN_MASK (0x3U) -#define ADC_CMDH_CMPEN_SHIFT (0U) -/*! CMPEN - Compare Function Enable - * 0b00..Compare disabled. - * 0b01..Reserved - * 0b10..Compare enabled. Store on true. - * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - */ -#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) - -#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) -#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) -/*! WAIT_TRIG - Wait for trigger assertion before execution. - * 0b0..This command will be automatically executed. - * 0b1..The active trigger must be asserted again before executing this command. - */ -#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) - -#define ADC_CMDH_LWI_MASK (0x80U) -#define ADC_CMDH_LWI_SHIFT (7U) -/*! LWI - Loop with Increment - * 0b0..Auto channel increment disabled - * 0b1..Auto channel increment enabled - */ -#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) - -#define ADC_CMDH_STS_MASK (0x700U) -#define ADC_CMDH_STS_SHIFT (8U) -/*! STS - Sample Time Select - * 0b000..Minimum sample time of 3 ADCK cycles. - * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - */ -#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) - -#define ADC_CMDH_AVGS_MASK (0x7000U) -#define ADC_CMDH_AVGS_SHIFT (12U) -/*! AVGS - Hardware Average Select - * 0b000..Single conversion. - * 0b001..2 conversions averaged. - * 0b010..4 conversions averaged. - * 0b011..8 conversions averaged. - * 0b100..16 conversions averaged. - * 0b101..32 conversions averaged. - * 0b110..64 conversions averaged. - * 0b111..128 conversions averaged. - */ -#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) - -#define ADC_CMDH_LOOP_MASK (0xF0000U) -#define ADC_CMDH_LOOP_SHIFT (16U) -/*! LOOP - Loop Count Select - * 0b0000..Looping not enabled. Command executes 1 time. - * 0b0001..Loop 1 time. Command executes 2 times. - * 0b0010..Loop 2 times. Command executes 3 times. - * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. - * 0b1111..Loop 15 times. Command executes 16 times. - */ -#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) - -#define ADC_CMDH_NEXT_MASK (0xF000000U) -#define ADC_CMDH_NEXT_SHIFT (24U) -/*! NEXT - Next Command Select - * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority - * trigger pending, begin command associated with lower priority trigger. - * 0b0001..Select CMD1 command buffer register as next command. - * 0b0010-0b1110..Select corresponding CMD command buffer register as next command - * 0b1111..Select CMD15 command buffer register as next command. - */ -#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) -/*! @} */ - -/* The count of ADC_CMDH */ -#define ADC_CMDH_COUNT (15U) - -/*! @name CV - Compare Value Register */ -/*! @{ */ - -#define ADC_CV_CVL_MASK (0xFFFFU) -#define ADC_CV_CVL_SHIFT (0U) -/*! CVL - Compare Value Low. - */ -#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) - -#define ADC_CV_CVH_MASK (0xFFFF0000U) -#define ADC_CV_CVH_SHIFT (16U) -/*! CVH - Compare Value High. - */ -#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) -/*! @} */ - -/* The count of ADC_CV */ -#define ADC_CV_COUNT (4U) - -/*! @name RESFIFO - ADC Data Result FIFO Register */ -/*! @{ */ - -#define ADC_RESFIFO_D_MASK (0xFFFFU) -#define ADC_RESFIFO_D_SHIFT (0U) -/*! D - Data result - */ -#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) - -#define ADC_RESFIFO_TSRC_MASK (0xF0000U) -#define ADC_RESFIFO_TSRC_SHIFT (16U) -/*! TSRC - Trigger Source - * 0b0000..Trigger source 0 initiated this conversion. - * 0b0001..Trigger source 1 initiated this conversion. - * 0b0010-0b1110..Corresponding trigger source initiated this conversion. - * 0b1111..Trigger source 15 initiated this conversion. - */ -#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) - -#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) -#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) -/*! LOOPCNT - Loop count value - * 0b0000..Result is from initial conversion in command. - * 0b0001..Result is from second conversion in command. - * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. - * 0b1111..Result is from 16th conversion in command. - */ -#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) - -#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) -#define ADC_RESFIFO_CMDSRC_SHIFT (24U) -/*! CMDSRC - Command Buffer Source - * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state - * prior to an ADC conversion result dataword being stored to a RESFIFO buffer. - * 0b0001..CMD1 buffer used as control settings for this conversion. - * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. - * 0b1111..CMD15 buffer used as control settings for this conversion. - */ -#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) - -#define ADC_RESFIFO_VALID_MASK (0x80000000U) -#define ADC_RESFIFO_VALID_SHIFT (31U) -/*! VALID - FIFO entry is valid - * 0b0..FIFO is empty. Discard any read from RESFIFO. - * 0b1..FIFO record read from RESFIFO is valid. - */ -#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) -/*! @} */ - -/* The count of ADC_RESFIFO */ -#define ADC_RESFIFO_COUNT (2U) - -/*! @name CAL_GAR - Calibration General A-Side Registers */ -/*! @{ */ - -#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) -#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) -/*! CAL_GAR_VAL - Calibration General A Side Register Element - */ -#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) -/*! @} */ - -/* The count of ADC_CAL_GAR */ -#define ADC_CAL_GAR_COUNT (33U) - -/*! @name CAL_GBR - Calibration General B-Side Registers */ -/*! @{ */ - -#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) -#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) -/*! CAL_GBR_VAL - Calibration General B Side Register Element - */ -#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) -/*! @} */ - -/* The count of ADC_CAL_GBR */ -#define ADC_CAL_GBR_COUNT (33U) - -/*! @name TST - ADC Test Register */ -/*! @{ */ - -#define ADC_TST_CST_LONG_MASK (0x1U) -#define ADC_TST_CST_LONG_SHIFT (0U) -/*! CST_LONG - Calibration Sample Time Long - * 0b0..Normal sample time. Minimum sample time of 3 ADCK cycles. - * 0b1..Increased sample time. 67 ADCK cycles total sample time. - */ -#define ADC_TST_CST_LONG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_CST_LONG_SHIFT)) & ADC_TST_CST_LONG_MASK) - -#define ADC_TST_FOFFM_MASK (0x100U) -#define ADC_TST_FOFFM_SHIFT (8U) -/*! FOFFM - Force M-side positive offset - * 0b0..Normal operation. No forced offset. - * 0b1..Test configuration. Forced positive offset on MDAC. - */ -#define ADC_TST_FOFFM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK) - -#define ADC_TST_FOFFP_MASK (0x200U) -#define ADC_TST_FOFFP_SHIFT (9U) -/*! FOFFP - Force P-side positive offset - * 0b0..Normal operation. No forced offset. - * 0b1..Test configuration. Forced positive offset on PDAC. - */ -#define ADC_TST_FOFFP(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK) - -#define ADC_TST_FOFFM2_MASK (0x400U) -#define ADC_TST_FOFFM2_SHIFT (10U) -/*! FOFFM2 - Force M-side negative offset - * 0b0..Normal operation. No forced offset. - * 0b1..Test configuration. Forced negative offset on MDAC. - */ -#define ADC_TST_FOFFM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM2_SHIFT)) & ADC_TST_FOFFM2_MASK) - -#define ADC_TST_FOFFP2_MASK (0x800U) -#define ADC_TST_FOFFP2_SHIFT (11U) -/*! FOFFP2 - Force P-side negative offset - * 0b0..Normal operation. No forced offset. - * 0b1..Test configuration. Forced negative offset on PDAC. - */ -#define ADC_TST_FOFFP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP2_SHIFT)) & ADC_TST_FOFFP2_MASK) - -#define ADC_TST_TESTEN_MASK (0x800000U) -#define ADC_TST_TESTEN_SHIFT (23U) -/*! TESTEN - Enable test configuration - * 0b0..Normal operation. Test configuration not enabled. - * 0b1..Hardware BIST Test in progress. - */ -#define ADC_TST_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_TESTEN_SHIFT)) & ADC_TST_TESTEN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ADC_Register_Masks */ - - -/* ADC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral ADC0 base address */ - #define ADC0_BASE (0x500A0000u) - /** Peripheral ADC0 base address */ - #define ADC0_BASE_NS (0x400A0000u) - /** Peripheral ADC0 base pointer */ - #define ADC0 ((ADC_Type *)ADC0_BASE) - /** Peripheral ADC0 base pointer */ - #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS { ADC0_BASE } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS { ADC0 } - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS_NS { ADC0_NS } -#else - /** Peripheral ADC0 base address */ - #define ADC0_BASE (0x400A0000u) - /** Peripheral ADC0 base pointer */ - #define ADC0 ((ADC_Type *)ADC0_BASE) - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS { ADC0_BASE } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS { ADC0 } -#endif -/** Interrupt vectors for the ADC peripheral type */ -#define ADC_IRQS { ADC0_IRQn } - -/*! - * @} - */ /* end of group ADC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- AHB_SECURE_CTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer - * @{ - */ - -/** AHB_SECURE_CTRL - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x30 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */ - uint8_t RESERVED_0[12]; - __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[3]; /**< Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */ - uint8_t RESERVED_1[4]; - __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */ - } SEC_CTRL_FLASH_ROM[1]; - struct { /* offset: 0x30, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAMX slaves., array offset: 0x40, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_RAMX[1]; - uint8_t RESERVED_0[12]; - struct { /* offset: 0x50, array step: 0x18 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x18 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM0 slaves., array offset: 0x60, array step: index*0x18, index2*0x4 */ - } SEC_CTRL_RAM0[1]; - uint8_t RESERVED_1[8]; - struct { /* offset: 0x70, array step: 0x18 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x18 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM1 slaves., array offset: 0x80, array step: index*0x18, index2*0x4 */ - } SEC_CTRL_RAM1[1]; - uint8_t RESERVED_2[8]; - struct { /* offset: 0x90, array step: 0x18 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x18 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step: index*0x18, index2*0x4 */ - } SEC_CTRL_RAM2[1]; - uint8_t RESERVED_3[8]; - struct { /* offset: 0xB0, array step: 0x18 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM3 slaves., array offset: 0xB0, array step: 0x18 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM3 slaves., array offset: 0xC0, array step: index*0x18, index2*0x4 */ - } SEC_CTRL_RAM3[1]; - uint8_t RESERVED_4[8]; - struct { /* offset: 0xD0, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM4 slaves., array offset: 0xD0, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM4 slaves., array offset: 0xE0, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_RAM4[1]; - uint8_t RESERVED_5[12]; - struct { /* offset: 0xF0, array step: 0x30 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for both APB Bridges slaves., array offset: 0xF0, array step: 0x30 */ - uint8_t RESERVED_0[12]; - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x100, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x104, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x108, array step: 0x30 */ - uint8_t RESERVED_1[4]; - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x110, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x114, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x118, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x11C, array step: 0x30 */ - } SEC_CTRL_APB_BRIDGE[1]; - __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */ - __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */ - uint8_t RESERVED_6[8]; - __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */ - __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */ - uint8_t RESERVED_7[8]; - struct { /* offset: 0x140, array step: 0x14 */ - __IO uint32_t SLAVE0_RULE; /**< Security access rules for AHB peripherals., array offset: 0x140, array step: 0x14 */ - __IO uint32_t SLAVE1_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */ - uint8_t RESERVED_0[8]; - __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x150, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_AHB_PORT10[1]; - uint8_t RESERVED_8[12]; - struct { /* offset: 0x160, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0x160, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM_USB_HS., array offset: 0x170, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_USB_HS[1]; - uint8_t RESERVED_9[3212]; - __I uint32_t SEC_VIO_ADDR[12]; /**< most recent security violation address for AHB port n, array offset: 0xE00, array step: 0x4 */ - uint8_t RESERVED_10[80]; - __I uint32_t SEC_VIO_MISC_INFO[12]; /**< most recent security violation miscellaneous information for AHB port n, array offset: 0xE80, array step: 0x4 */ - uint8_t RESERVED_11[80]; - __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */ - uint8_t RESERVED_12[124]; - __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */ - __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */ - uint8_t RESERVED_13[8]; - __IO uint32_t SEC_CPU_INT_MASK0; /**< Secure Interrupt mask for CPU1, offset: 0xF90 */ - __IO uint32_t SEC_CPU_INT_MASK1; /**< Secure Interrupt mask for CPU1, offset: 0xF94 */ - uint8_t RESERVED_14[36]; - __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */ - uint8_t RESERVED_15[16]; - __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */ - __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */ - uint8_t RESERVED_16[20]; - __IO uint32_t CPU0_LOCK_REG; /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */ - __IO uint32_t CPU1_LOCK_REG; /**< Miscalleneous control signals for in micro-Cortex M33 (CPU1), offset: 0xFF0 */ - uint8_t RESERVED_17[4]; - __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */ - __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */ -} AHB_SECURE_CTRL_Type; - -/* ---------------------------------------------------------------------------- - -- AHB_SECURE_CTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks - * @{ - */ - -/*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U) -/*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U) -/*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U) - -/*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U) - -/*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U) -/*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAMX_MEM_RULE - Security access rules for RAMX slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U) -/*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM0_MEM_RULE - Security access rules for RAM0 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT2 (2U) - -/*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT (0U) -/*! RAM1_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM1_MEM_RULE - Security access rules for RAM1 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT2 (2U) - -/*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U) -/*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM2_MEM_RULE - Security access rules for RAM2 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT2 (2U) - -/*! @name SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT (0U) -/*! RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM3_MEM_RULE - Security access rules for RAM3 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT2 (2U) - -/*! @name SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT (0U) -/*! RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM4_MEM_RULE - Security access rules for RAM4 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U) -/*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U) -/*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U) -/*! SYSCON_RULE - System Configuration - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U) -/*! IOCON_RULE - I/O Configuration - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U) -/*! GINT0_RULE - GPIO input Interrupt 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U) -/*! GINT1_RULE - GPIO input Interrupt 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U) -/*! PINT_RULE - Pin Interrupt and Pattern match - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U) -/*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT (24U) -/*! INPUTMUX_RULE - Peripheral input multiplexing - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U) -/*! CTIMER0_RULE - Standard counter/Timer 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U) -/*! CTIMER1_RULE - Standard counter/Timer 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U) -/*! WWDT_RULE - Windiwed wtachdog Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U) -/*! MRT_RULE - Multi-rate Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U) -/*! UTICK_RULE - Micro-Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U) -/*! ANACTRL_RULE - Analog Modules controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U) -/*! PMC_RULE - Power Management Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U) -/*! SYSCTRL_RULE - System Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U) -/*! CTIMER2_RULE - Standard counter/Timer 2 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U) -/*! CTIMER3_RULE - Standard counter/Timer 3 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U) -/*! CTIMER4_RULE - Standard counter/Timer 4 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U) -/*! RTC_RULE - Real Time Counter - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U) -/*! OSEVENT_RULE - OS Event Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U) -/*! FLASH_CTRL_RULE - Flash Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U) -/*! PRINCE_RULE - Prince - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U) -/*! USBHPHY_RULE - USB High Speed Phy controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U) -/*! RNG_RULE - True Random Number Generator - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT (12U) -/*! PUF_RULE - PUF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U) -/*! PLU_RULE - Programmable Look-Up logic - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U) - -/*! @name SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT (8U) -/*! DMA0_RULE - DMA Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT (16U) -/*! FS_USB_DEV_RULE - USB Full-speed device - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT (20U) -/*! SCT_RULE - SCTimer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT (24U) -/*! FLEXCOMM0_RULE - Flexcomm interface 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT (28U) -/*! FLEXCOMM1_RULE - Flexcomm interface 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT (0U) -/*! FLEXCOMM2_RULE - Flexcomm interface 2 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT (4U) -/*! FLEXCOMM3_RULE - Flexcomm interface 3 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT (8U) -/*! FLEXCOMM4_RULE - Flexcomm interface 4 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT (12U) -/*! MAILBOX_RULE - Inter CPU communication Mailbox - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT (16U) -/*! GPIO0_RULE - High Speed GPIO - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT (16U) -/*! USB_HS_DEV_RULE - USB high Speed device registers - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT (20U) -/*! CRC_RULE - CRC engine - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT (24U) -/*! FLEXCOMM5_RULE - Flexcomm interface 5 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT (28U) -/*! FLEXCOMM6_RULE - Flexcomm interface 6 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT (0U) -/*! FLEXCOMM7_RULE - Flexcomm interface 7 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT (12U) -/*! SDIO_RULE - SDMMC card interface - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT (16U) -/*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT (28U) -/*! HS_LSPI_RULE - High Speed SPI - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB_PORT10_SLAVE0_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT (0U) -/*! ADC_RULE - ADC - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT (8U) -/*! USB_FS_HOST_RULE - USB Full Speed Host registers. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT (12U) -/*! USB_HS_HOST_RULE - USB High speed host registers - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT (16U) -/*! HASH_RULE - SHA-2 crypto registers - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT (20U) -/*! CASPER_RULE - RSA/ECC crypto accelerator - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT (24U) -/*! PQ_RULE - Power Quad (CPU0 processor hardware accelerator) - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT (28U) -/*! DMA1_RULE - DMA Controller (Secure) - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_COUNT (1U) - -/*! @name SEC_CTRL_AHB_PORT10_SLAVE1_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT (0U) -/*! GPIO1_RULE - Secure High Speed GPIO - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U) -/*! AHB_SEC_CTRL_RULE - AHB Secure Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_COUNT (1U) - -/*! @name SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U) -/*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U) -/*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U) -/*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U) -/*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U) -/*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U) -/*! SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U) -/*! SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U) -/*! SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U) -/*! SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_VIO_ADDR - most recent security violation address for AHB port n */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) -/*! SEC_VIO_ADDR - security violation address for AHB port - */ -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */ -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (12U) - -/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB port n */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) -/*! SEC_VIO_INFO_WRITE - security violation access read/write indicator. - * 0b0..Read access. - * 0b1..Write access. - */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) -/*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator. - * 0b0..Code access. - * 0b1..Data access. - */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) -/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level - */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) -/*! SEC_VIO_INFO_MASTER - security violation master number - * 0b0000..CPU0 Code. - * 0b0001..CPU0 System. - * 0b0010..CPU1 Data. - * 0b0011..CPU1 System. - * 0b0100..USB-HS Device. - * 0b0101..SDMA0. - * 0b1000..SDIO. - * 0b1001..PowerQuad. - * 0b1010..HASH. - * 0b1011..USB-FS Host. - * 0b1100..SDMA1. - */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (12U) - -/*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) -/*! VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) -/*! VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) -/*! VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) -/*! VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) -/*! VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) -/*! VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) -/*! VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) -/*! VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) -/*! VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) -/*! VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U) -/*! VIO_INFO_VALID10 - violation information valid flag for AHB port 10. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U) -/*! VIO_INFO_VALID11 - violation information valid flag for AHB port 11. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK) -/*! @} */ - -/*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U) -/*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U) -/*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U) -/*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U) -/*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U) -/*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U) -/*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U) -/*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U) -/*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U) -/*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U) -/*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U) -/*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U) -/*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U) -/*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U) -/*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U) -/*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U) -/*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U) -/*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U) -/*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U) -/*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U) -/*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U) -/*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U) -/*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U) -/*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U) -/*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U) -/*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U) -/*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U) -/*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U) -/*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U) -/*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U) -/*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U) -/*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U) -/*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK) -/*! @} */ - -/*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U) -/*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U) -/*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U) -/*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U) -/*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U) -/*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U) -/*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U) -/*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U) -/*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U) -/*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U) -/*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U) -/*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U) -/*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U) -/*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U) -/*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U) -/*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U) -/*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U) -/*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U) -/*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U) -/*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U) -/*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U) -/*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U) -/*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U) -/*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U) -/*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U) -/*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U) -/*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U) -/*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U) -/*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U) -/*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U) -/*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U) -/*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U) -/*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK) -/*! @} */ - -/*! @name SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT (0U) -/*! SYS_IRQ - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT (1U) -/*! SDMA0_IRQ - System DMA 0 (non-secure) interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT (2U) -/*! GPIO_GLOBALINT0_IRQ - GPIO Group 0 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT (3U) -/*! GPIO_GLOBALINT1_IRQ - GPIO Group 1 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT (4U) -/*! GPIO_INT0_IRQ0 - Pin interrupt 0 or pattern match engine slice 0 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT (5U) -/*! GPIO_INT0_IRQ1 - Pin interrupt 1 or pattern match engine slice 1 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT (6U) -/*! GPIO_INT0_IRQ2 - Pin interrupt 2 or pattern match engine slice 2 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT (7U) -/*! GPIO_INT0_IRQ3 - Pin interrupt 3 or pattern match engine slice 3 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT (8U) -/*! UTICK_IRQ - Micro Tick Timer interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT (9U) -/*! MRT_IRQ - Multi-Rate Timer interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT (10U) -/*! CTIMER0_IRQ - Standard counter/timer 0 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT (11U) -/*! CTIMER1_IRQ - Standard counter/timer 1 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT (12U) -/*! SCT_IRQ - SCTimer/PWM interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT (13U) -/*! CTIMER3_IRQ - Standard counter/timer 3 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT (14U) -/*! FLEXCOMM0_IRQ - Flexcomm 0 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT (15U) -/*! FLEXCOMM1_IRQ - Flexcomm 1 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT (16U) -/*! FLEXCOMM2_IRQ - Flexcomm 2 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT (17U) -/*! FLEXCOMM3_IRQ - Flexcomm 3 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT (18U) -/*! FLEXCOMM4_IRQ - Flexcomm 4 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT (19U) -/*! FLEXCOMM5_IRQ - Flexcomm 5 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT (20U) -/*! FLEXCOMM6_IRQ - Flexcomm 6 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT (21U) -/*! FLEXCOMM7_IRQ - Flexcomm 7 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT (22U) -/*! ADC_IRQ - General Purpose ADC interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT (23U) -/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT (24U) -/*! ACMP_IRQ - Analog Comparator interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT (25U) -/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT (26U) -/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT (27U) -/*! USB0_NEEDCLK - USB Full Speed Controller Clock request interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT (28U) -/*! USB0_IRQ - USB Full Speed Controller interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT (29U) -/*! RTC_IRQ - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT (30U) -/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT (31U) -/*! MAILBOX_IRQ - Mailbox interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK) -/*! @} */ - -/*! @name SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT (0U) -/*! GPIO_INT0_IRQ4 - Pin interrupt 4 or pattern match engine slice 4 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT (1U) -/*! GPIO_INT0_IRQ5 - Pin interrupt 5 or pattern match engine slice 5 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT (2U) -/*! GPIO_INT0_IRQ6 - Pin interrupt 6 or pattern match engine slice 6 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT (3U) -/*! GPIO_INT0_IRQ7 - Pin interrupt 7 or pattern match engine slice 7 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT (4U) -/*! CTIMER2_IRQ - Standard counter/timer 2 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT (5U) -/*! CTIMER4_IRQ - Standard counter/timer 4 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT (6U) -/*! OS_EVENT_TIMER_IRQ - OS Event Timer and OS Event Timer Wakeup interrupts - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT (7U) -/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT (8U) -/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT (9U) -/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT (10U) -/*! SDIO_IRQ - SDIO Controller interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT (11U) -/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT (12U) -/*! RESERVED4 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT (13U) -/*! RESERVED5 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT (14U) -/*! USB1_PHY_IRQ - USB High Speed PHY Controller interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT (15U) -/*! USB1_IRQ - USB High Speed Controller interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT (16U) -/*! USB1_NEEDCLK - USB High Speed Controller Clock request interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT (17U) -/*! SEC_HYPERVISOR_CALL_IRQ - Secure fault Hyper Visor call interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT (18U) -/*! SEC_GPIO_INT0_IRQ0 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT (19U) -/*! SEC_GPIO_INT0_IRQ1 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT (20U) -/*! PLU_IRQ - Programmable Look-Up Controller interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT (21U) -/*! SEC_VIO_IRQ - Security Violation interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT (22U) -/*! SHA_IRQ - HASH-AES interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT (23U) -/*! CASPER_IRQ - CASPER interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT (24U) -/*! PUFKEY_IRQ - PUF interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT (25U) -/*! PQ_IRQ - Power Quad interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT (26U) -/*! SDMA1_IRQ - System DMA 1 (Secure) interrupt - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT (27U) -/*! LSPI_HS_IRQ - High Speed SPI interrupt - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK) -/*! @} */ - -/*! @name SEC_MASK_LOCK - Security General Purpose register access control. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) -/*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK) - -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) -/*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK) - -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (8U) -/*! SEC_CPU1_INT_MASK0_LOCK - SEC_CPU_INT_MASK0 register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK) - -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC00U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (10U) -/*! SEC_CPU1_INT_MASK1_LOCK - SEC_CPU_INT_MASK1 register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK) -/*! @} */ - -/*! @name MASTER_SEC_LEVEL - master secure level register */ -/*! @{ */ - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK (0x30U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT (4U) -/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK (0xC0U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT (6U) -/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U) -/*! USBFSD - USB Full Speed Device. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U) -/*! SDMA0 - System DMA 0. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK (0x30000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT (16U) -/*! SDIO - SDIO. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK (0xC0000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT (18U) -/*! PQ - Power Quad. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U) -/*! HASH - Hash. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U) -/*! USBFSH - USB Full speed Host. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U) -/*! SDMA1 - System DMA 1 security level. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) -/*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) -/*! @} */ - -/*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */ -/*! @{ */ - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK (0x30U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT (4U) -/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK (0xC0U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT (6U) -/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U) -/*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U) -/*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK (0x30000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT (16U) -/*! SDIO - SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0xC0000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (18U) -/*! PQ - Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U) -/*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U) -/*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U) -/*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) -/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) -/*! @} */ - -/*! @name CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) */ -/*! @{ */ - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) -/*! LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) -/*! LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) -/*! LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U) -/*! LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U) -/*! LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT (30U) -/*! CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK) -/*! @} */ - -/*! @name CPU1_LOCK_REG - Miscalleneous control signals for in micro-Cortex M33 (CPU1) */ -/*! @{ */ - -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) -/*! LOCK_NS_VTOR - micro-Cortex M33 (CPU1) VTOR_NS register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK) - -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) -/*! LOCK_NS_MPU - micro-Cortex M33 (CPU1) non-secure MPU register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK) - -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT (30U) -/*! CPU1_LOCK_REG_LOCK - CPU1_LOCK_REG write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK) -/*! @} */ - -/*! @name MISC_CTRL_DP_REG - secure control duplicate register */ -/*! @{ */ - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) -/*! WRITE_LOCK - Write lock. - * 0b10..Secure control registers can be written. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) -/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. - * 0b10..Disable check. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) -/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. - * 0b10..Disable check. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) -/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. - * 0b10..Disable check. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) -/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. - * 0b10..Enable abort fort secure checker. - * 0b01..Disable abort fort secure checker. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) -/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. - * 0b10..Simple master in strict mode. - * 0b01..Simple master in tier mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) -/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. - * 0b10..Smart master in strict mode. - * 0b01..Smart master in tier mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) -/*! IDAU_ALL_NS - Disable IDAU. - * 0b10..IDAU is enabled. - * 0b01..IDAU is disable. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) -/*! @} */ - -/*! @name MISC_CTRL_REG - secure control register */ -/*! @{ */ - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) -/*! WRITE_LOCK - Write lock. - * 0b10..Secure control registers can be written. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) -/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. - * 0b10..Disable check. - * 0b01..Enabled (restricted mode) - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) -/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. - * 0b10..Disable check. - * 0b01..Enabled (restricted mode) - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) -/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. - * 0b10..Disable check. - * 0b01..Enabled (restricted mode) - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) -/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. - * 0b10..Enable abort fort secure checker. - * 0b01..Disable abort fort secure checker. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) -/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. - * 0b10..Simple master in strict mode. - * 0b01..Simple master in tier mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) -/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. - * 0b10..Smart master in strict mode. - * 0b01..Smart master in tier mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) -/*! IDAU_ALL_NS - Disable IDAU. - * 0b10..IDAU is enabled. - * 0b01..IDAU is disable. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group AHB_SECURE_CTRL_Register_Masks */ - - -/* AHB_SECURE_CTRL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral AHB_SECURE_CTRL base address */ - #define AHB_SECURE_CTRL_BASE (0x500AC000u) - /** Peripheral AHB_SECURE_CTRL base address */ - #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u) - /** Peripheral AHB_SECURE_CTRL base pointer */ - #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) - /** Peripheral AHB_SECURE_CTRL base pointer */ - #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS) - /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ - #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } - /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ - #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } - /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ - #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS } - /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ - #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS } -#else - /** Peripheral AHB_SECURE_CTRL base address */ - #define AHB_SECURE_CTRL_BASE (0x400AC000u) - /** Peripheral AHB_SECURE_CTRL base pointer */ - #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) - /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ - #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } - /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ - #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } -#endif - -/*! - * @} - */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ANACTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer - * @{ - */ - -/** ANACTRL - Register Layout Typedef */ -typedef struct { - __IO uint32_t ANALOG_CTRL_CFG; /**< Various Analog blocks configuration (like FRO 192MHz trimmings source ...), offset: 0x0 */ - __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */ - __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */ - __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */ - __IO uint32_t ADC_CTRL; /**< General Purpose ADC VBAT Divider branch control, offset: 0x18 */ - uint8_t RESERVED_1[4]; - __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */ - __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status register, offset: 0x24 */ - uint8_t RESERVED_2[8]; - __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */ - __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */ - uint8_t RESERVED_3[8]; - __IO uint32_t RINGO0_CTRL; /**< First Ring Oscillator module control register., offset: 0x40 */ - __IO uint32_t RINGO1_CTRL; /**< Second Ring Oscillator module control register., offset: 0x44 */ - __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */ - uint8_t RESERVED_4[100]; - __IO uint32_t LDO_XO32M; /**< High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register, offset: 0xB0 */ - __IO uint32_t AUX_BIAS; /**< AUX_BIAS, offset: 0xB4 */ - uint8_t RESERVED_5[72]; - __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */ - __IO uint32_t USBHS_PHY_TRIM; /**< USB High Speed Phy Trim values, offset: 0x104 */ -} ANACTRL_Type; - -/* ---------------------------------------------------------------------------- - -- ANACTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks - * @{ - */ - -/*! @name ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) */ -/*! @{ */ - -#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK (0x1U) -#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT (0U) -/*! FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source. - * 0b0..FRO192M trimming and 'Enable' comes from eFUSE. - * 0b1..FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers. - */ -#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT)) & ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK) -/*! @} */ - -/*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */ -/*! @{ */ - -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U) -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U) -/*! FLASH_PWRDWN - Flash Power Down status. - * 0b0..Flash is not in power down mode. - * 0b1..Flash is in power down mode. - */ -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK) - -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U) -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U) -/*! FLASH_INIT_ERROR - Flash initialization error status. - * 0b0..No error. - * 0b1..At least one error occured during flash initialization.. - */ -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK) -/*! @} */ - -/*! @name FREQ_ME_CTRL - Frequency Measure function control register */ -/*! @{ */ - -#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU) -#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U) -/*! CAPVAL_SCALE - Frequency measure result /Frequency measur scale - */ -#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK) - -#define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U) -#define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U) -/*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit - * when the measurement cycle has completed and there is valid capture data in the CAPVAL field - * (bits 30:0). - */ -#define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK) -/*! @} */ - -/*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */ -/*! @{ */ - -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U) -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U) -/*! ENA_12MHZCLK - 12 MHz clock control. - * 0b0..12 MHz clock is disabled. - * 0b1..12 MHz clock is enabled. - */ -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) - -#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK (0x8000U) -#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT (15U) -/*! ENA_48MHZCLK - 48 MHz clock control. - * 0b0..Reserved. - * 0b1..48 MHz clock is enabled. - */ -#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK) - -#define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U) -#define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U) -/*! DAC_TRIM - Frequency trim. - */ -#define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK) - -#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U) -#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U) -/*! USBCLKADJ - If this bit is set and the USB peripheral is enabled into full speed device mode, - * the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF - * packets. - */ -#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK) - -#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U) -#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U) -/*! USBMODCHG - If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0. - */ -#define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK) - -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U) -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U) -/*! ENA_96MHZCLK - 96 MHz clock control. - * 0b0..96 MHz clock is disabled. - * 0b1..96 MHz clock is enabled. - */ -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) - -#define ANACTRL_FRO192M_CTRL_WRTRIM_MASK (0x80000000U) -#define ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT (31U) -/*! WRTRIM - This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields. - */ -#define ANACTRL_FRO192M_CTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_WRTRIM_MASK) -/*! @} */ - -/*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */ -/*! @{ */ - -#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U) -#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U) -/*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. - * 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). - * 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by - * FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). - */ -#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK) - -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U) -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U) -/*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses - * the threshold voltage of a SLVT transistor, this output signal will go high. It is also - * possible to observe the clk_valid signal. - */ -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK) -/*! @} */ - -/*! @name ADC_CTRL - General Purpose ADC VBAT Divider branch control */ -/*! @{ */ - -#define ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK (0x1U) -#define ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT (0U) -/*! VBATDIVENABLE - Switch On/Off VBAT divider branch. - * 0b0..VBAT divider branch is disabled. - * 0b1..VBAT divider branch is enabled. - */ -#define ANACTRL_ADC_CTRL_VBATDIVENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT)) & ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK) -/*! @} */ - -/*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */ -/*! @{ */ - -#define ANACTRL_XO32M_CTRL_SLAVE_MASK (0x10U) -#define ANACTRL_XO32M_CTRL_SLAVE_SHIFT (4U) -/*! SLAVE - Xo in slave mode. - */ -#define ANACTRL_XO32M_CTRL_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_SLAVE_SHIFT)) & ANACTRL_XO32M_CTRL_SLAVE_MASK) - -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK (0x7F00U) -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT (8U) -/*! OSC_CAP_IN - Tune capa banks of High speed Crystal Oscillator input pin - */ -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK) - -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK (0x3F8000U) -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT (15U) -/*! OSC_CAP_OUT - Tune capa banks of High speed Crystal Oscillator output pin - */ -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK) - -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U) -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U) -/*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. - * 0b0..XO AC buffer bypass is disabled. - * 0b1..XO AC buffer bypass is enabled. - */ -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK) - -#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U) -#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U) -/*! ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL. - * 0b0..High speed Crystal oscillator output to USB HS PLL is disabled. - * 0b1..High speed Crystal oscillator output to USB HS PLL is enabled. - */ -#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) - -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U) -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U) -/*! ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system. - * 0b0..High speed Crystal oscillator output to CPU system is disabled. - * 0b1..High speed Crystal oscillator output to CPU system is enabled. - */ -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) -/*! @} */ - -/*! @name XO32M_STATUS - High speed Crystal Oscillator Status register */ -/*! @{ */ - -#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U) -#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U) -/*! XO_READY - Indicates XO out frequency statibilty. - * 0b0..XO output frequency is not yet stable. - * 0b1..XO output frequency is stable. - */ -#define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK) -/*! @} */ - -/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */ -/*! @{ */ - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U) -/*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control. - * 0b0..BOD VBAT interrupt is disabled. - * 0b1..BOD VBAT interrupt is enabled. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U) -/*! BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U) -/*! BODCORE_INT_ENABLE - BOD CORE interrupt control. - * 0b0..BOD CORE interrupt is disabled. - * 0b1..BOD CORE interrupt is enabled. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U) -/*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U) -/*! DCDC_INT_ENABLE - DCDC interrupt control. - * 0b0..DCDC interrupt is disabled. - * 0b1..DCDC interrupt is enabled. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U) -/*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK) -/*! @} */ - -/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */ -/*! @{ */ - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U) -/*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U) -/*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U) -/*! BODVBAT_VAL - Current value of BOD VBAT power status output. - * 0b0..VBAT voltage level is below the threshold. - * 0b1..VBAT voltage level is above the threshold. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U) -/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U) -/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U) -/*! BODCORE_VAL - Current value of BOD CORE power status output. - * 0b0..CORE voltage level is below the threshold. - * 0b1..CORE voltage level is above the threshold. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U) -/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U) -/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U) -/*! DCDC_VAL - Current value of DCDC power status output. - * 0b0..DCDC output Voltage is below the targeted regulation level. - * 0b1..DCDC output Voltage is above the targeted regulation level. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK) -/*! @} */ - -/*! @name RINGO0_CTRL - First Ring Oscillator module control register. */ -/*! @{ */ - -#define ANACTRL_RINGO0_CTRL_SL_MASK (0x1U) -#define ANACTRL_RINGO0_CTRL_SL_SHIFT (0U) -/*! SL - Select short or long ringo (for all ringos types). - * 0b0..Select short ringo (few elements). - * 0b1..Select long ringo (many elements). - */ -#define ANACTRL_RINGO0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK) - -#define ANACTRL_RINGO0_CTRL_FS_MASK (0x2U) -#define ANACTRL_RINGO0_CTRL_FS_SHIFT (1U) -/*! FS - Ringo frequency output divider. - * 0b0..High frequency output (frequency lower than 100 MHz). - * 0b1..Low frequency output (frequency lower than 10 MHz). - */ -#define ANACTRL_RINGO0_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK) - -#define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK (0xCU) -#define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT (2U) -/*! SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control. - * 0b00..Normal mode. - * 0b01..P-Monitor mode. Measure with weak P transistor. - * 0b10..P-Monitor mode. Measure with weak N transistor. - * 0b11..Don't use. - */ -#define ANACTRL_RINGO0_CTRL_SWN_SWP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK) - -#define ANACTRL_RINGO0_CTRL_PD_MASK (0x10U) -#define ANACTRL_RINGO0_CTRL_PD_SHIFT (4U) -/*! PD - Ringo module Power control. - * 0b0..The Ringo module is enabled. - * 0b1..The Ringo module is disabled. - */ -#define ANACTRL_RINGO0_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK) - -#define ANACTRL_RINGO0_CTRL_E_ND0_MASK (0x20U) -#define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT (5U) -/*! E_ND0 - First NAND2-based ringo control. - * 0b0..First NAND2-based ringo is disabled. - * 0b1..First NAND2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_ND0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK) - -#define ANACTRL_RINGO0_CTRL_E_ND1_MASK (0x40U) -#define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT (6U) -/*! E_ND1 - Second NAND2-based ringo control. - * 0b0..Second NAND2-based ringo is disabled. - * 0b1..Second NAND2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_ND1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK) - -#define ANACTRL_RINGO0_CTRL_E_NR0_MASK (0x80U) -#define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT (7U) -/*! E_NR0 - First NOR2-based ringo control. - * 0b0..First NOR2-based ringo is disabled. - * 0b1..First NOR2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_NR0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK) - -#define ANACTRL_RINGO0_CTRL_E_NR1_MASK (0x100U) -#define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT (8U) -/*! E_NR1 - Second NOR2-based ringo control. - * 0b0..Second NORD2-based ringo is disabled. - * 0b1..Second NORD2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_NR1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK) - -#define ANACTRL_RINGO0_CTRL_E_IV0_MASK (0x200U) -#define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT (9U) -/*! E_IV0 - First Inverter-based ringo control. - * 0b0..First INV-based ringo is disabled. - * 0b1..First INV-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_IV0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK) - -#define ANACTRL_RINGO0_CTRL_E_IV1_MASK (0x400U) -#define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT (10U) -/*! E_IV1 - Second Inverter-based ringo control. - * 0b0..Second INV-based ringo is disabled. - * 0b1..Second INV-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_IV1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK) - -#define ANACTRL_RINGO0_CTRL_E_PN0_MASK (0x800U) -#define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT (11U) -/*! E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control. - * 0b0..First PN-based ringo is disabled. - * 0b1..First PN-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_PN0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK) - -#define ANACTRL_RINGO0_CTRL_E_PN1_MASK (0x1000U) -#define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT (12U) -/*! E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control. - * 0b0..Second PN-based ringo is disabled. - * 0b1..Second PN-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_PN1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK) - -#define ANACTRL_RINGO0_CTRL_DIVISOR_MASK (0xF0000U) -#define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT (16U) -/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) - */ -#define ANACTRL_RINGO0_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK) - -#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) -#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT (31U) -/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider - * value, cleared when the change is complete. - */ -#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK) -/*! @} */ - -/*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */ -/*! @{ */ - -#define ANACTRL_RINGO1_CTRL_S_MASK (0x1U) -#define ANACTRL_RINGO1_CTRL_S_SHIFT (0U) -/*! S - Select short or long ringo (for all ringos types). - * 0b0..Select short ringo (few elements). - * 0b1..Select long ringo (many elements). - */ -#define ANACTRL_RINGO1_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK) - -#define ANACTRL_RINGO1_CTRL_FS_MASK (0x2U) -#define ANACTRL_RINGO1_CTRL_FS_SHIFT (1U) -/*! FS - Ringo frequency output divider. - * 0b0..High frequency output (frequency lower than 100 MHz). - * 0b1..Low frequency output (frequency lower than 10 MHz). - */ -#define ANACTRL_RINGO1_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK) - -#define ANACTRL_RINGO1_CTRL_PD_MASK (0x4U) -#define ANACTRL_RINGO1_CTRL_PD_SHIFT (2U) -/*! PD - Ringo module Power control. - * 0b0..The Ringo module is enabled. - * 0b1..The Ringo module is disabled. - */ -#define ANACTRL_RINGO1_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK) - -#define ANACTRL_RINGO1_CTRL_E_R24_MASK (0x8U) -#define ANACTRL_RINGO1_CTRL_E_R24_SHIFT (3U) -/*! E_R24 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK) - -#define ANACTRL_RINGO1_CTRL_E_R35_MASK (0x10U) -#define ANACTRL_RINGO1_CTRL_E_R35_SHIFT (4U) -/*! E_R35 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK) - -#define ANACTRL_RINGO1_CTRL_E_M2_MASK (0x20U) -#define ANACTRL_RINGO1_CTRL_E_M2_SHIFT (5U) -/*! E_M2 - Metal 2 (M2) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK) - -#define ANACTRL_RINGO1_CTRL_E_M3_MASK (0x40U) -#define ANACTRL_RINGO1_CTRL_E_M3_SHIFT (6U) -/*! E_M3 - Metal 3 (M3) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK) - -#define ANACTRL_RINGO1_CTRL_E_M4_MASK (0x80U) -#define ANACTRL_RINGO1_CTRL_E_M4_SHIFT (7U) -/*! E_M4 - Metal 4 (M4) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK) - -#define ANACTRL_RINGO1_CTRL_E_M5_MASK (0x100U) -#define ANACTRL_RINGO1_CTRL_E_M5_SHIFT (8U) -/*! E_M5 - Metal 5 (M5) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK) - -#define ANACTRL_RINGO1_CTRL_DIVISOR_MASK (0xF0000U) -#define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT (16U) -/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) - */ -#define ANACTRL_RINGO1_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK) - -#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) -#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT (31U) -/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider - * value, cleared when the change is complete. - */ -#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK) -/*! @} */ - -/*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */ -/*! @{ */ - -#define ANACTRL_RINGO2_CTRL_S_MASK (0x1U) -#define ANACTRL_RINGO2_CTRL_S_SHIFT (0U) -/*! S - Select short or long ringo (for all ringos types). - * 0b0..Select short ringo (few elements). - * 0b1..Select long ringo (many elements). - */ -#define ANACTRL_RINGO2_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK) - -#define ANACTRL_RINGO2_CTRL_FS_MASK (0x2U) -#define ANACTRL_RINGO2_CTRL_FS_SHIFT (1U) -/*! FS - Ringo frequency output divider. - * 0b0..High frequency output (frequency lower than 100 MHz). - * 0b1..Low frequency output (frequency lower than 10 MHz). - */ -#define ANACTRL_RINGO2_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK) - -#define ANACTRL_RINGO2_CTRL_PD_MASK (0x4U) -#define ANACTRL_RINGO2_CTRL_PD_SHIFT (2U) -/*! PD - Ringo module Power control. - * 0b0..The Ringo module is enabled. - * 0b1..The Ringo module is disabled. - */ -#define ANACTRL_RINGO2_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK) - -#define ANACTRL_RINGO2_CTRL_E_R24_MASK (0x8U) -#define ANACTRL_RINGO2_CTRL_E_R24_SHIFT (3U) -/*! E_R24 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK) - -#define ANACTRL_RINGO2_CTRL_E_R35_MASK (0x10U) -#define ANACTRL_RINGO2_CTRL_E_R35_SHIFT (4U) -/*! E_R35 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK) - -#define ANACTRL_RINGO2_CTRL_E_M2_MASK (0x20U) -#define ANACTRL_RINGO2_CTRL_E_M2_SHIFT (5U) -/*! E_M2 - Metal 2 (M2) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK) - -#define ANACTRL_RINGO2_CTRL_E_M3_MASK (0x40U) -#define ANACTRL_RINGO2_CTRL_E_M3_SHIFT (6U) -/*! E_M3 - Metal 3 (M3) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK) - -#define ANACTRL_RINGO2_CTRL_E_M4_MASK (0x80U) -#define ANACTRL_RINGO2_CTRL_E_M4_SHIFT (7U) -/*! E_M4 - Metal 4 (M4) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK) - -#define ANACTRL_RINGO2_CTRL_E_M5_MASK (0x100U) -#define ANACTRL_RINGO2_CTRL_E_M5_SHIFT (8U) -/*! E_M5 - Metal 5 (M5) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK) - -#define ANACTRL_RINGO2_CTRL_DIVISOR_MASK (0xF0000U) -#define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT (16U) -/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) - */ -#define ANACTRL_RINGO2_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK) - -#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) -#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT (31U) -/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider - * value, cleared when the change is complete. - */ -#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK) -/*! @} */ - -/*! @name LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register */ -/*! @{ */ - -#define ANACTRL_LDO_XO32M_BYPASS_MASK (0x2U) -#define ANACTRL_LDO_XO32M_BYPASS_SHIFT (1U) -/*! BYPASS - Activate LDO bypass. - * 0b0..Disable bypass mode (for normal operations). - * 0b1..Activate LDO bypass. - */ -#define ANACTRL_LDO_XO32M_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_BYPASS_SHIFT)) & ANACTRL_LDO_XO32M_BYPASS_MASK) - -#define ANACTRL_LDO_XO32M_HIGHZ_MASK (0x4U) -#define ANACTRL_LDO_XO32M_HIGHZ_SHIFT (2U) -/*! HIGHZ - . - * 0b0..Output in High normal state. - * 0b1..Output in High Impedance state. - */ -#define ANACTRL_LDO_XO32M_HIGHZ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_HIGHZ_SHIFT)) & ANACTRL_LDO_XO32M_HIGHZ_MASK) - -#define ANACTRL_LDO_XO32M_VOUT_MASK (0x38U) -#define ANACTRL_LDO_XO32M_VOUT_SHIFT (3U) -/*! VOUT - Sets the LDO output level. - * 0b000..0.750 V. - * 0b001..0.775 V. - * 0b010..0.800 V. - * 0b011..0.825 V. - * 0b100..0.850 V. - * 0b101..0.875 V. - * 0b110..0.900 V. - * 0b111..0.925 V. - */ -#define ANACTRL_LDO_XO32M_VOUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_VOUT_SHIFT)) & ANACTRL_LDO_XO32M_VOUT_MASK) - -#define ANACTRL_LDO_XO32M_IBIAS_MASK (0xC0U) -#define ANACTRL_LDO_XO32M_IBIAS_SHIFT (6U) -/*! IBIAS - Adjust the biasing current. - */ -#define ANACTRL_LDO_XO32M_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_IBIAS_SHIFT)) & ANACTRL_LDO_XO32M_IBIAS_MASK) - -#define ANACTRL_LDO_XO32M_STABMODE_MASK (0x300U) -#define ANACTRL_LDO_XO32M_STABMODE_SHIFT (8U) -/*! STABMODE - Stability configuration. - */ -#define ANACTRL_LDO_XO32M_STABMODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_STABMODE_SHIFT)) & ANACTRL_LDO_XO32M_STABMODE_MASK) -/*! @} */ - -/*! @name AUX_BIAS - AUX_BIAS */ -/*! @{ */ - -#define ANACTRL_AUX_BIAS_VREF1VENABLE_MASK (0x2U) -#define ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT (1U) -/*! VREF1VENABLE - Control output of 1V reference voltage. - * 0b0..Output of 1V reference voltage buffer is bypassed. - * 0b1..Output of 1V reference voltage is enabled. - */ -#define ANACTRL_AUX_BIAS_VREF1VENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VENABLE_MASK) - -#define ANACTRL_AUX_BIAS_ITRIM_MASK (0x7CU) -#define ANACTRL_AUX_BIAS_ITRIM_SHIFT (2U) -/*! ITRIM - current trimming control word. - */ -#define ANACTRL_AUX_BIAS_ITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIM_SHIFT)) & ANACTRL_AUX_BIAS_ITRIM_MASK) - -#define ANACTRL_AUX_BIAS_PTATITRIM_MASK (0xF80U) -#define ANACTRL_AUX_BIAS_PTATITRIM_SHIFT (7U) -/*! PTATITRIM - current trimming control word for ptat current. - */ -#define ANACTRL_AUX_BIAS_PTATITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_PTATITRIM_SHIFT)) & ANACTRL_AUX_BIAS_PTATITRIM_MASK) - -#define ANACTRL_AUX_BIAS_VREF1VTRIM_MASK (0x1F000U) -#define ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT (12U) -/*! VREF1VTRIM - voltage trimming control word. - */ -#define ANACTRL_AUX_BIAS_VREF1VTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VTRIM_MASK) - -#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK (0xE0000U) -#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT (17U) -/*! VREF1VCURVETRIM - Control bit to configure trimming state of mirror. - */ -#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK) - -#define ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK (0x100000U) -#define ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT (20U) -/*! ITRIMCTRL0 - Control bit to configure trimming state of mirror. - */ -#define ANACTRL_AUX_BIAS_ITRIMCTRL0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK) - -#define ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK (0x200000U) -#define ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT (21U) -/*! ITRIMCTRL1 - Control bit to configure trimming state of mirror. - */ -#define ANACTRL_AUX_BIAS_ITRIMCTRL1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK) -/*! @} */ - -/*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */ -/*! @{ */ - -#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK (0x1U) -#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT (0U) -/*! usb_vbusvalid_ext - Override value for Vbus if using external detectors. - */ -#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK) - -#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK (0x2U) -#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT (1U) -/*! usb_id_ext - Override value for ID if using external detectors. - */ -#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK) -/*! @} */ - -/*! @name USBHS_PHY_TRIM - USB High Speed Phy Trim values */ -/*! @{ */ - -#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK (0x3U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT (0U) -/*! trim_usb_reg_env_tail_adj_vd - Adjusts time constant of HS RX squelch (envelope) comparator. - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK (0x3CU) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT (2U) -/*! trim_usbphy_tx_d_cal - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK (0x7C0U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT (6U) -/*! trim_usbphy_tx_cal45dp - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK (0xF800U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT (11U) -/*! trim_usbphy_tx_cal45dm - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK (0x30000U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT (16U) -/*! trim_usb2_refbias_tst - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK (0x1C0000U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT (18U) -/*! trim_usb2_refbias_vbgadj - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK (0xE00000U) -#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT (21U) -/*! trim_pll_ctrl0_div_sel - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ANACTRL_Register_Masks */ - - -/* ANACTRL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE (0x50013000u) - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE_NS (0x40013000u) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS) - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS { ANACTRL } - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS } -#else - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE (0x40013000u) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS { ANACTRL } -#endif - -/*! - * @} - */ /* end of group ANACTRL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CASPER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CASPER_Peripheral_Access_Layer CASPER Peripheral Access Layer - * @{ - */ - -/** CASPER - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL0; /**< Contains the offsets of AB and CD in the RAM., offset: 0x0 */ - __IO uint32_t CTRL1; /**< Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR., offset: 0x4 */ - __IO uint32_t LOADER; /**< Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations., offset: 0x8 */ - __IO uint32_t STATUS; /**< Indicates operational status and would contain the carry bit if used., offset: 0xC */ - __IO uint32_t INTENSET; /**< Sets interrupts, offset: 0x10 */ - __IO uint32_t INTENCLR; /**< Clears interrupts, offset: 0x14 */ - __I uint32_t INTSTAT; /**< Interrupt status bits (mask of INTENSET and STATUS), offset: 0x18 */ - uint8_t RESERVED_0[4]; - __IO uint32_t AREG; /**< A register, offset: 0x20 */ - __IO uint32_t BREG; /**< B register, offset: 0x24 */ - __IO uint32_t CREG; /**< C register, offset: 0x28 */ - __IO uint32_t DREG; /**< D register, offset: 0x2C */ - __IO uint32_t RES0; /**< Result register 0, offset: 0x30 */ - __IO uint32_t RES1; /**< Result register 1, offset: 0x34 */ - __IO uint32_t RES2; /**< Result register 2, offset: 0x38 */ - __IO uint32_t RES3; /**< Result register 3, offset: 0x3C */ - uint8_t RESERVED_1[32]; - __IO uint32_t MASK; /**< Optional mask register, offset: 0x60 */ - __IO uint32_t REMASK; /**< Optional re-mask register, offset: 0x64 */ - uint8_t RESERVED_2[24]; - __IO uint32_t LOCK; /**< Security lock register, offset: 0x80 */ -} CASPER_Type; - -/* ---------------------------------------------------------------------------- - -- CASPER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CASPER_Register_Masks CASPER Register Masks - * @{ - */ - -/*! @name CTRL0 - Contains the offsets of AB and CD in the RAM. */ -/*! @{ */ - -#define CASPER_CTRL0_ABBPAIR_MASK (0x1U) -#define CASPER_CTRL0_ABBPAIR_SHIFT (0U) -/*! ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_CTRL0_ABBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK) - -#define CASPER_CTRL0_ABOFF_MASK (0x1FFCU) -#define CASPER_CTRL0_ABOFF_SHIFT (2U) -/*! ABOFF - Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code - * sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed - * if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up - */ -#define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK) - -#define CASPER_CTRL0_CDBPAIR_MASK (0x10000U) -#define CASPER_CTRL0_CDBPAIR_SHIFT (16U) -/*! CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_CTRL0_CDBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK) - -#define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U) -#define CASPER_CTRL0_CDOFF_SHIFT (18U) -/*! CDOFF - Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees - * (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 - * bit operation. Ideally not in the same RAM as the AB values - */ -#define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK) -/*! @} */ - -/*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */ -/*! @{ */ - -#define CASPER_CTRL1_ITER_MASK (0xFFU) -#define CASPER_CTRL1_ITER_SHIFT (0U) -/*! ITER - Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate. - */ -#define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK) - -#define CASPER_CTRL1_MODE_MASK (0xFF00U) -#define CASPER_CTRL1_MODE_SHIFT (8U) -/*! MODE - Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active. - */ -#define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK) - -#define CASPER_CTRL1_RESBPAIR_MASK (0x10000U) -#define CASPER_CTRL1_RESBPAIR_SHIFT (16U) -/*! RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally - * this is not the same bank as ABBPAIR (when 4-up supported) - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_CTRL1_RESBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK) - -#define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U) -#define CASPER_CTRL1_RESOFF_SHIFT (18U) -/*! RESOFF - Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally - * not in the same RAM as the AB and CD values - */ -#define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK) - -#define CASPER_CTRL1_CSKIP_MASK (0xC0000000U) -#define CASPER_CTRL1_CSKIP_SHIFT (30U) -/*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: - * 0b00..No Skip - * 0b01..Skip if Carry is 1 - * 0b10..Skip if Carry is 0 - * 0b11..Set CTRLOFF to CDOFF and Skip - */ -#define CASPER_CTRL1_CSKIP(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK) -/*! @} */ - -/*! @name LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. */ -/*! @{ */ - -#define CASPER_LOADER_COUNT_MASK (0xFFU) -#define CASPER_LOADER_COUNT_SHIFT (0U) -/*! COUNT - Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one - * op - does not iterate, write N means N control pairs to load - */ -#define CASPER_LOADER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK) - -#define CASPER_LOADER_CTRLBPAIR_MASK (0x10000U) -#define CASPER_LOADER_CTRLBPAIR_SHIFT (16U) -/*! CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not - * matter which bank is used as this is loaded when not performing an operation. - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_LOADER_CTRLBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK) - -#define CASPER_LOADER_CTRLOFF_MASK (0x1FFC0000U) -#define CASPER_LOADER_CTRLOFF_SHIFT (18U) -/*! CTRLOFF - DWord Offset of CTRL pair to load next. - */ -#define CASPER_LOADER_CTRLOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK) -/*! @} */ - -/*! @name STATUS - Indicates operational status and would contain the carry bit if used. */ -/*! @{ */ - -#define CASPER_STATUS_DONE_MASK (0x1U) -#define CASPER_STATUS_DONE_SHIFT (0U) -/*! DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. - * 0b0..Busy or just cleared - * 0b1..Completed last operation - */ -#define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK) - -#define CASPER_STATUS_CARRY_MASK (0x10U) -#define CASPER_STATUS_CARRY_SHIFT (4U) -/*! CARRY - Last carry value if operation produced a carry bit - * 0b0..Carry was 0 or no carry - * 0b1..Carry was 1 - */ -#define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK) - -#define CASPER_STATUS_BUSY_MASK (0x20U) -#define CASPER_STATUS_BUSY_SHIFT (5U) -/*! BUSY - Indicates if the accelerator is busy performing an operation - * 0b0..Not busy - is idle - * 0b1..Is busy - */ -#define CASPER_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK) -/*! @} */ - -/*! @name INTENSET - Sets interrupts */ -/*! @{ */ - -#define CASPER_INTENSET_DONE_MASK (0x1U) -#define CASPER_INTENSET_DONE_SHIFT (0U) -/*! DONE - Set if the accelerator should interrupt when done. - * 0b0..Do not interrupt when done - * 0b1..Interrupt when done - */ -#define CASPER_INTENSET_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK) -/*! @} */ - -/*! @name INTENCLR - Clears interrupts */ -/*! @{ */ - -#define CASPER_INTENCLR_DONE_MASK (0x1U) -#define CASPER_INTENCLR_DONE_SHIFT (0U) -/*! DONE - Written to clear an interrupt set with INTENSET. - * 0b0..If written 0, ignored - * 0b1..If written 1, do not Interrupt when done - */ -#define CASPER_INTENCLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) */ -/*! @{ */ - -#define CASPER_INTSTAT_DONE_MASK (0x1U) -#define CASPER_INTSTAT_DONE_SHIFT (0U) -/*! DONE - If set, interrupt is caused by accelerator being done. - * 0b0..Not caused by accelerator being done - * 0b1..Caused by accelerator being done - */ -#define CASPER_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK) -/*! @} */ - -/*! @name AREG - A register */ -/*! @{ */ - -#define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_AREG_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, - * but is available when accelerator not busy. - */ -#define CASPER_AREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name BREG - B register */ -/*! @{ */ - -#define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_BREG_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, - * but is available when accelerator not busy. - */ -#define CASPER_BREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name CREG - C register */ -/*! @{ */ - -#define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_CREG_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, - * but is available when accelerator not busy. - */ -#define CASPER_CREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name DREG - D register */ -/*! @{ */ - -#define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_DREG_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, - * but is available when accelerator not busy. - */ -#define CASPER_DREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES0 - Result register 0 */ -/*! @{ */ - -#define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES0_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally - * written or read by application, but is available when accelerator not busy. - */ -#define CASPER_RES0_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES1 - Result register 1 */ -/*! @{ */ - -#define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES1_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally - * written or read by application, but is available when accelerator not busy. - */ -#define CASPER_RES1_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES2 - Result register 2 */ -/*! @{ */ - -#define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES2_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally - * written or read by application, but is available when accelerator not busy. - */ -#define CASPER_RES2_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES3 - Result register 3 */ -/*! @{ */ - -#define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES3_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally - * written or read by application, but is available when accelerator not busy. - */ -#define CASPER_RES3_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK) -/*! @} */ - -/*! @name MASK - Optional mask register */ -/*! @{ */ - -#define CASPER_MASK_MASK_MASK (0xFFFFFFFFU) -#define CASPER_MASK_MASK_SHIFT (0U) -/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values - */ -#define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK) -/*! @} */ - -/*! @name REMASK - Optional re-mask register */ -/*! @{ */ - -#define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU) -#define CASPER_REMASK_MASK_SHIFT (0U) -/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values - */ -#define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK) -/*! @} */ - -/*! @name LOCK - Security lock register */ -/*! @{ */ - -#define CASPER_LOCK_LOCK_MASK (0x1U) -#define CASPER_LOCK_LOCK_SHIFT (0U) -/*! LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. - * 0b0..unlock - * 0b1..Lock to current security level - */ -#define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK) - -#define CASPER_LOCK_KEY_MASK (0x1FFF0U) -#define CASPER_LOCK_KEY_SHIFT (4U) -/*! KEY - Must be written as 0x73D to change the register. - * 0b0011100111101..If set during write, will allow lock or unlock - */ -#define CASPER_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CASPER_Register_Masks */ - - -/* CASPER - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CASPER base address */ - #define CASPER_BASE (0x500A5000u) - /** Peripheral CASPER base address */ - #define CASPER_BASE_NS (0x400A5000u) - /** Peripheral CASPER base pointer */ - #define CASPER ((CASPER_Type *)CASPER_BASE) - /** Peripheral CASPER base pointer */ - #define CASPER_NS ((CASPER_Type *)CASPER_BASE_NS) - /** Array initializer of CASPER peripheral base addresses */ - #define CASPER_BASE_ADDRS { CASPER_BASE } - /** Array initializer of CASPER peripheral base pointers */ - #define CASPER_BASE_PTRS { CASPER } - /** Array initializer of CASPER peripheral base addresses */ - #define CASPER_BASE_ADDRS_NS { CASPER_BASE_NS } - /** Array initializer of CASPER peripheral base pointers */ - #define CASPER_BASE_PTRS_NS { CASPER_NS } -#else - /** Peripheral CASPER base address */ - #define CASPER_BASE (0x400A5000u) - /** Peripheral CASPER base pointer */ - #define CASPER ((CASPER_Type *)CASPER_BASE) - /** Array initializer of CASPER peripheral base addresses */ - #define CASPER_BASE_ADDRS { CASPER_BASE } - /** Array initializer of CASPER peripheral base pointers */ - #define CASPER_BASE_PTRS { CASPER } -#endif -/** Interrupt vectors for the CASPER peripheral type */ -#define CASPER_IRQS { CASER_IRQn } - -/*! - * @} - */ /* end of group CASPER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CRC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer - * @{ - */ - -/** CRC - Register Layout Typedef */ -typedef struct { - __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ - __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ - union { /* offset: 0x8 */ - __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ - __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ - }; -} CRC_Type; - -/* ---------------------------------------------------------------------------- - -- CRC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Register_Masks CRC Register Masks - * @{ - */ - -/*! @name MODE - CRC mode register */ -/*! @{ */ - -#define CRC_MODE_CRC_POLY_MASK (0x3U) -#define CRC_MODE_CRC_POLY_SHIFT (0U) -/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial - */ -#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) - -#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) -#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) -/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) - */ -#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) - -#define CRC_MODE_CMPL_WR_MASK (0x8U) -#define CRC_MODE_CMPL_WR_SHIFT (3U) -/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA - */ -#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) - -#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) -#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) -/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM - */ -#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) - -#define CRC_MODE_CMPL_SUM_MASK (0x20U) -#define CRC_MODE_CMPL_SUM_SHIFT (5U) -/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM - */ -#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) -/*! @} */ - -/*! @name SEED - CRC seed register */ -/*! @{ */ - -#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) -#define CRC_SEED_CRC_SEED_SHIFT (0U) -/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with - * selected bit order and 1's complement pre-processes. A write access to this register will - * overrule the CRC calculation in progresses. - */ -#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) -/*! @} */ - -/*! @name SUM - CRC checksum register */ -/*! @{ */ - -#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) -#define CRC_SUM_CRC_SUM_SHIFT (0U) -/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. - */ -#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) -/*! @} */ - -/*! @name WR_DATA - CRC data register */ -/*! @{ */ - -#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) -#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) -/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with - * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and - * accept back-to-back transactions. - */ -#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CRC_Register_Masks */ - - -/* CRC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CRC_ENGINE base address */ - #define CRC_ENGINE_BASE (0x50095000u) - /** Peripheral CRC_ENGINE base address */ - #define CRC_ENGINE_BASE_NS (0x40095000u) - /** Peripheral CRC_ENGINE base pointer */ - #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) - /** Peripheral CRC_ENGINE base pointer */ - #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS) - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS { CRC_ENGINE } - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS } -#else - /** Peripheral CRC_ENGINE base address */ - #define CRC_ENGINE_BASE (0x40095000u) - /** Peripheral CRC_ENGINE base pointer */ - #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS { CRC_ENGINE } -#endif - -/*! - * @} - */ /* end of group CRC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CTIMER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer - * @{ - */ - -/** CTIMER - Register Layout Typedef */ -typedef struct { - __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ - __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ - __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ - __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ - __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ - __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ - __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ - __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ - __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ - __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ - uint8_t RESERVED_0[48]; - __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ - __IO uint32_t PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */ - __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ -} CTIMER_Type; - -/* ---------------------------------------------------------------------------- - -- CTIMER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Register_Masks CTIMER Register Masks - * @{ - */ - -/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ -/*! @{ */ - -#define CTIMER_IR_MR0INT_MASK (0x1U) -#define CTIMER_IR_MR0INT_SHIFT (0U) -/*! MR0INT - Interrupt flag for match channel 0. - */ -#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) - -#define CTIMER_IR_MR1INT_MASK (0x2U) -#define CTIMER_IR_MR1INT_SHIFT (1U) -/*! MR1INT - Interrupt flag for match channel 1. - */ -#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) - -#define CTIMER_IR_MR2INT_MASK (0x4U) -#define CTIMER_IR_MR2INT_SHIFT (2U) -/*! MR2INT - Interrupt flag for match channel 2. - */ -#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) - -#define CTIMER_IR_MR3INT_MASK (0x8U) -#define CTIMER_IR_MR3INT_SHIFT (3U) -/*! MR3INT - Interrupt flag for match channel 3. - */ -#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) - -#define CTIMER_IR_CR0INT_MASK (0x10U) -#define CTIMER_IR_CR0INT_SHIFT (4U) -/*! CR0INT - Interrupt flag for capture channel 0 event. - */ -#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) - -#define CTIMER_IR_CR1INT_MASK (0x20U) -#define CTIMER_IR_CR1INT_SHIFT (5U) -/*! CR1INT - Interrupt flag for capture channel 1 event. - */ -#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) - -#define CTIMER_IR_CR2INT_MASK (0x40U) -#define CTIMER_IR_CR2INT_SHIFT (6U) -/*! CR2INT - Interrupt flag for capture channel 2 event. - */ -#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) - -#define CTIMER_IR_CR3INT_MASK (0x80U) -#define CTIMER_IR_CR3INT_SHIFT (7U) -/*! CR3INT - Interrupt flag for capture channel 3 event. - */ -#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) -/*! @} */ - -/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ -/*! @{ */ - -#define CTIMER_TCR_CEN_MASK (0x1U) -#define CTIMER_TCR_CEN_SHIFT (0U) -/*! CEN - Counter enable. - * 0b0..Disabled.The counters are disabled. - * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. - */ -#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) - -#define CTIMER_TCR_CRST_MASK (0x2U) -#define CTIMER_TCR_CRST_SHIFT (1U) -/*! CRST - Counter reset. - * 0b0..Disabled. Do nothing. - * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of - * the APB bus clock. The counters remain reset until TCR[1] is returned to zero. - */ -#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) -/*! @} */ - -/*! @name TC - Timer Counter */ -/*! @{ */ - -#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_TC_TCVAL_SHIFT (0U) -/*! TCVAL - Timer counter value. - */ -#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) -/*! @} */ - -/*! @name PR - Prescale Register */ -/*! @{ */ - -#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PR_PRVAL_SHIFT (0U) -/*! PRVAL - Prescale counter value. - */ -#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) -/*! @} */ - -/*! @name PC - Prescale Counter */ -/*! @{ */ - -#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PC_PCVAL_SHIFT (0U) -/*! PCVAL - Prescale counter value. - */ -#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) -/*! @} */ - -/*! @name MCR - Match Control Register */ -/*! @{ */ - -#define CTIMER_MCR_MR0I_MASK (0x1U) -#define CTIMER_MCR_MR0I_SHIFT (0U) -/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. - */ -#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) - -#define CTIMER_MCR_MR0R_MASK (0x2U) -#define CTIMER_MCR_MR0R_SHIFT (1U) -/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. - */ -#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) - -#define CTIMER_MCR_MR0S_MASK (0x4U) -#define CTIMER_MCR_MR0S_SHIFT (2U) -/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. - */ -#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) - -#define CTIMER_MCR_MR1I_MASK (0x8U) -#define CTIMER_MCR_MR1I_SHIFT (3U) -/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. - */ -#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) - -#define CTIMER_MCR_MR1R_MASK (0x10U) -#define CTIMER_MCR_MR1R_SHIFT (4U) -/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. - */ -#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) - -#define CTIMER_MCR_MR1S_MASK (0x20U) -#define CTIMER_MCR_MR1S_SHIFT (5U) -/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. - */ -#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) - -#define CTIMER_MCR_MR2I_MASK (0x40U) -#define CTIMER_MCR_MR2I_SHIFT (6U) -/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. - */ -#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) - -#define CTIMER_MCR_MR2R_MASK (0x80U) -#define CTIMER_MCR_MR2R_SHIFT (7U) -/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. - */ -#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) - -#define CTIMER_MCR_MR2S_MASK (0x100U) -#define CTIMER_MCR_MR2S_SHIFT (8U) -/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. - */ -#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) - -#define CTIMER_MCR_MR3I_MASK (0x200U) -#define CTIMER_MCR_MR3I_SHIFT (9U) -/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. - */ -#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) - -#define CTIMER_MCR_MR3R_MASK (0x400U) -#define CTIMER_MCR_MR3R_SHIFT (10U) -/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it. - */ -#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) - -#define CTIMER_MCR_MR3S_MASK (0x800U) -#define CTIMER_MCR_MR3S_SHIFT (11U) -/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. - */ -#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) - -#define CTIMER_MCR_MR0RL_MASK (0x1000000U) -#define CTIMER_MCR_MR0RL_SHIFT (24U) -/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero - * (either via a match event or a write to bit 1 of the TCR). - */ -#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) - -#define CTIMER_MCR_MR1RL_MASK (0x2000000U) -#define CTIMER_MCR_MR1RL_SHIFT (25U) -/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero - * (either via a match event or a write to bit 1 of the TCR). - */ -#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) - -#define CTIMER_MCR_MR2RL_MASK (0x4000000U) -#define CTIMER_MCR_MR2RL_SHIFT (26U) -/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero - * (either via a match event or a write to bit 1 of the TCR). - */ -#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) - -#define CTIMER_MCR_MR3RL_MASK (0x8000000U) -#define CTIMER_MCR_MR3RL_SHIFT (27U) -/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero - * (either via a match event or a write to bit 1 of the TCR). - */ -#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) -/*! @} */ - -/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ -/*! @{ */ - -#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) -#define CTIMER_MR_MATCH_SHIFT (0U) -/*! MATCH - Timer counter match value. - */ -#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) -/*! @} */ - -/* The count of CTIMER_MR */ -#define CTIMER_MR_COUNT (4U) - -/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ -/*! @{ */ - -#define CTIMER_CCR_CAP0RE_MASK (0x1U) -#define CTIMER_CCR_CAP0RE_SHIFT (0U) -/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) - -#define CTIMER_CCR_CAP0FE_MASK (0x2U) -#define CTIMER_CCR_CAP0FE_SHIFT (1U) -/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) - -#define CTIMER_CCR_CAP0I_MASK (0x4U) -#define CTIMER_CCR_CAP0I_SHIFT (2U) -/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. - */ -#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) - -#define CTIMER_CCR_CAP1RE_MASK (0x8U) -#define CTIMER_CCR_CAP1RE_SHIFT (3U) -/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) - -#define CTIMER_CCR_CAP1FE_MASK (0x10U) -#define CTIMER_CCR_CAP1FE_SHIFT (4U) -/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) - -#define CTIMER_CCR_CAP1I_MASK (0x20U) -#define CTIMER_CCR_CAP1I_SHIFT (5U) -/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. - */ -#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) - -#define CTIMER_CCR_CAP2RE_MASK (0x40U) -#define CTIMER_CCR_CAP2RE_SHIFT (6U) -/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) - -#define CTIMER_CCR_CAP2FE_MASK (0x80U) -#define CTIMER_CCR_CAP2FE_SHIFT (7U) -/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) - -#define CTIMER_CCR_CAP2I_MASK (0x100U) -#define CTIMER_CCR_CAP2I_SHIFT (8U) -/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. - */ -#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) - -#define CTIMER_CCR_CAP3RE_MASK (0x200U) -#define CTIMER_CCR_CAP3RE_SHIFT (9U) -/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) - -#define CTIMER_CCR_CAP3FE_MASK (0x400U) -#define CTIMER_CCR_CAP3FE_SHIFT (10U) -/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) - -#define CTIMER_CCR_CAP3I_MASK (0x800U) -#define CTIMER_CCR_CAP3I_SHIFT (11U) -/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. - */ -#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) -/*! @} */ - -/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ -/*! @{ */ - -#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) -#define CTIMER_CR_CAP_SHIFT (0U) -/*! CAP - Timer counter capture value. - */ -#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) -/*! @} */ - -/* The count of CTIMER_CR */ -#define CTIMER_CR_COUNT (4U) - -/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ -/*! @{ */ - -#define CTIMER_EMR_EM0_MASK (0x1U) -#define CTIMER_EMR_EM0_SHIFT (0U) -/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output - * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, - * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if - * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - */ -#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) - -#define CTIMER_EMR_EM1_MASK (0x2U) -#define CTIMER_EMR_EM1_SHIFT (1U) -/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output - * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, - * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if - * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - */ -#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) - -#define CTIMER_EMR_EM2_MASK (0x4U) -#define CTIMER_EMR_EM2_SHIFT (2U) -/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output - * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, - * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if - * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - */ -#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) - -#define CTIMER_EMR_EM3_MASK (0x8U) -#define CTIMER_EMR_EM3_SHIFT (3U) -/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output - * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, - * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins - * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - */ -#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) - -#define CTIMER_EMR_EMC0_MASK (0x30U) -#define CTIMER_EMR_EMC0_SHIFT (4U) -/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) - -#define CTIMER_EMR_EMC1_MASK (0xC0U) -#define CTIMER_EMR_EMC1_SHIFT (6U) -/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) - -#define CTIMER_EMR_EMC2_MASK (0x300U) -#define CTIMER_EMR_EMC2_SHIFT (8U) -/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) - -#define CTIMER_EMR_EMC3_MASK (0xC00U) -#define CTIMER_EMR_EMC3_SHIFT (10U) -/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) -/*! @} */ - -/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ -/*! @{ */ - -#define CTIMER_CTCR_CTMODE_MASK (0x3U) -#define CTIMER_CTCR_CTMODE_SHIFT (0U) -/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment - * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC - * is incremented when the Prescale Counter matches the Prescale Register. - * 0b00..Timer Mode. Incremented every rising APB bus clock edge. - * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. - * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. - * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. - */ -#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) - -#define CTIMER_CTCR_CINSEL_MASK (0xCU) -#define CTIMER_CTCR_CINSEL_SHIFT (2U) -/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which - * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input - * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be - * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the - * same timer. - * 0b00..Channel 0. CAPn.0 for CTIMERn - * 0b01..Channel 1. CAPn.1 for CTIMERn - * 0b10..Channel 2. CAPn.2 for CTIMERn - * 0b11..Channel 3. CAPn.3 for CTIMERn - */ -#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) - -#define CTIMER_CTCR_ENCC_MASK (0x10U) -#define CTIMER_CTCR_ENCC_SHIFT (4U) -/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the - * capture-edge event specified in bits 7:5 occurs. - */ -#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) - -#define CTIMER_CTCR_SELCC_MASK (0xE0U) -#define CTIMER_CTCR_SELCC_SHIFT (5U) -/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the - * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to - * 0x3 and 0x6 to 0x7 are reserved. - * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - */ -#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) -/*! @} */ - -/*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */ -/*! @{ */ - -#define CTIMER_PWMC_PWMEN0_MASK (0x1U) -#define CTIMER_PWMC_PWMEN0_SHIFT (0U) -/*! PWMEN0 - PWM mode enable for channel0. - * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. - */ -#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) - -#define CTIMER_PWMC_PWMEN1_MASK (0x2U) -#define CTIMER_PWMC_PWMEN1_SHIFT (1U) -/*! PWMEN1 - PWM mode enable for channel1. - * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. - */ -#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) - -#define CTIMER_PWMC_PWMEN2_MASK (0x4U) -#define CTIMER_PWMC_PWMEN2_SHIFT (2U) -/*! PWMEN2 - PWM mode enable for channel2. - * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. - */ -#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) - -#define CTIMER_PWMC_PWMEN3_MASK (0x8U) -#define CTIMER_PWMC_PWMEN3_SHIFT (3U) -/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. - * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. - * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. - */ -#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) -/*! @} */ - -/*! @name MSR - Match Shadow Register */ -/*! @{ */ - -#define CTIMER_MSR_SHADOW_MASK (0xFFFFFFFFU) -#define CTIMER_MSR_SHADOW_SHIFT (0U) -/*! SHADOW - Timer counter match shadow value. - */ -#define CTIMER_MSR_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOW_SHIFT)) & CTIMER_MSR_SHADOW_MASK) -/*! @} */ - -/* The count of CTIMER_MSR */ -#define CTIMER_MSR_COUNT (4U) - - -/*! - * @} - */ /* end of group CTIMER_Register_Masks */ - - -/* CTIMER - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE (0x50008000u) - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE_NS (0x40008000u) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE (0x50009000u) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE_NS (0x40009000u) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE (0x50028000u) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE_NS (0x40028000u) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE (0x50029000u) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE_NS (0x40029000u) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE (0x5002A000u) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE_NS (0x4002A000u) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } -#else - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE (0x40008000u) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE (0x40009000u) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE (0x40028000u) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE (0x40029000u) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE (0x4002A000u) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } -#endif -/** Interrupt vectors for the CTIMER peripheral type */ -#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } - -/*! - * @} - */ /* end of group CTIMER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DBGMAILBOX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DBGMAILBOX_Peripheral_Access_Layer DBGMAILBOX Peripheral Access Layer - * @{ - */ - -/** DBGMAILBOX - Register Layout Typedef */ -typedef struct { - __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */ - __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */ - __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */ - uint8_t RESERVED_0[240]; - __I uint32_t ID; /**< Identification register, offset: 0xFC */ -} DBGMAILBOX_Type; - -/* ---------------------------------------------------------------------------- - -- DBGMAILBOX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DBGMAILBOX_Register_Masks DBGMAILBOX Register Masks - * @{ - */ - -/*! @name CSW - CRC mode register */ -/*! @{ */ - -#define DBGMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) -#define DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) -/*! RESYNCH_REQ - Debugger will set this bit to 1 to request a resynchronrisation - */ -#define DBGMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DBGMAILBOX_CSW_RESYNCH_REQ_MASK) - -#define DBGMAILBOX_CSW_REQ_PENDING_MASK (0x2U) -#define DBGMAILBOX_CSW_REQ_PENDING_SHIFT (1U) -/*! REQ_PENDING - Request is pending from debugger (i.e unread value in REQUEST) - */ -#define DBGMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DBGMAILBOX_CSW_REQ_PENDING_MASK) - -#define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) -#define DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) -/*! DBG_OR_ERR - Debugger overrun error (previous REQUEST overwritten before being picked up by ROM) - */ -#define DBGMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK) - -#define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) -#define DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) -/*! AHB_OR_ERR - AHB overrun Error (Return value overwritten by ROM) - */ -#define DBGMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK) - -#define DBGMAILBOX_CSW_SOFT_RESET_MASK (0x10U) -#define DBGMAILBOX_CSW_SOFT_RESET_SHIFT (4U) -/*! SOFT_RESET - Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to - * this bit will cause a soft reset for DM. - */ -#define DBGMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DBGMAILBOX_CSW_SOFT_RESET_MASK) - -#define DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) -#define DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) -/*! CHIP_RESET_REQ - Write only bit. Once written will cause the chip to reset (note that the DM is - * not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event) - */ -#define DBGMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK) -/*! @} */ - -/*! @name REQUEST - CRC seed register */ -/*! @{ */ - -#define DBGMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU) -#define DBGMAILBOX_REQUEST_REQ_SHIFT (0U) -/*! REQ - Request Value - */ -#define DBGMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_REQUEST_REQ_SHIFT)) & DBGMAILBOX_REQUEST_REQ_MASK) -/*! @} */ - -/*! @name RETURN - Return value from ROM. */ -/*! @{ */ - -#define DBGMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) -#define DBGMAILBOX_RETURN_RET_SHIFT (0U) -/*! RET - The Return value from ROM. - */ -#define DBGMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_RETURN_RET_SHIFT)) & DBGMAILBOX_RETURN_RET_MASK) -/*! @} */ - -/*! @name ID - Identification register */ -/*! @{ */ - -#define DBGMAILBOX_ID_ID_MASK (0xFFFFFFFFU) -#define DBGMAILBOX_ID_ID_SHIFT (0U) -/*! ID - Identification value. - */ -#define DBGMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_ID_ID_SHIFT)) & DBGMAILBOX_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group DBGMAILBOX_Register_Masks */ - - -/* DBGMAILBOX - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral DBGMAILBOX base address */ - #define DBGMAILBOX_BASE (0x5009C000u) - /** Peripheral DBGMAILBOX base address */ - #define DBGMAILBOX_BASE_NS (0x4009C000u) - /** Peripheral DBGMAILBOX base pointer */ - #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) - /** Peripheral DBGMAILBOX base pointer */ - #define DBGMAILBOX_NS ((DBGMAILBOX_Type *)DBGMAILBOX_BASE_NS) - /** Array initializer of DBGMAILBOX peripheral base addresses */ - #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } - /** Array initializer of DBGMAILBOX peripheral base pointers */ - #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } - /** Array initializer of DBGMAILBOX peripheral base addresses */ - #define DBGMAILBOX_BASE_ADDRS_NS { DBGMAILBOX_BASE_NS } - /** Array initializer of DBGMAILBOX peripheral base pointers */ - #define DBGMAILBOX_BASE_PTRS_NS { DBGMAILBOX_NS } -#else - /** Peripheral DBGMAILBOX base address */ - #define DBGMAILBOX_BASE (0x4009C000u) - /** Peripheral DBGMAILBOX base pointer */ - #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) - /** Array initializer of DBGMAILBOX peripheral base addresses */ - #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } - /** Array initializer of DBGMAILBOX peripheral base pointers */ - #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } -#endif - -/*! - * @} - */ /* end of group DBGMAILBOX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer - * @{ - */ - -/** DMA - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ - __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ - __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ - uint8_t RESERVED_0[20]; - struct { /* offset: 0x20, array step: 0x5C */ - __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ - uint8_t RESERVED_0[4]; - __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ - uint8_t RESERVED_1[4]; - __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ - uint8_t RESERVED_2[4]; - __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ - uint8_t RESERVED_3[4]; - __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ - uint8_t RESERVED_4[4]; - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ - uint8_t RESERVED_5[4]; - __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ - uint8_t RESERVED_6[4]; - __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ - uint8_t RESERVED_7[4]; - __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ - uint8_t RESERVED_8[4]; - __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ - uint8_t RESERVED_9[4]; - __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ - uint8_t RESERVED_10[4]; - __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ - } COMMON[1]; - uint8_t RESERVED_1[900]; - struct { /* offset: 0x400, array step: 0x10 */ - __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ - __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ - __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } CHANNEL[23]; -} DMA_Type; - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/*! @name CTRL - DMA control. */ -/*! @{ */ - -#define DMA_CTRL_ENABLE_MASK (0x1U) -#define DMA_CTRL_ENABLE_SHIFT (0U) -/*! ENABLE - DMA controller master enable. - * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when - * disabled, but does not prevent re-triggering when the DMA controller is re-enabled. - * 0b1..Enabled. The DMA controller is enabled. - */ -#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status. */ -/*! @{ */ - -#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) -#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) -/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. - * 0b0..Not pending. No enabled interrupts are pending. - * 0b1..Pending. At least one enabled interrupt is pending. - */ -#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) - -#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) -#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) -/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. - * 0b0..Not pending. No error interrupts are pending. - * 0b1..Pending. At least one error interrupt is pending. - */ -#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) -/*! @} */ - -/*! @name SRAMBASE - SRAM address of the channel configuration table. */ -/*! @{ */ - -#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) -#define DMA_SRAMBASE_OFFSET_SHIFT (9U) -/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the - * table must begin on a 512 byte boundary. - */ -#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) -/*! @} */ - -/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) -/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = - * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. - */ -#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLESET */ -#define DMA_COMMON_ENABLESET_COUNT (1U) - -/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) -/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears - * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits - * are reserved. - */ -#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLECLR */ -#define DMA_COMMON_ENABLECLR_COUNT (1U) - -/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) -/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = - * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. - */ -#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ACTIVE */ -#define DMA_COMMON_ACTIVE_COUNT (1U) - -/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) -#define DMA_COMMON_BUSY_BSY_SHIFT (0U) -/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = - * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. - */ -#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) -/*! @} */ - -/* The count of DMA_COMMON_BUSY */ -#define DMA_COMMON_BUSY_COUNT (1U) - -/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) -/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of - * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is - * not active. 1 = error interrupt is active. - */ -#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ERRINT */ -#define DMA_COMMON_ERRINT_COUNT (1U) - -/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) -/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The - * number of bits = number of DMA channels in this device. Other bits are reserved. 0 = - * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENSET */ -#define DMA_COMMON_INTENSET_COUNT (1U) - -/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) -/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n - * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are - * reserved. - */ -#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENCLR */ -#define DMA_COMMON_INTENCLR_COUNT (1U) - -/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTA_IA_SHIFT (0U) -/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of - * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel - * interrupt A is not active. 1 = the DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTA */ -#define DMA_COMMON_INTA_COUNT (1U) - -/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTB_IB_SHIFT (0U) -/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of - * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel - * interrupt B is not active. 1 = the DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTB */ -#define DMA_COMMON_INTB_COUNT (1U) - -/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETVALID_SV_SHIFT (0U) -/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits - * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the - * VALIDPENDING control bit for DMA channel n - */ -#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETVALID */ -#define DMA_COMMON_SETVALID_COUNT (1U) - -/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) -/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number - * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = - * sets the TRIG bit for DMA channel n. - */ -#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETTRIG */ -#define DMA_COMMON_SETTRIG_COUNT (1U) - -/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) -/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. - * 1 = aborts DMA operations on channel n. - */ -#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ABORT */ -#define DMA_COMMON_ABORT_COUNT (1U) - -/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ -/*! @{ */ - -#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) -#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) -/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory - * move, any peripheral DMA request associated with that channel can be disabled to prevent any - * interaction between the peripheral and the DMA controller. - * 0b0..Disabled. Peripheral DMA requests are disabled. - * 0b1..Enabled. Peripheral DMA requests are enabled. - */ -#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) - -#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) -#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) -/*! HWTRIGEN - Hardware Triggering Enable for this channel. - * 0b0..Disabled. Hardware triggering is not used. - * 0b1..Enabled. Use hardware triggering. - */ -#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) - -#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) -#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) -/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. - * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. - * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. - */ -#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) - -#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) -#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) -/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. - * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. - * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = - * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the - * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger - * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the - * current BURSTPOWER length are completed. - */ -#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) - -#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) -#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) -/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. - * 0b0..Single transfer. Hardware trigger causes a single transfer. - * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a - * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a - * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is - * complete. - */ -#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) - -#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) -#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) -/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when - * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). - * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many - * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that - * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: - * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = - * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The - * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even - * multiple of the burst size. - */ -#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) - -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) -/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is - * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this - * could be used to read several sequential registers from a peripheral for each DMA burst, - * reading the same registers again for each burst. - * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. - * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. - */ -#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) - -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) -/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is - * 'wrapped', meaning that the destination address range for each burst will be the same. As an - * example, this could be used to write several sequential registers to a peripheral for each DMA - * burst, writing the same registers again for each burst. - * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. - * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. - */ -#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) - -#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) -#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) -/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority - * levels are supported: 0x0 = highest priority. 0x7 = lowest priority. - */ -#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CFG */ -#define DMA_CHANNEL_CFG_COUNT (23U) - -/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ -/*! @{ */ - -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) -/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the - * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. - * 0b0..No effect. No effect on DMA operation. - * 0b1..Valid pending. - */ -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) - -#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) -#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) -/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is - * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. - * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. - * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. - */ -#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CTLSTAT */ -#define DMA_CHANNEL_CTLSTAT_COUNT (23U) - -/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ -/*! @{ */ - -#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) -#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) -/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor - * is valid and can potentially be acted upon, if all other activation criteria are fulfilled. - * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. - * 0b1..Valid. The current channel descriptor is considered valid. - */ -#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) - -#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) -#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) -/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current - * descriptor is exhausted. Reloading allows ping-pong and linked transfers. - * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. - * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) - -#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) -#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) -/*! SWTRIG - Software Trigger. - * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by - * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. - * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not - * be used with level triggering when TRIGBURST = 0. - */ -#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) - -#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) -#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) -/*! CLRTRIG - Clear Trigger. - * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. - * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted - */ -#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) - -#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) -#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) -/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between - * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By - * convention, interrupt A may be used when only one interrupt flag is needed. - * 0b0..No effect. - * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) - -#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) -#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) -/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between - * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By - * convention, interrupt A may be used when only one interrupt flag is needed. - * 0b0..No effect. - * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) - -#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) -#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) -/*! WIDTH - Transfer width used for this DMA channel. - * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). - * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). - * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). - * 0b11..Reserved. Reserved setting, do not use. - */ -#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) - -#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) -#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) -/*! SRCINC - Determines whether the source address is incremented for each DMA transfer. - * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. - * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is - * the usual case when the source is memory. - * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. - * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. - */ -#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) - -#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) -#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) -/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. - * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when - * the destination is a peripheral device. - * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. - * This is the usual case when the destination is memory. - * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. - * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. - */ -#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) - -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) -/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes - * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller - * uses this bit field during transfer to count down. Hence, it cannot be used by software to read - * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 - * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of - * 1,024 transfers will be performed. - */ -#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_XFERCFG */ -#define DMA_CHANNEL_XFERCFG_COUNT (23U) - - -/*! - * @} - */ /* end of group DMA_Register_Masks */ - - -/* DMA - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral DMA0 base address */ - #define DMA0_BASE (0x50082000u) - /** Peripheral DMA0 base address */ - #define DMA0_BASE_NS (0x40082000u) - /** Peripheral DMA0 base pointer */ - #define DMA0 ((DMA_Type *)DMA0_BASE) - /** Peripheral DMA0 base pointer */ - #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) - /** Peripheral DMA1 base address */ - #define DMA1_BASE (0x500A7000u) - /** Peripheral DMA1 base address */ - #define DMA1_BASE_NS (0x400A7000u) - /** Peripheral DMA1 base pointer */ - #define DMA1 ((DMA_Type *)DMA1_BASE) - /** Peripheral DMA1 base pointer */ - #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS { DMA0, DMA1 } - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } -#else - /** Peripheral DMA0 base address */ - #define DMA0_BASE (0x40082000u) - /** Peripheral DMA0 base pointer */ - #define DMA0 ((DMA_Type *)DMA0_BASE) - /** Peripheral DMA1 base address */ - #define DMA1_BASE (0x400A7000u) - /** Peripheral DMA1 base pointer */ - #define DMA1 ((DMA_Type *)DMA1_BASE) - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS { DMA0, DMA1 } -#endif -/** Interrupt vectors for the DMA peripheral type */ -#define DMA_IRQS { DMA0_IRQn, DMA1_IRQn } - -/*! - * @} - */ /* end of group DMA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer - * @{ - */ - -/** FLASH - Register Layout Typedef */ -typedef struct { - __O uint32_t CMD; /**< command register, offset: 0x0 */ - __O uint32_t EVENT; /**< event register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */ - __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */ - uint8_t RESERVED_1[104]; - __IO uint32_t DATAW[4]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_2[3912]; - __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */ - __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */ - __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ - __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ - __O uint32_t INT_CLR_STATUS; /**< Clear interrupt status bits, offset: 0xFE8 */ - __O uint32_t INT_SET_STATUS; /**< Set interrupt status bits, offset: 0xFEC */ - uint8_t RESERVED_3[12]; - __I uint32_t MODULE_ID; /**< Controller+Memory module identification, offset: 0xFFC */ -} FLASH_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_Register_Masks FLASH Register Masks - * @{ - */ - -/*! @name CMD - command register */ -/*! @{ */ - -#define FLASH_CMD_CMD_MASK (0xFFFFFFFFU) -#define FLASH_CMD_CMD_SHIFT (0U) -/*! CMD - command register. - */ -#define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK) -/*! @} */ - -/*! @name EVENT - event register */ -/*! @{ */ - -#define FLASH_EVENT_RST_MASK (0x1U) -#define FLASH_EVENT_RST_SHIFT (0U) -/*! RST - When bit is set, the controller and flash are reset. - */ -#define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK) - -#define FLASH_EVENT_WAKEUP_MASK (0x2U) -#define FLASH_EVENT_WAKEUP_SHIFT (1U) -/*! WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active. - */ -#define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK) - -#define FLASH_EVENT_ABORT_MASK (0x4U) -#define FLASH_EVENT_ABORT_SHIFT (2U) -/*! ABORT - When bit is set, a running program/erase command is aborted. - */ -#define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK) -/*! @} */ - -/*! @name STARTA - start (or only) address for next flash command */ -/*! @{ */ - -#define FLASH_STARTA_STARTA_MASK (0x3FFFFU) -#define FLASH_STARTA_STARTA_SHIFT (0U) -/*! STARTA - Address / Start address for commands that take an address (range) as a parameter. - */ -#define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK) -/*! @} */ - -/*! @name STOPA - end address for next flash command, if command operates on address ranges */ -/*! @{ */ - -#define FLASH_STOPA_STOPA_MASK (0x3FFFFU) -#define FLASH_STOPA_STOPA_SHIFT (0U) -/*! STOPA - Stop address for commands that take an address range as a parameter (the word specified - * by STOPA is included in the address range). - */ -#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK) -/*! @} */ - -/*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */ -/*! @{ */ - -#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU) -#define FLASH_DATAW_DATAW_SHIFT (0U) -#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK) -/*! @} */ - -/* The count of FLASH_DATAW */ -#define FLASH_DATAW_COUNT (4U) - -/*! @name INT_CLR_ENABLE - Clear interrupt enable bits */ -/*! @{ */ - -#define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U) -#define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U) -/*! FAIL - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - */ -#define FLASH_INT_CLR_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK) - -#define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U) -#define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U) -/*! ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - */ -#define FLASH_INT_CLR_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK) - -#define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U) -#define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U) -/*! DONE - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - */ -#define FLASH_INT_CLR_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK) - -#define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U) -#define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - */ -#define FLASH_INT_CLR_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_SET_ENABLE - Set interrupt enable bits */ -/*! @{ */ - -#define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U) -#define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U) -/*! FAIL - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - */ -#define FLASH_INT_SET_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK) - -#define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U) -#define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U) -/*! ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - */ -#define FLASH_INT_SET_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK) - -#define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U) -#define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U) -/*! DONE - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - */ -#define FLASH_INT_SET_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK) - -#define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U) -#define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - */ -#define FLASH_INT_SET_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_STATUS - Interrupt status bits */ -/*! @{ */ - -#define FLASH_INT_STATUS_FAIL_MASK (0x1U) -#define FLASH_INT_STATUS_FAIL_SHIFT (0U) -/*! FAIL - This status bit is set if execution of a (legal) command failed. - */ -#define FLASH_INT_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK) - -#define FLASH_INT_STATUS_ERR_MASK (0x2U) -#define FLASH_INT_STATUS_ERR_SHIFT (1U) -/*! ERR - This status bit is set if execution of an illegal command is detected. - */ -#define FLASH_INT_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK) - -#define FLASH_INT_STATUS_DONE_MASK (0x4U) -#define FLASH_INT_STATUS_DONE_SHIFT (2U) -/*! DONE - This status bit is set at the end of command execution. - */ -#define FLASH_INT_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK) - -#define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U) -#define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested - * read, or a speculative read, or reads performed by a controller command), a correctable or - * uncorrectable error is detected by ECC decoding logic. - */ -#define FLASH_INT_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_ENABLE - Interrupt enable bits */ -/*! @{ */ - -#define FLASH_INT_ENABLE_FAIL_MASK (0x1U) -#define FLASH_INT_ENABLE_FAIL_SHIFT (0U) -/*! FAIL - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - */ -#define FLASH_INT_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK) - -#define FLASH_INT_ENABLE_ERR_MASK (0x2U) -#define FLASH_INT_ENABLE_ERR_SHIFT (1U) -/*! ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - */ -#define FLASH_INT_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK) - -#define FLASH_INT_ENABLE_DONE_MASK (0x4U) -#define FLASH_INT_ENABLE_DONE_SHIFT (2U) -/*! DONE - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - */ -#define FLASH_INT_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK) - -#define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U) -#define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - */ -#define FLASH_INT_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_CLR_STATUS - Clear interrupt status bits */ -/*! @{ */ - -#define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U) -#define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U) -/*! FAIL - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - */ -#define FLASH_INT_CLR_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK) - -#define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U) -#define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U) -/*! ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - */ -#define FLASH_INT_CLR_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK) - -#define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U) -#define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U) -/*! DONE - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - */ -#define FLASH_INT_CLR_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK) - -#define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U) -#define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - */ -#define FLASH_INT_CLR_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_SET_STATUS - Set interrupt status bits */ -/*! @{ */ - -#define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U) -#define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U) -/*! FAIL - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - */ -#define FLASH_INT_SET_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK) - -#define FLASH_INT_SET_STATUS_ERR_MASK (0x2U) -#define FLASH_INT_SET_STATUS_ERR_SHIFT (1U) -/*! ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - */ -#define FLASH_INT_SET_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK) - -#define FLASH_INT_SET_STATUS_DONE_MASK (0x4U) -#define FLASH_INT_SET_STATUS_DONE_SHIFT (2U) -/*! DONE - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - */ -#define FLASH_INT_SET_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK) - -#define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U) -#define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - */ -#define FLASH_INT_SET_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK) -/*! @} */ - -/*! @name MODULE_ID - Controller+Memory module identification */ -/*! @{ */ - -#define FLASH_MODULE_ID_APERTURE_MASK (0xFFU) -#define FLASH_MODULE_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture i. - */ -#define FLASH_MODULE_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK) - -#define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U) -#define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision i. - */ -#define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK) - -#define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U) -#define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision i. - */ -#define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK) - -#define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U) -#define FLASH_MODULE_ID_ID_SHIFT (16U) -/*! ID - Identifier. - */ -#define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLASH_Register_Masks */ - - -/* FLASH - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH base address */ - #define FLASH_BASE (0x50034000u) - /** Peripheral FLASH base address */ - #define FLASH_BASE_NS (0x40034000u) - /** Peripheral FLASH base pointer */ - #define FLASH ((FLASH_Type *)FLASH_BASE) - /** Peripheral FLASH base pointer */ - #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS) - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS { FLASH_BASE } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS { FLASH } - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS_NS { FLASH_NS } -#else - /** Peripheral FLASH base address */ - #define FLASH_BASE (0x40034000u) - /** Peripheral FLASH base pointer */ - #define FLASH ((FLASH_Type *)FLASH_BASE) - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS { FLASH_BASE } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS { FLASH } -#endif - -/*! - * @} - */ /* end of group FLASH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_CFPA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CFPA_Peripheral_Access_Layer FLASH_CFPA Peripheral Access Layer - * @{ - */ - -/** FLASH_CFPA - Register Layout Typedef */ -typedef struct { - __IO uint32_t HEADER; /**< , offset: 0x0 */ - __IO uint32_t VERSION; /**< , offset: 0x4 */ - __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */ - __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */ - __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */ - uint8_t RESERVED_0[4]; - __IO uint32_t ROTKH_REVOKE; /**< , offset: 0x18 */ - __IO uint32_t VENDOR_USAGE; /**< , offset: 0x1C */ - __IO uint32_t DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */ - __IO uint32_t DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */ - __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */ - __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */ - union { /* offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< , array offset: 0x30, array step: 0x4 */ - struct { /* offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< , offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< , offset: 0x34 */ - __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< , array offset: 0x38, array step: 0x4 */ - } PRINCE_REGION0_IV_CODE_CORE; - }; - union { /* offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< , array offset: 0x68, array step: 0x4 */ - struct { /* offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< , offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< , offset: 0x6C */ - __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< , array offset: 0x70, array step: 0x4 */ - } PRINCE_REGION1_IV_CODE_CORE; - }; - union { /* offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< , array offset: 0xA0, array step: 0x4 */ - struct { /* offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< , offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< , offset: 0xA4 */ - __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< , array offset: 0xA8, array step: 0x4 */ - } PRINCE_REGION2_IV_CODE_CORE; - }; - uint8_t RESERVED_1[40]; - __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ - __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ -} FLASH_CFPA_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_CFPA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CFPA_Register_Masks FLASH_CFPA Register Masks - * @{ - */ - -/*! @name HEADER - */ -/*! @{ */ - -#define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_HEADER_FIELD_SHIFT (0U) -#define FLASH_CFPA_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK) -/*! @} */ - -/*! @name VERSION - */ -/*! @{ */ - -#define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_VERSION_FIELD_SHIFT (0U) -#define FLASH_CFPA_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK) -/*! @} */ - -/*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */ -/*! @{ */ - -#define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U) -#define FLASH_CFPA_S_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK) -/*! @} */ - -/*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */ -/*! @{ */ - -#define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U) -#define FLASH_CFPA_NS_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK) -/*! @} */ - -/*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */ -/*! @{ */ - -#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U) -#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK) -/*! @} */ - -/*! @name ROTKH_REVOKE - */ -/*! @{ */ - -#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U) -/*! RoTK0_EN - RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK) - -#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U) -/*! RoTK1_EN - RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK) - -#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U) -/*! RoTK2_EN - RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK) - -#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK (0xC0U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT (6U) -/*! RoTK3_EN - RoT Key 3 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK) -/*! @} */ - -/*! @name VENDOR_USAGE - */ -/*! @{ */ - -#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU) -#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U) -/*! DBG_VENDOR_USAGE - DBG_VENDOR_USAGE. - */ -#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK) - -#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ -/*! @{ */ - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) -/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) -/*! FA_CMD_EN - FA Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) -/*! ME_CMD_EN - Flash Mass Erase Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) -/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) -/*! UUID_CHECK - Enforce UUID match during Debug authentication. - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ -/*! @{ */ - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) -/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) -/*! FA_CMD_EN - FA Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) -/*! ME_CMD_EN - Flash Mass Erase Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) -/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */ -/*! @{ */ - -#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK) -/*! @} */ - -/*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */ -/*! @{ */ - -#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U) -#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_IV_CODE - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */ -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U) - -/*! @name PRINCE_REGION0_IV_HEADER0 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_IV_HEADER1 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK) - -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK) - -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_IV_BODY - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */ -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U) - -/*! @name PRINCE_REGION1_IV_CODE - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */ -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U) - -/*! @name PRINCE_REGION1_IV_HEADER0 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_IV_HEADER1 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK) - -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK) - -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_IV_BODY - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */ -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U) - -/*! @name PRINCE_REGION2_IV_CODE - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */ -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U) - -/*! @name PRINCE_REGION2_IV_HEADER0 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_IV_HEADER1 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK) - -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK) - -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_IV_BODY - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION2_IV_BODY */ -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_COUNT (12U) - -/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ -/*! @{ */ - -#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) -#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_CUSTOMER_DEFINED */ -#define FLASH_CFPA_CUSTOMER_DEFINED_COUNT (56U) - -/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ -/*! @{ */ - -#define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U) -#define FLASH_CFPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_SHA256_DIGEST */ -#define FLASH_CFPA_SHA256_DIGEST_COUNT (8U) - - -/*! - * @} - */ /* end of group FLASH_CFPA_Register_Masks */ - - -/* FLASH_CFPA - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH_CFPA0 base address */ - #define FLASH_CFPA0_BASE (0x1009E000u) - /** Peripheral FLASH_CFPA0 base address */ - #define FLASH_CFPA0_BASE_NS (0x9E000u) - /** Peripheral FLASH_CFPA0 base pointer */ - #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) - /** Peripheral FLASH_CFPA0 base pointer */ - #define FLASH_CFPA0_NS ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS) - /** Peripheral FLASH_CFPA1 base address */ - #define FLASH_CFPA1_BASE (0x1009E200u) - /** Peripheral FLASH_CFPA1 base address */ - #define FLASH_CFPA1_BASE_NS (0x9E200u) - /** Peripheral FLASH_CFPA1 base pointer */ - #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) - /** Peripheral FLASH_CFPA1 base pointer */ - #define FLASH_CFPA1_NS ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS) - /** Peripheral FLASH_CFPA_SCRATCH base address */ - #define FLASH_CFPA_SCRATCH_BASE (0x1009DE00u) - /** Peripheral FLASH_CFPA_SCRATCH base address */ - #define FLASH_CFPA_SCRATCH_BASE_NS (0x9DE00u) - /** Peripheral FLASH_CFPA_SCRATCH base pointer */ - #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) - /** Peripheral FLASH_CFPA_SCRATCH base pointer */ - #define FLASH_CFPA_SCRATCH_NS ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS) - /** Array initializer of FLASH_CFPA peripheral base addresses */ - #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } - /** Array initializer of FLASH_CFPA peripheral base pointers */ - #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } - /** Array initializer of FLASH_CFPA peripheral base addresses */ - #define FLASH_CFPA_BASE_ADDRS_NS { FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS } - /** Array initializer of FLASH_CFPA peripheral base pointers */ - #define FLASH_CFPA_BASE_PTRS_NS { FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS } -#else - /** Peripheral FLASH_CFPA0 base address */ - #define FLASH_CFPA0_BASE (0x9E000u) - /** Peripheral FLASH_CFPA0 base pointer */ - #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) - /** Peripheral FLASH_CFPA1 base address */ - #define FLASH_CFPA1_BASE (0x9E200u) - /** Peripheral FLASH_CFPA1 base pointer */ - #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) - /** Peripheral FLASH_CFPA_SCRATCH base address */ - #define FLASH_CFPA_SCRATCH_BASE (0x9DE00u) - /** Peripheral FLASH_CFPA_SCRATCH base pointer */ - #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) - /** Array initializer of FLASH_CFPA peripheral base addresses */ - #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } - /** Array initializer of FLASH_CFPA peripheral base pointers */ - #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } -#endif - -/*! - * @} - */ /* end of group FLASH_CFPA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_CMPA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CMPA_Peripheral_Access_Layer FLASH_CMPA Peripheral Access Layer - * @{ - */ - -/** FLASH_CMPA - Register Layout Typedef */ -typedef struct { - __IO uint32_t BOOT_CFG; /**< , offset: 0x0 */ - __IO uint32_t SPI_FLASH_CFG; /**< , offset: 0x4 */ - __IO uint32_t USB_ID; /**< , offset: 0x8 */ - __IO uint32_t SDIO_CFG; /**< , offset: 0xC */ - __IO uint32_t CC_SOCU_PIN; /**< , offset: 0x10 */ - __IO uint32_t CC_SOCU_DFLT; /**< , offset: 0x14 */ - __IO uint32_t VENDOR_USAGE; /**< , offset: 0x18 */ - __IO uint32_t SECURE_BOOT_CFG; /**< Secure boot configuration flags., offset: 0x1C */ - __IO uint32_t PRINCE_BASE_ADDR; /**< , offset: 0x20 */ - __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */ - __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */ - __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */ - __IO uint32_t XTAL_32KHZ_CAPABANK_TRIM; /**< Xtal 32kHz capabank triming., offset: 0x30 */ - __IO uint32_t XTAL_16MHZ_CAPABANK_TRIM; /**< Xtal 16MHz capabank triming., offset: 0x34 */ - uint8_t RESERVED_0[24]; - __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */ - uint8_t RESERVED_1[144]; - __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ - __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ -} FLASH_CMPA_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_CMPA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CMPA_Register_Masks FLASH_CMPA Register Masks - * @{ - */ - -/*! @name BOOT_CFG - */ -/*! @{ */ - -#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U) -#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U) -/*! DEFAULT_ISP_MODE - Default ISP mode: - * 0b000..Auto ISP - * 0b001..USB_HID_ISP - * 0b010..UART ISP - * 0b011..SPI Slave ISP - * 0b100..I2C Slave ISP - * 0b111..Disable ISP fall through - */ -#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK) - -#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U) -#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U) -/*! BOOT_SPEED - Core clock: - * 0b00..Defined by NMPA.SYSTEM_SPEED_CODE - * 0b01..96MHz FRO - * 0b10..48MHz FRO - */ -#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK) - -#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U) -#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U) -/*! BOOT_FAILURE_PIN - GPIO port and pin number to use for indicating failure reason. The toggle - * rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO - * pin - */ -#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK) -/*! @} */ - -/*! @name SPI_FLASH_CFG - */ -/*! @{ */ - -#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK (0x1FU) -#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT (0U) -/*! SPI_RECOVERY_BOOT_EN - SPI flash recovery boot is enabled, if non-zero value is written to this field. - */ -#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK) -/*! @} */ - -/*! @name USB_ID - */ -/*! @{ */ - -#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU) -#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U) -#define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK) - -#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U) -#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U) -#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK) -/*! @} */ - -/*! @name SDIO_CFG - */ -/*! @{ */ - -#define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U) -#define FLASH_CMPA_SDIO_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK) -/*! @} */ - -/*! @name CC_SOCU_PIN - */ -/*! @{ */ - -#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK (0x1U) -#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK (0x2U) -#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) -#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK (0x8U) -#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK (0x10U) -#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) -#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) -/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) -#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) -/*! FA_CMD_EN - FA Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) -#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) -/*! ME_CMD_EN - Flash Mass Erase Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) -#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) -/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) -#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) -/*! UUID_CHECK - Enforce UUID match during Debug authentication. - */ -#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name CC_SOCU_DFLT - */ -/*! @{ */ - -#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK (0x1U) -#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK (0x2U) -#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) -#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) -#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK (0x10U) -#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) -#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) -/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) -#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) -/*! FA_CMD_EN - FA Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) -#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) -/*! ME_CMD_EN - Flash Mass Erase Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) -#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) -/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name VENDOR_USAGE - */ -/*! @{ */ - -#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK (0xFFFF0000U) -#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT (16U) -/*! VENDOR_USAGE - Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area. - */ -#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK) -/*! @} */ - -/*! @name SECURE_BOOT_CFG - Secure boot configuration flags. */ -/*! @{ */ - -#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U) -#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U) -/*! RSA4K - Use RSA4096 keys only. - * 0b00..Allow RSA2048 and higher - * 0b01..RSA4096 only - * 0b10..RSA4096 only - * 0b11..RSA4096 only - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK (0xCU) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT (2U) -/*! DICE_INC_NXP_CFG - Include NXP area in DICE computation. - * 0b00..not included - * 0b01..included - * 0b10..included - * 0b11..included - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U) -/*! DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. - * 0b00..not included - * 0b01..included - * 0b10..included - * 0b11..included - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U) -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U) -/*! SKIP_DICE - Skip DICE computation - * 0b00..Enable DICE - * 0b01..Disable DICE - * 0b10..Disable DICE - * 0b11..Disable DICE - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U) -#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U) -/*! TZM_IMAGE_TYPE - TrustZone-M mode - * 0b00..TZ-M image mode is taken from application image header - * 0b01..TZ-M disabled image, boots to non-secure mode - * 0b10..TZ-M enabled image, boots to secure mode - * 0b11..TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U) -/*! BLOCK_SET_KEY - Block PUF key code generation - * 0b00..Allow PUF Key Code generation - * 0b01..Disable PUF Key Code generation - * 0b10..Disable PUF Key Code generation - * 0b11..Disable PUF Key Code generation - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U) -/*! BLOCK_ENROLL - Block PUF enrollement - * 0b00..Allow PUF enroll operation - * 0b01..Disable PUF enroll operation - * 0b10..Disable PUF enroll operation - * 0b11..Disable PUF enroll operation - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK (0xC000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT (14U) -/*! DICE_INC_SEC_EPOCH - Include security EPOCH in DICE - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U) -/*! SEC_BOOT_EN - Secure boot enable - * 0b00..Plain image (internal flash with or without CRC) - * 0b01..Boot signed images. (internal flash, RSA signed) - * 0b10..Boot signed images. (internal flash, RSA signed) - * 0b11..Boot signed images. (internal flash, RSA signed) - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK) -/*! @} */ - -/*! @name PRINCE_BASE_ADDR - */ -/*! @{ */ - -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U) -/*! ADDR0_PRG - Programmable portion of the base address of region 0 - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U) -/*! ADDR1_PRG - Programmable portion of the base address of region 1 - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U) -/*! ADDR2_PRG - Programmable portion of the base address of region 2 - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0xC0000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (18U) -/*! LOCK_REG0 - Lock PRINCE region0 settings - * 0b00..Region is not locked - * 0b01..Region is locked - * 0b10..Region is locked - * 0b11..Region is locked - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0x300000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (20U) -/*! LOCK_REG1 - Lock PRINCE region1 settings - * 0b00..Region is not locked - * 0b01..Region is locked - * 0b10..Region is locked - * 0b11..Region is locked - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U) -/*! REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased together - * 0b00..Region is disabled - * 0b01..Region is enabled - * 0b10..Region is enabled - * 0b11..Region is enabled - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U) -/*! REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased together - * 0b00..Region is disabled - * 0b01..Region is enabled - * 0b10..Region is enabled - * 0b11..Region is enabled - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U) -/*! REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased together - * 0b00..Region is disabled - * 0b01..Region is enabled - * 0b10..Region is enabled - * 0b11..Region is enabled - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK) -/*! @} */ - -/*! @name PRINCE_SR_0 - Region 0, sub-region enable */ -/*! @{ */ - -#define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U) -#define FLASH_CMPA_PRINCE_SR_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_SR_1 - Region 1, sub-region enable */ -/*! @{ */ - -#define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U) -#define FLASH_CMPA_PRINCE_SR_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_SR_2 - Region 2, sub-region enable */ -/*! @{ */ - -#define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U) -#define FLASH_CMPA_PRINCE_SR_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK) -/*! @} */ - -/*! @name XTAL_32KHZ_CAPABANK_TRIM - Xtal 32kHz capabank triming. */ -/*! @{ */ - -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) -/*! TRIM_VALID - XTAL 32kHz capa bank trimmings - * 0b0..Capa Bank trimmings not valid. Default trimmings value are used - * 0b1..Capa Bank trimmings valid - */ -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK) - -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) -/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) - -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) -/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) - -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) -/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) -/*! @} */ - -/*! @name XTAL_16MHZ_CAPABANK_TRIM - Xtal 16MHz capabank triming. */ -/*! @{ */ - -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) -/*! TRIM_VALID - XTAL 16MHz capa bank trimmings - * 0b0..Capa Bank trimmings not valid. Default trimmings value are used - * 0b1..Capa Bank trimmings valid - */ -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK) - -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) -/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) - -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) -/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) - -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) -/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) -/*! @} */ - -/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0] */ -/*! @{ */ - -#define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U) -#define FLASH_CMPA_ROTKH_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CMPA_ROTKH */ -#define FLASH_CMPA_ROTKH_COUNT (8U) - -/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ -/*! @{ */ - -#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) -#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CMPA_CUSTOMER_DEFINED */ -#define FLASH_CMPA_CUSTOMER_DEFINED_COUNT (56U) - -/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ -/*! @{ */ - -#define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U) -#define FLASH_CMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CMPA_SHA256_DIGEST */ -#define FLASH_CMPA_SHA256_DIGEST_COUNT (8U) - - -/*! - * @} - */ /* end of group FLASH_CMPA_Register_Masks */ - - -/* FLASH_CMPA - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH_CMPA base address */ - #define FLASH_CMPA_BASE (0x1009E400u) - /** Peripheral FLASH_CMPA base address */ - #define FLASH_CMPA_BASE_NS (0x9E400u) - /** Peripheral FLASH_CMPA base pointer */ - #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) - /** Peripheral FLASH_CMPA base pointer */ - #define FLASH_CMPA_NS ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS) - /** Array initializer of FLASH_CMPA peripheral base addresses */ - #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } - /** Array initializer of FLASH_CMPA peripheral base pointers */ - #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } - /** Array initializer of FLASH_CMPA peripheral base addresses */ - #define FLASH_CMPA_BASE_ADDRS_NS { FLASH_CMPA_BASE_NS } - /** Array initializer of FLASH_CMPA peripheral base pointers */ - #define FLASH_CMPA_BASE_PTRS_NS { FLASH_CMPA_NS } -#else - /** Peripheral FLASH_CMPA base address */ - #define FLASH_CMPA_BASE (0x9E400u) - /** Peripheral FLASH_CMPA base pointer */ - #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) - /** Array initializer of FLASH_CMPA peripheral base addresses */ - #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } - /** Array initializer of FLASH_CMPA peripheral base pointers */ - #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } -#endif - -/*! - * @} - */ /* end of group FLASH_CMPA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_KEY_STORE Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_KEY_STORE_Peripheral_Access_Layer FLASH_KEY_STORE Peripheral Access Layer - * @{ - */ - -/** FLASH_KEY_STORE - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0 */ - __IO uint32_t HEADER; /**< Valid Key Sore Header : 0x95959595, offset: 0x0 */ - __IO uint32_t PUF_DISCHARGE_TIME_IN_MS; /**< puf discharge time in ms., offset: 0x4 */ - } KEY_STORE_HEADER; - __IO uint32_t ACTIVATION_CODE[298]; /**< ., array offset: 0x8, array step: 0x4 */ - union { /* offset: 0x4B0 */ - __IO uint32_t SBKEY_KEY_CODE[14]; /**< ., array offset: 0x4B0, array step: 0x4 */ - struct { /* offset: 0x4B0 */ - __IO uint32_t SBKEY_HEADER0; /**< ., offset: 0x4B0 */ - __IO uint32_t SBKEY_HEADER1; /**< ., offset: 0x4B4 */ - __IO uint32_t SBKEY_BODY[12]; /**< ., array offset: 0x4B8, array step: 0x4 */ - } SBKEY_KEY_CODE_CORE; - }; - union { /* offset: 0x4E8 */ - __IO uint32_t USER_KEK_KEY_CODE[14]; /**< ., array offset: 0x4E8, array step: 0x4 */ - struct { /* offset: 0x4E8 */ - __IO uint32_t USER_KEK_HEADER0; /**< ., offset: 0x4E8 */ - __IO uint32_t USER_KEK_HEADER1; /**< ., offset: 0x4EC */ - __IO uint32_t USER_KEK_BODY[12]; /**< ., array offset: 0x4F0, array step: 0x4 */ - } USER_KEK_KEY_CODE_CORE; - }; - union { /* offset: 0x520 */ - __IO uint32_t UDS_KEY_CODE[14]; /**< ., array offset: 0x520, array step: 0x4 */ - struct { /* offset: 0x520 */ - __IO uint32_t UDS_HEADER0; /**< ., offset: 0x520 */ - __IO uint32_t UDS_HEADER1; /**< ., offset: 0x524 */ - __IO uint32_t UDS_BODY[12]; /**< ., array offset: 0x528, array step: 0x4 */ - } UDS_KEY_CODE_CORE; - }; - union { /* offset: 0x558 */ - __IO uint32_t PRINCE_REGION0_KEY_CODE[14]; /**< ., array offset: 0x558, array step: 0x4 */ - struct { /* offset: 0x558 */ - __IO uint32_t PRINCE_REGION0_HEADER0; /**< ., offset: 0x558 */ - __IO uint32_t PRINCE_REGION0_HEADER1; /**< ., offset: 0x55C */ - __IO uint32_t PRINCE_REGION0_BODY[12]; /**< ., array offset: 0x560, array step: 0x4 */ - } PRINCE_REGION0_KEY_CODE_CORE; - }; - union { /* offset: 0x590 */ - __IO uint32_t PRINCE_REGION1_KEY_CODE[14]; /**< ., array offset: 0x590, array step: 0x4 */ - struct { /* offset: 0x590 */ - __IO uint32_t PRINCE_REGION1_HEADER0; /**< ., offset: 0x590 */ - __IO uint32_t PRINCE_REGION1_HEADER1; /**< ., offset: 0x594 */ - __IO uint32_t PRINCE_REGION1_BODY[12]; /**< ., array offset: 0x598, array step: 0x4 */ - } PRINCE_REGION1_KEY_CODE_CORE; - }; - union { /* offset: 0x5C8 */ - __IO uint32_t PRINCE_REGION2_KEY_CODE[14]; /**< ., array offset: 0x5C8, array step: 0x4 */ - struct { /* offset: 0x5C8 */ - __IO uint32_t PRINCE_REGION2_HEADER0; /**< ., offset: 0x5C8 */ - __IO uint32_t PRINCE_REGION2_HEADER1; /**< ., offset: 0x5CC */ - __IO uint32_t PRINCE_REGION2_BODY[12]; /**< ., array offset: 0x5D0, array step: 0x4 */ - } PRINCE_REGION2_KEY_CODE_CORE; - }; -} FLASH_KEY_STORE_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_KEY_STORE Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_KEY_STORE_Register_Masks FLASH_KEY_STORE Register Masks - * @{ - */ - -/*! @name HEADER - Valid Key Sore Header : 0x95959595 */ -/*! @{ */ - -#define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK) -/*! @} */ - -/*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */ -/*! @{ */ - -#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK) -/*! @} */ - -/*! @name ACTIVATION_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_ACTIVATION_CODE */ -#define FLASH_KEY_STORE_ACTIVATION_CODE_COUNT (298U) - -/*! @name SBKEY_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_SBKEY_KEY_CODE */ -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_COUNT (14U) - -/*! @name SBKEY_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name SBKEY_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name SBKEY_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_SBKEY_BODY */ -#define FLASH_KEY_STORE_SBKEY_BODY_COUNT (12U) - -/*! @name USER_KEK_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_USER_KEK_KEY_CODE */ -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_COUNT (14U) - -/*! @name USER_KEK_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name USER_KEK_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name USER_KEK_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_USER_KEK_BODY */ -#define FLASH_KEY_STORE_USER_KEK_BODY_COUNT (12U) - -/*! @name UDS_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_UDS_KEY_CODE */ -#define FLASH_KEY_STORE_UDS_KEY_CODE_COUNT (14U) - -/*! @name UDS_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name UDS_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name UDS_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_UDS_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_UDS_BODY */ -#define FLASH_KEY_STORE_UDS_BODY_COUNT (12U) - -/*! @name PRINCE_REGION0_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE */ -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_COUNT (14U) - -/*! @name PRINCE_REGION0_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION0_BODY */ -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_COUNT (12U) - -/*! @name PRINCE_REGION1_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE */ -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_COUNT (14U) - -/*! @name PRINCE_REGION1_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION1_BODY */ -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_COUNT (12U) - -/*! @name PRINCE_REGION2_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE */ -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_COUNT (14U) - -/*! @name PRINCE_REGION2_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION2_BODY */ -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_COUNT (12U) - - -/*! - * @} - */ /* end of group FLASH_KEY_STORE_Register_Masks */ - - -/* FLASH_KEY_STORE - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH_KEY_STORE base address */ - #define FLASH_KEY_STORE_BASE (0x1009E600u) - /** Peripheral FLASH_KEY_STORE base address */ - #define FLASH_KEY_STORE_BASE_NS (0x9E600u) - /** Peripheral FLASH_KEY_STORE base pointer */ - #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) - /** Peripheral FLASH_KEY_STORE base pointer */ - #define FLASH_KEY_STORE_NS ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS) - /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ - #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } - /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ - #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } - /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ - #define FLASH_KEY_STORE_BASE_ADDRS_NS { FLASH_KEY_STORE_BASE_NS } - /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ - #define FLASH_KEY_STORE_BASE_PTRS_NS { FLASH_KEY_STORE_NS } -#else - /** Peripheral FLASH_KEY_STORE base address */ - #define FLASH_KEY_STORE_BASE (0x9E600u) - /** Peripheral FLASH_KEY_STORE base pointer */ - #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) - /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ - #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } - /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ - #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } -#endif - -/*! - * @} - */ /* end of group FLASH_KEY_STORE_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer - * @{ - */ - -/** FLEXCOMM - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4088]; - __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ - __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ -} FLEXCOMM_Type; - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks - * @{ - */ - -/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ -/*! @{ */ - -#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) -#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) -/*! PERSEL - Peripheral Select. This field is writable by software. - * 0b000..No peripheral selected. - * 0b001..USART function selected. - * 0b010..SPI function selected. - * 0b011..I2C function selected. - * 0b100..I2S transmit function selected. - * 0b101..I2S receive function selected. - * 0b110..Reserved - * 0b111..Reserved - */ -#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) - -#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) -#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) -/*! LOCK - Lock the peripheral select. This field is writable by software. - * 0b0..Peripheral select can be changed by software. - * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. - */ -#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) - -#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) -#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) -/*! USARTPRESENT - USART present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the USART function. - * 0b1..This Flexcomm includes the USART function. - */ -#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) - -#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) -#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) -/*! SPIPRESENT - SPI present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the SPI function. - * 0b1..This Flexcomm includes the SPI function. - */ -#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) - -#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) -#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) -/*! I2CPRESENT - I2C present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the I2C function. - * 0b1..This Flexcomm includes the I2C function. - */ -#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) - -#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) -#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) -/*! I2SPRESENT - I 2S present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the I2S function. - * 0b1..This Flexcomm includes the I2S function. - */ -#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) - -#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) -#define FLEXCOMM_PSELID_ID_SHIFT (12U) -/*! ID - Flexcomm ID. - */ -#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) -/*! @} */ - -/*! @name PID - Peripheral identification register. */ -/*! @{ */ - -#define FLEXCOMM_PID_APERTURE_MASK (0xFFU) -#define FLEXCOMM_PID_APERTURE_SHIFT (0U) -/*! APERTURE - size aperture for the register port on the bus (APB or AHB). - */ -#define FLEXCOMM_PID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_APERTURE_SHIFT)) & FLEXCOMM_PID_APERTURE_MASK) - -#define FLEXCOMM_PID_MINOR_REV_MASK (0xF00U) -#define FLEXCOMM_PID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation. - */ -#define FLEXCOMM_PID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MINOR_REV_SHIFT)) & FLEXCOMM_PID_MINOR_REV_MASK) - -#define FLEXCOMM_PID_MAJOR_REV_MASK (0xF000U) -#define FLEXCOMM_PID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation. - */ -#define FLEXCOMM_PID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MAJOR_REV_SHIFT)) & FLEXCOMM_PID_MAJOR_REV_MASK) - -#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) -#define FLEXCOMM_PID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function. - */ -#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLEXCOMM_Register_Masks */ - - -/* FLEXCOMM - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE (0x50086000u) - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE_NS (0x40086000u) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE (0x50087000u) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE_NS (0x40087000u) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE (0x50088000u) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE_NS (0x40088000u) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE (0x50089000u) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE_NS (0x40089000u) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE (0x5008A000u) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE_NS (0x4008A000u) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE (0x50096000u) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE_NS (0x40096000u) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE (0x50097000u) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE_NS (0x40097000u) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE (0x50098000u) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE_NS (0x40098000u) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE (0x5009F000u) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE_NS (0x4009F000u) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS) - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS_NS { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS_NS { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS } -#else - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE (0x40086000u) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE (0x40087000u) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE (0x40088000u) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE (0x40089000u) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE (0x4008A000u) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE (0x40096000u) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE (0x40097000u) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE (0x40098000u) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE (0x4009F000u) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } -#endif -/** Interrupt vectors for the FLEXCOMM peripheral type */ -#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } - -/*! - * @} - */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer - * @{ - */ - -/** GINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ - uint8_t RESERVED_0[28]; - __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[24]; - __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ -} GINT_Type; - -/* ---------------------------------------------------------------------------- - -- GINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Register_Masks GINT Register Masks - * @{ - */ - -/*! @name CTRL - GPIO grouped interrupt control register */ -/*! @{ */ - -#define GINT_CTRL_INT_MASK (0x1U) -#define GINT_CTRL_INT_SHIFT (0U) -/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. - * 0b0..No request. No interrupt request is pending. - * 0b1..Request active. Interrupt request is active. - */ -#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) - -#define GINT_CTRL_COMB_MASK (0x2U) -#define GINT_CTRL_COMB_SHIFT (1U) -/*! COMB - Combine enabled inputs for group interrupt - * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). - * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). - */ -#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) - -#define GINT_CTRL_TRIG_MASK (0x4U) -#define GINT_CTRL_TRIG_SHIFT (2U) -/*! TRIG - Group interrupt trigger - * 0b0..Edge-triggered. - * 0b1..Level-triggered. - */ -#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) -/*! @} */ - -/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ -/*! @{ */ - -#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) -#define GINT_PORT_POL_POL_SHIFT (0U) -/*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n - * of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to - * the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin - * contributes to the group interrupt. - */ -#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) -/*! @} */ - -/* The count of GINT_PORT_POL */ -#define GINT_PORT_POL_COUNT (2U) - -/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ -/*! @{ */ - -#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) -#define GINT_PORT_ENA_ENA_SHIFT (0U) -/*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the - * port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is - * enabled and contributes to the grouped interrupt. - */ -#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) -/*! @} */ - -/* The count of GINT_PORT_ENA */ -#define GINT_PORT_ENA_COUNT (2U) - - -/*! - * @} - */ /* end of group GINT_Register_Masks */ - - -/* GINT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral GINT0 base address */ - #define GINT0_BASE (0x50002000u) - /** Peripheral GINT0 base address */ - #define GINT0_BASE_NS (0x40002000u) - /** Peripheral GINT0 base pointer */ - #define GINT0 ((GINT_Type *)GINT0_BASE) - /** Peripheral GINT0 base pointer */ - #define GINT0_NS ((GINT_Type *)GINT0_BASE_NS) - /** Peripheral GINT1 base address */ - #define GINT1_BASE (0x50003000u) - /** Peripheral GINT1 base address */ - #define GINT1_BASE_NS (0x40003000u) - /** Peripheral GINT1 base pointer */ - #define GINT1 ((GINT_Type *)GINT1_BASE) - /** Peripheral GINT1 base pointer */ - #define GINT1_NS ((GINT_Type *)GINT1_BASE_NS) - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS { GINT0, GINT1 } - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS_NS { GINT0_BASE_NS, GINT1_BASE_NS } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS_NS { GINT0_NS, GINT1_NS } -#else - /** Peripheral GINT0 base address */ - #define GINT0_BASE (0x40002000u) - /** Peripheral GINT0 base pointer */ - #define GINT0 ((GINT_Type *)GINT0_BASE) - /** Peripheral GINT1 base address */ - #define GINT1_BASE (0x40003000u) - /** Peripheral GINT1 base pointer */ - #define GINT1 ((GINT_Type *)GINT1_BASE) - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS { GINT0, GINT1 } -#endif -/** Interrupt vectors for the GINT peripheral type */ -#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } - -/*! - * @} - */ /* end of group GINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer - * @{ - */ - -/** GPIO - Register Layout Typedef */ -typedef struct { - __IO uint8_t B[2][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ - uint8_t RESERVED_0[4032]; - __IO uint32_t W[2][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ - uint8_t RESERVED_1[3840]; - __IO uint32_t DIR[2]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */ - uint8_t RESERVED_2[120]; - __IO uint32_t MASK[2]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */ - uint8_t RESERVED_3[120]; - __IO uint32_t PIN[2]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */ - uint8_t RESERVED_4[120]; - __IO uint32_t MPIN[2]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */ - uint8_t RESERVED_5[120]; - __IO uint32_t SET[2]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */ - uint8_t RESERVED_6[120]; - __O uint32_t CLR[2]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */ - uint8_t RESERVED_7[120]; - __O uint32_t NOT[2]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */ - uint8_t RESERVED_8[120]; - __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ - uint8_t RESERVED_9[120]; - __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ - uint8_t RESERVED_10[120]; - __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ -} GPIO_Type; - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/*! @name B - Byte pin registers for all port GPIO pins */ -/*! @{ */ - -#define GPIO_B_PBYTE_MASK (0x1U) -#define GPIO_B_PBYTE_SHIFT (0U) -/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, - * except that pins configured as analog I/O always read as 0. One register for each port pin. - * Supported pins depends on the specific device and package. Write: loads the pin's output bit. - * One register for each port pin. Supported pins depends on the specific device and package. - */ -#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) -/*! @} */ - -/* The count of GPIO_B */ -#define GPIO_B_COUNT (2U) - -/* The count of GPIO_B */ -#define GPIO_B_COUNT2 (32U) - -/*! @name W - Word pin registers for all port GPIO pins */ -/*! @{ */ - -#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) -#define GPIO_W_PWORD_SHIFT (0U) -/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is - * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be - * read. Writing any value other than 0 will set the output bit. One register for each port pin. - * Supported pins depends on the specific device and package. - */ -#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) -/*! @} */ - -/* The count of GPIO_W */ -#define GPIO_W_COUNT (2U) - -/* The count of GPIO_W */ -#define GPIO_W_COUNT2 (32U) - -/*! @name DIR - Direction registers for all port GPIO pins */ -/*! @{ */ - -#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) -#define GPIO_DIR_DIRP_SHIFT (0U) -/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported - * pins depends on the specific device and package. 0 = input. 1 = output. - */ -#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) -/*! @} */ - -/* The count of GPIO_DIR */ -#define GPIO_DIR_COUNT (2U) - -/*! @name MASK - Mask register for all port GPIO pins */ -/*! @{ */ - -#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) -#define GPIO_MASK_MASKP_SHIFT (0U) -/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = - * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = - * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit - * not affected. - */ -#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) -/*! @} */ - -/* The count of GPIO_MASK */ -#define GPIO_MASK_COUNT (2U) - -/*! @name PIN - Port pin register for all port GPIO pins */ -/*! @{ */ - -#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) -#define GPIO_PIN_PORT_SHIFT (0U) -/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported - * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. - * 1 = Read: pin is high; write: set output bit. - */ -#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) -/*! @} */ - -/* The count of GPIO_PIN */ -#define GPIO_PIN_COUNT (2U) - -/*! @name MPIN - Masked port register for all port GPIO pins */ -/*! @{ */ - -#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) -#define GPIO_MPIN_MPORTP_SHIFT (0U) -/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on - * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK - * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 - * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit - * if the corresponding bit in the MASK register is 0. - */ -#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) -/*! @} */ - -/* The count of GPIO_MPIN */ -#define GPIO_MPIN_COUNT (2U) - -/*! @name SET - Write: Set register for port. Read: output bits for port */ -/*! @{ */ - -#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) -#define GPIO_SET_SETP_SHIFT (0U) -/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on - * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output - * bit; write: set output bit. - */ -#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) -/*! @} */ - -/* The count of GPIO_SET */ -#define GPIO_SET_COUNT (2U) - -/*! @name CLR - Clear port for all port GPIO pins */ -/*! @{ */ - -#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) -#define GPIO_CLR_CLRP_SHIFT (0U) -/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the - * specific device and package. 0 = No operation. 1 = Clear output bit. - */ -#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) -/*! @} */ - -/* The count of GPIO_CLR */ -#define GPIO_CLR_COUNT (2U) - -/*! @name NOT - Toggle port for all port GPIO pins */ -/*! @{ */ - -#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) -#define GPIO_NOT_NOTP_SHIFT (0U) -/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the - * specific device and package. 0 = no operation. 1 = Toggle output bit. - */ -#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) -/*! @} */ - -/* The count of GPIO_NOT */ -#define GPIO_NOT_COUNT (2U) - -/*! @name DIRSET - Set pin direction bits for port */ -/*! @{ */ - -#define GPIO_DIRSET_DIRSETP_MASK (0xFFFFFFFFU) -#define GPIO_DIRSET_DIRSETP_SHIFT (0U) -/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on - * the specific device and package. 0 = No operation. 1 = Set direction bit. - */ -#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) -/*! @} */ - -/* The count of GPIO_DIRSET */ -#define GPIO_DIRSET_COUNT (2U) - -/*! @name DIRCLR - Clear pin direction bits for port */ -/*! @{ */ - -#define GPIO_DIRCLR_DIRCLRP_MASK (0xFFFFFFFFU) -#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) -/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on - * the specific device and package. 0 = No operation. 1 = Clear direction bit. - */ -#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) -/*! @} */ - -/* The count of GPIO_DIRCLR */ -#define GPIO_DIRCLR_COUNT (2U) - -/*! @name DIRNOT - Toggle pin direction bits for port */ -/*! @{ */ - -#define GPIO_DIRNOT_DIRNOTP_MASK (0xFFFFFFFFU) -#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) -/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends - * on the specific device and package. 0 = no operation. 1 = Toggle direction bit. - */ -#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) -/*! @} */ - -/* The count of GPIO_DIRNOT */ -#define GPIO_DIRNOT_COUNT (2U) - - -/*! - * @} - */ /* end of group GPIO_Register_Masks */ - - -/* GPIO - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral GPIO base address */ - #define GPIO_BASE (0x5008C000u) - /** Peripheral GPIO base address */ - #define GPIO_BASE_NS (0x4008C000u) - /** Peripheral GPIO base pointer */ - #define GPIO ((GPIO_Type *)GPIO_BASE) - /** Peripheral GPIO base pointer */ - #define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE (0x500A8000u) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE_NS (0x400A8000u) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS) - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO, SECGPIO } - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS_NS { GPIO_BASE_NS, SECGPIO_BASE_NS } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS_NS { GPIO_NS, SECGPIO_NS } -#else - /** Peripheral GPIO base address */ - #define GPIO_BASE (0x4008C000u) - /** Peripheral GPIO base pointer */ - #define GPIO ((GPIO_Type *)GPIO_BASE) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE (0x400A8000u) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO, SECGPIO } -#endif - -/*! - * @} - */ /* end of group GPIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- HASHCRYPT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup HASHCRYPT_Peripheral_Access_Layer HASHCRYPT Peripheral Access Layer - * @{ - */ - -/** HASHCRYPT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register to enable and operate Hash and Crypto, offset: 0x0 */ - __IO uint32_t STATUS; /**< Indicates status of Hash peripheral., offset: 0x4 */ - __IO uint32_t INTENSET; /**< Write 1 to enable interrupts; reads back with which are set., offset: 0x8 */ - __IO uint32_t INTENCLR; /**< Write 1 to clear interrupts., offset: 0xC */ - __IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available), offset: 0x10 */ - __IO uint32_t MEMADDR; /**< Address to start memory access from (if available)., offset: 0x14 */ - uint8_t RESERVED_0[8]; - __O uint32_t INDATA; /**< Input of 16 words at a time to load up buffer., offset: 0x20 */ - __O uint32_t ALIAS[7]; /**< , array offset: 0x24, array step: 0x4 */ - __I uint32_t DIGEST0[8]; /**< , array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_1[32]; - __IO uint32_t CRYPTCFG; /**< Crypto settings for AES and Salsa and ChaCha, offset: 0x80 */ - __I uint32_t CONFIG; /**< Returns the configuration of this block in this chip - indicates what services are available., offset: 0x84 */ - uint8_t RESERVED_2[4]; - __IO uint32_t LOCK; /**< Lock register allows locking to the current security level or unlocking by the lock holding level., offset: 0x8C */ - __O uint32_t MASK[4]; /**< , array offset: 0x90, array step: 0x4 */ -} HASHCRYPT_Type; - -/* ---------------------------------------------------------------------------- - -- HASHCRYPT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup HASHCRYPT_Register_Masks HASHCRYPT Register Masks - * @{ - */ - -/*! @name CTRL - Control register to enable and operate Hash and Crypto */ -/*! @{ */ - -#define HASHCRYPT_CTRL_MODE_MASK (0x7U) -#define HASHCRYPT_CTRL_MODE_SHIFT (0U) -/*! Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if - * specific modes beyond SHA1 and SHA2-256 are available. - * 0b000..Disabled - * 0b001..SHA1 is enabled - * 0b010..SHA2-256 is enabled - * 0b100..AES if available (see also CRYPTCFG register for more controls) - * 0b101..ICB-AES if available (see also CRYPTCFG register for more controls) - */ -#define HASHCRYPT_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK) - -#define HASHCRYPT_CTRL_NEW_HASH_MASK (0x10U) -#define HASHCRYPT_CTRL_NEW_HASH_SHIFT (4U) -/*! New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING - * Status bit will clear for a cycle during the initialization from New=1. - * 0b1..Starts a new Hash/Crypto and initializes the Digest/Result. - */ -#define HASHCRYPT_CTRL_NEW_HASH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK) - -#define HASHCRYPT_CTRL_DMA_I_MASK (0x100U) -#define HASHCRYPT_CTRL_DMA_I_SHIFT (8U) -/*! DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words - * and then will process the Hash. If Cryptographic, it will load as many words as needed, - * including key if not already loaded. It will then request again. Normal model is that the DMA - * interrupts the processor when its length expires. Note that if the processor will write the key and - * optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be - * expected to load those for the 1st block (when needed). - * 0b0..DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used. - * 0b1..DMA will push in the data. - */ -#define HASHCRYPT_CTRL_DMA_I(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK) - -#define HASHCRYPT_CTRL_DMA_O_MASK (0x200U) -#define HASHCRYPT_CTRL_DMA_O_SHIFT (9U) -/*! DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the - * DMA has to know to switch direction and the locations. This can be used for crypto uses. - * 0b0..DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. - */ -#define HASHCRYPT_CTRL_DMA_O(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK) - -#define HASHCRYPT_CTRL_HASHSWPB_MASK (0x1000U) -#define HASHCRYPT_CTRL_HASHSWPB_SHIFT (12U) -/*! HASHSWPB - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB - * is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For - * cryptographic swapping, see the CRYPTCFG register. - */ -#define HASHCRYPT_CTRL_HASHSWPB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK) -/*! @} */ - -/*! @name STATUS - Indicates status of Hash peripheral. */ -/*! @{ */ - -#define HASHCRYPT_STATUS_WAITING_MASK (0x1U) -#define HASHCRYPT_STATUS_WAITING_SHIFT (0U) -/*! WAITING - If 1, the block is waiting for more data to process. - * 0b0..Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set - * if IsLast is set nor will it set until at least 1 word is read of the output. - * 0b1..Waiting for data to be written in (16 words) - */ -#define HASHCRYPT_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK) - -#define HASHCRYPT_STATUS_DIGEST_MASK (0x2U) -#define HASHCRYPT_STATUS_DIGEST_SHIFT (1U) -/*! DIGEST - For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block - * already started. For Cryptographic uses, this will be set for each block processed, indicating - * OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared - * when any data is written, when New is written, for Cryptographic uses when the last word is read - * out, or when the block is disabled. - * 0b0..No Digest is ready - * 0b1..Digest is ready. Application may read it or may write more data - */ -#define HASHCRYPT_STATUS_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_SHIFT)) & HASHCRYPT_STATUS_DIGEST_MASK) - -#define HASHCRYPT_STATUS_ERROR_MASK (0x4U) -#define HASHCRYPT_STATUS_ERROR_SHIFT (2U) -/*! ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA - * was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT - * field will indicate which block it was on. - * 0b0..No error. - * 0b1..An error occurred since last cleared (written 1 to clear). - */ -#define HASHCRYPT_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK) - -#define HASHCRYPT_STATUS_NEEDKEY_MASK (0x10U) -#define HASHCRYPT_STATUS_NEEDKEY_SHIFT (4U) -/*! NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING) - * 0b0..No Key is needed and writes will not be treated as Key - * 0b1..Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. - */ -#define HASHCRYPT_STATUS_NEEDKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK) - -#define HASHCRYPT_STATUS_NEEDIV_MASK (0x20U) -#define HASHCRYPT_STATUS_NEEDIV_SHIFT (5U) -/*! NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING) - * 0b0..No IV/Nonce is needed, either because written already or because not needed. - * 0b1..IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. - */ -#define HASHCRYPT_STATUS_NEEDIV(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK) - -#define HASHCRYPT_STATUS_ICBIDX_MASK (0x3F0000U) -#define HASHCRYPT_STATUS_ICBIDX_SHIFT (16U) -/*! ICBIDX - If ICB-AES is selected, then reads as the ICB index count based on ICBSTRM (from - * CRYPTCFG). That is, if 3 bits of ICBSTRM, then this will count from 0 to 7 and then back to 0. On 0, - * it has to compute the full ICB, quicker when not 0. - */ -#define HASHCRYPT_STATUS_ICBIDX(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ICBIDX_SHIFT)) & HASHCRYPT_STATUS_ICBIDX_MASK) -/*! @} */ - -/*! @name INTENSET - Write 1 to enable interrupts; reads back with which are set. */ -/*! @{ */ - -#define HASHCRYPT_INTENSET_WAITING_MASK (0x1U) -#define HASHCRYPT_INTENSET_WAITING_SHIFT (0U) -/*! WAITING - Indicates if should interrupt when waiting for data input. - * 0b0..Will not interrupt when waiting. - * 0b1..Will interrupt when waiting - */ -#define HASHCRYPT_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK) - -#define HASHCRYPT_INTENSET_DIGEST_MASK (0x2U) -#define HASHCRYPT_INTENSET_DIGEST_SHIFT (1U) -/*! DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). - * 0b0..Will not interrupt when Digest is ready - * 0b1..Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). - */ -#define HASHCRYPT_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK) - -#define HASHCRYPT_INTENSET_ERROR_MASK (0x4U) -#define HASHCRYPT_INTENSET_ERROR_SHIFT (2U) -/*! ERROR - Indicates if should interrupt on an ERROR (as defined in Status) - * 0b0..Will not interrupt on Error. - * 0b1..Will interrupt on Error (until cleared). - */ -#define HASHCRYPT_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_ERROR_SHIFT)) & HASHCRYPT_INTENSET_ERROR_MASK) -/*! @} */ - -/*! @name INTENCLR - Write 1 to clear interrupts. */ -/*! @{ */ - -#define HASHCRYPT_INTENCLR_WAITING_MASK (0x1U) -#define HASHCRYPT_INTENCLR_WAITING_SHIFT (0U) -/*! WAITING - Write 1 to clear mask. - */ -#define HASHCRYPT_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK) - -#define HASHCRYPT_INTENCLR_DIGEST_MASK (0x2U) -#define HASHCRYPT_INTENCLR_DIGEST_SHIFT (1U) -/*! DIGEST - Write 1 to clear mask. - */ -#define HASHCRYPT_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK) - -#define HASHCRYPT_INTENCLR_ERROR_MASK (0x4U) -#define HASHCRYPT_INTENCLR_ERROR_SHIFT (2U) -/*! ERROR - Write 1 to clear mask. - */ -#define HASHCRYPT_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK) -/*! @} */ - -/*! @name MEMCTRL - Setup Master to access memory (if available) */ -/*! @{ */ - -#define HASHCRYPT_MEMCTRL_MASTER_MASK (0x1U) -#define HASHCRYPT_MEMCTRL_MASTER_SHIFT (0U) -/*! MASTER - Enables mastering. - * 0b0..Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. - * 0b1..Mastering is enabled and DMA and INDATA should not be used. - */ -#define HASHCRYPT_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK) - -#define HASHCRYPT_MEMCTRL_COUNT_MASK (0x7FF0000U) -#define HASHCRYPT_MEMCTRL_COUNT_SHIFT (16U) -/*! COUNT - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks - * to copy starting at MEMADDR. This register will decrement after each block is copied, ending - * in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA - * interrupt will occur on ever block. If a bus error occurs, it will stop with this field set - * to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) - * blocks to hash. - */ -#define HASHCRYPT_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK) -/*! @} */ - -/*! @name MEMADDR - Address to start memory access from (if available). */ -/*! @{ */ - -#define HASHCRYPT_MEMADDR_BASE_MASK (0xFFFFFFFFU) -#define HASHCRYPT_MEMADDR_BASE_SHIFT (0U) -/*! BASE - Address base to start copying from, word aligned (so bits 1:0 must be 0). This field will - * advance as it processes the words. If it fails with a bus error, the register will contain - * the failing word. N:Address in Flash or RAM space; RAM only as mapped in this part. May also be - * able to address SPIFI. - */ -#define HASHCRYPT_MEMADDR_BASE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK) -/*! @} */ - -/*! @name INDATA - Input of 16 words at a time to load up buffer. */ -/*! @{ */ - -#define HASHCRYPT_INDATA_DATA_MASK (0xFFFFFFFFU) -#define HASHCRYPT_INDATA_DATA_SHIFT (0U) -/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this - * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as - * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block - * will swap the word to restore into big endian. - */ -#define HASHCRYPT_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK) -/*! @} */ - -/*! @name ALIAS - */ -/*! @{ */ - -#define HASHCRYPT_ALIAS_DATA_MASK (0xFFFFFFFFU) -#define HASHCRYPT_ALIAS_DATA_SHIFT (0U) -/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this - * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as - * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block - * will swap the word to restore into big endian. - */ -#define HASHCRYPT_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK) -/*! @} */ - -/* The count of HASHCRYPT_ALIAS */ -#define HASHCRYPT_ALIAS_COUNT (7U) - -/*! @name DIGEST0 - */ -/*! @{ */ - -#define HASHCRYPT_DIGEST0_DIGEST_MASK (0xFFFFFFFFU) -#define HASHCRYPT_DIGEST0_DIGEST_SHIFT (0U) -/*! DIGEST - One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1. - */ -#define HASHCRYPT_DIGEST0_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_DIGEST0_DIGEST_SHIFT)) & HASHCRYPT_DIGEST0_DIGEST_MASK) -/*! @} */ - -/* The count of HASHCRYPT_DIGEST0 */ -#define HASHCRYPT_DIGEST0_COUNT (8U) - -/*! @name CRYPTCFG - Crypto settings for AES and Salsa and ChaCha */ -/*! @{ */ - -#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK (0x1U) -#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT (0U) -/*! MSW1ST_OUT - If 1, OUTDATA0 will be read Most significant word 1st for AES. Else it will be read - * in normal little endian - Least significant word 1st. Note: only if allowed by configuration. - */ -#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK) - -#define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK (0x2U) -#define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT (1U) -/*! SWAPKEY - If 1, will Swap the key input (bytes in each word). - */ -#define HASHCRYPT_CRYPTCFG_SWAPKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK) - -#define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK (0x4U) -#define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT (2U) -/*! SWAPDAT - If 1, will SWAP the data and IV inputs (bytes in each word). - */ -#define HASHCRYPT_CRYPTCFG_SWAPDAT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK) - -#define HASHCRYPT_CRYPTCFG_MSW1ST_MASK (0x8U) -#define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT (3U) -/*! MSW1ST - If 1, load of key, IV, and data is MSW 1st for AES. Else, the words are little endian. - * Note: only if allowed by configuration. - */ -#define HASHCRYPT_CRYPTCFG_MSW1ST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK) - -#define HASHCRYPT_CRYPTCFG_AESMODE_MASK (0x30U) -#define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT (4U) -/*! AESMODE - AES Cipher mode to use if plain AES - * 0b00..ECB - used as is - * 0b01..CBC mode (see details on IV/nonce) - * 0b10..CTR mode (see details on IV/nonce). See also AESCTRPOS. - * 0b11..reserved - */ -#define HASHCRYPT_CRYPTCFG_AESMODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK) - -#define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK (0x40U) -#define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT (6U) -/*! AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB - * 0b0..Encrypt - * 0b1..Decrypt - */ -#define HASHCRYPT_CRYPTCFG_AESDECRYPT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK) - -#define HASHCRYPT_CRYPTCFG_AESSECRET_MASK (0x80U) -#define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT (7U) -/*! AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are - * used, only the highest level is permitted to select this. - * 0b0..User key provided in normal way - * 0b1..Secret key provided in hidden way by HW - */ -#define HASHCRYPT_CRYPTCFG_AESSECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK) - -#define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK (0x300U) -#define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT (8U) -/*! AESKEYSZ - Sets the AES key size - * 0b00..128 bit key - * 0b01..192 bit key - * 0b10..256 bit key - * 0b11..reserved - */ -#define HASHCRYPT_CRYPTCFG_AESKEYSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK) - -#define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK (0x1C00U) -#define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT (10U) -/*! AESCTRPOS - Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for - * Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if - * using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other - * use CTR should use ECB directly and do its own XOR and so on. - */ -#define HASHCRYPT_CRYPTCFG_AESCTRPOS(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK) - -#define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK (0x10000U) -#define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT (16U) -/*! STREAMLAST - Is 1 if last stream block. If not 1, then the engine will compute the next "hash". - */ -#define HASHCRYPT_CRYPTCFG_STREAMLAST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK) - -#define HASHCRYPT_CRYPTCFG_ICBSZ_MASK (0x300000U) -#define HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT (20U) -/*! ICBSZ - This sets the ICB size between 32 and 128 bits, using the following rules. Note that the - * counter is assumed to occupy the low order bits of the IV. - * 0b00..32 bits of the IV/ctr are used (from 127:96) - * 0b01..64 bits of the IV/ctr are used (from 127:64) - * 0b10..96 bits of the IV/ctr are used (from 127:32) - * 0b11..All 128 bits of the IV/ctr are used - */ -#define HASHCRYPT_CRYPTCFG_ICBSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSZ_MASK) - -#define HASHCRYPT_CRYPTCFG_ICBSTRM_MASK (0xC00000U) -#define HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT (22U) -/*! ICBSTRM - The size of the ICB-AES stream that can be pushed before needing to compute a new - * IV/ctr (counter start). This optimizes the performance of the stream of blocks after the 1st. - * 0b00..8 blocks - * 0b01..16 blocks - * 0b10..32 blocks - * 0b11..64 blocks - */ -#define HASHCRYPT_CRYPTCFG_ICBSTRM(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSTRM_MASK) -/*! @} */ - -/*! @name CONFIG - Returns the configuration of this block in this chip - indicates what services are available. */ -/*! @{ */ - -#define HASHCRYPT_CONFIG_DUAL_MASK (0x1U) -#define HASHCRYPT_CONFIG_DUAL_SHIFT (0U) -/*! DUAL - 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit - */ -#define HASHCRYPT_CONFIG_DUAL(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK) - -#define HASHCRYPT_CONFIG_DMA_MASK (0x2U) -#define HASHCRYPT_CONFIG_DMA_SHIFT (1U) -/*! DMA - 1 if DMA is connected - */ -#define HASHCRYPT_CONFIG_DMA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK) - -#define HASHCRYPT_CONFIG_AHB_MASK (0x8U) -#define HASHCRYPT_CONFIG_AHB_SHIFT (3U) -/*! AHB - 1 if AHB Master is enabled - */ -#define HASHCRYPT_CONFIG_AHB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK) - -#define HASHCRYPT_CONFIG_AES_MASK (0x40U) -#define HASHCRYPT_CONFIG_AES_SHIFT (6U) -/*! AES - 1 if AES 128 included - */ -#define HASHCRYPT_CONFIG_AES(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK) - -#define HASHCRYPT_CONFIG_AESKEY_MASK (0x80U) -#define HASHCRYPT_CONFIG_AESKEY_SHIFT (7U) -/*! AESKEY - 1 if AES 192 and 256 also included - */ -#define HASHCRYPT_CONFIG_AESKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK) - -#define HASHCRYPT_CONFIG_SECRET_MASK (0x100U) -#define HASHCRYPT_CONFIG_SECRET_SHIFT (8U) -/*! SECRET - 1 if AES Secret key available - */ -#define HASHCRYPT_CONFIG_SECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK) - -#define HASHCRYPT_CONFIG_ICB_MASK (0x800U) -#define HASHCRYPT_CONFIG_ICB_SHIFT (11U) -/*! ICB - 1 if ICB over AES included - */ -#define HASHCRYPT_CONFIG_ICB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_ICB_SHIFT)) & HASHCRYPT_CONFIG_ICB_MASK) -/*! @} */ - -/*! @name LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. */ -/*! @{ */ - -#define HASHCRYPT_LOCK_SECLOCK_MASK (0x3U) -#define HASHCRYPT_LOCK_SECLOCK_SHIFT (0U) -/*! SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. - * If locked already, may only write if at same or higher security level as lock. Reads as: 0 if - * unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the - * only readable registers if locked and current state is lower than lock level. - * 0b00..Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests. - * 0b01..Locks to the current security level. AHB Master will issue requests at this level. - */ -#define HASHCRYPT_LOCK_SECLOCK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK) - -#define HASHCRYPT_LOCK_PATTERN_MASK (0xFFF0U) -#define HASHCRYPT_LOCK_PATTERN_SHIFT (4U) -/*! PATTERN - Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0 - */ -#define HASHCRYPT_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK) -/*! @} */ - -/*! @name MASK - */ -/*! @{ */ - -#define HASHCRYPT_MASK_MASK_MASK (0xFFFFFFFFU) -#define HASHCRYPT_MASK_MASK_SHIFT (0U) -/*! MASK - A random word. - */ -#define HASHCRYPT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK) -/*! @} */ - -/* The count of HASHCRYPT_MASK */ -#define HASHCRYPT_MASK_COUNT (4U) - - -/*! - * @} - */ /* end of group HASHCRYPT_Register_Masks */ - - -/* HASHCRYPT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral HASHCRYPT base address */ - #define HASHCRYPT_BASE (0x500A4000u) - /** Peripheral HASHCRYPT base address */ - #define HASHCRYPT_BASE_NS (0x400A4000u) - /** Peripheral HASHCRYPT base pointer */ - #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) - /** Peripheral HASHCRYPT base pointer */ - #define HASHCRYPT_NS ((HASHCRYPT_Type *)HASHCRYPT_BASE_NS) - /** Array initializer of HASHCRYPT peripheral base addresses */ - #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } - /** Array initializer of HASHCRYPT peripheral base pointers */ - #define HASHCRYPT_BASE_PTRS { HASHCRYPT } - /** Array initializer of HASHCRYPT peripheral base addresses */ - #define HASHCRYPT_BASE_ADDRS_NS { HASHCRYPT_BASE_NS } - /** Array initializer of HASHCRYPT peripheral base pointers */ - #define HASHCRYPT_BASE_PTRS_NS { HASHCRYPT_NS } -#else - /** Peripheral HASHCRYPT base address */ - #define HASHCRYPT_BASE (0x400A4000u) - /** Peripheral HASHCRYPT base pointer */ - #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) - /** Array initializer of HASHCRYPT peripheral base addresses */ - #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } - /** Array initializer of HASHCRYPT peripheral base pointers */ - #define HASHCRYPT_BASE_PTRS { HASHCRYPT } -#endif - -/*! - * @} - */ /* end of group HASHCRYPT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2C Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer - * @{ - */ - -/** I2C - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[2048]; - __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ - __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ - __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ - __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ - __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ - __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ - uint8_t RESERVED_1[4]; - __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ - __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ - __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ - uint8_t RESERVED_2[20]; - __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ - __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ - __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ - __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ - uint8_t RESERVED_3[36]; - __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ - uint8_t RESERVED_4[1912]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} I2C_Type; - -/* ---------------------------------------------------------------------------- - -- I2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Register_Masks I2C Register Masks - * @{ - */ - -/*! @name CFG - Configuration for shared functions. */ -/*! @{ */ - -#define I2C_CFG_MSTEN_MASK (0x1U) -#define I2C_CFG_MSTEN_SHIFT (0U) -/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not - * changed, but the Master function is internally reset. - * 0b0..Disabled. The I2C Master function is disabled. - * 0b1..Enabled. The I2C Master function is enabled. - */ -#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) - -#define I2C_CFG_SLVEN_MASK (0x2U) -#define I2C_CFG_SLVEN_SHIFT (1U) -/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not - * changed, but the Slave function is internally reset. - * 0b0..Disabled. The I2C slave function is disabled. - * 0b1..Enabled. The I2C slave function is enabled. - */ -#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) - -#define I2C_CFG_MONEN_MASK (0x4U) -#define I2C_CFG_MONEN_SHIFT (2U) -/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not - * changed, but the Monitor function is internally reset. - * 0b0..Disabled. The I2C Monitor function is disabled. - * 0b1..Enabled. The I2C Monitor function is enabled. - */ -#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) - -#define I2C_CFG_TIMEOUTEN_MASK (0x8U) -#define I2C_CFG_TIMEOUTEN_SHIFT (3U) -/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. - * 0b0..Disabled. Time-out function is disabled. - * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause - * interrupts if they are enabled. Typically, only one time-out will be used in a system. - */ -#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) - -#define I2C_CFG_MONCLKSTR_MASK (0x10U) -#define I2C_CFG_MONCLKSTR_SHIFT (4U) -/*! MONCLKSTR - Monitor function Clock Stretching. - * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able - * to read data provided by the Monitor function before it is overwritten. This mode may be used when - * non-invasive monitoring is critical. - * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can - * read all incoming data supplied by the Monitor function. - */ -#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) - -#define I2C_CFG_HSCAPABLE_MASK (0x20U) -#define I2C_CFG_HSCAPABLE_SHIFT (5U) -/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive - * and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies - * to all functions: Master, Slave, and Monitor. - * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the - * extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, - * such as changing the drive strength or filtering, must be made by software via the IOCON register associated - * with each I2C pin, - * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support - * High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more - * information. - */ -#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) -/*! @} */ - -/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ -/*! @{ */ - -#define I2C_STAT_MSTPENDING_MASK (0x1U) -#define I2C_STAT_MSTPENDING_SHIFT (0U) -/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on - * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what - * type of software service if any the master expects. This flag will cause an interrupt when set - * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling - * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle - * state, and no communication is needed, mask this interrupt. - * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. - * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the - * idle state, it is waiting to receive or transmit data or the NACK bit. - */ -#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) - -#define I2C_STAT_MSTSTATE_MASK (0xEU) -#define I2C_STAT_MSTSTATE_SHIFT (1U) -/*! MSTSTATE - Master State code. The master state code reflects the master state when the - * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field - * indicates a specific required service for the Master function. All other values are reserved. See - * Table 400 for details of state values and appropriate responses. - * 0b000..Idle. The Master function is available to be used for a new transaction. - * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. - * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. - * 0b011..NACK Address. Slave NACKed address. - * 0b100..NACK Data. Slave NACKed transmitted data. - */ -#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) - -#define I2C_STAT_MSTARBLOSS_MASK (0x10U) -#define I2C_STAT_MSTARBLOSS_SHIFT (4U) -/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to - * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - * 0b0..No Arbitration Loss has occurred. - * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master - * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, - * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. - */ -#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) - -#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) -/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to - * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - * 0b0..No Start/Stop Error has occurred. - * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is - * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an - * idle state, no action is required. A request for a Start could be made, or software could attempt to insure - * that the bus has not stalled. - */ -#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) - -#define I2C_STAT_SLVPENDING_MASK (0x100U) -#define I2C_STAT_SLVPENDING_SHIFT (8U) -/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue - * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if - * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the - * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is - * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time - * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section - * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are - * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must - * also be detected automatically, since the address must be acknowledged before the clock can be - * stretched. - * 0b0..In progress. The Slave function does not currently need service. - * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. - */ -#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) - -#define I2C_STAT_SLVSTATE_MASK (0x600U) -#define I2C_STAT_SLVSTATE_SHIFT (9U) -/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for - * the Slave function. All other values are reserved. See Table 401 for state values and actions. - * note that the occurrence of some states and how they are handled are affected by DMA mode and - * Automatic Operation modes. - * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. - * 0b01..Slave receive. Received data is available (Slave Receiver mode). - * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). - */ -#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) - -#define I2C_STAT_SLVNOTSTR_MASK (0x800U) -#define I2C_STAT_SLVNOTSTR_SHIFT (11U) -/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. - * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave - * operation. This read-only flag reflects the slave function status in real time. - * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. - * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or - * Power-down mode could be entered at this time. - */ -#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) - -#define I2C_STAT_SLVIDX_MASK (0x3000U) -#define I2C_STAT_SLVIDX_SHIFT (12U) -/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been - * selected by receiving an address that matches one of the slave addresses defined by any enabled - * slave address registers, and provides an identification of the address that was matched. It is - * possible that more than one address could be matched, but only one match can be reported here. - * 0b00..Address 0. Slave address 0 was matched. - * 0b01..Address 1. Slave address 1 was matched. - * 0b10..Address 2. Slave address 2 was matched. - * 0b11..Address 3. Slave address 3 was matched. - */ -#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) - -#define I2C_STAT_SLVSEL_MASK (0x4000U) -#define I2C_STAT_SLVSEL_SHIFT (14U) -/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave - * function to acknowledge the address, or when the address has been automatically acknowledged. - * It is cleared when another address cycle presents an address that does not match an enabled - * address on the Slave function, when slave software decides to NACK a matched address, when - * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of - * Automatic Operation. SLVSEL is not cleared if software NACKs data. - * 0b0..Not selected. The Slave function is not currently selected. - * 0b1..Selected. The Slave function is currently selected. - */ -#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) - -#define I2C_STAT_SLVDESEL_MASK (0x8000U) -#define I2C_STAT_SLVDESEL_SHIFT (15U) -/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via - * INTENSET. This flag can be cleared by writing a 1 to this bit. - * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently - * selected. That information can be found in the SLVSEL flag. - * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag - * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. - */ -#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) - -#define I2C_STAT_MONRDY_MASK (0x10000U) -#define I2C_STAT_MONRDY_SHIFT (16U) -/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. - * 0b0..No data. The Monitor function does not currently have data available. - * 0b1..Data waiting. The Monitor function has data waiting to be read. - */ -#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) - -#define I2C_STAT_MONOV_MASK (0x20000U) -#define I2C_STAT_MONOV_SHIFT (17U) -/*! MONOV - Monitor Overflow flag. - * 0b0..No overrun. Monitor data has not overrun. - * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not - * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. - */ -#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) - -#define I2C_STAT_MONACTIVE_MASK (0x40000U) -#define I2C_STAT_MONACTIVE_SHIFT (18U) -/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to - * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred - * more recently than a bus Stop. - * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. - * 0b1..Active. The Monitor function considers the I2C bus to be active. - */ -#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) - -#define I2C_STAT_MONIDLE_MASK (0x80000U) -#define I2C_STAT_MONIDLE_SHIFT (19U) -/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change - * from active to inactive. This can be used by software to decide when to process data - * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the - * INTENSET register. The flag can be cleared by writing a 1 to this bit. - * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. - * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. - */ -#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) - -#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) -/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been - * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock - * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus - * is idle. - * 0b0..No time-out. I2C bus events have not caused a time-out. - * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. - */ -#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) - -#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) -/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the - * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. - * 0b0..No time-out. SCL low time has not caused a time-out. - * 0b1..Time-out. SCL low time has caused a time-out. - */ -#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable Set and read register. */ -/*! @{ */ - -#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) -#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) -/*! MSTPENDINGEN - Master Pending interrupt Enable. - * 0b0..Disabled. The MstPending interrupt is disabled. - * 0b1..Enabled. The MstPending interrupt is enabled. - */ -#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) - -#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) -#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) -/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. - * 0b0..Disabled. The MstArbLoss interrupt is disabled. - * 0b1..Enabled. The MstArbLoss interrupt is enabled. - */ -#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) - -#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) -#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) -/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. - * 0b0..Disabled. The MstStStpErr interrupt is disabled. - * 0b1..Enabled. The MstStStpErr interrupt is enabled. - */ -#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) - -#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) -#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) -/*! SLVPENDINGEN - Slave Pending interrupt Enable. - * 0b0..Disabled. The SlvPending interrupt is disabled. - * 0b1..Enabled. The SlvPending interrupt is enabled. - */ -#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) - -#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) -#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) -/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. - * 0b0..Disabled. The SlvNotStr interrupt is disabled. - * 0b1..Enabled. The SlvNotStr interrupt is enabled. - */ -#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) - -#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) -#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) -/*! SLVDESELEN - Slave Deselect interrupt Enable. - * 0b0..Disabled. The SlvDeSel interrupt is disabled. - * 0b1..Enabled. The SlvDeSel interrupt is enabled. - */ -#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) - -#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) -#define I2C_INTENSET_MONRDYEN_SHIFT (16U) -/*! MONRDYEN - Monitor data Ready interrupt Enable. - * 0b0..Disabled. The MonRdy interrupt is disabled. - * 0b1..Enabled. The MonRdy interrupt is enabled. - */ -#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) - -#define I2C_INTENSET_MONOVEN_MASK (0x20000U) -#define I2C_INTENSET_MONOVEN_SHIFT (17U) -/*! MONOVEN - Monitor Overrun interrupt Enable. - * 0b0..Disabled. The MonOv interrupt is disabled. - * 0b1..Enabled. The MonOv interrupt is enabled. - */ -#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) - -#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) -#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) -/*! MONIDLEEN - Monitor Idle interrupt Enable. - * 0b0..Disabled. The MonIdle interrupt is disabled. - * 0b1..Enabled. The MonIdle interrupt is enabled. - */ -#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) - -#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) -#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) -/*! EVENTTIMEOUTEN - Event time-out interrupt Enable. - * 0b0..Disabled. The Event time-out interrupt is disabled. - * 0b1..Enabled. The Event time-out interrupt is enabled. - */ -#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) - -#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) -#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) -/*! SCLTIMEOUTEN - SCL time-out interrupt Enable. - * 0b0..Disabled. The SCL time-out interrupt is disabled. - * 0b1..Enabled. The SCL time-out interrupt is enabled. - */ -#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear register. */ -/*! @{ */ - -#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) -#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) -/*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding - * bit in the INTENSET register if implemented. - */ -#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) - -#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) -#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) -/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear. - */ -#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) - -#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) -#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) -/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear. - */ -#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) - -#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) -#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) -/*! SLVPENDINGCLR - Slave Pending interrupt clear. - */ -#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) - -#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) -#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) -/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear. - */ -#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) - -#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) -#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) -/*! SLVDESELCLR - Slave Deselect interrupt clear. - */ -#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) - -#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) -#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) -/*! MONRDYCLR - Monitor data Ready interrupt clear. - */ -#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) - -#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) -#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) -/*! MONOVCLR - Monitor Overrun interrupt clear. - */ -#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) - -#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) -#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) -/*! MONIDLECLR - Monitor Idle interrupt clear. - */ -#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) - -#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) -#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) -/*! EVENTTIMEOUTCLR - Event time-out interrupt clear. - */ -#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) - -#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) -#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) -/*! SCLTIMEOUTCLR - SCL time-out interrupt clear. - */ -#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) -/*! @} */ - -/*! @name TIMEOUT - Time-out value register. */ -/*! @{ */ - -#define I2C_TIMEOUT_TOMIN_MASK (0xFU) -#define I2C_TIMEOUT_TOMIN_SHIFT (0U) -/*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum - * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. - */ -#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) - -#define I2C_TIMEOUT_TO_MASK (0xFFF0U) -#define I2C_TIMEOUT_TO_SHIFT (4U) -/*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C - * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, - * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A - * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after - * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the - * I2C function clock. - */ -#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) -/*! @} */ - -/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ -/*! @{ */ - -#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) -#define I2C_CLKDIV_DIVVAL_SHIFT (0U) -/*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that - * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = - * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is - * divided by 65,536 before use. - */ -#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ -/*! @{ */ - -#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) -#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) -/*! MSTPENDING - Master Pending. - */ -#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) - -#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) -#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) -/*! MSTARBLOSS - Master Arbitration Loss flag. - */ -#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) - -#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) -/*! MSTSTSTPERR - Master Start/Stop Error flag. - */ -#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) - -#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) -#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) -/*! SLVPENDING - Slave Pending. - */ -#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) - -#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) -#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) -/*! SLVNOTSTR - Slave Not Stretching status. - */ -#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) - -#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) -#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) -/*! SLVDESEL - Slave Deselected flag. - */ -#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) - -#define I2C_INTSTAT_MONRDY_MASK (0x10000U) -#define I2C_INTSTAT_MONRDY_SHIFT (16U) -/*! MONRDY - Monitor Ready. - */ -#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) - -#define I2C_INTSTAT_MONOV_MASK (0x20000U) -#define I2C_INTSTAT_MONOV_SHIFT (17U) -/*! MONOV - Monitor Overflow flag. - */ -#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) - -#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) -#define I2C_INTSTAT_MONIDLE_SHIFT (19U) -/*! MONIDLE - Monitor Idle flag. - */ -#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) - -#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) -/*! EVENTTIMEOUT - Event time-out Interrupt flag. - */ -#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) - -#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) -/*! SCLTIMEOUT - SCL time-out Interrupt flag. - */ -#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name MSTCTL - Master control register. */ -/*! @{ */ - -#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) -#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) -/*! MSTCONTINUE - Master Continue. This bit is write-only. - * 0b0..No effect. - * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing - * transmit data, reading received data, or any other housekeeping related to the next bus operation. - */ -#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) - -#define I2C_MSTCTL_MSTSTART_MASK (0x2U) -#define I2C_MSTCTL_MSTSTART_SHIFT (1U) -/*! MSTSTART - Master Start control. This bit is write-only. - * 0b0..No effect. - * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. - */ -#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) - -#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) -#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) -/*! MSTSTOP - Master Stop control. This bit is write-only. - * 0b0..No effect. - * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave - * if the master is receiving data from the slave (Master Receiver mode). - */ -#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) - -#define I2C_MSTCTL_MSTDMA_MASK (0x8U) -#define I2C_MSTCTL_MSTDMA_SHIFT (3U) -/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type - * operations such as Start, address, Stop, and address match must always be done with software, - * typically via an interrupt. Address acknowledgement must also be done by software except when - * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by - * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA - * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is - * read/write. - * 0b0..Disable. No DMA requests are generated for master operation. - * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating - * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. - */ -#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) -/*! @} */ - -/*! @name MSTTIME - Master timing configuration. */ -/*! @{ */ - -#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) -#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) -/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this - * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This - * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters - * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. - * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. - * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. - * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. - * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. - * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. - * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. - * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. - * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. - */ -#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) - -#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) -#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) -/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this - * master on SCL. Other masters in a multi-master system could shorten this time. This - * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters - * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. - * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. - * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . - * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. - * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. - * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. - * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. - * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. - * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. - */ -#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) -/*! @} */ - -/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ -/*! @{ */ - -#define I2C_MSTDAT_DATA_MASK (0xFFU) -#define I2C_MSTDAT_DATA_SHIFT (0U) -/*! DATA - Master function data register. Read: read the most recently received data for the Master - * function. Write: transmit data using the Master function. - */ -#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVCTL - Slave control register. */ -/*! @{ */ - -#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) -#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) -/*! SLVCONTINUE - Slave Continue. - * 0b0..No effect. - * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag - * in the STAT register. This must be done after writing transmit data, reading received data, or any other - * housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE - * should not be set unless SLVPENDING = 1. - */ -#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) - -#define I2C_SLVCTL_SLVNACK_MASK (0x2U) -#define I2C_SLVCTL_SLVNACK_SHIFT (1U) -/*! SLVNACK - Slave NACK. - * 0b0..No effect. - * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). - */ -#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) - -#define I2C_SLVCTL_SLVDMA_MASK (0x8U) -#define I2C_SLVCTL_SLVDMA_SHIFT (3U) -/*! SLVDMA - Slave DMA enable. - * 0b0..Disabled. No DMA requests are issued for Slave mode operation. - * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. - */ -#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) - -#define I2C_SLVCTL_AUTOACK_MASK (0x100U) -#define I2C_SLVCTL_AUTOACK_SHIFT (8U) -/*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches - * SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA - * to allow processing of the data without intervention. If this bit is clear and a header - * matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or - * interrupt. - * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching - * address is received. If AUTONACK = 1, received addresses are NACKed (ignored). - * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, - * allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does - * not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK - * is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. - */ -#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) - -#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) -#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) -/*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write - * request on the next header with an address matching SLVADR0. Since DMA needs to be configured to - * match the transfer direction, the direction needs to be specified. This bit allows a direction to - * be chosen for the next operation. - * 0b0..The expected next operation in Automatic Mode is an I2C write. - * 0b1..The expected next operation in Automatic Mode is an I2C read. - */ -#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) -/*! @} */ - -/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ -/*! @{ */ - -#define I2C_SLVDAT_DATA_MASK (0xFFU) -#define I2C_SLVDAT_DATA_SHIFT (0U) -/*! DATA - Slave function data register. Read: read the most recently received data for the Slave - * function. Write: transmit data using the Slave function. - */ -#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVADR - Slave address register. */ -/*! @{ */ - -#define I2C_SLVADR_SADISABLE_MASK (0x1U) -#define I2C_SLVADR_SADISABLE_SHIFT (0U) -/*! SADISABLE - Slave Address n Disable. - * 0b0..Enabled. Slave Address n is enabled. - * 0b1..Ignored Slave Address n is ignored. - */ -#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) - -#define I2C_SLVADR_SLVADR_MASK (0xFEU) -#define I2C_SLVADR_SLVADR_SHIFT (1U) -/*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. - */ -#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) - -#define I2C_SLVADR_AUTONACK_MASK (0x8000U) -#define I2C_SLVADR_AUTONACK_SHIFT (15U) -/*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows - * software to ignore I2C traffic while handling previous I2C data or other operations. - * 0b0..Normal operation, matching I2C addresses are not ignored. - * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches - * SLVADRn, and AUTOMATCHREAD matches the direction. - */ -#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) -/*! @} */ - -/* The count of I2C_SLVADR */ -#define I2C_SLVADR_COUNT (4U) - -/*! @name SLVQUAL0 - Slave Qualification for address 0. */ -/*! @{ */ - -#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) -#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) -/*! QUALMODE0 - Qualify mode for slave address 0. - * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. - * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. - */ -#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) - -#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) -#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) -/*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to - * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is - * set to 1 will cause an automatic match of the corresponding bit of the received address when it - * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for - * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 - * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). - */ -#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) -/*! @} */ - -/*! @name MONRXDAT - Monitor receiver data register. */ -/*! @{ */ - -#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) -#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) -/*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. - */ -#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) - -#define I2C_MONRXDAT_MONSTART_MASK (0x100U) -#define I2C_MONRXDAT_MONSTART_SHIFT (8U) -/*! MONSTART - Monitor Received Start. - * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. - * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. - */ -#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) - -#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) -#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) -/*! MONRESTART - Monitor Received Repeated Start. - * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. - * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. - */ -#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) - -#define I2C_MONRXDAT_MONNACK_MASK (0x400U) -#define I2C_MONRXDAT_MONNACK_SHIFT (10U) -/*! MONNACK - Monitor Received NACK. - * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. - * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. - */ -#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ - -#define I2C_ID_APERTURE_MASK (0xFFU) -#define I2C_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - */ -#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) - -#define I2C_ID_MINOR_REV_MASK (0xF00U) -#define I2C_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation. - */ -#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) - -#define I2C_ID_MAJOR_REV_MASK (0xF000U) -#define I2C_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation. - */ -#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) - -#define I2C_ID_ID_MASK (0xFFFF0000U) -#define I2C_ID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function. - */ -#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2C_Register_Masks */ - - -/* I2C - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral I2C0 base address */ - #define I2C0_BASE (0x50086000u) - /** Peripheral I2C0 base address */ - #define I2C0_BASE_NS (0x40086000u) - /** Peripheral I2C0 base pointer */ - #define I2C0 ((I2C_Type *)I2C0_BASE) - /** Peripheral I2C0 base pointer */ - #define I2C0_NS ((I2C_Type *)I2C0_BASE_NS) - /** Peripheral I2C1 base address */ - #define I2C1_BASE (0x50087000u) - /** Peripheral I2C1 base address */ - #define I2C1_BASE_NS (0x40087000u) - /** Peripheral I2C1 base pointer */ - #define I2C1 ((I2C_Type *)I2C1_BASE) - /** Peripheral I2C1 base pointer */ - #define I2C1_NS ((I2C_Type *)I2C1_BASE_NS) - /** Peripheral I2C2 base address */ - #define I2C2_BASE (0x50088000u) - /** Peripheral I2C2 base address */ - #define I2C2_BASE_NS (0x40088000u) - /** Peripheral I2C2 base pointer */ - #define I2C2 ((I2C_Type *)I2C2_BASE) - /** Peripheral I2C2 base pointer */ - #define I2C2_NS ((I2C_Type *)I2C2_BASE_NS) - /** Peripheral I2C3 base address */ - #define I2C3_BASE (0x50089000u) - /** Peripheral I2C3 base address */ - #define I2C3_BASE_NS (0x40089000u) - /** Peripheral I2C3 base pointer */ - #define I2C3 ((I2C_Type *)I2C3_BASE) - /** Peripheral I2C3 base pointer */ - #define I2C3_NS ((I2C_Type *)I2C3_BASE_NS) - /** Peripheral I2C4 base address */ - #define I2C4_BASE (0x5008A000u) - /** Peripheral I2C4 base address */ - #define I2C4_BASE_NS (0x4008A000u) - /** Peripheral I2C4 base pointer */ - #define I2C4 ((I2C_Type *)I2C4_BASE) - /** Peripheral I2C4 base pointer */ - #define I2C4_NS ((I2C_Type *)I2C4_BASE_NS) - /** Peripheral I2C5 base address */ - #define I2C5_BASE (0x50096000u) - /** Peripheral I2C5 base address */ - #define I2C5_BASE_NS (0x40096000u) - /** Peripheral I2C5 base pointer */ - #define I2C5 ((I2C_Type *)I2C5_BASE) - /** Peripheral I2C5 base pointer */ - #define I2C5_NS ((I2C_Type *)I2C5_BASE_NS) - /** Peripheral I2C6 base address */ - #define I2C6_BASE (0x50097000u) - /** Peripheral I2C6 base address */ - #define I2C6_BASE_NS (0x40097000u) - /** Peripheral I2C6 base pointer */ - #define I2C6 ((I2C_Type *)I2C6_BASE) - /** Peripheral I2C6 base pointer */ - #define I2C6_NS ((I2C_Type *)I2C6_BASE_NS) - /** Peripheral I2C7 base address */ - #define I2C7_BASE (0x50098000u) - /** Peripheral I2C7 base address */ - #define I2C7_BASE_NS (0x40098000u) - /** Peripheral I2C7 base pointer */ - #define I2C7 ((I2C_Type *)I2C7_BASE) - /** Peripheral I2C7 base pointer */ - #define I2C7_NS ((I2C_Type *)I2C7_BASE_NS) - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS_NS { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS_NS { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS } -#else - /** Peripheral I2C0 base address */ - #define I2C0_BASE (0x40086000u) - /** Peripheral I2C0 base pointer */ - #define I2C0 ((I2C_Type *)I2C0_BASE) - /** Peripheral I2C1 base address */ - #define I2C1_BASE (0x40087000u) - /** Peripheral I2C1 base pointer */ - #define I2C1 ((I2C_Type *)I2C1_BASE) - /** Peripheral I2C2 base address */ - #define I2C2_BASE (0x40088000u) - /** Peripheral I2C2 base pointer */ - #define I2C2 ((I2C_Type *)I2C2_BASE) - /** Peripheral I2C3 base address */ - #define I2C3_BASE (0x40089000u) - /** Peripheral I2C3 base pointer */ - #define I2C3 ((I2C_Type *)I2C3_BASE) - /** Peripheral I2C4 base address */ - #define I2C4_BASE (0x4008A000u) - /** Peripheral I2C4 base pointer */ - #define I2C4 ((I2C_Type *)I2C4_BASE) - /** Peripheral I2C5 base address */ - #define I2C5_BASE (0x40096000u) - /** Peripheral I2C5 base pointer */ - #define I2C5 ((I2C_Type *)I2C5_BASE) - /** Peripheral I2C6 base address */ - #define I2C6_BASE (0x40097000u) - /** Peripheral I2C6 base pointer */ - #define I2C6 ((I2C_Type *)I2C6_BASE) - /** Peripheral I2C7 base address */ - #define I2C7_BASE (0x40098000u) - /** Peripheral I2C7 base pointer */ - #define I2C7 ((I2C_Type *)I2C7_BASE) - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } -#endif -/** Interrupt vectors for the I2C peripheral type */ -#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2C_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2S Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer - * @{ - */ - -/** I2S - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[3072]; - __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ - __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ - __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ - uint8_t RESERVED_2[480]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ - uint8_t RESERVED_5[8]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ - uint8_t RESERVED_6[8]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ - __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ - uint8_t RESERVED_7[432]; - __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */ -} I2S_Type; - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ -/*! @{ */ - -#define I2S_CFG1_MAINENABLE_MASK (0x1U) -#define I2S_CFG1_MAINENABLE_SHIFT (0U) -/*! MAINENABLE - Main enable for I 2S function in this Flexcomm - * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags - * are reset. No other channel pairs can be enabled. - * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. - */ -#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) - -#define I2S_CFG1_DATAPAUSE_MASK (0x2U) -#define I2S_CFG1_DATAPAUSE_SHIFT (1U) -/*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer - * and the FIFO. This could be done in order to change streams, or while restarting after a data - * underflow or overflow. When paused, FIFO operations can be done without corrupting data that is - * in the process of being sent or received. Once a data pause has been requested, the interface - * may need to complete sending data that was in progress before interrupting the flow of data. - * Software must check that the pause is actually in effect before taking action. This is done by - * monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer - * will resume at the beginning of the next frame. - * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. - * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. - */ -#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) - -#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) -#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) -/*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field - * whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this - * Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs - * in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. - * 0b00..1 I2S channel pairs in this flexcomm - * 0b01..2 I2S channel pairs in this flexcomm - * 0b10..3 I2S channel pairs in this flexcomm - * 0b11..4 I2S channel pairs in this flexcomm - */ -#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) - -#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) -#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) -/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. - * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. - * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of - * SCK, when divided from the Flexcomm function clock. - * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. - * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. - */ -#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) - -#define I2S_CFG1_MODE_MASK (0xC0U) -#define I2S_CFG1_MODE_SHIFT (6U) -/*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all - * supported cases. See Formats and modes for examples. - * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece - * of left channel data occurring during the first phase, and one pieces of right channel data occurring - * during the second phase. In this mode, the data region begins one clock after the leading WS edge for the - * frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If - * FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. - * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0. - * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame. - * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame. - */ -#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) - -#define I2S_CFG1_RIGHTLOW_MASK (0x100U) -#define I2S_CFG1_RIGHTLOW_SHIFT (8U) -/*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left - * and right channel data as it is transferred to or from the FIFO. This bit is not used if the - * data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 - * of this register) = 1, the one channel to be used is the nominally the left channel. POSITION - * can still place that data in the frame where right channel data is normally located. if all - * enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. - * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO - * bits 31:16 are used for the right channel. - * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO - * bits 15:0 are used for the right channel. - */ -#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) - -#define I2S_CFG1_LEFTJUST_MASK (0x200U) -#define I2S_CFG1_LEFTJUST_SHIFT (9U) -/*! LEFTJUST - Left Justify data. - * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting - * from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data - * in the stream on the data bus. - * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting - * from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would - * correspond to left justified data in the stream on the data bus. - */ -#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) - -#define I2S_CFG1_ONECHANNEL_MASK (0x400U) -#define I2S_CFG1_ONECHANNEL_SHIFT (10U) -/*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit - * applies only to the first I2S channel pair. Other channel pairs may select this mode - * independently in their separate CFG1 registers. - * 0b0..I2S data for this channel pair is treated as left and right channels. - * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this - * pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a - * clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel - * of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side - * (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data - * for the single channel of data is placed at the clock defined by POSITION. - */ -#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) - -#define I2S_CFG1_SCK_POL_MASK (0x1000U) -#define I2S_CFG1_SCK_POL_SHIFT (12U) -/*! SCK_POL - SCK polarity. - * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). - * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges. - */ -#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) - -#define I2S_CFG1_WS_POL_MASK (0x2000U) -#define I2S_CFG1_WS_POL_SHIFT (13U) -/*! WS_POL - WS polarity. - * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S). - * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). - */ -#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) - -#define I2S_CFG1_DATALEN_MASK (0x1F0000U) -#define I2S_CFG1_DATALEN_SHIFT (16U) -/*! DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or - * received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received - * from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the - * I2S: Determines the size of data transfers between the FIFO and the I2S - * serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of - * right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse - * at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to - * 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = - * data is 32 bits in length - */ -#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) -/*! @} */ - -/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ -/*! @{ */ - -#define I2S_CFG2_FRAMELEN_MASK (0x1FFU) -#define I2S_CFG2_FRAMELEN_SHIFT (0U) -/*! FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the - * frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported - * 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is - * 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in - * mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger - * than DATALEN in order for the WS pulse to be generated correctly. - */ -#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) - -#define I2S_CFG2_POSITION_MASK (0x1FF0000U) -#define I2S_CFG2_POSITION_SHIFT (16U) -/*! POSITION - Data Position. Defines the location within the frame of the data for this channel - * pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION - * defines the location of data in both the left phase and right phase, starting one clock after - * the WS edge. In other modes, POSITION defines the location of data within the entire frame. - * ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The - * combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels - * do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit - * position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS - * phase. 0x002 = data begins at bit position 2 within the frame or WS phase. - */ -#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) -/*! @} */ - -/*! @name STAT - Status register for the primary channel pair. */ -/*! @{ */ - -#define I2S_STAT_BUSY_MASK (0x1U) -#define I2S_STAT_BUSY_SHIFT (0U) -/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. - * 0b0..The transmitter/receiver for channel pair is currently idle. - * 0b1..The transmitter/receiver for channel pair is currently processing data. - */ -#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) - -#define I2S_STAT_SLVFRMERR_MASK (0x2U) -#define I2S_STAT_SLVFRMERR_SHIFT (1U) -/*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as - * a slave. An error indicates that the incoming WS signal did not transition as expected due to - * a mismatch between FRAMELEN and the actual incoming I2S stream. - * 0b0..No error has been recorded. - * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. - */ -#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) - -#define I2S_STAT_LR_MASK (0x4U) -#define I2S_STAT_LR_SHIFT (2U) -/*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to - * be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data - * being processed for the currently busy channel pair. - * 0b0..Left channel. - * 0b1..Right channel. - */ -#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) - -#define I2S_STAT_DATAPAUSED_MASK (0x8U) -#define I2S_STAT_DATAPAUSED_SHIFT (3U) -/*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels - * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for - * an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. - * 0b1..A data pause has been requested and is now in force. - */ -#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) -/*! @} */ - -/*! @name DIV - Clock divider, used by all channel pairs. */ -/*! @{ */ - -#define I2S_DIV_DIV_MASK (0xFFFU) -#define I2S_DIV_DIV_SHIFT (0U) -/*! DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The - * Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. - * 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is - * divided by 4,096. - */ -#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ - -#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) -#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) - -#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) -#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) - -#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) -#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) -/*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX - * FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is - * cleared, new data is provided, and the I2S is un-paused. - * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 - * bits or less, or when MONO = 1 for this channel pair. - * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. - */ -#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) - -#define I2S_FIFOCFG_PACK48_MASK (0x8U) -#define I2S_FIFOCFG_PACK48_SHIFT (3U) -/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. - * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values. - * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. - */ -#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) - -#define I2S_FIFOCFG_SIZE_MASK (0x30U) -#define I2S_FIFOCFG_SIZE_SHIFT (4U) -/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 - * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - */ -#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) - -#define I2S_FIFOCFG_DMATX_MASK (0x1000U) -#define I2S_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) - -#define I2S_FIFOCFG_DMARX_MASK (0x2000U) -#define I2S_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) - -#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) -#define I2S_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in - * FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) - -#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) -#define I2S_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in - * FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) - -#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) -/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - */ -#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) - -#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) -/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - */ -#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ - -#define I2S_FIFOSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow - * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is - * needed. Cleared by writing a 1 to this bit. - */ -#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) - -#define I2S_FIFOSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA - * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - */ -#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) - -#define I2S_FIFOSTAT_PERINT_MASK (0x8U) -#define I2S_FIFOSTAT_PERINT_SHIFT (3U) -/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted - * an interrupt. The details can be found by reading the peripheral's STAT register. - */ -#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) - -#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) -/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - */ -#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) - -#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) -/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be - * written. When 0, the transmit FIFO is full and another write would cause it to overflow. - */ -#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) - -#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - */ -#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) - -#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) -#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) -/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to - * prevent the peripheral from causing an overflow. - */ -#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) - -#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY - * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at - * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be - * 0. - */ -#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) - -#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and - * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the - * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be - * 1. - */ -#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ - -#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) - -#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) - -#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) -#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled - * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to - * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO - * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX - * FIFO level decreases to 15 entries (is no longer full). - */ -#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) - -#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data - * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level - * can wake up the device just enough to perform DMA, then return to the reduced power mode. See - * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no - * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX - * FIFO has received 16 entries (has become full). - */ -#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ - -#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) -#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) - -#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) -#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) - -#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases - * to the level specified by TXLVL in the FIFOTRIG register. - */ -#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) - -#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level - * increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ - -#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) -#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) -/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) - -#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) -#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) -/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) - -#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) -/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) - -#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) -/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ - -#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. - */ -#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) - -#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. - */ -#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) - -#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO level interrupt. - */ -#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) - -#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO level interrupt. - */ -#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) - -#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) -#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) -/*! PERINT - Peripheral interrupt. - */ -#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ - -#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFOWR_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details. - */ -#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ - -#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) -#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. - */ -#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ - -#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORD_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. The number of bits used depends on configuration details. - */ -#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ - -#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48H_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. - */ -#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ - -#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. - */ -#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ - -#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. - */ -#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) -/*! @} */ - -/*! @name FIFOSIZE - FIFO size register */ -/*! @{ */ - -#define I2S_FIFOSIZE_FIFOSIZE_MASK (0x1FU) -#define I2S_FIFOSIZE_FIFOSIZE_SHIFT (0U) -/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - */ -#define I2S_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSIZE_FIFOSIZE_SHIFT)) & I2S_FIFOSIZE_FIFOSIZE_MASK) -/*! @} */ - -/*! @name ID - I2S Module identification */ -/*! @{ */ - -#define I2S_ID_APERTURE_MASK (0xFFU) -#define I2S_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - */ -#define I2S_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_APERTURE_SHIFT)) & I2S_ID_APERTURE_MASK) - -#define I2S_ID_MINOR_REV_MASK (0xF00U) -#define I2S_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation, starting at 0. - */ -#define I2S_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK) - -#define I2S_ID_MAJOR_REV_MASK (0xF000U) -#define I2S_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation, starting at 0. - */ -#define I2S_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK) - -#define I2S_ID_ID_MASK (0xFFFF0000U) -#define I2S_ID_ID_SHIFT (16U) -/*! ID - Unique module identifier for this IP block. - */ -#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2S_Register_Masks */ - - -/* I2S - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral I2S0 base address */ - #define I2S0_BASE (0x50086000u) - /** Peripheral I2S0 base address */ - #define I2S0_BASE_NS (0x40086000u) - /** Peripheral I2S0 base pointer */ - #define I2S0 ((I2S_Type *)I2S0_BASE) - /** Peripheral I2S0 base pointer */ - #define I2S0_NS ((I2S_Type *)I2S0_BASE_NS) - /** Peripheral I2S1 base address */ - #define I2S1_BASE (0x50087000u) - /** Peripheral I2S1 base address */ - #define I2S1_BASE_NS (0x40087000u) - /** Peripheral I2S1 base pointer */ - #define I2S1 ((I2S_Type *)I2S1_BASE) - /** Peripheral I2S1 base pointer */ - #define I2S1_NS ((I2S_Type *)I2S1_BASE_NS) - /** Peripheral I2S2 base address */ - #define I2S2_BASE (0x50088000u) - /** Peripheral I2S2 base address */ - #define I2S2_BASE_NS (0x40088000u) - /** Peripheral I2S2 base pointer */ - #define I2S2 ((I2S_Type *)I2S2_BASE) - /** Peripheral I2S2 base pointer */ - #define I2S2_NS ((I2S_Type *)I2S2_BASE_NS) - /** Peripheral I2S3 base address */ - #define I2S3_BASE (0x50089000u) - /** Peripheral I2S3 base address */ - #define I2S3_BASE_NS (0x40089000u) - /** Peripheral I2S3 base pointer */ - #define I2S3 ((I2S_Type *)I2S3_BASE) - /** Peripheral I2S3 base pointer */ - #define I2S3_NS ((I2S_Type *)I2S3_BASE_NS) - /** Peripheral I2S4 base address */ - #define I2S4_BASE (0x5008A000u) - /** Peripheral I2S4 base address */ - #define I2S4_BASE_NS (0x4008A000u) - /** Peripheral I2S4 base pointer */ - #define I2S4 ((I2S_Type *)I2S4_BASE) - /** Peripheral I2S4 base pointer */ - #define I2S4_NS ((I2S_Type *)I2S4_BASE_NS) - /** Peripheral I2S5 base address */ - #define I2S5_BASE (0x50096000u) - /** Peripheral I2S5 base address */ - #define I2S5_BASE_NS (0x40096000u) - /** Peripheral I2S5 base pointer */ - #define I2S5 ((I2S_Type *)I2S5_BASE) - /** Peripheral I2S5 base pointer */ - #define I2S5_NS ((I2S_Type *)I2S5_BASE_NS) - /** Peripheral I2S6 base address */ - #define I2S6_BASE (0x50097000u) - /** Peripheral I2S6 base address */ - #define I2S6_BASE_NS (0x40097000u) - /** Peripheral I2S6 base pointer */ - #define I2S6 ((I2S_Type *)I2S6_BASE) - /** Peripheral I2S6 base pointer */ - #define I2S6_NS ((I2S_Type *)I2S6_BASE_NS) - /** Peripheral I2S7 base address */ - #define I2S7_BASE (0x50098000u) - /** Peripheral I2S7 base address */ - #define I2S7_BASE_NS (0x40098000u) - /** Peripheral I2S7 base pointer */ - #define I2S7 ((I2S_Type *)I2S7_BASE) - /** Peripheral I2S7 base pointer */ - #define I2S7_NS ((I2S_Type *)I2S7_BASE_NS) - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS_NS { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS_NS { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS } -#else - /** Peripheral I2S0 base address */ - #define I2S0_BASE (0x40086000u) - /** Peripheral I2S0 base pointer */ - #define I2S0 ((I2S_Type *)I2S0_BASE) - /** Peripheral I2S1 base address */ - #define I2S1_BASE (0x40087000u) - /** Peripheral I2S1 base pointer */ - #define I2S1 ((I2S_Type *)I2S1_BASE) - /** Peripheral I2S2 base address */ - #define I2S2_BASE (0x40088000u) - /** Peripheral I2S2 base pointer */ - #define I2S2 ((I2S_Type *)I2S2_BASE) - /** Peripheral I2S3 base address */ - #define I2S3_BASE (0x40089000u) - /** Peripheral I2S3 base pointer */ - #define I2S3 ((I2S_Type *)I2S3_BASE) - /** Peripheral I2S4 base address */ - #define I2S4_BASE (0x4008A000u) - /** Peripheral I2S4 base pointer */ - #define I2S4 ((I2S_Type *)I2S4_BASE) - /** Peripheral I2S5 base address */ - #define I2S5_BASE (0x40096000u) - /** Peripheral I2S5 base pointer */ - #define I2S5 ((I2S_Type *)I2S5_BASE) - /** Peripheral I2S6 base address */ - #define I2S6_BASE (0x40097000u) - /** Peripheral I2S6 base pointer */ - #define I2S6 ((I2S_Type *)I2S6_BASE) - /** Peripheral I2S7 base address */ - #define I2S7_BASE (0x40098000u) - /** Peripheral I2S7 base pointer */ - #define I2S7 ((I2S_Type *)I2S7_BASE) - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } -#endif -/** Interrupt vectors for the I2S peripheral type */ -#define I2S_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2S_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer - * @{ - */ - -/** INPUTMUX - Register Layout Typedef */ -typedef struct { - __IO uint32_t SCT0_INMUX[7]; /**< Input mux register for SCT0 input, array offset: 0x0, array step: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t TIMER0CAPTSEL[4]; /**< Capture select registers for TIMER0 inputs, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[16]; - __IO uint32_t TIMER1CAPTSEL[4]; /**< Capture select registers for TIMER1 inputs, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_2[16]; - __IO uint32_t TIMER2CAPTSEL[4]; /**< Capture select registers for TIMER2 inputs, array offset: 0x60, array step: 0x4 */ - uint8_t RESERVED_3[80]; - __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ - __IO uint32_t DMA0_ITRIG_INMUX[23]; /**< Trigger select register for DMA0 channel, array offset: 0xE0, array step: 0x4 */ - uint8_t RESERVED_4[36]; - __IO uint32_t DMA0_OTRIG_INMUX[4]; /**< DMA0 output trigger selection to become DMA0 trigger, array offset: 0x160, array step: 0x4 */ - uint8_t RESERVED_5[16]; - __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ - __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ - uint8_t RESERVED_6[24]; - __IO uint32_t TIMER3CAPTSEL[4]; /**< Capture select registers for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */ - uint8_t RESERVED_7[16]; - __IO uint32_t TIMER4CAPTSEL[4]; /**< Capture select registers for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */ - uint8_t RESERVED_8[16]; - __IO uint32_t PINTSECSEL[2]; /**< Pin interrupt secure select register, array offset: 0x1E0, array step: 0x4 */ - uint8_t RESERVED_9[24]; - __IO uint32_t DMA1_ITRIG_INMUX[10]; /**< Trigger select register for DMA1 channel, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_10[24]; - __IO uint32_t DMA1_OTRIG_INMUX[4]; /**< DMA1 output trigger selection to become DMA1 trigger, array offset: 0x240, array step: 0x4 */ - uint8_t RESERVED_11[1264]; - __IO uint32_t DMA0_REQ_ENA; /**< Enable DMA0 requests, offset: 0x740 */ - uint8_t RESERVED_12[4]; - __O uint32_t DMA0_REQ_ENA_SET; /**< Set one or several bits in DMA0_REQ_ENA register, offset: 0x748 */ - uint8_t RESERVED_13[4]; - __O uint32_t DMA0_REQ_ENA_CLR; /**< Clear one or several bits in DMA0_REQ_ENA register, offset: 0x750 */ - uint8_t RESERVED_14[12]; - __IO uint32_t DMA1_REQ_ENA; /**< Enable DMA1 requests, offset: 0x760 */ - uint8_t RESERVED_15[4]; - __O uint32_t DMA1_REQ_ENA_SET; /**< Set one or several bits in DMA1_REQ_ENA register, offset: 0x768 */ - uint8_t RESERVED_16[4]; - __O uint32_t DMA1_REQ_ENA_CLR; /**< Clear one or several bits in DMA1_REQ_ENA register, offset: 0x770 */ - uint8_t RESERVED_17[12]; - __IO uint32_t DMA0_ITRIG_ENA; /**< Enable DMA0 triggers, offset: 0x780 */ - uint8_t RESERVED_18[4]; - __O uint32_t DMA0_ITRIG_ENA_SET; /**< Set one or several bits in DMA0_ITRIG_ENA register, offset: 0x788 */ - uint8_t RESERVED_19[4]; - __O uint32_t DMA0_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA0_ITRIG_ENA register, offset: 0x790 */ - uint8_t RESERVED_20[12]; - __IO uint32_t DMA1_ITRIG_ENA; /**< Enable DMA1 triggers, offset: 0x7A0 */ - uint8_t RESERVED_21[4]; - __O uint32_t DMA1_ITRIG_ENA_SET; /**< Set one or several bits in DMA1_ITRIG_ENA register, offset: 0x7A8 */ - uint8_t RESERVED_22[4]; - __O uint32_t DMA1_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA1_ITRIG_ENA register, offset: 0x7B0 */ -} INPUTMUX_Type; - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks - * @{ - */ - -/*! @name SCT0_INMUX - Input mux register for SCT0 input */ -/*! @{ */ - -#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU) -#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) -/*! INP_N - Input number to SCT0 inputs 0 to 6.. - * 0b00000..SCT_GPI0 function selected from IOCON register - * 0b00001..SCT_GPI1 function selected from IOCON register - * 0b00010..SCT_GPI2 function selected from IOCON register - * 0b00011..SCT_GPI3 function selected from IOCON register - * 0b00100..SCT_GPI4 function selected from IOCON register - * 0b00101..SCT_GPI5 function selected from IOCON register - * 0b00110..SCT_GPI6 function selected from IOCON register - * 0b00111..SCT_GPI7 function selected from IOCON register - * 0b01000..T0_OUT0 ctimer 0 match[0] output - * 0b01001..T1_OUT0 ctimer 1 match[0] output - * 0b01010..T2_OUT0 ctimer 2 match[0] output - * 0b01011..T3_OUT0 ctimer 3 match[0] output - * 0b01100..T4_OUT0 ctimer 4 match[0] output - * 0b01101..ADC_IRQ interrupt request from ADC - * 0b01110..GPIOINT_BMATCH - * 0b01111..USB0_FRAME_TOGGLE - * 0b10000..USB1_FRAME_TOGGLE - * 0b10001..COMP_OUTPUT output from analog comparator - * 0b10010..I2S_SHARED_SCK[0] output from I2S pin sharing - * 0b10011..I2S_SHARED_SCK[1] output from I2S pin sharing - * 0b10100..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b10101..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b10110..ARM_TXEV interrupt event from cpu0 or cpu1 - * 0b10111..DEBUG_HALTED from cpu0 or cpu1 - * 0b11000-0b11111..None - */ -#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK) -/*! @} */ - -/* The count of INPUTMUX_SCT0_INMUX */ -#define INPUTMUX_SCT0_INMUX_COUNT (7U) - -/*! @name TIMER0CAPTSEL - Capture select registers for TIMER0 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..None - * 0b10010..None - * 0b10011..None - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER0CAPTSEL */ -#define INPUTMUX_TIMER0CAPTSEL_COUNT (4U) - -/*! @name TIMER1CAPTSEL - Capture select registers for TIMER1 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..None - * 0b10010..None - * 0b10011..None - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER1CAPTSEL */ -#define INPUTMUX_TIMER1CAPTSEL_COUNT (4U) - -/*! @name TIMER2CAPTSEL - Capture select registers for TIMER2 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..None - * 0b10010..None - * 0b10011..None - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER2CAPTSEL */ -#define INPUTMUX_TIMER2CAPTSEL_COUNT (4U) - -/*! @name PINTSEL - Pin interrupt select register */ -/*! @{ */ - -#define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU) -#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) -/*! INTPIN - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = - * (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. - */ -#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PINTSEL */ -#define INPUTMUX_PINTSEL_COUNT (8U) - -/*! @name DMA0_ITRIG_INMUX - Trigger select register for DMA0 channel */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U) -/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22). - * 0b00000..Pin interrupt 0 - * 0b00001..Pin interrupt 1 - * 0b00010..Pin interrupt 2 - * 0b00011..Pin interrupt 3 - * 0b00100..Timer CTIMER0 Match 0 - * 0b00101..Timer CTIMER0 Match 1 - * 0b00110..Timer CTIMER1 Match 0 - * 0b00111..Timer CTIMER1 Match 1 - * 0b01000..Timer CTIMER2 Match 0 - * 0b01001..Timer CTIMER2 Match 1 - * 0b01010..Timer CTIMER3 Match 0 - * 0b01011..Timer CTIMER3 Match 1 - * 0b01100..Timer CTIMER4 Match 0 - * 0b01101..Timer CTIMER4 Match 1 - * 0b01110..COMP_OUTPUT - * 0b01111..DMA0 output trigger mux 0 - * 0b10000..DMA0 output trigger mux 1 - * 0b10001..DMA0 output trigger mux 1 - * 0b10010..DMA0 output trigger mux 3 - * 0b10011..SCT0 DMA request 0 - * 0b10100..SCT0 DMA request 1 - * 0b10101..HASH DMA RX trigger - * 0b10110-0b11111..None - */ -#define INPUTMUX_DMA0_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA0_ITRIG_INMUX */ -#define INPUTMUX_DMA0_ITRIG_INMUX_COUNT (23U) - -/*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection to become DMA0 trigger */ -/*! @{ */ - -#define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U) -/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22). - */ -#define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA0_OTRIG_INMUX */ -#define INPUTMUX_DMA0_OTRIG_INMUX_COUNT (4U) - -/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ -/*! @{ */ - -#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) -/*! CLKIN - Clock source number (decimal value) for frequency measure function reference clock: - * 0b00000..External main crystal oscilator (Clock_in). - * 0b00001..FRO 12MHz clock. - * 0b00010..FRO 96MHz clock. - * 0b00011..Watchdog oscillator / FRO1MHz clock. - * 0b00100..32 kHz oscillator (32k_clk) clock. - * 0b00101..main clock (main_clock). - * 0b00110..FREQME_GPIO_CLK_A. - * 0b00111..FREQME_GPIO_CLK_B. - */ -#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) -/*! @} */ - -/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ -/*! @{ */ - -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) -/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: - * 0b00000..External main crystal oscilator (Clock_in). - * 0b00001..FRO 12MHz clock. - * 0b00010..FRO 96MHz clock. - * 0b00011..Watchdog oscillator / FRO1MHz clock. - * 0b00100..32 kHz oscillator (32k_clk) clock. - * 0b00101..main clock (main_clock). - * 0b00110..FREQME_GPIO_CLK_A. - * 0b00111..FREQME_GPIO_CLK_B. - */ -#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) -/*! @} */ - -/*! @name TIMER3CAPTSEL - Capture select registers for TIMER3 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER3CAPTSEL */ -#define INPUTMUX_TIMER3CAPTSEL_COUNT (4U) - -/*! @name TIMER4CAPTSEL - Capture select registers for TIMER4 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER4CAPTSEL */ -#define INPUTMUX_TIMER4CAPTSEL_COUNT (4U) - -/*! @name PINTSECSEL - Pin interrupt secure select register */ -/*! @{ */ - -#define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU) -#define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U) -/*! INTPIN - Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: - * INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31. - */ -#define INPUTMUX_PINTSECSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PINTSECSEL */ -#define INPUTMUX_PINTSECSEL_COUNT (2U) - -/*! @name DMA1_ITRIG_INMUX - Trigger select register for DMA1 channel */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0xFU) -#define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U) -/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9). - * 0b0000..Pin interrupt 0 - * 0b0001..Pin interrupt 1 - * 0b0010..Pin interrupt 2 - * 0b0011..Pin interrupt 3 - * 0b0100..Timer CTIMER0 Match 0 - * 0b0101..Timer CTIMER0 Match 1 - * 0b0110..Timer CTIMER2 Match 0 - * 0b0111..Timer CTIMER4 Match 0 - * 0b1000..DMA1 output trigger mux 0 - * 0b1001..DMA1 output trigger mux 1 - * 0b1010..DMA1 output trigger mux 2 - * 0b1011..DMA1 output trigger mux 3 - * 0b1100..SCT0 DMA request 0 - * 0b1101..SCT0 DMA request 1 - * 0b1110..HASH DMA RX trigger - * 0b1111..None - */ -#define INPUTMUX_DMA1_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA1_ITRIG_INMUX */ -#define INPUTMUX_DMA1_ITRIG_INMUX_COUNT (10U) - -/*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection to become DMA1 trigger */ -/*! @{ */ - -#define INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK (0xFU) -#define INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT (0U) -/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9). - */ -#define INPUTMUX_DMA1_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA1_OTRIG_INMUX */ -#define INPUTMUX_DMA1_OTRIG_INMUX_COUNT (4U) - -/*! @name DMA0_REQ_ENA - Enable DMA0 requests */ -/*! @{ */ - -#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK (0x7FFFFFU) -#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT (0U) -/*! REQ_ENA - Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK) -/*! @} */ - -/*! @name DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK (0x7FFFFFU) -#define INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT (0U) -/*! SET - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register - */ -#define INPUTMUX_DMA0_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK (0x7FFFFFU) -#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT (0U) -/*! CLR - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register - */ -#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK) -/*! @} */ - -/*! @name DMA1_REQ_ENA - Enable DMA1 requests */ -/*! @{ */ - -#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK (0x3FFU) -#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT (0U) -/*! REQ_ENA - Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK) -/*! @} */ - -/*! @name DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK (0x3FFU) -#define INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT (0U) -/*! SET - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register - */ -#define INPUTMUX_DMA1_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK (0x3FFU) -#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT (0U) -/*! CLR - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register - */ -#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_ENA - Enable DMA0 triggers */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK (0x3FFFFFU) -#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) -/*! ITRIG_ENA - Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK (0x3FFFFFU) -#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT (0U) -/*! SET - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIG_ENA register - */ -#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK (0x3FFFFFU) -#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT (0U) -/*! CLR - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIG_ENA register - */ -#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK) -/*! @} */ - -/*! @name DMA1_ITRIG_ENA - Enable DMA1 triggers */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK (0x7FFFU) -#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) -/*! ITRIG_ENA - Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK) -/*! @} */ - -/*! @name DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK (0x7FFFU) -#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT (0U) -/*! SET - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no - * change in DMA1_ITRIG_ENA register - */ -#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK (0x7FFFU) -#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT (0U) -/*! CLR - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no - * change in DMA1_ITRIG_ENA register - */ -#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group INPUTMUX_Register_Masks */ - - -/* INPUTMUX - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE (0x50006000u) - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE_NS (0x40006000u) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS) - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS { INPUTMUX } - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX_BASE_NS } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS_NS { INPUTMUX_NS } -#else - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE (0x40006000u) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS { INPUTMUX } -#endif - -/*! - * @} - */ /* end of group INPUTMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- IOCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer - * @{ - */ - -/** IOCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ -} IOCON_Type; - -/* ---------------------------------------------------------------------------- - -- IOCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Register_Masks IOCON Register Masks - * @{ - */ - -/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ -/*! @{ */ - -#define IOCON_PIO_FUNC_MASK (0xFU) -#define IOCON_PIO_FUNC_SHIFT (0U) -/*! FUNC - Selects pin function. - * 0b0000..Alternative connection 0. - * 0b0001..Alternative connection 1. - * 0b0010..Alternative connection 2. - * 0b0011..Alternative connection 3. - * 0b0100..Alternative connection 4. - * 0b0101..Alternative connection 5. - * 0b0110..Alternative connection 6. - * 0b0111..Alternative connection 7. - */ -#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) - -#define IOCON_PIO_MODE_MASK (0x30U) -#define IOCON_PIO_MODE_SHIFT (4U) -/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) - -#define IOCON_PIO_SLEW_MASK (0x40U) -#define IOCON_PIO_SLEW_SHIFT (6U) -/*! SLEW - Driver slew rate. - * 0b0..Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - * 0b1..Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - */ -#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) - -#define IOCON_PIO_INVERT_MASK (0x80U) -#define IOCON_PIO_INVERT_SHIFT (7U) -/*! INVERT - Input polarity. - * 0b0..Disabled. Input function is not inverted. - * 0b1..Enabled. Input is function inverted. - */ -#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) - -#define IOCON_PIO_DIGIMODE_MASK (0x100U) -#define IOCON_PIO_DIGIMODE_SHIFT (8U) -/*! DIGIMODE - Select Digital mode. - * 0b0..Disable digital mode. Digital input set to 0. - * 0b1..Enable Digital mode. Digital input is enabled. - */ -#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) - -#define IOCON_PIO_OD_MASK (0x200U) -#define IOCON_PIO_OD_SHIFT (9U) -/*! OD - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). - * 0b0..Normal. Normal push-pull output - * 0b1..Open-drain. Simulated open-drain output (high drive disabled). - */ -#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) - -#define IOCON_PIO_ASW_MASK (0x400U) -#define IOCON_PIO_ASW_SHIFT (10U) -/*! ASW - Analog switch input control. - * 0b0..For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed - * (enabled). For the other pins, analog switch is open (disabled). - * 0b1..For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - */ -#define IOCON_PIO_ASW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW_SHIFT)) & IOCON_PIO_ASW_MASK) - -#define IOCON_PIO_SSEL_MASK (0x800U) -#define IOCON_PIO_SSEL_SHIFT (11U) -/*! SSEL - Supply Selection bit. - * 0b0..3V3 Signaling in I2C Mode. - * 0b1..1V8 Signaling in I2C Mode. - */ -#define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK) - -#define IOCON_PIO_FILTEROFF_MASK (0x1000U) -#define IOCON_PIO_FILTEROFF_SHIFT (12U) -/*! FILTEROFF - Controls input glitch filter. - * 0b0..Filter enabled. - * 0b1..Filter disabled. - */ -#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) - -#define IOCON_PIO_ECS_MASK (0x2000U) -#define IOCON_PIO_ECS_SHIFT (13U) -/*! ECS - Pull-up current source enable in I2C mode. - * 0b1..Enabled. Pull resistor is conencted. - * 0b0..Disabled. IO is in open drain cell. - */ -#define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK) - -#define IOCON_PIO_EGP_MASK (0x4000U) -#define IOCON_PIO_EGP_SHIFT (14U) -/*! EGP - Switch between GPIO mode and I2C mode. - * 0b0..I2C mode. - * 0b1..GPIO mode. - */ -#define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK) - -#define IOCON_PIO_I2CFILTER_MASK (0x8000U) -#define IOCON_PIO_I2CFILTER_SHIFT (15U) -/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. - * 0b0..I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. - * 0b1..I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. - */ -#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) -/*! @} */ - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT (2U) - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT2 (32U) - - -/*! - * @} - */ /* end of group IOCON_Register_Masks */ - - -/* IOCON - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral IOCON base address */ - #define IOCON_BASE (0x50001000u) - /** Peripheral IOCON base address */ - #define IOCON_BASE_NS (0x40001000u) - /** Peripheral IOCON base pointer */ - #define IOCON ((IOCON_Type *)IOCON_BASE) - /** Peripheral IOCON base pointer */ - #define IOCON_NS ((IOCON_Type *)IOCON_BASE_NS) - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS { IOCON_BASE } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS { IOCON } - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS_NS { IOCON_BASE_NS } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS_NS { IOCON_NS } -#else - /** Peripheral IOCON base address */ - #define IOCON_BASE (0x40001000u) - /** Peripheral IOCON base pointer */ - #define IOCON ((IOCON_Type *)IOCON_BASE) - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS { IOCON_BASE } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS { IOCON } -#endif - -/*! - * @} - */ /* end of group IOCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MAILBOX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer - * @{ - */ - -/** MAILBOX - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x10 */ - __IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */ - __O uint32_t IRQSET; /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */ - __O uint32_t IRQCLR; /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } MBOXIRQ[2]; - uint8_t RESERVED_0[216]; - __IO uint32_t MUTEX; /**< Mutual exclusion register[1], offset: 0xF8 */ -} MAILBOX_Type; - -/* ---------------------------------------------------------------------------- - -- MAILBOX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks - * @{ - */ - -/*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */ -/*! @{ */ - -#define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) -#define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U) -/*! INTREQ - If any bit is set, an interrupt request is sent to the Cortex-M0+ interrupt controller. - */ -#define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK) -/*! @} */ - -/* The count of MAILBOX_MBOXIRQ_IRQ */ -#define MAILBOX_MBOXIRQ_IRQ_COUNT (2U) - -/*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */ -/*! @{ */ - -#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) -#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U) -/*! INTREQSET - Writing 1 sets the corresponding bit in the IRQ0 register. - */ -#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK) -/*! @} */ - -/* The count of MAILBOX_MBOXIRQ_IRQSET */ -#define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U) - -/*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */ -/*! @{ */ - -#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) -#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U) -/*! INTREQCLR - Writing 1 clears the corresponding bit in the IRQ0 register. - */ -#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK) -/*! @} */ - -/* The count of MAILBOX_MBOXIRQ_IRQCLR */ -#define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U) - -/*! @name MUTEX - Mutual exclusion register[1] */ -/*! @{ */ - -#define MAILBOX_MUTEX_EX_MASK (0x1U) -#define MAILBOX_MUTEX_EX_SHIFT (0U) -/*! EX - Cleared when read, set when written. See usage description above. - */ -#define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MAILBOX_Register_Masks */ - - -/* MAILBOX - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral MAILBOX base address */ - #define MAILBOX_BASE (0x5008B000u) - /** Peripheral MAILBOX base address */ - #define MAILBOX_BASE_NS (0x4008B000u) - /** Peripheral MAILBOX base pointer */ - #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) - /** Peripheral MAILBOX base pointer */ - #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) - /** Array initializer of MAILBOX peripheral base addresses */ - #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } - /** Array initializer of MAILBOX peripheral base pointers */ - #define MAILBOX_BASE_PTRS { MAILBOX } - /** Array initializer of MAILBOX peripheral base addresses */ - #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } - /** Array initializer of MAILBOX peripheral base pointers */ - #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } -#else - /** Peripheral MAILBOX base address */ - #define MAILBOX_BASE (0x4008B000u) - /** Peripheral MAILBOX base pointer */ - #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) - /** Array initializer of MAILBOX peripheral base addresses */ - #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } - /** Array initializer of MAILBOX peripheral base pointers */ - #define MAILBOX_BASE_PTRS { MAILBOX } -#endif -/** Interrupt vectors for the MAILBOX peripheral type */ -#define MAILBOX_IRQS { MAILBOX_IRQn } - -/*! - * @} - */ /* end of group MAILBOX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MRT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer - * @{ - */ - -/** MRT - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x10 */ - __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ - __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ - __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ - __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ - } CHANNEL[4]; - uint8_t RESERVED_0[176]; - __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ - __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ - __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ -} MRT_Type; - -/* ---------------------------------------------------------------------------- - -- MRT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Register_Masks MRT Register Masks - * @{ - */ - -/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ -/*! @{ */ - -#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) -/*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT - * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to - * this bit field starts the timer immediately. If the timer is running, writing a zero to this - * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer - * stops at the end of the time interval. - */ -#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) - -#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) -#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) -/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. - * This bit is write-only. Reading this bit always returns 0. - * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the - * time interval if the repeat mode is selected. - * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. - */ -#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_INTVAL */ -#define MRT_CHANNEL_INTVAL_COUNT (4U) - -/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ -/*! @{ */ - -#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) -/*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn - * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval - * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn - * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields - * returns -1 (0x00FF FFFF). - */ -#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_TIMER */ -#define MRT_CHANNEL_TIMER_COUNT (4U) - -/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ -/*! @{ */ - -#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) -#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) -/*! INTEN - Enable the TIMERn interrupt. - * 0b0..Disabled. TIMERn interrupt is disabled. - * 0b1..Enabled. TIMERn interrupt is enabled. - */ -#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) - -#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) -#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) -/*! MODE - Selects timer mode. - * 0b00..Repeat interrupt mode. - * 0b01..One-shot interrupt mode. - * 0b10..One-shot stall mode. - * 0b11..Reserved. - */ -#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_CTRL */ -#define MRT_CHANNEL_CTRL_COUNT (4U) - -/*! @name CHANNEL_STAT - MRT Status register. */ -/*! @{ */ - -#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) -#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) -/*! INTFLAG - Monitors the interrupt flag. - * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. - * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If - * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt - * are raised. Writing a 1 to this bit clears the interrupt request. - */ -#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) - -#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) -#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) -/*! RUN - Indicates the state of TIMERn. This bit is read-only. - * 0b0..Idle state. TIMERn is stopped. - * 0b1..Running. TIMERn is running. - */ -#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) - -#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) -#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) -/*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG - * register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating - * modes. - * 0b0..This channel is not in use. - * 0b1..This channel is in use. - */ -#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_STAT */ -#define MRT_CHANNEL_STAT_COUNT (4U) - -/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ -/*! @{ */ - -#define MRT_MODCFG_NOC_MASK (0xFU) -#define MRT_MODCFG_NOC_SHIFT (0U) -/*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.) - */ -#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) - -#define MRT_MODCFG_NOB_MASK (0x1F0U) -#define MRT_MODCFG_NOB_SHIFT (4U) -/*! NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.) - */ -#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) - -#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) -#define MRT_MODCFG_MULTITASK_SHIFT (31U) -/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. - * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. - * 0b1..Multi-task mode. - */ -#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) -/*! @} */ - -/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ -/*! @{ */ - -#define MRT_IDLE_CH_CHAN_MASK (0xF0U) -#define MRT_IDLE_CH_CHAN_SHIFT (4U) -/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is - * positioned such that it can be used as an offset from the MRT base address in order to access - * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See - * text above for more details. - */ -#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) -/*! @} */ - -/*! @name IRQ_FLAG - Global interrupt flag register */ -/*! @{ */ - -#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) -#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) -/*! GFLAG0 - Monitors the interrupt flag of TIMER0. - * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. - * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If - * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global - * interrupt are raised. Writing a 1 to this bit clears the interrupt request. - */ -#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) - -#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) -#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) -/*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0. - */ -#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) - -#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) -#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) -/*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0. - */ -#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) - -#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) -#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) -/*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0. - */ -#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MRT_Register_Masks */ - - -/* MRT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral MRT0 base address */ - #define MRT0_BASE (0x5000D000u) - /** Peripheral MRT0 base address */ - #define MRT0_BASE_NS (0x4000D000u) - /** Peripheral MRT0 base pointer */ - #define MRT0 ((MRT_Type *)MRT0_BASE) - /** Peripheral MRT0 base pointer */ - #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS { MRT0_BASE } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS { MRT0 } - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS_NS { MRT0_NS } -#else - /** Peripheral MRT0 base address */ - #define MRT0_BASE (0x4000D000u) - /** Peripheral MRT0 base pointer */ - #define MRT0 ((MRT_Type *)MRT0_BASE) - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS { MRT0_BASE } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS { MRT0 } -#endif -/** Interrupt vectors for the MRT peripheral type */ -#define MRT_IRQS { MRT0_IRQn } - -/*! - * @} - */ /* end of group MRT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- OSTIMER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer - * @{ - */ - -/** OSTIMER - Register Layout Typedef */ -typedef struct { - __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */ - __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */ - __I uint32_t CAPTURE_L; /**< Capture Low Register, offset: 0x8 */ - __I uint32_t CAPTURE_H; /**< Capture High Register, offset: 0xC */ - __IO uint32_t MATCH_L; /**< Match Low Register, offset: 0x10 */ - __IO uint32_t MATCH_H; /**< Match High Register, offset: 0x14 */ - uint8_t RESERVED_0[4]; - __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register, offset: 0x1C */ -} OSTIMER_Type; - -/* ---------------------------------------------------------------------------- - -- OSTIMER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks - * @{ - */ - -/*! @name EVTIMERL - EVTIMER Low Register */ -/*! @{ */ - -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) -/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the lower 32 bits of the 42-bits - * EVTIMER. Note: There is only one EVTIMER, readable from all domains. - */ -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) -/*! @} */ - -/*! @name EVTIMERH - EVTIMER High Register */ -/*! @{ */ - -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU) -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) -/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the upper 10 bits of the 42-bits - * EVTIMER. Note there is only one EVTIMER, readable from all domains. - */ -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) -/*! @} */ - -/*! @name CAPTURE_L - Capture Low Register */ -/*! @{ */ - -#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U) -/*! CAPTURE_VALUE - A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at - * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). - */ -#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK) -/*! @} */ - -/*! @name CAPTURE_H - Capture High Register */ -/*! @{ */ - -#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0x3FFU) -#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U) -/*! CAPTURE_VALUE - A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at - * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). - */ -#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK) -/*! @} */ - -/*! @name MATCH_L - Match Low Register */ -/*! @{ */ - -#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U) -/*! MATCH_VALUE - The value written to the MATCH (L/H) register pair is compared against the central - * EVTIMER. When a match occurs, an interrupt request is generated if enabled. - */ -#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK) -/*! @} */ - -/*! @name MATCH_H - Match High Register */ -/*! @{ */ - -#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0x3FFU) -#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U) -/*! MATCH_VALUE - The value written (upper 10 bits) to the MATCH (L/H) register pair is compared - * against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. - */ -#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK) -/*! @} */ - -/*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register */ -/*! @{ */ - -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) -/*! OSTIMER_INTRFLAG - This bit is set when a match occurs between the central 42-bits EVTIMER and - * the value programmed in the match-register pair. This bit is cleared by writing a '1'. Writes - * to clear this bit are asynchronous. It should be done before a new match value is written into - * the MATCH_L/H registers. - */ -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) - -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) -/*! OSTIMER_INTENA - When this bit is '1' an interrupt/wakeup request to the domain processor will - * be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests - * due to the OSTIMER_INTR flag are blocked. - */ -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) - -#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U) -#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U) -/*! MATCH_WR_RDY - This bit will be low when it is safe to write to reload the Match Registers. In - * typical applications it should not be necessary to test this bit. [1] - */ -#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group OSTIMER_Register_Masks */ - - -/* OSTIMER - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral OSTIMER base address */ - #define OSTIMER_BASE (0x5002D000u) - /** Peripheral OSTIMER base address */ - #define OSTIMER_BASE_NS (0x4002D000u) - /** Peripheral OSTIMER base pointer */ - #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) - /** Peripheral OSTIMER base pointer */ - #define OSTIMER_NS ((OSTIMER_Type *)OSTIMER_BASE_NS) - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS { OSTIMER } - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS_NS { OSTIMER_BASE_NS } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS_NS { OSTIMER_NS } -#else - /** Peripheral OSTIMER base address */ - #define OSTIMER_BASE (0x4002D000u) - /** Peripheral OSTIMER base pointer */ - #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS { OSTIMER } -#endif -/** Interrupt vectors for the OSTIMER peripheral type */ -#define OSTIMER_IRQS { OS_EVENT_IRQn } - -/*! - * @} - */ /* end of group OSTIMER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer - * @{ - */ - -/** PINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ - __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ - __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ - __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ - __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ - __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ - __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ - __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ - __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ - __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ - __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ - __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ - __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ -} PINT_Type; - -/* ---------------------------------------------------------------------------- - -- PINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Register_Masks PINT Register Masks - * @{ - */ - -/*! @name ISEL - Pin Interrupt Mode register */ -/*! @{ */ - -#define PINT_ISEL_PMODE_MASK (0xFFU) -#define PINT_ISEL_PMODE_SHIFT (0U) -/*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt - * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive - */ -#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) -/*! @} */ - -/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ -/*! @{ */ - -#define PINT_IENR_ENRL_MASK (0xFFU) -#define PINT_IENR_ENRL_SHIFT (0U) -/*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the - * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable - * rising edge or level interrupt. - */ -#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) -/*! @} */ - -/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ -/*! @{ */ - -#define PINT_SIENR_SETENRL_MASK (0xFFU) -#define PINT_SIENR_SETENRL_SHIFT (0U) -/*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n - * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. - */ -#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) -/*! @} */ - -/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ -/*! @{ */ - -#define PINT_CIENR_CENRL_MASK (0xFFU) -#define PINT_CIENR_CENRL_SHIFT (0U) -/*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit - * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level - * interrupt. - */ -#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) -/*! @} */ - -/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ -/*! @{ */ - -#define PINT_IENF_ENAF_MASK (0xFFU) -#define PINT_IENF_ENAF_SHIFT (0U) -/*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt. - * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt - * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active - * interrupt level HIGH. - */ -#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) -/*! @} */ - -/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ -/*! @{ */ - -#define PINT_SIENF_SETENAF_MASK (0xFFU) -#define PINT_SIENF_SETENAF_SHIFT (0U) -/*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n - * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable - * falling edge interrupt. - */ -#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) -/*! @} */ - -/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ -/*! @{ */ - -#define PINT_CIENF_CENAF_MASK (0xFFU) -#define PINT_CIENF_CENAF_SHIFT (0U) -/*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n - * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or - * falling edge interrupt disabled. - */ -#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) -/*! @} */ - -/*! @name RISE - Pin interrupt rising edge register */ -/*! @{ */ - -#define PINT_RISE_RDET_MASK (0xFFU) -#define PINT_RISE_RDET_SHIFT (0U) -/*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read - * 0: No rising edge has been detected on this pin since Reset or the last time a one was written - * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the - * last time a one was written to this bit. Write 1: clear rising edge detection for this pin. - */ -#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) -/*! @} */ - -/*! @name FALL - Pin interrupt falling edge register */ -/*! @{ */ - -#define PINT_FALL_FDET_MASK (0xFFU) -#define PINT_FALL_FDET_SHIFT (0U) -/*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read - * 0: No falling edge has been detected on this pin since Reset or the last time a one was - * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or - * the last time a one was written to this bit. Write 1: clear falling edge detection for this - * pin. - */ -#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) -/*! @} */ - -/*! @name IST - Pin interrupt status register */ -/*! @{ */ - -#define PINT_IST_PSTAT_MASK (0xFFU) -#define PINT_IST_PSTAT_SHIFT (0U) -/*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts - * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for - * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this - * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. - * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). - */ -#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) -/*! @} */ - -/*! @name PMCTRL - Pattern match interrupt control register */ -/*! @{ */ - -#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) -#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) -/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. - * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. - * 0b1..Pattern match. Interrupts are driven in response to pattern matches. - */ -#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) - -#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) -#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) -/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. - * 0b0..Disabled. RXEV output to the CPU is disabled. - * 0b1..Enabled. RXEV output to the CPU is enabled. - */ -#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) - -#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) -#define PINT_PMCTRL_PMAT_SHIFT (24U) -/*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field - * indicates that the corresponding product term is matched by the current state of the appropriate - * inputs. - */ -#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) -/*! @} */ - -/*! @name PMSRC - Pattern match interrupt bit-slice source register */ -/*! @{ */ - -#define PINT_PMSRC_SRC0_MASK (0x700U) -#define PINT_PMSRC_SRC0_SHIFT (8U) -/*! SRC0 - Selects the input source for bit slice 0 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. - */ -#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) - -#define PINT_PMSRC_SRC1_MASK (0x3800U) -#define PINT_PMSRC_SRC1_SHIFT (11U) -/*! SRC1 - Selects the input source for bit slice 1 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. - */ -#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) - -#define PINT_PMSRC_SRC2_MASK (0x1C000U) -#define PINT_PMSRC_SRC2_SHIFT (14U) -/*! SRC2 - Selects the input source for bit slice 2 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. - */ -#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) - -#define PINT_PMSRC_SRC3_MASK (0xE0000U) -#define PINT_PMSRC_SRC3_SHIFT (17U) -/*! SRC3 - Selects the input source for bit slice 3 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. - */ -#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) - -#define PINT_PMSRC_SRC4_MASK (0x700000U) -#define PINT_PMSRC_SRC4_SHIFT (20U) -/*! SRC4 - Selects the input source for bit slice 4 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. - */ -#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) - -#define PINT_PMSRC_SRC5_MASK (0x3800000U) -#define PINT_PMSRC_SRC5_SHIFT (23U) -/*! SRC5 - Selects the input source for bit slice 5 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. - */ -#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) - -#define PINT_PMSRC_SRC6_MASK (0x1C000000U) -#define PINT_PMSRC_SRC6_SHIFT (26U) -/*! SRC6 - Selects the input source for bit slice 6 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. - */ -#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) - -#define PINT_PMSRC_SRC7_MASK (0xE0000000U) -#define PINT_PMSRC_SRC7_SHIFT (29U) -/*! SRC7 - Selects the input source for bit slice 7 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. - */ -#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) -/*! @} */ - -/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ -/*! @{ */ - -#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) -#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) -/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. - * 0b0..No effect. Slice 0 is not an endpoint. - * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) - -#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) -#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) -/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. - * 0b0..No effect. Slice 1 is not an endpoint. - * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) - -#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) -#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) -/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. - * 0b0..No effect. Slice 2 is not an endpoint. - * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) - -#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) -#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) -/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. - * 0b0..No effect. Slice 3 is not an endpoint. - * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) - -#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) -#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) -/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. - * 0b0..No effect. Slice 4 is not an endpoint. - * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) - -#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) -#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) -/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. - * 0b0..No effect. Slice 5 is not an endpoint. - * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) - -#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) -#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) -/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. - * 0b0..No effect. Slice 6 is not an endpoint. - * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) - -#define PINT_PMCFG_CFG0_MASK (0x700U) -#define PINT_PMCFG_CFG0_SHIFT (8U) -/*! CFG0 - Specifies the match contribution condition for bit slice 0. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) - -#define PINT_PMCFG_CFG1_MASK (0x3800U) -#define PINT_PMCFG_CFG1_SHIFT (11U) -/*! CFG1 - Specifies the match contribution condition for bit slice 1. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) - -#define PINT_PMCFG_CFG2_MASK (0x1C000U) -#define PINT_PMCFG_CFG2_SHIFT (14U) -/*! CFG2 - Specifies the match contribution condition for bit slice 2. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) - -#define PINT_PMCFG_CFG3_MASK (0xE0000U) -#define PINT_PMCFG_CFG3_SHIFT (17U) -/*! CFG3 - Specifies the match contribution condition for bit slice 3. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) - -#define PINT_PMCFG_CFG4_MASK (0x700000U) -#define PINT_PMCFG_CFG4_SHIFT (20U) -/*! CFG4 - Specifies the match contribution condition for bit slice 4. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) - -#define PINT_PMCFG_CFG5_MASK (0x3800000U) -#define PINT_PMCFG_CFG5_SHIFT (23U) -/*! CFG5 - Specifies the match contribution condition for bit slice 5. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) - -#define PINT_PMCFG_CFG6_MASK (0x1C000000U) -#define PINT_PMCFG_CFG6_SHIFT (26U) -/*! CFG6 - Specifies the match contribution condition for bit slice 6. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) - -#define PINT_PMCFG_CFG7_MASK (0xE0000000U) -#define PINT_PMCFG_CFG7_SHIFT (29U) -/*! CFG7 - Specifies the match contribution condition for bit slice 7. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PINT_Register_Masks */ - - -/* PINT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PINT base address */ - #define PINT_BASE (0x50004000u) - /** Peripheral PINT base address */ - #define PINT_BASE_NS (0x40004000u) - /** Peripheral PINT base pointer */ - #define PINT ((PINT_Type *)PINT_BASE) - /** Peripheral PINT base pointer */ - #define PINT_NS ((PINT_Type *)PINT_BASE_NS) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE (0x50005000u) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE_NS (0x40005000u) - /** Peripheral SECPINT base pointer */ - #define SECPINT ((PINT_Type *)SECPINT_BASE) - /** Peripheral SECPINT base pointer */ - #define SECPINT_NS ((PINT_Type *)SECPINT_BASE_NS) - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS { PINT, SECPINT } - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS_NS { PINT_BASE_NS, SECPINT_BASE_NS } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS_NS { PINT_NS, SECPINT_NS } -#else - /** Peripheral PINT base address */ - #define PINT_BASE (0x40004000u) - /** Peripheral PINT base pointer */ - #define PINT ((PINT_Type *)PINT_BASE) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE (0x40005000u) - /** Peripheral SECPINT base pointer */ - #define SECPINT ((PINT_Type *)SECPINT_BASE) - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS { PINT, SECPINT } -#endif -/** Interrupt vectors for the PINT peripheral type */ -#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn } - -/*! - * @} - */ /* end of group PINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PLU Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PLU_Peripheral_Access_Layer PLU Peripheral Access Layer - * @{ - */ - -/** PLU - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x20 */ - __IO uint32_t INP_MUX[5]; /**< LUTn input x MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */ - uint8_t RESERVED_0[12]; - } LUT[26]; - uint8_t RESERVED_0[1216]; - __IO uint32_t LUT_TRUTH[26]; /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25, array offset: 0x800, array step: 0x4 */ - uint8_t RESERVED_1[152]; - __I uint32_t OUTPUTS; /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */ - __IO uint32_t WAKEINT_CTRL; /**< Wakeup interrupt control for PLU, offset: 0x904 */ - uint8_t RESERVED_2[760]; - __IO uint32_t OUTPUT_MUX[8]; /**< Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */ -} PLU_Type; - -/* ---------------------------------------------------------------------------- - -- PLU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PLU_Register_Masks PLU Register Masks - * @{ - */ - -/*! @name LUT_INP_MUX - LUTn input x MUX */ -/*! @{ */ - -#define PLU_LUT_INP_MUX_LUTn_INPx_MASK (0x3FU) -#define PLU_LUT_INP_MUX_LUTn_INPx_SHIFT (0U) -/*! LUTn_INPx - Selects the input source to be connected to LUT25 input4. For each LUT, the slot - * associated with the output from LUTn itself is tied low. - * 0b000000..The PLU primary inputs 0. - * 0b000001..The PLU primary inputs 1. - * 0b000010..The PLU primary inputs 2. - * 0b000011..The PLU primary inputs 3. - * 0b000100..The PLU primary inputs 4. - * 0b000101..The PLU primary inputs 5. - * 0b000110..The output of LUT0. - * 0b000111..The output of LUT1. - * 0b001000..The output of LUT2. - * 0b001001..The output of LUT3. - * 0b001010..The output of LUT4. - * 0b001011..The output of LUT5. - * 0b001100..The output of LUT6. - * 0b001101..The output of LUT7. - * 0b001110..The output of LUT8. - * 0b001111..The output of LUT9. - * 0b010000..The output of LUT10. - * 0b010001..The output of LUT11. - * 0b010010..The output of LUT12. - * 0b010011..The output of LUT13. - * 0b010100..The output of LUT14. - * 0b010101..The output of LUT15. - * 0b010110..The output of LUT16. - * 0b010111..The output of LUT17. - * 0b011000..The output of LUT18. - * 0b011001..The output of LUT19. - * 0b011010..The output of LUT20. - * 0b011011..The output of LUT21. - * 0b011100..The output of LUT22. - * 0b011101..The output of LUT23. - * 0b011110..The output of LUT24. - * 0b011111..The output of LUT25. - * 0b100000..state(0). - * 0b100001..state(1). - * 0b100010..state(2). - * 0b100011..state(3). - */ -#define PLU_LUT_INP_MUX_LUTn_INPx(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_MUX_LUTn_INPx_SHIFT)) & PLU_LUT_INP_MUX_LUTn_INPx_MASK) -/*! @} */ - -/* The count of PLU_LUT_INP_MUX */ -#define PLU_LUT_INP_MUX_COUNT (26U) - -/* The count of PLU_LUT_INP_MUX */ -#define PLU_LUT_INP_MUX_COUNT2 (5U) - -/*! @name LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */ -/*! @{ */ - -#define PLU_LUT_TRUTH_LUTn_TRUTH_MASK (0xFFFFFFFFU) -#define PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT (0U) -/*! LUTn_TRUTH - Specifies the Truth Table contents for LUT25.. - */ -#define PLU_LUT_TRUTH_LUTn_TRUTH(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT)) & PLU_LUT_TRUTH_LUTn_TRUTH_MASK) -/*! @} */ - -/* The count of PLU_LUT_TRUTH */ -#define PLU_LUT_TRUTH_COUNT (26U) - -/*! @name OUTPUTS - Provides the current state of the 8 designated PLU Outputs. */ -/*! @{ */ - -#define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU) -#define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U) -/*! OUTPUT_STATE - Provides the current state of the 8 designated PLU Outputs.. - */ -#define PLU_OUTPUTS_OUTPUT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK) -/*! @} */ - -/*! @name WAKEINT_CTRL - Wakeup interrupt control for PLU */ -/*! @{ */ - -#define PLU_WAKEINT_CTRL_MASK_MASK (0xFFU) -#define PLU_WAKEINT_CTRL_MASK_SHIFT (0U) -/*! MASK - Interrupt mask (which of the 8 PLU Outputs contribute to interrupt) - */ -#define PLU_WAKEINT_CTRL_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_MASK_SHIFT)) & PLU_WAKEINT_CTRL_MASK_MASK) - -#define PLU_WAKEINT_CTRL_FILTER_MODE_MASK (0x300U) -#define PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT (8U) -/*! FILTER_MODE - control input of the PLU, add filtering for glitch. - * 0b00..Bypass mode. - * 0b01..Filter 1 clock period. - * 0b10..Filter 2 clock period. - * 0b11..Filter 3 clock period. - */ -#define PLU_WAKEINT_CTRL_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_MODE_MASK) - -#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK (0xC00U) -#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT (10U) -/*! FILTER_CLKSEL - hclk is divided by 2**filter_clksel. - * 0b00..Selects the 1 MHz low-power oscillator as the filter clock. - * 0b01..Selects the 12 Mhz FRO as the filter clock. - * 0b10..Selects a third filter clock source, if provided. - * 0b11..Reserved. - */ -#define PLU_WAKEINT_CTRL_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK) - -#define PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK (0x1000U) -#define PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT (12U) -/*! LATCH_ENABLE - latch the interrupt , then can be cleared with next bit INTR_CLEAR - */ -#define PLU_WAKEINT_CTRL_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK) - -#define PLU_WAKEINT_CTRL_INTR_CLEAR_MASK (0x2000U) -#define PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT (13U) -/*! INTR_CLEAR - Write to clear wakeint_latched - */ -#define PLU_WAKEINT_CTRL_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK) -/*! @} */ - -/*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7 */ -/*! @{ */ - -#define PLU_OUTPUT_MUX_OUTPUTn_MASK (0x1FU) -#define PLU_OUTPUT_MUX_OUTPUTn_SHIFT (0U) -/*! OUTPUTn - Selects the source to be connected to PLU Output 7. - * 0b00000..The PLU output 0. - * 0b00001..The PLU output 1. - * 0b00010..The PLU output 2. - * 0b00011..The PLU output 3. - * 0b00100..The PLU output 4. - * 0b00101..The PLU output 5. - * 0b00110..The PLU output 6. - * 0b00111..The PLU output 7. - * 0b01000..The PLU output 8. - * 0b01001..The PLU output 9. - * 0b01010..The PLU output 10. - * 0b01011..The PLU output 11. - * 0b01100..The PLU output 12. - * 0b01101..The PLU output 13. - * 0b01110..The PLU output 14. - * 0b01111..The PLU output 15. - * 0b10000..The PLU output 16. - * 0b10001..The PLU output 17. - * 0b10010..The PLU output 18. - * 0b10011..The PLU output 19. - * 0b10100..The PLU output 20. - * 0b10101..The PLU output 21. - * 0b10110..The PLU output 22. - * 0b10111..The PLU output 23. - * 0b11000..The PLU output 24. - * 0b11001..The PLU output 25. - * 0b11010..state(0). - * 0b11011..state(1). - * 0b11100..state(2). - * 0b11101..state(3). - */ -#define PLU_OUTPUT_MUX_OUTPUTn(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUTn_SHIFT)) & PLU_OUTPUT_MUX_OUTPUTn_MASK) -/*! @} */ - -/* The count of PLU_OUTPUT_MUX */ -#define PLU_OUTPUT_MUX_COUNT (8U) - - -/*! - * @} - */ /* end of group PLU_Register_Masks */ - - -/* PLU - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PLU base address */ - #define PLU_BASE (0x5003D000u) - /** Peripheral PLU base address */ - #define PLU_BASE_NS (0x4003D000u) - /** Peripheral PLU base pointer */ - #define PLU ((PLU_Type *)PLU_BASE) - /** Peripheral PLU base pointer */ - #define PLU_NS ((PLU_Type *)PLU_BASE_NS) - /** Array initializer of PLU peripheral base addresses */ - #define PLU_BASE_ADDRS { PLU_BASE } - /** Array initializer of PLU peripheral base pointers */ - #define PLU_BASE_PTRS { PLU } - /** Array initializer of PLU peripheral base addresses */ - #define PLU_BASE_ADDRS_NS { PLU_BASE_NS } - /** Array initializer of PLU peripheral base pointers */ - #define PLU_BASE_PTRS_NS { PLU_NS } -#else - /** Peripheral PLU base address */ - #define PLU_BASE (0x4003D000u) - /** Peripheral PLU base pointer */ - #define PLU ((PLU_Type *)PLU_BASE) - /** Array initializer of PLU peripheral base addresses */ - #define PLU_BASE_ADDRS { PLU_BASE } - /** Array initializer of PLU peripheral base pointers */ - #define PLU_BASE_PTRS { PLU } -#endif - -/*! - * @} - */ /* end of group PLU_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer - * @{ - */ - -/** PMC - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4]; - __I uint32_t STATUS; /**< Power Management Controller FSM (Finite State Machines) status, offset: 0x4 */ - __IO uint32_t RESETCTRL; /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x8 */ - uint8_t RESERVED_1[4]; - __IO uint32_t DCDC0; /**< DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x10 */ - __IO uint32_t DCDC1; /**< DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x14 */ - uint8_t RESERVED_2[4]; - __IO uint32_t LDOPMU; /**< Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x1C */ - uint8_t RESERVED_3[16]; - __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */ - uint8_t RESERVED_4[12]; - __IO uint32_t REFFASTWKUP; /**< Analog References fast wake-up Control register [Reset by: PoR], offset: 0x40 */ - uint8_t RESERVED_5[8]; - __IO uint32_t XTAL32K; /**< 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x4C */ - __IO uint32_t COMP; /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x50 */ - uint8_t RESERVED_6[16]; - __IO uint32_t WAKEUPIOCTRL; /**< Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset], offset: 0x64 */ - __IO uint32_t WAKEIOCAUSE; /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */ - uint8_t RESERVED_7[8]; - __IO uint32_t STATUSCLK; /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */ - uint8_t RESERVED_8[12]; - __IO uint32_t AOREG1; /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset], offset: 0x84 */ - uint8_t RESERVED_9[8]; - __IO uint32_t MISCCTRL; /**< Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x90 */ - uint8_t RESERVED_10[4]; - __IO uint32_t RTCOSC32K; /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x98 */ - __IO uint32_t OSTIMERr; /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C */ - uint8_t RESERVED_11[24]; - __IO uint32_t PDRUNCFG0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */ - uint8_t RESERVED_12[4]; - __O uint32_t PDRUNCFGSET0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */ - uint8_t RESERVED_13[4]; - __O uint32_t PDRUNCFGCLR0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */ - uint8_t RESERVED_14[8]; - __IO uint32_t SRAMCTRL; /**< All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xD4 */ -} PMC_Type; - -/* ---------------------------------------------------------------------------- - -- PMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Register_Masks PMC Register Masks - * @{ - */ - -/*! @name STATUS - Power Management Controller FSM (Finite State Machines) status */ -/*! @{ */ - -#define PMC_STATUS_BOOTMODE_MASK (0xC0000U) -#define PMC_STATUS_BOOTMODE_SHIFT (18U) -/*! BOOTMODE - Latest IC Boot cause:. - * 0b00..Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset). - * 0b01..Latest IC boot was from DEEP SLEEP low power mode. - * 0b10..Latest IC boot was from POWER DOWN low power mode. - * 0b11..Latest IC boot was from DEEP POWER DOWN low power mode. - */ -#define PMC_STATUS_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_BOOTMODE_SHIFT)) & PMC_STATUS_BOOTMODE_MASK) -/*! @} */ - -/*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U) -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U) -/*! DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). - * 0b0..Reset event from DEEP POWER DOWN mode is disable. - * 0b1..Reset event from DEEP POWER DOWN mode is enable. - */ -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK) - -#define PMC_RESETCTRL_BODVBATRESETENABLE_MASK (0x2U) -#define PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT (1U) -/*! BODVBATRESETENABLE - BOD VBAT reset enable. - * 0b0..BOD VBAT reset is disable. - * 0b1..BOD VBAT reset is enable. - */ -#define PMC_RESETCTRL_BODVBATRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENABLE_MASK) - -#define PMC_RESETCTRL_BODCORERESETENABLE_MASK (0x4U) -#define PMC_RESETCTRL_BODCORERESETENABLE_SHIFT (2U) -/*! BODCORERESETENABLE - BOD CORE reset enable. - * 0b0..BOD CORE reset is disable. - * 0b1..BOD CORE reset is enable. - */ -#define PMC_RESETCTRL_BODCORERESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENABLE_SHIFT)) & PMC_RESETCTRL_BODCORERESETENABLE_MASK) - -#define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U) -#define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U) -/*! SWRRESETENABLE - Software reset enable. - * 0b0..Software reset is disable. - * 0b1..Software reset is enable. - */ -#define PMC_RESETCTRL_SWRRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK) -/*! @} */ - -/*! @name DCDC0 - DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_DCDC0_RC_MASK (0x3FU) -#define PMC_DCDC0_RC_SHIFT (0U) -/*! RC - Constant On-Time calibration. - */ -#define PMC_DCDC0_RC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_RC_SHIFT)) & PMC_DCDC0_RC_MASK) - -#define PMC_DCDC0_ICOMP_MASK (0xC0U) -#define PMC_DCDC0_ICOMP_SHIFT (6U) -/*! ICOMP - Select the type of ZCD comparator. - */ -#define PMC_DCDC0_ICOMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICOMP_SHIFT)) & PMC_DCDC0_ICOMP_MASK) - -#define PMC_DCDC0_ISEL_MASK (0x300U) -#define PMC_DCDC0_ISEL_SHIFT (8U) -/*! ISEL - Alter Internal biasing currents. - */ -#define PMC_DCDC0_ISEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ISEL_SHIFT)) & PMC_DCDC0_ISEL_MASK) - -#define PMC_DCDC0_ICENABLE_MASK (0x400U) -#define PMC_DCDC0_ICENABLE_SHIFT (10U) -/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD. - */ -#define PMC_DCDC0_ICENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICENABLE_SHIFT)) & PMC_DCDC0_ICENABLE_MASK) - -#define PMC_DCDC0_TMOS_MASK (0xF800U) -#define PMC_DCDC0_TMOS_SHIFT (11U) -/*! TMOS - One-shot generator reference current trimming signal. - */ -#define PMC_DCDC0_TMOS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_TMOS_SHIFT)) & PMC_DCDC0_TMOS_MASK) - -#define PMC_DCDC0_DISABLEISENSE_MASK (0x10000U) -#define PMC_DCDC0_DISABLEISENSE_SHIFT (16U) -/*! DISABLEISENSE - Disable Current sensing. - */ -#define PMC_DCDC0_DISABLEISENSE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_DISABLEISENSE_SHIFT)) & PMC_DCDC0_DISABLEISENSE_MASK) - -#define PMC_DCDC0_VOUT_MASK (0x1E0000U) -#define PMC_DCDC0_VOUT_SHIFT (17U) -/*! VOUT - Set output regulation voltage. - * 0b0000..0.95 V. - * 0b0001..0.975 V. - * 0b0010..1 V. - * 0b0011..1.025 V. - * 0b0100..1.05 V. - * 0b0101..1.075 V. - * 0b0110..1.1 V. - * 0b0111..1.125 V. - * 0b1000..1.15 V. - * 0b1001..1.175 V. - * 0b1010..1.2 V. - */ -#define PMC_DCDC0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_SHIFT)) & PMC_DCDC0_VOUT_MASK) - -#define PMC_DCDC0_SLICINGENABLE_MASK (0x200000U) -#define PMC_DCDC0_SLICINGENABLE_SHIFT (21U) -/*! SLICINGENABLE - Enable staggered switching of power switches. - */ -#define PMC_DCDC0_SLICINGENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_SLICINGENABLE_SHIFT)) & PMC_DCDC0_SLICINGENABLE_MASK) - -#define PMC_DCDC0_INDUCTORCLAMPENABLE_MASK (0x400000U) -#define PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT (22U) -/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. - */ -#define PMC_DCDC0_INDUCTORCLAMPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT)) & PMC_DCDC0_INDUCTORCLAMPENABLE_MASK) - -#define PMC_DCDC0_VOUT_PWD_MASK (0x7800000U) -#define PMC_DCDC0_VOUT_PWD_SHIFT (23U) -/*! VOUT_PWD - Set output regulation voltage during Deep Sleep. - */ -#define PMC_DCDC0_VOUT_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_PWD_SHIFT)) & PMC_DCDC0_VOUT_PWD_MASK) -/*! @} */ - -/*! @name DCDC1 - DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_DCDC1_RTRIMOFFET_MASK (0xFU) -#define PMC_DCDC1_RTRIMOFFET_SHIFT (0U) -/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator. - */ -#define PMC_DCDC1_RTRIMOFFET(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RTRIMOFFET_SHIFT)) & PMC_DCDC1_RTRIMOFFET_MASK) - -#define PMC_DCDC1_RSENSETRIM_MASK (0xF0U) -#define PMC_DCDC1_RSENSETRIM_SHIFT (4U) -/*! RSENSETRIM - Adjust Max inductor peak current limiting. - */ -#define PMC_DCDC1_RSENSETRIM(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RSENSETRIM_SHIFT)) & PMC_DCDC1_RSENSETRIM_MASK) - -#define PMC_DCDC1_DTESTENABLE_MASK (0x100U) -#define PMC_DCDC1_DTESTENABLE_SHIFT (8U) -/*! DTESTENABLE - Enable Digital test signals. - */ -#define PMC_DCDC1_DTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTENABLE_SHIFT)) & PMC_DCDC1_DTESTENABLE_MASK) - -#define PMC_DCDC1_SETCURVE_MASK (0x600U) -#define PMC_DCDC1_SETCURVE_SHIFT (9U) -/*! SETCURVE - Bandgap calibration parameter. - */ -#define PMC_DCDC1_SETCURVE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETCURVE_SHIFT)) & PMC_DCDC1_SETCURVE_MASK) - -#define PMC_DCDC1_SETDC_MASK (0x7800U) -#define PMC_DCDC1_SETDC_SHIFT (11U) -/*! SETDC - Bandgap calibration parameter. - */ -#define PMC_DCDC1_SETDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETDC_SHIFT)) & PMC_DCDC1_SETDC_MASK) - -#define PMC_DCDC1_DTESTSEL_MASK (0x38000U) -#define PMC_DCDC1_DTESTSEL_SHIFT (15U) -/*! DTESTSEL - Select the output signal for test. - */ -#define PMC_DCDC1_DTESTSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTSEL_SHIFT)) & PMC_DCDC1_DTESTSEL_MASK) - -#define PMC_DCDC1_ISCALEENABLE_MASK (0x40000U) -#define PMC_DCDC1_ISCALEENABLE_SHIFT (18U) -/*! ISCALEENABLE - Modify COT behavior. - */ -#define PMC_DCDC1_ISCALEENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_ISCALEENABLE_SHIFT)) & PMC_DCDC1_ISCALEENABLE_MASK) - -#define PMC_DCDC1_FORCEBYPASS_MASK (0x80000U) -#define PMC_DCDC1_FORCEBYPASS_SHIFT (19U) -/*! FORCEBYPASS - Force bypass mode. - */ -#define PMC_DCDC1_FORCEBYPASS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEBYPASS_SHIFT)) & PMC_DCDC1_FORCEBYPASS_MASK) - -#define PMC_DCDC1_TRIMAUTOCOT_MASK (0xF00000U) -#define PMC_DCDC1_TRIMAUTOCOT_SHIFT (20U) -/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. - */ -#define PMC_DCDC1_TRIMAUTOCOT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TRIMAUTOCOT_SHIFT)) & PMC_DCDC1_TRIMAUTOCOT_MASK) - -#define PMC_DCDC1_FORCEFULLCYCLE_MASK (0x1000000U) -#define PMC_DCDC1_FORCEFULLCYCLE_SHIFT (24U) -/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. - */ -#define PMC_DCDC1_FORCEFULLCYCLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEFULLCYCLE_SHIFT)) & PMC_DCDC1_FORCEFULLCYCLE_MASK) - -#define PMC_DCDC1_LCENABLE_MASK (0x2000000U) -#define PMC_DCDC1_LCENABLE_SHIFT (25U) -/*! LCENABLE - Change the range of the peak detector of current inside the inductor. - */ -#define PMC_DCDC1_LCENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_LCENABLE_SHIFT)) & PMC_DCDC1_LCENABLE_MASK) - -#define PMC_DCDC1_TOFF_MASK (0x7C000000U) -#define PMC_DCDC1_TOFF_SHIFT (26U) -/*! TOFF - Constant Off-Time calibration input. - */ -#define PMC_DCDC1_TOFF(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFF_SHIFT)) & PMC_DCDC1_TOFF_MASK) - -#define PMC_DCDC1_TOFFENABLE_MASK (0x80000000U) -#define PMC_DCDC1_TOFFENABLE_SHIFT (31U) -/*! TOFFENABLE - Enable Constant Off-Time feature. - */ -#define PMC_DCDC1_TOFFENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFFENABLE_SHIFT)) & PMC_DCDC1_TOFFENABLE_MASK) -/*! @} */ - -/*! @name LDOPMU - Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_LDOPMU_VADJ_MASK (0x1FU) -#define PMC_LDOPMU_VADJ_SHIFT (0U) -/*! VADJ - Sets the Always-On domain LDO output level. - * 0b00000..1.22 V. - * 0b00001..0.7 V. - * 0b00010..0.725 V. - * 0b00011..0.75 V. - * 0b00100..0.775 V. - * 0b00101..0.8 V. - * 0b00110..0.825 V. - * 0b00111..0.85 V. - * 0b01000..0.875 V. - * 0b01001..0.9 V. - * 0b01010..0.96 V. - * 0b01011..0.97 V. - * 0b01100..0.98 V. - * 0b01101..0.99 V. - * 0b01110..1 V. - * 0b01111..1.01 V. - * 0b10000..1.02 V. - * 0b10001..1.03 V. - * 0b10010..1.04 V. - * 0b10011..1.05 V. - * 0b10100..1.06 V. - * 0b10101..1.07 V. - * 0b10110..1.08 V. - * 0b10111..1.09 V. - * 0b11000..1.1 V. - * 0b11001..1.11 V. - * 0b11010..1.12 V. - * 0b11011..1.13 V. - * 0b11100..1.14 V. - * 0b11101..1.15 V. - * 0b11110..1.16 V. - * 0b11111..1.22 V. - */ -#define PMC_LDOPMU_VADJ(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_SHIFT)) & PMC_LDOPMU_VADJ_MASK) - -#define PMC_LDOPMU_VADJ_PWD_MASK (0x3E0U) -#define PMC_LDOPMU_VADJ_PWD_SHIFT (5U) -/*! VADJ_PWD - Sets the Always-On domain LDO output level in all power down modes. - */ -#define PMC_LDOPMU_VADJ_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_PWD_SHIFT)) & PMC_LDOPMU_VADJ_PWD_MASK) - -#define PMC_LDOPMU_VADJ_BOOST_MASK (0x7C00U) -#define PMC_LDOPMU_VADJ_BOOST_SHIFT (10U) -/*! VADJ_BOOST - Sets the Always-On domain LDO Boost output level. - */ -#define PMC_LDOPMU_VADJ_BOOST(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_MASK) - -#define PMC_LDOPMU_VADJ_BOOST_PWD_MASK (0xF8000U) -#define PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT (15U) -/*! VADJ_BOOST_PWD - Sets the Always-On domain LDO Boost output level in all power down modes. - */ -#define PMC_LDOPMU_VADJ_BOOST_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_PWD_MASK) - -#define PMC_LDOPMU_BOOST_ENA_MASK (0x1000000U) -#define PMC_LDOPMU_BOOST_ENA_SHIFT (24U) -/*! BOOST_ENA - Control the LDO AO boost mode in ACTIVE mode. - * 0b0..LDO AO Boost Mode is disable. - * 0b1..LDO AO Boost Mode is enable. - */ -#define PMC_LDOPMU_BOOST_ENA(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_SHIFT)) & PMC_LDOPMU_BOOST_ENA_MASK) - -#define PMC_LDOPMU_BOOST_ENA_PWD_MASK (0x2000000U) -#define PMC_LDOPMU_BOOST_ENA_PWD_SHIFT (25U) -/*! BOOST_ENA_PWD - Control the LDO AO boost mode in the different low power modes (DEEP SLEEP, POWERDOWN, and DEEP POWER DOWN). - * 0b0..LDO AO Boost Mode is disable. - * 0b1..LDO AO Boost Mode is enable. - */ -#define PMC_LDOPMU_BOOST_ENA_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_PWD_SHIFT)) & PMC_LDOPMU_BOOST_ENA_PWD_MASK) -/*! @} */ - -/*! @name BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] */ -/*! @{ */ - -#define PMC_BODVBAT_TRIGLVL_MASK (0x1FU) -#define PMC_BODVBAT_TRIGLVL_SHIFT (0U) -/*! TRIGLVL - BoD trigger level. - * 0b00000..1.00 V. - * 0b00001..1.10 V. - * 0b00010..1.20 V. - * 0b00011..1.30 V. - * 0b00100..1.40 V. - * 0b00101..1.50 V. - * 0b00110..1.60 V. - * 0b00111..1.65 V. - * 0b01000..1.70 V. - * 0b01001..1.75 V. - * 0b01010..1.80 V. - * 0b01011..1.90 V. - * 0b01100..2.00 V. - * 0b01101..2.10 V. - * 0b01110..2.20 V. - * 0b01111..2.30 V. - * 0b10000..2.40 V. - * 0b10001..2.50 V. - * 0b10010..2.60 V. - * 0b10011..2.70 V. - * 0b10100..2.806 V. - * 0b10101..2.90 V. - * 0b10110..3.00 V. - * 0b10111..3.10 V. - * 0b11000..3.20 V. - * 0b11001..3.30 V. - * 0b11010..3.30 V. - * 0b11011..3.30 V. - * 0b11100..3.30 V. - * 0b11101..3.30 V. - * 0b11110..3.30 V. - * 0b11111..3.30 V. - */ -#define PMC_BODVBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_TRIGLVL_SHIFT)) & PMC_BODVBAT_TRIGLVL_MASK) - -#define PMC_BODVBAT_HYST_MASK (0x60U) -#define PMC_BODVBAT_HYST_SHIFT (5U) -/*! HYST - BoD Hysteresis control. - * 0b00..25 mV. - * 0b01..50 mV. - * 0b10..75 mV. - * 0b11..100 mV. - */ -#define PMC_BODVBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK) -/*! @} */ - -/*! @name REFFASTWKUP - Analog References fast wake-up Control register [Reset by: PoR] */ -/*! @{ */ - -#define PMC_REFFASTWKUP_LPWKUP_MASK (0x1U) -#define PMC_REFFASTWKUP_LPWKUP_SHIFT (0U) -/*! LPWKUP - Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP POWER DOWN): . - * 0b0..Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode. - * 0b1..Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode. - */ -#define PMC_REFFASTWKUP_LPWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_LPWKUP_SHIFT)) & PMC_REFFASTWKUP_LPWKUP_MASK) - -#define PMC_REFFASTWKUP_HWWKUP_MASK (0x2U) -#define PMC_REFFASTWKUP_HWWKUP_SHIFT (1U) -/*! HWWKUP - Analog References fast wake-up in case of Hardware Pin reset: . - * 0b0..Analog References fast wake-up feature is disabled in case of Hardware Pin reset. - * 0b1..Analog References fast wake-up feature is enabled in case of Hardware Pin reset. - */ -#define PMC_REFFASTWKUP_HWWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_HWWKUP_SHIFT)) & PMC_REFFASTWKUP_HWWKUP_MASK) -/*! @} */ - -/*! @name XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_XTAL32K_IREF_MASK (0x6U) -#define PMC_XTAL32K_IREF_SHIFT (1U) -/*! IREF - reference output current selection inputs. - */ -#define PMC_XTAL32K_IREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IREF_SHIFT)) & PMC_XTAL32K_IREF_MASK) - -#define PMC_XTAL32K_TEST_MASK (0x8U) -#define PMC_XTAL32K_TEST_SHIFT (3U) -/*! TEST - Oscillator Test Mode. - */ -#define PMC_XTAL32K_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK) - -#define PMC_XTAL32K_IBIAS_MASK (0x30U) -#define PMC_XTAL32K_IBIAS_SHIFT (4U) -/*! IBIAS - bias current selection inputs. - */ -#define PMC_XTAL32K_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IBIAS_SHIFT)) & PMC_XTAL32K_IBIAS_MASK) - -#define PMC_XTAL32K_AMPL_MASK (0xC0U) -#define PMC_XTAL32K_AMPL_SHIFT (6U) -/*! AMPL - oscillator amplitude selection inputs. - */ -#define PMC_XTAL32K_AMPL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_AMPL_SHIFT)) & PMC_XTAL32K_AMPL_MASK) - -#define PMC_XTAL32K_CAPBANKIN_MASK (0x7F00U) -#define PMC_XTAL32K_CAPBANKIN_SHIFT (8U) -/*! CAPBANKIN - Capa bank setting input. - */ -#define PMC_XTAL32K_CAPBANKIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKIN_SHIFT)) & PMC_XTAL32K_CAPBANKIN_MASK) - -#define PMC_XTAL32K_CAPBANKOUT_MASK (0x3F8000U) -#define PMC_XTAL32K_CAPBANKOUT_SHIFT (15U) -/*! CAPBANKOUT - Capa bank setting output. - */ -#define PMC_XTAL32K_CAPBANKOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKOUT_SHIFT)) & PMC_XTAL32K_CAPBANKOUT_MASK) - -#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK (0x400000U) -#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT (22U) -/*! CAPTESTSTARTSRCSEL - Source selection for xo32k_captest_start_ao_set. - * 0b0..Sourced from CAPTESTSTART. - * 0b1..Sourced from calibration. - */ -#define PMC_XTAL32K_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT)) & PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK) - -#define PMC_XTAL32K_CAPTESTSTART_MASK (0x800000U) -#define PMC_XTAL32K_CAPTESTSTART_SHIFT (23U) -/*! CAPTESTSTART - Start test. - */ -#define PMC_XTAL32K_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTART_SHIFT)) & PMC_XTAL32K_CAPTESTSTART_MASK) - -#define PMC_XTAL32K_CAPTESTENABLE_MASK (0x1000000U) -#define PMC_XTAL32K_CAPTESTENABLE_SHIFT (24U) -/*! CAPTESTENABLE - Enable signal for cap test. - */ -#define PMC_XTAL32K_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTENABLE_SHIFT)) & PMC_XTAL32K_CAPTESTENABLE_MASK) - -#define PMC_XTAL32K_CAPTESTOSCINSEL_MASK (0x2000000U) -#define PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT (25U) -/*! CAPTESTOSCINSEL - Select the input for test. - * 0b0..Oscillator output pin (osc_out). - * 0b1..Oscillator input pin (osc_in). - */ -#define PMC_XTAL32K_CAPTESTOSCINSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT)) & PMC_XTAL32K_CAPTESTOSCINSEL_MASK) -/*! @} */ - -/*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_COMP_HYST_MASK (0x2U) -#define PMC_COMP_HYST_SHIFT (1U) -/*! HYST - Hysteris when hyst = '1'. - * 0b0..Hysteresis is disable. - * 0b1..Hysteresis is enable. - */ -#define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK) - -#define PMC_COMP_VREFINPUT_MASK (0x4U) -#define PMC_COMP_VREFINPUT_SHIFT (2U) -/*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). - * 0b0..Select internal VREF. - * 0b1..Select VDDA. - */ -#define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK) - -#define PMC_COMP_LOWPOWER_MASK (0x8U) -#define PMC_COMP_LOWPOWER_SHIFT (3U) -/*! LOWPOWER - Low power mode. - * 0b0..High speed mode. - * 0b1..Low power mode (Low speed). - */ -#define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK) - -#define PMC_COMP_PMUX_MASK (0x70U) -#define PMC_COMP_PMUX_SHIFT (4U) -/*! PMUX - Control word for P multiplexer:. - * 0b000..VREF (See fiedl VREFINPUT). - * 0b001..Pin P0_0. - * 0b010..Pin P0_9. - * 0b011..Pin P0_18. - * 0b100..Pin P1_14. - * 0b101..Pin P2_23. - */ -#define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK) - -#define PMC_COMP_NMUX_MASK (0x380U) -#define PMC_COMP_NMUX_SHIFT (7U) -/*! NMUX - Control word for N multiplexer:. - * 0b000..VREF (See field VREFINPUT). - * 0b001..Pin P0_0. - * 0b010..Pin P0_9. - * 0b011..Pin P0_18. - * 0b100..Pin P1_14. - * 0b101..Pin P2_23. - */ -#define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK) - -#define PMC_COMP_VREF_MASK (0x7C00U) -#define PMC_COMP_VREF_SHIFT (10U) -/*! VREF - Control reference voltage step, per steps of (VREFINPUT/31). - */ -#define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK) - -#define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U) -#define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U) -/*! FILTERCGF_SAMPLEMODE - Control the filtering of the Analog Comparator output. - * 0b00..Bypass mode. - * 0b01..Filter 1 clock period. - * 0b10..Filter 2 clock period. - * 0b11..Filter 3 clock period. - */ -#define PMC_COMP_FILTERCGF_SAMPLEMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK) - -#define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U) -#define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U) -/*! FILTERCGF_CLKDIV - Filter Clock divider. - * 0b000..Filter clock period duration equals 1 Analog Comparator clock period. - * 0b001..Filter clock period duration equals 2 Analog Comparator clock period. - * 0b010..Filter clock period duration equals 4 Analog Comparator clock period. - * 0b011..Filter clock period duration equals 8 Analog Comparator clock period. - * 0b100..Filter clock period duration equals 16 Analog Comparator clock period. - * 0b101..Filter clock period duration equals 32 Analog Comparator clock period. - * 0b110..Filter clock period duration equals 64 Analog Comparator clock period. - * 0b111..Filter clock period duration equals 128 Analog Comparator clock period. - */ -#define PMC_COMP_FILTERCGF_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK) -/*! @} */ - -/*! @name WAKEUPIOCTRL - Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] */ -/*! @{ */ - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK (0x1U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT (0U) -/*! RISINGEDGEWAKEUP0 - Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disable. - * 0b1..Rising edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK (0x2U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT (1U) -/*! FALLINGEDGEWAKEUP0 - Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disable. - * 0b1..Falling edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK) - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK (0x4U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT (2U) -/*! RISINGEDGEWAKEUP1 - Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disable. - * 0b1..Rising edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK (0x8U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT (3U) -/*! FALLINGEDGEWAKEUP1 - Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disable. - * 0b1..Falling edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK) - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK (0x10U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT (4U) -/*! RISINGEDGEWAKEUP2 - Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disable. - * 0b1..Rising edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK (0x20U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT (5U) -/*! FALLINGEDGEWAKEUP2 - Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disable. - * 0b1..Falling edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK) - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK (0x40U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT (6U) -/*! RISINGEDGEWAKEUP3 - Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disable. - * 0b1..Rising edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK (0x80U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT (7U) -/*! FALLINGEDGEWAKEUP3 - Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disable. - * 0b1..Falling edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUP0_MASK (0x100U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUP0_SHIFT (8U) -/*! MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP0_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUP1_MASK (0x200U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUP1_SHIFT (9U) -/*! MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP1_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUP2_MASK (0x400U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUP2_SHIFT (10U) -/*! MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP2_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUP3_MASK (0x800U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUP3_SHIFT (11U) -/*! MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP3_MASK) -/*! @} */ - -/*! @name WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode */ -/*! @{ */ - -#define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U) -#define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U) -/*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0. - */ -#define PMC_WAKEIOCAUSE_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK) - -#define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U) -#define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U) -/*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1. - */ -#define PMC_WAKEIOCAUSE_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK) - -#define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U) -#define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U) -/*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2. - */ -#define PMC_WAKEIOCAUSE_WAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK) - -#define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U) -#define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U) -/*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 3. - */ -#define PMC_WAKEIOCAUSE_WAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK) -/*! @} */ - -/*! @name STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U) -#define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U) -/*! XTAL32KOK - XTAL oscillator 32 K OK signal. - */ -#define PMC_STATUSCLK_XTAL32KOK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK) - -#define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U) -#define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U) -/*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. - * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared. - * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared. - */ -#define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK) -/*! @} */ - -/*! @name AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_AOREG1_POR_MASK (0x10U) -#define PMC_AOREG1_POR_SHIFT (4U) -/*! POR - The last chip reset was caused by a Power On Reset. - */ -#define PMC_AOREG1_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_POR_SHIFT)) & PMC_AOREG1_POR_MASK) - -#define PMC_AOREG1_PADRESET_MASK (0x20U) -#define PMC_AOREG1_PADRESET_SHIFT (5U) -/*! PADRESET - The last chip reset was caused by a Pin Reset. - */ -#define PMC_AOREG1_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_PADRESET_SHIFT)) & PMC_AOREG1_PADRESET_MASK) - -#define PMC_AOREG1_BODRESET_MASK (0x40U) -#define PMC_AOREG1_BODRESET_SHIFT (6U) -/*! BODRESET - The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. - */ -#define PMC_AOREG1_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BODRESET_SHIFT)) & PMC_AOREG1_BODRESET_MASK) - -#define PMC_AOREG1_SYSTEMRESET_MASK (0x80U) -#define PMC_AOREG1_SYSTEMRESET_SHIFT (7U) -/*! SYSTEMRESET - The last chip reset was caused by a System Reset requested by the ARM CPU. - */ -#define PMC_AOREG1_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SYSTEMRESET_SHIFT)) & PMC_AOREG1_SYSTEMRESET_MASK) - -#define PMC_AOREG1_WDTRESET_MASK (0x100U) -#define PMC_AOREG1_WDTRESET_SHIFT (8U) -/*! WDTRESET - The last chip reset was caused by the Watchdog Timer. - */ -#define PMC_AOREG1_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_WDTRESET_SHIFT)) & PMC_AOREG1_WDTRESET_MASK) - -#define PMC_AOREG1_SWRRESET_MASK (0x200U) -#define PMC_AOREG1_SWRRESET_SHIFT (9U) -/*! SWRRESET - The last chip reset was caused by a Software event. - */ -#define PMC_AOREG1_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SWRRESET_SHIFT)) & PMC_AOREG1_SWRRESET_MASK) - -#define PMC_AOREG1_DPDRESET_WAKEUPIO_MASK (0x400U) -#define PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT (10U) -/*! DPDRESET_WAKEUPIO - The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode. - */ -#define PMC_AOREG1_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT)) & PMC_AOREG1_DPDRESET_WAKEUPIO_MASK) - -#define PMC_AOREG1_DPDRESET_RTC_MASK (0x800U) -#define PMC_AOREG1_DPDRESET_RTC_SHIFT (11U) -/*! DPDRESET_RTC - The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode. - */ -#define PMC_AOREG1_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_RTC_SHIFT)) & PMC_AOREG1_DPDRESET_RTC_MASK) - -#define PMC_AOREG1_DPDRESET_OSTIMER_MASK (0x1000U) -#define PMC_AOREG1_DPDRESET_OSTIMER_SHIFT (12U) -/*! DPDRESET_OSTIMER - The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode. - */ -#define PMC_AOREG1_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_OSTIMER_SHIFT)) & PMC_AOREG1_DPDRESET_OSTIMER_MASK) - -#define PMC_AOREG1_BOOTERRORCOUNTER_MASK (0xF0000U) -#define PMC_AOREG1_BOOTERRORCOUNTER_SHIFT (16U) -/*! BOOTERRORCOUNTER - ROM Boot Fatal Error Counter. - */ -#define PMC_AOREG1_BOOTERRORCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BOOTERRORCOUNTER_SHIFT)) & PMC_AOREG1_BOOTERRORCOUNTER_MASK) -/*! @} */ - -/*! @name MISCCTRL - Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_MISCCTRL_LDODEEPSLEEPREF_MASK (0x1U) -#define PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT (0U) -/*! LDODEEPSLEEPREF - Select LDO Deep Sleep reference source. - * 0b0..LDO DEEP Sleep uses Flash buffer biasing as reference. - * 0b1..LDO DEEP Sleep uses Band Gap 0.8V as reference. - */ -#define PMC_MISCCTRL_LDODEEPSLEEPREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT)) & PMC_MISCCTRL_LDODEEPSLEEPREF_MASK) - -#define PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK (0x2U) -#define PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT (1U) -/*! LDOMEMHIGHZMODE - Control the activation of LDO MEM High Z mode. - * 0b0..LDO MEM High Z mode is disabled. - * 0b1..LDO MEM High Z mode is enabled. - */ -#define PMC_MISCCTRL_LDOMEMHIGHZMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT)) & PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK) - -#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK (0x4U) -#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT (2U) -#define PMC_MISCCTRL_LOWPWR_FLASH_BUF(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT)) & PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK) - -#define PMC_MISCCTRL_MISCCTRL_3_8_MASK (0xF8U) -#define PMC_MISCCTRL_MISCCTRL_3_8_SHIFT (3U) -/*! MISCCTRL_3_8 - Reserved. - */ -#define PMC_MISCCTRL_MISCCTRL_3_8(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_3_8_SHIFT)) & PMC_MISCCTRL_MISCCTRL_3_8_MASK) - -#define PMC_MISCCTRL_MODEWAKEUP0_MASK (0x100U) -#define PMC_MISCCTRL_MODEWAKEUP0_SHIFT (8U) -/*! MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode - */ -#define PMC_MISCCTRL_MODEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP0_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP0_MASK) - -#define PMC_MISCCTRL_MODEWAKEUP1_MASK (0x200U) -#define PMC_MISCCTRL_MODEWAKEUP1_SHIFT (9U) -/*! MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode - */ -#define PMC_MISCCTRL_MODEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP1_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP1_MASK) - -#define PMC_MISCCTRL_MODEWAKEUP2_MASK (0x400U) -#define PMC_MISCCTRL_MODEWAKEUP2_SHIFT (10U) -/*! MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode - */ -#define PMC_MISCCTRL_MODEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP2_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP2_MASK) - -#define PMC_MISCCTRL_MODEWAKEUP3_MASK (0x800U) -#define PMC_MISCCTRL_MODEWAKEUP3_SHIFT (11U) -/*! MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode - */ -#define PMC_MISCCTRL_MODEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP3_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP3_MASK) - -#define PMC_MISCCTRL_DISABLE_BLEED_MASK (0x1000U) -#define PMC_MISCCTRL_DISABLE_BLEED_SHIFT (12U) -/*! DISABLE_BLEED - Controls LDO MEM bleed current. This field is expected to be controlled by the - * Low Power Software only in DEEP SLEEP low power mode. - * 0b0..LDO_MEM bleed current is enabled. - * 0b1..LDO_MEM bleed current is disabled. Should be set before entering in Deep Sleep low power mode and cleared - * after wake up from Deep SLeep low power mode. - */ -#define PMC_MISCCTRL_DISABLE_BLEED(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_DISABLE_BLEED_SHIFT)) & PMC_MISCCTRL_DISABLE_BLEED_MASK) - -#define PMC_MISCCTRL_MISCCTRL_13_14_MASK (0x6000U) -#define PMC_MISCCTRL_MISCCTRL_13_14_SHIFT (13U) -/*! MISCCTRL_13_14 - Reserved. - */ -#define PMC_MISCCTRL_MISCCTRL_13_14(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_13_14_SHIFT)) & PMC_MISCCTRL_MISCCTRL_13_14_MASK) - -#define PMC_MISCCTRL_WAKUPIO_RST_MASK (0x8000U) -#define PMC_MISCCTRL_WAKUPIO_RST_SHIFT (15U) -/*! WAKUPIO_RST - WAKEUP IO event detector reset control. - * 0b1..Wakeup IO is reset. - * 0b0..Wakeup IO is not reset. - */ -#define PMC_MISCCTRL_WAKUPIO_RST(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_WAKUPIO_RST_SHIFT)) & PMC_MISCCTRL_WAKUPIO_RST_MASK) -/*! @} */ - -/*! @name RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_RTCOSC32K_SEL_MASK (0x1U) -#define PMC_RTCOSC32K_SEL_SHIFT (0U) -/*! SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . - * 0b0..FRO 32 KHz. - * 0b1..XTAL 32KHz. - */ -#define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK) - -#define PMC_RTCOSC32K_CLK1KHZDIV_MASK (0xEU) -#define PMC_RTCOSC32K_CLK1KHZDIV_SHIFT (1U) -/*! CLK1KHZDIV - Actual division ratio is : 28 + CLK1KHZDIV. - */ -#define PMC_RTCOSC32K_CLK1KHZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIV_MASK) - -#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK (0x8000U) -#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT (15U) -/*! CLK1KHZDIVUPDATEREQ - RTC 1KHz clock Divider status flag. - */ -#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK) - -#define PMC_RTCOSC32K_CLK1HZDIV_MASK (0x7FF0000U) -#define PMC_RTCOSC32K_CLK1HZDIV_SHIFT (16U) -/*! CLK1HZDIV - Actual division ratio is : 31744 + CLK1HZDIV. - */ -#define PMC_RTCOSC32K_CLK1HZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIV_MASK) - -#define PMC_RTCOSC32K_CLK1HZDIVHALT_MASK (0x40000000U) -#define PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT (30U) -/*! CLK1HZDIVHALT - Halts the divider counter. - */ -#define PMC_RTCOSC32K_CLK1HZDIVHALT(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVHALT_MASK) - -#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK (0x80000000U) -#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT (31U) -/*! CLK1HZDIVUPDATEREQ - RTC 1Hz Divider status flag. - */ -#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK) -/*! @} */ - -/*! @name OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_OSTIMER_SOFTRESET_MASK (0x1U) -#define PMC_OSTIMER_SOFTRESET_SHIFT (0U) -/*! SOFTRESET - Active high reset. - */ -#define PMC_OSTIMER_SOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_SOFTRESET_SHIFT)) & PMC_OSTIMER_SOFTRESET_MASK) - -#define PMC_OSTIMER_CLOCKENABLE_MASK (0x2U) -#define PMC_OSTIMER_CLOCKENABLE_SHIFT (1U) -/*! CLOCKENABLE - Enable OSTIMER 32 KHz clock. - */ -#define PMC_OSTIMER_CLOCKENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_CLOCKENABLE_SHIFT)) & PMC_OSTIMER_CLOCKENABLE_MASK) - -#define PMC_OSTIMER_DPDWAKEUPENABLE_MASK (0x4U) -#define PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT (2U) -/*! DPDWAKEUPENABLE - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode). - */ -#define PMC_OSTIMER_DPDWAKEUPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSTIMER_DPDWAKEUPENABLE_MASK) - -#define PMC_OSTIMER_OSC32KPD_MASK (0x8U) -#define PMC_OSTIMER_OSC32KPD_SHIFT (3U) -/*! OSC32KPD - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K. - */ -#define PMC_OSTIMER_OSC32KPD(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSC32KPD_SHIFT)) & PMC_OSTIMER_OSC32KPD_MASK) -/*! @} */ - -/*! @name PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_PDRUNCFG0_PDEN_BODVBAT_MASK (0x8U) -#define PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT (3U) -/*! PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD). - * 0b0..BOD VBAT is powered. - * 0b1..BOD VBAT is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVBAT_MASK) - -#define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U) -#define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U) -/*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. - * 0b0..FRO32KHz is powered. - * 0b1..FRO32KHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK) - -#define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U) -#define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U) -/*! PDEN_XTAL32K - Controls power to crystal 32 KHz. - * 0b0..Crystal 32KHz is powered. - * 0b1..Crystal 32KHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK) - -#define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK (0x100U) -#define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT (8U) -/*! PDEN_XTAL32M - Controls power to high speed crystal. - * 0b0..High speed crystal is powered. - * 0b1..High speed crystal is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK) - -#define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U) -#define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U) -/*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). - * 0b0..PLL0 is powered. - * 0b1..PLL0 is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK) - -#define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U) -#define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U) -/*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1). - * 0b0..PLL1 is powered. - * 0b1..PLL1 is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK) - -#define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK (0x800U) -#define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT (11U) -/*! PDEN_USBFSPHY - Controls power to USB Full Speed phy. - * 0b0..USB Full Speed phy is powered. - * 0b1..USB Full Speed phy is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK) - -#define PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK (0x1000U) -#define PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT (12U) -/*! PDEN_USBHSPHY - Controls power to USB High Speed Phy. - * 0b0..USB HS phy is powered. - * 0b1..USB HS phy is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK) - -#define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U) -#define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U) -/*! PDEN_COMP - Controls power to Analog Comparator. - * 0b0..Analog Comparator is powered. - * 0b1..Analog Comparator is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK) - -#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK (0x40000U) -#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT (18U) -/*! PDEN_LDOUSBHS - Controls power to USB high speed LDO. - * 0b0..USB high speed LDO is powered. - * 0b1..USB high speed LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK) - -#define PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK (0x80000U) -#define PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT (19U) -/*! PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS) - * 0b0..auxiliary biasing is powered. - * 0b1..auxiliary biasing is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK) - -#define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK (0x100000U) -#define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT (20U) -/*! PDEN_LDOXO32M - Controls power to high speed crystal LDO. - * 0b0..High speed crystal LDO is powered. - * 0b1..High speed crystal LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK) - -#define PMC_PDRUNCFG0_PDEN_RNG_MASK (0x400000U) -#define PMC_PDRUNCFG0_PDEN_RNG_SHIFT (22U) -/*! PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources. - * 0b0..TRNG clocks are powered. - * 0b1..TRNG clocks are powered down. - */ -#define PMC_PDRUNCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_RNG_SHIFT)) & PMC_PDRUNCFG0_PDEN_RNG_MASK) - -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U) -/*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. - * 0b0..PLL0 Sread spectrum module is powered. - * 0b1..PLL0 Sread spectrum module is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) -/*! @} */ - -/*! @name PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU) -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U) -/*! PDRUNCFGSET0 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. - */ -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK) -/*! @} */ - -/*! @name PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU) -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U) -/*! PDRUNCFGCLR0 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. - */ -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK) -/*! @} */ - -/*! @name SRAMCTRL - All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ -/*! @{ */ - -#define PMC_SRAMCTRL_SMB_MASK (0x3U) -#define PMC_SRAMCTRL_SMB_SHIFT (0U) -/*! SMB - Source Biasing voltage. - * 0b00..Low leakage. - * 0b01..Medium leakage. - * 0b10..Highest leakage. - * 0b11..Disable. - */ -#define PMC_SRAMCTRL_SMB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_SMB_SHIFT)) & PMC_SRAMCTRL_SMB_MASK) - -#define PMC_SRAMCTRL_RM_MASK (0x1CU) -#define PMC_SRAMCTRL_RM_SHIFT (2U) -/*! RM - Read Margin control settings. - */ -#define PMC_SRAMCTRL_RM(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_RM_SHIFT)) & PMC_SRAMCTRL_RM_MASK) - -#define PMC_SRAMCTRL_WM_MASK (0xE0U) -#define PMC_SRAMCTRL_WM_SHIFT (5U) -/*! WM - Write Margin control settings. - */ -#define PMC_SRAMCTRL_WM(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WM_SHIFT)) & PMC_SRAMCTRL_WM_MASK) - -#define PMC_SRAMCTRL_WRME_MASK (0x100U) -#define PMC_SRAMCTRL_WRME_SHIFT (8U) -/*! WRME - Write read margin enable. - */ -#define PMC_SRAMCTRL_WRME(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WRME_SHIFT)) & PMC_SRAMCTRL_WRME_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PMC_Register_Masks */ - - -/* PMC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PMC base address */ - #define PMC_BASE (0x50020000u) - /** Peripheral PMC base address */ - #define PMC_BASE_NS (0x40020000u) - /** Peripheral PMC base pointer */ - #define PMC ((PMC_Type *)PMC_BASE) - /** Peripheral PMC base pointer */ - #define PMC_NS ((PMC_Type *)PMC_BASE_NS) - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS { PMC_BASE } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS { PMC } - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS_NS { PMC_BASE_NS } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS_NS { PMC_NS } -#else - /** Peripheral PMC base address */ - #define PMC_BASE (0x40020000u) - /** Peripheral PMC base pointer */ - #define PMC ((PMC_Type *)PMC_BASE) - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS { PMC_BASE } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS { PMC } -#endif - -/*! - * @} - */ /* end of group PMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- POWERQUAD Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup POWERQUAD_Peripheral_Access_Layer POWERQUAD Peripheral Access Layer - * @{ - */ - -/** POWERQUAD - Register Layout Typedef */ -typedef struct { - __IO uint32_t OUTBASE; /**< Base address register for output region, offset: 0x0 */ - __IO uint32_t OUTFORMAT; /**< Output format, offset: 0x4 */ - __IO uint32_t TMPBASE; /**< Base address register for temp region, offset: 0x8 */ - __IO uint32_t TMPFORMAT; /**< Temp format, offset: 0xC */ - __IO uint32_t INABASE; /**< Base address register for input A region, offset: 0x10 */ - __IO uint32_t INAFORMAT; /**< Input A format, offset: 0x14 */ - __IO uint32_t INBBASE; /**< Base address register for input B region, offset: 0x18 */ - __IO uint32_t INBFORMAT; /**< Input B format, offset: 0x1C */ - uint8_t RESERVED_0[224]; - __IO uint32_t CONTROL; /**< PowerQuad Control register, offset: 0x100 */ - __IO uint32_t LENGTH; /**< Length register, offset: 0x104 */ - __IO uint32_t CPPRE; /**< Pre-scale register, offset: 0x108 */ - __IO uint32_t MISC; /**< Misc register, offset: 0x10C */ - __IO uint32_t CURSORY; /**< Cursory register, offset: 0x110 */ - uint8_t RESERVED_1[108]; - __IO uint32_t CORDIC_X; /**< Cordic input X register, offset: 0x180 */ - __IO uint32_t CORDIC_Y; /**< Cordic input Y register, offset: 0x184 */ - __IO uint32_t CORDIC_Z; /**< Cordic input Z register, offset: 0x188 */ - __IO uint32_t ERRSTAT; /**< Read/Write register where error statuses are captured (sticky), offset: 0x18C */ - __IO uint32_t INTREN; /**< INTERRUPT enable register, offset: 0x190 */ - __IO uint32_t EVENTEN; /**< Event Enable register, offset: 0x194 */ - __IO uint32_t INTRSTAT; /**< INTERRUPT STATUS register, offset: 0x198 */ - uint8_t RESERVED_2[100]; - __IO uint32_t GPREG[16]; /**< General purpose register bank N., array offset: 0x200, array step: 0x4 */ - __IO uint32_t COMPREG[8]; /**< Compute register bank, array offset: 0x240, array step: 0x4 */ -} POWERQUAD_Type; - -/* ---------------------------------------------------------------------------- - -- POWERQUAD Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup POWERQUAD_Register_Masks POWERQUAD Register Masks - * @{ - */ - -/*! @name OUTBASE - Base address register for output region */ -/*! @{ */ - -#define POWERQUAD_OUTBASE_OUTBASE_MASK (0xFFFFFFFFU) -#define POWERQUAD_OUTBASE_OUTBASE_SHIFT (0U) -/*! outbase - Base address register for the output region - */ -#define POWERQUAD_OUTBASE_OUTBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK) -/*! @} */ - -/*! @name OUTFORMAT - Output format */ -/*! @{ */ - -#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK (0x3U) -#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT (0U) -/*! out_formatint - Output Internal format (00: q15; 01:q31; 10:float) - */ -#define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK) - -#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK (0x30U) -#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT (4U) -/*! out_formatext - Output External format (00: q15; 01:q31; 10:float) - */ -#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK) - -#define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK (0xFF00U) -#define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT (8U) -/*! out_scaler - Output Scaler value (for scaled 'q31' formats) - */ -#define POWERQUAD_OUTFORMAT_OUT_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK) -/*! @} */ - -/*! @name TMPBASE - Base address register for temp region */ -/*! @{ */ - -#define POWERQUAD_TMPBASE_TMPBASE_MASK (0xFFFFFFFFU) -#define POWERQUAD_TMPBASE_TMPBASE_SHIFT (0U) -/*! tmpbase - Base address register for the temporary region - */ -#define POWERQUAD_TMPBASE_TMPBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK) -/*! @} */ - -/*! @name TMPFORMAT - Temp format */ -/*! @{ */ - -#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK (0x3U) -#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT (0U) -/*! tmp_formatint - Temp Internal format (00: q15; 01:q31; 10:float) - */ -#define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK) - -#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK (0x30U) -#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT (4U) -/*! tmp_formatext - Temp External format (00: q15; 01:q31; 10:float) - */ -#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK) - -#define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK (0xFF00U) -#define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT (8U) -/*! tmp_scaler - Temp Scaler value (for scaled 'q31' formats) - */ -#define POWERQUAD_TMPFORMAT_TMP_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK) -/*! @} */ - -/*! @name INABASE - Base address register for input A region */ -/*! @{ */ - -#define POWERQUAD_INABASE_INABASE_MASK (0xFFFFFFFFU) -#define POWERQUAD_INABASE_INABASE_SHIFT (0U) -/*! inabase - Base address register for the input A region - */ -#define POWERQUAD_INABASE_INABASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK) -/*! @} */ - -/*! @name INAFORMAT - Input A format */ -/*! @{ */ - -#define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK (0x3U) -#define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT (0U) -/*! ina_formatint - Input A Internal format (00: q15; 01:q31; 10:float) - */ -#define POWERQUAD_INAFORMAT_INA_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK) - -#define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK (0x30U) -#define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT (4U) -/*! ina_formatext - Input A External format (00: q15; 01:q31; 10:float) - */ -#define POWERQUAD_INAFORMAT_INA_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK) - -#define POWERQUAD_INAFORMAT_INA_SCALER_MASK (0xFF00U) -#define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT (8U) -/*! ina_scaler - Input A Scaler value (for scaled 'q31' formats) - */ -#define POWERQUAD_INAFORMAT_INA_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK) -/*! @} */ - -/*! @name INBBASE - Base address register for input B region */ -/*! @{ */ - -#define POWERQUAD_INBBASE_INBBASE_MASK (0xFFFFFFFFU) -#define POWERQUAD_INBBASE_INBBASE_SHIFT (0U) -/*! inbbase - Base address register for the input B region - */ -#define POWERQUAD_INBBASE_INBBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK) -/*! @} */ - -/*! @name INBFORMAT - Input B format */ -/*! @{ */ - -#define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK (0x3U) -#define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT (0U) -/*! inb_formatint - Input B Internal format (00: q15; 01:q31; 10:float) - */ -#define POWERQUAD_INBFORMAT_INB_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK) - -#define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK (0x30U) -#define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT (4U) -/*! inb_formatext - Input B External format (00: q15; 01:q31; 10:float) - */ -#define POWERQUAD_INBFORMAT_INB_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK) - -#define POWERQUAD_INBFORMAT_INB_SCALER_MASK (0xFF00U) -#define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT (8U) -/*! inb_scaler - Input B Scaler value (for scaled 'q31' formats) - */ -#define POWERQUAD_INBFORMAT_INB_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK) -/*! @} */ - -/*! @name CONTROL - PowerQuad Control register */ -/*! @{ */ - -#define POWERQUAD_CONTROL_DECODE_OPCODE_MASK (0xFU) -#define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT (0U) -/*! decode_opcode - opcode specific to decode_machine - */ -#define POWERQUAD_CONTROL_DECODE_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK) - -#define POWERQUAD_CONTROL_DECODE_MACHINE_MASK (0xF0U) -#define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT (4U) -/*! decode_machine - 0 : Coprocessor , 1 : matrix , 2 : fft , 3 : fir , 4 : stat , 5 : cordic , 6 -15 : NA - */ -#define POWERQUAD_CONTROL_DECODE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK) - -#define POWERQUAD_CONTROL_INST_BUSY_MASK (0x80000000U) -#define POWERQUAD_CONTROL_INST_BUSY_SHIFT (31U) -/*! inst_busy - Instruction busy signal when high indicates processing is on - */ -#define POWERQUAD_CONTROL_INST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK) -/*! @} */ - -/*! @name LENGTH - Length register */ -/*! @{ */ - -#define POWERQUAD_LENGTH_INST_LENGTH_MASK (0xFFFFFFFFU) -#define POWERQUAD_LENGTH_INST_LENGTH_SHIFT (0U) -/*! inst_length - Length register. When FIR : fir_xlength = inst_length[15:0] , fir_tlength = - * inst_len[31:16]. When MTX : rows_a = inst_length[4:0] , cols_a = inst_length[12:8] , cols_b = - * inst_length[20:16] - */ -#define POWERQUAD_LENGTH_INST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK) -/*! @} */ - -/*! @name CPPRE - Pre-scale register */ -/*! @{ */ - -#define POWERQUAD_CPPRE_CPPRE_IN_MASK (0xFFU) -#define POWERQUAD_CPPRE_CPPRE_IN_SHIFT (0U) -/*! cppre_in - co-processor scaling of input - */ -#define POWERQUAD_CPPRE_CPPRE_IN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK) - -#define POWERQUAD_CPPRE_CPPRE_OUT_MASK (0xFF00U) -#define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT (8U) -/*! cppre_out - co-processor fixed point output - */ -#define POWERQUAD_CPPRE_CPPRE_OUT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK) - -#define POWERQUAD_CPPRE_CPPRE_SAT_MASK (0x10000U) -#define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT (16U) -/*! cppre_sat - 1 : forces sub-32 bit saturation - */ -#define POWERQUAD_CPPRE_CPPRE_SAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK) - -#define POWERQUAD_CPPRE_CPPRE_SAT8_MASK (0x20000U) -#define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT (17U) -/*! cppre_sat8 - 0 = 8bits, 1 = 16bits - */ -#define POWERQUAD_CPPRE_CPPRE_SAT8(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK) -/*! @} */ - -/*! @name MISC - Misc register */ -/*! @{ */ - -#define POWERQUAD_MISC_INST_MISC_MASK (0xFFFFFFFFU) -#define POWERQUAD_MISC_INST_MISC_SHIFT (0U) -/*! inst_misc - Misc register. For Matrix : Used for scale factor - */ -#define POWERQUAD_MISC_INST_MISC(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK) -/*! @} */ - -/*! @name CURSORY - Cursory register */ -/*! @{ */ - -#define POWERQUAD_CURSORY_CURSORY_MASK (0x1U) -#define POWERQUAD_CURSORY_CURSORY_SHIFT (0U) -/*! cursory - 1 : Enable cursory mode - */ -#define POWERQUAD_CURSORY_CURSORY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK) -/*! @} */ - -/*! @name CORDIC_X - Cordic input X register */ -/*! @{ */ - -#define POWERQUAD_CORDIC_X_CORDIC_X_MASK (0xFFFFFFFFU) -#define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT (0U) -/*! cordic_x - Cordic input x - */ -#define POWERQUAD_CORDIC_X_CORDIC_X(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK) -/*! @} */ - -/*! @name CORDIC_Y - Cordic input Y register */ -/*! @{ */ - -#define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK (0xFFFFFFFFU) -#define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT (0U) -/*! cordic_y - Cordic input y - */ -#define POWERQUAD_CORDIC_Y_CORDIC_Y(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK) -/*! @} */ - -/*! @name CORDIC_Z - Cordic input Z register */ -/*! @{ */ - -#define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK (0xFFFFFFFFU) -#define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT (0U) -/*! cordic_z - Cordic input z - */ -#define POWERQUAD_CORDIC_Z_CORDIC_Z(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK) -/*! @} */ - -/*! @name ERRSTAT - Read/Write register where error statuses are captured (sticky) */ -/*! @{ */ - -#define POWERQUAD_ERRSTAT_OVERFLOW_MASK (0x1U) -#define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT (0U) -/*! OVERFLOW - overflow - */ -#define POWERQUAD_ERRSTAT_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK) - -#define POWERQUAD_ERRSTAT_NAN_MASK (0x2U) -#define POWERQUAD_ERRSTAT_NAN_SHIFT (1U) -/*! NAN - nan - */ -#define POWERQUAD_ERRSTAT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK) - -#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK (0x4U) -#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT (2U) -/*! FIXEDOVERFLOW - fixed_pt_overflow - */ -#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK) - -#define POWERQUAD_ERRSTAT_UNDERFLOW_MASK (0x8U) -#define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT (3U) -/*! UNDERFLOW - underflow - */ -#define POWERQUAD_ERRSTAT_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK) - -#define POWERQUAD_ERRSTAT_BUSERROR_MASK (0x10U) -#define POWERQUAD_ERRSTAT_BUSERROR_SHIFT (4U) -/*! BUSERROR - bus_error - */ -#define POWERQUAD_ERRSTAT_BUSERROR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK) -/*! @} */ - -/*! @name INTREN - INTERRUPT enable register */ -/*! @{ */ - -#define POWERQUAD_INTREN_INTR_OFLOW_MASK (0x1U) -#define POWERQUAD_INTREN_INTR_OFLOW_SHIFT (0U) -/*! intr_oflow - 1 : Enable interrupt on Floating point overflow - */ -#define POWERQUAD_INTREN_INTR_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK) - -#define POWERQUAD_INTREN_INTR_NAN_MASK (0x2U) -#define POWERQUAD_INTREN_INTR_NAN_SHIFT (1U) -/*! intr_nan - 1 : Enable interrupt on Floating point NaN - */ -#define POWERQUAD_INTREN_INTR_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK) - -#define POWERQUAD_INTREN_INTR_FIXED_MASK (0x4U) -#define POWERQUAD_INTREN_INTR_FIXED_SHIFT (2U) -/*! intr_fixed - 1: Enable interrupt on Fixed point Overflow - */ -#define POWERQUAD_INTREN_INTR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK) - -#define POWERQUAD_INTREN_INTR_UFLOW_MASK (0x8U) -#define POWERQUAD_INTREN_INTR_UFLOW_SHIFT (3U) -/*! intr_uflow - 1 : Enable interrupt on Subnormal truncation - */ -#define POWERQUAD_INTREN_INTR_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK) - -#define POWERQUAD_INTREN_INTR_BERR_MASK (0x10U) -#define POWERQUAD_INTREN_INTR_BERR_SHIFT (4U) -/*! intr_berr - 1: Enable interrupt on AHBM Buss Error - */ -#define POWERQUAD_INTREN_INTR_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK) - -#define POWERQUAD_INTREN_INTR_COMP_MASK (0x80U) -#define POWERQUAD_INTREN_INTR_COMP_SHIFT (7U) -/*! intr_comp - 1: Enable interrupt on instruction completion - */ -#define POWERQUAD_INTREN_INTR_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK) -/*! @} */ - -/*! @name EVENTEN - Event Enable register */ -/*! @{ */ - -#define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK (0x1U) -#define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT (0U) -/*! event_oflow - 1 : Enable event trigger on Floating point overflow - */ -#define POWERQUAD_EVENTEN_EVENT_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK) - -#define POWERQUAD_EVENTEN_EVENT_NAN_MASK (0x2U) -#define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT (1U) -/*! event_nan - 1 : Enable event trigger on Floating point NaN - */ -#define POWERQUAD_EVENTEN_EVENT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK) - -#define POWERQUAD_EVENTEN_EVENT_FIXED_MASK (0x4U) -#define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT (2U) -/*! event_fixed - 1: Enable event trigger on Fixed point Overflow - */ -#define POWERQUAD_EVENTEN_EVENT_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK) - -#define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK (0x8U) -#define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT (3U) -/*! event_uflow - 1 : Enable event trigger on Subnormal truncation - */ -#define POWERQUAD_EVENTEN_EVENT_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK) - -#define POWERQUAD_EVENTEN_EVENT_BERR_MASK (0x10U) -#define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT (4U) -/*! event_berr - 1: Enable event trigger on AHBM Buss Error - */ -#define POWERQUAD_EVENTEN_EVENT_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK) - -#define POWERQUAD_EVENTEN_EVENT_COMP_MASK (0x80U) -#define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT (7U) -/*! event_comp - 1: Enable event trigger on instruction completion - */ -#define POWERQUAD_EVENTEN_EVENT_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK) -/*! @} */ - -/*! @name INTRSTAT - INTERRUPT STATUS register */ -/*! @{ */ - -#define POWERQUAD_INTRSTAT_INTR_STAT_MASK (0x1U) -#define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT (0U) -/*! intr_stat - Intr status ( 1 bit to indicate interrupt captured, 0 means no new interrupt), write any value will clear this bit - */ -#define POWERQUAD_INTRSTAT_INTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK) -/*! @} */ - -/*! @name GPREG - General purpose register bank N. */ -/*! @{ */ - -#define POWERQUAD_GPREG_GPREG_MASK (0xFFFFFFFFU) -#define POWERQUAD_GPREG_GPREG_SHIFT (0U) -/*! gpreg - General purpose register bank - */ -#define POWERQUAD_GPREG_GPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK) -/*! @} */ - -/* The count of POWERQUAD_GPREG */ -#define POWERQUAD_GPREG_COUNT (16U) - -/*! @name COMPREGS_COMPREG - Compute register bank */ -/*! @{ */ - -#define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK (0xFFFFFFFFU) -#define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U) -/*! compreg - Compute register bank - */ -#define POWERQUAD_COMPREGS_COMPREG_COMPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK) -/*! @} */ - -/* The count of POWERQUAD_COMPREGS_COMPREG */ -#define POWERQUAD_COMPREGS_COMPREG_COUNT (8U) - - -/*! - * @} - */ /* end of group POWERQUAD_Register_Masks */ - - -/* POWERQUAD - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral POWERQUAD base address */ - #define POWERQUAD_BASE (0x500A6000u) - /** Peripheral POWERQUAD base address */ - #define POWERQUAD_BASE_NS (0x400A6000u) - /** Peripheral POWERQUAD base pointer */ - #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) - /** Peripheral POWERQUAD base pointer */ - #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) - /** Array initializer of POWERQUAD peripheral base addresses */ - #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } - /** Array initializer of POWERQUAD peripheral base pointers */ - #define POWERQUAD_BASE_PTRS { POWERQUAD } - /** Array initializer of POWERQUAD peripheral base addresses */ - #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } - /** Array initializer of POWERQUAD peripheral base pointers */ - #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } -#else - /** Peripheral POWERQUAD base address */ - #define POWERQUAD_BASE (0x400A6000u) - /** Peripheral POWERQUAD base pointer */ - #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) - /** Array initializer of POWERQUAD peripheral base addresses */ - #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } - /** Array initializer of POWERQUAD peripheral base pointers */ - #define POWERQUAD_BASE_PTRS { POWERQUAD } -#endif - -/*! - * @} - */ /* end of group POWERQUAD_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PRINCE Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PRINCE_Peripheral_Access_Layer PRINCE Peripheral Access Layer - * @{ - */ - -/** PRINCE - Register Layout Typedef */ -typedef struct { - __IO uint32_t ENC_ENABLE; /**< Encryption Enable register, offset: 0x0 */ - __O uint32_t MASK_LSB; /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */ - __O uint32_t MASK_MSB; /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */ - __IO uint32_t LOCK; /**< Lock register, offset: 0xC */ - __O uint32_t IV_LSB0; /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */ - __O uint32_t IV_MSB0; /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */ - __IO uint32_t BASE_ADDR0; /**< Base Address for region 0 register, offset: 0x18 */ - __IO uint32_t SR_ENABLE0; /**< Sub-Region Enable register for region 0, offset: 0x1C */ - __O uint32_t IV_LSB1; /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */ - __O uint32_t IV_MSB1; /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */ - __IO uint32_t BASE_ADDR1; /**< Base Address for region 1 register, offset: 0x28 */ - __IO uint32_t SR_ENABLE1; /**< Sub-Region Enable register for region 1, offset: 0x2C */ - __O uint32_t IV_LSB2; /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */ - __O uint32_t IV_MSB2; /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */ - __IO uint32_t BASE_ADDR2; /**< Base Address for region 2 register, offset: 0x38 */ - __IO uint32_t SR_ENABLE2; /**< Sub-Region Enable register for region 2, offset: 0x3C */ -} PRINCE_Type; - -/* ---------------------------------------------------------------------------- - -- PRINCE Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PRINCE_Register_Masks PRINCE Register Masks - * @{ - */ - -/*! @name ENC_ENABLE - Encryption Enable register */ -/*! @{ */ - -#define PRINCE_ENC_ENABLE_EN_MASK (0x1U) -#define PRINCE_ENC_ENABLE_EN_SHIFT (0U) -/*! EN - Encryption Enable. - * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled. - * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled. - */ -#define PRINCE_ENC_ENABLE_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK) -/*! @} */ - -/*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */ -/*! @{ */ - -#define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU) -#define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U) -/*! MASKVAL - Value of the 32 Least Significant Bits of the 64-bit data mask. - */ -#define PRINCE_MASK_LSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK) -/*! @} */ - -/*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */ -/*! @{ */ - -#define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU) -#define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U) -/*! MASKVAL - Value of the 32 Most Significant Bits of the 64-bit data mask. - */ -#define PRINCE_MASK_MSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK) -/*! @} */ - -/*! @name LOCK - Lock register */ -/*! @{ */ - -#define PRINCE_LOCK_LOCKREG0_MASK (0x1U) -#define PRINCE_LOCK_LOCKREG0_SHIFT (0U) -/*! LOCKREG0 - Lock Region 0 registers. - * 0b0..Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. - * 0b1..Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. - */ -#define PRINCE_LOCK_LOCKREG0(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK) - -#define PRINCE_LOCK_LOCKREG1_MASK (0x2U) -#define PRINCE_LOCK_LOCKREG1_SHIFT (1U) -/*! LOCKREG1 - Lock Region 1 registers. - * 0b0..Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. - * 0b1..Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. - */ -#define PRINCE_LOCK_LOCKREG1(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK) - -#define PRINCE_LOCK_LOCKREG2_MASK (0x4U) -#define PRINCE_LOCK_LOCKREG2_SHIFT (2U) -/*! LOCKREG2 - Lock Region 2 registers. - * 0b0..Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. - * 0b1..Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. - */ -#define PRINCE_LOCK_LOCKREG2(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK) - -#define PRINCE_LOCK_LOCKMASK_MASK (0x100U) -#define PRINCE_LOCK_LOCKMASK_SHIFT (8U) -/*! LOCKMASK - Lock the Mask registers. - * 0b0..Disabled. MASK_LSB, and MASK_MSB are writable.. - * 0b1..Enabled. MASK_LSB, and MASK_MSB are not writable.. - */ -#define PRINCE_LOCK_LOCKMASK(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK) -/*! @} */ - -/*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB0_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_LSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB0_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_MSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR0 - Base Address for region 0 register */ -/*! @{ */ - -#define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U) -/*! ADDR_FIXED - Fixed portion of the base address of region 0. - */ -#define PRINCE_BASE_ADDR0_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK) - -#define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U) -/*! ADDR_PRG - Programmable portion of the base address of region 0. - */ -#define PRINCE_BASE_ADDR0_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */ -/*! @{ */ - -#define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE0_EN_SHIFT (0U) -/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0. - */ -#define PRINCE_SR_ENABLE0_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK) -/*! @} */ - -/*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB1_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_LSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB1_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_MSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR1 - Base Address for region 1 register */ -/*! @{ */ - -#define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U) -/*! ADDR_FIXED - Fixed portion of the base address of region 1. - */ -#define PRINCE_BASE_ADDR1_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK) - -#define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U) -/*! ADDR_PRG - Programmable portion of the base address of region 1. - */ -#define PRINCE_BASE_ADDR1_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */ -/*! @{ */ - -#define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE1_EN_SHIFT (0U) -/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1. - */ -#define PRINCE_SR_ENABLE1_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK) -/*! @} */ - -/*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB2_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_LSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB2_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_MSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR2 - Base Address for region 2 register */ -/*! @{ */ - -#define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U) -/*! ADDR_FIXED - Fixed portion of the base address of region 2. - */ -#define PRINCE_BASE_ADDR2_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK) - -#define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U) -/*! ADDR_PRG - Programmable portion of the base address of region 2. - */ -#define PRINCE_BASE_ADDR2_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */ -/*! @{ */ - -#define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE2_EN_SHIFT (0U) -/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2. - */ -#define PRINCE_SR_ENABLE2_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PRINCE_Register_Masks */ - - -/* PRINCE - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PRINCE base address */ - #define PRINCE_BASE (0x50035000u) - /** Peripheral PRINCE base address */ - #define PRINCE_BASE_NS (0x40035000u) - /** Peripheral PRINCE base pointer */ - #define PRINCE ((PRINCE_Type *)PRINCE_BASE) - /** Peripheral PRINCE base pointer */ - #define PRINCE_NS ((PRINCE_Type *)PRINCE_BASE_NS) - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS { PRINCE_BASE } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS { PRINCE } - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS_NS { PRINCE_BASE_NS } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS_NS { PRINCE_NS } -#else - /** Peripheral PRINCE base address */ - #define PRINCE_BASE (0x40035000u) - /** Peripheral PRINCE base pointer */ - #define PRINCE ((PRINCE_Type *)PRINCE_BASE) - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS { PRINCE_BASE } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS { PRINCE } -#endif - -/*! - * @} - */ /* end of group PRINCE_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PUF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer - * @{ - */ - -/** PUF - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< PUF Control register, offset: 0x0 */ - __IO uint32_t KEYINDEX; /**< PUF Key Index register, offset: 0x4 */ - __IO uint32_t KEYSIZE; /**< PUF Key Size register, offset: 0x8 */ - uint8_t RESERVED_0[20]; - __I uint32_t STAT; /**< PUF Status register, offset: 0x20 */ - uint8_t RESERVED_1[4]; - __I uint32_t ALLOW; /**< PUF Allow register, offset: 0x28 */ - uint8_t RESERVED_2[20]; - __O uint32_t KEYINPUT; /**< PUF Key Input register, offset: 0x40 */ - __O uint32_t CODEINPUT; /**< PUF Code Input register, offset: 0x44 */ - __I uint32_t CODEOUTPUT; /**< PUF Code Output register, offset: 0x48 */ - uint8_t RESERVED_3[20]; - __I uint32_t KEYOUTINDEX; /**< PUF Key Output Index register, offset: 0x60 */ - __I uint32_t KEYOUTPUT; /**< PUF Key Output register, offset: 0x64 */ - uint8_t RESERVED_4[116]; - __IO uint32_t IFSTAT; /**< PUF Interface Status and clear register, offset: 0xDC */ - uint8_t RESERVED_5[28]; - __I uint32_t VERSION; /**< PUF version register., offset: 0xFC */ - __IO uint32_t INTEN; /**< PUF Interrupt Enable, offset: 0x100 */ - __IO uint32_t INTSTAT; /**< PUF interrupt status, offset: 0x104 */ - __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */ - __IO uint32_t CFG; /**< PUF config register for block bits, offset: 0x10C */ - uint8_t RESERVED_6[240]; - __IO uint32_t KEYLOCK; /**< Only reset in case of full IC reset, offset: 0x200 */ - __IO uint32_t KEYENABLE; /**< , offset: 0x204 */ - __O uint32_t KEYRESET; /**< Reinitialize Keys shift registers counters, offset: 0x208 */ - __IO uint32_t IDXBLK_L; /**< , offset: 0x20C */ - __IO uint32_t IDXBLK_H_DP; /**< , offset: 0x210 */ - __O uint32_t KEYMASK[4]; /**< Only reset in case of full IC reset, array offset: 0x214, array step: 0x4 */ - uint8_t RESERVED_7[48]; - __IO uint32_t IDXBLK_H; /**< , offset: 0x254 */ - __IO uint32_t IDXBLK_L_DP; /**< , offset: 0x258 */ - __I uint32_t SHIFT_STATUS; /**< , offset: 0x25C */ -} PUF_Type; - -/* ---------------------------------------------------------------------------- - -- PUF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_Register_Masks PUF Register Masks - * @{ - */ - -/*! @name CTRL - PUF Control register */ -/*! @{ */ - -#define PUF_CTRL_ZEROIZE_MASK (0x1U) -#define PUF_CTRL_ZEROIZE_SHIFT (0U) -/*! zeroize - Begin Zeroize operation for PUF and go to Error state - */ -#define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK) - -#define PUF_CTRL_ENROLL_MASK (0x2U) -#define PUF_CTRL_ENROLL_SHIFT (1U) -/*! enroll - Begin Enroll operation - */ -#define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK) - -#define PUF_CTRL_START_MASK (0x4U) -#define PUF_CTRL_START_SHIFT (2U) -/*! start - Begin Start operation - */ -#define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK) - -#define PUF_CTRL_GENERATEKEY_MASK (0x8U) -#define PUF_CTRL_GENERATEKEY_SHIFT (3U) -/*! GENERATEKEY - Begin Set Intrinsic Key operation - */ -#define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK) - -#define PUF_CTRL_SETKEY_MASK (0x10U) -#define PUF_CTRL_SETKEY_SHIFT (4U) -/*! SETKEY - Begin Set User Key operation - */ -#define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK) - -#define PUF_CTRL_GETKEY_MASK (0x40U) -#define PUF_CTRL_GETKEY_SHIFT (6U) -/*! GETKEY - Begin Get Key operation - */ -#define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK) -/*! @} */ - -/*! @name KEYINDEX - PUF Key Index register */ -/*! @{ */ - -#define PUF_KEYINDEX_KEYIDX_MASK (0xFU) -#define PUF_KEYINDEX_KEYIDX_SHIFT (0U) -/*! KEYIDX - Key index for Set Key operations - */ -#define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK) -/*! @} */ - -/*! @name KEYSIZE - PUF Key Size register */ -/*! @{ */ - -#define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU) -#define PUF_KEYSIZE_KEYSIZE_SHIFT (0U) -/*! KEYSIZE - Key size for Set Key operations - */ -#define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK) -/*! @} */ - -/*! @name STAT - PUF Status register */ -/*! @{ */ - -#define PUF_STAT_BUSY_MASK (0x1U) -#define PUF_STAT_BUSY_SHIFT (0U) -/*! busy - Indicates that operation is in progress - */ -#define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK) - -#define PUF_STAT_SUCCESS_MASK (0x2U) -#define PUF_STAT_SUCCESS_SHIFT (1U) -/*! SUCCESS - Last operation was successful - */ -#define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK) - -#define PUF_STAT_ERROR_MASK (0x4U) -#define PUF_STAT_ERROR_SHIFT (2U) -/*! error - PUF is in the Error state and no operations can be performed - */ -#define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK) - -#define PUF_STAT_KEYINREQ_MASK (0x10U) -#define PUF_STAT_KEYINREQ_SHIFT (4U) -/*! KEYINREQ - Request for next part of key - */ -#define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK) - -#define PUF_STAT_KEYOUTAVAIL_MASK (0x20U) -#define PUF_STAT_KEYOUTAVAIL_SHIFT (5U) -/*! KEYOUTAVAIL - Next part of key is available - */ -#define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK) - -#define PUF_STAT_CODEINREQ_MASK (0x40U) -#define PUF_STAT_CODEINREQ_SHIFT (6U) -/*! CODEINREQ - Request for next part of AC/KC - */ -#define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK) - -#define PUF_STAT_CODEOUTAVAIL_MASK (0x80U) -#define PUF_STAT_CODEOUTAVAIL_SHIFT (7U) -/*! CODEOUTAVAIL - Next part of AC/KC is available - */ -#define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK) -/*! @} */ - -/*! @name ALLOW - PUF Allow register */ -/*! @{ */ - -#define PUF_ALLOW_ALLOWENROLL_MASK (0x1U) -#define PUF_ALLOW_ALLOWENROLL_SHIFT (0U) -/*! ALLOWENROLL - Enroll operation is allowed - */ -#define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK) - -#define PUF_ALLOW_ALLOWSTART_MASK (0x2U) -#define PUF_ALLOW_ALLOWSTART_SHIFT (1U) -/*! ALLOWSTART - Start operation is allowed - */ -#define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK) - -#define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U) -#define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U) -/*! ALLOWSETKEY - Set Key operations are allowed - */ -#define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK) - -#define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U) -#define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U) -/*! ALLOWGETKEY - Get Key operation is allowed - */ -#define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK) -/*! @} */ - -/*! @name KEYINPUT - PUF Key Input register */ -/*! @{ */ - -#define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU) -#define PUF_KEYINPUT_KEYIN_SHIFT (0U) -/*! KEYIN - Key input data - */ -#define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK) -/*! @} */ - -/*! @name CODEINPUT - PUF Code Input register */ -/*! @{ */ - -#define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU) -#define PUF_CODEINPUT_CODEIN_SHIFT (0U) -/*! CODEIN - AC/KC input data - */ -#define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK) -/*! @} */ - -/*! @name CODEOUTPUT - PUF Code Output register */ -/*! @{ */ - -#define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU) -#define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U) -/*! CODEOUT - AC/KC output data - */ -#define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK) -/*! @} */ - -/*! @name KEYOUTINDEX - PUF Key Output Index register */ -/*! @{ */ - -#define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFU) -#define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U) -/*! KEYOUTIDX - Key index for the key that is currently output via the Key Output register - */ -#define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK) -/*! @} */ - -/*! @name KEYOUTPUT - PUF Key Output register */ -/*! @{ */ - -#define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU) -#define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U) -/*! KEYOUT - Key output data - */ -#define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK) -/*! @} */ - -/*! @name IFSTAT - PUF Interface Status and clear register */ -/*! @{ */ - -#define PUF_IFSTAT_ERROR_MASK (0x1U) -#define PUF_IFSTAT_ERROR_SHIFT (0U) -/*! ERROR - Indicates that an APB error has occurred,Writing logic1 clears the if_error bit - */ -#define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK) -/*! @} */ - -/*! @name VERSION - PUF version register. */ -/*! @{ */ - -#define PUF_VERSION_VERSION_MASK (0xFFFFFFFFU) -#define PUF_VERSION_VERSION_SHIFT (0U) -/*! VERSION - Version of the PUF module. - */ -#define PUF_VERSION_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_VERSION_SHIFT)) & PUF_VERSION_VERSION_MASK) -/*! @} */ - -/*! @name INTEN - PUF Interrupt Enable */ -/*! @{ */ - -#define PUF_INTEN_READYEN_MASK (0x1U) -#define PUF_INTEN_READYEN_SHIFT (0U) -/*! READYEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK) - -#define PUF_INTEN_SUCCESEN_MASK (0x2U) -#define PUF_INTEN_SUCCESEN_SHIFT (1U) -/*! SUCCESEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_SUCCESEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK) - -#define PUF_INTEN_ERROREN_MASK (0x4U) -#define PUF_INTEN_ERROREN_SHIFT (2U) -/*! ERROREN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK) - -#define PUF_INTEN_KEYINREQEN_MASK (0x10U) -#define PUF_INTEN_KEYINREQEN_SHIFT (4U) -/*! KEYINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK) - -#define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U) -#define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U) -/*! KEYOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK) - -#define PUF_INTEN_CODEINREQEN_MASK (0x40U) -#define PUF_INTEN_CODEINREQEN_SHIFT (6U) -/*! CODEINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK) - -#define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U) -#define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U) -/*! CODEOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK) -/*! @} */ - -/*! @name INTSTAT - PUF interrupt status */ -/*! @{ */ - -#define PUF_INTSTAT_READY_MASK (0x1U) -#define PUF_INTSTAT_READY_SHIFT (0U) -/*! READY - Triggers on falling edge of busy, write 1 to clear - */ -#define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK) - -#define PUF_INTSTAT_SUCCESS_MASK (0x2U) -#define PUF_INTSTAT_SUCCESS_SHIFT (1U) -/*! SUCCESS - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK) - -#define PUF_INTSTAT_ERROR_MASK (0x4U) -#define PUF_INTSTAT_ERROR_SHIFT (2U) -/*! ERROR - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK) - -#define PUF_INTSTAT_KEYINREQ_MASK (0x10U) -#define PUF_INTSTAT_KEYINREQ_SHIFT (4U) -/*! KEYINREQ - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK) - -#define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U) -#define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U) -/*! KEYOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK) - -#define PUF_INTSTAT_CODEINREQ_MASK (0x40U) -#define PUF_INTSTAT_CODEINREQ_SHIFT (6U) -/*! CODEINREQ - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK) - -#define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U) -#define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U) -/*! CODEOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK) -/*! @} */ - -/*! @name PWRCTRL - PUF RAM Power Control */ -/*! @{ */ - -#define PUF_PWRCTRL_RAMON_MASK (0x1U) -#define PUF_PWRCTRL_RAMON_SHIFT (0U) -/*! RAMON - Power on the PUF RAM. - */ -#define PUF_PWRCTRL_RAMON(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMON_SHIFT)) & PUF_PWRCTRL_RAMON_MASK) - -#define PUF_PWRCTRL_RAMSTAT_MASK (0x2U) -#define PUF_PWRCTRL_RAMSTAT_SHIFT (1U) -/*! RAMSTAT - PUF RAM status. - */ -#define PUF_PWRCTRL_RAMSTAT(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMSTAT_SHIFT)) & PUF_PWRCTRL_RAMSTAT_MASK) -/*! @} */ - -/*! @name CFG - PUF config register for block bits */ -/*! @{ */ - -#define PUF_CFG_BLOCKENROLL_SETKEY_MASK (0x1U) -#define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT (0U) -/*! BLOCKENROLL_SETKEY - Block enroll operation. Write 1 to set, cleared on reset. - */ -#define PUF_CFG_BLOCKENROLL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK) - -#define PUF_CFG_BLOCKKEYOUTPUT_MASK (0x2U) -#define PUF_CFG_BLOCKKEYOUTPUT_SHIFT (1U) -/*! BLOCKKEYOUTPUT - Block set key operation. Write 1 to set, cleared on reset. - */ -#define PUF_CFG_BLOCKKEYOUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK) -/*! @} */ - -/*! @name KEYLOCK - Only reset in case of full IC reset */ -/*! @{ */ - -#define PUF_KEYLOCK_KEY0_MASK (0x3U) -#define PUF_KEYLOCK_KEY0_SHIFT (0U) -/*! KEY0 - "10:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is allowed. 00, 01, - * 11:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is NOT allowed. Important Note : Once - * this field is written with a value different from '10', its value can no longer be modified - * until un Power On Reset occurs." - */ -#define PUF_KEYLOCK_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK) - -#define PUF_KEYLOCK_KEY1_MASK (0xCU) -#define PUF_KEYLOCK_KEY1_SHIFT (2U) -/*! KEY1 - "10:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is allowed. 00, 01, - * 11:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is NOT allowed. Important Note : Once - * this field is written with a value different from '10', its value can no longer be modified - * until un Power On Reset occurs." - */ -#define PUF_KEYLOCK_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK) - -#define PUF_KEYLOCK_KEY2_MASK (0x30U) -#define PUF_KEYLOCK_KEY2_SHIFT (4U) -/*! KEY2 - "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, - * 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once - * this field is written with a value different from '10', its value can no longer be modified - * until un Power On Reset occurs." - */ -#define PUF_KEYLOCK_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK) - -#define PUF_KEYLOCK_KEY3_MASK (0xC0U) -#define PUF_KEYLOCK_KEY3_SHIFT (6U) -/*! KEY3 - "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, - * 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once - * this field is written with a value different from '10', its value can no longer be modified - * until un Power On Reset occurs." - */ -#define PUF_KEYLOCK_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK) -/*! @} */ - -/*! @name KEYENABLE - */ -/*! @{ */ - -#define PUF_KEYENABLE_KEY0_MASK (0x3U) -#define PUF_KEYENABLE_KEY0_SHIFT (0U) -/*! KEY0 - "10: Data coming out from PUF Index 0 interface are shifted in KEY0 register. 00, 01, 11 - * : Data coming out from PUF Index 0 interface are NOT shifted in KEY0 register." - */ -#define PUF_KEYENABLE_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK) - -#define PUF_KEYENABLE_KEY1_MASK (0xCU) -#define PUF_KEYENABLE_KEY1_SHIFT (2U) -/*! KEY1 - "10: Data coming out from PUF Index 0 interface are shifted in KEY1 register. 00, 01, 11 - * : Data coming out from PUF Index 0 interface are NOT shifted in KEY1 register." - */ -#define PUF_KEYENABLE_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK) - -#define PUF_KEYENABLE_KEY2_MASK (0x30U) -#define PUF_KEYENABLE_KEY2_SHIFT (4U) -/*! KEY2 - "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 - * : Data coming out from PUF Index 0 interface are NOT shifted in KEY2 register." - */ -#define PUF_KEYENABLE_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK) - -#define PUF_KEYENABLE_KEY3_MASK (0xC0U) -#define PUF_KEYENABLE_KEY3_SHIFT (6U) -/*! KEY3 - "10: Data coming out from PUF Index 0 interface are shifted in KEY3 register. 00, 01, 11 - * : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." - */ -#define PUF_KEYENABLE_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK) -/*! @} */ - -/*! @name KEYRESET - Reinitialize Keys shift registers counters */ -/*! @{ */ - -#define PUF_KEYRESET_KEY0_MASK (0x3U) -#define PUF_KEYRESET_KEY0_SHIFT (0U) -/*! KEY0 - 10: Reset KEY0 shift register. Self clearing. Must be done before loading any new key. - */ -#define PUF_KEYRESET_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK) - -#define PUF_KEYRESET_KEY1_MASK (0xCU) -#define PUF_KEYRESET_KEY1_SHIFT (2U) -/*! KEY1 - 10: Reset KEY1 shift register. Self clearing. Must be done before loading any new key. - */ -#define PUF_KEYRESET_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK) - -#define PUF_KEYRESET_KEY2_MASK (0x30U) -#define PUF_KEYRESET_KEY2_SHIFT (4U) -/*! KEY2 - 10: Reset KEY2 shift register. Self clearing. Must be done before loading any new key. - */ -#define PUF_KEYRESET_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK) - -#define PUF_KEYRESET_KEY3_MASK (0xC0U) -#define PUF_KEYRESET_KEY3_SHIFT (6U) -/*! KEY3 - 10: Reset KEY3 shift register. Self clearing. Must be done before loading any new key. - */ -#define PUF_KEYRESET_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK) -/*! @} */ - -/*! @name IDXBLK_L - */ -/*! @{ */ - -#define PUF_IDXBLK_L_IDX1_MASK (0xCU) -#define PUF_IDXBLK_L_IDX1_SHIFT (2U) -/*! IDX1 - Use to block PUF index 1 - */ -#define PUF_IDXBLK_L_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX1_SHIFT)) & PUF_IDXBLK_L_IDX1_MASK) - -#define PUF_IDXBLK_L_IDX2_MASK (0x30U) -#define PUF_IDXBLK_L_IDX2_SHIFT (4U) -/*! IDX2 - Use to block PUF index 2 - */ -#define PUF_IDXBLK_L_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX2_SHIFT)) & PUF_IDXBLK_L_IDX2_MASK) - -#define PUF_IDXBLK_L_IDX3_MASK (0xC0U) -#define PUF_IDXBLK_L_IDX3_SHIFT (6U) -/*! IDX3 - Use to block PUF index 3 - */ -#define PUF_IDXBLK_L_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX3_SHIFT)) & PUF_IDXBLK_L_IDX3_MASK) - -#define PUF_IDXBLK_L_IDX4_MASK (0x300U) -#define PUF_IDXBLK_L_IDX4_SHIFT (8U) -/*! IDX4 - Use to block PUF index 4 - */ -#define PUF_IDXBLK_L_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX4_SHIFT)) & PUF_IDXBLK_L_IDX4_MASK) - -#define PUF_IDXBLK_L_IDX5_MASK (0xC00U) -#define PUF_IDXBLK_L_IDX5_SHIFT (10U) -/*! IDX5 - Use to block PUF index 5 - */ -#define PUF_IDXBLK_L_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX5_SHIFT)) & PUF_IDXBLK_L_IDX5_MASK) - -#define PUF_IDXBLK_L_IDX6_MASK (0x3000U) -#define PUF_IDXBLK_L_IDX6_SHIFT (12U) -/*! IDX6 - Use to block PUF index 6 - */ -#define PUF_IDXBLK_L_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX6_SHIFT)) & PUF_IDXBLK_L_IDX6_MASK) - -#define PUF_IDXBLK_L_IDX7_MASK (0xC000U) -#define PUF_IDXBLK_L_IDX7_SHIFT (14U) -/*! IDX7 - Use to block PUF index 7 - */ -#define PUF_IDXBLK_L_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX7_SHIFT)) & PUF_IDXBLK_L_IDX7_MASK) - -#define PUF_IDXBLK_L_LOCK_IDX_MASK (0xC0000000U) -#define PUF_IDXBLK_L_LOCK_IDX_SHIFT (30U) -/*! LOCK_IDX - Lock 0 to 7 PUF key indexes - */ -#define PUF_IDXBLK_L_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_LOCK_IDX_SHIFT)) & PUF_IDXBLK_L_LOCK_IDX_MASK) -/*! @} */ - -/*! @name IDXBLK_H_DP - */ -/*! @{ */ - -#define PUF_IDXBLK_H_DP_IDX8_MASK (0x3U) -#define PUF_IDXBLK_H_DP_IDX8_SHIFT (0U) -/*! IDX8 - Use to block PUF index 8 - */ -#define PUF_IDXBLK_H_DP_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX8_SHIFT)) & PUF_IDXBLK_H_DP_IDX8_MASK) - -#define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) -#define PUF_IDXBLK_H_DP_IDX9_SHIFT (2U) -/*! IDX9 - Use to block PUF index 9 - */ -#define PUF_IDXBLK_H_DP_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK) - -#define PUF_IDXBLK_H_DP_IDX10_MASK (0x30U) -#define PUF_IDXBLK_H_DP_IDX10_SHIFT (4U) -/*! IDX10 - Use to block PUF index 10 - */ -#define PUF_IDXBLK_H_DP_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX10_SHIFT)) & PUF_IDXBLK_H_DP_IDX10_MASK) - -#define PUF_IDXBLK_H_DP_IDX11_MASK (0xC0U) -#define PUF_IDXBLK_H_DP_IDX11_SHIFT (6U) -/*! IDX11 - Use to block PUF index 11 - */ -#define PUF_IDXBLK_H_DP_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX11_SHIFT)) & PUF_IDXBLK_H_DP_IDX11_MASK) - -#define PUF_IDXBLK_H_DP_IDX12_MASK (0x300U) -#define PUF_IDXBLK_H_DP_IDX12_SHIFT (8U) -/*! IDX12 - Use to block PUF index 12 - */ -#define PUF_IDXBLK_H_DP_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX12_SHIFT)) & PUF_IDXBLK_H_DP_IDX12_MASK) - -#define PUF_IDXBLK_H_DP_IDX13_MASK (0xC00U) -#define PUF_IDXBLK_H_DP_IDX13_SHIFT (10U) -/*! IDX13 - Use to block PUF index 13 - */ -#define PUF_IDXBLK_H_DP_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX13_SHIFT)) & PUF_IDXBLK_H_DP_IDX13_MASK) - -#define PUF_IDXBLK_H_DP_IDX14_MASK (0x3000U) -#define PUF_IDXBLK_H_DP_IDX14_SHIFT (12U) -/*! IDX14 - Use to block PUF index 14 - */ -#define PUF_IDXBLK_H_DP_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX14_SHIFT)) & PUF_IDXBLK_H_DP_IDX14_MASK) - -#define PUF_IDXBLK_H_DP_IDX15_MASK (0xC000U) -#define PUF_IDXBLK_H_DP_IDX15_SHIFT (14U) -/*! IDX15 - Use to block PUF index 15 - */ -#define PUF_IDXBLK_H_DP_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX15_SHIFT)) & PUF_IDXBLK_H_DP_IDX15_MASK) -/*! @} */ - -/*! @name KEYMASK - Only reset in case of full IC reset */ -/*! @{ */ - -#define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU) -#define PUF_KEYMASK_KEYMASK_SHIFT (0U) -#define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK) -/*! @} */ - -/* The count of PUF_KEYMASK */ -#define PUF_KEYMASK_COUNT (4U) - -/*! @name IDXBLK_H - */ -/*! @{ */ - -#define PUF_IDXBLK_H_IDX8_MASK (0x3U) -#define PUF_IDXBLK_H_IDX8_SHIFT (0U) -/*! IDX8 - Use to block PUF index 8 - */ -#define PUF_IDXBLK_H_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX8_SHIFT)) & PUF_IDXBLK_H_IDX8_MASK) - -#define PUF_IDXBLK_H_IDX9_MASK (0xCU) -#define PUF_IDXBLK_H_IDX9_SHIFT (2U) -/*! IDX9 - Use to block PUF index 9 - */ -#define PUF_IDXBLK_H_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX9_SHIFT)) & PUF_IDXBLK_H_IDX9_MASK) - -#define PUF_IDXBLK_H_IDX10_MASK (0x30U) -#define PUF_IDXBLK_H_IDX10_SHIFT (4U) -/*! IDX10 - Use to block PUF index 10 - */ -#define PUF_IDXBLK_H_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX10_SHIFT)) & PUF_IDXBLK_H_IDX10_MASK) - -#define PUF_IDXBLK_H_IDX11_MASK (0xC0U) -#define PUF_IDXBLK_H_IDX11_SHIFT (6U) -/*! IDX11 - Use to block PUF index 11 - */ -#define PUF_IDXBLK_H_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX11_SHIFT)) & PUF_IDXBLK_H_IDX11_MASK) - -#define PUF_IDXBLK_H_IDX12_MASK (0x300U) -#define PUF_IDXBLK_H_IDX12_SHIFT (8U) -/*! IDX12 - Use to block PUF index 12 - */ -#define PUF_IDXBLK_H_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX12_SHIFT)) & PUF_IDXBLK_H_IDX12_MASK) - -#define PUF_IDXBLK_H_IDX13_MASK (0xC00U) -#define PUF_IDXBLK_H_IDX13_SHIFT (10U) -/*! IDX13 - Use to block PUF index 13 - */ -#define PUF_IDXBLK_H_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX13_SHIFT)) & PUF_IDXBLK_H_IDX13_MASK) - -#define PUF_IDXBLK_H_IDX14_MASK (0x3000U) -#define PUF_IDXBLK_H_IDX14_SHIFT (12U) -/*! IDX14 - Use to block PUF index 14 - */ -#define PUF_IDXBLK_H_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX14_SHIFT)) & PUF_IDXBLK_H_IDX14_MASK) - -#define PUF_IDXBLK_H_IDX15_MASK (0xC000U) -#define PUF_IDXBLK_H_IDX15_SHIFT (14U) -/*! IDX15 - Use to block PUF index 15 - */ -#define PUF_IDXBLK_H_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX15_SHIFT)) & PUF_IDXBLK_H_IDX15_MASK) - -#define PUF_IDXBLK_H_LOCK_IDX_MASK (0xC0000000U) -#define PUF_IDXBLK_H_LOCK_IDX_SHIFT (30U) -/*! LOCK_IDX - Lock 8 to 15 PUF key indexes - */ -#define PUF_IDXBLK_H_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_LOCK_IDX_SHIFT)) & PUF_IDXBLK_H_LOCK_IDX_MASK) -/*! @} */ - -/*! @name IDXBLK_L_DP - */ -/*! @{ */ - -#define PUF_IDXBLK_L_DP_IDX1_MASK (0xCU) -#define PUF_IDXBLK_L_DP_IDX1_SHIFT (2U) -/*! IDX1 - Use to block PUF index 1 - */ -#define PUF_IDXBLK_L_DP_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX1_SHIFT)) & PUF_IDXBLK_L_DP_IDX1_MASK) - -#define PUF_IDXBLK_L_DP_IDX2_MASK (0x30U) -#define PUF_IDXBLK_L_DP_IDX2_SHIFT (4U) -/*! IDX2 - Use to block PUF index 2 - */ -#define PUF_IDXBLK_L_DP_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX2_SHIFT)) & PUF_IDXBLK_L_DP_IDX2_MASK) - -#define PUF_IDXBLK_L_DP_IDX3_MASK (0xC0U) -#define PUF_IDXBLK_L_DP_IDX3_SHIFT (6U) -/*! IDX3 - Use to block PUF index 3 - */ -#define PUF_IDXBLK_L_DP_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX3_SHIFT)) & PUF_IDXBLK_L_DP_IDX3_MASK) - -#define PUF_IDXBLK_L_DP_IDX4_MASK (0x300U) -#define PUF_IDXBLK_L_DP_IDX4_SHIFT (8U) -/*! IDX4 - Use to block PUF index 4 - */ -#define PUF_IDXBLK_L_DP_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX4_SHIFT)) & PUF_IDXBLK_L_DP_IDX4_MASK) - -#define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) -#define PUF_IDXBLK_L_DP_IDX5_SHIFT (10U) -/*! IDX5 - Use to block PUF index 5 - */ -#define PUF_IDXBLK_L_DP_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK) - -#define PUF_IDXBLK_L_DP_IDX6_MASK (0x3000U) -#define PUF_IDXBLK_L_DP_IDX6_SHIFT (12U) -/*! IDX6 - Use to block PUF index 6 - */ -#define PUF_IDXBLK_L_DP_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX6_SHIFT)) & PUF_IDXBLK_L_DP_IDX6_MASK) - -#define PUF_IDXBLK_L_DP_IDX7_MASK (0xC000U) -#define PUF_IDXBLK_L_DP_IDX7_SHIFT (14U) -/*! IDX7 - Use to block PUF index 7 - */ -#define PUF_IDXBLK_L_DP_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX7_SHIFT)) & PUF_IDXBLK_L_DP_IDX7_MASK) -/*! @} */ - -/*! @name SHIFT_STATUS - */ -/*! @{ */ - -#define PUF_SHIFT_STATUS_KEY0_MASK (0xFU) -#define PUF_SHIFT_STATUS_KEY0_SHIFT (0U) -/*! KEY0 - Index counter from key 0 shift register - */ -#define PUF_SHIFT_STATUS_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY0_SHIFT)) & PUF_SHIFT_STATUS_KEY0_MASK) - -#define PUF_SHIFT_STATUS_KEY1_MASK (0xF0U) -#define PUF_SHIFT_STATUS_KEY1_SHIFT (4U) -/*! KEY1 - Index counter from key 1 shift register - */ -#define PUF_SHIFT_STATUS_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY1_SHIFT)) & PUF_SHIFT_STATUS_KEY1_MASK) - -#define PUF_SHIFT_STATUS_KEY2_MASK (0xF00U) -#define PUF_SHIFT_STATUS_KEY2_SHIFT (8U) -/*! KEY2 - Index counter from key 2 shift register - */ -#define PUF_SHIFT_STATUS_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY2_SHIFT)) & PUF_SHIFT_STATUS_KEY2_MASK) - -#define PUF_SHIFT_STATUS_KEY3_MASK (0xF000U) -#define PUF_SHIFT_STATUS_KEY3_SHIFT (12U) -/*! KEY3 - Index counter from key 3 shift register - */ -#define PUF_SHIFT_STATUS_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY3_SHIFT)) & PUF_SHIFT_STATUS_KEY3_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PUF_Register_Masks */ - - -/* PUF - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PUF base address */ - #define PUF_BASE (0x5003B000u) - /** Peripheral PUF base address */ - #define PUF_BASE_NS (0x4003B000u) - /** Peripheral PUF base pointer */ - #define PUF ((PUF_Type *)PUF_BASE) - /** Peripheral PUF base pointer */ - #define PUF_NS ((PUF_Type *)PUF_BASE_NS) - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS { PUF_BASE } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS { PUF } - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS_NS { PUF_BASE_NS } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS_NS { PUF_NS } -#else - /** Peripheral PUF base address */ - #define PUF_BASE (0x4003B000u) - /** Peripheral PUF base pointer */ - #define PUF ((PUF_Type *)PUF_BASE) - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS { PUF_BASE } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS { PUF } -#endif -/** Interrupt vectors for the PUF peripheral type */ -#define PUF_IRQS { PUF_IRQn } - -/*! - * @} - */ /* end of group PUF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RNG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer - * @{ - */ - -/** RNG - Register Layout Typedef */ -typedef struct { - __I uint32_t RANDOM_NUMBER; /**< This register contains a random 32 bit number which is computed on demand, at each time it is read, offset: 0x0 */ - uint8_t RESERVED_0[4]; - __I uint32_t COUNTER_VAL; /**< , offset: 0x8 */ - __IO uint32_t COUNTER_CFG; /**< , offset: 0xC */ - __IO uint32_t ONLINE_TEST_CFG; /**< , offset: 0x10 */ - __I uint32_t ONLINE_TEST_VAL; /**< , offset: 0x14 */ - uint8_t RESERVED_1[4068]; - __I uint32_t MODULEID; /**< IP identifier, offset: 0xFFC */ -} RNG_Type; - -/* ---------------------------------------------------------------------------- - -- RNG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RNG_Register_Masks RNG Register Masks - * @{ - */ - -/*! @name RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read */ -/*! @{ */ - -#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK (0xFFFFFFFFU) -#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT (0U) -/*! RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read. - */ -#define RNG_RANDOM_NUMBER_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT)) & RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK) -/*! @} */ - -/*! @name COUNTER_VAL - */ -/*! @{ */ - -#define RNG_COUNTER_VAL_CLK_RATIO_MASK (0xFFU) -#define RNG_COUNTER_VAL_CLK_RATIO_SHIFT (0U) -/*! CLK_RATIO - Gives the ratio between the internal clocks frequencies and the register clock - * frequency for evaluation and certification purposes. - */ -#define RNG_COUNTER_VAL_CLK_RATIO(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_CLK_RATIO_SHIFT)) & RNG_COUNTER_VAL_CLK_RATIO_MASK) - -#define RNG_COUNTER_VAL_REFRESH_CNT_MASK (0x1F00U) -#define RNG_COUNTER_VAL_REFRESH_CNT_SHIFT (8U) -/*! REFRESH_CNT - Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER. - */ -#define RNG_COUNTER_VAL_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_REFRESH_CNT_SHIFT)) & RNG_COUNTER_VAL_REFRESH_CNT_MASK) -/*! @} */ - -/*! @name COUNTER_CFG - */ -/*! @{ */ - -#define RNG_COUNTER_CFG_MODE_MASK (0x3U) -#define RNG_COUNTER_CFG_MODE_SHIFT (0U) -/*! MODE - 00: disabled 01: update once. - */ -#define RNG_COUNTER_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_MODE_SHIFT)) & RNG_COUNTER_CFG_MODE_MASK) - -#define RNG_COUNTER_CFG_CLOCK_SEL_MASK (0x1CU) -#define RNG_COUNTER_CFG_CLOCK_SEL_SHIFT (2U) -/*! CLOCK_SEL - Selects the internal clock on which to compute statistics. - */ -#define RNG_COUNTER_CFG_CLOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_CLOCK_SEL_SHIFT)) & RNG_COUNTER_CFG_CLOCK_SEL_MASK) - -#define RNG_COUNTER_CFG_SHIFT4X_MASK (0xE0U) -#define RNG_COUNTER_CFG_SHIFT4X_SHIFT (5U) -/*! SHIFT4X - To be used to add precision to clock_ratio and determine 'entropy refill'. - */ -#define RNG_COUNTER_CFG_SHIFT4X(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_SHIFT4X_SHIFT)) & RNG_COUNTER_CFG_SHIFT4X_MASK) -/*! @} */ - -/*! @name ONLINE_TEST_CFG - */ -/*! @{ */ - -#define RNG_ONLINE_TEST_CFG_ACTIVATE_MASK (0x1U) -#define RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT (0U) -/*! ACTIVATE - 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER. - */ -#define RNG_ONLINE_TEST_CFG_ACTIVATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT)) & RNG_ONLINE_TEST_CFG_ACTIVATE_MASK) - -#define RNG_ONLINE_TEST_CFG_DATA_SEL_MASK (0x6U) -#define RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT (1U) -/*! DATA_SEL - Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one - * or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10: - * RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this - * field. - */ -#define RNG_ONLINE_TEST_CFG_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT)) & RNG_ONLINE_TEST_CFG_DATA_SEL_MASK) -/*! @} */ - -/*! @name ONLINE_TEST_VAL - */ -/*! @{ */ - -#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK (0xFU) -#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT (0U) -/*! LIVE_CHI_SQUARED - This value is updated as described in field 'activate'. - */ -#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK) - -#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK (0xF0U) -#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT (4U) -/*! MIN_CHI_SQUARED - This field is reset when 'activate'==0. - */ -#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) - -#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK (0xF00U) -#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT (8U) -/*! MAX_CHI_SQUARED - This field is reset when 'activate'==0. - */ -#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) -/*! @} */ - -/*! @name MODULEID - IP identifier */ -/*! @{ */ - -#define RNG_MODULEID_APERTURE_MASK (0xFFU) -#define RNG_MODULEID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture i. - */ -#define RNG_MODULEID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_APERTURE_SHIFT)) & RNG_MODULEID_APERTURE_MASK) - -#define RNG_MODULEID_MIN_REV_MASK (0xF00U) -#define RNG_MODULEID_MIN_REV_SHIFT (8U) -/*! MIN_REV - Minor revision i. - */ -#define RNG_MODULEID_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MIN_REV_SHIFT)) & RNG_MODULEID_MIN_REV_MASK) - -#define RNG_MODULEID_MAJ_REV_MASK (0xF000U) -#define RNG_MODULEID_MAJ_REV_SHIFT (12U) -/*! MAJ_REV - Major revision i. - */ -#define RNG_MODULEID_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MAJ_REV_SHIFT)) & RNG_MODULEID_MAJ_REV_MASK) - -#define RNG_MODULEID_ID_MASK (0xFFFF0000U) -#define RNG_MODULEID_ID_SHIFT (16U) -/*! ID - Identifier. - */ -#define RNG_MODULEID_ID(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_ID_SHIFT)) & RNG_MODULEID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group RNG_Register_Masks */ - - -/* RNG - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral RNG base address */ - #define RNG_BASE (0x5003A000u) - /** Peripheral RNG base address */ - #define RNG_BASE_NS (0x4003A000u) - /** Peripheral RNG base pointer */ - #define RNG ((RNG_Type *)RNG_BASE) - /** Peripheral RNG base pointer */ - #define RNG_NS ((RNG_Type *)RNG_BASE_NS) - /** Array initializer of RNG peripheral base addresses */ - #define RNG_BASE_ADDRS { RNG_BASE } - /** Array initializer of RNG peripheral base pointers */ - #define RNG_BASE_PTRS { RNG } - /** Array initializer of RNG peripheral base addresses */ - #define RNG_BASE_ADDRS_NS { RNG_BASE_NS } - /** Array initializer of RNG peripheral base pointers */ - #define RNG_BASE_PTRS_NS { RNG_NS } -#else - /** Peripheral RNG base address */ - #define RNG_BASE (0x4003A000u) - /** Peripheral RNG base pointer */ - #define RNG ((RNG_Type *)RNG_BASE) - /** Array initializer of RNG peripheral base addresses */ - #define RNG_BASE_ADDRS { RNG_BASE } - /** Array initializer of RNG peripheral base pointers */ - #define RNG_BASE_PTRS { RNG } -#endif - -/*! - * @} - */ /* end of group RNG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RTC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer - * @{ - */ - -/** RTC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ - __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ - __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ - __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ - __I uint32_t SUBSEC; /**< Sub-second counter register, offset: 0x10 */ - uint8_t RESERVED_0[44]; - __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */ -} RTC_Type; - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/*! @name CTRL - RTC control register */ -/*! @{ */ - -#define RTC_CTRL_SWRESET_MASK (0x1U) -#define RTC_CTRL_SWRESET_SHIFT (0U) -/*! SWRESET - Software reset control - * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. - * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value - * except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes - * to set any of the other bits within this register. Do not attempt to write to any bits of this register at - * the same time that the reset bit is being cleared. - */ -#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) - -#define RTC_CTRL_ALARM1HZ_MASK (0x4U) -#define RTC_CTRL_ALARM1HZ_SHIFT (2U) -/*! ALARM1HZ - RTC 1 Hz timer alarm flag status. - * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. - * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt - * request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. - */ -#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) - -#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) -#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) -/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status. - * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. - * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up - * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. - */ -#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) - -#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) -#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) -/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. - * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. - */ -#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) - -#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) -#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) -/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. - * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. - */ -#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) - -#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) -#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) -/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz - * timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). - * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. The 1 kHz RTC timer is enabled. - */ -#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) - -#define RTC_CTRL_RTC_EN_MASK (0x80U) -#define RTC_CTRL_RTC_EN_SHIFT (7U) -/*! RTC_EN - RTC enable. - * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should - * be 0 when writing to load a value in the RTC counter register. - * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate - * operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the - * high-resolution, 1 kHz clock, set bit 6 in this register. - */ -#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) - -#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) -#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) -/*! RTC_OSC_PD - RTC oscillator power-down control. - * 0b0..See RTC_OSC_BYPASS - * 0b1..RTC oscillator is powered-down. - */ -#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) - -#define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) -#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) -/*! RTC_OSC_BYPASS - RTC oscillator bypass control. - * 0b0..The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. - * 0b1..The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. - */ -#define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) - -#define RTC_CTRL_RTC_SUBSEC_ENA_MASK (0x400U) -#define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT (10U) -/*! RTC_SUBSEC_ENA - RTC Sub-second counter control. - * 0b0..The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD - * reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second - * counter, this bit will always read-back as a '0'. - * 0b1..The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first - * one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is - * set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip - * exits deep power-down mode. - */ -#define RTC_CTRL_RTC_SUBSEC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK) -/*! @} */ - -/*! @name MATCH - RTC match register */ -/*! @{ */ - -#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) -#define RTC_MATCH_MATVAL_SHIFT (0U) -/*! MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the - * alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. - */ -#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) -/*! @} */ - -/*! @name COUNT - RTC counter register */ -/*! @{ */ - -#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) -#define RTC_COUNT_VAL_SHIFT (0U) -/*! VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial - * value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC - * Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this - * register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after - * the RTC_EN bit is set. - */ -#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) -/*! @} */ - -/*! @name WAKE - High-resolution/wake-up timer control register */ -/*! @{ */ - -#define RTC_WAKE_VAL_MASK (0xFFFFU) -#define RTC_WAKE_VAL_SHIFT (0U) -/*! VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads - * a start count value into the wake-up timer and initializes a count-down sequence. Do not write - * to this register while counting is in progress. - */ -#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) -/*! @} */ - -/*! @name SUBSEC - Sub-second counter register */ -/*! @{ */ - -#define RTC_SUBSEC_SUBSEC_MASK (0x7FFFU) -#define RTC_SUBSEC_SUBSEC_SHIFT (0U) -/*! SUBSEC - A read reflects the current value of the 32KHz sub-second counter. This counter is - * cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz - * rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This - * counter must be re-enabled after exiting deep power-down mode or after the main RTC module is - * disabled and re-enabled. On modules not equipped with a sub-second counter, this register - * will read-back as all zeroes. - */ -#define RTC_SUBSEC_SUBSEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_SUBSEC_SHIFT)) & RTC_SUBSEC_SUBSEC_MASK) -/*! @} */ - -/*! @name GPREG - General Purpose register */ -/*! @{ */ - -#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU) -#define RTC_GPREG_GPDATA_SHIFT (0U) -/*! GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied. - */ -#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK) -/*! @} */ - -/* The count of RTC_GPREG */ -#define RTC_GPREG_COUNT (8U) - - -/*! - * @} - */ /* end of group RTC_Register_Masks */ - - -/* RTC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral RTC base address */ - #define RTC_BASE (0x5002C000u) - /** Peripheral RTC base address */ - #define RTC_BASE_NS (0x4002C000u) - /** Peripheral RTC base pointer */ - #define RTC ((RTC_Type *)RTC_BASE) - /** Peripheral RTC base pointer */ - #define RTC_NS ((RTC_Type *)RTC_BASE_NS) - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS { RTC_BASE } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS { RTC } - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS_NS { RTC_BASE_NS } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS_NS { RTC_NS } -#else - /** Peripheral RTC base address */ - #define RTC_BASE (0x4002C000u) - /** Peripheral RTC base pointer */ - #define RTC ((RTC_Type *)RTC_BASE) - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS { RTC_BASE } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS { RTC } -#endif -/** Interrupt vectors for the RTC peripheral type */ -#define RTC_IRQS { RTC_IRQn } - -/*! - * @} - */ /* end of group RTC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SCT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer - * @{ - */ - -/** SCT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ - union { /* offset: 0x4 */ - struct { /* offset: 0x4 */ - __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */ - __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */ - } CTRL_ACCESS16BIT; - __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ - }; - union { /* offset: 0x8 */ - struct { /* offset: 0x8 */ - __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */ - __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */ - } LIMIT_ACCESS16BIT; - __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ - }; - union { /* offset: 0xC */ - struct { /* offset: 0xC */ - __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */ - __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */ - } HALT_ACCESS16BIT; - __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ - }; - union { /* offset: 0x10 */ - struct { /* offset: 0x10 */ - __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */ - __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */ - } STOP_ACCESS16BIT; - __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ - }; - union { /* offset: 0x14 */ - struct { /* offset: 0x14 */ - __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */ - __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */ - } START_ACCESS16BIT; - __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ - }; - uint8_t RESERVED_0[40]; - union { /* offset: 0x40 */ - struct { /* offset: 0x40 */ - __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */ - __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */ - } COUNT_ACCESS16BIT; - __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ - }; - union { /* offset: 0x44 */ - struct { /* offset: 0x44 */ - __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */ - __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */ - } STATE_ACCESS16BIT; - __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ - }; - __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ - union { /* offset: 0x4C */ - struct { /* offset: 0x4C */ - __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */ - __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */ - } REGMODE_ACCESS16BIT; - __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ - }; - __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ - __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ - __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ - __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */ - __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */ - uint8_t RESERVED_1[140]; - __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ - __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ - __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ - __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ - union { /* offset: 0x100 */ - union { /* offset: 0x100, array step: 0x4 */ - struct { /* offset: 0x100, array step: 0x4 */ - __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */ - __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */ - } CAP_ACCESS16BIT[16]; - __IO uint32_t CAP[16]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ - }; - union { /* offset: 0x100, array step: 0x4 */ - struct { /* offset: 0x100, array step: 0x4 */ - __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */ - __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */ - } MATCH_ACCESS16BIT[16]; - __IO uint32_t MATCH[16]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ - }; - }; - uint8_t RESERVED_2[192]; - union { /* offset: 0x200 */ - union { /* offset: 0x200, array step: 0x4 */ - struct { /* offset: 0x200, array step: 0x4 */ - __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */ - __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */ - } CAPCTRL_ACCESS16BIT[16]; - __IO uint32_t CAPCTRL[16]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ - }; - union { /* offset: 0x200, array step: 0x4 */ - struct { /* offset: 0x200, array step: 0x4 */ - __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */ - __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */ - } MATCHREL_ACCESS16BIT[16]; - __IO uint32_t MATCHREL[16]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ - }; - }; - uint8_t RESERVED_3[192]; - struct { /* offset: 0x300, array step: 0x8 */ - __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ - __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ - } EV[16]; - uint8_t RESERVED_4[384]; - struct { /* offset: 0x500, array step: 0x8 */ - __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ - __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ - } OUT[10]; -} SCT_Type; - -/* ---------------------------------------------------------------------------- - -- SCT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Register_Masks SCT Register Masks - * @{ - */ - -/*! @name CONFIG - SCT configuration register */ -/*! @{ */ - -#define SCT_CONFIG_UNIFY_MASK (0x1U) -#define SCT_CONFIG_UNIFY_SHIFT (0U) -/*! UNIFY - SCT operation - * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. - * 0b1..The SCT operates as a unified 32-bit counter. - */ -#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) - -#define SCT_CONFIG_CLKMODE_MASK (0x6U) -#define SCT_CONFIG_CLKMODE_SHIFT (1U) -/*! CLKMODE - SCT clock mode - * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. - * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are - * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The - * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the - * high-performance, sampled-clock mode. - * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the - * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the - * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. - * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL - * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system - * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than - * the system clock. - */ -#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) - -#define SCT_CONFIG_CKSEL_MASK (0x78U) -#define SCT_CONFIG_CKSEL_SHIFT (3U) -/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent - * on the CLKMODE bit selection in this register. - * 0b0000..Rising edges on input 0. - * 0b0001..Falling edges on input 0. - * 0b0010..Rising edges on input 1. - * 0b0011..Falling edges on input 1. - * 0b0100..Rising edges on input 2. - * 0b0101..Falling edges on input 2. - * 0b0110..Rising edges on input 3. - * 0b0111..Falling edges on input 3. - * 0b1000..Rising edges on input 4. - * 0b1001..Falling edges on input 4. - * 0b1010..Rising edges on input 5. - * 0b1011..Falling edges on input 5. - * 0b1100..Rising edges on input 6. - * 0b1101..Falling edges on input 6. - * 0b1110..Rising edges on input 7. - * 0b1111..Falling edges on input 7. - */ -#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) - -#define SCT_CONFIG_NORELOAD_L_MASK (0x80U) -#define SCT_CONFIG_NORELOAD_L_SHIFT (7U) -/*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their - * respective reload registers. Setting this bit eliminates the need to write to the reload - * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any - * time. This bit applies to both the higher and lower registers when the UNIFY bit is set. - */ -#define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK) - -#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) -#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) -/*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their - * respective reload registers. Setting this bit eliminates the need to write to the reload - * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at - * any time. This bit is not used when the UNIFY bit is set. - */ -#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) - -#define SCT_CONFIG_INSYNC_MASK (0x1E00U) -#define SCT_CONFIG_INSYNC_SHIFT (9U) -/*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all - * other bits are reserved. A 1 in one of these bits subjects the corresponding input to - * synchronization to the SCT clock, before it is used to create an event. If an input is known to - * already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: - * The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input - * clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. - * It does not apply to the clock input specified in the CKSEL field. - */ -#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) - -#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) -#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) -/*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto - * LIMIT condition without the need to define an associated event. As with any LIMIT event, this - * automatic limit causes the counter to be cleared to zero in unidirectional mode or to change - * the direction of count in bi-directional mode. Software can write to set or clear this bit at - * any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. - */ -#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) - -#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) -#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) -/*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a - * de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, - * this automatic limit causes the counter to be cleared to zero in unidirectional mode or to - * change the direction of count in bi-directional mode. Software can write to set or clear this bit - * at any time. This bit is not used when the UNIFY bit is set. - */ -#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) -/*! @} */ - -/*! @name CTRLL - SCT_CTRLL register */ -/*! @{ */ - -#define SCT_CTRLL_DOWN_L_MASK (0x1U) -#define SCT_CTRLL_DOWN_L_SHIFT (0U) -/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit - * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit - * when the counter is counting down and a limit condition occurs or when the counter reaches 0. - */ -#define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK) - -#define SCT_CTRLL_STOP_L_MASK (0x2U) -#define SCT_CTRLL_STOP_L_SHIFT (1U) -/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events - * related to the counter can occur. If a designated start event occurs, this bit is cleared and - * counting resumes. - */ -#define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK) - -#define SCT_CTRLL_HALT_L_MASK (0x4U) -#define SCT_CTRLL_HALT_L_SHIFT (2U) -/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A - * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to - * remove the halt condition while keeping the SCT in the stop condition (not running) with a - * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, - * only software can clear this bit to restore counter operation. This bit is set on reset. - */ -#define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK) - -#define SCT_CTRLL_CLRCTR_L_MASK (0x8U) -#define SCT_CTRLL_CLRCTR_L_SHIFT (3U) -/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. - */ -#define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK) - -#define SCT_CTRLL_BIDIR_L_MASK (0x10U) -#define SCT_CTRLL_BIDIR_L_SHIFT (4U) -/*! BIDIR_L - L or unified counter direction select - * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. - * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK) - -#define SCT_CTRLL_PRE_L_MASK (0x1FE0U) -#define SCT_CTRLL_PRE_L_SHIFT (5U) -/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified - * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. - * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - */ -#define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK) -/*! @} */ - -/*! @name CTRLH - SCT_CTRLH register */ -/*! @{ */ - -#define SCT_CTRLH_DOWN_H_MASK (0x1U) -#define SCT_CTRLH_DOWN_H_SHIFT (0U) -/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the - * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit - * when the counter is counting down and a limit condition occurs or when the counter reaches 0. - */ -#define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK) - -#define SCT_CTRLH_STOP_H_MASK (0x2U) -#define SCT_CTRLH_STOP_H_SHIFT (1U) -/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to - * the counter can occur. If such an event matches the mask in the Start register, this bit is - * cleared and counting resumes. - */ -#define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK) - -#define SCT_CTRLH_HALT_H_MASK (0x4U) -#define SCT_CTRLH_HALT_H_SHIFT (2U) -/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets - * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the - * halt condition while keeping the SCT in the stop condition (not running) with a single write to - * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit - * can only be cleared by software to restore counter operation. This bit is set on reset. - */ -#define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK) - -#define SCT_CTRLH_CLRCTR_H_MASK (0x8U) -#define SCT_CTRLH_CLRCTR_H_SHIFT (3U) -/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. - */ -#define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK) - -#define SCT_CTRLH_BIDIR_H_MASK (0x10U) -#define SCT_CTRLH_BIDIR_H_SHIFT (4U) -/*! BIDIR_H - Direction select - * 0b0..The H counter counts up to its limit condition, then is cleared to zero. - * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK) - -#define SCT_CTRLH_PRE_H_MASK (0x1FE0U) -#define SCT_CTRLH_PRE_H_SHIFT (5U) -/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. - * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the - * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - */ -#define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK) -/*! @} */ - -/*! @name CTRL - SCT control register */ -/*! @{ */ - -#define SCT_CTRL_DOWN_L_MASK (0x1U) -#define SCT_CTRL_DOWN_L_SHIFT (0U) -/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit - * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit - * when the counter is counting down and a limit condition occurs or when the counter reaches 0. - */ -#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) - -#define SCT_CTRL_STOP_L_MASK (0x2U) -#define SCT_CTRL_STOP_L_SHIFT (1U) -/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events - * related to the counter can occur. If a designated start event occurs, this bit is cleared and - * counting resumes. - */ -#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) - -#define SCT_CTRL_HALT_L_MASK (0x4U) -#define SCT_CTRL_HALT_L_SHIFT (2U) -/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A - * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to - * remove the halt condition while keeping the SCT in the stop condition (not running) with a - * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, - * only software can clear this bit to restore counter operation. This bit is set on reset. - */ -#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) - -#define SCT_CTRL_CLRCTR_L_MASK (0x8U) -#define SCT_CTRL_CLRCTR_L_SHIFT (3U) -/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. - */ -#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) - -#define SCT_CTRL_BIDIR_L_MASK (0x10U) -#define SCT_CTRL_BIDIR_L_SHIFT (4U) -/*! BIDIR_L - L or unified counter direction select - * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. - * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) - -#define SCT_CTRL_PRE_L_MASK (0x1FE0U) -#define SCT_CTRL_PRE_L_SHIFT (5U) -/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified - * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. - * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - */ -#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) - -#define SCT_CTRL_DOWN_H_MASK (0x10000U) -#define SCT_CTRL_DOWN_H_SHIFT (16U) -/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the - * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit - * when the counter is counting down and a limit condition occurs or when the counter reaches 0. - */ -#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) - -#define SCT_CTRL_STOP_H_MASK (0x20000U) -#define SCT_CTRL_STOP_H_SHIFT (17U) -/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to - * the counter can occur. If such an event matches the mask in the Start register, this bit is - * cleared and counting resumes. - */ -#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) - -#define SCT_CTRL_HALT_H_MASK (0x40000U) -#define SCT_CTRL_HALT_H_SHIFT (18U) -/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets - * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the - * halt condition while keeping the SCT in the stop condition (not running) with a single write to - * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit - * can only be cleared by software to restore counter operation. This bit is set on reset. - */ -#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) - -#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) -#define SCT_CTRL_CLRCTR_H_SHIFT (19U) -/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. - */ -#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) - -#define SCT_CTRL_BIDIR_H_MASK (0x100000U) -#define SCT_CTRL_BIDIR_H_SHIFT (20U) -/*! BIDIR_H - Direction select - * 0b0..The H counter counts up to its limit condition, then is cleared to zero. - * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) - -#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) -#define SCT_CTRL_PRE_H_SHIFT (21U) -/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. - * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the - * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - */ -#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) -/*! @} */ - -/*! @name LIMITL - SCT_LIMITL register */ -/*! @{ */ - -#define SCT_LIMITL_LIMITL_MASK (0xFFFFU) -#define SCT_LIMITL_LIMITL_SHIFT (0U) -#define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK) -/*! @} */ - -/*! @name LIMITH - SCT_LIMITH register */ -/*! @{ */ - -#define SCT_LIMITH_LIMITH_MASK (0xFFFFU) -#define SCT_LIMITH_LIMITH_SHIFT (0U) -#define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK) -/*! @} */ - -/*! @name LIMIT - SCT limit event select register */ -/*! @{ */ - -#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) -#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) -/*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter - * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) - -#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) -#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) -/*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit - * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) -/*! @} */ - -/*! @name HALTL - SCT_HALTL register */ -/*! @{ */ - -#define SCT_HALTL_HALTL_MASK (0xFFFFU) -#define SCT_HALTL_HALTL_SHIFT (0U) -#define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK) -/*! @} */ - -/*! @name HALTH - SCT_HALTH register */ -/*! @{ */ - -#define SCT_HALTH_HALTH_MASK (0xFFFFU) -#define SCT_HALTH_HALTH_SHIFT (0U) -#define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK) -/*! @} */ - -/*! @name HALT - SCT halt event select register */ -/*! @{ */ - -#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) -#define SCT_HALT_HALTMSK_L_SHIFT (0U) -/*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, - * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) - -#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) -#define SCT_HALT_HALTMSK_H_SHIFT (16U) -/*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, - * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) -/*! @} */ - -/*! @name STOPL - SCT_STOPL register */ -/*! @{ */ - -#define SCT_STOPL_STOPL_MASK (0xFFFFU) -#define SCT_STOPL_STOPL_SHIFT (0U) -#define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK) -/*! @} */ - -/*! @name STOPH - SCT_STOPH register */ -/*! @{ */ - -#define SCT_STOPH_STOPH_MASK (0xFFFFU) -#define SCT_STOPH_STOPH_SHIFT (0U) -#define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK) -/*! @} */ - -/*! @name STOP - SCT stop event select register */ -/*! @{ */ - -#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) -#define SCT_STOP_STOPMSK_L_SHIFT (0U) -/*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, - * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) - -#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) -#define SCT_STOP_STOPMSK_H_SHIFT (16U) -/*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, - * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) -/*! @} */ - -/*! @name STARTL - SCT_STARTL register */ -/*! @{ */ - -#define SCT_STARTL_STARTL_MASK (0xFFFFU) -#define SCT_STARTL_STARTL_SHIFT (0U) -#define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK) -/*! @} */ - -/*! @name STARTH - SCT_STARTH register */ -/*! @{ */ - -#define SCT_STARTH_STARTH_MASK (0xFFFFU) -#define SCT_STARTH_STARTH_SHIFT (0U) -#define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK) -/*! @} */ - -/*! @name START - SCT start event select register */ -/*! @{ */ - -#define SCT_START_STARTMSK_L_MASK (0xFFFFU) -#define SCT_START_STARTMSK_L_SHIFT (0U) -/*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit - * 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) - -#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) -#define SCT_START_STARTMSK_H_SHIFT (16U) -/*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit - * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) -/*! @} */ - -/*! @name COUNTL - SCT_COUNTL register */ -/*! @{ */ - -#define SCT_COUNTL_COUNTL_MASK (0xFFFFU) -#define SCT_COUNTL_COUNTL_SHIFT (0U) -#define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK) -/*! @} */ - -/*! @name COUNTH - SCT_COUNTH register */ -/*! @{ */ - -#define SCT_COUNTH_COUNTH_MASK (0xFFFFU) -#define SCT_COUNTH_COUNTH_SHIFT (0U) -#define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK) -/*! @} */ - -/*! @name COUNT - SCT counter register */ -/*! @{ */ - -#define SCT_COUNT_CTR_L_MASK (0xFFFFU) -#define SCT_COUNT_CTR_L_SHIFT (0U) -/*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write - * the lower 16 bits of the 32-bit unified counter. - */ -#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) - -#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) -#define SCT_COUNT_CTR_H_SHIFT (16U) -/*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write - * the upper 16 bits of the 32-bit unified counter. - */ -#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) -/*! @} */ - -/*! @name STATEL - SCT_STATEL register */ -/*! @{ */ - -#define SCT_STATEL_STATEL_MASK (0xFFFFU) -#define SCT_STATEL_STATEL_SHIFT (0U) -#define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK) -/*! @} */ - -/*! @name STATEH - SCT_STATEH register */ -/*! @{ */ - -#define SCT_STATEH_STATEH_MASK (0xFFFFU) -#define SCT_STATEH_STATEH_SHIFT (0U) -#define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK) -/*! @} */ - -/*! @name STATE - SCT state register */ -/*! @{ */ - -#define SCT_STATE_STATE_L_MASK (0x1FU) -#define SCT_STATE_STATE_L_SHIFT (0U) -/*! STATE_L - State variable. - */ -#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) - -#define SCT_STATE_STATE_H_MASK (0x1F0000U) -#define SCT_STATE_STATE_H_SHIFT (16U) -/*! STATE_H - State variable. - */ -#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) -/*! @} */ - -/*! @name INPUT - SCT input register */ -/*! @{ */ - -#define SCT_INPUT_AIN0_MASK (0x1U) -#define SCT_INPUT_AIN0_SHIFT (0U) -/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) - -#define SCT_INPUT_AIN1_MASK (0x2U) -#define SCT_INPUT_AIN1_SHIFT (1U) -/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) - -#define SCT_INPUT_AIN2_MASK (0x4U) -#define SCT_INPUT_AIN2_SHIFT (2U) -/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) - -#define SCT_INPUT_AIN3_MASK (0x8U) -#define SCT_INPUT_AIN3_SHIFT (3U) -/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) - -#define SCT_INPUT_AIN4_MASK (0x10U) -#define SCT_INPUT_AIN4_SHIFT (4U) -/*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) - -#define SCT_INPUT_AIN5_MASK (0x20U) -#define SCT_INPUT_AIN5_SHIFT (5U) -/*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) - -#define SCT_INPUT_AIN6_MASK (0x40U) -#define SCT_INPUT_AIN6_SHIFT (6U) -/*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) - -#define SCT_INPUT_AIN7_MASK (0x80U) -#define SCT_INPUT_AIN7_SHIFT (7U) -/*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) - -#define SCT_INPUT_AIN8_MASK (0x100U) -#define SCT_INPUT_AIN8_SHIFT (8U) -/*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) - -#define SCT_INPUT_AIN9_MASK (0x200U) -#define SCT_INPUT_AIN9_SHIFT (9U) -/*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) - -#define SCT_INPUT_AIN10_MASK (0x400U) -#define SCT_INPUT_AIN10_SHIFT (10U) -/*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) - -#define SCT_INPUT_AIN11_MASK (0x800U) -#define SCT_INPUT_AIN11_SHIFT (11U) -/*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) - -#define SCT_INPUT_AIN12_MASK (0x1000U) -#define SCT_INPUT_AIN12_SHIFT (12U) -/*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) - -#define SCT_INPUT_AIN13_MASK (0x2000U) -#define SCT_INPUT_AIN13_SHIFT (13U) -/*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) - -#define SCT_INPUT_AIN14_MASK (0x4000U) -#define SCT_INPUT_AIN14_SHIFT (14U) -/*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) - -#define SCT_INPUT_AIN15_MASK (0x8000U) -#define SCT_INPUT_AIN15_SHIFT (15U) -/*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) - -#define SCT_INPUT_SIN0_MASK (0x10000U) -#define SCT_INPUT_SIN0_SHIFT (16U) -/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) - -#define SCT_INPUT_SIN1_MASK (0x20000U) -#define SCT_INPUT_SIN1_SHIFT (17U) -/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) - -#define SCT_INPUT_SIN2_MASK (0x40000U) -#define SCT_INPUT_SIN2_SHIFT (18U) -/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) - -#define SCT_INPUT_SIN3_MASK (0x80000U) -#define SCT_INPUT_SIN3_SHIFT (19U) -/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) - -#define SCT_INPUT_SIN4_MASK (0x100000U) -#define SCT_INPUT_SIN4_SHIFT (20U) -/*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) - -#define SCT_INPUT_SIN5_MASK (0x200000U) -#define SCT_INPUT_SIN5_SHIFT (21U) -/*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) - -#define SCT_INPUT_SIN6_MASK (0x400000U) -#define SCT_INPUT_SIN6_SHIFT (22U) -/*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) - -#define SCT_INPUT_SIN7_MASK (0x800000U) -#define SCT_INPUT_SIN7_SHIFT (23U) -/*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) - -#define SCT_INPUT_SIN8_MASK (0x1000000U) -#define SCT_INPUT_SIN8_SHIFT (24U) -/*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) - -#define SCT_INPUT_SIN9_MASK (0x2000000U) -#define SCT_INPUT_SIN9_SHIFT (25U) -/*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) - -#define SCT_INPUT_SIN10_MASK (0x4000000U) -#define SCT_INPUT_SIN10_SHIFT (26U) -/*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) - -#define SCT_INPUT_SIN11_MASK (0x8000000U) -#define SCT_INPUT_SIN11_SHIFT (27U) -/*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) - -#define SCT_INPUT_SIN12_MASK (0x10000000U) -#define SCT_INPUT_SIN12_SHIFT (28U) -/*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) - -#define SCT_INPUT_SIN13_MASK (0x20000000U) -#define SCT_INPUT_SIN13_SHIFT (29U) -/*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) - -#define SCT_INPUT_SIN14_MASK (0x40000000U) -#define SCT_INPUT_SIN14_SHIFT (30U) -/*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) - -#define SCT_INPUT_SIN15_MASK (0x80000000U) -#define SCT_INPUT_SIN15_SHIFT (31U) -/*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) -/*! @} */ - -/*! @name REGMODEL - SCT_REGMODEL register */ -/*! @{ */ - -#define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU) -#define SCT_REGMODEL_REGMODEL_SHIFT (0U) -#define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK) -/*! @} */ - -/*! @name REGMODEH - SCT_REGMODEH register */ -/*! @{ */ - -#define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU) -#define SCT_REGMODEH_REGMODEH_SHIFT (0U) -#define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK) -/*! @} */ - -/*! @name REGMODE - SCT match/capture mode register */ -/*! @{ */ - -#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) -#define SCT_REGMODE_REGMOD_L_SHIFT (0U) -/*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, - * etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as - * match register. 1 = register operates as capture register. - */ -#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) - -#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) -#define SCT_REGMODE_REGMOD_H_SHIFT (16U) -/*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit - * 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as - * match registers. 1 = register operates as capture registers. - */ -#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) -/*! @} */ - -/*! @name OUTPUT - SCT output register */ -/*! @{ */ - -#define SCT_OUTPUT_OUT_MASK (0xFFFFU) -#define SCT_OUTPUT_OUT_SHIFT (0U) -/*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the - * corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of - * outputs in this SCT. - */ -#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) -/*! @} */ - -/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ -/*! @{ */ - -#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) -#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) -/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) -#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) -/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) -#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) -/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) -#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) -/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) -#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) -/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) -#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) -/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) -#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) -/*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) -#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) -/*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) -#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) -/*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) -#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) -/*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) -#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) -/*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) -#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) -/*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) -/*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) -/*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) -/*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) -/*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) -/*! @} */ - -/*! @name RES - SCT conflict resolution register */ -/*! @{ */ - -#define SCT_RES_O0RES_MASK (0x3U) -#define SCT_RES_O0RES_SHIFT (0U) -/*! O0RES - Effect of simultaneous set and clear on output 0. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR0 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) - -#define SCT_RES_O1RES_MASK (0xCU) -#define SCT_RES_O1RES_SHIFT (2U) -/*! O1RES - Effect of simultaneous set and clear on output 1. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR1 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) - -#define SCT_RES_O2RES_MASK (0x30U) -#define SCT_RES_O2RES_SHIFT (4U) -/*! O2RES - Effect of simultaneous set and clear on output 2. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output n (or set based on the SETCLR2 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) - -#define SCT_RES_O3RES_MASK (0xC0U) -#define SCT_RES_O3RES_SHIFT (6U) -/*! O3RES - Effect of simultaneous set and clear on output 3. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR3 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) - -#define SCT_RES_O4RES_MASK (0x300U) -#define SCT_RES_O4RES_SHIFT (8U) -/*! O4RES - Effect of simultaneous set and clear on output 4. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR4 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) - -#define SCT_RES_O5RES_MASK (0xC00U) -#define SCT_RES_O5RES_SHIFT (10U) -/*! O5RES - Effect of simultaneous set and clear on output 5. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR5 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) - -#define SCT_RES_O6RES_MASK (0x3000U) -#define SCT_RES_O6RES_SHIFT (12U) -/*! O6RES - Effect of simultaneous set and clear on output 6. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR6 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) - -#define SCT_RES_O7RES_MASK (0xC000U) -#define SCT_RES_O7RES_SHIFT (14U) -/*! O7RES - Effect of simultaneous set and clear on output 7. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output n (or set based on the SETCLR7 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) - -#define SCT_RES_O8RES_MASK (0x30000U) -#define SCT_RES_O8RES_SHIFT (16U) -/*! O8RES - Effect of simultaneous set and clear on output 8. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR8 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) - -#define SCT_RES_O9RES_MASK (0xC0000U) -#define SCT_RES_O9RES_SHIFT (18U) -/*! O9RES - Effect of simultaneous set and clear on output 9. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR9 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) - -#define SCT_RES_O10RES_MASK (0x300000U) -#define SCT_RES_O10RES_SHIFT (20U) -/*! O10RES - Effect of simultaneous set and clear on output 10. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR10 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) - -#define SCT_RES_O11RES_MASK (0xC00000U) -#define SCT_RES_O11RES_SHIFT (22U) -/*! O11RES - Effect of simultaneous set and clear on output 11. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR11 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) - -#define SCT_RES_O12RES_MASK (0x3000000U) -#define SCT_RES_O12RES_SHIFT (24U) -/*! O12RES - Effect of simultaneous set and clear on output 12. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR12 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) - -#define SCT_RES_O13RES_MASK (0xC000000U) -#define SCT_RES_O13RES_SHIFT (26U) -/*! O13RES - Effect of simultaneous set and clear on output 13. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR13 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) - -#define SCT_RES_O14RES_MASK (0x30000000U) -#define SCT_RES_O14RES_SHIFT (28U) -/*! O14RES - Effect of simultaneous set and clear on output 14. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR14 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) - -#define SCT_RES_O15RES_MASK (0xC0000000U) -#define SCT_RES_O15RES_SHIFT (30U) -/*! O15RES - Effect of simultaneous set and clear on output 15. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR15 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) -/*! @} */ - -/*! @name DMAREQ0 - SCT DMA request 0 register */ -/*! @{ */ - -#define SCT_DMAREQ0_DEV_0_MASK (0xFFFFU) -#define SCT_DMAREQ0_DEV_0_SHIFT (0U) -/*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, - * etc.). The number of bits = number of events in this SCT. - */ -#define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK) - -#define SCT_DMAREQ0_DRL0_MASK (0x40000000U) -#define SCT_DMAREQ0_DRL0_SHIFT (30U) -/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. - */ -#define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK) - -#define SCT_DMAREQ0_DRQ0_MASK (0x80000000U) -#define SCT_DMAREQ0_DRQ0_SHIFT (31U) -/*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA - * channel is enabled and properly set up, it is unlikely that software will see this flag, it will - * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA - * setup. - */ -#define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK) -/*! @} */ - -/*! @name DMAREQ1 - SCT DMA request 1 register */ -/*! @{ */ - -#define SCT_DMAREQ1_DEV_1_MASK (0xFFFFU) -#define SCT_DMAREQ1_DEV_1_SHIFT (0U) -/*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, - * etc.). The number of bits = number of events in this SCT. - */ -#define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK) - -#define SCT_DMAREQ1_DRL1_MASK (0x40000000U) -#define SCT_DMAREQ1_DRL1_SHIFT (30U) -/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. - */ -#define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK) - -#define SCT_DMAREQ1_DRQ1_MASK (0x80000000U) -#define SCT_DMAREQ1_DRQ1_SHIFT (31U) -/*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA - * channel is enabled and properly set up, it is unlikely that software will see this flag, it will - * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA - * setup. - */ -#define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK) -/*! @} */ - -/*! @name EVEN - SCT event interrupt enable register */ -/*! @{ */ - -#define SCT_EVEN_IEN_MASK (0xFFFFU) -#define SCT_EVEN_IEN_SHIFT (0U) -/*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are - * both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in - * this SCT. - */ -#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) -/*! @} */ - -/*! @name EVFLAG - SCT event flag register */ -/*! @{ */ - -#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) -#define SCT_EVFLAG_FLAG_SHIFT (0U) -/*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit - * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) -/*! @} */ - -/*! @name CONEN - SCT conflict interrupt enable register */ -/*! @{ */ - -#define SCT_CONEN_NCEN_MASK (0xFFFFU) -#define SCT_CONEN_NCEN_SHIFT (0U) -/*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag - * register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of - * outputs in this SCT. - */ -#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) -/*! @} */ - -/*! @name CONFLAG - SCT conflict flag register */ -/*! @{ */ - -#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) -#define SCT_CONFLAG_NCFLAG_SHIFT (0U) -/*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was - * last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = - * number of outputs in this SCT. - */ -#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) - -#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) -#define SCT_CONFLAG_BUSERRL_SHIFT (30U) -/*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE - * L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write - * to certain L and H registers can be half successful and half unsuccessful. - */ -#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) - -#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) -#define SCT_CONFLAG_BUSERRH_SHIFT (31U) -/*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or - * the Output register when the H counter was not halted. - */ -#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) -/*! @} */ - -/*! @name CAPL - SCT_CAPL register */ -/*! @{ */ - -#define SCT_CAPL_CAPL_MASK (0xFFFFU) -#define SCT_CAPL_CAPL_SHIFT (0U) -#define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK) -/*! @} */ - -/* The count of SCT_CAPL */ -#define SCT_CAPL_COUNT (16U) - -/*! @name CAPH - SCT_CAPH register */ -/*! @{ */ - -#define SCT_CAPH_CAPH_MASK (0xFFFFU) -#define SCT_CAPH_CAPH_SHIFT (0U) -#define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK) -/*! @} */ - -/* The count of SCT_CAPH */ -#define SCT_CAPH_COUNT (16U) - -/*! @name CAP - SCT capture register of capture channel */ -/*! @{ */ - -#define SCT_CAP_CAPn_L_MASK (0xFFFFU) -#define SCT_CAP_CAPn_L_SHIFT (0U) -/*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. - * When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last - * captured. - */ -#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK) - -#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U) -#define SCT_CAP_CAPn_H_SHIFT (16U) -/*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. - * When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last - * captured. - */ -#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK) -/*! @} */ - -/* The count of SCT_CAP */ -#define SCT_CAP_COUNT (16U) - -/*! @name MATCHL - SCT_MATCHL register */ -/*! @{ */ - -#define SCT_MATCHL_MATCHL_MASK (0xFFFFU) -#define SCT_MATCHL_MATCHL_SHIFT (0U) -#define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK) -/*! @} */ - -/* The count of SCT_MATCHL */ -#define SCT_MATCHL_COUNT (16U) - -/*! @name MATCHH - SCT_MATCHH register */ -/*! @{ */ - -#define SCT_MATCHH_MATCHH_MASK (0xFFFFU) -#define SCT_MATCHH_MATCHH_SHIFT (0U) -#define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK) -/*! @} */ - -/* The count of SCT_MATCHH */ -#define SCT_MATCHH_COUNT (16U) - -/*! @name MATCH - SCT match value register of match channels */ -/*! @{ */ - -#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU) -#define SCT_MATCH_MATCHn_L_SHIFT (0U) -/*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When - * UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified - * counter. - */ -#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK) - -#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U) -#define SCT_MATCH_MATCHn_H_SHIFT (16U) -/*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When - * UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified - * counter. - */ -#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK) -/*! @} */ - -/* The count of SCT_MATCH */ -#define SCT_MATCH_COUNT (16U) - -/*! @name CAPCTRLL - SCT_CAPCTRLL register */ -/*! @{ */ - -#define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU) -#define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U) -#define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK) -/*! @} */ - -/* The count of SCT_CAPCTRLL */ -#define SCT_CAPCTRLL_COUNT (16U) - -/*! @name CAPCTRLH - SCT_CAPCTRLH register */ -/*! @{ */ - -#define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU) -#define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U) -#define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK) -/*! @} */ - -/* The count of SCT_CAPCTRLH */ -#define SCT_CAPCTRLH_COUNT (16U) - -/*! @name CAPCTRL - SCT capture control register */ -/*! @{ */ - -#define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU) -#define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U) -/*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) - * register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of - * match/captures in this SCT. - */ -#define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK) - -#define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) -#define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U) -/*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event - * 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - */ -#define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK) -/*! @} */ - -/* The count of SCT_CAPCTRL */ -#define SCT_CAPCTRL_COUNT (16U) - -/*! @name MATCHRELL - SCT_MATCHRELL register */ -/*! @{ */ - -#define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU) -#define SCT_MATCHRELL_MATCHRELL_SHIFT (0U) -#define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK) -/*! @} */ - -/* The count of SCT_MATCHRELL */ -#define SCT_MATCHRELL_COUNT (16U) - -/*! @name MATCHRELH - SCT_MATCHRELH register */ -/*! @{ */ - -#define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU) -#define SCT_MATCHRELH_MATCHRELH_SHIFT (0U) -#define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK) -/*! @} */ - -/* The count of SCT_MATCHRELH */ -#define SCT_MATCHRELH_COUNT (16U) - -/*! @name MATCHREL - SCT match reload value register */ -/*! @{ */ - -#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU) -#define SCT_MATCHREL_RELOADn_L_SHIFT (0U) -/*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. - * When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn - * register. - */ -#define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK) - -#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U) -#define SCT_MATCHREL_RELOADn_H_SHIFT (16U) -/*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When - * UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn - * register. - */ -#define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK) -/*! @} */ - -/* The count of SCT_MATCHREL */ -#define SCT_MATCHREL_COUNT (16U) - -/*! @name EV_STATE - SCT event state register 0 */ -/*! @{ */ - -#define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFU) -#define SCT_EV_STATE_STATEMSKn_SHIFT (0U) -/*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT - * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of - * bits = number of states in this SCT. - */ -#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK) -/*! @} */ - -/* The count of SCT_EV_STATE */ -#define SCT_EV_STATE_COUNT (16U) - -/*! @name EV_CTRL - SCT event control register 0 */ -/*! @{ */ - -#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU) -#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U) -/*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur - * only when the counter selected by the HEVENT bit is running. - */ -#define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK) - -#define SCT_EV_CTRL_HEVENT_MASK (0x10U) -#define SCT_EV_CTRL_HEVENT_SHIFT (4U) -/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. - * 0b0..Selects the L state and the L match register selected by MATCHSEL. - * 0b1..Selects the H state and the H match register selected by MATCHSEL. - */ -#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK) - -#define SCT_EV_CTRL_OUTSEL_MASK (0x20U) -#define SCT_EV_CTRL_OUTSEL_SHIFT (5U) -/*! OUTSEL - Input/output select - * 0b0..Selects the inputs selected by IOSEL. - * 0b1..Selects the outputs selected by IOSEL. - */ -#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK) - -#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U) -#define SCT_EV_CTRL_IOSEL_SHIFT (6U) -/*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not - * select an input in this register if CKMODE is 1x. In this case the clock input is an implicit - * ingredient of every event. - */ -#define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK) - -#define SCT_EV_CTRL_IOCOND_MASK (0xC00U) -#define SCT_EV_CTRL_IOCOND_SHIFT (10U) -/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the - * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state - * detection, an input must have a minimum pulse width of at least one SCT clock period . - * 0b00..LOW - * 0b01..Rise - * 0b10..Fall - * 0b11..HIGH - */ -#define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK) - -#define SCT_EV_CTRL_COMBMODE_MASK (0x3000U) -#define SCT_EV_CTRL_COMBMODE_SHIFT (12U) -/*! COMBMODE - Selects how the specified match and I/O condition are used and combined. - * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. - * 0b01..MATCH. Uses the specified match only. - * 0b10..IO. Uses the specified I/O condition only. - * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. - */ -#define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK) - -#define SCT_EV_CTRL_STATELD_MASK (0x4000U) -#define SCT_EV_CTRL_STATELD_SHIFT (14U) -/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this - * event is the highest-numbered event occurring for that state. - * 0b0..STATEV value is added into STATE (the carry-out is ignored). - * 0b1..STATEV value is loaded into STATE. - */ -#define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK) - -#define SCT_EV_CTRL_STATEV_MASK (0xF8000U) -#define SCT_EV_CTRL_STATEV_SHIFT (15U) -/*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on - * STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and - * STATEV are both zero, there is no change to the STATE value. - */ -#define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK) - -#define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U) -#define SCT_EV_CTRL_MATCHMEM_SHIFT (20U) -/*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the - * triggering of this event, then a match is considered to be active whenever the counter value is - * GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR - * EQUAL TO the match value when counting down. If this bit is zero, a match is only be active - * during the cycle when the counter is equal to the match value. - */ -#define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK) - -#define SCT_EV_CTRL_DIRECTION_MASK (0x600000U) -#define SCT_EV_CTRL_DIRECTION_SHIFT (21U) -/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters - * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. - * 0b00..Direction independent. This event is triggered regardless of the count direction. - * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. - * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. - */ -#define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK) -/*! @} */ - -/* The count of SCT_EV_CTRL */ -#define SCT_EV_CTRL_COUNT (16U) - -/*! @name OUT_SET - SCT output 0 set register */ -/*! @{ */ - -#define SCT_OUT_SET_SET_MASK (0xFFFFU) -#define SCT_OUT_SET_SET_SHIFT (0U) -/*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output - * 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the - * counter is used in bi-directional mode, it is possible to reverse the action specified by the - * output set and clear registers when counting down, See the OUTPUTCTRL register. - */ -#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) -/*! @} */ - -/* The count of SCT_OUT_SET */ -#define SCT_OUT_SET_COUNT (10U) - -/*! @name OUT_CLR - SCT output 0 clear register */ -/*! @{ */ - -#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) -#define SCT_OUT_CLR_CLR_SHIFT (0U) -/*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 - * = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the - * counter is used in bi-directional mode, it is possible to reverse the action specified by the - * output set and clear registers when counting down, See the OUTPUTCTRL register. - */ -#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) -/*! @} */ - -/* The count of SCT_OUT_CLR */ -#define SCT_OUT_CLR_COUNT (10U) - - -/*! - * @} - */ /* end of group SCT_Register_Masks */ - - -/* SCT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SCT0 base address */ - #define SCT0_BASE (0x50085000u) - /** Peripheral SCT0 base address */ - #define SCT0_BASE_NS (0x40085000u) - /** Peripheral SCT0 base pointer */ - #define SCT0 ((SCT_Type *)SCT0_BASE) - /** Peripheral SCT0 base pointer */ - #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS { SCT0_BASE } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS { SCT0 } - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS_NS { SCT0_NS } -#else - /** Peripheral SCT0 base address */ - #define SCT0_BASE (0x40085000u) - /** Peripheral SCT0 base pointer */ - #define SCT0 ((SCT_Type *)SCT0_BASE) - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS { SCT0_BASE } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS { SCT0 } -#endif -/** Interrupt vectors for the SCT peripheral type */ -#define SCT_IRQS { SCT0_IRQn } - -/*! - * @} - */ /* end of group SCT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SDIF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer - * @{ - */ - -/** SDIF - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register, offset: 0x0 */ - __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */ - __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */ - __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */ - __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */ - __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */ - __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */ - __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */ - __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */ - __IO uint32_t CMD; /**< Command register, offset: 0x2C */ - __IO uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */ - __IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */ - __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */ - __IO uint32_t STATUS; /**< Status register, offset: 0x48 */ - __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */ - __IO uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */ - __IO uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */ - uint8_t RESERVED_1[4]; - __IO uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */ - __IO uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */ - __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */ - uint8_t RESERVED_2[16]; - __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */ - uint8_t RESERVED_3[4]; - __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */ - __IO uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */ - __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */ - __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */ - __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */ - __IO uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */ - __IO uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */ - uint8_t RESERVED_4[100]; - __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */ - __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */ - uint8_t RESERVED_5[248]; - __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */ -} SDIF_Type; - -/* ---------------------------------------------------------------------------- - -- SDIF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDIF_Register_Masks SDIF Register Masks - * @{ - */ - -/*! @name CTRL - Control register */ -/*! @{ */ - -#define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U) -#define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U) -/*! CONTROLLER_RESET - Controller reset. - */ -#define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK) - -#define SDIF_CTRL_FIFO_RESET_MASK (0x2U) -#define SDIF_CTRL_FIFO_RESET_SHIFT (1U) -/*! FIFO_RESET - Fifo reset. - */ -#define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK) - -#define SDIF_CTRL_DMA_RESET_MASK (0x4U) -#define SDIF_CTRL_DMA_RESET_SHIFT (2U) -/*! DMA_RESET - DMA reset. - */ -#define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK) - -#define SDIF_CTRL_INT_ENABLE_MASK (0x10U) -#define SDIF_CTRL_INT_ENABLE_SHIFT (4U) -/*! INT_ENABLE - Global interrupt enable/disable bit. - */ -#define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK) - -#define SDIF_CTRL_READ_WAIT_MASK (0x40U) -#define SDIF_CTRL_READ_WAIT_SHIFT (6U) -/*! READ_WAIT - Read/wait. - */ -#define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK) - -#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U) -#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U) -/*! SEND_IRQ_RESPONSE - Send irq response. - */ -#define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK) - -#define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U) -#define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U) -/*! ABORT_READ_DATA - Abort read data. - */ -#define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK) - -#define SDIF_CTRL_SEND_CCSD_MASK (0x200U) -#define SDIF_CTRL_SEND_CCSD_SHIFT (9U) -/*! SEND_CCSD - Send ccsd. - */ -#define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK) - -#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U) -#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U) -/*! SEND_AUTO_STOP_CCSD - Send auto stop ccsd. - */ -#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK) - -#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U) -#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U) -/*! CEATA_DEVICE_INTERRUPT_STATUS - CEATA device interrupt status. - */ -#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK) - -#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U) -#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U) -/*! CARD_VOLTAGE_A0 - Controls the state of the SD_VOLT0 pin. - */ -#define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK) - -#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U) -#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U) -/*! CARD_VOLTAGE_A1 - Controls the state of the SD_VOLT1 pin. - */ -#define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK) - -#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U) -#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U) -/*! CARD_VOLTAGE_A2 - Controls the state of the SD_VOLT2 pin. - */ -#define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK) - -#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U) -#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U) -/*! USE_INTERNAL_DMAC - SD/MMC DMA use. - */ -#define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) -/*! @} */ - -/*! @name PWREN - Power Enable register */ -/*! @{ */ - -#define SDIF_PWREN_POWER_ENABLE0_MASK (0x1U) -#define SDIF_PWREN_POWER_ENABLE0_SHIFT (0U) -/*! POWER_ENABLE0 - Power on/off switch for card 0; once power is turned on, software should wait - * for regulator/switch ramp-up time before trying to initialize card 0. - */ -#define SDIF_PWREN_POWER_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE0_SHIFT)) & SDIF_PWREN_POWER_ENABLE0_MASK) - -#define SDIF_PWREN_POWER_ENABLE1_MASK (0x2U) -#define SDIF_PWREN_POWER_ENABLE1_SHIFT (1U) -/*! POWER_ENABLE1 - Power on/off switch for card 1; once power is turned on, software should wait - * for regulator/switch ramp-up time before trying to initialize card 1. - */ -#define SDIF_PWREN_POWER_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE1_SHIFT)) & SDIF_PWREN_POWER_ENABLE1_MASK) -/*! @} */ - -/*! @name CLKDIV - Clock Divider register */ -/*! @{ */ - -#define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU) -#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U) -/*! CLK_DIVIDER0 - Clock divider-0 value. - */ -#define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK) -/*! @} */ - -/*! @name CLKENA - Clock Enable register */ -/*! @{ */ - -#define SDIF_CLKENA_CCLK0_ENABLE_MASK (0x1U) -#define SDIF_CLKENA_CCLK0_ENABLE_SHIFT (0U) -/*! CCLK0_ENABLE - Clock-enable control for SD card 0 clock. - */ -#define SDIF_CLKENA_CCLK0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK0_ENABLE_MASK) - -#define SDIF_CLKENA_CCLK1_ENABLE_MASK (0x2U) -#define SDIF_CLKENA_CCLK1_ENABLE_SHIFT (1U) -/*! CCLK1_ENABLE - Clock-enable control for SD card 1 clock. - */ -#define SDIF_CLKENA_CCLK1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK1_ENABLE_MASK) - -#define SDIF_CLKENA_CCLK0_LOW_POWER_MASK (0x10000U) -#define SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT (16U) -/*! CCLK0_LOW_POWER - Low-power control for SD card 0 clock. - */ -#define SDIF_CLKENA_CCLK0_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK0_LOW_POWER_MASK) - -#define SDIF_CLKENA_CCLK1_LOW_POWER_MASK (0x20000U) -#define SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT (17U) -/*! CCLK1_LOW_POWER - Low-power control for SD card 1 clock. - */ -#define SDIF_CLKENA_CCLK1_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK1_LOW_POWER_MASK) -/*! @} */ - -/*! @name TMOUT - Time-out register */ -/*! @{ */ - -#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU) -#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U) -/*! RESPONSE_TIMEOUT - Response time-out value. - */ -#define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK) - -#define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U) -#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U) -/*! DATA_TIMEOUT - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. - */ -#define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK) -/*! @} */ - -/*! @name CTYPE - Card Type register */ -/*! @{ */ - -#define SDIF_CTYPE_CARD0_WIDTH0_MASK (0x1U) -#define SDIF_CTYPE_CARD0_WIDTH0_SHIFT (0U) -/*! CARD0_WIDTH0 - Indicates if card 0 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit - * modes only work when 8-bit mode in CARD0_WIDTH1 is not enabled (bit 16 in this register is set - * to 0). - */ -#define SDIF_CTYPE_CARD0_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH0_MASK) - -#define SDIF_CTYPE_CARD1_WIDTH0_MASK (0x2U) -#define SDIF_CTYPE_CARD1_WIDTH0_SHIFT (1U) -/*! CARD1_WIDTH0 - Indicates if card 1 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit - * modes only work when 8-bit mode in CARD1_WIDTH1 is not enabled (bit 16 in this register is set - * to 0). - */ -#define SDIF_CTYPE_CARD1_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH0_MASK) - -#define SDIF_CTYPE_CARD0_WIDTH1_MASK (0x10000U) -#define SDIF_CTYPE_CARD0_WIDTH1_SHIFT (16U) -/*! CARD0_WIDTH1 - Indicates if card 0 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. - */ -#define SDIF_CTYPE_CARD0_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH1_MASK) - -#define SDIF_CTYPE_CARD1_WIDTH1_MASK (0x20000U) -#define SDIF_CTYPE_CARD1_WIDTH1_SHIFT (17U) -/*! CARD1_WIDTH1 - Indicates if card 1 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. - */ -#define SDIF_CTYPE_CARD1_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH1_MASK) -/*! @} */ - -/*! @name BLKSIZ - Block Size register */ -/*! @{ */ - -#define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU) -#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U) -/*! BLOCK_SIZE - Block size. - */ -#define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK) -/*! @} */ - -/*! @name BYTCNT - Byte Count register */ -/*! @{ */ - -#define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU) -#define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U) -/*! BYTE_COUNT - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. - */ -#define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK) -/*! @} */ - -/*! @name INTMASK - Interrupt Mask register */ -/*! @{ */ - -#define SDIF_INTMASK_CDET_MASK (0x1U) -#define SDIF_INTMASK_CDET_SHIFT (0U) -/*! CDET - Card detect. - */ -#define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK) - -#define SDIF_INTMASK_RE_MASK (0x2U) -#define SDIF_INTMASK_RE_SHIFT (1U) -/*! RE - Response error. - */ -#define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK) - -#define SDIF_INTMASK_CDONE_MASK (0x4U) -#define SDIF_INTMASK_CDONE_SHIFT (2U) -/*! CDONE - Command done. - */ -#define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK) - -#define SDIF_INTMASK_DTO_MASK (0x8U) -#define SDIF_INTMASK_DTO_SHIFT (3U) -/*! DTO - Data transfer over. - */ -#define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK) - -#define SDIF_INTMASK_TXDR_MASK (0x10U) -#define SDIF_INTMASK_TXDR_SHIFT (4U) -/*! TXDR - Transmit FIFO data request. - */ -#define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK) - -#define SDIF_INTMASK_RXDR_MASK (0x20U) -#define SDIF_INTMASK_RXDR_SHIFT (5U) -/*! RXDR - Receive FIFO data request. - */ -#define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK) - -#define SDIF_INTMASK_RCRC_MASK (0x40U) -#define SDIF_INTMASK_RCRC_SHIFT (6U) -/*! RCRC - Response CRC error. - */ -#define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK) - -#define SDIF_INTMASK_DCRC_MASK (0x80U) -#define SDIF_INTMASK_DCRC_SHIFT (7U) -/*! DCRC - Data CRC error. - */ -#define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK) - -#define SDIF_INTMASK_RTO_MASK (0x100U) -#define SDIF_INTMASK_RTO_SHIFT (8U) -/*! RTO - Response time-out. - */ -#define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK) - -#define SDIF_INTMASK_DRTO_MASK (0x200U) -#define SDIF_INTMASK_DRTO_SHIFT (9U) -/*! DRTO - Data read time-out. - */ -#define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK) - -#define SDIF_INTMASK_HTO_MASK (0x400U) -#define SDIF_INTMASK_HTO_SHIFT (10U) -/*! HTO - Data starvation-by-host time-out (HTO). - */ -#define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK) - -#define SDIF_INTMASK_FRUN_MASK (0x800U) -#define SDIF_INTMASK_FRUN_SHIFT (11U) -/*! FRUN - FIFO underrun/overrun error. - */ -#define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK) - -#define SDIF_INTMASK_HLE_MASK (0x1000U) -#define SDIF_INTMASK_HLE_SHIFT (12U) -/*! HLE - Hardware locked write error. - */ -#define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK) - -#define SDIF_INTMASK_SBE_MASK (0x2000U) -#define SDIF_INTMASK_SBE_SHIFT (13U) -/*! SBE - Start-bit error. - */ -#define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK) - -#define SDIF_INTMASK_ACD_MASK (0x4000U) -#define SDIF_INTMASK_ACD_SHIFT (14U) -/*! ACD - Auto command done. - */ -#define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK) - -#define SDIF_INTMASK_EBE_MASK (0x8000U) -#define SDIF_INTMASK_EBE_SHIFT (15U) -/*! EBE - End-bit error (read)/Write no CRC. - */ -#define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK) - -#define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U) -#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U) -/*! SDIO_INT_MASK - Mask SDIO interrupt. - */ -#define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK) -/*! @} */ - -/*! @name CMDARG - Command Argument register */ -/*! @{ */ - -#define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU) -#define SDIF_CMDARG_CMD_ARG_SHIFT (0U) -/*! CMD_ARG - Value indicates command argument to be passed to card. - */ -#define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK) -/*! @} */ - -/*! @name CMD - Command register */ -/*! @{ */ - -#define SDIF_CMD_CMD_INDEX_MASK (0x3FU) -#define SDIF_CMD_CMD_INDEX_SHIFT (0U) -/*! CMD_INDEX - Command index. - */ -#define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK) - -#define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U) -#define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U) -/*! RESPONSE_EXPECT - Response expect. - */ -#define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK) - -#define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U) -#define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U) -/*! RESPONSE_LENGTH - Response length. - */ -#define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK) - -#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U) -#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U) -/*! CHECK_RESPONSE_CRC - Check response CRC. - */ -#define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK) - -#define SDIF_CMD_DATA_EXPECTED_MASK (0x200U) -#define SDIF_CMD_DATA_EXPECTED_SHIFT (9U) -/*! DATA_EXPECTED - Data expected. - */ -#define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK) - -#define SDIF_CMD_READ_WRITE_MASK (0x400U) -#define SDIF_CMD_READ_WRITE_SHIFT (10U) -/*! READ_WRITE - read/write. - */ -#define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK) - -#define SDIF_CMD_TRANSFER_MODE_MASK (0x800U) -#define SDIF_CMD_TRANSFER_MODE_SHIFT (11U) -/*! TRANSFER_MODE - Transfer mode. - */ -#define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK) - -#define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U) -#define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U) -/*! SEND_AUTO_STOP - Send auto stop. - */ -#define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK) - -#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U) -#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U) -/*! WAIT_PRVDATA_COMPLETE - Wait prvdata complete. - */ -#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK) - -#define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U) -#define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U) -/*! STOP_ABORT_CMD - Stop abort command. - */ -#define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK) - -#define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U) -#define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U) -/*! SEND_INITIALIZATION - Send initialization. - */ -#define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK) - -#define SDIF_CMD_CARD_NUMBER_MASK (0x1F0000U) -#define SDIF_CMD_CARD_NUMBER_SHIFT (16U) -/*! CARD_NUMBER - Specifies the card number of SDCARD for which the current Command is being executed - * 0b00000..Command will be execute on SDCARD 0 - * 0b00001..Command will be execute on SDCARD 1 - */ -#define SDIF_CMD_CARD_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CARD_NUMBER_SHIFT)) & SDIF_CMD_CARD_NUMBER_MASK) - -#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U) -#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U) -/*! UPDATE_CLOCK_REGISTERS_ONLY - Update clock registers only. - */ -#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK) - -#define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U) -#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U) -/*! READ_CEATA_DEVICE - Read ceata device. - */ -#define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK) - -#define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U) -#define SDIF_CMD_CCS_EXPECTED_SHIFT (23U) -/*! CCS_EXPECTED - CCS expected. - */ -#define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK) - -#define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U) -#define SDIF_CMD_ENABLE_BOOT_SHIFT (24U) -/*! ENABLE_BOOT - Enable Boot - this bit should be set only for mandatory boot mode. - */ -#define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK) - -#define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U) -#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U) -/*! EXPECT_BOOT_ACK - Expect Boot Acknowledge. - */ -#define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK) - -#define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U) -#define SDIF_CMD_DISABLE_BOOT_SHIFT (26U) -/*! DISABLE_BOOT - Disable Boot. - */ -#define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK) - -#define SDIF_CMD_BOOT_MODE_MASK (0x8000000U) -#define SDIF_CMD_BOOT_MODE_SHIFT (27U) -/*! BOOT_MODE - Boot Mode. - */ -#define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK) - -#define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U) -#define SDIF_CMD_VOLT_SWITCH_SHIFT (28U) -/*! VOLT_SWITCH - Voltage switch bit. - */ -#define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK) - -#define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U) -#define SDIF_CMD_USE_HOLD_REG_SHIFT (29U) -/*! USE_HOLD_REG - Use Hold Register. - */ -#define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK) - -#define SDIF_CMD_START_CMD_MASK (0x80000000U) -#define SDIF_CMD_START_CMD_SHIFT (31U) -/*! START_CMD - Start command. - */ -#define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK) -/*! @} */ - -/*! @name RESP - Response register */ -/*! @{ */ - -#define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU) -#define SDIF_RESP_RESPONSE_SHIFT (0U) -/*! RESPONSE - Bits of response. - */ -#define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK) -/*! @} */ - -/* The count of SDIF_RESP */ -#define SDIF_RESP_COUNT (4U) - -/*! @name MINTSTS - Masked Interrupt Status register */ -/*! @{ */ - -#define SDIF_MINTSTS_CDET_MASK (0x1U) -#define SDIF_MINTSTS_CDET_SHIFT (0U) -/*! CDET - Card detect. - */ -#define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK) - -#define SDIF_MINTSTS_RE_MASK (0x2U) -#define SDIF_MINTSTS_RE_SHIFT (1U) -/*! RE - Response error. - */ -#define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK) - -#define SDIF_MINTSTS_CDONE_MASK (0x4U) -#define SDIF_MINTSTS_CDONE_SHIFT (2U) -/*! CDONE - Command done. - */ -#define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK) - -#define SDIF_MINTSTS_DTO_MASK (0x8U) -#define SDIF_MINTSTS_DTO_SHIFT (3U) -/*! DTO - Data transfer over. - */ -#define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK) - -#define SDIF_MINTSTS_TXDR_MASK (0x10U) -#define SDIF_MINTSTS_TXDR_SHIFT (4U) -/*! TXDR - Transmit FIFO data request. - */ -#define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK) - -#define SDIF_MINTSTS_RXDR_MASK (0x20U) -#define SDIF_MINTSTS_RXDR_SHIFT (5U) -/*! RXDR - Receive FIFO data request. - */ -#define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK) - -#define SDIF_MINTSTS_RCRC_MASK (0x40U) -#define SDIF_MINTSTS_RCRC_SHIFT (6U) -/*! RCRC - Response CRC error. - */ -#define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK) - -#define SDIF_MINTSTS_DCRC_MASK (0x80U) -#define SDIF_MINTSTS_DCRC_SHIFT (7U) -/*! DCRC - Data CRC error. - */ -#define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK) - -#define SDIF_MINTSTS_RTO_MASK (0x100U) -#define SDIF_MINTSTS_RTO_SHIFT (8U) -/*! RTO - Response time-out. - */ -#define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK) - -#define SDIF_MINTSTS_DRTO_MASK (0x200U) -#define SDIF_MINTSTS_DRTO_SHIFT (9U) -/*! DRTO - Data read time-out. - */ -#define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK) - -#define SDIF_MINTSTS_HTO_MASK (0x400U) -#define SDIF_MINTSTS_HTO_SHIFT (10U) -/*! HTO - Data starvation-by-host time-out (HTO). - */ -#define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK) - -#define SDIF_MINTSTS_FRUN_MASK (0x800U) -#define SDIF_MINTSTS_FRUN_SHIFT (11U) -/*! FRUN - FIFO underrun/overrun error. - */ -#define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK) - -#define SDIF_MINTSTS_HLE_MASK (0x1000U) -#define SDIF_MINTSTS_HLE_SHIFT (12U) -/*! HLE - Hardware locked write error. - */ -#define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK) - -#define SDIF_MINTSTS_SBE_MASK (0x2000U) -#define SDIF_MINTSTS_SBE_SHIFT (13U) -/*! SBE - Start-bit error. - */ -#define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK) - -#define SDIF_MINTSTS_ACD_MASK (0x4000U) -#define SDIF_MINTSTS_ACD_SHIFT (14U) -/*! ACD - Auto command done. - */ -#define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK) - -#define SDIF_MINTSTS_EBE_MASK (0x8000U) -#define SDIF_MINTSTS_EBE_SHIFT (15U) -/*! EBE - End-bit error (read)/write no CRC. - */ -#define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK) - -#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U) -#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U) -/*! SDIO_INTERRUPT - Interrupt from SDIO card. - */ -#define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK) -/*! @} */ - -/*! @name RINTSTS - Raw Interrupt Status register */ -/*! @{ */ - -#define SDIF_RINTSTS_CDET_MASK (0x1U) -#define SDIF_RINTSTS_CDET_SHIFT (0U) -/*! CDET - Card detect. - */ -#define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK) - -#define SDIF_RINTSTS_RE_MASK (0x2U) -#define SDIF_RINTSTS_RE_SHIFT (1U) -/*! RE - Response error. - */ -#define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK) - -#define SDIF_RINTSTS_CDONE_MASK (0x4U) -#define SDIF_RINTSTS_CDONE_SHIFT (2U) -/*! CDONE - Command done. - */ -#define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK) - -#define SDIF_RINTSTS_DTO_MASK (0x8U) -#define SDIF_RINTSTS_DTO_SHIFT (3U) -/*! DTO - Data transfer over. - */ -#define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK) - -#define SDIF_RINTSTS_TXDR_MASK (0x10U) -#define SDIF_RINTSTS_TXDR_SHIFT (4U) -/*! TXDR - Transmit FIFO data request. - */ -#define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK) - -#define SDIF_RINTSTS_RXDR_MASK (0x20U) -#define SDIF_RINTSTS_RXDR_SHIFT (5U) -/*! RXDR - Receive FIFO data request. - */ -#define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK) - -#define SDIF_RINTSTS_RCRC_MASK (0x40U) -#define SDIF_RINTSTS_RCRC_SHIFT (6U) -/*! RCRC - Response CRC error. - */ -#define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK) - -#define SDIF_RINTSTS_DCRC_MASK (0x80U) -#define SDIF_RINTSTS_DCRC_SHIFT (7U) -/*! DCRC - Data CRC error. - */ -#define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK) - -#define SDIF_RINTSTS_RTO_BAR_MASK (0x100U) -#define SDIF_RINTSTS_RTO_BAR_SHIFT (8U) -/*! RTO_BAR - Response time-out (RTO)/Boot Ack Received (BAR). - */ -#define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK) - -#define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U) -#define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U) -/*! DRTO_BDS - Data read time-out (DRTO)/Boot Data Start (BDS). - */ -#define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK) - -#define SDIF_RINTSTS_HTO_MASK (0x400U) -#define SDIF_RINTSTS_HTO_SHIFT (10U) -/*! HTO - Data starvation-by-host time-out (HTO). - */ -#define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK) - -#define SDIF_RINTSTS_FRUN_MASK (0x800U) -#define SDIF_RINTSTS_FRUN_SHIFT (11U) -/*! FRUN - FIFO underrun/overrun error. - */ -#define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK) - -#define SDIF_RINTSTS_HLE_MASK (0x1000U) -#define SDIF_RINTSTS_HLE_SHIFT (12U) -/*! HLE - Hardware locked write error. - */ -#define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK) - -#define SDIF_RINTSTS_SBE_MASK (0x2000U) -#define SDIF_RINTSTS_SBE_SHIFT (13U) -/*! SBE - Start-bit error. - */ -#define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK) - -#define SDIF_RINTSTS_ACD_MASK (0x4000U) -#define SDIF_RINTSTS_ACD_SHIFT (14U) -/*! ACD - Auto command done. - */ -#define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK) - -#define SDIF_RINTSTS_EBE_MASK (0x8000U) -#define SDIF_RINTSTS_EBE_SHIFT (15U) -/*! EBE - End-bit error (read)/write no CRC. - */ -#define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK) - -#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U) -#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U) -/*! SDIO_INTERRUPT - Interrupt from SDIO card. - */ -#define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK) -/*! @} */ - -/*! @name STATUS - Status register */ -/*! @{ */ - -#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U) -#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U) -/*! FIFO_RX_WATERMARK - FIFO reached Receive watermark level; not qualified with data transfer. - */ -#define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK) - -#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U) -#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U) -/*! FIFO_TX_WATERMARK - FIFO reached Transmit watermark level; not qualified with data transfer. - */ -#define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK) - -#define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U) -#define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U) -/*! FIFO_EMPTY - FIFO is empty status. - */ -#define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK) - -#define SDIF_STATUS_FIFO_FULL_MASK (0x8U) -#define SDIF_STATUS_FIFO_FULL_SHIFT (3U) -/*! FIFO_FULL - FIFO is full status. - */ -#define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK) - -#define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U) -#define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U) -/*! CMDFSMSTATES - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx - * cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - - * Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp - * crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The - * command FSM state is represented using 19 bits. - */ -#define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK) - -#define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U) -#define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U) -/*! DATA_3_STATUS - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present. - */ -#define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK) - -#define SDIF_STATUS_DATA_BUSY_MASK (0x200U) -#define SDIF_STATUS_DATA_BUSY_SHIFT (9U) -/*! DATA_BUSY - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy. - */ -#define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK) - -#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U) -#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U) -/*! DATA_STATE_MC_BUSY - Data transmit or receive state-machine is busy. - */ -#define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK) - -#define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) -#define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U) -/*! RESPONSE_INDEX - Index of previous response, including any auto-stop sent by core. - */ -#define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK) - -#define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U) -#define SDIF_STATUS_FIFO_COUNT_SHIFT (17U) -/*! FIFO_COUNT - FIFO count - Number of filled locations in FIFO. - */ -#define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK) - -#define SDIF_STATUS_DMA_ACK_MASK (0x40000000U) -#define SDIF_STATUS_DMA_ACK_SHIFT (30U) -/*! DMA_ACK - DMA acknowledge signal state. - */ -#define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK) - -#define SDIF_STATUS_DMA_REQ_MASK (0x80000000U) -#define SDIF_STATUS_DMA_REQ_SHIFT (31U) -/*! DMA_REQ - DMA request signal state. - */ -#define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK) -/*! @} */ - -/*! @name FIFOTH - FIFO Threshold Watermark register */ -/*! @{ */ - -#define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU) -#define SDIF_FIFOTH_TX_WMARK_SHIFT (0U) -/*! TX_WMARK - FIFO threshold watermark level when transmitting data to card. - */ -#define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK) - -#define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U) -#define SDIF_FIFOTH_RX_WMARK_SHIFT (16U) -/*! RX_WMARK - FIFO threshold watermark level when receiving data to card. - */ -#define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK) - -#define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U) -#define SDIF_FIFOTH_DMA_MTS_SHIFT (28U) -/*! DMA_MTS - Burst size of multiple transaction; should be programmed same as DW-DMA controller - * multiple-transaction-size SRC/DEST_MSIZE. - */ -#define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK) -/*! @} */ - -/*! @name CDETECT - Card Detect register */ -/*! @{ */ - -#define SDIF_CDETECT_CARD0_DETECT_MASK (0x1U) -#define SDIF_CDETECT_CARD0_DETECT_SHIFT (0U) -/*! CARD0_DETECT - Card 0 detect - */ -#define SDIF_CDETECT_CARD0_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD0_DETECT_SHIFT)) & SDIF_CDETECT_CARD0_DETECT_MASK) - -#define SDIF_CDETECT_CARD1_DETECT_MASK (0x2U) -#define SDIF_CDETECT_CARD1_DETECT_SHIFT (1U) -/*! CARD1_DETECT - Card 1 detect - */ -#define SDIF_CDETECT_CARD1_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD1_DETECT_SHIFT)) & SDIF_CDETECT_CARD1_DETECT_MASK) -/*! @} */ - -/*! @name WRTPRT - Write Protect register */ -/*! @{ */ - -#define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U) -#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U) -/*! WRITE_PROTECT - Write protect. - */ -#define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK) -/*! @} */ - -/*! @name TCBCNT - Transferred CIU Card Byte Count register */ -/*! @{ */ - -#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU) -#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U) -/*! TRANS_CARD_BYTE_COUNT - Number of bytes transferred by CIU unit to card. - */ -#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK) -/*! @} */ - -/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */ -/*! @{ */ - -#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU) -#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U) -/*! TRANS_FIFO_BYTE_COUNT - Number of bytes transferred between Host/DMA memory and BIU FIFO. - */ -#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK) -/*! @} */ - -/*! @name DEBNCE - Debounce Count register */ -/*! @{ */ - -#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU) -#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U) -/*! DEBOUNCE_COUNT - Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms. - */ -#define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK) -/*! @} */ - -/*! @name RST_N - Hardware Reset */ -/*! @{ */ - -#define SDIF_RST_N_CARD_RESET_MASK (0x1U) -#define SDIF_RST_N_CARD_RESET_SHIFT (0U) -/*! CARD_RESET - Hardware reset. - */ -#define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK) -/*! @} */ - -/*! @name BMOD - Bus Mode register */ -/*! @{ */ - -#define SDIF_BMOD_SWR_MASK (0x1U) -#define SDIF_BMOD_SWR_SHIFT (0U) -/*! SWR - Software Reset. - */ -#define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK) - -#define SDIF_BMOD_FB_MASK (0x2U) -#define SDIF_BMOD_FB_SHIFT (1U) -/*! FB - Fixed Burst. - */ -#define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK) - -#define SDIF_BMOD_DSL_MASK (0x7CU) -#define SDIF_BMOD_DSL_SHIFT (2U) -/*! DSL - Descriptor Skip Length. - */ -#define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK) - -#define SDIF_BMOD_DE_MASK (0x80U) -#define SDIF_BMOD_DE_SHIFT (7U) -/*! DE - SD/MMC DMA Enable. - */ -#define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK) - -#define SDIF_BMOD_PBL_MASK (0x700U) -#define SDIF_BMOD_PBL_SHIFT (8U) -/*! PBL - Programmable Burst Length. - */ -#define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK) -/*! @} */ - -/*! @name PLDMND - Poll Demand register */ -/*! @{ */ - -#define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU) -#define SDIF_PLDMND_PD_SHIFT (0U) -/*! PD - Poll Demand. - */ -#define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK) -/*! @} */ - -/*! @name DBADDR - Descriptor List Base Address register */ -/*! @{ */ - -#define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU) -#define SDIF_DBADDR_SDL_SHIFT (0U) -/*! SDL - Start of Descriptor List. - */ -#define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK) -/*! @} */ - -/*! @name IDSTS - Internal DMAC Status register */ -/*! @{ */ - -#define SDIF_IDSTS_TI_MASK (0x1U) -#define SDIF_IDSTS_TI_SHIFT (0U) -/*! TI - Transmit Interrupt. - */ -#define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK) - -#define SDIF_IDSTS_RI_MASK (0x2U) -#define SDIF_IDSTS_RI_SHIFT (1U) -/*! RI - Receive Interrupt. - */ -#define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK) - -#define SDIF_IDSTS_FBE_MASK (0x4U) -#define SDIF_IDSTS_FBE_SHIFT (2U) -/*! FBE - Fatal Bus Error Interrupt. - */ -#define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK) - -#define SDIF_IDSTS_DU_MASK (0x10U) -#define SDIF_IDSTS_DU_SHIFT (4U) -/*! DU - Descriptor Unavailable Interrupt. - */ -#define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK) - -#define SDIF_IDSTS_CES_MASK (0x20U) -#define SDIF_IDSTS_CES_SHIFT (5U) -/*! CES - Card Error Summary. - */ -#define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK) - -#define SDIF_IDSTS_NIS_MASK (0x100U) -#define SDIF_IDSTS_NIS_SHIFT (8U) -/*! NIS - Normal Interrupt Summary. - */ -#define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK) - -#define SDIF_IDSTS_AIS_MASK (0x200U) -#define SDIF_IDSTS_AIS_SHIFT (9U) -/*! AIS - Abnormal Interrupt Summary. - */ -#define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK) - -#define SDIF_IDSTS_EB_MASK (0x1C00U) -#define SDIF_IDSTS_EB_SHIFT (10U) -/*! EB - Error Bits. - */ -#define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK) - -#define SDIF_IDSTS_FSM_MASK (0x1E000U) -#define SDIF_IDSTS_FSM_SHIFT (13U) -/*! FSM - DMAC state machine present state. - */ -#define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK) -/*! @} */ - -/*! @name IDINTEN - Internal DMAC Interrupt Enable register */ -/*! @{ */ - -#define SDIF_IDINTEN_TI_MASK (0x1U) -#define SDIF_IDINTEN_TI_SHIFT (0U) -/*! TI - Transmit Interrupt Enable. - */ -#define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK) - -#define SDIF_IDINTEN_RI_MASK (0x2U) -#define SDIF_IDINTEN_RI_SHIFT (1U) -/*! RI - Receive Interrupt Enable. - */ -#define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK) - -#define SDIF_IDINTEN_FBE_MASK (0x4U) -#define SDIF_IDINTEN_FBE_SHIFT (2U) -/*! FBE - Fatal Bus Error Enable. - */ -#define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK) - -#define SDIF_IDINTEN_DU_MASK (0x10U) -#define SDIF_IDINTEN_DU_SHIFT (4U) -/*! DU - Descriptor Unavailable Interrupt. - */ -#define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK) - -#define SDIF_IDINTEN_CES_MASK (0x20U) -#define SDIF_IDINTEN_CES_SHIFT (5U) -/*! CES - Card Error summary Interrupt Enable. - */ -#define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK) - -#define SDIF_IDINTEN_NIS_MASK (0x100U) -#define SDIF_IDINTEN_NIS_SHIFT (8U) -/*! NIS - Normal Interrupt Summary Enable. - */ -#define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK) - -#define SDIF_IDINTEN_AIS_MASK (0x200U) -#define SDIF_IDINTEN_AIS_SHIFT (9U) -/*! AIS - Abnormal Interrupt Summary Enable. - */ -#define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK) -/*! @} */ - -/*! @name DSCADDR - Current Host Descriptor Address register */ -/*! @{ */ - -#define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU) -#define SDIF_DSCADDR_HDA_SHIFT (0U) -/*! HDA - Host Descriptor Address Pointer. - */ -#define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK) -/*! @} */ - -/*! @name BUFADDR - Current Buffer Descriptor Address register */ -/*! @{ */ - -#define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU) -#define SDIF_BUFADDR_HBA_SHIFT (0U) -/*! HBA - Host Buffer Address Pointer. - */ -#define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK) -/*! @} */ - -/*! @name CARDTHRCTL - Card Threshold Control */ -/*! @{ */ - -#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U) -#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U) -/*! CARDRDTHREN - Card Read Threshold Enable. - */ -#define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK) - -#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U) -#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U) -/*! BSYCLRINTEN - Busy Clear Interrupt Enable. - */ -#define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK) - -#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U) -#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U) -/*! CARDTHRESHOLD - Card Threshold size. - */ -#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK) -/*! @} */ - -/*! @name BACKENDPWR - Power control */ -/*! @{ */ - -#define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U) -#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U) -/*! BACKENDPWR - Back-end Power control for card application. - */ -#define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK) -/*! @} */ - -/*! @name FIFO - SDIF FIFO */ -/*! @{ */ - -#define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU) -#define SDIF_FIFO_DATA_SHIFT (0U) -/*! DATA - SDIF FIFO. - */ -#define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK) -/*! @} */ - -/* The count of SDIF_FIFO */ -#define SDIF_FIFO_COUNT (64U) - - -/*! - * @} - */ /* end of group SDIF_Register_Masks */ - - -/* SDIF - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SDIF base address */ - #define SDIF_BASE (0x5009B000u) - /** Peripheral SDIF base address */ - #define SDIF_BASE_NS (0x4009B000u) - /** Peripheral SDIF base pointer */ - #define SDIF ((SDIF_Type *)SDIF_BASE) - /** Peripheral SDIF base pointer */ - #define SDIF_NS ((SDIF_Type *)SDIF_BASE_NS) - /** Array initializer of SDIF peripheral base addresses */ - #define SDIF_BASE_ADDRS { SDIF_BASE } - /** Array initializer of SDIF peripheral base pointers */ - #define SDIF_BASE_PTRS { SDIF } - /** Array initializer of SDIF peripheral base addresses */ - #define SDIF_BASE_ADDRS_NS { SDIF_BASE_NS } - /** Array initializer of SDIF peripheral base pointers */ - #define SDIF_BASE_PTRS_NS { SDIF_NS } -#else - /** Peripheral SDIF base address */ - #define SDIF_BASE (0x4009B000u) - /** Peripheral SDIF base pointer */ - #define SDIF ((SDIF_Type *)SDIF_BASE) - /** Array initializer of SDIF peripheral base addresses */ - #define SDIF_BASE_ADDRS { SDIF_BASE } - /** Array initializer of SDIF peripheral base pointers */ - #define SDIF_BASE_PTRS { SDIF } -#endif -/** Interrupt vectors for the SDIF peripheral type */ -#define SDIF_IRQS { SDIO_IRQn } - -/*! - * @} - */ /* end of group SDIF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer - * @{ - */ - -/** SPI - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[1024]; - __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ - __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ - __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ - __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ - __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ - __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ - uint8_t RESERVED_2[2516]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_6[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_7[4]; - __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ - uint8_t RESERVED_8[432]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} SPI_Type; - -/* ---------------------------------------------------------------------------- - -- SPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Register_Masks SPI Register Masks - * @{ - */ - -/*! @name CFG - SPI Configuration register */ -/*! @{ */ - -#define SPI_CFG_ENABLE_MASK (0x1U) -#define SPI_CFG_ENABLE_SHIFT (0U) -/*! ENABLE - SPI enable. - * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. - * 0b1..Enabled. The SPI is enabled for operation. - */ -#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) - -#define SPI_CFG_MASTER_MASK (0x4U) -#define SPI_CFG_MASTER_SHIFT (2U) -/*! MASTER - Master mode select. - * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. - * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. - */ -#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) - -#define SPI_CFG_LSBF_MASK (0x8U) -#define SPI_CFG_LSBF_SHIFT (3U) -/*! LSBF - LSB First mode enable. - * 0b0..Standard. Data is transmitted and received in standard MSB first order. - * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). - */ -#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) - -#define SPI_CFG_CPHA_MASK (0x10U) -#define SPI_CFG_CPHA_SHIFT (4U) -/*! CPHA - Clock Phase select. - * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock - * changes away from the rest state). Data is changed on the following edge. - * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock - * changes away from the rest state). Data is captured on the following edge. - */ -#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) - -#define SPI_CFG_CPOL_MASK (0x20U) -#define SPI_CFG_CPOL_SHIFT (5U) -/*! CPOL - Clock Polarity select. - * 0b0..Low. The rest state of the clock (between transfers) is low. - * 0b1..High. The rest state of the clock (between transfers) is high. - */ -#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) - -#define SPI_CFG_LOOP_MASK (0x80U) -#define SPI_CFG_LOOP_SHIFT (7U) -/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit - * and receive data connected together to allow simple software testing. - * 0b0..Disabled. - * 0b1..Enabled. - */ -#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) - -#define SPI_CFG_SPOL0_MASK (0x100U) -#define SPI_CFG_SPOL0_SHIFT (8U) -/*! SPOL0 - SSEL0 Polarity select. - * 0b0..Low. The SSEL0 pin is active low. - * 0b1..High. The SSEL0 pin is active high. - */ -#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) - -#define SPI_CFG_SPOL1_MASK (0x200U) -#define SPI_CFG_SPOL1_SHIFT (9U) -/*! SPOL1 - SSEL1 Polarity select. - * 0b0..Low. The SSEL1 pin is active low. - * 0b1..High. The SSEL1 pin is active high. - */ -#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) - -#define SPI_CFG_SPOL2_MASK (0x400U) -#define SPI_CFG_SPOL2_SHIFT (10U) -/*! SPOL2 - SSEL2 Polarity select. - * 0b0..Low. The SSEL2 pin is active low. - * 0b1..High. The SSEL2 pin is active high. - */ -#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) - -#define SPI_CFG_SPOL3_MASK (0x800U) -#define SPI_CFG_SPOL3_SHIFT (11U) -/*! SPOL3 - SSEL3 Polarity select. - * 0b0..Low. The SSEL3 pin is active low. - * 0b1..High. The SSEL3 pin is active high. - */ -#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) -/*! @} */ - -/*! @name DLY - SPI Delay register */ -/*! @{ */ - -#define SPI_DLY_PRE_DELAY_MASK (0xFU) -#define SPI_DLY_PRE_DELAY_SHIFT (0U) -/*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data - * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This - * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI - * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are - * inserted. - */ -#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) - -#define SPI_DLY_POST_DELAY_MASK (0xF0U) -#define SPI_DLY_POST_DELAY_SHIFT (4U) -/*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL - * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock - * times are inserted. 0xF = 15 SPI clock times are inserted. - */ -#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) - -#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) -#define SPI_DLY_FRAME_DELAY_SHIFT (8U) -/*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current - * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 - * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock - * times are inserted. - */ -#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) - -#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) -#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) -/*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between - * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 - * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that - * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 - * SPI clock times. - */ -#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) -/*! @} */ - -/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ -/*! @{ */ - -#define SPI_STAT_SSA_MASK (0x10U) -#define SPI_STAT_SSA_SHIFT (4U) -/*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from - * deasserted to asserted, in both master and slave modes. This allows determining when the SPI - * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a - * slave mode access begins. This flag is cleared by software. - */ -#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) - -#define SPI_STAT_SSD_MASK (0x20U) -#define SPI_STAT_SSD_SHIFT (5U) -/*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to - * deasserted, in both master and slave modes. This allows determining when the SPI - * transmit/receive functions become idle. This flag is cleared by software. - */ -#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) - -#define SPI_STAT_STALLED_MASK (0x40U) -#define SPI_STAT_STALLED_SHIFT (6U) -/*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition. - */ -#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) - -#define SPI_STAT_ENDTRANSFER_MASK (0x80U) -#define SPI_STAT_ENDTRANSFER_SHIFT (7U) -/*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current - * transfer when the transmitter finishes any activity already in progress, as if the EOT flag - * had been set prior to the last transmission. This capability is included to support cases where - * it is not known when transmit data is written that it will be the end of a transfer. The bit - * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end - * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. - */ -#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) - -#define SPI_STAT_MSTIDLE_MASK (0x100U) -#define SPI_STAT_MSTIDLE_SHIFT (8U) -/*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. - * This means that the transmit holding register is empty and the transmitter is not in the - * process of sending data. - */ -#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -/*! @{ */ - -#define SPI_INTENSET_SSAEN_MASK (0x10U) -#define SPI_INTENSET_SSAEN_SHIFT (4U) -/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. - * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. - * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. - */ -#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) - -#define SPI_INTENSET_SSDEN_MASK (0x20U) -#define SPI_INTENSET_SSDEN_SHIFT (5U) -/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. - * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. - * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. - */ -#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) - -#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) -#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) -/*! MSTIDLEEN - Master idle interrupt enable. - * 0b0..No interrupt will be generated when the SPI master function is idle. - * 0b1..An interrupt will be generated when the SPI master function is fully idle. - */ -#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) -/*! @} */ - -/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ -/*! @{ */ - -#define SPI_INTENCLR_SSAEN_MASK (0x10U) -#define SPI_INTENCLR_SSAEN_SHIFT (4U) -/*! SSAEN - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) - -#define SPI_INTENCLR_SSDEN_MASK (0x20U) -#define SPI_INTENCLR_SSDEN_SHIFT (5U) -/*! SSDEN - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) - -#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) -#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) -/*! MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) -/*! @} */ - -/*! @name DIV - SPI clock Divider */ -/*! @{ */ - -#define SPI_DIV_DIVVAL_MASK (0xFFFFU) -#define SPI_DIV_DIVVAL_SHIFT (0U) -/*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the - * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, - * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results - * in FCLK/65536. - */ -#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - SPI Interrupt Status */ -/*! @{ */ - -#define SPI_INTSTAT_SSA_MASK (0x10U) -#define SPI_INTSTAT_SSA_SHIFT (4U) -/*! SSA - Slave Select Assert. - */ -#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) - -#define SPI_INTSTAT_SSD_MASK (0x20U) -#define SPI_INTSTAT_SSD_SHIFT (5U) -/*! SSD - Slave Select Deassert. - */ -#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) - -#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) -#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) -/*! MSTIDLE - Master Idle status flag. - */ -#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ - -#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) -#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) - -#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) -#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) - -#define SPI_FIFOCFG_SIZE_MASK (0x30U) -#define SPI_FIFOCFG_SIZE_SHIFT (4U) -/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 - * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - */ -#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) - -#define SPI_FIFOCFG_DMATX_MASK (0x1000U) -#define SPI_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) - -#define SPI_FIFOCFG_DMARX_MASK (0x2000U) -#define SPI_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) - -#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) -#define SPI_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in - * FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) - -#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) -#define SPI_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in - * FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) - -#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) -/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - */ -#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) - -#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) -/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - */ -#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ - -#define SPI_FIFOSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow - * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is - * needed. Cleared by writing a 1 to this bit. - */ -#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) - -#define SPI_FIFOSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA - * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - */ -#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) - -#define SPI_FIFOSTAT_PERINT_MASK (0x8U) -#define SPI_FIFOSTAT_PERINT_SHIFT (3U) -/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted - * an interrupt. The details can be found by reading the peripheral's STAT register. - */ -#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) - -#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) -/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - */ -#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) - -#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) -/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be - * written. When 0, the transmit FIFO is full and another write would cause it to overflow. - */ -#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) - -#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - */ -#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) - -#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) -#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) -/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to - * prevent the peripheral from causing an overflow. - */ -#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) - -#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY - * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at - * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be - * 0. - */ -#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) - -#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and - * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the - * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be - * 1. - */ -#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ - -#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) - -#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) - -#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) -#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled - * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to - * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO - * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX - * FIFO level decreases to 15 entries (is no longer full). - */ -#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) - -#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data - * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level - * can wake up the device just enough to perform DMA, then return to the reduced power mode. See - * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no - * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX - * FIFO has received 16 entries (has become full). - */ -#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ - -#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) -#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) - -#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) -#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) - -#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases - * to the level specified by TXLVL in the FIFOTRIG register. - */ -#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) - -#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level - * increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ - -#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) -#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) -/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) - -#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) -#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) -/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) - -#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) -/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) - -#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) -/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ - -#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. - */ -#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) - -#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. - */ -#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) - -#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO level interrupt. - */ -#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) - -#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO level interrupt. - */ -#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) - -#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) -#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) -/*! PERINT - Peripheral interrupt. - */ -#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ - -#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) -#define SPI_FIFOWR_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit data to the FIFO. - */ -#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) - -#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) -#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) -/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL0 asserted. - * 0b1..SSEL0 not asserted. - */ -#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) - -#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) -#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) -/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL1 asserted. - * 0b1..SSEL1 not asserted. - */ -#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) - -#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) -#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) -/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL2 asserted. - * 0b1..SSEL2 not asserted. - */ -#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) - -#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) -#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) -/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL3 asserted. - * 0b1..SSEL3 not asserted. - */ -#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) - -#define SPI_FIFOWR_EOT_MASK (0x100000U) -#define SPI_FIFOWR_EOT_SHIFT (20U) -/*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain - * so far at least the time specified by the Transfer_delay value in the DLY register. - * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. - * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. - */ -#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) - -#define SPI_FIFOWR_EOF_MASK (0x200000U) -#define SPI_FIFOWR_EOF_SHIFT (21U) -/*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value - * in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay - * value = 0. This control can be used as part of the support for frame lengths greater than 16 - * bits. - * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame. - * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be - * inserted before subsequent data is transmitted. - */ -#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) - -#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) -#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) -/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to - * read unneeded data from the receiver. Setting this bit simplifies the transmit process and can - * be used with the DMA. - * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit - * will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data - * is not read before new data is received. - * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received - * data. No receiver flags are generated. - */ -#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) - -#define SPI_FIFOWR_LEN_MASK (0xF000000U) -#define SPI_FIFOWR_LEN_SHIFT (24U) -/*! LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths - * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. - * 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data - * transfer is 16 bits in length. - */ -#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ - -#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORD_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. - */ -#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) - -#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) -/*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved - * along with received data. The value will reflect the SSEL0 pin for both master and slave - * operation. A zero indicates that a slave select is active. The actual polarity of each slave select - * pin is configured by the related SPOL bit in CFG. - */ -#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) - -#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) -/*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved - * along with received data. The value will reflect the SSEL1 pin for both master and slave - * operation. A zero indicates that a slave select is active. The actual polarity of each slave select - * pin is configured by the related SPOL bit in CFG. - */ -#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) - -#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) -/*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved - * along with received data. The value will reflect the SSEL2 pin for both master and slave - * operation. A zero indicates that a slave select is active. The actual polarity of each slave select - * pin is configured by the related SPOL bit in CFG. - */ -#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) - -#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) -/*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved - * along with received data. The value will reflect the SSEL3 pin for both master and slave - * operation. A zero indicates that a slave select is active. The actual polarity of each slave select - * pin is configured by the related SPOL bit in CFG. - */ -#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) - -#define SPI_FIFORD_SOT_MASK (0x100000U) -#define SPI_FIFORD_SOT_SHIFT (20U) -/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went - * from deasserted to asserted (i.e., any previous transfer has ended). This information can be - * used to identify the first piece of data in cases where the transfer length is greater than 16 - * bits. - */ -#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ - -#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. - */ -#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) -/*! RXSSEL0_N - Slave Select for receive. - */ -#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) -/*! RXSSEL1_N - Slave Select for receive. - */ -#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) -/*! RXSSEL2_N - Slave Select for receive. - */ -#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) -/*! RXSSEL3_N - Slave Select for receive. - */ -#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) - -#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) -#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) -/*! SOT - Start of transfer flag. - */ -#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) -/*! @} */ - -/*! @name FIFOSIZE - FIFO size register */ -/*! @{ */ - -#define SPI_FIFOSIZE_FIFOSIZE_MASK (0x1FU) -#define SPI_FIFOSIZE_FIFOSIZE_SHIFT (0U) -/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - */ -#define SPI_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSIZE_FIFOSIZE_SHIFT)) & SPI_FIFOSIZE_FIFOSIZE_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ - -#define SPI_ID_APERTURE_MASK (0xFFU) -#define SPI_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - */ -#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) - -#define SPI_ID_MINOR_REV_MASK (0xF00U) -#define SPI_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation. - */ -#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) - -#define SPI_ID_MAJOR_REV_MASK (0xF000U) -#define SPI_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation. - */ -#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) - -#define SPI_ID_ID_MASK (0xFFFF0000U) -#define SPI_ID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function. - */ -#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SPI_Register_Masks */ - - -/* SPI - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SPI0 base address */ - #define SPI0_BASE (0x50086000u) - /** Peripheral SPI0 base address */ - #define SPI0_BASE_NS (0x40086000u) - /** Peripheral SPI0 base pointer */ - #define SPI0 ((SPI_Type *)SPI0_BASE) - /** Peripheral SPI0 base pointer */ - #define SPI0_NS ((SPI_Type *)SPI0_BASE_NS) - /** Peripheral SPI1 base address */ - #define SPI1_BASE (0x50087000u) - /** Peripheral SPI1 base address */ - #define SPI1_BASE_NS (0x40087000u) - /** Peripheral SPI1 base pointer */ - #define SPI1 ((SPI_Type *)SPI1_BASE) - /** Peripheral SPI1 base pointer */ - #define SPI1_NS ((SPI_Type *)SPI1_BASE_NS) - /** Peripheral SPI2 base address */ - #define SPI2_BASE (0x50088000u) - /** Peripheral SPI2 base address */ - #define SPI2_BASE_NS (0x40088000u) - /** Peripheral SPI2 base pointer */ - #define SPI2 ((SPI_Type *)SPI2_BASE) - /** Peripheral SPI2 base pointer */ - #define SPI2_NS ((SPI_Type *)SPI2_BASE_NS) - /** Peripheral SPI3 base address */ - #define SPI3_BASE (0x50089000u) - /** Peripheral SPI3 base address */ - #define SPI3_BASE_NS (0x40089000u) - /** Peripheral SPI3 base pointer */ - #define SPI3 ((SPI_Type *)SPI3_BASE) - /** Peripheral SPI3 base pointer */ - #define SPI3_NS ((SPI_Type *)SPI3_BASE_NS) - /** Peripheral SPI4 base address */ - #define SPI4_BASE (0x5008A000u) - /** Peripheral SPI4 base address */ - #define SPI4_BASE_NS (0x4008A000u) - /** Peripheral SPI4 base pointer */ - #define SPI4 ((SPI_Type *)SPI4_BASE) - /** Peripheral SPI4 base pointer */ - #define SPI4_NS ((SPI_Type *)SPI4_BASE_NS) - /** Peripheral SPI5 base address */ - #define SPI5_BASE (0x50096000u) - /** Peripheral SPI5 base address */ - #define SPI5_BASE_NS (0x40096000u) - /** Peripheral SPI5 base pointer */ - #define SPI5 ((SPI_Type *)SPI5_BASE) - /** Peripheral SPI5 base pointer */ - #define SPI5_NS ((SPI_Type *)SPI5_BASE_NS) - /** Peripheral SPI6 base address */ - #define SPI6_BASE (0x50097000u) - /** Peripheral SPI6 base address */ - #define SPI6_BASE_NS (0x40097000u) - /** Peripheral SPI6 base pointer */ - #define SPI6 ((SPI_Type *)SPI6_BASE) - /** Peripheral SPI6 base pointer */ - #define SPI6_NS ((SPI_Type *)SPI6_BASE_NS) - /** Peripheral SPI7 base address */ - #define SPI7_BASE (0x50098000u) - /** Peripheral SPI7 base address */ - #define SPI7_BASE_NS (0x40098000u) - /** Peripheral SPI7 base pointer */ - #define SPI7 ((SPI_Type *)SPI7_BASE) - /** Peripheral SPI7 base pointer */ - #define SPI7_NS ((SPI_Type *)SPI7_BASE_NS) - /** Peripheral SPI8 base address */ - #define SPI8_BASE (0x5009F000u) - /** Peripheral SPI8 base address */ - #define SPI8_BASE_NS (0x4009F000u) - /** Peripheral SPI8 base pointer */ - #define SPI8 ((SPI_Type *)SPI8_BASE) - /** Peripheral SPI8 base pointer */ - #define SPI8_NS ((SPI_Type *)SPI8_BASE_NS) - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS_NS { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS_NS { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS } -#else - /** Peripheral SPI0 base address */ - #define SPI0_BASE (0x40086000u) - /** Peripheral SPI0 base pointer */ - #define SPI0 ((SPI_Type *)SPI0_BASE) - /** Peripheral SPI1 base address */ - #define SPI1_BASE (0x40087000u) - /** Peripheral SPI1 base pointer */ - #define SPI1 ((SPI_Type *)SPI1_BASE) - /** Peripheral SPI2 base address */ - #define SPI2_BASE (0x40088000u) - /** Peripheral SPI2 base pointer */ - #define SPI2 ((SPI_Type *)SPI2_BASE) - /** Peripheral SPI3 base address */ - #define SPI3_BASE (0x40089000u) - /** Peripheral SPI3 base pointer */ - #define SPI3 ((SPI_Type *)SPI3_BASE) - /** Peripheral SPI4 base address */ - #define SPI4_BASE (0x4008A000u) - /** Peripheral SPI4 base pointer */ - #define SPI4 ((SPI_Type *)SPI4_BASE) - /** Peripheral SPI5 base address */ - #define SPI5_BASE (0x40096000u) - /** Peripheral SPI5 base pointer */ - #define SPI5 ((SPI_Type *)SPI5_BASE) - /** Peripheral SPI6 base address */ - #define SPI6_BASE (0x40097000u) - /** Peripheral SPI6 base pointer */ - #define SPI6 ((SPI_Type *)SPI6_BASE) - /** Peripheral SPI7 base address */ - #define SPI7_BASE (0x40098000u) - /** Peripheral SPI7 base pointer */ - #define SPI7 ((SPI_Type *)SPI7_BASE) - /** Peripheral SPI8 base address */ - #define SPI8_BASE (0x4009F000u) - /** Peripheral SPI8 base pointer */ - #define SPI8 ((SPI_Type *)SPI8_BASE) - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } -#endif -/** Interrupt vectors for the SPI peripheral type */ -#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } - -/*! - * @} - */ /* end of group SPI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SYSCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer - * @{ - */ - -/** SYSCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t MEMORYREMAP; /**< Memory Remap control register, offset: 0x0 */ - uint8_t RESERVED_0[12]; - __IO uint32_t AHBMATPRIO; /**< AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest, offset: 0x10 */ - uint8_t RESERVED_1[36]; - __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */ - __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */ - __IO uint32_t CPU1STCKCAL; /**< System tick calibration for CPU1, offset: 0x40 */ - uint8_t RESERVED_2[4]; - __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ - uint8_t RESERVED_3[180]; - union { /* offset: 0x100 */ - struct { /* offset: 0x100 */ - __IO uint32_t PRESETCTRL0; /**< Peripheral reset control 0, offset: 0x100 */ - __IO uint32_t PRESETCTRL1; /**< Peripheral reset control 1, offset: 0x104 */ - __IO uint32_t PRESETCTRL2; /**< Peripheral reset control 2, offset: 0x108 */ - } PRESETCTRL; - __IO uint32_t PRESETCTRLX[3]; /**< Peripheral reset control register, array offset: 0x100, array step: 0x4 */ - }; - uint8_t RESERVED_4[20]; - __IO uint32_t PRESETCTRLSET[3]; /**< Peripheral reset control set register, array offset: 0x120, array step: 0x4 */ - uint8_t RESERVED_5[20]; - __IO uint32_t PRESETCTRLCLR[3]; /**< Peripheral reset control clear register, array offset: 0x140, array step: 0x4 */ - uint8_t RESERVED_6[20]; - __O uint32_t SWR_RESET; /**< generate a software_reset, offset: 0x160 */ - uint8_t RESERVED_7[156]; - union { /* offset: 0x200 */ - struct { /* offset: 0x200 */ - __IO uint32_t AHBCLKCTRL0; /**< AHB Clock control 0, offset: 0x200 */ - __IO uint32_t AHBCLKCTRL1; /**< AHB Clock control 1, offset: 0x204 */ - __IO uint32_t AHBCLKCTRL2; /**< AHB Clock control 2, offset: 0x208 */ - } AHBCLKCTRL; - __IO uint32_t AHBCLKCTRLX[3]; /**< Peripheral reset control register, array offset: 0x200, array step: 0x4 */ - }; - uint8_t RESERVED_8[20]; - __IO uint32_t AHBCLKCTRLSET[3]; /**< Peripheral reset control register, array offset: 0x220, array step: 0x4 */ - uint8_t RESERVED_9[20]; - __IO uint32_t AHBCLKCTRLCLR[3]; /**< Peripheral reset control register, array offset: 0x240, array step: 0x4 */ - uint8_t RESERVED_10[20]; - union { /* offset: 0x260 */ - struct { /* offset: 0x260 */ - __IO uint32_t SYSTICKCLKSEL0; /**< System Tick Timer for CPU0 source select, offset: 0x260 */ - __IO uint32_t SYSTICKCLKSEL1; /**< System Tick Timer for CPU1 source select, offset: 0x264 */ - } SYSTICKCLKSEL; - __IO uint32_t SYSTICKCLKSELX[2]; /**< Peripheral reset control register, array offset: 0x260, array step: 0x4 */ - }; - __IO uint32_t TRACECLKSEL; /**< Trace clock source select, offset: 0x268 */ - union { /* offset: 0x26C */ - struct { /* offset: 0x26C */ - __IO uint32_t CTIMERCLKSEL0; /**< CTimer 0 clock source select, offset: 0x26C */ - __IO uint32_t CTIMERCLKSEL1; /**< CTimer 1 clock source select, offset: 0x270 */ - __IO uint32_t CTIMERCLKSEL2; /**< CTimer 2 clock source select, offset: 0x274 */ - __IO uint32_t CTIMERCLKSEL3; /**< CTimer 3 clock source select, offset: 0x278 */ - __IO uint32_t CTIMERCLKSEL4; /**< CTimer 4 clock source select, offset: 0x27C */ - } CTIMERCLKSEL; - __IO uint32_t CTIMERCLKSELX[5]; /**< Peripheral reset control register, array offset: 0x26C, array step: 0x4 */ - }; - __IO uint32_t MAINCLKSELA; /**< Main clock A source select, offset: 0x280 */ - __IO uint32_t MAINCLKSELB; /**< Main clock source select, offset: 0x284 */ - __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0x288 */ - uint8_t RESERVED_11[4]; - __IO uint32_t PLL0CLKSEL; /**< PLL0 clock source select, offset: 0x290 */ - __IO uint32_t PLL1CLKSEL; /**< PLL1 clock source select, offset: 0x294 */ - uint8_t RESERVED_12[12]; - __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ - __IO uint32_t USB0CLKSEL; /**< FS USB clock source select, offset: 0x2A8 */ - uint8_t RESERVED_13[4]; - union { /* offset: 0x2B0 */ - struct { /* offset: 0x2B0 */ - __IO uint32_t FCCLKSEL0; /**< Flexcomm Interface 0 clock source select for Fractional Rate Divider, offset: 0x2B0 */ - __IO uint32_t FCCLKSEL1; /**< Flexcomm Interface 1 clock source select for Fractional Rate Divider, offset: 0x2B4 */ - __IO uint32_t FCCLKSEL2; /**< Flexcomm Interface 2 clock source select for Fractional Rate Divider, offset: 0x2B8 */ - __IO uint32_t FCCLKSEL3; /**< Flexcomm Interface 3 clock source select for Fractional Rate Divider, offset: 0x2BC */ - __IO uint32_t FCCLKSEL4; /**< Flexcomm Interface 4 clock source select for Fractional Rate Divider, offset: 0x2C0 */ - __IO uint32_t FCCLKSEL5; /**< Flexcomm Interface 5 clock source select for Fractional Rate Divider, offset: 0x2C4 */ - __IO uint32_t FCCLKSEL6; /**< Flexcomm Interface 6 clock source select for Fractional Rate Divider, offset: 0x2C8 */ - __IO uint32_t FCCLKSEL7; /**< Flexcomm Interface 7 clock source select for Fractional Rate Divider, offset: 0x2CC */ - } FCCLKSEL; - __IO uint32_t FCCLKSELX[8]; /**< Peripheral reset control register, array offset: 0x2B0, array step: 0x4 */ - }; - __IO uint32_t HSLSPICLKSEL; /**< HS LSPI clock source select, offset: 0x2D0 */ - uint8_t RESERVED_14[12]; - __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ - uint8_t RESERVED_15[12]; - __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ - uint8_t RESERVED_16[4]; - __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */ - uint8_t RESERVED_17[4]; - __IO uint32_t SYSTICKCLKDIV0; /**< System Tick Timer divider for CPU0, offset: 0x300 */ - __IO uint32_t SYSTICKCLKDIV1; /**< System Tick Timer divider for CPU1, offset: 0x304 */ - __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */ - uint8_t RESERVED_18[20]; - union { /* offset: 0x320 */ - struct { /* offset: 0x320 */ - __IO uint32_t FLEXFRG0CTRL; /**< Fractional rate divider for flexcomm 0, offset: 0x320 */ - __IO uint32_t FLEXFRG1CTRL; /**< Fractional rate divider for flexcomm 1, offset: 0x324 */ - __IO uint32_t FLEXFRG2CTRL; /**< Fractional rate divider for flexcomm 2, offset: 0x328 */ - __IO uint32_t FLEXFRG3CTRL; /**< Fractional rate divider for flexcomm 3, offset: 0x32C */ - __IO uint32_t FLEXFRG4CTRL; /**< Fractional rate divider for flexcomm 4, offset: 0x330 */ - __IO uint32_t FLEXFRG5CTRL; /**< Fractional rate divider for flexcomm 5, offset: 0x334 */ - __IO uint32_t FLEXFRG6CTRL; /**< Fractional rate divider for flexcomm 6, offset: 0x338 */ - __IO uint32_t FLEXFRG7CTRL; /**< Fractional rate divider for flexcomm 7, offset: 0x33C */ - } FLEXFRGCTRL; - __IO uint32_t FLEXFRGXCTRL[8]; /**< Peripheral reset control register, array offset: 0x320, array step: 0x4 */ - }; - uint8_t RESERVED_19[64]; - __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */ - __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ - __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */ - __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */ - uint8_t RESERVED_20[4]; - __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ - __IO uint32_t USB0CLKDIV; /**< USB0 Clock divider, offset: 0x398 */ - uint8_t RESERVED_21[16]; - __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ - uint8_t RESERVED_22[4]; - __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ - uint8_t RESERVED_23[4]; - __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */ - uint8_t RESERVED_24[4]; - __IO uint32_t PLL0CLKDIV; /**< PLL0 clock divider, offset: 0x3C4 */ - uint8_t RESERVED_25[52]; - __IO uint32_t CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */ - __IO uint32_t FMCCR; /**< FMC configuration register, offset: 0x400 */ - uint8_t RESERVED_26[8]; - __IO uint32_t USB0NEEDCLKCTRL; /**< USB0 need clock control, offset: 0x40C */ - __I uint32_t USB0NEEDCLKSTAT; /**< USB0 need clock status, offset: 0x410 */ - uint8_t RESERVED_27[8]; - __O uint32_t FMCFLUSH; /**< FMCflush control, offset: 0x41C */ - __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */ - __IO uint32_t USB1NEEDCLKCTRL; /**< USB1 need clock control, offset: 0x424 */ - __I uint32_t USB1NEEDCLKSTAT; /**< USB1 need clock status, offset: 0x428 */ - uint8_t RESERVED_28[52]; - __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */ - uint8_t RESERVED_29[252]; - __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */ - __I uint32_t PLL1STAT; /**< PLL1 550m status, offset: 0x564 */ - __IO uint32_t PLL1NDEC; /**< PLL1 550m N divider, offset: 0x568 */ - __IO uint32_t PLL1MDEC; /**< PLL1 550m M divider, offset: 0x56C */ - __IO uint32_t PLL1PDEC; /**< PLL1 550m P divider, offset: 0x570 */ - uint8_t RESERVED_30[12]; - __IO uint32_t PLL0CTRL; /**< PLL0 550m control, offset: 0x580 */ - __I uint32_t PLL0STAT; /**< PLL0 550m status, offset: 0x584 */ - __IO uint32_t PLL0NDEC; /**< PLL0 550m N divider, offset: 0x588 */ - __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */ - __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */ - __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */ - uint8_t RESERVED_31[364]; - __IO uint32_t FUNCRETENTIONCTRL; /**< Functional retention control register, offset: 0x704 */ - uint8_t RESERVED_32[248]; - __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ - __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ - uint8_t RESERVED_33[4]; - __I uint32_t CPSTAT; /**< CPU Status, offset: 0x80C */ - uint8_t RESERVED_34[520]; - __IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures, offset: 0xA18 */ - uint8_t RESERVED_35[244]; - __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */ - __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */ - uint8_t RESERVED_36[748]; - __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */ - __IO uint32_t GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */ - uint8_t RESERVED_37[404]; - __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers., offset: 0xFA0 */ - __IO uint32_t DEBUG_FEATURES; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control., offset: 0xFA4 */ - __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register., offset: 0xFA8 */ - uint8_t RESERVED_38[16]; - __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index., offset: 0xFBC */ - __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug authentication BEACON register, offset: 0xFC0 */ - uint8_t RESERVED_39[16]; - __IO uint32_t CPUCFG; /**< CPUs configuration register, offset: 0xFD4 */ - uint8_t RESERVED_40[32]; - __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ - __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */ -} SYSCON_Type; - -/* ---------------------------------------------------------------------------- - -- SYSCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Register_Masks SYSCON Register Masks - * @{ - */ - -/*! @name MEMORYREMAP - Memory Remap control register */ -/*! @{ */ - -#define SYSCON_MEMORYREMAP_MAP_MASK (0x3U) -#define SYSCON_MEMORYREMAP_MAP_SHIFT (0U) -/*! MAP - Select the location of the vector table :. - * 0b00..Vector Table in ROM. - * 0b01..Vector Table in RAM. - * 0b10..Vector Table in Flash. - * 0b11..Vector Table in Flash. - */ -#define SYSCON_MEMORYREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK) -/*! @} */ - -/*! @name AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest */ -/*! @{ */ - -#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK (0x3U) -#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT (0U) -/*! PRI_CPU0_CBUS - CPU0 C-AHB bus. - */ -#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK (0xCU) -#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT (2U) -/*! PRI_CPU0_SBUS - CPU0 S-AHB bus. - */ -#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK (0x30U) -#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT (4U) -/*! PRI_CPU1_CBUS - CPU1 C-AHB bus. - */ -#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK (0xC0U) -#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT (6U) -/*! PRI_CPU1_SBUS - CPU1 S-AHB bus. - */ -#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_USB_FS_MASK (0x300U) -#define SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT (8U) -/*! PRI_USB_FS - USB-FS.(USB0) - */ -#define SYSCON_AHBMATPRIO_PRI_USB_FS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0xC00U) -#define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (10U) -/*! PRI_SDMA0 - DMA0 controller priority. - */ -#define SYSCON_AHBMATPRIO_PRI_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK) - -#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0x30000U) -#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (16U) -/*! PRI_SDIO - SDIO. - */ -#define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK) - -#define SYSCON_AHBMATPRIO_PRI_PQ_MASK (0xC0000U) -#define SYSCON_AHBMATPRIO_PRI_PQ_SHIFT (18U) -/*! PRI_PQ - PQ (HW Accelerator). - */ -#define SYSCON_AHBMATPRIO_PRI_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PQ_MASK) - -#define SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK (0x300000U) -#define SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT (20U) -/*! PRI_HASH_AES - HASH_AES. - */ -#define SYSCON_AHBMATPRIO_PRI_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT)) & SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK) - -#define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK (0xC00000U) -#define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT (22U) -/*! PRI_USB_HS - USB-HS.(USB1) - */ -#define SYSCON_AHBMATPRIO_PRI_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0x3000000U) -#define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (24U) -/*! PRI_SDMA1 - DMA1 controller priority. - */ -#define SYSCON_AHBMATPRIO_PRI_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK) -/*! @} */ - -/*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */ -/*! @{ */ - -#define SYSCON_CPU0STCKCAL_TENMS_MASK (0xFFFFFFU) -#define SYSCON_CPU0STCKCAL_TENMS_SHIFT (0U) -/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value - * reads as zero, the calibration value is not known. - */ -#define SYSCON_CPU0STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK) - -#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) -/*! SKEW - Initial value for the Systick timer. - */ -#define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) - -#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) -/*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference - * clock provided; 1 = no reference clock provided. - */ -#define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */ -/*! @{ */ - -#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) -#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) -/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the - * value reads as zero, the calibration value is not known. - */ -#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) - -#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) -/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. - */ -#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) - -#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) -/*! NOREF - Initial value for the Systick timer. - */ -#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name CPU1STCKCAL - System tick calibration for CPU1 */ -/*! @{ */ - -#define SYSCON_CPU1STCKCAL_TENMS_MASK (0xFFFFFFU) -#define SYSCON_CPU1STCKCAL_TENMS_SHIFT (0U) -/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value - * reads as zero, the calibration value is not known. - */ -#define SYSCON_CPU1STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_TENMS_SHIFT)) & SYSCON_CPU1STCKCAL_TENMS_MASK) - -#define SYSCON_CPU1STCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU1STCKCAL_SKEW_SHIFT (24U) -/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. - */ -#define SYSCON_CPU1STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_SKEW_SHIFT)) & SYSCON_CPU1STCKCAL_SKEW_MASK) - -#define SYSCON_CPU1STCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU1STCKCAL_NOREF_SHIFT (25U) -/*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference - * clock provided; 1 = no reference clock provided. - */ -#define SYSCON_CPU1STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_NOREF_SHIFT)) & SYSCON_CPU1STCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name NMISRC - NMI Source Select */ -/*! @{ */ - -#define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU) -#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) -/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0. - */ -#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) - -#define SYSCON_NMISRC_IRQCPU1_MASK (0x3F00U) -#define SYSCON_NMISRC_IRQCPU1_SHIFT (8U) -/*! IRQCPU1 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1, if enabled by NMIENCPU1. - */ -#define SYSCON_NMISRC_IRQCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU1_SHIFT)) & SYSCON_NMISRC_IRQCPU1_MASK) - -#define SYSCON_NMISRC_NMIENCPU1_MASK (0x40000000U) -#define SYSCON_NMISRC_NMIENCPU1_SHIFT (30U) -/*! NMIENCPU1 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU1. - */ -#define SYSCON_NMISRC_NMIENCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU1_SHIFT)) & SYSCON_NMISRC_NMIENCPU1_MASK) - -#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) -#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) -/*! NMIENCPU0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. - */ -#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) -/*! @} */ - -/*! @name PRESETCTRL0 - Peripheral reset control 0 */ -/*! @{ */ - -#define SYSCON_PRESETCTRL0_ROM_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL0_ROM_RST_SHIFT (1U) -/*! ROM_RST - ROM reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_ROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ROM_RST_SHIFT)) & SYSCON_PRESETCTRL0_ROM_RST_MASK) - -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U) -/*! SRAM_CTRL1_RST - SRAM Controller 1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK) - -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U) -/*! SRAM_CTRL2_RST - SRAM Controller 2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK) - -#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK (0x20U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT (5U) -/*! SRAM_CTRL3_RST - SRAM Controller 3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK) - -#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK (0x40U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT (6U) -/*! SRAM_CTRL4_RST - SRAM Controller 4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK) - -#define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U) -/*! FLASH_RST - Flash controller reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK) - -#define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U) -/*! FMC_RST - FMC controller reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK) - -#define SYSCON_PRESETCTRL0_MUX_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL0_MUX_RST_SHIFT (11U) -/*! MUX_RST - Input Mux reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK) - -#define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U) -/*! IOCON_RST - I/O controller reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK) - -#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U) -/*! GPIO0_RST - GPIO0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) - -#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U) -/*! GPIO1_RST - GPIO1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) - -#define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (16U) -/*! GPIO2_RST - GPIO2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK) - -#define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (17U) -/*! GPIO3_RST - GPIO3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK) - -#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U) -/*! PINT_RST - Pin interrupt (PINT) reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) - -#define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U) -/*! GINT_RST - Group interrupt (GINT) reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK) - -#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U) -#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U) -/*! DMA0_RST - DMA0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) - -#define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U) -#define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U) -/*! CRCGEN_RST - CRCGEN reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_CRCGEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK) - -#define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U) -/*! WWDT_RST - Watchdog Timer reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK) - -#define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U) -#define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U) -/*! RTC_RST - Real Time Clock (RTC) reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK) - -#define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U) -#define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U) -/*! MAILBOX_RST - Inter CPU communication Mailbox reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK) - -#define SYSCON_PRESETCTRL0_ADC_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL0_ADC_RST_SHIFT (27U) -/*! ADC_RST - ADC reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_ADC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRL1 - Peripheral reset control 1 */ -/*! @{ */ - -#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) -#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) -/*! MRT_RST - MRT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) - -#define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT (1U) -/*! OSTIMER_RST - OS Event Timer reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_OSTIMER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK) - -#define SYSCON_PRESETCTRL1_SCT_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL1_SCT_RST_SHIFT (2U) -/*! SCT_RST - SCT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_SCT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT_RST_MASK) - -#define SYSCON_PRESETCTRL1_SCTIPU_RST_MASK (0x40U) -#define SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT (6U) -/*! SCTIPU_RST - SCTIPU reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_SCTIPU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCTIPU_RST_MASK) - -#define SYSCON_PRESETCTRL1_UTICK_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT (10U) -/*! UTICK_RST - UTICK reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) -/*! FC0_RST - FC0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) -#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) -/*! FC1_RST - FC1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) -/*! FC2_RST - FC2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) -/*! FC3_RST - FC3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) -/*! FC4_RST - FC4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) -/*! FC5_RST - FC5 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) -/*! FC6_RST - FC6 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) -/*! FC7_RST - FC7 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) - -#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) -/*! TIMER2_RST - Timer 2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) - -#define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK (0x2000000U) -#define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT (25U) -/*! USB0_DEV_RST - USB0 DEV reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_USB0_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK) - -#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) -#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) -/*! TIMER0_RST - Timer 0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) - -#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) -/*! TIMER1_RST - Timer 1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRL2 - Peripheral reset control 2 */ -/*! @{ */ - -#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) -/*! DMA1_RST - DMA1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) - -#define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U) -/*! COMP_RST - Comparator reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_COMP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK) - -#define SYSCON_PRESETCTRL2_SDIO_RST_MASK (0x8U) -#define SYSCON_PRESETCTRL2_SDIO_RST_SHIFT (3U) -/*! SDIO_RST - SDIO reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_SDIO_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK (0x10U) -#define SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT (4U) -/*! USB1_HOST_RST - USB1 Host reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_HOST_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK (0x20U) -#define SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT (5U) -/*! USB1_DEV_RST - USB1 dev reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK (0x40U) -#define SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT (6U) -/*! USB1_RAM_RST - USB1 RAM reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT (7U) -/*! USB1_PHY_RST - USB1 PHY reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK) - -#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) -/*! FREQME_RST - Frequency meter reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) - -#define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U) -/*! RNG_RST - RNG reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK) - -#define SYSCON_PRESETCTRL2_SYSCTL_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT (15U) -/*! SYSCTL_RST - SYSCTL Block reset. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_SYSCTL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT)) & SYSCON_PRESETCTRL2_SYSCTL_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT (16U) -/*! USB0_HOSTM_RST - USB0 Host Master reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT (17U) -/*! USB0_HOSTS_RST - USB0 Host Slave reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK) - -#define SYSCON_PRESETCTRL2_HASH_AES_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT (18U) -/*! HASH_AES_RST - HASH_AES reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_HASH_AES_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH_AES_RST_MASK) - -#define SYSCON_PRESETCTRL2_PQ_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL2_PQ_RST_SHIFT (19U) -/*! PQ_RST - Power Quad reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_PQ_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK) - -#define SYSCON_PRESETCTRL2_PLULUT_RST_MASK (0x100000U) -#define SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT (20U) -/*! PLULUT_RST - PLU LUT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_PLULUT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLULUT_RST_MASK) - -#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) -#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) -/*! TIMER3_RST - Timer 3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) - -#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) -/*! TIMER4_RST - Timer 4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) - -#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) -#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) -/*! PUF_RST - PUF reset control reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) - -#define SYSCON_PRESETCTRL2_CASPER_RST_MASK (0x1000000U) -#define SYSCON_PRESETCTRL2_CASPER_RST_SHIFT (24U) -/*! CASPER_RST - Casper reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_CASPER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CASPER_RST_SHIFT)) & SYSCON_PRESETCTRL2_CASPER_RST_MASK) - -#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT (27U) -/*! ANALOG_CTRL_RST - analog control reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK) - -#define SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK (0x10000000U) -#define SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT (28U) -/*! HS_LSPI_RST - HS LSPI reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_HS_LSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK) - -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U) -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U) -/*! GPIO_SEC_RST - GPIO secure reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK) - -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U) -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U) -/*! GPIO_SEC_INT_RST - GPIO secure int reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRLX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_PRESETCTRLX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_PRESETCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLX_DATA_SHIFT)) & SYSCON_PRESETCTRLX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLX */ -#define SYSCON_PRESETCTRLX_COUNT (3U) - -/*! @name PRESETCTRLSET - Peripheral reset control set register */ -/*! @{ */ - -#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLSET */ -#define SYSCON_PRESETCTRLSET_COUNT (3U) - -/*! @name PRESETCTRLCLR - Peripheral reset control clear register */ -/*! @{ */ - -#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLCLR */ -#define SYSCON_PRESETCTRLCLR_COUNT (3U) - -/*! @name SWR_RESET - generate a software_reset */ -/*! @{ */ - -#define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU) -#define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U) -/*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset. - * 0b01011010000000000000000000000001..Generate a software reset. - * 0b00000000000000000000000000000000..Bloc is not reset. - */ -#define SYSCON_SWR_RESET_SWR_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL0 - AHB Clock control 0 */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) -#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) -/*! ROM - Enables the clock for the ROM. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) - -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U) -/*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK) - -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U) -/*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK) - -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK (0x20U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT (5U) -/*! SRAM_CTRL3 - Enables the clock for the SRAM Controller 3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK) - -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK (0x40U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT (6U) -/*! SRAM_CTRL4 - Enables the clock for the SRAM Controller 4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK) - -#define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U) -#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U) -/*! FLASH - Enables the clock for the Flash controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK) - -#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U) -#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U) -/*! FMC - Enables the clock for the FMC controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) - -#define SYSCON_AHBCLKCTRL0_MUX_MASK (0x800U) -#define SYSCON_AHBCLKCTRL0_MUX_SHIFT (11U) -/*! MUX - Enables the clock for the Input Mux. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_MUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK) - -#define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U) -/*! IOCON - Enables the clock for the I/O controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK) - -#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U) -/*! GPIO0 - Enables the clock for the GPIO0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) - -#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U) -/*! GPIO1 - Enables the clock for the GPIO1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) - -#define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (16U) -/*! GPIO2 - Enables the clock for the GPIO2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK) - -#define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (17U) -/*! GPIO3 - Enables the clock for the GPIO3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK) - -#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U) -/*! PINT - Enables the clock for the Pin interrupt (PINT). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) - -#define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U) -/*! GINT - Enables the clock for the Group interrupt (GINT). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK) - -#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U) -#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U) -/*! DMA0 - Enables the clock for the DMA0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) - -#define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U) -#define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U) -/*! CRCGEN - Enables the clock for the CRCGEN. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK) - -#define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U) -/*! WWDT - Enables the clock for the Watchdog Timer. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK) - -#define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U) -#define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U) -/*! RTC - Enables the clock for the Real Time Clock (RTC). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK) - -#define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U) -/*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK) - -#define SYSCON_AHBCLKCTRL0_ADC_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL0_ADC_SHIFT (27U) -/*! ADC - Enables the clock for the ADC. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL1 - AHB Clock control 1 */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) -#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) -/*! MRT - Enables the clock for the MRT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) - -#define SYSCON_AHBCLKCTRL1_OSTIMER_MASK (0x2U) -#define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT (1U) -/*! OSTIMER - Enables the clock for the OS Event Timer. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK) - -#define SYSCON_AHBCLKCTRL1_SCT_MASK (0x4U) -#define SYSCON_AHBCLKCTRL1_SCT_SHIFT (2U) -/*! SCT - Enables the clock for the SCT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_SCT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT_MASK) - -#define SYSCON_AHBCLKCTRL1_UTICK_MASK (0x400U) -#define SYSCON_AHBCLKCTRL1_UTICK_SHIFT (10U) -/*! UTICK - Enables the clock for the UTICK. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK) - -#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) -#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) -/*! FC0 - Enables the clock for the FC0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) - -#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) -#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) -/*! FC1 - Enables the clock for the FC1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) - -#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) -/*! FC2 - Enables the clock for the FC2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) - -#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) -/*! FC3 - Enables the clock for the FC3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) - -#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) -/*! FC4 - Enables the clock for the FC4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) - -#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) -/*! FC5 - Enables the clock for the FC5. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) - -#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) -/*! FC6 - Enables the clock for the FC6. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) - -#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) -/*! FC7 - Enables the clock for the FC7. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) - -#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) -/*! TIMER2 - Enables the clock for the Timer 2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) - -#define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK (0x2000000U) -#define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT (25U) -/*! USB0_DEV - Enables the clock for the USB0 DEV. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_USB0_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK) - -#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) -/*! TIMER0 - Enables the clock for the Timer 0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) - -#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) -/*! TIMER1 - Enables the clock for the Timer 1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL2 - AHB Clock control 2 */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) -#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) -/*! DMA1 - Enables the clock for the DMA1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) - -#define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U) -#define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U) -/*! COMP - Enables the clock for the Comparator. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK) - -#define SYSCON_AHBCLKCTRL2_SDIO_MASK (0x8U) -#define SYSCON_AHBCLKCTRL2_SDIO_SHIFT (3U) -/*! SDIO - Enables the clock for the SDIO. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL2_SDIO_MASK) - -#define SYSCON_AHBCLKCTRL2_USB1_HOST_MASK (0x10U) -#define SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT (4U) -/*! USB1_HOST - Enables the clock for the USB1 Host. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_HOST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_HOST_MASK) - -#define SYSCON_AHBCLKCTRL2_USB1_DEV_MASK (0x20U) -#define SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT (5U) -/*! USB1_DEV - Enables the clock for the USB1 dev. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_DEV_MASK) - -#define SYSCON_AHBCLKCTRL2_USB1_RAM_MASK (0x40U) -#define SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT (6U) -/*! USB1_RAM - Enables the clock for the USB1 RAM. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_RAM_MASK) - -#define SYSCON_AHBCLKCTRL2_USB1_PHY_MASK (0x80U) -#define SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT (7U) -/*! USB1_PHY - Enables the clock for the USB1 PHY. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_PHY_MASK) - -#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) -#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) -/*! FREQME - Enables the clock for the Frequency meter. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) - -#define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U) -/*! RNG - Enables the clock for the RNG. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK) - -#define SYSCON_AHBCLKCTRL2_SYSCTL_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT (15U) -/*! SYSCTL - SYSCTL block clock. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_SYSCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT)) & SYSCON_AHBCLKCTRL2_SYSCTL_MASK) - -#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT (16U) -/*! USB0_HOSTM - Enables the clock for the USB0 Host Master. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK) - -#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT (17U) -/*! USB0_HOSTS - Enables the clock for the USB0 Host Slave. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK) - -#define SYSCON_AHBCLKCTRL2_HASH_AES_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT (18U) -/*! HASH_AES - Enables the clock for the HASH_AES. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH_AES_MASK) - -#define SYSCON_AHBCLKCTRL2_PQ_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL2_PQ_SHIFT (19U) -/*! PQ - Enables the clock for the Power Quad. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK) - -#define SYSCON_AHBCLKCTRL2_PLULUT_MASK (0x100000U) -#define SYSCON_AHBCLKCTRL2_PLULUT_SHIFT (20U) -/*! PLULUT - Enables the clock for the PLU LUT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PLULUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLULUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLULUT_MASK) - -#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) -#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) -/*! TIMER3 - Enables the clock for the Timer 3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) - -#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) -/*! TIMER4 - Enables the clock for the Timer 4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) - -#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) -#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) -/*! PUF - Enables the clock for the PUF reset control. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) - -#define SYSCON_AHBCLKCTRL2_CASPER_MASK (0x1000000U) -#define SYSCON_AHBCLKCTRL2_CASPER_SHIFT (24U) -/*! CASPER - Enables the clock for the Casper. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CASPER_SHIFT)) & SYSCON_AHBCLKCTRL2_CASPER_MASK) - -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U) -/*! ANALOG_CTRL - Enables the clock for the analog control. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK) - -#define SYSCON_AHBCLKCTRL2_HS_LSPI_MASK (0x10000000U) -#define SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT (28U) -/*! HS_LSPI - Enables the clock for the HS LSPI. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_LSPI_MASK) - -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U) -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U) -/*! GPIO_SEC - Enables the clock for the GPIO secure. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK) - -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U) -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U) -/*! GPIO_SEC_INT - Enables the clock for the GPIO secure int. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK) -/*! @} */ - -/*! @name AHBCLKCTRLX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRLX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_AHBCLKCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLX_DATA_SHIFT)) & SYSCON_AHBCLKCTRLX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLX */ -#define SYSCON_AHBCLKCTRLX_COUNT (3U) - -/*! @name AHBCLKCTRLSET - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLSET */ -#define SYSCON_AHBCLKCTRLSET_COUNT (3U) - -/*! @name AHBCLKCTRLCLR - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLCLR */ -#define SYSCON_AHBCLKCTRLCLR_COUNT (3U) - -/*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) -/*! SEL - System Tick Timer for CPU0 source select. - * 0b000..System Tick 0 divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKSEL1 - System Tick Timer for CPU1 source select */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKSEL1_SEL_MASK (0x7U) -#define SYSCON_SYSTICKCLKSEL1_SEL_SHIFT (0U) -/*! SEL - System Tick Timer for CPU1 source select. - * 0b000..System Tick 1 divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SYSTICKCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL1_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL1_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKSELX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKSELX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_SYSTICKCLKSELX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_SYSTICKCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSELX_DATA_SHIFT)) & SYSCON_SYSTICKCLKSELX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_SYSTICKCLKSELX */ -#define SYSCON_SYSTICKCLKSELX_COUNT (2U) - -/*! @name TRACECLKSEL - Trace clock source select */ -/*! @{ */ - -#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) -#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) -/*! SEL - Trace clock source select. - * 0b000..Trace divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL0 - CTimer 0 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL0_SEL_SHIFT (0U) -/*! SEL - CTimer 0 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL0_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL1 - CTimer 1 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL1_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL1_SEL_SHIFT (0U) -/*! SEL - CTimer 1 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL1_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL1_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL2 - CTimer 2 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL2_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL2_SEL_SHIFT (0U) -/*! SEL - CTimer 2 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL2_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL2_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL3 - CTimer 3 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL3_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL3_SEL_SHIFT (0U) -/*! SEL - CTimer 3 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL3_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL3_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL4 - CTimer 4 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL4_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL4_SEL_SHIFT (0U) -/*! SEL - CTimer 4 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL4_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL4_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSELX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSELX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_CTIMERCLKSELX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_CTIMERCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSELX_DATA_SHIFT)) & SYSCON_CTIMERCLKSELX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_CTIMERCLKSELX */ -#define SYSCON_CTIMERCLKSELX_COUNT (5U) - -/*! @name MAINCLKSELA - Main clock A source select */ -/*! @{ */ - -#define SYSCON_MAINCLKSELA_SEL_MASK (0x7U) -#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) -/*! SEL - Main clock A source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..Reserved. - * 0b101..Reserved. - * 0b110..Reserved. - * 0b111..Reserved. - */ -#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) -/*! @} */ - -/*! @name MAINCLKSELB - Main clock source select */ -/*! @{ */ - -#define SYSCON_MAINCLKSELB_SEL_MASK (0x7U) -#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) -/*! SEL - Main clock source select. - * 0b000..Main Clock A. - * 0b001..PLL0 clock. - * 0b010..PLL1 clock. - * 0b011..Oscillator 32 kHz clock. - * 0b100..Reserved. - * 0b101..Reserved. - * 0b110..Reserved. - * 0b111..Reserved. - */ -#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) -/*! @} */ - -/*! @name CLKOUTSEL - CLKOUT clock source select */ -/*! @{ */ - -#define SYSCON_CLKOUTSEL_SEL_MASK (0x7U) -#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) -/*! SEL - CLKOUT clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..CLKIN clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..PLL1 clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) -/*! @} */ - -/*! @name PLL0CLKSEL - PLL0 clock source select */ -/*! @{ */ - -#define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U) -#define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U) -/*! SEL - PLL0 clock source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..Oscillator 32kHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_PLL0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name PLL1CLKSEL - PLL1 clock source select */ -/*! @{ */ - -#define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U) -#define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U) -/*! SEL - PLL1 clock source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..Oscillator 32kHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_PLL1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name ADCCLKSEL - ADC clock source select */ -/*! @{ */ - -#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) -#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) -/*! SEL - ADC clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..FRO 96 MHz clock. - * 0b011..Reserved. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name USB0CLKSEL - FS USB clock source select */ -/*! @{ */ - -#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) -#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) -/*! SEL - FS USB clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..PLL1 clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL0_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL0_SEL_SHIFT)) & SYSCON_FCCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL1_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL1_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL1_SEL_SHIFT)) & SYSCON_FCCLKSEL1_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL2_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL2_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL2_SEL_SHIFT)) & SYSCON_FCCLKSEL2_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL3_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL3_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL3_SEL_SHIFT)) & SYSCON_FCCLKSEL3_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL4_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL4_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL4_SEL_SHIFT)) & SYSCON_FCCLKSEL4_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL5_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL5_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL5_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL5_SEL_SHIFT)) & SYSCON_FCCLKSEL5_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL6_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL6_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL6_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL6_SEL_SHIFT)) & SYSCON_FCCLKSEL6_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL7_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL7_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL7_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL7_SEL_SHIFT)) & SYSCON_FCCLKSEL7_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSELX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_FCCLKSELX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_FCCLKSELX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_FCCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSELX_DATA_SHIFT)) & SYSCON_FCCLKSELX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_FCCLKSELX */ -#define SYSCON_FCCLKSELX_COUNT (8U) - -/*! @name HSLSPICLKSEL - HS LSPI clock source select */ -/*! @{ */ - -#define SYSCON_HSLSPICLKSEL_SEL_MASK (0x7U) -#define SYSCON_HSLSPICLKSEL_SEL_SHIFT (0U) -/*! SEL - HS LSPI clock source select. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..No clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_HSLSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HSLSPICLKSEL_SEL_SHIFT)) & SYSCON_HSLSPICLKSEL_SEL_MASK) -/*! @} */ - -/*! @name MCLKCLKSEL - MCLK clock source select */ -/*! @{ */ - -#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) -#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) -/*! SEL - MCLK clock source select. - * 0b000..FRO 96 MHz clock. - * 0b001..PLL0 clock. - * 0b010..Reserved. - * 0b011..Reserved. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SCTCLKSEL - SCTimer/PWM clock source select */ -/*! @{ */ - -#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) -#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) -/*! SEL - SCTimer/PWM clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..CLKIN clock. - * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..MCLK clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SDIOCLKSEL - SDIO clock source select */ -/*! @{ */ - -#define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U) -#define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U) -/*! SEL - SDIO clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..PLL1 clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKDIV0_DIV_MASK (0xFFU) -#define SYSCON_SYSTICKCLKDIV0_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_SYSTICKCLKDIV0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV0_DIV_MASK) - -#define SYSCON_SYSTICKCLKDIV0_RESET_MASK (0x20000000U) -#define SYSCON_SYSTICKCLKDIV0_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SYSTICKCLKDIV0_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV0_RESET_MASK) - -#define SYSCON_SYSTICKCLKDIV0_HALT_MASK (0x40000000U) -#define SYSCON_SYSTICKCLKDIV0_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SYSTICKCLKDIV0_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV0_HALT_MASK) - -#define SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK (0x80000000U) -#define SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SYSTICKCLKDIV0_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK) -/*! @} */ - -/*! @name SYSTICKCLKDIV1 - System Tick Timer divider for CPU1 */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKDIV1_DIV_MASK (0xFFU) -#define SYSCON_SYSTICKCLKDIV1_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_SYSTICKCLKDIV1_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV1_DIV_MASK) - -#define SYSCON_SYSTICKCLKDIV1_RESET_MASK (0x20000000U) -#define SYSCON_SYSTICKCLKDIV1_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SYSTICKCLKDIV1_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV1_RESET_MASK) - -#define SYSCON_SYSTICKCLKDIV1_HALT_MASK (0x40000000U) -#define SYSCON_SYSTICKCLKDIV1_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SYSTICKCLKDIV1_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV1_HALT_MASK) - -#define SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK (0x80000000U) -#define SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SYSTICKCLKDIV1_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK) -/*! @} */ - -/*! @name TRACECLKDIV - TRACE clock divider */ -/*! @{ */ - -#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) -#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) - -#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) - -#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) - -#define SYSCON_TRACECLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_TRACECLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_TRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_TRACECLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 */ -/*! @{ */ - -#define SYSCON_FLEXFRG0CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG0CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG0CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG0CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG0CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG0CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG0CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG0CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 */ -/*! @{ */ - -#define SYSCON_FLEXFRG1CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG1CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG1CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG1CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG1CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG1CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG1CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG1CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 */ -/*! @{ */ - -#define SYSCON_FLEXFRG2CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG2CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG2CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG2CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG2CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG2CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG2CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG2CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 */ -/*! @{ */ - -#define SYSCON_FLEXFRG3CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG3CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG3CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG3CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG3CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG3CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG3CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG3CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 */ -/*! @{ */ - -#define SYSCON_FLEXFRG4CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG4CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG4CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG4CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG4CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG4CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG4CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG4CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 */ -/*! @{ */ - -#define SYSCON_FLEXFRG5CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG5CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG5CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG5CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG5CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG5CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG5CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG5CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 */ -/*! @{ */ - -#define SYSCON_FLEXFRG6CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG6CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG6CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG6CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG6CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG6CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG6CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG6CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 */ -/*! @{ */ - -#define SYSCON_FLEXFRG7CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG7CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG7CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG7CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG7CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG7CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG7CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG7CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRGXCTRL - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_FLEXFRGXCTRL_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_FLEXFRGXCTRL_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_FLEXFRGXCTRL_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRGXCTRL_DATA_SHIFT)) & SYSCON_FLEXFRGXCTRL_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_FLEXFRGXCTRL */ -#define SYSCON_FLEXFRGXCTRL_COUNT (8U) - -/*! @name AHBCLKDIV - System clock divider */ -/*! @{ */ - -#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) - -#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) - -#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) - -#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name CLKOUTDIV - CLKOUT clock divider */ -/*! @{ */ - -#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) -#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) - -#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) -#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) - -#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) -#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) - -#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name FROHFDIV - FRO_HF (96MHz) clock divider */ -/*! @{ */ - -#define SYSCON_FROHFDIV_DIV_MASK (0xFFU) -#define SYSCON_FROHFDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) - -#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U) -#define SYSCON_FROHFDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK) - -#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) -#define SYSCON_FROHFDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) - -#define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_FROHFDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name WDTCLKDIV - WDT clock divider */ -/*! @{ */ - -#define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU) -#define SYSCON_WDTCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_WDTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK) - -#define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_WDTCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_WDTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK) - -#define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_WDTCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_WDTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK) - -#define SYSCON_WDTCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_WDTCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_WDTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_REQFLAG_SHIFT)) & SYSCON_WDTCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name ADCCLKDIV - ADC clock divider */ -/*! @{ */ - -#define SYSCON_ADCCLKDIV_DIV_MASK (0x7U) -#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) - -#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) - -#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) - -#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name USB0CLKDIV - USB0 Clock divider */ -/*! @{ */ - -#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) -#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) - -#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) - -#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) - -#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name MCLKDIV - I2S MCLK clock divider */ -/*! @{ */ - -#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_MCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) - -#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_MCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) - -#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_MCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) - -#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name SCTCLKDIV - SCT/PWM clock divider */ -/*! @{ */ - -#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) - -#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) - -#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) - -#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name SDIOCLKDIV - SDIO clock divider */ -/*! @{ */ - -#define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK) - -#define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK) - -#define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK) - -#define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name PLL0CLKDIV - PLL0 clock divider */ -/*! @{ */ - -#define SYSCON_PLL0CLKDIV_DIV_MASK (0xFFU) -#define SYSCON_PLL0CLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_PLL0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_DIV_SHIFT)) & SYSCON_PLL0CLKDIV_DIV_MASK) - -#define SYSCON_PLL0CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_PLL0CLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_PLL0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_RESET_SHIFT)) & SYSCON_PLL0CLKDIV_RESET_MASK) - -#define SYSCON_PLL0CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_PLL0CLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_PLL0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_HALT_SHIFT)) & SYSCON_PLL0CLKDIV_HALT_MASK) - -#define SYSCON_PLL0CLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_PLL0CLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_PLL0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_REQFLAG_SHIFT)) & SYSCON_PLL0CLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) */ -/*! @{ */ - -#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK (0xFFFFFFFFU) -#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT (0U) -/*! CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL). - * 0b00000000000000000000000000000001..update all clock configuration. - * 0b00000000000000000000000000000000..all hardware clock configruration are freeze. - */ -#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK) -/*! @} */ - -/*! @name FMCCR - FMC configuration register */ -/*! @{ */ - -#define SYSCON_FMCCR_FETCHCFG_MASK (0x3U) -#define SYSCON_FMCCR_FETCHCFG_SHIFT (0U) -/*! FETCHCFG - Instruction fetch configuration. - * 0b00..Instruction fetches from flash are not buffered. - * 0b01..One buffer is used for all instruction fetches. - * 0b10..All buffers may be used for instruction fetches. - */ -#define SYSCON_FMCCR_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCFG_SHIFT)) & SYSCON_FMCCR_FETCHCFG_MASK) - -#define SYSCON_FMCCR_DATACFG_MASK (0xCU) -#define SYSCON_FMCCR_DATACFG_SHIFT (2U) -/*! DATACFG - Data read configuration. - * 0b00..Data accesses from flash are not buffered. - * 0b01..One buffer is used for all data accesses. - * 0b10..All buffers can be used for data accesses. - */ -#define SYSCON_FMCCR_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACFG_SHIFT)) & SYSCON_FMCCR_DATACFG_MASK) - -#define SYSCON_FMCCR_ACCEL_MASK (0x10U) -#define SYSCON_FMCCR_ACCEL_SHIFT (4U) -/*! ACCEL - Acceleration enable. - * 0b0..Flash acceleration is disabled. - * 0b1..Flash acceleration is enabled. - */ -#define SYSCON_FMCCR_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK) - -#define SYSCON_FMCCR_PREFEN_MASK (0x20U) -#define SYSCON_FMCCR_PREFEN_SHIFT (5U) -/*! PREFEN - Prefetch enable. - * 0b0..No instruction prefetch is performed. - * 0b1..Instruction prefetch is enabled. - */ -#define SYSCON_FMCCR_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK) - -#define SYSCON_FMCCR_PREFOVR_MASK (0x40U) -#define SYSCON_FMCCR_PREFOVR_SHIFT (6U) -/*! PREFOVR - Prefetch override. - * 0b0..Any previously initiated prefetch will be completed. - * 0b1..Any previously initiated prefetch will be aborted, and the next flash line following the current - * execution address will be prefetched if not already buffered. - */ -#define SYSCON_FMCCR_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK) - -#define SYSCON_FMCCR_FLASHTIM_MASK (0xF000U) -#define SYSCON_FMCCR_FLASHTIM_SHIFT (12U) -/*! FLASHTIM - Flash memory access time. - * 0b0000..1 system clock flash access time (for system clock rates up to 11 MHz). - * 0b0001..2 system clocks flash access time (for system clock rates up to 22 MHz). - * 0b0010..3 system clocks flash access time (for system clock rates up to 33 MHz). - * 0b0011..4 system clocks flash access time (for system clock rates up to 44 MHz). - * 0b0100..5 system clocks flash access time (for system clock rates up to 55 MHz). - * 0b0101..6 system clocks flash access time (for system clock rates up to 66 MHz). - * 0b0110..7 system clocks flash access time (for system clock rates up to 77 MHz). - * 0b0111..8 system clocks flash access time (for system clock rates up to 88 MHz). - * 0b1000..9 system clocks flash access time (for system clock rates up to 100 MHz). - * 0b1001..10 system clocks flash access time (for system clock rates up to 115 MHz). - * 0b1010..11 system clocks flash access time (for system clock rates up to 130 MHz). - * 0b1011..12 system clocks flash access time (for system clock rates up to 150 MHz). - */ -#define SYSCON_FMCCR_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FLASHTIM_SHIFT)) & SYSCON_FMCCR_FLASHTIM_MASK) -/*! @} */ - -/*! @name USB0NEEDCLKCTRL - USB0 need clock control */ -/*! @{ */ - -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK (0x1U) -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT (0U) -/*! AP_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. - */ -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK) - -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK (0x2U) -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT (1U) -/*! POL_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. - * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. - * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK) - -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK (0x4U) -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT (2U) -/*! AP_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. - */ -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK) - -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK (0x8U) -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT (3U) -/*! POL_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. - * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. - * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK) -/*! @} */ - -/*! @name USB0NEEDCLKSTAT - USB0 need clock status */ -/*! @{ */ - -#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) -#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) -/*! DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal status:. - * 0b1..USB0 Device clock is high. - * 0b0..USB0 Device clock is low. - */ -#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK) - -#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) -#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) -/*! HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal status:. - * 0b1..USB0 Host clock is high. - * 0b0..USB0 Host clock is low. - */ -#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK) -/*! @} */ - -/*! @name FMCFLUSH - FMCflush control */ -/*! @{ */ - -#define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U) -#define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U) -/*! FLUSH - Flush control - * 0b1..Flush the FMC buffer contents. - * 0b0..No action is performed. - */ -#define SYSCON_FMCFLUSH_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK) -/*! @} */ - -/*! @name MCLKIO - MCLK control */ -/*! @{ */ - -#define SYSCON_MCLKIO_MCLKIO_MASK (0x1U) -#define SYSCON_MCLKIO_MCLKIO_SHIFT (0U) -/*! MCLKIO - MCLK control. - * 0b0..input mode. - * 0b1..output mode. - */ -#define SYSCON_MCLKIO_MCLKIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK) -/*! @} */ - -/*! @name USB1NEEDCLKCTRL - USB1 need clock control */ -/*! @{ */ - -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK (0x1U) -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT (0U) -/*! AP_HS_DEV_NEEDCLK - USB1 Device need_clock signal control: - * 0b0..HOST_NEEDCLK is under hardware control. - * 0b1..HOST_NEEDCLK is forced high. - */ -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK) - -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK (0x2U) -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT (1U) -/*! POL_HS_DEV_NEEDCLK - USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt: - * 0b0..Falling edge of DEV_NEEDCLK triggers wake-up. - * 0b1..Rising edge of DEV_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK) - -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK (0x4U) -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT (2U) -/*! AP_HS_HOST_NEEDCLK - USB1 Host need clock signal control: - * 0b0..HOST_NEEDCLK is under hardware control. - * 0b1..HOST_NEEDCLK is forced high. - */ -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK) - -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK (0x8U) -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT (3U) -/*! POL_HS_HOST_NEEDCLK - USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. - * 0b0..Falling edge of HOST_NEEDCLK triggers wake-up. - * 0b1..Rising edge of HOST_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK) - -#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U) -#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U) -/*! HS_DEV_WAKEUP_N - Software override of device controller PHY wake up logic. - * 0b0..Forces USB1_PHY to wake-up. - * 0b1..Normal USB1_PHY behavior. - */ -#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK) -/*! @} */ - -/*! @name USB1NEEDCLKSTAT - USB1 need clock status */ -/*! @{ */ - -#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) -#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) -/*! DEV_NEEDCLK - USB1 Device need_clock signal status:. - * 0b1..DEV_NEEDCLK is high. - * 0b0..DEV_NEEDCLK is low. - */ -#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK) - -#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) -#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) -/*! HOST_NEEDCLK - USB1 Host need_clock signal status:. - * 0b1..HOST_NEEDCLK is high. - * 0b0..HOST_NEEDCLK is low. - */ -#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK) -/*! @} */ - -/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */ -/*! @{ */ - -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U) -/*! CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in. - * 0b00..0 degree shift. - * 0b01..90 degree shift. - * 0b10..180 degree shift. - * 0b11..270 degree shift. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK) - -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U) -/*! CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. - * 0b00..0 degree shift. - * 0b01..90 degree shift. - * 0b10..180 degree shift. - * 0b11..270 degree shift. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK) - -#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) -#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U) -/*! PHASE_ACTIVE - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE. - * 0b0..Bypassed. - * 0b1..Activates phase shift logic. When active, the clock divider is active and phase delays are enabled. - */ -#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK) - -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U) -/*! CCLK_DRV_DELAY - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK) - -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U) -/*! CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field. - * 0b1..Enable drive delay. - * 0b0..Disable drive delay. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK) - -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U) -/*! CCLK_SAMPLE_DELAY - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK) - -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U) -/*! CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. - * 0b1..Enables sample delay. - * 0b0..Disables sample delay. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK) -/*! @} */ - -/*! @name PLL1CTRL - PLL1 550m control */ -/*! @{ */ - -#define SYSCON_PLL1CTRL_SELR_MASK (0xFU) -#define SYSCON_PLL1CTRL_SELR_SHIFT (0U) -/*! SELR - Bandwidth select R value. - */ -#define SYSCON_PLL1CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK) - -#define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U) -#define SYSCON_PLL1CTRL_SELI_SHIFT (4U) -/*! SELI - Bandwidth select I value. - */ -#define SYSCON_PLL1CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK) - -#define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U) -#define SYSCON_PLL1CTRL_SELP_SHIFT (10U) -/*! SELP - Bandwidth select P value. - */ -#define SYSCON_PLL1CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U) -#define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U) -/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - * 0b1..PLL input clock is sent directly to the PLL output. - * 0b0..use PLL. - */ -#define SYSCON_PLL1CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U) -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U) -/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - * 0b1..bypass of the divide-by-2 divider in the post-divider. - * 0b0..use the divide-by-2 divider in the post-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) - -#define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U) -#define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U) -/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. - */ -#define SYSCON_PLL1CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK) - -#define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U) -#define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U) -/*! BWDIRECT - control of the bandwidth of the PLL. - * 0b1..modify the bandwidth of the PLL directly. - * 0b0..the bandwidth is changed synchronously with the feedback-divider. - */ -#define SYSCON_PLL1CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U) -#define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U) -/*! BYPASSPREDIV - bypass of the pre-divider. - * 0b1..bypass of the pre-divider. - * 0b0..use the pre-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U) -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U) -/*! BYPASSPOSTDIV - bypass of the post-divider. - * 0b1..bypass of the post-divider. - * 0b0..use the post-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) - -#define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U) -#define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U) -/*! CLKEN - enable the output clock. - * 0b1..Enable the output clock. - * 0b0..Disable the output clock. - */ -#define SYSCON_PLL1CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK) - -#define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U) -#define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U) -/*! FRMEN - 1: free running mode. - */ -#define SYSCON_PLL1CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK) - -#define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U) -#define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U) -/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable. - */ -#define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK) - -#define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U) -#define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U) -/*! SKEWEN - Skew mode. - * 0b1..skewmode is enable. - * 0b0..skewmode is disable. - */ -#define SYSCON_PLL1CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK) -/*! @} */ - -/*! @name PLL1STAT - PLL1 550m status */ -/*! @{ */ - -#define SYSCON_PLL1STAT_LOCK_MASK (0x1U) -#define SYSCON_PLL1STAT_LOCK_SHIFT (0U) -/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. - */ -#define SYSCON_PLL1STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK) - -#define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U) -#define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U) -/*! PREDIVACK - pre-divider ratio change acknowledge. - */ -#define SYSCON_PLL1STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK) - -#define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U) -#define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U) -/*! FEEDDIVACK - feedback divider ratio change acknowledge. - */ -#define SYSCON_PLL1STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK) - -#define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U) -#define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U) -/*! POSTDIVACK - post-divider ratio change acknowledge. - */ -#define SYSCON_PLL1STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK) - -#define SYSCON_PLL1STAT_FRMDET_MASK (0x10U) -#define SYSCON_PLL1STAT_FRMDET_SHIFT (4U) -/*! FRMDET - free running detector output (active high). - */ -#define SYSCON_PLL1STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK) -/*! @} */ - -/*! @name PLL1NDEC - PLL1 550m N divider */ -/*! @{ */ - -#define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU) -#define SYSCON_PLL1NDEC_NDIV_SHIFT (0U) -/*! NDIV - pre-divider divider ratio (N-divider). - */ -#define SYSCON_PLL1NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK) - -#define SYSCON_PLL1NDEC_NREQ_MASK (0x100U) -#define SYSCON_PLL1NDEC_NREQ_SHIFT (8U) -/*! NREQ - pre-divider ratio change request. - */ -#define SYSCON_PLL1NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK) -/*! @} */ - -/*! @name PLL1MDEC - PLL1 550m M divider */ -/*! @{ */ - -#define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU) -#define SYSCON_PLL1MDEC_MDIV_SHIFT (0U) -/*! MDIV - feedback divider divider ratio (M-divider). - */ -#define SYSCON_PLL1MDEC_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK) - -#define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U) -#define SYSCON_PLL1MDEC_MREQ_SHIFT (16U) -/*! MREQ - feedback ratio change request. - */ -#define SYSCON_PLL1MDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK) -/*! @} */ - -/*! @name PLL1PDEC - PLL1 550m P divider */ -/*! @{ */ - -#define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU) -#define SYSCON_PLL1PDEC_PDIV_SHIFT (0U) -/*! PDIV - post-divider divider ratio (P-divider) - */ -#define SYSCON_PLL1PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK) - -#define SYSCON_PLL1PDEC_PREQ_MASK (0x20U) -#define SYSCON_PLL1PDEC_PREQ_SHIFT (5U) -/*! PREQ - feedback ratio change request. - */ -#define SYSCON_PLL1PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK) -/*! @} */ - -/*! @name PLL0CTRL - PLL0 550m control */ -/*! @{ */ - -#define SYSCON_PLL0CTRL_SELR_MASK (0xFU) -#define SYSCON_PLL0CTRL_SELR_SHIFT (0U) -/*! SELR - Bandwidth select R value. - */ -#define SYSCON_PLL0CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK) - -#define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U) -#define SYSCON_PLL0CTRL_SELI_SHIFT (4U) -/*! SELI - Bandwidth select I value. - */ -#define SYSCON_PLL0CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK) - -#define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U) -#define SYSCON_PLL0CTRL_SELP_SHIFT (10U) -/*! SELP - Bandwidth select P value. - */ -#define SYSCON_PLL0CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U) -#define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U) -/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - * 0b1..Bypass PLL input clock is sent directly to the PLL output. - * 0b0..use PLL. - */ -#define SYSCON_PLL0CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U) -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U) -/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - * 0b1..bypass of the divide-by-2 divider in the post-divider. - * 0b0..use the divide-by-2 divider in the post-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) - -#define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U) -#define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U) -/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. - */ -#define SYSCON_PLL0CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK) - -#define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U) -#define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U) -/*! BWDIRECT - Control of the bandwidth of the PLL. - * 0b1..modify the bandwidth of the PLL directly. - * 0b0..the bandwidth is changed synchronously with the feedback-divider. - */ -#define SYSCON_PLL0CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U) -#define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U) -/*! BYPASSPREDIV - bypass of the pre-divider. - * 0b1..bypass of the pre-divider. - * 0b0..use the pre-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U) -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U) -/*! BYPASSPOSTDIV - bypass of the post-divider. - * 0b1..bypass of the post-divider. - * 0b0..use the post-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) - -#define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U) -#define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U) -/*! CLKEN - enable the output clock. - * 0b1..enable the output clock. - * 0b0..disable the output clock. - */ -#define SYSCON_PLL0CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK) - -#define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U) -#define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U) -/*! FRMEN - free running mode. - * 0b1..free running mode is enable. - * 0b0..free running mode is disable. - */ -#define SYSCON_PLL0CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK) - -#define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U) -#define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U) -/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable. - */ -#define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK) - -#define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U) -#define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U) -/*! SKEWEN - skew mode. - * 0b1..skew mode is enable. - * 0b0..skew mode is disable. - */ -#define SYSCON_PLL0CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK) -/*! @} */ - -/*! @name PLL0STAT - PLL0 550m status */ -/*! @{ */ - -#define SYSCON_PLL0STAT_LOCK_MASK (0x1U) -#define SYSCON_PLL0STAT_LOCK_SHIFT (0U) -/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. - */ -#define SYSCON_PLL0STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK) - -#define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U) -#define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U) -/*! PREDIVACK - pre-divider ratio change acknowledge. - */ -#define SYSCON_PLL0STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK) - -#define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U) -#define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U) -/*! FEEDDIVACK - feedback divider ratio change acknowledge. - */ -#define SYSCON_PLL0STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK) - -#define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U) -#define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U) -/*! POSTDIVACK - post-divider ratio change acknowledge. - */ -#define SYSCON_PLL0STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK) - -#define SYSCON_PLL0STAT_FRMDET_MASK (0x10U) -#define SYSCON_PLL0STAT_FRMDET_SHIFT (4U) -/*! FRMDET - free running detector output (active high). - */ -#define SYSCON_PLL0STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK) -/*! @} */ - -/*! @name PLL0NDEC - PLL0 550m N divider */ -/*! @{ */ - -#define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU) -#define SYSCON_PLL0NDEC_NDIV_SHIFT (0U) -/*! NDIV - pre-divider divider ratio (N-divider). - */ -#define SYSCON_PLL0NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK) - -#define SYSCON_PLL0NDEC_NREQ_MASK (0x100U) -#define SYSCON_PLL0NDEC_NREQ_SHIFT (8U) -/*! NREQ - pre-divider ratio change request. - */ -#define SYSCON_PLL0NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK) -/*! @} */ - -/*! @name PLL0PDEC - PLL0 550m P divider */ -/*! @{ */ - -#define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU) -#define SYSCON_PLL0PDEC_PDIV_SHIFT (0U) -/*! PDIV - post-divider divider ratio (P-divider) - */ -#define SYSCON_PLL0PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK) - -#define SYSCON_PLL0PDEC_PREQ_MASK (0x20U) -#define SYSCON_PLL0PDEC_PREQ_SHIFT (5U) -/*! PREQ - feedback ratio change request. - */ -#define SYSCON_PLL0PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK) -/*! @} */ - -/*! @name PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 */ -/*! @{ */ - -#define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU) -#define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U) -/*! MD_LBS - input word of the wrapper bit 31 to 0. - */ -#define SYSCON_PLL0SSCG0_MD_LBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK) -/*! @} */ - -/*! @name PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 */ -/*! @{ */ - -#define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U) -#define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U) -/*! MD_MBS - input word of the wrapper bit 32. - */ -#define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK) - -#define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U) -#define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U) -/*! MD_REQ - md change request. - */ -#define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK) - -#define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) -#define SYSCON_PLL0SSCG1_MF_SHIFT (2U) -/*! MF - programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3. - */ -#define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK) - -#define SYSCON_PLL0SSCG1_MR_MASK (0xE0U) -#define SYSCON_PLL0SSCG1_MR_SHIFT (5U) -/*! MR - programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) - * mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1. - */ -#define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK) - -#define SYSCON_PLL0SSCG1_MC_MASK (0x300U) -#define SYSCON_PLL0SSCG1_MC_SHIFT (8U) -/*! MC - modulation waveform control Compensation for low pass filtering of the PLL to get a - * triangular modulation at the output of the PLL, giving a flat frequency spectrum. - */ -#define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK) - -#define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U) -#define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U) -/*! MDIV_EXT - to select an external mdiv value. - */ -#define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) - -#define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U) -#define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U) -/*! MREQ - to select an external mreq value. - */ -#define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK) - -#define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U) -#define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U) -/*! DITHER - dithering between two modulation frequencies in a random way or in a pseudo random way - * (white noise), in order to decrease the probability that the modulated waveform will occur - * with the same phase on a particular point on the screen. - */ -#define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK) - -#define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U) -#define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U) -/*! SEL_EXT - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext. - */ -#define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK) -/*! @} */ - -/*! @name FUNCRETENTIONCTRL - Functional retention control register */ -/*! @{ */ - -#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK (0x1U) -#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT (0U) -/*! FUNCRETENA - functional retention in power down only. - * 0b1..enable functional retention. - * 0b0..disable functional retention. - */ -#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK) - -#define SYSCON_FUNCRETENTIONCTRL_RET_START_MASK (0x3FFEU) -#define SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT (1U) -/*! RET_START - Start address divided by 4 inside SRAMX bank. - */ -#define SYSCON_FUNCRETENTIONCTRL_RET_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_START_MASK) - -#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK (0xFFC000U) -#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT (14U) -/*! RET_LENTH - lenth of Scan chains to save. - */ -#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) -/*! @} */ - -/*! @name CPUCTRL - CPU Control for multiple processors */ -/*! @{ */ - -#define SYSCON_CPUCTRL_CPU1CLKEN_MASK (0x8U) -#define SYSCON_CPUCTRL_CPU1CLKEN_SHIFT (3U) -/*! CPU1CLKEN - CPU1 clock enable. - * 0b1..The CPU1 clock is enabled. - * 0b0..The CPU1 clock is not enabled. - */ -#define SYSCON_CPUCTRL_CPU1CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1CLKEN_SHIFT)) & SYSCON_CPUCTRL_CPU1CLKEN_MASK) - -#define SYSCON_CPUCTRL_CPU1RSTEN_MASK (0x20U) -#define SYSCON_CPUCTRL_CPU1RSTEN_SHIFT (5U) -/*! CPU1RSTEN - CPU1 reset. - * 0b1..The CPU1 is being reset. - * 0b0..The CPU1 is not being reset. - */ -#define SYSCON_CPUCTRL_CPU1RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1RSTEN_SHIFT)) & SYSCON_CPUCTRL_CPU1RSTEN_MASK) -/*! @} */ - -/*! @name CPBOOT - Coprocessor Boot Address */ -/*! @{ */ - -#define SYSCON_CPBOOT_CPBOOT_MASK (0xFFFFFFFFU) -#define SYSCON_CPBOOT_CPBOOT_SHIFT (0U) -/*! CPBOOT - Coprocessor Boot Address for CPU1. - */ -#define SYSCON_CPBOOT_CPBOOT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_CPBOOT_SHIFT)) & SYSCON_CPBOOT_CPBOOT_MASK) -/*! @} */ - -/*! @name CPSTAT - CPU Status */ -/*! @{ */ - -#define SYSCON_CPSTAT_CPU0SLEEPING_MASK (0x1U) -#define SYSCON_CPSTAT_CPU0SLEEPING_SHIFT (0U) -/*! CPU0SLEEPING - The CPU0 sleeping state. - * 0b1..the CPU is sleeping. - * 0b0..the CPU is not sleeping. - */ -#define SYSCON_CPSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU0SLEEPING_MASK) - -#define SYSCON_CPSTAT_CPU1SLEEPING_MASK (0x2U) -#define SYSCON_CPSTAT_CPU1SLEEPING_SHIFT (1U) -/*! CPU1SLEEPING - The CPU1 sleeping state. - * 0b1..the CPU is sleeping. - * 0b0..the CPU is not sleeping. - */ -#define SYSCON_CPSTAT_CPU1SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU1SLEEPING_MASK) - -#define SYSCON_CPSTAT_CPU0LOCKUP_MASK (0x4U) -#define SYSCON_CPSTAT_CPU0LOCKUP_SHIFT (2U) -/*! CPU0LOCKUP - The CPU0 lockup state. - * 0b1..the CPU is in lockup. - * 0b0..the CPU is not in lockup. - */ -#define SYSCON_CPSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU0LOCKUP_MASK) - -#define SYSCON_CPSTAT_CPU1LOCKUP_MASK (0x8U) -#define SYSCON_CPSTAT_CPU1LOCKUP_SHIFT (3U) -/*! CPU1LOCKUP - The CPU1 lockup state. - * 0b1..the CPU is in lockup. - * 0b0..the CPU is not in lockup. - */ -#define SYSCON_CPSTAT_CPU1LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU1LOCKUP_MASK) -/*! @} */ - -/*! @name CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures */ -/*! @{ */ - -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U) -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U) -/*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U) -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U) -/*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U) -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U) -/*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U) -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U) -/*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) -#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) -/*! CLKIN_ENA - Enable clock_in clock for clock module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) -/*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U) -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U) -/*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U) -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U) -/*! XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U) -#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U) -/*! PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK) -/*! @} */ - -/*! @name COMP_INT_CTRL - Comparator Interrupt control */ -/*! @{ */ - -#define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U) -#define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U) -/*! INT_ENABLE - Analog Comparator interrupt enable control:. - * 0b1..interrupt enable. - * 0b0..interrupt disable. - */ -#define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK) - -#define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U) -#define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U) -/*! INT_CLEAR - Analog Comparator interrupt clear. - * 0b0..No effect. - * 0b1..Clear the interrupt. Self-cleared bit. - */ -#define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK) - -#define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU) -#define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U) -/*! INT_CTRL - Comparator interrupt type selector:. - * 0b000..The analog comparator interrupt edge sensitive is disabled. - * 0b010..analog comparator interrupt is rising edge sensitive. - * 0b100..analog comparator interrupt is falling edge sensitive. - * 0b110..analog comparator interrupt is rising and falling edge sensitive. - * 0b001..The analog comparator interrupt level sensitive is disabled. - * 0b011..Analog Comparator interrupt is high level sensitive. - * 0b101..Analog Comparator interrupt is low level sensitive. - * 0b111..The analog comparator interrupt level sensitive is disabled. - */ -#define SYSCON_COMP_INT_CTRL_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK) - -#define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U) -#define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U) -/*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. - * 0b0..Select Analog Comparator filtered output as input for interrupt detection. - * 0b1..Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when - * Analog comparator is used as wake up source in Power down mode. - */ -#define SYSCON_COMP_INT_CTRL_INT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK) -/*! @} */ - -/*! @name COMP_INT_STATUS - Comparator Interrupt status */ -/*! @{ */ - -#define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U) -#define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U) -/*! STATUS - Interrupt status BEFORE Interrupt Enable. - * 0b0..no interrupt pending. - * 0b1..interrupt pending. - */ -#define SYSCON_COMP_INT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK) - -#define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U) -#define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U) -/*! INT_STATUS - Interrupt status AFTER Interrupt Enable. - * 0b0..no interrupt pending. - * 0b1..interrupt pending. - */ -#define SYSCON_COMP_INT_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) - -#define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U) -#define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U) -/*! VAL - comparator analog output. - * 0b1..P+ is greater than P-. - * 0b0..P+ is smaller than P-. - */ -#define SYSCON_COMP_INT_STATUS_VAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK) -/*! @} */ - -/*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */ -/*! @{ */ - -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U) -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U) -/*! ROM - Control automatic clock gating of ROM controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK (0x2U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT (1U) -/*! RAMX_CTRL - Control automatic clock gating of RAMX controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK (0x4U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT (2U) -/*! RAM0_CTRL - Control automatic clock gating of RAM0 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK (0x8U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT (3U) -/*! RAM1_CTRL - Control automatic clock gating of RAM1 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK (0x10U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT (4U) -/*! RAM2_CTRL - Control automatic clock gating of RAM2 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK (0x20U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT (5U) -/*! RAM3_CTRL - Control automatic clock gating of RAM3 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK (0x40U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT (6U) -/*! RAM4_CTRL - Control automatic clock gating of RAM4 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U) -/*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U) -/*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U) -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U) -/*! CRCGEN - Control automatic clock gating of CRCGEN controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U) -/*! SDMA0 - Control automatic clock gating of DMA0 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U) -/*! SDMA1 - Control automatic clock gating of DMA1 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK (0x4000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT (14U) -/*! USB0 - Control automatic clock gating of USB controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U) -/*! SYSCON - Control automatic clock gating of synchronous system controller registers bank. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U) -/*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. - * 0b1100000011011110..Bit Fields 0 - 15 of this register are updated - * 0b0000000000000000..Bit Fields 0 - 15 of this register are not updated - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK) -/*! @} */ - -/*! @name GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module */ -/*! @{ */ - -#define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U) -#define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U) -/*! PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module. - * 0b1..bypass of the first stage of synchonization inside GPIO_INT module. - * 0b0..use the first stage of synchonization inside GPIO_INT module. - */ -#define SYSCON_GPIOPSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK) -/*! @} */ - -/*! @name DEBUG_LOCK_EN - Control write access to security registers. */ -/*! @{ */ - -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) -/*! LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, - * CODESECURITYPROTCPU1, CPU0_DEBUG_FEATURES, CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. - * 0b1010..1010: Enable write access to all 6 registers. - * 0b0000..Any other value than b1010: disable write access to all 6 registers. - */ -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) -/*! @} */ - -/*! @name DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control. */ -/*! @{ */ - -#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) -#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) -/*! CPU0_DBGEN - CPU0 Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) -#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) -/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK (0x30U) -#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (4U) -/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0xC0U) -#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U) -/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK (0x300U) -#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT (8U) -/*! CPU1_DBGEN - CPU1 Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK (0xC00U) -#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT (10U) -/*! CPU1_NIDEN - CPU1 Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK) -/*! @} */ - -/*! @name DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register. */ -/*! @{ */ - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) -/*! CPU0_DBGEN - CPU0 (CPU0) Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) -/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U) -/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U) -/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK (0x300U) -#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT (8U) -/*! CPU1_DBGEN - CPU1 Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK (0xC00U) -#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT (10U) -/*! CPU1_NIDEN - CPU1 Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK) -/*! @} */ - -/*! @name KEY_BLOCK - block quiddikey/PUF all index. */ -/*! @{ */ - -#define SYSCON_KEY_BLOCK_KEY_BLOCK_MASK (0xFFFFFFFFU) -#define SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT (0U) -/*! KEY_BLOCK - Write a value to block quiddikey/PUF all index. - */ -#define SYSCON_KEY_BLOCK_KEY_BLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCON_KEY_BLOCK_KEY_BLOCK_MASK) -/*! @} */ - -/*! @name DEBUG_AUTH_BEACON - Debug authentication BEACON register */ -/*! @{ */ - -#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) -#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) -/*! BEACON - Set by the debug authentication code in ROM to pass the debug beacons (Credential - * Beacon and Authentication Beacon) to application code. - */ -#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) -/*! @} */ - -/*! @name CPUCFG - CPUs configuration register */ -/*! @{ */ - -#define SYSCON_CPUCFG_CPU1ENABLE_MASK (0x4U) -#define SYSCON_CPUCFG_CPU1ENABLE_SHIFT (2U) -/*! CPU1ENABLE - Enable CPU1. - * 0b0..CPU1 is disable (Processor in reset). - * 0b1..CPU1 is enable. - */ -#define SYSCON_CPUCFG_CPU1ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCFG_CPU1ENABLE_SHIFT)) & SYSCON_CPUCFG_CPU1ENABLE_MASK) -/*! @} */ - -/*! @name DEVICE_ID0 - Device ID */ -/*! @{ */ - -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) -/*! ROM_REV_MINOR - ROM revision. - */ -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) -/*! @} */ - -/*! @name DIEID - Chip revision ID and Number */ -/*! @{ */ - -#define SYSCON_DIEID_REV_ID_MASK (0xFU) -#define SYSCON_DIEID_REV_ID_SHIFT (0U) -/*! REV_ID - Chip Metal Revision ID. - */ -#define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK) - -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U) -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U) -/*! MCO_NUM_IN_DIE_ID - Chip Number 0x426B. - */ -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SYSCON_Register_Masks */ - - -/* SYSCON - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SYSCON base address */ - #define SYSCON_BASE (0x50000000u) - /** Peripheral SYSCON base address */ - #define SYSCON_BASE_NS (0x40000000u) - /** Peripheral SYSCON base pointer */ - #define SYSCON ((SYSCON_Type *)SYSCON_BASE) - /** Peripheral SYSCON base pointer */ - #define SYSCON_NS ((SYSCON_Type *)SYSCON_BASE_NS) - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS { SYSCON_BASE } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS { SYSCON } - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS_NS { SYSCON_BASE_NS } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS_NS { SYSCON_NS } -#else - /** Peripheral SYSCON base address */ - #define SYSCON_BASE (0x40000000u) - /** Peripheral SYSCON base pointer */ - #define SYSCON ((SYSCON_Type *)SYSCON_BASE) - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS { SYSCON_BASE } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS { SYSCON } -#endif - -/*! - * @} - */ /* end of group SYSCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SYSCTL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCTL_Peripheral_Access_Layer SYSCTL Peripheral Access Layer - * @{ - */ - -/** SYSCTL - Register Layout Typedef */ -typedef struct { - __IO uint32_t UPDATELCKOUT; /**< update lock out control, offset: 0x0 */ - uint8_t RESERVED_0[60]; - __IO uint32_t FCCTRLSEL[8]; /**< Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_1[32]; - __IO uint32_t SHAREDCTRLSET[2]; /**< Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1., array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_2[120]; - __I uint32_t USB_HS_STATUS; /**< Status register for USB HS, offset: 0x100 */ -} SYSCTL_Type; - -/* ---------------------------------------------------------------------------- - -- SYSCTL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCTL_Register_Masks SYSCTL Register Masks - * @{ - */ - -/*! @name UPDATELCKOUT - update lock out control */ -/*! @{ */ - -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U) -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U) -/*! UPDATELCKOUT - All Registers - * 0b0..Normal Mode. Can be written to. - * 0b1..Protected Mode. Cannot be written to. - */ -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK) -/*! @} */ - -/*! @name FCCTRLSEL - Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7 */ -/*! @{ */ - -#define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U) -#define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U) -/*! SCKINSEL - Selects the source for SCK going into this Flexcomm. - * 0b00..Selects the dedicated FCn_SCK function for this Flexcomm. - * 0b01..SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK) - -#define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U) -#define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U) -/*! WSINSEL - Selects the source for WS going into this Flexcomm. - * 0b00..Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. - * 0b01..WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK) - -#define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U) -#define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U) -/*! DATAINSEL - Selects the source for DATA input to this Flexcomm. - * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. - * 0b01..Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK) - -#define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U) -#define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U) -/*! DATAOUTSEL - Selects the source for DATA output from this Flexcomm. - * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. - * 0b01..Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_DATAOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK) -/*! @} */ - -/* The count of SYSCTL_FCCTRLSEL */ -#define SYSCTL_FCCTRLSEL_COUNT (8U) - -/*! @name SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */ -/*! @{ */ - -#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U) -#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U) -/*! SHAREDSCKSEL - Selects the source for SCK of this shared signal set. - * 0b000..SCK for this shared signal set comes from Flexcomm 0. - * 0b001..SCK for this shared signal set comes from Flexcomm 1. - * 0b010..SCK for this shared signal set comes from Flexcomm 2. - * 0b011..SCK for this shared signal set comes from Flexcomm 3. - * 0b100..SCK for this shared signal set comes from Flexcomm 4. - * 0b101..SCK for this shared signal set comes from Flexcomm 5. - * 0b110..SCK for this shared signal set comes from Flexcomm 6. - * 0b111..SCK for this shared signal set comes from Flexcomm 7. - */ -#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK) - -#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U) -#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U) -/*! SHAREDWSSEL - Selects the source for WS of this shared signal set. - * 0b000..WS for this shared signal set comes from Flexcomm 0. - * 0b001..WS for this shared signal set comes from Flexcomm 1. - * 0b010..WS for this shared signal set comes from Flexcomm 2. - * 0b011..WS for this shared signal set comes from Flexcomm 3. - * 0b100..WS for this shared signal set comes from Flexcomm 4. - * 0b101..WS for this shared signal set comes from Flexcomm 5. - * 0b110..WS for this shared signal set comes from Flexcomm 6. - * 0b111..WS for this shared signal set comes from Flexcomm 7. - */ -#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK) - -#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U) -#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U) -/*! SHAREDDATASEL - Selects the source for DATA input for this shared signal set. - * 0b000..DATA input for this shared signal set comes from Flexcomm 0. - * 0b001..DATA input for this shared signal set comes from Flexcomm 1. - * 0b010..DATA input for this shared signal set comes from Flexcomm 2. - * 0b011..DATA input for this shared signal set comes from Flexcomm 3. - * 0b100..DATA input for this shared signal set comes from Flexcomm 4. - * 0b101..DATA input for this shared signal set comes from Flexcomm 5. - * 0b110..DATA input for this shared signal set comes from Flexcomm 6. - * 0b111..DATA input for this shared signal set comes from Flexcomm 7. - */ -#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U) -#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U) -/*! FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC0 does not contribute to this shared set. - * 0b1..Data output from FC0 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U) -#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U) -/*! FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC1 does not contribute to this shared set. - * 0b1..Data output from FC1 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK (0x40000U) -#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT (18U) -/*! FC2DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC2 does not contribute to this shared set. - * 0b1..Data output from FC2 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U) -#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U) -/*! FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC4 does not contribute to this shared set. - * 0b1..Data output from FC4 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U) -#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U) -/*! FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC5 does not contribute to this shared set. - * 0b1..Data output from FC5 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U) -#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U) -/*! FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC6 does not contribute to this shared set. - * 0b1..Data output from FC6 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U) -#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U) -/*! FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC7 does not contribute to this shared set. - * 0b1..Data output from FC7 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK) -/*! @} */ - -/* The count of SYSCTL_SHAREDCTRLSET */ -#define SYSCTL_SHAREDCTRLSET_COUNT (2U) - -/*! @name USB_HS_STATUS - Status register for USB HS */ -/*! @{ */ - -#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK (0x1U) -#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT (0U) -/*! USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply. - * 0b0..3v3 supply is good. - * 0b1..3v3 supply is too low. - */ -#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT)) & SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SYSCTL_Register_Masks */ - - -/* SYSCTL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE (0x50023000u) - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE_NS (0x40023000u) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL_NS ((SYSCTL_Type *)SYSCTL_BASE_NS) - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS { SYSCTL } - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS_NS { SYSCTL_BASE_NS } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS_NS { SYSCTL_NS } -#else - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE (0x40023000u) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS { SYSCTL } -#endif - -/*! - * @} - */ /* end of group SYSCTL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USART Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer - * @{ - */ - -/** USART - Register Layout Typedef */ -typedef struct { - __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ - __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ - __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ - uint8_t RESERVED_0[12]; - __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ - __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ - __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ - __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ - uint8_t RESERVED_1[3536]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_2[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_3[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_4[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_6[4]; - __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ - uint8_t RESERVED_7[432]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} USART_Type; - -/* ---------------------------------------------------------------------------- - -- USART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Register_Masks USART Register Masks - * @{ - */ - -/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ -/*! @{ */ - -#define USART_CFG_ENABLE_MASK (0x1U) -#define USART_CFG_ENABLE_SHIFT (0U) -/*! ENABLE - USART Enable. - * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, - * all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control - * bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the - * transmitter has been reset and is therefore available. - * 0b1..Enabled. The USART is enabled for operation. - */ -#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) - -#define USART_CFG_DATALEN_MASK (0xCU) -#define USART_CFG_DATALEN_SHIFT (2U) -/*! DATALEN - Selects the data size for the USART. - * 0b00..7 bit Data length. - * 0b01..8 bit Data length. - * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. - * 0b11..Reserved. - */ -#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) - -#define USART_CFG_PARITYSEL_MASK (0x30U) -#define USART_CFG_PARITYSEL_SHIFT (4U) -/*! PARITYSEL - Selects what type of parity is used by the USART. - * 0b00..No parity. - * 0b01..Reserved. - * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, - * and the number of 1s in a received character is expected to be even. - * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, - * and the number of 1s in a received character is expected to be odd. - */ -#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) - -#define USART_CFG_STOPLEN_MASK (0x40U) -#define USART_CFG_STOPLEN_SHIFT (6U) -/*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. - * 0b0..1 stop bit. - * 0b1..2 stop bits. This setting should only be used for asynchronous communication. - */ -#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) - -#define USART_CFG_MODE32K_MASK (0x80U) -#define USART_CFG_MODE32K_SHIFT (7U) -/*! MODE32K - Selects standard or 32 kHz clocking mode. - * 0b0..Disabled. USART uses standard clocking. - * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. - */ -#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) - -#define USART_CFG_LINMODE_MASK (0x100U) -#define USART_CFG_LINMODE_SHIFT (8U) -/*! LINMODE - LIN break mode enable. - * 0b0..Disabled. Break detect and generate is configured for normal operation. - * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. - */ -#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) - -#define USART_CFG_CTSEN_MASK (0x200U) -#define USART_CFG_CTSEN_SHIFT (9U) -/*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input - * pin, or from the USART's own RTS if loopback mode is enabled. - * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. - * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. - */ -#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) - -#define USART_CFG_SYNCEN_MASK (0x800U) -#define USART_CFG_SYNCEN_SHIFT (11U) -/*! SYNCEN - Selects synchronous or asynchronous operation. - * 0b0..Asynchronous mode. - * 0b1..Synchronous mode. - */ -#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) - -#define USART_CFG_CLKPOL_MASK (0x1000U) -#define USART_CFG_CLKPOL_SHIFT (12U) -/*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. - * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK. - * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. - */ -#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) - -#define USART_CFG_SYNCMST_MASK (0x4000U) -#define USART_CFG_SYNCMST_SHIFT (14U) -/*! SYNCMST - Synchronous mode Master select. - * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. - * 0b1..Master. When synchronous mode is enabled, the USART is a master. - */ -#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) - -#define USART_CFG_LOOP_MASK (0x8000U) -#define USART_CFG_LOOP_SHIFT (15U) -/*! LOOP - Selects data loopback mode. - * 0b0..Normal operation. - * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial - * data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD - * and Un_RTS activity will also appear on external pins if these functions are configured to appear on device - * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. - */ -#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) - -#define USART_CFG_OETA_MASK (0x40000U) -#define USART_CFG_OETA_SHIFT (18U) -/*! OETA - Output Enable Turnaround time enable for RS-485 operation. - * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. - * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the - * end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins - * before it is deasserted. - */ -#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) - -#define USART_CFG_AUTOADDR_MASK (0x80000U) -#define USART_CFG_AUTOADDR_SHIFT (19U) -/*! AUTOADDR - Automatic Address matching enable. - * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the - * possibility of versatile addressing (e.g. respond to more than one address). - * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in - * the ADDR register as the address to match. - */ -#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) - -#define USART_CFG_OESEL_MASK (0x100000U) -#define USART_CFG_OESEL_SHIFT (20U) -/*! OESEL - Output Enable Select. - * 0b0..Standard. The RTS signal is used as the standard flow control function. - * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. - */ -#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) - -#define USART_CFG_OEPOL_MASK (0x200000U) -#define USART_CFG_OEPOL_SHIFT (21U) -/*! OEPOL - Output Enable Polarity. - * 0b0..Low. If selected by OESEL, the output enable is active low. - * 0b1..High. If selected by OESEL, the output enable is active high. - */ -#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) - -#define USART_CFG_RXPOL_MASK (0x400000U) -#define USART_CFG_RXPOL_SHIFT (22U) -/*! RXPOL - Receive data polarity. - * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start - * bit is 0, data is not inverted, and the stop bit is 1. - * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is - * 0, start bit is 1, data is inverted, and the stop bit is 0. - */ -#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) - -#define USART_CFG_TXPOL_MASK (0x800000U) -#define USART_CFG_TXPOL_SHIFT (23U) -/*! TXPOL - Transmit data polarity. - * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is - * 0, data is not inverted, and the stop bit is 1. - * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value - * is 0, start bit is 1, data is inverted, and the stop bit is 0. - */ -#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) -/*! @} */ - -/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ -/*! @{ */ - -#define USART_CTL_TXBRKEN_MASK (0x2U) -#define USART_CTL_TXBRKEN_SHIFT (1U) -/*! TXBRKEN - Break Enable. - * 0b0..Normal operation. - * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit - * is cleared. A break may be sent without danger of corrupting any currently transmitting character if the - * transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled - * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. - */ -#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) - -#define USART_CTL_ADDRDET_MASK (0x4U) -#define USART_CTL_ADDRDET_SHIFT (2U) -/*! ADDRDET - Enable address detect mode. - * 0b0..Disabled. The USART presents all incoming data. - * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data - * (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, - * generating a received data interrupt. Software can then check the data to see if this is an address that - * should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled - * normally. - */ -#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) - -#define USART_CTL_TXDIS_MASK (0x40U) -#define USART_CTL_TXDIS_SHIFT (6U) -/*! TXDIS - Transmit Disable. - * 0b0..Not disabled. USART transmitter is not disabled. - * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This - * feature can be used to facilitate software flow control. - */ -#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) - -#define USART_CTL_CC_MASK (0x100U) -#define USART_CTL_CC_SHIFT (8U) -/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. - * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to - * complete a character that is being received. - * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on - * Un_RxD independently from transmission on Un_TXD). - */ -#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) - -#define USART_CTL_CLRCCONRX_MASK (0x200U) -#define USART_CTL_CLRCCONRX_SHIFT (9U) -/*! CLRCCONRX - Clear Continuous Clock. - * 0b0..No effect. No effect on the CC bit. - * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. - */ -#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) - -#define USART_CTL_AUTOBAUD_MASK (0x10000U) -#define USART_CTL_AUTOBAUD_SHIFT (16U) -/*! AUTOBAUD - Autobaud enable. - * 0b0..Disabled. USART is in normal operating mode. - * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The - * first start bit of RX is measured and used the update the BRG register to match the received data rate. - * AUTOBAUD is cleared once this process is complete, or if there is an AERR. - */ -#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) -/*! @} */ - -/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ -/*! @{ */ - -#define USART_STAT_RXIDLE_MASK (0x2U) -#define USART_STAT_RXIDLE_SHIFT (1U) -/*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of - * receiving data. When 1, indicates that the receiver is not currently in the process of receiving - * data. - */ -#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) - -#define USART_STAT_TXIDLE_MASK (0x8U) -#define USART_STAT_TXIDLE_SHIFT (3U) -/*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of - * sending data.When 1, indicate that the transmitter is not currently in the process of sending - * data. - */ -#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) - -#define USART_STAT_CTS_MASK (0x10U) -#define USART_STAT_CTS_SHIFT (4U) -/*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the - * CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode - * is enabled. - */ -#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) - -#define USART_STAT_DELTACTS_MASK (0x20U) -#define USART_STAT_DELTACTS_SHIFT (5U) -/*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. - */ -#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) - -#define USART_STAT_TXDISSTAT_MASK (0x40U) -#define USART_STAT_TXDISSTAT_SHIFT (6U) -/*! TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART - * transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). - */ -#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) - -#define USART_STAT_RXBRK_MASK (0x400U) -#define USART_STAT_RXBRK_SHIFT (10U) -/*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection - * logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also - * be set when this condition occurs because the stop bit(s) for the character would be missing. - * RXBRK is cleared when the Un_RXD pin goes high. - */ -#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) - -#define USART_STAT_DELTARXBRK_MASK (0x800U) -#define USART_STAT_DELTARXBRK_SHIFT (11U) -/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software. - */ -#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) - -#define USART_STAT_START_MASK (0x1000U) -#define USART_STAT_START_SHIFT (12U) -/*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily - * to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. - * Cleared by software. - */ -#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) - -#define USART_STAT_FRAMERRINT_MASK (0x2000U) -#define USART_STAT_FRAMERRINT_SHIFT (13U) -/*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a - * missing stop bit at the expected location. This could be an indication of a baud rate or - * configuration mismatch with the transmitting source. - */ -#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) - -#define USART_STAT_PARITYERRINT_MASK (0x4000U) -#define USART_STAT_PARITYERRINT_SHIFT (14U) -/*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. - */ -#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) - -#define USART_STAT_RXNOISEINT_MASK (0x8000U) -#define USART_STAT_RXNOISEINT_SHIFT (15U) -/*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to - * determine the value of each received data bit, except in synchronous mode. This acts as a - * noise filter if one sample disagrees. This flag is set when a received data bit contains one - * disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or - * loss of synchronization during data reception. - */ -#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) - -#define USART_STAT_ABERR_MASK (0x10000U) -#define USART_STAT_ABERR_SHIFT (16U) -/*! ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the - * end of the start bit that is being measured, essentially an auto baud time-out. - */ -#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -/*! @{ */ - -#define USART_INTENSET_TXIDLEEN_MASK (0x8U) -#define USART_INTENSET_TXIDLEEN_SHIFT (3U) -/*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). - */ -#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) - -#define USART_INTENSET_DELTACTSEN_MASK (0x20U) -#define USART_INTENSET_DELTACTSEN_SHIFT (5U) -/*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input. - */ -#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) - -#define USART_INTENSET_TXDISEN_MASK (0x40U) -#define USART_INTENSET_TXDISEN_SHIFT (6U) -/*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by - * the TXDISINT flag in STAT. See description of the TXDISINT bit for details. - */ -#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) - -#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) -#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) -/*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection - * of a received break condition (break condition asserted or deasserted). - */ -#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) - -#define USART_INTENSET_STARTEN_MASK (0x1000U) -#define USART_INTENSET_STARTEN_SHIFT (12U) -/*! STARTEN - When 1, enables an interrupt when a received start bit has been detected. - */ -#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) - -#define USART_INTENSET_FRAMERREN_MASK (0x2000U) -#define USART_INTENSET_FRAMERREN_SHIFT (13U) -/*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected. - */ -#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) - -#define USART_INTENSET_PARITYERREN_MASK (0x4000U) -#define USART_INTENSET_PARITYERREN_SHIFT (14U) -/*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected. - */ -#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) - -#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) -#define USART_INTENSET_RXNOISEEN_SHIFT (15U) -/*! RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. - */ -#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) - -#define USART_INTENSET_ABERREN_MASK (0x10000U) -#define USART_INTENSET_ABERREN_SHIFT (16U) -/*! ABERREN - When 1, enables an interrupt when an auto baud error occurs. - */ -#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ -/*! @{ */ - -#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) -#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) -/*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) - -#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) -#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) -/*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) - -#define USART_INTENCLR_TXDISCLR_MASK (0x40U) -#define USART_INTENCLR_TXDISCLR_SHIFT (6U) -/*! TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) - -#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) -#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) -/*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) - -#define USART_INTENCLR_STARTCLR_MASK (0x1000U) -#define USART_INTENCLR_STARTCLR_SHIFT (12U) -/*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) - -#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) -#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) -/*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) - -#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) -#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) -/*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) - -#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) -#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) -/*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) - -#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) -#define USART_INTENCLR_ABERRCLR_SHIFT (16U) -/*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) -/*! @} */ - -/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ -/*! @{ */ - -#define USART_BRG_BRGVAL_MASK (0xFFFFU) -#define USART_BRG_BRGVAL_SHIFT (0U) -/*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on - * the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is - * divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART - * function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. - */ -#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ -/*! @{ */ - -#define USART_INTSTAT_TXIDLE_MASK (0x8U) -#define USART_INTSTAT_TXIDLE_SHIFT (3U) -/*! TXIDLE - Transmitter Idle status. - */ -#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) - -#define USART_INTSTAT_DELTACTS_MASK (0x20U) -#define USART_INTSTAT_DELTACTS_SHIFT (5U) -/*! DELTACTS - This bit is set when a change in the state of the CTS input is detected. - */ -#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) - -#define USART_INTSTAT_TXDISINT_MASK (0x40U) -#define USART_INTSTAT_TXDISINT_SHIFT (6U) -/*! TXDISINT - Transmitter Disabled Interrupt flag. - */ -#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) - -#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) -#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) -/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. - */ -#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) - -#define USART_INTSTAT_START_MASK (0x1000U) -#define USART_INTSTAT_START_SHIFT (12U) -/*! START - This bit is set when a start is detected on the receiver input. - */ -#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) - -#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) -#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) -/*! FRAMERRINT - Framing Error interrupt flag. - */ -#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) - -#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) -#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) -/*! PARITYERRINT - Parity Error interrupt flag. - */ -#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) - -#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) -#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) -/*! RXNOISEINT - Received Noise interrupt flag. - */ -#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) - -#define USART_INTSTAT_ABERRINT_MASK (0x10000U) -#define USART_INTSTAT_ABERRINT_SHIFT (16U) -/*! ABERRINT - Auto baud Error Interrupt flag. - */ -#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) -/*! @} */ - -/*! @name OSR - Oversample selection register for asynchronous communication. */ -/*! @{ */ - -#define USART_OSR_OSRVAL_MASK (0xFU) -#define USART_OSR_OSRVAL_SHIFT (0U) -/*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to - * transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive - * each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. - */ -#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) -/*! @} */ - -/*! @name ADDR - Address register for automatic address matching. */ -/*! @{ */ - -#define USART_ADDR_ADDRESS_MASK (0xFFU) -#define USART_ADDR_ADDRESS_SHIFT (0U) -/*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is - * enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). - */ -#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ - -#define USART_FIFOCFG_ENABLETX_MASK (0x1U) -#define USART_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) - -#define USART_FIFOCFG_ENABLERX_MASK (0x2U) -#define USART_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) - -#define USART_FIFOCFG_SIZE_MASK (0x30U) -#define USART_FIFOCFG_SIZE_SHIFT (4U) -/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 - * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - */ -#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) - -#define USART_FIFOCFG_DMATX_MASK (0x1000U) -#define USART_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) - -#define USART_FIFOCFG_DMARX_MASK (0x2000U) -#define USART_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) - -#define USART_FIFOCFG_WAKETX_MASK (0x4000U) -#define USART_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in - * FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) - -#define USART_FIFOCFG_WAKERX_MASK (0x8000U) -#define USART_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in - * FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) - -#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) -/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - */ -#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) - -#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) -/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - */ -#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ - -#define USART_FIFOSTAT_TXERR_MASK (0x1U) -#define USART_FIFOSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow - * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is - * needed. Cleared by writing a 1 to this bit. - */ -#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) - -#define USART_FIFOSTAT_RXERR_MASK (0x2U) -#define USART_FIFOSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA - * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - */ -#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) - -#define USART_FIFOSTAT_PERINT_MASK (0x8U) -#define USART_FIFOSTAT_PERINT_SHIFT (3U) -/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted - * an interrupt. The details can be found by reading the peripheral's STAT register. - */ -#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) - -#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) -/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - */ -#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) - -#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) -/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be - * written. When 0, the transmit FIFO is full and another write would cause it to overflow. - */ -#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) - -#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - */ -#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) - -#define USART_FIFOSTAT_RXFULL_MASK (0x80U) -#define USART_FIFOSTAT_RXFULL_SHIFT (7U) -/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to - * prevent the peripheral from causing an overflow. - */ -#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) - -#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define USART_FIFOSTAT_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY - * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at - * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be - * 0. - */ -#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) - -#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define USART_FIFOSTAT_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and - * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the - * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be - * 1. - */ -#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ - -#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) - -#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) - -#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) -#define USART_FIFOTRIG_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled - * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to - * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO - * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX - * FIFO level decreases to 15 entries (is no longer full). - */ -#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) - -#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define USART_FIFOTRIG_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data - * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level - * can wake up the device just enough to perform DMA, then return to the reduced power mode. See - * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no - * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX - * FIFO has received 16 entries (has become full). - */ -#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ - -#define USART_FIFOINTENSET_TXERR_MASK (0x1U) -#define USART_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) - -#define USART_FIFOINTENSET_RXERR_MASK (0x2U) -#define USART_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) - -#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) -#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases - * to the level specified by TXLVL in the FIFOTRIG register. - */ -#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) - -#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) -#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level - * increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ - -#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) -#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) -/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) - -#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) -#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) -/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) - -#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) -/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) - -#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) -/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ - -#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) -#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. - */ -#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) - -#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) -#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. - */ -#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) - -#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO level interrupt. - */ -#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) - -#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO level interrupt. - */ -#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) - -#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) -#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) -/*! PERINT - Peripheral interrupt. - */ -#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ - -#define USART_FIFOWR_TXDATA_MASK (0x1FFU) -#define USART_FIFOWR_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit data to the FIFO. - */ -#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ - -#define USART_FIFORD_RXDATA_MASK (0x1FFU) -#define USART_FIFORD_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. - */ -#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) - -#define USART_FIFORD_FRAMERR_MASK (0x2000U) -#define USART_FIFORD_FRAMERR_SHIFT (13U) -/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along - * with from the FIFO, and indicates that the character was received with a missing stop bit at - * the expected location. This could be an indication of a baud rate or configuration mismatch - * with the transmitting source. - */ -#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) - -#define USART_FIFORD_PARITYERR_MASK (0x4000U) -#define USART_FIFORD_PARITYERR_SHIFT (14U) -/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along - * with from the FIFO. This bit will be set when a parity error is detected in a received - * character. - */ -#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) - -#define USART_FIFORD_RXNOISE_MASK (0x8000U) -#define USART_FIFORD_RXNOISE_SHIFT (15U) -/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. - */ -#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ - -#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) -#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. - */ -#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) - -#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) -#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) -/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along - * with from the FIFO, and indicates that the character was received with a missing stop bit at - * the expected location. This could be an indication of a baud rate or configuration mismatch - * with the transmitting source. - */ -#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) - -#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) -#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) -/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along - * with from the FIFO. This bit will be set when a parity error is detected in a received - * character. - */ -#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) - -#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) -#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) -/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. - */ -#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) -/*! @} */ - -/*! @name FIFOSIZE - FIFO size register */ -/*! @{ */ - -#define USART_FIFOSIZE_FIFOSIZE_MASK (0x1FU) -#define USART_FIFOSIZE_FIFOSIZE_SHIFT (0U) -/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - */ -#define USART_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSIZE_FIFOSIZE_SHIFT)) & USART_FIFOSIZE_FIFOSIZE_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ - -#define USART_ID_APERTURE_MASK (0xFFU) -#define USART_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - */ -#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) - -#define USART_ID_MINOR_REV_MASK (0xF00U) -#define USART_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation. - */ -#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) - -#define USART_ID_MAJOR_REV_MASK (0xF000U) -#define USART_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation. - */ -#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) - -#define USART_ID_ID_MASK (0xFFFF0000U) -#define USART_ID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function. - */ -#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USART_Register_Masks */ - - -/* USART - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USART0 base address */ - #define USART0_BASE (0x50086000u) - /** Peripheral USART0 base address */ - #define USART0_BASE_NS (0x40086000u) - /** Peripheral USART0 base pointer */ - #define USART0 ((USART_Type *)USART0_BASE) - /** Peripheral USART0 base pointer */ - #define USART0_NS ((USART_Type *)USART0_BASE_NS) - /** Peripheral USART1 base address */ - #define USART1_BASE (0x50087000u) - /** Peripheral USART1 base address */ - #define USART1_BASE_NS (0x40087000u) - /** Peripheral USART1 base pointer */ - #define USART1 ((USART_Type *)USART1_BASE) - /** Peripheral USART1 base pointer */ - #define USART1_NS ((USART_Type *)USART1_BASE_NS) - /** Peripheral USART2 base address */ - #define USART2_BASE (0x50088000u) - /** Peripheral USART2 base address */ - #define USART2_BASE_NS (0x40088000u) - /** Peripheral USART2 base pointer */ - #define USART2 ((USART_Type *)USART2_BASE) - /** Peripheral USART2 base pointer */ - #define USART2_NS ((USART_Type *)USART2_BASE_NS) - /** Peripheral USART3 base address */ - #define USART3_BASE (0x50089000u) - /** Peripheral USART3 base address */ - #define USART3_BASE_NS (0x40089000u) - /** Peripheral USART3 base pointer */ - #define USART3 ((USART_Type *)USART3_BASE) - /** Peripheral USART3 base pointer */ - #define USART3_NS ((USART_Type *)USART3_BASE_NS) - /** Peripheral USART4 base address */ - #define USART4_BASE (0x5008A000u) - /** Peripheral USART4 base address */ - #define USART4_BASE_NS (0x4008A000u) - /** Peripheral USART4 base pointer */ - #define USART4 ((USART_Type *)USART4_BASE) - /** Peripheral USART4 base pointer */ - #define USART4_NS ((USART_Type *)USART4_BASE_NS) - /** Peripheral USART5 base address */ - #define USART5_BASE (0x50096000u) - /** Peripheral USART5 base address */ - #define USART5_BASE_NS (0x40096000u) - /** Peripheral USART5 base pointer */ - #define USART5 ((USART_Type *)USART5_BASE) - /** Peripheral USART5 base pointer */ - #define USART5_NS ((USART_Type *)USART5_BASE_NS) - /** Peripheral USART6 base address */ - #define USART6_BASE (0x50097000u) - /** Peripheral USART6 base address */ - #define USART6_BASE_NS (0x40097000u) - /** Peripheral USART6 base pointer */ - #define USART6 ((USART_Type *)USART6_BASE) - /** Peripheral USART6 base pointer */ - #define USART6_NS ((USART_Type *)USART6_BASE_NS) - /** Peripheral USART7 base address */ - #define USART7_BASE (0x50098000u) - /** Peripheral USART7 base address */ - #define USART7_BASE_NS (0x40098000u) - /** Peripheral USART7 base pointer */ - #define USART7 ((USART_Type *)USART7_BASE) - /** Peripheral USART7 base pointer */ - #define USART7_NS ((USART_Type *)USART7_BASE_NS) - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS_NS { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS_NS { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS } -#else - /** Peripheral USART0 base address */ - #define USART0_BASE (0x40086000u) - /** Peripheral USART0 base pointer */ - #define USART0 ((USART_Type *)USART0_BASE) - /** Peripheral USART1 base address */ - #define USART1_BASE (0x40087000u) - /** Peripheral USART1 base pointer */ - #define USART1 ((USART_Type *)USART1_BASE) - /** Peripheral USART2 base address */ - #define USART2_BASE (0x40088000u) - /** Peripheral USART2 base pointer */ - #define USART2 ((USART_Type *)USART2_BASE) - /** Peripheral USART3 base address */ - #define USART3_BASE (0x40089000u) - /** Peripheral USART3 base pointer */ - #define USART3 ((USART_Type *)USART3_BASE) - /** Peripheral USART4 base address */ - #define USART4_BASE (0x4008A000u) - /** Peripheral USART4 base pointer */ - #define USART4 ((USART_Type *)USART4_BASE) - /** Peripheral USART5 base address */ - #define USART5_BASE (0x40096000u) - /** Peripheral USART5 base pointer */ - #define USART5 ((USART_Type *)USART5_BASE) - /** Peripheral USART6 base address */ - #define USART6_BASE (0x40097000u) - /** Peripheral USART6 base pointer */ - #define USART6 ((USART_Type *)USART6_BASE) - /** Peripheral USART7 base address */ - #define USART7_BASE (0x40098000u) - /** Peripheral USART7 base pointer */ - #define USART7 ((USART_Type *)USART7_BASE) - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } -#endif -/** Interrupt vectors for the USART peripheral type */ -#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group USART_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer - * @{ - */ - -/** USB - Register Layout Typedef */ -typedef struct { - __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ - __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ - __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ - __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ - __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ - __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ - __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ - __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ - __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ - __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ - __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ - uint8_t RESERVED_0[8]; - __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ -} USB_Type; - -/* ---------------------------------------------------------------------------- - -- USB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Register_Masks USB Register Masks - * @{ - */ - -/*! @name DEVCMDSTAT - USB Device Command/Status register */ -/*! @{ */ - -#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) -#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) -/*! DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit - * is set, the device will respond on packets for function address DEV_ADDR. When receiving a - * SetAddress Control Request from the USB host, software must program the new address before - * completing the status phase of the SetAddress Control Request. - */ -#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) - -#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) -#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) -/*! DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. - */ -#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) - -#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) -#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) -/*! SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this - * bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW - * must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the - * CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. - */ -#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) - -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) -/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: - * 0b0..USB_NEEDCLK has normal function. - * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. - */ -#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) - -#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) -#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) -/*! LPM_SUP - LPM Supported: - * 0b0..LPM not supported. - * 0b1..LPM supported. - */ -#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) - -#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) -#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) -/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) - -#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) -#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) -/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) - -#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) -#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) -/*! INTONNAK_CO - Interrupt on NAK for control OUT EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) - -#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) -#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) -/*! INTONNAK_CI - Interrupt on NAK for control IN EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) - -#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) -#define USB_DEVCMDSTAT_DCON_SHIFT (16U) -/*! DCON - Device status - connect. The connect bit must be set by SW to indicate that the device - * must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and - * the VBUSDEBOUNCED bit is one. - */ -#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) - -#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) -#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) -/*! DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set - * to 1 when the device hasn't seen any activity on its upstream port for more than 3 - * milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and - * the software writes a 0 to it, the device will generate a remote wake-up. This will only happen - * when the device is connected (Connect bit = 1). When the device is not connected or not - * suspended, a writing a 0 has no effect. Writing a 1 never has an effect. - */ -#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) - -#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) -#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) -/*! LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is - * set to 1 by HW when the device has acknowledged the LPM request from the USB host and the - * Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend - * bit = 1) and the software writes a zero to this bit, the device will generate a remote - * walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this - * bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the - * LPM_SUPP bit is equal to one. - */ -#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) - -#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) -#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) -/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake - * bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the - * host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset - * is received. Software can use this bit to check if the remote wake-up feature is enabled by the - * host for the LPM transaction. - */ -#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) - -#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) -#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) -/*! DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up - * resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. - */ -#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) - -#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) -#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) -/*! DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit - * toggles. The suspend bit can toggle because: - The device goes in the suspended state - The - * device is disconnected - The device receives resume signaling on its upstream port. The bit is - * reset by writing a one to it. - */ -#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) - -#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) -#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) -/*! DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On - * a bus reset the device will automatically go to the default state (unconfigured and responding - * to address 0). The bit is reset by writing a one to it. - */ -#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) - -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) -/*! VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when - * Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and - * the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. - */ -#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) -/*! @} */ - -/*! @name INFO - USB Info register */ -/*! @{ */ - -#define USB_INFO_FRAME_NR_MASK (0x7FFU) -#define USB_INFO_FRAME_NR_SHIFT (0U) -/*! FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF. - * In case no SOF was received by the device at the beginning of a frame, the frame number - * returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC - * error, the frame number returned will be the corrupted frame number as received by the device. - */ -#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) - -#define USB_INFO_ERR_CODE_MASK (0x7800U) -#define USB_INFO_ERR_CODE_SHIFT (11U) -/*! ERR_CODE - The error code which last occurred: - * 0b0000..No error - * 0b0001..PID encoding error - * 0b0010..PID unknown - * 0b0011..Packet unexpected - * 0b0100..Token CRC error - * 0b0101..Data CRC error - * 0b0110..Time out - * 0b0111..Babble - * 0b1000..Truncated EOP - * 0b1001..Sent/Received NAK - * 0b1010..Sent Stall - * 0b1011..Overrun - * 0b1100..Sent empty packet - * 0b1101..Bitstuff error - * 0b1110..Sync error - * 0b1111..Wrong data toggle - */ -#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) - -#define USB_INFO_MINREV_MASK (0xFF0000U) -#define USB_INFO_MINREV_SHIFT (16U) -/*! MINREV - Minor Revision. - */ -#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK) - -#define USB_INFO_MAJREV_MASK (0xFF000000U) -#define USB_INFO_MAJREV_SHIFT (24U) -/*! MAJREV - Major Revision. - */ -#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK) -/*! @} */ - -/*! @name EPLISTSTART - USB EP Command/Status List start address */ -/*! @{ */ - -#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) -#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) -/*! EP_LIST - Start address of the USB EP Command/Status List. - */ -#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) -/*! @} */ - -/*! @name DATABUFSTART - USB Data buffer start address */ -/*! @{ */ - -#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) -#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) -/*! DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located. - */ -#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) -/*! @} */ - -/*! @name LPM - USB Link Power Management register */ -/*! @{ */ - -#define USB_LPM_HIRD_HW_MASK (0xFU) -#define USB_LPM_HIRD_HW_SHIFT (0U) -/*! HIRD_HW - Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token - */ -#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) - -#define USB_LPM_HIRD_SW_MASK (0xF0U) -#define USB_LPM_HIRD_SW_SHIFT (4U) -/*! HIRD_SW - Host Initiated Resume Duration - SW. This is the time duration required by the USB - * device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. - */ -#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) - -#define USB_LPM_DATA_PENDING_MASK (0x100U) -#define USB_LPM_DATA_PENDING_SHIFT (8U) -/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will - * return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and - * this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has - * still data pending and LPM is supported, it must set this bit to 1. - */ -#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) -/*! @} */ - -/*! @name EPSKIP - USB Endpoint skip */ -/*! @{ */ - -#define USB_EPSKIP_SKIP_MASK (0x3FFU) -#define USB_EPSKIP_SKIP_SHIFT (0U) -/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must - * deactivate the buffer assigned to this endpoint and return control back to software. When HW has - * deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An - * interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, - * HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. - */ -#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) -/*! @} */ - -/*! @name EPINUSE - USB Endpoint Buffer in use */ -/*! @{ */ - -#define USB_EPINUSE_BUF_MASK (0x3FCU) -#define USB_EPINUSE_BUF_SHIFT (2U) -/*! BUF - Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer - * 0. 1: HW is accessing buffer 1. - */ -#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) -/*! @} */ - -/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ -/*! @{ */ - -#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) -#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) -/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: - * Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding - * EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle - * the EPINUSE bit when it clears the Active bit for the buffer. - */ -#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) -/*! @} */ - -/*! @name INTSTAT - USB interrupt status register */ -/*! @{ */ - -#define USB_INTSTAT_EP0OUT_MASK (0x1U) -#define USB_INTSTAT_EP0OUT_SHIFT (0U) -/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set - * if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is - * successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a - * NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a - * one to it. - */ -#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) - -#define USB_INTSTAT_EP0IN_MASK (0x2U) -#define USB_INTSTAT_EP0IN_SHIFT (1U) -/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if - * NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this - * bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can - * clear this bit by writing a one to it. - */ -#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) - -#define USB_INTSTAT_EP1OUT_MASK (0x4U) -#define USB_INTSTAT_EP1OUT_SHIFT (2U) -/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes - * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be - * set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by - * writing a one to it. - */ -#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) - -#define USB_INTSTAT_EP1IN_MASK (0x8U) -#define USB_INTSTAT_EP1IN_SHIFT (3U) -/*! EP1IN - Interrupt status register bit for the EP1 IN direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions - * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be - * set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing - * a one to it. - */ -#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) - -#define USB_INTSTAT_EP2OUT_MASK (0x10U) -#define USB_INTSTAT_EP2OUT_SHIFT (4U) -/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes - * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be - * set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by - * writing a one to it. - */ -#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) - -#define USB_INTSTAT_EP2IN_MASK (0x20U) -#define USB_INTSTAT_EP2IN_SHIFT (5U) -/*! EP2IN - Interrupt status register bit for the EP2 IN direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions - * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be - * set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing - * a one to it. - */ -#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) - -#define USB_INTSTAT_EP3OUT_MASK (0x40U) -#define USB_INTSTAT_EP3OUT_SHIFT (6U) -/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes - * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be - * set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by - * writing a one to it. - */ -#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) - -#define USB_INTSTAT_EP3IN_MASK (0x80U) -#define USB_INTSTAT_EP3IN_SHIFT (7U) -/*! EP3IN - Interrupt status register bit for the EP3 IN direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions - * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be - * set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing - * a one to it. - */ -#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) - -#define USB_INTSTAT_EP4OUT_MASK (0x100U) -#define USB_INTSTAT_EP4OUT_SHIFT (8U) -/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes - * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be - * set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by - * writing a one to it. - */ -#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) - -#define USB_INTSTAT_EP4IN_MASK (0x200U) -#define USB_INTSTAT_EP4IN_SHIFT (9U) -/*! EP4IN - Interrupt status register bit for the EP4 IN direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions - * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be - * set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing - * a one to it. - */ -#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) - -#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) -#define USB_INTSTAT_FRAME_INT_SHIFT (30U) -/*! FRAME_INT - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit - * and the DCON bit are set. This bit can be used by software when handling isochronous - * endpoints. Software can clear this bit by writing a one to it. - */ -#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) - -#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) -#define USB_INTSTAT_DEV_INT_SHIFT (31U) -/*! DEV_INT - Device status interrupt. This bit is set by HW when one of the bits in the Device - * Status Change register are set. Software can clear this bit by writing a one to it. - */ -#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) -/*! @} */ - -/*! @name INTEN - USB interrupt enable register */ -/*! @{ */ - -#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) -#define USB_INTEN_EP_INT_EN_SHIFT (0U) -/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing - * bit. - */ -#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) - -#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) -#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) -/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt - * routing bit. - */ -#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) - -#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) -#define USB_INTEN_DEV_INT_EN_SHIFT (31U) -/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing - * bit. - */ -#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) -/*! @} */ - -/*! @name INTSETSTAT - USB set interrupt status register */ -/*! @{ */ - -#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) -#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) -/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt - * status bit is set. When this register is read, the same value as the USB interrupt status register - * is returned. - */ -#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) - -#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) -#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) -/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt - * status bit is set. When this register is read, the same value as the USB interrupt status - * register is returned. - */ -#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) - -#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) -#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) -/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt - * status bit is set. When this register is read, the same value as the USB interrupt status - * register is returned. - */ -#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) -/*! @} */ - -/*! @name EPTOGGLE - USB Endpoint toggle register */ -/*! @{ */ - -#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) -#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) -/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. - */ -#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USB_Register_Masks */ - - -/* USB - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USB0 base address */ - #define USB0_BASE (0x50084000u) - /** Peripheral USB0 base address */ - #define USB0_BASE_NS (0x40084000u) - /** Peripheral USB0 base pointer */ - #define USB0 ((USB_Type *)USB0_BASE) - /** Peripheral USB0 base pointer */ - #define USB0_NS ((USB_Type *)USB0_BASE_NS) - /** Array initializer of USB peripheral base addresses */ - #define USB_BASE_ADDRS { USB0_BASE } - /** Array initializer of USB peripheral base pointers */ - #define USB_BASE_PTRS { USB0 } - /** Array initializer of USB peripheral base addresses */ - #define USB_BASE_ADDRS_NS { USB0_BASE_NS } - /** Array initializer of USB peripheral base pointers */ - #define USB_BASE_PTRS_NS { USB0_NS } -#else - /** Peripheral USB0 base address */ - #define USB0_BASE (0x40084000u) - /** Peripheral USB0 base pointer */ - #define USB0 ((USB_Type *)USB0_BASE) - /** Array initializer of USB peripheral base addresses */ - #define USB_BASE_ADDRS { USB0_BASE } - /** Array initializer of USB peripheral base pointers */ - #define USB_BASE_PTRS { USB0 } -#endif -/** Interrupt vectors for the USB peripheral type */ -#define USB_IRQS { USB0_IRQn } -#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBFSH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer - * @{ - */ - -/** USBFSH - Register Layout Typedef */ -typedef struct { - __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */ - __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */ - __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */ - __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */ - __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */ - __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */ - __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */ - __I uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */ - __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */ - __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */ - __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */ - __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */ - __I uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */ - __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */ - __I uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */ - __I uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */ - __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */ - __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */ - __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */ - __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */ - __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */ - __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */ - uint8_t RESERVED_0[4]; - __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */ -} USBFSH_Type; - -/* ---------------------------------------------------------------------------- - -- USBFSH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBFSH_Register_Masks USBFSH Register Masks - * @{ - */ - -/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */ -/*! @{ */ - -#define USBFSH_HCREVISION_REV_MASK (0xFFU) -#define USBFSH_HCREVISION_REV_SHIFT (0U) -/*! REV - Revision. - */ -#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK) -/*! @} */ - -/*! @name HCCONTROL - Defines the operating modes of the HC */ -/*! @{ */ - -#define USBFSH_HCCONTROL_CBSR_MASK (0x3U) -#define USBFSH_HCCONTROL_CBSR_SHIFT (0U) -/*! CBSR - ControlBulkServiceRatio. - */ -#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK) - -#define USBFSH_HCCONTROL_PLE_MASK (0x4U) -#define USBFSH_HCCONTROL_PLE_SHIFT (2U) -/*! PLE - PeriodicListEnable. - */ -#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK) - -#define USBFSH_HCCONTROL_IE_MASK (0x8U) -#define USBFSH_HCCONTROL_IE_SHIFT (3U) -/*! IE - IsochronousEnable. - */ -#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK) - -#define USBFSH_HCCONTROL_CLE_MASK (0x10U) -#define USBFSH_HCCONTROL_CLE_SHIFT (4U) -/*! CLE - ControlListEnable. - */ -#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK) - -#define USBFSH_HCCONTROL_BLE_MASK (0x20U) -#define USBFSH_HCCONTROL_BLE_SHIFT (5U) -/*! BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. - */ -#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK) - -#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U) -#define USBFSH_HCCONTROL_HCFS_SHIFT (6U) -/*! HCFS - HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL - * 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin - * 1 ms later. - */ -#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK) - -#define USBFSH_HCCONTROL_IR_MASK (0x100U) -#define USBFSH_HCCONTROL_IR_SHIFT (8U) -/*! IR - InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. - */ -#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK) - -#define USBFSH_HCCONTROL_RWC_MASK (0x200U) -#define USBFSH_HCCONTROL_RWC_SHIFT (9U) -/*! RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling. - */ -#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK) - -#define USBFSH_HCCONTROL_RWE_MASK (0x400U) -#define USBFSH_HCCONTROL_RWE_SHIFT (10U) -/*! RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature - * upon the detection of upstream resume signaling. - */ -#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK) -/*! @} */ - -/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */ -/*! @{ */ - -#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U) -#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U) -/*! HCR - HostControllerReset This bit is set by HCD to initiate a software reset of HC. - */ -#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK) - -#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U) -#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U) -/*! CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. - */ -#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK) - -#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U) -#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U) -/*! BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. - */ -#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK) - -#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U) -#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U) -/*! OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC. - */ -#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK) - -#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U) -#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U) -/*! SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error. - */ -#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK) -/*! @} */ - -/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */ -/*! @{ */ - -#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U) -/*! SO - SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and - * after the update of HccaFrameNumber. - */ -#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U) -/*! WDH - WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead. - */ -#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U) -/*! SF - StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. - */ -#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U) -/*! RD - ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling. - */ -#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U) -/*! UE - UnrecoverableError This bit is set when HC detects a system error not related to USB. - */ -#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U) -/*! FNO - FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value, - * from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated. - */ -#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U) -/*! RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any - * of HcRhPortStatus[NumberofDownstreamPort] has changed. - */ -#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U) -#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U) -/*! OC - OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus. - */ -#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK) -/*! @} */ - -/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */ -/*! @{ */ - -#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U) -/*! SO - Scheduling Overrun interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK) - -#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U) -/*! WDH - HcDoneHead Writeback interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK) - -#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U) -/*! SF - Start of Frame interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK) - -#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U) -/*! RD - Resume Detect interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK) - -#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U) -/*! UE - Unrecoverable Error interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK) - -#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U) -/*! FNO - Frame Number Overflow interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK) - -#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U) -/*! RHSC - Root Hub Status Change interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK) - -#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U) -#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U) -/*! OC - Ownership Change interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK) - -#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U) -#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U) -/*! MIE - Master Interrupt Enable. - */ -#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK) -/*! @} */ - -/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */ -/*! @{ */ - -#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U) -/*! SO - Scheduling Overrun interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U) -/*! WDH - HcDoneHead Writeback interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U) -/*! SF - Start of Frame interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U) -/*! RD - Resume Detect interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U) -/*! UE - Unrecoverable Error interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U) -/*! FNO - Frame Number Overflow interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U) -/*! RHSC - Root Hub Status Change interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U) -#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U) -/*! OC - Ownership Change interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U) -#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U) -/*! MIE - A 0 written to this field is ignored by HC. - */ -#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK) -/*! @} */ - -/*! @name HCHCCA - Contains the physical address of the host controller communication area */ -/*! @{ */ - -#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U) -#define USBFSH_HCHCCA_HCCA_SHIFT (8U) -/*! HCCA - Base address of the Host Controller Communication Area. - */ -#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK) -/*! @} */ - -/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */ -/*! @{ */ - -#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U) -/*! PCED - The content of this register is updated by HC after a periodic ED is processed. - */ -#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK) -/*! @} */ - -/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */ -/*! @{ */ - -#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U) -#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U) -/*! CHED - HC traverses the Control list starting with the HcControlHeadED pointer. - */ -#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK) -/*! @} */ - -/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */ -/*! @{ */ - -#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U) -/*! CCED - ControlCurrentED. - */ -#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK) -/*! @} */ - -/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */ -/*! @{ */ - -#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U) -#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U) -/*! BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer. - */ -#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK) -/*! @} */ - -/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */ -/*! @{ */ - -#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U) -/*! BCED - BulkCurrentED This is advanced to the next ED after the HC has served the current one. - */ -#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK) -/*! @} */ - -/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */ -/*! @{ */ - -#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U) -#define USBFSH_HCDONEHEAD_DH_SHIFT (4U) -/*! DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. - */ -#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK) -/*! @} */ - -/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */ -/*! @{ */ - -#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU) -#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U) -/*! FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times. - */ -#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK) - -#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U) -#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U) -/*! FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data - * Packet Counter at the beginning of each frame. - */ -#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK) - -#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U) -#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U) -/*! FIT - FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval. - */ -#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK) -/*! @} */ - -/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */ -/*! @{ */ - -#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU) -#define USBFSH_HCFMREMAINING_FR_SHIFT (0U) -/*! FR - FrameRemaining This counter is decremented at each bit time. - */ -#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK) - -#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U) -#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U) -/*! FRT - FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval - * whenever FrameRemaining reaches 0. - */ -#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK) -/*! @} */ - -/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */ -/*! @{ */ - -#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU) -#define USBFSH_HCFMNUMBER_FN_SHIFT (0U) -/*! FN - FrameNumber This is incremented when HcFmRemaining is re-loaded. - */ -#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK) -/*! @} */ - -/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */ -/*! @{ */ - -#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU) -#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U) -/*! PS - PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization. - */ -#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK) -/*! @} */ - -/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */ -/*! @{ */ - -#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU) -#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U) -/*! LST - LSThreshold This field contains a value which is compared to the FrameRemaining field - * prior to initiating a Low Speed transaction. - */ -#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK) -/*! @} */ - -/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */ -/*! @{ */ - -#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU) -#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U) -/*! NDP - NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub. - */ -#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK) - -#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U) -#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U) -/*! PSM - PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled. - */ -#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK) - -#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U) -#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U) -/*! NPS - NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered. - */ -#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK) - -#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U) -#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U) -/*! DT - DeviceType This bit specifies that the root hub is not a compound device. - */ -#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK) - -#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U) -#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U) -/*! OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported. - */ -#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK) - -#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U) -#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U) -/*! NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported. - */ -#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK) - -#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U) -#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U) -/*! POTPGT - PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before - * accessing a powered-on port of the root hub. - */ -#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK) -/*! @} */ - -/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */ -/*! @{ */ - -#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU) -#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U) -/*! DR - DeviceRemovable Each bit is dedicated to a port of the Root Hub. - */ -#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK) - -#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U) -#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U) -/*! PPCM - PortPowerControlMask Each bit indicates if a port is affected by a global power control - * command when PowerSwitchingMode is set. - */ -#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK) -/*! @} */ - -/*! @name HCRHSTATUS - This register is divided into two parts */ -/*! @{ */ - -#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U) -#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U) -/*! LPS - (read) LocalPowerStatus The Root Hub does not support the local power status feature; - * thus, this bit is always read as 0. - */ -#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK) - -#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U) -#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U) -/*! OCI - OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented. - */ -#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK) - -#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U) -#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U) -/*! DRWE - (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume - * event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected - * interrupt. - */ -#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK) - -#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U) -#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U) -/*! LPSC - (read) LocalPowerStatusChange The root hub does not support the local power status feature. - */ -#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK) - -#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U) -#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U) -/*! OCIC - OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register. - */ -#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK) - -#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U) -#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U) -/*! CRWE - (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable. - */ -#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK) -/*! @} */ - -/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */ -/*! @{ */ - -#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U) -#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U) -/*! CCS - (read) CurrentConnectStatus This bit reflects the current state of the downstream port. - */ -#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK) - -#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U) -#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U) -/*! PES - (read) PortEnableStatus This bit indicates whether the port is enabled or disabled. - */ -#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK) - -#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U) -#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U) -/*! PSS - (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence. - */ -#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK) - -#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U) -#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U) -/*! POCI - (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in - * such a way that overcurrent conditions are reported on a per-port basis. - */ -#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK) - -#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U) -#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U) -/*! PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. - */ -#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK) - -#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U) -#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U) -/*! PPS - (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type - * of power switching implemented. - */ -#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK) - -#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U) -#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U) -/*! LSDA - (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. - */ -#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK) - -#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U) -#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U) -/*! CSC - ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. - */ -#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK) - -#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U) -#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U) -/*! PESC - PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared. - */ -#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK) - -#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U) -#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U) -/*! PSSC - PortSuspendStatusChange This bit is set when the full resume sequence is completed. - */ -#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK) - -#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U) -#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U) -/*! OCIC - PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis. - */ -#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK) - -#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U) -#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U) -/*! PRSC - PortResetStatusChange This bit is set at the end of the 10 ms port reset signal. - */ -#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK) -/*! @} */ - -/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ -/*! @{ */ - -#define USBFSH_PORTMODE_ID_MASK (0x1U) -#define USBFSH_PORTMODE_ID_SHIFT (0U) -/*! ID - Port ID pin value. - */ -#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK) - -#define USBFSH_PORTMODE_ID_EN_MASK (0x100U) -#define USBFSH_PORTMODE_ID_EN_SHIFT (8U) -/*! ID_EN - Port ID pin pull-up enable. - */ -#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK) - -#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) -#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U) -/*! DEV_ENABLE - 1: device 0: host. - */ -#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBFSH_Register_Masks */ - - -/* USBFSH - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USBFSH base address */ - #define USBFSH_BASE (0x500A2000u) - /** Peripheral USBFSH base address */ - #define USBFSH_BASE_NS (0x400A2000u) - /** Peripheral USBFSH base pointer */ - #define USBFSH ((USBFSH_Type *)USBFSH_BASE) - /** Peripheral USBFSH base pointer */ - #define USBFSH_NS ((USBFSH_Type *)USBFSH_BASE_NS) - /** Array initializer of USBFSH peripheral base addresses */ - #define USBFSH_BASE_ADDRS { USBFSH_BASE } - /** Array initializer of USBFSH peripheral base pointers */ - #define USBFSH_BASE_PTRS { USBFSH } - /** Array initializer of USBFSH peripheral base addresses */ - #define USBFSH_BASE_ADDRS_NS { USBFSH_BASE_NS } - /** Array initializer of USBFSH peripheral base pointers */ - #define USBFSH_BASE_PTRS_NS { USBFSH_NS } -#else - /** Peripheral USBFSH base address */ - #define USBFSH_BASE (0x400A2000u) - /** Peripheral USBFSH base pointer */ - #define USBFSH ((USBFSH_Type *)USBFSH_BASE) - /** Array initializer of USBFSH peripheral base addresses */ - #define USBFSH_BASE_ADDRS { USBFSH_BASE } - /** Array initializer of USBFSH peripheral base pointers */ - #define USBFSH_BASE_PTRS { USBFSH } -#endif -/** Interrupt vectors for the USBFSH peripheral type */ -#define USBFSH_IRQS { USB0_IRQn } -#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBFSH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBHSD Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer - * @{ - */ - -/** USBHSD - Register Layout Typedef */ -typedef struct { - __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ - __I uint32_t INFO; /**< USB Info register, offset: 0x4 */ - __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ - __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ - __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ - __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ - __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ - __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ - __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ - __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ - __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ - uint8_t RESERVED_0[8]; - __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ -} USBHSD_Type; - -/* ---------------------------------------------------------------------------- - -- USBHSD Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSD_Register_Masks USBHSD Register Masks - * @{ - */ - -/*! @name DEVCMDSTAT - USB Device Command/Status register */ -/*! @{ */ - -#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) -#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) -/*! DEV_ADDR - USB device address. - */ -#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK) - -#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U) -#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U) -/*! DEV_EN - USB device enable. - */ -#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK) - -#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U) -#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U) -/*! SETUP - SETUP token received. - */ -#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK) - -#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) -#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) -/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:. - */ -#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK) - -#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U) -#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U) -/*! LPM_SUP - LPM Supported:. - */ -#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK) - -#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) -/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP:. - */ -#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK) - -#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) -/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP:. - */ -#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK) - -#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) -/*! INTONNAK_CO - Interrupt on NAK for control OUT EP:. - */ -#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK) - -#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) -/*! INTONNAK_CI - Interrupt on NAK for control IN EP:. - */ -#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK) - -#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U) -#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U) -/*! DCON - Device status - connect. - */ -#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK) - -#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U) -#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U) -/*! DSUS - Device status - suspend. - */ -#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK) - -#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) -#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U) -/*! LPM_SUS - Device status - LPM Suspend. - */ -#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK) - -#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) -#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U) -/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. - */ -#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK) - -#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U) -#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U) -/*! Speed - This field indicates the speed at which the device operates: 00b: reserved 01b: - * full-speed 10b: high-speed 11b: super-speed (reserved for future use). - */ -#define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK) - -#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U) -#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U) -/*! DCON_C - Device status - connect change. - */ -#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK) - -#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) -#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U) -/*! DSUS_C - Device status - suspend change. - */ -#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK) - -#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U) -#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U) -/*! DRES_C - Device status - reset change. - */ -#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK) - -#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U) -#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U) -/*! VBUS_DEBOUNCED - This bit indicates if VBUS is detected or not. - */ -#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK) - -#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U) -#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U) -/*! PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification. - * 0b000..Test mode disabled. - * 0b001..Test_J. - * 0b010..Test_K. - * 0b011..Test_SE0_NAK. - * 0b100..Test_Packet. - * 0b101..Test_Force_Enable. - */ -#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK) -/*! @} */ - -/*! @name INFO - USB Info register */ -/*! @{ */ - -#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU) -#define USBHSD_INFO_FRAME_NR_SHIFT (0U) -/*! FRAME_NR - Frame number. - */ -#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK) - -#define USBHSD_INFO_ERR_CODE_MASK (0x7800U) -#define USBHSD_INFO_ERR_CODE_SHIFT (11U) -/*! ERR_CODE - The error code which last occurred:. - */ -#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK) - -#define USBHSD_INFO_MINREV_MASK (0xFF0000U) -#define USBHSD_INFO_MINREV_SHIFT (16U) -/*! MINREV - Minor revision. - */ -#define USBHSD_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MINREV_SHIFT)) & USBHSD_INFO_MINREV_MASK) - -#define USBHSD_INFO_MAJREV_MASK (0xFF000000U) -#define USBHSD_INFO_MAJREV_SHIFT (24U) -/*! MAJREV - Major revision. - */ -#define USBHSD_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MAJREV_SHIFT)) & USBHSD_INFO_MAJREV_MASK) -/*! @} */ - -/*! @name EPLISTSTART - USB EP Command/Status List start address */ -/*! @{ */ - -#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U) -#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U) -/*! EP_LIST_PRG - Programmable portion of the USB EP Command/Status List address. - */ -#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK) - -#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U) -#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U) -/*! EP_LIST_FIXED - Fixed portion of USB EP Command/Status List address. - */ -#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK) -/*! @} */ - -/*! @name DATABUFSTART - USB Data buffer start address */ -/*! @{ */ - -#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU) -#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U) -/*! DA_BUF - Start address of the memory page where all endpoint data buffers are located. - */ -#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK) -/*! @} */ - -/*! @name LPM - USB Link Power Management register */ -/*! @{ */ - -#define USBHSD_LPM_HIRD_HW_MASK (0xFU) -#define USBHSD_LPM_HIRD_HW_SHIFT (0U) -/*! HIRD_HW - Host Initiated Resume Duration - HW. - */ -#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK) - -#define USBHSD_LPM_HIRD_SW_MASK (0xF0U) -#define USBHSD_LPM_HIRD_SW_SHIFT (4U) -/*! HIRD_SW - Host Initiated Resume Duration - SW. - */ -#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK) - -#define USBHSD_LPM_DATA_PENDING_MASK (0x100U) -#define USBHSD_LPM_DATA_PENDING_SHIFT (8U) -/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will - * return a NYET handshake on every LPM token it receives. - */ -#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK) -/*! @} */ - -/*! @name EPSKIP - USB Endpoint skip */ -/*! @{ */ - -#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU) -#define USBHSD_EPSKIP_SKIP_SHIFT (0U) -/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must - * deactivate the buffer assigned to this endpoint and return control back to software. - */ -#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK) -/*! @} */ - -/*! @name EPINUSE - USB Endpoint Buffer in use */ -/*! @{ */ - -#define USBHSD_EPINUSE_BUF_MASK (0xFFCU) -#define USBHSD_EPINUSE_BUF_SHIFT (2U) -/*! BUF - Buffer in use: This register has one bit per physical endpoint. - */ -#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK) -/*! @} */ - -/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ -/*! @{ */ - -#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU) -#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U) -/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. - */ -#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK) -/*! @} */ - -/*! @name INTSTAT - USB interrupt status register */ -/*! @{ */ - -#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U) -#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U) -/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. - */ -#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK) - -#define USBHSD_INTSTAT_EP0IN_MASK (0x2U) -#define USBHSD_INTSTAT_EP0IN_SHIFT (1U) -/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. - */ -#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK) - -#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U) -#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U) -/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. - */ -#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK) - -#define USBHSD_INTSTAT_EP1IN_MASK (0x8U) -#define USBHSD_INTSTAT_EP1IN_SHIFT (3U) -/*! EP1IN - Interrupt status register bit for the EP1 IN direction. - */ -#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK) - -#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U) -#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U) -/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. - */ -#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK) - -#define USBHSD_INTSTAT_EP2IN_MASK (0x20U) -#define USBHSD_INTSTAT_EP2IN_SHIFT (5U) -/*! EP2IN - Interrupt status register bit for the EP2 IN direction. - */ -#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK) - -#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U) -#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U) -/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. - */ -#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK) - -#define USBHSD_INTSTAT_EP3IN_MASK (0x80U) -#define USBHSD_INTSTAT_EP3IN_SHIFT (7U) -/*! EP3IN - Interrupt status register bit for the EP3 IN direction. - */ -#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK) - -#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U) -#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U) -/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. - */ -#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK) - -#define USBHSD_INTSTAT_EP4IN_MASK (0x200U) -#define USBHSD_INTSTAT_EP4IN_SHIFT (9U) -/*! EP4IN - Interrupt status register bit for the EP4 IN direction. - */ -#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK) - -#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U) -#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U) -/*! EP5OUT - Interrupt status register bit for the EP5 OUT direction. - */ -#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK) - -#define USBHSD_INTSTAT_EP5IN_MASK (0x800U) -#define USBHSD_INTSTAT_EP5IN_SHIFT (11U) -/*! EP5IN - Interrupt status register bit for the EP5 IN direction. - */ -#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK) - -#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U) -#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U) -/*! FRAME_INT - Frame interrupt. - */ -#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK) - -#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U) -#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U) -/*! DEV_INT - Device status interrupt. - */ -#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK) -/*! @} */ - -/*! @name INTEN - USB interrupt enable register */ -/*! @{ */ - -#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU) -#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U) -/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line. - */ -#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK) - -#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U) -#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U) -/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line. - */ -#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK) - -#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U) -#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U) -/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line. - */ -#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK) -/*! @} */ - -/*! @name INTSETSTAT - USB set interrupt status register */ -/*! @{ */ - -#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU) -#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U) -/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. - */ -#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK) - -#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) -#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) -/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. - */ -#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK) - -#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) -#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U) -/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. - */ -#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK) -/*! @} */ - -/*! @name EPTOGGLE - USB Endpoint toggle register */ -/*! @{ */ - -#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU) -#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U) -/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. - */ -#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBHSD_Register_Masks */ - - -/* USBHSD - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USBHSD base address */ - #define USBHSD_BASE (0x50094000u) - /** Peripheral USBHSD base address */ - #define USBHSD_BASE_NS (0x40094000u) - /** Peripheral USBHSD base pointer */ - #define USBHSD ((USBHSD_Type *)USBHSD_BASE) - /** Peripheral USBHSD base pointer */ - #define USBHSD_NS ((USBHSD_Type *)USBHSD_BASE_NS) - /** Array initializer of USBHSD peripheral base addresses */ - #define USBHSD_BASE_ADDRS { USBHSD_BASE } - /** Array initializer of USBHSD peripheral base pointers */ - #define USBHSD_BASE_PTRS { USBHSD } - /** Array initializer of USBHSD peripheral base addresses */ - #define USBHSD_BASE_ADDRS_NS { USBHSD_BASE_NS } - /** Array initializer of USBHSD peripheral base pointers */ - #define USBHSD_BASE_PTRS_NS { USBHSD_NS } -#else - /** Peripheral USBHSD base address */ - #define USBHSD_BASE (0x40094000u) - /** Peripheral USBHSD base pointer */ - #define USBHSD ((USBHSD_Type *)USBHSD_BASE) - /** Array initializer of USBHSD peripheral base addresses */ - #define USBHSD_BASE_ADDRS { USBHSD_BASE } - /** Array initializer of USBHSD peripheral base pointers */ - #define USBHSD_BASE_PTRS { USBHSD } -#endif -/** Interrupt vectors for the USBHSD peripheral type */ -#define USBHSD_IRQS { USB1_IRQn } -#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBHSD_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBHSH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer - * @{ - */ - -/** USBHSH - Register Layout Typedef */ -typedef struct { - __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */ - __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */ - __IO uint32_t ATLPTD; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */ - __IO uint32_t ISOPTD; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */ - __IO uint32_t INTPTD; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */ - __IO uint32_t DATAPAYLOAD; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */ - __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */ - __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */ - __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */ - __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */ - __IO uint32_t ATLPTDD; /**< Done map for each ATL PTD, offset: 0x30 */ - __IO uint32_t ATLPTDS; /**< Skip map for each ATL PTD, offset: 0x34 */ - __IO uint32_t ISOPTDD; /**< Done map for each ISO PTD, offset: 0x38 */ - __IO uint32_t ISOPTDS; /**< Skip map for each ISO PTD, offset: 0x3C */ - __IO uint32_t INTPTDD; /**< Done map for each INT PTD, offset: 0x40 */ - __IO uint32_t INTPTDS; /**< Skip map for each INT PTD, offset: 0x44 */ - __IO uint32_t LASTPTD; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */ - uint8_t RESERVED_1[4]; - __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */ -} USBHSH_Type; - -/* ---------------------------------------------------------------------------- - -- USBHSH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSH_Register_Masks USBHSH Register Masks - * @{ - */ - -/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */ -/*! @{ */ - -#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU) -#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U) -/*! CAPLENGTH - Capability Length: This is used as an offset. - */ -#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK) - -#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U) -#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U) -/*! CHIPID - Chip identification: indicates major and minor revision of the IP: [31:24] = Major - * revision [23:16] = Minor revision Major revisions used: 0x01: USB2. - */ -#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK) -/*! @} */ - -/*! @name HCSPARAMS - Host Controller Structural Parameters */ -/*! @{ */ - -#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU) -#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U) -/*! N_PORTS - This register specifies the number of physical downstream ports implemented on this host controller. - */ -#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK) - -#define USBHSH_HCSPARAMS_PPC_MASK (0x10U) -#define USBHSH_HCSPARAMS_PPC_SHIFT (4U) -/*! PPC - This field indicates whether the host controller implementation includes port power control. - */ -#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK) - -#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U) -#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U) -/*! P_INDICATOR - This bit indicates whether the ports support port indicator control. - */ -#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK) -/*! @} */ - -/*! @name FLADJ_FRINDEX - Frame Length Adjustment */ -/*! @{ */ - -#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU) -#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U) -/*! FLADJ - Frame Length Timing Value. - */ -#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK) - -#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U) -#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U) -/*! FRINDEX - Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet. - */ -#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) -/*! @} */ - -/*! @name ATLPTD - Memory base address where ATL PTD0 is stored */ -/*! @{ */ - -#define USBHSH_ATLPTD_ATL_CUR_MASK (0x1F0U) -#define USBHSH_ATLPTD_ATL_CUR_SHIFT (4U) -/*! ATL_CUR - This indicates the current PTD that is used by the hardware when it is processing the ATL list. - */ -#define USBHSH_ATLPTD_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_CUR_SHIFT)) & USBHSH_ATLPTD_ATL_CUR_MASK) - -#define USBHSH_ATLPTD_ATL_BASE_MASK (0xFFFFFE00U) -#define USBHSH_ATLPTD_ATL_BASE_SHIFT (9U) -/*! ATL_BASE - Base address to be used by the hardware to find the start of the ATL list. - */ -#define USBHSH_ATLPTD_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_BASE_SHIFT)) & USBHSH_ATLPTD_ATL_BASE_MASK) -/*! @} */ - -/*! @name ISOPTD - Memory base address where ISO PTD0 is stored */ -/*! @{ */ - -#define USBHSH_ISOPTD_ISO_FIRST_MASK (0x3E0U) -#define USBHSH_ISOPTD_ISO_FIRST_SHIFT (5U) -/*! ISO_FIRST - This indicates the first PTD that is used by the hardware when it is processing the ISO list. - */ -#define USBHSH_ISOPTD_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_FIRST_SHIFT)) & USBHSH_ISOPTD_ISO_FIRST_MASK) - -#define USBHSH_ISOPTD_ISO_BASE_MASK (0xFFFFFC00U) -#define USBHSH_ISOPTD_ISO_BASE_SHIFT (10U) -/*! ISO_BASE - Base address to be used by the hardware to find the start of the ISO list. - */ -#define USBHSH_ISOPTD_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_BASE_SHIFT)) & USBHSH_ISOPTD_ISO_BASE_MASK) -/*! @} */ - -/*! @name INTPTD - Memory base address where INT PTD0 is stored */ -/*! @{ */ - -#define USBHSH_INTPTD_INT_FIRST_MASK (0x3E0U) -#define USBHSH_INTPTD_INT_FIRST_SHIFT (5U) -/*! INT_FIRST - This indicates the first PTD that is used by the hardware when it is processing the INT list. - */ -#define USBHSH_INTPTD_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_FIRST_SHIFT)) & USBHSH_INTPTD_INT_FIRST_MASK) - -#define USBHSH_INTPTD_INT_BASE_MASK (0xFFFFFC00U) -#define USBHSH_INTPTD_INT_BASE_SHIFT (10U) -/*! INT_BASE - Base address to be used by the hardware to find the start of the INT list. - */ -#define USBHSH_INTPTD_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_BASE_SHIFT)) & USBHSH_INTPTD_INT_BASE_MASK) -/*! @} */ - -/*! @name DATAPAYLOAD - Memory base address that indicates the start of the data payload buffers */ -/*! @{ */ - -#define USBHSH_DATAPAYLOAD_DAT_BASE_MASK (0xFFFF0000U) -#define USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT (16U) -/*! DAT_BASE - Base address to be used by the hardware to find the start of the data payload section. - */ -#define USBHSH_DATAPAYLOAD_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT)) & USBHSH_DATAPAYLOAD_DAT_BASE_MASK) -/*! @} */ - -/*! @name USBCMD - USB Command register */ -/*! @{ */ - -#define USBHSH_USBCMD_RS_MASK (0x1U) -#define USBHSH_USBCMD_RS_SHIFT (0U) -/*! RS - Run/Stop: 1b = Run. - */ -#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK) - -#define USBHSH_USBCMD_HCRESET_MASK (0x2U) -#define USBHSH_USBCMD_HCRESET_SHIFT (1U) -/*! HCRESET - Host Controller Reset: This control bit is used by the software to reset the host controller. - */ -#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK) - -#define USBHSH_USBCMD_FLS_MASK (0xCU) -#define USBHSH_USBCMD_FLS_SHIFT (2U) -/*! FLS - Frame List Size: This field specifies the size of the frame list. - */ -#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK) - -#define USBHSH_USBCMD_LHCR_MASK (0x80U) -#define USBHSH_USBCMD_LHCR_SHIFT (7U) -/*! LHCR - Light Host Controller Reset: This bit allows the driver software to reset the host - * controller without affecting the state of the ports. - */ -#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK) - -#define USBHSH_USBCMD_ATL_EN_MASK (0x100U) -#define USBHSH_USBCMD_ATL_EN_SHIFT (8U) -/*! ATL_EN - ATL List enabled. - */ -#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK) - -#define USBHSH_USBCMD_ISO_EN_MASK (0x200U) -#define USBHSH_USBCMD_ISO_EN_SHIFT (9U) -/*! ISO_EN - ISO List enabled. - */ -#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK) - -#define USBHSH_USBCMD_INT_EN_MASK (0x400U) -#define USBHSH_USBCMD_INT_EN_SHIFT (10U) -/*! INT_EN - INT List enabled. - */ -#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK) -/*! @} */ - -/*! @name USBSTS - USB Interrupt Status register */ -/*! @{ */ - -#define USBHSH_USBSTS_PCD_MASK (0x4U) -#define USBHSH_USBSTS_PCD_SHIFT (2U) -/*! PCD - Port Change Detect: The host controller sets this bit to logic 1 when any port has a - * change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a - * result of a J-K transition detected on a suspended port. - */ -#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK) - -#define USBHSH_USBSTS_FLR_MASK (0x8U) -#define USBHSH_USBSTS_FLR_SHIFT (3U) -/*! FLR - Frame List Rollover: The host controller sets this bit to logic 1 when the frame list - * index rolls over its maximum value to 0. - */ -#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK) - -#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U) -#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U) -/*! ATL_IRQ - ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed. - */ -#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK) - -#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U) -#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U) -/*! ISO_IRQ - ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed. - */ -#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK) - -#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U) -#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U) -/*! INT_IRQ - INT IRQ: Indicates that an INT PTD (with I-bit set) was completed. - */ -#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK) - -#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U) -#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U) -/*! SOF_IRQ - SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set. - */ -#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK) -/*! @} */ - -/*! @name USBINTR - USB Interrupt Enable register */ -/*! @{ */ - -#define USBHSH_USBINTR_PCDE_MASK (0x4U) -#define USBHSH_USBINTR_PCDE_SHIFT (2U) -/*! PCDE - Port Change Detect Interrupt Enable: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK) - -#define USBHSH_USBINTR_FLRE_MASK (0x8U) -#define USBHSH_USBINTR_FLRE_SHIFT (3U) -/*! FLRE - Frame List Rollover Interrupt Enable: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK) - -#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U) -#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U) -/*! ATL_IRQ_E - ATL IRQ Enable bit: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK) - -#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U) -#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U) -/*! ISO_IRQ_E - ISO IRQ Enable bit: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK) - -#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U) -#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U) -/*! INT_IRQ_E - INT IRQ Enable bit: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK) - -#define USBHSH_USBINTR_SOF_E_MASK (0x80000U) -#define USBHSH_USBINTR_SOF_E_SHIFT (19U) -/*! SOF_E - SOF Interrupt Enable bit: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK) -/*! @} */ - -/*! @name PORTSC1 - Port Status and Control register */ -/*! @{ */ - -#define USBHSH_PORTSC1_CCS_MASK (0x1U) -#define USBHSH_PORTSC1_CCS_SHIFT (0U) -/*! CCS - Current Connect Status: Logic 1 indicates a device is present on the port. - */ -#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK) - -#define USBHSH_PORTSC1_CSC_MASK (0x2U) -#define USBHSH_PORTSC1_CSC_SHIFT (1U) -/*! CSC - Connect Status Change: Logic 1 means that the value of CCS has changed. - */ -#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK) - -#define USBHSH_PORTSC1_PED_MASK (0x4U) -#define USBHSH_PORTSC1_PED_SHIFT (2U) -/*! PED - Port Enabled/Disabled. - */ -#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK) - -#define USBHSH_PORTSC1_PEDC_MASK (0x8U) -#define USBHSH_PORTSC1_PEDC_SHIFT (3U) -/*! PEDC - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed. - */ -#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK) - -#define USBHSH_PORTSC1_OCA_MASK (0x10U) -#define USBHSH_PORTSC1_OCA_SHIFT (4U) -/*! OCA - Over-current active: Logic 1 means that this port has an over-current condition. - */ -#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK) - -#define USBHSH_PORTSC1_OCC_MASK (0x20U) -#define USBHSH_PORTSC1_OCC_SHIFT (5U) -/*! OCC - Over-current change: Logic 1 means that the value of OCA has changed. - */ -#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK) - -#define USBHSH_PORTSC1_FPR_MASK (0x40U) -#define USBHSH_PORTSC1_FPR_SHIFT (6U) -/*! FPR - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port. - */ -#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK) - -#define USBHSH_PORTSC1_SUSP_MASK (0x80U) -#define USBHSH_PORTSC1_SUSP_SHIFT (7U) -/*! SUSP - Suspend: Logic 1 means port is in the suspend state. - */ -#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK) - -#define USBHSH_PORTSC1_PR_MASK (0x100U) -#define USBHSH_PORTSC1_PR_SHIFT (8U) -/*! PR - Port Reset: Logic 1 means the port is in the reset state. - */ -#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK) - -#define USBHSH_PORTSC1_LS_MASK (0xC00U) -#define USBHSH_PORTSC1_LS_SHIFT (10U) -/*! LS - Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. - */ -#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK) - -#define USBHSH_PORTSC1_PP_MASK (0x1000U) -#define USBHSH_PORTSC1_PP_SHIFT (12U) -/*! PP - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register. - */ -#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK) - -#define USBHSH_PORTSC1_PIC_MASK (0xC000U) -#define USBHSH_PORTSC1_PIC_SHIFT (14U) -/*! PIC - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the - * HCSPARAMS register is logic 0. - */ -#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK) - -#define USBHSH_PORTSC1_PTC_MASK (0xF0000U) -#define USBHSH_PORTSC1_PTC_SHIFT (16U) -/*! PTC - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value. - */ -#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK) - -#define USBHSH_PORTSC1_PSPD_MASK (0x300000U) -#define USBHSH_PORTSC1_PSPD_SHIFT (20U) -/*! PSPD - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved. - */ -#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK) - -#define USBHSH_PORTSC1_WOO_MASK (0x400000U) -#define USBHSH_PORTSC1_WOO_SHIFT (22U) -/*! WOO - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to - * overcurrent conditions as wake-up events. - */ -#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK) -/*! @} */ - -/*! @name ATLPTDD - Done map for each ATL PTD */ -/*! @{ */ - -#define USBHSH_ATLPTDD_ATL_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_ATLPTDD_ATL_DONE_SHIFT (0U) -/*! ATL_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - */ -#define USBHSH_ATLPTDD_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDD_ATL_DONE_SHIFT)) & USBHSH_ATLPTDD_ATL_DONE_MASK) -/*! @} */ - -/*! @name ATLPTDS - Skip map for each ATL PTD */ -/*! @{ */ - -#define USBHSH_ATLPTDS_ATL_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_ATLPTDS_ATL_SKIP_SHIFT (0U) -/*! ATL_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be - * skipped, independent of the V bit setting. - */ -#define USBHSH_ATLPTDS_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDS_ATL_SKIP_SHIFT)) & USBHSH_ATLPTDS_ATL_SKIP_MASK) -/*! @} */ - -/*! @name ISOPTDD - Done map for each ISO PTD */ -/*! @{ */ - -#define USBHSH_ISOPTDD_ISO_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_ISOPTDD_ISO_DONE_SHIFT (0U) -/*! ISO_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - */ -#define USBHSH_ISOPTDD_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDD_ISO_DONE_SHIFT)) & USBHSH_ISOPTDD_ISO_DONE_MASK) -/*! @} */ - -/*! @name ISOPTDS - Skip map for each ISO PTD */ -/*! @{ */ - -#define USBHSH_ISOPTDS_ISO_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_ISOPTDS_ISO_SKIP_SHIFT (0U) -/*! ISO_SKIP - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - */ -#define USBHSH_ISOPTDS_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDS_ISO_SKIP_SHIFT)) & USBHSH_ISOPTDS_ISO_SKIP_MASK) -/*! @} */ - -/*! @name INTPTDD - Done map for each INT PTD */ -/*! @{ */ - -#define USBHSH_INTPTDD_INT_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_INTPTDD_INT_DONE_SHIFT (0U) -/*! INT_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - */ -#define USBHSH_INTPTDD_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDD_INT_DONE_SHIFT)) & USBHSH_INTPTDD_INT_DONE_MASK) -/*! @} */ - -/*! @name INTPTDS - Skip map for each INT PTD */ -/*! @{ */ - -#define USBHSH_INTPTDS_INT_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_INTPTDS_INT_SKIP_SHIFT (0U) -/*! INT_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be - * skipped, independent of the V bit setting. - */ -#define USBHSH_INTPTDS_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDS_INT_SKIP_SHIFT)) & USBHSH_INTPTDS_INT_SKIP_MASK) -/*! @} */ - -/*! @name LASTPTD - Marks the last PTD in the list for ISO, INT and ATL */ -/*! @{ */ - -#define USBHSH_LASTPTD_ATL_LAST_MASK (0x1FU) -#define USBHSH_LASTPTD_ATL_LAST_SHIFT (0U) -/*! ATL_LAST - If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed. - */ -#define USBHSH_LASTPTD_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ATL_LAST_SHIFT)) & USBHSH_LASTPTD_ATL_LAST_MASK) - -#define USBHSH_LASTPTD_ISO_LAST_MASK (0x1F00U) -#define USBHSH_LASTPTD_ISO_LAST_SHIFT (8U) -/*! ISO_LAST - This indicates the last PTD in the ISO list. - */ -#define USBHSH_LASTPTD_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ISO_LAST_SHIFT)) & USBHSH_LASTPTD_ISO_LAST_MASK) - -#define USBHSH_LASTPTD_INT_LAST_MASK (0x1F0000U) -#define USBHSH_LASTPTD_INT_LAST_SHIFT (16U) -/*! INT_LAST - This indicates the last PTD in the INT list. - */ -#define USBHSH_LASTPTD_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_INT_LAST_SHIFT)) & USBHSH_LASTPTD_INT_LAST_MASK) -/*! @} */ - -/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ -/*! @{ */ - -#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) -#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U) -/*! DEV_ENABLE - If this bit is set to one, one of the ports will behave as a USB device. - */ -#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK) - -#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U) -#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U) -/*! SW_CTRL_PDCOM - This bit indicates if the PHY power-down input is controlled by software or by hardware. - */ -#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK) - -#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U) -#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U) -/*! SW_PDCOM - This bit is only used when SW_CTRL_PDCOM is set to 1b. - */ -#define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBHSH_Register_Masks */ - - -/* USBHSH - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USBHSH base address */ - #define USBHSH_BASE (0x500A3000u) - /** Peripheral USBHSH base address */ - #define USBHSH_BASE_NS (0x400A3000u) - /** Peripheral USBHSH base pointer */ - #define USBHSH ((USBHSH_Type *)USBHSH_BASE) - /** Peripheral USBHSH base pointer */ - #define USBHSH_NS ((USBHSH_Type *)USBHSH_BASE_NS) - /** Array initializer of USBHSH peripheral base addresses */ - #define USBHSH_BASE_ADDRS { USBHSH_BASE } - /** Array initializer of USBHSH peripheral base pointers */ - #define USBHSH_BASE_PTRS { USBHSH } - /** Array initializer of USBHSH peripheral base addresses */ - #define USBHSH_BASE_ADDRS_NS { USBHSH_BASE_NS } - /** Array initializer of USBHSH peripheral base pointers */ - #define USBHSH_BASE_PTRS_NS { USBHSH_NS } -#else - /** Peripheral USBHSH base address */ - #define USBHSH_BASE (0x400A3000u) - /** Peripheral USBHSH base pointer */ - #define USBHSH ((USBHSH_Type *)USBHSH_BASE) - /** Array initializer of USBHSH peripheral base addresses */ - #define USBHSH_BASE_ADDRS { USBHSH_BASE } - /** Array initializer of USBHSH peripheral base pointers */ - #define USBHSH_BASE_PTRS { USBHSH } -#endif -/** Interrupt vectors for the USBHSH peripheral type */ -#define USBHSH_IRQS { USB1_IRQn } -#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBHSH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBPHY Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer - * @{ - */ - -/** USBPHY - Register Layout Typedef */ -typedef struct { - __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ - __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ - __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ - __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ - __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ - __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ - __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ - __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ - __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ - __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ - __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ - __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ - __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ - __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ - __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ - __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ - __I uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ - uint8_t RESERVED_0[92]; - __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */ - __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */ - __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */ - __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */ - uint8_t RESERVED_1[16]; - __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */ - __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */ - __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */ - __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */ - uint8_t RESERVED_2[48]; - __IO uint32_t ANACTRLr; /**< USB PHY Analog Control Register, offset: 0x100 */ - __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */ - __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */ - __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */ -} USBPHY_Type; - -/* ---------------------------------------------------------------------------- - -- USBPHY Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBPHY_Register_Masks USBPHY Register Masks - * @{ - */ - -/*! @name PWD - USB PHY Power-Down Register */ -/*! @{ */ - -#define USBPHY_PWD_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) - -#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) - -#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) - -#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) - -#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) - -#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) - -#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) -/*! @} */ - -/*! @name PWD_SET - USB PHY Power-Down Register */ -/*! @{ */ - -#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) - -#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) - -#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) - -#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) - -#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) - -#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) - -#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) -/*! @} */ - -/*! @name PWD_CLR - USB PHY Power-Down Register */ -/*! @{ */ - -#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) - -#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) - -#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) - -#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) - -#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) - -#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) - -#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) -/*! @} */ - -/*! @name PWD_TOG - USB PHY Power-Down Register */ -/*! @{ */ - -#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) - -#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) - -#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) - -#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) - -#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) - -#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) - -#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) -/*! @} */ - -/*! @name TX - USB PHY Transmitter Control Register */ -/*! @{ */ - -#define USBPHY_TX_D_CAL_MASK (0xFU) -#define USBPHY_TX_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) - -#define USBPHY_TX_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK) - -#define USBPHY_TX_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DN_SHIFT)) & USBPHY_TX_TXENCAL45DN_MASK) - -#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) - -#define USBPHY_TX_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name TX_SET - USB PHY Transmitter Control Register */ -/*! @{ */ - -#define USBPHY_TX_SET_D_CAL_MASK (0xFU) -#define USBPHY_TX_SET_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) - -#define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK) - -#define USBPHY_TX_SET_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_SET_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_SET_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DN_SHIFT)) & USBPHY_TX_SET_TXENCAL45DN_MASK) - -#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) - -#define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_SET_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name TX_CLR - USB PHY Transmitter Control Register */ -/*! @{ */ - -#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) -#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) - -#define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK) - -#define USBPHY_TX_CLR_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_CLR_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_CLR_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DN_MASK) - -#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) - -#define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_CLR_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name TX_TOG - USB PHY Transmitter Control Register */ -/*! @{ */ - -#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) -#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) - -#define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK) - -#define USBPHY_TX_TOG_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_TOG_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_TOG_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DN_MASK) - -#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) - -#define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_TOG_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name RX - USB PHY Receiver Control Register */ -/*! @{ */ - -#define USBPHY_RX_ENVADJ_MASK (0x7U) -#define USBPHY_RX_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) - -#define USBPHY_RX_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) - -#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) -/*! @} */ - -/*! @name RX_SET - USB PHY Receiver Control Register */ -/*! @{ */ - -#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) -#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) - -#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) - -#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) -/*! @} */ - -/*! @name RX_CLR - USB PHY Receiver Control Register */ -/*! @{ */ - -#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) -#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) - -#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) - -#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) -/*! @} */ - -/*! @name RX_TOG - USB PHY Receiver Control Register */ -/*! @{ */ - -#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) -#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) - -#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) - -#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) -/*! @} */ - -/*! @name CTRL - USB PHY General Control Register */ -/*! @{ */ - -#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) - -#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) -#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) -#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) - -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) - -#define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK) - -#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) -#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) -#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) - -#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) -#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) -#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) - -#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) -#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) -#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) - -#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) -#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) -#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) - -#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) - -#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) - -#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) - -#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) -#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) -#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) - -#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) -#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) -#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) - -#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) - -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) - -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) - -#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) -#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) -#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) - -#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) -#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) -#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) - -#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) -#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT (25U) -#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK) - -#define USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK (0x4000000U) -#define USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT (26U) -#define USBPHY_CTRL_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK) - -#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) - -#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) - -#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) - -#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_SET - USB PHY General Control Register */ -/*! @{ */ - -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) - -#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) -#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) -#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) - -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) - -#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK) - -#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) -#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) -#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) - -#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) -#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) -#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) - -#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) -#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) -#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) - -#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) -#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) -#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) - -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) - -#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) - -#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) - -#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) -#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) -#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) - -#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) -#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) -#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) - -#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) - -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) - -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) - -#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) -#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) -#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) - -#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) -#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) -#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) - -#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) -#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT (25U) -#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK) - -#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK (0x4000000U) -#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT (26U) -#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK) - -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) - -#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) - -#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) - -#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_CLR - USB PHY General Control Register */ -/*! @{ */ - -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) - -#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) -#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) -#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) - -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) - -#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK) - -#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) - -#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) -#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) -#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) - -#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) -#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) -#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) - -#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) -#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) -#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) - -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) - -#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) - -#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) - -#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) -#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) -#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) - -#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) -#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) -#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) - -#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) - -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) - -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) - -#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) -#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) -#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) - -#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) -#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) -#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) - -#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT (25U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK) - -#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK (0x4000000U) -#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT (26U) -#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK) - -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) - -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) - -#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) - -#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_TOG - USB PHY General Control Register */ -/*! @{ */ - -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) - -#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) -#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) -#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) - -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) - -#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK) - -#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) - -#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) -#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) -#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) - -#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) -#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) -#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) - -#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) -#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) -#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) - -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) - -#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) - -#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) - -#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) -#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) -#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) - -#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) -#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) -#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) - -#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) - -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) - -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) - -#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) -#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) -#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) - -#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) -#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) -#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) - -#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT (25U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK) - -#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK (0x4000000U) -#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT (26U) -#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK) - -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) - -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) - -#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) - -#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) -/*! @} */ - -/*! @name STATUS - USB PHY Status Register */ -/*! @{ */ - -#define USBPHY_STATUS_OK_STATUS_3V_MASK (0x1U) -#define USBPHY_STATUS_OK_STATUS_3V_SHIFT (0U) -#define USBPHY_STATUS_OK_STATUS_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OK_STATUS_3V_SHIFT)) & USBPHY_STATUS_OK_STATUS_3V_MASK) - -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) -/*! HOSTDISCONDETECT_STATUS - * 0b0..USB cable disconnect has not been detected at the local host - * 0b1..USB cable disconnect has been detected at the local host - */ -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) - -#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) -#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) -/*! DEVPLUGIN_STATUS - * 0b0..No attachment to a USB host is detected - * 0b1..Cable attachment to a USB host is detected - */ -#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) - -#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) -#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) -#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) -/*! @} */ - -/*! @name PLL_SIC - USB PHY PLL Control/Status Register */ -/*! @{ */ - -#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) - -#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) - -#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) - -#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) - -#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) - -#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) - -#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) - -#define USBPHY_PLL_SIC_PLL_PREDIV_MASK (0x40000000U) -#define USBPHY_PLL_SIC_PLL_PREDIV_SHIFT (30U) -#define USBPHY_PLL_SIC_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_PREDIV_MASK) - -#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */ -/*! @{ */ - -#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) - -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) - -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK (0x40000000U) -#define USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT (30U) -#define USBPHY_PLL_SIC_SET_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */ -/*! @{ */ - -#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) - -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) - -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK (0x40000000U) -#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT (30U) -#define USBPHY_PLL_SIC_CLR_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */ -/*! @{ */ - -#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) - -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) - -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK (0x40000000U) -#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT (30U) -#define USBPHY_PLL_SIC_TOG_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */ -/*! @{ */ - -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U) -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U) -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U) -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U) -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK (0x2000U) -#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. - * 0b1..Select the external ID value. - */ -#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) -#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. - * 0b1..Select the external VBUS VALID value. - */ -#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK (0x80000U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT (19U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK) - -#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x700000U) -#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b000..Powers down the VBUS_VALID comparator - * 0b111..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK) - -#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */ -/*! @{ */ - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U) -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U) -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U) -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U) -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK (0x2000U) -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. - * 0b1..Select the external ID value. - */ -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. - * 0b1..Select the external VBUS VALID value. - */ -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK (0x80000U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT (19U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U) -#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b000..Powers down the VBUS_VALID comparator - * 0b111..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */ -/*! @{ */ - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U) -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U) -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U) -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK (0x2000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. - * 0b1..Select the external ID value. - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - * 0b0..Select the muxed value chosen using VBUS_OVERRIDE_EN. - * 0b1..Select the external VBUS VALID value. - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK (0x80000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT (19U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b000..Powers down the VBUS_VALID comparator - * 0b111..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */ -/*! @{ */ - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U) -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U) -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U) -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK (0x2000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - * 0b0..Select the muxed value chosen using ID_OVERRIDE_EN. - * 0b1..Select the external ID value. - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. - * 0b1..Select the external VBUS VALID value. - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK (0x80000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT (19U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b000..Powers down the VBUS_VALID comparator - * 0b111..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) -/*! @} */ - -/*! @name ANACTRL - USB PHY Analog Control Register */ -/*! @{ */ - -#define USBPHY_ANACTRL_LVI_EN_MASK (0x2U) -#define USBPHY_ANACTRL_LVI_EN_SHIFT (1U) -#define USBPHY_ANACTRL_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_LVI_EN_SHIFT)) & USBPHY_ANACTRL_LVI_EN_MASK) - -#define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU) -#define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U) -#define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) - -#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) -/*! @} */ - -/*! @name ANACTRL_SET - USB PHY Analog Control Register */ -/*! @{ */ - -#define USBPHY_ANACTRL_SET_LVI_EN_MASK (0x2U) -#define USBPHY_ANACTRL_SET_LVI_EN_SHIFT (1U) -#define USBPHY_ANACTRL_SET_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_LVI_EN_SHIFT)) & USBPHY_ANACTRL_SET_LVI_EN_MASK) - -#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU) -#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U) -#define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK) - -#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) -/*! @} */ - -/*! @name ANACTRL_CLR - USB PHY Analog Control Register */ -/*! @{ */ - -#define USBPHY_ANACTRL_CLR_LVI_EN_MASK (0x2U) -#define USBPHY_ANACTRL_CLR_LVI_EN_SHIFT (1U) -#define USBPHY_ANACTRL_CLR_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_LVI_EN_SHIFT)) & USBPHY_ANACTRL_CLR_LVI_EN_MASK) - -#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU) -#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U) -#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK) - -#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) -/*! @} */ - -/*! @name ANACTRL_TOG - USB PHY Analog Control Register */ -/*! @{ */ - -#define USBPHY_ANACTRL_TOG_LVI_EN_MASK (0x2U) -#define USBPHY_ANACTRL_TOG_LVI_EN_SHIFT (1U) -#define USBPHY_ANACTRL_TOG_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_LVI_EN_SHIFT)) & USBPHY_ANACTRL_TOG_LVI_EN_MASK) - -#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU) -#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U) -#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK) - -#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBPHY_Register_Masks */ - - -/* USBPHY - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USBPHY base address */ - #define USBPHY_BASE (0x50038000u) - /** Peripheral USBPHY base address */ - #define USBPHY_BASE_NS (0x40038000u) - /** Peripheral USBPHY base pointer */ - #define USBPHY ((USBPHY_Type *)USBPHY_BASE) - /** Peripheral USBPHY base pointer */ - #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) - /** Array initializer of USBPHY peripheral base addresses */ - #define USBPHY_BASE_ADDRS { USBPHY_BASE } - /** Array initializer of USBPHY peripheral base pointers */ - #define USBPHY_BASE_PTRS { USBPHY } - /** Array initializer of USBPHY peripheral base addresses */ - #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } - /** Array initializer of USBPHY peripheral base pointers */ - #define USBPHY_BASE_PTRS_NS { USBPHY_NS } -#else - /** Peripheral USBPHY base address */ - #define USBPHY_BASE (0x40038000u) - /** Peripheral USBPHY base pointer */ - #define USBPHY ((USBPHY_Type *)USBPHY_BASE) - /** Array initializer of USBPHY peripheral base addresses */ - #define USBPHY_BASE_ADDRS { USBPHY_BASE } - /** Array initializer of USBPHY peripheral base pointers */ - #define USBPHY_BASE_PTRS { USBPHY } -#endif -/** Interrupt vectors for the USBPHY peripheral type */ -#define USBPHY_IRQS { USB1_PHY_IRQn } - -/*! - * @} - */ /* end of group USBPHY_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- UTICK Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer - * @{ - */ - -/** UTICK - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ - __IO uint32_t STAT; /**< Status register., offset: 0x4 */ - __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ - __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ - __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ -} UTICK_Type; - -/* ---------------------------------------------------------------------------- - -- UTICK Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Register_Masks UTICK Register Masks - * @{ - */ - -/*! @name CTRL - Control register. */ -/*! @{ */ - -#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) -#define UTICK_CTRL_DELAYVAL_SHIFT (0U) -/*! DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer - * clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer. - */ -#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) - -#define UTICK_CTRL_REPEAT_MASK (0x80000000U) -#define UTICK_CTRL_REPEAT_SHIFT (31U) -/*! REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. - */ -#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) -/*! @} */ - -/*! @name STAT - Status register. */ -/*! @{ */ - -#define UTICK_STAT_INTR_MASK (0x1U) -#define UTICK_STAT_INTR_SHIFT (0U) -/*! INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any - * value to this register clears this flag. - */ -#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) - -#define UTICK_STAT_ACTIVE_MASK (0x2U) -#define UTICK_STAT_ACTIVE_SHIFT (1U) -/*! ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. - */ -#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) -/*! @} */ - -/*! @name CFG - Capture configuration register. */ -/*! @{ */ - -#define UTICK_CFG_CAPEN0_MASK (0x1U) -#define UTICK_CFG_CAPEN0_SHIFT (0U) -/*! CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled. - */ -#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) - -#define UTICK_CFG_CAPEN1_MASK (0x2U) -#define UTICK_CFG_CAPEN1_SHIFT (1U) -/*! CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled. - */ -#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) - -#define UTICK_CFG_CAPEN2_MASK (0x4U) -#define UTICK_CFG_CAPEN2_SHIFT (2U) -/*! CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled. - */ -#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) - -#define UTICK_CFG_CAPEN3_MASK (0x8U) -#define UTICK_CFG_CAPEN3_SHIFT (3U) -/*! CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled. - */ -#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) - -#define UTICK_CFG_CAPPOL0_MASK (0x100U) -#define UTICK_CFG_CAPPOL0_SHIFT (8U) -/*! CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. - */ -#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) - -#define UTICK_CFG_CAPPOL1_MASK (0x200U) -#define UTICK_CFG_CAPPOL1_SHIFT (9U) -/*! CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. - */ -#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) - -#define UTICK_CFG_CAPPOL2_MASK (0x400U) -#define UTICK_CFG_CAPPOL2_SHIFT (10U) -/*! CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. - */ -#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) - -#define UTICK_CFG_CAPPOL3_MASK (0x800U) -#define UTICK_CFG_CAPPOL3_SHIFT (11U) -/*! CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. - */ -#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) -/*! @} */ - -/*! @name CAPCLR - Capture clear register. */ -/*! @{ */ - -#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) -#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) -/*! CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value. - */ -#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) - -#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) -#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) -/*! CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value. - */ -#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) - -#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) -#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) -/*! CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value. - */ -#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) - -#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) -#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) -/*! CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value. - */ -#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) -/*! @} */ - -/*! @name CAP - Capture register . */ -/*! @{ */ - -#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) -#define UTICK_CAP_CAP_VALUE_SHIFT (0U) -/*! CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower - * than the actual value of the Micro-tick Timer at the moment of the capture event. - */ -#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) - -#define UTICK_CAP_VALID_MASK (0x80000000U) -#define UTICK_CAP_VALID_SHIFT (31U) -/*! VALID - Capture Valid. When 1, a value has been captured based on a transition of the related - * UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. - */ -#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) -/*! @} */ - -/* The count of UTICK_CAP */ -#define UTICK_CAP_COUNT (4U) - - -/*! - * @} - */ /* end of group UTICK_Register_Masks */ - - -/* UTICK - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE (0x5000E000u) - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE_NS (0x4000E000u) - /** Peripheral UTICK0 base pointer */ - #define UTICK0 ((UTICK_Type *)UTICK0_BASE) - /** Peripheral UTICK0 base pointer */ - #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS { UTICK0_BASE } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS { UTICK0 } - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS_NS { UTICK0_NS } -#else - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE (0x4000E000u) - /** Peripheral UTICK0 base pointer */ - #define UTICK0 ((UTICK_Type *)UTICK0_BASE) - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS { UTICK0_BASE } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS { UTICK0 } -#endif -/** Interrupt vectors for the UTICK peripheral type */ -#define UTICK_IRQS { UTICK0_IRQn } - -/*! - * @} - */ /* end of group UTICK_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- WWDT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer - * @{ - */ - -/** WWDT - Register Layout Typedef */ -typedef struct { - __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ - __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ - __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ - __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ - uint8_t RESERVED_0[4]; - __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ - __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ -} WWDT_Type; - -/* ---------------------------------------------------------------------------- - -- WWDT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Register_Masks WWDT Register Masks - * @{ - */ - -/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ -/*! @{ */ - -#define WWDT_MOD_WDEN_MASK (0x1U) -#define WWDT_MOD_WDEN_SHIFT (0U) -/*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the - * watchdog timer will run permanently. - * 0b0..Stop. The watchdog timer is stopped. - * 0b1..Run. The watchdog timer is running. - */ -#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) - -#define WWDT_MOD_WDRESET_MASK (0x2U) -#define WWDT_MOD_WDRESET_SHIFT (1U) -/*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. - * 0b0..Interrupt. A watchdog time-out will not cause a chip reset. - * 0b1..Reset. A watchdog time-out will cause a chip reset. - */ -#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) - -#define WWDT_MOD_WDTOF_MASK (0x4U) -#define WWDT_MOD_WDTOF_SHIFT (2U) -/*! WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by - * events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a - * chip reset if WDRESET = 1. - */ -#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) - -#define WWDT_MOD_WDINT_MASK (0x8U) -#define WWDT_MOD_WDINT_SHIFT (3U) -/*! WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. - * Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the - * WARNINT value is equal to the value of the TV register. This can occur if the value of - * WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. - */ -#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) - -#define WWDT_MOD_WDPROTECT_MASK (0x10U) -#define WWDT_MOD_WDPROTECT_SHIFT (4U) -/*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. - * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time. - * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. - */ -#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) -/*! @} */ - -/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ -/*! @{ */ - -#define WWDT_TC_COUNT_MASK (0xFFFFFFU) -#define WWDT_TC_COUNT_SHIFT (0U) -/*! COUNT - Watchdog time-out value. - */ -#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) -/*! @} */ - -/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ -/*! @{ */ - -#define WWDT_FEED_FEED_MASK (0xFFU) -#define WWDT_FEED_FEED_SHIFT (0U) -/*! FEED - Feed value should be 0xAA followed by 0x55. - */ -#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) -/*! @} */ - -/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ -/*! @{ */ - -#define WWDT_TV_COUNT_MASK (0xFFFFFFU) -#define WWDT_TV_COUNT_SHIFT (0U) -/*! COUNT - Counter timer value. - */ -#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) -/*! @} */ - -/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ -/*! @{ */ - -#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) -#define WWDT_WARNINT_WARNINT_SHIFT (0U) -/*! WARNINT - Watchdog warning interrupt compare value. - */ -#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) -/*! @} */ - -/*! @name WINDOW - Watchdog Window compare value. */ -/*! @{ */ - -#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) -#define WWDT_WINDOW_WINDOW_SHIFT (0U) -/*! WINDOW - Watchdog window value. - */ -#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group WWDT_Register_Masks */ - - -/* WWDT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral WWDT base address */ - #define WWDT_BASE (0x5000C000u) - /** Peripheral WWDT base address */ - #define WWDT_BASE_NS (0x4000C000u) - /** Peripheral WWDT base pointer */ - #define WWDT ((WWDT_Type *)WWDT_BASE) - /** Peripheral WWDT base pointer */ - #define WWDT_NS ((WWDT_Type *)WWDT_BASE_NS) - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS { WWDT_BASE } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS { WWDT } - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS_NS { WWDT_BASE_NS } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS_NS { WWDT_NS } -#else - /** Peripheral WWDT base address */ - #define WWDT_BASE (0x4000C000u) - /** Peripheral WWDT base pointer */ - #define WWDT ((WWDT_Type *)WWDT_BASE) - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS { WWDT_BASE } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS { WWDT } -#endif -/** Interrupt vectors for the WWDT peripheral type */ -#define WWDT_IRQS { WDT_BOD_IRQn } - -/*! - * @} - */ /* end of group WWDT_Peripheral_Access_Layer */ - - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop - #else - #pragma pop - #endif -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -/*! - * @} - */ /* end of group Peripheral_access_layer */ - - -/* ---------------------------------------------------------------------------- - -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - * @{ - */ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang system_header - #endif -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma system_include -#endif - -/** - * @brief Mask and left-shift a bit field value for use in a register bit range. - * @param field Name of the register bit field. - * @param value Value of the bit field. - * @return Masked and shifted value. - */ -#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) -/** - * @brief Mask and right-shift a register value to extract a bit field value. - * @param field Name of the register bit field. - * @param value Value of the register. - * @return Masked and shifted bit field value. - */ -#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) - -/*! - * @} - */ /* end of group Bit_Field_Generic_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SDK Compatibility - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDK_Compatibility_Symbols SDK Compatibility - * @{ - */ - -/** High Speed SPI (Flexcomm 8) interrupt name */ -#define LSPI_HS_IRQn FLEXCOMM8_IRQn - -/*! - * @brief Get the chip value. - * - * @return chip version, 0x0: A0 version chip, 0x1: A1 version chip, 0xFF: invalid version. - */ -static inline uint32_t Chip_GetVersion(void) -{ - uint32_t deviceRevision; - - deviceRevision = SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK; - - if(0UL == deviceRevision) /* A0 device revision is 0 */ - { - return 0x0; - } - else if(1UL == deviceRevision) /* A1 device revision is 1 */ - { - return 0x1; - } - else - { - return 0xFF; - } -} - - -/*! - * @} - */ /* end of group SDK_Compatibility_Symbols */ - - -#endif /* _LPC55S69_CM33_CORE0_H_ */ - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.xml b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.xml deleted file mode 100644 index 0353d8f92be..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.xml +++ /dev/null @@ -1,85475 +0,0 @@ - - - nxp.com - LPC55S69_cm33_core0 - 1.0 - LPC55S69JBD100,LPC55S69JBD64,LPC55S69JEV98 - -Copyright 2016-2021 NXP -All rights reserved. - -SPDX-License-Identifier: BSD-3-Clause - - - CM33 - r2p0 - little - true - true - true - 3 - false - - 8 - 32 - - - FLASH_CFPA0 - FLASH_CFPA - FLASH_CFPA - FLASH_CFPA - 0x9E000 - - 0 - 0x200 - registers - - - - HEADER - no description available - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - VERSION - no description available - 0x4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - S_FW_Version - Secure firmware version (Monotonic counter) - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - NS_FW_Version - Non-Secure firmware version (Monotonic counter) - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - ROTKH_REVOKE - no description available - 0x18 - 32 - read-write - 0 - 0xFFFFFFFF - - - RoTK0_EN - RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - 0 - 2 - read-write - - - RoTK1_EN - RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - 2 - 2 - read-write - - - RoTK2_EN - RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - 4 - 2 - read-write - - - RoTK3_EN - RoT Key 3 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - 6 - 2 - read-write - - - - - VENDOR_USAGE - no description available - 0x1C - 32 - read-write - 0 - 0xFFFFFFFF - - - DBG_VENDOR_USAGE - DBG_VENDOR_USAGE. - 0 - 16 - read-write - - - INVERSE_VALUE - inverse value of bits [15:0] - 16 - 16 - read-write - - - - - DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. - 0x20 - 32 - read-write - 0 - 0xFFFFFFFF - - - NIDEN - Non Secure non-invasive debug enable - 0 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - DBGEN - Non Secure debug enable - 1 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - SPNIDEN - Secure non-invasive debug enable - 2 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - SPIDEN - Secure invasive debug enable - 3 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - TAPEN - JTAG TAP enable - 4 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable - 5 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - ISP_CMD_EN - ISP Boot Command enable - 6 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - FA_CMD_EN - FA Command enable - 7 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - ME_CMD_EN - Flash Mass Erase Command enable - 8 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable - 9 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - UUID_CHECK - Enforce UUID match during Debug authentication. - 15 - 1 - read-write - - - INVERSE_VALUE - inverse value of bits [15:0] - 16 - 16 - read-write - - - - - DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. - 0x24 - 32 - read-write - 0 - 0xFFFFFFFF - - - NIDEN - Non Secure non-invasive debug fixed state - 0 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - DBGEN - Non Secure debug fixed state - 1 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - SPNIDEN - Secure non-invasive debug fixed state - 2 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - SPIDEN - Secure invasive debug fixed state - 3 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - TAPEN - JTAG TAP fixed state - 4 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state - 5 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - ISP_CMD_EN - ISP Boot Command fixed state - 6 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - FA_CMD_EN - FA Command fixed state - 7 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - ME_CMD_EN - Flash Mass Erase Command fixed state - 8 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state - 9 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - INVERSE_VALUE - inverse value of bits [15:0] - 16 - 16 - read-write - - - - - ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. - 0x28 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. - 0x2C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE0 - no description available - PRINCE_REGION0_IV_CODE - 0x30 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_HEADER0 - no description available - PRINCE_REGION0_IV_CODE - 0x30 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE1 - no description available - PRINCE_REGION0_IV_CODE - 0x34 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_HEADER1 - no description available - PRINCE_REGION0_IV_CODE - 0x34 - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - no description available - 0 - 2 - read-write - - - INDEX - no description available - 8 - 4 - read-write - - - SIZE - no description available - 24 - 6 - read-write - - - - - PRINCE_REGION0_IV_BODY0 - no description available - PRINCE_REGION0_IV_CODE - 0x38 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE2 - no description available - PRINCE_REGION0_IV_CODE - 0x38 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY1 - no description available - PRINCE_REGION0_IV_CODE - 0x3C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE3 - no description available - PRINCE_REGION0_IV_CODE - 0x3C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY2 - no description available - PRINCE_REGION0_IV_CODE - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE4 - no description available - PRINCE_REGION0_IV_CODE - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY3 - no description available - PRINCE_REGION0_IV_CODE - 0x44 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE5 - no description available - PRINCE_REGION0_IV_CODE - 0x44 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY4 - no description available - PRINCE_REGION0_IV_CODE - 0x48 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE6 - no description available - PRINCE_REGION0_IV_CODE - 0x48 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY5 - no description available - PRINCE_REGION0_IV_CODE - 0x4C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE7 - no description available - PRINCE_REGION0_IV_CODE - 0x4C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY6 - no description available - PRINCE_REGION0_IV_CODE - 0x50 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE8 - no description available - PRINCE_REGION0_IV_CODE - 0x50 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY7 - no description available - PRINCE_REGION0_IV_CODE - 0x54 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE9 - no description available - PRINCE_REGION0_IV_CODE - 0x54 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY8 - no description available - PRINCE_REGION0_IV_CODE - 0x58 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE10 - no description available - PRINCE_REGION0_IV_CODE - 0x58 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY9 - no description available - PRINCE_REGION0_IV_CODE - 0x5C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE11 - no description available - PRINCE_REGION0_IV_CODE - 0x5C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY10 - no description available - PRINCE_REGION0_IV_CODE - 0x60 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE12 - no description available - PRINCE_REGION0_IV_CODE - 0x60 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY11 - no description available - PRINCE_REGION0_IV_CODE - 0x64 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE13 - no description available - PRINCE_REGION0_IV_CODE - 0x64 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE0 - no description available - PRINCE_REGION1_IV_CODE - 0x68 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_HEADER0 - no description available - PRINCE_REGION1_IV_CODE - 0x68 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE1 - no description available - PRINCE_REGION1_IV_CODE - 0x6C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_HEADER1 - no description available - PRINCE_REGION1_IV_CODE - 0x6C - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - no description available - 0 - 2 - read-write - - - INDEX - no description available - 8 - 4 - read-write - - - SIZE - no description available - 24 - 6 - read-write - - - - - PRINCE_REGION1_IV_BODY0 - no description available - PRINCE_REGION1_IV_CODE - 0x70 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE2 - no description available - PRINCE_REGION1_IV_CODE - 0x70 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY1 - no description available - PRINCE_REGION1_IV_CODE - 0x74 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE3 - no description available - PRINCE_REGION1_IV_CODE - 0x74 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY2 - no description available - PRINCE_REGION1_IV_CODE - 0x78 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE4 - no description available - PRINCE_REGION1_IV_CODE - 0x78 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY3 - no description available - PRINCE_REGION1_IV_CODE - 0x7C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE5 - no description available - PRINCE_REGION1_IV_CODE - 0x7C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY4 - no description available - PRINCE_REGION1_IV_CODE - 0x80 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE6 - no description available - PRINCE_REGION1_IV_CODE - 0x80 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY5 - no description available - PRINCE_REGION1_IV_CODE - 0x84 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE7 - no description available - PRINCE_REGION1_IV_CODE - 0x84 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY6 - no description available - PRINCE_REGION1_IV_CODE - 0x88 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE8 - no description available - PRINCE_REGION1_IV_CODE - 0x88 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY7 - no description available - PRINCE_REGION1_IV_CODE - 0x8C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE9 - no description available - PRINCE_REGION1_IV_CODE - 0x8C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY8 - no description available - PRINCE_REGION1_IV_CODE - 0x90 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE10 - no description available - PRINCE_REGION1_IV_CODE - 0x90 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY9 - no description available - PRINCE_REGION1_IV_CODE - 0x94 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE11 - no description available - PRINCE_REGION1_IV_CODE - 0x94 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY10 - no description available - PRINCE_REGION1_IV_CODE - 0x98 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE12 - no description available - PRINCE_REGION1_IV_CODE - 0x98 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY11 - no description available - PRINCE_REGION1_IV_CODE - 0x9C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE13 - no description available - PRINCE_REGION1_IV_CODE - 0x9C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE0 - no description available - PRINCE_REGION2_IV_CODE - 0xA0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_HEADER0 - no description available - PRINCE_REGION2_IV_CODE - 0xA0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE1 - no description available - PRINCE_REGION2_IV_CODE - 0xA4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_HEADER1 - no description available - PRINCE_REGION2_IV_CODE - 0xA4 - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - no description available - 0 - 2 - read-write - - - INDEX - no description available - 8 - 4 - read-write - - - SIZE - no description available - 24 - 6 - read-write - - - - - PRINCE_REGION2_IV_BODY0 - no description available - PRINCE_REGION2_IV_CODE - 0xA8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE2 - no description available - PRINCE_REGION2_IV_CODE - 0xA8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY1 - no description available - PRINCE_REGION2_IV_CODE - 0xAC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE3 - no description available - PRINCE_REGION2_IV_CODE - 0xAC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY2 - no description available - PRINCE_REGION2_IV_CODE - 0xB0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE4 - no description available - PRINCE_REGION2_IV_CODE - 0xB0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY3 - no description available - PRINCE_REGION2_IV_CODE - 0xB4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE5 - no description available - PRINCE_REGION2_IV_CODE - 0xB4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY4 - no description available - PRINCE_REGION2_IV_CODE - 0xB8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE6 - no description available - PRINCE_REGION2_IV_CODE - 0xB8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY5 - no description available - PRINCE_REGION2_IV_CODE - 0xBC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE7 - no description available - PRINCE_REGION2_IV_CODE - 0xBC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY6 - no description available - PRINCE_REGION2_IV_CODE - 0xC0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE8 - no description available - PRINCE_REGION2_IV_CODE - 0xC0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY7 - no description available - PRINCE_REGION2_IV_CODE - 0xC4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE9 - no description available - PRINCE_REGION2_IV_CODE - 0xC4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY8 - no description available - PRINCE_REGION2_IV_CODE - 0xC8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE10 - no description available - PRINCE_REGION2_IV_CODE - 0xC8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY9 - no description available - PRINCE_REGION2_IV_CODE - 0xCC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE11 - no description available - PRINCE_REGION2_IV_CODE - 0xCC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY10 - no description available - PRINCE_REGION2_IV_CODE - 0xD0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE12 - no description available - PRINCE_REGION2_IV_CODE - 0xD0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY11 - no description available - PRINCE_REGION2_IV_CODE - 0xD4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE13 - no description available - PRINCE_REGION2_IV_CODE - 0xD4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - 56 - 0x4 - CUSTOMER_DEFINED[%s] - Customer Defined (Programable through ROM API) - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - 8 - 0x4 - SHA256_DIGEST[%s] - SHA256_DIGESTindex for DIGEST[((index * 32) + 31):(index * 32)] - 0x1E0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - - - FLASH_CFPA_SCRATCH - FLASH_CFPA - FLASH_CFPA - 0x9DE00 - - 0 - 0x200 - registers - - - - FLASH_CFPA1 - FLASH_CFPA - FLASH_CFPA - 0x9E200 - - 0 - 0x200 - registers - - - - FLASH_CMPA - FLASH_CMPA - FLASH_CMPA - 0x9E400 - - 0 - 0x200 - registers - - - - BOOT_CFG - no description available - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - DEFAULT_ISP_MODE - Default ISP mode: - 4 - 3 - read-write - - - AUTO_ISP - Auto ISP - 0 - - - USB_HID_ISP - USB_HID_ISP - 0x1 - - - UART_ISP - UART ISP - 0x2 - - - SPI_ISP - SPI Slave ISP - 0x3 - - - I2C_ISP - I2C Slave ISP - 0x4 - - - DISABLE - Disable ISP fall through - 0x7 - - - - - BOOT_SPEED - Core clock: - 7 - 2 - read-write - - - VALUE_0 - Defined by NMPA.SYSTEM_SPEED_CODE - 0 - - - VALUE_1 - 96MHz FRO - 0x1 - - - VALUE_2 - 48MHz FRO - 0x2 - - - - - BOOT_FAILURE_PIN - GPIO port and pin number to use for indicating failure reason. The toggle rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO pin - 24 - 8 - read-write - - - - - SPI_FLASH_CFG - no description available - 0x4 - 32 - read-write - 0 - 0xFFFFFFFF - - - SPI_RECOVERY_BOOT_EN - SPI flash recovery boot is enabled, if non-zero value is written to this field. - 0 - 5 - read-write - - - - - USB_ID - no description available - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - USB_VENDOR_ID - no description available - 0 - 16 - read-write - - - USB_PRODUCT_ID - no description available - 16 - 16 - read-write - - - - - SDIO_CFG - no description available - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - CC_SOCU_PIN - no description available - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - NIDEN - Non Secure non-invasive debug enable - 0 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - DBGEN - Non Secure debug enable - 1 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - SPNIDEN - Secure non-invasive debug enable - 2 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - SPIDEN - Secure invasive debug enable - 3 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - TAPEN - JTAG TAP enable - 4 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable - 5 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - ISP_CMD_EN - ISP Boot Command enable - 6 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - FA_CMD_EN - FA Command enable - 7 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - ME_CMD_EN - Flash Mass Erase Command enable - 8 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable - 9 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - UUID_CHECK - Enforce UUID match during Debug authentication. - 15 - 1 - read-write - - - INVERSE_VALUE - inverse value of bits [15:0] - 16 - 16 - read-write - - - - - CC_SOCU_DFLT - no description available - 0x14 - 32 - read-write - 0 - 0xFFFFFFFF - - - NIDEN - Non Secure non-invasive debug fixed state - 0 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - DBGEN - Non Secure debug fixed state - 1 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - SPNIDEN - Secure non-invasive debug fixed state - 2 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - SPIDEN - Secure invasive debug fixed state - 3 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - TAPEN - JTAG TAP fixed state - 4 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state - 5 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - ISP_CMD_EN - ISP Boot Command fixed state - 6 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - FA_CMD_EN - FA Command fixed state - 7 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - ME_CMD_EN - Flash Mass Erase Command fixed state - 8 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state - 9 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - INVERSE_VALUE - inverse value of bits [15:0] - 16 - 16 - read-write - - - - - VENDOR_USAGE - no description available - 0x18 - 32 - read-write - 0 - 0xFFFFFFFF - - - VENDOR_USAGE - Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area. - 16 - 16 - read-write - - - - - SECURE_BOOT_CFG - Secure boot configuration flags. - 0x1C - 32 - read-write - 0 - 0xFFFFFFFF - - - RSA4K - Use RSA4096 keys only. - 0 - 2 - read-write - - - VALUE_0 - Allow RSA2048 and higher - 0 - - - VALUE_1 - RSA4096 only - 0x1 - - - VALUE_2 - RSA4096 only - 0x2 - - - VALUE_3 - RSA4096 only - 0x3 - - - - - DICE_INC_NXP_CFG - Include NXP area in DICE computation. - 2 - 2 - read-write - - - NOT_INCLUD - not included - 0 - - - INCLUD - included - 0x1 - - - VALUE_2 - included - 0x2 - - - VALUE_3 - included - 0x3 - - - - - DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. - 4 - 2 - read-write - - - NOT_INCLUD - not included - 0 - - - UNCLUD - included - 0x1 - - - VALUE_2 - included - 0x2 - - - VALUE_3 - included - 0x3 - - - - - SKIP_DICE - Skip DICE computation - 6 - 2 - read-write - - - ENABLE - Enable DICE - 0 - - - DISABLE - Disable DICE - 0x1 - - - VALUE_2 - Disable DICE - 0x2 - - - VALUE_3 - Disable DICE - 0x3 - - - - - TZM_IMAGE_TYPE - TrustZone-M mode - 8 - 2 - read-write - - - VALUE_0 - TZ-M image mode is taken from application image header - 0 - - - VALUE_1 - TZ-M disabled image, boots to non-secure mode - 0x1 - - - VALUE_2 - TZ-M enabled image, boots to secure mode - 0x2 - - - VALUE_3 - TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header - 0x3 - - - - - BLOCK_SET_KEY - Block PUF key code generation - 10 - 2 - read-write - - - ALLOW - Allow PUF Key Code generation - 0 - - - DISABLE - Disable PUF Key Code generation - 0x1 - - - VALUE_2 - Disable PUF Key Code generation - 0x2 - - - VALUE_3 - Disable PUF Key Code generation - 0x3 - - - - - BLOCK_ENROLL - Block PUF enrollement - 12 - 2 - read-write - - - ALLOW - Allow PUF enroll operation - 0 - - - DISABLE - Disable PUF enroll operation - 0x1 - - - VALUE_2 - Disable PUF enroll operation - 0x2 - - - VALUE_3 - Disable PUF enroll operation - 0x3 - - - - - DICE_INC_SEC_EPOCH - Include security EPOCH in DICE - 14 - 2 - read-write - - - SEC_BOOT_EN - Secure boot enable - 30 - 2 - read-write - - - DISABLE - Plain image (internal flash with or without CRC) - 0 - - - ENABLE - Boot signed images. (internal flash, RSA signed) - 0x1 - - - VALUE_2 - Boot signed images. (internal flash, RSA signed) - 0x2 - - - VALUE_3 - Boot signed images. (internal flash, RSA signed) - 0x3 - - - - - - - PRINCE_BASE_ADDR - no description available - 0x20 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADDR0_PRG - Programmable portion of the base address of region 0 - 0 - 4 - read-write - - - ADDR1_PRG - Programmable portion of the base address of region 1 - 4 - 4 - read-write - - - ADDR2_PRG - Programmable portion of the base address of region 2 - 8 - 4 - read-write - - - LOCK_REG0 - Lock PRINCE region0 settings - 18 - 2 - read-write - - - UNLOCK - Region is not locked - 0 - - - LOCK - Region is locked - 0x1 - - - VALUE_2 - Region is locked - 0x2 - - - VALUE_3 - Region is locked - 0x3 - - - - - LOCK_REG1 - Lock PRINCE region1 settings - 20 - 2 - read-write - - - UNLOCK - Region is not locked - 0 - - - LOCK - Region is locked - 0x1 - - - VALUE_2 - Region is locked - 0x2 - - - VALUE_3 - Region is locked - 0x3 - - - - - REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased together - 24 - 2 - read-write - - - DISABLE - Region is disabled - 0 - - - ENABLE - Region is enabled - 0x1 - - - VALUE_2 - Region is enabled - 0x2 - - - VALUE_3 - Region is enabled - 0x3 - - - - - REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased together - 26 - 2 - read-write - - - DISABLE - Region is disabled - 0 - - - ENABLE - Region is enabled - 0x1 - - - VALUE_2 - Region is enabled - 0x2 - - - VALUE_3 - Region is enabled - 0x3 - - - - - REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased together - 28 - 2 - read-write - - - DISABLE - Region is disabled - 0 - - - ENABLE - Region is enabled - 0x1 - - - VALUE_2 - Region is enabled - 0x2 - - - VALUE_3 - Region is enabled - 0x3 - - - - - - - PRINCE_SR_0 - Region 0, sub-region enable - 0x24 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_SR_1 - Region 1, sub-region enable - 0x28 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_SR_2 - Region 2, sub-region enable - 0x2C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - XTAL_32KHZ_CAPABANK_TRIM - Xtal 32kHz capabank triming. - 0x30 - 32 - read-write - 0 - 0xFFFFFFFF - - - TRIM_VALID - XTAL 32kHz capa bank trimmings - 0 - 1 - read-write - - - NOT_TRIM - Capa Bank trimmings not valid. Default trimmings value are used - 0 - - - VALID - Capa Bank trimmings valid - 0x1 - - - - - XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. - 1 - 10 - read-write - - - PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. - 11 - 10 - read-write - - - PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. - 21 - 10 - read-write - - - - - XTAL_16MHZ_CAPABANK_TRIM - Xtal 16MHz capabank triming. - 0x34 - 32 - read-write - 0 - 0xFFFFFFFF - - - TRIM_VALID - XTAL 16MHz capa bank trimmings - 0 - 1 - read-write - - - NOT_TRIM - Capa Bank trimmings not valid. Default trimmings value are used - 0 - - - VALID - Capa Bank trimmings valid - 0x1 - - - - - XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. - 1 - 10 - read-write - - - PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. - 11 - 10 - read-write - - - PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. - 21 - 10 - read-write - - - - - 8 - 0x4 - ROTKH[%s] - ROTKHindex for Root of Trust Keys Table hash[(((7 - index) * 32) + 31):((7 - index) * 32)] - 0x50 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - 56 - 0x4 - CUSTOMER_DEFINED[%s] - Customer Defined (Programable through ROM API) - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - 8 - 0x4 - SHA256_DIGEST[%s] - SHA256_DIGESTindex for DIGEST[((index * 32) + 31):(index * 32)] - 0x1E0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - - - FLASH_KEY_STORE - FLASH_KEY_STORE - FLASH_KEY_STORE - 0x9E600 - - 0 - 0x600 - registers - - - - HEADER - Valid Key Sore Header : 0x95959595 - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - puf_discharge_time_in_ms - puf discharge time in ms. - 0x4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - 298 - 0x4 - ACTIVATION_CODE[%s] - . - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_HEADER0 - . - SBKEY_KEY_CODE - 0x4B0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE0 - . - SBKEY_KEY_CODE - 0x4B0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_HEADER1 - . - SBKEY_KEY_CODE - 0x4B4 - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - . - 0 - 2 - read-write - - - INDEX - . - 8 - 4 - read-write - - - SIZE - . - 24 - 6 - read-write - - - - - SBKEY_KEY_CODE1 - . - SBKEY_KEY_CODE - 0x4B4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY0 - . - SBKEY_KEY_CODE - 0x4B8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE2 - . - SBKEY_KEY_CODE - 0x4B8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY1 - . - SBKEY_KEY_CODE - 0x4BC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE3 - . - SBKEY_KEY_CODE - 0x4BC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY2 - . - SBKEY_KEY_CODE - 0x4C0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE4 - . - SBKEY_KEY_CODE - 0x4C0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY3 - . - SBKEY_KEY_CODE - 0x4C4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE5 - . - SBKEY_KEY_CODE - 0x4C4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY4 - . - SBKEY_KEY_CODE - 0x4C8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE6 - . - SBKEY_KEY_CODE - 0x4C8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY5 - . - SBKEY_KEY_CODE - 0x4CC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE7 - . - SBKEY_KEY_CODE - 0x4CC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY6 - . - SBKEY_KEY_CODE - 0x4D0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE8 - . - SBKEY_KEY_CODE - 0x4D0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY7 - . - SBKEY_KEY_CODE - 0x4D4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE9 - . - SBKEY_KEY_CODE - 0x4D4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY8 - . - SBKEY_KEY_CODE - 0x4D8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE10 - . - SBKEY_KEY_CODE - 0x4D8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY9 - . - SBKEY_KEY_CODE - 0x4DC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE11 - . - SBKEY_KEY_CODE - 0x4DC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY10 - . - SBKEY_KEY_CODE - 0x4E0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE12 - . - SBKEY_KEY_CODE - 0x4E0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY11 - . - SBKEY_KEY_CODE - 0x4E4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE13 - . - SBKEY_KEY_CODE - 0x4E4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_HEADER0 - . - USER_KEK_KEY_CODE - 0x4E8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE0 - . - USER_KEK_KEY_CODE - 0x4E8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_HEADER1 - . - USER_KEK_KEY_CODE - 0x4EC - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - . - 0 - 2 - read-write - - - INDEX - . - 8 - 4 - read-write - - - SIZE - . - 24 - 6 - read-write - - - - - USER_KEK_KEY_CODE1 - . - USER_KEK_KEY_CODE - 0x4EC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY0 - . - USER_KEK_KEY_CODE - 0x4F0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE2 - . - USER_KEK_KEY_CODE - 0x4F0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY1 - . - USER_KEK_KEY_CODE - 0x4F4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE3 - . - USER_KEK_KEY_CODE - 0x4F4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY2 - . - USER_KEK_KEY_CODE - 0x4F8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE4 - . - USER_KEK_KEY_CODE - 0x4F8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY3 - . - USER_KEK_KEY_CODE - 0x4FC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE5 - . - USER_KEK_KEY_CODE - 0x4FC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY4 - . - USER_KEK_KEY_CODE - 0x500 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE6 - . - USER_KEK_KEY_CODE - 0x500 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY5 - . - USER_KEK_KEY_CODE - 0x504 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE7 - . - USER_KEK_KEY_CODE - 0x504 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY6 - . - USER_KEK_KEY_CODE - 0x508 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE8 - . - USER_KEK_KEY_CODE - 0x508 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY7 - . - USER_KEK_KEY_CODE - 0x50C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE9 - . - USER_KEK_KEY_CODE - 0x50C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY8 - . - USER_KEK_KEY_CODE - 0x510 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE10 - . - USER_KEK_KEY_CODE - 0x510 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY9 - . - USER_KEK_KEY_CODE - 0x514 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE11 - . - USER_KEK_KEY_CODE - 0x514 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY10 - . - USER_KEK_KEY_CODE - 0x518 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE12 - . - USER_KEK_KEY_CODE - 0x518 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY11 - . - USER_KEK_KEY_CODE - 0x51C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE13 - . - USER_KEK_KEY_CODE - 0x51C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_HEADER0 - . - UDS_KEY_CODE - 0x520 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE0 - . - UDS_KEY_CODE - 0x520 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_HEADER1 - . - UDS_KEY_CODE - 0x524 - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - . - 0 - 2 - read-write - - - INDEX - . - 8 - 4 - read-write - - - SIZE - . - 24 - 6 - read-write - - - - - UDS_KEY_CODE1 - . - UDS_KEY_CODE - 0x524 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY0 - . - UDS_KEY_CODE - 0x528 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE2 - . - UDS_KEY_CODE - 0x528 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY1 - . - UDS_KEY_CODE - 0x52C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE3 - . - UDS_KEY_CODE - 0x52C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY2 - . - UDS_KEY_CODE - 0x530 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE4 - . - UDS_KEY_CODE - 0x530 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY3 - . - UDS_KEY_CODE - 0x534 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE5 - . - UDS_KEY_CODE - 0x534 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY4 - . - UDS_KEY_CODE - 0x538 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE6 - . - UDS_KEY_CODE - 0x538 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY5 - . - UDS_KEY_CODE - 0x53C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE7 - . - UDS_KEY_CODE - 0x53C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY6 - . - UDS_KEY_CODE - 0x540 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE8 - . - UDS_KEY_CODE - 0x540 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY7 - . - UDS_KEY_CODE - 0x544 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE9 - . - UDS_KEY_CODE - 0x544 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY8 - . - UDS_KEY_CODE - 0x548 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE10 - . - UDS_KEY_CODE - 0x548 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY9 - . - UDS_KEY_CODE - 0x54C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE11 - . - UDS_KEY_CODE - 0x54C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY10 - . - UDS_KEY_CODE - 0x550 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE12 - . - UDS_KEY_CODE - 0x550 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY11 - . - UDS_KEY_CODE - 0x554 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE13 - . - UDS_KEY_CODE - 0x554 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_HEADER0 - . - PRINCE_REGION0_KEY_CODE - 0x558 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE0 - . - PRINCE_REGION0_KEY_CODE - 0x558 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_HEADER1 - . - PRINCE_REGION0_KEY_CODE - 0x55C - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - . - 0 - 2 - read-write - - - INDEX - . - 8 - 4 - read-write - - - SIZE - . - 24 - 6 - read-write - - - - - PRINCE_REGION0_KEY_CODE1 - . - PRINCE_REGION0_KEY_CODE - 0x55C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY0 - . - PRINCE_REGION0_KEY_CODE - 0x560 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE2 - . - PRINCE_REGION0_KEY_CODE - 0x560 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY1 - . - PRINCE_REGION0_KEY_CODE - 0x564 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE3 - . - PRINCE_REGION0_KEY_CODE - 0x564 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY2 - . - PRINCE_REGION0_KEY_CODE - 0x568 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE4 - . - PRINCE_REGION0_KEY_CODE - 0x568 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY3 - . - PRINCE_REGION0_KEY_CODE - 0x56C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE5 - . - PRINCE_REGION0_KEY_CODE - 0x56C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY4 - . - PRINCE_REGION0_KEY_CODE - 0x570 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE6 - . - PRINCE_REGION0_KEY_CODE - 0x570 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY5 - . - PRINCE_REGION0_KEY_CODE - 0x574 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE7 - . - PRINCE_REGION0_KEY_CODE - 0x574 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY6 - . - PRINCE_REGION0_KEY_CODE - 0x578 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE8 - . - PRINCE_REGION0_KEY_CODE - 0x578 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY7 - . - PRINCE_REGION0_KEY_CODE - 0x57C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE9 - . - PRINCE_REGION0_KEY_CODE - 0x57C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY8 - . - PRINCE_REGION0_KEY_CODE - 0x580 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE10 - . - PRINCE_REGION0_KEY_CODE - 0x580 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY9 - . - PRINCE_REGION0_KEY_CODE - 0x584 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE11 - . - PRINCE_REGION0_KEY_CODE - 0x584 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY10 - . - PRINCE_REGION0_KEY_CODE - 0x588 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE12 - . - PRINCE_REGION0_KEY_CODE - 0x588 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY11 - . - PRINCE_REGION0_KEY_CODE - 0x58C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE13 - . - PRINCE_REGION0_KEY_CODE - 0x58C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_HEADER0 - . - PRINCE_REGION1_KEY_CODE - 0x590 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE0 - . - PRINCE_REGION1_KEY_CODE - 0x590 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_HEADER1 - . - PRINCE_REGION1_KEY_CODE - 0x594 - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - . - 0 - 2 - read-write - - - INDEX - . - 8 - 4 - read-write - - - SIZE - . - 24 - 6 - read-write - - - - - PRINCE_REGION1_KEY_CODE1 - . - PRINCE_REGION1_KEY_CODE - 0x594 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY0 - . - PRINCE_REGION1_KEY_CODE - 0x598 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE2 - . - PRINCE_REGION1_KEY_CODE - 0x598 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY1 - . - PRINCE_REGION1_KEY_CODE - 0x59C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE3 - . - PRINCE_REGION1_KEY_CODE - 0x59C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY2 - . - PRINCE_REGION1_KEY_CODE - 0x5A0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE4 - . - PRINCE_REGION1_KEY_CODE - 0x5A0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY3 - . - PRINCE_REGION1_KEY_CODE - 0x5A4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE5 - . - PRINCE_REGION1_KEY_CODE - 0x5A4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY4 - . - PRINCE_REGION1_KEY_CODE - 0x5A8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE6 - . - PRINCE_REGION1_KEY_CODE - 0x5A8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY5 - . - PRINCE_REGION1_KEY_CODE - 0x5AC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE7 - . - PRINCE_REGION1_KEY_CODE - 0x5AC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY6 - . - PRINCE_REGION1_KEY_CODE - 0x5B0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE8 - . - PRINCE_REGION1_KEY_CODE - 0x5B0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY7 - . - PRINCE_REGION1_KEY_CODE - 0x5B4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE9 - . - PRINCE_REGION1_KEY_CODE - 0x5B4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY8 - . - PRINCE_REGION1_KEY_CODE - 0x5B8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE10 - . - PRINCE_REGION1_KEY_CODE - 0x5B8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY9 - . - PRINCE_REGION1_KEY_CODE - 0x5BC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE11 - . - PRINCE_REGION1_KEY_CODE - 0x5BC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY10 - . - PRINCE_REGION1_KEY_CODE - 0x5C0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE12 - . - PRINCE_REGION1_KEY_CODE - 0x5C0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY11 - . - PRINCE_REGION1_KEY_CODE - 0x5C4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE13 - . - PRINCE_REGION1_KEY_CODE - 0x5C4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_HEADER0 - . - PRINCE_REGION2_KEY_CODE - 0x5C8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE0 - . - PRINCE_REGION2_KEY_CODE - 0x5C8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_HEADER1 - . - PRINCE_REGION2_KEY_CODE - 0x5CC - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - . - 0 - 2 - read-write - - - INDEX - . - 8 - 4 - read-write - - - SIZE - . - 24 - 6 - read-write - - - - - PRINCE_REGION2_KEY_CODE1 - . - PRINCE_REGION2_KEY_CODE - 0x5CC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY0 - . - PRINCE_REGION2_KEY_CODE - 0x5D0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE2 - . - PRINCE_REGION2_KEY_CODE - 0x5D0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY1 - . - PRINCE_REGION2_KEY_CODE - 0x5D4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE3 - . - PRINCE_REGION2_KEY_CODE - 0x5D4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY2 - . - PRINCE_REGION2_KEY_CODE - 0x5D8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE4 - . - PRINCE_REGION2_KEY_CODE - 0x5D8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY3 - . - PRINCE_REGION2_KEY_CODE - 0x5DC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE5 - . - PRINCE_REGION2_KEY_CODE - 0x5DC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY4 - . - PRINCE_REGION2_KEY_CODE - 0x5E0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE6 - . - PRINCE_REGION2_KEY_CODE - 0x5E0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY5 - . - PRINCE_REGION2_KEY_CODE - 0x5E4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE7 - . - PRINCE_REGION2_KEY_CODE - 0x5E4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY6 - . - PRINCE_REGION2_KEY_CODE - 0x5E8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE8 - . - PRINCE_REGION2_KEY_CODE - 0x5E8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY7 - . - PRINCE_REGION2_KEY_CODE - 0x5EC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE9 - . - PRINCE_REGION2_KEY_CODE - 0x5EC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY8 - . - PRINCE_REGION2_KEY_CODE - 0x5F0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE10 - . - PRINCE_REGION2_KEY_CODE - 0x5F0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY9 - . - PRINCE_REGION2_KEY_CODE - 0x5F4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE11 - . - PRINCE_REGION2_KEY_CODE - 0x5F4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY10 - . - PRINCE_REGION2_KEY_CODE - 0x5F8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE12 - . - PRINCE_REGION2_KEY_CODE - 0x5F8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY11 - . - PRINCE_REGION2_KEY_CODE - 0x5FC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE13 - . - PRINCE_REGION2_KEY_CODE - 0x5FC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - - - SYSCON - SYSCON - SYSCON - 0x40000000 - - 0 - 0x1000 - registers - - - - MEMORYREMAP - Memory Remap control register - 0 - 32 - read-write - 0 - 0x3 - - - MAP - Select the location of the vector table :. - 0 - 2 - read-write - - - ROM0 - Vector Table in ROM. - 0 - - - RAM1 - Vector Table in RAM. - 0x1 - - - FLASH0 - Vector Table in Flash. - 0x2 - - - FLASH1 - Vector Table in Flash. - 0x3 - - - - - - - AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest - 0x10 - 32 - read-write - 0 - 0x3FFFFFF - - - PRI_CPU0_CBUS - CPU0 C-AHB bus. - 0 - 2 - read-write - - - PRI_CPU0_SBUS - CPU0 S-AHB bus. - 2 - 2 - read-write - - - PRI_CPU1_CBUS - CPU1 C-AHB bus. - 4 - 2 - read-write - - - PRI_CPU1_SBUS - CPU1 S-AHB bus. - 6 - 2 - read-write - - - PRI_USB_FS - USB-FS.(USB0) - 8 - 2 - read-write - - - PRI_SDMA0 - DMA0 controller priority. - 10 - 2 - read-write - - - PRI_SDIO - SDIO. - 16 - 2 - read-write - - - PRI_PQ - PQ (HW Accelerator). - 18 - 2 - read-write - - - PRI_HASH_AES - HASH_AES. - 20 - 2 - read-write - - - PRI_USB_HS - USB-HS.(USB1) - 22 - 2 - read-write - - - PRI_SDMA1 - DMA1 controller priority. - 24 - 2 - read-write - - - - - CPU0STCKCAL - System tick calibration for secure part of CPU0 - 0x38 - 32 - read-write - 0 - 0x3FFFFFF - - - TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. - 0 - 24 - read-write - - - SKEW - Initial value for the Systick timer. - 24 - 1 - read-write - - - NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference clock provided; 1 = no reference clock provided. - 25 - 1 - read-write - - - - - CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 - 0x3C - 32 - read-write - 0 - 0x3FFFFFF - - - TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. - 0 - 24 - read-write - - - SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. - 24 - 1 - read-write - - - NOREF - Initial value for the Systick timer. - 25 - 1 - read-write - - - - - CPU1STCKCAL - System tick calibration for CPU1 - 0x40 - 32 - read-write - 0 - 0x3FFFFFF - - - TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. - 0 - 24 - read-write - - - SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. - 24 - 1 - read-write - - - NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference clock provided; 1 = no reference clock provided. - 25 - 1 - read-write - - - - - NMISRC - NMI Source Select - 0x48 - 32 - read-write - 0 - 0xC0003F3F - - - IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0. - 0 - 6 - read-write - - - IRQCPU1 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1, if enabled by NMIENCPU1. - 8 - 6 - read-write - - - NMIENCPU1 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU1. - 30 - 1 - read-write - - - NMIENCPU0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. - 31 - 1 - read-write - - - - - PRESETCTRL0 - Peripheral reset control 0 - PRESETCTRL - 0x100 - 32 - read-write - 0 - 0xCFFE9FA - - - ROM_RST - ROM reset control. - 1 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SRAM_CTRL1_RST - SRAM Controller 1 reset control. - 3 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SRAM_CTRL2_RST - SRAM Controller 2 reset control. - 4 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SRAM_CTRL3_RST - SRAM Controller 3 reset control. - 5 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SRAM_CTRL4_RST - SRAM Controller 4 reset control. - 6 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FLASH_RST - Flash controller reset control. - 7 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FMC_RST - FMC controller reset control. - 8 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - MUX_RST - Input Mux reset control. - 11 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - IOCON_RST - I/O controller reset control. - 13 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GPIO0_RST - GPIO0 reset control. - 14 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GPIO1_RST - GPIO1 reset control. - 15 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GPIO2_RST - GPIO2 reset control. - 16 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GPIO3_RST - GPIO3 reset control. - 17 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - PINT_RST - Pin interrupt (PINT) reset control. - 18 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GINT_RST - Group interrupt (GINT) reset control. - 19 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - DMA0_RST - DMA0 reset control. - 20 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - CRCGEN_RST - CRCGEN reset control. - 21 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - WWDT_RST - Watchdog Timer reset control. - 22 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - RTC_RST - Real Time Clock (RTC) reset control. - 23 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - MAILBOX_RST - Inter CPU communication Mailbox reset control. - 26 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - ADC_RST - ADC reset control. - 27 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - - - PRESETCTRLX0 - Peripheral reset control register - PRESETCTRL - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - PRESETCTRL1 - Peripheral reset control 1 - PRESETCTRL - 0x104 - 32 - read-write - 0 - 0xDE57FC47 - - - MRT_RST - MRT reset control. - 0 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - OSTIMER_RST - OS Event Timer reset control. - 1 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SCT_RST - SCT reset control. - 2 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SCTIPU_RST - SCTIPU reset control. - 6 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - UTICK_RST - UTICK reset control. - 10 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC0_RST - FC0 reset control. - 11 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC1_RST - FC1 reset control. - 12 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC2_RST - FC2 reset control. - 13 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC3_RST - FC3 reset control. - 14 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC4_RST - FC4 reset control. - 15 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC5_RST - FC5 reset control. - 16 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC6_RST - FC6 reset control. - 17 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC7_RST - FC7 reset control. - 18 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - TIMER2_RST - Timer 2 reset control. - 22 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - USB0_DEV_RST - USB0 DEV reset control. - 25 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - TIMER0_RST - Timer 0 reset control. - 26 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - TIMER1_RST - Timer 1 reset control. - 27 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - - - PRESETCTRLX1 - Peripheral reset control register - PRESETCTRL - 0x104 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - PRESETCTRL2 - Peripheral reset control 2 - PRESETCTRL - 0x108 - 32 - read-write - 0 - 0x7FFF77FE - - - DMA1_RST - DMA1 reset control. - 1 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - COMP_RST - Comparator reset control. - 2 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SDIO_RST - SDIO reset control. - 3 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - USB1_HOST_RST - USB1 Host reset control. - 4 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - USB1_DEV_RST - USB1 dev reset control. - 5 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - USB1_RAM_RST - USB1 RAM reset control. - 6 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - USB1_PHY_RST - USB1 PHY reset control. - 7 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FREQME_RST - Frequency meter reset control. - 8 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - RNG_RST - RNG reset control. - 13 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SYSCTL_RST - SYSCTL Block reset. - 15 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - USB0_HOSTM_RST - USB0 Host Master reset control. - 16 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - USB0_HOSTS_RST - USB0 Host Slave reset control. - 17 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - HASH_AES_RST - HASH_AES reset control. - 18 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - PQ_RST - Power Quad reset control. - 19 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - PLULUT_RST - PLU LUT reset control. - 20 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - TIMER3_RST - Timer 3 reset control. - 21 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - TIMER4_RST - Timer 4 reset control. - 22 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - PUF_RST - PUF reset control reset control. - 23 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - CASPER_RST - Casper reset control. - 24 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - ANALOG_CTRL_RST - analog control reset control. - 27 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - HS_LSPI_RST - HS LSPI reset control. - 28 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GPIO_SEC_RST - GPIO secure reset control. - 29 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GPIO_SEC_INT_RST - GPIO secure int reset control. - 30 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - - - PRESETCTRLX2 - Peripheral reset control register - PRESETCTRL - 0x108 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - 3 - 0x4 - PRESETCTRLSET[%s] - Peripheral reset control set register - 0x120 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - 3 - 0x4 - PRESETCTRLCLR[%s] - Peripheral reset control clear register - 0x140 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - SWR_RESET - generate a software_reset - 0x160 - 32 - write-only - 0 - 0xFFFFFFFF - - - SWR_RESET - Write 0x5A00_0001 to generate a software_reset. - 0 - 32 - write-only - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Generate a software reset. - 0x5A000001 - - - - - - - AHBCLKCTRL0 - AHB Clock control 0 - AHBCLKCTRL - 0x200 - 32 - read-write - 0x180 - 0xCFFE9FA - - - ROM - Enables the clock for the ROM. - 1 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. - 3 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. - 4 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - SRAM_CTRL3 - Enables the clock for the SRAM Controller 3. - 5 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - SRAM_CTRL4 - Enables the clock for the SRAM Controller 4. - 6 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FLASH - Enables the clock for the Flash controller. - 7 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FMC - Enables the clock for the FMC controller. - 8 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - MUX - Enables the clock for the Input Mux. - 11 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - IOCON - Enables the clock for the I/O controller. - 13 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GPIO0 - Enables the clock for the GPIO0. - 14 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GPIO1 - Enables the clock for the GPIO1. - 15 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GPIO2 - Enables the clock for the GPIO2. - 16 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GPIO3 - Enables the clock for the GPIO3. - 17 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - PINT - Enables the clock for the Pin interrupt (PINT). - 18 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GINT - Enables the clock for the Group interrupt (GINT). - 19 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - DMA0 - Enables the clock for the DMA0. - 20 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - CRCGEN - Enables the clock for the CRCGEN. - 21 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - WWDT - Enables the clock for the Watchdog Timer. - 22 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - RTC - Enables the clock for the Real Time Clock (RTC). - 23 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - MAILBOX - Enables the clock for the Inter CPU communication Mailbox. - 26 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - ADC - Enables the clock for the ADC. - 27 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - - - AHBCLKCTRLX0 - Peripheral reset control register - AHBCLKCTRL - 0x200 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - AHBCLKCTRL1 - AHB Clock control 1 - AHBCLKCTRL - 0x204 - 32 - read-write - 0 - 0xDE57FC47 - - - MRT - Enables the clock for the MRT. - 0 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - OSTIMER - Enables the clock for the OS Event Timer. - 1 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - SCT - Enables the clock for the SCT. - 2 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - UTICK - Enables the clock for the UTICK. - 10 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC0 - Enables the clock for the FC0. - 11 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC1 - Enables the clock for the FC1. - 12 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC2 - Enables the clock for the FC2. - 13 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC3 - Enables the clock for the FC3. - 14 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC4 - Enables the clock for the FC4. - 15 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC5 - Enables the clock for the FC5. - 16 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC6 - Enables the clock for the FC6. - 17 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC7 - Enables the clock for the FC7. - 18 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - TIMER2 - Enables the clock for the Timer 2. - 22 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - USB0_DEV - Enables the clock for the USB0 DEV. - 25 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - TIMER0 - Enables the clock for the Timer 0. - 26 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - TIMER1 - Enables the clock for the Timer 1. - 27 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - - - AHBCLKCTRLX1 - Peripheral reset control register - AHBCLKCTRL - 0x204 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - AHBCLKCTRL2 - AHB Clock control 2 - AHBCLKCTRL - 0x208 - 32 - read-write - 0 - 0x7FFF77FE - - - DMA1 - Enables the clock for the DMA1. - 1 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - COMP - Enables the clock for the Comparator. - 2 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - SDIO - Enables the clock for the SDIO. - 3 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - USB1_HOST - Enables the clock for the USB1 Host. - 4 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - USB1_DEV - Enables the clock for the USB1 dev. - 5 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - USB1_RAM - Enables the clock for the USB1 RAM. - 6 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - USB1_PHY - Enables the clock for the USB1 PHY. - 7 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FREQME - Enables the clock for the Frequency meter. - 8 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - RNG - Enables the clock for the RNG. - 13 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - SYSCTL - SYSCTL block clock. - 15 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - USB0_HOSTM - Enables the clock for the USB0 Host Master. - 16 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - USB0_HOSTS - Enables the clock for the USB0 Host Slave. - 17 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - HASH_AES - Enables the clock for the HASH_AES. - 18 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - PQ - Enables the clock for the Power Quad. - 19 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - PLULUT - Enables the clock for the PLU LUT. - 20 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - TIMER3 - Enables the clock for the Timer 3. - 21 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - TIMER4 - Enables the clock for the Timer 4. - 22 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - PUF - Enables the clock for the PUF reset control. - 23 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - CASPER - Enables the clock for the Casper. - 24 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - ANALOG_CTRL - Enables the clock for the analog control. - 27 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - HS_LSPI - Enables the clock for the HS LSPI. - 28 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GPIO_SEC - Enables the clock for the GPIO secure. - 29 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GPIO_SEC_INT - Enables the clock for the GPIO secure int. - 30 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - - - AHBCLKCTRLX2 - Peripheral reset control register - AHBCLKCTRL - 0x208 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - 3 - 0x4 - AHBCLKCTRLSET[%s] - Peripheral reset control register - 0x220 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - 3 - 0x4 - AHBCLKCTRLCLR[%s] - Peripheral reset control register - 0x240 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select - SYSTICKCLKSEL - 0x260 - 32 - read-write - 0x7 - 0x7 - - - SEL - System Tick Timer for CPU0 source select. - 0 - 3 - read-write - - - ENUM_0x0 - System Tick 0 divided clock. - 0 - - - ENUM_0x1 - FRO 1MHz clock. - 0x1 - - - ENUM_0x2 - Oscillator 32 kHz clock. - 0x2 - - - ENUM_0x3 - No clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - SYSTICKCLKSELX0 - Peripheral reset control register - SYSTICKCLKSEL - 0x260 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - SYSTICKCLKSEL1 - System Tick Timer for CPU1 source select - SYSTICKCLKSEL - 0x264 - 32 - read-write - 0x7 - 0x7 - - - SEL - System Tick Timer for CPU1 source select. - 0 - 3 - read-write - - - ENUM_0x0 - System Tick 1 divided clock. - 0 - - - ENUM_0x1 - FRO 1MHz clock. - 0x1 - - - ENUM_0x2 - Oscillator 32 kHz clock. - 0x2 - - - ENUM_0x3 - No clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - SYSTICKCLKSELX1 - Peripheral reset control register - SYSTICKCLKSEL - 0x264 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - TRACECLKSEL - Trace clock source select - 0x268 - 32 - read-write - 0x7 - 0x7 - - - SEL - Trace clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Trace divided clock. - 0 - - - ENUM_0x1 - FRO 1MHz clock. - 0x1 - - - ENUM_0x2 - Oscillator 32 kHz clock. - 0x2 - - - ENUM_0x3 - No clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - CTIMERCLKSEL0 - CTimer 0 clock source select - CTIMERCLKSEL - 0x26C - 32 - read-write - 0x7 - 0x7 - - - SEL - CTimer 0 clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - CTIMERCLKSELX0 - Peripheral reset control register - CTIMERCLKSEL - 0x26C - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - CTIMERCLKSEL1 - CTimer 1 clock source select - CTIMERCLKSEL - 0x270 - 32 - read-write - 0x7 - 0x7 - - - SEL - CTimer 1 clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - CTIMERCLKSELX1 - Peripheral reset control register - CTIMERCLKSEL - 0x270 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - CTIMERCLKSEL2 - CTimer 2 clock source select - CTIMERCLKSEL - 0x274 - 32 - read-write - 0x7 - 0x7 - - - SEL - CTimer 2 clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - CTIMERCLKSELX2 - Peripheral reset control register - CTIMERCLKSEL - 0x274 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - CTIMERCLKSEL3 - CTimer 3 clock source select - CTIMERCLKSEL - 0x278 - 32 - read-write - 0x7 - 0x7 - - - SEL - CTimer 3 clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - CTIMERCLKSELX3 - Peripheral reset control register - CTIMERCLKSEL - 0x278 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - CTIMERCLKSEL4 - CTimer 4 clock source select - CTIMERCLKSEL - 0x27C - 32 - read-write - 0x7 - 0x7 - - - SEL - CTimer 4 clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - CTIMERCLKSELX4 - Peripheral reset control register - CTIMERCLKSEL - 0x27C - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - MAINCLKSELA - Main clock A source select - 0x280 - 32 - read-write - 0 - 0x7 - - - SEL - Main clock A source select. - 0 - 3 - read-write - - - ENUM_0x0 - FRO 12 MHz clock. - 0 - - - ENUM_0x1 - CLKIN clock. - 0x1 - - - ENUM_0x2 - FRO 1MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - - - - - MAINCLKSELB - Main clock source select - 0x284 - 32 - read-write - 0 - 0x7 - - - SEL - Main clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main Clock A. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - PLL1 clock. - 0x2 - - - ENUM_0x3 - Oscillator 32 kHz clock. - 0x3 - - - - - - - CLKOUTSEL - CLKOUT clock source select - 0x288 - 32 - read-write - 0x7 - 0x7 - - - SEL - CLKOUT clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - CLKIN clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - PLL1 clock. - 0x5 - - - ENUM_0x6 - Oscillator 32kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - PLL0CLKSEL - PLL0 clock source select - 0x290 - 32 - read-write - 0x7 - 0x7 - - - SEL - PLL0 clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - FRO 12 MHz clock. - 0 - - - ENUM_0x1 - CLKIN clock. - 0x1 - - - ENUM_0x2 - FRO 1MHz clock. - 0x2 - - - ENUM_0x3 - Oscillator 32kHz clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - PLL1CLKSEL - PLL1 clock source select - 0x294 - 32 - read-write - 0x7 - 0x7 - - - SEL - PLL1 clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - FRO 12 MHz clock. - 0 - - - ENUM_0x1 - CLKIN clock. - 0x1 - - - ENUM_0x2 - FRO 1MHz clock. - 0x2 - - - ENUM_0x3 - Oscillator 32kHz clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - ADCCLKSEL - ADC clock source select - 0x2A4 - 32 - read-write - 0x7 - 0x7 - - - SEL - ADC clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - FRO 96 MHz clock. - 0x2 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - USB0CLKSEL - FS USB clock source select - 0x2A8 - 32 - read-write - 0x7 - 0x7 - - - SEL - FS USB clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - PLL1 clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2B0 - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX0 - Peripheral reset control register - FCCLKSEL - 0x2B0 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2B4 - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX1 - Peripheral reset control register - FCCLKSEL - 0x2B4 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2B8 - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX2 - Peripheral reset control register - FCCLKSEL - 0x2B8 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2BC - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX3 - Peripheral reset control register - FCCLKSEL - 0x2BC - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2C0 - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX4 - Peripheral reset control register - FCCLKSEL - 0x2C0 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2C4 - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX5 - Peripheral reset control register - FCCLKSEL - 0x2C4 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2C8 - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX6 - Peripheral reset control register - FCCLKSEL - 0x2C8 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2CC - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX7 - Peripheral reset control register - FCCLKSEL - 0x2CC - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - HSLSPICLKSEL - HS LSPI clock source select - 0x2D0 - 32 - read-write - 0x7 - 0x7 - - - SEL - HS LSPI clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - MCLKCLKSEL - MCLK clock source select - 0x2E0 - 32 - read-write - 0x7 - 0x7 - - - SEL - MCLK clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - FRO 96 MHz clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - SCTCLKSEL - SCTimer/PWM clock source select - 0x2F0 - 32 - read-write - 0x7 - 0x7 - - - SEL - SCTimer/PWM clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - CLKIN clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - SDIOCLKSEL - SDIO clock source select - 0x2F8 - 32 - read-write - 0x7 - 0x7 - - - SEL - SDIO clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - PLL1 clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 - 0x300 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - SYSTICKCLKDIV1 - System Tick Timer divider for CPU1 - 0x304 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - TRACECLKDIV - TRACE clock divider - 0x308 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 - FLEXFRGCTRL - 0x320 - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL0 - Peripheral reset control register - FLEXFRGCTRL - 0x320 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 - FLEXFRGCTRL - 0x324 - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL1 - Peripheral reset control register - FLEXFRGCTRL - 0x324 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 - FLEXFRGCTRL - 0x328 - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL2 - Peripheral reset control register - FLEXFRGCTRL - 0x328 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 - FLEXFRGCTRL - 0x32C - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL3 - Peripheral reset control register - FLEXFRGCTRL - 0x32C - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 - FLEXFRGCTRL - 0x330 - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL4 - Peripheral reset control register - FLEXFRGCTRL - 0x330 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 - FLEXFRGCTRL - 0x334 - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL5 - Peripheral reset control register - FLEXFRGCTRL - 0x334 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 - FLEXFRGCTRL - 0x338 - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL6 - Peripheral reset control register - FLEXFRGCTRL - 0x338 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 - FLEXFRGCTRL - 0x33C - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL7 - Peripheral reset control register - FLEXFRGCTRL - 0x33C - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - AHBCLKDIV - System clock divider - 0x380 - 32 - read-write - 0 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - CLKOUTDIV - CLKOUT clock divider - 0x384 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - FROHFDIV - FRO_HF (96MHz) clock divider - 0x388 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - WDTCLKDIV - WDT clock divider - 0x38C - 32 - read-write - 0x40000000 - 0xE000003F - - - DIV - Clock divider value. - 0 - 6 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - ADCCLKDIV - ADC clock divider - 0x394 - 32 - read-write - 0x40000000 - 0xE0000007 - - - DIV - Clock divider value. - 0 - 3 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - USB0CLKDIV - USB0 Clock divider - 0x398 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - MCLKDIV - I2S MCLK clock divider - 0x3AC - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - SCTCLKDIV - SCT/PWM clock divider - 0x3B4 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - SDIOCLKDIV - SDIO clock divider - 0x3BC - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - PLL0CLKDIV - PLL0 clock divider - 0x3C4 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) - 0x3FC - 32 - read-write - 0 - 0xFFFFFFFF - - - CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL). - 0 - 32 - read-write - - - FREEZE - all hardware clock configruration are freeze. - 0 - - - ENABLE - update all clock configuration. - 0x1 - - - - - - - FMCCR - FMC configuration register - 0x400 - 32 - read-write - 0x2000 - 0xFFFFFFFF - - - FETCHCFG - Instruction fetch configuration. - 0 - 2 - read-write - - - NOBUF - Instruction fetches from flash are not buffered. - 0 - - - ONEBUF - One buffer is used for all instruction fetches. - 0x1 - - - ALLBUF - All buffers may be used for instruction fetches. - 0x2 - - - - - DATACFG - Data read configuration. - 2 - 2 - read-write - - - NOBUF - Data accesses from flash are not buffered. - 0 - - - ONEBUF - One buffer is used for all data accesses. - 0x1 - - - ALLBUF - All buffers can be used for data accesses. - 0x2 - - - - - ACCEL - Acceleration enable. - 4 - 1 - read-write - - - DISABLE - Flash acceleration is disabled. - 0 - - - ENABLE - Flash acceleration is enabled. - 0x1 - - - - - PREFEN - Prefetch enable. - 5 - 1 - read-write - - - DISABLE - No instruction prefetch is performed. - 0 - - - ENABLE - Instruction prefetch is enabled. - 0x1 - - - - - PREFOVR - Prefetch override. - 6 - 1 - read-write - - - NORMAL - Any previously initiated prefetch will be completed. - 0 - - - OVERRIDE - Any previously initiated prefetch will be aborted, and the next flash line following the current execution address will be prefetched if not already buffered. - 0x1 - - - - - FLASHTIM - Flash memory access time. - 12 - 4 - read-write - - - FLASHTIM0 - 1 system clock flash access time (for system clock rates up to 11 MHz). - 0 - - - FLASHTIM1 - 2 system clocks flash access time (for system clock rates up to 22 MHz). - 0x1 - - - FLASHTIM2 - 3 system clocks flash access time (for system clock rates up to 33 MHz). - 0x2 - - - FLASHTIM3 - 4 system clocks flash access time (for system clock rates up to 44 MHz). - 0x3 - - - FLASHTIM4 - 5 system clocks flash access time (for system clock rates up to 55 MHz). - 0x4 - - - FLASHTIM5 - 6 system clocks flash access time (for system clock rates up to 66 MHz). - 0x5 - - - FLASHTIM6 - 7 system clocks flash access time (for system clock rates up to 77 MHz). - 0x6 - - - FLASHTIM7 - 8 system clocks flash access time (for system clock rates up to 88 MHz). - 0x7 - - - FLASHTIM8 - 9 system clocks flash access time (for system clock rates up to 100 MHz). - 0x8 - - - FLASHTIM9 - 10 system clocks flash access time (for system clock rates up to 115 MHz). - 0x9 - - - FLASHTIM10 - 11 system clocks flash access time (for system clock rates up to 130 MHz). - 0xA - - - FLASHTIM11 - 12 system clocks flash access time (for system clock rates up to 150 MHz). - 0xB - - - - - - - USB0NEEDCLKCTRL - USB0 need clock control - 0x40C - 32 - read-write - 0 - 0x1F - - - AP_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal control:. - 0 - 1 - read-write - - - HW_CTRL - Under hardware control. - 0 - - - FORCED - Forced high. - 0x1 - - - - - POL_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. - 1 - 1 - read-write - - - FALLING - Falling edge of device USB0_NEEDCLK triggers wake-up. - 0 - - - RISING - Rising edge of device USB0_NEEDCLK triggers wake-up. - 0x1 - - - - - AP_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal control:. - 2 - 1 - read-write - - - HW_CTRL - Under hardware control. - 0 - - - FORCED - Forced high. - 0x1 - - - - - POL_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. - 3 - 1 - read-write - - - FALLING - Falling edge of device USB0_NEEDCLK triggers wake-up. - 0 - - - RISING - Rising edge of device USB0_NEEDCLK triggers wake-up. - 0x1 - - - - - - - USB0NEEDCLKSTAT - USB0 need clock status - 0x410 - 32 - read-write - 0 - 0x3 - - - DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal status:. - 0 - 1 - read-only - - - LOW - USB0 Device clock is low. - 0 - - - HIGH - USB0 Device clock is high. - 0x1 - - - - - HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal status:. - 1 - 1 - read-only - - - LOW - USB0 Host clock is low. - 0 - - - HIGH - USB0 Host clock is high. - 0x1 - - - - - - - FMCFLUSH - FMCflush control - 0x41C - 32 - write-only - 0 - 0xFFFFFFFF - - - FLUSH - Flush control - 0 - 1 - write-only - - - NO_FLUSH - No action is performed. - 0 - - - FLUSH - Flush the FMC buffer contents. - 0x1 - - - - - - - MCLKIO - MCLK control - 0x420 - 32 - read-write - 0 - 0xFFFFFFFF - - - MCLKIO - MCLK control. - 0 - 1 - read-write - - - INPUT - input mode. - 0 - - - OUTPUT - output mode. - 0x1 - - - - - - - USB1NEEDCLKCTRL - USB1 need clock control - 0x424 - 32 - read-write - 0x10 - 0x1F - - - AP_HS_DEV_NEEDCLK - USB1 Device need_clock signal control: - 0 - 1 - read-write - - - HW_CTRL - HOST_NEEDCLK is under hardware control. - 0 - - - FORCED - HOST_NEEDCLK is forced high. - 0x1 - - - - - POL_HS_DEV_NEEDCLK - USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt: - 1 - 1 - read-write - - - FALLING - Falling edge of DEV_NEEDCLK triggers wake-up. - 0 - - - RISING - Rising edge of DEV_NEEDCLK triggers wake-up. - 0x1 - - - - - AP_HS_HOST_NEEDCLK - USB1 Host need clock signal control: - 2 - 1 - read-write - - - HW_CTRL - HOST_NEEDCLK is under hardware control. - 0 - - - FORCED - HOST_NEEDCLK is forced high. - 0x1 - - - - - POL_HS_HOST_NEEDCLK - USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. - 3 - 1 - read-write - - - FALLING - Falling edge of HOST_NEEDCLK triggers wake-up. - 0 - - - RISING - Rising edge of HOST_NEEDCLK triggers wake-up. - 0x1 - - - - - HS_DEV_WAKEUP_N - Software override of device controller PHY wake up logic. - 4 - 1 - read-write - - - FORCE_WUP - Forces USB1_PHY to wake-up. - 0 - - - NORMAL_WUP - Normal USB1_PHY behavior. - 0x1 - - - - - - - USB1NEEDCLKSTAT - USB1 need clock status - 0x428 - 32 - read-write - 0 - 0x3 - - - DEV_NEEDCLK - USB1 Device need_clock signal status:. - 0 - 1 - read-only - - - LOW - DEV_NEEDCLK is low. - 0 - - - HIGH - DEV_NEEDCLK is high. - 0x1 - - - - - HOST_NEEDCLK - USB1 Host need_clock signal status:. - 1 - 1 - read-only - - - LOW - HOST_NEEDCLK is low. - 0 - - - HIGH - HOST_NEEDCLK is high. - 0x1 - - - - - - - SDIOCLKCTRL - SDIO CCLKIN phase and delay control - 0x460 - 32 - read-write - 0 - 0x9F9F008F - - - CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in. - 0 - 2 - read-write - - - ENUM_0_DEG - 0 degree shift. - 0 - - - ENUM_90_DEG - 90 degree shift. - 0x1 - - - ENUM_180_DEG - 180 degree shift. - 0x2 - - - ENUM_270_DEG - 270 degree shift. - 0x3 - - - - - CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. - 2 - 2 - read-write - - - ENUM_0_DEG - 0 degree shift. - 0 - - - ENUM_90_DEG - 90 degree shift. - 0x1 - - - ENUM_180_DEG - 180 degree shift. - 0x2 - - - ENUM_270_DEG - 270 degree shift. - 0x3 - - - - - PHASE_ACTIVE - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE. - 7 - 1 - read-write - - - BYPASSED - Bypassed. - 0 - - - PH_SHIFT - Activates phase shift logic. When active, the clock divider is active and phase delays are enabled. - 0x1 - - - - - CCLK_DRV_DELAY - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in. - 16 - 5 - read-write - - - CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field. - 23 - 1 - read-write - - - DISABLE - Disable drive delay. - 0 - - - ENABLE - Enable drive delay. - 0x1 - - - - - CCLK_SAMPLE_DELAY - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. - 24 - 5 - read-write - - - CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. - 31 - 1 - read-write - - - DISABLE - Disables sample delay. - 0 - - - ENABLE - Enables sample delay. - 0x1 - - - - - - - PLL1CTRL - PLL1 550m control - 0x560 - 32 - read-write - 0 - 0x1FFFFFF - - - SELR - Bandwidth select R value. - 0 - 4 - read-write - - - SELI - Bandwidth select I value. - 4 - 6 - read-write - - - SELP - Bandwidth select P value. - 10 - 5 - read-write - - - BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - 15 - 1 - read-write - - - USED - use PLL. - 0 - - - BYPASSED - PLL input clock is sent directly to the PLL output. - 0x1 - - - - - BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - 16 - 1 - read-write - - - USED - use the divide-by-2 divider in the post-divider. - 0 - - - BYPASSED - bypass of the divide-by-2 divider in the post-divider. - 0x1 - - - - - LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. - 17 - 1 - read-write - - - BWDIRECT - control of the bandwidth of the PLL. - 18 - 1 - read-write - - - SYNC - the bandwidth is changed synchronously with the feedback-divider. - 0 - - - DIRECT - modify the bandwidth of the PLL directly. - 0x1 - - - - - BYPASSPREDIV - bypass of the pre-divider. - 19 - 1 - read-write - - - USED - use the pre-divider. - 0 - - - BYPASSED - bypass of the pre-divider. - 0x1 - - - - - BYPASSPOSTDIV - bypass of the post-divider. - 20 - 1 - read-write - - - USED - use the post-divider. - 0 - - - BYPASSED - bypass of the post-divider. - 0x1 - - - - - CLKEN - enable the output clock. - 21 - 1 - read-write - - - DISABLE - Disable the output clock. - 0 - - - ENABLE - Enable the output clock. - 0x1 - - - - - FRMEN - 1: free running mode. - 22 - 1 - read-write - - - FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable. - 23 - 1 - read-write - - - SKEWEN - Skew mode. - 24 - 1 - read-write - - - DISABLE - skewmode is disable. - 0 - - - ENABLE - skewmode is enable. - 0x1 - - - - - - - PLL1STAT - PLL1 550m status - 0x564 - 32 - read-write - 0 - 0x1F - - - LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. - 0 - 1 - read-only - - - PREDIVACK - pre-divider ratio change acknowledge. - 1 - 1 - read-only - - - FEEDDIVACK - feedback divider ratio change acknowledge. - 2 - 1 - read-only - - - POSTDIVACK - post-divider ratio change acknowledge. - 3 - 1 - read-only - - - FRMDET - free running detector output (active high). - 4 - 1 - read-only - - - - - PLL1NDEC - PLL1 550m N divider - 0x568 - 32 - read-write - 0 - 0x1FF - - - NDIV - pre-divider divider ratio (N-divider). - 0 - 8 - read-write - - - NREQ - pre-divider ratio change request. - 8 - 1 - read-write - - - - - PLL1MDEC - PLL1 550m M divider - 0x56C - 32 - read-write - 0 - 0x1FFFF - - - MDIV - feedback divider divider ratio (M-divider). - 0 - 16 - read-write - - - MREQ - feedback ratio change request. - 16 - 1 - read-write - - - - - PLL1PDEC - PLL1 550m P divider - 0x570 - 32 - read-write - 0 - 0x3F - - - PDIV - post-divider divider ratio (P-divider) - 0 - 5 - read-write - - - PREQ - feedback ratio change request. - 5 - 1 - read-write - - - - - PLL0CTRL - PLL0 550m control - 0x580 - 32 - read-write - 0 - 0x1FFFFFF - - - SELR - Bandwidth select R value. - 0 - 4 - read-write - - - SELI - Bandwidth select I value. - 4 - 6 - read-write - - - SELP - Bandwidth select P value. - 10 - 5 - read-write - - - BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - 15 - 1 - read-write - - - USED - use PLL. - 0 - - - BYPASSED - Bypass PLL input clock is sent directly to the PLL output. - 0x1 - - - - - BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - 16 - 1 - read-write - - - USED - use the divide-by-2 divider in the post-divider. - 0 - - - BYPASSED - bypass of the divide-by-2 divider in the post-divider. - 0x1 - - - - - LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. - 17 - 1 - read-write - - - BWDIRECT - Control of the bandwidth of the PLL. - 18 - 1 - read-write - - - SYNC - the bandwidth is changed synchronously with the feedback-divider. - 0 - - - DIRECT - modify the bandwidth of the PLL directly. - 0x1 - - - - - BYPASSPREDIV - bypass of the pre-divider. - 19 - 1 - read-write - - - USED - use the pre-divider. - 0 - - - BYPASSED - bypass of the pre-divider. - 0x1 - - - - - BYPASSPOSTDIV - bypass of the post-divider. - 20 - 1 - read-write - - - USED - use the post-divider. - 0 - - - BYPASSED - bypass of the post-divider. - 0x1 - - - - - CLKEN - enable the output clock. - 21 - 1 - read-write - - - DISABLE - disable the output clock. - 0 - - - ENABLE - enable the output clock. - 0x1 - - - - - FRMEN - free running mode. - 22 - 1 - read-write - - - DISABLE - free running mode is disable. - 0 - - - ENABLE - free running mode is enable. - 0x1 - - - - - FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable. - 23 - 1 - read-write - - - SKEWEN - skew mode. - 24 - 1 - read-write - - - DISABLE - skew mode is disable. - 0 - - - ENABLE - skew mode is enable. - 0x1 - - - - - - - PLL0STAT - PLL0 550m status - 0x584 - 32 - read-write - 0 - 0x1F - - - LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. - 0 - 1 - read-only - - - PREDIVACK - pre-divider ratio change acknowledge. - 1 - 1 - read-only - - - FEEDDIVACK - feedback divider ratio change acknowledge. - 2 - 1 - read-only - - - POSTDIVACK - post-divider ratio change acknowledge. - 3 - 1 - read-only - - - FRMDET - free running detector output (active high). - 4 - 1 - read-only - - - - - PLL0NDEC - PLL0 550m N divider - 0x588 - 32 - read-write - 0 - 0x1FF - - - NDIV - pre-divider divider ratio (N-divider). - 0 - 8 - read-write - - - NREQ - pre-divider ratio change request. - 8 - 1 - read-write - - - - - PLL0PDEC - PLL0 550m P divider - 0x58C - 32 - read-write - 0 - 0x3F - - - PDIV - post-divider divider ratio (P-divider) - 0 - 5 - read-write - - - PREQ - feedback ratio change request. - 5 - 1 - read-write - - - - - PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 - 0x590 - 32 - read-write - 0 - 0xFFFFFFFF - - - MD_LBS - input word of the wrapper bit 31 to 0. - 0 - 32 - read-write - - - - - PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 - 0x594 - 32 - read-write - 0 - 0x1FFFFFFF - - - MD_MBS - input word of the wrapper bit 32. - 0 - 1 - read-write - - - MD_REQ - md change request. - 1 - 1 - read-write - - - MF - programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3. - 2 - 3 - read-write - - - MR - programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1. - 5 - 3 - read-write - - - MC - modulation waveform control Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency spectrum. - 8 - 2 - read-write - - - MDIV_EXT - to select an external mdiv value. - 10 - 16 - read-write - - - MREQ - to select an external mreq value. - 26 - 1 - read-write - - - DITHER - dithering between two modulation frequencies in a random way or in a pseudo random way (white noise), in order to decrease the probability that the modulated waveform will occur with the same phase on a particular point on the screen. - 27 - 1 - read-write - - - SEL_EXT - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext. - 28 - 1 - read-write - - - - - FUNCRETENTIONCTRL - Functional retention control register - 0x704 - 32 - read-write - 0x50C000 - 0xFFFFFF - - - FUNCRETENA - functional retention in power down only. - 0 - 1 - read-write - - - DISABLE - disable functional retention. - 0 - - - ENABLE - enable functional retention. - 0x1 - - - - - RET_START - Start address divided by 4 inside SRAMX bank. - 1 - 13 - read-write - - - RET_LENTH - lenth of Scan chains to save. - 14 - 10 - read-write - - - - - CPUCTRL - CPU Control for multiple processors - 0x800 - 32 - read-write - 0x2C - 0x3D - - - CPU1CLKEN - CPU1 clock enable. - 3 - 1 - read-write - - - DISABLE - The CPU1 clock is not enabled. - 0 - - - ENABLE - The CPU1 clock is enabled. - 0x1 - - - - - CPU1RSTEN - CPU1 reset. - 5 - 1 - read-write - - - RELEASED - The CPU1 is not being reset. - 0 - - - ASSERTED - The CPU1 is being reset. - 0x1 - - - - - - - CPBOOT - Coprocessor Boot Address - 0x804 - 32 - read-write - 0 - 0xFFFFFFFF - - - CPBOOT - Coprocessor Boot Address for CPU1. - 0 - 32 - read-write - - - - - CPSTAT - CPU Status - 0x80C - 32 - read-write - 0 - 0xF - - - CPU0SLEEPING - The CPU0 sleeping state. - 0 - 1 - read-only - - - AWAKE - the CPU is not sleeping. - 0 - - - SLEEPING - the CPU is sleeping. - 0x1 - - - - - CPU1SLEEPING - The CPU1 sleeping state. - 1 - 1 - read-only - - - AWAKE - the CPU is not sleeping. - 0 - - - SLEEPING - the CPU is sleeping. - 0x1 - - - - - CPU0LOCKUP - The CPU0 lockup state. - 2 - 1 - read-only - - - AWAKE - the CPU is not in lockup. - 0 - - - SLEEPING - the CPU is in lockup. - 0x1 - - - - - CPU1LOCKUP - The CPU1 lockup state. - 3 - 1 - read-only - - - AWAKE - the CPU is not in lockup. - 0 - - - SLEEPING - the CPU is in lockup. - 0x1 - - - - - - - CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures - 0xA18 - 32 - read-write - 0x1 - 0x3FF - - - XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. - 1 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. - 2 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. - 3 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. - 4 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - CLKIN_ENA - Enable clock_in clock for clock module. - 5 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. - 6 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. - 7 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration. - 8 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. - 9 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - - - COMP_INT_CTRL - Comparator Interrupt control - 0xB10 - 32 - read-write - 0 - 0x3F - - - INT_ENABLE - Analog Comparator interrupt enable control:. - 0 - 1 - read-write - - - INT_DISABLE - interrupt disable. - 0 - - - INT_ENABLE - interrupt enable. - 0x1 - - - - - INT_CLEAR - Analog Comparator interrupt clear. - 1 - 1 - read-write - - - NONE - No effect. - 0 - - - CLEAR - Clear the interrupt. Self-cleared bit. - 0x1 - - - - - INT_CTRL - Comparator interrupt type selector:. - 2 - 3 - read-write - - - EDGE_DISABLE - The analog comparator interrupt edge sensitive is disabled. - 0 - - - LVL_DISABLE - The analog comparator interrupt level sensitive is disabled. - 0x1 - - - EDGE_RISING - analog comparator interrupt is rising edge sensitive. - 0x2 - - - LVL_HIGH - Analog Comparator interrupt is high level sensitive. - 0x3 - - - EDGE_FALLING - analog comparator interrupt is falling edge sensitive. - 0x4 - - - LVL_LOW - Analog Comparator interrupt is low level sensitive. - 0x5 - - - EDGE_BOTH - analog comparator interrupt is rising and falling edge sensitive. - 0x6 - - - LVL_DIS2 - The analog comparator interrupt level sensitive is disabled. - 0x7 - - - - - INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. - 5 - 1 - read-write - - - FILTER_INT - Select Analog Comparator filtered output as input for interrupt detection. - 0 - - - RAW_INT - Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when Analog comparator is used as wake up source in Power down mode. - 0x1 - - - - - - - COMP_INT_STATUS - Comparator Interrupt status - 0xB14 - 32 - read-write - 0 - 0x7 - - - STATUS - Interrupt status BEFORE Interrupt Enable. - 0 - 1 - read-only - - - NO_INT - no interrupt pending. - 0 - - - PENDING - interrupt pending. - 0x1 - - - - - INT_STATUS - Interrupt status AFTER Interrupt Enable. - 1 - 1 - read-only - - - NO_INT - no interrupt pending. - 0 - - - PENDING - interrupt pending. - 0x1 - - - - - VAL - comparator analog output. - 2 - 1 - read-only - - - SMALLER - P+ is smaller than P-. - 0 - - - GREATER - P+ is greater than P-. - 0x1 - - - - - - - AUTOCLKGATEOVERRIDE - Control automatic clock gating - 0xE04 - 32 - read-write - 0xFFFF - 0xFFFFFFFF - - - ROM - Control automatic clock gating of ROM controller. - 0 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - RAMX_CTRL - Control automatic clock gating of RAMX controller. - 1 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - RAM0_CTRL - Control automatic clock gating of RAM0 controller. - 2 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - RAM1_CTRL - Control automatic clock gating of RAM1 controller. - 3 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - RAM2_CTRL - Control automatic clock gating of RAM2 controller. - 4 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - RAM3_CTRL - Control automatic clock gating of RAM3 controller. - 5 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - RAM4_CTRL - Control automatic clock gating of RAM4 controller. - 6 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. - 7 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. - 8 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - CRCGEN - Control automatic clock gating of CRCGEN controller. - 11 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - SDMA0 - Control automatic clock gating of DMA0 controller. - 12 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - SDMA1 - Control automatic clock gating of DMA1 controller. - 13 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - USB0 - Control automatic clock gating of USB controller. - 14 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - SYSCON - Control automatic clock gating of synchronous system controller registers bank. - 15 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. - 16 - 16 - write-only - - - DISABLE - Bit Fields 0 - 15 of this register are not updated - 0 - - - ENABLE - Bit Fields 0 - 15 of this register are updated - 0xC0DE - - - - - - - GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module - 0xE08 - 32 - read-write - 0 - 0x1 - - - PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module. - 0 - 1 - read-write - - - USED - use the first stage of synchonization inside GPIO_INT module. - 0 - - - BYPASS - bypass of the first stage of synchonization inside GPIO_INT module. - 0x1 - - - - - - - DEBUG_LOCK_EN - Control write access to security registers. - 0xFA0 - 32 - read-write - 0x5 - 0xF - - - LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, CODESECURITYPROTCPU1, CPU0_DEBUG_FEATURES, CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. - 0 - 4 - read-write - - - DISABLE - Any other value than b1010: disable write access to all 6 registers. - 0 - - - ENABLE - 1010: Enable write access to all 6 registers. - 0xA - - - - - - - DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control. - 0xFA4 - 32 - read-write - 0 - 0xFFF - - - CPU0_DBGEN - CPU0 Invasive debug control:. - 0 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU0_NIDEN - CPU0 Non Invasive debug control:. - 2 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU0_SPIDEN - CPU0 Secure Invasive debug control:. - 4 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. - 6 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU1_DBGEN - CPU1 Invasive debug control:. - 8 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU1_NIDEN - CPU1 Non Invasive debug control:. - 10 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - - - DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register. - 0xFA8 - 32 - read-write - 0x555 - 0xFFF - - - CPU0_DBGEN - CPU0 (CPU0) Invasive debug control:. - 0 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU0_NIDEN - CPU0 Non Invasive debug control:. - 2 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU0_SPIDEN - CPU0 Secure Invasive debug control:. - 4 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. - 6 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU1_DBGEN - CPU1 Invasive debug control:. - 8 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU1_NIDEN - CPU1 Non Invasive debug control:. - 10 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - - - KEY_BLOCK - block quiddikey/PUF all index. - 0xFBC - 32 - write-only - 0x3CC35AA5 - 0xFFFFFFFF - - - KEY_BLOCK - Write a value to block quiddikey/PUF all index. - 0 - 32 - write-only - - - - - DEBUG_AUTH_BEACON - Debug authentication BEACON register - 0xFC0 - 32 - read-write - 0 - 0xFFFFFFFF - - - BEACON - Set by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to application code. - 0 - 32 - read-write - - - - - CPUCFG - CPUs configuration register - 0xFD4 - 32 - read-write - 0x2 - 0x7 - - - CPU1ENABLE - Enable CPU1. - 2 - 1 - read-write - - - DISABLE - CPU1 is disable (Processor in reset). - 0 - - - ENABLE - CPU1 is enable. - 0x1 - - - - - - - DEVICE_ID0 - Device ID - 0xFF8 - 32 - read-only - 0 - 0xFFFFFFFF - - - ROM_REV_MINOR - ROM revision. - 20 - 4 - read-only - - - - - DIEID - Chip revision ID and Number - 0xFFC - 32 - read-only - 0x426B0 - 0xFFFFFF - - - REV_ID - Chip Metal Revision ID. - 0 - 4 - read-only - - - MCO_NUM_IN_DIE_ID - Chip Number 0x426B. - 4 - 20 - read-only - - - - - - - IOCON - I/O pin configuration (IOCON) - IOCON - 0x40001000 - - 0 - 0x100 - registers - - - - PIO0_0 - Digital I/O control for port 0 pins PIO0_0 - 0 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_1 - Digital I/O control for port 0 pins PIO0_1 - 0x4 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_2 - Digital I/O control for port 0 pins PIO0_2 - 0x8 - 32 - read-write - 0x110 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_3 - Digital I/O control for port 0 pins PIO0_3 - 0xC - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_4 - Digital I/O control for port 0 pins PIO0_4 - 0x10 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_5 - Digital I/O control for port 0 pins PIO0_5 - 0x14 - 32 - read-write - 0x120 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_6 - Digital I/O control for port 0 pins PIO0_6 - 0x18 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_7 - Digital I/O control for port 0 pins PIO0_7 - 0x1C - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_8 - Digital I/O control for port 0 pins PIO0_8 - 0x20 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_9 - Digital I/O control for port 0 pins PIO0_9 - 0x24 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_10 - Digital I/O control for port 0 pins PIO0_10 - 0x28 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_11 - Digital I/O control for port 0 pins PIO0_11 - 0x2C - 32 - read-write - 0x116 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_12 - Digital I/O control for port 0 pins PIO0_12 - 0x30 - 32 - read-write - 0x126 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_13 - Digital I/O control for port 0 pins PIO0_13 - 0x34 - 32 - read-write - 0x5000 - 0xFFFF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - SSEL - Supply Selection bit. - 11 - 1 - read-write - - - SEL3V3 - 3V3 Signaling in I2C Mode. - 0 - - - SEL1V8 - 1V8 Signaling in I2C Mode. - 0x1 - - - - - FILTEROFF - Controls input glitch filter. - 12 - 1 - read-write - - - ENABLED - Filter enabled. - 0 - - - DISABLED - Filter disabled. - 0x1 - - - - - ECS - Pull-up current source enable in I2C mode. - 13 - 1 - read-write - - - DISABLED - Disabled. IO is in open drain cell. - 0 - - - ENABLED - Enabled. Pull resistor is conencted. - 0x1 - - - - - EGP - Switch between GPIO mode and I2C mode. - 14 - 1 - read-write - - - I2C_MODE - I2C mode. - 0 - - - GPIO_MODE - GPIO mode. - 0x1 - - - - - I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. - 15 - 1 - read-write - - - FAST_MODE - I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. - 0 - - - STANDARD_MODE - I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. - 0x1 - - - - - - - PIO0_14 - Digital I/O control for port 0 pins PIO0_14 - 0x38 - 32 - read-write - 0x5000 - 0xFFFF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - SSEL - Supply Selection bit. - 11 - 1 - read-write - - - SEL3V3 - 3V3 Signaling in I2C Mode. - 0 - - - SEL1V8 - 1V8 Signaling in I2C Mode. - 0x1 - - - - - FILTEROFF - Controls input glitch filter. - 12 - 1 - read-write - - - ENABLED - Filter enabled. - 0 - - - DISABLED - Filter disabled. - 0x1 - - - - - ECS - Pull-up current source enable in I2C mode. - 13 - 1 - read-write - - - DISABLED - Disabled. IO is in open drain cell. - 0 - - - ENABLED - Enabled. Pull resistor is conencted. - 0x1 - - - - - EGP - Switch between GPIO mode and I2C mode. - 14 - 1 - read-write - - - I2C_MODE - I2C mode. - 0 - - - GPIO_MODE - GPIO mode. - 0x1 - - - - - I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. - 15 - 1 - read-write - - - FAST_MODE - I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. - 0 - - - STANDARD_MODE - I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. - 0x1 - - - - - - - PIO0_15 - Digital I/O control for port 0 pins PIO0_15 - 0x3C - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_16 - Digital I/O control for port 0 pins PIO0_16 - 0x40 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_17 - Digital I/O control for port 0 pins PIO0_17 - 0x44 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_18 - Digital I/O control for port 0 pins PIO0_18 - 0x48 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_19 - Digital I/O control for port 0 pins PIO0_19 - 0x4C - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_20 - Digital I/O control for port 0 pins PIO0_20 - 0x50 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_21 - Digital I/O control for port 0 pins PIO0_21 - 0x54 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_22 - Digital I/O control for port 0 pins PIO0_22 - 0x58 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_23 - Digital I/O control for port 0 pins PIO0_23 - 0x5C - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_24 - Digital I/O control for port 0 pins PIO0_24 - 0x60 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_25 - Digital I/O control for port 0 pins PIO0_25 - 0x64 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_26 - Digital I/O control for port 0 pins PIO0_26 - 0x68 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_27 - Digital I/O control for port 0 pins PIO0_27 - 0x6C - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_28 - Digital I/O control for port 0 pins PIO0_28 - 0x70 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_29 - Digital I/O control for port 0 pins PIO0_29 - 0x74 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_30 - Digital I/O control for port 0 pins PIO0_30 - 0x78 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_31 - Digital I/O control for port 0 pins PIO0_31 - 0x7C - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO1_0 - Digital I/O control for port 1 pins PIO1_0 - 0x80 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO1_1 - Digital I/O control for port 1 pins PIO1_1 - 0x84 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_2 - Digital I/O control for port 1 pins PIO1_2 - 0x88 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_3 - Digital I/O control for port 1 pins PIO1_3 - 0x8C - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_4 - Digital I/O control for port 1 pins PIO1_4 - 0x90 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_5 - Digital I/O control for port 1 pins PIO1_5 - 0x94 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_6 - Digital I/O control for port 1 pins PIO1_6 - 0x98 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_7 - Digital I/O control for port 1 pins PIO1_7 - 0x9C - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_8 - Digital I/O control for port 1 pins PIO1_8 - 0xA0 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO1_9 - Digital I/O control for port 1 pins PIO1_9 - 0xA4 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO1_10 - Digital I/O control for port 1 pins PIO1_10 - 0xA8 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_11 - Digital I/O control for port 1 pins PIO1_11 - 0xAC - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_12 - Digital I/O control for port 1 pins PIO1_12 - 0xB0 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_13 - Digital I/O control for port 1 pins PIO1_13 - 0xB4 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_14 - Digital I/O control for port 1 pins PIO1_14 - 0xB8 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO1_15 - Digital I/O control for port 1 pins PIO1_15 - 0xBC - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_16 - Digital I/O control for port 1 pins PIO1_16 - 0xC0 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_17 - Digital I/O control for port 1 pins PIO1_17 - 0xC4 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_18 - Digital I/O control for port 1 pins PIO1_18 - 0xC8 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_19 - Digital I/O control for port 1 pins PIO1_19 - 0xCC - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO1_20 - Digital I/O control for port 1 pins PIO1_20 - 0xD0 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_21 - Digital I/O control for port 1 pins PIO1_21 - 0xD4 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_22 - Digital I/O control for port 1 pins PIO1_22 - 0xD8 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_23 - Digital I/O control for port 1 pins PIO1_23 - 0xDC - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_24 - Digital I/O control for port 1 pins PIO1_24 - 0xE0 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_25 - Digital I/O control for port 1 pins PIO1_25 - 0xE4 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_26 - Digital I/O control for port 1 pins PIO1_26 - 0xE8 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_27 - Digital I/O control for port 1 pins PIO1_27 - 0xEC - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_28 - Digital I/O control for port 1 pins PIO1_28 - 0xF0 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_29 - Digital I/O control for port 1 pins PIO1_29 - 0xF4 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_30 - Digital I/O control for port 1 pins PIO1_30 - 0xF8 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_31 - Digital I/O control for port 1 pins PIO1_31 - 0xFC - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - - - GINT0 - Group GPIO input interrupt (GINT0/1) - GINT - GINT - 0x40002000 - - 0 - 0x48 - registers - - - GINT0 - 2 - - - - CTRL - GPIO grouped interrupt control register - 0 - 32 - read-write - 0 - 0x7 - - - INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. - 0 - 1 - read-write - - - NO_REQUEST - No request. No interrupt request is pending. - 0 - - - REQUEST_ACTIVE - Request active. Interrupt request is active. - 0x1 - - - - - COMB - Combine enabled inputs for group interrupt - 1 - 1 - read-write - - - OR - Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). - 0 - - - AND - And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). - 0x1 - - - - - TRIG - Group interrupt trigger - 2 - 1 - read-write - - - EDGE_TRIGGERED - Edge-triggered. - 0 - - - LEVEL_TRIGGERED - Level-triggered. - 0x1 - - - - - - - 2 - 0x4 - PORT_POL[%s] - GPIO grouped interrupt port 0 polarity register - 0x20 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. - 0 - 32 - read-write - - - - - 2 - 0x4 - PORT_ENA[%s] - GPIO grouped interrupt port 0 enable register - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. - 0 - 32 - read-write - - - - - - - GINT1 - Group GPIO input interrupt (GINT0/1) - GINT - 0x40003000 - - 0 - 0x48 - registers - - - GINT1 - 3 - - - - PINT - Pin interrupt and pattern match (PINT) - PINT - PINT - 0x40004000 - - 0 - 0x34 - registers - - - PIN_INT0 - 4 - - - PIN_INT1 - 5 - - - PIN_INT2 - 6 - - - PIN_INT3 - 7 - - - PIN_INT4 - 32 - - - PIN_INT5 - 33 - - - PIN_INT6 - 34 - - - PIN_INT7 - 35 - - - - ISEL - Pin Interrupt Mode register - 0 - 32 - read-write - 0 - 0xFF - - - PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive - 0 - 8 - read-write - - - - - IENR - Pin interrupt level or rising edge interrupt enable register - 0x4 - 32 - read-write - 0 - 0xFF - - - ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. - 0 - 8 - read-write - - - - - SIENR - Pin interrupt level or rising edge interrupt set register - 0x8 - 32 - write-only - 0 - 0 - - - SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. - 0 - 8 - write-only - - - - - CIENR - Pin interrupt level (rising edge interrupt) clear register - 0xC - 32 - write-only - 0 - 0 - - - CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. - 0 - 8 - write-only - - - - - IENF - Pin interrupt active level or falling edge interrupt enable register - 0x10 - 32 - read-write - 0 - 0xFF - - - ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. - 0 - 8 - read-write - - - - - SIENF - Pin interrupt active level or falling edge interrupt set register - 0x14 - 32 - write-only - 0 - 0 - - - SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. - 0 - 8 - write-only - - - - - CIENF - Pin interrupt active level or falling edge interrupt clear register - 0x18 - 32 - write-only - 0 - 0 - - - CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. - 0 - 8 - write-only - - - - - RISE - Pin interrupt rising edge register - 0x1C - 32 - read-write - 0 - 0xFF - - - RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. - 0 - 8 - read-write - - - - - FALL - Pin interrupt falling edge register - 0x20 - 32 - read-write - 0 - 0xFF - - - FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. - 0 - 8 - read-write - - - - - IST - Pin interrupt status register - 0x24 - 32 - read-write - 0 - 0xFF - - - PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). - 0 - 8 - read-write - - - - - PMCTRL - Pattern match interrupt control register - 0x28 - 32 - read-write - 0 - 0xFF000003 - - - SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. - 0 - 1 - read-write - - - PIN_INTERRUPT - Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. - 0 - - - PATTERN_MATCH - Pattern match. Interrupts are driven in response to pattern matches. - 0x1 - - - - - ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. - 1 - 1 - read-write - - - DISABLED - Disabled. RXEV output to the CPU is disabled. - 0 - - - ENABLED - Enabled. RXEV output to the CPU is enabled. - 0x1 - - - - - PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs. - 24 - 8 - read-write - - - - - PMSRC - Pattern match interrupt bit-slice source register - 0x2C - 32 - read-write - 0 - 0xFFFFFF00 - - - SRC0 - Selects the input source for bit slice 0 - 8 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. - 0x7 - - - - - SRC1 - Selects the input source for bit slice 1 - 11 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. - 0x7 - - - - - SRC2 - Selects the input source for bit slice 2 - 14 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. - 0x7 - - - - - SRC3 - Selects the input source for bit slice 3 - 17 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. - 0x7 - - - - - SRC4 - Selects the input source for bit slice 4 - 20 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. - 0x7 - - - - - SRC5 - Selects the input source for bit slice 5 - 23 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. - 0x7 - - - - - SRC6 - Selects the input source for bit slice 6 - 26 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. - 0x7 - - - - - SRC7 - Selects the input source for bit slice 7 - 29 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. - 0x7 - - - - - - - PMCFG - Pattern match interrupt bit slice configuration register - 0x30 - 32 - read-write - 0 - 0xFFFFFF7F - - - PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. - 0 - 1 - read-write - - - NO_EFFECT - No effect. Slice 0 is not an endpoint. - 0 - - - ENDPOINT - endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. - 0x1 - - - - - PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. - 1 - 1 - read-write - - - NO_EFFECT - No effect. Slice 1 is not an endpoint. - 0 - - - ENDPOINT - endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. - 0x1 - - - - - PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. - 2 - 1 - read-write - - - NO_EFFECT - No effect. Slice 2 is not an endpoint. - 0 - - - ENDPOINT - endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. - 0x1 - - - - - PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. - 3 - 1 - read-write - - - NO_EFFECT - No effect. Slice 3 is not an endpoint. - 0 - - - ENDPOINT - endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. - 0x1 - - - - - PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. - 4 - 1 - read-write - - - NO_EFFECT - No effect. Slice 4 is not an endpoint. - 0 - - - ENDPOINT - endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. - 0x1 - - - - - PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. - 5 - 1 - read-write - - - NO_EFFECT - No effect. Slice 5 is not an endpoint. - 0 - - - ENDPOINT - endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. - 0x1 - - - - - PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. - 6 - 1 - read-write - - - NO_EFFECT - No effect. Slice 6 is not an endpoint. - 0 - - - ENDPOINT - endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. - 0x1 - - - - - CFG0 - Specifies the match contribution condition for bit slice 0. - 8 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - CFG1 - Specifies the match contribution condition for bit slice 1. - 11 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - CFG2 - Specifies the match contribution condition for bit slice 2. - 14 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - CFG3 - Specifies the match contribution condition for bit slice 3. - 17 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - CFG4 - Specifies the match contribution condition for bit slice 4. - 20 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - CFG5 - Specifies the match contribution condition for bit slice 5. - 23 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - CFG6 - Specifies the match contribution condition for bit slice 6. - 26 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - CFG7 - Specifies the match contribution condition for bit slice 7. - 29 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - - - - - SECPINT - Pin interrupt and pattern match (PINT) - PINT - 0x40005000 - - 0 - 0x34 - registers - - - SEC_HYPERVISOR_CALL - 49 - - - SEC_GPIO_INT0_IRQ0 - 50 - - - SEC_GPIO_INT0_IRQ1 - 51 - - - SEC_VIO - 53 - - - - INPUTMUX - Input multiplexing (INPUT MUX) - INPUTMUX - 0x40006000 - - 0 - 0x7B4 - registers - - - - 7 - 0x4 - SCT0_INMUX[%s] - Input mux register for SCT0 input - 0 - 32 - read-write - 0x1F - 0x1F - - - INP_N - Input number to SCT0 inputs 0 to 6.. - 0 - 5 - read-write - - - val0 - SCT_GPI0 function selected from IOCON register - 0 - - - val1 - SCT_GPI1 function selected from IOCON register - 0x1 - - - val2 - SCT_GPI2 function selected from IOCON register - 0x2 - - - val3 - SCT_GPI3 function selected from IOCON register - 0x3 - - - val4 - SCT_GPI4 function selected from IOCON register - 0x4 - - - val5 - SCT_GPI5 function selected from IOCON register - 0x5 - - - val6 - SCT_GPI6 function selected from IOCON register - 0x6 - - - val7 - SCT_GPI7 function selected from IOCON register - 0x7 - - - val8 - T0_OUT0 ctimer 0 match[0] output - 0x8 - - - val9 - T1_OUT0 ctimer 1 match[0] output - 0x9 - - - val10 - T2_OUT0 ctimer 2 match[0] output - 0xA - - - val11 - T3_OUT0 ctimer 3 match[0] output - 0xB - - - val12 - T4_OUT0 ctimer 4 match[0] output - 0xC - - - val13 - ADC_IRQ interrupt request from ADC - 0xD - - - val14 - GPIOINT_BMATCH - 0xE - - - val15 - USB0_FRAME_TOGGLE - 0xF - - - val16 - USB1_FRAME_TOGGLE - 0x10 - - - val17 - COMP_OUTPUT output from analog comparator - 0x11 - - - val18 - I2S_SHARED_SCK[0] output from I2S pin sharing - 0x12 - - - val19 - I2S_SHARED_SCK[1] output from I2S pin sharing - 0x13 - - - val20 - I2S_SHARED_WS[0] output from I2S pin sharing - 0x14 - - - val21 - I2S_SHARED_WS[1] output from I2S pin sharing - 0x15 - - - val22 - ARM_TXEV interrupt event from cpu0 or cpu1 - 0x16 - - - val23 - DEBUG_HALTED from cpu0 or cpu1 - 0x17 - - - val24 - None - 0x18 - - - val24 - None - 0x19 - - - val24 - None - 0x1A - - - val24 - None - 0x1B - - - val24 - None - 0x1C - - - val24 - None - 0x1D - - - val24 - None - 0x1E - - - val24 - None - 0x1F - - - - - - - 4 - 0x4 - TIMER0CAPTSEL[%s] - Capture select registers for TIMER0 inputs - 0x20 - 32 - read-write - 0x1F - 0x1F - - - CAPTSEL - Input number to TIMER0 capture inputs 0 to 4 - 0 - 5 - read-write - - - val0 - CT_INP0 function selected from IOCON register - 0 - - - val1 - CT_INP1 function selected from IOCON register - 0x1 - - - val2 - CT_INP2 function selected from IOCON register - 0x2 - - - val3 - CT_INP3 function selected from IOCON register - 0x3 - - - val4 - CT_INP4 function selected from IOCON register - 0x4 - - - val5 - CT_INP5 function selected from IOCON register - 0x5 - - - val6 - CT_INP6 function selected from IOCON register - 0x6 - - - val7 - CT_INP7 function selected from IOCON register - 0x7 - - - val8 - CT_INP8 function selected from IOCON register - 0x8 - - - val9 - CT_INP9 function selected from IOCON register - 0x9 - - - val10 - CT_INP10 function selected from IOCON register - 0xA - - - val11 - CT_INP11 function selected from IOCON register - 0xB - - - val12 - CT_INP12 function selected from IOCON register - 0xC - - - val13 - CT_INP13 function selected from IOCON register - 0xD - - - val14 - CT_INP14 function selected from IOCON register - 0xE - - - val15 - CT_INP15 function selected from IOCON register - 0xF - - - val16 - CT_INP16 function selected from IOCON register - 0x10 - - - val17 - None - 0x11 - - - val18 - None - 0x12 - - - val19 - None - 0x13 - - - val20 - USB0_FRAME_TOGGLE - 0x14 - - - val21 - USB1_FRAME_TOGGLE - 0x15 - - - val22 - COMP_OUTPUT output from analog comparator - 0x16 - - - val23 - I2S_SHARED_WS[0] output from I2S pin sharing - 0x17 - - - val24 - I2S_SHARED_WS[1] output from I2S pin sharing - 0x18 - - - val25 - None - 0x19 - - - val25 - None - 0x1A - - - val25 - None - 0x1B - - - val25 - None - 0x1C - - - val25 - None - 0x1D - - - val25 - None - 0x1E - - - val25 - None - 0x1F - - - - - - - 4 - 0x4 - TIMER1CAPTSEL[%s] - Capture select registers for TIMER1 inputs - 0x40 - 32 - read-write - 0x1F - 0x1F - - - CAPTSEL - Input number to TIMER1 capture inputs 0 to 4 - 0 - 5 - read-write - - - val0 - CT_INP0 function selected from IOCON register - 0 - - - val1 - CT_INP1 function selected from IOCON register - 0x1 - - - val2 - CT_INP2 function selected from IOCON register - 0x2 - - - val3 - CT_INP3 function selected from IOCON register - 0x3 - - - val4 - CT_INP4 function selected from IOCON register - 0x4 - - - val5 - CT_INP5 function selected from IOCON register - 0x5 - - - val6 - CT_INP6 function selected from IOCON register - 0x6 - - - val7 - CT_INP7 function selected from IOCON register - 0x7 - - - val8 - CT_INP8 function selected from IOCON register - 0x8 - - - val9 - CT_INP9 function selected from IOCON register - 0x9 - - - val10 - CT_INP10 function selected from IOCON register - 0xA - - - val11 - CT_INP11 function selected from IOCON register - 0xB - - - val12 - CT_INP12 function selected from IOCON register - 0xC - - - val13 - CT_INP13 function selected from IOCON register - 0xD - - - val14 - CT_INP14 function selected from IOCON register - 0xE - - - val15 - CT_INP15 function selected from IOCON register - 0xF - - - val16 - CT_INP16 function selected from IOCON register - 0x10 - - - val17 - None - 0x11 - - - val18 - None - 0x12 - - - val19 - None - 0x13 - - - val20 - USB0_FRAME_TOGGLE - 0x14 - - - val21 - USB1_FRAME_TOGGLE - 0x15 - - - val22 - COMP_OUTPUT output from analog comparator - 0x16 - - - val23 - I2S_SHARED_WS[0] output from I2S pin sharing - 0x17 - - - val24 - I2S_SHARED_WS[1] output from I2S pin sharing - 0x18 - - - val25 - None - 0x19 - - - val25 - None - 0x1A - - - val25 - None - 0x1B - - - val25 - None - 0x1C - - - val25 - None - 0x1D - - - val25 - None - 0x1E - - - val25 - None - 0x1F - - - - - - - 4 - 0x4 - TIMER2CAPTSEL[%s] - Capture select registers for TIMER2 inputs - 0x60 - 32 - read-write - 0x1F - 0x1F - - - CAPTSEL - Input number to TIMER2 capture inputs 0 to 4 - 0 - 5 - read-write - - - val0 - CT_INP0 function selected from IOCON register - 0 - - - val1 - CT_INP1 function selected from IOCON register - 0x1 - - - val2 - CT_INP2 function selected from IOCON register - 0x2 - - - val3 - CT_INP3 function selected from IOCON register - 0x3 - - - val4 - CT_INP4 function selected from IOCON register - 0x4 - - - val5 - CT_INP5 function selected from IOCON register - 0x5 - - - val6 - CT_INP6 function selected from IOCON register - 0x6 - - - val7 - CT_INP7 function selected from IOCON register - 0x7 - - - val8 - CT_INP8 function selected from IOCON register - 0x8 - - - val9 - CT_INP9 function selected from IOCON register - 0x9 - - - val10 - CT_INP10 function selected from IOCON register - 0xA - - - val11 - CT_INP11 function selected from IOCON register - 0xB - - - val12 - CT_INP12 function selected from IOCON register - 0xC - - - val13 - CT_INP13 function selected from IOCON register - 0xD - - - val14 - CT_INP14 function selected from IOCON register - 0xE - - - val15 - CT_INP15 function selected from IOCON register - 0xF - - - val16 - CT_INP16 function selected from IOCON register - 0x10 - - - val17 - None - 0x11 - - - val18 - None - 0x12 - - - val19 - None - 0x13 - - - val20 - USB0_FRAME_TOGGLE - 0x14 - - - val21 - USB1_FRAME_TOGGLE - 0x15 - - - val22 - COMP_OUTPUT output from analog comparator - 0x16 - - - val23 - I2S_SHARED_WS[0] output from I2S pin sharing - 0x17 - - - val24 - I2S_SHARED_WS[1] output from I2S pin sharing - 0x18 - - - val25 - None - 0x19 - - - val25 - None - 0x1A - - - val25 - None - 0x1B - - - val25 - None - 0x1C - - - val25 - None - 0x1D - - - val25 - None - 0x1E - - - val25 - None - 0x1F - - - - - - - 8 - 0x4 - PINTSEL[%s] - Pin interrupt select register - 0xC0 - 32 - read-write - 0x7F - 0x7F - - - INTPIN - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. - 0 - 7 - read-write - - - - - 23 - 0x4 - DMA0_ITRIG_INMUX[%s] - Trigger select register for DMA0 channel - 0xE0 - 32 - read-write - 0x1F - 0x1F - - - INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22). - 0 - 5 - read-write - - - val0 - Pin interrupt 0 - 0 - - - val1 - Pin interrupt 1 - 0x1 - - - val2 - Pin interrupt 2 - 0x2 - - - val3 - Pin interrupt 3 - 0x3 - - - val4 - Timer CTIMER0 Match 0 - 0x4 - - - val5 - Timer CTIMER0 Match 1 - 0x5 - - - val6 - Timer CTIMER1 Match 0 - 0x6 - - - val7 - Timer CTIMER1 Match 1 - 0x7 - - - val8 - Timer CTIMER2 Match 0 - 0x8 - - - val9 - Timer CTIMER2 Match 1 - 0x9 - - - val10 - Timer CTIMER3 Match 0 - 0xA - - - val11 - Timer CTIMER3 Match 1 - 0xB - - - val12 - Timer CTIMER4 Match 0 - 0xC - - - val13 - Timer CTIMER4 Match 1 - 0xD - - - val14 - COMP_OUTPUT - 0xE - - - val15 - DMA0 output trigger mux 0 - 0xF - - - val16 - DMA0 output trigger mux 1 - 0x10 - - - val17 - DMA0 output trigger mux 1 - 0x11 - - - val18 - DMA0 output trigger mux 3 - 0x12 - - - val19 - SCT0 DMA request 0 - 0x13 - - - val20 - SCT0 DMA request 1 - 0x14 - - - val21 - HASH DMA RX trigger - 0x15 - - - val22 - None - 0x16 - - - val22 - None - 0x17 - - - val22 - None - 0x18 - - - val22 - None - 0x19 - - - val22 - None - 0x1A - - - val22 - None - 0x1B - - - val22 - None - 0x1C - - - val22 - None - 0x1D - - - val22 - None - 0x1E - - - val22 - None - 0x1F - - - - - - - 4 - 0x4 - DMA0_OTRIG_INMUX[%s] - DMA0 output trigger selection to become DMA0 trigger - 0x160 - 32 - read-write - 0x1F - 0x1F - - - INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22). - 0 - 5 - read-write - - - - - FREQMEAS_REF - Selection for frequency measurement reference clock - 0x180 - 32 - read-write - 0x1F - 0x1F - - - CLKIN - Clock source number (decimal value) for frequency measure function reference clock: - 0 - 5 - read-write - - - VALUE0 - External main crystal oscilator (Clock_in). - 0 - - - VALUE1 - FRO 12MHz clock. - 0x1 - - - VALUE2 - FRO 96MHz clock. - 0x2 - - - VALUE3 - Watchdog oscillator / FRO1MHz clock. - 0x3 - - - VALUE4 - 32 kHz oscillator (32k_clk) clock. - 0x4 - - - VALUE5 - main clock (main_clock). - 0x5 - - - VALUE6 - FREQME_GPIO_CLK_A. - 0x6 - - - VALUE7 - FREQME_GPIO_CLK_B. - 0x7 - - - - - - - FREQMEAS_TARGET - Selection for frequency measurement target clock - 0x184 - 32 - read-write - 0x1F - 0x1F - - - CLKIN - Clock source number (decimal value) for frequency measure function target clock: - 0 - 5 - read-write - - - VALUE0 - External main crystal oscilator (Clock_in). - 0 - - - VALUE1 - FRO 12MHz clock. - 0x1 - - - VALUE2 - FRO 96MHz clock. - 0x2 - - - VALUE3 - Watchdog oscillator / FRO1MHz clock. - 0x3 - - - VALUE4 - 32 kHz oscillator (32k_clk) clock. - 0x4 - - - VALUE5 - main clock (main_clock). - 0x5 - - - VALUE6 - FREQME_GPIO_CLK_A. - 0x6 - - - VALUE7 - FREQME_GPIO_CLK_B. - 0x7 - - - - - - - 4 - 0x4 - TIMER3CAPTSEL[%s] - Capture select registers for TIMER3 inputs - 0x1A0 - 32 - read-write - 0x1F - 0x1F - - - CAPTSEL - Input number to TIMER3 capture inputs 0 to 4 - 0 - 5 - read-write - - - val0 - CT_INP0 function selected from IOCON register - 0 - - - val1 - CT_INP1 function selected from IOCON register - 0x1 - - - val2 - CT_INP2 function selected from IOCON register - 0x2 - - - val3 - CT_INP3 function selected from IOCON register - 0x3 - - - val4 - CT_INP4 function selected from IOCON register - 0x4 - - - val5 - CT_INP5 function selected from IOCON register - 0x5 - - - val6 - CT_INP6 function selected from IOCON register - 0x6 - - - val7 - CT_INP7 function selected from IOCON register - 0x7 - - - val8 - CT_INP8 function selected from IOCON register - 0x8 - - - val9 - CT_INP9 function selected from IOCON register - 0x9 - - - val10 - CT_INP10 function selected from IOCON register - 0xA - - - val11 - CT_INP11 function selected from IOCON register - 0xB - - - val12 - CT_INP12 function selected from IOCON register - 0xC - - - val13 - CT_INP13 function selected from IOCON register - 0xD - - - val14 - CT_INP14 function selected from IOCON register - 0xE - - - val15 - CT_INP15 function selected from IOCON register - 0xF - - - val16 - CT_INP16 function selected from IOCON register - 0x10 - - - val17 - CT_INP17 function selected from IOCON register - 0x11 - - - val18 - CT_INP18 function selected from IOCON register - 0x12 - - - val19 - CT_INP19 function selected from IOCON register - 0x13 - - - val20 - USB0_FRAME_TOGGLE - 0x14 - - - val21 - USB1_FRAME_TOGGLE - 0x15 - - - val22 - COMP_OUTPUT output from analog comparator - 0x16 - - - val23 - I2S_SHARED_WS[0] output from I2S pin sharing - 0x17 - - - val24 - I2S_SHARED_WS[1] output from I2S pin sharing - 0x18 - - - val25 - None - 0x19 - - - val25 - None - 0x1A - - - val25 - None - 0x1B - - - val25 - None - 0x1C - - - val25 - None - 0x1D - - - val25 - None - 0x1E - - - val25 - None - 0x1F - - - - - - - 4 - 0x4 - TIMER4CAPTSEL[%s] - Capture select registers for TIMER4 inputs - 0x1C0 - 32 - read-write - 0x1F - 0x1F - - - CAPTSEL - Input number to TIMER4 capture inputs 0 to 4 - 0 - 5 - read-write - - - val0 - CT_INP0 function selected from IOCON register - 0 - - - val1 - CT_INP1 function selected from IOCON register - 0x1 - - - val2 - CT_INP2 function selected from IOCON register - 0x2 - - - val3 - CT_INP3 function selected from IOCON register - 0x3 - - - val4 - CT_INP4 function selected from IOCON register - 0x4 - - - val5 - CT_INP5 function selected from IOCON register - 0x5 - - - val6 - CT_INP6 function selected from IOCON register - 0x6 - - - val7 - CT_INP7 function selected from IOCON register - 0x7 - - - val8 - CT_INP8 function selected from IOCON register - 0x8 - - - val9 - CT_INP9 function selected from IOCON register - 0x9 - - - val10 - CT_INP10 function selected from IOCON register - 0xA - - - val11 - CT_INP11 function selected from IOCON register - 0xB - - - val12 - CT_INP12 function selected from IOCON register - 0xC - - - val13 - CT_INP13 function selected from IOCON register - 0xD - - - val14 - CT_INP14 function selected from IOCON register - 0xE - - - val15 - CT_INP15 function selected from IOCON register - 0xF - - - val16 - CT_INP16 function selected from IOCON register - 0x10 - - - val17 - CT_INP17 function selected from IOCON register - 0x11 - - - val18 - CT_INP18 function selected from IOCON register - 0x12 - - - val19 - CT_INP19 function selected from IOCON register - 0x13 - - - val20 - USB0_FRAME_TOGGLE - 0x14 - - - val21 - USB1_FRAME_TOGGLE - 0x15 - - - val22 - COMP_OUTPUT output from analog comparator - 0x16 - - - val23 - I2S_SHARED_WS[0] output from I2S pin sharing - 0x17 - - - val24 - I2S_SHARED_WS[1] output from I2S pin sharing - 0x18 - - - val25 - None - 0x19 - - - val25 - None - 0x1A - - - val25 - None - 0x1B - - - val25 - None - 0x1C - - - val25 - None - 0x1D - - - val25 - None - 0x1E - - - val25 - None - 0x1F - - - - - - - 2 - 0x4 - PINTSECSEL[%s] - Pin interrupt secure select register - 0x1E0 - 32 - read-write - 0x3F - 0x3F - - - INTPIN - Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31. - 0 - 6 - read-write - - - - - 10 - 0x4 - DMA1_ITRIG_INMUX[%s] - Trigger select register for DMA1 channel - 0x200 - 32 - read-write - 0xF - 0xF - - - INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9). - 0 - 4 - read-write - - - val0 - Pin interrupt 0 - 0 - - - val1 - Pin interrupt 1 - 0x1 - - - val2 - Pin interrupt 2 - 0x2 - - - val3 - Pin interrupt 3 - 0x3 - - - val4 - Timer CTIMER0 Match 0 - 0x4 - - - val5 - Timer CTIMER0 Match 1 - 0x5 - - - val6 - Timer CTIMER2 Match 0 - 0x6 - - - val7 - Timer CTIMER4 Match 0 - 0x7 - - - val8 - DMA1 output trigger mux 0 - 0x8 - - - val9 - DMA1 output trigger mux 1 - 0x9 - - - val10 - DMA1 output trigger mux 2 - 0xA - - - val11 - DMA1 output trigger mux 3 - 0xB - - - val12 - SCT0 DMA request 0 - 0xC - - - val13 - SCT0 DMA request 1 - 0xD - - - val14 - HASH DMA RX trigger - 0xE - - - val15 - None - 0xF - - - - - - - 4 - 0x4 - DMA1_OTRIG_INMUX[%s] - DMA1 output trigger selection to become DMA1 trigger - 0x240 - 32 - read-write - 0xF - 0xF - - - INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9). - 0 - 4 - read-write - - - - - DMA0_REQ_ENA - Enable DMA0 requests - 0x740 - 32 - read-write - 0x7FFFFF - 0x7FFFFF - - - REQ_ENA - Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - 0 - 23 - read-write - - - - - DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register - 0x748 - 32 - write-only - 0 - 0x7FFFFF - - - SET - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register - 0 - 23 - write-only - - - - - DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register - 0x750 - 32 - write-only - 0 - 0x7FFFFF - - - CLR - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register - 0 - 23 - write-only - - - - - DMA1_REQ_ENA - Enable DMA1 requests - 0x760 - 32 - read-write - 0x3FF - 0x3FF - - - REQ_ENA - Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - 0 - 10 - read-write - - - - - DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register - 0x768 - 32 - write-only - 0 - 0x3FF - - - SET - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register - 0 - 10 - write-only - - - - - DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register - 0x770 - 32 - write-only - 0 - 0x3FF - - - CLR - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register - 0 - 10 - write-only - - - - - DMA0_ITRIG_ENA - Enable DMA0 triggers - 0x780 - 32 - read-write - 0x3FFFFF - 0x3FFFFF - - - ITRIG_ENA - Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - 0 - 22 - read-write - - - - - DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register - 0x788 - 32 - write-only - 0 - 0x3FFFFF - - - SET - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no change in DMA0_ITRIG_ENA register - 0 - 22 - write-only - - - - - DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register - 0x790 - 32 - write-only - 0 - 0x3FFFFF - - - CLR - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_ITRIG_ENA register - 0 - 22 - write-only - - - - - DMA1_ITRIG_ENA - Enable DMA1 triggers - 0x7A0 - 32 - read-write - 0x7FFF - 0x7FFF - - - ITRIG_ENA - Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - 0 - 15 - read-write - - - - - DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register - 0x7A8 - 32 - write-only - 0 - 0x7FFF - - - SET - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no change in DMA1_ITRIG_ENA register - 0 - 15 - write-only - - - - - DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register - 0x7B0 - 32 - write-only - 0 - 0x7FFF - - - CLR - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIG_ENA register - 0 - 15 - write-only - - - - - - - CTIMER0 - Standard counter/timers (CTIMER0 to 4) - CTIMER - CTIMER - 0x40008000 - - 0 - 0x88 - registers - - - CTIMER0 - 10 - - - - IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. - 0 - 32 - read-write - 0 - 0xFF - - - MR0INT - Interrupt flag for match channel 0. - 0 - 1 - read-write - - - MR1INT - Interrupt flag for match channel 1. - 1 - 1 - read-write - - - MR2INT - Interrupt flag for match channel 2. - 2 - 1 - read-write - - - MR3INT - Interrupt flag for match channel 3. - 3 - 1 - read-write - - - CR0INT - Interrupt flag for capture channel 0 event. - 4 - 1 - read-write - - - CR1INT - Interrupt flag for capture channel 1 event. - 5 - 1 - read-write - - - CR2INT - Interrupt flag for capture channel 2 event. - 6 - 1 - read-write - - - CR3INT - Interrupt flag for capture channel 3 event. - 7 - 1 - read-write - - - - - TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. - 0x4 - 32 - read-write - 0 - 0x3 - - - CEN - Counter enable. - 0 - 1 - read-write - - - DISABLED - Disabled.The counters are disabled. - 0 - - - ENABLED - Enabled. The Timer Counter and Prescale Counter are enabled. - 0x1 - - - - - CRST - Counter reset. - 1 - 1 - read-write - - - DISABLED - Disabled. Do nothing. - 0 - - - ENABLED - Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero. - 0x1 - - - - - - - TC - Timer Counter - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - TCVAL - Timer counter value. - 0 - 32 - read-write - - - - - PR - Prescale Register - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - PRVAL - Prescale counter value. - 0 - 32 - read-write - - - - - PC - Prescale Counter - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - PCVAL - Prescale counter value. - 0 - 32 - read-write - - - - - MCR - Match Control Register - 0x14 - 32 - read-write - 0 - 0xF000FFF - - - MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. - 0 - 1 - read-write - - - MR0R - Reset on MR0: the TC will be reset if MR0 matches it. - 1 - 1 - read-write - - - MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. - 2 - 1 - read-write - - - MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. - 3 - 1 - read-write - - - MR1R - Reset on MR1: the TC will be reset if MR1 matches it. - 4 - 1 - read-write - - - MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. - 5 - 1 - read-write - - - MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. - 6 - 1 - read-write - - - MR2R - Reset on MR2: the TC will be reset if MR2 matches it. - 7 - 1 - read-write - - - MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. - 8 - 1 - read-write - - - MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. - 9 - 1 - read-write - - - MR3R - Reset on MR3: the TC will be reset if MR3 matches it. - 10 - 1 - read-write - - - MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. - 11 - 1 - read-write - - - MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). - 24 - 1 - read-write - - - MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). - 25 - 1 - read-write - - - MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). - 26 - 1 - read-write - - - MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). - 27 - 1 - read-write - - - - - 4 - 0x4 - MR[%s] - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. - 0x18 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCH - Timer counter match value. - 0 - 32 - read-write - - - - - CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. - 0x28 - 32 - read-write - 0 - 0xFFF - - - CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 0 - 1 - read-write - - - CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 1 - 1 - read-write - - - CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. - 2 - 1 - read-write - - - CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 3 - 1 - read-write - - - CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 4 - 1 - read-write - - - CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. - 5 - 1 - read-write - - - CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 6 - 1 - read-write - - - CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 7 - 1 - read-write - - - CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. - 8 - 1 - read-write - - - CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 9 - 1 - read-write - - - CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 10 - 1 - read-write - - - CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. - 11 - 1 - read-write - - - - - 4 - 0x4 - CR[%s] - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. - 0x2C - 32 - read-only - 0 - 0xFFFFFFFF - - - CAP - Timer counter capture value. - 0 - 32 - read-only - - - - - EMR - External Match Register. The EMR controls the match function and the external match pins. - 0x3C - 32 - read-write - 0 - 0xFFF - - - EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - 0 - 1 - read-write - - - EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - 1 - 1 - read-write - - - EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - 2 - 1 - read-write - - - EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - 3 - 1 - read-write - - - EMC0 - External Match Control 0. Determines the functionality of External Match 0. - 4 - 2 - read-write - - - DO_NOTHING - Do Nothing. - 0 - - - CLEAR - Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). - 0x1 - - - SET - Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). - 0x2 - - - TOGGLE - Toggle. Toggle the corresponding External Match bit/output. - 0x3 - - - - - EMC1 - External Match Control 1. Determines the functionality of External Match 1. - 6 - 2 - read-write - - - DO_NOTHING - Do Nothing. - 0 - - - CLEAR - Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). - 0x1 - - - SET - Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). - 0x2 - - - TOGGLE - Toggle. Toggle the corresponding External Match bit/output. - 0x3 - - - - - EMC2 - External Match Control 2. Determines the functionality of External Match 2. - 8 - 2 - read-write - - - DO_NOTHING - Do Nothing. - 0 - - - CLEAR - Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). - 0x1 - - - SET - Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). - 0x2 - - - TOGGLE - Toggle. Toggle the corresponding External Match bit/output. - 0x3 - - - - - EMC3 - External Match Control 3. Determines the functionality of External Match 3. - 10 - 2 - read-write - - - DO_NOTHING - Do Nothing. - 0 - - - CLEAR - Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). - 0x1 - - - SET - Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). - 0x2 - - - TOGGLE - Toggle. Toggle the corresponding External Match bit/output. - 0x3 - - - - - - - CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. - 0x70 - 32 - read-write - 0 - 0xFF - - - CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. - 0 - 2 - read-write - - - TIMER - Timer Mode. Incremented every rising APB bus clock edge. - 0 - - - COUNTER_RISING_EDGE - Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. - 0x1 - - - COUNTER_FALLING_EDGE - Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. - 0x2 - - - COUNTER_DUAL_EDGE - Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. - 0x3 - - - - - CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. - 2 - 2 - read-write - - - CHANNEL_0 - Channel 0. CAPn.0 for CTIMERn - 0 - - - CHANNEL_1 - Channel 1. CAPn.1 for CTIMERn - 0x1 - - - CHANNEL_2 - Channel 2. CAPn.2 for CTIMERn - 0x2 - - - CHANNEL_3 - Channel 3. CAPn.3 for CTIMERn - 0x3 - - - - - ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. - 4 - 1 - read-write - - - SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. - 5 - 3 - read-write - - - CHANNEL_0_RISING - Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - 0 - - - CHANNEL_0_FALLING - Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - 0x1 - - - CHANNEL_1_RISING - Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - 0x2 - - - CHANNEL_1_FALLING - Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - 0x3 - - - CHANNEL_2_RISING - Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - 0x4 - - - CHANNEL_2_FALLING - Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - 0x5 - - - - - - - PWMC - PWM Control Register. This register enables PWM mode for the external match pins. - 0x74 - 32 - read-write - 0 - 0xF - - - PWMEN0 - PWM mode enable for channel0. - 0 - 1 - read-write - - - MATCH - Match. CTIMERn_MAT0 is controlled by EM0. - 0 - - - PWM - PWM. PWM mode is enabled for CTIMERn_MAT0. - 0x1 - - - - - PWMEN1 - PWM mode enable for channel1. - 1 - 1 - read-write - - - MATCH - Match. CTIMERn_MAT01 is controlled by EM1. - 0 - - - PWM - PWM. PWM mode is enabled for CTIMERn_MAT1. - 0x1 - - - - - PWMEN2 - PWM mode enable for channel2. - 2 - 1 - read-write - - - MATCH - Match. CTIMERn_MAT2 is controlled by EM2. - 0 - - - PWM - PWM. PWM mode is enabled for CTIMERn_MAT2. - 0x1 - - - - - PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. - 3 - 1 - read-write - - - MATCH - Match. CTIMERn_MAT3 is controlled by EM3. - 0 - - - PWM - PWM. PWM mode is enabled for CT132Bn_MAT3. - 0x1 - - - - - - - 4 - 0x4 - MSR[%s] - Match Shadow Register - 0x78 - 32 - read-write - 0 - 0xFFFFFFFF - - - SHADOW - Timer counter match shadow value. - 0 - 32 - read-write - - - - - - - CTIMER1 - Standard counter/timers (CTIMER0 to 4) - CTIMER - 0x40009000 - - 0 - 0x88 - registers - - - CTIMER1 - 11 - - - - CTIMER2 - Standard counter/timers (CTIMER0 to 4) - CTIMER - 0x40028000 - - 0 - 0x88 - registers - - - CTIMER2 - 36 - - - - CTIMER3 - Standard counter/timers (CTIMER0 to 4) - CTIMER - 0x40029000 - - 0 - 0x88 - registers - - - CTIMER3 - 13 - - - - CTIMER4 - Standard counter/timers (CTIMER0 to 4) - CTIMER - 0x4002A000 - - 0 - 0x88 - registers - - - CTIMER4 - 37 - - - - WWDT - Windowed Watchdog Timer (WWDT) - WWDT - 0x4000C000 - - 0 - 0x1C - registers - - - WDT_BOD - 0 - - - - MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. - 0 - 32 - read-write - 0 - 0x3F - - - WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently. - 0 - 1 - read-write - - - STOP - Stop. The watchdog timer is stopped. - 0 - - - RUN - Run. The watchdog timer is running. - 0x1 - - - - - WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. - 1 - 1 - read-write - - - INTERRUPT - Interrupt. A watchdog time-out will not cause a chip reset. - 0 - - - RESET - Reset. A watchdog time-out will cause a chip reset. - 0x1 - - - - - WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1. - 2 - 1 - read-write - - - WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. - 3 - 1 - read-write - - - WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. - 4 - 1 - read-write - - - FLEXIBLE - Flexible. The watchdog time-out value (TC) can be changed at any time. - 0 - - - THRESHOLD - Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. - 0x1 - - - - - - - TC - Watchdog timer constant register. This 24-bit register determines the time-out value. - 0x4 - 32 - read-write - 0xFF - 0xFFFFFF - - - COUNT - Watchdog time-out value. - 0 - 24 - read-write - - - - - FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. - 0x8 - 32 - write-only - 0 - 0 - - - FEED - Feed value should be 0xAA followed by 0x55. - 0 - 8 - write-only - - - - - TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. - 0xC - 32 - read-only - 0xFF - 0xFFFFFF - - - COUNT - Counter timer value. - 0 - 24 - read-only - - - - - WARNINT - Watchdog Warning Interrupt compare value. - 0x14 - 32 - read-write - 0 - 0x3FF - - - WARNINT - Watchdog warning interrupt compare value. - 0 - 10 - read-write - - - - - WINDOW - Watchdog Window compare value. - 0x18 - 32 - read-write - 0xFFFFFF - 0xFFFFFF - - - WINDOW - Watchdog window value. - 0 - 24 - read-write - - - - - - - MRT0 - Multi-Rate Timer (MRT) - MRT - 0x4000D000 - - 0 - 0xFC - registers - - - MRT0 - 9 - - - - 4 - 0x10 - CHANNEL[%s] - no description available - 0 - - INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. - 0 - 32 - read-write - 0 - 0x80FFFFFF - - - IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval. - 0 - 24 - read-write - - - LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. - 31 - 1 - read-write - - - NO_FORCE_LOAD - No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected. - 0 - - - FORCE_LOAD - Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. - 0x1 - - - - - - - TIMER - MRT Timer register. This register reads the value of the down-counter. - 0x4 - 32 - read-only - 0xFFFFFF - 0xFFFFFF - - - VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF). - 0 - 24 - read-only - - - - - CTRL - MRT Control register. This register controls the MRT modes. - 0x8 - 32 - read-write - 0 - 0x7 - - - INTEN - Enable the TIMERn interrupt. - 0 - 1 - read-write - - - DISABLED - Disabled. TIMERn interrupt is disabled. - 0 - - - ENABLED - Enabled. TIMERn interrupt is enabled. - 0x1 - - - - - MODE - Selects timer mode. - 1 - 2 - read-write - - - REPEAT_INTERRUPT_MODE - Repeat interrupt mode. - 0 - - - ONE_SHOT_INTERRUPT_MODE - One-shot interrupt mode. - 0x1 - - - ONE_SHOT_STALL_MODE - One-shot stall mode. - 0x2 - - - - - - - STAT - MRT Status register. - 0xC - 32 - read-write - 0 - 0x7 - - - INTFLAG - Monitors the interrupt flag. - 0 - 1 - read-write - - - NO_PENDING_INTERRUPT - No pending interrupt. Writing a zero is equivalent to no operation. - 0 - - - PENDING_INTERRUPT - Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. - 0x1 - - - - - RUN - Indicates the state of TIMERn. This bit is read-only. - 1 - 1 - read-write - - - IDLE_STATE - Idle state. TIMERn is stopped. - 0 - - - RUNNING - Running. TIMERn is running. - 0x1 - - - - - INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes. - 2 - 1 - read-write - - - NO - This channel is not in use. - 0 - - - YES - This channel is in use. - 0x1 - - - - - - - - MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. - 0xF0 - 32 - read-write - 0x173 - 0x800001FF - - - NOC - Identifies the number of channels in this MRT.(4 channels on this device.) - 0 - 4 - read-write - - - NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.) - 4 - 5 - read-write - - - MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. - 31 - 1 - read-write - - - HARDWARE_STATUS_MODE - Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. - 0 - - - MULTI_TASK_MODE - Multi-task mode. - 0x1 - - - - - - - IDLE_CH - Idle channel register. This register returns the number of the first idle channel. - 0xF4 - 32 - read-only - 0 - 0xF0 - - - CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details. - 4 - 4 - read-only - - - - - IRQ_FLAG - Global interrupt flag register - 0xF8 - 32 - read-write - 0 - 0xF - - - GFLAG0 - Monitors the interrupt flag of TIMER0. - 0 - 1 - read-write - - - NO_PENDING_INTERRUPT - No pending interrupt. Writing a zero is equivalent to no operation. - 0 - - - PENDING_INTERRUPT - Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. - 0x1 - - - - - GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0. - 1 - 1 - read-write - - - GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0. - 2 - 1 - read-write - - - GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0. - 3 - 1 - read-write - - - - - - - UTICK0 - Micro-tick Timer (UTICK) - UTICK - 0x4000E000 - - 0 - 0x20 - registers - - - UTICK0 - 8 - - - - CTRL - Control register. - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer. - 0 - 31 - read-write - - - REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. - 31 - 1 - read-write - - - - - STAT - Status register. - 0x4 - 32 - read-write - 0 - 0x3 - - - INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any value to this register clears this flag. - 0 - 1 - read-write - - - ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. - 1 - 1 - read-write - - - - - CFG - Capture configuration register. - 0x8 - 32 - read-write - 0 - 0xF0F - - - CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled. - 0 - 1 - read-write - - - CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled. - 1 - 1 - read-write - - - CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled. - 2 - 1 - read-write - - - CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled. - 3 - 1 - read-write - - - CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. - 8 - 1 - read-write - - - CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. - 9 - 1 - read-write - - - CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. - 10 - 1 - read-write - - - CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. - 11 - 1 - read-write - - - - - CAPCLR - Capture clear register. - 0xC - 32 - write-only - 0 - 0 - - - CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value. - 0 - 1 - write-only - - - CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value. - 1 - 1 - write-only - - - CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value. - 2 - 1 - write-only - - - CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value. - 3 - 1 - write-only - - - - - 4 - 0x4 - CAP[%s] - Capture register . - 0x10 - 32 - read-only - 0 - 0xFFFFFFFF - - - CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower than the actual value of the Micro-tick Timer at the moment of the capture event. - 0 - 31 - read-only - - - VALID - Capture Valid. When 1, a value has been captured based on a transition of the related UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. - 31 - 1 - read-only - - - - - - - ANACTRL - ANALOGCTRL - ANACTRL - 0x40013000 - - 0 - 0x108 - registers - - - - ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) - 0 - 32 - read-write - 0 - 0x1 - - - FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source. - 0 - 1 - read-write - - - EFUSE - FRO192M trimming and 'Enable' comes from eFUSE. - 0 - - - FRO192MCTRL - FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers. - 0x1 - - - - - - - ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers - 0x4 - 32 - read-only - 0x50000000 - 0xF0003FFF - - - FLASH_PWRDWN - Flash Power Down status. - 12 - 1 - read-only - - - PWRUP - Flash is not in power down mode. - 0 - - - PWRDWN - Flash is in power down mode. - 0x1 - - - - - FLASH_INIT_ERROR - Flash initialization error status. - 13 - 1 - read-only - - - NOERROR - No error. - 0 - - - ERROR - At least one error occured during flash initialization.. - 0x1 - - - - - - - FREQ_ME_CTRL - Frequency Measure function control register - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPVAL_SCALE - Frequency measure result /Frequency measur scale - 0 - 31 - read-write - - - PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 30:0). - 31 - 1 - read-write - - - - - FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register - 0x10 - 32 - read-write - 0x80D01A - 0xF3FFFFBF - - - ENA_12MHZCLK - 12 MHz clock control. - 14 - 1 - read-write - - - DISABLE - 12 MHz clock is disabled. - 0 - - - ENABLE - 12 MHz clock is enabled. - 0x1 - - - - - ENA_48MHZCLK - 48 MHz clock control. - 15 - 1 - read-write - - - ENABLE - 48 MHz clock is enabled. - 0x1 - - - - - DAC_TRIM - Frequency trim. - 16 - 8 - read-write - - - USBCLKADJ - If this bit is set and the USB peripheral is enabled into full speed device mode, the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF packets. - 24 - 1 - read-write - - - USBMODCHG - If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0. - 25 - 1 - read-only - - - ENA_96MHZCLK - 96 MHz clock control. - 30 - 1 - read-write - - - DISABLE - 96 MHz clock is disabled. - 0 - - - ENABLE - 96 MHz clock is enabled. - 0x1 - - - - - WRTRIM - This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields. - 31 - 1 - write-only - - - - - FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register - 0x14 - 32 - read-write - 0x3 - 0x3 - - - CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. - 0 - 1 - read-only - - - NOCLKOUT - No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). - 0 - - - CLKOUT - Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). - 0x1 - - - - - ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses the threshold voltage of a SLVT transistor, this output signal will go high. It is also possible to observe the clk_valid signal. - 1 - 1 - read-only - - - - - ADC_CTRL - General Purpose ADC VBAT Divider branch control - 0x18 - 32 - read-write - 0 - 0x1 - - - VBATDIVENABLE - Switch On/Off VBAT divider branch. - 0 - 1 - read-write - - - DISABLE - VBAT divider branch is disabled. - 0 - - - ENABLE - VBAT divider branch is enabled. - 0x1 - - - - - - - XO32M_CTRL - High speed Crystal Oscillator Control register - 0x20 - 32 - read-write - 0x21428A - 0x1FFFFFFE - - - SLAVE - Xo in slave mode. - 4 - 1 - read-write - - - OSC_CAP_IN - Tune capa banks of High speed Crystal Oscillator input pin - 8 - 7 - read-write - - - OSC_CAP_OUT - Tune capa banks of High speed Crystal Oscillator output pin - 15 - 7 - read-write - - - ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. - 22 - 1 - read-write - - - DISABLE - XO AC buffer bypass is disabled. - 0 - - - ENABLE - XO AC buffer bypass is enabled. - 0x1 - - - - - ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL. - 23 - 1 - read-write - - - DISABLE - High speed Crystal oscillator output to USB HS PLL is disabled. - 0 - - - ENABLE - High speed Crystal oscillator output to USB HS PLL is enabled. - 0x1 - - - - - ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system. - 24 - 1 - read-write - - - DISABLE - High speed Crystal oscillator output to CPU system is disabled. - 0 - - - ENABLE - High speed Crystal oscillator output to CPU system is enabled. - 0x1 - - - - - - - XO32M_STATUS - High speed Crystal Oscillator Status register - 0x24 - 32 - read-only - 0 - 0x1 - - - XO_READY - Indicates XO out frequency statibilty. - 0 - 1 - read-only - - - NOT_STABLE - XO output frequency is not yet stable. - 0 - - - STABLE - XO output frequency is stable. - 0x1 - - - - - - - BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register - 0x30 - 32 - read-write - 0 - 0x3F - - - BODVBAT_INT_ENABLE - BOD VBAT interrupt control. - 0 - 1 - read-write - - - DISABLE - BOD VBAT interrupt is disabled. - 0 - - - ENABLE - BOD VBAT interrupt is enabled. - 0x1 - - - - - BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit. - 1 - 1 - read-write - - - BODCORE_INT_ENABLE - BOD CORE interrupt control. - 2 - 1 - read-write - - - DISABLE - BOD CORE interrupt is disabled. - 0 - - - ENABLE - BOD CORE interrupt is enabled. - 0x1 - - - - - BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. - 3 - 1 - read-write - - - DCDC_INT_ENABLE - DCDC interrupt control. - 4 - 1 - read-write - - - DISABLE - DCDC interrupt is disabled. - 0 - - - ENABLE - DCDC interrupt is enabled. - 0x1 - - - - - DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. - 5 - 1 - read-write - - - - - BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register - 0x34 - 32 - read-only - 0x104 - 0x1FF - - - BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. - 0 - 1 - read-only - - - NOT_PENDING - No interrupt pending.. - 0 - - - PENDING - Interrupt pending.. - 0x1 - - - - - BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. - 1 - 1 - read-only - - - NOT_PENDING - No interrupt pending.. - 0 - - - PENDING - Interrupt pending.. - 0x1 - - - - - BODVBAT_VAL - Current value of BOD VBAT power status output. - 2 - 1 - read-only - - - NOT_OK - VBAT voltage level is below the threshold. - 0 - - - OK - VBAT voltage level is above the threshold. - 0x1 - - - - - BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. - 3 - 1 - read-only - - - NOT_PENDING - No interrupt pending.. - 0 - - - PENDING - Interrupt pending.. - 0x1 - - - - - BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. - 4 - 1 - read-only - - - NOT_PENDING - No interrupt pending.. - 0 - - - PENDING - Interrupt pending.. - 0x1 - - - - - BODCORE_VAL - Current value of BOD CORE power status output. - 5 - 1 - read-only - - - NOT_OK - CORE voltage level is below the threshold. - 0 - - - OK - CORE voltage level is above the threshold. - 0x1 - - - - - DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. - 6 - 1 - read-only - - - NOT_PENDING - No interrupt pending.. - 0 - - - PENDING - Interrupt pending.. - 0x1 - - - - - DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. - 7 - 1 - read-only - - - NOT_PENDING - No interrupt pending.. - 0 - - - PENDING - Interrupt pending.. - 0x1 - - - - - DCDC_VAL - Current value of DCDC power status output. - 8 - 1 - read-only - - - NOT_OK - DCDC output Voltage is below the targeted regulation level. - 0 - - - OK - DCDC output Voltage is above the targeted regulation level. - 0x1 - - - - - - - RINGO0_CTRL - First Ring Oscillator module control register. - 0x40 - 32 - read-write - 0x40 - 0x803F1FFF - - - SL - Select short or long ringo (for all ringos types). - 0 - 1 - read-write - - - SHORT - Select short ringo (few elements). - 0 - - - LONG - Select long ringo (many elements). - 0x1 - - - - - FS - Ringo frequency output divider. - 1 - 1 - read-write - - - FAST - High frequency output (frequency lower than 100 MHz). - 0 - - - SLOW - Low frequency output (frequency lower than 10 MHz). - 0x1 - - - - - SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control. - 2 - 2 - read-write - - - NORMAL - Normal mode. - 0 - - - P_MONITOR - P-Monitor mode. Measure with weak P transistor. - 0x1 - - - N_MONITOR - P-Monitor mode. Measure with weak N transistor. - 0x2 - - - FORBIDDEN - Don't use. - 0x3 - - - - - PD - Ringo module Power control. - 4 - 1 - read-write - - - POWERED_ON - The Ringo module is enabled. - 0 - - - POWERED_DOWN - The Ringo module is disabled. - 0x1 - - - - - E_ND0 - First NAND2-based ringo control. - 5 - 1 - read-write - - - DISABLE - First NAND2-based ringo is disabled. - 0 - - - ENABLE - First NAND2-based ringo is enabled. - 0x1 - - - - - E_ND1 - Second NAND2-based ringo control. - 6 - 1 - read-write - - - DISABLE - Second NAND2-based ringo is disabled. - 0 - - - ENABLE - Second NAND2-based ringo is enabled. - 0x1 - - - - - E_NR0 - First NOR2-based ringo control. - 7 - 1 - read-write - - - DISABLE - First NOR2-based ringo is disabled. - 0 - - - ENABLE - First NOR2-based ringo is enabled. - 0x1 - - - - - E_NR1 - Second NOR2-based ringo control. - 8 - 1 - read-write - - - DISABLE - Second NORD2-based ringo is disabled. - 0 - - - ENABLE - Second NORD2-based ringo is enabled. - 0x1 - - - - - E_IV0 - First Inverter-based ringo control. - 9 - 1 - read-write - - - DISABLE - First INV-based ringo is disabled. - 0 - - - ENABLE - First INV-based ringo is enabled. - 0x1 - - - - - E_IV1 - Second Inverter-based ringo control. - 10 - 1 - read-write - - - DISABLE - Second INV-based ringo is disabled. - 0 - - - ENABLE - Second INV-based ringo is enabled. - 0x1 - - - - - E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control. - 11 - 1 - read-write - - - DISABLE - First PN-based ringo is disabled. - 0 - - - ENABLE - First PN-based ringo is enabled. - 0x1 - - - - - E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control. - 12 - 1 - read-write - - - DISABLE - Second PN-based ringo is disabled. - 0 - - - ENABLE - Second PN-based ringo is enabled. - 0x1 - - - - - DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) - 16 - 4 - read-write - - - DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. - 31 - 1 - read-only - - - - - RINGO1_CTRL - Second Ring Oscillator module control register. - 0x44 - 32 - read-write - 0x40 - 0x803F01FF - - - S - Select short or long ringo (for all ringos types). - 0 - 1 - read-write - - - SHORT - Select short ringo (few elements). - 0 - - - LONG - Select long ringo (many elements). - 0x1 - - - - - FS - Ringo frequency output divider. - 1 - 1 - read-write - - - FAST - High frequency output (frequency lower than 100 MHz). - 0 - - - SLOW - Low frequency output (frequency lower than 10 MHz). - 0x1 - - - - - PD - Ringo module Power control. - 2 - 1 - read-write - - - POWERED_ON - The Ringo module is enabled. - 0 - - - POWERED_DOWN - The Ringo module is disabled. - 0x1 - - - - - E_R24 - . - 3 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_R35 - . - 4 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M2 - Metal 2 (M2) monitor control. - 5 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M3 - Metal 3 (M3) monitor control. - 6 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M4 - Metal 4 (M4) monitor control. - 7 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M5 - Metal 5 (M5) monitor control. - 8 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) - 16 - 4 - read-write - - - DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. - 31 - 1 - read-only - - - - - RINGO2_CTRL - Third Ring Oscillator module control register. - 0x48 - 32 - read-write - 0x40 - 0x803F01FF - - - S - Select short or long ringo (for all ringos types). - 0 - 1 - read-write - - - SHORT - Select short ringo (few elements). - 0 - - - LONG - Select long ringo (many elements). - 0x1 - - - - - FS - Ringo frequency output divider. - 1 - 1 - read-write - - - FAST - High frequency output (frequency lower than 100 MHz). - 0 - - - SLOW - Low frequency output (frequency lower than 10 MHz). - 0x1 - - - - - PD - Ringo module Power control. - 2 - 1 - read-write - - - POWERED_ON - The Ringo module is enabled. - 0 - - - POWERED_DOWN - The Ringo module is disabled. - 0x1 - - - - - E_R24 - . - 3 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_R35 - . - 4 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M2 - Metal 2 (M2) monitor control. - 5 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M3 - Metal 3 (M3) monitor control. - 6 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M4 - Metal 4 (M4) monitor control. - 7 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M5 - Metal 5 (M5) monitor control. - 8 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) - 16 - 4 - read-write - - - DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. - 31 - 1 - read-only - - - - - LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register - 0xB0 - 32 - read-write - 0x3A0 - 0x3FE - - - BYPASS - Activate LDO bypass. - 1 - 1 - read-write - - - DISABLE - Disable bypass mode (for normal operations). - 0 - - - ENABLE - Activate LDO bypass. - 0x1 - - - - - HIGHZ - . - 2 - 1 - read-write - - - NORMALMPEDANCE - Output in High normal state. - 0 - - - HIGHIMPEDANCE - Output in High Impedance state. - 0x1 - - - - - VOUT - Sets the LDO output level. - 3 - 3 - read-write - - - V_0P750 - 0.750 V. - 0 - - - V_0P775 - 0.775 V. - 0x1 - - - V_0P800 - 0.800 V. - 0x2 - - - V_0P825 - 0.825 V. - 0x3 - - - V_0P850 - 0.850 V. - 0x4 - - - V_0P875 - 0.875 V. - 0x5 - - - V_0P900 - 0.900 V. - 0x6 - - - V_0P925 - 0.925 V. - 0x7 - - - - - IBIAS - Adjust the biasing current. - 6 - 2 - read-write - - - STABMODE - Stability configuration. - 8 - 2 - read-write - - - - - AUX_BIAS - AUX_BIAS - 0xB4 - 32 - read-write - 0x703A0 - 0x3FFFFE - - - VREF1VENABLE - Control output of 1V reference voltage. - 1 - 1 - read-write - - - DISABLE - Output of 1V reference voltage buffer is bypassed. - 0 - - - ENABLE - Output of 1V reference voltage is enabled. - 0x1 - - - - - ITRIM - current trimming control word. - 2 - 5 - read-write - - - PTATITRIM - current trimming control word for ptat current. - 7 - 5 - read-write - - - VREF1VTRIM - voltage trimming control word. - 12 - 5 - read-write - - - VREF1VCURVETRIM - Control bit to configure trimming state of mirror. - 17 - 3 - read-write - - - ITRIMCTRL0 - Control bit to configure trimming state of mirror. - 20 - 1 - read-write - - - ITRIMCTRL1 - Control bit to configure trimming state of mirror. - 21 - 1 - read-write - - - - - USBHS_PHY_CTRL - USB High Speed Phy Control - 0x100 - 32 - read-write - 0x8 - 0xF - - - usb_vbusvalid_ext - Override value for Vbus if using external detectors. - 0 - 1 - read-write - - - usb_id_ext - Override value for ID if using external detectors. - 1 - 1 - read-write - - - - - USBHS_PHY_TRIM - USB High Speed Phy Trim values - 0x104 - 32 - read-write - 0 - 0xFFFFFF - - - trim_usb_reg_env_tail_adj_vd - Adjusts time constant of HS RX squelch (envelope) comparator. - 0 - 2 - read-write - - - trim_usbphy_tx_d_cal - . - 2 - 4 - read-write - - - trim_usbphy_tx_cal45dp - . - 6 - 5 - read-write - - - trim_usbphy_tx_cal45dm - . - 11 - 5 - read-write - - - trim_usb2_refbias_tst - . - 16 - 2 - read-write - - - trim_usb2_refbias_vbgadj - . - 18 - 3 - read-write - - - trim_pll_ctrl0_div_sel - . - 21 - 3 - read-write - - - - - - - PMC - PMC - PMC - 0x40020000 - - 0 - 0xD8 - registers - - - ACMP - 24 - - - - STATUS - Power Management Controller FSM (Finite State Machines) status - 0x4 - 32 - read-only - 0 - 0xF00FFFFF - - - BOOTMODE - Latest IC Boot cause:. - 18 - 2 - read-only - - - POWERUP - Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset). - 0 - - - DEEPSLEEP - Latest IC boot was from DEEP SLEEP low power mode. - 0x1 - - - POWERDOWN - Latest IC boot was from POWER DOWN low power mode. - 0x2 - - - DEEPPOWERDOWN - Latest IC boot was from DEEP POWER DOWN low power mode. - 0x3 - - - - - - - RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x8 - 32 - read-write - 0 - 0xF - - - DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). - 0 - 1 - read-write - - - DISABLE - Reset event from DEEP POWER DOWN mode is disable. - 0 - - - ENABLE - Reset event from DEEP POWER DOWN mode is enable. - 0x1 - - - - - BODVBATRESETENABLE - BOD VBAT reset enable. - 1 - 1 - read-write - - - DISABLE - BOD VBAT reset is disable. - 0 - - - ENABLE - BOD VBAT reset is enable. - 0x1 - - - - - BODCORERESETENABLE - BOD CORE reset enable. - 2 - 1 - read-write - - - DISABLE - BOD CORE reset is disable. - 0 - - - ENABLE - BOD CORE reset is enable. - 0x1 - - - - - SWRRESETENABLE - Software reset enable. - 3 - 1 - read-write - - - DISABLE - Software reset is disable. - 0 - - - ENABLE - Software reset is enable. - 0x1 - - - - - - - DCDC0 - DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x10 - 32 - read-write - 0x10C4E68 - 0x7FFFFFF - - - RC - Constant On-Time calibration. - 0 - 6 - read-write - - - ICOMP - Select the type of ZCD comparator. - 6 - 2 - read-write - - - ISEL - Alter Internal biasing currents. - 8 - 2 - read-write - - - ICENABLE - Selection of auto scaling of COT period with variations in VDD. - 10 - 1 - read-write - - - TMOS - One-shot generator reference current trimming signal. - 11 - 5 - read-write - - - DISABLEISENSE - Disable Current sensing. - 16 - 1 - read-write - - - VOUT - Set output regulation voltage. - 17 - 4 - read-write - - - V_DCDC_0P950 - 0.95 V. - 0 - - - V_DCDC_0P975 - 0.975 V. - 0x1 - - - V_DCDC_1P000 - 1 V. - 0x2 - - - V_DCDC_1P025 - 1.025 V. - 0x3 - - - V_DCDC_1P050 - 1.05 V. - 0x4 - - - V_DCDC_1P075 - 1.075 V. - 0x5 - - - V_DCDC_1P100 - 1.1 V. - 0x6 - - - V_DCDC_1P125 - 1.125 V. - 0x7 - - - V_DCDC_1P150 - 1.15 V. - 0x8 - - - V_DCDC_1P175 - 1.175 V. - 0x9 - - - V_DCDC_1P200 - 1.2 V. - 0xA - - - - - SLICINGENABLE - Enable staggered switching of power switches. - 21 - 1 - read-write - - - INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. - 22 - 1 - read-write - - - VOUT_PWD - Set output regulation voltage during Deep Sleep. - 23 - 4 - read-write - - - - - DCDC1 - DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x14 - 32 - read-write - 0x1803A98 - 0xFFFFFFFF - - - RTRIMOFFET - Adjust the offset voltage of BJT based comparator. - 0 - 4 - read-write - - - RSENSETRIM - Adjust Max inductor peak current limiting. - 4 - 4 - read-write - - - DTESTENABLE - Enable Digital test signals. - 8 - 1 - read-write - - - SETCURVE - Bandgap calibration parameter. - 9 - 2 - read-write - - - SETDC - Bandgap calibration parameter. - 11 - 4 - read-write - - - DTESTSEL - Select the output signal for test. - 15 - 3 - read-write - - - ISCALEENABLE - Modify COT behavior. - 18 - 1 - read-write - - - FORCEBYPASS - Force bypass mode. - 19 - 1 - read-write - - - TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. - 20 - 4 - read-write - - - FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. - 24 - 1 - read-write - - - LCENABLE - Change the range of the peak detector of current inside the inductor. - 25 - 1 - read-write - - - TOFF - Constant Off-Time calibration input. - 26 - 5 - read-write - - - TOFFENABLE - Enable Constant Off-Time feature. - 31 - 1 - read-write - - - - - LDOPMU - Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x1C - 32 - read-write - 0x10EF718 - 0x31FFFFF - - - VADJ - Sets the Always-On domain LDO output level. - 0 - 5 - read-write - - - V_1P220 - 1.22 V. - 0 - - - V_0P700 - 0.7 V. - 0x1 - - - V_0P725 - 0.725 V. - 0x2 - - - V_0P750 - 0.75 V. - 0x3 - - - V_0P775 - 0.775 V. - 0x4 - - - V_0P800 - 0.8 V. - 0x5 - - - V_0P825 - 0.825 V. - 0x6 - - - V_0P850 - 0.85 V. - 0x7 - - - V_0P875 - 0.875 V. - 0x8 - - - V_0P900 - 0.9 V. - 0x9 - - - V_0P960 - 0.96 V. - 0xA - - - V_0P970 - 0.97 V. - 0xB - - - V_0P980 - 0.98 V. - 0xC - - - V_0P990 - 0.99 V. - 0xD - - - V_1P000 - 1 V. - 0xE - - - V_1P010 - 1.01 V. - 0xF - - - V_1P020 - 1.02 V. - 0x10 - - - V_1P030 - 1.03 V. - 0x11 - - - V_1P040 - 1.04 V. - 0x12 - - - V_1P050 - 1.05 V. - 0x13 - - - V_1P060 - 1.06 V. - 0x14 - - - V_1P070 - 1.07 V. - 0x15 - - - V_1P080 - 1.08 V. - 0x16 - - - V_1P090 - 1.09 V. - 0x17 - - - V_1P100 - 1.1 V. - 0x18 - - - V_1P110 - 1.11 V. - 0x19 - - - V_1P120 - 1.12 V. - 0x1A - - - V_1P130 - 1.13 V. - 0x1B - - - V_1P140 - 1.14 V. - 0x1C - - - V_1P150 - 1.15 V. - 0x1D - - - V_1P160 - 1.16 V. - 0x1E - - - V_1P220_1 - 1.22 V. - 0x1F - - - - - VADJ_PWD - Sets the Always-On domain LDO output level in all power down modes. - 5 - 5 - read-write - - - VADJ_BOOST - Sets the Always-On domain LDO Boost output level. - 10 - 5 - read-write - - - VADJ_BOOST_PWD - Sets the Always-On domain LDO Boost output level in all power down modes. - 15 - 5 - read-write - - - BOOST_ENA - Control the LDO AO boost mode in ACTIVE mode. - 24 - 1 - read-write - - - DISABLE - LDO AO Boost Mode is disable. - 0 - - - ENABLE - LDO AO Boost Mode is enable. - 0x1 - - - - - BOOST_ENA_PWD - Control the LDO AO boost mode in the different low power modes (DEEP SLEEP, POWERDOWN, and DEEP POWER DOWN). - 25 - 1 - read-write - - - DISABLE - LDO AO Boost Mode is disable. - 0 - - - ENABLE - LDO AO Boost Mode is enable. - 0x1 - - - - - - - BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] - 0x30 - 32 - read-write - 0x47 - 0x7F - - - TRIGLVL - BoD trigger level. - 0 - 5 - read-write - - - V_1P00 - 1.00 V. - 0 - - - V_1P10 - 1.10 V. - 0x1 - - - V_1P20 - 1.20 V. - 0x2 - - - V_1P30 - 1.30 V. - 0x3 - - - V_1P40 - 1.40 V. - 0x4 - - - V_1P50 - 1.50 V. - 0x5 - - - V_1P60 - 1.60 V. - 0x6 - - - V_1P65 - 1.65 V. - 0x7 - - - V_1P70 - 1.70 V. - 0x8 - - - V_1P75 - 1.75 V. - 0x9 - - - V_1P80 - 1.80 V. - 0xA - - - V_1P90 - 1.90 V. - 0xB - - - V_2P00 - 2.00 V. - 0xC - - - V_2P10 - 2.10 V. - 0xD - - - V_2P20 - 2.20 V. - 0xE - - - V_2P30 - 2.30 V. - 0xF - - - V_2P40 - 2.40 V. - 0x10 - - - V_2P50 - 2.50 V. - 0x11 - - - V_2P60 - 2.60 V. - 0x12 - - - V_2P70 - 2.70 V. - 0x13 - - - V_2P80 - 2.806 V. - 0x14 - - - V_2P90 - 2.90 V. - 0x15 - - - V_3P00 - 3.00 V. - 0x16 - - - V_3P10 - 3.10 V. - 0x17 - - - V_3P20 - 3.20 V. - 0x18 - - - V_3P30_2 - 3.30 V. - 0x19 - - - V_3P30_3 - 3.30 V. - 0x1A - - - V_3P30_4 - 3.30 V. - 0x1B - - - V_3P30_5 - 3.30 V. - 0x1C - - - V_3P30_6 - 3.30 V. - 0x1D - - - V_3P30_7 - 3.30 V. - 0x1E - - - V_3P30_8 - 3.30 V. - 0x1F - - - - - HYST - BoD Hysteresis control. - 5 - 2 - read-write - - - HYST_25MV - 25 mV. - 0 - - - HYST_50MV - 50 mV. - 0x1 - - - HYST_75MV - 75 mV. - 0x2 - - - HYST_100MV - 100 mV. - 0x3 - - - - - - - REFFASTWKUP - Analog References fast wake-up Control register [Reset by: PoR] - 0x40 - 32 - read-write - 0x1 - 0x3 - - - LPWKUP - Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP POWER DOWN): . - 0 - 1 - read-write - - - DISABLE - Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode. - 0 - - - ENABLE - Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode. - 0x1 - - - - - HWWKUP - Analog References fast wake-up in case of Hardware Pin reset: . - 1 - 1 - read-write - - - DISABLE - Analog References fast wake-up feature is disabled in case of Hardware Pin reset. - 0 - - - ENABLE - Analog References fast wake-up feature is enabled in case of Hardware Pin reset. - 0x1 - - - - - - - XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] - 0x4C - 32 - read-write - 0x204052 - 0x3FFFFFE - - - IREF - reference output current selection inputs. - 1 - 2 - read-write - - - TEST - Oscillator Test Mode. - 3 - 1 - read-write - - - IBIAS - bias current selection inputs. - 4 - 2 - read-write - - - AMPL - oscillator amplitude selection inputs. - 6 - 2 - read-write - - - CAPBANKIN - Capa bank setting input. - 8 - 7 - read-write - - - CAPBANKOUT - Capa bank setting output. - 15 - 7 - read-write - - - CAPTESTSTARTSRCSEL - Source selection for xo32k_captest_start_ao_set. - 22 - 1 - read-write - - - CAPSTART - Sourced from CAPTESTSTART. - 0 - - - CALIB - Sourced from calibration. - 0x1 - - - - - CAPTESTSTART - Start test. - 23 - 1 - read-write - - - CAPTESTENABLE - Enable signal for cap test. - 24 - 1 - read-write - - - CAPTESTOSCINSEL - Select the input for test. - 25 - 1 - read-write - - - OSCOUT - Oscillator output pin (osc_out). - 0 - - - OSCIN - Oscillator input pin (osc_in). - 0x1 - - - - - - - COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x50 - 32 - read-write - 0xA - 0xFF7FFE - - - HYST - Hysteris when hyst = '1'. - 1 - 1 - read-write - - - DISABLE - Hysteresis is disable. - 0 - - - ENABLE - Hysteresis is enable. - 0x1 - - - - - VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). - 2 - 1 - read-write - - - INTERNALREF - Select internal VREF. - 0 - - - VDDA - Select VDDA. - 0x1 - - - - - LOWPOWER - Low power mode. - 3 - 1 - read-write - - - HIGHSPEED - High speed mode. - 0 - - - LOWSPEED - Low power mode (Low speed). - 0x1 - - - - - PMUX - Control word for P multiplexer:. - 4 - 3 - read-write - - - VREF - VREF (See fiedl VREFINPUT). - 0 - - - CMP0_A - Pin P0_0. - 0x1 - - - CMP0_B - Pin P0_9. - 0x2 - - - CMP0_C - Pin P0_18. - 0x3 - - - CMP0_D - Pin P1_14. - 0x4 - - - CMP0_E - Pin P2_23. - 0x5 - - - - - NMUX - Control word for N multiplexer:. - 7 - 3 - read-write - - - VREF - VREF (See field VREFINPUT). - 0 - - - CMP0_A - Pin P0_0. - 0x1 - - - CMP0_B - Pin P0_9. - 0x2 - - - CMP0_C - Pin P0_18. - 0x3 - - - CMP0_D - Pin P1_14. - 0x4 - - - CMP0_E - Pin P2_23. - 0x5 - - - - - VREF - Control reference voltage step, per steps of (VREFINPUT/31). - 10 - 5 - read-write - - - FILTERCGF_SAMPLEMODE - Control the filtering of the Analog Comparator output. - 16 - 2 - read-write - - - BYPASS - Bypass mode. - 0 - - - FILTER1CLK - Filter 1 clock period. - 0x1 - - - FILTER2CLK - Filter 2 clock period. - 0x2 - - - FILTER3CLK - Filter 3 clock period. - 0x3 - - - - - FILTERCGF_CLKDIV - Filter Clock divider. - 18 - 3 - read-write - - - FILTER_1CLK_PERIOD - Filter clock period duration equals 1 Analog Comparator clock period. - 0 - - - FILTER_2CLK_PERIOD - Filter clock period duration equals 2 Analog Comparator clock period. - 0x1 - - - FILTER_4CLK_PERIOD - Filter clock period duration equals 4 Analog Comparator clock period. - 0x2 - - - FILTER_8CLK_PERIOD - Filter clock period duration equals 8 Analog Comparator clock period. - 0x3 - - - FILTER_16CLK_PERIOD - Filter clock period duration equals 16 Analog Comparator clock period. - 0x4 - - - FILTER_32CLK_PERIOD - Filter clock period duration equals 32 Analog Comparator clock period. - 0x5 - - - FILTER_64CLK_PERIOD - Filter clock period duration equals 64 Analog Comparator clock period. - 0x6 - - - FILTER_128CLK_PERIOD - Filter clock period duration equals 128 Analog Comparator clock period. - 0x7 - - - - - - - WAKEUPIOCTRL - Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] - 0x64 - 32 - read-write - 0 - 0xFF - - - RISINGEDGEWAKEUP0 - Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:. - 0 - 1 - read-write - - - DISABLE - Rising edge detection is disable. - 0 - - - ENABLE - Rising edge detection is enable. - 0x1 - - - - - FALLINGEDGEWAKEUP0 - Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:. - 1 - 1 - read-write - - - DISABLE - Falling edge detection is disable. - 0 - - - ENABLE - Falling edge detection is enable. - 0x1 - - - - - RISINGEDGEWAKEUP1 - Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:. - 2 - 1 - read-write - - - DISABLE - Rising edge detection is disable. - 0 - - - ENABLE - Rising edge detection is enable. - 0x1 - - - - - FALLINGEDGEWAKEUP1 - Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:. - 3 - 1 - read-write - - - DISABLE - Falling edge detection is disable. - 0 - - - ENABLE - Falling edge detection is enable. - 0x1 - - - - - RISINGEDGEWAKEUP2 - Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:. - 4 - 1 - read-write - - - DISABLE - Rising edge detection is disable. - 0 - - - ENABLE - Rising edge detection is enable. - 0x1 - - - - - FALLINGEDGEWAKEUP2 - Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:. - 5 - 1 - read-write - - - DISABLE - Falling edge detection is disable. - 0 - - - ENABLE - Falling edge detection is enable. - 0x1 - - - - - RISINGEDGEWAKEUP3 - Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes:. - 6 - 1 - read-write - - - DISABLE - Rising edge detection is disable. - 0 - - - ENABLE - Rising edge detection is enable. - 0x1 - - - - - FALLINGEDGEWAKEUP3 - Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes:. - 7 - 1 - read-write - - - DISABLE - Falling edge detection is disable. - 0 - - - ENABLE - Falling edge detection is enable. - 0x1 - - - - - MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode - 8 - 1 - read-write - - - MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode - 9 - 1 - read-write - - - MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode - 10 - 1 - read-write - - - MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode - 11 - 1 - read-write - - - - - WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode - 0x68 - 32 - read-write - 0 - 0xF - - - WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. - 0 - 1 - read-only - - - NOEVENT - Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. - 0 - - - EVENT - Last wake up from Deep Power down mode was triggred by wake up I/O 0. - 0x1 - - - - - WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. - 1 - 1 - read-write - - - NOEVENT - Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. - 0 - - - EVENT - Last wake up from Deep Power down mode was triggred by wake up I/O 1. - 0x1 - - - - - WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. - 2 - 1 - read-write - - - NOEVENT - Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. - 0 - - - EVENT - Last wake up from Deep Power down mode was triggred by wake up I/O 2. - 0x1 - - - - - WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. - 3 - 1 - read-write - - - NOEVENT - Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. - 0 - - - EVENT - Last wake up from Deep Power down mode was triggred by wake up I/O 3. - 0x1 - - - - - - - STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] - 0x74 - 32 - read-write - 0x6 - 0x7 - - - XTAL32KOK - XTAL oscillator 32 K OK signal. - 0 - 1 - read-only - - - XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. - 2 - 1 - read-write - - - NOFAIL - No oscillation failure has been detetced since the last time this bit has been cleared. - 0 - - - FAILURE - At least one oscillation failure has been detetced since the last time this bit has been cleared. - 0x1 - - - - - - - AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] - 0x84 - 32 - read-write - 0 - 0xFFFFFFFF - - - POR - The last chip reset was caused by a Power On Reset. - 4 - 1 - read-write - - - PADRESET - The last chip reset was caused by a Pin Reset. - 5 - 1 - read-write - - - BODRESET - The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. - 6 - 1 - read-write - - - SYSTEMRESET - The last chip reset was caused by a System Reset requested by the ARM CPU. - 7 - 1 - read-write - - - WDTRESET - The last chip reset was caused by the Watchdog Timer. - 8 - 1 - read-write - - - SWRRESET - The last chip reset was caused by a Software event. - 9 - 1 - read-write - - - DPDRESET_WAKEUPIO - The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode. - 10 - 1 - read-write - - - DPDRESET_RTC - The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode. - 11 - 1 - read-write - - - DPDRESET_OSTIMER - The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode. - 12 - 1 - read-write - - - BOOTERRORCOUNTER - ROM Boot Fatal Error Counter. - 16 - 4 - read-write - - - - - MISCCTRL - Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x90 - 32 - read-write - 0 - 0xFFFF - - - LDODEEPSLEEPREF - Select LDO Deep Sleep reference source. - 0 - 1 - read-write - - - FLASHBUFFER - LDO DEEP Sleep uses Flash buffer biasing as reference. - 0 - - - BGP0P8V - LDO DEEP Sleep uses Band Gap 0.8V as reference. - 0x1 - - - - - LDOMEMHIGHZMODE - Control the activation of LDO MEM High Z mode. - 1 - 1 - read-write - - - DISABLE - LDO MEM High Z mode is disabled. - 0 - - - ENABLE - LDO MEM High Z mode is enabled. - 0x1 - - - - - LOWPWR_FLASH_BUF - no description available - 2 - 1 - read-write - - - MISCCTRL_3_8 - Reserved. - 3 - 5 - read-write - - - MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode - 8 - 1 - read-write - - - MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode - 9 - 1 - read-write - - - MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode - 10 - 1 - read-write - - - MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode - 11 - 1 - read-write - - - DISABLE_BLEED - Controls LDO MEM bleed current. This field is expected to be controlled by the Low Power Software only in DEEP SLEEP low power mode. - 12 - 1 - read-write - - - BLEED_ENABLE - LDO_MEM bleed current is enabled. - 0 - - - BLEED_DISABLE - LDO_MEM bleed current is disabled. Should be set before entering in Deep Sleep low power mode and cleared after wake up from Deep SLeep low power mode. - 0x1 - - - - - MISCCTRL_13_14 - Reserved. - 13 - 2 - read-write - - - WAKUPIO_RST - WAKEUP IO event detector reset control. - 15 - 1 - read-write - - - RELEASED - Wakeup IO is not reset. - 0 - - - ASSERTED - Wakeup IO is reset. - 0x1 - - - - - - - RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] - 0x98 - 32 - read-write - 0x3FF0008 - 0xC7FF800F - - - SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . - 0 - 1 - read-write - - - FRO32K - FRO 32 KHz. - 0 - - - XTAL32K - XTAL 32KHz. - 0x1 - - - - - CLK1KHZDIV - Actual division ratio is : 28 + CLK1KHZDIV. - 1 - 3 - read-write - - - CLK1KHZDIVUPDATEREQ - RTC 1KHz clock Divider status flag. - 15 - 1 - read-write - - - CLK1HZDIV - Actual division ratio is : 31744 + CLK1HZDIV. - 16 - 11 - read-write - - - CLK1HZDIVHALT - Halts the divider counter. - 30 - 1 - read-write - - - CLK1HZDIVUPDATEREQ - RTC 1Hz Divider status flag. - 31 - 1 - read-write - - - - - OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] - 0x9C - 32 - read-write - 0x8 - 0xF - - - SOFTRESET - Active high reset. - 0 - 1 - read-write - - - CLOCKENABLE - Enable OSTIMER 32 KHz clock. - 1 - 1 - read-write - - - DPDWAKEUPENABLE - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode). - 2 - 1 - read-write - - - OSC32KPD - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K. - 3 - 1 - read-write - - - - - PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0xB8 - 32 - read-write - 0xDEFFC4 - 0xFFFFEF - - - PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD). - 3 - 1 - read-write - - - POWEREDON - BOD VBAT is powered. - 0 - - - POWEREDOFF - BOD VBAT is powered down. - 0x1 - - - - - PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. - 6 - 1 - read-write - - - POWEREDON - FRO32KHz is powered. - 0 - - - POWEREDOFF - FRO32KHz is powered down. - 0x1 - - - - - PDEN_XTAL32K - Controls power to crystal 32 KHz. - 7 - 1 - read-write - - - POWEREDON - Crystal 32KHz is powered. - 0 - - - POWEREDOFF - Crystal 32KHz is powered down. - 0x1 - - - - - PDEN_XTAL32M - Controls power to high speed crystal. - 8 - 1 - read-write - - - POWEREDON - High speed crystal is powered. - 0 - - - POWEREDOFF - High speed crystal is powered down. - 0x1 - - - - - PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). - 9 - 1 - read-write - - - POWEREDON - PLL0 is powered. - 0 - - - POWEREDOFF - PLL0 is powered down. - 0x1 - - - - - PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1). - 10 - 1 - read-write - - - POWEREDON - PLL1 is powered. - 0 - - - POWEREDOFF - PLL1 is powered down. - 0x1 - - - - - PDEN_USBFSPHY - Controls power to USB Full Speed phy. - 11 - 1 - read-write - - - POWEREDON - USB Full Speed phy is powered. - 0 - - - POWEREDOFF - USB Full Speed phy is powered down. - 0x1 - - - - - PDEN_USBHSPHY - Controls power to USB High Speed Phy. - 12 - 1 - read-write - - - POWEREDON - USB HS phy is powered. - 0 - - - POWEREDOFF - USB HS phy is powered down. - 0x1 - - - - - PDEN_COMP - Controls power to Analog Comparator. - 13 - 1 - read-write - - - POWEREDON - Analog Comparator is powered. - 0 - - - POWEREDOFF - Analog Comparator is powered down. - 0x1 - - - - - PDEN_LDOUSBHS - Controls power to USB high speed LDO. - 18 - 1 - read-write - - - POWEREDON - USB high speed LDO is powered. - 0 - - - POWEREDOFF - USB high speed LDO is powered down. - 0x1 - - - - - PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS) - 19 - 1 - read-write - - - POWEREDON - auxiliary biasing is powered. - 0 - - - POWEREDOFF - auxiliary biasing is powered down. - 0x1 - - - - - PDEN_LDOXO32M - Controls power to high speed crystal LDO. - 20 - 1 - read-write - - - POWEREDON - High speed crystal LDO is powered. - 0 - - - POWEREDOFF - High speed crystal LDO is powered down. - 0x1 - - - - - PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources. - 22 - 1 - read-write - - - POWEREDON - TRNG clocks are powered. - 0 - - - POWEREDOFF - TRNG clocks are powered down. - 0x1 - - - - - PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. - 23 - 1 - read-write - - - POWEREDON - PLL0 Sread spectrum module is powered. - 0 - - - POWEREDOFF - PLL0 Sread spectrum module is powered down. - 0x1 - - - - - - - PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0xC0 - 32 - write-only - 0 - 0xFFFFFFFF - - - PDRUNCFGSET0 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. - 0 - 32 - write-only - - - - - PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0xC8 - 32 - write-only - 0 - 0xFFFFFFFF - - - PDRUNCFGCLR0 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. - 0 - 32 - write-only - - - - - SRAMCTRL - All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] - 0xD4 - 32 - read-write - 0x1 - 0x1FF - - - SMB - Source Biasing voltage. - 0 - 2 - read-write - - - LOW - Low leakage. - 0 - - - MEDIUM - Medium leakage. - 0x1 - - - HIGHEST - Highest leakage. - 0x2 - - - DISABLE - Disable. - 0x3 - - - - - RM - Read Margin control settings. - 2 - 3 - read-write - - - WM - Write Margin control settings. - 5 - 3 - read-write - - - WRME - Write read margin enable. - 8 - 1 - read-write - - - - - - - SYSCTL - system controller - SYSCTL - 0x40023000 - - 0 - 0x104 - registers - - - - UPDATELCKOUT - update lock out control - 0 - 32 - read-write - 0 - 0x1 - - - UPDATELCKOUT - All Registers - 0 - 1 - read-write - - - NORMAL_MODE - Normal Mode. Can be written to. - 0 - - - PROTECTED_MODE - Protected Mode. Cannot be written to. - 0x1 - - - - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - FCCTRLSEL%s - Selects the source for SCK going into Flexcomm index - 0x40 - 32 - read-write - 0 - 0x3030303 - - - SCKINSEL - Selects the source for SCK going into this Flexcomm. - 0 - 2 - read-writeOnce - - - ORIG_FLEX_I2S_SIGNALS - Selects the dedicated FCn_SCK function for this Flexcomm. - 0 - - - SHARED_SET0_I2S_SIGNALS - SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - 0x1 - - - SHARED_SET1_I2S_SIGNALS - SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - 0x2 - - - - - WSINSEL - Selects the source for WS going into this Flexcomm. - 8 - 2 - read-write - - - ORIG_FLEX_I2S_SIGNALS - Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. - 0 - - - SHARED_SET0_I2S_SIGNALS - WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - 0x1 - - - SHARED_SET1_I2S_SIGNALS - WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - 0x2 - - - - - DATAINSEL - Selects the source for DATA input to this Flexcomm. - 16 - 2 - read-write - - - ORIG_FLEX_I2S_SIGNALS - Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. - 0 - - - SHARED_SET0_I2S_SIGNALS - Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - 0x1 - - - SHARED_SET1_I2S_SIGNALS - Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - 0x2 - - - - - DATAOUTSEL - Selects the source for DATA output from this Flexcomm. - 24 - 2 - read-write - - - ORIG_FLEX_I2S_SIGNALS - Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. - 0 - - - SHARED_SET0_I2S_SIGNALS - Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - 0x1 - - - SHARED_SET1_I2S_SIGNALS - Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - 0x2 - - - - - - - 2 - 0x4 - 0,1 - SHAREDCTRLSET%s - Selects sources and data combinations for shared signal set index. - 0x80 - 32 - read-write - 0 - 0xFF0777 - - - SHAREDSCKSEL - Selects the source for SCK of this shared signal set. - 0 - 3 - read-write - - - FLEXCOMM0 - SCK for this shared signal set comes from Flexcomm 0. - 0 - - - FLEXCOMM1 - SCK for this shared signal set comes from Flexcomm 1. - 0x1 - - - FLEXCOMM2 - SCK for this shared signal set comes from Flexcomm 2. - 0x2 - - - FLEXCOMM3 - SCK for this shared signal set comes from Flexcomm 3. - 0x3 - - - FLEXCOMM4 - SCK for this shared signal set comes from Flexcomm 4. - 0x4 - - - FLEXCOMM5 - SCK for this shared signal set comes from Flexcomm 5. - 0x5 - - - FLEXCOMM6 - SCK for this shared signal set comes from Flexcomm 6. - 0x6 - - - FLEXCOMM7 - SCK for this shared signal set comes from Flexcomm 7. - 0x7 - - - - - SHAREDWSSEL - Selects the source for WS of this shared signal set. - 4 - 3 - read-write - - - FLEXCOMM0 - WS for this shared signal set comes from Flexcomm 0. - 0 - - - FLEXCOMM1 - WS for this shared signal set comes from Flexcomm 1. - 0x1 - - - FLEXCOMM2 - WS for this shared signal set comes from Flexcomm 2. - 0x2 - - - FLEXCOMM3 - WS for this shared signal set comes from Flexcomm 3. - 0x3 - - - FLEXCOMM4 - WS for this shared signal set comes from Flexcomm 4. - 0x4 - - - FLEXCOMM5 - WS for this shared signal set comes from Flexcomm 5. - 0x5 - - - FLEXCOMM6 - WS for this shared signal set comes from Flexcomm 6. - 0x6 - - - FLEXCOMM7 - WS for this shared signal set comes from Flexcomm 7. - 0x7 - - - - - SHAREDDATASEL - Selects the source for DATA input for this shared signal set. - 8 - 3 - read-write - - - FLEXCOMM0 - DATA input for this shared signal set comes from Flexcomm 0. - 0 - - - FLEXCOMM1 - DATA input for this shared signal set comes from Flexcomm 1. - 0x1 - - - FLEXCOMM2 - DATA input for this shared signal set comes from Flexcomm 2. - 0x2 - - - FLEXCOMM3 - DATA input for this shared signal set comes from Flexcomm 3. - 0x3 - - - FLEXCOMM4 - DATA input for this shared signal set comes from Flexcomm 4. - 0x4 - - - FLEXCOMM5 - DATA input for this shared signal set comes from Flexcomm 5. - 0x5 - - - FLEXCOMM6 - DATA input for this shared signal set comes from Flexcomm 6. - 0x6 - - - FLEXCOMM7 - DATA input for this shared signal set comes from Flexcomm 7. - 0x7 - - - - - FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set. - 16 - 1 - read-write - - - INPUT - Data output from FC0 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC0 does contribute to this shared set. - 0x1 - - - - - FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set. - 17 - 1 - read-write - - - INPUT - Data output from FC1 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC1 does contribute to this shared set. - 0x1 - - - - - FC2DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. - 18 - 1 - read-write - - - INPUT - Data output from FC2 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC2 does contribute to this shared set. - 0x1 - - - - - FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set. - 20 - 1 - read-write - - - INPUT - Data output from FC4 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC4 does contribute to this shared set. - 0x1 - - - - - FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set. - 21 - 1 - read-write - - - INPUT - Data output from FC5 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC5 does contribute to this shared set. - 0x1 - - - - - FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set. - 22 - 1 - read-write - - - INPUT - Data output from FC6 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC6 does contribute to this shared set. - 0x1 - - - - - FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set. - 23 - 1 - read-write - - - INPUT - Data output from FC7 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC7 does contribute to this shared set. - 0x1 - - - - - - - USB_HS_STATUS - Status register for USB HS - 0x100 - 32 - read-only - 0 - 0x1C0FF00 - - - USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply. - 0 - 1 - read-only - - - SUPPLY_3V_OK - 3v3 supply is good. - 0 - - - SUPPLY_3V_LOW - 3v3 supply is too low. - 0x1 - - - - - - - - - RTC - Real-Time Clock (RTC) - RTC - 0x4002C000 - - 0 - 0x60 - registers - - - RTC - 29 - - - - CTRL - RTC control register - 0 - 32 - read-write - 0x1 - 0x7FD - - - SWRESET - Software reset control - 0 - 1 - read-write - - - NOT_IN_RESET - Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. - 0 - - - IN_RESET - In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared. - 0x1 - - - - - ALARM1HZ - RTC 1 Hz timer alarm flag status. - 2 - 1 - read-write - - - NO_MATCH - No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. - 0 - - - MATCH - Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. - 0x1 - - - - - WAKE1KHZ - RTC 1 kHz timer wake-up flag status. - 3 - 1 - read-write - - - RUN - Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. - 0 - - - TIMEOUT - Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. - 0x1 - - - - - ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. - 4 - 1 - read-write - - - DISABLE - Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. - 0 - - - ENABLE - Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. - 0x1 - - - - - WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. - 5 - 1 - read-write - - - DISABLE - Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - 0 - - - ENABLE - Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. - 0x1 - - - - - RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). - 6 - 1 - read-write - - - DISABLE - Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - 0 - - - ENABLE - Enable. The 1 kHz RTC timer is enabled. - 0x1 - - - - - RTC_EN - RTC enable. - 7 - 1 - read-write - - - DISABLE - Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register. - 0 - - - ENABLE - Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register. - 0x1 - - - - - RTC_OSC_PD - RTC oscillator power-down control. - 8 - 1 - read-write - - - POWER_UP - See RTC_OSC_BYPASS - 0 - - - POWERED_DOWN - RTC oscillator is powered-down. - 0x1 - - - - - RTC_OSC_BYPASS - RTC oscillator bypass control. - 9 - 1 - read-write - - - USED - The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. - 0 - - - BYPASS - The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. - 0x1 - - - - - RTC_SUBSEC_ENA - RTC Sub-second counter control. - 10 - 1 - read-write - - - POWER_UP - The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second counter, this bit will always read-back as a '0'. - 0 - - - POWERED_DOWN - The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip exits deep power-down mode. - 0x1 - - - - - - - MATCH - RTC match register - 0x4 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. - 0 - 32 - read-write - - - - - COUNT - RTC counter register - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after the RTC_EN bit is set. - 0 - 32 - read-write - - - - - WAKE - High-resolution/wake-up timer control register - 0xC - 32 - read-write - 0 - 0xFFFF - - - VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence. Do not write to this register while counting is in progress. - 0 - 16 - read-write - - - - - SUBSEC - Sub-second counter register - 0x10 - 32 - read-write - 0 - 0xFFFF - - - SUBSEC - A read reflects the current value of the 32KHz sub-second counter. This counter is cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This counter must be re-enabled after exiting deep power-down mode or after the main RTC module is disabled and re-enabled. On modules not equipped with a sub-second counter, this register will read-back as all zeroes. - 0 - 15 - read-only - - - - - 8 - 0x4 - GPREG[%s] - General Purpose register - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied. - 0 - 32 - read-write - - - - - - - OSTIMER - Synchronous OS/Event timer with Wakeup Timer - OSTIMER - 0x4002D000 - - 0 - 0x20 - registers - - - OS_EVENT - 38 - - - - EVTIMERL - EVTIMER Low Register - 0 - 32 - read-only - 0 - 0xFFFFFFFF - - - EVTIMER_COUNT_VALUE - A read reflects the current value of the lower 32 bits of the 42-bits EVTIMER. Note: There is only one EVTIMER, readable from all domains. - 0 - 32 - read-only - - - - - EVTIMERH - EVTIMER High Register - 0x4 - 32 - read-write - 0 - 0xFFFFFFFF - - - EVTIMER_COUNT_VALUE - A read reflects the current value of the upper 10 bits of the 42-bits EVTIMER. Note there is only one EVTIMER, readable from all domains. - 0 - 10 - read-only - - - - - CAPTURE_L - Capture Low Register - 0x8 - 32 - read-only - 0 - 0xFFFFFFFF - - - CAPTURE_VALUE - A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). - 0 - 32 - read-only - - - - - CAPTURE_H - Capture High Register - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPTURE_VALUE - A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). - 0 - 10 - read-only - - - - - MATCH_L - Match Low Register - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCH_VALUE - The value written to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. - 0 - 32 - read-write - - - - - MATCH_H - Match High Register - 0x14 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCH_VALUE - The value written (upper 10 bits) to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. - 0 - 10 - read-write - - - - - OSEVENT_CTRL - OS_EVENT TIMER Control Register - 0x1C - 32 - read-write - 0 - 0x7 - - - OSTIMER_INTRFLAG - This bit is set when a match occurs between the central 42-bits EVTIMER and the value programmed in the match-register pair. This bit is cleared by writing a '1'. Writes to clear this bit are asynchronous. It should be done before a new match value is written into the MATCH_L/H registers. - 0 - 1 - read-write - - - OSTIMER_INTENA - When this bit is '1' an interrupt/wakeup request to the domain processor will be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests due to the OSTIMER_INTR flag are blocked. - 1 - 1 - read-write - - - MATCH_WR_RDY - This bit will be low when it is safe to write to reload the Match Registers. In typical applications it should not be necessary to test this bit. [1] - 2 - 1 - read-only - - - - - - - FLASH - FLASH - FLASH - 0x40034000 - - 0 - 0x1000 - registers - - - - CMD - command register - 0 - 32 - write-only - 0 - 0xFFFFFFFF - - - CMD - command register. - 0 - 32 - write-only - - - - - EVENT - event register - 0x4 - 32 - write-only - 0 - 0x7 - - - RST - When bit is set, the controller and flash are reset. - 0 - 1 - write-only - - - WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active. - 1 - 1 - write-only - - - ABORT - When bit is set, a running program/erase command is aborted. - 2 - 1 - write-only - - - - - STARTA - start (or only) address for next flash command - 0x10 - 32 - read-write - 0 - 0x3FFFF - - - STARTA - Address / Start address for commands that take an address (range) as a parameter. - 0 - 18 - read-write - - - - - STOPA - end address for next flash command, if command operates on address ranges - 0x14 - 32 - read-write - 0 - 0x3FFFF - - - STOPA - Stop address for commands that take an address range as a parameter (the word specified by STOPA is included in the address range). - 0 - 18 - read-write - - - - - 4 - 0x4 - DATAW[%s] - data register, word 0-7; Memory data, or command parameter, or command result. - 0x80 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATAW - no description available - 0 - 32 - read-write - - - - - INT_CLR_ENABLE - Clear interrupt enable bits - 0xFD8 - 32 - write-only - 0 - 0xF - - - FAIL - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - 0 - 1 - write-only - - - ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - 1 - 1 - write-only - - - DONE - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - 2 - 1 - write-only - - - ECC_ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - 3 - 1 - write-only - - - - - INT_SET_ENABLE - Set interrupt enable bits - 0xFDC - 32 - write-only - 0 - 0xF - - - FAIL - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - 0 - 1 - write-only - - - ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - 1 - 1 - write-only - - - DONE - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - 2 - 1 - write-only - - - ECC_ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - 3 - 1 - write-only - - - - - INT_STATUS - Interrupt status bits - 0xFE0 - 32 - read-write - 0 - 0xF - - - FAIL - This status bit is set if execution of a (legal) command failed. - 0 - 1 - read-only - - - ERR - This status bit is set if execution of an illegal command is detected. - 1 - 1 - read-only - - - DONE - This status bit is set at the end of command execution. - 2 - 1 - read-only - - - ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested read, or a speculative read, or reads performed by a controller command), a correctable or uncorrectable error is detected by ECC decoding logic. - 3 - 1 - read-only - - - - - INT_ENABLE - Interrupt enable bits - 0xFE4 - 32 - read-write - 0 - 0xF - - - FAIL - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - 0 - 1 - read-only - - - ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - 1 - 1 - read-only - - - DONE - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - 2 - 1 - read-only - - - ECC_ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - 3 - 1 - read-only - - - - - INT_CLR_STATUS - Clear interrupt status bits - 0xFE8 - 32 - write-only - 0 - 0xF - - - FAIL - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - 0 - 1 - write-only - - - ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - 1 - 1 - write-only - - - DONE - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - 2 - 1 - write-only - - - ECC_ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - 3 - 1 - write-only - - - - - INT_SET_STATUS - Set interrupt status bits - 0xFEC - 32 - write-only - 0 - 0xF - - - FAIL - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - 0 - 1 - write-only - - - ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - 1 - 1 - write-only - - - DONE - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - 2 - 1 - write-only - - - ECC_ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - 3 - 1 - write-only - - - - - MODULE_ID - Controller+Memory module identification - 0xFFC - 32 - read-only - 0xC40F0800 - 0xFFFFFFFF - - - APERTURE - Aperture i. - 0 - 8 - read-only - - - MINOR_REV - Minor revision i. - 8 - 4 - read-only - - - MAJOR_REV - Major revision i. - 12 - 4 - read-only - - - ID - Identifier. - 16 - 16 - read-only - - - - - - - PRINCE - PRINCE - PRINCE - 0x40035000 - - 0 - 0x40 - registers - - - - ENC_ENABLE - Encryption Enable register - 0 - 32 - read-write - 0 - 0x1 - - - EN - Encryption Enable. - 0 - 1 - read-write - - - DISABLED - Encryption of writes to the flash controller DATAW* registers is disabled. - 0 - - - ENABLED - Encryption of writes to the flash controller DATAW* registers is enabled. - 0x1 - - - - - - - MASK_LSB - Data Mask register, 32 Least Significant Bits - 0x4 - 32 - write-only - 0 - 0xFFFFFFFF - - - MASKVAL - Value of the 32 Least Significant Bits of the 64-bit data mask. - 0 - 32 - write-only - - - - - MASK_MSB - Data Mask register, 32 Most Significant Bits - 0x8 - 32 - write-only - 0 - 0xFFFFFFFF - - - MASKVAL - Value of the 32 Most Significant Bits of the 64-bit data mask. - 0 - 32 - write-only - - - - - LOCK - Lock register - 0xC - 32 - read-write - 0 - 0x107 - - - LOCKREG0 - Lock Region 0 registers. - 0 - 1 - read-write - - - DISABLED - Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. - 0 - - - ENABLED - Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. - 0x1 - - - - - LOCKREG1 - Lock Region 1 registers. - 1 - 1 - read-write - - - DISABLED - Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. - 0 - - - ENABLED - Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. - 0x1 - - - - - LOCKREG2 - Lock Region 2 registers. - 2 - 1 - read-write - - - DISABLED - Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. - 0 - - - ENABLED - Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. - 0x1 - - - - - LOCKMASK - Lock the Mask registers. - 8 - 1 - read-write - - - DISABLED - Disabled. MASK_LSB, and MASK_MSB are writable.. - 0 - - - ENABLED - Enabled. MASK_LSB, and MASK_MSB are not writable.. - 0x1 - - - - - - - IV_LSB0 - Initial Vector register for region 0, Least Significant Bits - 0x10 - 32 - write-only - 0 - 0xFFFFFFFF - - - IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - 0 - 32 - write-only - - - - - IV_MSB0 - Initial Vector register for region 0, Most Significant Bits - 0x14 - 32 - write-only - 0 - 0xFFFFFFFF - - - IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - 0 - 32 - write-only - - - - - BASE_ADDR0 - Base Address for region 0 register - 0x18 - 32 - read-write - 0 - 0xFFFFF - - - ADDR_FIXED - Fixed portion of the base address of region 0. - 0 - 18 - read-only - - - ADDR_PRG - Programmable portion of the base address of region 0. - 18 - 2 - read-write - - - - - SR_ENABLE0 - Sub-Region Enable register for region 0 - 0x1C - 32 - read-write - 0 - 0xFFFFFFFF - - - EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0. - 0 - 32 - read-write - - - - - IV_LSB1 - Initial Vector register for region 1, Least Significant Bits - 0x20 - 32 - write-only - 0 - 0xFFFFFFFF - - - IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - 0 - 32 - write-only - - - - - IV_MSB1 - Initial Vector register for region 1, Most Significant Bits - 0x24 - 32 - write-only - 0 - 0xFFFFFFFF - - - IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - 0 - 32 - write-only - - - - - BASE_ADDR1 - Base Address for region 1 register - 0x28 - 32 - read-write - 0x40000 - 0xFFFFF - - - ADDR_FIXED - Fixed portion of the base address of region 1. - 0 - 18 - read-only - - - ADDR_PRG - Programmable portion of the base address of region 1. - 18 - 2 - read-write - - - - - SR_ENABLE1 - Sub-Region Enable register for region 1 - 0x2C - 32 - read-write - 0 - 0xFFFFFFFF - - - EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1. - 0 - 32 - read-write - - - - - IV_LSB2 - Initial Vector register for region 2, Least Significant Bits - 0x30 - 32 - write-only - 0 - 0xFFFFFFFF - - - IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - 0 - 32 - write-only - - - - - IV_MSB2 - Initial Vector register for region 2, Most Significant Bits - 0x34 - 32 - write-only - 0 - 0xFFFFFFFF - - - IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - 0 - 32 - write-only - - - - - BASE_ADDR2 - Base Address for region 2 register - 0x38 - 32 - read-write - 0x80000 - 0xFFFFF - - - ADDR_FIXED - Fixed portion of the base address of region 2. - 0 - 18 - read-only - - - ADDR_PRG - Programmable portion of the base address of region 2. - 18 - 2 - read-write - - - - - SR_ENABLE2 - Sub-Region Enable register for region 2 - 0x3C - 32 - read-write - 0 - 0xFFFFFFFF - - - EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2. - 0 - 32 - read-write - - - - - - - USBPHY - Universal System Bus Physical Layer - USBPHY - 0x40038000 - - 0 - 0x110 - registers - - - USB1_PHY - 46 - - - - PWD - USB PHY Power-Down Register - 0 - 32 - read-write - 0x1E1C00 - 0xFFFFFFFF - - - TXPWDFS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 10 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - 0x1 - - - - - TXPWDIBIAS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 11 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - 0x1 - - - - - TXPWDV2I - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 12 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY transmit V-to-I converter and the current mirror - 0x1 - - - - - RXPWDENV - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 17 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed receiver envelope detector (squelch signal) - 0x1 - - - - - RXPWD1PT1 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 18 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed differential receiver. - 0x1 - - - - - RXPWDDIFF - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 19 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed differential receive - 0x1 - - - - - RXPWDRX - This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 20 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the entire USB PHY receiver block except for the full-speed differential receiver - 0x1 - - - - - - - PWD_SET - USB PHY Power-Down Register - 0x4 - 32 - read-write - 0x1E1C00 - 0xFFFFFFFF - - - TXPWDFS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 10 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - 0x1 - - - - - TXPWDIBIAS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 11 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - 0x1 - - - - - TXPWDV2I - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 12 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY transmit V-to-I converter and the current mirror - 0x1 - - - - - RXPWDENV - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 17 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed receiver envelope detector (squelch signal) - 0x1 - - - - - RXPWD1PT1 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 18 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed differential receiver. - 0x1 - - - - - RXPWDDIFF - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 19 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed differential receive - 0x1 - - - - - RXPWDRX - This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 20 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the entire USB PHY receiver block except for the full-speed differential receiver - 0x1 - - - - - - - PWD_CLR - USB PHY Power-Down Register - 0x8 - 32 - read-write - 0x1E1C00 - 0xFFFFFFFF - - - TXPWDFS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 10 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - 0x1 - - - - - TXPWDIBIAS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 11 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - 0x1 - - - - - TXPWDV2I - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 12 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY transmit V-to-I converter and the current mirror - 0x1 - - - - - RXPWDENV - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 17 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed receiver envelope detector (squelch signal) - 0x1 - - - - - RXPWD1PT1 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 18 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed differential receiver. - 0x1 - - - - - RXPWDDIFF - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 19 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed differential receive - 0x1 - - - - - RXPWDRX - This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 20 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the entire USB PHY receiver block except for the full-speed differential receiver - 0x1 - - - - - - - PWD_TOG - USB PHY Power-Down Register - 0xC - 32 - read-write - 0x1E1C00 - 0xFFFFFFFF - - - TXPWDFS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 10 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - 0x1 - - - - - TXPWDIBIAS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 11 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - 0x1 - - - - - TXPWDV2I - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 12 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY transmit V-to-I converter and the current mirror - 0x1 - - - - - RXPWDENV - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 17 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed receiver envelope detector (squelch signal) - 0x1 - - - - - RXPWD1PT1 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 18 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed differential receiver. - 0x1 - - - - - RXPWDDIFF - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 19 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed differential receive - 0x1 - - - - - RXPWDRX - This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 20 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the entire USB PHY receiver block except for the full-speed differential receiver - 0x1 - - - - - - - TX - USB PHY Transmitter Control Register - 0x10 - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - D_CAL - Decode to trim the nominal 17 - 0 - 4 - read-write - - - value0 - Maximum current, approximately 19% above nominal. - 0 - - - value7 - Nominal - 0x7 - - - value15 - Minimum current, approximately 19% below nominal. - 0xF - - - - - TXCAL45DM - Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin - 8 - 4 - read-write - - - TXENCAL45DN - Enable resistance calibration on DN. - 13 - 1 - read-write - - - TXCAL45DP - Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin - 16 - 4 - read-write - - - TXENCAL45DP - Enable resistance calibration on DP. - 21 - 1 - read-write - - - - - TX_SET - USB PHY Transmitter Control Register - 0x14 - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - D_CAL - Decode to trim the nominal 17 - 0 - 4 - read-write - - - value0 - Maximum current, approximately 19% above nominal. - 0 - - - value7 - Nominal - 0x7 - - - value15 - Minimum current, approximately 19% below nominal. - 0xF - - - - - TXCAL45DM - Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin - 8 - 4 - read-write - - - TXENCAL45DN - Enable resistance calibration on DN. - 13 - 1 - read-write - - - TXCAL45DP - Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin - 16 - 4 - read-write - - - TXENCAL45DP - Enable resistance calibration on DP. - 21 - 1 - read-write - - - - - TX_CLR - USB PHY Transmitter Control Register - 0x18 - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - D_CAL - Decode to trim the nominal 17 - 0 - 4 - read-write - - - value0 - Maximum current, approximately 19% above nominal. - 0 - - - value7 - Nominal - 0x7 - - - value15 - Minimum current, approximately 19% below nominal. - 0xF - - - - - TXCAL45DM - Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin - 8 - 4 - read-write - - - TXENCAL45DN - Enable resistance calibration on DN. - 13 - 1 - read-write - - - TXCAL45DP - Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin - 16 - 4 - read-write - - - TXENCAL45DP - Enable resistance calibration on DP. - 21 - 1 - read-write - - - - - TX_TOG - USB PHY Transmitter Control Register - 0x1C - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - D_CAL - Decode to trim the nominal 17 - 0 - 4 - read-write - - - value0 - Maximum current, approximately 19% above nominal. - 0 - - - value7 - Nominal - 0x7 - - - value15 - Minimum current, approximately 19% below nominal. - 0xF - - - - - TXCAL45DM - Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin - 8 - 4 - read-write - - - TXENCAL45DN - Enable resistance calibration on DN. - 13 - 1 - read-write - - - TXCAL45DP - Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin - 16 - 4 - read-write - - - TXENCAL45DP - Enable resistance calibration on DP. - 21 - 1 - read-write - - - - - RX - USB PHY Receiver Control Register - 0x20 - 32 - read-write - 0 - 0xFFFFFFFF - - - ENVADJ - The ENVADJ field adjusts the trip point for the envelope detector - 0 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.1000 V - 0 - - - value1 - Trip-Level Voltage is 0.1125 V - 0x1 - - - value2 - Trip-Level Voltage is 0.1250 V - 0x2 - - - value3 - Trip-Level Voltage is 0.0875 V - 0x3 - - - - - DISCONADJ - The DISCONADJ field adjusts the trip point for the disconnect detector. - 4 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.56875 V - 0 - - - value1 - Trip-Level Voltage is 0.55000 V - 0x1 - - - value2 - Trip-Level Voltage is 0.58125 V - 0x2 - - - value3 - Trip-Level Voltage is 0.60000 V - 0x3 - - - - - RXDBYPASS - This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver - 22 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - 0x1 - - - - - - - RX_SET - USB PHY Receiver Control Register - 0x24 - 32 - read-write - 0 - 0xFFFFFFFF - - - ENVADJ - The ENVADJ field adjusts the trip point for the envelope detector - 0 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.1000 V - 0 - - - value1 - Trip-Level Voltage is 0.1125 V - 0x1 - - - value2 - Trip-Level Voltage is 0.1250 V - 0x2 - - - value3 - Trip-Level Voltage is 0.0875 V - 0x3 - - - - - DISCONADJ - The DISCONADJ field adjusts the trip point for the disconnect detector. - 4 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.56875 V - 0 - - - value1 - Trip-Level Voltage is 0.55000 V - 0x1 - - - value2 - Trip-Level Voltage is 0.58125 V - 0x2 - - - value3 - Trip-Level Voltage is 0.60000 V - 0x3 - - - - - RXDBYPASS - This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver - 22 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - 0x1 - - - - - - - RX_CLR - USB PHY Receiver Control Register - 0x28 - 32 - read-write - 0 - 0xFFFFFFFF - - - ENVADJ - The ENVADJ field adjusts the trip point for the envelope detector - 0 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.1000 V - 0 - - - value1 - Trip-Level Voltage is 0.1125 V - 0x1 - - - value2 - Trip-Level Voltage is 0.1250 V - 0x2 - - - value3 - Trip-Level Voltage is 0.0875 V - 0x3 - - - - - DISCONADJ - The DISCONADJ field adjusts the trip point for the disconnect detector. - 4 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.56875 V - 0 - - - value1 - Trip-Level Voltage is 0.55000 V - 0x1 - - - value2 - Trip-Level Voltage is 0.58125 V - 0x2 - - - value3 - Trip-Level Voltage is 0.60000 V - 0x3 - - - - - RXDBYPASS - This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver - 22 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - 0x1 - - - - - - - RX_TOG - USB PHY Receiver Control Register - 0x2C - 32 - read-write - 0 - 0xFFFFFFFF - - - ENVADJ - The ENVADJ field adjusts the trip point for the envelope detector - 0 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.1000 V - 0 - - - value1 - Trip-Level Voltage is 0.1125 V - 0x1 - - - value2 - Trip-Level Voltage is 0.1250 V - 0x2 - - - value3 - Trip-Level Voltage is 0.0875 V - 0x3 - - - - - DISCONADJ - The DISCONADJ field adjusts the trip point for the disconnect detector. - 4 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.56875 V - 0 - - - value1 - Trip-Level Voltage is 0.55000 V - 0x1 - - - value2 - Trip-Level Voltage is 0.58125 V - 0x2 - - - value3 - Trip-Level Voltage is 0.60000 V - 0x3 - - - - - RXDBYPASS - This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver - 22 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - 0x1 - - - - - - - CTRL - USB PHY General Control Register - 0x30 - 32 - read-write - 0xC0000000 - 0xFFFFFFFF - - - ENHOSTDISCONDETECT - For host mode, enables high-speed disconnect detector - 1 - 1 - read-write - - - ENIRQHOSTDISCON - Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode - 2 - 1 - read-write - - - HOSTDISCONDETECT_IRQ - Indicates that the device has disconnected in High-Speed mode - 3 - 1 - read-write - - - ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode - 4 - 1 - read-write - - - value0 - Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - 0 - - - value1 - Enables 200kohm pullup resistors on USB_DP and USB_DM pins - 0x1 - - - - - DEVPLUGIN_POLARITY - Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in - 5 - 1 - read-write - - - RESUMEIRQSTICKY - Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it - 8 - 1 - read-write - - - ENIRQRESUMEDETECT - Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line - 9 - 1 - read-write - - - RESUME_IRQ - Resume IRQ: Indicates that the host is sending a wake-up after suspend - 10 - 1 - read-write - - - DEVPLUGIN_IRQ - Indicates that the device is connected - 12 - 1 - read-write - - - ENUTMILEVEL2 - Enables UTMI+ Level 2 operation for the USB HS PHY - 14 - 1 - read-write - - - ENUTMILEVEL3 - Enables UTMI+ Level 3 operation for the USB HS PHY - 15 - 1 - read-write - - - ENIRQWAKEUP - Enable wake-up IRQ: Enables interrupt for the wake-up events. - 16 - 1 - read-write - - - WAKEUP_IRQ - Wake-up IRQ: Indicates that there is a wak-eup event - 17 - 1 - read-write - - - AUTORESUME_EN - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) - 18 - 1 - read-write - - - ENAUTOCLR_CLKGATE - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended - 19 - 1 - read-write - - - ENAUTOCLR_PHY_PWD - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended - 20 - 1 - read-write - - - ENDPDMCHG_WKUP - Enable DP DM change wake-up: Not for customer use - 21 - 1 - read-write - - - ENVBUSCHG_WKUP - Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended - 23 - 1 - read-write - - - ENAUTOCLR_USBCLKGATE - Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 25 - 1 - read-write - - - ENAUTOSET_USBCLKS - Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 26 - 1 - read-write - - - HOST_FORCE_LS_SE0 - Forces the next FS packet that is transmitted to have a EOP with low-speed timing - 28 - 1 - read-write - - - UTMI_SUSPENDM - Used by the PHY to indicate a powered-down state - 29 - 1 - read-write - - - CLKGATE - Gate UTMI Clocks - 30 - 1 - read-write - - - SFTRST - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers - 31 - 1 - read-write - - - - - CTRL_SET - USB PHY General Control Register - 0x34 - 32 - read-write - 0xC0000000 - 0xFFFFFFFF - - - ENHOSTDISCONDETECT - For host mode, enables high-speed disconnect detector - 1 - 1 - read-write - - - ENIRQHOSTDISCON - Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode - 2 - 1 - read-write - - - HOSTDISCONDETECT_IRQ - Indicates that the device has disconnected in High-Speed mode - 3 - 1 - read-write - - - ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode - 4 - 1 - read-write - - - value0 - Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - 0 - - - value1 - Enables 200kohm pullup resistors on USB_DP and USB_DM pins - 0x1 - - - - - DEVPLUGIN_POLARITY - Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in - 5 - 1 - read-write - - - RESUMEIRQSTICKY - Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it - 8 - 1 - read-write - - - ENIRQRESUMEDETECT - Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line - 9 - 1 - read-write - - - RESUME_IRQ - Resume IRQ: Indicates that the host is sending a wake-up after suspend - 10 - 1 - read-write - - - DEVPLUGIN_IRQ - Indicates that the device is connected - 12 - 1 - read-write - - - ENUTMILEVEL2 - Enables UTMI+ Level 2 operation for the USB HS PHY - 14 - 1 - read-write - - - ENUTMILEVEL3 - Enables UTMI+ Level 3 operation for the USB HS PHY - 15 - 1 - read-write - - - ENIRQWAKEUP - Enable wake-up IRQ: Enables interrupt for the wake-up events. - 16 - 1 - read-write - - - WAKEUP_IRQ - Wake-up IRQ: Indicates that there is a wak-eup event - 17 - 1 - read-write - - - AUTORESUME_EN - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) - 18 - 1 - read-write - - - ENAUTOCLR_CLKGATE - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended - 19 - 1 - read-write - - - ENAUTOCLR_PHY_PWD - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended - 20 - 1 - read-write - - - ENDPDMCHG_WKUP - Enable DP DM change wake-up: Not for customer use - 21 - 1 - read-write - - - ENVBUSCHG_WKUP - Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended - 23 - 1 - read-write - - - ENAUTOCLR_USBCLKGATE - Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 25 - 1 - read-write - - - ENAUTOSET_USBCLKS - Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 26 - 1 - read-write - - - HOST_FORCE_LS_SE0 - Forces the next FS packet that is transmitted to have a EOP with low-speed timing - 28 - 1 - read-write - - - UTMI_SUSPENDM - Used by the PHY to indicate a powered-down state - 29 - 1 - read-only - - - CLKGATE - Gate UTMI Clocks - 30 - 1 - read-write - - - SFTRST - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers - 31 - 1 - read-write - - - - - CTRL_CLR - USB PHY General Control Register - 0x38 - 32 - read-write - 0xC0000000 - 0xFFFFFFFF - - - ENHOSTDISCONDETECT - For host mode, enables high-speed disconnect detector - 1 - 1 - read-write - - - ENIRQHOSTDISCON - Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode - 2 - 1 - read-write - - - HOSTDISCONDETECT_IRQ - Indicates that the device has disconnected in High-Speed mode - 3 - 1 - read-write - - - ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode - 4 - 1 - read-write - - - value0 - Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - 0 - - - value1 - Enables 200kohm pullup resistors on USB_DP and USB_DM pins - 0x1 - - - - - DEVPLUGIN_POLARITY - Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in - 5 - 1 - read-write - - - RESUMEIRQSTICKY - Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it - 8 - 1 - read-write - - - ENIRQRESUMEDETECT - Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line - 9 - 1 - read-write - - - RESUME_IRQ - Resume IRQ: Indicates that the host is sending a wake-up after suspend - 10 - 1 - read-write - - - DEVPLUGIN_IRQ - Indicates that the device is connected - 12 - 1 - read-write - - - ENUTMILEVEL2 - Enables UTMI+ Level 2 operation for the USB HS PHY - 14 - 1 - read-write - - - ENUTMILEVEL3 - Enables UTMI+ Level 3 operation for the USB HS PHY - 15 - 1 - read-write - - - ENIRQWAKEUP - Enable wake-up IRQ: Enables interrupt for the wake-up events. - 16 - 1 - read-write - - - WAKEUP_IRQ - Wake-up IRQ: Indicates that there is a wak-eup event - 17 - 1 - read-write - - - AUTORESUME_EN - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) - 18 - 1 - read-write - - - ENAUTOCLR_CLKGATE - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended - 19 - 1 - read-write - - - ENAUTOCLR_PHY_PWD - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended - 20 - 1 - read-write - - - ENDPDMCHG_WKUP - Enable DP DM change wake-up: Not for customer use - 21 - 1 - read-write - - - ENVBUSCHG_WKUP - Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended - 23 - 1 - read-write - - - ENAUTOCLR_USBCLKGATE - Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 25 - 1 - read-write - - - ENAUTOSET_USBCLKS - Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 26 - 1 - read-write - - - HOST_FORCE_LS_SE0 - Forces the next FS packet that is transmitted to have a EOP with low-speed timing - 28 - 1 - read-write - - - UTMI_SUSPENDM - Used by the PHY to indicate a powered-down state - 29 - 1 - read-write - - - CLKGATE - Gate UTMI Clocks - 30 - 1 - read-write - - - SFTRST - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers - 31 - 1 - read-write - - - - - CTRL_TOG - USB PHY General Control Register - 0x3C - 32 - read-write - 0xC0000000 - 0xFFFFFFFF - - - ENHOSTDISCONDETECT - For host mode, enables high-speed disconnect detector - 1 - 1 - read-write - - - ENIRQHOSTDISCON - Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode - 2 - 1 - read-write - - - HOSTDISCONDETECT_IRQ - Indicates that the device has disconnected in High-Speed mode - 3 - 1 - read-write - - - ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode - 4 - 1 - read-write - - - value0 - Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - 0 - - - value1 - Enables 200kohm pullup resistors on USB_DP and USB_DM pins - 0x1 - - - - - DEVPLUGIN_POLARITY - Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in - 5 - 1 - read-write - - - RESUMEIRQSTICKY - Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it - 8 - 1 - read-write - - - ENIRQRESUMEDETECT - Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line - 9 - 1 - read-write - - - RESUME_IRQ - Resume IRQ: Indicates that the host is sending a wake-up after suspend - 10 - 1 - read-write - - - DEVPLUGIN_IRQ - Indicates that the device is connected - 12 - 1 - read-write - - - ENUTMILEVEL2 - Enables UTMI+ Level 2 operation for the USB HS PHY - 14 - 1 - read-write - - - ENUTMILEVEL3 - Enables UTMI+ Level 3 operation for the USB HS PHY - 15 - 1 - read-write - - - ENIRQWAKEUP - Enable wake-up IRQ: Enables interrupt for the wake-up events. - 16 - 1 - read-write - - - WAKEUP_IRQ - Wake-up IRQ: Indicates that there is a wak-eup event - 17 - 1 - read-write - - - AUTORESUME_EN - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) - 18 - 1 - read-write - - - ENAUTOCLR_CLKGATE - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended - 19 - 1 - read-write - - - ENAUTOCLR_PHY_PWD - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended - 20 - 1 - read-write - - - ENDPDMCHG_WKUP - Enable DP DM change wake-up: Not for customer use - 21 - 1 - read-write - - - ENVBUSCHG_WKUP - Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended - 23 - 1 - read-write - - - ENAUTOCLR_USBCLKGATE - Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 25 - 1 - read-write - - - ENAUTOSET_USBCLKS - Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 26 - 1 - read-write - - - HOST_FORCE_LS_SE0 - Forces the next FS packet that is transmitted to have a EOP with low-speed timing - 28 - 1 - read-write - - - UTMI_SUSPENDM - Used by the PHY to indicate a powered-down state - 29 - 1 - read-write - - - CLKGATE - Gate UTMI Clocks - 30 - 1 - read-write - - - SFTRST - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers - 31 - 1 - read-write - - - - - STATUS - USB PHY Status Register - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - OK_STATUS_3V - Indicates the USB 3v power rails are in range. - 0 - 1 - read-only - - - HOSTDISCONDETECT_STATUS - Indicates at the local host (downstream) port that the remote device has disconnected while in High-Speed mode - 3 - 1 - read-only - - - value0 - USB cable disconnect has not been detected at the local host - 0 - - - value1 - USB cable disconnect has been detected at the local host - 0x1 - - - - - DEVPLUGIN_STATUS - Status indicator for non-standard resistive plugged-in detection Indicates that the device has been connected on the USB_DP and USB_DM lines using the nonstandard resistive plugged-in detection method controlled by CTRL[4] - 6 - 1 - read-only - - - value0 - No attachment to a USB host is detected - 0 - - - value1 - Cable attachment to a USB host is detected - 0x1 - - - - - RESUME_STATUS - Indicates that the host is sending a wake-up after Suspend and has triggered an interrupt. - 10 - 1 - read-only - - - - - PLL_SIC - USB PHY PLL Control/Status Register - 0xA0 - 32 - read-write - 0xD12000 - 0xFFFFFFFF - - - PLL_EN_USB_CLKS - Enables the USB clock from PLL to USB PHY - 6 - 1 - read-write - - - PLL_POWER - Power up the USB PLL - 12 - 1 - read-write - - - PLL_ENABLE - Enables the clock output from the USB PLL - 13 - 1 - read-write - - - REFBIAS_PWD_SEL - Reference bias power down select. - 19 - 1 - read-write - - - value0 - Selects PLL_POWER to control the reference bias - 0 - - - value1 - Selects REFBIAS_PWD to control the reference bias - 0x1 - - - - - REFBIAS_PWD - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. - 20 - 1 - read-write - - - PLL_REG_ENABLE - This field controls the USB PLL regulator, set to enable the regulator - 21 - 1 - read-write - - - PLL_DIV_SEL - This field controls the USB PLL feedback loop divider - 22 - 3 - read-write - - - value0 - Divide by 13 - 0 - - - value1 - Divide by 15 - 0x1 - - - value2 - Divide by 16 - 0x2 - - - value3 - Divide by 20 - 0x3 - - - value4 - Divide by 22 - 0x4 - - - value5 - Divide by 25 - 0x5 - - - value6 - Divide by 30 - 0x6 - - - value7 - Divide by 240 - 0x7 - - - - - PLL_PREDIV - This is selection between /1 or /2 to expand the range of ref input clock. - 30 - 1 - read-write - - - PLL_LOCK - USB PLL lock status indicator - 31 - 1 - read-only - - - value0 - PLL is not currently locked - 0 - - - value1 - PLL is currently locked - 0x1 - - - - - - - PLL_SIC_SET - USB PHY PLL Control/Status Register - 0xA4 - 32 - read-write - 0xD12000 - 0xFFFFFFFF - - - PLL_EN_USB_CLKS - Enables the USB clock from PLL to USB PHY - 6 - 1 - read-write - - - PLL_POWER - Power up the USB PLL - 12 - 1 - read-write - - - PLL_ENABLE - Enables the clock output from the USB PLL - 13 - 1 - read-write - - - REFBIAS_PWD_SEL - Reference bias power down select. - 19 - 1 - read-write - - - value0 - Selects PLL_POWER to control the reference bias - 0 - - - value1 - Selects REFBIAS_PWD to control the reference bias - 0x1 - - - - - REFBIAS_PWD - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. - 20 - 1 - read-write - - - PLL_REG_ENABLE - This field controls the USB PLL regulator, set to enable the regulator - 21 - 1 - read-write - - - PLL_DIV_SEL - This field controls the USB PLL feedback loop divider - 22 - 3 - read-write - - - value0 - Divide by 13 - 0 - - - value1 - Divide by 15 - 0x1 - - - value2 - Divide by 16 - 0x2 - - - value3 - Divide by 20 - 0x3 - - - value4 - Divide by 22 - 0x4 - - - value5 - Divide by 25 - 0x5 - - - value6 - Divide by 30 - 0x6 - - - value7 - Divide by 240 - 0x7 - - - - - PLL_PREDIV - This is selection between /1 or /2 to expand the range of ref input clock. - 30 - 1 - read-write - - - PLL_LOCK - USB PLL lock status indicator - 31 - 1 - read-only - - - value0 - PLL is not currently locked - 0 - - - value1 - PLL is currently locked - 0x1 - - - - - - - PLL_SIC_CLR - USB PHY PLL Control/Status Register - 0xA8 - 32 - read-write - 0xD12000 - 0xFFFFFFFF - - - PLL_EN_USB_CLKS - Enables the USB clock from PLL to USB PHY - 6 - 1 - read-write - - - PLL_POWER - Power up the USB PLL - 12 - 1 - read-write - - - PLL_ENABLE - Enables the clock output from the USB PLL - 13 - 1 - read-write - - - REFBIAS_PWD_SEL - Reference bias power down select. - 19 - 1 - read-write - - - value0 - Selects PLL_POWER to control the reference bias - 0 - - - value1 - Selects REFBIAS_PWD to control the reference bias - 0x1 - - - - - REFBIAS_PWD - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. - 20 - 1 - read-write - - - PLL_REG_ENABLE - This field controls the USB PLL regulator, set to enable the regulator - 21 - 1 - read-write - - - PLL_DIV_SEL - This field controls the USB PLL feedback loop divider - 22 - 3 - read-write - - - value0 - Divide by 13 - 0 - - - value1 - Divide by 15 - 0x1 - - - value2 - Divide by 16 - 0x2 - - - value3 - Divide by 20 - 0x3 - - - value4 - Divide by 22 - 0x4 - - - value5 - Divide by 25 - 0x5 - - - value6 - Divide by 30 - 0x6 - - - value7 - Divide by 240 - 0x7 - - - - - PLL_PREDIV - This is selection between /1 or /2 to expand the range of ref input clock. - 30 - 1 - read-write - - - PLL_LOCK - USB PLL lock status indicator - 31 - 1 - read-only - - - value0 - PLL is not currently locked - 0 - - - value1 - PLL is currently locked - 0x1 - - - - - - - PLL_SIC_TOG - USB PHY PLL Control/Status Register - 0xAC - 32 - read-write - 0xD12000 - 0xFFFFFFFF - - - PLL_EN_USB_CLKS - Enables the USB clock from PLL to USB PHY - 6 - 1 - read-write - - - PLL_POWER - Power up the USB PLL - 12 - 1 - read-write - - - PLL_ENABLE - Enables the clock output from the USB PLL - 13 - 1 - read-write - - - REFBIAS_PWD_SEL - Reference bias power down select. - 19 - 1 - read-write - - - value0 - Selects PLL_POWER to control the reference bias - 0 - - - value1 - Selects REFBIAS_PWD to control the reference bias - 0x1 - - - - - REFBIAS_PWD - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. - 20 - 1 - read-write - - - PLL_REG_ENABLE - This field controls the USB PLL regulator, set to enable the regulator - 21 - 1 - read-write - - - PLL_DIV_SEL - This field controls the USB PLL feedback loop divider - 22 - 3 - read-write - - - value0 - Divide by 13 - 0 - - - value1 - Divide by 15 - 0x1 - - - value2 - Divide by 16 - 0x2 - - - value3 - Divide by 20 - 0x3 - - - value4 - Divide by 22 - 0x4 - - - value5 - Divide by 25 - 0x5 - - - value6 - Divide by 30 - 0x6 - - - value7 - Divide by 240 - 0x7 - - - - - PLL_PREDIV - This is selection between /1 or /2 to expand the range of ref input clock. - 30 - 1 - read-write - - - PLL_LOCK - USB PLL lock status indicator - 31 - 1 - read-only - - - value0 - PLL is not currently locked - 0 - - - value1 - PLL is currently locked - 0x1 - - - - - - - USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register - 0xC0 - 32 - read-write - 0x700004 - 0xFFFFFFFF - - - VBUSVALID_THRESH - Sets the threshold for the VBUSVALID comparator - 0 - 3 - read-write - - - value0 - 4.0V - 0 - - - value1 - 4.1V - 0x1 - - - value2 - 4.2V - 0x2 - - - value3 - 4.3V - 0x3 - - - value4 - 4.4V(Default) - 0x4 - - - value5 - 4.5V - 0x5 - - - value6 - 4.6V - 0x6 - - - value7 - 4.7V - 0x7 - - - - - VBUS_OVERRIDE_EN - VBUS detect signal override enable - 3 - 1 - read-write - - - value0 - Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - 0 - - - value1 - Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - 0x1 - - - - - SESSEND_OVERRIDE - Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 - 4 - 1 - read-write - - - BVALID_OVERRIDE - Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 - 5 - 1 - read-write - - - AVALID_OVERRIDE - Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 - 6 - 1 - read-write - - - VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 - 7 - 1 - read-write - - - VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 8 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the VBUS_VALID_3V detector results for signal reported to the USB controller - 0x1 - - - - - VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 9 - 2 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the Session Valid comparator results for signal reported to the USB controller - 0x1 - - - value2 - Use the Session Valid comparator results for signal reported to the USB controller - 0x2 - - - - - ID_OVERRIDE_EN - Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. - 11 - 1 - read-write - - - ID_OVERRIDE - ID override value. - 12 - 1 - read-write - - - EXT_ID_OVERRIDE_EN - Enable ID override using the pinmuxed value: - 13 - 1 - read-write - - - value0 - Select the Muxed value chosen using ID_OVERRIDE_EN. - 0 - - - value1 - Select the external ID value. - 0x1 - - - - - EXT_VBUS_OVERRIDE_EN - Enable VBUS override using the pinmuxed value. - 14 - 1 - read-write - - - value0 - Select the Muxed value chosen using VBUS_OVERRIDE_EN. - 0 - - - value1 - Select the external VBUS VALID value. - 0x1 - - - - - VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator - 18 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator for VBUS_VALID results - 0 - - - value1 - Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - 0x1 - - - - - VBUSVALID_5VDETECT - no description available - 19 - 1 - read-write - - - PWRUP_CMPS - Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector - 20 - 3 - read-write - - - value0 - Powers down the VBUS_VALID comparator - 0 - - - value1 - Enables the VBUS_VALID comparator (default) - 0x7 - - - - - DISCHARGE_VBUS - Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground - 26 - 1 - read-write - - - value0 - VBUS discharge resistor is disabled (Default) - 0 - - - value1 - VBUS discharge resistor is enabled - 0x1 - - - - - - - USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register - 0xC4 - 32 - read-write - 0x700004 - 0xFFFFFFFF - - - VBUSVALID_THRESH - Sets the threshold for the VBUSVALID comparator - 0 - 3 - read-write - - - value0 - 4.0V - 0 - - - value1 - 4.1V - 0x1 - - - value2 - 4.2V - 0x2 - - - value3 - 4.3V - 0x3 - - - value4 - 4.4V(Default) - 0x4 - - - value5 - 4.5V - 0x5 - - - value6 - 4.6V - 0x6 - - - value7 - 4.7V - 0x7 - - - - - VBUS_OVERRIDE_EN - VBUS detect signal override enable - 3 - 1 - read-write - - - value0 - Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - 0 - - - value1 - Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - 0x1 - - - - - SESSEND_OVERRIDE - Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 - 4 - 1 - read-write - - - BVALID_OVERRIDE - Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 - 5 - 1 - read-write - - - AVALID_OVERRIDE - Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 - 6 - 1 - read-write - - - VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 - 7 - 1 - read-write - - - VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 8 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the VBUS_VALID_3V detector results for signal reported to the USB controller - 0x1 - - - - - VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 9 - 2 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the Session Valid comparator results for signal reported to the USB controller - 0x1 - - - value2 - Use the Session Valid comparator results for signal reported to the USB controller - 0x2 - - - - - ID_OVERRIDE_EN - Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. - 11 - 1 - read-write - - - ID_OVERRIDE - ID override value. - 12 - 1 - read-write - - - EXT_ID_OVERRIDE_EN - Enable ID override using the pinmuxed value: - 13 - 1 - read-write - - - value0 - Select the Muxed value chosen using ID_OVERRIDE_EN. - 0 - - - value1 - Select the external ID value. - 0x1 - - - - - EXT_VBUS_OVERRIDE_EN - Enable VBUS override using the pinmuxed value. - 14 - 1 - read-write - - - value0 - Select the Muxed value chosen using VBUS_OVERRIDE_EN. - 0 - - - value1 - Select the external VBUS VALID value. - 0x1 - - - - - VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator - 18 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator for VBUS_VALID results - 0 - - - value1 - Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - 0x1 - - - - - VBUSVALID_5VDETECT - no description available - 19 - 1 - read-write - - - PWRUP_CMPS - Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector - 20 - 3 - read-write - - - value0 - Powers down the VBUS_VALID comparator - 0 - - - value1 - Enables the VBUS_VALID comparator (default) - 0x7 - - - - - DISCHARGE_VBUS - Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground - 26 - 1 - read-write - - - value0 - VBUS discharge resistor is disabled (Default) - 0 - - - value1 - VBUS discharge resistor is enabled - 0x1 - - - - - - - USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register - 0xC8 - 32 - read-write - 0x700004 - 0xFFFFFFFF - - - VBUSVALID_THRESH - Sets the threshold for the VBUSVALID comparator - 0 - 3 - read-write - - - value0 - 4.0V - 0 - - - value1 - 4.1V - 0x1 - - - value2 - 4.2V - 0x2 - - - value3 - 4.3V - 0x3 - - - value4 - 4.4V(Default) - 0x4 - - - value5 - 4.5V - 0x5 - - - value6 - 4.6V - 0x6 - - - value7 - 4.7V - 0x7 - - - - - VBUS_OVERRIDE_EN - VBUS detect signal override enable - 3 - 1 - read-write - - - value0 - Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - 0 - - - value1 - Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - 0x1 - - - - - SESSEND_OVERRIDE - Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 - 4 - 1 - read-write - - - BVALID_OVERRIDE - Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 - 5 - 1 - read-write - - - AVALID_OVERRIDE - Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 - 6 - 1 - read-write - - - VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 - 7 - 1 - read-write - - - VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 8 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the VBUS_VALID_3V detector results for signal reported to the USB controller - 0x1 - - - - - VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 9 - 2 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the Session Valid comparator results for signal reported to the USB controller - 0x1 - - - value2 - Use the Session Valid comparator results for signal reported to the USB controller - 0x2 - - - - - ID_OVERRIDE_EN - Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. - 11 - 1 - read-write - - - ID_OVERRIDE - ID override value. - 12 - 1 - read-write - - - EXT_ID_OVERRIDE_EN - Enable ID override using the pinmuxed value: - 13 - 1 - read-write - - - value0 - Select the Muxed value chosen using ID_OVERRIDE_EN. - 0 - - - value1 - Select the external ID value. - 0x1 - - - - - EXT_VBUS_OVERRIDE_EN - Enable VBUS override using the pin muxed value. - 14 - 1 - read-write - - - value0 - Select the muxed value chosen using VBUS_OVERRIDE_EN. - 0 - - - value1 - Select the external VBUS VALID value. - 0x1 - - - - - VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator - 18 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator for VBUS_VALID results - 0 - - - value1 - Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - 0x1 - - - - - VBUSVALID_5VDETECT - no description available - 19 - 1 - read-write - - - PWRUP_CMPS - Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector - 20 - 3 - read-write - - - value0 - Powers down the VBUS_VALID comparator - 0 - - - value1 - Enables the VBUS_VALID comparator (default) - 0x7 - - - - - DISCHARGE_VBUS - Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground - 26 - 1 - read-write - - - value0 - VBUS discharge resistor is disabled (Default) - 0 - - - value1 - VBUS discharge resistor is enabled - 0x1 - - - - - - - USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register - 0xCC - 32 - read-write - 0x700004 - 0xFFFFFFFF - - - VBUSVALID_THRESH - Sets the threshold for the VBUSVALID comparator - 0 - 3 - read-write - - - value0 - 4.0V - 0 - - - value1 - 4.1V - 0x1 - - - value2 - 4.2V - 0x2 - - - value3 - 4.3V - 0x3 - - - value4 - 4.4V(Default) - 0x4 - - - value5 - 4.5V - 0x5 - - - value6 - 4.6V - 0x6 - - - value7 - 4.7V - 0x7 - - - - - VBUS_OVERRIDE_EN - VBUS detect signal override enable - 3 - 1 - read-write - - - value0 - Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - 0 - - - value1 - Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - 0x1 - - - - - SESSEND_OVERRIDE - Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 - 4 - 1 - read-write - - - BVALID_OVERRIDE - Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 - 5 - 1 - read-write - - - AVALID_OVERRIDE - Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 - 6 - 1 - read-write - - - VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 - 7 - 1 - read-write - - - VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 8 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the VBUS_VALID_3V detector results for signal reported to the USB controller - 0x1 - - - - - VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 9 - 2 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the Session Valid comparator results for signal reported to the USB controller - 0x1 - - - value2 - Use the Session Valid comparator results for signal reported to the USB controller - 0x2 - - - - - ID_OVERRIDE_EN - Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. - 11 - 1 - read-write - - - ID_OVERRIDE - ID override value. - 12 - 1 - read-write - - - EXT_ID_OVERRIDE_EN - Enable ID override using the pin muxed value. - 13 - 1 - read-write - - - value0 - Select the muxed value chosen using ID_OVERRIDE_EN. - 0 - - - value1 - Select the external ID value. - 0x1 - - - - - EXT_VBUS_OVERRIDE_EN - Enable VBUS override using the pin muxed value. - 14 - 1 - read-write - - - value0 - Select the Muxed value chosen using VBUS_OVERRIDE_EN. - 0 - - - value1 - Select the external VBUS VALID value. - 0x1 - - - - - VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator - 18 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator for VBUS_VALID results - 0 - - - value1 - Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - 0x1 - - - - - VBUSVALID_5VDETECT - no description available - 19 - 1 - read-write - - - PWRUP_CMPS - Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector - 20 - 3 - read-write - - - value0 - Powers down the VBUS_VALID comparator - 0 - - - value1 - Enables the VBUS_VALID comparator (default) - 0x7 - - - - - DISCHARGE_VBUS - Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground - 26 - 1 - read-write - - - value0 - VBUS discharge resistor is disabled (Default) - 0 - - - value1 - VBUS discharge resistor is enabled - 0x1 - - - - - - - ANACTRL - USB PHY Analog Control Register - 0x100 - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - LVI_EN - Vow voltage detector enable bit. - 1 - 1 - read-write - - - PFD_CLK_SEL - For normal USB operation, this bit field must remain at value 2'b00. - 2 - 2 - read-write - - - DEV_PULLDOWN - Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins - 10 - 1 - read-write - - - value0 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - 0 - - - value1 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - 0x1 - - - - - - - ANACTRL_SET - USB PHY Analog Control Register - 0x104 - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - LVI_EN - Vow voltage detector enable bit. - 1 - 1 - read-write - - - PFD_CLK_SEL - For normal USB operation, this bit field must remain at value 2'b00. - 2 - 2 - read-write - - - DEV_PULLDOWN - Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins - 10 - 1 - read-write - - - value0 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - 0 - - - value1 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - 0x1 - - - - - - - ANACTRL_CLR - USB PHY Analog Control Register - 0x108 - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - LVI_EN - Vow voltage detector enable bit. - 1 - 1 - read-write - - - PFD_CLK_SEL - For normal USB operation, this bit field must remain at value 2'b00. - 2 - 2 - read-write - - - DEV_PULLDOWN - Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins - 10 - 1 - read-write - - - value0 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - 0 - - - value1 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - 0x1 - - - - - - - ANACTRL_TOG - USB PHY Analog Control Register - 0x10C - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - LVI_EN - Vow voltage detector enable bit. - 1 - 1 - read-write - - - PFD_CLK_SEL - For normal USB operation, this bit field must remain at value 2'b00. - 2 - 2 - read-write - - - DEV_PULLDOWN - Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins - 10 - 1 - read-write - - - value0 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - 0 - - - value1 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - 0x1 - - - - - - - - - RNG - RNG - RNG - 0x4003A000 - - 0 - 0x1000 - registers - - - - RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read - 0 - 32 - read-only - 0 - 0xFFFFFFFF - - - RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read. - 0 - 32 - read-only - - - - - COUNTER_VAL - no description available - 0x8 - 32 - read-write - 0 - 0x1FFF - - - CLK_RATIO - Gives the ratio between the internal clocks frequencies and the register clock frequency for evaluation and certification purposes. - 0 - 8 - read-only - - - REFRESH_CNT - Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER. - 8 - 5 - read-only - - - - - COUNTER_CFG - no description available - 0xC - 32 - read-write - 0 - 0x3FF - - - MODE - 00: disabled 01: update once. - 0 - 2 - read-write - - - CLOCK_SEL - Selects the internal clock on which to compute statistics. - 2 - 3 - read-write - - - SHIFT4X - To be used to add precision to clock_ratio and determine 'entropy refill'. - 5 - 3 - read-write - - - - - ONLINE_TEST_CFG - no description available - 0x10 - 32 - read-write - 0 - 0x7 - - - ACTIVATE - 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER. - 0 - 1 - read-write - - - DATA_SEL - Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10: RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this field. - 1 - 2 - read-write - - - - - ONLINE_TEST_VAL - no description available - 0x14 - 32 - read-write - 0 - 0xFFF - - - LIVE_CHI_SQUARED - This value is updated as described in field 'activate'. - 0 - 4 - read-only - - - MIN_CHI_SQUARED - This field is reset when 'activate'==0. - 4 - 4 - read-only - - - MAX_CHI_SQUARED - This field is reset when 'activate'==0. - 8 - 4 - read-only - - - - - MODULEID - IP identifier - 0xFFC - 32 - read-only - 0xA0B83200 - 0xFFFFFFFF - - - APERTURE - Aperture i. - 0 - 8 - read-only - - - MIN_REV - Minor revision i. - 8 - 4 - read-only - - - MAJ_REV - Major revision i. - 12 - 4 - read-only - - - ID - Identifier. - 16 - 16 - read-only - - - - - - - PUF - PUFCTRL - PUF - 0x4003B000 - - 0 - 0x260 - registers - - - PUF - 56 - - - - CTRL - PUF Control register - 0 - 32 - read-write - 0 - 0x5F - - - zeroize - Begin Zeroize operation for PUF and go to Error state - 0 - 1 - read-write - - - enroll - Begin Enroll operation - 1 - 1 - read-write - - - start - Begin Start operation - 2 - 1 - read-write - - - GENERATEKEY - Begin Set Intrinsic Key operation - 3 - 1 - read-write - - - SETKEY - Begin Set User Key operation - 4 - 1 - read-write - - - GETKEY - Begin Get Key operation - 6 - 1 - read-write - - - - - KEYINDEX - PUF Key Index register - 0x4 - 32 - read-write - 0 - 0xF - - - KEYIDX - Key index for Set Key operations - 0 - 4 - read-write - - - - - KEYSIZE - PUF Key Size register - 0x8 - 32 - read-write - 0 - 0x3F - - - KEYSIZE - Key size for Set Key operations - 0 - 6 - read-write - - - - - STAT - PUF Status register - 0x20 - 32 - read-write - 0x1 - 0xF7 - - - busy - Indicates that operation is in progress - 0 - 1 - read-only - - - SUCCESS - Last operation was successful - 1 - 1 - read-only - - - error - PUF is in the Error state and no operations can be performed - 2 - 1 - read-only - - - KEYINREQ - Request for next part of key - 4 - 1 - read-only - - - KEYOUTAVAIL - Next part of key is available - 5 - 1 - read-only - - - CODEINREQ - Request for next part of AC/KC - 6 - 1 - read-only - - - CODEOUTAVAIL - Next part of AC/KC is available - 7 - 1 - read-only - - - - - ALLOW - PUF Allow register - 0x28 - 32 - read-write - 0 - 0x8F - - - ALLOWENROLL - Enroll operation is allowed - 0 - 1 - read-only - - - ALLOWSTART - Start operation is allowed - 1 - 1 - read-only - - - ALLOWSETKEY - Set Key operations are allowed - 2 - 1 - read-only - - - ALLOWGETKEY - Get Key operation is allowed - 3 - 1 - read-only - - - - - KEYINPUT - PUF Key Input register - 0x40 - 32 - write-only - 0 - 0xFFFFFFFF - - - KEYIN - Key input data - 0 - 32 - write-only - - - - - CODEINPUT - PUF Code Input register - 0x44 - 32 - write-only - 0 - 0xFFFFFFFF - - - CODEIN - AC/KC input data - 0 - 32 - write-only - - - - - CODEOUTPUT - PUF Code Output register - 0x48 - 32 - read-only - 0 - 0xFFFFFFFF - - - CODEOUT - AC/KC output data - 0 - 32 - read-only - - - - - KEYOUTINDEX - PUF Key Output Index register - 0x60 - 32 - read-write - 0 - 0xF - - - KEYOUTIDX - Key index for the key that is currently output via the Key Output register - 0 - 4 - read-only - - - - - KEYOUTPUT - PUF Key Output register - 0x64 - 32 - read-only - 0 - 0xFFFFFFFF - - - KEYOUT - Key output data - 0 - 32 - read-only - - - - - IFSTAT - PUF Interface Status and clear register - 0xDC - 32 - read-write - 0 - 0x1 - - - ERROR - Indicates that an APB error has occurred,Writing logic1 clears the if_error bit - 0 - 1 - read-write - - - - - VERSION - PUF version register. - 0xFC - 32 - read-only - 0 - 0xFFFFFFFF - - - VERSION - Version of the PUF module. - 0 - 32 - read-only - - - - - INTEN - PUF Interrupt Enable - 0x100 - 32 - read-write - 0 - 0xF7 - - - READYEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - 0 - 1 - read-write - - - SUCCESEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - 1 - 1 - read-write - - - ERROREN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - 2 - 1 - read-write - - - KEYINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - 4 - 1 - read-write - - - KEYOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - 5 - 1 - read-write - - - CODEINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - 6 - 1 - read-write - - - CODEOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - 7 - 1 - read-write - - - - - INTSTAT - PUF interrupt status - 0x104 - 32 - read-write - 0 - 0xF7 - - - READY - Triggers on falling edge of busy, write 1 to clear - 0 - 1 - read-write - - - SUCCESS - Level sensitive interrupt, cleared when interrupt source clears - 1 - 1 - read-write - - - ERROR - Level sensitive interrupt, cleared when interrupt source clears - 2 - 1 - read-write - - - KEYINREQ - Level sensitive interrupt, cleared when interrupt source clears - 4 - 1 - read-write - - - KEYOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears - 5 - 1 - read-write - - - CODEINREQ - Level sensitive interrupt, cleared when interrupt source clears - 6 - 1 - read-write - - - CODEOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears - 7 - 1 - read-write - - - - - PWRCTRL - PUF RAM Power Control - 0x108 - 32 - read-write - 0xF8 - 0xFD - - - RAMON - Power on the PUF RAM. - 0 - 1 - read-write - - - RAMSTAT - PUF RAM status. - 1 - 1 - read-write - - - - - CFG - PUF config register for block bits - 0x10C - 32 - read-write - 0 - 0x3 - - - BLOCKENROLL_SETKEY - Block enroll operation. Write 1 to set, cleared on reset. - 0 - 1 - read-write - - - BLOCKKEYOUTPUT - Block set key operation. Write 1 to set, cleared on reset. - 1 - 1 - read-write - - - - - KEYLOCK - Only reset in case of full IC reset - 0x200 - 32 - read-write - 0xAA - 0xFF - - - KEY0 - "10:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is allowed. 00, 01, 11:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." - 0 - 2 - read-write - - - KEY1 - "10:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is allowed. 00, 01, 11:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." - 2 - 2 - read-write - - - KEY2 - "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." - 4 - 2 - read-write - - - KEY3 - "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." - 6 - 2 - read-write - - - - - KEYENABLE - no description available - 0x204 - 32 - read-write - 0x55 - 0xFF - - - KEY0 - "10: Data coming out from PUF Index 0 interface are shifted in KEY0 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY0 register." - 0 - 2 - read-write - - - KEY1 - "10: Data coming out from PUF Index 0 interface are shifted in KEY1 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY1 register." - 2 - 2 - read-write - - - KEY2 - "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY2 register." - 4 - 2 - read-write - - - KEY3 - "10: Data coming out from PUF Index 0 interface are shifted in KEY3 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." - 6 - 2 - read-write - - - - - KEYRESET - Reinitialize Keys shift registers counters - 0x208 - 32 - write-only - 0 - 0xFFFFFFFF - - - KEY0 - 10: Reset KEY0 shift register. Self clearing. Must be done before loading any new key. - 0 - 2 - write-only - - - KEY1 - 10: Reset KEY1 shift register. Self clearing. Must be done before loading any new key. - 2 - 2 - write-only - - - KEY2 - 10: Reset KEY2 shift register. Self clearing. Must be done before loading any new key. - 4 - 2 - write-only - - - KEY3 - 10: Reset KEY3 shift register. Self clearing. Must be done before loading any new key. - 6 - 2 - write-only - - - - - IDXBLK_L - no description available - 0x20C - 32 - read-write - 0x8000AAAA - 0xC000FFFF - - - IDX1 - Use to block PUF index 1 - 2 - 2 - read-write - - - IDX2 - Use to block PUF index 2 - 4 - 2 - read-write - - - IDX3 - Use to block PUF index 3 - 6 - 2 - read-write - - - IDX4 - Use to block PUF index 4 - 8 - 2 - read-write - - - IDX5 - Use to block PUF index 5 - 10 - 2 - read-write - - - IDX6 - Use to block PUF index 6 - 12 - 2 - read-write - - - IDX7 - Use to block PUF index 7 - 14 - 2 - read-write - - - LOCK_IDX - Lock 0 to 7 PUF key indexes - 30 - 2 - write-only - - - - - IDXBLK_H_DP - no description available - 0x210 - 32 - read-write - 0xAAAA - 0xFFFFFFFF - - - IDX8 - Use to block PUF index 8 - 0 - 2 - read-write - - - IDX9 - Use to block PUF index 9 - 2 - 2 - read-write - - - IDX10 - Use to block PUF index 10 - 4 - 2 - read-write - - - IDX11 - Use to block PUF index 11 - 6 - 2 - read-write - - - IDX12 - Use to block PUF index 12 - 8 - 2 - read-write - - - IDX13 - Use to block PUF index 13 - 10 - 2 - read-write - - - IDX14 - Use to block PUF index 14 - 12 - 2 - read-write - - - IDX15 - Use to block PUF index 15 - 14 - 2 - read-write - - - - - 4 - 0x4 - KEYMASK[%s] - Only reset in case of full IC reset - 0x214 - 32 - write-only - 0 - 0xFFFFFFFF - - - KEYMASK - no description available - 0 - 32 - write-only - - - - - IDXBLK_H - no description available - 0x254 - 32 - read-write - 0x8000AAAA - 0xC000FFFF - - - IDX8 - Use to block PUF index 8 - 0 - 2 - read-write - - - IDX9 - Use to block PUF index 9 - 2 - 2 - read-write - - - IDX10 - Use to block PUF index 10 - 4 - 2 - read-write - - - IDX11 - Use to block PUF index 11 - 6 - 2 - read-write - - - IDX12 - Use to block PUF index 12 - 8 - 2 - read-write - - - IDX13 - Use to block PUF index 13 - 10 - 2 - read-write - - - IDX14 - Use to block PUF index 14 - 12 - 2 - read-write - - - IDX15 - Use to block PUF index 15 - 14 - 2 - read-write - - - LOCK_IDX - Lock 8 to 15 PUF key indexes - 30 - 2 - write-only - - - - - IDXBLK_L_DP - no description available - 0x258 - 32 - read-write - 0xAAAA - 0xFFFF - - - IDX1 - Use to block PUF index 1 - 2 - 2 - read-write - - - IDX2 - Use to block PUF index 2 - 4 - 2 - read-write - - - IDX3 - Use to block PUF index 3 - 6 - 2 - read-write - - - IDX4 - Use to block PUF index 4 - 8 - 2 - read-write - - - IDX5 - Use to block PUF index 5 - 10 - 2 - read-write - - - IDX6 - Use to block PUF index 6 - 12 - 2 - read-write - - - IDX7 - Use to block PUF index 7 - 14 - 2 - read-write - - - - - SHIFT_STATUS - no description available - 0x25C - 32 - read-write - 0 - 0xFFFF - - - KEY0 - Index counter from key 0 shift register - 0 - 4 - read-only - - - KEY1 - Index counter from key 1 shift register - 4 - 4 - read-only - - - KEY2 - Index counter from key 2 shift register - 8 - 4 - read-only - - - KEY3 - Index counter from key 3 shift register - 12 - 4 - read-only - - - - - - - PLU - LPC80X Programmable Logic Unit (PLU) - PLU - 0x4003D000 - - 0 - 0xC20 - registers - - - PLU - 52 - - - - 26 - 0x20 - LUT[%s] - no description available - 0 - - 5 - 0x4 - 0,1,2,3,4 - LUT_INP_MUX%s - LUTn input x MUX - 0 - 32 - read-write - 0 - 0x3F - - - LUTn_INPx - Selects the input source to be connected to LUT0 input0. For each LUT, the slot associated with the output from LUTn itself is tied low. - 0 - 6 - read-write - - - plu_inputs0 - The PLU primary inputs 0. - 0 - - - plu_inputs1 - The PLU primary inputs 1. - 0x1 - - - plu_inputs2 - The PLU primary inputs 2. - 0x2 - - - plu_inputs3 - The PLU primary inputs 3. - 0x3 - - - plu_inputs4 - The PLU primary inputs 4. - 0x4 - - - plu_inputs5 - The PLU primary inputs 5. - 0x5 - - - lut_outputs0 - The output of LUT0. - 0x6 - - - lut_outputs1 - The output of LUT1. - 0x7 - - - lut_outputs2 - The output of LUT2. - 0x8 - - - lut_outputs3 - The output of LUT3. - 0x9 - - - lut_outputs4 - The output of LUT4. - 0xA - - - lut_outputs5 - The output of LUT5. - 0xB - - - lut_outputs6 - The output of LUT6. - 0xC - - - lut_outputs7 - The output of LUT7. - 0xD - - - lut_outputs8 - The output of LUT8. - 0xE - - - lut_outputs9 - The output of LUT9. - 0xF - - - lut_outputs10 - The output of LUT10. - 0x10 - - - lut_outputs11 - The output of LUT11. - 0x11 - - - lut_outputs12 - The output of LUT12. - 0x12 - - - lut_outputs13 - The output of LUT13. - 0x13 - - - lut_outputs14 - The output of LUT14. - 0x14 - - - lut_outputs15 - The output of LUT15. - 0x15 - - - lut_outputs16 - The output of LUT16. - 0x16 - - - lut_outputs17 - The output of LUT17. - 0x17 - - - lut_outputs18 - The output of LUT18. - 0x18 - - - lut_outputs19 - The output of LUT19. - 0x19 - - - lut_outputs20 - The output of LUT20. - 0x1A - - - lut_outputs21 - The output of LUT21. - 0x1B - - - lut_outputs22 - The output of LUT22. - 0x1C - - - lut_outputs23 - The output of LUT23. - 0x1D - - - lut_outputs24 - The output of LUT24. - 0x1E - - - lut_outputs25 - The output of LUT25. - 0x1F - - - state0 - state(0). - 0x20 - - - state1 - state(1). - 0x21 - - - state2 - state(2). - 0x22 - - - state3 - state(3). - 0x23 - - - - - - - - 26 - 0x4 - LUT_TRUTH[%s] - Specifies the Truth Table contents for LUTLUTn - 0x800 - 32 - read-write - 0 - 0xFFFFFFFF - - - LUTn_TRUTH - Specifies the Truth Table contents for LUT0.. - 0 - 32 - read-write - - - - - OUTPUTS - Provides the current state of the 8 designated PLU Outputs. - 0x900 - 32 - read-write - 0 - 0xFFFFFFFF - - - OUTPUT_STATE - Provides the current state of the 8 designated PLU Outputs.. - 0 - 8 - read-only - - - - - WAKEINT_CTRL - Wakeup interrupt control for PLU - 0x904 - 32 - read-write - 0 - 0xFFFFFFFF - - - MASK - Interrupt mask (which of the 8 PLU Outputs contribute to interrupt) - 0 - 8 - read-write - - - FILTER_MODE - control input of the PLU, add filtering for glitch. - 8 - 2 - read-write - - - BYPASS - Bypass mode. - 0 - - - FILTER1CLK - Filter 1 clock period. - 0x1 - - - FILTER2CLK - Filter 2 clock period. - 0x2 - - - FILTER3CLK - Filter 3 clock period. - 0x3 - - - - - FILTER_CLKSEL - hclk is divided by 2**filter_clksel. - 10 - 2 - read-write - - - FRO1MHZ - Selects the 1 MHz low-power oscillator as the filter clock. - 0 - - - FRO12MHZ - Selects the 12 Mhz FRO as the filter clock. - 0x1 - - - OTHER_CLOCK - Selects a third filter clock source, if provided. - 0x2 - - - - - LATCH_ENABLE - latch the interrupt , then can be cleared with next bit INTR_CLEAR - 12 - 1 - read-write - - - INTR_CLEAR - Write to clear wakeint_latched - 13 - 1 - read-write - oneToClear - - - - - 8 - 0x4 - OUTPUT_MUX[%s] - Selects the source to be connected to PLU Output OUTPUT_n - 0xC00 - 32 - read-write - 0 - 0xFFFFFFFF - - - OUTPUTn - Selects the source to be connected to PLU Output 0. - 0 - 5 - read-write - - - plu_output0 - The PLU output 0. - 0 - - - plu_output1 - The PLU output 1. - 0x1 - - - plu_output2 - The PLU output 2. - 0x2 - - - plu_output3 - The PLU output 3. - 0x3 - - - plu_output4 - The PLU output 4. - 0x4 - - - plu_output5 - The PLU output 5. - 0x5 - - - plu_output6 - The PLU output 6. - 0x6 - - - plu_output7 - The PLU output 7. - 0x7 - - - plu_output8 - The PLU output 8. - 0x8 - - - plu_output9 - The PLU output 9. - 0x9 - - - plu_output10 - The PLU output 10. - 0xA - - - plu_output11 - The PLU output 11. - 0xB - - - plu_output12 - The PLU output 12. - 0xC - - - plu_output13 - The PLU output 13. - 0xD - - - plu_output14 - The PLU output 14. - 0xE - - - plu_output15 - The PLU output 15. - 0xF - - - plu_output16 - The PLU output 16. - 0x10 - - - plu_output17 - The PLU output 17. - 0x11 - - - plu_output18 - The PLU output 18. - 0x12 - - - plu_output19 - The PLU output 19. - 0x13 - - - plu_output20 - The PLU output 20. - 0x14 - - - plu_output21 - The PLU output 21. - 0x15 - - - plu_output22 - The PLU output 22. - 0x16 - - - plu_output23 - The PLU output 23. - 0x17 - - - plu_output24 - The PLU output 24. - 0x18 - - - plu_output25 - The PLU output 25. - 0x19 - - - state0 - state(0). - 0x1A - - - state1 - state(1). - 0x1B - - - state2 - state(2). - 0x1C - - - state3 - state(3). - 0x1D - - - - - - - - - DMA0 - DMA controller - DMA - DMA - 0x40082000 - - 0 - 0x56C - registers - - - DMA0 - 1 - - - - CTRL - DMA control. - 0 - 32 - read-write - 0 - 0x1 - - - ENABLE - DMA controller master enable. - 0 - 1 - read-write - - - DISABLED - Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled. - 0 - - - ENABLED - Enabled. The DMA controller is enabled. - 0x1 - - - - - - - INTSTAT - Interrupt status. - 0x4 - 32 - read-only - 0 - 0x6 - - - ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. - 1 - 1 - read-only - - - NOT_PENDING - Not pending. No enabled interrupts are pending. - 0 - - - PENDING - Pending. At least one enabled interrupt is pending. - 0x1 - - - - - ACTIVEERRINT - Summarizes whether any error interrupts are pending. - 2 - 1 - read-only - - - NOT_PENDING - Not pending. No error interrupts are pending. - 0 - - - PENDING - Pending. At least one error interrupt is pending. - 0x1 - - - - - - - SRAMBASE - SRAM address of the channel configuration table. - 0x8 - 32 - read-write - 0 - 0xFFFFFE00 - - - OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the table must begin on a 512 byte boundary. - 9 - 23 - read-write - - - - - ENABLESET0 - Channel Enable read and Set for all DMA channels. - 0x20 - 32 - read-write - 0 - 0xFFFFFFFF - - - ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. - 0 - 32 - read-write - - - - - ENABLECLR0 - Channel Enable Clear for all DMA channels. - 0x28 - 32 - write-only - 0 - 0 - - - CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved. - 0 - 32 - write-only - - - - - ACTIVE0 - Channel Active status for all DMA channels. - 0x30 - 32 - read-only - 0 - 0xFFFFFFFF - - - ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. - 0 - 32 - read-only - - - - - BUSY0 - Channel Busy status for all DMA channels. - 0x38 - 32 - read-only - 0 - 0xFFFFFFFF - - - BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. - 0 - 32 - read-only - - - - - ERRINT0 - Error Interrupt status for all DMA channels. - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active. - 0 - 32 - read-write - - - - - INTENSET0 - Interrupt Enable read and Set for all DMA channels. - 0x48 - 32 - read-write - 0 - 0xFFFFFFFF - - - INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. - 0 - 32 - read-write - - - - - INTENCLR0 - Interrupt Enable Clear for all DMA channels. - 0x50 - 32 - write-only - 0 - 0 - - - CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. - 0 - 32 - write-only - - - - - INTA0 - Interrupt A status for all DMA channels. - 0x58 - 32 - read-write - 0 - 0xFFFFFFFF - - - IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. - 0 - 32 - read-write - - - - - INTB0 - Interrupt B status for all DMA channels. - 0x60 - 32 - read-write - 0 - 0xFFFFFFFF - - - IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. - 0 - 32 - read-write - - - - - SETVALID0 - Set ValidPending control bits for all DMA channels. - 0x68 - 32 - write-only - 0 - 0 - - - SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n - 0 - 32 - write-only - - - - - SETTRIG0 - Set Trigger control bits for all DMA channels. - 0x70 - 32 - write-only - 0 - 0 - - - TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. - 0 - 32 - write-only - - - - - ABORT0 - Channel Abort control for all DMA channels. - 0x78 - 32 - write-only - 0 - 0 - - - ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. - 0 - 32 - write-only - - - - - 23 - 0x10 - CHANNEL[%s] - no description available - 0x400 - - CFG - Configuration register for DMA channel . - 0 - 32 - read-write - 0 - 0x7CF73 - - - PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. - 0 - 1 - read-write - - - DISABLED - Disabled. Peripheral DMA requests are disabled. - 0 - - - ENABLED - Enabled. Peripheral DMA requests are enabled. - 0x1 - - - - - HWTRIGEN - Hardware Triggering Enable for this channel. - 1 - 1 - read-write - - - DISABLED - Disabled. Hardware triggering is not used. - 0 - - - ENABLED - Enabled. Use hardware triggering. - 0x1 - - - - - TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. - 4 - 1 - read-write - - - ACTIVE_LOW_FALLING - Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. - 0 - - - ACTIVE_HIGH_RISING - Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. - 0x1 - - - - - TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. - 5 - 1 - read-write - - - EDGE - Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. - 0 - - - LEVEL - Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. - 0x1 - - - - - TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. - 6 - 1 - read-write - - - SINGLE - Single transfer. Hardware trigger causes a single transfer. - 0 - - - BURST - Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. - 0x1 - - - - - BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. - 8 - 4 - read-write - - - SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. - 14 - 1 - read-write - - - DISABLED - Disabled. Source burst wrapping is not enabled for this DMA channel. - 0 - - - ENABLED - Enabled. Source burst wrapping is enabled for this DMA channel. - 0x1 - - - - - DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. - 15 - 1 - read-write - - - DISABLED - Disabled. Destination burst wrapping is not enabled for this DMA channel. - 0 - - - ENABLED - Enabled. Destination burst wrapping is enabled for this DMA channel. - 0x1 - - - - - CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. - 16 - 3 - read-write - - - - - CTLSTAT - Control and status register for DMA channel . - 0x4 - 32 - read-only - 0 - 0x5 - - - VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. - 0 - 1 - read-only - - - NO_EFFECT - No effect. No effect on DMA operation. - 0 - - - VALID_PENDING - Valid pending. - 0x1 - - - - - TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. - 2 - 1 - read-only - - - NOT_TRIGGERED - Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. - 0 - - - TRIGGERED - Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. - 0x1 - - - - - - - XFERCFG - Transfer configuration register for DMA channel . - 0x8 - 32 - read-write - 0 - 0x3FFF33F - - - CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. - 0 - 1 - read-write - - - NOT_VALID - Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. - 0 - - - VALID - Valid. The current channel descriptor is considered valid. - 0x1 - - - - - RELOAD - Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. - 1 - 1 - read-write - - - DISABLED - Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. - 0 - - - ENABLED - Enabled. Reload the channels' control structure when the current descriptor is exhausted. - 0x1 - - - - - SWTRIG - Software Trigger. - 2 - 1 - read-write - - - NOT_SET - Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. - 0 - - - SET - Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. - 0x1 - - - - - CLRTRIG - Clear Trigger. - 3 - 1 - read-write - - - NOT_CLEARED - Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. - 0 - - - CLEARED - Cleared. The trigger is cleared when this descriptor is exhausted - 0x1 - - - - - SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. - 4 - 1 - read-write - - - NO_EFFECT - No effect. - 0 - - - SET - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. - 0x1 - - - - - SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. - 5 - 1 - read-write - - - NO_EFFECT - No effect. - 0 - - - SET - Set. The INTB flag for this channel will be set when the current descriptor is exhausted. - 0x1 - - - - - WIDTH - Transfer width used for this DMA channel. - 8 - 2 - read-write - - - BIT_8 - 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). - 0 - - - BIT_16 - 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). - 0x1 - - - BIT_32 - 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). - 0x2 - - - - - SRCINC - Determines whether the source address is incremented for each DMA transfer. - 12 - 2 - read-write - - - NO_INCREMENT - No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. - 0 - - - WIDTH_X_1 - 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. - 0x1 - - - WIDTH_X_2 - 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. - 0x2 - - - WIDTH_X_4 - 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. - 0x3 - - - - - DSTINC - Determines whether the destination address is incremented for each DMA transfer. - 14 - 2 - read-write - - - NO_INCREMENT - No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. - 0 - - - WIDTH_X_1 - 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. - 0x1 - - - WIDTH_X_2 - 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. - 0x2 - - - WIDTH_X_4 - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. - 0x3 - - - - - XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. - 16 - 10 - read-write - - - - - - - - DMA1 - DMA controller - DMA - 0x400A7000 - - 0 - 0x49C - registers - - - DMA1 - 58 - - - - USB0 - USB 2.0 Device Controller - USB - 0x40084000 - - 0 - 0x38 - registers - - - USB0_NEEDCLK - 27 - - - USB0 - 28 - - - - DEVCMDSTAT - USB Device Command/Status register - 0 - 32 - read-write - 0x800 - 0x171BFBFF - - - DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request. - 0 - 7 - read-write - - - DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. - 7 - 1 - read-write - - - SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. - 8 - 1 - read-write - - - FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: - 9 - 1 - read-write - - - NORMAL - USB_NEEDCLK has normal function. - 0 - - - ALWAYS_ON - USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. - 0x1 - - - - - LPM_SUP - LPM Supported: - 11 - 1 - read-write - - - NO - LPM not supported. - 0 - - - YES - LPM supported. - 0x1 - - - - - INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP - 12 - 1 - read-write - - - DISABLED - Only acknowledged packets generate an interrupt - 0 - - - ENABLED - Both acknowledged and NAKed packets generate interrupts. - 0x1 - - - - - INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP - 13 - 1 - read-write - - - DISABLED - Only acknowledged packets generate an interrupt - 0 - - - ENABLED - Both acknowledged and NAKed packets generate interrupts. - 0x1 - - - - - INTONNAK_CO - Interrupt on NAK for control OUT EP - 14 - 1 - read-write - - - DISABLED - Only acknowledged packets generate an interrupt - 0 - - - ENABLED - Both acknowledged and NAKed packets generate interrupts. - 0x1 - - - - - INTONNAK_CI - Interrupt on NAK for control IN EP - 15 - 1 - read-write - - - DISABLED - Only acknowledged packets generate an interrupt - 0 - - - ENABLED - Both acknowledged and NAKed packets generate interrupts. - 0x1 - - - - - DCON - Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VBUSDEBOUNCED bit is one. - 16 - 1 - read-write - - - DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect. - 17 - 1 - read-write - - - LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one. - 19 - 1 - read-write - - - LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction. - 20 - 1 - read-only - - - DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. - 24 - 1 - read-write - - - DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on its upstream port. The bit is reset by writing a one to it. - 25 - 1 - read-write - - - DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it. - 26 - 1 - read-write - - - VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. - 28 - 1 - read-only - - - - - INFO - USB Info register - 0x4 - 32 - read-write - 0 - 0x7FFF - - - FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device. - 0 - 11 - read-only - - - ERR_CODE - The error code which last occurred: - 11 - 4 - read-write - - - NO_ERROR - No error - 0 - - - PID_ENCODING_ERROR - PID encoding error - 0x1 - - - PID_UNKNOWN - PID unknown - 0x2 - - - PACKET_UNEXPECTED - Packet unexpected - 0x3 - - - TOKEN_CRC_ERROR - Token CRC error - 0x4 - - - DATA_CRC_ERROR - Data CRC error - 0x5 - - - TIMEOUT - Time out - 0x6 - - - BABBLE - Babble - 0x7 - - - TRUNCATED_EOP - Truncated EOP - 0x8 - - - SENT_RECEIVED_NAK - Sent/Received NAK - 0x9 - - - SENT_STALL - Sent Stall - 0xA - - - OVERRUN - Overrun - 0xB - - - SENT_EMPTY_PACKET - Sent empty packet - 0xC - - - BITSTUFF_ERROR - Bitstuff error - 0xD - - - SYNC_ERROR - Sync error - 0xE - - - WRONG_DATA_TOGGLE - Wrong data toggle - 0xF - - - - - MINREV - Minor Revision. - 16 - 8 - read-only - - - MAJREV - Major Revision. - 24 - 8 - read-only - - - - - EPLISTSTART - USB EP Command/Status List start address - 0x8 - 32 - read-write - 0 - 0xFFFFFF00 - - - EP_LIST - Start address of the USB EP Command/Status List. - 8 - 24 - read-write - - - - - DATABUFSTART - USB Data buffer start address - 0xC - 32 - read-write - 0 - 0xFFC00000 - - - DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located. - 22 - 10 - read-write - - - - - LPM - USB Link Power Management register - 0x10 - 32 - read-write - 0 - 0x1FF - - - HIRD_HW - Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token - 0 - 4 - read-only - - - HIRD_SW - Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. - 4 - 4 - read-write - - - DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1. - 8 - 1 - read-write - - - - - EPSKIP - USB Endpoint skip - 0x14 - 32 - read-write - 0 - 0x3FFFFFFF - - - SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. - 0 - 10 - read-write - - - - - EPINUSE - USB Endpoint Buffer in use - 0x18 - 32 - read-write - 0 - 0x3FC - - - BUF - Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 0. 1: HW is accessing buffer 1. - 2 - 8 - read-write - - - - - EPBUFCFG - USB Endpoint Buffer Configuration register - 0x1C - 32 - read-write - 0 - 0x3FC - - - BUF_SB - Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer. - 2 - 8 - read-write - - - - - INTSTAT - USB interrupt status register - 0x20 - 32 - read-write - 0 - 0xC00003FF - - - EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it. - 0 - 1 - read-write - - - EP0IN - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it. - 1 - 1 - read-write - - - EP1OUT - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it. - 2 - 1 - read-write - - - EP1IN - Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it. - 3 - 1 - read-write - - - EP2OUT - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it. - 4 - 1 - read-write - - - EP2IN - Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it. - 5 - 1 - read-write - - - EP3OUT - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it. - 6 - 1 - read-write - - - EP3IN - Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it. - 7 - 1 - read-write - - - EP4OUT - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it. - 8 - 1 - read-write - - - EP4IN - Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it. - 9 - 1 - read-write - - - FRAME_INT - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it. - 30 - 1 - read-write - - - DEV_INT - Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it. - 31 - 1 - read-write - - - - - INTEN - USB interrupt enable register - 0x24 - 32 - read-write - 0 - 0xC00003FF - - - EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. - 0 - 10 - read-write - - - FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. - 30 - 1 - read-write - - - DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. - 31 - 1 - read-write - - - - - INTSETSTAT - USB set interrupt status register - 0x28 - 32 - read-write - 0 - 0xC00003FF - - - EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. - 0 - 10 - read-write - - - FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. - 30 - 1 - read-write - - - DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. - 31 - 1 - read-write - - - - - EPTOGGLE - USB Endpoint toggle register - 0x34 - 32 - read-write - 0 - 0x3FF - - - TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. - 0 - 10 - read-write - - - - - - - SCT0 - SCTimer/PWM (SCT) - SCT - 0x40085000 - - 0 - 0x550 - registers - - - SCT0 - 12 - - - - CONFIG - SCT configuration register - 0 - 32 - read-write - 0x1E00 - 0x61FFF - - - UNIFY - SCT operation - 0 - 1 - read-write - - - DUAL_COUNTER - The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. - 0 - - - UNIFIED_COUNTER - The SCT operates as a unified 32-bit counter. - 0x1 - - - - - CLKMODE - SCT clock mode - 1 - 2 - read-write - - - SYSTEM_CLOCK_MODE - System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. - 0 - - - SAMPLED_SYSTEM_CLOCK_MODE - Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode. - 0x1 - - - SCT_INPUT_CLOCK_MODE - SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. - 0x2 - - - ASYNCHRONOUS_MODE - Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock. - 0x3 - - - - - CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register. - 3 - 4 - read-write - - - INPUT_0_RISING_EDGES - Rising edges on input 0. - 0 - - - INPUT_0_FALLING_EDGE - Falling edges on input 0. - 0x1 - - - INPUT_1_RISING_EDGES - Rising edges on input 1. - 0x2 - - - INPUT_1_FALLING_EDGE - Falling edges on input 1. - 0x3 - - - INPUT_2_RISING_EDGES - Rising edges on input 2. - 0x4 - - - INPUT_2_FALLING_EDGE - Falling edges on input 2. - 0x5 - - - INPUT_3_RISING_EDGES - Rising edges on input 3. - 0x6 - - - INPUT_3_FALLING_EDGE - Falling edges on input 3. - 0x7 - - - INPUT_4_RISING_EDGES - Rising edges on input 4. - 0x8 - - - INPUT_4_FALLING_EDGE - Falling edges on input 4. - 0x9 - - - INPUT_5_RISING_EDGES - Rising edges on input 5. - 0xA - - - INPUT_5_FALLING_EDGE - Falling edges on input 5. - 0xB - - - INPUT_6_RISING_EDGES - Rising edges on input 6. - 0xC - - - INPUT_6_FALLING_EDGE - Falling edges on input 6. - 0xD - - - INPUT_7_RISING_EDGES - Rising edges on input 7. - 0xE - - - INPUT_7_FALLING_EDGE - Falling edges on input 7. - 0xF - - - - - NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. - 7 - 1 - read-write - - - NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. - 8 - 1 - read-write - - - INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field. - 9 - 4 - read-write - - - AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. - 17 - 1 - read-write - - - AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. - 18 - 1 - read-write - - - - - CTRL - SCT control register - 0x4 - 32 - read-write - 0x40004 - 0x1FFF1FFF - - - DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. - 0 - 1 - read-write - - - STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes. - 1 - 1 - read-write - - - HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset. - 2 - 1 - read-write - - - CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. - 3 - 1 - read-write - - - BIDIR_L - L or unified counter direction select - 4 - 1 - read-write - - - UP - Up. The counter counts up to a limit condition, then is cleared to zero. - 0 - - - UP_DOWN - Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. - 0x1 - - - - - PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - 5 - 8 - read-write - - - DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. - 16 - 1 - read-write - - - STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. - 17 - 1 - read-write - - - HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset. - 18 - 1 - read-write - - - CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. - 19 - 1 - read-write - - - BIDIR_H - Direction select - 20 - 1 - read-write - - - UP - The H counter counts up to its limit condition, then is cleared to zero. - 0 - - - UP_DOWN - The H counter counts up to its limit, then counts down to a limit condition or to 0. - 0x1 - - - - - PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - 21 - 8 - read-write - - - - - LIMIT - SCT limit event select register - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - 16 - 16 - read-write - - - - - HALT - SCT halt event select register - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - 16 - 16 - read-write - - - - - STOP - SCT stop event select register - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - 16 - 16 - read-write - - - - - START - SCT start event select register - 0x14 - 32 - read-write - 0 - 0xFFFFFFFF - - - STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - 16 - 16 - read-write - - - - - COUNT - SCT counter register - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter. - 0 - 16 - read-write - - - CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter. - 16 - 16 - read-write - - - - - STATE - SCT state register - 0x44 - 32 - read-write - 0 - 0x1F001F - - - STATE_L - State variable. - 0 - 5 - read-write - - - STATE_H - State variable. - 16 - 5 - read-write - - - - - INPUT - SCT input register - 0x48 - 32 - read-only - 0 - 0xFFFFFFFF - - - AIN0 - Input 0 state. Input 0 state on the last SCT clock edge. - 0 - 1 - read-only - - - AIN1 - Input 1 state. Input 1 state on the last SCT clock edge. - 1 - 1 - read-only - - - AIN2 - Input 2 state. Input 2 state on the last SCT clock edge. - 2 - 1 - read-only - - - AIN3 - Input 3 state. Input 3 state on the last SCT clock edge. - 3 - 1 - read-only - - - AIN4 - Input 4 state. Input 4 state on the last SCT clock edge. - 4 - 1 - read-only - - - AIN5 - Input 5 state. Input 5 state on the last SCT clock edge. - 5 - 1 - read-only - - - AIN6 - Input 6 state. Input 6 state on the last SCT clock edge. - 6 - 1 - read-only - - - AIN7 - Input 7 state. Input 7 state on the last SCT clock edge. - 7 - 1 - read-only - - - AIN8 - Input 8 state. Input 8 state on the last SCT clock edge. - 8 - 1 - read-only - - - AIN9 - Input 9 state. Input 9 state on the last SCT clock edge. - 9 - 1 - read-only - - - AIN10 - Input 10 state. Input 10 state on the last SCT clock edge. - 10 - 1 - read-only - - - AIN11 - Input 11 state. Input 11 state on the last SCT clock edge. - 11 - 1 - read-only - - - AIN12 - Input 12 state. Input 12 state on the last SCT clock edge. - 12 - 1 - read-only - - - AIN13 - Input 13 state. Input 13 state on the last SCT clock edge. - 13 - 1 - read-only - - - AIN14 - Input 14 state. Input 14 state on the last SCT clock edge. - 14 - 1 - read-only - - - AIN15 - Input 15 state. Input 15 state on the last SCT clock edge. - 15 - 1 - read-only - - - SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC. - 16 - 1 - read-only - - - SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC. - 17 - 1 - read-only - - - SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC. - 18 - 1 - read-only - - - SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC. - 19 - 1 - read-only - - - SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC. - 20 - 1 - read-only - - - SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC. - 21 - 1 - read-only - - - SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC. - 22 - 1 - read-only - - - SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC. - 23 - 1 - read-only - - - SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC. - 24 - 1 - read-only - - - SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC. - 25 - 1 - read-only - - - SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC. - 26 - 1 - read-only - - - SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC. - 27 - 1 - read-only - - - SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC. - 28 - 1 - read-only - - - SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC. - 29 - 1 - read-only - - - SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC. - 30 - 1 - read-only - - - SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC. - 31 - 1 - read-only - - - - - REGMODE - SCT match/capture mode register - 0x4C - 32 - read-write - 0 - 0xFFFFFFFF - - - REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match register. 1 = register operates as capture register. - 0 - 16 - read-write - - - REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match registers. 1 = register operates as capture registers. - 16 - 16 - read-write - - - - - OUTPUT - SCT output register - 0x50 - 32 - read-write - 0 - 0xFFFF - - - OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. - 0 - 16 - read-write - - - - - OUTPUTDIRCTRL - SCT output counter direction control register - 0x54 - 32 - read-write - 0 - 0xFFFFFFFF - - - SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. - 0 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. - 2 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. - 4 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. - 6 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. - 8 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. - 10 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. - 12 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. - 14 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. - 16 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. - 18 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. - 20 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. - 22 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. - 24 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. - 26 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. - 28 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. - 30 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - - - RES - SCT conflict resolution register - 0x58 - 32 - read-write - 0 - 0xFFFFFFFF - - - O0RES - Effect of simultaneous set and clear on output 0. - 0 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR0 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O1RES - Effect of simultaneous set and clear on output 1. - 2 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR1 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O2RES - Effect of simultaneous set and clear on output 2. - 4 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output n (or set based on the SETCLR2 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O3RES - Effect of simultaneous set and clear on output 3. - 6 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR3 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O4RES - Effect of simultaneous set and clear on output 4. - 8 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR4 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O5RES - Effect of simultaneous set and clear on output 5. - 10 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR5 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O6RES - Effect of simultaneous set and clear on output 6. - 12 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR6 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O7RES - Effect of simultaneous set and clear on output 7. - 14 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output n (or set based on the SETCLR7 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O8RES - Effect of simultaneous set and clear on output 8. - 16 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR8 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O9RES - Effect of simultaneous set and clear on output 9. - 18 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR9 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O10RES - Effect of simultaneous set and clear on output 10. - 20 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR10 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O11RES - Effect of simultaneous set and clear on output 11. - 22 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR11 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O12RES - Effect of simultaneous set and clear on output 12. - 24 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR12 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O13RES - Effect of simultaneous set and clear on output 13. - 26 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR13 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O14RES - Effect of simultaneous set and clear on output 14. - 28 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR14 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O15RES - Effect of simultaneous set and clear on output 15. - 30 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR15 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - - - DMAREQ0 - SCT DMA request 0 register - 0x5C - 32 - read-write - 0 - 0xC000FFFF - - - DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. - 30 - 1 - read-write - - - DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. - 31 - 1 - read-write - - - - - DMAREQ1 - SCT DMA request 1 register - 0x60 - 32 - read-write - 0 - 0xC000FFFF - - - DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. - 30 - 1 - read-write - - - DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. - 31 - 1 - read-write - - - - - EVEN - SCT event interrupt enable register - 0xF0 - 32 - read-write - 0 - 0xFFFF - - - IEN - The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - - - EVFLAG - SCT event flag register - 0xF4 - 32 - read-write - 0 - 0xFFFF - - - FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - - - CONEN - SCT conflict interrupt enable register - 0xF8 - 32 - read-write - 0 - 0xFFFF - - - NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. - 0 - 16 - read-write - - - - - CONFLAG - SCT conflict flag register - 0xFC - 32 - read-write - 0 - 0xC000FFFF - - - NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. - 0 - 16 - read-write - - - BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful. - 30 - 1 - read-write - - - BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted. - 31 - 1 - read-write - - - - - CAP0 - SCT capture register of capture channel - CAP_MATCH - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH0 - SCT match value register of match channels - CAP_MATCH - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP1 - SCT capture register of capture channel - CAP_MATCH - 0x104 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH1 - SCT match value register of match channels - CAP_MATCH - 0x104 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP2 - SCT capture register of capture channel - CAP_MATCH - 0x108 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH2 - SCT match value register of match channels - CAP_MATCH - 0x108 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP3 - SCT capture register of capture channel - CAP_MATCH - 0x10C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH3 - SCT match value register of match channels - CAP_MATCH - 0x10C - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP4 - SCT capture register of capture channel - CAP_MATCH - 0x110 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH4 - SCT match value register of match channels - CAP_MATCH - 0x110 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP5 - SCT capture register of capture channel - CAP_MATCH - 0x114 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH5 - SCT match value register of match channels - CAP_MATCH - 0x114 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP6 - SCT capture register of capture channel - CAP_MATCH - 0x118 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH6 - SCT match value register of match channels - CAP_MATCH - 0x118 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP7 - SCT capture register of capture channel - CAP_MATCH - 0x11C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH7 - SCT match value register of match channels - CAP_MATCH - 0x11C - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP8 - SCT capture register of capture channel - CAP_MATCH - 0x120 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH8 - SCT match value register of match channels - CAP_MATCH - 0x120 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP9 - SCT capture register of capture channel - CAP_MATCH - 0x124 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH9 - SCT match value register of match channels - CAP_MATCH - 0x124 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP10 - SCT capture register of capture channel - CAP_MATCH - 0x128 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH10 - SCT match value register of match channels - CAP_MATCH - 0x128 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP11 - SCT capture register of capture channel - CAP_MATCH - 0x12C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH11 - SCT match value register of match channels - CAP_MATCH - 0x12C - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP12 - SCT capture register of capture channel - CAP_MATCH - 0x130 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH12 - SCT match value register of match channels - CAP_MATCH - 0x130 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP13 - SCT capture register of capture channel - CAP_MATCH - 0x134 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH13 - SCT match value register of match channels - CAP_MATCH - 0x134 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP14 - SCT capture register of capture channel - CAP_MATCH - 0x138 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH14 - SCT match value register of match channels - CAP_MATCH - 0x138 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP15 - SCT capture register of capture channel - CAP_MATCH - 0x13C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH15 - SCT match value register of match channels - CAP_MATCH - 0x13C - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAPCTRL0 - SCT capture control register - CAPCTRL_MATCHREL - 0x200 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL0 - SCT match reload value register - CAPCTRL_MATCHREL - 0x200 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL1 - SCT capture control register - CAPCTRL_MATCHREL - 0x204 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL1 - SCT match reload value register - CAPCTRL_MATCHREL - 0x204 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL2 - SCT capture control register - CAPCTRL_MATCHREL - 0x208 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL2 - SCT match reload value register - CAPCTRL_MATCHREL - 0x208 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL3 - SCT capture control register - CAPCTRL_MATCHREL - 0x20C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL3 - SCT match reload value register - CAPCTRL_MATCHREL - 0x20C - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL4 - SCT capture control register - CAPCTRL_MATCHREL - 0x210 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL4 - SCT match reload value register - CAPCTRL_MATCHREL - 0x210 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL5 - SCT capture control register - CAPCTRL_MATCHREL - 0x214 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL5 - SCT match reload value register - CAPCTRL_MATCHREL - 0x214 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL6 - SCT capture control register - CAPCTRL_MATCHREL - 0x218 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL6 - SCT match reload value register - CAPCTRL_MATCHREL - 0x218 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL7 - SCT capture control register - CAPCTRL_MATCHREL - 0x21C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL7 - SCT match reload value register - CAPCTRL_MATCHREL - 0x21C - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL8 - SCT capture control register - CAPCTRL_MATCHREL - 0x220 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL8 - SCT match reload value register - CAPCTRL_MATCHREL - 0x220 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL9 - SCT capture control register - CAPCTRL_MATCHREL - 0x224 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL9 - SCT match reload value register - CAPCTRL_MATCHREL - 0x224 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL10 - SCT capture control register - CAPCTRL_MATCHREL - 0x228 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL10 - SCT match reload value register - CAPCTRL_MATCHREL - 0x228 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL11 - SCT capture control register - CAPCTRL_MATCHREL - 0x22C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL11 - SCT match reload value register - CAPCTRL_MATCHREL - 0x22C - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL12 - SCT capture control register - CAPCTRL_MATCHREL - 0x230 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL12 - SCT match reload value register - CAPCTRL_MATCHREL - 0x230 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL13 - SCT capture control register - CAPCTRL_MATCHREL - 0x234 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL13 - SCT match reload value register - CAPCTRL_MATCHREL - 0x234 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL14 - SCT capture control register - CAPCTRL_MATCHREL - 0x238 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL14 - SCT match reload value register - CAPCTRL_MATCHREL - 0x238 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL15 - SCT capture control register - CAPCTRL_MATCHREL - 0x23C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL15 - SCT match reload value register - CAPCTRL_MATCHREL - 0x23C - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - 16 - 0x8 - EV[%s] - no description available - 0x300 - - EV_STATE - SCT event state register 0 - 0 - 32 - read-write - 0 - 0xFFFF - - - STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT. - 0 - 16 - read-write - - - - - EV_CTRL - SCT event control register 0 - 0x4 - 32 - read-write - 0 - 0x7FFFFF - - - MATCHSEL - Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. - 0 - 4 - read-write - - - HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. - 4 - 1 - read-write - - - L_COUNTER - Selects the L state and the L match register selected by MATCHSEL. - 0 - - - H_COUNTER - Selects the H state and the H match register selected by MATCHSEL. - 0x1 - - - - - OUTSEL - Input/output select - 5 - 1 - read-write - - - INPUT - Selects the inputs selected by IOSEL. - 0 - - - OUTPUT - Selects the outputs selected by IOSEL. - 0x1 - - - - - IOSEL - Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. - 6 - 4 - read-write - - - IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . - 10 - 2 - read-write - - - LOW - LOW - 0 - - - RISE - Rise - 0x1 - - - FALL - Fall - 0x2 - - - HIGH - HIGH - 0x3 - - - - - COMBMODE - Selects how the specified match and I/O condition are used and combined. - 12 - 2 - read-write - - - OR - OR. The event occurs when either the specified match or I/O condition occurs. - 0 - - - MATCH - MATCH. Uses the specified match only. - 0x1 - - - IO - IO. Uses the specified I/O condition only. - 0x2 - - - AND - AND. The event occurs when the specified match and I/O condition occur simultaneously. - 0x3 - - - - - STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. - 14 - 1 - read-write - - - ADD - STATEV value is added into STATE (the carry-out is ignored). - 0 - - - LOAD - STATEV value is loaded into STATE. - 0x1 - - - - - STATEV - This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. - 15 - 5 - read-write - - - MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. - 20 - 1 - read-write - - - DIRECTION - Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. - 21 - 2 - read-write - - - DIRECTION_INDEPENDENT - Direction independent. This event is triggered regardless of the count direction. - 0 - - - COUNTING_UP - Counting up. This event is triggered only during up-counting when BIDIR = 1. - 0x1 - - - COUNTING_DOWN - Counting down. This event is triggered only during down-counting when BIDIR = 1. - 0x2 - - - - - - - - 10 - 0x8 - OUT[%s] - no description available - 0x500 - - OUT_SET - SCT output 0 set register - 0 - 32 - read-write - 0 - 0xFFFF - - - SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. - 0 - 16 - read-write - - - - - OUT_CLR - SCT output 0 clear register - 0x4 - 32 - read-write - 0 - 0xFFFF - - - CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. - 0 - 16 - read-write - - - - - - - - FLEXCOMM0 - Flexcomm serial communication - FLEXCOMM - FLEXCOMM - 0x40086000 - - 0 - 0x1000 - registers - - - FLEXCOMM0 - 14 - - - - PSELID - Peripheral Select and Flexcomm ID register. - 0xFF8 - 32 - read-write - 0x101000 - 0xFFFFF0FF - - - PERSEL - Peripheral Select. This field is writable by software. - 0 - 3 - read-write - - - NO_PERIPH_SELECTED - No peripheral selected. - 0 - - - USART - USART function selected. - 0x1 - - - SPI - SPI function selected. - 0x2 - - - I2C - I2C function selected. - 0x3 - - - I2S_TRANSMIT - I2S transmit function selected. - 0x4 - - - I2S_RECEIVE - I2S receive function selected. - 0x5 - - - - - LOCK - Lock the peripheral select. This field is writable by software. - 3 - 1 - read-write - - - UNLOCKED - Peripheral select can be changed by software. - 0 - - - LOCKED - Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. - 0x1 - - - - - USARTPRESENT - USART present indicator. This field is Read-only. - 4 - 1 - read-only - - - NOT_PRESENT - This Flexcomm does not include the USART function. - 0 - - - PRESENT - This Flexcomm includes the USART function. - 0x1 - - - - - SPIPRESENT - SPI present indicator. This field is Read-only. - 5 - 1 - read-only - - - NOT_PRESENT - This Flexcomm does not include the SPI function. - 0 - - - PRESENT - This Flexcomm includes the SPI function. - 0x1 - - - - - I2CPRESENT - I2C present indicator. This field is Read-only. - 6 - 1 - read-only - - - NOT_PRESENT - This Flexcomm does not include the I2C function. - 0 - - - PRESENT - This Flexcomm includes the I2C function. - 0x1 - - - - - I2SPRESENT - I 2S present indicator. This field is Read-only. - 7 - 1 - read-only - - - NOT_PRESENT - This Flexcomm does not include the I2S function. - 0 - - - PRESENT - This Flexcomm includes the I2S function. - 0x1 - - - - - ID - Flexcomm ID. - 12 - 20 - read-only - - - - - PID - Peripheral identification register. - 0xFFC - 32 - read-only - 0 - 0xFFFFFFFF - - - APERTURE - size aperture for the register port on the bus (APB or AHB). - 0 - 8 - read-only - - - MINOR_REV - Minor revision of module implementation. - 8 - 4 - read-only - - - MAJOR_REV - Major revision of module implementation. - 12 - 4 - read-only - - - ID - Module identifier for the selected function. - 16 - 16 - read-only - - - - - - - FLEXCOMM1 - Flexcomm serial communication - FLEXCOMM - 0x40087000 - - 0 - 0x1000 - registers - - - FLEXCOMM1 - 15 - - - - FLEXCOMM2 - Flexcomm serial communication - FLEXCOMM - 0x40088000 - - 0 - 0x1000 - registers - - - FLEXCOMM2 - 16 - - - - FLEXCOMM3 - Flexcomm serial communication - FLEXCOMM - 0x40089000 - - 0 - 0x1000 - registers - - - FLEXCOMM3 - 17 - - - - FLEXCOMM4 - Flexcomm serial communication - FLEXCOMM - 0x4008A000 - - 0 - 0x1000 - registers - - - FLEXCOMM4 - 18 - - - - FLEXCOMM5 - Flexcomm serial communication - FLEXCOMM - 0x40096000 - - 0 - 0x1000 - registers - - - FLEXCOMM5 - 19 - - - - FLEXCOMM6 - Flexcomm serial communication - FLEXCOMM - 0x40097000 - - 0 - 0x1000 - registers - - - FLEXCOMM6 - 20 - - - - FLEXCOMM7 - Flexcomm serial communication - FLEXCOMM - 0x40098000 - - 0 - 0x1000 - registers - - - FLEXCOMM7 - 21 - - - - FLEXCOMM8 - Flexcomm serial communication - FLEXCOMM - 0x4009F000 - - 0 - 0x1000 - registers - - - FLEXCOMM8 - 59 - - - - I2C0 - I2C-bus interfaces - FLEXCOMM0 - I2C - I2C - 0x40086000 - - 0 - 0x1000 - registers - - - FLEXCOMM0 - 14 - - - - CFG - Configuration for shared functions. - 0x800 - 32 - read-write - 0 - 0x3F - - - MSTEN - Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset. - 0 - 1 - read-write - - - DISABLED - Disabled. The I2C Master function is disabled. - 0 - - - ENABLED - Enabled. The I2C Master function is enabled. - 0x1 - - - - - SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. - 1 - 1 - read-write - - - DISABLED - Disabled. The I2C slave function is disabled. - 0 - - - ENABLED - Enabled. The I2C slave function is enabled. - 0x1 - - - - - MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset. - 2 - 1 - read-write - - - DISABLED - Disabled. The I2C Monitor function is disabled. - 0 - - - ENABLED - Enabled. The I2C Monitor function is enabled. - 0x1 - - - - - TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. - 3 - 1 - read-write - - - DISABLED - Disabled. Time-out function is disabled. - 0 - - - ENABLED - Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system. - 0x1 - - - - - MONCLKSTR - Monitor function Clock Stretching. - 4 - 1 - read-write - - - DISABLED - Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical. - 0 - - - ENABLED - Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function. - 0x1 - - - - - HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor. - 5 - 1 - read-write - - - FAST_MODE_PLUS - Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin, - 0 - - - HIGH_SPEED - High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information. - 0x1 - - - - - - - STAT - Status register for Master, Slave, and Monitor functions. - 0x804 - 32 - read-write - 0x801 - 0x30FFF5F - - - MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt. - 0 - 1 - read-only - - - IN_PROGRESS - In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. - 0 - - - PENDING - Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit. - 0x1 - - - - - MSTSTATE - Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses. - 1 - 3 - read-only - - - IDLE - Idle. The Master function is available to be used for a new transaction. - 0 - - - RECEIVE_READY - Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. - 0x1 - - - TRANSMIT_READY - Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. - 0x2 - - - NACK_ADDRESS - NACK Address. Slave NACKed address. - 0x3 - - - NACK_DATA - NACK Data. Slave NACKed transmitted data. - 0x4 - - - - - MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - 4 - 1 - read-write - - - NO_LOSS - No Arbitration Loss has occurred. - 0 - - - ARBITRATION_LOSS - Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. - 0x1 - - - - - MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - 6 - 1 - read-write - - - NO_ERROR - No Start/Stop Error has occurred. - 0 - - - ERROR - The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled. - 0x1 - - - - - SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched. - 8 - 1 - read-only - - - IN_PROGRESS - In progress. The Slave function does not currently need service. - 0 - - - PENDING - Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. - 0x1 - - - - - SLVSTATE - Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes. - 9 - 2 - read-only - - - SLAVE_ADDRESS - Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. - 0 - - - SLAVE_RECEIVE - Slave receive. Received data is available (Slave Receiver mode). - 0x1 - - - SLAVE_TRANSMIT - Slave transmit. Data can be transmitted (Slave Transmitter mode). - 0x2 - - - - - SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. - 11 - 1 - read-only - - - STRETCHING - Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. - 0 - - - NOT_STRETCHING - Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time. - 0x1 - - - - - SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. - 12 - 2 - read-only - - - ADDRESS0 - Address 0. Slave address 0 was matched. - 0 - - - ADDRESS1 - Address 1. Slave address 1 was matched. - 0x1 - - - ADDRESS2 - Address 2. Slave address 2 was matched. - 0x2 - - - ADDRESS3 - Address 3. Slave address 3 was matched. - 0x3 - - - - - SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data. - 14 - 1 - read-only - - - NOT_SELECTED - Not selected. The Slave function is not currently selected. - 0 - - - SELECTED - Selected. The Slave function is currently selected. - 0x1 - - - - - SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. - 15 - 1 - read-write - - - NOT_DESELECTED - Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag. - 0 - - - DESELECTED - Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. - 0x1 - - - - - MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. - 16 - 1 - read-only - - - NO_DATA - No data. The Monitor function does not currently have data available. - 0 - - - DATA_WAITING - Data waiting. The Monitor function has data waiting to be read. - 0x1 - - - - - MONOV - Monitor Overflow flag. - 17 - 1 - read-write - - - NO_OVERRUN - No overrun. Monitor data has not overrun. - 0 - - - OVERRUN - Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. - 0x1 - - - - - MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. - 18 - 1 - read-only - - - INACTIVE - Inactive. The Monitor function considers the I2C bus to be inactive. - 0 - - - ACTIVE - Active. The Monitor function considers the I2C bus to be active. - 0x1 - - - - - MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit. - 19 - 1 - read-write - - - NOT_IDLE - Not idle. The I2C bus is not idle, or this flag has been cleared by software. - 0 - - - IDLE - Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. - 0x1 - - - - - EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle. - 24 - 1 - read-write - - - NO_TIMEOUT - No time-out. I2C bus events have not caused a time-out. - 0 - - - EVEN_TIMEOUT - Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. - 0x1 - - - - - SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. - 25 - 1 - read-write - - - NO_TIMEOUT - No time-out. SCL low time has not caused a time-out. - 0 - - - TIMEOUT - Time-out. SCL low time has caused a time-out. - 0x1 - - - - - - - INTENSET - Interrupt Enable Set and read register. - 0x808 - 32 - read-write - 0 - 0x30B8951 - - - MSTPENDINGEN - Master Pending interrupt Enable. - 0 - 1 - read-write - - - DISABLED - Disabled. The MstPending interrupt is disabled. - 0 - - - ENABLED - Enabled. The MstPending interrupt is enabled. - 0x1 - - - - - MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. - 4 - 1 - read-write - - - DISABLED - Disabled. The MstArbLoss interrupt is disabled. - 0 - - - ENABLED - Enabled. The MstArbLoss interrupt is enabled. - 0x1 - - - - - MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. - 6 - 1 - read-write - - - DISABLED - Disabled. The MstStStpErr interrupt is disabled. - 0 - - - ENABLED - Enabled. The MstStStpErr interrupt is enabled. - 0x1 - - - - - SLVPENDINGEN - Slave Pending interrupt Enable. - 8 - 1 - read-write - - - DISABLED - Disabled. The SlvPending interrupt is disabled. - 0 - - - ENABLED - Enabled. The SlvPending interrupt is enabled. - 0x1 - - - - - SLVNOTSTREN - Slave Not Stretching interrupt Enable. - 11 - 1 - read-write - - - DISABLED - Disabled. The SlvNotStr interrupt is disabled. - 0 - - - ENABLED - Enabled. The SlvNotStr interrupt is enabled. - 0x1 - - - - - SLVDESELEN - Slave Deselect interrupt Enable. - 15 - 1 - read-write - - - DISABLED - Disabled. The SlvDeSel interrupt is disabled. - 0 - - - ENABLED - Enabled. The SlvDeSel interrupt is enabled. - 0x1 - - - - - MONRDYEN - Monitor data Ready interrupt Enable. - 16 - 1 - read-write - - - DISABLED - Disabled. The MonRdy interrupt is disabled. - 0 - - - ENABLED - Enabled. The MonRdy interrupt is enabled. - 0x1 - - - - - MONOVEN - Monitor Overrun interrupt Enable. - 17 - 1 - read-write - - - DISABLED - Disabled. The MonOv interrupt is disabled. - 0 - - - ENABLED - Enabled. The MonOv interrupt is enabled. - 0x1 - - - - - MONIDLEEN - Monitor Idle interrupt Enable. - 19 - 1 - read-write - - - DISABLED - Disabled. The MonIdle interrupt is disabled. - 0 - - - ENABLED - Enabled. The MonIdle interrupt is enabled. - 0x1 - - - - - EVENTTIMEOUTEN - Event time-out interrupt Enable. - 24 - 1 - read-write - - - DISABLED - Disabled. The Event time-out interrupt is disabled. - 0 - - - ENABLED - Enabled. The Event time-out interrupt is enabled. - 0x1 - - - - - SCLTIMEOUTEN - SCL time-out interrupt Enable. - 25 - 1 - read-write - - - DISABLED - Disabled. The SCL time-out interrupt is disabled. - 0 - - - ENABLED - Enabled. The SCL time-out interrupt is enabled. - 0x1 - - - - - - - INTENCLR - Interrupt Enable Clear register. - 0x80C - 32 - write-only - 0 - 0 - - - MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented. - 0 - 1 - write-only - - - MSTARBLOSSCLR - Master Arbitration Loss interrupt clear. - 4 - 1 - write-only - - - MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear. - 6 - 1 - write-only - - - SLVPENDINGCLR - Slave Pending interrupt clear. - 8 - 1 - write-only - - - SLVNOTSTRCLR - Slave Not Stretching interrupt clear. - 11 - 1 - write-only - - - SLVDESELCLR - Slave Deselect interrupt clear. - 15 - 1 - write-only - - - MONRDYCLR - Monitor data Ready interrupt clear. - 16 - 1 - write-only - - - MONOVCLR - Monitor Overrun interrupt clear. - 17 - 1 - write-only - - - MONIDLECLR - Monitor Idle interrupt clear. - 19 - 1 - write-only - - - EVENTTIMEOUTCLR - Event time-out interrupt clear. - 24 - 1 - write-only - - - SCLTIMEOUTCLR - SCL time-out interrupt clear. - 25 - 1 - write-only - - - - - TIMEOUT - Time-out value register. - 0x810 - 32 - read-write - 0xFFFF - 0xFFFF - - - TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. - 0 - 4 - read-write - - - TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock. - 4 - 12 - read-write - - - - - CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. - 0x814 - 32 - read-write - 0 - 0xFFFF - - - DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use. - 0 - 16 - read-write - - - - - INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. - 0x818 - 32 - read-only - 0x801 - 0x30B8951 - - - MSTPENDING - Master Pending. - 0 - 1 - read-only - - - MSTARBLOSS - Master Arbitration Loss flag. - 4 - 1 - read-only - - - MSTSTSTPERR - Master Start/Stop Error flag. - 6 - 1 - read-only - - - SLVPENDING - Slave Pending. - 8 - 1 - read-only - - - SLVNOTSTR - Slave Not Stretching status. - 11 - 1 - read-only - - - SLVDESEL - Slave Deselected flag. - 15 - 1 - read-only - - - MONRDY - Monitor Ready. - 16 - 1 - read-only - - - MONOV - Monitor Overflow flag. - 17 - 1 - read-only - - - MONIDLE - Monitor Idle flag. - 19 - 1 - read-only - - - EVENTTIMEOUT - Event time-out Interrupt flag. - 24 - 1 - read-only - - - SCLTIMEOUT - SCL time-out Interrupt flag. - 25 - 1 - read-only - - - - - MSTCTL - Master control register. - 0x820 - 32 - read-write - 0 - 0xE - - - MSTCONTINUE - Master Continue. This bit is write-only. - 0 - 1 - write-only - - - NO_EFFECT - No effect. - 0 - - - CONTINUE - Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. - 0x1 - - - - - MSTSTART - Master Start control. This bit is write-only. - 1 - 1 - read-write - - - NO_EFFECT - No effect. - 0 - - - START - Start. A Start will be generated on the I2C bus at the next allowed time. - 0x1 - - - - - MSTSTOP - Master Stop control. This bit is write-only. - 2 - 1 - read-write - - - NO_EFFECT - No effect. - 0 - - - STOP - Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode). - 0x1 - - - - - MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write. - 3 - 1 - read-write - - - DISABLED - Disable. No DMA requests are generated for master operation. - 0 - - - ENABLED - Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. - 0x1 - - - - - - - MSTTIME - Master timing configuration. - 0x824 - 32 - read-write - 0x77 - 0x77 - - - MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. - 0 - 3 - read-write - - - CLOCKS_2 - 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. - 0 - - - CLOCKS_3 - 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. - 0x1 - - - CLOCKS_4 - 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. - 0x2 - - - CLOCKS_5 - 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. - 0x3 - - - CLOCKS_6 - 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. - 0x4 - - - CLOCKS_7 - 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. - 0x5 - - - CLOCKS_8 - 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. - 0x6 - - - CLOCKS_9 - 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. - 0x7 - - - - - MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. - 4 - 3 - read-write - - - CLOCKS_2 - 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. - 0 - - - CLOCKS_3 - 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . - 0x1 - - - CLOCKS_4 - 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. - 0x2 - - - CLOCKS_5 - 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. - 0x3 - - - CLOCKS_6 - 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. - 0x4 - - - CLOCKS_7 - 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. - 0x5 - - - CLOCKS_8 - 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. - 0x6 - - - CLOCKS_9 - 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. - 0x7 - - - - - - - MSTDAT - Combined Master receiver and transmitter data register. - 0x828 - 32 - read-write - 0 - 0xFF - - - DATA - Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function. - 0 - 8 - read-write - - - - - SLVCTL - Slave control register. - 0x840 - 32 - read-write - 0 - 0x30B - - - SLVCONTINUE - Slave Continue. - 0 - 1 - read-write - - - NO_EFFECT - No effect. - 0 - - - CONTINUE - Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1. - 0x1 - - - - - SLVNACK - Slave NACK. - 1 - 1 - read-write - - - NO_EFFECT - No effect. - 0 - - - NACK - NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). - 0x1 - - - - - SLVDMA - Slave DMA enable. - 3 - 1 - read-write - - - DISABLED - Disabled. No DMA requests are issued for Slave mode operation. - 0 - - - ENABLED - Enabled. DMA requests are issued for I2C slave data transmission and reception. - 0x1 - - - - - AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt. - 8 - 1 - read-write - - - NORMAL - Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored). - 0 - - - AUTOMATIC_ACK - A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. - 0x1 - - - - - AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation. - 9 - 1 - read-write - - - I2C_WRITE - The expected next operation in Automatic Mode is an I2C write. - 0 - - - I2C_READ - The expected next operation in Automatic Mode is an I2C read. - 0x1 - - - - - - - SLVDAT - Combined Slave receiver and transmitter data register. - 0x844 - 32 - read-write - 0 - 0xFF - - - DATA - Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function. - 0 - 8 - read-write - - - - - SLVADR0 - Slave address register. - 0x848 - 32 - read-write - 0x1 - 0xFF - - - SADISABLE - Slave Address n Disable. - 0 - 1 - read-write - - - ENABLED - Enabled. Slave Address n is enabled. - 0 - - - DISABLED - Ignored Slave Address n is ignored. - 0x1 - - - - - SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. - 1 - 7 - read-write - - - AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations. - 15 - 1 - read-write - - - NORMAL - Normal operation, matching I2C addresses are not ignored. - 0 - - - AUTOMATIC - Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction. - 0x1 - - - - - - - SLVADR1 - Slave address register. - 0x84C - 32 - read-write - 0x1 - 0xFF - - - SADISABLE - Slave Address n Disable. - 0 - 1 - read-write - - - ENABLED - Enabled. Slave Address n is enabled. - 0 - - - DISABLED - Ignored Slave Address n is ignored. - 0x1 - - - - - SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. - 1 - 7 - read-write - - - - - SLVADR2 - Slave address register. - 0x850 - 32 - read-write - 0x1 - 0xFF - - - SADISABLE - Slave Address n Disable. - 0 - 1 - read-write - - - ENABLED - Enabled. Slave Address n is enabled. - 0 - - - DISABLED - Ignored Slave Address n is ignored. - 0x1 - - - - - SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. - 1 - 7 - read-write - - - - - SLVADR3 - Slave address register. - 0x854 - 32 - read-write - 0x1 - 0xFF - - - SADISABLE - Slave Address n Disable. - 0 - 1 - read-write - - - ENABLED - Enabled. Slave Address n is enabled. - 0 - - - DISABLED - Ignored Slave Address n is ignored. - 0x1 - - - - - SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. - 1 - 7 - read-write - - - - - SLVQUAL0 - Slave Qualification for address 0. - 0x858 - 32 - read-write - 0 - 0xFF - - - QUALMODE0 - Qualify mode for slave address 0. - 0 - 1 - read-write - - - MASK - Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. - 0 - - - EXTEND - Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. - 0x1 - - - - - SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). - 1 - 7 - read-write - - - - - MONRXDAT - Monitor receiver data register. - 0x880 - 32 - read-only - 0 - 0x7FF - - - MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. - 0 - 8 - read-only - - - MONSTART - Monitor Received Start. - 8 - 1 - read-only - - - NO_START_DETECTED - No start detected. The Monitor function has not detected a Start event on the I2C bus. - 0 - - - START_DETECTED - Start detected. The Monitor function has detected a Start event on the I2C bus. - 0x1 - - - - - MONRESTART - Monitor Received Repeated Start. - 9 - 1 - read-only - - - NOT_DETECTED - No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. - 0 - - - DETECTED - Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. - 0x1 - - - - - MONNACK - Monitor Received NACK. - 10 - 1 - read-only - - - ACKNOWLEDGED - Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. - 0 - - - NOT_ACKNOWLEDGED - Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. - 0x1 - - - - - - - ID - Peripheral identification register. - 0xFFC - 32 - read-only - 0 - 0xFFFFFFFF - - - APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - 0 - 8 - read-only - - - MINOR_REV - Minor revision of module implementation. - 8 - 4 - read-only - - - MAJOR_REV - Major revision of module implementation. - 12 - 4 - read-only - - - ID - Module identifier for the selected function. - 16 - 16 - read-only - - - - - - - I2C1 - I2C-bus interfaces - FLEXCOMM1 - I2C - 0x40087000 - - 0 - 0x1000 - registers - - - FLEXCOMM1 - 15 - - - - I2C2 - I2C-bus interfaces - FLEXCOMM2 - I2C - 0x40088000 - - 0 - 0x1000 - registers - - - FLEXCOMM2 - 16 - - - - I2C3 - I2C-bus interfaces - FLEXCOMM3 - I2C - 0x40089000 - - 0 - 0x1000 - registers - - - FLEXCOMM3 - 17 - - - - I2C4 - I2C-bus interfaces - FLEXCOMM4 - I2C - 0x4008A000 - - 0 - 0x1000 - registers - - - FLEXCOMM4 - 18 - - - - I2C5 - I2C-bus interfaces - FLEXCOMM5 - I2C - 0x40096000 - - 0 - 0x1000 - registers - - - FLEXCOMM5 - 19 - - - - I2C6 - I2C-bus interfaces - FLEXCOMM6 - I2C - 0x40097000 - - 0 - 0x1000 - registers - - - FLEXCOMM6 - 20 - - - - I2C7 - I2C-bus interfaces - FLEXCOMM7 - I2C - 0x40098000 - - 0 - 0x1000 - registers - - - FLEXCOMM7 - 21 - - - - I2S0 - I2S interface - FLEXCOMM0 - I2S - I2S - 0x40086000 - - 0 - 0x1000 - registers - - - FLEXCOMM0 - 14 - - - - CFG1 - Configuration register 1 for the primary channel pair. - 0xC00 - 32 - read-write - 0 - 0x1F3FFF - - - MAINENABLE - Main enable for I 2S function in this Flexcomm - 0 - 1 - read-write - - - DISABLED - All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags are reset. No other channel pairs can be enabled. - 0 - - - ENABLED - This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. - 0x1 - - - - - DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame. - 1 - 1 - read-write - - - NORMAL - Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. - 0 - - - PAUSE - A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. - 0x1 - - - - - PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. - 2 - 2 - read-write - - - PAIRS_1 - 1 I2S channel pairs in this flexcomm - 0 - - - PAIRS_2 - 2 I2S channel pairs in this flexcomm - 0x1 - - - PAIRS_3 - 3 I2S channel pairs in this flexcomm - 0x2 - - - PAIRS_4 - 4 I2S channel pairs in this flexcomm - 0x3 - - - - - MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. - 4 - 2 - read-write - - - NORMAL_SLAVE_MODE - Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. - 0 - - - WS_SYNC_MASTER - WS synchronized master. WS is received from another master and used to synchronize the generation of SCK, when divided from the Flexcomm function clock. - 0x1 - - - MASTER_USING_SCK - Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. - 0x2 - - - NORMAL_MASTER - Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. - 0x3 - - - - - MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples. - 6 - 2 - read-write - - - CLASSIC_MODE - I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece of left channel data occurring during the first phase, and one pieces of right channel data occurring during the second phase. In this mode, the data region begins one clock after the leading WS edge for the frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. - 0 - - - DSP_MODE_WS_50_DUTYCYCLE - DSP mode where WS has a 50% duty cycle. See remark for mode 0. - 0x1 - - - DSP_MODE_WS_1_CLOCK - DSP mode where WS has a one clock long pulse at the beginning of each data frame. - 0x2 - - - DSP_MODE_WS_1_DATA - DSP mode where WS has a one data slot long pulse at the beginning of each data frame. - 0x3 - - - - - RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. - 8 - 1 - read-write - - - RIGHT_HIGH - The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO bits 31:16 are used for the right channel. - 0 - - - RIGHT_LOW - The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO bits 15:0 are used for the right channel. - 0x1 - - - - - LEFTJUST - Left Justify data. - 9 - 1 - read-write - - - RIGHT_JUSTIFIED - Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data in the stream on the data bus. - 0 - - - LEFT_JUSTIFIED - Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would correspond to left justified data in the stream on the data bus. - 0x1 - - - - - ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers. - 10 - 1 - read-write - - - DUAL_CHANNEL - I2S data for this channel pair is treated as left and right channels. - 0 - - - SINGLE_CHANNEL - I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data for the single channel of data is placed at the clock defined by POSITION. - 0x1 - - - - - SCK_POL - SCK polarity. - 12 - 1 - read-write - - - FALLING_EDGE - Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). - 0 - - - RISING_EDGE - Data is launched on SCK rising edges and sampled on SCK falling edges. - 0x1 - - - - - WS_POL - WS polarity. - 13 - 1 - read-write - - - NOT_INVERTED - Data frames begin at a falling edge of WS (standard for classic I2S). - 0 - - - INVERTED - WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). - 0x1 - - - - - DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the I2S: Determines the size of data transfers between the FIFO and the I2S serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = data is 32 bits in length - 16 - 5 - read-write - - - - - CFG2 - Configuration register 2 for the primary channel pair. - 0xC04 - 32 - read-write - 0 - 0x1FF01FF - - - FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger than DATALEN in order for the WS pulse to be generated correctly. - 0 - 9 - read-write - - - POSITION - Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION defines the location of data in both the left phase and right phase, starting one clock after the WS edge. In other modes, POSITION defines the location of data within the entire frame. ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS phase. 0x002 = data begins at bit position 2 within the frame or WS phase. - 16 - 9 - read-write - - - - - STAT - Status register for the primary channel pair. - 0xC08 - 32 - read-write - 0 - 0xD - - - BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. - 0 - 1 - read-only - - - IDLE - The transmitter/receiver for channel pair is currently idle. - 0 - - - BUSY - The transmitter/receiver for channel pair is currently processing data. - 0x1 - - - - - SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream. - 1 - 1 - write-only - - - NO_ERROR - No error has been recorded. - 0 - - - ERROR - An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. - 0x1 - - - - - LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair. - 2 - 1 - read-only - - - LEFT_CHANNEL - Left channel. - 0 - - - RIGHT_CHANNEL - Right channel. - 0x1 - - - - - DATAPAUSED - Data Paused status flag. Applies to all I2S channels - 3 - 1 - read-only - - - NOT_PAUSED - Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. - 0 - - - PAUSED - A data pause has been requested and is now in force. - 0x1 - - - - - - - DIV - Clock divider, used by all channel pairs. - 0xC1C - 32 - read-write - 0 - 0xFFF - - - DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is divided by 4,096. - 0 - 12 - read-write - - - - - FIFOCFG - FIFO configuration and enable register. - 0xE00 - 32 - read-write - 0 - 0x7F033 - - - ENABLETX - Enable the transmit FIFO. - 0 - 1 - read-write - - - DISABLED - The transmit FIFO is not enabled. - 0 - - - ENABLED - The transmit FIFO is enabled. - 0x1 - - - - - ENABLERX - Enable the receive FIFO. - 1 - 1 - read-write - - - DISABLED - The receive FIFO is not enabled. - 0 - - - ENABLED - The receive FIFO is enabled. - 0x1 - - - - - TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused. - 2 - 1 - read-write - - - LAST_VALUE - If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 bits or less, or when MONO = 1 for this channel pair. - 0 - - - ZERO - If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. - 0x1 - - - - - PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. - 3 - 1 - read-write - - - BIT_24 - 48-bit I2S FIFO entries are handled as all 24-bit values. - 0 - - - BIT_32_16 - 48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. - 0x1 - - - - - SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - 4 - 2 - read-only - - - DMATX - DMA configuration for transmit. - 12 - 1 - read-write - - - DISABLED - DMA is not used for the transmit function. - 0 - - - ENABLED - Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - 0x1 - - - - - DMARX - DMA configuration for receive. - 13 - 1 - read-write - - - DISABLED - DMA is not used for the receive function. - 0 - - - ENABLED - Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - 0x1 - - - - - WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 14 - 1 - read-write - - - DISABLED - Only enabled interrupts will wake up the device form reduced power modes. - 0 - - - ENABLED - A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. - 0x1 - - - - - WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 15 - 1 - read-write - - - DISABLED - Only enabled interrupts will wake up the device form reduced power modes. - 0 - - - ENABLED - A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. - 0x1 - - - - - EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - 16 - 1 - read-write - - - EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - 17 - 1 - read-write - - - - - FIFOSTAT - FIFO status register. - 0xE04 - 32 - read-write - 0x30 - 0x1F1FFB - - - TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. - 0 - 1 - read-write - - - RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - 1 - 1 - read-write - - - PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. - 3 - 1 - read-only - - - TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - 4 - 1 - read-only - - - TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. - 5 - 1 - read-only - - - RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - 6 - 1 - read-only - - - RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. - 7 - 1 - read-only - - - TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. - 8 - 5 - read-only - - - RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. - 16 - 5 - read-only - - - - - FIFOTRIG - FIFO trigger settings for interrupt and DMA request. - 0xE08 - 32 - read-write - 0 - 0xF0F03 - - - TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - 0 - 1 - read-write - - - DISABLED - Transmit FIFO level does not generate a FIFO level trigger. - 0 - - - ENABLED - An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - 0x1 - - - - - RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - 1 - 1 - read-write - - - DISABLED - Receive FIFO level does not generate a FIFO level trigger. - 0 - - - ENABLED - An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - 0x1 - - - - - TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). - 8 - 4 - read-write - - - RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). - 16 - 4 - read-write - - - - - FIFOINTENSET - FIFO interrupt enable set (enable) and read register. - 0xE10 - 32 - read-write - 0 - 0xF - - - TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - 0 - 1 - read-write - - - DISABLED - No interrupt will be generated for a transmit error. - 0 - - - ENABLED - An interrupt will be generated when a transmit error occurs. - 0x1 - - - - - RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - 1 - 1 - read-write - - - DISABLED - No interrupt will be generated for a receive error. - 0 - - - ENABLED - An interrupt will be generated when a receive error occurs. - 0x1 - - - - - TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 2 - 1 - read-write - - - DISABLED - No interrupt will be generated based on the TX FIFO level. - 0 - - - ENABLED - If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. - 0x1 - - - - - RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 3 - 1 - read-write - - - DISABLED - No interrupt will be generated based on the RX FIFO level. - 0 - - - ENABLED - If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. - 0x1 - - - - - - - FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. - 0xE14 - 32 - read-write - 0 - 0xF - - - TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - 0 - 1 - read-write - - - RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - 1 - 1 - read-write - - - TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - 2 - 1 - read-write - - - RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - 3 - 1 - read-write - - - - - FIFOINTSTAT - FIFO interrupt status register. - 0xE18 - 32 - read-only - 0 - 0x1F - - - TXERR - TX FIFO error. - 0 - 1 - read-only - - - RXERR - RX FIFO error. - 1 - 1 - read-only - - - TXLVL - Transmit FIFO level interrupt. - 2 - 1 - read-only - - - RXLVL - Receive FIFO level interrupt. - 3 - 1 - read-only - - - PERINT - Peripheral interrupt. - 4 - 1 - read-only - - - - - FIFOWR - FIFO write data. - 0xE20 - 32 - write-only - 0 - 0 - - - TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details. - 0 - 32 - write-only - - - - - FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. - 0xE24 - 32 - write-only - 0 - 0 - - - TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. - 0 - 24 - write-only - - - - - FIFORD - FIFO read data. - 0xE30 - 32 - read-only - 0 - 0 - - - RXDATA - Received data from the FIFO. The number of bits used depends on configuration details. - 0 - 32 - read-only - - - - - FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. - 0xE34 - 32 - read-only - 0 - 0xFFFFFF - - - RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. - 0 - 24 - read-only - - - - - FIFORDNOPOP - FIFO data read with no FIFO pop. - 0xE40 - 32 - read-only - 0 - 0 - - - RXDATA - Received data from the FIFO. - 0 - 32 - read-only - - - - - FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. - 0xE44 - 32 - read-only - 0 - 0xFFFFFF - - - RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. - 0 - 24 - read-only - - - - - FIFOSIZE - FIFO size register - 0xE48 - 32 - read-write - 0x8 - 0xFFFFFFFF - - - FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - 0 - 5 - read-only - - - - - ID - I2S Module identification - 0xFFC - 32 - read-only - 0xE0900000 - 0xFFFFFFFF - - - APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - 0 - 8 - read-only - - - MINOR_REV - Minor revision of module implementation, starting at 0. - 8 - 4 - read-only - - - MAJOR_REV - Major revision of module implementation, starting at 0. - 12 - 4 - read-only - - - ID - Unique module identifier for this IP block. - 16 - 16 - read-only - - - - - - - I2S1 - I2S interface - FLEXCOMM1 - I2S - 0x40087000 - - 0 - 0x1000 - registers - - - FLEXCOMM1 - 15 - - - - I2S2 - I2S interface - FLEXCOMM2 - I2S - 0x40088000 - - 0 - 0x1000 - registers - - - FLEXCOMM2 - 16 - - - - I2S3 - I2S interface - FLEXCOMM3 - I2S - 0x40089000 - - 0 - 0x1000 - registers - - - FLEXCOMM3 - 17 - - - - I2S4 - I2S interface - FLEXCOMM4 - I2S - 0x4008A000 - - 0 - 0x1000 - registers - - - FLEXCOMM4 - 18 - - - - I2S5 - I2S interface - FLEXCOMM5 - I2S - 0x40096000 - - 0 - 0x1000 - registers - - - FLEXCOMM5 - 19 - - - - I2S6 - I2S interface - FLEXCOMM6 - I2S - 0x40097000 - - 0 - 0x1000 - registers - - - FLEXCOMM6 - 20 - - - - I2S7 - I2S interface - FLEXCOMM7 - I2S - 0x40098000 - - 0 - 0x1000 - registers - - - FLEXCOMM7 - 21 - - - - SPI0 - Serial Peripheral Interfaces (SPI) - FLEXCOMM0 - SPI - SPI - 0x40086000 - - 0 - 0x1000 - registers - - - FLEXCOMM0 - 14 - - - - CFG - SPI Configuration register - 0x400 - 32 - read-write - 0 - 0xFBD - - - ENABLE - SPI enable. - 0 - 1 - read-write - - - DISABLED - Disabled. The SPI is disabled and the internal state machine and counters are reset. - 0 - - - ENABLED - Enabled. The SPI is enabled for operation. - 0x1 - - - - - MASTER - Master mode select. - 2 - 1 - read-write - - - SLAVE_MODE - Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. - 0 - - - MASTER_MODE - Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. - 0x1 - - - - - LSBF - LSB First mode enable. - 3 - 1 - read-write - - - STANDARD - Standard. Data is transmitted and received in standard MSB first order. - 0 - - - REVERSE - Reverse. Data is transmitted and received in reverse order (LSB first). - 0x1 - - - - - CPHA - Clock Phase select. - 4 - 1 - read-write - - - CHANGE - Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge. - 0 - - - CAPTURE - Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge. - 0x1 - - - - - CPOL - Clock Polarity select. - 5 - 1 - read-write - - - LOW - Low. The rest state of the clock (between transfers) is low. - 0 - - - HIGH - High. The rest state of the clock (between transfers) is high. - 0x1 - - - - - LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. - 7 - 1 - read-write - - - DISABLED - Disabled. - 0 - - - ENABLED - Enabled. - 0x1 - - - - - SPOL0 - SSEL0 Polarity select. - 8 - 1 - read-write - - - LOW - Low. The SSEL0 pin is active low. - 0 - - - HIGH - High. The SSEL0 pin is active high. - 0x1 - - - - - SPOL1 - SSEL1 Polarity select. - 9 - 1 - read-write - - - LOW - Low. The SSEL1 pin is active low. - 0 - - - HIGH - High. The SSEL1 pin is active high. - 0x1 - - - - - SPOL2 - SSEL2 Polarity select. - 10 - 1 - read-write - - - LOW - Low. The SSEL2 pin is active low. - 0 - - - HIGH - High. The SSEL2 pin is active high. - 0x1 - - - - - SPOL3 - SSEL3 Polarity select. - 11 - 1 - read-write - - - LOW - Low. The SSEL3 pin is active low. - 0 - - - HIGH - High. The SSEL3 pin is active high. - 0x1 - - - - - - - DLY - SPI Delay register - 0x404 - 32 - read-write - 0 - 0xFFFF - - - PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. - 0 - 4 - read-write - - - POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. - 4 - 4 - read-write - - - FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. - 8 - 4 - read-write - - - TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times. - 12 - 4 - read-write - - - - - STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. - 0x408 - 32 - read-write - 0x100 - 0x1C0 - - - SSA - Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software. - 4 - 1 - write-only - - - SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software. - 5 - 1 - write-only - - - STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition. - 6 - 1 - read-only - - - ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. - 7 - 1 - read-write - - - MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data. - 8 - 1 - read-only - - - - - INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. - 0x40C - 32 - read-write - 0 - 0x130 - - - SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. - 4 - 1 - read-write - - - DISABLED - Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. - 0 - - - ENABLED - Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. - 0x1 - - - - - SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. - 5 - 1 - read-write - - - DISABLED - Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. - 0 - - - ENABLED - Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. - 0x1 - - - - - MSTIDLEEN - Master idle interrupt enable. - 8 - 1 - read-write - - - DISABLED - No interrupt will be generated when the SPI master function is idle. - 0 - - - ENABLED - An interrupt will be generated when the SPI master function is fully idle. - 0x1 - - - - - - - INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. - 0x410 - 32 - write-only - 0 - 0 - - - SSAEN - Writing 1 clears the corresponding bit in the INTENSET register. - 4 - 1 - write-only - - - SSDEN - Writing 1 clears the corresponding bit in the INTENSET register. - 5 - 1 - write-only - - - MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register. - 8 - 1 - write-only - - - - - DIV - SPI clock Divider - 0x424 - 32 - read-write - 0 - 0xFFFF - - - DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536. - 0 - 16 - read-write - - - - - INTSTAT - SPI Interrupt Status - 0x428 - 32 - read-only - 0 - 0x130 - - - SSA - Slave Select Assert. - 4 - 1 - read-only - - - SSD - Slave Select Deassert. - 5 - 1 - read-only - - - MSTIDLE - Master Idle status flag. - 8 - 1 - read-only - - - - - FIFOCFG - FIFO configuration and enable register. - 0xE00 - 32 - read-write - 0 - 0x7F033 - - - ENABLETX - Enable the transmit FIFO. - 0 - 1 - read-write - - - DISABLED - The transmit FIFO is not enabled. - 0 - - - ENABLED - The transmit FIFO is enabled. - 0x1 - - - - - ENABLERX - Enable the receive FIFO. - 1 - 1 - read-write - - - DISABLED - The receive FIFO is not enabled. - 0 - - - ENABLED - The receive FIFO is enabled. - 0x1 - - - - - SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - 4 - 2 - read-only - - - DMATX - DMA configuration for transmit. - 12 - 1 - read-write - - - DISABLED - DMA is not used for the transmit function. - 0 - - - ENABLED - Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - 0x1 - - - - - DMARX - DMA configuration for receive. - 13 - 1 - read-write - - - DISABLED - DMA is not used for the receive function. - 0 - - - ENABLED - Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - 0x1 - - - - - WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 14 - 1 - read-write - - - DISABLED - Only enabled interrupts will wake up the device form reduced power modes. - 0 - - - ENABLED - A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. - 0x1 - - - - - WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 15 - 1 - read-write - - - DISABLED - Only enabled interrupts will wake up the device form reduced power modes. - 0 - - - ENABLED - A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. - 0x1 - - - - - EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - 16 - 1 - read-write - - - EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - 17 - 1 - read-write - - - - - FIFOSTAT - FIFO status register. - 0xE04 - 32 - read-write - 0x30 - 0x1F1FFB - - - TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. - 0 - 1 - read-write - - - RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - 1 - 1 - read-write - - - PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. - 3 - 1 - read-only - - - TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - 4 - 1 - read-only - - - TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. - 5 - 1 - read-only - - - RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - 6 - 1 - read-only - - - RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. - 7 - 1 - read-only - - - TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. - 8 - 5 - read-only - - - RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. - 16 - 5 - read-only - - - - - FIFOTRIG - FIFO trigger settings for interrupt and DMA request. - 0xE08 - 32 - read-write - 0 - 0xF0F03 - - - TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - 0 - 1 - read-write - - - DISABLED - Transmit FIFO level does not generate a FIFO level trigger. - 0 - - - ENABLED - An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - 0x1 - - - - - RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - 1 - 1 - read-write - - - DISABLED - Receive FIFO level does not generate a FIFO level trigger. - 0 - - - ENABLED - An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - 0x1 - - - - - TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). - 8 - 4 - read-write - - - RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). - 16 - 4 - read-write - - - - - FIFOINTENSET - FIFO interrupt enable set (enable) and read register. - 0xE10 - 32 - read-write - 0 - 0xF - - - TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - 0 - 1 - read-write - - - DISABLED - No interrupt will be generated for a transmit error. - 0 - - - ENABLED - An interrupt will be generated when a transmit error occurs. - 0x1 - - - - - RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - 1 - 1 - read-write - - - DISABLED - No interrupt will be generated for a receive error. - 0 - - - ENABLED - An interrupt will be generated when a receive error occurs. - 0x1 - - - - - TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 2 - 1 - read-write - - - DISABLED - No interrupt will be generated based on the TX FIFO level. - 0 - - - ENABLED - If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. - 0x1 - - - - - RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 3 - 1 - read-write - - - DISABLED - No interrupt will be generated based on the RX FIFO level. - 0 - - - ENABLED - If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. - 0x1 - - - - - - - FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. - 0xE14 - 32 - read-write - 0 - 0xF - - - TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - 0 - 1 - read-write - - - RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - 1 - 1 - read-write - - - TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - 2 - 1 - read-write - - - RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - 3 - 1 - read-write - - - - - FIFOINTSTAT - FIFO interrupt status register. - 0xE18 - 32 - read-only - 0 - 0x1F - - - TXERR - TX FIFO error. - 0 - 1 - read-only - - - RXERR - RX FIFO error. - 1 - 1 - read-only - - - TXLVL - Transmit FIFO level interrupt. - 2 - 1 - read-only - - - RXLVL - Receive FIFO level interrupt. - 3 - 1 - read-only - - - PERINT - Peripheral interrupt. - 4 - 1 - read-only - - - - - FIFOWR - FIFO write data. - 0xE20 - 32 - write-only - 0 - 0 - - - TXDATA - Transmit data to the FIFO. - 0 - 16 - write-only - - - TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. - 16 - 1 - write-only - - - ASSERTED - SSEL0 asserted. - 0 - - - NOT_ASSERTED - SSEL0 not asserted. - 0x1 - - - - - TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. - 17 - 1 - write-only - - - ASSERTED - SSEL1 asserted. - 0 - - - NOT_ASSERTED - SSEL1 not asserted. - 0x1 - - - - - TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. - 18 - 1 - write-only - - - ASSERTED - SSEL2 asserted. - 0 - - - NOT_ASSERTED - SSEL2 not asserted. - 0x1 - - - - - TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. - 19 - 1 - write-only - - - ASSERTED - SSEL3 asserted. - 0 - - - NOT_ASSERTED - SSEL3 not asserted. - 0x1 - - - - - EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register. - 20 - 1 - write-only - - - NOT_DEASSERTED - SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. - 0 - - - DEASSERTED - SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. - 0x1 - - - - - EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. - 21 - 1 - write-only - - - NOT_EOF - Data not EOF. This piece of data transmitted is not treated as the end of a frame. - 0 - - - EOF - Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted. - 0x1 - - - - - RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA. - 22 - 1 - write-only - - - READ - Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received. - 0 - - - IGNORE - Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated. - 0x1 - - - - - LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length. - 24 - 4 - write-only - - - - - FIFORD - FIFO read data. - 0xE30 - 32 - read-only - 0 - 0xE1FF - - - RXDATA - Received data from the FIFO. - 0 - 16 - read-only - - - RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. - 16 - 1 - read-only - - - RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. - 17 - 1 - read-only - - - RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. - 18 - 1 - read-only - - - RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. - 19 - 1 - read-only - - - SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bits. - 20 - 1 - read-only - - - - - FIFORDNOPOP - FIFO data read with no FIFO pop. - 0xE40 - 32 - read-only - 0 - 0xE1FF - - - RXDATA - Received data from the FIFO. - 0 - 16 - read-only - - - RXSSEL0_N - Slave Select for receive. - 16 - 1 - read-only - - - RXSSEL1_N - Slave Select for receive. - 17 - 1 - read-only - - - RXSSEL2_N - Slave Select for receive. - 18 - 1 - read-only - - - RXSSEL3_N - Slave Select for receive. - 19 - 1 - read-only - - - SOT - Start of transfer flag. - 20 - 1 - read-only - - - - - FIFOSIZE - FIFO size register - 0xE48 - 32 - read-write - 0x8 - 0xFFFFFFFF - - - FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - 0 - 5 - read-only - - - - - ID - Peripheral identification register. - 0xFFC - 32 - read-only - 0xE0201200 - 0xFFFFFFFF - - - APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - 0 - 8 - read-only - - - MINOR_REV - Minor revision of module implementation. - 8 - 4 - read-only - - - MAJOR_REV - Major revision of module implementation. - 12 - 4 - read-only - - - ID - Module identifier for the selected function. - 16 - 16 - read-only - - - - - - - SPI1 - Serial Peripheral Interfaces (SPI) - FLEXCOMM1 - SPI - 0x40087000 - - 0 - 0x1000 - registers - - - FLEXCOMM1 - 15 - - - - SPI2 - Serial Peripheral Interfaces (SPI) - FLEXCOMM2 - SPI - 0x40088000 - - 0 - 0x1000 - registers - - - FLEXCOMM2 - 16 - - - - SPI3 - Serial Peripheral Interfaces (SPI) - FLEXCOMM3 - SPI - 0x40089000 - - 0 - 0x1000 - registers - - - FLEXCOMM3 - 17 - - - - SPI4 - Serial Peripheral Interfaces (SPI) - FLEXCOMM4 - SPI - 0x4008A000 - - 0 - 0x1000 - registers - - - FLEXCOMM4 - 18 - - - - SPI5 - Serial Peripheral Interfaces (SPI) - FLEXCOMM5 - SPI - 0x40096000 - - 0 - 0x1000 - registers - - - FLEXCOMM5 - 19 - - - - SPI6 - Serial Peripheral Interfaces (SPI) - FLEXCOMM6 - SPI - 0x40097000 - - 0 - 0x1000 - registers - - - FLEXCOMM6 - 20 - - - - SPI7 - Serial Peripheral Interfaces (SPI) - FLEXCOMM7 - SPI - 0x40098000 - - 0 - 0x1000 - registers - - - FLEXCOMM7 - 21 - - - - SPI8 - Serial Peripheral Interfaces (SPI) - FLEXCOMM8 - SPI - 0x4009F000 - - 0 - 0x1000 - registers - - - FLEXCOMM8 - 59 - - - - USART0 - USARTs - FLEXCOMM0 - USART - USART - 0x40086000 - - 0 - 0x1000 - registers - - - FLEXCOMM0 - 14 - - - - CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. - 0 - 32 - read-write - 0 - 0xFDDBFD - - - ENABLE - USART Enable. - 0 - 1 - read-write - - - DISABLED - Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available. - 0 - - - ENABLED - Enabled. The USART is enabled for operation. - 0x1 - - - - - DATALEN - Selects the data size for the USART. - 2 - 2 - read-write - - - BIT_7 - 7 bit Data length. - 0 - - - BIT_8 - 8 bit Data length. - 0x1 - - - BIT_9 - 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. - 0x2 - - - - - PARITYSEL - Selects what type of parity is used by the USART. - 4 - 2 - read-write - - - NO_PARITY - No parity. - 0 - - - EVEN_PARITY - Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. - 0x2 - - - ODD_PARITY - Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. - 0x3 - - - - - STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. - 6 - 1 - read-write - - - BIT_1 - 1 stop bit. - 0 - - - BITS_2 - 2 stop bits. This setting should only be used for asynchronous communication. - 0x1 - - - - - MODE32K - Selects standard or 32 kHz clocking mode. - 7 - 1 - read-write - - - DISABLED - Disabled. USART uses standard clocking. - 0 - - - ENABLED - Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. - 0x1 - - - - - LINMODE - LIN break mode enable. - 8 - 1 - read-write - - - DISABLED - Disabled. Break detect and generate is configured for normal operation. - 0 - - - ENABLED - Enabled. Break detect and generate is configured for LIN bus operation. - 0x1 - - - - - CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. - 9 - 1 - read-write - - - DISABLED - No flow control. The transmitter does not receive any automatic flow control signal. - 0 - - - ENABLED - Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. - 0x1 - - - - - SYNCEN - Selects synchronous or asynchronous operation. - 11 - 1 - read-write - - - ASYNCHRONOUS_MODE - Asynchronous mode. - 0 - - - SYNCHRONOUS_MODE - Synchronous mode. - 0x1 - - - - - CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. - 12 - 1 - read-write - - - FALLING_EDGE - Falling edge. Un_RXD is sampled on the falling edge of SCLK. - 0 - - - RISING_EDGE - Rising edge. Un_RXD is sampled on the rising edge of SCLK. - 0x1 - - - - - SYNCMST - Synchronous mode Master select. - 14 - 1 - read-write - - - SLAVE - Slave. When synchronous mode is enabled, the USART is a slave. - 0 - - - MASTER - Master. When synchronous mode is enabled, the USART is a master. - 0x1 - - - - - LOOP - Selects data loopback mode. - 15 - 1 - read-write - - - NORMAL - Normal operation. - 0 - - - LOOPBACK - Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. - 0x1 - - - - - OETA - Output Enable Turnaround time enable for RS-485 operation. - 18 - 1 - read-write - - - DISABLED - Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. - 0 - - - ENABLED - Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted. - 0x1 - - - - - AUTOADDR - Automatic Address matching enable. - 19 - 1 - read-write - - - DISABLED - Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). - 0 - - - ENABLED - Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match. - 0x1 - - - - - OESEL - Output Enable Select. - 20 - 1 - read-write - - - STANDARD - Standard. The RTS signal is used as the standard flow control function. - 0 - - - RS_485 - RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. - 0x1 - - - - - OEPOL - Output Enable Polarity. - 21 - 1 - read-write - - - LOW - Low. If selected by OESEL, the output enable is active low. - 0 - - - HIGH - High. If selected by OESEL, the output enable is active high. - 0x1 - - - - - RXPOL - Receive data polarity. - 22 - 1 - read-write - - - STANDARD - Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. - 0 - - - INVERTED - Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. - 0x1 - - - - - TXPOL - Transmit data polarity. - 23 - 1 - read-write - - - STANDARD - Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. - 0 - - - INVERTED - Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. - 0x1 - - - - - - - CTL - USART Control register. USART control settings that are more likely to change during operation. - 0x4 - 32 - read-write - 0 - 0x10346 - - - TXBRKEN - Break Enable. - 1 - 1 - read-write - - - NORMAL - Normal operation. - 0 - - - CONTINOUS - Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. - 0x1 - - - - - ADDRDET - Enable address detect mode. - 2 - 1 - read-write - - - DISABLED - Disabled. The USART presents all incoming data. - 0 - - - ENABLED - Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. - 0x1 - - - - - TXDIS - Transmit Disable. - 6 - 1 - read-write - - - ENABLED - Not disabled. USART transmitter is not disabled. - 0 - - - DISABLED - Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. - 0x1 - - - - - CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. - 8 - 1 - read-write - - - CLOCK_ON_CHARACTER - Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. - 0 - - - CONTINOUS_CLOCK - Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). - 0x1 - - - - - CLRCCONRX - Clear Continuous Clock. - 9 - 1 - read-write - - - NO_EFFECT - No effect. No effect on the CC bit. - 0 - - - AUTO_CLEAR - Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. - 0x1 - - - - - AUTOBAUD - Autobaud enable. - 16 - 1 - read-write - - - DISABLED - Disabled. USART is in normal operating mode. - 0 - - - ENABLED - Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. - 0x1 - - - - - - - STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. - 0x8 - 32 - read-write - 0xA - 0x45A - - - RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data. - 1 - 1 - read-only - - - TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data. - 3 - 1 - read-only - - - CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. - 4 - 1 - read-only - - - DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. - 5 - 1 - write-only - - - TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). - 6 - 1 - read-only - - - RXBRK - Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high. - 10 - 1 - read-only - - - DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software. - 11 - 1 - write-only - - - START - This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software. - 12 - 1 - write-only - - - FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. - 13 - 1 - write-only - - - PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. - 14 - 1 - write-only - - - RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception. - 15 - 1 - write-only - - - ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto baud time-out. - 16 - 1 - write-only - - - - - INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. - 0xC - 32 - read-write - 0 - 0x1F868 - - - TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). - 3 - 1 - read-write - - - DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input. - 5 - 1 - read-write - - - TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details. - 6 - 1 - read-write - - - DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted). - 11 - 1 - read-write - - - STARTEN - When 1, enables an interrupt when a received start bit has been detected. - 12 - 1 - read-write - - - FRAMERREN - When 1, enables an interrupt when a framing error has been detected. - 13 - 1 - read-write - - - PARITYERREN - When 1, enables an interrupt when a parity error has been detected. - 14 - 1 - read-write - - - RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. - 15 - 1 - read-write - - - ABERREN - When 1, enables an interrupt when an auto baud error occurs. - 16 - 1 - read-write - - - - - INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. - 0x10 - 32 - write-only - 0 - 0 - - - TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register. - 3 - 1 - write-only - - - DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register. - 5 - 1 - write-only - - - TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register. - 6 - 1 - write-only - - - DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register. - 11 - 1 - write-only - - - STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register. - 12 - 1 - write-only - - - FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - 13 - 1 - write-only - - - PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - 14 - 1 - write-only - - - RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register. - 15 - 1 - write-only - - - ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - 16 - 1 - write-only - - - - - BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. - 0x20 - 32 - read-write - 0 - 0xFFFF - - - BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. - 0 - 16 - read-write - - - - - INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. - 0x24 - 32 - read-only - 0 - 0x1F968 - - - TXIDLE - Transmitter Idle status. - 3 - 1 - read-only - - - DELTACTS - This bit is set when a change in the state of the CTS input is detected. - 5 - 1 - read-only - - - TXDISINT - Transmitter Disabled Interrupt flag. - 6 - 1 - read-only - - - DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. - 11 - 1 - read-only - - - START - This bit is set when a start is detected on the receiver input. - 12 - 1 - read-only - - - FRAMERRINT - Framing Error interrupt flag. - 13 - 1 - read-only - - - PARITYERRINT - Parity Error interrupt flag. - 14 - 1 - read-only - - - RXNOISEINT - Received Noise interrupt flag. - 15 - 1 - read-only - - - ABERRINT - Auto baud Error Interrupt flag. - 16 - 1 - read-only - - - - - OSR - Oversample selection register for asynchronous communication. - 0x28 - 32 - read-write - 0xF - 0xF - - - OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. - 0 - 4 - read-write - - - - - ADDR - Address register for automatic address matching. - 0x2C - 32 - read-write - 0 - 0xFF - - - ADDRESS - 8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). - 0 - 8 - read-write - - - - - FIFOCFG - FIFO configuration and enable register. - 0xE00 - 32 - read-write - 0 - 0x7F033 - - - ENABLETX - Enable the transmit FIFO. - 0 - 1 - read-write - - - DISABLED - The transmit FIFO is not enabled. - 0 - - - ENABLED - The transmit FIFO is enabled. - 0x1 - - - - - ENABLERX - Enable the receive FIFO. - 1 - 1 - read-write - - - DISABLED - The receive FIFO is not enabled. - 0 - - - ENABLED - The receive FIFO is enabled. - 0x1 - - - - - SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - 4 - 2 - read-only - - - DMATX - DMA configuration for transmit. - 12 - 1 - read-write - - - DISABLED - DMA is not used for the transmit function. - 0 - - - ENABLED - Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - 0x1 - - - - - DMARX - DMA configuration for receive. - 13 - 1 - read-write - - - DISABLED - DMA is not used for the receive function. - 0 - - - ENABLED - Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - 0x1 - - - - - WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 14 - 1 - read-write - - - DISABLED - Only enabled interrupts will wake up the device form reduced power modes. - 0 - - - ENABLED - A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. - 0x1 - - - - - WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 15 - 1 - read-write - - - DISABLED - Only enabled interrupts will wake up the device form reduced power modes. - 0 - - - ENABLED - A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. - 0x1 - - - - - EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - 16 - 1 - read-write - - - EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - 17 - 1 - read-write - - - - - FIFOSTAT - FIFO status register. - 0xE04 - 32 - read-write - 0x30 - 0x1F1FFB - - - TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. - 0 - 1 - read-write - - - RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - 1 - 1 - read-write - - - PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. - 3 - 1 - read-only - - - TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - 4 - 1 - read-only - - - TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. - 5 - 1 - read-only - - - RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - 6 - 1 - read-only - - - RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. - 7 - 1 - read-only - - - TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. - 8 - 5 - read-only - - - RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. - 16 - 5 - read-only - - - - - FIFOTRIG - FIFO trigger settings for interrupt and DMA request. - 0xE08 - 32 - read-write - 0 - 0xF0F03 - - - TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - 0 - 1 - read-write - - - DISABLED - Transmit FIFO level does not generate a FIFO level trigger. - 0 - - - ENABLED - An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - 0x1 - - - - - RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - 1 - 1 - read-write - - - DISABLED - Receive FIFO level does not generate a FIFO level trigger. - 0 - - - ENABLED - An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - 0x1 - - - - - TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). - 8 - 4 - read-write - - - RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). - 16 - 4 - read-write - - - - - FIFOINTENSET - FIFO interrupt enable set (enable) and read register. - 0xE10 - 32 - read-write - 0 - 0xF - - - TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - 0 - 1 - read-write - - - DISABLED - No interrupt will be generated for a transmit error. - 0 - - - ENABLED - An interrupt will be generated when a transmit error occurs. - 0x1 - - - - - RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - 1 - 1 - read-write - - - DISABLED - No interrupt will be generated for a receive error. - 0 - - - ENABLED - An interrupt will be generated when a receive error occurs. - 0x1 - - - - - TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 2 - 1 - read-write - - - DISABLED - No interrupt will be generated based on the TX FIFO level. - 0 - - - ENABLED - If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. - 0x1 - - - - - RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 3 - 1 - read-write - - - DISABLED - No interrupt will be generated based on the RX FIFO level. - 0 - - - ENABLED - If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. - 0x1 - - - - - - - FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. - 0xE14 - 32 - read-write - 0 - 0xF - - - TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - 0 - 1 - read-write - - - RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - 1 - 1 - read-write - - - TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - 2 - 1 - read-write - - - RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - 3 - 1 - read-write - - - - - FIFOINTSTAT - FIFO interrupt status register. - 0xE18 - 32 - read-only - 0 - 0x1F - - - TXERR - TX FIFO error. - 0 - 1 - read-only - - - RXERR - RX FIFO error. - 1 - 1 - read-only - - - TXLVL - Transmit FIFO level interrupt. - 2 - 1 - read-only - - - RXLVL - Receive FIFO level interrupt. - 3 - 1 - read-only - - - PERINT - Peripheral interrupt. - 4 - 1 - read-only - - - - - FIFOWR - FIFO write data. - 0xE20 - 32 - write-only - 0 - 0 - - - TXDATA - Transmit data to the FIFO. - 0 - 9 - write-only - - - - - FIFORD - FIFO read data. - 0xE30 - 32 - read-only - 0 - 0xE1FF - - - RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. - 0 - 9 - read-only - - - FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. - 13 - 1 - read-only - - - PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. - 14 - 1 - read-only - - - RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. - 15 - 1 - read-only - - - - - FIFORDNOPOP - FIFO data read with no FIFO pop. - 0xE40 - 32 - read-only - 0 - 0xE1FF - - - RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. - 0 - 9 - read-only - - - FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. - 13 - 1 - read-only - - - PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. - 14 - 1 - read-only - - - RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. - 15 - 1 - read-only - - - - - FIFOSIZE - FIFO size register - 0xE48 - 32 - read-write - 0x8 - 0xFFFFFFFF - - - FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - 0 - 5 - read-only - - - - - ID - Peripheral identification register. - 0xFFC - 32 - read-only - 0 - 0xFFFFFFFF - - - APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - 0 - 8 - read-only - - - MINOR_REV - Minor revision of module implementation. - 8 - 4 - read-only - - - MAJOR_REV - Major revision of module implementation. - 12 - 4 - read-only - - - ID - Module identifier for the selected function. - 16 - 16 - read-only - - - - - - - USART1 - USARTs - FLEXCOMM1 - USART - 0x40087000 - - 0 - 0x1000 - registers - - - FLEXCOMM1 - 15 - - - - USART2 - USARTs - FLEXCOMM2 - USART - 0x40088000 - - 0 - 0x1000 - registers - - - FLEXCOMM2 - 16 - - - - USART3 - USARTs - FLEXCOMM3 - USART - 0x40089000 - - 0 - 0x1000 - registers - - - FLEXCOMM3 - 17 - - - - USART4 - USARTs - FLEXCOMM4 - USART - 0x4008A000 - - 0 - 0x1000 - registers - - - FLEXCOMM4 - 18 - - - - USART5 - USARTs - FLEXCOMM5 - USART - 0x40096000 - - 0 - 0x1000 - registers - - - FLEXCOMM5 - 19 - - - - USART6 - USARTs - FLEXCOMM6 - USART - 0x40097000 - - 0 - 0x1000 - registers - - - FLEXCOMM6 - 20 - - - - USART7 - USARTs - FLEXCOMM7 - USART - 0x40098000 - - 0 - 0x1000 - registers - - - FLEXCOMM7 - 21 - - - - MAILBOX - Mailbox - MAILBOX - 0x4008B000 - - 0 - 0xFC - registers - - - MAILBOX - 31 - - - - 2 - 0x10 - MBOXIRQ[%s] - no description available - 0 - - IRQ - Interrupt request register for the Cortex-M0+ CPU. - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - INTREQ - If any bit is set, an interrupt request is sent to the Cortex-M0+ interrupt controller. - 0 - 32 - read-write - - - - - IRQSET - Set bits in IRQ0 - 0x4 - 32 - write-only - 0 - 0 - - - INTREQSET - Writing 1 sets the corresponding bit in the IRQ0 register. - 0 - 32 - write-only - - - - - IRQCLR - Clear bits in IRQ0 - 0x8 - 32 - write-only - 0 - 0 - - - INTREQCLR - Writing 1 clears the corresponding bit in the IRQ0 register. - 0 - 32 - write-only - - - - - - MUTEX - Mutual exclusion register[1] - 0xF8 - 32 - read-write - 0x1 - 0x1 - - - EX - Cleared when read, set when written. See usage description above. - 0 - 1 - read-write - - - - - - - GPIO - General Purpose I/O (GPIO) - GPIO - 0x4008C000 - - 0 - 0x2488 - registers - - - - 2 - 0x20 - B[%s] - no description available - 0 - - 32 - 0x1 - B_[%s] - Byte pin registers for all port GPIO pins - 0 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - - 2 - 0x80 - W[%s] - no description available - 0x1000 - - 32 - 0x4 - W_[%s] - Word pin registers for all port GPIO pins - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - - 2 - 0x4 - DIR[%s] - Direction registers for all port GPIO pins - 0x2000 - 32 - read-write - 0 - 0xFFFFFFFF - - - DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output. - 0 - 32 - read-write - - - - - 2 - 0x4 - MASK[%s] - Mask register for all port GPIO pins - 0x2080 - 32 - read-write - 0 - 0xFFFFFFFF - - - MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. - 0 - 32 - read-write - - - - - 2 - 0x4 - PIN[%s] - Port pin register for all port GPIO pins - 0x2100 - 32 - read-write - 0 - 0xFFFFFFFF - - - PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. - 0 - 32 - read-write - - - - - 2 - 0x4 - MPIN[%s] - Masked port register for all port GPIO pins - 0x2180 - 32 - read-write - 0 - 0xFFFFFFFF - - - MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. - 0 - 32 - read-write - - - - - 2 - 0x4 - SET[%s] - Write: Set register for port. Read: output bits for port - 0x2200 - 32 - read-write - 0 - 0xFFFFFFFF - - - SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. - 0 - 32 - read-write - - - - - 2 - 0x4 - CLR[%s] - Clear port for all port GPIO pins - 0x2280 - 32 - write-only - 0 - 0 - - - CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit. - 0 - 32 - write-only - - - - - 2 - 0x4 - NOT[%s] - Toggle port for all port GPIO pins - 0x2300 - 32 - write-only - 0 - 0 - - - NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit. - 0 - 32 - write-only - - - - - 2 - 0x4 - DIRSET[%s] - Set pin direction bits for port - 0x2380 - 32 - write-only - 0 - 0 - - - DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit. - 0 - 32 - write-only - - - - - 2 - 0x4 - DIRCLR[%s] - Clear pin direction bits for port - 0x2400 - 32 - write-only - 0 - 0 - - - DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit. - 0 - 32 - write-only - - - - - 2 - 0x4 - DIRNOT[%s] - Toggle pin direction bits for port - 0x2480 - 32 - write-only - 0 - 0 - - - DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit. - 0 - 32 - write-only - - - - - - - USBHSD - USB1 High-speed Device Controller - USBHSD - 0x40094000 - - 0 - 0x38 - registers - - - USB1 - 47 - - - USB1_NEEDCLK - 48 - - - - DEVCMDSTAT - USB Device Command/Status register - 0 - 32 - read-write - 0x800 - 0xF7DBFFFF - - - DEV_ADDR - USB device address. - 0 - 7 - read-write - - - DEV_EN - USB device enable. - 7 - 1 - read-write - - - SETUP - SETUP token received. - 8 - 1 - read-write - - - FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:. - 9 - 1 - read-write - - - LPM_SUP - LPM Supported:. - 11 - 1 - read-write - - - INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP:. - 12 - 1 - read-write - - - INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP:. - 13 - 1 - read-write - - - INTONNAK_CO - Interrupt on NAK for control OUT EP:. - 14 - 1 - read-write - - - INTONNAK_CI - Interrupt on NAK for control IN EP:. - 15 - 1 - read-write - - - DCON - Device status - connect. - 16 - 1 - read-write - - - DSUS - Device status - suspend. - 17 - 1 - read-write - - - LPM_SUS - Device status - LPM Suspend. - 19 - 1 - read-write - - - LPM_REWP - LPM Remote Wake-up Enabled by USB host. - 20 - 1 - read-only - - - Speed - This field indicates the speed at which the device operates: 00b: reserved 01b: full-speed 10b: high-speed 11b: super-speed (reserved for future use). - 22 - 2 - read-only - - - DCON_C - Device status - connect change. - 24 - 1 - read-write - - - DSUS_C - Device status - suspend change. - 25 - 1 - read-write - - - DRES_C - Device status - reset change. - 26 - 1 - read-write - - - VBUS_DEBOUNCED - This bit indicates if VBUS is detected or not. - 28 - 1 - read-only - - - PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification. - 29 - 3 - read-write - - - DISABLE - Test mode disabled. - 0 - - - TEST_J - Test_J. - 0x1 - - - TEST_K - Test_K. - 0x2 - - - TEST_SE0_NAK - Test_SE0_NAK. - 0x3 - - - TEST_PACKET - Test_Packet. - 0x4 - - - TEST_FORCE_ENABLE - Test_Force_Enable. - 0x5 - - - - - - - INFO - USB Info register - 0x4 - 32 - read-only - 0x2000000 - 0xFFFF7FFF - - - FRAME_NR - Frame number. - 0 - 11 - read-only - - - ERR_CODE - The error code which last occurred:. - 11 - 4 - read-only - - - MINREV - Minor revision. - 16 - 8 - read-only - - - MAJREV - Major revision. - 24 - 8 - read-only - - - - - EPLISTSTART - USB EP Command/Status List start address - 0x8 - 32 - read-write - 0 - 0xFFFFFF00 - - - EP_LIST_PRG - Programmable portion of the USB EP Command/Status List address. - 8 - 12 - read-write - - - EP_LIST_FIXED - Fixed portion of USB EP Command/Status List address. - 20 - 12 - read-only - - - - - DATABUFSTART - USB Data buffer start address - 0xC - 32 - read-write - 0x41000000 - 0xFFFFFFFF - - - DA_BUF - Start address of the memory page where all endpoint data buffers are located. - 0 - 32 - read-write - - - - - LPM - USB Link Power Management register - 0x10 - 32 - read-write - 0 - 0x1FF - - - HIRD_HW - Host Initiated Resume Duration - HW. - 0 - 4 - read-only - - - HIRD_SW - Host Initiated Resume Duration - SW. - 4 - 4 - read-write - - - DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. - 8 - 1 - read-write - - - - - EPSKIP - USB Endpoint skip - 0x14 - 32 - read-write - 0 - 0xFFF - - - SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. - 0 - 12 - read-write - - - - - EPINUSE - USB Endpoint Buffer in use - 0x18 - 32 - read-write - 0 - 0xFFC - - - BUF - Buffer in use: This register has one bit per physical endpoint. - 2 - 10 - read-write - - - - - EPBUFCFG - USB Endpoint Buffer Configuration register - 0x1C - 32 - read-write - 0 - 0xFFC - - - BUF_SB - Buffer usage: This register has one bit per physical endpoint. - 2 - 10 - read-write - - - - - INTSTAT - USB interrupt status register - 0x20 - 32 - read-write - 0 - 0xC0000FFF - - - EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. - 0 - 1 - read-write - - - EP0IN - Interrupt status register bit for the Control EP0 IN direction. - 1 - 1 - read-write - - - EP1OUT - Interrupt status register bit for the EP1 OUT direction. - 2 - 1 - read-write - - - EP1IN - Interrupt status register bit for the EP1 IN direction. - 3 - 1 - read-write - - - EP2OUT - Interrupt status register bit for the EP2 OUT direction. - 4 - 1 - read-write - - - EP2IN - Interrupt status register bit for the EP2 IN direction. - 5 - 1 - read-write - - - EP3OUT - Interrupt status register bit for the EP3 OUT direction. - 6 - 1 - read-write - - - EP3IN - Interrupt status register bit for the EP3 IN direction. - 7 - 1 - read-write - - - EP4OUT - Interrupt status register bit for the EP4 OUT direction. - 8 - 1 - read-write - - - EP4IN - Interrupt status register bit for the EP4 IN direction. - 9 - 1 - read-write - - - EP5OUT - Interrupt status register bit for the EP5 OUT direction. - 10 - 1 - read-write - - - EP5IN - Interrupt status register bit for the EP5 IN direction. - 11 - 1 - read-write - - - FRAME_INT - Frame interrupt. - 30 - 1 - read-write - - - DEV_INT - Device status interrupt. - 31 - 1 - read-write - - - - - INTEN - USB interrupt enable register - 0x24 - 32 - read-write - 0 - 0xC0000FFF - - - EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. - 0 - 12 - read-write - - - FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. - 30 - 1 - read-write - - - DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. - 31 - 1 - read-write - - - - - INTSETSTAT - USB set interrupt status register - 0x28 - 32 - read-write - 0 - 0xC0000FFF - - - EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. - 0 - 12 - read-write - - - FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. - 30 - 1 - read-write - - - DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. - 31 - 1 - read-write - - - - - EPTOGGLE - USB Endpoint toggle register - 0x34 - 32 - read-only - 0 - 0x3FFFFFFF - - - TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. - 0 - 30 - read-only - - - - - - - CRC_ENGINE - CRC engine - CRC - 0x40095000 - - 0 - 0xC - registers - - - - MODE - CRC mode register - 0 - 32 - read-write - 0 - 0x3F - - - CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial - 0 - 2 - read-write - - - BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) - 2 - 1 - read-write - - - CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA - 3 - 1 - read-write - - - BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM - 4 - 1 - read-write - - - CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM - 5 - 1 - read-write - - - - - SEED - CRC seed register - 0x4 - 32 - read-write - 0xFFFF - 0xFFFFFFFF - - - CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses. - 0 - 32 - read-write - - - - - SUM - CRC checksum register - SUM_WR_DATA - 0x8 - 32 - read-only - 0xFFFF - 0xFFFFFFFF - - - CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. - 0 - 32 - read-only - - - - - WR_DATA - CRC data register - SUM_WR_DATA - 0x8 - 32 - write-only - 0 - 0 - - - CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions. - 0 - 32 - write-only - - - - - - - SDIF - SDMMC - SDIF - 0x4009B000 - - 0 - 0x300 - registers - - - SDIO - 42 - - - - CTRL - Control register - 0 - 32 - read-write - 0 - 0x2070FD7 - - - CONTROLLER_RESET - Controller reset. - 0 - 1 - read-write - - - FIFO_RESET - Fifo reset. - 1 - 1 - read-write - - - DMA_RESET - DMA reset. - 2 - 1 - read-write - - - INT_ENABLE - Global interrupt enable/disable bit. - 4 - 1 - read-write - - - READ_WAIT - Read/wait. - 6 - 1 - read-write - - - SEND_IRQ_RESPONSE - Send irq response. - 7 - 1 - read-write - - - ABORT_READ_DATA - Abort read data. - 8 - 1 - read-write - - - SEND_CCSD - Send ccsd. - 9 - 1 - read-write - - - SEND_AUTO_STOP_CCSD - Send auto stop ccsd. - 10 - 1 - read-write - - - CEATA_DEVICE_INTERRUPT_STATUS - CEATA device interrupt status. - 11 - 1 - read-write - - - CARD_VOLTAGE_A0 - Controls the state of the SD_VOLT0 pin. - 16 - 1 - read-write - - - CARD_VOLTAGE_A1 - Controls the state of the SD_VOLT1 pin. - 17 - 1 - read-write - - - CARD_VOLTAGE_A2 - Controls the state of the SD_VOLT2 pin. - 18 - 1 - read-write - - - USE_INTERNAL_DMAC - SD/MMC DMA use. - 25 - 1 - read-write - - - - - PWREN - Power Enable register - 0x4 - 32 - read-write - 0 - 0x3 - - - POWER_ENABLE0 - Power on/off switch for card 0; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card 0. - 0 - 1 - read-write - - - POWER_ENABLE1 - Power on/off switch for card 1; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card 1. - 1 - 1 - read-write - - - - - CLKDIV - Clock Divider register - 0x8 - 32 - read-write - 0 - 0xFF - - - CLK_DIVIDER0 - Clock divider-0 value. - 0 - 8 - read-write - - - - - CLKENA - Clock Enable register - 0x10 - 32 - read-write - 0 - 0x30003 - - - CCLK0_ENABLE - Clock-enable control for SD card 0 clock. - 0 - 1 - read-write - - - CCLK1_ENABLE - Clock-enable control for SD card 1 clock. - 1 - 1 - read-write - - - CCLK0_LOW_POWER - Low-power control for SD card 0 clock. - 16 - 1 - read-write - - - CCLK1_LOW_POWER - Low-power control for SD card 1 clock. - 17 - 1 - read-write - - - - - TMOUT - Time-out register - 0x14 - 32 - read-write - 0xFFFFFF40 - 0xFFFFFFFF - - - RESPONSE_TIMEOUT - Response time-out value. - 0 - 8 - read-write - - - DATA_TIMEOUT - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. - 8 - 24 - read-write - - - - - CTYPE - Card Type register - 0x18 - 32 - read-write - 0 - 0x30003 - - - CARD0_WIDTH0 - Indicates if card 0 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD0_WIDTH1 is not enabled (bit 16 in this register is set to 0). - 0 - 1 - read-write - - - CARD1_WIDTH0 - Indicates if card 1 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD1_WIDTH1 is not enabled (bit 16 in this register is set to 0). - 1 - 1 - read-write - - - CARD0_WIDTH1 - Indicates if card 0 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. - 16 - 1 - read-write - - - CARD1_WIDTH1 - Indicates if card 1 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. - 17 - 1 - read-write - - - - - BLKSIZ - Block Size register - 0x1C - 32 - read-write - 0x200 - 0xFFFF - - - BLOCK_SIZE - Block size. - 0 - 16 - read-write - - - - - BYTCNT - Byte Count register - 0x20 - 32 - read-write - 0x200 - 0xFFFFFFFF - - - BYTE_COUNT - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. - 0 - 32 - read-write - - - - - INTMASK - Interrupt Mask register - 0x24 - 32 - read-write - 0 - 0x1FFFF - - - CDET - Card detect. - 0 - 1 - read-write - - - RE - Response error. - 1 - 1 - read-write - - - CDONE - Command done. - 2 - 1 - read-write - - - DTO - Data transfer over. - 3 - 1 - read-write - - - TXDR - Transmit FIFO data request. - 4 - 1 - read-write - - - RXDR - Receive FIFO data request. - 5 - 1 - read-write - - - RCRC - Response CRC error. - 6 - 1 - read-write - - - DCRC - Data CRC error. - 7 - 1 - read-write - - - RTO - Response time-out. - 8 - 1 - read-write - - - DRTO - Data read time-out. - 9 - 1 - read-write - - - HTO - Data starvation-by-host time-out (HTO). - 10 - 1 - read-write - - - FRUN - FIFO underrun/overrun error. - 11 - 1 - read-write - - - HLE - Hardware locked write error. - 12 - 1 - read-write - - - SBE - Start-bit error. - 13 - 1 - read-write - - - ACD - Auto command done. - 14 - 1 - read-write - - - EBE - End-bit error (read)/Write no CRC. - 15 - 1 - read-write - - - SDIO_INT_MASK - Mask SDIO interrupt. - 16 - 1 - read-write - - - - - CMDARG - Command Argument register - 0x28 - 32 - read-write - 0 - 0xFFFFFFFF - - - CMD_ARG - Value indicates command argument to be passed to card. - 0 - 32 - read-write - - - - - CMD - Command register - 0x2C - 32 - read-write - 0 - 0xBFFFFFFF - - - CMD_INDEX - Command index. - 0 - 6 - read-write - - - RESPONSE_EXPECT - Response expect. - 6 - 1 - read-write - - - RESPONSE_LENGTH - Response length. - 7 - 1 - read-write - - - CHECK_RESPONSE_CRC - Check response CRC. - 8 - 1 - read-write - - - DATA_EXPECTED - Data expected. - 9 - 1 - read-write - - - READ_WRITE - read/write. - 10 - 1 - read-write - - - TRANSFER_MODE - Transfer mode. - 11 - 1 - read-write - - - SEND_AUTO_STOP - Send auto stop. - 12 - 1 - read-write - - - WAIT_PRVDATA_COMPLETE - Wait prvdata complete. - 13 - 1 - read-write - - - STOP_ABORT_CMD - Stop abort command. - 14 - 1 - read-write - - - SEND_INITIALIZATION - Send initialization. - 15 - 1 - read-write - - - CARD_NUMBER - Specifies the card number of SDCARD for which the current Command is being executed - 16 - 5 - read-write - - - CARD0 - Command will be execute on SDCARD 0 - 0 - - - CARD1 - Command will be execute on SDCARD 1 - 0x1 - - - - - UPDATE_CLOCK_REGISTERS_ONLY - Update clock registers only. - 21 - 1 - read-write - - - READ_CEATA_DEVICE - Read ceata device. - 22 - 1 - read-write - - - CCS_EXPECTED - CCS expected. - 23 - 1 - read-write - - - ENABLE_BOOT - Enable Boot - this bit should be set only for mandatory boot mode. - 24 - 1 - read-write - - - EXPECT_BOOT_ACK - Expect Boot Acknowledge. - 25 - 1 - read-write - - - DISABLE_BOOT - Disable Boot. - 26 - 1 - read-write - - - BOOT_MODE - Boot Mode. - 27 - 1 - read-write - - - VOLT_SWITCH - Voltage switch bit. - 28 - 1 - read-write - - - USE_HOLD_REG - Use Hold Register. - 29 - 1 - read-write - - - START_CMD - Start command. - 31 - 1 - read-write - - - - - 4 - 0x4 - RESP[%s] - Response register - 0x30 - 32 - read-write - 0 - 0xFFFFFFFF - - - RESPONSE - Bits of response. - 0 - 32 - read-write - - - - - MINTSTS - Masked Interrupt Status register - 0x40 - 32 - read-write - 0 - 0x1FFFF - - - CDET - Card detect. - 0 - 1 - read-write - - - RE - Response error. - 1 - 1 - read-write - - - CDONE - Command done. - 2 - 1 - read-write - - - DTO - Data transfer over. - 3 - 1 - read-write - - - TXDR - Transmit FIFO data request. - 4 - 1 - read-write - - - RXDR - Receive FIFO data request. - 5 - 1 - read-write - - - RCRC - Response CRC error. - 6 - 1 - read-write - - - DCRC - Data CRC error. - 7 - 1 - read-write - - - RTO - Response time-out. - 8 - 1 - read-write - - - DRTO - Data read time-out. - 9 - 1 - read-write - - - HTO - Data starvation-by-host time-out (HTO). - 10 - 1 - read-write - - - FRUN - FIFO underrun/overrun error. - 11 - 1 - read-write - - - HLE - Hardware locked write error. - 12 - 1 - read-write - - - SBE - Start-bit error. - 13 - 1 - read-write - - - ACD - Auto command done. - 14 - 1 - read-write - - - EBE - End-bit error (read)/write no CRC. - 15 - 1 - read-write - - - SDIO_INTERRUPT - Interrupt from SDIO card. - 16 - 1 - read-write - - - - - RINTSTS - Raw Interrupt Status register - 0x44 - 32 - read-write - 0 - 0x1FFFF - - - CDET - Card detect. - 0 - 1 - read-write - - - RE - Response error. - 1 - 1 - read-write - - - CDONE - Command done. - 2 - 1 - read-write - - - DTO - Data transfer over. - 3 - 1 - read-write - - - TXDR - Transmit FIFO data request. - 4 - 1 - read-write - - - RXDR - Receive FIFO data request. - 5 - 1 - read-write - - - RCRC - Response CRC error. - 6 - 1 - read-write - - - DCRC - Data CRC error. - 7 - 1 - read-write - - - RTO_BAR - Response time-out (RTO)/Boot Ack Received (BAR). - 8 - 1 - read-write - - - DRTO_BDS - Data read time-out (DRTO)/Boot Data Start (BDS). - 9 - 1 - read-write - - - HTO - Data starvation-by-host time-out (HTO). - 10 - 1 - read-write - - - FRUN - FIFO underrun/overrun error. - 11 - 1 - read-write - - - HLE - Hardware locked write error. - 12 - 1 - read-write - - - SBE - Start-bit error. - 13 - 1 - read-write - - - ACD - Auto command done. - 14 - 1 - read-write - - - EBE - End-bit error (read)/write no CRC. - 15 - 1 - read-write - - - SDIO_INTERRUPT - Interrupt from SDIO card. - 16 - 1 - read-write - - - - - STATUS - Status register - 0x48 - 32 - read-write - 0x406 - 0xFFFFFFFF - - - FIFO_RX_WATERMARK - FIFO reached Receive watermark level; not qualified with data transfer. - 0 - 1 - read-write - - - FIFO_TX_WATERMARK - FIFO reached Transmit watermark level; not qualified with data transfer. - 1 - 1 - read-write - - - FIFO_EMPTY - FIFO is empty status. - 2 - 1 - read-write - - - FIFO_FULL - FIFO is full status. - 3 - 1 - read-write - - - CMDFSMSTATES - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The command FSM state is represented using 19 bits. - 4 - 4 - read-write - - - DATA_3_STATUS - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present. - 8 - 1 - read-write - - - DATA_BUSY - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy. - 9 - 1 - read-write - - - DATA_STATE_MC_BUSY - Data transmit or receive state-machine is busy. - 10 - 1 - read-write - - - RESPONSE_INDEX - Index of previous response, including any auto-stop sent by core. - 11 - 6 - read-write - - - FIFO_COUNT - FIFO count - Number of filled locations in FIFO. - 17 - 13 - read-write - - - DMA_ACK - DMA acknowledge signal state. - 30 - 1 - read-write - - - DMA_REQ - DMA request signal state. - 31 - 1 - read-write - - - - - FIFOTH - FIFO Threshold Watermark register - 0x4C - 32 - read-write - 0x1F0000 - 0x7FFF0FFF - - - TX_WMARK - FIFO threshold watermark level when transmitting data to card. - 0 - 12 - read-write - - - RX_WMARK - FIFO threshold watermark level when receiving data to card. - 16 - 12 - read-write - - - DMA_MTS - Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE. - 28 - 3 - read-write - - - - - CDETECT - Card Detect register - 0x50 - 32 - read-write - 0 - 0x1 - - - CARD0_DETECT - Card 0 detect - 0 - 1 - read-write - - - CARD1_DETECT - Card 1 detect - 1 - 1 - read-write - - - - - WRTPRT - Write Protect register - 0x54 - 32 - read-write - 0 - 0x1 - - - WRITE_PROTECT - Write protect. - 0 - 1 - read-write - - - - - TCBCNT - Transferred CIU Card Byte Count register - 0x5C - 32 - read-write - 0 - 0xFFFFFFFF - - - TRANS_CARD_BYTE_COUNT - Number of bytes transferred by CIU unit to card. - 0 - 32 - read-write - - - - - TBBCNT - Transferred Host to BIU-FIFO Byte Count register - 0x60 - 32 - read-write - 0 - 0xFFFFFFFF - - - TRANS_FIFO_BYTE_COUNT - Number of bytes transferred between Host/DMA memory and BIU FIFO. - 0 - 32 - read-write - - - - - DEBNCE - Debounce Count register - 0x64 - 32 - read-write - 0xFFFFFF - 0xFFFFFF - - - DEBOUNCE_COUNT - Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms. - 0 - 24 - read-write - - - - - RST_N - Hardware Reset - 0x78 - 32 - read-write - 0x1 - 0x1 - - - CARD_RESET - Hardware reset. - 0 - 1 - read-write - - - - - BMOD - Bus Mode register - 0x80 - 32 - read-write - 0 - 0x7FF - - - SWR - Software Reset. - 0 - 1 - read-write - - - FB - Fixed Burst. - 1 - 1 - read-write - - - DSL - Descriptor Skip Length. - 2 - 5 - read-write - - - DE - SD/MMC DMA Enable. - 7 - 1 - read-write - - - PBL - Programmable Burst Length. - 8 - 3 - read-write - - - - - PLDMND - Poll Demand register - 0x84 - 32 - read-write - 0 - 0xFFFFFFFF - - - PD - Poll Demand. - 0 - 32 - read-write - - - - - DBADDR - Descriptor List Base Address register - 0x88 - 32 - read-write - 0 - 0xFFFFFFFF - - - SDL - Start of Descriptor List. - 0 - 32 - read-write - - - - - IDSTS - Internal DMAC Status register - 0x8C - 32 - read-write - 0 - 0x1FF37 - - - TI - Transmit Interrupt. - 0 - 1 - read-write - - - RI - Receive Interrupt. - 1 - 1 - read-write - - - FBE - Fatal Bus Error Interrupt. - 2 - 1 - read-write - - - DU - Descriptor Unavailable Interrupt. - 4 - 1 - read-write - - - CES - Card Error Summary. - 5 - 1 - read-write - - - NIS - Normal Interrupt Summary. - 8 - 1 - read-write - - - AIS - Abnormal Interrupt Summary. - 9 - 1 - read-write - - - EB - Error Bits. - 10 - 3 - read-write - - - FSM - DMAC state machine present state. - 13 - 4 - read-write - - - - - IDINTEN - Internal DMAC Interrupt Enable register - 0x90 - 32 - read-write - 0 - 0x337 - - - TI - Transmit Interrupt Enable. - 0 - 1 - read-write - - - RI - Receive Interrupt Enable. - 1 - 1 - read-write - - - FBE - Fatal Bus Error Enable. - 2 - 1 - read-write - - - DU - Descriptor Unavailable Interrupt. - 4 - 1 - read-write - - - CES - Card Error summary Interrupt Enable. - 5 - 1 - read-write - - - NIS - Normal Interrupt Summary Enable. - 8 - 1 - read-write - - - AIS - Abnormal Interrupt Summary Enable. - 9 - 1 - read-write - - - - - DSCADDR - Current Host Descriptor Address register - 0x94 - 32 - read-write - 0 - 0xFFFFFFFF - - - HDA - Host Descriptor Address Pointer. - 0 - 32 - read-write - - - - - BUFADDR - Current Buffer Descriptor Address register - 0x98 - 32 - read-write - 0 - 0xFFFFFFFF - - - HBA - Host Buffer Address Pointer. - 0 - 32 - read-write - - - - - CARDTHRCTL - Card Threshold Control - 0x100 - 32 - read-write - 0 - 0xFF0003 - - - CARDRDTHREN - Card Read Threshold Enable. - 0 - 1 - read-write - - - BSYCLRINTEN - Busy Clear Interrupt Enable. - 1 - 1 - read-write - - - CARDTHRESHOLD - Card Threshold size. - 16 - 8 - read-write - - - - - BACKENDPWR - Power control - 0x104 - 32 - read-write - 0 - 0x1 - - - BACKENDPWR - Back-end Power control for card application. - 0 - 1 - read-write - - - - - 64 - 0x4 - FIFO[%s] - SDIF FIFO - 0x200 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - SDIF FIFO. - 0 - 32 - read-write - - - - - - - DBGMAILBOX - MCU Debugger Mailbox - DBGMAILBOX - 0x4009C000 - - 0 - 0x100 - registers - - - - CSW - CRC mode register - 0 - 32 - read-write - 0 - 0x3F - - - RESYNCH_REQ - Debugger will set this bit to 1 to request a resynchronrisation - 0 - 1 - read-write - - - REQ_PENDING - Request is pending from debugger (i.e unread value in REQUEST) - 1 - 1 - read-write - - - DBG_OR_ERR - Debugger overrun error (previous REQUEST overwritten before being picked up by ROM) - 2 - 1 - read-write - - - AHB_OR_ERR - AHB overrun Error (Return value overwritten by ROM) - 3 - 1 - read-write - - - SOFT_RESET - Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to this bit will cause a soft reset for DM. - 4 - 1 - read-write - - - CHIP_RESET_REQ - Write only bit. Once written will cause the chip to reset (note that the DM is not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event) - 5 - 1 - write-only - - - - - REQUEST - CRC seed register - 0x4 - 32 - read-write - 0xFFFF - 0xFFFFFFFF - - - REQ - Request Value - 0 - 32 - read-write - - - - - RETURN - Return value from ROM. - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - RET - The Return value from ROM. - 0 - 32 - read-write - - - - - ID - Identification register - 0xFC - 32 - read-only - 0x2A0000 - 0xFFFFFFFF - - - ID - Identification value. - 0 - 32 - read-only - - - - - - - ADC0 - ADC - ADC - 0x400A0000 - - 0 - 0x1000 - registers - - - ADC0 - 22 - - - - VERID - Version ID Register - 0 - 32 - read-only - 0x1002C0B - 0xFFFFFFFF - - - RES - Resolution - 0 - 1 - read-only - - - RES_0 - Up to 13-bit differential/12-bit single ended resolution supported. - 0 - - - RES_1 - Up to 16-bit differential/16-bit single ended resolution supported. - 0x1 - - - - - DIFFEN - Differential Supported - 1 - 1 - read-only - - - DIFFEN_0 - Differential operation not supported. - 0 - - - DIFFEN_1 - Differential operation supported. CMDLa[CTYPE] controls fields implemented. - 0x1 - - - - - MVI - Multi Vref Implemented - 3 - 1 - read-only - - - MVI_0 - Single voltage reference high (VREFH) input supported. - 0 - - - MVI_1 - Multiple voltage reference high (VREFH) inputs supported. - 0x1 - - - - - CSW - Channel Scale Width - 4 - 3 - read-only - - - CSW_0 - Channel scaling not supported. - 0 - - - CSW_1 - Channel scaling supported. 1-bit CSCALE control field. - 0x1 - - - CSW_6 - Channel scaling supported. 6-bit CSCALE control field. - 0x6 - - - - - VR1RNGI - Voltage Reference 1 Range Control Bit Implemented - 8 - 1 - read-only - - - VR1RNGI_0 - Range control not required. CFG[VREF1RNG] is not implemented. - 0 - - - VR1RNGI_1 - Range control required. CFG[VREF1RNG] is implemented. - 0x1 - - - - - IADCKI - Internal ADC Clock implemented - 9 - 1 - read-only - - - IADCKI_0 - Internal clock source not implemented. - 0 - - - IADCKI_1 - Internal clock source (and CFG[ADCKEN]) implemented. - 0x1 - - - - - CALOFSI - Calibration Function Implemented - 10 - 1 - read-only - - - CALOFSI_0 - Calibration Not Implemented. - 0 - - - CALOFSI_1 - Calibration Implemented. - 0x1 - - - - - NUM_SEC - Number of Single Ended Outputs Supported - 11 - 1 - read-only - - - NUM_SEC_0 - This design supports one single ended conversion at a time. - 0 - - - NUM_SEC_1 - This design supports two simultanious single ended conversions. - 0x1 - - - - - NUM_FIFO - Number of FIFOs - 12 - 3 - read-only - - - NUM_FIFO_0 - N/A - 0 - - - NUM_FIFO_1 - This design supports one result FIFO. - 0x1 - - - NUM_FIFO_2 - This design supports two result FIFOs. - 0x2 - - - NUM_FIFO_3 - This design supports three result FIFOs. - 0x3 - - - NUM_FIFO_4 - This design supports four result FIFOs. - 0x4 - - - - - MINOR - Minor Version Number - 16 - 8 - read-only - - - MAJOR - Major Version Number - 24 - 8 - read-only - - - - - PARAM - Parameter Register - 0x4 - 32 - read-only - 0xF041010 - 0xFFFFFFFF - - - TRIG_NUM - Trigger Number - 0 - 8 - read-only - - - FIFOSIZE - Result FIFO Depth - 8 - 8 - read-only - - - FIFOSIZE_1 - Result FIFO depth = 1 dataword. - 0x1 - - - FIFOSIZE_4 - Result FIFO depth = 4 datawords. - 0x4 - - - FIFOSIZE_8 - Result FIFO depth = 8 datawords. - 0x8 - - - FIFOSIZE_16 - Result FIFO depth = 16 datawords. - 0x10 - - - FIFOSIZE_32 - Result FIFO depth = 32 datawords. - 0x20 - - - FIFOSIZE_64 - Result FIFO depth = 64 datawords. - 0x40 - - - - - CV_NUM - Compare Value Number - 16 - 8 - read-only - - - CMD_NUM - Command Buffer Number - 24 - 8 - read-only - - - - - CTRL - ADC Control Register - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCEN - ADC Enable - 0 - 1 - read-write - - - ADCEN_0 - ADC is disabled. - 0 - - - ADCEN_1 - ADC is enabled. - 0x1 - - - - - RST - Software Reset - 1 - 1 - read-write - - - RST_0 - ADC logic is not reset. - 0 - - - RST_1 - ADC logic is reset. - 0x1 - - - - - DOZEN - Doze Enable - 2 - 1 - read-write - - - DOZEN_0 - ADC is enabled in Doze mode. - 0 - - - DOZEN_1 - ADC is disabled in Doze mode. - 0x1 - - - - - CAL_REQ - Auto-Calibration Request - 3 - 1 - read-write - - - CAL_REQ_0 - No request for auto-calibration has been made. - 0 - - - CAL_REQ_1 - A request for auto-calibration has been made - 0x1 - - - - - CALOFS - Configure for offset calibration function - 4 - 1 - read-write - - - CALOFS_0 - Calibration function disabled - 0 - - - CALOFS_1 - Request for offset calibration function - 0x1 - - - - - RSTFIFO0 - Reset FIFO 0 - 8 - 1 - read-write - - - RSTFIFO0_0 - No effect. - 0 - - - RSTFIFO0_1 - FIFO 0 is reset. - 0x1 - - - - - RSTFIFO1 - Reset FIFO 1 - 9 - 1 - read-write - - - RSTFIFO1_0 - No effect. - 0 - - - RSTFIFO1_1 - FIFO 1 is reset. - 0x1 - - - - - CAL_AVGS - Auto-Calibration Averages - 16 - 3 - read-write - - - CAL_AVGS_0 - Single conversion. - 0 - - - CAL_AVGS_1 - 2 conversions averaged. - 0x1 - - - CAL_AVGS_2 - 4 conversions averaged. - 0x2 - - - CAL_AVGS_3 - 8 conversions averaged. - 0x3 - - - CAL_AVGS_4 - 16 conversions averaged. - 0x4 - - - CAL_AVGS_5 - 32 conversions averaged. - 0x5 - - - CAL_AVGS_6 - 64 conversions averaged. - 0x6 - - - CAL_AVGS_7 - 128 conversions averaged. - 0x7 - - - - - - - STAT - ADC Status Register - 0x14 - 32 - read-write - 0 - 0xFFFFFFFF - - - RDY0 - Result FIFO 0 Ready Flag - 0 - 1 - read-only - - - RDY0_0 - Result FIFO 0 data level not above watermark level. - 0 - - - RDY0_1 - Result FIFO 0 holding data above watermark level. - 0x1 - - - - - FOF0 - Result FIFO 0 Overflow Flag - 1 - 1 - read-write - oneToClear - - - FOF0_0 - No result FIFO 0 overflow has occurred since the last time the flag was cleared. - 0 - - - FOF0_1 - At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. - 0x1 - - - - - RDY1 - Result FIFO1 Ready Flag - 2 - 1 - read-only - - - RDY1_0 - Result FIFO1 data level not above watermark level. - 0 - - - RDY1_1 - Result FIFO1 holding data above watermark level. - 0x1 - - - - - FOF1 - Result FIFO1 Overflow Flag - 3 - 1 - read-write - oneToClear - - - FOF1_0 - No result FIFO1 overflow has occurred since the last time the flag was cleared. - 0 - - - FOF1_1 - At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - 0x1 - - - - - TEXC_INT - Interrupt Flag For High Priority Trigger Exception - 8 - 1 - read-write - oneToClear - - - TEXC_INT_0 - No trigger exceptions have occurred. - 0 - - - TEXC_INT_1 - A trigger exception has occurred and is pending acknowledgement. - 0x1 - - - - - TCOMP_INT - Interrupt Flag For Trigger Completion - 9 - 1 - read-write - oneToClear - - - TCOMP_INT_0 - Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. - 0 - - - TCOMP_INT_1 - Trigger sequence has been completed and all data is stored in the associated FIFO. - 0x1 - - - - - CAL_RDY - Calibration Ready - 10 - 1 - read-only - - - CAL_RDY_0 - Calibration is incomplete or hasn't been ran. - 0 - - - CAL_RDY_1 - The ADC is calibrated. - 0x1 - - - - - ADC_ACTIVE - ADC Active - 11 - 1 - read-only - - - ADC_ACTIVE_0 - The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. - 0 - - - ADC_ACTIVE_1 - The ADC is processing a conversion, running through the power up delay, or servicing a trigger. - 0x1 - - - - - TRGACT - Trigger Active - 16 - 4 - read-only - - - TRGACT_0 - Command (sequence) associated with Trigger 0 currently being executed. - 0 - - - TRGACT_1 - Command (sequence) associated with Trigger 1 currently being executed. - 0x1 - - - TRGACT_2 - Command (sequence) associated with Trigger 2 currently being executed. - 0x2 - - - TRGACT_3 - Command (sequence) from the associated Trigger number is currently being executed. - 0x3 - - - TRGACT_4 - Command (sequence) from the associated Trigger number is currently being executed. - 0x4 - - - TRGACT_5 - Command (sequence) from the associated Trigger number is currently being executed. - 0x5 - - - TRGACT_6 - Command (sequence) from the associated Trigger number is currently being executed. - 0x6 - - - TRGACT_7 - Command (sequence) from the associated Trigger number is currently being executed. - 0x7 - - - TRGACT_8 - Command (sequence) from the associated Trigger number is currently being executed. - 0x8 - - - TRGACT_9 - Command (sequence) from the associated Trigger number is currently being executed. - 0x9 - - - - - CMDACT - Command Active - 24 - 4 - read-only - - - CMDACT_0 - No command is currently in progress. - 0 - - - CMDACT_1 - Command 1 currently being executed. - 0x1 - - - CMDACT_2 - Command 2 currently being executed. - 0x2 - - - CMDACT_3 - Associated command number is currently being executed. - 0x3 - - - CMDACT_4 - Associated command number is currently being executed. - 0x4 - - - CMDACT_5 - Associated command number is currently being executed. - 0x5 - - - CMDACT_6 - Associated command number is currently being executed. - 0x6 - - - CMDACT_7 - Associated command number is currently being executed. - 0x7 - - - CMDACT_8 - Associated command number is currently being executed. - 0x8 - - - CMDACT_9 - Associated command number is currently being executed. - 0x9 - - - - - - - IE - Interrupt Enable Register - 0x18 - 32 - read-write - 0 - 0xFFFFFFFF - - - FWMIE0 - FIFO 0 Watermark Interrupt Enable - 0 - 1 - read-write - - - FWMIE0_0 - FIFO 0 watermark interrupts are not enabled. - 0 - - - FWMIE0_1 - FIFO 0 watermark interrupts are enabled. - 0x1 - - - - - FOFIE0 - Result FIFO 0 Overflow Interrupt Enable - 1 - 1 - read-write - - - FOFIE0_0 - FIFO 0 overflow interrupts are not enabled. - 0 - - - FOFIE0_1 - FIFO 0 overflow interrupts are enabled. - 0x1 - - - - - FWMIE1 - FIFO1 Watermark Interrupt Enable - 2 - 1 - read-write - - - FWMIE1_0 - FIFO1 watermark interrupts are not enabled. - 0 - - - FWMIE1_1 - FIFO1 watermark interrupts are enabled. - 0x1 - - - - - FOFIE1 - Result FIFO1 Overflow Interrupt Enable - 3 - 1 - read-write - - - FOFIE1_0 - No result FIFO1 overflow has occurred since the last time the flag was cleared. - 0 - - - FOFIE1_1 - At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - 0x1 - - - - - TEXC_IE - Trigger Exception Interrupt Enable - 8 - 1 - read-write - - - TEXC_IE_0 - Trigger exception interrupts are disabled. - 0 - - - TEXC_IE_1 - Trigger exception interrupts are enabled. - 0x1 - - - - - TCOMP_IE - Trigger Completion Interrupt Enable - 16 - 16 - read-write - - - TCOMP_IE_0 - Trigger completion interrupts are disabled. - 0 - - - TCOMP_IE_1 - Trigger completion interrupts are enabled for trigger source 0 only. - 0x1 - - - TCOMP_IE_2 - Trigger completion interrupts are enabled for trigger source 1 only. - 0x2 - - - TCOMP_IE_3 - Associated trigger completion interrupts are enabled. - 0x3 - - - TCOMP_IE_4 - Associated trigger completion interrupts are enabled. - 0x4 - - - TCOMP_IE_5 - Associated trigger completion interrupts are enabled. - 0x5 - - - TCOMP_IE_6 - Associated trigger completion interrupts are enabled. - 0x6 - - - TCOMP_IE_7 - Associated trigger completion interrupts are enabled. - 0x7 - - - TCOMP_IE_8 - Associated trigger completion interrupts are enabled. - 0x8 - - - TCOMP_IE_9 - Associated trigger completion interrupts are enabled. - 0x9 - - - TCOMP_IE_65535 - Trigger completion interrupts are enabled for every trigger source. - 0xFFFF - - - - - - - DE - DMA Enable Register - 0x1C - 32 - read-write - 0 - 0xFFFFFFFF - - - FWMDE0 - FIFO 0 Watermark DMA Enable - 0 - 1 - read-write - - - FWMDE0_0 - DMA request disabled. - 0 - - - FWMDE0_1 - DMA request enabled. - 0x1 - - - - - FWMDE1 - FIFO1 Watermark DMA Enable - 1 - 1 - read-write - - - FWMDE1_0 - DMA request disabled. - 0 - - - FWMDE1_1 - DMA request enabled. - 0x1 - - - - - - - CFG - ADC Configuration Register - 0x20 - 32 - read-write - 0x800000 - 0xFFFFFFFF - - - TPRICTRL - ADC trigger priority control - 0 - 2 - read-write - - - TPRICTRL_0 - If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started. - 0 - - - TPRICTRL_1 - If a higher priority trigger is received during command processing, the current command is stopped after after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. - 0x1 - - - TPRICTRL_2 - If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger. - 0x2 - - - - - PWRSEL - Power Configuration Select - 4 - 2 - read-write - - - PWRSEL_0 - Lowest power setting. - 0 - - - PWRSEL_1 - Higher power setting than 0b0. - 0x1 - - - PWRSEL_2 - Higher power setting than 0b1. - 0x2 - - - PWRSEL_3 - Highest power setting. - 0x3 - - - - - REFSEL - Voltage Reference Selection - 6 - 2 - read-write - - - REFSEL_0 - (Default) Option 1 setting. - 0 - - - REFSEL_1 - Option 2 setting. - 0x1 - - - REFSEL_2 - Option 3 setting. - 0x2 - - - - - TRES - Trigger Resume Enable - 8 - 1 - read-write - - - TRES_0 - Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. - 0 - - - TRES_1 - Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. - 0x1 - - - - - TCMDRES - Trigger Command Resume - 9 - 1 - read-write - - - TCMDRES_0 - Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. - 0 - - - TCMDRES_1 - Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. - 0x1 - - - - - HPT_EXDI - High Priority Trigger Exception Disable - 10 - 1 - read-write - - - HPT_EXDI_0 - High priority trigger exceptions are enabled. - 0 - - - HPT_EXDI_1 - High priority trigger exceptions are disabled. - 0x1 - - - - - PUDLY - Power Up Delay - 16 - 8 - read-write - - - PWREN - ADC Analog Pre-Enable - 28 - 1 - read-write - - - PWREN_0 - ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. - 0 - - - PWREN_1 - ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog will remain pre-enabled, and no additional delays will be executed. - 0x1 - - - - - - - PAUSE - ADC Pause Register - 0x24 - 32 - read-write - 0 - 0xFFFFFFFF - - - PAUSEDLY - Pause Delay - 0 - 9 - read-write - - - PAUSEEN - PAUSE Option Enable - 31 - 1 - read-write - - - PAUSEEN_0 - Pause operation disabled - 0 - - - PAUSEEN_1 - Pause operation enabled - 0x1 - - - - - - - SWTRIG - Software Trigger Register - 0x34 - 32 - read-write - 0 - 0xFFFFFFFF - - - SWT0 - Software trigger 0 event - 0 - 1 - read-write - - - SWT0_0 - No trigger 0 event generated. - 0 - - - SWT0_1 - Trigger 0 event generated. - 0x1 - - - - - SWT1 - Software trigger 1 event - 1 - 1 - read-write - - - SWT1_0 - No trigger 1 event generated. - 0 - - - SWT1_1 - Trigger 1 event generated. - 0x1 - - - - - SWT2 - Software trigger 2 event - 2 - 1 - read-write - - - SWT2_0 - No trigger 2 event generated. - 0 - - - SWT2_1 - Trigger 2 event generated. - 0x1 - - - - - SWT3 - Software trigger 3 event - 3 - 1 - read-write - - - SWT3_0 - No trigger 3 event generated. - 0 - - - SWT3_1 - Trigger 3 event generated. - 0x1 - - - - - SWT4 - Software trigger 4 event - 4 - 1 - read-write - - - SWT4_0 - No trigger 4 event generated. - 0 - - - SWT4_1 - Trigger 4 event generated. - 0x1 - - - - - SWT5 - Software trigger 5 event - 5 - 1 - read-write - - - SWT5_0 - No trigger 5 event generated. - 0 - - - SWT5_1 - Trigger 5 event generated. - 0x1 - - - - - SWT6 - Software trigger 6 event - 6 - 1 - read-write - - - SWT6_0 - No trigger 6 event generated. - 0 - - - SWT6_1 - Trigger 6 event generated. - 0x1 - - - - - SWT7 - Software trigger 7 event - 7 - 1 - read-write - - - SWT7_0 - No trigger 7 event generated. - 0 - - - SWT7_1 - Trigger 7 event generated. - 0x1 - - - - - SWT8 - Software trigger 8 event - 8 - 1 - read-write - - - SWT8_0 - No trigger 8 event generated. - 0 - - - SWT8_1 - Trigger 8 event generated. - 0x1 - - - - - SWT9 - Software trigger 9 event - 9 - 1 - read-write - - - SWT9_0 - No trigger 9 event generated. - 0 - - - SWT9_1 - Trigger 9 event generated. - 0x1 - - - - - SWT10 - Software trigger 10 event - 10 - 1 - read-write - - - SWT10_0 - No trigger 10 event generated. - 0 - - - SWT10_1 - Trigger 10 event generated. - 0x1 - - - - - SWT11 - Software trigger 11 event - 11 - 1 - read-write - - - SWT11_0 - No trigger 11 event generated. - 0 - - - SWT11_1 - Trigger 11 event generated. - 0x1 - - - - - SWT12 - Software trigger 12 event - 12 - 1 - read-write - - - SWT12_0 - No trigger 12 event generated. - 0 - - - SWT12_1 - Trigger 12 event generated. - 0x1 - - - - - SWT13 - Software trigger 13 event - 13 - 1 - read-write - - - SWT13_0 - No trigger 13 event generated. - 0 - - - SWT13_1 - Trigger 13 event generated. - 0x1 - - - - - SWT14 - Software trigger 14 event - 14 - 1 - read-write - - - SWT14_0 - No trigger 14 event generated. - 0 - - - SWT14_1 - Trigger 14 event generated. - 0x1 - - - - - SWT15 - Software trigger 15 event - 15 - 1 - read-write - - - SWT15_0 - No trigger 15 event generated. - 0 - - - SWT15_1 - Trigger 15 event generated. - 0x1 - - - - - - - TSTAT - Trigger Status Register - 0x38 - 32 - read-write - 0 - 0xFFFFFFFF - - - TEXC_NUM - Trigger Exception Number - 0 - 16 - read-write - oneToClear - - - TEXC_NUM_0 - No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. - 0 - - - TEXC_NUM_1 - Trigger 0 has been interrupted by a high priority exception. - 0x1 - - - TEXC_NUM_2 - Trigger 1 has been interrupted by a high priority exception. - 0x2 - - - TEXC_NUM_3 - Associated trigger sequence has interrupted by a high priority exception. - 0x3 - - - TEXC_NUM_4 - Associated trigger sequence has interrupted by a high priority exception. - 0x4 - - - TEXC_NUM_5 - Associated trigger sequence has interrupted by a high priority exception. - 0x5 - - - TEXC_NUM_6 - Associated trigger sequence has interrupted by a high priority exception. - 0x6 - - - TEXC_NUM_7 - Associated trigger sequence has interrupted by a high priority exception. - 0x7 - - - TEXC_NUM_8 - Associated trigger sequence has interrupted by a high priority exception. - 0x8 - - - TEXC_NUM_9 - Associated trigger sequence has interrupted by a high priority exception. - 0x9 - - - TEXC_NUM_65535 - Every trigger sequence has been interrupted by a high priority exception. - 0xFFFF - - - - - TCOMP_FLAG - Trigger Completion Flag - 16 - 16 - read-write - oneToClear - - - TCOMP_FLAG_0 - No triggers have been completed. Trigger completion interrupts are disabled. - 0 - - - TCOMP_FLAG_1 - Trigger 0 has been completed and triger 0 has enabled completion interrupts. - 0x1 - - - TCOMP_FLAG_2 - Trigger 1 has been completed and triger 1 has enabled completion interrupts. - 0x2 - - - TCOMP_FLAG_3 - Associated trigger sequence has completed and has enabled completion interrupts. - 0x3 - - - TCOMP_FLAG_4 - Associated trigger sequence has completed and has enabled completion interrupts. - 0x4 - - - TCOMP_FLAG_5 - Associated trigger sequence has completed and has enabled completion interrupts. - 0x5 - - - TCOMP_FLAG_6 - Associated trigger sequence has completed and has enabled completion interrupts. - 0x6 - - - TCOMP_FLAG_7 - Associated trigger sequence has completed and has enabled completion interrupts. - 0x7 - - - TCOMP_FLAG_8 - Associated trigger sequence has completed and has enabled completion interrupts. - 0x8 - - - TCOMP_FLAG_9 - Associated trigger sequence has completed and has enabled completion interrupts. - 0x9 - - - TCOMP_FLAG_65535 - Every trigger sequence has been completed and every trigger has enabled completion interrupts. - 0xFFFF - - - - - - - OFSTRIM - ADC Offset Trim Register - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - OFSTRIM_A - Trim for offset - 0 - 5 - read-write - - - OFSTRIM_B - Trim for offset - 16 - 5 - read-write - - - - - 16 - 0x4 - TCTRL[%s] - Trigger Control Register - 0xA0 - 32 - read-write - 0 - 0xFFFFFFFF - - - HTEN - Trigger enable - 0 - 1 - read-write - - - HTEN_0 - Hardware trigger source disabled - 0 - - - HTEN_1 - Hardware trigger source enabled - 0x1 - - - - - FIFO_SEL_A - SAR Result Destination For Channel A - 1 - 1 - read-write - - - FIFO_SEL_A_0 - Result written to FIFO 0 - 0 - - - FIFO_SEL_A_1 - Result written to FIFO 1 - 0x1 - - - - - FIFO_SEL_B - SAR Result Destination For Channel B - 2 - 1 - read-write - - - FIFO_SEL_B_0 - Result written to FIFO 0 - 0 - - - FIFO_SEL_B_1 - Result written to FIFO 1 - 0x1 - - - - - TPRI - Trigger priority setting - 8 - 4 - read-write - - - TPRI_0 - Set to highest priority, Level 1 - 0 - - - TPRI_1 - Set to corresponding priority level - 0x1 - - - TPRI_2 - Set to corresponding priority level - 0x2 - - - TPRI_3 - Set to corresponding priority level - 0x3 - - - TPRI_4 - Set to corresponding priority level - 0x4 - - - TPRI_5 - Set to corresponding priority level - 0x5 - - - TPRI_6 - Set to corresponding priority level - 0x6 - - - TPRI_7 - Set to corresponding priority level - 0x7 - - - TPRI_8 - Set to corresponding priority level - 0x8 - - - TPRI_9 - Set to corresponding priority level - 0x9 - - - TPRI_15 - Set to lowest priority, Level 16 - 0xF - - - - - RSYNC - Trigger Resync - 15 - 1 - read-write - - - TDLY - Trigger delay select - 16 - 4 - read-write - - - TCMD - Trigger command select - 24 - 4 - read-write - - - TCMD_0 - Not a valid selection from the command buffer. Trigger event is ignored. - 0 - - - TCMD_1 - CMD1 is executed - 0x1 - - - TCMD_2 - Corresponding CMD is executed - 0x2 - - - TCMD_3 - Corresponding CMD is executed - 0x3 - - - TCMD_4 - Corresponding CMD is executed - 0x4 - - - TCMD_5 - Corresponding CMD is executed - 0x5 - - - TCMD_6 - Corresponding CMD is executed - 0x6 - - - TCMD_7 - Corresponding CMD is executed - 0x7 - - - TCMD_8 - Corresponding CMD is executed - 0x8 - - - TCMD_9 - Corresponding CMD is executed - 0x9 - - - TCMD_15 - CMD15 is executed - 0xF - - - - - - - 2 - 0x4 - FCTRL[%s] - FIFO Control Register - 0xE0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FCOUNT - Result FIFO counter - 0 - 5 - read-only - - - FWMARK - Watermark level selection - 16 - 4 - read-write - - - - - 2 - 0x4 - GCC[%s] - Gain Calibration Control - 0xF0 - 32 - read-only - 0 - 0xFFFFFFFF - - - GAIN_CAL - Gain Calibration Value - 0 - 16 - read-only - - - RDY - Gain Calibration Value Valid - 24 - 1 - read-only - - - RDY_0 - The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. - 0 - - - RDY_1 - The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. - 0x1 - - - - - - - 2 - 0x4 - GCR[%s] - Gain Calculation Result - 0xF8 - 32 - read-write - 0 - 0xFFFFFFFF - - - GCALR - Gain Calculation Result - 0 - 16 - read-write - - - RDY - Gain Calculation Ready - 24 - 1 - read-write - - - RDY_0 - The gain offset calculation value is invalid. - 0 - - - RDY_1 - The gain calibration value is valid. - 0x1 - - - - - - - CMDL1 - ADC Command Low Buffer Register - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH1 - ADC Command High Buffer Register - 0x104 - 32 - read-write - 0 - 0xFFFFFFFF - - - CMPEN - Compare Function Enable - 0 - 2 - read-write - - - CMPEN_0 - Compare disabled. - 0 - - - CMPEN_2 - Compare enabled. Store on true. - 0x2 - - - CMPEN_3 - Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - 0x3 - - - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL2 - ADC Command Low Buffer Register - 0x108 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH2 - ADC Command High Buffer Register - 0x10C - 32 - read-write - 0 - 0xFFFFFFFF - - - CMPEN - Compare Function Enable - 0 - 2 - read-write - - - CMPEN_0 - Compare disabled. - 0 - - - CMPEN_2 - Compare enabled. Store on true. - 0x2 - - - CMPEN_3 - Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - 0x3 - - - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL3 - ADC Command Low Buffer Register - 0x110 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH3 - ADC Command High Buffer Register - 0x114 - 32 - read-write - 0 - 0xFFFFFFFF - - - CMPEN - Compare Function Enable - 0 - 2 - read-write - - - CMPEN_0 - Compare disabled. - 0 - - - CMPEN_2 - Compare enabled. Store on true. - 0x2 - - - CMPEN_3 - Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - 0x3 - - - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL4 - ADC Command Low Buffer Register - 0x118 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH4 - ADC Command High Buffer Register - 0x11C - 32 - read-write - 0 - 0xFFFFFFFF - - - CMPEN - Compare Function Enable - 0 - 2 - read-write - - - CMPEN_0 - Compare disabled. - 0 - - - CMPEN_2 - Compare enabled. Store on true. - 0x2 - - - CMPEN_3 - Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - 0x3 - - - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL5 - ADC Command Low Buffer Register - 0x120 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH5 - ADC Command High Buffer Register - 0x124 - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL6 - ADC Command Low Buffer Register - 0x128 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH6 - ADC Command High Buffer Register - 0x12C - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL7 - ADC Command Low Buffer Register - 0x130 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH7 - ADC Command High Buffer Register - 0x134 - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL8 - ADC Command Low Buffer Register - 0x138 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH8 - ADC Command High Buffer Register - 0x13C - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL9 - ADC Command Low Buffer Register - 0x140 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH9 - ADC Command High Buffer Register - 0x144 - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL10 - ADC Command Low Buffer Register - 0x148 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH10 - ADC Command High Buffer Register - 0x14C - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL11 - ADC Command Low Buffer Register - 0x150 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH11 - ADC Command High Buffer Register - 0x154 - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL12 - ADC Command Low Buffer Register - 0x158 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH12 - ADC Command High Buffer Register - 0x15C - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL13 - ADC Command Low Buffer Register - 0x160 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH13 - ADC Command High Buffer Register - 0x164 - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL14 - ADC Command Low Buffer Register - 0x168 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH14 - ADC Command High Buffer Register - 0x16C - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL15 - ADC Command Low Buffer Register - 0x170 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH15 - ADC Command High Buffer Register - 0x174 - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - 4 - 0x4 - 1,2,3,4 - CV%s - Compare Value Register - 0x200 - 32 - read-write - 0 - 0xFFFFFFFF - - - CVL - Compare Value Low. - 0 - 16 - read-write - - - CVH - Compare Value High. - 16 - 16 - read-write - - - - - 2 - 0x4 - RESFIFO[%s] - ADC Data Result FIFO Register - 0x300 - 32 - read-only - 0 - 0xFFFFFFFF - - - D - Data result - 0 - 16 - read-only - - - TSRC - Trigger Source - 16 - 4 - read-only - - - TSRC_0 - Trigger source 0 initiated this conversion. - 0 - - - TSRC_1 - Trigger source 1 initiated this conversion. - 0x1 - - - TSRC_2 - Corresponding trigger source initiated this conversion. - 0x2 - - - TSRC_3 - Corresponding trigger source initiated this conversion. - 0x3 - - - TSRC_4 - Corresponding trigger source initiated this conversion. - 0x4 - - - TSRC_5 - Corresponding trigger source initiated this conversion. - 0x5 - - - TSRC_6 - Corresponding trigger source initiated this conversion. - 0x6 - - - TSRC_7 - Corresponding trigger source initiated this conversion. - 0x7 - - - TSRC_8 - Corresponding trigger source initiated this conversion. - 0x8 - - - TSRC_9 - Corresponding trigger source initiated this conversion. - 0x9 - - - TSRC_15 - Trigger source 15 initiated this conversion. - 0xF - - - - - LOOPCNT - Loop count value - 20 - 4 - read-only - - - LOOPCNT_0 - Result is from initial conversion in command. - 0 - - - LOOPCNT_1 - Result is from second conversion in command. - 0x1 - - - LOOPCNT_2 - Result is from LOOPCNT+1 conversion in command. - 0x2 - - - LOOPCNT_3 - Result is from LOOPCNT+1 conversion in command. - 0x3 - - - LOOPCNT_4 - Result is from LOOPCNT+1 conversion in command. - 0x4 - - - LOOPCNT_5 - Result is from LOOPCNT+1 conversion in command. - 0x5 - - - LOOPCNT_6 - Result is from LOOPCNT+1 conversion in command. - 0x6 - - - LOOPCNT_7 - Result is from LOOPCNT+1 conversion in command. - 0x7 - - - LOOPCNT_8 - Result is from LOOPCNT+1 conversion in command. - 0x8 - - - LOOPCNT_9 - Result is from LOOPCNT+1 conversion in command. - 0x9 - - - LOOPCNT_15 - Result is from 16th conversion in command. - 0xF - - - - - CMDSRC - Command Buffer Source - 24 - 4 - read-only - - - CMDSRC_0 - Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer. - 0 - - - CMDSRC_1 - CMD1 buffer used as control settings for this conversion. - 0x1 - - - CMDSRC_2 - Corresponding command buffer used as control settings for this conversion. - 0x2 - - - CMDSRC_3 - Corresponding command buffer used as control settings for this conversion. - 0x3 - - - CMDSRC_4 - Corresponding command buffer used as control settings for this conversion. - 0x4 - - - CMDSRC_5 - Corresponding command buffer used as control settings for this conversion. - 0x5 - - - CMDSRC_6 - Corresponding command buffer used as control settings for this conversion. - 0x6 - - - CMDSRC_7 - Corresponding command buffer used as control settings for this conversion. - 0x7 - - - CMDSRC_8 - Corresponding command buffer used as control settings for this conversion. - 0x8 - - - CMDSRC_9 - Corresponding command buffer used as control settings for this conversion. - 0x9 - - - CMDSRC_15 - CMD15 buffer used as control settings for this conversion. - 0xF - - - - - VALID - FIFO entry is valid - 31 - 1 - read-only - - - VALID_0 - FIFO is empty. Discard any read from RESFIFO. - 0 - - - VALID_1 - FIFO record read from RESFIFO is valid. - 0x1 - - - - - - - 33 - 0x4 - CAL_GAR[%s] - Calibration General A-Side Registers - 0x400 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAL_GAR_VAL - Calibration General A Side Register Element - 0 - 16 - read-write - - - - - 33 - 0x4 - CAL_GBR[%s] - Calibration General B-Side Registers - 0x500 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAL_GBR_VAL - Calibration General B Side Register Element - 0 - 16 - read-write - - - - - TST - ADC Test Register - 0xFFC - 32 - read-write - 0 - 0xFFFFFFFF - - - CST_LONG - Calibration Sample Time Long - 0 - 1 - read-write - - - CST_LONG_0 - Normal sample time. Minimum sample time of 3 ADCK cycles. - 0 - - - CST_LONG_1 - Increased sample time. 67 ADCK cycles total sample time. - 0x1 - - - - - FOFFM - Force M-side positive offset - 8 - 1 - read-write - - - FOFFM_0 - Normal operation. No forced offset. - 0 - - - FOFFM_1 - Test configuration. Forced positive offset on MDAC. - 0x1 - - - - - FOFFP - Force P-side positive offset - 9 - 1 - read-write - - - FOFFP_0 - Normal operation. No forced offset. - 0 - - - FOFFP_1 - Test configuration. Forced positive offset on PDAC. - 0x1 - - - - - FOFFM2 - Force M-side negative offset - 10 - 1 - read-write - - - FOFFM2_0 - Normal operation. No forced offset. - 0 - - - FOFFM2_1 - Test configuration. Forced negative offset on MDAC. - 0x1 - - - - - FOFFP2 - Force P-side negative offset - 11 - 1 - read-write - - - FOFFP2_0 - Normal operation. No forced offset. - 0 - - - FOFFP2_1 - Test configuration. Forced negative offset on PDAC. - 0x1 - - - - - TESTEN - Enable test configuration - 23 - 1 - read-write - - - TESTEN_0 - Normal operation. Test configuration not enabled. - 0 - - - TESTEN_1 - Hardware BIST Test in progress. - 0x1 - - - - - - - - - USBFSH - USB0 Full-speed Host controller - USBFSH - 0x400A2000 - - 0 - 0x60 - registers - - - USB0_NEEDCLK - 27 - - - USB0 - 28 - - - - HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) - 0 - 32 - read-only - 0x10 - 0xFF - - - REV - Revision. - 0 - 8 - read-only - - - - - HCCONTROL - Defines the operating modes of the HC - 0x4 - 32 - read-write - 0 - 0x7FF - - - CBSR - ControlBulkServiceRatio. - 0 - 2 - read-write - - - PLE - PeriodicListEnable. - 2 - 1 - read-write - - - IE - IsochronousEnable. - 3 - 1 - read-write - - - CLE - ControlListEnable. - 4 - 1 - read-write - - - BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. - 5 - 1 - read-write - - - HCFS - HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin 1 ms later. - 6 - 2 - read-write - - - IR - InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. - 8 - 1 - read-write - - - RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling. - 9 - 1 - read-write - - - RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature upon the detection of upstream resume signaling. - 10 - 1 - read-write - - - - - HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) - 0x8 - 32 - read-write - 0 - 0xCF - - - HCR - HostControllerReset This bit is set by HCD to initiate a software reset of HC. - 0 - 1 - read-write - - - CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. - 1 - 1 - read-write - - - BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. - 2 - 1 - read-write - - - OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC. - 3 - 1 - read-write - - - SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error. - 6 - 2 - read-write - - - - - HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits - 0xC - 32 - read-write - 0 - 0xFFFFFC7F - - - SO - SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and after the update of HccaFrameNumber. - 0 - 1 - read-write - - - WDH - WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead. - 1 - 1 - read-write - - - SF - StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. - 2 - 1 - read-write - - - RD - ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling. - 3 - 1 - read-write - - - UE - UnrecoverableError This bit is set when HC detects a system error not related to USB. - 4 - 1 - read-write - - - FNO - FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value, from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated. - 5 - 1 - read-write - - - RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed. - 6 - 1 - read-write - - - OC - OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus. - 10 - 22 - read-write - - - - - HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt - 0x10 - 32 - read-write - 0 - 0xC000007F - - - SO - Scheduling Overrun interrupt. - 0 - 1 - read-write - - - WDH - HcDoneHead Writeback interrupt. - 1 - 1 - read-write - - - SF - Start of Frame interrupt. - 2 - 1 - read-write - - - RD - Resume Detect interrupt. - 3 - 1 - read-write - - - UE - Unrecoverable Error interrupt. - 4 - 1 - read-write - - - FNO - Frame Number Overflow interrupt. - 5 - 1 - read-write - - - RHSC - Root Hub Status Change interrupt. - 6 - 1 - read-write - - - OC - Ownership Change interrupt. - 30 - 1 - read-write - - - MIE - Master Interrupt Enable. - 31 - 1 - read-write - - - - - HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt - 0x14 - 32 - read-write - 0 - 0xC000007F - - - SO - Scheduling Overrun interrupt. - 0 - 1 - read-write - - - WDH - HcDoneHead Writeback interrupt. - 1 - 1 - read-write - - - SF - Start of Frame interrupt. - 2 - 1 - read-write - - - RD - Resume Detect interrupt. - 3 - 1 - read-write - - - UE - Unrecoverable Error interrupt. - 4 - 1 - read-write - - - FNO - Frame Number Overflow interrupt. - 5 - 1 - read-write - - - RHSC - Root Hub Status Change interrupt. - 6 - 1 - read-write - - - OC - Ownership Change interrupt. - 30 - 1 - read-write - - - MIE - A 0 written to this field is ignored by HC. - 31 - 1 - read-write - - - - - HCHCCA - Contains the physical address of the host controller communication area - 0x18 - 32 - read-write - 0 - 0xFFFFFF00 - - - HCCA - Base address of the Host Controller Communication Area. - 8 - 24 - read-write - - - - - HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor - 0x1C - 32 - read-write - 0 - 0xFFFFFFF0 - - - PCED - The content of this register is updated by HC after a periodic ED is processed. - 4 - 28 - read-only - - - - - HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list - 0x20 - 32 - read-write - 0 - 0xFFFFFFF0 - - - CHED - HC traverses the Control list starting with the HcControlHeadED pointer. - 4 - 28 - read-write - - - - - HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list - 0x24 - 32 - read-write - 0 - 0xFFFFFFF0 - - - CCED - ControlCurrentED. - 4 - 28 - read-write - - - - - HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list - 0x28 - 32 - read-write - 0 - 0xFFFFFFF0 - - - BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer. - 4 - 28 - read-write - - - - - HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list - 0x2C - 32 - read-write - 0 - 0xFFFFFFF0 - - - BCED - BulkCurrentED This is advanced to the next ED after the HC has served the current one. - 4 - 28 - read-write - - - - - HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue - 0x30 - 32 - read-write - 0 - 0xFFFFFFF0 - - - DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. - 4 - 28 - read-only - - - - - HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun - 0x34 - 32 - read-write - 0x2EDF - 0xFFFF3FFF - - - FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times. - 0 - 14 - read-write - - - FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame. - 16 - 15 - read-write - - - FIT - FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval. - 31 - 1 - read-write - - - - - HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame - 0x38 - 32 - read-write - 0 - 0x80003FFF - - - FR - FrameRemaining This counter is decremented at each bit time. - 0 - 14 - read-only - - - FRT - FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0. - 31 - 1 - read-only - - - - - HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD - 0x3C - 32 - read-write - 0 - 0xFFFF - - - FN - FrameNumber This is incremented when HcFmRemaining is re-loaded. - 0 - 16 - read-only - - - - - HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list - 0x40 - 32 - read-write - 0 - 0x3FFF - - - PS - PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization. - 0 - 14 - read-write - - - - - HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF - 0x44 - 32 - read-write - 0x628 - 0xFFF - - - LST - LSThreshold This field contains a value which is compared to the FrameRemaining field prior to initiating a Low Speed transaction. - 0 - 12 - read-write - - - - - HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub - 0x48 - 32 - read-write - 0xFF000902 - 0xFF001FFF - - - NDP - NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub. - 0 - 8 - read-write - - - PSM - PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled. - 8 - 1 - read-write - - - NPS - NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered. - 9 - 1 - read-write - - - DT - DeviceType This bit specifies that the root hub is not a compound device. - 10 - 1 - read-write - - - OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported. - 11 - 1 - read-write - - - NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported. - 12 - 1 - read-write - - - POTPGT - PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before accessing a powered-on port of the root hub. - 24 - 8 - read-write - - - - - HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub - 0x4C - 32 - read-write - 0 - 0x3FFFFFFF - - - DR - DeviceRemovable Each bit is dedicated to a port of the Root Hub. - 0 - 16 - read-write - - - PPCM - PortPowerControlMask Each bit indicates if a port is affected by a global power control command when PowerSwitchingMode is set. - 16 - 16 - read-write - - - - - HCRHSTATUS - This register is divided into two parts - 0x50 - 32 - read-write - 0 - 0x80038003 - - - LPS - (read) LocalPowerStatus The Root Hub does not support the local power status feature; thus, this bit is always read as 0. - 0 - 1 - read-write - - - OCI - OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented. - 1 - 1 - read-write - - - DRWE - (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected interrupt. - 15 - 1 - read-write - - - LPSC - (read) LocalPowerStatusChange The root hub does not support the local power status feature. - 16 - 1 - read-write - - - OCIC - OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register. - 17 - 1 - read-write - - - CRWE - (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable. - 31 - 1 - read-write - - - - - HCRHPORTSTATUS - Controls and reports the port events on a per-port basis - 0x54 - 32 - read-write - 0 - 0x1F031F - - - CCS - (read) CurrentConnectStatus This bit reflects the current state of the downstream port. - 0 - 1 - read-write - - - PES - (read) PortEnableStatus This bit indicates whether the port is enabled or disabled. - 1 - 1 - read-write - - - PSS - (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence. - 2 - 1 - read-write - - - POCI - (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in such a way that overcurrent conditions are reported on a per-port basis. - 3 - 1 - read-write - - - PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. - 4 - 1 - read-write - - - PPS - (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type of power switching implemented. - 8 - 1 - read-write - - - LSDA - (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. - 9 - 1 - read-write - - - CSC - ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. - 16 - 1 - read-write - - - PESC - PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared. - 17 - 1 - read-write - - - PSSC - PortSuspendStatusChange This bit is set when the full resume sequence is completed. - 18 - 1 - read-write - - - OCIC - PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis. - 19 - 1 - read-write - - - PRSC - PortResetStatusChange This bit is set at the end of the 10 ms port reset signal. - 20 - 1 - read-write - - - - - PORTMODE - Controls the port if it is attached to the host block or the device block - 0x5C - 32 - read-write - 0 - 0x10101 - - - ID - Port ID pin value. - 0 - 1 - read-write - - - ID_EN - Port ID pin pull-up enable. - 8 - 1 - read-write - - - DEV_ENABLE - 1: device 0: host. - 16 - 1 - read-write - - - - - - - USBHSH - USB1 High-speed Host Controller - USBHSH - 0x400A3000 - - 0 - 0x54 - registers - - - USB1 - 47 - - - USB1_NEEDCLK - 48 - - - - CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block - 0 - 32 - read-only - 0x1010010 - 0xFFFF00FF - - - CAPLENGTH - Capability Length: This is used as an offset. - 0 - 8 - read-only - - - CHIPID - Chip identification: indicates major and minor revision of the IP: [31:24] = Major revision [23:16] = Minor revision Major revisions used: 0x01: USB2. - 16 - 16 - read-only - - - - - HCSPARAMS - Host Controller Structural Parameters - 0x4 - 32 - read-only - 0x10011 - 0x1001F - - - N_PORTS - This register specifies the number of physical downstream ports implemented on this host controller. - 0 - 4 - read-only - - - PPC - This field indicates whether the host controller implementation includes port power control. - 4 - 1 - read-only - - - P_INDICATOR - This bit indicates whether the ports support port indicator control. - 16 - 1 - read-only - - - - - FLADJ_FRINDEX - Frame Length Adjustment - 0xC - 32 - read-write - 0x20 - 0x3FFF003F - - - FLADJ - Frame Length Timing Value. - 0 - 6 - read-write - - - FRINDEX - Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet. - 16 - 14 - read-write - - - - - ATLPTD - Memory base address where ATL PTD0 is stored - 0x10 - 32 - read-write - 0 - 0xFFFFFFF0 - - - ATL_CUR - This indicates the current PTD that is used by the hardware when it is processing the ATL list. - 4 - 5 - read-write - - - ATL_BASE - Base address to be used by the hardware to find the start of the ATL list. - 9 - 23 - read-write - - - - - ISOPTD - Memory base address where ISO PTD0 is stored - 0x14 - 32 - read-write - 0 - 0xFFFFFFE0 - - - ISO_FIRST - This indicates the first PTD that is used by the hardware when it is processing the ISO list. - 5 - 5 - read-write - - - ISO_BASE - Base address to be used by the hardware to find the start of the ISO list. - 10 - 22 - read-write - - - - - INTPTD - Memory base address where INT PTD0 is stored - 0x18 - 32 - read-write - 0 - 0xFFFFFFE0 - - - INT_FIRST - This indicates the first PTD that is used by the hardware when it is processing the INT list. - 5 - 5 - read-write - - - INT_BASE - Base address to be used by the hardware to find the start of the INT list. - 10 - 22 - read-write - - - - - DATAPAYLOAD - Memory base address that indicates the start of the data payload buffers - 0x1C - 32 - read-write - 0 - 0xFFFF0000 - - - DAT_BASE - Base address to be used by the hardware to find the start of the data payload section. - 16 - 16 - read-write - - - - - USBCMD - USB Command register - 0x20 - 32 - read-write - 0 - 0x1F00078F - - - RS - Run/Stop: 1b = Run. - 0 - 1 - read-write - - - HCRESET - Host Controller Reset: This control bit is used by the software to reset the host controller. - 1 - 1 - read-write - - - FLS - Frame List Size: This field specifies the size of the frame list. - 2 - 2 - read-write - - - LHCR - Light Host Controller Reset: This bit allows the driver software to reset the host controller without affecting the state of the ports. - 7 - 1 - read-write - - - ATL_EN - ATL List enabled. - 8 - 1 - read-write - - - ISO_EN - ISO List enabled. - 9 - 1 - read-write - - - INT_EN - INT List enabled. - 10 - 1 - read-write - - - - - USBSTS - USB Interrupt Status register - 0x24 - 32 - read-write - 0 - 0xF000C - - - PCD - Port Change Detect: The host controller sets this bit to logic 1 when any port has a change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a result of a J-K transition detected on a suspended port. - 2 - 1 - read-write - - - FLR - Frame List Rollover: The host controller sets this bit to logic 1 when the frame list index rolls over its maximum value to 0. - 3 - 1 - read-write - - - ATL_IRQ - ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed. - 16 - 1 - read-write - - - ISO_IRQ - ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed. - 17 - 1 - read-write - - - INT_IRQ - INT IRQ: Indicates that an INT PTD (with I-bit set) was completed. - 18 - 1 - read-write - - - SOF_IRQ - SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set. - 19 - 1 - read-write - - - - - USBINTR - USB Interrupt Enable register - 0x28 - 32 - read-write - 0 - 0xF000C - - - PCDE - Port Change Detect Interrupt Enable: 1: enable 0: disable. - 2 - 1 - read-write - - - FLRE - Frame List Rollover Interrupt Enable: 1: enable 0: disable. - 3 - 1 - read-write - - - ATL_IRQ_E - ATL IRQ Enable bit: 1: enable 0: disable. - 16 - 1 - read-write - - - ISO_IRQ_E - ISO IRQ Enable bit: 1: enable 0: disable. - 17 - 1 - read-write - - - INT_IRQ_E - INT IRQ Enable bit: 1: enable 0: disable. - 18 - 1 - read-write - - - SOF_E - SOF Interrupt Enable bit: 1: enable 0: disable. - 19 - 1 - read-write - - - - - PORTSC1 - Port Status and Control register - 0x2C - 32 - read-write - 0 - 0xFFFFDFFF - - - CCS - Current Connect Status: Logic 1 indicates a device is present on the port. - 0 - 1 - read-write - - - CSC - Connect Status Change: Logic 1 means that the value of CCS has changed. - 1 - 1 - read-write - - - PED - Port Enabled/Disabled. - 2 - 1 - read-write - - - PEDC - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed. - 3 - 1 - read-write - - - OCA - Over-current active: Logic 1 means that this port has an over-current condition. - 4 - 1 - read-write - - - OCC - Over-current change: Logic 1 means that the value of OCA has changed. - 5 - 1 - read-write - - - FPR - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port. - 6 - 1 - read-write - - - SUSP - Suspend: Logic 1 means port is in the suspend state. - 7 - 1 - read-write - - - PR - Port Reset: Logic 1 means the port is in the reset state. - 8 - 1 - read-write - - - LS - Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. - 10 - 2 - read-only - - - PP - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register. - 12 - 1 - read-write - - - PIC - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is logic 0. - 14 - 2 - read-write - - - PTC - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value. - 16 - 4 - read-write - - - PSPD - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved. - 20 - 2 - read-write - - - WOO - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to overcurrent conditions as wake-up events. - 22 - 1 - read-write - - - - - ATLPTDD - Done map for each ATL PTD - 0x30 - 32 - read-write - 0 - 0xFFFFFFFF - - - ATL_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - 0 - 32 - read-write - - - - - ATLPTDS - Skip map for each ATL PTD - 0x34 - 32 - read-write - 0 - 0xFFFFFFFF - - - ATL_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be skipped, independent of the V bit setting. - 0 - 32 - read-write - - - - - ISOPTDD - Done map for each ISO PTD - 0x38 - 32 - read-write - 0 - 0xFFFFFFFF - - - ISO_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - 0 - 32 - read-write - - - - - ISOPTDS - Skip map for each ISO PTD - 0x3C - 32 - read-write - 0 - 0xFFFFFFFF - - - ISO_SKIP - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - 0 - 32 - read-write - - - - - INTPTDD - Done map for each INT PTD - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - INT_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - 0 - 32 - read-write - - - - - INTPTDS - Skip map for each INT PTD - 0x44 - 32 - read-write - 0 - 0xFFFFFFFF - - - INT_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be skipped, independent of the V bit setting. - 0 - 32 - read-write - - - - - LASTPTD - Marks the last PTD in the list for ISO, INT and ATL - 0x48 - 32 - read-write - 0 - 0x1F1F1F - - - ATL_LAST - If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed. - 0 - 5 - read-write - - - ISO_LAST - This indicates the last PTD in the ISO list. - 8 - 5 - read-write - - - INT_LAST - This indicates the last PTD in the INT list. - 16 - 5 - read-write - - - - - PORTMODE - Controls the port if it is attached to the host block or the device block - 0x50 - 32 - read-write - 0x40000 - 0xD0101 - - - DEV_ENABLE - If this bit is set to one, one of the ports will behave as a USB device. - 16 - 1 - read-write - - - SW_CTRL_PDCOM - This bit indicates if the PHY power-down input is controlled by software or by hardware. - 18 - 1 - read-write - - - SW_PDCOM - This bit is only used when SW_CTRL_PDCOM is set to 1b. - 19 - 1 - read-write - - - - - - - HASHCRYPT - Hash-Crypt peripheral - HASHCRYPT - 0x400A4000 - - 0 - 0xA0 - registers - - - HASHCRYPT - 54 - - - - CTRL - Control register to enable and operate Hash and Crypto - 0 - 32 - read-write - 0 - 0x3317 - - - Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if specific modes beyond SHA1 and SHA2-256 are available. - 0 - 3 - read-write - - - DISABLED - Disabled - 0 - - - SHA1 - SHA1 is enabled - 0x1 - - - SHA2_256 - SHA2-256 is enabled - 0x2 - - - AES - AES if available (see also CRYPTCFG register for more controls) - 0x4 - - - ICB_AES - ICB-AES if available (see also CRYPTCFG register for more controls) - 0x5 - - - - - New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING Status bit will clear for a cycle during the initialization from New=1. - 4 - 1 - write-only - - - START - Starts a new Hash/Crypto and initializes the Digest/Result. - 0x1 - - - - - DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words and then will process the Hash. If Cryptographic, it will load as many words as needed, including key if not already loaded. It will then request again. Normal model is that the DMA interrupts the processor when its length expires. Note that if the processor will write the key and optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be expected to load those for the 1st block (when needed). - 8 - 1 - read-write - - - NOT_USED - DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used. - 0 - - - PUSH - DMA will push in the data. - 0x1 - - - - - DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the DMA has to know to switch direction and the locations. This can be used for crypto uses. - 9 - 1 - read-write - - - NOTUSED - DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. - 0 - - - - - HASHSWPB - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For cryptographic swapping, see the CRYPTCFG register. - 12 - 1 - read-write - - - - - STATUS - Indicates status of Hash peripheral. - 0x4 - 32 - read-write - 0 - 0x3F0037 - - - WAITING - If 1, the block is waiting for more data to process. - 0 - 1 - read-only - - - NOT_WAITING - Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set if IsLast is set nor will it set until at least 1 word is read of the output. - 0 - - - WAITING - Waiting for data to be written in (16 words) - 0x1 - - - - - DIGEST - For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block already started. For Cryptographic uses, this will be set for each block processed, indicating OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared when any data is written, when New is written, for Cryptographic uses when the last word is read out, or when the block is disabled. - 1 - 1 - read-only - - - NOT_READY - No Digest is ready - 0 - - - READY - Digest is ready. Application may read it or may write more data - 0x1 - - - - - ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT field will indicate which block it was on. - 2 - 1 - read-write - oneToClear - - - NO_ERROR - No error. - 0 - - - ERROR - An error occurred since last cleared (written 1 to clear). - 0x1 - - - - - NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING) - 4 - 1 - read-only - - - NOT_NEED - No Key is needed and writes will not be treated as Key - 0 - - - NEED - Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. - 0x1 - - - - - NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING) - 5 - 1 - read-only - - - NOT_NEED - No IV/Nonce is needed, either because written already or because not needed. - 0 - - - NEED - IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. - 0x1 - - - - - ICBIDX - If ICB-AES is selected, then reads as the ICB index count based on ICBSTRM (from CRYPTCFG). That is, if 3 bits of ICBSTRM, then this will count from 0 to 7 and then back to 0. On 0, it has to compute the full ICB, quicker when not 0. - 16 - 6 - read-only - - - - - INTENSET - Write 1 to enable interrupts; reads back with which are set. - 0x8 - 32 - read-write - 0 - 0x7 - - - WAITING - Indicates if should interrupt when waiting for data input. - 0 - 1 - read-write - - - NO_INTERRUPT - Will not interrupt when waiting. - 0 - - - INTERRUPT - Will interrupt when waiting - 0x1 - - - - - DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). - 1 - 1 - read-write - - - NO_INTERRUPT - Will not interrupt when Digest is ready - 0 - - - INTERRUPT - Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). - 0x1 - - - - - ERROR - Indicates if should interrupt on an ERROR (as defined in Status) - 2 - 1 - read-write - - - NOT_INTERRUPT - Will not interrupt on Error. - 0 - - - INTERRUPT - Will interrupt on Error (until cleared). - 0x1 - - - - - - - INTENCLR - Write 1 to clear interrupts. - 0xC - 32 - read-write - 0 - 0 - - - WAITING - Write 1 to clear mask. - 0 - 1 - read-write - oneToClear - - - DIGEST - Write 1 to clear mask. - 1 - 1 - read-write - oneToClear - - - ERROR - Write 1 to clear mask. - 2 - 1 - read-write - oneToClear - - - - - MEMCTRL - Setup Master to access memory (if available) - 0x10 - 32 - read-write - 0 - 0x7FF0001 - - - MASTER - Enables mastering. - 0 - 1 - read-write - - - NOT_USED - Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. - 0 - - - ENABLED - Mastering is enabled and DMA and INDATA should not be used. - 0x1 - - - - - COUNT - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks to copy starting at MEMADDR. This register will decrement after each block is copied, ending in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA interrupt will occur on ever block. If a bus error occurs, it will stop with this field set to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) blocks to hash. - 16 - 11 - read-write - - - - - MEMADDR - Address to start memory access from (if available). - 0x14 - 32 - read-write - 0 - 0xFFFFFFFF - - - BASE - Address base to start copying from, word aligned (so bits 1:0 must be 0). This field will advance as it processes the words. If it fails with a bus error, the register will contain the failing word. N:Address in Flash or RAM space; RAM only as mapped in this part. May also be able to address SPIFI. - 0 - 32 - read-write - - - - - INDATA - Input of 16 words at a time to load up buffer. - 0x20 - 32 - write-only - 0 - 0 - - - DATA - Write next word in little-endian form. The hash requires big endian word data, but this block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block will swap the word to restore into big endian. - 0 - 32 - write-only - - - - - 7 - 0x4 - ALIAS[%s] - no description available - 0x24 - 32 - write-only - 0 - 0 - - - DATA - Write next word in little-endian form. The hash requires big endian word data, but this block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block will swap the word to restore into big endian. - 0 - 32 - write-only - - - - - 8 - 0x4 - DIGEST0[%s] - no description available - 0x40 - 32 - read-only - 0 - 0xFFFFFFFF - - - DIGEST - One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1. - 0 - 32 - read-only - - - - - CRYPTCFG - Crypto settings for AES and Salsa and ChaCha - 0x80 - 32 - read-write - 0 - 0xF31FFF - - - MSW1ST_OUT - If 1, OUTDATA0 will be read Most significant word 1st for AES. Else it will be read in normal little endian - Least significant word 1st. Note: only if allowed by configuration. - 0 - 1 - read-write - - - SWAPKEY - If 1, will Swap the key input (bytes in each word). - 1 - 1 - read-write - - - SWAPDAT - If 1, will SWAP the data and IV inputs (bytes in each word). - 2 - 1 - read-write - - - MSW1ST - If 1, load of key, IV, and data is MSW 1st for AES. Else, the words are little endian. Note: only if allowed by configuration. - 3 - 1 - read-write - - - AESMODE - AES Cipher mode to use if plain AES - 4 - 2 - read-write - - - ECB - ECB - used as is - 0 - - - CBC - CBC mode (see details on IV/nonce) - 0x1 - - - CTR - CTR mode (see details on IV/nonce). See also AESCTRPOS. - 0x2 - - - - - AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB - 6 - 1 - read-write - - - ENCRYPT - Encrypt - 0 - - - DECRYPT - Decrypt - 0x1 - - - - - AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are used, only the highest level is permitted to select this. - 7 - 1 - read-write - - - NORMAL_WAY - User key provided in normal way - 0 - - - HIDDEN_WAY - Secret key provided in hidden way by HW - 0x1 - - - - - AESKEYSZ - Sets the AES key size - 8 - 2 - read-write - - - BITS_128 - 128 bit key - 0 - - - BITS_192 - 192 bit key - 0x1 - - - BITS_256 - 256 bit key - 0x2 - - - - - AESCTRPOS - Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other use CTR should use ECB directly and do its own XOR and so on. - 10 - 3 - read-write - - - STREAMLAST - Is 1 if last stream block. If not 1, then the engine will compute the next "hash". - 16 - 1 - read-write - - - ICBSZ - This sets the ICB size between 32 and 128 bits, using the following rules. Note that the counter is assumed to occupy the low order bits of the IV. - 20 - 2 - read-write - - - BITS_32 - 32 bits of the IV/ctr are used (from 127:96) - 0 - - - BITS_64 - 64 bits of the IV/ctr are used (from 127:64) - 0x1 - - - BITS_96 - 96 bits of the IV/ctr are used (from 127:32) - 0x2 - - - BIT_128 - All 128 bits of the IV/ctr are used - 0x3 - - - - - ICBSTRM - The size of the ICB-AES stream that can be pushed before needing to compute a new IV/ctr (counter start). This optimizes the performance of the stream of blocks after the 1st. - 22 - 2 - read-write - - - BLOCKS_8 - 8 blocks - 0 - - - BLOCKS_16 - 16 blocks - 0x1 - - - BLOCKS_32 - 32 blocks - 0x2 - - - BLOCKS_64 - 64 blocks - 0x3 - - - - - - - CONFIG - Returns the configuration of this block in this chip - indicates what services are available. - 0x84 - 32 - read-write - 0 - 0 - - - DUAL - 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit - 0 - 1 - read-only - - - DMA - 1 if DMA is connected - 1 - 1 - read-only - - - AHB - 1 if AHB Master is enabled - 3 - 1 - read-only - - - AES - 1 if AES 128 included - 6 - 1 - read-only - - - AESKEY - 1 if AES 192 and 256 also included - 7 - 1 - read-only - - - SECRET - 1 if AES Secret key available - 8 - 1 - read-only - - - ICB - 1 if ICB over AES included - 11 - 1 - read-only - - - - - LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. - 0x8C - 32 - read-write - 0 - 0xFFF3 - - - SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. If locked already, may only write if at same or higher security level as lock. Reads as: 0 if unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the only readable registers if locked and current state is lower than lock level. - 0 - 2 - read-write - - - UNLOCK - Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests. - 0 - - - LOCK - Locks to the current security level. AHB Master will issue requests at this level. - 0x1 - - - - - PATTERN - Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0 - 4 - 12 - read-write - - - - - 4 - 0x4 - MASK[%s] - no description available - 0x90 - 32 - write-only - 0 - 0 - - - MASK - A random word. - 0 - 32 - write-only - - - - - - - CASPER - CASPER - CASPER - 0x400A5000 - - 0 - 0x84 - registers - - - CASER - 55 - - - - CTRL0 - Contains the offsets of AB and CD in the RAM. - 0 - 32 - read-write - 0 - 0x1FFD0005 - - - ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up - 0 - 1 - read-write - - - PAIR0 - Bank-pair 0 (1st) - 0 - - - PAIR1 - Bank-pair 1 (2nd) - 0x1 - - - - - ABOFF - Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up - 2 - 11 - read-write - - - CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up - 16 - 1 - read-write - - - PAIR0 - Bank-pair 0 (1st) - 0 - - - PAIR1 - Bank-pair 1 (2nd) - 0x1 - - - - - CDOFF - Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the AB values - 18 - 11 - read-write - - - - - CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. - 0x4 - 32 - read-write - 0 - 0xDFFDFFFF - - - ITER - Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate. - 0 - 8 - read-write - - - MODE - Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active. - 8 - 8 - read-write - - - RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally this is not the same bank as ABBPAIR (when 4-up supported) - 16 - 1 - read-write - - - PAIR0 - Bank-pair 0 (1st) - 0 - - - PAIR1 - Bank-pair 1 (2nd) - 0x1 - - - - - RESOFF - Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the AB and CD values - 18 - 11 - read-write - - - CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: - 30 - 2 - read-write - - - NO_SKIP - No Skip - 0 - - - SKIP_IF_1 - Skip if Carry is 1 - 0x1 - - - SKIP_IF_0 - Skip if Carry is 0 - 0x2 - - - SET_AND_SKIP - Set CTRLOFF to CDOFF and Skip - 0x3 - - - - - - - LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. - 0x8 - 32 - read-write - 0 - 0x1FFD00FF - - - COUNT - Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one op - does not iterate, write N means N control pairs to load - 0 - 8 - read-write - - - CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not matter which bank is used as this is loaded when not performing an operation. - 16 - 1 - read-write - - - PAIR0 - Bank-pair 0 (1st) - 0 - - - PAIR1 - Bank-pair 1 (2nd) - 0x1 - - - - - CTRLOFF - DWord Offset of CTRL pair to load next. - 18 - 11 - read-write - - - - - STATUS - Indicates operational status and would contain the carry bit if used. - 0xC - 32 - read-write - 0 - 0x31 - - - DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. - 0 - 1 - read-write - - - BUSY - Busy or just cleared - 0 - - - COMPLETED - Completed last operation - 0x1 - - - - - CARRY - Last carry value if operation produced a carry bit - 4 - 1 - read-only - - - NO_CARRY - Carry was 0 or no carry - 0 - - - CARRY - Carry was 1 - 0x1 - - - - - BUSY - Indicates if the accelerator is busy performing an operation - 5 - 1 - read-only - - - IDLE - Not busy - is idle - 0 - - - BUSY - Is busy - 0x1 - - - - - - - INTENSET - Sets interrupts - 0x10 - 32 - read-write - 0 - 0x1 - - - DONE - Set if the accelerator should interrupt when done. - 0 - 1 - read-write - - - NO_INTERRUPT - Do not interrupt when done - 0 - - - INTERRUPT - Interrupt when done - 0x1 - - - - - - - INTENCLR - Clears interrupts - 0x14 - 32 - read-write - 0 - 0x1 - - - DONE - Written to clear an interrupt set with INTENSET. - 0 - 1 - read-write - oneToClear - - - IGNORED - If written 0, ignored - 0 - - - NO_INTERRUPT - If written 1, do not Interrupt when done - 0x1 - - - - - - - INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) - 0x18 - 32 - read-write - 0 - 0x1 - - - DONE - If set, interrupt is caused by accelerator being done. - 0 - 1 - read-only - - - NOT_CAUSED - Not caused by accelerator being done - 0 - - - CAUSED - Caused by accelerator being done - 0x1 - - - - - - - AREG - A register - 0x20 - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - BREG - B register - 0x24 - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - CREG - C register - 0x28 - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - DREG - D register - 0x2C - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - RES0 - Result register 0 - 0x30 - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - RES1 - Result register 1 - 0x34 - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - RES2 - Result register 2 - 0x38 - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - RES3 - Result register 3 - 0x3C - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - MASK - Optional mask register - 0x60 - 32 - read-write - 0 - 0xFFFFFFFF - - - MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values - 0 - 32 - read-write - - - - - REMASK - Optional re-mask register - 0x64 - 32 - read-write - 0 - 0xFFFFFFFF - - - MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values - 0 - 32 - read-write - - - - - LOCK - Security lock register - 0x80 - 32 - read-write - 0 - 0x1FFFF - - - LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. - 0 - 1 - read-write - - - UNLOCK - unlock - 0 - - - LOCK - Lock to current security level - 0x1 - - - - - KEY - Must be written as 0x73D to change the register. - 4 - 13 - read-write - - - KWY_VALUE - If set during write, will allow lock or unlock - 0x73D - - - - - - - - - POWERQUAD - Digital Signal Co-Processing companion to a Cortex-M v8M CPU core - POWERQUAD - 0x400A6000 - - 0 - 0x260 - registers - - - PQ - 57 - - - - OUTBASE - Base address register for output region - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - outbase - Base address register for the output region - 0 - 32 - read-write - - - - - OUTFORMAT - Output format - 0x4 - 32 - read-write - 0 - 0xFF33 - - - out_formatint - Output Internal format (00: q15; 01:q31; 10:float) - 0 - 2 - read-write - - - out_formatext - Output External format (00: q15; 01:q31; 10:float) - 4 - 2 - read-write - - - out_scaler - Output Scaler value (for scaled 'q31' formats) - 8 - 8 - read-write - - - - - TMPBASE - Base address register for temp region - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - tmpbase - Base address register for the temporary region - 0 - 32 - read-write - - - - - TMPFORMAT - Temp format - 0xC - 32 - read-write - 0 - 0xFF33 - - - tmp_formatint - Temp Internal format (00: q15; 01:q31; 10:float) - 0 - 2 - read-write - - - tmp_formatext - Temp External format (00: q15; 01:q31; 10:float) - 4 - 2 - read-write - - - tmp_scaler - Temp Scaler value (for scaled 'q31' formats) - 8 - 8 - read-write - - - - - INABASE - Base address register for input A region - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - inabase - Base address register for the input A region - 0 - 32 - read-write - - - - - INAFORMAT - Input A format - 0x14 - 32 - read-write - 0 - 0xFF33 - - - ina_formatint - Input A Internal format (00: q15; 01:q31; 10:float) - 0 - 2 - read-write - - - ina_formatext - Input A External format (00: q15; 01:q31; 10:float) - 4 - 2 - read-write - - - ina_scaler - Input A Scaler value (for scaled 'q31' formats) - 8 - 8 - read-write - - - - - INBBASE - Base address register for input B region - 0x18 - 32 - read-write - 0 - 0xFFFFFFFF - - - inbbase - Base address register for the input B region - 0 - 32 - read-write - - - - - INBFORMAT - Input B format - 0x1C - 32 - read-write - 0 - 0xFF33 - - - inb_formatint - Input B Internal format (00: q15; 01:q31; 10:float) - 0 - 2 - read-write - - - inb_formatext - Input B External format (00: q15; 01:q31; 10:float) - 4 - 2 - read-write - - - inb_scaler - Input B Scaler value (for scaled 'q31' formats) - 8 - 8 - read-write - - - - - CONTROL - PowerQuad Control register - 0x100 - 32 - read-write - 0 - 0x8000FFFF - - - decode_opcode - opcode specific to decode_machine - 0 - 4 - read-write - - - decode_machine - 0 : Coprocessor , 1 : matrix , 2 : fft , 3 : fir , 4 : stat , 5 : cordic , 6 -15 : NA - 4 - 4 - read-write - - - inst_busy - Instruction busy signal when high indicates processing is on - 31 - 1 - read-only - - - - - LENGTH - Length register - 0x104 - 32 - read-write - 0 - 0xFFFFFFFF - - - inst_length - Length register. When FIR : fir_xlength = inst_length[15:0] , fir_tlength = inst_len[31:16]. When MTX : rows_a = inst_length[4:0] , cols_a = inst_length[12:8] , cols_b = inst_length[20:16] - 0 - 32 - read-write - - - - - CPPRE - Pre-scale register - 0x108 - 32 - read-write - 0 - 0x3FFFF - - - cppre_in - co-processor scaling of input - 0 - 8 - read-write - - - cppre_out - co-processor fixed point output - 8 - 8 - read-write - - - cppre_sat - 1 : forces sub-32 bit saturation - 16 - 1 - read-write - - - cppre_sat8 - 0 = 8bits, 1 = 16bits - 17 - 1 - read-write - - - - - MISC - Misc register - 0x10C - 32 - read-write - 0 - 0xFFFFFFFF - - - inst_misc - Misc register. For Matrix : Used for scale factor - 0 - 32 - read-write - - - - - CURSORY - Cursory register - 0x110 - 32 - read-write - 0 - 0x1 - - - cursory - 1 : Enable cursory mode - 0 - 1 - read-write - - - - - CORDIC_X - Cordic input X register - 0x180 - 32 - read-write - 0 - 0xFFFFFFFF - - - cordic_x - Cordic input x - 0 - 32 - read-write - - - - - CORDIC_Y - Cordic input Y register - 0x184 - 32 - read-write - 0 - 0xFFFFFFFF - - - cordic_y - Cordic input y - 0 - 32 - read-write - - - - - CORDIC_Z - Cordic input Z register - 0x188 - 32 - read-write - 0 - 0xFFFFFFFF - - - cordic_z - Cordic input z - 0 - 32 - read-write - - - - - ERRSTAT - Read/Write register where error statuses are captured (sticky) - 0x18C - 32 - read-write - 0 - 0x1F - - - OVERFLOW - overflow - 0 - 1 - read-write - - - NAN - nan - 1 - 1 - read-write - - - FIXEDOVERFLOW - fixed_pt_overflow - 2 - 1 - read-write - - - UNDERFLOW - underflow - 3 - 1 - read-write - - - BUSERROR - bus_error - 4 - 1 - read-write - - - - - INTREN - INTERRUPT enable register - 0x190 - 32 - read-write - 0 - 0x7F - - - intr_oflow - 1 : Enable interrupt on Floating point overflow - 0 - 1 - read-write - - - intr_nan - 1 : Enable interrupt on Floating point NaN - 1 - 1 - read-write - - - intr_fixed - 1: Enable interrupt on Fixed point Overflow - 2 - 1 - read-write - - - intr_uflow - 1 : Enable interrupt on Subnormal truncation - 3 - 1 - read-write - - - intr_berr - 1: Enable interrupt on AHBM Buss Error - 4 - 1 - read-write - - - intr_comp - 1: Enable interrupt on instruction completion - 7 - 1 - read-write - - - - - EVENTEN - Event Enable register - 0x194 - 32 - read-write - 0 - 0xFFFFFFFF - - - event_oflow - 1 : Enable event trigger on Floating point overflow - 0 - 1 - read-write - - - event_nan - 1 : Enable event trigger on Floating point NaN - 1 - 1 - read-write - - - event_fixed - 1: Enable event trigger on Fixed point Overflow - 2 - 1 - read-write - - - event_uflow - 1 : Enable event trigger on Subnormal truncation - 3 - 1 - read-write - - - event_berr - 1: Enable event trigger on AHBM Buss Error - 4 - 1 - read-write - - - event_comp - 1: Enable event trigger on instruction completion - 7 - 1 - read-write - - - - - INTRSTAT - INTERRUPT STATUS register - 0x198 - 32 - read-write - 0 - 0x1 - - - intr_stat - Intr status ( 1 bit to indicate interrupt captured, 0 means no new interrupt), write any value will clear this bit - 0 - 1 - read-write - - - - - 16 - 0x4 - gpreg[%s] - General purpose register bank N. - 0x200 - 32 - read-write - 0 - 0x7CF73 - - - gpreg - General purpose register bank - 0 - 32 - read-write - - - - - 8 - 0x4 - compreg[%s] - Compute register bank - 0x240 - 32 - read-write - 0 - 0xFFFFFFFF - - - compreg - Compute register bank - 0 - 32 - read-write - - - - - - - SECGPIO - General Purpose I/O (GPIO) - GPIO - 0x400A8000 - - 0 - 0x2484 - registers - - - - B0_0 - Byte pin registers for all port GPIO pins - 0 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_1 - Byte pin registers for all port GPIO pins - 0x1 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_2 - Byte pin registers for all port GPIO pins - 0x2 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_3 - Byte pin registers for all port GPIO pins - 0x3 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_4 - Byte pin registers for all port GPIO pins - 0x4 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_5 - Byte pin registers for all port GPIO pins - 0x5 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_6 - Byte pin registers for all port GPIO pins - 0x6 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_7 - Byte pin registers for all port GPIO pins - 0x7 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_8 - Byte pin registers for all port GPIO pins - 0x8 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_9 - Byte pin registers for all port GPIO pins - 0x9 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_10 - Byte pin registers for all port GPIO pins - 0xA - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_11 - Byte pin registers for all port GPIO pins - 0xB - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_12 - Byte pin registers for all port GPIO pins - 0xC - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_13 - Byte pin registers for all port GPIO pins - 0xD - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_14 - Byte pin registers for all port GPIO pins - 0xE - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_15 - Byte pin registers for all port GPIO pins - 0xF - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_16 - Byte pin registers for all port GPIO pins - 0x10 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_17 - Byte pin registers for all port GPIO pins - 0x11 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_18 - Byte pin registers for all port GPIO pins - 0x12 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_19 - Byte pin registers for all port GPIO pins - 0x13 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_20 - Byte pin registers for all port GPIO pins - 0x14 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_21 - Byte pin registers for all port GPIO pins - 0x15 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_22 - Byte pin registers for all port GPIO pins - 0x16 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_23 - Byte pin registers for all port GPIO pins - 0x17 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_24 - Byte pin registers for all port GPIO pins - 0x18 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_25 - Byte pin registers for all port GPIO pins - 0x19 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_26 - Byte pin registers for all port GPIO pins - 0x1A - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_27 - Byte pin registers for all port GPIO pins - 0x1B - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_28 - Byte pin registers for all port GPIO pins - 0x1C - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_29 - Byte pin registers for all port GPIO pins - 0x1D - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_30 - Byte pin registers for all port GPIO pins - 0x1E - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_31 - Byte pin registers for all port GPIO pins - 0x1F - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - W0_0 - Word pin registers for all port GPIO pins - 0x1000 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_1 - Word pin registers for all port GPIO pins - 0x1004 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_2 - Word pin registers for all port GPIO pins - 0x1008 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_3 - Word pin registers for all port GPIO pins - 0x100C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_4 - Word pin registers for all port GPIO pins - 0x1010 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_5 - Word pin registers for all port GPIO pins - 0x1014 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_6 - Word pin registers for all port GPIO pins - 0x1018 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_7 - Word pin registers for all port GPIO pins - 0x101C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_8 - Word pin registers for all port GPIO pins - 0x1020 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_9 - Word pin registers for all port GPIO pins - 0x1024 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_10 - Word pin registers for all port GPIO pins - 0x1028 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_11 - Word pin registers for all port GPIO pins - 0x102C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_12 - Word pin registers for all port GPIO pins - 0x1030 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_13 - Word pin registers for all port GPIO pins - 0x1034 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_14 - Word pin registers for all port GPIO pins - 0x1038 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_15 - Word pin registers for all port GPIO pins - 0x103C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_16 - Word pin registers for all port GPIO pins - 0x1040 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_17 - Word pin registers for all port GPIO pins - 0x1044 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_18 - Word pin registers for all port GPIO pins - 0x1048 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_19 - Word pin registers for all port GPIO pins - 0x104C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_20 - Word pin registers for all port GPIO pins - 0x1050 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_21 - Word pin registers for all port GPIO pins - 0x1054 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_22 - Word pin registers for all port GPIO pins - 0x1058 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_23 - Word pin registers for all port GPIO pins - 0x105C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_24 - Word pin registers for all port GPIO pins - 0x1060 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_25 - Word pin registers for all port GPIO pins - 0x1064 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_26 - Word pin registers for all port GPIO pins - 0x1068 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_27 - Word pin registers for all port GPIO pins - 0x106C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_28 - Word pin registers for all port GPIO pins - 0x1070 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_29 - Word pin registers for all port GPIO pins - 0x1074 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_30 - Word pin registers for all port GPIO pins - 0x1078 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_31 - Word pin registers for all port GPIO pins - 0x107C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - DIR0 - Direction registers for all port GPIO pins - 0x2000 - 32 - read-write - 0 - 0xFFFFFFFF - - - DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output. - 0 - 32 - read-write - - - - - MASK0 - Mask register for all port GPIO pins - 0x2080 - 32 - read-write - 0 - 0xFFFFFFFF - - - MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. - 0 - 32 - read-write - - - - - PIN0 - Port pin register for all port GPIO pins - 0x2100 - 32 - read-write - 0 - 0xFFFFFFFF - - - PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. - 0 - 32 - read-write - - - - - MPIN0 - Masked port register for all port GPIO pins - 0x2180 - 32 - read-write - 0 - 0xFFFFFFFF - - - MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. - 0 - 32 - read-write - - - - - SET0 - Write: Set register for port. Read: output bits for port - 0x2200 - 32 - read-write - 0 - 0xFFFFFFFF - - - SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. - 0 - 32 - read-write - - - - - CLR0 - Clear port for all port GPIO pins - 0x2280 - 32 - write-only - 0 - 0 - - - CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit. - 0 - 32 - write-only - - - - - NOT0 - Toggle port for all port GPIO pins - 0x2300 - 32 - write-only - 0 - 0 - - - NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit. - 0 - 32 - write-only - - - - - DIRSET0 - Set pin direction bits for port - 0x2380 - 32 - write-only - 0 - 0 - - - DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit. - 0 - 32 - write-only - - - - - DIRCLR0 - Clear pin direction bits for port - 0x2400 - 32 - write-only - 0 - 0 - - - DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit. - 0 - 32 - write-only - - - - - DIRNOT0 - Toggle pin direction bits for port - 0x2480 - 32 - write-only - 0 - 0 - - - DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit. - 0 - 32 - write-only - - - - - - - AHB_SECURE_CTRL - AHB secure controller - AHB_SECURE_CTRL - 0x400AC000 - - 0 - 0x1000 - registers - - - - SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_FLASH_MEM_RULE0 - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_FLASH_MEM_RULE1 - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. - 0x14 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_FLASH_MEM_RULE2 - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. - 0x18 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_ROM_MEM_RULE0 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. - 0x20 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_ROM_MEM_RULE1 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. - 0x24 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_ROM_MEM_RULE2 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. - 0x28 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_ROM_MEM_RULE3 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. - 0x2C - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. - 0x30 - 32 - read-write - 0 - 0xFFFFFFFF - - - RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAMX_MEM_RULE0 - Security access rules for RAMX slaves. - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. - 0x50 - 32 - read-write - 0 - 0xFFFFFFFF - - - RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM0_MEM_RULE0 - Security access rules for RAM0 slaves. - 0x60 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM0_MEM_RULE1 - Security access rules for RAM0 slaves. - 0x64 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. - 0x70 - 32 - read-write - 0 - 0xFFFFFFFF - - - RAM1_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM1_MEM_RULE0 - Security access rules for RAM1 slaves. - 0x80 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM1_MEM_RULE1 - Security access rules for RAM1 slaves. - 0x84 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. - 0x90 - 32 - read-write - 0 - 0xFFFFFFFF - - - RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM2_MEM_RULE0 - Security access rules for RAM2 slaves. - 0xA0 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM2_MEM_RULE1 - Security access rules for RAM2 slaves. - 0xA4 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. - 0xB0 - 32 - read-write - 0 - 0xFFFFFFFF - - - RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM3_MEM_RULE0 - Security access rules for RAM3 slaves. - 0xC0 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM3_MEM_RULE1 - Security access rules for RAM3 slaves. - 0xC4 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. - 0xD0 - 32 - read-write - 0 - 0xFFFFFFFF - - - RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM4_MEM_RULE0 - Security access rules for RAM4 slaves. - 0xE0 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. - 0xF0 - 32 - read-write - 0 - 0xFFFFFFFF - - - APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - SYSCON_RULE - System Configuration - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - IOCON_RULE - I/O Configuration - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - GINT0_RULE - GPIO input Interrupt 0 - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - GINT1_RULE - GPIO input Interrupt 1 - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - PINT_RULE - Pin Interrupt and Pattern match - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SEC_PINT_RULE - Secure Pin Interrupt and Pattern match - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - INPUTMUX_RULE - Peripheral input multiplexing - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. - 0x104 - 32 - read-write - 0 - 0xFFFFFFFF - - - CTIMER0_RULE - Standard counter/Timer 0 - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - CTIMER1_RULE - Standard counter/Timer 1 - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - WWDT_RULE - Windiwed wtachdog Timer - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - MRT_RULE - Multi-rate Timer - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - UTICK_RULE - Micro-Timer - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. - 0x108 - 32 - read-write - 0 - 0xFFFFFFFF - - - ANACTRL_RULE - Analog Modules controller - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. - 0x110 - 32 - read-write - 0 - 0xFFFFFFFF - - - PMC_RULE - Power Management Controller - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SYSCTRL_RULE - System Controller - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. - 0x114 - 32 - read-write - 0 - 0xFFFFFFFF - - - CTIMER2_RULE - Standard counter/Timer 2 - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - CTIMER3_RULE - Standard counter/Timer 3 - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - CTIMER4_RULE - Standard counter/Timer 4 - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RTC_RULE - Real Time Counter - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - OSEVENT_RULE - OS Event Timer - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. - 0x118 - 32 - read-write - 0 - 0xFFFFFFFF - - - FLASH_CTRL_RULE - Flash Controller - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - PRINCE_RULE - Prince - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. - 0x11C - 32 - read-write - 0 - 0xFFFFFFFF - - - USBHPHY_RULE - USB High Speed Phy controller - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RNG_RULE - True Random Number Generator - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - PUF_RULE - PUF - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - PLU_RULE - Programmable Look-Up logic - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. - 0x120 - 32 - read-write - 0 - 0xFFFFFFFF - - - DMA0_RULE - DMA Controller - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - FS_USB_DEV_RULE - USB Full-speed device - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SCT_RULE - SCTimer - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - FLEXCOMM0_RULE - Flexcomm interface 0 - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - FLEXCOMM1_RULE - Flexcomm interface 1 - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. - 0x124 - 32 - read-write - 0 - 0xFFFFFFFF - - - FLEXCOMM2_RULE - Flexcomm interface 2 - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - FLEXCOMM3_RULE - Flexcomm interface 3 - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - FLEXCOMM4_RULE - Flexcomm interface 4 - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - MAILBOX_RULE - Inter CPU communication Mailbox - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - GPIO0_RULE - High Speed GPIO - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. - 0x130 - 32 - read-write - 0 - 0xFFFFFFFF - - - USB_HS_DEV_RULE - USB high Speed device registers - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - CRC_RULE - CRC engine - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - FLEXCOMM5_RULE - Flexcomm interface 5 - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - FLEXCOMM6_RULE - Flexcomm interface 6 - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. - 0x134 - 32 - read-write - 0 - 0xFFFFFFFF - - - FLEXCOMM7_RULE - Flexcomm interface 7 - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SDIO_RULE - SDMMC card interface - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - HS_LSPI_RULE - High Speed SPI - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_AHB_PORT10_SLAVE0_RULE - Security access rules for AHB peripherals. - 0x140 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADC_RULE - ADC - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - USB_FS_HOST_RULE - USB Full Speed Host registers. - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - USB_HS_HOST_RULE - USB High speed host registers - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - HASH_RULE - SHA-2 crypto registers - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - CASPER_RULE - RSA/ECC crypto accelerator - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - PQ_RULE - Power Quad (CPU0 processor hardware accelerator) - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - DMA1_RULE - DMA Controller (Secure) - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_AHB_PORT10_SLAVE1_RULE - Security access rules for AHB peripherals. - 0x144 - 32 - read-write - 0 - 0xFFFFFFFF - - - GPIO1_RULE - Secure High Speed GPIO - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - AHB_SEC_CTRL_RULE - AHB Secure Controller - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. - 0x150 - 32 - read-write - 0 - 0xFFFFFFFF - - - AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. - 0x160 - 32 - read-write - 0 - 0xFFFFFFFF - - - RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. - 0x170 - 32 - read-write - 0 - 0xFFFFFFFF - - - SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - 12 - 0x4 - sec_vio_addr[%s] - most recent security violation address for AHB port n - 0xE00 - 32 - read-only - 0 - 0xFFFFFFFF - - - SEC_VIO_ADDR - security violation address for AHB port - 0 - 32 - read-only - - - - - 12 - 0x4 - sec_vio_misc_info[%s] - most recent security violation miscellaneous information for AHB port n - 0xE80 - 32 - read-only - 0 - 0xFF3 - - - SEC_VIO_INFO_WRITE - security violation access read/write indicator. - 0 - 1 - read-only - - - READ - Read access. - 0 - - - WRITE - Write access. - 0x1 - - - - - SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator. - 1 - 1 - read-only - - - CODE - Code access. - 0 - - - DATA - Data access. - 0x1 - - - - - SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level - 4 - 4 - read-only - - - SEC_VIO_INFO_MASTER - security violation master number - 8 - 4 - read-only - - - VALUE_0 - CPU0 Code. - 0 - - - VALUE_1 - CPU0 System. - 0x1 - - - VALUE_2 - CPU1 Data. - 0x2 - - - VALUE_3 - CPU1 System. - 0x3 - - - VALUE_4 - USB-HS Device. - 0x4 - - - VALUE_5 - SDMA0. - 0x5 - - - VALUE_8 - SDIO. - 0x8 - - - VALUE_9 - PowerQuad. - 0x9 - - - VALUE_10 - HASH. - 0xA - - - VALUE_11 - USB-FS Host. - 0xB - - - VALUE_12 - SDMA1. - 0xC - - - - - - - SEC_VIO_INFO_VALID - security violation address/information registers valid flags - 0xF00 - 32 - read-write - 0 - 0x3FFFF - - - VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear. - 0 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear. - 1 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear. - 2 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear. - 3 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear. - 4 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear. - 5 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear. - 6 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear. - 7 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear. - 8 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear. - 9 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID10 - violation information valid flag for AHB port 10. Write 1 to clear. - 10 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID11 - violation information valid flag for AHB port 11. Write 1 to clear. - 11 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - - - SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. - 0xF80 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0 - 0 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1 - 1 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2 - 2 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3 - 3 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4 - 4 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5 - 5 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6 - 6 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7 - 7 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8 - 8 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9 - 9 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10 - 10 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11 - 11 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12 - 12 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13 - 13 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14 - 14 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15 - 15 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16 - 16 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17 - 17 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18 - 18 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19 - 19 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20 - 20 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21 - 21 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22 - 22 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23 - 23 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24 - 24 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25 - 25 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26 - 26 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27 - 27 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28 - 28 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29 - 29 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30 - 30 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31 - 31 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - - - SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. - 0xF84 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0 - 0 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1 - 1 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2 - 2 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3 - 3 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4 - 4 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5 - 5 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6 - 6 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7 - 7 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8 - 8 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9 - 9 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10 - 10 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11 - 11 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12 - 12 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13 - 13 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14 - 14 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15 - 15 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16 - 16 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17 - 17 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18 - 18 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19 - 19 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20 - 20 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21 - 21 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22 - 22 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23 - 23 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24 - 24 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25 - 25 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26 - 26 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27 - 27 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28 - 28 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29 - 29 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30 - 30 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31 - 31 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - - - SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 - 0xF90 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - SYS_IRQ - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts - 0 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SDMA0_IRQ - System DMA 0 (non-secure) interrupt. - 1 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_GLOBALINT0_IRQ - GPIO Group 0 interrupt. - 2 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_GLOBALINT1_IRQ - GPIO Group 1 interrupt. - 3 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_INT0_IRQ0 - Pin interrupt 0 or pattern match engine slice 0 interrupt. - 4 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_INT0_IRQ1 - Pin interrupt 1 or pattern match engine slice 1 interrupt. - 5 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_INT0_IRQ2 - Pin interrupt 2 or pattern match engine slice 2 interrupt. - 6 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_INT0_IRQ3 - Pin interrupt 3 or pattern match engine slice 3 interrupt. - 7 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - UTICK_IRQ - Micro Tick Timer interrupt. - 8 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - MRT_IRQ - Multi-Rate Timer interrupt. - 9 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - CTIMER0_IRQ - Standard counter/timer 0 interrupt. - 10 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - CTIMER1_IRQ - Standard counter/timer 1 interrupt. - 11 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SCT_IRQ - SCTimer/PWM interrupt. - 12 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - CTIMER3_IRQ - Standard counter/timer 3 interrupt. - 13 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM0_IRQ - Flexcomm 0 interrupt (USART, SPI, I2C, I2S). - 14 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM1_IRQ - Flexcomm 1 interrupt (USART, SPI, I2C, I2S). - 15 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM2_IRQ - Flexcomm 2 interrupt (USART, SPI, I2C, I2S). - 16 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM3_IRQ - Flexcomm 3 interrupt (USART, SPI, I2C, I2S). - 17 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM4_IRQ - Flexcomm 4 interrupt (USART, SPI, I2C, I2S). - 18 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM5_IRQ - Flexcomm 5 interrupt (USART, SPI, I2C, I2S). - 19 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM6_IRQ - Flexcomm 6 interrupt (USART, SPI, I2C, I2S). - 20 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM7_IRQ - Flexcomm 7 interrupt (USART, SPI, I2C, I2S). - 21 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - ADC_IRQ - General Purpose ADC interrupt. - 22 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED0 - Reserved. Read value is undefined, only zero should be written. - 23 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - ACMP_IRQ - Analog Comparator interrupt. - 24 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED1 - Reserved. Read value is undefined, only zero should be written. - 25 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED2 - Reserved. Read value is undefined, only zero should be written. - 26 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - USB0_NEEDCLK - USB Full Speed Controller Clock request interrupt. - 27 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - USB0_IRQ - USB Full Speed Controller interrupt. - 28 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RTC_IRQ - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ - 29 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED3 - Reserved. Read value is undefined, only zero should be written. - 30 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - MAILBOX_IRQ - Mailbox interrupt. - 31 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - - - SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 - 0xF94 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - GPIO_INT0_IRQ4 - Pin interrupt 4 or pattern match engine slice 4 interrupt. - 0 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_INT0_IRQ5 - Pin interrupt 5 or pattern match engine slice 5 interrupt. - 1 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_INT0_IRQ6 - Pin interrupt 6 or pattern match engine slice 6 interrupt. - 2 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_INT0_IRQ7 - Pin interrupt 7 or pattern match engine slice 7 interrupt. - 3 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - CTIMER2_IRQ - Standard counter/timer 2 interrupt. - 4 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - CTIMER4_IRQ - Standard counter/timer 4 interrupt. - 5 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - OS_EVENT_TIMER_IRQ - OS Event Timer and OS Event Timer Wakeup interrupts - 6 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED0 - Reserved. Read value is undefined, only zero should be written. - 7 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED1 - Reserved. Read value is undefined, only zero should be written. - 8 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED2 - Reserved. Read value is undefined, only zero should be written. - 9 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SDIO_IRQ - SDIO Controller interrupt. - 10 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED3 - Reserved. Read value is undefined, only zero should be written. - 11 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED4 - Reserved. Read value is undefined, only zero should be written. - 12 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED5 - Reserved. Read value is undefined, only zero should be written. - 13 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - USB1_PHY_IRQ - USB High Speed PHY Controller interrupt. - 14 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - USB1_IRQ - USB High Speed Controller interrupt. - 15 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - USB1_NEEDCLK - USB High Speed Controller Clock request interrupt. - 16 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SEC_HYPERVISOR_CALL_IRQ - Secure fault Hyper Visor call interrupt. - 17 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SEC_GPIO_INT0_IRQ0 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt. - 18 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SEC_GPIO_INT0_IRQ1 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt. - 19 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - PLU_IRQ - Programmable Look-Up Controller interrupt. - 20 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SEC_VIO_IRQ - Security Violation interrupt. - 21 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SHA_IRQ - HASH-AES interrupt. - 22 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - CASPER_IRQ - CASPER interrupt. - 23 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - PUFKEY_IRQ - PUF interrupt. - 24 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - PQ_IRQ - Power Quad interrupt. - 25 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SDMA1_IRQ - System DMA 1 (Secure) interrupt - 26 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - LSPI_HS_IRQ - High Speed SPI interrupt - 27 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - - - SEC_MASK_LOCK - Security General Purpose register access control. - 0xFBC - 32 - read-write - 0xAAA - 0xFFF - - - SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock. - 0 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock. - 2 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - SEC_CPU1_INT_MASK0_LOCK - SEC_CPU_INT_MASK0 register write-lock. - 8 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - SEC_CPU1_INT_MASK1_LOCK - SEC_CPU_INT_MASK1 register write-lock. - 10 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - - - MASTER_SEC_LEVEL - master secure level register - 0xFD0 - 32 - read-write - 0x80000000 - 0xFFFFFFFF - - - CPU1C - Micro-Cortex M33 (CPU1) Code bus. - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - CPU1S - Micro-Cortex M33 (CPU1) System bus. - 6 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - USBFSD - USB Full Speed Device. - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SDMA0 - System DMA 0. - 10 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SDIO - SDIO. - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - PQ - Power Quad. - 18 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - HASH - Hash. - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - USBFSH - USB Full speed Host. - 22 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SDMA1 - System DMA 1 security level. - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock. - 30 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - - - MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register - 0xFD4 - 32 - read-write - 0xBFFFFFFF - 0xFFFFFFFF - - - CPU1C - Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C) - 4 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - CPU1S - Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S) - 6 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) - 8 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) - 10 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - SDIO - SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO) - 16 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - PQ - Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ) - 18 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) - 20 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) - 22 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) - 24 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock. - 30 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - - - CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) - 0xFEC - 32 - read-write - 0x800002AA - 0xC00003FF - - - LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock. - 0 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock. - 2 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. - 4 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock. - 6 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock. - 8 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock. - 30 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - - - CPU1_LOCK_REG - Miscalleneous control signals for in micro-Cortex M33 (CPU1) - 0xFF0 - 32 - read-write - 0x8000000A - 0xC000000F - - - LOCK_NS_VTOR - micro-Cortex M33 (CPU1) VTOR_NS register write-lock. - 0 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - LOCK_NS_MPU - micro-Cortex M33 (CPU1) non-secure MPU register write-lock. - 2 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - CPU1_LOCK_REG_LOCK - CPU1_LOCK_REG write-lock. - 30 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - - - MISC_CTRL_DP_REG - secure control duplicate register - 0xFF8 - 32 - read-write - 0xAAAA - 0xFFFF - - - WRITE_LOCK - Write lock. - 0 - 2 - read-write - - - RESTRICTED - Restricted mode. - 0x1 - - - ACCESSIBLE - Secure control registers can be written. - 0x2 - - - - - ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. - 2 - 2 - read-write - - - ENABLE - Restricted mode. - 0x1 - - - DISABLE - Disable check. - 0x2 - - - - - ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. - 4 - 2 - read-write - - - ENABLE - Restricted mode. - 0x1 - - - DISABLE - Disable check. - 0x2 - - - - - ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. - 6 - 2 - read-write - - - ENABLE - Restricted mode. - 0x1 - - - DISABLE - Disable check. - 0x2 - - - - - DISABLE_VIOLATION_ABORT - Disable secure violation abort. - 8 - 2 - read-write - - - DISABLE - Disable abort fort secure checker. - 0x1 - - - ENABLE - Enable abort fort secure checker. - 0x2 - - - - - DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. - 10 - 2 - read-write - - - TIER_MODE - Simple master in tier mode. - 0x1 - - - STRICT_MODE - Simple master in strict mode. - 0x2 - - - - - DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. - 12 - 2 - read-write - - - TIER_MODE - Smart master in tier mode. - 0x1 - - - STRICT_MODE - Smart master in strict mode. - 0x2 - - - - - IDAU_ALL_NS - Disable IDAU. - 14 - 2 - read-write - - - DISABLE - IDAU is disable. - 0x1 - - - ENABLE - IDAU is enabled. - 0x2 - - - - - - - MISC_CTRL_REG - secure control register - 0xFFC - 32 - read-write - 0xAAAA - 0xFFFF - - - WRITE_LOCK - Write lock. - 0 - 2 - read-write - - - RESTRICTED - Restricted mode. - 0x1 - - - ACCESSIBLE - Secure control registers can be written. - 0x2 - - - - - ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. - 2 - 2 - read-write - - - ENABLE - Enabled (restricted mode) - 0x1 - - - DISABLE - Disable check. - 0x2 - - - - - ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. - 4 - 2 - read-write - - - ENABLE - Enabled (restricted mode) - 0x1 - - - DISABLE - Disable check. - 0x2 - - - - - ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. - 6 - 2 - read-write - - - ENABLE - Enabled (restricted mode) - 0x1 - - - DISABLE - Disable check. - 0x2 - - - - - DISABLE_VIOLATION_ABORT - Disable secure violation abort. - 8 - 2 - read-write - - - DISABLE - Disable abort fort secure checker. - 0x1 - - - ENABLE - Enable abort fort secure checker. - 0x2 - - - - - DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. - 10 - 2 - read-write - - - TIER_MODE - Simple master in tier mode. - 0x1 - - - STRICT_MODE - Simple master in strict mode. - 0x2 - - - - - DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. - 12 - 2 - read-write - - - TIER_MODE - Smart master in tier mode. - 0x1 - - - STRICT_MODE - Smart master in strict mode. - 0x2 - - - - - IDAU_ALL_NS - Disable IDAU. - 14 - 2 - read-write - - - DISABLE - IDAU is disable. - 0x1 - - - ENABLE - IDAU is enabled. - 0x2 - - - - - - - - - SCnSCB - no description available - SCNSCB - 0xE000E000 - - 0 - 0x10 - registers - - - - CPPWR - Coprocessor Power Control Register - 0xC - 32 - read-write - 0 - 0 - - - SU0 - State UNKNOWN 0. - 0 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS0 - State UNKNOWN Secure only 0. - 1 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU0 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU0 field is only accessible from the Secure state. - 0x1 - - - - - SU1 - State UNKNOWN 1. - 2 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS1 - State UNKNOWN Secure only 1. - 3 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU7 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU7 field is only accessible from the Secure state. - 0x1 - - - - - SU2 - State UNKNOWN 2. - 4 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS2 - State UNKNOWN Secure only 2. - 5 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU2 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU2 field is only accessible from the Secure state. - 0x1 - - - - - SU3 - State UNKNOWN 3. - 6 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS3 - State UNKNOWN Secure only 3. - 7 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU3 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU3 field is only accessible from the Secure state. - 0x1 - - - - - SU4 - State UNKNOWN 4. - 8 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS4 - State UNKNOWN Secure only 4. - 9 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU4 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU4 field is only accessible from the Secure state. - 0x1 - - - - - SU5 - State UNKNOWN 5. - 10 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS5 - State UNKNOWN Secure only 5. - 11 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU5 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU5 field is only accessible from the Secure state. - 0x1 - - - - - SU6 - State UNKNOWN 6. - 12 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS6 - State UNKNOWN Secure only 6. - 13 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU6 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU6 field is only accessible from the Secure state. - 0x1 - - - - - SU7 - State UNKNOWN 7. - 14 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS7 - State UNKNOWN Secure only 7. - 15 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU7 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU7 field is only accessible from the Secure state. - 0x1 - - - - - SU10 - State UNKNOWN 10. - 20 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The floating-point state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The floating-point state is permitted to become UNKNOWN - 0x1 - - - - - SUS10 - State UNKNOWN Secure only 10. - 21 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU10 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU10 field is only accessible from the Secure state. - 0x1 - - - - - SU11 - State UNKNOWN 11. - 22 - 1 - read-write - - - SUS11 - State UNKNOWN Secure only 11. - 23 - 1 - read-write - - - - - - - NVIC - no description available - NVIC - 0xE000E100 - - 0 - 0xE04 - registers - - - - 16 - 0x4 - ISER[%s] - Interrupt Set Enable Register - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - SETENA0 - Interrupt set-enable bits. - 0 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA1 - Interrupt set-enable bits. - 1 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA2 - Interrupt set-enable bits. - 2 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA3 - Interrupt set-enable bits. - 3 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA4 - Interrupt set-enable bits. - 4 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA5 - Interrupt set-enable bits. - 5 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA6 - Interrupt set-enable bits. - 6 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA7 - Interrupt set-enable bits. - 7 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA8 - Interrupt set-enable bits. - 8 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA9 - Interrupt set-enable bits. - 9 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA10 - Interrupt set-enable bits. - 10 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA11 - Interrupt set-enable bits. - 11 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA12 - Interrupt set-enable bits. - 12 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA13 - Interrupt set-enable bits. - 13 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA14 - Interrupt set-enable bits. - 14 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA15 - Interrupt set-enable bits. - 15 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA16 - Interrupt set-enable bits. - 16 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA17 - Interrupt set-enable bits. - 17 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA18 - Interrupt set-enable bits. - 18 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA19 - Interrupt set-enable bits. - 19 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA20 - Interrupt set-enable bits. - 20 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA21 - Interrupt set-enable bits. - 21 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA22 - Interrupt set-enable bits. - 22 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA23 - Interrupt set-enable bits. - 23 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA24 - Interrupt set-enable bits. - 24 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA25 - Interrupt set-enable bits. - 25 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA26 - Interrupt set-enable bits. - 26 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA27 - Interrupt set-enable bits. - 27 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA28 - Interrupt set-enable bits. - 28 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA29 - Interrupt set-enable bits. - 29 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA30 - Interrupt set-enable bits. - 30 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA31 - Interrupt set-enable bits. - 31 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - - - 16 - 0x4 - ICER[%s] - Interrupt Clear Enable Register - 0x80 - 32 - read-write - 0 - 0xFFFFFFFF - - - CLRENA0 - Interrupt clear-enable bits. - 0 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA1 - Interrupt clear-enable bits. - 1 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA2 - Interrupt clear-enable bits. - 2 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA3 - Interrupt clear-enable bits. - 3 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA4 - Interrupt clear-enable bits. - 4 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA5 - Interrupt clear-enable bits. - 5 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA6 - Interrupt clear-enable bits. - 6 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA7 - Interrupt clear-enable bits. - 7 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA8 - Interrupt clear-enable bits. - 8 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA9 - Interrupt clear-enable bits. - 9 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA10 - Interrupt clear-enable bits. - 10 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA11 - Interrupt clear-enable bits. - 11 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA12 - Interrupt clear-enable bits. - 12 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA13 - Interrupt clear-enable bits. - 13 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA14 - Interrupt clear-enable bits. - 14 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA15 - Interrupt clear-enable bits. - 15 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA16 - Interrupt clear-enable bits. - 16 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA17 - Interrupt clear-enable bits. - 17 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA18 - Interrupt clear-enable bits. - 18 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA19 - Interrupt clear-enable bits. - 19 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA20 - Interrupt clear-enable bits. - 20 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA21 - Interrupt clear-enable bits. - 21 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA22 - Interrupt clear-enable bits. - 22 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA23 - Interrupt clear-enable bits. - 23 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA24 - Interrupt clear-enable bits. - 24 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA25 - Interrupt clear-enable bits. - 25 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA26 - Interrupt clear-enable bits. - 26 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA27 - Interrupt clear-enable bits. - 27 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA28 - Interrupt clear-enable bits. - 28 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA29 - Interrupt clear-enable bits. - 29 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA30 - Interrupt clear-enable bits. - 30 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA31 - Interrupt clear-enable bits. - 31 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - - - 16 - 0x4 - ISPR[%s] - Interrupt Set Pending Register - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - SETPEND0 - Interrupt set-pending bits. - 0 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND1 - Interrupt set-pending bits. - 1 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND2 - Interrupt set-pending bits. - 2 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND3 - Interrupt set-pending bits. - 3 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND4 - Interrupt set-pending bits. - 4 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND5 - Interrupt set-pending bits. - 5 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND6 - Interrupt set-pending bits. - 6 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND7 - Interrupt set-pending bits. - 7 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND8 - Interrupt set-pending bits. - 8 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND9 - Interrupt set-pending bits. - 9 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND10 - Interrupt set-pending bits. - 10 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND11 - Interrupt set-pending bits. - 11 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND12 - Interrupt set-pending bits. - 12 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND13 - Interrupt set-pending bits. - 13 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND14 - Interrupt set-pending bits. - 14 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND15 - Interrupt set-pending bits. - 15 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND16 - Interrupt set-pending bits. - 16 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND17 - Interrupt set-pending bits. - 17 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND18 - Interrupt set-pending bits. - 18 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND19 - Interrupt set-pending bits. - 19 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND20 - Interrupt set-pending bits. - 20 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND21 - Interrupt set-pending bits. - 21 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND22 - Interrupt set-pending bits. - 22 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND23 - Interrupt set-pending bits. - 23 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND24 - Interrupt set-pending bits. - 24 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND25 - Interrupt set-pending bits. - 25 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND26 - Interrupt set-pending bits. - 26 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND27 - Interrupt set-pending bits. - 27 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND28 - Interrupt set-pending bits. - 28 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND29 - Interrupt set-pending bits. - 29 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND30 - Interrupt set-pending bits. - 30 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND31 - Interrupt set-pending bits. - 31 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - - - 16 - 0x4 - ICPR[%s] - Interrupt Clear Pending Register - 0x180 - 32 - read-write - 0 - 0xFFFFFFFF - - - CLRPEND0 - Interrupt clear-pending bits. - 0 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND1 - Interrupt clear-pending bits. - 1 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND2 - Interrupt clear-pending bits. - 2 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND3 - Interrupt clear-pending bits. - 3 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND4 - Interrupt clear-pending bits. - 4 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND5 - Interrupt clear-pending bits. - 5 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND6 - Interrupt clear-pending bits. - 6 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND7 - Interrupt clear-pending bits. - 7 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND8 - Interrupt clear-pending bits. - 8 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND9 - Interrupt clear-pending bits. - 9 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND10 - Interrupt clear-pending bits. - 10 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND11 - Interrupt clear-pending bits. - 11 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND12 - Interrupt clear-pending bits. - 12 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND13 - Interrupt clear-pending bits. - 13 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND14 - Interrupt clear-pending bits. - 14 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND15 - Interrupt clear-pending bits. - 15 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND16 - Interrupt clear-pending bits. - 16 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND17 - Interrupt clear-pending bits. - 17 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND18 - Interrupt clear-pending bits. - 18 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND19 - Interrupt clear-pending bits. - 19 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND20 - Interrupt clear-pending bits. - 20 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND21 - Interrupt clear-pending bits. - 21 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND22 - Interrupt clear-pending bits. - 22 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND23 - Interrupt clear-pending bits. - 23 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND24 - Interrupt clear-pending bits. - 24 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND25 - Interrupt clear-pending bits. - 25 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND26 - Interrupt clear-pending bits. - 26 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND27 - Interrupt clear-pending bits. - 27 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND28 - Interrupt clear-pending bits. - 28 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND29 - Interrupt clear-pending bits. - 29 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND30 - Interrupt clear-pending bits. - 30 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND31 - Interrupt clear-pending bits. - 31 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - - - 16 - 0x4 - IABR[%s] - Interrupt Active Bit Register - 0x200 - 32 - read-write - 0 - 0 - - - ACTIVE0 - Active state bits. - 0 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE1 - Active state bits. - 1 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE2 - Active state bits. - 2 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE3 - Active state bits. - 3 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE4 - Active state bits. - 4 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE5 - Active state bits. - 5 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE6 - Active state bits. - 6 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE7 - Active state bits. - 7 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE8 - Active state bits. - 8 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE9 - Active state bits. - 9 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE10 - Active state bits. - 10 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE11 - Active state bits. - 11 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE12 - Active state bits. - 12 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE13 - Active state bits. - 13 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE14 - Active state bits. - 14 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE15 - Active state bits. - 15 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE16 - Active state bits. - 16 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE17 - Active state bits. - 17 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE18 - Active state bits. - 18 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE19 - Active state bits. - 19 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE20 - Active state bits. - 20 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE21 - Active state bits. - 21 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE22 - Active state bits. - 22 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE23 - Active state bits. - 23 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE24 - Active state bits. - 24 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE25 - Active state bits. - 25 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE26 - Active state bits. - 26 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE27 - Active state bits. - 27 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE28 - Active state bits. - 28 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE29 - Active state bits. - 29 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE30 - Active state bits. - 30 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE31 - Active state bits. - 31 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - - - 16 - 0x4 - ITNS[%s] - Interrupt Target Non-secure Register - 0x280 - 32 - read-write - 0 - 0 - - - INTS0 - Interrupt Targets Non-secure bits. - 0 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS1 - Interrupt Targets Non-secure bits. - 1 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS2 - Interrupt Targets Non-secure bits. - 2 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS3 - Interrupt Targets Non-secure bits. - 3 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS4 - Interrupt Targets Non-secure bits. - 4 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS5 - Interrupt Targets Non-secure bits. - 5 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS6 - Interrupt Targets Non-secure bits. - 6 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS7 - Interrupt Targets Non-secure bits. - 7 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS8 - Interrupt Targets Non-secure bits. - 8 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS9 - Interrupt Targets Non-secure bits. - 9 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS10 - Interrupt Targets Non-secure bits. - 10 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS11 - Interrupt Targets Non-secure bits. - 11 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS12 - Interrupt Targets Non-secure bits. - 12 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS13 - Interrupt Targets Non-secure bits. - 13 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS14 - Interrupt Targets Non-secure bits. - 14 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS15 - Interrupt Targets Non-secure bits. - 15 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS16 - Interrupt Targets Non-secure bits. - 16 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS17 - Interrupt Targets Non-secure bits. - 17 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS18 - Interrupt Targets Non-secure bits. - 18 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS19 - Interrupt Targets Non-secure bits. - 19 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS20 - Interrupt Targets Non-secure bits. - 20 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS21 - Interrupt Targets Non-secure bits. - 21 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS22 - Interrupt Targets Non-secure bits. - 22 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS23 - Interrupt Targets Non-secure bits. - 23 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS24 - Interrupt Targets Non-secure bits. - 24 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS25 - Interrupt Targets Non-secure bits. - 25 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS26 - Interrupt Targets Non-secure bits. - 26 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS27 - Interrupt Targets Non-secure bits. - 27 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS28 - Interrupt Targets Non-secure bits. - 28 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS29 - Interrupt Targets Non-secure bits. - 29 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS30 - Interrupt Targets Non-secure bits. - 30 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS31 - Interrupt Targets Non-secure bits. - 31 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - - - 120 - 0x4 - IPR[%s] - Interrupt Priority Register - 0x300 - 32 - read-write - 0 - 0 - - - PRI_0 - no description available - 0 - 8 - read-write - - - PRI_1 - no description available - 8 - 8 - read-write - - - PRI_2 - no description available - 16 - 8 - read-write - - - PRI_3 - no description available - 24 - 8 - read-write - - - - - STIR - Software Trigger Interrupt Register - 0xE00 - 32 - write-only - 0 - 0xFFFFFFFF - - - INTID - Interrupt ID of the interrupt to trigger, in the range 0-479. - 0 - 9 - write-only - - - - - - - SCB - no description available - SCB - 0xE000ED00 - - 0 - 0x90 - registers - - - - AIRCR - Application Interrupt and Reset Control Register - 0xC - 32 - read-write - 0xFA050000 - 0xFFFFFFFF - - - VECTCLRACTIVE - Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is UNPREDICTABLE. This bit is not banked between Security states. - 1 - 1 - write-only - - - SYSRESETREQ - System reset request. This bit allows software or a debugger to request a system reset. This bit is not banked between Security states. RW if SYSRESETREQS is 0. When SYSRESETREQS is set to 1, from Non-secure state this bit acts as RAZ/WI. - 2 - 1 - read-write - - - NO_REQUEST - Do not request a system reset. - 0 - - - REQUEST_RESET - Request a system reset. - 0x1 - - - - - SYSRESETREQS - System reset request, Secure state only. The value of this bit defines whether the SYSRESETREQ bit is functional for Non-secure use. This bit is not banked between Security states. RW from Secure State and RAZ/WI from Non-secure state. - 3 - 1 - read-write - - - SECURE_AND_NON_SECURE - SYSRESETREQ functionality is available to both Security states. - 0 - - - SECURE_ONLY - SYSRESETREQ functionality is only available to Secure state. - 0x1 - - - - - PRIGROUP - Interrupt priority grouping field. This field determines the split of group priority from subpriority. This bit is banked between Security states - 8 - 3 - read-write - - - BFHFNMINS - BusFault, HardFault, and NMI Non-secure enable. The value of this bit defines whether BusFault and NMI exceptions are Non-secure, and whether exceptions target the Non-secure HardFault exception. This bit is not banked between Security states. RW from Secure-state and RO from Non-secure state. - 13 - 1 - read-write - - - SECURE - BusFault, HardFault, and NMI are Secure. - 0 - - - NON_SECURE - BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault. - 0x1 - - - - - PRIS - Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. This bit is not banked between Security states. RW from Secure state and RAZ/WI from Non-secure state. - 14 - 1 - read-write - - - SAME_PRIORITY - Priority ranges of Secure and Non-secure exceptions are identical - 0 - - - SECURE_PRIORITIZED - Non-secure exceptions are de-prioritized - 0x1 - - - - - ENDIANNESS - Data endianness bit. This bit is not banked between Security states. - 15 - 1 - read-only - - - LITTLE_ENDIAN - Little-endian. - 0 - - - BIG_ENDIAN - Big-endian - 0x1 - - - - - VECTKEY - Register key: Reads as 0xFA05. On writes, write 0x5FA to VECTKEY, otherwise the write is ignored. This Field is not banked between Security states. - 16 - 16 - read-only - - - - - SCR - The SCR controls features of entry to and exit from low-power state. - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - SLEEPONEXIT - Indicates sleep-on-exit when returning from Handler mode to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. This bit is banked between Security states. - 1 - 1 - read-write - - - NOT_SLEEP - Do not sleep when returning to Thread mode. - 0 - - - SLEEP - Enter sleep, or deep sleep, on return from an ISR - 0x1 - - - - - SLEEPDEEP - Controls whether the processor uses sleep or deep sleep as its low-power mode. This bit is not banked between Security states. - 2 - 1 - read-write - - - SLEEP - Sleep. - 0 - - - DEEP_SLEEP - Deep sleep. - 0x1 - - - - - SLEEPDEEPS - Controls whether the SLEEPDEEP bit is only accessible from the Secure state. This bit in only accessible from the Secure state, and behaves as RAZ/WI when accessed from the Nonsecure state. This bit is not banked between Security states. - 3 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SLEEPDEEP bit is accessible from both Security states. - 0 - - - SECURE_ONLY - The SLEEPDEEP bit behaves as RAZ/WI when accessed from the Non-secure state. - 0x1 - - - - - SEVONPEND - Send Event on Pending bit. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event. This bit is banked between Security states. - 4 - 1 - read-write - - - EXCLUDE_DISABLED_INTERRUPTS - Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. - 0 - - - INCLUDE_DISABLED_INTERRUPTS - Enabled events and all interrupts, including disabled interrupts, can wakeup the processor - 0x1 - - - - - - - SHCSR - System Handler Control and State Register - 0x24 - 32 - read-write - 0 - 0xFFFFFFFF - - - MEMFAULTACT - MemManage exception active. - 0 - 1 - read-write - - - NOT_ACTIVE - MemManage exception is not active. - 0 - - - ACTIVE - MemManage exception is active. - 0x1 - - - - - BUSFAULTACT - BusFault exception active. - 1 - 1 - read-write - - - NOT_ACTIVE - BusFault exception is not active. - 0 - - - ACTIVE - BusFault exception is active. - 0x1 - - - - - HARDFAULTACT - HardFault exception active. - 2 - 1 - read-write - - - NOT_ACTIVE - HardFault exception is not active. - 0 - - - ACTIVE - HardFault exception is active. - 0x1 - - - - - USGFAULTACT - UsageFault exception active. - 3 - 1 - read-write - - - NOT_ACTIVE - UsageFault exception is not active. - 0 - - - ACTIVE - UsageFault exception is active. - 0x1 - - - - - SECUREFAULTACT - SecureFault exception active - 4 - 1 - read-write - - - NOT_ACTIVE - SecureFault exception is not active. - 0 - - - ACTIVE - SecureFault exception is active. - 0x1 - - - - - NMIACT - NMI exception active. - 5 - 1 - read-write - - - NOT_ACTIVE - NMI exception is not active. - 0 - - - ACTIVE - NMI exception is active. - 0x1 - - - - - SVCALLACT - SVCall active. - 7 - 1 - read-write - - - NOT_ACTIVE - SVCall exception is not active. - 0 - - - ACTIVE - SVCall exception is active. - 0x1 - - - - - MONITORACT - Debug monitor active. - 8 - 1 - read-write - - - NOT_ACTIVE - Debug monitor exception is not active. - 0 - - - ACTIVE - Debug monitor exception is active. - 0x1 - - - - - PENDSVACT - PendSV exception active. - 10 - 1 - read-write - - - NOT_ACTIVE - PendSV exception is not active. - 0 - - - ACTIVE - PendSV exception is active. - 0x1 - - - - - SYSTICKACT - SysTick exception active. - 11 - 1 - read-write - - - NOT_ACTIVE - SysTick exception is not active. - 0 - - - ACTIVE - SysTick exception is active. - 0x1 - - - - - USGFAULTPENDED - UsageFault exception pending. - 12 - 1 - read-write - - - NOT_PENDING - UsageFault exception is not pending. - 0 - - - PENDING - UsageFault exception is pending. - 0x1 - - - - - MEMFAULTPENDED - MemManage exception pending. - 13 - 1 - read-write - - - NOT_PENDING - MemManage exception is not pending. - 0 - - - PENDING - MemManage exception is pending. - 0x1 - - - - - BUSFAULTPENDED - BusFault exception pending. - 14 - 1 - read-write - - - NOT_PENDING - BusFault exception is pending. - 0 - - - PENDING - BusFault exception is not pending. - 0x1 - - - - - SVCALLPENDED - SVCall pending. - 15 - 1 - read-write - - - NOT_PENDING - SVCall exception is not pending. - 0 - - - PENDING - SVCall exception is pending. - 0x1 - - - - - MEMFAULTENA - MemManage enable. - 16 - 1 - read-write - - - DISABLED - MemManage exception is disabled. - 0 - - - ENABLED - MemManage exception is enabled. - 0x1 - - - - - BUSFAULTENA - BusFault enable. - 17 - 1 - read-write - - - DISABLED - BusFault is disabled. - 0 - - - ENABLED - BusFault is enabled. - 0x1 - - - - - USGFAULTENA - UsageFault enable. - 18 - 1 - read-write - - - DISABLED - UsageFault is disabled. - 0 - - - ENABLED - UsageFault is enabled. - 0x1 - - - - - SECUREFAULTENA - SecureFault exception enable. - 19 - 1 - read-write - - - DISABLED - SecureFault exception is disabled. - 0 - - - ENABLED - SecureFault exception is enabled. - 0x1 - - - - - SECUREFAULTPENDED - SecureFault exception pended state bit. - 20 - 1 - read-write - - - DISABLED - SecureFault exception modification is disabled. - 0 - - - ENABLED - SecureFault exception modification is enabled. - 0x1 - - - - - HARDFAULTPENDED - HardFault exception pended state - 21 - 1 - read-write - - - DISABLED - HardFault exception modification is disabled. - 0 - - - ENABLED - HardFault exception modification is enabled. - 0x1 - - - - - - - NSACR - Non-secure Access Control Register - 0x8C - 32 - read-write - 0 - 0 - - - CP0 - CP0 access. - 0 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP1 - CP1 access. - 1 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP2 - CP2 access. - 2 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP3 - CP3 access. - 3 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP4 - CP4 access. - 4 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP5 - CP5 access. - 5 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP6 - CP6 access. - 6 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP7 - CP7 access. - 7 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP10 - CP10 access. - 10 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to the Floating-point Extension generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to the Floatingpoint Extension permitted. - 0x1 - - - - - CP11 - CP11 access. - 11 - 1 - read-write - - - - - - - SAU - no description available - SAU - 0xE000EDD0 - - 0 - 0xEC - registers - - - - CTRL - Security Attribution Unit Control Register - 0xD0 - 32 - read-write - 0 - 0xFFFFFFFF - - - ENABLE - Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region. - 0 - 1 - read-write - - - DISABLED - The SAU is disabled. - 0 - - - ENABLED - The SAU is enabled. - 0x1 - - - - - ALLNS - All Non-secure. - 1 - 1 - read-write - - - SECURED_MEMORY - Memory is marked as Secure and is not Non-secure callable. - 0 - - - NON_SECURED_MEMORY - Memory is marked as Non-secure. - 0x1 - - - - - - - TYPE - Security Attribution Unit Type Register - 0xD4 - 32 - read-write - 0 - 0xFFFFFFFF - - - SREGION - SAU regions. The number of implemented SAU regions. - 0 - 8 - read-write - - - - - RNR - Security Attribution Unit Region Number Register - 0xD8 - 32 - read-write - 0 - 0 - - - REGION - Region number. - 0 - 8 - read-write - - - - - RBAR - Security Attribution Unit Region Base Address Register - 0xDC - 32 - read-write - 0 - 0 - - - BADDR - Base address. Holds bits[31:5] of the base address for the selected SAU region. Bits[4:0] of the base address are defined as 0x00. - 5 - 27 - read-write - - - - - RLAR - Security Attribution Unit Region Limit Address Register - 0xE0 - 32 - read-write - 0 - 0 - - - ENABLE - Enable. SAU region enable. - 0 - 1 - read-write - - - ENABLED - SAU region is enabled. - 0 - - - DISABLED - SAU region is disabled. - 0x1 - - - - - NSC - Non-secure callable. Controls whether Non-secure state is permitted to execute an SG instruction from this region. - 1 - 1 - read-write - - - NOT_NON_SECURE_CALLABLE - Region is not Non-secure callable. - 0 - - - NON_SECURE_CALLABLE - Region is Non-secure callable. - 0x1 - - - - - LADDR - Limit address. Holds bits[31:5] of the limit address for the selected SAU region. Bits[4:0] of the limit address are defined as 0x1F. - 5 - 27 - read-write - - - - - SFSR - Secure Fault Status Register - 0xE4 - 32 - read-write - 0 - 0xFFFFFFFF - - - INVEP - Invalid entry point. - 0 - 1 - read-write - - - NO_ERROR - Error has not occurred. - 0 - - - ERROR - Error has occurred. - 0x1 - - - - - INVIS - Invalid integrity signature flag. - 1 - 1 - read-write - - - NO_ERROR - Error has not occurred. - 0 - - - ERROR - Error has occurred. - 0x1 - - - - - INVER - Invalid exception return flag. - 2 - 1 - read-write - - - NO_ERROR - Error has not occurred. - 0 - - - ERROR - Error has occurred. - 0x1 - - - - - AUVIOL - Attribution unit violation flag. - 3 - 1 - read-write - - - NO_ERROR - Error has not occurred. - 0 - - - ERROR - Error has occurred. - 0x1 - - - - - INVTRAN - Invalid transition flag. - 4 - 1 - read-write - - - NO_ERROR - Error has not occurred. - 0 - - - ERROR - Error has occurred. - 0x1 - - - - - LSPERR - Lazy state preservation error flag. - 5 - 1 - read-write - - - NO_ERROR - Error has not occurred. - 0 - - - ERROR - Error has occurred. - 0x1 - - - - - SFARVALID - Secure fault address valid. - 6 - 1 - read-write - - - NOT_VALID - SFAR content not valid. - 0 - - - VALID - SFAR content valid. - 0x1 - - - - - LSERR - Lazy state error flag. - 7 - 1 - read-write - - - NO_ERROR - Error has not occurred - 0 - - - ERROR - Error has occurred. - 0x1 - - - - - - - SFAR - Secure Fault Address Register - 0xE8 - 32 - read-write - 0 - 0 - - - ADDRESS - When the SFARVALID bit of the SFSR is set to 1, this field holds the address of an access that caused an SAU violation. - 0 - 32 - read-write - - - - - - - \ No newline at end of file diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0_features.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0_features.h deleted file mode 100644 index 926c9857a0b..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0_features.h +++ /dev/null @@ -1,447 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.1, 2019-05-16 -** Build: b220303 -** -** Abstract: -** Chip specific module features. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** - rev. 1.1 (2019-05-16) -** Initial A1 version based on v1.3UM -** -** ################################################################### -*/ - -#ifndef _LPC55S69_cm33_core0_FEATURES_H_ -#define _LPC55S69_cm33_core0_FEATURES_H_ - -/* SOC module features */ - -/* @brief CASPER availability on the SoC. */ -#define FSL_FEATURE_SOC_CASPER_COUNT (1) -/* @brief CRC availability on the SoC. */ -#define FSL_FEATURE_SOC_CRC_COUNT (1) -/* @brief CTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_CTIMER_COUNT (5) -/* @brief DMA availability on the SoC. */ -#define FSL_FEATURE_SOC_DMA_COUNT (2) -/* @brief FLASH availability on the SoC. */ -#define FSL_FEATURE_SOC_FLASH_COUNT (1) -/* @brief FLEXCOMM availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) -/* @brief GINT availability on the SoC. */ -#define FSL_FEATURE_SOC_GINT_COUNT (2) -/* @brief GPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_GPIO_COUNT (1) -/* @brief SECGPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_SECGPIO_COUNT (1) -/* @brief HASHCRYPT availability on the SoC. */ -#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) -/* @brief I2C availability on the SoC. */ -#define FSL_FEATURE_SOC_I2C_COUNT (8) -/* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (8) -/* @brief INPUTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) -/* @brief IOCON availability on the SoC. */ -#define FSL_FEATURE_SOC_IOCON_COUNT (1) -/* @brief LPADC availability on the SoC. */ -#define FSL_FEATURE_SOC_LPADC_COUNT (1) -/* @brief MAILBOX availability on the SoC. */ -#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) -/* @brief MRT availability on the SoC. */ -#define FSL_FEATURE_SOC_MRT_COUNT (1) -/* @brief OSTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) -/* @brief PINT availability on the SoC. */ -#define FSL_FEATURE_SOC_PINT_COUNT (1) -/* @brief SECPINT availability on the SoC. */ -#define FSL_FEATURE_SOC_SECPINT_COUNT (1) -/* @brief PMC availability on the SoC. */ -#define FSL_FEATURE_SOC_PMC_COUNT (1) -/* @brief POWERQUAD availability on the SoC. */ -#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) -/* @brief PUF availability on the SoC. */ -#define FSL_FEATURE_SOC_PUF_COUNT (1) -/* @brief LPC_RNG1 availability on the SoC. */ -#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) -/* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (1) -/* @brief SCT availability on the SoC. */ -#define FSL_FEATURE_SOC_SCT_COUNT (1) -/* @brief SDIF availability on the SoC. */ -#define FSL_FEATURE_SOC_SDIF_COUNT (1) -/* @brief SPI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPI_COUNT (9) -/* @brief SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCON_COUNT (1) -/* @brief SYSCTL1 availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) -/* @brief USART availability on the SoC. */ -#define FSL_FEATURE_SOC_USART_COUNT (8) -/* @brief USB availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_COUNT (1) -/* @brief USBFSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBFSH_COUNT (1) -/* @brief USBHSD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSD_COUNT (1) -/* @brief USBHSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSH_COUNT (1) -/* @brief USBPHY availability on the SoC. */ -#define FSL_FEATURE_SOC_USBPHY_COUNT (1) -/* @brief UTICK availability on the SoC. */ -#define FSL_FEATURE_SOC_UTICK_COUNT (1) -/* @brief WWDT availability on the SoC. */ -#define FSL_FEATURE_SOC_WWDT_COUNT (1) - -/* LPADC module features */ - -/* @brief FIFO availability on the SoC. */ -#define FSL_FEATURE_LPADC_FIFO_COUNT (2) -/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) -/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) -/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) -/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) -/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) -/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) -/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) -/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) -/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) -/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) -/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) -/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) -/* @brief Has calibration (bitfield CFG[CALOFS]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) -/* @brief Has offset trim (register OFSTRIM). */ -#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) -/* @brief Has Trigger status register. */ -#define FSL_FEATURE_LPADC_HAS_TSTAT (1) -/* @brief Has power select (bitfield CFG[PWRSEL]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) -/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) -/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) -/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) -/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) -/* @brief Conversion averaged bitfiled width. */ -#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) -/* @brief Has internal temperature sensor. */ -#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) -/* @brief Temperature sensor parameter A (slope). */ -#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (744.6f) -/* @brief Temperature sensor parameter B (offset). */ -#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (313.7f) -/* @brief Temperature sensor parameter Alpha. */ -#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.5f) -/* @brief the buffer size of temperature sensor. */ -#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U) - -/* ANALOGCTRL module features */ - -/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ -#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) -/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ -#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (0) -/* @brief Has auxiliary bias(register AUX_BIAS). */ -#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1) - -/* CASPER module features */ - -/* @brief Base address of the CASPER dedicated RAM */ -#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) -/* @brief SW interleaving of the CASPER dedicated RAM */ -#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1) -/* @brief CASPER dedicated RAM offset */ -#define FSL_FEATURE_CASPER_RAM_OFFSET (0xE) - -/* CTIMER module features */ - -/* @brief CTIMER has no capture channel. */ -#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) -/* @brief CTIMER has no capture 2 interrupt. */ -#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) -/* @brief CTIMER capture 3 interrupt. */ -#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) -/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ -#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) -/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ -#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) - -/* DMA module features */ - -/* @brief Number of channels */ -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23) -/* @brief Align size of DMA descriptor */ -#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) -/* @brief DMA head link descriptor table align size */ -#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) - -/* FLEXCOMM module features */ - -/* @brief FLEXCOMM0 USART INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) -/* @brief FLEXCOMM0 SPI INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) -/* @brief FLEXCOMM0 I2C INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) -/* @brief FLEXCOMM0 I2S INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) -/* @brief FLEXCOMM1 USART INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) -/* @brief FLEXCOMM1 SPI INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) -/* @brief FLEXCOMM1 I2C INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) -/* @brief FLEXCOMM1 I2S INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) -/* @brief FLEXCOMM2 USART INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) -/* @brief FLEXCOMM2 SPI INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) -/* @brief FLEXCOMM2 I2C INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) -/* @brief FLEXCOMM2 I2S INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) -/* @brief FLEXCOMM3 USART INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) -/* @brief FLEXCOMM3 SPI INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) -/* @brief FLEXCOMM3 I2C INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) -/* @brief FLEXCOMM3 I2S INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) -/* @brief FLEXCOMM4 USART INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) -/* @brief FLEXCOMM4 SPI INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) -/* @brief FLEXCOMM4 I2C INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) -/* @brief FLEXCOMM4 I2S INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) -/* @brief FLEXCOMM5 USART INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) -/* @brief FLEXCOMM5 SPI INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) -/* @brief FLEXCOMM5 I2C INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) -/* @brief FLEXCOMM5 I2S INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) -/* @brief FLEXCOMM6 USART INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) -/* @brief FLEXCOMM6 SPI INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) -/* @brief FLEXCOMM6 I2C INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) -/* @brief FLEXCOMM6 I2S INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) -/* @brief FLEXCOMM7 USART INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) -/* @brief FLEXCOMM7 SPI INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) -/* @brief FLEXCOMM7 I2C INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) -/* @brief FLEXCOMM7 I2S INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) -/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ -#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) -/* @brief I2S has DMIC interconnection */ -#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) - -/* HASHCRYPT module features */ - -/* @brief the address of alias offset */ -#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000) - -/* I2S module features */ - -/* @brief I2S support dual channel transfer. */ -#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0) -/* @brief I2S has DMIC interconnection */ -#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) - -/* IOCON module features */ - -/* @brief Func bit field width */ -#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) - -/* MAILBOX module features */ - -/* @brief Mailbox side for current core */ -#define FSL_FEATURE_MAILBOX_SIDE_A (1) - -/* MRT module features */ - -/* @brief number of channels. */ -#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) - -/* PINT module features */ - -/* @brief Number of connected outputs */ -#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) - -/* PLU module features */ - -/* @brief Has WAKEINT_CTRL register. */ -#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) - -/* PMC module features */ - -/* @brief UTICK does not support PD configure. */ -#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) -/* @brief WDT OSC does not support PD configure. */ -#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) - -/* POWERLIB module features */ - -/* @brief Powerlib API is different with other LPC series devices. */ -#define FSL_FEATURE_POWERLIB_EXTEND (1) - -/* POWERQUAD module features */ - -/* @brief Sine and Cossine fix errata */ -#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1) - -/* PUF module features */ - -/* @brief Number of PUF key slots available on device. */ -#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4) -/* @brief the shift status value */ -#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) - -/* RTC module features */ - -/* No feature definitions */ - -/* SCT module features */ - -/* @brief Number of events */ -#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) -/* @brief Number of states */ -#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) -/* @brief Number of match capture */ -#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) -/* @brief Number of outputs */ -#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) - -/* SDIF module features */ - -/* @brief FIFO depth, every location is a WORD */ -#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) -/* @brief Max DMA buffer size */ -#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) -/* @brief Max source clock in HZ */ -#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) -/* @brief support 2 cards */ -#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1) - -/* SECPINT module features */ - -/* @brief Number of connected outputs */ -#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) - -/* SYSCON module features */ - -/* @brief Flash page size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) -/* @brief Flash sector size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) -/* @brief Flash size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (645120) -/* @brief Has Power Down mode */ -#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) -/* @brief CCM_ANALOG availability on the SoC. */ -#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) -/* @brief Starter register discontinuous. */ -#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) - -/* SYSCTL1 module features */ - -/* No feature definitions */ - -/* USB module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USB_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USB version */ -#define FSL_FEATURE_USB_VERSION (200) -/* @brief Number of the endpoint in USB FS */ -#define FSL_FEATURE_USB_EP_NUM (5) - -/* USBFSH module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USBFSH version */ -#define FSL_FEATURE_USBFSH_VERSION (200) - -/* USBHSD module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USBHSD version */ -#define FSL_FEATURE_USBHSD_VERSION (300) -/* @brief Number of the endpoint in USB HS */ -#define FSL_FEATURE_USBHSD_EP_NUM (6) - -/* USBHSH module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USBHSH version */ -#define FSL_FEATURE_USBHSH_VERSION (300) - -/* USBPHY module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBPHY_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USBHSD version */ -#define FSL_FEATURE_USBPHY_VERSION (300) -/* @brief Number of the endpoint in USB HS */ -#define FSL_FEATURE_USBPHY_EP_NUM (6) - -/* WWDT module features */ - -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) -/* @brief WWDT does not support oscillator lock. */ -#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) - -#endif /* _LPC55S69_cm33_core0_FEATURES_H_ */ - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.h deleted file mode 100644 index 0c92b268aa9..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.h +++ /dev/null @@ -1,31239 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JBD64_cm33_core1 -** LPC55S69JEV98_cm33_core1 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b211009 -** -** Abstract: -** CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 -** -** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** - rev. 1.1 (2019-05-16) -** Initial A1 version based on v1.3UM -** -** ################################################################### -*/ - -/*! - * @file LPC55S69_cm33_core1.h - * @version 1.1 - * @date 2019-05-16 - * @brief CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 - * - * CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 - */ - -#ifndef _LPC55S69_CM33_CORE1_H_ -#define _LPC55S69_CM33_CORE1_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0001U - - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 76 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Auxiliary constants */ - NotAvail_IRQn = -128, /**< Not available device specific interrupt */ - - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ - - /* Device specific interrupts */ - WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */ - DMA0_IRQn = 1, /**< DMA0 controller */ - GINT0_IRQn = 2, /**< GPIO group 0 */ - GINT1_IRQn = 3, /**< GPIO group 1 */ - PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ - PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ - PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ - PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ - UTICK0_IRQn = 8, /**< Micro-tick Timer */ - MRT0_IRQn = 9, /**< Multi-rate timer */ - CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ - CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ - SCT0_IRQn = 12, /**< SCTimer/PWM */ - CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ - FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - ADC0_IRQn = 22, /**< ADC0 */ - Reserved39_IRQn = 23, /**< Reserved interrupt */ - ACMP_IRQn = 24, /**< ACMP interrupts */ - Reserved41_IRQn = 25, /**< Reserved interrupt */ - Reserved42_IRQn = 26, /**< Reserved interrupt */ - USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ - USB0_IRQn = 28, /**< USB device */ - RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ - Reserved46_IRQn = 30, /**< Reserved interrupt */ - MAILBOX_IRQn = 31, /**< WAKEUP,Mailbox interrupt (present on selected devices) */ - PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ - PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ - PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ - PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ - CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ - CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ - OS_EVENT_IRQn = 38, /**< OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ - Reserved55_IRQn = 39, /**< Reserved interrupt */ - Reserved56_IRQn = 40, /**< Reserved interrupt */ - Reserved57_IRQn = 41, /**< Reserved interrupt */ - SDIO_IRQn = 42, /**< SD/MMC */ - Reserved59_IRQn = 43, /**< Reserved interrupt */ - Reserved60_IRQn = 44, /**< Reserved interrupt */ - Reserved61_IRQn = 45, /**< Reserved interrupt */ - USB1_PHY_IRQn = 46, /**< USB1_PHY */ - USB1_IRQn = 47, /**< USB1 interrupt */ - USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ - SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */ - SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */ - SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */ - PLU_IRQn = 52, /**< PLU interrupt */ - SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */ - HASHCRYPT_IRQn = 54, /**< HASHCRYPT interrupt */ - CASER_IRQn = 55, /**< CASPER interrupt */ - PUF_IRQn = 56, /**< PUF interrupt */ - PQ_IRQn = 57, /**< PQ interrupt */ - DMA1_IRQn = 58, /**< DMA1 interrupt */ - FLEXCOMM8_IRQn = 59 /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M33 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration - * @{ - */ - -#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ -#define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */ -#define __DSP_PRESENT 0 /**< Defines if Armv8-M Mainline core supports DSP instructions */ -#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ - -#include "core_cm33.h" /* Core Peripheral Access Layer */ -#include "system_LPC55S69_cm33_core1.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Mapping Information - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Mapping_Information Mapping Information - * @{ - */ - -/** Mapping Information */ -/*! - * @addtogroup dma_request - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief Structure for the DMA hardware request - * - * Defines the structure for the DMA hardware request collections. The user can configure the - * hardware request to trigger the DMA transfer accordingly. The index - * of the hardware request varies according to the to SoC. - */ -typedef enum _dma_request_source -{ - kDma0RequestHashCrypt = 0U, /**< HashCrypt */ - kDma1RequestHashCrypt = 0U, /**< HashCrypt */ - kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ - kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ - kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ - kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ - kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ - kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ - kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ - kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ - kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ - kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ - kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ - kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ - kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ - kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ - kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ - kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ - kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ - kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ - kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */ - kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */ - kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */ - kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */ - kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */ - kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */ - kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */ - kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */ - kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */ - kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */ - kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */ - kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */ - kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */ -} dma_request_source_t; - -/* @} */ - - -/*! - * @} - */ /* end of group Mapping_Information */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #else - #pragma push - #pragma anon_unions - #endif -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ - __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ - __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ - __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ - __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ - __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ - uint8_t RESERVED_1[12]; - __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ - __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ - uint8_t RESERVED_2[4]; - __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ - uint8_t RESERVED_3[92]; - __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ - __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ - uint8_t RESERVED_4[8]; - __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ - __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ - struct { /* offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ - } CMD[15]; - uint8_t RESERVED_5[136]; - __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_6[240]; - __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ - uint8_t RESERVED_7[248]; - __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ - uint8_t RESERVED_8[124]; - __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */ - uint8_t RESERVED_9[2680]; - __IO uint32_t TST; /**< ADC Test Register, offset: 0xFFC */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ - -#define ADC_VERID_RES_MASK (0x1U) -#define ADC_VERID_RES_SHIFT (0U) -/*! RES - Resolution - * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. - * 0b1..Up to 16-bit differential/16-bit single ended resolution supported. - */ -#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) - -#define ADC_VERID_DIFFEN_MASK (0x2U) -#define ADC_VERID_DIFFEN_SHIFT (1U) -/*! DIFFEN - Differential Supported - * 0b0..Differential operation not supported. - * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented. - */ -#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) - -#define ADC_VERID_MVI_MASK (0x8U) -#define ADC_VERID_MVI_SHIFT (3U) -/*! MVI - Multi Vref Implemented - * 0b0..Single voltage reference high (VREFH) input supported. - * 0b1..Multiple voltage reference high (VREFH) inputs supported. - */ -#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) - -#define ADC_VERID_CSW_MASK (0x70U) -#define ADC_VERID_CSW_SHIFT (4U) -/*! CSW - Channel Scale Width - * 0b000..Channel scaling not supported. - * 0b001..Channel scaling supported. 1-bit CSCALE control field. - * 0b110..Channel scaling supported. 6-bit CSCALE control field. - */ -#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) - -#define ADC_VERID_VR1RNGI_MASK (0x100U) -#define ADC_VERID_VR1RNGI_SHIFT (8U) -/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented - * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. - * 0b1..Range control required. CFG[VREF1RNG] is implemented. - */ -#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) - -#define ADC_VERID_IADCKI_MASK (0x200U) -#define ADC_VERID_IADCKI_SHIFT (9U) -/*! IADCKI - Internal ADC Clock implemented - * 0b0..Internal clock source not implemented. - * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. - */ -#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) - -#define ADC_VERID_CALOFSI_MASK (0x400U) -#define ADC_VERID_CALOFSI_SHIFT (10U) -/*! CALOFSI - Calibration Function Implemented - * 0b0..Calibration Not Implemented. - * 0b1..Calibration Implemented. - */ -#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) - -#define ADC_VERID_NUM_SEC_MASK (0x800U) -#define ADC_VERID_NUM_SEC_SHIFT (11U) -/*! NUM_SEC - Number of Single Ended Outputs Supported - * 0b0..This design supports one single ended conversion at a time. - * 0b1..This design supports two simultanious single ended conversions. - */ -#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) - -#define ADC_VERID_NUM_FIFO_MASK (0x7000U) -#define ADC_VERID_NUM_FIFO_SHIFT (12U) -/*! NUM_FIFO - Number of FIFOs - * 0b000..N/A - * 0b001..This design supports one result FIFO. - * 0b010..This design supports two result FIFOs. - * 0b011..This design supports three result FIFOs. - * 0b100..This design supports four result FIFOs. - */ -#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) - -#define ADC_VERID_MINOR_MASK (0xFF0000U) -#define ADC_VERID_MINOR_SHIFT (16U) -/*! MINOR - Minor Version Number - */ -#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) - -#define ADC_VERID_MAJOR_MASK (0xFF000000U) -#define ADC_VERID_MAJOR_SHIFT (24U) -/*! MAJOR - Major Version Number - */ -#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ - -#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) -#define ADC_PARAM_TRIG_NUM_SHIFT (0U) -/*! TRIG_NUM - Trigger Number - */ -#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) - -#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) -#define ADC_PARAM_FIFOSIZE_SHIFT (8U) -/*! FIFOSIZE - Result FIFO Depth - * 0b00000001..Result FIFO depth = 1 dataword. - * 0b00000100..Result FIFO depth = 4 datawords. - * 0b00001000..Result FIFO depth = 8 datawords. - * 0b00010000..Result FIFO depth = 16 datawords. - * 0b00100000..Result FIFO depth = 32 datawords. - * 0b01000000..Result FIFO depth = 64 datawords. - */ -#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) - -#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) -#define ADC_PARAM_CV_NUM_SHIFT (16U) -/*! CV_NUM - Compare Value Number - */ -#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) - -#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) -#define ADC_PARAM_CMD_NUM_SHIFT (24U) -/*! CMD_NUM - Command Buffer Number - */ -#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) -/*! @} */ - -/*! @name CTRL - ADC Control Register */ -/*! @{ */ - -#define ADC_CTRL_ADCEN_MASK (0x1U) -#define ADC_CTRL_ADCEN_SHIFT (0U) -/*! ADCEN - ADC Enable - * 0b0..ADC is disabled. - * 0b1..ADC is enabled. - */ -#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) - -#define ADC_CTRL_RST_MASK (0x2U) -#define ADC_CTRL_RST_SHIFT (1U) -/*! RST - Software Reset - * 0b0..ADC logic is not reset. - * 0b1..ADC logic is reset. - */ -#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) - -#define ADC_CTRL_DOZEN_MASK (0x4U) -#define ADC_CTRL_DOZEN_SHIFT (2U) -/*! DOZEN - Doze Enable - * 0b0..ADC is enabled in Doze mode. - * 0b1..ADC is disabled in Doze mode. - */ -#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) - -#define ADC_CTRL_CAL_REQ_MASK (0x8U) -#define ADC_CTRL_CAL_REQ_SHIFT (3U) -/*! CAL_REQ - Auto-Calibration Request - * 0b0..No request for auto-calibration has been made. - * 0b1..A request for auto-calibration has been made - */ -#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) - -#define ADC_CTRL_CALOFS_MASK (0x10U) -#define ADC_CTRL_CALOFS_SHIFT (4U) -/*! CALOFS - Configure for offset calibration function - * 0b0..Calibration function disabled - * 0b1..Request for offset calibration function - */ -#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) - -#define ADC_CTRL_RSTFIFO0_MASK (0x100U) -#define ADC_CTRL_RSTFIFO0_SHIFT (8U) -/*! RSTFIFO0 - Reset FIFO 0 - * 0b0..No effect. - * 0b1..FIFO 0 is reset. - */ -#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) - -#define ADC_CTRL_RSTFIFO1_MASK (0x200U) -#define ADC_CTRL_RSTFIFO1_SHIFT (9U) -/*! RSTFIFO1 - Reset FIFO 1 - * 0b0..No effect. - * 0b1..FIFO 1 is reset. - */ -#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) - -#define ADC_CTRL_CAL_AVGS_MASK (0x70000U) -#define ADC_CTRL_CAL_AVGS_SHIFT (16U) -/*! CAL_AVGS - Auto-Calibration Averages - * 0b000..Single conversion. - * 0b001..2 conversions averaged. - * 0b010..4 conversions averaged. - * 0b011..8 conversions averaged. - * 0b100..16 conversions averaged. - * 0b101..32 conversions averaged. - * 0b110..64 conversions averaged. - * 0b111..128 conversions averaged. - */ -#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) -/*! @} */ - -/*! @name STAT - ADC Status Register */ -/*! @{ */ - -#define ADC_STAT_RDY0_MASK (0x1U) -#define ADC_STAT_RDY0_SHIFT (0U) -/*! RDY0 - Result FIFO 0 Ready Flag - * 0b0..Result FIFO 0 data level not above watermark level. - * 0b1..Result FIFO 0 holding data above watermark level. - */ -#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) - -#define ADC_STAT_FOF0_MASK (0x2U) -#define ADC_STAT_FOF0_SHIFT (1U) -/*! FOF0 - Result FIFO 0 Overflow Flag - * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) - -#define ADC_STAT_RDY1_MASK (0x4U) -#define ADC_STAT_RDY1_SHIFT (2U) -/*! RDY1 - Result FIFO1 Ready Flag - * 0b0..Result FIFO1 data level not above watermark level. - * 0b1..Result FIFO1 holding data above watermark level. - */ -#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) - -#define ADC_STAT_FOF1_MASK (0x8U) -#define ADC_STAT_FOF1_SHIFT (3U) -/*! FOF1 - Result FIFO1 Overflow Flag - * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) - -#define ADC_STAT_TEXC_INT_MASK (0x100U) -#define ADC_STAT_TEXC_INT_SHIFT (8U) -/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception - * 0b0..No trigger exceptions have occurred. - * 0b1..A trigger exception has occurred and is pending acknowledgement. - */ -#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) - -#define ADC_STAT_TCOMP_INT_MASK (0x200U) -#define ADC_STAT_TCOMP_INT_SHIFT (9U) -/*! TCOMP_INT - Interrupt Flag For Trigger Completion - * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. - * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. - */ -#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) - -#define ADC_STAT_CAL_RDY_MASK (0x400U) -#define ADC_STAT_CAL_RDY_SHIFT (10U) -/*! CAL_RDY - Calibration Ready - * 0b0..Calibration is incomplete or hasn't been ran. - * 0b1..The ADC is calibrated. - */ -#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) - -#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) -#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) -/*! ADC_ACTIVE - ADC Active - * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. - * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. - */ -#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) - -#define ADC_STAT_TRGACT_MASK (0xF0000U) -#define ADC_STAT_TRGACT_SHIFT (16U) -/*! TRGACT - Trigger Active - * 0b0000..Command (sequence) associated with Trigger 0 currently being executed. - * 0b0001..Command (sequence) associated with Trigger 1 currently being executed. - * 0b0010..Command (sequence) associated with Trigger 2 currently being executed. - * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed. - */ -#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) - -#define ADC_STAT_CMDACT_MASK (0xF000000U) -#define ADC_STAT_CMDACT_SHIFT (24U) -/*! CMDACT - Command Active - * 0b0000..No command is currently in progress. - * 0b0001..Command 1 currently being executed. - * 0b0010..Command 2 currently being executed. - * 0b0011-0b1111..Associated command number is currently being executed. - */ -#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) -/*! @} */ - -/*! @name IE - Interrupt Enable Register */ -/*! @{ */ - -#define ADC_IE_FWMIE0_MASK (0x1U) -#define ADC_IE_FWMIE0_SHIFT (0U) -/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable - * 0b0..FIFO 0 watermark interrupts are not enabled. - * 0b1..FIFO 0 watermark interrupts are enabled. - */ -#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) - -#define ADC_IE_FOFIE0_MASK (0x2U) -#define ADC_IE_FOFIE0_SHIFT (1U) -/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable - * 0b0..FIFO 0 overflow interrupts are not enabled. - * 0b1..FIFO 0 overflow interrupts are enabled. - */ -#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) - -#define ADC_IE_FWMIE1_MASK (0x4U) -#define ADC_IE_FWMIE1_SHIFT (2U) -/*! FWMIE1 - FIFO1 Watermark Interrupt Enable - * 0b0..FIFO1 watermark interrupts are not enabled. - * 0b1..FIFO1 watermark interrupts are enabled. - */ -#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) - -#define ADC_IE_FOFIE1_MASK (0x8U) -#define ADC_IE_FOFIE1_SHIFT (3U) -/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable - * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) - -#define ADC_IE_TEXC_IE_MASK (0x100U) -#define ADC_IE_TEXC_IE_SHIFT (8U) -/*! TEXC_IE - Trigger Exception Interrupt Enable - * 0b0..Trigger exception interrupts are disabled. - * 0b1..Trigger exception interrupts are enabled. - */ -#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) - -#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U) -#define ADC_IE_TCOMP_IE_SHIFT (16U) -/*! TCOMP_IE - Trigger Completion Interrupt Enable - * 0b0000000000000000..Trigger completion interrupts are disabled. - * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only. - * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only. - * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled. - * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source. - */ -#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) -/*! @} */ - -/*! @name DE - DMA Enable Register */ -/*! @{ */ - -#define ADC_DE_FWMDE0_MASK (0x1U) -#define ADC_DE_FWMDE0_SHIFT (0U) -/*! FWMDE0 - FIFO 0 Watermark DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) - -#define ADC_DE_FWMDE1_MASK (0x2U) -#define ADC_DE_FWMDE1_SHIFT (1U) -/*! FWMDE1 - FIFO1 Watermark DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) -/*! @} */ - -/*! @name CFG - ADC Configuration Register */ -/*! @{ */ - -#define ADC_CFG_TPRICTRL_MASK (0x3U) -#define ADC_CFG_TPRICTRL_SHIFT (0U) -/*! TPRICTRL - ADC trigger priority control - * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted - * and the new command specified by the trigger is started. - * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after - * after completing the current conversion. If averaging is enabled, the averaging loop will be completed. - * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. - * 0b10..If a higher priority trigger is received during command processing, the current command will be - * completed (averaging, looping, compare) before servicing the higher priority trigger. - * 0b11..RESERVED - */ -#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) - -#define ADC_CFG_PWRSEL_MASK (0x30U) -#define ADC_CFG_PWRSEL_SHIFT (4U) -/*! PWRSEL - Power Configuration Select - * 0b00..Lowest power setting. - * 0b01..Higher power setting than 0b0. - * 0b10..Higher power setting than 0b1. - * 0b11..Highest power setting. - */ -#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) - -#define ADC_CFG_REFSEL_MASK (0xC0U) -#define ADC_CFG_REFSEL_SHIFT (6U) -/*! REFSEL - Voltage Reference Selection - * 0b00..(Default) Option 1 setting. - * 0b01..Option 2 setting. - * 0b10..Option 3 setting. - * 0b11..Reserved - */ -#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) - -#define ADC_CFG_TRES_MASK (0x100U) -#define ADC_CFG_TRES_SHIFT (8U) -/*! TRES - Trigger Resume Enable - * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. - * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. - */ -#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) - -#define ADC_CFG_TCMDRES_MASK (0x200U) -#define ADC_CFG_TCMDRES_SHIFT (9U) -/*! TCMDRES - Trigger Command Resume - * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. - * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. - */ -#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) - -#define ADC_CFG_HPT_EXDI_MASK (0x400U) -#define ADC_CFG_HPT_EXDI_SHIFT (10U) -/*! HPT_EXDI - High Priority Trigger Exception Disable - * 0b0..High priority trigger exceptions are enabled. - * 0b1..High priority trigger exceptions are disabled. - */ -#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) - -#define ADC_CFG_PUDLY_MASK (0xFF0000U) -#define ADC_CFG_PUDLY_SHIFT (16U) -/*! PUDLY - Power Up Delay - */ -#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) - -#define ADC_CFG_PWREN_MASK (0x10000000U) -#define ADC_CFG_PWREN_SHIFT (28U) -/*! PWREN - ADC Analog Pre-Enable - * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. - * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost - * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN - * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. - * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be - * executed. - */ -#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) -/*! @} */ - -/*! @name PAUSE - ADC Pause Register */ -/*! @{ */ - -#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) -#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) -/*! PAUSEDLY - Pause Delay - */ -#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) - -#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) -#define ADC_PAUSE_PAUSEEN_SHIFT (31U) -/*! PAUSEEN - PAUSE Option Enable - * 0b0..Pause operation disabled - * 0b1..Pause operation enabled - */ -#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) -/*! @} */ - -/*! @name SWTRIG - Software Trigger Register */ -/*! @{ */ - -#define ADC_SWTRIG_SWT0_MASK (0x1U) -#define ADC_SWTRIG_SWT0_SHIFT (0U) -/*! SWT0 - Software trigger 0 event - * 0b0..No trigger 0 event generated. - * 0b1..Trigger 0 event generated. - */ -#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) - -#define ADC_SWTRIG_SWT1_MASK (0x2U) -#define ADC_SWTRIG_SWT1_SHIFT (1U) -/*! SWT1 - Software trigger 1 event - * 0b0..No trigger 1 event generated. - * 0b1..Trigger 1 event generated. - */ -#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) - -#define ADC_SWTRIG_SWT2_MASK (0x4U) -#define ADC_SWTRIG_SWT2_SHIFT (2U) -/*! SWT2 - Software trigger 2 event - * 0b0..No trigger 2 event generated. - * 0b1..Trigger 2 event generated. - */ -#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) - -#define ADC_SWTRIG_SWT3_MASK (0x8U) -#define ADC_SWTRIG_SWT3_SHIFT (3U) -/*! SWT3 - Software trigger 3 event - * 0b0..No trigger 3 event generated. - * 0b1..Trigger 3 event generated. - */ -#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) - -#define ADC_SWTRIG_SWT4_MASK (0x10U) -#define ADC_SWTRIG_SWT4_SHIFT (4U) -/*! SWT4 - Software trigger 4 event - * 0b0..No trigger 4 event generated. - * 0b1..Trigger 4 event generated. - */ -#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) - -#define ADC_SWTRIG_SWT5_MASK (0x20U) -#define ADC_SWTRIG_SWT5_SHIFT (5U) -/*! SWT5 - Software trigger 5 event - * 0b0..No trigger 5 event generated. - * 0b1..Trigger 5 event generated. - */ -#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) - -#define ADC_SWTRIG_SWT6_MASK (0x40U) -#define ADC_SWTRIG_SWT6_SHIFT (6U) -/*! SWT6 - Software trigger 6 event - * 0b0..No trigger 6 event generated. - * 0b1..Trigger 6 event generated. - */ -#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) - -#define ADC_SWTRIG_SWT7_MASK (0x80U) -#define ADC_SWTRIG_SWT7_SHIFT (7U) -/*! SWT7 - Software trigger 7 event - * 0b0..No trigger 7 event generated. - * 0b1..Trigger 7 event generated. - */ -#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) - -#define ADC_SWTRIG_SWT8_MASK (0x100U) -#define ADC_SWTRIG_SWT8_SHIFT (8U) -/*! SWT8 - Software trigger 8 event - * 0b0..No trigger 8 event generated. - * 0b1..Trigger 8 event generated. - */ -#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK) - -#define ADC_SWTRIG_SWT9_MASK (0x200U) -#define ADC_SWTRIG_SWT9_SHIFT (9U) -/*! SWT9 - Software trigger 9 event - * 0b0..No trigger 9 event generated. - * 0b1..Trigger 9 event generated. - */ -#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK) - -#define ADC_SWTRIG_SWT10_MASK (0x400U) -#define ADC_SWTRIG_SWT10_SHIFT (10U) -/*! SWT10 - Software trigger 10 event - * 0b0..No trigger 10 event generated. - * 0b1..Trigger 10 event generated. - */ -#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK) - -#define ADC_SWTRIG_SWT11_MASK (0x800U) -#define ADC_SWTRIG_SWT11_SHIFT (11U) -/*! SWT11 - Software trigger 11 event - * 0b0..No trigger 11 event generated. - * 0b1..Trigger 11 event generated. - */ -#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK) - -#define ADC_SWTRIG_SWT12_MASK (0x1000U) -#define ADC_SWTRIG_SWT12_SHIFT (12U) -/*! SWT12 - Software trigger 12 event - * 0b0..No trigger 12 event generated. - * 0b1..Trigger 12 event generated. - */ -#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK) - -#define ADC_SWTRIG_SWT13_MASK (0x2000U) -#define ADC_SWTRIG_SWT13_SHIFT (13U) -/*! SWT13 - Software trigger 13 event - * 0b0..No trigger 13 event generated. - * 0b1..Trigger 13 event generated. - */ -#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK) - -#define ADC_SWTRIG_SWT14_MASK (0x4000U) -#define ADC_SWTRIG_SWT14_SHIFT (14U) -/*! SWT14 - Software trigger 14 event - * 0b0..No trigger 14 event generated. - * 0b1..Trigger 14 event generated. - */ -#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK) - -#define ADC_SWTRIG_SWT15_MASK (0x8000U) -#define ADC_SWTRIG_SWT15_SHIFT (15U) -/*! SWT15 - Software trigger 15 event - * 0b0..No trigger 15 event generated. - * 0b1..Trigger 15 event generated. - */ -#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK) -/*! @} */ - -/*! @name TSTAT - Trigger Status Register */ -/*! @{ */ - -#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU) -#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) -/*! TEXC_NUM - Trigger Exception Number - * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. - * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception. - * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception. - * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception. - * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception. - */ -#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) - -#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U) -#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) -/*! TCOMP_FLAG - Trigger Completion Flag - * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled. - * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts. - * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts. - * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts. - * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. - */ -#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) -/*! @} */ - -/*! @name OFSTRIM - ADC Offset Trim Register */ -/*! @{ */ - -#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) -#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) -/*! OFSTRIM_A - Trim for offset - */ -#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) - -#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) -#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) -/*! OFSTRIM_B - Trim for offset - */ -#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) -/*! @} */ - -/*! @name TCTRL - Trigger Control Register */ -/*! @{ */ - -#define ADC_TCTRL_HTEN_MASK (0x1U) -#define ADC_TCTRL_HTEN_SHIFT (0U) -/*! HTEN - Trigger enable - * 0b0..Hardware trigger source disabled - * 0b1..Hardware trigger source enabled - */ -#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) - -#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) -#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) -/*! FIFO_SEL_A - SAR Result Destination For Channel A - * 0b0..Result written to FIFO 0 - * 0b1..Result written to FIFO 1 - */ -#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) - -#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) -#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) -/*! FIFO_SEL_B - SAR Result Destination For Channel B - * 0b0..Result written to FIFO 0 - * 0b1..Result written to FIFO 1 - */ -#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) - -#define ADC_TCTRL_TPRI_MASK (0xF00U) -#define ADC_TCTRL_TPRI_SHIFT (8U) -/*! TPRI - Trigger priority setting - * 0b0000..Set to highest priority, Level 1 - * 0b0001-0b1110..Set to corresponding priority level - * 0b1111..Set to lowest priority, Level 16 - */ -#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) - -#define ADC_TCTRL_RSYNC_MASK (0x8000U) -#define ADC_TCTRL_RSYNC_SHIFT (15U) -/*! RSYNC - Trigger Resync - */ -#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) - -#define ADC_TCTRL_TDLY_MASK (0xF0000U) -#define ADC_TCTRL_TDLY_SHIFT (16U) -/*! TDLY - Trigger delay select - */ -#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) - -#define ADC_TCTRL_TCMD_MASK (0xF000000U) -#define ADC_TCTRL_TCMD_SHIFT (24U) -/*! TCMD - Trigger command select - * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. - * 0b0001..CMD1 is executed - * 0b0010-0b1110..Corresponding CMD is executed - * 0b1111..CMD15 is executed - */ -#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) -/*! @} */ - -/* The count of ADC_TCTRL */ -#define ADC_TCTRL_COUNT (16U) - -/*! @name FCTRL - FIFO Control Register */ -/*! @{ */ - -#define ADC_FCTRL_FCOUNT_MASK (0x1FU) -#define ADC_FCTRL_FCOUNT_SHIFT (0U) -/*! FCOUNT - Result FIFO counter - */ -#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) - -#define ADC_FCTRL_FWMARK_MASK (0xF0000U) -#define ADC_FCTRL_FWMARK_SHIFT (16U) -/*! FWMARK - Watermark level selection - */ -#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) -/*! @} */ - -/* The count of ADC_FCTRL */ -#define ADC_FCTRL_COUNT (2U) - -/*! @name GCC - Gain Calibration Control */ -/*! @{ */ - -#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) -#define ADC_GCC_GAIN_CAL_SHIFT (0U) -/*! GAIN_CAL - Gain Calibration Value - */ -#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) - -#define ADC_GCC_RDY_MASK (0x1000000U) -#define ADC_GCC_RDY_SHIFT (24U) -/*! RDY - Gain Calibration Value Valid - * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. - * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. - */ -#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) -/*! @} */ - -/* The count of ADC_GCC */ -#define ADC_GCC_COUNT (2U) - -/*! @name GCR - Gain Calculation Result */ -/*! @{ */ - -#define ADC_GCR_GCALR_MASK (0xFFFFU) -#define ADC_GCR_GCALR_SHIFT (0U) -/*! GCALR - Gain Calculation Result - */ -#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) - -#define ADC_GCR_RDY_MASK (0x1000000U) -#define ADC_GCR_RDY_SHIFT (24U) -/*! RDY - Gain Calculation Ready - * 0b0..The gain offset calculation value is invalid. - * 0b1..The gain calibration value is valid. - */ -#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) -/*! @} */ - -/* The count of ADC_GCR */ -#define ADC_GCR_COUNT (2U) - -/*! @name CMDL - ADC Command Low Buffer Register */ -/*! @{ */ - -#define ADC_CMDL_ADCH_MASK (0x1FU) -#define ADC_CMDL_ADCH_SHIFT (0U) -/*! ADCH - Input channel select - * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. - * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. - * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. - * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. - * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. - * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. - */ -#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) - -#define ADC_CMDL_CTYPE_MASK (0x60U) -#define ADC_CMDL_CTYPE_SHIFT (5U) -/*! CTYPE - Conversion Type - * 0b00..Single-Ended Mode. Only A side channel is converted. - * 0b01..Single-Ended Mode. Only B side channel is converted. - * 0b10..Differential Mode. A-B. - * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - */ -#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) - -#define ADC_CMDL_MODE_MASK (0x80U) -#define ADC_CMDL_MODE_SHIFT (7U) -/*! MODE - Select resolution of conversions - * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - */ -#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) -/*! @} */ - -/* The count of ADC_CMDL */ -#define ADC_CMDL_COUNT (15U) - -/*! @name CMDH - ADC Command High Buffer Register */ -/*! @{ */ - -#define ADC_CMDH_CMPEN_MASK (0x3U) -#define ADC_CMDH_CMPEN_SHIFT (0U) -/*! CMPEN - Compare Function Enable - * 0b00..Compare disabled. - * 0b01..Reserved - * 0b10..Compare enabled. Store on true. - * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - */ -#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) - -#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) -#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) -/*! WAIT_TRIG - Wait for trigger assertion before execution. - * 0b0..This command will be automatically executed. - * 0b1..The active trigger must be asserted again before executing this command. - */ -#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) - -#define ADC_CMDH_LWI_MASK (0x80U) -#define ADC_CMDH_LWI_SHIFT (7U) -/*! LWI - Loop with Increment - * 0b0..Auto channel increment disabled - * 0b1..Auto channel increment enabled - */ -#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) - -#define ADC_CMDH_STS_MASK (0x700U) -#define ADC_CMDH_STS_SHIFT (8U) -/*! STS - Sample Time Select - * 0b000..Minimum sample time of 3 ADCK cycles. - * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - */ -#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) - -#define ADC_CMDH_AVGS_MASK (0x7000U) -#define ADC_CMDH_AVGS_SHIFT (12U) -/*! AVGS - Hardware Average Select - * 0b000..Single conversion. - * 0b001..2 conversions averaged. - * 0b010..4 conversions averaged. - * 0b011..8 conversions averaged. - * 0b100..16 conversions averaged. - * 0b101..32 conversions averaged. - * 0b110..64 conversions averaged. - * 0b111..128 conversions averaged. - */ -#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) - -#define ADC_CMDH_LOOP_MASK (0xF0000U) -#define ADC_CMDH_LOOP_SHIFT (16U) -/*! LOOP - Loop Count Select - * 0b0000..Looping not enabled. Command executes 1 time. - * 0b0001..Loop 1 time. Command executes 2 times. - * 0b0010..Loop 2 times. Command executes 3 times. - * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. - * 0b1111..Loop 15 times. Command executes 16 times. - */ -#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) - -#define ADC_CMDH_NEXT_MASK (0xF000000U) -#define ADC_CMDH_NEXT_SHIFT (24U) -/*! NEXT - Next Command Select - * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority - * trigger pending, begin command associated with lower priority trigger. - * 0b0001..Select CMD1 command buffer register as next command. - * 0b0010-0b1110..Select corresponding CMD command buffer register as next command - * 0b1111..Select CMD15 command buffer register as next command. - */ -#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) -/*! @} */ - -/* The count of ADC_CMDH */ -#define ADC_CMDH_COUNT (15U) - -/*! @name CV - Compare Value Register */ -/*! @{ */ - -#define ADC_CV_CVL_MASK (0xFFFFU) -#define ADC_CV_CVL_SHIFT (0U) -/*! CVL - Compare Value Low. - */ -#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) - -#define ADC_CV_CVH_MASK (0xFFFF0000U) -#define ADC_CV_CVH_SHIFT (16U) -/*! CVH - Compare Value High. - */ -#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) -/*! @} */ - -/* The count of ADC_CV */ -#define ADC_CV_COUNT (4U) - -/*! @name RESFIFO - ADC Data Result FIFO Register */ -/*! @{ */ - -#define ADC_RESFIFO_D_MASK (0xFFFFU) -#define ADC_RESFIFO_D_SHIFT (0U) -/*! D - Data result - */ -#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) - -#define ADC_RESFIFO_TSRC_MASK (0xF0000U) -#define ADC_RESFIFO_TSRC_SHIFT (16U) -/*! TSRC - Trigger Source - * 0b0000..Trigger source 0 initiated this conversion. - * 0b0001..Trigger source 1 initiated this conversion. - * 0b0010-0b1110..Corresponding trigger source initiated this conversion. - * 0b1111..Trigger source 15 initiated this conversion. - */ -#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) - -#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) -#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) -/*! LOOPCNT - Loop count value - * 0b0000..Result is from initial conversion in command. - * 0b0001..Result is from second conversion in command. - * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. - * 0b1111..Result is from 16th conversion in command. - */ -#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) - -#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) -#define ADC_RESFIFO_CMDSRC_SHIFT (24U) -/*! CMDSRC - Command Buffer Source - * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state - * prior to an ADC conversion result dataword being stored to a RESFIFO buffer. - * 0b0001..CMD1 buffer used as control settings for this conversion. - * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. - * 0b1111..CMD15 buffer used as control settings for this conversion. - */ -#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) - -#define ADC_RESFIFO_VALID_MASK (0x80000000U) -#define ADC_RESFIFO_VALID_SHIFT (31U) -/*! VALID - FIFO entry is valid - * 0b0..FIFO is empty. Discard any read from RESFIFO. - * 0b1..FIFO record read from RESFIFO is valid. - */ -#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) -/*! @} */ - -/* The count of ADC_RESFIFO */ -#define ADC_RESFIFO_COUNT (2U) - -/*! @name CAL_GAR - Calibration General A-Side Registers */ -/*! @{ */ - -#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) -#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) -/*! CAL_GAR_VAL - Calibration General A Side Register Element - */ -#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) -/*! @} */ - -/* The count of ADC_CAL_GAR */ -#define ADC_CAL_GAR_COUNT (33U) - -/*! @name CAL_GBR - Calibration General B-Side Registers */ -/*! @{ */ - -#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) -#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) -/*! CAL_GBR_VAL - Calibration General B Side Register Element - */ -#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) -/*! @} */ - -/* The count of ADC_CAL_GBR */ -#define ADC_CAL_GBR_COUNT (33U) - -/*! @name TST - ADC Test Register */ -/*! @{ */ - -#define ADC_TST_CST_LONG_MASK (0x1U) -#define ADC_TST_CST_LONG_SHIFT (0U) -/*! CST_LONG - Calibration Sample Time Long - * 0b0..Normal sample time. Minimum sample time of 3 ADCK cycles. - * 0b1..Increased sample time. 67 ADCK cycles total sample time. - */ -#define ADC_TST_CST_LONG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_CST_LONG_SHIFT)) & ADC_TST_CST_LONG_MASK) - -#define ADC_TST_FOFFM_MASK (0x100U) -#define ADC_TST_FOFFM_SHIFT (8U) -/*! FOFFM - Force M-side positive offset - * 0b0..Normal operation. No forced offset. - * 0b1..Test configuration. Forced positive offset on MDAC. - */ -#define ADC_TST_FOFFM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK) - -#define ADC_TST_FOFFP_MASK (0x200U) -#define ADC_TST_FOFFP_SHIFT (9U) -/*! FOFFP - Force P-side positive offset - * 0b0..Normal operation. No forced offset. - * 0b1..Test configuration. Forced positive offset on PDAC. - */ -#define ADC_TST_FOFFP(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK) - -#define ADC_TST_FOFFM2_MASK (0x400U) -#define ADC_TST_FOFFM2_SHIFT (10U) -/*! FOFFM2 - Force M-side negative offset - * 0b0..Normal operation. No forced offset. - * 0b1..Test configuration. Forced negative offset on MDAC. - */ -#define ADC_TST_FOFFM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM2_SHIFT)) & ADC_TST_FOFFM2_MASK) - -#define ADC_TST_FOFFP2_MASK (0x800U) -#define ADC_TST_FOFFP2_SHIFT (11U) -/*! FOFFP2 - Force P-side negative offset - * 0b0..Normal operation. No forced offset. - * 0b1..Test configuration. Forced negative offset on PDAC. - */ -#define ADC_TST_FOFFP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP2_SHIFT)) & ADC_TST_FOFFP2_MASK) - -#define ADC_TST_TESTEN_MASK (0x800000U) -#define ADC_TST_TESTEN_SHIFT (23U) -/*! TESTEN - Enable test configuration - * 0b0..Normal operation. Test configuration not enabled. - * 0b1..Hardware BIST Test in progress. - */ -#define ADC_TST_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_TESTEN_SHIFT)) & ADC_TST_TESTEN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ADC_Register_Masks */ - - -/* ADC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral ADC0 base address */ - #define ADC0_BASE (0x500A0000u) - /** Peripheral ADC0 base address */ - #define ADC0_BASE_NS (0x400A0000u) - /** Peripheral ADC0 base pointer */ - #define ADC0 ((ADC_Type *)ADC0_BASE) - /** Peripheral ADC0 base pointer */ - #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS { ADC0_BASE } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS { ADC0 } - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS_NS { ADC0_NS } -#else - /** Peripheral ADC0 base address */ - #define ADC0_BASE (0x400A0000u) - /** Peripheral ADC0 base pointer */ - #define ADC0 ((ADC_Type *)ADC0_BASE) - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS { ADC0_BASE } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS { ADC0 } -#endif -/** Interrupt vectors for the ADC peripheral type */ -#define ADC_IRQS { ADC0_IRQn } - -/*! - * @} - */ /* end of group ADC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- AHB_SECURE_CTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer - * @{ - */ - -/** AHB_SECURE_CTRL - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x30 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */ - uint8_t RESERVED_0[12]; - __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[3]; /**< Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */ - uint8_t RESERVED_1[4]; - __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */ - } SEC_CTRL_FLASH_ROM[1]; - struct { /* offset: 0x30, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAMX slaves., array offset: 0x40, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_RAMX[1]; - uint8_t RESERVED_0[12]; - struct { /* offset: 0x50, array step: 0x18 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x18 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM0 slaves., array offset: 0x60, array step: index*0x18, index2*0x4 */ - } SEC_CTRL_RAM0[1]; - uint8_t RESERVED_1[8]; - struct { /* offset: 0x70, array step: 0x18 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x18 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM1 slaves., array offset: 0x80, array step: index*0x18, index2*0x4 */ - } SEC_CTRL_RAM1[1]; - uint8_t RESERVED_2[8]; - struct { /* offset: 0x90, array step: 0x18 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x18 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step: index*0x18, index2*0x4 */ - } SEC_CTRL_RAM2[1]; - uint8_t RESERVED_3[8]; - struct { /* offset: 0xB0, array step: 0x18 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM3 slaves., array offset: 0xB0, array step: 0x18 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM3 slaves., array offset: 0xC0, array step: index*0x18, index2*0x4 */ - } SEC_CTRL_RAM3[1]; - uint8_t RESERVED_4[8]; - struct { /* offset: 0xD0, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM4 slaves., array offset: 0xD0, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM4 slaves., array offset: 0xE0, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_RAM4[1]; - uint8_t RESERVED_5[12]; - struct { /* offset: 0xF0, array step: 0x30 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for both APB Bridges slaves., array offset: 0xF0, array step: 0x30 */ - uint8_t RESERVED_0[12]; - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x100, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x104, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x108, array step: 0x30 */ - uint8_t RESERVED_1[4]; - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x110, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x114, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x118, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x11C, array step: 0x30 */ - } SEC_CTRL_APB_BRIDGE[1]; - __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */ - __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */ - uint8_t RESERVED_6[8]; - __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */ - __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */ - uint8_t RESERVED_7[8]; - struct { /* offset: 0x140, array step: 0x14 */ - __IO uint32_t SLAVE0_RULE; /**< Security access rules for AHB peripherals., array offset: 0x140, array step: 0x14 */ - __IO uint32_t SLAVE1_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */ - uint8_t RESERVED_0[8]; - __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x150, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_AHB_PORT10[1]; - uint8_t RESERVED_8[12]; - struct { /* offset: 0x160, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0x160, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM_USB_HS., array offset: 0x170, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_USB_HS[1]; - uint8_t RESERVED_9[3212]; - __I uint32_t SEC_VIO_ADDR[12]; /**< most recent security violation address for AHB port n, array offset: 0xE00, array step: 0x4 */ - uint8_t RESERVED_10[80]; - __I uint32_t SEC_VIO_MISC_INFO[12]; /**< most recent security violation miscellaneous information for AHB port n, array offset: 0xE80, array step: 0x4 */ - uint8_t RESERVED_11[80]; - __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */ - uint8_t RESERVED_12[124]; - __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */ - __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */ - uint8_t RESERVED_13[8]; - __IO uint32_t SEC_CPU_INT_MASK0; /**< Secure Interrupt mask for CPU1, offset: 0xF90 */ - __IO uint32_t SEC_CPU_INT_MASK1; /**< Secure Interrupt mask for CPU1, offset: 0xF94 */ - uint8_t RESERVED_14[36]; - __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */ - uint8_t RESERVED_15[16]; - __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */ - __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */ - uint8_t RESERVED_16[20]; - __IO uint32_t CPU0_LOCK_REG; /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */ - __IO uint32_t CPU1_LOCK_REG; /**< Miscalleneous control signals for in micro-Cortex M33 (CPU1), offset: 0xFF0 */ - uint8_t RESERVED_17[4]; - __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */ - __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */ -} AHB_SECURE_CTRL_Type; - -/* ---------------------------------------------------------------------------- - -- AHB_SECURE_CTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks - * @{ - */ - -/*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U) -/*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U) -/*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U) - -/*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U) - -/*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U) -/*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAMX_MEM_RULE - Security access rules for RAMX slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U) -/*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM0_MEM_RULE - Security access rules for RAM0 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT2 (2U) - -/*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT (0U) -/*! RAM1_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM1_MEM_RULE - Security access rules for RAM1 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT2 (2U) - -/*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U) -/*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM2_MEM_RULE - Security access rules for RAM2 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT2 (2U) - -/*! @name SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT (0U) -/*! RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM3_MEM_RULE - Security access rules for RAM3 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT2 (2U) - -/*! @name SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT (0U) -/*! RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM4_MEM_RULE - Security access rules for RAM4 slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U) -/*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U) -/*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U) -/*! SYSCON_RULE - System Configuration - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U) -/*! IOCON_RULE - I/O Configuration - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U) -/*! GINT0_RULE - GPIO input Interrupt 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U) -/*! GINT1_RULE - GPIO input Interrupt 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U) -/*! PINT_RULE - Pin Interrupt and Pattern match - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U) -/*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT (24U) -/*! INPUTMUX_RULE - Peripheral input multiplexing - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U) -/*! CTIMER0_RULE - Standard counter/Timer 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U) -/*! CTIMER1_RULE - Standard counter/Timer 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U) -/*! WWDT_RULE - Windiwed wtachdog Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U) -/*! MRT_RULE - Multi-rate Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U) -/*! UTICK_RULE - Micro-Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U) -/*! ANACTRL_RULE - Analog Modules controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U) -/*! PMC_RULE - Power Management Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U) -/*! SYSCTRL_RULE - System Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U) -/*! CTIMER2_RULE - Standard counter/Timer 2 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U) -/*! CTIMER3_RULE - Standard counter/Timer 3 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U) -/*! CTIMER4_RULE - Standard counter/Timer 4 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U) -/*! RTC_RULE - Real Time Counter - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U) -/*! OSEVENT_RULE - OS Event Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U) -/*! FLASH_CTRL_RULE - Flash Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U) -/*! PRINCE_RULE - Prince - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U) -/*! USBHPHY_RULE - USB High Speed Phy controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U) -/*! RNG_RULE - True Random Number Generator - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT (12U) -/*! PUF_RULE - PUF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U) -/*! PLU_RULE - Programmable Look-Up logic - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U) - -/*! @name SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT (8U) -/*! DMA0_RULE - DMA Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT (16U) -/*! FS_USB_DEV_RULE - USB Full-speed device - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT (20U) -/*! SCT_RULE - SCTimer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT (24U) -/*! FLEXCOMM0_RULE - Flexcomm interface 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT (28U) -/*! FLEXCOMM1_RULE - Flexcomm interface 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT (0U) -/*! FLEXCOMM2_RULE - Flexcomm interface 2 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT (4U) -/*! FLEXCOMM3_RULE - Flexcomm interface 3 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT (8U) -/*! FLEXCOMM4_RULE - Flexcomm interface 4 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT (12U) -/*! MAILBOX_RULE - Inter CPU communication Mailbox - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT (16U) -/*! GPIO0_RULE - High Speed GPIO - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT (16U) -/*! USB_HS_DEV_RULE - USB high Speed device registers - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT (20U) -/*! CRC_RULE - CRC engine - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT (24U) -/*! FLEXCOMM5_RULE - Flexcomm interface 5 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT (28U) -/*! FLEXCOMM6_RULE - Flexcomm interface 6 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT (0U) -/*! FLEXCOMM7_RULE - Flexcomm interface 7 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT (12U) -/*! SDIO_RULE - SDMMC card interface - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT (16U) -/*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT (28U) -/*! HS_LSPI_RULE - High Speed SPI - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB_PORT10_SLAVE0_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT (0U) -/*! ADC_RULE - ADC - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT (8U) -/*! USB_FS_HOST_RULE - USB Full Speed Host registers. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT (12U) -/*! USB_HS_HOST_RULE - USB High speed host registers - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT (16U) -/*! HASH_RULE - SHA-2 crypto registers - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT (20U) -/*! CASPER_RULE - RSA/ECC crypto accelerator - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT (24U) -/*! PQ_RULE - Power Quad (CPU0 processor hardware accelerator) - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT (28U) -/*! DMA1_RULE - DMA Controller (Secure) - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_COUNT (1U) - -/*! @name SEC_CTRL_AHB_PORT10_SLAVE1_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT (0U) -/*! GPIO1_RULE - Secure High Speed GPIO - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U) -/*! AHB_SEC_CTRL_RULE - AHB Secure Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_COUNT (1U) - -/*! @name SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U) -/*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U) -/*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U) -/*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U) -/*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U) -/*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U) -/*! SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U) -/*! SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U) -/*! SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK) - -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U) -/*! SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_VIO_ADDR - most recent security violation address for AHB port n */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) -/*! SEC_VIO_ADDR - security violation address for AHB port - */ -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */ -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (12U) - -/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB port n */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) -/*! SEC_VIO_INFO_WRITE - security violation access read/write indicator. - * 0b0..Read access. - * 0b1..Write access. - */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) -/*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator. - * 0b0..Code access. - * 0b1..Data access. - */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) -/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level - */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) -/*! SEC_VIO_INFO_MASTER - security violation master number - * 0b0000..CPU0 Code. - * 0b0001..CPU0 System. - * 0b0010..CPU1 Data. - * 0b0011..CPU1 System. - * 0b0100..USB-HS Device. - * 0b0101..SDMA0. - * 0b1000..SDIO. - * 0b1001..PowerQuad. - * 0b1010..HASH. - * 0b1011..USB-FS Host. - * 0b1100..SDMA1. - */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (12U) - -/*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) -/*! VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) -/*! VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) -/*! VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) -/*! VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) -/*! VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) -/*! VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) -/*! VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) -/*! VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) -/*! VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) -/*! VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U) -/*! VIO_INFO_VALID10 - violation information valid flag for AHB port 10. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK) - -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U) -/*! VIO_INFO_VALID11 - violation information valid flag for AHB port 11. Write 1 to clear. - * 0b0..Not valid. - * 0b1..Valid (violation occurred). - */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK) -/*! @} */ - -/*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U) -/*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U) -/*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U) -/*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U) -/*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U) -/*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U) -/*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U) -/*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U) -/*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U) -/*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U) -/*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U) -/*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U) -/*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U) -/*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U) -/*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U) -/*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U) -/*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U) -/*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U) -/*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U) -/*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U) -/*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U) -/*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U) -/*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U) -/*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U) -/*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U) -/*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U) -/*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U) -/*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U) -/*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U) -/*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U) -/*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U) -/*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U) -/*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK) -/*! @} */ - -/*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U) -/*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U) -/*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U) -/*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U) -/*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U) -/*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U) -/*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U) -/*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U) -/*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U) -/*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U) -/*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U) -/*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U) -/*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U) -/*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U) -/*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U) -/*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U) -/*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U) -/*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U) -/*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U) -/*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U) -/*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U) -/*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U) -/*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U) -/*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U) -/*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U) -/*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U) -/*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U) -/*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U) -/*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U) -/*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U) -/*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U) -/*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK) - -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U) -/*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31 - * 0b1..Pin state is readable by non-secure world. - * 0b0..Pin state is blocked to non-secure world. - */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK) -/*! @} */ - -/*! @name SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT (0U) -/*! SYS_IRQ - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT (1U) -/*! SDMA0_IRQ - System DMA 0 (non-secure) interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT (2U) -/*! GPIO_GLOBALINT0_IRQ - GPIO Group 0 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT (3U) -/*! GPIO_GLOBALINT1_IRQ - GPIO Group 1 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT (4U) -/*! GPIO_INT0_IRQ0 - Pin interrupt 0 or pattern match engine slice 0 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT (5U) -/*! GPIO_INT0_IRQ1 - Pin interrupt 1 or pattern match engine slice 1 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT (6U) -/*! GPIO_INT0_IRQ2 - Pin interrupt 2 or pattern match engine slice 2 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT (7U) -/*! GPIO_INT0_IRQ3 - Pin interrupt 3 or pattern match engine slice 3 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT (8U) -/*! UTICK_IRQ - Micro Tick Timer interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT (9U) -/*! MRT_IRQ - Multi-Rate Timer interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT (10U) -/*! CTIMER0_IRQ - Standard counter/timer 0 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT (11U) -/*! CTIMER1_IRQ - Standard counter/timer 1 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT (12U) -/*! SCT_IRQ - SCTimer/PWM interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT (13U) -/*! CTIMER3_IRQ - Standard counter/timer 3 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT (14U) -/*! FLEXCOMM0_IRQ - Flexcomm 0 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT (15U) -/*! FLEXCOMM1_IRQ - Flexcomm 1 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT (16U) -/*! FLEXCOMM2_IRQ - Flexcomm 2 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT (17U) -/*! FLEXCOMM3_IRQ - Flexcomm 3 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT (18U) -/*! FLEXCOMM4_IRQ - Flexcomm 4 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT (19U) -/*! FLEXCOMM5_IRQ - Flexcomm 5 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT (20U) -/*! FLEXCOMM6_IRQ - Flexcomm 6 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT (21U) -/*! FLEXCOMM7_IRQ - Flexcomm 7 interrupt (USART, SPI, I2C, I2S). - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT (22U) -/*! ADC_IRQ - General Purpose ADC interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT (23U) -/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT (24U) -/*! ACMP_IRQ - Analog Comparator interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT (25U) -/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT (26U) -/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT (27U) -/*! USB0_NEEDCLK - USB Full Speed Controller Clock request interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT (28U) -/*! USB0_IRQ - USB Full Speed Controller interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT (29U) -/*! RTC_IRQ - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT (30U) -/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT (31U) -/*! MAILBOX_IRQ - Mailbox interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK) -/*! @} */ - -/*! @name SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT (0U) -/*! GPIO_INT0_IRQ4 - Pin interrupt 4 or pattern match engine slice 4 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT (1U) -/*! GPIO_INT0_IRQ5 - Pin interrupt 5 or pattern match engine slice 5 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT (2U) -/*! GPIO_INT0_IRQ6 - Pin interrupt 6 or pattern match engine slice 6 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT (3U) -/*! GPIO_INT0_IRQ7 - Pin interrupt 7 or pattern match engine slice 7 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT (4U) -/*! CTIMER2_IRQ - Standard counter/timer 2 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT (5U) -/*! CTIMER4_IRQ - Standard counter/timer 4 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT (6U) -/*! OS_EVENT_TIMER_IRQ - OS Event Timer and OS Event Timer Wakeup interrupts - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT (7U) -/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT (8U) -/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT (9U) -/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT (10U) -/*! SDIO_IRQ - SDIO Controller interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT (11U) -/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT (12U) -/*! RESERVED4 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT (13U) -/*! RESERVED5 - Reserved. Read value is undefined, only zero should be written. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT (14U) -/*! USB1_PHY_IRQ - USB High Speed PHY Controller interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT (15U) -/*! USB1_IRQ - USB High Speed Controller interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT (16U) -/*! USB1_NEEDCLK - USB High Speed Controller Clock request interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT (17U) -/*! SEC_HYPERVISOR_CALL_IRQ - Secure fault Hyper Visor call interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT (18U) -/*! SEC_GPIO_INT0_IRQ0 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT (19U) -/*! SEC_GPIO_INT0_IRQ1 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT (20U) -/*! PLU_IRQ - Programmable Look-Up Controller interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT (21U) -/*! SEC_VIO_IRQ - Security Violation interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT (22U) -/*! SHA_IRQ - HASH-AES interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT (23U) -/*! CASPER_IRQ - CASPER interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT (24U) -/*! PUFKEY_IRQ - PUF interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT (25U) -/*! PQ_IRQ - Power Quad interrupt. - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT (26U) -/*! SDMA1_IRQ - System DMA 1 (Secure) interrupt - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK) - -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT (27U) -/*! LSPI_HS_IRQ - High Speed SPI interrupt - * 0b0.. - * 0b1.. - */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK) -/*! @} */ - -/*! @name SEC_MASK_LOCK - Security General Purpose register access control. */ -/*! @{ */ - -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) -/*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK) - -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) -/*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK) - -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (8U) -/*! SEC_CPU1_INT_MASK0_LOCK - SEC_CPU_INT_MASK0 register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK) - -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC00U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (10U) -/*! SEC_CPU1_INT_MASK1_LOCK - SEC_CPU_INT_MASK1 register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK) -/*! @} */ - -/*! @name MASTER_SEC_LEVEL - master secure level register */ -/*! @{ */ - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK (0x30U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT (4U) -/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK (0xC0U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT (6U) -/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U) -/*! USBFSD - USB Full Speed Device. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U) -/*! SDMA0 - System DMA 0. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK (0x30000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT (16U) -/*! SDIO - SDIO. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK (0xC0000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT (18U) -/*! PQ - Power Quad. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U) -/*! HASH - Hash. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U) -/*! USBFSH - USB Full speed Host. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U) -/*! SDMA1 - System DMA 1 security level. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) -/*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) -/*! @} */ - -/*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */ -/*! @{ */ - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK (0x30U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT (4U) -/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK (0xC0U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT (6U) -/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U) -/*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U) -/*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK (0x30000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT (16U) -/*! SDIO - SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0xC0000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (18U) -/*! PQ - Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U) -/*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U) -/*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U) -/*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) - * 0b11..Non-secure and Non-priviledge user access allowed. - * 0b10..Non-secure and Privilege access allowed. - * 0b01..Secure and Non-priviledge user access allowed. - * 0b00..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK) - -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) -/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) -/*! @} */ - -/*! @name CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) */ -/*! @{ */ - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) -/*! LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) -/*! LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) -/*! LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U) -/*! LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U) -/*! LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK) - -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT (30U) -/*! CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK) -/*! @} */ - -/*! @name CPU1_LOCK_REG - Miscalleneous control signals for in micro-Cortex M33 (CPU1) */ -/*! @{ */ - -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) -/*! LOCK_NS_VTOR - micro-Cortex M33 (CPU1) VTOR_NS register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK) - -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) -/*! LOCK_NS_MPU - micro-Cortex M33 (CPU1) non-secure MPU register write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK) - -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT (30U) -/*! CPU1_LOCK_REG_LOCK - CPU1_LOCK_REG write-lock. - * 0b10..Writable. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK) -/*! @} */ - -/*! @name MISC_CTRL_DP_REG - secure control duplicate register */ -/*! @{ */ - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) -/*! WRITE_LOCK - Write lock. - * 0b10..Secure control registers can be written. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) -/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. - * 0b10..Disable check. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) -/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. - * 0b10..Disable check. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) -/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. - * 0b10..Disable check. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) -/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. - * 0b10..Enable abort fort secure checker. - * 0b01..Disable abort fort secure checker. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) -/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. - * 0b10..Simple master in strict mode. - * 0b01..Simple master in tier mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) -/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. - * 0b10..Smart master in strict mode. - * 0b01..Smart master in tier mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) -/*! IDAU_ALL_NS - Disable IDAU. - * 0b10..IDAU is enabled. - * 0b01..IDAU is disable. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) -/*! @} */ - -/*! @name MISC_CTRL_REG - secure control register */ -/*! @{ */ - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) -/*! WRITE_LOCK - Write lock. - * 0b10..Secure control registers can be written. - * 0b01..Restricted mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) -/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. - * 0b10..Disable check. - * 0b01..Enabled (restricted mode) - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) -/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. - * 0b10..Disable check. - * 0b01..Enabled (restricted mode) - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) -/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. - * 0b10..Disable check. - * 0b01..Enabled (restricted mode) - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) -/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. - * 0b10..Enable abort fort secure checker. - * 0b01..Disable abort fort secure checker. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) -/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. - * 0b10..Simple master in strict mode. - * 0b01..Simple master in tier mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) -/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. - * 0b10..Smart master in strict mode. - * 0b01..Smart master in tier mode. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) - -#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) -/*! IDAU_ALL_NS - Disable IDAU. - * 0b10..IDAU is enabled. - * 0b01..IDAU is disable. - */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group AHB_SECURE_CTRL_Register_Masks */ - - -/* AHB_SECURE_CTRL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral AHB_SECURE_CTRL base address */ - #define AHB_SECURE_CTRL_BASE (0x500AC000u) - /** Peripheral AHB_SECURE_CTRL base address */ - #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u) - /** Peripheral AHB_SECURE_CTRL base pointer */ - #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) - /** Peripheral AHB_SECURE_CTRL base pointer */ - #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS) - /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ - #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } - /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ - #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } - /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ - #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS } - /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ - #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS } -#else - /** Peripheral AHB_SECURE_CTRL base address */ - #define AHB_SECURE_CTRL_BASE (0x400AC000u) - /** Peripheral AHB_SECURE_CTRL base pointer */ - #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) - /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ - #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } - /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ - #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } -#endif - -/*! - * @} - */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ANACTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer - * @{ - */ - -/** ANACTRL - Register Layout Typedef */ -typedef struct { - __IO uint32_t ANALOG_CTRL_CFG; /**< Various Analog blocks configuration (like FRO 192MHz trimmings source ...), offset: 0x0 */ - __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */ - __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */ - __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */ - __IO uint32_t ADC_CTRL; /**< General Purpose ADC VBAT Divider branch control, offset: 0x18 */ - uint8_t RESERVED_1[4]; - __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */ - __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status register, offset: 0x24 */ - uint8_t RESERVED_2[8]; - __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */ - __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */ - uint8_t RESERVED_3[8]; - __IO uint32_t RINGO0_CTRL; /**< First Ring Oscillator module control register., offset: 0x40 */ - __IO uint32_t RINGO1_CTRL; /**< Second Ring Oscillator module control register., offset: 0x44 */ - __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */ - uint8_t RESERVED_4[100]; - __IO uint32_t LDO_XO32M; /**< High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register, offset: 0xB0 */ - __IO uint32_t AUX_BIAS; /**< AUX_BIAS, offset: 0xB4 */ - uint8_t RESERVED_5[72]; - __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */ - __IO uint32_t USBHS_PHY_TRIM; /**< USB High Speed Phy Trim values, offset: 0x104 */ -} ANACTRL_Type; - -/* ---------------------------------------------------------------------------- - -- ANACTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks - * @{ - */ - -/*! @name ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) */ -/*! @{ */ - -#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK (0x1U) -#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT (0U) -/*! FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source. - * 0b0..FRO192M trimming and 'Enable' comes from eFUSE. - * 0b1..FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers. - */ -#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT)) & ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK) -/*! @} */ - -/*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */ -/*! @{ */ - -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U) -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U) -/*! FLASH_PWRDWN - Flash Power Down status. - * 0b0..Flash is not in power down mode. - * 0b1..Flash is in power down mode. - */ -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK) - -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U) -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U) -/*! FLASH_INIT_ERROR - Flash initialization error status. - * 0b0..No error. - * 0b1..At least one error occured during flash initialization.. - */ -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK) -/*! @} */ - -/*! @name FREQ_ME_CTRL - Frequency Measure function control register */ -/*! @{ */ - -#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU) -#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U) -/*! CAPVAL_SCALE - Frequency measure result /Frequency measur scale - */ -#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK) - -#define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U) -#define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U) -/*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit - * when the measurement cycle has completed and there is valid capture data in the CAPVAL field - * (bits 30:0). - */ -#define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK) -/*! @} */ - -/*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */ -/*! @{ */ - -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U) -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U) -/*! ENA_12MHZCLK - 12 MHz clock control. - * 0b0..12 MHz clock is disabled. - * 0b1..12 MHz clock is enabled. - */ -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) - -#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK (0x8000U) -#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT (15U) -/*! ENA_48MHZCLK - 48 MHz clock control. - * 0b0..Reserved. - * 0b1..48 MHz clock is enabled. - */ -#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK) - -#define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U) -#define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U) -/*! DAC_TRIM - Frequency trim. - */ -#define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK) - -#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U) -#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U) -/*! USBCLKADJ - If this bit is set and the USB peripheral is enabled into full speed device mode, - * the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF - * packets. - */ -#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK) - -#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U) -#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U) -/*! USBMODCHG - If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0. - */ -#define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK) - -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U) -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U) -/*! ENA_96MHZCLK - 96 MHz clock control. - * 0b0..96 MHz clock is disabled. - * 0b1..96 MHz clock is enabled. - */ -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) - -#define ANACTRL_FRO192M_CTRL_WRTRIM_MASK (0x80000000U) -#define ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT (31U) -/*! WRTRIM - This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields. - */ -#define ANACTRL_FRO192M_CTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_WRTRIM_MASK) -/*! @} */ - -/*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */ -/*! @{ */ - -#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U) -#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U) -/*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. - * 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). - * 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by - * FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). - */ -#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK) - -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U) -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U) -/*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses - * the threshold voltage of a SLVT transistor, this output signal will go high. It is also - * possible to observe the clk_valid signal. - */ -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK) -/*! @} */ - -/*! @name ADC_CTRL - General Purpose ADC VBAT Divider branch control */ -/*! @{ */ - -#define ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK (0x1U) -#define ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT (0U) -/*! VBATDIVENABLE - Switch On/Off VBAT divider branch. - * 0b0..VBAT divider branch is disabled. - * 0b1..VBAT divider branch is enabled. - */ -#define ANACTRL_ADC_CTRL_VBATDIVENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT)) & ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK) -/*! @} */ - -/*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */ -/*! @{ */ - -#define ANACTRL_XO32M_CTRL_SLAVE_MASK (0x10U) -#define ANACTRL_XO32M_CTRL_SLAVE_SHIFT (4U) -/*! SLAVE - Xo in slave mode. - */ -#define ANACTRL_XO32M_CTRL_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_SLAVE_SHIFT)) & ANACTRL_XO32M_CTRL_SLAVE_MASK) - -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK (0x7F00U) -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT (8U) -/*! OSC_CAP_IN - Tune capa banks of High speed Crystal Oscillator input pin - */ -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK) - -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK (0x3F8000U) -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT (15U) -/*! OSC_CAP_OUT - Tune capa banks of High speed Crystal Oscillator output pin - */ -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK) - -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U) -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U) -/*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. - * 0b0..XO AC buffer bypass is disabled. - * 0b1..XO AC buffer bypass is enabled. - */ -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK) - -#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U) -#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U) -/*! ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL. - * 0b0..High speed Crystal oscillator output to USB HS PLL is disabled. - * 0b1..High speed Crystal oscillator output to USB HS PLL is enabled. - */ -#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) - -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U) -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U) -/*! ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system. - * 0b0..High speed Crystal oscillator output to CPU system is disabled. - * 0b1..High speed Crystal oscillator output to CPU system is enabled. - */ -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) -/*! @} */ - -/*! @name XO32M_STATUS - High speed Crystal Oscillator Status register */ -/*! @{ */ - -#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U) -#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U) -/*! XO_READY - Indicates XO out frequency statibilty. - * 0b0..XO output frequency is not yet stable. - * 0b1..XO output frequency is stable. - */ -#define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK) -/*! @} */ - -/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */ -/*! @{ */ - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U) -/*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control. - * 0b0..BOD VBAT interrupt is disabled. - * 0b1..BOD VBAT interrupt is enabled. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U) -/*! BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U) -/*! BODCORE_INT_ENABLE - BOD CORE interrupt control. - * 0b0..BOD CORE interrupt is disabled. - * 0b1..BOD CORE interrupt is enabled. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U) -/*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U) -/*! DCDC_INT_ENABLE - DCDC interrupt control. - * 0b0..DCDC interrupt is disabled. - * 0b1..DCDC interrupt is enabled. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK) - -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U) -/*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK) -/*! @} */ - -/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */ -/*! @{ */ - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U) -/*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U) -/*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U) -/*! BODVBAT_VAL - Current value of BOD VBAT power status output. - * 0b0..VBAT voltage level is below the threshold. - * 0b1..VBAT voltage level is above the threshold. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U) -/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U) -/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U) -/*! BODCORE_VAL - Current value of BOD CORE power status output. - * 0b0..CORE voltage level is below the threshold. - * 0b1..CORE voltage level is above the threshold. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U) -/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U) -/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK) - -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U) -/*! DCDC_VAL - Current value of DCDC power status output. - * 0b0..DCDC output Voltage is below the targeted regulation level. - * 0b1..DCDC output Voltage is above the targeted regulation level. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK) -/*! @} */ - -/*! @name RINGO0_CTRL - First Ring Oscillator module control register. */ -/*! @{ */ - -#define ANACTRL_RINGO0_CTRL_SL_MASK (0x1U) -#define ANACTRL_RINGO0_CTRL_SL_SHIFT (0U) -/*! SL - Select short or long ringo (for all ringos types). - * 0b0..Select short ringo (few elements). - * 0b1..Select long ringo (many elements). - */ -#define ANACTRL_RINGO0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK) - -#define ANACTRL_RINGO0_CTRL_FS_MASK (0x2U) -#define ANACTRL_RINGO0_CTRL_FS_SHIFT (1U) -/*! FS - Ringo frequency output divider. - * 0b0..High frequency output (frequency lower than 100 MHz). - * 0b1..Low frequency output (frequency lower than 10 MHz). - */ -#define ANACTRL_RINGO0_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK) - -#define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK (0xCU) -#define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT (2U) -/*! SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control. - * 0b00..Normal mode. - * 0b01..P-Monitor mode. Measure with weak P transistor. - * 0b10..P-Monitor mode. Measure with weak N transistor. - * 0b11..Don't use. - */ -#define ANACTRL_RINGO0_CTRL_SWN_SWP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK) - -#define ANACTRL_RINGO0_CTRL_PD_MASK (0x10U) -#define ANACTRL_RINGO0_CTRL_PD_SHIFT (4U) -/*! PD - Ringo module Power control. - * 0b0..The Ringo module is enabled. - * 0b1..The Ringo module is disabled. - */ -#define ANACTRL_RINGO0_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK) - -#define ANACTRL_RINGO0_CTRL_E_ND0_MASK (0x20U) -#define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT (5U) -/*! E_ND0 - First NAND2-based ringo control. - * 0b0..First NAND2-based ringo is disabled. - * 0b1..First NAND2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_ND0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK) - -#define ANACTRL_RINGO0_CTRL_E_ND1_MASK (0x40U) -#define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT (6U) -/*! E_ND1 - Second NAND2-based ringo control. - * 0b0..Second NAND2-based ringo is disabled. - * 0b1..Second NAND2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_ND1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK) - -#define ANACTRL_RINGO0_CTRL_E_NR0_MASK (0x80U) -#define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT (7U) -/*! E_NR0 - First NOR2-based ringo control. - * 0b0..First NOR2-based ringo is disabled. - * 0b1..First NOR2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_NR0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK) - -#define ANACTRL_RINGO0_CTRL_E_NR1_MASK (0x100U) -#define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT (8U) -/*! E_NR1 - Second NOR2-based ringo control. - * 0b0..Second NORD2-based ringo is disabled. - * 0b1..Second NORD2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_NR1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK) - -#define ANACTRL_RINGO0_CTRL_E_IV0_MASK (0x200U) -#define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT (9U) -/*! E_IV0 - First Inverter-based ringo control. - * 0b0..First INV-based ringo is disabled. - * 0b1..First INV-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_IV0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK) - -#define ANACTRL_RINGO0_CTRL_E_IV1_MASK (0x400U) -#define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT (10U) -/*! E_IV1 - Second Inverter-based ringo control. - * 0b0..Second INV-based ringo is disabled. - * 0b1..Second INV-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_IV1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK) - -#define ANACTRL_RINGO0_CTRL_E_PN0_MASK (0x800U) -#define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT (11U) -/*! E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control. - * 0b0..First PN-based ringo is disabled. - * 0b1..First PN-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_PN0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK) - -#define ANACTRL_RINGO0_CTRL_E_PN1_MASK (0x1000U) -#define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT (12U) -/*! E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control. - * 0b0..Second PN-based ringo is disabled. - * 0b1..Second PN-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_PN1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK) - -#define ANACTRL_RINGO0_CTRL_DIVISOR_MASK (0xF0000U) -#define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT (16U) -/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) - */ -#define ANACTRL_RINGO0_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK) - -#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) -#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT (31U) -/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider - * value, cleared when the change is complete. - */ -#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK) -/*! @} */ - -/*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */ -/*! @{ */ - -#define ANACTRL_RINGO1_CTRL_S_MASK (0x1U) -#define ANACTRL_RINGO1_CTRL_S_SHIFT (0U) -/*! S - Select short or long ringo (for all ringos types). - * 0b0..Select short ringo (few elements). - * 0b1..Select long ringo (many elements). - */ -#define ANACTRL_RINGO1_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK) - -#define ANACTRL_RINGO1_CTRL_FS_MASK (0x2U) -#define ANACTRL_RINGO1_CTRL_FS_SHIFT (1U) -/*! FS - Ringo frequency output divider. - * 0b0..High frequency output (frequency lower than 100 MHz). - * 0b1..Low frequency output (frequency lower than 10 MHz). - */ -#define ANACTRL_RINGO1_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK) - -#define ANACTRL_RINGO1_CTRL_PD_MASK (0x4U) -#define ANACTRL_RINGO1_CTRL_PD_SHIFT (2U) -/*! PD - Ringo module Power control. - * 0b0..The Ringo module is enabled. - * 0b1..The Ringo module is disabled. - */ -#define ANACTRL_RINGO1_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK) - -#define ANACTRL_RINGO1_CTRL_E_R24_MASK (0x8U) -#define ANACTRL_RINGO1_CTRL_E_R24_SHIFT (3U) -/*! E_R24 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK) - -#define ANACTRL_RINGO1_CTRL_E_R35_MASK (0x10U) -#define ANACTRL_RINGO1_CTRL_E_R35_SHIFT (4U) -/*! E_R35 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK) - -#define ANACTRL_RINGO1_CTRL_E_M2_MASK (0x20U) -#define ANACTRL_RINGO1_CTRL_E_M2_SHIFT (5U) -/*! E_M2 - Metal 2 (M2) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK) - -#define ANACTRL_RINGO1_CTRL_E_M3_MASK (0x40U) -#define ANACTRL_RINGO1_CTRL_E_M3_SHIFT (6U) -/*! E_M3 - Metal 3 (M3) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK) - -#define ANACTRL_RINGO1_CTRL_E_M4_MASK (0x80U) -#define ANACTRL_RINGO1_CTRL_E_M4_SHIFT (7U) -/*! E_M4 - Metal 4 (M4) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK) - -#define ANACTRL_RINGO1_CTRL_E_M5_MASK (0x100U) -#define ANACTRL_RINGO1_CTRL_E_M5_SHIFT (8U) -/*! E_M5 - Metal 5 (M5) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK) - -#define ANACTRL_RINGO1_CTRL_DIVISOR_MASK (0xF0000U) -#define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT (16U) -/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) - */ -#define ANACTRL_RINGO1_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK) - -#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) -#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT (31U) -/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider - * value, cleared when the change is complete. - */ -#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK) -/*! @} */ - -/*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */ -/*! @{ */ - -#define ANACTRL_RINGO2_CTRL_S_MASK (0x1U) -#define ANACTRL_RINGO2_CTRL_S_SHIFT (0U) -/*! S - Select short or long ringo (for all ringos types). - * 0b0..Select short ringo (few elements). - * 0b1..Select long ringo (many elements). - */ -#define ANACTRL_RINGO2_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK) - -#define ANACTRL_RINGO2_CTRL_FS_MASK (0x2U) -#define ANACTRL_RINGO2_CTRL_FS_SHIFT (1U) -/*! FS - Ringo frequency output divider. - * 0b0..High frequency output (frequency lower than 100 MHz). - * 0b1..Low frequency output (frequency lower than 10 MHz). - */ -#define ANACTRL_RINGO2_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK) - -#define ANACTRL_RINGO2_CTRL_PD_MASK (0x4U) -#define ANACTRL_RINGO2_CTRL_PD_SHIFT (2U) -/*! PD - Ringo module Power control. - * 0b0..The Ringo module is enabled. - * 0b1..The Ringo module is disabled. - */ -#define ANACTRL_RINGO2_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK) - -#define ANACTRL_RINGO2_CTRL_E_R24_MASK (0x8U) -#define ANACTRL_RINGO2_CTRL_E_R24_SHIFT (3U) -/*! E_R24 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK) - -#define ANACTRL_RINGO2_CTRL_E_R35_MASK (0x10U) -#define ANACTRL_RINGO2_CTRL_E_R35_SHIFT (4U) -/*! E_R35 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK) - -#define ANACTRL_RINGO2_CTRL_E_M2_MASK (0x20U) -#define ANACTRL_RINGO2_CTRL_E_M2_SHIFT (5U) -/*! E_M2 - Metal 2 (M2) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK) - -#define ANACTRL_RINGO2_CTRL_E_M3_MASK (0x40U) -#define ANACTRL_RINGO2_CTRL_E_M3_SHIFT (6U) -/*! E_M3 - Metal 3 (M3) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK) - -#define ANACTRL_RINGO2_CTRL_E_M4_MASK (0x80U) -#define ANACTRL_RINGO2_CTRL_E_M4_SHIFT (7U) -/*! E_M4 - Metal 4 (M4) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK) - -#define ANACTRL_RINGO2_CTRL_E_M5_MASK (0x100U) -#define ANACTRL_RINGO2_CTRL_E_M5_SHIFT (8U) -/*! E_M5 - Metal 5 (M5) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK) - -#define ANACTRL_RINGO2_CTRL_DIVISOR_MASK (0xF0000U) -#define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT (16U) -/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) - */ -#define ANACTRL_RINGO2_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK) - -#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) -#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT (31U) -/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider - * value, cleared when the change is complete. - */ -#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK) -/*! @} */ - -/*! @name LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register */ -/*! @{ */ - -#define ANACTRL_LDO_XO32M_BYPASS_MASK (0x2U) -#define ANACTRL_LDO_XO32M_BYPASS_SHIFT (1U) -/*! BYPASS - Activate LDO bypass. - * 0b0..Disable bypass mode (for normal operations). - * 0b1..Activate LDO bypass. - */ -#define ANACTRL_LDO_XO32M_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_BYPASS_SHIFT)) & ANACTRL_LDO_XO32M_BYPASS_MASK) - -#define ANACTRL_LDO_XO32M_HIGHZ_MASK (0x4U) -#define ANACTRL_LDO_XO32M_HIGHZ_SHIFT (2U) -/*! HIGHZ - . - * 0b0..Output in High normal state. - * 0b1..Output in High Impedance state. - */ -#define ANACTRL_LDO_XO32M_HIGHZ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_HIGHZ_SHIFT)) & ANACTRL_LDO_XO32M_HIGHZ_MASK) - -#define ANACTRL_LDO_XO32M_VOUT_MASK (0x38U) -#define ANACTRL_LDO_XO32M_VOUT_SHIFT (3U) -/*! VOUT - Sets the LDO output level. - * 0b000..0.750 V. - * 0b001..0.775 V. - * 0b010..0.800 V. - * 0b011..0.825 V. - * 0b100..0.850 V. - * 0b101..0.875 V. - * 0b110..0.900 V. - * 0b111..0.925 V. - */ -#define ANACTRL_LDO_XO32M_VOUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_VOUT_SHIFT)) & ANACTRL_LDO_XO32M_VOUT_MASK) - -#define ANACTRL_LDO_XO32M_IBIAS_MASK (0xC0U) -#define ANACTRL_LDO_XO32M_IBIAS_SHIFT (6U) -/*! IBIAS - Adjust the biasing current. - */ -#define ANACTRL_LDO_XO32M_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_IBIAS_SHIFT)) & ANACTRL_LDO_XO32M_IBIAS_MASK) - -#define ANACTRL_LDO_XO32M_STABMODE_MASK (0x300U) -#define ANACTRL_LDO_XO32M_STABMODE_SHIFT (8U) -/*! STABMODE - Stability configuration. - */ -#define ANACTRL_LDO_XO32M_STABMODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_STABMODE_SHIFT)) & ANACTRL_LDO_XO32M_STABMODE_MASK) -/*! @} */ - -/*! @name AUX_BIAS - AUX_BIAS */ -/*! @{ */ - -#define ANACTRL_AUX_BIAS_VREF1VENABLE_MASK (0x2U) -#define ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT (1U) -/*! VREF1VENABLE - Control output of 1V reference voltage. - * 0b0..Output of 1V reference voltage buffer is bypassed. - * 0b1..Output of 1V reference voltage is enabled. - */ -#define ANACTRL_AUX_BIAS_VREF1VENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VENABLE_MASK) - -#define ANACTRL_AUX_BIAS_ITRIM_MASK (0x7CU) -#define ANACTRL_AUX_BIAS_ITRIM_SHIFT (2U) -/*! ITRIM - current trimming control word. - */ -#define ANACTRL_AUX_BIAS_ITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIM_SHIFT)) & ANACTRL_AUX_BIAS_ITRIM_MASK) - -#define ANACTRL_AUX_BIAS_PTATITRIM_MASK (0xF80U) -#define ANACTRL_AUX_BIAS_PTATITRIM_SHIFT (7U) -/*! PTATITRIM - current trimming control word for ptat current. - */ -#define ANACTRL_AUX_BIAS_PTATITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_PTATITRIM_SHIFT)) & ANACTRL_AUX_BIAS_PTATITRIM_MASK) - -#define ANACTRL_AUX_BIAS_VREF1VTRIM_MASK (0x1F000U) -#define ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT (12U) -/*! VREF1VTRIM - voltage trimming control word. - */ -#define ANACTRL_AUX_BIAS_VREF1VTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VTRIM_MASK) - -#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK (0xE0000U) -#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT (17U) -/*! VREF1VCURVETRIM - Control bit to configure trimming state of mirror. - */ -#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK) - -#define ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK (0x100000U) -#define ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT (20U) -/*! ITRIMCTRL0 - Control bit to configure trimming state of mirror. - */ -#define ANACTRL_AUX_BIAS_ITRIMCTRL0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK) - -#define ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK (0x200000U) -#define ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT (21U) -/*! ITRIMCTRL1 - Control bit to configure trimming state of mirror. - */ -#define ANACTRL_AUX_BIAS_ITRIMCTRL1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK) -/*! @} */ - -/*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */ -/*! @{ */ - -#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK (0x1U) -#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT (0U) -/*! usb_vbusvalid_ext - Override value for Vbus if using external detectors. - */ -#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK) - -#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK (0x2U) -#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT (1U) -/*! usb_id_ext - Override value for ID if using external detectors. - */ -#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK) -/*! @} */ - -/*! @name USBHS_PHY_TRIM - USB High Speed Phy Trim values */ -/*! @{ */ - -#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK (0x3U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT (0U) -/*! trim_usb_reg_env_tail_adj_vd - Adjusts time constant of HS RX squelch (envelope) comparator. - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK (0x3CU) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT (2U) -/*! trim_usbphy_tx_d_cal - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK (0x7C0U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT (6U) -/*! trim_usbphy_tx_cal45dp - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK (0xF800U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT (11U) -/*! trim_usbphy_tx_cal45dm - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK (0x30000U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT (16U) -/*! trim_usb2_refbias_tst - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK (0x1C0000U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT (18U) -/*! trim_usb2_refbias_vbgadj - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK) - -#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK (0xE00000U) -#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT (21U) -/*! trim_pll_ctrl0_div_sel - . - */ -#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ANACTRL_Register_Masks */ - - -/* ANACTRL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE (0x50013000u) - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE_NS (0x40013000u) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS) - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS { ANACTRL } - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS } -#else - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE (0x40013000u) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS { ANACTRL } -#endif - -/*! - * @} - */ /* end of group ANACTRL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CASPER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CASPER_Peripheral_Access_Layer CASPER Peripheral Access Layer - * @{ - */ - -/** CASPER - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL0; /**< Contains the offsets of AB and CD in the RAM., offset: 0x0 */ - __IO uint32_t CTRL1; /**< Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR., offset: 0x4 */ - __IO uint32_t LOADER; /**< Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations., offset: 0x8 */ - __IO uint32_t STATUS; /**< Indicates operational status and would contain the carry bit if used., offset: 0xC */ - __IO uint32_t INTENSET; /**< Sets interrupts, offset: 0x10 */ - __IO uint32_t INTENCLR; /**< Clears interrupts, offset: 0x14 */ - __I uint32_t INTSTAT; /**< Interrupt status bits (mask of INTENSET and STATUS), offset: 0x18 */ - uint8_t RESERVED_0[4]; - __IO uint32_t AREG; /**< A register, offset: 0x20 */ - __IO uint32_t BREG; /**< B register, offset: 0x24 */ - __IO uint32_t CREG; /**< C register, offset: 0x28 */ - __IO uint32_t DREG; /**< D register, offset: 0x2C */ - __IO uint32_t RES0; /**< Result register 0, offset: 0x30 */ - __IO uint32_t RES1; /**< Result register 1, offset: 0x34 */ - __IO uint32_t RES2; /**< Result register 2, offset: 0x38 */ - __IO uint32_t RES3; /**< Result register 3, offset: 0x3C */ - uint8_t RESERVED_1[32]; - __IO uint32_t MASK; /**< Optional mask register, offset: 0x60 */ - __IO uint32_t REMASK; /**< Optional re-mask register, offset: 0x64 */ - uint8_t RESERVED_2[24]; - __IO uint32_t LOCK; /**< Security lock register, offset: 0x80 */ -} CASPER_Type; - -/* ---------------------------------------------------------------------------- - -- CASPER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CASPER_Register_Masks CASPER Register Masks - * @{ - */ - -/*! @name CTRL0 - Contains the offsets of AB and CD in the RAM. */ -/*! @{ */ - -#define CASPER_CTRL0_ABBPAIR_MASK (0x1U) -#define CASPER_CTRL0_ABBPAIR_SHIFT (0U) -/*! ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_CTRL0_ABBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK) - -#define CASPER_CTRL0_ABOFF_MASK (0x1FFCU) -#define CASPER_CTRL0_ABOFF_SHIFT (2U) -/*! ABOFF - Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code - * sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed - * if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up - */ -#define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK) - -#define CASPER_CTRL0_CDBPAIR_MASK (0x10000U) -#define CASPER_CTRL0_CDBPAIR_SHIFT (16U) -/*! CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_CTRL0_CDBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK) - -#define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U) -#define CASPER_CTRL0_CDOFF_SHIFT (18U) -/*! CDOFF - Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees - * (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 - * bit operation. Ideally not in the same RAM as the AB values - */ -#define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK) -/*! @} */ - -/*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */ -/*! @{ */ - -#define CASPER_CTRL1_ITER_MASK (0xFFU) -#define CASPER_CTRL1_ITER_SHIFT (0U) -/*! ITER - Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate. - */ -#define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK) - -#define CASPER_CTRL1_MODE_MASK (0xFF00U) -#define CASPER_CTRL1_MODE_SHIFT (8U) -/*! MODE - Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active. - */ -#define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK) - -#define CASPER_CTRL1_RESBPAIR_MASK (0x10000U) -#define CASPER_CTRL1_RESBPAIR_SHIFT (16U) -/*! RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally - * this is not the same bank as ABBPAIR (when 4-up supported) - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_CTRL1_RESBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK) - -#define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U) -#define CASPER_CTRL1_RESOFF_SHIFT (18U) -/*! RESOFF - Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally - * not in the same RAM as the AB and CD values - */ -#define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK) - -#define CASPER_CTRL1_CSKIP_MASK (0xC0000000U) -#define CASPER_CTRL1_CSKIP_SHIFT (30U) -/*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: - * 0b00..No Skip - * 0b01..Skip if Carry is 1 - * 0b10..Skip if Carry is 0 - * 0b11..Set CTRLOFF to CDOFF and Skip - */ -#define CASPER_CTRL1_CSKIP(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK) -/*! @} */ - -/*! @name LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. */ -/*! @{ */ - -#define CASPER_LOADER_COUNT_MASK (0xFFU) -#define CASPER_LOADER_COUNT_SHIFT (0U) -/*! COUNT - Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one - * op - does not iterate, write N means N control pairs to load - */ -#define CASPER_LOADER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK) - -#define CASPER_LOADER_CTRLBPAIR_MASK (0x10000U) -#define CASPER_LOADER_CTRLBPAIR_SHIFT (16U) -/*! CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not - * matter which bank is used as this is loaded when not performing an operation. - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_LOADER_CTRLBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK) - -#define CASPER_LOADER_CTRLOFF_MASK (0x1FFC0000U) -#define CASPER_LOADER_CTRLOFF_SHIFT (18U) -/*! CTRLOFF - DWord Offset of CTRL pair to load next. - */ -#define CASPER_LOADER_CTRLOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK) -/*! @} */ - -/*! @name STATUS - Indicates operational status and would contain the carry bit if used. */ -/*! @{ */ - -#define CASPER_STATUS_DONE_MASK (0x1U) -#define CASPER_STATUS_DONE_SHIFT (0U) -/*! DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. - * 0b0..Busy or just cleared - * 0b1..Completed last operation - */ -#define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK) - -#define CASPER_STATUS_CARRY_MASK (0x10U) -#define CASPER_STATUS_CARRY_SHIFT (4U) -/*! CARRY - Last carry value if operation produced a carry bit - * 0b0..Carry was 0 or no carry - * 0b1..Carry was 1 - */ -#define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK) - -#define CASPER_STATUS_BUSY_MASK (0x20U) -#define CASPER_STATUS_BUSY_SHIFT (5U) -/*! BUSY - Indicates if the accelerator is busy performing an operation - * 0b0..Not busy - is idle - * 0b1..Is busy - */ -#define CASPER_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK) -/*! @} */ - -/*! @name INTENSET - Sets interrupts */ -/*! @{ */ - -#define CASPER_INTENSET_DONE_MASK (0x1U) -#define CASPER_INTENSET_DONE_SHIFT (0U) -/*! DONE - Set if the accelerator should interrupt when done. - * 0b0..Do not interrupt when done - * 0b1..Interrupt when done - */ -#define CASPER_INTENSET_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK) -/*! @} */ - -/*! @name INTENCLR - Clears interrupts */ -/*! @{ */ - -#define CASPER_INTENCLR_DONE_MASK (0x1U) -#define CASPER_INTENCLR_DONE_SHIFT (0U) -/*! DONE - Written to clear an interrupt set with INTENSET. - * 0b0..If written 0, ignored - * 0b1..If written 1, do not Interrupt when done - */ -#define CASPER_INTENCLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) */ -/*! @{ */ - -#define CASPER_INTSTAT_DONE_MASK (0x1U) -#define CASPER_INTSTAT_DONE_SHIFT (0U) -/*! DONE - If set, interrupt is caused by accelerator being done. - * 0b0..Not caused by accelerator being done - * 0b1..Caused by accelerator being done - */ -#define CASPER_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK) -/*! @} */ - -/*! @name AREG - A register */ -/*! @{ */ - -#define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_AREG_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, - * but is available when accelerator not busy. - */ -#define CASPER_AREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name BREG - B register */ -/*! @{ */ - -#define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_BREG_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, - * but is available when accelerator not busy. - */ -#define CASPER_BREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name CREG - C register */ -/*! @{ */ - -#define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_CREG_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, - * but is available when accelerator not busy. - */ -#define CASPER_CREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name DREG - D register */ -/*! @{ */ - -#define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_DREG_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, - * but is available when accelerator not busy. - */ -#define CASPER_DREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES0 - Result register 0 */ -/*! @{ */ - -#define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES0_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally - * written or read by application, but is available when accelerator not busy. - */ -#define CASPER_RES0_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES1 - Result register 1 */ -/*! @{ */ - -#define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES1_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally - * written or read by application, but is available when accelerator not busy. - */ -#define CASPER_RES1_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES2 - Result register 2 */ -/*! @{ */ - -#define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES2_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally - * written or read by application, but is available when accelerator not busy. - */ -#define CASPER_RES2_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES3 - Result register 3 */ -/*! @{ */ - -#define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES3_REG_VALUE_SHIFT (0U) -/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally - * written or read by application, but is available when accelerator not busy. - */ -#define CASPER_RES3_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK) -/*! @} */ - -/*! @name MASK - Optional mask register */ -/*! @{ */ - -#define CASPER_MASK_MASK_MASK (0xFFFFFFFFU) -#define CASPER_MASK_MASK_SHIFT (0U) -/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values - */ -#define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK) -/*! @} */ - -/*! @name REMASK - Optional re-mask register */ -/*! @{ */ - -#define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU) -#define CASPER_REMASK_MASK_SHIFT (0U) -/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values - */ -#define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK) -/*! @} */ - -/*! @name LOCK - Security lock register */ -/*! @{ */ - -#define CASPER_LOCK_LOCK_MASK (0x1U) -#define CASPER_LOCK_LOCK_SHIFT (0U) -/*! LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. - * 0b0..unlock - * 0b1..Lock to current security level - */ -#define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK) - -#define CASPER_LOCK_KEY_MASK (0x1FFF0U) -#define CASPER_LOCK_KEY_SHIFT (4U) -/*! KEY - Must be written as 0x73D to change the register. - * 0b0011100111101..If set during write, will allow lock or unlock - */ -#define CASPER_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CASPER_Register_Masks */ - - -/* CASPER - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CASPER base address */ - #define CASPER_BASE (0x500A5000u) - /** Peripheral CASPER base address */ - #define CASPER_BASE_NS (0x400A5000u) - /** Peripheral CASPER base pointer */ - #define CASPER ((CASPER_Type *)CASPER_BASE) - /** Peripheral CASPER base pointer */ - #define CASPER_NS ((CASPER_Type *)CASPER_BASE_NS) - /** Array initializer of CASPER peripheral base addresses */ - #define CASPER_BASE_ADDRS { CASPER_BASE } - /** Array initializer of CASPER peripheral base pointers */ - #define CASPER_BASE_PTRS { CASPER } - /** Array initializer of CASPER peripheral base addresses */ - #define CASPER_BASE_ADDRS_NS { CASPER_BASE_NS } - /** Array initializer of CASPER peripheral base pointers */ - #define CASPER_BASE_PTRS_NS { CASPER_NS } -#else - /** Peripheral CASPER base address */ - #define CASPER_BASE (0x400A5000u) - /** Peripheral CASPER base pointer */ - #define CASPER ((CASPER_Type *)CASPER_BASE) - /** Array initializer of CASPER peripheral base addresses */ - #define CASPER_BASE_ADDRS { CASPER_BASE } - /** Array initializer of CASPER peripheral base pointers */ - #define CASPER_BASE_PTRS { CASPER } -#endif -/** Interrupt vectors for the CASPER peripheral type */ -#define CASPER_IRQS { CASER_IRQn } - -/*! - * @} - */ /* end of group CASPER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CRC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer - * @{ - */ - -/** CRC - Register Layout Typedef */ -typedef struct { - __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ - __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ - union { /* offset: 0x8 */ - __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ - __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ - }; -} CRC_Type; - -/* ---------------------------------------------------------------------------- - -- CRC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Register_Masks CRC Register Masks - * @{ - */ - -/*! @name MODE - CRC mode register */ -/*! @{ */ - -#define CRC_MODE_CRC_POLY_MASK (0x3U) -#define CRC_MODE_CRC_POLY_SHIFT (0U) -/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial - */ -#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) - -#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) -#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) -/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) - */ -#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) - -#define CRC_MODE_CMPL_WR_MASK (0x8U) -#define CRC_MODE_CMPL_WR_SHIFT (3U) -/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA - */ -#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) - -#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) -#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) -/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM - */ -#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) - -#define CRC_MODE_CMPL_SUM_MASK (0x20U) -#define CRC_MODE_CMPL_SUM_SHIFT (5U) -/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM - */ -#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) -/*! @} */ - -/*! @name SEED - CRC seed register */ -/*! @{ */ - -#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) -#define CRC_SEED_CRC_SEED_SHIFT (0U) -/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with - * selected bit order and 1's complement pre-processes. A write access to this register will - * overrule the CRC calculation in progresses. - */ -#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) -/*! @} */ - -/*! @name SUM - CRC checksum register */ -/*! @{ */ - -#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) -#define CRC_SUM_CRC_SUM_SHIFT (0U) -/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. - */ -#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) -/*! @} */ - -/*! @name WR_DATA - CRC data register */ -/*! @{ */ - -#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) -#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) -/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with - * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and - * accept back-to-back transactions. - */ -#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CRC_Register_Masks */ - - -/* CRC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CRC_ENGINE base address */ - #define CRC_ENGINE_BASE (0x50095000u) - /** Peripheral CRC_ENGINE base address */ - #define CRC_ENGINE_BASE_NS (0x40095000u) - /** Peripheral CRC_ENGINE base pointer */ - #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) - /** Peripheral CRC_ENGINE base pointer */ - #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS) - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS { CRC_ENGINE } - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS } -#else - /** Peripheral CRC_ENGINE base address */ - #define CRC_ENGINE_BASE (0x40095000u) - /** Peripheral CRC_ENGINE base pointer */ - #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS { CRC_ENGINE } -#endif - -/*! - * @} - */ /* end of group CRC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CTIMER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer - * @{ - */ - -/** CTIMER - Register Layout Typedef */ -typedef struct { - __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ - __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ - __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ - __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ - __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ - __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ - __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ - __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ - __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ - __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ - uint8_t RESERVED_0[48]; - __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ - __IO uint32_t PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */ - __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ -} CTIMER_Type; - -/* ---------------------------------------------------------------------------- - -- CTIMER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Register_Masks CTIMER Register Masks - * @{ - */ - -/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ -/*! @{ */ - -#define CTIMER_IR_MR0INT_MASK (0x1U) -#define CTIMER_IR_MR0INT_SHIFT (0U) -/*! MR0INT - Interrupt flag for match channel 0. - */ -#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) - -#define CTIMER_IR_MR1INT_MASK (0x2U) -#define CTIMER_IR_MR1INT_SHIFT (1U) -/*! MR1INT - Interrupt flag for match channel 1. - */ -#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) - -#define CTIMER_IR_MR2INT_MASK (0x4U) -#define CTIMER_IR_MR2INT_SHIFT (2U) -/*! MR2INT - Interrupt flag for match channel 2. - */ -#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) - -#define CTIMER_IR_MR3INT_MASK (0x8U) -#define CTIMER_IR_MR3INT_SHIFT (3U) -/*! MR3INT - Interrupt flag for match channel 3. - */ -#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) - -#define CTIMER_IR_CR0INT_MASK (0x10U) -#define CTIMER_IR_CR0INT_SHIFT (4U) -/*! CR0INT - Interrupt flag for capture channel 0 event. - */ -#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) - -#define CTIMER_IR_CR1INT_MASK (0x20U) -#define CTIMER_IR_CR1INT_SHIFT (5U) -/*! CR1INT - Interrupt flag for capture channel 1 event. - */ -#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) - -#define CTIMER_IR_CR2INT_MASK (0x40U) -#define CTIMER_IR_CR2INT_SHIFT (6U) -/*! CR2INT - Interrupt flag for capture channel 2 event. - */ -#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) - -#define CTIMER_IR_CR3INT_MASK (0x80U) -#define CTIMER_IR_CR3INT_SHIFT (7U) -/*! CR3INT - Interrupt flag for capture channel 3 event. - */ -#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) -/*! @} */ - -/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ -/*! @{ */ - -#define CTIMER_TCR_CEN_MASK (0x1U) -#define CTIMER_TCR_CEN_SHIFT (0U) -/*! CEN - Counter enable. - * 0b0..Disabled.The counters are disabled. - * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. - */ -#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) - -#define CTIMER_TCR_CRST_MASK (0x2U) -#define CTIMER_TCR_CRST_SHIFT (1U) -/*! CRST - Counter reset. - * 0b0..Disabled. Do nothing. - * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of - * the APB bus clock. The counters remain reset until TCR[1] is returned to zero. - */ -#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) -/*! @} */ - -/*! @name TC - Timer Counter */ -/*! @{ */ - -#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_TC_TCVAL_SHIFT (0U) -/*! TCVAL - Timer counter value. - */ -#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) -/*! @} */ - -/*! @name PR - Prescale Register */ -/*! @{ */ - -#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PR_PRVAL_SHIFT (0U) -/*! PRVAL - Prescale counter value. - */ -#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) -/*! @} */ - -/*! @name PC - Prescale Counter */ -/*! @{ */ - -#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PC_PCVAL_SHIFT (0U) -/*! PCVAL - Prescale counter value. - */ -#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) -/*! @} */ - -/*! @name MCR - Match Control Register */ -/*! @{ */ - -#define CTIMER_MCR_MR0I_MASK (0x1U) -#define CTIMER_MCR_MR0I_SHIFT (0U) -/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. - */ -#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) - -#define CTIMER_MCR_MR0R_MASK (0x2U) -#define CTIMER_MCR_MR0R_SHIFT (1U) -/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. - */ -#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) - -#define CTIMER_MCR_MR0S_MASK (0x4U) -#define CTIMER_MCR_MR0S_SHIFT (2U) -/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. - */ -#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) - -#define CTIMER_MCR_MR1I_MASK (0x8U) -#define CTIMER_MCR_MR1I_SHIFT (3U) -/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. - */ -#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) - -#define CTIMER_MCR_MR1R_MASK (0x10U) -#define CTIMER_MCR_MR1R_SHIFT (4U) -/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. - */ -#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) - -#define CTIMER_MCR_MR1S_MASK (0x20U) -#define CTIMER_MCR_MR1S_SHIFT (5U) -/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. - */ -#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) - -#define CTIMER_MCR_MR2I_MASK (0x40U) -#define CTIMER_MCR_MR2I_SHIFT (6U) -/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. - */ -#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) - -#define CTIMER_MCR_MR2R_MASK (0x80U) -#define CTIMER_MCR_MR2R_SHIFT (7U) -/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. - */ -#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) - -#define CTIMER_MCR_MR2S_MASK (0x100U) -#define CTIMER_MCR_MR2S_SHIFT (8U) -/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. - */ -#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) - -#define CTIMER_MCR_MR3I_MASK (0x200U) -#define CTIMER_MCR_MR3I_SHIFT (9U) -/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. - */ -#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) - -#define CTIMER_MCR_MR3R_MASK (0x400U) -#define CTIMER_MCR_MR3R_SHIFT (10U) -/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it. - */ -#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) - -#define CTIMER_MCR_MR3S_MASK (0x800U) -#define CTIMER_MCR_MR3S_SHIFT (11U) -/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. - */ -#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) - -#define CTIMER_MCR_MR0RL_MASK (0x1000000U) -#define CTIMER_MCR_MR0RL_SHIFT (24U) -/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero - * (either via a match event or a write to bit 1 of the TCR). - */ -#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) - -#define CTIMER_MCR_MR1RL_MASK (0x2000000U) -#define CTIMER_MCR_MR1RL_SHIFT (25U) -/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero - * (either via a match event or a write to bit 1 of the TCR). - */ -#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) - -#define CTIMER_MCR_MR2RL_MASK (0x4000000U) -#define CTIMER_MCR_MR2RL_SHIFT (26U) -/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero - * (either via a match event or a write to bit 1 of the TCR). - */ -#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) - -#define CTIMER_MCR_MR3RL_MASK (0x8000000U) -#define CTIMER_MCR_MR3RL_SHIFT (27U) -/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero - * (either via a match event or a write to bit 1 of the TCR). - */ -#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) -/*! @} */ - -/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ -/*! @{ */ - -#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) -#define CTIMER_MR_MATCH_SHIFT (0U) -/*! MATCH - Timer counter match value. - */ -#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) -/*! @} */ - -/* The count of CTIMER_MR */ -#define CTIMER_MR_COUNT (4U) - -/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ -/*! @{ */ - -#define CTIMER_CCR_CAP0RE_MASK (0x1U) -#define CTIMER_CCR_CAP0RE_SHIFT (0U) -/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) - -#define CTIMER_CCR_CAP0FE_MASK (0x2U) -#define CTIMER_CCR_CAP0FE_SHIFT (1U) -/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) - -#define CTIMER_CCR_CAP0I_MASK (0x4U) -#define CTIMER_CCR_CAP0I_SHIFT (2U) -/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. - */ -#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) - -#define CTIMER_CCR_CAP1RE_MASK (0x8U) -#define CTIMER_CCR_CAP1RE_SHIFT (3U) -/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) - -#define CTIMER_CCR_CAP1FE_MASK (0x10U) -#define CTIMER_CCR_CAP1FE_SHIFT (4U) -/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) - -#define CTIMER_CCR_CAP1I_MASK (0x20U) -#define CTIMER_CCR_CAP1I_SHIFT (5U) -/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. - */ -#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) - -#define CTIMER_CCR_CAP2RE_MASK (0x40U) -#define CTIMER_CCR_CAP2RE_SHIFT (6U) -/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) - -#define CTIMER_CCR_CAP2FE_MASK (0x80U) -#define CTIMER_CCR_CAP2FE_SHIFT (7U) -/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) - -#define CTIMER_CCR_CAP2I_MASK (0x100U) -#define CTIMER_CCR_CAP2I_SHIFT (8U) -/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. - */ -#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) - -#define CTIMER_CCR_CAP3RE_MASK (0x200U) -#define CTIMER_CCR_CAP3RE_SHIFT (9U) -/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) - -#define CTIMER_CCR_CAP3FE_MASK (0x400U) -#define CTIMER_CCR_CAP3FE_SHIFT (10U) -/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with - * the contents of TC. 0 = disabled. 1 = enabled. - */ -#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) - -#define CTIMER_CCR_CAP3I_MASK (0x800U) -#define CTIMER_CCR_CAP3I_SHIFT (11U) -/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. - */ -#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) -/*! @} */ - -/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ -/*! @{ */ - -#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) -#define CTIMER_CR_CAP_SHIFT (0U) -/*! CAP - Timer counter capture value. - */ -#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) -/*! @} */ - -/* The count of CTIMER_CR */ -#define CTIMER_CR_COUNT (4U) - -/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ -/*! @{ */ - -#define CTIMER_EMR_EM0_MASK (0x1U) -#define CTIMER_EMR_EM0_SHIFT (0U) -/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output - * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, - * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if - * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - */ -#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) - -#define CTIMER_EMR_EM1_MASK (0x2U) -#define CTIMER_EMR_EM1_SHIFT (1U) -/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output - * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, - * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if - * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - */ -#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) - -#define CTIMER_EMR_EM2_MASK (0x4U) -#define CTIMER_EMR_EM2_SHIFT (2U) -/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output - * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, - * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if - * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - */ -#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) - -#define CTIMER_EMR_EM3_MASK (0x8U) -#define CTIMER_EMR_EM3_SHIFT (3U) -/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output - * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, - * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins - * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - */ -#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) - -#define CTIMER_EMR_EMC0_MASK (0x30U) -#define CTIMER_EMR_EMC0_SHIFT (4U) -/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) - -#define CTIMER_EMR_EMC1_MASK (0xC0U) -#define CTIMER_EMR_EMC1_SHIFT (6U) -/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) - -#define CTIMER_EMR_EMC2_MASK (0x300U) -#define CTIMER_EMR_EMC2_SHIFT (8U) -/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) - -#define CTIMER_EMR_EMC3_MASK (0xC00U) -#define CTIMER_EMR_EMC3_SHIFT (10U) -/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) -/*! @} */ - -/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ -/*! @{ */ - -#define CTIMER_CTCR_CTMODE_MASK (0x3U) -#define CTIMER_CTCR_CTMODE_SHIFT (0U) -/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment - * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC - * is incremented when the Prescale Counter matches the Prescale Register. - * 0b00..Timer Mode. Incremented every rising APB bus clock edge. - * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. - * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. - * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. - */ -#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) - -#define CTIMER_CTCR_CINSEL_MASK (0xCU) -#define CTIMER_CTCR_CINSEL_SHIFT (2U) -/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which - * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input - * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be - * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the - * same timer. - * 0b00..Channel 0. CAPn.0 for CTIMERn - * 0b01..Channel 1. CAPn.1 for CTIMERn - * 0b10..Channel 2. CAPn.2 for CTIMERn - * 0b11..Channel 3. CAPn.3 for CTIMERn - */ -#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) - -#define CTIMER_CTCR_ENCC_MASK (0x10U) -#define CTIMER_CTCR_ENCC_SHIFT (4U) -/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the - * capture-edge event specified in bits 7:5 occurs. - */ -#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) - -#define CTIMER_CTCR_SELCC_MASK (0xE0U) -#define CTIMER_CTCR_SELCC_SHIFT (5U) -/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the - * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to - * 0x3 and 0x6 to 0x7 are reserved. - * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - */ -#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) -/*! @} */ - -/*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */ -/*! @{ */ - -#define CTIMER_PWMC_PWMEN0_MASK (0x1U) -#define CTIMER_PWMC_PWMEN0_SHIFT (0U) -/*! PWMEN0 - PWM mode enable for channel0. - * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. - */ -#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) - -#define CTIMER_PWMC_PWMEN1_MASK (0x2U) -#define CTIMER_PWMC_PWMEN1_SHIFT (1U) -/*! PWMEN1 - PWM mode enable for channel1. - * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. - */ -#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) - -#define CTIMER_PWMC_PWMEN2_MASK (0x4U) -#define CTIMER_PWMC_PWMEN2_SHIFT (2U) -/*! PWMEN2 - PWM mode enable for channel2. - * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. - */ -#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) - -#define CTIMER_PWMC_PWMEN3_MASK (0x8U) -#define CTIMER_PWMC_PWMEN3_SHIFT (3U) -/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. - * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. - * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. - */ -#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) -/*! @} */ - -/*! @name MSR - Match Shadow Register */ -/*! @{ */ - -#define CTIMER_MSR_SHADOW_MASK (0xFFFFFFFFU) -#define CTIMER_MSR_SHADOW_SHIFT (0U) -/*! SHADOW - Timer counter match shadow value. - */ -#define CTIMER_MSR_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOW_SHIFT)) & CTIMER_MSR_SHADOW_MASK) -/*! @} */ - -/* The count of CTIMER_MSR */ -#define CTIMER_MSR_COUNT (4U) - - -/*! - * @} - */ /* end of group CTIMER_Register_Masks */ - - -/* CTIMER - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE (0x50008000u) - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE_NS (0x40008000u) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE (0x50009000u) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE_NS (0x40009000u) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE (0x50028000u) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE_NS (0x40028000u) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE (0x50029000u) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE_NS (0x40029000u) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE (0x5002A000u) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE_NS (0x4002A000u) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } -#else - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE (0x40008000u) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE (0x40009000u) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE (0x40028000u) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE (0x40029000u) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE (0x4002A000u) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } -#endif -/** Interrupt vectors for the CTIMER peripheral type */ -#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } - -/*! - * @} - */ /* end of group CTIMER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DBGMAILBOX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DBGMAILBOX_Peripheral_Access_Layer DBGMAILBOX Peripheral Access Layer - * @{ - */ - -/** DBGMAILBOX - Register Layout Typedef */ -typedef struct { - __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */ - __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */ - __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */ - uint8_t RESERVED_0[240]; - __I uint32_t ID; /**< Identification register, offset: 0xFC */ -} DBGMAILBOX_Type; - -/* ---------------------------------------------------------------------------- - -- DBGMAILBOX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DBGMAILBOX_Register_Masks DBGMAILBOX Register Masks - * @{ - */ - -/*! @name CSW - CRC mode register */ -/*! @{ */ - -#define DBGMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) -#define DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) -/*! RESYNCH_REQ - Debugger will set this bit to 1 to request a resynchronrisation - */ -#define DBGMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DBGMAILBOX_CSW_RESYNCH_REQ_MASK) - -#define DBGMAILBOX_CSW_REQ_PENDING_MASK (0x2U) -#define DBGMAILBOX_CSW_REQ_PENDING_SHIFT (1U) -/*! REQ_PENDING - Request is pending from debugger (i.e unread value in REQUEST) - */ -#define DBGMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DBGMAILBOX_CSW_REQ_PENDING_MASK) - -#define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) -#define DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) -/*! DBG_OR_ERR - Debugger overrun error (previous REQUEST overwritten before being picked up by ROM) - */ -#define DBGMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK) - -#define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) -#define DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) -/*! AHB_OR_ERR - AHB overrun Error (Return value overwritten by ROM) - */ -#define DBGMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK) - -#define DBGMAILBOX_CSW_SOFT_RESET_MASK (0x10U) -#define DBGMAILBOX_CSW_SOFT_RESET_SHIFT (4U) -/*! SOFT_RESET - Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to - * this bit will cause a soft reset for DM. - */ -#define DBGMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DBGMAILBOX_CSW_SOFT_RESET_MASK) - -#define DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) -#define DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) -/*! CHIP_RESET_REQ - Write only bit. Once written will cause the chip to reset (note that the DM is - * not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event) - */ -#define DBGMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK) -/*! @} */ - -/*! @name REQUEST - CRC seed register */ -/*! @{ */ - -#define DBGMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU) -#define DBGMAILBOX_REQUEST_REQ_SHIFT (0U) -/*! REQ - Request Value - */ -#define DBGMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_REQUEST_REQ_SHIFT)) & DBGMAILBOX_REQUEST_REQ_MASK) -/*! @} */ - -/*! @name RETURN - Return value from ROM. */ -/*! @{ */ - -#define DBGMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) -#define DBGMAILBOX_RETURN_RET_SHIFT (0U) -/*! RET - The Return value from ROM. - */ -#define DBGMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_RETURN_RET_SHIFT)) & DBGMAILBOX_RETURN_RET_MASK) -/*! @} */ - -/*! @name ID - Identification register */ -/*! @{ */ - -#define DBGMAILBOX_ID_ID_MASK (0xFFFFFFFFU) -#define DBGMAILBOX_ID_ID_SHIFT (0U) -/*! ID - Identification value. - */ -#define DBGMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_ID_ID_SHIFT)) & DBGMAILBOX_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group DBGMAILBOX_Register_Masks */ - - -/* DBGMAILBOX - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral DBGMAILBOX base address */ - #define DBGMAILBOX_BASE (0x5009C000u) - /** Peripheral DBGMAILBOX base address */ - #define DBGMAILBOX_BASE_NS (0x4009C000u) - /** Peripheral DBGMAILBOX base pointer */ - #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) - /** Peripheral DBGMAILBOX base pointer */ - #define DBGMAILBOX_NS ((DBGMAILBOX_Type *)DBGMAILBOX_BASE_NS) - /** Array initializer of DBGMAILBOX peripheral base addresses */ - #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } - /** Array initializer of DBGMAILBOX peripheral base pointers */ - #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } - /** Array initializer of DBGMAILBOX peripheral base addresses */ - #define DBGMAILBOX_BASE_ADDRS_NS { DBGMAILBOX_BASE_NS } - /** Array initializer of DBGMAILBOX peripheral base pointers */ - #define DBGMAILBOX_BASE_PTRS_NS { DBGMAILBOX_NS } -#else - /** Peripheral DBGMAILBOX base address */ - #define DBGMAILBOX_BASE (0x4009C000u) - /** Peripheral DBGMAILBOX base pointer */ - #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) - /** Array initializer of DBGMAILBOX peripheral base addresses */ - #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } - /** Array initializer of DBGMAILBOX peripheral base pointers */ - #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } -#endif - -/*! - * @} - */ /* end of group DBGMAILBOX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer - * @{ - */ - -/** DMA - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ - __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ - __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ - uint8_t RESERVED_0[20]; - struct { /* offset: 0x20, array step: 0x5C */ - __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ - uint8_t RESERVED_0[4]; - __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ - uint8_t RESERVED_1[4]; - __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ - uint8_t RESERVED_2[4]; - __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ - uint8_t RESERVED_3[4]; - __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ - uint8_t RESERVED_4[4]; - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ - uint8_t RESERVED_5[4]; - __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ - uint8_t RESERVED_6[4]; - __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ - uint8_t RESERVED_7[4]; - __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ - uint8_t RESERVED_8[4]; - __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ - uint8_t RESERVED_9[4]; - __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ - uint8_t RESERVED_10[4]; - __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ - } COMMON[1]; - uint8_t RESERVED_1[900]; - struct { /* offset: 0x400, array step: 0x10 */ - __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ - __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ - __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } CHANNEL[23]; -} DMA_Type; - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/*! @name CTRL - DMA control. */ -/*! @{ */ - -#define DMA_CTRL_ENABLE_MASK (0x1U) -#define DMA_CTRL_ENABLE_SHIFT (0U) -/*! ENABLE - DMA controller master enable. - * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when - * disabled, but does not prevent re-triggering when the DMA controller is re-enabled. - * 0b1..Enabled. The DMA controller is enabled. - */ -#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status. */ -/*! @{ */ - -#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) -#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) -/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. - * 0b0..Not pending. No enabled interrupts are pending. - * 0b1..Pending. At least one enabled interrupt is pending. - */ -#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) - -#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) -#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) -/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. - * 0b0..Not pending. No error interrupts are pending. - * 0b1..Pending. At least one error interrupt is pending. - */ -#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) -/*! @} */ - -/*! @name SRAMBASE - SRAM address of the channel configuration table. */ -/*! @{ */ - -#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) -#define DMA_SRAMBASE_OFFSET_SHIFT (9U) -/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the - * table must begin on a 512 byte boundary. - */ -#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) -/*! @} */ - -/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) -/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = - * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. - */ -#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLESET */ -#define DMA_COMMON_ENABLESET_COUNT (1U) - -/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) -/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears - * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits - * are reserved. - */ -#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLECLR */ -#define DMA_COMMON_ENABLECLR_COUNT (1U) - -/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) -/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = - * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. - */ -#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ACTIVE */ -#define DMA_COMMON_ACTIVE_COUNT (1U) - -/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) -#define DMA_COMMON_BUSY_BSY_SHIFT (0U) -/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = - * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. - */ -#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) -/*! @} */ - -/* The count of DMA_COMMON_BUSY */ -#define DMA_COMMON_BUSY_COUNT (1U) - -/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) -/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of - * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is - * not active. 1 = error interrupt is active. - */ -#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ERRINT */ -#define DMA_COMMON_ERRINT_COUNT (1U) - -/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) -/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The - * number of bits = number of DMA channels in this device. Other bits are reserved. 0 = - * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. - */ -#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENSET */ -#define DMA_COMMON_INTENSET_COUNT (1U) - -/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) -/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n - * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are - * reserved. - */ -#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENCLR */ -#define DMA_COMMON_INTENCLR_COUNT (1U) - -/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTA_IA_SHIFT (0U) -/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of - * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel - * interrupt A is not active. 1 = the DMA channel interrupt A is active. - */ -#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTA */ -#define DMA_COMMON_INTA_COUNT (1U) - -/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTB_IB_SHIFT (0U) -/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of - * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel - * interrupt B is not active. 1 = the DMA channel interrupt B is active. - */ -#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTB */ -#define DMA_COMMON_INTB_COUNT (1U) - -/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETVALID_SV_SHIFT (0U) -/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits - * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the - * VALIDPENDING control bit for DMA channel n - */ -#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETVALID */ -#define DMA_COMMON_SETVALID_COUNT (1U) - -/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) -/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number - * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = - * sets the TRIG bit for DMA channel n. - */ -#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETTRIG */ -#define DMA_COMMON_SETTRIG_COUNT (1U) - -/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ -/*! @{ */ - -#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) -/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. - * 1 = aborts DMA operations on channel n. - */ -#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ABORT */ -#define DMA_COMMON_ABORT_COUNT (1U) - -/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ -/*! @{ */ - -#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) -#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) -/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory - * move, any peripheral DMA request associated with that channel can be disabled to prevent any - * interaction between the peripheral and the DMA controller. - * 0b0..Disabled. Peripheral DMA requests are disabled. - * 0b1..Enabled. Peripheral DMA requests are enabled. - */ -#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) - -#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) -#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) -/*! HWTRIGEN - Hardware Triggering Enable for this channel. - * 0b0..Disabled. Hardware triggering is not used. - * 0b1..Enabled. Use hardware triggering. - */ -#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) - -#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) -#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) -/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. - * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. - * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. - */ -#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) - -#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) -#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) -/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. - * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. - * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = - * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the - * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger - * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the - * current BURSTPOWER length are completed. - */ -#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) - -#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) -#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) -/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. - * 0b0..Single transfer. Hardware trigger causes a single transfer. - * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a - * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a - * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is - * complete. - */ -#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) - -#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) -#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) -/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when - * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). - * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many - * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that - * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: - * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = - * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The - * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even - * multiple of the burst size. - */ -#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) - -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) -/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is - * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this - * could be used to read several sequential registers from a peripheral for each DMA burst, - * reading the same registers again for each burst. - * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. - * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. - */ -#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) - -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) -/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is - * 'wrapped', meaning that the destination address range for each burst will be the same. As an - * example, this could be used to write several sequential registers to a peripheral for each DMA - * burst, writing the same registers again for each burst. - * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. - * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. - */ -#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) - -#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) -#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) -/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority - * levels are supported: 0x0 = highest priority. 0x7 = lowest priority. - */ -#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CFG */ -#define DMA_CHANNEL_CFG_COUNT (23U) - -/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ -/*! @{ */ - -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) -/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the - * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. - * 0b0..No effect. No effect on DMA operation. - * 0b1..Valid pending. - */ -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) - -#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) -#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) -/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is - * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. - * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. - * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. - */ -#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CTLSTAT */ -#define DMA_CHANNEL_CTLSTAT_COUNT (23U) - -/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ -/*! @{ */ - -#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) -#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) -/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor - * is valid and can potentially be acted upon, if all other activation criteria are fulfilled. - * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. - * 0b1..Valid. The current channel descriptor is considered valid. - */ -#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) - -#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) -#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) -/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current - * descriptor is exhausted. Reloading allows ping-pong and linked transfers. - * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. - * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) - -#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) -#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) -/*! SWTRIG - Software Trigger. - * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by - * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. - * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not - * be used with level triggering when TRIGBURST = 0. - */ -#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) - -#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) -#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) -/*! CLRTRIG - Clear Trigger. - * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. - * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted - */ -#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) - -#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) -#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) -/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between - * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By - * convention, interrupt A may be used when only one interrupt flag is needed. - * 0b0..No effect. - * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) - -#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) -#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) -/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between - * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By - * convention, interrupt A may be used when only one interrupt flag is needed. - * 0b0..No effect. - * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) - -#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) -#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) -/*! WIDTH - Transfer width used for this DMA channel. - * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). - * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). - * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). - * 0b11..Reserved. Reserved setting, do not use. - */ -#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) - -#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) -#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) -/*! SRCINC - Determines whether the source address is incremented for each DMA transfer. - * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. - * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is - * the usual case when the source is memory. - * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. - * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. - */ -#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) - -#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) -#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) -/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. - * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when - * the destination is a peripheral device. - * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. - * This is the usual case when the destination is memory. - * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. - * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. - */ -#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) - -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) -/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes - * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller - * uses this bit field during transfer to count down. Hence, it cannot be used by software to read - * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 - * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of - * 1,024 transfers will be performed. - */ -#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_XFERCFG */ -#define DMA_CHANNEL_XFERCFG_COUNT (23U) - - -/*! - * @} - */ /* end of group DMA_Register_Masks */ - - -/* DMA - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral DMA0 base address */ - #define DMA0_BASE (0x50082000u) - /** Peripheral DMA0 base address */ - #define DMA0_BASE_NS (0x40082000u) - /** Peripheral DMA0 base pointer */ - #define DMA0 ((DMA_Type *)DMA0_BASE) - /** Peripheral DMA0 base pointer */ - #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) - /** Peripheral DMA1 base address */ - #define DMA1_BASE (0x500A7000u) - /** Peripheral DMA1 base address */ - #define DMA1_BASE_NS (0x400A7000u) - /** Peripheral DMA1 base pointer */ - #define DMA1 ((DMA_Type *)DMA1_BASE) - /** Peripheral DMA1 base pointer */ - #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS { DMA0, DMA1 } - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } -#else - /** Peripheral DMA0 base address */ - #define DMA0_BASE (0x40082000u) - /** Peripheral DMA0 base pointer */ - #define DMA0 ((DMA_Type *)DMA0_BASE) - /** Peripheral DMA1 base address */ - #define DMA1_BASE (0x400A7000u) - /** Peripheral DMA1 base pointer */ - #define DMA1 ((DMA_Type *)DMA1_BASE) - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS { DMA0, DMA1 } -#endif -/** Interrupt vectors for the DMA peripheral type */ -#define DMA_IRQS { DMA0_IRQn, DMA1_IRQn } - -/*! - * @} - */ /* end of group DMA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer - * @{ - */ - -/** FLASH - Register Layout Typedef */ -typedef struct { - __O uint32_t CMD; /**< command register, offset: 0x0 */ - __O uint32_t EVENT; /**< event register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */ - __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */ - uint8_t RESERVED_1[104]; - __IO uint32_t DATAW[4]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_2[3912]; - __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */ - __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */ - __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ - __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ - __O uint32_t INT_CLR_STATUS; /**< Clear interrupt status bits, offset: 0xFE8 */ - __O uint32_t INT_SET_STATUS; /**< Set interrupt status bits, offset: 0xFEC */ - uint8_t RESERVED_3[12]; - __I uint32_t MODULE_ID; /**< Controller+Memory module identification, offset: 0xFFC */ -} FLASH_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_Register_Masks FLASH Register Masks - * @{ - */ - -/*! @name CMD - command register */ -/*! @{ */ - -#define FLASH_CMD_CMD_MASK (0xFFFFFFFFU) -#define FLASH_CMD_CMD_SHIFT (0U) -/*! CMD - command register. - */ -#define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK) -/*! @} */ - -/*! @name EVENT - event register */ -/*! @{ */ - -#define FLASH_EVENT_RST_MASK (0x1U) -#define FLASH_EVENT_RST_SHIFT (0U) -/*! RST - When bit is set, the controller and flash are reset. - */ -#define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK) - -#define FLASH_EVENT_WAKEUP_MASK (0x2U) -#define FLASH_EVENT_WAKEUP_SHIFT (1U) -/*! WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active. - */ -#define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK) - -#define FLASH_EVENT_ABORT_MASK (0x4U) -#define FLASH_EVENT_ABORT_SHIFT (2U) -/*! ABORT - When bit is set, a running program/erase command is aborted. - */ -#define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK) -/*! @} */ - -/*! @name STARTA - start (or only) address for next flash command */ -/*! @{ */ - -#define FLASH_STARTA_STARTA_MASK (0x3FFFFU) -#define FLASH_STARTA_STARTA_SHIFT (0U) -/*! STARTA - Address / Start address for commands that take an address (range) as a parameter. - */ -#define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK) -/*! @} */ - -/*! @name STOPA - end address for next flash command, if command operates on address ranges */ -/*! @{ */ - -#define FLASH_STOPA_STOPA_MASK (0x3FFFFU) -#define FLASH_STOPA_STOPA_SHIFT (0U) -/*! STOPA - Stop address for commands that take an address range as a parameter (the word specified - * by STOPA is included in the address range). - */ -#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK) -/*! @} */ - -/*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */ -/*! @{ */ - -#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU) -#define FLASH_DATAW_DATAW_SHIFT (0U) -#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK) -/*! @} */ - -/* The count of FLASH_DATAW */ -#define FLASH_DATAW_COUNT (4U) - -/*! @name INT_CLR_ENABLE - Clear interrupt enable bits */ -/*! @{ */ - -#define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U) -#define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U) -/*! FAIL - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - */ -#define FLASH_INT_CLR_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK) - -#define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U) -#define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U) -/*! ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - */ -#define FLASH_INT_CLR_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK) - -#define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U) -#define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U) -/*! DONE - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - */ -#define FLASH_INT_CLR_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK) - -#define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U) -#define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - */ -#define FLASH_INT_CLR_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_SET_ENABLE - Set interrupt enable bits */ -/*! @{ */ - -#define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U) -#define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U) -/*! FAIL - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - */ -#define FLASH_INT_SET_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK) - -#define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U) -#define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U) -/*! ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - */ -#define FLASH_INT_SET_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK) - -#define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U) -#define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U) -/*! DONE - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - */ -#define FLASH_INT_SET_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK) - -#define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U) -#define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - */ -#define FLASH_INT_SET_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_STATUS - Interrupt status bits */ -/*! @{ */ - -#define FLASH_INT_STATUS_FAIL_MASK (0x1U) -#define FLASH_INT_STATUS_FAIL_SHIFT (0U) -/*! FAIL - This status bit is set if execution of a (legal) command failed. - */ -#define FLASH_INT_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK) - -#define FLASH_INT_STATUS_ERR_MASK (0x2U) -#define FLASH_INT_STATUS_ERR_SHIFT (1U) -/*! ERR - This status bit is set if execution of an illegal command is detected. - */ -#define FLASH_INT_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK) - -#define FLASH_INT_STATUS_DONE_MASK (0x4U) -#define FLASH_INT_STATUS_DONE_SHIFT (2U) -/*! DONE - This status bit is set at the end of command execution. - */ -#define FLASH_INT_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK) - -#define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U) -#define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested - * read, or a speculative read, or reads performed by a controller command), a correctable or - * uncorrectable error is detected by ECC decoding logic. - */ -#define FLASH_INT_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_ENABLE - Interrupt enable bits */ -/*! @{ */ - -#define FLASH_INT_ENABLE_FAIL_MASK (0x1U) -#define FLASH_INT_ENABLE_FAIL_SHIFT (0U) -/*! FAIL - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - */ -#define FLASH_INT_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK) - -#define FLASH_INT_ENABLE_ERR_MASK (0x2U) -#define FLASH_INT_ENABLE_ERR_SHIFT (1U) -/*! ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - */ -#define FLASH_INT_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK) - -#define FLASH_INT_ENABLE_DONE_MASK (0x4U) -#define FLASH_INT_ENABLE_DONE_SHIFT (2U) -/*! DONE - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - */ -#define FLASH_INT_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK) - -#define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U) -#define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - */ -#define FLASH_INT_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_CLR_STATUS - Clear interrupt status bits */ -/*! @{ */ - -#define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U) -#define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U) -/*! FAIL - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - */ -#define FLASH_INT_CLR_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK) - -#define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U) -#define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U) -/*! ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - */ -#define FLASH_INT_CLR_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK) - -#define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U) -#define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U) -/*! DONE - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - */ -#define FLASH_INT_CLR_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK) - -#define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U) -#define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - */ -#define FLASH_INT_CLR_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_SET_STATUS - Set interrupt status bits */ -/*! @{ */ - -#define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U) -#define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U) -/*! FAIL - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - */ -#define FLASH_INT_SET_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK) - -#define FLASH_INT_SET_STATUS_ERR_MASK (0x2U) -#define FLASH_INT_SET_STATUS_ERR_SHIFT (1U) -/*! ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - */ -#define FLASH_INT_SET_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK) - -#define FLASH_INT_SET_STATUS_DONE_MASK (0x4U) -#define FLASH_INT_SET_STATUS_DONE_SHIFT (2U) -/*! DONE - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - */ -#define FLASH_INT_SET_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK) - -#define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U) -#define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U) -/*! ECC_ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - */ -#define FLASH_INT_SET_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK) -/*! @} */ - -/*! @name MODULE_ID - Controller+Memory module identification */ -/*! @{ */ - -#define FLASH_MODULE_ID_APERTURE_MASK (0xFFU) -#define FLASH_MODULE_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture i. - */ -#define FLASH_MODULE_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK) - -#define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U) -#define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision i. - */ -#define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK) - -#define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U) -#define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision i. - */ -#define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK) - -#define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U) -#define FLASH_MODULE_ID_ID_SHIFT (16U) -/*! ID - Identifier. - */ -#define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLASH_Register_Masks */ - - -/* FLASH - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH base address */ - #define FLASH_BASE (0x50034000u) - /** Peripheral FLASH base address */ - #define FLASH_BASE_NS (0x40034000u) - /** Peripheral FLASH base pointer */ - #define FLASH ((FLASH_Type *)FLASH_BASE) - /** Peripheral FLASH base pointer */ - #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS) - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS { FLASH_BASE } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS { FLASH } - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS_NS { FLASH_NS } -#else - /** Peripheral FLASH base address */ - #define FLASH_BASE (0x40034000u) - /** Peripheral FLASH base pointer */ - #define FLASH ((FLASH_Type *)FLASH_BASE) - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS { FLASH_BASE } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS { FLASH } -#endif - -/*! - * @} - */ /* end of group FLASH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_CFPA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CFPA_Peripheral_Access_Layer FLASH_CFPA Peripheral Access Layer - * @{ - */ - -/** FLASH_CFPA - Register Layout Typedef */ -typedef struct { - __IO uint32_t HEADER; /**< , offset: 0x0 */ - __IO uint32_t VERSION; /**< , offset: 0x4 */ - __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */ - __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */ - __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */ - uint8_t RESERVED_0[4]; - __IO uint32_t ROTKH_REVOKE; /**< , offset: 0x18 */ - __IO uint32_t VENDOR_USAGE; /**< , offset: 0x1C */ - __IO uint32_t DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */ - __IO uint32_t DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */ - __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */ - __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */ - union { /* offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< , array offset: 0x30, array step: 0x4 */ - struct { /* offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< , offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< , offset: 0x34 */ - __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< , array offset: 0x38, array step: 0x4 */ - } PRINCE_REGION0_IV_CODE_CORE; - }; - union { /* offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< , array offset: 0x68, array step: 0x4 */ - struct { /* offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< , offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< , offset: 0x6C */ - __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< , array offset: 0x70, array step: 0x4 */ - } PRINCE_REGION1_IV_CODE_CORE; - }; - union { /* offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< , array offset: 0xA0, array step: 0x4 */ - struct { /* offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< , offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< , offset: 0xA4 */ - __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< , array offset: 0xA8, array step: 0x4 */ - } PRINCE_REGION2_IV_CODE_CORE; - }; - uint8_t RESERVED_1[40]; - __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ - __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ -} FLASH_CFPA_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_CFPA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CFPA_Register_Masks FLASH_CFPA Register Masks - * @{ - */ - -/*! @name HEADER - */ -/*! @{ */ - -#define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_HEADER_FIELD_SHIFT (0U) -#define FLASH_CFPA_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK) -/*! @} */ - -/*! @name VERSION - */ -/*! @{ */ - -#define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_VERSION_FIELD_SHIFT (0U) -#define FLASH_CFPA_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK) -/*! @} */ - -/*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */ -/*! @{ */ - -#define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U) -#define FLASH_CFPA_S_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK) -/*! @} */ - -/*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */ -/*! @{ */ - -#define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U) -#define FLASH_CFPA_NS_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK) -/*! @} */ - -/*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */ -/*! @{ */ - -#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U) -#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK) -/*! @} */ - -/*! @name ROTKH_REVOKE - */ -/*! @{ */ - -#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U) -/*! RoTK0_EN - RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK) - -#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U) -/*! RoTK1_EN - RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK) - -#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U) -/*! RoTK2_EN - RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK) - -#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK (0xC0U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT (6U) -/*! RoTK3_EN - RoT Key 3 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK) -/*! @} */ - -/*! @name VENDOR_USAGE - */ -/*! @{ */ - -#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU) -#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U) -/*! DBG_VENDOR_USAGE - DBG_VENDOR_USAGE. - */ -#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK) - -#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ -/*! @{ */ - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) -/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) -/*! FA_CMD_EN - FA Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) -/*! ME_CMD_EN - Flash Mass Erase Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) -/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) -/*! UUID_CHECK - Enforce UUID match during Debug authentication. - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ -/*! @{ */ - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) -/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) -/*! FA_CMD_EN - FA Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) -/*! ME_CMD_EN - Flash Mass Erase Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) -/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK) - -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */ -/*! @{ */ - -#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK) -/*! @} */ - -/*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */ -/*! @{ */ - -#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U) -#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_IV_CODE - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */ -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U) - -/*! @name PRINCE_REGION0_IV_HEADER0 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_IV_HEADER1 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK) - -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK) - -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_IV_BODY - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */ -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U) - -/*! @name PRINCE_REGION1_IV_CODE - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */ -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U) - -/*! @name PRINCE_REGION1_IV_HEADER0 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_IV_HEADER1 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK) - -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK) - -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_IV_BODY - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */ -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U) - -/*! @name PRINCE_REGION2_IV_CODE - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */ -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U) - -/*! @name PRINCE_REGION2_IV_HEADER0 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_IV_HEADER1 - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK) - -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK) - -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_IV_BODY - */ -/*! @{ */ - -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION2_IV_BODY */ -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_COUNT (12U) - -/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ -/*! @{ */ - -#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) -#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_CUSTOMER_DEFINED */ -#define FLASH_CFPA_CUSTOMER_DEFINED_COUNT (56U) - -/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ -/*! @{ */ - -#define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U) -#define FLASH_CFPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_SHA256_DIGEST */ -#define FLASH_CFPA_SHA256_DIGEST_COUNT (8U) - - -/*! - * @} - */ /* end of group FLASH_CFPA_Register_Masks */ - - -/* FLASH_CFPA - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH_CFPA0 base address */ - #define FLASH_CFPA0_BASE (0x1009E000u) - /** Peripheral FLASH_CFPA0 base address */ - #define FLASH_CFPA0_BASE_NS (0x9E000u) - /** Peripheral FLASH_CFPA0 base pointer */ - #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) - /** Peripheral FLASH_CFPA0 base pointer */ - #define FLASH_CFPA0_NS ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS) - /** Peripheral FLASH_CFPA1 base address */ - #define FLASH_CFPA1_BASE (0x1009E200u) - /** Peripheral FLASH_CFPA1 base address */ - #define FLASH_CFPA1_BASE_NS (0x9E200u) - /** Peripheral FLASH_CFPA1 base pointer */ - #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) - /** Peripheral FLASH_CFPA1 base pointer */ - #define FLASH_CFPA1_NS ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS) - /** Peripheral FLASH_CFPA_SCRATCH base address */ - #define FLASH_CFPA_SCRATCH_BASE (0x1009DE00u) - /** Peripheral FLASH_CFPA_SCRATCH base address */ - #define FLASH_CFPA_SCRATCH_BASE_NS (0x9DE00u) - /** Peripheral FLASH_CFPA_SCRATCH base pointer */ - #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) - /** Peripheral FLASH_CFPA_SCRATCH base pointer */ - #define FLASH_CFPA_SCRATCH_NS ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS) - /** Array initializer of FLASH_CFPA peripheral base addresses */ - #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } - /** Array initializer of FLASH_CFPA peripheral base pointers */ - #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } - /** Array initializer of FLASH_CFPA peripheral base addresses */ - #define FLASH_CFPA_BASE_ADDRS_NS { FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS } - /** Array initializer of FLASH_CFPA peripheral base pointers */ - #define FLASH_CFPA_BASE_PTRS_NS { FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS } -#else - /** Peripheral FLASH_CFPA0 base address */ - #define FLASH_CFPA0_BASE (0x9E000u) - /** Peripheral FLASH_CFPA0 base pointer */ - #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) - /** Peripheral FLASH_CFPA1 base address */ - #define FLASH_CFPA1_BASE (0x9E200u) - /** Peripheral FLASH_CFPA1 base pointer */ - #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) - /** Peripheral FLASH_CFPA_SCRATCH base address */ - #define FLASH_CFPA_SCRATCH_BASE (0x9DE00u) - /** Peripheral FLASH_CFPA_SCRATCH base pointer */ - #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) - /** Array initializer of FLASH_CFPA peripheral base addresses */ - #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } - /** Array initializer of FLASH_CFPA peripheral base pointers */ - #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } -#endif - -/*! - * @} - */ /* end of group FLASH_CFPA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_CMPA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CMPA_Peripheral_Access_Layer FLASH_CMPA Peripheral Access Layer - * @{ - */ - -/** FLASH_CMPA - Register Layout Typedef */ -typedef struct { - __IO uint32_t BOOT_CFG; /**< , offset: 0x0 */ - __IO uint32_t SPI_FLASH_CFG; /**< , offset: 0x4 */ - __IO uint32_t USB_ID; /**< , offset: 0x8 */ - __IO uint32_t SDIO_CFG; /**< , offset: 0xC */ - __IO uint32_t CC_SOCU_PIN; /**< , offset: 0x10 */ - __IO uint32_t CC_SOCU_DFLT; /**< , offset: 0x14 */ - __IO uint32_t VENDOR_USAGE; /**< , offset: 0x18 */ - __IO uint32_t SECURE_BOOT_CFG; /**< Secure boot configuration flags., offset: 0x1C */ - __IO uint32_t PRINCE_BASE_ADDR; /**< , offset: 0x20 */ - __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */ - __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */ - __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */ - __IO uint32_t XTAL_32KHZ_CAPABANK_TRIM; /**< Xtal 32kHz capabank triming., offset: 0x30 */ - __IO uint32_t XTAL_16MHZ_CAPABANK_TRIM; /**< Xtal 16MHz capabank triming., offset: 0x34 */ - uint8_t RESERVED_0[24]; - __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */ - uint8_t RESERVED_1[144]; - __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ - __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ -} FLASH_CMPA_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_CMPA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CMPA_Register_Masks FLASH_CMPA Register Masks - * @{ - */ - -/*! @name BOOT_CFG - */ -/*! @{ */ - -#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U) -#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U) -/*! DEFAULT_ISP_MODE - Default ISP mode: - * 0b000..Auto ISP - * 0b001..USB_HID_ISP - * 0b010..UART ISP - * 0b011..SPI Slave ISP - * 0b100..I2C Slave ISP - * 0b111..Disable ISP fall through - */ -#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK) - -#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U) -#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U) -/*! BOOT_SPEED - Core clock: - * 0b00..Defined by NMPA.SYSTEM_SPEED_CODE - * 0b01..96MHz FRO - * 0b10..48MHz FRO - */ -#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK) - -#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U) -#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U) -/*! BOOT_FAILURE_PIN - GPIO port and pin number to use for indicating failure reason. The toggle - * rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO - * pin - */ -#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK) -/*! @} */ - -/*! @name SPI_FLASH_CFG - */ -/*! @{ */ - -#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK (0x1FU) -#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT (0U) -/*! SPI_RECOVERY_BOOT_EN - SPI flash recovery boot is enabled, if non-zero value is written to this field. - */ -#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK) -/*! @} */ - -/*! @name USB_ID - */ -/*! @{ */ - -#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU) -#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U) -#define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK) - -#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U) -#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U) -#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK) -/*! @} */ - -/*! @name SDIO_CFG - */ -/*! @{ */ - -#define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U) -#define FLASH_CMPA_SDIO_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK) -/*! @} */ - -/*! @name CC_SOCU_PIN - */ -/*! @{ */ - -#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK (0x1U) -#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK (0x2U) -#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) -#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK (0x8U) -#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK (0x10U) -#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) -#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) -/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) -#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) -/*! FA_CMD_EN - FA Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) -#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) -/*! ME_CMD_EN - Flash Mass Erase Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) -#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) -/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) -#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) -/*! UUID_CHECK - Enforce UUID match during Debug authentication. - */ -#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK) - -#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name CC_SOCU_DFLT - */ -/*! @{ */ - -#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK (0x1U) -#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK (0x2U) -#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) -#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) -#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK (0x10U) -#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) -#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) -/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) -#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) -/*! FA_CMD_EN - FA Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) -#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) -/*! ME_CMD_EN - Flash Mass Erase Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) -#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) -/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK) - -#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) -/*! INVERSE_VALUE - inverse value of bits [15:0] - */ -#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name VENDOR_USAGE - */ -/*! @{ */ - -#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK (0xFFFF0000U) -#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT (16U) -/*! VENDOR_USAGE - Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area. - */ -#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK) -/*! @} */ - -/*! @name SECURE_BOOT_CFG - Secure boot configuration flags. */ -/*! @{ */ - -#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U) -#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U) -/*! RSA4K - Use RSA4096 keys only. - * 0b00..Allow RSA2048 and higher - * 0b01..RSA4096 only - * 0b10..RSA4096 only - * 0b11..RSA4096 only - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK (0xCU) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT (2U) -/*! DICE_INC_NXP_CFG - Include NXP area in DICE computation. - * 0b00..not included - * 0b01..included - * 0b10..included - * 0b11..included - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U) -/*! DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. - * 0b00..not included - * 0b01..included - * 0b10..included - * 0b11..included - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U) -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U) -/*! SKIP_DICE - Skip DICE computation - * 0b00..Enable DICE - * 0b01..Disable DICE - * 0b10..Disable DICE - * 0b11..Disable DICE - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U) -#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U) -/*! TZM_IMAGE_TYPE - TrustZone-M mode - * 0b00..TZ-M image mode is taken from application image header - * 0b01..TZ-M disabled image, boots to non-secure mode - * 0b10..TZ-M enabled image, boots to secure mode - * 0b11..TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U) -/*! BLOCK_SET_KEY - Block PUF key code generation - * 0b00..Allow PUF Key Code generation - * 0b01..Disable PUF Key Code generation - * 0b10..Disable PUF Key Code generation - * 0b11..Disable PUF Key Code generation - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U) -/*! BLOCK_ENROLL - Block PUF enrollement - * 0b00..Allow PUF enroll operation - * 0b01..Disable PUF enroll operation - * 0b10..Disable PUF enroll operation - * 0b11..Disable PUF enroll operation - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK (0xC000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT (14U) -/*! DICE_INC_SEC_EPOCH - Include security EPOCH in DICE - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK) - -#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U) -/*! SEC_BOOT_EN - Secure boot enable - * 0b00..Plain image (internal flash with or without CRC) - * 0b01..Boot signed images. (internal flash, RSA signed) - * 0b10..Boot signed images. (internal flash, RSA signed) - * 0b11..Boot signed images. (internal flash, RSA signed) - */ -#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK) -/*! @} */ - -/*! @name PRINCE_BASE_ADDR - */ -/*! @{ */ - -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U) -/*! ADDR0_PRG - Programmable portion of the base address of region 0 - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U) -/*! ADDR1_PRG - Programmable portion of the base address of region 1 - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U) -/*! ADDR2_PRG - Programmable portion of the base address of region 2 - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0xC0000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (18U) -/*! LOCK_REG0 - Lock PRINCE region0 settings - * 0b00..Region is not locked - * 0b01..Region is locked - * 0b10..Region is locked - * 0b11..Region is locked - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0x300000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (20U) -/*! LOCK_REG1 - Lock PRINCE region1 settings - * 0b00..Region is not locked - * 0b01..Region is locked - * 0b10..Region is locked - * 0b11..Region is locked - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U) -/*! REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased together - * 0b00..Region is disabled - * 0b01..Region is enabled - * 0b10..Region is enabled - * 0b11..Region is enabled - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U) -/*! REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased together - * 0b00..Region is disabled - * 0b01..Region is enabled - * 0b10..Region is enabled - * 0b11..Region is enabled - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK) - -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U) -/*! REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased together - * 0b00..Region is disabled - * 0b01..Region is enabled - * 0b10..Region is enabled - * 0b11..Region is enabled - */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK) -/*! @} */ - -/*! @name PRINCE_SR_0 - Region 0, sub-region enable */ -/*! @{ */ - -#define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U) -#define FLASH_CMPA_PRINCE_SR_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_SR_1 - Region 1, sub-region enable */ -/*! @{ */ - -#define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U) -#define FLASH_CMPA_PRINCE_SR_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_SR_2 - Region 2, sub-region enable */ -/*! @{ */ - -#define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U) -#define FLASH_CMPA_PRINCE_SR_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK) -/*! @} */ - -/*! @name XTAL_32KHZ_CAPABANK_TRIM - Xtal 32kHz capabank triming. */ -/*! @{ */ - -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) -/*! TRIM_VALID - XTAL 32kHz capa bank trimmings - * 0b0..Capa Bank trimmings not valid. Default trimmings value are used - * 0b1..Capa Bank trimmings valid - */ -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK) - -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) -/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) - -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) -/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) - -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) -/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) -/*! @} */ - -/*! @name XTAL_16MHZ_CAPABANK_TRIM - Xtal 16MHz capabank triming. */ -/*! @{ */ - -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) -/*! TRIM_VALID - XTAL 16MHz capa bank trimmings - * 0b0..Capa Bank trimmings not valid. Default trimmings value are used - * 0b1..Capa Bank trimmings valid - */ -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK) - -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) -/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) - -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) -/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) - -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) -/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. - */ -#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) -/*! @} */ - -/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0] */ -/*! @{ */ - -#define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U) -#define FLASH_CMPA_ROTKH_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CMPA_ROTKH */ -#define FLASH_CMPA_ROTKH_COUNT (8U) - -/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ -/*! @{ */ - -#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) -#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CMPA_CUSTOMER_DEFINED */ -#define FLASH_CMPA_CUSTOMER_DEFINED_COUNT (56U) - -/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ -/*! @{ */ - -#define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U) -#define FLASH_CMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CMPA_SHA256_DIGEST */ -#define FLASH_CMPA_SHA256_DIGEST_COUNT (8U) - - -/*! - * @} - */ /* end of group FLASH_CMPA_Register_Masks */ - - -/* FLASH_CMPA - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH_CMPA base address */ - #define FLASH_CMPA_BASE (0x1009E400u) - /** Peripheral FLASH_CMPA base address */ - #define FLASH_CMPA_BASE_NS (0x9E400u) - /** Peripheral FLASH_CMPA base pointer */ - #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) - /** Peripheral FLASH_CMPA base pointer */ - #define FLASH_CMPA_NS ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS) - /** Array initializer of FLASH_CMPA peripheral base addresses */ - #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } - /** Array initializer of FLASH_CMPA peripheral base pointers */ - #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } - /** Array initializer of FLASH_CMPA peripheral base addresses */ - #define FLASH_CMPA_BASE_ADDRS_NS { FLASH_CMPA_BASE_NS } - /** Array initializer of FLASH_CMPA peripheral base pointers */ - #define FLASH_CMPA_BASE_PTRS_NS { FLASH_CMPA_NS } -#else - /** Peripheral FLASH_CMPA base address */ - #define FLASH_CMPA_BASE (0x9E400u) - /** Peripheral FLASH_CMPA base pointer */ - #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) - /** Array initializer of FLASH_CMPA peripheral base addresses */ - #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } - /** Array initializer of FLASH_CMPA peripheral base pointers */ - #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } -#endif - -/*! - * @} - */ /* end of group FLASH_CMPA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_KEY_STORE Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_KEY_STORE_Peripheral_Access_Layer FLASH_KEY_STORE Peripheral Access Layer - * @{ - */ - -/** FLASH_KEY_STORE - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0 */ - __IO uint32_t HEADER; /**< Valid Key Sore Header : 0x95959595, offset: 0x0 */ - __IO uint32_t PUF_DISCHARGE_TIME_IN_MS; /**< puf discharge time in ms., offset: 0x4 */ - } KEY_STORE_HEADER; - __IO uint32_t ACTIVATION_CODE[298]; /**< ., array offset: 0x8, array step: 0x4 */ - union { /* offset: 0x4B0 */ - __IO uint32_t SBKEY_KEY_CODE[14]; /**< ., array offset: 0x4B0, array step: 0x4 */ - struct { /* offset: 0x4B0 */ - __IO uint32_t SBKEY_HEADER0; /**< ., offset: 0x4B0 */ - __IO uint32_t SBKEY_HEADER1; /**< ., offset: 0x4B4 */ - __IO uint32_t SBKEY_BODY[12]; /**< ., array offset: 0x4B8, array step: 0x4 */ - } SBKEY_KEY_CODE_CORE; - }; - union { /* offset: 0x4E8 */ - __IO uint32_t USER_KEK_KEY_CODE[14]; /**< ., array offset: 0x4E8, array step: 0x4 */ - struct { /* offset: 0x4E8 */ - __IO uint32_t USER_KEK_HEADER0; /**< ., offset: 0x4E8 */ - __IO uint32_t USER_KEK_HEADER1; /**< ., offset: 0x4EC */ - __IO uint32_t USER_KEK_BODY[12]; /**< ., array offset: 0x4F0, array step: 0x4 */ - } USER_KEK_KEY_CODE_CORE; - }; - union { /* offset: 0x520 */ - __IO uint32_t UDS_KEY_CODE[14]; /**< ., array offset: 0x520, array step: 0x4 */ - struct { /* offset: 0x520 */ - __IO uint32_t UDS_HEADER0; /**< ., offset: 0x520 */ - __IO uint32_t UDS_HEADER1; /**< ., offset: 0x524 */ - __IO uint32_t UDS_BODY[12]; /**< ., array offset: 0x528, array step: 0x4 */ - } UDS_KEY_CODE_CORE; - }; - union { /* offset: 0x558 */ - __IO uint32_t PRINCE_REGION0_KEY_CODE[14]; /**< ., array offset: 0x558, array step: 0x4 */ - struct { /* offset: 0x558 */ - __IO uint32_t PRINCE_REGION0_HEADER0; /**< ., offset: 0x558 */ - __IO uint32_t PRINCE_REGION0_HEADER1; /**< ., offset: 0x55C */ - __IO uint32_t PRINCE_REGION0_BODY[12]; /**< ., array offset: 0x560, array step: 0x4 */ - } PRINCE_REGION0_KEY_CODE_CORE; - }; - union { /* offset: 0x590 */ - __IO uint32_t PRINCE_REGION1_KEY_CODE[14]; /**< ., array offset: 0x590, array step: 0x4 */ - struct { /* offset: 0x590 */ - __IO uint32_t PRINCE_REGION1_HEADER0; /**< ., offset: 0x590 */ - __IO uint32_t PRINCE_REGION1_HEADER1; /**< ., offset: 0x594 */ - __IO uint32_t PRINCE_REGION1_BODY[12]; /**< ., array offset: 0x598, array step: 0x4 */ - } PRINCE_REGION1_KEY_CODE_CORE; - }; - union { /* offset: 0x5C8 */ - __IO uint32_t PRINCE_REGION2_KEY_CODE[14]; /**< ., array offset: 0x5C8, array step: 0x4 */ - struct { /* offset: 0x5C8 */ - __IO uint32_t PRINCE_REGION2_HEADER0; /**< ., offset: 0x5C8 */ - __IO uint32_t PRINCE_REGION2_HEADER1; /**< ., offset: 0x5CC */ - __IO uint32_t PRINCE_REGION2_BODY[12]; /**< ., array offset: 0x5D0, array step: 0x4 */ - } PRINCE_REGION2_KEY_CODE_CORE; - }; -} FLASH_KEY_STORE_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_KEY_STORE Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_KEY_STORE_Register_Masks FLASH_KEY_STORE Register Masks - * @{ - */ - -/*! @name HEADER - Valid Key Sore Header : 0x95959595 */ -/*! @{ */ - -#define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK) -/*! @} */ - -/*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */ -/*! @{ */ - -#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK) -/*! @} */ - -/*! @name ACTIVATION_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_ACTIVATION_CODE */ -#define FLASH_KEY_STORE_ACTIVATION_CODE_COUNT (298U) - -/*! @name SBKEY_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_SBKEY_KEY_CODE */ -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_COUNT (14U) - -/*! @name SBKEY_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name SBKEY_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name SBKEY_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_SBKEY_BODY */ -#define FLASH_KEY_STORE_SBKEY_BODY_COUNT (12U) - -/*! @name USER_KEK_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_USER_KEK_KEY_CODE */ -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_COUNT (14U) - -/*! @name USER_KEK_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name USER_KEK_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name USER_KEK_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_USER_KEK_BODY */ -#define FLASH_KEY_STORE_USER_KEK_BODY_COUNT (12U) - -/*! @name UDS_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_UDS_KEY_CODE */ -#define FLASH_KEY_STORE_UDS_KEY_CODE_COUNT (14U) - -/*! @name UDS_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name UDS_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name UDS_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_UDS_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_UDS_BODY */ -#define FLASH_KEY_STORE_UDS_BODY_COUNT (12U) - -/*! @name PRINCE_REGION0_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE */ -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_COUNT (14U) - -/*! @name PRINCE_REGION0_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION0_BODY */ -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_COUNT (12U) - -/*! @name PRINCE_REGION1_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE */ -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_COUNT (14U) - -/*! @name PRINCE_REGION1_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION1_BODY */ -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_COUNT (12U) - -/*! @name PRINCE_REGION2_KEY_CODE - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE */ -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_COUNT (14U) - -/*! @name PRINCE_REGION2_HEADER0 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_HEADER1 - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U) -/*! TYPE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U) -/*! INDEX - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK) - -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U) -/*! SIZE - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_BODY - . */ -/*! @{ */ - -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U) -/*! FIELD - . - */ -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION2_BODY */ -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_COUNT (12U) - - -/*! - * @} - */ /* end of group FLASH_KEY_STORE_Register_Masks */ - - -/* FLASH_KEY_STORE - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLASH_KEY_STORE base address */ - #define FLASH_KEY_STORE_BASE (0x1009E600u) - /** Peripheral FLASH_KEY_STORE base address */ - #define FLASH_KEY_STORE_BASE_NS (0x9E600u) - /** Peripheral FLASH_KEY_STORE base pointer */ - #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) - /** Peripheral FLASH_KEY_STORE base pointer */ - #define FLASH_KEY_STORE_NS ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS) - /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ - #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } - /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ - #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } - /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ - #define FLASH_KEY_STORE_BASE_ADDRS_NS { FLASH_KEY_STORE_BASE_NS } - /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ - #define FLASH_KEY_STORE_BASE_PTRS_NS { FLASH_KEY_STORE_NS } -#else - /** Peripheral FLASH_KEY_STORE base address */ - #define FLASH_KEY_STORE_BASE (0x9E600u) - /** Peripheral FLASH_KEY_STORE base pointer */ - #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) - /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ - #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } - /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ - #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } -#endif - -/*! - * @} - */ /* end of group FLASH_KEY_STORE_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer - * @{ - */ - -/** FLEXCOMM - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4088]; - __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ - __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ -} FLEXCOMM_Type; - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks - * @{ - */ - -/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ -/*! @{ */ - -#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) -#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) -/*! PERSEL - Peripheral Select. This field is writable by software. - * 0b000..No peripheral selected. - * 0b001..USART function selected. - * 0b010..SPI function selected. - * 0b011..I2C function selected. - * 0b100..I2S transmit function selected. - * 0b101..I2S receive function selected. - * 0b110..Reserved - * 0b111..Reserved - */ -#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) - -#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) -#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) -/*! LOCK - Lock the peripheral select. This field is writable by software. - * 0b0..Peripheral select can be changed by software. - * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. - */ -#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) - -#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) -#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) -/*! USARTPRESENT - USART present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the USART function. - * 0b1..This Flexcomm includes the USART function. - */ -#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) - -#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) -#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) -/*! SPIPRESENT - SPI present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the SPI function. - * 0b1..This Flexcomm includes the SPI function. - */ -#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) - -#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) -#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) -/*! I2CPRESENT - I2C present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the I2C function. - * 0b1..This Flexcomm includes the I2C function. - */ -#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) - -#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) -#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) -/*! I2SPRESENT - I 2S present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the I2S function. - * 0b1..This Flexcomm includes the I2S function. - */ -#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) - -#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) -#define FLEXCOMM_PSELID_ID_SHIFT (12U) -/*! ID - Flexcomm ID. - */ -#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) -/*! @} */ - -/*! @name PID - Peripheral identification register. */ -/*! @{ */ - -#define FLEXCOMM_PID_APERTURE_MASK (0xFFU) -#define FLEXCOMM_PID_APERTURE_SHIFT (0U) -/*! APERTURE - size aperture for the register port on the bus (APB or AHB). - */ -#define FLEXCOMM_PID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_APERTURE_SHIFT)) & FLEXCOMM_PID_APERTURE_MASK) - -#define FLEXCOMM_PID_MINOR_REV_MASK (0xF00U) -#define FLEXCOMM_PID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation. - */ -#define FLEXCOMM_PID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MINOR_REV_SHIFT)) & FLEXCOMM_PID_MINOR_REV_MASK) - -#define FLEXCOMM_PID_MAJOR_REV_MASK (0xF000U) -#define FLEXCOMM_PID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation. - */ -#define FLEXCOMM_PID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MAJOR_REV_SHIFT)) & FLEXCOMM_PID_MAJOR_REV_MASK) - -#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) -#define FLEXCOMM_PID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function. - */ -#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLEXCOMM_Register_Masks */ - - -/* FLEXCOMM - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE (0x50086000u) - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE_NS (0x40086000u) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE (0x50087000u) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE_NS (0x40087000u) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE (0x50088000u) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE_NS (0x40088000u) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE (0x50089000u) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE_NS (0x40089000u) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE (0x5008A000u) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE_NS (0x4008A000u) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE (0x50096000u) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE_NS (0x40096000u) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE (0x50097000u) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE_NS (0x40097000u) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE (0x50098000u) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE_NS (0x40098000u) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE (0x5009F000u) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE_NS (0x4009F000u) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS) - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS_NS { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS_NS { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS } -#else - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE (0x40086000u) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE (0x40087000u) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE (0x40088000u) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE (0x40089000u) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE (0x4008A000u) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE (0x40096000u) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE (0x40097000u) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE (0x40098000u) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE (0x4009F000u) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } -#endif -/** Interrupt vectors for the FLEXCOMM peripheral type */ -#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } - -/*! - * @} - */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer - * @{ - */ - -/** GINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ - uint8_t RESERVED_0[28]; - __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[24]; - __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ -} GINT_Type; - -/* ---------------------------------------------------------------------------- - -- GINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Register_Masks GINT Register Masks - * @{ - */ - -/*! @name CTRL - GPIO grouped interrupt control register */ -/*! @{ */ - -#define GINT_CTRL_INT_MASK (0x1U) -#define GINT_CTRL_INT_SHIFT (0U) -/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. - * 0b0..No request. No interrupt request is pending. - * 0b1..Request active. Interrupt request is active. - */ -#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) - -#define GINT_CTRL_COMB_MASK (0x2U) -#define GINT_CTRL_COMB_SHIFT (1U) -/*! COMB - Combine enabled inputs for group interrupt - * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). - * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). - */ -#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) - -#define GINT_CTRL_TRIG_MASK (0x4U) -#define GINT_CTRL_TRIG_SHIFT (2U) -/*! TRIG - Group interrupt trigger - * 0b0..Edge-triggered. - * 0b1..Level-triggered. - */ -#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) -/*! @} */ - -/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ -/*! @{ */ - -#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) -#define GINT_PORT_POL_POL_SHIFT (0U) -/*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n - * of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to - * the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin - * contributes to the group interrupt. - */ -#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) -/*! @} */ - -/* The count of GINT_PORT_POL */ -#define GINT_PORT_POL_COUNT (2U) - -/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ -/*! @{ */ - -#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) -#define GINT_PORT_ENA_ENA_SHIFT (0U) -/*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the - * port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is - * enabled and contributes to the grouped interrupt. - */ -#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) -/*! @} */ - -/* The count of GINT_PORT_ENA */ -#define GINT_PORT_ENA_COUNT (2U) - - -/*! - * @} - */ /* end of group GINT_Register_Masks */ - - -/* GINT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral GINT0 base address */ - #define GINT0_BASE (0x50002000u) - /** Peripheral GINT0 base address */ - #define GINT0_BASE_NS (0x40002000u) - /** Peripheral GINT0 base pointer */ - #define GINT0 ((GINT_Type *)GINT0_BASE) - /** Peripheral GINT0 base pointer */ - #define GINT0_NS ((GINT_Type *)GINT0_BASE_NS) - /** Peripheral GINT1 base address */ - #define GINT1_BASE (0x50003000u) - /** Peripheral GINT1 base address */ - #define GINT1_BASE_NS (0x40003000u) - /** Peripheral GINT1 base pointer */ - #define GINT1 ((GINT_Type *)GINT1_BASE) - /** Peripheral GINT1 base pointer */ - #define GINT1_NS ((GINT_Type *)GINT1_BASE_NS) - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS { GINT0, GINT1 } - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS_NS { GINT0_BASE_NS, GINT1_BASE_NS } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS_NS { GINT0_NS, GINT1_NS } -#else - /** Peripheral GINT0 base address */ - #define GINT0_BASE (0x40002000u) - /** Peripheral GINT0 base pointer */ - #define GINT0 ((GINT_Type *)GINT0_BASE) - /** Peripheral GINT1 base address */ - #define GINT1_BASE (0x40003000u) - /** Peripheral GINT1 base pointer */ - #define GINT1 ((GINT_Type *)GINT1_BASE) - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS { GINT0, GINT1 } -#endif -/** Interrupt vectors for the GINT peripheral type */ -#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } - -/*! - * @} - */ /* end of group GINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer - * @{ - */ - -/** GPIO - Register Layout Typedef */ -typedef struct { - __IO uint8_t B[2][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ - uint8_t RESERVED_0[4032]; - __IO uint32_t W[2][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ - uint8_t RESERVED_1[3840]; - __IO uint32_t DIR[2]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */ - uint8_t RESERVED_2[120]; - __IO uint32_t MASK[2]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */ - uint8_t RESERVED_3[120]; - __IO uint32_t PIN[2]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */ - uint8_t RESERVED_4[120]; - __IO uint32_t MPIN[2]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */ - uint8_t RESERVED_5[120]; - __IO uint32_t SET[2]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */ - uint8_t RESERVED_6[120]; - __O uint32_t CLR[2]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */ - uint8_t RESERVED_7[120]; - __O uint32_t NOT[2]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */ - uint8_t RESERVED_8[120]; - __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ - uint8_t RESERVED_9[120]; - __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ - uint8_t RESERVED_10[120]; - __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ -} GPIO_Type; - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/*! @name B - Byte pin registers for all port GPIO pins */ -/*! @{ */ - -#define GPIO_B_PBYTE_MASK (0x1U) -#define GPIO_B_PBYTE_SHIFT (0U) -/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, - * except that pins configured as analog I/O always read as 0. One register for each port pin. - * Supported pins depends on the specific device and package. Write: loads the pin's output bit. - * One register for each port pin. Supported pins depends on the specific device and package. - */ -#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) -/*! @} */ - -/* The count of GPIO_B */ -#define GPIO_B_COUNT (2U) - -/* The count of GPIO_B */ -#define GPIO_B_COUNT2 (32U) - -/*! @name W - Word pin registers for all port GPIO pins */ -/*! @{ */ - -#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) -#define GPIO_W_PWORD_SHIFT (0U) -/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is - * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be - * read. Writing any value other than 0 will set the output bit. One register for each port pin. - * Supported pins depends on the specific device and package. - */ -#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) -/*! @} */ - -/* The count of GPIO_W */ -#define GPIO_W_COUNT (2U) - -/* The count of GPIO_W */ -#define GPIO_W_COUNT2 (32U) - -/*! @name DIR - Direction registers for all port GPIO pins */ -/*! @{ */ - -#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) -#define GPIO_DIR_DIRP_SHIFT (0U) -/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported - * pins depends on the specific device and package. 0 = input. 1 = output. - */ -#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) -/*! @} */ - -/* The count of GPIO_DIR */ -#define GPIO_DIR_COUNT (2U) - -/*! @name MASK - Mask register for all port GPIO pins */ -/*! @{ */ - -#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) -#define GPIO_MASK_MASKP_SHIFT (0U) -/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = - * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = - * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit - * not affected. - */ -#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) -/*! @} */ - -/* The count of GPIO_MASK */ -#define GPIO_MASK_COUNT (2U) - -/*! @name PIN - Port pin register for all port GPIO pins */ -/*! @{ */ - -#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) -#define GPIO_PIN_PORT_SHIFT (0U) -/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported - * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. - * 1 = Read: pin is high; write: set output bit. - */ -#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) -/*! @} */ - -/* The count of GPIO_PIN */ -#define GPIO_PIN_COUNT (2U) - -/*! @name MPIN - Masked port register for all port GPIO pins */ -/*! @{ */ - -#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) -#define GPIO_MPIN_MPORTP_SHIFT (0U) -/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on - * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK - * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 - * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit - * if the corresponding bit in the MASK register is 0. - */ -#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) -/*! @} */ - -/* The count of GPIO_MPIN */ -#define GPIO_MPIN_COUNT (2U) - -/*! @name SET - Write: Set register for port. Read: output bits for port */ -/*! @{ */ - -#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) -#define GPIO_SET_SETP_SHIFT (0U) -/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on - * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output - * bit; write: set output bit. - */ -#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) -/*! @} */ - -/* The count of GPIO_SET */ -#define GPIO_SET_COUNT (2U) - -/*! @name CLR - Clear port for all port GPIO pins */ -/*! @{ */ - -#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) -#define GPIO_CLR_CLRP_SHIFT (0U) -/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the - * specific device and package. 0 = No operation. 1 = Clear output bit. - */ -#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) -/*! @} */ - -/* The count of GPIO_CLR */ -#define GPIO_CLR_COUNT (2U) - -/*! @name NOT - Toggle port for all port GPIO pins */ -/*! @{ */ - -#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) -#define GPIO_NOT_NOTP_SHIFT (0U) -/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the - * specific device and package. 0 = no operation. 1 = Toggle output bit. - */ -#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) -/*! @} */ - -/* The count of GPIO_NOT */ -#define GPIO_NOT_COUNT (2U) - -/*! @name DIRSET - Set pin direction bits for port */ -/*! @{ */ - -#define GPIO_DIRSET_DIRSETP_MASK (0xFFFFFFFFU) -#define GPIO_DIRSET_DIRSETP_SHIFT (0U) -/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on - * the specific device and package. 0 = No operation. 1 = Set direction bit. - */ -#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) -/*! @} */ - -/* The count of GPIO_DIRSET */ -#define GPIO_DIRSET_COUNT (2U) - -/*! @name DIRCLR - Clear pin direction bits for port */ -/*! @{ */ - -#define GPIO_DIRCLR_DIRCLRP_MASK (0xFFFFFFFFU) -#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) -/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on - * the specific device and package. 0 = No operation. 1 = Clear direction bit. - */ -#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) -/*! @} */ - -/* The count of GPIO_DIRCLR */ -#define GPIO_DIRCLR_COUNT (2U) - -/*! @name DIRNOT - Toggle pin direction bits for port */ -/*! @{ */ - -#define GPIO_DIRNOT_DIRNOTP_MASK (0xFFFFFFFFU) -#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) -/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends - * on the specific device and package. 0 = no operation. 1 = Toggle direction bit. - */ -#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) -/*! @} */ - -/* The count of GPIO_DIRNOT */ -#define GPIO_DIRNOT_COUNT (2U) - - -/*! - * @} - */ /* end of group GPIO_Register_Masks */ - - -/* GPIO - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral GPIO base address */ - #define GPIO_BASE (0x5008C000u) - /** Peripheral GPIO base address */ - #define GPIO_BASE_NS (0x4008C000u) - /** Peripheral GPIO base pointer */ - #define GPIO ((GPIO_Type *)GPIO_BASE) - /** Peripheral GPIO base pointer */ - #define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE (0x500A8000u) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE_NS (0x400A8000u) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS) - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO, SECGPIO } - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS_NS { GPIO_BASE_NS, SECGPIO_BASE_NS } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS_NS { GPIO_NS, SECGPIO_NS } -#else - /** Peripheral GPIO base address */ - #define GPIO_BASE (0x4008C000u) - /** Peripheral GPIO base pointer */ - #define GPIO ((GPIO_Type *)GPIO_BASE) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE (0x400A8000u) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO, SECGPIO } -#endif - -/*! - * @} - */ /* end of group GPIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- HASHCRYPT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup HASHCRYPT_Peripheral_Access_Layer HASHCRYPT Peripheral Access Layer - * @{ - */ - -/** HASHCRYPT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register to enable and operate Hash and Crypto, offset: 0x0 */ - __IO uint32_t STATUS; /**< Indicates status of Hash peripheral., offset: 0x4 */ - __IO uint32_t INTENSET; /**< Write 1 to enable interrupts; reads back with which are set., offset: 0x8 */ - __IO uint32_t INTENCLR; /**< Write 1 to clear interrupts., offset: 0xC */ - __IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available), offset: 0x10 */ - __IO uint32_t MEMADDR; /**< Address to start memory access from (if available)., offset: 0x14 */ - uint8_t RESERVED_0[8]; - __O uint32_t INDATA; /**< Input of 16 words at a time to load up buffer., offset: 0x20 */ - __O uint32_t ALIAS[7]; /**< , array offset: 0x24, array step: 0x4 */ - __I uint32_t DIGEST0[8]; /**< , array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_1[32]; - __IO uint32_t CRYPTCFG; /**< Crypto settings for AES and Salsa and ChaCha, offset: 0x80 */ - __I uint32_t CONFIG; /**< Returns the configuration of this block in this chip - indicates what services are available., offset: 0x84 */ - uint8_t RESERVED_2[4]; - __IO uint32_t LOCK; /**< Lock register allows locking to the current security level or unlocking by the lock holding level., offset: 0x8C */ - __O uint32_t MASK[4]; /**< , array offset: 0x90, array step: 0x4 */ -} HASHCRYPT_Type; - -/* ---------------------------------------------------------------------------- - -- HASHCRYPT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup HASHCRYPT_Register_Masks HASHCRYPT Register Masks - * @{ - */ - -/*! @name CTRL - Control register to enable and operate Hash and Crypto */ -/*! @{ */ - -#define HASHCRYPT_CTRL_MODE_MASK (0x7U) -#define HASHCRYPT_CTRL_MODE_SHIFT (0U) -/*! Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if - * specific modes beyond SHA1 and SHA2-256 are available. - * 0b000..Disabled - * 0b001..SHA1 is enabled - * 0b010..SHA2-256 is enabled - * 0b100..AES if available (see also CRYPTCFG register for more controls) - * 0b101..ICB-AES if available (see also CRYPTCFG register for more controls) - */ -#define HASHCRYPT_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK) - -#define HASHCRYPT_CTRL_NEW_HASH_MASK (0x10U) -#define HASHCRYPT_CTRL_NEW_HASH_SHIFT (4U) -/*! New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING - * Status bit will clear for a cycle during the initialization from New=1. - * 0b1..Starts a new Hash/Crypto and initializes the Digest/Result. - */ -#define HASHCRYPT_CTRL_NEW_HASH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK) - -#define HASHCRYPT_CTRL_DMA_I_MASK (0x100U) -#define HASHCRYPT_CTRL_DMA_I_SHIFT (8U) -/*! DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words - * and then will process the Hash. If Cryptographic, it will load as many words as needed, - * including key if not already loaded. It will then request again. Normal model is that the DMA - * interrupts the processor when its length expires. Note that if the processor will write the key and - * optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be - * expected to load those for the 1st block (when needed). - * 0b0..DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used. - * 0b1..DMA will push in the data. - */ -#define HASHCRYPT_CTRL_DMA_I(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK) - -#define HASHCRYPT_CTRL_DMA_O_MASK (0x200U) -#define HASHCRYPT_CTRL_DMA_O_SHIFT (9U) -/*! DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the - * DMA has to know to switch direction and the locations. This can be used for crypto uses. - * 0b0..DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. - */ -#define HASHCRYPT_CTRL_DMA_O(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK) - -#define HASHCRYPT_CTRL_HASHSWPB_MASK (0x1000U) -#define HASHCRYPT_CTRL_HASHSWPB_SHIFT (12U) -/*! HASHSWPB - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB - * is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For - * cryptographic swapping, see the CRYPTCFG register. - */ -#define HASHCRYPT_CTRL_HASHSWPB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK) -/*! @} */ - -/*! @name STATUS - Indicates status of Hash peripheral. */ -/*! @{ */ - -#define HASHCRYPT_STATUS_WAITING_MASK (0x1U) -#define HASHCRYPT_STATUS_WAITING_SHIFT (0U) -/*! WAITING - If 1, the block is waiting for more data to process. - * 0b0..Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set - * if IsLast is set nor will it set until at least 1 word is read of the output. - * 0b1..Waiting for data to be written in (16 words) - */ -#define HASHCRYPT_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK) - -#define HASHCRYPT_STATUS_DIGEST_MASK (0x2U) -#define HASHCRYPT_STATUS_DIGEST_SHIFT (1U) -/*! DIGEST - For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block - * already started. For Cryptographic uses, this will be set for each block processed, indicating - * OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared - * when any data is written, when New is written, for Cryptographic uses when the last word is read - * out, or when the block is disabled. - * 0b0..No Digest is ready - * 0b1..Digest is ready. Application may read it or may write more data - */ -#define HASHCRYPT_STATUS_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_SHIFT)) & HASHCRYPT_STATUS_DIGEST_MASK) - -#define HASHCRYPT_STATUS_ERROR_MASK (0x4U) -#define HASHCRYPT_STATUS_ERROR_SHIFT (2U) -/*! ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA - * was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT - * field will indicate which block it was on. - * 0b0..No error. - * 0b1..An error occurred since last cleared (written 1 to clear). - */ -#define HASHCRYPT_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK) - -#define HASHCRYPT_STATUS_NEEDKEY_MASK (0x10U) -#define HASHCRYPT_STATUS_NEEDKEY_SHIFT (4U) -/*! NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING) - * 0b0..No Key is needed and writes will not be treated as Key - * 0b1..Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. - */ -#define HASHCRYPT_STATUS_NEEDKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK) - -#define HASHCRYPT_STATUS_NEEDIV_MASK (0x20U) -#define HASHCRYPT_STATUS_NEEDIV_SHIFT (5U) -/*! NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING) - * 0b0..No IV/Nonce is needed, either because written already or because not needed. - * 0b1..IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. - */ -#define HASHCRYPT_STATUS_NEEDIV(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK) - -#define HASHCRYPT_STATUS_ICBIDX_MASK (0x3F0000U) -#define HASHCRYPT_STATUS_ICBIDX_SHIFT (16U) -/*! ICBIDX - If ICB-AES is selected, then reads as the ICB index count based on ICBSTRM (from - * CRYPTCFG). That is, if 3 bits of ICBSTRM, then this will count from 0 to 7 and then back to 0. On 0, - * it has to compute the full ICB, quicker when not 0. - */ -#define HASHCRYPT_STATUS_ICBIDX(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ICBIDX_SHIFT)) & HASHCRYPT_STATUS_ICBIDX_MASK) -/*! @} */ - -/*! @name INTENSET - Write 1 to enable interrupts; reads back with which are set. */ -/*! @{ */ - -#define HASHCRYPT_INTENSET_WAITING_MASK (0x1U) -#define HASHCRYPT_INTENSET_WAITING_SHIFT (0U) -/*! WAITING - Indicates if should interrupt when waiting for data input. - * 0b0..Will not interrupt when waiting. - * 0b1..Will interrupt when waiting - */ -#define HASHCRYPT_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK) - -#define HASHCRYPT_INTENSET_DIGEST_MASK (0x2U) -#define HASHCRYPT_INTENSET_DIGEST_SHIFT (1U) -/*! DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). - * 0b0..Will not interrupt when Digest is ready - * 0b1..Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). - */ -#define HASHCRYPT_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK) - -#define HASHCRYPT_INTENSET_ERROR_MASK (0x4U) -#define HASHCRYPT_INTENSET_ERROR_SHIFT (2U) -/*! ERROR - Indicates if should interrupt on an ERROR (as defined in Status) - * 0b0..Will not interrupt on Error. - * 0b1..Will interrupt on Error (until cleared). - */ -#define HASHCRYPT_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_ERROR_SHIFT)) & HASHCRYPT_INTENSET_ERROR_MASK) -/*! @} */ - -/*! @name INTENCLR - Write 1 to clear interrupts. */ -/*! @{ */ - -#define HASHCRYPT_INTENCLR_WAITING_MASK (0x1U) -#define HASHCRYPT_INTENCLR_WAITING_SHIFT (0U) -/*! WAITING - Write 1 to clear mask. - */ -#define HASHCRYPT_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK) - -#define HASHCRYPT_INTENCLR_DIGEST_MASK (0x2U) -#define HASHCRYPT_INTENCLR_DIGEST_SHIFT (1U) -/*! DIGEST - Write 1 to clear mask. - */ -#define HASHCRYPT_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK) - -#define HASHCRYPT_INTENCLR_ERROR_MASK (0x4U) -#define HASHCRYPT_INTENCLR_ERROR_SHIFT (2U) -/*! ERROR - Write 1 to clear mask. - */ -#define HASHCRYPT_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK) -/*! @} */ - -/*! @name MEMCTRL - Setup Master to access memory (if available) */ -/*! @{ */ - -#define HASHCRYPT_MEMCTRL_MASTER_MASK (0x1U) -#define HASHCRYPT_MEMCTRL_MASTER_SHIFT (0U) -/*! MASTER - Enables mastering. - * 0b0..Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. - * 0b1..Mastering is enabled and DMA and INDATA should not be used. - */ -#define HASHCRYPT_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK) - -#define HASHCRYPT_MEMCTRL_COUNT_MASK (0x7FF0000U) -#define HASHCRYPT_MEMCTRL_COUNT_SHIFT (16U) -/*! COUNT - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks - * to copy starting at MEMADDR. This register will decrement after each block is copied, ending - * in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA - * interrupt will occur on ever block. If a bus error occurs, it will stop with this field set - * to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) - * blocks to hash. - */ -#define HASHCRYPT_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK) -/*! @} */ - -/*! @name MEMADDR - Address to start memory access from (if available). */ -/*! @{ */ - -#define HASHCRYPT_MEMADDR_BASE_MASK (0xFFFFFFFFU) -#define HASHCRYPT_MEMADDR_BASE_SHIFT (0U) -/*! BASE - Address base to start copying from, word aligned (so bits 1:0 must be 0). This field will - * advance as it processes the words. If it fails with a bus error, the register will contain - * the failing word. N:Address in Flash or RAM space; RAM only as mapped in this part. May also be - * able to address SPIFI. - */ -#define HASHCRYPT_MEMADDR_BASE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK) -/*! @} */ - -/*! @name INDATA - Input of 16 words at a time to load up buffer. */ -/*! @{ */ - -#define HASHCRYPT_INDATA_DATA_MASK (0xFFFFFFFFU) -#define HASHCRYPT_INDATA_DATA_SHIFT (0U) -/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this - * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as - * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block - * will swap the word to restore into big endian. - */ -#define HASHCRYPT_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK) -/*! @} */ - -/*! @name ALIAS - */ -/*! @{ */ - -#define HASHCRYPT_ALIAS_DATA_MASK (0xFFFFFFFFU) -#define HASHCRYPT_ALIAS_DATA_SHIFT (0U) -/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this - * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as - * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block - * will swap the word to restore into big endian. - */ -#define HASHCRYPT_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK) -/*! @} */ - -/* The count of HASHCRYPT_ALIAS */ -#define HASHCRYPT_ALIAS_COUNT (7U) - -/*! @name DIGEST0 - */ -/*! @{ */ - -#define HASHCRYPT_DIGEST0_DIGEST_MASK (0xFFFFFFFFU) -#define HASHCRYPT_DIGEST0_DIGEST_SHIFT (0U) -/*! DIGEST - One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1. - */ -#define HASHCRYPT_DIGEST0_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_DIGEST0_DIGEST_SHIFT)) & HASHCRYPT_DIGEST0_DIGEST_MASK) -/*! @} */ - -/* The count of HASHCRYPT_DIGEST0 */ -#define HASHCRYPT_DIGEST0_COUNT (8U) - -/*! @name CRYPTCFG - Crypto settings for AES and Salsa and ChaCha */ -/*! @{ */ - -#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK (0x1U) -#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT (0U) -/*! MSW1ST_OUT - If 1, OUTDATA0 will be read Most significant word 1st for AES. Else it will be read - * in normal little endian - Least significant word 1st. Note: only if allowed by configuration. - */ -#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK) - -#define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK (0x2U) -#define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT (1U) -/*! SWAPKEY - If 1, will Swap the key input (bytes in each word). - */ -#define HASHCRYPT_CRYPTCFG_SWAPKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK) - -#define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK (0x4U) -#define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT (2U) -/*! SWAPDAT - If 1, will SWAP the data and IV inputs (bytes in each word). - */ -#define HASHCRYPT_CRYPTCFG_SWAPDAT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK) - -#define HASHCRYPT_CRYPTCFG_MSW1ST_MASK (0x8U) -#define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT (3U) -/*! MSW1ST - If 1, load of key, IV, and data is MSW 1st for AES. Else, the words are little endian. - * Note: only if allowed by configuration. - */ -#define HASHCRYPT_CRYPTCFG_MSW1ST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK) - -#define HASHCRYPT_CRYPTCFG_AESMODE_MASK (0x30U) -#define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT (4U) -/*! AESMODE - AES Cipher mode to use if plain AES - * 0b00..ECB - used as is - * 0b01..CBC mode (see details on IV/nonce) - * 0b10..CTR mode (see details on IV/nonce). See also AESCTRPOS. - * 0b11..reserved - */ -#define HASHCRYPT_CRYPTCFG_AESMODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK) - -#define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK (0x40U) -#define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT (6U) -/*! AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB - * 0b0..Encrypt - * 0b1..Decrypt - */ -#define HASHCRYPT_CRYPTCFG_AESDECRYPT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK) - -#define HASHCRYPT_CRYPTCFG_AESSECRET_MASK (0x80U) -#define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT (7U) -/*! AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are - * used, only the highest level is permitted to select this. - * 0b0..User key provided in normal way - * 0b1..Secret key provided in hidden way by HW - */ -#define HASHCRYPT_CRYPTCFG_AESSECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK) - -#define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK (0x300U) -#define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT (8U) -/*! AESKEYSZ - Sets the AES key size - * 0b00..128 bit key - * 0b01..192 bit key - * 0b10..256 bit key - * 0b11..reserved - */ -#define HASHCRYPT_CRYPTCFG_AESKEYSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK) - -#define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK (0x1C00U) -#define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT (10U) -/*! AESCTRPOS - Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for - * Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if - * using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other - * use CTR should use ECB directly and do its own XOR and so on. - */ -#define HASHCRYPT_CRYPTCFG_AESCTRPOS(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK) - -#define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK (0x10000U) -#define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT (16U) -/*! STREAMLAST - Is 1 if last stream block. If not 1, then the engine will compute the next "hash". - */ -#define HASHCRYPT_CRYPTCFG_STREAMLAST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK) - -#define HASHCRYPT_CRYPTCFG_ICBSZ_MASK (0x300000U) -#define HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT (20U) -/*! ICBSZ - This sets the ICB size between 32 and 128 bits, using the following rules. Note that the - * counter is assumed to occupy the low order bits of the IV. - * 0b00..32 bits of the IV/ctr are used (from 127:96) - * 0b01..64 bits of the IV/ctr are used (from 127:64) - * 0b10..96 bits of the IV/ctr are used (from 127:32) - * 0b11..All 128 bits of the IV/ctr are used - */ -#define HASHCRYPT_CRYPTCFG_ICBSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSZ_MASK) - -#define HASHCRYPT_CRYPTCFG_ICBSTRM_MASK (0xC00000U) -#define HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT (22U) -/*! ICBSTRM - The size of the ICB-AES stream that can be pushed before needing to compute a new - * IV/ctr (counter start). This optimizes the performance of the stream of blocks after the 1st. - * 0b00..8 blocks - * 0b01..16 blocks - * 0b10..32 blocks - * 0b11..64 blocks - */ -#define HASHCRYPT_CRYPTCFG_ICBSTRM(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSTRM_MASK) -/*! @} */ - -/*! @name CONFIG - Returns the configuration of this block in this chip - indicates what services are available. */ -/*! @{ */ - -#define HASHCRYPT_CONFIG_DUAL_MASK (0x1U) -#define HASHCRYPT_CONFIG_DUAL_SHIFT (0U) -/*! DUAL - 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit - */ -#define HASHCRYPT_CONFIG_DUAL(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK) - -#define HASHCRYPT_CONFIG_DMA_MASK (0x2U) -#define HASHCRYPT_CONFIG_DMA_SHIFT (1U) -/*! DMA - 1 if DMA is connected - */ -#define HASHCRYPT_CONFIG_DMA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK) - -#define HASHCRYPT_CONFIG_AHB_MASK (0x8U) -#define HASHCRYPT_CONFIG_AHB_SHIFT (3U) -/*! AHB - 1 if AHB Master is enabled - */ -#define HASHCRYPT_CONFIG_AHB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK) - -#define HASHCRYPT_CONFIG_AES_MASK (0x40U) -#define HASHCRYPT_CONFIG_AES_SHIFT (6U) -/*! AES - 1 if AES 128 included - */ -#define HASHCRYPT_CONFIG_AES(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK) - -#define HASHCRYPT_CONFIG_AESKEY_MASK (0x80U) -#define HASHCRYPT_CONFIG_AESKEY_SHIFT (7U) -/*! AESKEY - 1 if AES 192 and 256 also included - */ -#define HASHCRYPT_CONFIG_AESKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK) - -#define HASHCRYPT_CONFIG_SECRET_MASK (0x100U) -#define HASHCRYPT_CONFIG_SECRET_SHIFT (8U) -/*! SECRET - 1 if AES Secret key available - */ -#define HASHCRYPT_CONFIG_SECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK) - -#define HASHCRYPT_CONFIG_ICB_MASK (0x800U) -#define HASHCRYPT_CONFIG_ICB_SHIFT (11U) -/*! ICB - 1 if ICB over AES included - */ -#define HASHCRYPT_CONFIG_ICB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_ICB_SHIFT)) & HASHCRYPT_CONFIG_ICB_MASK) -/*! @} */ - -/*! @name LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. */ -/*! @{ */ - -#define HASHCRYPT_LOCK_SECLOCK_MASK (0x3U) -#define HASHCRYPT_LOCK_SECLOCK_SHIFT (0U) -/*! SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. - * If locked already, may only write if at same or higher security level as lock. Reads as: 0 if - * unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the - * only readable registers if locked and current state is lower than lock level. - * 0b00..Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests. - * 0b01..Locks to the current security level. AHB Master will issue requests at this level. - */ -#define HASHCRYPT_LOCK_SECLOCK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK) - -#define HASHCRYPT_LOCK_PATTERN_MASK (0xFFF0U) -#define HASHCRYPT_LOCK_PATTERN_SHIFT (4U) -/*! PATTERN - Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0 - */ -#define HASHCRYPT_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK) -/*! @} */ - -/*! @name MASK - */ -/*! @{ */ - -#define HASHCRYPT_MASK_MASK_MASK (0xFFFFFFFFU) -#define HASHCRYPT_MASK_MASK_SHIFT (0U) -/*! MASK - A random word. - */ -#define HASHCRYPT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK) -/*! @} */ - -/* The count of HASHCRYPT_MASK */ -#define HASHCRYPT_MASK_COUNT (4U) - - -/*! - * @} - */ /* end of group HASHCRYPT_Register_Masks */ - - -/* HASHCRYPT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral HASHCRYPT base address */ - #define HASHCRYPT_BASE (0x500A4000u) - /** Peripheral HASHCRYPT base address */ - #define HASHCRYPT_BASE_NS (0x400A4000u) - /** Peripheral HASHCRYPT base pointer */ - #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) - /** Peripheral HASHCRYPT base pointer */ - #define HASHCRYPT_NS ((HASHCRYPT_Type *)HASHCRYPT_BASE_NS) - /** Array initializer of HASHCRYPT peripheral base addresses */ - #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } - /** Array initializer of HASHCRYPT peripheral base pointers */ - #define HASHCRYPT_BASE_PTRS { HASHCRYPT } - /** Array initializer of HASHCRYPT peripheral base addresses */ - #define HASHCRYPT_BASE_ADDRS_NS { HASHCRYPT_BASE_NS } - /** Array initializer of HASHCRYPT peripheral base pointers */ - #define HASHCRYPT_BASE_PTRS_NS { HASHCRYPT_NS } -#else - /** Peripheral HASHCRYPT base address */ - #define HASHCRYPT_BASE (0x400A4000u) - /** Peripheral HASHCRYPT base pointer */ - #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) - /** Array initializer of HASHCRYPT peripheral base addresses */ - #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } - /** Array initializer of HASHCRYPT peripheral base pointers */ - #define HASHCRYPT_BASE_PTRS { HASHCRYPT } -#endif - -/*! - * @} - */ /* end of group HASHCRYPT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2C Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer - * @{ - */ - -/** I2C - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[2048]; - __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ - __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ - __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ - __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ - __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ - __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ - uint8_t RESERVED_1[4]; - __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ - __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ - __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ - uint8_t RESERVED_2[20]; - __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ - __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ - __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ - __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ - uint8_t RESERVED_3[36]; - __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ - uint8_t RESERVED_4[1912]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} I2C_Type; - -/* ---------------------------------------------------------------------------- - -- I2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Register_Masks I2C Register Masks - * @{ - */ - -/*! @name CFG - Configuration for shared functions. */ -/*! @{ */ - -#define I2C_CFG_MSTEN_MASK (0x1U) -#define I2C_CFG_MSTEN_SHIFT (0U) -/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not - * changed, but the Master function is internally reset. - * 0b0..Disabled. The I2C Master function is disabled. - * 0b1..Enabled. The I2C Master function is enabled. - */ -#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) - -#define I2C_CFG_SLVEN_MASK (0x2U) -#define I2C_CFG_SLVEN_SHIFT (1U) -/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not - * changed, but the Slave function is internally reset. - * 0b0..Disabled. The I2C slave function is disabled. - * 0b1..Enabled. The I2C slave function is enabled. - */ -#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) - -#define I2C_CFG_MONEN_MASK (0x4U) -#define I2C_CFG_MONEN_SHIFT (2U) -/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not - * changed, but the Monitor function is internally reset. - * 0b0..Disabled. The I2C Monitor function is disabled. - * 0b1..Enabled. The I2C Monitor function is enabled. - */ -#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) - -#define I2C_CFG_TIMEOUTEN_MASK (0x8U) -#define I2C_CFG_TIMEOUTEN_SHIFT (3U) -/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. - * 0b0..Disabled. Time-out function is disabled. - * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause - * interrupts if they are enabled. Typically, only one time-out will be used in a system. - */ -#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) - -#define I2C_CFG_MONCLKSTR_MASK (0x10U) -#define I2C_CFG_MONCLKSTR_SHIFT (4U) -/*! MONCLKSTR - Monitor function Clock Stretching. - * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able - * to read data provided by the Monitor function before it is overwritten. This mode may be used when - * non-invasive monitoring is critical. - * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can - * read all incoming data supplied by the Monitor function. - */ -#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) - -#define I2C_CFG_HSCAPABLE_MASK (0x20U) -#define I2C_CFG_HSCAPABLE_SHIFT (5U) -/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive - * and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies - * to all functions: Master, Slave, and Monitor. - * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the - * extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, - * such as changing the drive strength or filtering, must be made by software via the IOCON register associated - * with each I2C pin, - * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support - * High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more - * information. - */ -#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) -/*! @} */ - -/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ -/*! @{ */ - -#define I2C_STAT_MSTPENDING_MASK (0x1U) -#define I2C_STAT_MSTPENDING_SHIFT (0U) -/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on - * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what - * type of software service if any the master expects. This flag will cause an interrupt when set - * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling - * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle - * state, and no communication is needed, mask this interrupt. - * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. - * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the - * idle state, it is waiting to receive or transmit data or the NACK bit. - */ -#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) - -#define I2C_STAT_MSTSTATE_MASK (0xEU) -#define I2C_STAT_MSTSTATE_SHIFT (1U) -/*! MSTSTATE - Master State code. The master state code reflects the master state when the - * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field - * indicates a specific required service for the Master function. All other values are reserved. See - * Table 400 for details of state values and appropriate responses. - * 0b000..Idle. The Master function is available to be used for a new transaction. - * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. - * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. - * 0b011..NACK Address. Slave NACKed address. - * 0b100..NACK Data. Slave NACKed transmitted data. - */ -#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) - -#define I2C_STAT_MSTARBLOSS_MASK (0x10U) -#define I2C_STAT_MSTARBLOSS_SHIFT (4U) -/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to - * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - * 0b0..No Arbitration Loss has occurred. - * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master - * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, - * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. - */ -#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) - -#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) -/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to - * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - * 0b0..No Start/Stop Error has occurred. - * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is - * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an - * idle state, no action is required. A request for a Start could be made, or software could attempt to insure - * that the bus has not stalled. - */ -#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) - -#define I2C_STAT_SLVPENDING_MASK (0x100U) -#define I2C_STAT_SLVPENDING_SHIFT (8U) -/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue - * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if - * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the - * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is - * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time - * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section - * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are - * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must - * also be detected automatically, since the address must be acknowledged before the clock can be - * stretched. - * 0b0..In progress. The Slave function does not currently need service. - * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. - */ -#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) - -#define I2C_STAT_SLVSTATE_MASK (0x600U) -#define I2C_STAT_SLVSTATE_SHIFT (9U) -/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for - * the Slave function. All other values are reserved. See Table 401 for state values and actions. - * note that the occurrence of some states and how they are handled are affected by DMA mode and - * Automatic Operation modes. - * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. - * 0b01..Slave receive. Received data is available (Slave Receiver mode). - * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). - */ -#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) - -#define I2C_STAT_SLVNOTSTR_MASK (0x800U) -#define I2C_STAT_SLVNOTSTR_SHIFT (11U) -/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. - * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave - * operation. This read-only flag reflects the slave function status in real time. - * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. - * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or - * Power-down mode could be entered at this time. - */ -#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) - -#define I2C_STAT_SLVIDX_MASK (0x3000U) -#define I2C_STAT_SLVIDX_SHIFT (12U) -/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been - * selected by receiving an address that matches one of the slave addresses defined by any enabled - * slave address registers, and provides an identification of the address that was matched. It is - * possible that more than one address could be matched, but only one match can be reported here. - * 0b00..Address 0. Slave address 0 was matched. - * 0b01..Address 1. Slave address 1 was matched. - * 0b10..Address 2. Slave address 2 was matched. - * 0b11..Address 3. Slave address 3 was matched. - */ -#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) - -#define I2C_STAT_SLVSEL_MASK (0x4000U) -#define I2C_STAT_SLVSEL_SHIFT (14U) -/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave - * function to acknowledge the address, or when the address has been automatically acknowledged. - * It is cleared when another address cycle presents an address that does not match an enabled - * address on the Slave function, when slave software decides to NACK a matched address, when - * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of - * Automatic Operation. SLVSEL is not cleared if software NACKs data. - * 0b0..Not selected. The Slave function is not currently selected. - * 0b1..Selected. The Slave function is currently selected. - */ -#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) - -#define I2C_STAT_SLVDESEL_MASK (0x8000U) -#define I2C_STAT_SLVDESEL_SHIFT (15U) -/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via - * INTENSET. This flag can be cleared by writing a 1 to this bit. - * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently - * selected. That information can be found in the SLVSEL flag. - * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag - * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. - */ -#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) - -#define I2C_STAT_MONRDY_MASK (0x10000U) -#define I2C_STAT_MONRDY_SHIFT (16U) -/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. - * 0b0..No data. The Monitor function does not currently have data available. - * 0b1..Data waiting. The Monitor function has data waiting to be read. - */ -#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) - -#define I2C_STAT_MONOV_MASK (0x20000U) -#define I2C_STAT_MONOV_SHIFT (17U) -/*! MONOV - Monitor Overflow flag. - * 0b0..No overrun. Monitor data has not overrun. - * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not - * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. - */ -#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) - -#define I2C_STAT_MONACTIVE_MASK (0x40000U) -#define I2C_STAT_MONACTIVE_SHIFT (18U) -/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to - * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred - * more recently than a bus Stop. - * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. - * 0b1..Active. The Monitor function considers the I2C bus to be active. - */ -#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) - -#define I2C_STAT_MONIDLE_MASK (0x80000U) -#define I2C_STAT_MONIDLE_SHIFT (19U) -/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change - * from active to inactive. This can be used by software to decide when to process data - * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the - * INTENSET register. The flag can be cleared by writing a 1 to this bit. - * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. - * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. - */ -#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) - -#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) -/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been - * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock - * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus - * is idle. - * 0b0..No time-out. I2C bus events have not caused a time-out. - * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. - */ -#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) - -#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) -/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the - * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. - * 0b0..No time-out. SCL low time has not caused a time-out. - * 0b1..Time-out. SCL low time has caused a time-out. - */ -#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable Set and read register. */ -/*! @{ */ - -#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) -#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) -/*! MSTPENDINGEN - Master Pending interrupt Enable. - * 0b0..Disabled. The MstPending interrupt is disabled. - * 0b1..Enabled. The MstPending interrupt is enabled. - */ -#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) - -#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) -#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) -/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. - * 0b0..Disabled. The MstArbLoss interrupt is disabled. - * 0b1..Enabled. The MstArbLoss interrupt is enabled. - */ -#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) - -#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) -#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) -/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. - * 0b0..Disabled. The MstStStpErr interrupt is disabled. - * 0b1..Enabled. The MstStStpErr interrupt is enabled. - */ -#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) - -#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) -#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) -/*! SLVPENDINGEN - Slave Pending interrupt Enable. - * 0b0..Disabled. The SlvPending interrupt is disabled. - * 0b1..Enabled. The SlvPending interrupt is enabled. - */ -#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) - -#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) -#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) -/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. - * 0b0..Disabled. The SlvNotStr interrupt is disabled. - * 0b1..Enabled. The SlvNotStr interrupt is enabled. - */ -#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) - -#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) -#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) -/*! SLVDESELEN - Slave Deselect interrupt Enable. - * 0b0..Disabled. The SlvDeSel interrupt is disabled. - * 0b1..Enabled. The SlvDeSel interrupt is enabled. - */ -#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) - -#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) -#define I2C_INTENSET_MONRDYEN_SHIFT (16U) -/*! MONRDYEN - Monitor data Ready interrupt Enable. - * 0b0..Disabled. The MonRdy interrupt is disabled. - * 0b1..Enabled. The MonRdy interrupt is enabled. - */ -#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) - -#define I2C_INTENSET_MONOVEN_MASK (0x20000U) -#define I2C_INTENSET_MONOVEN_SHIFT (17U) -/*! MONOVEN - Monitor Overrun interrupt Enable. - * 0b0..Disabled. The MonOv interrupt is disabled. - * 0b1..Enabled. The MonOv interrupt is enabled. - */ -#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) - -#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) -#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) -/*! MONIDLEEN - Monitor Idle interrupt Enable. - * 0b0..Disabled. The MonIdle interrupt is disabled. - * 0b1..Enabled. The MonIdle interrupt is enabled. - */ -#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) - -#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) -#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) -/*! EVENTTIMEOUTEN - Event time-out interrupt Enable. - * 0b0..Disabled. The Event time-out interrupt is disabled. - * 0b1..Enabled. The Event time-out interrupt is enabled. - */ -#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) - -#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) -#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) -/*! SCLTIMEOUTEN - SCL time-out interrupt Enable. - * 0b0..Disabled. The SCL time-out interrupt is disabled. - * 0b1..Enabled. The SCL time-out interrupt is enabled. - */ -#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear register. */ -/*! @{ */ - -#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) -#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) -/*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding - * bit in the INTENSET register if implemented. - */ -#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) - -#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) -#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) -/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear. - */ -#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) - -#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) -#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) -/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear. - */ -#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) - -#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) -#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) -/*! SLVPENDINGCLR - Slave Pending interrupt clear. - */ -#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) - -#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) -#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) -/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear. - */ -#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) - -#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) -#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) -/*! SLVDESELCLR - Slave Deselect interrupt clear. - */ -#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) - -#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) -#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) -/*! MONRDYCLR - Monitor data Ready interrupt clear. - */ -#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) - -#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) -#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) -/*! MONOVCLR - Monitor Overrun interrupt clear. - */ -#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) - -#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) -#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) -/*! MONIDLECLR - Monitor Idle interrupt clear. - */ -#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) - -#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) -#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) -/*! EVENTTIMEOUTCLR - Event time-out interrupt clear. - */ -#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) - -#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) -#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) -/*! SCLTIMEOUTCLR - SCL time-out interrupt clear. - */ -#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) -/*! @} */ - -/*! @name TIMEOUT - Time-out value register. */ -/*! @{ */ - -#define I2C_TIMEOUT_TOMIN_MASK (0xFU) -#define I2C_TIMEOUT_TOMIN_SHIFT (0U) -/*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum - * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. - */ -#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) - -#define I2C_TIMEOUT_TO_MASK (0xFFF0U) -#define I2C_TIMEOUT_TO_SHIFT (4U) -/*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C - * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, - * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A - * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after - * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the - * I2C function clock. - */ -#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) -/*! @} */ - -/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ -/*! @{ */ - -#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) -#define I2C_CLKDIV_DIVVAL_SHIFT (0U) -/*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that - * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = - * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is - * divided by 65,536 before use. - */ -#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ -/*! @{ */ - -#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) -#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) -/*! MSTPENDING - Master Pending. - */ -#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) - -#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) -#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) -/*! MSTARBLOSS - Master Arbitration Loss flag. - */ -#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) - -#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) -/*! MSTSTSTPERR - Master Start/Stop Error flag. - */ -#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) - -#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) -#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) -/*! SLVPENDING - Slave Pending. - */ -#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) - -#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) -#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) -/*! SLVNOTSTR - Slave Not Stretching status. - */ -#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) - -#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) -#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) -/*! SLVDESEL - Slave Deselected flag. - */ -#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) - -#define I2C_INTSTAT_MONRDY_MASK (0x10000U) -#define I2C_INTSTAT_MONRDY_SHIFT (16U) -/*! MONRDY - Monitor Ready. - */ -#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) - -#define I2C_INTSTAT_MONOV_MASK (0x20000U) -#define I2C_INTSTAT_MONOV_SHIFT (17U) -/*! MONOV - Monitor Overflow flag. - */ -#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) - -#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) -#define I2C_INTSTAT_MONIDLE_SHIFT (19U) -/*! MONIDLE - Monitor Idle flag. - */ -#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) - -#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) -/*! EVENTTIMEOUT - Event time-out Interrupt flag. - */ -#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) - -#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) -/*! SCLTIMEOUT - SCL time-out Interrupt flag. - */ -#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name MSTCTL - Master control register. */ -/*! @{ */ - -#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) -#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) -/*! MSTCONTINUE - Master Continue. This bit is write-only. - * 0b0..No effect. - * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing - * transmit data, reading received data, or any other housekeeping related to the next bus operation. - */ -#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) - -#define I2C_MSTCTL_MSTSTART_MASK (0x2U) -#define I2C_MSTCTL_MSTSTART_SHIFT (1U) -/*! MSTSTART - Master Start control. This bit is write-only. - * 0b0..No effect. - * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. - */ -#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) - -#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) -#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) -/*! MSTSTOP - Master Stop control. This bit is write-only. - * 0b0..No effect. - * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave - * if the master is receiving data from the slave (Master Receiver mode). - */ -#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) - -#define I2C_MSTCTL_MSTDMA_MASK (0x8U) -#define I2C_MSTCTL_MSTDMA_SHIFT (3U) -/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type - * operations such as Start, address, Stop, and address match must always be done with software, - * typically via an interrupt. Address acknowledgement must also be done by software except when - * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by - * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA - * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is - * read/write. - * 0b0..Disable. No DMA requests are generated for master operation. - * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating - * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. - */ -#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) -/*! @} */ - -/*! @name MSTTIME - Master timing configuration. */ -/*! @{ */ - -#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) -#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) -/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this - * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This - * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters - * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. - * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. - * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. - * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. - * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. - * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. - * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. - * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. - * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. - */ -#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) - -#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) -#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) -/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this - * master on SCL. Other masters in a multi-master system could shorten this time. This - * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters - * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. - * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. - * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . - * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. - * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. - * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. - * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. - * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. - * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. - */ -#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) -/*! @} */ - -/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ -/*! @{ */ - -#define I2C_MSTDAT_DATA_MASK (0xFFU) -#define I2C_MSTDAT_DATA_SHIFT (0U) -/*! DATA - Master function data register. Read: read the most recently received data for the Master - * function. Write: transmit data using the Master function. - */ -#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVCTL - Slave control register. */ -/*! @{ */ - -#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) -#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) -/*! SLVCONTINUE - Slave Continue. - * 0b0..No effect. - * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag - * in the STAT register. This must be done after writing transmit data, reading received data, or any other - * housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE - * should not be set unless SLVPENDING = 1. - */ -#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) - -#define I2C_SLVCTL_SLVNACK_MASK (0x2U) -#define I2C_SLVCTL_SLVNACK_SHIFT (1U) -/*! SLVNACK - Slave NACK. - * 0b0..No effect. - * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). - */ -#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) - -#define I2C_SLVCTL_SLVDMA_MASK (0x8U) -#define I2C_SLVCTL_SLVDMA_SHIFT (3U) -/*! SLVDMA - Slave DMA enable. - * 0b0..Disabled. No DMA requests are issued for Slave mode operation. - * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. - */ -#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) - -#define I2C_SLVCTL_AUTOACK_MASK (0x100U) -#define I2C_SLVCTL_AUTOACK_SHIFT (8U) -/*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches - * SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA - * to allow processing of the data without intervention. If this bit is clear and a header - * matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or - * interrupt. - * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching - * address is received. If AUTONACK = 1, received addresses are NACKed (ignored). - * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, - * allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does - * not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK - * is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. - */ -#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) - -#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) -#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) -/*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write - * request on the next header with an address matching SLVADR0. Since DMA needs to be configured to - * match the transfer direction, the direction needs to be specified. This bit allows a direction to - * be chosen for the next operation. - * 0b0..The expected next operation in Automatic Mode is an I2C write. - * 0b1..The expected next operation in Automatic Mode is an I2C read. - */ -#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) -/*! @} */ - -/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ -/*! @{ */ - -#define I2C_SLVDAT_DATA_MASK (0xFFU) -#define I2C_SLVDAT_DATA_SHIFT (0U) -/*! DATA - Slave function data register. Read: read the most recently received data for the Slave - * function. Write: transmit data using the Slave function. - */ -#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVADR - Slave address register. */ -/*! @{ */ - -#define I2C_SLVADR_SADISABLE_MASK (0x1U) -#define I2C_SLVADR_SADISABLE_SHIFT (0U) -/*! SADISABLE - Slave Address n Disable. - * 0b0..Enabled. Slave Address n is enabled. - * 0b1..Ignored Slave Address n is ignored. - */ -#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) - -#define I2C_SLVADR_SLVADR_MASK (0xFEU) -#define I2C_SLVADR_SLVADR_SHIFT (1U) -/*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. - */ -#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) - -#define I2C_SLVADR_AUTONACK_MASK (0x8000U) -#define I2C_SLVADR_AUTONACK_SHIFT (15U) -/*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows - * software to ignore I2C traffic while handling previous I2C data or other operations. - * 0b0..Normal operation, matching I2C addresses are not ignored. - * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches - * SLVADRn, and AUTOMATCHREAD matches the direction. - */ -#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) -/*! @} */ - -/* The count of I2C_SLVADR */ -#define I2C_SLVADR_COUNT (4U) - -/*! @name SLVQUAL0 - Slave Qualification for address 0. */ -/*! @{ */ - -#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) -#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) -/*! QUALMODE0 - Qualify mode for slave address 0. - * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. - * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. - */ -#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) - -#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) -#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) -/*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to - * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is - * set to 1 will cause an automatic match of the corresponding bit of the received address when it - * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for - * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 - * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). - */ -#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) -/*! @} */ - -/*! @name MONRXDAT - Monitor receiver data register. */ -/*! @{ */ - -#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) -#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) -/*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. - */ -#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) - -#define I2C_MONRXDAT_MONSTART_MASK (0x100U) -#define I2C_MONRXDAT_MONSTART_SHIFT (8U) -/*! MONSTART - Monitor Received Start. - * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. - * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. - */ -#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) - -#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) -#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) -/*! MONRESTART - Monitor Received Repeated Start. - * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. - * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. - */ -#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) - -#define I2C_MONRXDAT_MONNACK_MASK (0x400U) -#define I2C_MONRXDAT_MONNACK_SHIFT (10U) -/*! MONNACK - Monitor Received NACK. - * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. - * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. - */ -#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ - -#define I2C_ID_APERTURE_MASK (0xFFU) -#define I2C_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - */ -#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) - -#define I2C_ID_MINOR_REV_MASK (0xF00U) -#define I2C_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation. - */ -#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) - -#define I2C_ID_MAJOR_REV_MASK (0xF000U) -#define I2C_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation. - */ -#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) - -#define I2C_ID_ID_MASK (0xFFFF0000U) -#define I2C_ID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function. - */ -#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2C_Register_Masks */ - - -/* I2C - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral I2C0 base address */ - #define I2C0_BASE (0x50086000u) - /** Peripheral I2C0 base address */ - #define I2C0_BASE_NS (0x40086000u) - /** Peripheral I2C0 base pointer */ - #define I2C0 ((I2C_Type *)I2C0_BASE) - /** Peripheral I2C0 base pointer */ - #define I2C0_NS ((I2C_Type *)I2C0_BASE_NS) - /** Peripheral I2C1 base address */ - #define I2C1_BASE (0x50087000u) - /** Peripheral I2C1 base address */ - #define I2C1_BASE_NS (0x40087000u) - /** Peripheral I2C1 base pointer */ - #define I2C1 ((I2C_Type *)I2C1_BASE) - /** Peripheral I2C1 base pointer */ - #define I2C1_NS ((I2C_Type *)I2C1_BASE_NS) - /** Peripheral I2C2 base address */ - #define I2C2_BASE (0x50088000u) - /** Peripheral I2C2 base address */ - #define I2C2_BASE_NS (0x40088000u) - /** Peripheral I2C2 base pointer */ - #define I2C2 ((I2C_Type *)I2C2_BASE) - /** Peripheral I2C2 base pointer */ - #define I2C2_NS ((I2C_Type *)I2C2_BASE_NS) - /** Peripheral I2C3 base address */ - #define I2C3_BASE (0x50089000u) - /** Peripheral I2C3 base address */ - #define I2C3_BASE_NS (0x40089000u) - /** Peripheral I2C3 base pointer */ - #define I2C3 ((I2C_Type *)I2C3_BASE) - /** Peripheral I2C3 base pointer */ - #define I2C3_NS ((I2C_Type *)I2C3_BASE_NS) - /** Peripheral I2C4 base address */ - #define I2C4_BASE (0x5008A000u) - /** Peripheral I2C4 base address */ - #define I2C4_BASE_NS (0x4008A000u) - /** Peripheral I2C4 base pointer */ - #define I2C4 ((I2C_Type *)I2C4_BASE) - /** Peripheral I2C4 base pointer */ - #define I2C4_NS ((I2C_Type *)I2C4_BASE_NS) - /** Peripheral I2C5 base address */ - #define I2C5_BASE (0x50096000u) - /** Peripheral I2C5 base address */ - #define I2C5_BASE_NS (0x40096000u) - /** Peripheral I2C5 base pointer */ - #define I2C5 ((I2C_Type *)I2C5_BASE) - /** Peripheral I2C5 base pointer */ - #define I2C5_NS ((I2C_Type *)I2C5_BASE_NS) - /** Peripheral I2C6 base address */ - #define I2C6_BASE (0x50097000u) - /** Peripheral I2C6 base address */ - #define I2C6_BASE_NS (0x40097000u) - /** Peripheral I2C6 base pointer */ - #define I2C6 ((I2C_Type *)I2C6_BASE) - /** Peripheral I2C6 base pointer */ - #define I2C6_NS ((I2C_Type *)I2C6_BASE_NS) - /** Peripheral I2C7 base address */ - #define I2C7_BASE (0x50098000u) - /** Peripheral I2C7 base address */ - #define I2C7_BASE_NS (0x40098000u) - /** Peripheral I2C7 base pointer */ - #define I2C7 ((I2C_Type *)I2C7_BASE) - /** Peripheral I2C7 base pointer */ - #define I2C7_NS ((I2C_Type *)I2C7_BASE_NS) - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS_NS { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS_NS { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS } -#else - /** Peripheral I2C0 base address */ - #define I2C0_BASE (0x40086000u) - /** Peripheral I2C0 base pointer */ - #define I2C0 ((I2C_Type *)I2C0_BASE) - /** Peripheral I2C1 base address */ - #define I2C1_BASE (0x40087000u) - /** Peripheral I2C1 base pointer */ - #define I2C1 ((I2C_Type *)I2C1_BASE) - /** Peripheral I2C2 base address */ - #define I2C2_BASE (0x40088000u) - /** Peripheral I2C2 base pointer */ - #define I2C2 ((I2C_Type *)I2C2_BASE) - /** Peripheral I2C3 base address */ - #define I2C3_BASE (0x40089000u) - /** Peripheral I2C3 base pointer */ - #define I2C3 ((I2C_Type *)I2C3_BASE) - /** Peripheral I2C4 base address */ - #define I2C4_BASE (0x4008A000u) - /** Peripheral I2C4 base pointer */ - #define I2C4 ((I2C_Type *)I2C4_BASE) - /** Peripheral I2C5 base address */ - #define I2C5_BASE (0x40096000u) - /** Peripheral I2C5 base pointer */ - #define I2C5 ((I2C_Type *)I2C5_BASE) - /** Peripheral I2C6 base address */ - #define I2C6_BASE (0x40097000u) - /** Peripheral I2C6 base pointer */ - #define I2C6 ((I2C_Type *)I2C6_BASE) - /** Peripheral I2C7 base address */ - #define I2C7_BASE (0x40098000u) - /** Peripheral I2C7 base pointer */ - #define I2C7 ((I2C_Type *)I2C7_BASE) - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } -#endif -/** Interrupt vectors for the I2C peripheral type */ -#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2C_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2S Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer - * @{ - */ - -/** I2S - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[3072]; - __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ - __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ - __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ - uint8_t RESERVED_2[480]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ - uint8_t RESERVED_5[8]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ - uint8_t RESERVED_6[8]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ - __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ - uint8_t RESERVED_7[432]; - __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */ -} I2S_Type; - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ -/*! @{ */ - -#define I2S_CFG1_MAINENABLE_MASK (0x1U) -#define I2S_CFG1_MAINENABLE_SHIFT (0U) -/*! MAINENABLE - Main enable for I 2S function in this Flexcomm - * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags - * are reset. No other channel pairs can be enabled. - * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. - */ -#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) - -#define I2S_CFG1_DATAPAUSE_MASK (0x2U) -#define I2S_CFG1_DATAPAUSE_SHIFT (1U) -/*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer - * and the FIFO. This could be done in order to change streams, or while restarting after a data - * underflow or overflow. When paused, FIFO operations can be done without corrupting data that is - * in the process of being sent or received. Once a data pause has been requested, the interface - * may need to complete sending data that was in progress before interrupting the flow of data. - * Software must check that the pause is actually in effect before taking action. This is done by - * monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer - * will resume at the beginning of the next frame. - * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. - * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. - */ -#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) - -#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) -#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) -/*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field - * whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this - * Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs - * in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. - * 0b00..1 I2S channel pairs in this flexcomm - * 0b01..2 I2S channel pairs in this flexcomm - * 0b10..3 I2S channel pairs in this flexcomm - * 0b11..4 I2S channel pairs in this flexcomm - */ -#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) - -#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) -#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) -/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. - * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. - * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of - * SCK, when divided from the Flexcomm function clock. - * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. - * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. - */ -#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) - -#define I2S_CFG1_MODE_MASK (0xC0U) -#define I2S_CFG1_MODE_SHIFT (6U) -/*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all - * supported cases. See Formats and modes for examples. - * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece - * of left channel data occurring during the first phase, and one pieces of right channel data occurring - * during the second phase. In this mode, the data region begins one clock after the leading WS edge for the - * frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If - * FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. - * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0. - * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame. - * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame. - */ -#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) - -#define I2S_CFG1_RIGHTLOW_MASK (0x100U) -#define I2S_CFG1_RIGHTLOW_SHIFT (8U) -/*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left - * and right channel data as it is transferred to or from the FIFO. This bit is not used if the - * data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 - * of this register) = 1, the one channel to be used is the nominally the left channel. POSITION - * can still place that data in the frame where right channel data is normally located. if all - * enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. - * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO - * bits 31:16 are used for the right channel. - * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO - * bits 15:0 are used for the right channel. - */ -#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) - -#define I2S_CFG1_LEFTJUST_MASK (0x200U) -#define I2S_CFG1_LEFTJUST_SHIFT (9U) -/*! LEFTJUST - Left Justify data. - * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting - * from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data - * in the stream on the data bus. - * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting - * from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would - * correspond to left justified data in the stream on the data bus. - */ -#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) - -#define I2S_CFG1_ONECHANNEL_MASK (0x400U) -#define I2S_CFG1_ONECHANNEL_SHIFT (10U) -/*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit - * applies only to the first I2S channel pair. Other channel pairs may select this mode - * independently in their separate CFG1 registers. - * 0b0..I2S data for this channel pair is treated as left and right channels. - * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this - * pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a - * clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel - * of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side - * (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data - * for the single channel of data is placed at the clock defined by POSITION. - */ -#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) - -#define I2S_CFG1_SCK_POL_MASK (0x1000U) -#define I2S_CFG1_SCK_POL_SHIFT (12U) -/*! SCK_POL - SCK polarity. - * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). - * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges. - */ -#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) - -#define I2S_CFG1_WS_POL_MASK (0x2000U) -#define I2S_CFG1_WS_POL_SHIFT (13U) -/*! WS_POL - WS polarity. - * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S). - * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). - */ -#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) - -#define I2S_CFG1_DATALEN_MASK (0x1F0000U) -#define I2S_CFG1_DATALEN_SHIFT (16U) -/*! DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or - * received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received - * from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the - * I2S: Determines the size of data transfers between the FIFO and the I2S - * serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of - * right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse - * at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to - * 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = - * data is 32 bits in length - */ -#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) -/*! @} */ - -/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ -/*! @{ */ - -#define I2S_CFG2_FRAMELEN_MASK (0x1FFU) -#define I2S_CFG2_FRAMELEN_SHIFT (0U) -/*! FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the - * frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported - * 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is - * 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in - * mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger - * than DATALEN in order for the WS pulse to be generated correctly. - */ -#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) - -#define I2S_CFG2_POSITION_MASK (0x1FF0000U) -#define I2S_CFG2_POSITION_SHIFT (16U) -/*! POSITION - Data Position. Defines the location within the frame of the data for this channel - * pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION - * defines the location of data in both the left phase and right phase, starting one clock after - * the WS edge. In other modes, POSITION defines the location of data within the entire frame. - * ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The - * combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels - * do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit - * position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS - * phase. 0x002 = data begins at bit position 2 within the frame or WS phase. - */ -#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) -/*! @} */ - -/*! @name STAT - Status register for the primary channel pair. */ -/*! @{ */ - -#define I2S_STAT_BUSY_MASK (0x1U) -#define I2S_STAT_BUSY_SHIFT (0U) -/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. - * 0b0..The transmitter/receiver for channel pair is currently idle. - * 0b1..The transmitter/receiver for channel pair is currently processing data. - */ -#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) - -#define I2S_STAT_SLVFRMERR_MASK (0x2U) -#define I2S_STAT_SLVFRMERR_SHIFT (1U) -/*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as - * a slave. An error indicates that the incoming WS signal did not transition as expected due to - * a mismatch between FRAMELEN and the actual incoming I2S stream. - * 0b0..No error has been recorded. - * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. - */ -#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) - -#define I2S_STAT_LR_MASK (0x4U) -#define I2S_STAT_LR_SHIFT (2U) -/*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to - * be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data - * being processed for the currently busy channel pair. - * 0b0..Left channel. - * 0b1..Right channel. - */ -#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) - -#define I2S_STAT_DATAPAUSED_MASK (0x8U) -#define I2S_STAT_DATAPAUSED_SHIFT (3U) -/*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels - * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for - * an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. - * 0b1..A data pause has been requested and is now in force. - */ -#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) -/*! @} */ - -/*! @name DIV - Clock divider, used by all channel pairs. */ -/*! @{ */ - -#define I2S_DIV_DIV_MASK (0xFFFU) -#define I2S_DIV_DIV_SHIFT (0U) -/*! DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The - * Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. - * 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is - * divided by 4,096. - */ -#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ - -#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) -#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) - -#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) -#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) - -#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) -#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) -/*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX - * FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is - * cleared, new data is provided, and the I2S is un-paused. - * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 - * bits or less, or when MONO = 1 for this channel pair. - * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. - */ -#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) - -#define I2S_FIFOCFG_PACK48_MASK (0x8U) -#define I2S_FIFOCFG_PACK48_SHIFT (3U) -/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. - * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values. - * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. - */ -#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) - -#define I2S_FIFOCFG_SIZE_MASK (0x30U) -#define I2S_FIFOCFG_SIZE_SHIFT (4U) -/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 - * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - */ -#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) - -#define I2S_FIFOCFG_DMATX_MASK (0x1000U) -#define I2S_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) - -#define I2S_FIFOCFG_DMARX_MASK (0x2000U) -#define I2S_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) - -#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) -#define I2S_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in - * FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) - -#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) -#define I2S_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in - * FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) - -#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) -/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - */ -#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) - -#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) -/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - */ -#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ - -#define I2S_FIFOSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow - * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is - * needed. Cleared by writing a 1 to this bit. - */ -#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) - -#define I2S_FIFOSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA - * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - */ -#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) - -#define I2S_FIFOSTAT_PERINT_MASK (0x8U) -#define I2S_FIFOSTAT_PERINT_SHIFT (3U) -/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted - * an interrupt. The details can be found by reading the peripheral's STAT register. - */ -#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) - -#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) -/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - */ -#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) - -#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) -/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be - * written. When 0, the transmit FIFO is full and another write would cause it to overflow. - */ -#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) - -#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - */ -#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) - -#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) -#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) -/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to - * prevent the peripheral from causing an overflow. - */ -#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) - -#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY - * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at - * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be - * 0. - */ -#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) - -#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and - * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the - * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be - * 1. - */ -#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ - -#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) - -#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) - -#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) -#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled - * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to - * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO - * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX - * FIFO level decreases to 15 entries (is no longer full). - */ -#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) - -#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data - * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level - * can wake up the device just enough to perform DMA, then return to the reduced power mode. See - * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no - * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX - * FIFO has received 16 entries (has become full). - */ -#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ - -#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) -#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) - -#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) -#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) - -#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases - * to the level specified by TXLVL in the FIFOTRIG register. - */ -#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) - -#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level - * increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ - -#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) -#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) -/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) - -#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) -#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) -/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) - -#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) -/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) - -#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) -/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ - -#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. - */ -#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) - -#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. - */ -#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) - -#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO level interrupt. - */ -#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) - -#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO level interrupt. - */ -#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) - -#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) -#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) -/*! PERINT - Peripheral interrupt. - */ -#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ - -#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFOWR_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details. - */ -#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ - -#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) -#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. - */ -#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ - -#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORD_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. The number of bits used depends on configuration details. - */ -#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ - -#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48H_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. - */ -#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ - -#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. - */ -#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ - -#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. - */ -#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) -/*! @} */ - -/*! @name FIFOSIZE - FIFO size register */ -/*! @{ */ - -#define I2S_FIFOSIZE_FIFOSIZE_MASK (0x1FU) -#define I2S_FIFOSIZE_FIFOSIZE_SHIFT (0U) -/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - */ -#define I2S_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSIZE_FIFOSIZE_SHIFT)) & I2S_FIFOSIZE_FIFOSIZE_MASK) -/*! @} */ - -/*! @name ID - I2S Module identification */ -/*! @{ */ - -#define I2S_ID_APERTURE_MASK (0xFFU) -#define I2S_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - */ -#define I2S_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_APERTURE_SHIFT)) & I2S_ID_APERTURE_MASK) - -#define I2S_ID_MINOR_REV_MASK (0xF00U) -#define I2S_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation, starting at 0. - */ -#define I2S_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK) - -#define I2S_ID_MAJOR_REV_MASK (0xF000U) -#define I2S_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation, starting at 0. - */ -#define I2S_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK) - -#define I2S_ID_ID_MASK (0xFFFF0000U) -#define I2S_ID_ID_SHIFT (16U) -/*! ID - Unique module identifier for this IP block. - */ -#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2S_Register_Masks */ - - -/* I2S - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral I2S0 base address */ - #define I2S0_BASE (0x50086000u) - /** Peripheral I2S0 base address */ - #define I2S0_BASE_NS (0x40086000u) - /** Peripheral I2S0 base pointer */ - #define I2S0 ((I2S_Type *)I2S0_BASE) - /** Peripheral I2S0 base pointer */ - #define I2S0_NS ((I2S_Type *)I2S0_BASE_NS) - /** Peripheral I2S1 base address */ - #define I2S1_BASE (0x50087000u) - /** Peripheral I2S1 base address */ - #define I2S1_BASE_NS (0x40087000u) - /** Peripheral I2S1 base pointer */ - #define I2S1 ((I2S_Type *)I2S1_BASE) - /** Peripheral I2S1 base pointer */ - #define I2S1_NS ((I2S_Type *)I2S1_BASE_NS) - /** Peripheral I2S2 base address */ - #define I2S2_BASE (0x50088000u) - /** Peripheral I2S2 base address */ - #define I2S2_BASE_NS (0x40088000u) - /** Peripheral I2S2 base pointer */ - #define I2S2 ((I2S_Type *)I2S2_BASE) - /** Peripheral I2S2 base pointer */ - #define I2S2_NS ((I2S_Type *)I2S2_BASE_NS) - /** Peripheral I2S3 base address */ - #define I2S3_BASE (0x50089000u) - /** Peripheral I2S3 base address */ - #define I2S3_BASE_NS (0x40089000u) - /** Peripheral I2S3 base pointer */ - #define I2S3 ((I2S_Type *)I2S3_BASE) - /** Peripheral I2S3 base pointer */ - #define I2S3_NS ((I2S_Type *)I2S3_BASE_NS) - /** Peripheral I2S4 base address */ - #define I2S4_BASE (0x5008A000u) - /** Peripheral I2S4 base address */ - #define I2S4_BASE_NS (0x4008A000u) - /** Peripheral I2S4 base pointer */ - #define I2S4 ((I2S_Type *)I2S4_BASE) - /** Peripheral I2S4 base pointer */ - #define I2S4_NS ((I2S_Type *)I2S4_BASE_NS) - /** Peripheral I2S5 base address */ - #define I2S5_BASE (0x50096000u) - /** Peripheral I2S5 base address */ - #define I2S5_BASE_NS (0x40096000u) - /** Peripheral I2S5 base pointer */ - #define I2S5 ((I2S_Type *)I2S5_BASE) - /** Peripheral I2S5 base pointer */ - #define I2S5_NS ((I2S_Type *)I2S5_BASE_NS) - /** Peripheral I2S6 base address */ - #define I2S6_BASE (0x50097000u) - /** Peripheral I2S6 base address */ - #define I2S6_BASE_NS (0x40097000u) - /** Peripheral I2S6 base pointer */ - #define I2S6 ((I2S_Type *)I2S6_BASE) - /** Peripheral I2S6 base pointer */ - #define I2S6_NS ((I2S_Type *)I2S6_BASE_NS) - /** Peripheral I2S7 base address */ - #define I2S7_BASE (0x50098000u) - /** Peripheral I2S7 base address */ - #define I2S7_BASE_NS (0x40098000u) - /** Peripheral I2S7 base pointer */ - #define I2S7 ((I2S_Type *)I2S7_BASE) - /** Peripheral I2S7 base pointer */ - #define I2S7_NS ((I2S_Type *)I2S7_BASE_NS) - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS_NS { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS_NS { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS } -#else - /** Peripheral I2S0 base address */ - #define I2S0_BASE (0x40086000u) - /** Peripheral I2S0 base pointer */ - #define I2S0 ((I2S_Type *)I2S0_BASE) - /** Peripheral I2S1 base address */ - #define I2S1_BASE (0x40087000u) - /** Peripheral I2S1 base pointer */ - #define I2S1 ((I2S_Type *)I2S1_BASE) - /** Peripheral I2S2 base address */ - #define I2S2_BASE (0x40088000u) - /** Peripheral I2S2 base pointer */ - #define I2S2 ((I2S_Type *)I2S2_BASE) - /** Peripheral I2S3 base address */ - #define I2S3_BASE (0x40089000u) - /** Peripheral I2S3 base pointer */ - #define I2S3 ((I2S_Type *)I2S3_BASE) - /** Peripheral I2S4 base address */ - #define I2S4_BASE (0x4008A000u) - /** Peripheral I2S4 base pointer */ - #define I2S4 ((I2S_Type *)I2S4_BASE) - /** Peripheral I2S5 base address */ - #define I2S5_BASE (0x40096000u) - /** Peripheral I2S5 base pointer */ - #define I2S5 ((I2S_Type *)I2S5_BASE) - /** Peripheral I2S6 base address */ - #define I2S6_BASE (0x40097000u) - /** Peripheral I2S6 base pointer */ - #define I2S6 ((I2S_Type *)I2S6_BASE) - /** Peripheral I2S7 base address */ - #define I2S7_BASE (0x40098000u) - /** Peripheral I2S7 base pointer */ - #define I2S7 ((I2S_Type *)I2S7_BASE) - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } -#endif -/** Interrupt vectors for the I2S peripheral type */ -#define I2S_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2S_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer - * @{ - */ - -/** INPUTMUX - Register Layout Typedef */ -typedef struct { - __IO uint32_t SCT0_INMUX[7]; /**< Input mux register for SCT0 input, array offset: 0x0, array step: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t TIMER0CAPTSEL[4]; /**< Capture select registers for TIMER0 inputs, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[16]; - __IO uint32_t TIMER1CAPTSEL[4]; /**< Capture select registers for TIMER1 inputs, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_2[16]; - __IO uint32_t TIMER2CAPTSEL[4]; /**< Capture select registers for TIMER2 inputs, array offset: 0x60, array step: 0x4 */ - uint8_t RESERVED_3[80]; - __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ - __IO uint32_t DMA0_ITRIG_INMUX[23]; /**< Trigger select register for DMA0 channel, array offset: 0xE0, array step: 0x4 */ - uint8_t RESERVED_4[36]; - __IO uint32_t DMA0_OTRIG_INMUX[4]; /**< DMA0 output trigger selection to become DMA0 trigger, array offset: 0x160, array step: 0x4 */ - uint8_t RESERVED_5[16]; - __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ - __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ - uint8_t RESERVED_6[24]; - __IO uint32_t TIMER3CAPTSEL[4]; /**< Capture select registers for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */ - uint8_t RESERVED_7[16]; - __IO uint32_t TIMER4CAPTSEL[4]; /**< Capture select registers for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */ - uint8_t RESERVED_8[16]; - __IO uint32_t PINTSECSEL[2]; /**< Pin interrupt secure select register, array offset: 0x1E0, array step: 0x4 */ - uint8_t RESERVED_9[24]; - __IO uint32_t DMA1_ITRIG_INMUX[10]; /**< Trigger select register for DMA1 channel, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_10[24]; - __IO uint32_t DMA1_OTRIG_INMUX[4]; /**< DMA1 output trigger selection to become DMA1 trigger, array offset: 0x240, array step: 0x4 */ - uint8_t RESERVED_11[1264]; - __IO uint32_t DMA0_REQ_ENA; /**< Enable DMA0 requests, offset: 0x740 */ - uint8_t RESERVED_12[4]; - __O uint32_t DMA0_REQ_ENA_SET; /**< Set one or several bits in DMA0_REQ_ENA register, offset: 0x748 */ - uint8_t RESERVED_13[4]; - __O uint32_t DMA0_REQ_ENA_CLR; /**< Clear one or several bits in DMA0_REQ_ENA register, offset: 0x750 */ - uint8_t RESERVED_14[12]; - __IO uint32_t DMA1_REQ_ENA; /**< Enable DMA1 requests, offset: 0x760 */ - uint8_t RESERVED_15[4]; - __O uint32_t DMA1_REQ_ENA_SET; /**< Set one or several bits in DMA1_REQ_ENA register, offset: 0x768 */ - uint8_t RESERVED_16[4]; - __O uint32_t DMA1_REQ_ENA_CLR; /**< Clear one or several bits in DMA1_REQ_ENA register, offset: 0x770 */ - uint8_t RESERVED_17[12]; - __IO uint32_t DMA0_ITRIG_ENA; /**< Enable DMA0 triggers, offset: 0x780 */ - uint8_t RESERVED_18[4]; - __O uint32_t DMA0_ITRIG_ENA_SET; /**< Set one or several bits in DMA0_ITRIG_ENA register, offset: 0x788 */ - uint8_t RESERVED_19[4]; - __O uint32_t DMA0_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA0_ITRIG_ENA register, offset: 0x790 */ - uint8_t RESERVED_20[12]; - __IO uint32_t DMA1_ITRIG_ENA; /**< Enable DMA1 triggers, offset: 0x7A0 */ - uint8_t RESERVED_21[4]; - __O uint32_t DMA1_ITRIG_ENA_SET; /**< Set one or several bits in DMA1_ITRIG_ENA register, offset: 0x7A8 */ - uint8_t RESERVED_22[4]; - __O uint32_t DMA1_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA1_ITRIG_ENA register, offset: 0x7B0 */ -} INPUTMUX_Type; - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks - * @{ - */ - -/*! @name SCT0_INMUX - Input mux register for SCT0 input */ -/*! @{ */ - -#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU) -#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) -/*! INP_N - Input number to SCT0 inputs 0 to 6.. - * 0b00000..SCT_GPI0 function selected from IOCON register - * 0b00001..SCT_GPI1 function selected from IOCON register - * 0b00010..SCT_GPI2 function selected from IOCON register - * 0b00011..SCT_GPI3 function selected from IOCON register - * 0b00100..SCT_GPI4 function selected from IOCON register - * 0b00101..SCT_GPI5 function selected from IOCON register - * 0b00110..SCT_GPI6 function selected from IOCON register - * 0b00111..SCT_GPI7 function selected from IOCON register - * 0b01000..T0_OUT0 ctimer 0 match[0] output - * 0b01001..T1_OUT0 ctimer 1 match[0] output - * 0b01010..T2_OUT0 ctimer 2 match[0] output - * 0b01011..T3_OUT0 ctimer 3 match[0] output - * 0b01100..T4_OUT0 ctimer 4 match[0] output - * 0b01101..ADC_IRQ interrupt request from ADC - * 0b01110..GPIOINT_BMATCH - * 0b01111..USB0_FRAME_TOGGLE - * 0b10000..USB1_FRAME_TOGGLE - * 0b10001..COMP_OUTPUT output from analog comparator - * 0b10010..I2S_SHARED_SCK[0] output from I2S pin sharing - * 0b10011..I2S_SHARED_SCK[1] output from I2S pin sharing - * 0b10100..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b10101..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b10110..ARM_TXEV interrupt event from cpu0 or cpu1 - * 0b10111..DEBUG_HALTED from cpu0 or cpu1 - * 0b11000-0b11111..None - */ -#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK) -/*! @} */ - -/* The count of INPUTMUX_SCT0_INMUX */ -#define INPUTMUX_SCT0_INMUX_COUNT (7U) - -/*! @name TIMER0CAPTSEL - Capture select registers for TIMER0 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..None - * 0b10010..None - * 0b10011..None - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER0CAPTSEL */ -#define INPUTMUX_TIMER0CAPTSEL_COUNT (4U) - -/*! @name TIMER1CAPTSEL - Capture select registers for TIMER1 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..None - * 0b10010..None - * 0b10011..None - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER1CAPTSEL */ -#define INPUTMUX_TIMER1CAPTSEL_COUNT (4U) - -/*! @name TIMER2CAPTSEL - Capture select registers for TIMER2 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..None - * 0b10010..None - * 0b10011..None - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER2CAPTSEL */ -#define INPUTMUX_TIMER2CAPTSEL_COUNT (4U) - -/*! @name PINTSEL - Pin interrupt select register */ -/*! @{ */ - -#define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU) -#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) -/*! INTPIN - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = - * (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. - */ -#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PINTSEL */ -#define INPUTMUX_PINTSEL_COUNT (8U) - -/*! @name DMA0_ITRIG_INMUX - Trigger select register for DMA0 channel */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U) -/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22). - * 0b00000..Pin interrupt 0 - * 0b00001..Pin interrupt 1 - * 0b00010..Pin interrupt 2 - * 0b00011..Pin interrupt 3 - * 0b00100..Timer CTIMER0 Match 0 - * 0b00101..Timer CTIMER0 Match 1 - * 0b00110..Timer CTIMER1 Match 0 - * 0b00111..Timer CTIMER1 Match 1 - * 0b01000..Timer CTIMER2 Match 0 - * 0b01001..Timer CTIMER2 Match 1 - * 0b01010..Timer CTIMER3 Match 0 - * 0b01011..Timer CTIMER3 Match 1 - * 0b01100..Timer CTIMER4 Match 0 - * 0b01101..Timer CTIMER4 Match 1 - * 0b01110..COMP_OUTPUT - * 0b01111..DMA0 output trigger mux 0 - * 0b10000..DMA0 output trigger mux 1 - * 0b10001..DMA0 output trigger mux 1 - * 0b10010..DMA0 output trigger mux 3 - * 0b10011..SCT0 DMA request 0 - * 0b10100..SCT0 DMA request 1 - * 0b10101..HASH DMA RX trigger - * 0b10110-0b11111..None - */ -#define INPUTMUX_DMA0_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA0_ITRIG_INMUX */ -#define INPUTMUX_DMA0_ITRIG_INMUX_COUNT (23U) - -/*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection to become DMA0 trigger */ -/*! @{ */ - -#define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U) -/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22). - */ -#define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA0_OTRIG_INMUX */ -#define INPUTMUX_DMA0_OTRIG_INMUX_COUNT (4U) - -/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ -/*! @{ */ - -#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) -/*! CLKIN - Clock source number (decimal value) for frequency measure function reference clock: - * 0b00000..External main crystal oscilator (Clock_in). - * 0b00001..FRO 12MHz clock. - * 0b00010..FRO 96MHz clock. - * 0b00011..Watchdog oscillator / FRO1MHz clock. - * 0b00100..32 kHz oscillator (32k_clk) clock. - * 0b00101..main clock (main_clock). - * 0b00110..FREQME_GPIO_CLK_A. - * 0b00111..FREQME_GPIO_CLK_B. - */ -#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) -/*! @} */ - -/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ -/*! @{ */ - -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) -/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: - * 0b00000..External main crystal oscilator (Clock_in). - * 0b00001..FRO 12MHz clock. - * 0b00010..FRO 96MHz clock. - * 0b00011..Watchdog oscillator / FRO1MHz clock. - * 0b00100..32 kHz oscillator (32k_clk) clock. - * 0b00101..main clock (main_clock). - * 0b00110..FREQME_GPIO_CLK_A. - * 0b00111..FREQME_GPIO_CLK_B. - */ -#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) -/*! @} */ - -/*! @name TIMER3CAPTSEL - Capture select registers for TIMER3 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER3CAPTSEL */ -#define INPUTMUX_TIMER3CAPTSEL_COUNT (4U) - -/*! @name TIMER4CAPTSEL - Capture select registers for TIMER4 inputs */ -/*! @{ */ - -#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER4CAPTSEL */ -#define INPUTMUX_TIMER4CAPTSEL_COUNT (4U) - -/*! @name PINTSECSEL - Pin interrupt secure select register */ -/*! @{ */ - -#define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU) -#define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U) -/*! INTPIN - Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: - * INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31. - */ -#define INPUTMUX_PINTSECSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PINTSECSEL */ -#define INPUTMUX_PINTSECSEL_COUNT (2U) - -/*! @name DMA1_ITRIG_INMUX - Trigger select register for DMA1 channel */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0xFU) -#define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U) -/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9). - * 0b0000..Pin interrupt 0 - * 0b0001..Pin interrupt 1 - * 0b0010..Pin interrupt 2 - * 0b0011..Pin interrupt 3 - * 0b0100..Timer CTIMER0 Match 0 - * 0b0101..Timer CTIMER0 Match 1 - * 0b0110..Timer CTIMER2 Match 0 - * 0b0111..Timer CTIMER4 Match 0 - * 0b1000..DMA1 output trigger mux 0 - * 0b1001..DMA1 output trigger mux 1 - * 0b1010..DMA1 output trigger mux 2 - * 0b1011..DMA1 output trigger mux 3 - * 0b1100..SCT0 DMA request 0 - * 0b1101..SCT0 DMA request 1 - * 0b1110..HASH DMA RX trigger - * 0b1111..None - */ -#define INPUTMUX_DMA1_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA1_ITRIG_INMUX */ -#define INPUTMUX_DMA1_ITRIG_INMUX_COUNT (10U) - -/*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection to become DMA1 trigger */ -/*! @{ */ - -#define INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK (0xFU) -#define INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT (0U) -/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9). - */ -#define INPUTMUX_DMA1_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA1_OTRIG_INMUX */ -#define INPUTMUX_DMA1_OTRIG_INMUX_COUNT (4U) - -/*! @name DMA0_REQ_ENA - Enable DMA0 requests */ -/*! @{ */ - -#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK (0x7FFFFFU) -#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT (0U) -/*! REQ_ENA - Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK) -/*! @} */ - -/*! @name DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK (0x7FFFFFU) -#define INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT (0U) -/*! SET - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register - */ -#define INPUTMUX_DMA0_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK (0x7FFFFFU) -#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT (0U) -/*! CLR - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register - */ -#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK) -/*! @} */ - -/*! @name DMA1_REQ_ENA - Enable DMA1 requests */ -/*! @{ */ - -#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK (0x3FFU) -#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT (0U) -/*! REQ_ENA - Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - */ -#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK) -/*! @} */ - -/*! @name DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK (0x3FFU) -#define INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT (0U) -/*! SET - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register - */ -#define INPUTMUX_DMA1_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK (0x3FFU) -#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT (0U) -/*! CLR - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register - */ -#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_ENA - Enable DMA0 triggers */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK (0x3FFFFFU) -#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) -/*! ITRIG_ENA - Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK (0x3FFFFFU) -#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT (0U) -/*! SET - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no - * change in DMA0_ITRIG_ENA register - */ -#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK (0x3FFFFFU) -#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT (0U) -/*! CLR - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no - * change in DMA0_ITRIG_ENA register - */ -#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK) -/*! @} */ - -/*! @name DMA1_ITRIG_ENA - Enable DMA1 triggers */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK (0x7FFFU) -#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) -/*! ITRIG_ENA - Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - */ -#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK) -/*! @} */ - -/*! @name DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK (0x7FFFU) -#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT (0U) -/*! SET - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no - * change in DMA1_ITRIG_ENA register - */ -#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register */ -/*! @{ */ - -#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK (0x7FFFU) -#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT (0U) -/*! CLR - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no - * change in DMA1_ITRIG_ENA register - */ -#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group INPUTMUX_Register_Masks */ - - -/* INPUTMUX - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE (0x50006000u) - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE_NS (0x40006000u) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS) - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS { INPUTMUX } - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX_BASE_NS } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS_NS { INPUTMUX_NS } -#else - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE (0x40006000u) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS { INPUTMUX } -#endif - -/*! - * @} - */ /* end of group INPUTMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- IOCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer - * @{ - */ - -/** IOCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ -} IOCON_Type; - -/* ---------------------------------------------------------------------------- - -- IOCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Register_Masks IOCON Register Masks - * @{ - */ - -/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ -/*! @{ */ - -#define IOCON_PIO_FUNC_MASK (0xFU) -#define IOCON_PIO_FUNC_SHIFT (0U) -/*! FUNC - Selects pin function. - * 0b0000..Alternative connection 0. - * 0b0001..Alternative connection 1. - * 0b0010..Alternative connection 2. - * 0b0011..Alternative connection 3. - * 0b0100..Alternative connection 4. - * 0b0101..Alternative connection 5. - * 0b0110..Alternative connection 6. - * 0b0111..Alternative connection 7. - */ -#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) - -#define IOCON_PIO_MODE_MASK (0x30U) -#define IOCON_PIO_MODE_SHIFT (4U) -/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) - -#define IOCON_PIO_SLEW_MASK (0x40U) -#define IOCON_PIO_SLEW_SHIFT (6U) -/*! SLEW - Driver slew rate. - * 0b0..Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - * 0b1..Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - */ -#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) - -#define IOCON_PIO_INVERT_MASK (0x80U) -#define IOCON_PIO_INVERT_SHIFT (7U) -/*! INVERT - Input polarity. - * 0b0..Disabled. Input function is not inverted. - * 0b1..Enabled. Input is function inverted. - */ -#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) - -#define IOCON_PIO_DIGIMODE_MASK (0x100U) -#define IOCON_PIO_DIGIMODE_SHIFT (8U) -/*! DIGIMODE - Select Digital mode. - * 0b0..Disable digital mode. Digital input set to 0. - * 0b1..Enable Digital mode. Digital input is enabled. - */ -#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) - -#define IOCON_PIO_OD_MASK (0x200U) -#define IOCON_PIO_OD_SHIFT (9U) -/*! OD - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). - * 0b0..Normal. Normal push-pull output - * 0b1..Open-drain. Simulated open-drain output (high drive disabled). - */ -#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) - -#define IOCON_PIO_ASW_MASK (0x400U) -#define IOCON_PIO_ASW_SHIFT (10U) -/*! ASW - Analog switch input control. - * 0b0..For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed - * (enabled). For the other pins, analog switch is open (disabled). - * 0b1..For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - */ -#define IOCON_PIO_ASW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW_SHIFT)) & IOCON_PIO_ASW_MASK) - -#define IOCON_PIO_SSEL_MASK (0x800U) -#define IOCON_PIO_SSEL_SHIFT (11U) -/*! SSEL - Supply Selection bit. - * 0b0..3V3 Signaling in I2C Mode. - * 0b1..1V8 Signaling in I2C Mode. - */ -#define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK) - -#define IOCON_PIO_FILTEROFF_MASK (0x1000U) -#define IOCON_PIO_FILTEROFF_SHIFT (12U) -/*! FILTEROFF - Controls input glitch filter. - * 0b0..Filter enabled. - * 0b1..Filter disabled. - */ -#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) - -#define IOCON_PIO_ECS_MASK (0x2000U) -#define IOCON_PIO_ECS_SHIFT (13U) -/*! ECS - Pull-up current source enable in I2C mode. - * 0b1..Enabled. Pull resistor is conencted. - * 0b0..Disabled. IO is in open drain cell. - */ -#define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK) - -#define IOCON_PIO_EGP_MASK (0x4000U) -#define IOCON_PIO_EGP_SHIFT (14U) -/*! EGP - Switch between GPIO mode and I2C mode. - * 0b0..I2C mode. - * 0b1..GPIO mode. - */ -#define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK) - -#define IOCON_PIO_I2CFILTER_MASK (0x8000U) -#define IOCON_PIO_I2CFILTER_SHIFT (15U) -/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. - * 0b0..I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. - * 0b1..I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. - */ -#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) -/*! @} */ - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT (2U) - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT2 (32U) - - -/*! - * @} - */ /* end of group IOCON_Register_Masks */ - - -/* IOCON - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral IOCON base address */ - #define IOCON_BASE (0x50001000u) - /** Peripheral IOCON base address */ - #define IOCON_BASE_NS (0x40001000u) - /** Peripheral IOCON base pointer */ - #define IOCON ((IOCON_Type *)IOCON_BASE) - /** Peripheral IOCON base pointer */ - #define IOCON_NS ((IOCON_Type *)IOCON_BASE_NS) - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS { IOCON_BASE } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS { IOCON } - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS_NS { IOCON_BASE_NS } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS_NS { IOCON_NS } -#else - /** Peripheral IOCON base address */ - #define IOCON_BASE (0x40001000u) - /** Peripheral IOCON base pointer */ - #define IOCON ((IOCON_Type *)IOCON_BASE) - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS { IOCON_BASE } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS { IOCON } -#endif - -/*! - * @} - */ /* end of group IOCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MAILBOX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer - * @{ - */ - -/** MAILBOX - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x10 */ - __IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */ - __O uint32_t IRQSET; /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */ - __O uint32_t IRQCLR; /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } MBOXIRQ[2]; - uint8_t RESERVED_0[216]; - __IO uint32_t MUTEX; /**< Mutual exclusion register[1], offset: 0xF8 */ -} MAILBOX_Type; - -/* ---------------------------------------------------------------------------- - -- MAILBOX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks - * @{ - */ - -/*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */ -/*! @{ */ - -#define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) -#define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U) -/*! INTREQ - If any bit is set, an interrupt request is sent to the Cortex-M0+ interrupt controller. - */ -#define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK) -/*! @} */ - -/* The count of MAILBOX_MBOXIRQ_IRQ */ -#define MAILBOX_MBOXIRQ_IRQ_COUNT (2U) - -/*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */ -/*! @{ */ - -#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) -#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U) -/*! INTREQSET - Writing 1 sets the corresponding bit in the IRQ0 register. - */ -#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK) -/*! @} */ - -/* The count of MAILBOX_MBOXIRQ_IRQSET */ -#define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U) - -/*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */ -/*! @{ */ - -#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) -#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U) -/*! INTREQCLR - Writing 1 clears the corresponding bit in the IRQ0 register. - */ -#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK) -/*! @} */ - -/* The count of MAILBOX_MBOXIRQ_IRQCLR */ -#define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U) - -/*! @name MUTEX - Mutual exclusion register[1] */ -/*! @{ */ - -#define MAILBOX_MUTEX_EX_MASK (0x1U) -#define MAILBOX_MUTEX_EX_SHIFT (0U) -/*! EX - Cleared when read, set when written. See usage description above. - */ -#define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MAILBOX_Register_Masks */ - - -/* MAILBOX - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral MAILBOX base address */ - #define MAILBOX_BASE (0x5008B000u) - /** Peripheral MAILBOX base address */ - #define MAILBOX_BASE_NS (0x4008B000u) - /** Peripheral MAILBOX base pointer */ - #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) - /** Peripheral MAILBOX base pointer */ - #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) - /** Array initializer of MAILBOX peripheral base addresses */ - #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } - /** Array initializer of MAILBOX peripheral base pointers */ - #define MAILBOX_BASE_PTRS { MAILBOX } - /** Array initializer of MAILBOX peripheral base addresses */ - #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } - /** Array initializer of MAILBOX peripheral base pointers */ - #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } -#else - /** Peripheral MAILBOX base address */ - #define MAILBOX_BASE (0x4008B000u) - /** Peripheral MAILBOX base pointer */ - #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) - /** Array initializer of MAILBOX peripheral base addresses */ - #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } - /** Array initializer of MAILBOX peripheral base pointers */ - #define MAILBOX_BASE_PTRS { MAILBOX } -#endif -/** Interrupt vectors for the MAILBOX peripheral type */ -#define MAILBOX_IRQS { MAILBOX_IRQn } - -/*! - * @} - */ /* end of group MAILBOX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MRT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer - * @{ - */ - -/** MRT - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x10 */ - __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ - __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ - __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ - __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ - } CHANNEL[4]; - uint8_t RESERVED_0[176]; - __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ - __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ - __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ -} MRT_Type; - -/* ---------------------------------------------------------------------------- - -- MRT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Register_Masks MRT Register Masks - * @{ - */ - -/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ -/*! @{ */ - -#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) -/*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT - * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to - * this bit field starts the timer immediately. If the timer is running, writing a zero to this - * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer - * stops at the end of the time interval. - */ -#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) - -#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) -#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) -/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. - * This bit is write-only. Reading this bit always returns 0. - * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the - * time interval if the repeat mode is selected. - * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. - */ -#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_INTVAL */ -#define MRT_CHANNEL_INTVAL_COUNT (4U) - -/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ -/*! @{ */ - -#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) -/*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn - * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval - * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn - * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields - * returns -1 (0x00FF FFFF). - */ -#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_TIMER */ -#define MRT_CHANNEL_TIMER_COUNT (4U) - -/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ -/*! @{ */ - -#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) -#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) -/*! INTEN - Enable the TIMERn interrupt. - * 0b0..Disabled. TIMERn interrupt is disabled. - * 0b1..Enabled. TIMERn interrupt is enabled. - */ -#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) - -#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) -#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) -/*! MODE - Selects timer mode. - * 0b00..Repeat interrupt mode. - * 0b01..One-shot interrupt mode. - * 0b10..One-shot stall mode. - * 0b11..Reserved. - */ -#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_CTRL */ -#define MRT_CHANNEL_CTRL_COUNT (4U) - -/*! @name CHANNEL_STAT - MRT Status register. */ -/*! @{ */ - -#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) -#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) -/*! INTFLAG - Monitors the interrupt flag. - * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. - * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If - * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt - * are raised. Writing a 1 to this bit clears the interrupt request. - */ -#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) - -#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) -#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) -/*! RUN - Indicates the state of TIMERn. This bit is read-only. - * 0b0..Idle state. TIMERn is stopped. - * 0b1..Running. TIMERn is running. - */ -#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) - -#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) -#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) -/*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG - * register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating - * modes. - * 0b0..This channel is not in use. - * 0b1..This channel is in use. - */ -#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_STAT */ -#define MRT_CHANNEL_STAT_COUNT (4U) - -/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ -/*! @{ */ - -#define MRT_MODCFG_NOC_MASK (0xFU) -#define MRT_MODCFG_NOC_SHIFT (0U) -/*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.) - */ -#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) - -#define MRT_MODCFG_NOB_MASK (0x1F0U) -#define MRT_MODCFG_NOB_SHIFT (4U) -/*! NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.) - */ -#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) - -#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) -#define MRT_MODCFG_MULTITASK_SHIFT (31U) -/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. - * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. - * 0b1..Multi-task mode. - */ -#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) -/*! @} */ - -/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ -/*! @{ */ - -#define MRT_IDLE_CH_CHAN_MASK (0xF0U) -#define MRT_IDLE_CH_CHAN_SHIFT (4U) -/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is - * positioned such that it can be used as an offset from the MRT base address in order to access - * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See - * text above for more details. - */ -#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) -/*! @} */ - -/*! @name IRQ_FLAG - Global interrupt flag register */ -/*! @{ */ - -#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) -#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) -/*! GFLAG0 - Monitors the interrupt flag of TIMER0. - * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. - * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If - * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global - * interrupt are raised. Writing a 1 to this bit clears the interrupt request. - */ -#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) - -#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) -#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) -/*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0. - */ -#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) - -#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) -#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) -/*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0. - */ -#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) - -#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) -#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) -/*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0. - */ -#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MRT_Register_Masks */ - - -/* MRT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral MRT0 base address */ - #define MRT0_BASE (0x5000D000u) - /** Peripheral MRT0 base address */ - #define MRT0_BASE_NS (0x4000D000u) - /** Peripheral MRT0 base pointer */ - #define MRT0 ((MRT_Type *)MRT0_BASE) - /** Peripheral MRT0 base pointer */ - #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS { MRT0_BASE } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS { MRT0 } - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS_NS { MRT0_NS } -#else - /** Peripheral MRT0 base address */ - #define MRT0_BASE (0x4000D000u) - /** Peripheral MRT0 base pointer */ - #define MRT0 ((MRT_Type *)MRT0_BASE) - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS { MRT0_BASE } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS { MRT0 } -#endif -/** Interrupt vectors for the MRT peripheral type */ -#define MRT_IRQS { MRT0_IRQn } - -/*! - * @} - */ /* end of group MRT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- OSTIMER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer - * @{ - */ - -/** OSTIMER - Register Layout Typedef */ -typedef struct { - __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */ - __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */ - __I uint32_t CAPTURE_L; /**< Capture Low Register, offset: 0x8 */ - __I uint32_t CAPTURE_H; /**< Capture High Register, offset: 0xC */ - __IO uint32_t MATCH_L; /**< Match Low Register, offset: 0x10 */ - __IO uint32_t MATCH_H; /**< Match High Register, offset: 0x14 */ - uint8_t RESERVED_0[4]; - __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register, offset: 0x1C */ -} OSTIMER_Type; - -/* ---------------------------------------------------------------------------- - -- OSTIMER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks - * @{ - */ - -/*! @name EVTIMERL - EVTIMER Low Register */ -/*! @{ */ - -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) -/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the lower 32 bits of the 42-bits - * EVTIMER. Note: There is only one EVTIMER, readable from all domains. - */ -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) -/*! @} */ - -/*! @name EVTIMERH - EVTIMER High Register */ -/*! @{ */ - -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU) -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) -/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the upper 10 bits of the 42-bits - * EVTIMER. Note there is only one EVTIMER, readable from all domains. - */ -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) -/*! @} */ - -/*! @name CAPTURE_L - Capture Low Register */ -/*! @{ */ - -#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U) -/*! CAPTURE_VALUE - A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at - * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). - */ -#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK) -/*! @} */ - -/*! @name CAPTURE_H - Capture High Register */ -/*! @{ */ - -#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0x3FFU) -#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U) -/*! CAPTURE_VALUE - A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at - * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). - */ -#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK) -/*! @} */ - -/*! @name MATCH_L - Match Low Register */ -/*! @{ */ - -#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U) -/*! MATCH_VALUE - The value written to the MATCH (L/H) register pair is compared against the central - * EVTIMER. When a match occurs, an interrupt request is generated if enabled. - */ -#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK) -/*! @} */ - -/*! @name MATCH_H - Match High Register */ -/*! @{ */ - -#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0x3FFU) -#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U) -/*! MATCH_VALUE - The value written (upper 10 bits) to the MATCH (L/H) register pair is compared - * against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. - */ -#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK) -/*! @} */ - -/*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register */ -/*! @{ */ - -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) -/*! OSTIMER_INTRFLAG - This bit is set when a match occurs between the central 42-bits EVTIMER and - * the value programmed in the match-register pair. This bit is cleared by writing a '1'. Writes - * to clear this bit are asynchronous. It should be done before a new match value is written into - * the MATCH_L/H registers. - */ -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) - -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) -/*! OSTIMER_INTENA - When this bit is '1' an interrupt/wakeup request to the domain processor will - * be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests - * due to the OSTIMER_INTR flag are blocked. - */ -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) - -#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U) -#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U) -/*! MATCH_WR_RDY - This bit will be low when it is safe to write to reload the Match Registers. In - * typical applications it should not be necessary to test this bit. [1] - */ -#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group OSTIMER_Register_Masks */ - - -/* OSTIMER - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral OSTIMER base address */ - #define OSTIMER_BASE (0x5002D000u) - /** Peripheral OSTIMER base address */ - #define OSTIMER_BASE_NS (0x4002D000u) - /** Peripheral OSTIMER base pointer */ - #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) - /** Peripheral OSTIMER base pointer */ - #define OSTIMER_NS ((OSTIMER_Type *)OSTIMER_BASE_NS) - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS { OSTIMER } - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS_NS { OSTIMER_BASE_NS } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS_NS { OSTIMER_NS } -#else - /** Peripheral OSTIMER base address */ - #define OSTIMER_BASE (0x4002D000u) - /** Peripheral OSTIMER base pointer */ - #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS { OSTIMER } -#endif -/** Interrupt vectors for the OSTIMER peripheral type */ -#define OSTIMER_IRQS { OS_EVENT_IRQn } - -/*! - * @} - */ /* end of group OSTIMER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer - * @{ - */ - -/** PINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ - __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ - __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ - __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ - __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ - __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ - __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ - __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ - __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ - __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ - __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ - __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ - __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ -} PINT_Type; - -/* ---------------------------------------------------------------------------- - -- PINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Register_Masks PINT Register Masks - * @{ - */ - -/*! @name ISEL - Pin Interrupt Mode register */ -/*! @{ */ - -#define PINT_ISEL_PMODE_MASK (0xFFU) -#define PINT_ISEL_PMODE_SHIFT (0U) -/*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt - * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive - */ -#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) -/*! @} */ - -/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ -/*! @{ */ - -#define PINT_IENR_ENRL_MASK (0xFFU) -#define PINT_IENR_ENRL_SHIFT (0U) -/*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the - * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable - * rising edge or level interrupt. - */ -#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) -/*! @} */ - -/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ -/*! @{ */ - -#define PINT_SIENR_SETENRL_MASK (0xFFU) -#define PINT_SIENR_SETENRL_SHIFT (0U) -/*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n - * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. - */ -#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) -/*! @} */ - -/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ -/*! @{ */ - -#define PINT_CIENR_CENRL_MASK (0xFFU) -#define PINT_CIENR_CENRL_SHIFT (0U) -/*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit - * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level - * interrupt. - */ -#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) -/*! @} */ - -/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ -/*! @{ */ - -#define PINT_IENF_ENAF_MASK (0xFFU) -#define PINT_IENF_ENAF_SHIFT (0U) -/*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt. - * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt - * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active - * interrupt level HIGH. - */ -#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) -/*! @} */ - -/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ -/*! @{ */ - -#define PINT_SIENF_SETENAF_MASK (0xFFU) -#define PINT_SIENF_SETENAF_SHIFT (0U) -/*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n - * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable - * falling edge interrupt. - */ -#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) -/*! @} */ - -/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ -/*! @{ */ - -#define PINT_CIENF_CENAF_MASK (0xFFU) -#define PINT_CIENF_CENAF_SHIFT (0U) -/*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n - * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or - * falling edge interrupt disabled. - */ -#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) -/*! @} */ - -/*! @name RISE - Pin interrupt rising edge register */ -/*! @{ */ - -#define PINT_RISE_RDET_MASK (0xFFU) -#define PINT_RISE_RDET_SHIFT (0U) -/*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read - * 0: No rising edge has been detected on this pin since Reset or the last time a one was written - * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the - * last time a one was written to this bit. Write 1: clear rising edge detection for this pin. - */ -#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) -/*! @} */ - -/*! @name FALL - Pin interrupt falling edge register */ -/*! @{ */ - -#define PINT_FALL_FDET_MASK (0xFFU) -#define PINT_FALL_FDET_SHIFT (0U) -/*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read - * 0: No falling edge has been detected on this pin since Reset or the last time a one was - * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or - * the last time a one was written to this bit. Write 1: clear falling edge detection for this - * pin. - */ -#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) -/*! @} */ - -/*! @name IST - Pin interrupt status register */ -/*! @{ */ - -#define PINT_IST_PSTAT_MASK (0xFFU) -#define PINT_IST_PSTAT_SHIFT (0U) -/*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts - * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for - * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this - * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. - * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). - */ -#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) -/*! @} */ - -/*! @name PMCTRL - Pattern match interrupt control register */ -/*! @{ */ - -#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) -#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) -/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. - * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. - * 0b1..Pattern match. Interrupts are driven in response to pattern matches. - */ -#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) - -#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) -#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) -/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. - * 0b0..Disabled. RXEV output to the CPU is disabled. - * 0b1..Enabled. RXEV output to the CPU is enabled. - */ -#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) - -#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) -#define PINT_PMCTRL_PMAT_SHIFT (24U) -/*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field - * indicates that the corresponding product term is matched by the current state of the appropriate - * inputs. - */ -#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) -/*! @} */ - -/*! @name PMSRC - Pattern match interrupt bit-slice source register */ -/*! @{ */ - -#define PINT_PMSRC_SRC0_MASK (0x700U) -#define PINT_PMSRC_SRC0_SHIFT (8U) -/*! SRC0 - Selects the input source for bit slice 0 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. - */ -#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) - -#define PINT_PMSRC_SRC1_MASK (0x3800U) -#define PINT_PMSRC_SRC1_SHIFT (11U) -/*! SRC1 - Selects the input source for bit slice 1 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. - */ -#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) - -#define PINT_PMSRC_SRC2_MASK (0x1C000U) -#define PINT_PMSRC_SRC2_SHIFT (14U) -/*! SRC2 - Selects the input source for bit slice 2 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. - */ -#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) - -#define PINT_PMSRC_SRC3_MASK (0xE0000U) -#define PINT_PMSRC_SRC3_SHIFT (17U) -/*! SRC3 - Selects the input source for bit slice 3 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. - */ -#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) - -#define PINT_PMSRC_SRC4_MASK (0x700000U) -#define PINT_PMSRC_SRC4_SHIFT (20U) -/*! SRC4 - Selects the input source for bit slice 4 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. - */ -#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) - -#define PINT_PMSRC_SRC5_MASK (0x3800000U) -#define PINT_PMSRC_SRC5_SHIFT (23U) -/*! SRC5 - Selects the input source for bit slice 5 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. - */ -#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) - -#define PINT_PMSRC_SRC6_MASK (0x1C000000U) -#define PINT_PMSRC_SRC6_SHIFT (26U) -/*! SRC6 - Selects the input source for bit slice 6 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. - */ -#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) - -#define PINT_PMSRC_SRC7_MASK (0xE0000000U) -#define PINT_PMSRC_SRC7_SHIFT (29U) -/*! SRC7 - Selects the input source for bit slice 7 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. - */ -#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) -/*! @} */ - -/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ -/*! @{ */ - -#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) -#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) -/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. - * 0b0..No effect. Slice 0 is not an endpoint. - * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) - -#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) -#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) -/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. - * 0b0..No effect. Slice 1 is not an endpoint. - * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) - -#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) -#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) -/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. - * 0b0..No effect. Slice 2 is not an endpoint. - * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) - -#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) -#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) -/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. - * 0b0..No effect. Slice 3 is not an endpoint. - * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) - -#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) -#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) -/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. - * 0b0..No effect. Slice 4 is not an endpoint. - * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) - -#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) -#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) -/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. - * 0b0..No effect. Slice 5 is not an endpoint. - * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) - -#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) -#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) -/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. - * 0b0..No effect. Slice 6 is not an endpoint. - * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) - -#define PINT_PMCFG_CFG0_MASK (0x700U) -#define PINT_PMCFG_CFG0_SHIFT (8U) -/*! CFG0 - Specifies the match contribution condition for bit slice 0. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) - -#define PINT_PMCFG_CFG1_MASK (0x3800U) -#define PINT_PMCFG_CFG1_SHIFT (11U) -/*! CFG1 - Specifies the match contribution condition for bit slice 1. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) - -#define PINT_PMCFG_CFG2_MASK (0x1C000U) -#define PINT_PMCFG_CFG2_SHIFT (14U) -/*! CFG2 - Specifies the match contribution condition for bit slice 2. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) - -#define PINT_PMCFG_CFG3_MASK (0xE0000U) -#define PINT_PMCFG_CFG3_SHIFT (17U) -/*! CFG3 - Specifies the match contribution condition for bit slice 3. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) - -#define PINT_PMCFG_CFG4_MASK (0x700000U) -#define PINT_PMCFG_CFG4_SHIFT (20U) -/*! CFG4 - Specifies the match contribution condition for bit slice 4. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) - -#define PINT_PMCFG_CFG5_MASK (0x3800000U) -#define PINT_PMCFG_CFG5_SHIFT (23U) -/*! CFG5 - Specifies the match contribution condition for bit slice 5. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) - -#define PINT_PMCFG_CFG6_MASK (0x1C000000U) -#define PINT_PMCFG_CFG6_SHIFT (26U) -/*! CFG6 - Specifies the match contribution condition for bit slice 6. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) - -#define PINT_PMCFG_CFG7_MASK (0xE0000000U) -#define PINT_PMCFG_CFG7_SHIFT (29U) -/*! CFG7 - Specifies the match contribution condition for bit slice 7. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last - * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the - * PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input - * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only - * cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or - * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit - * is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PINT_Register_Masks */ - - -/* PINT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PINT base address */ - #define PINT_BASE (0x50004000u) - /** Peripheral PINT base address */ - #define PINT_BASE_NS (0x40004000u) - /** Peripheral PINT base pointer */ - #define PINT ((PINT_Type *)PINT_BASE) - /** Peripheral PINT base pointer */ - #define PINT_NS ((PINT_Type *)PINT_BASE_NS) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE (0x50005000u) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE_NS (0x40005000u) - /** Peripheral SECPINT base pointer */ - #define SECPINT ((PINT_Type *)SECPINT_BASE) - /** Peripheral SECPINT base pointer */ - #define SECPINT_NS ((PINT_Type *)SECPINT_BASE_NS) - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS { PINT, SECPINT } - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS_NS { PINT_BASE_NS, SECPINT_BASE_NS } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS_NS { PINT_NS, SECPINT_NS } -#else - /** Peripheral PINT base address */ - #define PINT_BASE (0x40004000u) - /** Peripheral PINT base pointer */ - #define PINT ((PINT_Type *)PINT_BASE) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE (0x40005000u) - /** Peripheral SECPINT base pointer */ - #define SECPINT ((PINT_Type *)SECPINT_BASE) - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS { PINT, SECPINT } -#endif -/** Interrupt vectors for the PINT peripheral type */ -#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn } - -/*! - * @} - */ /* end of group PINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PLU Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PLU_Peripheral_Access_Layer PLU Peripheral Access Layer - * @{ - */ - -/** PLU - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x20 */ - __IO uint32_t INP_MUX[5]; /**< LUTn input x MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */ - uint8_t RESERVED_0[12]; - } LUT[26]; - uint8_t RESERVED_0[1216]; - __IO uint32_t LUT_TRUTH[26]; /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25, array offset: 0x800, array step: 0x4 */ - uint8_t RESERVED_1[152]; - __I uint32_t OUTPUTS; /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */ - __IO uint32_t WAKEINT_CTRL; /**< Wakeup interrupt control for PLU, offset: 0x904 */ - uint8_t RESERVED_2[760]; - __IO uint32_t OUTPUT_MUX[8]; /**< Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */ -} PLU_Type; - -/* ---------------------------------------------------------------------------- - -- PLU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PLU_Register_Masks PLU Register Masks - * @{ - */ - -/*! @name LUT_INP_MUX - LUTn input x MUX */ -/*! @{ */ - -#define PLU_LUT_INP_MUX_LUTn_INPx_MASK (0x3FU) -#define PLU_LUT_INP_MUX_LUTn_INPx_SHIFT (0U) -/*! LUTn_INPx - Selects the input source to be connected to LUT25 input4. For each LUT, the slot - * associated with the output from LUTn itself is tied low. - * 0b000000..The PLU primary inputs 0. - * 0b000001..The PLU primary inputs 1. - * 0b000010..The PLU primary inputs 2. - * 0b000011..The PLU primary inputs 3. - * 0b000100..The PLU primary inputs 4. - * 0b000101..The PLU primary inputs 5. - * 0b000110..The output of LUT0. - * 0b000111..The output of LUT1. - * 0b001000..The output of LUT2. - * 0b001001..The output of LUT3. - * 0b001010..The output of LUT4. - * 0b001011..The output of LUT5. - * 0b001100..The output of LUT6. - * 0b001101..The output of LUT7. - * 0b001110..The output of LUT8. - * 0b001111..The output of LUT9. - * 0b010000..The output of LUT10. - * 0b010001..The output of LUT11. - * 0b010010..The output of LUT12. - * 0b010011..The output of LUT13. - * 0b010100..The output of LUT14. - * 0b010101..The output of LUT15. - * 0b010110..The output of LUT16. - * 0b010111..The output of LUT17. - * 0b011000..The output of LUT18. - * 0b011001..The output of LUT19. - * 0b011010..The output of LUT20. - * 0b011011..The output of LUT21. - * 0b011100..The output of LUT22. - * 0b011101..The output of LUT23. - * 0b011110..The output of LUT24. - * 0b011111..The output of LUT25. - * 0b100000..state(0). - * 0b100001..state(1). - * 0b100010..state(2). - * 0b100011..state(3). - */ -#define PLU_LUT_INP_MUX_LUTn_INPx(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_MUX_LUTn_INPx_SHIFT)) & PLU_LUT_INP_MUX_LUTn_INPx_MASK) -/*! @} */ - -/* The count of PLU_LUT_INP_MUX */ -#define PLU_LUT_INP_MUX_COUNT (26U) - -/* The count of PLU_LUT_INP_MUX */ -#define PLU_LUT_INP_MUX_COUNT2 (5U) - -/*! @name LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */ -/*! @{ */ - -#define PLU_LUT_TRUTH_LUTn_TRUTH_MASK (0xFFFFFFFFU) -#define PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT (0U) -/*! LUTn_TRUTH - Specifies the Truth Table contents for LUT25.. - */ -#define PLU_LUT_TRUTH_LUTn_TRUTH(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT)) & PLU_LUT_TRUTH_LUTn_TRUTH_MASK) -/*! @} */ - -/* The count of PLU_LUT_TRUTH */ -#define PLU_LUT_TRUTH_COUNT (26U) - -/*! @name OUTPUTS - Provides the current state of the 8 designated PLU Outputs. */ -/*! @{ */ - -#define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU) -#define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U) -/*! OUTPUT_STATE - Provides the current state of the 8 designated PLU Outputs.. - */ -#define PLU_OUTPUTS_OUTPUT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK) -/*! @} */ - -/*! @name WAKEINT_CTRL - Wakeup interrupt control for PLU */ -/*! @{ */ - -#define PLU_WAKEINT_CTRL_MASK_MASK (0xFFU) -#define PLU_WAKEINT_CTRL_MASK_SHIFT (0U) -/*! MASK - Interrupt mask (which of the 8 PLU Outputs contribute to interrupt) - */ -#define PLU_WAKEINT_CTRL_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_MASK_SHIFT)) & PLU_WAKEINT_CTRL_MASK_MASK) - -#define PLU_WAKEINT_CTRL_FILTER_MODE_MASK (0x300U) -#define PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT (8U) -/*! FILTER_MODE - control input of the PLU, add filtering for glitch. - * 0b00..Bypass mode. - * 0b01..Filter 1 clock period. - * 0b10..Filter 2 clock period. - * 0b11..Filter 3 clock period. - */ -#define PLU_WAKEINT_CTRL_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_MODE_MASK) - -#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK (0xC00U) -#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT (10U) -/*! FILTER_CLKSEL - hclk is divided by 2**filter_clksel. - * 0b00..Selects the 1 MHz low-power oscillator as the filter clock. - * 0b01..Selects the 12 Mhz FRO as the filter clock. - * 0b10..Selects a third filter clock source, if provided. - * 0b11..Reserved. - */ -#define PLU_WAKEINT_CTRL_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK) - -#define PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK (0x1000U) -#define PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT (12U) -/*! LATCH_ENABLE - latch the interrupt , then can be cleared with next bit INTR_CLEAR - */ -#define PLU_WAKEINT_CTRL_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK) - -#define PLU_WAKEINT_CTRL_INTR_CLEAR_MASK (0x2000U) -#define PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT (13U) -/*! INTR_CLEAR - Write to clear wakeint_latched - */ -#define PLU_WAKEINT_CTRL_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK) -/*! @} */ - -/*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7 */ -/*! @{ */ - -#define PLU_OUTPUT_MUX_OUTPUTn_MASK (0x1FU) -#define PLU_OUTPUT_MUX_OUTPUTn_SHIFT (0U) -/*! OUTPUTn - Selects the source to be connected to PLU Output 7. - * 0b00000..The PLU output 0. - * 0b00001..The PLU output 1. - * 0b00010..The PLU output 2. - * 0b00011..The PLU output 3. - * 0b00100..The PLU output 4. - * 0b00101..The PLU output 5. - * 0b00110..The PLU output 6. - * 0b00111..The PLU output 7. - * 0b01000..The PLU output 8. - * 0b01001..The PLU output 9. - * 0b01010..The PLU output 10. - * 0b01011..The PLU output 11. - * 0b01100..The PLU output 12. - * 0b01101..The PLU output 13. - * 0b01110..The PLU output 14. - * 0b01111..The PLU output 15. - * 0b10000..The PLU output 16. - * 0b10001..The PLU output 17. - * 0b10010..The PLU output 18. - * 0b10011..The PLU output 19. - * 0b10100..The PLU output 20. - * 0b10101..The PLU output 21. - * 0b10110..The PLU output 22. - * 0b10111..The PLU output 23. - * 0b11000..The PLU output 24. - * 0b11001..The PLU output 25. - * 0b11010..state(0). - * 0b11011..state(1). - * 0b11100..state(2). - * 0b11101..state(3). - */ -#define PLU_OUTPUT_MUX_OUTPUTn(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUTn_SHIFT)) & PLU_OUTPUT_MUX_OUTPUTn_MASK) -/*! @} */ - -/* The count of PLU_OUTPUT_MUX */ -#define PLU_OUTPUT_MUX_COUNT (8U) - - -/*! - * @} - */ /* end of group PLU_Register_Masks */ - - -/* PLU - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PLU base address */ - #define PLU_BASE (0x5003D000u) - /** Peripheral PLU base address */ - #define PLU_BASE_NS (0x4003D000u) - /** Peripheral PLU base pointer */ - #define PLU ((PLU_Type *)PLU_BASE) - /** Peripheral PLU base pointer */ - #define PLU_NS ((PLU_Type *)PLU_BASE_NS) - /** Array initializer of PLU peripheral base addresses */ - #define PLU_BASE_ADDRS { PLU_BASE } - /** Array initializer of PLU peripheral base pointers */ - #define PLU_BASE_PTRS { PLU } - /** Array initializer of PLU peripheral base addresses */ - #define PLU_BASE_ADDRS_NS { PLU_BASE_NS } - /** Array initializer of PLU peripheral base pointers */ - #define PLU_BASE_PTRS_NS { PLU_NS } -#else - /** Peripheral PLU base address */ - #define PLU_BASE (0x4003D000u) - /** Peripheral PLU base pointer */ - #define PLU ((PLU_Type *)PLU_BASE) - /** Array initializer of PLU peripheral base addresses */ - #define PLU_BASE_ADDRS { PLU_BASE } - /** Array initializer of PLU peripheral base pointers */ - #define PLU_BASE_PTRS { PLU } -#endif - -/*! - * @} - */ /* end of group PLU_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer - * @{ - */ - -/** PMC - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4]; - __I uint32_t STATUS; /**< Power Management Controller FSM (Finite State Machines) status, offset: 0x4 */ - __IO uint32_t RESETCTRL; /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x8 */ - uint8_t RESERVED_1[4]; - __IO uint32_t DCDC0; /**< DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x10 */ - __IO uint32_t DCDC1; /**< DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x14 */ - uint8_t RESERVED_2[4]; - __IO uint32_t LDOPMU; /**< Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x1C */ - uint8_t RESERVED_3[16]; - __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */ - uint8_t RESERVED_4[12]; - __IO uint32_t REFFASTWKUP; /**< Analog References fast wake-up Control register [Reset by: PoR], offset: 0x40 */ - uint8_t RESERVED_5[8]; - __IO uint32_t XTAL32K; /**< 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x4C */ - __IO uint32_t COMP; /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x50 */ - uint8_t RESERVED_6[16]; - __IO uint32_t WAKEUPIOCTRL; /**< Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset], offset: 0x64 */ - __IO uint32_t WAKEIOCAUSE; /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */ - uint8_t RESERVED_7[8]; - __IO uint32_t STATUSCLK; /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */ - uint8_t RESERVED_8[12]; - __IO uint32_t AOREG1; /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset], offset: 0x84 */ - uint8_t RESERVED_9[8]; - __IO uint32_t MISCCTRL; /**< Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x90 */ - uint8_t RESERVED_10[4]; - __IO uint32_t RTCOSC32K; /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x98 */ - __IO uint32_t OSTIMERr; /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C */ - uint8_t RESERVED_11[24]; - __IO uint32_t PDRUNCFG0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */ - uint8_t RESERVED_12[4]; - __O uint32_t PDRUNCFGSET0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */ - uint8_t RESERVED_13[4]; - __O uint32_t PDRUNCFGCLR0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */ - uint8_t RESERVED_14[8]; - __IO uint32_t SRAMCTRL; /**< All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xD4 */ -} PMC_Type; - -/* ---------------------------------------------------------------------------- - -- PMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Register_Masks PMC Register Masks - * @{ - */ - -/*! @name STATUS - Power Management Controller FSM (Finite State Machines) status */ -/*! @{ */ - -#define PMC_STATUS_BOOTMODE_MASK (0xC0000U) -#define PMC_STATUS_BOOTMODE_SHIFT (18U) -/*! BOOTMODE - Latest IC Boot cause:. - * 0b00..Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset). - * 0b01..Latest IC boot was from DEEP SLEEP low power mode. - * 0b10..Latest IC boot was from POWER DOWN low power mode. - * 0b11..Latest IC boot was from DEEP POWER DOWN low power mode. - */ -#define PMC_STATUS_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_BOOTMODE_SHIFT)) & PMC_STATUS_BOOTMODE_MASK) -/*! @} */ - -/*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U) -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U) -/*! DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). - * 0b0..Reset event from DEEP POWER DOWN mode is disable. - * 0b1..Reset event from DEEP POWER DOWN mode is enable. - */ -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK) - -#define PMC_RESETCTRL_BODVBATRESETENABLE_MASK (0x2U) -#define PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT (1U) -/*! BODVBATRESETENABLE - BOD VBAT reset enable. - * 0b0..BOD VBAT reset is disable. - * 0b1..BOD VBAT reset is enable. - */ -#define PMC_RESETCTRL_BODVBATRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENABLE_MASK) - -#define PMC_RESETCTRL_BODCORERESETENABLE_MASK (0x4U) -#define PMC_RESETCTRL_BODCORERESETENABLE_SHIFT (2U) -/*! BODCORERESETENABLE - BOD CORE reset enable. - * 0b0..BOD CORE reset is disable. - * 0b1..BOD CORE reset is enable. - */ -#define PMC_RESETCTRL_BODCORERESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENABLE_SHIFT)) & PMC_RESETCTRL_BODCORERESETENABLE_MASK) - -#define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U) -#define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U) -/*! SWRRESETENABLE - Software reset enable. - * 0b0..Software reset is disable. - * 0b1..Software reset is enable. - */ -#define PMC_RESETCTRL_SWRRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK) -/*! @} */ - -/*! @name DCDC0 - DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_DCDC0_RC_MASK (0x3FU) -#define PMC_DCDC0_RC_SHIFT (0U) -/*! RC - Constant On-Time calibration. - */ -#define PMC_DCDC0_RC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_RC_SHIFT)) & PMC_DCDC0_RC_MASK) - -#define PMC_DCDC0_ICOMP_MASK (0xC0U) -#define PMC_DCDC0_ICOMP_SHIFT (6U) -/*! ICOMP - Select the type of ZCD comparator. - */ -#define PMC_DCDC0_ICOMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICOMP_SHIFT)) & PMC_DCDC0_ICOMP_MASK) - -#define PMC_DCDC0_ISEL_MASK (0x300U) -#define PMC_DCDC0_ISEL_SHIFT (8U) -/*! ISEL - Alter Internal biasing currents. - */ -#define PMC_DCDC0_ISEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ISEL_SHIFT)) & PMC_DCDC0_ISEL_MASK) - -#define PMC_DCDC0_ICENABLE_MASK (0x400U) -#define PMC_DCDC0_ICENABLE_SHIFT (10U) -/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD. - */ -#define PMC_DCDC0_ICENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICENABLE_SHIFT)) & PMC_DCDC0_ICENABLE_MASK) - -#define PMC_DCDC0_TMOS_MASK (0xF800U) -#define PMC_DCDC0_TMOS_SHIFT (11U) -/*! TMOS - One-shot generator reference current trimming signal. - */ -#define PMC_DCDC0_TMOS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_TMOS_SHIFT)) & PMC_DCDC0_TMOS_MASK) - -#define PMC_DCDC0_DISABLEISENSE_MASK (0x10000U) -#define PMC_DCDC0_DISABLEISENSE_SHIFT (16U) -/*! DISABLEISENSE - Disable Current sensing. - */ -#define PMC_DCDC0_DISABLEISENSE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_DISABLEISENSE_SHIFT)) & PMC_DCDC0_DISABLEISENSE_MASK) - -#define PMC_DCDC0_VOUT_MASK (0x1E0000U) -#define PMC_DCDC0_VOUT_SHIFT (17U) -/*! VOUT - Set output regulation voltage. - * 0b0000..0.95 V. - * 0b0001..0.975 V. - * 0b0010..1 V. - * 0b0011..1.025 V. - * 0b0100..1.05 V. - * 0b0101..1.075 V. - * 0b0110..1.1 V. - * 0b0111..1.125 V. - * 0b1000..1.15 V. - * 0b1001..1.175 V. - * 0b1010..1.2 V. - */ -#define PMC_DCDC0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_SHIFT)) & PMC_DCDC0_VOUT_MASK) - -#define PMC_DCDC0_SLICINGENABLE_MASK (0x200000U) -#define PMC_DCDC0_SLICINGENABLE_SHIFT (21U) -/*! SLICINGENABLE - Enable staggered switching of power switches. - */ -#define PMC_DCDC0_SLICINGENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_SLICINGENABLE_SHIFT)) & PMC_DCDC0_SLICINGENABLE_MASK) - -#define PMC_DCDC0_INDUCTORCLAMPENABLE_MASK (0x400000U) -#define PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT (22U) -/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. - */ -#define PMC_DCDC0_INDUCTORCLAMPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT)) & PMC_DCDC0_INDUCTORCLAMPENABLE_MASK) - -#define PMC_DCDC0_VOUT_PWD_MASK (0x7800000U) -#define PMC_DCDC0_VOUT_PWD_SHIFT (23U) -/*! VOUT_PWD - Set output regulation voltage during Deep Sleep. - */ -#define PMC_DCDC0_VOUT_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_PWD_SHIFT)) & PMC_DCDC0_VOUT_PWD_MASK) -/*! @} */ - -/*! @name DCDC1 - DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_DCDC1_RTRIMOFFET_MASK (0xFU) -#define PMC_DCDC1_RTRIMOFFET_SHIFT (0U) -/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator. - */ -#define PMC_DCDC1_RTRIMOFFET(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RTRIMOFFET_SHIFT)) & PMC_DCDC1_RTRIMOFFET_MASK) - -#define PMC_DCDC1_RSENSETRIM_MASK (0xF0U) -#define PMC_DCDC1_RSENSETRIM_SHIFT (4U) -/*! RSENSETRIM - Adjust Max inductor peak current limiting. - */ -#define PMC_DCDC1_RSENSETRIM(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RSENSETRIM_SHIFT)) & PMC_DCDC1_RSENSETRIM_MASK) - -#define PMC_DCDC1_DTESTENABLE_MASK (0x100U) -#define PMC_DCDC1_DTESTENABLE_SHIFT (8U) -/*! DTESTENABLE - Enable Digital test signals. - */ -#define PMC_DCDC1_DTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTENABLE_SHIFT)) & PMC_DCDC1_DTESTENABLE_MASK) - -#define PMC_DCDC1_SETCURVE_MASK (0x600U) -#define PMC_DCDC1_SETCURVE_SHIFT (9U) -/*! SETCURVE - Bandgap calibration parameter. - */ -#define PMC_DCDC1_SETCURVE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETCURVE_SHIFT)) & PMC_DCDC1_SETCURVE_MASK) - -#define PMC_DCDC1_SETDC_MASK (0x7800U) -#define PMC_DCDC1_SETDC_SHIFT (11U) -/*! SETDC - Bandgap calibration parameter. - */ -#define PMC_DCDC1_SETDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETDC_SHIFT)) & PMC_DCDC1_SETDC_MASK) - -#define PMC_DCDC1_DTESTSEL_MASK (0x38000U) -#define PMC_DCDC1_DTESTSEL_SHIFT (15U) -/*! DTESTSEL - Select the output signal for test. - */ -#define PMC_DCDC1_DTESTSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTSEL_SHIFT)) & PMC_DCDC1_DTESTSEL_MASK) - -#define PMC_DCDC1_ISCALEENABLE_MASK (0x40000U) -#define PMC_DCDC1_ISCALEENABLE_SHIFT (18U) -/*! ISCALEENABLE - Modify COT behavior. - */ -#define PMC_DCDC1_ISCALEENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_ISCALEENABLE_SHIFT)) & PMC_DCDC1_ISCALEENABLE_MASK) - -#define PMC_DCDC1_FORCEBYPASS_MASK (0x80000U) -#define PMC_DCDC1_FORCEBYPASS_SHIFT (19U) -/*! FORCEBYPASS - Force bypass mode. - */ -#define PMC_DCDC1_FORCEBYPASS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEBYPASS_SHIFT)) & PMC_DCDC1_FORCEBYPASS_MASK) - -#define PMC_DCDC1_TRIMAUTOCOT_MASK (0xF00000U) -#define PMC_DCDC1_TRIMAUTOCOT_SHIFT (20U) -/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. - */ -#define PMC_DCDC1_TRIMAUTOCOT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TRIMAUTOCOT_SHIFT)) & PMC_DCDC1_TRIMAUTOCOT_MASK) - -#define PMC_DCDC1_FORCEFULLCYCLE_MASK (0x1000000U) -#define PMC_DCDC1_FORCEFULLCYCLE_SHIFT (24U) -/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. - */ -#define PMC_DCDC1_FORCEFULLCYCLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEFULLCYCLE_SHIFT)) & PMC_DCDC1_FORCEFULLCYCLE_MASK) - -#define PMC_DCDC1_LCENABLE_MASK (0x2000000U) -#define PMC_DCDC1_LCENABLE_SHIFT (25U) -/*! LCENABLE - Change the range of the peak detector of current inside the inductor. - */ -#define PMC_DCDC1_LCENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_LCENABLE_SHIFT)) & PMC_DCDC1_LCENABLE_MASK) - -#define PMC_DCDC1_TOFF_MASK (0x7C000000U) -#define PMC_DCDC1_TOFF_SHIFT (26U) -/*! TOFF - Constant Off-Time calibration input. - */ -#define PMC_DCDC1_TOFF(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFF_SHIFT)) & PMC_DCDC1_TOFF_MASK) - -#define PMC_DCDC1_TOFFENABLE_MASK (0x80000000U) -#define PMC_DCDC1_TOFFENABLE_SHIFT (31U) -/*! TOFFENABLE - Enable Constant Off-Time feature. - */ -#define PMC_DCDC1_TOFFENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFFENABLE_SHIFT)) & PMC_DCDC1_TOFFENABLE_MASK) -/*! @} */ - -/*! @name LDOPMU - Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_LDOPMU_VADJ_MASK (0x1FU) -#define PMC_LDOPMU_VADJ_SHIFT (0U) -/*! VADJ - Sets the Always-On domain LDO output level. - * 0b00000..1.22 V. - * 0b00001..0.7 V. - * 0b00010..0.725 V. - * 0b00011..0.75 V. - * 0b00100..0.775 V. - * 0b00101..0.8 V. - * 0b00110..0.825 V. - * 0b00111..0.85 V. - * 0b01000..0.875 V. - * 0b01001..0.9 V. - * 0b01010..0.96 V. - * 0b01011..0.97 V. - * 0b01100..0.98 V. - * 0b01101..0.99 V. - * 0b01110..1 V. - * 0b01111..1.01 V. - * 0b10000..1.02 V. - * 0b10001..1.03 V. - * 0b10010..1.04 V. - * 0b10011..1.05 V. - * 0b10100..1.06 V. - * 0b10101..1.07 V. - * 0b10110..1.08 V. - * 0b10111..1.09 V. - * 0b11000..1.1 V. - * 0b11001..1.11 V. - * 0b11010..1.12 V. - * 0b11011..1.13 V. - * 0b11100..1.14 V. - * 0b11101..1.15 V. - * 0b11110..1.16 V. - * 0b11111..1.22 V. - */ -#define PMC_LDOPMU_VADJ(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_SHIFT)) & PMC_LDOPMU_VADJ_MASK) - -#define PMC_LDOPMU_VADJ_PWD_MASK (0x3E0U) -#define PMC_LDOPMU_VADJ_PWD_SHIFT (5U) -/*! VADJ_PWD - Sets the Always-On domain LDO output level in all power down modes. - */ -#define PMC_LDOPMU_VADJ_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_PWD_SHIFT)) & PMC_LDOPMU_VADJ_PWD_MASK) - -#define PMC_LDOPMU_VADJ_BOOST_MASK (0x7C00U) -#define PMC_LDOPMU_VADJ_BOOST_SHIFT (10U) -/*! VADJ_BOOST - Sets the Always-On domain LDO Boost output level. - */ -#define PMC_LDOPMU_VADJ_BOOST(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_MASK) - -#define PMC_LDOPMU_VADJ_BOOST_PWD_MASK (0xF8000U) -#define PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT (15U) -/*! VADJ_BOOST_PWD - Sets the Always-On domain LDO Boost output level in all power down modes. - */ -#define PMC_LDOPMU_VADJ_BOOST_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_PWD_MASK) - -#define PMC_LDOPMU_BOOST_ENA_MASK (0x1000000U) -#define PMC_LDOPMU_BOOST_ENA_SHIFT (24U) -/*! BOOST_ENA - Control the LDO AO boost mode in ACTIVE mode. - * 0b0..LDO AO Boost Mode is disable. - * 0b1..LDO AO Boost Mode is enable. - */ -#define PMC_LDOPMU_BOOST_ENA(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_SHIFT)) & PMC_LDOPMU_BOOST_ENA_MASK) - -#define PMC_LDOPMU_BOOST_ENA_PWD_MASK (0x2000000U) -#define PMC_LDOPMU_BOOST_ENA_PWD_SHIFT (25U) -/*! BOOST_ENA_PWD - Control the LDO AO boost mode in the different low power modes (DEEP SLEEP, POWERDOWN, and DEEP POWER DOWN). - * 0b0..LDO AO Boost Mode is disable. - * 0b1..LDO AO Boost Mode is enable. - */ -#define PMC_LDOPMU_BOOST_ENA_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_PWD_SHIFT)) & PMC_LDOPMU_BOOST_ENA_PWD_MASK) -/*! @} */ - -/*! @name BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] */ -/*! @{ */ - -#define PMC_BODVBAT_TRIGLVL_MASK (0x1FU) -#define PMC_BODVBAT_TRIGLVL_SHIFT (0U) -/*! TRIGLVL - BoD trigger level. - * 0b00000..1.00 V. - * 0b00001..1.10 V. - * 0b00010..1.20 V. - * 0b00011..1.30 V. - * 0b00100..1.40 V. - * 0b00101..1.50 V. - * 0b00110..1.60 V. - * 0b00111..1.65 V. - * 0b01000..1.70 V. - * 0b01001..1.75 V. - * 0b01010..1.80 V. - * 0b01011..1.90 V. - * 0b01100..2.00 V. - * 0b01101..2.10 V. - * 0b01110..2.20 V. - * 0b01111..2.30 V. - * 0b10000..2.40 V. - * 0b10001..2.50 V. - * 0b10010..2.60 V. - * 0b10011..2.70 V. - * 0b10100..2.806 V. - * 0b10101..2.90 V. - * 0b10110..3.00 V. - * 0b10111..3.10 V. - * 0b11000..3.20 V. - * 0b11001..3.30 V. - * 0b11010..3.30 V. - * 0b11011..3.30 V. - * 0b11100..3.30 V. - * 0b11101..3.30 V. - * 0b11110..3.30 V. - * 0b11111..3.30 V. - */ -#define PMC_BODVBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_TRIGLVL_SHIFT)) & PMC_BODVBAT_TRIGLVL_MASK) - -#define PMC_BODVBAT_HYST_MASK (0x60U) -#define PMC_BODVBAT_HYST_SHIFT (5U) -/*! HYST - BoD Hysteresis control. - * 0b00..25 mV. - * 0b01..50 mV. - * 0b10..75 mV. - * 0b11..100 mV. - */ -#define PMC_BODVBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK) -/*! @} */ - -/*! @name REFFASTWKUP - Analog References fast wake-up Control register [Reset by: PoR] */ -/*! @{ */ - -#define PMC_REFFASTWKUP_LPWKUP_MASK (0x1U) -#define PMC_REFFASTWKUP_LPWKUP_SHIFT (0U) -/*! LPWKUP - Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP POWER DOWN): . - * 0b0..Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode. - * 0b1..Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode. - */ -#define PMC_REFFASTWKUP_LPWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_LPWKUP_SHIFT)) & PMC_REFFASTWKUP_LPWKUP_MASK) - -#define PMC_REFFASTWKUP_HWWKUP_MASK (0x2U) -#define PMC_REFFASTWKUP_HWWKUP_SHIFT (1U) -/*! HWWKUP - Analog References fast wake-up in case of Hardware Pin reset: . - * 0b0..Analog References fast wake-up feature is disabled in case of Hardware Pin reset. - * 0b1..Analog References fast wake-up feature is enabled in case of Hardware Pin reset. - */ -#define PMC_REFFASTWKUP_HWWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_HWWKUP_SHIFT)) & PMC_REFFASTWKUP_HWWKUP_MASK) -/*! @} */ - -/*! @name XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_XTAL32K_IREF_MASK (0x6U) -#define PMC_XTAL32K_IREF_SHIFT (1U) -/*! IREF - reference output current selection inputs. - */ -#define PMC_XTAL32K_IREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IREF_SHIFT)) & PMC_XTAL32K_IREF_MASK) - -#define PMC_XTAL32K_TEST_MASK (0x8U) -#define PMC_XTAL32K_TEST_SHIFT (3U) -/*! TEST - Oscillator Test Mode. - */ -#define PMC_XTAL32K_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK) - -#define PMC_XTAL32K_IBIAS_MASK (0x30U) -#define PMC_XTAL32K_IBIAS_SHIFT (4U) -/*! IBIAS - bias current selection inputs. - */ -#define PMC_XTAL32K_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IBIAS_SHIFT)) & PMC_XTAL32K_IBIAS_MASK) - -#define PMC_XTAL32K_AMPL_MASK (0xC0U) -#define PMC_XTAL32K_AMPL_SHIFT (6U) -/*! AMPL - oscillator amplitude selection inputs. - */ -#define PMC_XTAL32K_AMPL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_AMPL_SHIFT)) & PMC_XTAL32K_AMPL_MASK) - -#define PMC_XTAL32K_CAPBANKIN_MASK (0x7F00U) -#define PMC_XTAL32K_CAPBANKIN_SHIFT (8U) -/*! CAPBANKIN - Capa bank setting input. - */ -#define PMC_XTAL32K_CAPBANKIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKIN_SHIFT)) & PMC_XTAL32K_CAPBANKIN_MASK) - -#define PMC_XTAL32K_CAPBANKOUT_MASK (0x3F8000U) -#define PMC_XTAL32K_CAPBANKOUT_SHIFT (15U) -/*! CAPBANKOUT - Capa bank setting output. - */ -#define PMC_XTAL32K_CAPBANKOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKOUT_SHIFT)) & PMC_XTAL32K_CAPBANKOUT_MASK) - -#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK (0x400000U) -#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT (22U) -/*! CAPTESTSTARTSRCSEL - Source selection for xo32k_captest_start_ao_set. - * 0b0..Sourced from CAPTESTSTART. - * 0b1..Sourced from calibration. - */ -#define PMC_XTAL32K_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT)) & PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK) - -#define PMC_XTAL32K_CAPTESTSTART_MASK (0x800000U) -#define PMC_XTAL32K_CAPTESTSTART_SHIFT (23U) -/*! CAPTESTSTART - Start test. - */ -#define PMC_XTAL32K_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTART_SHIFT)) & PMC_XTAL32K_CAPTESTSTART_MASK) - -#define PMC_XTAL32K_CAPTESTENABLE_MASK (0x1000000U) -#define PMC_XTAL32K_CAPTESTENABLE_SHIFT (24U) -/*! CAPTESTENABLE - Enable signal for cap test. - */ -#define PMC_XTAL32K_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTENABLE_SHIFT)) & PMC_XTAL32K_CAPTESTENABLE_MASK) - -#define PMC_XTAL32K_CAPTESTOSCINSEL_MASK (0x2000000U) -#define PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT (25U) -/*! CAPTESTOSCINSEL - Select the input for test. - * 0b0..Oscillator output pin (osc_out). - * 0b1..Oscillator input pin (osc_in). - */ -#define PMC_XTAL32K_CAPTESTOSCINSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT)) & PMC_XTAL32K_CAPTESTOSCINSEL_MASK) -/*! @} */ - -/*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_COMP_HYST_MASK (0x2U) -#define PMC_COMP_HYST_SHIFT (1U) -/*! HYST - Hysteris when hyst = '1'. - * 0b0..Hysteresis is disable. - * 0b1..Hysteresis is enable. - */ -#define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK) - -#define PMC_COMP_VREFINPUT_MASK (0x4U) -#define PMC_COMP_VREFINPUT_SHIFT (2U) -/*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). - * 0b0..Select internal VREF. - * 0b1..Select VDDA. - */ -#define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK) - -#define PMC_COMP_LOWPOWER_MASK (0x8U) -#define PMC_COMP_LOWPOWER_SHIFT (3U) -/*! LOWPOWER - Low power mode. - * 0b0..High speed mode. - * 0b1..Low power mode (Low speed). - */ -#define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK) - -#define PMC_COMP_PMUX_MASK (0x70U) -#define PMC_COMP_PMUX_SHIFT (4U) -/*! PMUX - Control word for P multiplexer:. - * 0b000..VREF (See fiedl VREFINPUT). - * 0b001..Pin P0_0. - * 0b010..Pin P0_9. - * 0b011..Pin P0_18. - * 0b100..Pin P1_14. - * 0b101..Pin P2_23. - */ -#define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK) - -#define PMC_COMP_NMUX_MASK (0x380U) -#define PMC_COMP_NMUX_SHIFT (7U) -/*! NMUX - Control word for N multiplexer:. - * 0b000..VREF (See field VREFINPUT). - * 0b001..Pin P0_0. - * 0b010..Pin P0_9. - * 0b011..Pin P0_18. - * 0b100..Pin P1_14. - * 0b101..Pin P2_23. - */ -#define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK) - -#define PMC_COMP_VREF_MASK (0x7C00U) -#define PMC_COMP_VREF_SHIFT (10U) -/*! VREF - Control reference voltage step, per steps of (VREFINPUT/31). - */ -#define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK) - -#define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U) -#define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U) -/*! FILTERCGF_SAMPLEMODE - Control the filtering of the Analog Comparator output. - * 0b00..Bypass mode. - * 0b01..Filter 1 clock period. - * 0b10..Filter 2 clock period. - * 0b11..Filter 3 clock period. - */ -#define PMC_COMP_FILTERCGF_SAMPLEMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK) - -#define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U) -#define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U) -/*! FILTERCGF_CLKDIV - Filter Clock divider. - * 0b000..Filter clock period duration equals 1 Analog Comparator clock period. - * 0b001..Filter clock period duration equals 2 Analog Comparator clock period. - * 0b010..Filter clock period duration equals 4 Analog Comparator clock period. - * 0b011..Filter clock period duration equals 8 Analog Comparator clock period. - * 0b100..Filter clock period duration equals 16 Analog Comparator clock period. - * 0b101..Filter clock period duration equals 32 Analog Comparator clock period. - * 0b110..Filter clock period duration equals 64 Analog Comparator clock period. - * 0b111..Filter clock period duration equals 128 Analog Comparator clock period. - */ -#define PMC_COMP_FILTERCGF_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK) -/*! @} */ - -/*! @name WAKEUPIOCTRL - Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] */ -/*! @{ */ - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK (0x1U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT (0U) -/*! RISINGEDGEWAKEUP0 - Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disable. - * 0b1..Rising edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK (0x2U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT (1U) -/*! FALLINGEDGEWAKEUP0 - Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disable. - * 0b1..Falling edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK) - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK (0x4U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT (2U) -/*! RISINGEDGEWAKEUP1 - Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disable. - * 0b1..Rising edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK (0x8U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT (3U) -/*! FALLINGEDGEWAKEUP1 - Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disable. - * 0b1..Falling edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK) - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK (0x10U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT (4U) -/*! RISINGEDGEWAKEUP2 - Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disable. - * 0b1..Rising edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK (0x20U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT (5U) -/*! FALLINGEDGEWAKEUP2 - Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disable. - * 0b1..Falling edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK) - -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK (0x40U) -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT (6U) -/*! RISINGEDGEWAKEUP3 - Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes:. - * 0b0..Rising edge detection is disable. - * 0b1..Rising edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK) - -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK (0x80U) -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT (7U) -/*! FALLINGEDGEWAKEUP3 - Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes:. - * 0b0..Falling edge detection is disable. - * 0b1..Falling edge detection is enable. - */ -#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUP0_MASK (0x100U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUP0_SHIFT (8U) -/*! MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP0_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUP1_MASK (0x200U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUP1_SHIFT (9U) -/*! MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP1_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUP2_MASK (0x400U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUP2_SHIFT (10U) -/*! MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP2_MASK) - -#define PMC_WAKEUPIOCTRL_MODEWAKEUP3_MASK (0x800U) -#define PMC_WAKEUPIOCTRL_MODEWAKEUP3_SHIFT (11U) -/*! MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode - */ -#define PMC_WAKEUPIOCTRL_MODEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP3_MASK) -/*! @} */ - -/*! @name WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode */ -/*! @{ */ - -#define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U) -#define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U) -/*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0. - */ -#define PMC_WAKEIOCAUSE_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK) - -#define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U) -#define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U) -/*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1. - */ -#define PMC_WAKEIOCAUSE_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK) - -#define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U) -#define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U) -/*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2. - */ -#define PMC_WAKEIOCAUSE_WAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK) - -#define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U) -#define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U) -/*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 3. - */ -#define PMC_WAKEIOCAUSE_WAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK) -/*! @} */ - -/*! @name STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U) -#define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U) -/*! XTAL32KOK - XTAL oscillator 32 K OK signal. - */ -#define PMC_STATUSCLK_XTAL32KOK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK) - -#define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U) -#define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U) -/*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. - * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared. - * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared. - */ -#define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK) -/*! @} */ - -/*! @name AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_AOREG1_POR_MASK (0x10U) -#define PMC_AOREG1_POR_SHIFT (4U) -/*! POR - The last chip reset was caused by a Power On Reset. - */ -#define PMC_AOREG1_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_POR_SHIFT)) & PMC_AOREG1_POR_MASK) - -#define PMC_AOREG1_PADRESET_MASK (0x20U) -#define PMC_AOREG1_PADRESET_SHIFT (5U) -/*! PADRESET - The last chip reset was caused by a Pin Reset. - */ -#define PMC_AOREG1_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_PADRESET_SHIFT)) & PMC_AOREG1_PADRESET_MASK) - -#define PMC_AOREG1_BODRESET_MASK (0x40U) -#define PMC_AOREG1_BODRESET_SHIFT (6U) -/*! BODRESET - The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. - */ -#define PMC_AOREG1_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BODRESET_SHIFT)) & PMC_AOREG1_BODRESET_MASK) - -#define PMC_AOREG1_SYSTEMRESET_MASK (0x80U) -#define PMC_AOREG1_SYSTEMRESET_SHIFT (7U) -/*! SYSTEMRESET - The last chip reset was caused by a System Reset requested by the ARM CPU. - */ -#define PMC_AOREG1_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SYSTEMRESET_SHIFT)) & PMC_AOREG1_SYSTEMRESET_MASK) - -#define PMC_AOREG1_WDTRESET_MASK (0x100U) -#define PMC_AOREG1_WDTRESET_SHIFT (8U) -/*! WDTRESET - The last chip reset was caused by the Watchdog Timer. - */ -#define PMC_AOREG1_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_WDTRESET_SHIFT)) & PMC_AOREG1_WDTRESET_MASK) - -#define PMC_AOREG1_SWRRESET_MASK (0x200U) -#define PMC_AOREG1_SWRRESET_SHIFT (9U) -/*! SWRRESET - The last chip reset was caused by a Software event. - */ -#define PMC_AOREG1_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SWRRESET_SHIFT)) & PMC_AOREG1_SWRRESET_MASK) - -#define PMC_AOREG1_DPDRESET_WAKEUPIO_MASK (0x400U) -#define PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT (10U) -/*! DPDRESET_WAKEUPIO - The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode. - */ -#define PMC_AOREG1_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT)) & PMC_AOREG1_DPDRESET_WAKEUPIO_MASK) - -#define PMC_AOREG1_DPDRESET_RTC_MASK (0x800U) -#define PMC_AOREG1_DPDRESET_RTC_SHIFT (11U) -/*! DPDRESET_RTC - The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode. - */ -#define PMC_AOREG1_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_RTC_SHIFT)) & PMC_AOREG1_DPDRESET_RTC_MASK) - -#define PMC_AOREG1_DPDRESET_OSTIMER_MASK (0x1000U) -#define PMC_AOREG1_DPDRESET_OSTIMER_SHIFT (12U) -/*! DPDRESET_OSTIMER - The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode. - */ -#define PMC_AOREG1_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_OSTIMER_SHIFT)) & PMC_AOREG1_DPDRESET_OSTIMER_MASK) - -#define PMC_AOREG1_BOOTERRORCOUNTER_MASK (0xF0000U) -#define PMC_AOREG1_BOOTERRORCOUNTER_SHIFT (16U) -/*! BOOTERRORCOUNTER - ROM Boot Fatal Error Counter. - */ -#define PMC_AOREG1_BOOTERRORCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BOOTERRORCOUNTER_SHIFT)) & PMC_AOREG1_BOOTERRORCOUNTER_MASK) -/*! @} */ - -/*! @name MISCCTRL - Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_MISCCTRL_LDODEEPSLEEPREF_MASK (0x1U) -#define PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT (0U) -/*! LDODEEPSLEEPREF - Select LDO Deep Sleep reference source. - * 0b0..LDO DEEP Sleep uses Flash buffer biasing as reference. - * 0b1..LDO DEEP Sleep uses Band Gap 0.8V as reference. - */ -#define PMC_MISCCTRL_LDODEEPSLEEPREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT)) & PMC_MISCCTRL_LDODEEPSLEEPREF_MASK) - -#define PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK (0x2U) -#define PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT (1U) -/*! LDOMEMHIGHZMODE - Control the activation of LDO MEM High Z mode. - * 0b0..LDO MEM High Z mode is disabled. - * 0b1..LDO MEM High Z mode is enabled. - */ -#define PMC_MISCCTRL_LDOMEMHIGHZMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT)) & PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK) - -#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK (0x4U) -#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT (2U) -#define PMC_MISCCTRL_LOWPWR_FLASH_BUF(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT)) & PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK) - -#define PMC_MISCCTRL_MISCCTRL_3_8_MASK (0xF8U) -#define PMC_MISCCTRL_MISCCTRL_3_8_SHIFT (3U) -/*! MISCCTRL_3_8 - Reserved. - */ -#define PMC_MISCCTRL_MISCCTRL_3_8(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_3_8_SHIFT)) & PMC_MISCCTRL_MISCCTRL_3_8_MASK) - -#define PMC_MISCCTRL_MODEWAKEUP0_MASK (0x100U) -#define PMC_MISCCTRL_MODEWAKEUP0_SHIFT (8U) -/*! MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode - */ -#define PMC_MISCCTRL_MODEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP0_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP0_MASK) - -#define PMC_MISCCTRL_MODEWAKEUP1_MASK (0x200U) -#define PMC_MISCCTRL_MODEWAKEUP1_SHIFT (9U) -/*! MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode - */ -#define PMC_MISCCTRL_MODEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP1_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP1_MASK) - -#define PMC_MISCCTRL_MODEWAKEUP2_MASK (0x400U) -#define PMC_MISCCTRL_MODEWAKEUP2_SHIFT (10U) -/*! MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode - */ -#define PMC_MISCCTRL_MODEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP2_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP2_MASK) - -#define PMC_MISCCTRL_MODEWAKEUP3_MASK (0x800U) -#define PMC_MISCCTRL_MODEWAKEUP3_SHIFT (11U) -/*! MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode - */ -#define PMC_MISCCTRL_MODEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP3_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP3_MASK) - -#define PMC_MISCCTRL_DISABLE_BLEED_MASK (0x1000U) -#define PMC_MISCCTRL_DISABLE_BLEED_SHIFT (12U) -/*! DISABLE_BLEED - Controls LDO MEM bleed current. This field is expected to be controlled by the - * Low Power Software only in DEEP SLEEP low power mode. - * 0b0..LDO_MEM bleed current is enabled. - * 0b1..LDO_MEM bleed current is disabled. Should be set before entering in Deep Sleep low power mode and cleared - * after wake up from Deep SLeep low power mode. - */ -#define PMC_MISCCTRL_DISABLE_BLEED(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_DISABLE_BLEED_SHIFT)) & PMC_MISCCTRL_DISABLE_BLEED_MASK) - -#define PMC_MISCCTRL_MISCCTRL_13_14_MASK (0x6000U) -#define PMC_MISCCTRL_MISCCTRL_13_14_SHIFT (13U) -/*! MISCCTRL_13_14 - Reserved. - */ -#define PMC_MISCCTRL_MISCCTRL_13_14(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_13_14_SHIFT)) & PMC_MISCCTRL_MISCCTRL_13_14_MASK) - -#define PMC_MISCCTRL_WAKUPIO_RST_MASK (0x8000U) -#define PMC_MISCCTRL_WAKUPIO_RST_SHIFT (15U) -/*! WAKUPIO_RST - WAKEUP IO event detector reset control. - * 0b1..Wakeup IO is reset. - * 0b0..Wakeup IO is not reset. - */ -#define PMC_MISCCTRL_WAKUPIO_RST(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_WAKUPIO_RST_SHIFT)) & PMC_MISCCTRL_WAKUPIO_RST_MASK) -/*! @} */ - -/*! @name RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_RTCOSC32K_SEL_MASK (0x1U) -#define PMC_RTCOSC32K_SEL_SHIFT (0U) -/*! SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . - * 0b0..FRO 32 KHz. - * 0b1..XTAL 32KHz. - */ -#define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK) - -#define PMC_RTCOSC32K_CLK1KHZDIV_MASK (0xEU) -#define PMC_RTCOSC32K_CLK1KHZDIV_SHIFT (1U) -/*! CLK1KHZDIV - Actual division ratio is : 28 + CLK1KHZDIV. - */ -#define PMC_RTCOSC32K_CLK1KHZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIV_MASK) - -#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK (0x8000U) -#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT (15U) -/*! CLK1KHZDIVUPDATEREQ - RTC 1KHz clock Divider status flag. - */ -#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK) - -#define PMC_RTCOSC32K_CLK1HZDIV_MASK (0x7FF0000U) -#define PMC_RTCOSC32K_CLK1HZDIV_SHIFT (16U) -/*! CLK1HZDIV - Actual division ratio is : 31744 + CLK1HZDIV. - */ -#define PMC_RTCOSC32K_CLK1HZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIV_MASK) - -#define PMC_RTCOSC32K_CLK1HZDIVHALT_MASK (0x40000000U) -#define PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT (30U) -/*! CLK1HZDIVHALT - Halts the divider counter. - */ -#define PMC_RTCOSC32K_CLK1HZDIVHALT(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVHALT_MASK) - -#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK (0x80000000U) -#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT (31U) -/*! CLK1HZDIVUPDATEREQ - RTC 1Hz Divider status flag. - */ -#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK) -/*! @} */ - -/*! @name OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ - -#define PMC_OSTIMER_SOFTRESET_MASK (0x1U) -#define PMC_OSTIMER_SOFTRESET_SHIFT (0U) -/*! SOFTRESET - Active high reset. - */ -#define PMC_OSTIMER_SOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_SOFTRESET_SHIFT)) & PMC_OSTIMER_SOFTRESET_MASK) - -#define PMC_OSTIMER_CLOCKENABLE_MASK (0x2U) -#define PMC_OSTIMER_CLOCKENABLE_SHIFT (1U) -/*! CLOCKENABLE - Enable OSTIMER 32 KHz clock. - */ -#define PMC_OSTIMER_CLOCKENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_CLOCKENABLE_SHIFT)) & PMC_OSTIMER_CLOCKENABLE_MASK) - -#define PMC_OSTIMER_DPDWAKEUPENABLE_MASK (0x4U) -#define PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT (2U) -/*! DPDWAKEUPENABLE - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode). - */ -#define PMC_OSTIMER_DPDWAKEUPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSTIMER_DPDWAKEUPENABLE_MASK) - -#define PMC_OSTIMER_OSC32KPD_MASK (0x8U) -#define PMC_OSTIMER_OSC32KPD_SHIFT (3U) -/*! OSC32KPD - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K. - */ -#define PMC_OSTIMER_OSC32KPD(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSC32KPD_SHIFT)) & PMC_OSTIMER_OSC32KPD_MASK) -/*! @} */ - -/*! @name PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_PDRUNCFG0_PDEN_BODVBAT_MASK (0x8U) -#define PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT (3U) -/*! PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD). - * 0b0..BOD VBAT is powered. - * 0b1..BOD VBAT is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVBAT_MASK) - -#define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U) -#define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U) -/*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. - * 0b0..FRO32KHz is powered. - * 0b1..FRO32KHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK) - -#define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U) -#define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U) -/*! PDEN_XTAL32K - Controls power to crystal 32 KHz. - * 0b0..Crystal 32KHz is powered. - * 0b1..Crystal 32KHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK) - -#define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK (0x100U) -#define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT (8U) -/*! PDEN_XTAL32M - Controls power to high speed crystal. - * 0b0..High speed crystal is powered. - * 0b1..High speed crystal is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK) - -#define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U) -#define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U) -/*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). - * 0b0..PLL0 is powered. - * 0b1..PLL0 is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK) - -#define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U) -#define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U) -/*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1). - * 0b0..PLL1 is powered. - * 0b1..PLL1 is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK) - -#define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK (0x800U) -#define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT (11U) -/*! PDEN_USBFSPHY - Controls power to USB Full Speed phy. - * 0b0..USB Full Speed phy is powered. - * 0b1..USB Full Speed phy is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK) - -#define PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK (0x1000U) -#define PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT (12U) -/*! PDEN_USBHSPHY - Controls power to USB High Speed Phy. - * 0b0..USB HS phy is powered. - * 0b1..USB HS phy is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK) - -#define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U) -#define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U) -/*! PDEN_COMP - Controls power to Analog Comparator. - * 0b0..Analog Comparator is powered. - * 0b1..Analog Comparator is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK) - -#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK (0x40000U) -#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT (18U) -/*! PDEN_LDOUSBHS - Controls power to USB high speed LDO. - * 0b0..USB high speed LDO is powered. - * 0b1..USB high speed LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK) - -#define PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK (0x80000U) -#define PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT (19U) -/*! PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS) - * 0b0..auxiliary biasing is powered. - * 0b1..auxiliary biasing is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK) - -#define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK (0x100000U) -#define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT (20U) -/*! PDEN_LDOXO32M - Controls power to high speed crystal LDO. - * 0b0..High speed crystal LDO is powered. - * 0b1..High speed crystal LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK) - -#define PMC_PDRUNCFG0_PDEN_RNG_MASK (0x400000U) -#define PMC_PDRUNCFG0_PDEN_RNG_SHIFT (22U) -/*! PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources. - * 0b0..TRNG clocks are powered. - * 0b1..TRNG clocks are powered down. - */ -#define PMC_PDRUNCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_RNG_SHIFT)) & PMC_PDRUNCFG0_PDEN_RNG_MASK) - -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U) -/*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. - * 0b0..PLL0 Sread spectrum module is powered. - * 0b1..PLL0 Sread spectrum module is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) -/*! @} */ - -/*! @name PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU) -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U) -/*! PDRUNCFGSET0 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. - */ -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK) -/*! @} */ - -/*! @name PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ - -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU) -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U) -/*! PDRUNCFGCLR0 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. - */ -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK) -/*! @} */ - -/*! @name SRAMCTRL - All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ -/*! @{ */ - -#define PMC_SRAMCTRL_SMB_MASK (0x3U) -#define PMC_SRAMCTRL_SMB_SHIFT (0U) -/*! SMB - Source Biasing voltage. - * 0b00..Low leakage. - * 0b01..Medium leakage. - * 0b10..Highest leakage. - * 0b11..Disable. - */ -#define PMC_SRAMCTRL_SMB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_SMB_SHIFT)) & PMC_SRAMCTRL_SMB_MASK) - -#define PMC_SRAMCTRL_RM_MASK (0x1CU) -#define PMC_SRAMCTRL_RM_SHIFT (2U) -/*! RM - Read Margin control settings. - */ -#define PMC_SRAMCTRL_RM(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_RM_SHIFT)) & PMC_SRAMCTRL_RM_MASK) - -#define PMC_SRAMCTRL_WM_MASK (0xE0U) -#define PMC_SRAMCTRL_WM_SHIFT (5U) -/*! WM - Write Margin control settings. - */ -#define PMC_SRAMCTRL_WM(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WM_SHIFT)) & PMC_SRAMCTRL_WM_MASK) - -#define PMC_SRAMCTRL_WRME_MASK (0x100U) -#define PMC_SRAMCTRL_WRME_SHIFT (8U) -/*! WRME - Write read margin enable. - */ -#define PMC_SRAMCTRL_WRME(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WRME_SHIFT)) & PMC_SRAMCTRL_WRME_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PMC_Register_Masks */ - - -/* PMC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PMC base address */ - #define PMC_BASE (0x50020000u) - /** Peripheral PMC base address */ - #define PMC_BASE_NS (0x40020000u) - /** Peripheral PMC base pointer */ - #define PMC ((PMC_Type *)PMC_BASE) - /** Peripheral PMC base pointer */ - #define PMC_NS ((PMC_Type *)PMC_BASE_NS) - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS { PMC_BASE } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS { PMC } - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS_NS { PMC_BASE_NS } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS_NS { PMC_NS } -#else - /** Peripheral PMC base address */ - #define PMC_BASE (0x40020000u) - /** Peripheral PMC base pointer */ - #define PMC ((PMC_Type *)PMC_BASE) - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS { PMC_BASE } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS { PMC } -#endif - -/*! - * @} - */ /* end of group PMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- POWERQUAD Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup POWERQUAD_Peripheral_Access_Layer POWERQUAD Peripheral Access Layer - * @{ - */ - -/** POWERQUAD - Register Layout Typedef */ -typedef struct { - __IO uint32_t OUTBASE; /**< Base address register for output region, offset: 0x0 */ - __IO uint32_t OUTFORMAT; /**< Output format, offset: 0x4 */ - __IO uint32_t TMPBASE; /**< Base address register for temp region, offset: 0x8 */ - __IO uint32_t TMPFORMAT; /**< Temp format, offset: 0xC */ - __IO uint32_t INABASE; /**< Base address register for input A region, offset: 0x10 */ - __IO uint32_t INAFORMAT; /**< Input A format, offset: 0x14 */ - __IO uint32_t INBBASE; /**< Base address register for input B region, offset: 0x18 */ - __IO uint32_t INBFORMAT; /**< Input B format, offset: 0x1C */ - uint8_t RESERVED_0[224]; - __IO uint32_t CONTROL; /**< PowerQuad Control register, offset: 0x100 */ - __IO uint32_t LENGTH; /**< Length register, offset: 0x104 */ - __IO uint32_t CPPRE; /**< Pre-scale register, offset: 0x108 */ - __IO uint32_t MISC; /**< Misc register, offset: 0x10C */ - __IO uint32_t CURSORY; /**< Cursory register, offset: 0x110 */ - uint8_t RESERVED_1[108]; - __IO uint32_t CORDIC_X; /**< Cordic input X register, offset: 0x180 */ - __IO uint32_t CORDIC_Y; /**< Cordic input Y register, offset: 0x184 */ - __IO uint32_t CORDIC_Z; /**< Cordic input Z register, offset: 0x188 */ - __IO uint32_t ERRSTAT; /**< Read/Write register where error statuses are captured (sticky), offset: 0x18C */ - __IO uint32_t INTREN; /**< INTERRUPT enable register, offset: 0x190 */ - __IO uint32_t EVENTEN; /**< Event Enable register, offset: 0x194 */ - __IO uint32_t INTRSTAT; /**< INTERRUPT STATUS register, offset: 0x198 */ - uint8_t RESERVED_2[100]; - __IO uint32_t GPREG[16]; /**< General purpose register bank N., array offset: 0x200, array step: 0x4 */ - __IO uint32_t COMPREG[8]; /**< Compute register bank, array offset: 0x240, array step: 0x4 */ -} POWERQUAD_Type; - -/* ---------------------------------------------------------------------------- - -- POWERQUAD Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup POWERQUAD_Register_Masks POWERQUAD Register Masks - * @{ - */ - -/*! @name OUTBASE - Base address register for output region */ -/*! @{ */ - -#define POWERQUAD_OUTBASE_OUTBASE_MASK (0xFFFFFFFFU) -#define POWERQUAD_OUTBASE_OUTBASE_SHIFT (0U) -/*! outbase - Base address register for the output region - */ -#define POWERQUAD_OUTBASE_OUTBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK) -/*! @} */ - -/*! @name OUTFORMAT - Output format */ -/*! @{ */ - -#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK (0x3U) -#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT (0U) -/*! out_formatint - Output Internal format (00: q15; 01:q31; 10:float) - */ -#define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK) - -#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK (0x30U) -#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT (4U) -/*! out_formatext - Output External format (00: q15; 01:q31; 10:float) - */ -#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK) - -#define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK (0xFF00U) -#define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT (8U) -/*! out_scaler - Output Scaler value (for scaled 'q31' formats) - */ -#define POWERQUAD_OUTFORMAT_OUT_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK) -/*! @} */ - -/*! @name TMPBASE - Base address register for temp region */ -/*! @{ */ - -#define POWERQUAD_TMPBASE_TMPBASE_MASK (0xFFFFFFFFU) -#define POWERQUAD_TMPBASE_TMPBASE_SHIFT (0U) -/*! tmpbase - Base address register for the temporary region - */ -#define POWERQUAD_TMPBASE_TMPBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK) -/*! @} */ - -/*! @name TMPFORMAT - Temp format */ -/*! @{ */ - -#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK (0x3U) -#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT (0U) -/*! tmp_formatint - Temp Internal format (00: q15; 01:q31; 10:float) - */ -#define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK) - -#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK (0x30U) -#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT (4U) -/*! tmp_formatext - Temp External format (00: q15; 01:q31; 10:float) - */ -#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK) - -#define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK (0xFF00U) -#define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT (8U) -/*! tmp_scaler - Temp Scaler value (for scaled 'q31' formats) - */ -#define POWERQUAD_TMPFORMAT_TMP_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK) -/*! @} */ - -/*! @name INABASE - Base address register for input A region */ -/*! @{ */ - -#define POWERQUAD_INABASE_INABASE_MASK (0xFFFFFFFFU) -#define POWERQUAD_INABASE_INABASE_SHIFT (0U) -/*! inabase - Base address register for the input A region - */ -#define POWERQUAD_INABASE_INABASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK) -/*! @} */ - -/*! @name INAFORMAT - Input A format */ -/*! @{ */ - -#define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK (0x3U) -#define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT (0U) -/*! ina_formatint - Input A Internal format (00: q15; 01:q31; 10:float) - */ -#define POWERQUAD_INAFORMAT_INA_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK) - -#define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK (0x30U) -#define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT (4U) -/*! ina_formatext - Input A External format (00: q15; 01:q31; 10:float) - */ -#define POWERQUAD_INAFORMAT_INA_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK) - -#define POWERQUAD_INAFORMAT_INA_SCALER_MASK (0xFF00U) -#define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT (8U) -/*! ina_scaler - Input A Scaler value (for scaled 'q31' formats) - */ -#define POWERQUAD_INAFORMAT_INA_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK) -/*! @} */ - -/*! @name INBBASE - Base address register for input B region */ -/*! @{ */ - -#define POWERQUAD_INBBASE_INBBASE_MASK (0xFFFFFFFFU) -#define POWERQUAD_INBBASE_INBBASE_SHIFT (0U) -/*! inbbase - Base address register for the input B region - */ -#define POWERQUAD_INBBASE_INBBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK) -/*! @} */ - -/*! @name INBFORMAT - Input B format */ -/*! @{ */ - -#define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK (0x3U) -#define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT (0U) -/*! inb_formatint - Input B Internal format (00: q15; 01:q31; 10:float) - */ -#define POWERQUAD_INBFORMAT_INB_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK) - -#define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK (0x30U) -#define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT (4U) -/*! inb_formatext - Input B External format (00: q15; 01:q31; 10:float) - */ -#define POWERQUAD_INBFORMAT_INB_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK) - -#define POWERQUAD_INBFORMAT_INB_SCALER_MASK (0xFF00U) -#define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT (8U) -/*! inb_scaler - Input B Scaler value (for scaled 'q31' formats) - */ -#define POWERQUAD_INBFORMAT_INB_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK) -/*! @} */ - -/*! @name CONTROL - PowerQuad Control register */ -/*! @{ */ - -#define POWERQUAD_CONTROL_DECODE_OPCODE_MASK (0xFU) -#define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT (0U) -/*! decode_opcode - opcode specific to decode_machine - */ -#define POWERQUAD_CONTROL_DECODE_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK) - -#define POWERQUAD_CONTROL_DECODE_MACHINE_MASK (0xF0U) -#define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT (4U) -/*! decode_machine - 0 : Coprocessor , 1 : matrix , 2 : fft , 3 : fir , 4 : stat , 5 : cordic , 6 -15 : NA - */ -#define POWERQUAD_CONTROL_DECODE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK) - -#define POWERQUAD_CONTROL_INST_BUSY_MASK (0x80000000U) -#define POWERQUAD_CONTROL_INST_BUSY_SHIFT (31U) -/*! inst_busy - Instruction busy signal when high indicates processing is on - */ -#define POWERQUAD_CONTROL_INST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK) -/*! @} */ - -/*! @name LENGTH - Length register */ -/*! @{ */ - -#define POWERQUAD_LENGTH_INST_LENGTH_MASK (0xFFFFFFFFU) -#define POWERQUAD_LENGTH_INST_LENGTH_SHIFT (0U) -/*! inst_length - Length register. When FIR : fir_xlength = inst_length[15:0] , fir_tlength = - * inst_len[31:16]. When MTX : rows_a = inst_length[4:0] , cols_a = inst_length[12:8] , cols_b = - * inst_length[20:16] - */ -#define POWERQUAD_LENGTH_INST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK) -/*! @} */ - -/*! @name CPPRE - Pre-scale register */ -/*! @{ */ - -#define POWERQUAD_CPPRE_CPPRE_IN_MASK (0xFFU) -#define POWERQUAD_CPPRE_CPPRE_IN_SHIFT (0U) -/*! cppre_in - co-processor scaling of input - */ -#define POWERQUAD_CPPRE_CPPRE_IN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK) - -#define POWERQUAD_CPPRE_CPPRE_OUT_MASK (0xFF00U) -#define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT (8U) -/*! cppre_out - co-processor fixed point output - */ -#define POWERQUAD_CPPRE_CPPRE_OUT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK) - -#define POWERQUAD_CPPRE_CPPRE_SAT_MASK (0x10000U) -#define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT (16U) -/*! cppre_sat - 1 : forces sub-32 bit saturation - */ -#define POWERQUAD_CPPRE_CPPRE_SAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK) - -#define POWERQUAD_CPPRE_CPPRE_SAT8_MASK (0x20000U) -#define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT (17U) -/*! cppre_sat8 - 0 = 8bits, 1 = 16bits - */ -#define POWERQUAD_CPPRE_CPPRE_SAT8(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK) -/*! @} */ - -/*! @name MISC - Misc register */ -/*! @{ */ - -#define POWERQUAD_MISC_INST_MISC_MASK (0xFFFFFFFFU) -#define POWERQUAD_MISC_INST_MISC_SHIFT (0U) -/*! inst_misc - Misc register. For Matrix : Used for scale factor - */ -#define POWERQUAD_MISC_INST_MISC(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK) -/*! @} */ - -/*! @name CURSORY - Cursory register */ -/*! @{ */ - -#define POWERQUAD_CURSORY_CURSORY_MASK (0x1U) -#define POWERQUAD_CURSORY_CURSORY_SHIFT (0U) -/*! cursory - 1 : Enable cursory mode - */ -#define POWERQUAD_CURSORY_CURSORY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK) -/*! @} */ - -/*! @name CORDIC_X - Cordic input X register */ -/*! @{ */ - -#define POWERQUAD_CORDIC_X_CORDIC_X_MASK (0xFFFFFFFFU) -#define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT (0U) -/*! cordic_x - Cordic input x - */ -#define POWERQUAD_CORDIC_X_CORDIC_X(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK) -/*! @} */ - -/*! @name CORDIC_Y - Cordic input Y register */ -/*! @{ */ - -#define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK (0xFFFFFFFFU) -#define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT (0U) -/*! cordic_y - Cordic input y - */ -#define POWERQUAD_CORDIC_Y_CORDIC_Y(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK) -/*! @} */ - -/*! @name CORDIC_Z - Cordic input Z register */ -/*! @{ */ - -#define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK (0xFFFFFFFFU) -#define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT (0U) -/*! cordic_z - Cordic input z - */ -#define POWERQUAD_CORDIC_Z_CORDIC_Z(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK) -/*! @} */ - -/*! @name ERRSTAT - Read/Write register where error statuses are captured (sticky) */ -/*! @{ */ - -#define POWERQUAD_ERRSTAT_OVERFLOW_MASK (0x1U) -#define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT (0U) -/*! OVERFLOW - overflow - */ -#define POWERQUAD_ERRSTAT_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK) - -#define POWERQUAD_ERRSTAT_NAN_MASK (0x2U) -#define POWERQUAD_ERRSTAT_NAN_SHIFT (1U) -/*! NAN - nan - */ -#define POWERQUAD_ERRSTAT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK) - -#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK (0x4U) -#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT (2U) -/*! FIXEDOVERFLOW - fixed_pt_overflow - */ -#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK) - -#define POWERQUAD_ERRSTAT_UNDERFLOW_MASK (0x8U) -#define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT (3U) -/*! UNDERFLOW - underflow - */ -#define POWERQUAD_ERRSTAT_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK) - -#define POWERQUAD_ERRSTAT_BUSERROR_MASK (0x10U) -#define POWERQUAD_ERRSTAT_BUSERROR_SHIFT (4U) -/*! BUSERROR - bus_error - */ -#define POWERQUAD_ERRSTAT_BUSERROR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK) -/*! @} */ - -/*! @name INTREN - INTERRUPT enable register */ -/*! @{ */ - -#define POWERQUAD_INTREN_INTR_OFLOW_MASK (0x1U) -#define POWERQUAD_INTREN_INTR_OFLOW_SHIFT (0U) -/*! intr_oflow - 1 : Enable interrupt on Floating point overflow - */ -#define POWERQUAD_INTREN_INTR_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK) - -#define POWERQUAD_INTREN_INTR_NAN_MASK (0x2U) -#define POWERQUAD_INTREN_INTR_NAN_SHIFT (1U) -/*! intr_nan - 1 : Enable interrupt on Floating point NaN - */ -#define POWERQUAD_INTREN_INTR_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK) - -#define POWERQUAD_INTREN_INTR_FIXED_MASK (0x4U) -#define POWERQUAD_INTREN_INTR_FIXED_SHIFT (2U) -/*! intr_fixed - 1: Enable interrupt on Fixed point Overflow - */ -#define POWERQUAD_INTREN_INTR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK) - -#define POWERQUAD_INTREN_INTR_UFLOW_MASK (0x8U) -#define POWERQUAD_INTREN_INTR_UFLOW_SHIFT (3U) -/*! intr_uflow - 1 : Enable interrupt on Subnormal truncation - */ -#define POWERQUAD_INTREN_INTR_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK) - -#define POWERQUAD_INTREN_INTR_BERR_MASK (0x10U) -#define POWERQUAD_INTREN_INTR_BERR_SHIFT (4U) -/*! intr_berr - 1: Enable interrupt on AHBM Buss Error - */ -#define POWERQUAD_INTREN_INTR_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK) - -#define POWERQUAD_INTREN_INTR_COMP_MASK (0x80U) -#define POWERQUAD_INTREN_INTR_COMP_SHIFT (7U) -/*! intr_comp - 1: Enable interrupt on instruction completion - */ -#define POWERQUAD_INTREN_INTR_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK) -/*! @} */ - -/*! @name EVENTEN - Event Enable register */ -/*! @{ */ - -#define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK (0x1U) -#define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT (0U) -/*! event_oflow - 1 : Enable event trigger on Floating point overflow - */ -#define POWERQUAD_EVENTEN_EVENT_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK) - -#define POWERQUAD_EVENTEN_EVENT_NAN_MASK (0x2U) -#define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT (1U) -/*! event_nan - 1 : Enable event trigger on Floating point NaN - */ -#define POWERQUAD_EVENTEN_EVENT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK) - -#define POWERQUAD_EVENTEN_EVENT_FIXED_MASK (0x4U) -#define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT (2U) -/*! event_fixed - 1: Enable event trigger on Fixed point Overflow - */ -#define POWERQUAD_EVENTEN_EVENT_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK) - -#define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK (0x8U) -#define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT (3U) -/*! event_uflow - 1 : Enable event trigger on Subnormal truncation - */ -#define POWERQUAD_EVENTEN_EVENT_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK) - -#define POWERQUAD_EVENTEN_EVENT_BERR_MASK (0x10U) -#define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT (4U) -/*! event_berr - 1: Enable event trigger on AHBM Buss Error - */ -#define POWERQUAD_EVENTEN_EVENT_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK) - -#define POWERQUAD_EVENTEN_EVENT_COMP_MASK (0x80U) -#define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT (7U) -/*! event_comp - 1: Enable event trigger on instruction completion - */ -#define POWERQUAD_EVENTEN_EVENT_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK) -/*! @} */ - -/*! @name INTRSTAT - INTERRUPT STATUS register */ -/*! @{ */ - -#define POWERQUAD_INTRSTAT_INTR_STAT_MASK (0x1U) -#define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT (0U) -/*! intr_stat - Intr status ( 1 bit to indicate interrupt captured, 0 means no new interrupt), write any value will clear this bit - */ -#define POWERQUAD_INTRSTAT_INTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK) -/*! @} */ - -/*! @name GPREG - General purpose register bank N. */ -/*! @{ */ - -#define POWERQUAD_GPREG_GPREG_MASK (0xFFFFFFFFU) -#define POWERQUAD_GPREG_GPREG_SHIFT (0U) -/*! gpreg - General purpose register bank - */ -#define POWERQUAD_GPREG_GPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK) -/*! @} */ - -/* The count of POWERQUAD_GPREG */ -#define POWERQUAD_GPREG_COUNT (16U) - -/*! @name COMPREGS_COMPREG - Compute register bank */ -/*! @{ */ - -#define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK (0xFFFFFFFFU) -#define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U) -/*! compreg - Compute register bank - */ -#define POWERQUAD_COMPREGS_COMPREG_COMPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK) -/*! @} */ - -/* The count of POWERQUAD_COMPREGS_COMPREG */ -#define POWERQUAD_COMPREGS_COMPREG_COUNT (8U) - - -/*! - * @} - */ /* end of group POWERQUAD_Register_Masks */ - - -/* POWERQUAD - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral POWERQUAD base address */ - #define POWERQUAD_BASE (0x500A6000u) - /** Peripheral POWERQUAD base address */ - #define POWERQUAD_BASE_NS (0x400A6000u) - /** Peripheral POWERQUAD base pointer */ - #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) - /** Peripheral POWERQUAD base pointer */ - #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) - /** Array initializer of POWERQUAD peripheral base addresses */ - #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } - /** Array initializer of POWERQUAD peripheral base pointers */ - #define POWERQUAD_BASE_PTRS { POWERQUAD } - /** Array initializer of POWERQUAD peripheral base addresses */ - #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } - /** Array initializer of POWERQUAD peripheral base pointers */ - #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } -#else - /** Peripheral POWERQUAD base address */ - #define POWERQUAD_BASE (0x400A6000u) - /** Peripheral POWERQUAD base pointer */ - #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) - /** Array initializer of POWERQUAD peripheral base addresses */ - #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } - /** Array initializer of POWERQUAD peripheral base pointers */ - #define POWERQUAD_BASE_PTRS { POWERQUAD } -#endif - -/*! - * @} - */ /* end of group POWERQUAD_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PRINCE Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PRINCE_Peripheral_Access_Layer PRINCE Peripheral Access Layer - * @{ - */ - -/** PRINCE - Register Layout Typedef */ -typedef struct { - __IO uint32_t ENC_ENABLE; /**< Encryption Enable register, offset: 0x0 */ - __O uint32_t MASK_LSB; /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */ - __O uint32_t MASK_MSB; /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */ - __IO uint32_t LOCK; /**< Lock register, offset: 0xC */ - __O uint32_t IV_LSB0; /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */ - __O uint32_t IV_MSB0; /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */ - __IO uint32_t BASE_ADDR0; /**< Base Address for region 0 register, offset: 0x18 */ - __IO uint32_t SR_ENABLE0; /**< Sub-Region Enable register for region 0, offset: 0x1C */ - __O uint32_t IV_LSB1; /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */ - __O uint32_t IV_MSB1; /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */ - __IO uint32_t BASE_ADDR1; /**< Base Address for region 1 register, offset: 0x28 */ - __IO uint32_t SR_ENABLE1; /**< Sub-Region Enable register for region 1, offset: 0x2C */ - __O uint32_t IV_LSB2; /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */ - __O uint32_t IV_MSB2; /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */ - __IO uint32_t BASE_ADDR2; /**< Base Address for region 2 register, offset: 0x38 */ - __IO uint32_t SR_ENABLE2; /**< Sub-Region Enable register for region 2, offset: 0x3C */ -} PRINCE_Type; - -/* ---------------------------------------------------------------------------- - -- PRINCE Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PRINCE_Register_Masks PRINCE Register Masks - * @{ - */ - -/*! @name ENC_ENABLE - Encryption Enable register */ -/*! @{ */ - -#define PRINCE_ENC_ENABLE_EN_MASK (0x1U) -#define PRINCE_ENC_ENABLE_EN_SHIFT (0U) -/*! EN - Encryption Enable. - * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled. - * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled. - */ -#define PRINCE_ENC_ENABLE_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK) -/*! @} */ - -/*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */ -/*! @{ */ - -#define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU) -#define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U) -/*! MASKVAL - Value of the 32 Least Significant Bits of the 64-bit data mask. - */ -#define PRINCE_MASK_LSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK) -/*! @} */ - -/*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */ -/*! @{ */ - -#define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU) -#define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U) -/*! MASKVAL - Value of the 32 Most Significant Bits of the 64-bit data mask. - */ -#define PRINCE_MASK_MSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK) -/*! @} */ - -/*! @name LOCK - Lock register */ -/*! @{ */ - -#define PRINCE_LOCK_LOCKREG0_MASK (0x1U) -#define PRINCE_LOCK_LOCKREG0_SHIFT (0U) -/*! LOCKREG0 - Lock Region 0 registers. - * 0b0..Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. - * 0b1..Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. - */ -#define PRINCE_LOCK_LOCKREG0(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK) - -#define PRINCE_LOCK_LOCKREG1_MASK (0x2U) -#define PRINCE_LOCK_LOCKREG1_SHIFT (1U) -/*! LOCKREG1 - Lock Region 1 registers. - * 0b0..Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. - * 0b1..Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. - */ -#define PRINCE_LOCK_LOCKREG1(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK) - -#define PRINCE_LOCK_LOCKREG2_MASK (0x4U) -#define PRINCE_LOCK_LOCKREG2_SHIFT (2U) -/*! LOCKREG2 - Lock Region 2 registers. - * 0b0..Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. - * 0b1..Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. - */ -#define PRINCE_LOCK_LOCKREG2(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK) - -#define PRINCE_LOCK_LOCKMASK_MASK (0x100U) -#define PRINCE_LOCK_LOCKMASK_SHIFT (8U) -/*! LOCKMASK - Lock the Mask registers. - * 0b0..Disabled. MASK_LSB, and MASK_MSB are writable.. - * 0b1..Enabled. MASK_LSB, and MASK_MSB are not writable.. - */ -#define PRINCE_LOCK_LOCKMASK(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK) -/*! @} */ - -/*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB0_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_LSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB0_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_MSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR0 - Base Address for region 0 register */ -/*! @{ */ - -#define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U) -/*! ADDR_FIXED - Fixed portion of the base address of region 0. - */ -#define PRINCE_BASE_ADDR0_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK) - -#define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U) -/*! ADDR_PRG - Programmable portion of the base address of region 0. - */ -#define PRINCE_BASE_ADDR0_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */ -/*! @{ */ - -#define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE0_EN_SHIFT (0U) -/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0. - */ -#define PRINCE_SR_ENABLE0_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK) -/*! @} */ - -/*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB1_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_LSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB1_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_MSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR1 - Base Address for region 1 register */ -/*! @{ */ - -#define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U) -/*! ADDR_FIXED - Fixed portion of the base address of region 1. - */ -#define PRINCE_BASE_ADDR1_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK) - -#define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U) -/*! ADDR_PRG - Programmable portion of the base address of region 1. - */ -#define PRINCE_BASE_ADDR1_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */ -/*! @{ */ - -#define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE1_EN_SHIFT (0U) -/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1. - */ -#define PRINCE_SR_ENABLE1_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK) -/*! @} */ - -/*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB2_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_LSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */ -/*! @{ */ - -#define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB2_IVVAL_SHIFT (0U) -/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - */ -#define PRINCE_IV_MSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR2 - Base Address for region 2 register */ -/*! @{ */ - -#define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U) -/*! ADDR_FIXED - Fixed portion of the base address of region 2. - */ -#define PRINCE_BASE_ADDR2_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK) - -#define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U) -/*! ADDR_PRG - Programmable portion of the base address of region 2. - */ -#define PRINCE_BASE_ADDR2_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */ -/*! @{ */ - -#define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE2_EN_SHIFT (0U) -/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2. - */ -#define PRINCE_SR_ENABLE2_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PRINCE_Register_Masks */ - - -/* PRINCE - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PRINCE base address */ - #define PRINCE_BASE (0x50035000u) - /** Peripheral PRINCE base address */ - #define PRINCE_BASE_NS (0x40035000u) - /** Peripheral PRINCE base pointer */ - #define PRINCE ((PRINCE_Type *)PRINCE_BASE) - /** Peripheral PRINCE base pointer */ - #define PRINCE_NS ((PRINCE_Type *)PRINCE_BASE_NS) - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS { PRINCE_BASE } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS { PRINCE } - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS_NS { PRINCE_BASE_NS } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS_NS { PRINCE_NS } -#else - /** Peripheral PRINCE base address */ - #define PRINCE_BASE (0x40035000u) - /** Peripheral PRINCE base pointer */ - #define PRINCE ((PRINCE_Type *)PRINCE_BASE) - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS { PRINCE_BASE } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS { PRINCE } -#endif - -/*! - * @} - */ /* end of group PRINCE_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PUF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer - * @{ - */ - -/** PUF - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< PUF Control register, offset: 0x0 */ - __IO uint32_t KEYINDEX; /**< PUF Key Index register, offset: 0x4 */ - __IO uint32_t KEYSIZE; /**< PUF Key Size register, offset: 0x8 */ - uint8_t RESERVED_0[20]; - __I uint32_t STAT; /**< PUF Status register, offset: 0x20 */ - uint8_t RESERVED_1[4]; - __I uint32_t ALLOW; /**< PUF Allow register, offset: 0x28 */ - uint8_t RESERVED_2[20]; - __O uint32_t KEYINPUT; /**< PUF Key Input register, offset: 0x40 */ - __O uint32_t CODEINPUT; /**< PUF Code Input register, offset: 0x44 */ - __I uint32_t CODEOUTPUT; /**< PUF Code Output register, offset: 0x48 */ - uint8_t RESERVED_3[20]; - __I uint32_t KEYOUTINDEX; /**< PUF Key Output Index register, offset: 0x60 */ - __I uint32_t KEYOUTPUT; /**< PUF Key Output register, offset: 0x64 */ - uint8_t RESERVED_4[116]; - __IO uint32_t IFSTAT; /**< PUF Interface Status and clear register, offset: 0xDC */ - uint8_t RESERVED_5[28]; - __I uint32_t VERSION; /**< PUF version register., offset: 0xFC */ - __IO uint32_t INTEN; /**< PUF Interrupt Enable, offset: 0x100 */ - __IO uint32_t INTSTAT; /**< PUF interrupt status, offset: 0x104 */ - __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */ - __IO uint32_t CFG; /**< PUF config register for block bits, offset: 0x10C */ - uint8_t RESERVED_6[240]; - __IO uint32_t KEYLOCK; /**< Only reset in case of full IC reset, offset: 0x200 */ - __IO uint32_t KEYENABLE; /**< , offset: 0x204 */ - __O uint32_t KEYRESET; /**< Reinitialize Keys shift registers counters, offset: 0x208 */ - __IO uint32_t IDXBLK_L; /**< , offset: 0x20C */ - __IO uint32_t IDXBLK_H_DP; /**< , offset: 0x210 */ - __O uint32_t KEYMASK[4]; /**< Only reset in case of full IC reset, array offset: 0x214, array step: 0x4 */ - uint8_t RESERVED_7[48]; - __IO uint32_t IDXBLK_H; /**< , offset: 0x254 */ - __IO uint32_t IDXBLK_L_DP; /**< , offset: 0x258 */ - __I uint32_t SHIFT_STATUS; /**< , offset: 0x25C */ -} PUF_Type; - -/* ---------------------------------------------------------------------------- - -- PUF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_Register_Masks PUF Register Masks - * @{ - */ - -/*! @name CTRL - PUF Control register */ -/*! @{ */ - -#define PUF_CTRL_ZEROIZE_MASK (0x1U) -#define PUF_CTRL_ZEROIZE_SHIFT (0U) -/*! zeroize - Begin Zeroize operation for PUF and go to Error state - */ -#define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK) - -#define PUF_CTRL_ENROLL_MASK (0x2U) -#define PUF_CTRL_ENROLL_SHIFT (1U) -/*! enroll - Begin Enroll operation - */ -#define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK) - -#define PUF_CTRL_START_MASK (0x4U) -#define PUF_CTRL_START_SHIFT (2U) -/*! start - Begin Start operation - */ -#define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK) - -#define PUF_CTRL_GENERATEKEY_MASK (0x8U) -#define PUF_CTRL_GENERATEKEY_SHIFT (3U) -/*! GENERATEKEY - Begin Set Intrinsic Key operation - */ -#define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK) - -#define PUF_CTRL_SETKEY_MASK (0x10U) -#define PUF_CTRL_SETKEY_SHIFT (4U) -/*! SETKEY - Begin Set User Key operation - */ -#define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK) - -#define PUF_CTRL_GETKEY_MASK (0x40U) -#define PUF_CTRL_GETKEY_SHIFT (6U) -/*! GETKEY - Begin Get Key operation - */ -#define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK) -/*! @} */ - -/*! @name KEYINDEX - PUF Key Index register */ -/*! @{ */ - -#define PUF_KEYINDEX_KEYIDX_MASK (0xFU) -#define PUF_KEYINDEX_KEYIDX_SHIFT (0U) -/*! KEYIDX - Key index for Set Key operations - */ -#define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK) -/*! @} */ - -/*! @name KEYSIZE - PUF Key Size register */ -/*! @{ */ - -#define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU) -#define PUF_KEYSIZE_KEYSIZE_SHIFT (0U) -/*! KEYSIZE - Key size for Set Key operations - */ -#define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK) -/*! @} */ - -/*! @name STAT - PUF Status register */ -/*! @{ */ - -#define PUF_STAT_BUSY_MASK (0x1U) -#define PUF_STAT_BUSY_SHIFT (0U) -/*! busy - Indicates that operation is in progress - */ -#define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK) - -#define PUF_STAT_SUCCESS_MASK (0x2U) -#define PUF_STAT_SUCCESS_SHIFT (1U) -/*! SUCCESS - Last operation was successful - */ -#define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK) - -#define PUF_STAT_ERROR_MASK (0x4U) -#define PUF_STAT_ERROR_SHIFT (2U) -/*! error - PUF is in the Error state and no operations can be performed - */ -#define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK) - -#define PUF_STAT_KEYINREQ_MASK (0x10U) -#define PUF_STAT_KEYINREQ_SHIFT (4U) -/*! KEYINREQ - Request for next part of key - */ -#define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK) - -#define PUF_STAT_KEYOUTAVAIL_MASK (0x20U) -#define PUF_STAT_KEYOUTAVAIL_SHIFT (5U) -/*! KEYOUTAVAIL - Next part of key is available - */ -#define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK) - -#define PUF_STAT_CODEINREQ_MASK (0x40U) -#define PUF_STAT_CODEINREQ_SHIFT (6U) -/*! CODEINREQ - Request for next part of AC/KC - */ -#define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK) - -#define PUF_STAT_CODEOUTAVAIL_MASK (0x80U) -#define PUF_STAT_CODEOUTAVAIL_SHIFT (7U) -/*! CODEOUTAVAIL - Next part of AC/KC is available - */ -#define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK) -/*! @} */ - -/*! @name ALLOW - PUF Allow register */ -/*! @{ */ - -#define PUF_ALLOW_ALLOWENROLL_MASK (0x1U) -#define PUF_ALLOW_ALLOWENROLL_SHIFT (0U) -/*! ALLOWENROLL - Enroll operation is allowed - */ -#define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK) - -#define PUF_ALLOW_ALLOWSTART_MASK (0x2U) -#define PUF_ALLOW_ALLOWSTART_SHIFT (1U) -/*! ALLOWSTART - Start operation is allowed - */ -#define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK) - -#define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U) -#define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U) -/*! ALLOWSETKEY - Set Key operations are allowed - */ -#define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK) - -#define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U) -#define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U) -/*! ALLOWGETKEY - Get Key operation is allowed - */ -#define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK) -/*! @} */ - -/*! @name KEYINPUT - PUF Key Input register */ -/*! @{ */ - -#define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU) -#define PUF_KEYINPUT_KEYIN_SHIFT (0U) -/*! KEYIN - Key input data - */ -#define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK) -/*! @} */ - -/*! @name CODEINPUT - PUF Code Input register */ -/*! @{ */ - -#define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU) -#define PUF_CODEINPUT_CODEIN_SHIFT (0U) -/*! CODEIN - AC/KC input data - */ -#define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK) -/*! @} */ - -/*! @name CODEOUTPUT - PUF Code Output register */ -/*! @{ */ - -#define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU) -#define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U) -/*! CODEOUT - AC/KC output data - */ -#define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK) -/*! @} */ - -/*! @name KEYOUTINDEX - PUF Key Output Index register */ -/*! @{ */ - -#define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFU) -#define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U) -/*! KEYOUTIDX - Key index for the key that is currently output via the Key Output register - */ -#define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK) -/*! @} */ - -/*! @name KEYOUTPUT - PUF Key Output register */ -/*! @{ */ - -#define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU) -#define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U) -/*! KEYOUT - Key output data - */ -#define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK) -/*! @} */ - -/*! @name IFSTAT - PUF Interface Status and clear register */ -/*! @{ */ - -#define PUF_IFSTAT_ERROR_MASK (0x1U) -#define PUF_IFSTAT_ERROR_SHIFT (0U) -/*! ERROR - Indicates that an APB error has occurred,Writing logic1 clears the if_error bit - */ -#define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK) -/*! @} */ - -/*! @name VERSION - PUF version register. */ -/*! @{ */ - -#define PUF_VERSION_VERSION_MASK (0xFFFFFFFFU) -#define PUF_VERSION_VERSION_SHIFT (0U) -/*! VERSION - Version of the PUF module. - */ -#define PUF_VERSION_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_VERSION_SHIFT)) & PUF_VERSION_VERSION_MASK) -/*! @} */ - -/*! @name INTEN - PUF Interrupt Enable */ -/*! @{ */ - -#define PUF_INTEN_READYEN_MASK (0x1U) -#define PUF_INTEN_READYEN_SHIFT (0U) -/*! READYEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK) - -#define PUF_INTEN_SUCCESEN_MASK (0x2U) -#define PUF_INTEN_SUCCESEN_SHIFT (1U) -/*! SUCCESEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_SUCCESEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK) - -#define PUF_INTEN_ERROREN_MASK (0x4U) -#define PUF_INTEN_ERROREN_SHIFT (2U) -/*! ERROREN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK) - -#define PUF_INTEN_KEYINREQEN_MASK (0x10U) -#define PUF_INTEN_KEYINREQEN_SHIFT (4U) -/*! KEYINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK) - -#define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U) -#define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U) -/*! KEYOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK) - -#define PUF_INTEN_CODEINREQEN_MASK (0x40U) -#define PUF_INTEN_CODEINREQEN_SHIFT (6U) -/*! CODEINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK) - -#define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U) -#define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U) -/*! CODEOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - */ -#define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK) -/*! @} */ - -/*! @name INTSTAT - PUF interrupt status */ -/*! @{ */ - -#define PUF_INTSTAT_READY_MASK (0x1U) -#define PUF_INTSTAT_READY_SHIFT (0U) -/*! READY - Triggers on falling edge of busy, write 1 to clear - */ -#define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK) - -#define PUF_INTSTAT_SUCCESS_MASK (0x2U) -#define PUF_INTSTAT_SUCCESS_SHIFT (1U) -/*! SUCCESS - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK) - -#define PUF_INTSTAT_ERROR_MASK (0x4U) -#define PUF_INTSTAT_ERROR_SHIFT (2U) -/*! ERROR - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK) - -#define PUF_INTSTAT_KEYINREQ_MASK (0x10U) -#define PUF_INTSTAT_KEYINREQ_SHIFT (4U) -/*! KEYINREQ - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK) - -#define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U) -#define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U) -/*! KEYOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK) - -#define PUF_INTSTAT_CODEINREQ_MASK (0x40U) -#define PUF_INTSTAT_CODEINREQ_SHIFT (6U) -/*! CODEINREQ - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK) - -#define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U) -#define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U) -/*! CODEOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears - */ -#define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK) -/*! @} */ - -/*! @name PWRCTRL - PUF RAM Power Control */ -/*! @{ */ - -#define PUF_PWRCTRL_RAMON_MASK (0x1U) -#define PUF_PWRCTRL_RAMON_SHIFT (0U) -/*! RAMON - Power on the PUF RAM. - */ -#define PUF_PWRCTRL_RAMON(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMON_SHIFT)) & PUF_PWRCTRL_RAMON_MASK) - -#define PUF_PWRCTRL_RAMSTAT_MASK (0x2U) -#define PUF_PWRCTRL_RAMSTAT_SHIFT (1U) -/*! RAMSTAT - PUF RAM status. - */ -#define PUF_PWRCTRL_RAMSTAT(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMSTAT_SHIFT)) & PUF_PWRCTRL_RAMSTAT_MASK) -/*! @} */ - -/*! @name CFG - PUF config register for block bits */ -/*! @{ */ - -#define PUF_CFG_BLOCKENROLL_SETKEY_MASK (0x1U) -#define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT (0U) -/*! BLOCKENROLL_SETKEY - Block enroll operation. Write 1 to set, cleared on reset. - */ -#define PUF_CFG_BLOCKENROLL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK) - -#define PUF_CFG_BLOCKKEYOUTPUT_MASK (0x2U) -#define PUF_CFG_BLOCKKEYOUTPUT_SHIFT (1U) -/*! BLOCKKEYOUTPUT - Block set key operation. Write 1 to set, cleared on reset. - */ -#define PUF_CFG_BLOCKKEYOUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK) -/*! @} */ - -/*! @name KEYLOCK - Only reset in case of full IC reset */ -/*! @{ */ - -#define PUF_KEYLOCK_KEY0_MASK (0x3U) -#define PUF_KEYLOCK_KEY0_SHIFT (0U) -/*! KEY0 - "10:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is allowed. 00, 01, - * 11:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is NOT allowed. Important Note : Once - * this field is written with a value different from '10', its value can no longer be modified - * until un Power On Reset occurs." - */ -#define PUF_KEYLOCK_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK) - -#define PUF_KEYLOCK_KEY1_MASK (0xCU) -#define PUF_KEYLOCK_KEY1_SHIFT (2U) -/*! KEY1 - "10:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is allowed. 00, 01, - * 11:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is NOT allowed. Important Note : Once - * this field is written with a value different from '10', its value can no longer be modified - * until un Power On Reset occurs." - */ -#define PUF_KEYLOCK_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK) - -#define PUF_KEYLOCK_KEY2_MASK (0x30U) -#define PUF_KEYLOCK_KEY2_SHIFT (4U) -/*! KEY2 - "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, - * 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once - * this field is written with a value different from '10', its value can no longer be modified - * until un Power On Reset occurs." - */ -#define PUF_KEYLOCK_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK) - -#define PUF_KEYLOCK_KEY3_MASK (0xC0U) -#define PUF_KEYLOCK_KEY3_SHIFT (6U) -/*! KEY3 - "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, - * 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once - * this field is written with a value different from '10', its value can no longer be modified - * until un Power On Reset occurs." - */ -#define PUF_KEYLOCK_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK) -/*! @} */ - -/*! @name KEYENABLE - */ -/*! @{ */ - -#define PUF_KEYENABLE_KEY0_MASK (0x3U) -#define PUF_KEYENABLE_KEY0_SHIFT (0U) -/*! KEY0 - "10: Data coming out from PUF Index 0 interface are shifted in KEY0 register. 00, 01, 11 - * : Data coming out from PUF Index 0 interface are NOT shifted in KEY0 register." - */ -#define PUF_KEYENABLE_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK) - -#define PUF_KEYENABLE_KEY1_MASK (0xCU) -#define PUF_KEYENABLE_KEY1_SHIFT (2U) -/*! KEY1 - "10: Data coming out from PUF Index 0 interface are shifted in KEY1 register. 00, 01, 11 - * : Data coming out from PUF Index 0 interface are NOT shifted in KEY1 register." - */ -#define PUF_KEYENABLE_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK) - -#define PUF_KEYENABLE_KEY2_MASK (0x30U) -#define PUF_KEYENABLE_KEY2_SHIFT (4U) -/*! KEY2 - "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 - * : Data coming out from PUF Index 0 interface are NOT shifted in KEY2 register." - */ -#define PUF_KEYENABLE_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK) - -#define PUF_KEYENABLE_KEY3_MASK (0xC0U) -#define PUF_KEYENABLE_KEY3_SHIFT (6U) -/*! KEY3 - "10: Data coming out from PUF Index 0 interface are shifted in KEY3 register. 00, 01, 11 - * : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." - */ -#define PUF_KEYENABLE_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK) -/*! @} */ - -/*! @name KEYRESET - Reinitialize Keys shift registers counters */ -/*! @{ */ - -#define PUF_KEYRESET_KEY0_MASK (0x3U) -#define PUF_KEYRESET_KEY0_SHIFT (0U) -/*! KEY0 - 10: Reset KEY0 shift register. Self clearing. Must be done before loading any new key. - */ -#define PUF_KEYRESET_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK) - -#define PUF_KEYRESET_KEY1_MASK (0xCU) -#define PUF_KEYRESET_KEY1_SHIFT (2U) -/*! KEY1 - 10: Reset KEY1 shift register. Self clearing. Must be done before loading any new key. - */ -#define PUF_KEYRESET_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK) - -#define PUF_KEYRESET_KEY2_MASK (0x30U) -#define PUF_KEYRESET_KEY2_SHIFT (4U) -/*! KEY2 - 10: Reset KEY2 shift register. Self clearing. Must be done before loading any new key. - */ -#define PUF_KEYRESET_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK) - -#define PUF_KEYRESET_KEY3_MASK (0xC0U) -#define PUF_KEYRESET_KEY3_SHIFT (6U) -/*! KEY3 - 10: Reset KEY3 shift register. Self clearing. Must be done before loading any new key. - */ -#define PUF_KEYRESET_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK) -/*! @} */ - -/*! @name IDXBLK_L - */ -/*! @{ */ - -#define PUF_IDXBLK_L_IDX1_MASK (0xCU) -#define PUF_IDXBLK_L_IDX1_SHIFT (2U) -/*! IDX1 - Use to block PUF index 1 - */ -#define PUF_IDXBLK_L_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX1_SHIFT)) & PUF_IDXBLK_L_IDX1_MASK) - -#define PUF_IDXBLK_L_IDX2_MASK (0x30U) -#define PUF_IDXBLK_L_IDX2_SHIFT (4U) -/*! IDX2 - Use to block PUF index 2 - */ -#define PUF_IDXBLK_L_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX2_SHIFT)) & PUF_IDXBLK_L_IDX2_MASK) - -#define PUF_IDXBLK_L_IDX3_MASK (0xC0U) -#define PUF_IDXBLK_L_IDX3_SHIFT (6U) -/*! IDX3 - Use to block PUF index 3 - */ -#define PUF_IDXBLK_L_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX3_SHIFT)) & PUF_IDXBLK_L_IDX3_MASK) - -#define PUF_IDXBLK_L_IDX4_MASK (0x300U) -#define PUF_IDXBLK_L_IDX4_SHIFT (8U) -/*! IDX4 - Use to block PUF index 4 - */ -#define PUF_IDXBLK_L_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX4_SHIFT)) & PUF_IDXBLK_L_IDX4_MASK) - -#define PUF_IDXBLK_L_IDX5_MASK (0xC00U) -#define PUF_IDXBLK_L_IDX5_SHIFT (10U) -/*! IDX5 - Use to block PUF index 5 - */ -#define PUF_IDXBLK_L_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX5_SHIFT)) & PUF_IDXBLK_L_IDX5_MASK) - -#define PUF_IDXBLK_L_IDX6_MASK (0x3000U) -#define PUF_IDXBLK_L_IDX6_SHIFT (12U) -/*! IDX6 - Use to block PUF index 6 - */ -#define PUF_IDXBLK_L_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX6_SHIFT)) & PUF_IDXBLK_L_IDX6_MASK) - -#define PUF_IDXBLK_L_IDX7_MASK (0xC000U) -#define PUF_IDXBLK_L_IDX7_SHIFT (14U) -/*! IDX7 - Use to block PUF index 7 - */ -#define PUF_IDXBLK_L_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX7_SHIFT)) & PUF_IDXBLK_L_IDX7_MASK) - -#define PUF_IDXBLK_L_LOCK_IDX_MASK (0xC0000000U) -#define PUF_IDXBLK_L_LOCK_IDX_SHIFT (30U) -/*! LOCK_IDX - Lock 0 to 7 PUF key indexes - */ -#define PUF_IDXBLK_L_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_LOCK_IDX_SHIFT)) & PUF_IDXBLK_L_LOCK_IDX_MASK) -/*! @} */ - -/*! @name IDXBLK_H_DP - */ -/*! @{ */ - -#define PUF_IDXBLK_H_DP_IDX8_MASK (0x3U) -#define PUF_IDXBLK_H_DP_IDX8_SHIFT (0U) -/*! IDX8 - Use to block PUF index 8 - */ -#define PUF_IDXBLK_H_DP_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX8_SHIFT)) & PUF_IDXBLK_H_DP_IDX8_MASK) - -#define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) -#define PUF_IDXBLK_H_DP_IDX9_SHIFT (2U) -/*! IDX9 - Use to block PUF index 9 - */ -#define PUF_IDXBLK_H_DP_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK) - -#define PUF_IDXBLK_H_DP_IDX10_MASK (0x30U) -#define PUF_IDXBLK_H_DP_IDX10_SHIFT (4U) -/*! IDX10 - Use to block PUF index 10 - */ -#define PUF_IDXBLK_H_DP_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX10_SHIFT)) & PUF_IDXBLK_H_DP_IDX10_MASK) - -#define PUF_IDXBLK_H_DP_IDX11_MASK (0xC0U) -#define PUF_IDXBLK_H_DP_IDX11_SHIFT (6U) -/*! IDX11 - Use to block PUF index 11 - */ -#define PUF_IDXBLK_H_DP_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX11_SHIFT)) & PUF_IDXBLK_H_DP_IDX11_MASK) - -#define PUF_IDXBLK_H_DP_IDX12_MASK (0x300U) -#define PUF_IDXBLK_H_DP_IDX12_SHIFT (8U) -/*! IDX12 - Use to block PUF index 12 - */ -#define PUF_IDXBLK_H_DP_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX12_SHIFT)) & PUF_IDXBLK_H_DP_IDX12_MASK) - -#define PUF_IDXBLK_H_DP_IDX13_MASK (0xC00U) -#define PUF_IDXBLK_H_DP_IDX13_SHIFT (10U) -/*! IDX13 - Use to block PUF index 13 - */ -#define PUF_IDXBLK_H_DP_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX13_SHIFT)) & PUF_IDXBLK_H_DP_IDX13_MASK) - -#define PUF_IDXBLK_H_DP_IDX14_MASK (0x3000U) -#define PUF_IDXBLK_H_DP_IDX14_SHIFT (12U) -/*! IDX14 - Use to block PUF index 14 - */ -#define PUF_IDXBLK_H_DP_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX14_SHIFT)) & PUF_IDXBLK_H_DP_IDX14_MASK) - -#define PUF_IDXBLK_H_DP_IDX15_MASK (0xC000U) -#define PUF_IDXBLK_H_DP_IDX15_SHIFT (14U) -/*! IDX15 - Use to block PUF index 15 - */ -#define PUF_IDXBLK_H_DP_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX15_SHIFT)) & PUF_IDXBLK_H_DP_IDX15_MASK) -/*! @} */ - -/*! @name KEYMASK - Only reset in case of full IC reset */ -/*! @{ */ - -#define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU) -#define PUF_KEYMASK_KEYMASK_SHIFT (0U) -#define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK) -/*! @} */ - -/* The count of PUF_KEYMASK */ -#define PUF_KEYMASK_COUNT (4U) - -/*! @name IDXBLK_H - */ -/*! @{ */ - -#define PUF_IDXBLK_H_IDX8_MASK (0x3U) -#define PUF_IDXBLK_H_IDX8_SHIFT (0U) -/*! IDX8 - Use to block PUF index 8 - */ -#define PUF_IDXBLK_H_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX8_SHIFT)) & PUF_IDXBLK_H_IDX8_MASK) - -#define PUF_IDXBLK_H_IDX9_MASK (0xCU) -#define PUF_IDXBLK_H_IDX9_SHIFT (2U) -/*! IDX9 - Use to block PUF index 9 - */ -#define PUF_IDXBLK_H_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX9_SHIFT)) & PUF_IDXBLK_H_IDX9_MASK) - -#define PUF_IDXBLK_H_IDX10_MASK (0x30U) -#define PUF_IDXBLK_H_IDX10_SHIFT (4U) -/*! IDX10 - Use to block PUF index 10 - */ -#define PUF_IDXBLK_H_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX10_SHIFT)) & PUF_IDXBLK_H_IDX10_MASK) - -#define PUF_IDXBLK_H_IDX11_MASK (0xC0U) -#define PUF_IDXBLK_H_IDX11_SHIFT (6U) -/*! IDX11 - Use to block PUF index 11 - */ -#define PUF_IDXBLK_H_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX11_SHIFT)) & PUF_IDXBLK_H_IDX11_MASK) - -#define PUF_IDXBLK_H_IDX12_MASK (0x300U) -#define PUF_IDXBLK_H_IDX12_SHIFT (8U) -/*! IDX12 - Use to block PUF index 12 - */ -#define PUF_IDXBLK_H_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX12_SHIFT)) & PUF_IDXBLK_H_IDX12_MASK) - -#define PUF_IDXBLK_H_IDX13_MASK (0xC00U) -#define PUF_IDXBLK_H_IDX13_SHIFT (10U) -/*! IDX13 - Use to block PUF index 13 - */ -#define PUF_IDXBLK_H_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX13_SHIFT)) & PUF_IDXBLK_H_IDX13_MASK) - -#define PUF_IDXBLK_H_IDX14_MASK (0x3000U) -#define PUF_IDXBLK_H_IDX14_SHIFT (12U) -/*! IDX14 - Use to block PUF index 14 - */ -#define PUF_IDXBLK_H_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX14_SHIFT)) & PUF_IDXBLK_H_IDX14_MASK) - -#define PUF_IDXBLK_H_IDX15_MASK (0xC000U) -#define PUF_IDXBLK_H_IDX15_SHIFT (14U) -/*! IDX15 - Use to block PUF index 15 - */ -#define PUF_IDXBLK_H_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX15_SHIFT)) & PUF_IDXBLK_H_IDX15_MASK) - -#define PUF_IDXBLK_H_LOCK_IDX_MASK (0xC0000000U) -#define PUF_IDXBLK_H_LOCK_IDX_SHIFT (30U) -/*! LOCK_IDX - Lock 8 to 15 PUF key indexes - */ -#define PUF_IDXBLK_H_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_LOCK_IDX_SHIFT)) & PUF_IDXBLK_H_LOCK_IDX_MASK) -/*! @} */ - -/*! @name IDXBLK_L_DP - */ -/*! @{ */ - -#define PUF_IDXBLK_L_DP_IDX1_MASK (0xCU) -#define PUF_IDXBLK_L_DP_IDX1_SHIFT (2U) -/*! IDX1 - Use to block PUF index 1 - */ -#define PUF_IDXBLK_L_DP_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX1_SHIFT)) & PUF_IDXBLK_L_DP_IDX1_MASK) - -#define PUF_IDXBLK_L_DP_IDX2_MASK (0x30U) -#define PUF_IDXBLK_L_DP_IDX2_SHIFT (4U) -/*! IDX2 - Use to block PUF index 2 - */ -#define PUF_IDXBLK_L_DP_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX2_SHIFT)) & PUF_IDXBLK_L_DP_IDX2_MASK) - -#define PUF_IDXBLK_L_DP_IDX3_MASK (0xC0U) -#define PUF_IDXBLK_L_DP_IDX3_SHIFT (6U) -/*! IDX3 - Use to block PUF index 3 - */ -#define PUF_IDXBLK_L_DP_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX3_SHIFT)) & PUF_IDXBLK_L_DP_IDX3_MASK) - -#define PUF_IDXBLK_L_DP_IDX4_MASK (0x300U) -#define PUF_IDXBLK_L_DP_IDX4_SHIFT (8U) -/*! IDX4 - Use to block PUF index 4 - */ -#define PUF_IDXBLK_L_DP_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX4_SHIFT)) & PUF_IDXBLK_L_DP_IDX4_MASK) - -#define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) -#define PUF_IDXBLK_L_DP_IDX5_SHIFT (10U) -/*! IDX5 - Use to block PUF index 5 - */ -#define PUF_IDXBLK_L_DP_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK) - -#define PUF_IDXBLK_L_DP_IDX6_MASK (0x3000U) -#define PUF_IDXBLK_L_DP_IDX6_SHIFT (12U) -/*! IDX6 - Use to block PUF index 6 - */ -#define PUF_IDXBLK_L_DP_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX6_SHIFT)) & PUF_IDXBLK_L_DP_IDX6_MASK) - -#define PUF_IDXBLK_L_DP_IDX7_MASK (0xC000U) -#define PUF_IDXBLK_L_DP_IDX7_SHIFT (14U) -/*! IDX7 - Use to block PUF index 7 - */ -#define PUF_IDXBLK_L_DP_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX7_SHIFT)) & PUF_IDXBLK_L_DP_IDX7_MASK) -/*! @} */ - -/*! @name SHIFT_STATUS - */ -/*! @{ */ - -#define PUF_SHIFT_STATUS_KEY0_MASK (0xFU) -#define PUF_SHIFT_STATUS_KEY0_SHIFT (0U) -/*! KEY0 - Index counter from key 0 shift register - */ -#define PUF_SHIFT_STATUS_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY0_SHIFT)) & PUF_SHIFT_STATUS_KEY0_MASK) - -#define PUF_SHIFT_STATUS_KEY1_MASK (0xF0U) -#define PUF_SHIFT_STATUS_KEY1_SHIFT (4U) -/*! KEY1 - Index counter from key 1 shift register - */ -#define PUF_SHIFT_STATUS_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY1_SHIFT)) & PUF_SHIFT_STATUS_KEY1_MASK) - -#define PUF_SHIFT_STATUS_KEY2_MASK (0xF00U) -#define PUF_SHIFT_STATUS_KEY2_SHIFT (8U) -/*! KEY2 - Index counter from key 2 shift register - */ -#define PUF_SHIFT_STATUS_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY2_SHIFT)) & PUF_SHIFT_STATUS_KEY2_MASK) - -#define PUF_SHIFT_STATUS_KEY3_MASK (0xF000U) -#define PUF_SHIFT_STATUS_KEY3_SHIFT (12U) -/*! KEY3 - Index counter from key 3 shift register - */ -#define PUF_SHIFT_STATUS_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY3_SHIFT)) & PUF_SHIFT_STATUS_KEY3_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PUF_Register_Masks */ - - -/* PUF - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PUF base address */ - #define PUF_BASE (0x5003B000u) - /** Peripheral PUF base address */ - #define PUF_BASE_NS (0x4003B000u) - /** Peripheral PUF base pointer */ - #define PUF ((PUF_Type *)PUF_BASE) - /** Peripheral PUF base pointer */ - #define PUF_NS ((PUF_Type *)PUF_BASE_NS) - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS { PUF_BASE } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS { PUF } - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS_NS { PUF_BASE_NS } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS_NS { PUF_NS } -#else - /** Peripheral PUF base address */ - #define PUF_BASE (0x4003B000u) - /** Peripheral PUF base pointer */ - #define PUF ((PUF_Type *)PUF_BASE) - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS { PUF_BASE } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS { PUF } -#endif -/** Interrupt vectors for the PUF peripheral type */ -#define PUF_IRQS { PUF_IRQn } - -/*! - * @} - */ /* end of group PUF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RNG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer - * @{ - */ - -/** RNG - Register Layout Typedef */ -typedef struct { - __I uint32_t RANDOM_NUMBER; /**< This register contains a random 32 bit number which is computed on demand, at each time it is read, offset: 0x0 */ - uint8_t RESERVED_0[4]; - __I uint32_t COUNTER_VAL; /**< , offset: 0x8 */ - __IO uint32_t COUNTER_CFG; /**< , offset: 0xC */ - __IO uint32_t ONLINE_TEST_CFG; /**< , offset: 0x10 */ - __I uint32_t ONLINE_TEST_VAL; /**< , offset: 0x14 */ - uint8_t RESERVED_1[4068]; - __I uint32_t MODULEID; /**< IP identifier, offset: 0xFFC */ -} RNG_Type; - -/* ---------------------------------------------------------------------------- - -- RNG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RNG_Register_Masks RNG Register Masks - * @{ - */ - -/*! @name RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read */ -/*! @{ */ - -#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK (0xFFFFFFFFU) -#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT (0U) -/*! RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read. - */ -#define RNG_RANDOM_NUMBER_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT)) & RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK) -/*! @} */ - -/*! @name COUNTER_VAL - */ -/*! @{ */ - -#define RNG_COUNTER_VAL_CLK_RATIO_MASK (0xFFU) -#define RNG_COUNTER_VAL_CLK_RATIO_SHIFT (0U) -/*! CLK_RATIO - Gives the ratio between the internal clocks frequencies and the register clock - * frequency for evaluation and certification purposes. - */ -#define RNG_COUNTER_VAL_CLK_RATIO(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_CLK_RATIO_SHIFT)) & RNG_COUNTER_VAL_CLK_RATIO_MASK) - -#define RNG_COUNTER_VAL_REFRESH_CNT_MASK (0x1F00U) -#define RNG_COUNTER_VAL_REFRESH_CNT_SHIFT (8U) -/*! REFRESH_CNT - Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER. - */ -#define RNG_COUNTER_VAL_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_REFRESH_CNT_SHIFT)) & RNG_COUNTER_VAL_REFRESH_CNT_MASK) -/*! @} */ - -/*! @name COUNTER_CFG - */ -/*! @{ */ - -#define RNG_COUNTER_CFG_MODE_MASK (0x3U) -#define RNG_COUNTER_CFG_MODE_SHIFT (0U) -/*! MODE - 00: disabled 01: update once. - */ -#define RNG_COUNTER_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_MODE_SHIFT)) & RNG_COUNTER_CFG_MODE_MASK) - -#define RNG_COUNTER_CFG_CLOCK_SEL_MASK (0x1CU) -#define RNG_COUNTER_CFG_CLOCK_SEL_SHIFT (2U) -/*! CLOCK_SEL - Selects the internal clock on which to compute statistics. - */ -#define RNG_COUNTER_CFG_CLOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_CLOCK_SEL_SHIFT)) & RNG_COUNTER_CFG_CLOCK_SEL_MASK) - -#define RNG_COUNTER_CFG_SHIFT4X_MASK (0xE0U) -#define RNG_COUNTER_CFG_SHIFT4X_SHIFT (5U) -/*! SHIFT4X - To be used to add precision to clock_ratio and determine 'entropy refill'. - */ -#define RNG_COUNTER_CFG_SHIFT4X(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_SHIFT4X_SHIFT)) & RNG_COUNTER_CFG_SHIFT4X_MASK) -/*! @} */ - -/*! @name ONLINE_TEST_CFG - */ -/*! @{ */ - -#define RNG_ONLINE_TEST_CFG_ACTIVATE_MASK (0x1U) -#define RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT (0U) -/*! ACTIVATE - 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER. - */ -#define RNG_ONLINE_TEST_CFG_ACTIVATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT)) & RNG_ONLINE_TEST_CFG_ACTIVATE_MASK) - -#define RNG_ONLINE_TEST_CFG_DATA_SEL_MASK (0x6U) -#define RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT (1U) -/*! DATA_SEL - Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one - * or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10: - * RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this - * field. - */ -#define RNG_ONLINE_TEST_CFG_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT)) & RNG_ONLINE_TEST_CFG_DATA_SEL_MASK) -/*! @} */ - -/*! @name ONLINE_TEST_VAL - */ -/*! @{ */ - -#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK (0xFU) -#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT (0U) -/*! LIVE_CHI_SQUARED - This value is updated as described in field 'activate'. - */ -#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK) - -#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK (0xF0U) -#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT (4U) -/*! MIN_CHI_SQUARED - This field is reset when 'activate'==0. - */ -#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) - -#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK (0xF00U) -#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT (8U) -/*! MAX_CHI_SQUARED - This field is reset when 'activate'==0. - */ -#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) -/*! @} */ - -/*! @name MODULEID - IP identifier */ -/*! @{ */ - -#define RNG_MODULEID_APERTURE_MASK (0xFFU) -#define RNG_MODULEID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture i. - */ -#define RNG_MODULEID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_APERTURE_SHIFT)) & RNG_MODULEID_APERTURE_MASK) - -#define RNG_MODULEID_MIN_REV_MASK (0xF00U) -#define RNG_MODULEID_MIN_REV_SHIFT (8U) -/*! MIN_REV - Minor revision i. - */ -#define RNG_MODULEID_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MIN_REV_SHIFT)) & RNG_MODULEID_MIN_REV_MASK) - -#define RNG_MODULEID_MAJ_REV_MASK (0xF000U) -#define RNG_MODULEID_MAJ_REV_SHIFT (12U) -/*! MAJ_REV - Major revision i. - */ -#define RNG_MODULEID_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MAJ_REV_SHIFT)) & RNG_MODULEID_MAJ_REV_MASK) - -#define RNG_MODULEID_ID_MASK (0xFFFF0000U) -#define RNG_MODULEID_ID_SHIFT (16U) -/*! ID - Identifier. - */ -#define RNG_MODULEID_ID(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_ID_SHIFT)) & RNG_MODULEID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group RNG_Register_Masks */ - - -/* RNG - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral RNG base address */ - #define RNG_BASE (0x5003A000u) - /** Peripheral RNG base address */ - #define RNG_BASE_NS (0x4003A000u) - /** Peripheral RNG base pointer */ - #define RNG ((RNG_Type *)RNG_BASE) - /** Peripheral RNG base pointer */ - #define RNG_NS ((RNG_Type *)RNG_BASE_NS) - /** Array initializer of RNG peripheral base addresses */ - #define RNG_BASE_ADDRS { RNG_BASE } - /** Array initializer of RNG peripheral base pointers */ - #define RNG_BASE_PTRS { RNG } - /** Array initializer of RNG peripheral base addresses */ - #define RNG_BASE_ADDRS_NS { RNG_BASE_NS } - /** Array initializer of RNG peripheral base pointers */ - #define RNG_BASE_PTRS_NS { RNG_NS } -#else - /** Peripheral RNG base address */ - #define RNG_BASE (0x4003A000u) - /** Peripheral RNG base pointer */ - #define RNG ((RNG_Type *)RNG_BASE) - /** Array initializer of RNG peripheral base addresses */ - #define RNG_BASE_ADDRS { RNG_BASE } - /** Array initializer of RNG peripheral base pointers */ - #define RNG_BASE_PTRS { RNG } -#endif - -/*! - * @} - */ /* end of group RNG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RTC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer - * @{ - */ - -/** RTC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ - __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ - __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ - __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ - __I uint32_t SUBSEC; /**< Sub-second counter register, offset: 0x10 */ - uint8_t RESERVED_0[44]; - __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */ -} RTC_Type; - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/*! @name CTRL - RTC control register */ -/*! @{ */ - -#define RTC_CTRL_SWRESET_MASK (0x1U) -#define RTC_CTRL_SWRESET_SHIFT (0U) -/*! SWRESET - Software reset control - * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. - * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value - * except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes - * to set any of the other bits within this register. Do not attempt to write to any bits of this register at - * the same time that the reset bit is being cleared. - */ -#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) - -#define RTC_CTRL_ALARM1HZ_MASK (0x4U) -#define RTC_CTRL_ALARM1HZ_SHIFT (2U) -/*! ALARM1HZ - RTC 1 Hz timer alarm flag status. - * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. - * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt - * request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. - */ -#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) - -#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) -#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) -/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status. - * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. - * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up - * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. - */ -#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) - -#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) -#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) -/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. - * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. - */ -#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) - -#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) -#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) -/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. - * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. - */ -#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) - -#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) -#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) -/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz - * timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). - * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. The 1 kHz RTC timer is enabled. - */ -#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) - -#define RTC_CTRL_RTC_EN_MASK (0x80U) -#define RTC_CTRL_RTC_EN_SHIFT (7U) -/*! RTC_EN - RTC enable. - * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should - * be 0 when writing to load a value in the RTC counter register. - * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate - * operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the - * high-resolution, 1 kHz clock, set bit 6 in this register. - */ -#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) - -#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) -#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) -/*! RTC_OSC_PD - RTC oscillator power-down control. - * 0b0..See RTC_OSC_BYPASS - * 0b1..RTC oscillator is powered-down. - */ -#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) - -#define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) -#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) -/*! RTC_OSC_BYPASS - RTC oscillator bypass control. - * 0b0..The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. - * 0b1..The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. - */ -#define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) - -#define RTC_CTRL_RTC_SUBSEC_ENA_MASK (0x400U) -#define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT (10U) -/*! RTC_SUBSEC_ENA - RTC Sub-second counter control. - * 0b0..The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD - * reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second - * counter, this bit will always read-back as a '0'. - * 0b1..The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first - * one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is - * set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip - * exits deep power-down mode. - */ -#define RTC_CTRL_RTC_SUBSEC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK) -/*! @} */ - -/*! @name MATCH - RTC match register */ -/*! @{ */ - -#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) -#define RTC_MATCH_MATVAL_SHIFT (0U) -/*! MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the - * alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. - */ -#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) -/*! @} */ - -/*! @name COUNT - RTC counter register */ -/*! @{ */ - -#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) -#define RTC_COUNT_VAL_SHIFT (0U) -/*! VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial - * value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC - * Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this - * register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after - * the RTC_EN bit is set. - */ -#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) -/*! @} */ - -/*! @name WAKE - High-resolution/wake-up timer control register */ -/*! @{ */ - -#define RTC_WAKE_VAL_MASK (0xFFFFU) -#define RTC_WAKE_VAL_SHIFT (0U) -/*! VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads - * a start count value into the wake-up timer and initializes a count-down sequence. Do not write - * to this register while counting is in progress. - */ -#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) -/*! @} */ - -/*! @name SUBSEC - Sub-second counter register */ -/*! @{ */ - -#define RTC_SUBSEC_SUBSEC_MASK (0x7FFFU) -#define RTC_SUBSEC_SUBSEC_SHIFT (0U) -/*! SUBSEC - A read reflects the current value of the 32KHz sub-second counter. This counter is - * cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz - * rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This - * counter must be re-enabled after exiting deep power-down mode or after the main RTC module is - * disabled and re-enabled. On modules not equipped with a sub-second counter, this register - * will read-back as all zeroes. - */ -#define RTC_SUBSEC_SUBSEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_SUBSEC_SHIFT)) & RTC_SUBSEC_SUBSEC_MASK) -/*! @} */ - -/*! @name GPREG - General Purpose register */ -/*! @{ */ - -#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU) -#define RTC_GPREG_GPDATA_SHIFT (0U) -/*! GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied. - */ -#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK) -/*! @} */ - -/* The count of RTC_GPREG */ -#define RTC_GPREG_COUNT (8U) - - -/*! - * @} - */ /* end of group RTC_Register_Masks */ - - -/* RTC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral RTC base address */ - #define RTC_BASE (0x5002C000u) - /** Peripheral RTC base address */ - #define RTC_BASE_NS (0x4002C000u) - /** Peripheral RTC base pointer */ - #define RTC ((RTC_Type *)RTC_BASE) - /** Peripheral RTC base pointer */ - #define RTC_NS ((RTC_Type *)RTC_BASE_NS) - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS { RTC_BASE } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS { RTC } - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS_NS { RTC_BASE_NS } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS_NS { RTC_NS } -#else - /** Peripheral RTC base address */ - #define RTC_BASE (0x4002C000u) - /** Peripheral RTC base pointer */ - #define RTC ((RTC_Type *)RTC_BASE) - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS { RTC_BASE } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS { RTC } -#endif -/** Interrupt vectors for the RTC peripheral type */ -#define RTC_IRQS { RTC_IRQn } - -/*! - * @} - */ /* end of group RTC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SCT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer - * @{ - */ - -/** SCT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ - union { /* offset: 0x4 */ - struct { /* offset: 0x4 */ - __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */ - __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */ - } CTRL_ACCESS16BIT; - __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ - }; - union { /* offset: 0x8 */ - struct { /* offset: 0x8 */ - __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */ - __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */ - } LIMIT_ACCESS16BIT; - __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ - }; - union { /* offset: 0xC */ - struct { /* offset: 0xC */ - __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */ - __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */ - } HALT_ACCESS16BIT; - __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ - }; - union { /* offset: 0x10 */ - struct { /* offset: 0x10 */ - __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */ - __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */ - } STOP_ACCESS16BIT; - __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ - }; - union { /* offset: 0x14 */ - struct { /* offset: 0x14 */ - __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */ - __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */ - } START_ACCESS16BIT; - __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ - }; - uint8_t RESERVED_0[40]; - union { /* offset: 0x40 */ - struct { /* offset: 0x40 */ - __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */ - __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */ - } COUNT_ACCESS16BIT; - __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ - }; - union { /* offset: 0x44 */ - struct { /* offset: 0x44 */ - __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */ - __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */ - } STATE_ACCESS16BIT; - __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ - }; - __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ - union { /* offset: 0x4C */ - struct { /* offset: 0x4C */ - __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */ - __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */ - } REGMODE_ACCESS16BIT; - __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ - }; - __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ - __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ - __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ - __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */ - __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */ - uint8_t RESERVED_1[140]; - __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ - __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ - __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ - __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ - union { /* offset: 0x100 */ - union { /* offset: 0x100, array step: 0x4 */ - struct { /* offset: 0x100, array step: 0x4 */ - __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */ - __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */ - } CAP_ACCESS16BIT[16]; - __IO uint32_t CAP[16]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ - }; - union { /* offset: 0x100, array step: 0x4 */ - struct { /* offset: 0x100, array step: 0x4 */ - __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */ - __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */ - } MATCH_ACCESS16BIT[16]; - __IO uint32_t MATCH[16]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ - }; - }; - uint8_t RESERVED_2[192]; - union { /* offset: 0x200 */ - union { /* offset: 0x200, array step: 0x4 */ - struct { /* offset: 0x200, array step: 0x4 */ - __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */ - __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */ - } CAPCTRL_ACCESS16BIT[16]; - __IO uint32_t CAPCTRL[16]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ - }; - union { /* offset: 0x200, array step: 0x4 */ - struct { /* offset: 0x200, array step: 0x4 */ - __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */ - __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */ - } MATCHREL_ACCESS16BIT[16]; - __IO uint32_t MATCHREL[16]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ - }; - }; - uint8_t RESERVED_3[192]; - struct { /* offset: 0x300, array step: 0x8 */ - __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ - __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ - } EV[16]; - uint8_t RESERVED_4[384]; - struct { /* offset: 0x500, array step: 0x8 */ - __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ - __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ - } OUT[10]; -} SCT_Type; - -/* ---------------------------------------------------------------------------- - -- SCT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Register_Masks SCT Register Masks - * @{ - */ - -/*! @name CONFIG - SCT configuration register */ -/*! @{ */ - -#define SCT_CONFIG_UNIFY_MASK (0x1U) -#define SCT_CONFIG_UNIFY_SHIFT (0U) -/*! UNIFY - SCT operation - * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. - * 0b1..The SCT operates as a unified 32-bit counter. - */ -#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) - -#define SCT_CONFIG_CLKMODE_MASK (0x6U) -#define SCT_CONFIG_CLKMODE_SHIFT (1U) -/*! CLKMODE - SCT clock mode - * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. - * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are - * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The - * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the - * high-performance, sampled-clock mode. - * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the - * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the - * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. - * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL - * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system - * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than - * the system clock. - */ -#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) - -#define SCT_CONFIG_CKSEL_MASK (0x78U) -#define SCT_CONFIG_CKSEL_SHIFT (3U) -/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent - * on the CLKMODE bit selection in this register. - * 0b0000..Rising edges on input 0. - * 0b0001..Falling edges on input 0. - * 0b0010..Rising edges on input 1. - * 0b0011..Falling edges on input 1. - * 0b0100..Rising edges on input 2. - * 0b0101..Falling edges on input 2. - * 0b0110..Rising edges on input 3. - * 0b0111..Falling edges on input 3. - * 0b1000..Rising edges on input 4. - * 0b1001..Falling edges on input 4. - * 0b1010..Rising edges on input 5. - * 0b1011..Falling edges on input 5. - * 0b1100..Rising edges on input 6. - * 0b1101..Falling edges on input 6. - * 0b1110..Rising edges on input 7. - * 0b1111..Falling edges on input 7. - */ -#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) - -#define SCT_CONFIG_NORELOAD_L_MASK (0x80U) -#define SCT_CONFIG_NORELOAD_L_SHIFT (7U) -/*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their - * respective reload registers. Setting this bit eliminates the need to write to the reload - * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any - * time. This bit applies to both the higher and lower registers when the UNIFY bit is set. - */ -#define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK) - -#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) -#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) -/*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their - * respective reload registers. Setting this bit eliminates the need to write to the reload - * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at - * any time. This bit is not used when the UNIFY bit is set. - */ -#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) - -#define SCT_CONFIG_INSYNC_MASK (0x1E00U) -#define SCT_CONFIG_INSYNC_SHIFT (9U) -/*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all - * other bits are reserved. A 1 in one of these bits subjects the corresponding input to - * synchronization to the SCT clock, before it is used to create an event. If an input is known to - * already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: - * The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input - * clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. - * It does not apply to the clock input specified in the CKSEL field. - */ -#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) - -#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) -#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) -/*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto - * LIMIT condition without the need to define an associated event. As with any LIMIT event, this - * automatic limit causes the counter to be cleared to zero in unidirectional mode or to change - * the direction of count in bi-directional mode. Software can write to set or clear this bit at - * any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. - */ -#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) - -#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) -#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) -/*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a - * de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, - * this automatic limit causes the counter to be cleared to zero in unidirectional mode or to - * change the direction of count in bi-directional mode. Software can write to set or clear this bit - * at any time. This bit is not used when the UNIFY bit is set. - */ -#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) -/*! @} */ - -/*! @name CTRLL - SCT_CTRLL register */ -/*! @{ */ - -#define SCT_CTRLL_DOWN_L_MASK (0x1U) -#define SCT_CTRLL_DOWN_L_SHIFT (0U) -/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit - * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit - * when the counter is counting down and a limit condition occurs or when the counter reaches 0. - */ -#define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK) - -#define SCT_CTRLL_STOP_L_MASK (0x2U) -#define SCT_CTRLL_STOP_L_SHIFT (1U) -/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events - * related to the counter can occur. If a designated start event occurs, this bit is cleared and - * counting resumes. - */ -#define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK) - -#define SCT_CTRLL_HALT_L_MASK (0x4U) -#define SCT_CTRLL_HALT_L_SHIFT (2U) -/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A - * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to - * remove the halt condition while keeping the SCT in the stop condition (not running) with a - * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, - * only software can clear this bit to restore counter operation. This bit is set on reset. - */ -#define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK) - -#define SCT_CTRLL_CLRCTR_L_MASK (0x8U) -#define SCT_CTRLL_CLRCTR_L_SHIFT (3U) -/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. - */ -#define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK) - -#define SCT_CTRLL_BIDIR_L_MASK (0x10U) -#define SCT_CTRLL_BIDIR_L_SHIFT (4U) -/*! BIDIR_L - L or unified counter direction select - * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. - * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK) - -#define SCT_CTRLL_PRE_L_MASK (0x1FE0U) -#define SCT_CTRLL_PRE_L_SHIFT (5U) -/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified - * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. - * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - */ -#define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK) -/*! @} */ - -/*! @name CTRLH - SCT_CTRLH register */ -/*! @{ */ - -#define SCT_CTRLH_DOWN_H_MASK (0x1U) -#define SCT_CTRLH_DOWN_H_SHIFT (0U) -/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the - * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit - * when the counter is counting down and a limit condition occurs or when the counter reaches 0. - */ -#define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK) - -#define SCT_CTRLH_STOP_H_MASK (0x2U) -#define SCT_CTRLH_STOP_H_SHIFT (1U) -/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to - * the counter can occur. If such an event matches the mask in the Start register, this bit is - * cleared and counting resumes. - */ -#define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK) - -#define SCT_CTRLH_HALT_H_MASK (0x4U) -#define SCT_CTRLH_HALT_H_SHIFT (2U) -/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets - * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the - * halt condition while keeping the SCT in the stop condition (not running) with a single write to - * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit - * can only be cleared by software to restore counter operation. This bit is set on reset. - */ -#define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK) - -#define SCT_CTRLH_CLRCTR_H_MASK (0x8U) -#define SCT_CTRLH_CLRCTR_H_SHIFT (3U) -/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. - */ -#define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK) - -#define SCT_CTRLH_BIDIR_H_MASK (0x10U) -#define SCT_CTRLH_BIDIR_H_SHIFT (4U) -/*! BIDIR_H - Direction select - * 0b0..The H counter counts up to its limit condition, then is cleared to zero. - * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK) - -#define SCT_CTRLH_PRE_H_MASK (0x1FE0U) -#define SCT_CTRLH_PRE_H_SHIFT (5U) -/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. - * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the - * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - */ -#define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK) -/*! @} */ - -/*! @name CTRL - SCT control register */ -/*! @{ */ - -#define SCT_CTRL_DOWN_L_MASK (0x1U) -#define SCT_CTRL_DOWN_L_SHIFT (0U) -/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit - * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit - * when the counter is counting down and a limit condition occurs or when the counter reaches 0. - */ -#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) - -#define SCT_CTRL_STOP_L_MASK (0x2U) -#define SCT_CTRL_STOP_L_SHIFT (1U) -/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events - * related to the counter can occur. If a designated start event occurs, this bit is cleared and - * counting resumes. - */ -#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) - -#define SCT_CTRL_HALT_L_MASK (0x4U) -#define SCT_CTRL_HALT_L_SHIFT (2U) -/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A - * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to - * remove the halt condition while keeping the SCT in the stop condition (not running) with a - * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, - * only software can clear this bit to restore counter operation. This bit is set on reset. - */ -#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) - -#define SCT_CTRL_CLRCTR_L_MASK (0x8U) -#define SCT_CTRL_CLRCTR_L_SHIFT (3U) -/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. - */ -#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) - -#define SCT_CTRL_BIDIR_L_MASK (0x10U) -#define SCT_CTRL_BIDIR_L_SHIFT (4U) -/*! BIDIR_L - L or unified counter direction select - * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. - * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) - -#define SCT_CTRL_PRE_L_MASK (0x1FE0U) -#define SCT_CTRL_PRE_L_SHIFT (5U) -/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified - * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. - * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - */ -#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) - -#define SCT_CTRL_DOWN_H_MASK (0x10000U) -#define SCT_CTRL_DOWN_H_SHIFT (16U) -/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the - * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit - * when the counter is counting down and a limit condition occurs or when the counter reaches 0. - */ -#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) - -#define SCT_CTRL_STOP_H_MASK (0x20000U) -#define SCT_CTRL_STOP_H_SHIFT (17U) -/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to - * the counter can occur. If such an event matches the mask in the Start register, this bit is - * cleared and counting resumes. - */ -#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) - -#define SCT_CTRL_HALT_H_MASK (0x40000U) -#define SCT_CTRL_HALT_H_SHIFT (18U) -/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets - * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the - * halt condition while keeping the SCT in the stop condition (not running) with a single write to - * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit - * can only be cleared by software to restore counter operation. This bit is set on reset. - */ -#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) - -#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) -#define SCT_CTRL_CLRCTR_H_SHIFT (19U) -/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. - */ -#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) - -#define SCT_CTRL_BIDIR_H_MASK (0x100000U) -#define SCT_CTRL_BIDIR_H_SHIFT (20U) -/*! BIDIR_H - Direction select - * 0b0..The H counter counts up to its limit condition, then is cleared to zero. - * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) - -#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) -#define SCT_CTRL_PRE_H_SHIFT (21U) -/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. - * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the - * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - */ -#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) -/*! @} */ - -/*! @name LIMITL - SCT_LIMITL register */ -/*! @{ */ - -#define SCT_LIMITL_LIMITL_MASK (0xFFFFU) -#define SCT_LIMITL_LIMITL_SHIFT (0U) -#define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK) -/*! @} */ - -/*! @name LIMITH - SCT_LIMITH register */ -/*! @{ */ - -#define SCT_LIMITH_LIMITH_MASK (0xFFFFU) -#define SCT_LIMITH_LIMITH_SHIFT (0U) -#define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK) -/*! @} */ - -/*! @name LIMIT - SCT limit event select register */ -/*! @{ */ - -#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) -#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) -/*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter - * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) - -#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) -#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) -/*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit - * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) -/*! @} */ - -/*! @name HALTL - SCT_HALTL register */ -/*! @{ */ - -#define SCT_HALTL_HALTL_MASK (0xFFFFU) -#define SCT_HALTL_HALTL_SHIFT (0U) -#define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK) -/*! @} */ - -/*! @name HALTH - SCT_HALTH register */ -/*! @{ */ - -#define SCT_HALTH_HALTH_MASK (0xFFFFU) -#define SCT_HALTH_HALTH_SHIFT (0U) -#define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK) -/*! @} */ - -/*! @name HALT - SCT halt event select register */ -/*! @{ */ - -#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) -#define SCT_HALT_HALTMSK_L_SHIFT (0U) -/*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, - * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) - -#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) -#define SCT_HALT_HALTMSK_H_SHIFT (16U) -/*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, - * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) -/*! @} */ - -/*! @name STOPL - SCT_STOPL register */ -/*! @{ */ - -#define SCT_STOPL_STOPL_MASK (0xFFFFU) -#define SCT_STOPL_STOPL_SHIFT (0U) -#define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK) -/*! @} */ - -/*! @name STOPH - SCT_STOPH register */ -/*! @{ */ - -#define SCT_STOPH_STOPH_MASK (0xFFFFU) -#define SCT_STOPH_STOPH_SHIFT (0U) -#define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK) -/*! @} */ - -/*! @name STOP - SCT stop event select register */ -/*! @{ */ - -#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) -#define SCT_STOP_STOPMSK_L_SHIFT (0U) -/*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, - * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) - -#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) -#define SCT_STOP_STOPMSK_H_SHIFT (16U) -/*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, - * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) -/*! @} */ - -/*! @name STARTL - SCT_STARTL register */ -/*! @{ */ - -#define SCT_STARTL_STARTL_MASK (0xFFFFU) -#define SCT_STARTL_STARTL_SHIFT (0U) -#define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK) -/*! @} */ - -/*! @name STARTH - SCT_STARTH register */ -/*! @{ */ - -#define SCT_STARTH_STARTH_MASK (0xFFFFU) -#define SCT_STARTH_STARTH_SHIFT (0U) -#define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK) -/*! @} */ - -/*! @name START - SCT start event select register */ -/*! @{ */ - -#define SCT_START_STARTMSK_L_MASK (0xFFFFU) -#define SCT_START_STARTMSK_L_SHIFT (0U) -/*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit - * 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) - -#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) -#define SCT_START_STARTMSK_H_SHIFT (16U) -/*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit - * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) -/*! @} */ - -/*! @name COUNTL - SCT_COUNTL register */ -/*! @{ */ - -#define SCT_COUNTL_COUNTL_MASK (0xFFFFU) -#define SCT_COUNTL_COUNTL_SHIFT (0U) -#define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK) -/*! @} */ - -/*! @name COUNTH - SCT_COUNTH register */ -/*! @{ */ - -#define SCT_COUNTH_COUNTH_MASK (0xFFFFU) -#define SCT_COUNTH_COUNTH_SHIFT (0U) -#define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK) -/*! @} */ - -/*! @name COUNT - SCT counter register */ -/*! @{ */ - -#define SCT_COUNT_CTR_L_MASK (0xFFFFU) -#define SCT_COUNT_CTR_L_SHIFT (0U) -/*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write - * the lower 16 bits of the 32-bit unified counter. - */ -#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) - -#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) -#define SCT_COUNT_CTR_H_SHIFT (16U) -/*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write - * the upper 16 bits of the 32-bit unified counter. - */ -#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) -/*! @} */ - -/*! @name STATEL - SCT_STATEL register */ -/*! @{ */ - -#define SCT_STATEL_STATEL_MASK (0xFFFFU) -#define SCT_STATEL_STATEL_SHIFT (0U) -#define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK) -/*! @} */ - -/*! @name STATEH - SCT_STATEH register */ -/*! @{ */ - -#define SCT_STATEH_STATEH_MASK (0xFFFFU) -#define SCT_STATEH_STATEH_SHIFT (0U) -#define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK) -/*! @} */ - -/*! @name STATE - SCT state register */ -/*! @{ */ - -#define SCT_STATE_STATE_L_MASK (0x1FU) -#define SCT_STATE_STATE_L_SHIFT (0U) -/*! STATE_L - State variable. - */ -#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) - -#define SCT_STATE_STATE_H_MASK (0x1F0000U) -#define SCT_STATE_STATE_H_SHIFT (16U) -/*! STATE_H - State variable. - */ -#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) -/*! @} */ - -/*! @name INPUT - SCT input register */ -/*! @{ */ - -#define SCT_INPUT_AIN0_MASK (0x1U) -#define SCT_INPUT_AIN0_SHIFT (0U) -/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) - -#define SCT_INPUT_AIN1_MASK (0x2U) -#define SCT_INPUT_AIN1_SHIFT (1U) -/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) - -#define SCT_INPUT_AIN2_MASK (0x4U) -#define SCT_INPUT_AIN2_SHIFT (2U) -/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) - -#define SCT_INPUT_AIN3_MASK (0x8U) -#define SCT_INPUT_AIN3_SHIFT (3U) -/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) - -#define SCT_INPUT_AIN4_MASK (0x10U) -#define SCT_INPUT_AIN4_SHIFT (4U) -/*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) - -#define SCT_INPUT_AIN5_MASK (0x20U) -#define SCT_INPUT_AIN5_SHIFT (5U) -/*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) - -#define SCT_INPUT_AIN6_MASK (0x40U) -#define SCT_INPUT_AIN6_SHIFT (6U) -/*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) - -#define SCT_INPUT_AIN7_MASK (0x80U) -#define SCT_INPUT_AIN7_SHIFT (7U) -/*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) - -#define SCT_INPUT_AIN8_MASK (0x100U) -#define SCT_INPUT_AIN8_SHIFT (8U) -/*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) - -#define SCT_INPUT_AIN9_MASK (0x200U) -#define SCT_INPUT_AIN9_SHIFT (9U) -/*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) - -#define SCT_INPUT_AIN10_MASK (0x400U) -#define SCT_INPUT_AIN10_SHIFT (10U) -/*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) - -#define SCT_INPUT_AIN11_MASK (0x800U) -#define SCT_INPUT_AIN11_SHIFT (11U) -/*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) - -#define SCT_INPUT_AIN12_MASK (0x1000U) -#define SCT_INPUT_AIN12_SHIFT (12U) -/*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) - -#define SCT_INPUT_AIN13_MASK (0x2000U) -#define SCT_INPUT_AIN13_SHIFT (13U) -/*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) - -#define SCT_INPUT_AIN14_MASK (0x4000U) -#define SCT_INPUT_AIN14_SHIFT (14U) -/*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) - -#define SCT_INPUT_AIN15_MASK (0x8000U) -#define SCT_INPUT_AIN15_SHIFT (15U) -/*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge. - */ -#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) - -#define SCT_INPUT_SIN0_MASK (0x10000U) -#define SCT_INPUT_SIN0_SHIFT (16U) -/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) - -#define SCT_INPUT_SIN1_MASK (0x20000U) -#define SCT_INPUT_SIN1_SHIFT (17U) -/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) - -#define SCT_INPUT_SIN2_MASK (0x40000U) -#define SCT_INPUT_SIN2_SHIFT (18U) -/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) - -#define SCT_INPUT_SIN3_MASK (0x80000U) -#define SCT_INPUT_SIN3_SHIFT (19U) -/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) - -#define SCT_INPUT_SIN4_MASK (0x100000U) -#define SCT_INPUT_SIN4_SHIFT (20U) -/*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) - -#define SCT_INPUT_SIN5_MASK (0x200000U) -#define SCT_INPUT_SIN5_SHIFT (21U) -/*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) - -#define SCT_INPUT_SIN6_MASK (0x400000U) -#define SCT_INPUT_SIN6_SHIFT (22U) -/*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) - -#define SCT_INPUT_SIN7_MASK (0x800000U) -#define SCT_INPUT_SIN7_SHIFT (23U) -/*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) - -#define SCT_INPUT_SIN8_MASK (0x1000000U) -#define SCT_INPUT_SIN8_SHIFT (24U) -/*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) - -#define SCT_INPUT_SIN9_MASK (0x2000000U) -#define SCT_INPUT_SIN9_SHIFT (25U) -/*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) - -#define SCT_INPUT_SIN10_MASK (0x4000000U) -#define SCT_INPUT_SIN10_SHIFT (26U) -/*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) - -#define SCT_INPUT_SIN11_MASK (0x8000000U) -#define SCT_INPUT_SIN11_SHIFT (27U) -/*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) - -#define SCT_INPUT_SIN12_MASK (0x10000000U) -#define SCT_INPUT_SIN12_SHIFT (28U) -/*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) - -#define SCT_INPUT_SIN13_MASK (0x20000000U) -#define SCT_INPUT_SIN13_SHIFT (29U) -/*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) - -#define SCT_INPUT_SIN14_MASK (0x40000000U) -#define SCT_INPUT_SIN14_SHIFT (30U) -/*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) - -#define SCT_INPUT_SIN15_MASK (0x80000000U) -#define SCT_INPUT_SIN15_SHIFT (31U) -/*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC. - */ -#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) -/*! @} */ - -/*! @name REGMODEL - SCT_REGMODEL register */ -/*! @{ */ - -#define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU) -#define SCT_REGMODEL_REGMODEL_SHIFT (0U) -#define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK) -/*! @} */ - -/*! @name REGMODEH - SCT_REGMODEH register */ -/*! @{ */ - -#define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU) -#define SCT_REGMODEH_REGMODEH_SHIFT (0U) -#define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK) -/*! @} */ - -/*! @name REGMODE - SCT match/capture mode register */ -/*! @{ */ - -#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) -#define SCT_REGMODE_REGMOD_L_SHIFT (0U) -/*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, - * etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as - * match register. 1 = register operates as capture register. - */ -#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) - -#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) -#define SCT_REGMODE_REGMOD_H_SHIFT (16U) -/*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit - * 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as - * match registers. 1 = register operates as capture registers. - */ -#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) -/*! @} */ - -/*! @name OUTPUT - SCT output register */ -/*! @{ */ - -#define SCT_OUTPUT_OUT_MASK (0xFFFFU) -#define SCT_OUTPUT_OUT_SHIFT (0U) -/*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the - * corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of - * outputs in this SCT. - */ -#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) -/*! @} */ - -/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ -/*! @{ */ - -#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) -#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) -/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) -#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) -/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) -#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) -/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) -#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) -/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) -#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) -/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) -#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) -/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) -#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) -/*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) -#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) -/*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) -#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) -/*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) -#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) -/*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) -#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) -/*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) -#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) -/*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) -/*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) -/*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) -/*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) - -#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) -/*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) -/*! @} */ - -/*! @name RES - SCT conflict resolution register */ -/*! @{ */ - -#define SCT_RES_O0RES_MASK (0x3U) -#define SCT_RES_O0RES_SHIFT (0U) -/*! O0RES - Effect of simultaneous set and clear on output 0. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR0 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) - -#define SCT_RES_O1RES_MASK (0xCU) -#define SCT_RES_O1RES_SHIFT (2U) -/*! O1RES - Effect of simultaneous set and clear on output 1. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR1 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) - -#define SCT_RES_O2RES_MASK (0x30U) -#define SCT_RES_O2RES_SHIFT (4U) -/*! O2RES - Effect of simultaneous set and clear on output 2. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output n (or set based on the SETCLR2 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) - -#define SCT_RES_O3RES_MASK (0xC0U) -#define SCT_RES_O3RES_SHIFT (6U) -/*! O3RES - Effect of simultaneous set and clear on output 3. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR3 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) - -#define SCT_RES_O4RES_MASK (0x300U) -#define SCT_RES_O4RES_SHIFT (8U) -/*! O4RES - Effect of simultaneous set and clear on output 4. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR4 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) - -#define SCT_RES_O5RES_MASK (0xC00U) -#define SCT_RES_O5RES_SHIFT (10U) -/*! O5RES - Effect of simultaneous set and clear on output 5. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR5 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) - -#define SCT_RES_O6RES_MASK (0x3000U) -#define SCT_RES_O6RES_SHIFT (12U) -/*! O6RES - Effect of simultaneous set and clear on output 6. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR6 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) - -#define SCT_RES_O7RES_MASK (0xC000U) -#define SCT_RES_O7RES_SHIFT (14U) -/*! O7RES - Effect of simultaneous set and clear on output 7. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output n (or set based on the SETCLR7 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) - -#define SCT_RES_O8RES_MASK (0x30000U) -#define SCT_RES_O8RES_SHIFT (16U) -/*! O8RES - Effect of simultaneous set and clear on output 8. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR8 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) - -#define SCT_RES_O9RES_MASK (0xC0000U) -#define SCT_RES_O9RES_SHIFT (18U) -/*! O9RES - Effect of simultaneous set and clear on output 9. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR9 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) - -#define SCT_RES_O10RES_MASK (0x300000U) -#define SCT_RES_O10RES_SHIFT (20U) -/*! O10RES - Effect of simultaneous set and clear on output 10. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR10 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) - -#define SCT_RES_O11RES_MASK (0xC00000U) -#define SCT_RES_O11RES_SHIFT (22U) -/*! O11RES - Effect of simultaneous set and clear on output 11. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR11 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) - -#define SCT_RES_O12RES_MASK (0x3000000U) -#define SCT_RES_O12RES_SHIFT (24U) -/*! O12RES - Effect of simultaneous set and clear on output 12. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR12 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) - -#define SCT_RES_O13RES_MASK (0xC000000U) -#define SCT_RES_O13RES_SHIFT (26U) -/*! O13RES - Effect of simultaneous set and clear on output 13. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR13 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) - -#define SCT_RES_O14RES_MASK (0x30000000U) -#define SCT_RES_O14RES_SHIFT (28U) -/*! O14RES - Effect of simultaneous set and clear on output 14. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR14 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) - -#define SCT_RES_O15RES_MASK (0xC0000000U) -#define SCT_RES_O15RES_SHIFT (30U) -/*! O15RES - Effect of simultaneous set and clear on output 15. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR15 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) -/*! @} */ - -/*! @name DMAREQ0 - SCT DMA request 0 register */ -/*! @{ */ - -#define SCT_DMAREQ0_DEV_0_MASK (0xFFFFU) -#define SCT_DMAREQ0_DEV_0_SHIFT (0U) -/*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, - * etc.). The number of bits = number of events in this SCT. - */ -#define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK) - -#define SCT_DMAREQ0_DRL0_MASK (0x40000000U) -#define SCT_DMAREQ0_DRL0_SHIFT (30U) -/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. - */ -#define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK) - -#define SCT_DMAREQ0_DRQ0_MASK (0x80000000U) -#define SCT_DMAREQ0_DRQ0_SHIFT (31U) -/*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA - * channel is enabled and properly set up, it is unlikely that software will see this flag, it will - * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA - * setup. - */ -#define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK) -/*! @} */ - -/*! @name DMAREQ1 - SCT DMA request 1 register */ -/*! @{ */ - -#define SCT_DMAREQ1_DEV_1_MASK (0xFFFFU) -#define SCT_DMAREQ1_DEV_1_SHIFT (0U) -/*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, - * etc.). The number of bits = number of events in this SCT. - */ -#define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK) - -#define SCT_DMAREQ1_DRL1_MASK (0x40000000U) -#define SCT_DMAREQ1_DRL1_SHIFT (30U) -/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. - */ -#define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK) - -#define SCT_DMAREQ1_DRQ1_MASK (0x80000000U) -#define SCT_DMAREQ1_DRQ1_SHIFT (31U) -/*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA - * channel is enabled and properly set up, it is unlikely that software will see this flag, it will - * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA - * setup. - */ -#define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK) -/*! @} */ - -/*! @name EVEN - SCT event interrupt enable register */ -/*! @{ */ - -#define SCT_EVEN_IEN_MASK (0xFFFFU) -#define SCT_EVEN_IEN_SHIFT (0U) -/*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are - * both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in - * this SCT. - */ -#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) -/*! @} */ - -/*! @name EVFLAG - SCT event flag register */ -/*! @{ */ - -#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) -#define SCT_EVFLAG_FLAG_SHIFT (0U) -/*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit - * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - */ -#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) -/*! @} */ - -/*! @name CONEN - SCT conflict interrupt enable register */ -/*! @{ */ - -#define SCT_CONEN_NCEN_MASK (0xFFFFU) -#define SCT_CONEN_NCEN_SHIFT (0U) -/*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag - * register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of - * outputs in this SCT. - */ -#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) -/*! @} */ - -/*! @name CONFLAG - SCT conflict flag register */ -/*! @{ */ - -#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) -#define SCT_CONFLAG_NCFLAG_SHIFT (0U) -/*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was - * last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = - * number of outputs in this SCT. - */ -#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) - -#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) -#define SCT_CONFLAG_BUSERRL_SHIFT (30U) -/*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE - * L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write - * to certain L and H registers can be half successful and half unsuccessful. - */ -#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) - -#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) -#define SCT_CONFLAG_BUSERRH_SHIFT (31U) -/*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or - * the Output register when the H counter was not halted. - */ -#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) -/*! @} */ - -/*! @name CAPL - SCT_CAPL register */ -/*! @{ */ - -#define SCT_CAPL_CAPL_MASK (0xFFFFU) -#define SCT_CAPL_CAPL_SHIFT (0U) -#define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK) -/*! @} */ - -/* The count of SCT_CAPL */ -#define SCT_CAPL_COUNT (16U) - -/*! @name CAPH - SCT_CAPH register */ -/*! @{ */ - -#define SCT_CAPH_CAPH_MASK (0xFFFFU) -#define SCT_CAPH_CAPH_SHIFT (0U) -#define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK) -/*! @} */ - -/* The count of SCT_CAPH */ -#define SCT_CAPH_COUNT (16U) - -/*! @name CAP - SCT capture register of capture channel */ -/*! @{ */ - -#define SCT_CAP_CAPn_L_MASK (0xFFFFU) -#define SCT_CAP_CAPn_L_SHIFT (0U) -/*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. - * When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last - * captured. - */ -#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK) - -#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U) -#define SCT_CAP_CAPn_H_SHIFT (16U) -/*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. - * When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last - * captured. - */ -#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK) -/*! @} */ - -/* The count of SCT_CAP */ -#define SCT_CAP_COUNT (16U) - -/*! @name MATCHL - SCT_MATCHL register */ -/*! @{ */ - -#define SCT_MATCHL_MATCHL_MASK (0xFFFFU) -#define SCT_MATCHL_MATCHL_SHIFT (0U) -#define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK) -/*! @} */ - -/* The count of SCT_MATCHL */ -#define SCT_MATCHL_COUNT (16U) - -/*! @name MATCHH - SCT_MATCHH register */ -/*! @{ */ - -#define SCT_MATCHH_MATCHH_MASK (0xFFFFU) -#define SCT_MATCHH_MATCHH_SHIFT (0U) -#define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK) -/*! @} */ - -/* The count of SCT_MATCHH */ -#define SCT_MATCHH_COUNT (16U) - -/*! @name MATCH - SCT match value register of match channels */ -/*! @{ */ - -#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU) -#define SCT_MATCH_MATCHn_L_SHIFT (0U) -/*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When - * UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified - * counter. - */ -#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK) - -#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U) -#define SCT_MATCH_MATCHn_H_SHIFT (16U) -/*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When - * UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified - * counter. - */ -#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK) -/*! @} */ - -/* The count of SCT_MATCH */ -#define SCT_MATCH_COUNT (16U) - -/*! @name CAPCTRLL - SCT_CAPCTRLL register */ -/*! @{ */ - -#define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU) -#define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U) -#define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK) -/*! @} */ - -/* The count of SCT_CAPCTRLL */ -#define SCT_CAPCTRLL_COUNT (16U) - -/*! @name CAPCTRLH - SCT_CAPCTRLH register */ -/*! @{ */ - -#define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU) -#define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U) -#define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK) -/*! @} */ - -/* The count of SCT_CAPCTRLH */ -#define SCT_CAPCTRLH_COUNT (16U) - -/*! @name CAPCTRL - SCT capture control register */ -/*! @{ */ - -#define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU) -#define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U) -/*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) - * register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of - * match/captures in this SCT. - */ -#define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK) - -#define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) -#define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U) -/*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event - * 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - */ -#define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK) -/*! @} */ - -/* The count of SCT_CAPCTRL */ -#define SCT_CAPCTRL_COUNT (16U) - -/*! @name MATCHRELL - SCT_MATCHRELL register */ -/*! @{ */ - -#define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU) -#define SCT_MATCHRELL_MATCHRELL_SHIFT (0U) -#define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK) -/*! @} */ - -/* The count of SCT_MATCHRELL */ -#define SCT_MATCHRELL_COUNT (16U) - -/*! @name MATCHRELH - SCT_MATCHRELH register */ -/*! @{ */ - -#define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU) -#define SCT_MATCHRELH_MATCHRELH_SHIFT (0U) -#define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK) -/*! @} */ - -/* The count of SCT_MATCHRELH */ -#define SCT_MATCHRELH_COUNT (16U) - -/*! @name MATCHREL - SCT match reload value register */ -/*! @{ */ - -#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU) -#define SCT_MATCHREL_RELOADn_L_SHIFT (0U) -/*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. - * When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn - * register. - */ -#define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK) - -#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U) -#define SCT_MATCHREL_RELOADn_H_SHIFT (16U) -/*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When - * UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn - * register. - */ -#define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK) -/*! @} */ - -/* The count of SCT_MATCHREL */ -#define SCT_MATCHREL_COUNT (16U) - -/*! @name EV_STATE - SCT event state register 0 */ -/*! @{ */ - -#define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFU) -#define SCT_EV_STATE_STATEMSKn_SHIFT (0U) -/*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT - * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of - * bits = number of states in this SCT. - */ -#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK) -/*! @} */ - -/* The count of SCT_EV_STATE */ -#define SCT_EV_STATE_COUNT (16U) - -/*! @name EV_CTRL - SCT event control register 0 */ -/*! @{ */ - -#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU) -#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U) -/*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur - * only when the counter selected by the HEVENT bit is running. - */ -#define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK) - -#define SCT_EV_CTRL_HEVENT_MASK (0x10U) -#define SCT_EV_CTRL_HEVENT_SHIFT (4U) -/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. - * 0b0..Selects the L state and the L match register selected by MATCHSEL. - * 0b1..Selects the H state and the H match register selected by MATCHSEL. - */ -#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK) - -#define SCT_EV_CTRL_OUTSEL_MASK (0x20U) -#define SCT_EV_CTRL_OUTSEL_SHIFT (5U) -/*! OUTSEL - Input/output select - * 0b0..Selects the inputs selected by IOSEL. - * 0b1..Selects the outputs selected by IOSEL. - */ -#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK) - -#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U) -#define SCT_EV_CTRL_IOSEL_SHIFT (6U) -/*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not - * select an input in this register if CKMODE is 1x. In this case the clock input is an implicit - * ingredient of every event. - */ -#define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK) - -#define SCT_EV_CTRL_IOCOND_MASK (0xC00U) -#define SCT_EV_CTRL_IOCOND_SHIFT (10U) -/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the - * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state - * detection, an input must have a minimum pulse width of at least one SCT clock period . - * 0b00..LOW - * 0b01..Rise - * 0b10..Fall - * 0b11..HIGH - */ -#define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK) - -#define SCT_EV_CTRL_COMBMODE_MASK (0x3000U) -#define SCT_EV_CTRL_COMBMODE_SHIFT (12U) -/*! COMBMODE - Selects how the specified match and I/O condition are used and combined. - * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. - * 0b01..MATCH. Uses the specified match only. - * 0b10..IO. Uses the specified I/O condition only. - * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. - */ -#define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK) - -#define SCT_EV_CTRL_STATELD_MASK (0x4000U) -#define SCT_EV_CTRL_STATELD_SHIFT (14U) -/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this - * event is the highest-numbered event occurring for that state. - * 0b0..STATEV value is added into STATE (the carry-out is ignored). - * 0b1..STATEV value is loaded into STATE. - */ -#define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK) - -#define SCT_EV_CTRL_STATEV_MASK (0xF8000U) -#define SCT_EV_CTRL_STATEV_SHIFT (15U) -/*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on - * STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and - * STATEV are both zero, there is no change to the STATE value. - */ -#define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK) - -#define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U) -#define SCT_EV_CTRL_MATCHMEM_SHIFT (20U) -/*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the - * triggering of this event, then a match is considered to be active whenever the counter value is - * GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR - * EQUAL TO the match value when counting down. If this bit is zero, a match is only be active - * during the cycle when the counter is equal to the match value. - */ -#define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK) - -#define SCT_EV_CTRL_DIRECTION_MASK (0x600000U) -#define SCT_EV_CTRL_DIRECTION_SHIFT (21U) -/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters - * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. - * 0b00..Direction independent. This event is triggered regardless of the count direction. - * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. - * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. - */ -#define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK) -/*! @} */ - -/* The count of SCT_EV_CTRL */ -#define SCT_EV_CTRL_COUNT (16U) - -/*! @name OUT_SET - SCT output 0 set register */ -/*! @{ */ - -#define SCT_OUT_SET_SET_MASK (0xFFFFU) -#define SCT_OUT_SET_SET_SHIFT (0U) -/*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output - * 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the - * counter is used in bi-directional mode, it is possible to reverse the action specified by the - * output set and clear registers when counting down, See the OUTPUTCTRL register. - */ -#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) -/*! @} */ - -/* The count of SCT_OUT_SET */ -#define SCT_OUT_SET_COUNT (10U) - -/*! @name OUT_CLR - SCT output 0 clear register */ -/*! @{ */ - -#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) -#define SCT_OUT_CLR_CLR_SHIFT (0U) -/*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 - * = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the - * counter is used in bi-directional mode, it is possible to reverse the action specified by the - * output set and clear registers when counting down, See the OUTPUTCTRL register. - */ -#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) -/*! @} */ - -/* The count of SCT_OUT_CLR */ -#define SCT_OUT_CLR_COUNT (10U) - - -/*! - * @} - */ /* end of group SCT_Register_Masks */ - - -/* SCT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SCT0 base address */ - #define SCT0_BASE (0x50085000u) - /** Peripheral SCT0 base address */ - #define SCT0_BASE_NS (0x40085000u) - /** Peripheral SCT0 base pointer */ - #define SCT0 ((SCT_Type *)SCT0_BASE) - /** Peripheral SCT0 base pointer */ - #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS { SCT0_BASE } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS { SCT0 } - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS_NS { SCT0_NS } -#else - /** Peripheral SCT0 base address */ - #define SCT0_BASE (0x40085000u) - /** Peripheral SCT0 base pointer */ - #define SCT0 ((SCT_Type *)SCT0_BASE) - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS { SCT0_BASE } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS { SCT0 } -#endif -/** Interrupt vectors for the SCT peripheral type */ -#define SCT_IRQS { SCT0_IRQn } - -/*! - * @} - */ /* end of group SCT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SDIF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer - * @{ - */ - -/** SDIF - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register, offset: 0x0 */ - __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */ - __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */ - __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */ - __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */ - __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */ - __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */ - __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */ - __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */ - __IO uint32_t CMD; /**< Command register, offset: 0x2C */ - __IO uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */ - __IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */ - __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */ - __IO uint32_t STATUS; /**< Status register, offset: 0x48 */ - __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */ - __IO uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */ - __IO uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */ - uint8_t RESERVED_1[4]; - __IO uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */ - __IO uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */ - __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */ - uint8_t RESERVED_2[16]; - __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */ - uint8_t RESERVED_3[4]; - __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */ - __IO uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */ - __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */ - __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */ - __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */ - __IO uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */ - __IO uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */ - uint8_t RESERVED_4[100]; - __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */ - __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */ - uint8_t RESERVED_5[248]; - __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */ -} SDIF_Type; - -/* ---------------------------------------------------------------------------- - -- SDIF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDIF_Register_Masks SDIF Register Masks - * @{ - */ - -/*! @name CTRL - Control register */ -/*! @{ */ - -#define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U) -#define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U) -/*! CONTROLLER_RESET - Controller reset. - */ -#define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK) - -#define SDIF_CTRL_FIFO_RESET_MASK (0x2U) -#define SDIF_CTRL_FIFO_RESET_SHIFT (1U) -/*! FIFO_RESET - Fifo reset. - */ -#define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK) - -#define SDIF_CTRL_DMA_RESET_MASK (0x4U) -#define SDIF_CTRL_DMA_RESET_SHIFT (2U) -/*! DMA_RESET - DMA reset. - */ -#define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK) - -#define SDIF_CTRL_INT_ENABLE_MASK (0x10U) -#define SDIF_CTRL_INT_ENABLE_SHIFT (4U) -/*! INT_ENABLE - Global interrupt enable/disable bit. - */ -#define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK) - -#define SDIF_CTRL_READ_WAIT_MASK (0x40U) -#define SDIF_CTRL_READ_WAIT_SHIFT (6U) -/*! READ_WAIT - Read/wait. - */ -#define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK) - -#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U) -#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U) -/*! SEND_IRQ_RESPONSE - Send irq response. - */ -#define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK) - -#define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U) -#define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U) -/*! ABORT_READ_DATA - Abort read data. - */ -#define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK) - -#define SDIF_CTRL_SEND_CCSD_MASK (0x200U) -#define SDIF_CTRL_SEND_CCSD_SHIFT (9U) -/*! SEND_CCSD - Send ccsd. - */ -#define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK) - -#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U) -#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U) -/*! SEND_AUTO_STOP_CCSD - Send auto stop ccsd. - */ -#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK) - -#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U) -#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U) -/*! CEATA_DEVICE_INTERRUPT_STATUS - CEATA device interrupt status. - */ -#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK) - -#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U) -#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U) -/*! CARD_VOLTAGE_A0 - Controls the state of the SD_VOLT0 pin. - */ -#define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK) - -#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U) -#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U) -/*! CARD_VOLTAGE_A1 - Controls the state of the SD_VOLT1 pin. - */ -#define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK) - -#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U) -#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U) -/*! CARD_VOLTAGE_A2 - Controls the state of the SD_VOLT2 pin. - */ -#define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK) - -#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U) -#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U) -/*! USE_INTERNAL_DMAC - SD/MMC DMA use. - */ -#define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) -/*! @} */ - -/*! @name PWREN - Power Enable register */ -/*! @{ */ - -#define SDIF_PWREN_POWER_ENABLE0_MASK (0x1U) -#define SDIF_PWREN_POWER_ENABLE0_SHIFT (0U) -/*! POWER_ENABLE0 - Power on/off switch for card 0; once power is turned on, software should wait - * for regulator/switch ramp-up time before trying to initialize card 0. - */ -#define SDIF_PWREN_POWER_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE0_SHIFT)) & SDIF_PWREN_POWER_ENABLE0_MASK) - -#define SDIF_PWREN_POWER_ENABLE1_MASK (0x2U) -#define SDIF_PWREN_POWER_ENABLE1_SHIFT (1U) -/*! POWER_ENABLE1 - Power on/off switch for card 1; once power is turned on, software should wait - * for regulator/switch ramp-up time before trying to initialize card 1. - */ -#define SDIF_PWREN_POWER_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE1_SHIFT)) & SDIF_PWREN_POWER_ENABLE1_MASK) -/*! @} */ - -/*! @name CLKDIV - Clock Divider register */ -/*! @{ */ - -#define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU) -#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U) -/*! CLK_DIVIDER0 - Clock divider-0 value. - */ -#define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK) -/*! @} */ - -/*! @name CLKENA - Clock Enable register */ -/*! @{ */ - -#define SDIF_CLKENA_CCLK0_ENABLE_MASK (0x1U) -#define SDIF_CLKENA_CCLK0_ENABLE_SHIFT (0U) -/*! CCLK0_ENABLE - Clock-enable control for SD card 0 clock. - */ -#define SDIF_CLKENA_CCLK0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK0_ENABLE_MASK) - -#define SDIF_CLKENA_CCLK1_ENABLE_MASK (0x2U) -#define SDIF_CLKENA_CCLK1_ENABLE_SHIFT (1U) -/*! CCLK1_ENABLE - Clock-enable control for SD card 1 clock. - */ -#define SDIF_CLKENA_CCLK1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK1_ENABLE_MASK) - -#define SDIF_CLKENA_CCLK0_LOW_POWER_MASK (0x10000U) -#define SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT (16U) -/*! CCLK0_LOW_POWER - Low-power control for SD card 0 clock. - */ -#define SDIF_CLKENA_CCLK0_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK0_LOW_POWER_MASK) - -#define SDIF_CLKENA_CCLK1_LOW_POWER_MASK (0x20000U) -#define SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT (17U) -/*! CCLK1_LOW_POWER - Low-power control for SD card 1 clock. - */ -#define SDIF_CLKENA_CCLK1_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK1_LOW_POWER_MASK) -/*! @} */ - -/*! @name TMOUT - Time-out register */ -/*! @{ */ - -#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU) -#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U) -/*! RESPONSE_TIMEOUT - Response time-out value. - */ -#define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK) - -#define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U) -#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U) -/*! DATA_TIMEOUT - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. - */ -#define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK) -/*! @} */ - -/*! @name CTYPE - Card Type register */ -/*! @{ */ - -#define SDIF_CTYPE_CARD0_WIDTH0_MASK (0x1U) -#define SDIF_CTYPE_CARD0_WIDTH0_SHIFT (0U) -/*! CARD0_WIDTH0 - Indicates if card 0 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit - * modes only work when 8-bit mode in CARD0_WIDTH1 is not enabled (bit 16 in this register is set - * to 0). - */ -#define SDIF_CTYPE_CARD0_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH0_MASK) - -#define SDIF_CTYPE_CARD1_WIDTH0_MASK (0x2U) -#define SDIF_CTYPE_CARD1_WIDTH0_SHIFT (1U) -/*! CARD1_WIDTH0 - Indicates if card 1 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit - * modes only work when 8-bit mode in CARD1_WIDTH1 is not enabled (bit 16 in this register is set - * to 0). - */ -#define SDIF_CTYPE_CARD1_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH0_MASK) - -#define SDIF_CTYPE_CARD0_WIDTH1_MASK (0x10000U) -#define SDIF_CTYPE_CARD0_WIDTH1_SHIFT (16U) -/*! CARD0_WIDTH1 - Indicates if card 0 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. - */ -#define SDIF_CTYPE_CARD0_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH1_MASK) - -#define SDIF_CTYPE_CARD1_WIDTH1_MASK (0x20000U) -#define SDIF_CTYPE_CARD1_WIDTH1_SHIFT (17U) -/*! CARD1_WIDTH1 - Indicates if card 1 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. - */ -#define SDIF_CTYPE_CARD1_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH1_MASK) -/*! @} */ - -/*! @name BLKSIZ - Block Size register */ -/*! @{ */ - -#define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU) -#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U) -/*! BLOCK_SIZE - Block size. - */ -#define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK) -/*! @} */ - -/*! @name BYTCNT - Byte Count register */ -/*! @{ */ - -#define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU) -#define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U) -/*! BYTE_COUNT - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. - */ -#define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK) -/*! @} */ - -/*! @name INTMASK - Interrupt Mask register */ -/*! @{ */ - -#define SDIF_INTMASK_CDET_MASK (0x1U) -#define SDIF_INTMASK_CDET_SHIFT (0U) -/*! CDET - Card detect. - */ -#define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK) - -#define SDIF_INTMASK_RE_MASK (0x2U) -#define SDIF_INTMASK_RE_SHIFT (1U) -/*! RE - Response error. - */ -#define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK) - -#define SDIF_INTMASK_CDONE_MASK (0x4U) -#define SDIF_INTMASK_CDONE_SHIFT (2U) -/*! CDONE - Command done. - */ -#define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK) - -#define SDIF_INTMASK_DTO_MASK (0x8U) -#define SDIF_INTMASK_DTO_SHIFT (3U) -/*! DTO - Data transfer over. - */ -#define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK) - -#define SDIF_INTMASK_TXDR_MASK (0x10U) -#define SDIF_INTMASK_TXDR_SHIFT (4U) -/*! TXDR - Transmit FIFO data request. - */ -#define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK) - -#define SDIF_INTMASK_RXDR_MASK (0x20U) -#define SDIF_INTMASK_RXDR_SHIFT (5U) -/*! RXDR - Receive FIFO data request. - */ -#define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK) - -#define SDIF_INTMASK_RCRC_MASK (0x40U) -#define SDIF_INTMASK_RCRC_SHIFT (6U) -/*! RCRC - Response CRC error. - */ -#define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK) - -#define SDIF_INTMASK_DCRC_MASK (0x80U) -#define SDIF_INTMASK_DCRC_SHIFT (7U) -/*! DCRC - Data CRC error. - */ -#define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK) - -#define SDIF_INTMASK_RTO_MASK (0x100U) -#define SDIF_INTMASK_RTO_SHIFT (8U) -/*! RTO - Response time-out. - */ -#define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK) - -#define SDIF_INTMASK_DRTO_MASK (0x200U) -#define SDIF_INTMASK_DRTO_SHIFT (9U) -/*! DRTO - Data read time-out. - */ -#define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK) - -#define SDIF_INTMASK_HTO_MASK (0x400U) -#define SDIF_INTMASK_HTO_SHIFT (10U) -/*! HTO - Data starvation-by-host time-out (HTO). - */ -#define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK) - -#define SDIF_INTMASK_FRUN_MASK (0x800U) -#define SDIF_INTMASK_FRUN_SHIFT (11U) -/*! FRUN - FIFO underrun/overrun error. - */ -#define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK) - -#define SDIF_INTMASK_HLE_MASK (0x1000U) -#define SDIF_INTMASK_HLE_SHIFT (12U) -/*! HLE - Hardware locked write error. - */ -#define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK) - -#define SDIF_INTMASK_SBE_MASK (0x2000U) -#define SDIF_INTMASK_SBE_SHIFT (13U) -/*! SBE - Start-bit error. - */ -#define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK) - -#define SDIF_INTMASK_ACD_MASK (0x4000U) -#define SDIF_INTMASK_ACD_SHIFT (14U) -/*! ACD - Auto command done. - */ -#define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK) - -#define SDIF_INTMASK_EBE_MASK (0x8000U) -#define SDIF_INTMASK_EBE_SHIFT (15U) -/*! EBE - End-bit error (read)/Write no CRC. - */ -#define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK) - -#define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U) -#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U) -/*! SDIO_INT_MASK - Mask SDIO interrupt. - */ -#define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK) -/*! @} */ - -/*! @name CMDARG - Command Argument register */ -/*! @{ */ - -#define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU) -#define SDIF_CMDARG_CMD_ARG_SHIFT (0U) -/*! CMD_ARG - Value indicates command argument to be passed to card. - */ -#define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK) -/*! @} */ - -/*! @name CMD - Command register */ -/*! @{ */ - -#define SDIF_CMD_CMD_INDEX_MASK (0x3FU) -#define SDIF_CMD_CMD_INDEX_SHIFT (0U) -/*! CMD_INDEX - Command index. - */ -#define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK) - -#define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U) -#define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U) -/*! RESPONSE_EXPECT - Response expect. - */ -#define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK) - -#define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U) -#define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U) -/*! RESPONSE_LENGTH - Response length. - */ -#define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK) - -#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U) -#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U) -/*! CHECK_RESPONSE_CRC - Check response CRC. - */ -#define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK) - -#define SDIF_CMD_DATA_EXPECTED_MASK (0x200U) -#define SDIF_CMD_DATA_EXPECTED_SHIFT (9U) -/*! DATA_EXPECTED - Data expected. - */ -#define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK) - -#define SDIF_CMD_READ_WRITE_MASK (0x400U) -#define SDIF_CMD_READ_WRITE_SHIFT (10U) -/*! READ_WRITE - read/write. - */ -#define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK) - -#define SDIF_CMD_TRANSFER_MODE_MASK (0x800U) -#define SDIF_CMD_TRANSFER_MODE_SHIFT (11U) -/*! TRANSFER_MODE - Transfer mode. - */ -#define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK) - -#define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U) -#define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U) -/*! SEND_AUTO_STOP - Send auto stop. - */ -#define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK) - -#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U) -#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U) -/*! WAIT_PRVDATA_COMPLETE - Wait prvdata complete. - */ -#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK) - -#define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U) -#define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U) -/*! STOP_ABORT_CMD - Stop abort command. - */ -#define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK) - -#define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U) -#define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U) -/*! SEND_INITIALIZATION - Send initialization. - */ -#define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK) - -#define SDIF_CMD_CARD_NUMBER_MASK (0x1F0000U) -#define SDIF_CMD_CARD_NUMBER_SHIFT (16U) -/*! CARD_NUMBER - Specifies the card number of SDCARD for which the current Command is being executed - * 0b00000..Command will be execute on SDCARD 0 - * 0b00001..Command will be execute on SDCARD 1 - */ -#define SDIF_CMD_CARD_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CARD_NUMBER_SHIFT)) & SDIF_CMD_CARD_NUMBER_MASK) - -#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U) -#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U) -/*! UPDATE_CLOCK_REGISTERS_ONLY - Update clock registers only. - */ -#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK) - -#define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U) -#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U) -/*! READ_CEATA_DEVICE - Read ceata device. - */ -#define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK) - -#define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U) -#define SDIF_CMD_CCS_EXPECTED_SHIFT (23U) -/*! CCS_EXPECTED - CCS expected. - */ -#define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK) - -#define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U) -#define SDIF_CMD_ENABLE_BOOT_SHIFT (24U) -/*! ENABLE_BOOT - Enable Boot - this bit should be set only for mandatory boot mode. - */ -#define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK) - -#define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U) -#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U) -/*! EXPECT_BOOT_ACK - Expect Boot Acknowledge. - */ -#define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK) - -#define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U) -#define SDIF_CMD_DISABLE_BOOT_SHIFT (26U) -/*! DISABLE_BOOT - Disable Boot. - */ -#define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK) - -#define SDIF_CMD_BOOT_MODE_MASK (0x8000000U) -#define SDIF_CMD_BOOT_MODE_SHIFT (27U) -/*! BOOT_MODE - Boot Mode. - */ -#define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK) - -#define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U) -#define SDIF_CMD_VOLT_SWITCH_SHIFT (28U) -/*! VOLT_SWITCH - Voltage switch bit. - */ -#define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK) - -#define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U) -#define SDIF_CMD_USE_HOLD_REG_SHIFT (29U) -/*! USE_HOLD_REG - Use Hold Register. - */ -#define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK) - -#define SDIF_CMD_START_CMD_MASK (0x80000000U) -#define SDIF_CMD_START_CMD_SHIFT (31U) -/*! START_CMD - Start command. - */ -#define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK) -/*! @} */ - -/*! @name RESP - Response register */ -/*! @{ */ - -#define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU) -#define SDIF_RESP_RESPONSE_SHIFT (0U) -/*! RESPONSE - Bits of response. - */ -#define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK) -/*! @} */ - -/* The count of SDIF_RESP */ -#define SDIF_RESP_COUNT (4U) - -/*! @name MINTSTS - Masked Interrupt Status register */ -/*! @{ */ - -#define SDIF_MINTSTS_CDET_MASK (0x1U) -#define SDIF_MINTSTS_CDET_SHIFT (0U) -/*! CDET - Card detect. - */ -#define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK) - -#define SDIF_MINTSTS_RE_MASK (0x2U) -#define SDIF_MINTSTS_RE_SHIFT (1U) -/*! RE - Response error. - */ -#define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK) - -#define SDIF_MINTSTS_CDONE_MASK (0x4U) -#define SDIF_MINTSTS_CDONE_SHIFT (2U) -/*! CDONE - Command done. - */ -#define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK) - -#define SDIF_MINTSTS_DTO_MASK (0x8U) -#define SDIF_MINTSTS_DTO_SHIFT (3U) -/*! DTO - Data transfer over. - */ -#define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK) - -#define SDIF_MINTSTS_TXDR_MASK (0x10U) -#define SDIF_MINTSTS_TXDR_SHIFT (4U) -/*! TXDR - Transmit FIFO data request. - */ -#define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK) - -#define SDIF_MINTSTS_RXDR_MASK (0x20U) -#define SDIF_MINTSTS_RXDR_SHIFT (5U) -/*! RXDR - Receive FIFO data request. - */ -#define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK) - -#define SDIF_MINTSTS_RCRC_MASK (0x40U) -#define SDIF_MINTSTS_RCRC_SHIFT (6U) -/*! RCRC - Response CRC error. - */ -#define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK) - -#define SDIF_MINTSTS_DCRC_MASK (0x80U) -#define SDIF_MINTSTS_DCRC_SHIFT (7U) -/*! DCRC - Data CRC error. - */ -#define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK) - -#define SDIF_MINTSTS_RTO_MASK (0x100U) -#define SDIF_MINTSTS_RTO_SHIFT (8U) -/*! RTO - Response time-out. - */ -#define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK) - -#define SDIF_MINTSTS_DRTO_MASK (0x200U) -#define SDIF_MINTSTS_DRTO_SHIFT (9U) -/*! DRTO - Data read time-out. - */ -#define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK) - -#define SDIF_MINTSTS_HTO_MASK (0x400U) -#define SDIF_MINTSTS_HTO_SHIFT (10U) -/*! HTO - Data starvation-by-host time-out (HTO). - */ -#define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK) - -#define SDIF_MINTSTS_FRUN_MASK (0x800U) -#define SDIF_MINTSTS_FRUN_SHIFT (11U) -/*! FRUN - FIFO underrun/overrun error. - */ -#define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK) - -#define SDIF_MINTSTS_HLE_MASK (0x1000U) -#define SDIF_MINTSTS_HLE_SHIFT (12U) -/*! HLE - Hardware locked write error. - */ -#define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK) - -#define SDIF_MINTSTS_SBE_MASK (0x2000U) -#define SDIF_MINTSTS_SBE_SHIFT (13U) -/*! SBE - Start-bit error. - */ -#define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK) - -#define SDIF_MINTSTS_ACD_MASK (0x4000U) -#define SDIF_MINTSTS_ACD_SHIFT (14U) -/*! ACD - Auto command done. - */ -#define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK) - -#define SDIF_MINTSTS_EBE_MASK (0x8000U) -#define SDIF_MINTSTS_EBE_SHIFT (15U) -/*! EBE - End-bit error (read)/write no CRC. - */ -#define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK) - -#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U) -#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U) -/*! SDIO_INTERRUPT - Interrupt from SDIO card. - */ -#define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK) -/*! @} */ - -/*! @name RINTSTS - Raw Interrupt Status register */ -/*! @{ */ - -#define SDIF_RINTSTS_CDET_MASK (0x1U) -#define SDIF_RINTSTS_CDET_SHIFT (0U) -/*! CDET - Card detect. - */ -#define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK) - -#define SDIF_RINTSTS_RE_MASK (0x2U) -#define SDIF_RINTSTS_RE_SHIFT (1U) -/*! RE - Response error. - */ -#define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK) - -#define SDIF_RINTSTS_CDONE_MASK (0x4U) -#define SDIF_RINTSTS_CDONE_SHIFT (2U) -/*! CDONE - Command done. - */ -#define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK) - -#define SDIF_RINTSTS_DTO_MASK (0x8U) -#define SDIF_RINTSTS_DTO_SHIFT (3U) -/*! DTO - Data transfer over. - */ -#define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK) - -#define SDIF_RINTSTS_TXDR_MASK (0x10U) -#define SDIF_RINTSTS_TXDR_SHIFT (4U) -/*! TXDR - Transmit FIFO data request. - */ -#define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK) - -#define SDIF_RINTSTS_RXDR_MASK (0x20U) -#define SDIF_RINTSTS_RXDR_SHIFT (5U) -/*! RXDR - Receive FIFO data request. - */ -#define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK) - -#define SDIF_RINTSTS_RCRC_MASK (0x40U) -#define SDIF_RINTSTS_RCRC_SHIFT (6U) -/*! RCRC - Response CRC error. - */ -#define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK) - -#define SDIF_RINTSTS_DCRC_MASK (0x80U) -#define SDIF_RINTSTS_DCRC_SHIFT (7U) -/*! DCRC - Data CRC error. - */ -#define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK) - -#define SDIF_RINTSTS_RTO_BAR_MASK (0x100U) -#define SDIF_RINTSTS_RTO_BAR_SHIFT (8U) -/*! RTO_BAR - Response time-out (RTO)/Boot Ack Received (BAR). - */ -#define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK) - -#define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U) -#define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U) -/*! DRTO_BDS - Data read time-out (DRTO)/Boot Data Start (BDS). - */ -#define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK) - -#define SDIF_RINTSTS_HTO_MASK (0x400U) -#define SDIF_RINTSTS_HTO_SHIFT (10U) -/*! HTO - Data starvation-by-host time-out (HTO). - */ -#define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK) - -#define SDIF_RINTSTS_FRUN_MASK (0x800U) -#define SDIF_RINTSTS_FRUN_SHIFT (11U) -/*! FRUN - FIFO underrun/overrun error. - */ -#define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK) - -#define SDIF_RINTSTS_HLE_MASK (0x1000U) -#define SDIF_RINTSTS_HLE_SHIFT (12U) -/*! HLE - Hardware locked write error. - */ -#define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK) - -#define SDIF_RINTSTS_SBE_MASK (0x2000U) -#define SDIF_RINTSTS_SBE_SHIFT (13U) -/*! SBE - Start-bit error. - */ -#define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK) - -#define SDIF_RINTSTS_ACD_MASK (0x4000U) -#define SDIF_RINTSTS_ACD_SHIFT (14U) -/*! ACD - Auto command done. - */ -#define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK) - -#define SDIF_RINTSTS_EBE_MASK (0x8000U) -#define SDIF_RINTSTS_EBE_SHIFT (15U) -/*! EBE - End-bit error (read)/write no CRC. - */ -#define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK) - -#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U) -#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U) -/*! SDIO_INTERRUPT - Interrupt from SDIO card. - */ -#define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK) -/*! @} */ - -/*! @name STATUS - Status register */ -/*! @{ */ - -#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U) -#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U) -/*! FIFO_RX_WATERMARK - FIFO reached Receive watermark level; not qualified with data transfer. - */ -#define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK) - -#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U) -#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U) -/*! FIFO_TX_WATERMARK - FIFO reached Transmit watermark level; not qualified with data transfer. - */ -#define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK) - -#define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U) -#define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U) -/*! FIFO_EMPTY - FIFO is empty status. - */ -#define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK) - -#define SDIF_STATUS_FIFO_FULL_MASK (0x8U) -#define SDIF_STATUS_FIFO_FULL_SHIFT (3U) -/*! FIFO_FULL - FIFO is full status. - */ -#define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK) - -#define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U) -#define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U) -/*! CMDFSMSTATES - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx - * cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - - * Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp - * crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The - * command FSM state is represented using 19 bits. - */ -#define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK) - -#define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U) -#define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U) -/*! DATA_3_STATUS - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present. - */ -#define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK) - -#define SDIF_STATUS_DATA_BUSY_MASK (0x200U) -#define SDIF_STATUS_DATA_BUSY_SHIFT (9U) -/*! DATA_BUSY - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy. - */ -#define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK) - -#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U) -#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U) -/*! DATA_STATE_MC_BUSY - Data transmit or receive state-machine is busy. - */ -#define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK) - -#define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) -#define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U) -/*! RESPONSE_INDEX - Index of previous response, including any auto-stop sent by core. - */ -#define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK) - -#define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U) -#define SDIF_STATUS_FIFO_COUNT_SHIFT (17U) -/*! FIFO_COUNT - FIFO count - Number of filled locations in FIFO. - */ -#define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK) - -#define SDIF_STATUS_DMA_ACK_MASK (0x40000000U) -#define SDIF_STATUS_DMA_ACK_SHIFT (30U) -/*! DMA_ACK - DMA acknowledge signal state. - */ -#define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK) - -#define SDIF_STATUS_DMA_REQ_MASK (0x80000000U) -#define SDIF_STATUS_DMA_REQ_SHIFT (31U) -/*! DMA_REQ - DMA request signal state. - */ -#define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK) -/*! @} */ - -/*! @name FIFOTH - FIFO Threshold Watermark register */ -/*! @{ */ - -#define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU) -#define SDIF_FIFOTH_TX_WMARK_SHIFT (0U) -/*! TX_WMARK - FIFO threshold watermark level when transmitting data to card. - */ -#define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK) - -#define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U) -#define SDIF_FIFOTH_RX_WMARK_SHIFT (16U) -/*! RX_WMARK - FIFO threshold watermark level when receiving data to card. - */ -#define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK) - -#define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U) -#define SDIF_FIFOTH_DMA_MTS_SHIFT (28U) -/*! DMA_MTS - Burst size of multiple transaction; should be programmed same as DW-DMA controller - * multiple-transaction-size SRC/DEST_MSIZE. - */ -#define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK) -/*! @} */ - -/*! @name CDETECT - Card Detect register */ -/*! @{ */ - -#define SDIF_CDETECT_CARD0_DETECT_MASK (0x1U) -#define SDIF_CDETECT_CARD0_DETECT_SHIFT (0U) -/*! CARD0_DETECT - Card 0 detect - */ -#define SDIF_CDETECT_CARD0_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD0_DETECT_SHIFT)) & SDIF_CDETECT_CARD0_DETECT_MASK) - -#define SDIF_CDETECT_CARD1_DETECT_MASK (0x2U) -#define SDIF_CDETECT_CARD1_DETECT_SHIFT (1U) -/*! CARD1_DETECT - Card 1 detect - */ -#define SDIF_CDETECT_CARD1_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD1_DETECT_SHIFT)) & SDIF_CDETECT_CARD1_DETECT_MASK) -/*! @} */ - -/*! @name WRTPRT - Write Protect register */ -/*! @{ */ - -#define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U) -#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U) -/*! WRITE_PROTECT - Write protect. - */ -#define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK) -/*! @} */ - -/*! @name TCBCNT - Transferred CIU Card Byte Count register */ -/*! @{ */ - -#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU) -#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U) -/*! TRANS_CARD_BYTE_COUNT - Number of bytes transferred by CIU unit to card. - */ -#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK) -/*! @} */ - -/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */ -/*! @{ */ - -#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU) -#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U) -/*! TRANS_FIFO_BYTE_COUNT - Number of bytes transferred between Host/DMA memory and BIU FIFO. - */ -#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK) -/*! @} */ - -/*! @name DEBNCE - Debounce Count register */ -/*! @{ */ - -#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU) -#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U) -/*! DEBOUNCE_COUNT - Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms. - */ -#define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK) -/*! @} */ - -/*! @name RST_N - Hardware Reset */ -/*! @{ */ - -#define SDIF_RST_N_CARD_RESET_MASK (0x1U) -#define SDIF_RST_N_CARD_RESET_SHIFT (0U) -/*! CARD_RESET - Hardware reset. - */ -#define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK) -/*! @} */ - -/*! @name BMOD - Bus Mode register */ -/*! @{ */ - -#define SDIF_BMOD_SWR_MASK (0x1U) -#define SDIF_BMOD_SWR_SHIFT (0U) -/*! SWR - Software Reset. - */ -#define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK) - -#define SDIF_BMOD_FB_MASK (0x2U) -#define SDIF_BMOD_FB_SHIFT (1U) -/*! FB - Fixed Burst. - */ -#define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK) - -#define SDIF_BMOD_DSL_MASK (0x7CU) -#define SDIF_BMOD_DSL_SHIFT (2U) -/*! DSL - Descriptor Skip Length. - */ -#define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK) - -#define SDIF_BMOD_DE_MASK (0x80U) -#define SDIF_BMOD_DE_SHIFT (7U) -/*! DE - SD/MMC DMA Enable. - */ -#define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK) - -#define SDIF_BMOD_PBL_MASK (0x700U) -#define SDIF_BMOD_PBL_SHIFT (8U) -/*! PBL - Programmable Burst Length. - */ -#define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK) -/*! @} */ - -/*! @name PLDMND - Poll Demand register */ -/*! @{ */ - -#define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU) -#define SDIF_PLDMND_PD_SHIFT (0U) -/*! PD - Poll Demand. - */ -#define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK) -/*! @} */ - -/*! @name DBADDR - Descriptor List Base Address register */ -/*! @{ */ - -#define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU) -#define SDIF_DBADDR_SDL_SHIFT (0U) -/*! SDL - Start of Descriptor List. - */ -#define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK) -/*! @} */ - -/*! @name IDSTS - Internal DMAC Status register */ -/*! @{ */ - -#define SDIF_IDSTS_TI_MASK (0x1U) -#define SDIF_IDSTS_TI_SHIFT (0U) -/*! TI - Transmit Interrupt. - */ -#define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK) - -#define SDIF_IDSTS_RI_MASK (0x2U) -#define SDIF_IDSTS_RI_SHIFT (1U) -/*! RI - Receive Interrupt. - */ -#define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK) - -#define SDIF_IDSTS_FBE_MASK (0x4U) -#define SDIF_IDSTS_FBE_SHIFT (2U) -/*! FBE - Fatal Bus Error Interrupt. - */ -#define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK) - -#define SDIF_IDSTS_DU_MASK (0x10U) -#define SDIF_IDSTS_DU_SHIFT (4U) -/*! DU - Descriptor Unavailable Interrupt. - */ -#define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK) - -#define SDIF_IDSTS_CES_MASK (0x20U) -#define SDIF_IDSTS_CES_SHIFT (5U) -/*! CES - Card Error Summary. - */ -#define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK) - -#define SDIF_IDSTS_NIS_MASK (0x100U) -#define SDIF_IDSTS_NIS_SHIFT (8U) -/*! NIS - Normal Interrupt Summary. - */ -#define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK) - -#define SDIF_IDSTS_AIS_MASK (0x200U) -#define SDIF_IDSTS_AIS_SHIFT (9U) -/*! AIS - Abnormal Interrupt Summary. - */ -#define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK) - -#define SDIF_IDSTS_EB_MASK (0x1C00U) -#define SDIF_IDSTS_EB_SHIFT (10U) -/*! EB - Error Bits. - */ -#define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK) - -#define SDIF_IDSTS_FSM_MASK (0x1E000U) -#define SDIF_IDSTS_FSM_SHIFT (13U) -/*! FSM - DMAC state machine present state. - */ -#define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK) -/*! @} */ - -/*! @name IDINTEN - Internal DMAC Interrupt Enable register */ -/*! @{ */ - -#define SDIF_IDINTEN_TI_MASK (0x1U) -#define SDIF_IDINTEN_TI_SHIFT (0U) -/*! TI - Transmit Interrupt Enable. - */ -#define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK) - -#define SDIF_IDINTEN_RI_MASK (0x2U) -#define SDIF_IDINTEN_RI_SHIFT (1U) -/*! RI - Receive Interrupt Enable. - */ -#define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK) - -#define SDIF_IDINTEN_FBE_MASK (0x4U) -#define SDIF_IDINTEN_FBE_SHIFT (2U) -/*! FBE - Fatal Bus Error Enable. - */ -#define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK) - -#define SDIF_IDINTEN_DU_MASK (0x10U) -#define SDIF_IDINTEN_DU_SHIFT (4U) -/*! DU - Descriptor Unavailable Interrupt. - */ -#define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK) - -#define SDIF_IDINTEN_CES_MASK (0x20U) -#define SDIF_IDINTEN_CES_SHIFT (5U) -/*! CES - Card Error summary Interrupt Enable. - */ -#define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK) - -#define SDIF_IDINTEN_NIS_MASK (0x100U) -#define SDIF_IDINTEN_NIS_SHIFT (8U) -/*! NIS - Normal Interrupt Summary Enable. - */ -#define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK) - -#define SDIF_IDINTEN_AIS_MASK (0x200U) -#define SDIF_IDINTEN_AIS_SHIFT (9U) -/*! AIS - Abnormal Interrupt Summary Enable. - */ -#define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK) -/*! @} */ - -/*! @name DSCADDR - Current Host Descriptor Address register */ -/*! @{ */ - -#define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU) -#define SDIF_DSCADDR_HDA_SHIFT (0U) -/*! HDA - Host Descriptor Address Pointer. - */ -#define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK) -/*! @} */ - -/*! @name BUFADDR - Current Buffer Descriptor Address register */ -/*! @{ */ - -#define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU) -#define SDIF_BUFADDR_HBA_SHIFT (0U) -/*! HBA - Host Buffer Address Pointer. - */ -#define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK) -/*! @} */ - -/*! @name CARDTHRCTL - Card Threshold Control */ -/*! @{ */ - -#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U) -#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U) -/*! CARDRDTHREN - Card Read Threshold Enable. - */ -#define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK) - -#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U) -#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U) -/*! BSYCLRINTEN - Busy Clear Interrupt Enable. - */ -#define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK) - -#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U) -#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U) -/*! CARDTHRESHOLD - Card Threshold size. - */ -#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK) -/*! @} */ - -/*! @name BACKENDPWR - Power control */ -/*! @{ */ - -#define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U) -#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U) -/*! BACKENDPWR - Back-end Power control for card application. - */ -#define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK) -/*! @} */ - -/*! @name FIFO - SDIF FIFO */ -/*! @{ */ - -#define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU) -#define SDIF_FIFO_DATA_SHIFT (0U) -/*! DATA - SDIF FIFO. - */ -#define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK) -/*! @} */ - -/* The count of SDIF_FIFO */ -#define SDIF_FIFO_COUNT (64U) - - -/*! - * @} - */ /* end of group SDIF_Register_Masks */ - - -/* SDIF - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SDIF base address */ - #define SDIF_BASE (0x5009B000u) - /** Peripheral SDIF base address */ - #define SDIF_BASE_NS (0x4009B000u) - /** Peripheral SDIF base pointer */ - #define SDIF ((SDIF_Type *)SDIF_BASE) - /** Peripheral SDIF base pointer */ - #define SDIF_NS ((SDIF_Type *)SDIF_BASE_NS) - /** Array initializer of SDIF peripheral base addresses */ - #define SDIF_BASE_ADDRS { SDIF_BASE } - /** Array initializer of SDIF peripheral base pointers */ - #define SDIF_BASE_PTRS { SDIF } - /** Array initializer of SDIF peripheral base addresses */ - #define SDIF_BASE_ADDRS_NS { SDIF_BASE_NS } - /** Array initializer of SDIF peripheral base pointers */ - #define SDIF_BASE_PTRS_NS { SDIF_NS } -#else - /** Peripheral SDIF base address */ - #define SDIF_BASE (0x4009B000u) - /** Peripheral SDIF base pointer */ - #define SDIF ((SDIF_Type *)SDIF_BASE) - /** Array initializer of SDIF peripheral base addresses */ - #define SDIF_BASE_ADDRS { SDIF_BASE } - /** Array initializer of SDIF peripheral base pointers */ - #define SDIF_BASE_PTRS { SDIF } -#endif -/** Interrupt vectors for the SDIF peripheral type */ -#define SDIF_IRQS { SDIO_IRQn } - -/*! - * @} - */ /* end of group SDIF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer - * @{ - */ - -/** SPI - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[1024]; - __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ - __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ - __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ - __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ - __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ - __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ - uint8_t RESERVED_2[2516]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_6[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_7[4]; - __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ - uint8_t RESERVED_8[432]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} SPI_Type; - -/* ---------------------------------------------------------------------------- - -- SPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Register_Masks SPI Register Masks - * @{ - */ - -/*! @name CFG - SPI Configuration register */ -/*! @{ */ - -#define SPI_CFG_ENABLE_MASK (0x1U) -#define SPI_CFG_ENABLE_SHIFT (0U) -/*! ENABLE - SPI enable. - * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. - * 0b1..Enabled. The SPI is enabled for operation. - */ -#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) - -#define SPI_CFG_MASTER_MASK (0x4U) -#define SPI_CFG_MASTER_SHIFT (2U) -/*! MASTER - Master mode select. - * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. - * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. - */ -#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) - -#define SPI_CFG_LSBF_MASK (0x8U) -#define SPI_CFG_LSBF_SHIFT (3U) -/*! LSBF - LSB First mode enable. - * 0b0..Standard. Data is transmitted and received in standard MSB first order. - * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). - */ -#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) - -#define SPI_CFG_CPHA_MASK (0x10U) -#define SPI_CFG_CPHA_SHIFT (4U) -/*! CPHA - Clock Phase select. - * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock - * changes away from the rest state). Data is changed on the following edge. - * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock - * changes away from the rest state). Data is captured on the following edge. - */ -#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) - -#define SPI_CFG_CPOL_MASK (0x20U) -#define SPI_CFG_CPOL_SHIFT (5U) -/*! CPOL - Clock Polarity select. - * 0b0..Low. The rest state of the clock (between transfers) is low. - * 0b1..High. The rest state of the clock (between transfers) is high. - */ -#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) - -#define SPI_CFG_LOOP_MASK (0x80U) -#define SPI_CFG_LOOP_SHIFT (7U) -/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit - * and receive data connected together to allow simple software testing. - * 0b0..Disabled. - * 0b1..Enabled. - */ -#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) - -#define SPI_CFG_SPOL0_MASK (0x100U) -#define SPI_CFG_SPOL0_SHIFT (8U) -/*! SPOL0 - SSEL0 Polarity select. - * 0b0..Low. The SSEL0 pin is active low. - * 0b1..High. The SSEL0 pin is active high. - */ -#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) - -#define SPI_CFG_SPOL1_MASK (0x200U) -#define SPI_CFG_SPOL1_SHIFT (9U) -/*! SPOL1 - SSEL1 Polarity select. - * 0b0..Low. The SSEL1 pin is active low. - * 0b1..High. The SSEL1 pin is active high. - */ -#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) - -#define SPI_CFG_SPOL2_MASK (0x400U) -#define SPI_CFG_SPOL2_SHIFT (10U) -/*! SPOL2 - SSEL2 Polarity select. - * 0b0..Low. The SSEL2 pin is active low. - * 0b1..High. The SSEL2 pin is active high. - */ -#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) - -#define SPI_CFG_SPOL3_MASK (0x800U) -#define SPI_CFG_SPOL3_SHIFT (11U) -/*! SPOL3 - SSEL3 Polarity select. - * 0b0..Low. The SSEL3 pin is active low. - * 0b1..High. The SSEL3 pin is active high. - */ -#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) -/*! @} */ - -/*! @name DLY - SPI Delay register */ -/*! @{ */ - -#define SPI_DLY_PRE_DELAY_MASK (0xFU) -#define SPI_DLY_PRE_DELAY_SHIFT (0U) -/*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data - * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This - * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI - * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are - * inserted. - */ -#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) - -#define SPI_DLY_POST_DELAY_MASK (0xF0U) -#define SPI_DLY_POST_DELAY_SHIFT (4U) -/*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL - * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock - * times are inserted. 0xF = 15 SPI clock times are inserted. - */ -#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) - -#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) -#define SPI_DLY_FRAME_DELAY_SHIFT (8U) -/*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current - * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 - * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock - * times are inserted. - */ -#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) - -#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) -#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) -/*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between - * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 - * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that - * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 - * SPI clock times. - */ -#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) -/*! @} */ - -/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ -/*! @{ */ - -#define SPI_STAT_SSA_MASK (0x10U) -#define SPI_STAT_SSA_SHIFT (4U) -/*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from - * deasserted to asserted, in both master and slave modes. This allows determining when the SPI - * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a - * slave mode access begins. This flag is cleared by software. - */ -#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) - -#define SPI_STAT_SSD_MASK (0x20U) -#define SPI_STAT_SSD_SHIFT (5U) -/*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to - * deasserted, in both master and slave modes. This allows determining when the SPI - * transmit/receive functions become idle. This flag is cleared by software. - */ -#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) - -#define SPI_STAT_STALLED_MASK (0x40U) -#define SPI_STAT_STALLED_SHIFT (6U) -/*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition. - */ -#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) - -#define SPI_STAT_ENDTRANSFER_MASK (0x80U) -#define SPI_STAT_ENDTRANSFER_SHIFT (7U) -/*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current - * transfer when the transmitter finishes any activity already in progress, as if the EOT flag - * had been set prior to the last transmission. This capability is included to support cases where - * it is not known when transmit data is written that it will be the end of a transfer. The bit - * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end - * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. - */ -#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) - -#define SPI_STAT_MSTIDLE_MASK (0x100U) -#define SPI_STAT_MSTIDLE_SHIFT (8U) -/*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. - * This means that the transmit holding register is empty and the transmitter is not in the - * process of sending data. - */ -#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -/*! @{ */ - -#define SPI_INTENSET_SSAEN_MASK (0x10U) -#define SPI_INTENSET_SSAEN_SHIFT (4U) -/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. - * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. - * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. - */ -#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) - -#define SPI_INTENSET_SSDEN_MASK (0x20U) -#define SPI_INTENSET_SSDEN_SHIFT (5U) -/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. - * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. - * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. - */ -#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) - -#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) -#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) -/*! MSTIDLEEN - Master idle interrupt enable. - * 0b0..No interrupt will be generated when the SPI master function is idle. - * 0b1..An interrupt will be generated when the SPI master function is fully idle. - */ -#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) -/*! @} */ - -/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ -/*! @{ */ - -#define SPI_INTENCLR_SSAEN_MASK (0x10U) -#define SPI_INTENCLR_SSAEN_SHIFT (4U) -/*! SSAEN - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) - -#define SPI_INTENCLR_SSDEN_MASK (0x20U) -#define SPI_INTENCLR_SSDEN_SHIFT (5U) -/*! SSDEN - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) - -#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) -#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) -/*! MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) -/*! @} */ - -/*! @name DIV - SPI clock Divider */ -/*! @{ */ - -#define SPI_DIV_DIVVAL_MASK (0xFFFFU) -#define SPI_DIV_DIVVAL_SHIFT (0U) -/*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the - * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, - * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results - * in FCLK/65536. - */ -#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - SPI Interrupt Status */ -/*! @{ */ - -#define SPI_INTSTAT_SSA_MASK (0x10U) -#define SPI_INTSTAT_SSA_SHIFT (4U) -/*! SSA - Slave Select Assert. - */ -#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) - -#define SPI_INTSTAT_SSD_MASK (0x20U) -#define SPI_INTSTAT_SSD_SHIFT (5U) -/*! SSD - Slave Select Deassert. - */ -#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) - -#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) -#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) -/*! MSTIDLE - Master Idle status flag. - */ -#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ - -#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) -#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) - -#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) -#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) - -#define SPI_FIFOCFG_SIZE_MASK (0x30U) -#define SPI_FIFOCFG_SIZE_SHIFT (4U) -/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 - * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - */ -#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) - -#define SPI_FIFOCFG_DMATX_MASK (0x1000U) -#define SPI_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) - -#define SPI_FIFOCFG_DMARX_MASK (0x2000U) -#define SPI_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) - -#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) -#define SPI_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in - * FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) - -#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) -#define SPI_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in - * FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) - -#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) -/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - */ -#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) - -#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) -/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - */ -#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ - -#define SPI_FIFOSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow - * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is - * needed. Cleared by writing a 1 to this bit. - */ -#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) - -#define SPI_FIFOSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA - * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - */ -#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) - -#define SPI_FIFOSTAT_PERINT_MASK (0x8U) -#define SPI_FIFOSTAT_PERINT_SHIFT (3U) -/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted - * an interrupt. The details can be found by reading the peripheral's STAT register. - */ -#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) - -#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) -/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - */ -#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) - -#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) -/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be - * written. When 0, the transmit FIFO is full and another write would cause it to overflow. - */ -#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) - -#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - */ -#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) - -#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) -#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) -/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to - * prevent the peripheral from causing an overflow. - */ -#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) - -#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY - * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at - * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be - * 0. - */ -#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) - -#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and - * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the - * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be - * 1. - */ -#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ - -#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) - -#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) - -#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) -#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled - * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to - * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO - * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX - * FIFO level decreases to 15 entries (is no longer full). - */ -#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) - -#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data - * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level - * can wake up the device just enough to perform DMA, then return to the reduced power mode. See - * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no - * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX - * FIFO has received 16 entries (has become full). - */ -#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ - -#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) -#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) - -#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) -#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) - -#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases - * to the level specified by TXLVL in the FIFOTRIG register. - */ -#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) - -#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level - * increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ - -#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) -#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) -/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) - -#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) -#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) -/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) - -#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) -/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) - -#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) -/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ - -#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. - */ -#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) - -#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. - */ -#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) - -#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO level interrupt. - */ -#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) - -#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO level interrupt. - */ -#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) - -#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) -#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) -/*! PERINT - Peripheral interrupt. - */ -#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ - -#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) -#define SPI_FIFOWR_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit data to the FIFO. - */ -#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) - -#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) -#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) -/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL0 asserted. - * 0b1..SSEL0 not asserted. - */ -#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) - -#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) -#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) -/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL1 asserted. - * 0b1..SSEL1 not asserted. - */ -#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) - -#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) -#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) -/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL2 asserted. - * 0b1..SSEL2 not asserted. - */ -#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) - -#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) -#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) -/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL3 asserted. - * 0b1..SSEL3 not asserted. - */ -#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) - -#define SPI_FIFOWR_EOT_MASK (0x100000U) -#define SPI_FIFOWR_EOT_SHIFT (20U) -/*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain - * so far at least the time specified by the Transfer_delay value in the DLY register. - * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. - * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. - */ -#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) - -#define SPI_FIFOWR_EOF_MASK (0x200000U) -#define SPI_FIFOWR_EOF_SHIFT (21U) -/*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value - * in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay - * value = 0. This control can be used as part of the support for frame lengths greater than 16 - * bits. - * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame. - * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be - * inserted before subsequent data is transmitted. - */ -#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) - -#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) -#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) -/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to - * read unneeded data from the receiver. Setting this bit simplifies the transmit process and can - * be used with the DMA. - * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit - * will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data - * is not read before new data is received. - * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received - * data. No receiver flags are generated. - */ -#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) - -#define SPI_FIFOWR_LEN_MASK (0xF000000U) -#define SPI_FIFOWR_LEN_SHIFT (24U) -/*! LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths - * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. - * 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data - * transfer is 16 bits in length. - */ -#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ - -#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORD_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. - */ -#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) - -#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) -/*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved - * along with received data. The value will reflect the SSEL0 pin for both master and slave - * operation. A zero indicates that a slave select is active. The actual polarity of each slave select - * pin is configured by the related SPOL bit in CFG. - */ -#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) - -#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) -/*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved - * along with received data. The value will reflect the SSEL1 pin for both master and slave - * operation. A zero indicates that a slave select is active. The actual polarity of each slave select - * pin is configured by the related SPOL bit in CFG. - */ -#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) - -#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) -/*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved - * along with received data. The value will reflect the SSEL2 pin for both master and slave - * operation. A zero indicates that a slave select is active. The actual polarity of each slave select - * pin is configured by the related SPOL bit in CFG. - */ -#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) - -#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) -/*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved - * along with received data. The value will reflect the SSEL3 pin for both master and slave - * operation. A zero indicates that a slave select is active. The actual polarity of each slave select - * pin is configured by the related SPOL bit in CFG. - */ -#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) - -#define SPI_FIFORD_SOT_MASK (0x100000U) -#define SPI_FIFORD_SOT_SHIFT (20U) -/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went - * from deasserted to asserted (i.e., any previous transfer has ended). This information can be - * used to identify the first piece of data in cases where the transfer length is greater than 16 - * bits. - */ -#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ - -#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. - */ -#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) -/*! RXSSEL0_N - Slave Select for receive. - */ -#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) -/*! RXSSEL1_N - Slave Select for receive. - */ -#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) -/*! RXSSEL2_N - Slave Select for receive. - */ -#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) - -#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) -/*! RXSSEL3_N - Slave Select for receive. - */ -#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) - -#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) -#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) -/*! SOT - Start of transfer flag. - */ -#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) -/*! @} */ - -/*! @name FIFOSIZE - FIFO size register */ -/*! @{ */ - -#define SPI_FIFOSIZE_FIFOSIZE_MASK (0x1FU) -#define SPI_FIFOSIZE_FIFOSIZE_SHIFT (0U) -/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - */ -#define SPI_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSIZE_FIFOSIZE_SHIFT)) & SPI_FIFOSIZE_FIFOSIZE_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ - -#define SPI_ID_APERTURE_MASK (0xFFU) -#define SPI_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - */ -#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) - -#define SPI_ID_MINOR_REV_MASK (0xF00U) -#define SPI_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation. - */ -#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) - -#define SPI_ID_MAJOR_REV_MASK (0xF000U) -#define SPI_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation. - */ -#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) - -#define SPI_ID_ID_MASK (0xFFFF0000U) -#define SPI_ID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function. - */ -#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SPI_Register_Masks */ - - -/* SPI - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SPI0 base address */ - #define SPI0_BASE (0x50086000u) - /** Peripheral SPI0 base address */ - #define SPI0_BASE_NS (0x40086000u) - /** Peripheral SPI0 base pointer */ - #define SPI0 ((SPI_Type *)SPI0_BASE) - /** Peripheral SPI0 base pointer */ - #define SPI0_NS ((SPI_Type *)SPI0_BASE_NS) - /** Peripheral SPI1 base address */ - #define SPI1_BASE (0x50087000u) - /** Peripheral SPI1 base address */ - #define SPI1_BASE_NS (0x40087000u) - /** Peripheral SPI1 base pointer */ - #define SPI1 ((SPI_Type *)SPI1_BASE) - /** Peripheral SPI1 base pointer */ - #define SPI1_NS ((SPI_Type *)SPI1_BASE_NS) - /** Peripheral SPI2 base address */ - #define SPI2_BASE (0x50088000u) - /** Peripheral SPI2 base address */ - #define SPI2_BASE_NS (0x40088000u) - /** Peripheral SPI2 base pointer */ - #define SPI2 ((SPI_Type *)SPI2_BASE) - /** Peripheral SPI2 base pointer */ - #define SPI2_NS ((SPI_Type *)SPI2_BASE_NS) - /** Peripheral SPI3 base address */ - #define SPI3_BASE (0x50089000u) - /** Peripheral SPI3 base address */ - #define SPI3_BASE_NS (0x40089000u) - /** Peripheral SPI3 base pointer */ - #define SPI3 ((SPI_Type *)SPI3_BASE) - /** Peripheral SPI3 base pointer */ - #define SPI3_NS ((SPI_Type *)SPI3_BASE_NS) - /** Peripheral SPI4 base address */ - #define SPI4_BASE (0x5008A000u) - /** Peripheral SPI4 base address */ - #define SPI4_BASE_NS (0x4008A000u) - /** Peripheral SPI4 base pointer */ - #define SPI4 ((SPI_Type *)SPI4_BASE) - /** Peripheral SPI4 base pointer */ - #define SPI4_NS ((SPI_Type *)SPI4_BASE_NS) - /** Peripheral SPI5 base address */ - #define SPI5_BASE (0x50096000u) - /** Peripheral SPI5 base address */ - #define SPI5_BASE_NS (0x40096000u) - /** Peripheral SPI5 base pointer */ - #define SPI5 ((SPI_Type *)SPI5_BASE) - /** Peripheral SPI5 base pointer */ - #define SPI5_NS ((SPI_Type *)SPI5_BASE_NS) - /** Peripheral SPI6 base address */ - #define SPI6_BASE (0x50097000u) - /** Peripheral SPI6 base address */ - #define SPI6_BASE_NS (0x40097000u) - /** Peripheral SPI6 base pointer */ - #define SPI6 ((SPI_Type *)SPI6_BASE) - /** Peripheral SPI6 base pointer */ - #define SPI6_NS ((SPI_Type *)SPI6_BASE_NS) - /** Peripheral SPI7 base address */ - #define SPI7_BASE (0x50098000u) - /** Peripheral SPI7 base address */ - #define SPI7_BASE_NS (0x40098000u) - /** Peripheral SPI7 base pointer */ - #define SPI7 ((SPI_Type *)SPI7_BASE) - /** Peripheral SPI7 base pointer */ - #define SPI7_NS ((SPI_Type *)SPI7_BASE_NS) - /** Peripheral SPI8 base address */ - #define SPI8_BASE (0x5009F000u) - /** Peripheral SPI8 base address */ - #define SPI8_BASE_NS (0x4009F000u) - /** Peripheral SPI8 base pointer */ - #define SPI8 ((SPI_Type *)SPI8_BASE) - /** Peripheral SPI8 base pointer */ - #define SPI8_NS ((SPI_Type *)SPI8_BASE_NS) - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS_NS { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS_NS { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS } -#else - /** Peripheral SPI0 base address */ - #define SPI0_BASE (0x40086000u) - /** Peripheral SPI0 base pointer */ - #define SPI0 ((SPI_Type *)SPI0_BASE) - /** Peripheral SPI1 base address */ - #define SPI1_BASE (0x40087000u) - /** Peripheral SPI1 base pointer */ - #define SPI1 ((SPI_Type *)SPI1_BASE) - /** Peripheral SPI2 base address */ - #define SPI2_BASE (0x40088000u) - /** Peripheral SPI2 base pointer */ - #define SPI2 ((SPI_Type *)SPI2_BASE) - /** Peripheral SPI3 base address */ - #define SPI3_BASE (0x40089000u) - /** Peripheral SPI3 base pointer */ - #define SPI3 ((SPI_Type *)SPI3_BASE) - /** Peripheral SPI4 base address */ - #define SPI4_BASE (0x4008A000u) - /** Peripheral SPI4 base pointer */ - #define SPI4 ((SPI_Type *)SPI4_BASE) - /** Peripheral SPI5 base address */ - #define SPI5_BASE (0x40096000u) - /** Peripheral SPI5 base pointer */ - #define SPI5 ((SPI_Type *)SPI5_BASE) - /** Peripheral SPI6 base address */ - #define SPI6_BASE (0x40097000u) - /** Peripheral SPI6 base pointer */ - #define SPI6 ((SPI_Type *)SPI6_BASE) - /** Peripheral SPI7 base address */ - #define SPI7_BASE (0x40098000u) - /** Peripheral SPI7 base pointer */ - #define SPI7 ((SPI_Type *)SPI7_BASE) - /** Peripheral SPI8 base address */ - #define SPI8_BASE (0x4009F000u) - /** Peripheral SPI8 base pointer */ - #define SPI8 ((SPI_Type *)SPI8_BASE) - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } -#endif -/** Interrupt vectors for the SPI peripheral type */ -#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } - -/*! - * @} - */ /* end of group SPI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SYSCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer - * @{ - */ - -/** SYSCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t MEMORYREMAP; /**< Memory Remap control register, offset: 0x0 */ - uint8_t RESERVED_0[12]; - __IO uint32_t AHBMATPRIO; /**< AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest, offset: 0x10 */ - uint8_t RESERVED_1[36]; - __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */ - __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */ - __IO uint32_t CPU1STCKCAL; /**< System tick calibration for CPU1, offset: 0x40 */ - uint8_t RESERVED_2[4]; - __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ - uint8_t RESERVED_3[180]; - union { /* offset: 0x100 */ - struct { /* offset: 0x100 */ - __IO uint32_t PRESETCTRL0; /**< Peripheral reset control 0, offset: 0x100 */ - __IO uint32_t PRESETCTRL1; /**< Peripheral reset control 1, offset: 0x104 */ - __IO uint32_t PRESETCTRL2; /**< Peripheral reset control 2, offset: 0x108 */ - } PRESETCTRL; - __IO uint32_t PRESETCTRLX[3]; /**< Peripheral reset control register, array offset: 0x100, array step: 0x4 */ - }; - uint8_t RESERVED_4[20]; - __IO uint32_t PRESETCTRLSET[3]; /**< Peripheral reset control set register, array offset: 0x120, array step: 0x4 */ - uint8_t RESERVED_5[20]; - __IO uint32_t PRESETCTRLCLR[3]; /**< Peripheral reset control clear register, array offset: 0x140, array step: 0x4 */ - uint8_t RESERVED_6[20]; - __O uint32_t SWR_RESET; /**< generate a software_reset, offset: 0x160 */ - uint8_t RESERVED_7[156]; - union { /* offset: 0x200 */ - struct { /* offset: 0x200 */ - __IO uint32_t AHBCLKCTRL0; /**< AHB Clock control 0, offset: 0x200 */ - __IO uint32_t AHBCLKCTRL1; /**< AHB Clock control 1, offset: 0x204 */ - __IO uint32_t AHBCLKCTRL2; /**< AHB Clock control 2, offset: 0x208 */ - } AHBCLKCTRL; - __IO uint32_t AHBCLKCTRLX[3]; /**< Peripheral reset control register, array offset: 0x200, array step: 0x4 */ - }; - uint8_t RESERVED_8[20]; - __IO uint32_t AHBCLKCTRLSET[3]; /**< Peripheral reset control register, array offset: 0x220, array step: 0x4 */ - uint8_t RESERVED_9[20]; - __IO uint32_t AHBCLKCTRLCLR[3]; /**< Peripheral reset control register, array offset: 0x240, array step: 0x4 */ - uint8_t RESERVED_10[20]; - union { /* offset: 0x260 */ - struct { /* offset: 0x260 */ - __IO uint32_t SYSTICKCLKSEL0; /**< System Tick Timer for CPU0 source select, offset: 0x260 */ - __IO uint32_t SYSTICKCLKSEL1; /**< System Tick Timer for CPU1 source select, offset: 0x264 */ - } SYSTICKCLKSEL; - __IO uint32_t SYSTICKCLKSELX[2]; /**< Peripheral reset control register, array offset: 0x260, array step: 0x4 */ - }; - __IO uint32_t TRACECLKSEL; /**< Trace clock source select, offset: 0x268 */ - union { /* offset: 0x26C */ - struct { /* offset: 0x26C */ - __IO uint32_t CTIMERCLKSEL0; /**< CTimer 0 clock source select, offset: 0x26C */ - __IO uint32_t CTIMERCLKSEL1; /**< CTimer 1 clock source select, offset: 0x270 */ - __IO uint32_t CTIMERCLKSEL2; /**< CTimer 2 clock source select, offset: 0x274 */ - __IO uint32_t CTIMERCLKSEL3; /**< CTimer 3 clock source select, offset: 0x278 */ - __IO uint32_t CTIMERCLKSEL4; /**< CTimer 4 clock source select, offset: 0x27C */ - } CTIMERCLKSEL; - __IO uint32_t CTIMERCLKSELX[5]; /**< Peripheral reset control register, array offset: 0x26C, array step: 0x4 */ - }; - __IO uint32_t MAINCLKSELA; /**< Main clock A source select, offset: 0x280 */ - __IO uint32_t MAINCLKSELB; /**< Main clock source select, offset: 0x284 */ - __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0x288 */ - uint8_t RESERVED_11[4]; - __IO uint32_t PLL0CLKSEL; /**< PLL0 clock source select, offset: 0x290 */ - __IO uint32_t PLL1CLKSEL; /**< PLL1 clock source select, offset: 0x294 */ - uint8_t RESERVED_12[12]; - __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ - __IO uint32_t USB0CLKSEL; /**< FS USB clock source select, offset: 0x2A8 */ - uint8_t RESERVED_13[4]; - union { /* offset: 0x2B0 */ - struct { /* offset: 0x2B0 */ - __IO uint32_t FCCLKSEL0; /**< Flexcomm Interface 0 clock source select for Fractional Rate Divider, offset: 0x2B0 */ - __IO uint32_t FCCLKSEL1; /**< Flexcomm Interface 1 clock source select for Fractional Rate Divider, offset: 0x2B4 */ - __IO uint32_t FCCLKSEL2; /**< Flexcomm Interface 2 clock source select for Fractional Rate Divider, offset: 0x2B8 */ - __IO uint32_t FCCLKSEL3; /**< Flexcomm Interface 3 clock source select for Fractional Rate Divider, offset: 0x2BC */ - __IO uint32_t FCCLKSEL4; /**< Flexcomm Interface 4 clock source select for Fractional Rate Divider, offset: 0x2C0 */ - __IO uint32_t FCCLKSEL5; /**< Flexcomm Interface 5 clock source select for Fractional Rate Divider, offset: 0x2C4 */ - __IO uint32_t FCCLKSEL6; /**< Flexcomm Interface 6 clock source select for Fractional Rate Divider, offset: 0x2C8 */ - __IO uint32_t FCCLKSEL7; /**< Flexcomm Interface 7 clock source select for Fractional Rate Divider, offset: 0x2CC */ - } FCCLKSEL; - __IO uint32_t FCCLKSELX[8]; /**< Peripheral reset control register, array offset: 0x2B0, array step: 0x4 */ - }; - __IO uint32_t HSLSPICLKSEL; /**< HS LSPI clock source select, offset: 0x2D0 */ - uint8_t RESERVED_14[12]; - __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ - uint8_t RESERVED_15[12]; - __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ - uint8_t RESERVED_16[4]; - __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */ - uint8_t RESERVED_17[4]; - __IO uint32_t SYSTICKCLKDIV0; /**< System Tick Timer divider for CPU0, offset: 0x300 */ - __IO uint32_t SYSTICKCLKDIV1; /**< System Tick Timer divider for CPU1, offset: 0x304 */ - __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */ - uint8_t RESERVED_18[20]; - union { /* offset: 0x320 */ - struct { /* offset: 0x320 */ - __IO uint32_t FLEXFRG0CTRL; /**< Fractional rate divider for flexcomm 0, offset: 0x320 */ - __IO uint32_t FLEXFRG1CTRL; /**< Fractional rate divider for flexcomm 1, offset: 0x324 */ - __IO uint32_t FLEXFRG2CTRL; /**< Fractional rate divider for flexcomm 2, offset: 0x328 */ - __IO uint32_t FLEXFRG3CTRL; /**< Fractional rate divider for flexcomm 3, offset: 0x32C */ - __IO uint32_t FLEXFRG4CTRL; /**< Fractional rate divider for flexcomm 4, offset: 0x330 */ - __IO uint32_t FLEXFRG5CTRL; /**< Fractional rate divider for flexcomm 5, offset: 0x334 */ - __IO uint32_t FLEXFRG6CTRL; /**< Fractional rate divider for flexcomm 6, offset: 0x338 */ - __IO uint32_t FLEXFRG7CTRL; /**< Fractional rate divider for flexcomm 7, offset: 0x33C */ - } FLEXFRGCTRL; - __IO uint32_t FLEXFRGXCTRL[8]; /**< Peripheral reset control register, array offset: 0x320, array step: 0x4 */ - }; - uint8_t RESERVED_19[64]; - __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */ - __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ - __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */ - __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */ - uint8_t RESERVED_20[4]; - __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ - __IO uint32_t USB0CLKDIV; /**< USB0 Clock divider, offset: 0x398 */ - uint8_t RESERVED_21[16]; - __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ - uint8_t RESERVED_22[4]; - __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ - uint8_t RESERVED_23[4]; - __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */ - uint8_t RESERVED_24[4]; - __IO uint32_t PLL0CLKDIV; /**< PLL0 clock divider, offset: 0x3C4 */ - uint8_t RESERVED_25[52]; - __IO uint32_t CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */ - __IO uint32_t FMCCR; /**< FMC configuration register, offset: 0x400 */ - uint8_t RESERVED_26[8]; - __IO uint32_t USB0NEEDCLKCTRL; /**< USB0 need clock control, offset: 0x40C */ - __I uint32_t USB0NEEDCLKSTAT; /**< USB0 need clock status, offset: 0x410 */ - uint8_t RESERVED_27[8]; - __O uint32_t FMCFLUSH; /**< FMCflush control, offset: 0x41C */ - __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */ - __IO uint32_t USB1NEEDCLKCTRL; /**< USB1 need clock control, offset: 0x424 */ - __I uint32_t USB1NEEDCLKSTAT; /**< USB1 need clock status, offset: 0x428 */ - uint8_t RESERVED_28[52]; - __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */ - uint8_t RESERVED_29[252]; - __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */ - __I uint32_t PLL1STAT; /**< PLL1 550m status, offset: 0x564 */ - __IO uint32_t PLL1NDEC; /**< PLL1 550m N divider, offset: 0x568 */ - __IO uint32_t PLL1MDEC; /**< PLL1 550m M divider, offset: 0x56C */ - __IO uint32_t PLL1PDEC; /**< PLL1 550m P divider, offset: 0x570 */ - uint8_t RESERVED_30[12]; - __IO uint32_t PLL0CTRL; /**< PLL0 550m control, offset: 0x580 */ - __I uint32_t PLL0STAT; /**< PLL0 550m status, offset: 0x584 */ - __IO uint32_t PLL0NDEC; /**< PLL0 550m N divider, offset: 0x588 */ - __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */ - __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */ - __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */ - uint8_t RESERVED_31[364]; - __IO uint32_t FUNCRETENTIONCTRL; /**< Functional retention control register, offset: 0x704 */ - uint8_t RESERVED_32[248]; - __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ - __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ - uint8_t RESERVED_33[4]; - __I uint32_t CPSTAT; /**< CPU Status, offset: 0x80C */ - uint8_t RESERVED_34[520]; - __IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures, offset: 0xA18 */ - uint8_t RESERVED_35[244]; - __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */ - __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */ - uint8_t RESERVED_36[748]; - __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */ - __IO uint32_t GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */ - uint8_t RESERVED_37[404]; - __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers., offset: 0xFA0 */ - __IO uint32_t DEBUG_FEATURES; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control., offset: 0xFA4 */ - __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register., offset: 0xFA8 */ - uint8_t RESERVED_38[16]; - __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index., offset: 0xFBC */ - __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug authentication BEACON register, offset: 0xFC0 */ - uint8_t RESERVED_39[16]; - __IO uint32_t CPUCFG; /**< CPUs configuration register, offset: 0xFD4 */ - uint8_t RESERVED_40[32]; - __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ - __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */ -} SYSCON_Type; - -/* ---------------------------------------------------------------------------- - -- SYSCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Register_Masks SYSCON Register Masks - * @{ - */ - -/*! @name MEMORYREMAP - Memory Remap control register */ -/*! @{ */ - -#define SYSCON_MEMORYREMAP_MAP_MASK (0x3U) -#define SYSCON_MEMORYREMAP_MAP_SHIFT (0U) -/*! MAP - Select the location of the vector table :. - * 0b00..Vector Table in ROM. - * 0b01..Vector Table in RAM. - * 0b10..Vector Table in Flash. - * 0b11..Vector Table in Flash. - */ -#define SYSCON_MEMORYREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK) -/*! @} */ - -/*! @name AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest */ -/*! @{ */ - -#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK (0x3U) -#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT (0U) -/*! PRI_CPU0_CBUS - CPU0 C-AHB bus. - */ -#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK (0xCU) -#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT (2U) -/*! PRI_CPU0_SBUS - CPU0 S-AHB bus. - */ -#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK (0x30U) -#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT (4U) -/*! PRI_CPU1_CBUS - CPU1 C-AHB bus. - */ -#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK (0xC0U) -#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT (6U) -/*! PRI_CPU1_SBUS - CPU1 S-AHB bus. - */ -#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_USB_FS_MASK (0x300U) -#define SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT (8U) -/*! PRI_USB_FS - USB-FS.(USB0) - */ -#define SYSCON_AHBMATPRIO_PRI_USB_FS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0xC00U) -#define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (10U) -/*! PRI_SDMA0 - DMA0 controller priority. - */ -#define SYSCON_AHBMATPRIO_PRI_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK) - -#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0x30000U) -#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (16U) -/*! PRI_SDIO - SDIO. - */ -#define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK) - -#define SYSCON_AHBMATPRIO_PRI_PQ_MASK (0xC0000U) -#define SYSCON_AHBMATPRIO_PRI_PQ_SHIFT (18U) -/*! PRI_PQ - PQ (HW Accelerator). - */ -#define SYSCON_AHBMATPRIO_PRI_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PQ_MASK) - -#define SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK (0x300000U) -#define SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT (20U) -/*! PRI_HASH_AES - HASH_AES. - */ -#define SYSCON_AHBMATPRIO_PRI_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT)) & SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK) - -#define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK (0xC00000U) -#define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT (22U) -/*! PRI_USB_HS - USB-HS.(USB1) - */ -#define SYSCON_AHBMATPRIO_PRI_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK) - -#define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0x3000000U) -#define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (24U) -/*! PRI_SDMA1 - DMA1 controller priority. - */ -#define SYSCON_AHBMATPRIO_PRI_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK) -/*! @} */ - -/*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */ -/*! @{ */ - -#define SYSCON_CPU0STCKCAL_TENMS_MASK (0xFFFFFFU) -#define SYSCON_CPU0STCKCAL_TENMS_SHIFT (0U) -/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value - * reads as zero, the calibration value is not known. - */ -#define SYSCON_CPU0STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK) - -#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) -/*! SKEW - Initial value for the Systick timer. - */ -#define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) - -#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) -/*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference - * clock provided; 1 = no reference clock provided. - */ -#define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */ -/*! @{ */ - -#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) -#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) -/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the - * value reads as zero, the calibration value is not known. - */ -#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) - -#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) -/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. - */ -#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) - -#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) -/*! NOREF - Initial value for the Systick timer. - */ -#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name CPU1STCKCAL - System tick calibration for CPU1 */ -/*! @{ */ - -#define SYSCON_CPU1STCKCAL_TENMS_MASK (0xFFFFFFU) -#define SYSCON_CPU1STCKCAL_TENMS_SHIFT (0U) -/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value - * reads as zero, the calibration value is not known. - */ -#define SYSCON_CPU1STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_TENMS_SHIFT)) & SYSCON_CPU1STCKCAL_TENMS_MASK) - -#define SYSCON_CPU1STCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU1STCKCAL_SKEW_SHIFT (24U) -/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. - */ -#define SYSCON_CPU1STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_SKEW_SHIFT)) & SYSCON_CPU1STCKCAL_SKEW_MASK) - -#define SYSCON_CPU1STCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU1STCKCAL_NOREF_SHIFT (25U) -/*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference - * clock provided; 1 = no reference clock provided. - */ -#define SYSCON_CPU1STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_NOREF_SHIFT)) & SYSCON_CPU1STCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name NMISRC - NMI Source Select */ -/*! @{ */ - -#define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU) -#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) -/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0. - */ -#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) - -#define SYSCON_NMISRC_IRQCPU1_MASK (0x3F00U) -#define SYSCON_NMISRC_IRQCPU1_SHIFT (8U) -/*! IRQCPU1 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1, if enabled by NMIENCPU1. - */ -#define SYSCON_NMISRC_IRQCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU1_SHIFT)) & SYSCON_NMISRC_IRQCPU1_MASK) - -#define SYSCON_NMISRC_NMIENCPU1_MASK (0x40000000U) -#define SYSCON_NMISRC_NMIENCPU1_SHIFT (30U) -/*! NMIENCPU1 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU1. - */ -#define SYSCON_NMISRC_NMIENCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU1_SHIFT)) & SYSCON_NMISRC_NMIENCPU1_MASK) - -#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) -#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) -/*! NMIENCPU0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. - */ -#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) -/*! @} */ - -/*! @name PRESETCTRL0 - Peripheral reset control 0 */ -/*! @{ */ - -#define SYSCON_PRESETCTRL0_ROM_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL0_ROM_RST_SHIFT (1U) -/*! ROM_RST - ROM reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_ROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ROM_RST_SHIFT)) & SYSCON_PRESETCTRL0_ROM_RST_MASK) - -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U) -/*! SRAM_CTRL1_RST - SRAM Controller 1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK) - -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U) -/*! SRAM_CTRL2_RST - SRAM Controller 2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK) - -#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK (0x20U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT (5U) -/*! SRAM_CTRL3_RST - SRAM Controller 3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK) - -#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK (0x40U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT (6U) -/*! SRAM_CTRL4_RST - SRAM Controller 4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK) - -#define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U) -/*! FLASH_RST - Flash controller reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK) - -#define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U) -/*! FMC_RST - FMC controller reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK) - -#define SYSCON_PRESETCTRL0_MUX_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL0_MUX_RST_SHIFT (11U) -/*! MUX_RST - Input Mux reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK) - -#define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U) -/*! IOCON_RST - I/O controller reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK) - -#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U) -/*! GPIO0_RST - GPIO0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) - -#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U) -/*! GPIO1_RST - GPIO1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) - -#define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (16U) -/*! GPIO2_RST - GPIO2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK) - -#define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (17U) -/*! GPIO3_RST - GPIO3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK) - -#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U) -/*! PINT_RST - Pin interrupt (PINT) reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) - -#define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U) -/*! GINT_RST - Group interrupt (GINT) reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK) - -#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U) -#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U) -/*! DMA0_RST - DMA0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) - -#define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U) -#define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U) -/*! CRCGEN_RST - CRCGEN reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_CRCGEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK) - -#define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U) -/*! WWDT_RST - Watchdog Timer reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK) - -#define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U) -#define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U) -/*! RTC_RST - Real Time Clock (RTC) reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK) - -#define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U) -#define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U) -/*! MAILBOX_RST - Inter CPU communication Mailbox reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK) - -#define SYSCON_PRESETCTRL0_ADC_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL0_ADC_RST_SHIFT (27U) -/*! ADC_RST - ADC reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_ADC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRL1 - Peripheral reset control 1 */ -/*! @{ */ - -#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) -#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) -/*! MRT_RST - MRT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) - -#define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT (1U) -/*! OSTIMER_RST - OS Event Timer reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_OSTIMER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK) - -#define SYSCON_PRESETCTRL1_SCT_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL1_SCT_RST_SHIFT (2U) -/*! SCT_RST - SCT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_SCT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT_RST_MASK) - -#define SYSCON_PRESETCTRL1_SCTIPU_RST_MASK (0x40U) -#define SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT (6U) -/*! SCTIPU_RST - SCTIPU reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_SCTIPU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCTIPU_RST_MASK) - -#define SYSCON_PRESETCTRL1_UTICK_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT (10U) -/*! UTICK_RST - UTICK reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) -/*! FC0_RST - FC0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) -#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) -/*! FC1_RST - FC1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) -/*! FC2_RST - FC2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) -/*! FC3_RST - FC3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) -/*! FC4_RST - FC4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) -/*! FC5_RST - FC5 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) -/*! FC6_RST - FC6 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) - -#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) -/*! FC7_RST - FC7 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) - -#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) -/*! TIMER2_RST - Timer 2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) - -#define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK (0x2000000U) -#define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT (25U) -/*! USB0_DEV_RST - USB0 DEV reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_USB0_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK) - -#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) -#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) -/*! TIMER0_RST - Timer 0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) - -#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) -/*! TIMER1_RST - Timer 1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRL2 - Peripheral reset control 2 */ -/*! @{ */ - -#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) -/*! DMA1_RST - DMA1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) - -#define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U) -/*! COMP_RST - Comparator reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_COMP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK) - -#define SYSCON_PRESETCTRL2_SDIO_RST_MASK (0x8U) -#define SYSCON_PRESETCTRL2_SDIO_RST_SHIFT (3U) -/*! SDIO_RST - SDIO reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_SDIO_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK (0x10U) -#define SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT (4U) -/*! USB1_HOST_RST - USB1 Host reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_HOST_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK (0x20U) -#define SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT (5U) -/*! USB1_DEV_RST - USB1 dev reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK (0x40U) -#define SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT (6U) -/*! USB1_RAM_RST - USB1 RAM reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT (7U) -/*! USB1_PHY_RST - USB1 PHY reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK) - -#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) -/*! FREQME_RST - Frequency meter reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) - -#define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U) -/*! RNG_RST - RNG reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK) - -#define SYSCON_PRESETCTRL2_SYSCTL_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT (15U) -/*! SYSCTL_RST - SYSCTL Block reset. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_SYSCTL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT)) & SYSCON_PRESETCTRL2_SYSCTL_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT (16U) -/*! USB0_HOSTM_RST - USB0 Host Master reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK) - -#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT (17U) -/*! USB0_HOSTS_RST - USB0 Host Slave reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK) - -#define SYSCON_PRESETCTRL2_HASH_AES_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT (18U) -/*! HASH_AES_RST - HASH_AES reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_HASH_AES_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH_AES_RST_MASK) - -#define SYSCON_PRESETCTRL2_PQ_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL2_PQ_RST_SHIFT (19U) -/*! PQ_RST - Power Quad reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_PQ_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK) - -#define SYSCON_PRESETCTRL2_PLULUT_RST_MASK (0x100000U) -#define SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT (20U) -/*! PLULUT_RST - PLU LUT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_PLULUT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLULUT_RST_MASK) - -#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) -#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) -/*! TIMER3_RST - Timer 3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) - -#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) -/*! TIMER4_RST - Timer 4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) - -#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) -#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) -/*! PUF_RST - PUF reset control reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) - -#define SYSCON_PRESETCTRL2_CASPER_RST_MASK (0x1000000U) -#define SYSCON_PRESETCTRL2_CASPER_RST_SHIFT (24U) -/*! CASPER_RST - Casper reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_CASPER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CASPER_RST_SHIFT)) & SYSCON_PRESETCTRL2_CASPER_RST_MASK) - -#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT (27U) -/*! ANALOG_CTRL_RST - analog control reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK) - -#define SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK (0x10000000U) -#define SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT (28U) -/*! HS_LSPI_RST - HS LSPI reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_HS_LSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK) - -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U) -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U) -/*! GPIO_SEC_RST - GPIO secure reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK) - -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U) -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U) -/*! GPIO_SEC_INT_RST - GPIO secure int reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRLX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_PRESETCTRLX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_PRESETCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLX_DATA_SHIFT)) & SYSCON_PRESETCTRLX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLX */ -#define SYSCON_PRESETCTRLX_COUNT (3U) - -/*! @name PRESETCTRLSET - Peripheral reset control set register */ -/*! @{ */ - -#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLSET */ -#define SYSCON_PRESETCTRLSET_COUNT (3U) - -/*! @name PRESETCTRLCLR - Peripheral reset control clear register */ -/*! @{ */ - -#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLCLR */ -#define SYSCON_PRESETCTRLCLR_COUNT (3U) - -/*! @name SWR_RESET - generate a software_reset */ -/*! @{ */ - -#define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU) -#define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U) -/*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset. - * 0b01011010000000000000000000000001..Generate a software reset. - * 0b00000000000000000000000000000000..Bloc is not reset. - */ -#define SYSCON_SWR_RESET_SWR_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL0 - AHB Clock control 0 */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) -#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) -/*! ROM - Enables the clock for the ROM. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) - -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U) -/*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK) - -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U) -/*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK) - -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK (0x20U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT (5U) -/*! SRAM_CTRL3 - Enables the clock for the SRAM Controller 3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK) - -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK (0x40U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT (6U) -/*! SRAM_CTRL4 - Enables the clock for the SRAM Controller 4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK) - -#define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U) -#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U) -/*! FLASH - Enables the clock for the Flash controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK) - -#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U) -#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U) -/*! FMC - Enables the clock for the FMC controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) - -#define SYSCON_AHBCLKCTRL0_MUX_MASK (0x800U) -#define SYSCON_AHBCLKCTRL0_MUX_SHIFT (11U) -/*! MUX - Enables the clock for the Input Mux. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_MUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK) - -#define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U) -/*! IOCON - Enables the clock for the I/O controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK) - -#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U) -/*! GPIO0 - Enables the clock for the GPIO0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) - -#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U) -/*! GPIO1 - Enables the clock for the GPIO1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) - -#define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (16U) -/*! GPIO2 - Enables the clock for the GPIO2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK) - -#define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (17U) -/*! GPIO3 - Enables the clock for the GPIO3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK) - -#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U) -/*! PINT - Enables the clock for the Pin interrupt (PINT). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) - -#define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U) -/*! GINT - Enables the clock for the Group interrupt (GINT). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK) - -#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U) -#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U) -/*! DMA0 - Enables the clock for the DMA0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) - -#define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U) -#define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U) -/*! CRCGEN - Enables the clock for the CRCGEN. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK) - -#define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U) -/*! WWDT - Enables the clock for the Watchdog Timer. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK) - -#define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U) -#define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U) -/*! RTC - Enables the clock for the Real Time Clock (RTC). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK) - -#define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U) -/*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK) - -#define SYSCON_AHBCLKCTRL0_ADC_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL0_ADC_SHIFT (27U) -/*! ADC - Enables the clock for the ADC. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL1 - AHB Clock control 1 */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) -#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) -/*! MRT - Enables the clock for the MRT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) - -#define SYSCON_AHBCLKCTRL1_OSTIMER_MASK (0x2U) -#define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT (1U) -/*! OSTIMER - Enables the clock for the OS Event Timer. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK) - -#define SYSCON_AHBCLKCTRL1_SCT_MASK (0x4U) -#define SYSCON_AHBCLKCTRL1_SCT_SHIFT (2U) -/*! SCT - Enables the clock for the SCT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_SCT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT_MASK) - -#define SYSCON_AHBCLKCTRL1_UTICK_MASK (0x400U) -#define SYSCON_AHBCLKCTRL1_UTICK_SHIFT (10U) -/*! UTICK - Enables the clock for the UTICK. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK) - -#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) -#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) -/*! FC0 - Enables the clock for the FC0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) - -#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) -#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) -/*! FC1 - Enables the clock for the FC1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) - -#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) -/*! FC2 - Enables the clock for the FC2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) - -#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) -/*! FC3 - Enables the clock for the FC3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) - -#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) -/*! FC4 - Enables the clock for the FC4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) - -#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) -/*! FC5 - Enables the clock for the FC5. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) - -#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) -/*! FC6 - Enables the clock for the FC6. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) - -#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) -/*! FC7 - Enables the clock for the FC7. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) - -#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) -/*! TIMER2 - Enables the clock for the Timer 2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) - -#define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK (0x2000000U) -#define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT (25U) -/*! USB0_DEV - Enables the clock for the USB0 DEV. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_USB0_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK) - -#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) -/*! TIMER0 - Enables the clock for the Timer 0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) - -#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) -/*! TIMER1 - Enables the clock for the Timer 1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL2 - AHB Clock control 2 */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) -#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) -/*! DMA1 - Enables the clock for the DMA1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) - -#define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U) -#define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U) -/*! COMP - Enables the clock for the Comparator. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK) - -#define SYSCON_AHBCLKCTRL2_SDIO_MASK (0x8U) -#define SYSCON_AHBCLKCTRL2_SDIO_SHIFT (3U) -/*! SDIO - Enables the clock for the SDIO. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL2_SDIO_MASK) - -#define SYSCON_AHBCLKCTRL2_USB1_HOST_MASK (0x10U) -#define SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT (4U) -/*! USB1_HOST - Enables the clock for the USB1 Host. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_HOST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_HOST_MASK) - -#define SYSCON_AHBCLKCTRL2_USB1_DEV_MASK (0x20U) -#define SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT (5U) -/*! USB1_DEV - Enables the clock for the USB1 dev. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_DEV_MASK) - -#define SYSCON_AHBCLKCTRL2_USB1_RAM_MASK (0x40U) -#define SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT (6U) -/*! USB1_RAM - Enables the clock for the USB1 RAM. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_RAM_MASK) - -#define SYSCON_AHBCLKCTRL2_USB1_PHY_MASK (0x80U) -#define SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT (7U) -/*! USB1_PHY - Enables the clock for the USB1 PHY. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_PHY_MASK) - -#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) -#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) -/*! FREQME - Enables the clock for the Frequency meter. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) - -#define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U) -/*! RNG - Enables the clock for the RNG. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK) - -#define SYSCON_AHBCLKCTRL2_SYSCTL_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT (15U) -/*! SYSCTL - SYSCTL block clock. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_SYSCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT)) & SYSCON_AHBCLKCTRL2_SYSCTL_MASK) - -#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT (16U) -/*! USB0_HOSTM - Enables the clock for the USB0 Host Master. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK) - -#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT (17U) -/*! USB0_HOSTS - Enables the clock for the USB0 Host Slave. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK) - -#define SYSCON_AHBCLKCTRL2_HASH_AES_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT (18U) -/*! HASH_AES - Enables the clock for the HASH_AES. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH_AES_MASK) - -#define SYSCON_AHBCLKCTRL2_PQ_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL2_PQ_SHIFT (19U) -/*! PQ - Enables the clock for the Power Quad. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK) - -#define SYSCON_AHBCLKCTRL2_PLULUT_MASK (0x100000U) -#define SYSCON_AHBCLKCTRL2_PLULUT_SHIFT (20U) -/*! PLULUT - Enables the clock for the PLU LUT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PLULUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLULUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLULUT_MASK) - -#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) -#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) -/*! TIMER3 - Enables the clock for the Timer 3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) - -#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) -/*! TIMER4 - Enables the clock for the Timer 4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) - -#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) -#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) -/*! PUF - Enables the clock for the PUF reset control. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) - -#define SYSCON_AHBCLKCTRL2_CASPER_MASK (0x1000000U) -#define SYSCON_AHBCLKCTRL2_CASPER_SHIFT (24U) -/*! CASPER - Enables the clock for the Casper. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CASPER_SHIFT)) & SYSCON_AHBCLKCTRL2_CASPER_MASK) - -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U) -/*! ANALOG_CTRL - Enables the clock for the analog control. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK) - -#define SYSCON_AHBCLKCTRL2_HS_LSPI_MASK (0x10000000U) -#define SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT (28U) -/*! HS_LSPI - Enables the clock for the HS LSPI. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_LSPI_MASK) - -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U) -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U) -/*! GPIO_SEC - Enables the clock for the GPIO secure. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK) - -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U) -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U) -/*! GPIO_SEC_INT - Enables the clock for the GPIO secure int. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK) -/*! @} */ - -/*! @name AHBCLKCTRLX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRLX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_AHBCLKCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLX_DATA_SHIFT)) & SYSCON_AHBCLKCTRLX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLX */ -#define SYSCON_AHBCLKCTRLX_COUNT (3U) - -/*! @name AHBCLKCTRLSET - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLSET */ -#define SYSCON_AHBCLKCTRLSET_COUNT (3U) - -/*! @name AHBCLKCTRLCLR - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLCLR */ -#define SYSCON_AHBCLKCTRLCLR_COUNT (3U) - -/*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) -/*! SEL - System Tick Timer for CPU0 source select. - * 0b000..System Tick 0 divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKSEL1 - System Tick Timer for CPU1 source select */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKSEL1_SEL_MASK (0x7U) -#define SYSCON_SYSTICKCLKSEL1_SEL_SHIFT (0U) -/*! SEL - System Tick Timer for CPU1 source select. - * 0b000..System Tick 1 divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SYSTICKCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL1_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL1_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKSELX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKSELX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_SYSTICKCLKSELX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_SYSTICKCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSELX_DATA_SHIFT)) & SYSCON_SYSTICKCLKSELX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_SYSTICKCLKSELX */ -#define SYSCON_SYSTICKCLKSELX_COUNT (2U) - -/*! @name TRACECLKSEL - Trace clock source select */ -/*! @{ */ - -#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) -#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) -/*! SEL - Trace clock source select. - * 0b000..Trace divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL0 - CTimer 0 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL0_SEL_SHIFT (0U) -/*! SEL - CTimer 0 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL0_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL1 - CTimer 1 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL1_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL1_SEL_SHIFT (0U) -/*! SEL - CTimer 1 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL1_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL1_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL2 - CTimer 2 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL2_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL2_SEL_SHIFT (0U) -/*! SEL - CTimer 2 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL2_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL2_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL3 - CTimer 3 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL3_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL3_SEL_SHIFT (0U) -/*! SEL - CTimer 3 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL3_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL3_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL4 - CTimer 4 clock source select */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSEL4_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL4_SEL_SHIFT (0U) -/*! SEL - CTimer 4 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL4_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL4_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSELX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_CTIMERCLKSELX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_CTIMERCLKSELX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_CTIMERCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSELX_DATA_SHIFT)) & SYSCON_CTIMERCLKSELX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_CTIMERCLKSELX */ -#define SYSCON_CTIMERCLKSELX_COUNT (5U) - -/*! @name MAINCLKSELA - Main clock A source select */ -/*! @{ */ - -#define SYSCON_MAINCLKSELA_SEL_MASK (0x7U) -#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) -/*! SEL - Main clock A source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..Reserved. - * 0b101..Reserved. - * 0b110..Reserved. - * 0b111..Reserved. - */ -#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) -/*! @} */ - -/*! @name MAINCLKSELB - Main clock source select */ -/*! @{ */ - -#define SYSCON_MAINCLKSELB_SEL_MASK (0x7U) -#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) -/*! SEL - Main clock source select. - * 0b000..Main Clock A. - * 0b001..PLL0 clock. - * 0b010..PLL1 clock. - * 0b011..Oscillator 32 kHz clock. - * 0b100..Reserved. - * 0b101..Reserved. - * 0b110..Reserved. - * 0b111..Reserved. - */ -#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) -/*! @} */ - -/*! @name CLKOUTSEL - CLKOUT clock source select */ -/*! @{ */ - -#define SYSCON_CLKOUTSEL_SEL_MASK (0x7U) -#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) -/*! SEL - CLKOUT clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..CLKIN clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..PLL1 clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) -/*! @} */ - -/*! @name PLL0CLKSEL - PLL0 clock source select */ -/*! @{ */ - -#define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U) -#define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U) -/*! SEL - PLL0 clock source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..Oscillator 32kHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_PLL0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name PLL1CLKSEL - PLL1 clock source select */ -/*! @{ */ - -#define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U) -#define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U) -/*! SEL - PLL1 clock source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..Oscillator 32kHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_PLL1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name ADCCLKSEL - ADC clock source select */ -/*! @{ */ - -#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) -#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) -/*! SEL - ADC clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..FRO 96 MHz clock. - * 0b011..Reserved. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name USB0CLKSEL - FS USB clock source select */ -/*! @{ */ - -#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) -#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) -/*! SEL - FS USB clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..PLL1 clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL0_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL0_SEL_SHIFT)) & SYSCON_FCCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL1_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL1_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL1_SEL_SHIFT)) & SYSCON_FCCLKSEL1_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL2_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL2_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL2_SEL_SHIFT)) & SYSCON_FCCLKSEL2_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL3_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL3_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL3_SEL_SHIFT)) & SYSCON_FCCLKSEL3_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL4_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL4_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL4_SEL_SHIFT)) & SYSCON_FCCLKSEL4_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL5_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL5_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL5_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL5_SEL_SHIFT)) & SYSCON_FCCLKSEL5_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL6_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL6_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL6_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL6_SEL_SHIFT)) & SYSCON_FCCLKSEL6_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider */ -/*! @{ */ - -#define SYSCON_FCCLKSEL7_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL7_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL7_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL7_SEL_SHIFT)) & SYSCON_FCCLKSEL7_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSELX - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_FCCLKSELX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_FCCLKSELX_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_FCCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSELX_DATA_SHIFT)) & SYSCON_FCCLKSELX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_FCCLKSELX */ -#define SYSCON_FCCLKSELX_COUNT (8U) - -/*! @name HSLSPICLKSEL - HS LSPI clock source select */ -/*! @{ */ - -#define SYSCON_HSLSPICLKSEL_SEL_MASK (0x7U) -#define SYSCON_HSLSPICLKSEL_SEL_SHIFT (0U) -/*! SEL - HS LSPI clock source select. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..No clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_HSLSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HSLSPICLKSEL_SEL_SHIFT)) & SYSCON_HSLSPICLKSEL_SEL_MASK) -/*! @} */ - -/*! @name MCLKCLKSEL - MCLK clock source select */ -/*! @{ */ - -#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) -#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) -/*! SEL - MCLK clock source select. - * 0b000..FRO 96 MHz clock. - * 0b001..PLL0 clock. - * 0b010..Reserved. - * 0b011..Reserved. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SCTCLKSEL - SCTimer/PWM clock source select */ -/*! @{ */ - -#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) -#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) -/*! SEL - SCTimer/PWM clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..CLKIN clock. - * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..MCLK clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SDIOCLKSEL - SDIO clock source select */ -/*! @{ */ - -#define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U) -#define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U) -/*! SEL - SDIO clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..PLL1 clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKDIV0_DIV_MASK (0xFFU) -#define SYSCON_SYSTICKCLKDIV0_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_SYSTICKCLKDIV0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV0_DIV_MASK) - -#define SYSCON_SYSTICKCLKDIV0_RESET_MASK (0x20000000U) -#define SYSCON_SYSTICKCLKDIV0_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SYSTICKCLKDIV0_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV0_RESET_MASK) - -#define SYSCON_SYSTICKCLKDIV0_HALT_MASK (0x40000000U) -#define SYSCON_SYSTICKCLKDIV0_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SYSTICKCLKDIV0_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV0_HALT_MASK) - -#define SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK (0x80000000U) -#define SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SYSTICKCLKDIV0_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK) -/*! @} */ - -/*! @name SYSTICKCLKDIV1 - System Tick Timer divider for CPU1 */ -/*! @{ */ - -#define SYSCON_SYSTICKCLKDIV1_DIV_MASK (0xFFU) -#define SYSCON_SYSTICKCLKDIV1_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_SYSTICKCLKDIV1_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV1_DIV_MASK) - -#define SYSCON_SYSTICKCLKDIV1_RESET_MASK (0x20000000U) -#define SYSCON_SYSTICKCLKDIV1_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SYSTICKCLKDIV1_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV1_RESET_MASK) - -#define SYSCON_SYSTICKCLKDIV1_HALT_MASK (0x40000000U) -#define SYSCON_SYSTICKCLKDIV1_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SYSTICKCLKDIV1_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV1_HALT_MASK) - -#define SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK (0x80000000U) -#define SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SYSTICKCLKDIV1_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK) -/*! @} */ - -/*! @name TRACECLKDIV - TRACE clock divider */ -/*! @{ */ - -#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) -#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) - -#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) - -#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) - -#define SYSCON_TRACECLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_TRACECLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_TRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_TRACECLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 */ -/*! @{ */ - -#define SYSCON_FLEXFRG0CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG0CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG0CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG0CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG0CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG0CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG0CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG0CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 */ -/*! @{ */ - -#define SYSCON_FLEXFRG1CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG1CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG1CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG1CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG1CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG1CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG1CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG1CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 */ -/*! @{ */ - -#define SYSCON_FLEXFRG2CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG2CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG2CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG2CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG2CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG2CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG2CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG2CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 */ -/*! @{ */ - -#define SYSCON_FLEXFRG3CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG3CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG3CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG3CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG3CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG3CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG3CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG3CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 */ -/*! @{ */ - -#define SYSCON_FLEXFRG4CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG4CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG4CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG4CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG4CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG4CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG4CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG4CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 */ -/*! @{ */ - -#define SYSCON_FLEXFRG5CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG5CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG5CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG5CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG5CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG5CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG5CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG5CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 */ -/*! @{ */ - -#define SYSCON_FLEXFRG6CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG6CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG6CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG6CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG6CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG6CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG6CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG6CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 */ -/*! @{ */ - -#define SYSCON_FLEXFRG7CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG7CTRL_DIV_SHIFT (0U) -/*! DIV - Denominator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG7CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG7CTRL_DIV_MASK) - -#define SYSCON_FLEXFRG7CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG7CTRL_MULT_SHIFT (8U) -/*! MULT - Numerator of the fractional rate divider. - */ -#define SYSCON_FLEXFRG7CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG7CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRGXCTRL - Peripheral reset control register */ -/*! @{ */ - -#define SYSCON_FLEXFRGXCTRL_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_FLEXFRGXCTRL_DATA_SHIFT (0U) -/*! DATA - Data array value - */ -#define SYSCON_FLEXFRGXCTRL_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRGXCTRL_DATA_SHIFT)) & SYSCON_FLEXFRGXCTRL_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_FLEXFRGXCTRL */ -#define SYSCON_FLEXFRGXCTRL_COUNT (8U) - -/*! @name AHBCLKDIV - System clock divider */ -/*! @{ */ - -#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) - -#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) - -#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) - -#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name CLKOUTDIV - CLKOUT clock divider */ -/*! @{ */ - -#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) -#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) - -#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) -#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) - -#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) -#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) - -#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name FROHFDIV - FRO_HF (96MHz) clock divider */ -/*! @{ */ - -#define SYSCON_FROHFDIV_DIV_MASK (0xFFU) -#define SYSCON_FROHFDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) - -#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U) -#define SYSCON_FROHFDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK) - -#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) -#define SYSCON_FROHFDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) - -#define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_FROHFDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name WDTCLKDIV - WDT clock divider */ -/*! @{ */ - -#define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU) -#define SYSCON_WDTCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_WDTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK) - -#define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_WDTCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_WDTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK) - -#define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_WDTCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_WDTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK) - -#define SYSCON_WDTCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_WDTCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_WDTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_REQFLAG_SHIFT)) & SYSCON_WDTCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name ADCCLKDIV - ADC clock divider */ -/*! @{ */ - -#define SYSCON_ADCCLKDIV_DIV_MASK (0x7U) -#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) - -#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) - -#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) - -#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name USB0CLKDIV - USB0 Clock divider */ -/*! @{ */ - -#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) -#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) - -#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) - -#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) - -#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name MCLKDIV - I2S MCLK clock divider */ -/*! @{ */ - -#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_MCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) - -#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_MCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) - -#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_MCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) - -#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name SCTCLKDIV - SCT/PWM clock divider */ -/*! @{ */ - -#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) - -#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) - -#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) - -#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name SDIOCLKDIV - SDIO clock divider */ -/*! @{ */ - -#define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK) - -#define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK) - -#define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK) - -#define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name PLL0CLKDIV - PLL0 clock divider */ -/*! @{ */ - -#define SYSCON_PLL0CLKDIV_DIV_MASK (0xFFU) -#define SYSCON_PLL0CLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock divider value. - */ -#define SYSCON_PLL0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_DIV_SHIFT)) & SYSCON_PLL0CLKDIV_DIV_MASK) - -#define SYSCON_PLL0CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_PLL0CLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_PLL0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_RESET_SHIFT)) & SYSCON_PLL0CLKDIV_RESET_MASK) - -#define SYSCON_PLL0CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_PLL0CLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_PLL0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_HALT_SHIFT)) & SYSCON_PLL0CLKDIV_HALT_MASK) - -#define SYSCON_PLL0CLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_PLL0CLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_PLL0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_REQFLAG_SHIFT)) & SYSCON_PLL0CLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) */ -/*! @{ */ - -#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK (0xFFFFFFFFU) -#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT (0U) -/*! CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL). - * 0b00000000000000000000000000000001..update all clock configuration. - * 0b00000000000000000000000000000000..all hardware clock configruration are freeze. - */ -#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK) -/*! @} */ - -/*! @name FMCCR - FMC configuration register */ -/*! @{ */ - -#define SYSCON_FMCCR_FETCHCFG_MASK (0x3U) -#define SYSCON_FMCCR_FETCHCFG_SHIFT (0U) -/*! FETCHCFG - Instruction fetch configuration. - * 0b00..Instruction fetches from flash are not buffered. - * 0b01..One buffer is used for all instruction fetches. - * 0b10..All buffers may be used for instruction fetches. - */ -#define SYSCON_FMCCR_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCFG_SHIFT)) & SYSCON_FMCCR_FETCHCFG_MASK) - -#define SYSCON_FMCCR_DATACFG_MASK (0xCU) -#define SYSCON_FMCCR_DATACFG_SHIFT (2U) -/*! DATACFG - Data read configuration. - * 0b00..Data accesses from flash are not buffered. - * 0b01..One buffer is used for all data accesses. - * 0b10..All buffers can be used for data accesses. - */ -#define SYSCON_FMCCR_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACFG_SHIFT)) & SYSCON_FMCCR_DATACFG_MASK) - -#define SYSCON_FMCCR_ACCEL_MASK (0x10U) -#define SYSCON_FMCCR_ACCEL_SHIFT (4U) -/*! ACCEL - Acceleration enable. - * 0b0..Flash acceleration is disabled. - * 0b1..Flash acceleration is enabled. - */ -#define SYSCON_FMCCR_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK) - -#define SYSCON_FMCCR_PREFEN_MASK (0x20U) -#define SYSCON_FMCCR_PREFEN_SHIFT (5U) -/*! PREFEN - Prefetch enable. - * 0b0..No instruction prefetch is performed. - * 0b1..Instruction prefetch is enabled. - */ -#define SYSCON_FMCCR_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK) - -#define SYSCON_FMCCR_PREFOVR_MASK (0x40U) -#define SYSCON_FMCCR_PREFOVR_SHIFT (6U) -/*! PREFOVR - Prefetch override. - * 0b0..Any previously initiated prefetch will be completed. - * 0b1..Any previously initiated prefetch will be aborted, and the next flash line following the current - * execution address will be prefetched if not already buffered. - */ -#define SYSCON_FMCCR_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK) - -#define SYSCON_FMCCR_FLASHTIM_MASK (0xF000U) -#define SYSCON_FMCCR_FLASHTIM_SHIFT (12U) -/*! FLASHTIM - Flash memory access time. - * 0b0000..1 system clock flash access time (for system clock rates up to 11 MHz). - * 0b0001..2 system clocks flash access time (for system clock rates up to 22 MHz). - * 0b0010..3 system clocks flash access time (for system clock rates up to 33 MHz). - * 0b0011..4 system clocks flash access time (for system clock rates up to 44 MHz). - * 0b0100..5 system clocks flash access time (for system clock rates up to 55 MHz). - * 0b0101..6 system clocks flash access time (for system clock rates up to 66 MHz). - * 0b0110..7 system clocks flash access time (for system clock rates up to 77 MHz). - * 0b0111..8 system clocks flash access time (for system clock rates up to 88 MHz). - * 0b1000..9 system clocks flash access time (for system clock rates up to 100 MHz). - * 0b1001..10 system clocks flash access time (for system clock rates up to 115 MHz). - * 0b1010..11 system clocks flash access time (for system clock rates up to 130 MHz). - * 0b1011..12 system clocks flash access time (for system clock rates up to 150 MHz). - */ -#define SYSCON_FMCCR_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FLASHTIM_SHIFT)) & SYSCON_FMCCR_FLASHTIM_MASK) -/*! @} */ - -/*! @name USB0NEEDCLKCTRL - USB0 need clock control */ -/*! @{ */ - -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK (0x1U) -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT (0U) -/*! AP_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. - */ -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK) - -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK (0x2U) -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT (1U) -/*! POL_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. - * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. - * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK) - -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK (0x4U) -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT (2U) -/*! AP_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. - */ -#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK) - -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK (0x8U) -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT (3U) -/*! POL_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. - * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. - * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK) -/*! @} */ - -/*! @name USB0NEEDCLKSTAT - USB0 need clock status */ -/*! @{ */ - -#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) -#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) -/*! DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal status:. - * 0b1..USB0 Device clock is high. - * 0b0..USB0 Device clock is low. - */ -#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK) - -#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) -#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) -/*! HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal status:. - * 0b1..USB0 Host clock is high. - * 0b0..USB0 Host clock is low. - */ -#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK) -/*! @} */ - -/*! @name FMCFLUSH - FMCflush control */ -/*! @{ */ - -#define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U) -#define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U) -/*! FLUSH - Flush control - * 0b1..Flush the FMC buffer contents. - * 0b0..No action is performed. - */ -#define SYSCON_FMCFLUSH_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK) -/*! @} */ - -/*! @name MCLKIO - MCLK control */ -/*! @{ */ - -#define SYSCON_MCLKIO_MCLKIO_MASK (0x1U) -#define SYSCON_MCLKIO_MCLKIO_SHIFT (0U) -/*! MCLKIO - MCLK control. - * 0b0..input mode. - * 0b1..output mode. - */ -#define SYSCON_MCLKIO_MCLKIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK) -/*! @} */ - -/*! @name USB1NEEDCLKCTRL - USB1 need clock control */ -/*! @{ */ - -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK (0x1U) -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT (0U) -/*! AP_HS_DEV_NEEDCLK - USB1 Device need_clock signal control: - * 0b0..HOST_NEEDCLK is under hardware control. - * 0b1..HOST_NEEDCLK is forced high. - */ -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK) - -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK (0x2U) -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT (1U) -/*! POL_HS_DEV_NEEDCLK - USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt: - * 0b0..Falling edge of DEV_NEEDCLK triggers wake-up. - * 0b1..Rising edge of DEV_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK) - -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK (0x4U) -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT (2U) -/*! AP_HS_HOST_NEEDCLK - USB1 Host need clock signal control: - * 0b0..HOST_NEEDCLK is under hardware control. - * 0b1..HOST_NEEDCLK is forced high. - */ -#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK) - -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK (0x8U) -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT (3U) -/*! POL_HS_HOST_NEEDCLK - USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. - * 0b0..Falling edge of HOST_NEEDCLK triggers wake-up. - * 0b1..Rising edge of HOST_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK) - -#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U) -#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U) -/*! HS_DEV_WAKEUP_N - Software override of device controller PHY wake up logic. - * 0b0..Forces USB1_PHY to wake-up. - * 0b1..Normal USB1_PHY behavior. - */ -#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK) -/*! @} */ - -/*! @name USB1NEEDCLKSTAT - USB1 need clock status */ -/*! @{ */ - -#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) -#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) -/*! DEV_NEEDCLK - USB1 Device need_clock signal status:. - * 0b1..DEV_NEEDCLK is high. - * 0b0..DEV_NEEDCLK is low. - */ -#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK) - -#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) -#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) -/*! HOST_NEEDCLK - USB1 Host need_clock signal status:. - * 0b1..HOST_NEEDCLK is high. - * 0b0..HOST_NEEDCLK is low. - */ -#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK) -/*! @} */ - -/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */ -/*! @{ */ - -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U) -/*! CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in. - * 0b00..0 degree shift. - * 0b01..90 degree shift. - * 0b10..180 degree shift. - * 0b11..270 degree shift. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK) - -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U) -/*! CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. - * 0b00..0 degree shift. - * 0b01..90 degree shift. - * 0b10..180 degree shift. - * 0b11..270 degree shift. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK) - -#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) -#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U) -/*! PHASE_ACTIVE - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE. - * 0b0..Bypassed. - * 0b1..Activates phase shift logic. When active, the clock divider is active and phase delays are enabled. - */ -#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK) - -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U) -/*! CCLK_DRV_DELAY - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK) - -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U) -/*! CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field. - * 0b1..Enable drive delay. - * 0b0..Disable drive delay. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK) - -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U) -/*! CCLK_SAMPLE_DELAY - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK) - -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U) -/*! CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. - * 0b1..Enables sample delay. - * 0b0..Disables sample delay. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK) -/*! @} */ - -/*! @name PLL1CTRL - PLL1 550m control */ -/*! @{ */ - -#define SYSCON_PLL1CTRL_SELR_MASK (0xFU) -#define SYSCON_PLL1CTRL_SELR_SHIFT (0U) -/*! SELR - Bandwidth select R value. - */ -#define SYSCON_PLL1CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK) - -#define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U) -#define SYSCON_PLL1CTRL_SELI_SHIFT (4U) -/*! SELI - Bandwidth select I value. - */ -#define SYSCON_PLL1CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK) - -#define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U) -#define SYSCON_PLL1CTRL_SELP_SHIFT (10U) -/*! SELP - Bandwidth select P value. - */ -#define SYSCON_PLL1CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U) -#define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U) -/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - * 0b1..PLL input clock is sent directly to the PLL output. - * 0b0..use PLL. - */ -#define SYSCON_PLL1CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U) -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U) -/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - * 0b1..bypass of the divide-by-2 divider in the post-divider. - * 0b0..use the divide-by-2 divider in the post-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) - -#define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U) -#define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U) -/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. - */ -#define SYSCON_PLL1CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK) - -#define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U) -#define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U) -/*! BWDIRECT - control of the bandwidth of the PLL. - * 0b1..modify the bandwidth of the PLL directly. - * 0b0..the bandwidth is changed synchronously with the feedback-divider. - */ -#define SYSCON_PLL1CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U) -#define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U) -/*! BYPASSPREDIV - bypass of the pre-divider. - * 0b1..bypass of the pre-divider. - * 0b0..use the pre-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) - -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U) -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U) -/*! BYPASSPOSTDIV - bypass of the post-divider. - * 0b1..bypass of the post-divider. - * 0b0..use the post-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) - -#define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U) -#define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U) -/*! CLKEN - enable the output clock. - * 0b1..Enable the output clock. - * 0b0..Disable the output clock. - */ -#define SYSCON_PLL1CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK) - -#define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U) -#define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U) -/*! FRMEN - 1: free running mode. - */ -#define SYSCON_PLL1CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK) - -#define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U) -#define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U) -/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable. - */ -#define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK) - -#define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U) -#define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U) -/*! SKEWEN - Skew mode. - * 0b1..skewmode is enable. - * 0b0..skewmode is disable. - */ -#define SYSCON_PLL1CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK) -/*! @} */ - -/*! @name PLL1STAT - PLL1 550m status */ -/*! @{ */ - -#define SYSCON_PLL1STAT_LOCK_MASK (0x1U) -#define SYSCON_PLL1STAT_LOCK_SHIFT (0U) -/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. - */ -#define SYSCON_PLL1STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK) - -#define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U) -#define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U) -/*! PREDIVACK - pre-divider ratio change acknowledge. - */ -#define SYSCON_PLL1STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK) - -#define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U) -#define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U) -/*! FEEDDIVACK - feedback divider ratio change acknowledge. - */ -#define SYSCON_PLL1STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK) - -#define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U) -#define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U) -/*! POSTDIVACK - post-divider ratio change acknowledge. - */ -#define SYSCON_PLL1STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK) - -#define SYSCON_PLL1STAT_FRMDET_MASK (0x10U) -#define SYSCON_PLL1STAT_FRMDET_SHIFT (4U) -/*! FRMDET - free running detector output (active high). - */ -#define SYSCON_PLL1STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK) -/*! @} */ - -/*! @name PLL1NDEC - PLL1 550m N divider */ -/*! @{ */ - -#define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU) -#define SYSCON_PLL1NDEC_NDIV_SHIFT (0U) -/*! NDIV - pre-divider divider ratio (N-divider). - */ -#define SYSCON_PLL1NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK) - -#define SYSCON_PLL1NDEC_NREQ_MASK (0x100U) -#define SYSCON_PLL1NDEC_NREQ_SHIFT (8U) -/*! NREQ - pre-divider ratio change request. - */ -#define SYSCON_PLL1NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK) -/*! @} */ - -/*! @name PLL1MDEC - PLL1 550m M divider */ -/*! @{ */ - -#define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU) -#define SYSCON_PLL1MDEC_MDIV_SHIFT (0U) -/*! MDIV - feedback divider divider ratio (M-divider). - */ -#define SYSCON_PLL1MDEC_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK) - -#define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U) -#define SYSCON_PLL1MDEC_MREQ_SHIFT (16U) -/*! MREQ - feedback ratio change request. - */ -#define SYSCON_PLL1MDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK) -/*! @} */ - -/*! @name PLL1PDEC - PLL1 550m P divider */ -/*! @{ */ - -#define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU) -#define SYSCON_PLL1PDEC_PDIV_SHIFT (0U) -/*! PDIV - post-divider divider ratio (P-divider) - */ -#define SYSCON_PLL1PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK) - -#define SYSCON_PLL1PDEC_PREQ_MASK (0x20U) -#define SYSCON_PLL1PDEC_PREQ_SHIFT (5U) -/*! PREQ - feedback ratio change request. - */ -#define SYSCON_PLL1PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK) -/*! @} */ - -/*! @name PLL0CTRL - PLL0 550m control */ -/*! @{ */ - -#define SYSCON_PLL0CTRL_SELR_MASK (0xFU) -#define SYSCON_PLL0CTRL_SELR_SHIFT (0U) -/*! SELR - Bandwidth select R value. - */ -#define SYSCON_PLL0CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK) - -#define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U) -#define SYSCON_PLL0CTRL_SELI_SHIFT (4U) -/*! SELI - Bandwidth select I value. - */ -#define SYSCON_PLL0CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK) - -#define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U) -#define SYSCON_PLL0CTRL_SELP_SHIFT (10U) -/*! SELP - Bandwidth select P value. - */ -#define SYSCON_PLL0CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U) -#define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U) -/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - * 0b1..Bypass PLL input clock is sent directly to the PLL output. - * 0b0..use PLL. - */ -#define SYSCON_PLL0CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U) -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U) -/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - * 0b1..bypass of the divide-by-2 divider in the post-divider. - * 0b0..use the divide-by-2 divider in the post-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) - -#define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U) -#define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U) -/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. - */ -#define SYSCON_PLL0CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK) - -#define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U) -#define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U) -/*! BWDIRECT - Control of the bandwidth of the PLL. - * 0b1..modify the bandwidth of the PLL directly. - * 0b0..the bandwidth is changed synchronously with the feedback-divider. - */ -#define SYSCON_PLL0CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U) -#define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U) -/*! BYPASSPREDIV - bypass of the pre-divider. - * 0b1..bypass of the pre-divider. - * 0b0..use the pre-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) - -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U) -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U) -/*! BYPASSPOSTDIV - bypass of the post-divider. - * 0b1..bypass of the post-divider. - * 0b0..use the post-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) - -#define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U) -#define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U) -/*! CLKEN - enable the output clock. - * 0b1..enable the output clock. - * 0b0..disable the output clock. - */ -#define SYSCON_PLL0CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK) - -#define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U) -#define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U) -/*! FRMEN - free running mode. - * 0b1..free running mode is enable. - * 0b0..free running mode is disable. - */ -#define SYSCON_PLL0CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK) - -#define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U) -#define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U) -/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable. - */ -#define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK) - -#define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U) -#define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U) -/*! SKEWEN - skew mode. - * 0b1..skew mode is enable. - * 0b0..skew mode is disable. - */ -#define SYSCON_PLL0CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK) -/*! @} */ - -/*! @name PLL0STAT - PLL0 550m status */ -/*! @{ */ - -#define SYSCON_PLL0STAT_LOCK_MASK (0x1U) -#define SYSCON_PLL0STAT_LOCK_SHIFT (0U) -/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. - */ -#define SYSCON_PLL0STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK) - -#define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U) -#define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U) -/*! PREDIVACK - pre-divider ratio change acknowledge. - */ -#define SYSCON_PLL0STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK) - -#define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U) -#define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U) -/*! FEEDDIVACK - feedback divider ratio change acknowledge. - */ -#define SYSCON_PLL0STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK) - -#define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U) -#define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U) -/*! POSTDIVACK - post-divider ratio change acknowledge. - */ -#define SYSCON_PLL0STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK) - -#define SYSCON_PLL0STAT_FRMDET_MASK (0x10U) -#define SYSCON_PLL0STAT_FRMDET_SHIFT (4U) -/*! FRMDET - free running detector output (active high). - */ -#define SYSCON_PLL0STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK) -/*! @} */ - -/*! @name PLL0NDEC - PLL0 550m N divider */ -/*! @{ */ - -#define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU) -#define SYSCON_PLL0NDEC_NDIV_SHIFT (0U) -/*! NDIV - pre-divider divider ratio (N-divider). - */ -#define SYSCON_PLL0NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK) - -#define SYSCON_PLL0NDEC_NREQ_MASK (0x100U) -#define SYSCON_PLL0NDEC_NREQ_SHIFT (8U) -/*! NREQ - pre-divider ratio change request. - */ -#define SYSCON_PLL0NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK) -/*! @} */ - -/*! @name PLL0PDEC - PLL0 550m P divider */ -/*! @{ */ - -#define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU) -#define SYSCON_PLL0PDEC_PDIV_SHIFT (0U) -/*! PDIV - post-divider divider ratio (P-divider) - */ -#define SYSCON_PLL0PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK) - -#define SYSCON_PLL0PDEC_PREQ_MASK (0x20U) -#define SYSCON_PLL0PDEC_PREQ_SHIFT (5U) -/*! PREQ - feedback ratio change request. - */ -#define SYSCON_PLL0PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK) -/*! @} */ - -/*! @name PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 */ -/*! @{ */ - -#define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU) -#define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U) -/*! MD_LBS - input word of the wrapper bit 31 to 0. - */ -#define SYSCON_PLL0SSCG0_MD_LBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK) -/*! @} */ - -/*! @name PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 */ -/*! @{ */ - -#define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U) -#define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U) -/*! MD_MBS - input word of the wrapper bit 32. - */ -#define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK) - -#define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U) -#define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U) -/*! MD_REQ - md change request. - */ -#define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK) - -#define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) -#define SYSCON_PLL0SSCG1_MF_SHIFT (2U) -/*! MF - programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3. - */ -#define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK) - -#define SYSCON_PLL0SSCG1_MR_MASK (0xE0U) -#define SYSCON_PLL0SSCG1_MR_SHIFT (5U) -/*! MR - programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) - * mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1. - */ -#define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK) - -#define SYSCON_PLL0SSCG1_MC_MASK (0x300U) -#define SYSCON_PLL0SSCG1_MC_SHIFT (8U) -/*! MC - modulation waveform control Compensation for low pass filtering of the PLL to get a - * triangular modulation at the output of the PLL, giving a flat frequency spectrum. - */ -#define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK) - -#define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U) -#define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U) -/*! MDIV_EXT - to select an external mdiv value. - */ -#define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) - -#define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U) -#define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U) -/*! MREQ - to select an external mreq value. - */ -#define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK) - -#define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U) -#define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U) -/*! DITHER - dithering between two modulation frequencies in a random way or in a pseudo random way - * (white noise), in order to decrease the probability that the modulated waveform will occur - * with the same phase on a particular point on the screen. - */ -#define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK) - -#define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U) -#define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U) -/*! SEL_EXT - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext. - */ -#define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK) -/*! @} */ - -/*! @name FUNCRETENTIONCTRL - Functional retention control register */ -/*! @{ */ - -#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK (0x1U) -#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT (0U) -/*! FUNCRETENA - functional retention in power down only. - * 0b1..enable functional retention. - * 0b0..disable functional retention. - */ -#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK) - -#define SYSCON_FUNCRETENTIONCTRL_RET_START_MASK (0x3FFEU) -#define SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT (1U) -/*! RET_START - Start address divided by 4 inside SRAMX bank. - */ -#define SYSCON_FUNCRETENTIONCTRL_RET_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_START_MASK) - -#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK (0xFFC000U) -#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT (14U) -/*! RET_LENTH - lenth of Scan chains to save. - */ -#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) -/*! @} */ - -/*! @name CPUCTRL - CPU Control for multiple processors */ -/*! @{ */ - -#define SYSCON_CPUCTRL_CPU1CLKEN_MASK (0x8U) -#define SYSCON_CPUCTRL_CPU1CLKEN_SHIFT (3U) -/*! CPU1CLKEN - CPU1 clock enable. - * 0b1..The CPU1 clock is enabled. - * 0b0..The CPU1 clock is not enabled. - */ -#define SYSCON_CPUCTRL_CPU1CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1CLKEN_SHIFT)) & SYSCON_CPUCTRL_CPU1CLKEN_MASK) - -#define SYSCON_CPUCTRL_CPU1RSTEN_MASK (0x20U) -#define SYSCON_CPUCTRL_CPU1RSTEN_SHIFT (5U) -/*! CPU1RSTEN - CPU1 reset. - * 0b1..The CPU1 is being reset. - * 0b0..The CPU1 is not being reset. - */ -#define SYSCON_CPUCTRL_CPU1RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1RSTEN_SHIFT)) & SYSCON_CPUCTRL_CPU1RSTEN_MASK) -/*! @} */ - -/*! @name CPBOOT - Coprocessor Boot Address */ -/*! @{ */ - -#define SYSCON_CPBOOT_CPBOOT_MASK (0xFFFFFFFFU) -#define SYSCON_CPBOOT_CPBOOT_SHIFT (0U) -/*! CPBOOT - Coprocessor Boot Address for CPU1. - */ -#define SYSCON_CPBOOT_CPBOOT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_CPBOOT_SHIFT)) & SYSCON_CPBOOT_CPBOOT_MASK) -/*! @} */ - -/*! @name CPSTAT - CPU Status */ -/*! @{ */ - -#define SYSCON_CPSTAT_CPU0SLEEPING_MASK (0x1U) -#define SYSCON_CPSTAT_CPU0SLEEPING_SHIFT (0U) -/*! CPU0SLEEPING - The CPU0 sleeping state. - * 0b1..the CPU is sleeping. - * 0b0..the CPU is not sleeping. - */ -#define SYSCON_CPSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU0SLEEPING_MASK) - -#define SYSCON_CPSTAT_CPU1SLEEPING_MASK (0x2U) -#define SYSCON_CPSTAT_CPU1SLEEPING_SHIFT (1U) -/*! CPU1SLEEPING - The CPU1 sleeping state. - * 0b1..the CPU is sleeping. - * 0b0..the CPU is not sleeping. - */ -#define SYSCON_CPSTAT_CPU1SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU1SLEEPING_MASK) - -#define SYSCON_CPSTAT_CPU0LOCKUP_MASK (0x4U) -#define SYSCON_CPSTAT_CPU0LOCKUP_SHIFT (2U) -/*! CPU0LOCKUP - The CPU0 lockup state. - * 0b1..the CPU is in lockup. - * 0b0..the CPU is not in lockup. - */ -#define SYSCON_CPSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU0LOCKUP_MASK) - -#define SYSCON_CPSTAT_CPU1LOCKUP_MASK (0x8U) -#define SYSCON_CPSTAT_CPU1LOCKUP_SHIFT (3U) -/*! CPU1LOCKUP - The CPU1 lockup state. - * 0b1..the CPU is in lockup. - * 0b0..the CPU is not in lockup. - */ -#define SYSCON_CPSTAT_CPU1LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU1LOCKUP_MASK) -/*! @} */ - -/*! @name CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures */ -/*! @{ */ - -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U) -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U) -/*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U) -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U) -/*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U) -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U) -/*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U) -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U) -/*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) -#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) -/*! CLKIN_ENA - Enable clock_in clock for clock module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) -/*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U) -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U) -/*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U) -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U) -/*! XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK) - -#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U) -#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U) -/*! PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK) -/*! @} */ - -/*! @name COMP_INT_CTRL - Comparator Interrupt control */ -/*! @{ */ - -#define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U) -#define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U) -/*! INT_ENABLE - Analog Comparator interrupt enable control:. - * 0b1..interrupt enable. - * 0b0..interrupt disable. - */ -#define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK) - -#define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U) -#define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U) -/*! INT_CLEAR - Analog Comparator interrupt clear. - * 0b0..No effect. - * 0b1..Clear the interrupt. Self-cleared bit. - */ -#define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK) - -#define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU) -#define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U) -/*! INT_CTRL - Comparator interrupt type selector:. - * 0b000..The analog comparator interrupt edge sensitive is disabled. - * 0b010..analog comparator interrupt is rising edge sensitive. - * 0b100..analog comparator interrupt is falling edge sensitive. - * 0b110..analog comparator interrupt is rising and falling edge sensitive. - * 0b001..The analog comparator interrupt level sensitive is disabled. - * 0b011..Analog Comparator interrupt is high level sensitive. - * 0b101..Analog Comparator interrupt is low level sensitive. - * 0b111..The analog comparator interrupt level sensitive is disabled. - */ -#define SYSCON_COMP_INT_CTRL_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK) - -#define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U) -#define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U) -/*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. - * 0b0..Select Analog Comparator filtered output as input for interrupt detection. - * 0b1..Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when - * Analog comparator is used as wake up source in Power down mode. - */ -#define SYSCON_COMP_INT_CTRL_INT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK) -/*! @} */ - -/*! @name COMP_INT_STATUS - Comparator Interrupt status */ -/*! @{ */ - -#define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U) -#define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U) -/*! STATUS - Interrupt status BEFORE Interrupt Enable. - * 0b0..no interrupt pending. - * 0b1..interrupt pending. - */ -#define SYSCON_COMP_INT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK) - -#define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U) -#define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U) -/*! INT_STATUS - Interrupt status AFTER Interrupt Enable. - * 0b0..no interrupt pending. - * 0b1..interrupt pending. - */ -#define SYSCON_COMP_INT_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) - -#define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U) -#define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U) -/*! VAL - comparator analog output. - * 0b1..P+ is greater than P-. - * 0b0..P+ is smaller than P-. - */ -#define SYSCON_COMP_INT_STATUS_VAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK) -/*! @} */ - -/*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */ -/*! @{ */ - -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U) -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U) -/*! ROM - Control automatic clock gating of ROM controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK (0x2U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT (1U) -/*! RAMX_CTRL - Control automatic clock gating of RAMX controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK (0x4U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT (2U) -/*! RAM0_CTRL - Control automatic clock gating of RAM0 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK (0x8U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT (3U) -/*! RAM1_CTRL - Control automatic clock gating of RAM1 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK (0x10U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT (4U) -/*! RAM2_CTRL - Control automatic clock gating of RAM2 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK (0x20U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT (5U) -/*! RAM3_CTRL - Control automatic clock gating of RAM3 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK (0x40U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT (6U) -/*! RAM4_CTRL - Control automatic clock gating of RAM4 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U) -/*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U) -/*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U) -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U) -/*! CRCGEN - Control automatic clock gating of CRCGEN controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U) -/*! SDMA0 - Control automatic clock gating of DMA0 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U) -/*! SDMA1 - Control automatic clock gating of DMA1 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK (0x4000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT (14U) -/*! USB0 - Control automatic clock gating of USB controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U) -/*! SYSCON - Control automatic clock gating of synchronous system controller registers bank. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK) - -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U) -/*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. - * 0b1100000011011110..Bit Fields 0 - 15 of this register are updated - * 0b0000000000000000..Bit Fields 0 - 15 of this register are not updated - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK) -/*! @} */ - -/*! @name GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module */ -/*! @{ */ - -#define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U) -#define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U) -/*! PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module. - * 0b1..bypass of the first stage of synchonization inside GPIO_INT module. - * 0b0..use the first stage of synchonization inside GPIO_INT module. - */ -#define SYSCON_GPIOPSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK) -/*! @} */ - -/*! @name DEBUG_LOCK_EN - Control write access to security registers. */ -/*! @{ */ - -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) -/*! LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, - * CODESECURITYPROTCPU1, CPU0_DEBUG_FEATURES, CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. - * 0b1010..1010: Enable write access to all 6 registers. - * 0b0000..Any other value than b1010: disable write access to all 6 registers. - */ -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) -/*! @} */ - -/*! @name DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control. */ -/*! @{ */ - -#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) -#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) -/*! CPU0_DBGEN - CPU0 Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) -#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) -/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK (0x30U) -#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (4U) -/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0xC0U) -#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U) -/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK (0x300U) -#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT (8U) -/*! CPU1_DBGEN - CPU1 Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK) - -#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK (0xC00U) -#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT (10U) -/*! CPU1_NIDEN - CPU1 Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK) -/*! @} */ - -/*! @name DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register. */ -/*! @{ */ - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) -/*! CPU0_DBGEN - CPU0 (CPU0) Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) -/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U) -/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U) -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U) -/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK (0x300U) -#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT (8U) -/*! CPU1_DBGEN - CPU1 Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK) - -#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK (0xC00U) -#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT (10U) -/*! CPU1_NIDEN - CPU1 Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK) -/*! @} */ - -/*! @name KEY_BLOCK - block quiddikey/PUF all index. */ -/*! @{ */ - -#define SYSCON_KEY_BLOCK_KEY_BLOCK_MASK (0xFFFFFFFFU) -#define SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT (0U) -/*! KEY_BLOCK - Write a value to block quiddikey/PUF all index. - */ -#define SYSCON_KEY_BLOCK_KEY_BLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCON_KEY_BLOCK_KEY_BLOCK_MASK) -/*! @} */ - -/*! @name DEBUG_AUTH_BEACON - Debug authentication BEACON register */ -/*! @{ */ - -#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) -#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) -/*! BEACON - Set by the debug authentication code in ROM to pass the debug beacons (Credential - * Beacon and Authentication Beacon) to application code. - */ -#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) -/*! @} */ - -/*! @name CPUCFG - CPUs configuration register */ -/*! @{ */ - -#define SYSCON_CPUCFG_CPU1ENABLE_MASK (0x4U) -#define SYSCON_CPUCFG_CPU1ENABLE_SHIFT (2U) -/*! CPU1ENABLE - Enable CPU1. - * 0b0..CPU1 is disable (Processor in reset). - * 0b1..CPU1 is enable. - */ -#define SYSCON_CPUCFG_CPU1ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCFG_CPU1ENABLE_SHIFT)) & SYSCON_CPUCFG_CPU1ENABLE_MASK) -/*! @} */ - -/*! @name DEVICE_ID0 - Device ID */ -/*! @{ */ - -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) -/*! ROM_REV_MINOR - ROM revision. - */ -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) -/*! @} */ - -/*! @name DIEID - Chip revision ID and Number */ -/*! @{ */ - -#define SYSCON_DIEID_REV_ID_MASK (0xFU) -#define SYSCON_DIEID_REV_ID_SHIFT (0U) -/*! REV_ID - Chip Metal Revision ID. - */ -#define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK) - -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U) -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U) -/*! MCO_NUM_IN_DIE_ID - Chip Number 0x426B. - */ -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SYSCON_Register_Masks */ - - -/* SYSCON - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SYSCON base address */ - #define SYSCON_BASE (0x50000000u) - /** Peripheral SYSCON base address */ - #define SYSCON_BASE_NS (0x40000000u) - /** Peripheral SYSCON base pointer */ - #define SYSCON ((SYSCON_Type *)SYSCON_BASE) - /** Peripheral SYSCON base pointer */ - #define SYSCON_NS ((SYSCON_Type *)SYSCON_BASE_NS) - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS { SYSCON_BASE } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS { SYSCON } - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS_NS { SYSCON_BASE_NS } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS_NS { SYSCON_NS } -#else - /** Peripheral SYSCON base address */ - #define SYSCON_BASE (0x40000000u) - /** Peripheral SYSCON base pointer */ - #define SYSCON ((SYSCON_Type *)SYSCON_BASE) - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS { SYSCON_BASE } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS { SYSCON } -#endif - -/*! - * @} - */ /* end of group SYSCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SYSCTL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCTL_Peripheral_Access_Layer SYSCTL Peripheral Access Layer - * @{ - */ - -/** SYSCTL - Register Layout Typedef */ -typedef struct { - __IO uint32_t UPDATELCKOUT; /**< update lock out control, offset: 0x0 */ - uint8_t RESERVED_0[60]; - __IO uint32_t FCCTRLSEL[8]; /**< Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_1[32]; - __IO uint32_t SHAREDCTRLSET[2]; /**< Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1., array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_2[120]; - __I uint32_t USB_HS_STATUS; /**< Status register for USB HS, offset: 0x100 */ -} SYSCTL_Type; - -/* ---------------------------------------------------------------------------- - -- SYSCTL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCTL_Register_Masks SYSCTL Register Masks - * @{ - */ - -/*! @name UPDATELCKOUT - update lock out control */ -/*! @{ */ - -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U) -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U) -/*! UPDATELCKOUT - All Registers - * 0b0..Normal Mode. Can be written to. - * 0b1..Protected Mode. Cannot be written to. - */ -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK) -/*! @} */ - -/*! @name FCCTRLSEL - Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7 */ -/*! @{ */ - -#define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U) -#define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U) -/*! SCKINSEL - Selects the source for SCK going into this Flexcomm. - * 0b00..Selects the dedicated FCn_SCK function for this Flexcomm. - * 0b01..SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK) - -#define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U) -#define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U) -/*! WSINSEL - Selects the source for WS going into this Flexcomm. - * 0b00..Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. - * 0b01..WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK) - -#define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U) -#define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U) -/*! DATAINSEL - Selects the source for DATA input to this Flexcomm. - * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. - * 0b01..Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK) - -#define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U) -#define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U) -/*! DATAOUTSEL - Selects the source for DATA output from this Flexcomm. - * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. - * 0b01..Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_DATAOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK) -/*! @} */ - -/* The count of SYSCTL_FCCTRLSEL */ -#define SYSCTL_FCCTRLSEL_COUNT (8U) - -/*! @name SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */ -/*! @{ */ - -#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U) -#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U) -/*! SHAREDSCKSEL - Selects the source for SCK of this shared signal set. - * 0b000..SCK for this shared signal set comes from Flexcomm 0. - * 0b001..SCK for this shared signal set comes from Flexcomm 1. - * 0b010..SCK for this shared signal set comes from Flexcomm 2. - * 0b011..SCK for this shared signal set comes from Flexcomm 3. - * 0b100..SCK for this shared signal set comes from Flexcomm 4. - * 0b101..SCK for this shared signal set comes from Flexcomm 5. - * 0b110..SCK for this shared signal set comes from Flexcomm 6. - * 0b111..SCK for this shared signal set comes from Flexcomm 7. - */ -#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK) - -#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U) -#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U) -/*! SHAREDWSSEL - Selects the source for WS of this shared signal set. - * 0b000..WS for this shared signal set comes from Flexcomm 0. - * 0b001..WS for this shared signal set comes from Flexcomm 1. - * 0b010..WS for this shared signal set comes from Flexcomm 2. - * 0b011..WS for this shared signal set comes from Flexcomm 3. - * 0b100..WS for this shared signal set comes from Flexcomm 4. - * 0b101..WS for this shared signal set comes from Flexcomm 5. - * 0b110..WS for this shared signal set comes from Flexcomm 6. - * 0b111..WS for this shared signal set comes from Flexcomm 7. - */ -#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK) - -#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U) -#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U) -/*! SHAREDDATASEL - Selects the source for DATA input for this shared signal set. - * 0b000..DATA input for this shared signal set comes from Flexcomm 0. - * 0b001..DATA input for this shared signal set comes from Flexcomm 1. - * 0b010..DATA input for this shared signal set comes from Flexcomm 2. - * 0b011..DATA input for this shared signal set comes from Flexcomm 3. - * 0b100..DATA input for this shared signal set comes from Flexcomm 4. - * 0b101..DATA input for this shared signal set comes from Flexcomm 5. - * 0b110..DATA input for this shared signal set comes from Flexcomm 6. - * 0b111..DATA input for this shared signal set comes from Flexcomm 7. - */ -#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U) -#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U) -/*! FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC0 does not contribute to this shared set. - * 0b1..Data output from FC0 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U) -#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U) -/*! FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC1 does not contribute to this shared set. - * 0b1..Data output from FC1 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK (0x40000U) -#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT (18U) -/*! FC2DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC2 does not contribute to this shared set. - * 0b1..Data output from FC2 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U) -#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U) -/*! FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC4 does not contribute to this shared set. - * 0b1..Data output from FC4 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U) -#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U) -/*! FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC5 does not contribute to this shared set. - * 0b1..Data output from FC5 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U) -#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U) -/*! FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC6 does not contribute to this shared set. - * 0b1..Data output from FC6 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK) - -#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U) -#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U) -/*! FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC7 does not contribute to this shared set. - * 0b1..Data output from FC7 does contribute to this shared set. - */ -#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK) -/*! @} */ - -/* The count of SYSCTL_SHAREDCTRLSET */ -#define SYSCTL_SHAREDCTRLSET_COUNT (2U) - -/*! @name USB_HS_STATUS - Status register for USB HS */ -/*! @{ */ - -#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK (0x1U) -#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT (0U) -/*! USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply. - * 0b0..3v3 supply is good. - * 0b1..3v3 supply is too low. - */ -#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT)) & SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SYSCTL_Register_Masks */ - - -/* SYSCTL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE (0x50023000u) - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE_NS (0x40023000u) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL_NS ((SYSCTL_Type *)SYSCTL_BASE_NS) - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS { SYSCTL } - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS_NS { SYSCTL_BASE_NS } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS_NS { SYSCTL_NS } -#else - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE (0x40023000u) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS { SYSCTL } -#endif - -/*! - * @} - */ /* end of group SYSCTL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USART Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer - * @{ - */ - -/** USART - Register Layout Typedef */ -typedef struct { - __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ - __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ - __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ - uint8_t RESERVED_0[12]; - __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ - __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ - __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ - __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ - uint8_t RESERVED_1[3536]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_2[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_3[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_4[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_6[4]; - __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ - uint8_t RESERVED_7[432]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} USART_Type; - -/* ---------------------------------------------------------------------------- - -- USART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Register_Masks USART Register Masks - * @{ - */ - -/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ -/*! @{ */ - -#define USART_CFG_ENABLE_MASK (0x1U) -#define USART_CFG_ENABLE_SHIFT (0U) -/*! ENABLE - USART Enable. - * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, - * all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control - * bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the - * transmitter has been reset and is therefore available. - * 0b1..Enabled. The USART is enabled for operation. - */ -#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) - -#define USART_CFG_DATALEN_MASK (0xCU) -#define USART_CFG_DATALEN_SHIFT (2U) -/*! DATALEN - Selects the data size for the USART. - * 0b00..7 bit Data length. - * 0b01..8 bit Data length. - * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. - * 0b11..Reserved. - */ -#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) - -#define USART_CFG_PARITYSEL_MASK (0x30U) -#define USART_CFG_PARITYSEL_SHIFT (4U) -/*! PARITYSEL - Selects what type of parity is used by the USART. - * 0b00..No parity. - * 0b01..Reserved. - * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, - * and the number of 1s in a received character is expected to be even. - * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, - * and the number of 1s in a received character is expected to be odd. - */ -#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) - -#define USART_CFG_STOPLEN_MASK (0x40U) -#define USART_CFG_STOPLEN_SHIFT (6U) -/*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. - * 0b0..1 stop bit. - * 0b1..2 stop bits. This setting should only be used for asynchronous communication. - */ -#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) - -#define USART_CFG_MODE32K_MASK (0x80U) -#define USART_CFG_MODE32K_SHIFT (7U) -/*! MODE32K - Selects standard or 32 kHz clocking mode. - * 0b0..Disabled. USART uses standard clocking. - * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. - */ -#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) - -#define USART_CFG_LINMODE_MASK (0x100U) -#define USART_CFG_LINMODE_SHIFT (8U) -/*! LINMODE - LIN break mode enable. - * 0b0..Disabled. Break detect and generate is configured for normal operation. - * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. - */ -#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) - -#define USART_CFG_CTSEN_MASK (0x200U) -#define USART_CFG_CTSEN_SHIFT (9U) -/*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input - * pin, or from the USART's own RTS if loopback mode is enabled. - * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. - * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. - */ -#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) - -#define USART_CFG_SYNCEN_MASK (0x800U) -#define USART_CFG_SYNCEN_SHIFT (11U) -/*! SYNCEN - Selects synchronous or asynchronous operation. - * 0b0..Asynchronous mode. - * 0b1..Synchronous mode. - */ -#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) - -#define USART_CFG_CLKPOL_MASK (0x1000U) -#define USART_CFG_CLKPOL_SHIFT (12U) -/*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. - * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK. - * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. - */ -#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) - -#define USART_CFG_SYNCMST_MASK (0x4000U) -#define USART_CFG_SYNCMST_SHIFT (14U) -/*! SYNCMST - Synchronous mode Master select. - * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. - * 0b1..Master. When synchronous mode is enabled, the USART is a master. - */ -#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) - -#define USART_CFG_LOOP_MASK (0x8000U) -#define USART_CFG_LOOP_SHIFT (15U) -/*! LOOP - Selects data loopback mode. - * 0b0..Normal operation. - * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial - * data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD - * and Un_RTS activity will also appear on external pins if these functions are configured to appear on device - * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. - */ -#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) - -#define USART_CFG_OETA_MASK (0x40000U) -#define USART_CFG_OETA_SHIFT (18U) -/*! OETA - Output Enable Turnaround time enable for RS-485 operation. - * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. - * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the - * end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins - * before it is deasserted. - */ -#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) - -#define USART_CFG_AUTOADDR_MASK (0x80000U) -#define USART_CFG_AUTOADDR_SHIFT (19U) -/*! AUTOADDR - Automatic Address matching enable. - * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the - * possibility of versatile addressing (e.g. respond to more than one address). - * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in - * the ADDR register as the address to match. - */ -#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) - -#define USART_CFG_OESEL_MASK (0x100000U) -#define USART_CFG_OESEL_SHIFT (20U) -/*! OESEL - Output Enable Select. - * 0b0..Standard. The RTS signal is used as the standard flow control function. - * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. - */ -#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) - -#define USART_CFG_OEPOL_MASK (0x200000U) -#define USART_CFG_OEPOL_SHIFT (21U) -/*! OEPOL - Output Enable Polarity. - * 0b0..Low. If selected by OESEL, the output enable is active low. - * 0b1..High. If selected by OESEL, the output enable is active high. - */ -#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) - -#define USART_CFG_RXPOL_MASK (0x400000U) -#define USART_CFG_RXPOL_SHIFT (22U) -/*! RXPOL - Receive data polarity. - * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start - * bit is 0, data is not inverted, and the stop bit is 1. - * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is - * 0, start bit is 1, data is inverted, and the stop bit is 0. - */ -#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) - -#define USART_CFG_TXPOL_MASK (0x800000U) -#define USART_CFG_TXPOL_SHIFT (23U) -/*! TXPOL - Transmit data polarity. - * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is - * 0, data is not inverted, and the stop bit is 1. - * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value - * is 0, start bit is 1, data is inverted, and the stop bit is 0. - */ -#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) -/*! @} */ - -/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ -/*! @{ */ - -#define USART_CTL_TXBRKEN_MASK (0x2U) -#define USART_CTL_TXBRKEN_SHIFT (1U) -/*! TXBRKEN - Break Enable. - * 0b0..Normal operation. - * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit - * is cleared. A break may be sent without danger of corrupting any currently transmitting character if the - * transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled - * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. - */ -#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) - -#define USART_CTL_ADDRDET_MASK (0x4U) -#define USART_CTL_ADDRDET_SHIFT (2U) -/*! ADDRDET - Enable address detect mode. - * 0b0..Disabled. The USART presents all incoming data. - * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data - * (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, - * generating a received data interrupt. Software can then check the data to see if this is an address that - * should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled - * normally. - */ -#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) - -#define USART_CTL_TXDIS_MASK (0x40U) -#define USART_CTL_TXDIS_SHIFT (6U) -/*! TXDIS - Transmit Disable. - * 0b0..Not disabled. USART transmitter is not disabled. - * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This - * feature can be used to facilitate software flow control. - */ -#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) - -#define USART_CTL_CC_MASK (0x100U) -#define USART_CTL_CC_SHIFT (8U) -/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. - * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to - * complete a character that is being received. - * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on - * Un_RxD independently from transmission on Un_TXD). - */ -#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) - -#define USART_CTL_CLRCCONRX_MASK (0x200U) -#define USART_CTL_CLRCCONRX_SHIFT (9U) -/*! CLRCCONRX - Clear Continuous Clock. - * 0b0..No effect. No effect on the CC bit. - * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. - */ -#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) - -#define USART_CTL_AUTOBAUD_MASK (0x10000U) -#define USART_CTL_AUTOBAUD_SHIFT (16U) -/*! AUTOBAUD - Autobaud enable. - * 0b0..Disabled. USART is in normal operating mode. - * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The - * first start bit of RX is measured and used the update the BRG register to match the received data rate. - * AUTOBAUD is cleared once this process is complete, or if there is an AERR. - */ -#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) -/*! @} */ - -/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ -/*! @{ */ - -#define USART_STAT_RXIDLE_MASK (0x2U) -#define USART_STAT_RXIDLE_SHIFT (1U) -/*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of - * receiving data. When 1, indicates that the receiver is not currently in the process of receiving - * data. - */ -#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) - -#define USART_STAT_TXIDLE_MASK (0x8U) -#define USART_STAT_TXIDLE_SHIFT (3U) -/*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of - * sending data.When 1, indicate that the transmitter is not currently in the process of sending - * data. - */ -#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) - -#define USART_STAT_CTS_MASK (0x10U) -#define USART_STAT_CTS_SHIFT (4U) -/*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the - * CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode - * is enabled. - */ -#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) - -#define USART_STAT_DELTACTS_MASK (0x20U) -#define USART_STAT_DELTACTS_SHIFT (5U) -/*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. - */ -#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) - -#define USART_STAT_TXDISSTAT_MASK (0x40U) -#define USART_STAT_TXDISSTAT_SHIFT (6U) -/*! TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART - * transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). - */ -#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) - -#define USART_STAT_RXBRK_MASK (0x400U) -#define USART_STAT_RXBRK_SHIFT (10U) -/*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection - * logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also - * be set when this condition occurs because the stop bit(s) for the character would be missing. - * RXBRK is cleared when the Un_RXD pin goes high. - */ -#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) - -#define USART_STAT_DELTARXBRK_MASK (0x800U) -#define USART_STAT_DELTARXBRK_SHIFT (11U) -/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software. - */ -#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) - -#define USART_STAT_START_MASK (0x1000U) -#define USART_STAT_START_SHIFT (12U) -/*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily - * to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. - * Cleared by software. - */ -#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) - -#define USART_STAT_FRAMERRINT_MASK (0x2000U) -#define USART_STAT_FRAMERRINT_SHIFT (13U) -/*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a - * missing stop bit at the expected location. This could be an indication of a baud rate or - * configuration mismatch with the transmitting source. - */ -#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) - -#define USART_STAT_PARITYERRINT_MASK (0x4000U) -#define USART_STAT_PARITYERRINT_SHIFT (14U) -/*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. - */ -#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) - -#define USART_STAT_RXNOISEINT_MASK (0x8000U) -#define USART_STAT_RXNOISEINT_SHIFT (15U) -/*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to - * determine the value of each received data bit, except in synchronous mode. This acts as a - * noise filter if one sample disagrees. This flag is set when a received data bit contains one - * disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or - * loss of synchronization during data reception. - */ -#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) - -#define USART_STAT_ABERR_MASK (0x10000U) -#define USART_STAT_ABERR_SHIFT (16U) -/*! ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the - * end of the start bit that is being measured, essentially an auto baud time-out. - */ -#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -/*! @{ */ - -#define USART_INTENSET_TXIDLEEN_MASK (0x8U) -#define USART_INTENSET_TXIDLEEN_SHIFT (3U) -/*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). - */ -#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) - -#define USART_INTENSET_DELTACTSEN_MASK (0x20U) -#define USART_INTENSET_DELTACTSEN_SHIFT (5U) -/*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input. - */ -#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) - -#define USART_INTENSET_TXDISEN_MASK (0x40U) -#define USART_INTENSET_TXDISEN_SHIFT (6U) -/*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by - * the TXDISINT flag in STAT. See description of the TXDISINT bit for details. - */ -#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) - -#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) -#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) -/*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection - * of a received break condition (break condition asserted or deasserted). - */ -#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) - -#define USART_INTENSET_STARTEN_MASK (0x1000U) -#define USART_INTENSET_STARTEN_SHIFT (12U) -/*! STARTEN - When 1, enables an interrupt when a received start bit has been detected. - */ -#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) - -#define USART_INTENSET_FRAMERREN_MASK (0x2000U) -#define USART_INTENSET_FRAMERREN_SHIFT (13U) -/*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected. - */ -#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) - -#define USART_INTENSET_PARITYERREN_MASK (0x4000U) -#define USART_INTENSET_PARITYERREN_SHIFT (14U) -/*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected. - */ -#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) - -#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) -#define USART_INTENSET_RXNOISEEN_SHIFT (15U) -/*! RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. - */ -#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) - -#define USART_INTENSET_ABERREN_MASK (0x10000U) -#define USART_INTENSET_ABERREN_SHIFT (16U) -/*! ABERREN - When 1, enables an interrupt when an auto baud error occurs. - */ -#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ -/*! @{ */ - -#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) -#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) -/*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) - -#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) -#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) -/*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) - -#define USART_INTENCLR_TXDISCLR_MASK (0x40U) -#define USART_INTENCLR_TXDISCLR_SHIFT (6U) -/*! TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) - -#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) -#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) -/*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) - -#define USART_INTENCLR_STARTCLR_MASK (0x1000U) -#define USART_INTENCLR_STARTCLR_SHIFT (12U) -/*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) - -#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) -#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) -/*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) - -#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) -#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) -/*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) - -#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) -#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) -/*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) - -#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) -#define USART_INTENCLR_ABERRCLR_SHIFT (16U) -/*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - */ -#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) -/*! @} */ - -/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ -/*! @{ */ - -#define USART_BRG_BRGVAL_MASK (0xFFFFU) -#define USART_BRG_BRGVAL_SHIFT (0U) -/*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on - * the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is - * divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART - * function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. - */ -#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ -/*! @{ */ - -#define USART_INTSTAT_TXIDLE_MASK (0x8U) -#define USART_INTSTAT_TXIDLE_SHIFT (3U) -/*! TXIDLE - Transmitter Idle status. - */ -#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) - -#define USART_INTSTAT_DELTACTS_MASK (0x20U) -#define USART_INTSTAT_DELTACTS_SHIFT (5U) -/*! DELTACTS - This bit is set when a change in the state of the CTS input is detected. - */ -#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) - -#define USART_INTSTAT_TXDISINT_MASK (0x40U) -#define USART_INTSTAT_TXDISINT_SHIFT (6U) -/*! TXDISINT - Transmitter Disabled Interrupt flag. - */ -#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) - -#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) -#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) -/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. - */ -#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) - -#define USART_INTSTAT_START_MASK (0x1000U) -#define USART_INTSTAT_START_SHIFT (12U) -/*! START - This bit is set when a start is detected on the receiver input. - */ -#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) - -#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) -#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) -/*! FRAMERRINT - Framing Error interrupt flag. - */ -#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) - -#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) -#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) -/*! PARITYERRINT - Parity Error interrupt flag. - */ -#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) - -#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) -#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) -/*! RXNOISEINT - Received Noise interrupt flag. - */ -#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) - -#define USART_INTSTAT_ABERRINT_MASK (0x10000U) -#define USART_INTSTAT_ABERRINT_SHIFT (16U) -/*! ABERRINT - Auto baud Error Interrupt flag. - */ -#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) -/*! @} */ - -/*! @name OSR - Oversample selection register for asynchronous communication. */ -/*! @{ */ - -#define USART_OSR_OSRVAL_MASK (0xFU) -#define USART_OSR_OSRVAL_SHIFT (0U) -/*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to - * transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive - * each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. - */ -#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) -/*! @} */ - -/*! @name ADDR - Address register for automatic address matching. */ -/*! @{ */ - -#define USART_ADDR_ADDRESS_MASK (0xFFU) -#define USART_ADDR_ADDRESS_SHIFT (0U) -/*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is - * enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). - */ -#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ - -#define USART_FIFOCFG_ENABLETX_MASK (0x1U) -#define USART_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) - -#define USART_FIFOCFG_ENABLERX_MASK (0x2U) -#define USART_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) - -#define USART_FIFOCFG_SIZE_MASK (0x30U) -#define USART_FIFOCFG_SIZE_SHIFT (4U) -/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 - * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - */ -#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) - -#define USART_FIFOCFG_DMATX_MASK (0x1000U) -#define USART_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) - -#define USART_FIFOCFG_DMARX_MASK (0x2000U) -#define USART_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) - -#define USART_FIFOCFG_WAKETX_MASK (0x4000U) -#define USART_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in - * FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) - -#define USART_FIFOCFG_WAKERX_MASK (0x8000U) -#define USART_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power - * modes (up to power-down, as long as the peripheral function works in that power mode) without - * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The - * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware - * Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in - * FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) - -#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) -/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - */ -#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) - -#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) -/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - */ -#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ - -#define USART_FIFOSTAT_TXERR_MASK (0x1U) -#define USART_FIFOSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow - * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is - * needed. Cleared by writing a 1 to this bit. - */ -#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) - -#define USART_FIFOSTAT_RXERR_MASK (0x2U) -#define USART_FIFOSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA - * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - */ -#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) - -#define USART_FIFOSTAT_PERINT_MASK (0x8U) -#define USART_FIFOSTAT_PERINT_SHIFT (3U) -/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted - * an interrupt. The details can be found by reading the peripheral's STAT register. - */ -#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) - -#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) -/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - */ -#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) - -#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) -/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be - * written. When 0, the transmit FIFO is full and another write would cause it to overflow. - */ -#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) - -#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - */ -#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) - -#define USART_FIFOSTAT_RXFULL_MASK (0x80U) -#define USART_FIFOSTAT_RXFULL_SHIFT (7U) -/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to - * prevent the peripheral from causing an overflow. - */ -#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) - -#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define USART_FIFOSTAT_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY - * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at - * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be - * 0. - */ -#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) - -#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define USART_FIFOSTAT_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and - * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the - * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be - * 1. - */ -#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ - -#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) - -#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled - * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) - -#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) -#define USART_FIFOTRIG_TXLVL_SHIFT (8U) -/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled - * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to - * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO - * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX - * FIFO level decreases to 15 entries (is no longer full). - */ -#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) - -#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define USART_FIFOTRIG_RXLVL_SHIFT (16U) -/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data - * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level - * can wake up the device just enough to perform DMA, then return to the reduced power mode. See - * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no - * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX - * FIFO has received 16 entries (has become full). - */ -#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ - -#define USART_FIFOINTENSET_TXERR_MASK (0x1U) -#define USART_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) - -#define USART_FIFOINTENSET_RXERR_MASK (0x2U) -#define USART_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) - -#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) -#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases - * to the level specified by TXLVL in the FIFOTRIG register. - */ -#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) - -#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) -#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level - * specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level - * increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ - -#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) -#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) -/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) - -#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) -#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) -/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) - -#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) -/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) - -#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) -/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - */ -#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ - -#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) -#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) -/*! TXERR - TX FIFO error. - */ -#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) - -#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) -#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) -/*! RXERR - RX FIFO error. - */ -#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) - -#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) -/*! TXLVL - Transmit FIFO level interrupt. - */ -#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) - -#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) -/*! RXLVL - Receive FIFO level interrupt. - */ -#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) - -#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) -#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) -/*! PERINT - Peripheral interrupt. - */ -#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ - -#define USART_FIFOWR_TXDATA_MASK (0x1FFU) -#define USART_FIFOWR_TXDATA_SHIFT (0U) -/*! TXDATA - Transmit data to the FIFO. - */ -#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ - -#define USART_FIFORD_RXDATA_MASK (0x1FFU) -#define USART_FIFORD_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. - */ -#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) - -#define USART_FIFORD_FRAMERR_MASK (0x2000U) -#define USART_FIFORD_FRAMERR_SHIFT (13U) -/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along - * with from the FIFO, and indicates that the character was received with a missing stop bit at - * the expected location. This could be an indication of a baud rate or configuration mismatch - * with the transmitting source. - */ -#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) - -#define USART_FIFORD_PARITYERR_MASK (0x4000U) -#define USART_FIFORD_PARITYERR_SHIFT (14U) -/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along - * with from the FIFO. This bit will be set when a parity error is detected in a received - * character. - */ -#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) - -#define USART_FIFORD_RXNOISE_MASK (0x8000U) -#define USART_FIFORD_RXNOISE_SHIFT (15U) -/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. - */ -#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ - -#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) -#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) -/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. - */ -#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) - -#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) -#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) -/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along - * with from the FIFO, and indicates that the character was received with a missing stop bit at - * the expected location. This could be an indication of a baud rate or configuration mismatch - * with the transmitting source. - */ -#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) - -#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) -#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) -/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along - * with from the FIFO. This bit will be set when a parity error is detected in a received - * character. - */ -#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) - -#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) -#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) -/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. - */ -#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) -/*! @} */ - -/*! @name FIFOSIZE - FIFO size register */ -/*! @{ */ - -#define USART_FIFOSIZE_FIFOSIZE_MASK (0x1FU) -#define USART_FIFOSIZE_FIFOSIZE_SHIFT (0U) -/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - */ -#define USART_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSIZE_FIFOSIZE_SHIFT)) & USART_FIFOSIZE_FIFOSIZE_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ - -#define USART_ID_APERTURE_MASK (0xFFU) -#define USART_ID_APERTURE_SHIFT (0U) -/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - */ -#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) - -#define USART_ID_MINOR_REV_MASK (0xF00U) -#define USART_ID_MINOR_REV_SHIFT (8U) -/*! MINOR_REV - Minor revision of module implementation. - */ -#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) - -#define USART_ID_MAJOR_REV_MASK (0xF000U) -#define USART_ID_MAJOR_REV_SHIFT (12U) -/*! MAJOR_REV - Major revision of module implementation. - */ -#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) - -#define USART_ID_ID_MASK (0xFFFF0000U) -#define USART_ID_ID_SHIFT (16U) -/*! ID - Module identifier for the selected function. - */ -#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USART_Register_Masks */ - - -/* USART - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USART0 base address */ - #define USART0_BASE (0x50086000u) - /** Peripheral USART0 base address */ - #define USART0_BASE_NS (0x40086000u) - /** Peripheral USART0 base pointer */ - #define USART0 ((USART_Type *)USART0_BASE) - /** Peripheral USART0 base pointer */ - #define USART0_NS ((USART_Type *)USART0_BASE_NS) - /** Peripheral USART1 base address */ - #define USART1_BASE (0x50087000u) - /** Peripheral USART1 base address */ - #define USART1_BASE_NS (0x40087000u) - /** Peripheral USART1 base pointer */ - #define USART1 ((USART_Type *)USART1_BASE) - /** Peripheral USART1 base pointer */ - #define USART1_NS ((USART_Type *)USART1_BASE_NS) - /** Peripheral USART2 base address */ - #define USART2_BASE (0x50088000u) - /** Peripheral USART2 base address */ - #define USART2_BASE_NS (0x40088000u) - /** Peripheral USART2 base pointer */ - #define USART2 ((USART_Type *)USART2_BASE) - /** Peripheral USART2 base pointer */ - #define USART2_NS ((USART_Type *)USART2_BASE_NS) - /** Peripheral USART3 base address */ - #define USART3_BASE (0x50089000u) - /** Peripheral USART3 base address */ - #define USART3_BASE_NS (0x40089000u) - /** Peripheral USART3 base pointer */ - #define USART3 ((USART_Type *)USART3_BASE) - /** Peripheral USART3 base pointer */ - #define USART3_NS ((USART_Type *)USART3_BASE_NS) - /** Peripheral USART4 base address */ - #define USART4_BASE (0x5008A000u) - /** Peripheral USART4 base address */ - #define USART4_BASE_NS (0x4008A000u) - /** Peripheral USART4 base pointer */ - #define USART4 ((USART_Type *)USART4_BASE) - /** Peripheral USART4 base pointer */ - #define USART4_NS ((USART_Type *)USART4_BASE_NS) - /** Peripheral USART5 base address */ - #define USART5_BASE (0x50096000u) - /** Peripheral USART5 base address */ - #define USART5_BASE_NS (0x40096000u) - /** Peripheral USART5 base pointer */ - #define USART5 ((USART_Type *)USART5_BASE) - /** Peripheral USART5 base pointer */ - #define USART5_NS ((USART_Type *)USART5_BASE_NS) - /** Peripheral USART6 base address */ - #define USART6_BASE (0x50097000u) - /** Peripheral USART6 base address */ - #define USART6_BASE_NS (0x40097000u) - /** Peripheral USART6 base pointer */ - #define USART6 ((USART_Type *)USART6_BASE) - /** Peripheral USART6 base pointer */ - #define USART6_NS ((USART_Type *)USART6_BASE_NS) - /** Peripheral USART7 base address */ - #define USART7_BASE (0x50098000u) - /** Peripheral USART7 base address */ - #define USART7_BASE_NS (0x40098000u) - /** Peripheral USART7 base pointer */ - #define USART7 ((USART_Type *)USART7_BASE) - /** Peripheral USART7 base pointer */ - #define USART7_NS ((USART_Type *)USART7_BASE_NS) - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS_NS { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS_NS { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS } -#else - /** Peripheral USART0 base address */ - #define USART0_BASE (0x40086000u) - /** Peripheral USART0 base pointer */ - #define USART0 ((USART_Type *)USART0_BASE) - /** Peripheral USART1 base address */ - #define USART1_BASE (0x40087000u) - /** Peripheral USART1 base pointer */ - #define USART1 ((USART_Type *)USART1_BASE) - /** Peripheral USART2 base address */ - #define USART2_BASE (0x40088000u) - /** Peripheral USART2 base pointer */ - #define USART2 ((USART_Type *)USART2_BASE) - /** Peripheral USART3 base address */ - #define USART3_BASE (0x40089000u) - /** Peripheral USART3 base pointer */ - #define USART3 ((USART_Type *)USART3_BASE) - /** Peripheral USART4 base address */ - #define USART4_BASE (0x4008A000u) - /** Peripheral USART4 base pointer */ - #define USART4 ((USART_Type *)USART4_BASE) - /** Peripheral USART5 base address */ - #define USART5_BASE (0x40096000u) - /** Peripheral USART5 base pointer */ - #define USART5 ((USART_Type *)USART5_BASE) - /** Peripheral USART6 base address */ - #define USART6_BASE (0x40097000u) - /** Peripheral USART6 base pointer */ - #define USART6 ((USART_Type *)USART6_BASE) - /** Peripheral USART7 base address */ - #define USART7_BASE (0x40098000u) - /** Peripheral USART7 base pointer */ - #define USART7 ((USART_Type *)USART7_BASE) - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } -#endif -/** Interrupt vectors for the USART peripheral type */ -#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group USART_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer - * @{ - */ - -/** USB - Register Layout Typedef */ -typedef struct { - __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ - __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ - __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ - __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ - __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ - __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ - __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ - __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ - __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ - __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ - __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ - uint8_t RESERVED_0[8]; - __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ -} USB_Type; - -/* ---------------------------------------------------------------------------- - -- USB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Register_Masks USB Register Masks - * @{ - */ - -/*! @name DEVCMDSTAT - USB Device Command/Status register */ -/*! @{ */ - -#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) -#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) -/*! DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit - * is set, the device will respond on packets for function address DEV_ADDR. When receiving a - * SetAddress Control Request from the USB host, software must program the new address before - * completing the status phase of the SetAddress Control Request. - */ -#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) - -#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) -#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) -/*! DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. - */ -#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) - -#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) -#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) -/*! SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this - * bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW - * must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the - * CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. - */ -#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) - -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) -/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: - * 0b0..USB_NEEDCLK has normal function. - * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. - */ -#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) - -#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) -#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) -/*! LPM_SUP - LPM Supported: - * 0b0..LPM not supported. - * 0b1..LPM supported. - */ -#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) - -#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) -#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) -/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) - -#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) -#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) -/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) - -#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) -#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) -/*! INTONNAK_CO - Interrupt on NAK for control OUT EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) - -#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) -#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) -/*! INTONNAK_CI - Interrupt on NAK for control IN EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) - -#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) -#define USB_DEVCMDSTAT_DCON_SHIFT (16U) -/*! DCON - Device status - connect. The connect bit must be set by SW to indicate that the device - * must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and - * the VBUSDEBOUNCED bit is one. - */ -#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) - -#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) -#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) -/*! DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set - * to 1 when the device hasn't seen any activity on its upstream port for more than 3 - * milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and - * the software writes a 0 to it, the device will generate a remote wake-up. This will only happen - * when the device is connected (Connect bit = 1). When the device is not connected or not - * suspended, a writing a 0 has no effect. Writing a 1 never has an effect. - */ -#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) - -#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) -#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) -/*! LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is - * set to 1 by HW when the device has acknowledged the LPM request from the USB host and the - * Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend - * bit = 1) and the software writes a zero to this bit, the device will generate a remote - * walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this - * bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the - * LPM_SUPP bit is equal to one. - */ -#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) - -#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) -#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) -/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake - * bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the - * host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset - * is received. Software can use this bit to check if the remote wake-up feature is enabled by the - * host for the LPM transaction. - */ -#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) - -#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) -#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) -/*! DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up - * resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. - */ -#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) - -#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) -#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) -/*! DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit - * toggles. The suspend bit can toggle because: - The device goes in the suspended state - The - * device is disconnected - The device receives resume signaling on its upstream port. The bit is - * reset by writing a one to it. - */ -#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) - -#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) -#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) -/*! DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On - * a bus reset the device will automatically go to the default state (unconfigured and responding - * to address 0). The bit is reset by writing a one to it. - */ -#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) - -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) -/*! VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when - * Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and - * the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. - */ -#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) -/*! @} */ - -/*! @name INFO - USB Info register */ -/*! @{ */ - -#define USB_INFO_FRAME_NR_MASK (0x7FFU) -#define USB_INFO_FRAME_NR_SHIFT (0U) -/*! FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF. - * In case no SOF was received by the device at the beginning of a frame, the frame number - * returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC - * error, the frame number returned will be the corrupted frame number as received by the device. - */ -#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) - -#define USB_INFO_ERR_CODE_MASK (0x7800U) -#define USB_INFO_ERR_CODE_SHIFT (11U) -/*! ERR_CODE - The error code which last occurred: - * 0b0000..No error - * 0b0001..PID encoding error - * 0b0010..PID unknown - * 0b0011..Packet unexpected - * 0b0100..Token CRC error - * 0b0101..Data CRC error - * 0b0110..Time out - * 0b0111..Babble - * 0b1000..Truncated EOP - * 0b1001..Sent/Received NAK - * 0b1010..Sent Stall - * 0b1011..Overrun - * 0b1100..Sent empty packet - * 0b1101..Bitstuff error - * 0b1110..Sync error - * 0b1111..Wrong data toggle - */ -#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) - -#define USB_INFO_MINREV_MASK (0xFF0000U) -#define USB_INFO_MINREV_SHIFT (16U) -/*! MINREV - Minor Revision. - */ -#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK) - -#define USB_INFO_MAJREV_MASK (0xFF000000U) -#define USB_INFO_MAJREV_SHIFT (24U) -/*! MAJREV - Major Revision. - */ -#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK) -/*! @} */ - -/*! @name EPLISTSTART - USB EP Command/Status List start address */ -/*! @{ */ - -#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) -#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) -/*! EP_LIST - Start address of the USB EP Command/Status List. - */ -#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) -/*! @} */ - -/*! @name DATABUFSTART - USB Data buffer start address */ -/*! @{ */ - -#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) -#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) -/*! DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located. - */ -#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) -/*! @} */ - -/*! @name LPM - USB Link Power Management register */ -/*! @{ */ - -#define USB_LPM_HIRD_HW_MASK (0xFU) -#define USB_LPM_HIRD_HW_SHIFT (0U) -/*! HIRD_HW - Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token - */ -#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) - -#define USB_LPM_HIRD_SW_MASK (0xF0U) -#define USB_LPM_HIRD_SW_SHIFT (4U) -/*! HIRD_SW - Host Initiated Resume Duration - SW. This is the time duration required by the USB - * device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. - */ -#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) - -#define USB_LPM_DATA_PENDING_MASK (0x100U) -#define USB_LPM_DATA_PENDING_SHIFT (8U) -/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will - * return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and - * this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has - * still data pending and LPM is supported, it must set this bit to 1. - */ -#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) -/*! @} */ - -/*! @name EPSKIP - USB Endpoint skip */ -/*! @{ */ - -#define USB_EPSKIP_SKIP_MASK (0x3FFU) -#define USB_EPSKIP_SKIP_SHIFT (0U) -/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must - * deactivate the buffer assigned to this endpoint and return control back to software. When HW has - * deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An - * interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, - * HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. - */ -#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) -/*! @} */ - -/*! @name EPINUSE - USB Endpoint Buffer in use */ -/*! @{ */ - -#define USB_EPINUSE_BUF_MASK (0x3FCU) -#define USB_EPINUSE_BUF_SHIFT (2U) -/*! BUF - Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer - * 0. 1: HW is accessing buffer 1. - */ -#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) -/*! @} */ - -/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ -/*! @{ */ - -#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) -#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) -/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: - * Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding - * EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle - * the EPINUSE bit when it clears the Active bit for the buffer. - */ -#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) -/*! @} */ - -/*! @name INTSTAT - USB interrupt status register */ -/*! @{ */ - -#define USB_INTSTAT_EP0OUT_MASK (0x1U) -#define USB_INTSTAT_EP0OUT_SHIFT (0U) -/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set - * if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is - * successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a - * NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a - * one to it. - */ -#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) - -#define USB_INTSTAT_EP0IN_MASK (0x2U) -#define USB_INTSTAT_EP0IN_SHIFT (1U) -/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if - * NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this - * bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can - * clear this bit by writing a one to it. - */ -#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) - -#define USB_INTSTAT_EP1OUT_MASK (0x4U) -#define USB_INTSTAT_EP1OUT_SHIFT (2U) -/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes - * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be - * set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by - * writing a one to it. - */ -#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) - -#define USB_INTSTAT_EP1IN_MASK (0x8U) -#define USB_INTSTAT_EP1IN_SHIFT (3U) -/*! EP1IN - Interrupt status register bit for the EP1 IN direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions - * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be - * set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing - * a one to it. - */ -#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) - -#define USB_INTSTAT_EP2OUT_MASK (0x10U) -#define USB_INTSTAT_EP2OUT_SHIFT (4U) -/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes - * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be - * set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by - * writing a one to it. - */ -#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) - -#define USB_INTSTAT_EP2IN_MASK (0x20U) -#define USB_INTSTAT_EP2IN_SHIFT (5U) -/*! EP2IN - Interrupt status register bit for the EP2 IN direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions - * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be - * set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing - * a one to it. - */ -#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) - -#define USB_INTSTAT_EP3OUT_MASK (0x40U) -#define USB_INTSTAT_EP3OUT_SHIFT (6U) -/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes - * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be - * set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by - * writing a one to it. - */ -#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) - -#define USB_INTSTAT_EP3IN_MASK (0x80U) -#define USB_INTSTAT_EP3IN_SHIFT (7U) -/*! EP3IN - Interrupt status register bit for the EP3 IN direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions - * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be - * set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing - * a one to it. - */ -#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) - -#define USB_INTSTAT_EP4OUT_MASK (0x100U) -#define USB_INTSTAT_EP4OUT_SHIFT (8U) -/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes - * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be - * set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by - * writing a one to it. - */ -#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) - -#define USB_INTSTAT_EP4IN_MASK (0x200U) -#define USB_INTSTAT_EP4IN_SHIFT (9U) -/*! EP4IN - Interrupt status register bit for the EP4 IN direction. This bit will be set if the - * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions - * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be - * set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing - * a one to it. - */ -#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) - -#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) -#define USB_INTSTAT_FRAME_INT_SHIFT (30U) -/*! FRAME_INT - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit - * and the DCON bit are set. This bit can be used by software when handling isochronous - * endpoints. Software can clear this bit by writing a one to it. - */ -#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) - -#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) -#define USB_INTSTAT_DEV_INT_SHIFT (31U) -/*! DEV_INT - Device status interrupt. This bit is set by HW when one of the bits in the Device - * Status Change register are set. Software can clear this bit by writing a one to it. - */ -#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) -/*! @} */ - -/*! @name INTEN - USB interrupt enable register */ -/*! @{ */ - -#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) -#define USB_INTEN_EP_INT_EN_SHIFT (0U) -/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing - * bit. - */ -#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) - -#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) -#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) -/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt - * routing bit. - */ -#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) - -#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) -#define USB_INTEN_DEV_INT_EN_SHIFT (31U) -/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing - * bit. - */ -#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) -/*! @} */ - -/*! @name INTSETSTAT - USB set interrupt status register */ -/*! @{ */ - -#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) -#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) -/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt - * status bit is set. When this register is read, the same value as the USB interrupt status register - * is returned. - */ -#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) - -#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) -#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) -/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt - * status bit is set. When this register is read, the same value as the USB interrupt status - * register is returned. - */ -#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) - -#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) -#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) -/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt - * status bit is set. When this register is read, the same value as the USB interrupt status - * register is returned. - */ -#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) -/*! @} */ - -/*! @name EPTOGGLE - USB Endpoint toggle register */ -/*! @{ */ - -#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) -#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) -/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. - */ -#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USB_Register_Masks */ - - -/* USB - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USB0 base address */ - #define USB0_BASE (0x50084000u) - /** Peripheral USB0 base address */ - #define USB0_BASE_NS (0x40084000u) - /** Peripheral USB0 base pointer */ - #define USB0 ((USB_Type *)USB0_BASE) - /** Peripheral USB0 base pointer */ - #define USB0_NS ((USB_Type *)USB0_BASE_NS) - /** Array initializer of USB peripheral base addresses */ - #define USB_BASE_ADDRS { USB0_BASE } - /** Array initializer of USB peripheral base pointers */ - #define USB_BASE_PTRS { USB0 } - /** Array initializer of USB peripheral base addresses */ - #define USB_BASE_ADDRS_NS { USB0_BASE_NS } - /** Array initializer of USB peripheral base pointers */ - #define USB_BASE_PTRS_NS { USB0_NS } -#else - /** Peripheral USB0 base address */ - #define USB0_BASE (0x40084000u) - /** Peripheral USB0 base pointer */ - #define USB0 ((USB_Type *)USB0_BASE) - /** Array initializer of USB peripheral base addresses */ - #define USB_BASE_ADDRS { USB0_BASE } - /** Array initializer of USB peripheral base pointers */ - #define USB_BASE_PTRS { USB0 } -#endif -/** Interrupt vectors for the USB peripheral type */ -#define USB_IRQS { USB0_IRQn } -#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBFSH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer - * @{ - */ - -/** USBFSH - Register Layout Typedef */ -typedef struct { - __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */ - __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */ - __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */ - __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */ - __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */ - __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */ - __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */ - __I uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */ - __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */ - __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */ - __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */ - __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */ - __I uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */ - __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */ - __I uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */ - __I uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */ - __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */ - __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */ - __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */ - __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */ - __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */ - __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */ - uint8_t RESERVED_0[4]; - __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */ -} USBFSH_Type; - -/* ---------------------------------------------------------------------------- - -- USBFSH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBFSH_Register_Masks USBFSH Register Masks - * @{ - */ - -/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */ -/*! @{ */ - -#define USBFSH_HCREVISION_REV_MASK (0xFFU) -#define USBFSH_HCREVISION_REV_SHIFT (0U) -/*! REV - Revision. - */ -#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK) -/*! @} */ - -/*! @name HCCONTROL - Defines the operating modes of the HC */ -/*! @{ */ - -#define USBFSH_HCCONTROL_CBSR_MASK (0x3U) -#define USBFSH_HCCONTROL_CBSR_SHIFT (0U) -/*! CBSR - ControlBulkServiceRatio. - */ -#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK) - -#define USBFSH_HCCONTROL_PLE_MASK (0x4U) -#define USBFSH_HCCONTROL_PLE_SHIFT (2U) -/*! PLE - PeriodicListEnable. - */ -#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK) - -#define USBFSH_HCCONTROL_IE_MASK (0x8U) -#define USBFSH_HCCONTROL_IE_SHIFT (3U) -/*! IE - IsochronousEnable. - */ -#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK) - -#define USBFSH_HCCONTROL_CLE_MASK (0x10U) -#define USBFSH_HCCONTROL_CLE_SHIFT (4U) -/*! CLE - ControlListEnable. - */ -#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK) - -#define USBFSH_HCCONTROL_BLE_MASK (0x20U) -#define USBFSH_HCCONTROL_BLE_SHIFT (5U) -/*! BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. - */ -#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK) - -#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U) -#define USBFSH_HCCONTROL_HCFS_SHIFT (6U) -/*! HCFS - HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL - * 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin - * 1 ms later. - */ -#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK) - -#define USBFSH_HCCONTROL_IR_MASK (0x100U) -#define USBFSH_HCCONTROL_IR_SHIFT (8U) -/*! IR - InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. - */ -#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK) - -#define USBFSH_HCCONTROL_RWC_MASK (0x200U) -#define USBFSH_HCCONTROL_RWC_SHIFT (9U) -/*! RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling. - */ -#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK) - -#define USBFSH_HCCONTROL_RWE_MASK (0x400U) -#define USBFSH_HCCONTROL_RWE_SHIFT (10U) -/*! RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature - * upon the detection of upstream resume signaling. - */ -#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK) -/*! @} */ - -/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */ -/*! @{ */ - -#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U) -#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U) -/*! HCR - HostControllerReset This bit is set by HCD to initiate a software reset of HC. - */ -#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK) - -#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U) -#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U) -/*! CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. - */ -#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK) - -#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U) -#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U) -/*! BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. - */ -#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK) - -#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U) -#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U) -/*! OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC. - */ -#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK) - -#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U) -#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U) -/*! SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error. - */ -#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK) -/*! @} */ - -/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */ -/*! @{ */ - -#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U) -/*! SO - SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and - * after the update of HccaFrameNumber. - */ -#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U) -/*! WDH - WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead. - */ -#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U) -/*! SF - StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. - */ -#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U) -/*! RD - ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling. - */ -#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U) -/*! UE - UnrecoverableError This bit is set when HC detects a system error not related to USB. - */ -#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U) -/*! FNO - FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value, - * from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated. - */ -#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U) -/*! RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any - * of HcRhPortStatus[NumberofDownstreamPort] has changed. - */ -#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK) - -#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U) -#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U) -/*! OC - OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus. - */ -#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK) -/*! @} */ - -/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */ -/*! @{ */ - -#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U) -/*! SO - Scheduling Overrun interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK) - -#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U) -/*! WDH - HcDoneHead Writeback interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK) - -#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U) -/*! SF - Start of Frame interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK) - -#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U) -/*! RD - Resume Detect interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK) - -#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U) -/*! UE - Unrecoverable Error interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK) - -#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U) -/*! FNO - Frame Number Overflow interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK) - -#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U) -/*! RHSC - Root Hub Status Change interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK) - -#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U) -#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U) -/*! OC - Ownership Change interrupt. - */ -#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK) - -#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U) -#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U) -/*! MIE - Master Interrupt Enable. - */ -#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK) -/*! @} */ - -/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */ -/*! @{ */ - -#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U) -/*! SO - Scheduling Overrun interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U) -/*! WDH - HcDoneHead Writeback interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U) -/*! SF - Start of Frame interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U) -/*! RD - Resume Detect interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U) -/*! UE - Unrecoverable Error interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U) -/*! FNO - Frame Number Overflow interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U) -/*! RHSC - Root Hub Status Change interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U) -#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U) -/*! OC - Ownership Change interrupt. - */ -#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK) - -#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U) -#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U) -/*! MIE - A 0 written to this field is ignored by HC. - */ -#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK) -/*! @} */ - -/*! @name HCHCCA - Contains the physical address of the host controller communication area */ -/*! @{ */ - -#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U) -#define USBFSH_HCHCCA_HCCA_SHIFT (8U) -/*! HCCA - Base address of the Host Controller Communication Area. - */ -#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK) -/*! @} */ - -/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */ -/*! @{ */ - -#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U) -/*! PCED - The content of this register is updated by HC after a periodic ED is processed. - */ -#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK) -/*! @} */ - -/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */ -/*! @{ */ - -#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U) -#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U) -/*! CHED - HC traverses the Control list starting with the HcControlHeadED pointer. - */ -#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK) -/*! @} */ - -/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */ -/*! @{ */ - -#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U) -/*! CCED - ControlCurrentED. - */ -#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK) -/*! @} */ - -/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */ -/*! @{ */ - -#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U) -#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U) -/*! BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer. - */ -#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK) -/*! @} */ - -/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */ -/*! @{ */ - -#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U) -/*! BCED - BulkCurrentED This is advanced to the next ED after the HC has served the current one. - */ -#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK) -/*! @} */ - -/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */ -/*! @{ */ - -#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U) -#define USBFSH_HCDONEHEAD_DH_SHIFT (4U) -/*! DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. - */ -#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK) -/*! @} */ - -/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */ -/*! @{ */ - -#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU) -#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U) -/*! FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times. - */ -#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK) - -#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U) -#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U) -/*! FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data - * Packet Counter at the beginning of each frame. - */ -#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK) - -#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U) -#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U) -/*! FIT - FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval. - */ -#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK) -/*! @} */ - -/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */ -/*! @{ */ - -#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU) -#define USBFSH_HCFMREMAINING_FR_SHIFT (0U) -/*! FR - FrameRemaining This counter is decremented at each bit time. - */ -#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK) - -#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U) -#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U) -/*! FRT - FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval - * whenever FrameRemaining reaches 0. - */ -#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK) -/*! @} */ - -/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */ -/*! @{ */ - -#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU) -#define USBFSH_HCFMNUMBER_FN_SHIFT (0U) -/*! FN - FrameNumber This is incremented when HcFmRemaining is re-loaded. - */ -#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK) -/*! @} */ - -/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */ -/*! @{ */ - -#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU) -#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U) -/*! PS - PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization. - */ -#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK) -/*! @} */ - -/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */ -/*! @{ */ - -#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU) -#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U) -/*! LST - LSThreshold This field contains a value which is compared to the FrameRemaining field - * prior to initiating a Low Speed transaction. - */ -#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK) -/*! @} */ - -/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */ -/*! @{ */ - -#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU) -#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U) -/*! NDP - NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub. - */ -#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK) - -#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U) -#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U) -/*! PSM - PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled. - */ -#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK) - -#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U) -#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U) -/*! NPS - NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered. - */ -#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK) - -#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U) -#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U) -/*! DT - DeviceType This bit specifies that the root hub is not a compound device. - */ -#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK) - -#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U) -#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U) -/*! OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported. - */ -#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK) - -#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U) -#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U) -/*! NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported. - */ -#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK) - -#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U) -#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U) -/*! POTPGT - PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before - * accessing a powered-on port of the root hub. - */ -#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK) -/*! @} */ - -/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */ -/*! @{ */ - -#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU) -#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U) -/*! DR - DeviceRemovable Each bit is dedicated to a port of the Root Hub. - */ -#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK) - -#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U) -#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U) -/*! PPCM - PortPowerControlMask Each bit indicates if a port is affected by a global power control - * command when PowerSwitchingMode is set. - */ -#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK) -/*! @} */ - -/*! @name HCRHSTATUS - This register is divided into two parts */ -/*! @{ */ - -#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U) -#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U) -/*! LPS - (read) LocalPowerStatus The Root Hub does not support the local power status feature; - * thus, this bit is always read as 0. - */ -#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK) - -#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U) -#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U) -/*! OCI - OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented. - */ -#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK) - -#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U) -#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U) -/*! DRWE - (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume - * event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected - * interrupt. - */ -#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK) - -#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U) -#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U) -/*! LPSC - (read) LocalPowerStatusChange The root hub does not support the local power status feature. - */ -#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK) - -#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U) -#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U) -/*! OCIC - OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register. - */ -#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK) - -#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U) -#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U) -/*! CRWE - (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable. - */ -#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK) -/*! @} */ - -/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */ -/*! @{ */ - -#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U) -#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U) -/*! CCS - (read) CurrentConnectStatus This bit reflects the current state of the downstream port. - */ -#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK) - -#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U) -#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U) -/*! PES - (read) PortEnableStatus This bit indicates whether the port is enabled or disabled. - */ -#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK) - -#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U) -#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U) -/*! PSS - (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence. - */ -#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK) - -#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U) -#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U) -/*! POCI - (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in - * such a way that overcurrent conditions are reported on a per-port basis. - */ -#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK) - -#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U) -#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U) -/*! PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. - */ -#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK) - -#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U) -#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U) -/*! PPS - (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type - * of power switching implemented. - */ -#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK) - -#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U) -#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U) -/*! LSDA - (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. - */ -#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK) - -#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U) -#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U) -/*! CSC - ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. - */ -#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK) - -#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U) -#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U) -/*! PESC - PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared. - */ -#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK) - -#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U) -#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U) -/*! PSSC - PortSuspendStatusChange This bit is set when the full resume sequence is completed. - */ -#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK) - -#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U) -#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U) -/*! OCIC - PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis. - */ -#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK) - -#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U) -#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U) -/*! PRSC - PortResetStatusChange This bit is set at the end of the 10 ms port reset signal. - */ -#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK) -/*! @} */ - -/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ -/*! @{ */ - -#define USBFSH_PORTMODE_ID_MASK (0x1U) -#define USBFSH_PORTMODE_ID_SHIFT (0U) -/*! ID - Port ID pin value. - */ -#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK) - -#define USBFSH_PORTMODE_ID_EN_MASK (0x100U) -#define USBFSH_PORTMODE_ID_EN_SHIFT (8U) -/*! ID_EN - Port ID pin pull-up enable. - */ -#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK) - -#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) -#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U) -/*! DEV_ENABLE - 1: device 0: host. - */ -#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBFSH_Register_Masks */ - - -/* USBFSH - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USBFSH base address */ - #define USBFSH_BASE (0x500A2000u) - /** Peripheral USBFSH base address */ - #define USBFSH_BASE_NS (0x400A2000u) - /** Peripheral USBFSH base pointer */ - #define USBFSH ((USBFSH_Type *)USBFSH_BASE) - /** Peripheral USBFSH base pointer */ - #define USBFSH_NS ((USBFSH_Type *)USBFSH_BASE_NS) - /** Array initializer of USBFSH peripheral base addresses */ - #define USBFSH_BASE_ADDRS { USBFSH_BASE } - /** Array initializer of USBFSH peripheral base pointers */ - #define USBFSH_BASE_PTRS { USBFSH } - /** Array initializer of USBFSH peripheral base addresses */ - #define USBFSH_BASE_ADDRS_NS { USBFSH_BASE_NS } - /** Array initializer of USBFSH peripheral base pointers */ - #define USBFSH_BASE_PTRS_NS { USBFSH_NS } -#else - /** Peripheral USBFSH base address */ - #define USBFSH_BASE (0x400A2000u) - /** Peripheral USBFSH base pointer */ - #define USBFSH ((USBFSH_Type *)USBFSH_BASE) - /** Array initializer of USBFSH peripheral base addresses */ - #define USBFSH_BASE_ADDRS { USBFSH_BASE } - /** Array initializer of USBFSH peripheral base pointers */ - #define USBFSH_BASE_PTRS { USBFSH } -#endif -/** Interrupt vectors for the USBFSH peripheral type */ -#define USBFSH_IRQS { USB0_IRQn } -#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBFSH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBHSD Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer - * @{ - */ - -/** USBHSD - Register Layout Typedef */ -typedef struct { - __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ - __I uint32_t INFO; /**< USB Info register, offset: 0x4 */ - __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ - __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ - __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ - __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ - __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ - __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ - __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ - __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ - __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ - uint8_t RESERVED_0[8]; - __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ -} USBHSD_Type; - -/* ---------------------------------------------------------------------------- - -- USBHSD Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSD_Register_Masks USBHSD Register Masks - * @{ - */ - -/*! @name DEVCMDSTAT - USB Device Command/Status register */ -/*! @{ */ - -#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) -#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) -/*! DEV_ADDR - USB device address. - */ -#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK) - -#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U) -#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U) -/*! DEV_EN - USB device enable. - */ -#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK) - -#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U) -#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U) -/*! SETUP - SETUP token received. - */ -#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK) - -#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) -#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) -/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:. - */ -#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK) - -#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U) -#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U) -/*! LPM_SUP - LPM Supported:. - */ -#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK) - -#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) -/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP:. - */ -#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK) - -#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) -/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP:. - */ -#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK) - -#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) -/*! INTONNAK_CO - Interrupt on NAK for control OUT EP:. - */ -#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK) - -#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) -/*! INTONNAK_CI - Interrupt on NAK for control IN EP:. - */ -#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK) - -#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U) -#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U) -/*! DCON - Device status - connect. - */ -#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK) - -#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U) -#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U) -/*! DSUS - Device status - suspend. - */ -#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK) - -#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) -#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U) -/*! LPM_SUS - Device status - LPM Suspend. - */ -#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK) - -#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) -#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U) -/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. - */ -#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK) - -#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U) -#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U) -/*! Speed - This field indicates the speed at which the device operates: 00b: reserved 01b: - * full-speed 10b: high-speed 11b: super-speed (reserved for future use). - */ -#define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK) - -#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U) -#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U) -/*! DCON_C - Device status - connect change. - */ -#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK) - -#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) -#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U) -/*! DSUS_C - Device status - suspend change. - */ -#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK) - -#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U) -#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U) -/*! DRES_C - Device status - reset change. - */ -#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK) - -#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U) -#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U) -/*! VBUS_DEBOUNCED - This bit indicates if VBUS is detected or not. - */ -#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK) - -#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U) -#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U) -/*! PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification. - * 0b000..Test mode disabled. - * 0b001..Test_J. - * 0b010..Test_K. - * 0b011..Test_SE0_NAK. - * 0b100..Test_Packet. - * 0b101..Test_Force_Enable. - */ -#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK) -/*! @} */ - -/*! @name INFO - USB Info register */ -/*! @{ */ - -#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU) -#define USBHSD_INFO_FRAME_NR_SHIFT (0U) -/*! FRAME_NR - Frame number. - */ -#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK) - -#define USBHSD_INFO_ERR_CODE_MASK (0x7800U) -#define USBHSD_INFO_ERR_CODE_SHIFT (11U) -/*! ERR_CODE - The error code which last occurred:. - */ -#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK) - -#define USBHSD_INFO_MINREV_MASK (0xFF0000U) -#define USBHSD_INFO_MINREV_SHIFT (16U) -/*! MINREV - Minor revision. - */ -#define USBHSD_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MINREV_SHIFT)) & USBHSD_INFO_MINREV_MASK) - -#define USBHSD_INFO_MAJREV_MASK (0xFF000000U) -#define USBHSD_INFO_MAJREV_SHIFT (24U) -/*! MAJREV - Major revision. - */ -#define USBHSD_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MAJREV_SHIFT)) & USBHSD_INFO_MAJREV_MASK) -/*! @} */ - -/*! @name EPLISTSTART - USB EP Command/Status List start address */ -/*! @{ */ - -#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U) -#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U) -/*! EP_LIST_PRG - Programmable portion of the USB EP Command/Status List address. - */ -#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK) - -#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U) -#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U) -/*! EP_LIST_FIXED - Fixed portion of USB EP Command/Status List address. - */ -#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK) -/*! @} */ - -/*! @name DATABUFSTART - USB Data buffer start address */ -/*! @{ */ - -#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU) -#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U) -/*! DA_BUF - Start address of the memory page where all endpoint data buffers are located. - */ -#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK) -/*! @} */ - -/*! @name LPM - USB Link Power Management register */ -/*! @{ */ - -#define USBHSD_LPM_HIRD_HW_MASK (0xFU) -#define USBHSD_LPM_HIRD_HW_SHIFT (0U) -/*! HIRD_HW - Host Initiated Resume Duration - HW. - */ -#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK) - -#define USBHSD_LPM_HIRD_SW_MASK (0xF0U) -#define USBHSD_LPM_HIRD_SW_SHIFT (4U) -/*! HIRD_SW - Host Initiated Resume Duration - SW. - */ -#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK) - -#define USBHSD_LPM_DATA_PENDING_MASK (0x100U) -#define USBHSD_LPM_DATA_PENDING_SHIFT (8U) -/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will - * return a NYET handshake on every LPM token it receives. - */ -#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK) -/*! @} */ - -/*! @name EPSKIP - USB Endpoint skip */ -/*! @{ */ - -#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU) -#define USBHSD_EPSKIP_SKIP_SHIFT (0U) -/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must - * deactivate the buffer assigned to this endpoint and return control back to software. - */ -#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK) -/*! @} */ - -/*! @name EPINUSE - USB Endpoint Buffer in use */ -/*! @{ */ - -#define USBHSD_EPINUSE_BUF_MASK (0xFFCU) -#define USBHSD_EPINUSE_BUF_SHIFT (2U) -/*! BUF - Buffer in use: This register has one bit per physical endpoint. - */ -#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK) -/*! @} */ - -/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ -/*! @{ */ - -#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU) -#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U) -/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. - */ -#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK) -/*! @} */ - -/*! @name INTSTAT - USB interrupt status register */ -/*! @{ */ - -#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U) -#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U) -/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. - */ -#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK) - -#define USBHSD_INTSTAT_EP0IN_MASK (0x2U) -#define USBHSD_INTSTAT_EP0IN_SHIFT (1U) -/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. - */ -#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK) - -#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U) -#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U) -/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. - */ -#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK) - -#define USBHSD_INTSTAT_EP1IN_MASK (0x8U) -#define USBHSD_INTSTAT_EP1IN_SHIFT (3U) -/*! EP1IN - Interrupt status register bit for the EP1 IN direction. - */ -#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK) - -#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U) -#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U) -/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. - */ -#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK) - -#define USBHSD_INTSTAT_EP2IN_MASK (0x20U) -#define USBHSD_INTSTAT_EP2IN_SHIFT (5U) -/*! EP2IN - Interrupt status register bit for the EP2 IN direction. - */ -#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK) - -#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U) -#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U) -/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. - */ -#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK) - -#define USBHSD_INTSTAT_EP3IN_MASK (0x80U) -#define USBHSD_INTSTAT_EP3IN_SHIFT (7U) -/*! EP3IN - Interrupt status register bit for the EP3 IN direction. - */ -#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK) - -#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U) -#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U) -/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. - */ -#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK) - -#define USBHSD_INTSTAT_EP4IN_MASK (0x200U) -#define USBHSD_INTSTAT_EP4IN_SHIFT (9U) -/*! EP4IN - Interrupt status register bit for the EP4 IN direction. - */ -#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK) - -#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U) -#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U) -/*! EP5OUT - Interrupt status register bit for the EP5 OUT direction. - */ -#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK) - -#define USBHSD_INTSTAT_EP5IN_MASK (0x800U) -#define USBHSD_INTSTAT_EP5IN_SHIFT (11U) -/*! EP5IN - Interrupt status register bit for the EP5 IN direction. - */ -#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK) - -#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U) -#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U) -/*! FRAME_INT - Frame interrupt. - */ -#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK) - -#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U) -#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U) -/*! DEV_INT - Device status interrupt. - */ -#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK) -/*! @} */ - -/*! @name INTEN - USB interrupt enable register */ -/*! @{ */ - -#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU) -#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U) -/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line. - */ -#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK) - -#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U) -#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U) -/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line. - */ -#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK) - -#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U) -#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U) -/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW - * interrupt is generated on the interrupt line. - */ -#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK) -/*! @} */ - -/*! @name INTSETSTAT - USB set interrupt status register */ -/*! @{ */ - -#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU) -#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U) -/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. - */ -#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK) - -#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) -#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) -/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. - */ -#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK) - -#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) -#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U) -/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. - */ -#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK) -/*! @} */ - -/*! @name EPTOGGLE - USB Endpoint toggle register */ -/*! @{ */ - -#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU) -#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U) -/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. - */ -#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBHSD_Register_Masks */ - - -/* USBHSD - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USBHSD base address */ - #define USBHSD_BASE (0x50094000u) - /** Peripheral USBHSD base address */ - #define USBHSD_BASE_NS (0x40094000u) - /** Peripheral USBHSD base pointer */ - #define USBHSD ((USBHSD_Type *)USBHSD_BASE) - /** Peripheral USBHSD base pointer */ - #define USBHSD_NS ((USBHSD_Type *)USBHSD_BASE_NS) - /** Array initializer of USBHSD peripheral base addresses */ - #define USBHSD_BASE_ADDRS { USBHSD_BASE } - /** Array initializer of USBHSD peripheral base pointers */ - #define USBHSD_BASE_PTRS { USBHSD } - /** Array initializer of USBHSD peripheral base addresses */ - #define USBHSD_BASE_ADDRS_NS { USBHSD_BASE_NS } - /** Array initializer of USBHSD peripheral base pointers */ - #define USBHSD_BASE_PTRS_NS { USBHSD_NS } -#else - /** Peripheral USBHSD base address */ - #define USBHSD_BASE (0x40094000u) - /** Peripheral USBHSD base pointer */ - #define USBHSD ((USBHSD_Type *)USBHSD_BASE) - /** Array initializer of USBHSD peripheral base addresses */ - #define USBHSD_BASE_ADDRS { USBHSD_BASE } - /** Array initializer of USBHSD peripheral base pointers */ - #define USBHSD_BASE_PTRS { USBHSD } -#endif -/** Interrupt vectors for the USBHSD peripheral type */ -#define USBHSD_IRQS { USB1_IRQn } -#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBHSD_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBHSH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer - * @{ - */ - -/** USBHSH - Register Layout Typedef */ -typedef struct { - __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */ - __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */ - __IO uint32_t ATLPTD; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */ - __IO uint32_t ISOPTD; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */ - __IO uint32_t INTPTD; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */ - __IO uint32_t DATAPAYLOAD; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */ - __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */ - __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */ - __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */ - __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */ - __IO uint32_t ATLPTDD; /**< Done map for each ATL PTD, offset: 0x30 */ - __IO uint32_t ATLPTDS; /**< Skip map for each ATL PTD, offset: 0x34 */ - __IO uint32_t ISOPTDD; /**< Done map for each ISO PTD, offset: 0x38 */ - __IO uint32_t ISOPTDS; /**< Skip map for each ISO PTD, offset: 0x3C */ - __IO uint32_t INTPTDD; /**< Done map for each INT PTD, offset: 0x40 */ - __IO uint32_t INTPTDS; /**< Skip map for each INT PTD, offset: 0x44 */ - __IO uint32_t LASTPTD; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */ - uint8_t RESERVED_1[4]; - __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */ -} USBHSH_Type; - -/* ---------------------------------------------------------------------------- - -- USBHSH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSH_Register_Masks USBHSH Register Masks - * @{ - */ - -/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */ -/*! @{ */ - -#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU) -#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U) -/*! CAPLENGTH - Capability Length: This is used as an offset. - */ -#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK) - -#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U) -#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U) -/*! CHIPID - Chip identification: indicates major and minor revision of the IP: [31:24] = Major - * revision [23:16] = Minor revision Major revisions used: 0x01: USB2. - */ -#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK) -/*! @} */ - -/*! @name HCSPARAMS - Host Controller Structural Parameters */ -/*! @{ */ - -#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU) -#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U) -/*! N_PORTS - This register specifies the number of physical downstream ports implemented on this host controller. - */ -#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK) - -#define USBHSH_HCSPARAMS_PPC_MASK (0x10U) -#define USBHSH_HCSPARAMS_PPC_SHIFT (4U) -/*! PPC - This field indicates whether the host controller implementation includes port power control. - */ -#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK) - -#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U) -#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U) -/*! P_INDICATOR - This bit indicates whether the ports support port indicator control. - */ -#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK) -/*! @} */ - -/*! @name FLADJ_FRINDEX - Frame Length Adjustment */ -/*! @{ */ - -#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU) -#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U) -/*! FLADJ - Frame Length Timing Value. - */ -#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK) - -#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U) -#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U) -/*! FRINDEX - Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet. - */ -#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) -/*! @} */ - -/*! @name ATLPTD - Memory base address where ATL PTD0 is stored */ -/*! @{ */ - -#define USBHSH_ATLPTD_ATL_CUR_MASK (0x1F0U) -#define USBHSH_ATLPTD_ATL_CUR_SHIFT (4U) -/*! ATL_CUR - This indicates the current PTD that is used by the hardware when it is processing the ATL list. - */ -#define USBHSH_ATLPTD_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_CUR_SHIFT)) & USBHSH_ATLPTD_ATL_CUR_MASK) - -#define USBHSH_ATLPTD_ATL_BASE_MASK (0xFFFFFE00U) -#define USBHSH_ATLPTD_ATL_BASE_SHIFT (9U) -/*! ATL_BASE - Base address to be used by the hardware to find the start of the ATL list. - */ -#define USBHSH_ATLPTD_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_BASE_SHIFT)) & USBHSH_ATLPTD_ATL_BASE_MASK) -/*! @} */ - -/*! @name ISOPTD - Memory base address where ISO PTD0 is stored */ -/*! @{ */ - -#define USBHSH_ISOPTD_ISO_FIRST_MASK (0x3E0U) -#define USBHSH_ISOPTD_ISO_FIRST_SHIFT (5U) -/*! ISO_FIRST - This indicates the first PTD that is used by the hardware when it is processing the ISO list. - */ -#define USBHSH_ISOPTD_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_FIRST_SHIFT)) & USBHSH_ISOPTD_ISO_FIRST_MASK) - -#define USBHSH_ISOPTD_ISO_BASE_MASK (0xFFFFFC00U) -#define USBHSH_ISOPTD_ISO_BASE_SHIFT (10U) -/*! ISO_BASE - Base address to be used by the hardware to find the start of the ISO list. - */ -#define USBHSH_ISOPTD_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_BASE_SHIFT)) & USBHSH_ISOPTD_ISO_BASE_MASK) -/*! @} */ - -/*! @name INTPTD - Memory base address where INT PTD0 is stored */ -/*! @{ */ - -#define USBHSH_INTPTD_INT_FIRST_MASK (0x3E0U) -#define USBHSH_INTPTD_INT_FIRST_SHIFT (5U) -/*! INT_FIRST - This indicates the first PTD that is used by the hardware when it is processing the INT list. - */ -#define USBHSH_INTPTD_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_FIRST_SHIFT)) & USBHSH_INTPTD_INT_FIRST_MASK) - -#define USBHSH_INTPTD_INT_BASE_MASK (0xFFFFFC00U) -#define USBHSH_INTPTD_INT_BASE_SHIFT (10U) -/*! INT_BASE - Base address to be used by the hardware to find the start of the INT list. - */ -#define USBHSH_INTPTD_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_BASE_SHIFT)) & USBHSH_INTPTD_INT_BASE_MASK) -/*! @} */ - -/*! @name DATAPAYLOAD - Memory base address that indicates the start of the data payload buffers */ -/*! @{ */ - -#define USBHSH_DATAPAYLOAD_DAT_BASE_MASK (0xFFFF0000U) -#define USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT (16U) -/*! DAT_BASE - Base address to be used by the hardware to find the start of the data payload section. - */ -#define USBHSH_DATAPAYLOAD_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT)) & USBHSH_DATAPAYLOAD_DAT_BASE_MASK) -/*! @} */ - -/*! @name USBCMD - USB Command register */ -/*! @{ */ - -#define USBHSH_USBCMD_RS_MASK (0x1U) -#define USBHSH_USBCMD_RS_SHIFT (0U) -/*! RS - Run/Stop: 1b = Run. - */ -#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK) - -#define USBHSH_USBCMD_HCRESET_MASK (0x2U) -#define USBHSH_USBCMD_HCRESET_SHIFT (1U) -/*! HCRESET - Host Controller Reset: This control bit is used by the software to reset the host controller. - */ -#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK) - -#define USBHSH_USBCMD_FLS_MASK (0xCU) -#define USBHSH_USBCMD_FLS_SHIFT (2U) -/*! FLS - Frame List Size: This field specifies the size of the frame list. - */ -#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK) - -#define USBHSH_USBCMD_LHCR_MASK (0x80U) -#define USBHSH_USBCMD_LHCR_SHIFT (7U) -/*! LHCR - Light Host Controller Reset: This bit allows the driver software to reset the host - * controller without affecting the state of the ports. - */ -#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK) - -#define USBHSH_USBCMD_ATL_EN_MASK (0x100U) -#define USBHSH_USBCMD_ATL_EN_SHIFT (8U) -/*! ATL_EN - ATL List enabled. - */ -#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK) - -#define USBHSH_USBCMD_ISO_EN_MASK (0x200U) -#define USBHSH_USBCMD_ISO_EN_SHIFT (9U) -/*! ISO_EN - ISO List enabled. - */ -#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK) - -#define USBHSH_USBCMD_INT_EN_MASK (0x400U) -#define USBHSH_USBCMD_INT_EN_SHIFT (10U) -/*! INT_EN - INT List enabled. - */ -#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK) -/*! @} */ - -/*! @name USBSTS - USB Interrupt Status register */ -/*! @{ */ - -#define USBHSH_USBSTS_PCD_MASK (0x4U) -#define USBHSH_USBSTS_PCD_SHIFT (2U) -/*! PCD - Port Change Detect: The host controller sets this bit to logic 1 when any port has a - * change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a - * result of a J-K transition detected on a suspended port. - */ -#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK) - -#define USBHSH_USBSTS_FLR_MASK (0x8U) -#define USBHSH_USBSTS_FLR_SHIFT (3U) -/*! FLR - Frame List Rollover: The host controller sets this bit to logic 1 when the frame list - * index rolls over its maximum value to 0. - */ -#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK) - -#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U) -#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U) -/*! ATL_IRQ - ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed. - */ -#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK) - -#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U) -#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U) -/*! ISO_IRQ - ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed. - */ -#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK) - -#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U) -#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U) -/*! INT_IRQ - INT IRQ: Indicates that an INT PTD (with I-bit set) was completed. - */ -#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK) - -#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U) -#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U) -/*! SOF_IRQ - SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set. - */ -#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK) -/*! @} */ - -/*! @name USBINTR - USB Interrupt Enable register */ -/*! @{ */ - -#define USBHSH_USBINTR_PCDE_MASK (0x4U) -#define USBHSH_USBINTR_PCDE_SHIFT (2U) -/*! PCDE - Port Change Detect Interrupt Enable: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK) - -#define USBHSH_USBINTR_FLRE_MASK (0x8U) -#define USBHSH_USBINTR_FLRE_SHIFT (3U) -/*! FLRE - Frame List Rollover Interrupt Enable: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK) - -#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U) -#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U) -/*! ATL_IRQ_E - ATL IRQ Enable bit: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK) - -#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U) -#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U) -/*! ISO_IRQ_E - ISO IRQ Enable bit: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK) - -#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U) -#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U) -/*! INT_IRQ_E - INT IRQ Enable bit: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK) - -#define USBHSH_USBINTR_SOF_E_MASK (0x80000U) -#define USBHSH_USBINTR_SOF_E_SHIFT (19U) -/*! SOF_E - SOF Interrupt Enable bit: 1: enable 0: disable. - */ -#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK) -/*! @} */ - -/*! @name PORTSC1 - Port Status and Control register */ -/*! @{ */ - -#define USBHSH_PORTSC1_CCS_MASK (0x1U) -#define USBHSH_PORTSC1_CCS_SHIFT (0U) -/*! CCS - Current Connect Status: Logic 1 indicates a device is present on the port. - */ -#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK) - -#define USBHSH_PORTSC1_CSC_MASK (0x2U) -#define USBHSH_PORTSC1_CSC_SHIFT (1U) -/*! CSC - Connect Status Change: Logic 1 means that the value of CCS has changed. - */ -#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK) - -#define USBHSH_PORTSC1_PED_MASK (0x4U) -#define USBHSH_PORTSC1_PED_SHIFT (2U) -/*! PED - Port Enabled/Disabled. - */ -#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK) - -#define USBHSH_PORTSC1_PEDC_MASK (0x8U) -#define USBHSH_PORTSC1_PEDC_SHIFT (3U) -/*! PEDC - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed. - */ -#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK) - -#define USBHSH_PORTSC1_OCA_MASK (0x10U) -#define USBHSH_PORTSC1_OCA_SHIFT (4U) -/*! OCA - Over-current active: Logic 1 means that this port has an over-current condition. - */ -#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK) - -#define USBHSH_PORTSC1_OCC_MASK (0x20U) -#define USBHSH_PORTSC1_OCC_SHIFT (5U) -/*! OCC - Over-current change: Logic 1 means that the value of OCA has changed. - */ -#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK) - -#define USBHSH_PORTSC1_FPR_MASK (0x40U) -#define USBHSH_PORTSC1_FPR_SHIFT (6U) -/*! FPR - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port. - */ -#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK) - -#define USBHSH_PORTSC1_SUSP_MASK (0x80U) -#define USBHSH_PORTSC1_SUSP_SHIFT (7U) -/*! SUSP - Suspend: Logic 1 means port is in the suspend state. - */ -#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK) - -#define USBHSH_PORTSC1_PR_MASK (0x100U) -#define USBHSH_PORTSC1_PR_SHIFT (8U) -/*! PR - Port Reset: Logic 1 means the port is in the reset state. - */ -#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK) - -#define USBHSH_PORTSC1_LS_MASK (0xC00U) -#define USBHSH_PORTSC1_LS_SHIFT (10U) -/*! LS - Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. - */ -#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK) - -#define USBHSH_PORTSC1_PP_MASK (0x1000U) -#define USBHSH_PORTSC1_PP_SHIFT (12U) -/*! PP - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register. - */ -#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK) - -#define USBHSH_PORTSC1_PIC_MASK (0xC000U) -#define USBHSH_PORTSC1_PIC_SHIFT (14U) -/*! PIC - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the - * HCSPARAMS register is logic 0. - */ -#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK) - -#define USBHSH_PORTSC1_PTC_MASK (0xF0000U) -#define USBHSH_PORTSC1_PTC_SHIFT (16U) -/*! PTC - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value. - */ -#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK) - -#define USBHSH_PORTSC1_PSPD_MASK (0x300000U) -#define USBHSH_PORTSC1_PSPD_SHIFT (20U) -/*! PSPD - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved. - */ -#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK) - -#define USBHSH_PORTSC1_WOO_MASK (0x400000U) -#define USBHSH_PORTSC1_WOO_SHIFT (22U) -/*! WOO - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to - * overcurrent conditions as wake-up events. - */ -#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK) -/*! @} */ - -/*! @name ATLPTDD - Done map for each ATL PTD */ -/*! @{ */ - -#define USBHSH_ATLPTDD_ATL_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_ATLPTDD_ATL_DONE_SHIFT (0U) -/*! ATL_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - */ -#define USBHSH_ATLPTDD_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDD_ATL_DONE_SHIFT)) & USBHSH_ATLPTDD_ATL_DONE_MASK) -/*! @} */ - -/*! @name ATLPTDS - Skip map for each ATL PTD */ -/*! @{ */ - -#define USBHSH_ATLPTDS_ATL_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_ATLPTDS_ATL_SKIP_SHIFT (0U) -/*! ATL_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be - * skipped, independent of the V bit setting. - */ -#define USBHSH_ATLPTDS_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDS_ATL_SKIP_SHIFT)) & USBHSH_ATLPTDS_ATL_SKIP_MASK) -/*! @} */ - -/*! @name ISOPTDD - Done map for each ISO PTD */ -/*! @{ */ - -#define USBHSH_ISOPTDD_ISO_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_ISOPTDD_ISO_DONE_SHIFT (0U) -/*! ISO_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - */ -#define USBHSH_ISOPTDD_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDD_ISO_DONE_SHIFT)) & USBHSH_ISOPTDD_ISO_DONE_MASK) -/*! @} */ - -/*! @name ISOPTDS - Skip map for each ISO PTD */ -/*! @{ */ - -#define USBHSH_ISOPTDS_ISO_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_ISOPTDS_ISO_SKIP_SHIFT (0U) -/*! ISO_SKIP - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - */ -#define USBHSH_ISOPTDS_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDS_ISO_SKIP_SHIFT)) & USBHSH_ISOPTDS_ISO_SKIP_MASK) -/*! @} */ - -/*! @name INTPTDD - Done map for each INT PTD */ -/*! @{ */ - -#define USBHSH_INTPTDD_INT_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_INTPTDD_INT_DONE_SHIFT (0U) -/*! INT_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - */ -#define USBHSH_INTPTDD_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDD_INT_DONE_SHIFT)) & USBHSH_INTPTDD_INT_DONE_MASK) -/*! @} */ - -/*! @name INTPTDS - Skip map for each INT PTD */ -/*! @{ */ - -#define USBHSH_INTPTDS_INT_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_INTPTDS_INT_SKIP_SHIFT (0U) -/*! INT_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be - * skipped, independent of the V bit setting. - */ -#define USBHSH_INTPTDS_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDS_INT_SKIP_SHIFT)) & USBHSH_INTPTDS_INT_SKIP_MASK) -/*! @} */ - -/*! @name LASTPTD - Marks the last PTD in the list for ISO, INT and ATL */ -/*! @{ */ - -#define USBHSH_LASTPTD_ATL_LAST_MASK (0x1FU) -#define USBHSH_LASTPTD_ATL_LAST_SHIFT (0U) -/*! ATL_LAST - If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed. - */ -#define USBHSH_LASTPTD_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ATL_LAST_SHIFT)) & USBHSH_LASTPTD_ATL_LAST_MASK) - -#define USBHSH_LASTPTD_ISO_LAST_MASK (0x1F00U) -#define USBHSH_LASTPTD_ISO_LAST_SHIFT (8U) -/*! ISO_LAST - This indicates the last PTD in the ISO list. - */ -#define USBHSH_LASTPTD_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ISO_LAST_SHIFT)) & USBHSH_LASTPTD_ISO_LAST_MASK) - -#define USBHSH_LASTPTD_INT_LAST_MASK (0x1F0000U) -#define USBHSH_LASTPTD_INT_LAST_SHIFT (16U) -/*! INT_LAST - This indicates the last PTD in the INT list. - */ -#define USBHSH_LASTPTD_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_INT_LAST_SHIFT)) & USBHSH_LASTPTD_INT_LAST_MASK) -/*! @} */ - -/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ -/*! @{ */ - -#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) -#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U) -/*! DEV_ENABLE - If this bit is set to one, one of the ports will behave as a USB device. - */ -#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK) - -#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U) -#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U) -/*! SW_CTRL_PDCOM - This bit indicates if the PHY power-down input is controlled by software or by hardware. - */ -#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK) - -#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U) -#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U) -/*! SW_PDCOM - This bit is only used when SW_CTRL_PDCOM is set to 1b. - */ -#define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBHSH_Register_Masks */ - - -/* USBHSH - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USBHSH base address */ - #define USBHSH_BASE (0x500A3000u) - /** Peripheral USBHSH base address */ - #define USBHSH_BASE_NS (0x400A3000u) - /** Peripheral USBHSH base pointer */ - #define USBHSH ((USBHSH_Type *)USBHSH_BASE) - /** Peripheral USBHSH base pointer */ - #define USBHSH_NS ((USBHSH_Type *)USBHSH_BASE_NS) - /** Array initializer of USBHSH peripheral base addresses */ - #define USBHSH_BASE_ADDRS { USBHSH_BASE } - /** Array initializer of USBHSH peripheral base pointers */ - #define USBHSH_BASE_PTRS { USBHSH } - /** Array initializer of USBHSH peripheral base addresses */ - #define USBHSH_BASE_ADDRS_NS { USBHSH_BASE_NS } - /** Array initializer of USBHSH peripheral base pointers */ - #define USBHSH_BASE_PTRS_NS { USBHSH_NS } -#else - /** Peripheral USBHSH base address */ - #define USBHSH_BASE (0x400A3000u) - /** Peripheral USBHSH base pointer */ - #define USBHSH ((USBHSH_Type *)USBHSH_BASE) - /** Array initializer of USBHSH peripheral base addresses */ - #define USBHSH_BASE_ADDRS { USBHSH_BASE } - /** Array initializer of USBHSH peripheral base pointers */ - #define USBHSH_BASE_PTRS { USBHSH } -#endif -/** Interrupt vectors for the USBHSH peripheral type */ -#define USBHSH_IRQS { USB1_IRQn } -#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBHSH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBPHY Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer - * @{ - */ - -/** USBPHY - Register Layout Typedef */ -typedef struct { - __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ - __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ - __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ - __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ - __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ - __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ - __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ - __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ - __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ - __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ - __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ - __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ - __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ - __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ - __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ - __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ - __I uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ - uint8_t RESERVED_0[92]; - __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */ - __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */ - __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */ - __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */ - uint8_t RESERVED_1[16]; - __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */ - __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */ - __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */ - __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */ - uint8_t RESERVED_2[48]; - __IO uint32_t ANACTRLr; /**< USB PHY Analog Control Register, offset: 0x100 */ - __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */ - __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */ - __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */ -} USBPHY_Type; - -/* ---------------------------------------------------------------------------- - -- USBPHY Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBPHY_Register_Masks USBPHY Register Masks - * @{ - */ - -/*! @name PWD - USB PHY Power-Down Register */ -/*! @{ */ - -#define USBPHY_PWD_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) - -#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) - -#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) - -#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) - -#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) - -#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) - -#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) -/*! @} */ - -/*! @name PWD_SET - USB PHY Power-Down Register */ -/*! @{ */ - -#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) - -#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) - -#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) - -#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) - -#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) - -#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) - -#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) -/*! @} */ - -/*! @name PWD_CLR - USB PHY Power-Down Register */ -/*! @{ */ - -#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) - -#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) - -#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) - -#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) - -#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) - -#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) - -#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) -/*! @} */ - -/*! @name PWD_TOG - USB PHY Power-Down Register */ -/*! @{ */ - -#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) - -#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) - -#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) - -#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) - -#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) - -#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) - -#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) -/*! @} */ - -/*! @name TX - USB PHY Transmitter Control Register */ -/*! @{ */ - -#define USBPHY_TX_D_CAL_MASK (0xFU) -#define USBPHY_TX_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) - -#define USBPHY_TX_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK) - -#define USBPHY_TX_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DN_SHIFT)) & USBPHY_TX_TXENCAL45DN_MASK) - -#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) - -#define USBPHY_TX_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name TX_SET - USB PHY Transmitter Control Register */ -/*! @{ */ - -#define USBPHY_TX_SET_D_CAL_MASK (0xFU) -#define USBPHY_TX_SET_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) - -#define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK) - -#define USBPHY_TX_SET_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_SET_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_SET_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DN_SHIFT)) & USBPHY_TX_SET_TXENCAL45DN_MASK) - -#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) - -#define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_SET_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name TX_CLR - USB PHY Transmitter Control Register */ -/*! @{ */ - -#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) -#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) - -#define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK) - -#define USBPHY_TX_CLR_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_CLR_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_CLR_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DN_MASK) - -#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) - -#define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_CLR_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name TX_TOG - USB PHY Transmitter Control Register */ -/*! @{ */ - -#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) -#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) - -#define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK) - -#define USBPHY_TX_TOG_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_TOG_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_TOG_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DN_MASK) - -#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) - -#define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_TOG_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name RX - USB PHY Receiver Control Register */ -/*! @{ */ - -#define USBPHY_RX_ENVADJ_MASK (0x7U) -#define USBPHY_RX_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) - -#define USBPHY_RX_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) - -#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) -/*! @} */ - -/*! @name RX_SET - USB PHY Receiver Control Register */ -/*! @{ */ - -#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) -#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) - -#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) - -#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) -/*! @} */ - -/*! @name RX_CLR - USB PHY Receiver Control Register */ -/*! @{ */ - -#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) -#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) - -#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) - -#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) -/*! @} */ - -/*! @name RX_TOG - USB PHY Receiver Control Register */ -/*! @{ */ - -#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) -#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) - -#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) - -#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) -/*! @} */ - -/*! @name CTRL - USB PHY General Control Register */ -/*! @{ */ - -#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) - -#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) -#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) -#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) - -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) - -#define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK) - -#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) -#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) -#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) - -#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) -#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) -#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) - -#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) -#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) -#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) - -#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) -#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) -#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) - -#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) - -#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) - -#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) - -#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) -#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) -#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) - -#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) -#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) -#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) - -#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) - -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) - -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) - -#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) -#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) -#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) - -#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) -#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) -#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) - -#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) -#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT (25U) -#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK) - -#define USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK (0x4000000U) -#define USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT (26U) -#define USBPHY_CTRL_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK) - -#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) - -#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) - -#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) - -#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_SET - USB PHY General Control Register */ -/*! @{ */ - -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) - -#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) -#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) -#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) - -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) - -#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK) - -#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) -#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) -#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) - -#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) -#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) -#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) - -#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) -#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) -#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) - -#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) -#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) -#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) - -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) - -#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) - -#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) - -#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) -#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) -#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) - -#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) -#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) -#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) - -#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) - -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) - -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) - -#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) -#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) -#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) - -#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) -#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) -#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) - -#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) -#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT (25U) -#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK) - -#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK (0x4000000U) -#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT (26U) -#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK) - -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) - -#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) - -#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) - -#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_CLR - USB PHY General Control Register */ -/*! @{ */ - -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) - -#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) -#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) -#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) - -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) - -#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK) - -#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) - -#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) -#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) -#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) - -#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) -#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) -#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) - -#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) -#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) -#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) - -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) - -#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) - -#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) - -#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) -#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) -#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) - -#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) -#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) -#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) - -#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) - -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) - -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) - -#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) -#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) -#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) - -#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) -#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) -#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) - -#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT (25U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK) - -#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK (0x4000000U) -#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT (26U) -#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK) - -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) - -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) - -#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) - -#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_TOG - USB PHY General Control Register */ -/*! @{ */ - -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) - -#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) -#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) -#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) - -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) - -#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK) - -#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) - -#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) -#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) -#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) - -#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) -#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) -#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) - -#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) -#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) -#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) - -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) - -#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) - -#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) - -#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) -#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) -#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) - -#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) -#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) -#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) - -#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) - -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) - -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) - -#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) -#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) -#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) - -#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) -#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) -#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) - -#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT (25U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK) - -#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK (0x4000000U) -#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT (26U) -#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK) - -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) - -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) - -#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) - -#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) -/*! @} */ - -/*! @name STATUS - USB PHY Status Register */ -/*! @{ */ - -#define USBPHY_STATUS_OK_STATUS_3V_MASK (0x1U) -#define USBPHY_STATUS_OK_STATUS_3V_SHIFT (0U) -#define USBPHY_STATUS_OK_STATUS_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OK_STATUS_3V_SHIFT)) & USBPHY_STATUS_OK_STATUS_3V_MASK) - -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) -/*! HOSTDISCONDETECT_STATUS - * 0b0..USB cable disconnect has not been detected at the local host - * 0b1..USB cable disconnect has been detected at the local host - */ -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) - -#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) -#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) -/*! DEVPLUGIN_STATUS - * 0b0..No attachment to a USB host is detected - * 0b1..Cable attachment to a USB host is detected - */ -#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) - -#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) -#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) -#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) -/*! @} */ - -/*! @name PLL_SIC - USB PHY PLL Control/Status Register */ -/*! @{ */ - -#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) - -#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) - -#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) - -#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) - -#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) - -#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) - -#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) - -#define USBPHY_PLL_SIC_PLL_PREDIV_MASK (0x40000000U) -#define USBPHY_PLL_SIC_PLL_PREDIV_SHIFT (30U) -#define USBPHY_PLL_SIC_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_PREDIV_MASK) - -#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */ -/*! @{ */ - -#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) - -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) - -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK (0x40000000U) -#define USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT (30U) -#define USBPHY_PLL_SIC_SET_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK) - -#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */ -/*! @{ */ - -#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) - -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) - -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK (0x40000000U) -#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT (30U) -#define USBPHY_PLL_SIC_CLR_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK) - -#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */ -/*! @{ */ - -#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) - -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) - -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK (0x40000000U) -#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT (30U) -#define USBPHY_PLL_SIC_TOG_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK) - -#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */ -/*! @{ */ - -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U) -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U) -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U) -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U) -#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK (0x2000U) -#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. - * 0b1..Select the external ID value. - */ -#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) -#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. - * 0b1..Select the external VBUS VALID value. - */ -#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK) - -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK (0x80000U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT (19U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK) - -#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x700000U) -#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b000..Powers down the VBUS_VALID comparator - * 0b111..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK) - -#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */ -/*! @{ */ - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U) -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U) -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U) -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U) -#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK (0x2000U) -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. - * 0b1..Select the external ID value. - */ -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. - * 0b1..Select the external VBUS VALID value. - */ -#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK (0x80000U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT (19U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U) -#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b000..Powers down the VBUS_VALID comparator - * 0b111..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK) - -#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */ -/*! @{ */ - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U) -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U) -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U) -#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK (0x2000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. - * 0b1..Select the external ID value. - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - * 0b0..Select the muxed value chosen using VBUS_OVERRIDE_EN. - * 0b1..Select the external VBUS VALID value. - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK (0x80000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT (19U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b000..Powers down the VBUS_VALID comparator - * 0b111..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK) - -#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */ -/*! @{ */ - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U) -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U) -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U) -#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK (0x2000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - * 0b0..Select the muxed value chosen using ID_OVERRIDE_EN. - * 0b1..Select the external ID value. - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. - * 0b1..Select the external VBUS VALID value. - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK (0x80000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT (19U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b000..Powers down the VBUS_VALID comparator - * 0b111..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK) - -#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) -/*! @} */ - -/*! @name ANACTRL - USB PHY Analog Control Register */ -/*! @{ */ - -#define USBPHY_ANACTRL_LVI_EN_MASK (0x2U) -#define USBPHY_ANACTRL_LVI_EN_SHIFT (1U) -#define USBPHY_ANACTRL_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_LVI_EN_SHIFT)) & USBPHY_ANACTRL_LVI_EN_MASK) - -#define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU) -#define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U) -#define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) - -#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) -/*! @} */ - -/*! @name ANACTRL_SET - USB PHY Analog Control Register */ -/*! @{ */ - -#define USBPHY_ANACTRL_SET_LVI_EN_MASK (0x2U) -#define USBPHY_ANACTRL_SET_LVI_EN_SHIFT (1U) -#define USBPHY_ANACTRL_SET_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_LVI_EN_SHIFT)) & USBPHY_ANACTRL_SET_LVI_EN_MASK) - -#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU) -#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U) -#define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK) - -#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) -/*! @} */ - -/*! @name ANACTRL_CLR - USB PHY Analog Control Register */ -/*! @{ */ - -#define USBPHY_ANACTRL_CLR_LVI_EN_MASK (0x2U) -#define USBPHY_ANACTRL_CLR_LVI_EN_SHIFT (1U) -#define USBPHY_ANACTRL_CLR_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_LVI_EN_SHIFT)) & USBPHY_ANACTRL_CLR_LVI_EN_MASK) - -#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU) -#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U) -#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK) - -#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) -/*! @} */ - -/*! @name ANACTRL_TOG - USB PHY Analog Control Register */ -/*! @{ */ - -#define USBPHY_ANACTRL_TOG_LVI_EN_MASK (0x2U) -#define USBPHY_ANACTRL_TOG_LVI_EN_SHIFT (1U) -#define USBPHY_ANACTRL_TOG_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_LVI_EN_SHIFT)) & USBPHY_ANACTRL_TOG_LVI_EN_MASK) - -#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU) -#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U) -#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK) - -#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBPHY_Register_Masks */ - - -/* USBPHY - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral USBPHY base address */ - #define USBPHY_BASE (0x50038000u) - /** Peripheral USBPHY base address */ - #define USBPHY_BASE_NS (0x40038000u) - /** Peripheral USBPHY base pointer */ - #define USBPHY ((USBPHY_Type *)USBPHY_BASE) - /** Peripheral USBPHY base pointer */ - #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) - /** Array initializer of USBPHY peripheral base addresses */ - #define USBPHY_BASE_ADDRS { USBPHY_BASE } - /** Array initializer of USBPHY peripheral base pointers */ - #define USBPHY_BASE_PTRS { USBPHY } - /** Array initializer of USBPHY peripheral base addresses */ - #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } - /** Array initializer of USBPHY peripheral base pointers */ - #define USBPHY_BASE_PTRS_NS { USBPHY_NS } -#else - /** Peripheral USBPHY base address */ - #define USBPHY_BASE (0x40038000u) - /** Peripheral USBPHY base pointer */ - #define USBPHY ((USBPHY_Type *)USBPHY_BASE) - /** Array initializer of USBPHY peripheral base addresses */ - #define USBPHY_BASE_ADDRS { USBPHY_BASE } - /** Array initializer of USBPHY peripheral base pointers */ - #define USBPHY_BASE_PTRS { USBPHY } -#endif -/** Interrupt vectors for the USBPHY peripheral type */ -#define USBPHY_IRQS { USB1_PHY_IRQn } - -/*! - * @} - */ /* end of group USBPHY_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- UTICK Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer - * @{ - */ - -/** UTICK - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ - __IO uint32_t STAT; /**< Status register., offset: 0x4 */ - __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ - __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ - __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ -} UTICK_Type; - -/* ---------------------------------------------------------------------------- - -- UTICK Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Register_Masks UTICK Register Masks - * @{ - */ - -/*! @name CTRL - Control register. */ -/*! @{ */ - -#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) -#define UTICK_CTRL_DELAYVAL_SHIFT (0U) -/*! DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer - * clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer. - */ -#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) - -#define UTICK_CTRL_REPEAT_MASK (0x80000000U) -#define UTICK_CTRL_REPEAT_SHIFT (31U) -/*! REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. - */ -#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) -/*! @} */ - -/*! @name STAT - Status register. */ -/*! @{ */ - -#define UTICK_STAT_INTR_MASK (0x1U) -#define UTICK_STAT_INTR_SHIFT (0U) -/*! INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any - * value to this register clears this flag. - */ -#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) - -#define UTICK_STAT_ACTIVE_MASK (0x2U) -#define UTICK_STAT_ACTIVE_SHIFT (1U) -/*! ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. - */ -#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) -/*! @} */ - -/*! @name CFG - Capture configuration register. */ -/*! @{ */ - -#define UTICK_CFG_CAPEN0_MASK (0x1U) -#define UTICK_CFG_CAPEN0_SHIFT (0U) -/*! CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled. - */ -#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) - -#define UTICK_CFG_CAPEN1_MASK (0x2U) -#define UTICK_CFG_CAPEN1_SHIFT (1U) -/*! CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled. - */ -#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) - -#define UTICK_CFG_CAPEN2_MASK (0x4U) -#define UTICK_CFG_CAPEN2_SHIFT (2U) -/*! CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled. - */ -#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) - -#define UTICK_CFG_CAPEN3_MASK (0x8U) -#define UTICK_CFG_CAPEN3_SHIFT (3U) -/*! CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled. - */ -#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) - -#define UTICK_CFG_CAPPOL0_MASK (0x100U) -#define UTICK_CFG_CAPPOL0_SHIFT (8U) -/*! CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. - */ -#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) - -#define UTICK_CFG_CAPPOL1_MASK (0x200U) -#define UTICK_CFG_CAPPOL1_SHIFT (9U) -/*! CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. - */ -#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) - -#define UTICK_CFG_CAPPOL2_MASK (0x400U) -#define UTICK_CFG_CAPPOL2_SHIFT (10U) -/*! CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. - */ -#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) - -#define UTICK_CFG_CAPPOL3_MASK (0x800U) -#define UTICK_CFG_CAPPOL3_SHIFT (11U) -/*! CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. - */ -#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) -/*! @} */ - -/*! @name CAPCLR - Capture clear register. */ -/*! @{ */ - -#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) -#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) -/*! CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value. - */ -#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) - -#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) -#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) -/*! CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value. - */ -#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) - -#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) -#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) -/*! CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value. - */ -#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) - -#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) -#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) -/*! CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value. - */ -#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) -/*! @} */ - -/*! @name CAP - Capture register . */ -/*! @{ */ - -#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) -#define UTICK_CAP_CAP_VALUE_SHIFT (0U) -/*! CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower - * than the actual value of the Micro-tick Timer at the moment of the capture event. - */ -#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) - -#define UTICK_CAP_VALID_MASK (0x80000000U) -#define UTICK_CAP_VALID_SHIFT (31U) -/*! VALID - Capture Valid. When 1, a value has been captured based on a transition of the related - * UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. - */ -#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) -/*! @} */ - -/* The count of UTICK_CAP */ -#define UTICK_CAP_COUNT (4U) - - -/*! - * @} - */ /* end of group UTICK_Register_Masks */ - - -/* UTICK - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE (0x5000E000u) - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE_NS (0x4000E000u) - /** Peripheral UTICK0 base pointer */ - #define UTICK0 ((UTICK_Type *)UTICK0_BASE) - /** Peripheral UTICK0 base pointer */ - #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS { UTICK0_BASE } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS { UTICK0 } - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS_NS { UTICK0_NS } -#else - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE (0x4000E000u) - /** Peripheral UTICK0 base pointer */ - #define UTICK0 ((UTICK_Type *)UTICK0_BASE) - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS { UTICK0_BASE } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS { UTICK0 } -#endif -/** Interrupt vectors for the UTICK peripheral type */ -#define UTICK_IRQS { UTICK0_IRQn } - -/*! - * @} - */ /* end of group UTICK_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- WWDT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer - * @{ - */ - -/** WWDT - Register Layout Typedef */ -typedef struct { - __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ - __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ - __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ - __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ - uint8_t RESERVED_0[4]; - __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ - __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ -} WWDT_Type; - -/* ---------------------------------------------------------------------------- - -- WWDT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Register_Masks WWDT Register Masks - * @{ - */ - -/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ -/*! @{ */ - -#define WWDT_MOD_WDEN_MASK (0x1U) -#define WWDT_MOD_WDEN_SHIFT (0U) -/*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the - * watchdog timer will run permanently. - * 0b0..Stop. The watchdog timer is stopped. - * 0b1..Run. The watchdog timer is running. - */ -#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) - -#define WWDT_MOD_WDRESET_MASK (0x2U) -#define WWDT_MOD_WDRESET_SHIFT (1U) -/*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. - * 0b0..Interrupt. A watchdog time-out will not cause a chip reset. - * 0b1..Reset. A watchdog time-out will cause a chip reset. - */ -#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) - -#define WWDT_MOD_WDTOF_MASK (0x4U) -#define WWDT_MOD_WDTOF_SHIFT (2U) -/*! WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by - * events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a - * chip reset if WDRESET = 1. - */ -#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) - -#define WWDT_MOD_WDINT_MASK (0x8U) -#define WWDT_MOD_WDINT_SHIFT (3U) -/*! WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. - * Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the - * WARNINT value is equal to the value of the TV register. This can occur if the value of - * WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. - */ -#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) - -#define WWDT_MOD_WDPROTECT_MASK (0x10U) -#define WWDT_MOD_WDPROTECT_SHIFT (4U) -/*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. - * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time. - * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. - */ -#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) -/*! @} */ - -/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ -/*! @{ */ - -#define WWDT_TC_COUNT_MASK (0xFFFFFFU) -#define WWDT_TC_COUNT_SHIFT (0U) -/*! COUNT - Watchdog time-out value. - */ -#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) -/*! @} */ - -/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ -/*! @{ */ - -#define WWDT_FEED_FEED_MASK (0xFFU) -#define WWDT_FEED_FEED_SHIFT (0U) -/*! FEED - Feed value should be 0xAA followed by 0x55. - */ -#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) -/*! @} */ - -/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ -/*! @{ */ - -#define WWDT_TV_COUNT_MASK (0xFFFFFFU) -#define WWDT_TV_COUNT_SHIFT (0U) -/*! COUNT - Counter timer value. - */ -#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) -/*! @} */ - -/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ -/*! @{ */ - -#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) -#define WWDT_WARNINT_WARNINT_SHIFT (0U) -/*! WARNINT - Watchdog warning interrupt compare value. - */ -#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) -/*! @} */ - -/*! @name WINDOW - Watchdog Window compare value. */ -/*! @{ */ - -#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) -#define WWDT_WINDOW_WINDOW_SHIFT (0U) -/*! WINDOW - Watchdog window value. - */ -#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group WWDT_Register_Masks */ - - -/* WWDT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral WWDT base address */ - #define WWDT_BASE (0x5000C000u) - /** Peripheral WWDT base address */ - #define WWDT_BASE_NS (0x4000C000u) - /** Peripheral WWDT base pointer */ - #define WWDT ((WWDT_Type *)WWDT_BASE) - /** Peripheral WWDT base pointer */ - #define WWDT_NS ((WWDT_Type *)WWDT_BASE_NS) - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS { WWDT_BASE } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS { WWDT } - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS_NS { WWDT_BASE_NS } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS_NS { WWDT_NS } -#else - /** Peripheral WWDT base address */ - #define WWDT_BASE (0x4000C000u) - /** Peripheral WWDT base pointer */ - #define WWDT ((WWDT_Type *)WWDT_BASE) - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS { WWDT_BASE } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS { WWDT } -#endif -/** Interrupt vectors for the WWDT peripheral type */ -#define WWDT_IRQS { WDT_BOD_IRQn } - -/*! - * @} - */ /* end of group WWDT_Peripheral_Access_Layer */ - - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop - #else - #pragma pop - #endif -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -/*! - * @} - */ /* end of group Peripheral_access_layer */ - - -/* ---------------------------------------------------------------------------- - -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - * @{ - */ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang system_header - #endif -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma system_include -#endif - -/** - * @brief Mask and left-shift a bit field value for use in a register bit range. - * @param field Name of the register bit field. - * @param value Value of the bit field. - * @return Masked and shifted value. - */ -#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) -/** - * @brief Mask and right-shift a register value to extract a bit field value. - * @param field Name of the register bit field. - * @param value Value of the register. - * @return Masked and shifted bit field value. - */ -#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) - -/*! - * @} - */ /* end of group Bit_Field_Generic_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SDK Compatibility - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDK_Compatibility_Symbols SDK Compatibility - * @{ - */ - -/** High Speed SPI (Flexcomm 8) interrupt name */ -#define LSPI_HS_IRQn FLEXCOMM8_IRQn - -/*! - * @brief Get the chip value. - * - * @return chip version, 0x0: A0 version chip, 0x1: A1 version chip, 0xFF: invalid version. - */ -static inline uint32_t Chip_GetVersion(void) -{ - uint32_t deviceRevision; - - deviceRevision = SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK; - - if(0UL == deviceRevision) /* A0 device revision is 0 */ - { - return 0x0; - } - else if(1UL == deviceRevision) /* A1 device revision is 1 */ - { - return 0x1; - } - else - { - return 0xFF; - } -} - - -/*! - * @} - */ /* end of group SDK_Compatibility_Symbols */ - - -#endif /* _LPC55S69_CM33_CORE1_H_ */ - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.xml b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.xml deleted file mode 100644 index cbdca23f9db..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.xml +++ /dev/null @@ -1,85475 +0,0 @@ - - - nxp.com - LPC55S69_cm33_core1 - 1.0 - LPC55S69JBD100,LPC55S69JBD64,LPC55S69JEV98 - -Copyright 2016-2021 NXP -All rights reserved. - -SPDX-License-Identifier: BSD-3-Clause - - - CM33 - r2p0 - little - false - false - true - 3 - false - - 8 - 32 - - - FLASH_CFPA0 - FLASH_CFPA - FLASH_CFPA - FLASH_CFPA - 0x9E000 - - 0 - 0x200 - registers - - - - HEADER - no description available - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - VERSION - no description available - 0x4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - S_FW_Version - Secure firmware version (Monotonic counter) - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - NS_FW_Version - Non-Secure firmware version (Monotonic counter) - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - ROTKH_REVOKE - no description available - 0x18 - 32 - read-write - 0 - 0xFFFFFFFF - - - RoTK0_EN - RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - 0 - 2 - read-write - - - RoTK1_EN - RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - 2 - 2 - read-write - - - RoTK2_EN - RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - 4 - 2 - read-write - - - RoTK3_EN - RoT Key 3 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked - 6 - 2 - read-write - - - - - VENDOR_USAGE - no description available - 0x1C - 32 - read-write - 0 - 0xFFFFFFFF - - - DBG_VENDOR_USAGE - DBG_VENDOR_USAGE. - 0 - 16 - read-write - - - INVERSE_VALUE - inverse value of bits [15:0] - 16 - 16 - read-write - - - - - DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. - 0x20 - 32 - read-write - 0 - 0xFFFFFFFF - - - NIDEN - Non Secure non-invasive debug enable - 0 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - DBGEN - Non Secure debug enable - 1 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - SPNIDEN - Secure non-invasive debug enable - 2 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - SPIDEN - Secure invasive debug enable - 3 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - TAPEN - JTAG TAP enable - 4 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable - 5 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - ISP_CMD_EN - ISP Boot Command enable - 6 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - FA_CMD_EN - FA Command enable - 7 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - ME_CMD_EN - Flash Mass Erase Command enable - 8 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable - 9 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - UUID_CHECK - Enforce UUID match during Debug authentication. - 15 - 1 - read-write - - - INVERSE_VALUE - inverse value of bits [15:0] - 16 - 16 - read-write - - - - - DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. - 0x24 - 32 - read-write - 0 - 0xFFFFFFFF - - - NIDEN - Non Secure non-invasive debug fixed state - 0 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - DBGEN - Non Secure debug fixed state - 1 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - SPNIDEN - Secure non-invasive debug fixed state - 2 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - SPIDEN - Secure invasive debug fixed state - 3 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - TAPEN - JTAG TAP fixed state - 4 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state - 5 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - ISP_CMD_EN - ISP Boot Command fixed state - 6 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - FA_CMD_EN - FA Command fixed state - 7 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - ME_CMD_EN - Flash Mass Erase Command fixed state - 8 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state - 9 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - INVERSE_VALUE - inverse value of bits [15:0] - 16 - 16 - read-write - - - - - ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. - 0x28 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. - 0x2C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE0 - no description available - PRINCE_REGION0_IV_CODE - 0x30 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_HEADER0 - no description available - PRINCE_REGION0_IV_CODE - 0x30 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE1 - no description available - PRINCE_REGION0_IV_CODE - 0x34 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_HEADER1 - no description available - PRINCE_REGION0_IV_CODE - 0x34 - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - no description available - 0 - 2 - read-write - - - INDEX - no description available - 8 - 4 - read-write - - - SIZE - no description available - 24 - 6 - read-write - - - - - PRINCE_REGION0_IV_BODY0 - no description available - PRINCE_REGION0_IV_CODE - 0x38 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE2 - no description available - PRINCE_REGION0_IV_CODE - 0x38 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY1 - no description available - PRINCE_REGION0_IV_CODE - 0x3C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE3 - no description available - PRINCE_REGION0_IV_CODE - 0x3C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY2 - no description available - PRINCE_REGION0_IV_CODE - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE4 - no description available - PRINCE_REGION0_IV_CODE - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY3 - no description available - PRINCE_REGION0_IV_CODE - 0x44 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE5 - no description available - PRINCE_REGION0_IV_CODE - 0x44 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY4 - no description available - PRINCE_REGION0_IV_CODE - 0x48 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE6 - no description available - PRINCE_REGION0_IV_CODE - 0x48 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY5 - no description available - PRINCE_REGION0_IV_CODE - 0x4C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE7 - no description available - PRINCE_REGION0_IV_CODE - 0x4C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY6 - no description available - PRINCE_REGION0_IV_CODE - 0x50 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE8 - no description available - PRINCE_REGION0_IV_CODE - 0x50 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY7 - no description available - PRINCE_REGION0_IV_CODE - 0x54 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE9 - no description available - PRINCE_REGION0_IV_CODE - 0x54 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY8 - no description available - PRINCE_REGION0_IV_CODE - 0x58 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE10 - no description available - PRINCE_REGION0_IV_CODE - 0x58 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY9 - no description available - PRINCE_REGION0_IV_CODE - 0x5C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE11 - no description available - PRINCE_REGION0_IV_CODE - 0x5C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY10 - no description available - PRINCE_REGION0_IV_CODE - 0x60 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE12 - no description available - PRINCE_REGION0_IV_CODE - 0x60 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_BODY11 - no description available - PRINCE_REGION0_IV_CODE - 0x64 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION0_IV_CODE13 - no description available - PRINCE_REGION0_IV_CODE - 0x64 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE0 - no description available - PRINCE_REGION1_IV_CODE - 0x68 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_HEADER0 - no description available - PRINCE_REGION1_IV_CODE - 0x68 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE1 - no description available - PRINCE_REGION1_IV_CODE - 0x6C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_HEADER1 - no description available - PRINCE_REGION1_IV_CODE - 0x6C - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - no description available - 0 - 2 - read-write - - - INDEX - no description available - 8 - 4 - read-write - - - SIZE - no description available - 24 - 6 - read-write - - - - - PRINCE_REGION1_IV_BODY0 - no description available - PRINCE_REGION1_IV_CODE - 0x70 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE2 - no description available - PRINCE_REGION1_IV_CODE - 0x70 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY1 - no description available - PRINCE_REGION1_IV_CODE - 0x74 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE3 - no description available - PRINCE_REGION1_IV_CODE - 0x74 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY2 - no description available - PRINCE_REGION1_IV_CODE - 0x78 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE4 - no description available - PRINCE_REGION1_IV_CODE - 0x78 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY3 - no description available - PRINCE_REGION1_IV_CODE - 0x7C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE5 - no description available - PRINCE_REGION1_IV_CODE - 0x7C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY4 - no description available - PRINCE_REGION1_IV_CODE - 0x80 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE6 - no description available - PRINCE_REGION1_IV_CODE - 0x80 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY5 - no description available - PRINCE_REGION1_IV_CODE - 0x84 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE7 - no description available - PRINCE_REGION1_IV_CODE - 0x84 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY6 - no description available - PRINCE_REGION1_IV_CODE - 0x88 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE8 - no description available - PRINCE_REGION1_IV_CODE - 0x88 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY7 - no description available - PRINCE_REGION1_IV_CODE - 0x8C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE9 - no description available - PRINCE_REGION1_IV_CODE - 0x8C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY8 - no description available - PRINCE_REGION1_IV_CODE - 0x90 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE10 - no description available - PRINCE_REGION1_IV_CODE - 0x90 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY9 - no description available - PRINCE_REGION1_IV_CODE - 0x94 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE11 - no description available - PRINCE_REGION1_IV_CODE - 0x94 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY10 - no description available - PRINCE_REGION1_IV_CODE - 0x98 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE12 - no description available - PRINCE_REGION1_IV_CODE - 0x98 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_BODY11 - no description available - PRINCE_REGION1_IV_CODE - 0x9C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION1_IV_CODE13 - no description available - PRINCE_REGION1_IV_CODE - 0x9C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE0 - no description available - PRINCE_REGION2_IV_CODE - 0xA0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_HEADER0 - no description available - PRINCE_REGION2_IV_CODE - 0xA0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE1 - no description available - PRINCE_REGION2_IV_CODE - 0xA4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_HEADER1 - no description available - PRINCE_REGION2_IV_CODE - 0xA4 - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - no description available - 0 - 2 - read-write - - - INDEX - no description available - 8 - 4 - read-write - - - SIZE - no description available - 24 - 6 - read-write - - - - - PRINCE_REGION2_IV_BODY0 - no description available - PRINCE_REGION2_IV_CODE - 0xA8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE2 - no description available - PRINCE_REGION2_IV_CODE - 0xA8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY1 - no description available - PRINCE_REGION2_IV_CODE - 0xAC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE3 - no description available - PRINCE_REGION2_IV_CODE - 0xAC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY2 - no description available - PRINCE_REGION2_IV_CODE - 0xB0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE4 - no description available - PRINCE_REGION2_IV_CODE - 0xB0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY3 - no description available - PRINCE_REGION2_IV_CODE - 0xB4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE5 - no description available - PRINCE_REGION2_IV_CODE - 0xB4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY4 - no description available - PRINCE_REGION2_IV_CODE - 0xB8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE6 - no description available - PRINCE_REGION2_IV_CODE - 0xB8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY5 - no description available - PRINCE_REGION2_IV_CODE - 0xBC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE7 - no description available - PRINCE_REGION2_IV_CODE - 0xBC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY6 - no description available - PRINCE_REGION2_IV_CODE - 0xC0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE8 - no description available - PRINCE_REGION2_IV_CODE - 0xC0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY7 - no description available - PRINCE_REGION2_IV_CODE - 0xC4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE9 - no description available - PRINCE_REGION2_IV_CODE - 0xC4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY8 - no description available - PRINCE_REGION2_IV_CODE - 0xC8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE10 - no description available - PRINCE_REGION2_IV_CODE - 0xC8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY9 - no description available - PRINCE_REGION2_IV_CODE - 0xCC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE11 - no description available - PRINCE_REGION2_IV_CODE - 0xCC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY10 - no description available - PRINCE_REGION2_IV_CODE - 0xD0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE12 - no description available - PRINCE_REGION2_IV_CODE - 0xD0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_BODY11 - no description available - PRINCE_REGION2_IV_CODE - 0xD4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_REGION2_IV_CODE13 - no description available - PRINCE_REGION2_IV_CODE - 0xD4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - 56 - 0x4 - CUSTOMER_DEFINED[%s] - Customer Defined (Programable through ROM API) - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - 8 - 0x4 - SHA256_DIGEST[%s] - SHA256_DIGESTindex for DIGEST[((index * 32) + 31):(index * 32)] - 0x1E0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - - - FLASH_CFPA_SCRATCH - FLASH_CFPA - FLASH_CFPA - 0x9DE00 - - 0 - 0x200 - registers - - - - FLASH_CFPA1 - FLASH_CFPA - FLASH_CFPA - 0x9E200 - - 0 - 0x200 - registers - - - - FLASH_CMPA - FLASH_CMPA - FLASH_CMPA - 0x9E400 - - 0 - 0x200 - registers - - - - BOOT_CFG - no description available - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - DEFAULT_ISP_MODE - Default ISP mode: - 4 - 3 - read-write - - - AUTO_ISP - Auto ISP - 0 - - - USB_HID_ISP - USB_HID_ISP - 0x1 - - - UART_ISP - UART ISP - 0x2 - - - SPI_ISP - SPI Slave ISP - 0x3 - - - I2C_ISP - I2C Slave ISP - 0x4 - - - DISABLE - Disable ISP fall through - 0x7 - - - - - BOOT_SPEED - Core clock: - 7 - 2 - read-write - - - VALUE_0 - Defined by NMPA.SYSTEM_SPEED_CODE - 0 - - - VALUE_1 - 96MHz FRO - 0x1 - - - VALUE_2 - 48MHz FRO - 0x2 - - - - - BOOT_FAILURE_PIN - GPIO port and pin number to use for indicating failure reason. The toggle rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO pin - 24 - 8 - read-write - - - - - SPI_FLASH_CFG - no description available - 0x4 - 32 - read-write - 0 - 0xFFFFFFFF - - - SPI_RECOVERY_BOOT_EN - SPI flash recovery boot is enabled, if non-zero value is written to this field. - 0 - 5 - read-write - - - - - USB_ID - no description available - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - USB_VENDOR_ID - no description available - 0 - 16 - read-write - - - USB_PRODUCT_ID - no description available - 16 - 16 - read-write - - - - - SDIO_CFG - no description available - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - CC_SOCU_PIN - no description available - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - NIDEN - Non Secure non-invasive debug enable - 0 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - DBGEN - Non Secure debug enable - 1 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - SPNIDEN - Secure non-invasive debug enable - 2 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - SPIDEN - Secure invasive debug enable - 3 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - TAPEN - JTAG TAP enable - 4 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable - 5 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - ISP_CMD_EN - ISP Boot Command enable - 6 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - FA_CMD_EN - FA Command enable - 7 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - ME_CMD_EN - Flash Mass Erase Command enable - 8 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable - 9 - 1 - read-write - - - ENABLE - Use DAP to enable - 0 - - - DISABLE - Fixed state - 0x1 - - - - - UUID_CHECK - Enforce UUID match during Debug authentication. - 15 - 1 - read-write - - - INVERSE_VALUE - inverse value of bits [15:0] - 16 - 16 - read-write - - - - - CC_SOCU_DFLT - no description available - 0x14 - 32 - read-write - 0 - 0xFFFFFFFF - - - NIDEN - Non Secure non-invasive debug fixed state - 0 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - DBGEN - Non Secure debug fixed state - 1 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - SPNIDEN - Secure non-invasive debug fixed state - 2 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - SPIDEN - Secure invasive debug fixed state - 3 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - TAPEN - JTAG TAP fixed state - 4 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state - 5 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - ISP_CMD_EN - ISP Boot Command fixed state - 6 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - FA_CMD_EN - FA Command fixed state - 7 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - ME_CMD_EN - Flash Mass Erase Command fixed state - 8 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state - 9 - 1 - read-write - - - DISABLE - Disable - 0 - - - ENABLE - Enable - 0x1 - - - - - INVERSE_VALUE - inverse value of bits [15:0] - 16 - 16 - read-write - - - - - VENDOR_USAGE - no description available - 0x18 - 32 - read-write - 0 - 0xFFFFFFFF - - - VENDOR_USAGE - Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area. - 16 - 16 - read-write - - - - - SECURE_BOOT_CFG - Secure boot configuration flags. - 0x1C - 32 - read-write - 0 - 0xFFFFFFFF - - - RSA4K - Use RSA4096 keys only. - 0 - 2 - read-write - - - VALUE_0 - Allow RSA2048 and higher - 0 - - - VALUE_1 - RSA4096 only - 0x1 - - - VALUE_2 - RSA4096 only - 0x2 - - - VALUE_3 - RSA4096 only - 0x3 - - - - - DICE_INC_NXP_CFG - Include NXP area in DICE computation. - 2 - 2 - read-write - - - NOT_INCLUD - not included - 0 - - - INCLUD - included - 0x1 - - - VALUE_2 - included - 0x2 - - - VALUE_3 - included - 0x3 - - - - - DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. - 4 - 2 - read-write - - - NOT_INCLUD - not included - 0 - - - UNCLUD - included - 0x1 - - - VALUE_2 - included - 0x2 - - - VALUE_3 - included - 0x3 - - - - - SKIP_DICE - Skip DICE computation - 6 - 2 - read-write - - - ENABLE - Enable DICE - 0 - - - DISABLE - Disable DICE - 0x1 - - - VALUE_2 - Disable DICE - 0x2 - - - VALUE_3 - Disable DICE - 0x3 - - - - - TZM_IMAGE_TYPE - TrustZone-M mode - 8 - 2 - read-write - - - VALUE_0 - TZ-M image mode is taken from application image header - 0 - - - VALUE_1 - TZ-M disabled image, boots to non-secure mode - 0x1 - - - VALUE_2 - TZ-M enabled image, boots to secure mode - 0x2 - - - VALUE_3 - TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header - 0x3 - - - - - BLOCK_SET_KEY - Block PUF key code generation - 10 - 2 - read-write - - - ALLOW - Allow PUF Key Code generation - 0 - - - DISABLE - Disable PUF Key Code generation - 0x1 - - - VALUE_2 - Disable PUF Key Code generation - 0x2 - - - VALUE_3 - Disable PUF Key Code generation - 0x3 - - - - - BLOCK_ENROLL - Block PUF enrollement - 12 - 2 - read-write - - - ALLOW - Allow PUF enroll operation - 0 - - - DISABLE - Disable PUF enroll operation - 0x1 - - - VALUE_2 - Disable PUF enroll operation - 0x2 - - - VALUE_3 - Disable PUF enroll operation - 0x3 - - - - - DICE_INC_SEC_EPOCH - Include security EPOCH in DICE - 14 - 2 - read-write - - - SEC_BOOT_EN - Secure boot enable - 30 - 2 - read-write - - - DISABLE - Plain image (internal flash with or without CRC) - 0 - - - ENABLE - Boot signed images. (internal flash, RSA signed) - 0x1 - - - VALUE_2 - Boot signed images. (internal flash, RSA signed) - 0x2 - - - VALUE_3 - Boot signed images. (internal flash, RSA signed) - 0x3 - - - - - - - PRINCE_BASE_ADDR - no description available - 0x20 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADDR0_PRG - Programmable portion of the base address of region 0 - 0 - 4 - read-write - - - ADDR1_PRG - Programmable portion of the base address of region 1 - 4 - 4 - read-write - - - ADDR2_PRG - Programmable portion of the base address of region 2 - 8 - 4 - read-write - - - LOCK_REG0 - Lock PRINCE region0 settings - 18 - 2 - read-write - - - UNLOCK - Region is not locked - 0 - - - LOCK - Region is locked - 0x1 - - - VALUE_2 - Region is locked - 0x2 - - - VALUE_3 - Region is locked - 0x3 - - - - - LOCK_REG1 - Lock PRINCE region1 settings - 20 - 2 - read-write - - - UNLOCK - Region is not locked - 0 - - - LOCK - Region is locked - 0x1 - - - VALUE_2 - Region is locked - 0x2 - - - VALUE_3 - Region is locked - 0x3 - - - - - REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased together - 24 - 2 - read-write - - - DISABLE - Region is disabled - 0 - - - ENABLE - Region is enabled - 0x1 - - - VALUE_2 - Region is enabled - 0x2 - - - VALUE_3 - Region is enabled - 0x3 - - - - - REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased together - 26 - 2 - read-write - - - DISABLE - Region is disabled - 0 - - - ENABLE - Region is enabled - 0x1 - - - VALUE_2 - Region is enabled - 0x2 - - - VALUE_3 - Region is enabled - 0x3 - - - - - REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased together - 28 - 2 - read-write - - - DISABLE - Region is disabled - 0 - - - ENABLE - Region is enabled - 0x1 - - - VALUE_2 - Region is enabled - 0x2 - - - VALUE_3 - Region is enabled - 0x3 - - - - - - - PRINCE_SR_0 - Region 0, sub-region enable - 0x24 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_SR_1 - Region 1, sub-region enable - 0x28 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - PRINCE_SR_2 - Region 2, sub-region enable - 0x2C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - XTAL_32KHZ_CAPABANK_TRIM - Xtal 32kHz capabank triming. - 0x30 - 32 - read-write - 0 - 0xFFFFFFFF - - - TRIM_VALID - XTAL 32kHz capa bank trimmings - 0 - 1 - read-write - - - NOT_TRIM - Capa Bank trimmings not valid. Default trimmings value are used - 0 - - - VALID - Capa Bank trimmings valid - 0x1 - - - - - XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. - 1 - 10 - read-write - - - PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. - 11 - 10 - read-write - - - PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. - 21 - 10 - read-write - - - - - XTAL_16MHZ_CAPABANK_TRIM - Xtal 16MHz capabank triming. - 0x34 - 32 - read-write - 0 - 0xFFFFFFFF - - - TRIM_VALID - XTAL 16MHz capa bank trimmings - 0 - 1 - read-write - - - NOT_TRIM - Capa Bank trimmings not valid. Default trimmings value are used - 0 - - - VALID - Capa Bank trimmings valid - 0x1 - - - - - XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. - 1 - 10 - read-write - - - PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. - 11 - 10 - read-write - - - PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. - 21 - 10 - read-write - - - - - 8 - 0x4 - ROTKH[%s] - ROTKHindex for Root of Trust Keys Table hash[(((7 - index) * 32) + 31):((7 - index) * 32)] - 0x50 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - 56 - 0x4 - CUSTOMER_DEFINED[%s] - Customer Defined (Programable through ROM API) - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - 8 - 0x4 - SHA256_DIGEST[%s] - SHA256_DIGESTindex for DIGEST[((index * 32) + 31):(index * 32)] - 0x1E0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - no description available - 0 - 32 - read-write - - - - - - - FLASH_KEY_STORE - FLASH_KEY_STORE - FLASH_KEY_STORE - 0x9E600 - - 0 - 0x600 - registers - - - - HEADER - Valid Key Sore Header : 0x95959595 - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - puf_discharge_time_in_ms - puf discharge time in ms. - 0x4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - 298 - 0x4 - ACTIVATION_CODE[%s] - . - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_HEADER0 - . - SBKEY_KEY_CODE - 0x4B0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE0 - . - SBKEY_KEY_CODE - 0x4B0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_HEADER1 - . - SBKEY_KEY_CODE - 0x4B4 - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - . - 0 - 2 - read-write - - - INDEX - . - 8 - 4 - read-write - - - SIZE - . - 24 - 6 - read-write - - - - - SBKEY_KEY_CODE1 - . - SBKEY_KEY_CODE - 0x4B4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY0 - . - SBKEY_KEY_CODE - 0x4B8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE2 - . - SBKEY_KEY_CODE - 0x4B8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY1 - . - SBKEY_KEY_CODE - 0x4BC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE3 - . - SBKEY_KEY_CODE - 0x4BC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY2 - . - SBKEY_KEY_CODE - 0x4C0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE4 - . - SBKEY_KEY_CODE - 0x4C0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY3 - . - SBKEY_KEY_CODE - 0x4C4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE5 - . - SBKEY_KEY_CODE - 0x4C4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY4 - . - SBKEY_KEY_CODE - 0x4C8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE6 - . - SBKEY_KEY_CODE - 0x4C8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY5 - . - SBKEY_KEY_CODE - 0x4CC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE7 - . - SBKEY_KEY_CODE - 0x4CC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY6 - . - SBKEY_KEY_CODE - 0x4D0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE8 - . - SBKEY_KEY_CODE - 0x4D0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY7 - . - SBKEY_KEY_CODE - 0x4D4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE9 - . - SBKEY_KEY_CODE - 0x4D4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY8 - . - SBKEY_KEY_CODE - 0x4D8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE10 - . - SBKEY_KEY_CODE - 0x4D8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY9 - . - SBKEY_KEY_CODE - 0x4DC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE11 - . - SBKEY_KEY_CODE - 0x4DC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY10 - . - SBKEY_KEY_CODE - 0x4E0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE12 - . - SBKEY_KEY_CODE - 0x4E0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_BODY11 - . - SBKEY_KEY_CODE - 0x4E4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - SBKEY_KEY_CODE13 - . - SBKEY_KEY_CODE - 0x4E4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_HEADER0 - . - USER_KEK_KEY_CODE - 0x4E8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE0 - . - USER_KEK_KEY_CODE - 0x4E8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_HEADER1 - . - USER_KEK_KEY_CODE - 0x4EC - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - . - 0 - 2 - read-write - - - INDEX - . - 8 - 4 - read-write - - - SIZE - . - 24 - 6 - read-write - - - - - USER_KEK_KEY_CODE1 - . - USER_KEK_KEY_CODE - 0x4EC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY0 - . - USER_KEK_KEY_CODE - 0x4F0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE2 - . - USER_KEK_KEY_CODE - 0x4F0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY1 - . - USER_KEK_KEY_CODE - 0x4F4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE3 - . - USER_KEK_KEY_CODE - 0x4F4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY2 - . - USER_KEK_KEY_CODE - 0x4F8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE4 - . - USER_KEK_KEY_CODE - 0x4F8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY3 - . - USER_KEK_KEY_CODE - 0x4FC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE5 - . - USER_KEK_KEY_CODE - 0x4FC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY4 - . - USER_KEK_KEY_CODE - 0x500 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE6 - . - USER_KEK_KEY_CODE - 0x500 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY5 - . - USER_KEK_KEY_CODE - 0x504 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE7 - . - USER_KEK_KEY_CODE - 0x504 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY6 - . - USER_KEK_KEY_CODE - 0x508 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE8 - . - USER_KEK_KEY_CODE - 0x508 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY7 - . - USER_KEK_KEY_CODE - 0x50C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE9 - . - USER_KEK_KEY_CODE - 0x50C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY8 - . - USER_KEK_KEY_CODE - 0x510 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE10 - . - USER_KEK_KEY_CODE - 0x510 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY9 - . - USER_KEK_KEY_CODE - 0x514 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE11 - . - USER_KEK_KEY_CODE - 0x514 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY10 - . - USER_KEK_KEY_CODE - 0x518 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE12 - . - USER_KEK_KEY_CODE - 0x518 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_BODY11 - . - USER_KEK_KEY_CODE - 0x51C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - USER_KEK_KEY_CODE13 - . - USER_KEK_KEY_CODE - 0x51C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_HEADER0 - . - UDS_KEY_CODE - 0x520 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE0 - . - UDS_KEY_CODE - 0x520 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_HEADER1 - . - UDS_KEY_CODE - 0x524 - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - . - 0 - 2 - read-write - - - INDEX - . - 8 - 4 - read-write - - - SIZE - . - 24 - 6 - read-write - - - - - UDS_KEY_CODE1 - . - UDS_KEY_CODE - 0x524 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY0 - . - UDS_KEY_CODE - 0x528 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE2 - . - UDS_KEY_CODE - 0x528 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY1 - . - UDS_KEY_CODE - 0x52C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE3 - . - UDS_KEY_CODE - 0x52C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY2 - . - UDS_KEY_CODE - 0x530 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE4 - . - UDS_KEY_CODE - 0x530 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY3 - . - UDS_KEY_CODE - 0x534 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE5 - . - UDS_KEY_CODE - 0x534 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY4 - . - UDS_KEY_CODE - 0x538 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE6 - . - UDS_KEY_CODE - 0x538 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY5 - . - UDS_KEY_CODE - 0x53C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE7 - . - UDS_KEY_CODE - 0x53C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY6 - . - UDS_KEY_CODE - 0x540 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE8 - . - UDS_KEY_CODE - 0x540 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY7 - . - UDS_KEY_CODE - 0x544 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE9 - . - UDS_KEY_CODE - 0x544 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY8 - . - UDS_KEY_CODE - 0x548 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE10 - . - UDS_KEY_CODE - 0x548 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY9 - . - UDS_KEY_CODE - 0x54C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE11 - . - UDS_KEY_CODE - 0x54C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY10 - . - UDS_KEY_CODE - 0x550 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE12 - . - UDS_KEY_CODE - 0x550 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_BODY11 - . - UDS_KEY_CODE - 0x554 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - UDS_KEY_CODE13 - . - UDS_KEY_CODE - 0x554 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_HEADER0 - . - PRINCE_REGION0_KEY_CODE - 0x558 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE0 - . - PRINCE_REGION0_KEY_CODE - 0x558 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_HEADER1 - . - PRINCE_REGION0_KEY_CODE - 0x55C - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - . - 0 - 2 - read-write - - - INDEX - . - 8 - 4 - read-write - - - SIZE - . - 24 - 6 - read-write - - - - - PRINCE_REGION0_KEY_CODE1 - . - PRINCE_REGION0_KEY_CODE - 0x55C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY0 - . - PRINCE_REGION0_KEY_CODE - 0x560 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE2 - . - PRINCE_REGION0_KEY_CODE - 0x560 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY1 - . - PRINCE_REGION0_KEY_CODE - 0x564 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE3 - . - PRINCE_REGION0_KEY_CODE - 0x564 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY2 - . - PRINCE_REGION0_KEY_CODE - 0x568 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE4 - . - PRINCE_REGION0_KEY_CODE - 0x568 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY3 - . - PRINCE_REGION0_KEY_CODE - 0x56C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE5 - . - PRINCE_REGION0_KEY_CODE - 0x56C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY4 - . - PRINCE_REGION0_KEY_CODE - 0x570 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE6 - . - PRINCE_REGION0_KEY_CODE - 0x570 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY5 - . - PRINCE_REGION0_KEY_CODE - 0x574 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE7 - . - PRINCE_REGION0_KEY_CODE - 0x574 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY6 - . - PRINCE_REGION0_KEY_CODE - 0x578 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE8 - . - PRINCE_REGION0_KEY_CODE - 0x578 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY7 - . - PRINCE_REGION0_KEY_CODE - 0x57C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE9 - . - PRINCE_REGION0_KEY_CODE - 0x57C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY8 - . - PRINCE_REGION0_KEY_CODE - 0x580 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE10 - . - PRINCE_REGION0_KEY_CODE - 0x580 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY9 - . - PRINCE_REGION0_KEY_CODE - 0x584 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE11 - . - PRINCE_REGION0_KEY_CODE - 0x584 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY10 - . - PRINCE_REGION0_KEY_CODE - 0x588 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE12 - . - PRINCE_REGION0_KEY_CODE - 0x588 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_BODY11 - . - PRINCE_REGION0_KEY_CODE - 0x58C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION0_KEY_CODE13 - . - PRINCE_REGION0_KEY_CODE - 0x58C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_HEADER0 - . - PRINCE_REGION1_KEY_CODE - 0x590 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE0 - . - PRINCE_REGION1_KEY_CODE - 0x590 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_HEADER1 - . - PRINCE_REGION1_KEY_CODE - 0x594 - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - . - 0 - 2 - read-write - - - INDEX - . - 8 - 4 - read-write - - - SIZE - . - 24 - 6 - read-write - - - - - PRINCE_REGION1_KEY_CODE1 - . - PRINCE_REGION1_KEY_CODE - 0x594 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY0 - . - PRINCE_REGION1_KEY_CODE - 0x598 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE2 - . - PRINCE_REGION1_KEY_CODE - 0x598 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY1 - . - PRINCE_REGION1_KEY_CODE - 0x59C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE3 - . - PRINCE_REGION1_KEY_CODE - 0x59C - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY2 - . - PRINCE_REGION1_KEY_CODE - 0x5A0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE4 - . - PRINCE_REGION1_KEY_CODE - 0x5A0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY3 - . - PRINCE_REGION1_KEY_CODE - 0x5A4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE5 - . - PRINCE_REGION1_KEY_CODE - 0x5A4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY4 - . - PRINCE_REGION1_KEY_CODE - 0x5A8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE6 - . - PRINCE_REGION1_KEY_CODE - 0x5A8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY5 - . - PRINCE_REGION1_KEY_CODE - 0x5AC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE7 - . - PRINCE_REGION1_KEY_CODE - 0x5AC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY6 - . - PRINCE_REGION1_KEY_CODE - 0x5B0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE8 - . - PRINCE_REGION1_KEY_CODE - 0x5B0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY7 - . - PRINCE_REGION1_KEY_CODE - 0x5B4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE9 - . - PRINCE_REGION1_KEY_CODE - 0x5B4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY8 - . - PRINCE_REGION1_KEY_CODE - 0x5B8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE10 - . - PRINCE_REGION1_KEY_CODE - 0x5B8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY9 - . - PRINCE_REGION1_KEY_CODE - 0x5BC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE11 - . - PRINCE_REGION1_KEY_CODE - 0x5BC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY10 - . - PRINCE_REGION1_KEY_CODE - 0x5C0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE12 - . - PRINCE_REGION1_KEY_CODE - 0x5C0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_BODY11 - . - PRINCE_REGION1_KEY_CODE - 0x5C4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION1_KEY_CODE13 - . - PRINCE_REGION1_KEY_CODE - 0x5C4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_HEADER0 - . - PRINCE_REGION2_KEY_CODE - 0x5C8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE0 - . - PRINCE_REGION2_KEY_CODE - 0x5C8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_HEADER1 - . - PRINCE_REGION2_KEY_CODE - 0x5CC - 32 - read-write - 0 - 0xFFFFFFFF - - - TYPE - . - 0 - 2 - read-write - - - INDEX - . - 8 - 4 - read-write - - - SIZE - . - 24 - 6 - read-write - - - - - PRINCE_REGION2_KEY_CODE1 - . - PRINCE_REGION2_KEY_CODE - 0x5CC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY0 - . - PRINCE_REGION2_KEY_CODE - 0x5D0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE2 - . - PRINCE_REGION2_KEY_CODE - 0x5D0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY1 - . - PRINCE_REGION2_KEY_CODE - 0x5D4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE3 - . - PRINCE_REGION2_KEY_CODE - 0x5D4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY2 - . - PRINCE_REGION2_KEY_CODE - 0x5D8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE4 - . - PRINCE_REGION2_KEY_CODE - 0x5D8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY3 - . - PRINCE_REGION2_KEY_CODE - 0x5DC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE5 - . - PRINCE_REGION2_KEY_CODE - 0x5DC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY4 - . - PRINCE_REGION2_KEY_CODE - 0x5E0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE6 - . - PRINCE_REGION2_KEY_CODE - 0x5E0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY5 - . - PRINCE_REGION2_KEY_CODE - 0x5E4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE7 - . - PRINCE_REGION2_KEY_CODE - 0x5E4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY6 - . - PRINCE_REGION2_KEY_CODE - 0x5E8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE8 - . - PRINCE_REGION2_KEY_CODE - 0x5E8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY7 - . - PRINCE_REGION2_KEY_CODE - 0x5EC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE9 - . - PRINCE_REGION2_KEY_CODE - 0x5EC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY8 - . - PRINCE_REGION2_KEY_CODE - 0x5F0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE10 - . - PRINCE_REGION2_KEY_CODE - 0x5F0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY9 - . - PRINCE_REGION2_KEY_CODE - 0x5F4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE11 - . - PRINCE_REGION2_KEY_CODE - 0x5F4 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY10 - . - PRINCE_REGION2_KEY_CODE - 0x5F8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE12 - . - PRINCE_REGION2_KEY_CODE - 0x5F8 - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_BODY11 - . - PRINCE_REGION2_KEY_CODE - 0x5FC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - PRINCE_REGION2_KEY_CODE13 - . - PRINCE_REGION2_KEY_CODE - 0x5FC - 32 - read-write - 0 - 0xFFFFFFFF - - - FIELD - . - 0 - 32 - read-write - - - - - - - SYSCON - SYSCON - SYSCON - 0x40000000 - - 0 - 0x1000 - registers - - - - MEMORYREMAP - Memory Remap control register - 0 - 32 - read-write - 0 - 0x3 - - - MAP - Select the location of the vector table :. - 0 - 2 - read-write - - - ROM0 - Vector Table in ROM. - 0 - - - RAM1 - Vector Table in RAM. - 0x1 - - - FLASH0 - Vector Table in Flash. - 0x2 - - - FLASH1 - Vector Table in Flash. - 0x3 - - - - - - - AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest - 0x10 - 32 - read-write - 0 - 0x3FFFFFF - - - PRI_CPU0_CBUS - CPU0 C-AHB bus. - 0 - 2 - read-write - - - PRI_CPU0_SBUS - CPU0 S-AHB bus. - 2 - 2 - read-write - - - PRI_CPU1_CBUS - CPU1 C-AHB bus. - 4 - 2 - read-write - - - PRI_CPU1_SBUS - CPU1 S-AHB bus. - 6 - 2 - read-write - - - PRI_USB_FS - USB-FS.(USB0) - 8 - 2 - read-write - - - PRI_SDMA0 - DMA0 controller priority. - 10 - 2 - read-write - - - PRI_SDIO - SDIO. - 16 - 2 - read-write - - - PRI_PQ - PQ (HW Accelerator). - 18 - 2 - read-write - - - PRI_HASH_AES - HASH_AES. - 20 - 2 - read-write - - - PRI_USB_HS - USB-HS.(USB1) - 22 - 2 - read-write - - - PRI_SDMA1 - DMA1 controller priority. - 24 - 2 - read-write - - - - - CPU0STCKCAL - System tick calibration for secure part of CPU0 - 0x38 - 32 - read-write - 0 - 0x3FFFFFF - - - TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. - 0 - 24 - read-write - - - SKEW - Initial value for the Systick timer. - 24 - 1 - read-write - - - NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference clock provided; 1 = no reference clock provided. - 25 - 1 - read-write - - - - - CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 - 0x3C - 32 - read-write - 0 - 0x3FFFFFF - - - TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. - 0 - 24 - read-write - - - SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. - 24 - 1 - read-write - - - NOREF - Initial value for the Systick timer. - 25 - 1 - read-write - - - - - CPU1STCKCAL - System tick calibration for CPU1 - 0x40 - 32 - read-write - 0 - 0x3FFFFFF - - - TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. - 0 - 24 - read-write - - - SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. - 24 - 1 - read-write - - - NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference clock provided; 1 = no reference clock provided. - 25 - 1 - read-write - - - - - NMISRC - NMI Source Select - 0x48 - 32 - read-write - 0 - 0xC0003F3F - - - IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0. - 0 - 6 - read-write - - - IRQCPU1 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1, if enabled by NMIENCPU1. - 8 - 6 - read-write - - - NMIENCPU1 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU1. - 30 - 1 - read-write - - - NMIENCPU0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. - 31 - 1 - read-write - - - - - PRESETCTRL0 - Peripheral reset control 0 - PRESETCTRL - 0x100 - 32 - read-write - 0 - 0xCFFE9FA - - - ROM_RST - ROM reset control. - 1 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SRAM_CTRL1_RST - SRAM Controller 1 reset control. - 3 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SRAM_CTRL2_RST - SRAM Controller 2 reset control. - 4 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SRAM_CTRL3_RST - SRAM Controller 3 reset control. - 5 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SRAM_CTRL4_RST - SRAM Controller 4 reset control. - 6 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FLASH_RST - Flash controller reset control. - 7 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FMC_RST - FMC controller reset control. - 8 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - MUX_RST - Input Mux reset control. - 11 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - IOCON_RST - I/O controller reset control. - 13 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GPIO0_RST - GPIO0 reset control. - 14 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GPIO1_RST - GPIO1 reset control. - 15 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GPIO2_RST - GPIO2 reset control. - 16 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GPIO3_RST - GPIO3 reset control. - 17 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - PINT_RST - Pin interrupt (PINT) reset control. - 18 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GINT_RST - Group interrupt (GINT) reset control. - 19 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - DMA0_RST - DMA0 reset control. - 20 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - CRCGEN_RST - CRCGEN reset control. - 21 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - WWDT_RST - Watchdog Timer reset control. - 22 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - RTC_RST - Real Time Clock (RTC) reset control. - 23 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - MAILBOX_RST - Inter CPU communication Mailbox reset control. - 26 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - ADC_RST - ADC reset control. - 27 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - - - PRESETCTRLX0 - Peripheral reset control register - PRESETCTRL - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - PRESETCTRL1 - Peripheral reset control 1 - PRESETCTRL - 0x104 - 32 - read-write - 0 - 0xDE57FC47 - - - MRT_RST - MRT reset control. - 0 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - OSTIMER_RST - OS Event Timer reset control. - 1 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SCT_RST - SCT reset control. - 2 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SCTIPU_RST - SCTIPU reset control. - 6 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - UTICK_RST - UTICK reset control. - 10 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC0_RST - FC0 reset control. - 11 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC1_RST - FC1 reset control. - 12 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC2_RST - FC2 reset control. - 13 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC3_RST - FC3 reset control. - 14 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC4_RST - FC4 reset control. - 15 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC5_RST - FC5 reset control. - 16 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC6_RST - FC6 reset control. - 17 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FC7_RST - FC7 reset control. - 18 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - TIMER2_RST - Timer 2 reset control. - 22 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - USB0_DEV_RST - USB0 DEV reset control. - 25 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - TIMER0_RST - Timer 0 reset control. - 26 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - TIMER1_RST - Timer 1 reset control. - 27 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - - - PRESETCTRLX1 - Peripheral reset control register - PRESETCTRL - 0x104 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - PRESETCTRL2 - Peripheral reset control 2 - PRESETCTRL - 0x108 - 32 - read-write - 0 - 0x7FFF77FE - - - DMA1_RST - DMA1 reset control. - 1 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - COMP_RST - Comparator reset control. - 2 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SDIO_RST - SDIO reset control. - 3 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - USB1_HOST_RST - USB1 Host reset control. - 4 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - USB1_DEV_RST - USB1 dev reset control. - 5 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - USB1_RAM_RST - USB1 RAM reset control. - 6 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - USB1_PHY_RST - USB1 PHY reset control. - 7 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - FREQME_RST - Frequency meter reset control. - 8 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - RNG_RST - RNG reset control. - 13 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - SYSCTL_RST - SYSCTL Block reset. - 15 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - USB0_HOSTM_RST - USB0 Host Master reset control. - 16 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - USB0_HOSTS_RST - USB0 Host Slave reset control. - 17 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - HASH_AES_RST - HASH_AES reset control. - 18 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - PQ_RST - Power Quad reset control. - 19 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - PLULUT_RST - PLU LUT reset control. - 20 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - TIMER3_RST - Timer 3 reset control. - 21 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - TIMER4_RST - Timer 4 reset control. - 22 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - PUF_RST - PUF reset control reset control. - 23 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - CASPER_RST - Casper reset control. - 24 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - ANALOG_CTRL_RST - analog control reset control. - 27 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - HS_LSPI_RST - HS LSPI reset control. - 28 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GPIO_SEC_RST - GPIO secure reset control. - 29 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GPIO_SEC_INT_RST - GPIO secure int reset control. - 30 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - - - PRESETCTRLX2 - Peripheral reset control register - PRESETCTRL - 0x108 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - 3 - 0x4 - PRESETCTRLSET[%s] - Peripheral reset control set register - 0x120 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - 3 - 0x4 - PRESETCTRLCLR[%s] - Peripheral reset control clear register - 0x140 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - SWR_RESET - generate a software_reset - 0x160 - 32 - write-only - 0 - 0xFFFFFFFF - - - SWR_RESET - Write 0x5A00_0001 to generate a software_reset. - 0 - 32 - write-only - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Generate a software reset. - 0x5A000001 - - - - - - - AHBCLKCTRL0 - AHB Clock control 0 - AHBCLKCTRL - 0x200 - 32 - read-write - 0x180 - 0xCFFE9FA - - - ROM - Enables the clock for the ROM. - 1 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. - 3 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. - 4 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - SRAM_CTRL3 - Enables the clock for the SRAM Controller 3. - 5 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - SRAM_CTRL4 - Enables the clock for the SRAM Controller 4. - 6 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FLASH - Enables the clock for the Flash controller. - 7 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FMC - Enables the clock for the FMC controller. - 8 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - MUX - Enables the clock for the Input Mux. - 11 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - IOCON - Enables the clock for the I/O controller. - 13 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GPIO0 - Enables the clock for the GPIO0. - 14 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GPIO1 - Enables the clock for the GPIO1. - 15 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GPIO2 - Enables the clock for the GPIO2. - 16 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GPIO3 - Enables the clock for the GPIO3. - 17 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - PINT - Enables the clock for the Pin interrupt (PINT). - 18 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GINT - Enables the clock for the Group interrupt (GINT). - 19 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - DMA0 - Enables the clock for the DMA0. - 20 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - CRCGEN - Enables the clock for the CRCGEN. - 21 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - WWDT - Enables the clock for the Watchdog Timer. - 22 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - RTC - Enables the clock for the Real Time Clock (RTC). - 23 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - MAILBOX - Enables the clock for the Inter CPU communication Mailbox. - 26 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - ADC - Enables the clock for the ADC. - 27 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - - - AHBCLKCTRLX0 - Peripheral reset control register - AHBCLKCTRL - 0x200 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - AHBCLKCTRL1 - AHB Clock control 1 - AHBCLKCTRL - 0x204 - 32 - read-write - 0 - 0xDE57FC47 - - - MRT - Enables the clock for the MRT. - 0 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - OSTIMER - Enables the clock for the OS Event Timer. - 1 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - SCT - Enables the clock for the SCT. - 2 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - UTICK - Enables the clock for the UTICK. - 10 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC0 - Enables the clock for the FC0. - 11 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC1 - Enables the clock for the FC1. - 12 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC2 - Enables the clock for the FC2. - 13 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC3 - Enables the clock for the FC3. - 14 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC4 - Enables the clock for the FC4. - 15 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC5 - Enables the clock for the FC5. - 16 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC6 - Enables the clock for the FC6. - 17 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FC7 - Enables the clock for the FC7. - 18 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - TIMER2 - Enables the clock for the Timer 2. - 22 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - USB0_DEV - Enables the clock for the USB0 DEV. - 25 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - TIMER0 - Enables the clock for the Timer 0. - 26 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - TIMER1 - Enables the clock for the Timer 1. - 27 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - - - AHBCLKCTRLX1 - Peripheral reset control register - AHBCLKCTRL - 0x204 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - AHBCLKCTRL2 - AHB Clock control 2 - AHBCLKCTRL - 0x208 - 32 - read-write - 0 - 0x7FFF77FE - - - DMA1 - Enables the clock for the DMA1. - 1 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - COMP - Enables the clock for the Comparator. - 2 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - SDIO - Enables the clock for the SDIO. - 3 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - USB1_HOST - Enables the clock for the USB1 Host. - 4 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - USB1_DEV - Enables the clock for the USB1 dev. - 5 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - USB1_RAM - Enables the clock for the USB1 RAM. - 6 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - USB1_PHY - Enables the clock for the USB1 PHY. - 7 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - FREQME - Enables the clock for the Frequency meter. - 8 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - RNG - Enables the clock for the RNG. - 13 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - SYSCTL - SYSCTL block clock. - 15 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - USB0_HOSTM - Enables the clock for the USB0 Host Master. - 16 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - USB0_HOSTS - Enables the clock for the USB0 Host Slave. - 17 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - HASH_AES - Enables the clock for the HASH_AES. - 18 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - PQ - Enables the clock for the Power Quad. - 19 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - PLULUT - Enables the clock for the PLU LUT. - 20 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - TIMER3 - Enables the clock for the Timer 3. - 21 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - TIMER4 - Enables the clock for the Timer 4. - 22 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - PUF - Enables the clock for the PUF reset control. - 23 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - CASPER - Enables the clock for the Casper. - 24 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - ANALOG_CTRL - Enables the clock for the analog control. - 27 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - HS_LSPI - Enables the clock for the HS LSPI. - 28 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GPIO_SEC - Enables the clock for the GPIO secure. - 29 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GPIO_SEC_INT - Enables the clock for the GPIO secure int. - 30 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - - - AHBCLKCTRLX2 - Peripheral reset control register - AHBCLKCTRL - 0x208 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - 3 - 0x4 - AHBCLKCTRLSET[%s] - Peripheral reset control register - 0x220 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - 3 - 0x4 - AHBCLKCTRLCLR[%s] - Peripheral reset control register - 0x240 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select - SYSTICKCLKSEL - 0x260 - 32 - read-write - 0x7 - 0x7 - - - SEL - System Tick Timer for CPU0 source select. - 0 - 3 - read-write - - - ENUM_0x0 - System Tick 0 divided clock. - 0 - - - ENUM_0x1 - FRO 1MHz clock. - 0x1 - - - ENUM_0x2 - Oscillator 32 kHz clock. - 0x2 - - - ENUM_0x3 - No clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - SYSTICKCLKSELX0 - Peripheral reset control register - SYSTICKCLKSEL - 0x260 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - SYSTICKCLKSEL1 - System Tick Timer for CPU1 source select - SYSTICKCLKSEL - 0x264 - 32 - read-write - 0x7 - 0x7 - - - SEL - System Tick Timer for CPU1 source select. - 0 - 3 - read-write - - - ENUM_0x0 - System Tick 1 divided clock. - 0 - - - ENUM_0x1 - FRO 1MHz clock. - 0x1 - - - ENUM_0x2 - Oscillator 32 kHz clock. - 0x2 - - - ENUM_0x3 - No clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - SYSTICKCLKSELX1 - Peripheral reset control register - SYSTICKCLKSEL - 0x264 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - TRACECLKSEL - Trace clock source select - 0x268 - 32 - read-write - 0x7 - 0x7 - - - SEL - Trace clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Trace divided clock. - 0 - - - ENUM_0x1 - FRO 1MHz clock. - 0x1 - - - ENUM_0x2 - Oscillator 32 kHz clock. - 0x2 - - - ENUM_0x3 - No clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - CTIMERCLKSEL0 - CTimer 0 clock source select - CTIMERCLKSEL - 0x26C - 32 - read-write - 0x7 - 0x7 - - - SEL - CTimer 0 clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - CTIMERCLKSELX0 - Peripheral reset control register - CTIMERCLKSEL - 0x26C - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - CTIMERCLKSEL1 - CTimer 1 clock source select - CTIMERCLKSEL - 0x270 - 32 - read-write - 0x7 - 0x7 - - - SEL - CTimer 1 clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - CTIMERCLKSELX1 - Peripheral reset control register - CTIMERCLKSEL - 0x270 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - CTIMERCLKSEL2 - CTimer 2 clock source select - CTIMERCLKSEL - 0x274 - 32 - read-write - 0x7 - 0x7 - - - SEL - CTimer 2 clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - CTIMERCLKSELX2 - Peripheral reset control register - CTIMERCLKSEL - 0x274 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - CTIMERCLKSEL3 - CTimer 3 clock source select - CTIMERCLKSEL - 0x278 - 32 - read-write - 0x7 - 0x7 - - - SEL - CTimer 3 clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - CTIMERCLKSELX3 - Peripheral reset control register - CTIMERCLKSEL - 0x278 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - CTIMERCLKSEL4 - CTimer 4 clock source select - CTIMERCLKSEL - 0x27C - 32 - read-write - 0x7 - 0x7 - - - SEL - CTimer 4 clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - CTIMERCLKSELX4 - Peripheral reset control register - CTIMERCLKSEL - 0x27C - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - MAINCLKSELA - Main clock A source select - 0x280 - 32 - read-write - 0 - 0x7 - - - SEL - Main clock A source select. - 0 - 3 - read-write - - - ENUM_0x0 - FRO 12 MHz clock. - 0 - - - ENUM_0x1 - CLKIN clock. - 0x1 - - - ENUM_0x2 - FRO 1MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - - - - - MAINCLKSELB - Main clock source select - 0x284 - 32 - read-write - 0 - 0x7 - - - SEL - Main clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main Clock A. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - PLL1 clock. - 0x2 - - - ENUM_0x3 - Oscillator 32 kHz clock. - 0x3 - - - - - - - CLKOUTSEL - CLKOUT clock source select - 0x288 - 32 - read-write - 0x7 - 0x7 - - - SEL - CLKOUT clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - CLKIN clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - PLL1 clock. - 0x5 - - - ENUM_0x6 - Oscillator 32kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - PLL0CLKSEL - PLL0 clock source select - 0x290 - 32 - read-write - 0x7 - 0x7 - - - SEL - PLL0 clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - FRO 12 MHz clock. - 0 - - - ENUM_0x1 - CLKIN clock. - 0x1 - - - ENUM_0x2 - FRO 1MHz clock. - 0x2 - - - ENUM_0x3 - Oscillator 32kHz clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - PLL1CLKSEL - PLL1 clock source select - 0x294 - 32 - read-write - 0x7 - 0x7 - - - SEL - PLL1 clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - FRO 12 MHz clock. - 0 - - - ENUM_0x1 - CLKIN clock. - 0x1 - - - ENUM_0x2 - FRO 1MHz clock. - 0x2 - - - ENUM_0x3 - Oscillator 32kHz clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - ADCCLKSEL - ADC clock source select - 0x2A4 - 32 - read-write - 0x7 - 0x7 - - - SEL - ADC clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - FRO 96 MHz clock. - 0x2 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - USB0CLKSEL - FS USB clock source select - 0x2A8 - 32 - read-write - 0x7 - 0x7 - - - SEL - FS USB clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - PLL1 clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2B0 - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX0 - Peripheral reset control register - FCCLKSEL - 0x2B0 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2B4 - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX1 - Peripheral reset control register - FCCLKSEL - 0x2B4 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2B8 - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX2 - Peripheral reset control register - FCCLKSEL - 0x2B8 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2BC - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX3 - Peripheral reset control register - FCCLKSEL - 0x2BC - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2C0 - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX4 - Peripheral reset control register - FCCLKSEL - 0x2C0 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2C4 - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX5 - Peripheral reset control register - FCCLKSEL - 0x2C4 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2C8 - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX6 - Peripheral reset control register - FCCLKSEL - 0x2C8 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider - FCCLKSEL - 0x2CC - 32 - read-write - 0x7 - 0x7 - - - SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - FCCLKSELX7 - Peripheral reset control register - FCCLKSEL - 0x2CC - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - HSLSPICLKSEL - HS LSPI clock source select - 0x2D0 - 32 - read-write - 0x7 - 0x7 - - - SEL - HS LSPI clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - system PLL divided clock. - 0x1 - - - ENUM_0x2 - FRO 12 MHz clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - FRO 1MHz clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - Oscillator 32 kHz clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - MCLKCLKSEL - MCLK clock source select - 0x2E0 - 32 - read-write - 0x7 - 0x7 - - - SEL - MCLK clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - FRO 96 MHz clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - SCTCLKSEL - SCTimer/PWM clock source select - 0x2F0 - 32 - read-write - 0x7 - 0x7 - - - SEL - SCTimer/PWM clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - CLKIN clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - MCLK clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - SDIOCLKSEL - SDIO clock source select - 0x2F8 - 32 - read-write - 0x7 - 0x7 - - - SEL - SDIO clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - FRO 96 MHz clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - PLL1 clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - - - SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 - 0x300 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - SYSTICKCLKDIV1 - System Tick Timer divider for CPU1 - 0x304 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - TRACECLKDIV - TRACE clock divider - 0x308 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 - FLEXFRGCTRL - 0x320 - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL0 - Peripheral reset control register - FLEXFRGCTRL - 0x320 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 - FLEXFRGCTRL - 0x324 - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL1 - Peripheral reset control register - FLEXFRGCTRL - 0x324 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 - FLEXFRGCTRL - 0x328 - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL2 - Peripheral reset control register - FLEXFRGCTRL - 0x328 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 - FLEXFRGCTRL - 0x32C - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL3 - Peripheral reset control register - FLEXFRGCTRL - 0x32C - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 - FLEXFRGCTRL - 0x330 - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL4 - Peripheral reset control register - FLEXFRGCTRL - 0x330 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 - FLEXFRGCTRL - 0x334 - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL5 - Peripheral reset control register - FLEXFRGCTRL - 0x334 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 - FLEXFRGCTRL - 0x338 - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL6 - Peripheral reset control register - FLEXFRGCTRL - 0x338 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 - FLEXFRGCTRL - 0x33C - 32 - read-write - 0xFF - 0xFFFF - - - DIV - Denominator of the fractional rate divider. - 0 - 8 - read-write - - - MULT - Numerator of the fractional rate divider. - 8 - 8 - read-write - - - - - FLEXFRGXCTRL7 - Peripheral reset control register - FLEXFRGCTRL - 0x33C - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - Data array value - 0 - 32 - read-write - - - - - AHBCLKDIV - System clock divider - 0x380 - 32 - read-write - 0 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - CLKOUTDIV - CLKOUT clock divider - 0x384 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - FROHFDIV - FRO_HF (96MHz) clock divider - 0x388 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - WDTCLKDIV - WDT clock divider - 0x38C - 32 - read-write - 0x40000000 - 0xE000003F - - - DIV - Clock divider value. - 0 - 6 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - ADCCLKDIV - ADC clock divider - 0x394 - 32 - read-write - 0x40000000 - 0xE0000007 - - - DIV - Clock divider value. - 0 - 3 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - USB0CLKDIV - USB0 Clock divider - 0x398 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - MCLKDIV - I2S MCLK clock divider - 0x3AC - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - SCTCLKDIV - SCT/PWM clock divider - 0x3B4 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - SDIOCLKDIV - SDIO clock divider - 0x3BC - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - PLL0CLKDIV - PLL0 clock divider - 0x3C4 - 32 - read-write - 0x40000000 - 0xE00000FF - - - DIV - Clock divider value. - 0 - 8 - read-write - - - RESET - Resets the divider counter. - 29 - 1 - write-only - - - RELEASED - Divider is not reset. - 0 - - - ASSERTED - Divider is reset. - 0x1 - - - - - HALT - Halts the divider counter. - 30 - 1 - read-write - - - RUN - Divider clock is running. - 0 - - - HALT - Divider clock is stoped. - 0x1 - - - - - REQFLAG - Divider status flag. - 31 - 1 - read-only - - - STABLE - Divider clock is stable. - 0 - - - ONGOING - Clock frequency is not stable. - 0x1 - - - - - - - CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) - 0x3FC - 32 - read-write - 0 - 0xFFFFFFFF - - - CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL). - 0 - 32 - read-write - - - FREEZE - all hardware clock configruration are freeze. - 0 - - - ENABLE - update all clock configuration. - 0x1 - - - - - - - FMCCR - FMC configuration register - 0x400 - 32 - read-write - 0x2000 - 0xFFFFFFFF - - - FETCHCFG - Instruction fetch configuration. - 0 - 2 - read-write - - - NOBUF - Instruction fetches from flash are not buffered. - 0 - - - ONEBUF - One buffer is used for all instruction fetches. - 0x1 - - - ALLBUF - All buffers may be used for instruction fetches. - 0x2 - - - - - DATACFG - Data read configuration. - 2 - 2 - read-write - - - NOBUF - Data accesses from flash are not buffered. - 0 - - - ONEBUF - One buffer is used for all data accesses. - 0x1 - - - ALLBUF - All buffers can be used for data accesses. - 0x2 - - - - - ACCEL - Acceleration enable. - 4 - 1 - read-write - - - DISABLE - Flash acceleration is disabled. - 0 - - - ENABLE - Flash acceleration is enabled. - 0x1 - - - - - PREFEN - Prefetch enable. - 5 - 1 - read-write - - - DISABLE - No instruction prefetch is performed. - 0 - - - ENABLE - Instruction prefetch is enabled. - 0x1 - - - - - PREFOVR - Prefetch override. - 6 - 1 - read-write - - - NORMAL - Any previously initiated prefetch will be completed. - 0 - - - OVERRIDE - Any previously initiated prefetch will be aborted, and the next flash line following the current execution address will be prefetched if not already buffered. - 0x1 - - - - - FLASHTIM - Flash memory access time. - 12 - 4 - read-write - - - FLASHTIM0 - 1 system clock flash access time (for system clock rates up to 11 MHz). - 0 - - - FLASHTIM1 - 2 system clocks flash access time (for system clock rates up to 22 MHz). - 0x1 - - - FLASHTIM2 - 3 system clocks flash access time (for system clock rates up to 33 MHz). - 0x2 - - - FLASHTIM3 - 4 system clocks flash access time (for system clock rates up to 44 MHz). - 0x3 - - - FLASHTIM4 - 5 system clocks flash access time (for system clock rates up to 55 MHz). - 0x4 - - - FLASHTIM5 - 6 system clocks flash access time (for system clock rates up to 66 MHz). - 0x5 - - - FLASHTIM6 - 7 system clocks flash access time (for system clock rates up to 77 MHz). - 0x6 - - - FLASHTIM7 - 8 system clocks flash access time (for system clock rates up to 88 MHz). - 0x7 - - - FLASHTIM8 - 9 system clocks flash access time (for system clock rates up to 100 MHz). - 0x8 - - - FLASHTIM9 - 10 system clocks flash access time (for system clock rates up to 115 MHz). - 0x9 - - - FLASHTIM10 - 11 system clocks flash access time (for system clock rates up to 130 MHz). - 0xA - - - FLASHTIM11 - 12 system clocks flash access time (for system clock rates up to 150 MHz). - 0xB - - - - - - - USB0NEEDCLKCTRL - USB0 need clock control - 0x40C - 32 - read-write - 0 - 0x1F - - - AP_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal control:. - 0 - 1 - read-write - - - HW_CTRL - Under hardware control. - 0 - - - FORCED - Forced high. - 0x1 - - - - - POL_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. - 1 - 1 - read-write - - - FALLING - Falling edge of device USB0_NEEDCLK triggers wake-up. - 0 - - - RISING - Rising edge of device USB0_NEEDCLK triggers wake-up. - 0x1 - - - - - AP_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal control:. - 2 - 1 - read-write - - - HW_CTRL - Under hardware control. - 0 - - - FORCED - Forced high. - 0x1 - - - - - POL_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. - 3 - 1 - read-write - - - FALLING - Falling edge of device USB0_NEEDCLK triggers wake-up. - 0 - - - RISING - Rising edge of device USB0_NEEDCLK triggers wake-up. - 0x1 - - - - - - - USB0NEEDCLKSTAT - USB0 need clock status - 0x410 - 32 - read-write - 0 - 0x3 - - - DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal status:. - 0 - 1 - read-only - - - LOW - USB0 Device clock is low. - 0 - - - HIGH - USB0 Device clock is high. - 0x1 - - - - - HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal status:. - 1 - 1 - read-only - - - LOW - USB0 Host clock is low. - 0 - - - HIGH - USB0 Host clock is high. - 0x1 - - - - - - - FMCFLUSH - FMCflush control - 0x41C - 32 - write-only - 0 - 0xFFFFFFFF - - - FLUSH - Flush control - 0 - 1 - write-only - - - NO_FLUSH - No action is performed. - 0 - - - FLUSH - Flush the FMC buffer contents. - 0x1 - - - - - - - MCLKIO - MCLK control - 0x420 - 32 - read-write - 0 - 0xFFFFFFFF - - - MCLKIO - MCLK control. - 0 - 1 - read-write - - - INPUT - input mode. - 0 - - - OUTPUT - output mode. - 0x1 - - - - - - - USB1NEEDCLKCTRL - USB1 need clock control - 0x424 - 32 - read-write - 0x10 - 0x1F - - - AP_HS_DEV_NEEDCLK - USB1 Device need_clock signal control: - 0 - 1 - read-write - - - HW_CTRL - HOST_NEEDCLK is under hardware control. - 0 - - - FORCED - HOST_NEEDCLK is forced high. - 0x1 - - - - - POL_HS_DEV_NEEDCLK - USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt: - 1 - 1 - read-write - - - FALLING - Falling edge of DEV_NEEDCLK triggers wake-up. - 0 - - - RISING - Rising edge of DEV_NEEDCLK triggers wake-up. - 0x1 - - - - - AP_HS_HOST_NEEDCLK - USB1 Host need clock signal control: - 2 - 1 - read-write - - - HW_CTRL - HOST_NEEDCLK is under hardware control. - 0 - - - FORCED - HOST_NEEDCLK is forced high. - 0x1 - - - - - POL_HS_HOST_NEEDCLK - USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. - 3 - 1 - read-write - - - FALLING - Falling edge of HOST_NEEDCLK triggers wake-up. - 0 - - - RISING - Rising edge of HOST_NEEDCLK triggers wake-up. - 0x1 - - - - - HS_DEV_WAKEUP_N - Software override of device controller PHY wake up logic. - 4 - 1 - read-write - - - FORCE_WUP - Forces USB1_PHY to wake-up. - 0 - - - NORMAL_WUP - Normal USB1_PHY behavior. - 0x1 - - - - - - - USB1NEEDCLKSTAT - USB1 need clock status - 0x428 - 32 - read-write - 0 - 0x3 - - - DEV_NEEDCLK - USB1 Device need_clock signal status:. - 0 - 1 - read-only - - - LOW - DEV_NEEDCLK is low. - 0 - - - HIGH - DEV_NEEDCLK is high. - 0x1 - - - - - HOST_NEEDCLK - USB1 Host need_clock signal status:. - 1 - 1 - read-only - - - LOW - HOST_NEEDCLK is low. - 0 - - - HIGH - HOST_NEEDCLK is high. - 0x1 - - - - - - - SDIOCLKCTRL - SDIO CCLKIN phase and delay control - 0x460 - 32 - read-write - 0 - 0x9F9F008F - - - CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in. - 0 - 2 - read-write - - - ENUM_0_DEG - 0 degree shift. - 0 - - - ENUM_90_DEG - 90 degree shift. - 0x1 - - - ENUM_180_DEG - 180 degree shift. - 0x2 - - - ENUM_270_DEG - 270 degree shift. - 0x3 - - - - - CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. - 2 - 2 - read-write - - - ENUM_0_DEG - 0 degree shift. - 0 - - - ENUM_90_DEG - 90 degree shift. - 0x1 - - - ENUM_180_DEG - 180 degree shift. - 0x2 - - - ENUM_270_DEG - 270 degree shift. - 0x3 - - - - - PHASE_ACTIVE - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE. - 7 - 1 - read-write - - - BYPASSED - Bypassed. - 0 - - - PH_SHIFT - Activates phase shift logic. When active, the clock divider is active and phase delays are enabled. - 0x1 - - - - - CCLK_DRV_DELAY - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in. - 16 - 5 - read-write - - - CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field. - 23 - 1 - read-write - - - DISABLE - Disable drive delay. - 0 - - - ENABLE - Enable drive delay. - 0x1 - - - - - CCLK_SAMPLE_DELAY - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. - 24 - 5 - read-write - - - CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. - 31 - 1 - read-write - - - DISABLE - Disables sample delay. - 0 - - - ENABLE - Enables sample delay. - 0x1 - - - - - - - PLL1CTRL - PLL1 550m control - 0x560 - 32 - read-write - 0 - 0x1FFFFFF - - - SELR - Bandwidth select R value. - 0 - 4 - read-write - - - SELI - Bandwidth select I value. - 4 - 6 - read-write - - - SELP - Bandwidth select P value. - 10 - 5 - read-write - - - BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - 15 - 1 - read-write - - - USED - use PLL. - 0 - - - BYPASSED - PLL input clock is sent directly to the PLL output. - 0x1 - - - - - BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - 16 - 1 - read-write - - - USED - use the divide-by-2 divider in the post-divider. - 0 - - - BYPASSED - bypass of the divide-by-2 divider in the post-divider. - 0x1 - - - - - LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. - 17 - 1 - read-write - - - BWDIRECT - control of the bandwidth of the PLL. - 18 - 1 - read-write - - - SYNC - the bandwidth is changed synchronously with the feedback-divider. - 0 - - - DIRECT - modify the bandwidth of the PLL directly. - 0x1 - - - - - BYPASSPREDIV - bypass of the pre-divider. - 19 - 1 - read-write - - - USED - use the pre-divider. - 0 - - - BYPASSED - bypass of the pre-divider. - 0x1 - - - - - BYPASSPOSTDIV - bypass of the post-divider. - 20 - 1 - read-write - - - USED - use the post-divider. - 0 - - - BYPASSED - bypass of the post-divider. - 0x1 - - - - - CLKEN - enable the output clock. - 21 - 1 - read-write - - - DISABLE - Disable the output clock. - 0 - - - ENABLE - Enable the output clock. - 0x1 - - - - - FRMEN - 1: free running mode. - 22 - 1 - read-write - - - FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable. - 23 - 1 - read-write - - - SKEWEN - Skew mode. - 24 - 1 - read-write - - - DISABLE - skewmode is disable. - 0 - - - ENABLE - skewmode is enable. - 0x1 - - - - - - - PLL1STAT - PLL1 550m status - 0x564 - 32 - read-write - 0 - 0x1F - - - LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. - 0 - 1 - read-only - - - PREDIVACK - pre-divider ratio change acknowledge. - 1 - 1 - read-only - - - FEEDDIVACK - feedback divider ratio change acknowledge. - 2 - 1 - read-only - - - POSTDIVACK - post-divider ratio change acknowledge. - 3 - 1 - read-only - - - FRMDET - free running detector output (active high). - 4 - 1 - read-only - - - - - PLL1NDEC - PLL1 550m N divider - 0x568 - 32 - read-write - 0 - 0x1FF - - - NDIV - pre-divider divider ratio (N-divider). - 0 - 8 - read-write - - - NREQ - pre-divider ratio change request. - 8 - 1 - read-write - - - - - PLL1MDEC - PLL1 550m M divider - 0x56C - 32 - read-write - 0 - 0x1FFFF - - - MDIV - feedback divider divider ratio (M-divider). - 0 - 16 - read-write - - - MREQ - feedback ratio change request. - 16 - 1 - read-write - - - - - PLL1PDEC - PLL1 550m P divider - 0x570 - 32 - read-write - 0 - 0x3F - - - PDIV - post-divider divider ratio (P-divider) - 0 - 5 - read-write - - - PREQ - feedback ratio change request. - 5 - 1 - read-write - - - - - PLL0CTRL - PLL0 550m control - 0x580 - 32 - read-write - 0 - 0x1FFFFFF - - - SELR - Bandwidth select R value. - 0 - 4 - read-write - - - SELI - Bandwidth select I value. - 4 - 6 - read-write - - - SELP - Bandwidth select P value. - 10 - 5 - read-write - - - BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - 15 - 1 - read-write - - - USED - use PLL. - 0 - - - BYPASSED - Bypass PLL input clock is sent directly to the PLL output. - 0x1 - - - - - BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - 16 - 1 - read-write - - - USED - use the divide-by-2 divider in the post-divider. - 0 - - - BYPASSED - bypass of the divide-by-2 divider in the post-divider. - 0x1 - - - - - LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. - 17 - 1 - read-write - - - BWDIRECT - Control of the bandwidth of the PLL. - 18 - 1 - read-write - - - SYNC - the bandwidth is changed synchronously with the feedback-divider. - 0 - - - DIRECT - modify the bandwidth of the PLL directly. - 0x1 - - - - - BYPASSPREDIV - bypass of the pre-divider. - 19 - 1 - read-write - - - USED - use the pre-divider. - 0 - - - BYPASSED - bypass of the pre-divider. - 0x1 - - - - - BYPASSPOSTDIV - bypass of the post-divider. - 20 - 1 - read-write - - - USED - use the post-divider. - 0 - - - BYPASSED - bypass of the post-divider. - 0x1 - - - - - CLKEN - enable the output clock. - 21 - 1 - read-write - - - DISABLE - disable the output clock. - 0 - - - ENABLE - enable the output clock. - 0x1 - - - - - FRMEN - free running mode. - 22 - 1 - read-write - - - DISABLE - free running mode is disable. - 0 - - - ENABLE - free running mode is enable. - 0x1 - - - - - FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable. - 23 - 1 - read-write - - - SKEWEN - skew mode. - 24 - 1 - read-write - - - DISABLE - skew mode is disable. - 0 - - - ENABLE - skew mode is enable. - 0x1 - - - - - - - PLL0STAT - PLL0 550m status - 0x584 - 32 - read-write - 0 - 0x1F - - - LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. - 0 - 1 - read-only - - - PREDIVACK - pre-divider ratio change acknowledge. - 1 - 1 - read-only - - - FEEDDIVACK - feedback divider ratio change acknowledge. - 2 - 1 - read-only - - - POSTDIVACK - post-divider ratio change acknowledge. - 3 - 1 - read-only - - - FRMDET - free running detector output (active high). - 4 - 1 - read-only - - - - - PLL0NDEC - PLL0 550m N divider - 0x588 - 32 - read-write - 0 - 0x1FF - - - NDIV - pre-divider divider ratio (N-divider). - 0 - 8 - read-write - - - NREQ - pre-divider ratio change request. - 8 - 1 - read-write - - - - - PLL0PDEC - PLL0 550m P divider - 0x58C - 32 - read-write - 0 - 0x3F - - - PDIV - post-divider divider ratio (P-divider) - 0 - 5 - read-write - - - PREQ - feedback ratio change request. - 5 - 1 - read-write - - - - - PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 - 0x590 - 32 - read-write - 0 - 0xFFFFFFFF - - - MD_LBS - input word of the wrapper bit 31 to 0. - 0 - 32 - read-write - - - - - PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 - 0x594 - 32 - read-write - 0 - 0x1FFFFFFF - - - MD_MBS - input word of the wrapper bit 32. - 0 - 1 - read-write - - - MD_REQ - md change request. - 1 - 1 - read-write - - - MF - programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3. - 2 - 3 - read-write - - - MR - programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1. - 5 - 3 - read-write - - - MC - modulation waveform control Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency spectrum. - 8 - 2 - read-write - - - MDIV_EXT - to select an external mdiv value. - 10 - 16 - read-write - - - MREQ - to select an external mreq value. - 26 - 1 - read-write - - - DITHER - dithering between two modulation frequencies in a random way or in a pseudo random way (white noise), in order to decrease the probability that the modulated waveform will occur with the same phase on a particular point on the screen. - 27 - 1 - read-write - - - SEL_EXT - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext. - 28 - 1 - read-write - - - - - FUNCRETENTIONCTRL - Functional retention control register - 0x704 - 32 - read-write - 0x50C000 - 0xFFFFFF - - - FUNCRETENA - functional retention in power down only. - 0 - 1 - read-write - - - DISABLE - disable functional retention. - 0 - - - ENABLE - enable functional retention. - 0x1 - - - - - RET_START - Start address divided by 4 inside SRAMX bank. - 1 - 13 - read-write - - - RET_LENTH - lenth of Scan chains to save. - 14 - 10 - read-write - - - - - CPUCTRL - CPU Control for multiple processors - 0x800 - 32 - read-write - 0x2C - 0x3D - - - CPU1CLKEN - CPU1 clock enable. - 3 - 1 - read-write - - - DISABLE - The CPU1 clock is not enabled. - 0 - - - ENABLE - The CPU1 clock is enabled. - 0x1 - - - - - CPU1RSTEN - CPU1 reset. - 5 - 1 - read-write - - - RELEASED - The CPU1 is not being reset. - 0 - - - ASSERTED - The CPU1 is being reset. - 0x1 - - - - - - - CPBOOT - Coprocessor Boot Address - 0x804 - 32 - read-write - 0 - 0xFFFFFFFF - - - CPBOOT - Coprocessor Boot Address for CPU1. - 0 - 32 - read-write - - - - - CPSTAT - CPU Status - 0x80C - 32 - read-write - 0 - 0xF - - - CPU0SLEEPING - The CPU0 sleeping state. - 0 - 1 - read-only - - - AWAKE - the CPU is not sleeping. - 0 - - - SLEEPING - the CPU is sleeping. - 0x1 - - - - - CPU1SLEEPING - The CPU1 sleeping state. - 1 - 1 - read-only - - - AWAKE - the CPU is not sleeping. - 0 - - - SLEEPING - the CPU is sleeping. - 0x1 - - - - - CPU0LOCKUP - The CPU0 lockup state. - 2 - 1 - read-only - - - AWAKE - the CPU is not in lockup. - 0 - - - SLEEPING - the CPU is in lockup. - 0x1 - - - - - CPU1LOCKUP - The CPU1 lockup state. - 3 - 1 - read-only - - - AWAKE - the CPU is not in lockup. - 0 - - - SLEEPING - the CPU is in lockup. - 0x1 - - - - - - - CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures - 0xA18 - 32 - read-write - 0x1 - 0x3FF - - - XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. - 1 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. - 2 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. - 3 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. - 4 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - CLKIN_ENA - Enable clock_in clock for clock module. - 5 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. - 6 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. - 7 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration. - 8 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. - 9 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - - - - - COMP_INT_CTRL - Comparator Interrupt control - 0xB10 - 32 - read-write - 0 - 0x3F - - - INT_ENABLE - Analog Comparator interrupt enable control:. - 0 - 1 - read-write - - - INT_DISABLE - interrupt disable. - 0 - - - INT_ENABLE - interrupt enable. - 0x1 - - - - - INT_CLEAR - Analog Comparator interrupt clear. - 1 - 1 - read-write - - - NONE - No effect. - 0 - - - CLEAR - Clear the interrupt. Self-cleared bit. - 0x1 - - - - - INT_CTRL - Comparator interrupt type selector:. - 2 - 3 - read-write - - - EDGE_DISABLE - The analog comparator interrupt edge sensitive is disabled. - 0 - - - LVL_DISABLE - The analog comparator interrupt level sensitive is disabled. - 0x1 - - - EDGE_RISING - analog comparator interrupt is rising edge sensitive. - 0x2 - - - LVL_HIGH - Analog Comparator interrupt is high level sensitive. - 0x3 - - - EDGE_FALLING - analog comparator interrupt is falling edge sensitive. - 0x4 - - - LVL_LOW - Analog Comparator interrupt is low level sensitive. - 0x5 - - - EDGE_BOTH - analog comparator interrupt is rising and falling edge sensitive. - 0x6 - - - LVL_DIS2 - The analog comparator interrupt level sensitive is disabled. - 0x7 - - - - - INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. - 5 - 1 - read-write - - - FILTER_INT - Select Analog Comparator filtered output as input for interrupt detection. - 0 - - - RAW_INT - Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when Analog comparator is used as wake up source in Power down mode. - 0x1 - - - - - - - COMP_INT_STATUS - Comparator Interrupt status - 0xB14 - 32 - read-write - 0 - 0x7 - - - STATUS - Interrupt status BEFORE Interrupt Enable. - 0 - 1 - read-only - - - NO_INT - no interrupt pending. - 0 - - - PENDING - interrupt pending. - 0x1 - - - - - INT_STATUS - Interrupt status AFTER Interrupt Enable. - 1 - 1 - read-only - - - NO_INT - no interrupt pending. - 0 - - - PENDING - interrupt pending. - 0x1 - - - - - VAL - comparator analog output. - 2 - 1 - read-only - - - SMALLER - P+ is smaller than P-. - 0 - - - GREATER - P+ is greater than P-. - 0x1 - - - - - - - AUTOCLKGATEOVERRIDE - Control automatic clock gating - 0xE04 - 32 - read-write - 0xFFFF - 0xFFFFFFFF - - - ROM - Control automatic clock gating of ROM controller. - 0 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - RAMX_CTRL - Control automatic clock gating of RAMX controller. - 1 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - RAM0_CTRL - Control automatic clock gating of RAM0 controller. - 2 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - RAM1_CTRL - Control automatic clock gating of RAM1 controller. - 3 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - RAM2_CTRL - Control automatic clock gating of RAM2 controller. - 4 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - RAM3_CTRL - Control automatic clock gating of RAM3 controller. - 5 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - RAM4_CTRL - Control automatic clock gating of RAM4 controller. - 6 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. - 7 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. - 8 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - CRCGEN - Control automatic clock gating of CRCGEN controller. - 11 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - SDMA0 - Control automatic clock gating of DMA0 controller. - 12 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - SDMA1 - Control automatic clock gating of DMA1 controller. - 13 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - USB0 - Control automatic clock gating of USB controller. - 14 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - SYSCON - Control automatic clock gating of synchronous system controller registers bank. - 15 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. - 16 - 16 - write-only - - - DISABLE - Bit Fields 0 - 15 of this register are not updated - 0 - - - ENABLE - Bit Fields 0 - 15 of this register are updated - 0xC0DE - - - - - - - GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module - 0xE08 - 32 - read-write - 0 - 0x1 - - - PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module. - 0 - 1 - read-write - - - USED - use the first stage of synchonization inside GPIO_INT module. - 0 - - - BYPASS - bypass of the first stage of synchonization inside GPIO_INT module. - 0x1 - - - - - - - DEBUG_LOCK_EN - Control write access to security registers. - 0xFA0 - 32 - read-write - 0x5 - 0xF - - - LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, CODESECURITYPROTCPU1, CPU0_DEBUG_FEATURES, CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. - 0 - 4 - read-write - - - DISABLE - Any other value than b1010: disable write access to all 6 registers. - 0 - - - ENABLE - 1010: Enable write access to all 6 registers. - 0xA - - - - - - - DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control. - 0xFA4 - 32 - read-write - 0 - 0xFFF - - - CPU0_DBGEN - CPU0 Invasive debug control:. - 0 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU0_NIDEN - CPU0 Non Invasive debug control:. - 2 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU0_SPIDEN - CPU0 Secure Invasive debug control:. - 4 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. - 6 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU1_DBGEN - CPU1 Invasive debug control:. - 8 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU1_NIDEN - CPU1 Non Invasive debug control:. - 10 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - - - DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register. - 0xFA8 - 32 - read-write - 0x555 - 0xFFF - - - CPU0_DBGEN - CPU0 (CPU0) Invasive debug control:. - 0 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU0_NIDEN - CPU0 Non Invasive debug control:. - 2 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU0_SPIDEN - CPU0 Secure Invasive debug control:. - 4 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. - 6 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU1_DBGEN - CPU1 Invasive debug control:. - 8 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - CPU1_NIDEN - CPU1 Non Invasive debug control:. - 10 - 2 - read-write - - - DISABLE - Any other value than b10: invasive debug is disable. - 0x1 - - - ENABLE - 10: Invasive debug is enabled. - 0x2 - - - - - - - KEY_BLOCK - block quiddikey/PUF all index. - 0xFBC - 32 - write-only - 0x3CC35AA5 - 0xFFFFFFFF - - - KEY_BLOCK - Write a value to block quiddikey/PUF all index. - 0 - 32 - write-only - - - - - DEBUG_AUTH_BEACON - Debug authentication BEACON register - 0xFC0 - 32 - read-write - 0 - 0xFFFFFFFF - - - BEACON - Set by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to application code. - 0 - 32 - read-write - - - - - CPUCFG - CPUs configuration register - 0xFD4 - 32 - read-write - 0x2 - 0x7 - - - CPU1ENABLE - Enable CPU1. - 2 - 1 - read-write - - - DISABLE - CPU1 is disable (Processor in reset). - 0 - - - ENABLE - CPU1 is enable. - 0x1 - - - - - - - DEVICE_ID0 - Device ID - 0xFF8 - 32 - read-only - 0 - 0xFFFFFFFF - - - ROM_REV_MINOR - ROM revision. - 20 - 4 - read-only - - - - - DIEID - Chip revision ID and Number - 0xFFC - 32 - read-only - 0x426B0 - 0xFFFFFF - - - REV_ID - Chip Metal Revision ID. - 0 - 4 - read-only - - - MCO_NUM_IN_DIE_ID - Chip Number 0x426B. - 4 - 20 - read-only - - - - - - - IOCON - I/O pin configuration (IOCON) - IOCON - 0x40001000 - - 0 - 0x100 - registers - - - - PIO0_0 - Digital I/O control for port 0 pins PIO0_0 - 0 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_1 - Digital I/O control for port 0 pins PIO0_1 - 0x4 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_2 - Digital I/O control for port 0 pins PIO0_2 - 0x8 - 32 - read-write - 0x110 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_3 - Digital I/O control for port 0 pins PIO0_3 - 0xC - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_4 - Digital I/O control for port 0 pins PIO0_4 - 0x10 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_5 - Digital I/O control for port 0 pins PIO0_5 - 0x14 - 32 - read-write - 0x120 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_6 - Digital I/O control for port 0 pins PIO0_6 - 0x18 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_7 - Digital I/O control for port 0 pins PIO0_7 - 0x1C - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_8 - Digital I/O control for port 0 pins PIO0_8 - 0x20 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_9 - Digital I/O control for port 0 pins PIO0_9 - 0x24 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_10 - Digital I/O control for port 0 pins PIO0_10 - 0x28 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_11 - Digital I/O control for port 0 pins PIO0_11 - 0x2C - 32 - read-write - 0x116 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_12 - Digital I/O control for port 0 pins PIO0_12 - 0x30 - 32 - read-write - 0x126 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_13 - Digital I/O control for port 0 pins PIO0_13 - 0x34 - 32 - read-write - 0x5000 - 0xFFFF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - SSEL - Supply Selection bit. - 11 - 1 - read-write - - - SEL3V3 - 3V3 Signaling in I2C Mode. - 0 - - - SEL1V8 - 1V8 Signaling in I2C Mode. - 0x1 - - - - - FILTEROFF - Controls input glitch filter. - 12 - 1 - read-write - - - ENABLED - Filter enabled. - 0 - - - DISABLED - Filter disabled. - 0x1 - - - - - ECS - Pull-up current source enable in I2C mode. - 13 - 1 - read-write - - - DISABLED - Disabled. IO is in open drain cell. - 0 - - - ENABLED - Enabled. Pull resistor is conencted. - 0x1 - - - - - EGP - Switch between GPIO mode and I2C mode. - 14 - 1 - read-write - - - I2C_MODE - I2C mode. - 0 - - - GPIO_MODE - GPIO mode. - 0x1 - - - - - I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. - 15 - 1 - read-write - - - FAST_MODE - I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. - 0 - - - STANDARD_MODE - I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. - 0x1 - - - - - - - PIO0_14 - Digital I/O control for port 0 pins PIO0_14 - 0x38 - 32 - read-write - 0x5000 - 0xFFFF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - SSEL - Supply Selection bit. - 11 - 1 - read-write - - - SEL3V3 - 3V3 Signaling in I2C Mode. - 0 - - - SEL1V8 - 1V8 Signaling in I2C Mode. - 0x1 - - - - - FILTEROFF - Controls input glitch filter. - 12 - 1 - read-write - - - ENABLED - Filter enabled. - 0 - - - DISABLED - Filter disabled. - 0x1 - - - - - ECS - Pull-up current source enable in I2C mode. - 13 - 1 - read-write - - - DISABLED - Disabled. IO is in open drain cell. - 0 - - - ENABLED - Enabled. Pull resistor is conencted. - 0x1 - - - - - EGP - Switch between GPIO mode and I2C mode. - 14 - 1 - read-write - - - I2C_MODE - I2C mode. - 0 - - - GPIO_MODE - GPIO mode. - 0x1 - - - - - I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. - 15 - 1 - read-write - - - FAST_MODE - I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. - 0 - - - STANDARD_MODE - I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. - 0x1 - - - - - - - PIO0_15 - Digital I/O control for port 0 pins PIO0_15 - 0x3C - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_16 - Digital I/O control for port 0 pins PIO0_16 - 0x40 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_17 - Digital I/O control for port 0 pins PIO0_17 - 0x44 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_18 - Digital I/O control for port 0 pins PIO0_18 - 0x48 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_19 - Digital I/O control for port 0 pins PIO0_19 - 0x4C - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_20 - Digital I/O control for port 0 pins PIO0_20 - 0x50 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_21 - Digital I/O control for port 0 pins PIO0_21 - 0x54 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_22 - Digital I/O control for port 0 pins PIO0_22 - 0x58 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_23 - Digital I/O control for port 0 pins PIO0_23 - 0x5C - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO0_24 - Digital I/O control for port 0 pins PIO0_24 - 0x60 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_25 - Digital I/O control for port 0 pins PIO0_25 - 0x64 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_26 - Digital I/O control for port 0 pins PIO0_26 - 0x68 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_27 - Digital I/O control for port 0 pins PIO0_27 - 0x6C - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_28 - Digital I/O control for port 0 pins PIO0_28 - 0x70 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_29 - Digital I/O control for port 0 pins PIO0_29 - 0x74 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_30 - Digital I/O control for port 0 pins PIO0_30 - 0x78 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO0_31 - Digital I/O control for port 0 pins PIO0_31 - 0x7C - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO1_0 - Digital I/O control for port 1 pins PIO1_0 - 0x80 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO1_1 - Digital I/O control for port 1 pins PIO1_1 - 0x84 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_2 - Digital I/O control for port 1 pins PIO1_2 - 0x88 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_3 - Digital I/O control for port 1 pins PIO1_3 - 0x8C - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_4 - Digital I/O control for port 1 pins PIO1_4 - 0x90 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_5 - Digital I/O control for port 1 pins PIO1_5 - 0x94 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_6 - Digital I/O control for port 1 pins PIO1_6 - 0x98 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_7 - Digital I/O control for port 1 pins PIO1_7 - 0x9C - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_8 - Digital I/O control for port 1 pins PIO1_8 - 0xA0 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO1_9 - Digital I/O control for port 1 pins PIO1_9 - 0xA4 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO1_10 - Digital I/O control for port 1 pins PIO1_10 - 0xA8 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_11 - Digital I/O control for port 1 pins PIO1_11 - 0xAC - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_12 - Digital I/O control for port 1 pins PIO1_12 - 0xB0 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_13 - Digital I/O control for port 1 pins PIO1_13 - 0xB4 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_14 - Digital I/O control for port 1 pins PIO1_14 - 0xB8 - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO1_15 - Digital I/O control for port 1 pins PIO1_15 - 0xBC - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_16 - Digital I/O control for port 1 pins PIO1_16 - 0xC0 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_17 - Digital I/O control for port 1 pins PIO1_17 - 0xC4 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_18 - Digital I/O control for port 1 pins PIO1_18 - 0xC8 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_19 - Digital I/O control for port 1 pins PIO1_19 - 0xCC - 32 - read-write - 0 - 0x7FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - ASW - Analog switch input control. - 10 - 1 - read-write - - - VALUE0 - For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). - 0 - - - VALUE1 - For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) - 0x1 - - - - - - - PIO1_20 - Digital I/O control for port 1 pins PIO1_20 - 0xD0 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_21 - Digital I/O control for port 1 pins PIO1_21 - 0xD4 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_22 - Digital I/O control for port 1 pins PIO1_22 - 0xD8 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_23 - Digital I/O control for port 1 pins PIO1_23 - 0xDC - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_24 - Digital I/O control for port 1 pins PIO1_24 - 0xE0 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_25 - Digital I/O control for port 1 pins PIO1_25 - 0xE4 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_26 - Digital I/O control for port 1 pins PIO1_26 - 0xE8 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_27 - Digital I/O control for port 1 pins PIO1_27 - 0xEC - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_28 - Digital I/O control for port 1 pins PIO1_28 - 0xF0 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_29 - Digital I/O control for port 1 pins PIO1_29 - 0xF4 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_30 - Digital I/O control for port 1 pins PIO1_30 - 0xF8 - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - PIO1_31 - Digital I/O control for port 1 pins PIO1_31 - 0xFC - 32 - read-write - 0 - 0x3FF - - - FUNC - Selects pin function. - 0 - 4 - read-write - - - ALT0 - Alternative connection 0. - 0 - - - ALT1 - Alternative connection 1. - 0x1 - - - ALT2 - Alternative connection 2. - 0x2 - - - ALT3 - Alternative connection 3. - 0x3 - - - ALT4 - Alternative connection 4. - 0x4 - - - ALT5 - Alternative connection 5. - 0x5 - - - ALT6 - Alternative connection 6. - 0x6 - - - ALT7 - Alternative connection 7. - 0x7 - - - - - MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - 4 - 2 - read-write - - - INACTIVE - Inactive. Inactive (no pull-down/pull-up resistor enabled). - 0 - - - PULL_DOWN - Pull-down. Pull-down resistor enabled. - 0x1 - - - PULL_UP - Pull-up. Pull-up resistor enabled. - 0x2 - - - REPEATER - Repeater. Repeater mode. - 0x3 - - - - - SLEW - Driver slew rate. - 6 - 1 - read-write - - - STANDARD - Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. - 0 - - - FAST - Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. - 0x1 - - - - - INVERT - Input polarity. - 7 - 1 - read-write - - - DISABLED - Disabled. Input function is not inverted. - 0 - - - ENABLED - Enabled. Input is function inverted. - 0x1 - - - - - DIGIMODE - Select Digital mode. - 8 - 1 - read-write - - - ANALOG - Disable digital mode. Digital input set to 0. - 0 - - - DIGITAL - Enable Digital mode. Digital input is enabled. - 0x1 - - - - - OD - Controls open-drain mode. - 9 - 1 - read-write - - - NORMAL - Normal. Normal push-pull output - 0 - - - OPEN_DRAIN - Open-drain. Simulated open-drain output (high drive disabled). - 0x1 - - - - - - - - - GINT0 - Group GPIO input interrupt (GINT0/1) - GINT - GINT - 0x40002000 - - 0 - 0x48 - registers - - - GINT0 - 2 - - - - CTRL - GPIO grouped interrupt control register - 0 - 32 - read-write - 0 - 0x7 - - - INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. - 0 - 1 - read-write - - - NO_REQUEST - No request. No interrupt request is pending. - 0 - - - REQUEST_ACTIVE - Request active. Interrupt request is active. - 0x1 - - - - - COMB - Combine enabled inputs for group interrupt - 1 - 1 - read-write - - - OR - Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). - 0 - - - AND - And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). - 0x1 - - - - - TRIG - Group interrupt trigger - 2 - 1 - read-write - - - EDGE_TRIGGERED - Edge-triggered. - 0 - - - LEVEL_TRIGGERED - Level-triggered. - 0x1 - - - - - - - 2 - 0x4 - PORT_POL[%s] - GPIO grouped interrupt port 0 polarity register - 0x20 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. - 0 - 32 - read-write - - - - - 2 - 0x4 - PORT_ENA[%s] - GPIO grouped interrupt port 0 enable register - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. - 0 - 32 - read-write - - - - - - - GINT1 - Group GPIO input interrupt (GINT0/1) - GINT - 0x40003000 - - 0 - 0x48 - registers - - - GINT1 - 3 - - - - PINT - Pin interrupt and pattern match (PINT) - PINT - PINT - 0x40004000 - - 0 - 0x34 - registers - - - PIN_INT0 - 4 - - - PIN_INT1 - 5 - - - PIN_INT2 - 6 - - - PIN_INT3 - 7 - - - PIN_INT4 - 32 - - - PIN_INT5 - 33 - - - PIN_INT6 - 34 - - - PIN_INT7 - 35 - - - - ISEL - Pin Interrupt Mode register - 0 - 32 - read-write - 0 - 0xFF - - - PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive - 0 - 8 - read-write - - - - - IENR - Pin interrupt level or rising edge interrupt enable register - 0x4 - 32 - read-write - 0 - 0xFF - - - ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. - 0 - 8 - read-write - - - - - SIENR - Pin interrupt level or rising edge interrupt set register - 0x8 - 32 - write-only - 0 - 0 - - - SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. - 0 - 8 - write-only - - - - - CIENR - Pin interrupt level (rising edge interrupt) clear register - 0xC - 32 - write-only - 0 - 0 - - - CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. - 0 - 8 - write-only - - - - - IENF - Pin interrupt active level or falling edge interrupt enable register - 0x10 - 32 - read-write - 0 - 0xFF - - - ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. - 0 - 8 - read-write - - - - - SIENF - Pin interrupt active level or falling edge interrupt set register - 0x14 - 32 - write-only - 0 - 0 - - - SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. - 0 - 8 - write-only - - - - - CIENF - Pin interrupt active level or falling edge interrupt clear register - 0x18 - 32 - write-only - 0 - 0 - - - CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. - 0 - 8 - write-only - - - - - RISE - Pin interrupt rising edge register - 0x1C - 32 - read-write - 0 - 0xFF - - - RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. - 0 - 8 - read-write - - - - - FALL - Pin interrupt falling edge register - 0x20 - 32 - read-write - 0 - 0xFF - - - FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. - 0 - 8 - read-write - - - - - IST - Pin interrupt status register - 0x24 - 32 - read-write - 0 - 0xFF - - - PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). - 0 - 8 - read-write - - - - - PMCTRL - Pattern match interrupt control register - 0x28 - 32 - read-write - 0 - 0xFF000003 - - - SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. - 0 - 1 - read-write - - - PIN_INTERRUPT - Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. - 0 - - - PATTERN_MATCH - Pattern match. Interrupts are driven in response to pattern matches. - 0x1 - - - - - ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. - 1 - 1 - read-write - - - DISABLED - Disabled. RXEV output to the CPU is disabled. - 0 - - - ENABLED - Enabled. RXEV output to the CPU is enabled. - 0x1 - - - - - PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs. - 24 - 8 - read-write - - - - - PMSRC - Pattern match interrupt bit-slice source register - 0x2C - 32 - read-write - 0 - 0xFFFFFF00 - - - SRC0 - Selects the input source for bit slice 0 - 8 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. - 0x7 - - - - - SRC1 - Selects the input source for bit slice 1 - 11 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. - 0x7 - - - - - SRC2 - Selects the input source for bit slice 2 - 14 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. - 0x7 - - - - - SRC3 - Selects the input source for bit slice 3 - 17 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. - 0x7 - - - - - SRC4 - Selects the input source for bit slice 4 - 20 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. - 0x7 - - - - - SRC5 - Selects the input source for bit slice 5 - 23 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. - 0x7 - - - - - SRC6 - Selects the input source for bit slice 6 - 26 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. - 0x7 - - - - - SRC7 - Selects the input source for bit slice 7 - 29 - 3 - read-write - - - INPUT0 - Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. - 0 - - - INPUT1 - Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. - 0x1 - - - INPUT2 - Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. - 0x2 - - - INPUT3 - Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. - 0x3 - - - INPUT4 - Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. - 0x4 - - - INPUT5 - Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. - 0x5 - - - INPUT6 - Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. - 0x6 - - - INPUT7 - Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. - 0x7 - - - - - - - PMCFG - Pattern match interrupt bit slice configuration register - 0x30 - 32 - read-write - 0 - 0xFFFFFF7F - - - PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. - 0 - 1 - read-write - - - NO_EFFECT - No effect. Slice 0 is not an endpoint. - 0 - - - ENDPOINT - endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. - 0x1 - - - - - PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. - 1 - 1 - read-write - - - NO_EFFECT - No effect. Slice 1 is not an endpoint. - 0 - - - ENDPOINT - endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. - 0x1 - - - - - PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. - 2 - 1 - read-write - - - NO_EFFECT - No effect. Slice 2 is not an endpoint. - 0 - - - ENDPOINT - endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. - 0x1 - - - - - PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. - 3 - 1 - read-write - - - NO_EFFECT - No effect. Slice 3 is not an endpoint. - 0 - - - ENDPOINT - endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. - 0x1 - - - - - PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. - 4 - 1 - read-write - - - NO_EFFECT - No effect. Slice 4 is not an endpoint. - 0 - - - ENDPOINT - endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. - 0x1 - - - - - PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. - 5 - 1 - read-write - - - NO_EFFECT - No effect. Slice 5 is not an endpoint. - 0 - - - ENDPOINT - endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. - 0x1 - - - - - PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. - 6 - 1 - read-write - - - NO_EFFECT - No effect. Slice 6 is not an endpoint. - 0 - - - ENDPOINT - endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. - 0x1 - - - - - CFG0 - Specifies the match contribution condition for bit slice 0. - 8 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - CFG1 - Specifies the match contribution condition for bit slice 1. - 11 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - CFG2 - Specifies the match contribution condition for bit slice 2. - 14 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - CFG3 - Specifies the match contribution condition for bit slice 3. - 17 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - CFG4 - Specifies the match contribution condition for bit slice 4. - 20 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - CFG5 - Specifies the match contribution condition for bit slice 5. - 23 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - CFG6 - Specifies the match contribution condition for bit slice 6. - 26 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - CFG7 - Specifies the match contribution condition for bit slice 7. - 29 - 3 - read-write - - - CONSTANT_HIGH - Constant HIGH. This bit slice always contributes to a product term match. - 0 - - - STICKY_RISING_EDGE - Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x1 - - - STICKY_FALLING_EDGE - Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x2 - - - STICKY_RISING_FALLING_EDGE - Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - 0x3 - - - HIGH_LEVEL - High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - 0x4 - - - LOW_LEVEL - Low level. Match occurs when there is a low level on the specified input. - 0x5 - - - CONSTANT_ZERO - Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - 0x6 - - - EVENT - Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - 0x7 - - - - - - - - - SECPINT - Pin interrupt and pattern match (PINT) - PINT - 0x40005000 - - 0 - 0x34 - registers - - - SEC_HYPERVISOR_CALL - 49 - - - SEC_GPIO_INT0_IRQ0 - 50 - - - SEC_GPIO_INT0_IRQ1 - 51 - - - SEC_VIO - 53 - - - - INPUTMUX - Input multiplexing (INPUT MUX) - INPUTMUX - 0x40006000 - - 0 - 0x7B4 - registers - - - - 7 - 0x4 - SCT0_INMUX[%s] - Input mux register for SCT0 input - 0 - 32 - read-write - 0x1F - 0x1F - - - INP_N - Input number to SCT0 inputs 0 to 6.. - 0 - 5 - read-write - - - val0 - SCT_GPI0 function selected from IOCON register - 0 - - - val1 - SCT_GPI1 function selected from IOCON register - 0x1 - - - val2 - SCT_GPI2 function selected from IOCON register - 0x2 - - - val3 - SCT_GPI3 function selected from IOCON register - 0x3 - - - val4 - SCT_GPI4 function selected from IOCON register - 0x4 - - - val5 - SCT_GPI5 function selected from IOCON register - 0x5 - - - val6 - SCT_GPI6 function selected from IOCON register - 0x6 - - - val7 - SCT_GPI7 function selected from IOCON register - 0x7 - - - val8 - T0_OUT0 ctimer 0 match[0] output - 0x8 - - - val9 - T1_OUT0 ctimer 1 match[0] output - 0x9 - - - val10 - T2_OUT0 ctimer 2 match[0] output - 0xA - - - val11 - T3_OUT0 ctimer 3 match[0] output - 0xB - - - val12 - T4_OUT0 ctimer 4 match[0] output - 0xC - - - val13 - ADC_IRQ interrupt request from ADC - 0xD - - - val14 - GPIOINT_BMATCH - 0xE - - - val15 - USB0_FRAME_TOGGLE - 0xF - - - val16 - USB1_FRAME_TOGGLE - 0x10 - - - val17 - COMP_OUTPUT output from analog comparator - 0x11 - - - val18 - I2S_SHARED_SCK[0] output from I2S pin sharing - 0x12 - - - val19 - I2S_SHARED_SCK[1] output from I2S pin sharing - 0x13 - - - val20 - I2S_SHARED_WS[0] output from I2S pin sharing - 0x14 - - - val21 - I2S_SHARED_WS[1] output from I2S pin sharing - 0x15 - - - val22 - ARM_TXEV interrupt event from cpu0 or cpu1 - 0x16 - - - val23 - DEBUG_HALTED from cpu0 or cpu1 - 0x17 - - - val24 - None - 0x18 - - - val24 - None - 0x19 - - - val24 - None - 0x1A - - - val24 - None - 0x1B - - - val24 - None - 0x1C - - - val24 - None - 0x1D - - - val24 - None - 0x1E - - - val24 - None - 0x1F - - - - - - - 4 - 0x4 - TIMER0CAPTSEL[%s] - Capture select registers for TIMER0 inputs - 0x20 - 32 - read-write - 0x1F - 0x1F - - - CAPTSEL - Input number to TIMER0 capture inputs 0 to 4 - 0 - 5 - read-write - - - val0 - CT_INP0 function selected from IOCON register - 0 - - - val1 - CT_INP1 function selected from IOCON register - 0x1 - - - val2 - CT_INP2 function selected from IOCON register - 0x2 - - - val3 - CT_INP3 function selected from IOCON register - 0x3 - - - val4 - CT_INP4 function selected from IOCON register - 0x4 - - - val5 - CT_INP5 function selected from IOCON register - 0x5 - - - val6 - CT_INP6 function selected from IOCON register - 0x6 - - - val7 - CT_INP7 function selected from IOCON register - 0x7 - - - val8 - CT_INP8 function selected from IOCON register - 0x8 - - - val9 - CT_INP9 function selected from IOCON register - 0x9 - - - val10 - CT_INP10 function selected from IOCON register - 0xA - - - val11 - CT_INP11 function selected from IOCON register - 0xB - - - val12 - CT_INP12 function selected from IOCON register - 0xC - - - val13 - CT_INP13 function selected from IOCON register - 0xD - - - val14 - CT_INP14 function selected from IOCON register - 0xE - - - val15 - CT_INP15 function selected from IOCON register - 0xF - - - val16 - CT_INP16 function selected from IOCON register - 0x10 - - - val17 - None - 0x11 - - - val18 - None - 0x12 - - - val19 - None - 0x13 - - - val20 - USB0_FRAME_TOGGLE - 0x14 - - - val21 - USB1_FRAME_TOGGLE - 0x15 - - - val22 - COMP_OUTPUT output from analog comparator - 0x16 - - - val23 - I2S_SHARED_WS[0] output from I2S pin sharing - 0x17 - - - val24 - I2S_SHARED_WS[1] output from I2S pin sharing - 0x18 - - - val25 - None - 0x19 - - - val25 - None - 0x1A - - - val25 - None - 0x1B - - - val25 - None - 0x1C - - - val25 - None - 0x1D - - - val25 - None - 0x1E - - - val25 - None - 0x1F - - - - - - - 4 - 0x4 - TIMER1CAPTSEL[%s] - Capture select registers for TIMER1 inputs - 0x40 - 32 - read-write - 0x1F - 0x1F - - - CAPTSEL - Input number to TIMER1 capture inputs 0 to 4 - 0 - 5 - read-write - - - val0 - CT_INP0 function selected from IOCON register - 0 - - - val1 - CT_INP1 function selected from IOCON register - 0x1 - - - val2 - CT_INP2 function selected from IOCON register - 0x2 - - - val3 - CT_INP3 function selected from IOCON register - 0x3 - - - val4 - CT_INP4 function selected from IOCON register - 0x4 - - - val5 - CT_INP5 function selected from IOCON register - 0x5 - - - val6 - CT_INP6 function selected from IOCON register - 0x6 - - - val7 - CT_INP7 function selected from IOCON register - 0x7 - - - val8 - CT_INP8 function selected from IOCON register - 0x8 - - - val9 - CT_INP9 function selected from IOCON register - 0x9 - - - val10 - CT_INP10 function selected from IOCON register - 0xA - - - val11 - CT_INP11 function selected from IOCON register - 0xB - - - val12 - CT_INP12 function selected from IOCON register - 0xC - - - val13 - CT_INP13 function selected from IOCON register - 0xD - - - val14 - CT_INP14 function selected from IOCON register - 0xE - - - val15 - CT_INP15 function selected from IOCON register - 0xF - - - val16 - CT_INP16 function selected from IOCON register - 0x10 - - - val17 - None - 0x11 - - - val18 - None - 0x12 - - - val19 - None - 0x13 - - - val20 - USB0_FRAME_TOGGLE - 0x14 - - - val21 - USB1_FRAME_TOGGLE - 0x15 - - - val22 - COMP_OUTPUT output from analog comparator - 0x16 - - - val23 - I2S_SHARED_WS[0] output from I2S pin sharing - 0x17 - - - val24 - I2S_SHARED_WS[1] output from I2S pin sharing - 0x18 - - - val25 - None - 0x19 - - - val25 - None - 0x1A - - - val25 - None - 0x1B - - - val25 - None - 0x1C - - - val25 - None - 0x1D - - - val25 - None - 0x1E - - - val25 - None - 0x1F - - - - - - - 4 - 0x4 - TIMER2CAPTSEL[%s] - Capture select registers for TIMER2 inputs - 0x60 - 32 - read-write - 0x1F - 0x1F - - - CAPTSEL - Input number to TIMER2 capture inputs 0 to 4 - 0 - 5 - read-write - - - val0 - CT_INP0 function selected from IOCON register - 0 - - - val1 - CT_INP1 function selected from IOCON register - 0x1 - - - val2 - CT_INP2 function selected from IOCON register - 0x2 - - - val3 - CT_INP3 function selected from IOCON register - 0x3 - - - val4 - CT_INP4 function selected from IOCON register - 0x4 - - - val5 - CT_INP5 function selected from IOCON register - 0x5 - - - val6 - CT_INP6 function selected from IOCON register - 0x6 - - - val7 - CT_INP7 function selected from IOCON register - 0x7 - - - val8 - CT_INP8 function selected from IOCON register - 0x8 - - - val9 - CT_INP9 function selected from IOCON register - 0x9 - - - val10 - CT_INP10 function selected from IOCON register - 0xA - - - val11 - CT_INP11 function selected from IOCON register - 0xB - - - val12 - CT_INP12 function selected from IOCON register - 0xC - - - val13 - CT_INP13 function selected from IOCON register - 0xD - - - val14 - CT_INP14 function selected from IOCON register - 0xE - - - val15 - CT_INP15 function selected from IOCON register - 0xF - - - val16 - CT_INP16 function selected from IOCON register - 0x10 - - - val17 - None - 0x11 - - - val18 - None - 0x12 - - - val19 - None - 0x13 - - - val20 - USB0_FRAME_TOGGLE - 0x14 - - - val21 - USB1_FRAME_TOGGLE - 0x15 - - - val22 - COMP_OUTPUT output from analog comparator - 0x16 - - - val23 - I2S_SHARED_WS[0] output from I2S pin sharing - 0x17 - - - val24 - I2S_SHARED_WS[1] output from I2S pin sharing - 0x18 - - - val25 - None - 0x19 - - - val25 - None - 0x1A - - - val25 - None - 0x1B - - - val25 - None - 0x1C - - - val25 - None - 0x1D - - - val25 - None - 0x1E - - - val25 - None - 0x1F - - - - - - - 8 - 0x4 - PINTSEL[%s] - Pin interrupt select register - 0xC0 - 32 - read-write - 0x7F - 0x7F - - - INTPIN - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. - 0 - 7 - read-write - - - - - 23 - 0x4 - DMA0_ITRIG_INMUX[%s] - Trigger select register for DMA0 channel - 0xE0 - 32 - read-write - 0x1F - 0x1F - - - INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22). - 0 - 5 - read-write - - - val0 - Pin interrupt 0 - 0 - - - val1 - Pin interrupt 1 - 0x1 - - - val2 - Pin interrupt 2 - 0x2 - - - val3 - Pin interrupt 3 - 0x3 - - - val4 - Timer CTIMER0 Match 0 - 0x4 - - - val5 - Timer CTIMER0 Match 1 - 0x5 - - - val6 - Timer CTIMER1 Match 0 - 0x6 - - - val7 - Timer CTIMER1 Match 1 - 0x7 - - - val8 - Timer CTIMER2 Match 0 - 0x8 - - - val9 - Timer CTIMER2 Match 1 - 0x9 - - - val10 - Timer CTIMER3 Match 0 - 0xA - - - val11 - Timer CTIMER3 Match 1 - 0xB - - - val12 - Timer CTIMER4 Match 0 - 0xC - - - val13 - Timer CTIMER4 Match 1 - 0xD - - - val14 - COMP_OUTPUT - 0xE - - - val15 - DMA0 output trigger mux 0 - 0xF - - - val16 - DMA0 output trigger mux 1 - 0x10 - - - val17 - DMA0 output trigger mux 1 - 0x11 - - - val18 - DMA0 output trigger mux 3 - 0x12 - - - val19 - SCT0 DMA request 0 - 0x13 - - - val20 - SCT0 DMA request 1 - 0x14 - - - val21 - HASH DMA RX trigger - 0x15 - - - val22 - None - 0x16 - - - val22 - None - 0x17 - - - val22 - None - 0x18 - - - val22 - None - 0x19 - - - val22 - None - 0x1A - - - val22 - None - 0x1B - - - val22 - None - 0x1C - - - val22 - None - 0x1D - - - val22 - None - 0x1E - - - val22 - None - 0x1F - - - - - - - 4 - 0x4 - DMA0_OTRIG_INMUX[%s] - DMA0 output trigger selection to become DMA0 trigger - 0x160 - 32 - read-write - 0x1F - 0x1F - - - INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22). - 0 - 5 - read-write - - - - - FREQMEAS_REF - Selection for frequency measurement reference clock - 0x180 - 32 - read-write - 0x1F - 0x1F - - - CLKIN - Clock source number (decimal value) for frequency measure function reference clock: - 0 - 5 - read-write - - - VALUE0 - External main crystal oscilator (Clock_in). - 0 - - - VALUE1 - FRO 12MHz clock. - 0x1 - - - VALUE2 - FRO 96MHz clock. - 0x2 - - - VALUE3 - Watchdog oscillator / FRO1MHz clock. - 0x3 - - - VALUE4 - 32 kHz oscillator (32k_clk) clock. - 0x4 - - - VALUE5 - main clock (main_clock). - 0x5 - - - VALUE6 - FREQME_GPIO_CLK_A. - 0x6 - - - VALUE7 - FREQME_GPIO_CLK_B. - 0x7 - - - - - - - FREQMEAS_TARGET - Selection for frequency measurement target clock - 0x184 - 32 - read-write - 0x1F - 0x1F - - - CLKIN - Clock source number (decimal value) for frequency measure function target clock: - 0 - 5 - read-write - - - VALUE0 - External main crystal oscilator (Clock_in). - 0 - - - VALUE1 - FRO 12MHz clock. - 0x1 - - - VALUE2 - FRO 96MHz clock. - 0x2 - - - VALUE3 - Watchdog oscillator / FRO1MHz clock. - 0x3 - - - VALUE4 - 32 kHz oscillator (32k_clk) clock. - 0x4 - - - VALUE5 - main clock (main_clock). - 0x5 - - - VALUE6 - FREQME_GPIO_CLK_A. - 0x6 - - - VALUE7 - FREQME_GPIO_CLK_B. - 0x7 - - - - - - - 4 - 0x4 - TIMER3CAPTSEL[%s] - Capture select registers for TIMER3 inputs - 0x1A0 - 32 - read-write - 0x1F - 0x1F - - - CAPTSEL - Input number to TIMER3 capture inputs 0 to 4 - 0 - 5 - read-write - - - val0 - CT_INP0 function selected from IOCON register - 0 - - - val1 - CT_INP1 function selected from IOCON register - 0x1 - - - val2 - CT_INP2 function selected from IOCON register - 0x2 - - - val3 - CT_INP3 function selected from IOCON register - 0x3 - - - val4 - CT_INP4 function selected from IOCON register - 0x4 - - - val5 - CT_INP5 function selected from IOCON register - 0x5 - - - val6 - CT_INP6 function selected from IOCON register - 0x6 - - - val7 - CT_INP7 function selected from IOCON register - 0x7 - - - val8 - CT_INP8 function selected from IOCON register - 0x8 - - - val9 - CT_INP9 function selected from IOCON register - 0x9 - - - val10 - CT_INP10 function selected from IOCON register - 0xA - - - val11 - CT_INP11 function selected from IOCON register - 0xB - - - val12 - CT_INP12 function selected from IOCON register - 0xC - - - val13 - CT_INP13 function selected from IOCON register - 0xD - - - val14 - CT_INP14 function selected from IOCON register - 0xE - - - val15 - CT_INP15 function selected from IOCON register - 0xF - - - val16 - CT_INP16 function selected from IOCON register - 0x10 - - - val17 - CT_INP17 function selected from IOCON register - 0x11 - - - val18 - CT_INP18 function selected from IOCON register - 0x12 - - - val19 - CT_INP19 function selected from IOCON register - 0x13 - - - val20 - USB0_FRAME_TOGGLE - 0x14 - - - val21 - USB1_FRAME_TOGGLE - 0x15 - - - val22 - COMP_OUTPUT output from analog comparator - 0x16 - - - val23 - I2S_SHARED_WS[0] output from I2S pin sharing - 0x17 - - - val24 - I2S_SHARED_WS[1] output from I2S pin sharing - 0x18 - - - val25 - None - 0x19 - - - val25 - None - 0x1A - - - val25 - None - 0x1B - - - val25 - None - 0x1C - - - val25 - None - 0x1D - - - val25 - None - 0x1E - - - val25 - None - 0x1F - - - - - - - 4 - 0x4 - TIMER4CAPTSEL[%s] - Capture select registers for TIMER4 inputs - 0x1C0 - 32 - read-write - 0x1F - 0x1F - - - CAPTSEL - Input number to TIMER4 capture inputs 0 to 4 - 0 - 5 - read-write - - - val0 - CT_INP0 function selected from IOCON register - 0 - - - val1 - CT_INP1 function selected from IOCON register - 0x1 - - - val2 - CT_INP2 function selected from IOCON register - 0x2 - - - val3 - CT_INP3 function selected from IOCON register - 0x3 - - - val4 - CT_INP4 function selected from IOCON register - 0x4 - - - val5 - CT_INP5 function selected from IOCON register - 0x5 - - - val6 - CT_INP6 function selected from IOCON register - 0x6 - - - val7 - CT_INP7 function selected from IOCON register - 0x7 - - - val8 - CT_INP8 function selected from IOCON register - 0x8 - - - val9 - CT_INP9 function selected from IOCON register - 0x9 - - - val10 - CT_INP10 function selected from IOCON register - 0xA - - - val11 - CT_INP11 function selected from IOCON register - 0xB - - - val12 - CT_INP12 function selected from IOCON register - 0xC - - - val13 - CT_INP13 function selected from IOCON register - 0xD - - - val14 - CT_INP14 function selected from IOCON register - 0xE - - - val15 - CT_INP15 function selected from IOCON register - 0xF - - - val16 - CT_INP16 function selected from IOCON register - 0x10 - - - val17 - CT_INP17 function selected from IOCON register - 0x11 - - - val18 - CT_INP18 function selected from IOCON register - 0x12 - - - val19 - CT_INP19 function selected from IOCON register - 0x13 - - - val20 - USB0_FRAME_TOGGLE - 0x14 - - - val21 - USB1_FRAME_TOGGLE - 0x15 - - - val22 - COMP_OUTPUT output from analog comparator - 0x16 - - - val23 - I2S_SHARED_WS[0] output from I2S pin sharing - 0x17 - - - val24 - I2S_SHARED_WS[1] output from I2S pin sharing - 0x18 - - - val25 - None - 0x19 - - - val25 - None - 0x1A - - - val25 - None - 0x1B - - - val25 - None - 0x1C - - - val25 - None - 0x1D - - - val25 - None - 0x1E - - - val25 - None - 0x1F - - - - - - - 2 - 0x4 - PINTSECSEL[%s] - Pin interrupt secure select register - 0x1E0 - 32 - read-write - 0x3F - 0x3F - - - INTPIN - Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31. - 0 - 6 - read-write - - - - - 10 - 0x4 - DMA1_ITRIG_INMUX[%s] - Trigger select register for DMA1 channel - 0x200 - 32 - read-write - 0xF - 0xF - - - INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9). - 0 - 4 - read-write - - - val0 - Pin interrupt 0 - 0 - - - val1 - Pin interrupt 1 - 0x1 - - - val2 - Pin interrupt 2 - 0x2 - - - val3 - Pin interrupt 3 - 0x3 - - - val4 - Timer CTIMER0 Match 0 - 0x4 - - - val5 - Timer CTIMER0 Match 1 - 0x5 - - - val6 - Timer CTIMER2 Match 0 - 0x6 - - - val7 - Timer CTIMER4 Match 0 - 0x7 - - - val8 - DMA1 output trigger mux 0 - 0x8 - - - val9 - DMA1 output trigger mux 1 - 0x9 - - - val10 - DMA1 output trigger mux 2 - 0xA - - - val11 - DMA1 output trigger mux 3 - 0xB - - - val12 - SCT0 DMA request 0 - 0xC - - - val13 - SCT0 DMA request 1 - 0xD - - - val14 - HASH DMA RX trigger - 0xE - - - val15 - None - 0xF - - - - - - - 4 - 0x4 - DMA1_OTRIG_INMUX[%s] - DMA1 output trigger selection to become DMA1 trigger - 0x240 - 32 - read-write - 0xF - 0xF - - - INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9). - 0 - 4 - read-write - - - - - DMA0_REQ_ENA - Enable DMA0 requests - 0x740 - 32 - read-write - 0x7FFFFF - 0x7FFFFF - - - REQ_ENA - Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. - 0 - 23 - read-write - - - - - DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register - 0x748 - 32 - write-only - 0 - 0x7FFFFF - - - SET - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register - 0 - 23 - write-only - - - - - DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register - 0x750 - 32 - write-only - 0 - 0x7FFFFF - - - CLR - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register - 0 - 23 - write-only - - - - - DMA1_REQ_ENA - Enable DMA1 requests - 0x760 - 32 - read-write - 0x3FF - 0x3FF - - - REQ_ENA - Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. - 0 - 10 - read-write - - - - - DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register - 0x768 - 32 - write-only - 0 - 0x3FF - - - SET - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register - 0 - 10 - write-only - - - - - DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register - 0x770 - 32 - write-only - 0 - 0x3FF - - - CLR - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register - 0 - 10 - write-only - - - - - DMA0_ITRIG_ENA - Enable DMA0 triggers - 0x780 - 32 - read-write - 0x3FFFFF - 0x3FFFFF - - - ITRIG_ENA - Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. - 0 - 22 - read-write - - - - - DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register - 0x788 - 32 - write-only - 0 - 0x3FFFFF - - - SET - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no change in DMA0_ITRIG_ENA register - 0 - 22 - write-only - - - - - DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register - 0x790 - 32 - write-only - 0 - 0x3FFFFF - - - CLR - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_ITRIG_ENA register - 0 - 22 - write-only - - - - - DMA1_ITRIG_ENA - Enable DMA1 triggers - 0x7A0 - 32 - read-write - 0x7FFF - 0x7FFF - - - ITRIG_ENA - Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. - 0 - 15 - read-write - - - - - DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register - 0x7A8 - 32 - write-only - 0 - 0x7FFF - - - SET - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no change in DMA1_ITRIG_ENA register - 0 - 15 - write-only - - - - - DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register - 0x7B0 - 32 - write-only - 0 - 0x7FFF - - - CLR - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIG_ENA register - 0 - 15 - write-only - - - - - - - CTIMER0 - Standard counter/timers (CTIMER0 to 4) - CTIMER - CTIMER - 0x40008000 - - 0 - 0x88 - registers - - - CTIMER0 - 10 - - - - IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. - 0 - 32 - read-write - 0 - 0xFF - - - MR0INT - Interrupt flag for match channel 0. - 0 - 1 - read-write - - - MR1INT - Interrupt flag for match channel 1. - 1 - 1 - read-write - - - MR2INT - Interrupt flag for match channel 2. - 2 - 1 - read-write - - - MR3INT - Interrupt flag for match channel 3. - 3 - 1 - read-write - - - CR0INT - Interrupt flag for capture channel 0 event. - 4 - 1 - read-write - - - CR1INT - Interrupt flag for capture channel 1 event. - 5 - 1 - read-write - - - CR2INT - Interrupt flag for capture channel 2 event. - 6 - 1 - read-write - - - CR3INT - Interrupt flag for capture channel 3 event. - 7 - 1 - read-write - - - - - TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. - 0x4 - 32 - read-write - 0 - 0x3 - - - CEN - Counter enable. - 0 - 1 - read-write - - - DISABLED - Disabled.The counters are disabled. - 0 - - - ENABLED - Enabled. The Timer Counter and Prescale Counter are enabled. - 0x1 - - - - - CRST - Counter reset. - 1 - 1 - read-write - - - DISABLED - Disabled. Do nothing. - 0 - - - ENABLED - Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero. - 0x1 - - - - - - - TC - Timer Counter - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - TCVAL - Timer counter value. - 0 - 32 - read-write - - - - - PR - Prescale Register - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - PRVAL - Prescale counter value. - 0 - 32 - read-write - - - - - PC - Prescale Counter - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - PCVAL - Prescale counter value. - 0 - 32 - read-write - - - - - MCR - Match Control Register - 0x14 - 32 - read-write - 0 - 0xF000FFF - - - MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. - 0 - 1 - read-write - - - MR0R - Reset on MR0: the TC will be reset if MR0 matches it. - 1 - 1 - read-write - - - MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. - 2 - 1 - read-write - - - MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. - 3 - 1 - read-write - - - MR1R - Reset on MR1: the TC will be reset if MR1 matches it. - 4 - 1 - read-write - - - MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. - 5 - 1 - read-write - - - MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. - 6 - 1 - read-write - - - MR2R - Reset on MR2: the TC will be reset if MR2 matches it. - 7 - 1 - read-write - - - MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. - 8 - 1 - read-write - - - MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. - 9 - 1 - read-write - - - MR3R - Reset on MR3: the TC will be reset if MR3 matches it. - 10 - 1 - read-write - - - MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. - 11 - 1 - read-write - - - MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). - 24 - 1 - read-write - - - MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). - 25 - 1 - read-write - - - MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). - 26 - 1 - read-write - - - MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). - 27 - 1 - read-write - - - - - 4 - 0x4 - MR[%s] - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. - 0x18 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCH - Timer counter match value. - 0 - 32 - read-write - - - - - CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. - 0x28 - 32 - read-write - 0 - 0xFFF - - - CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 0 - 1 - read-write - - - CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 1 - 1 - read-write - - - CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. - 2 - 1 - read-write - - - CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 3 - 1 - read-write - - - CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 4 - 1 - read-write - - - CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. - 5 - 1 - read-write - - - CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 6 - 1 - read-write - - - CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 7 - 1 - read-write - - - CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. - 8 - 1 - read-write - - - CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 9 - 1 - read-write - - - CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. - 10 - 1 - read-write - - - CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. - 11 - 1 - read-write - - - - - 4 - 0x4 - CR[%s] - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. - 0x2C - 32 - read-only - 0 - 0xFFFFFFFF - - - CAP - Timer counter capture value. - 0 - 32 - read-only - - - - - EMR - External Match Register. The EMR controls the match function and the external match pins. - 0x3C - 32 - read-write - 0 - 0xFFF - - - EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - 0 - 1 - read-write - - - EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - 1 - 1 - read-write - - - EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - 2 - 1 - read-write - - - EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - 3 - 1 - read-write - - - EMC0 - External Match Control 0. Determines the functionality of External Match 0. - 4 - 2 - read-write - - - DO_NOTHING - Do Nothing. - 0 - - - CLEAR - Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). - 0x1 - - - SET - Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). - 0x2 - - - TOGGLE - Toggle. Toggle the corresponding External Match bit/output. - 0x3 - - - - - EMC1 - External Match Control 1. Determines the functionality of External Match 1. - 6 - 2 - read-write - - - DO_NOTHING - Do Nothing. - 0 - - - CLEAR - Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). - 0x1 - - - SET - Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). - 0x2 - - - TOGGLE - Toggle. Toggle the corresponding External Match bit/output. - 0x3 - - - - - EMC2 - External Match Control 2. Determines the functionality of External Match 2. - 8 - 2 - read-write - - - DO_NOTHING - Do Nothing. - 0 - - - CLEAR - Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). - 0x1 - - - SET - Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). - 0x2 - - - TOGGLE - Toggle. Toggle the corresponding External Match bit/output. - 0x3 - - - - - EMC3 - External Match Control 3. Determines the functionality of External Match 3. - 10 - 2 - read-write - - - DO_NOTHING - Do Nothing. - 0 - - - CLEAR - Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). - 0x1 - - - SET - Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). - 0x2 - - - TOGGLE - Toggle. Toggle the corresponding External Match bit/output. - 0x3 - - - - - - - CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. - 0x70 - 32 - read-write - 0 - 0xFF - - - CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. - 0 - 2 - read-write - - - TIMER - Timer Mode. Incremented every rising APB bus clock edge. - 0 - - - COUNTER_RISING_EDGE - Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. - 0x1 - - - COUNTER_FALLING_EDGE - Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. - 0x2 - - - COUNTER_DUAL_EDGE - Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. - 0x3 - - - - - CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. - 2 - 2 - read-write - - - CHANNEL_0 - Channel 0. CAPn.0 for CTIMERn - 0 - - - CHANNEL_1 - Channel 1. CAPn.1 for CTIMERn - 0x1 - - - CHANNEL_2 - Channel 2. CAPn.2 for CTIMERn - 0x2 - - - CHANNEL_3 - Channel 3. CAPn.3 for CTIMERn - 0x3 - - - - - ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. - 4 - 1 - read-write - - - SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. - 5 - 3 - read-write - - - CHANNEL_0_RISING - Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - 0 - - - CHANNEL_0_FALLING - Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - 0x1 - - - CHANNEL_1_RISING - Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - 0x2 - - - CHANNEL_1_FALLING - Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - 0x3 - - - CHANNEL_2_RISING - Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - 0x4 - - - CHANNEL_2_FALLING - Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - 0x5 - - - - - - - PWMC - PWM Control Register. This register enables PWM mode for the external match pins. - 0x74 - 32 - read-write - 0 - 0xF - - - PWMEN0 - PWM mode enable for channel0. - 0 - 1 - read-write - - - MATCH - Match. CTIMERn_MAT0 is controlled by EM0. - 0 - - - PWM - PWM. PWM mode is enabled for CTIMERn_MAT0. - 0x1 - - - - - PWMEN1 - PWM mode enable for channel1. - 1 - 1 - read-write - - - MATCH - Match. CTIMERn_MAT01 is controlled by EM1. - 0 - - - PWM - PWM. PWM mode is enabled for CTIMERn_MAT1. - 0x1 - - - - - PWMEN2 - PWM mode enable for channel2. - 2 - 1 - read-write - - - MATCH - Match. CTIMERn_MAT2 is controlled by EM2. - 0 - - - PWM - PWM. PWM mode is enabled for CTIMERn_MAT2. - 0x1 - - - - - PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. - 3 - 1 - read-write - - - MATCH - Match. CTIMERn_MAT3 is controlled by EM3. - 0 - - - PWM - PWM. PWM mode is enabled for CT132Bn_MAT3. - 0x1 - - - - - - - 4 - 0x4 - MSR[%s] - Match Shadow Register - 0x78 - 32 - read-write - 0 - 0xFFFFFFFF - - - SHADOW - Timer counter match shadow value. - 0 - 32 - read-write - - - - - - - CTIMER1 - Standard counter/timers (CTIMER0 to 4) - CTIMER - 0x40009000 - - 0 - 0x88 - registers - - - CTIMER1 - 11 - - - - CTIMER2 - Standard counter/timers (CTIMER0 to 4) - CTIMER - 0x40028000 - - 0 - 0x88 - registers - - - CTIMER2 - 36 - - - - CTIMER3 - Standard counter/timers (CTIMER0 to 4) - CTIMER - 0x40029000 - - 0 - 0x88 - registers - - - CTIMER3 - 13 - - - - CTIMER4 - Standard counter/timers (CTIMER0 to 4) - CTIMER - 0x4002A000 - - 0 - 0x88 - registers - - - CTIMER4 - 37 - - - - WWDT - Windowed Watchdog Timer (WWDT) - WWDT - 0x4000C000 - - 0 - 0x1C - registers - - - WDT_BOD - 0 - - - - MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. - 0 - 32 - read-write - 0 - 0x3F - - - WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently. - 0 - 1 - read-write - - - STOP - Stop. The watchdog timer is stopped. - 0 - - - RUN - Run. The watchdog timer is running. - 0x1 - - - - - WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. - 1 - 1 - read-write - - - INTERRUPT - Interrupt. A watchdog time-out will not cause a chip reset. - 0 - - - RESET - Reset. A watchdog time-out will cause a chip reset. - 0x1 - - - - - WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1. - 2 - 1 - read-write - - - WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. - 3 - 1 - read-write - - - WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. - 4 - 1 - read-write - - - FLEXIBLE - Flexible. The watchdog time-out value (TC) can be changed at any time. - 0 - - - THRESHOLD - Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. - 0x1 - - - - - - - TC - Watchdog timer constant register. This 24-bit register determines the time-out value. - 0x4 - 32 - read-write - 0xFF - 0xFFFFFF - - - COUNT - Watchdog time-out value. - 0 - 24 - read-write - - - - - FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. - 0x8 - 32 - write-only - 0 - 0 - - - FEED - Feed value should be 0xAA followed by 0x55. - 0 - 8 - write-only - - - - - TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. - 0xC - 32 - read-only - 0xFF - 0xFFFFFF - - - COUNT - Counter timer value. - 0 - 24 - read-only - - - - - WARNINT - Watchdog Warning Interrupt compare value. - 0x14 - 32 - read-write - 0 - 0x3FF - - - WARNINT - Watchdog warning interrupt compare value. - 0 - 10 - read-write - - - - - WINDOW - Watchdog Window compare value. - 0x18 - 32 - read-write - 0xFFFFFF - 0xFFFFFF - - - WINDOW - Watchdog window value. - 0 - 24 - read-write - - - - - - - MRT0 - Multi-Rate Timer (MRT) - MRT - 0x4000D000 - - 0 - 0xFC - registers - - - MRT0 - 9 - - - - 4 - 0x10 - CHANNEL[%s] - no description available - 0 - - INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. - 0 - 32 - read-write - 0 - 0x80FFFFFF - - - IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval. - 0 - 24 - read-write - - - LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. - 31 - 1 - read-write - - - NO_FORCE_LOAD - No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected. - 0 - - - FORCE_LOAD - Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. - 0x1 - - - - - - - TIMER - MRT Timer register. This register reads the value of the down-counter. - 0x4 - 32 - read-only - 0xFFFFFF - 0xFFFFFF - - - VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF). - 0 - 24 - read-only - - - - - CTRL - MRT Control register. This register controls the MRT modes. - 0x8 - 32 - read-write - 0 - 0x7 - - - INTEN - Enable the TIMERn interrupt. - 0 - 1 - read-write - - - DISABLED - Disabled. TIMERn interrupt is disabled. - 0 - - - ENABLED - Enabled. TIMERn interrupt is enabled. - 0x1 - - - - - MODE - Selects timer mode. - 1 - 2 - read-write - - - REPEAT_INTERRUPT_MODE - Repeat interrupt mode. - 0 - - - ONE_SHOT_INTERRUPT_MODE - One-shot interrupt mode. - 0x1 - - - ONE_SHOT_STALL_MODE - One-shot stall mode. - 0x2 - - - - - - - STAT - MRT Status register. - 0xC - 32 - read-write - 0 - 0x7 - - - INTFLAG - Monitors the interrupt flag. - 0 - 1 - read-write - - - NO_PENDING_INTERRUPT - No pending interrupt. Writing a zero is equivalent to no operation. - 0 - - - PENDING_INTERRUPT - Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. - 0x1 - - - - - RUN - Indicates the state of TIMERn. This bit is read-only. - 1 - 1 - read-write - - - IDLE_STATE - Idle state. TIMERn is stopped. - 0 - - - RUNNING - Running. TIMERn is running. - 0x1 - - - - - INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes. - 2 - 1 - read-write - - - NO - This channel is not in use. - 0 - - - YES - This channel is in use. - 0x1 - - - - - - - - MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. - 0xF0 - 32 - read-write - 0x173 - 0x800001FF - - - NOC - Identifies the number of channels in this MRT.(4 channels on this device.) - 0 - 4 - read-write - - - NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.) - 4 - 5 - read-write - - - MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. - 31 - 1 - read-write - - - HARDWARE_STATUS_MODE - Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. - 0 - - - MULTI_TASK_MODE - Multi-task mode. - 0x1 - - - - - - - IDLE_CH - Idle channel register. This register returns the number of the first idle channel. - 0xF4 - 32 - read-only - 0 - 0xF0 - - - CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details. - 4 - 4 - read-only - - - - - IRQ_FLAG - Global interrupt flag register - 0xF8 - 32 - read-write - 0 - 0xF - - - GFLAG0 - Monitors the interrupt flag of TIMER0. - 0 - 1 - read-write - - - NO_PENDING_INTERRUPT - No pending interrupt. Writing a zero is equivalent to no operation. - 0 - - - PENDING_INTERRUPT - Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. - 0x1 - - - - - GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0. - 1 - 1 - read-write - - - GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0. - 2 - 1 - read-write - - - GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0. - 3 - 1 - read-write - - - - - - - UTICK0 - Micro-tick Timer (UTICK) - UTICK - 0x4000E000 - - 0 - 0x20 - registers - - - UTICK0 - 8 - - - - CTRL - Control register. - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer. - 0 - 31 - read-write - - - REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. - 31 - 1 - read-write - - - - - STAT - Status register. - 0x4 - 32 - read-write - 0 - 0x3 - - - INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any value to this register clears this flag. - 0 - 1 - read-write - - - ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. - 1 - 1 - read-write - - - - - CFG - Capture configuration register. - 0x8 - 32 - read-write - 0 - 0xF0F - - - CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled. - 0 - 1 - read-write - - - CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled. - 1 - 1 - read-write - - - CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled. - 2 - 1 - read-write - - - CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled. - 3 - 1 - read-write - - - CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. - 8 - 1 - read-write - - - CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. - 9 - 1 - read-write - - - CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. - 10 - 1 - read-write - - - CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. - 11 - 1 - read-write - - - - - CAPCLR - Capture clear register. - 0xC - 32 - write-only - 0 - 0 - - - CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value. - 0 - 1 - write-only - - - CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value. - 1 - 1 - write-only - - - CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value. - 2 - 1 - write-only - - - CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value. - 3 - 1 - write-only - - - - - 4 - 0x4 - CAP[%s] - Capture register . - 0x10 - 32 - read-only - 0 - 0xFFFFFFFF - - - CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower than the actual value of the Micro-tick Timer at the moment of the capture event. - 0 - 31 - read-only - - - VALID - Capture Valid. When 1, a value has been captured based on a transition of the related UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. - 31 - 1 - read-only - - - - - - - ANACTRL - ANALOGCTRL - ANACTRL - 0x40013000 - - 0 - 0x108 - registers - - - - ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) - 0 - 32 - read-write - 0 - 0x1 - - - FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source. - 0 - 1 - read-write - - - EFUSE - FRO192M trimming and 'Enable' comes from eFUSE. - 0 - - - FRO192MCTRL - FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers. - 0x1 - - - - - - - ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers - 0x4 - 32 - read-only - 0x50000000 - 0xF0003FFF - - - FLASH_PWRDWN - Flash Power Down status. - 12 - 1 - read-only - - - PWRUP - Flash is not in power down mode. - 0 - - - PWRDWN - Flash is in power down mode. - 0x1 - - - - - FLASH_INIT_ERROR - Flash initialization error status. - 13 - 1 - read-only - - - NOERROR - No error. - 0 - - - ERROR - At least one error occured during flash initialization.. - 0x1 - - - - - - - FREQ_ME_CTRL - Frequency Measure function control register - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPVAL_SCALE - Frequency measure result /Frequency measur scale - 0 - 31 - read-write - - - PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 30:0). - 31 - 1 - read-write - - - - - FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register - 0x10 - 32 - read-write - 0x80D01A - 0xF3FFFFBF - - - ENA_12MHZCLK - 12 MHz clock control. - 14 - 1 - read-write - - - DISABLE - 12 MHz clock is disabled. - 0 - - - ENABLE - 12 MHz clock is enabled. - 0x1 - - - - - ENA_48MHZCLK - 48 MHz clock control. - 15 - 1 - read-write - - - ENABLE - 48 MHz clock is enabled. - 0x1 - - - - - DAC_TRIM - Frequency trim. - 16 - 8 - read-write - - - USBCLKADJ - If this bit is set and the USB peripheral is enabled into full speed device mode, the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF packets. - 24 - 1 - read-write - - - USBMODCHG - If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0. - 25 - 1 - read-only - - - ENA_96MHZCLK - 96 MHz clock control. - 30 - 1 - read-write - - - DISABLE - 96 MHz clock is disabled. - 0 - - - ENABLE - 96 MHz clock is enabled. - 0x1 - - - - - WRTRIM - This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields. - 31 - 1 - write-only - - - - - FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register - 0x14 - 32 - read-write - 0x3 - 0x3 - - - CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. - 0 - 1 - read-only - - - NOCLKOUT - No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). - 0 - - - CLKOUT - Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). - 0x1 - - - - - ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses the threshold voltage of a SLVT transistor, this output signal will go high. It is also possible to observe the clk_valid signal. - 1 - 1 - read-only - - - - - ADC_CTRL - General Purpose ADC VBAT Divider branch control - 0x18 - 32 - read-write - 0 - 0x1 - - - VBATDIVENABLE - Switch On/Off VBAT divider branch. - 0 - 1 - read-write - - - DISABLE - VBAT divider branch is disabled. - 0 - - - ENABLE - VBAT divider branch is enabled. - 0x1 - - - - - - - XO32M_CTRL - High speed Crystal Oscillator Control register - 0x20 - 32 - read-write - 0x21428A - 0x1FFFFFFE - - - SLAVE - Xo in slave mode. - 4 - 1 - read-write - - - OSC_CAP_IN - Tune capa banks of High speed Crystal Oscillator input pin - 8 - 7 - read-write - - - OSC_CAP_OUT - Tune capa banks of High speed Crystal Oscillator output pin - 15 - 7 - read-write - - - ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. - 22 - 1 - read-write - - - DISABLE - XO AC buffer bypass is disabled. - 0 - - - ENABLE - XO AC buffer bypass is enabled. - 0x1 - - - - - ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL. - 23 - 1 - read-write - - - DISABLE - High speed Crystal oscillator output to USB HS PLL is disabled. - 0 - - - ENABLE - High speed Crystal oscillator output to USB HS PLL is enabled. - 0x1 - - - - - ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system. - 24 - 1 - read-write - - - DISABLE - High speed Crystal oscillator output to CPU system is disabled. - 0 - - - ENABLE - High speed Crystal oscillator output to CPU system is enabled. - 0x1 - - - - - - - XO32M_STATUS - High speed Crystal Oscillator Status register - 0x24 - 32 - read-only - 0 - 0x1 - - - XO_READY - Indicates XO out frequency statibilty. - 0 - 1 - read-only - - - NOT_STABLE - XO output frequency is not yet stable. - 0 - - - STABLE - XO output frequency is stable. - 0x1 - - - - - - - BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register - 0x30 - 32 - read-write - 0 - 0x3F - - - BODVBAT_INT_ENABLE - BOD VBAT interrupt control. - 0 - 1 - read-write - - - DISABLE - BOD VBAT interrupt is disabled. - 0 - - - ENABLE - BOD VBAT interrupt is enabled. - 0x1 - - - - - BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit. - 1 - 1 - read-write - - - BODCORE_INT_ENABLE - BOD CORE interrupt control. - 2 - 1 - read-write - - - DISABLE - BOD CORE interrupt is disabled. - 0 - - - ENABLE - BOD CORE interrupt is enabled. - 0x1 - - - - - BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. - 3 - 1 - read-write - - - DCDC_INT_ENABLE - DCDC interrupt control. - 4 - 1 - read-write - - - DISABLE - DCDC interrupt is disabled. - 0 - - - ENABLE - DCDC interrupt is enabled. - 0x1 - - - - - DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. - 5 - 1 - read-write - - - - - BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register - 0x34 - 32 - read-only - 0x104 - 0x1FF - - - BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. - 0 - 1 - read-only - - - NOT_PENDING - No interrupt pending.. - 0 - - - PENDING - Interrupt pending.. - 0x1 - - - - - BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. - 1 - 1 - read-only - - - NOT_PENDING - No interrupt pending.. - 0 - - - PENDING - Interrupt pending.. - 0x1 - - - - - BODVBAT_VAL - Current value of BOD VBAT power status output. - 2 - 1 - read-only - - - NOT_OK - VBAT voltage level is below the threshold. - 0 - - - OK - VBAT voltage level is above the threshold. - 0x1 - - - - - BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. - 3 - 1 - read-only - - - NOT_PENDING - No interrupt pending.. - 0 - - - PENDING - Interrupt pending.. - 0x1 - - - - - BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. - 4 - 1 - read-only - - - NOT_PENDING - No interrupt pending.. - 0 - - - PENDING - Interrupt pending.. - 0x1 - - - - - BODCORE_VAL - Current value of BOD CORE power status output. - 5 - 1 - read-only - - - NOT_OK - CORE voltage level is below the threshold. - 0 - - - OK - CORE voltage level is above the threshold. - 0x1 - - - - - DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. - 6 - 1 - read-only - - - NOT_PENDING - No interrupt pending.. - 0 - - - PENDING - Interrupt pending.. - 0x1 - - - - - DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. - 7 - 1 - read-only - - - NOT_PENDING - No interrupt pending.. - 0 - - - PENDING - Interrupt pending.. - 0x1 - - - - - DCDC_VAL - Current value of DCDC power status output. - 8 - 1 - read-only - - - NOT_OK - DCDC output Voltage is below the targeted regulation level. - 0 - - - OK - DCDC output Voltage is above the targeted regulation level. - 0x1 - - - - - - - RINGO0_CTRL - First Ring Oscillator module control register. - 0x40 - 32 - read-write - 0x40 - 0x803F1FFF - - - SL - Select short or long ringo (for all ringos types). - 0 - 1 - read-write - - - SHORT - Select short ringo (few elements). - 0 - - - LONG - Select long ringo (many elements). - 0x1 - - - - - FS - Ringo frequency output divider. - 1 - 1 - read-write - - - FAST - High frequency output (frequency lower than 100 MHz). - 0 - - - SLOW - Low frequency output (frequency lower than 10 MHz). - 0x1 - - - - - SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control. - 2 - 2 - read-write - - - NORMAL - Normal mode. - 0 - - - P_MONITOR - P-Monitor mode. Measure with weak P transistor. - 0x1 - - - N_MONITOR - P-Monitor mode. Measure with weak N transistor. - 0x2 - - - FORBIDDEN - Don't use. - 0x3 - - - - - PD - Ringo module Power control. - 4 - 1 - read-write - - - POWERED_ON - The Ringo module is enabled. - 0 - - - POWERED_DOWN - The Ringo module is disabled. - 0x1 - - - - - E_ND0 - First NAND2-based ringo control. - 5 - 1 - read-write - - - DISABLE - First NAND2-based ringo is disabled. - 0 - - - ENABLE - First NAND2-based ringo is enabled. - 0x1 - - - - - E_ND1 - Second NAND2-based ringo control. - 6 - 1 - read-write - - - DISABLE - Second NAND2-based ringo is disabled. - 0 - - - ENABLE - Second NAND2-based ringo is enabled. - 0x1 - - - - - E_NR0 - First NOR2-based ringo control. - 7 - 1 - read-write - - - DISABLE - First NOR2-based ringo is disabled. - 0 - - - ENABLE - First NOR2-based ringo is enabled. - 0x1 - - - - - E_NR1 - Second NOR2-based ringo control. - 8 - 1 - read-write - - - DISABLE - Second NORD2-based ringo is disabled. - 0 - - - ENABLE - Second NORD2-based ringo is enabled. - 0x1 - - - - - E_IV0 - First Inverter-based ringo control. - 9 - 1 - read-write - - - DISABLE - First INV-based ringo is disabled. - 0 - - - ENABLE - First INV-based ringo is enabled. - 0x1 - - - - - E_IV1 - Second Inverter-based ringo control. - 10 - 1 - read-write - - - DISABLE - Second INV-based ringo is disabled. - 0 - - - ENABLE - Second INV-based ringo is enabled. - 0x1 - - - - - E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control. - 11 - 1 - read-write - - - DISABLE - First PN-based ringo is disabled. - 0 - - - ENABLE - First PN-based ringo is enabled. - 0x1 - - - - - E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control. - 12 - 1 - read-write - - - DISABLE - Second PN-based ringo is disabled. - 0 - - - ENABLE - Second PN-based ringo is enabled. - 0x1 - - - - - DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) - 16 - 4 - read-write - - - DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. - 31 - 1 - read-only - - - - - RINGO1_CTRL - Second Ring Oscillator module control register. - 0x44 - 32 - read-write - 0x40 - 0x803F01FF - - - S - Select short or long ringo (for all ringos types). - 0 - 1 - read-write - - - SHORT - Select short ringo (few elements). - 0 - - - LONG - Select long ringo (many elements). - 0x1 - - - - - FS - Ringo frequency output divider. - 1 - 1 - read-write - - - FAST - High frequency output (frequency lower than 100 MHz). - 0 - - - SLOW - Low frequency output (frequency lower than 10 MHz). - 0x1 - - - - - PD - Ringo module Power control. - 2 - 1 - read-write - - - POWERED_ON - The Ringo module is enabled. - 0 - - - POWERED_DOWN - The Ringo module is disabled. - 0x1 - - - - - E_R24 - . - 3 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_R35 - . - 4 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M2 - Metal 2 (M2) monitor control. - 5 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M3 - Metal 3 (M3) monitor control. - 6 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M4 - Metal 4 (M4) monitor control. - 7 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M5 - Metal 5 (M5) monitor control. - 8 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) - 16 - 4 - read-write - - - DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. - 31 - 1 - read-only - - - - - RINGO2_CTRL - Third Ring Oscillator module control register. - 0x48 - 32 - read-write - 0x40 - 0x803F01FF - - - S - Select short or long ringo (for all ringos types). - 0 - 1 - read-write - - - SHORT - Select short ringo (few elements). - 0 - - - LONG - Select long ringo (many elements). - 0x1 - - - - - FS - Ringo frequency output divider. - 1 - 1 - read-write - - - FAST - High frequency output (frequency lower than 100 MHz). - 0 - - - SLOW - Low frequency output (frequency lower than 10 MHz). - 0x1 - - - - - PD - Ringo module Power control. - 2 - 1 - read-write - - - POWERED_ON - The Ringo module is enabled. - 0 - - - POWERED_DOWN - The Ringo module is disabled. - 0x1 - - - - - E_R24 - . - 3 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_R35 - . - 4 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M2 - Metal 2 (M2) monitor control. - 5 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M3 - Metal 3 (M3) monitor control. - 6 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M4 - Metal 4 (M4) monitor control. - 7 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - E_M5 - Metal 5 (M5) monitor control. - 8 - 1 - read-write - - - DISABLE - Ringo is disabled. - 0 - - - ENABLE - Ringo is enabled. - 0x1 - - - - - DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) - 16 - 4 - read-write - - - DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. - 31 - 1 - read-only - - - - - LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register - 0xB0 - 32 - read-write - 0x3A0 - 0x3FE - - - BYPASS - Activate LDO bypass. - 1 - 1 - read-write - - - DISABLE - Disable bypass mode (for normal operations). - 0 - - - ENABLE - Activate LDO bypass. - 0x1 - - - - - HIGHZ - . - 2 - 1 - read-write - - - NORMALMPEDANCE - Output in High normal state. - 0 - - - HIGHIMPEDANCE - Output in High Impedance state. - 0x1 - - - - - VOUT - Sets the LDO output level. - 3 - 3 - read-write - - - V_0P750 - 0.750 V. - 0 - - - V_0P775 - 0.775 V. - 0x1 - - - V_0P800 - 0.800 V. - 0x2 - - - V_0P825 - 0.825 V. - 0x3 - - - V_0P850 - 0.850 V. - 0x4 - - - V_0P875 - 0.875 V. - 0x5 - - - V_0P900 - 0.900 V. - 0x6 - - - V_0P925 - 0.925 V. - 0x7 - - - - - IBIAS - Adjust the biasing current. - 6 - 2 - read-write - - - STABMODE - Stability configuration. - 8 - 2 - read-write - - - - - AUX_BIAS - AUX_BIAS - 0xB4 - 32 - read-write - 0x703A0 - 0x3FFFFE - - - VREF1VENABLE - Control output of 1V reference voltage. - 1 - 1 - read-write - - - DISABLE - Output of 1V reference voltage buffer is bypassed. - 0 - - - ENABLE - Output of 1V reference voltage is enabled. - 0x1 - - - - - ITRIM - current trimming control word. - 2 - 5 - read-write - - - PTATITRIM - current trimming control word for ptat current. - 7 - 5 - read-write - - - VREF1VTRIM - voltage trimming control word. - 12 - 5 - read-write - - - VREF1VCURVETRIM - Control bit to configure trimming state of mirror. - 17 - 3 - read-write - - - ITRIMCTRL0 - Control bit to configure trimming state of mirror. - 20 - 1 - read-write - - - ITRIMCTRL1 - Control bit to configure trimming state of mirror. - 21 - 1 - read-write - - - - - USBHS_PHY_CTRL - USB High Speed Phy Control - 0x100 - 32 - read-write - 0x8 - 0xF - - - usb_vbusvalid_ext - Override value for Vbus if using external detectors. - 0 - 1 - read-write - - - usb_id_ext - Override value for ID if using external detectors. - 1 - 1 - read-write - - - - - USBHS_PHY_TRIM - USB High Speed Phy Trim values - 0x104 - 32 - read-write - 0 - 0xFFFFFF - - - trim_usb_reg_env_tail_adj_vd - Adjusts time constant of HS RX squelch (envelope) comparator. - 0 - 2 - read-write - - - trim_usbphy_tx_d_cal - . - 2 - 4 - read-write - - - trim_usbphy_tx_cal45dp - . - 6 - 5 - read-write - - - trim_usbphy_tx_cal45dm - . - 11 - 5 - read-write - - - trim_usb2_refbias_tst - . - 16 - 2 - read-write - - - trim_usb2_refbias_vbgadj - . - 18 - 3 - read-write - - - trim_pll_ctrl0_div_sel - . - 21 - 3 - read-write - - - - - - - PMC - PMC - PMC - 0x40020000 - - 0 - 0xD8 - registers - - - ACMP - 24 - - - - STATUS - Power Management Controller FSM (Finite State Machines) status - 0x4 - 32 - read-only - 0 - 0xF00FFFFF - - - BOOTMODE - Latest IC Boot cause:. - 18 - 2 - read-only - - - POWERUP - Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset). - 0 - - - DEEPSLEEP - Latest IC boot was from DEEP SLEEP low power mode. - 0x1 - - - POWERDOWN - Latest IC boot was from POWER DOWN low power mode. - 0x2 - - - DEEPPOWERDOWN - Latest IC boot was from DEEP POWER DOWN low power mode. - 0x3 - - - - - - - RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x8 - 32 - read-write - 0 - 0xF - - - DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). - 0 - 1 - read-write - - - DISABLE - Reset event from DEEP POWER DOWN mode is disable. - 0 - - - ENABLE - Reset event from DEEP POWER DOWN mode is enable. - 0x1 - - - - - BODVBATRESETENABLE - BOD VBAT reset enable. - 1 - 1 - read-write - - - DISABLE - BOD VBAT reset is disable. - 0 - - - ENABLE - BOD VBAT reset is enable. - 0x1 - - - - - BODCORERESETENABLE - BOD CORE reset enable. - 2 - 1 - read-write - - - DISABLE - BOD CORE reset is disable. - 0 - - - ENABLE - BOD CORE reset is enable. - 0x1 - - - - - SWRRESETENABLE - Software reset enable. - 3 - 1 - read-write - - - DISABLE - Software reset is disable. - 0 - - - ENABLE - Software reset is enable. - 0x1 - - - - - - - DCDC0 - DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x10 - 32 - read-write - 0x10C4E68 - 0x7FFFFFF - - - RC - Constant On-Time calibration. - 0 - 6 - read-write - - - ICOMP - Select the type of ZCD comparator. - 6 - 2 - read-write - - - ISEL - Alter Internal biasing currents. - 8 - 2 - read-write - - - ICENABLE - Selection of auto scaling of COT period with variations in VDD. - 10 - 1 - read-write - - - TMOS - One-shot generator reference current trimming signal. - 11 - 5 - read-write - - - DISABLEISENSE - Disable Current sensing. - 16 - 1 - read-write - - - VOUT - Set output regulation voltage. - 17 - 4 - read-write - - - V_DCDC_0P950 - 0.95 V. - 0 - - - V_DCDC_0P975 - 0.975 V. - 0x1 - - - V_DCDC_1P000 - 1 V. - 0x2 - - - V_DCDC_1P025 - 1.025 V. - 0x3 - - - V_DCDC_1P050 - 1.05 V. - 0x4 - - - V_DCDC_1P075 - 1.075 V. - 0x5 - - - V_DCDC_1P100 - 1.1 V. - 0x6 - - - V_DCDC_1P125 - 1.125 V. - 0x7 - - - V_DCDC_1P150 - 1.15 V. - 0x8 - - - V_DCDC_1P175 - 1.175 V. - 0x9 - - - V_DCDC_1P200 - 1.2 V. - 0xA - - - - - SLICINGENABLE - Enable staggered switching of power switches. - 21 - 1 - read-write - - - INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. - 22 - 1 - read-write - - - VOUT_PWD - Set output regulation voltage during Deep Sleep. - 23 - 4 - read-write - - - - - DCDC1 - DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x14 - 32 - read-write - 0x1803A98 - 0xFFFFFFFF - - - RTRIMOFFET - Adjust the offset voltage of BJT based comparator. - 0 - 4 - read-write - - - RSENSETRIM - Adjust Max inductor peak current limiting. - 4 - 4 - read-write - - - DTESTENABLE - Enable Digital test signals. - 8 - 1 - read-write - - - SETCURVE - Bandgap calibration parameter. - 9 - 2 - read-write - - - SETDC - Bandgap calibration parameter. - 11 - 4 - read-write - - - DTESTSEL - Select the output signal for test. - 15 - 3 - read-write - - - ISCALEENABLE - Modify COT behavior. - 18 - 1 - read-write - - - FORCEBYPASS - Force bypass mode. - 19 - 1 - read-write - - - TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. - 20 - 4 - read-write - - - FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. - 24 - 1 - read-write - - - LCENABLE - Change the range of the peak detector of current inside the inductor. - 25 - 1 - read-write - - - TOFF - Constant Off-Time calibration input. - 26 - 5 - read-write - - - TOFFENABLE - Enable Constant Off-Time feature. - 31 - 1 - read-write - - - - - LDOPMU - Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x1C - 32 - read-write - 0x10EF718 - 0x31FFFFF - - - VADJ - Sets the Always-On domain LDO output level. - 0 - 5 - read-write - - - V_1P220 - 1.22 V. - 0 - - - V_0P700 - 0.7 V. - 0x1 - - - V_0P725 - 0.725 V. - 0x2 - - - V_0P750 - 0.75 V. - 0x3 - - - V_0P775 - 0.775 V. - 0x4 - - - V_0P800 - 0.8 V. - 0x5 - - - V_0P825 - 0.825 V. - 0x6 - - - V_0P850 - 0.85 V. - 0x7 - - - V_0P875 - 0.875 V. - 0x8 - - - V_0P900 - 0.9 V. - 0x9 - - - V_0P960 - 0.96 V. - 0xA - - - V_0P970 - 0.97 V. - 0xB - - - V_0P980 - 0.98 V. - 0xC - - - V_0P990 - 0.99 V. - 0xD - - - V_1P000 - 1 V. - 0xE - - - V_1P010 - 1.01 V. - 0xF - - - V_1P020 - 1.02 V. - 0x10 - - - V_1P030 - 1.03 V. - 0x11 - - - V_1P040 - 1.04 V. - 0x12 - - - V_1P050 - 1.05 V. - 0x13 - - - V_1P060 - 1.06 V. - 0x14 - - - V_1P070 - 1.07 V. - 0x15 - - - V_1P080 - 1.08 V. - 0x16 - - - V_1P090 - 1.09 V. - 0x17 - - - V_1P100 - 1.1 V. - 0x18 - - - V_1P110 - 1.11 V. - 0x19 - - - V_1P120 - 1.12 V. - 0x1A - - - V_1P130 - 1.13 V. - 0x1B - - - V_1P140 - 1.14 V. - 0x1C - - - V_1P150 - 1.15 V. - 0x1D - - - V_1P160 - 1.16 V. - 0x1E - - - V_1P220_1 - 1.22 V. - 0x1F - - - - - VADJ_PWD - Sets the Always-On domain LDO output level in all power down modes. - 5 - 5 - read-write - - - VADJ_BOOST - Sets the Always-On domain LDO Boost output level. - 10 - 5 - read-write - - - VADJ_BOOST_PWD - Sets the Always-On domain LDO Boost output level in all power down modes. - 15 - 5 - read-write - - - BOOST_ENA - Control the LDO AO boost mode in ACTIVE mode. - 24 - 1 - read-write - - - DISABLE - LDO AO Boost Mode is disable. - 0 - - - ENABLE - LDO AO Boost Mode is enable. - 0x1 - - - - - BOOST_ENA_PWD - Control the LDO AO boost mode in the different low power modes (DEEP SLEEP, POWERDOWN, and DEEP POWER DOWN). - 25 - 1 - read-write - - - DISABLE - LDO AO Boost Mode is disable. - 0 - - - ENABLE - LDO AO Boost Mode is enable. - 0x1 - - - - - - - BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] - 0x30 - 32 - read-write - 0x47 - 0x7F - - - TRIGLVL - BoD trigger level. - 0 - 5 - read-write - - - V_1P00 - 1.00 V. - 0 - - - V_1P10 - 1.10 V. - 0x1 - - - V_1P20 - 1.20 V. - 0x2 - - - V_1P30 - 1.30 V. - 0x3 - - - V_1P40 - 1.40 V. - 0x4 - - - V_1P50 - 1.50 V. - 0x5 - - - V_1P60 - 1.60 V. - 0x6 - - - V_1P65 - 1.65 V. - 0x7 - - - V_1P70 - 1.70 V. - 0x8 - - - V_1P75 - 1.75 V. - 0x9 - - - V_1P80 - 1.80 V. - 0xA - - - V_1P90 - 1.90 V. - 0xB - - - V_2P00 - 2.00 V. - 0xC - - - V_2P10 - 2.10 V. - 0xD - - - V_2P20 - 2.20 V. - 0xE - - - V_2P30 - 2.30 V. - 0xF - - - V_2P40 - 2.40 V. - 0x10 - - - V_2P50 - 2.50 V. - 0x11 - - - V_2P60 - 2.60 V. - 0x12 - - - V_2P70 - 2.70 V. - 0x13 - - - V_2P80 - 2.806 V. - 0x14 - - - V_2P90 - 2.90 V. - 0x15 - - - V_3P00 - 3.00 V. - 0x16 - - - V_3P10 - 3.10 V. - 0x17 - - - V_3P20 - 3.20 V. - 0x18 - - - V_3P30_2 - 3.30 V. - 0x19 - - - V_3P30_3 - 3.30 V. - 0x1A - - - V_3P30_4 - 3.30 V. - 0x1B - - - V_3P30_5 - 3.30 V. - 0x1C - - - V_3P30_6 - 3.30 V. - 0x1D - - - V_3P30_7 - 3.30 V. - 0x1E - - - V_3P30_8 - 3.30 V. - 0x1F - - - - - HYST - BoD Hysteresis control. - 5 - 2 - read-write - - - HYST_25MV - 25 mV. - 0 - - - HYST_50MV - 50 mV. - 0x1 - - - HYST_75MV - 75 mV. - 0x2 - - - HYST_100MV - 100 mV. - 0x3 - - - - - - - REFFASTWKUP - Analog References fast wake-up Control register [Reset by: PoR] - 0x40 - 32 - read-write - 0x1 - 0x3 - - - LPWKUP - Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP POWER DOWN): . - 0 - 1 - read-write - - - DISABLE - Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode. - 0 - - - ENABLE - Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode. - 0x1 - - - - - HWWKUP - Analog References fast wake-up in case of Hardware Pin reset: . - 1 - 1 - read-write - - - DISABLE - Analog References fast wake-up feature is disabled in case of Hardware Pin reset. - 0 - - - ENABLE - Analog References fast wake-up feature is enabled in case of Hardware Pin reset. - 0x1 - - - - - - - XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] - 0x4C - 32 - read-write - 0x204052 - 0x3FFFFFE - - - IREF - reference output current selection inputs. - 1 - 2 - read-write - - - TEST - Oscillator Test Mode. - 3 - 1 - read-write - - - IBIAS - bias current selection inputs. - 4 - 2 - read-write - - - AMPL - oscillator amplitude selection inputs. - 6 - 2 - read-write - - - CAPBANKIN - Capa bank setting input. - 8 - 7 - read-write - - - CAPBANKOUT - Capa bank setting output. - 15 - 7 - read-write - - - CAPTESTSTARTSRCSEL - Source selection for xo32k_captest_start_ao_set. - 22 - 1 - read-write - - - CAPSTART - Sourced from CAPTESTSTART. - 0 - - - CALIB - Sourced from calibration. - 0x1 - - - - - CAPTESTSTART - Start test. - 23 - 1 - read-write - - - CAPTESTENABLE - Enable signal for cap test. - 24 - 1 - read-write - - - CAPTESTOSCINSEL - Select the input for test. - 25 - 1 - read-write - - - OSCOUT - Oscillator output pin (osc_out). - 0 - - - OSCIN - Oscillator input pin (osc_in). - 0x1 - - - - - - - COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x50 - 32 - read-write - 0xA - 0xFF7FFE - - - HYST - Hysteris when hyst = '1'. - 1 - 1 - read-write - - - DISABLE - Hysteresis is disable. - 0 - - - ENABLE - Hysteresis is enable. - 0x1 - - - - - VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). - 2 - 1 - read-write - - - INTERNALREF - Select internal VREF. - 0 - - - VDDA - Select VDDA. - 0x1 - - - - - LOWPOWER - Low power mode. - 3 - 1 - read-write - - - HIGHSPEED - High speed mode. - 0 - - - LOWSPEED - Low power mode (Low speed). - 0x1 - - - - - PMUX - Control word for P multiplexer:. - 4 - 3 - read-write - - - VREF - VREF (See fiedl VREFINPUT). - 0 - - - CMP0_A - Pin P0_0. - 0x1 - - - CMP0_B - Pin P0_9. - 0x2 - - - CMP0_C - Pin P0_18. - 0x3 - - - CMP0_D - Pin P1_14. - 0x4 - - - CMP0_E - Pin P2_23. - 0x5 - - - - - NMUX - Control word for N multiplexer:. - 7 - 3 - read-write - - - VREF - VREF (See field VREFINPUT). - 0 - - - CMP0_A - Pin P0_0. - 0x1 - - - CMP0_B - Pin P0_9. - 0x2 - - - CMP0_C - Pin P0_18. - 0x3 - - - CMP0_D - Pin P1_14. - 0x4 - - - CMP0_E - Pin P2_23. - 0x5 - - - - - VREF - Control reference voltage step, per steps of (VREFINPUT/31). - 10 - 5 - read-write - - - FILTERCGF_SAMPLEMODE - Control the filtering of the Analog Comparator output. - 16 - 2 - read-write - - - BYPASS - Bypass mode. - 0 - - - FILTER1CLK - Filter 1 clock period. - 0x1 - - - FILTER2CLK - Filter 2 clock period. - 0x2 - - - FILTER3CLK - Filter 3 clock period. - 0x3 - - - - - FILTERCGF_CLKDIV - Filter Clock divider. - 18 - 3 - read-write - - - FILTER_1CLK_PERIOD - Filter clock period duration equals 1 Analog Comparator clock period. - 0 - - - FILTER_2CLK_PERIOD - Filter clock period duration equals 2 Analog Comparator clock period. - 0x1 - - - FILTER_4CLK_PERIOD - Filter clock period duration equals 4 Analog Comparator clock period. - 0x2 - - - FILTER_8CLK_PERIOD - Filter clock period duration equals 8 Analog Comparator clock period. - 0x3 - - - FILTER_16CLK_PERIOD - Filter clock period duration equals 16 Analog Comparator clock period. - 0x4 - - - FILTER_32CLK_PERIOD - Filter clock period duration equals 32 Analog Comparator clock period. - 0x5 - - - FILTER_64CLK_PERIOD - Filter clock period duration equals 64 Analog Comparator clock period. - 0x6 - - - FILTER_128CLK_PERIOD - Filter clock period duration equals 128 Analog Comparator clock period. - 0x7 - - - - - - - WAKEUPIOCTRL - Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] - 0x64 - 32 - read-write - 0 - 0xFF - - - RISINGEDGEWAKEUP0 - Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:. - 0 - 1 - read-write - - - DISABLE - Rising edge detection is disable. - 0 - - - ENABLE - Rising edge detection is enable. - 0x1 - - - - - FALLINGEDGEWAKEUP0 - Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:. - 1 - 1 - read-write - - - DISABLE - Falling edge detection is disable. - 0 - - - ENABLE - Falling edge detection is enable. - 0x1 - - - - - RISINGEDGEWAKEUP1 - Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:. - 2 - 1 - read-write - - - DISABLE - Rising edge detection is disable. - 0 - - - ENABLE - Rising edge detection is enable. - 0x1 - - - - - FALLINGEDGEWAKEUP1 - Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:. - 3 - 1 - read-write - - - DISABLE - Falling edge detection is disable. - 0 - - - ENABLE - Falling edge detection is enable. - 0x1 - - - - - RISINGEDGEWAKEUP2 - Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:. - 4 - 1 - read-write - - - DISABLE - Rising edge detection is disable. - 0 - - - ENABLE - Rising edge detection is enable. - 0x1 - - - - - FALLINGEDGEWAKEUP2 - Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:. - 5 - 1 - read-write - - - DISABLE - Falling edge detection is disable. - 0 - - - ENABLE - Falling edge detection is enable. - 0x1 - - - - - RISINGEDGEWAKEUP3 - Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes:. - 6 - 1 - read-write - - - DISABLE - Rising edge detection is disable. - 0 - - - ENABLE - Rising edge detection is enable. - 0x1 - - - - - FALLINGEDGEWAKEUP3 - Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes:. - 7 - 1 - read-write - - - DISABLE - Falling edge detection is disable. - 0 - - - ENABLE - Falling edge detection is enable. - 0x1 - - - - - MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode - 8 - 1 - read-write - - - MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode - 9 - 1 - read-write - - - MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode - 10 - 1 - read-write - - - MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode - 11 - 1 - read-write - - - - - WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode - 0x68 - 32 - read-write - 0 - 0xF - - - WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. - 0 - 1 - read-only - - - NOEVENT - Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. - 0 - - - EVENT - Last wake up from Deep Power down mode was triggred by wake up I/O 0. - 0x1 - - - - - WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. - 1 - 1 - read-write - - - NOEVENT - Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. - 0 - - - EVENT - Last wake up from Deep Power down mode was triggred by wake up I/O 1. - 0x1 - - - - - WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. - 2 - 1 - read-write - - - NOEVENT - Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. - 0 - - - EVENT - Last wake up from Deep Power down mode was triggred by wake up I/O 2. - 0x1 - - - - - WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. - 3 - 1 - read-write - - - NOEVENT - Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. - 0 - - - EVENT - Last wake up from Deep Power down mode was triggred by wake up I/O 3. - 0x1 - - - - - - - STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] - 0x74 - 32 - read-write - 0x6 - 0x7 - - - XTAL32KOK - XTAL oscillator 32 K OK signal. - 0 - 1 - read-only - - - XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. - 2 - 1 - read-write - - - NOFAIL - No oscillation failure has been detetced since the last time this bit has been cleared. - 0 - - - FAILURE - At least one oscillation failure has been detetced since the last time this bit has been cleared. - 0x1 - - - - - - - AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] - 0x84 - 32 - read-write - 0 - 0xFFFFFFFF - - - POR - The last chip reset was caused by a Power On Reset. - 4 - 1 - read-write - - - PADRESET - The last chip reset was caused by a Pin Reset. - 5 - 1 - read-write - - - BODRESET - The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. - 6 - 1 - read-write - - - SYSTEMRESET - The last chip reset was caused by a System Reset requested by the ARM CPU. - 7 - 1 - read-write - - - WDTRESET - The last chip reset was caused by the Watchdog Timer. - 8 - 1 - read-write - - - SWRRESET - The last chip reset was caused by a Software event. - 9 - 1 - read-write - - - DPDRESET_WAKEUPIO - The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode. - 10 - 1 - read-write - - - DPDRESET_RTC - The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode. - 11 - 1 - read-write - - - DPDRESET_OSTIMER - The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode. - 12 - 1 - read-write - - - BOOTERRORCOUNTER - ROM Boot Fatal Error Counter. - 16 - 4 - read-write - - - - - MISCCTRL - Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x90 - 32 - read-write - 0 - 0xFFFF - - - LDODEEPSLEEPREF - Select LDO Deep Sleep reference source. - 0 - 1 - read-write - - - FLASHBUFFER - LDO DEEP Sleep uses Flash buffer biasing as reference. - 0 - - - BGP0P8V - LDO DEEP Sleep uses Band Gap 0.8V as reference. - 0x1 - - - - - LDOMEMHIGHZMODE - Control the activation of LDO MEM High Z mode. - 1 - 1 - read-write - - - DISABLE - LDO MEM High Z mode is disabled. - 0 - - - ENABLE - LDO MEM High Z mode is enabled. - 0x1 - - - - - LOWPWR_FLASH_BUF - no description available - 2 - 1 - read-write - - - MISCCTRL_3_8 - Reserved. - 3 - 5 - read-write - - - MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode - 8 - 1 - read-write - - - MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode - 9 - 1 - read-write - - - MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode - 10 - 1 - read-write - - - MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode - 11 - 1 - read-write - - - DISABLE_BLEED - Controls LDO MEM bleed current. This field is expected to be controlled by the Low Power Software only in DEEP SLEEP low power mode. - 12 - 1 - read-write - - - BLEED_ENABLE - LDO_MEM bleed current is enabled. - 0 - - - BLEED_DISABLE - LDO_MEM bleed current is disabled. Should be set before entering in Deep Sleep low power mode and cleared after wake up from Deep SLeep low power mode. - 0x1 - - - - - MISCCTRL_13_14 - Reserved. - 13 - 2 - read-write - - - WAKUPIO_RST - WAKEUP IO event detector reset control. - 15 - 1 - read-write - - - RELEASED - Wakeup IO is not reset. - 0 - - - ASSERTED - Wakeup IO is reset. - 0x1 - - - - - - - RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] - 0x98 - 32 - read-write - 0x3FF0008 - 0xC7FF800F - - - SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . - 0 - 1 - read-write - - - FRO32K - FRO 32 KHz. - 0 - - - XTAL32K - XTAL 32KHz. - 0x1 - - - - - CLK1KHZDIV - Actual division ratio is : 28 + CLK1KHZDIV. - 1 - 3 - read-write - - - CLK1KHZDIVUPDATEREQ - RTC 1KHz clock Divider status flag. - 15 - 1 - read-write - - - CLK1HZDIV - Actual division ratio is : 31744 + CLK1HZDIV. - 16 - 11 - read-write - - - CLK1HZDIVHALT - Halts the divider counter. - 30 - 1 - read-write - - - CLK1HZDIVUPDATEREQ - RTC 1Hz Divider status flag. - 31 - 1 - read-write - - - - - OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] - 0x9C - 32 - read-write - 0x8 - 0xF - - - SOFTRESET - Active high reset. - 0 - 1 - read-write - - - CLOCKENABLE - Enable OSTIMER 32 KHz clock. - 1 - 1 - read-write - - - DPDWAKEUPENABLE - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode). - 2 - 1 - read-write - - - OSC32KPD - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K. - 3 - 1 - read-write - - - - - PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0xB8 - 32 - read-write - 0xDEFFC4 - 0xFFFFEF - - - PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD). - 3 - 1 - read-write - - - POWEREDON - BOD VBAT is powered. - 0 - - - POWEREDOFF - BOD VBAT is powered down. - 0x1 - - - - - PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. - 6 - 1 - read-write - - - POWEREDON - FRO32KHz is powered. - 0 - - - POWEREDOFF - FRO32KHz is powered down. - 0x1 - - - - - PDEN_XTAL32K - Controls power to crystal 32 KHz. - 7 - 1 - read-write - - - POWEREDON - Crystal 32KHz is powered. - 0 - - - POWEREDOFF - Crystal 32KHz is powered down. - 0x1 - - - - - PDEN_XTAL32M - Controls power to high speed crystal. - 8 - 1 - read-write - - - POWEREDON - High speed crystal is powered. - 0 - - - POWEREDOFF - High speed crystal is powered down. - 0x1 - - - - - PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). - 9 - 1 - read-write - - - POWEREDON - PLL0 is powered. - 0 - - - POWEREDOFF - PLL0 is powered down. - 0x1 - - - - - PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1). - 10 - 1 - read-write - - - POWEREDON - PLL1 is powered. - 0 - - - POWEREDOFF - PLL1 is powered down. - 0x1 - - - - - PDEN_USBFSPHY - Controls power to USB Full Speed phy. - 11 - 1 - read-write - - - POWEREDON - USB Full Speed phy is powered. - 0 - - - POWEREDOFF - USB Full Speed phy is powered down. - 0x1 - - - - - PDEN_USBHSPHY - Controls power to USB High Speed Phy. - 12 - 1 - read-write - - - POWEREDON - USB HS phy is powered. - 0 - - - POWEREDOFF - USB HS phy is powered down. - 0x1 - - - - - PDEN_COMP - Controls power to Analog Comparator. - 13 - 1 - read-write - - - POWEREDON - Analog Comparator is powered. - 0 - - - POWEREDOFF - Analog Comparator is powered down. - 0x1 - - - - - PDEN_LDOUSBHS - Controls power to USB high speed LDO. - 18 - 1 - read-write - - - POWEREDON - USB high speed LDO is powered. - 0 - - - POWEREDOFF - USB high speed LDO is powered down. - 0x1 - - - - - PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS) - 19 - 1 - read-write - - - POWEREDON - auxiliary biasing is powered. - 0 - - - POWEREDOFF - auxiliary biasing is powered down. - 0x1 - - - - - PDEN_LDOXO32M - Controls power to high speed crystal LDO. - 20 - 1 - read-write - - - POWEREDON - High speed crystal LDO is powered. - 0 - - - POWEREDOFF - High speed crystal LDO is powered down. - 0x1 - - - - - PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources. - 22 - 1 - read-write - - - POWEREDON - TRNG clocks are powered. - 0 - - - POWEREDOFF - TRNG clocks are powered down. - 0x1 - - - - - PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. - 23 - 1 - read-write - - - POWEREDON - PLL0 Sread spectrum module is powered. - 0 - - - POWEREDOFF - PLL0 Sread spectrum module is powered down. - 0x1 - - - - - - - PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0xC0 - 32 - write-only - 0 - 0xFFFFFFFF - - - PDRUNCFGSET0 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. - 0 - 32 - write-only - - - - - PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0xC8 - 32 - write-only - 0 - 0xFFFFFFFF - - - PDRUNCFGCLR0 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. - 0 - 32 - write-only - - - - - SRAMCTRL - All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] - 0xD4 - 32 - read-write - 0x1 - 0x1FF - - - SMB - Source Biasing voltage. - 0 - 2 - read-write - - - LOW - Low leakage. - 0 - - - MEDIUM - Medium leakage. - 0x1 - - - HIGHEST - Highest leakage. - 0x2 - - - DISABLE - Disable. - 0x3 - - - - - RM - Read Margin control settings. - 2 - 3 - read-write - - - WM - Write Margin control settings. - 5 - 3 - read-write - - - WRME - Write read margin enable. - 8 - 1 - read-write - - - - - - - SYSCTL - system controller - SYSCTL - 0x40023000 - - 0 - 0x104 - registers - - - - UPDATELCKOUT - update lock out control - 0 - 32 - read-write - 0 - 0x1 - - - UPDATELCKOUT - All Registers - 0 - 1 - read-write - - - NORMAL_MODE - Normal Mode. Can be written to. - 0 - - - PROTECTED_MODE - Protected Mode. Cannot be written to. - 0x1 - - - - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - FCCTRLSEL%s - Selects the source for SCK going into Flexcomm index - 0x40 - 32 - read-write - 0 - 0x3030303 - - - SCKINSEL - Selects the source for SCK going into this Flexcomm. - 0 - 2 - read-writeOnce - - - ORIG_FLEX_I2S_SIGNALS - Selects the dedicated FCn_SCK function for this Flexcomm. - 0 - - - SHARED_SET0_I2S_SIGNALS - SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - 0x1 - - - SHARED_SET1_I2S_SIGNALS - SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - 0x2 - - - - - WSINSEL - Selects the source for WS going into this Flexcomm. - 8 - 2 - read-write - - - ORIG_FLEX_I2S_SIGNALS - Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. - 0 - - - SHARED_SET0_I2S_SIGNALS - WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - 0x1 - - - SHARED_SET1_I2S_SIGNALS - WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - 0x2 - - - - - DATAINSEL - Selects the source for DATA input to this Flexcomm. - 16 - 2 - read-write - - - ORIG_FLEX_I2S_SIGNALS - Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. - 0 - - - SHARED_SET0_I2S_SIGNALS - Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - 0x1 - - - SHARED_SET1_I2S_SIGNALS - Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - 0x2 - - - - - DATAOUTSEL - Selects the source for DATA output from this Flexcomm. - 24 - 2 - read-write - - - ORIG_FLEX_I2S_SIGNALS - Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. - 0 - - - SHARED_SET0_I2S_SIGNALS - Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - 0x1 - - - SHARED_SET1_I2S_SIGNALS - Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - 0x2 - - - - - - - 2 - 0x4 - 0,1 - SHAREDCTRLSET%s - Selects sources and data combinations for shared signal set index. - 0x80 - 32 - read-write - 0 - 0xFF0777 - - - SHAREDSCKSEL - Selects the source for SCK of this shared signal set. - 0 - 3 - read-write - - - FLEXCOMM0 - SCK for this shared signal set comes from Flexcomm 0. - 0 - - - FLEXCOMM1 - SCK for this shared signal set comes from Flexcomm 1. - 0x1 - - - FLEXCOMM2 - SCK for this shared signal set comes from Flexcomm 2. - 0x2 - - - FLEXCOMM3 - SCK for this shared signal set comes from Flexcomm 3. - 0x3 - - - FLEXCOMM4 - SCK for this shared signal set comes from Flexcomm 4. - 0x4 - - - FLEXCOMM5 - SCK for this shared signal set comes from Flexcomm 5. - 0x5 - - - FLEXCOMM6 - SCK for this shared signal set comes from Flexcomm 6. - 0x6 - - - FLEXCOMM7 - SCK for this shared signal set comes from Flexcomm 7. - 0x7 - - - - - SHAREDWSSEL - Selects the source for WS of this shared signal set. - 4 - 3 - read-write - - - FLEXCOMM0 - WS for this shared signal set comes from Flexcomm 0. - 0 - - - FLEXCOMM1 - WS for this shared signal set comes from Flexcomm 1. - 0x1 - - - FLEXCOMM2 - WS for this shared signal set comes from Flexcomm 2. - 0x2 - - - FLEXCOMM3 - WS for this shared signal set comes from Flexcomm 3. - 0x3 - - - FLEXCOMM4 - WS for this shared signal set comes from Flexcomm 4. - 0x4 - - - FLEXCOMM5 - WS for this shared signal set comes from Flexcomm 5. - 0x5 - - - FLEXCOMM6 - WS for this shared signal set comes from Flexcomm 6. - 0x6 - - - FLEXCOMM7 - WS for this shared signal set comes from Flexcomm 7. - 0x7 - - - - - SHAREDDATASEL - Selects the source for DATA input for this shared signal set. - 8 - 3 - read-write - - - FLEXCOMM0 - DATA input for this shared signal set comes from Flexcomm 0. - 0 - - - FLEXCOMM1 - DATA input for this shared signal set comes from Flexcomm 1. - 0x1 - - - FLEXCOMM2 - DATA input for this shared signal set comes from Flexcomm 2. - 0x2 - - - FLEXCOMM3 - DATA input for this shared signal set comes from Flexcomm 3. - 0x3 - - - FLEXCOMM4 - DATA input for this shared signal set comes from Flexcomm 4. - 0x4 - - - FLEXCOMM5 - DATA input for this shared signal set comes from Flexcomm 5. - 0x5 - - - FLEXCOMM6 - DATA input for this shared signal set comes from Flexcomm 6. - 0x6 - - - FLEXCOMM7 - DATA input for this shared signal set comes from Flexcomm 7. - 0x7 - - - - - FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set. - 16 - 1 - read-write - - - INPUT - Data output from FC0 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC0 does contribute to this shared set. - 0x1 - - - - - FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set. - 17 - 1 - read-write - - - INPUT - Data output from FC1 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC1 does contribute to this shared set. - 0x1 - - - - - FC2DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. - 18 - 1 - read-write - - - INPUT - Data output from FC2 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC2 does contribute to this shared set. - 0x1 - - - - - FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set. - 20 - 1 - read-write - - - INPUT - Data output from FC4 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC4 does contribute to this shared set. - 0x1 - - - - - FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set. - 21 - 1 - read-write - - - INPUT - Data output from FC5 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC5 does contribute to this shared set. - 0x1 - - - - - FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set. - 22 - 1 - read-write - - - INPUT - Data output from FC6 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC6 does contribute to this shared set. - 0x1 - - - - - FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set. - 23 - 1 - read-write - - - INPUT - Data output from FC7 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC7 does contribute to this shared set. - 0x1 - - - - - - - USB_HS_STATUS - Status register for USB HS - 0x100 - 32 - read-only - 0 - 0x1C0FF00 - - - USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply. - 0 - 1 - read-only - - - SUPPLY_3V_OK - 3v3 supply is good. - 0 - - - SUPPLY_3V_LOW - 3v3 supply is too low. - 0x1 - - - - - - - - - RTC - Real-Time Clock (RTC) - RTC - 0x4002C000 - - 0 - 0x60 - registers - - - RTC - 29 - - - - CTRL - RTC control register - 0 - 32 - read-write - 0x1 - 0x7FD - - - SWRESET - Software reset control - 0 - 1 - read-write - - - NOT_IN_RESET - Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. - 0 - - - IN_RESET - In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared. - 0x1 - - - - - ALARM1HZ - RTC 1 Hz timer alarm flag status. - 2 - 1 - read-write - - - NO_MATCH - No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. - 0 - - - MATCH - Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. - 0x1 - - - - - WAKE1KHZ - RTC 1 kHz timer wake-up flag status. - 3 - 1 - read-write - - - RUN - Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. - 0 - - - TIMEOUT - Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. - 0x1 - - - - - ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. - 4 - 1 - read-write - - - DISABLE - Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. - 0 - - - ENABLE - Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. - 0x1 - - - - - WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. - 5 - 1 - read-write - - - DISABLE - Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - 0 - - - ENABLE - Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. - 0x1 - - - - - RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). - 6 - 1 - read-write - - - DISABLE - Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - 0 - - - ENABLE - Enable. The 1 kHz RTC timer is enabled. - 0x1 - - - - - RTC_EN - RTC enable. - 7 - 1 - read-write - - - DISABLE - Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register. - 0 - - - ENABLE - Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register. - 0x1 - - - - - RTC_OSC_PD - RTC oscillator power-down control. - 8 - 1 - read-write - - - POWER_UP - See RTC_OSC_BYPASS - 0 - - - POWERED_DOWN - RTC oscillator is powered-down. - 0x1 - - - - - RTC_OSC_BYPASS - RTC oscillator bypass control. - 9 - 1 - read-write - - - USED - The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. - 0 - - - BYPASS - The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. - 0x1 - - - - - RTC_SUBSEC_ENA - RTC Sub-second counter control. - 10 - 1 - read-write - - - POWER_UP - The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second counter, this bit will always read-back as a '0'. - 0 - - - POWERED_DOWN - The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip exits deep power-down mode. - 0x1 - - - - - - - MATCH - RTC match register - 0x4 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. - 0 - 32 - read-write - - - - - COUNT - RTC counter register - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after the RTC_EN bit is set. - 0 - 32 - read-write - - - - - WAKE - High-resolution/wake-up timer control register - 0xC - 32 - read-write - 0 - 0xFFFF - - - VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence. Do not write to this register while counting is in progress. - 0 - 16 - read-write - - - - - SUBSEC - Sub-second counter register - 0x10 - 32 - read-write - 0 - 0xFFFF - - - SUBSEC - A read reflects the current value of the 32KHz sub-second counter. This counter is cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This counter must be re-enabled after exiting deep power-down mode or after the main RTC module is disabled and re-enabled. On modules not equipped with a sub-second counter, this register will read-back as all zeroes. - 0 - 15 - read-only - - - - - 8 - 0x4 - GPREG[%s] - General Purpose register - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied. - 0 - 32 - read-write - - - - - - - OSTIMER - Synchronous OS/Event timer with Wakeup Timer - OSTIMER - 0x4002D000 - - 0 - 0x20 - registers - - - OS_EVENT - 38 - - - - EVTIMERL - EVTIMER Low Register - 0 - 32 - read-only - 0 - 0xFFFFFFFF - - - EVTIMER_COUNT_VALUE - A read reflects the current value of the lower 32 bits of the 42-bits EVTIMER. Note: There is only one EVTIMER, readable from all domains. - 0 - 32 - read-only - - - - - EVTIMERH - EVTIMER High Register - 0x4 - 32 - read-write - 0 - 0xFFFFFFFF - - - EVTIMER_COUNT_VALUE - A read reflects the current value of the upper 10 bits of the 42-bits EVTIMER. Note there is only one EVTIMER, readable from all domains. - 0 - 10 - read-only - - - - - CAPTURE_L - Capture Low Register - 0x8 - 32 - read-only - 0 - 0xFFFFFFFF - - - CAPTURE_VALUE - A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). - 0 - 32 - read-only - - - - - CAPTURE_H - Capture High Register - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPTURE_VALUE - A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). - 0 - 10 - read-only - - - - - MATCH_L - Match Low Register - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCH_VALUE - The value written to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. - 0 - 32 - read-write - - - - - MATCH_H - Match High Register - 0x14 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCH_VALUE - The value written (upper 10 bits) to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. - 0 - 10 - read-write - - - - - OSEVENT_CTRL - OS_EVENT TIMER Control Register - 0x1C - 32 - read-write - 0 - 0x7 - - - OSTIMER_INTRFLAG - This bit is set when a match occurs between the central 42-bits EVTIMER and the value programmed in the match-register pair. This bit is cleared by writing a '1'. Writes to clear this bit are asynchronous. It should be done before a new match value is written into the MATCH_L/H registers. - 0 - 1 - read-write - - - OSTIMER_INTENA - When this bit is '1' an interrupt/wakeup request to the domain processor will be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests due to the OSTIMER_INTR flag are blocked. - 1 - 1 - read-write - - - MATCH_WR_RDY - This bit will be low when it is safe to write to reload the Match Registers. In typical applications it should not be necessary to test this bit. [1] - 2 - 1 - read-only - - - - - - - FLASH - FLASH - FLASH - 0x40034000 - - 0 - 0x1000 - registers - - - - CMD - command register - 0 - 32 - write-only - 0 - 0xFFFFFFFF - - - CMD - command register. - 0 - 32 - write-only - - - - - EVENT - event register - 0x4 - 32 - write-only - 0 - 0x7 - - - RST - When bit is set, the controller and flash are reset. - 0 - 1 - write-only - - - WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active. - 1 - 1 - write-only - - - ABORT - When bit is set, a running program/erase command is aborted. - 2 - 1 - write-only - - - - - STARTA - start (or only) address for next flash command - 0x10 - 32 - read-write - 0 - 0x3FFFF - - - STARTA - Address / Start address for commands that take an address (range) as a parameter. - 0 - 18 - read-write - - - - - STOPA - end address for next flash command, if command operates on address ranges - 0x14 - 32 - read-write - 0 - 0x3FFFF - - - STOPA - Stop address for commands that take an address range as a parameter (the word specified by STOPA is included in the address range). - 0 - 18 - read-write - - - - - 4 - 0x4 - DATAW[%s] - data register, word 0-7; Memory data, or command parameter, or command result. - 0x80 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATAW - no description available - 0 - 32 - read-write - - - - - INT_CLR_ENABLE - Clear interrupt enable bits - 0xFD8 - 32 - write-only - 0 - 0xF - - - FAIL - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - 0 - 1 - write-only - - - ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - 1 - 1 - write-only - - - DONE - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - 2 - 1 - write-only - - - ECC_ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. - 3 - 1 - write-only - - - - - INT_SET_ENABLE - Set interrupt enable bits - 0xFDC - 32 - write-only - 0 - 0xF - - - FAIL - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - 0 - 1 - write-only - - - ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - 1 - 1 - write-only - - - DONE - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - 2 - 1 - write-only - - - ECC_ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. - 3 - 1 - write-only - - - - - INT_STATUS - Interrupt status bits - 0xFE0 - 32 - read-write - 0 - 0xF - - - FAIL - This status bit is set if execution of a (legal) command failed. - 0 - 1 - read-only - - - ERR - This status bit is set if execution of an illegal command is detected. - 1 - 1 - read-only - - - DONE - This status bit is set at the end of command execution. - 2 - 1 - read-only - - - ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested read, or a speculative read, or reads performed by a controller command), a correctable or uncorrectable error is detected by ECC decoding logic. - 3 - 1 - read-only - - - - - INT_ENABLE - Interrupt enable bits - 0xFE4 - 32 - read-write - 0 - 0xF - - - FAIL - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - 0 - 1 - read-only - - - ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - 1 - 1 - read-only - - - DONE - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - 2 - 1 - read-only - - - ECC_ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. - 3 - 1 - read-only - - - - - INT_CLR_STATUS - Clear interrupt status bits - 0xFE8 - 32 - write-only - 0 - 0xF - - - FAIL - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - 0 - 1 - write-only - - - ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - 1 - 1 - write-only - - - DONE - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - 2 - 1 - write-only - - - ECC_ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. - 3 - 1 - write-only - - - - - INT_SET_STATUS - Set interrupt status bits - 0xFEC - 32 - write-only - 0 - 0xF - - - FAIL - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - 0 - 1 - write-only - - - ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - 1 - 1 - write-only - - - DONE - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - 2 - 1 - write-only - - - ECC_ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. - 3 - 1 - write-only - - - - - MODULE_ID - Controller+Memory module identification - 0xFFC - 32 - read-only - 0xC40F0800 - 0xFFFFFFFF - - - APERTURE - Aperture i. - 0 - 8 - read-only - - - MINOR_REV - Minor revision i. - 8 - 4 - read-only - - - MAJOR_REV - Major revision i. - 12 - 4 - read-only - - - ID - Identifier. - 16 - 16 - read-only - - - - - - - PRINCE - PRINCE - PRINCE - 0x40035000 - - 0 - 0x40 - registers - - - - ENC_ENABLE - Encryption Enable register - 0 - 32 - read-write - 0 - 0x1 - - - EN - Encryption Enable. - 0 - 1 - read-write - - - DISABLED - Encryption of writes to the flash controller DATAW* registers is disabled. - 0 - - - ENABLED - Encryption of writes to the flash controller DATAW* registers is enabled. - 0x1 - - - - - - - MASK_LSB - Data Mask register, 32 Least Significant Bits - 0x4 - 32 - write-only - 0 - 0xFFFFFFFF - - - MASKVAL - Value of the 32 Least Significant Bits of the 64-bit data mask. - 0 - 32 - write-only - - - - - MASK_MSB - Data Mask register, 32 Most Significant Bits - 0x8 - 32 - write-only - 0 - 0xFFFFFFFF - - - MASKVAL - Value of the 32 Most Significant Bits of the 64-bit data mask. - 0 - 32 - write-only - - - - - LOCK - Lock register - 0xC - 32 - read-write - 0 - 0x107 - - - LOCKREG0 - Lock Region 0 registers. - 0 - 1 - read-write - - - DISABLED - Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. - 0 - - - ENABLED - Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. - 0x1 - - - - - LOCKREG1 - Lock Region 1 registers. - 1 - 1 - read-write - - - DISABLED - Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. - 0 - - - ENABLED - Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. - 0x1 - - - - - LOCKREG2 - Lock Region 2 registers. - 2 - 1 - read-write - - - DISABLED - Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. - 0 - - - ENABLED - Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. - 0x1 - - - - - LOCKMASK - Lock the Mask registers. - 8 - 1 - read-write - - - DISABLED - Disabled. MASK_LSB, and MASK_MSB are writable.. - 0 - - - ENABLED - Enabled. MASK_LSB, and MASK_MSB are not writable.. - 0x1 - - - - - - - IV_LSB0 - Initial Vector register for region 0, Least Significant Bits - 0x10 - 32 - write-only - 0 - 0xFFFFFFFF - - - IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - 0 - 32 - write-only - - - - - IV_MSB0 - Initial Vector register for region 0, Most Significant Bits - 0x14 - 32 - write-only - 0 - 0xFFFFFFFF - - - IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - 0 - 32 - write-only - - - - - BASE_ADDR0 - Base Address for region 0 register - 0x18 - 32 - read-write - 0 - 0xFFFFF - - - ADDR_FIXED - Fixed portion of the base address of region 0. - 0 - 18 - read-only - - - ADDR_PRG - Programmable portion of the base address of region 0. - 18 - 2 - read-write - - - - - SR_ENABLE0 - Sub-Region Enable register for region 0 - 0x1C - 32 - read-write - 0 - 0xFFFFFFFF - - - EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0. - 0 - 32 - read-write - - - - - IV_LSB1 - Initial Vector register for region 1, Least Significant Bits - 0x20 - 32 - write-only - 0 - 0xFFFFFFFF - - - IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - 0 - 32 - write-only - - - - - IV_MSB1 - Initial Vector register for region 1, Most Significant Bits - 0x24 - 32 - write-only - 0 - 0xFFFFFFFF - - - IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - 0 - 32 - write-only - - - - - BASE_ADDR1 - Base Address for region 1 register - 0x28 - 32 - read-write - 0x40000 - 0xFFFFF - - - ADDR_FIXED - Fixed portion of the base address of region 1. - 0 - 18 - read-only - - - ADDR_PRG - Programmable portion of the base address of region 1. - 18 - 2 - read-write - - - - - SR_ENABLE1 - Sub-Region Enable register for region 1 - 0x2C - 32 - read-write - 0 - 0xFFFFFFFF - - - EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1. - 0 - 32 - read-write - - - - - IV_LSB2 - Initial Vector register for region 2, Least Significant Bits - 0x30 - 32 - write-only - 0 - 0xFFFFFFFF - - - IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. - 0 - 32 - write-only - - - - - IV_MSB2 - Initial Vector register for region 2, Most Significant Bits - 0x34 - 32 - write-only - 0 - 0xFFFFFFFF - - - IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. - 0 - 32 - write-only - - - - - BASE_ADDR2 - Base Address for region 2 register - 0x38 - 32 - read-write - 0x80000 - 0xFFFFF - - - ADDR_FIXED - Fixed portion of the base address of region 2. - 0 - 18 - read-only - - - ADDR_PRG - Programmable portion of the base address of region 2. - 18 - 2 - read-write - - - - - SR_ENABLE2 - Sub-Region Enable register for region 2 - 0x3C - 32 - read-write - 0 - 0xFFFFFFFF - - - EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2. - 0 - 32 - read-write - - - - - - - USBPHY - Universal System Bus Physical Layer - USBPHY - 0x40038000 - - 0 - 0x110 - registers - - - USB1_PHY - 46 - - - - PWD - USB PHY Power-Down Register - 0 - 32 - read-write - 0x1E1C00 - 0xFFFFFFFF - - - TXPWDFS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 10 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - 0x1 - - - - - TXPWDIBIAS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 11 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - 0x1 - - - - - TXPWDV2I - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 12 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY transmit V-to-I converter and the current mirror - 0x1 - - - - - RXPWDENV - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 17 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed receiver envelope detector (squelch signal) - 0x1 - - - - - RXPWD1PT1 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 18 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed differential receiver. - 0x1 - - - - - RXPWDDIFF - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 19 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed differential receive - 0x1 - - - - - RXPWDRX - This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 20 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the entire USB PHY receiver block except for the full-speed differential receiver - 0x1 - - - - - - - PWD_SET - USB PHY Power-Down Register - 0x4 - 32 - read-write - 0x1E1C00 - 0xFFFFFFFF - - - TXPWDFS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 10 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - 0x1 - - - - - TXPWDIBIAS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 11 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - 0x1 - - - - - TXPWDV2I - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 12 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY transmit V-to-I converter and the current mirror - 0x1 - - - - - RXPWDENV - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 17 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed receiver envelope detector (squelch signal) - 0x1 - - - - - RXPWD1PT1 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 18 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed differential receiver. - 0x1 - - - - - RXPWDDIFF - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 19 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed differential receive - 0x1 - - - - - RXPWDRX - This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 20 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the entire USB PHY receiver block except for the full-speed differential receiver - 0x1 - - - - - - - PWD_CLR - USB PHY Power-Down Register - 0x8 - 32 - read-write - 0x1E1C00 - 0xFFFFFFFF - - - TXPWDFS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 10 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - 0x1 - - - - - TXPWDIBIAS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 11 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - 0x1 - - - - - TXPWDV2I - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 12 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY transmit V-to-I converter and the current mirror - 0x1 - - - - - RXPWDENV - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 17 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed receiver envelope detector (squelch signal) - 0x1 - - - - - RXPWD1PT1 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 18 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed differential receiver. - 0x1 - - - - - RXPWDDIFF - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 19 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed differential receive - 0x1 - - - - - RXPWDRX - This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 20 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the entire USB PHY receiver block except for the full-speed differential receiver - 0x1 - - - - - - - PWD_TOG - USB PHY Power-Down Register - 0xC - 32 - read-write - 0x1E1C00 - 0xFFFFFFFF - - - TXPWDFS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 10 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - 0x1 - - - - - TXPWDIBIAS - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 11 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - 0x1 - - - - - TXPWDV2I - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 12 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB PHY transmit V-to-I converter and the current mirror - 0x1 - - - - - RXPWDENV - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 17 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed receiver envelope detector (squelch signal) - 0x1 - - - - - RXPWD1PT1 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 18 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB full-speed differential receiver. - 0x1 - - - - - RXPWDDIFF - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 19 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the USB high-speed differential receive - 0x1 - - - - - RXPWDRX - This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled - 20 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Power-down the entire USB PHY receiver block except for the full-speed differential receiver - 0x1 - - - - - - - TX - USB PHY Transmitter Control Register - 0x10 - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - D_CAL - Decode to trim the nominal 17 - 0 - 4 - read-write - - - value0 - Maximum current, approximately 19% above nominal. - 0 - - - value7 - Nominal - 0x7 - - - value15 - Minimum current, approximately 19% below nominal. - 0xF - - - - - TXCAL45DM - Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin - 8 - 4 - read-write - - - TXENCAL45DN - Enable resistance calibration on DN. - 13 - 1 - read-write - - - TXCAL45DP - Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin - 16 - 4 - read-write - - - TXENCAL45DP - Enable resistance calibration on DP. - 21 - 1 - read-write - - - - - TX_SET - USB PHY Transmitter Control Register - 0x14 - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - D_CAL - Decode to trim the nominal 17 - 0 - 4 - read-write - - - value0 - Maximum current, approximately 19% above nominal. - 0 - - - value7 - Nominal - 0x7 - - - value15 - Minimum current, approximately 19% below nominal. - 0xF - - - - - TXCAL45DM - Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin - 8 - 4 - read-write - - - TXENCAL45DN - Enable resistance calibration on DN. - 13 - 1 - read-write - - - TXCAL45DP - Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin - 16 - 4 - read-write - - - TXENCAL45DP - Enable resistance calibration on DP. - 21 - 1 - read-write - - - - - TX_CLR - USB PHY Transmitter Control Register - 0x18 - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - D_CAL - Decode to trim the nominal 17 - 0 - 4 - read-write - - - value0 - Maximum current, approximately 19% above nominal. - 0 - - - value7 - Nominal - 0x7 - - - value15 - Minimum current, approximately 19% below nominal. - 0xF - - - - - TXCAL45DM - Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin - 8 - 4 - read-write - - - TXENCAL45DN - Enable resistance calibration on DN. - 13 - 1 - read-write - - - TXCAL45DP - Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin - 16 - 4 - read-write - - - TXENCAL45DP - Enable resistance calibration on DP. - 21 - 1 - read-write - - - - - TX_TOG - USB PHY Transmitter Control Register - 0x1C - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - D_CAL - Decode to trim the nominal 17 - 0 - 4 - read-write - - - value0 - Maximum current, approximately 19% above nominal. - 0 - - - value7 - Nominal - 0x7 - - - value15 - Minimum current, approximately 19% below nominal. - 0xF - - - - - TXCAL45DM - Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin - 8 - 4 - read-write - - - TXENCAL45DN - Enable resistance calibration on DN. - 13 - 1 - read-write - - - TXCAL45DP - Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin - 16 - 4 - read-write - - - TXENCAL45DP - Enable resistance calibration on DP. - 21 - 1 - read-write - - - - - RX - USB PHY Receiver Control Register - 0x20 - 32 - read-write - 0 - 0xFFFFFFFF - - - ENVADJ - The ENVADJ field adjusts the trip point for the envelope detector - 0 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.1000 V - 0 - - - value1 - Trip-Level Voltage is 0.1125 V - 0x1 - - - value2 - Trip-Level Voltage is 0.1250 V - 0x2 - - - value3 - Trip-Level Voltage is 0.0875 V - 0x3 - - - - - DISCONADJ - The DISCONADJ field adjusts the trip point for the disconnect detector. - 4 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.56875 V - 0 - - - value1 - Trip-Level Voltage is 0.55000 V - 0x1 - - - value2 - Trip-Level Voltage is 0.58125 V - 0x2 - - - value3 - Trip-Level Voltage is 0.60000 V - 0x3 - - - - - RXDBYPASS - This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver - 22 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - 0x1 - - - - - - - RX_SET - USB PHY Receiver Control Register - 0x24 - 32 - read-write - 0 - 0xFFFFFFFF - - - ENVADJ - The ENVADJ field adjusts the trip point for the envelope detector - 0 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.1000 V - 0 - - - value1 - Trip-Level Voltage is 0.1125 V - 0x1 - - - value2 - Trip-Level Voltage is 0.1250 V - 0x2 - - - value3 - Trip-Level Voltage is 0.0875 V - 0x3 - - - - - DISCONADJ - The DISCONADJ field adjusts the trip point for the disconnect detector. - 4 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.56875 V - 0 - - - value1 - Trip-Level Voltage is 0.55000 V - 0x1 - - - value2 - Trip-Level Voltage is 0.58125 V - 0x2 - - - value3 - Trip-Level Voltage is 0.60000 V - 0x3 - - - - - RXDBYPASS - This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver - 22 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - 0x1 - - - - - - - RX_CLR - USB PHY Receiver Control Register - 0x28 - 32 - read-write - 0 - 0xFFFFFFFF - - - ENVADJ - The ENVADJ field adjusts the trip point for the envelope detector - 0 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.1000 V - 0 - - - value1 - Trip-Level Voltage is 0.1125 V - 0x1 - - - value2 - Trip-Level Voltage is 0.1250 V - 0x2 - - - value3 - Trip-Level Voltage is 0.0875 V - 0x3 - - - - - DISCONADJ - The DISCONADJ field adjusts the trip point for the disconnect detector. - 4 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.56875 V - 0 - - - value1 - Trip-Level Voltage is 0.55000 V - 0x1 - - - value2 - Trip-Level Voltage is 0.58125 V - 0x2 - - - value3 - Trip-Level Voltage is 0.60000 V - 0x3 - - - - - RXDBYPASS - This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver - 22 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - 0x1 - - - - - - - RX_TOG - USB PHY Receiver Control Register - 0x2C - 32 - read-write - 0 - 0xFFFFFFFF - - - ENVADJ - The ENVADJ field adjusts the trip point for the envelope detector - 0 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.1000 V - 0 - - - value1 - Trip-Level Voltage is 0.1125 V - 0x1 - - - value2 - Trip-Level Voltage is 0.1250 V - 0x2 - - - value3 - Trip-Level Voltage is 0.0875 V - 0x3 - - - - - DISCONADJ - The DISCONADJ field adjusts the trip point for the disconnect detector. - 4 - 3 - read-write - - - value0 - Trip-Level Voltage is 0.56875 V - 0 - - - value1 - Trip-Level Voltage is 0.55000 V - 0x1 - - - value2 - Trip-Level Voltage is 0.58125 V - 0x2 - - - value3 - Trip-Level Voltage is 0.60000 V - 0x3 - - - - - RXDBYPASS - This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver - 22 - 1 - read-write - - - value0 - Normal operation. - 0 - - - value1 - Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - 0x1 - - - - - - - CTRL - USB PHY General Control Register - 0x30 - 32 - read-write - 0xC0000000 - 0xFFFFFFFF - - - ENHOSTDISCONDETECT - For host mode, enables high-speed disconnect detector - 1 - 1 - read-write - - - ENIRQHOSTDISCON - Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode - 2 - 1 - read-write - - - HOSTDISCONDETECT_IRQ - Indicates that the device has disconnected in High-Speed mode - 3 - 1 - read-write - - - ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode - 4 - 1 - read-write - - - value0 - Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - 0 - - - value1 - Enables 200kohm pullup resistors on USB_DP and USB_DM pins - 0x1 - - - - - DEVPLUGIN_POLARITY - Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in - 5 - 1 - read-write - - - RESUMEIRQSTICKY - Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it - 8 - 1 - read-write - - - ENIRQRESUMEDETECT - Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line - 9 - 1 - read-write - - - RESUME_IRQ - Resume IRQ: Indicates that the host is sending a wake-up after suspend - 10 - 1 - read-write - - - DEVPLUGIN_IRQ - Indicates that the device is connected - 12 - 1 - read-write - - - ENUTMILEVEL2 - Enables UTMI+ Level 2 operation for the USB HS PHY - 14 - 1 - read-write - - - ENUTMILEVEL3 - Enables UTMI+ Level 3 operation for the USB HS PHY - 15 - 1 - read-write - - - ENIRQWAKEUP - Enable wake-up IRQ: Enables interrupt for the wake-up events. - 16 - 1 - read-write - - - WAKEUP_IRQ - Wake-up IRQ: Indicates that there is a wak-eup event - 17 - 1 - read-write - - - AUTORESUME_EN - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) - 18 - 1 - read-write - - - ENAUTOCLR_CLKGATE - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended - 19 - 1 - read-write - - - ENAUTOCLR_PHY_PWD - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended - 20 - 1 - read-write - - - ENDPDMCHG_WKUP - Enable DP DM change wake-up: Not for customer use - 21 - 1 - read-write - - - ENVBUSCHG_WKUP - Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended - 23 - 1 - read-write - - - ENAUTOCLR_USBCLKGATE - Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 25 - 1 - read-write - - - ENAUTOSET_USBCLKS - Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 26 - 1 - read-write - - - HOST_FORCE_LS_SE0 - Forces the next FS packet that is transmitted to have a EOP with low-speed timing - 28 - 1 - read-write - - - UTMI_SUSPENDM - Used by the PHY to indicate a powered-down state - 29 - 1 - read-write - - - CLKGATE - Gate UTMI Clocks - 30 - 1 - read-write - - - SFTRST - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers - 31 - 1 - read-write - - - - - CTRL_SET - USB PHY General Control Register - 0x34 - 32 - read-write - 0xC0000000 - 0xFFFFFFFF - - - ENHOSTDISCONDETECT - For host mode, enables high-speed disconnect detector - 1 - 1 - read-write - - - ENIRQHOSTDISCON - Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode - 2 - 1 - read-write - - - HOSTDISCONDETECT_IRQ - Indicates that the device has disconnected in High-Speed mode - 3 - 1 - read-write - - - ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode - 4 - 1 - read-write - - - value0 - Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - 0 - - - value1 - Enables 200kohm pullup resistors on USB_DP and USB_DM pins - 0x1 - - - - - DEVPLUGIN_POLARITY - Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in - 5 - 1 - read-write - - - RESUMEIRQSTICKY - Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it - 8 - 1 - read-write - - - ENIRQRESUMEDETECT - Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line - 9 - 1 - read-write - - - RESUME_IRQ - Resume IRQ: Indicates that the host is sending a wake-up after suspend - 10 - 1 - read-write - - - DEVPLUGIN_IRQ - Indicates that the device is connected - 12 - 1 - read-write - - - ENUTMILEVEL2 - Enables UTMI+ Level 2 operation for the USB HS PHY - 14 - 1 - read-write - - - ENUTMILEVEL3 - Enables UTMI+ Level 3 operation for the USB HS PHY - 15 - 1 - read-write - - - ENIRQWAKEUP - Enable wake-up IRQ: Enables interrupt for the wake-up events. - 16 - 1 - read-write - - - WAKEUP_IRQ - Wake-up IRQ: Indicates that there is a wak-eup event - 17 - 1 - read-write - - - AUTORESUME_EN - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) - 18 - 1 - read-write - - - ENAUTOCLR_CLKGATE - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended - 19 - 1 - read-write - - - ENAUTOCLR_PHY_PWD - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended - 20 - 1 - read-write - - - ENDPDMCHG_WKUP - Enable DP DM change wake-up: Not for customer use - 21 - 1 - read-write - - - ENVBUSCHG_WKUP - Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended - 23 - 1 - read-write - - - ENAUTOCLR_USBCLKGATE - Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 25 - 1 - read-write - - - ENAUTOSET_USBCLKS - Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 26 - 1 - read-write - - - HOST_FORCE_LS_SE0 - Forces the next FS packet that is transmitted to have a EOP with low-speed timing - 28 - 1 - read-write - - - UTMI_SUSPENDM - Used by the PHY to indicate a powered-down state - 29 - 1 - read-only - - - CLKGATE - Gate UTMI Clocks - 30 - 1 - read-write - - - SFTRST - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers - 31 - 1 - read-write - - - - - CTRL_CLR - USB PHY General Control Register - 0x38 - 32 - read-write - 0xC0000000 - 0xFFFFFFFF - - - ENHOSTDISCONDETECT - For host mode, enables high-speed disconnect detector - 1 - 1 - read-write - - - ENIRQHOSTDISCON - Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode - 2 - 1 - read-write - - - HOSTDISCONDETECT_IRQ - Indicates that the device has disconnected in High-Speed mode - 3 - 1 - read-write - - - ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode - 4 - 1 - read-write - - - value0 - Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - 0 - - - value1 - Enables 200kohm pullup resistors on USB_DP and USB_DM pins - 0x1 - - - - - DEVPLUGIN_POLARITY - Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in - 5 - 1 - read-write - - - RESUMEIRQSTICKY - Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it - 8 - 1 - read-write - - - ENIRQRESUMEDETECT - Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line - 9 - 1 - read-write - - - RESUME_IRQ - Resume IRQ: Indicates that the host is sending a wake-up after suspend - 10 - 1 - read-write - - - DEVPLUGIN_IRQ - Indicates that the device is connected - 12 - 1 - read-write - - - ENUTMILEVEL2 - Enables UTMI+ Level 2 operation for the USB HS PHY - 14 - 1 - read-write - - - ENUTMILEVEL3 - Enables UTMI+ Level 3 operation for the USB HS PHY - 15 - 1 - read-write - - - ENIRQWAKEUP - Enable wake-up IRQ: Enables interrupt for the wake-up events. - 16 - 1 - read-write - - - WAKEUP_IRQ - Wake-up IRQ: Indicates that there is a wak-eup event - 17 - 1 - read-write - - - AUTORESUME_EN - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) - 18 - 1 - read-write - - - ENAUTOCLR_CLKGATE - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended - 19 - 1 - read-write - - - ENAUTOCLR_PHY_PWD - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended - 20 - 1 - read-write - - - ENDPDMCHG_WKUP - Enable DP DM change wake-up: Not for customer use - 21 - 1 - read-write - - - ENVBUSCHG_WKUP - Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended - 23 - 1 - read-write - - - ENAUTOCLR_USBCLKGATE - Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 25 - 1 - read-write - - - ENAUTOSET_USBCLKS - Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 26 - 1 - read-write - - - HOST_FORCE_LS_SE0 - Forces the next FS packet that is transmitted to have a EOP with low-speed timing - 28 - 1 - read-write - - - UTMI_SUSPENDM - Used by the PHY to indicate a powered-down state - 29 - 1 - read-write - - - CLKGATE - Gate UTMI Clocks - 30 - 1 - read-write - - - SFTRST - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers - 31 - 1 - read-write - - - - - CTRL_TOG - USB PHY General Control Register - 0x3C - 32 - read-write - 0xC0000000 - 0xFFFFFFFF - - - ENHOSTDISCONDETECT - For host mode, enables high-speed disconnect detector - 1 - 1 - read-write - - - ENIRQHOSTDISCON - Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode - 2 - 1 - read-write - - - HOSTDISCONDETECT_IRQ - Indicates that the device has disconnected in High-Speed mode - 3 - 1 - read-write - - - ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode - 4 - 1 - read-write - - - value0 - Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - 0 - - - value1 - Enables 200kohm pullup resistors on USB_DP and USB_DM pins - 0x1 - - - - - DEVPLUGIN_POLARITY - Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in - 5 - 1 - read-write - - - RESUMEIRQSTICKY - Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it - 8 - 1 - read-write - - - ENIRQRESUMEDETECT - Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line - 9 - 1 - read-write - - - RESUME_IRQ - Resume IRQ: Indicates that the host is sending a wake-up after suspend - 10 - 1 - read-write - - - DEVPLUGIN_IRQ - Indicates that the device is connected - 12 - 1 - read-write - - - ENUTMILEVEL2 - Enables UTMI+ Level 2 operation for the USB HS PHY - 14 - 1 - read-write - - - ENUTMILEVEL3 - Enables UTMI+ Level 3 operation for the USB HS PHY - 15 - 1 - read-write - - - ENIRQWAKEUP - Enable wake-up IRQ: Enables interrupt for the wake-up events. - 16 - 1 - read-write - - - WAKEUP_IRQ - Wake-up IRQ: Indicates that there is a wak-eup event - 17 - 1 - read-write - - - AUTORESUME_EN - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) - 18 - 1 - read-write - - - ENAUTOCLR_CLKGATE - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended - 19 - 1 - read-write - - - ENAUTOCLR_PHY_PWD - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended - 20 - 1 - read-write - - - ENDPDMCHG_WKUP - Enable DP DM change wake-up: Not for customer use - 21 - 1 - read-write - - - ENVBUSCHG_WKUP - Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended - 23 - 1 - read-write - - - ENAUTOCLR_USBCLKGATE - Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 25 - 1 - read-write - - - ENAUTOSET_USBCLKS - Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended - 26 - 1 - read-write - - - HOST_FORCE_LS_SE0 - Forces the next FS packet that is transmitted to have a EOP with low-speed timing - 28 - 1 - read-write - - - UTMI_SUSPENDM - Used by the PHY to indicate a powered-down state - 29 - 1 - read-write - - - CLKGATE - Gate UTMI Clocks - 30 - 1 - read-write - - - SFTRST - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers - 31 - 1 - read-write - - - - - STATUS - USB PHY Status Register - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - OK_STATUS_3V - Indicates the USB 3v power rails are in range. - 0 - 1 - read-only - - - HOSTDISCONDETECT_STATUS - Indicates at the local host (downstream) port that the remote device has disconnected while in High-Speed mode - 3 - 1 - read-only - - - value0 - USB cable disconnect has not been detected at the local host - 0 - - - value1 - USB cable disconnect has been detected at the local host - 0x1 - - - - - DEVPLUGIN_STATUS - Status indicator for non-standard resistive plugged-in detection Indicates that the device has been connected on the USB_DP and USB_DM lines using the nonstandard resistive plugged-in detection method controlled by CTRL[4] - 6 - 1 - read-only - - - value0 - No attachment to a USB host is detected - 0 - - - value1 - Cable attachment to a USB host is detected - 0x1 - - - - - RESUME_STATUS - Indicates that the host is sending a wake-up after Suspend and has triggered an interrupt. - 10 - 1 - read-only - - - - - PLL_SIC - USB PHY PLL Control/Status Register - 0xA0 - 32 - read-write - 0xD12000 - 0xFFFFFFFF - - - PLL_EN_USB_CLKS - Enables the USB clock from PLL to USB PHY - 6 - 1 - read-write - - - PLL_POWER - Power up the USB PLL - 12 - 1 - read-write - - - PLL_ENABLE - Enables the clock output from the USB PLL - 13 - 1 - read-write - - - REFBIAS_PWD_SEL - Reference bias power down select. - 19 - 1 - read-write - - - value0 - Selects PLL_POWER to control the reference bias - 0 - - - value1 - Selects REFBIAS_PWD to control the reference bias - 0x1 - - - - - REFBIAS_PWD - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. - 20 - 1 - read-write - - - PLL_REG_ENABLE - This field controls the USB PLL regulator, set to enable the regulator - 21 - 1 - read-write - - - PLL_DIV_SEL - This field controls the USB PLL feedback loop divider - 22 - 3 - read-write - - - value0 - Divide by 13 - 0 - - - value1 - Divide by 15 - 0x1 - - - value2 - Divide by 16 - 0x2 - - - value3 - Divide by 20 - 0x3 - - - value4 - Divide by 22 - 0x4 - - - value5 - Divide by 25 - 0x5 - - - value6 - Divide by 30 - 0x6 - - - value7 - Divide by 240 - 0x7 - - - - - PLL_PREDIV - This is selection between /1 or /2 to expand the range of ref input clock. - 30 - 1 - read-write - - - PLL_LOCK - USB PLL lock status indicator - 31 - 1 - read-only - - - value0 - PLL is not currently locked - 0 - - - value1 - PLL is currently locked - 0x1 - - - - - - - PLL_SIC_SET - USB PHY PLL Control/Status Register - 0xA4 - 32 - read-write - 0xD12000 - 0xFFFFFFFF - - - PLL_EN_USB_CLKS - Enables the USB clock from PLL to USB PHY - 6 - 1 - read-write - - - PLL_POWER - Power up the USB PLL - 12 - 1 - read-write - - - PLL_ENABLE - Enables the clock output from the USB PLL - 13 - 1 - read-write - - - REFBIAS_PWD_SEL - Reference bias power down select. - 19 - 1 - read-write - - - value0 - Selects PLL_POWER to control the reference bias - 0 - - - value1 - Selects REFBIAS_PWD to control the reference bias - 0x1 - - - - - REFBIAS_PWD - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. - 20 - 1 - read-write - - - PLL_REG_ENABLE - This field controls the USB PLL regulator, set to enable the regulator - 21 - 1 - read-write - - - PLL_DIV_SEL - This field controls the USB PLL feedback loop divider - 22 - 3 - read-write - - - value0 - Divide by 13 - 0 - - - value1 - Divide by 15 - 0x1 - - - value2 - Divide by 16 - 0x2 - - - value3 - Divide by 20 - 0x3 - - - value4 - Divide by 22 - 0x4 - - - value5 - Divide by 25 - 0x5 - - - value6 - Divide by 30 - 0x6 - - - value7 - Divide by 240 - 0x7 - - - - - PLL_PREDIV - This is selection between /1 or /2 to expand the range of ref input clock. - 30 - 1 - read-write - - - PLL_LOCK - USB PLL lock status indicator - 31 - 1 - read-only - - - value0 - PLL is not currently locked - 0 - - - value1 - PLL is currently locked - 0x1 - - - - - - - PLL_SIC_CLR - USB PHY PLL Control/Status Register - 0xA8 - 32 - read-write - 0xD12000 - 0xFFFFFFFF - - - PLL_EN_USB_CLKS - Enables the USB clock from PLL to USB PHY - 6 - 1 - read-write - - - PLL_POWER - Power up the USB PLL - 12 - 1 - read-write - - - PLL_ENABLE - Enables the clock output from the USB PLL - 13 - 1 - read-write - - - REFBIAS_PWD_SEL - Reference bias power down select. - 19 - 1 - read-write - - - value0 - Selects PLL_POWER to control the reference bias - 0 - - - value1 - Selects REFBIAS_PWD to control the reference bias - 0x1 - - - - - REFBIAS_PWD - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. - 20 - 1 - read-write - - - PLL_REG_ENABLE - This field controls the USB PLL regulator, set to enable the regulator - 21 - 1 - read-write - - - PLL_DIV_SEL - This field controls the USB PLL feedback loop divider - 22 - 3 - read-write - - - value0 - Divide by 13 - 0 - - - value1 - Divide by 15 - 0x1 - - - value2 - Divide by 16 - 0x2 - - - value3 - Divide by 20 - 0x3 - - - value4 - Divide by 22 - 0x4 - - - value5 - Divide by 25 - 0x5 - - - value6 - Divide by 30 - 0x6 - - - value7 - Divide by 240 - 0x7 - - - - - PLL_PREDIV - This is selection between /1 or /2 to expand the range of ref input clock. - 30 - 1 - read-write - - - PLL_LOCK - USB PLL lock status indicator - 31 - 1 - read-only - - - value0 - PLL is not currently locked - 0 - - - value1 - PLL is currently locked - 0x1 - - - - - - - PLL_SIC_TOG - USB PHY PLL Control/Status Register - 0xAC - 32 - read-write - 0xD12000 - 0xFFFFFFFF - - - PLL_EN_USB_CLKS - Enables the USB clock from PLL to USB PHY - 6 - 1 - read-write - - - PLL_POWER - Power up the USB PLL - 12 - 1 - read-write - - - PLL_ENABLE - Enables the clock output from the USB PLL - 13 - 1 - read-write - - - REFBIAS_PWD_SEL - Reference bias power down select. - 19 - 1 - read-write - - - value0 - Selects PLL_POWER to control the reference bias - 0 - - - value1 - Selects REFBIAS_PWD to control the reference bias - 0x1 - - - - - REFBIAS_PWD - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. - 20 - 1 - read-write - - - PLL_REG_ENABLE - This field controls the USB PLL regulator, set to enable the regulator - 21 - 1 - read-write - - - PLL_DIV_SEL - This field controls the USB PLL feedback loop divider - 22 - 3 - read-write - - - value0 - Divide by 13 - 0 - - - value1 - Divide by 15 - 0x1 - - - value2 - Divide by 16 - 0x2 - - - value3 - Divide by 20 - 0x3 - - - value4 - Divide by 22 - 0x4 - - - value5 - Divide by 25 - 0x5 - - - value6 - Divide by 30 - 0x6 - - - value7 - Divide by 240 - 0x7 - - - - - PLL_PREDIV - This is selection between /1 or /2 to expand the range of ref input clock. - 30 - 1 - read-write - - - PLL_LOCK - USB PLL lock status indicator - 31 - 1 - read-only - - - value0 - PLL is not currently locked - 0 - - - value1 - PLL is currently locked - 0x1 - - - - - - - USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register - 0xC0 - 32 - read-write - 0x700004 - 0xFFFFFFFF - - - VBUSVALID_THRESH - Sets the threshold for the VBUSVALID comparator - 0 - 3 - read-write - - - value0 - 4.0V - 0 - - - value1 - 4.1V - 0x1 - - - value2 - 4.2V - 0x2 - - - value3 - 4.3V - 0x3 - - - value4 - 4.4V(Default) - 0x4 - - - value5 - 4.5V - 0x5 - - - value6 - 4.6V - 0x6 - - - value7 - 4.7V - 0x7 - - - - - VBUS_OVERRIDE_EN - VBUS detect signal override enable - 3 - 1 - read-write - - - value0 - Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - 0 - - - value1 - Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - 0x1 - - - - - SESSEND_OVERRIDE - Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 - 4 - 1 - read-write - - - BVALID_OVERRIDE - Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 - 5 - 1 - read-write - - - AVALID_OVERRIDE - Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 - 6 - 1 - read-write - - - VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 - 7 - 1 - read-write - - - VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 8 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the VBUS_VALID_3V detector results for signal reported to the USB controller - 0x1 - - - - - VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 9 - 2 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the Session Valid comparator results for signal reported to the USB controller - 0x1 - - - value2 - Use the Session Valid comparator results for signal reported to the USB controller - 0x2 - - - - - ID_OVERRIDE_EN - Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. - 11 - 1 - read-write - - - ID_OVERRIDE - ID override value. - 12 - 1 - read-write - - - EXT_ID_OVERRIDE_EN - Enable ID override using the pinmuxed value: - 13 - 1 - read-write - - - value0 - Select the Muxed value chosen using ID_OVERRIDE_EN. - 0 - - - value1 - Select the external ID value. - 0x1 - - - - - EXT_VBUS_OVERRIDE_EN - Enable VBUS override using the pinmuxed value. - 14 - 1 - read-write - - - value0 - Select the Muxed value chosen using VBUS_OVERRIDE_EN. - 0 - - - value1 - Select the external VBUS VALID value. - 0x1 - - - - - VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator - 18 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator for VBUS_VALID results - 0 - - - value1 - Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - 0x1 - - - - - VBUSVALID_5VDETECT - no description available - 19 - 1 - read-write - - - PWRUP_CMPS - Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector - 20 - 3 - read-write - - - value0 - Powers down the VBUS_VALID comparator - 0 - - - value1 - Enables the VBUS_VALID comparator (default) - 0x7 - - - - - DISCHARGE_VBUS - Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground - 26 - 1 - read-write - - - value0 - VBUS discharge resistor is disabled (Default) - 0 - - - value1 - VBUS discharge resistor is enabled - 0x1 - - - - - - - USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register - 0xC4 - 32 - read-write - 0x700004 - 0xFFFFFFFF - - - VBUSVALID_THRESH - Sets the threshold for the VBUSVALID comparator - 0 - 3 - read-write - - - value0 - 4.0V - 0 - - - value1 - 4.1V - 0x1 - - - value2 - 4.2V - 0x2 - - - value3 - 4.3V - 0x3 - - - value4 - 4.4V(Default) - 0x4 - - - value5 - 4.5V - 0x5 - - - value6 - 4.6V - 0x6 - - - value7 - 4.7V - 0x7 - - - - - VBUS_OVERRIDE_EN - VBUS detect signal override enable - 3 - 1 - read-write - - - value0 - Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - 0 - - - value1 - Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - 0x1 - - - - - SESSEND_OVERRIDE - Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 - 4 - 1 - read-write - - - BVALID_OVERRIDE - Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 - 5 - 1 - read-write - - - AVALID_OVERRIDE - Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 - 6 - 1 - read-write - - - VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 - 7 - 1 - read-write - - - VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 8 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the VBUS_VALID_3V detector results for signal reported to the USB controller - 0x1 - - - - - VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 9 - 2 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the Session Valid comparator results for signal reported to the USB controller - 0x1 - - - value2 - Use the Session Valid comparator results for signal reported to the USB controller - 0x2 - - - - - ID_OVERRIDE_EN - Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. - 11 - 1 - read-write - - - ID_OVERRIDE - ID override value. - 12 - 1 - read-write - - - EXT_ID_OVERRIDE_EN - Enable ID override using the pinmuxed value: - 13 - 1 - read-write - - - value0 - Select the Muxed value chosen using ID_OVERRIDE_EN. - 0 - - - value1 - Select the external ID value. - 0x1 - - - - - EXT_VBUS_OVERRIDE_EN - Enable VBUS override using the pinmuxed value. - 14 - 1 - read-write - - - value0 - Select the Muxed value chosen using VBUS_OVERRIDE_EN. - 0 - - - value1 - Select the external VBUS VALID value. - 0x1 - - - - - VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator - 18 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator for VBUS_VALID results - 0 - - - value1 - Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - 0x1 - - - - - VBUSVALID_5VDETECT - no description available - 19 - 1 - read-write - - - PWRUP_CMPS - Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector - 20 - 3 - read-write - - - value0 - Powers down the VBUS_VALID comparator - 0 - - - value1 - Enables the VBUS_VALID comparator (default) - 0x7 - - - - - DISCHARGE_VBUS - Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground - 26 - 1 - read-write - - - value0 - VBUS discharge resistor is disabled (Default) - 0 - - - value1 - VBUS discharge resistor is enabled - 0x1 - - - - - - - USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register - 0xC8 - 32 - read-write - 0x700004 - 0xFFFFFFFF - - - VBUSVALID_THRESH - Sets the threshold for the VBUSVALID comparator - 0 - 3 - read-write - - - value0 - 4.0V - 0 - - - value1 - 4.1V - 0x1 - - - value2 - 4.2V - 0x2 - - - value3 - 4.3V - 0x3 - - - value4 - 4.4V(Default) - 0x4 - - - value5 - 4.5V - 0x5 - - - value6 - 4.6V - 0x6 - - - value7 - 4.7V - 0x7 - - - - - VBUS_OVERRIDE_EN - VBUS detect signal override enable - 3 - 1 - read-write - - - value0 - Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - 0 - - - value1 - Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - 0x1 - - - - - SESSEND_OVERRIDE - Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 - 4 - 1 - read-write - - - BVALID_OVERRIDE - Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 - 5 - 1 - read-write - - - AVALID_OVERRIDE - Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 - 6 - 1 - read-write - - - VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 - 7 - 1 - read-write - - - VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 8 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the VBUS_VALID_3V detector results for signal reported to the USB controller - 0x1 - - - - - VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 9 - 2 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the Session Valid comparator results for signal reported to the USB controller - 0x1 - - - value2 - Use the Session Valid comparator results for signal reported to the USB controller - 0x2 - - - - - ID_OVERRIDE_EN - Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. - 11 - 1 - read-write - - - ID_OVERRIDE - ID override value. - 12 - 1 - read-write - - - EXT_ID_OVERRIDE_EN - Enable ID override using the pinmuxed value: - 13 - 1 - read-write - - - value0 - Select the Muxed value chosen using ID_OVERRIDE_EN. - 0 - - - value1 - Select the external ID value. - 0x1 - - - - - EXT_VBUS_OVERRIDE_EN - Enable VBUS override using the pin muxed value. - 14 - 1 - read-write - - - value0 - Select the muxed value chosen using VBUS_OVERRIDE_EN. - 0 - - - value1 - Select the external VBUS VALID value. - 0x1 - - - - - VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator - 18 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator for VBUS_VALID results - 0 - - - value1 - Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - 0x1 - - - - - VBUSVALID_5VDETECT - no description available - 19 - 1 - read-write - - - PWRUP_CMPS - Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector - 20 - 3 - read-write - - - value0 - Powers down the VBUS_VALID comparator - 0 - - - value1 - Enables the VBUS_VALID comparator (default) - 0x7 - - - - - DISCHARGE_VBUS - Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground - 26 - 1 - read-write - - - value0 - VBUS discharge resistor is disabled (Default) - 0 - - - value1 - VBUS discharge resistor is enabled - 0x1 - - - - - - - USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register - 0xCC - 32 - read-write - 0x700004 - 0xFFFFFFFF - - - VBUSVALID_THRESH - Sets the threshold for the VBUSVALID comparator - 0 - 3 - read-write - - - value0 - 4.0V - 0 - - - value1 - 4.1V - 0x1 - - - value2 - 4.2V - 0x2 - - - value3 - 4.3V - 0x3 - - - value4 - 4.4V(Default) - 0x4 - - - value5 - 4.5V - 0x5 - - - value6 - 4.6V - 0x6 - - - value7 - 4.7V - 0x7 - - - - - VBUS_OVERRIDE_EN - VBUS detect signal override enable - 3 - 1 - read-write - - - value0 - Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - 0 - - - value1 - Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - 0x1 - - - - - SESSEND_OVERRIDE - Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 - 4 - 1 - read-write - - - BVALID_OVERRIDE - Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 - 5 - 1 - read-write - - - AVALID_OVERRIDE - Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 - 6 - 1 - read-write - - - VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 - 7 - 1 - read-write - - - VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 8 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the VBUS_VALID_3V detector results for signal reported to the USB controller - 0x1 - - - - - VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller - 9 - 2 - read-write - - - value0 - Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - 0 - - - value1 - Use the Session Valid comparator results for signal reported to the USB controller - 0x1 - - - value2 - Use the Session Valid comparator results for signal reported to the USB controller - 0x2 - - - - - ID_OVERRIDE_EN - Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. - 11 - 1 - read-write - - - ID_OVERRIDE - ID override value. - 12 - 1 - read-write - - - EXT_ID_OVERRIDE_EN - Enable ID override using the pin muxed value. - 13 - 1 - read-write - - - value0 - Select the muxed value chosen using ID_OVERRIDE_EN. - 0 - - - value1 - Select the external ID value. - 0x1 - - - - - EXT_VBUS_OVERRIDE_EN - Enable VBUS override using the pin muxed value. - 14 - 1 - read-write - - - value0 - Select the Muxed value chosen using VBUS_OVERRIDE_EN. - 0 - - - value1 - Select the external VBUS VALID value. - 0x1 - - - - - VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator - 18 - 1 - read-write - - - value0 - Use the VBUS_VALID comparator for VBUS_VALID results - 0 - - - value1 - Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - 0x1 - - - - - VBUSVALID_5VDETECT - no description available - 19 - 1 - read-write - - - PWRUP_CMPS - Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector - 20 - 3 - read-write - - - value0 - Powers down the VBUS_VALID comparator - 0 - - - value1 - Enables the VBUS_VALID comparator (default) - 0x7 - - - - - DISCHARGE_VBUS - Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground - 26 - 1 - read-write - - - value0 - VBUS discharge resistor is disabled (Default) - 0 - - - value1 - VBUS discharge resistor is enabled - 0x1 - - - - - - - ANACTRL - USB PHY Analog Control Register - 0x100 - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - LVI_EN - Vow voltage detector enable bit. - 1 - 1 - read-write - - - PFD_CLK_SEL - For normal USB operation, this bit field must remain at value 2'b00. - 2 - 2 - read-write - - - DEV_PULLDOWN - Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins - 10 - 1 - read-write - - - value0 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - 0 - - - value1 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - 0x1 - - - - - - - ANACTRL_SET - USB PHY Analog Control Register - 0x104 - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - LVI_EN - Vow voltage detector enable bit. - 1 - 1 - read-write - - - PFD_CLK_SEL - For normal USB operation, this bit field must remain at value 2'b00. - 2 - 2 - read-write - - - DEV_PULLDOWN - Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins - 10 - 1 - read-write - - - value0 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - 0 - - - value1 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - 0x1 - - - - - - - ANACTRL_CLR - USB PHY Analog Control Register - 0x108 - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - LVI_EN - Vow voltage detector enable bit. - 1 - 1 - read-write - - - PFD_CLK_SEL - For normal USB operation, this bit field must remain at value 2'b00. - 2 - 2 - read-write - - - DEV_PULLDOWN - Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins - 10 - 1 - read-write - - - value0 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - 0 - - - value1 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - 0x1 - - - - - - - ANACTRL_TOG - USB PHY Analog Control Register - 0x10C - 32 - read-write - 0xA000402 - 0xFFFFFFFF - - - LVI_EN - Vow voltage detector enable bit. - 1 - 1 - read-write - - - PFD_CLK_SEL - For normal USB operation, this bit field must remain at value 2'b00. - 2 - 2 - read-write - - - DEV_PULLDOWN - Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins - 10 - 1 - read-write - - - value0 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - 0 - - - value1 - The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - 0x1 - - - - - - - - - RNG - RNG - RNG - 0x4003A000 - - 0 - 0x1000 - registers - - - - RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read - 0 - 32 - read-only - 0 - 0xFFFFFFFF - - - RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read. - 0 - 32 - read-only - - - - - COUNTER_VAL - no description available - 0x8 - 32 - read-write - 0 - 0x1FFF - - - CLK_RATIO - Gives the ratio between the internal clocks frequencies and the register clock frequency for evaluation and certification purposes. - 0 - 8 - read-only - - - REFRESH_CNT - Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER. - 8 - 5 - read-only - - - - - COUNTER_CFG - no description available - 0xC - 32 - read-write - 0 - 0x3FF - - - MODE - 00: disabled 01: update once. - 0 - 2 - read-write - - - CLOCK_SEL - Selects the internal clock on which to compute statistics. - 2 - 3 - read-write - - - SHIFT4X - To be used to add precision to clock_ratio and determine 'entropy refill'. - 5 - 3 - read-write - - - - - ONLINE_TEST_CFG - no description available - 0x10 - 32 - read-write - 0 - 0x7 - - - ACTIVATE - 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER. - 0 - 1 - read-write - - - DATA_SEL - Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10: RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this field. - 1 - 2 - read-write - - - - - ONLINE_TEST_VAL - no description available - 0x14 - 32 - read-write - 0 - 0xFFF - - - LIVE_CHI_SQUARED - This value is updated as described in field 'activate'. - 0 - 4 - read-only - - - MIN_CHI_SQUARED - This field is reset when 'activate'==0. - 4 - 4 - read-only - - - MAX_CHI_SQUARED - This field is reset when 'activate'==0. - 8 - 4 - read-only - - - - - MODULEID - IP identifier - 0xFFC - 32 - read-only - 0xA0B83200 - 0xFFFFFFFF - - - APERTURE - Aperture i. - 0 - 8 - read-only - - - MIN_REV - Minor revision i. - 8 - 4 - read-only - - - MAJ_REV - Major revision i. - 12 - 4 - read-only - - - ID - Identifier. - 16 - 16 - read-only - - - - - - - PUF - PUFCTRL - PUF - 0x4003B000 - - 0 - 0x260 - registers - - - PUF - 56 - - - - CTRL - PUF Control register - 0 - 32 - read-write - 0 - 0x5F - - - zeroize - Begin Zeroize operation for PUF and go to Error state - 0 - 1 - read-write - - - enroll - Begin Enroll operation - 1 - 1 - read-write - - - start - Begin Start operation - 2 - 1 - read-write - - - GENERATEKEY - Begin Set Intrinsic Key operation - 3 - 1 - read-write - - - SETKEY - Begin Set User Key operation - 4 - 1 - read-write - - - GETKEY - Begin Get Key operation - 6 - 1 - read-write - - - - - KEYINDEX - PUF Key Index register - 0x4 - 32 - read-write - 0 - 0xF - - - KEYIDX - Key index for Set Key operations - 0 - 4 - read-write - - - - - KEYSIZE - PUF Key Size register - 0x8 - 32 - read-write - 0 - 0x3F - - - KEYSIZE - Key size for Set Key operations - 0 - 6 - read-write - - - - - STAT - PUF Status register - 0x20 - 32 - read-write - 0x1 - 0xF7 - - - busy - Indicates that operation is in progress - 0 - 1 - read-only - - - SUCCESS - Last operation was successful - 1 - 1 - read-only - - - error - PUF is in the Error state and no operations can be performed - 2 - 1 - read-only - - - KEYINREQ - Request for next part of key - 4 - 1 - read-only - - - KEYOUTAVAIL - Next part of key is available - 5 - 1 - read-only - - - CODEINREQ - Request for next part of AC/KC - 6 - 1 - read-only - - - CODEOUTAVAIL - Next part of AC/KC is available - 7 - 1 - read-only - - - - - ALLOW - PUF Allow register - 0x28 - 32 - read-write - 0 - 0x8F - - - ALLOWENROLL - Enroll operation is allowed - 0 - 1 - read-only - - - ALLOWSTART - Start operation is allowed - 1 - 1 - read-only - - - ALLOWSETKEY - Set Key operations are allowed - 2 - 1 - read-only - - - ALLOWGETKEY - Get Key operation is allowed - 3 - 1 - read-only - - - - - KEYINPUT - PUF Key Input register - 0x40 - 32 - write-only - 0 - 0xFFFFFFFF - - - KEYIN - Key input data - 0 - 32 - write-only - - - - - CODEINPUT - PUF Code Input register - 0x44 - 32 - write-only - 0 - 0xFFFFFFFF - - - CODEIN - AC/KC input data - 0 - 32 - write-only - - - - - CODEOUTPUT - PUF Code Output register - 0x48 - 32 - read-only - 0 - 0xFFFFFFFF - - - CODEOUT - AC/KC output data - 0 - 32 - read-only - - - - - KEYOUTINDEX - PUF Key Output Index register - 0x60 - 32 - read-write - 0 - 0xF - - - KEYOUTIDX - Key index for the key that is currently output via the Key Output register - 0 - 4 - read-only - - - - - KEYOUTPUT - PUF Key Output register - 0x64 - 32 - read-only - 0 - 0xFFFFFFFF - - - KEYOUT - Key output data - 0 - 32 - read-only - - - - - IFSTAT - PUF Interface Status and clear register - 0xDC - 32 - read-write - 0 - 0x1 - - - ERROR - Indicates that an APB error has occurred,Writing logic1 clears the if_error bit - 0 - 1 - read-write - - - - - VERSION - PUF version register. - 0xFC - 32 - read-only - 0 - 0xFFFFFFFF - - - VERSION - Version of the PUF module. - 0 - 32 - read-only - - - - - INTEN - PUF Interrupt Enable - 0x100 - 32 - read-write - 0 - 0xF7 - - - READYEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - 0 - 1 - read-write - - - SUCCESEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - 1 - 1 - read-write - - - ERROREN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - 2 - 1 - read-write - - - KEYINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - 4 - 1 - read-write - - - KEYOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - 5 - 1 - read-write - - - CODEINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - 6 - 1 - read-write - - - CODEOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) - 7 - 1 - read-write - - - - - INTSTAT - PUF interrupt status - 0x104 - 32 - read-write - 0 - 0xF7 - - - READY - Triggers on falling edge of busy, write 1 to clear - 0 - 1 - read-write - - - SUCCESS - Level sensitive interrupt, cleared when interrupt source clears - 1 - 1 - read-write - - - ERROR - Level sensitive interrupt, cleared when interrupt source clears - 2 - 1 - read-write - - - KEYINREQ - Level sensitive interrupt, cleared when interrupt source clears - 4 - 1 - read-write - - - KEYOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears - 5 - 1 - read-write - - - CODEINREQ - Level sensitive interrupt, cleared when interrupt source clears - 6 - 1 - read-write - - - CODEOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears - 7 - 1 - read-write - - - - - PWRCTRL - PUF RAM Power Control - 0x108 - 32 - read-write - 0xF8 - 0xFD - - - RAMON - Power on the PUF RAM. - 0 - 1 - read-write - - - RAMSTAT - PUF RAM status. - 1 - 1 - read-write - - - - - CFG - PUF config register for block bits - 0x10C - 32 - read-write - 0 - 0x3 - - - BLOCKENROLL_SETKEY - Block enroll operation. Write 1 to set, cleared on reset. - 0 - 1 - read-write - - - BLOCKKEYOUTPUT - Block set key operation. Write 1 to set, cleared on reset. - 1 - 1 - read-write - - - - - KEYLOCK - Only reset in case of full IC reset - 0x200 - 32 - read-write - 0xAA - 0xFF - - - KEY0 - "10:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is allowed. 00, 01, 11:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." - 0 - 2 - read-write - - - KEY1 - "10:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is allowed. 00, 01, 11:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." - 2 - 2 - read-write - - - KEY2 - "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." - 4 - 2 - read-write - - - KEY3 - "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." - 6 - 2 - read-write - - - - - KEYENABLE - no description available - 0x204 - 32 - read-write - 0x55 - 0xFF - - - KEY0 - "10: Data coming out from PUF Index 0 interface are shifted in KEY0 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY0 register." - 0 - 2 - read-write - - - KEY1 - "10: Data coming out from PUF Index 0 interface are shifted in KEY1 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY1 register." - 2 - 2 - read-write - - - KEY2 - "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY2 register." - 4 - 2 - read-write - - - KEY3 - "10: Data coming out from PUF Index 0 interface are shifted in KEY3 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." - 6 - 2 - read-write - - - - - KEYRESET - Reinitialize Keys shift registers counters - 0x208 - 32 - write-only - 0 - 0xFFFFFFFF - - - KEY0 - 10: Reset KEY0 shift register. Self clearing. Must be done before loading any new key. - 0 - 2 - write-only - - - KEY1 - 10: Reset KEY1 shift register. Self clearing. Must be done before loading any new key. - 2 - 2 - write-only - - - KEY2 - 10: Reset KEY2 shift register. Self clearing. Must be done before loading any new key. - 4 - 2 - write-only - - - KEY3 - 10: Reset KEY3 shift register. Self clearing. Must be done before loading any new key. - 6 - 2 - write-only - - - - - IDXBLK_L - no description available - 0x20C - 32 - read-write - 0x8000AAAA - 0xC000FFFF - - - IDX1 - Use to block PUF index 1 - 2 - 2 - read-write - - - IDX2 - Use to block PUF index 2 - 4 - 2 - read-write - - - IDX3 - Use to block PUF index 3 - 6 - 2 - read-write - - - IDX4 - Use to block PUF index 4 - 8 - 2 - read-write - - - IDX5 - Use to block PUF index 5 - 10 - 2 - read-write - - - IDX6 - Use to block PUF index 6 - 12 - 2 - read-write - - - IDX7 - Use to block PUF index 7 - 14 - 2 - read-write - - - LOCK_IDX - Lock 0 to 7 PUF key indexes - 30 - 2 - write-only - - - - - IDXBLK_H_DP - no description available - 0x210 - 32 - read-write - 0xAAAA - 0xFFFFFFFF - - - IDX8 - Use to block PUF index 8 - 0 - 2 - read-write - - - IDX9 - Use to block PUF index 9 - 2 - 2 - read-write - - - IDX10 - Use to block PUF index 10 - 4 - 2 - read-write - - - IDX11 - Use to block PUF index 11 - 6 - 2 - read-write - - - IDX12 - Use to block PUF index 12 - 8 - 2 - read-write - - - IDX13 - Use to block PUF index 13 - 10 - 2 - read-write - - - IDX14 - Use to block PUF index 14 - 12 - 2 - read-write - - - IDX15 - Use to block PUF index 15 - 14 - 2 - read-write - - - - - 4 - 0x4 - KEYMASK[%s] - Only reset in case of full IC reset - 0x214 - 32 - write-only - 0 - 0xFFFFFFFF - - - KEYMASK - no description available - 0 - 32 - write-only - - - - - IDXBLK_H - no description available - 0x254 - 32 - read-write - 0x8000AAAA - 0xC000FFFF - - - IDX8 - Use to block PUF index 8 - 0 - 2 - read-write - - - IDX9 - Use to block PUF index 9 - 2 - 2 - read-write - - - IDX10 - Use to block PUF index 10 - 4 - 2 - read-write - - - IDX11 - Use to block PUF index 11 - 6 - 2 - read-write - - - IDX12 - Use to block PUF index 12 - 8 - 2 - read-write - - - IDX13 - Use to block PUF index 13 - 10 - 2 - read-write - - - IDX14 - Use to block PUF index 14 - 12 - 2 - read-write - - - IDX15 - Use to block PUF index 15 - 14 - 2 - read-write - - - LOCK_IDX - Lock 8 to 15 PUF key indexes - 30 - 2 - write-only - - - - - IDXBLK_L_DP - no description available - 0x258 - 32 - read-write - 0xAAAA - 0xFFFF - - - IDX1 - Use to block PUF index 1 - 2 - 2 - read-write - - - IDX2 - Use to block PUF index 2 - 4 - 2 - read-write - - - IDX3 - Use to block PUF index 3 - 6 - 2 - read-write - - - IDX4 - Use to block PUF index 4 - 8 - 2 - read-write - - - IDX5 - Use to block PUF index 5 - 10 - 2 - read-write - - - IDX6 - Use to block PUF index 6 - 12 - 2 - read-write - - - IDX7 - Use to block PUF index 7 - 14 - 2 - read-write - - - - - SHIFT_STATUS - no description available - 0x25C - 32 - read-write - 0 - 0xFFFF - - - KEY0 - Index counter from key 0 shift register - 0 - 4 - read-only - - - KEY1 - Index counter from key 1 shift register - 4 - 4 - read-only - - - KEY2 - Index counter from key 2 shift register - 8 - 4 - read-only - - - KEY3 - Index counter from key 3 shift register - 12 - 4 - read-only - - - - - - - PLU - LPC80X Programmable Logic Unit (PLU) - PLU - 0x4003D000 - - 0 - 0xC20 - registers - - - PLU - 52 - - - - 26 - 0x20 - LUT[%s] - no description available - 0 - - 5 - 0x4 - 0,1,2,3,4 - LUT_INP_MUX%s - LUTn input x MUX - 0 - 32 - read-write - 0 - 0x3F - - - LUTn_INPx - Selects the input source to be connected to LUT0 input0. For each LUT, the slot associated with the output from LUTn itself is tied low. - 0 - 6 - read-write - - - plu_inputs0 - The PLU primary inputs 0. - 0 - - - plu_inputs1 - The PLU primary inputs 1. - 0x1 - - - plu_inputs2 - The PLU primary inputs 2. - 0x2 - - - plu_inputs3 - The PLU primary inputs 3. - 0x3 - - - plu_inputs4 - The PLU primary inputs 4. - 0x4 - - - plu_inputs5 - The PLU primary inputs 5. - 0x5 - - - lut_outputs0 - The output of LUT0. - 0x6 - - - lut_outputs1 - The output of LUT1. - 0x7 - - - lut_outputs2 - The output of LUT2. - 0x8 - - - lut_outputs3 - The output of LUT3. - 0x9 - - - lut_outputs4 - The output of LUT4. - 0xA - - - lut_outputs5 - The output of LUT5. - 0xB - - - lut_outputs6 - The output of LUT6. - 0xC - - - lut_outputs7 - The output of LUT7. - 0xD - - - lut_outputs8 - The output of LUT8. - 0xE - - - lut_outputs9 - The output of LUT9. - 0xF - - - lut_outputs10 - The output of LUT10. - 0x10 - - - lut_outputs11 - The output of LUT11. - 0x11 - - - lut_outputs12 - The output of LUT12. - 0x12 - - - lut_outputs13 - The output of LUT13. - 0x13 - - - lut_outputs14 - The output of LUT14. - 0x14 - - - lut_outputs15 - The output of LUT15. - 0x15 - - - lut_outputs16 - The output of LUT16. - 0x16 - - - lut_outputs17 - The output of LUT17. - 0x17 - - - lut_outputs18 - The output of LUT18. - 0x18 - - - lut_outputs19 - The output of LUT19. - 0x19 - - - lut_outputs20 - The output of LUT20. - 0x1A - - - lut_outputs21 - The output of LUT21. - 0x1B - - - lut_outputs22 - The output of LUT22. - 0x1C - - - lut_outputs23 - The output of LUT23. - 0x1D - - - lut_outputs24 - The output of LUT24. - 0x1E - - - lut_outputs25 - The output of LUT25. - 0x1F - - - state0 - state(0). - 0x20 - - - state1 - state(1). - 0x21 - - - state2 - state(2). - 0x22 - - - state3 - state(3). - 0x23 - - - - - - - - 26 - 0x4 - LUT_TRUTH[%s] - Specifies the Truth Table contents for LUTLUTn - 0x800 - 32 - read-write - 0 - 0xFFFFFFFF - - - LUTn_TRUTH - Specifies the Truth Table contents for LUT0.. - 0 - 32 - read-write - - - - - OUTPUTS - Provides the current state of the 8 designated PLU Outputs. - 0x900 - 32 - read-write - 0 - 0xFFFFFFFF - - - OUTPUT_STATE - Provides the current state of the 8 designated PLU Outputs.. - 0 - 8 - read-only - - - - - WAKEINT_CTRL - Wakeup interrupt control for PLU - 0x904 - 32 - read-write - 0 - 0xFFFFFFFF - - - MASK - Interrupt mask (which of the 8 PLU Outputs contribute to interrupt) - 0 - 8 - read-write - - - FILTER_MODE - control input of the PLU, add filtering for glitch. - 8 - 2 - read-write - - - BYPASS - Bypass mode. - 0 - - - FILTER1CLK - Filter 1 clock period. - 0x1 - - - FILTER2CLK - Filter 2 clock period. - 0x2 - - - FILTER3CLK - Filter 3 clock period. - 0x3 - - - - - FILTER_CLKSEL - hclk is divided by 2**filter_clksel. - 10 - 2 - read-write - - - FRO1MHZ - Selects the 1 MHz low-power oscillator as the filter clock. - 0 - - - FRO12MHZ - Selects the 12 Mhz FRO as the filter clock. - 0x1 - - - OTHER_CLOCK - Selects a third filter clock source, if provided. - 0x2 - - - - - LATCH_ENABLE - latch the interrupt , then can be cleared with next bit INTR_CLEAR - 12 - 1 - read-write - - - INTR_CLEAR - Write to clear wakeint_latched - 13 - 1 - read-write - oneToClear - - - - - 8 - 0x4 - OUTPUT_MUX[%s] - Selects the source to be connected to PLU Output OUTPUT_n - 0xC00 - 32 - read-write - 0 - 0xFFFFFFFF - - - OUTPUTn - Selects the source to be connected to PLU Output 0. - 0 - 5 - read-write - - - plu_output0 - The PLU output 0. - 0 - - - plu_output1 - The PLU output 1. - 0x1 - - - plu_output2 - The PLU output 2. - 0x2 - - - plu_output3 - The PLU output 3. - 0x3 - - - plu_output4 - The PLU output 4. - 0x4 - - - plu_output5 - The PLU output 5. - 0x5 - - - plu_output6 - The PLU output 6. - 0x6 - - - plu_output7 - The PLU output 7. - 0x7 - - - plu_output8 - The PLU output 8. - 0x8 - - - plu_output9 - The PLU output 9. - 0x9 - - - plu_output10 - The PLU output 10. - 0xA - - - plu_output11 - The PLU output 11. - 0xB - - - plu_output12 - The PLU output 12. - 0xC - - - plu_output13 - The PLU output 13. - 0xD - - - plu_output14 - The PLU output 14. - 0xE - - - plu_output15 - The PLU output 15. - 0xF - - - plu_output16 - The PLU output 16. - 0x10 - - - plu_output17 - The PLU output 17. - 0x11 - - - plu_output18 - The PLU output 18. - 0x12 - - - plu_output19 - The PLU output 19. - 0x13 - - - plu_output20 - The PLU output 20. - 0x14 - - - plu_output21 - The PLU output 21. - 0x15 - - - plu_output22 - The PLU output 22. - 0x16 - - - plu_output23 - The PLU output 23. - 0x17 - - - plu_output24 - The PLU output 24. - 0x18 - - - plu_output25 - The PLU output 25. - 0x19 - - - state0 - state(0). - 0x1A - - - state1 - state(1). - 0x1B - - - state2 - state(2). - 0x1C - - - state3 - state(3). - 0x1D - - - - - - - - - DMA0 - DMA controller - DMA - DMA - 0x40082000 - - 0 - 0x56C - registers - - - DMA0 - 1 - - - - CTRL - DMA control. - 0 - 32 - read-write - 0 - 0x1 - - - ENABLE - DMA controller master enable. - 0 - 1 - read-write - - - DISABLED - Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled. - 0 - - - ENABLED - Enabled. The DMA controller is enabled. - 0x1 - - - - - - - INTSTAT - Interrupt status. - 0x4 - 32 - read-only - 0 - 0x6 - - - ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. - 1 - 1 - read-only - - - NOT_PENDING - Not pending. No enabled interrupts are pending. - 0 - - - PENDING - Pending. At least one enabled interrupt is pending. - 0x1 - - - - - ACTIVEERRINT - Summarizes whether any error interrupts are pending. - 2 - 1 - read-only - - - NOT_PENDING - Not pending. No error interrupts are pending. - 0 - - - PENDING - Pending. At least one error interrupt is pending. - 0x1 - - - - - - - SRAMBASE - SRAM address of the channel configuration table. - 0x8 - 32 - read-write - 0 - 0xFFFFFE00 - - - OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the table must begin on a 512 byte boundary. - 9 - 23 - read-write - - - - - ENABLESET0 - Channel Enable read and Set for all DMA channels. - 0x20 - 32 - read-write - 0 - 0xFFFFFFFF - - - ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. - 0 - 32 - read-write - - - - - ENABLECLR0 - Channel Enable Clear for all DMA channels. - 0x28 - 32 - write-only - 0 - 0 - - - CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved. - 0 - 32 - write-only - - - - - ACTIVE0 - Channel Active status for all DMA channels. - 0x30 - 32 - read-only - 0 - 0xFFFFFFFF - - - ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. - 0 - 32 - read-only - - - - - BUSY0 - Channel Busy status for all DMA channels. - 0x38 - 32 - read-only - 0 - 0xFFFFFFFF - - - BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. - 0 - 32 - read-only - - - - - ERRINT0 - Error Interrupt status for all DMA channels. - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active. - 0 - 32 - read-write - - - - - INTENSET0 - Interrupt Enable read and Set for all DMA channels. - 0x48 - 32 - read-write - 0 - 0xFFFFFFFF - - - INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. - 0 - 32 - read-write - - - - - INTENCLR0 - Interrupt Enable Clear for all DMA channels. - 0x50 - 32 - write-only - 0 - 0 - - - CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. - 0 - 32 - write-only - - - - - INTA0 - Interrupt A status for all DMA channels. - 0x58 - 32 - read-write - 0 - 0xFFFFFFFF - - - IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. - 0 - 32 - read-write - - - - - INTB0 - Interrupt B status for all DMA channels. - 0x60 - 32 - read-write - 0 - 0xFFFFFFFF - - - IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. - 0 - 32 - read-write - - - - - SETVALID0 - Set ValidPending control bits for all DMA channels. - 0x68 - 32 - write-only - 0 - 0 - - - SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n - 0 - 32 - write-only - - - - - SETTRIG0 - Set Trigger control bits for all DMA channels. - 0x70 - 32 - write-only - 0 - 0 - - - TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. - 0 - 32 - write-only - - - - - ABORT0 - Channel Abort control for all DMA channels. - 0x78 - 32 - write-only - 0 - 0 - - - ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. - 0 - 32 - write-only - - - - - 23 - 0x10 - CHANNEL[%s] - no description available - 0x400 - - CFG - Configuration register for DMA channel . - 0 - 32 - read-write - 0 - 0x7CF73 - - - PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. - 0 - 1 - read-write - - - DISABLED - Disabled. Peripheral DMA requests are disabled. - 0 - - - ENABLED - Enabled. Peripheral DMA requests are enabled. - 0x1 - - - - - HWTRIGEN - Hardware Triggering Enable for this channel. - 1 - 1 - read-write - - - DISABLED - Disabled. Hardware triggering is not used. - 0 - - - ENABLED - Enabled. Use hardware triggering. - 0x1 - - - - - TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. - 4 - 1 - read-write - - - ACTIVE_LOW_FALLING - Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. - 0 - - - ACTIVE_HIGH_RISING - Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. - 0x1 - - - - - TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. - 5 - 1 - read-write - - - EDGE - Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. - 0 - - - LEVEL - Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. - 0x1 - - - - - TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. - 6 - 1 - read-write - - - SINGLE - Single transfer. Hardware trigger causes a single transfer. - 0 - - - BURST - Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. - 0x1 - - - - - BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. - 8 - 4 - read-write - - - SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. - 14 - 1 - read-write - - - DISABLED - Disabled. Source burst wrapping is not enabled for this DMA channel. - 0 - - - ENABLED - Enabled. Source burst wrapping is enabled for this DMA channel. - 0x1 - - - - - DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. - 15 - 1 - read-write - - - DISABLED - Disabled. Destination burst wrapping is not enabled for this DMA channel. - 0 - - - ENABLED - Enabled. Destination burst wrapping is enabled for this DMA channel. - 0x1 - - - - - CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. - 16 - 3 - read-write - - - - - CTLSTAT - Control and status register for DMA channel . - 0x4 - 32 - read-only - 0 - 0x5 - - - VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. - 0 - 1 - read-only - - - NO_EFFECT - No effect. No effect on DMA operation. - 0 - - - VALID_PENDING - Valid pending. - 0x1 - - - - - TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. - 2 - 1 - read-only - - - NOT_TRIGGERED - Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. - 0 - - - TRIGGERED - Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. - 0x1 - - - - - - - XFERCFG - Transfer configuration register for DMA channel . - 0x8 - 32 - read-write - 0 - 0x3FFF33F - - - CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. - 0 - 1 - read-write - - - NOT_VALID - Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. - 0 - - - VALID - Valid. The current channel descriptor is considered valid. - 0x1 - - - - - RELOAD - Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. - 1 - 1 - read-write - - - DISABLED - Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. - 0 - - - ENABLED - Enabled. Reload the channels' control structure when the current descriptor is exhausted. - 0x1 - - - - - SWTRIG - Software Trigger. - 2 - 1 - read-write - - - NOT_SET - Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. - 0 - - - SET - Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. - 0x1 - - - - - CLRTRIG - Clear Trigger. - 3 - 1 - read-write - - - NOT_CLEARED - Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. - 0 - - - CLEARED - Cleared. The trigger is cleared when this descriptor is exhausted - 0x1 - - - - - SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. - 4 - 1 - read-write - - - NO_EFFECT - No effect. - 0 - - - SET - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. - 0x1 - - - - - SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. - 5 - 1 - read-write - - - NO_EFFECT - No effect. - 0 - - - SET - Set. The INTB flag for this channel will be set when the current descriptor is exhausted. - 0x1 - - - - - WIDTH - Transfer width used for this DMA channel. - 8 - 2 - read-write - - - BIT_8 - 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). - 0 - - - BIT_16 - 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). - 0x1 - - - BIT_32 - 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). - 0x2 - - - - - SRCINC - Determines whether the source address is incremented for each DMA transfer. - 12 - 2 - read-write - - - NO_INCREMENT - No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. - 0 - - - WIDTH_X_1 - 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. - 0x1 - - - WIDTH_X_2 - 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. - 0x2 - - - WIDTH_X_4 - 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. - 0x3 - - - - - DSTINC - Determines whether the destination address is incremented for each DMA transfer. - 14 - 2 - read-write - - - NO_INCREMENT - No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. - 0 - - - WIDTH_X_1 - 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. - 0x1 - - - WIDTH_X_2 - 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. - 0x2 - - - WIDTH_X_4 - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. - 0x3 - - - - - XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. - 16 - 10 - read-write - - - - - - - - DMA1 - DMA controller - DMA - 0x400A7000 - - 0 - 0x49C - registers - - - DMA1 - 58 - - - - USB0 - USB 2.0 Device Controller - USB - 0x40084000 - - 0 - 0x38 - registers - - - USB0_NEEDCLK - 27 - - - USB0 - 28 - - - - DEVCMDSTAT - USB Device Command/Status register - 0 - 32 - read-write - 0x800 - 0x171BFBFF - - - DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request. - 0 - 7 - read-write - - - DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. - 7 - 1 - read-write - - - SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. - 8 - 1 - read-write - - - FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: - 9 - 1 - read-write - - - NORMAL - USB_NEEDCLK has normal function. - 0 - - - ALWAYS_ON - USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. - 0x1 - - - - - LPM_SUP - LPM Supported: - 11 - 1 - read-write - - - NO - LPM not supported. - 0 - - - YES - LPM supported. - 0x1 - - - - - INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP - 12 - 1 - read-write - - - DISABLED - Only acknowledged packets generate an interrupt - 0 - - - ENABLED - Both acknowledged and NAKed packets generate interrupts. - 0x1 - - - - - INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP - 13 - 1 - read-write - - - DISABLED - Only acknowledged packets generate an interrupt - 0 - - - ENABLED - Both acknowledged and NAKed packets generate interrupts. - 0x1 - - - - - INTONNAK_CO - Interrupt on NAK for control OUT EP - 14 - 1 - read-write - - - DISABLED - Only acknowledged packets generate an interrupt - 0 - - - ENABLED - Both acknowledged and NAKed packets generate interrupts. - 0x1 - - - - - INTONNAK_CI - Interrupt on NAK for control IN EP - 15 - 1 - read-write - - - DISABLED - Only acknowledged packets generate an interrupt - 0 - - - ENABLED - Both acknowledged and NAKed packets generate interrupts. - 0x1 - - - - - DCON - Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VBUSDEBOUNCED bit is one. - 16 - 1 - read-write - - - DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect. - 17 - 1 - read-write - - - LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one. - 19 - 1 - read-write - - - LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction. - 20 - 1 - read-only - - - DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. - 24 - 1 - read-write - - - DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on its upstream port. The bit is reset by writing a one to it. - 25 - 1 - read-write - - - DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it. - 26 - 1 - read-write - - - VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. - 28 - 1 - read-only - - - - - INFO - USB Info register - 0x4 - 32 - read-write - 0 - 0x7FFF - - - FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device. - 0 - 11 - read-only - - - ERR_CODE - The error code which last occurred: - 11 - 4 - read-write - - - NO_ERROR - No error - 0 - - - PID_ENCODING_ERROR - PID encoding error - 0x1 - - - PID_UNKNOWN - PID unknown - 0x2 - - - PACKET_UNEXPECTED - Packet unexpected - 0x3 - - - TOKEN_CRC_ERROR - Token CRC error - 0x4 - - - DATA_CRC_ERROR - Data CRC error - 0x5 - - - TIMEOUT - Time out - 0x6 - - - BABBLE - Babble - 0x7 - - - TRUNCATED_EOP - Truncated EOP - 0x8 - - - SENT_RECEIVED_NAK - Sent/Received NAK - 0x9 - - - SENT_STALL - Sent Stall - 0xA - - - OVERRUN - Overrun - 0xB - - - SENT_EMPTY_PACKET - Sent empty packet - 0xC - - - BITSTUFF_ERROR - Bitstuff error - 0xD - - - SYNC_ERROR - Sync error - 0xE - - - WRONG_DATA_TOGGLE - Wrong data toggle - 0xF - - - - - MINREV - Minor Revision. - 16 - 8 - read-only - - - MAJREV - Major Revision. - 24 - 8 - read-only - - - - - EPLISTSTART - USB EP Command/Status List start address - 0x8 - 32 - read-write - 0 - 0xFFFFFF00 - - - EP_LIST - Start address of the USB EP Command/Status List. - 8 - 24 - read-write - - - - - DATABUFSTART - USB Data buffer start address - 0xC - 32 - read-write - 0 - 0xFFC00000 - - - DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located. - 22 - 10 - read-write - - - - - LPM - USB Link Power Management register - 0x10 - 32 - read-write - 0 - 0x1FF - - - HIRD_HW - Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token - 0 - 4 - read-only - - - HIRD_SW - Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. - 4 - 4 - read-write - - - DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1. - 8 - 1 - read-write - - - - - EPSKIP - USB Endpoint skip - 0x14 - 32 - read-write - 0 - 0x3FFFFFFF - - - SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. - 0 - 10 - read-write - - - - - EPINUSE - USB Endpoint Buffer in use - 0x18 - 32 - read-write - 0 - 0x3FC - - - BUF - Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 0. 1: HW is accessing buffer 1. - 2 - 8 - read-write - - - - - EPBUFCFG - USB Endpoint Buffer Configuration register - 0x1C - 32 - read-write - 0 - 0x3FC - - - BUF_SB - Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer. - 2 - 8 - read-write - - - - - INTSTAT - USB interrupt status register - 0x20 - 32 - read-write - 0 - 0xC00003FF - - - EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it. - 0 - 1 - read-write - - - EP0IN - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it. - 1 - 1 - read-write - - - EP1OUT - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it. - 2 - 1 - read-write - - - EP1IN - Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it. - 3 - 1 - read-write - - - EP2OUT - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it. - 4 - 1 - read-write - - - EP2IN - Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it. - 5 - 1 - read-write - - - EP3OUT - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it. - 6 - 1 - read-write - - - EP3IN - Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it. - 7 - 1 - read-write - - - EP4OUT - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it. - 8 - 1 - read-write - - - EP4IN - Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it. - 9 - 1 - read-write - - - FRAME_INT - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it. - 30 - 1 - read-write - - - DEV_INT - Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it. - 31 - 1 - read-write - - - - - INTEN - USB interrupt enable register - 0x24 - 32 - read-write - 0 - 0xC00003FF - - - EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. - 0 - 10 - read-write - - - FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. - 30 - 1 - read-write - - - DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. - 31 - 1 - read-write - - - - - INTSETSTAT - USB set interrupt status register - 0x28 - 32 - read-write - 0 - 0xC00003FF - - - EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. - 0 - 10 - read-write - - - FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. - 30 - 1 - read-write - - - DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. - 31 - 1 - read-write - - - - - EPTOGGLE - USB Endpoint toggle register - 0x34 - 32 - read-write - 0 - 0x3FF - - - TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. - 0 - 10 - read-write - - - - - - - SCT0 - SCTimer/PWM (SCT) - SCT - 0x40085000 - - 0 - 0x550 - registers - - - SCT0 - 12 - - - - CONFIG - SCT configuration register - 0 - 32 - read-write - 0x1E00 - 0x61FFF - - - UNIFY - SCT operation - 0 - 1 - read-write - - - DUAL_COUNTER - The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. - 0 - - - UNIFIED_COUNTER - The SCT operates as a unified 32-bit counter. - 0x1 - - - - - CLKMODE - SCT clock mode - 1 - 2 - read-write - - - SYSTEM_CLOCK_MODE - System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. - 0 - - - SAMPLED_SYSTEM_CLOCK_MODE - Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode. - 0x1 - - - SCT_INPUT_CLOCK_MODE - SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. - 0x2 - - - ASYNCHRONOUS_MODE - Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock. - 0x3 - - - - - CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register. - 3 - 4 - read-write - - - INPUT_0_RISING_EDGES - Rising edges on input 0. - 0 - - - INPUT_0_FALLING_EDGE - Falling edges on input 0. - 0x1 - - - INPUT_1_RISING_EDGES - Rising edges on input 1. - 0x2 - - - INPUT_1_FALLING_EDGE - Falling edges on input 1. - 0x3 - - - INPUT_2_RISING_EDGES - Rising edges on input 2. - 0x4 - - - INPUT_2_FALLING_EDGE - Falling edges on input 2. - 0x5 - - - INPUT_3_RISING_EDGES - Rising edges on input 3. - 0x6 - - - INPUT_3_FALLING_EDGE - Falling edges on input 3. - 0x7 - - - INPUT_4_RISING_EDGES - Rising edges on input 4. - 0x8 - - - INPUT_4_FALLING_EDGE - Falling edges on input 4. - 0x9 - - - INPUT_5_RISING_EDGES - Rising edges on input 5. - 0xA - - - INPUT_5_FALLING_EDGE - Falling edges on input 5. - 0xB - - - INPUT_6_RISING_EDGES - Rising edges on input 6. - 0xC - - - INPUT_6_FALLING_EDGE - Falling edges on input 6. - 0xD - - - INPUT_7_RISING_EDGES - Rising edges on input 7. - 0xE - - - INPUT_7_FALLING_EDGE - Falling edges on input 7. - 0xF - - - - - NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. - 7 - 1 - read-write - - - NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. - 8 - 1 - read-write - - - INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field. - 9 - 4 - read-write - - - AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. - 17 - 1 - read-write - - - AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. - 18 - 1 - read-write - - - - - CTRL - SCT control register - 0x4 - 32 - read-write - 0x40004 - 0x1FFF1FFF - - - DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. - 0 - 1 - read-write - - - STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes. - 1 - 1 - read-write - - - HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset. - 2 - 1 - read-write - - - CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. - 3 - 1 - read-write - - - BIDIR_L - L or unified counter direction select - 4 - 1 - read-write - - - UP - Up. The counter counts up to a limit condition, then is cleared to zero. - 0 - - - UP_DOWN - Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. - 0x1 - - - - - PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - 5 - 8 - read-write - - - DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. - 16 - 1 - read-write - - - STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. - 17 - 1 - read-write - - - HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset. - 18 - 1 - read-write - - - CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. - 19 - 1 - read-write - - - BIDIR_H - Direction select - 20 - 1 - read-write - - - UP - The H counter counts up to its limit condition, then is cleared to zero. - 0 - - - UP_DOWN - The H counter counts up to its limit, then counts down to a limit condition or to 0. - 0x1 - - - - - PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. - 21 - 8 - read-write - - - - - LIMIT - SCT limit event select register - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - 16 - 16 - read-write - - - - - HALT - SCT halt event select register - 0xC - 32 - read-write - 0 - 0xFFFFFFFF - - - HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - 16 - 16 - read-write - - - - - STOP - SCT stop event select register - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - 16 - 16 - read-write - - - - - START - SCT start event select register - 0x14 - 32 - read-write - 0 - 0xFFFFFFFF - - - STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. - 16 - 16 - read-write - - - - - COUNT - SCT counter register - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter. - 0 - 16 - read-write - - - CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter. - 16 - 16 - read-write - - - - - STATE - SCT state register - 0x44 - 32 - read-write - 0 - 0x1F001F - - - STATE_L - State variable. - 0 - 5 - read-write - - - STATE_H - State variable. - 16 - 5 - read-write - - - - - INPUT - SCT input register - 0x48 - 32 - read-only - 0 - 0xFFFFFFFF - - - AIN0 - Input 0 state. Input 0 state on the last SCT clock edge. - 0 - 1 - read-only - - - AIN1 - Input 1 state. Input 1 state on the last SCT clock edge. - 1 - 1 - read-only - - - AIN2 - Input 2 state. Input 2 state on the last SCT clock edge. - 2 - 1 - read-only - - - AIN3 - Input 3 state. Input 3 state on the last SCT clock edge. - 3 - 1 - read-only - - - AIN4 - Input 4 state. Input 4 state on the last SCT clock edge. - 4 - 1 - read-only - - - AIN5 - Input 5 state. Input 5 state on the last SCT clock edge. - 5 - 1 - read-only - - - AIN6 - Input 6 state. Input 6 state on the last SCT clock edge. - 6 - 1 - read-only - - - AIN7 - Input 7 state. Input 7 state on the last SCT clock edge. - 7 - 1 - read-only - - - AIN8 - Input 8 state. Input 8 state on the last SCT clock edge. - 8 - 1 - read-only - - - AIN9 - Input 9 state. Input 9 state on the last SCT clock edge. - 9 - 1 - read-only - - - AIN10 - Input 10 state. Input 10 state on the last SCT clock edge. - 10 - 1 - read-only - - - AIN11 - Input 11 state. Input 11 state on the last SCT clock edge. - 11 - 1 - read-only - - - AIN12 - Input 12 state. Input 12 state on the last SCT clock edge. - 12 - 1 - read-only - - - AIN13 - Input 13 state. Input 13 state on the last SCT clock edge. - 13 - 1 - read-only - - - AIN14 - Input 14 state. Input 14 state on the last SCT clock edge. - 14 - 1 - read-only - - - AIN15 - Input 15 state. Input 15 state on the last SCT clock edge. - 15 - 1 - read-only - - - SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC. - 16 - 1 - read-only - - - SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC. - 17 - 1 - read-only - - - SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC. - 18 - 1 - read-only - - - SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC. - 19 - 1 - read-only - - - SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC. - 20 - 1 - read-only - - - SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC. - 21 - 1 - read-only - - - SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC. - 22 - 1 - read-only - - - SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC. - 23 - 1 - read-only - - - SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC. - 24 - 1 - read-only - - - SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC. - 25 - 1 - read-only - - - SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC. - 26 - 1 - read-only - - - SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC. - 27 - 1 - read-only - - - SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC. - 28 - 1 - read-only - - - SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC. - 29 - 1 - read-only - - - SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC. - 30 - 1 - read-only - - - SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC. - 31 - 1 - read-only - - - - - REGMODE - SCT match/capture mode register - 0x4C - 32 - read-write - 0 - 0xFFFFFFFF - - - REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match register. 1 = register operates as capture register. - 0 - 16 - read-write - - - REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match registers. 1 = register operates as capture registers. - 16 - 16 - read-write - - - - - OUTPUT - SCT output register - 0x50 - 32 - read-write - 0 - 0xFFFF - - - OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. - 0 - 16 - read-write - - - - - OUTPUTDIRCTRL - SCT output counter direction control register - 0x54 - 32 - read-write - 0 - 0xFFFFFFFF - - - SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. - 0 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. - 2 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. - 4 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. - 6 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. - 8 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. - 10 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. - 12 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. - 14 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. - 16 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. - 18 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. - 20 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. - 22 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. - 24 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. - 26 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. - 28 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. - 30 - 2 - read-write - - - INDEPENDENT - Set and clear do not depend on the direction of any counter. - 0 - - - L_REVERSED - Set and clear are reversed when counter L or the unified counter is counting down. - 0x1 - - - H_REVERSED - Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - 0x2 - - - - - - - RES - SCT conflict resolution register - 0x58 - 32 - read-write - 0 - 0xFFFFFFFF - - - O0RES - Effect of simultaneous set and clear on output 0. - 0 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR0 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O1RES - Effect of simultaneous set and clear on output 1. - 2 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR1 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O2RES - Effect of simultaneous set and clear on output 2. - 4 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output n (or set based on the SETCLR2 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O3RES - Effect of simultaneous set and clear on output 3. - 6 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR3 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O4RES - Effect of simultaneous set and clear on output 4. - 8 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR4 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O5RES - Effect of simultaneous set and clear on output 5. - 10 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR5 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O6RES - Effect of simultaneous set and clear on output 6. - 12 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR6 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O7RES - Effect of simultaneous set and clear on output 7. - 14 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output n (or set based on the SETCLR7 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O8RES - Effect of simultaneous set and clear on output 8. - 16 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR8 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O9RES - Effect of simultaneous set and clear on output 9. - 18 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR9 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O10RES - Effect of simultaneous set and clear on output 10. - 20 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR10 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O11RES - Effect of simultaneous set and clear on output 11. - 22 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR11 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O12RES - Effect of simultaneous set and clear on output 12. - 24 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR12 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O13RES - Effect of simultaneous set and clear on output 13. - 26 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR13 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O14RES - Effect of simultaneous set and clear on output 14. - 28 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR14 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - O15RES - Effect of simultaneous set and clear on output 15. - 30 - 2 - read-write - - - NO_CHANGE - No change. - 0 - - - SET - Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). - 0x1 - - - CLEAR - Clear output (or set based on the SETCLR15 field). - 0x2 - - - TOGGLE_OUTPUT - Toggle output. - 0x3 - - - - - - - DMAREQ0 - SCT DMA request 0 register - 0x5C - 32 - read-write - 0 - 0xC000FFFF - - - DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. - 30 - 1 - read-write - - - DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. - 31 - 1 - read-write - - - - - DMAREQ1 - SCT DMA request 1 register - 0x60 - 32 - read-write - 0 - 0xC000FFFF - - - DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. - 30 - 1 - read-write - - - DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. - 31 - 1 - read-write - - - - - EVEN - SCT event interrupt enable register - 0xF0 - 32 - read-write - 0 - 0xFFFF - - - IEN - The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - - - EVFLAG - SCT event flag register - 0xF4 - 32 - read-write - 0 - 0xFFFF - - - FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. - 0 - 16 - read-write - - - - - CONEN - SCT conflict interrupt enable register - 0xF8 - 32 - read-write - 0 - 0xFFFF - - - NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. - 0 - 16 - read-write - - - - - CONFLAG - SCT conflict flag register - 0xFC - 32 - read-write - 0 - 0xC000FFFF - - - NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. - 0 - 16 - read-write - - - BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful. - 30 - 1 - read-write - - - BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted. - 31 - 1 - read-write - - - - - CAP0 - SCT capture register of capture channel - CAP_MATCH - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH0 - SCT match value register of match channels - CAP_MATCH - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP1 - SCT capture register of capture channel - CAP_MATCH - 0x104 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH1 - SCT match value register of match channels - CAP_MATCH - 0x104 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP2 - SCT capture register of capture channel - CAP_MATCH - 0x108 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH2 - SCT match value register of match channels - CAP_MATCH - 0x108 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP3 - SCT capture register of capture channel - CAP_MATCH - 0x10C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH3 - SCT match value register of match channels - CAP_MATCH - 0x10C - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP4 - SCT capture register of capture channel - CAP_MATCH - 0x110 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH4 - SCT match value register of match channels - CAP_MATCH - 0x110 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP5 - SCT capture register of capture channel - CAP_MATCH - 0x114 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH5 - SCT match value register of match channels - CAP_MATCH - 0x114 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP6 - SCT capture register of capture channel - CAP_MATCH - 0x118 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH6 - SCT match value register of match channels - CAP_MATCH - 0x118 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP7 - SCT capture register of capture channel - CAP_MATCH - 0x11C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH7 - SCT match value register of match channels - CAP_MATCH - 0x11C - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP8 - SCT capture register of capture channel - CAP_MATCH - 0x120 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH8 - SCT match value register of match channels - CAP_MATCH - 0x120 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP9 - SCT capture register of capture channel - CAP_MATCH - 0x124 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH9 - SCT match value register of match channels - CAP_MATCH - 0x124 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP10 - SCT capture register of capture channel - CAP_MATCH - 0x128 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH10 - SCT match value register of match channels - CAP_MATCH - 0x128 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP11 - SCT capture register of capture channel - CAP_MATCH - 0x12C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH11 - SCT match value register of match channels - CAP_MATCH - 0x12C - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP12 - SCT capture register of capture channel - CAP_MATCH - 0x130 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH12 - SCT match value register of match channels - CAP_MATCH - 0x130 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP13 - SCT capture register of capture channel - CAP_MATCH - 0x134 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH13 - SCT match value register of match channels - CAP_MATCH - 0x134 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP14 - SCT capture register of capture channel - CAP_MATCH - 0x138 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH14 - SCT match value register of match channels - CAP_MATCH - 0x138 - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAP15 - SCT capture register of capture channel - CAP_MATCH - 0x13C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. - 0 - 16 - read-write - - - CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. - 16 - 16 - read-write - - - - - MATCH15 - SCT match value register of match channels - CAP_MATCH - 0x13C - 32 - read-write - 0 - 0xFFFFFFFF - - - MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. - 0 - 16 - read-write - - - MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. - 16 - 16 - read-write - - - - - CAPCTRL0 - SCT capture control register - CAPCTRL_MATCHREL - 0x200 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL0 - SCT match reload value register - CAPCTRL_MATCHREL - 0x200 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL1 - SCT capture control register - CAPCTRL_MATCHREL - 0x204 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL1 - SCT match reload value register - CAPCTRL_MATCHREL - 0x204 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL2 - SCT capture control register - CAPCTRL_MATCHREL - 0x208 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL2 - SCT match reload value register - CAPCTRL_MATCHREL - 0x208 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL3 - SCT capture control register - CAPCTRL_MATCHREL - 0x20C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL3 - SCT match reload value register - CAPCTRL_MATCHREL - 0x20C - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL4 - SCT capture control register - CAPCTRL_MATCHREL - 0x210 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL4 - SCT match reload value register - CAPCTRL_MATCHREL - 0x210 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL5 - SCT capture control register - CAPCTRL_MATCHREL - 0x214 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL5 - SCT match reload value register - CAPCTRL_MATCHREL - 0x214 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL6 - SCT capture control register - CAPCTRL_MATCHREL - 0x218 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL6 - SCT match reload value register - CAPCTRL_MATCHREL - 0x218 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL7 - SCT capture control register - CAPCTRL_MATCHREL - 0x21C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL7 - SCT match reload value register - CAPCTRL_MATCHREL - 0x21C - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL8 - SCT capture control register - CAPCTRL_MATCHREL - 0x220 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL8 - SCT match reload value register - CAPCTRL_MATCHREL - 0x220 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL9 - SCT capture control register - CAPCTRL_MATCHREL - 0x224 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL9 - SCT match reload value register - CAPCTRL_MATCHREL - 0x224 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL10 - SCT capture control register - CAPCTRL_MATCHREL - 0x228 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL10 - SCT match reload value register - CAPCTRL_MATCHREL - 0x228 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL11 - SCT capture control register - CAPCTRL_MATCHREL - 0x22C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL11 - SCT match reload value register - CAPCTRL_MATCHREL - 0x22C - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL12 - SCT capture control register - CAPCTRL_MATCHREL - 0x230 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL12 - SCT match reload value register - CAPCTRL_MATCHREL - 0x230 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL13 - SCT capture control register - CAPCTRL_MATCHREL - 0x234 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL13 - SCT match reload value register - CAPCTRL_MATCHREL - 0x234 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL14 - SCT capture control register - CAPCTRL_MATCHREL - 0x238 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL14 - SCT match reload value register - CAPCTRL_MATCHREL - 0x238 - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - CAPCTRL15 - SCT capture control register - CAPCTRL_MATCHREL - 0x23C - 32 - read-write - 0 - 0xFFFFFFFF - - - CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. - 0 - 16 - read-write - - - CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. - 16 - 16 - read-write - - - - - MATCHREL15 - SCT match reload value register - CAPCTRL_MATCHREL - 0x23C - 32 - read-write - 0 - 0xFFFFFFFF - - - RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. - 0 - 16 - read-write - - - RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. - 16 - 16 - read-write - - - - - 16 - 0x8 - EV[%s] - no description available - 0x300 - - EV_STATE - SCT event state register 0 - 0 - 32 - read-write - 0 - 0xFFFF - - - STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT. - 0 - 16 - read-write - - - - - EV_CTRL - SCT event control register 0 - 0x4 - 32 - read-write - 0 - 0x7FFFFF - - - MATCHSEL - Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. - 0 - 4 - read-write - - - HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. - 4 - 1 - read-write - - - L_COUNTER - Selects the L state and the L match register selected by MATCHSEL. - 0 - - - H_COUNTER - Selects the H state and the H match register selected by MATCHSEL. - 0x1 - - - - - OUTSEL - Input/output select - 5 - 1 - read-write - - - INPUT - Selects the inputs selected by IOSEL. - 0 - - - OUTPUT - Selects the outputs selected by IOSEL. - 0x1 - - - - - IOSEL - Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. - 6 - 4 - read-write - - - IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . - 10 - 2 - read-write - - - LOW - LOW - 0 - - - RISE - Rise - 0x1 - - - FALL - Fall - 0x2 - - - HIGH - HIGH - 0x3 - - - - - COMBMODE - Selects how the specified match and I/O condition are used and combined. - 12 - 2 - read-write - - - OR - OR. The event occurs when either the specified match or I/O condition occurs. - 0 - - - MATCH - MATCH. Uses the specified match only. - 0x1 - - - IO - IO. Uses the specified I/O condition only. - 0x2 - - - AND - AND. The event occurs when the specified match and I/O condition occur simultaneously. - 0x3 - - - - - STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. - 14 - 1 - read-write - - - ADD - STATEV value is added into STATE (the carry-out is ignored). - 0 - - - LOAD - STATEV value is loaded into STATE. - 0x1 - - - - - STATEV - This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. - 15 - 5 - read-write - - - MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. - 20 - 1 - read-write - - - DIRECTION - Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. - 21 - 2 - read-write - - - DIRECTION_INDEPENDENT - Direction independent. This event is triggered regardless of the count direction. - 0 - - - COUNTING_UP - Counting up. This event is triggered only during up-counting when BIDIR = 1. - 0x1 - - - COUNTING_DOWN - Counting down. This event is triggered only during down-counting when BIDIR = 1. - 0x2 - - - - - - - - 10 - 0x8 - OUT[%s] - no description available - 0x500 - - OUT_SET - SCT output 0 set register - 0 - 32 - read-write - 0 - 0xFFFF - - - SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. - 0 - 16 - read-write - - - - - OUT_CLR - SCT output 0 clear register - 0x4 - 32 - read-write - 0 - 0xFFFF - - - CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. - 0 - 16 - read-write - - - - - - - - FLEXCOMM0 - Flexcomm serial communication - FLEXCOMM - FLEXCOMM - 0x40086000 - - 0 - 0x1000 - registers - - - FLEXCOMM0 - 14 - - - - PSELID - Peripheral Select and Flexcomm ID register. - 0xFF8 - 32 - read-write - 0x101000 - 0xFFFFF0FF - - - PERSEL - Peripheral Select. This field is writable by software. - 0 - 3 - read-write - - - NO_PERIPH_SELECTED - No peripheral selected. - 0 - - - USART - USART function selected. - 0x1 - - - SPI - SPI function selected. - 0x2 - - - I2C - I2C function selected. - 0x3 - - - I2S_TRANSMIT - I2S transmit function selected. - 0x4 - - - I2S_RECEIVE - I2S receive function selected. - 0x5 - - - - - LOCK - Lock the peripheral select. This field is writable by software. - 3 - 1 - read-write - - - UNLOCKED - Peripheral select can be changed by software. - 0 - - - LOCKED - Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. - 0x1 - - - - - USARTPRESENT - USART present indicator. This field is Read-only. - 4 - 1 - read-only - - - NOT_PRESENT - This Flexcomm does not include the USART function. - 0 - - - PRESENT - This Flexcomm includes the USART function. - 0x1 - - - - - SPIPRESENT - SPI present indicator. This field is Read-only. - 5 - 1 - read-only - - - NOT_PRESENT - This Flexcomm does not include the SPI function. - 0 - - - PRESENT - This Flexcomm includes the SPI function. - 0x1 - - - - - I2CPRESENT - I2C present indicator. This field is Read-only. - 6 - 1 - read-only - - - NOT_PRESENT - This Flexcomm does not include the I2C function. - 0 - - - PRESENT - This Flexcomm includes the I2C function. - 0x1 - - - - - I2SPRESENT - I 2S present indicator. This field is Read-only. - 7 - 1 - read-only - - - NOT_PRESENT - This Flexcomm does not include the I2S function. - 0 - - - PRESENT - This Flexcomm includes the I2S function. - 0x1 - - - - - ID - Flexcomm ID. - 12 - 20 - read-only - - - - - PID - Peripheral identification register. - 0xFFC - 32 - read-only - 0 - 0xFFFFFFFF - - - APERTURE - size aperture for the register port on the bus (APB or AHB). - 0 - 8 - read-only - - - MINOR_REV - Minor revision of module implementation. - 8 - 4 - read-only - - - MAJOR_REV - Major revision of module implementation. - 12 - 4 - read-only - - - ID - Module identifier for the selected function. - 16 - 16 - read-only - - - - - - - FLEXCOMM1 - Flexcomm serial communication - FLEXCOMM - 0x40087000 - - 0 - 0x1000 - registers - - - FLEXCOMM1 - 15 - - - - FLEXCOMM2 - Flexcomm serial communication - FLEXCOMM - 0x40088000 - - 0 - 0x1000 - registers - - - FLEXCOMM2 - 16 - - - - FLEXCOMM3 - Flexcomm serial communication - FLEXCOMM - 0x40089000 - - 0 - 0x1000 - registers - - - FLEXCOMM3 - 17 - - - - FLEXCOMM4 - Flexcomm serial communication - FLEXCOMM - 0x4008A000 - - 0 - 0x1000 - registers - - - FLEXCOMM4 - 18 - - - - FLEXCOMM5 - Flexcomm serial communication - FLEXCOMM - 0x40096000 - - 0 - 0x1000 - registers - - - FLEXCOMM5 - 19 - - - - FLEXCOMM6 - Flexcomm serial communication - FLEXCOMM - 0x40097000 - - 0 - 0x1000 - registers - - - FLEXCOMM6 - 20 - - - - FLEXCOMM7 - Flexcomm serial communication - FLEXCOMM - 0x40098000 - - 0 - 0x1000 - registers - - - FLEXCOMM7 - 21 - - - - FLEXCOMM8 - Flexcomm serial communication - FLEXCOMM - 0x4009F000 - - 0 - 0x1000 - registers - - - FLEXCOMM8 - 59 - - - - I2C0 - I2C-bus interfaces - FLEXCOMM0 - I2C - I2C - 0x40086000 - - 0 - 0x1000 - registers - - - FLEXCOMM0 - 14 - - - - CFG - Configuration for shared functions. - 0x800 - 32 - read-write - 0 - 0x3F - - - MSTEN - Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset. - 0 - 1 - read-write - - - DISABLED - Disabled. The I2C Master function is disabled. - 0 - - - ENABLED - Enabled. The I2C Master function is enabled. - 0x1 - - - - - SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. - 1 - 1 - read-write - - - DISABLED - Disabled. The I2C slave function is disabled. - 0 - - - ENABLED - Enabled. The I2C slave function is enabled. - 0x1 - - - - - MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset. - 2 - 1 - read-write - - - DISABLED - Disabled. The I2C Monitor function is disabled. - 0 - - - ENABLED - Enabled. The I2C Monitor function is enabled. - 0x1 - - - - - TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. - 3 - 1 - read-write - - - DISABLED - Disabled. Time-out function is disabled. - 0 - - - ENABLED - Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system. - 0x1 - - - - - MONCLKSTR - Monitor function Clock Stretching. - 4 - 1 - read-write - - - DISABLED - Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical. - 0 - - - ENABLED - Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function. - 0x1 - - - - - HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor. - 5 - 1 - read-write - - - FAST_MODE_PLUS - Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin, - 0 - - - HIGH_SPEED - High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information. - 0x1 - - - - - - - STAT - Status register for Master, Slave, and Monitor functions. - 0x804 - 32 - read-write - 0x801 - 0x30FFF5F - - - MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt. - 0 - 1 - read-only - - - IN_PROGRESS - In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. - 0 - - - PENDING - Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit. - 0x1 - - - - - MSTSTATE - Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses. - 1 - 3 - read-only - - - IDLE - Idle. The Master function is available to be used for a new transaction. - 0 - - - RECEIVE_READY - Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. - 0x1 - - - TRANSMIT_READY - Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. - 0x2 - - - NACK_ADDRESS - NACK Address. Slave NACKed address. - 0x3 - - - NACK_DATA - NACK Data. Slave NACKed transmitted data. - 0x4 - - - - - MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - 4 - 1 - read-write - - - NO_LOSS - No Arbitration Loss has occurred. - 0 - - - ARBITRATION_LOSS - Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. - 0x1 - - - - - MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - 6 - 1 - read-write - - - NO_ERROR - No Start/Stop Error has occurred. - 0 - - - ERROR - The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled. - 0x1 - - - - - SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched. - 8 - 1 - read-only - - - IN_PROGRESS - In progress. The Slave function does not currently need service. - 0 - - - PENDING - Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. - 0x1 - - - - - SLVSTATE - Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes. - 9 - 2 - read-only - - - SLAVE_ADDRESS - Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. - 0 - - - SLAVE_RECEIVE - Slave receive. Received data is available (Slave Receiver mode). - 0x1 - - - SLAVE_TRANSMIT - Slave transmit. Data can be transmitted (Slave Transmitter mode). - 0x2 - - - - - SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. - 11 - 1 - read-only - - - STRETCHING - Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. - 0 - - - NOT_STRETCHING - Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time. - 0x1 - - - - - SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. - 12 - 2 - read-only - - - ADDRESS0 - Address 0. Slave address 0 was matched. - 0 - - - ADDRESS1 - Address 1. Slave address 1 was matched. - 0x1 - - - ADDRESS2 - Address 2. Slave address 2 was matched. - 0x2 - - - ADDRESS3 - Address 3. Slave address 3 was matched. - 0x3 - - - - - SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data. - 14 - 1 - read-only - - - NOT_SELECTED - Not selected. The Slave function is not currently selected. - 0 - - - SELECTED - Selected. The Slave function is currently selected. - 0x1 - - - - - SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. - 15 - 1 - read-write - - - NOT_DESELECTED - Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag. - 0 - - - DESELECTED - Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. - 0x1 - - - - - MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. - 16 - 1 - read-only - - - NO_DATA - No data. The Monitor function does not currently have data available. - 0 - - - DATA_WAITING - Data waiting. The Monitor function has data waiting to be read. - 0x1 - - - - - MONOV - Monitor Overflow flag. - 17 - 1 - read-write - - - NO_OVERRUN - No overrun. Monitor data has not overrun. - 0 - - - OVERRUN - Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. - 0x1 - - - - - MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. - 18 - 1 - read-only - - - INACTIVE - Inactive. The Monitor function considers the I2C bus to be inactive. - 0 - - - ACTIVE - Active. The Monitor function considers the I2C bus to be active. - 0x1 - - - - - MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit. - 19 - 1 - read-write - - - NOT_IDLE - Not idle. The I2C bus is not idle, or this flag has been cleared by software. - 0 - - - IDLE - Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. - 0x1 - - - - - EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle. - 24 - 1 - read-write - - - NO_TIMEOUT - No time-out. I2C bus events have not caused a time-out. - 0 - - - EVEN_TIMEOUT - Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. - 0x1 - - - - - SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. - 25 - 1 - read-write - - - NO_TIMEOUT - No time-out. SCL low time has not caused a time-out. - 0 - - - TIMEOUT - Time-out. SCL low time has caused a time-out. - 0x1 - - - - - - - INTENSET - Interrupt Enable Set and read register. - 0x808 - 32 - read-write - 0 - 0x30B8951 - - - MSTPENDINGEN - Master Pending interrupt Enable. - 0 - 1 - read-write - - - DISABLED - Disabled. The MstPending interrupt is disabled. - 0 - - - ENABLED - Enabled. The MstPending interrupt is enabled. - 0x1 - - - - - MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. - 4 - 1 - read-write - - - DISABLED - Disabled. The MstArbLoss interrupt is disabled. - 0 - - - ENABLED - Enabled. The MstArbLoss interrupt is enabled. - 0x1 - - - - - MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. - 6 - 1 - read-write - - - DISABLED - Disabled. The MstStStpErr interrupt is disabled. - 0 - - - ENABLED - Enabled. The MstStStpErr interrupt is enabled. - 0x1 - - - - - SLVPENDINGEN - Slave Pending interrupt Enable. - 8 - 1 - read-write - - - DISABLED - Disabled. The SlvPending interrupt is disabled. - 0 - - - ENABLED - Enabled. The SlvPending interrupt is enabled. - 0x1 - - - - - SLVNOTSTREN - Slave Not Stretching interrupt Enable. - 11 - 1 - read-write - - - DISABLED - Disabled. The SlvNotStr interrupt is disabled. - 0 - - - ENABLED - Enabled. The SlvNotStr interrupt is enabled. - 0x1 - - - - - SLVDESELEN - Slave Deselect interrupt Enable. - 15 - 1 - read-write - - - DISABLED - Disabled. The SlvDeSel interrupt is disabled. - 0 - - - ENABLED - Enabled. The SlvDeSel interrupt is enabled. - 0x1 - - - - - MONRDYEN - Monitor data Ready interrupt Enable. - 16 - 1 - read-write - - - DISABLED - Disabled. The MonRdy interrupt is disabled. - 0 - - - ENABLED - Enabled. The MonRdy interrupt is enabled. - 0x1 - - - - - MONOVEN - Monitor Overrun interrupt Enable. - 17 - 1 - read-write - - - DISABLED - Disabled. The MonOv interrupt is disabled. - 0 - - - ENABLED - Enabled. The MonOv interrupt is enabled. - 0x1 - - - - - MONIDLEEN - Monitor Idle interrupt Enable. - 19 - 1 - read-write - - - DISABLED - Disabled. The MonIdle interrupt is disabled. - 0 - - - ENABLED - Enabled. The MonIdle interrupt is enabled. - 0x1 - - - - - EVENTTIMEOUTEN - Event time-out interrupt Enable. - 24 - 1 - read-write - - - DISABLED - Disabled. The Event time-out interrupt is disabled. - 0 - - - ENABLED - Enabled. The Event time-out interrupt is enabled. - 0x1 - - - - - SCLTIMEOUTEN - SCL time-out interrupt Enable. - 25 - 1 - read-write - - - DISABLED - Disabled. The SCL time-out interrupt is disabled. - 0 - - - ENABLED - Enabled. The SCL time-out interrupt is enabled. - 0x1 - - - - - - - INTENCLR - Interrupt Enable Clear register. - 0x80C - 32 - write-only - 0 - 0 - - - MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented. - 0 - 1 - write-only - - - MSTARBLOSSCLR - Master Arbitration Loss interrupt clear. - 4 - 1 - write-only - - - MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear. - 6 - 1 - write-only - - - SLVPENDINGCLR - Slave Pending interrupt clear. - 8 - 1 - write-only - - - SLVNOTSTRCLR - Slave Not Stretching interrupt clear. - 11 - 1 - write-only - - - SLVDESELCLR - Slave Deselect interrupt clear. - 15 - 1 - write-only - - - MONRDYCLR - Monitor data Ready interrupt clear. - 16 - 1 - write-only - - - MONOVCLR - Monitor Overrun interrupt clear. - 17 - 1 - write-only - - - MONIDLECLR - Monitor Idle interrupt clear. - 19 - 1 - write-only - - - EVENTTIMEOUTCLR - Event time-out interrupt clear. - 24 - 1 - write-only - - - SCLTIMEOUTCLR - SCL time-out interrupt clear. - 25 - 1 - write-only - - - - - TIMEOUT - Time-out value register. - 0x810 - 32 - read-write - 0xFFFF - 0xFFFF - - - TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. - 0 - 4 - read-write - - - TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock. - 4 - 12 - read-write - - - - - CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. - 0x814 - 32 - read-write - 0 - 0xFFFF - - - DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use. - 0 - 16 - read-write - - - - - INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. - 0x818 - 32 - read-only - 0x801 - 0x30B8951 - - - MSTPENDING - Master Pending. - 0 - 1 - read-only - - - MSTARBLOSS - Master Arbitration Loss flag. - 4 - 1 - read-only - - - MSTSTSTPERR - Master Start/Stop Error flag. - 6 - 1 - read-only - - - SLVPENDING - Slave Pending. - 8 - 1 - read-only - - - SLVNOTSTR - Slave Not Stretching status. - 11 - 1 - read-only - - - SLVDESEL - Slave Deselected flag. - 15 - 1 - read-only - - - MONRDY - Monitor Ready. - 16 - 1 - read-only - - - MONOV - Monitor Overflow flag. - 17 - 1 - read-only - - - MONIDLE - Monitor Idle flag. - 19 - 1 - read-only - - - EVENTTIMEOUT - Event time-out Interrupt flag. - 24 - 1 - read-only - - - SCLTIMEOUT - SCL time-out Interrupt flag. - 25 - 1 - read-only - - - - - MSTCTL - Master control register. - 0x820 - 32 - read-write - 0 - 0xE - - - MSTCONTINUE - Master Continue. This bit is write-only. - 0 - 1 - write-only - - - NO_EFFECT - No effect. - 0 - - - CONTINUE - Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. - 0x1 - - - - - MSTSTART - Master Start control. This bit is write-only. - 1 - 1 - read-write - - - NO_EFFECT - No effect. - 0 - - - START - Start. A Start will be generated on the I2C bus at the next allowed time. - 0x1 - - - - - MSTSTOP - Master Stop control. This bit is write-only. - 2 - 1 - read-write - - - NO_EFFECT - No effect. - 0 - - - STOP - Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode). - 0x1 - - - - - MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write. - 3 - 1 - read-write - - - DISABLED - Disable. No DMA requests are generated for master operation. - 0 - - - ENABLED - Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. - 0x1 - - - - - - - MSTTIME - Master timing configuration. - 0x824 - 32 - read-write - 0x77 - 0x77 - - - MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. - 0 - 3 - read-write - - - CLOCKS_2 - 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. - 0 - - - CLOCKS_3 - 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. - 0x1 - - - CLOCKS_4 - 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. - 0x2 - - - CLOCKS_5 - 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. - 0x3 - - - CLOCKS_6 - 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. - 0x4 - - - CLOCKS_7 - 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. - 0x5 - - - CLOCKS_8 - 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. - 0x6 - - - CLOCKS_9 - 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. - 0x7 - - - - - MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. - 4 - 3 - read-write - - - CLOCKS_2 - 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. - 0 - - - CLOCKS_3 - 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . - 0x1 - - - CLOCKS_4 - 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. - 0x2 - - - CLOCKS_5 - 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. - 0x3 - - - CLOCKS_6 - 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. - 0x4 - - - CLOCKS_7 - 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. - 0x5 - - - CLOCKS_8 - 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. - 0x6 - - - CLOCKS_9 - 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. - 0x7 - - - - - - - MSTDAT - Combined Master receiver and transmitter data register. - 0x828 - 32 - read-write - 0 - 0xFF - - - DATA - Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function. - 0 - 8 - read-write - - - - - SLVCTL - Slave control register. - 0x840 - 32 - read-write - 0 - 0x30B - - - SLVCONTINUE - Slave Continue. - 0 - 1 - read-write - - - NO_EFFECT - No effect. - 0 - - - CONTINUE - Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1. - 0x1 - - - - - SLVNACK - Slave NACK. - 1 - 1 - read-write - - - NO_EFFECT - No effect. - 0 - - - NACK - NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). - 0x1 - - - - - SLVDMA - Slave DMA enable. - 3 - 1 - read-write - - - DISABLED - Disabled. No DMA requests are issued for Slave mode operation. - 0 - - - ENABLED - Enabled. DMA requests are issued for I2C slave data transmission and reception. - 0x1 - - - - - AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt. - 8 - 1 - read-write - - - NORMAL - Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored). - 0 - - - AUTOMATIC_ACK - A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. - 0x1 - - - - - AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation. - 9 - 1 - read-write - - - I2C_WRITE - The expected next operation in Automatic Mode is an I2C write. - 0 - - - I2C_READ - The expected next operation in Automatic Mode is an I2C read. - 0x1 - - - - - - - SLVDAT - Combined Slave receiver and transmitter data register. - 0x844 - 32 - read-write - 0 - 0xFF - - - DATA - Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function. - 0 - 8 - read-write - - - - - SLVADR0 - Slave address register. - 0x848 - 32 - read-write - 0x1 - 0xFF - - - SADISABLE - Slave Address n Disable. - 0 - 1 - read-write - - - ENABLED - Enabled. Slave Address n is enabled. - 0 - - - DISABLED - Ignored Slave Address n is ignored. - 0x1 - - - - - SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. - 1 - 7 - read-write - - - AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations. - 15 - 1 - read-write - - - NORMAL - Normal operation, matching I2C addresses are not ignored. - 0 - - - AUTOMATIC - Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction. - 0x1 - - - - - - - SLVADR1 - Slave address register. - 0x84C - 32 - read-write - 0x1 - 0xFF - - - SADISABLE - Slave Address n Disable. - 0 - 1 - read-write - - - ENABLED - Enabled. Slave Address n is enabled. - 0 - - - DISABLED - Ignored Slave Address n is ignored. - 0x1 - - - - - SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. - 1 - 7 - read-write - - - - - SLVADR2 - Slave address register. - 0x850 - 32 - read-write - 0x1 - 0xFF - - - SADISABLE - Slave Address n Disable. - 0 - 1 - read-write - - - ENABLED - Enabled. Slave Address n is enabled. - 0 - - - DISABLED - Ignored Slave Address n is ignored. - 0x1 - - - - - SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. - 1 - 7 - read-write - - - - - SLVADR3 - Slave address register. - 0x854 - 32 - read-write - 0x1 - 0xFF - - - SADISABLE - Slave Address n Disable. - 0 - 1 - read-write - - - ENABLED - Enabled. Slave Address n is enabled. - 0 - - - DISABLED - Ignored Slave Address n is ignored. - 0x1 - - - - - SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. - 1 - 7 - read-write - - - - - SLVQUAL0 - Slave Qualification for address 0. - 0x858 - 32 - read-write - 0 - 0xFF - - - QUALMODE0 - Qualify mode for slave address 0. - 0 - 1 - read-write - - - MASK - Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. - 0 - - - EXTEND - Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. - 0x1 - - - - - SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). - 1 - 7 - read-write - - - - - MONRXDAT - Monitor receiver data register. - 0x880 - 32 - read-only - 0 - 0x7FF - - - MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. - 0 - 8 - read-only - - - MONSTART - Monitor Received Start. - 8 - 1 - read-only - - - NO_START_DETECTED - No start detected. The Monitor function has not detected a Start event on the I2C bus. - 0 - - - START_DETECTED - Start detected. The Monitor function has detected a Start event on the I2C bus. - 0x1 - - - - - MONRESTART - Monitor Received Repeated Start. - 9 - 1 - read-only - - - NOT_DETECTED - No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. - 0 - - - DETECTED - Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. - 0x1 - - - - - MONNACK - Monitor Received NACK. - 10 - 1 - read-only - - - ACKNOWLEDGED - Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. - 0 - - - NOT_ACKNOWLEDGED - Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. - 0x1 - - - - - - - ID - Peripheral identification register. - 0xFFC - 32 - read-only - 0 - 0xFFFFFFFF - - - APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - 0 - 8 - read-only - - - MINOR_REV - Minor revision of module implementation. - 8 - 4 - read-only - - - MAJOR_REV - Major revision of module implementation. - 12 - 4 - read-only - - - ID - Module identifier for the selected function. - 16 - 16 - read-only - - - - - - - I2C1 - I2C-bus interfaces - FLEXCOMM1 - I2C - 0x40087000 - - 0 - 0x1000 - registers - - - FLEXCOMM1 - 15 - - - - I2C2 - I2C-bus interfaces - FLEXCOMM2 - I2C - 0x40088000 - - 0 - 0x1000 - registers - - - FLEXCOMM2 - 16 - - - - I2C3 - I2C-bus interfaces - FLEXCOMM3 - I2C - 0x40089000 - - 0 - 0x1000 - registers - - - FLEXCOMM3 - 17 - - - - I2C4 - I2C-bus interfaces - FLEXCOMM4 - I2C - 0x4008A000 - - 0 - 0x1000 - registers - - - FLEXCOMM4 - 18 - - - - I2C5 - I2C-bus interfaces - FLEXCOMM5 - I2C - 0x40096000 - - 0 - 0x1000 - registers - - - FLEXCOMM5 - 19 - - - - I2C6 - I2C-bus interfaces - FLEXCOMM6 - I2C - 0x40097000 - - 0 - 0x1000 - registers - - - FLEXCOMM6 - 20 - - - - I2C7 - I2C-bus interfaces - FLEXCOMM7 - I2C - 0x40098000 - - 0 - 0x1000 - registers - - - FLEXCOMM7 - 21 - - - - I2S0 - I2S interface - FLEXCOMM0 - I2S - I2S - 0x40086000 - - 0 - 0x1000 - registers - - - FLEXCOMM0 - 14 - - - - CFG1 - Configuration register 1 for the primary channel pair. - 0xC00 - 32 - read-write - 0 - 0x1F3FFF - - - MAINENABLE - Main enable for I 2S function in this Flexcomm - 0 - 1 - read-write - - - DISABLED - All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags are reset. No other channel pairs can be enabled. - 0 - - - ENABLED - This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. - 0x1 - - - - - DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame. - 1 - 1 - read-write - - - NORMAL - Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. - 0 - - - PAUSE - A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. - 0x1 - - - - - PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. - 2 - 2 - read-write - - - PAIRS_1 - 1 I2S channel pairs in this flexcomm - 0 - - - PAIRS_2 - 2 I2S channel pairs in this flexcomm - 0x1 - - - PAIRS_3 - 3 I2S channel pairs in this flexcomm - 0x2 - - - PAIRS_4 - 4 I2S channel pairs in this flexcomm - 0x3 - - - - - MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. - 4 - 2 - read-write - - - NORMAL_SLAVE_MODE - Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. - 0 - - - WS_SYNC_MASTER - WS synchronized master. WS is received from another master and used to synchronize the generation of SCK, when divided from the Flexcomm function clock. - 0x1 - - - MASTER_USING_SCK - Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. - 0x2 - - - NORMAL_MASTER - Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. - 0x3 - - - - - MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples. - 6 - 2 - read-write - - - CLASSIC_MODE - I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece of left channel data occurring during the first phase, and one pieces of right channel data occurring during the second phase. In this mode, the data region begins one clock after the leading WS edge for the frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. - 0 - - - DSP_MODE_WS_50_DUTYCYCLE - DSP mode where WS has a 50% duty cycle. See remark for mode 0. - 0x1 - - - DSP_MODE_WS_1_CLOCK - DSP mode where WS has a one clock long pulse at the beginning of each data frame. - 0x2 - - - DSP_MODE_WS_1_DATA - DSP mode where WS has a one data slot long pulse at the beginning of each data frame. - 0x3 - - - - - RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. - 8 - 1 - read-write - - - RIGHT_HIGH - The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO bits 31:16 are used for the right channel. - 0 - - - RIGHT_LOW - The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO bits 15:0 are used for the right channel. - 0x1 - - - - - LEFTJUST - Left Justify data. - 9 - 1 - read-write - - - RIGHT_JUSTIFIED - Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data in the stream on the data bus. - 0 - - - LEFT_JUSTIFIED - Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would correspond to left justified data in the stream on the data bus. - 0x1 - - - - - ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers. - 10 - 1 - read-write - - - DUAL_CHANNEL - I2S data for this channel pair is treated as left and right channels. - 0 - - - SINGLE_CHANNEL - I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data for the single channel of data is placed at the clock defined by POSITION. - 0x1 - - - - - SCK_POL - SCK polarity. - 12 - 1 - read-write - - - FALLING_EDGE - Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). - 0 - - - RISING_EDGE - Data is launched on SCK rising edges and sampled on SCK falling edges. - 0x1 - - - - - WS_POL - WS polarity. - 13 - 1 - read-write - - - NOT_INVERTED - Data frames begin at a falling edge of WS (standard for classic I2S). - 0 - - - INVERTED - WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). - 0x1 - - - - - DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the I2S: Determines the size of data transfers between the FIFO and the I2S serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = data is 32 bits in length - 16 - 5 - read-write - - - - - CFG2 - Configuration register 2 for the primary channel pair. - 0xC04 - 32 - read-write - 0 - 0x1FF01FF - - - FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger than DATALEN in order for the WS pulse to be generated correctly. - 0 - 9 - read-write - - - POSITION - Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION defines the location of data in both the left phase and right phase, starting one clock after the WS edge. In other modes, POSITION defines the location of data within the entire frame. ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS phase. 0x002 = data begins at bit position 2 within the frame or WS phase. - 16 - 9 - read-write - - - - - STAT - Status register for the primary channel pair. - 0xC08 - 32 - read-write - 0 - 0xD - - - BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. - 0 - 1 - read-only - - - IDLE - The transmitter/receiver for channel pair is currently idle. - 0 - - - BUSY - The transmitter/receiver for channel pair is currently processing data. - 0x1 - - - - - SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream. - 1 - 1 - write-only - - - NO_ERROR - No error has been recorded. - 0 - - - ERROR - An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. - 0x1 - - - - - LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair. - 2 - 1 - read-only - - - LEFT_CHANNEL - Left channel. - 0 - - - RIGHT_CHANNEL - Right channel. - 0x1 - - - - - DATAPAUSED - Data Paused status flag. Applies to all I2S channels - 3 - 1 - read-only - - - NOT_PAUSED - Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. - 0 - - - PAUSED - A data pause has been requested and is now in force. - 0x1 - - - - - - - DIV - Clock divider, used by all channel pairs. - 0xC1C - 32 - read-write - 0 - 0xFFF - - - DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is divided by 4,096. - 0 - 12 - read-write - - - - - FIFOCFG - FIFO configuration and enable register. - 0xE00 - 32 - read-write - 0 - 0x7F033 - - - ENABLETX - Enable the transmit FIFO. - 0 - 1 - read-write - - - DISABLED - The transmit FIFO is not enabled. - 0 - - - ENABLED - The transmit FIFO is enabled. - 0x1 - - - - - ENABLERX - Enable the receive FIFO. - 1 - 1 - read-write - - - DISABLED - The receive FIFO is not enabled. - 0 - - - ENABLED - The receive FIFO is enabled. - 0x1 - - - - - TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused. - 2 - 1 - read-write - - - LAST_VALUE - If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 bits or less, or when MONO = 1 for this channel pair. - 0 - - - ZERO - If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. - 0x1 - - - - - PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. - 3 - 1 - read-write - - - BIT_24 - 48-bit I2S FIFO entries are handled as all 24-bit values. - 0 - - - BIT_32_16 - 48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. - 0x1 - - - - - SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - 4 - 2 - read-only - - - DMATX - DMA configuration for transmit. - 12 - 1 - read-write - - - DISABLED - DMA is not used for the transmit function. - 0 - - - ENABLED - Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - 0x1 - - - - - DMARX - DMA configuration for receive. - 13 - 1 - read-write - - - DISABLED - DMA is not used for the receive function. - 0 - - - ENABLED - Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - 0x1 - - - - - WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 14 - 1 - read-write - - - DISABLED - Only enabled interrupts will wake up the device form reduced power modes. - 0 - - - ENABLED - A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. - 0x1 - - - - - WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 15 - 1 - read-write - - - DISABLED - Only enabled interrupts will wake up the device form reduced power modes. - 0 - - - ENABLED - A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. - 0x1 - - - - - EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - 16 - 1 - read-write - - - EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - 17 - 1 - read-write - - - - - FIFOSTAT - FIFO status register. - 0xE04 - 32 - read-write - 0x30 - 0x1F1FFB - - - TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. - 0 - 1 - read-write - - - RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - 1 - 1 - read-write - - - PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. - 3 - 1 - read-only - - - TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - 4 - 1 - read-only - - - TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. - 5 - 1 - read-only - - - RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - 6 - 1 - read-only - - - RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. - 7 - 1 - read-only - - - TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. - 8 - 5 - read-only - - - RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. - 16 - 5 - read-only - - - - - FIFOTRIG - FIFO trigger settings for interrupt and DMA request. - 0xE08 - 32 - read-write - 0 - 0xF0F03 - - - TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - 0 - 1 - read-write - - - DISABLED - Transmit FIFO level does not generate a FIFO level trigger. - 0 - - - ENABLED - An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - 0x1 - - - - - RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - 1 - 1 - read-write - - - DISABLED - Receive FIFO level does not generate a FIFO level trigger. - 0 - - - ENABLED - An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - 0x1 - - - - - TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). - 8 - 4 - read-write - - - RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). - 16 - 4 - read-write - - - - - FIFOINTENSET - FIFO interrupt enable set (enable) and read register. - 0xE10 - 32 - read-write - 0 - 0xF - - - TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - 0 - 1 - read-write - - - DISABLED - No interrupt will be generated for a transmit error. - 0 - - - ENABLED - An interrupt will be generated when a transmit error occurs. - 0x1 - - - - - RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - 1 - 1 - read-write - - - DISABLED - No interrupt will be generated for a receive error. - 0 - - - ENABLED - An interrupt will be generated when a receive error occurs. - 0x1 - - - - - TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 2 - 1 - read-write - - - DISABLED - No interrupt will be generated based on the TX FIFO level. - 0 - - - ENABLED - If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. - 0x1 - - - - - RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 3 - 1 - read-write - - - DISABLED - No interrupt will be generated based on the RX FIFO level. - 0 - - - ENABLED - If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. - 0x1 - - - - - - - FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. - 0xE14 - 32 - read-write - 0 - 0xF - - - TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - 0 - 1 - read-write - - - RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - 1 - 1 - read-write - - - TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - 2 - 1 - read-write - - - RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - 3 - 1 - read-write - - - - - FIFOINTSTAT - FIFO interrupt status register. - 0xE18 - 32 - read-only - 0 - 0x1F - - - TXERR - TX FIFO error. - 0 - 1 - read-only - - - RXERR - RX FIFO error. - 1 - 1 - read-only - - - TXLVL - Transmit FIFO level interrupt. - 2 - 1 - read-only - - - RXLVL - Receive FIFO level interrupt. - 3 - 1 - read-only - - - PERINT - Peripheral interrupt. - 4 - 1 - read-only - - - - - FIFOWR - FIFO write data. - 0xE20 - 32 - write-only - 0 - 0 - - - TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details. - 0 - 32 - write-only - - - - - FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. - 0xE24 - 32 - write-only - 0 - 0 - - - TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. - 0 - 24 - write-only - - - - - FIFORD - FIFO read data. - 0xE30 - 32 - read-only - 0 - 0 - - - RXDATA - Received data from the FIFO. The number of bits used depends on configuration details. - 0 - 32 - read-only - - - - - FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. - 0xE34 - 32 - read-only - 0 - 0xFFFFFF - - - RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. - 0 - 24 - read-only - - - - - FIFORDNOPOP - FIFO data read with no FIFO pop. - 0xE40 - 32 - read-only - 0 - 0 - - - RXDATA - Received data from the FIFO. - 0 - 32 - read-only - - - - - FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. - 0xE44 - 32 - read-only - 0 - 0xFFFFFF - - - RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. - 0 - 24 - read-only - - - - - FIFOSIZE - FIFO size register - 0xE48 - 32 - read-write - 0x8 - 0xFFFFFFFF - - - FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - 0 - 5 - read-only - - - - - ID - I2S Module identification - 0xFFC - 32 - read-only - 0xE0900000 - 0xFFFFFFFF - - - APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - 0 - 8 - read-only - - - MINOR_REV - Minor revision of module implementation, starting at 0. - 8 - 4 - read-only - - - MAJOR_REV - Major revision of module implementation, starting at 0. - 12 - 4 - read-only - - - ID - Unique module identifier for this IP block. - 16 - 16 - read-only - - - - - - - I2S1 - I2S interface - FLEXCOMM1 - I2S - 0x40087000 - - 0 - 0x1000 - registers - - - FLEXCOMM1 - 15 - - - - I2S2 - I2S interface - FLEXCOMM2 - I2S - 0x40088000 - - 0 - 0x1000 - registers - - - FLEXCOMM2 - 16 - - - - I2S3 - I2S interface - FLEXCOMM3 - I2S - 0x40089000 - - 0 - 0x1000 - registers - - - FLEXCOMM3 - 17 - - - - I2S4 - I2S interface - FLEXCOMM4 - I2S - 0x4008A000 - - 0 - 0x1000 - registers - - - FLEXCOMM4 - 18 - - - - I2S5 - I2S interface - FLEXCOMM5 - I2S - 0x40096000 - - 0 - 0x1000 - registers - - - FLEXCOMM5 - 19 - - - - I2S6 - I2S interface - FLEXCOMM6 - I2S - 0x40097000 - - 0 - 0x1000 - registers - - - FLEXCOMM6 - 20 - - - - I2S7 - I2S interface - FLEXCOMM7 - I2S - 0x40098000 - - 0 - 0x1000 - registers - - - FLEXCOMM7 - 21 - - - - SPI0 - Serial Peripheral Interfaces (SPI) - FLEXCOMM0 - SPI - SPI - 0x40086000 - - 0 - 0x1000 - registers - - - FLEXCOMM0 - 14 - - - - CFG - SPI Configuration register - 0x400 - 32 - read-write - 0 - 0xFBD - - - ENABLE - SPI enable. - 0 - 1 - read-write - - - DISABLED - Disabled. The SPI is disabled and the internal state machine and counters are reset. - 0 - - - ENABLED - Enabled. The SPI is enabled for operation. - 0x1 - - - - - MASTER - Master mode select. - 2 - 1 - read-write - - - SLAVE_MODE - Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. - 0 - - - MASTER_MODE - Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. - 0x1 - - - - - LSBF - LSB First mode enable. - 3 - 1 - read-write - - - STANDARD - Standard. Data is transmitted and received in standard MSB first order. - 0 - - - REVERSE - Reverse. Data is transmitted and received in reverse order (LSB first). - 0x1 - - - - - CPHA - Clock Phase select. - 4 - 1 - read-write - - - CHANGE - Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge. - 0 - - - CAPTURE - Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge. - 0x1 - - - - - CPOL - Clock Polarity select. - 5 - 1 - read-write - - - LOW - Low. The rest state of the clock (between transfers) is low. - 0 - - - HIGH - High. The rest state of the clock (between transfers) is high. - 0x1 - - - - - LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. - 7 - 1 - read-write - - - DISABLED - Disabled. - 0 - - - ENABLED - Enabled. - 0x1 - - - - - SPOL0 - SSEL0 Polarity select. - 8 - 1 - read-write - - - LOW - Low. The SSEL0 pin is active low. - 0 - - - HIGH - High. The SSEL0 pin is active high. - 0x1 - - - - - SPOL1 - SSEL1 Polarity select. - 9 - 1 - read-write - - - LOW - Low. The SSEL1 pin is active low. - 0 - - - HIGH - High. The SSEL1 pin is active high. - 0x1 - - - - - SPOL2 - SSEL2 Polarity select. - 10 - 1 - read-write - - - LOW - Low. The SSEL2 pin is active low. - 0 - - - HIGH - High. The SSEL2 pin is active high. - 0x1 - - - - - SPOL3 - SSEL3 Polarity select. - 11 - 1 - read-write - - - LOW - Low. The SSEL3 pin is active low. - 0 - - - HIGH - High. The SSEL3 pin is active high. - 0x1 - - - - - - - DLY - SPI Delay register - 0x404 - 32 - read-write - 0 - 0xFFFF - - - PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. - 0 - 4 - read-write - - - POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. - 4 - 4 - read-write - - - FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. - 8 - 4 - read-write - - - TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times. - 12 - 4 - read-write - - - - - STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. - 0x408 - 32 - read-write - 0x100 - 0x1C0 - - - SSA - Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software. - 4 - 1 - write-only - - - SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software. - 5 - 1 - write-only - - - STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition. - 6 - 1 - read-only - - - ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. - 7 - 1 - read-write - - - MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data. - 8 - 1 - read-only - - - - - INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. - 0x40C - 32 - read-write - 0 - 0x130 - - - SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. - 4 - 1 - read-write - - - DISABLED - Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. - 0 - - - ENABLED - Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. - 0x1 - - - - - SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. - 5 - 1 - read-write - - - DISABLED - Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. - 0 - - - ENABLED - Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. - 0x1 - - - - - MSTIDLEEN - Master idle interrupt enable. - 8 - 1 - read-write - - - DISABLED - No interrupt will be generated when the SPI master function is idle. - 0 - - - ENABLED - An interrupt will be generated when the SPI master function is fully idle. - 0x1 - - - - - - - INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. - 0x410 - 32 - write-only - 0 - 0 - - - SSAEN - Writing 1 clears the corresponding bit in the INTENSET register. - 4 - 1 - write-only - - - SSDEN - Writing 1 clears the corresponding bit in the INTENSET register. - 5 - 1 - write-only - - - MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register. - 8 - 1 - write-only - - - - - DIV - SPI clock Divider - 0x424 - 32 - read-write - 0 - 0xFFFF - - - DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536. - 0 - 16 - read-write - - - - - INTSTAT - SPI Interrupt Status - 0x428 - 32 - read-only - 0 - 0x130 - - - SSA - Slave Select Assert. - 4 - 1 - read-only - - - SSD - Slave Select Deassert. - 5 - 1 - read-only - - - MSTIDLE - Master Idle status flag. - 8 - 1 - read-only - - - - - FIFOCFG - FIFO configuration and enable register. - 0xE00 - 32 - read-write - 0 - 0x7F033 - - - ENABLETX - Enable the transmit FIFO. - 0 - 1 - read-write - - - DISABLED - The transmit FIFO is not enabled. - 0 - - - ENABLED - The transmit FIFO is enabled. - 0x1 - - - - - ENABLERX - Enable the receive FIFO. - 1 - 1 - read-write - - - DISABLED - The receive FIFO is not enabled. - 0 - - - ENABLED - The receive FIFO is enabled. - 0x1 - - - - - SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - 4 - 2 - read-only - - - DMATX - DMA configuration for transmit. - 12 - 1 - read-write - - - DISABLED - DMA is not used for the transmit function. - 0 - - - ENABLED - Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - 0x1 - - - - - DMARX - DMA configuration for receive. - 13 - 1 - read-write - - - DISABLED - DMA is not used for the receive function. - 0 - - - ENABLED - Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - 0x1 - - - - - WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 14 - 1 - read-write - - - DISABLED - Only enabled interrupts will wake up the device form reduced power modes. - 0 - - - ENABLED - A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. - 0x1 - - - - - WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 15 - 1 - read-write - - - DISABLED - Only enabled interrupts will wake up the device form reduced power modes. - 0 - - - ENABLED - A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. - 0x1 - - - - - EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - 16 - 1 - read-write - - - EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - 17 - 1 - read-write - - - - - FIFOSTAT - FIFO status register. - 0xE04 - 32 - read-write - 0x30 - 0x1F1FFB - - - TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. - 0 - 1 - read-write - - - RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - 1 - 1 - read-write - - - PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. - 3 - 1 - read-only - - - TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - 4 - 1 - read-only - - - TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. - 5 - 1 - read-only - - - RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - 6 - 1 - read-only - - - RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. - 7 - 1 - read-only - - - TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. - 8 - 5 - read-only - - - RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. - 16 - 5 - read-only - - - - - FIFOTRIG - FIFO trigger settings for interrupt and DMA request. - 0xE08 - 32 - read-write - 0 - 0xF0F03 - - - TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - 0 - 1 - read-write - - - DISABLED - Transmit FIFO level does not generate a FIFO level trigger. - 0 - - - ENABLED - An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - 0x1 - - - - - RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - 1 - 1 - read-write - - - DISABLED - Receive FIFO level does not generate a FIFO level trigger. - 0 - - - ENABLED - An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - 0x1 - - - - - TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). - 8 - 4 - read-write - - - RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). - 16 - 4 - read-write - - - - - FIFOINTENSET - FIFO interrupt enable set (enable) and read register. - 0xE10 - 32 - read-write - 0 - 0xF - - - TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - 0 - 1 - read-write - - - DISABLED - No interrupt will be generated for a transmit error. - 0 - - - ENABLED - An interrupt will be generated when a transmit error occurs. - 0x1 - - - - - RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - 1 - 1 - read-write - - - DISABLED - No interrupt will be generated for a receive error. - 0 - - - ENABLED - An interrupt will be generated when a receive error occurs. - 0x1 - - - - - TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 2 - 1 - read-write - - - DISABLED - No interrupt will be generated based on the TX FIFO level. - 0 - - - ENABLED - If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. - 0x1 - - - - - RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 3 - 1 - read-write - - - DISABLED - No interrupt will be generated based on the RX FIFO level. - 0 - - - ENABLED - If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. - 0x1 - - - - - - - FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. - 0xE14 - 32 - read-write - 0 - 0xF - - - TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - 0 - 1 - read-write - - - RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - 1 - 1 - read-write - - - TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - 2 - 1 - read-write - - - RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - 3 - 1 - read-write - - - - - FIFOINTSTAT - FIFO interrupt status register. - 0xE18 - 32 - read-only - 0 - 0x1F - - - TXERR - TX FIFO error. - 0 - 1 - read-only - - - RXERR - RX FIFO error. - 1 - 1 - read-only - - - TXLVL - Transmit FIFO level interrupt. - 2 - 1 - read-only - - - RXLVL - Receive FIFO level interrupt. - 3 - 1 - read-only - - - PERINT - Peripheral interrupt. - 4 - 1 - read-only - - - - - FIFOWR - FIFO write data. - 0xE20 - 32 - write-only - 0 - 0 - - - TXDATA - Transmit data to the FIFO. - 0 - 16 - write-only - - - TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. - 16 - 1 - write-only - - - ASSERTED - SSEL0 asserted. - 0 - - - NOT_ASSERTED - SSEL0 not asserted. - 0x1 - - - - - TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. - 17 - 1 - write-only - - - ASSERTED - SSEL1 asserted. - 0 - - - NOT_ASSERTED - SSEL1 not asserted. - 0x1 - - - - - TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. - 18 - 1 - write-only - - - ASSERTED - SSEL2 asserted. - 0 - - - NOT_ASSERTED - SSEL2 not asserted. - 0x1 - - - - - TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. - 19 - 1 - write-only - - - ASSERTED - SSEL3 asserted. - 0 - - - NOT_ASSERTED - SSEL3 not asserted. - 0x1 - - - - - EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register. - 20 - 1 - write-only - - - NOT_DEASSERTED - SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. - 0 - - - DEASSERTED - SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. - 0x1 - - - - - EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. - 21 - 1 - write-only - - - NOT_EOF - Data not EOF. This piece of data transmitted is not treated as the end of a frame. - 0 - - - EOF - Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted. - 0x1 - - - - - RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA. - 22 - 1 - write-only - - - READ - Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received. - 0 - - - IGNORE - Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated. - 0x1 - - - - - LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length. - 24 - 4 - write-only - - - - - FIFORD - FIFO read data. - 0xE30 - 32 - read-only - 0 - 0xE1FF - - - RXDATA - Received data from the FIFO. - 0 - 16 - read-only - - - RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. - 16 - 1 - read-only - - - RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. - 17 - 1 - read-only - - - RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. - 18 - 1 - read-only - - - RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. - 19 - 1 - read-only - - - SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bits. - 20 - 1 - read-only - - - - - FIFORDNOPOP - FIFO data read with no FIFO pop. - 0xE40 - 32 - read-only - 0 - 0xE1FF - - - RXDATA - Received data from the FIFO. - 0 - 16 - read-only - - - RXSSEL0_N - Slave Select for receive. - 16 - 1 - read-only - - - RXSSEL1_N - Slave Select for receive. - 17 - 1 - read-only - - - RXSSEL2_N - Slave Select for receive. - 18 - 1 - read-only - - - RXSSEL3_N - Slave Select for receive. - 19 - 1 - read-only - - - SOT - Start of transfer flag. - 20 - 1 - read-only - - - - - FIFOSIZE - FIFO size register - 0xE48 - 32 - read-write - 0x8 - 0xFFFFFFFF - - - FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - 0 - 5 - read-only - - - - - ID - Peripheral identification register. - 0xFFC - 32 - read-only - 0xE0201200 - 0xFFFFFFFF - - - APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - 0 - 8 - read-only - - - MINOR_REV - Minor revision of module implementation. - 8 - 4 - read-only - - - MAJOR_REV - Major revision of module implementation. - 12 - 4 - read-only - - - ID - Module identifier for the selected function. - 16 - 16 - read-only - - - - - - - SPI1 - Serial Peripheral Interfaces (SPI) - FLEXCOMM1 - SPI - 0x40087000 - - 0 - 0x1000 - registers - - - FLEXCOMM1 - 15 - - - - SPI2 - Serial Peripheral Interfaces (SPI) - FLEXCOMM2 - SPI - 0x40088000 - - 0 - 0x1000 - registers - - - FLEXCOMM2 - 16 - - - - SPI3 - Serial Peripheral Interfaces (SPI) - FLEXCOMM3 - SPI - 0x40089000 - - 0 - 0x1000 - registers - - - FLEXCOMM3 - 17 - - - - SPI4 - Serial Peripheral Interfaces (SPI) - FLEXCOMM4 - SPI - 0x4008A000 - - 0 - 0x1000 - registers - - - FLEXCOMM4 - 18 - - - - SPI5 - Serial Peripheral Interfaces (SPI) - FLEXCOMM5 - SPI - 0x40096000 - - 0 - 0x1000 - registers - - - FLEXCOMM5 - 19 - - - - SPI6 - Serial Peripheral Interfaces (SPI) - FLEXCOMM6 - SPI - 0x40097000 - - 0 - 0x1000 - registers - - - FLEXCOMM6 - 20 - - - - SPI7 - Serial Peripheral Interfaces (SPI) - FLEXCOMM7 - SPI - 0x40098000 - - 0 - 0x1000 - registers - - - FLEXCOMM7 - 21 - - - - SPI8 - Serial Peripheral Interfaces (SPI) - FLEXCOMM8 - SPI - 0x4009F000 - - 0 - 0x1000 - registers - - - FLEXCOMM8 - 59 - - - - USART0 - USARTs - FLEXCOMM0 - USART - USART - 0x40086000 - - 0 - 0x1000 - registers - - - FLEXCOMM0 - 14 - - - - CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. - 0 - 32 - read-write - 0 - 0xFDDBFD - - - ENABLE - USART Enable. - 0 - 1 - read-write - - - DISABLED - Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available. - 0 - - - ENABLED - Enabled. The USART is enabled for operation. - 0x1 - - - - - DATALEN - Selects the data size for the USART. - 2 - 2 - read-write - - - BIT_7 - 7 bit Data length. - 0 - - - BIT_8 - 8 bit Data length. - 0x1 - - - BIT_9 - 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. - 0x2 - - - - - PARITYSEL - Selects what type of parity is used by the USART. - 4 - 2 - read-write - - - NO_PARITY - No parity. - 0 - - - EVEN_PARITY - Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. - 0x2 - - - ODD_PARITY - Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. - 0x3 - - - - - STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. - 6 - 1 - read-write - - - BIT_1 - 1 stop bit. - 0 - - - BITS_2 - 2 stop bits. This setting should only be used for asynchronous communication. - 0x1 - - - - - MODE32K - Selects standard or 32 kHz clocking mode. - 7 - 1 - read-write - - - DISABLED - Disabled. USART uses standard clocking. - 0 - - - ENABLED - Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. - 0x1 - - - - - LINMODE - LIN break mode enable. - 8 - 1 - read-write - - - DISABLED - Disabled. Break detect and generate is configured for normal operation. - 0 - - - ENABLED - Enabled. Break detect and generate is configured for LIN bus operation. - 0x1 - - - - - CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. - 9 - 1 - read-write - - - DISABLED - No flow control. The transmitter does not receive any automatic flow control signal. - 0 - - - ENABLED - Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. - 0x1 - - - - - SYNCEN - Selects synchronous or asynchronous operation. - 11 - 1 - read-write - - - ASYNCHRONOUS_MODE - Asynchronous mode. - 0 - - - SYNCHRONOUS_MODE - Synchronous mode. - 0x1 - - - - - CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. - 12 - 1 - read-write - - - FALLING_EDGE - Falling edge. Un_RXD is sampled on the falling edge of SCLK. - 0 - - - RISING_EDGE - Rising edge. Un_RXD is sampled on the rising edge of SCLK. - 0x1 - - - - - SYNCMST - Synchronous mode Master select. - 14 - 1 - read-write - - - SLAVE - Slave. When synchronous mode is enabled, the USART is a slave. - 0 - - - MASTER - Master. When synchronous mode is enabled, the USART is a master. - 0x1 - - - - - LOOP - Selects data loopback mode. - 15 - 1 - read-write - - - NORMAL - Normal operation. - 0 - - - LOOPBACK - Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. - 0x1 - - - - - OETA - Output Enable Turnaround time enable for RS-485 operation. - 18 - 1 - read-write - - - DISABLED - Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. - 0 - - - ENABLED - Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted. - 0x1 - - - - - AUTOADDR - Automatic Address matching enable. - 19 - 1 - read-write - - - DISABLED - Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). - 0 - - - ENABLED - Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match. - 0x1 - - - - - OESEL - Output Enable Select. - 20 - 1 - read-write - - - STANDARD - Standard. The RTS signal is used as the standard flow control function. - 0 - - - RS_485 - RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. - 0x1 - - - - - OEPOL - Output Enable Polarity. - 21 - 1 - read-write - - - LOW - Low. If selected by OESEL, the output enable is active low. - 0 - - - HIGH - High. If selected by OESEL, the output enable is active high. - 0x1 - - - - - RXPOL - Receive data polarity. - 22 - 1 - read-write - - - STANDARD - Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. - 0 - - - INVERTED - Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. - 0x1 - - - - - TXPOL - Transmit data polarity. - 23 - 1 - read-write - - - STANDARD - Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. - 0 - - - INVERTED - Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. - 0x1 - - - - - - - CTL - USART Control register. USART control settings that are more likely to change during operation. - 0x4 - 32 - read-write - 0 - 0x10346 - - - TXBRKEN - Break Enable. - 1 - 1 - read-write - - - NORMAL - Normal operation. - 0 - - - CONTINOUS - Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. - 0x1 - - - - - ADDRDET - Enable address detect mode. - 2 - 1 - read-write - - - DISABLED - Disabled. The USART presents all incoming data. - 0 - - - ENABLED - Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. - 0x1 - - - - - TXDIS - Transmit Disable. - 6 - 1 - read-write - - - ENABLED - Not disabled. USART transmitter is not disabled. - 0 - - - DISABLED - Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. - 0x1 - - - - - CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. - 8 - 1 - read-write - - - CLOCK_ON_CHARACTER - Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. - 0 - - - CONTINOUS_CLOCK - Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). - 0x1 - - - - - CLRCCONRX - Clear Continuous Clock. - 9 - 1 - read-write - - - NO_EFFECT - No effect. No effect on the CC bit. - 0 - - - AUTO_CLEAR - Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. - 0x1 - - - - - AUTOBAUD - Autobaud enable. - 16 - 1 - read-write - - - DISABLED - Disabled. USART is in normal operating mode. - 0 - - - ENABLED - Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. - 0x1 - - - - - - - STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. - 0x8 - 32 - read-write - 0xA - 0x45A - - - RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data. - 1 - 1 - read-only - - - TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data. - 3 - 1 - read-only - - - CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. - 4 - 1 - read-only - - - DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. - 5 - 1 - write-only - - - TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). - 6 - 1 - read-only - - - RXBRK - Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high. - 10 - 1 - read-only - - - DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software. - 11 - 1 - write-only - - - START - This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software. - 12 - 1 - write-only - - - FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. - 13 - 1 - write-only - - - PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. - 14 - 1 - write-only - - - RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception. - 15 - 1 - write-only - - - ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto baud time-out. - 16 - 1 - write-only - - - - - INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. - 0xC - 32 - read-write - 0 - 0x1F868 - - - TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). - 3 - 1 - read-write - - - DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input. - 5 - 1 - read-write - - - TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details. - 6 - 1 - read-write - - - DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted). - 11 - 1 - read-write - - - STARTEN - When 1, enables an interrupt when a received start bit has been detected. - 12 - 1 - read-write - - - FRAMERREN - When 1, enables an interrupt when a framing error has been detected. - 13 - 1 - read-write - - - PARITYERREN - When 1, enables an interrupt when a parity error has been detected. - 14 - 1 - read-write - - - RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. - 15 - 1 - read-write - - - ABERREN - When 1, enables an interrupt when an auto baud error occurs. - 16 - 1 - read-write - - - - - INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. - 0x10 - 32 - write-only - 0 - 0 - - - TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register. - 3 - 1 - write-only - - - DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register. - 5 - 1 - write-only - - - TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register. - 6 - 1 - write-only - - - DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register. - 11 - 1 - write-only - - - STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register. - 12 - 1 - write-only - - - FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - 13 - 1 - write-only - - - PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - 14 - 1 - write-only - - - RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register. - 15 - 1 - write-only - - - ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. - 16 - 1 - write-only - - - - - BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. - 0x20 - 32 - read-write - 0 - 0xFFFF - - - BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. - 0 - 16 - read-write - - - - - INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. - 0x24 - 32 - read-only - 0 - 0x1F968 - - - TXIDLE - Transmitter Idle status. - 3 - 1 - read-only - - - DELTACTS - This bit is set when a change in the state of the CTS input is detected. - 5 - 1 - read-only - - - TXDISINT - Transmitter Disabled Interrupt flag. - 6 - 1 - read-only - - - DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. - 11 - 1 - read-only - - - START - This bit is set when a start is detected on the receiver input. - 12 - 1 - read-only - - - FRAMERRINT - Framing Error interrupt flag. - 13 - 1 - read-only - - - PARITYERRINT - Parity Error interrupt flag. - 14 - 1 - read-only - - - RXNOISEINT - Received Noise interrupt flag. - 15 - 1 - read-only - - - ABERRINT - Auto baud Error Interrupt flag. - 16 - 1 - read-only - - - - - OSR - Oversample selection register for asynchronous communication. - 0x28 - 32 - read-write - 0xF - 0xF - - - OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. - 0 - 4 - read-write - - - - - ADDR - Address register for automatic address matching. - 0x2C - 32 - read-write - 0 - 0xFF - - - ADDRESS - 8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). - 0 - 8 - read-write - - - - - FIFOCFG - FIFO configuration and enable register. - 0xE00 - 32 - read-write - 0 - 0x7F033 - - - ENABLETX - Enable the transmit FIFO. - 0 - 1 - read-write - - - DISABLED - The transmit FIFO is not enabled. - 0 - - - ENABLED - The transmit FIFO is enabled. - 0x1 - - - - - ENABLERX - Enable the receive FIFO. - 1 - 1 - read-write - - - DISABLED - The receive FIFO is not enabled. - 0 - - - ENABLED - The receive FIFO is enabled. - 0x1 - - - - - SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. - 4 - 2 - read-only - - - DMATX - DMA configuration for transmit. - 12 - 1 - read-write - - - DISABLED - DMA is not used for the transmit function. - 0 - - - ENABLED - Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - 0x1 - - - - - DMARX - DMA configuration for receive. - 13 - 1 - read-write - - - DISABLED - DMA is not used for the receive function. - 0 - - - ENABLED - Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - 0x1 - - - - - WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 14 - 1 - read-write - - - DISABLED - Only enabled interrupts will wake up the device form reduced power modes. - 0 - - - ENABLED - A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. - 0x1 - - - - - WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - 15 - 1 - read-write - - - DISABLED - Only enabled interrupts will wake up the device form reduced power modes. - 0 - - - ENABLED - A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. - 0x1 - - - - - EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. - 16 - 1 - read-write - - - EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. - 17 - 1 - read-write - - - - - FIFOSTAT - FIFO status register. - 0xE04 - 32 - read-write - 0x30 - 0x1F1FFB - - - TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. - 0 - 1 - read-write - - - RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. - 1 - 1 - read-write - - - PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. - 3 - 1 - read-only - - - TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. - 4 - 1 - read-only - - - TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. - 5 - 1 - read-only - - - RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. - 6 - 1 - read-only - - - RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. - 7 - 1 - read-only - - - TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. - 8 - 5 - read-only - - - RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. - 16 - 5 - read-only - - - - - FIFOTRIG - FIFO trigger settings for interrupt and DMA request. - 0xE08 - 32 - read-write - 0 - 0xF0F03 - - - TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - 0 - 1 - read-write - - - DISABLED - Transmit FIFO level does not generate a FIFO level trigger. - 0 - - - ENABLED - An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - 0x1 - - - - - RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - 1 - 1 - read-write - - - DISABLED - Receive FIFO level does not generate a FIFO level trigger. - 0 - - - ENABLED - An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - 0x1 - - - - - TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). - 8 - 4 - read-write - - - RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). - 16 - 4 - read-write - - - - - FIFOINTENSET - FIFO interrupt enable set (enable) and read register. - 0xE10 - 32 - read-write - 0 - 0xF - - - TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - 0 - 1 - read-write - - - DISABLED - No interrupt will be generated for a transmit error. - 0 - - - ENABLED - An interrupt will be generated when a transmit error occurs. - 0x1 - - - - - RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - 1 - 1 - read-write - - - DISABLED - No interrupt will be generated for a receive error. - 0 - - - ENABLED - An interrupt will be generated when a receive error occurs. - 0x1 - - - - - TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 2 - 1 - read-write - - - DISABLED - No interrupt will be generated based on the TX FIFO level. - 0 - - - ENABLED - If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. - 0x1 - - - - - RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - 3 - 1 - read-write - - - DISABLED - No interrupt will be generated based on the RX FIFO level. - 0 - - - ENABLED - If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. - 0x1 - - - - - - - FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. - 0xE14 - 32 - read-write - 0 - 0xF - - - TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - 0 - 1 - read-write - - - RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. - 1 - 1 - read-write - - - TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - 2 - 1 - read-write - - - RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. - 3 - 1 - read-write - - - - - FIFOINTSTAT - FIFO interrupt status register. - 0xE18 - 32 - read-only - 0 - 0x1F - - - TXERR - TX FIFO error. - 0 - 1 - read-only - - - RXERR - RX FIFO error. - 1 - 1 - read-only - - - TXLVL - Transmit FIFO level interrupt. - 2 - 1 - read-only - - - RXLVL - Receive FIFO level interrupt. - 3 - 1 - read-only - - - PERINT - Peripheral interrupt. - 4 - 1 - read-only - - - - - FIFOWR - FIFO write data. - 0xE20 - 32 - write-only - 0 - 0 - - - TXDATA - Transmit data to the FIFO. - 0 - 9 - write-only - - - - - FIFORD - FIFO read data. - 0xE30 - 32 - read-only - 0 - 0xE1FF - - - RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. - 0 - 9 - read-only - - - FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. - 13 - 1 - read-only - - - PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. - 14 - 1 - read-only - - - RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. - 15 - 1 - read-only - - - - - FIFORDNOPOP - FIFO data read with no FIFO pop. - 0xE40 - 32 - read-only - 0 - 0xE1FF - - - RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. - 0 - 9 - read-only - - - FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. - 13 - 1 - read-only - - - PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. - 14 - 1 - read-only - - - RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. - 15 - 1 - read-only - - - - - FIFOSIZE - FIFO size register - 0xE48 - 32 - read-write - 0x8 - 0xFFFFFFFF - - - FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. - 0 - 5 - read-only - - - - - ID - Peripheral identification register. - 0xFFC - 32 - read-only - 0 - 0xFFFFFFFF - - - APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. - 0 - 8 - read-only - - - MINOR_REV - Minor revision of module implementation. - 8 - 4 - read-only - - - MAJOR_REV - Major revision of module implementation. - 12 - 4 - read-only - - - ID - Module identifier for the selected function. - 16 - 16 - read-only - - - - - - - USART1 - USARTs - FLEXCOMM1 - USART - 0x40087000 - - 0 - 0x1000 - registers - - - FLEXCOMM1 - 15 - - - - USART2 - USARTs - FLEXCOMM2 - USART - 0x40088000 - - 0 - 0x1000 - registers - - - FLEXCOMM2 - 16 - - - - USART3 - USARTs - FLEXCOMM3 - USART - 0x40089000 - - 0 - 0x1000 - registers - - - FLEXCOMM3 - 17 - - - - USART4 - USARTs - FLEXCOMM4 - USART - 0x4008A000 - - 0 - 0x1000 - registers - - - FLEXCOMM4 - 18 - - - - USART5 - USARTs - FLEXCOMM5 - USART - 0x40096000 - - 0 - 0x1000 - registers - - - FLEXCOMM5 - 19 - - - - USART6 - USARTs - FLEXCOMM6 - USART - 0x40097000 - - 0 - 0x1000 - registers - - - FLEXCOMM6 - 20 - - - - USART7 - USARTs - FLEXCOMM7 - USART - 0x40098000 - - 0 - 0x1000 - registers - - - FLEXCOMM7 - 21 - - - - MAILBOX - Mailbox - MAILBOX - 0x4008B000 - - 0 - 0xFC - registers - - - MAILBOX - 31 - - - - 2 - 0x10 - MBOXIRQ[%s] - no description available - 0 - - IRQ - Interrupt request register for the Cortex-M0+ CPU. - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - INTREQ - If any bit is set, an interrupt request is sent to the Cortex-M0+ interrupt controller. - 0 - 32 - read-write - - - - - IRQSET - Set bits in IRQ0 - 0x4 - 32 - write-only - 0 - 0 - - - INTREQSET - Writing 1 sets the corresponding bit in the IRQ0 register. - 0 - 32 - write-only - - - - - IRQCLR - Clear bits in IRQ0 - 0x8 - 32 - write-only - 0 - 0 - - - INTREQCLR - Writing 1 clears the corresponding bit in the IRQ0 register. - 0 - 32 - write-only - - - - - - MUTEX - Mutual exclusion register[1] - 0xF8 - 32 - read-write - 0x1 - 0x1 - - - EX - Cleared when read, set when written. See usage description above. - 0 - 1 - read-write - - - - - - - GPIO - General Purpose I/O (GPIO) - GPIO - 0x4008C000 - - 0 - 0x2488 - registers - - - - 2 - 0x20 - B[%s] - no description available - 0 - - 32 - 0x1 - B_[%s] - Byte pin registers for all port GPIO pins - 0 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - - 2 - 0x80 - W[%s] - no description available - 0x1000 - - 32 - 0x4 - W_[%s] - Word pin registers for all port GPIO pins - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - - 2 - 0x4 - DIR[%s] - Direction registers for all port GPIO pins - 0x2000 - 32 - read-write - 0 - 0xFFFFFFFF - - - DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output. - 0 - 32 - read-write - - - - - 2 - 0x4 - MASK[%s] - Mask register for all port GPIO pins - 0x2080 - 32 - read-write - 0 - 0xFFFFFFFF - - - MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. - 0 - 32 - read-write - - - - - 2 - 0x4 - PIN[%s] - Port pin register for all port GPIO pins - 0x2100 - 32 - read-write - 0 - 0xFFFFFFFF - - - PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. - 0 - 32 - read-write - - - - - 2 - 0x4 - MPIN[%s] - Masked port register for all port GPIO pins - 0x2180 - 32 - read-write - 0 - 0xFFFFFFFF - - - MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. - 0 - 32 - read-write - - - - - 2 - 0x4 - SET[%s] - Write: Set register for port. Read: output bits for port - 0x2200 - 32 - read-write - 0 - 0xFFFFFFFF - - - SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. - 0 - 32 - read-write - - - - - 2 - 0x4 - CLR[%s] - Clear port for all port GPIO pins - 0x2280 - 32 - write-only - 0 - 0 - - - CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit. - 0 - 32 - write-only - - - - - 2 - 0x4 - NOT[%s] - Toggle port for all port GPIO pins - 0x2300 - 32 - write-only - 0 - 0 - - - NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit. - 0 - 32 - write-only - - - - - 2 - 0x4 - DIRSET[%s] - Set pin direction bits for port - 0x2380 - 32 - write-only - 0 - 0 - - - DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit. - 0 - 32 - write-only - - - - - 2 - 0x4 - DIRCLR[%s] - Clear pin direction bits for port - 0x2400 - 32 - write-only - 0 - 0 - - - DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit. - 0 - 32 - write-only - - - - - 2 - 0x4 - DIRNOT[%s] - Toggle pin direction bits for port - 0x2480 - 32 - write-only - 0 - 0 - - - DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit. - 0 - 32 - write-only - - - - - - - USBHSD - USB1 High-speed Device Controller - USBHSD - 0x40094000 - - 0 - 0x38 - registers - - - USB1 - 47 - - - USB1_NEEDCLK - 48 - - - - DEVCMDSTAT - USB Device Command/Status register - 0 - 32 - read-write - 0x800 - 0xF7DBFFFF - - - DEV_ADDR - USB device address. - 0 - 7 - read-write - - - DEV_EN - USB device enable. - 7 - 1 - read-write - - - SETUP - SETUP token received. - 8 - 1 - read-write - - - FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:. - 9 - 1 - read-write - - - LPM_SUP - LPM Supported:. - 11 - 1 - read-write - - - INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP:. - 12 - 1 - read-write - - - INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP:. - 13 - 1 - read-write - - - INTONNAK_CO - Interrupt on NAK for control OUT EP:. - 14 - 1 - read-write - - - INTONNAK_CI - Interrupt on NAK for control IN EP:. - 15 - 1 - read-write - - - DCON - Device status - connect. - 16 - 1 - read-write - - - DSUS - Device status - suspend. - 17 - 1 - read-write - - - LPM_SUS - Device status - LPM Suspend. - 19 - 1 - read-write - - - LPM_REWP - LPM Remote Wake-up Enabled by USB host. - 20 - 1 - read-only - - - Speed - This field indicates the speed at which the device operates: 00b: reserved 01b: full-speed 10b: high-speed 11b: super-speed (reserved for future use). - 22 - 2 - read-only - - - DCON_C - Device status - connect change. - 24 - 1 - read-write - - - DSUS_C - Device status - suspend change. - 25 - 1 - read-write - - - DRES_C - Device status - reset change. - 26 - 1 - read-write - - - VBUS_DEBOUNCED - This bit indicates if VBUS is detected or not. - 28 - 1 - read-only - - - PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification. - 29 - 3 - read-write - - - DISABLE - Test mode disabled. - 0 - - - TEST_J - Test_J. - 0x1 - - - TEST_K - Test_K. - 0x2 - - - TEST_SE0_NAK - Test_SE0_NAK. - 0x3 - - - TEST_PACKET - Test_Packet. - 0x4 - - - TEST_FORCE_ENABLE - Test_Force_Enable. - 0x5 - - - - - - - INFO - USB Info register - 0x4 - 32 - read-only - 0x2000000 - 0xFFFF7FFF - - - FRAME_NR - Frame number. - 0 - 11 - read-only - - - ERR_CODE - The error code which last occurred:. - 11 - 4 - read-only - - - MINREV - Minor revision. - 16 - 8 - read-only - - - MAJREV - Major revision. - 24 - 8 - read-only - - - - - EPLISTSTART - USB EP Command/Status List start address - 0x8 - 32 - read-write - 0 - 0xFFFFFF00 - - - EP_LIST_PRG - Programmable portion of the USB EP Command/Status List address. - 8 - 12 - read-write - - - EP_LIST_FIXED - Fixed portion of USB EP Command/Status List address. - 20 - 12 - read-only - - - - - DATABUFSTART - USB Data buffer start address - 0xC - 32 - read-write - 0x41000000 - 0xFFFFFFFF - - - DA_BUF - Start address of the memory page where all endpoint data buffers are located. - 0 - 32 - read-write - - - - - LPM - USB Link Power Management register - 0x10 - 32 - read-write - 0 - 0x1FF - - - HIRD_HW - Host Initiated Resume Duration - HW. - 0 - 4 - read-only - - - HIRD_SW - Host Initiated Resume Duration - SW. - 4 - 4 - read-write - - - DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. - 8 - 1 - read-write - - - - - EPSKIP - USB Endpoint skip - 0x14 - 32 - read-write - 0 - 0xFFF - - - SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. - 0 - 12 - read-write - - - - - EPINUSE - USB Endpoint Buffer in use - 0x18 - 32 - read-write - 0 - 0xFFC - - - BUF - Buffer in use: This register has one bit per physical endpoint. - 2 - 10 - read-write - - - - - EPBUFCFG - USB Endpoint Buffer Configuration register - 0x1C - 32 - read-write - 0 - 0xFFC - - - BUF_SB - Buffer usage: This register has one bit per physical endpoint. - 2 - 10 - read-write - - - - - INTSTAT - USB interrupt status register - 0x20 - 32 - read-write - 0 - 0xC0000FFF - - - EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. - 0 - 1 - read-write - - - EP0IN - Interrupt status register bit for the Control EP0 IN direction. - 1 - 1 - read-write - - - EP1OUT - Interrupt status register bit for the EP1 OUT direction. - 2 - 1 - read-write - - - EP1IN - Interrupt status register bit for the EP1 IN direction. - 3 - 1 - read-write - - - EP2OUT - Interrupt status register bit for the EP2 OUT direction. - 4 - 1 - read-write - - - EP2IN - Interrupt status register bit for the EP2 IN direction. - 5 - 1 - read-write - - - EP3OUT - Interrupt status register bit for the EP3 OUT direction. - 6 - 1 - read-write - - - EP3IN - Interrupt status register bit for the EP3 IN direction. - 7 - 1 - read-write - - - EP4OUT - Interrupt status register bit for the EP4 OUT direction. - 8 - 1 - read-write - - - EP4IN - Interrupt status register bit for the EP4 IN direction. - 9 - 1 - read-write - - - EP5OUT - Interrupt status register bit for the EP5 OUT direction. - 10 - 1 - read-write - - - EP5IN - Interrupt status register bit for the EP5 IN direction. - 11 - 1 - read-write - - - FRAME_INT - Frame interrupt. - 30 - 1 - read-write - - - DEV_INT - Device status interrupt. - 31 - 1 - read-write - - - - - INTEN - USB interrupt enable register - 0x24 - 32 - read-write - 0 - 0xC0000FFF - - - EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. - 0 - 12 - read-write - - - FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. - 30 - 1 - read-write - - - DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. - 31 - 1 - read-write - - - - - INTSETSTAT - USB set interrupt status register - 0x28 - 32 - read-write - 0 - 0xC0000FFF - - - EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. - 0 - 12 - read-write - - - FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. - 30 - 1 - read-write - - - DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. - 31 - 1 - read-write - - - - - EPTOGGLE - USB Endpoint toggle register - 0x34 - 32 - read-only - 0 - 0x3FFFFFFF - - - TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. - 0 - 30 - read-only - - - - - - - CRC_ENGINE - CRC engine - CRC - 0x40095000 - - 0 - 0xC - registers - - - - MODE - CRC mode register - 0 - 32 - read-write - 0 - 0x3F - - - CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial - 0 - 2 - read-write - - - BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) - 2 - 1 - read-write - - - CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA - 3 - 1 - read-write - - - BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM - 4 - 1 - read-write - - - CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM - 5 - 1 - read-write - - - - - SEED - CRC seed register - 0x4 - 32 - read-write - 0xFFFF - 0xFFFFFFFF - - - CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses. - 0 - 32 - read-write - - - - - SUM - CRC checksum register - SUM_WR_DATA - 0x8 - 32 - read-only - 0xFFFF - 0xFFFFFFFF - - - CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. - 0 - 32 - read-only - - - - - WR_DATA - CRC data register - SUM_WR_DATA - 0x8 - 32 - write-only - 0 - 0 - - - CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions. - 0 - 32 - write-only - - - - - - - SDIF - SDMMC - SDIF - 0x4009B000 - - 0 - 0x300 - registers - - - SDIO - 42 - - - - CTRL - Control register - 0 - 32 - read-write - 0 - 0x2070FD7 - - - CONTROLLER_RESET - Controller reset. - 0 - 1 - read-write - - - FIFO_RESET - Fifo reset. - 1 - 1 - read-write - - - DMA_RESET - DMA reset. - 2 - 1 - read-write - - - INT_ENABLE - Global interrupt enable/disable bit. - 4 - 1 - read-write - - - READ_WAIT - Read/wait. - 6 - 1 - read-write - - - SEND_IRQ_RESPONSE - Send irq response. - 7 - 1 - read-write - - - ABORT_READ_DATA - Abort read data. - 8 - 1 - read-write - - - SEND_CCSD - Send ccsd. - 9 - 1 - read-write - - - SEND_AUTO_STOP_CCSD - Send auto stop ccsd. - 10 - 1 - read-write - - - CEATA_DEVICE_INTERRUPT_STATUS - CEATA device interrupt status. - 11 - 1 - read-write - - - CARD_VOLTAGE_A0 - Controls the state of the SD_VOLT0 pin. - 16 - 1 - read-write - - - CARD_VOLTAGE_A1 - Controls the state of the SD_VOLT1 pin. - 17 - 1 - read-write - - - CARD_VOLTAGE_A2 - Controls the state of the SD_VOLT2 pin. - 18 - 1 - read-write - - - USE_INTERNAL_DMAC - SD/MMC DMA use. - 25 - 1 - read-write - - - - - PWREN - Power Enable register - 0x4 - 32 - read-write - 0 - 0x3 - - - POWER_ENABLE0 - Power on/off switch for card 0; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card 0. - 0 - 1 - read-write - - - POWER_ENABLE1 - Power on/off switch for card 1; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card 1. - 1 - 1 - read-write - - - - - CLKDIV - Clock Divider register - 0x8 - 32 - read-write - 0 - 0xFF - - - CLK_DIVIDER0 - Clock divider-0 value. - 0 - 8 - read-write - - - - - CLKENA - Clock Enable register - 0x10 - 32 - read-write - 0 - 0x30003 - - - CCLK0_ENABLE - Clock-enable control for SD card 0 clock. - 0 - 1 - read-write - - - CCLK1_ENABLE - Clock-enable control for SD card 1 clock. - 1 - 1 - read-write - - - CCLK0_LOW_POWER - Low-power control for SD card 0 clock. - 16 - 1 - read-write - - - CCLK1_LOW_POWER - Low-power control for SD card 1 clock. - 17 - 1 - read-write - - - - - TMOUT - Time-out register - 0x14 - 32 - read-write - 0xFFFFFF40 - 0xFFFFFFFF - - - RESPONSE_TIMEOUT - Response time-out value. - 0 - 8 - read-write - - - DATA_TIMEOUT - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. - 8 - 24 - read-write - - - - - CTYPE - Card Type register - 0x18 - 32 - read-write - 0 - 0x30003 - - - CARD0_WIDTH0 - Indicates if card 0 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD0_WIDTH1 is not enabled (bit 16 in this register is set to 0). - 0 - 1 - read-write - - - CARD1_WIDTH0 - Indicates if card 1 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD1_WIDTH1 is not enabled (bit 16 in this register is set to 0). - 1 - 1 - read-write - - - CARD0_WIDTH1 - Indicates if card 0 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. - 16 - 1 - read-write - - - CARD1_WIDTH1 - Indicates if card 1 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. - 17 - 1 - read-write - - - - - BLKSIZ - Block Size register - 0x1C - 32 - read-write - 0x200 - 0xFFFF - - - BLOCK_SIZE - Block size. - 0 - 16 - read-write - - - - - BYTCNT - Byte Count register - 0x20 - 32 - read-write - 0x200 - 0xFFFFFFFF - - - BYTE_COUNT - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. - 0 - 32 - read-write - - - - - INTMASK - Interrupt Mask register - 0x24 - 32 - read-write - 0 - 0x1FFFF - - - CDET - Card detect. - 0 - 1 - read-write - - - RE - Response error. - 1 - 1 - read-write - - - CDONE - Command done. - 2 - 1 - read-write - - - DTO - Data transfer over. - 3 - 1 - read-write - - - TXDR - Transmit FIFO data request. - 4 - 1 - read-write - - - RXDR - Receive FIFO data request. - 5 - 1 - read-write - - - RCRC - Response CRC error. - 6 - 1 - read-write - - - DCRC - Data CRC error. - 7 - 1 - read-write - - - RTO - Response time-out. - 8 - 1 - read-write - - - DRTO - Data read time-out. - 9 - 1 - read-write - - - HTO - Data starvation-by-host time-out (HTO). - 10 - 1 - read-write - - - FRUN - FIFO underrun/overrun error. - 11 - 1 - read-write - - - HLE - Hardware locked write error. - 12 - 1 - read-write - - - SBE - Start-bit error. - 13 - 1 - read-write - - - ACD - Auto command done. - 14 - 1 - read-write - - - EBE - End-bit error (read)/Write no CRC. - 15 - 1 - read-write - - - SDIO_INT_MASK - Mask SDIO interrupt. - 16 - 1 - read-write - - - - - CMDARG - Command Argument register - 0x28 - 32 - read-write - 0 - 0xFFFFFFFF - - - CMD_ARG - Value indicates command argument to be passed to card. - 0 - 32 - read-write - - - - - CMD - Command register - 0x2C - 32 - read-write - 0 - 0xBFFFFFFF - - - CMD_INDEX - Command index. - 0 - 6 - read-write - - - RESPONSE_EXPECT - Response expect. - 6 - 1 - read-write - - - RESPONSE_LENGTH - Response length. - 7 - 1 - read-write - - - CHECK_RESPONSE_CRC - Check response CRC. - 8 - 1 - read-write - - - DATA_EXPECTED - Data expected. - 9 - 1 - read-write - - - READ_WRITE - read/write. - 10 - 1 - read-write - - - TRANSFER_MODE - Transfer mode. - 11 - 1 - read-write - - - SEND_AUTO_STOP - Send auto stop. - 12 - 1 - read-write - - - WAIT_PRVDATA_COMPLETE - Wait prvdata complete. - 13 - 1 - read-write - - - STOP_ABORT_CMD - Stop abort command. - 14 - 1 - read-write - - - SEND_INITIALIZATION - Send initialization. - 15 - 1 - read-write - - - CARD_NUMBER - Specifies the card number of SDCARD for which the current Command is being executed - 16 - 5 - read-write - - - CARD0 - Command will be execute on SDCARD 0 - 0 - - - CARD1 - Command will be execute on SDCARD 1 - 0x1 - - - - - UPDATE_CLOCK_REGISTERS_ONLY - Update clock registers only. - 21 - 1 - read-write - - - READ_CEATA_DEVICE - Read ceata device. - 22 - 1 - read-write - - - CCS_EXPECTED - CCS expected. - 23 - 1 - read-write - - - ENABLE_BOOT - Enable Boot - this bit should be set only for mandatory boot mode. - 24 - 1 - read-write - - - EXPECT_BOOT_ACK - Expect Boot Acknowledge. - 25 - 1 - read-write - - - DISABLE_BOOT - Disable Boot. - 26 - 1 - read-write - - - BOOT_MODE - Boot Mode. - 27 - 1 - read-write - - - VOLT_SWITCH - Voltage switch bit. - 28 - 1 - read-write - - - USE_HOLD_REG - Use Hold Register. - 29 - 1 - read-write - - - START_CMD - Start command. - 31 - 1 - read-write - - - - - 4 - 0x4 - RESP[%s] - Response register - 0x30 - 32 - read-write - 0 - 0xFFFFFFFF - - - RESPONSE - Bits of response. - 0 - 32 - read-write - - - - - MINTSTS - Masked Interrupt Status register - 0x40 - 32 - read-write - 0 - 0x1FFFF - - - CDET - Card detect. - 0 - 1 - read-write - - - RE - Response error. - 1 - 1 - read-write - - - CDONE - Command done. - 2 - 1 - read-write - - - DTO - Data transfer over. - 3 - 1 - read-write - - - TXDR - Transmit FIFO data request. - 4 - 1 - read-write - - - RXDR - Receive FIFO data request. - 5 - 1 - read-write - - - RCRC - Response CRC error. - 6 - 1 - read-write - - - DCRC - Data CRC error. - 7 - 1 - read-write - - - RTO - Response time-out. - 8 - 1 - read-write - - - DRTO - Data read time-out. - 9 - 1 - read-write - - - HTO - Data starvation-by-host time-out (HTO). - 10 - 1 - read-write - - - FRUN - FIFO underrun/overrun error. - 11 - 1 - read-write - - - HLE - Hardware locked write error. - 12 - 1 - read-write - - - SBE - Start-bit error. - 13 - 1 - read-write - - - ACD - Auto command done. - 14 - 1 - read-write - - - EBE - End-bit error (read)/write no CRC. - 15 - 1 - read-write - - - SDIO_INTERRUPT - Interrupt from SDIO card. - 16 - 1 - read-write - - - - - RINTSTS - Raw Interrupt Status register - 0x44 - 32 - read-write - 0 - 0x1FFFF - - - CDET - Card detect. - 0 - 1 - read-write - - - RE - Response error. - 1 - 1 - read-write - - - CDONE - Command done. - 2 - 1 - read-write - - - DTO - Data transfer over. - 3 - 1 - read-write - - - TXDR - Transmit FIFO data request. - 4 - 1 - read-write - - - RXDR - Receive FIFO data request. - 5 - 1 - read-write - - - RCRC - Response CRC error. - 6 - 1 - read-write - - - DCRC - Data CRC error. - 7 - 1 - read-write - - - RTO_BAR - Response time-out (RTO)/Boot Ack Received (BAR). - 8 - 1 - read-write - - - DRTO_BDS - Data read time-out (DRTO)/Boot Data Start (BDS). - 9 - 1 - read-write - - - HTO - Data starvation-by-host time-out (HTO). - 10 - 1 - read-write - - - FRUN - FIFO underrun/overrun error. - 11 - 1 - read-write - - - HLE - Hardware locked write error. - 12 - 1 - read-write - - - SBE - Start-bit error. - 13 - 1 - read-write - - - ACD - Auto command done. - 14 - 1 - read-write - - - EBE - End-bit error (read)/write no CRC. - 15 - 1 - read-write - - - SDIO_INTERRUPT - Interrupt from SDIO card. - 16 - 1 - read-write - - - - - STATUS - Status register - 0x48 - 32 - read-write - 0x406 - 0xFFFFFFFF - - - FIFO_RX_WATERMARK - FIFO reached Receive watermark level; not qualified with data transfer. - 0 - 1 - read-write - - - FIFO_TX_WATERMARK - FIFO reached Transmit watermark level; not qualified with data transfer. - 1 - 1 - read-write - - - FIFO_EMPTY - FIFO is empty status. - 2 - 1 - read-write - - - FIFO_FULL - FIFO is full status. - 3 - 1 - read-write - - - CMDFSMSTATES - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The command FSM state is represented using 19 bits. - 4 - 4 - read-write - - - DATA_3_STATUS - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present. - 8 - 1 - read-write - - - DATA_BUSY - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy. - 9 - 1 - read-write - - - DATA_STATE_MC_BUSY - Data transmit or receive state-machine is busy. - 10 - 1 - read-write - - - RESPONSE_INDEX - Index of previous response, including any auto-stop sent by core. - 11 - 6 - read-write - - - FIFO_COUNT - FIFO count - Number of filled locations in FIFO. - 17 - 13 - read-write - - - DMA_ACK - DMA acknowledge signal state. - 30 - 1 - read-write - - - DMA_REQ - DMA request signal state. - 31 - 1 - read-write - - - - - FIFOTH - FIFO Threshold Watermark register - 0x4C - 32 - read-write - 0x1F0000 - 0x7FFF0FFF - - - TX_WMARK - FIFO threshold watermark level when transmitting data to card. - 0 - 12 - read-write - - - RX_WMARK - FIFO threshold watermark level when receiving data to card. - 16 - 12 - read-write - - - DMA_MTS - Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE. - 28 - 3 - read-write - - - - - CDETECT - Card Detect register - 0x50 - 32 - read-write - 0 - 0x1 - - - CARD0_DETECT - Card 0 detect - 0 - 1 - read-write - - - CARD1_DETECT - Card 1 detect - 1 - 1 - read-write - - - - - WRTPRT - Write Protect register - 0x54 - 32 - read-write - 0 - 0x1 - - - WRITE_PROTECT - Write protect. - 0 - 1 - read-write - - - - - TCBCNT - Transferred CIU Card Byte Count register - 0x5C - 32 - read-write - 0 - 0xFFFFFFFF - - - TRANS_CARD_BYTE_COUNT - Number of bytes transferred by CIU unit to card. - 0 - 32 - read-write - - - - - TBBCNT - Transferred Host to BIU-FIFO Byte Count register - 0x60 - 32 - read-write - 0 - 0xFFFFFFFF - - - TRANS_FIFO_BYTE_COUNT - Number of bytes transferred between Host/DMA memory and BIU FIFO. - 0 - 32 - read-write - - - - - DEBNCE - Debounce Count register - 0x64 - 32 - read-write - 0xFFFFFF - 0xFFFFFF - - - DEBOUNCE_COUNT - Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms. - 0 - 24 - read-write - - - - - RST_N - Hardware Reset - 0x78 - 32 - read-write - 0x1 - 0x1 - - - CARD_RESET - Hardware reset. - 0 - 1 - read-write - - - - - BMOD - Bus Mode register - 0x80 - 32 - read-write - 0 - 0x7FF - - - SWR - Software Reset. - 0 - 1 - read-write - - - FB - Fixed Burst. - 1 - 1 - read-write - - - DSL - Descriptor Skip Length. - 2 - 5 - read-write - - - DE - SD/MMC DMA Enable. - 7 - 1 - read-write - - - PBL - Programmable Burst Length. - 8 - 3 - read-write - - - - - PLDMND - Poll Demand register - 0x84 - 32 - read-write - 0 - 0xFFFFFFFF - - - PD - Poll Demand. - 0 - 32 - read-write - - - - - DBADDR - Descriptor List Base Address register - 0x88 - 32 - read-write - 0 - 0xFFFFFFFF - - - SDL - Start of Descriptor List. - 0 - 32 - read-write - - - - - IDSTS - Internal DMAC Status register - 0x8C - 32 - read-write - 0 - 0x1FF37 - - - TI - Transmit Interrupt. - 0 - 1 - read-write - - - RI - Receive Interrupt. - 1 - 1 - read-write - - - FBE - Fatal Bus Error Interrupt. - 2 - 1 - read-write - - - DU - Descriptor Unavailable Interrupt. - 4 - 1 - read-write - - - CES - Card Error Summary. - 5 - 1 - read-write - - - NIS - Normal Interrupt Summary. - 8 - 1 - read-write - - - AIS - Abnormal Interrupt Summary. - 9 - 1 - read-write - - - EB - Error Bits. - 10 - 3 - read-write - - - FSM - DMAC state machine present state. - 13 - 4 - read-write - - - - - IDINTEN - Internal DMAC Interrupt Enable register - 0x90 - 32 - read-write - 0 - 0x337 - - - TI - Transmit Interrupt Enable. - 0 - 1 - read-write - - - RI - Receive Interrupt Enable. - 1 - 1 - read-write - - - FBE - Fatal Bus Error Enable. - 2 - 1 - read-write - - - DU - Descriptor Unavailable Interrupt. - 4 - 1 - read-write - - - CES - Card Error summary Interrupt Enable. - 5 - 1 - read-write - - - NIS - Normal Interrupt Summary Enable. - 8 - 1 - read-write - - - AIS - Abnormal Interrupt Summary Enable. - 9 - 1 - read-write - - - - - DSCADDR - Current Host Descriptor Address register - 0x94 - 32 - read-write - 0 - 0xFFFFFFFF - - - HDA - Host Descriptor Address Pointer. - 0 - 32 - read-write - - - - - BUFADDR - Current Buffer Descriptor Address register - 0x98 - 32 - read-write - 0 - 0xFFFFFFFF - - - HBA - Host Buffer Address Pointer. - 0 - 32 - read-write - - - - - CARDTHRCTL - Card Threshold Control - 0x100 - 32 - read-write - 0 - 0xFF0003 - - - CARDRDTHREN - Card Read Threshold Enable. - 0 - 1 - read-write - - - BSYCLRINTEN - Busy Clear Interrupt Enable. - 1 - 1 - read-write - - - CARDTHRESHOLD - Card Threshold size. - 16 - 8 - read-write - - - - - BACKENDPWR - Power control - 0x104 - 32 - read-write - 0 - 0x1 - - - BACKENDPWR - Back-end Power control for card application. - 0 - 1 - read-write - - - - - 64 - 0x4 - FIFO[%s] - SDIF FIFO - 0x200 - 32 - read-write - 0 - 0xFFFFFFFF - - - DATA - SDIF FIFO. - 0 - 32 - read-write - - - - - - - DBGMAILBOX - MCU Debugger Mailbox - DBGMAILBOX - 0x4009C000 - - 0 - 0x100 - registers - - - - CSW - CRC mode register - 0 - 32 - read-write - 0 - 0x3F - - - RESYNCH_REQ - Debugger will set this bit to 1 to request a resynchronrisation - 0 - 1 - read-write - - - REQ_PENDING - Request is pending from debugger (i.e unread value in REQUEST) - 1 - 1 - read-write - - - DBG_OR_ERR - Debugger overrun error (previous REQUEST overwritten before being picked up by ROM) - 2 - 1 - read-write - - - AHB_OR_ERR - AHB overrun Error (Return value overwritten by ROM) - 3 - 1 - read-write - - - SOFT_RESET - Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to this bit will cause a soft reset for DM. - 4 - 1 - read-write - - - CHIP_RESET_REQ - Write only bit. Once written will cause the chip to reset (note that the DM is not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event) - 5 - 1 - write-only - - - - - REQUEST - CRC seed register - 0x4 - 32 - read-write - 0xFFFF - 0xFFFFFFFF - - - REQ - Request Value - 0 - 32 - read-write - - - - - RETURN - Return value from ROM. - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - RET - The Return value from ROM. - 0 - 32 - read-write - - - - - ID - Identification register - 0xFC - 32 - read-only - 0x2A0000 - 0xFFFFFFFF - - - ID - Identification value. - 0 - 32 - read-only - - - - - - - ADC0 - ADC - ADC - 0x400A0000 - - 0 - 0x1000 - registers - - - ADC0 - 22 - - - - VERID - Version ID Register - 0 - 32 - read-only - 0x1002C0B - 0xFFFFFFFF - - - RES - Resolution - 0 - 1 - read-only - - - RES_0 - Up to 13-bit differential/12-bit single ended resolution supported. - 0 - - - RES_1 - Up to 16-bit differential/16-bit single ended resolution supported. - 0x1 - - - - - DIFFEN - Differential Supported - 1 - 1 - read-only - - - DIFFEN_0 - Differential operation not supported. - 0 - - - DIFFEN_1 - Differential operation supported. CMDLa[CTYPE] controls fields implemented. - 0x1 - - - - - MVI - Multi Vref Implemented - 3 - 1 - read-only - - - MVI_0 - Single voltage reference high (VREFH) input supported. - 0 - - - MVI_1 - Multiple voltage reference high (VREFH) inputs supported. - 0x1 - - - - - CSW - Channel Scale Width - 4 - 3 - read-only - - - CSW_0 - Channel scaling not supported. - 0 - - - CSW_1 - Channel scaling supported. 1-bit CSCALE control field. - 0x1 - - - CSW_6 - Channel scaling supported. 6-bit CSCALE control field. - 0x6 - - - - - VR1RNGI - Voltage Reference 1 Range Control Bit Implemented - 8 - 1 - read-only - - - VR1RNGI_0 - Range control not required. CFG[VREF1RNG] is not implemented. - 0 - - - VR1RNGI_1 - Range control required. CFG[VREF1RNG] is implemented. - 0x1 - - - - - IADCKI - Internal ADC Clock implemented - 9 - 1 - read-only - - - IADCKI_0 - Internal clock source not implemented. - 0 - - - IADCKI_1 - Internal clock source (and CFG[ADCKEN]) implemented. - 0x1 - - - - - CALOFSI - Calibration Function Implemented - 10 - 1 - read-only - - - CALOFSI_0 - Calibration Not Implemented. - 0 - - - CALOFSI_1 - Calibration Implemented. - 0x1 - - - - - NUM_SEC - Number of Single Ended Outputs Supported - 11 - 1 - read-only - - - NUM_SEC_0 - This design supports one single ended conversion at a time. - 0 - - - NUM_SEC_1 - This design supports two simultanious single ended conversions. - 0x1 - - - - - NUM_FIFO - Number of FIFOs - 12 - 3 - read-only - - - NUM_FIFO_0 - N/A - 0 - - - NUM_FIFO_1 - This design supports one result FIFO. - 0x1 - - - NUM_FIFO_2 - This design supports two result FIFOs. - 0x2 - - - NUM_FIFO_3 - This design supports three result FIFOs. - 0x3 - - - NUM_FIFO_4 - This design supports four result FIFOs. - 0x4 - - - - - MINOR - Minor Version Number - 16 - 8 - read-only - - - MAJOR - Major Version Number - 24 - 8 - read-only - - - - - PARAM - Parameter Register - 0x4 - 32 - read-only - 0xF041010 - 0xFFFFFFFF - - - TRIG_NUM - Trigger Number - 0 - 8 - read-only - - - FIFOSIZE - Result FIFO Depth - 8 - 8 - read-only - - - FIFOSIZE_1 - Result FIFO depth = 1 dataword. - 0x1 - - - FIFOSIZE_4 - Result FIFO depth = 4 datawords. - 0x4 - - - FIFOSIZE_8 - Result FIFO depth = 8 datawords. - 0x8 - - - FIFOSIZE_16 - Result FIFO depth = 16 datawords. - 0x10 - - - FIFOSIZE_32 - Result FIFO depth = 32 datawords. - 0x20 - - - FIFOSIZE_64 - Result FIFO depth = 64 datawords. - 0x40 - - - - - CV_NUM - Compare Value Number - 16 - 8 - read-only - - - CMD_NUM - Command Buffer Number - 24 - 8 - read-only - - - - - CTRL - ADC Control Register - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCEN - ADC Enable - 0 - 1 - read-write - - - ADCEN_0 - ADC is disabled. - 0 - - - ADCEN_1 - ADC is enabled. - 0x1 - - - - - RST - Software Reset - 1 - 1 - read-write - - - RST_0 - ADC logic is not reset. - 0 - - - RST_1 - ADC logic is reset. - 0x1 - - - - - DOZEN - Doze Enable - 2 - 1 - read-write - - - DOZEN_0 - ADC is enabled in Doze mode. - 0 - - - DOZEN_1 - ADC is disabled in Doze mode. - 0x1 - - - - - CAL_REQ - Auto-Calibration Request - 3 - 1 - read-write - - - CAL_REQ_0 - No request for auto-calibration has been made. - 0 - - - CAL_REQ_1 - A request for auto-calibration has been made - 0x1 - - - - - CALOFS - Configure for offset calibration function - 4 - 1 - read-write - - - CALOFS_0 - Calibration function disabled - 0 - - - CALOFS_1 - Request for offset calibration function - 0x1 - - - - - RSTFIFO0 - Reset FIFO 0 - 8 - 1 - read-write - - - RSTFIFO0_0 - No effect. - 0 - - - RSTFIFO0_1 - FIFO 0 is reset. - 0x1 - - - - - RSTFIFO1 - Reset FIFO 1 - 9 - 1 - read-write - - - RSTFIFO1_0 - No effect. - 0 - - - RSTFIFO1_1 - FIFO 1 is reset. - 0x1 - - - - - CAL_AVGS - Auto-Calibration Averages - 16 - 3 - read-write - - - CAL_AVGS_0 - Single conversion. - 0 - - - CAL_AVGS_1 - 2 conversions averaged. - 0x1 - - - CAL_AVGS_2 - 4 conversions averaged. - 0x2 - - - CAL_AVGS_3 - 8 conversions averaged. - 0x3 - - - CAL_AVGS_4 - 16 conversions averaged. - 0x4 - - - CAL_AVGS_5 - 32 conversions averaged. - 0x5 - - - CAL_AVGS_6 - 64 conversions averaged. - 0x6 - - - CAL_AVGS_7 - 128 conversions averaged. - 0x7 - - - - - - - STAT - ADC Status Register - 0x14 - 32 - read-write - 0 - 0xFFFFFFFF - - - RDY0 - Result FIFO 0 Ready Flag - 0 - 1 - read-only - - - RDY0_0 - Result FIFO 0 data level not above watermark level. - 0 - - - RDY0_1 - Result FIFO 0 holding data above watermark level. - 0x1 - - - - - FOF0 - Result FIFO 0 Overflow Flag - 1 - 1 - read-write - oneToClear - - - FOF0_0 - No result FIFO 0 overflow has occurred since the last time the flag was cleared. - 0 - - - FOF0_1 - At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. - 0x1 - - - - - RDY1 - Result FIFO1 Ready Flag - 2 - 1 - read-only - - - RDY1_0 - Result FIFO1 data level not above watermark level. - 0 - - - RDY1_1 - Result FIFO1 holding data above watermark level. - 0x1 - - - - - FOF1 - Result FIFO1 Overflow Flag - 3 - 1 - read-write - oneToClear - - - FOF1_0 - No result FIFO1 overflow has occurred since the last time the flag was cleared. - 0 - - - FOF1_1 - At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - 0x1 - - - - - TEXC_INT - Interrupt Flag For High Priority Trigger Exception - 8 - 1 - read-write - oneToClear - - - TEXC_INT_0 - No trigger exceptions have occurred. - 0 - - - TEXC_INT_1 - A trigger exception has occurred and is pending acknowledgement. - 0x1 - - - - - TCOMP_INT - Interrupt Flag For Trigger Completion - 9 - 1 - read-write - oneToClear - - - TCOMP_INT_0 - Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. - 0 - - - TCOMP_INT_1 - Trigger sequence has been completed and all data is stored in the associated FIFO. - 0x1 - - - - - CAL_RDY - Calibration Ready - 10 - 1 - read-only - - - CAL_RDY_0 - Calibration is incomplete or hasn't been ran. - 0 - - - CAL_RDY_1 - The ADC is calibrated. - 0x1 - - - - - ADC_ACTIVE - ADC Active - 11 - 1 - read-only - - - ADC_ACTIVE_0 - The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. - 0 - - - ADC_ACTIVE_1 - The ADC is processing a conversion, running through the power up delay, or servicing a trigger. - 0x1 - - - - - TRGACT - Trigger Active - 16 - 4 - read-only - - - TRGACT_0 - Command (sequence) associated with Trigger 0 currently being executed. - 0 - - - TRGACT_1 - Command (sequence) associated with Trigger 1 currently being executed. - 0x1 - - - TRGACT_2 - Command (sequence) associated with Trigger 2 currently being executed. - 0x2 - - - TRGACT_3 - Command (sequence) from the associated Trigger number is currently being executed. - 0x3 - - - TRGACT_4 - Command (sequence) from the associated Trigger number is currently being executed. - 0x4 - - - TRGACT_5 - Command (sequence) from the associated Trigger number is currently being executed. - 0x5 - - - TRGACT_6 - Command (sequence) from the associated Trigger number is currently being executed. - 0x6 - - - TRGACT_7 - Command (sequence) from the associated Trigger number is currently being executed. - 0x7 - - - TRGACT_8 - Command (sequence) from the associated Trigger number is currently being executed. - 0x8 - - - TRGACT_9 - Command (sequence) from the associated Trigger number is currently being executed. - 0x9 - - - - - CMDACT - Command Active - 24 - 4 - read-only - - - CMDACT_0 - No command is currently in progress. - 0 - - - CMDACT_1 - Command 1 currently being executed. - 0x1 - - - CMDACT_2 - Command 2 currently being executed. - 0x2 - - - CMDACT_3 - Associated command number is currently being executed. - 0x3 - - - CMDACT_4 - Associated command number is currently being executed. - 0x4 - - - CMDACT_5 - Associated command number is currently being executed. - 0x5 - - - CMDACT_6 - Associated command number is currently being executed. - 0x6 - - - CMDACT_7 - Associated command number is currently being executed. - 0x7 - - - CMDACT_8 - Associated command number is currently being executed. - 0x8 - - - CMDACT_9 - Associated command number is currently being executed. - 0x9 - - - - - - - IE - Interrupt Enable Register - 0x18 - 32 - read-write - 0 - 0xFFFFFFFF - - - FWMIE0 - FIFO 0 Watermark Interrupt Enable - 0 - 1 - read-write - - - FWMIE0_0 - FIFO 0 watermark interrupts are not enabled. - 0 - - - FWMIE0_1 - FIFO 0 watermark interrupts are enabled. - 0x1 - - - - - FOFIE0 - Result FIFO 0 Overflow Interrupt Enable - 1 - 1 - read-write - - - FOFIE0_0 - FIFO 0 overflow interrupts are not enabled. - 0 - - - FOFIE0_1 - FIFO 0 overflow interrupts are enabled. - 0x1 - - - - - FWMIE1 - FIFO1 Watermark Interrupt Enable - 2 - 1 - read-write - - - FWMIE1_0 - FIFO1 watermark interrupts are not enabled. - 0 - - - FWMIE1_1 - FIFO1 watermark interrupts are enabled. - 0x1 - - - - - FOFIE1 - Result FIFO1 Overflow Interrupt Enable - 3 - 1 - read-write - - - FOFIE1_0 - No result FIFO1 overflow has occurred since the last time the flag was cleared. - 0 - - - FOFIE1_1 - At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - 0x1 - - - - - TEXC_IE - Trigger Exception Interrupt Enable - 8 - 1 - read-write - - - TEXC_IE_0 - Trigger exception interrupts are disabled. - 0 - - - TEXC_IE_1 - Trigger exception interrupts are enabled. - 0x1 - - - - - TCOMP_IE - Trigger Completion Interrupt Enable - 16 - 16 - read-write - - - TCOMP_IE_0 - Trigger completion interrupts are disabled. - 0 - - - TCOMP_IE_1 - Trigger completion interrupts are enabled for trigger source 0 only. - 0x1 - - - TCOMP_IE_2 - Trigger completion interrupts are enabled for trigger source 1 only. - 0x2 - - - TCOMP_IE_3 - Associated trigger completion interrupts are enabled. - 0x3 - - - TCOMP_IE_4 - Associated trigger completion interrupts are enabled. - 0x4 - - - TCOMP_IE_5 - Associated trigger completion interrupts are enabled. - 0x5 - - - TCOMP_IE_6 - Associated trigger completion interrupts are enabled. - 0x6 - - - TCOMP_IE_7 - Associated trigger completion interrupts are enabled. - 0x7 - - - TCOMP_IE_8 - Associated trigger completion interrupts are enabled. - 0x8 - - - TCOMP_IE_9 - Associated trigger completion interrupts are enabled. - 0x9 - - - TCOMP_IE_65535 - Trigger completion interrupts are enabled for every trigger source. - 0xFFFF - - - - - - - DE - DMA Enable Register - 0x1C - 32 - read-write - 0 - 0xFFFFFFFF - - - FWMDE0 - FIFO 0 Watermark DMA Enable - 0 - 1 - read-write - - - FWMDE0_0 - DMA request disabled. - 0 - - - FWMDE0_1 - DMA request enabled. - 0x1 - - - - - FWMDE1 - FIFO1 Watermark DMA Enable - 1 - 1 - read-write - - - FWMDE1_0 - DMA request disabled. - 0 - - - FWMDE1_1 - DMA request enabled. - 0x1 - - - - - - - CFG - ADC Configuration Register - 0x20 - 32 - read-write - 0x800000 - 0xFFFFFFFF - - - TPRICTRL - ADC trigger priority control - 0 - 2 - read-write - - - TPRICTRL_0 - If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started. - 0 - - - TPRICTRL_1 - If a higher priority trigger is received during command processing, the current command is stopped after after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. - 0x1 - - - TPRICTRL_2 - If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger. - 0x2 - - - - - PWRSEL - Power Configuration Select - 4 - 2 - read-write - - - PWRSEL_0 - Lowest power setting. - 0 - - - PWRSEL_1 - Higher power setting than 0b0. - 0x1 - - - PWRSEL_2 - Higher power setting than 0b1. - 0x2 - - - PWRSEL_3 - Highest power setting. - 0x3 - - - - - REFSEL - Voltage Reference Selection - 6 - 2 - read-write - - - REFSEL_0 - (Default) Option 1 setting. - 0 - - - REFSEL_1 - Option 2 setting. - 0x1 - - - REFSEL_2 - Option 3 setting. - 0x2 - - - - - TRES - Trigger Resume Enable - 8 - 1 - read-write - - - TRES_0 - Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. - 0 - - - TRES_1 - Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. - 0x1 - - - - - TCMDRES - Trigger Command Resume - 9 - 1 - read-write - - - TCMDRES_0 - Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. - 0 - - - TCMDRES_1 - Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. - 0x1 - - - - - HPT_EXDI - High Priority Trigger Exception Disable - 10 - 1 - read-write - - - HPT_EXDI_0 - High priority trigger exceptions are enabled. - 0 - - - HPT_EXDI_1 - High priority trigger exceptions are disabled. - 0x1 - - - - - PUDLY - Power Up Delay - 16 - 8 - read-write - - - PWREN - ADC Analog Pre-Enable - 28 - 1 - read-write - - - PWREN_0 - ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. - 0 - - - PWREN_1 - ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog will remain pre-enabled, and no additional delays will be executed. - 0x1 - - - - - - - PAUSE - ADC Pause Register - 0x24 - 32 - read-write - 0 - 0xFFFFFFFF - - - PAUSEDLY - Pause Delay - 0 - 9 - read-write - - - PAUSEEN - PAUSE Option Enable - 31 - 1 - read-write - - - PAUSEEN_0 - Pause operation disabled - 0 - - - PAUSEEN_1 - Pause operation enabled - 0x1 - - - - - - - SWTRIG - Software Trigger Register - 0x34 - 32 - read-write - 0 - 0xFFFFFFFF - - - SWT0 - Software trigger 0 event - 0 - 1 - read-write - - - SWT0_0 - No trigger 0 event generated. - 0 - - - SWT0_1 - Trigger 0 event generated. - 0x1 - - - - - SWT1 - Software trigger 1 event - 1 - 1 - read-write - - - SWT1_0 - No trigger 1 event generated. - 0 - - - SWT1_1 - Trigger 1 event generated. - 0x1 - - - - - SWT2 - Software trigger 2 event - 2 - 1 - read-write - - - SWT2_0 - No trigger 2 event generated. - 0 - - - SWT2_1 - Trigger 2 event generated. - 0x1 - - - - - SWT3 - Software trigger 3 event - 3 - 1 - read-write - - - SWT3_0 - No trigger 3 event generated. - 0 - - - SWT3_1 - Trigger 3 event generated. - 0x1 - - - - - SWT4 - Software trigger 4 event - 4 - 1 - read-write - - - SWT4_0 - No trigger 4 event generated. - 0 - - - SWT4_1 - Trigger 4 event generated. - 0x1 - - - - - SWT5 - Software trigger 5 event - 5 - 1 - read-write - - - SWT5_0 - No trigger 5 event generated. - 0 - - - SWT5_1 - Trigger 5 event generated. - 0x1 - - - - - SWT6 - Software trigger 6 event - 6 - 1 - read-write - - - SWT6_0 - No trigger 6 event generated. - 0 - - - SWT6_1 - Trigger 6 event generated. - 0x1 - - - - - SWT7 - Software trigger 7 event - 7 - 1 - read-write - - - SWT7_0 - No trigger 7 event generated. - 0 - - - SWT7_1 - Trigger 7 event generated. - 0x1 - - - - - SWT8 - Software trigger 8 event - 8 - 1 - read-write - - - SWT8_0 - No trigger 8 event generated. - 0 - - - SWT8_1 - Trigger 8 event generated. - 0x1 - - - - - SWT9 - Software trigger 9 event - 9 - 1 - read-write - - - SWT9_0 - No trigger 9 event generated. - 0 - - - SWT9_1 - Trigger 9 event generated. - 0x1 - - - - - SWT10 - Software trigger 10 event - 10 - 1 - read-write - - - SWT10_0 - No trigger 10 event generated. - 0 - - - SWT10_1 - Trigger 10 event generated. - 0x1 - - - - - SWT11 - Software trigger 11 event - 11 - 1 - read-write - - - SWT11_0 - No trigger 11 event generated. - 0 - - - SWT11_1 - Trigger 11 event generated. - 0x1 - - - - - SWT12 - Software trigger 12 event - 12 - 1 - read-write - - - SWT12_0 - No trigger 12 event generated. - 0 - - - SWT12_1 - Trigger 12 event generated. - 0x1 - - - - - SWT13 - Software trigger 13 event - 13 - 1 - read-write - - - SWT13_0 - No trigger 13 event generated. - 0 - - - SWT13_1 - Trigger 13 event generated. - 0x1 - - - - - SWT14 - Software trigger 14 event - 14 - 1 - read-write - - - SWT14_0 - No trigger 14 event generated. - 0 - - - SWT14_1 - Trigger 14 event generated. - 0x1 - - - - - SWT15 - Software trigger 15 event - 15 - 1 - read-write - - - SWT15_0 - No trigger 15 event generated. - 0 - - - SWT15_1 - Trigger 15 event generated. - 0x1 - - - - - - - TSTAT - Trigger Status Register - 0x38 - 32 - read-write - 0 - 0xFFFFFFFF - - - TEXC_NUM - Trigger Exception Number - 0 - 16 - read-write - oneToClear - - - TEXC_NUM_0 - No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. - 0 - - - TEXC_NUM_1 - Trigger 0 has been interrupted by a high priority exception. - 0x1 - - - TEXC_NUM_2 - Trigger 1 has been interrupted by a high priority exception. - 0x2 - - - TEXC_NUM_3 - Associated trigger sequence has interrupted by a high priority exception. - 0x3 - - - TEXC_NUM_4 - Associated trigger sequence has interrupted by a high priority exception. - 0x4 - - - TEXC_NUM_5 - Associated trigger sequence has interrupted by a high priority exception. - 0x5 - - - TEXC_NUM_6 - Associated trigger sequence has interrupted by a high priority exception. - 0x6 - - - TEXC_NUM_7 - Associated trigger sequence has interrupted by a high priority exception. - 0x7 - - - TEXC_NUM_8 - Associated trigger sequence has interrupted by a high priority exception. - 0x8 - - - TEXC_NUM_9 - Associated trigger sequence has interrupted by a high priority exception. - 0x9 - - - TEXC_NUM_65535 - Every trigger sequence has been interrupted by a high priority exception. - 0xFFFF - - - - - TCOMP_FLAG - Trigger Completion Flag - 16 - 16 - read-write - oneToClear - - - TCOMP_FLAG_0 - No triggers have been completed. Trigger completion interrupts are disabled. - 0 - - - TCOMP_FLAG_1 - Trigger 0 has been completed and triger 0 has enabled completion interrupts. - 0x1 - - - TCOMP_FLAG_2 - Trigger 1 has been completed and triger 1 has enabled completion interrupts. - 0x2 - - - TCOMP_FLAG_3 - Associated trigger sequence has completed and has enabled completion interrupts. - 0x3 - - - TCOMP_FLAG_4 - Associated trigger sequence has completed and has enabled completion interrupts. - 0x4 - - - TCOMP_FLAG_5 - Associated trigger sequence has completed and has enabled completion interrupts. - 0x5 - - - TCOMP_FLAG_6 - Associated trigger sequence has completed and has enabled completion interrupts. - 0x6 - - - TCOMP_FLAG_7 - Associated trigger sequence has completed and has enabled completion interrupts. - 0x7 - - - TCOMP_FLAG_8 - Associated trigger sequence has completed and has enabled completion interrupts. - 0x8 - - - TCOMP_FLAG_9 - Associated trigger sequence has completed and has enabled completion interrupts. - 0x9 - - - TCOMP_FLAG_65535 - Every trigger sequence has been completed and every trigger has enabled completion interrupts. - 0xFFFF - - - - - - - OFSTRIM - ADC Offset Trim Register - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - OFSTRIM_A - Trim for offset - 0 - 5 - read-write - - - OFSTRIM_B - Trim for offset - 16 - 5 - read-write - - - - - 16 - 0x4 - TCTRL[%s] - Trigger Control Register - 0xA0 - 32 - read-write - 0 - 0xFFFFFFFF - - - HTEN - Trigger enable - 0 - 1 - read-write - - - HTEN_0 - Hardware trigger source disabled - 0 - - - HTEN_1 - Hardware trigger source enabled - 0x1 - - - - - FIFO_SEL_A - SAR Result Destination For Channel A - 1 - 1 - read-write - - - FIFO_SEL_A_0 - Result written to FIFO 0 - 0 - - - FIFO_SEL_A_1 - Result written to FIFO 1 - 0x1 - - - - - FIFO_SEL_B - SAR Result Destination For Channel B - 2 - 1 - read-write - - - FIFO_SEL_B_0 - Result written to FIFO 0 - 0 - - - FIFO_SEL_B_1 - Result written to FIFO 1 - 0x1 - - - - - TPRI - Trigger priority setting - 8 - 4 - read-write - - - TPRI_0 - Set to highest priority, Level 1 - 0 - - - TPRI_1 - Set to corresponding priority level - 0x1 - - - TPRI_2 - Set to corresponding priority level - 0x2 - - - TPRI_3 - Set to corresponding priority level - 0x3 - - - TPRI_4 - Set to corresponding priority level - 0x4 - - - TPRI_5 - Set to corresponding priority level - 0x5 - - - TPRI_6 - Set to corresponding priority level - 0x6 - - - TPRI_7 - Set to corresponding priority level - 0x7 - - - TPRI_8 - Set to corresponding priority level - 0x8 - - - TPRI_9 - Set to corresponding priority level - 0x9 - - - TPRI_15 - Set to lowest priority, Level 16 - 0xF - - - - - RSYNC - Trigger Resync - 15 - 1 - read-write - - - TDLY - Trigger delay select - 16 - 4 - read-write - - - TCMD - Trigger command select - 24 - 4 - read-write - - - TCMD_0 - Not a valid selection from the command buffer. Trigger event is ignored. - 0 - - - TCMD_1 - CMD1 is executed - 0x1 - - - TCMD_2 - Corresponding CMD is executed - 0x2 - - - TCMD_3 - Corresponding CMD is executed - 0x3 - - - TCMD_4 - Corresponding CMD is executed - 0x4 - - - TCMD_5 - Corresponding CMD is executed - 0x5 - - - TCMD_6 - Corresponding CMD is executed - 0x6 - - - TCMD_7 - Corresponding CMD is executed - 0x7 - - - TCMD_8 - Corresponding CMD is executed - 0x8 - - - TCMD_9 - Corresponding CMD is executed - 0x9 - - - TCMD_15 - CMD15 is executed - 0xF - - - - - - - 2 - 0x4 - FCTRL[%s] - FIFO Control Register - 0xE0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FCOUNT - Result FIFO counter - 0 - 5 - read-only - - - FWMARK - Watermark level selection - 16 - 4 - read-write - - - - - 2 - 0x4 - GCC[%s] - Gain Calibration Control - 0xF0 - 32 - read-only - 0 - 0xFFFFFFFF - - - GAIN_CAL - Gain Calibration Value - 0 - 16 - read-only - - - RDY - Gain Calibration Value Valid - 24 - 1 - read-only - - - RDY_0 - The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. - 0 - - - RDY_1 - The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. - 0x1 - - - - - - - 2 - 0x4 - GCR[%s] - Gain Calculation Result - 0xF8 - 32 - read-write - 0 - 0xFFFFFFFF - - - GCALR - Gain Calculation Result - 0 - 16 - read-write - - - RDY - Gain Calculation Ready - 24 - 1 - read-write - - - RDY_0 - The gain offset calculation value is invalid. - 0 - - - RDY_1 - The gain calibration value is valid. - 0x1 - - - - - - - CMDL1 - ADC Command Low Buffer Register - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH1 - ADC Command High Buffer Register - 0x104 - 32 - read-write - 0 - 0xFFFFFFFF - - - CMPEN - Compare Function Enable - 0 - 2 - read-write - - - CMPEN_0 - Compare disabled. - 0 - - - CMPEN_2 - Compare enabled. Store on true. - 0x2 - - - CMPEN_3 - Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - 0x3 - - - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL2 - ADC Command Low Buffer Register - 0x108 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH2 - ADC Command High Buffer Register - 0x10C - 32 - read-write - 0 - 0xFFFFFFFF - - - CMPEN - Compare Function Enable - 0 - 2 - read-write - - - CMPEN_0 - Compare disabled. - 0 - - - CMPEN_2 - Compare enabled. Store on true. - 0x2 - - - CMPEN_3 - Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - 0x3 - - - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL3 - ADC Command Low Buffer Register - 0x110 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH3 - ADC Command High Buffer Register - 0x114 - 32 - read-write - 0 - 0xFFFFFFFF - - - CMPEN - Compare Function Enable - 0 - 2 - read-write - - - CMPEN_0 - Compare disabled. - 0 - - - CMPEN_2 - Compare enabled. Store on true. - 0x2 - - - CMPEN_3 - Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - 0x3 - - - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL4 - ADC Command Low Buffer Register - 0x118 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH4 - ADC Command High Buffer Register - 0x11C - 32 - read-write - 0 - 0xFFFFFFFF - - - CMPEN - Compare Function Enable - 0 - 2 - read-write - - - CMPEN_0 - Compare disabled. - 0 - - - CMPEN_2 - Compare enabled. Store on true. - 0x2 - - - CMPEN_3 - Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - 0x3 - - - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL5 - ADC Command Low Buffer Register - 0x120 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH5 - ADC Command High Buffer Register - 0x124 - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL6 - ADC Command Low Buffer Register - 0x128 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH6 - ADC Command High Buffer Register - 0x12C - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL7 - ADC Command Low Buffer Register - 0x130 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH7 - ADC Command High Buffer Register - 0x134 - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL8 - ADC Command Low Buffer Register - 0x138 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH8 - ADC Command High Buffer Register - 0x13C - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL9 - ADC Command Low Buffer Register - 0x140 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH9 - ADC Command High Buffer Register - 0x144 - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL10 - ADC Command Low Buffer Register - 0x148 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH10 - ADC Command High Buffer Register - 0x14C - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL11 - ADC Command Low Buffer Register - 0x150 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH11 - ADC Command High Buffer Register - 0x154 - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL12 - ADC Command Low Buffer Register - 0x158 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH12 - ADC Command High Buffer Register - 0x15C - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL13 - ADC Command Low Buffer Register - 0x160 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH13 - ADC Command High Buffer Register - 0x164 - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL14 - ADC Command Low Buffer Register - 0x168 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH14 - ADC Command High Buffer Register - 0x16C - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - CMDL15 - ADC Command Low Buffer Register - 0x170 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADCH - Input channel select - 0 - 5 - read-write - - - ADCH_0 - Select CH0A or CH0B or CH0A/CH0B pair. - 0 - - - ADCH_1 - Select CH1A or CH1B or CH1A/CH1B pair. - 0x1 - - - ADCH_2 - Select CH2A or CH2B or CH2A/CH2B pair. - 0x2 - - - ADCH_3 - Select CH3A or CH3B or CH3A/CH3B pair. - 0x3 - - - ADCH_4 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x4 - - - ADCH_5 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x5 - - - ADCH_6 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x6 - - - ADCH_7 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x7 - - - ADCH_8 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x8 - - - ADCH_9 - Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - 0x9 - - - ADCH_30 - Select CH30A or CH30B or CH30A/CH30B pair. - 0x1E - - - ADCH_31 - Select CH31A or CH31B or CH31A/CH31B pair. - 0x1F - - - - - CTYPE - Conversion Type - 5 - 2 - read-write - - - CTYPE_0 - Single-Ended Mode. Only A side channel is converted. - 0 - - - CTYPE_1 - Single-Ended Mode. Only B side channel is converted. - 0x1 - - - CTYPE_2 - Differential Mode. A-B. - 0x2 - - - CTYPE_3 - Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - 0x3 - - - - - MODE - Select resolution of conversions - 7 - 1 - read-write - - - MODE_0 - Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - 0 - - - MODE_1 - High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - 0x1 - - - - - - - CMDH15 - ADC Command High Buffer Register - 0x174 - 32 - read-write - 0 - 0xFFFFFFFF - - - WAIT_TRIG - Wait for trigger assertion before execution. - 2 - 1 - read-write - - - WAIT_TRIG_0 - This command will be automatically executed. - 0 - - - WAIT_TRIG_1 - The active trigger must be asserted again before executing this command. - 0x1 - - - - - LWI - Loop with Increment - 7 - 1 - read-write - - - LWI_0 - Auto channel increment disabled - 0 - - - LWI_1 - Auto channel increment enabled - 0x1 - - - - - STS - Sample Time Select - 8 - 3 - read-write - - - STS_0 - Minimum sample time of 3 ADCK cycles. - 0 - - - STS_1 - 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - 0x1 - - - STS_2 - 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - 0x2 - - - STS_3 - 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - 0x3 - - - STS_4 - 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - 0x4 - - - STS_5 - 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - 0x5 - - - STS_6 - 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - 0x6 - - - STS_7 - 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - 0x7 - - - - - AVGS - Hardware Average Select - 12 - 3 - read-write - - - AVGS_0 - Single conversion. - 0 - - - AVGS_1 - 2 conversions averaged. - 0x1 - - - AVGS_2 - 4 conversions averaged. - 0x2 - - - AVGS_3 - 8 conversions averaged. - 0x3 - - - AVGS_4 - 16 conversions averaged. - 0x4 - - - AVGS_5 - 32 conversions averaged. - 0x5 - - - AVGS_6 - 64 conversions averaged. - 0x6 - - - AVGS_7 - 128 conversions averaged. - 0x7 - - - - - LOOP - Loop Count Select - 16 - 4 - read-write - - - LOOP_0 - Looping not enabled. Command executes 1 time. - 0 - - - LOOP_1 - Loop 1 time. Command executes 2 times. - 0x1 - - - LOOP_2 - Loop 2 times. Command executes 3 times. - 0x2 - - - LOOP_3 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x3 - - - LOOP_4 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x4 - - - LOOP_5 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x5 - - - LOOP_6 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x6 - - - LOOP_7 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x7 - - - LOOP_8 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x8 - - - LOOP_9 - Loop corresponding number of times. Command executes LOOP+1 times. - 0x9 - - - LOOP_15 - Loop 15 times. Command executes 16 times. - 0xF - - - - - NEXT - Next Command Select - 24 - 4 - read-write - - - NEXT_0 - No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - 0 - - - NEXT_1 - Select CMD1 command buffer register as next command. - 0x1 - - - NEXT_2 - Select corresponding CMD command buffer register as next command - 0x2 - - - NEXT_3 - Select corresponding CMD command buffer register as next command - 0x3 - - - NEXT_4 - Select corresponding CMD command buffer register as next command - 0x4 - - - NEXT_5 - Select corresponding CMD command buffer register as next command - 0x5 - - - NEXT_6 - Select corresponding CMD command buffer register as next command - 0x6 - - - NEXT_7 - Select corresponding CMD command buffer register as next command - 0x7 - - - NEXT_8 - Select corresponding CMD command buffer register as next command - 0x8 - - - NEXT_9 - Select corresponding CMD command buffer register as next command - 0x9 - - - NEXT_15 - Select CMD15 command buffer register as next command. - 0xF - - - - - - - 4 - 0x4 - 1,2,3,4 - CV%s - Compare Value Register - 0x200 - 32 - read-write - 0 - 0xFFFFFFFF - - - CVL - Compare Value Low. - 0 - 16 - read-write - - - CVH - Compare Value High. - 16 - 16 - read-write - - - - - 2 - 0x4 - RESFIFO[%s] - ADC Data Result FIFO Register - 0x300 - 32 - read-only - 0 - 0xFFFFFFFF - - - D - Data result - 0 - 16 - read-only - - - TSRC - Trigger Source - 16 - 4 - read-only - - - TSRC_0 - Trigger source 0 initiated this conversion. - 0 - - - TSRC_1 - Trigger source 1 initiated this conversion. - 0x1 - - - TSRC_2 - Corresponding trigger source initiated this conversion. - 0x2 - - - TSRC_3 - Corresponding trigger source initiated this conversion. - 0x3 - - - TSRC_4 - Corresponding trigger source initiated this conversion. - 0x4 - - - TSRC_5 - Corresponding trigger source initiated this conversion. - 0x5 - - - TSRC_6 - Corresponding trigger source initiated this conversion. - 0x6 - - - TSRC_7 - Corresponding trigger source initiated this conversion. - 0x7 - - - TSRC_8 - Corresponding trigger source initiated this conversion. - 0x8 - - - TSRC_9 - Corresponding trigger source initiated this conversion. - 0x9 - - - TSRC_15 - Trigger source 15 initiated this conversion. - 0xF - - - - - LOOPCNT - Loop count value - 20 - 4 - read-only - - - LOOPCNT_0 - Result is from initial conversion in command. - 0 - - - LOOPCNT_1 - Result is from second conversion in command. - 0x1 - - - LOOPCNT_2 - Result is from LOOPCNT+1 conversion in command. - 0x2 - - - LOOPCNT_3 - Result is from LOOPCNT+1 conversion in command. - 0x3 - - - LOOPCNT_4 - Result is from LOOPCNT+1 conversion in command. - 0x4 - - - LOOPCNT_5 - Result is from LOOPCNT+1 conversion in command. - 0x5 - - - LOOPCNT_6 - Result is from LOOPCNT+1 conversion in command. - 0x6 - - - LOOPCNT_7 - Result is from LOOPCNT+1 conversion in command. - 0x7 - - - LOOPCNT_8 - Result is from LOOPCNT+1 conversion in command. - 0x8 - - - LOOPCNT_9 - Result is from LOOPCNT+1 conversion in command. - 0x9 - - - LOOPCNT_15 - Result is from 16th conversion in command. - 0xF - - - - - CMDSRC - Command Buffer Source - 24 - 4 - read-only - - - CMDSRC_0 - Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer. - 0 - - - CMDSRC_1 - CMD1 buffer used as control settings for this conversion. - 0x1 - - - CMDSRC_2 - Corresponding command buffer used as control settings for this conversion. - 0x2 - - - CMDSRC_3 - Corresponding command buffer used as control settings for this conversion. - 0x3 - - - CMDSRC_4 - Corresponding command buffer used as control settings for this conversion. - 0x4 - - - CMDSRC_5 - Corresponding command buffer used as control settings for this conversion. - 0x5 - - - CMDSRC_6 - Corresponding command buffer used as control settings for this conversion. - 0x6 - - - CMDSRC_7 - Corresponding command buffer used as control settings for this conversion. - 0x7 - - - CMDSRC_8 - Corresponding command buffer used as control settings for this conversion. - 0x8 - - - CMDSRC_9 - Corresponding command buffer used as control settings for this conversion. - 0x9 - - - CMDSRC_15 - CMD15 buffer used as control settings for this conversion. - 0xF - - - - - VALID - FIFO entry is valid - 31 - 1 - read-only - - - VALID_0 - FIFO is empty. Discard any read from RESFIFO. - 0 - - - VALID_1 - FIFO record read from RESFIFO is valid. - 0x1 - - - - - - - 33 - 0x4 - CAL_GAR[%s] - Calibration General A-Side Registers - 0x400 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAL_GAR_VAL - Calibration General A Side Register Element - 0 - 16 - read-write - - - - - 33 - 0x4 - CAL_GBR[%s] - Calibration General B-Side Registers - 0x500 - 32 - read-write - 0 - 0xFFFFFFFF - - - CAL_GBR_VAL - Calibration General B Side Register Element - 0 - 16 - read-write - - - - - TST - ADC Test Register - 0xFFC - 32 - read-write - 0 - 0xFFFFFFFF - - - CST_LONG - Calibration Sample Time Long - 0 - 1 - read-write - - - CST_LONG_0 - Normal sample time. Minimum sample time of 3 ADCK cycles. - 0 - - - CST_LONG_1 - Increased sample time. 67 ADCK cycles total sample time. - 0x1 - - - - - FOFFM - Force M-side positive offset - 8 - 1 - read-write - - - FOFFM_0 - Normal operation. No forced offset. - 0 - - - FOFFM_1 - Test configuration. Forced positive offset on MDAC. - 0x1 - - - - - FOFFP - Force P-side positive offset - 9 - 1 - read-write - - - FOFFP_0 - Normal operation. No forced offset. - 0 - - - FOFFP_1 - Test configuration. Forced positive offset on PDAC. - 0x1 - - - - - FOFFM2 - Force M-side negative offset - 10 - 1 - read-write - - - FOFFM2_0 - Normal operation. No forced offset. - 0 - - - FOFFM2_1 - Test configuration. Forced negative offset on MDAC. - 0x1 - - - - - FOFFP2 - Force P-side negative offset - 11 - 1 - read-write - - - FOFFP2_0 - Normal operation. No forced offset. - 0 - - - FOFFP2_1 - Test configuration. Forced negative offset on PDAC. - 0x1 - - - - - TESTEN - Enable test configuration - 23 - 1 - read-write - - - TESTEN_0 - Normal operation. Test configuration not enabled. - 0 - - - TESTEN_1 - Hardware BIST Test in progress. - 0x1 - - - - - - - - - USBFSH - USB0 Full-speed Host controller - USBFSH - 0x400A2000 - - 0 - 0x60 - registers - - - USB0_NEEDCLK - 27 - - - USB0 - 28 - - - - HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) - 0 - 32 - read-only - 0x10 - 0xFF - - - REV - Revision. - 0 - 8 - read-only - - - - - HCCONTROL - Defines the operating modes of the HC - 0x4 - 32 - read-write - 0 - 0x7FF - - - CBSR - ControlBulkServiceRatio. - 0 - 2 - read-write - - - PLE - PeriodicListEnable. - 2 - 1 - read-write - - - IE - IsochronousEnable. - 3 - 1 - read-write - - - CLE - ControlListEnable. - 4 - 1 - read-write - - - BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. - 5 - 1 - read-write - - - HCFS - HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin 1 ms later. - 6 - 2 - read-write - - - IR - InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. - 8 - 1 - read-write - - - RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling. - 9 - 1 - read-write - - - RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature upon the detection of upstream resume signaling. - 10 - 1 - read-write - - - - - HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) - 0x8 - 32 - read-write - 0 - 0xCF - - - HCR - HostControllerReset This bit is set by HCD to initiate a software reset of HC. - 0 - 1 - read-write - - - CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. - 1 - 1 - read-write - - - BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. - 2 - 1 - read-write - - - OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC. - 3 - 1 - read-write - - - SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error. - 6 - 2 - read-write - - - - - HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits - 0xC - 32 - read-write - 0 - 0xFFFFFC7F - - - SO - SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and after the update of HccaFrameNumber. - 0 - 1 - read-write - - - WDH - WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead. - 1 - 1 - read-write - - - SF - StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. - 2 - 1 - read-write - - - RD - ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling. - 3 - 1 - read-write - - - UE - UnrecoverableError This bit is set when HC detects a system error not related to USB. - 4 - 1 - read-write - - - FNO - FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value, from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated. - 5 - 1 - read-write - - - RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed. - 6 - 1 - read-write - - - OC - OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus. - 10 - 22 - read-write - - - - - HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt - 0x10 - 32 - read-write - 0 - 0xC000007F - - - SO - Scheduling Overrun interrupt. - 0 - 1 - read-write - - - WDH - HcDoneHead Writeback interrupt. - 1 - 1 - read-write - - - SF - Start of Frame interrupt. - 2 - 1 - read-write - - - RD - Resume Detect interrupt. - 3 - 1 - read-write - - - UE - Unrecoverable Error interrupt. - 4 - 1 - read-write - - - FNO - Frame Number Overflow interrupt. - 5 - 1 - read-write - - - RHSC - Root Hub Status Change interrupt. - 6 - 1 - read-write - - - OC - Ownership Change interrupt. - 30 - 1 - read-write - - - MIE - Master Interrupt Enable. - 31 - 1 - read-write - - - - - HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt - 0x14 - 32 - read-write - 0 - 0xC000007F - - - SO - Scheduling Overrun interrupt. - 0 - 1 - read-write - - - WDH - HcDoneHead Writeback interrupt. - 1 - 1 - read-write - - - SF - Start of Frame interrupt. - 2 - 1 - read-write - - - RD - Resume Detect interrupt. - 3 - 1 - read-write - - - UE - Unrecoverable Error interrupt. - 4 - 1 - read-write - - - FNO - Frame Number Overflow interrupt. - 5 - 1 - read-write - - - RHSC - Root Hub Status Change interrupt. - 6 - 1 - read-write - - - OC - Ownership Change interrupt. - 30 - 1 - read-write - - - MIE - A 0 written to this field is ignored by HC. - 31 - 1 - read-write - - - - - HCHCCA - Contains the physical address of the host controller communication area - 0x18 - 32 - read-write - 0 - 0xFFFFFF00 - - - HCCA - Base address of the Host Controller Communication Area. - 8 - 24 - read-write - - - - - HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor - 0x1C - 32 - read-write - 0 - 0xFFFFFFF0 - - - PCED - The content of this register is updated by HC after a periodic ED is processed. - 4 - 28 - read-only - - - - - HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list - 0x20 - 32 - read-write - 0 - 0xFFFFFFF0 - - - CHED - HC traverses the Control list starting with the HcControlHeadED pointer. - 4 - 28 - read-write - - - - - HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list - 0x24 - 32 - read-write - 0 - 0xFFFFFFF0 - - - CCED - ControlCurrentED. - 4 - 28 - read-write - - - - - HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list - 0x28 - 32 - read-write - 0 - 0xFFFFFFF0 - - - BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer. - 4 - 28 - read-write - - - - - HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list - 0x2C - 32 - read-write - 0 - 0xFFFFFFF0 - - - BCED - BulkCurrentED This is advanced to the next ED after the HC has served the current one. - 4 - 28 - read-write - - - - - HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue - 0x30 - 32 - read-write - 0 - 0xFFFFFFF0 - - - DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. - 4 - 28 - read-only - - - - - HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun - 0x34 - 32 - read-write - 0x2EDF - 0xFFFF3FFF - - - FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times. - 0 - 14 - read-write - - - FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame. - 16 - 15 - read-write - - - FIT - FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval. - 31 - 1 - read-write - - - - - HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame - 0x38 - 32 - read-write - 0 - 0x80003FFF - - - FR - FrameRemaining This counter is decremented at each bit time. - 0 - 14 - read-only - - - FRT - FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0. - 31 - 1 - read-only - - - - - HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD - 0x3C - 32 - read-write - 0 - 0xFFFF - - - FN - FrameNumber This is incremented when HcFmRemaining is re-loaded. - 0 - 16 - read-only - - - - - HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list - 0x40 - 32 - read-write - 0 - 0x3FFF - - - PS - PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization. - 0 - 14 - read-write - - - - - HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF - 0x44 - 32 - read-write - 0x628 - 0xFFF - - - LST - LSThreshold This field contains a value which is compared to the FrameRemaining field prior to initiating a Low Speed transaction. - 0 - 12 - read-write - - - - - HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub - 0x48 - 32 - read-write - 0xFF000902 - 0xFF001FFF - - - NDP - NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub. - 0 - 8 - read-write - - - PSM - PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled. - 8 - 1 - read-write - - - NPS - NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered. - 9 - 1 - read-write - - - DT - DeviceType This bit specifies that the root hub is not a compound device. - 10 - 1 - read-write - - - OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported. - 11 - 1 - read-write - - - NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported. - 12 - 1 - read-write - - - POTPGT - PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before accessing a powered-on port of the root hub. - 24 - 8 - read-write - - - - - HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub - 0x4C - 32 - read-write - 0 - 0x3FFFFFFF - - - DR - DeviceRemovable Each bit is dedicated to a port of the Root Hub. - 0 - 16 - read-write - - - PPCM - PortPowerControlMask Each bit indicates if a port is affected by a global power control command when PowerSwitchingMode is set. - 16 - 16 - read-write - - - - - HCRHSTATUS - This register is divided into two parts - 0x50 - 32 - read-write - 0 - 0x80038003 - - - LPS - (read) LocalPowerStatus The Root Hub does not support the local power status feature; thus, this bit is always read as 0. - 0 - 1 - read-write - - - OCI - OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented. - 1 - 1 - read-write - - - DRWE - (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected interrupt. - 15 - 1 - read-write - - - LPSC - (read) LocalPowerStatusChange The root hub does not support the local power status feature. - 16 - 1 - read-write - - - OCIC - OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register. - 17 - 1 - read-write - - - CRWE - (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable. - 31 - 1 - read-write - - - - - HCRHPORTSTATUS - Controls and reports the port events on a per-port basis - 0x54 - 32 - read-write - 0 - 0x1F031F - - - CCS - (read) CurrentConnectStatus This bit reflects the current state of the downstream port. - 0 - 1 - read-write - - - PES - (read) PortEnableStatus This bit indicates whether the port is enabled or disabled. - 1 - 1 - read-write - - - PSS - (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence. - 2 - 1 - read-write - - - POCI - (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in such a way that overcurrent conditions are reported on a per-port basis. - 3 - 1 - read-write - - - PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. - 4 - 1 - read-write - - - PPS - (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type of power switching implemented. - 8 - 1 - read-write - - - LSDA - (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. - 9 - 1 - read-write - - - CSC - ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. - 16 - 1 - read-write - - - PESC - PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared. - 17 - 1 - read-write - - - PSSC - PortSuspendStatusChange This bit is set when the full resume sequence is completed. - 18 - 1 - read-write - - - OCIC - PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis. - 19 - 1 - read-write - - - PRSC - PortResetStatusChange This bit is set at the end of the 10 ms port reset signal. - 20 - 1 - read-write - - - - - PORTMODE - Controls the port if it is attached to the host block or the device block - 0x5C - 32 - read-write - 0 - 0x10101 - - - ID - Port ID pin value. - 0 - 1 - read-write - - - ID_EN - Port ID pin pull-up enable. - 8 - 1 - read-write - - - DEV_ENABLE - 1: device 0: host. - 16 - 1 - read-write - - - - - - - USBHSH - USB1 High-speed Host Controller - USBHSH - 0x400A3000 - - 0 - 0x54 - registers - - - USB1 - 47 - - - USB1_NEEDCLK - 48 - - - - CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block - 0 - 32 - read-only - 0x1010010 - 0xFFFF00FF - - - CAPLENGTH - Capability Length: This is used as an offset. - 0 - 8 - read-only - - - CHIPID - Chip identification: indicates major and minor revision of the IP: [31:24] = Major revision [23:16] = Minor revision Major revisions used: 0x01: USB2. - 16 - 16 - read-only - - - - - HCSPARAMS - Host Controller Structural Parameters - 0x4 - 32 - read-only - 0x10011 - 0x1001F - - - N_PORTS - This register specifies the number of physical downstream ports implemented on this host controller. - 0 - 4 - read-only - - - PPC - This field indicates whether the host controller implementation includes port power control. - 4 - 1 - read-only - - - P_INDICATOR - This bit indicates whether the ports support port indicator control. - 16 - 1 - read-only - - - - - FLADJ_FRINDEX - Frame Length Adjustment - 0xC - 32 - read-write - 0x20 - 0x3FFF003F - - - FLADJ - Frame Length Timing Value. - 0 - 6 - read-write - - - FRINDEX - Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet. - 16 - 14 - read-write - - - - - ATLPTD - Memory base address where ATL PTD0 is stored - 0x10 - 32 - read-write - 0 - 0xFFFFFFF0 - - - ATL_CUR - This indicates the current PTD that is used by the hardware when it is processing the ATL list. - 4 - 5 - read-write - - - ATL_BASE - Base address to be used by the hardware to find the start of the ATL list. - 9 - 23 - read-write - - - - - ISOPTD - Memory base address where ISO PTD0 is stored - 0x14 - 32 - read-write - 0 - 0xFFFFFFE0 - - - ISO_FIRST - This indicates the first PTD that is used by the hardware when it is processing the ISO list. - 5 - 5 - read-write - - - ISO_BASE - Base address to be used by the hardware to find the start of the ISO list. - 10 - 22 - read-write - - - - - INTPTD - Memory base address where INT PTD0 is stored - 0x18 - 32 - read-write - 0 - 0xFFFFFFE0 - - - INT_FIRST - This indicates the first PTD that is used by the hardware when it is processing the INT list. - 5 - 5 - read-write - - - INT_BASE - Base address to be used by the hardware to find the start of the INT list. - 10 - 22 - read-write - - - - - DATAPAYLOAD - Memory base address that indicates the start of the data payload buffers - 0x1C - 32 - read-write - 0 - 0xFFFF0000 - - - DAT_BASE - Base address to be used by the hardware to find the start of the data payload section. - 16 - 16 - read-write - - - - - USBCMD - USB Command register - 0x20 - 32 - read-write - 0 - 0x1F00078F - - - RS - Run/Stop: 1b = Run. - 0 - 1 - read-write - - - HCRESET - Host Controller Reset: This control bit is used by the software to reset the host controller. - 1 - 1 - read-write - - - FLS - Frame List Size: This field specifies the size of the frame list. - 2 - 2 - read-write - - - LHCR - Light Host Controller Reset: This bit allows the driver software to reset the host controller without affecting the state of the ports. - 7 - 1 - read-write - - - ATL_EN - ATL List enabled. - 8 - 1 - read-write - - - ISO_EN - ISO List enabled. - 9 - 1 - read-write - - - INT_EN - INT List enabled. - 10 - 1 - read-write - - - - - USBSTS - USB Interrupt Status register - 0x24 - 32 - read-write - 0 - 0xF000C - - - PCD - Port Change Detect: The host controller sets this bit to logic 1 when any port has a change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a result of a J-K transition detected on a suspended port. - 2 - 1 - read-write - - - FLR - Frame List Rollover: The host controller sets this bit to logic 1 when the frame list index rolls over its maximum value to 0. - 3 - 1 - read-write - - - ATL_IRQ - ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed. - 16 - 1 - read-write - - - ISO_IRQ - ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed. - 17 - 1 - read-write - - - INT_IRQ - INT IRQ: Indicates that an INT PTD (with I-bit set) was completed. - 18 - 1 - read-write - - - SOF_IRQ - SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set. - 19 - 1 - read-write - - - - - USBINTR - USB Interrupt Enable register - 0x28 - 32 - read-write - 0 - 0xF000C - - - PCDE - Port Change Detect Interrupt Enable: 1: enable 0: disable. - 2 - 1 - read-write - - - FLRE - Frame List Rollover Interrupt Enable: 1: enable 0: disable. - 3 - 1 - read-write - - - ATL_IRQ_E - ATL IRQ Enable bit: 1: enable 0: disable. - 16 - 1 - read-write - - - ISO_IRQ_E - ISO IRQ Enable bit: 1: enable 0: disable. - 17 - 1 - read-write - - - INT_IRQ_E - INT IRQ Enable bit: 1: enable 0: disable. - 18 - 1 - read-write - - - SOF_E - SOF Interrupt Enable bit: 1: enable 0: disable. - 19 - 1 - read-write - - - - - PORTSC1 - Port Status and Control register - 0x2C - 32 - read-write - 0 - 0xFFFFDFFF - - - CCS - Current Connect Status: Logic 1 indicates a device is present on the port. - 0 - 1 - read-write - - - CSC - Connect Status Change: Logic 1 means that the value of CCS has changed. - 1 - 1 - read-write - - - PED - Port Enabled/Disabled. - 2 - 1 - read-write - - - PEDC - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed. - 3 - 1 - read-write - - - OCA - Over-current active: Logic 1 means that this port has an over-current condition. - 4 - 1 - read-write - - - OCC - Over-current change: Logic 1 means that the value of OCA has changed. - 5 - 1 - read-write - - - FPR - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port. - 6 - 1 - read-write - - - SUSP - Suspend: Logic 1 means port is in the suspend state. - 7 - 1 - read-write - - - PR - Port Reset: Logic 1 means the port is in the reset state. - 8 - 1 - read-write - - - LS - Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. - 10 - 2 - read-only - - - PP - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register. - 12 - 1 - read-write - - - PIC - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is logic 0. - 14 - 2 - read-write - - - PTC - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value. - 16 - 4 - read-write - - - PSPD - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved. - 20 - 2 - read-write - - - WOO - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to overcurrent conditions as wake-up events. - 22 - 1 - read-write - - - - - ATLPTDD - Done map for each ATL PTD - 0x30 - 32 - read-write - 0 - 0xFFFFFFFF - - - ATL_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - 0 - 32 - read-write - - - - - ATLPTDS - Skip map for each ATL PTD - 0x34 - 32 - read-write - 0 - 0xFFFFFFFF - - - ATL_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be skipped, independent of the V bit setting. - 0 - 32 - read-write - - - - - ISOPTDD - Done map for each ISO PTD - 0x38 - 32 - read-write - 0 - 0xFFFFFFFF - - - ISO_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - 0 - 32 - read-write - - - - - ISOPTDS - Skip map for each ISO PTD - 0x3C - 32 - read-write - 0 - 0xFFFFFFFF - - - ISO_SKIP - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - 0 - 32 - read-write - - - - - INTPTDD - Done map for each INT PTD - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - INT_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. - 0 - 32 - read-write - - - - - INTPTDS - Skip map for each INT PTD - 0x44 - 32 - read-write - 0 - 0xFFFFFFFF - - - INT_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be skipped, independent of the V bit setting. - 0 - 32 - read-write - - - - - LASTPTD - Marks the last PTD in the list for ISO, INT and ATL - 0x48 - 32 - read-write - 0 - 0x1F1F1F - - - ATL_LAST - If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed. - 0 - 5 - read-write - - - ISO_LAST - This indicates the last PTD in the ISO list. - 8 - 5 - read-write - - - INT_LAST - This indicates the last PTD in the INT list. - 16 - 5 - read-write - - - - - PORTMODE - Controls the port if it is attached to the host block or the device block - 0x50 - 32 - read-write - 0x40000 - 0xD0101 - - - DEV_ENABLE - If this bit is set to one, one of the ports will behave as a USB device. - 16 - 1 - read-write - - - SW_CTRL_PDCOM - This bit indicates if the PHY power-down input is controlled by software or by hardware. - 18 - 1 - read-write - - - SW_PDCOM - This bit is only used when SW_CTRL_PDCOM is set to 1b. - 19 - 1 - read-write - - - - - - - HASHCRYPT - Hash-Crypt peripheral - HASHCRYPT - 0x400A4000 - - 0 - 0xA0 - registers - - - HASHCRYPT - 54 - - - - CTRL - Control register to enable and operate Hash and Crypto - 0 - 32 - read-write - 0 - 0x3317 - - - Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if specific modes beyond SHA1 and SHA2-256 are available. - 0 - 3 - read-write - - - DISABLED - Disabled - 0 - - - SHA1 - SHA1 is enabled - 0x1 - - - SHA2_256 - SHA2-256 is enabled - 0x2 - - - AES - AES if available (see also CRYPTCFG register for more controls) - 0x4 - - - ICB_AES - ICB-AES if available (see also CRYPTCFG register for more controls) - 0x5 - - - - - New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING Status bit will clear for a cycle during the initialization from New=1. - 4 - 1 - write-only - - - START - Starts a new Hash/Crypto and initializes the Digest/Result. - 0x1 - - - - - DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words and then will process the Hash. If Cryptographic, it will load as many words as needed, including key if not already loaded. It will then request again. Normal model is that the DMA interrupts the processor when its length expires. Note that if the processor will write the key and optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be expected to load those for the 1st block (when needed). - 8 - 1 - read-write - - - NOT_USED - DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used. - 0 - - - PUSH - DMA will push in the data. - 0x1 - - - - - DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the DMA has to know to switch direction and the locations. This can be used for crypto uses. - 9 - 1 - read-write - - - NOTUSED - DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. - 0 - - - - - HASHSWPB - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For cryptographic swapping, see the CRYPTCFG register. - 12 - 1 - read-write - - - - - STATUS - Indicates status of Hash peripheral. - 0x4 - 32 - read-write - 0 - 0x3F0037 - - - WAITING - If 1, the block is waiting for more data to process. - 0 - 1 - read-only - - - NOT_WAITING - Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set if IsLast is set nor will it set until at least 1 word is read of the output. - 0 - - - WAITING - Waiting for data to be written in (16 words) - 0x1 - - - - - DIGEST - For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block already started. For Cryptographic uses, this will be set for each block processed, indicating OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared when any data is written, when New is written, for Cryptographic uses when the last word is read out, or when the block is disabled. - 1 - 1 - read-only - - - NOT_READY - No Digest is ready - 0 - - - READY - Digest is ready. Application may read it or may write more data - 0x1 - - - - - ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT field will indicate which block it was on. - 2 - 1 - read-write - oneToClear - - - NO_ERROR - No error. - 0 - - - ERROR - An error occurred since last cleared (written 1 to clear). - 0x1 - - - - - NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING) - 4 - 1 - read-only - - - NOT_NEED - No Key is needed and writes will not be treated as Key - 0 - - - NEED - Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. - 0x1 - - - - - NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING) - 5 - 1 - read-only - - - NOT_NEED - No IV/Nonce is needed, either because written already or because not needed. - 0 - - - NEED - IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. - 0x1 - - - - - ICBIDX - If ICB-AES is selected, then reads as the ICB index count based on ICBSTRM (from CRYPTCFG). That is, if 3 bits of ICBSTRM, then this will count from 0 to 7 and then back to 0. On 0, it has to compute the full ICB, quicker when not 0. - 16 - 6 - read-only - - - - - INTENSET - Write 1 to enable interrupts; reads back with which are set. - 0x8 - 32 - read-write - 0 - 0x7 - - - WAITING - Indicates if should interrupt when waiting for data input. - 0 - 1 - read-write - - - NO_INTERRUPT - Will not interrupt when waiting. - 0 - - - INTERRUPT - Will interrupt when waiting - 0x1 - - - - - DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). - 1 - 1 - read-write - - - NO_INTERRUPT - Will not interrupt when Digest is ready - 0 - - - INTERRUPT - Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). - 0x1 - - - - - ERROR - Indicates if should interrupt on an ERROR (as defined in Status) - 2 - 1 - read-write - - - NOT_INTERRUPT - Will not interrupt on Error. - 0 - - - INTERRUPT - Will interrupt on Error (until cleared). - 0x1 - - - - - - - INTENCLR - Write 1 to clear interrupts. - 0xC - 32 - read-write - 0 - 0 - - - WAITING - Write 1 to clear mask. - 0 - 1 - read-write - oneToClear - - - DIGEST - Write 1 to clear mask. - 1 - 1 - read-write - oneToClear - - - ERROR - Write 1 to clear mask. - 2 - 1 - read-write - oneToClear - - - - - MEMCTRL - Setup Master to access memory (if available) - 0x10 - 32 - read-write - 0 - 0x7FF0001 - - - MASTER - Enables mastering. - 0 - 1 - read-write - - - NOT_USED - Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. - 0 - - - ENABLED - Mastering is enabled and DMA and INDATA should not be used. - 0x1 - - - - - COUNT - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks to copy starting at MEMADDR. This register will decrement after each block is copied, ending in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA interrupt will occur on ever block. If a bus error occurs, it will stop with this field set to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) blocks to hash. - 16 - 11 - read-write - - - - - MEMADDR - Address to start memory access from (if available). - 0x14 - 32 - read-write - 0 - 0xFFFFFFFF - - - BASE - Address base to start copying from, word aligned (so bits 1:0 must be 0). This field will advance as it processes the words. If it fails with a bus error, the register will contain the failing word. N:Address in Flash or RAM space; RAM only as mapped in this part. May also be able to address SPIFI. - 0 - 32 - read-write - - - - - INDATA - Input of 16 words at a time to load up buffer. - 0x20 - 32 - write-only - 0 - 0 - - - DATA - Write next word in little-endian form. The hash requires big endian word data, but this block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block will swap the word to restore into big endian. - 0 - 32 - write-only - - - - - 7 - 0x4 - ALIAS[%s] - no description available - 0x24 - 32 - write-only - 0 - 0 - - - DATA - Write next word in little-endian form. The hash requires big endian word data, but this block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block will swap the word to restore into big endian. - 0 - 32 - write-only - - - - - 8 - 0x4 - DIGEST0[%s] - no description available - 0x40 - 32 - read-only - 0 - 0xFFFFFFFF - - - DIGEST - One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1. - 0 - 32 - read-only - - - - - CRYPTCFG - Crypto settings for AES and Salsa and ChaCha - 0x80 - 32 - read-write - 0 - 0xF31FFF - - - MSW1ST_OUT - If 1, OUTDATA0 will be read Most significant word 1st for AES. Else it will be read in normal little endian - Least significant word 1st. Note: only if allowed by configuration. - 0 - 1 - read-write - - - SWAPKEY - If 1, will Swap the key input (bytes in each word). - 1 - 1 - read-write - - - SWAPDAT - If 1, will SWAP the data and IV inputs (bytes in each word). - 2 - 1 - read-write - - - MSW1ST - If 1, load of key, IV, and data is MSW 1st for AES. Else, the words are little endian. Note: only if allowed by configuration. - 3 - 1 - read-write - - - AESMODE - AES Cipher mode to use if plain AES - 4 - 2 - read-write - - - ECB - ECB - used as is - 0 - - - CBC - CBC mode (see details on IV/nonce) - 0x1 - - - CTR - CTR mode (see details on IV/nonce). See also AESCTRPOS. - 0x2 - - - - - AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB - 6 - 1 - read-write - - - ENCRYPT - Encrypt - 0 - - - DECRYPT - Decrypt - 0x1 - - - - - AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are used, only the highest level is permitted to select this. - 7 - 1 - read-write - - - NORMAL_WAY - User key provided in normal way - 0 - - - HIDDEN_WAY - Secret key provided in hidden way by HW - 0x1 - - - - - AESKEYSZ - Sets the AES key size - 8 - 2 - read-write - - - BITS_128 - 128 bit key - 0 - - - BITS_192 - 192 bit key - 0x1 - - - BITS_256 - 256 bit key - 0x2 - - - - - AESCTRPOS - Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other use CTR should use ECB directly and do its own XOR and so on. - 10 - 3 - read-write - - - STREAMLAST - Is 1 if last stream block. If not 1, then the engine will compute the next "hash". - 16 - 1 - read-write - - - ICBSZ - This sets the ICB size between 32 and 128 bits, using the following rules. Note that the counter is assumed to occupy the low order bits of the IV. - 20 - 2 - read-write - - - BITS_32 - 32 bits of the IV/ctr are used (from 127:96) - 0 - - - BITS_64 - 64 bits of the IV/ctr are used (from 127:64) - 0x1 - - - BITS_96 - 96 bits of the IV/ctr are used (from 127:32) - 0x2 - - - BIT_128 - All 128 bits of the IV/ctr are used - 0x3 - - - - - ICBSTRM - The size of the ICB-AES stream that can be pushed before needing to compute a new IV/ctr (counter start). This optimizes the performance of the stream of blocks after the 1st. - 22 - 2 - read-write - - - BLOCKS_8 - 8 blocks - 0 - - - BLOCKS_16 - 16 blocks - 0x1 - - - BLOCKS_32 - 32 blocks - 0x2 - - - BLOCKS_64 - 64 blocks - 0x3 - - - - - - - CONFIG - Returns the configuration of this block in this chip - indicates what services are available. - 0x84 - 32 - read-write - 0 - 0 - - - DUAL - 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit - 0 - 1 - read-only - - - DMA - 1 if DMA is connected - 1 - 1 - read-only - - - AHB - 1 if AHB Master is enabled - 3 - 1 - read-only - - - AES - 1 if AES 128 included - 6 - 1 - read-only - - - AESKEY - 1 if AES 192 and 256 also included - 7 - 1 - read-only - - - SECRET - 1 if AES Secret key available - 8 - 1 - read-only - - - ICB - 1 if ICB over AES included - 11 - 1 - read-only - - - - - LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. - 0x8C - 32 - read-write - 0 - 0xFFF3 - - - SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. If locked already, may only write if at same or higher security level as lock. Reads as: 0 if unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the only readable registers if locked and current state is lower than lock level. - 0 - 2 - read-write - - - UNLOCK - Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests. - 0 - - - LOCK - Locks to the current security level. AHB Master will issue requests at this level. - 0x1 - - - - - PATTERN - Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0 - 4 - 12 - read-write - - - - - 4 - 0x4 - MASK[%s] - no description available - 0x90 - 32 - write-only - 0 - 0 - - - MASK - A random word. - 0 - 32 - write-only - - - - - - - CASPER - CASPER - CASPER - 0x400A5000 - - 0 - 0x84 - registers - - - CASER - 55 - - - - CTRL0 - Contains the offsets of AB and CD in the RAM. - 0 - 32 - read-write - 0 - 0x1FFD0005 - - - ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up - 0 - 1 - read-write - - - PAIR0 - Bank-pair 0 (1st) - 0 - - - PAIR1 - Bank-pair 1 (2nd) - 0x1 - - - - - ABOFF - Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up - 2 - 11 - read-write - - - CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up - 16 - 1 - read-write - - - PAIR0 - Bank-pair 0 (1st) - 0 - - - PAIR1 - Bank-pair 1 (2nd) - 0x1 - - - - - CDOFF - Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the AB values - 18 - 11 - read-write - - - - - CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. - 0x4 - 32 - read-write - 0 - 0xDFFDFFFF - - - ITER - Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate. - 0 - 8 - read-write - - - MODE - Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active. - 8 - 8 - read-write - - - RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally this is not the same bank as ABBPAIR (when 4-up supported) - 16 - 1 - read-write - - - PAIR0 - Bank-pair 0 (1st) - 0 - - - PAIR1 - Bank-pair 1 (2nd) - 0x1 - - - - - RESOFF - Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the AB and CD values - 18 - 11 - read-write - - - CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: - 30 - 2 - read-write - - - NO_SKIP - No Skip - 0 - - - SKIP_IF_1 - Skip if Carry is 1 - 0x1 - - - SKIP_IF_0 - Skip if Carry is 0 - 0x2 - - - SET_AND_SKIP - Set CTRLOFF to CDOFF and Skip - 0x3 - - - - - - - LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. - 0x8 - 32 - read-write - 0 - 0x1FFD00FF - - - COUNT - Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one op - does not iterate, write N means N control pairs to load - 0 - 8 - read-write - - - CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not matter which bank is used as this is loaded when not performing an operation. - 16 - 1 - read-write - - - PAIR0 - Bank-pair 0 (1st) - 0 - - - PAIR1 - Bank-pair 1 (2nd) - 0x1 - - - - - CTRLOFF - DWord Offset of CTRL pair to load next. - 18 - 11 - read-write - - - - - STATUS - Indicates operational status and would contain the carry bit if used. - 0xC - 32 - read-write - 0 - 0x31 - - - DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. - 0 - 1 - read-write - - - BUSY - Busy or just cleared - 0 - - - COMPLETED - Completed last operation - 0x1 - - - - - CARRY - Last carry value if operation produced a carry bit - 4 - 1 - read-only - - - NO_CARRY - Carry was 0 or no carry - 0 - - - CARRY - Carry was 1 - 0x1 - - - - - BUSY - Indicates if the accelerator is busy performing an operation - 5 - 1 - read-only - - - IDLE - Not busy - is idle - 0 - - - BUSY - Is busy - 0x1 - - - - - - - INTENSET - Sets interrupts - 0x10 - 32 - read-write - 0 - 0x1 - - - DONE - Set if the accelerator should interrupt when done. - 0 - 1 - read-write - - - NO_INTERRUPT - Do not interrupt when done - 0 - - - INTERRUPT - Interrupt when done - 0x1 - - - - - - - INTENCLR - Clears interrupts - 0x14 - 32 - read-write - 0 - 0x1 - - - DONE - Written to clear an interrupt set with INTENSET. - 0 - 1 - read-write - oneToClear - - - IGNORED - If written 0, ignored - 0 - - - NO_INTERRUPT - If written 1, do not Interrupt when done - 0x1 - - - - - - - INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) - 0x18 - 32 - read-write - 0 - 0x1 - - - DONE - If set, interrupt is caused by accelerator being done. - 0 - 1 - read-only - - - NOT_CAUSED - Not caused by accelerator being done - 0 - - - CAUSED - Caused by accelerator being done - 0x1 - - - - - - - AREG - A register - 0x20 - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - BREG - B register - 0x24 - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - CREG - C register - 0x28 - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - DREG - D register - 0x2C - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - RES0 - Result register 0 - 0x30 - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - RES1 - Result register 1 - 0x34 - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - RES2 - Result register 2 - 0x38 - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - RES3 - Result register 3 - 0x3C - 32 - read-write - 0 - 0xFFFFFFFF - - - REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. - 0 - 32 - read-write - - - - - MASK - Optional mask register - 0x60 - 32 - read-write - 0 - 0xFFFFFFFF - - - MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values - 0 - 32 - read-write - - - - - REMASK - Optional re-mask register - 0x64 - 32 - read-write - 0 - 0xFFFFFFFF - - - MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values - 0 - 32 - read-write - - - - - LOCK - Security lock register - 0x80 - 32 - read-write - 0 - 0x1FFFF - - - LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. - 0 - 1 - read-write - - - UNLOCK - unlock - 0 - - - LOCK - Lock to current security level - 0x1 - - - - - KEY - Must be written as 0x73D to change the register. - 4 - 13 - read-write - - - KWY_VALUE - If set during write, will allow lock or unlock - 0x73D - - - - - - - - - POWERQUAD - Digital Signal Co-Processing companion to a Cortex-M v8M CPU core - POWERQUAD - 0x400A6000 - - 0 - 0x260 - registers - - - PQ - 57 - - - - OUTBASE - Base address register for output region - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - outbase - Base address register for the output region - 0 - 32 - read-write - - - - - OUTFORMAT - Output format - 0x4 - 32 - read-write - 0 - 0xFF33 - - - out_formatint - Output Internal format (00: q15; 01:q31; 10:float) - 0 - 2 - read-write - - - out_formatext - Output External format (00: q15; 01:q31; 10:float) - 4 - 2 - read-write - - - out_scaler - Output Scaler value (for scaled 'q31' formats) - 8 - 8 - read-write - - - - - TMPBASE - Base address register for temp region - 0x8 - 32 - read-write - 0 - 0xFFFFFFFF - - - tmpbase - Base address register for the temporary region - 0 - 32 - read-write - - - - - TMPFORMAT - Temp format - 0xC - 32 - read-write - 0 - 0xFF33 - - - tmp_formatint - Temp Internal format (00: q15; 01:q31; 10:float) - 0 - 2 - read-write - - - tmp_formatext - Temp External format (00: q15; 01:q31; 10:float) - 4 - 2 - read-write - - - tmp_scaler - Temp Scaler value (for scaled 'q31' formats) - 8 - 8 - read-write - - - - - INABASE - Base address register for input A region - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - inabase - Base address register for the input A region - 0 - 32 - read-write - - - - - INAFORMAT - Input A format - 0x14 - 32 - read-write - 0 - 0xFF33 - - - ina_formatint - Input A Internal format (00: q15; 01:q31; 10:float) - 0 - 2 - read-write - - - ina_formatext - Input A External format (00: q15; 01:q31; 10:float) - 4 - 2 - read-write - - - ina_scaler - Input A Scaler value (for scaled 'q31' formats) - 8 - 8 - read-write - - - - - INBBASE - Base address register for input B region - 0x18 - 32 - read-write - 0 - 0xFFFFFFFF - - - inbbase - Base address register for the input B region - 0 - 32 - read-write - - - - - INBFORMAT - Input B format - 0x1C - 32 - read-write - 0 - 0xFF33 - - - inb_formatint - Input B Internal format (00: q15; 01:q31; 10:float) - 0 - 2 - read-write - - - inb_formatext - Input B External format (00: q15; 01:q31; 10:float) - 4 - 2 - read-write - - - inb_scaler - Input B Scaler value (for scaled 'q31' formats) - 8 - 8 - read-write - - - - - CONTROL - PowerQuad Control register - 0x100 - 32 - read-write - 0 - 0x8000FFFF - - - decode_opcode - opcode specific to decode_machine - 0 - 4 - read-write - - - decode_machine - 0 : Coprocessor , 1 : matrix , 2 : fft , 3 : fir , 4 : stat , 5 : cordic , 6 -15 : NA - 4 - 4 - read-write - - - inst_busy - Instruction busy signal when high indicates processing is on - 31 - 1 - read-only - - - - - LENGTH - Length register - 0x104 - 32 - read-write - 0 - 0xFFFFFFFF - - - inst_length - Length register. When FIR : fir_xlength = inst_length[15:0] , fir_tlength = inst_len[31:16]. When MTX : rows_a = inst_length[4:0] , cols_a = inst_length[12:8] , cols_b = inst_length[20:16] - 0 - 32 - read-write - - - - - CPPRE - Pre-scale register - 0x108 - 32 - read-write - 0 - 0x3FFFF - - - cppre_in - co-processor scaling of input - 0 - 8 - read-write - - - cppre_out - co-processor fixed point output - 8 - 8 - read-write - - - cppre_sat - 1 : forces sub-32 bit saturation - 16 - 1 - read-write - - - cppre_sat8 - 0 = 8bits, 1 = 16bits - 17 - 1 - read-write - - - - - MISC - Misc register - 0x10C - 32 - read-write - 0 - 0xFFFFFFFF - - - inst_misc - Misc register. For Matrix : Used for scale factor - 0 - 32 - read-write - - - - - CURSORY - Cursory register - 0x110 - 32 - read-write - 0 - 0x1 - - - cursory - 1 : Enable cursory mode - 0 - 1 - read-write - - - - - CORDIC_X - Cordic input X register - 0x180 - 32 - read-write - 0 - 0xFFFFFFFF - - - cordic_x - Cordic input x - 0 - 32 - read-write - - - - - CORDIC_Y - Cordic input Y register - 0x184 - 32 - read-write - 0 - 0xFFFFFFFF - - - cordic_y - Cordic input y - 0 - 32 - read-write - - - - - CORDIC_Z - Cordic input Z register - 0x188 - 32 - read-write - 0 - 0xFFFFFFFF - - - cordic_z - Cordic input z - 0 - 32 - read-write - - - - - ERRSTAT - Read/Write register where error statuses are captured (sticky) - 0x18C - 32 - read-write - 0 - 0x1F - - - OVERFLOW - overflow - 0 - 1 - read-write - - - NAN - nan - 1 - 1 - read-write - - - FIXEDOVERFLOW - fixed_pt_overflow - 2 - 1 - read-write - - - UNDERFLOW - underflow - 3 - 1 - read-write - - - BUSERROR - bus_error - 4 - 1 - read-write - - - - - INTREN - INTERRUPT enable register - 0x190 - 32 - read-write - 0 - 0x7F - - - intr_oflow - 1 : Enable interrupt on Floating point overflow - 0 - 1 - read-write - - - intr_nan - 1 : Enable interrupt on Floating point NaN - 1 - 1 - read-write - - - intr_fixed - 1: Enable interrupt on Fixed point Overflow - 2 - 1 - read-write - - - intr_uflow - 1 : Enable interrupt on Subnormal truncation - 3 - 1 - read-write - - - intr_berr - 1: Enable interrupt on AHBM Buss Error - 4 - 1 - read-write - - - intr_comp - 1: Enable interrupt on instruction completion - 7 - 1 - read-write - - - - - EVENTEN - Event Enable register - 0x194 - 32 - read-write - 0 - 0xFFFFFFFF - - - event_oflow - 1 : Enable event trigger on Floating point overflow - 0 - 1 - read-write - - - event_nan - 1 : Enable event trigger on Floating point NaN - 1 - 1 - read-write - - - event_fixed - 1: Enable event trigger on Fixed point Overflow - 2 - 1 - read-write - - - event_uflow - 1 : Enable event trigger on Subnormal truncation - 3 - 1 - read-write - - - event_berr - 1: Enable event trigger on AHBM Buss Error - 4 - 1 - read-write - - - event_comp - 1: Enable event trigger on instruction completion - 7 - 1 - read-write - - - - - INTRSTAT - INTERRUPT STATUS register - 0x198 - 32 - read-write - 0 - 0x1 - - - intr_stat - Intr status ( 1 bit to indicate interrupt captured, 0 means no new interrupt), write any value will clear this bit - 0 - 1 - read-write - - - - - 16 - 0x4 - gpreg[%s] - General purpose register bank N. - 0x200 - 32 - read-write - 0 - 0x7CF73 - - - gpreg - General purpose register bank - 0 - 32 - read-write - - - - - 8 - 0x4 - compreg[%s] - Compute register bank - 0x240 - 32 - read-write - 0 - 0xFFFFFFFF - - - compreg - Compute register bank - 0 - 32 - read-write - - - - - - - SECGPIO - General Purpose I/O (GPIO) - GPIO - 0x400A8000 - - 0 - 0x2484 - registers - - - - B0_0 - Byte pin registers for all port GPIO pins - 0 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_1 - Byte pin registers for all port GPIO pins - 0x1 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_2 - Byte pin registers for all port GPIO pins - 0x2 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_3 - Byte pin registers for all port GPIO pins - 0x3 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_4 - Byte pin registers for all port GPIO pins - 0x4 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_5 - Byte pin registers for all port GPIO pins - 0x5 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_6 - Byte pin registers for all port GPIO pins - 0x6 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_7 - Byte pin registers for all port GPIO pins - 0x7 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_8 - Byte pin registers for all port GPIO pins - 0x8 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_9 - Byte pin registers for all port GPIO pins - 0x9 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_10 - Byte pin registers for all port GPIO pins - 0xA - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_11 - Byte pin registers for all port GPIO pins - 0xB - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_12 - Byte pin registers for all port GPIO pins - 0xC - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_13 - Byte pin registers for all port GPIO pins - 0xD - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_14 - Byte pin registers for all port GPIO pins - 0xE - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_15 - Byte pin registers for all port GPIO pins - 0xF - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_16 - Byte pin registers for all port GPIO pins - 0x10 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_17 - Byte pin registers for all port GPIO pins - 0x11 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_18 - Byte pin registers for all port GPIO pins - 0x12 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_19 - Byte pin registers for all port GPIO pins - 0x13 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_20 - Byte pin registers for all port GPIO pins - 0x14 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_21 - Byte pin registers for all port GPIO pins - 0x15 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_22 - Byte pin registers for all port GPIO pins - 0x16 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_23 - Byte pin registers for all port GPIO pins - 0x17 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_24 - Byte pin registers for all port GPIO pins - 0x18 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_25 - Byte pin registers for all port GPIO pins - 0x19 - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_26 - Byte pin registers for all port GPIO pins - 0x1A - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_27 - Byte pin registers for all port GPIO pins - 0x1B - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_28 - Byte pin registers for all port GPIO pins - 0x1C - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_29 - Byte pin registers for all port GPIO pins - 0x1D - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_30 - Byte pin registers for all port GPIO pins - 0x1E - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - B0_31 - Byte pin registers for all port GPIO pins - 0x1F - 8 - read-write - 0 - 0x1 - - - PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 1 - read-write - - - - - W0_0 - Word pin registers for all port GPIO pins - 0x1000 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_1 - Word pin registers for all port GPIO pins - 0x1004 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_2 - Word pin registers for all port GPIO pins - 0x1008 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_3 - Word pin registers for all port GPIO pins - 0x100C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_4 - Word pin registers for all port GPIO pins - 0x1010 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_5 - Word pin registers for all port GPIO pins - 0x1014 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_6 - Word pin registers for all port GPIO pins - 0x1018 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_7 - Word pin registers for all port GPIO pins - 0x101C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_8 - Word pin registers for all port GPIO pins - 0x1020 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_9 - Word pin registers for all port GPIO pins - 0x1024 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_10 - Word pin registers for all port GPIO pins - 0x1028 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_11 - Word pin registers for all port GPIO pins - 0x102C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_12 - Word pin registers for all port GPIO pins - 0x1030 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_13 - Word pin registers for all port GPIO pins - 0x1034 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_14 - Word pin registers for all port GPIO pins - 0x1038 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_15 - Word pin registers for all port GPIO pins - 0x103C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_16 - Word pin registers for all port GPIO pins - 0x1040 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_17 - Word pin registers for all port GPIO pins - 0x1044 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_18 - Word pin registers for all port GPIO pins - 0x1048 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_19 - Word pin registers for all port GPIO pins - 0x104C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_20 - Word pin registers for all port GPIO pins - 0x1050 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_21 - Word pin registers for all port GPIO pins - 0x1054 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_22 - Word pin registers for all port GPIO pins - 0x1058 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_23 - Word pin registers for all port GPIO pins - 0x105C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_24 - Word pin registers for all port GPIO pins - 0x1060 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_25 - Word pin registers for all port GPIO pins - 0x1064 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_26 - Word pin registers for all port GPIO pins - 0x1068 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_27 - Word pin registers for all port GPIO pins - 0x106C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_28 - Word pin registers for all port GPIO pins - 0x1070 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_29 - Word pin registers for all port GPIO pins - 0x1074 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_30 - Word pin registers for all port GPIO pins - 0x1078 - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - W0_31 - Word pin registers for all port GPIO pins - 0x107C - 32 - read-write - 0 - 0xFFFFFFFF - - - PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. - 0 - 32 - read-write - - - - - DIR0 - Direction registers for all port GPIO pins - 0x2000 - 32 - read-write - 0 - 0xFFFFFFFF - - - DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output. - 0 - 32 - read-write - - - - - MASK0 - Mask register for all port GPIO pins - 0x2080 - 32 - read-write - 0 - 0xFFFFFFFF - - - MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. - 0 - 32 - read-write - - - - - PIN0 - Port pin register for all port GPIO pins - 0x2100 - 32 - read-write - 0 - 0xFFFFFFFF - - - PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. - 0 - 32 - read-write - - - - - MPIN0 - Masked port register for all port GPIO pins - 0x2180 - 32 - read-write - 0 - 0xFFFFFFFF - - - MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. - 0 - 32 - read-write - - - - - SET0 - Write: Set register for port. Read: output bits for port - 0x2200 - 32 - read-write - 0 - 0xFFFFFFFF - - - SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. - 0 - 32 - read-write - - - - - CLR0 - Clear port for all port GPIO pins - 0x2280 - 32 - write-only - 0 - 0 - - - CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit. - 0 - 32 - write-only - - - - - NOT0 - Toggle port for all port GPIO pins - 0x2300 - 32 - write-only - 0 - 0 - - - NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit. - 0 - 32 - write-only - - - - - DIRSET0 - Set pin direction bits for port - 0x2380 - 32 - write-only - 0 - 0 - - - DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit. - 0 - 32 - write-only - - - - - DIRCLR0 - Clear pin direction bits for port - 0x2400 - 32 - write-only - 0 - 0 - - - DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit. - 0 - 32 - write-only - - - - - DIRNOT0 - Toggle pin direction bits for port - 0x2480 - 32 - write-only - 0 - 0 - - - DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit. - 0 - 32 - write-only - - - - - - - AHB_SECURE_CTRL - AHB secure controller - AHB_SECURE_CTRL - 0x400AC000 - - 0 - 0x1000 - registers - - - - SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_FLASH_MEM_RULE0 - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_FLASH_MEM_RULE1 - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. - 0x14 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_FLASH_MEM_RULE2 - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. - 0x18 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_ROM_MEM_RULE0 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. - 0x20 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_ROM_MEM_RULE1 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. - 0x24 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_ROM_MEM_RULE2 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. - 0x28 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_ROM_MEM_RULE3 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. - 0x2C - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. - 0x30 - 32 - read-write - 0 - 0xFFFFFFFF - - - RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAMX_MEM_RULE0 - Security access rules for RAMX slaves. - 0x40 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. - 0x50 - 32 - read-write - 0 - 0xFFFFFFFF - - - RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM0_MEM_RULE0 - Security access rules for RAM0 slaves. - 0x60 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM0_MEM_RULE1 - Security access rules for RAM0 slaves. - 0x64 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. - 0x70 - 32 - read-write - 0 - 0xFFFFFFFF - - - RAM1_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM1_MEM_RULE0 - Security access rules for RAM1 slaves. - 0x80 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM1_MEM_RULE1 - Security access rules for RAM1 slaves. - 0x84 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. - 0x90 - 32 - read-write - 0 - 0xFFFFFFFF - - - RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM2_MEM_RULE0 - Security access rules for RAM2 slaves. - 0xA0 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM2_MEM_RULE1 - Security access rules for RAM2 slaves. - 0xA4 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. - 0xB0 - 32 - read-write - 0 - 0xFFFFFFFF - - - RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM3_MEM_RULE0 - Security access rules for RAM3 slaves. - 0xC0 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM3_MEM_RULE1 - Security access rules for RAM3 slaves. - 0xC4 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. - 0xD0 - 32 - read-write - 0 - 0xFFFFFFFF - - - RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_RAM4_MEM_RULE0 - Security access rules for RAM4 slaves. - 0xE0 - 32 - read-write - 0 - 0xFFFFFFFF - - - RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. - 0xF0 - 32 - read-write - 0 - 0xFFFFFFFF - - - APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - SYSCON_RULE - System Configuration - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - IOCON_RULE - I/O Configuration - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - GINT0_RULE - GPIO input Interrupt 0 - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - GINT1_RULE - GPIO input Interrupt 1 - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - PINT_RULE - Pin Interrupt and Pattern match - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SEC_PINT_RULE - Secure Pin Interrupt and Pattern match - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - INPUTMUX_RULE - Peripheral input multiplexing - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. - 0x104 - 32 - read-write - 0 - 0xFFFFFFFF - - - CTIMER0_RULE - Standard counter/Timer 0 - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - CTIMER1_RULE - Standard counter/Timer 1 - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - WWDT_RULE - Windiwed wtachdog Timer - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - MRT_RULE - Multi-rate Timer - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - UTICK_RULE - Micro-Timer - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. - 0x108 - 32 - read-write - 0 - 0xFFFFFFFF - - - ANACTRL_RULE - Analog Modules controller - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. - 0x110 - 32 - read-write - 0 - 0xFFFFFFFF - - - PMC_RULE - Power Management Controller - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SYSCTRL_RULE - System Controller - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. - 0x114 - 32 - read-write - 0 - 0xFFFFFFFF - - - CTIMER2_RULE - Standard counter/Timer 2 - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - CTIMER3_RULE - Standard counter/Timer 3 - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - CTIMER4_RULE - Standard counter/Timer 4 - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RTC_RULE - Real Time Counter - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - OSEVENT_RULE - OS Event Timer - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. - 0x118 - 32 - read-write - 0 - 0xFFFFFFFF - - - FLASH_CTRL_RULE - Flash Controller - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - PRINCE_RULE - Prince - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. - 0x11C - 32 - read-write - 0 - 0xFFFFFFFF - - - USBHPHY_RULE - USB High Speed Phy controller - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - RNG_RULE - True Random Number Generator - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - PUF_RULE - PUF - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - PLU_RULE - Programmable Look-Up logic - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. - 0x120 - 32 - read-write - 0 - 0xFFFFFFFF - - - DMA0_RULE - DMA Controller - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - FS_USB_DEV_RULE - USB Full-speed device - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SCT_RULE - SCTimer - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - FLEXCOMM0_RULE - Flexcomm interface 0 - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - FLEXCOMM1_RULE - Flexcomm interface 1 - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. - 0x124 - 32 - read-write - 0 - 0xFFFFFFFF - - - FLEXCOMM2_RULE - Flexcomm interface 2 - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - FLEXCOMM3_RULE - Flexcomm interface 3 - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - FLEXCOMM4_RULE - Flexcomm interface 4 - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - MAILBOX_RULE - Inter CPU communication Mailbox - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - GPIO0_RULE - High Speed GPIO - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. - 0x130 - 32 - read-write - 0 - 0xFFFFFFFF - - - USB_HS_DEV_RULE - USB high Speed device registers - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - CRC_RULE - CRC engine - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - FLEXCOMM5_RULE - Flexcomm interface 5 - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - FLEXCOMM6_RULE - Flexcomm interface 6 - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. - 0x134 - 32 - read-write - 0 - 0xFFFFFFFF - - - FLEXCOMM7_RULE - Flexcomm interface 7 - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SDIO_RULE - SDMMC card interface - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - HS_LSPI_RULE - High Speed SPI - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_AHB_PORT10_SLAVE0_RULE - Security access rules for AHB peripherals. - 0x140 - 32 - read-write - 0 - 0xFFFFFFFF - - - ADC_RULE - ADC - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - USB_FS_HOST_RULE - USB Full Speed Host registers. - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - USB_HS_HOST_RULE - USB High speed host registers - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - HASH_RULE - SHA-2 crypto registers - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - CASPER_RULE - RSA/ECC crypto accelerator - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - PQ_RULE - Power Quad (CPU0 processor hardware accelerator) - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - DMA1_RULE - DMA Controller (Secure) - 28 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_AHB_PORT10_SLAVE1_RULE - Security access rules for AHB peripherals. - 0x144 - 32 - read-write - 0 - 0xFFFFFFFF - - - GPIO1_RULE - Secure High Speed GPIO - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - AHB_SEC_CTRL_RULE - AHB Secure Controller - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. - 0x150 - 32 - read-write - 0 - 0xFFFFFFFF - - - AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. - 0x160 - 32 - read-write - 0 - 0xFFFFFFFF - - - RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. - 0x170 - 32 - read-write - 0 - 0xFFFFFFFF - - - SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF - 0 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF - 12 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - - - 12 - 0x4 - sec_vio_addr[%s] - most recent security violation address for AHB port n - 0xE00 - 32 - read-only - 0 - 0xFFFFFFFF - - - SEC_VIO_ADDR - security violation address for AHB port - 0 - 32 - read-only - - - - - 12 - 0x4 - sec_vio_misc_info[%s] - most recent security violation miscellaneous information for AHB port n - 0xE80 - 32 - read-only - 0 - 0xFF3 - - - SEC_VIO_INFO_WRITE - security violation access read/write indicator. - 0 - 1 - read-only - - - READ - Read access. - 0 - - - WRITE - Write access. - 0x1 - - - - - SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator. - 1 - 1 - read-only - - - CODE - Code access. - 0 - - - DATA - Data access. - 0x1 - - - - - SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level - 4 - 4 - read-only - - - SEC_VIO_INFO_MASTER - security violation master number - 8 - 4 - read-only - - - VALUE_0 - CPU0 Code. - 0 - - - VALUE_1 - CPU0 System. - 0x1 - - - VALUE_2 - CPU1 Data. - 0x2 - - - VALUE_3 - CPU1 System. - 0x3 - - - VALUE_4 - USB-HS Device. - 0x4 - - - VALUE_5 - SDMA0. - 0x5 - - - VALUE_8 - SDIO. - 0x8 - - - VALUE_9 - PowerQuad. - 0x9 - - - VALUE_10 - HASH. - 0xA - - - VALUE_11 - USB-FS Host. - 0xB - - - VALUE_12 - SDMA1. - 0xC - - - - - - - SEC_VIO_INFO_VALID - security violation address/information registers valid flags - 0xF00 - 32 - read-write - 0 - 0x3FFFF - - - VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear. - 0 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear. - 1 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear. - 2 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear. - 3 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear. - 4 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear. - 5 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear. - 6 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear. - 7 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear. - 8 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear. - 9 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID10 - violation information valid flag for AHB port 10. Write 1 to clear. - 10 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - VIO_INFO_VALID11 - violation information valid flag for AHB port 11. Write 1 to clear. - 11 - 1 - read-write - - - NOT_VALID - Not valid. - 0 - - - VALID - Valid (violation occurred). - 0x1 - - - - - - - SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. - 0xF80 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0 - 0 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1 - 1 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2 - 2 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3 - 3 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4 - 4 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5 - 5 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6 - 6 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7 - 7 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8 - 8 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9 - 9 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10 - 10 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11 - 11 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12 - 12 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13 - 13 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14 - 14 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15 - 15 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16 - 16 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17 - 17 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18 - 18 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19 - 19 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20 - 20 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21 - 21 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22 - 22 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23 - 23 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24 - 24 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25 - 25 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26 - 26 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27 - 27 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28 - 28 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29 - 29 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30 - 30 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31 - 31 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - - - SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. - 0xF84 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0 - 0 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1 - 1 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2 - 2 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3 - 3 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4 - 4 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5 - 5 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6 - 6 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7 - 7 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8 - 8 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9 - 9 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10 - 10 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11 - 11 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12 - 12 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13 - 13 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14 - 14 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15 - 15 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16 - 16 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17 - 17 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18 - 18 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19 - 19 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20 - 20 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21 - 21 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22 - 22 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23 - 23 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24 - 24 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25 - 25 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26 - 26 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27 - 27 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28 - 28 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29 - 29 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30 - 30 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31 - 31 - 1 - read-write - - - BLOCKED - Pin state is blocked to non-secure world. - 0 - - - READABLE - Pin state is readable by non-secure world. - 0x1 - - - - - - - SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 - 0xF90 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - SYS_IRQ - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts - 0 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SDMA0_IRQ - System DMA 0 (non-secure) interrupt. - 1 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_GLOBALINT0_IRQ - GPIO Group 0 interrupt. - 2 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_GLOBALINT1_IRQ - GPIO Group 1 interrupt. - 3 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_INT0_IRQ0 - Pin interrupt 0 or pattern match engine slice 0 interrupt. - 4 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_INT0_IRQ1 - Pin interrupt 1 or pattern match engine slice 1 interrupt. - 5 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_INT0_IRQ2 - Pin interrupt 2 or pattern match engine slice 2 interrupt. - 6 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_INT0_IRQ3 - Pin interrupt 3 or pattern match engine slice 3 interrupt. - 7 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - UTICK_IRQ - Micro Tick Timer interrupt. - 8 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - MRT_IRQ - Multi-Rate Timer interrupt. - 9 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - CTIMER0_IRQ - Standard counter/timer 0 interrupt. - 10 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - CTIMER1_IRQ - Standard counter/timer 1 interrupt. - 11 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SCT_IRQ - SCTimer/PWM interrupt. - 12 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - CTIMER3_IRQ - Standard counter/timer 3 interrupt. - 13 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM0_IRQ - Flexcomm 0 interrupt (USART, SPI, I2C, I2S). - 14 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM1_IRQ - Flexcomm 1 interrupt (USART, SPI, I2C, I2S). - 15 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM2_IRQ - Flexcomm 2 interrupt (USART, SPI, I2C, I2S). - 16 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM3_IRQ - Flexcomm 3 interrupt (USART, SPI, I2C, I2S). - 17 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM4_IRQ - Flexcomm 4 interrupt (USART, SPI, I2C, I2S). - 18 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM5_IRQ - Flexcomm 5 interrupt (USART, SPI, I2C, I2S). - 19 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM6_IRQ - Flexcomm 6 interrupt (USART, SPI, I2C, I2S). - 20 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - FLEXCOMM7_IRQ - Flexcomm 7 interrupt (USART, SPI, I2C, I2S). - 21 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - ADC_IRQ - General Purpose ADC interrupt. - 22 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED0 - Reserved. Read value is undefined, only zero should be written. - 23 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - ACMP_IRQ - Analog Comparator interrupt. - 24 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED1 - Reserved. Read value is undefined, only zero should be written. - 25 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED2 - Reserved. Read value is undefined, only zero should be written. - 26 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - USB0_NEEDCLK - USB Full Speed Controller Clock request interrupt. - 27 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - USB0_IRQ - USB Full Speed Controller interrupt. - 28 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RTC_IRQ - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ - 29 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED3 - Reserved. Read value is undefined, only zero should be written. - 30 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - MAILBOX_IRQ - Mailbox interrupt. - 31 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - - - SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 - 0xF94 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - GPIO_INT0_IRQ4 - Pin interrupt 4 or pattern match engine slice 4 interrupt. - 0 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_INT0_IRQ5 - Pin interrupt 5 or pattern match engine slice 5 interrupt. - 1 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_INT0_IRQ6 - Pin interrupt 6 or pattern match engine slice 6 interrupt. - 2 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - GPIO_INT0_IRQ7 - Pin interrupt 7 or pattern match engine slice 7 interrupt. - 3 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - CTIMER2_IRQ - Standard counter/timer 2 interrupt. - 4 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - CTIMER4_IRQ - Standard counter/timer 4 interrupt. - 5 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - OS_EVENT_TIMER_IRQ - OS Event Timer and OS Event Timer Wakeup interrupts - 6 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED0 - Reserved. Read value is undefined, only zero should be written. - 7 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED1 - Reserved. Read value is undefined, only zero should be written. - 8 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED2 - Reserved. Read value is undefined, only zero should be written. - 9 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SDIO_IRQ - SDIO Controller interrupt. - 10 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED3 - Reserved. Read value is undefined, only zero should be written. - 11 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED4 - Reserved. Read value is undefined, only zero should be written. - 12 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - RESERVED5 - Reserved. Read value is undefined, only zero should be written. - 13 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - USB1_PHY_IRQ - USB High Speed PHY Controller interrupt. - 14 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - USB1_IRQ - USB High Speed Controller interrupt. - 15 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - USB1_NEEDCLK - USB High Speed Controller Clock request interrupt. - 16 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SEC_HYPERVISOR_CALL_IRQ - Secure fault Hyper Visor call interrupt. - 17 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SEC_GPIO_INT0_IRQ0 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt. - 18 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SEC_GPIO_INT0_IRQ1 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt. - 19 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - PLU_IRQ - Programmable Look-Up Controller interrupt. - 20 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SEC_VIO_IRQ - Security Violation interrupt. - 21 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SHA_IRQ - HASH-AES interrupt. - 22 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - CASPER_IRQ - CASPER interrupt. - 23 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - PUFKEY_IRQ - PUF interrupt. - 24 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - PQ_IRQ - Power Quad interrupt. - 25 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - SDMA1_IRQ - System DMA 1 (Secure) interrupt - 26 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - LSPI_HS_IRQ - High Speed SPI interrupt - 27 - 1 - read-write - - - INVISIBLE - no description available - 0 - - - VISIBLE - no description available - 0x1 - - - - - - - SEC_MASK_LOCK - Security General Purpose register access control. - 0xFBC - 32 - read-write - 0xAAA - 0xFFF - - - SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock. - 0 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock. - 2 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - SEC_CPU1_INT_MASK0_LOCK - SEC_CPU_INT_MASK0 register write-lock. - 8 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - SEC_CPU1_INT_MASK1_LOCK - SEC_CPU_INT_MASK1 register write-lock. - 10 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - - - MASTER_SEC_LEVEL - master secure level register - 0xFD0 - 32 - read-write - 0x80000000 - 0xFFFFFFFF - - - CPU1C - Micro-Cortex M33 (CPU1) Code bus. - 4 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - CPU1S - Micro-Cortex M33 (CPU1) System bus. - 6 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - USBFSD - USB Full Speed Device. - 8 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SDMA0 - System DMA 0. - 10 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SDIO - SDIO. - 16 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - PQ - Power Quad. - 18 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - HASH - Hash. - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - USBFSH - USB Full speed Host. - 22 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SDMA1 - System DMA 1 security level. - 24 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock. - 30 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - - - MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register - 0xFD4 - 32 - read-write - 0xBFFFFFFF - 0xFFFFFFFF - - - CPU1C - Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C) - 4 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - CPU1S - Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S) - 6 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) - 8 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) - 10 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - SDIO - SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO) - 16 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - PQ - Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ) - 18 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) - 20 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) - 22 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) - 24 - 2 - read-write - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x1 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x2 - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0x3 - - - - - MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock. - 30 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - - - CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) - 0xFEC - 32 - read-write - 0x800002AA - 0xC00003FF - - - LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock. - 0 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock. - 2 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. - 4 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock. - 6 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock. - 8 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock. - 30 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - - - CPU1_LOCK_REG - Miscalleneous control signals for in micro-Cortex M33 (CPU1) - 0xFF0 - 32 - read-write - 0x8000000A - 0xC000000F - - - LOCK_NS_VTOR - micro-Cortex M33 (CPU1) VTOR_NS register write-lock. - 0 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - LOCK_NS_MPU - micro-Cortex M33 (CPU1) non-secure MPU register write-lock. - 2 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - CPU1_LOCK_REG_LOCK - CPU1_LOCK_REG write-lock. - 30 - 2 - read-write - - - BLOCKED - Restricted mode. - 0x1 - - - WRITABLE - Writable. - 0x2 - - - - - - - MISC_CTRL_DP_REG - secure control duplicate register - 0xFF8 - 32 - read-write - 0xAAAA - 0xFFFF - - - WRITE_LOCK - Write lock. - 0 - 2 - read-write - - - RESTRICTED - Restricted mode. - 0x1 - - - ACCESSIBLE - Secure control registers can be written. - 0x2 - - - - - ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. - 2 - 2 - read-write - - - ENABLE - Restricted mode. - 0x1 - - - DISABLE - Disable check. - 0x2 - - - - - ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. - 4 - 2 - read-write - - - ENABLE - Restricted mode. - 0x1 - - - DISABLE - Disable check. - 0x2 - - - - - ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. - 6 - 2 - read-write - - - ENABLE - Restricted mode. - 0x1 - - - DISABLE - Disable check. - 0x2 - - - - - DISABLE_VIOLATION_ABORT - Disable secure violation abort. - 8 - 2 - read-write - - - DISABLE - Disable abort fort secure checker. - 0x1 - - - ENABLE - Enable abort fort secure checker. - 0x2 - - - - - DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. - 10 - 2 - read-write - - - TIER_MODE - Simple master in tier mode. - 0x1 - - - STRICT_MODE - Simple master in strict mode. - 0x2 - - - - - DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. - 12 - 2 - read-write - - - TIER_MODE - Smart master in tier mode. - 0x1 - - - STRICT_MODE - Smart master in strict mode. - 0x2 - - - - - IDAU_ALL_NS - Disable IDAU. - 14 - 2 - read-write - - - DISABLE - IDAU is disable. - 0x1 - - - ENABLE - IDAU is enabled. - 0x2 - - - - - - - MISC_CTRL_REG - secure control register - 0xFFC - 32 - read-write - 0xAAAA - 0xFFFF - - - WRITE_LOCK - Write lock. - 0 - 2 - read-write - - - RESTRICTED - Restricted mode. - 0x1 - - - ACCESSIBLE - Secure control registers can be written. - 0x2 - - - - - ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. - 2 - 2 - read-write - - - ENABLE - Enabled (restricted mode) - 0x1 - - - DISABLE - Disable check. - 0x2 - - - - - ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. - 4 - 2 - read-write - - - ENABLE - Enabled (restricted mode) - 0x1 - - - DISABLE - Disable check. - 0x2 - - - - - ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. - 6 - 2 - read-write - - - ENABLE - Enabled (restricted mode) - 0x1 - - - DISABLE - Disable check. - 0x2 - - - - - DISABLE_VIOLATION_ABORT - Disable secure violation abort. - 8 - 2 - read-write - - - DISABLE - Disable abort fort secure checker. - 0x1 - - - ENABLE - Enable abort fort secure checker. - 0x2 - - - - - DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. - 10 - 2 - read-write - - - TIER_MODE - Simple master in tier mode. - 0x1 - - - STRICT_MODE - Simple master in strict mode. - 0x2 - - - - - DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. - 12 - 2 - read-write - - - TIER_MODE - Smart master in tier mode. - 0x1 - - - STRICT_MODE - Smart master in strict mode. - 0x2 - - - - - IDAU_ALL_NS - Disable IDAU. - 14 - 2 - read-write - - - DISABLE - IDAU is disable. - 0x1 - - - ENABLE - IDAU is enabled. - 0x2 - - - - - - - - - SCnSCB - no description available - SCNSCB - 0xE000E000 - - 0 - 0x10 - registers - - - - CPPWR - Coprocessor Power Control Register - 0xC - 32 - read-write - 0 - 0 - - - SU0 - State UNKNOWN 0. - 0 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS0 - State UNKNOWN Secure only 0. - 1 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU0 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU0 field is only accessible from the Secure state. - 0x1 - - - - - SU1 - State UNKNOWN 1. - 2 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS1 - State UNKNOWN Secure only 1. - 3 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU7 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU7 field is only accessible from the Secure state. - 0x1 - - - - - SU2 - State UNKNOWN 2. - 4 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS2 - State UNKNOWN Secure only 2. - 5 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU2 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU2 field is only accessible from the Secure state. - 0x1 - - - - - SU3 - State UNKNOWN 3. - 6 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS3 - State UNKNOWN Secure only 3. - 7 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU3 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU3 field is only accessible from the Secure state. - 0x1 - - - - - SU4 - State UNKNOWN 4. - 8 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS4 - State UNKNOWN Secure only 4. - 9 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU4 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU4 field is only accessible from the Secure state. - 0x1 - - - - - SU5 - State UNKNOWN 5. - 10 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS5 - State UNKNOWN Secure only 5. - 11 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU5 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU5 field is only accessible from the Secure state. - 0x1 - - - - - SU6 - State UNKNOWN 6. - 12 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS6 - State UNKNOWN Secure only 6. - 13 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU6 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU6 field is only accessible from the Secure state. - 0x1 - - - - - SU7 - State UNKNOWN 7. - 14 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The coprocessor state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The coprocessor state is permitted to become UNKNOWN. - 0x1 - - - - - SUS7 - State UNKNOWN Secure only 7. - 15 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU7 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU7 field is only accessible from the Secure state. - 0x1 - - - - - SU10 - State UNKNOWN 10. - 20 - 1 - read-write - - - UNKNOWN_NOT_PERMITTED - The floating-point state is not permitted to become UNKNOWN. - 0 - - - UNKNOWN_PERMITTED - The floating-point state is permitted to become UNKNOWN - 0x1 - - - - - SUS10 - State UNKNOWN Secure only 10. - 21 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SU10 field is accessible from both Security states. - 0 - - - SECURE_ONLY - The SU10 field is only accessible from the Secure state. - 0x1 - - - - - SU11 - State UNKNOWN 11. - 22 - 1 - read-write - - - SUS11 - State UNKNOWN Secure only 11. - 23 - 1 - read-write - - - - - - - NVIC - no description available - NVIC - 0xE000E100 - - 0 - 0xE04 - registers - - - - 16 - 0x4 - ISER[%s] - Interrupt Set Enable Register - 0 - 32 - read-write - 0 - 0xFFFFFFFF - - - SETENA0 - Interrupt set-enable bits. - 0 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA1 - Interrupt set-enable bits. - 1 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA2 - Interrupt set-enable bits. - 2 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA3 - Interrupt set-enable bits. - 3 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA4 - Interrupt set-enable bits. - 4 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA5 - Interrupt set-enable bits. - 5 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA6 - Interrupt set-enable bits. - 6 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA7 - Interrupt set-enable bits. - 7 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA8 - Interrupt set-enable bits. - 8 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA9 - Interrupt set-enable bits. - 9 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA10 - Interrupt set-enable bits. - 10 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA11 - Interrupt set-enable bits. - 11 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA12 - Interrupt set-enable bits. - 12 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA13 - Interrupt set-enable bits. - 13 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA14 - Interrupt set-enable bits. - 14 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA15 - Interrupt set-enable bits. - 15 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA16 - Interrupt set-enable bits. - 16 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA17 - Interrupt set-enable bits. - 17 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA18 - Interrupt set-enable bits. - 18 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA19 - Interrupt set-enable bits. - 19 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA20 - Interrupt set-enable bits. - 20 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA21 - Interrupt set-enable bits. - 21 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA22 - Interrupt set-enable bits. - 22 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA23 - Interrupt set-enable bits. - 23 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA24 - Interrupt set-enable bits. - 24 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA25 - Interrupt set-enable bits. - 25 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA26 - Interrupt set-enable bits. - 26 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA27 - Interrupt set-enable bits. - 27 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA28 - Interrupt set-enable bits. - 28 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA29 - Interrupt set-enable bits. - 29 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA30 - Interrupt set-enable bits. - 30 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - SETENA31 - Interrupt set-enable bits. - 31 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - - - 16 - 0x4 - ICER[%s] - Interrupt Clear Enable Register - 0x80 - 32 - read-write - 0 - 0xFFFFFFFF - - - CLRENA0 - Interrupt clear-enable bits. - 0 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA1 - Interrupt clear-enable bits. - 1 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA2 - Interrupt clear-enable bits. - 2 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA3 - Interrupt clear-enable bits. - 3 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA4 - Interrupt clear-enable bits. - 4 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA5 - Interrupt clear-enable bits. - 5 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA6 - Interrupt clear-enable bits. - 6 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA7 - Interrupt clear-enable bits. - 7 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA8 - Interrupt clear-enable bits. - 8 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA9 - Interrupt clear-enable bits. - 9 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA10 - Interrupt clear-enable bits. - 10 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA11 - Interrupt clear-enable bits. - 11 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA12 - Interrupt clear-enable bits. - 12 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA13 - Interrupt clear-enable bits. - 13 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA14 - Interrupt clear-enable bits. - 14 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA15 - Interrupt clear-enable bits. - 15 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA16 - Interrupt clear-enable bits. - 16 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA17 - Interrupt clear-enable bits. - 17 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA18 - Interrupt clear-enable bits. - 18 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA19 - Interrupt clear-enable bits. - 19 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA20 - Interrupt clear-enable bits. - 20 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA21 - Interrupt clear-enable bits. - 21 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA22 - Interrupt clear-enable bits. - 22 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA23 - Interrupt clear-enable bits. - 23 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA24 - Interrupt clear-enable bits. - 24 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA25 - Interrupt clear-enable bits. - 25 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA26 - Interrupt clear-enable bits. - 26 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA27 - Interrupt clear-enable bits. - 27 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA28 - Interrupt clear-enable bits. - 28 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA29 - Interrupt clear-enable bits. - 29 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA30 - Interrupt clear-enable bits. - 30 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - CLRENA31 - Interrupt clear-enable bits. - 31 - 1 - read-write - - - DISABLED - Write: No effect; Read: Interrupt 32n+m disabled - 0 - - - ENABLED - Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled - 0x1 - - - - - - - 16 - 0x4 - ISPR[%s] - Interrupt Set Pending Register - 0x100 - 32 - read-write - 0 - 0xFFFFFFFF - - - SETPEND0 - Interrupt set-pending bits. - 0 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND1 - Interrupt set-pending bits. - 1 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND2 - Interrupt set-pending bits. - 2 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND3 - Interrupt set-pending bits. - 3 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND4 - Interrupt set-pending bits. - 4 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND5 - Interrupt set-pending bits. - 5 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND6 - Interrupt set-pending bits. - 6 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND7 - Interrupt set-pending bits. - 7 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND8 - Interrupt set-pending bits. - 8 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND9 - Interrupt set-pending bits. - 9 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND10 - Interrupt set-pending bits. - 10 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND11 - Interrupt set-pending bits. - 11 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND12 - Interrupt set-pending bits. - 12 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND13 - Interrupt set-pending bits. - 13 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND14 - Interrupt set-pending bits. - 14 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND15 - Interrupt set-pending bits. - 15 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND16 - Interrupt set-pending bits. - 16 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND17 - Interrupt set-pending bits. - 17 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND18 - Interrupt set-pending bits. - 18 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND19 - Interrupt set-pending bits. - 19 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND20 - Interrupt set-pending bits. - 20 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND21 - Interrupt set-pending bits. - 21 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND22 - Interrupt set-pending bits. - 22 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND23 - Interrupt set-pending bits. - 23 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND24 - Interrupt set-pending bits. - 24 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND25 - Interrupt set-pending bits. - 25 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND26 - Interrupt set-pending bits. - 26 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND27 - Interrupt set-pending bits. - 27 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND28 - Interrupt set-pending bits. - 28 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND29 - Interrupt set-pending bits. - 29 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND30 - Interrupt set-pending bits. - 30 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - SETPEND31 - Interrupt set-pending bits. - 31 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending - 0x1 - - - - - - - 16 - 0x4 - ICPR[%s] - Interrupt Clear Pending Register - 0x180 - 32 - read-write - 0 - 0xFFFFFFFF - - - CLRPEND0 - Interrupt clear-pending bits. - 0 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND1 - Interrupt clear-pending bits. - 1 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND2 - Interrupt clear-pending bits. - 2 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND3 - Interrupt clear-pending bits. - 3 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND4 - Interrupt clear-pending bits. - 4 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND5 - Interrupt clear-pending bits. - 5 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND6 - Interrupt clear-pending bits. - 6 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND7 - Interrupt clear-pending bits. - 7 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND8 - Interrupt clear-pending bits. - 8 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND9 - Interrupt clear-pending bits. - 9 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND10 - Interrupt clear-pending bits. - 10 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND11 - Interrupt clear-pending bits. - 11 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND12 - Interrupt clear-pending bits. - 12 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND13 - Interrupt clear-pending bits. - 13 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND14 - Interrupt clear-pending bits. - 14 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND15 - Interrupt clear-pending bits. - 15 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND16 - Interrupt clear-pending bits. - 16 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND17 - Interrupt clear-pending bits. - 17 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND18 - Interrupt clear-pending bits. - 18 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND19 - Interrupt clear-pending bits. - 19 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND20 - Interrupt clear-pending bits. - 20 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND21 - Interrupt clear-pending bits. - 21 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND22 - Interrupt clear-pending bits. - 22 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND23 - Interrupt clear-pending bits. - 23 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND24 - Interrupt clear-pending bits. - 24 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND25 - Interrupt clear-pending bits. - 25 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND26 - Interrupt clear-pending bits. - 26 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND27 - Interrupt clear-pending bits. - 27 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND28 - Interrupt clear-pending bits. - 28 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND29 - Interrupt clear-pending bits. - 29 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND30 - Interrupt clear-pending bits. - 30 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - CLRPEND31 - Interrupt clear-pending bits. - 31 - 1 - read-write - - - NOT_PENDING - Write: No effect; Read: Interrupt 32n+m is not pending - 0 - - - PENDING - Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending - 0x1 - - - - - - - 16 - 0x4 - IABR[%s] - Interrupt Active Bit Register - 0x200 - 32 - read-write - 0 - 0 - - - ACTIVE0 - Active state bits. - 0 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE1 - Active state bits. - 1 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE2 - Active state bits. - 2 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE3 - Active state bits. - 3 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE4 - Active state bits. - 4 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE5 - Active state bits. - 5 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE6 - Active state bits. - 6 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE7 - Active state bits. - 7 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE8 - Active state bits. - 8 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE9 - Active state bits. - 9 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE10 - Active state bits. - 10 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE11 - Active state bits. - 11 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE12 - Active state bits. - 12 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE13 - Active state bits. - 13 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE14 - Active state bits. - 14 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE15 - Active state bits. - 15 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE16 - Active state bits. - 16 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE17 - Active state bits. - 17 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE18 - Active state bits. - 18 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE19 - Active state bits. - 19 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE20 - Active state bits. - 20 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE21 - Active state bits. - 21 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE22 - Active state bits. - 22 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE23 - Active state bits. - 23 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE24 - Active state bits. - 24 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE25 - Active state bits. - 25 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE26 - Active state bits. - 26 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE27 - Active state bits. - 27 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE28 - Active state bits. - 28 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE29 - Active state bits. - 29 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE30 - Active state bits. - 30 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - ACTIVE31 - Active state bits. - 31 - 1 - read-write - - - NOT_ACTIVE - The interrupt is not active. - 0 - - - ACTIVE - The interrupt is active. - 0x1 - - - - - - - 16 - 0x4 - ITNS[%s] - Interrupt Target Non-secure Register - 0x280 - 32 - read-write - 0 - 0 - - - INTS0 - Interrupt Targets Non-secure bits. - 0 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS1 - Interrupt Targets Non-secure bits. - 1 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS2 - Interrupt Targets Non-secure bits. - 2 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS3 - Interrupt Targets Non-secure bits. - 3 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS4 - Interrupt Targets Non-secure bits. - 4 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS5 - Interrupt Targets Non-secure bits. - 5 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS6 - Interrupt Targets Non-secure bits. - 6 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS7 - Interrupt Targets Non-secure bits. - 7 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS8 - Interrupt Targets Non-secure bits. - 8 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS9 - Interrupt Targets Non-secure bits. - 9 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS10 - Interrupt Targets Non-secure bits. - 10 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS11 - Interrupt Targets Non-secure bits. - 11 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS12 - Interrupt Targets Non-secure bits. - 12 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS13 - Interrupt Targets Non-secure bits. - 13 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS14 - Interrupt Targets Non-secure bits. - 14 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS15 - Interrupt Targets Non-secure bits. - 15 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS16 - Interrupt Targets Non-secure bits. - 16 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS17 - Interrupt Targets Non-secure bits. - 17 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS18 - Interrupt Targets Non-secure bits. - 18 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS19 - Interrupt Targets Non-secure bits. - 19 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS20 - Interrupt Targets Non-secure bits. - 20 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS21 - Interrupt Targets Non-secure bits. - 21 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS22 - Interrupt Targets Non-secure bits. - 22 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS23 - Interrupt Targets Non-secure bits. - 23 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS24 - Interrupt Targets Non-secure bits. - 24 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS25 - Interrupt Targets Non-secure bits. - 25 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS26 - Interrupt Targets Non-secure bits. - 26 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS27 - Interrupt Targets Non-secure bits. - 27 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS28 - Interrupt Targets Non-secure bits. - 28 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS29 - Interrupt Targets Non-secure bits. - 29 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS30 - Interrupt Targets Non-secure bits. - 30 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - INTS31 - Interrupt Targets Non-secure bits. - 31 - 1 - read-write - - - SECURE_STATE - The interrupt targets Secure state. - 0 - - - NON_SECURE_STATE - The interrupt targets Non-secure state. - 0x1 - - - - - - - 120 - 0x4 - IPR[%s] - Interrupt Priority Register - 0x300 - 32 - read-write - 0 - 0 - - - PRI_0 - no description available - 0 - 8 - read-write - - - PRI_1 - no description available - 8 - 8 - read-write - - - PRI_2 - no description available - 16 - 8 - read-write - - - PRI_3 - no description available - 24 - 8 - read-write - - - - - STIR - Software Trigger Interrupt Register - 0xE00 - 32 - write-only - 0 - 0xFFFFFFFF - - - INTID - Interrupt ID of the interrupt to trigger, in the range 0-479. - 0 - 9 - write-only - - - - - - - SCB - no description available - SCB - 0xE000ED00 - - 0 - 0x90 - registers - - - - AIRCR - Application Interrupt and Reset Control Register - 0xC - 32 - read-write - 0xFA050000 - 0xFFFFFFFF - - - VECTCLRACTIVE - Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is UNPREDICTABLE. This bit is not banked between Security states. - 1 - 1 - write-only - - - SYSRESETREQ - System reset request. This bit allows software or a debugger to request a system reset. This bit is not banked between Security states. RW if SYSRESETREQS is 0. When SYSRESETREQS is set to 1, from Non-secure state this bit acts as RAZ/WI. - 2 - 1 - read-write - - - NO_REQUEST - Do not request a system reset. - 0 - - - REQUEST_RESET - Request a system reset. - 0x1 - - - - - SYSRESETREQS - System reset request, Secure state only. The value of this bit defines whether the SYSRESETREQ bit is functional for Non-secure use. This bit is not banked between Security states. RW from Secure State and RAZ/WI from Non-secure state. - 3 - 1 - read-write - - - SECURE_AND_NON_SECURE - SYSRESETREQ functionality is available to both Security states. - 0 - - - SECURE_ONLY - SYSRESETREQ functionality is only available to Secure state. - 0x1 - - - - - PRIGROUP - Interrupt priority grouping field. This field determines the split of group priority from subpriority. This bit is banked between Security states - 8 - 3 - read-write - - - BFHFNMINS - BusFault, HardFault, and NMI Non-secure enable. The value of this bit defines whether BusFault and NMI exceptions are Non-secure, and whether exceptions target the Non-secure HardFault exception. This bit is not banked between Security states. RW from Secure-state and RO from Non-secure state. - 13 - 1 - read-write - - - SECURE - BusFault, HardFault, and NMI are Secure. - 0 - - - NON_SECURE - BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault. - 0x1 - - - - - PRIS - Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. This bit is not banked between Security states. RW from Secure state and RAZ/WI from Non-secure state. - 14 - 1 - read-write - - - SAME_PRIORITY - Priority ranges of Secure and Non-secure exceptions are identical - 0 - - - SECURE_PRIORITIZED - Non-secure exceptions are de-prioritized - 0x1 - - - - - ENDIANNESS - Data endianness bit. This bit is not banked between Security states. - 15 - 1 - read-only - - - LITTLE_ENDIAN - Little-endian. - 0 - - - BIG_ENDIAN - Big-endian - 0x1 - - - - - VECTKEY - Register key: Reads as 0xFA05. On writes, write 0x5FA to VECTKEY, otherwise the write is ignored. This Field is not banked between Security states. - 16 - 16 - read-only - - - - - SCR - The SCR controls features of entry to and exit from low-power state. - 0x10 - 32 - read-write - 0 - 0xFFFFFFFF - - - SLEEPONEXIT - Indicates sleep-on-exit when returning from Handler mode to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. This bit is banked between Security states. - 1 - 1 - read-write - - - NOT_SLEEP - Do not sleep when returning to Thread mode. - 0 - - - SLEEP - Enter sleep, or deep sleep, on return from an ISR - 0x1 - - - - - SLEEPDEEP - Controls whether the processor uses sleep or deep sleep as its low-power mode. This bit is not banked between Security states. - 2 - 1 - read-write - - - SLEEP - Sleep. - 0 - - - DEEP_SLEEP - Deep sleep. - 0x1 - - - - - SLEEPDEEPS - Controls whether the SLEEPDEEP bit is only accessible from the Secure state. This bit in only accessible from the Secure state, and behaves as RAZ/WI when accessed from the Nonsecure state. This bit is not banked between Security states. - 3 - 1 - read-write - - - SECURE_AND_NON_SECURE - The SLEEPDEEP bit is accessible from both Security states. - 0 - - - SECURE_ONLY - The SLEEPDEEP bit behaves as RAZ/WI when accessed from the Non-secure state. - 0x1 - - - - - SEVONPEND - Send Event on Pending bit. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event. This bit is banked between Security states. - 4 - 1 - read-write - - - EXCLUDE_DISABLED_INTERRUPTS - Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. - 0 - - - INCLUDE_DISABLED_INTERRUPTS - Enabled events and all interrupts, including disabled interrupts, can wakeup the processor - 0x1 - - - - - - - SHCSR - System Handler Control and State Register - 0x24 - 32 - read-write - 0 - 0xFFFFFFFF - - - MEMFAULTACT - MemManage exception active. - 0 - 1 - read-write - - - NOT_ACTIVE - MemManage exception is not active. - 0 - - - ACTIVE - MemManage exception is active. - 0x1 - - - - - BUSFAULTACT - BusFault exception active. - 1 - 1 - read-write - - - NOT_ACTIVE - BusFault exception is not active. - 0 - - - ACTIVE - BusFault exception is active. - 0x1 - - - - - HARDFAULTACT - HardFault exception active. - 2 - 1 - read-write - - - NOT_ACTIVE - HardFault exception is not active. - 0 - - - ACTIVE - HardFault exception is active. - 0x1 - - - - - USGFAULTACT - UsageFault exception active. - 3 - 1 - read-write - - - NOT_ACTIVE - UsageFault exception is not active. - 0 - - - ACTIVE - UsageFault exception is active. - 0x1 - - - - - SECUREFAULTACT - SecureFault exception active - 4 - 1 - read-write - - - NOT_ACTIVE - SecureFault exception is not active. - 0 - - - ACTIVE - SecureFault exception is active. - 0x1 - - - - - NMIACT - NMI exception active. - 5 - 1 - read-write - - - NOT_ACTIVE - NMI exception is not active. - 0 - - - ACTIVE - NMI exception is active. - 0x1 - - - - - SVCALLACT - SVCall active. - 7 - 1 - read-write - - - NOT_ACTIVE - SVCall exception is not active. - 0 - - - ACTIVE - SVCall exception is active. - 0x1 - - - - - MONITORACT - Debug monitor active. - 8 - 1 - read-write - - - NOT_ACTIVE - Debug monitor exception is not active. - 0 - - - ACTIVE - Debug monitor exception is active. - 0x1 - - - - - PENDSVACT - PendSV exception active. - 10 - 1 - read-write - - - NOT_ACTIVE - PendSV exception is not active. - 0 - - - ACTIVE - PendSV exception is active. - 0x1 - - - - - SYSTICKACT - SysTick exception active. - 11 - 1 - read-write - - - NOT_ACTIVE - SysTick exception is not active. - 0 - - - ACTIVE - SysTick exception is active. - 0x1 - - - - - USGFAULTPENDED - UsageFault exception pending. - 12 - 1 - read-write - - - NOT_PENDING - UsageFault exception is not pending. - 0 - - - PENDING - UsageFault exception is pending. - 0x1 - - - - - MEMFAULTPENDED - MemManage exception pending. - 13 - 1 - read-write - - - NOT_PENDING - MemManage exception is not pending. - 0 - - - PENDING - MemManage exception is pending. - 0x1 - - - - - BUSFAULTPENDED - BusFault exception pending. - 14 - 1 - read-write - - - NOT_PENDING - BusFault exception is pending. - 0 - - - PENDING - BusFault exception is not pending. - 0x1 - - - - - SVCALLPENDED - SVCall pending. - 15 - 1 - read-write - - - NOT_PENDING - SVCall exception is not pending. - 0 - - - PENDING - SVCall exception is pending. - 0x1 - - - - - MEMFAULTENA - MemManage enable. - 16 - 1 - read-write - - - DISABLED - MemManage exception is disabled. - 0 - - - ENABLED - MemManage exception is enabled. - 0x1 - - - - - BUSFAULTENA - BusFault enable. - 17 - 1 - read-write - - - DISABLED - BusFault is disabled. - 0 - - - ENABLED - BusFault is enabled. - 0x1 - - - - - USGFAULTENA - UsageFault enable. - 18 - 1 - read-write - - - DISABLED - UsageFault is disabled. - 0 - - - ENABLED - UsageFault is enabled. - 0x1 - - - - - SECUREFAULTENA - SecureFault exception enable. - 19 - 1 - read-write - - - DISABLED - SecureFault exception is disabled. - 0 - - - ENABLED - SecureFault exception is enabled. - 0x1 - - - - - SECUREFAULTPENDED - SecureFault exception pended state bit. - 20 - 1 - read-write - - - DISABLED - SecureFault exception modification is disabled. - 0 - - - ENABLED - SecureFault exception modification is enabled. - 0x1 - - - - - HARDFAULTPENDED - HardFault exception pended state - 21 - 1 - read-write - - - DISABLED - HardFault exception modification is disabled. - 0 - - - ENABLED - HardFault exception modification is enabled. - 0x1 - - - - - - - NSACR - Non-secure Access Control Register - 0x8C - 32 - read-write - 0 - 0 - - - CP0 - CP0 access. - 0 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP1 - CP1 access. - 1 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP2 - CP2 access. - 2 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP3 - CP3 access. - 3 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP4 - CP4 access. - 4 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP5 - CP5 access. - 5 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP6 - CP6 access. - 6 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP7 - CP7 access. - 7 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to this coprocessor generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to this coprocessor permitted. - 0x1 - - - - - CP10 - CP10 access. - 10 - 1 - read-write - - - NOT_PERMITTED - Non-secure accesses to the Floating-point Extension generate a NOCP UsageFault. - 0 - - - PERMITTED - Non-secure access to the Floatingpoint Extension permitted. - 0x1 - - - - - CP11 - CP11 access. - 11 - 1 - read-write - - - - - - - SAU - no description available - SAU - 0xE000EDD0 - - 0 - 0xEC - registers - - - - CTRL - Security Attribution Unit Control Register - 0xD0 - 32 - read-write - 0 - 0xFFFFFFFF - - - ENABLE - Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region. - 0 - 1 - read-write - - - DISABLED - The SAU is disabled. - 0 - - - ENABLED - The SAU is enabled. - 0x1 - - - - - ALLNS - All Non-secure. - 1 - 1 - read-write - - - SECURED_MEMORY - Memory is marked as Secure and is not Non-secure callable. - 0 - - - NON_SECURED_MEMORY - Memory is marked as Non-secure. - 0x1 - - - - - - - TYPE - Security Attribution Unit Type Register - 0xD4 - 32 - read-write - 0 - 0xFFFFFFFF - - - SREGION - SAU regions. The number of implemented SAU regions. - 0 - 8 - read-write - - - - - RNR - Security Attribution Unit Region Number Register - 0xD8 - 32 - read-write - 0 - 0 - - - REGION - Region number. - 0 - 8 - read-write - - - - - RBAR - Security Attribution Unit Region Base Address Register - 0xDC - 32 - read-write - 0 - 0 - - - BADDR - Base address. Holds bits[31:5] of the base address for the selected SAU region. Bits[4:0] of the base address are defined as 0x00. - 5 - 27 - read-write - - - - - RLAR - Security Attribution Unit Region Limit Address Register - 0xE0 - 32 - read-write - 0 - 0 - - - ENABLE - Enable. SAU region enable. - 0 - 1 - read-write - - - ENABLED - SAU region is enabled. - 0 - - - DISABLED - SAU region is disabled. - 0x1 - - - - - NSC - Non-secure callable. Controls whether Non-secure state is permitted to execute an SG instruction from this region. - 1 - 1 - read-write - - - NOT_NON_SECURE_CALLABLE - Region is not Non-secure callable. - 0 - - - NON_SECURE_CALLABLE - Region is Non-secure callable. - 0x1 - - - - - LADDR - Limit address. Holds bits[31:5] of the limit address for the selected SAU region. Bits[4:0] of the limit address are defined as 0x1F. - 5 - 27 - read-write - - - - - SFSR - Secure Fault Status Register - 0xE4 - 32 - read-write - 0 - 0xFFFFFFFF - - - INVEP - Invalid entry point. - 0 - 1 - read-write - - - NO_ERROR - Error has not occurred. - 0 - - - ERROR - Error has occurred. - 0x1 - - - - - INVIS - Invalid integrity signature flag. - 1 - 1 - read-write - - - NO_ERROR - Error has not occurred. - 0 - - - ERROR - Error has occurred. - 0x1 - - - - - INVER - Invalid exception return flag. - 2 - 1 - read-write - - - NO_ERROR - Error has not occurred. - 0 - - - ERROR - Error has occurred. - 0x1 - - - - - AUVIOL - Attribution unit violation flag. - 3 - 1 - read-write - - - NO_ERROR - Error has not occurred. - 0 - - - ERROR - Error has occurred. - 0x1 - - - - - INVTRAN - Invalid transition flag. - 4 - 1 - read-write - - - NO_ERROR - Error has not occurred. - 0 - - - ERROR - Error has occurred. - 0x1 - - - - - LSPERR - Lazy state preservation error flag. - 5 - 1 - read-write - - - NO_ERROR - Error has not occurred. - 0 - - - ERROR - Error has occurred. - 0x1 - - - - - SFARVALID - Secure fault address valid. - 6 - 1 - read-write - - - NOT_VALID - SFAR content not valid. - 0 - - - VALID - SFAR content valid. - 0x1 - - - - - LSERR - Lazy state error flag. - 7 - 1 - read-write - - - NO_ERROR - Error has not occurred - 0 - - - ERROR - Error has occurred. - 0x1 - - - - - - - SFAR - Secure Fault Address Register - 0xE8 - 32 - read-write - 0 - 0 - - - ADDRESS - When the SFARVALID bit of the SFSR is set to 1, this field holds the address of an access that caused an SAU violation. - 0 - 32 - read-write - - - - - - - \ No newline at end of file diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1_features.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1_features.h deleted file mode 100644 index 2e189cda53f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1_features.h +++ /dev/null @@ -1,447 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.1, 2019-05-16 -** Build: b220303 -** -** Abstract: -** Chip specific module features. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** - rev. 1.1 (2019-05-16) -** Initial A1 version based on v1.3UM -** -** ################################################################### -*/ - -#ifndef _LPC55S69_cm33_core1_FEATURES_H_ -#define _LPC55S69_cm33_core1_FEATURES_H_ - -/* SOC module features */ - -/* @brief CASPER availability on the SoC. */ -#define FSL_FEATURE_SOC_CASPER_COUNT (1) -/* @brief CRC availability on the SoC. */ -#define FSL_FEATURE_SOC_CRC_COUNT (1) -/* @brief CTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_CTIMER_COUNT (5) -/* @brief DMA availability on the SoC. */ -#define FSL_FEATURE_SOC_DMA_COUNT (2) -/* @brief FLASH availability on the SoC. */ -#define FSL_FEATURE_SOC_FLASH_COUNT (1) -/* @brief FLEXCOMM availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) -/* @brief GINT availability on the SoC. */ -#define FSL_FEATURE_SOC_GINT_COUNT (2) -/* @brief GPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_GPIO_COUNT (1) -/* @brief SECGPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_SECGPIO_COUNT (1) -/* @brief HASHCRYPT availability on the SoC. */ -#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) -/* @brief I2C availability on the SoC. */ -#define FSL_FEATURE_SOC_I2C_COUNT (8) -/* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (8) -/* @brief INPUTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) -/* @brief IOCON availability on the SoC. */ -#define FSL_FEATURE_SOC_IOCON_COUNT (1) -/* @brief LPADC availability on the SoC. */ -#define FSL_FEATURE_SOC_LPADC_COUNT (1) -/* @brief MAILBOX availability on the SoC. */ -#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) -/* @brief MRT availability on the SoC. */ -#define FSL_FEATURE_SOC_MRT_COUNT (1) -/* @brief OSTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) -/* @brief PINT availability on the SoC. */ -#define FSL_FEATURE_SOC_PINT_COUNT (1) -/* @brief SECPINT availability on the SoC. */ -#define FSL_FEATURE_SOC_SECPINT_COUNT (1) -/* @brief PMC availability on the SoC. */ -#define FSL_FEATURE_SOC_PMC_COUNT (1) -/* @brief POWERQUAD availability on the SoC. */ -#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) -/* @brief PUF availability on the SoC. */ -#define FSL_FEATURE_SOC_PUF_COUNT (1) -/* @brief LPC_RNG1 availability on the SoC. */ -#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) -/* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (1) -/* @brief SCT availability on the SoC. */ -#define FSL_FEATURE_SOC_SCT_COUNT (1) -/* @brief SDIF availability on the SoC. */ -#define FSL_FEATURE_SOC_SDIF_COUNT (1) -/* @brief SPI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPI_COUNT (9) -/* @brief SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCON_COUNT (1) -/* @brief SYSCTL1 availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) -/* @brief USART availability on the SoC. */ -#define FSL_FEATURE_SOC_USART_COUNT (8) -/* @brief USB availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_COUNT (1) -/* @brief USBFSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBFSH_COUNT (1) -/* @brief USBHSD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSD_COUNT (1) -/* @brief USBHSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSH_COUNT (1) -/* @brief USBPHY availability on the SoC. */ -#define FSL_FEATURE_SOC_USBPHY_COUNT (1) -/* @brief UTICK availability on the SoC. */ -#define FSL_FEATURE_SOC_UTICK_COUNT (1) -/* @brief WWDT availability on the SoC. */ -#define FSL_FEATURE_SOC_WWDT_COUNT (1) - -/* LPADC module features */ - -/* @brief FIFO availability on the SoC. */ -#define FSL_FEATURE_LPADC_FIFO_COUNT (2) -/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) -/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) -/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) -/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) -/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) -/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) -/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) -/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) -/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) -/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) -/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) -/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) -/* @brief Has calibration (bitfield CFG[CALOFS]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) -/* @brief Has offset trim (register OFSTRIM). */ -#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) -/* @brief Has Trigger status register. */ -#define FSL_FEATURE_LPADC_HAS_TSTAT (1) -/* @brief Has power select (bitfield CFG[PWRSEL]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) -/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) -/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) -/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) -/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) -/* @brief Conversion averaged bitfiled width. */ -#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) -/* @brief Has internal temperature sensor. */ -#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) -/* @brief Temperature sensor parameter A (slope). */ -#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (744.6f) -/* @brief Temperature sensor parameter B (offset). */ -#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (313.7f) -/* @brief Temperature sensor parameter Alpha. */ -#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.5f) -/* @brief the buffer size of temperature sensor. */ -#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U) - -/* ANALOGCTRL module features */ - -/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ -#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) -/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ -#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (0) -/* @brief Has auxiliary bias(register AUX_BIAS). */ -#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1) - -/* CASPER module features */ - -/* @brief Base address of the CASPER dedicated RAM */ -#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) -/* @brief SW interleaving of the CASPER dedicated RAM */ -#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1) -/* @brief CASPER dedicated RAM offset */ -#define FSL_FEATURE_CASPER_RAM_OFFSET (0xE) - -/* CTIMER module features */ - -/* @brief CTIMER has no capture channel. */ -#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) -/* @brief CTIMER has no capture 2 interrupt. */ -#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) -/* @brief CTIMER capture 3 interrupt. */ -#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) -/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ -#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) -/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ -#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) - -/* DMA module features */ - -/* @brief Number of channels */ -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23) -/* @brief Align size of DMA descriptor */ -#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) -/* @brief DMA head link descriptor table align size */ -#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) - -/* FLEXCOMM module features */ - -/* @brief FLEXCOMM0 USART INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) -/* @brief FLEXCOMM0 SPI INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) -/* @brief FLEXCOMM0 I2C INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) -/* @brief FLEXCOMM0 I2S INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) -/* @brief FLEXCOMM1 USART INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) -/* @brief FLEXCOMM1 SPI INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) -/* @brief FLEXCOMM1 I2C INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) -/* @brief FLEXCOMM1 I2S INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) -/* @brief FLEXCOMM2 USART INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) -/* @brief FLEXCOMM2 SPI INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) -/* @brief FLEXCOMM2 I2C INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) -/* @brief FLEXCOMM2 I2S INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) -/* @brief FLEXCOMM3 USART INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) -/* @brief FLEXCOMM3 SPI INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) -/* @brief FLEXCOMM3 I2C INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) -/* @brief FLEXCOMM3 I2S INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) -/* @brief FLEXCOMM4 USART INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) -/* @brief FLEXCOMM4 SPI INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) -/* @brief FLEXCOMM4 I2C INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) -/* @brief FLEXCOMM4 I2S INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) -/* @brief FLEXCOMM5 USART INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) -/* @brief FLEXCOMM5 SPI INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) -/* @brief FLEXCOMM5 I2C INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) -/* @brief FLEXCOMM5 I2S INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) -/* @brief FLEXCOMM6 USART INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) -/* @brief FLEXCOMM6 SPI INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) -/* @brief FLEXCOMM6 I2C INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) -/* @brief FLEXCOMM6 I2S INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) -/* @brief FLEXCOMM7 USART INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) -/* @brief FLEXCOMM7 SPI INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) -/* @brief FLEXCOMM7 I2C INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) -/* @brief FLEXCOMM7 I2S INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) -/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ -#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) -/* @brief I2S has DMIC interconnection */ -#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) - -/* HASHCRYPT module features */ - -/* @brief the address of alias offset */ -#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000) - -/* I2S module features */ - -/* @brief I2S support dual channel transfer. */ -#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0) -/* @brief I2S has DMIC interconnection */ -#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) - -/* IOCON module features */ - -/* @brief Func bit field width */ -#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) - -/* MAILBOX module features */ - -/* @brief Mailbox side for current core */ -#define FSL_FEATURE_MAILBOX_SIDE_B (1) - -/* MRT module features */ - -/* @brief number of channels. */ -#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) - -/* PINT module features */ - -/* @brief Number of connected outputs */ -#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) - -/* PLU module features */ - -/* @brief Has WAKEINT_CTRL register. */ -#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) - -/* PMC module features */ - -/* @brief UTICK does not support PD configure. */ -#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) -/* @brief WDT OSC does not support PD configure. */ -#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) - -/* POWERLIB module features */ - -/* @brief Powerlib API is different with other LPC series devices. */ -#define FSL_FEATURE_POWERLIB_EXTEND (1) - -/* POWERQUAD module features */ - -/* @brief Sine and Cossine fix errata */ -#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1) - -/* PUF module features */ - -/* @brief Number of PUF key slots available on device. */ -#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4) -/* @brief the shift status value */ -#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) - -/* RTC module features */ - -/* No feature definitions */ - -/* SCT module features */ - -/* @brief Number of events */ -#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) -/* @brief Number of states */ -#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) -/* @brief Number of match capture */ -#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) -/* @brief Number of outputs */ -#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) - -/* SDIF module features */ - -/* @brief FIFO depth, every location is a WORD */ -#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) -/* @brief Max DMA buffer size */ -#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) -/* @brief Max source clock in HZ */ -#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) -/* @brief support 2 cards */ -#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1) - -/* SECPINT module features */ - -/* @brief Number of connected outputs */ -#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) - -/* SYSCON module features */ - -/* @brief Flash page size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) -/* @brief Flash sector size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) -/* @brief Flash size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (645120) -/* @brief Has Power Down mode */ -#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) -/* @brief CCM_ANALOG availability on the SoC. */ -#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) -/* @brief Starter register discontinuous. */ -#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) - -/* SYSCTL1 module features */ - -/* No feature definitions */ - -/* USB module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USB_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USB version */ -#define FSL_FEATURE_USB_VERSION (200) -/* @brief Number of the endpoint in USB FS */ -#define FSL_FEATURE_USB_EP_NUM (5) - -/* USBFSH module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USBFSH version */ -#define FSL_FEATURE_USBFSH_VERSION (200) - -/* USBHSD module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USBHSD version */ -#define FSL_FEATURE_USBHSD_VERSION (300) -/* @brief Number of the endpoint in USB HS */ -#define FSL_FEATURE_USBHSD_EP_NUM (6) - -/* USBHSH module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USBHSH version */ -#define FSL_FEATURE_USBHSH_VERSION (300) - -/* USBPHY module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBPHY_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USBHSD version */ -#define FSL_FEATURE_USBPHY_VERSION (300) -/* @brief Number of the endpoint in USB HS */ -#define FSL_FEATURE_USBPHY_EP_NUM (6) - -/* WWDT module features */ - -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) -/* @brief WWDT does not support oscillator lock. */ -#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) - -#endif /* _LPC55S69_cm33_core1_FEATURES_H_ */ - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash.scf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash.scf deleted file mode 100644 index 67cd92d97b9..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash.scf +++ /dev/null @@ -1,105 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JBD64_cm33_core0 -** LPC55S69JEV98_cm33_core0 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b210928 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#define m_interrupts_start 0x00000000 -#define m_interrupts_size 0x00000200 - -#define m_text_start 0x00000200 -#define m_text_size 0x00071E00 - -#define m_core1_image_start 0x00072000 -#define m_core1_image_size 0x0002B800 - -#if (defined(__use_shmem__)) - #define m_data_start 0x20000000 - #define m_data_size 0x00031800 - #define m_rpmsg_sh_mem_start 0x20031800 - #define m_rpmsg_sh_mem_size 0x00001800 -#else - #define m_data_start 0x20000000 - #define m_data_size 0x00033000 -#endif - -#define m_usb_sram_start 0x40100000 -#define m_usb_sram_size 0x00004000 - - -LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region - - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - -#if (defined(__use_shmem__)) - RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG - * (rpmsg_sh_mem_section) - } -#endif - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - - RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (*m_usb_bdt) - } - - RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (*m_usb_global) - } -} - -LR_CORE1_IMAGE m_core1_image_start { - CORE1_REGION m_core1_image_start m_core1_image_size { - * (.core1_code) - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_ns.scf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_ns.scf deleted file mode 100644 index d3162db09fd..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_ns.scf +++ /dev/null @@ -1,107 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JBD64_cm33_core0 -** LPC55S69JEV98_cm33_core0 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b190923 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -/* The first 64kB of FLASH is used as secure memory. The rest of FLASH memory is non-secure memory. */ -#define m_interrupts_start 0x00010000 -#define m_interrupts_size 0x00000200 - -#define m_text_start 0x00010200 -#define m_text_size 0x00061E00 - -#define m_core1_image_start 0x00072000 -#define m_core1_image_size 0x0002B800 - -/* The first 32kB of data RAM is used as secure memory. The rest of data RAM memory is non-secure memory. */ -#if (defined(__use_shmem__)) - #define m_data_start 0x20008000 - #define m_data_size 0x00029000 - #define m_rpmsg_sh_mem_start 0x20031800 - #define m_rpmsg_sh_mem_size 0x00001800 -#else - #define m_data_start 0x20008000 - #define m_data_size 0x0002B000 -#endif - -#define m_usb_sram_start 0x40100000 -#define m_usb_sram_size 0x00004000 - - -LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region - - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - -#if (defined(__use_shmem__)) - RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG - * (rpmsg_sh_mem_section) - } -#endif - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - - RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (*m_usb_bdt) - } - - RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (*m_usb_global) - } -} - -LR_CORE1_IMAGE m_core1_image_start { - CORE1_REGION m_core1_image_start m_core1_image_size { - * (.core1_code) - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_s.scf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_s.scf deleted file mode 100644 index fe8d3f6b9d6..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_s.scf +++ /dev/null @@ -1,116 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JBD64_cm33_core0 -** LPC55S69JEV98_cm33_core0 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b190923 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -/* Only the first 64kB of flash is used as secure memory. */ -#define m_interrupts_start 0x10000000 -#define m_interrupts_size 0x00000200 - -#define m_text_start 0x10000200 -#define m_text_size 0x0000FC00 - -#define m_core1_image_start 0x10072000 -#define m_core1_image_size 0x0002B800 - -/* Only first 32kB of data RAM is used as secure memory. */ -#if (defined(__use_shmem__)) - #define m_data_start 0x30000000 - #define m_data_size 0x00008000 - #define m_rpmsg_sh_mem_start 0x30031800 - #define m_rpmsg_sh_mem_size 0x00001800 -#else - #define m_data_start 0x30000000 - #define m_data_size 0x00008000 -#endif - -/* 512B - memory for veneer table (NSC - secure, non-secure callable memory) */ -#define m_veneer_table_start 0x1000FE00 -#define m_veneer_table_size 0x200 - - -#define m_usb_sram_start 0x50100000 -#define m_usb_sram_size 0x00004000 - - -LR_m_text m_interrupts_start m_interrupts_size+m_text_size+m_veneer_table_size { ; load region size_region - - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - -#if (defined(__use_shmem__)) - RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG - * (rpmsg_sh_mem_section) - } -#endif - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - - ER_m_veneer_table m_veneer_table_start FIXED m_veneer_table_size {; veneer table - *(Veneer$$CMSE) - } - - RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (*m_usb_bdt) - } - - RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (*m_usb_global) - } -} - -LR_CORE1_IMAGE m_core1_image_start { - CORE1_REGION m_core1_image_start m_core1_image_size { - * (.core1_code) - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_ram.scf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_ram.scf deleted file mode 100644 index 797443048a5..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_ram.scf +++ /dev/null @@ -1,105 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JBD64_cm33_core0 -** LPC55S69JEV98_cm33_core0 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b200722 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2020 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#define m_interrupts_start 0x04000000 -#define m_interrupts_size 0x00000200 - -#define m_text_start 0x04000200 -#define m_text_size 0x00007E00 - -#define m_core1_image_start 0x20033000 -#define m_core1_image_size 0x0000C800 - -#if (defined(__use_shmem__)) - #define m_data_start 0x20000000 - #define m_data_size 0x00031800 - #define m_rpmsg_sh_mem_start 0x20031800 - #define m_rpmsg_sh_mem_size 0x00001800 -#else - #define m_data_start 0x20000000 - #define m_data_size 0x00033000 -#endif - -#define m_usb_sram_start 0x40100000 -#define m_usb_sram_size 0x00004000 - - -LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region - - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - -#if (defined(__use_shmem__)) - RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG - * (rpmsg_sh_mem_section) - } -#endif - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - - RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (*m_usb_bdt) - } - - RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (*m_usb_global) - } -} - -LR_CORE1_IMAGE m_core1_image_start { - CORE1_REGION m_core1_image_start m_core1_image_size { - * (.core1_code) - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_flash.scf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_flash.scf deleted file mode 100644 index b54320ccb78..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_flash.scf +++ /dev/null @@ -1,96 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JBD64_cm33_core1 -** LPC55S69JEV98_cm33_core1 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b210928 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#define m_interrupts_start 0x00072000 -#define m_interrupts_size 0x00000200 - -#define m_text_start 0x00072200 -#define m_text_size 0x0002B600 - - -#define m_data_start 0x20033000 -#define m_data_size 0x00011000 - -#if (defined(__use_shmem__)) - #define m_rpmsg_sh_mem_start 0x20031800 - #define m_rpmsg_sh_mem_size 0x00001800 -#endif - -#define m_usb_sram_start 0x40100000 -#define m_usb_sram_size 0x00004000 - - -LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region - - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - - RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (*m_usb_bdt) - } - - RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (*m_usb_global) - } - #if (defined(__use_shmem__)) - RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG - * (rpmsg_sh_mem_section) - } - #endif - } - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram.scf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram.scf deleted file mode 100644 index f3ba53c93ad..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram.scf +++ /dev/null @@ -1,96 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JBD64_cm33_core1 -** LPC55S69JEV98_cm33_core1 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b200722 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2020 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#define m_interrupts_start 0x20033000 -#define m_interrupts_size 0x00000200 - -#define m_text_start 0x20033200 -#define m_text_size 0x0000C600 - - -#define m_data_start 0x2003F800 -#define m_data_size 0x00004800 - -#if (defined(__use_shmem__)) - #define m_rpmsg_sh_mem_start 0x20031800 - #define m_rpmsg_sh_mem_size 0x00001800 -#endif - -#define m_usb_sram_start 0x40100000 -#define m_usb_sram_size 0x00004000 - - -LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region - - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - - RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (*m_usb_bdt) - } - - RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (*m_usb_global) - } - #if (defined(__use_shmem__)) - RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG - * (rpmsg_sh_mem_section) - } - #endif - } - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram_s.scf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram_s.scf deleted file mode 100644 index d67fdecb6e1..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram_s.scf +++ /dev/null @@ -1,96 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JBD64_cm33_core1 -** LPC55S69JEV98_cm33_core1 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b190923 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#define m_interrupts_start 0x30033000 -#define m_interrupts_size 0x00000200 - -#define m_text_start 0x30033200 -#define m_text_size 0x0000C600 - - -#define m_data_start 0x3003F800 -#define m_data_size 0x00004800 - -#if (defined(__use_shmem__)) - #define m_rpmsg_sh_mem_start 0x30031800 - #define m_rpmsg_sh_mem_size 0x00001800 -#endif - -#define m_usb_sram_start 0x50100000 -#define m_usb_sram_size 0x00004000 - - -LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region - - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - - RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (*m_usb_bdt) - } - - RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (*m_usb_global) - } -#if (defined(__use_shmem__)) - RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG - * (rpmsg_sh_mem_section) - } -#endif -} - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55XX_640.FLM b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55XX_640.FLM deleted file mode 100644 index 167a941d8f2..00000000000 Binary files a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55XX_640.FLM and /dev/null differ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55XX_S_640.FLM b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55XX_S_640.FLM deleted file mode 100644 index 53dcca7bd23..00000000000 Binary files a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55XX_S_640.FLM and /dev/null differ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55xx.dbgconf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55xx.dbgconf deleted file mode 100644 index 1cc3a2af84a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55xx.dbgconf +++ /dev/null @@ -1,18 +0,0 @@ -// <<< Use Configuration Wizard in Context Menu >>> - -// SWO pin -// The SWO (Serial Wire Output) pin optionally provides data from the ITM -// for an external debug tool to evaluate. -// <0=> PIO0_10 -// <1=> PIO0_8 -SWO_Pin = 0; -// - -// Debug Configuration -// StopAfterBootloader Stop after Bootloader -// -Dbg_CR = 0x00000001; -// - - -// <<< end of configuration section >>> \ No newline at end of file diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core0.s b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core0.s deleted file mode 100644 index 9a573e0c1dc..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core0.s +++ /dev/null @@ -1,801 +0,0 @@ -/* --------------------------------------------------------------------------------------- - * @file: startup_LPC55S69_cm33_core0.s - * @purpose: CMSIS Cortex-M33 Core Device Startup File for the LPC55S69_cm33_core0 - * @version: 1.1 - * @date: 2019-5-16 - * ---------------------------------------------------------------------------------------*/ -/* - * Copyright 1997-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - - .syntax unified - .arch armv8-m.main - .eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */ - - .section .isr_vector, "a" - .align 2 - .globl __Vectors - -__Vectors: - .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long MemManage_Handler /* MPU Fault Handler*/ - .long BusFault_Handler /* Bus Fault Handler*/ - .long UsageFault_Handler /* Usage Fault Handler*/ - .long SecureFault_Handler /* Secure Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long DebugMon_Handler /* Debug Monitor Handler*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts*/ - .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ - .long DMA0_IRQHandler /* DMA0 controller */ - .long GINT0_IRQHandler /* GPIO group 0 */ - .long GINT1_IRQHandler /* GPIO group 1 */ - .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - .long UTICK0_IRQHandler /* Micro-tick Timer */ - .long MRT0_IRQHandler /* Multi-rate timer */ - .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ - .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ - .long SCT0_IRQHandler /* SCTimer/PWM */ - .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ - .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long ADC0_IRQHandler /* ADC0 */ - .long Reserved39_IRQHandler /* Reserved interrupt */ - .long ACMP_IRQHandler /* ACMP interrupts */ - .long Reserved41_IRQHandler /* Reserved interrupt */ - .long Reserved42_IRQHandler /* Reserved interrupt */ - .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ - .long USB0_IRQHandler /* USB device */ - .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ - .long Reserved46_IRQHandler /* Reserved interrupt */ - .long MAILBOX_IRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */ - .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ - .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ - .long OS_EVENT_IRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ - .long Reserved55_IRQHandler /* Reserved interrupt */ - .long Reserved56_IRQHandler /* Reserved interrupt */ - .long Reserved57_IRQHandler /* Reserved interrupt */ - .long SDIO_IRQHandler /* SD/MMC */ - .long Reserved59_IRQHandler /* Reserved interrupt */ - .long Reserved60_IRQHandler /* Reserved interrupt */ - .long Reserved61_IRQHandler /* Reserved interrupt */ - .long USB1_PHY_IRQHandler /* USB1_PHY */ - .long USB1_IRQHandler /* USB1 interrupt */ - .long USB1_NEEDCLK_IRQHandler /* USB1 activity */ - .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ - .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ - .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ - .long PLU_IRQHandler /* PLU interrupt */ - .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ - .long HASHCRYPT_IRQHandler /* HASHCRYPT interrupt */ - .long CASER_IRQHandler /* CASPER interrupt */ - .long PUF_IRQHandler /* PUF interrupt */ - .long PQ_IRQHandler /* PQ interrupt */ - .long DMA1_IRQHandler /* DMA1 interrupt */ - .long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ - .size __Vectors, . - __Vectors - - .text - .thumb - -/* Reset Handler */ - .thumb_func - .align 2 - .weak Reset_Handler - .type Reset_Handler, %function - -Reset_Handler: - cpsid i /* Mask interrupts */ - .equ VTOR, 0xE000ED08 - ldr r0, =VTOR - ldr r1, =__Vectors - str r1, [r0] - ldr r2, [r1] - msr msp, r2 - ldr R0, =Image$$ARM_LIB_STACK$$ZI$$Base - msr msplim, R0 - ldr r0,=SystemInit - blx r0 - cpsie i /* Unmask interrupts */ - ldr r0,=__main - bx r0 - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - .align 1 - .thumb_func - .weak WDT_BOD_IRQHandler - .type WDT_BOD_IRQHandler, %function -WDT_BOD_IRQHandler: - ldr r0,=WDT_BOD_DriverIRQHandler - bx r0 - .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler - - .align 1 - .thumb_func - .weak DMA0_IRQHandler - .type DMA0_IRQHandler, %function -DMA0_IRQHandler: - ldr r0,=DMA0_DriverIRQHandler - bx r0 - .size DMA0_IRQHandler, . - DMA0_IRQHandler - - .align 1 - .thumb_func - .weak GINT0_IRQHandler - .type GINT0_IRQHandler, %function -GINT0_IRQHandler: - ldr r0,=GINT0_DriverIRQHandler - bx r0 - .size GINT0_IRQHandler, . - GINT0_IRQHandler - - .align 1 - .thumb_func - .weak GINT1_IRQHandler - .type GINT1_IRQHandler, %function -GINT1_IRQHandler: - ldr r0,=GINT1_DriverIRQHandler - bx r0 - .size GINT1_IRQHandler, . - GINT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT0_IRQHandler - .type PIN_INT0_IRQHandler, %function -PIN_INT0_IRQHandler: - ldr r0,=PIN_INT0_DriverIRQHandler - bx r0 - .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT1_IRQHandler - .type PIN_INT1_IRQHandler, %function -PIN_INT1_IRQHandler: - ldr r0,=PIN_INT1_DriverIRQHandler - bx r0 - .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT2_IRQHandler - .type PIN_INT2_IRQHandler, %function -PIN_INT2_IRQHandler: - ldr r0,=PIN_INT2_DriverIRQHandler - bx r0 - .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT3_IRQHandler - .type PIN_INT3_IRQHandler, %function -PIN_INT3_IRQHandler: - ldr r0,=PIN_INT3_DriverIRQHandler - bx r0 - .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler - - .align 1 - .thumb_func - .weak UTICK0_IRQHandler - .type UTICK0_IRQHandler, %function -UTICK0_IRQHandler: - ldr r0,=UTICK0_DriverIRQHandler - bx r0 - .size UTICK0_IRQHandler, . - UTICK0_IRQHandler - - .align 1 - .thumb_func - .weak MRT0_IRQHandler - .type MRT0_IRQHandler, %function -MRT0_IRQHandler: - ldr r0,=MRT0_DriverIRQHandler - bx r0 - .size MRT0_IRQHandler, . - MRT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER0_IRQHandler - .type CTIMER0_IRQHandler, %function -CTIMER0_IRQHandler: - ldr r0,=CTIMER0_DriverIRQHandler - bx r0 - .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER1_IRQHandler - .type CTIMER1_IRQHandler, %function -CTIMER1_IRQHandler: - ldr r0,=CTIMER1_DriverIRQHandler - bx r0 - .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler - - .align 1 - .thumb_func - .weak SCT0_IRQHandler - .type SCT0_IRQHandler, %function -SCT0_IRQHandler: - ldr r0,=SCT0_DriverIRQHandler - bx r0 - .size SCT0_IRQHandler, . - SCT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER3_IRQHandler - .type CTIMER3_IRQHandler, %function -CTIMER3_IRQHandler: - ldr r0,=CTIMER3_DriverIRQHandler - bx r0 - .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM0_IRQHandler - .type FLEXCOMM0_IRQHandler, %function -FLEXCOMM0_IRQHandler: - ldr r0,=FLEXCOMM0_DriverIRQHandler - bx r0 - .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM1_IRQHandler - .type FLEXCOMM1_IRQHandler, %function -FLEXCOMM1_IRQHandler: - ldr r0,=FLEXCOMM1_DriverIRQHandler - bx r0 - .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM2_IRQHandler - .type FLEXCOMM2_IRQHandler, %function -FLEXCOMM2_IRQHandler: - ldr r0,=FLEXCOMM2_DriverIRQHandler - bx r0 - .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM3_IRQHandler - .type FLEXCOMM3_IRQHandler, %function -FLEXCOMM3_IRQHandler: - ldr r0,=FLEXCOMM3_DriverIRQHandler - bx r0 - .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM4_IRQHandler - .type FLEXCOMM4_IRQHandler, %function -FLEXCOMM4_IRQHandler: - ldr r0,=FLEXCOMM4_DriverIRQHandler - bx r0 - .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM5_IRQHandler - .type FLEXCOMM5_IRQHandler, %function -FLEXCOMM5_IRQHandler: - ldr r0,=FLEXCOMM5_DriverIRQHandler - bx r0 - .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM6_IRQHandler - .type FLEXCOMM6_IRQHandler, %function -FLEXCOMM6_IRQHandler: - ldr r0,=FLEXCOMM6_DriverIRQHandler - bx r0 - .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM7_IRQHandler - .type FLEXCOMM7_IRQHandler, %function -FLEXCOMM7_IRQHandler: - ldr r0,=FLEXCOMM7_DriverIRQHandler - bx r0 - .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_IRQHandler - .type ADC0_IRQHandler, %function -ADC0_IRQHandler: - ldr r0,=ADC0_DriverIRQHandler - bx r0 - .size ADC0_IRQHandler, . - ADC0_IRQHandler - - .align 1 - .thumb_func - .weak Reserved39_IRQHandler - .type Reserved39_IRQHandler, %function -Reserved39_IRQHandler: - ldr r0,=Reserved39_DriverIRQHandler - bx r0 - .size Reserved39_IRQHandler, . - Reserved39_IRQHandler - - .align 1 - .thumb_func - .weak ACMP_IRQHandler - .type ACMP_IRQHandler, %function -ACMP_IRQHandler: - ldr r0,=ACMP_DriverIRQHandler - bx r0 - .size ACMP_IRQHandler, . - ACMP_IRQHandler - - .align 1 - .thumb_func - .weak Reserved41_IRQHandler - .type Reserved41_IRQHandler, %function -Reserved41_IRQHandler: - ldr r0,=Reserved41_DriverIRQHandler - bx r0 - .size Reserved41_IRQHandler, . - Reserved41_IRQHandler - - .align 1 - .thumb_func - .weak Reserved42_IRQHandler - .type Reserved42_IRQHandler, %function -Reserved42_IRQHandler: - ldr r0,=Reserved42_DriverIRQHandler - bx r0 - .size Reserved42_IRQHandler, . - Reserved42_IRQHandler - - .align 1 - .thumb_func - .weak USB0_NEEDCLK_IRQHandler - .type USB0_NEEDCLK_IRQHandler, %function -USB0_NEEDCLK_IRQHandler: - ldr r0,=USB0_NEEDCLK_DriverIRQHandler - bx r0 - .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak USB0_IRQHandler - .type USB0_IRQHandler, %function -USB0_IRQHandler: - ldr r0,=USB0_DriverIRQHandler - bx r0 - .size USB0_IRQHandler, . - USB0_IRQHandler - - .align 1 - .thumb_func - .weak RTC_IRQHandler - .type RTC_IRQHandler, %function -RTC_IRQHandler: - ldr r0,=RTC_DriverIRQHandler - bx r0 - .size RTC_IRQHandler, . - RTC_IRQHandler - - .align 1 - .thumb_func - .weak Reserved46_IRQHandler - .type Reserved46_IRQHandler, %function -Reserved46_IRQHandler: - ldr r0,=Reserved46_DriverIRQHandler - bx r0 - .size Reserved46_IRQHandler, . - Reserved46_IRQHandler - - .align 1 - .thumb_func - .weak MAILBOX_IRQHandler - .type MAILBOX_IRQHandler, %function -MAILBOX_IRQHandler: - ldr r0,=MAILBOX_DriverIRQHandler - bx r0 - .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT4_IRQHandler - .type PIN_INT4_IRQHandler, %function -PIN_INT4_IRQHandler: - ldr r0,=PIN_INT4_DriverIRQHandler - bx r0 - .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT5_IRQHandler - .type PIN_INT5_IRQHandler, %function -PIN_INT5_IRQHandler: - ldr r0,=PIN_INT5_DriverIRQHandler - bx r0 - .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT6_IRQHandler - .type PIN_INT6_IRQHandler, %function -PIN_INT6_IRQHandler: - ldr r0,=PIN_INT6_DriverIRQHandler - bx r0 - .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT7_IRQHandler - .type PIN_INT7_IRQHandler, %function -PIN_INT7_IRQHandler: - ldr r0,=PIN_INT7_DriverIRQHandler - bx r0 - .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER2_IRQHandler - .type CTIMER2_IRQHandler, %function -CTIMER2_IRQHandler: - ldr r0,=CTIMER2_DriverIRQHandler - bx r0 - .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER4_IRQHandler - .type CTIMER4_IRQHandler, %function -CTIMER4_IRQHandler: - ldr r0,=CTIMER4_DriverIRQHandler - bx r0 - .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler - - .align 1 - .thumb_func - .weak OS_EVENT_IRQHandler - .type OS_EVENT_IRQHandler, %function -OS_EVENT_IRQHandler: - ldr r0,=OS_EVENT_DriverIRQHandler - bx r0 - .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler - - .align 1 - .thumb_func - .weak Reserved55_IRQHandler - .type Reserved55_IRQHandler, %function -Reserved55_IRQHandler: - ldr r0,=Reserved55_DriverIRQHandler - bx r0 - .size Reserved55_IRQHandler, . - Reserved55_IRQHandler - - .align 1 - .thumb_func - .weak Reserved56_IRQHandler - .type Reserved56_IRQHandler, %function -Reserved56_IRQHandler: - ldr r0,=Reserved56_DriverIRQHandler - bx r0 - .size Reserved56_IRQHandler, . - Reserved56_IRQHandler - - .align 1 - .thumb_func - .weak Reserved57_IRQHandler - .type Reserved57_IRQHandler, %function -Reserved57_IRQHandler: - ldr r0,=Reserved57_DriverIRQHandler - bx r0 - .size Reserved57_IRQHandler, . - Reserved57_IRQHandler - - .align 1 - .thumb_func - .weak SDIO_IRQHandler - .type SDIO_IRQHandler, %function -SDIO_IRQHandler: - ldr r0,=SDIO_DriverIRQHandler - bx r0 - .size SDIO_IRQHandler, . - SDIO_IRQHandler - - .align 1 - .thumb_func - .weak Reserved59_IRQHandler - .type Reserved59_IRQHandler, %function -Reserved59_IRQHandler: - ldr r0,=Reserved59_DriverIRQHandler - bx r0 - .size Reserved59_IRQHandler, . - Reserved59_IRQHandler - - .align 1 - .thumb_func - .weak Reserved60_IRQHandler - .type Reserved60_IRQHandler, %function -Reserved60_IRQHandler: - ldr r0,=Reserved60_DriverIRQHandler - bx r0 - .size Reserved60_IRQHandler, . - Reserved60_IRQHandler - - .align 1 - .thumb_func - .weak Reserved61_IRQHandler - .type Reserved61_IRQHandler, %function -Reserved61_IRQHandler: - ldr r0,=Reserved61_DriverIRQHandler - bx r0 - .size Reserved61_IRQHandler, . - Reserved61_IRQHandler - - .align 1 - .thumb_func - .weak USB1_PHY_IRQHandler - .type USB1_PHY_IRQHandler, %function -USB1_PHY_IRQHandler: - ldr r0,=USB1_PHY_DriverIRQHandler - bx r0 - .size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler - - .align 1 - .thumb_func - .weak USB1_IRQHandler - .type USB1_IRQHandler, %function -USB1_IRQHandler: - ldr r0,=USB1_DriverIRQHandler - bx r0 - .size USB1_IRQHandler, . - USB1_IRQHandler - - .align 1 - .thumb_func - .weak USB1_NEEDCLK_IRQHandler - .type USB1_NEEDCLK_IRQHandler, %function -USB1_NEEDCLK_IRQHandler: - ldr r0,=USB1_NEEDCLK_DriverIRQHandler - bx r0 - .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak SEC_HYPERVISOR_CALL_IRQHandler - .type SEC_HYPERVISOR_CALL_IRQHandler, %function -SEC_HYPERVISOR_CALL_IRQHandler: - ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler - bx r0 - .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ0_IRQHandler - .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function -SEC_GPIO_INT0_IRQ0_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ1_IRQHandler - .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function -SEC_GPIO_INT0_IRQ1_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak PLU_IRQHandler - .type PLU_IRQHandler, %function -PLU_IRQHandler: - ldr r0,=PLU_DriverIRQHandler - bx r0 - .size PLU_IRQHandler, . - PLU_IRQHandler - - .align 1 - .thumb_func - .weak SEC_VIO_IRQHandler - .type SEC_VIO_IRQHandler, %function -SEC_VIO_IRQHandler: - ldr r0,=SEC_VIO_DriverIRQHandler - bx r0 - .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler - - .align 1 - .thumb_func - .weak HASHCRYPT_IRQHandler - .type HASHCRYPT_IRQHandler, %function -HASHCRYPT_IRQHandler: - ldr r0,=HASHCRYPT_DriverIRQHandler - bx r0 - .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler - - .align 1 - .thumb_func - .weak CASER_IRQHandler - .type CASER_IRQHandler, %function -CASER_IRQHandler: - ldr r0,=CASER_DriverIRQHandler - bx r0 - .size CASER_IRQHandler, . - CASER_IRQHandler - - .align 1 - .thumb_func - .weak PUF_IRQHandler - .type PUF_IRQHandler, %function -PUF_IRQHandler: - ldr r0,=PUF_DriverIRQHandler - bx r0 - .size PUF_IRQHandler, . - PUF_IRQHandler - - .align 1 - .thumb_func - .weak PQ_IRQHandler - .type PQ_IRQHandler, %function -PQ_IRQHandler: - ldr r0,=PQ_DriverIRQHandler - bx r0 - .size PQ_IRQHandler, . - PQ_IRQHandler - - .align 1 - .thumb_func - .weak DMA1_IRQHandler - .type DMA1_IRQHandler, %function -DMA1_IRQHandler: - ldr r0,=DMA1_DriverIRQHandler - bx r0 - .size DMA1_IRQHandler, . - DMA1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM8_IRQHandler - .type FLEXCOMM8_IRQHandler, %function -FLEXCOMM8_IRQHandler: - ldr r0,=FLEXCOMM8_DriverIRQHandler - bx r0 - .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm -/* Exception Handlers */ - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SecureFault_Handler - def_irq_handler DebugMon_Handler - def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ - def_irq_handler DMA0_DriverIRQHandler /* DMA0 controller */ - def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */ - def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */ - def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */ - def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */ - def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */ - def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */ - def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */ - def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */ - def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler ADC0_DriverIRQHandler /* ADC0 */ - def_irq_handler Reserved39_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler ACMP_DriverIRQHandler /* ACMP interrupts */ - def_irq_handler Reserved41_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved42_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */ - def_irq_handler USB0_DriverIRQHandler /* USB device */ - def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */ - def_irq_handler Reserved46_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler MAILBOX_DriverIRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */ - def_irq_handler PIN_INT4_DriverIRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - def_irq_handler PIN_INT5_DriverIRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - def_irq_handler PIN_INT6_DriverIRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - def_irq_handler PIN_INT7_DriverIRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - def_irq_handler CTIMER2_DriverIRQHandler /* Standard counter/timer CTIMER2 */ - def_irq_handler CTIMER4_DriverIRQHandler /* Standard counter/timer CTIMER4 */ - def_irq_handler OS_EVENT_DriverIRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ - def_irq_handler Reserved55_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved56_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved57_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler SDIO_DriverIRQHandler /* SD/MMC */ - def_irq_handler Reserved59_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved60_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved61_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler USB1_PHY_DriverIRQHandler /* USB1_PHY */ - def_irq_handler USB1_DriverIRQHandler /* USB1 interrupt */ - def_irq_handler USB1_NEEDCLK_DriverIRQHandler /* USB1 activity */ - def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler /* SEC_HYPERVISOR_CALL interrupt */ - def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ - def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ - def_irq_handler PLU_DriverIRQHandler /* PLU interrupt */ - def_irq_handler SEC_VIO_DriverIRQHandler /* SEC_VIO interrupt */ - def_irq_handler HASHCRYPT_DriverIRQHandler /* HASHCRYPT interrupt */ - def_irq_handler CASER_DriverIRQHandler /* CASPER interrupt */ - def_irq_handler PUF_DriverIRQHandler /* PUF interrupt */ - def_irq_handler PQ_DriverIRQHandler /* PQ interrupt */ - def_irq_handler DMA1_DriverIRQHandler /* DMA1 interrupt */ - def_irq_handler FLEXCOMM8_DriverIRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ - - .end diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core1.s b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core1.s deleted file mode 100644 index 116a16b56ab..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core1.s +++ /dev/null @@ -1,795 +0,0 @@ -/* --------------------------------------------------------------------------------------- - * @file: startup_LPC55S69_cm33_core1.s - * @purpose: CMSIS Cortex-M33 Core Device Startup File for the LPC55S69_cm33_core1 - * @version: 1.1 - * @date: 2019-5-16 - * ---------------------------------------------------------------------------------------*/ -/* - * Copyright 1997-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - - .syntax unified - .arch armv8-m.main - .eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */ - - .section .isr_vector, "a" - .align 2 - .globl __Vectors - -__Vectors: - .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long MemManage_Handler /* MPU Fault Handler*/ - .long BusFault_Handler /* Bus Fault Handler*/ - .long UsageFault_Handler /* Usage Fault Handler*/ - .long SecureFault_Handler /* Secure Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long DebugMon_Handler /* Debug Monitor Handler*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts*/ - .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ - .long DMA0_IRQHandler /* DMA0 controller */ - .long GINT0_IRQHandler /* GPIO group 0 */ - .long GINT1_IRQHandler /* GPIO group 1 */ - .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - .long UTICK0_IRQHandler /* Micro-tick Timer */ - .long MRT0_IRQHandler /* Multi-rate timer */ - .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ - .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ - .long SCT0_IRQHandler /* SCTimer/PWM */ - .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ - .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long ADC0_IRQHandler /* ADC0 */ - .long Reserved39_IRQHandler /* Reserved interrupt */ - .long ACMP_IRQHandler /* ACMP interrupts */ - .long Reserved41_IRQHandler /* Reserved interrupt */ - .long Reserved42_IRQHandler /* Reserved interrupt */ - .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ - .long USB0_IRQHandler /* USB device */ - .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ - .long Reserved46_IRQHandler /* Reserved interrupt */ - .long MAILBOX_IRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */ - .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ - .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ - .long OS_EVENT_IRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ - .long Reserved55_IRQHandler /* Reserved interrupt */ - .long Reserved56_IRQHandler /* Reserved interrupt */ - .long Reserved57_IRQHandler /* Reserved interrupt */ - .long SDIO_IRQHandler /* SD/MMC */ - .long Reserved59_IRQHandler /* Reserved interrupt */ - .long Reserved60_IRQHandler /* Reserved interrupt */ - .long Reserved61_IRQHandler /* Reserved interrupt */ - .long USB1_PHY_IRQHandler /* USB1_PHY */ - .long USB1_IRQHandler /* USB1 interrupt */ - .long USB1_NEEDCLK_IRQHandler /* USB1 activity */ - .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ - .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ - .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ - .long PLU_IRQHandler /* PLU interrupt */ - .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ - .long HASHCRYPT_IRQHandler /* HASHCRYPT interrupt */ - .long CASER_IRQHandler /* CASPER interrupt */ - .long PUF_IRQHandler /* PUF interrupt */ - .long PQ_IRQHandler /* PQ interrupt */ - .long DMA1_IRQHandler /* DMA1 interrupt */ - .long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ - .size __Vectors, . - __Vectors - - .text - .thumb - -/* Reset Handler */ - .thumb_func - .align 2 - .weak Reset_Handler - .type Reset_Handler, %function - -Reset_Handler: - cpsid i /* mask interrupts */ - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Base - msr msplim, r0 - ldr r0,=SystemInit - blx r0 - cpsie i /* Unmask interrupts */ - ldr r0,=__main - bx r0 - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - .align 1 - .thumb_func - .weak WDT_BOD_IRQHandler - .type WDT_BOD_IRQHandler, %function -WDT_BOD_IRQHandler: - ldr r0,=WDT_BOD_DriverIRQHandler - bx r0 - .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler - - .align 1 - .thumb_func - .weak DMA0_IRQHandler - .type DMA0_IRQHandler, %function -DMA0_IRQHandler: - ldr r0,=DMA0_DriverIRQHandler - bx r0 - .size DMA0_IRQHandler, . - DMA0_IRQHandler - - .align 1 - .thumb_func - .weak GINT0_IRQHandler - .type GINT0_IRQHandler, %function -GINT0_IRQHandler: - ldr r0,=GINT0_DriverIRQHandler - bx r0 - .size GINT0_IRQHandler, . - GINT0_IRQHandler - - .align 1 - .thumb_func - .weak GINT1_IRQHandler - .type GINT1_IRQHandler, %function -GINT1_IRQHandler: - ldr r0,=GINT1_DriverIRQHandler - bx r0 - .size GINT1_IRQHandler, . - GINT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT0_IRQHandler - .type PIN_INT0_IRQHandler, %function -PIN_INT0_IRQHandler: - ldr r0,=PIN_INT0_DriverIRQHandler - bx r0 - .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT1_IRQHandler - .type PIN_INT1_IRQHandler, %function -PIN_INT1_IRQHandler: - ldr r0,=PIN_INT1_DriverIRQHandler - bx r0 - .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT2_IRQHandler - .type PIN_INT2_IRQHandler, %function -PIN_INT2_IRQHandler: - ldr r0,=PIN_INT2_DriverIRQHandler - bx r0 - .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT3_IRQHandler - .type PIN_INT3_IRQHandler, %function -PIN_INT3_IRQHandler: - ldr r0,=PIN_INT3_DriverIRQHandler - bx r0 - .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler - - .align 1 - .thumb_func - .weak UTICK0_IRQHandler - .type UTICK0_IRQHandler, %function -UTICK0_IRQHandler: - ldr r0,=UTICK0_DriverIRQHandler - bx r0 - .size UTICK0_IRQHandler, . - UTICK0_IRQHandler - - .align 1 - .thumb_func - .weak MRT0_IRQHandler - .type MRT0_IRQHandler, %function -MRT0_IRQHandler: - ldr r0,=MRT0_DriverIRQHandler - bx r0 - .size MRT0_IRQHandler, . - MRT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER0_IRQHandler - .type CTIMER0_IRQHandler, %function -CTIMER0_IRQHandler: - ldr r0,=CTIMER0_DriverIRQHandler - bx r0 - .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER1_IRQHandler - .type CTIMER1_IRQHandler, %function -CTIMER1_IRQHandler: - ldr r0,=CTIMER1_DriverIRQHandler - bx r0 - .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler - - .align 1 - .thumb_func - .weak SCT0_IRQHandler - .type SCT0_IRQHandler, %function -SCT0_IRQHandler: - ldr r0,=SCT0_DriverIRQHandler - bx r0 - .size SCT0_IRQHandler, . - SCT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER3_IRQHandler - .type CTIMER3_IRQHandler, %function -CTIMER3_IRQHandler: - ldr r0,=CTIMER3_DriverIRQHandler - bx r0 - .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM0_IRQHandler - .type FLEXCOMM0_IRQHandler, %function -FLEXCOMM0_IRQHandler: - ldr r0,=FLEXCOMM0_DriverIRQHandler - bx r0 - .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM1_IRQHandler - .type FLEXCOMM1_IRQHandler, %function -FLEXCOMM1_IRQHandler: - ldr r0,=FLEXCOMM1_DriverIRQHandler - bx r0 - .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM2_IRQHandler - .type FLEXCOMM2_IRQHandler, %function -FLEXCOMM2_IRQHandler: - ldr r0,=FLEXCOMM2_DriverIRQHandler - bx r0 - .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM3_IRQHandler - .type FLEXCOMM3_IRQHandler, %function -FLEXCOMM3_IRQHandler: - ldr r0,=FLEXCOMM3_DriverIRQHandler - bx r0 - .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM4_IRQHandler - .type FLEXCOMM4_IRQHandler, %function -FLEXCOMM4_IRQHandler: - ldr r0,=FLEXCOMM4_DriverIRQHandler - bx r0 - .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM5_IRQHandler - .type FLEXCOMM5_IRQHandler, %function -FLEXCOMM5_IRQHandler: - ldr r0,=FLEXCOMM5_DriverIRQHandler - bx r0 - .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM6_IRQHandler - .type FLEXCOMM6_IRQHandler, %function -FLEXCOMM6_IRQHandler: - ldr r0,=FLEXCOMM6_DriverIRQHandler - bx r0 - .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM7_IRQHandler - .type FLEXCOMM7_IRQHandler, %function -FLEXCOMM7_IRQHandler: - ldr r0,=FLEXCOMM7_DriverIRQHandler - bx r0 - .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_IRQHandler - .type ADC0_IRQHandler, %function -ADC0_IRQHandler: - ldr r0,=ADC0_DriverIRQHandler - bx r0 - .size ADC0_IRQHandler, . - ADC0_IRQHandler - - .align 1 - .thumb_func - .weak Reserved39_IRQHandler - .type Reserved39_IRQHandler, %function -Reserved39_IRQHandler: - ldr r0,=Reserved39_DriverIRQHandler - bx r0 - .size Reserved39_IRQHandler, . - Reserved39_IRQHandler - - .align 1 - .thumb_func - .weak ACMP_IRQHandler - .type ACMP_IRQHandler, %function -ACMP_IRQHandler: - ldr r0,=ACMP_DriverIRQHandler - bx r0 - .size ACMP_IRQHandler, . - ACMP_IRQHandler - - .align 1 - .thumb_func - .weak Reserved41_IRQHandler - .type Reserved41_IRQHandler, %function -Reserved41_IRQHandler: - ldr r0,=Reserved41_DriverIRQHandler - bx r0 - .size Reserved41_IRQHandler, . - Reserved41_IRQHandler - - .align 1 - .thumb_func - .weak Reserved42_IRQHandler - .type Reserved42_IRQHandler, %function -Reserved42_IRQHandler: - ldr r0,=Reserved42_DriverIRQHandler - bx r0 - .size Reserved42_IRQHandler, . - Reserved42_IRQHandler - - .align 1 - .thumb_func - .weak USB0_NEEDCLK_IRQHandler - .type USB0_NEEDCLK_IRQHandler, %function -USB0_NEEDCLK_IRQHandler: - ldr r0,=USB0_NEEDCLK_DriverIRQHandler - bx r0 - .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak USB0_IRQHandler - .type USB0_IRQHandler, %function -USB0_IRQHandler: - ldr r0,=USB0_DriverIRQHandler - bx r0 - .size USB0_IRQHandler, . - USB0_IRQHandler - - .align 1 - .thumb_func - .weak RTC_IRQHandler - .type RTC_IRQHandler, %function -RTC_IRQHandler: - ldr r0,=RTC_DriverIRQHandler - bx r0 - .size RTC_IRQHandler, . - RTC_IRQHandler - - .align 1 - .thumb_func - .weak Reserved46_IRQHandler - .type Reserved46_IRQHandler, %function -Reserved46_IRQHandler: - ldr r0,=Reserved46_DriverIRQHandler - bx r0 - .size Reserved46_IRQHandler, . - Reserved46_IRQHandler - - .align 1 - .thumb_func - .weak MAILBOX_IRQHandler - .type MAILBOX_IRQHandler, %function -MAILBOX_IRQHandler: - ldr r0,=MAILBOX_DriverIRQHandler - bx r0 - .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT4_IRQHandler - .type PIN_INT4_IRQHandler, %function -PIN_INT4_IRQHandler: - ldr r0,=PIN_INT4_DriverIRQHandler - bx r0 - .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT5_IRQHandler - .type PIN_INT5_IRQHandler, %function -PIN_INT5_IRQHandler: - ldr r0,=PIN_INT5_DriverIRQHandler - bx r0 - .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT6_IRQHandler - .type PIN_INT6_IRQHandler, %function -PIN_INT6_IRQHandler: - ldr r0,=PIN_INT6_DriverIRQHandler - bx r0 - .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT7_IRQHandler - .type PIN_INT7_IRQHandler, %function -PIN_INT7_IRQHandler: - ldr r0,=PIN_INT7_DriverIRQHandler - bx r0 - .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER2_IRQHandler - .type CTIMER2_IRQHandler, %function -CTIMER2_IRQHandler: - ldr r0,=CTIMER2_DriverIRQHandler - bx r0 - .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER4_IRQHandler - .type CTIMER4_IRQHandler, %function -CTIMER4_IRQHandler: - ldr r0,=CTIMER4_DriverIRQHandler - bx r0 - .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler - - .align 1 - .thumb_func - .weak OS_EVENT_IRQHandler - .type OS_EVENT_IRQHandler, %function -OS_EVENT_IRQHandler: - ldr r0,=OS_EVENT_DriverIRQHandler - bx r0 - .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler - - .align 1 - .thumb_func - .weak Reserved55_IRQHandler - .type Reserved55_IRQHandler, %function -Reserved55_IRQHandler: - ldr r0,=Reserved55_DriverIRQHandler - bx r0 - .size Reserved55_IRQHandler, . - Reserved55_IRQHandler - - .align 1 - .thumb_func - .weak Reserved56_IRQHandler - .type Reserved56_IRQHandler, %function -Reserved56_IRQHandler: - ldr r0,=Reserved56_DriverIRQHandler - bx r0 - .size Reserved56_IRQHandler, . - Reserved56_IRQHandler - - .align 1 - .thumb_func - .weak Reserved57_IRQHandler - .type Reserved57_IRQHandler, %function -Reserved57_IRQHandler: - ldr r0,=Reserved57_DriverIRQHandler - bx r0 - .size Reserved57_IRQHandler, . - Reserved57_IRQHandler - - .align 1 - .thumb_func - .weak SDIO_IRQHandler - .type SDIO_IRQHandler, %function -SDIO_IRQHandler: - ldr r0,=SDIO_DriverIRQHandler - bx r0 - .size SDIO_IRQHandler, . - SDIO_IRQHandler - - .align 1 - .thumb_func - .weak Reserved59_IRQHandler - .type Reserved59_IRQHandler, %function -Reserved59_IRQHandler: - ldr r0,=Reserved59_DriverIRQHandler - bx r0 - .size Reserved59_IRQHandler, . - Reserved59_IRQHandler - - .align 1 - .thumb_func - .weak Reserved60_IRQHandler - .type Reserved60_IRQHandler, %function -Reserved60_IRQHandler: - ldr r0,=Reserved60_DriverIRQHandler - bx r0 - .size Reserved60_IRQHandler, . - Reserved60_IRQHandler - - .align 1 - .thumb_func - .weak Reserved61_IRQHandler - .type Reserved61_IRQHandler, %function -Reserved61_IRQHandler: - ldr r0,=Reserved61_DriverIRQHandler - bx r0 - .size Reserved61_IRQHandler, . - Reserved61_IRQHandler - - .align 1 - .thumb_func - .weak USB1_PHY_IRQHandler - .type USB1_PHY_IRQHandler, %function -USB1_PHY_IRQHandler: - ldr r0,=USB1_PHY_DriverIRQHandler - bx r0 - .size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler - - .align 1 - .thumb_func - .weak USB1_IRQHandler - .type USB1_IRQHandler, %function -USB1_IRQHandler: - ldr r0,=USB1_DriverIRQHandler - bx r0 - .size USB1_IRQHandler, . - USB1_IRQHandler - - .align 1 - .thumb_func - .weak USB1_NEEDCLK_IRQHandler - .type USB1_NEEDCLK_IRQHandler, %function -USB1_NEEDCLK_IRQHandler: - ldr r0,=USB1_NEEDCLK_DriverIRQHandler - bx r0 - .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak SEC_HYPERVISOR_CALL_IRQHandler - .type SEC_HYPERVISOR_CALL_IRQHandler, %function -SEC_HYPERVISOR_CALL_IRQHandler: - ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler - bx r0 - .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ0_IRQHandler - .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function -SEC_GPIO_INT0_IRQ0_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ1_IRQHandler - .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function -SEC_GPIO_INT0_IRQ1_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak PLU_IRQHandler - .type PLU_IRQHandler, %function -PLU_IRQHandler: - ldr r0,=PLU_DriverIRQHandler - bx r0 - .size PLU_IRQHandler, . - PLU_IRQHandler - - .align 1 - .thumb_func - .weak SEC_VIO_IRQHandler - .type SEC_VIO_IRQHandler, %function -SEC_VIO_IRQHandler: - ldr r0,=SEC_VIO_DriverIRQHandler - bx r0 - .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler - - .align 1 - .thumb_func - .weak HASHCRYPT_IRQHandler - .type HASHCRYPT_IRQHandler, %function -HASHCRYPT_IRQHandler: - ldr r0,=HASHCRYPT_DriverIRQHandler - bx r0 - .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler - - .align 1 - .thumb_func - .weak CASER_IRQHandler - .type CASER_IRQHandler, %function -CASER_IRQHandler: - ldr r0,=CASER_DriverIRQHandler - bx r0 - .size CASER_IRQHandler, . - CASER_IRQHandler - - .align 1 - .thumb_func - .weak PUF_IRQHandler - .type PUF_IRQHandler, %function -PUF_IRQHandler: - ldr r0,=PUF_DriverIRQHandler - bx r0 - .size PUF_IRQHandler, . - PUF_IRQHandler - - .align 1 - .thumb_func - .weak PQ_IRQHandler - .type PQ_IRQHandler, %function -PQ_IRQHandler: - ldr r0,=PQ_DriverIRQHandler - bx r0 - .size PQ_IRQHandler, . - PQ_IRQHandler - - .align 1 - .thumb_func - .weak DMA1_IRQHandler - .type DMA1_IRQHandler, %function -DMA1_IRQHandler: - ldr r0,=DMA1_DriverIRQHandler - bx r0 - .size DMA1_IRQHandler, . - DMA1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM8_IRQHandler - .type FLEXCOMM8_IRQHandler, %function -FLEXCOMM8_IRQHandler: - ldr r0,=FLEXCOMM8_DriverIRQHandler - bx r0 - .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm -/* Exception Handlers */ - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SecureFault_Handler - def_irq_handler DebugMon_Handler - def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ - def_irq_handler DMA0_DriverIRQHandler /* DMA0 controller */ - def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */ - def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */ - def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */ - def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */ - def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */ - def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */ - def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */ - def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */ - def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - def_irq_handler ADC0_DriverIRQHandler /* ADC0 */ - def_irq_handler Reserved39_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler ACMP_DriverIRQHandler /* ACMP interrupts */ - def_irq_handler Reserved41_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved42_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */ - def_irq_handler USB0_DriverIRQHandler /* USB device */ - def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */ - def_irq_handler Reserved46_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler MAILBOX_DriverIRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */ - def_irq_handler PIN_INT4_DriverIRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - def_irq_handler PIN_INT5_DriverIRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - def_irq_handler PIN_INT6_DriverIRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - def_irq_handler PIN_INT7_DriverIRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - def_irq_handler CTIMER2_DriverIRQHandler /* Standard counter/timer CTIMER2 */ - def_irq_handler CTIMER4_DriverIRQHandler /* Standard counter/timer CTIMER4 */ - def_irq_handler OS_EVENT_DriverIRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ - def_irq_handler Reserved55_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved56_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved57_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler SDIO_DriverIRQHandler /* SD/MMC */ - def_irq_handler Reserved59_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved60_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved61_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler USB1_PHY_DriverIRQHandler /* USB1_PHY */ - def_irq_handler USB1_DriverIRQHandler /* USB1 interrupt */ - def_irq_handler USB1_NEEDCLK_DriverIRQHandler /* USB1 activity */ - def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler /* SEC_HYPERVISOR_CALL interrupt */ - def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ - def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ - def_irq_handler PLU_DriverIRQHandler /* PLU interrupt */ - def_irq_handler SEC_VIO_DriverIRQHandler /* SEC_VIO interrupt */ - def_irq_handler HASHCRYPT_DriverIRQHandler /* HASHCRYPT interrupt */ - def_irq_handler CASER_DriverIRQHandler /* CASPER interrupt */ - def_irq_handler PUF_DriverIRQHandler /* PUF interrupt */ - def_irq_handler PQ_DriverIRQHandler /* PQ interrupt */ - def_irq_handler DMA1_DriverIRQHandler /* DMA1 interrupt */ - def_irq_handler FLEXCOMM8_DriverIRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ - - .end diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.c deleted file mode 100644 index 68175b880a3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright 2018-2021, NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_anactrl.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.anactrl" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for ANACTRL module. - * - * @param base ANACTRL peripheral base address - */ -static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to ANACTRL bases for each instance. */ -static ANACTRL_Type *const s_anactrlBases[] = ANACTRL_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to ANACTRL clocks for each instance. */ -static const clock_ip_name_t s_anactrlClocks[] = ANALOGCTRL_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! - * brief Get the ANACTRL instance from peripheral base address. - * - * param base ANACTRL peripheral base address. - * return ANACTRL instance. - */ -static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_anactrlBases); instance++) - { - if (s_anactrlBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_anactrlBases)); - - return instance; -} - -/*! - * brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function. - * - * param base ANACTRL peripheral base address. - */ -void ANACTRL_Init(ANACTRL_Type *base) -{ - assert(NULL != base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock for ANACTRL instance. */ - CLOCK_EnableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function. - * - * param base ANACTRL peripheral base address. - */ -void ANACTRL_Deinit(ANACTRL_Type *base) -{ - assert(NULL != base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock for ANACTRL instance. */ - CLOCK_DisableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock output - * and enable/disable 96MHZ clock output. - * - * param base ANACTRL peripheral base address. - * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure. - */ -void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32 = base->FRO192M_CTRL; - - tmp32 &= ~(ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK); - - if (config->enable12MHzClk) - { - tmp32 |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK; - } - if (config->enable96MHzClk) - { - tmp32 |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; - } - - base->FRO192M_CTRL |= tmp32; -} - -/*! - * brief Gets the default configuration of FRO192M. - * The default values are: - * code - config->enable12MHzClk = true; - config->enable96MHzClk = false; - endcode - * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure. - */ -void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enable12MHzClk = true; - config->enable96MHzClk = false; -} - -/*! - * brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU - * system, and so on. - * - * param base ANACTRL peripheral base address. - * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure. - */ -void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32 = base->XO32M_CTRL; - - tmp32 &= ~(ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK | ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK); - - /* Set XO32M CTRL. */ -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) - tmp32 &= ~ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; - if (config->enablePllUsbOutput) - { - tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; - } -#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ - - if (config->enableACBufferBypass) - { - tmp32 |= ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; - } - - if (config->enableSysCLkOutput) - { - tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; - } - base->XO32M_CTRL = tmp32; - -#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) - if (config->enableADCOutput) - { - base->DUMMY_CTRL |= ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK; - } - else - { - base->DUMMY_CTRL &= ~ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK; - } -#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ -} - -/*! - * brief Gets the default configuration of XO32M. - * The default values are: - * code - config->enableSysCLkOutput = false; - config->enableACBufferBypass = false; - endcode - * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure. - */ -void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) - config->enablePllUsbOutput = false; -#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ - config->enableSysCLkOutput = false; - config->enableACBufferBypass = false; -#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) - config->enableADCOutput = true; -#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ -} - -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) -/*! - * brief Measures the frequency of the target clock source. - * - * This function measures target frequency according to a accurate reference frequency.The formula is: - * Ftarget = (CAPVAL * Freference) / ((1<= 2U); - - uint32_t targetClkFreq = 0U; - uint32_t capval = 0U; - - /* Init a measurement cycle. */ - base->FREQ_ME_CTRL = ANACTRL_FREQ_ME_CTRL_PROG_MASK + ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(scale); - while (ANACTRL_FREQ_ME_CTRL_PROG_MASK == (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_PROG_MASK)) - { - } - - /* Calculate the target clock frequency. */ - capval = (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK); - targetClkFreq = (capval * refClkFreq) / ((1UL << scale) - 1UL); - - return targetClkFreq; -} -#endif /* FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.h deleted file mode 100644 index 4ca845b5a9a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.h +++ /dev/null @@ -1,377 +0,0 @@ -/* - * Copyright 2018-2021, NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __FSL_ANACTRL_H__ -#define __FSL_ANACTRL_H__ - -#include "fsl_common.h" - -/*! - * @addtogroup anactrl - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief ANACTRL driver version. */ -#define FSL_ANACTRL_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*!< Version 2.3.0. */` - -/*! - * @brief ANACTRL interrupt flags - */ -enum _anactrl_interrupt_flags -{ -#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) - kANACTRL_BodVDDMainFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_MASK, /*!< BOD VDDMAIN Interrupt status - before Interrupt Enable. */ - kANACTRL_BodVDDMainInterruptFlag = - ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_MASK, /*!< BOD VDDMAIN Interrupt status - after Interrupt Enable. */ - kANACTRL_BodVDDMainPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_MASK, /*!< Current value of BOD VDDMAIN - power status output. */ -#else - kANACTRL_BodVbatFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK, /*!< BOD VBAT Interrupt status before - Interrupt Enable. */ - kANACTRL_BodVbatInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK, /*!< BOD VBAT Interrupt status - after Interrupt Enable. */ - kANACTRL_BodVbatPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK, /*!< Current value of BOD VBAT power - status output. */ -#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */ - kANACTRL_BodCoreFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK, /*!< BOD CORE Interrupt status before - Interrupt Enable. */ - kANACTRL_BodCoreInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK, /*!< BOD CORE Interrupt status - after Interrupt Enable. */ - kANACTRL_BodCorePowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK, /*!< Current value of BOD CORE power - status output. */ - kANACTRL_DcdcFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK, /*!< DCDC Interrupt status before - Interrupt Enable. */ - kANACTRL_DcdcInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK, /*!< DCDC Interrupt status after - Interrupt Enable. */ - kANACTRL_DcdcPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK, /*!< Current value of DCDC power - status output. */ -}; - -/*! - * @brief ANACTRL interrupt control - */ -enum _anactrl_interrupt -{ -#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) - kANACTRL_BodVDDMainInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_MASK, /*!< BOD VDDMAIN - interrupt control. */ -#else - kANACTRL_BodVbatInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK, /*!< BOD VBAT interrupt - control. */ -#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */ - kANACTRL_BodCoreInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK, /*!< BOD CORE interrupt - control. */ - kANACTRL_DcdcInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK, /*!< DCDC interrupt control. */ -}; - -/*! - * @brief ANACTRL status flags - */ -enum _anactrl_flags -{ - kANACTRL_FlashPowerDownFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK, /*!< Flash power-down status. */ - kANACTRL_FlashInitErrorFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK, /*!< Flash initialization - error status. */ -}; - -/*! - * @brief ANACTRL FRO192M and XO32M status flags - */ -enum _anactrl_osc_flags -{ - kANACTRL_OutputClkValidFlag = ANACTRL_FRO192M_STATUS_CLK_VALID_MASK, /*!< Output clock valid signal. */ - kANACTRL_CCOThresholdVoltageFlag = ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK, /*!< CCO threshold voltage detector - output (signal vcco_ok). */ - kANACTRL_XO32MOutputReadyFlag = ANACTRL_XO32M_STATUS_XO_READY_MASK << 16U, /*!< Indicates XO out - frequency statibilty. */ -}; - -/*! - * @brief Configuration for FRO192M - * - * This structure holds the configuration settings for the on-chip high-speed Free Running Oscillator. To initialize - * this structure to reasonable defaults, call the ANACTRL_GetDefaultFro192MConfig() function and pass a - * pointer to your config structure instance. - */ -typedef struct _anactrl_fro192M_config -{ - bool enable12MHzClk; /*!< Enable 12MHz clock. */ - bool enable96MHzClk; /*!< Enable 96MHz clock. */ -} anactrl_fro192M_config_t; - -/*! - * @brief Configuration for XO32M - * - * This structure holds the configuration settings for the 32 MHz crystal oscillator. To initialize this - * structure to reasonable defaults, call the ANACTRL_GetDefaultXo32MConfig() function and pass a - * pointer to your config structure instance. - */ -typedef struct _anactrl_xo32M_config -{ - bool enableACBufferBypass; /*!< Enable XO AC buffer bypass in pll and top level. */ -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) - bool enablePllUsbOutput; /*!< Enable XO 32 MHz output to USB HS PLL. */ -#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ - bool enableSysCLkOutput; /*!< Enable XO 32 MHz output to CPU system, SCT, and CLKOUT */ -#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ - FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) - bool enableADCOutput; /*!< Enable High speed crystal oscillator output to ADC. */ -#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ -} anactrl_xo32M_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function. - * - * @param base ANACTRL peripheral base address. - */ -void ANACTRL_Init(ANACTRL_Type *base); - -/*! - * @brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function. - * - * @param base ANACTRL peripheral base address. - */ -void ANACTRL_Deinit(ANACTRL_Type *base); -/* @} */ - -/*! - * @name Set oscillators - * @{ - */ - -/*! - * @brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock - * output and enable/disable 96MHZ clock output. - * - * @param base ANACTRL peripheral base address. - * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure. - */ -void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config); - -/*! - * @brief Gets the default configuration of FRO192M. - * The default values are: - * @code - config->enable12MHzClk = true; - config->enable96MHzClk = false; - @endcode - * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure. - */ -void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config); - -/*! - * @brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU - * system, and so on. - * - * @param base ANACTRL peripheral base address. - * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure. - */ -void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config); - -/*! - * @brief Gets the default configuration of XO32M. - * The default values are: - * @code - config->enableSysCLkOutput = false; - config->enableACBufferBypass = false; - @endcode - * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure. - */ -void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config); - -/* @} */ - -#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) -/*! - * @name Measure Frequency - * @{ - */ - -/*! - * @brief Measures the frequency of the target clock source. - * - * This function measures target frequency according to a accurate reference frequency.The formula is: - * Ftarget = (CAPVAL * Freference) / ((1<BOD_DCDC_INT_CTRL |= (0x15U & mask); -} - -/*! - * @brief Disables the ANACTRL interrupts. - * - * @param base ANACTRL peripheral base address. - * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration. - */ -static inline void ANACTRL_DisableInterrupts(ANACTRL_Type *base, uint32_t mask) -{ - base->BOD_DCDC_INT_CTRL &= ~(0x15U & mask); -} - -/*! - * @brief Clears the ANACTRL interrupts. - * - * @param base ANACTRL peripheral base address. - * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration. - */ -static inline void ANACTRL_ClearInterrupts(ANACTRL_Type *base, uint32_t mask) -{ - base->BOD_DCDC_INT_CTRL |= (uint32_t)(mask << 1UL); -} -/* @} */ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets ANACTRL status flags. - * - * This function gets Analog control status flags. The flags are returned as the logical - * OR value of the enumerators @ref _anactrl_flags. To check for a specific status, - * compare the return value with enumerators in the @ref _anactrl_flags. - * For example, to check whether the flash is in power down mode: - * @code - * if (kANACTRL_FlashPowerDownFlag & ANACTRL_ANACTRL_GetStatusFlags(ANACTRL)) - * { - * ... - * } - * @endcode - * - * @param base ANACTRL peripheral base address. - * @return ANACTRL status flags which are given in the enumerators in the @ref _anactrl_flags. - */ -static inline uint32_t ANACTRL_GetStatusFlags(ANACTRL_Type *base) -{ - return base->ANALOG_CTRL_STATUS; -} - -/*! - * @brief Gets ANACTRL oscillators status flags. - * - * This function gets Anactrl oscillators status flags. The flags are returned as the logical - * OR value of the enumerators @ref _anactrl_osc_flags. To check for a specific status, - * compare the return value with enumerators in the @ref _anactrl_osc_flags. - * For example, to check whether the FRO192M clock output is valid: - * @code - * if (kANACTRL_OutputClkValidFlag & ANACTRL_ANACTRL_GetOscStatusFlags(ANACTRL)) - * { - * ... - * } - * @endcode - * - * @param base ANACTRL peripheral base address. - * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags. - */ -static inline uint32_t ANACTRL_GetOscStatusFlags(ANACTRL_Type *base) -{ - return (base->FRO192M_STATUS & 0xFFU) | ((base->XO32M_STATUS & 0xFFU) << 16U); -} - -/*! - * @brief Gets ANACTRL interrupt status flags. - * - * This function gets Anactrl interrupt status flags. The flags are returned as the logical - * OR value of the enumerators @ref _anactrl_interrupt_flags. To check for a specific status, - * compare the return value with enumerators in the @ref _anactrl_interrupt_flags. - * For example, to check whether the VBAT voltage level is above the threshold: - * @code - * if (kANACTRL_BodVbatPowerFlag & ANACTRL_ANACTRL_GetInterruptStatusFlags(ANACTRL)) - * { - * ... - * } - * @endcode - * - * @param base ANACTRL peripheral base address. - * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags. - */ -static inline uint32_t ANACTRL_GetInterruptStatusFlags(ANACTRL_Type *base) -{ - return base->BOD_DCDC_INT_STATUS & 0x1FFU; -} -/* @} */ - -#if (defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) && (FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG == 1U)) -/*! - * @brief Aux_Bias Control Interfaces - * @{ - */ - -/*! - * @brief Enables/disabless 1V reference voltage buffer. - * - * @param base ANACTRL peripheral base address. - * @param enable Used to enable or disable 1V reference voltage buffer. - */ -static inline void ANACTRL_EnableVref1V(ANACTRL_Type *base, bool enable) -{ - if (enable) - { - base->AUX_BIAS |= ANACTRL_AUX_BIAS_VREF1VENABLE_MASK; - } - else - { - base->AUX_BIAS &= ~ANACTRL_AUX_BIAS_VREF1VENABLE_MASK; - } -} - -/* @} */ -#endif /* defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) */ - -#if defined(__cplusplus) -} -#endif - -/* @}*/ - -#endif /* __FSL_ANACTRL_H__ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_casper.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_casper.c deleted file mode 100644 index ed3770fa8ba..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_casper.c +++ /dev/null @@ -1,3433 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_casper.h" -#include /* ceil TODO check if really need it */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.casper" -#endif - -/* Recoding length for the secure scalar multiplication: - * Use n=256 and w=4 --> compute ciel(384/3) = 86 + 1 digits - * Use n=384 and w=4 --> compute ciel(384/3) = 128 + 1 digits - * Use n=521 and w=4 --> compute ciel(521/3) = 174 + 1 digits - */ - -/*!< Recoding length for the secure scalar multiplication */ -enum _casper_ecc_recode_len -{ - kCASPER_ECC_P256_recode_len = 87u, - kCASPER_ECC_P384_recode_len = 129u, - kCASPER_ECC_P521_recode_len = 175u, -}; - -enum _casper_ecc_N_bitlen -{ - kCASPER_ECC_P256_N_bitlen = 256u, - kCASPER_ECC_P384_N_bitlen = 384u, - kCASPER_ECC_P521_N_bitlen = 576u, -}; - -enum _casper_ecc_N_wordlen -{ - kCASPER_ECC_P256_wordlen = 256U / 32U, - kCASPER_ECC_P384_wordlen = 384u / 32U, - kCASPER_ECC_P521_wordlen = 576u / 32U, -}; - -#if defined(__GNUC__) -/* Enforce O1 optimize level, specifically to remove strict-aliasing option. - (-fno-strict-aliasing is required for this driver). */ -#pragma GCC push_options -#pragma GCC optimize("-O1") -#endif - -#if (defined(__CC_ARM) || defined(__ARMCC_VERSION)) -/* Enforce optimization off for clang, specifically to remove strict-aliasing option. -(-fno-strict-aliasing is required for this driver). */ -#pragma clang optimize off -#endif - -/* CASPER driver allows usage of 256, 384 and 521 ECC */ -#define CASPER_MAX_ECC_SIZE_WORDLEN (576u / 32U) -#define CASPER_RECODE_LENGTH_MAX 175 - -#define CASPER_RAM_BASE_NS (FSL_FEATURE_CASPER_RAM_BASE_ADDRESS) - -#if defined(FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED) && FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED -#define CASPER_RAM_OFFSET (FSL_FEATURE_CASPER_RAM_OFFSET) -#define INTERLEAVE(addr) \ - (((((((addr) >> 2U) & 0x00000001U) << CASPER_RAM_OFFSET) + (((addr) >> 3U) << 2U) + ((addr)&0x00000003U)) & \ - 0xFFFFU) | \ - s_casperRamBase) -#define DEINTERLEAVE(addr) INTERLEAVE(addr) -#define GET_WORD(addr) (*((uint32_t *)DEINTERLEAVE((uint32_t)(addr)))) -#define GET_DWORD(addr) (((uint64_t)GET_WORD(addr)) | (((uint64_t)GET_WORD(((uint32_t)(addr)) + 4U)) << 32U)) -#define SET_WORD(addr, value) *((uint32_t *)INTERLEAVE((uint32_t)(addr))) = ((uint32_t)(value)) -#define SET_DWORD(addr, value) \ - do \ - { \ - SET_WORD(addr, (uint32_t)(value & 0xFFFFFFFFU)); \ - SET_WORD(((uint32_t)(addr)) + 4U, (uint32_t)((value & 0xFFFFFFFF00000000U) >> 32U)); \ - } while (false) - -/* memcopy is always word aligned */ -/* interleaved to interleaved - static void CASPER_MEMCPY_I2I(void *dst, const void *src, size_t siz) - */ -#define CASPER_MEMCPY_I2I(dst, src, siz) \ - \ - { \ - uint32_t *dst32 = (uint32_t *)(dst); \ - const uint32_t *src32 = (const uint32_t *)(const uint32_t *)(src); \ - uint32_t i; \ - for (i = 0U; i < (siz) / 4U; i++) \ - { \ - SET_WORD(&dst32[i], GET_WORD(&src32[i])); \ - } \ - } - -/* interleaved to non-interleaved - static void CASPER_MEMCPY_I2N(void *dst, const void *src, size_t siz) - */ -#define CASPER_MEMCPY_I2N(dst, src, siz) \ - \ - { \ - uint32_t *dst32 = (uint32_t *)(dst); \ - const uint32_t *src32 = (const uint32_t *)(const uint32_t *)(src); \ - uint32_t i; \ - for (i = 0U; i < (siz) / 4U; i++) \ - { \ - dst32[i] = GET_WORD(&src32[i]); \ - } \ - } - -/* non-interleaved to interleaved - static void CASPER_MEMCPY_N2I(void *dst, const void *src, size_t siz) - */ -#define CASPER_MEMCPY_N2I(dst, src, siz) \ - \ - { \ - volatile uint32_t *dst32 = (uint32_t *)(dst); \ - const uint32_t *src32 = (const uint32_t *)(const uint32_t *)(src); \ - uint32_t i; \ - for (i = 0U; i < (siz) / 4U; i++) \ - { \ - SET_WORD(&dst32[i], src32[i]); \ - } \ - } -#else -#define GET_WORD(addr) (*((uint32_t *)(uint32_t)(addr))) -#define GET_DWORD(addr) (*((uint64_t *)(addr))) -#define SET_WORD(addr, value) *((uint32_t *)(uint32_t)(addr)) = ((uint32_t)(value)) -#define SET_DWORD(addr, value) *((uint64_t *)(addr)) = ((uint64_t)(value)) - -#define CASPER_MEMCPY_I2I(dst, src, siz) (void)memcpy(dst, src, siz) -#define CASPER_MEMCPY_I2N(dst, src, siz) (void)memcpy(dst, src, siz) -#define CASPER_MEMCPY_N2I(dst, src, siz) (void)memcpy(dst, src, siz) -#endif - -#define WORK_BUFF_MUL4 (N_wordlen_max * 4 + 2) /* ! working buffer is 4xN_wordlen to allow in place math */ -#define N_bytelen (N_wordlen * 4U) /* for memory copy and the like */ -#define N_dwordlen (unsigned)(N_wordlen / 2U) - -#define PreZeroW(i, w_out) \ - for ((i) = 0U; (i) < N_wordlen; (i) += 4U) \ - { \ - SET_WORD(&(w_out)[(i) + 0U], 0U); \ - SET_WORD(&(w_out)[(i) + 1U], 0U); \ - SET_WORD(&(w_out)[(i) + 2U], 0U); \ - SET_WORD(&(w_out)[(i) + 3U], 0U); \ - } /* unrolled partly */ -#define PreZeroW2up(i, w_out) \ - for (i = N_wordlen; i <= N_wordlen * 2U; i += 4U) \ - { \ - SET_WORD(&w_out[i + 0U], 0U); \ - SET_WORD(&w_out[i + 1U], 0U); \ - SET_WORD(&w_out[i + 2U], 0U); \ - SET_WORD(&w_out[i + 3U], 0U); \ - } /* unrolled partly */ - -/* Macros for the ECC component in Casper */ - -/* CASPER memory layout for ECC */ - -#define CASPER_MEM ((uint32_t *)msg_ret) - -/* Currently these macros work on 32-bit platforms */ - -#define add(c1, c0, a, b) \ - \ - do \ - { \ - uint32_t _t; \ - _t = a + b; \ - c1 = (uint32_t)(_t < a); \ - c0 = _t; \ - \ - } while (false) - -#define add_cout(carry, c, a, b) add((carry), (c), (a), (b)) - -#define add_cout_cin(carryout, c, a, b, carryin) \ - do \ - { \ - uint64_t _t = (uint64_t)(a) + (b) + (carryin); \ - (c) = (uint32_t)_t; \ - (carryout) = (uint32_t)(_t >> 32); \ - } while (false) - -#define sub_borrowout(borrow, c, a, b) \ - do \ - { \ - uint32_t _b = (uint32_t)((b) > (a)); \ - (c) = (a) - (b); \ - (borrow) = _b; \ - } while (false) - -#define sub_borrowin_borrowout(borrowout, c, a, b, borrowin) \ - do \ - { \ - uint32_t _t, _borrow1, _borrow2; \ - sub_borrowout(_borrow1, _t, (a), (b)); \ - sub_borrowout(_borrow2, (c), _t, (borrowin)); \ - (borrowout) = _borrow1 + _borrow2; \ - } while (false) - -#define sub_borrowout_1(borrow, c, a) \ - do \ - { \ - uint32_t _b = 0; \ - c = a - b; \ - borrow = _b; \ - } while (false) - -#define sub_borrowin_borrowout_1(borrowout, c, a, borrowin) \ - do \ - { \ - uint32_t _t, _borrow1, _borrow2; \ - sub_borrowout_1(_borrow1, _t, a); \ - sub_borrowout(_borrow2, c, _t, borrowin); \ - borrowout = _borrow1 + _borrow2; \ - } while (false) - -/* 32 x 32 --> 64-bit multiplication - * (c1,c0) = a * b - */ -#define mul(c1, c0, a, b) \ - \ - do \ - { \ - uint64_t __m; \ - __m = (uint64_t)a * (uint64_t)b; \ - c0 = (uint32_t)__m; \ - c1 = (uint32_t)(__m >> (uint64_t)32); \ - \ - } while (false) - -/* Multiply-and-accumulate - * (c1,c0) = a*b+c0 - */ -#define muladd(c1, c0, a, b) \ - \ - do \ - { \ - uint32_t __ma = c0; \ - mul(c1, c0, a, b); \ - c0 = c0 + __ma; \ - c1 = c1 + (c0 < __ma); \ - \ - } while (0) - -/* Multiply-and-accumulate-accumulate - * (c1,c0) = a*b+c0+c1 - */ -#define muladdadd(c1, c0, a, b) \ - \ - do \ - { \ - uint32_t __maa0 = c0, __maa1 = c1; \ - mul(c1, c0, a, b); \ - c0 = c0 + __maa0; \ - c1 = c1 + (c0 < __maa0); \ - c0 = c0 + __maa1; \ - c1 = c1 + (c0 < __maa1); \ - \ - } while (0) - -#define square_casper(c, a) multiply_casper(c, a, a) -#define sub_casper(c, a, b) CASPER_montsub(c, a, b, &CASPER_MEM[(N_wordlen + 4U)]) -#define add_casper(c, a, b) CASPER_montadd(c, a, b, &CASPER_MEM[(N_wordlen + 4U)]) -#define mul2_casper(c, a) add_casper(c, a, a) -#define half(c, a, b) CASPER_half(c, a, b) -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* The model for this algo is that it can be implemented for a fixed size RSA key */ -/* for max speed. If this is made into a variable (to allow varying size), then */ -/* it will be slower by a bit. */ -/* The file is compiled with N_bitlen passed in as number of bits of the RSA key */ -/* #define N_bitlen 2048 */ -static size_t N_wordlen = 0U; /* ! number of words (e.g. 4096/32 is 128 words) */ - -static uint32_t s_casperRamBase = CASPER_RAM_BASE_NS; -static uint32_t *msg_ret = (uint32_t *)CASPER_RAM_BASE_NS; - -/* NISTp-256 = 2^256-2^224+2^192+2^96-1 */ -static uint32_t NISTp256[256 / 32u] = {0xffffffffU, 0xffffffffU, 0xffffffffU, 0x00000000, - 0x00000000, 0x00000000, 0x00000001, 0xffffffffU}; - -/* The cardinality of the curve E(F_p) */ -static uint32_t NISTp256_q[256 / 32u] = {0xfc632551U, 0xf3b9cac2U, 0xa7179e84U, 0xbce6faadU, - 0xffffffffU, 0xffffffffU, 0x00000000, 0xffffffffU}; - -/* R = 2^256 mod p, the value "1" in Montgomery form. */ -static uint32_t NISTr256[256 / 32u] = {0x00000001, 0x00000000, 0x00000000, 0xffffffffU, - 0xffffffffU, 0xffffffffU, 0xfffffffeU, 0x00000000}; - -static uint32_t Np256[2] = {1, 0}; - -/* NISTp-384 = 2^384 - 2^128 - 2^96 + 2^32 - 1 */ -static uint32_t NISTp384[384 / 32u] = {0xffffffffU, 0x00000000, 0x00000000, 0xffffffffU, 0xfffffffeU, 0xffffffffU, - 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU}; - -/* The cardinality of the curve E(F_p) */ -static uint32_t NISTp384_q[384 / 32u] = {0xccc52973U, 0xecec196aU, 0x48b0a77aU, 0x581a0db2U, 0xf4372ddfU, 0xc7634d81U, - 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU}; - -/* R = 2^256 mod p, the value "1" in Montgomery form. */ -static uint32_t NISTr384[384 / 32u] = {0x00000001, 0xffffffffU, 0xffffffffU, 0x00000000, 0x1, 0, 0, 0, 0, 0, 0, 0}; - -// -p^-1 mod 2^64 = 0x100000001 -static uint32_t Np384[2] = {1, 1}; - -/* NISTp-521 = 2^521 - 1 */ -static uint32_t NISTp521[576 / 32U] = {0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, - 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, - 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0x1ffU, 0}; - -/* The cardinality of the curve E(F_p) */ -static uint32_t NISTp521_q[576 / 32U] = {0x91386409U, 0xbb6fb71eU, 0x899c47aeU, 0x3bb5c9b8U, 0xf709a5d0U, 0x7fcc0148U, - 0xbf2f966bU, 0x51868783U, 0xfffffffaU, 0xffffffffU, 0xffffffffU, 0xffffffffU, - 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0x1ffU, 0}; - -/* R = 2^576 mod p, the value "1" in Montgomery form. */ -static uint32_t NISTr521[576 / 32U] = {0, 0x800000, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - -/* -p^-1 mod 2^64 = 1 */ -static uint32_t Np521[2] = {1, 0}; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/* Convert a projective point (X1 : Y1 : Z1) - * to the affine point (X3, Y3) = (X1/Z1^2,Y1/Z1^3) - * The memory of (X3, Y3) and (X1 : Y1 : Z1) should not overlap - */ -void Jac_toAffine(uint32_t *X3, uint32_t *Y3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1); - -/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2 : Y2 : Z2) - * where (X1: Y1: Z1) != (X2 : Y2 : Z2) - * (X3 : Y3: Z3) may be the same as one of the inputs. - */ -void Jac_addition(uint32_t *X3, - uint32_t *Y3, - uint32_t *Z3, - uint32_t *X1, - uint32_t *Y1, - uint32_t *Z1, - uint32_t *X2, - uint32_t *Y2, - uint32_t *Z2); - -/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2, Y2) - * where (X1: Y1: Z1) != (X2, Y2) - * (X3 : Y3: Z3) may not overlap with (X1: Y1: Z1). - * Source: 2004 Hankerson?Menezes?Vanstone, page 91. - */ -void Jac_add_affine( - uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *X2, uint32_t *Y2); - -/* Point doubling from: 2004 Hankerson?Menezes?Vanstone, page 91. - * Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X1 : Y1 : Z1) - * (X3 : Y3: Z3) may be the same as the input. - */ -void Jac_double(uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1); - -/* Constant time elliptic curve scalar multiplication. - * Source: https://eprint.iacr.org/2014/130.pdf - * when using w = 4. - * Computes (X3 : Y3 : Z3) = k * (X1, Y1) \in E(F_p) - * p is the prime used to define the finite field F_p - * q is the (prime) order of the curve - */ -void Jac_scalar_multiplication( - uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *k, uint32_t *p, uint32_t *q); - -/* Compute the double scalar multiplication - * (X3 : Y3 : Z3) = k1 * (X1, Y1) + k2 * (X2, Y2) - * Using Shamir's trick and precomputing 16 points. - * This code is *not* constant time since this is used - * for verification only. - */ -void double_scalar_multiplication(uint32_t *X3, - uint32_t *Y3, - uint32_t *Z3, - uint32_t *X1, - uint32_t *Y1, - uint32_t *k1, - uint32_t *X2, - uint32_t *Y2, - uint32_t *k2); - -/* Compute inversion modulo NIST-p384 using Fermats little theorem. - * Using c = a^(p-2) = a^(-1) mod p. - * This computes the modular inversion if all arithmetic is "regular" - * modular arithmetic or computes automatically the Montgomery inverse - * if all arithmetic is Montgomery arithmetic. - */ -static void invert_mod_p384(uint32_t *c, uint32_t *a); - -/* Modular inversion for NIST-P256 */ -static void invert_mod_p256(uint32_t *c, uint32_t *a); - -/* Modular inversion for NIST-P521 */ -static void invert_mod_p521(uint32_t *c, uint32_t *a); - -// A and C do not need to be in Casper memory -static void toMontgomery_ECC_P256(uint32_t *C, uint32_t *A); -static void toMontgomery_ECC_P384(uint32_t *C, uint32_t *A); -static void toMontgomery_ECC_P521(uint32_t *C, uint32_t *A); - -static void CASPER_montsub(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod); -static void CASPER_montadd(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod); - -/* Compute c = a/2 mod p where b is scratch space. */ -static void CASPER_half(uint32_t *c, uint32_t *a, uint32_t *b); - -void CASPER_MEMCPY(void *dst, const void *src, size_t siz); - -static void multiply_casper(uint32_t w_out[], const uint32_t a[], const uint32_t b[]); - -static uint8_t int8abs(int8_t v); - -/* Constant time select c = a if m = 0 or - * c = b if m = 1 - * a, b, c are n words - */ -static void casper_select(uint32_t *c, uint32_t *a, uint32_t *b, int m, int n); - -/* Dumb n-limb addition of c=a+b, return carry. */ -static uint32_t add_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n); - -#if 0 -/* Dumb n-limb addition of c=a+b, return carry. */ -static uint32_t add_n(uint32_t *c, uint32_t *a, uint32_t *b, int n); - -/* Dumb n-limb subtraction of c=a-b, return borrow. */ -static uint32_t sub_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n); -#endif - -/* Dumb n-limb subtraction of c=a-b, return borrow. */ -static uint32_t sub_n(uint32_t *c, uint32_t *a, uint32_t *b, int n); - -int RSA_SignatureToPlaintextFast(const unsigned signature[N_wordlen_max], - const unsigned exp_pubkey, - const unsigned pubkey[N_wordlen_max], - unsigned MsgRet[WORK_BUFF_MUL4]); - -int RSA_MontSignatureToPlaintextFast(const unsigned mont_signature[N_wordlen_max], - const unsigned exp_pubkey, - const unsigned pubkey[N_wordlen_max], - unsigned MsgRet[WORK_BUFF_MUL4]); - -void MultprecMultiply(unsigned w_out[], const unsigned u[], const unsigned v[]); - -void MultprecGenNp64(const unsigned *Nmod, unsigned *np64_ret); -void MultprecMontPrepareX(unsigned Xmont_out[], const unsigned x[], const unsigned Rp[], const unsigned Nmod[]); -void MultprecModulo(unsigned r_out[], const unsigned v[], int top); -void MultprecCiosMul( - unsigned w_out[], const unsigned a[], const unsigned b[], const unsigned Nmod[], const unsigned *Np); -void MultprecMontCalcRp(unsigned Rp[], const unsigned exp_pubkey, const unsigned Nmod[]); - -static void MultprecCiosMul_ct( - uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np); - -static void MultprecCiosMul521_ct( - uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np); - -static void shiftrightSysram(uint32_t *z, uint32_t *x, uint32_t c); -static void shiftright(uint32_t *z, uint32_t *x, uint32_t c); -static void shiftleft(uint32_t *z, uint32_t *x, uint32_t c); - -/******************************************************************************* - * Code - ******************************************************************************/ - -__STATIC_FORCEINLINE uint32_t CA_MK_OFF(const void *addr) -{ - return ((uint32_t)(const uint32_t *)addr - s_casperRamBase); -} - -#if 1 -__STATIC_FORCEINLINE void Accel_done(void) -{ - register uint32_t status; - do - { - status = CASPER->STATUS; - } while (0U == (status & CASPER_STATUS_DONE_MASK)); -} - -__STATIC_FORCEINLINE void Accel_SetABCD_Addr(uint32_t ab, uint32_t cd) -{ - CASPER->CTRL0 = ab | (cd << 16); /* CDoffset << 16 | ABoffset */ -} - -__STATIC_FORCEINLINE void Accel_crypto_mul(uint32_t ctrl1) -{ - CASPER->CTRL1 = ctrl1; -} -#else -#include "intrinsics.h" -#define Accel_done() \ - { \ - register uint32_t status; \ - do \ - { \ - status = CASPER_Rd32b(CASPER_CP_STATUS); \ - } while (0 == (status & CASPER_STATUS_DONE_MASK)); \ - } -#if 0 -__STATIC_FORCEINLINE void Accel_done(void) -{ - register uint32_t status; - do - { - status = CASPER->STATUS; - } while (0 == (status & CASPER_STATUS_DONE_MASK)); -} -#endif -#define Accel_SetABCD_Addr(ab, cd) CASPER_Wr32b((uint32_t)ab | ((uint32_t)cd << 16), CASPER_CP_CTRL0); -#define Accel_crypto_mul(ctrl1) CASPER_Wr32b((uint32_t)ctrl1, CASPER_CP_CTRL1); -#endif - -__STATIC_FORCEINLINE uint32_t Accel_IterOpcodeResaddr(uint32_t iter, uint32_t opcode, uint32_t resAddr) -{ - return CASPER_CTRL1_ITER(iter) | CASPER_CTRL1_MODE(opcode) | (resAddr << 16); -} - -void CASPER_MEMCPY(void *dst, const void *src, size_t siz) -{ - bool bdst = - ((((uint32_t)(uint32_t *)dst) | 0x10000000u) >= ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) && - (((uint32_t)(uint32_t *)dst) | 0x10000000u) < - ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) + 8u * 1024u); - - bool bsrc = ((((uint32_t)(const uint32_t *)src) | 0x10000000u) >= - ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) && - (((uint32_t)(const uint32_t *)src) | 0x10000000u) < - ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) + 8u * 1024u); - - if (bdst && bsrc) - { - CASPER_MEMCPY_I2I(dst, src, siz); - } - else if (bdst && !bsrc) - { - CASPER_MEMCPY_N2I(dst, src, siz); - } - else if (!bdst && bsrc) - { - CASPER_MEMCPY_I2N(dst, src, siz); - } - else - { - (void)memcpy(dst, src, siz); - } -} - -/* Constant time select c = a if m = 0 or - * c = b if m = 1 - * a, b, c are n words - */ -static void casper_select(uint32_t *c, uint32_t *a, uint32_t *b, int m, int n) -{ - uint32_t m1 = 0U - (uint32_t)m, m2 = ~m1; - int i; - - for (i = 0; i < n; i++) - { - SET_WORD(&c[i], (GET_WORD(&a[i]) & m2) | (GET_WORD(&b[i]) & m1)); - } -} - -/* Compute R`, which is R mod N. This is done using subtraction */ -/* R has 1 in N_wordlen, but we do not fill it in since borrowed. */ -/* Exp-pubkey only used to optimize for exp=3 */ -void MultprecMontCalcRp(unsigned Rp[], const unsigned exp_pubkey, const unsigned Nmod[]) -{ - uint32_t i; - - /* R is 2^n where n is 1 bit longer than Nmod, so 1 followed by 32 or 64 0 words for example */ - /* Note that Nmod's upper most bit has to be 1 by definition, so one subtract is enough. We */ - /* do not set the 1 since it is "borrowed" so no point */ - PreZeroW(i, Rp); - Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(Rp))); - Accel_done(); - /* final borrow cannot happen since we know we started with a larger number */ -} - -/* MultprecMultiply - multiple w=u*v (per Knuth) */ -/* w_out is 2x the size of u and v */ -void MultprecMultiply(unsigned w_out[], const unsigned u[], const unsigned v[]) -{ - uint32_t i, j; - - /* Knuth 4.3.1 - Algorithm M */ - /* Compute w = u * v */ - /* u and v are N bits long in 32 bit word form */ - /* w is 2*N bits long in 32 bit word form */ - /* Note: We just multiply in place */ - - /* Step 1. Fill w[t-1:0] with 0s, the upper half will be written as we go */ - PreZeroW(i, w_out); - - /* We do 1st pass NOSUM so we do not have to 0 output */ - Accel_SetABCD_Addr(CA_MK_OFF(&v[0]), CA_MK_OFF(u)); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpMul6464NoSum, CA_MK_OFF(&w_out[0]))); - Accel_done(); - /* Step 2. iterate over N words of v using j */ - for (j = 2U; j < N_wordlen; j += 2U) - { - /* Step 2b. Check for 0 on v word - skip if so since we 0ed already */ - /* Step 3. Iterate over N words of u using i - perform Multiply-accumulate */ - if (0U != (GET_WORD(&v[j])) || 0U != (GET_WORD(&v[j + 1U]))) - { - Accel_SetABCD_Addr(CA_MK_OFF(&v[j]), CA_MK_OFF(u)); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpMul6464Sum, CA_MK_OFF(&w_out[j]))); - Accel_done(); - } - } -} - -/* MultprecModulo performs divide to get remainer as needed for RSA */ -/* This performs (q,r) = u/v, but we do not keep q */ -/* r_out is module (remainder) and is 2*N */ -/* u is in r_out (1st N) at start (passed in) */ -/* v is N long */ -void MultprecModulo(unsigned r_out[], const unsigned v[], int top) -{ - uint64_t u64; /* use 64 bit math mixed with 32 bit */ - unsigned u32; /* allows us to work on U in 32 bit */ - unsigned u_n, ul16, uh16, *u_shft; /* u_shft is because r_out is u initially */ - unsigned vl16, vh16, v_Nm1; - unsigned q_hat, r_hat, q_over; - unsigned borrow, carry; - uint32_t i; - int j, tmp; - - /* Knuth 4.3.1 - Algorithm D */ - /* Compute q = u / v giving remainder r = u mod v */ - /* -- we only want r, so we build qhat but do not store the Qs */ - /* v is N long, with u,q,r 2N long because u is slowly replavced by r. */ - /* We normalize/unnormlize per Knuth in the buffer (not copied) */ - - /* Step 1. Normalize value so MSb is in v[n-1]. Remember that v is */ - /* the public key - to call it a 2048 bit number, they cannot have 0 */ - /* in the MSb (or it would be less than 2048 bits) and so we know we */ - /* are normalized already. Therefore, u is effectively shifted already. */ - /* For u, we have it in r_out. u[n] holds any overflow */ - /* Since divide on CM3/4 is 32/32=32, we break into 16 bit halves, but */ - /* multiply can be 32x32=64. */ - u_n = 0; - u_shft = r_out; /* u (shifted) is in r_out */ - - v_Nm1 = GET_WORD(&v[N_wordlen - 1U]); /* MSw of public key */ - vl16 = v_Nm1 & 0xFFFFU; /* lower 16 */ - vh16 = v_Nm1 >> 16; /* upper 16 */ - /* Step 2. Iterate j from m-n down to 0 (M selected per Knuth as 2*N) */ - for (j = top; j >= 0; j--) - { - /* Step 3. estimate q_hat as (U[j+n]*B + U[j+n-1]) / V[n-1] */ - /* Note: using subset of Knuth algo since v is 1/2 len of u (which is */ - /* from multiply or x^2 leading into this). */ - u32 = u_n; /* pickup u4u3u2, knowing u4 is 0 */ - u64 = ((uint64_t)u_n << 32) | GET_WORD(&u_shft[(uint32_t)j + N_wordlen - 1U]); - ul16 = (unsigned int)(u64 & 0xFFFFU); /* lower 16 */ - uh16 = (unsigned int)((u64 >> 16) & 0xFFFFU); /* upper 16 */ - - /* we see if even possible (u large enough relative to v) */ - if ((u32 - v_Nm1) <= u32) - { - u32 -= v_Nm1; - q_over = 1; /* overflow from the sub */ - } - else - { - q_over = 0; - } - /* q_hat = u32 / vh16 -- is the upper partial value */ - /* estimate; if too much, then back down by 1 or 2 */ - q_hat = u32 / vh16; - r_hat = u32 - (q_hat * vh16); - /* see if Q is more than 16 bits or remainder is too large (over div) */ - if ((q_hat == 0x10000U) || ((q_hat * vl16) > ((r_hat << 16) | uh16))) - { - /* too much - undo a division */ - q_hat--; - r_hat += vh16; - /* check if still too much */ - if ((r_hat < 0x10000U) && ((q_hat * vl16) > ((r_hat << 16) | uh16))) - { - q_hat--; /* yes, so undo a 2nd */ - } - } - - /* compose u3u2uh16, then sub q_hat*v if OK */ - u64 = (((uint64_t)u32 << 16) | uh16) - ((uint64_t)q_hat * v_Nm1); - if (0U != (u64 >> 48)) - { - /* no, so add v back */ - u32 = (unsigned)(u64 + v_Nm1); - q_hat--; - } - else - { - u32 = (unsigned)u64; - } - tmp = (int32_t)(uint32_t)(q_hat << 16); /* quotient upper part */ - - /* divide lower part: q = u2uh16ul16 / v. */ - /* estimate and add back if over divdied */ - q_hat = u32 / vh16; - r_hat = u32 - (q_hat * vh16); - if ((q_hat == 0x10000U) || ((q_hat * vl16) > ((r_hat << 16) | ul16))) - { - /* too much - undo a division */ - q_hat--; - r_hat += vh16; - /* check if still too much */ - if ((r_hat < 0x10000U) && ((q_hat * vl16) > ((r_hat << 16) | ul16))) - { - q_hat--; /* yes, so undo a 2nd */ - } - } - - /* compose u2uh16ul16, then sub q_hat*v if OK */ - u64 = (((uint64_t)u32 << 16) | ul16) - ((uint64_t)q_hat * v_Nm1); - if (0U != (u64 >> 48)) - { - /* no, so add v back */ - r_hat = (unsigned)(u64 + v_Nm1); - q_hat--; - } - else - { - r_hat = (unsigned)u64; - } - q_hat |= (unsigned)tmp; /* other half of the quotient */ - while ((q_over != 0U) || ((uint64_t)q_hat * GET_WORD(&v[N_wordlen - 2U])) > - ((1ULL << 32) * r_hat) + (uint64_t)GET_WORD(&u_shft[(uint32_t)j + N_wordlen - 2U])) - { /* if Qhat>b, then reduce to b-1, then adjust up Rhat */ - q_hat--; - r_hat += v_Nm1; - if (r_hat < v_Nm1) - { - break; /* no overflow */ - /* else repeat since Rhat >= b */ - } - } - - /* Step 4. Multiply and subtract. We know the amount, */ - /* so we do the schoolboy math. Have to do on */ - /* the large value. */ - if (q_hat != 0U) - { - borrow = 0; - for (i = 0; i < N_wordlen; i++) - { - u64 = (uint64_t)q_hat * GET_WORD(&v[i]) + borrow; - borrow = (unsigned)(u64 >> 32); - if (GET_WORD(&u_shft[i + (unsigned)j]) < (unsigned)u64) - { - borrow++; /* carry the overflow */ - } - SET_WORD(&u_shft[i + (unsigned)j], GET_WORD(&u_shft[i + (unsigned)j]) - (unsigned)u64); - } - u_n -= borrow; /* overflow from shift left does not fit otherwise */ - } - - /* Store 5. (update Q - we don't), and add back V to remainder if we over-subtracted */ - /* That restores remainder to correct (we could only be off by 1) */ - /* This should happen very rarely. */ - if (u_n != 0U) - { - carry = 0; - for (i = 0; i < N_wordlen; i++) - { - SET_WORD(&u_shft[i + (unsigned)j], GET_WORD(&u_shft[i + (unsigned)j]) + carry); - carry = (GET_WORD(&u_shft[i + (unsigned)j]) < carry) ? 1U : 0U; - SET_WORD(&u_shft[i + (unsigned)j], GET_WORD(&u_shft[i + (unsigned)j]) + GET_WORD(&v[i])); - if (GET_WORD(&u_shft[i + (unsigned)j]) < GET_WORD(&v[i])) - { - carry++; - } - } - } - u_n = GET_WORD( - &u_shft[(uint32_t)j + N_wordlen - 1U]); /* hold upper part of u to catch overflow (to borrow from) */ - } - /* low N bits of r are valid as remainder */ -} - -/* We convert X into a Mont form number. Note length of arrays: */ -/* x is N_wordlen, Nmod is N_wordlen */ -/* Rp is N_wordlen (it is R` which is R mod N) */ -/* Xmont_out is N_wordlen*2+1 */ -void MultprecMontPrepareX(unsigned Xmont_out[], const unsigned x[], const unsigned Rp[], const unsigned Nmod[]) -{ - MultprecMultiply(Xmont_out, x, Rp); - MultprecModulo(Xmont_out, Nmod, (int32_t)N_wordlen); -} - -void MultprecGenNp64(const unsigned *Nmod, unsigned *np64_ret) /* only pass the low order double word */ -{ - uint64_t nprime, Nmod_0; - Nmod_0 = GET_WORD(&Nmod[0]) | ((uint64_t)GET_WORD(&Nmod[1]) << 32); - -#define COMP_NPN_1 ((2U - Nmod_0 * nprime) * nprime) /* computes N`*N0=1 mod 2^P where P is the partial built up */ - nprime = (((2U + Nmod_0) & 4U) << 1) + Nmod_0; /* mod 2^4 */ - nprime = COMP_NPN_1; - nprime = COMP_NPN_1; - nprime = COMP_NPN_1; - nprime = COMP_NPN_1; - /* 8 multiplies of uint64_t */ - *((uint64_t *)(uintptr_t)np64_ret) = (~0ULL - nprime) + 1ULL; -} - -/* CIOS Multiply. This is the Coarse Integrated form where the values are */ -/* multiplied and reduced for each step of "i". This uses less memory and */ -/* is faster as a result. Note that this is used to square as well as mul, */ -/* so not as fast as pure squaring could be. */ -void MultprecCiosMul( - unsigned w_out[], const unsigned a[], const unsigned b[], const unsigned Nmod[], const unsigned *Np) -{ - int j; - uint32_t i; - uint64_t *m64 = (uint64_t *)(uintptr_t)&msg_ret[kCASPER_RamOffset_M64]; - uint64_t Np64; - uint64_t carry; - uint64_t *a64, *b64, *w64, *N64; - - Np64 = *(uint64_t *)(uintptr_t)Np; - - a64 = (uint64_t *)(uintptr_t)a; - b64 = (uint64_t *)(uintptr_t)b; - w64 = (uint64_t *)(uintptr_t)w_out; - N64 = (uint64_t *)(uintptr_t)Nmod; - - if (a != NULL) - { /* if !a, we are reducing only */ - PreZeroW(i, w_out); - } - SET_DWORD(&w64[N_dwordlen], 0ULL); - SET_DWORD(&w64[N_dwordlen + 1U], 0ULL); - /* with accelerator */ - - /* loop i and then reduce after each j round */ - for (i = 0; i < N_dwordlen; i++) - { - /* Step 3. Iterate over N words of u using i - perform Multiply-accumulate */ - /* push-pull: we do a*b and then separately m*n (reduce) */ - if (a != NULL) - { /* if mul&reduce vs. reduce only */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(&b64[i]), CA_MK_OFF(a64)); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); - Accel_done(); - /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ - /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ - /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ - /* w64[N_dwordlen+1] = g_carry; */ - carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); - SET_DWORD(&w64[N_dwordlen + 1U], carry); - } - SET_DWORD(&m64[0], GET_DWORD(&w64[0]) * Np64); /* prime for 1st; modulo a double-word */ - - /* we are reducing, so the 1st [0th] 64 bit value product is tossed, but we */ - /* need its carry. We let the accel do this separately - really need a mode to */ - /* do this "reduce" since it is natural */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(m64), CA_MK_OFF(&N64[0])); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(&w64[0]))); - Accel_done(); - carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); - - Accel_SetABCD_Addr(CA_MK_OFF(&w64[1]), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpCopy, CA_MK_OFF(&w64[0]))); - - Accel_done(); - SET_DWORD(&w64[N_dwordlen], (GET_DWORD(&w64[N_dwordlen + 1U]) + carry)); - } - - /* now check if need to subtract Nmod */ - if (0U != (GET_WORD(&w_out[N_wordlen]))) - { - j = 1; /* we have to subtract for sure if carry up */ - } - else - { - j = 0; - for (i = N_wordlen - 1U; i > 0U; i--) - { - if (GET_WORD(&w_out[i]) != GET_WORD(&Nmod[i])) - { - j = (int32_t)(GET_WORD(&w_out[i]) > GET_WORD(&Nmod[i])); /* if larger sub */ - break; /* we would remove the break if worrying about side channel */ - } - } - } - if (0 == j) - { - return; /* Is smaller than Nmod, so done. */ - } - Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(w_out))); - Accel_done(); - /* last borrow is OK since we know it could only be <2N and */ -} - -/* RSA_MontSignatureToPlaintextFast: */ -/* MsgRet[] = Message return buffer - must be large enough to hold input and output (4*N+2) */ -/* exp_pubkey = the "e" that the value is raised to. Usually 3 or 0x10001. */ -/* signature = N bitpos len long "message" to process in Montgomery form - so saving conversion (divide) */ -/* pubkey = N bitpos len long public key to process signature with */ -/* returns: 0 */ -/* */ -/* Algo: compute M = signaturen^e mod public_key */ -/* where M is original plaintext, signature is signed value */ -/* note: e is usually either 0x3 or 0x10001 */ -int RSA_MontSignatureToPlaintextFast(const unsigned mont_signature[N_wordlen_max], - const unsigned exp_pubkey, - const unsigned pubkey[N_wordlen_max], - unsigned MsgRet[WORK_BUFF_MUL4]) -{ - int bidx = 0; - int bitpos; - unsigned np64[2]; - - /* MsgRet working area: */ - /* 0..N = RESULT, starting with S` */ - /* N..N*2 = S` and then working BASE during math. */ - /* N*2..N*4+2 = temp working area for Mont mul */ - - /* 1. Copy sig into MsgRet so we have one working result buffer */ - CASPER_MEMCPY_I2I((uint32_t *)(uintptr_t)&MsgRet[kCASPER_RamOffset_Result], - (const uint32_t *)(uintptr_t)mont_signature, N_bytelen); - MultprecGenNp64(pubkey, np64); /* Generate N` from LSW of N (LSW being lowest 64b word) */ - bitpos = (int8_t)(uint8_t)(31U - __CLZ(exp_pubkey)); /* count of bits after the left most 1 */ - while (--bitpos >= 0) - { - /* This operates on: */ - /* result = 1; */ - /* base = signature */ - /* loop while exponent bits from MSb to LSb */ - /* if (exp bit is 1) */ - /* result = result * base */ - /* base = base^2 */ - /* Because the MSb of exp is always 1 by definition, we can invert this a bit: */ - /* base = signature` */ - /* result = base; equivalent to result = 1*base from 1st pass, but now square is needed 1st */ - /* loop while exponent bits from MSb-1 to LSb */ - /* base = base^2 */ - /* if (exp bit is 1) */ - /* result = result * base */ - /* This ends up doing the same thing but skips two wasteful steps of multiplying by 1 and */ - /* a final squaring never used. */ - /* */ - /* Next we have the problem that CIOS mul needs a separate dest buffer. So, we bounce */ - /* base between base and temp, and likewise for result. */ - MultprecCiosMul(&MsgRet[(bidx != 0) ? kCASPER_RamOffset_Base : kCASPER_RamOffset_TempBase], - &MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], - &MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], pubkey, np64); - if (0U != (exp_pubkey & (uint32_t)(uint8_t)(1U << (uint8_t)bitpos))) /* where e is 1 */ - { - /* result has result, so we need to work into other temp area */ - MultprecCiosMul(&MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], - &MsgRet[kCASPER_RamOffset_Result], - &MsgRet[(bidx != 0) ? kCASPER_RamOffset_Base : kCASPER_RamOffset_TempBase], pubkey, np64); - /* we have to copy back to result */ - - // CASPER_MEMCPY_I2I(&MsgRet[kCASPER_RamOffset_Result], - // &MsgRet[bidx ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], N_bytelen); - } - else - { - bidx = (int32_t)(uint32_t) ~(unsigned)bidx; - } - } - - CASPER_MEMCPY_I2I((uint32_t *)(uintptr_t)&MsgRet[kCASPER_RamOffset_Result], - (uint32_t *)(uintptr_t)&MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], - N_bytelen); - - /* final step is one more reduction to get back to normal form (ie. divide R out) */ - MultprecCiosMul(&MsgRet[kCASPER_RamOffset_Result], NULL, NULL, pubkey, np64); - return (0); /* always 0 */ -} - -/* RSA_SignatureToPlaintextFast: */ -/* MsgRet[] = Message return buffer - must be large enough to hold input and output (4*N+2) */ -/* exp_pubkey = the "e" that the value is raised to. Usually 3 or 0x10001. */ -/* signature = N bitpos len long "message" to process in normal form - so converted to Mont form */ -/* pubkey = N bitpos len long public key to process signature with */ -/* returns: 0 */ -/* */ -/* Algo: compute M = signaturen^e mod public_key */ -/* where M is original plaintext, signature is signed value */ -/* note: e is usually either 0x3 or 0x10001 */ -int RSA_SignatureToPlaintextFast(const unsigned signature[N_wordlen_max], - const unsigned exp_pubkey, - const unsigned pubkey[N_wordlen_max], - unsigned MsgRet[WORK_BUFF_MUL4]) -{ - /* MsgRet working area: */ - /* 0..N = RESULT, starting with S`; it is used for R` just during creation of S` */ - /* N..N*2 = S` and then working BASE during math. Note overflow beyond N*2 when making S` */ - /* N*2..N*4+2 = temp working area for Mont mul */ - - MultprecMontCalcRp(&MsgRet[kCASPER_RamOffset_Result], exp_pubkey, pubkey); /* calculate R` (=R mod N) */ - MultprecMontPrepareX(&MsgRet[kCASPER_RamOffset_Base], signature, &MsgRet[kCASPER_RamOffset_Result], - pubkey); /* X*R1` mod N */ - return (RSA_MontSignatureToPlaintextFast(&MsgRet[kCASPER_RamOffset_Base], exp_pubkey, pubkey, MsgRet)); -} - -/*! - * brief Performs modular exponentiation - (A^E) mod N. - * - * This function performs modular exponentiation. - * - * param base CASPER base address - * param signature first addend (in little endian format) - * param pubN modulus (in little endian format) - * param wordLen Size of pubN in bytes - * param pubE exponent - * param[out] plaintext Output array to store result of operation (in little endian format) - */ -void CASPER_ModExp( - CASPER_Type *base, const uint8_t *signature, const uint8_t *pubN, size_t wordLen, uint32_t pubE, uint8_t *plaintext) -{ -#define PK_LOC &msg_ret[kCASPER_RamOffset_Modulus] -#define SIG_LOC &msg_ret[(unsigned)kCASPER_RamOffset_Modulus + N_wordlen_max] - - N_wordlen = wordLen; /* set global variable for key length - used by RSA_SignatureToPlaintextFast() */ - CASPER_MEMCPY_N2I(PK_LOC, (const uint32_t *)(uintptr_t)pubN, N_bytelen); - CASPER_MEMCPY_N2I(SIG_LOC, (const uint32_t *)(uintptr_t)signature, N_bytelen); - (void)RSA_SignatureToPlaintextFast((const unsigned *)(uintptr_t)(SIG_LOC), pubE, - (const unsigned *)(uintptr_t)(PK_LOC), (unsigned int *)(uintptr_t)msg_ret); - - CASPER_MEMCPY_I2N((uint32_t *)(uintptr_t)plaintext, msg_ret, N_bytelen); -} - -/*! - * brief Enables clock and disables reset for CASPER peripheral. - * - * Enable clock and disable reset for CASPER. - * - * param base CASPER base address - */ -void CASPER_Init(CASPER_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(CASPER_CLOCKS) - CLOCK_EnableClock(kCLOCK_Casper); -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if defined(CASPER_RSTS) - RESET_PeripheralReset(kCASPER_RST_SHIFT_RSTn); -#endif -#if defined(FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE) && (FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE > 0) - /* Enable hardware interleaving to RAMX0 and RAMX1 for CASPER */ - SYSCON->CASPER_CTRL = SYSCON_CASPER_CTRL_INTERLEAVE(1); -#endif /* FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE */ - /* If Casper init is called with secure address, use secure addres also for accessing Casper RAM. */ - s_casperRamBase = (unsigned)CASPER_RAM_BASE_NS | ((uint32_t)base & 0x10000000u); - msg_ret = (uint32_t *)s_casperRamBase; -} - -/*! - * brief Disables clock for CASPER peripheral. - * - * Disable clock and enable reset. - * - * param base CASPER base address - */ -void CASPER_Deinit(CASPER_Type *base) -{ -#if defined(CASPER_RSTS) - RESET_SetPeripheralReset(kCASPER_RST_SHIFT_RSTn); -#endif -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(CASPER_CLOCKS) - CLOCK_DisableClock(kCLOCK_Casper); -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/* New ECC code which uses Casper. */ - -/* Set the prime modulus mod in Casper memory. - */ -void CASPER_ecc_init(casper_algo_t curve) -{ - uint32_t *mod; - - if (curve == kCASPER_ECC_P256) - { - N_wordlen = 256U / 32U; - mod = NISTp256; - } - - if (curve == kCASPER_ECC_P384) - { - N_wordlen = 384U / 32U; - mod = NISTp384; - } - - if (curve == kCASPER_ECC_P521) - { - N_wordlen = 576U / 32U; - mod = NISTp521; - } - - CASPER_MEMCPY(&CASPER_MEM[(N_wordlen + 4U)], mod, N_wordlen * sizeof(uint32_t)); - uint8_t a[((CASPER_MAX_ECC_SIZE_WORDLEN + 4U) - CASPER_MAX_ECC_SIZE_WORDLEN) * sizeof(uint32_t)] = {0}; - CASPER_MEMCPY(&CASPER_MEM[(N_wordlen + 4U) + N_wordlen], a, ((N_wordlen + 4U) - N_wordlen) * sizeof(uint32_t)); -} - -void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2) -{ - uint32_t a[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; - uint32_t b[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; - uint32_t c = 0; - CASPER_MEMCPY(a, op1, N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(b, op2, N_wordlen * sizeof(uint32_t)); - - do - { - uint32_t _i; - c = (a[0] ^ b[0]); - for (_i = 1; _i < N_wordlen; _i++) - { - c |= (a[_i] ^ b[_i]); - } - } while (false); - - *res = (int32_t)c; -} - -void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1) -{ - uint32_t a[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; - uint32_t c = 0; - CASPER_MEMCPY(a, op1, N_wordlen * sizeof(uint32_t)); - - do - { - uint32_t _i; - c = a[0]; - for (_i = 1; _i < N_wordlen; _i++) - { - c |= a[_i]; - } - } while (false); - - *res = (int32_t)c; -} - -void CASPER_ECC_SECP256R1_Mul( - CASPER_Type *base, uint32_t resX[8], uint32_t resY[8], uint32_t X[8], uint32_t Y[8], uint32_t scalar[8]) -{ - uint32_t X1[8] = {0}; - uint32_t Y1[8] = {0}; - toMontgomery_ECC_P256(X1, X); - toMontgomery_ECC_P256(Y1, Y); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - - Jac_scalar_multiplication( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - scalar, NISTp256, NISTp256_q); - - Jac_toAffine( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - - /* Montgomery to Normal */ - /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ - uint32_t one[(kCASPER_ECC_P256_wordlen + 4U)] = {0x0}; - one[0] = 0x1u; - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - one, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - - /* copy out to result */ - CASPER_MEMCPY( - resX, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - resY, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP256R1_MulAdd(CASPER_Type *base, - uint32_t resX[8], - uint32_t resY[8], - uint32_t X1[8], - uint32_t Y1[8], - uint32_t scalar1[8], - uint32_t X2[8], - uint32_t Y2[8], - uint32_t scalar2[8]) -{ - uint32_t zeroes[(kCASPER_ECC_P256_wordlen + 4U)] = {0}; - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - X2, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - Y2, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - - toMontgomery_ECC_P256( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - toMontgomery_ECC_P256( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - toMontgomery_ECC_P256( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - toMontgomery_ECC_P256( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); - double_scalar_multiplication( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - scalar1, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - scalar2); - - Jac_toAffine( - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - - uint32_t one[(kCASPER_ECC_P256_wordlen + 4U)] = {0x0}; - one[0] = 0x1u; - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - one, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - - CASPER_MEMCPY(resX, - (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(resY, - (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP384R1_Mul( - CASPER_Type *base, uint32_t resX[12], uint32_t resY[12], uint32_t X[12], uint32_t Y[12], uint32_t scalar[12]) -{ - uint32_t X1[12] = {0}; - uint32_t Y1[12] = {0}; - toMontgomery_ECC_P384(X1, X); - toMontgomery_ECC_P384(Y1, Y); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - - Jac_scalar_multiplication( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - scalar, NISTp384, NISTp384_q); - - Jac_toAffine( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - - /* Montgomery to Normal */ - /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ - uint32_t one[12] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - one, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - - /* copy out to result */ - CASPER_MEMCPY( - resX, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - resY, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base, - uint32_t resX[12], - uint32_t resY[12], - uint32_t X1[12], - uint32_t Y1[12], - uint32_t scalar1[12], - uint32_t X2[12], - uint32_t Y2[12], - uint32_t scalar2[12]) -{ - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - X2, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - Y2, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - - toMontgomery_ECC_P384( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - toMontgomery_ECC_P384( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - toMontgomery_ECC_P384( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - toMontgomery_ECC_P384( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - - double_scalar_multiplication( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - scalar1, - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - scalar2); - - Jac_toAffine( - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - - uint32_t one[12] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; - CASPER_MEMCPY( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - one, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], - &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - - CASPER_MEMCPY(resX, - (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + - 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(resY, - (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + - 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP521R1_Mul( - CASPER_Type *base, uint32_t resX[18], uint32_t resY[18], uint32_t X[18], uint32_t Y[18], uint32_t scalar[18]) -{ - uint32_t X1[18] = {0}; - uint32_t Y1[18] = {0}; - toMontgomery_ECC_P521(X1, X); - toMontgomery_ECC_P521(Y1, Y); - - CASPER_MEMCPY( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - - Jac_scalar_multiplication( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 7U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 8U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - scalar, NISTp521, NISTp521_q); - - Jac_toAffine( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 7U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 8U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - - /* Montgomery to Normal */ - /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ - uint32_t one[18] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; - CASPER_MEMCPY( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - one, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - - /* copy out to result */ - CASPER_MEMCPY( - resX, - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - resY, - &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + - 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP521R1_MulAdd(CASPER_Type *base, - uint32_t resX[18], - uint32_t resY[18], - uint32_t X1[18], - uint32_t Y1[18], - uint32_t scalar1[18], - uint32_t X2[18], - uint32_t Y2[18], - uint32_t scalar2[18]) -{ - uint32_t zeroes[(kCASPER_ECC_P521_wordlen + 4U)] = {0}; - - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - X1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - Y1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - X2, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - Y2, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - - toMontgomery_ECC_P521( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - toMontgomery_ECC_P521( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - toMontgomery_ECC_P521( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - toMontgomery_ECC_P521( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - zeroes, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); - double_scalar_multiplication( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - scalar1, - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - scalar2); - - Jac_toAffine( - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - - uint32_t one[(kCASPER_ECC_P521_wordlen + 4U)] = {0x0}; - one[0] = 0x1u; - CASPER_MEMCPY( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - one, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); - multiply_casper( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - multiply_casper( - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + - 2U * ((uint32_t)(uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], - &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); - - CASPER_MEMCPY( - resX, - (&CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY( - resY, - (&CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]), - (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); -} - -// CIOS Multiply. This is the Coarse Integrated form where the values are -// multiplied and reduced for each step of "i". This uses less memory and -// is faster as a result. Note that this is used to square as well as mul, -// so not as fast as pure squaring could be. -static void MultprecCiosMul_ct( - uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np) -{ - uint32_t j; - uint64_t *m64 = (uint64_t *)(uintptr_t)&msg_ret[kCASPER_RamOffset_M64]; - uint64_t Np64; - uint64_t carry; - uint64_t *a64, *b64, *w64, *N64; - uint32_t *T1 = &CASPER_MEM[0], borrow; - - Np64 = *(uint64_t *)(uintptr_t)Np; - - a64 = (uint64_t *)(uintptr_t)a; - b64 = (uint64_t *)(uintptr_t)b; - w64 = (uint64_t *)(uintptr_t)w_out; - N64 = (uint64_t *)(uintptr_t)Nmod; - - if (a != NULL) - { /* if !a, we are reducing only */ - PreZeroW(j, w_out); - } - SET_DWORD(&w64[N_dwordlen], 0ULL); - SET_DWORD(&w64[N_dwordlen + 1U], 0ULL); - /* with accelerator */ - - /* loop j and then reduce after each j round */ - for (j = 0; j < N_dwordlen; j++) - { - /* Step 3. Iterate over N words of u using j - perform Multiply-accumulate */ - /* push-pull: we do a*b and then separately m*n (reduce) */ - if (a != NULL) - { /* if mul&reduce vs. reduce only */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(&b64[j]), CA_MK_OFF(a64)); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); - Accel_done(); - /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ - /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ - /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ - /* w64[N_dwordlen+1] = g_carry; */ - carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); - SET_DWORD(&w64[N_dwordlen + 1U], carry); - } - SET_DWORD(&m64[0], GET_DWORD(&w64[0]) * Np64); /* prime for 1st; modulo a double-word */ - - /* we are reducing, so the 1st [0th] 64 bit value product is tossed, but we */ - /* need its carry. We let the accel do this separately - really need a mode to */ - /* do this "reduce" since it is natural */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(m64), CA_MK_OFF(&N64[0])); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(&w64[0]))); - Accel_done(); - carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); - - Accel_SetABCD_Addr(CA_MK_OFF(&w64[1]), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpCopy, CA_MK_OFF(&w64[0]))); - - Accel_done(); - SET_DWORD(&w64[N_dwordlen], (GET_DWORD(&w64[N_dwordlen + 1U]) + carry)); - } - - /* now check if need to subtract Nmod */ - CASPER_MEMCPY_I2I(T1, w_out, (N_wordlen + 1U) * sizeof(uint32_t)); - - /* Compute w = w - N */ - Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(w_out))); - Accel_done(); - - // if w_out > T1 then there was a borrow - borrow = (uint32_t)(GET_WORD(&((uint32_t *)w_out)[N_wordlen]) > GET_WORD(&T1[N_wordlen])); - - SET_WORD(&w_out[N_wordlen + 1U], 0); - SET_WORD(&w_out[N_wordlen], 0); - casper_select(w_out, w_out, T1, (int32_t)borrow, (int16_t)(uint16_t)N_wordlen); -} - -/* Compute C = A - B % mod - * Assumes all operand have two extra limbs to store carry. - */ -static void CASPER_montsub(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod) -{ - uint64_t *b64, *c64, *m64, *tmp; - int borrow; - - b64 = (uint64_t *)(uintptr_t)B; - c64 = (uint64_t *)(uintptr_t)C; - m64 = (uint64_t *)(uintptr_t)mod; - - tmp = (uint64_t *)(uintptr_t)&CASPER_MEM[0]; - - CASPER_MEMCPY(tmp, A, N_wordlen * sizeof(uint32_t)); - - /* Compute tmp = A - B. */ - Accel_SetABCD_Addr(CA_MK_OFF(b64), 0); - - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(tmp))); - Accel_done(); - - borrow = (int32_t)((GET_WORD(&((uint32_t *)(uintptr_t)tmp)[N_wordlen - 1U])) > GET_WORD(&A[N_wordlen - 1U])); - CASPER_MEMCPY(c64, tmp, N_wordlen * sizeof(uint32_t)); - - /* Compute C = Mod + tmp */ - Accel_SetABCD_Addr(CA_MK_OFF(m64), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpAdd64, CA_MK_OFF(c64))); - Accel_done(); - - casper_select(C, (uint32_t *)(uintptr_t)tmp, C, borrow, (int16_t)(uint16_t)N_wordlen); -} - -/* Compute C = A + B % mod - * Assumes all operand have two extra limbs to store carry. - */ -static void CASPER_montadd(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod) -{ - uint64_t *b64, *c64, *m64, *tmp; - int borrow; - - b64 = (uint64_t *)(uintptr_t)B; - c64 = (uint64_t *)(uintptr_t)C; - m64 = (uint64_t *)(uintptr_t)mod; - - tmp = (uint64_t *)(uintptr_t)&CASPER_MEM[0]; - - CASPER_MEMCPY(tmp, A, N_wordlen * sizeof(uint32_t)); - SET_DWORD(&tmp[N_wordlen / 2U], 0ULL); - SET_DWORD(&b64[N_wordlen / 2U], 0ULL); - SET_DWORD(&m64[N_wordlen / 2U], 0ULL); - - /* Compute tmp = A + B using one additonal double-length limb. */ - Accel_SetABCD_Addr(CA_MK_OFF(b64), 0); - - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U, (uint32_t)kCASPER_OpAdd64, CA_MK_OFF(tmp))); - Accel_done(); - - CASPER_MEMCPY(c64, tmp, (N_wordlen + 2U) * sizeof(uint32_t)); - - /* Compute C = Mod - tmp */ - Accel_SetABCD_Addr(CA_MK_OFF(m64), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(c64))); - Accel_done(); - - // borrow = g_carry; - borrow = (int32_t)(GET_WORD(&C[N_wordlen]) > GET_WORD(&(((uint32_t *)(uintptr_t)tmp)[N_wordlen]))); - casper_select(C, C, (uint32_t *)(uintptr_t)tmp, borrow, (int16_t)(uint16_t)N_wordlen); -} - -/* Compute c = a/2 mod p where b is scratch space. */ -static void CASPER_half(uint32_t *c, uint32_t *a, uint32_t *b) -{ - shiftright(b, a, 1U); /* Compute a/2 and (a+p)/2 */ - - /* Compute tmp = a + p using one additonal double-length limb. */ - CASPER_MEMCPY(c, a, N_wordlen * sizeof(uint32_t)); - SET_WORD(&c[N_wordlen], 0); - SET_WORD(&c[N_wordlen + 1U], 0U); - - Accel_SetABCD_Addr(CA_MK_OFF(((uint64_t *)(uintptr_t)&CASPER_MEM[(N_wordlen + 4U)])), 0); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_wordlen / 2U, (uint32_t)kCASPER_OpAdd64, CA_MK_OFF(((uint64_t *)(uintptr_t)c)))); - Accel_done(); - - shiftright(c, c, 1U); - SET_WORD(&c[N_wordlen - 1U], GET_WORD(&c[N_wordlen - 1U]) | (GET_WORD(&c[N_wordlen]) << 31)); - SET_WORD(&c[N_wordlen], 0U); - casper_select(c, b, c, (int32_t)(uint32_t)(GET_WORD(&a[0]) & 1U), (int16_t)(uint16_t)(N_wordlen)); -} - -static uint32_t casper_get_word(uint32_t *addr) -{ - return GET_WORD(addr); -} - -/* Shift right by 1 <= c <= 31. z[] and x[] in system RAM, no interleaving macros used. */ -static void shiftrightSysram(uint32_t *z, uint32_t *x, uint32_t c) -{ - z[0] = (x[1] << (32U - (c))) | (x[0] >> (c)); - z[1] = (x[2] << (32U - (c))) | (x[1] >> (c)); - z[2] = (x[3] << (32U - (c))) | (x[2] >> (c)); - z[3] = (x[4] << (32U - (c))) | (x[3] >> (c)); - z[4] = (x[5] << (32U - (c))) | (x[4] >> (c)); - z[5] = (x[6] << (32U - (c))) | (x[5] >> (c)); - z[6] = (x[7] << (32U - (c))) | (x[6] >> (c)); - - if (N_wordlen == 18U) - { - z[7] = (x[8] << (32U - (c))) | (x[7] >> (c)); - z[8] = (x[9] << (32U - (c))) | (x[8] >> (c)); - z[9] = (x[10] << (32U - (c))) | (x[9] >> (c)); - z[10] = (x[11] << (32U - (c))) | (x[10] >> (c)); - z[11] = (x[12] << (32U - (c))) | (x[11] >> (c)); - z[12] = (x[13] << (32U - (c))) | (x[12] >> (c)); - z[13] = (x[14] << (32U - (c))) | (x[13] >> (c)); - z[14] = (x[15] << (32U - (c))) | (x[14] >> (c)); - z[15] = (x[16] << (32U - (c))) | (x[15] >> (c)); - z[16] = (x[17] << (32U - (c))) | (x[16] >> (c)); - z[17] = (x[17] >> (c)); - } - - if (N_wordlen == 12U) - { - z[7] = (x[8] << (32U - (c))) | (x[7] >> (c)); - z[8] = (x[9] << (32U - (c))) | (x[8] >> (c)); - z[9] = (x[10] << (32U - (c))) | (x[9] >> (c)); - z[10] = (x[11] << (32U - (c))) | (x[10] >> (c)); - z[11] = (x[11] >> (c)); - } - if (N_wordlen == 8U) - { - z[7] = (x[7] >> (c)); - } -} -/* Shift right by 1 <= c <= 31. */ -static void shiftright(uint32_t *z, uint32_t *x, uint32_t c) -{ - SET_WORD(&z[0], (GET_WORD(&x[1]) << (32U - (c))) | (GET_WORD(&x[0]) >> (c))); - SET_WORD(&z[1], (GET_WORD(&x[2]) << (32U - (c))) | (GET_WORD(&x[1]) >> (c))); - SET_WORD(&z[2], (GET_WORD(&x[3]) << (32U - (c))) | (GET_WORD(&x[2]) >> (c))); - SET_WORD(&z[3], (GET_WORD(&x[4]) << (32U - (c))) | (GET_WORD(&x[3]) >> (c))); - SET_WORD(&z[4], (GET_WORD(&x[5]) << (32U - (c))) | (GET_WORD(&x[4]) >> (c))); - SET_WORD(&z[5], (GET_WORD(&x[6]) << (32U - (c))) | (GET_WORD(&x[5]) >> (c))); - SET_WORD(&z[6], (GET_WORD(&x[7]) << (32U - (c))) | (GET_WORD(&x[6]) >> (c))); - - if (N_wordlen == 18U) - { - SET_WORD(&z[7], (GET_WORD(&x[8]) << (32U - (c))) | (GET_WORD(&x[7]) >> (c))); - SET_WORD(&z[8], (GET_WORD(&x[9]) << (32U - (c))) | (GET_WORD(&x[8]) >> (c))); - SET_WORD(&z[9], (GET_WORD(&x[10]) << (32U - (c))) | (GET_WORD(&x[9]) >> (c))); - SET_WORD(&z[10], (GET_WORD(&x[11]) << (32U - (c))) | (GET_WORD(&x[10]) >> (c))); - SET_WORD(&z[11], (GET_WORD(&x[12]) << (32U - (c))) | (GET_WORD(&x[11]) >> (c))); - SET_WORD(&z[12], (GET_WORD(&x[13]) << (32U - (c))) | (GET_WORD(&x[12]) >> (c))); - SET_WORD(&z[13], (GET_WORD(&x[14]) << (32U - (c))) | (GET_WORD(&x[13]) >> (c))); - SET_WORD(&z[14], (GET_WORD(&x[15]) << (32U - (c))) | (GET_WORD(&x[14]) >> (c))); - SET_WORD(&z[15], (GET_WORD(&x[16]) << (32U - (c))) | (GET_WORD(&x[15]) >> (c))); - SET_WORD(&z[16], (GET_WORD(&x[17]) << (32U - (c))) | (GET_WORD(&x[16]) >> (c))); - SET_WORD(&z[17], (GET_WORD(&x[17]) >> (c))); - } - if (N_wordlen == 12U) - { - SET_WORD(&z[7], (GET_WORD(&x[8]) << (32U - (c))) | (GET_WORD(&x[7]) >> (c))); - SET_WORD(&z[8], (GET_WORD(&x[9]) << (32U - (c))) | (GET_WORD(&x[8]) >> (c))); - SET_WORD(&z[9], (GET_WORD(&x[10]) << (32U - (c))) | (GET_WORD(&x[9]) >> (c))); - SET_WORD(&z[10], (GET_WORD(&x[11]) << (32U - (c))) | (GET_WORD(&x[10]) >> (c))); - SET_WORD(&z[11], (GET_WORD(&x[11]) >> (c))); - } - if (N_wordlen == 8U) - { - SET_WORD((&z[7]), (GET_WORD(&x[7]) >> (c))); - } -} -/* Shift left by 1 <= c <= 31. */ -static void shiftleft(uint32_t *z, uint32_t *x, uint32_t c) -{ - if (N_wordlen == 18U) - { - SET_WORD(&z[17], (GET_WORD(&x[17]) << (c)) | GET_WORD(&z[16]) >> (32U - (c))); - SET_WORD(&z[16], (GET_WORD(&x[16]) << (c)) | GET_WORD(&z[15]) >> (32U - (c))); - SET_WORD(&z[15], (GET_WORD(&x[15]) << (c)) | GET_WORD(&z[14]) >> (32U - (c))); - SET_WORD(&z[14], (GET_WORD(&x[14]) << (c)) | GET_WORD(&z[13]) >> (32U - (c))); - SET_WORD(&z[13], (GET_WORD(&x[13]) << (c)) | GET_WORD(&z[12]) >> (32U - (c))); - SET_WORD(&z[12], (GET_WORD(&x[12]) << (c)) | GET_WORD(&z[11]) >> (32U - (c))); - SET_WORD(&z[11], (GET_WORD(&x[11]) << (c)) | GET_WORD(&z[10]) >> (32U - (c))); - SET_WORD(&z[10], (GET_WORD(&x[10]) << (c)) | GET_WORD(&z[9]) >> (32U - (c))); - SET_WORD(&z[9], (GET_WORD(&x[9]) << (c)) | GET_WORD(&z[8]) >> (32U - (c))); - SET_WORD(&z[8], (GET_WORD(&x[8]) << (c)) | GET_WORD(&z[7]) >> (32U - (c))); - } - if (N_wordlen == 12U) - { - SET_WORD(&z[11], (GET_WORD(&x[11]) << (c)) | GET_WORD(&z[10]) >> (32U - (c))); - SET_WORD(&z[10], (GET_WORD(&x[10]) << (c)) | GET_WORD(&z[9]) >> (32U - (c))); - SET_WORD(&z[9], (GET_WORD(&x[9]) << (c)) | GET_WORD(&z[8]) >> (32U - (c))); - SET_WORD(&z[8], (GET_WORD(&x[8]) << (c)) | GET_WORD(&z[7]) >> (32U - (c))); - } - SET_WORD(&z[7], (GET_WORD(&x[7]) << (c)) | GET_WORD(&z[6]) >> (32U - (c))); - SET_WORD(&z[6], (GET_WORD(&x[6]) << (c)) | GET_WORD(&z[5]) >> (32U - (c))); - SET_WORD(&z[5], (GET_WORD(&x[5]) << (c)) | GET_WORD(&z[4]) >> (32U - (c))); - SET_WORD(&z[4], (GET_WORD(&x[4]) << (c)) | GET_WORD(&z[3]) >> (32U - (c))); - SET_WORD(&z[3], (GET_WORD(&x[3]) << (c)) | GET_WORD(&z[2]) >> (32U - (c))); - SET_WORD(&z[2], (GET_WORD(&x[2]) << (c)) | GET_WORD(&z[1]) >> (32U - (c))); - SET_WORD(&z[1], (GET_WORD(&x[1]) << (c)) | GET_WORD(&z[0]) >> (32U - (c))); - SET_WORD(&z[0], (GET_WORD(&x[0]) << (c))); -} - -static void multiply_casper(uint32_t w_out[], const uint32_t a[], const uint32_t b[]) -{ - uint32_t *Np; - - if (N_wordlen == 8U) - { - Np = Np256; - MultprecCiosMul_ct(w_out, a, b, &CASPER_MEM[(N_wordlen + 4U)], Np); - } - if (N_wordlen == 12U) - { - Np = Np384; - MultprecCiosMul_ct(w_out, a, b, &CASPER_MEM[(N_wordlen + 4U)], Np); - } - - if (N_wordlen == 18U) - { - Np = Np521; - MultprecCiosMul521_ct(w_out, a, b, &CASPER_MEM[(N_wordlen + 4U)], Np); - } -} -/* Convert a projective point (X1 : Y1 : Z1) - * to the affine point (X3, Y3) = (X1/Z1^2,Y1/Z1^3) - * The memory of (X3, Y3) and (X1 : Y1 : Z1) should not overlap - */ -void Jac_toAffine(uint32_t *X3, uint32_t *Y3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1) -{ - uint32_t *T1, *T2; - - T1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; - T2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; - - square_casper(T1, Z1); // Z^2 - multiply_casper(T2, T1, Z1); // Z^3 - - // Montgomery inverse - if (N_wordlen == 8U) - { - invert_mod_p256(T1, T2); - } - - if (N_wordlen == 12U) - { - invert_mod_p384(T1, T2); - } - - if (N_wordlen == 18U) - { - invert_mod_p521(T1, T2); - } - - multiply_casper(Y3, Y1, T1); // Y3 = Y/Z^3 - multiply_casper(T2, T1, Z1); // Z^-2 - multiply_casper(X3, X1, T2); // X3 = X/Z^2 -} - -/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2 : Y2 : Z2) - * where (X1: Y1: Z1) != (X2 : Y2 : Z2) - * (X3 : Y3: Z3) may be the same as one of the inputs. - */ -void Jac_addition(uint32_t *X3, - uint32_t *Y3, - uint32_t *Z3, - uint32_t *X1, - uint32_t *Y1, - uint32_t *Z1, - uint32_t *X2, - uint32_t *Y2, - uint32_t *Z2) -{ - uint32_t *Z1Z1, *Z2Z2, *U1, *S1, *J, *H, *V, *t0, *t1; - int m1, m2; - - Z1Z1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; - Z2Z2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; - U1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 2U * (N_wordlen + 4U)]; - S1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 3U * (N_wordlen + 4U)]; - J = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 4U * (N_wordlen + 4U)]; - H = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 5U * (N_wordlen + 4U)]; - V = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 6U * (N_wordlen + 4U)]; - t0 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 7U * (N_wordlen + 4U)]; - t1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 8U * (N_wordlen + 4U)]; - - CASPER_ECC_equal_to_zero(&m1, Z1); - CASPER_ECC_equal_to_zero(&m2, Z2); - if (m1 == 0) - { - CASPER_MEMCPY(X3, X2, N_wordlen * 4U); - CASPER_MEMCPY(Y3, Y2, N_wordlen * 4U); - CASPER_MEMCPY(Z3, Z2, N_wordlen * 4U); - return; - } - if (m2 == 0) - { - CASPER_MEMCPY(X3, X1, N_wordlen * 4U); - CASPER_MEMCPY(Y3, Y1, N_wordlen * 4U); - CASPER_MEMCPY(Z3, Z1, N_wordlen * 4U); - return; - } - - square_casper(Z1Z1, Z1); - square_casper(Z2Z2, Z2); - multiply_casper(U1, X1, Z2Z2); - multiply_casper(H, X2, Z1Z1); /* if H equals U1 then X's are the same */ - multiply_casper(t0, Z2, Z2Z2); - multiply_casper(S1, Y1, t0); - multiply_casper(t0, Z1, Z1Z1); - multiply_casper(J, Y2, t0); /* if (S1 == J) then Y's are the same */ - - CASPER_ECC_equal(&m1, H, U1); /* If H and U1 match then the X-coordinates are the same. */ - CASPER_ECC_equal(&m2, S1, J); /* If S1 and J match then the Y-coordinates are the same. */ - if (m1 == 0) - { - if (m2 == 0) - { - Jac_double(X3, Y3, Z3, X1, Y1, Z1); - return; - } - /* else { - We work with the point at infinity. - The Z-coordinate will be set to zero in this function. - } */ - } - - sub_casper(H, H, U1); - mul2_casper(t0, H); - square_casper(t1, t0); - sub_casper(t0, J, S1); - multiply_casper(J, H, t1); - multiply_casper(V, U1, t1); - mul2_casper(U1, t0); - square_casper(t0, U1); - mul2_casper(t1, V); - sub_casper(t0, t0, J); - sub_casper(X3, t0, t1); - sub_casper(t0, V, X3); - multiply_casper(t1, S1, J); - mul2_casper(t1, t1); - multiply_casper(V, U1, t0); - sub_casper(Y3, V, t1); - add_casper(V, Z1, Z2); - square_casper(t1, V); - sub_casper(t1, t1, Z1Z1); - sub_casper(t1, t1, Z2Z2); - multiply_casper(Z3, t1, H); -} - -/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2, Y2) - * where (X1: Y1: Z1) != (X2, Y2) - * (X3 : Y3: Z3) may not overlap with (X1: Y1: Z1). - * Source: 2004 Hankerson?Menezes?Vanstone, page 91. - */ -void Jac_add_affine( - uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *X2, uint32_t *Y2) -{ - uint32_t *T1, *T2, *T3, *T4, *T5; - uint32_t *ONE = NULL; - int m1, m2; - - if (N_wordlen == 8U) - { - ONE = NISTr256; - } - if (N_wordlen == 12U) - { - ONE = NISTr384; - } - if (N_wordlen == 18U) - { - ONE = NISTr521; - } - - T1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; - T2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; - T3 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 2U * (N_wordlen + 4U)]; - T4 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 3U * (N_wordlen + 4U)]; - T5 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 4U * (N_wordlen + 4U)]; - - CASPER_ECC_equal_to_zero(&m1, Z1); - if (m1 == 0) - { - CASPER_MEMCPY(X3, X2, N_wordlen * 4U); - CASPER_MEMCPY(Y3, Y2, N_wordlen * 4U); - CASPER_MEMCPY(Z3, ONE, N_wordlen * 4U); - return; - } - - CASPER_MEMCPY(T5, Z1, N_wordlen * sizeof(uint32_t)); - square_casper(T3, Z1); - multiply_casper(T2, T3, Z1); - multiply_casper(T4, T3, X2); - multiply_casper(T3, T2, Y2); - - CASPER_ECC_equal(&m1, T4, X1); - CASPER_ECC_equal(&m2, T3, Y1); - if (m1 == 0) - { - if (m2 == 0) - { - Jac_double(X3, Y3, Z3, X1, Y1, Z1); - return; - } - /* else { - We work with the point at infinity. - The Z-coordinate will be set to zero in this function. - } */ - } - - sub_casper(T1, T4, X1); - sub_casper(T2, T3, Y1); - multiply_casper(Z3, T5, T1); - square_casper(T3, T1); - multiply_casper(T4, T3, T1); - multiply_casper(T5, T3, X1); - mul2_casper(T1, T5); - square_casper(X3, T2); - sub_casper(X3, X3, T1); - sub_casper(X3, X3, T4); - sub_casper(T3, T5, X3); - multiply_casper(T1, T3, T2); - multiply_casper(T2, T4, Y1); - sub_casper(Y3, T1, T2); -} - -static uint32_t casper_get_word(uint32_t *addr); - -/* Point doubling from: 2004 Hankerson?Menezes?Vanstone, page 91. - * Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X1 : Y1 : Z1) - * (X3 : Y3: Z3) may be the same as the input. - */ -void Jac_double(uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1) -{ - uint32_t *T1, *T2, *T3, *T4, *T5; - - T1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; - T2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; - T3 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 2U * (N_wordlen + 4U)]; - T4 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 3U * (N_wordlen + 4U)]; - T5 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 4U * (N_wordlen + 4U)]; - - square_casper(T1, Z1); - sub_casper(T3, X1, T1); - add_casper(T1, X1, T1); - multiply_casper(T4, T3, T1); - - mul2_casper(T3, T4); - - add_casper(T2, T3, T4); - - mul2_casper(Y3, Y1); - - CASPER_MEMCPY(T5, Z1, N_wordlen * sizeof(uint32_t)); - multiply_casper(Z3, Y3, T5); - - square_casper(T5, Y3); - - multiply_casper(T3, T5, X1); - - square_casper(Y3, T5); - - half(T5, Y3, T4); - - square_casper(X3, T2); - - mul2_casper(T1, T3); - - sub_casper(X3, X3, T1); - - sub_casper(T1, T3, X3); - - multiply_casper(T3, T1, T2); - - sub_casper(Y3, T3, T5); -} - -/* Recoding for a signed fixed window. - * Source: https://eprint.iacr.org/2014/130.pdf, Algorithm 6 - * Recode the n-bit integer k into ciel(log2(n)/(w-1)) digits - * where each digit is in - * { +/- 1, +/- 3, ..., +/- 2^(w-1)-1 } - * and put the result in c. - */ -static void recode(int8_t *c, uint32_t *k, int n, int w) -{ - int i, t; - uint32_t K[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; - (void)memcpy(K, k, (size_t)ceil(((float)n / 8.))); - t = (n + (w - 2)) / (w - 1); - for (i = 0; i < t; i++) - { - c[i] = (int8_t)(uint8_t)((K[0] & ((uint32_t)(uint32_t)(1UL << (uint32_t)w) - 1UL)) - - (uint32_t)(uint32_t)(1UL << ((uint32_t)w - 1UL))); - shiftrightSysram(K, K, (unsigned)w - 1U); - (void)add_n_1(K, K, (uint32_t)c[i] >> 31, (int16_t)(uint16_t)N_wordlen); - } - c[t] = (int8_t)K[0]; -} - -static uint32_t sub_n(uint32_t *c, uint32_t *a, uint32_t *b, int n) -{ - int i; - uint32_t borrow; - sub_borrowout(borrow, GET_WORD(&c[0]), a[0], GET_WORD(&b[0])); - for (i = 1; i < n; i++) - { - sub_borrowin_borrowout(borrow, GET_WORD(&c[i]), a[i], GET_WORD(&b[i]), borrow); - } - return borrow; -} - -#if 0 -/* Dumb n-limb subtraction of c=a-b, return borrow. */ -static uint32_t sub_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n) { - int i; - uint32_t borrow; - sub_borrowout(borrow, c[0], a[0], b); - for (i = 1; i < n; i++) { - sub_borrowin_borrowout_1(borrow, c[i], a[i], borrow); - } - return borrow; -} - -/* Dumb n-limb addition of c=a+b, return carry. */ -static uint32_t add_n(uint32_t *c, uint32_t *a, uint32_t *b, int n) { - int i; - uint32_t carry; - add_cout(carry, c[0], a[0], b[0]); - for (i = 1; i < n; i++) { - add_cout_cin(carry, c[i], a[i], b[i], carry); - } - return carry; -} -#endif - -/* Dumb n-limb addition of c=a+b, return carry. */ -static uint32_t add_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n) -{ - int i; - uint32_t carry; - add_cout(carry, c[0], a[0], b); - for (i = 1; i < n; i++) - { - add_cout_cin(carry, c[i], a[i], 0U, carry); - } - return carry; -} - -static uint8_t int8abs(int8_t v) -{ - return ((v < 0) ? ((uint8_t)-v) : ((uint8_t)v)); -} - -/* Constant time elliptic curve scalar multiplication. - * Source: https://eprint.iacr.org/2014/130.pdf - * when using w = 4. - * Computes (X3 : Y3 : Z3) = k * (X1, Y1) \in E(F_p) - * p is the prime used to define the finite field F_p - * q is the (prime) order of the curve - */ -void Jac_scalar_multiplication( - uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *k, uint32_t *p, uint32_t *q) -{ - uint32_t *scalar, *M, *X, *Y, *Z, *mem; - uint32_t *ONE = NULL; - int i, sign, odd; - uint8_t index; - size_t recodeLength = 175u; - size_t bitlen = 0u; - int8_t rec[CASPER_RECODE_LENGTH_MAX] = {0}; - - if (N_wordlen == 8U) - { - recodeLength = (size_t)kCASPER_ECC_P256_recode_len; - bitlen = (size_t)kCASPER_ECC_P256_N_bitlen; - ONE = NISTr256; - } - - if (N_wordlen == 12U) - { - recodeLength = (size_t)kCASPER_ECC_P384_recode_len; - bitlen = (size_t)kCASPER_ECC_P384_N_bitlen; - ONE = NISTr384; - } - - if (N_wordlen == 18U) - { - recodeLength = (size_t)kCASPER_ECC_P521_recode_len; - bitlen = (size_t)521U; - ONE = NISTr521; - } - - /* Point to the start of the LUT table space. */ - mem = &CASPER_MEM[(20U * N_wordlen + 80U)]; - - scalar = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * (N_wordlen + 4U)]; - X = &CASPER_MEM[(20U * N_wordlen + 80U) + 13U * (N_wordlen + 4U)]; - Y = &CASPER_MEM[(20U * N_wordlen + 80U) + 14U * (N_wordlen + 4U)]; - Z = &CASPER_MEM[(20U * N_wordlen + 80U) + 15U * (N_wordlen + 4U)]; - M = &CASPER_MEM[(20U * N_wordlen + 80U) + 16U * (N_wordlen + 4U)]; - - /* Point to memory the recoded scalar. - */ - CASPER_MEMCPY(scalar, k, sizeof(uint32_t) * N_wordlen); - -/* Precomputation: compute 1*P, 3*P, 5*P, and 7*P */ -#define FSL_CASPER_LUT(P, x) (mem + (3U * ((P)-1U) / 2U + (x)) * (N_wordlen + 4U)) - - /* Set 1*P */ - CASPER_MEMCPY(Z3, ONE, N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(FSL_CASPER_LUT(1U, 0U), X1, N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(FSL_CASPER_LUT(1U, 1U), Y1, N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(FSL_CASPER_LUT(1U, 2U), Z3, N_wordlen * sizeof(uint32_t)); - - /* Compute 2*P */ - Jac_double(X3, Y3, Z3, X1, Y1, Z3); - - /* Compute 3*P = 2P + P */ - Jac_add_affine(FSL_CASPER_LUT(3U, 0U), FSL_CASPER_LUT(3U, 1U), FSL_CASPER_LUT(3U, 2U), X3, Y3, Z3, X1, Y1); - - /* Compute 5*P = 3P + 2P */ - Jac_addition(FSL_CASPER_LUT(5U, 0U), FSL_CASPER_LUT(5U, 1U), FSL_CASPER_LUT(5U, 2U), FSL_CASPER_LUT(3U, 0U), - FSL_CASPER_LUT(3U, 1U), FSL_CASPER_LUT(3U, 2U), X3, Y3, Z3); - - /* Compute 7*P = 5P + 2P */ - Jac_addition(FSL_CASPER_LUT(7U, 0U), FSL_CASPER_LUT(7U, 1U), FSL_CASPER_LUT(7U, 2U), FSL_CASPER_LUT(5U, 0U), - FSL_CASPER_LUT(5U, 1U), FSL_CASPER_LUT(5U, 2U), X3, Y3, Z3); - - /* Recode the scalar */ - odd = (int32_t)((uint32_t)(casper_get_word(&scalar[0]) & 1U)); - (void)sub_n(M, q, scalar, (int16_t)(uint16_t)N_wordlen); // todo!!! - casper_select(scalar, M, scalar, odd, (int16_t)(uint16_t)N_wordlen); - - /* Use n=384 and w=4 --> compute ciel(384/3) = 128 + 1 digits */ - uint32_t scalarSysram[CASPER_MAX_ECC_SIZE_WORDLEN]; - CASPER_MEMCPY(scalarSysram, scalar, /*CASPER_*/ N_wordlen * sizeof(uint32_t)); - recode(rec, scalarSysram, (int32_t)bitlen, 4); - - /* Set the first value. */ - index = int8abs(rec[recodeLength - 1U]); - sign = (int32_t)(uint32_t)(uint8_t)(((uint8_t)rec[recodeLength - 1U]) >> 7); - - CASPER_MEMCPY(X3, FSL_CASPER_LUT((uint32_t)index, 0U), N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Y3, FSL_CASPER_LUT((uint32_t)index, 1U), N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Z3, FSL_CASPER_LUT((uint32_t)index, 2U), N_wordlen * sizeof(uint32_t)); - - /* Get the correct LUT element in constant time by touching - * all elements and masking out the correct one. - */ - -#define GET_LUT(x, y, z, index) \ - do \ - { \ - int m; \ - CASPER_MEMCPY((x), FSL_CASPER_LUT(1U, 0U), N_wordlen * sizeof(uint32_t)); \ - CASPER_MEMCPY((y), FSL_CASPER_LUT(1U, 1U), N_wordlen * sizeof(uint32_t)); \ - CASPER_MEMCPY((z), FSL_CASPER_LUT(1U, 2U), N_wordlen * sizeof(uint32_t)); \ - m = (int32_t)((index) == 3U); \ - casper_select((x), (x), FSL_CASPER_LUT(3U, 0U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((y), (y), FSL_CASPER_LUT(3U, 1U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((z), (z), FSL_CASPER_LUT(3U, 2U), m, (int16_t)(uint16_t)N_wordlen); \ - m = (int32_t)((index) == 5U); \ - casper_select((x), (x), FSL_CASPER_LUT(5U, 0U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((y), (y), FSL_CASPER_LUT(5U, 1U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((z), (z), FSL_CASPER_LUT(5U, 2U), m, (int16_t)(uint16_t)N_wordlen); \ - m = (int32_t)((index) == 7U); \ - casper_select((x), (x), FSL_CASPER_LUT(7U, 0U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((y), (y), FSL_CASPER_LUT(7U, 1U), m, (int16_t)(uint16_t)N_wordlen); \ - casper_select((z), (z), FSL_CASPER_LUT(7U, 2U), m, (int16_t)(uint16_t)N_wordlen); \ - } while (false) - - GET_LUT(X3, Y3, Z3, index); - - /* Compute -y and select the positive or negative point. */ - (void)sub_n(M, p, Y3, (int16_t)(uint16_t)N_wordlen); // todo!!! - casper_select(Y3, Y3, M, sign, (int16_t)(uint16_t)N_wordlen); - - for (i = (int)(uint32_t)(recodeLength - 2U); i >= 0; i--) - { - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - - index = int8abs(rec[i]); - sign = (int32_t)(uint32_t)(uint8_t)(((uint8_t)rec[i]) >> 7); - - GET_LUT(X, Y, Z, index); - - /* Compute -y and select the positive or negative point. */ - (void)sub_n(scalar, p, Y, (int16_t)(uint16_t)N_wordlen); // todo!!! - casper_select(scalar, Y, scalar, sign, (int16_t)(uint16_t)N_wordlen); - - Jac_addition(X3, Y3, Z3, X3, Y3, Z3, X, scalar, Z); - } - - (void)sub_n(M, p, Y3, (int16_t)(uint16_t)N_wordlen); // todo!!! - - casper_select(Y3, M, Y3, odd, (int16_t)(uint16_t)N_wordlen); -} - -#undef FSL_CASPER_LUT -#undef GET_LUT - -/* - * Pre-compute the following 16 points: - * 00 00 = 0*P + 0*Q <-- Not needed when using sliding windows - * 00 01 = 0*P + 1*Q <-- Not needed when using sliding windows - * 00 10 = 0*P + 2*Q - * 00 11 = 0*P + 3*Q - * - * 01 00 = 1*P + 0*Q <-- Not needed when using sliding windows - * 01 01 = 1*P + 1*Q <-- Not needed when using sliding windows - * 01 10 = 1*P + 2*Q - * 01 11 = 1*P + 3*Q - * - * 10 00 = 2*P + 0*Q - * 10 01 = 2*P + 1*Q - * 10 10 = 2*P + 2*Q - * 10 11 = 2*P + 3*Q - * - * 11 00 = 3*P + 0*Q - * 11 01 = 3*P + 1*Q - * 11 10 = 3*P + 2*Q - * 11 11 = 3*P + 3*Q - * - * index = (bitsi||bitsj)-2 - (biti != 0)*2 - * - * Input: P = (X1 : Y1 : Z1) and - * Q = (X2 : Y2 : Z2) - * Output: mem, memory location for the LUT. - */ - -static void precompute_double_scalar_LUT16(uint32_t *Px, uint32_t *Py, uint32_t *Qx, uint32_t *Qy) -{ - uint32_t *Q2x, *Q2y, *Q2z, *P2x, *P2y, *P2z, *Z, *mem; - uint32_t *ONE = NULL; - uint32_t index = 0; - - if (N_wordlen == 8U) - { - ONE = NISTr256; - } - - if (N_wordlen == 12U) - { - ONE = NISTr384; - } - - Q2x = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 0U * (N_wordlen + 4U)]; - Q2y = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 1U * (N_wordlen + 4U)]; - Q2z = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 2U * (N_wordlen + 4U)]; - - /* Re-use memory from different scratch space since no - * projective point addition is used below. */ - P2x = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 5U * (N_wordlen + 4U)]; - P2z = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 6U * (N_wordlen + 4U)]; - P2y = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 7U * (N_wordlen + 4U)]; - Z = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 8U * (N_wordlen + 4U)]; - - mem = &CASPER_MEM[(20U * N_wordlen + 80U)]; - - CASPER_MEMCPY(Z, ONE, N_wordlen * sizeof(uint32_t)); - - // 00 10 = 0*P + 2*Q - Jac_double(Q2x, Q2y, Q2z, Qx, Qy, Z); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 00 11 = 0*P + 3*Q - Jac_add_affine(P2x, P2y, P2z, Q2x, Q2y, Q2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 01 10 = 1*P + 2*Q - Jac_add_affine(P2x, P2y, P2z, Q2x, Q2y, Q2z, Px, Py); - CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 01 11 = 1*P + 3*Q - Jac_add_affine(P2x, P2y, P2z, P2x, P2y, P2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 10 00 = 2*P + 0*Q - Jac_double(P2x, P2y, P2z, Px, Py, Z); - CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 10 01 = 2*P + 1*Q - Jac_add_affine(Q2x, Q2y, Q2z, P2x, P2y, P2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 10 10 = 2*P + 2*Q - Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 10 11 = 2*P + 3*Q - Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 11 00 = 3*P + 0*Q - Jac_add_affine(P2x, P2y, P2z, P2x, P2y, P2z, Px, Py); - CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 11 01 = 3*P + 1*Q - Jac_add_affine(Q2x, Q2y, Q2z, P2x, P2y, P2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 11 10 = 3*P + 2*Q - Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 11 11 = 3*P + 3*Q - Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; -} - -/* - * Pre-compute the following 4 points: - * 0 0 = 0*P + 0*Q <-- Not needed when using sliding windows - * 0 1 = 0*P + 1*Q - * - * 1 0 = 1*P + 0*Q - * 1 1 = 1*P + 1*Q - * - * index = (bitsj+1) & (0-bitsi) - * - * Input: P = (X1 : Y1 : Z1) and - * Q = (X2 : Y2 : Z2) - * Output: mem, memory location for the LUT. - */ - -static void precompute_double_scalar_LUT4(uint32_t *Px, uint32_t *Py, uint32_t *Qx, uint32_t *Qy) -{ - uint32_t *Z, *mem, *ONE; - uint32_t index = 0; - - ONE = NISTr521; - - /* Re-use memory from different scratch space since no - * projective point addition is used below. */ - Z = &CASPER_MEM[(11U * N_wordlen + 4U) + 5U * (N_wordlen + 4U)]; - mem = &CASPER_MEM[(20U * N_wordlen + 80U)]; - - CASPER_MEMCPY(Z, ONE, N_wordlen * sizeof(uint32_t)); - - // 0*P + 1*Q - CASPER_MEMCPY(&mem[index], Qx, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Qy, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 1*P + 0*Q - CASPER_MEMCPY(&mem[index], Px, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Py, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - CASPER_MEMCPY(&mem[index], Z, N_wordlen * sizeof(uint32_t)); - index += N_wordlen; - - // 1*P + 1*Q - Jac_add_affine(&mem[index], &mem[index + N_wordlen], &mem[index + 2U * N_wordlen], Px, Py, Z, Qx, Qy); -} - -#define GETLUTX(x) (3U * (x)*N_wordlen) -#define GETLUTY(x) (3U * (x)*N_wordlen + 1U * N_wordlen) -#define GETLUTZ(x) (3U * (x)*N_wordlen + 2U * N_wordlen) - -/* Compute the double scalar multiplication - * (X3 : Y3 : Z3) = k1 * (X1, Y1) + k2 * (X2, Y2) - * Using Shamir's trick and precomputing 16 points. - * This code is *not* constant time since this is used - * for verification only. - */ -void double_scalar_multiplication(uint32_t *X3, - uint32_t *Y3, - uint32_t *Z3, - uint32_t *X1, - uint32_t *Y1, - uint32_t *k1, - uint32_t *X2, - uint32_t *Y2, - uint32_t *k2) -{ - uint32_t index = 0, c = 0; - uint32_t *p1 = NULL, *p2 = NULL, x1, x2, *lut, *Tx = NULL, *Ty = NULL, *Tz = NULL; - size_t bitlen, shiftr, shiftl = 0u; - - if (N_wordlen == 8U) - { - bitlen = (size_t)kCASPER_ECC_P256_N_bitlen; - precompute_double_scalar_LUT16(X1, Y1, X2, Y2); - shiftr = 30U; - shiftl = 2U; - } - - if (N_wordlen == 12U) - { - bitlen = (size_t)kCASPER_ECC_P384_N_bitlen; - precompute_double_scalar_LUT16(X1, Y1, X2, Y2); - shiftr = 30U; - shiftl = 2U; - } - - if (N_wordlen == 18U) - { - bitlen = (size_t)kCASPER_ECC_P521_N_bitlen; - precompute_double_scalar_LUT4(X1, Y1, X2, Y2); - shiftr = 31U; - shiftl = 1U; - } - - lut = &CASPER_MEM[(20U * N_wordlen + 80U)]; - - if (N_wordlen == 8U || N_wordlen == 12U) - { - p1 = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen]; - p2 = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 1U * (N_wordlen + 4U)]; - - Tx = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 2U * (N_wordlen + 4U)]; - Ty = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 3U * (N_wordlen + 4U)]; - Tz = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 4U * (N_wordlen + 4U)]; - } - - if (N_wordlen == 18U) - { - p1 = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen]; - p2 = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 1U * (N_wordlen + 4U)]; - - Tx = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 2U * (N_wordlen + 4U)]; - Ty = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 3U * (N_wordlen + 4U)]; - Tz = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 4U * (N_wordlen + 4U)]; - } - - CASPER_MEMCPY(p1, k1, sizeof(uint32_t) * N_wordlen); - CASPER_MEMCPY(p2, k2, sizeof(uint32_t) * N_wordlen); - - /* Check if we can slide. */ - while (((casper_get_word(&p1[N_wordlen - 1U]) | casper_get_word(&p2[N_wordlen - 1U])) >> 31) == 0U && c < bitlen) - { - shiftleft(p1, p1, 1U); - shiftleft(p2, p2, 1U); - c++; - /* No doubling needed. */ - } - - /* Set the first value. */ - x1 = casper_get_word(&p1[N_wordlen - 1U]) >> shiftr; - x2 = casper_get_word(&p2[N_wordlen - 1U]) >> shiftr; - if (N_wordlen == 8U || N_wordlen == 12U) - { - index = (x2 | (x1 << 2)) - 2U - (uint32_t)(x1 != 0U) * 2U; - } - - if (N_wordlen == 18U) - { - index = (((x2) + 1U) & (0U - (x1))); - } - shiftleft(p1, p1, shiftl); - shiftleft(p2, p2, shiftl); - - CASPER_MEMCPY(X3, &lut[GETLUTX(index)], N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Y3, &lut[GETLUTY(index)], N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Z3, &lut[GETLUTZ(index)], N_wordlen * sizeof(uint32_t)); - c += shiftl; - - // todo: create an is_zero function - - while ((casper_get_word(&p1[0]) | casper_get_word(&p1[1]) | casper_get_word(&p1[2]) | casper_get_word(&p1[3]) | - casper_get_word(&p1[4]) | casper_get_word(&p1[5]) | casper_get_word(&p1[6]) | casper_get_word(&p1[7]) | - casper_get_word(&p1[8]) | casper_get_word(&p1[9]) | casper_get_word(&p1[10]) | casper_get_word(&p1[11]) | - casper_get_word(&p1[12]) | casper_get_word(&p1[13]) | casper_get_word(&p1[14]) | casper_get_word(&p1[15]) | - casper_get_word(&p1[16]) | casper_get_word(&p1[17]) | casper_get_word(&p2[0]) | casper_get_word(&p2[1]) | - casper_get_word(&p2[2]) | casper_get_word(&p2[3]) | casper_get_word(&p2[4]) | casper_get_word(&p2[5]) | - casper_get_word(&p2[6]) | casper_get_word(&p2[7]) | casper_get_word(&p2[8]) | casper_get_word(&p2[9]) | - casper_get_word(&p2[10]) | casper_get_word(&p2[11]) | casper_get_word(&p2[12]) | casper_get_word(&p2[13]) | - casper_get_word(&p2[14]) | casper_get_word(&p2[15]) | casper_get_word(&p2[16]) | - casper_get_word(&p2[17])) != 0U) - { - /* Check if we can slide. */ - while (((casper_get_word(&p1[N_wordlen - 1U]) | casper_get_word(&p2[N_wordlen - 1U])) >> 31) == 0U && - c < bitlen) - { - shiftleft(p1, p1, 1U); - shiftleft(p2, p2, 1U); - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - c++; - } - - if (c >= (bitlen - 1U)) - { - break; - } - - for (uint32_t i = 0; i < shiftl; i++) - { - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - } - - x1 = casper_get_word(&p1[N_wordlen - 1U]) >> shiftr; - x2 = casper_get_word(&p2[N_wordlen - 1U]) >> shiftr; - - if (N_wordlen == 8U || N_wordlen == 12U) - { - index = (x2 | (x1 << 2)) - 2U - (uint32_t)(x1 != 0U) * 2U; - } - - if (N_wordlen == 18U) - { - index = (((x2) + 1U) & (0U - (x1))); - } - - shiftleft(p1, p1, shiftl); - shiftleft(p2, p2, shiftl); - - CASPER_MEMCPY(Tx, &lut[GETLUTX(index)], N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Ty, &lut[GETLUTY(index)], N_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(Tz, &lut[GETLUTZ(index)], N_wordlen * sizeof(uint32_t)); - - Jac_addition(X3, Y3, Z3, X3, Y3, Z3, Tx, Ty, - Tz); //&lut[GETLUTX(index)], &lut[GETLUTY(index)], &lut[GETLUTZ(index)]); - c += shiftl; - } - - /* Special case in the end. */ - if (c == (bitlen - 1U)) - { - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - x1 = casper_get_word(&p1[N_wordlen - 1U]) >> 31; - x2 = casper_get_word(&p2[N_wordlen - 1U]) >> 31; - if (0U != x1) - { - Jac_add_affine(X3, Y3, Z3, X3, Y3, Z3, X1, Y1); - } - if (x2 != 0U) - { - Jac_add_affine(X3, Y3, Z3, X3, Y3, Z3, X2, Y2); - } - c++; - } - - while (c < bitlen) - { - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - c++; - } -} - -static void invert_mod_p256(uint32_t *c, uint32_t *a) -{ - int i; - uint32_t *t, *t2, *s1, *s2, *s4, *s8, *tmp; - - /* Assuming it is safe to use the ECC scratch size. */ - t = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - t2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - s1 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - s2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - s4 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - s8 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 7U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - tmp = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 8U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - - // t2 = n^(2^1)*n # 11 - square_casper(tmp, a); - multiply_casper(t2, tmp, a); - - // s1 = t2^(2^2)*t2 # F - square_casper(s1, t2); - square_casper(tmp, s1); - multiply_casper(s1, tmp, t2); - - // s2 = s1^(2^4)*s1 # FF - square_casper(s2, s1); - // for (i = 1; i < 4; i++) square(s2, s2); - square_casper(tmp, s2); - square_casper(s2, tmp); - square_casper(tmp, s2); - multiply_casper(s2, tmp, s1); - - // s4 = s2^(2^8)*s2 # FFFF - square_casper(s4, s2); - for (i = 1; i < 7; i += 2) - { - square_casper(tmp, s4); - square_casper(s4, tmp); - } - square_casper(tmp, s4); - multiply_casper(s4, tmp, s2); - - // s8 = s4^(2^16)*s4 # FFFFFFFF - square_casper(s8, s4); - for (i = 1; i < 15; i += 2) - { - square_casper(tmp, s8); - square_casper(s8, tmp); - } - square_casper(tmp, s8); - multiply_casper(s8, tmp, s4); - - // t = s8^(2^32)*n # ffffffff00000001 - square_casper(tmp, s8); - for (i = 1; i < 31; i += 2) - { - square_casper(t, tmp); - square_casper(tmp, t); - } - square_casper(t, tmp); - multiply_casper(tmp, t, a); - - // t = t^(2^128)*s8 # ffffffff00000001000000000000000000000000ffffffff - for (i = 0; i < 128; i += 2) - { - square_casper(t, tmp); - square_casper(tmp, t); - } - multiply_casper(t, tmp, s8); - - // t = t^(2^32)*s8 # ffffffff00000001000000000000000000000000ffffffffffffffff - for (i = 0; i < 32; i += 2) - { - square_casper(tmp, t); - square_casper(t, tmp); - } - multiply_casper(tmp, t, s8); - - // t = t^(2^16)*s4 # ffffffff00000001000000000000000000000000ffffffffffffffffffff - for (i = 0; i < 16; i += 2) - { - square_casper(t, tmp); - square_casper(tmp, t); - } - multiply_casper(t, tmp, s4); - - // t = t^(2^8)*s2 # ffffffff00000001000000000000000000000000ffffffffffffffffffffff - for (i = 0; i < 8; i += 2) - { - square_casper(tmp, t); - square_casper(t, tmp); - } - multiply_casper(tmp, t, s2); - - // t = t^(2^4)*s1 # ffffffff00000001000000000000000000000000fffffffffffffffffffffff - for (i = 0; i < 4; i += 2) - { - square_casper(t, tmp); - square_casper(tmp, t); - } - multiply_casper(t, tmp, s1); - - // t = t^(2^2)*t2 - square_casper(tmp, t); - square_casper(t, tmp); - multiply_casper(tmp, t, t2); - - // t = t^(2^2)*n # ffffffff00000001000000000000000000000000fffffffffffffffffffffffd - square_casper(t, tmp); - square_casper(tmp, t); - multiply_casper(c, tmp, a); -} - -// A and C do not need to be in Casper memory -static void toMontgomery_ECC_P256(uint32_t *C, uint32_t *A) -{ - /* R^2 = 2^512 mod p, used to convert values to Montgomery form. */ - uint32_t R2[kCASPER_ECC_P256_wordlen] = {0x00000003, 0x00000000, 0xffffffffU, 0xfffffffbU, - 0xfffffffeU, 0xffffffffU, 0xfffffffdU, 0x4}; - uint32_t *T1, *T2, *T3; - T1 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - T2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - T3 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + - 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - - CASPER_MEMCPY(T1, R2, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(T2, A, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - - multiply_casper(T3, T2, T1); - CASPER_MEMCPY(C, T3, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); -} - -/* Compute inversion modulo NIST-p384 using Fermats little theorem. - * Using c = a^(p-2) = a^(-1) mod p. - * This computes the modular inversion if all arithmetic is "regular" - * modular arithmetic or computes automatically the Montgomery inverse - * if all arithmetic is Montgomery arithmetic. - */ - -static void invert_mod_p384(uint32_t *c, uint32_t *a) -{ - int i; - uint32_t *e, *d, *tmp, *t0, *t1, *t2, *t3, *t4, *t5, *t6; // 10 residues needed - - /* Assuming it is safe to use the LUT scratch size. - * Hence, do not invert while elements in the LUT are needed. - */ - e = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - d = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - tmp = - &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t0 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t1 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t4 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 7U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t5 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 8U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - t6 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - - square_casper(tmp, a); // 2 - square_casper(t1, tmp); // 4 - square_casper(tmp, t1); // 8 - multiply_casper(t2, tmp, t1); // 12 - multiply_casper(d, a, t2); // 13 - multiply_casper(e, d, a); // 14 - multiply_casper(t0, e, a); // 15 - - // t1 = t0^(2^4)*t0 # ff - square_casper(tmp, t0); - square_casper(t1, tmp); - square_casper(tmp, t1); - square_casper(t2, tmp); - multiply_casper(t1, t2, t0); - - // t2 = t1^(2^8)*t1 # 4f - square_casper(tmp, t1); - for (i = 0; i < 3; i++) - { - square_casper(t3, tmp); - square_casper(tmp, t3); - } - square_casper(t3, tmp); - multiply_casper(t2, t3, t1); - - // t3 = t2^(2^16)*t2 # 8f - square_casper(tmp, t2); - for (i = 0; i < 7; i++) - { - square_casper(t4, tmp); - square_casper(tmp, t4); - } - square_casper(t4, tmp); - multiply_casper(t3, t4, t2); - - // t4 = t3^(2^32)*t3 # 16f - square_casper(tmp, t3); - for (i = 0; i < 15; i++) - { - square_casper(t5, tmp); - square_casper(tmp, t5); - } - square_casper(t5, tmp); - multiply_casper(t4, t5, t3); - - // t5 = t4^(2^64)*t4 # 32f - square_casper(tmp, t4); - for (i = 0; i < 31; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t4); - - // t5 = t5^(2^64)*t4 # 48f - square_casper(tmp, t5); - for (i = 0; i < 31; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t4); - - // t5 = t5^(2^32)*t3 # 56f - square_casper(tmp, t5); - for (i = 0; i < 15; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t3); - - // t5 = t5^(2^16)*t2 # 60f - square_casper(tmp, t5); - for (i = 0; i < 7; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t2); - - // t5 = t5^(2^8)*t1 # 62f - square_casper(tmp, t5); - for (i = 0; i < 3; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t1); - - // n = t5^(2^4)*t0 # 63f - square_casper(tmp, t5); - for (i = 0; i < 1; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t0); - - // n = n^(2^4)*e - square_casper(tmp, t5); - for (i = 0; i < 1; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, e); - - // n = n^(2^32)*t3 - square_casper(tmp, t5); - for (i = 0; i < 15; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t3); - - // n = n^(2^64) - square_casper(tmp, t5); - for (i = 0; i < 31; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t5, tmp); - - // n = n^(2^16)*t2 - square_casper(tmp, t5); - for (i = 0; i < 7; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t2); - - // n = n^(2^8)*t1 - square_casper(tmp, t5); - for (i = 0; i < 3; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t1); - - // n = n^(2^4)*t0 - square_casper(tmp, t5); - for (i = 0; i < 1; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t0); - - // n = n^(2^4)*d - square_casper(tmp, t5); - for (i = 0; i < 1; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(c, t6, d); -} - -// A and C do not need to be in Casper memory -static void toMontgomery_ECC_P384(uint32_t *C, uint32_t *A) -{ - /* R^2 = 2^768 mod p, used to convert values to Montgomery form. */ - uint32_t R2[kCASPER_ECC_P384_wordlen] = {0x00000001, 0xfffffffeU, 0x00000000, 0x00000002, 0x00000000, 0xfffffffeU, - 0x00000000, 0x00000002, 0x1, 0x0, 0x0, 0x0}; - uint32_t *T1, *T2, *T3; - T1 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U))) + - 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - T2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U))) + - 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - T3 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + - (9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U))) + - 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - - CASPER_MEMCPY(T1, R2, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(T2, A, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - - multiply_casper(T3, T2, T1); - CASPER_MEMCPY(C, T3, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); -} - -static void invert_mod_p521(uint32_t *c, uint32_t *a) -{ - int i; - uint32_t *e3, *d2, *d3, *d4, *T2, *T4; // 6 residues needed - - /* Assuming it is safe to use the LUT scratch size. - * Hence, do not invert while elements in the LUT are needed. - */ - e3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - d2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - d3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - d4 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - T2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - T4 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - - square_casper(d2, a); - multiply_casper(T2, d2, a); - - // d3 = 2^2 * T2 - square_casper(d3, T2); - square_casper(e3, d3); - multiply_casper(T4, e3, T2); - - // d3 = 2^4 * T4 - square_casper(d3, T4); - square_casper(e3, d3); - square_casper(d3, e3); - square_casper(e3, d3); - multiply_casper(d2, e3, T4); - - // d3 = 2^8 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - for (i = 0; i < 3; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d4, e3, d2); - - // d3 = 2^16 * d2 - square_casper(d3, d4); - square_casper(e3, d3); - for (i = 0; i < 7; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d2, e3, d4); - - // d3 = 2^32 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - for (i = 0; i < 15; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d4, e3, d2); - - // d3 = 2^64 * d2 - square_casper(d3, d4); - square_casper(e3, d3); - for (i = 0; i < 31; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d2, e3, d4); - - // d3 = 2^128 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - for (i = 0; i < 63; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d4, e3, d2); - - // d3 = 2^256 * d2 - square_casper(d3, d4); - square_casper(e3, d3); - for (i = 0; i < 127; i++) - { - square_casper(d3, e3); - square_casper(e3, d3); - } - multiply_casper(d2, e3, d4); - - // d3 = 2^2 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - multiply_casper(d2, e3, T2); - - // d3 = 2^4 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - square_casper(d3, e3); - square_casper(e3, d3); - multiply_casper(d2, e3, T4); - - square_casper(d3, d2); - multiply_casper(d2, d3, a); - - // d3 = 2 ^ 2 * d2 - square_casper(d3, d2); - square_casper(e3, d3); - multiply_casper(c, e3, a); -} - -static void toMontgomery_ECC_P521(uint32_t *C, uint32_t *A) -{ - /* R^2 = 2^1088 mod p, used to convert values to Montgomery form. */ - // uint32_t R2[NUM_LIMBS] = { 0x00000000, 0x4000, 0, 0, - // 0, 0, 0, 0, - // 0, 0, 0, 0, - // 0 }; - /* R^2 = 2^1152 mod p, used to convert values to Montgomery form. */ - uint32_t R2[kCASPER_ECC_P521_wordlen] = {0, 0, 0, 0x4000, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - - uint32_t *T1, *T2, *T3; - T1 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - T2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - T3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; - - CASPER_MEMCPY(T1, R2, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(T2, A, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); - - multiply_casper(T3, T2, T1); - CASPER_MEMCPY(C, T3, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); -} - -static void MultprecCiosMul521_ct( - uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np) -{ - uint32_t j; - uint64_t carry; - uint64_t *a64, *b64, *w64; - - uint32_t *T1 = &CASPER_MEM[0], borrow; - - a64 = (uint64_t *)(uintptr_t)a; - b64 = (uint64_t *)(uintptr_t)b; - w64 = (uint64_t *)(uintptr_t)w_out; - - if (a != NULL) - { /* if !a, we are reducing only */ - PreZeroW(j, w_out); - } - SET_DWORD(&w64[N_dwordlen], 0ULL); - SET_DWORD(&w64[N_dwordlen + 1U], 0ULL); - /* with accelerator */ - - /* loop j and then reduce after each j round */ - for (j = 0; j < N_dwordlen; j++) - { - /* Step 3. Iterate over N words of u using j - perform Multiply-accumulate */ - /* push-pull: we do a*b and then separately m*n (reduce) */ - if (a != NULL) - { /* if mul&reduce vs. reduce only */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(&b64[j]), CA_MK_OFF(a64)); - Accel_crypto_mul( - Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); - Accel_done(); - /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ - /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ - /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ - /* w64[N_dwordlen+1] = g_carry; */ - carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); - SET_DWORD(&w64[N_dwordlen + 1U], carry); - } - - /* Fast reduction using only shifts for this special shape: - * (c - (-p^-1*c mod 2^64) * p)/2^64 = - * (c - c_0 * p)/2^64 = - * (\sum_{j=0}^9 c_i*2^64 - c_0 * p)/2^64 = - * (\sum_{j=0}^9 c_i*2^64 - c_0 * (2^521-1))/2^64 = - * (\sum_{j=0}^9 c_i*2^64 - c_0 * 2^521 - c_0)/2^64 = - * c_1 + c_2*2^64 + c_3*2^128 + c_4*2^192 + c_5*2^256 + c_6*2^320 + c_7*2^384 + c_8*2^448 + c_9*2^512 + c_0 * - * 2^{448 + 9} so one only needs to compute this 128-bit addition: [c_8, c_9] + c_0 * 2^9 - */ - - uint64_t *p64 = (uint64_t *)(uintptr_t)T1; - - /* p64[0] = w64[0] << 9;*/ - SET_DWORD(&p64[0], GET_DWORD(&w64[0]) << 9U); - /* p64[1] = w64[0] >> (64 - 9); */ - SET_DWORD(&p64[1], GET_DWORD(&w64[0]) >> (64 - 9)); - /* w64[0] = w64[1]; */ - SET_DWORD(&w64[0], GET_DWORD(&w64[1])); - /* w64[1] = w64[2]; */ - SET_DWORD(&w64[1], GET_DWORD(&w64[2])); - /* w64[2] = w64[3]; */ - SET_DWORD(&w64[2], GET_DWORD(&w64[3])); - /* w64[3] = w64[4]; */ - SET_DWORD(&w64[3], GET_DWORD(&w64[4])); - /* w64[4] = w64[5]; */ - SET_DWORD(&w64[4], GET_DWORD(&w64[5])); - /* w64[5] = w64[6]; */ - SET_DWORD(&w64[5], GET_DWORD(&w64[6])); - /* w64[6] = w64[7]; */ - SET_DWORD(&w64[6], GET_DWORD(&w64[7])); - - /* Compute p64 = p64 + {w64[8], w64[9]} using one additonal double-length limb, - * where p64 = w64[0] * 2^9. - */ - Accel_SetABCD_Addr(CA_MK_OFF(&w64[8]), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(2, (uint32_t)kCASPER_OpAdd64, /* kCASPER_OpAdd64, */ - CA_MK_OFF(p64))); - Accel_done(); - - /* w64[7] = p64[0]; */ - SET_DWORD(&w64[7], GET_DWORD(&p64[0])); - /* w64[8] = p64[1]; */ - SET_DWORD(&w64[8], GET_DWORD(&p64[1])); - /* w64[9] = 0; */ - SET_DWORD(&w64[9], (uint64_t)0U); - } - - /* memcpy(T1, w_out, (NUM_LIMBS + 1) * sizeof(uint32_t)); */ - /* now check if need to subtract Nmod */ - CASPER_MEMCPY_I2I(T1, w_out, (N_wordlen + 1U) * sizeof(uint32_t)); - - /* Compute w = w - N */ - Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(w_out))); - Accel_done(); - - /* if w_out > T1 then there was a borrow */ - /* borrow = (((uint32_t*)w_out)[NUM_LIMBS] > T1[NUM_LIMBS]); */ - borrow = (uint32_t)(GET_WORD(&((uint32_t *)w_out)[N_wordlen]) > GET_WORD(&T1[N_wordlen])); - SET_WORD(&w_out[N_wordlen + 1U], 0); - SET_WORD(&w_out[N_wordlen], 0); - /* w_out[NUM_LIMBS + 1] = 0; */ - /* w_out[NUM_LIMBS] = 0; */ - casper_select(w_out, w_out, T1, (int32_t)borrow, (int32_t)N_wordlen); -} - -#if defined(__GNUC__) -/* End of enforcing O1 optimize level for gcc*/ -#pragma GCC pop_options -#endif - -#if (defined(__CC_ARM) || defined(__ARMCC_VERSION)) -// End of enforcing optimize off for clang -#pragma clang optimize on -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_casper.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_casper.h deleted file mode 100644 index 328dc101116..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_casper.h +++ /dev/null @@ -1,386 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CASPER_H_ -#define _FSL_CASPER_H_ - -#include "fsl_common.h" - -/*! @file */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! - * @addtogroup casper_driver - * @{ - */ -/*! @name Driver version */ -/*@{*/ -/*! @brief CASPER driver version. Version 2.2.3. - * - * Current version: 2.2.3 - * - * Change log: - * - Version 2.0.0 - * - Initial version - * - Version 2.0.1 - * - Bug fix KPSDK-24531 double_scalar_multiplication() result may be all zeroes for some specific input - * - Version 2.0.2 - * - Bug fix KPSDK-25015 CASPER_MEMCPY hard-fault on LPC55xx when both source and destination buffers are outside of - * CASPER_RAM - * - Version 2.0.3 - * - Bug fix KPSDK-28107 RSUB, FILL and ZERO operations not implemented in enum _casper_operation. - * - Version 2.0.4 - * - For GCC compiler, enforce O1 optimize level, specifically to remove strict-aliasing option. - * This driver is very specific and requires -fno-strict-aliasing. - * - Version 2.0.5 - * - Fix sign-compare warning. - * - Version 2.0.6 - * - Fix IAR Pa082 warning. - * - Version 2.0.7 - * - Fix MISRA-C 2012 issue. - * - Version 2.0.8 - * - Add feature macro for CASPER_RAM_OFFSET. - * - Version 2.0.9 - * - Remove unused function Jac_oncurve(). - * - Fix ECC384 build. - * - Version 2.0.10 - * - Fix MISRA-C 2012 issue. - * - Version 2.1.0 - * - Add ECC NIST P-521 elliptic curve. - * - Version 2.2.0 - * - Rework driver to support multiple curves at once. - * - Version 2.2.1 - * - Fix MISRA-C 2012 issue. - * - Version 2.2.2 - * - Enable hardware interleaving to RAMX0 and RAMX1 for CASPER by feature macro FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE - * - Version 2.2.3 - * - Added macro into CASPER_Init and CASPER_Deinit to support devices without clock and reset control. - */ -#define FSL_CASPER_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) -/*@}*/ - -/*! @brief CASPER operation - * - */ -typedef enum _casper_operation -{ - kCASPER_OpMul6464NoSum = 0x01, /*! Walking 1 or more of J loop, doing r=a*b using 64x64=128*/ - kCASPER_OpMul6464Sum = - 0x02, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but assume inner j loop*/ - kCASPER_OpMul6464FullSum = - 0x03, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but sum all of w. */ - kCASPER_OpMul6464Reduce = - 0x04, /*! Walking 1 or more of J loop, doing c,r[-1]=r+a*b using 64x64=128, but skip 1st write*/ - kCASPER_OpAdd64 = 0x08, /*! Walking add with off_AB, and in/out off_RES doing c,r=r+a+c using 64+64=65*/ - kCASPER_OpSub64 = 0x09, /*! Walking subtract with off_AB, and in/out off_RES doing r=r-a using 64-64=64, with last - borrow implicit if any*/ - kCASPER_OpDouble64 = 0x0A, /*! Walking add to self with off_RES doing c,r=r+r+c using 64+64=65*/ - kCASPER_OpXor64 = 0x0B, /*! Walking XOR with off_AB, and in/out off_RES doing r=r^a using 64^64=64*/ - kCASPER_OpRSub64 = 0x0C, /*! Walking subtract with off_AB, and in/out off_RES using r=a-r */ - kCASPER_OpShiftLeft32 = - 0x10, /*! Walking shift left doing r1,r=(b*D)|r1, where D is 2^amt and is loaded by app (off_CD not used)*/ - kCASPER_OpShiftRight32 = 0x11, /*! Walking shift right doing r,r1=(b*D)|r1, where D is 2^(32-amt) and is loaded by - app (off_CD not used) and off_RES starts at MSW*/ - kCASPER_OpCopy = 0x14, /*! Copy from ABoff to resoff, 64b at a time*/ - kCASPER_OpRemask = 0x15, /*! Copy and mask from ABoff to resoff, 64b at a time*/ - kCASPER_OpFill = 0x16, /*! Fill RESOFF using 64 bits at a time with value in A and B */ - kCASPER_OpZero = 0x17, /*! Fill RESOFF using 64 bits at a time of 0s */ - kCASPER_OpCompare = 0x18, /*! Compare two arrays, running all the way to the end*/ - kCASPER_OpCompareFast = 0x19, /*! Compare two arrays, stopping on 1st !=*/ -} casper_operation_t; - -/*! @brief Algorithm used for CASPER operation */ -typedef enum _casper_algo_t -{ - kCASPER_ECC_P256 = 0x01, /*!< ECC_P256*/ - kCASPER_ECC_P384 = 0x02, /*!< ECC_P384 */ - kCASPER_ECC_P521 = 0x03, /*!< ECC_P521 */ -} casper_algo_t; - -#define CASPER_CP 1 -#define CASPER_CP_CTRL0 (0x0 >> 2) -#define CASPER_CP_CTRL1 (0x4 >> 2) -#define CASPER_CP_LOADER (0x8 >> 2) -#define CASPER_CP_STATUS (0xC >> 2) -#define CASPER_CP_INTENSET (0x10 >> 2) -#define CASPER_CP_INTENCLR (0x14 >> 2) -#define CASPER_CP_INTSTAT (0x18 >> 2) -#define CASPER_CP_AREG (0x20 >> 2) -#define CASPER_CP_BREG (0x24 >> 2) -#define CASPER_CP_CREG (0x28 >> 2) -#define CASPER_CP_DREG (0x2C >> 2) -#define CASPER_CP_RES0 (0x30 >> 2) -#define CASPER_CP_RES1 (0x34 >> 2) -#define CASPER_CP_RES2 (0x38 >> 2) -#define CASPER_CP_RES3 (0x3C >> 2) -#define CASPER_CP_MASK (0x60 >> 2) -#define CASPER_CP_REMASK (0x64 >> 2) -#define CASPER_CP_LOCK (0x80 >> 2) -#define CASPER_CP_ID (0xFFC >> 2) -/* mcr (cp, opc1, value, CRn, CRm, opc2) */ -#define CASPER_Wr32b(value, off) __arm_mcr(CASPER_CP, 0, value, ((off >> 4)), (off), 0) -/* mcrr(coproc, opc1, value, CRm) */ -#define CASPER_Wr64b(value, off) __arm_mcrr(CASPER_CP, 0, value, off) -/* mrc(coproc, opc1, CRn, CRm, opc2) */ -#define CASPER_Rd32b(off) __arm_mrc(CASPER_CP, 0, ((off >> 4)), (off), 0) - -/* The model for this algo is that it can be implemented for a fixed size RSA key */ -/* for max speed. If this is made into a variable (to allow varying size), then */ -/* it will be slower by a bit. */ -/* The file is compiled with N_bitlen passed in as number of bits of the RSA key */ -/* #define N_bitlen 2048 */ -#define N_wordlen_max (4096U / 32U) - -enum -{ - kCASPER_RamOffset_Result = 0x0u, - kCASPER_RamOffset_Base = (N_wordlen_max + 8u), - kCASPER_RamOffset_TempBase = (2u * N_wordlen_max + 16u), - kCASPER_RamOffset_Modulus = (kCASPER_RamOffset_TempBase + N_wordlen_max + 4u), - kCASPER_RamOffset_M64 = 1022U, -}; - -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup casper_driver - * @{ - */ - -/*! - * @brief Enables clock and disables reset for CASPER peripheral. - * - * Enable clock and disable reset for CASPER. - * - * @param base CASPER base address - */ -void CASPER_Init(CASPER_Type *base); - -/*! - * @brief Disables clock for CASPER peripheral. - * - * Disable clock and enable reset. - * - * @param base CASPER base address - */ -void CASPER_Deinit(CASPER_Type *base); - -/*! - *@} - */ /* end of casper_driver */ - -/******************************************************************************* - * PKHA API - ******************************************************************************/ - -/*! - * @addtogroup casper_driver_pkha - * @{ - */ - -/*! - * @brief Performs modular exponentiation - (A^E) mod N. - * - * This function performs modular exponentiation. - * - * @param base CASPER base address - * @param signature first addend (in little endian format) - * @param pubN modulus (in little endian format) - * @param wordLen Size of pubN in bytes - * @param pubE exponent - * @param[out] plaintext Output array to store result of operation (in little endian format) - */ -void CASPER_ModExp(CASPER_Type *base, - const uint8_t *signature, - const uint8_t *pubN, - size_t wordLen, - uint32_t pubE, - uint8_t *plaintext); - -/*! - * @brief Initialize prime modulus mod in Casper memory . - * - * Set the prime modulus mod in Casper memory and set N_wordlen - * according to selected algorithm. - * - * @param curve elliptic curve algoritm - */ -void CASPER_ecc_init(casper_algo_t curve); - -/*! - * @brief Performs ECC secp256r1 point single scalar multiplication - * - * This function performs ECC secp256r1 point single scalar multiplication - * [resX; resY] = scalar * [X; Y] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate in normal form, little endian. - * @param[out] resY Output Y affine coordinate in normal form, little endian. - * @param X Input X affine coordinate in normal form, little endian. - * @param Y Input Y affine coordinate in normal form, little endian. - * @param scalar Input scalar integer, in normal form, little endian. - */ -void CASPER_ECC_SECP256R1_Mul( - CASPER_Type *base, uint32_t resX[8], uint32_t resY[8], uint32_t X[8], uint32_t Y[8], uint32_t scalar[8]); - -/*! - * @brief Performs ECC secp256r1 point double scalar multiplication - * - * This function performs ECC secp256r1 point double scalar multiplication - * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate. - * @param[out] resY Output Y affine coordinate. - * @param X1 Input X1 affine coordinate. - * @param Y1 Input Y1 affine coordinate. - * @param scalar1 Input scalar1 integer. - * @param X2 Input X2 affine coordinate. - * @param Y2 Input Y2 affine coordinate. - * @param scalar2 Input scalar2 integer. - */ -void CASPER_ECC_SECP256R1_MulAdd(CASPER_Type *base, - uint32_t resX[8], - uint32_t resY[8], - uint32_t X1[8], - uint32_t Y1[8], - uint32_t scalar1[8], - uint32_t X2[8], - uint32_t Y2[8], - uint32_t scalar2[8]); - -/*! - * @brief Performs ECC secp384r1 point single scalar multiplication - * - * This function performs ECC secp384r1 point single scalar multiplication - * [resX; resY] = scalar * [X; Y] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate in normal form, little endian. - * @param[out] resY Output Y affine coordinate in normal form, little endian. - * @param X Input X affine coordinate in normal form, little endian. - * @param Y Input Y affine coordinate in normal form, little endian. - * @param scalar Input scalar integer, in normal form, little endian. - */ -void CASPER_ECC_SECP384R1_Mul( - CASPER_Type *base, uint32_t resX[12], uint32_t resY[12], uint32_t X[12], uint32_t Y[12], uint32_t scalar[12]); - -/*! - * @brief Performs ECC secp384r1 point double scalar multiplication - * - * This function performs ECC secp384r1 point double scalar multiplication - * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate. - * @param[out] resY Output Y affine coordinate. - * @param X1 Input X1 affine coordinate. - * @param Y1 Input Y1 affine coordinate. - * @param scalar1 Input scalar1 integer. - * @param X2 Input X2 affine coordinate. - * @param Y2 Input Y2 affine coordinate. - * @param scalar2 Input scalar2 integer. - */ -void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base, - uint32_t resX[12], - uint32_t resY[12], - uint32_t X1[12], - uint32_t Y1[12], - uint32_t scalar1[12], - uint32_t X2[12], - uint32_t Y2[12], - uint32_t scalar2[12]); - -/*! - * @brief Performs ECC secp521r1 point single scalar multiplication - * - * This function performs ECC secp521r1 point single scalar multiplication - * [resX; resY] = scalar * [X; Y] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate in normal form, little endian. - * @param[out] resY Output Y affine coordinate in normal form, little endian. - * @param X Input X affine coordinate in normal form, little endian. - * @param Y Input Y affine coordinate in normal form, little endian. - * @param scalar Input scalar integer, in normal form, little endian. - */ -void CASPER_ECC_SECP521R1_Mul( - CASPER_Type *base, uint32_t resX[18], uint32_t resY[18], uint32_t X[18], uint32_t Y[18], uint32_t scalar[18]); - -/*! - * @brief Performs ECC secp521r1 point double scalar multiplication - * - * This function performs ECC secp521r1 point double scalar multiplication - * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate. - * @param[out] resY Output Y affine coordinate. - * @param X1 Input X1 affine coordinate. - * @param Y1 Input Y1 affine coordinate. - * @param scalar1 Input scalar1 integer. - * @param X2 Input X2 affine coordinate. - * @param Y2 Input Y2 affine coordinate. - * @param scalar2 Input scalar2 integer. - */ -void CASPER_ECC_SECP521R1_MulAdd(CASPER_Type *base, - uint32_t resX[18], - uint32_t resY[18], - uint32_t X1[18], - uint32_t Y1[18], - uint32_t scalar1[18], - uint32_t X2[18], - uint32_t Y2[18], - uint32_t scalar2[18]); - -void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2); -void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1); - -/*! - *@} - */ /* end of casper_driver_pkha */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_CASPER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_clock.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_clock.c deleted file mode 100644 index 80460c09050..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_clock.c +++ /dev/null @@ -1,2106 +0,0 @@ -/* - * Copyright 2017 - 2021 , NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_clock.h" -#include "fsl_power.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.clock" -#endif -#define NVALMAX (0x100U) -#define PVALMAX (0x20U) -#define MVALMAX (0x10000U) - -#define PLL_MAX_N_DIV 0x100U - -/*-------------------------------------------------------------------------- -!!! If required these #defines can be moved to chip library file -----------------------------------------------------------------------------*/ - -#define PLL_SSCG1_MDEC_VAL_P (10U) /* MDEC is in bits 25 downto 10 */ -#define PLL_SSCG1_MDEC_VAL_M (0xFFFFULL << PLL_SSCG1_MDEC_VAL_P) -#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */ -#define PLL_NDEC_VAL_M (0xFFUL << PLL_NDEC_VAL_P) -#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */ -#define PLL_PDEC_VAL_M (0x1FUL << PLL_PDEC_VAL_P) - -#define PLL_MIN_CCO_FREQ_MHZ (275000000U) -#define PLL_MAX_CCO_FREQ_MHZ (550000000U) -#define PLL_LOWER_IN_LIMIT (2000U) /*!< Minimum PLL input rate */ -#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */ -#define PLL_MIN_IN_SSMODE (3000000U) -#define PLL_MAX_IN_SSMODE \ - (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */ - -/* PLL NDEC reg */ -#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) -/* PLL PDEC reg */ -#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M) -/* SSCG control1 */ -#define PLL_SSCG1_MDEC_VAL_SET(value) (((uint64_t)(value) << PLL_SSCG1_MDEC_VAL_P) & PLL_SSCG1_MDEC_VAL_M) - -/* PLL0 SSCG control1 */ -#define PLL0_SSCG_MD_FRACT_P 0U -#define PLL0_SSCG_MD_INT_P 25U -#define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) -#define PLL0_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL0_SSCG_MD_INT_P) - -#define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_FRACT_M) -#define PLL0_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_INT_P) & PLL0_SSCG_MD_INT_M) - -/* Saved value of PLL output rate, computed whenever needed to save run-time - computation on each call to retrive the PLL rate. */ -static uint32_t s_Pll0_Freq; -static uint32_t s_Pll1_Freq; - -/** External clock rate on the CLKIN pin in Hz. If not used, - set this to 0. Otherwise, set it to the exact rate in Hz this pin is - being driven at. */ -static uint32_t s_Ext_Clk_Freq = 16000000U; -static uint32_t s_I2S_Mclk_Freq = 0U; -static uint32_t s_PLU_ClkIn_Freq = 0U; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ -static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); -/* Get predivider (N) from PLL0 NDEC setting */ -static uint32_t findPll0PreDiv(void); -/* Get predivider (N) from PLL1 NDEC setting */ -static uint32_t findPll1PreDiv(void); -/* Get postdivider (P) from PLL0 PDEC setting */ -static uint32_t findPll0PostDiv(void); -/* Get multiplier (M) from PLL0 MDEC and SSCG settings */ -static float findPll0MMult(void); -/* Get the greatest common divisor */ -static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); -/* Set PLL output based on desired output rate */ -static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS); -/* Update local PLL rate variable */ -static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup); - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Clock Selection for IP */ -/** - * brief Configure the clock selection muxes. - * param connection : Clock to be configured. - * return Nothing - */ -void CLOCK_AttachClk(clock_attach_id_t connection) -{ - uint8_t mux; - uint8_t sel; - uint16_t item; - uint32_t tmp32 = (uint32_t)connection; - uint32_t i; - volatile uint32_t *pClkSel; - - pClkSel = &(SYSCON->SYSTICKCLKSELX[0]); - - if (kNONE_to_NONE != connection) - { - for (i = 0U; i < 2U; i++) - { - if (tmp32 == 0U) - { - break; - } - item = (uint16_t)GET_ID_ITEM(tmp32); - if (item != 0U) - { - mux = GET_ID_ITEM_MUX(item); - sel = GET_ID_ITEM_SEL(item); - if (mux == CM_RTCOSC32KCLKSEL) - { - PMC->RTCOSC32K |= sel; - } - else - { - pClkSel[mux] = sel; - } - } - tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */ - } - } -} - -/* Return the actual clock attach id */ -/** - * brief Get the actual clock attach id. - * This fuction uses the offset in input attach id, then it reads the actual source value in - * the register and combine the offset to obtain an actual attach id. - * param attachId : Clock attach id to get. - * return Clock source value. - */ -clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId) -{ - uint8_t mux; - uint8_t actualSel; - uint32_t tmp32 = (uint32_t)attachId; - uint32_t i; - uint32_t actualAttachId = 0U; - uint32_t selector = GET_ID_SELECTOR(tmp32); - volatile uint32_t *pClkSel; - - pClkSel = &(SYSCON->SYSTICKCLKSELX[0]); - - if (kNONE_to_NONE == attachId) - { - return kNONE_to_NONE; - } - - for (i = 0U; i < 2U; i++) - { - mux = GET_ID_ITEM_MUX(tmp32); - if (tmp32 != 0UL) - { - if (mux == CM_RTCOSC32KCLKSEL) - { - actualSel = (uint8_t)(PMC->RTCOSC32K); - } - else - { - actualSel = (uint8_t)(pClkSel[mux]); - } - - /* Consider the combination of two registers */ - actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i); - } - tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */ - } - - actualAttachId |= selector; - - return (clock_attach_id_t)actualAttachId; -} - -/* Set IP Clock Divider */ -/** - * brief Setup peripheral clock dividers. - * param div_name : Clock divider name - * param divided_by_value: Value to be divided - * param reset : Whether to reset the divider counter. - * return Nothing - */ -void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) -{ - volatile uint32_t *pClkDiv; - - pClkDiv = &(SYSCON->SYSTICKCLKDIV0); - if ((div_name >= kCLOCK_DivFlexFrg0) && (div_name <= kCLOCK_DivFlexFrg7)) - { - /*!< Flexcomm Interface function clock = (clock selected via FCCLKSEL) / (1+ MULT /DIV), DIV = 0xFF */ - ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = - SYSCON_FLEXFRG0CTRL_DIV_MASK | SYSCON_FLEXFRG0CTRL_MULT(divided_by_value); - } - else - { - if (reset) - { - ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = 1UL << 29U; - } - if (divided_by_value == 0U) /*!< halt */ - { - ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = 1UL << 30U; - } - else - { - ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = (divided_by_value - 1U); - } - } -} - -/* Set RTC 1KHz Clock Divider */ -/** - * brief Setup rtc 1khz clock divider. - * param divided_by_value: Value to be divided - * return Nothing - */ -void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value) -{ - PMC->RTCOSC32K |= (((divided_by_value - 28U) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT) | PMC_RTCOSC32K_CLK1KHZDIV_MASK); -} - -/* Set RTC 1KHz Clock Divider */ -/** - * brief Setup rtc 1hz clock divider. - * param divided_by_value: Value to be divided - * return Nothing - */ -void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value) -{ - if (divided_by_value == 0U) /*!< halt */ - { - PMC->RTCOSC32K |= (1UL << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT); - } - else - { - PMC->RTCOSC32K |= - (((divided_by_value - 31744U) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT) | PMC_RTCOSC32K_CLK1HZDIV_MASK); - } -} - -/* Set FRO Clocking */ -/** - * brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). - * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is - * enabled. - * param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ) - * return returns success or fail status. - */ -status_t CLOCK_SetupFROClocking(uint32_t iFreq) -{ - if ((iFreq != 12000000U) && (iFreq != 48000000U) && (iFreq != 96000000U)) - { - return kStatus_Fail; - } - /* Enable Analog Control module */ - SYSCON->PRESETCTRLCLR[2] = (1UL << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT); - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK; - /* Power up the FRO192M */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); - - if (iFreq == 96000000U) - { - ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(1); - } - /* always enable - else if (iFreq == 48000000U) - { - ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(1); - }*/ - else - { - ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(1); - } - return kStatus_Success; -} - -/* Set the FLASH wait states for the passed frequency */ -/** - * brief Set the flash wait states for the input freuqency. - * param iFreq: Input frequency - * return Nothing - */ -void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq) -{ - uint32_t num_wait_states; /* Flash Controller & FMC internal number of Wait States (minus 1) */ - - if (iFreq <= 11000000UL) - { - /* [0 - 11 MHz] */ - num_wait_states = 0UL; - } - else if (iFreq <= 22000000UL) - { - /* [11 MHz - 22 MHz] */ - num_wait_states = 1UL; - } - else if (iFreq <= 33000000UL) - { - /* [22 MHz - 33 MHz] */ - num_wait_states = 2UL; - } - else if (iFreq <= 44000000UL) - { - /* [33 MHz - 44 MHz] */ - num_wait_states = 3UL; - } - else if (iFreq <= 55000000UL) - { - /* [44 MHz - 55 MHz] */ - num_wait_states = 4UL; - } - else if (iFreq <= 66000000UL) - { - /* [55 MHz - 662 MHz] */ - num_wait_states = 5UL; - } - else if (iFreq <= 77000000UL) - { - /* [66 MHz - 77 MHz] */ - num_wait_states = 6UL; - } - else if (iFreq <= 88000000UL) - { - /* [77 MHz - 88 MHz] */ - num_wait_states = 7UL; - } - else if (iFreq <= 100000000UL) - { - /* [88 MHz - 100 MHz] */ - num_wait_states = 8UL; - } - else if (iFreq <= 115000000UL) - { - /* [100 MHz - 115 MHz] */ - num_wait_states = 9UL; - } - else if (iFreq <= 130000000UL) - { - /* [115 MHz - 130 MHz] */ - num_wait_states = 10UL; - } - else if (iFreq <= 150000000UL) - { - /* [130 MHz - 150 MHz] */ - num_wait_states = 11UL; - } - else - { - /* Above 150 MHz */ - num_wait_states = 12UL; - } - - FLASH->INT_CLR_STATUS = 0x1FUL; /* Clear all status flags */ - - FLASH->DATAW[0] = (FLASH->DATAW[0] & 0xFFFFFFF0UL) | - (num_wait_states & (SYSCON_FMCCR_FLASHTIM_MASK >> SYSCON_FMCCR_FLASHTIM_SHIFT)); - - FLASH->CMD = 0x2; /* CMD_SET_READ_MODE */ - - /* Wait until the cmd is completed (without error) */ - while (0UL == (FLASH->INT_STATUS & FLASH_INT_STATUS_DONE_MASK)) - { - ; - } - - /* Adjust FMC waiting time cycles (num_wait_states) */ - SYSCON->FMCCR = (SYSCON->FMCCR & ~SYSCON_FMCCR_FLASHTIM_MASK) | - ((num_wait_states << SYSCON_FMCCR_FLASHTIM_SHIFT) & SYSCON_FMCCR_FLASHTIM_MASK); -} - -/* Set EXT OSC Clk */ -/** - * brief Initialize the external osc clock to given frequency. - * Crystal oscillator with an operating frequency of 12 MHz to 32 MHz. - * Option for external clock input (bypass mode) for clock frequencies of up to 25 MHz. - * param iFreq : Desired frequency (must be equal to exact rate in Hz) - * return returns success or fail status. - */ -status_t CLOCK_SetupExtClocking(uint32_t iFreq) -{ - if (iFreq > 32000000U) - { - return kStatus_Fail; - } - /* Turn on power for crystal 32 MHz */ - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); - /* Enable clock_in clock for clock module. */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; - - s_Ext_Clk_Freq = iFreq; - return kStatus_Success; -} - -/* Set I2S MCLK Clk */ -/** - * brief Initialize the I2S MCLK clock to given frequency. - * param iFreq : Desired frequency (must be equal to exact rate in Hz) - * return returns success or fail status. - */ -status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq) -{ - s_I2S_Mclk_Freq = iFreq; - return kStatus_Success; -} - -/* Set PLU CLKIN Clk */ -/** - * brief Initialize the PLU CLKIN clock to given frequency. - * param iFreq : Desired frequency (must be equal to exact rate in Hz) - * return returns success or fail status. - */ -status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq) -{ - s_PLU_ClkIn_Freq = iFreq; - return kStatus_Success; -} - -/* Get CLOCK OUT Clk */ -/*! brief Return Frequency of ClockOut - * return Frequency of ClockOut - */ -uint32_t CLOCK_GetClockOutClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->CLKOUTSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - - case 2U: - freq = CLOCK_GetExtClkFreq(); - break; - - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - - case 5U: - freq = CLOCK_GetPll1OutFreq(); - break; - - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - - case 7U: - freq = 0U; - break; - - default: - assert(false); - break; - } - return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U); -} - -/* Get ADC Clk */ -/*! brief Return Frequency of Adc Clock - * return Frequency of Adc. - */ -uint32_t CLOCK_GetAdcClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->ADCCLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 2U: - freq = CLOCK_GetFroHfFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - assert(false); - break; - } - - return freq / ((SYSCON->ADCCLKDIV & SYSCON_ADCCLKDIV_DIV_MASK) + 1U); -} - -/* Get USB0 Clk */ -/*! brief Return Frequency of Usb0 Clock - * return Frequency of Usb0 Clock. - */ -uint32_t CLOCK_GetUsb0ClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->USB0CLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 5U: - freq = CLOCK_GetPll1OutFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - assert(false); - break; - } - - return freq / ((SYSCON->USB0CLKDIV & 0xffU) + 1U); -} - -/* Get USB1 Clk */ -/*! brief Return Frequency of Usb1 Clock - * return Frequency of Usb1 Clock. - */ -uint32_t CLOCK_GetUsb1ClkFreq(void) -{ - return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; -} - -/* Get MCLK Clk */ -/*! brief Return Frequency of MClk Clock - * return Frequency of MClk Clock. - */ -uint32_t CLOCK_GetMclkClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->MCLKCLKSEL) - { - case 0U: - freq = CLOCK_GetFroHfFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - assert(false); - break; - } - - return freq / ((SYSCON->MCLKDIV & 0xffU) + 1U); -} - -/* Get SCTIMER Clk */ -/*! brief Return Frequency of SCTimer Clock - * return Frequency of SCTimer Clock. - */ -uint32_t CLOCK_GetSctClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->SCTCLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 2U: - freq = CLOCK_GetExtClkFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 5U: - freq = CLOCK_GetI2SMClkFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - assert(false); - break; - } - - return freq / ((SYSCON->SCTCLKDIV & 0xffU) + 1U); -} - -/* Get SDIO Clk */ -/*! brief Return Frequency of SDIO Clock - * return Frequency of SDIO Clock. - */ -uint32_t CLOCK_GetSdioClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->SDIOCLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 5U: - freq = CLOCK_GetPll1OutFreq(); - break; - case 7U: - freq = 0U; - break; - default: - assert(false); - break; - } - - return freq / ((SYSCON->SDIOCLKDIV & 0xffU) + 1U); -} - -/* Get FRO 12M Clk */ -/*! brief Return Frequency of FRO 12MHz - * return Frequency of FRO 12MHz - */ -uint32_t CLOCK_GetFro12MFreq(void) -{ - return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; -} - -/* Get FRO 1M Clk */ -/*! brief Return Frequency of FRO 1MHz - * return Frequency of FRO 1MHz - */ -uint32_t CLOCK_GetFro1MFreq(void) -{ - return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; -} - -/* Get EXT OSC Clk */ -/*! brief Return Frequency of External Clock - * return Frequency of External Clock. If no external clock is used returns 0. - */ -uint32_t CLOCK_GetExtClkFreq(void) -{ - return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; -} - -/* Get WATCH DOG Clk */ -/*! brief Return Frequency of Watchdog - * return Frequency of Watchdog - */ -uint32_t CLOCK_GetWdtClkFreq(void) -{ - return CLOCK_GetFro1MFreq() / ((SYSCON->WDTCLKDIV & SYSCON_WDTCLKDIV_DIV_MASK) + 1U); -} - -/* Get HF FRO Clk */ -/*! brief Return Frequency of High-Freq output of FRO - * return Frequency of High-Freq output of FRO - */ -uint32_t CLOCK_GetFroHfFreq(void) -{ - return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; -} - -/* Get SYSTEM PLL Clk */ -/*! brief Return Frequency of PLL - * return Frequency of PLL - */ -uint32_t CLOCK_GetPll0OutFreq(void) -{ - return s_Pll0_Freq; -} - -/* Get USB PLL Clk */ -/*! brief Return Frequency of USB PLL - * return Frequency of PLL - */ -uint32_t CLOCK_GetPll1OutFreq(void) -{ - return s_Pll1_Freq; -} - -/* Get RTC OSC Clk */ -/*! brief Return Frequency of 32kHz osc - * return Frequency of 32kHz osc - */ -uint32_t CLOCK_GetOsc32KFreq(void) -{ - return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && - (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? - CLK_RTC_32K_CLK : - ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && - (0UL != (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? - CLK_RTC_32K_CLK : - 0U; -} - -/* Get MAIN Clk */ -/*! brief Return Frequency of Core System - * return Frequency of Core System - */ -uint32_t CLOCK_GetCoreSysClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->MAINCLKSELB) - { - case 0U: - if (SYSCON->MAINCLKSELA == 0U) - { - freq = CLOCK_GetFro12MFreq(); - } - else if (SYSCON->MAINCLKSELA == 1U) - { - freq = CLOCK_GetExtClkFreq(); - } - else if (SYSCON->MAINCLKSELA == 2U) - { - freq = CLOCK_GetFro1MFreq(); - } - else if (SYSCON->MAINCLKSELA == 3U) - { - freq = CLOCK_GetFroHfFreq(); - } - else - { - /* Add comments to prevent the case of MISRA C-2012 rule 15.7. */ - } - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 2U: - freq = CLOCK_GetPll1OutFreq(); - break; - - case 3U: - freq = CLOCK_GetOsc32KFreq(); - break; - - default: - freq = 0U; - break; - } - - return freq; -} - -/* Get I2S MCLK Clk */ -/*! brief Return Frequency of I2S MCLK Clock - * return Frequency of I2S MCLK Clock - */ -uint32_t CLOCK_GetI2SMClkFreq(void) -{ - return s_I2S_Mclk_Freq; -} - -/* Get PLU CLKIN Clk */ -/*! brief Return Frequency of PLU CLKIN Clock - * return Frequency of PLU CLKIN Clock - */ -uint32_t CLOCK_GetPLUClkInFreq(void) -{ - return s_PLU_ClkIn_Freq; -} - -/* Get FLEXCOMM input clock */ -/*! brief Return Frequency of flexcomm input clock - * param id : flexcomm instance id - * return Frequency value - */ -uint32_t CLOCK_GetFlexCommInputClock(uint32_t id) -{ - uint32_t freq = 0U; - - switch (SYSCON->FCCLKSELX[id]) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U); - break; - case 2U: - freq = CLOCK_GetFro12MFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); - break; - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - case 5U: - freq = CLOCK_GetI2SMClkFreq(); - break; - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - assert(false); - break; - } - - return freq; -} - -/* Get FLEXCOMM Clk */ -uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) -{ - uint32_t freq = 0U; - uint32_t frgMul = 0U; - uint32_t frgDiv = 0U; - - freq = CLOCK_GetFlexCommInputClock(id); - frgMul = (SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_MULT_MASK) >> 8U; - frgDiv = SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_DIV_MASK; - return (uint32_t)(((uint64_t)freq * ((uint64_t)frgDiv + 1ULL)) / (frgMul + frgDiv + 1UL)); -} - -/* Get HS_LPSI Clk */ -uint32_t CLOCK_GetHsLspiClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->HSLSPICLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U); - break; - case 2U: - freq = CLOCK_GetFro12MFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); - break; - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - assert(false); - break; - } - - return freq; -} - -/* Get CTimer Clk */ -/*! brief Return Frequency of CTimer functional Clock - * return Frequency of CTimer functional Clock - */ -uint32_t CLOCK_GetCTimerClkFreq(uint32_t id) -{ - uint32_t freq = 0U; - - switch (SYSCON->CTIMERCLKSELX[id]) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - case 5U: - freq = CLOCK_GetI2SMClkFreq(); - break; - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - assert(false); - break; - } - - return freq; -} - -/* Get Systick Clk */ -/*! brief Return Frequency of SystickClock - * return Frequency of Systick Clock - */ -uint32_t CLOCK_GetSystickClkFreq(uint32_t id) -{ - volatile uint32_t *pSystickClkDiv; - pSystickClkDiv = &(SYSCON->SYSTICKCLKDIV0); - uint32_t freq = 0U; - - switch (SYSCON->SYSTICKCLKSELX[id]) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq() / ((((volatile uint32_t *)pSystickClkDiv)[(uint32_t)id] & 0xffU) + 1U); - break; - case 1U: - freq = CLOCK_GetFro1MFreq(); - break; - case 2U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - freq = 0U; - break; - } - - return freq; -} - -/* Set FlexComm Clock */ -/** - * brief Set the flexcomm output frequency. - * param id : flexcomm instance id - * freq : output frequency - * return 0 : the frequency range is out of range. - * 1 : switch successfully. - */ -uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq) -{ - uint32_t input = CLOCK_GetFlexCommClkFreq(id); - uint32_t mul; - - if ((freq > 48000000UL) || (freq > input) || (input / freq >= 2UL)) - { - /* FRG output frequency should be less than equal to 48MHz */ - return 0UL; - } - else - { - mul = (uint32_t)((((uint64_t)input - freq) * 256ULL) / ((uint64_t)freq)); - SYSCON->FLEXFRGXCTRL[id] = (mul << 8U) | 0xFFU; - return 1UL; - } -} - -/* Get IP Clk */ -/*! brief Return Frequency of selected clock - * return Frequency of selected clock - */ -uint32_t CLOCK_GetFreq(clock_name_t clockName) -{ - uint32_t freq; - switch (clockName) - { - case kCLOCK_CoreSysClk: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case kCLOCK_BusClk: - freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); - break; - case kCLOCK_ClockOut: - freq = CLOCK_GetClockOutClkFreq(); - break; - case kCLOCK_Pll1Out: - freq = CLOCK_GetPll1OutFreq(); - break; - case kCLOCK_Mclk: - freq = CLOCK_GetMclkClkFreq(); - break; - case kCLOCK_FroHf: - freq = CLOCK_GetFroHfFreq(); - break; - case kCLOCK_Fro12M: - freq = CLOCK_GetFro12MFreq(); - break; - case kCLOCK_ExtClk: - freq = CLOCK_GetExtClkFreq(); - break; - case kCLOCK_Pll0Out: - freq = CLOCK_GetPll0OutFreq(); - break; - case kCLOCK_FlexI2S: - freq = CLOCK_GetI2SMClkFreq(); - break; - default: - freq = 0U; - break; - } - return freq; -} - -/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ -static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) -{ - uint32_t seli, selp; - /* bandwidth: compute selP from Multiplier */ - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ - { - selp = (M >> 2U) + 1U; - if (selp >= 31U) - { - selp = 31U; - } - *pSelP = selp; - - if (M >= 8000UL) - { - seli = 1UL; - } - else if (M >= 122UL) - { - seli = (uint32_t)(8000UL / M); /*floor(8000/M) */ - } - else - { - seli = 2UL * ((uint32_t)(M / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ - } - - if (seli >= 63UL) - { - seli = 63UL; - } - *pSelI = seli; - - *pSelR = 0U; - } - else - { - /* Note: If the spread spectrum mode, choose N to ensure 3 MHz < Fin/N < 5 MHz */ - *pSelP = 3U; - *pSelI = 4U; - *pSelR = 4U; - } -} - -/* Get predivider (N) from PLL0 NDEC setting */ -static uint32_t findPll0PreDiv(void) -{ - uint32_t preDiv = 1UL; - - /* Direct input is not used? */ - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) - { - preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; - if (preDiv == 0UL) - { - preDiv = 1UL; - } - } - return preDiv; -} - -/* Get predivider (N) from PLL1 NDEC setting */ -static uint32_t findPll1PreDiv(void) -{ - uint32_t preDiv = 1UL; - - /* Direct input is not used? */ - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) - { - preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; - if (preDiv == 0UL) - { - preDiv = 1UL; - } - } - return preDiv; -} - -/* Get postdivider (P) from PLL0 PDEC setting */ -static uint32_t findPll0PostDiv(void) -{ - uint32_t postDiv = 1UL; - - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) - { - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) - { - postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; - } - else - { - postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); - } - if (postDiv == 0UL) - { - postDiv = 2UL; - } - } - return postDiv; -} - -/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ -static float findPll0MMult(void) -{ - float mMult = 1.0F; - float mMult_fract; - uint32_t mMult_int; - - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) - { - mMult = - (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); - } - else - { - mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); - mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL0_SSCG_MD_INT_P); - mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL0_SSCG_MD_FRACT_M) / - (float)(uint32_t)(1UL << PLL0_SSCG_MD_INT_P)); - mMult = (float)mMult_int + mMult_fract; - } - if(0ULL == ((uint64_t)mMult)) - { - mMult = 1.0F; - } - return mMult; -} - -/* Find greatest common divisor between m and n */ -static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) -{ - uint32_t tmp; - - while (n != 0U) - { - tmp = n; - n = m % n; - m = tmp; - } - - return m; -} - -/* - * Set PLL0 output based on desired output rate. - * In this function, the it calculates the PLL0 setting for output frequency from input clock - * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. - * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. - */ -static pll_error_t CLOCK_GetPll0ConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) -{ - uint32_t nDivOutHz, fccoHz; - uint32_t pllPreDivider, pllMultiplier, pllPostDivider; - uint32_t pllDirectInput, pllDirectOutput; - uint32_t pllSelP, pllSelI, pllSelR, uplimoff; - - /* Baseline parameters (no input or output dividers) */ - pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ - pllPostDivider = 1U; /* 1 implies post-divider will be disabled */ - pllDirectOutput = 1U; - - /* Verify output rate parameter */ - if (foutHz > PLL_MAX_CCO_FREQ_MHZ) - { - /* Maximum PLL output with post divider=1 cannot go above this frequency */ - return kStatus_PLL_OutputTooHigh; - } - if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) - { - /* Minmum PLL output with maximum post divider cannot go below this frequency */ - return kStatus_PLL_OutputTooLow; - } - - /* If using SS mode, input clock needs to be between 3MHz and 20MHz */ - if (useSS) - { - /* Verify input rate parameter */ - if (finHz < PLL_MIN_IN_SSMODE) - { - /* Input clock into the PLL cannot be lower than this */ - return kStatus_PLL_InputTooLow; - } - /* PLL input in SS mode must be under 20MHz */ - if (finHz > (PLL_MAX_IN_SSMODE * NVALMAX)) - { - return kStatus_PLL_InputTooHigh; - } - } - else - { - /* Verify input rate parameter */ - if (finHz < PLL_LOWER_IN_LIMIT) - { - /* Input clock into the PLL cannot be lower than this */ - return kStatus_PLL_InputTooLow; - } - if (finHz > PLL_HIGHER_IN_LIMIT) - { - /* Input clock into the PLL cannot be higher than this */ - return kStatus_PLL_InputTooHigh; - } - } - - /* Find the optimal CCO frequency for the output and input that - will keep it inside the PLL CCO range. This may require - tweaking the post-divider for the PLL. */ - fccoHz = foutHz; - while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) - { - /* CCO output is less than minimum CCO range, so the CCO output - needs to be bumped up and the post-divider is used to bring - the PLL output back down. */ - pllPostDivider++; - if (pllPostDivider > PVALMAX) - { - return kStatus_PLL_OutsideIntLimit; - } - - /* Target CCO goes up, PLL output goes down */ - /* divide-by-2 divider in the post-divider is always work*/ - fccoHz = foutHz * (pllPostDivider * 2U); - pllDirectOutput = 0U; - } - - /* Determine if a pre-divider is needed to get the best frequency */ - if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) - { - uint32_t a = FindGreatestCommonDivisor(fccoHz, finHz); - - if (a > PLL_LOWER_IN_LIMIT) - { - a = finHz / a; - if ((a != 0U) && (a < PLL_MAX_N_DIV)) - { - pllPreDivider = a; - } - } - } - - /* Bypass pre-divider hardware if pre-divider is 1 */ - if (pllPreDivider > 1U) - { - pllDirectInput = 0U; - } - else - { - pllDirectInput = 1U; - } - - /* Determine PLL multipler */ - nDivOutHz = (finHz / pllPreDivider); - pllMultiplier = (fccoHz / nDivOutHz); - - /* Find optimal values for filter */ - if (useSS == false) - { - /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ - if ((nDivOutHz * ((pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) - { - pllMultiplier++; - } - - /* Setup filtering */ - pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR); - uplimoff = 0U; - - /* Get encoded value for M (mult) and use manual filter, disable SS mode */ - pSetup->pllsscg[1] = - (uint32_t)((PLL_SSCG1_MDEC_VAL_SET(pllMultiplier)) | (1UL << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)); - } - else - { - uint64_t fc; - - /* Filtering will be handled by SSC */ - pllSelR = 0U; - pllSelI = 0U; - pllSelP = 0U; - uplimoff = 1U; - - /* The PLL multiplier will get very close and slightly under the - desired target frequency. A small fractional component can be - added to fine tune the frequency upwards to the target. */ - fc = (((uint64_t)fccoHz % (uint64_t)nDivOutHz) << 25U) / nDivOutHz; - - /* Set multiplier */ - pSetup->pllsscg[0] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) | PLL0_SSCG_MD_FRACT_SET((uint32_t)fc)); - pSetup->pllsscg[1] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) >> 32U); - } - - /* Get encoded values for N (prediv) and P (postdiv) */ - pSetup->pllndec = PLL_NDEC_VAL_SET(pllPreDivider); - pSetup->pllpdec = PLL_PDEC_VAL_SET(pllPostDivider); - - /* PLL control */ - pSetup->pllctrl = (pllSelR << SYSCON_PLL0CTRL_SELR_SHIFT) | /* Filter coefficient */ - (pllSelI << SYSCON_PLL0CTRL_SELI_SHIFT) | /* Filter coefficient */ - (pllSelP << SYSCON_PLL0CTRL_SELP_SHIFT) | /* Filter coefficient */ - (0UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT) | /* PLL bypass mode disabled */ - (uplimoff << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */ - (pllDirectInput << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */ - (pllDirectOutput << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT) | /* Bypass post-divider? */ - (1UL << SYSCON_PLL0CTRL_CLKEN_SHIFT); /* Ensure the PLL clock output */ - - return kStatus_PLL_Success; -} - -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) -/* Alloct the static buffer for cache. */ -static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; -static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; -static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; -static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; -static uint32_t s_PllSetupCacheIdx = 0U; -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - -/* - * Calculate the PLL setting values from input clock freq to output freq. - */ -static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) -{ - pll_error_t retErr; -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - uint32_t i; - - for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) - { - if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && (useSS == s_UseSSCache[i])) - { - /* Hit the target in cache buffer. */ - pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl; - pSetup->pllndec = s_PllSetupCacheStruct[i].pllndec; - pSetup->pllpdec = s_PllSetupCacheStruct[i].pllpdec; - pSetup->pllsscg[0] = s_PllSetupCacheStruct[i].pllsscg[0]; - pSetup->pllsscg[1] = s_PllSetupCacheStruct[i].pllsscg[1]; - retErr = kStatus_PLL_Success; - break; - } - } - - if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - { - return retErr; - } -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - - retErr = CLOCK_GetPll0ConfigInternal(finHz, foutHz, pSetup, useSS); - -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - /* Cache the most recent calulation result into buffer. */ - s_FinHzCache[s_PllSetupCacheIdx] = finHz; - s_FoutHzCache[s_PllSetupCacheIdx] = foutHz; - s_UseSSCache[s_PllSetupCacheIdx] = useSS; - - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndec = pSetup->pllndec; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdec = pSetup->pllpdec; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[0] = pSetup->pllsscg[0]; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[1] = pSetup->pllsscg[1]; - /* Update the index for next available buffer. */ - s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - - return retErr; -} - -/* Update local PLL rate variable */ -static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup) -{ - s_Pll0_Freq = CLOCK_GetPLL0OutFromSetup(pSetup); -} - -/* Return System PLL input clock rate */ -/*! brief Return PLL0 input clock rate - * return PLL0 input clock rate - */ -uint32_t CLOCK_GetPLL0InClockRate(void) -{ - uint32_t clkRate = 0U; - - switch ((SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK)) - { - case 0x00U: - clkRate = CLK_FRO_12MHZ; - break; - - case 0x01U: - clkRate = CLOCK_GetExtClkFreq(); - break; - - case 0x02U: - clkRate = CLOCK_GetFro1MFreq(); - break; - - case 0x03U: - clkRate = CLOCK_GetOsc32KFreq(); - break; - - default: - clkRate = 0U; - break; - } - - return clkRate; -} - -/* Return PLL1 input clock rate */ -uint32_t CLOCK_GetPLL1InClockRate(void) -{ - uint32_t clkRate = 0U; - - switch ((SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK)) - { - case 0x00U: - clkRate = CLK_FRO_12MHZ; - break; - - case 0x01U: - clkRate = CLOCK_GetExtClkFreq(); - break; - - case 0x02U: - clkRate = CLOCK_GetFro1MFreq(); - break; - - case 0x03U: - clkRate = CLOCK_GetOsc32KFreq(); - break; - - default: - clkRate = 0U; - break; - } - - return clkRate; -} - -/* Return PLL0 output clock rate from setup structure */ -/*! brief Return PLL0 output clock rate from setup structure - * param pSetup : Pointer to a PLL setup structure - * return PLL0 output clock rate the setup structure will generate - */ -uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup) -{ - uint32_t clkRate = 0; - uint32_t prediv, postdiv; - float workRate = 0.0F; - - /* Get the input clock frequency of PLL. */ - clkRate = CLOCK_GetPLL0InClockRate(); - - if (((pSetup->pllctrl & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && - ((pSetup->pllctrl & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && - ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && - ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) - { - prediv = findPll0PreDiv(); - postdiv = findPll0PostDiv(); - /* Adjust input clock */ - clkRate = clkRate / prediv; - /* MDEC used for rate */ - workRate = (float)clkRate * (float)findPll0MMult(); - workRate /= (float)postdiv; - } - - return (uint32_t)workRate; -} - -/* Set the current PLL0 Rate */ -/*! brief Store the current PLL rate - * param rate: Current rate of the PLL - * return Nothing - **/ -void CLOCK_SetStoredPLL0ClockRate(uint32_t rate) -{ - s_Pll0_Freq = rate; -} - -/* Return PLL0 output clock rate */ -/*! brief Return PLL0 output clock rate - * param recompute : Forces a PLL rate recomputation if true - * return PLL0 output clock rate - * note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetPLL0OutClockRate(bool recompute) -{ - pll_setup_t Setup; - uint32_t rate; - - if ((recompute) || (s_Pll0_Freq == 0U)) - { - Setup.pllctrl = SYSCON->PLL0CTRL; - Setup.pllndec = SYSCON->PLL0NDEC; - Setup.pllpdec = SYSCON->PLL0PDEC; - Setup.pllsscg[0] = SYSCON->PLL0SSCG0; - Setup.pllsscg[1] = SYSCON->PLL0SSCG1; - - CLOCK_GetPLL0OutFromSetupUpdate(&Setup); - } - - rate = s_Pll0_Freq; - - return rate; -} - -/* Set PLL0 output based on the passed PLL setup data */ -/*! brief Set PLL output based on the passed PLL setup data - * param pControl : Pointer to populated PLL control structure to generate setup with - * param pSetup : Pointer to PLL setup structure to be filled - * return PLL_ERROR_SUCCESS on success, or PLL setup error code - * note Actual frequency for setup may vary from the desired frequency based on the - * accuracy of input clocks, rounding, non-fractional PLL mode, etc. - */ -pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup) -{ - uint32_t inRate; - bool useSS = ((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0U); - - pll_error_t pllError; - - /* Determine input rate for the PLL */ - if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U) - { - inRate = pControl->inputRate; - } - else - { - inRate = CLOCK_GetPLL0InClockRate(); - } - - /* PLL flag options */ - pllError = CLOCK_GetPll0Config(inRate, pControl->desiredRate, pSetup, useSS); - if ((useSS) && (pllError == kStatus_PLL_Success)) - { - /* If using SS mode, then some tweaks are made to the generated setup */ - pSetup->pllsscg[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc; - if (pControl->mfDither) - { - pSetup->pllsscg[1] |= (1UL << SYSCON_PLL0SSCG1_DITHER_SHIFT); - } - } - - return pllError; -} - -/* Set PLL0 output from PLL setup structure */ -/*! brief Set PLL output from PLL setup structure (precise frequency) - * param pSetup : Pointer to populated PLL setup structure - * param flagcfg : Flag configuration for PLL config structure - * return PLL_ERROR_SUCCESS on success, or PLL setup error code - * note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg) -{ - uint32_t inRate, clkRate, prediv; - - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_PLL0); - POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); - - pSetup->flags = flagcfg; - - /* Write PLL setup data */ - SYSCON->PLL0CTRL = pSetup->pllctrl; - SYSCON->PLL0NDEC = pSetup->pllndec; - SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ - SYSCON->PLL0PDEC = pSetup->pllpdec; - SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ - SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; - SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; - SYSCON->PLL0SSCG1 = - pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT); /* latch */ - - POWER_DisablePD(kPDRUNCFG_PD_PLL0); - POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); - - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) - { - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ - { - inRate = CLOCK_GetPLL0InClockRate(); - prediv = findPll0PreDiv(); - /* Adjust input clock */ - clkRate = inRate / prediv; - /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ - if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) - { - while (CLOCK_IsPLL0Locked() == false) - { - } - } - else - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval - to insure the PLL will be stable */ - } - } - else /* spread spectrum mode */ - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to - insure the PLL will be stable */ - } - } - - /* Update current programmed PLL rate var */ - CLOCK_GetPLL0OutFromSetupUpdate(pSetup); - - /* System voltage adjustment, occurs prior to setting main system clock */ - if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U) - { - POWER_SetVoltageForFreq(s_Pll0_Freq); - } - - return kStatus_PLL_Success; -} - -/* Setup PLL Frequency from pre-calculated value */ -/** - * brief Set PLL0 output from PLL setup structure (precise frequency) - * param pSetup : Pointer to populated PLL setup structure - * return kStatus_PLL_Success on success, or PLL setup error code - * note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup) -{ - uint32_t inRate, clkRate, prediv; - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_PLL0); - POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); - - /* Write PLL setup data */ - SYSCON->PLL0CTRL = pSetup->pllctrl; - SYSCON->PLL0NDEC = pSetup->pllndec; - SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ - SYSCON->PLL0PDEC = pSetup->pllpdec; - SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ - SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; - SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; - SYSCON->PLL0SSCG1 = - pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* latch */ - - POWER_DisablePD(kPDRUNCFG_PD_PLL0); - POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); - - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) - { - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ - { - inRate = CLOCK_GetPLL0InClockRate(); - prediv = findPll0PreDiv(); - /* Adjust input clock */ - clkRate = inRate / prediv; - /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ - if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) - { - while (CLOCK_IsPLL0Locked() == false) - { - } - } - else - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval - to insure the PLL will be stable */ - } - } - else /* spread spectrum mode */ - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to - insure the PLL will be stable */ - } - } - - /* Update current programmed PLL rate var */ - s_Pll0_Freq = pSetup->pllRate; - - return kStatus_PLL_Success; -} - -/* Setup PLL1 Frequency from pre-calculated value */ -/** - * brief Set PLL1 output from PLL setup structure (precise frequency) - * param pSetup : Pointer to populated PLL setup structure - * return kStatus_PLL_Success on success, or PLL setup error code - * note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup) -{ - uint32_t inRate, clkRate, prediv; - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_PLL1); - - /* Write PLL setup data */ - SYSCON->PLL1CTRL = pSetup->pllctrl; - SYSCON->PLL1NDEC = pSetup->pllndec; - SYSCON->PLL1NDEC = pSetup->pllndec | (1UL << SYSCON_PLL1NDEC_NREQ_SHIFT); /* latch */ - SYSCON->PLL1PDEC = pSetup->pllpdec; - SYSCON->PLL1PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL1PDEC_PREQ_SHIFT); /* latch */ - SYSCON->PLL1MDEC = pSetup->pllmdec; - SYSCON->PLL1MDEC = pSetup->pllmdec | (1UL << SYSCON_PLL1MDEC_MREQ_SHIFT); /* latch */ - - POWER_DisablePD(kPDRUNCFG_PD_PLL1); - - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) - { - inRate = CLOCK_GetPLL1InClockRate(); - prediv = findPll1PreDiv(); - /* Adjust input clock */ - clkRate = inRate / prediv; - /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ - if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) - { - while (CLOCK_IsPLL1Locked() == false) - { - } - } - else - { - SDK_DelayAtLeastUs(6000U, - SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to - insure the PLL will be stable */ - } - } - - /* Update current programmed PLL rate var */ - s_Pll1_Freq = pSetup->pllRate; - - return kStatus_PLL_Success; -} - -/* Set PLL0 clock based on the input frequency and multiplier */ -/*! brief Set PLL0 output based on the multiplier and input frequency - * param multiply_by : multiplier - * param input_freq : Clock input frequency of the PLL - * return Nothing - * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this - * function does not disable or enable PLL power, wait for PLL lock, - * or adjust system voltages. These must be done in the application. - * The function will not alter any source clocks (ie, main systen clock) - * that may use the PLL, so these should be setup prior to and after - * exiting the function. - */ -void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq) -{ - uint32_t cco_freq = input_freq * multiply_by; - uint32_t pdec = 1U; - uint32_t selr; - uint32_t seli; - uint32_t selp; - uint32_t mdec, ndec; - - while (cco_freq < 275000000U) - { - multiply_by <<= 1U; /* double value in each iteration */ - pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */ - cco_freq = input_freq * multiply_by; - } - - selr = 0U; - - if (multiply_by >= 8000UL) - { - seli = 1UL; - } - else if (multiply_by >= 122UL) - { - seli = (uint32_t)(8000UL / multiply_by); /*floor(8000/M) */ - } - else - { - seli = 2UL * ((uint32_t)(multiply_by / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ - } - - if (seli >= 63U) - { - seli = 63U; - } - - { - selp = 31U; - } - - if (pdec > 1U) - { - pdec = pdec / 2U; /* Account for minus 1 encoding */ - /* Translate P value */ - } - - mdec = (uint32_t)PLL_SSCG1_MDEC_VAL_SET(multiply_by); - ndec = 0x1U; /* pre divide by 1 (hardcoded) */ - - SYSCON->PLL0CTRL = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_BYPASSPOSTDIV(0) | - SYSCON_PLL0CTRL_BYPASSPOSTDIV2(0) | (selr << SYSCON_PLL0CTRL_SELR_SHIFT) | - (seli << SYSCON_PLL0CTRL_SELI_SHIFT) | (selp << SYSCON_PLL0CTRL_SELP_SHIFT); - SYSCON->PLL0PDEC = pdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* set Pdec value and assert preq */ - SYSCON->PLL0NDEC = ndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* set Pdec value and assert preq */ - SYSCON->PLL0SSCG1 = - mdec | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* select non sscg MDEC value, assert mreq and select mdec value */ -} - -/* Enable USB DEVICE FULL SPEED clock */ -/*! brief Enable USB Device FS clock. - * param src : clock source - * param freq: clock frequency - * Enable USB Device Full Speed clock. - */ -bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq) -{ - bool ret = true; - - CLOCK_DisableClock(kCLOCK_Usbd0); - - if (kCLOCK_UsbfsSrcFro == src) - { - switch (freq) - { - case 96000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ - break; - - default: - ret = false; - break; - } - /* Turn ON FRO HF */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); - /* Enable FRO 96MHz output */ - ANACTRL->FRO192M_CTRL = - ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK | ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK; - /* Select FRO 96 or 48 MHz */ - CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); - } - else - { - /*!< Configure XTAL32M */ - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ - (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ - - /*!< Set up PLL1 */ - POWER_DisablePD(kPDRUNCFG_PD_PLL1); - CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ - const pll_setup_t pll1Setup = { - .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U), - .pllndec = SYSCON_PLL1NDEC_NDIV(1U), - .pllpdec = SYSCON_PLL1PDEC_PDIV(5U), - .pllmdec = SYSCON_PLL1MDEC_MDIV(30U), - .pllRate = 48000000U, - .flags = PLL_SETUPFLAG_WAITLOCK}; - (void)CLOCK_SetPLL1Freq(&pll1Setup); - - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); - CLOCK_AttachClk(kPLL1_to_USB0_CLK); - SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - } - CLOCK_EnableClock(kCLOCK_Usbd0); - CLOCK_EnableClock(kCLOCK_UsbRam1); - - return ret; -} - -/* Enable USB HOST FULL SPEED clock */ -/*! brief Enable USB HOST FS clock. - * param src : clock source - * param freq: clock frequency - * Enable USB HOST Full Speed clock. - */ -bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq) -{ - bool ret = true; - - CLOCK_DisableClock(kCLOCK_Usbhmr0); - CLOCK_DisableClock(kCLOCK_Usbhsl0); - - if (kCLOCK_UsbfsSrcFro == src) - { - switch (freq) - { - case 96000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ - break; - - default: - ret = false; - break; - } - /* Turn ON FRO HF */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); - /* Enable FRO 96MHz output */ - ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; - /* Select FRO 96 MHz */ - CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); - } - else - { - /*!< Configure XTAL32M */ - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ - (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ - - /*!< Set up PLL1 */ - POWER_DisablePD(kPDRUNCFG_PD_PLL1); - CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ - const pll_setup_t pll1Setup = { - .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U), - .pllndec = SYSCON_PLL1NDEC_NDIV(1U), - .pllpdec = SYSCON_PLL1PDEC_PDIV(5U), - .pllmdec = SYSCON_PLL1MDEC_MDIV(30U), - .pllRate = 48000000U, - .flags = PLL_SETUPFLAG_WAITLOCK}; - (void)CLOCK_SetPLL1Freq(&pll1Setup); - - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); - CLOCK_AttachClk(kPLL1_to_USB0_CLK); - SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - } - CLOCK_EnableClock(kCLOCK_Usbhmr0); - CLOCK_EnableClock(kCLOCK_Usbhsl0); - CLOCK_EnableClock(kCLOCK_UsbRam1); - - return ret; -} - -/* Enable USB PHY clock */ -bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) -{ - volatile uint32_t i; - uint32_t phyPllDiv = 0U; - uint16_t multiplier = 0U; - bool ret = true; - - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); - POWER_DisablePD(kPDRUNCFG_PD_FRO32K); /*!< Ensure FRO32k is on */ - POWER_DisablePD(kPDRUNCFG_PD_XTAL32K); /*!< Ensure xtal32k is on */ - POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /*!< Ensure xtal32k is on */ - POWER_DisablePD(kPDRUNCFG_PD_LDOUSBHS); /*!< Ensure xtal32k is on */ - - /* wait to make sure PHY power is fully up */ - i = 100000U; - while ((i--) != 0U) - { - __ASM("nop"); - } - - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL(1); - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_PHY(1); - - USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; - - multiplier = (uint16_t)(480000000UL / freq); - - switch (multiplier) - { - case 15U: - { - phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(0U); - break; - } - case 16U: - { - phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(1U); - break; - } - case 20U: - { - phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(2U); - break; - } - case 24U: - { - phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(4U); - break; - } - case 25U: - { - phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(5U); - break; - } - case 30U: - { - phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(6U); - break; - } - case 40U: - { - phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(7U); - break; - } - default: - { - ret = false; - break; - } - } - - if (ret) - { - USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | phyPllDiv; - USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK; - USBPHY->PLL_SIC_CLR = (1UL << 16U); // Reserved. User must set this bit to 0x0 - USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_POWER_MASK; - USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK; - - USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; - USBPHY->PWD_SET = 0x0; - } - - return ret; -} - -/* Enable USB DEVICE HIGH SPEED clock */ -bool CLOCK_EnableUsbhs0DeviceClock(clock_usbhs_src_t src, uint32_t freq) -{ - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1); - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_DEV(1); - - /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1); - return true; -} - -/* Enable USB HOST HIGH SPEED clock */ -bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq) -{ - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1); - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_HOST(1); - - /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1); - - return true; -} - -/*! @brief Enable the OSTIMER 32k clock. - * @return Nothing - */ -void CLOCK_EnableOstimer32kClock(void) -{ - PMC->OSTIMERr |= PMC_OSTIMER_CLOCKENABLE_MASK; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_clock.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_clock.h deleted file mode 100644 index 8ad899be1f0..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_clock.h +++ /dev/null @@ -1,1506 +0,0 @@ -/* - * Copyright 2017 - 2021 , NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CLOCK_H_ -#define _FSL_CLOCK_H_ - -#include "fsl_common.h" - -/*! @addtogroup clock */ -/*! @{ */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CLOCK driver version 2.3.6. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 6)) -/*@}*/ - -/*! @brief Configure whether driver controls clock - * - * When set to 0, peripheral drivers will enable clock in initialize function - * and disable clock in de-initialize function. When set to 1, peripheral - * driver will not control the clock, application could control the clock out of - * the driver. - * - * @note All drivers share this feature switcher. If it is set to 1, application - * should handle clock enable and disable for all drivers. - */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) -#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 -#endif - -/*! - * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. - * - * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function - * would cache the recent calulation and accelerate the execution to get the - * right settings. - */ -#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT -#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U -#endif - -/* Definition for delay API in clock driver, users can redefine it to the real application. */ -#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY -#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (150000000UL) -#endif - -/*! @brief Clock ip name array for ROM. */ -#define ROM_CLOCKS \ - { \ - kCLOCK_Rom \ - } -/*! @brief Clock ip name array for SRAM. */ -#define SRAM_CLOCKS \ - { \ - kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3, kCLOCK_Sram4 \ - } -/*! @brief Clock ip name array for FLASH. */ -#define FLASH_CLOCKS \ - { \ - kCLOCK_Flash \ - } -/*! @brief Clock ip name array for FMC. */ -#define FMC_CLOCKS \ - { \ - kCLOCK_Fmc \ - } -/*! @brief Clock ip name array for INPUTMUX. */ -#define INPUTMUX_CLOCKS \ - { \ - kCLOCK_InputMux0 \ - } -/*! @brief Clock ip name array for IOCON. */ -#define IOCON_CLOCKS \ - { \ - kCLOCK_Iocon \ - } -/*! @brief Clock ip name array for GPIO. */ -#define GPIO_CLOCKS \ - { \ - kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3 \ - } -/*! @brief Clock ip name array for PINT. */ -#define PINT_CLOCKS \ - { \ - kCLOCK_Pint \ - } -/*! @brief Clock ip name array for GINT. */ -#define GINT_CLOCKS \ - { \ - kCLOCK_Gint, kCLOCK_Gint \ - } -/*! @brief Clock ip name array for DMA. */ -#define DMA_CLOCKS \ - { \ - kCLOCK_Dma0, kCLOCK_Dma1 \ - } -/*! @brief Clock ip name array for CRC. */ -#define CRC_CLOCKS \ - { \ - kCLOCK_Crc \ - } -/*! @brief Clock ip name array for WWDT. */ -#define WWDT_CLOCKS \ - { \ - kCLOCK_Wwdt \ - } -/*! @brief Clock ip name array for RTC. */ -#define RTC_CLOCKS \ - { \ - kCLOCK_Rtc \ - } -/*! @brief Clock ip name array for Mailbox. */ -#define MAILBOX_CLOCKS \ - { \ - kCLOCK_Mailbox \ - } -/*! @brief Clock ip name array for LPADC. */ -#define LPADC_CLOCKS \ - { \ - kCLOCK_Adc0 \ - } -/*! @brief Clock ip name array for MRT. */ -#define MRT_CLOCKS \ - { \ - kCLOCK_Mrt \ - } -/*! @brief Clock ip name array for OSTIMER. */ -#define OSTIMER_CLOCKS \ - { \ - kCLOCK_OsTimer0 \ - } -/*! @brief Clock ip name array for SCT0. */ -#define SCT_CLOCKS \ - { \ - kCLOCK_Sct0 \ - } -/*! @brief Clock ip name array for UTICK. */ -#define UTICK_CLOCKS \ - { \ - kCLOCK_Utick0 \ - } -/*! @brief Clock ip name array for FLEXCOMM. */ -#define FLEXCOMM_CLOCKS \ - { \ - kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \ - kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi \ - } -/*! @brief Clock ip name array for LPUART. */ -#define LPUART_CLOCKS \ - { \ - kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \ - kCLOCK_MinUart6, kCLOCK_MinUart7 \ - } - -/*! @brief Clock ip name array for BI2C. */ -#define BI2C_CLOCKS \ - { \ - kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \ - } -/*! @brief Clock ip name array for LSPI. */ -#define LPSPI_CLOCKS \ - { \ - kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \ - } -/*! @brief Clock ip name array for FLEXI2S. */ -#define FLEXI2S_CLOCKS \ - { \ - kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \ - kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \ - } -/*! @brief Clock ip name array for CTIMER. */ -#define CTIMER_CLOCKS \ - { \ - kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ - } -/*! @brief Clock ip name array for COMP */ -#define COMP_CLOCKS \ - { \ - kCLOCK_Comp \ - } -/*! @brief Clock ip name array for SDIO. */ -#define SDIO_CLOCKS \ - { \ - kCLOCK_Sdio \ - } -/*! @brief Clock ip name array for USB1CLK. */ -#define USB1CLK_CLOCKS \ - { \ - kCLOCK_Usb1Clk \ - } -/*! @brief Clock ip name array for FREQME. */ -#define FREQME_CLOCKS \ - { \ - kCLOCK_Freqme \ - } -/*! @brief Clock ip name array for USBRAM. */ -#define USBRAM_CLOCKS \ - { \ - kCLOCK_UsbRam1 \ - } -/*! @brief Clock ip name array for RNG. */ -#define RNG_CLOCKS \ - { \ - kCLOCK_Rng \ - } -/*! @brief Clock ip name array for USBHMR0. */ -#define USBHMR0_CLOCKS \ - { \ - kCLOCK_Usbhmr0 \ - } -/*! @brief Clock ip name array for USBHSL0. */ -#define USBHSL0_CLOCKS \ - { \ - kCLOCK_Usbhsl0 \ - } -/*! @brief Clock ip name array for HashCrypt. */ -#define HASHCRYPT_CLOCKS \ - { \ - kCLOCK_HashCrypt \ - } -/*! @brief Clock ip name array for PowerQuad. */ -#define POWERQUAD_CLOCKS \ - { \ - kCLOCK_PowerQuad \ - } -/*! @brief Clock ip name array for PLULUT. */ -#define PLULUT_CLOCKS \ - { \ - kCLOCK_PluLut \ - } -/*! @brief Clock ip name array for PUF. */ -#define PUF_CLOCKS \ - { \ - kCLOCK_Puf \ - } -/*! @brief Clock ip name array for CASPER. */ -#define CASPER_CLOCKS \ - { \ - kCLOCK_Casper \ - } -/*! @brief Clock ip name array for ANALOGCTRL. */ -#define ANALOGCTRL_CLOCKS \ - { \ - kCLOCK_AnalogCtrl \ - } -/*! @brief Clock ip name array for HS_LSPI. */ -#define HS_LSPI_CLOCKS \ - { \ - kCLOCK_Hs_Lspi \ - } -/*! @brief Clock ip name array for GPIO_SEC. */ -#define GPIO_SEC_CLOCKS \ - { \ - kCLOCK_Gpio_Sec \ - } -/*! @brief Clock ip name array for GPIO_SEC_INT. */ -#define GPIO_SEC_INT_CLOCKS \ - { \ - kCLOCK_Gpio_Sec_Int \ - } -/*! @brief Clock ip name array for USBD. */ -#define USBD_CLOCKS \ - { \ - kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \ - } -/*! @brief Clock ip name array for USBH. */ -#define USBH_CLOCKS \ - { \ - kCLOCK_Usbh1 \ - } -#define PLU_CLOCKS \ - { \ - kCLOCK_PluLut \ - } -#define SYSCTL_CLOCKS \ - { \ - kCLOCK_Sysctl \ - } -/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ -/*------------------------------------------------------------------------------ - clock_ip_name_t definition: -------------------------------------------------------------------------------*/ - -#define CLK_GATE_REG_OFFSET_SHIFT 8U -#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U -#define CLK_GATE_BIT_SHIFT_SHIFT 0U -#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU - -#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ - ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ - (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) - -#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) -#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) - -#define AHB_CLK_CTRL0 0 -#define AHB_CLK_CTRL1 1 -#define AHB_CLK_CTRL2 2 - -/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ -typedef enum _clock_ip_name -{ - kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */ - kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /*!< Clock gate name: Rom. */ - - kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /*!< Clock gate name: Sram1. */ - - kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /*!< Clock gate name: Sram2. */ - - kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /*!< Clock gate name: Sram3. */ - - kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), /*!< Clock gate name: Sram4. */ - - kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /*!< Clock gate name: Flash. */ - - kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /*!< Clock gate name: Fmc. */ - - kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /*!< Clock gate name: InputMux. */ - - kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Iocon. */ - - kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Gpio0. */ - - kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Gpio1. */ - - kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), /*!< Clock gate name: Gpio2. */ - - kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), /*!< Clock gate name: Gpio3. */ - - kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), /*!< Clock gate name: Pint. */ - - kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gint. */ - - kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Dma0. */ - - kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Crc. */ - - kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Wwdt. */ - - kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Rtc. */ - - kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), /*!< Clock gate name: Mailbox. */ - - kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), /*!< Clock gate name: Adc0. */ - - kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), /*!< Clock gate name: Mrt. */ - - kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), /*!< Clock gate name: OsTimer0. */ - - kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), /*!< Clock gate name: Sct0. */ - - kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), /*!< Clock gate name: Utick0. */ - - kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexComm0. */ - - kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexComm1. */ - - kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexComm2. */ - - kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexComm3. */ - - kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexComm4. */ - - kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexComm5. */ - - kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexComm6. */ - - kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexComm7. */ - - kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: MinUart0. */ - - kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: MinUart1. */ - - kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: MinUart2. */ - - kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: MinUart3. */ - - kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: MinUart4. */ - - kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: MinUart5. */ - - kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: MinUart6. */ - - kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: MinUart7. */ - - kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LSpi0. */ - - kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LSpi1. */ - - kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LSpi2. */ - - kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LSpi3. */ - - kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LSpi4. */ - - kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LSpi5. */ - - kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LSpi6. */ - - kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LSpi7. */ - - kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: BI2c0. */ - - kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: BI2c1. */ - - kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: BI2c2. */ - - kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: BI2c3. */ - - kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: BI2c4. */ - - kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: BI2c5. */ - - kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: BI2c6. */ - - kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: BI2c7. */ - - kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexI2s0. */ - - kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexI2s1. */ - - kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexI2s2. */ - - kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexI2s3. */ - - kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexI2s4. */ - - kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexI2s5. */ - - kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexI2s6. */ - - kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexI2s7. */ - - kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), /*!< Clock gate name: Timer2. */ - - kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), /*!< Clock gate name: Usbd0. */ - - kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), /*!< Clock gate name: Timer0. */ - - kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), /*!< Clock gate name: Timer1. */ - - kCLOCK_Pvt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28), /*!< Clock gate name: Pvt. */ - - kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30), /*!< Clock gate name: Ezha. */ - - kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), /*!< Clock gate name: Ezhb. */ - - kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), /*!< Clock gate name: Dma1. */ - - kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), /*!< Clock gate name: Comp. */ - - kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3), /*!< Clock gate name: Sdio. */ - - kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), /*!< Clock gate name: Usbh1. */ - - kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), /*!< Clock gate name: Usbd1. */ - - kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), /*!< Clock gate name: UsbRam1. */ - - kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), /*!< Clock gate name: Usb1Clk. */ - - kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), /*!< Clock gate name: Freqme. */ - - kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), /*!< Clock gate name: Rng. */ - - kCLOCK_InputMux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: InputMux1. */ - - kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: Sysctl. */ - - kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), /*!< Clock gate name: Usbhmr0. */ - - kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), /*!< Clock gate name: Usbhsl0. */ - - kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), /*!< Clock gate name: HashCrypt. */ - - kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19), /*!< Clock gate name: PowerQuad. */ - - kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), /*!< Clock gate name: PluLut. */ - - kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), /*!< Clock gate name: Timer3. */ - - kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), /*!< Clock gate name: Timer4. */ - - kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), /*!< Clock gate name: Puf. */ - - kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), /*!< Clock gate name: Casper. */ - - kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27), /*!< Clock gate name: AnalogCtrl. */ - - kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28), /*!< Clock gate name: Lspi. */ - - kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), /*!< Clock gate name: GPIO Sec. */ - - kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30) /*!< Clock gate name: GPIO SEC Int. */ -} clock_ip_name_t; - -/*! @brief Peripherals clock source definition. */ -#define BUS_CLK kCLOCK_BusClk - -#define I2C0_CLK_SRC BUS_CLK - -/*! @brief Clock name used to get clock frequency. */ -typedef enum _clock_name -{ - kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ - kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ - kCLOCK_ClockOut, /*!< CLOCKOUT */ - kCLOCK_FroHf, /*!< FRO48/96 */ - kCLOCK_Pll1Out, /*!< PLL1 Output */ - kCLOCK_Mclk, /*!< MCLK */ - kCLOCK_Fro12M, /*!< FRO12M */ - kCLOCK_ExtClk, /*!< External Clock */ - kCLOCK_Pll0Out, /*!< PLL0 Output */ - kCLOCK_FlexI2S, /*!< FlexI2S clock */ - -} clock_name_t; - -/*! @brief Clock Mux Switches - * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable - * starting from LSB upwards - * - * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* - * - */ - -#define CLK_ATTACH_ID(mux, sel, pos) \ - ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((uint32_t)(pos)*12U)) -#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U) -#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U)) - -#define GET_ID_ITEM(connection) ((connection)&0xFFFU) -#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U) -#define GET_ID_ITEM_MUX(connection) (((uint8_t)connection) & 0xFFU) -#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF00U) >> 8U) - 1U)) -#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) - -#define CM_SYSTICKCLKSEL0 0U -#define CM_SYSTICKCLKSEL1 1U -#define CM_TRACECLKSEL 2U -#define CM_CTIMERCLKSEL0 3U -#define CM_CTIMERCLKSEL1 4U -#define CM_CTIMERCLKSEL2 5U -#define CM_CTIMERCLKSEL3 6U -#define CM_CTIMERCLKSEL4 7U -#define CM_MAINCLKSELA 8U -#define CM_MAINCLKSELB 9U -#define CM_CLKOUTCLKSEL 10U -#define CM_PLL0CLKSEL 12U -#define CM_PLL1CLKSEL 13U -#define CM_ADCASYNCCLKSEL 17U -#define CM_USB0CLKSEL 18U -#define CM_FXCOMCLKSEL0 20U -#define CM_FXCOMCLKSEL1 21U -#define CM_FXCOMCLKSEL2 22U -#define CM_FXCOMCLKSEL3 23U -#define CM_FXCOMCLKSEL4 24U -#define CM_FXCOMCLKSEL5 25U -#define CM_FXCOMCLKSEL6 26U -#define CM_FXCOMCLKSEL7 27U -#define CM_HSLSPICLKSEL 28U -#define CM_MCLKCLKSEL 32U -#define CM_SCTCLKSEL 36U -#define CM_SDIOCLKSEL 38U - -#define CM_RTCOSC32KCLKSEL 63U - -/*! - * @brief The enumerator of clock attach Id. - */ -typedef enum _clock_attach_id -{ - - kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO12M to MAIN_CLK. */ - - kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach EXT_CLK to MAIN_CLK. */ - - kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO1M to MAIN_CLK. */ - - kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO_HF to MAIN_CLK. */ - - kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0), /*!< Attach PLL0 to MAIN_CLK. */ - - kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), /*!< Attach PLL1 to MAIN_CLK. */ - - kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), /*!< Attach OSC32K to MAIN_CLK. */ - - kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Attach MAIN_CLK to CLKOUT. */ - - kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Attach PLL0 to CLKOUT. */ - - kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Attach EXT_CLK to CLKOUT. */ - - kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Attach FRO_HF to CLKOUT. */ - - kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Attach FRO1M to CLKOUT. */ - - kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Attach PLL1 to CLKOUT. */ - - kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Attach OSC32K to CLKOUT. */ - - kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< Attach NONE to SYS_CLKOUT. */ - - kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0), /*!< Attach FRO12M to PLL0. */ - - kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1), /*!< Attach EXT_CLK to PLL0. */ - - kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2), /*!< Attach FRO1M to PLL0. */ - - kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3), /*!< Attach OSC32K to PLL0. */ - - kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7), /*!< Attach NONE to PLL0. */ - - kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), /*!< Attach MAIN_CLK to ADC_CLK. */ - - kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), /*!< Attach PLL0 to ADC_CLK. */ - - kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), /*!< Attach FRO_HF to ADC_CLK. */ - - kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), /*!< Attach NONE to ADC_CLK. */ - - kMAIN_CLK_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0), /*!< Attach MAIN_CLK to USB0_CLK. */ - - kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1), /*!< Attach PLL0 to USB0_CLK. */ - - kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3), /*!< Attach FRO_HF to USB0_CLK. */ - - kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5), /*!< Attach PLL1 to USB0_CLK. */ - - kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7), /*!< Attach NONE to USB0_CLK. */ - - kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), /*!< Attach MAIN_CLK to FLEXCOMM0. */ - - kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), /*!< Attach PLL0_DIV to FLEXCOMM0. */ - - kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), /*!< Attach FRO12M to FLEXCOMM0. */ - - kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM0. */ - - kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), /*!< Attach FRO1M to FLEXCOMM0. */ - - kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5), /*!< Attach MCLK to FLEXCOMM0. */ - - kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6), /*!< Attach OSC32K to FLEXCOMM0. */ - - kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */ - - kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), /*!< Attach MAIN_CLK to FLEXCOMM1. */ - - kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), /*!< Attach PLL0_DIV to FLEXCOMM1. */ - - kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), /*!< Attach FRO12M to FLEXCOMM1. */ - - kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM1. */ - - kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), /*!< Attach FRO1M to FLEXCOMM1. */ - - kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5), /*!< Attach MCLK to FLEXCOMM1. */ - - kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6), /*!< Attach OSC32K to FLEXCOMM1. */ - - kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */ - - kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), /*!< Attach MAIN_CLK to FLEXCOMM2. */ - - kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), /*!< Attach PLL0_DIV to FLEXCOMM2. */ - - kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), /*!< Attach FRO12M to FLEXCOMM2. */ - - kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM2. */ - - kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), /*!< Attach FRO1M to FLEXCOMM2. */ - - kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5), /*!< Attach MCLK to FLEXCOMM2. */ - - kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6), /*!< Attach OSC32K to FLEXCOMM2. */ - - kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */ - - kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), /*!< Attach MAIN_CLK to FLEXCOMM3. */ - - kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), /*!< Attach PLL0_DIV to FLEXCOMM3. */ - - kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), /*!< Attach FRO12M to FLEXCOMM3. */ - - kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM3. */ - - kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), /*!< Attach FRO1M to FLEXCOMM3. */ - - kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5), /*!< Attach MCLK to FLEXCOMM3. */ - - kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6), /*!< Attach OSC32K to FLEXCOMM3. */ - - kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */ - - kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), /*!< Attach MAIN_CLK to FLEXCOMM4. */ - - kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), /*!< Attach PLL0_DIV to FLEXCOMM4. */ - - kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), /*!< Attach FRO12M to FLEXCOMM4. */ - - kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM4. */ - - kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), /*!< Attach FRO1M to FLEXCOMM4. */ - - kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5), /*!< Attach MCLK to FLEXCOMM4. */ - - kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6), /*!< Attach OSC32K to FLEXCOMM4. */ - - kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */ - - kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), /*!< Attach MAIN_CLK to FLEXCOMM5. */ - - kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), /*!< Attach PLL0_DIV to FLEXCOMM5. */ - - kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), /*!< Attach FRO12M to FLEXCOMM5. */ - - kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM5. */ - - kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), /*!< Attach FRO1M to FLEXCOMM5. */ - - kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5), /*!< Attach MCLK to FLEXCOMM5. */ - - kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6), /*!< Attach OSC32K to FLEXCOMM5. */ - - kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */ - - kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), /*!< Attach MAIN_CLK to FLEXCOMM6. */ - - kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), /*!< Attach PLL0_DIV to FLEXCOMM6. */ - - kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), /*!< Attach FRO12M to FLEXCOMM6. */ - - kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM6. */ - - kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), /*!< Attach FRO1M to FLEXCOMM6. */ - - kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5), /*!< Attach MCLK to FLEXCOMM6. */ - - kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6), /*!< Attach OSC32K to FLEXCOMM6. */ - - kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */ - - kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), /*!< Attach MAIN_CLK to FLEXCOMM7. */ - - kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), /*!< Attach PLL0_DIV to FLEXCOMM7. */ - - kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), /*!< Attach FRO12M to FLEXCOMM7. */ - - kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM7. */ - - kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), /*!< Attach FRO1M to FLEXCOMM7. */ - - kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5), /*!< Attach MCLK to FLEXCOMM7. */ - - kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6), /*!< Attach OSC32K to FLEXCOMM7. */ - - kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */ - - kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0), /*!< Attach MAIN_CLK to HSLSPI. */ - - kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1), /*!< Attach PLL0_DIV to HSLSPI. */ - - kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2), /*!< Attach FRO12M to HSLSPI. */ - - kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3), /*!< Attach FRO_HF_DIV to HSLSPI. */ - - kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4), /*!< Attach FRO1M to HSLSPI. */ - - kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6), /*!< Attach OSC32K to HSLSPI. */ - - kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7), /*!< Attach NONE to HSLSPI. */ - - kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), /*!< Attach FRO_HF to MCLK. */ - - kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), /*!< Attach PLL0 to MCLK. */ - - kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), /*!< Attach NONE to MCLK. */ - - kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), /*!< Attach MAIN_CLK to SCT_CLK. */ - - kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), /*!< Attach PLL0 to SCT_CLK. */ - - kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), /*!< Attach EXT_CLK to SCT_CLK. */ - - kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), /*!< Attach FRO_HF to SCT_CLK. */ - - kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5), /*!< Attach MCLK to SCT_CLK. */ - - kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), /*!< Attach NONE to SCT_CLK. */ - - kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0), /*!< Attach MAIN_CLK to SDIO_CLK. */ - - kPLL0_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1), /*!< Attach PLL0 to SDIO_CLK. */ - - kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3), /*!< Attach FRO_HF to SDIO_CLK. */ - - kPLL1_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 5), /*!< Attach PLL1 to SDIO_CLK. */ - - kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7), /*!< Attach NONE to SDIO_CLK. */ - - kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0), /*!< Attach FRO32K to OSC32K. */ - - kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1), /*!< Attach XTAL32K to OSC32K. */ - - kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), /*!< Attach TRACE_DIV to TRACE. */ - - kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), /*!< Attach FRO1M to TRACE. */ - - kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), /*!< Attach OSC32K to TRACE. */ - - kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), /*!< Attach NONE to TRACE. */ - - kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), /*!< Attach SYSTICK_DIV0 to SYSTICK0. */ - - kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), /*!< Attach FRO1M to SYSTICK0. */ - - kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), /*!< Attach OSC32K to SYSTICK0. */ - - kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), /*!< Attach NONE to SYSTICK0. */ - - kSYSTICK_DIV1_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 0), /*!< Attach SYSTICK_DIV1 to SYSTICK1. */ - - kFRO1M_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 1), /*!< Attach FRO1M to SYSTICK1. */ - - kOSC32K_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 2), /*!< Attach OSC32K to SYSTICK1. */ - - kNONE_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 7), /*!< Attach NONE to SYSTICK1. */ - - kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0), /*!< Attach FRO12M to PLL1. */ - - kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1), /*!< Attach EXT_CLK to PLL1. */ - - kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2), /*!< Attach FRO1M to PLL1. */ - - kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3), /*!< Attach OSC32K to PLL1. */ - - kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7), /*!< Attach NONE to PLL1. */ - - kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), /*!< Attach MAIN_CLK to CTIMER0. */ - - kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), /*!< Attach PLL0 to CTIMER0. */ - - kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), /*!< Attach FRO_HF to CTIMER0. */ - - kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), /*!< Attach FRO1M to CTIMER0. */ - - kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), /*!< Attach MCLK to CTIMER0. */ - - kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), /*!< Attach OSC32K to CTIMER0. */ - - kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7), /*!< Attach NONE to CTIMER0. */ - - kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), /*!< Attach MAIN_CLK to CTIMER1. */ - - kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), /*!< Attach PLL0 to CTIMER1. */ - - kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), /*!< Attach FRO_HF to CTIMER1. */ - - kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), /*!< Attach FRO1M to CTIMER1. */ - - kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), /*!< Attach MCLK to CTIMER1. */ - - kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), /*!< Attach OSC32K to CTIMER1. */ - - kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7), /*!< Attach NONE to CTIMER1. */ - - kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), /*!< Attach MAIN_CLK to CTIMER2. */ - - kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), /*!< Attach PLL0 to CTIMER2. */ - - kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), /*!< Attach FRO_HF to CTIMER2. */ - - kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), /*!< Attach FRO1M to CTIMER2. */ - - kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), /*!< Attach MCLK to CTIMER2. */ - - kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), /*!< Attach OSC32K to CTIMER2. */ - - kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7), /*!< Attach NONE to CTIMER2. */ - - kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), /*!< Attach MAIN_CLK to CTIMER3. */ - - kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), /*!< Attach PLL0 to CTIMER3. */ - - kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), /*!< Attach FRO_HF to CTIMER3. */ - - kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), /*!< Attach FRO1M to CTIMER3. */ - - kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), /*!< Attach MCLK to CTIMER3. */ - - kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), /*!< Attach OSC32K to CTIMER3. */ - - kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7), /*!< Attach NONE to CTIMER3. */ - - kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), /*!< Attach MAIN_CLK to CTIMER4. */ - - kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), /*!< Attach PLL0 to CTIMER4. */ - - kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), /*!< Attach FRO_HF to CTIMER4. */ - - kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), /*!< Attach FRO1M to CTIMER4. */ - - kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), /*!< Attach MCLK to CTIMER4. */ - - kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), /*!< Attach OSC32K to CTIMER4. */ - - kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7), /*!< Attach NONE to CTIMER4. */ - - kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */ - -} clock_attach_id_t; - -/*! @brief Clock dividers */ -typedef enum _clock_div_name -{ - kCLOCK_DivSystickClk0 = 0, /*!< Systick Clk0 Divider. */ - - kCLOCK_DivSystickClk1 = 1, /*!< Systick Clk1 Divider. */ - - kCLOCK_DivArmTrClkDiv = 2, /*!< Arm Tr Clk Div Divider. */ - - kCLOCK_DivFlexFrg0 = 8, /*!< Flex Frg0 Divider. */ - - kCLOCK_DivFlexFrg1 = 9, /*!< Flex Frg1 Divider. */ - - kCLOCK_DivFlexFrg2 = 10, /*!< Flex Frg2 Divider. */ - - kCLOCK_DivFlexFrg3 = 11, /*!< Flex Frg3 Divider. */ - - kCLOCK_DivFlexFrg4 = 12, /*!< Flex Frg4 Divider. */ - - kCLOCK_DivFlexFrg5 = 13, /*!< Flex Frg5 Divider. */ - - kCLOCK_DivFlexFrg6 = 14, /*!< Flex Frg6 Divider. */ - - kCLOCK_DivFlexFrg7 = 15, /*!< Flex Frg7 Divider. */ - - kCLOCK_DivAhbClk = 32, /*!< Ahb Clock Divider. */ - - kCLOCK_DivClkOut = 33, /*!< Clk Out Divider. */ - - kCLOCK_DivFrohfClk = 34, /*!< Frohf Clock Divider. */ - - kCLOCK_DivWdtClk = 35, /*!< Wdt Clock Divider. */ - - kCLOCK_DivAdcAsyncClk = 37, /*!< Adc Async Clock Divider. */ - - kCLOCK_DivUsb0Clk = 38, /*!< Usb0 Clock Divider. */ - - kCLOCK_DivMClk = 43, /*!< I2S MCLK Clock Divider. */ - - kCLOCK_DivSctClk = 45, /*!< Sct Clock Divider. */ - - kCLOCK_DivSdioClk = 47, /*!< Sdio Clock Divider. */ - - kCLOCK_DivPll0Clk = 49 /*!< PLL clock divider. */ -} clock_div_name_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief Enable the clock for specific IP. - * @param clk : Clock to be enabled. - * @return Nothing - */ -static inline void CLOCK_EnableClock(clock_ip_name_t clk) -{ - uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); -} -/** - * @brief Disable the clock for specific IP. - * @param clk : Clock to be Disabled. - * @return Nothing - */ -static inline void CLOCK_DisableClock(clock_ip_name_t clk) -{ - uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); -} -/** - * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). - * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is - * enabled. - * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ) - * @return returns success or fail status. - */ -status_t CLOCK_SetupFROClocking(uint32_t iFreq); -/** - * @brief Set the flash wait states for the input freuqency. - * @param iFreq : Input frequency - * @return Nothing - */ -void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq); -/** - * @brief Initialize the external osc clock to given frequency. - * @param iFreq : Desired frequency (must be equal to exact rate in Hz) - * @return returns success or fail status. - */ -status_t CLOCK_SetupExtClocking(uint32_t iFreq); -/** - * @brief Initialize the I2S MCLK clock to given frequency. - * @param iFreq : Desired frequency (must be equal to exact rate in Hz) - * @return returns success or fail status. - */ -status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq); -/** - * @brief Initialize the PLU CLKIN clock to given frequency. - * @param iFreq : Desired frequency (must be equal to exact rate in Hz) - * @return returns success or fail status. - */ -status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq); -/** - * @brief Configure the clock selection muxes. - * @param connection : Clock to be configured. - * @return Nothing - */ -void CLOCK_AttachClk(clock_attach_id_t connection); -/** - * @brief Get the actual clock attach id. - * This fuction uses the offset in input attach id, then it reads the actual source value in - * the register and combine the offset to obtain an actual attach id. - * @param attachId : Clock attach id to get. - * @return Clock source value. - */ -clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId); -/** - * @brief Setup peripheral clock dividers. - * @param div_name : Clock divider name - * @param divided_by_value: Value to be divided - * @param reset : Whether to reset the divider counter. - * @return Nothing - */ -void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset); -/** - * @brief Setup rtc 1khz clock divider. - * @param divided_by_value: Value to be divided - * @return Nothing - */ -void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value); -/** - * @brief Setup rtc 1hz clock divider. - * @param divided_by_value: Value to be divided - * @return Nothing - */ -void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value); - -/** - * @brief Set the flexcomm output frequency. - * @param id : flexcomm instance id - * @param freq : output frequency - * @return 0 : the frequency range is out of range. - * 1 : switch successfully. - */ -uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq); - -/*! @brief Return Frequency of flexcomm input clock - * @param id : flexcomm instance id - * @return Frequency value - */ -uint32_t CLOCK_GetFlexCommInputClock(uint32_t id); - -/*! @brief Return Frequency of selected clock - * @return Frequency of selected clock - */ -uint32_t CLOCK_GetFreq(clock_name_t clockName); -/*! @brief Return Frequency of FRO 12MHz - * @return Frequency of FRO 12MHz - */ -uint32_t CLOCK_GetFro12MFreq(void); -/*! @brief Return Frequency of FRO 1MHz - * @return Frequency of FRO 1MHz - */ -uint32_t CLOCK_GetFro1MFreq(void); -/*! @brief Return Frequency of ClockOut - * @return Frequency of ClockOut - */ -uint32_t CLOCK_GetClockOutClkFreq(void); -/*! @brief Return Frequency of Adc Clock - * @return Frequency of Adc. - */ -uint32_t CLOCK_GetAdcClkFreq(void); -/*! @brief Return Frequency of Usb0 Clock - * @return Frequency of Usb0 Clock. - */ -uint32_t CLOCK_GetUsb0ClkFreq(void); -/*! @brief Return Frequency of Usb1 Clock - * @return Frequency of Usb1 Clock. - */ -uint32_t CLOCK_GetUsb1ClkFreq(void); -/*! @brief Return Frequency of MClk Clock - * @return Frequency of MClk Clock. - */ -uint32_t CLOCK_GetMclkClkFreq(void); -/*! @brief Return Frequency of SCTimer Clock - * @return Frequency of SCTimer Clock. - */ -uint32_t CLOCK_GetSctClkFreq(void); -/*! @brief Return Frequency of SDIO Clock - * @return Frequency of SDIO Clock. - */ -uint32_t CLOCK_GetSdioClkFreq(void); -/*! @brief Return Frequency of External Clock - * @return Frequency of External Clock. If no external clock is used returns 0. - */ -uint32_t CLOCK_GetExtClkFreq(void); -/*! @brief Return Frequency of Watchdog - * @return Frequency of Watchdog - */ -uint32_t CLOCK_GetWdtClkFreq(void); -/*! @brief Return Frequency of High-Freq output of FRO - * @return Frequency of High-Freq output of FRO - */ -uint32_t CLOCK_GetFroHfFreq(void); -/*! @brief Return Frequency of PLL - * @return Frequency of PLL - */ -uint32_t CLOCK_GetPll0OutFreq(void); -/*! @brief Return Frequency of USB PLL - * @return Frequency of PLL - */ -uint32_t CLOCK_GetPll1OutFreq(void); -/*! @brief Return Frequency of 32kHz osc - * @return Frequency of 32kHz osc - */ -uint32_t CLOCK_GetOsc32KFreq(void); -/*! @brief Return Frequency of Core System - * @return Frequency of Core System - */ -uint32_t CLOCK_GetCoreSysClkFreq(void); -/*! @brief Return Frequency of I2S MCLK Clock - * @return Frequency of I2S MCLK Clock - */ -uint32_t CLOCK_GetI2SMClkFreq(void); -/*! @brief Return Frequency of PLU CLKIN Clock - * @return Frequency of PLU CLKIN Clock - */ -uint32_t CLOCK_GetPLUClkInFreq(void); -/*! @brief Return Frequency of FlexComm Clock - * @return Frequency of FlexComm Clock - */ -uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id); -/*! @brief Return Frequency of High speed SPI Clock - * @return Frequency of High speed SPI Clock - */ -uint32_t CLOCK_GetHsLspiClkFreq(void); -/*! @brief Return Frequency of CTimer functional Clock - * @return Frequency of CTimer functional Clock - */ -uint32_t CLOCK_GetCTimerClkFreq(uint32_t id); -/*! @brief Return Frequency of SystickClock - * @return Frequency of Systick Clock - */ -uint32_t CLOCK_GetSystickClkFreq(uint32_t id); - -/*! @brief Return PLL0 input clock rate - * @return PLL0 input clock rate - */ -uint32_t CLOCK_GetPLL0InClockRate(void); - -/*! @brief Return PLL1 input clock rate - * @return PLL1 input clock rate - */ -uint32_t CLOCK_GetPLL1InClockRate(void); - -/*! @brief Return PLL0 output clock rate - * @param recompute : Forces a PLL rate recomputation if true - * @return PLL0 output clock rate - * @note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetPLL0OutClockRate(bool recompute); - -/*! @brief Enables and disables PLL0 bypass mode - * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass - * @return PLL0 output clock rate - */ -__STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass) -{ - if (bypass) - { - SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); - } - else - { - SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); - } -} - -/*! @brief Enables and disables PLL1 bypass mode - * @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass - * @return PLL1 output clock rate - */ -__STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass) -{ - if (bypass) - { - SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); - } - else - { - SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); - } -} - -/*! @brief Check if PLL is locked or not - * @return true if the PLL is locked, false if not locked - */ -__STATIC_INLINE bool CLOCK_IsPLL0Locked(void) -{ - return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0UL); -} - -/*! @brief Check if PLL1 is locked or not - * @return true if the PLL1 is locked, false if not locked - */ -__STATIC_INLINE bool CLOCK_IsPLL1Locked(void) -{ - return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0UL); -} - -/*! @brief Store the current PLL0 rate - * @param rate: Current rate of the PLL0 - * @return Nothing - **/ -void CLOCK_SetStoredPLL0ClockRate(uint32_t rate); - -/*! @brief PLL configuration structure flags for 'flags' field - * These flags control how the PLL configuration function sets up the PLL setup structure.
- * - * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the - * configuration structure must be assigned with the expected PLL frequency. If the - * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration - * function and the driver will determine the PLL rate from the currently selected - * PLL source. This flag might be used to configure the PLL input clock more accurately - * when using the WDT oscillator or a more dyanmic CLKIN source.
- * - * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the - * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider - * are not used.
- */ -#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */ -#define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U) -/*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */ - -/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency - * See (MF) field in the PLL0SSCG1 register in the UM. - */ -typedef enum _ss_progmodfm -{ - kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */ - kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */ - kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */ - kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */ - kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */ - kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */ - kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */ - kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */ -} ss_progmodfm_t; - -/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth - * See (MR) field in the PLL0SSCG1 register in the UM. - */ -typedef enum _ss_progmoddp -{ - kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */ - kSS_MR_K1 = (1 << 23), /*!< k = 1 */ - kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */ - kSS_MR_K2 = (3 << 23), /*!< k = 2 */ - kSS_MR_K3 = (4 << 23), /*!< k = 3 */ - kSS_MR_K4 = (5 << 23), /*!< k = 4 */ - kSS_MR_K6 = (6 << 23), /*!< k = 6 */ - kSS_MR_K8 = (7 << 23) /*!< k = 8 */ -} ss_progmoddp_t; - -/*! @brief PLL Spread Spectrum (SS) Modulation waveform control - * See (MC) field in the PLL0SSCG1 register in the UM.
- * Compensation for low pass filtering of the PLL to get a triangular - * modulation at the output of the PLL, giving a flat frequency spectrum. - */ -typedef enum _ss_modwvctrl -{ - kSS_MC_NOC = (0 << 26), /*!< no compensation */ - kSS_MC_RECC = (2 << 26), /*!< recommended setting */ - kSS_MC_MAXC = (3 << 26), /*!< max. compensation */ -} ss_modwvctrl_t; - -/*! @brief PLL configuration structure - * - * This structure can be used to configure the settings for a PLL - * setup structure. Fill in the desired configuration for the PLL - * and call the PLL setup function to fill in a PLL setup structure. - */ -typedef struct _pll_config -{ - uint32_t desiredRate; /*!< Desired PLL rate in Hz */ - uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */ - uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ - ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - ss_modwvctrl_t - ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ - bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - -} pll_config_t; - -/*! @brief PLL setup structure flags for 'flags' field - * These flags control how the PLL setup function sets up the PLL - */ -#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */ -#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ -#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */ -#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */ - -/*! @brief PLL0 setup structure - * This structure can be used to pre-build a PLL setup configuration - * at run-time and quickly set the PLL to the configuration. It can be - * populated with the PLL setup function. If powering up or waiting - * for PLL lock, the PLL input clock source should be configured prior - * to PLL setup. - */ -typedef struct _pll_setup -{ - uint32_t pllctrl; /*!< PLL control register PLL0CTRL */ - uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */ - uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */ - uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */ - uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/ - uint32_t pllRate; /*!< Acutal PLL rate */ - uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ -} pll_setup_t; - -/*! @brief PLL status definitions - */ -typedef enum _pll_error -{ - kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ - kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ - kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ - kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ - kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ - kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */ - kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */ - kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */ -} pll_error_t; - -/*! @brief USB FS clock source definition. */ -typedef enum _clock_usbfs_src -{ - kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 MHz. */ - kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, /*!< Use PLL0 output. */ - kCLOCK_UsbfsSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */ - kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, /*!< Use PLL1 clock. */ - - kCLOCK_UsbfsSrcNone = - SYSCON_USB0CLKSEL_SEL(7) /*!COMP & ~(PMC_COMP_LOWPOWER_MASK | PMC_COMP_HYST_MASK | PMC_COMP_FILTERCGF_CLKDIV_MASK | - PMC_COMP_FILTERCGF_SAMPLEMODE_MASK)); - - if (true == config->enableLowPower) - { - tmpReg |= PMC_COMP_LOWPOWER_MASK; - } - else - { - tmpReg &= ~PMC_COMP_LOWPOWER_MASK; - } - - if (true == config->enableHysteresis) - { - tmpReg |= PMC_COMP_HYST_MASK; - } - else - { - tmpReg &= ~PMC_COMP_HYST_MASK; - } - - tmpReg |= (PMC_COMP_FILTERCGF_CLKDIV(config->filterClockDivider) | - PMC_COMP_FILTERCGF_SAMPLEMODE(config->filterSampleMode)); - - PMC->COMP = tmpReg; -} - -/*! - * @brief CMP deinitialization. - * - * This function gates the clock for CMP module. - */ -void CMP_Deinit(void) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(kCLOCK_Comp); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Initializes the CMP user configuration structure. - * - * This function initializes the user configuration structure to these default values. - * @code - * config->enableHysteresis = true; - * config->enableLowPower = true; - * config->filterClockDivider = kCMP_FilterClockDivide1; - * config->filterSampleMode = kCMP_FilterSampleMode0; - * @endcode - * @param config Pointer to the configuration structure. - */ -void CMP_GetDefaultConfig(cmp_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enableHysteresis = true; - config->enableLowPower = true; - config->filterClockDivider = kCMP_FilterClockDivide1; - config->filterSampleMode = kCMP_FilterSampleMode0; -} - -/*! - * @brief Configures the VREFINPUT. - * - * @param config Pointer to the configuration structure. - */ -void CMP_SetVREF(const cmp_vref_config_t *config) -{ - assert(NULL != config); - assert(config->vrefValue < 32U); - - uint32_t tmpReg = PMC->COMP & ~(PMC_COMP_VREF_MASK | PMC_COMP_VREFINPUT_MASK); - - tmpReg |= PMC_COMP_VREFINPUT(config->vrefSource) | PMC_COMP_VREF(config->vrefValue); - - PMC->COMP = tmpReg; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_cmp.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_cmp.h deleted file mode 100644 index 1afdc972808..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_cmp.h +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Copyright 2018-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __FSL_CMP_H_ -#define __FSL_CMP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup cmp_1 - * @{ - */ - -/****************************************************************************** - * Definitions. - *****************************************************************************/ -/*! @name Driver version */ -/*@{*/ -/*! @brief Driver version 2.2.1. */ -#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 1U)) -/*@}*/ - -/*! @brief CMP input mux for positive and negative sides. */ -enum _cmp_input_mux -{ - kCMP_InputVREF = 0U, /*!< Cmp input from VREF. */ - kCMP_Input1 = 1U, /*!< Cmp input source 1. */ - kCMP_Input2 = 2U, /*!< Cmp input source 2. */ - kCMP_Input3 = 3U, /*!< Cmp input source 3. */ - kCMP_Input4 = 4U, /*!< Cmp input source 4. */ - kCMP_Input5 = 5U, /*!< Cmp input source 5. */ -}; - -/*! @brief CMP interrupt type. */ -enum _cmp_interrupt_type -{ - kCMP_EdgeDisable = 0U, /*!< Disable edge interupt. */ - kCMP_EdgeRising = 2U, /*!< Interrupt on falling edge. */ - kCMP_EdgeFalling = 4U, /*!< Interrupt on rising edge. */ - kCMP_EdgeRisingFalling = 6U, /*!< Interrupt on both rising and falling edges. */ - - kCMP_LevelDisable = 1U, /*!< Disable level interupt. */ - kCMP_LevelHigh = 3U, /*!< Interrupt on high level. */ - kCMP_LevelLow = 5U, /*!< Interrupt on low level. */ -}; - -/*! @brief CMP Voltage Reference source. */ -typedef enum _cmp_vref_source -{ - KCMP_VREFSourceVDDA = 1U, /*!< Select VDDA as VREF. */ - KCMP_VREFSourceInternalVREF = 0U, /*!< Select internal VREF as VREF. */ -} cmp_vref_source_t; - -typedef struct _cmp_vref_config -{ - cmp_vref_source_t vrefSource; /*!< Reference voltage source. */ - uint8_t vrefValue; /*!< Reference voltage step. Available range is 0-31. Per step equals to VREFINPUT/31. */ -} cmp_vref_config_t; - -/*! @brief CMP Filter sample mode. */ -typedef enum _cmp_filtercgf_samplemode -{ - kCMP_FilterSampleMode0 = 0U, /*!< Bypass mode. Filtering is disabled. */ - kCMP_FilterSampleMode1 = 1U, /*!< Filter 1 clock period. */ - kCMP_FilterSampleMode2 = 2U, /*!< Filter 2 clock period. */ - kCMP_FilterSampleMode3 = 3U /*!< Filter 3 clock period. */ -} cmp_filtercgf_samplemode_t; - -/*! @brief CMP Filter clock divider. */ -typedef enum _cmp_filtercgf_clkdiv -{ - kCMP_FilterClockDivide1 = 0U, /*!< Filter clock period duration equals 1 analog comparator clock period. */ - kCMP_FilterClockDivide2 = 1U, /*!< Filter clock period duration equals 2 analog comparator clock period. */ - kCMP_FilterClockDivide4 = 2U, /*!< Filter clock period duration equals 4 analog comparator clock period. */ - kCMP_FilterClockDivide8 = 3U, /*!< Filter clock period duration equals 8 analog comparator clock period. */ - kCMP_FilterClockDivide16 = 4U, /*!< Filter clock period duration equals 16 analog comparator clock period. */ - kCMP_FilterClockDivide32 = 5U, /*!< Filter clock period duration equals 32 analog comparator clock period. */ - kCMP_FilterClockDivide64 = 6U /*!< Filter clock period duration equals 64 analog comparator clock period. */ -} cmp_filtercgf_clkdiv_t; - -/*! @brief CMP configuration structure. */ -typedef struct _cmp_config -{ - bool enableHysteresis; /*!< Enable hysteresis. */ - bool enableLowPower; /*!< Enable low power mode. */ - cmp_filtercgf_clkdiv_t filterClockDivider; /* Filter clock divider. Filter clock equals the Analog Comparator clock - divided by 2^FILTERCGF_CLKDIV. */ - cmp_filtercgf_samplemode_t - filterSampleMode; /* Filter sample mode. Control the filtering of the Analog Comparator output. */ -} cmp_config_t; - -/************************************************************************************************* - * API - ************************************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief CMP initialization. - * - * This function enables the CMP module and do necessary settings. - * - * @param config Pointer to the configuration structure. - */ -void CMP_Init(const cmp_config_t *config); - -/*! - * @brief CMP deinitialization. - * - * This function gates the clock for CMP module. - */ -void CMP_Deinit(void); - -/*! - * @brief Initializes the CMP user configuration structure. - * - * This function initializes the user configuration structure to these default values. - * @code - * config->enableHysteresis = true; - * config->enableLowPower = true; - * config->filterClockDivider = kCMP_FilterClockDivide1; - * config->filterSampleMode = kCMP_FilterSampleMode0; - * @endcode - * @param config Pointer to the configuration structure. - */ -void CMP_GetDefaultConfig(cmp_config_t *config); - -/* @} */ - -/*! - * @name Compare Interface - * @{ - */ - -/* - * @brief Set the input channels for the comparator. - * - * @param positiveChannel Positive side input channel number. See "_cmp_input_mux". - * @param negativeChannel Negative side input channel number. See "_cmp_input_mux". - */ -static inline void CMP_SetInputChannels(uint8_t positiveChannel, uint8_t negativeChannel) -{ - PMC->COMP &= ~(PMC_COMP_PMUX_MASK | PMC_COMP_NMUX_MASK); - PMC->COMP |= (PMC_COMP_PMUX(positiveChannel) | PMC_COMP_NMUX(negativeChannel)); -} - -/*! - * @brief Configures the VREFINPUT. - * - * @param config Pointer to the configuration structure. - */ -void CMP_SetVREF(const cmp_vref_config_t *config); - -/*! - * @brief Get CMP compare output. - * - * @return The output result. true: voltage on positive side is greater than negative side. - * false: voltage on positive side is lower than negative side. - */ -static inline bool CMP_GetOutput(void) -{ - return SYSCON_COMP_INT_STATUS_VAL_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_VAL_MASK); -} - -/* @} */ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief CMP enable interrupt. - * - * @param type CMP interrupt type. See "_cmp_interrupt_type". - */ -static inline void CMP_EnableInterrupt(uint32_t type) -{ - SYSCON->COMP_INT_CTRL |= (SYSCON_COMP_INT_CTRL_INT_CTRL(type) | SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK); -} - -/*! - * @brief CMP disable interrupt. - * - */ -static inline void CMP_DisableInterrupt(void) -{ - SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK; -} - -/*! - * @brief CMP clear interrupt. - * - */ -static inline void CMP_ClearInterrupt(void) -{ - SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK; -} - -/*! - * @brief Select which Analog comparator output (filtered or un-filtered) is used for interrupt detection. - * - * @param enable false: Select Analog Comparator raw output (unfiltered) as input for interrupt detection. - * true: Select Analog Comparator filtered output as input for interrupt detection. - * - * @note: When CMP is configured as the wakeup source in power down mode, this function must use the raw output as the - * interupt source, that is, call this function and set parameter enable to false. - */ -static inline void CMP_EnableFilteredInterruptSource(bool enable) -{ - if (enable) - { - SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; - } - else - { - SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; - } -} -/* @} */ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Get CMP interrupt status before interupt enable. - * - * @return Interrupt status. true: interrupt pending, - * false: no interrupt pending. - */ -static inline bool CMP_GetPreviousInterruptStatus(void) -{ - return SYSCON_COMP_INT_STATUS_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_STATUS_MASK); -} - -/*! - * @brief Get CMP interrupt status after interupt enable. - * - * @return Interrupt status. true: interrupt pending, - * false: no interrupt pending. - */ -static inline bool CMP_GetInterruptStatus(void) -{ - return SYSCON_COMP_INT_STATUS_INT_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK); -} -/* @} */ - -/*! - * @name Filter Interface - * @{ - */ - -/*! - * @brief CMP Filter Sample Config. - * - * This function allows the users to configure the sampling mode and clock divider of the CMP Filter. - * - * @param filterSampleMode CMP Select filter sample mode - * @param filterClockDivider CMP Set fileter clock divider - */ -static inline void CMP_FilterSampleConfig(cmp_filtercgf_samplemode_t filterSampleMode, - cmp_filtercgf_clkdiv_t filterClockDivider) -{ - uint32_t comp = PMC->COMP; - - comp &= ~(PMC_COMP_FILTERCGF_CLKDIV_MASK | PMC_COMP_FILTERCGF_SAMPLEMODE_MASK); - comp |= (((uint32_t)filterClockDivider << PMC_COMP_FILTERCGF_CLKDIV_SHIFT) | - ((uint32_t)filterSampleMode << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)); - - PMC->COMP = comp; -} -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ -#endif /* __FSL_CMP_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.c deleted file mode 100644 index d3af9fdfc67..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" - -#define SDK_MEM_MAGIC_NUMBER 12345U - -typedef struct _mem_align_control_block -{ - uint16_t identifier; /*!< Identifier for the memory control block. */ - uint16_t offset; /*!< offset from aligned address to real address */ -} mem_align_cb_t; - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.common" -#endif - -#if !((defined(__DSC__) && defined(__CW__))) -void *SDK_Malloc(size_t size, size_t alignbytes) -{ - mem_align_cb_t *p_cb = NULL; - uint32_t alignedsize; - - /* Check overflow. */ - alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes); - if (alignedsize < size) - { - return NULL; - } - - if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t)) - { - return NULL; - } - - alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t); - - union - { - void *pointer_value; - uintptr_t unsigned_value; - } p_align_addr, p_addr; - - p_addr.pointer_value = malloc((size_t)alignedsize); - - if (p_addr.pointer_value == NULL) - { - return NULL; - } - - p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes); - - p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U); - p_cb->identifier = SDK_MEM_MAGIC_NUMBER; - p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value); - - return p_align_addr.pointer_value; -} - -void SDK_Free(void *ptr) -{ - union - { - void *pointer_value; - uintptr_t unsigned_value; - } p_free; - p_free.pointer_value = ptr; - mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U); - - if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) - { - return; - } - - p_free.unsigned_value = p_free.unsigned_value - p_cb->offset; - - free(p_free.pointer_value); -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.h deleted file mode 100644 index d9cb304f2f8..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.h +++ /dev/null @@ -1,316 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_COMMON_H_ -#define _FSL_COMMON_H_ - -#include -#include -#include -#include -#include - -#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__) -#include -#endif - -#include "fsl_device_registers.h" - -/*! - * @addtogroup ksdk_common - * @{ - */ - -/******************************************************************************* - * Configurations - ******************************************************************************/ - -/*! @brief Macro to use the default weak IRQ handler in drivers. */ -#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ -#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Construct a status code value from a group and code number. */ -#define MAKE_STATUS(group, code) ((((group)*100L) + (code))) - -/*! @brief Construct the version number for drivers. - * - * The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M) - * and 16-bit platforms(such as DSC). - * - * @verbatim - - | Unused || Major Version || Minor Version || Bug Fix | - 31 25 24 17 16 9 8 0 - - @endverbatim - */ -#define MAKE_VERSION(major, minor, bugfix) (((major) * 65536L) + ((minor) * 256L) + (bugfix)) - -/*! @name Driver version */ -/*@{*/ -/*! @brief common driver version. */ -#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 2)) -/*@}*/ - -/* Debug console type definition. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */ - -/*! @brief Status group numbers. */ -enum _status_groups -{ - kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ - kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ - kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ - kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ - kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ - kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ - kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ - kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ - kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ - kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ - kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ - kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ - kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ - kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ - kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ - kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ - kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ - kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ - kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ - kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ - kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ - kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ - kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ - kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ - kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ - kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ - kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ - kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ - kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ - kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ - kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ - kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ - kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ - kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ - kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ - kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ - kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ - kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ - kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ - kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ - kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ - kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ - kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ - kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ - kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ - kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ - kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ - kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ - kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ - kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ - kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ - kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ - kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ - kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ - kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ - kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ - kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ - kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ - kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ - kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ - kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ - kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ - kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ - kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ - kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ - kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ - kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ - kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ - kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ - kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ - kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ - kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ - kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ - kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/ - kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */ - kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */ - kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */ - - kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ - kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ - kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ - kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ - kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ - kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ - kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ - kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ - kStatusGroup_HAL_I2S = 129, /*!< Group number for HAL I2S status codes. */ - kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ - kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ - kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ - kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ - kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ - kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ - kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ - kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ - kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ - kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ - kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ - kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ - kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ - kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ - kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */ - kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */ - kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */ - kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */ - kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */ - kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */ - kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */ - kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */ - kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */ - kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */ - kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */ - kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */ - kStatusGroup_CSS_PKC = 161, /*!< Group number for CSS PKC status codes. */ - kStatusGroup_HOSTIF = 162, /*!< Group number for HOSTIF status codes. */ - kStatusGroup_CLIF = 163, /*!< Group number for CLIF status codes. */ - kStatusGroup_BMA = 164, /*!< Group number for BMA status codes. */ -}; - -/*! \public - * @brief Generic status return codes. - */ -enum -{ - kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */ - kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */ - kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */ - kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */ - kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */ - kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */ - kStatus_NoTransferInProgress = - MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */ - kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */ - kStatus_NoData = - MAKE_STATUS(kStatusGroup_Generic, 8), /*!< Generic status for no data is found for the operation. */ -}; - -/*! @brief Type used for all status and error return values. */ -typedef int32_t status_t; - -/*! - * @name Min/max macros - * @{ - */ -#if !defined(MIN) -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) -#endif - -#if !defined(MAX) -#define MAX(a, b) (((a) > (b)) ? (a) : (b)) -#endif -/* @} */ - -/*! @brief Computes the number of elements in an array. */ -#if !defined(ARRAY_SIZE) -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) -#endif - -/*! @name UINT16_MAX/UINT32_MAX value */ -/* @{ */ -#if !defined(UINT16_MAX) -#define UINT16_MAX ((uint16_t)-1) -#endif - -#if !defined(UINT32_MAX) -#define UINT32_MAX ((uint32_t)-1) -#endif -/* @} */ - -/*! @name Suppress fallthrough warning macro */ -/* For switch case code block, if case section ends without "break;" statement, there wil be - fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. - To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each - case section which misses "break;"statement. - */ -/* @{ */ -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) -#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough)) -#else -#define SUPPRESS_FALL_THROUGH_WARNING() -#endif -/* @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -#if !((defined(__DSC__) && defined(__CW__))) -/*! - * @brief Allocate memory with given alignment and aligned size. - * - * This is provided to support the dynamically allocated memory - * used in cache-able region. - * @param size The length required to malloc. - * @param alignbytes The alignment size. - * @retval The allocated memory. - */ -void *SDK_Malloc(size_t size, size_t alignbytes); - -/*! - * @brief Free memory. - * - * @param ptr The memory to be release. - */ -void SDK_Free(void *ptr); -#endif - -/*! - * @brief Delay at least for some time. - * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, - * if precise delay count was needed, please implement a new delay function with hardware timer. - * - * @param delayTime_us Delay time in unit of microsecond. - * @param coreClock_Hz Core clock frequency with Hz. - */ -void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#if (defined(__DSC__) && defined(__CW__)) -#include "fsl_common_dsc.h" -#elif defined(__XCC__) -#include "fsl_common_dsp.h" -#else -#include "fsl_common_arm.h" -#endif - -#endif /* _FSL_COMMON_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common_arm.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common_arm.c deleted file mode 100644 index e77a265ce43..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common_arm.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.common_arm" -#endif - -#ifndef __GIC_PRIO_BITS -#if defined(ENABLE_RAM_VECTOR_TABLE) -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) -{ -#ifdef __VECTOR_TABLE -#undef __VECTOR_TABLE -#endif - -/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) - extern uint32_t Image$$VECTOR_ROM$$Base[]; - extern uint32_t Image$$VECTOR_RAM$$Base[]; - extern uint32_t Image$$RW_m_data$$Base[]; - -#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base -#define __VECTOR_RAM Image$$VECTOR_RAM$$Base -#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) -#elif defined(__ICCARM__) - extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; -#elif defined(__GNUC__) - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; - extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; - uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); -#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ - uint32_t n; - uint32_t ret; - uint32_t irqMaskValue; - - irqMaskValue = DisableGlobalIRQ(); - if (SCB->VTOR != (uint32_t)__VECTOR_RAM) - { - /* Copy the vector table from ROM to RAM */ - for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) - { - __VECTOR_RAM[n] = __VECTOR_TABLE[n]; - } - /* Point the VTOR to the position of vector table */ - SCB->VTOR = (uint32_t)__VECTOR_RAM; - } - - ret = __VECTOR_RAM[(int32_t)irq + 16]; - /* make sure the __VECTOR_RAM is noncachable */ - __VECTOR_RAM[(int32_t)irq + 16] = irqHandler; - - EnableGlobalIRQ(irqMaskValue); - - return ret; -} -#endif /* ENABLE_RAM_VECTOR_TABLE. */ -#endif /* __GIC_PRIO_BITS. */ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - -/* - * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, - * powerlib should be used instead of these functions. - */ -#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) - -/* - * When the SYSCON STARTER registers are discontinuous, these functions are - * implemented in fsl_power.c. - */ -#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) - -void EnableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t intNumber = (uint32_t)interrupt; - - uint32_t index = 0; - - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERSET[index] = 1UL << intNumber; - (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */ -} - -void DisableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t intNumber = (uint32_t)interrupt; - - (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */ - uint32_t index = 0; - - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERCLR[index] = 1UL << intNumber; -} -#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ -#endif /* FSL_FEATURE_POWERLIB_EXTEND */ -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - -#if defined(SDK_DELAY_USE_DWT) && defined(DWT) -/* Use WDT. */ -static void enableCpuCycleCounter(void) -{ - /* Make sure the DWT trace fucntion is enabled. */ - if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) - { - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - } - - /* CYCCNT not supported on this device. */ - assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); - - /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */ - if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) - { - DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; - } -} - -static uint32_t getCpuCycleCount(void) -{ - return DWT->CYCCNT; -} -#else /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ -/* Use software loop. */ -#if defined(__CC_ARM) /* This macro is arm v5 specific */ -/* clang-format off */ -__ASM static void DelayLoop(uint32_t count) -{ -loop - SUBS R0, R0, #1 - CMP R0, #0 - BNE loop - BX LR -} -/* clang-format on */ -#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__) -/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler, - * use SUB and CMP here for compatibility */ -static void DelayLoop(uint32_t count) -{ - __ASM volatile(" MOV R0, %0" : : "r"(count)); - __ASM volatile( - "loop: \n" -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) - " SUB R0, R0, #1 \n" -#else - " SUBS R0, R0, #1 \n" -#endif - " CMP R0, #0 \n" - - " BNE loop \n" - : - : - : "r0"); -} -#endif /* defined(__CC_ARM) */ -#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ - -/*! - * @brief Delay at least for some time. - * Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have - * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and - * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports - * up to 4294967 in current code. If long time delay is needed, please implement a new delay function. - * - * @param delayTime_us Delay time in unit of microsecond. - * @param coreClock_Hz Core clock frequency with Hz. - */ -void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) -{ - uint64_t count; - - if (delayTime_us > 0U) - { - count = USEC_TO_COUNT(delayTime_us, coreClock_Hz); - - assert(count <= UINT32_MAX); - -#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */ - - enableCpuCycleCounter(); - /* Calculate the count ticks. */ - count += getCpuCycleCount(); - - if (count > UINT32_MAX) - { - count -= UINT32_MAX; - /* Wait for cyccnt overflow. */ - while (count < getCpuCycleCount()) - { - } - } - - /* Wait for cyccnt reach count value. */ - while (count > getCpuCycleCount()) - { - } -#else - /* Divide value may be different in various environment to ensure delay is precise. - * Every loop count includes three instructions, due to Cortex-M7 sometimes executes - * two instructions in one period, through test here set divide 1.5. Other M cores use - * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does - * not matter because other instructions outside while loop is enough to fill the time. - */ -#if (__CORTEX_M == 7) - count = count / 3U * 2U; -#else - count = count / 4U; -#endif - DelayLoop((uint32_t)count); -#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common_arm.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common_arm.h deleted file mode 100644 index 2678ff625c7..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common_arm.h +++ /dev/null @@ -1,671 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_COMMON_ARM_H_ -#define _FSL_COMMON_ARM_H_ - -/* - * For CMSIS pack RTE. - * CMSIS pack RTE generates "RTC_Components.h" which contains the statements - * of the related element for all selected software components. - */ -#ifdef _RTE_ -#include "RTE_Components.h" -#endif - -/*! - * @addtogroup ksdk_common - * @{ - */ - -/*! @name Atomic modification - * - * These macros are used for atomic access, such as read-modify-write - * to the peripheral registers. - * - * - SDK_ATOMIC_LOCAL_ADD - * - SDK_ATOMIC_LOCAL_SET - * - SDK_ATOMIC_LOCAL_CLEAR - * - SDK_ATOMIC_LOCAL_TOGGLE - * - SDK_ATOMIC_LOCAL_CLEAR_AND_SET - * - * Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr - * means the address of the peripheral register or variable you want to modify - * atomically, the parameter @c clearBits is the bits to clear, the parameter - * @c setBits it the bits to set. - * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this: - * - * @code - volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR; - - SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02); - @endcode - * - * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result, - * register bit1:bit0 = 0b10. - * - * @note For the platforms don't support exclusive load and store, these macros - * disable the global interrupt to pretect the modification. - * - * @note These macros only guarantee the local processor atomic operations. For - * the multi-processor devices, use hardware semaphore such as SEMA42 to - * guarantee exclusive access if necessary. - * - * @{ - */ - -/* clang-format off */ -#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) -/* clang-format on */ - -/* If the LDREX and STREX are supported, use them. */ -#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \ - do \ - { \ - (val) = __LDREXB(addr); \ - (ops); \ - } while (0UL != __STREXB((val), (addr))) - -#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \ - do \ - { \ - (val) = __LDREXH(addr); \ - (ops); \ - } while (0UL != __STREXH((val), (addr))) - -#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \ - do \ - { \ - (val) = __LDREXW(addr); \ - (ops); \ - } while (0UL != __STREXW((val), (addr))) - -static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val); -} - -static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val); -} - -static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val); -} - -static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val); -} - -static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val); -} - -static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val); -} - -static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits); -} - -static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits); -} - -static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits); -} - -static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits); -} - -static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits); -} - -static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits); -} - -static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits); -} - -static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits); -} - -static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits); -} - -static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits) -{ - uint8_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); -} - -static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits) -{ - uint16_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); -} - -static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits) -{ - uint32_t s_val; - - _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); -} - -#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ - ((1UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalAdd1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \ - ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \ - _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val)))) - -#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ - ((1UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ - ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ - _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) - -#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ - ((1UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalClear1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ - ((2UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalClear2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ - _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) - -#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ - ((1UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalToggle1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ - ((2UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalToggle2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ - _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) - -#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ - ((1UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(clearBits), (uint8_t)(setBits)) : \ - ((2UL == sizeof(*(addr))) ? \ - _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(clearBits), (uint16_t)(setBits)) : \ - _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(clearBits), (uint32_t)(setBits)))) -#else - -#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ - do \ - { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) += (val); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ - do \ - { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) |= (bits); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ - do \ - { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) &= ~(bits); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ - do \ - { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) ^= (bits); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ - do \ - { \ - uint32_t s_atomicOldInt; \ - s_atomicOldInt = DisableGlobalIRQ(); \ - *(addr) = (*(addr) & ~(clearBits)) | (setBits); \ - EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) - -#endif -/* @} */ - -/*! @name Timer utilities */ -/* @{ */ -/*! Macro to convert a microsecond period to raw count value */ -#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) -/*! Macro to convert a raw count value to microsecond */ -#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000000U / (clockFreqInHz)) - -/*! Macro to convert a millisecond period to raw count value */ -#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) -/*! Macro to convert a raw count value to millisecond */ -#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz)) -/* @} */ - -/*! @name ISR exit barrier - * @{ - * - * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - * exception return operation might vector to incorrect interrupt. - * For Cortex-M7, if core speed much faster than peripheral register write speed, - * the peripheral interrupt flags may be still set after exiting ISR, this results to - * the same error similar with errata 83869. - */ -#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U)) -#define SDK_ISR_EXIT_BARRIER __DSB() -#else -#define SDK_ISR_EXIT_BARRIER -#endif - -/* @} */ - -/*! @name Alignment variable definition macros */ -/* @{ */ -#if (defined(__ICCARM__)) -/* - * Workaround to disable MISRA C message suppress warnings for IAR compiler. - * http:/ /supp.iar.com/Support/?note=24725 - */ -_Pragma("diag_suppress=Pm120") -#define SDK_PRAGMA(x) _Pragma(#x) - _Pragma("diag_error=Pm120") -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var -#elif defined(__GNUC__) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) -#else -#error Toolchain not supported -#endif - -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#endif - -/*! Macro to change a value to a given size aligned value */ -#define SDK_SIZEALIGN(var, alignbytes) \ - ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) -/* @} */ - -/*! @name Non-cacheable region definition macros */ -/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or - * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable - * variables, please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, - * these zero-inited variables will be initialized to zero in system startup. - */ -/* @{ */ - -#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \ - defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) - -#if (defined(__ICCARM__)) -#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" -#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" - -#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var -#if (defined(__CC_ARM)) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var -#else -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var -#endif - -#elif (defined(__GNUC__)) -/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" - * in your projects to make sure the non-cacheable section variables will be initialized in system startup. - */ -#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) -#else -#error Toolchain not supported. -#endif - -#else - -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes) -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes) - -#endif - -/* @} */ - -/*! - * @name Time sensitive region - * @{ - */ -#if (defined(__ICCARM__)) -#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" -#define AT_QUICKACCESS_SECTION_DATA(var) var @"DataQuickAccess" -#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ - SDK_PRAGMA(data_alignment = alignbytes) var @"DataQuickAccess" -#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func -#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var -#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ - __attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var -#elif (defined(__GNUC__)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func -#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var -#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ - __attribute__((section("DataQuickAccess"))) var __attribute__((aligned(alignbytes))) -#else -#error Toolchain not supported. -#endif /* defined(__ICCARM__) */ - -/*! @name Ram Function */ -#if (defined(__ICCARM__)) -#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" -#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func -#elif (defined(__GNUC__)) -#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func -#else -#error Toolchain not supported. -#endif /* defined(__ICCARM__) */ -/* @} */ - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - void DefaultISR(void); -#endif - -/* - * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t - * defined in previous of this file. - */ -#include "fsl_clock.h" - -/* - * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral - */ -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) -#include "fsl_reset.h" -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief Enable specific interrupt. - * - * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt enabled successfully - * @retval kStatus_Fail Failed to enable the interrupt - */ -static inline status_t EnableIRQ(IRQn_Type interrupt) -{ - status_t status = kStatus_Success; - - if (NotAvail_IRQn == interrupt) - { - status = kStatus_Fail; - } - -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - status = kStatus_Fail; - } -#endif - - else - { -#if defined(__GIC_PRIO_BITS) - GIC_EnableIRQ(interrupt); -#else - NVIC_EnableIRQ(interrupt); -#endif - } - - return status; -} - -/*! - * @brief Disable specific interrupt. - * - * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt disabled successfully - * @retval kStatus_Fail Failed to disable the interrupt - */ -static inline status_t DisableIRQ(IRQn_Type interrupt) -{ - status_t status = kStatus_Success; - - if (NotAvail_IRQn == interrupt) - { - status = kStatus_Fail; - } - -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - status = kStatus_Fail; - } -#endif - - else - { -#if defined(__GIC_PRIO_BITS) - GIC_DisableIRQ(interrupt); -#else - NVIC_DisableIRQ(interrupt); -#endif - } - - return status; -} - -/*! - * @brief Disable the global IRQ - * - * Disable the global interrupt and return the current primask register. User is required to provided the primask - * register for the EnableGlobalIRQ(). - * - * @return Current primask value. - */ -static inline uint32_t DisableGlobalIRQ(void) -{ -#if defined(CPSR_I_Msk) - uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; - - __disable_irq(); - - return cpsr; -#else - uint32_t regPrimask = __get_PRIMASK(); - - __disable_irq(); - - return regPrimask; -#endif -} - -/*! - * @brief Enable the global IRQ - * - * Set the primask register with the provided primask value but not just enable the primask. The idea is for the - * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to - * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. - * - * @param primask value of primask register to be restored. The primask value is supposed to be provided by the - * DisableGlobalIRQ(). - */ -static inline void EnableGlobalIRQ(uint32_t primask) -{ -#if defined(CPSR_I_Msk) - __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); -#else - __set_PRIMASK(primask); -#endif -} - -#if defined(ENABLE_RAM_VECTOR_TABLE) -/*! - * @brief install IRQ handler - * - * @param irq IRQ number - * @param irqHandler IRQ handler address - * @return The old IRQ handler address - */ -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); -#endif /* ENABLE_RAM_VECTOR_TABLE. */ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - -/* - * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, - * powerlib should be used instead of these functions. - */ -#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) -/*! - * @brief Enable specific interrupt for wake-up from deep-sleep mode. - * - * Enable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). - * - * @param interrupt The IRQ number. - */ -void EnableDeepSleepIRQ(IRQn_Type interrupt); - -/*! - * @brief Disable specific interrupt for wake-up from deep-sleep mode. - * - * Disable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). - * - * @param interrupt The IRQ number. - */ -void DisableDeepSleepIRQ(IRQn_Type interrupt); -#endif /* FSL_FEATURE_POWERLIB_EXTEND */ -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @} */ - -#endif /* _FSL_COMMON_ARM_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.c deleted file mode 100644 index c73f84997af..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2019-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_crc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_crc" -#endif - -#if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT -/* @brief Default user configuration structure for CRC-CCITT */ -#define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT -/*< CRC-CCIT polynomial x^16 + x^12 + x^5 + x^0 */ -#define CRC_DRIVER_DEFAULT_REVERSE_IN false -/*< Default is no bit reverse */ -#define CRC_DRIVER_DEFAULT_COMPLEMENT_IN false -/*< Default is without complement of written data */ -#define CRC_DRIVER_DEFAULT_REVERSE_OUT false -/*< Default is no bit reverse */ -#define CRC_DRIVER_DEFAULT_COMPLEMENT_OUT false -/*< Default is without complement of CRC data register read data */ -#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU -/*< Default initial checksum */ -#endif /* CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Enables and configures the CRC peripheral module. - * - * This functions enables the CRC peripheral clock in the LPC SYSCON block. - * It also configures the CRC engine and starts checksum computation by writing the seed. - * - * param base CRC peripheral address. - * param config CRC module configuration structure. - */ -void CRC_Init(CRC_Type *base, const crc_config_t *config) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* enable clock to CRC */ - CLOCK_EnableClock(kCLOCK_Crc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_CRC_HAS_NO_RESET) && FSL_FEATURE_CRC_HAS_NO_RESET) - RESET_PeripheralReset(kCRC_RST_SHIFT_RSTn); -#endif - - /* configure CRC module and write the seed */ - base->MODE = CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) | - CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) | - CRC_MODE_CMPL_SUM(config->complementOut); - base->SEED = config->seed; -} - -/*! - * brief Loads default values to CRC protocol configuration structure. - * - * Loads default values to CRC protocol configuration structure. The default values are: - * code - * config->polynomial = kCRC_Polynomial_CRC_CCITT; - * config->reverseIn = false; - * config->complementIn = false; - * config->reverseOut = false; - * config->complementOut = false; - * config->seed = 0xFFFFU; - * endcode - * - * param config CRC protocol configuration structure - */ -void CRC_GetDefaultConfig(crc_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_REVERSE_IN, - CRC_DRIVER_DEFAULT_COMPLEMENT_IN, CRC_DRIVER_DEFAULT_REVERSE_OUT, - CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED}; - - *config = default_config; -} - -/*! - * brief resets CRC peripheral module. - * - * param base CRC peripheral address. - */ -void CRC_Reset(CRC_Type *base) -{ - crc_config_t config; - CRC_GetDefaultConfig(&config); - CRC_Init(base, &config); -} - -/*! - * brief Write seed (initial checksum) to CRC peripheral module. - * - * param base CRC peripheral address. - * param seed CRC Seed value. - */ -void CRC_WriteSeed(CRC_Type *base, uint32_t seed) -{ - /* write the seed (initial checksum) */ - base->SEED = seed; -} - -/*! - * brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure. - * - * The values, including seed, can be used to resume CRC calculation later. - - * param base CRC peripheral address. - * param config CRC protocol configuration structure - */ -void CRC_GetConfig(CRC_Type *base, crc_config_t *config) -{ - /* extract CRC mode settings */ - uint32_t mode = base->MODE; - config->polynomial = - (crc_polynomial_t)(uint32_t)(((uint32_t)(mode & CRC_MODE_CRC_POLY_MASK)) >> CRC_MODE_CRC_POLY_SHIFT); - config->reverseIn = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK); - config->complementIn = (bool)(mode & CRC_MODE_CMPL_WR_MASK); - config->reverseOut = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK); - config->complementOut = (bool)(mode & CRC_MODE_CMPL_SUM_MASK); - - /* reset CRC sum bit reverse and 1's complement setting, so its value can be used as a seed */ - base->MODE = mode & ~((1U << CRC_MODE_BIT_RVS_SUM_SHIFT) | (1U << CRC_MODE_CMPL_SUM_SHIFT)); - - /* now we can obtain intermediate raw CRC sum value */ - config->seed = base->SUM; - - /* restore original CRC sum bit reverse and 1's complement setting */ - base->MODE = mode; -} - -/*! - * brief Writes data to the CRC module. - * - * Writes input data buffer bytes to CRC data register. - * - * param base CRC peripheral address. - * param data Input data stream, MSByte in data[0]. - * param dataSize Size of the input data buffer in bytes. - */ -void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) -{ - const uint32_t *data32; - - /* 8-bit reads and writes till source address is aligned 4 bytes */ - while ((0U != dataSize) && (0U != ((uint32_t)data & 3U))) - { - *((__O uint8_t *)&(base->WR_DATA)) = *data; - data++; - dataSize--; - } - - /* use 32-bit reads and writes as long as possible */ - data32 = (const uint32_t *)(uint32_t)data; - while (dataSize >= sizeof(uint32_t)) - { - *((__O uint32_t *)&(base->WR_DATA)) = *data32; - data32++; - dataSize -= sizeof(uint32_t); - } - - data = (const uint8_t *)data32; - - /* 8-bit reads and writes till end of data buffer */ - while (0U != dataSize) - { - *((__O uint8_t *)&(base->WR_DATA)) = *data; - data++; - dataSize--; - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.h deleted file mode 100644 index 08e08bd57d3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2019-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CRC_H_ -#define _FSL_CRC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup crc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CRC driver version. Version 2.1.1. - * - * Current version: 2.1.1 - * - * Change log: - * - Version 2.0.0 - * - initial version - * - Version 2.0.1 - * - add explicit type cast when writing to WR_DATA - * - Version 2.0.2 - * - Fix MISRA issue - * - Version 2.1.0 - * - Add CRC_WriteSeed function - * - Version 2.1.1 - * - Fix MISRA issue - */ -#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) -/*@}*/ - -#ifndef CRC_DRIVER_CUSTOM_DEFAULTS -/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Uses CRC-16/CCITT-FALSE as default. */ -#define CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT 1 -#endif - -/*! @brief CRC polynomials to use. */ -typedef enum _crc_polynomial -{ - kCRC_Polynomial_CRC_CCITT = 0U, /*!< x^16+x^12+x^5+1 */ - kCRC_Polynomial_CRC_16 = 1U, /*!< x^16+x^15+x^2+1 */ - kCRC_Polynomial_CRC_32 = 2U /*!< x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */ -} crc_polynomial_t; - -/*! - * @brief CRC protocol configuration. - * - * This structure holds the configuration for the CRC protocol. - * - */ -typedef struct _crc_config -{ - crc_polynomial_t polynomial; /*!< CRC polynomial. */ - bool reverseIn; /*!< Reverse bits on input. */ - bool complementIn; /*!< Perform 1's complement on input. */ - bool reverseOut; /*!< Reverse bits on output. */ - bool complementOut; /*!< Perform 1's complement on output. */ - uint32_t seed; /*!< Starting checksum value. */ -} crc_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Enables and configures the CRC peripheral module. - * - * This functions enables the CRC peripheral clock in the LPC SYSCON block. - * It also configures the CRC engine and starts checksum computation by writing the seed. - * - * @param base CRC peripheral address. - * @param config CRC module configuration structure. - */ -void CRC_Init(CRC_Type *base, const crc_config_t *config); - -/*! - * @brief Disables the CRC peripheral module. - * - * This functions disables the CRC peripheral clock in the LPC SYSCON block. - * - * @param base CRC peripheral address. - */ -static inline void CRC_Deinit(CRC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* disable clock to CRC */ - CLOCK_DisableClock(kCLOCK_Crc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief resets CRC peripheral module. - * - * @param base CRC peripheral address. - */ -void CRC_Reset(CRC_Type *base); - -/*! - * @brief Write seed to CRC peripheral module. - * - * @param base CRC peripheral address. - * @param seed CRC Seed value. - */ -void CRC_WriteSeed(CRC_Type *base, uint32_t seed); - -/*! - * @brief Loads default values to CRC protocol configuration structure. - * - * Loads default values to CRC protocol configuration structure. The default values are: - * @code - * config->polynomial = kCRC_Polynomial_CRC_CCITT; - * config->reverseIn = false; - * config->complementIn = false; - * config->reverseOut = false; - * config->complementOut = false; - * config->seed = 0xFFFFU; - * @endcode - * - * @param config CRC protocol configuration structure - */ -void CRC_GetDefaultConfig(crc_config_t *config); - -/*! - * @brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure. - * - * The values, including seed, can be used to resume CRC calculation later. - - * @param base CRC peripheral address. - * @param config CRC protocol configuration structure - */ -void CRC_GetConfig(CRC_Type *base, crc_config_t *config); - -/*! - * @brief Writes data to the CRC module. - * - * Writes input data buffer bytes to CRC data register. - * - * @param base CRC peripheral address. - * @param data Input data stream, MSByte in data[0]. - * @param dataSize Size of the input data buffer in bytes. - */ -void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize); - -/*! - * @brief Reads 32-bit checksum from the CRC module. - * - * Reads CRC data register. - * - * @param base CRC peripheral address. - * @return final 32-bit checksum, after configured bit reverse and complement operations. - */ -static inline uint32_t CRC_Get32bitResult(CRC_Type *base) -{ - return base->SUM; -} - -/*! - * @brief Reads 16-bit checksum from the CRC module. - * - * Reads CRC data register. - * - * @param base CRC peripheral address. - * @return final 16-bit checksum, after configured bit reverse and complement operations. - */ -static inline uint16_t CRC_Get16bitResult(CRC_Type *base) -{ - return (uint16_t)base->SUM; -} - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_CRC_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.c deleted file mode 100644 index e53bebdd013..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.c +++ /dev/null @@ -1,577 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_ctimer.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.ctimer" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base Ctimer peripheral base address - * - * @return The Timer instance - */ -static uint32_t CTIMER_GetInstance(CTIMER_Type *base); - -/*! - * @brief CTIMER generic IRQ handle function. - * - * @param index FlexCAN peripheral instance index. - */ -static void CTIMER_GenericIRQHandler(uint32_t index); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to Timer bases for each instance. */ -static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to Timer clocks for each instance. */ -static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET -/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N; -#else -/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; -#endif -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/*! @brief Pointers real ISRs installed by drivers for each instance. */ -static ctimer_callback_t *s_ctimerCallback[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = {0}; - -/*! @brief Callback type installed by drivers for each instance. */ -static ctimer_callback_type_t ctimerCallbackType[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = { - kCTIMER_SingleCallback}; - -/*! @brief Array to map timer instance to IRQ number. */ -static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t CTIMER_GetInstance(CTIMER_Type *base) -{ - uint32_t instance; - uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ctimerArrayCount; instance++) - { - if (s_ctimerBases[instance] == base) - { - break; - } - } - - assert(instance < ctimerArrayCount); - - return instance; -} - -/*! - * brief Ungates the clock and configures the peripheral for basic operation. - * - * note This API should be called at the beginning of the application before using the driver. - * - * param base Ctimer peripheral base address - * param config Pointer to the user configuration structure. - */ -void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) -{ - assert(config != NULL); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the timer clock*/ - CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -/* Reset the module. */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) - RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]); -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/* Setup the cimer mode and count select */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input); -#endif - /* Setup the timer prescale value */ - base->PR = CTIMER_PR_PRVAL(config->prescale); -} - -/*! - * brief Gates the timer clock. - * - * param base Ctimer peripheral base address - */ -void CTIMER_Deinit(CTIMER_Type *base) -{ - uint32_t index = CTIMER_GetInstance(base); - /* Stop the timer */ - base->TCR &= ~CTIMER_TCR_CEN_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the timer clock*/ - CLOCK_DisableClock(s_ctimerClocks[index]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Disable IRQ at NVIC Level */ - (void)DisableIRQ(s_ctimerIRQ[index]); -} - -/*! - * brief Fills in the timers configuration structure with the default settings. - * - * The default values are: - * code - * config->mode = kCTIMER_TimerMode; - * config->input = kCTIMER_Capture_0; - * config->prescale = 0; - * endcode - * param config Pointer to the user configuration structure. - */ -void CTIMER_GetDefaultConfig(ctimer_config_t *config) -{ - assert(config != NULL); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* Run as a timer */ - config->mode = kCTIMER_TimerMode; - /* This field is ignored when mode is timer */ - config->input = kCTIMER_Capture_0; - /* Timer counter is incremented on every APB bus clock */ - config->prescale = 0; -} - -/*! - * brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function can manually assign the specified channel to set the PWM cycle. - * - * note When setting PWM output from multiple output pins, all should use the same PWM - * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. - * - * param base Ctimer peripheral base address - * param pwmPeriodChannel Specify the channel to control the PWM period - * param matchChannel Match pin to be used to output the PWM signal - * param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 - * param pwmFreq_Hz PWM signal frequency in Hz - * param srcClock_Hz Timer counter clock in Hz - * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt will be generated. - * - * return kStatus_Success on success - * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM cycle - */ -status_t CTIMER_SetupPwm(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - bool enableInt) -{ - assert(pwmFreq_Hz > 0U); - - uint32_t reg; - uint32_t period, pulsePeriod = 0; - uint32_t timerClock = srcClock_Hz / (base->PR + 1U); - uint32_t index = CTIMER_GetInstance(base); - - if (matchChannel == pwmPeriodChannel) - { - return kStatus_Fail; - } - - /* Enable PWM mode on the match channel */ - base->PWMC |= (1UL << (uint32_t)matchChannel); - - /* Clear the stop, reset and interrupt bits for this channel */ - reg = base->MCR; - reg &= - ~(((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK)) - << ((uint32_t)matchChannel * 3U)); - - /* If call back function is valid then enable match interrupt for the channel */ - if (enableInt) - { - reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); - } - - /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ - reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); - - base->MCR = reg; - - /* Calculate PWM period match value */ - period = (timerClock / pwmFreq_Hz) - 1U; - - /* Calculate pulse width match value */ - if (dutyCyclePercent == 0U) - { - pulsePeriod = period + 1U; - } - else - { - pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; - } - - /* Specified channel pwmPeriodChannel will define the PWM period */ - base->MR[pwmPeriodChannel] = period; - - /* This will define the PWM pulse period */ - base->MR[matchChannel] = pulsePeriod; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); - /* If call back function is valid then enable interrupt and update the call back function */ - if (enableInt) - { - (void)EnableIRQ(s_ctimerIRQ[index]); - } - - return kStatus_Success; -} - -/*! - * brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function can manually assign the specified channel to set the PWM cycle. - * - * note When setting PWM output from multiple output pins, all should use the same PWM - * period - * - * param base Ctimer peripheral base address - * param pwmPeriodChannel Specify the channel to control the PWM period - * param matchChannel Match pin to be used to output the PWM signal - * param pwmPeriod PWM period match value - * param pulsePeriod Pulse width match value - * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt will be generated. - * - * return kStatus_Success on success - * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM period - */ -status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint32_t pwmPeriod, - uint32_t pulsePeriod, - bool enableInt) -{ -/* Some CTimers only have 16bits , so the value is limited*/ -#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B - assert(!((FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32) && (pulsePeriod > 0xFFFFU))); -#endif - - uint32_t reg; - uint32_t index = CTIMER_GetInstance(base); - - if (matchChannel == pwmPeriodChannel) - { - return kStatus_Fail; - } - - /* Enable PWM mode on PWM pulse channel */ - base->PWMC |= (1UL << (uint32_t)matchChannel); - - /* Clear the stop, reset and interrupt bits for PWM pulse channel */ - reg = base->MCR; - reg &= - ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) - << ((uint32_t)matchChannel * 3U)); - - /* If call back function is valid then enable match interrupt for PWM pulse channel */ - if (enableInt) - { - reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); - } - - /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ - reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); - - base->MCR = reg; - - /* Specified channel pwmPeriodChannel will define the PWM period */ - base->MR[pwmPeriodChannel] = pwmPeriod; - - /* This will define the PWM pulse period */ - base->MR[matchChannel] = pulsePeriod; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); - /* If call back function is valid then enable interrupt and update the call back function */ - if (enableInt) - { - (void)EnableIRQ(s_ctimerIRQ[index]); - } - - return kStatus_Success; -} - -/*! - * brief Updates the duty cycle of an active PWM signal. - * - * note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. - * This function can manually assign the specified channel to set the PWM cycle. - * - * param base Ctimer peripheral base address - * param pwmPeriodChannel Specify the channel to control the PWM period - * param matchChannel Match pin to be used to output the PWM signal - * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 - */ -void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent) -{ - uint32_t pulsePeriod = 0, period; - - /* Specified channel pwmPeriodChannel defines the PWM period */ - period = base->MR[pwmPeriodChannel]; - - /* For 0% dutycyle, make pulse period greater than period so the event will never occur */ - if (dutyCyclePercent == 0U) - { - pulsePeriod = period + 1U; - } - else - { - pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; - } - - /* Update dutycycle */ - base->MR[matchChannel] = pulsePeriod; -} - -/*! - * brief Setup the match register. - * - * User configuration is used to setup the match value and action to be taken when a match occurs. - * - * param base Ctimer peripheral base address - * param matchChannel Match register to configure - * param config Pointer to the match configuration structure - */ -void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config) -{ -/* Some CTimers only have 16bits , so the value is limited*/ -#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B - assert(!(FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32 && config->matchValue > 0xFFFFU)); -#endif - uint32_t reg; - uint32_t index = CTIMER_GetInstance(base); - - /* Set the counter operation when a match on this channel occurs */ - reg = base->MCR; - reg &= - ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) - << ((uint32_t)matchChannel * 3U)); - reg |= ((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)matchChannel * 3U))); - reg |= ((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)matchChannel * 3U))); - reg |= ((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); - base->MCR = reg; - - reg = base->EMR; - /* Set the match output operation when a match on this channel occurs */ - reg &= ~(((uint32_t)CTIMER_EMR_EMC0_MASK) << ((uint32_t)matchChannel * 2U)); - reg |= ((uint32_t)config->outControl) << (CTIMER_EMR_EMC0_SHIFT + ((uint32_t)matchChannel * 2U)); - - /* Set the initial state of the EM bit/output */ - reg &= ~(((uint32_t)CTIMER_EMR_EM0_MASK) << (uint32_t)matchChannel); - reg |= ((uint32_t)config->outPinInitState) << (uint32_t)matchChannel; - base->EMR = reg; - - /* Set the match value */ - base->MR[matchChannel] = config->matchValue; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); - /* If interrupt is enabled then enable interrupt and update the call back function */ - if (config->enableInterrupt) - { - (void)EnableIRQ(s_ctimerIRQ[index]); - } -} - -/*! - * brief Get the status of output match. - * - * This function gets the status of output MAT, whether or not this output is connected to a pin. - * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - * - * param base Ctimer peripheral base address - * param matchChannel External match channel, user can obtain the status of multiple match channels - * at the same time by using the logic of "|" - * enumeration ::ctimer_external_match_t - * return The mask of external match channel status flags. Users need to use the - * _ctimer_external_match type to decode the return variables. - */ -uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel) -{ - return (base->EMR & matchChannel); -} - -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) -/*! - * brief Setup the capture. - * - * param base Ctimer peripheral base address - * param capture Capture channel to configure - * param edge Edge on the channel that will trigger a capture - * param enableInt Flag to enable channel interrupts, if enabled then the registered call back - * is called upon capture - */ -void CTIMER_SetupCapture(CTIMER_Type *base, - ctimer_capture_channel_t capture, - ctimer_capture_edge_t edge, - bool enableInt) -{ - uint32_t reg = base->CCR; - uint32_t index = CTIMER_GetInstance(base); - - /* Set the capture edge */ - reg &= ~((uint32_t)((uint32_t)CTIMER_CCR_CAP0RE_MASK | (uint32_t)CTIMER_CCR_CAP0FE_MASK | - (uint32_t)CTIMER_CCR_CAP0I_MASK) - << ((uint32_t)capture * 3U)); - reg |= ((uint32_t)edge) << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U)); - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, (((uint32_t)kCTIMER_Capture0Flag) << (uint32_t)capture)); - /* If call back function is valid then enable capture interrupt for the channel and update the call back function */ - if (enableInt) - { - reg |= ((uint32_t)CTIMER_CCR_CAP0I_MASK) << ((uint32_t)capture * 3U); - (void)EnableIRQ(s_ctimerIRQ[index]); - } - base->CCR = reg; -} -#endif - -/*! - * brief Register callback. - * - * param base Ctimer peripheral base address - * param cb_func callback function - * param cb_type callback function type, singular or multiple - */ -void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type) -{ - uint32_t index = CTIMER_GetInstance(base); - s_ctimerCallback[index] = cb_func; - ctimerCallbackType[index] = cb_type; -} - -/*! - * brief CTIMER generic IRQ handle function. - * - * param index FlexCAN peripheral instance index. - */ -static void CTIMER_GenericIRQHandler(uint32_t index) -{ - uint32_t int_stat, i, mask; - /* Get Interrupt status flags */ - int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]); - /* Clear the status flags that were set */ - CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat); - if (ctimerCallbackType[index] == kCTIMER_SingleCallback) - { - if (s_ctimerCallback[index][0] != NULL) - { - s_ctimerCallback[index][0](int_stat); - } - } - else - { -#if defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE - for (i = 0; i <= CTIMER_IR_MR3INT_SHIFT; i++) -#else -#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT - for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) -#else -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) - for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) -#else - for (i = 0; i <= CTIMER_IR_CR1INT_SHIFT; i++) -#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ -#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ -#endif - { - mask = 0x01UL << i; - /* For each status flag bit that was set call the callback function if it is valid */ - if (((int_stat & mask) != 0U) && (s_ctimerCallback[index][i] != NULL)) - { - s_ctimerCallback[index][i](int_stat); - } - } - } - SDK_ISR_EXIT_BARRIER; -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(CTIMER0) -void CTIMER0_DriverIRQHandler(void); -void CTIMER0_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(0); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CTIMER1) -void CTIMER1_DriverIRQHandler(void); -void CTIMER1_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(1); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CTIMER2) -void CTIMER2_DriverIRQHandler(void); -void CTIMER2_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(2); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CTIMER3) -void CTIMER3_DriverIRQHandler(void); -void CTIMER3_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(3); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(CTIMER4) -void CTIMER4_DriverIRQHandler(void); -void CTIMER4_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(4); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.h deleted file mode 100644 index ca39c95d30e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.h +++ /dev/null @@ -1,533 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_CTIMER_H_ -#define _FSL_CTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup ctimer - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) /*!< Version 2.2.2 */ -/*@}*/ - -/*! @brief List of Timer capture channels */ -typedef enum _ctimer_capture_channel -{ - kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ - kCTIMER_Capture_1, /*!< Timer capture channel 1 */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - kCTIMER_Capture_2, /*!< Timer capture channel 2 */ -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - kCTIMER_Capture_3 /*!< Timer capture channel 3 */ -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ -} ctimer_capture_channel_t; - -/*! @brief List of capture edge options */ -typedef enum _ctimer_capture_edge -{ - kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */ - kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */ - kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */ -} ctimer_capture_edge_t; - -/*! @brief List of Timer match registers */ -typedef enum _ctimer_match -{ - kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */ - kCTIMER_Match_1, /*!< Timer match register 1 */ - kCTIMER_Match_2, /*!< Timer match register 2 */ - kCTIMER_Match_3 /*!< Timer match register 3 */ -} ctimer_match_t; - -/*! @brief List of external match */ -typedef enum _ctimer_external_match -{ - kCTIMER_External_Match_0 = (1U << 0), /*!< External match 0 */ - kCTIMER_External_Match_1 = (1U << 1), /*!< External match 1 */ - kCTIMER_External_Match_2 = (1U << 2), /*!< External match 2 */ - kCTIMER_External_Match_3 = (1U << 3) /*!< External match 3 */ -} ctimer_external_match_t; - -/*! @brief List of output control options */ -typedef enum _ctimer_match_output_control -{ - kCTIMER_Output_NoAction = 0U, /*!< No action is taken */ - kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */ - kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */ - kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */ -} ctimer_match_output_control_t; - -/*! @brief List of Timer modes */ -typedef enum _ctimer_timer_mode -{ - kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */ - kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */ - kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */ - kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */ -} ctimer_timer_mode_t; - -/*! @brief List of Timer interrupts */ -typedef enum _ctimer_interrupt_enable -{ - kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ - kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ - kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ - kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ - kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ -#endif -} ctimer_interrupt_enable_t; - -/*! @brief List of Timer flags */ -typedef enum _ctimer_status_flags -{ - kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ - kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ - kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ - kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ - kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) - kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ -#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ -#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT - kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ -#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ -#endif -} ctimer_status_flags_t; - -typedef void (*ctimer_callback_t)(uint32_t flags); - -/*! @brief Callback type when registering for a callback. When registering a callback - * an array of function pointers is passed the size could be 1 or 8, the callback - * type will tell that. - */ -typedef enum -{ - kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. - based on the status flags different channels needs to be handled differently */ - kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. - for both match/capture */ -} ctimer_callback_type_t; - -/*! - * @brief Match configuration - * - * This structure holds the configuration settings for each match register. - */ -typedef struct _ctimer_match_config -{ - uint32_t matchValue; /*!< This is stored in the match register */ - bool enableCounterReset; /*!< true: Match will reset the counter - false: Match will not reser the counter */ - bool enableCounterStop; /*!< true: Match will stop the counter - false: Match will not stop the counter */ - ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */ - bool outPinInitState; /*!< Initial value of the EM bit/output */ - bool enableInterrupt; /*!< true: Generate interrupt upon match - false: Do not generate interrupt on match */ - -} ctimer_match_config_t; - -/*! - * @brief Timer configuration structure - * - * This structure holds the configuration settings for the Timer peripheral. To initialize this - * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a - * pointer to the configuration structure instance. - * - * The configuration structure can be made constant so as to reside in flash. - */ -typedef struct _ctimer_config -{ - ctimer_timer_mode_t mode; /*!< Timer mode */ - ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer - modes that rely on this input signal to increment TC */ - uint32_t prescale; /*!< Prescale value */ -} ctimer_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application before using the driver. - * - * @param base Ctimer peripheral base address - * @param config Pointer to the user configuration structure. - */ -void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config); - -/*! - * @brief Gates the timer clock. - * - * @param base Ctimer peripheral base address - */ -void CTIMER_Deinit(CTIMER_Type *base); - -/*! - * @brief Fills in the timers configuration structure with the default settings. - * - * The default values are: - * @code - * config->mode = kCTIMER_TimerMode; - * config->input = kCTIMER_Capture_0; - * config->prescale = 0; - * @endcode - * @param config Pointer to the user configuration structure. - */ -void CTIMER_GetDefaultConfig(ctimer_config_t *config); - -/*! @}*/ - -/*! - * @name PWM setup operations - * @{ - */ - -/*! - * @brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function can manually assign the specified channel to set the PWM cycle. - * - * @note When setting PWM output from multiple output pins, all should use the same PWM - * period - * - * @param base Ctimer peripheral base address - * @param pwmPeriodChannel Specify the channel to control the PWM period - * @param matchChannel Match pin to be used to output the PWM signal - * @param pwmPeriod PWM period match value - * @param pulsePeriod Pulse width match value - * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt will be generated. - */ -status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint32_t pwmPeriod, - uint32_t pulsePeriod, - bool enableInt); - -/*! - * @brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function can manually assign the specified channel to set the PWM cycle. - * - * @note When setting PWM output from multiple output pins, all should use the same PWM - * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. - * - * @param base Ctimer peripheral base address - * @param pwmPeriodChannel Specify the channel to control the PWM period - * @param matchChannel Match pin to be used to output the PWM signal - * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz Timer counter clock in Hz - * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt will be generated. - */ -status_t CTIMER_SetupPwm(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - bool enableInt); - -/*! - * @brief Updates the pulse period of an active PWM signal. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match pin to be used to output the PWM signal - * @param pulsePeriod New PWM pulse width match value - */ -static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod) -{ - /* Update PWM pulse period match value */ - base->MR[matchChannel] = pulsePeriod; -} - -/*! - * @brief Updates the duty cycle of an active PWM signal. - * - * @note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. - * This function can manually assign the specified channel to set the PWM cycle. - * - * @param base Ctimer peripheral base address - * @param pwmPeriodChannel Specify the channel to control the PWM period - * @param matchChannel Match pin to be used to output the PWM signal - * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 - */ -void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, - const ctimer_match_t pwmPeriodChannel, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent); - -/*! @}*/ - -/*! - * @brief Setup the match register. - * - * User configuration is used to setup the match value and action to be taken when a match occurs. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match register to configure - * @param config Pointer to the match configuration structure - */ -void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config); - -/*! - * @brief Get the status of output match. - * - * This function gets the status of output MAT, whether or not this output is connected to a pin. - * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. - * - * @param base Ctimer peripheral base address - * @param matchChannel External match channel, user can obtain the status of multiple match channels - * at the same time by using the logic of "|" - * enumeration ::ctimer_external_match_t - * @return The mask of external match channel status flags. Users need to use the - * _ctimer_external_match type to decode the return variables. - */ -uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel); - -/*! - * @brief Setup the capture. - * - * @param base Ctimer peripheral base address - * @param capture Capture channel to configure - * @param edge Edge on the channel that will trigger a capture - * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back - * is called upon capture - */ -void CTIMER_SetupCapture(CTIMER_Type *base, - ctimer_capture_channel_t capture, - ctimer_capture_edge_t edge, - bool enableInt); - -/*! - * @brief Get the timer count value from TC register. - * - * @param base Ctimer peripheral base address. - * @return return the timer count value. - */ -static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base) -{ - return (base->TC); -} - -/*! - * @brief Register callback. - * - * @param base Ctimer peripheral base address - * @param cb_func callback function - * @param cb_type callback function type, singular or multiple - */ -void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type); - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected Timer interrupts. - * - * @param base Ctimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) -{ - /* Enable match interrupts */ - base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); - -/* Enable capture interrupts */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - | CTIMER_CCR_CAP2I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - ); -#endif -} - -/*! - * @brief Disables the selected Timer interrupts. - * - * @param base Ctimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) -{ - /* Disable match interrupts */ - base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK)); - -/* Disable capture interrupts */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - | CTIMER_CCR_CAP2I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - )); -#endif -} - -/*! - * @brief Gets the enabled Timer interrupts. - * - * @param base Ctimer peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) -{ - uint32_t enabledIntrs = 0; - - /* Get all the match interrupts enabled */ - enabledIntrs = - base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); - -/* Get all the capture interrupts enabled */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) - | CTIMER_CCR_CAP2I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - ); -#endif - - return enabledIntrs; -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the Timer status flags. - * - * @param base Ctimer peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::ctimer_status_flags_t - */ -static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base) -{ - return base->IR; -} - -/*! - * @brief Clears the Timer status flags. - * - * @param base Ctimer peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::ctimer_status_flags_t - */ -static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask) -{ - base->IR = mask; -} - -/*! @}*/ - -/*! - * @name Counter Start and Stop - * @{ - */ - -/*! - * @brief Starts the Timer counter. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_StartTimer(CTIMER_Type *base) -{ - base->TCR |= CTIMER_TCR_CEN_MASK; -} - -/*! - * @brief Stops the Timer counter. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_StopTimer(CTIMER_Type *base) -{ - base->TCR &= ~CTIMER_TCR_CEN_MASK; -} - -/*! @}*/ - -/*! - * @brief Reset the counter. - * - * The timer counter and prescale counter are reset on the next positive edge of the APB clock. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_Reset(CTIMER_Type *base) -{ - base->TCR |= CTIMER_TCR_CRST_MASK; - base->TCR &= ~CTIMER_TCR_CRST_MASK; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_CTIMER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.c deleted file mode 100644 index 6b7bc594ad0..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.c +++ /dev/null @@ -1,1079 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_dma.h" -#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) -#include "fsl_memory.h" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_dma" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for DMA. - * - * @param base DMA peripheral base address. - */ -static uint32_t DMA_GetInstance(DMA_Type *base); - -/*! - * @brief Get virtual channel number. - * - * @param base DMA peripheral base address. - */ -static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map DMA instance number to base pointer. */ -static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map DMA instance number to clock name. */ -static const clock_ip_name_t s_dmaClockName[] = DMA_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET) -/*! @brief Pointers to DMA resets for each instance. */ -static const reset_ip_name_t s_dmaResets[] = DMA_RSTS_N; -#endif /*! @brief Array to map DMA instance number to IRQ number. */ -static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS; - -/*! @brief Pointers to transfer handle for each DMA channel. */ -static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_ALL_CHANNELS]; - -/*! @brief DMA driver internal descriptor table */ -#ifdef FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE -SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE); -#else -#if (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) -AT_NONCACHEABLE_SECTION_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -#else -SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -#endif /* (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) */ -#endif /* FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE */ - -#if defined(DMA1) -#ifdef FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE -SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE); -#else -#if (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) -AT_NONCACHEABLE_SECTION_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -#else -SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -#endif /* (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) */ -#endif /* FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE */ -static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0, s_dma_descriptor_table1}; -#else -static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0}; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t DMA_GetInstance(DMA_Type *base) -{ - uint32_t instance; - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++) - { - if (s_dmaBases[instance] == base) - { - break; - } - } - assert(instance < ARRAY_SIZE(s_dmaBases)); - - return instance; -} - -static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base) -{ - uint32_t startChannel = 0, instance = 0; - uint32_t i = 0; - - instance = DMA_GetInstance(base); - - /* Compute start channel */ - for (i = 0; i < instance; i++) - { - startChannel += (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(s_dmaBases[i]); - } - - return startChannel; -} - -/*! - * brief Initializes DMA peripheral. - * - * This function enable the DMA clock, set descriptor table and - * enable DMA peripheral. - * - * param base DMA peripheral base address. - */ -void DMA_Init(DMA_Type *base) -{ - uint32_t instance = DMA_GetInstance(base); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* enable dma clock gate */ - CLOCK_EnableClock(s_dmaClockName[DMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET) - /* Reset the DMA module */ - RESET_PeripheralReset(s_dmaResets[DMA_GetInstance(base)]); -#endif - /* set descriptor table */ -#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) - base->SRAMBASE = MEMORY_ConvertMemoryMapAddress((uint32_t)s_dma_descriptor_table[instance], kMEMORY_Local2DMA); -#else - base->SRAMBASE = (uint32_t)s_dma_descriptor_table[instance]; -#endif - /* enable dma peripheral */ - base->CTRL |= DMA_CTRL_ENABLE_MASK; -} - -/*! - * brief Deinitializes DMA peripheral. - * - * This function gates the DMA clock. - * - * param base DMA peripheral base address. - */ -void DMA_Deinit(DMA_Type *base) -{ - /* Disable DMA peripheral */ - base->CTRL &= ~(DMA_CTRL_ENABLE_MASK); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(s_dmaClockName[DMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Set trigger settings of DMA channel. - * deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig. - * - * param base DMA peripheral base address. - * param channel DMA channel number. - * param trigger trigger configuration. - */ -void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger) -{ - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); - assert((channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)) && (NULL != trigger)); - - uint32_t tmpReg = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | - DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | - DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK); - tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); - tmpReg |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); - base->CHANNEL[channel].CFG = tmpReg; -} - -/*! - * brief Gets the remaining bytes of the current DMA descriptor transfer. - * - * param base DMA peripheral base address. - * param channel DMA channel number. - * return The number of bytes which have not been transferred yet. - */ -uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) -{ - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); - assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - - /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes - * impossible to distinguish between: - * - transfer finishes (represented by value '0x3FF') - * - and remaining 1024 bytes to transfer (value 0x3FF) - * for all descriptor in chain, except the last one. - * If you decide to use this function, please use 1023 transfers as maximal value */ - - /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */ - if ((!DMA_ChannelIsActive(base, channel)) && - (0x3FFUL == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> - DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))) - { - return 0UL; - } - - return ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> - DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + - 1UL; -} - -/* Verify and convert dma_xfercfg_t to XFERCFG register */ -static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr) -{ - assert(xfercfg != NULL); - /* check source increment */ - assert((xfercfg->srcInc <= (uint8_t)kDMA_AddressInterleave4xWidth) && - (xfercfg->dstInc <= (uint8_t)kDMA_AddressInterleave4xWidth)); - /* check data width */ - assert(xfercfg->byteWidth <= (uint8_t)kDMA_Transfer32BitWidth); - /* check transfer count */ - assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT); - - uint32_t xfer = 0; - - /* set valid flag - descriptor is ready now */ - xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid); - /* set reload - allow link to next descriptor */ - xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload); - /* set swtrig flag - start transfer */ - xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig); - /* set transfer count */ - xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig); - /* set INTA */ - xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA); - /* set INTB */ - xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB); - /* set data width */ - xfer |= DMA_CHANNEL_XFERCFG_WIDTH(xfercfg->byteWidth == 4U ? 2U : xfercfg->byteWidth - 1UL); - /* set source increment value */ - xfer |= DMA_CHANNEL_XFERCFG_SRCINC( - (xfercfg->srcInc == (uint8_t)kDMA_AddressInterleave4xWidth) ? (xfercfg->srcInc - 1UL) : xfercfg->srcInc); - /* set destination increment value */ - xfer |= DMA_CHANNEL_XFERCFG_DSTINC( - (xfercfg->dstInc == (uint8_t)kDMA_AddressInterleave4xWidth) ? (xfercfg->dstInc - 1UL) : xfercfg->dstInc); - /* set transfer count */ - xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1UL); - - /* store xferCFG */ - *xfercfg_addr = xfer; -} - -/*! - * brief setup dma descriptor - * Note: This function do not support configure wrap descriptor. - * param desc DMA descriptor address. - * param xfercfg Transfer configuration for DMA descriptor. - * param srcStartAddr Start address of source address. - * param dstStartAddr Start address of destination address. - * param nextDesc Address of next descriptor in chain. - */ -void DMA_SetupDescriptor( - dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) -{ - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - -#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) - srcStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)srcStartAddr, kMEMORY_Local2DMA); - dstStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)dstStartAddr, kMEMORY_Local2DMA); - nextDesc = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)nextDesc, kMEMORY_Local2DMA); -#endif - - uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; - - width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT; - srcInc = (xfercfg & DMA_CHANNEL_XFERCFG_SRCINC_MASK) >> DMA_CHANNEL_XFERCFG_SRCINC_SHIFT; - dstInc = (xfercfg & DMA_CHANNEL_XFERCFG_DSTINC_MASK) >> DMA_CHANNEL_XFERCFG_DSTINC_SHIFT; - transferCount = ((xfercfg & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1U; - - /* covert register value to actual value */ - if (width == 2U) - { - width = kDMA_Transfer32BitWidth; - } - else - { - width += 1U; - } - - /* - * Transfers of 16 bit width require an address alignment to a multiple of 2 bytes. - * Transfers of 32 bit width require an address alignment to a multiple of 4 bytes. - * Transfers of 8 bit width can be at any address - */ - if (((NULL != srcStartAddr) && (0UL == ((uint32_t)(uint32_t *)srcStartAddr) % width)) && - ((NULL != dstStartAddr) && (0UL == ((uint32_t)(uint32_t *)dstStartAddr) % width))) - { - if (srcInc == 3U) - { - srcInc = kDMA_AddressInterleave4xWidth; - } - - if (dstInc == 3U) - { - dstInc = kDMA_AddressInterleave4xWidth; - } - - desc->xfercfg = xfercfg; - desc->srcEndAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); - desc->dstEndAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); - desc->linkToNextDesc = nextDesc; - } - else - { - /* if address alignment not satisfy the requirement, reset the descriptor to make sure DMA generate error */ - desc->xfercfg = 0U; - desc->srcEndAddr = NULL; - desc->dstEndAddr = NULL; - } -} - -/*! - * brief setup dma channel descriptor - * Note: This function support configure wrap descriptor. - * param desc DMA descriptor address. - * param xfercfg Transfer configuration for DMA descriptor. - * param srcStartAddr Start address of source address. - * param dstStartAddr Start address of destination address. - * param nextDesc Address of next descriptor in chain. - * param wrapType burst wrap type. - * param burstSize burst size, reference _dma_burst_size. - */ -void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, - uint32_t xfercfg, - void *srcStartAddr, - void *dstStartAddr, - void *nextDesc, - dma_burst_wrap_t wrapType, - uint32_t burstSize) -{ - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - -#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) - srcStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)srcStartAddr, kMEMORY_Local2DMA); - dstStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)dstStartAddr, kMEMORY_Local2DMA); - nextDesc = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)nextDesc, kMEMORY_Local2DMA); -#endif - - uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; - - width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT; - srcInc = (xfercfg & DMA_CHANNEL_XFERCFG_SRCINC_MASK) >> DMA_CHANNEL_XFERCFG_SRCINC_SHIFT; - dstInc = (xfercfg & DMA_CHANNEL_XFERCFG_DSTINC_MASK) >> DMA_CHANNEL_XFERCFG_DSTINC_SHIFT; - transferCount = ((xfercfg & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1U; - - /* covert register value to actual value */ - if (width == 2U) - { - width = kDMA_Transfer32BitWidth; - } - else - { - width += 1U; - } - - /* - * Transfers of 16 bit width require an address alignment to a multiple of 2 bytes. - * Transfers of 32 bit width require an address alignment to a multiple of 4 bytes. - * Transfers of 8 bit width can be at any address - */ - if (((NULL != srcStartAddr) && (0UL == ((uint32_t)(uint32_t *)srcStartAddr) % width)) && - ((NULL != dstStartAddr) && (0UL == ((uint32_t)(uint32_t *)dstStartAddr) % width))) - { - if (srcInc == 3U) - { - srcInc = kDMA_AddressInterleave4xWidth; - } - - if (dstInc == 3U) - { - dstInc = kDMA_AddressInterleave4xWidth; - } - - desc->xfercfg = xfercfg; - - if (wrapType == kDMA_NoWrap) - { - desc->srcEndAddr = - DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); - desc->dstEndAddr = - DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); - } - /* for the wrap transfer, the destination address should be determined by the burstSize/width/interleave size */ - if (wrapType == kDMA_SrcWrap) - { - desc->srcEndAddr = - (uint32_t *)((uint32_t)(uint32_t *)srcStartAddr + ((1UL << burstSize) - 1UL) * width * srcInc); - desc->dstEndAddr = - DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); - } - if (wrapType == kDMA_DstWrap) - { - desc->srcEndAddr = - DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); - desc->dstEndAddr = - (uint32_t *)((uint32_t)(uint32_t *)dstStartAddr + ((1UL << burstSize) - 1UL) * width * dstInc); - } - if (wrapType == kDMA_SrcAndDstWrap) - { - desc->srcEndAddr = - (uint32_t *)(((uint32_t)(uint32_t *)srcStartAddr) + ((1UL << burstSize) - 1UL) * width * srcInc); - desc->dstEndAddr = - (uint32_t *)(((uint32_t)(uint32_t *)dstStartAddr) + ((1UL << burstSize) - 1UL) * width * dstInc); - } - - desc->linkToNextDesc = nextDesc; - } - else - { - /* if address alignment not satisfy the requirement, reset the descriptor to make sure DMA generate error */ - desc->xfercfg = 0U; - desc->srcEndAddr = NULL; - desc->dstEndAddr = NULL; - } -} - -/*! - * brief Create application specific DMA descriptor - * to be used in a chain in transfer - * deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor - * param desc DMA descriptor address. - * param xfercfg Transfer configuration for DMA descriptor. - * param srcAddr Address of last item to transmit - * param dstAddr Address of last item to receive. - * param nextDesc Address of next descriptor in chain. - */ -void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc) -{ - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - assert((NULL != srcAddr) && (0UL == ((uint32_t)(uint32_t *)srcAddr) % xfercfg->byteWidth)); - assert((NULL != dstAddr) && (0UL == ((uint32_t)(uint32_t *)dstAddr) % xfercfg->byteWidth)); - - uint32_t xfercfg_reg = 0; - - DMA_SetupXferCFG(xfercfg, &xfercfg_reg); - - /* Set descriptor structure */ - DMA_SetupDescriptor(desc, xfercfg_reg, srcAddr, dstAddr, nextDesc); -} - -/*! - * brief Abort running transfer by handle. - * - * This function aborts DMA transfer specified by handle. - * - * param handle DMA handle pointer. - */ -void DMA_AbortTransfer(dma_handle_t *handle) -{ - assert(NULL != handle); - - DMA_DisableChannel(handle->base, handle->channel); - while ((DMA_COMMON_CONST_REG_GET(handle->base, handle->channel, BUSY) & - (1UL << DMA_CHANNEL_INDEX(handle->base, handle->channel))) != 0UL) - { - } - DMA_COMMON_REG_GET(handle->base, handle->channel, ABORT) |= 1UL << DMA_CHANNEL_INDEX(handle->base, handle->channel); - DMA_EnableChannel(handle->base, handle->channel); -} - -/*! - * brief Creates the DMA handle. - * - * This function is called if using transaction API for DMA. This function - * initializes the internal state of DMA handle. - * - * param handle DMA handle pointer. The DMA handle stores callback function and - * parameters. - * param base DMA peripheral base address. - * param channel DMA channel number. - */ -void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel) -{ - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); - assert((NULL != handle) && (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - - uint32_t dmaInstance; - uint32_t startChannel = 0; - /* base address is invalid DMA instance */ - dmaInstance = DMA_GetInstance(base); - startChannel = DMA_GetVirtualStartChannel(base); - - (void)memset(handle, 0, sizeof(*handle)); - handle->base = base; - handle->channel = (uint8_t)channel; - s_DMAHandle[startChannel + channel] = handle; - /* Enable NVIC interrupt */ - (void)EnableIRQ(s_dmaIRQNumber[dmaInstance]); - /* Enable channel interrupt */ - DMA_EnableChannelInterrupts(handle->base, channel); -} - -/*! - * brief Installs a callback function for the DMA transfer. - * - * This callback is called in DMA IRQ handler. Use the callback to do something after - * the current major loop transfer completes. - * - * param handle DMA handle pointer. - * param callback DMA callback function pointer. - * param userData Parameter for callback function. - */ -void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData) -{ - assert(handle != NULL); - - handle->callback = callback; - handle->userData = userData; -} - -/*! - * brief Prepares the DMA transfer structure. - * deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer and - * DMA_PrepareChannelXfer. - * This function prepares the transfer configuration structure according to the user input. - * - * param config The user configuration structure of type dma_transfer_t. - * param srcAddr DMA transfer source address. - * param dstAddr DMA transfer destination address. - * param byteWidth DMA transfer destination address width(bytes). - * param transferBytes DMA transfer bytes to be transferred. - * param type DMA transfer type. - * param nextDesc Chain custom descriptor to transfer. - * note The data address and the data width must be consistent. For example, if the SRC - * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in - * source address error(SAE). - */ -void DMA_PrepareTransfer(dma_transfer_config_t *config, - void *srcAddr, - void *dstAddr, - uint32_t byteWidth, - uint32_t transferBytes, - dma_transfer_type_t type, - void *nextDesc) -{ - uint32_t xfer_count; - assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr)); - assert((byteWidth == 1UL) || (byteWidth == 2UL) || (byteWidth == 4UL)); - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - - /* check max */ - xfer_count = transferBytes / byteWidth; - assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0UL == transferBytes % byteWidth)); - - (void)memset(config, 0, sizeof(*config)); - - if (type == kDMA_MemoryToMemory) - { - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 1; - config->isPeriph = false; - } - - else if (type == kDMA_PeripheralToMemory) - { - /* Peripheral register - source doesn't increment */ - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 1; - config->isPeriph = true; - } - else if (type == kDMA_MemoryToPeripheral) - { - /* Peripheral register - destination doesn't increment */ - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - } - /* kDMA_StaticToStatic */ - else - { - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - } - - config->dstAddr = (uint8_t *)dstAddr; - config->srcAddr = (uint8_t *)srcAddr; - config->nextDesc = (uint8_t *)nextDesc; - config->xfercfg.transferCount = (uint16_t)xfer_count; - config->xfercfg.byteWidth = (uint8_t)byteWidth; - config->xfercfg.intA = true; - config->xfercfg.reload = nextDesc != NULL; - config->xfercfg.valid = true; -} - -/*! - * brief set channel config. - * - * This function provide a interface to configure channel configuration reisters. - * - * param base DMA base address. - * param channel DMA channel number. - * param config channel configurations structure. - */ -void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph) -{ - assert(channel < (uint32_t)FSL_FEATURE_DMA_MAX_CHANNELS); - - uint32_t tmpReg = DMA_CHANNEL_CFG_PERIPHREQEN_MASK; - - if (trigger != NULL) - { - tmpReg |= DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | - DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | - DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK; - } - - tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); - - if (trigger != NULL) - { - tmpReg |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); - } - - tmpReg |= DMA_CHANNEL_CFG_PERIPHREQEN(isPeriph); - - base->CHANNEL[channel].CFG = tmpReg; -} - -/*! - * brief Prepare channel transfer configurations. - * - * This function used to prepare channel transfer configurations. - * - * param config Pointer to DMA channel transfer configuration structure. - * param srcStartAddr source start address. - * param dstStartAddr destination start address. - * param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * param type transfer type. - * param trigger DMA channel trigger configurations. - * param nextDesc address of next descriptor. - */ -void DMA_PrepareChannelTransfer(dma_channel_config_t *config, - void *srcStartAddr, - void *dstStartAddr, - uint32_t xferCfg, - dma_transfer_type_t type, - dma_channel_trigger_t *trigger, - void *nextDesc) -{ - assert((NULL != config) && (NULL != srcStartAddr) && (NULL != dstStartAddr)); - assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); - - /* check max */ - (void)memset(config, 0, sizeof(*config)); - - if (type == kDMA_MemoryToMemory) - { - config->isPeriph = false; - } - else if (type == kDMA_PeripheralToMemory) - { - config->isPeriph = true; - } - else if (type == kDMA_MemoryToPeripheral) - { - config->isPeriph = true; - } - /* kDMA_StaticToStatic */ - else - { - config->isPeriph = true; - } - - config->dstStartAddr = (uint8_t *)dstStartAddr; - config->srcStartAddr = (uint8_t *)srcStartAddr; - config->nextDesc = (uint8_t *)nextDesc; - config->trigger = trigger; - config->xferCfg = xferCfg; -} - -/*! - * brief load channel transfer decriptor. - * - * This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA - * transfer, the head descriptor table is defined in DMA driver, it is useful for the case: - * 1. for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly - * and then call this api to load the configured descriptor to driver descriptor table. code DMA_Init(DMA0); - * DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL); - * DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL); - * DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc); - * DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL); - * while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL)) - * {} - * endcode - * - * param base DMA base address. - * param channel DMA channel. - * param descriptor configured DMA descriptor. - */ -void DMA_LoadChannelDescriptor(DMA_Type *base, uint32_t channel, dma_descriptor_t *descriptor) -{ - assert(NULL != descriptor); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); - assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - - uint32_t instance = DMA_GetInstance(base); - dma_descriptor_t *channelDescriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][channel]); - - channelDescriptor->xfercfg = descriptor->xfercfg; - channelDescriptor->srcEndAddr = descriptor->srcEndAddr; - channelDescriptor->dstEndAddr = descriptor->dstEndAddr; - channelDescriptor->linkToNextDesc = descriptor->linkToNextDesc; - - /* Set channel XFERCFG register according first channel descriptor. */ - base->CHANNEL[channel].XFERCFG = descriptor->xfercfg; -} - -/*! - * brief Install DMA descriptor memory. - * - * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong - * transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has - * a default DMA descriptor buffer, but it support one DMA descriptor for one channel only. - * User should be take care about the address of DMA descriptor pool which required align with 512BYTE. - * - * param handle Pointer to DMA channel transfer handle. - * param addr DMA descriptor address - * param num DMA descriptor number. - */ -void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr) -{ - assert(addr != NULL); - -#if defined FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn - assert((((uint32_t)(uint32_t *)addr) & ((uint32_t)FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn(base) - 1UL)) == 0U); -#else - assert((((uint32_t)(uint32_t *)addr) & ((uint32_t)FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0U); -#endif - /* reconfigure the DMA descriptor base address */ - base->SRAMBASE = (uint32_t)(uint32_t *)addr; -} - -/*! - * brief Submit channel transfer paramter directly. - * - * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table - * is defined in DMA driver, it is useful for the case: - * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used - for it. - * code - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, - bytes), srcStartAddr, dstStartAddr, NULL); - DMA_StartTransfer(handle) - * endcode - * - * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is - required, then application should prepare - * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc2); - DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, NULL); - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, - bytes), srcStartAddr, dstStartAddr, nextDesc0); - DMA_StartTransfer(handle); - * endcode - * - * param handle Pointer to DMA handle. - * param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * param srcStartAddr source start address. - * param dstStartAddr destination start address. - * param nextDesc address of next descriptor. - */ -void DMA_SubmitChannelTransferParameter( - dma_handle_t *handle, uint32_t xferCfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) -{ - assert((NULL != srcStartAddr) && (NULL != dstStartAddr)); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); - assert(handle->channel < (uint8_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - - uint32_t instance = DMA_GetInstance(handle->base); - dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); - - DMA_SetupDescriptor(descriptor, xferCfg, srcStartAddr, dstStartAddr, nextDesc); - - /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = xferCfg; -} - -/*! - * brief Submit channel descriptor. - * - * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table - is defined in - * DMA driver, this functiono is typical for the ping pong case: - * - * 1. for the ping pong case, application should responsible for the descriptor, for example, application should - * prepare two descriptor table with macro. - * code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc0); - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelDescriptor(handle, nextDesc0); - DMA_StartTransfer(handle); - * endcode - * - * param handle Pointer to DMA handle. - * param descriptor descriptor to submit. - */ -void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descriptor) -{ - assert((NULL != handle) && (NULL != descriptor)); - - DMA_LoadChannelDescriptor(handle->base, handle->channel, descriptor); -} - -/*! - * brief Submits the DMA channel transfer request. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * It is used for the case: - * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used - for it. - * code - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,NULL); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * endcode - * - * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is - required, then application should prepare - * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc2); - DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, NULL); - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * endcode - * - * 3. for the ping pong case, application should responsible for link descriptor, for example, application should - prepare - * two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc0); - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * endcode - * param handle DMA handle pointer. - * param config Pointer to DMA transfer configuration structure. - * retval kStatus_DMA_Success It means submit transfer request succeed. - * retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config) -{ - assert((NULL != handle) && (NULL != config)); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); - assert(handle->channel < (uint8_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - uint32_t instance = DMA_GetInstance(handle->base); - dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); - - /* Previous transfer has not finished */ - if (DMA_ChannelIsActive(handle->base, handle->channel)) - { - return kStatus_DMA_Busy; - } - - /* setup channgel trigger configurations */ - DMA_SetChannelConfig(handle->base, handle->channel, config->trigger, config->isPeriph); - - DMA_SetupChannelDescriptor( - descriptor, config->xferCfg, config->srcStartAddr, config->dstStartAddr, config->nextDesc, - config->trigger == NULL ? kDMA_NoWrap : config->trigger->wrap, - (config->trigger == NULL ? (uint32_t)kDMA_BurstSize1 : - ((uint32_t)config->trigger->burst & (DMA_CHANNEL_CFG_BURSTPOWER_MASK)) >> - DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)); - - /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = config->xferCfg; - - return kStatus_Success; -} - -/*! - * brief Submits the DMA transfer request. - * deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * - * param handle DMA handle pointer. - * param config Pointer to DMA transfer configuration structure. - * retval kStatus_DMA_Success It means submit transfer request succeed. - * retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) -{ - assert((NULL != handle) && (NULL != config)); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); - assert(handle->channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - - uint32_t instance = DMA_GetInstance(handle->base); - dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); - - /* Previous transfer has not finished */ - if (DMA_ChannelIsActive(handle->base, handle->channel)) - { - return kStatus_DMA_Busy; - } - - /* enable/disable peripheral request */ - if (config->isPeriph) - { - DMA_EnableChannelPeriphRq(handle->base, handle->channel); - } - else - { - DMA_DisableChannelPeriphRq(handle->base, handle->channel); - } - - DMA_CreateDescriptor(descriptor, &config->xfercfg, config->srcAddr, config->dstAddr, config->nextDesc); - /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = descriptor->xfercfg; - - return kStatus_Success; -} - -/*! - * brief DMA start transfer. - * - * This function enables the channel request. User can call this function after submitting the transfer request - * It will trigger transfer start with software trigger only when hardware trigger is not used. - * - * param handle DMA handle pointer. - */ -void DMA_StartTransfer(dma_handle_t *handle) -{ - assert(NULL != handle); - assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); - - uint32_t channel = handle->channel; - assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - - /* enable channel */ - DMA_EnableChannel(handle->base, channel); - - /* Do software trigger only when HW trigger is not enabled. */ - if ((handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK) == 0U) - { - handle->base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; - } -} - -void DMA_IRQHandle(DMA_Type *base) -{ - dma_handle_t *handle; - uint8_t channel_index; - uint32_t startChannel = DMA_GetVirtualStartChannel(base); - uint32_t i = 0; - bool intEnabled = false, intA = false, intB = false; - - /* Find channels that have completed transfer */ - for (i = 0; i < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base); i++) - { - handle = s_DMAHandle[i + startChannel]; - /* Handle is not present */ - if (NULL == handle) - { - continue; - } - channel_index = DMA_CHANNEL_INDEX(base, handle->channel); - /* Channel uses INTA flag */ - intEnabled = ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTENSET) & (1UL << channel_index)) != 0UL); - intA = ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTA) & (1UL << channel_index)) != 0UL); - if (intEnabled && intA) - { - /* Clear INTA flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, INTA, (1UL << channel_index)); - if (handle->callback != NULL) - { - (handle->callback)(handle, handle->userData, true, kDMA_IntA); - } - } - - intB = ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTB) & (1UL << channel_index)) != 0UL); - /* Channel uses INTB flag */ - if (intEnabled && intB) - { - /* Clear INTB flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, INTB, (1UL << channel_index)); - if (handle->callback != NULL) - { - (handle->callback)(handle, handle->userData, true, kDMA_IntB); - } - } - /* Error flag */ - if ((DMA_COMMON_REG_GET(handle->base, handle->channel, ERRINT) & (1UL << channel_index)) != 0UL) - { - /* Clear error flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, ERRINT, (1UL << channel_index)); - if (handle->callback != NULL) - { - (handle->callback)(handle, handle->userData, false, kDMA_IntError); - } - } - } -} - -void DMA0_DriverIRQHandler(void); -void DMA0_DriverIRQHandler(void) -{ - DMA_IRQHandle(DMA0); - SDK_ISR_EXIT_BARRIER; -} - -#if defined(DMA1) -void DMA1_DriverIRQHandler(void); -void DMA1_DriverIRQHandler(void) -{ - DMA_IRQHandle(DMA1); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.h deleted file mode 100644 index 0e857752e58..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.h +++ /dev/null @@ -1,892 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_DMA_H_ -#define _FSL_DMA_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup dma - * @{ - */ - -/*! @file */ -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief DMA driver version */ -#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 4)) /*!< Version 2.4.4. */ -/*@}*/ - -/*! @brief DMA max transfer size */ -#define DMA_MAX_TRANSFER_COUNT 0x400U -/*! @brief DMA channel numbers */ -#if defined FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_MAX_CHANNELS FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_ALL_CHANNELS (FSL_FEATURE_DMA_NUMBER_OF_CHANNELS * FSL_FEATURE_SOC_DMA_COUNT) -#endif -/*! @brief DMA head link descriptor table align size */ -#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) -/*! @brief DMA head descriptor table allocate macro - * To simplify user interface, this macro will help allocate descriptor memory, - * user just need to provide the name and the number for the allocate descriptor. - * - * @param name Allocate decriptor name. - * @param number Number of descriptor to be allocated. - */ -#define DMA_ALLOCATE_HEAD_DESCRIPTORS(name, number) \ - SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE) -/*! @brief DMA head descriptor table allocate macro at noncacheable section - * To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, - * user just need to provide the name and the number for the allocate descriptor. - * - * @param name Allocate decriptor name. - * @param number Number of descriptor to be allocated. - */ -#define DMA_ALLOCATE_HEAD_DESCRIPTORS_AT_NONCACHEABLE(name, number) \ - AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE) -/*! @brief DMA link descriptor table allocate macro - * To simplify user interface, this macro will help allocate descriptor memory, - * user just need to provide the name and the number for the allocate descriptor. - * - * @param name Allocate decriptor name. - * @param number Number of descriptor to be allocated. - */ -#define DMA_ALLOCATE_LINK_DESCRIPTORS(name, number) \ - SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE) -/*! @brief DMA link descriptor table allocate macro at noncacheable section - * To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, - * user just need to provide the name and the number for the allocate descriptor. - * - * @param name Allocate decriptor name. - * @param number Number of descriptor to be allocated. - */ -#define DMA_ALLOCATE_LINK_DESCRIPTORS_AT_NONCACHEABLE(name, number) \ - AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE) -/*! @brief DMA transfer buffer address need to align with the transfer width */ -#define DMA_ALLOCATE_DATA_TRANSFER_BUFFER(name, width) SDK_ALIGN(name, width) -/* Channel group consists of 32 channels. channel_group = 0 */ -#define DMA_CHANNEL_GROUP(channel) (((uint8_t)(channel)) >> 5U) -/* Channel index in channel group. channel_index = (channel % (channel number per instance)) */ -#define DMA_CHANNEL_INDEX(base, channel) (((uint8_t)(channel)) & 0x1FU) -/*! @brief DMA linked descriptor address algin size */ -#define DMA_COMMON_REG_GET(base, channel, reg) \ - (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) -#define DMA_COMMON_CONST_REG_GET(base, channel, reg) \ - (((volatile const uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) -#define DMA_COMMON_REG_SET(base, channel, reg, value) \ - (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)] = (value)) - -/*! @brief DMA descriptor end address calculate - * @param start start address - * @param inc address interleave size - * @param bytes transfer bytes - * @param width transfer width - */ -#define DMA_DESCRIPTOR_END_ADDRESS(start, inc, bytes, width) \ - ((uint32_t *)((uint32_t)(start) + (inc) * (bytes) - (inc) * (width))) - -/*! @brief DMA channel transfer configurations macro - * @param reload true is reload link descriptor after current exhaust, false is not - * @param clrTrig true is clear trigger status, wait software trigger, false is not - * @param intA enable interruptA - * @param intB enable interruptB - * @param width transfer width - * @param srcInc source address interleave size - * @param dstInc destination address interleave size - * @param bytes transfer bytes - */ -#define DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes) \ - DMA_CHANNEL_XFERCFG_CFGVALID_MASK | DMA_CHANNEL_XFERCFG_RELOAD(reload) | DMA_CHANNEL_XFERCFG_CLRTRIG(clrTrig) | \ - DMA_CHANNEL_XFERCFG_SETINTA(intA) | DMA_CHANNEL_XFERCFG_SETINTB(intB) | \ - DMA_CHANNEL_XFERCFG_WIDTH(width == 4UL ? 2UL : (width - 1UL)) | \ - DMA_CHANNEL_XFERCFG_SRCINC(srcInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (srcInc - 1UL) : srcInc) | \ - DMA_CHANNEL_XFERCFG_DSTINC(dstInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (dstInc - 1UL) : dstInc) | \ - DMA_CHANNEL_XFERCFG_XFERCOUNT(bytes / width - 1UL) - -/*! @brief _dma_transfer_status DMA transfer status */ -enum -{ - kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the - transfer request. */ -}; - -/*! @brief _dma_addr_interleave_size dma address interleave size */ -enum -{ - kDMA_AddressInterleave0xWidth = 0U, /*!< dma source/destination address no interleave */ - kDMA_AddressInterleave1xWidth = 1U, /*!< dma source/destination address interleave 1xwidth */ - kDMA_AddressInterleave2xWidth = 2U, /*!< dma source/destination address interleave 2xwidth */ - kDMA_AddressInterleave4xWidth = 4U, /*!< dma source/destination address interleave 3xwidth */ -}; - -/*! @brief _dma_transfer_width dma transfer width */ -enum -{ - kDMA_Transfer8BitWidth = 1U, /*!< dma channel transfer bit width is 8 bit */ - kDMA_Transfer16BitWidth = 2U, /*!< dma channel transfer bit width is 16 bit */ - kDMA_Transfer32BitWidth = 4U, /*!< dma channel transfer bit width is 32 bit */ -}; - -/*! @brief DMA descriptor structure */ -typedef struct _dma_descriptor -{ - volatile uint32_t xfercfg; /*!< Transfer configuration */ - void *srcEndAddr; /*!< Last source address of DMA transfer */ - void *dstEndAddr; /*!< Last destination address of DMA transfer */ - void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */ -} dma_descriptor_t; - -/*! @brief DMA transfer configuration */ -typedef struct _dma_xfercfg -{ - bool valid; /*!< Descriptor is ready to transfer */ - bool reload; /*!< Reload channel configuration register after - current descriptor is exhausted */ - bool swtrig; /*!< Perform software trigger. Transfer if fired - when 'valid' is set */ - bool clrtrig; /*!< Clear trigger */ - bool intA; /*!< Raises IRQ when transfer is done and set IRQA status register flag */ - bool intB; /*!< Raises IRQ when transfer is done and set IRQB status register flag */ - uint8_t byteWidth; /*!< Byte width of data to transfer */ - uint8_t srcInc; /*!< Increment source address by 'srcInc' x 'byteWidth' */ - uint8_t dstInc; /*!< Increment destination address by 'dstInc' x 'byteWidth' */ - uint16_t transferCount; /*!< Number of transfers */ -} dma_xfercfg_t; - -/*! @brief DMA channel priority */ -typedef enum _dma_priority -{ - kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */ - kDMA_ChannelPriority1, /*!< Channel priority 1 */ - kDMA_ChannelPriority2, /*!< Channel priority 2 */ - kDMA_ChannelPriority3, /*!< Channel priority 3 */ - kDMA_ChannelPriority4, /*!< Channel priority 4 */ - kDMA_ChannelPriority5, /*!< Channel priority 5 */ - kDMA_ChannelPriority6, /*!< Channel priority 6 */ - kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */ -} dma_priority_t; - -/*! @brief DMA interrupt flags */ -typedef enum _dma_int -{ - kDMA_IntA, /*!< DMA interrupt flag A */ - kDMA_IntB, /*!< DMA interrupt flag B */ - kDMA_IntError, /*!< DMA interrupt flag error */ -} dma_irq_t; - -/*! @brief DMA trigger type*/ -typedef enum _dma_trigger_type -{ - kDMA_NoTrigger = 0, /*!< Trigger is disabled */ - kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */ - kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | - DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */ - kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */ - kDMA_RisingEdgeTrigger = - DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */ -} dma_trigger_type_t; - -/*! @brief _dma_burst_size DMA burst size*/ -enum -{ - kDMA_BurstSize1 = 0U, /*!< burst size 1 transfer */ - kDMA_BurstSize2 = 1U, /*!< burst size 2 transfer */ - kDMA_BurstSize4 = 2U, /*!< burst size 4 transfer */ - kDMA_BurstSize8 = 3U, /*!< burst size 8 transfer */ - kDMA_BurstSize16 = 4U, /*!< burst size 16 transfer */ - kDMA_BurstSize32 = 5U, /*!< burst size 32 transfer */ - kDMA_BurstSize64 = 6U, /*!< burst size 64 transfer */ - kDMA_BurstSize128 = 7U, /*!< burst size 128 transfer */ - kDMA_BurstSize256 = 8U, /*!< burst size 256 transfer */ - kDMA_BurstSize512 = 9U, /*!< burst size 512 transfer */ - kDMA_BurstSize1024 = 10U, /*!< burst size 1024 transfer */ -}; - -/*! @brief DMA trigger burst */ -typedef enum _dma_trigger_burst -{ - kDMA_SingleTransfer = 0, /*!< Single transfer */ - kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */ - kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */ - kDMA_EdgeBurstTransfer2 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */ - kDMA_EdgeBurstTransfer4 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */ - kDMA_EdgeBurstTransfer8 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */ - kDMA_EdgeBurstTransfer16 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */ - kDMA_EdgeBurstTransfer32 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */ - kDMA_EdgeBurstTransfer64 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */ - kDMA_EdgeBurstTransfer128 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */ - kDMA_EdgeBurstTransfer256 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */ - kDMA_EdgeBurstTransfer512 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */ - kDMA_EdgeBurstTransfer1024 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */ -} dma_trigger_burst_t; - -/*! @brief DMA burst wrapping */ -typedef enum _dma_burst_wrap -{ - kDMA_NoWrap = 0, /*!< Wrapping is disabled */ - kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */ - kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */ - kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | - DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */ -} dma_burst_wrap_t; - -/*! @brief DMA transfer type */ -typedef enum _dma_transfer_type -{ - kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */ - kDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory (increment only destination) */ - kDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral (increment only source)*/ - kDMA_StaticToStatic, /*!< Peripheral to static memory (do not increment source or destination) */ -} dma_transfer_type_t; - -/*! @brief DMA channel trigger */ -typedef struct _dma_channel_trigger -{ - dma_trigger_type_t type; /*!< Select hardware trigger as edge triggered or level triggered. */ - dma_trigger_burst_t burst; /*!< Select whether hardware triggers cause a single or burst transfer. */ - dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */ -} dma_channel_trigger_t; - -/*! @brief DMA channel trigger */ -typedef struct _dma_channel_config -{ - void *srcStartAddr; /*!< Source data address */ - void *dstStartAddr; /*!< Destination data address */ - void *nextDesc; /*!< Chain custom descriptor */ - uint32_t xferCfg; /*!< channel transfer configurations */ - dma_channel_trigger_t *trigger; /*!< DMA trigger type */ - bool isPeriph; /*!< select the request type */ -} dma_channel_config_t; - -/*! @brief DMA transfer configuration */ -typedef struct _dma_transfer_config -{ - uint8_t *srcAddr; /*!< Source data address */ - uint8_t *dstAddr; /*!< Destination data address */ - uint8_t *nextDesc; /*!< Chain custom descriptor */ - dma_xfercfg_t xfercfg; /*!< Transfer options */ - bool isPeriph; /*!< DMA transfer is driven by peripheral */ -} dma_transfer_config_t; - -/*! @brief Callback for DMA */ -struct _dma_handle; - -/*! @brief Define Callback function for DMA. */ -typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode); - -/*! @brief DMA transfer handle structure */ -typedef struct _dma_handle -{ - dma_callback callback; /*!< Callback function. Invoked when transfer - of descriptor with interrupt flag finishes */ - void *userData; /*!< Callback function parameter */ - DMA_Type *base; /*!< DMA peripheral base address */ - uint8_t channel; /*!< DMA channel number */ -} dma_handle_t; - -/******************************************************************************* - * APIs - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name DMA initialization and De-initialization - * @{ - */ - -/*! - * @brief Initializes DMA peripheral. - * - * This function enable the DMA clock, set descriptor table and - * enable DMA peripheral. - * - * @param base DMA peripheral base address. - */ -void DMA_Init(DMA_Type *base); - -/*! - * @brief Deinitializes DMA peripheral. - * - * This function gates the DMA clock. - * - * @param base DMA peripheral base address. - */ -void DMA_Deinit(DMA_Type *base); - -/*! - * @brief Install DMA descriptor memory. - * - * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong - * transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has - * a default DMA descriptor buffer, but it support one DMA descriptor for one channel only. - * - * @param base DMA base address. - * @param addr DMA descriptor address - */ -void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr); - -/* @} */ - -/*! - * @name DMA Channel Operation - * @{ - */ - -/*! - * @brief Return whether DMA channel is processing transfer - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return True for active state, false otherwise. - */ -static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - - return (DMA_COMMON_CONST_REG_GET(base, channel, ACTIVE) & (1UL << DMA_CHANNEL_INDEX(base, channel))) != 0UL; -} - -/*! - * @brief Return whether DMA channel is busy - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return True for busy state, false otherwise. - */ -static inline bool DMA_ChannelIsBusy(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - - return (DMA_COMMON_CONST_REG_GET(base, channel, BUSY) & (1UL << DMA_CHANNEL_INDEX(base, channel))) != 0UL; -} - -/*! - * @brief Enables the interrupt source for the DMA transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - DMA_COMMON_REG_GET(base, channel, INTENSET) |= 1UL << DMA_CHANNEL_INDEX(base, channel); -} - -/*! - * @brief Disables the interrupt source for the DMA transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - DMA_COMMON_REG_GET(base, channel, INTENCLR) |= 1UL << DMA_CHANNEL_INDEX(base, channel); -} - -/*! - * @brief Enable DMA channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - DMA_COMMON_REG_GET(base, channel, ENABLESET) |= 1UL << DMA_CHANNEL_INDEX(base, channel); -} - -/*! - * @brief Disable DMA channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - DMA_COMMON_REG_GET(base, channel, ENABLECLR) |= 1UL << DMA_CHANNEL_INDEX(base, channel); -} - -/*! - * @brief Set PERIPHREQEN of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK; -} - -/*! - * @brief Get PERIPHREQEN value of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return True for enabled PeriphRq, false for disabled. - */ -static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK; -} - -/*! - * @brief Set trigger settings of DMA channel. - * @deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param trigger trigger configuration. - */ -void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger); - -/*! - * @brief set channel config. - * - * This function provide a interface to configure channel configuration reisters. - * - * @param base DMA base address. - * @param channel DMA channel number. - * @param trigger channel configurations structure. - * @param isPeriph true is periph request, false is not. - */ -void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph); - -/*! - * @brief Gets the remaining bytes of the current DMA descriptor transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return The number of bytes which have not been transferred yet. - */ -uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel); - -/*! - * @brief Set priority of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param priority Channel priority value. - */ -static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - base->CHANNEL[channel].CFG = - (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority); -} - -/*! - * @brief Get priority of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return Channel priority value. - */ -static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel) -{ - assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && - (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - return (dma_priority_t)(uint8_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> - DMA_CHANNEL_CFG_CHPRIORITY_SHIFT); -} - -/*! - * @brief Set channel configuration valid. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_SetChannelConfigValid(DMA_Type *base, uint32_t channel) -{ - base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_CFGVALID_MASK; -} - -/*! - * @brief Do software trigger for the channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DoChannelSoftwareTrigger(DMA_Type *base, uint32_t channel) -{ - base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; -} - -/*! - * @brief Load channel transfer configurations. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param xfer transfer configurations. - */ -static inline void DMA_LoadChannelTransferConfig(DMA_Type *base, uint32_t channel, uint32_t xfer) -{ - base->CHANNEL[channel].XFERCFG = xfer; -} - -/*! - * @brief Create application specific DMA descriptor - * to be used in a chain in transfer - * @deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor. - * @param desc DMA descriptor address. - * @param xfercfg Transfer configuration for DMA descriptor. - * @param srcAddr Address of last item to transmit - * @param dstAddr Address of last item to receive. - * @param nextDesc Address of next descriptor in chain. - */ -void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc); - -/*! - * @brief setup dma descriptor - * - * Note: This function do not support configure wrap descriptor. - * - * @param desc DMA descriptor address. - * @param xfercfg Transfer configuration for DMA descriptor. - * @param srcStartAddr Start address of source address. - * @param dstStartAddr Start address of destination address. - * @param nextDesc Address of next descriptor in chain. - */ -void DMA_SetupDescriptor( - dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc); - -/*! - * @brief setup dma channel descriptor - * - * Note: This function support configure wrap descriptor. - * - * @param desc DMA descriptor address. - * @param xfercfg Transfer configuration for DMA descriptor. - * @param srcStartAddr Start address of source address. - * @param dstStartAddr Start address of destination address. - * @param nextDesc Address of next descriptor in chain. - * @param wrapType burst wrap type. - * @param burstSize burst size, reference _dma_burst_size. - */ -void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, - uint32_t xfercfg, - void *srcStartAddr, - void *dstStartAddr, - void *nextDesc, - dma_burst_wrap_t wrapType, - uint32_t burstSize); - -/*! - * @brief load channel transfer decriptor. - * - * This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA - * transfer, the head descriptor table is defined in DMA driver, it is useful for the case: - * 1. for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly - * and then call this api to load the configured descriptor to driver descriptor table. - * @code - * DMA_Init(DMA0); - * DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL); - * DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL); - * DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc); - * DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL); - * while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL)) - * {} - * @endcode - * - * @param base DMA base address. - * @param channel DMA channel. - * @param descriptor configured DMA descriptor. - */ -void DMA_LoadChannelDescriptor(DMA_Type *base, uint32_t channel, dma_descriptor_t *descriptor); - -/* @} */ - -/*! - * @name DMA Transactional Operation - * @{ - */ - -/*! - * @brief Abort running transfer by handle. - * - * This function aborts DMA transfer specified by handle. - * - * @param handle DMA handle pointer. - */ -void DMA_AbortTransfer(dma_handle_t *handle); - -/*! - * @brief Creates the DMA handle. - * - * This function is called if using transaction API for DMA. This function - * initializes the internal state of DMA handle. - * - * @param handle DMA handle pointer. The DMA handle stores callback function and - * parameters. - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel); - -/*! - * @brief Installs a callback function for the DMA transfer. - * - * This callback is called in DMA IRQ handler. Use the callback to do something after - * the current major loop transfer completes. - * - * @param handle DMA handle pointer. - * @param callback DMA callback function pointer. - * @param userData Parameter for callback function. - */ -void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData); - -/*! - * @brief Prepares the DMA transfer structure. - * @deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer. - * This function prepares the transfer configuration structure according to the user input. - * - * @param config The user configuration structure of type dma_transfer_t. - * @param srcAddr DMA transfer source address. - * @param dstAddr DMA transfer destination address. - * @param byteWidth DMA transfer destination address width(bytes). - * @param transferBytes DMA transfer bytes to be transferred. - * @param type DMA transfer type. - * @param nextDesc Chain custom descriptor to transfer. - * @note The data address and the data width must be consistent. For example, if the SRC - * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in - * source address error(SAE). - */ -void DMA_PrepareTransfer(dma_transfer_config_t *config, - void *srcAddr, - void *dstAddr, - uint32_t byteWidth, - uint32_t transferBytes, - dma_transfer_type_t type, - void *nextDesc); - -/*! - * @brief Prepare channel transfer configurations. - * - * This function used to prepare channel transfer configurations. - * - * @param config Pointer to DMA channel transfer configuration structure. - * @param srcStartAddr source start address. - * @param dstStartAddr destination start address. - * @param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * @param type transfer type. - * @param trigger DMA channel trigger configurations. - * @param nextDesc address of next descriptor. - */ -void DMA_PrepareChannelTransfer(dma_channel_config_t *config, - void *srcStartAddr, - void *dstStartAddr, - uint32_t xferCfg, - dma_transfer_type_t type, - dma_channel_trigger_t *trigger, - void *nextDesc); - -/*! - * @brief Submits the DMA transfer request. - * @deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * - * @param handle DMA handle pointer. - * @param config Pointer to DMA transfer configuration structure. - * @retval kStatus_DMA_Success It means submit transfer request succeed. - * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config); - -/*! - * @brief Submit channel transfer paramter directly. - * - * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table - * is defined in DMA driver, it is useful for the case: - * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used - for it. - * @code - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, - bytes), srcStartAddr, dstStartAddr, NULL); - DMA_StartTransfer(handle) - * @endcode - * - * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is - required, then application should prepare - * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * @code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc2); - DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, NULL); - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, - bytes), srcStartAddr, dstStartAddr, nextDesc0); - DMA_StartTransfer(handle); - * @endcode - * - * @param handle Pointer to DMA handle. - * @param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * @param srcStartAddr source start address. - * @param dstStartAddr destination start address. - * @param nextDesc address of next descriptor. - */ -void DMA_SubmitChannelTransferParameter( - dma_handle_t *handle, uint32_t xferCfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc); - -/*! - * @brief Submit channel descriptor. - * - * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table - is defined in - * DMA driver, this functiono is typical for the ping pong case: - * - * 1. for the ping pong case, application should responsible for the descriptor, for example, application should - * prepare two descriptor table with macro. - * @code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc0); - DMA_SetChannelConfig(base, channel, trigger, isPeriph); - DMA_CreateHandle(handle, base, channel) - DMA_SubmitChannelDescriptor(handle, nextDesc0); - DMA_StartTransfer(handle); - * @endcode - * - * @param handle Pointer to DMA handle. - * @param descriptor descriptor to submit. - */ -void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descriptor); - -/*! - * @brief Submits the DMA channel transfer request. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * It is used for the case: - * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used - for it. - * @code - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,NULL); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * @endcode - * - * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is - required, then application should prepare - * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * @code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc2); - DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, NULL); - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * @endcode - * - * 3. for the ping pong case, application should responsible for link descriptor, for example, application should - prepare - * two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. - * @code - define link descriptor table in application with macro - DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); - - DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc1); - DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), - srcStartAddr, dstStartAddr, nextDesc0); - DMA_CreateHandle(handle, base, channel) - DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); - DMA_SubmitChannelTransfer(handle, config) - DMA_StartTransfer(handle) - * @endcode - * @param handle DMA handle pointer. - * @param config Pointer to DMA transfer configuration structure. - * @retval kStatus_DMA_Success It means submit transfer request succeed. - * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config); - -/*! - * @brief DMA start transfer. - * - * This function enables the channel request. User can call this function after submitting the transfer request - * It will trigger transfer start with software trigger only when hardware trigger is not used. - * - * @param handle DMA handle pointer. - */ -void DMA_StartTransfer(dma_handle_t *handle); - -/*! - * @brief DMA IRQ handler for descriptor transfer complete. - * - * This function clears the channel major interrupt flag and call - * the callback function if it is not NULL. - * - * @param base DMA base address. - */ -void DMA_IRQHandle(DMA_Type *base); - -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/* @} */ - -#endif /*_FSL_DMA_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.c deleted file mode 100644 index 7a21a1ce0ea..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.c +++ /dev/null @@ -1,412 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm" -#endif - -/*! - * @brief Used for conversion between `void*` and `uint32_t`. - */ -typedef union pvoid_to_u32 -{ - void *pvoid; - uint32_t u32; -} pvoid_to_u32_t; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! @brief Set the FLEXCOMM mode . */ -static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock); - -/*! @brief check whether flexcomm supports peripheral type */ -static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map FLEXCOMM instance number to base address. */ -static const uint32_t s_flexcommBaseAddrs[] = FLEXCOMM_BASE_ADDRS; - -/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ -static flexcomm_irq_handler_t s_flexcommIrqHandler[ARRAY_SIZE(s_flexcommBaseAddrs)]; - -/*! @brief Pointers to handles for each instance to provide context to interrupt routines */ -static void *s_flexcommHandle[ARRAY_SIZE(s_flexcommBaseAddrs)]; - -/*! @brief Array to map FLEXCOMM instance number to IRQ number. */ -IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief IDs of clock for each FLEXCOMM module */ -static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) -/*! @brief Pointers to FLEXCOMM resets for each instance. */ -static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* check whether flexcomm supports peripheral type */ -static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph) -{ - if (periph == FLEXCOMM_PERIPH_NONE) - { - return true; - } - else if (periph <= FLEXCOMM_PERIPH_I2S_TX) - { - return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false; - } - else if (periph == FLEXCOMM_PERIPH_I2S_RX) - { - return (base->PSELID & (1U << 7U)) > (uint32_t)0U ? true : false; - } - else - { - return false; - } -} - -/* Get the index corresponding to the FLEXCOMM */ -/*! brief Returns instance number for FLEXCOMM module with given base address. */ -uint32_t FLEXCOMM_GetInstance(void *base) -{ - uint32_t i; - pvoid_to_u32_t BaseAddr; - BaseAddr.pvoid = base; - - for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++) - { - if (BaseAddr.u32 == s_flexcommBaseAddrs[i]) - { - break; - } - } - - assert(i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT); - return i; -} - -/* Changes FLEXCOMM mode */ -static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock) -{ - /* Check whether peripheral type is present */ - if (!FLEXCOMM_PeripheralIsPresent(base, periph)) - { - return kStatus_OutOfRange; - } - - /* Flexcomm is locked to different peripheral type than expected */ - if (((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) != 0U) && - ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph)) - { - return kStatus_Fail; - } - - /* Check if we are asked to lock */ - if (lock != 0) - { - base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK; - } - else - { - base->PSELID = (uint32_t)periph; - } - - return kStatus_Success; -} - -/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ -status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) -{ - uint32_t idx = FLEXCOMM_GetInstance(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the peripheral clock */ - CLOCK_EnableClock(s_flexcommClocks[idx]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) - /* Reset the FLEXCOMM module */ - RESET_PeripheralReset(s_flexcommResets[idx]); -#endif - - /* Set the FLEXCOMM to given peripheral */ - return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0); -} - -/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM - * mode */ -void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(base); - - /* Clear handler first to avoid execution of the handler with wrong handle */ - s_flexcommIrqHandler[instance] = NULL; - s_flexcommHandle[instance] = flexcommHandle; - s_flexcommIrqHandler[instance] = handler; - SDK_ISR_EXIT_BARRIER; -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(FLEXCOMM0) -void FLEXCOMM0_DriverIRQHandler(void); -void FLEXCOMM0_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM0); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM1) -void FLEXCOMM1_DriverIRQHandler(void); -void FLEXCOMM1_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM1); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM2) -void FLEXCOMM2_DriverIRQHandler(void); -void FLEXCOMM2_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM2); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM3) -void FLEXCOMM3_DriverIRQHandler(void); -void FLEXCOMM3_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM3); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM4) -void FLEXCOMM4_DriverIRQHandler(void); -void FLEXCOMM4_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM4); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} - -#endif - -#if defined(FLEXCOMM5) -void FLEXCOMM5_DriverIRQHandler(void); -void FLEXCOMM5_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM5); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM6) -void FLEXCOMM6_DriverIRQHandler(void); -void FLEXCOMM6_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM6); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM7) -void FLEXCOMM7_DriverIRQHandler(void); -void FLEXCOMM7_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM7); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM8) -void FLEXCOMM8_DriverIRQHandler(void); -void FLEXCOMM8_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM8); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM9) -void FLEXCOMM9_DriverIRQHandler(void); -void FLEXCOMM9_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM9); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM10) -void FLEXCOMM10_DriverIRQHandler(void); -void FLEXCOMM10_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM10); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM11) -void FLEXCOMM11_DriverIRQHandler(void); -void FLEXCOMM11_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM11); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM12) -void FLEXCOMM12_DriverIRQHandler(void); -void FLEXCOMM12_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM12); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM13) -void FLEXCOMM13_DriverIRQHandler(void); -void FLEXCOMM13_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM13); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM14) -void FLEXCOMM14_DriverIRQHandler(void); -void FLEXCOMM14_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM14); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM15) -void FLEXCOMM15_DriverIRQHandler(void); -void FLEXCOMM15_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM15); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(FLEXCOMM16) -void FLEXCOMM16_DriverIRQHandler(void); -void FLEXCOMM16_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM16); - assert(s_flexcommIrqHandler[instance] != NULL); - s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.h deleted file mode 100644 index f96086fdecc..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_FLEXCOMM_H_ -#define _FSL_FLEXCOMM_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup flexcomm_driver - * @{ - */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FlexCOMM driver version 2.0.2. */ -#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -/*! @brief FLEXCOMM peripheral modes. */ -typedef enum -{ - FLEXCOMM_PERIPH_NONE, /*!< No peripheral */ - FLEXCOMM_PERIPH_USART, /*!< USART peripheral */ - FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */ - FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */ - FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */ - FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */ -} FLEXCOMM_PERIPH_T; - -/*! @brief Typedef for interrupt handler. */ -typedef void (*flexcomm_irq_handler_t)(void *base, void *handle); - -/*! @brief Array with IRQ number for each FLEXCOMM module. */ -extern IRQn_Type const kFlexcommIrqs[]; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @brief Returns instance number for FLEXCOMM module with given base address. */ -uint32_t FLEXCOMM_GetInstance(void *base); - -/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ -status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph); - -/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM - * mode */ -void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle); - -#if defined(__cplusplus) -} -#endif - -/*@}*/ - -#endif /* _FSL_FLEXCOMM_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_fro_calib.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_fro_calib.h deleted file mode 100644 index 9662444a526..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_fro_calib.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2017, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_FRO_CALIB_H_ -#define _FSL_FRO_CALIB_H_ - -#include "fsl_common.h" -#include "fsl_device_registers.h" -#include - -/*! - * @addtogroup power - * @{ - */ -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FRO_CALIB driver version 1.0.0. */ -#define FSL_FRO_CALIB_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) -/*@}*/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.fro_calib" -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Returns the version of the FRO Calibration library */ -unsigned int fro_calib_Get_Lib_Ver(void); - -/* ctimer instance */ -/* ctimer clock frquency in KHz */ -void Chip_TIMER_Instance_Freq(CTIMER_Type *base, unsigned int ctimerFreq); - -/* USB_SOF_Event */ -/* Application software should be written to make sure the USB_SOF_EVENT() is */ -/* being called with lower interrupt latency for calibration to work properly */ -void USB_SOF_Event(void); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* _FSL_FRO_CALIB_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.c deleted file mode 100644 index 9dc2e5eff0d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.c +++ /dev/null @@ -1,372 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_gint.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.gint" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to GINT bases for each instance. */ -static GINT_Type *const s_gintBases[FSL_FEATURE_SOC_GINT_COUNT] = GINT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Clocks for each instance. */ -static const clock_ip_name_t s_gintClocks[FSL_FEATURE_SOC_GINT_COUNT] = GINT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -/*! @brief Resets for each instance. */ -static const reset_ip_name_t s_gintResets[FSL_FEATURE_SOC_GINT_COUNT] = GINT_RSTS; -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/* @brief Irq number for each instance */ -static const IRQn_Type s_gintIRQ[FSL_FEATURE_SOC_GINT_COUNT] = GINT_IRQS; - -/*! @brief Callback function array for GINT(s). */ -static gint_cb_t s_gintCallback[FSL_FEATURE_SOC_GINT_COUNT]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t GINT_GetInstance(GINT_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_gintBases); instance++) - { - if (s_gintBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_gintBases)); - - return instance; -} - -/*! - * brief Initialize GINT peripheral. - - * This function initializes the GINT peripheral and enables the clock. - * - * param base Base address of the GINT peripheral. - * - * retval None. - */ -void GINT_Init(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - s_gintCallback[instance] = NULL; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the peripheral clock */ - CLOCK_EnableClock(s_gintClocks[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_gintResets[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -} - -/*! - * brief Setup GINT peripheral control parameters. - - * This function sets the control parameters of GINT peripheral. - * - * param base Base address of the GINT peripheral. - * param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. - * param trig Controls if the enabled inputs are level or edge sensitive based on polarity. - * param callback This function is called when configured group interrupt is generated. - * - * retval None. - */ -void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - base->CTRL = (GINT_CTRL_COMB(comb) | GINT_CTRL_TRIG(trig)); - - /* Save callback pointer */ - s_gintCallback[instance] = callback; -} - -/*! - * brief Get GINT peripheral control parameters. - - * This function returns the control parameters of GINT peripheral. - * - * param base Base address of the GINT peripheral. - * param comb Pointer to store combine input value. - * param trig Pointer to store trigger value. - * param callback Pointer to store callback function. - * - * retval None. - */ -void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback) -{ - uint32_t instance; - uint32_t combValue; - uint32_t trigValue; - - instance = GINT_GetInstance(base); - - combValue = (base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT; - *comb = (gint_comb_t)combValue; - trigValue = (base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT; - *trig = (gint_trig_t)trigValue; - *callback = s_gintCallback[instance]; -} - -/*! - * brief Configure GINT peripheral pins. - - * This function enables and controls the polarity of enabled pin(s) of a given port. - * - * param base Base address of the GINT peripheral. - * param port Port number. - * param polarityMask Each bit position selects the polarity of the corresponding enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * param enableMask Each bit position selects if the corresponding pin is enabled or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * retval None. - */ -void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask) -{ - base->PORT_POL[port] = polarityMask; - base->PORT_ENA[port] = enableMask; -} - -/*! - * brief Get GINT peripheral pin configuration. - - * This function returns the pin configuration of a given port. - * - * param base Base address of the GINT peripheral. - * param port Port number. - * param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding - enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled - or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * retval None. - */ -void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask) -{ - *polarityMask = base->PORT_POL[port]; - *enableMask = base->PORT_ENA[port]; -} - -/*! - * brief Enable callback. - - * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * param base Base address of the GINT peripheral. - * - * retval None. - */ -void GINT_EnableCallback(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - /* If GINT is configured in "AND" mode a spurious interrupt is generated. - Clear status and pending interrupt before enabling the irq in NVIC. */ - GINT_ClrStatus(base); - NVIC_ClearPendingIRQ(s_gintIRQ[instance]); - (void)EnableIRQ(s_gintIRQ[instance]); -} - -/*! - * brief Disable callback. - - * This function disables the interrupt for the selected GINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * param base Base address of the peripheral. - * - * retval None. - */ -void GINT_DisableCallback(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - (void)DisableIRQ(s_gintIRQ[instance]); - GINT_ClrStatus(base); - NVIC_ClearPendingIRQ(s_gintIRQ[instance]); -} - -/*! - * brief Deinitialize GINT peripheral. - - * This function disables the GINT clock. - * - * param base Base address of the GINT peripheral. - * - * retval None. - */ -void GINT_Deinit(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - /* Cleanup */ - GINT_DisableCallback(base); - s_gintCallback[instance] = NULL; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_gintResets[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the peripheral clock */ - CLOCK_DisableClock(s_gintClocks[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(GINT0) -void GINT0_DriverIRQHandler(void); -void GINT0_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[0]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[0] != NULL) - { - s_gintCallback[0](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT1) -void GINT1_DriverIRQHandler(void); -void GINT1_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[1]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[1] != NULL) - { - s_gintCallback[1](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT2) -void GINT2_DriverIRQHandler(void); -void GINT2_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[2]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[2] != NULL) - { - s_gintCallback[2](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT3) -void GINT3_DriverIRQHandler(void); -void GINT3_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[3]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[3] != NULL) - { - s_gintCallback[3](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT4) -void GINT4_DriverIRQHandler(void); -void GINT4_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[4]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[4] != NULL) - { - s_gintCallback[4](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT5) -void GINT5_DriverIRQHandler(void); -void GINT5_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[5]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[5] != NULL) - { - s_gintCallback[5](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT6) -void GINT6_DriverIRQHandler(void); -void GINT6_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[6]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[6] != NULL) - { - s_gintCallback[6](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(GINT7) -void GINT7_DriverIRQHandler(void); -void GINT7_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[7]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[7] != NULL) - { - s_gintCallback[7](); - } - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.h deleted file mode 100644 index adc301a9e0d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_GINT_H_ -#define _FSL_GINT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup gint_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3. */ -/*@}*/ - -/*! @brief GINT combine inputs type */ -typedef enum _gint_comb -{ - kGINT_CombineOr = 0U, /*!< A grouped interrupt is generated when any one of the enabled inputs is active */ - kGINT_CombineAnd = 1U /*!< A grouped interrupt is generated when all enabled inputs are active */ -} gint_comb_t; - -/*! @brief GINT trigger type */ -typedef enum _gint_trig -{ - kGINT_TrigEdge = 0U, /*!< Edge triggered based on polarity */ - kGINT_TrigLevel = 1U /*!< Level triggered based on polarity */ -} gint_trig_t; - -/* @brief GINT port type */ -typedef enum _gint_port -{ - kGINT_Port0 = 0U, - kGINT_Port1 = 1U, -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 2U) - kGINT_Port2 = 2U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 3U) - kGINT_Port3 = 3U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 4U) - kGINT_Port4 = 4U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 5U) - kGINT_Port5 = 5U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 6U) - kGINT_Port6 = 6U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 7U) - kGINT_Port7 = 7U, -#endif -} gint_port_t; - -/*! @brief GINT Callback function. */ -typedef void (*gint_cb_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize GINT peripheral. - - * This function initializes the GINT peripheral and enables the clock. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_Init(GINT_Type *base); - -/*! - * @brief Setup GINT peripheral control parameters. - - * This function sets the control parameters of GINT peripheral. - * - * @param base Base address of the GINT peripheral. - * @param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. - * @param trig Controls if the enabled inputs are level or edge sensitive based on polarity. - * @param callback This function is called when configured group interrupt is generated. - * - * @retval None. - */ -void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback); - -/*! - * @brief Get GINT peripheral control parameters. - - * This function returns the control parameters of GINT peripheral. - * - * @param base Base address of the GINT peripheral. - * @param comb Pointer to store combine input value. - * @param trig Pointer to store trigger value. - * @param callback Pointer to store callback function. - * - * @retval None. - */ -void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback); - -/*! - * @brief Configure GINT peripheral pins. - - * This function enables and controls the polarity of enabled pin(s) of a given port. - * - * @param base Base address of the GINT peripheral. - * @param port Port number. - * @param polarityMask Each bit position selects the polarity of the corresponding enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * @param enableMask Each bit position selects if the corresponding pin is enabled or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * @retval None. - */ -void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask); - -/*! - * @brief Get GINT peripheral pin configuration. - - * This function returns the pin configuration of a given port. - * - * @param base Base address of the GINT peripheral. - * @param port Port number. - * @param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding - enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * @param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled - or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * @retval None. - */ -void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask); - -/*! - * @brief Enable callback. - - * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_EnableCallback(GINT_Type *base); - -/*! - * @brief Disable callback. - - * This function disables the interrupt for the selected GINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * @param base Base address of the peripheral. - * - * @retval None. - */ -void GINT_DisableCallback(GINT_Type *base); - -/*! - * @brief Clear GINT status. - - * This function clears the GINT status bit. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -static inline void GINT_ClrStatus(GINT_Type *base) -{ - base->CTRL |= GINT_CTRL_INT_MASK; -} - -/*! - * @brief Get GINT status. - - * This function returns the GINT status. - * - * @param base Base address of the GINT peripheral. - * - * @retval status = 0 No group interrupt request. = 1 Group interrupt request active. - */ -static inline uint32_t GINT_GetStatus(GINT_Type *base) -{ - return (base->CTRL & GINT_CTRL_INT_MASK); -} - -/*! - * @brief Deinitialize GINT peripheral. - - * This function disables the GINT clock. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_Deinit(GINT_Type *base); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_GINT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.c deleted file mode 100644 index be100d5e9e3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.c +++ /dev/null @@ -1,317 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_gpio.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map FGPIO instance number to clock name. */ -static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) -/*! @brief Pointers to GPIO resets for each instance. */ -static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N; -#endif -/******************************************************************************* - * Prototypes - ************ ******************************************************************/ -/*! - * @brief Enable GPIO port clock. - * - * @param base GPIO peripheral base pointer. - * @param port GPIO port number. - */ -static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port); - -/******************************************************************************* - * Code - ******************************************************************************/ -static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - assert(port < ARRAY_SIZE(s_gpioClockName)); - - /* Upgate the GPIO clock */ - CLOCK_EnableClock(s_gpioClockName[port]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Initializes the GPIO peripheral. - * - * This function ungates the GPIO clock. - * - * param base GPIO peripheral base pointer. - * param port GPIO port number. - */ -void GPIO_PortInit(GPIO_Type *base, uint32_t port) -{ - GPIO_EnablePortClock(base, port); - -#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) - /* Reset the GPIO module */ - RESET_PeripheralReset(s_gpioResets[port]); -#endif -} - -/*! - * brief Initializes a GPIO pin used by the board. - * - * To initialize the GPIO, define a pin configuration, either input or output, in the user file. - * Then, call the GPIO_PinInit() function. - * - * This is an example to define an input pin or output pin configuration: - * code - * Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * endcode - * - * param base GPIO peripheral base pointer(Typically GPIO) - * param port GPIO port number - * param pin GPIO pin number - * param config GPIO pin configuration pointer - */ -void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) -{ - GPIO_EnablePortClock(base, port); - - if (config->pinDirection == kGPIO_DigitalInput) - { -#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) - base->DIRCLR[port] = 1UL << pin; -#else - base->DIR[port] &= ~(1UL << pin); -#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ - } - else - { - /* Set default output value */ - if (config->outputLogic == 0U) - { - base->CLR[port] = (1UL << pin); - } - else - { - base->SET[port] = (1UL << pin); - } -/* Set pin direction */ -#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) - base->DIRSET[port] = 1UL << pin; -#else - base->DIR[port] |= 1UL << pin; -#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ - } -} - -#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT -/*! - * @brief Set the configuration of pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param pin GPIO pin number. - * @param config GPIO pin interrupt configuration.. - */ -void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config) -{ - base->INTEDG[port] = (base->INTEDG[port] & ~(1UL << pin)) | ((uint32_t)config->mode << pin); - - base->INTPOL[port] = (base->INTPOL[port] & ~(1UL << pin)) | ((uint32_t)config->polarity << pin); -} - -/*! - * @brief Enables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] | mask; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] | mask; - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Disables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] & ~mask; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] & ~mask; - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Clears multiple pins interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTSTATA[port] = mask; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTSTATB[port] = mask; - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @ Read port interrupt status. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param index GPIO interrupt number. - * @retval masked GPIO status value - */ -uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index) -{ - uint32_t status = 0U; - - if ((uint32_t)kGPIO_InterruptA == index) - { - status = base->INTSTATA[port]; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - status = base->INTSTATB[port]; - } - else - { - /*Should not enter here*/ - } - return status; -} - -/*! - * @brief Enables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] | (1UL << pin); - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] | (1UL << pin); - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Disables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] & ~(1UL << pin); - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] & ~(1UL << pin); - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Clears the specific pin interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) -{ - if ((uint32_t)kGPIO_InterruptA == index) - { - base->INTSTATA[port] = 1UL << pin; - } - else if ((uint32_t)kGPIO_InterruptB == index) - { - base->INTSTATB[port] = 1UL << pin; - } - else - { - /*Should not enter here*/ - } -} -#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.h deleted file mode 100644 index 50a33f89208..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.h +++ /dev/null @@ -1,364 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _LPC_GPIO_H_ -#define _LPC_GPIO_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_gpio - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPC GPIO driver version. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 7)) -/*@}*/ - -/*! @brief LPC GPIO direction definition */ -typedef enum _gpio_pin_direction -{ - kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ - kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ -} gpio_pin_direction_t; - -/*! - * @brief The GPIO pin configuration structure. - * - * Every pin can only be configured as either output pin or input pin at a time. - * If configured as a input pin, then leave the outputConfig unused. - */ -typedef struct _gpio_pin_config -{ - gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ - /* Output configurations, please ignore if configured as a input one */ - uint8_t outputLogic; /*!< Set default output logic, no use in input */ -} gpio_pin_config_t; - -#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT) -#define GPIO_PIN_INT_LEVEL 0x00U -#define GPIO_PIN_INT_EDGE 0x01U - -#define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U -#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U - -/*! @brief GPIO Pin Interrupt enable mode */ -typedef enum _gpio_pin_enable_mode -{ - kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */ - kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE /*!< Generate Pin Interrupt on edge mode */ -} gpio_pin_enable_mode_t; - -/*! @brief GPIO Pin Interrupt enable polarity */ -typedef enum _gpio_pin_enable_polarity -{ - kGPIO_PinIntEnableHighOrRise = - PINT_PIN_INT_HIGH_OR_RISE_TRIGGER, /*!< Generate Pin Interrupt on high level or rising edge */ - kGPIO_PinIntEnableLowOrFall = - PINT_PIN_INT_LOW_OR_FALL_TRIGGER /*!< Generate Pin Interrupt on low level or falling edge */ -} gpio_pin_enable_polarity_t; - -/*! @brief LPC GPIO interrupt index definition */ -typedef enum _gpio_interrupt_index -{ - kGPIO_InterruptA = 0U, /*!< Set current pin as interrupt A*/ - kGPIO_InterruptB = 1U, /*!< Set current pin as interrupt B*/ -} gpio_interrupt_index_t; - -/*! @brief Configures the interrupt generation condition. */ -typedef struct _gpio_interrupt_config -{ - uint8_t mode; /* The trigger mode of GPIO interrupts */ - uint8_t polarity; /* The polarity of GPIO interrupts */ -} gpio_interrupt_config_t; -#endif - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @name GPIO Configuration */ -/*@{*/ - -/*! - * @brief Initializes the GPIO peripheral. - * - * This function ungates the GPIO clock. - * - * @param base GPIO peripheral base pointer. - * @param port GPIO port number. - */ -void GPIO_PortInit(GPIO_Type *base, uint32_t port); - -/*! - * @brief Initializes a GPIO pin used by the board. - * - * To initialize the GPIO, define a pin configuration, either input or output, in the user file. - * Then, call the GPIO_PinInit() function. - * - * This is an example to define an input pin or output pin configuration: - * @code - * Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * @endcode - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @param config GPIO pin configuration pointer - */ -void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config); - -/*@}*/ - -/*! @name GPIO Output Operations */ -/*@{*/ - -/*! - * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @param output GPIO pin output logic level. - * - 0: corresponding pin output low-logic level. - * - 1: corresponding pin output high-logic level. - */ -static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) -{ - base->B[port][pin] = output; -} - -/*@}*/ -/*! @name GPIO Input Operations */ -/*@{*/ - -/*! - * @brief Reads the current input value of the GPIO PIN. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @retval GPIO port input value - * - 0: corresponding pin input low-logic level. - * - 1: corresponding pin input high-logic level. - */ -static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) -{ - return (uint32_t)base->B[port][pin]; -} - -/*@}*/ - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 1. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->SET[port] = mask; -} - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 0. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->CLR[port] = mask; -} - -/*! - * @brief Reverses current output logic of the multiple GPIO pins. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->NOT[port] = mask; -} - -/*@}*/ - -/*! - * @brief Reads the current input value of the whole GPIO port. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - */ -static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port) -{ - return (uint32_t)base->PIN[port]; -} - -/*@}*/ -/*! @name GPIO Mask Operations */ -/*@{*/ - -/*! - * @brief Sets port mask, 0 - enable pin, 1 - disable pin. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->MASK[port] = mask; -} - -/*! - * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param output GPIO port output value. - */ -static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output) -{ - base->MPIN[port] = output; -} - -/*! - * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be - * affected. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @retval masked GPIO port value - */ -static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) -{ - return (uint32_t)base->MPIN[port]; -} - -#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT -/*! - * @brief Set the configuration of pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param pin GPIO pin number. - * @param config GPIO pin interrupt configuration.. - */ -void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config); - -/*! - * @brief Enables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); - -/*! - * @brief Disables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); - -/*! - * @brief Clears pin interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); - -/*! - * @ Read port interrupt status. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param index GPIO interrupt number. - * @retval masked GPIO status value - */ -uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index); - -/*! - * @brief Enables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); - -/*! - * @brief Disables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); - -/*! - * @brief Clears the specific pin interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); - -#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* _LPC_GPIO_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.c deleted file mode 100644 index 73a2037ae2a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.c +++ /dev/null @@ -1,1721 +0,0 @@ -/* - * Copyright 2017-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_hashcrypt.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.hashcrypt" -#endif - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*!< SHA-1 and SHA-256 block size */ -#define SHA_BLOCK_SIZE 64U -/*!< max number of blocks that can be proccessed in one run (master mode) */ -#define SHA_MASTER_MAX_BLOCKS 2048U - -/*!< Use standard C library memcpy */ -#define hashcrypt_memcpy memcpy - -/*! Internal states of the HASH creation process */ -typedef enum _hashcrypt_sha_algo_state -{ - kHASHCRYPT_HashInit = 1u, /*!< Init state, the NEW bit in SHA Control register has not been written yet. */ - kHASHCRYPT_HashUpdate, /*!< Update state, DIGEST registers contain running hash, NEW bit in SHA control register has - been written. */ -} hashcrypt_sha_algo_state_t; - -/*! 64-byte block represented as byte array of 16 32-bit words */ -typedef union _sha_hash_block -{ - uint32_t w[SHA_BLOCK_SIZE / 4]; /*!< array of 32-bit words */ - uint8_t b[SHA_BLOCK_SIZE]; /*!< byte array */ -} hashcrypt_sha_block_t; - -/*! internal sha context structure */ -typedef struct _hashcrypt_sha_ctx_internal -{ - hashcrypt_sha_block_t blk; /*!< memory buffer. only full 64-byte blocks are written to SHA during hash updates */ - size_t blksz; /*!< number of valid bytes in memory buffer */ - hashcrypt_algo_t algo; /*!< selected algorithm from the set of supported algorithms */ - hashcrypt_sha_algo_state_t state; /*!< finite machine state of the hash software process */ - size_t fullMessageSize; /*!< track message size during SHA_Update(). The value is used for padding. */ - uint32_t remainingBlcks; /*!< number of remaining blocks to process in AHB master mode */ - hashcrypt_callback_t hashCallback; /*!< pointer to HASH callback function */ - void - *userData; /*!< user data to be passed as an argument to callback function, once callback is invoked from isr */ -#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) - uint32_t runningHash[8]; /*!< running hash. up to SHA-256, that is 32 bytes. */ -#endif -} hashcrypt_sha_ctx_internal_t; - -#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) -#define SHA1_LEN 5u -#define SHA256_LEN 8u -#endif - -/*!< SHA-1 and SHA-256 digest length in bytes */ -enum _hashcrypt_sha_digest_len -{ - kHASHCRYPT_OutLenSha1 = 20u, - kHASHCRYPT_OutLenSha256 = 32u, -}; - -/*!< pointer to hash context structure used by isr */ -static hashcrypt_hash_ctx_t *s_ctx; - -/*!< macro for checking build time condition. It is used to assure the hashcrypt_sha_ctx_internal_t can fit into - * hashcrypt_hash_ctx_t */ -#define BUILD_ASSERT(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused)) - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * @brief Swap bytes withing 32-bit word. - * - * This function changes endianess of a 32-bit word. - * - * @param in 32-bit unsigned integer - * @return 32-bit unsigned integer with different endianess (big endian to little endian and vice versa). - */ - -#define swap_bytes(in) __REV(in) - -/*! - * @brief Increment a 16 byte integer. - * - * This function increments by one a 16 byte integer. - * - * @param input Pointer to a 16 byte integer to be incremented by one. - */ -static void ctrIncrement(uint8_t *input) -{ - int i = 15; - while (input[i] == (uint8_t)0xFFu) - { - input[i] = (uint8_t)0x00u; - i--; - if (i < 0) - { - return; - } - } - - if (i >= 0) - { - input[i] += (uint8_t)1u; - } -} - -/*! - * @brief Reads an unaligned word. - * - * This function creates a 32-bit word from an input array of four bytes. - * - * @param src Input array of four bytes. The array can start at any address in memory. - * @return 32-bit unsigned int created from the input byte array. - */ - -/* Force lower optimization for Keil, otherwise it replaces inline LDR with LDM */ -#if defined(__CC_ARM) -#pragma push -#pragma O0 -#endif - -static inline uint32_t hashcrypt_get_word_from_unaligned(const uint8_t *srcAddr) -{ -#if (!(defined(__CORTEX_M)) || (defined(__CORTEX_M) && (__CORTEX_M == 0))) - register const uint8_t *src = srcAddr; - /* Cortex M0 does not support misaligned loads */ - if (0U != ((uint32_t)src & 0x3u)) - { - union _align_bytes_t - { - uint32_t word; - uint8_t byte[sizeof(uint32_t)]; - } my_bytes; - - my_bytes.byte[0] = *src; - my_bytes.byte[1] = src[1]; - my_bytes.byte[2] = src[2]; - my_bytes.byte[3] = src[3]; - return my_bytes.word; - } - else - { - /* addr aligned to 0-modulo-4 so it is safe to type cast */ - return *((const uint32_t *)(uint32_t)src); - } -#elif defined(__CC_ARM) - /* -O3 optimization in Keil 5.15 and 5.16a uses LDM instruction here (LDM r4!, {r0}) - * which is wrong, because srcAddr might be unaligned. - * LDM on unaligned address causes hard-fault. in contrary, - * LDR supports unaligned address on Cortex M4 */ - - register uint32_t retVal; - __asm - { - LDR retVal, [srcAddr] - } - return retVal; -#else - return *((const uint32_t *)(uintptr_t)srcAddr); -#endif -} - -/* End lower optimization */ -#if defined(__CC_ARM) -#pragma pop -#endif - -static status_t hashcrypt_get_key_from_unaligned_src(uint8_t *dest, const uint8_t *src, size_t size) -{ - status_t retVal = kStatus_InvalidArgument; - uint32_t i; - - /* destination is SDK driver internal workspace and it must be aligned */ - assert(0x0u == ((uint32_t)dest & 0x1u)); - if (0U != ((uint32_t)dest & 0x1u)) - { - return retVal; - } - - for (i = 0; i < ((uint32_t)size / 4u); i++) - { - ((uint32_t *)(uintptr_t)dest)[i] = hashcrypt_get_word_from_unaligned(&src[i * sizeof(uint32_t)]); - } - - return kStatus_Success; -} - -/*! - * @brief LDM to SHA engine INDATA and ALIAS registers. - * - * This function writes 16 words starting from the src address (must be word aligned) - * to the dst address. Dst address does not increment (destination is peripheral module register INDATA). - * Src address increments to load 16 consecutive words. - * - * @param dst peripheral register address (word aligned) - * @param src address of the input 512-bit block (16 words) (word aligned) - * - */ -__STATIC_FORCEINLINE void hashcrypt_sha_ldm_stm_16_words(HASHCRYPT_Type *base, const uint32_t *src) -{ - /* Data Synchronization Barrier */ - __DSB(); - /* - typedef struct _one_block - { - uint32_t a[8]; - } one_block_t; - - volatile one_block_t *ldst = (void *)(uintptr_t)(&base->INDATA); - one_block_t *lsrc = (void *)(uintptr_t)src; - *ldst = lsrc[0]; - *ldst = lsrc[1]; - */ - - /* Data Synchronization Barrier prevent compiler from reordering memory write when -O2 or higher is used. */ - /* The address is passed to the crypto engine for hashing below, therefore out */ - /* of order memory write due to compiler optimization must be prevented. */ - __DSB(); - - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(src); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(1); - - __DSB(); -} - -/*! - * @brief Loads data to Hashcrypt engine INDATA register. - * - * This function writes desired number of bytes starting from the src address - * to the dst address. Dst address does not increment (destination is peripheral module register INDATA). - * Src address increments to load consecutive words. - * - * @param src address of the input block - * @param size number of bytes to write - * - */ -__STATIC_INLINE void hashcrypt_load_data(HASHCRYPT_Type *base, uint32_t *src, size_t size) -{ - /* 16 bytes aligned input block */ - uint32_t __attribute__((aligned(4))) inAlign[HASHCRYPT_AES_BLOCK_SIZE / sizeof(uint32_t)]; - uint32_t *in; - uint8_t i; - - in = src; - /* Check if address of src data is aligned */ - if ((0U != ((uint32_t)in & 3U))) - { - for (i = 0; i < ((uint32_t)size / 4U); i++) - { - inAlign[i] = hashcrypt_get_word_from_unaligned((uint8_t *)&src[i]); - } - in = &inAlign[0]; - } - - if (size >= sizeof(uint32_t)) - { - base->INDATA = in[0]; - size -= sizeof(uint32_t); - } - - for (uint32_t j = 0; j < size / 4U; j++) - { - base->ALIAS[j] = in[j + 1U]; - } -} - -/*! - * @brief Checks availability of HW AES key. - * - * This function checks if the AES key is present at dedicated hardware bus - * and can be used at actual security level. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @return kStatus_Success if available, kStatus_Fail otherwise. - * - */ -static status_t hashcrypt_check_need_key(HASHCRYPT_Type *base, hashcrypt_handle_t *handle) -{ - if (handle->keyType == kHASHCRYPT_SecretKey) - { - volatile uint32_t wait = 50u; - /* wait until STATUS register is non-zero */ - while ((wait > 0U) && (base->STATUS == 0U)) - { - wait--; - } - /* if NEEDKEY bit is not set, HW key is available */ - if (0U == (base->STATUS & HASHCRYPT_STATUS_NEEDKEY_MASK)) - { - return kStatus_Success; - } - /* NEEDKEY is set, HW key is not available */ - return kStatus_Fail; - } - else - { - /* in case user key is used, return success */ - return kStatus_Success; - } -} - -/*! - * @brief Read OUTDATA registers. - * - * This function copies OUTDATA to output buffer. - * - * @param base Hachcrypt peripheral base address. - * @param[out] output Output buffer. - * @param Number of bytes to copy. - */ -static void hashcrypt_get_data(HASHCRYPT_Type *base, uint32_t *output, size_t outputSize) -{ - uint32_t digest[8]; - - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - - for (int i = 0; i < 8; i++) - { - digest[i] = swap_bytes(base->DIGEST0[i]); - } - - if (outputSize > sizeof(digest)) - { - outputSize = sizeof(digest); - } - (void)hashcrypt_memcpy(output, digest, outputSize); -} - -/*! - * @brief Initialize the Hashcrypt engine for new operation. - * - * This function sets NEW and MODE fields in Hashcrypt Control register to start new operation. - * - * @param base Hashcrypt peripheral base address. - * @param hashcrypt_algo_t Internal context. - */ -static void hashcrypt_engine_init(HASHCRYPT_Type *base, hashcrypt_algo_t algo) -{ - /* NEW bit must be set before we switch from previous mode otherwise new mode will not work correctly */ - base->CTRL = HASHCRYPT_CTRL_NEW_HASH(1); - base->CTRL = HASHCRYPT_CTRL_MODE(algo) | HASHCRYPT_CTRL_NEW_HASH(1); -} - -/*! - * @brief Deinitialization of the Hashcrypt engine. - * - * This function sets MODE field in Hashcrypt Control register to zero - disabled. - * This reduces power consumption of HASHCRYPT. - * - * @param base Hashcrypt peripheral base address. - */ -static inline void hashcrypt_engine_deinit(HASHCRYPT_Type *base) -{ - base->CTRL &= ~(HASHCRYPT_CTRL_MODE_MASK); -} - -/*! - * @brief Loads user key to INDATA register. - * - * This function writes user key stored in handle into HashCrypt INDATA register. - * - * @param base Hashcrypt peripheral base address. - * @param handle Handle used for this request. - */ -static void hashcrypt_aes_load_userKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle) -{ - size_t keySize = 0; - - switch (handle->keySize) - { - case kHASHCRYPT_Aes128: - keySize = 16; - break; - case kHASHCRYPT_Aes192: - keySize = 24; - break; - case kHASHCRYPT_Aes256: - keySize = 32; - break; - default: - /* All the cases have been listed above, the default clause should not be reached. */ - break; - } - if (keySize == 0U) - { - return; - } - hashcrypt_load_data(base, &handle->keyWord[0], keySize); -} - -/*! - * @brief Performs AES encryption/decryption of one data block. - * - * This function encrypts/decrypts one block of data with specified size. - * - * @param base Hashcrypt peripheral base address. - * @param input input data - * @param output output data - * @param size size of data block to process in bytes (must be 16bytes multiple). - */ -static status_t hashcrypt_aes_one_block_aligned(HASHCRYPT_Type *base, - const uint8_t *input, - uint8_t *output, - size_t size) -{ - status_t status = kStatus_Fail; - uint32_t idx = 0; - - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(input); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(size / 16U); - while (size >= HASHCRYPT_AES_BLOCK_SIZE) - { - /* Get result */ - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - - for (int i = 0; i < 4; i++) - { - ((uint32_t *)(uintptr_t)output + idx)[i] = swap_bytes(base->DIGEST0[i]); - } - - idx += HASHCRYPT_AES_BLOCK_SIZE / 4U; - size -= HASHCRYPT_AES_BLOCK_SIZE; - } - - if (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * @brief Performs AES encryption/decryption of one data block. - * - * This function encrypts/decrypts one block of data with specified size. - * - * @param base Hashcrypt peripheral base address. - * @param input input data - * @param output output data - * @param size size of data block to process in bytes (must be 16bytes multiple). - */ -static status_t hashcrypt_aes_one_block_unaligned(HASHCRYPT_Type *base, - const uint8_t *input, - uint8_t *output, - size_t size) -{ - status_t status = kStatus_Fail; - - /* we use AHB master mode as much as possible */ - /* however, it can work only with aligned input data */ - /* so, if unaligned, we do memcpy to temp buffer on stack, which is aligned, and use AHB mode to read data in */ - /* then we read data back to it and do memcpy to the output buffer */ - uint32_t temp[256 / sizeof(uint32_t)]; - int cnt = 0; - while (size != 0U) - { - size_t actSz = size >= 256u ? 256u : size; - size_t actSzOrig = actSz; - (void)memcpy(temp, (const uint32_t *)(uintptr_t)(input + 256 * cnt), actSz); - size -= actSz; - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(temp); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(actSz / 16U); - uint32_t outidx = 0; - while (actSz != 0U) - { - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - for (int i = 0; i < 4; i++) - { - (temp + outidx)[i] = swap_bytes(base->DIGEST0[i]); - } - outidx += HASHCRYPT_AES_BLOCK_SIZE / 4U; - actSz -= HASHCRYPT_AES_BLOCK_SIZE; - } - (void)memcpy(output + 256 * cnt, (const uint8_t *)(uintptr_t)temp, actSzOrig); - cnt++; - } - - if (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * @brief Performs AES encryption/decryption of one data block. - * - * This function encrypts/decrypts one block of data with specified size. - * - * @param base Hashcrypt peripheral base address. - * @param input input data - * @param output output data - * @param size size of data block to process in bytes (must be 16bytes multiple). - */ -static status_t hashcrypt_aes_one_block(HASHCRYPT_Type *base, const uint8_t *input, uint8_t *output, size_t size) -{ - status_t status = kStatus_Fail; - - /*MEMCTRL bitfield for COUNT is 11 bits, and this limits the number of blocks to process in one Master run to 2047 - (2^11 -1) blocks . Each block is 16bytes long, so biggest data size which can we do in one Master run is (2047 - blocks *16 bytes) = 32752 So, when size is overflowing HASHCRYPT_MEMCTRL_COUNT field of MEMCTRL register, we split - our data into more smaller chunks */ - - if (size > 32752U) - - { - size_t numBlock = size / 32752U; /* number of blocks, each block is processed in one run*/ - size_t remainingSize = size - (numBlock * 32752U); /* size of last block */ - - if ((0U != ((uint32_t)input & 0x3u)) || (0U != ((uint32_t)output & 0x3u))) /* If data is unaligned*/ - { - for (uint32_t i = 0; i < numBlock; i++) - { - status = hashcrypt_aes_one_block_unaligned(base, input, output, 32752U); - input += 32752U; - output += 32752U; - } - status = hashcrypt_aes_one_block_unaligned(base, input, output, remainingSize); - } - else /* If data is aligned*/ - { - for (uint32_t i = 0; i < numBlock; i++) - { - status = hashcrypt_aes_one_block_aligned(base, input, output, 32752U); - input += 32752U; - output += 32752U; - } - status = hashcrypt_aes_one_block_aligned(base, input, output, remainingSize); - } - } - - else /* size is less than COUNT field of MEMCTRL register so we can process all data at once */ - { - /* we use AHB master mode as much as possible */ - /* however, it can work only with aligned input data */ - /* so, if unaligned, we do memcpy to temp buffer on stack, which is aligned, and use AHB mode to read data in */ - /* then we read data back to it and do memcpy to the output buffer */ - if ((0U != ((uint32_t)input & 0x3u)) || (0U != ((uint32_t)output & 0x3u))) - { - status = hashcrypt_aes_one_block_unaligned(base, input, output, size); - } - else - { - status = hashcrypt_aes_one_block_aligned(base, input, output, size); - } - } - return status; -} - -/*! - * @brief Check validity of algoritm. - * - * This function checks the validity of input argument. - * - * @param algo Tested algorithm value. - * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. - */ -static status_t hashcrypt_sha_check_input_alg(HASHCRYPT_Type *base, hashcrypt_algo_t algo) -{ - if ((algo == kHASHCRYPT_Sha1) || (algo == kHASHCRYPT_Sha256)) - { - return kStatus_Success; - } - - return kStatus_InvalidArgument; -} - -/*! - * @brief Check validity of input arguments. - * - * This function checks the validity of input arguments. - * - * @param base SHA peripheral base address. - * @param ctx Memory buffer given by user application where the SHA_Init/SHA_Update/SHA_Finish store context. - * @param algo Tested algorithm value. - * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. - */ -static status_t hashcrypt_sha_check_input_args(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo) -{ - /* Check validity of input algorithm */ - if (kStatus_Success != hashcrypt_sha_check_input_alg(base, algo)) - { - return kStatus_InvalidArgument; - } - - if ((NULL == ctx) || (NULL == base)) - { - return kStatus_InvalidArgument; - } - - return kStatus_Success; -} - -/*! - * @brief Check validity of internal software context. - * - * This function checks if the internal context structure looks correct. - * - * @param ctxInternal Internal context. - * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. - */ -static status_t hashcrypt_sha_check_context(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) -{ - if ((NULL == ctxInternal) || (kStatus_Success != hashcrypt_sha_check_input_alg(base, ctxInternal->algo))) - { - return kStatus_InvalidArgument; - } - return kStatus_Success; -} - -/*! - * @brief Load 512-bit block (16 words) into SHA engine. - * - * This function aligns the input block and moves it into SHA engine INDATA. - * CPU polls the WAITING bit and then moves data by using LDM and STM instructions. - * - * @param base SHA peripheral base address. - * @param blk 512-bit block - */ -static void hashcrypt_sha_one_block(HASHCRYPT_Type *base, const uint8_t *blk) -{ - uint32_t temp[SHA_BLOCK_SIZE / sizeof(uint32_t)]; - const uint32_t *actBlk; - - /* make sure the 512-bit block is word aligned */ - if (0U != ((uintptr_t)blk & 0x3u)) - { - (void)hashcrypt_memcpy(temp, (const uint32_t *)(uintptr_t)blk, SHA_BLOCK_SIZE); - actBlk = (const uint32_t *)(uintptr_t)temp; - } - else - { - actBlk = (const uint32_t *)(uintptr_t)blk; - } - - /* poll waiting. */ - while (0U == (base->STATUS & HASHCRYPT_STATUS_WAITING_MASK)) - { - } - /* feed INDATA (and ALIASes). use STM instruction. */ - hashcrypt_sha_ldm_stm_16_words(base, actBlk); -} - -/*! - * @brief Adds message to current hash. - * - * This function merges the message to fill the internal buffer, empties the internal buffer if - * it becomes full, then process all remaining message data. - * - * - * @param base SHA peripheral base address. - * @param ctxInternal Internal context. - * @param message Input message. - * @param messageSize Size of input message in bytes. - * @return kStatus_Success. - */ -static status_t hashcrypt_sha_process_message_data(HASHCRYPT_Type *base, - hashcrypt_sha_ctx_internal_t *ctxInternal, - const uint8_t *message, - size_t messageSize) -{ - /* first fill the internal buffer to full block */ - if (ctxInternal->blksz != 0U) - { - size_t toCopy = SHA_BLOCK_SIZE - ctxInternal->blksz; - (void)hashcrypt_memcpy(&ctxInternal->blk.b[ctxInternal->blksz], message, toCopy); - message += toCopy; - messageSize -= toCopy; - - /* process full internal block */ - hashcrypt_sha_one_block(base, &ctxInternal->blk.b[0]); - } - - /* process all full blocks in message[] */ - if (messageSize >= SHA_BLOCK_SIZE) - { - if (0U != ((uintptr_t)message & 0x3u)) - { - while (messageSize >= SHA_BLOCK_SIZE) - { - hashcrypt_sha_one_block(base, message); - message += SHA_BLOCK_SIZE; - messageSize -= SHA_BLOCK_SIZE; - } - } - else - { - /* poll waiting. */ - while (0U == (base->STATUS & HASHCRYPT_STATUS_WAITING_MASK)) - { - } - uint32_t blkNum = (messageSize >> 6); /* div by 64 bytes */ - uint32_t blkBytes = blkNum * 64u; /* number of bytes in 64 bytes blocks */ - __DSB(); - __ISB(); - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(message); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(blkNum); - message += blkBytes; - messageSize -= blkBytes; - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - } - } - - /* copy last incomplete message bytes into internal block */ - (void)hashcrypt_memcpy(&ctxInternal->blk.b[0], message, messageSize); - ctxInternal->blksz = messageSize; - return kStatus_Success; -} - -/*! - * @brief Finalize the running hash to make digest. - * - * This function empties the internal buffer, adds padding bits, and generates final digest. - * - * @param base SHA peripheral base address. - * @param ctxInternal Internal context. - * @return kStatus_Success. - */ -static status_t hashcrypt_sha_finalize(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) -{ - hashcrypt_sha_block_t lastBlock; - - (void)memset(&lastBlock, 0, sizeof(hashcrypt_sha_block_t)); - - /* this is last call, so need to flush buffered message bytes along with padding */ - if (ctxInternal->blksz <= 55u) - { - /* last data is 440 bits or less. */ - (void)hashcrypt_memcpy(&lastBlock.b[0], &ctxInternal->blk.b[0], ctxInternal->blksz); - lastBlock.b[ctxInternal->blksz] = (uint8_t)0x80U; - lastBlock.w[SHA_BLOCK_SIZE / 4U - 1U] = swap_bytes(8u * ctxInternal->fullMessageSize); - hashcrypt_sha_one_block(base, &lastBlock.b[0]); - } - else - { - if (ctxInternal->blksz < SHA_BLOCK_SIZE) - { - ctxInternal->blk.b[ctxInternal->blksz] = (uint8_t)0x80U; - for (uint32_t i = ctxInternal->blksz + 1u; i < SHA_BLOCK_SIZE; i++) - { - ctxInternal->blk.b[i] = 0; - } - } - else - { - lastBlock.b[0] = (uint8_t)0x80U; - } - - hashcrypt_sha_one_block(base, &ctxInternal->blk.b[0]); - lastBlock.w[SHA_BLOCK_SIZE / 4U - 1U] = swap_bytes(8u * ctxInternal->fullMessageSize); - hashcrypt_sha_one_block(base, &lastBlock.b[0]); - } - /* poll wait for final digest */ - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - return kStatus_Success; -} - -static void hashcrypt_save_running_hash(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) -{ -#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) - size_t len = (ctxInternal->algo == kHASHCRYPT_Sha1) ? SHA1_LEN : SHA256_LEN; - - /* Wait until digest is ready */ - while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) - { - } - - /* Store partial digest to context */ - for (uint32_t i = 0; i < len; i++) - { - ctxInternal->runningHash[i] = base->DIGEST0[i]; - } -#endif -} - -static void hashcrypt_restore_running_hash(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) -{ -#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) - size_t len = (ctxInternal->algo == kHASHCRYPT_Sha1) ? SHA1_LEN : SHA256_LEN; - - /* When switching from different mode, need to set NEW bit to work properly */ - if ((base->CTRL & HASHCRYPT_CTRL_MODE_MASK) != HASHCRYPT_CTRL_MODE(ctxInternal->algo)) - { - base->CTRL = HASHCRYPT_CTRL_NEW_HASH(1); - base->CTRL = HASHCRYPT_CTRL_MODE(ctxInternal->algo) | HASHCRYPT_CTRL_NEW_HASH(1); - } - /* Set RELOAD bit to allow registers to be used */ - base->CTRL |= HASHCRYPT_CTRL_RELOAD_MASK; - - /* Reload partial hash digest */ - for (uint32_t i = 0; i < len; i++) - { - base->RELOAD[i] = ctxInternal->runningHash[i]; - } - /* Clear RELOAD register before continuing */ - base->CTRL &= ~HASHCRYPT_CTRL_RELOAD_MASK; -#endif -} - -status_t HASHCRYPT_SHA(HASHCRYPT_Type *base, - hashcrypt_algo_t algo, - const uint8_t *input, - size_t inputSize, - uint8_t *output, - size_t *outputSize) -{ - hashcrypt_hash_ctx_t hashCtx; - status_t status; - - status = HASHCRYPT_SHA_Init(base, &hashCtx, algo); - if (status != kStatus_Success) - { - return status; - } - - status = HASHCRYPT_SHA_Update(base, &hashCtx, input, inputSize); - if (status != kStatus_Success) - { - return status; - } - - status = HASHCRYPT_SHA_Finish(base, &hashCtx, output, outputSize); - - return status; -} - -status_t HASHCRYPT_SHA_Init(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo) -{ - status_t status; - - hashcrypt_sha_ctx_internal_t *ctxInternal; - /* compile time check for the correct structure size */ - BUILD_ASSERT(sizeof(hashcrypt_hash_ctx_t) >= sizeof(hashcrypt_sha_ctx_internal_t), hashcrypt_hash_ctx_t_size); - - status = hashcrypt_sha_check_input_args(base, ctx, algo); - if (status != kStatus_Success) - { - return status; - } - - /* set algorithm in context struct for later use */ - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; - ctxInternal->algo = algo; - ctxInternal->blksz = 0u; -#ifdef HASHCRYPT_SHA_DO_WIPE_CONTEXT - for (int i = 0; i < sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]); i++) - { - ctxInternal->blk.w[i] = 0u; - } -#endif /* HASHCRYPT_SHA_DO_WIPE_CONTEXT */ - ctxInternal->state = kHASHCRYPT_HashInit; - ctxInternal->fullMessageSize = 0; - return kStatus_Success; -} - -status_t HASHCRYPT_SHA_Update(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize) -{ - bool isUpdateState; - status_t status; - hashcrypt_sha_ctx_internal_t *ctxInternal; - size_t blockSize; - - if (inputSize == 0U) - { - return kStatus_Success; - } - - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; -#ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT - status = hashcrypt_sha_check_context(base, ctxInternal); - if (kStatus_Success != status) - { - return status; - } -#endif /* HASHCRYPT_SHA_DO_CHECK_CONTEXT */ - - ctxInternal->fullMessageSize += inputSize; - blockSize = SHA_BLOCK_SIZE; - /* if we are still less than 64 bytes, keep only in context */ - if ((ctxInternal->blksz + inputSize) <= blockSize) - { - (void)hashcrypt_memcpy((&ctxInternal->blk.b[0]) + ctxInternal->blksz, input, inputSize); - ctxInternal->blksz += inputSize; - return kStatus_Success; - } - else - { - isUpdateState = ctxInternal->state == kHASHCRYPT_HashUpdate; - if (!isUpdateState) - { - /* start NEW hash */ - hashcrypt_engine_init(base, ctxInternal->algo); - ctxInternal->state = kHASHCRYPT_HashUpdate; - } - else - { - hashcrypt_restore_running_hash(base, ctxInternal); - } - } - - /* process message data */ - status = hashcrypt_sha_process_message_data(base, ctxInternal, input, inputSize); - hashcrypt_save_running_hash(base, ctxInternal); - return status; -} - -status_t HASHCRYPT_SHA_Finish(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize) -{ - size_t algOutSize = 0; - status_t status; - hashcrypt_sha_ctx_internal_t *ctxInternal; -#ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT - uint32_t *ctxW; - uint32_t i; -#endif /* HASHCRYPT_SHA_DO_CHECK_CONTEXT */ - - if (output == NULL) - { - return kStatus_InvalidArgument; - } - - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; -#ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT - status = hashcrypt_sha_check_context(base, ctxInternal); - if (kStatus_Success != status) - { - return status; - } -#endif /* HASHCRYPT_SHA_DO_CHECK_CONTEXT */ - - if (ctxInternal->state == kHASHCRYPT_HashInit) - { - hashcrypt_engine_init(base, ctxInternal->algo); - } - else - { - hashcrypt_restore_running_hash(base, ctxInternal); - } - - size_t outSize = 0u; - - /* compute algorithm output length */ - switch (ctxInternal->algo) - { - case kHASHCRYPT_Sha1: - outSize = (size_t)kHASHCRYPT_OutLenSha1; - break; - case kHASHCRYPT_Sha256: - outSize = (size_t)kHASHCRYPT_OutLenSha256; - break; - default: - /* All the cases have been listed above, the default clause should not be reached. */ - break; - } - algOutSize = outSize; - - /* flush message last incomplete block, if there is any, and add padding bits */ - status = hashcrypt_sha_finalize(base, ctxInternal); - - if (outputSize != NULL) - { - if (algOutSize < *outputSize) - { - *outputSize = algOutSize; - } - else - { - algOutSize = *outputSize; - } - } - - hashcrypt_get_data(base, (uint32_t *)(uintptr_t)output, algOutSize); - -#ifdef HASHCRYPT_SHA_DO_WIPE_CONTEXT - ctxW = (uint32_t *)ctx; - for (i = 0; i < HASHCRYPT_HASH_CTX_SIZE; i++) - { - ctxW[i] = 0u; - } -#endif /* HASHCRYPT_SHA_DO_WIPE_CONTEXT */ - return status; -} - -void HASHCRYPT_SHA_SetCallback(HASHCRYPT_Type *base, - hashcrypt_hash_ctx_t *ctx, - hashcrypt_callback_t callback, - void *userData) -{ - hashcrypt_sha_ctx_internal_t *ctxInternal; - - s_ctx = ctx; - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; - ctxInternal->hashCallback = callback; - ctxInternal->userData = userData; - - (void)EnableIRQ(HASHCRYPT_IRQn); -} - -status_t HASHCRYPT_SHA_UpdateNonBlocking(HASHCRYPT_Type *base, - hashcrypt_hash_ctx_t *ctx, - const uint8_t *input, - size_t inputSize) -{ - hashcrypt_sha_ctx_internal_t *ctxInternal; - uint32_t numBlocks; - status_t status; - - if (inputSize == 0U) - { - return kStatus_Success; - } - - if (0U != ((uintptr_t)input & 0x3U)) - { - return kStatus_Fail; - } - - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; - status = hashcrypt_sha_check_context(base, ctxInternal); - if (kStatus_Success != status) - { - return status; - } - - ctxInternal->fullMessageSize = inputSize; - ctxInternal->remainingBlcks = inputSize / SHA_BLOCK_SIZE; - ctxInternal->blksz = inputSize % SHA_BLOCK_SIZE; - - /* copy last incomplete block to context */ - if ((ctxInternal->blksz > 0U) && (ctxInternal->blksz <= SHA_BLOCK_SIZE)) - { - (void)hashcrypt_memcpy((&ctxInternal->blk.b[0]), input + SHA_BLOCK_SIZE * ctxInternal->remainingBlcks, - ctxInternal->blksz); - } - - if (ctxInternal->remainingBlcks >= SHA_MASTER_MAX_BLOCKS) - { - numBlocks = SHA_MASTER_MAX_BLOCKS - 1U; - } - else - { - numBlocks = ctxInternal->remainingBlcks; - } - /* update remainingBlks so that ISR can run another hash if necessary */ - ctxInternal->remainingBlcks -= numBlocks; - - /* compute hash using AHB Master mode for full blocks */ - if (numBlocks > 0U) - { - ctxInternal->state = kHASHCRYPT_HashUpdate; - hashcrypt_engine_init(base, ctxInternal->algo); - - /* Enable digest and error interrupts and start hash */ - base->INTENSET = HASHCRYPT_INTENCLR_DIGEST_MASK | HASHCRYPT_INTENCLR_ERROR_MASK; - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(input); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(numBlocks); - } - /* no full blocks, invoke callback directly */ - else - { - ctxInternal->hashCallback(HASHCRYPT, ctx, status, ctxInternal->userData); - } - - return status; -} - -status_t HASHCRYPT_AES_SetKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *key, size_t keySize) -{ - status_t retVal = kStatus_InvalidArgument; - - switch (keySize) - { - case 16: - handle->keySize = kHASHCRYPT_Aes128; - break; - case 24: - handle->keySize = kHASHCRYPT_Aes192; - break; - case 32: - handle->keySize = kHASHCRYPT_Aes256; - break; - default: - handle->keySize = kHASHCRYPT_InvalidKey; - break; - } - - if (handle->keySize == kHASHCRYPT_InvalidKey) - { - return retVal; - } - - if (handle->keyType == kHASHCRYPT_SecretKey) - { - /* for kHASHCRYPT_SecretKey just return Success */ - retVal = kStatus_Success; - } - else if (handle->keyType == kHASHCRYPT_UserKey) - { - retVal = hashcrypt_get_key_from_unaligned_src((uint8_t *)&handle->keyWord[0], key, keySize); - } - else - { - retVal = kStatus_InvalidArgument; - } - - return retVal; -} - -status_t HASHCRYPT_AES_EncryptEcb( - HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size) -{ - status_t status = kStatus_Fail; - - if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesEcb) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load message and get result */ - status = hashcrypt_aes_one_block(base, plaintext, ciphertext, size); - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - - return status; -} - -status_t HASHCRYPT_AES_DecryptEcb( - HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size) -{ - status_t status = kStatus_Fail; - - if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesEcb) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_DECRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load message and get result */ - status = hashcrypt_aes_one_block(base, ciphertext, plaintext, size); - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -status_t HASHCRYPT_AES_EncryptCbc(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t iv[16]) -{ - status_t status = kStatus_Fail; - - if (0U != ((size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load 16b iv */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, 16); - - /* load message and get result */ - status = hashcrypt_aes_one_block(base, plaintext, ciphertext, size); - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -status_t HASHCRYPT_AES_DecryptCbc(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t iv[16]) -{ - status_t status = kStatus_Fail; - - if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_DECRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load iv */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, 16); - - /* load message and get result */ - status = hashcrypt_aes_one_block(base, ciphertext, plaintext, size); - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *input, - uint8_t *output, - size_t size, - uint8_t counter[HASHCRYPT_AES_BLOCK_SIZE], - uint8_t counterlast[HASHCRYPT_AES_BLOCK_SIZE], - size_t *szLeft) -{ - uint32_t lastSize; - uint8_t lastBlock[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - uint8_t *lastEncryptedCounter; - status_t status = kStatus_Fail; - - if (handle->keySize == kHASHCRYPT_InvalidKey) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCtr) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load nonce */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)counter, 16); - - lastSize = size % HASHCRYPT_AES_BLOCK_SIZE; - size -= lastSize; - - /* encrypt full 16byte blocks */ - status = hashcrypt_aes_one_block(base, input, output, size); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - - while (size != 0U) - { - ctrIncrement(counter); - size -= 16u; - input += 16; - output += 16; - } - - if (lastSize != 0U) - { - if (counterlast != NULL) - { - lastEncryptedCounter = counterlast; - } - else - { - lastEncryptedCounter = lastBlock; - } - - /* Perform encryption with all zeros to get last counter. XOR with zeros doesn't change. */ - status = hashcrypt_aes_one_block(base, lastBlock, lastEncryptedCounter, HASHCRYPT_AES_BLOCK_SIZE); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* remain output = input XOR counterlast */ - for (uint32_t i = 0; i < lastSize; i++) - { - output[i] = input[i] ^ lastEncryptedCounter[i]; - } - /* Increment counter parameter */ - ctrIncrement(counter); - } - else - { - lastSize = HASHCRYPT_AES_BLOCK_SIZE; - /* no remaining bytes in couterlast so clearing it */ - if (counterlast != NULL) - { - (void)memset(counterlast, 0, HASHCRYPT_AES_BLOCK_SIZE); - } - } - - if (szLeft != NULL) - { - *szLeft = HASHCRYPT_AES_BLOCK_SIZE - lastSize; - } - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return kStatus_Success; -} - -status_t HASHCRYPT_AES_CryptOfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *input, - uint8_t *output, - size_t size, - const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]) -{ - status_t status = kStatus_Fail; - uint8_t zeroes[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - uint8_t blockOutput[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - - if (handle->keySize == kHASHCRYPT_InvalidKey) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load iv */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, HASHCRYPT_AES_BLOCK_SIZE); - - /*Use AES CBC mode and feed input with zeroes as input*/ - /*Output block is then XORed with input*/ - - while (size >= 16u) - { - status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* XOR input with output block to get output*/ - for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) - { - output[i] = input[i] ^ blockOutput[i]; - } - size -= 16u; - output += 16; - input += 16; - } - - /* OFB can have non-block multiple size.*/ - if (size != 0U) - { - status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - - /* XOR input with output block to get output*/ - for (uint32_t i = 0; i < size; i++) - { - output[i] = input[i] ^ blockOutput[i]; - } - } - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -status_t HASHCRYPT_AES_EncryptCfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]) -{ - status_t status = kStatus_Fail; - uint8_t zeroes[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - uint8_t blockOutput[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - - /* For CFB mode size must be 16-byte multiple */ - if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load iv */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, HASHCRYPT_AES_BLOCK_SIZE); - - /*Use AES CBC mode and feed input with zeroes for first block */ - /*Output block is then XORed with plaintext to get ciphertext*/ - - status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* XOR plaintext with output block to get ciphertext*/ - for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) - { - ciphertext[i] = plaintext[i] ^ blockOutput[i]; - } - size -= 16u; - - /*Remaining blocks use previous plaintext as input for aes block function */ - while (size >= 16u) - { - status = hashcrypt_aes_one_block(base, plaintext, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - ciphertext += 16; - plaintext += 16; - - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* XOR plaintext with output block to get ciphertext*/ - for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) - { - ciphertext[i] = plaintext[i] ^ blockOutput[i]; - } - size -= 16u; - } - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -status_t HASHCRYPT_AES_DecryptCfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]) -{ - status_t status = kStatus_Fail; - uint8_t zeroes[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - uint8_t blockOutput[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - - /* For CFB mode size must be 16-byte multiple */ - if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; - - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* in case of HW AES key, check if it is available */ - if (hashcrypt_check_need_key(base, handle) != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return kStatus_Fail; - } - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load iv */ - hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, HASHCRYPT_AES_BLOCK_SIZE); - - /*Use AES CBC mode and feed input with zeroes for first block */ - /*Output block is then XORed with ciphertext to get plaintext*/ - - status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* XOR ciphertext with output block to get plaintext*/ - for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) - { - plaintext[i] = ciphertext[i] ^ blockOutput[i]; - } - size -= 16u; - - /*Remaining blocks use previous plaintext as input for aes block function */ - while (size >= 16u) - { - status = hashcrypt_aes_one_block(base, plaintext, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); - ciphertext += 16; - plaintext += 16; - - if (status != kStatus_Success) - { - hashcrypt_engine_deinit(base); - return status; - } - /* XOR plaintext with ciphertext block to get plaintext*/ - for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) - { - plaintext[i] = ciphertext[i] ^ blockOutput[i]; - } - size -= 16u; - } - - /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ - hashcrypt_engine_deinit(base); - return status; -} - -void HASHCRYPT_DriverIRQHandler(void); -void HASHCRYPT_DriverIRQHandler(void) -{ - hashcrypt_sha_ctx_internal_t *ctxInternal; - HASHCRYPT_Type *base = HASHCRYPT; - uint32_t numBlocks; - status_t status; - - ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)s_ctx; - - if (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) - { - if (ctxInternal->remainingBlcks > 0U) - { - if (ctxInternal->remainingBlcks >= SHA_MASTER_MAX_BLOCKS) - { - numBlocks = SHA_MASTER_MAX_BLOCKS - 1U; - } - else - { - numBlocks = ctxInternal->remainingBlcks; - } - /* some blocks still remaining, update remainingBlcks for next ISR and start another hash */ - ctxInternal->remainingBlcks -= numBlocks; - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(numBlocks); - return; - } - /* no full blocks left, disable interrupts and AHB master mode */ - base->INTENCLR = HASHCRYPT_INTENCLR_DIGEST_MASK | HASHCRYPT_INTENCLR_ERROR_MASK; - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(0); - hashcrypt_save_running_hash(base, ctxInternal); - status = kStatus_Success; - } - else - { - status = kStatus_Fail; - } - - /* Invoke callback if there is one */ - if (NULL != ctxInternal->hashCallback) - { - ctxInternal->hashCallback(HASHCRYPT, s_ctx, status, ctxInternal->userData); - } -} - -void HASHCRYPT_Init(HASHCRYPT_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_HashCrypt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - RESET_PeripheralReset(kHASHCRYPT_RST_SHIFT_RSTn); -} - -void HASHCRYPT_Deinit(HASHCRYPT_Type *base) -{ - RESET_SetPeripheralReset(kHASHCRYPT_RST_SHIFT_RSTn); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_HashCrypt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.h deleted file mode 100644 index 1aa78d5959b..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.h +++ /dev/null @@ -1,528 +0,0 @@ -/* - * Copyright 2017-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_HASHCRYPT_H_ -#define _FSL_HASHCRYPT_H_ - -#include "fsl_common.h" - -/*! @brief HASHCRYPT status return codes. */ -enum _hashcrypt_status -{ - kStatus_HASHCRYPT_Again = - MAKE_STATUS(kStatusGroup_HASHCRYPT, 0), /*!< Non-blocking function shall be called again. */ -}; - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! - * @addtogroup hashcrypt_driver - * @{ - */ -/*! @name Driver version */ -/*@{*/ -/*! @brief HASHCRYPT driver version. Version 2.2.5. - * - * Current version: 2.2.5 - * - * Change log: - * - Version 2.0.0 - * - Initial version - * - Version 2.0.1 - * - Support loading AES key from unaligned address - * - Version 2.0.2 - * - Support loading AES key from unaligned address for different compiler and core variants - * - Version 2.0.3 - * - Remove SHA512 and AES ICB algorithm definitions - * - Version 2.0.4 - * - Add SHA context switch support - * - Version 2.1.0 - * - Update the register name and macro to align with new header. - * - Version 2.1.1 - * - Fix MISRA C-2012. - * - Version 2.1.2 - * - Support loading AES input data from unaligned address. - * - Version 2.1.3 - * - Fix MISRA C-2012. - * - Version 2.1.4 - * - Fix context switch cannot work when switching from AES. - * - Version 2.1.5 - * - Add data synchronization barriere inside hashcrypt_sha_ldm_stm_16_words() - * to prevent possible optimization issue. - * - Version 2.2.0 - * - Add AES-OFB and AES-CFB mixed IP/SW modes. - * - Version 2.2.1 - * - Add data synchronization barrier inside hashcrypt_sha_ldm_stm_16_words() - * prevent compiler from reordering memory write when -O2 or higher is used. - * - Version 2.2.2 - * - Add data synchronization barrier inside hashcrypt_sha_ldm_stm_16_words() - * to fix optimization issue - * - Version 2.2.3 - * - Added check for size in hashcrypt_aes_one_block to prevent overflowing COUNT field in MEMCTRL register, if its - * bigger than COUNT field do a multiple runs. - * - Version 2.2.4 - * - In all HASHCRYPT_AES_xx functions have been added setting CTRL_MODE bitfield to 0 after processing data, which - * decreases power consumption. - * - Version 2.2.5 - * - Add data synchronization barrier and instruction synchronization barrier inside - * hashcrypt_sha_process_message_data() to fix optimization issue - */ -#define FSL_HASHCRYPT_DRIVER_VERSION (MAKE_VERSION(2, 2, 5)) -/*@}*/ - -/*! @brief Algorithm definitions correspond with the values for Mode field in Control register !*/ -#define HASHCRYPT_MODE_SHA1 0x1 -#define HASHCRYPT_MODE_SHA256 0x2 -#define HASHCRYPT_MODE_AES 0x4 - -/*! @brief Algorithm used for Hashcrypt operation */ -typedef enum _hashcrypt_algo_t -{ - kHASHCRYPT_Sha1 = HASHCRYPT_MODE_SHA1, /*!< SHA_1 */ - kHASHCRYPT_Sha256 = HASHCRYPT_MODE_SHA256, /*!< SHA_256 */ - kHASHCRYPT_Aes = HASHCRYPT_MODE_AES, /*!< AES */ -} hashcrypt_algo_t; - -/*! @} */ - -/******************************************************************************* - * AES Definitions - *******************************************************************************/ - -/*! - * @addtogroup hashcrypt_driver_aes - * @{ - */ - -/*! AES block size in bytes */ -#define HASHCRYPT_AES_BLOCK_SIZE 16U -#define AES_ENCRYPT 0 -#define AES_DECRYPT 1 - -/*! @brief AES mode */ -typedef enum _hashcrypt_aes_mode_t -{ - kHASHCRYPT_AesEcb = 0U, /*!< AES ECB mode */ - kHASHCRYPT_AesCbc = 1U, /*!< AES CBC mode */ - kHASHCRYPT_AesCtr = 2U, /*!< AES CTR mode */ -} hashcrypt_aes_mode_t; - -/*! @brief Size of AES key */ -typedef enum _hashcrypt_aes_keysize_t -{ - kHASHCRYPT_Aes128 = 0U, /*!< AES 128 bit key */ - kHASHCRYPT_Aes192 = 1U, /*!< AES 192 bit key */ - kHASHCRYPT_Aes256 = 2U, /*!< AES 256 bit key */ - kHASHCRYPT_InvalidKey = 3U, /*!< AES invalid key */ -} hashcrypt_aes_keysize_t; - -/*! @brief HASHCRYPT key source selection. - * - */ -typedef enum _hashcrypt_key -{ - kHASHCRYPT_UserKey = 0xc3c3U, /*!< HASHCRYPT user key */ - kHASHCRYPT_SecretKey = 0x3c3cU, /*!< HASHCRYPT secret key (dedicated hw bus from PUF) */ -} hashcrypt_key_t; - -/*! @brief Specify HASHCRYPT's key resource. */ -struct _hashcrypt_handle -{ - uint32_t keyWord[8]; /*!< Copy of user key (set by HASHCRYPT_AES_SetKey(). */ - hashcrypt_aes_keysize_t keySize; - hashcrypt_key_t keyType; /*!< For operations with key (such as AES encryption/decryption), specify key type. */ -} __attribute__((aligned)); - -typedef struct _hashcrypt_handle hashcrypt_handle_t; - -/*! - *@} - */ /* end of hashcrypt_driver_aes */ - -/******************************************************************************* - * HASH Definitions - ******************************************************************************/ -/*! - * @addtogroup hashcrypt_driver_hash - * @{ - */ - -/*! @brief HASHCRYPT HASH Context size. */ -#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) -#define HASHCRYPT_HASH_CTX_SIZE 30 -#else -#define HASHCRYPT_HASH_CTX_SIZE 22 -#endif - -/*! @brief Storage type used to save hash context. */ -typedef struct _hashcrypt_hash_ctx_t -{ - uint32_t x[HASHCRYPT_HASH_CTX_SIZE]; /*!< storage */ -} hashcrypt_hash_ctx_t; - -/*! @brief HASHCRYPT background hash callback function. */ -typedef void (*hashcrypt_callback_t)(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, status_t status, void *userData); - -/*! - *@} - */ /* end of hashcrypt_driver_hash */ - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup hashcrypt_driver - * @{ - */ - -/*! - * @brief Enables clock and disables reset for HASHCRYPT peripheral. - * - * Enable clock and disable reset for HASHCRYPT. - * - * @param base HASHCRYPT base address - */ -void HASHCRYPT_Init(HASHCRYPT_Type *base); - -/*! - * @brief Disables clock for HASHCRYPT peripheral. - * - * Disable clock and enable reset. - * - * @param base HASHCRYPT base address - */ -void HASHCRYPT_Deinit(HASHCRYPT_Type *base); - -/*! - *@} - */ /* end of hashcrypt_driver */ - -/******************************************************************************* - * AES API - ******************************************************************************/ - -/*! - * @addtogroup hashcrypt_driver_aes - * @{ - */ - -/*! - * @brief Set AES key to hashcrypt_handle_t struct and optionally to HASHCRYPT. - * - * Sets the AES key for encryption/decryption with the hashcrypt_handle_t structure. - * The hashcrypt_handle_t input argument specifies key source. - * - * @param base HASHCRYPT peripheral base address. - * @param handle Handle used for the request. - * @param key 0-mod-4 aligned pointer to AES key. - * @param keySize AES key size in bytes. Shall equal 16, 24 or 32. - * @return status from set key operation - */ -status_t HASHCRYPT_AES_SetKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *key, size_t keySize); - -/*! - * @brief Encrypts AES on one or multiple 128-bit block(s). - * - * Encrypts AES. - * The source plaintext and destination ciphertext can overlap in system memory. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @return Status from encrypt operation - */ -status_t HASHCRYPT_AES_EncryptEcb( - HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size); - -/*! - * @brief Decrypts AES on one or multiple 128-bit block(s). - * - * Decrypts AES. - * The source ciphertext and destination plaintext can overlap in system memory. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param ciphertext Input plain text to encrypt - * @param[out] plaintext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @return Status from decrypt operation - */ -status_t HASHCRYPT_AES_DecryptEcb( - HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size); - -/*! - * @brief Encrypts AES using CBC block mode. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return Status from encrypt operation - */ -status_t HASHCRYPT_AES_EncryptCbc(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t iv[16]); - -/*! - * @brief Decrypts AES using CBC block mode. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param ciphertext Input cipher text to decrypt - * @param[out] plaintext Output plain text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return Status from decrypt operation - */ -status_t HASHCRYPT_AES_DecryptCbc(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t iv[16]); - -/*! - * @brief Encrypts or decrypts AES using CTR block mode. - * - * Encrypts or decrypts AES using CTR block mode. - * AES CTR mode uses only forward AES cipher and same algorithm for encryption and decryption. - * The only difference between encryption and decryption is that, for encryption, the input argument - * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text - * and the output argument is plain text. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param input Input data for CTR block mode - * @param[out] output Output data for CTR block mode - * @param size Size of input and output data in bytes - * @param[in,out] counter Input counter (updates on return) - * @param[out] counterlast Output cipher of last counter, for chained CTR calls (statefull encryption). NULL can be - * passed if chained calls are - * not used. - * @param[out] szLeft Output number of bytes in left unused in counterlast block. NULL can be passed if chained calls - * are not used. - * @return Status from encrypt operation - */ -status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *input, - uint8_t *output, - size_t size, - uint8_t counter[HASHCRYPT_AES_BLOCK_SIZE], - uint8_t counterlast[HASHCRYPT_AES_BLOCK_SIZE], - size_t *szLeft); - -/*! - * @brief Encrypts or decrypts AES using OFB block mode. - * - * Encrypts or decrypts AES using OFB block mode. - * AES OFB mode uses only forward AES cipher and same algorithm for encryption and decryption. - * The only difference between encryption and decryption is that, for encryption, the input argument - * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text - * and the output argument is plain text. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param input Input data for OFB block mode - * @param[out] output Output data for OFB block mode - * @param size Size of input and output data in bytes - * @param iv Input initial vector to combine with the first input block. - * @return Status from encrypt operation - */ - -status_t HASHCRYPT_AES_CryptOfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *input, - uint8_t *output, - size_t size, - const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]); - -/*! - * @brief Encrypts AES using CFB block mode. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return Status from encrypt operation - */ - -status_t HASHCRYPT_AES_EncryptCfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t iv[16]); - -/*! - * @brief Decrypts AES using CFB block mode. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param ciphertext Input cipher text to decrypt - * @param[out] plaintext Output plaintext text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return Status from encrypt operation - */ - -status_t HASHCRYPT_AES_DecryptCfb(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t iv[16]); -/*! - *@} - */ /* end of hashcrypt_driver_aes */ - -/******************************************************************************* - * HASH API - ******************************************************************************/ - -/*! - * @addtogroup hashcrypt_driver_hash - * @{ - */ - -/*! - * @brief Create HASH on given data - * - * Perform the full SHA in one function call. The function is blocking. - * - * @param base HASHCRYPT peripheral base address - * @param algo Underlaying algorithm to use for hash computation. - * @param input Input data - * @param inputSize Size of input data in bytes - * @param[out] output Output hash data - * @param[out] outputSize Output parameter storing the size of the output hash in bytes - * @return Status of the one call hash operation. - */ -status_t HASHCRYPT_SHA(HASHCRYPT_Type *base, - hashcrypt_algo_t algo, - const uint8_t *input, - size_t inputSize, - uint8_t *output, - size_t *outputSize); - -/*! - * @brief Initialize HASH context - * - * This function initializes the HASH. - * - * @param base HASHCRYPT peripheral base address - * @param[out] ctx Output hash context - * @param algo Underlaying algorithm to use for hash computation. - * @return Status of initialization - */ -status_t HASHCRYPT_SHA_Init(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo); - -/*! - * @brief Add data to current HASH - * - * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be - * hashed. The functions blocks. If it returns kStatus_Success, the running hash - * has been updated (HASHCRYPT has processed the input data), so the memory at \p input pointer - * can be released back to system. The HASHCRYPT context buffer is updated with the running hash - * and with all necessary information to support possible context switch. - * - * @param base HASHCRYPT peripheral base address - * @param[in,out] ctx HASH context - * @param input Input data - * @param inputSize Size of input data in bytes - * @return Status of the hash update operation - */ -status_t HASHCRYPT_SHA_Update(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize); - -/*! - * @brief Finalize hashing - * - * Outputs the final hash (computed by HASHCRYPT_HASH_Update()) and erases the context. - * - * @param base HASHCRYPT peripheral base address - * @param[in,out] ctx Input hash context - * @param[out] output Output hash data - * @param[in,out] outputSize Optional parameter (can be passed as NULL). On function entry, it specifies the size of - * output[] buffer. On function return, it stores the number of updated output bytes. - * @return Status of the hash finish operation - */ -status_t HASHCRYPT_SHA_Finish(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize); - -/*! - *@} - */ /* end of hashcrypt_driver_hash */ - -/*! - * @addtogroup hashcrypt_background_driver_hash - * @{ - */ - -/*! - * @brief Initializes the HASHCRYPT handle for background hashing. - * - * This function initializes the hash context for background hashing - * (Non-blocking) APIs. This is less typical interface to hash function, but can be used - * for parallel processing, when main CPU has something else to do. - * Example is digital signature RSASSA-PKCS1-V1_5-VERIFY((n,e),M,S) algorithm, where - * background hashing of M can be started, then CPU can compute S^e mod n - * (in parallel with background hashing) and once the digest becomes available, - * CPU can proceed to comparison of EM with EM'. - * - * @param base HASHCRYPT peripheral base address. - * @param[out] ctx Hash context. - * @param callback Callback function. - * @param userData User data (to be passed as an argument to callback function, once callback is invoked from isr). - */ -void HASHCRYPT_SHA_SetCallback(HASHCRYPT_Type *base, - hashcrypt_hash_ctx_t *ctx, - hashcrypt_callback_t callback, - void *userData); - -/*! - * @brief Create running hash on given data. - * - * Configures the HASHCRYPT to compute new running hash as AHB master - * and returns immediately. HASHCRYPT AHB Master mode supports only aligned \p input - * address and can be called only once per continuous block of data. Every call to this function - * must be preceded with HASHCRYPT_SHA_Init() and finished with HASHCRYPT_SHA_Finish(). - * Once callback function is invoked by HASHCRYPT isr, it should set a flag - * for the main application to finalize the hashing (padding) and to read out the final digest - * by calling HASHCRYPT_SHA_Finish(). - * - * @param base HASHCRYPT peripheral base address - * @param ctx Specifies callback. Last incomplete 512-bit block of the input is copied into clear buffer for padding. - * @param input 32-bit word aligned pointer to Input data. - * @param inputSize Size of input data in bytes (must be word aligned) - * @return Status of the hash update operation. - */ -status_t HASHCRYPT_SHA_UpdateNonBlocking(HASHCRYPT_Type *base, - hashcrypt_hash_ctx_t *ctx, - const uint8_t *input, - size_t inputSize); -/*! - *@} - */ /* end of hashcrypt_background_driver_hash */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_HASHCRYPT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c.c deleted file mode 100644 index 9ecde80c90a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c.c +++ /dev/null @@ -1,2085 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_i2c.h" -#include "fsl_flexcomm.h" -#include -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c" -#endif - -/*! @brief Common sets of flags used by the driver's transactional layer internally. */ -enum _i2c_flag_constants -{ - kI2C_MasterIrqFlags = I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | - I2C_INTSTAT_EVENTTIMEOUT_MASK | I2C_INTSTAT_SCLTIMEOUT_MASK, - kI2C_SlaveIrqFlags = I2C_INTSTAT_SLVPENDING_MASK | I2C_INTSTAT_SLVDESEL_MASK, -}; - -/*! - * @brief Used for conversion from `flexcomm_irq_handler_t` to `flexcomm_i2c_master_irq_handler_t` and - * `flexcomm_i2c_slave_irq_handler_t`. - */ -typedef union i2c_to_flexcomm -{ - flexcomm_i2c_master_irq_handler_t i2c_master_handler; - flexcomm_i2c_slave_irq_handler_t i2c_slave_handler; - flexcomm_irq_handler_t flexcomm_handler; -} i2c_to_flexcomm_t; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Waits for Master Pending status bit to set and check for bus error status. - * - * @param base The I2C peripheral base address. - * @return Bus status. - */ -static status_t I2C_PendingStatusWait(I2C_Type *base); - -/*! - * @brief Prepares the transfer state machine and fills in the command buffer. - * @param base The I2C peripheral base address. - * @param handle Master nonblocking driver handle. - * @param xfer The I2C transfer configuration structure. - */ -static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Resets the slave hardware state machine. - * According to documentation, after disabling slave to rest the slave hardware state machine, the register - * configuration remains unchanged. - * @param base The I2C peripheral base address. - */ -static void I2C_SlaveInternalStateMachineReset(I2C_Type *base); - -/*! - * @brief Compute CLKDIV - * - * This function computes CLKDIV value according to the given bus speed and Flexcomm source clock frequency. - * This setting is used by hardware during slave clock stretching. - * - * @param base The I2C peripheral base address. - * @return status of the operation - */ -static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal); - -/*! - * @brief Poll wait for the SLVPENDING flag. - * - * Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register. - * - * @param base The I2C peripheral base address. - * @return status register at time the SLVPENDING bit is read as set - */ -static uint32_t I2C_SlavePollPending(I2C_Type *base); - -/*! - * @brief Invoke event from I2C_SlaveTransferHandleIRQ(). - * - * Sets the event type to transfer structure and invokes the event callback, if it has been - * enabled by eventMask. - * - * @param base The I2C peripheral base address. - * @param handle The I2C slave handle for non-blocking APIs. - * @param event The I2C slave event to invoke. - */ -static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event); - -/*! - * @brief Handle slave address match event. - * - * Called by Slave interrupt routine to ACK or NACK the matched address. - * It also determines master direction (read or write). - * - * @param base The I2C peripheral base address. - * @return true if the matched address is ACK'ed - * @return false if the matched address is NACK'ed - */ -static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle); - -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. - * @param txData Data to be transmitted to master in response to master read from slave requests. NULL if slave RX only. - * @param txSize Size of txData buffer in bytes. - * @param rxData Data where received data from master will be stored in response to master write to slave requests. NULL - * if slave TX only. - * @param rxSize Size of rxData buffer in bytes. - * @retval #kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, - i2c_slave_handle_t *handle, - const void *txData, - size_t txSize, - void *rxData, - size_t rxSize, - uint32_t eventMask); - -/*! - * @brief Execute master transfer software state machine until FIFOs are exhausted. - * - * For master transmit, the states would be kStartState->kTransmitSubaddrState->kTransmitDataState->kStopState - * For master receive, the states would be kStartState->kTransmitSubaddrState->kStartState->kReceiveDataState-> - * kWaitForCompletionState - * - * @param handle Master nonblocking driver handle. - * @param[out] isDone Set to true if the transfer has completed. - * @retval #kStatus_Success - * @retval #kStatus_I2C_ArbitrationLost - * @retval #kStatus_I2C_Nak - */ -static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone); - -/*! - * @brief Checks the slave response to master's start signal. - * - * @param base I2C peripheral base address. - * @retval kStatus_Success Successfully complete the data transmission. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStataus_I2C_Nak Transfer error, receive NAK during addressing. - */ -static status_t I2C_MasterCheckStartResponse(I2C_Type *base); -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map i2c instance number to base address. */ -static const uint32_t s_i2cBaseAddrs[FSL_FEATURE_SOC_I2C_COUNT] = I2C_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_i2cIRQ[] = I2C_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * param base The I2C peripheral base address. - * return I2C instance number starting from 0. - */ -uint32_t I2C_GetInstance(I2C_Type *base) -{ - uint32_t i; - for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_I2C_COUNT; i++) - { - if ((uint32_t)base == s_i2cBaseAddrs[i]) - { - break; - } - } - assert(i < (uint32_t)FSL_FEATURE_SOC_I2C_COUNT); - return i; -} - -/*! - * brief Provides a default configuration for the I2C master peripheral. - * - * This function provides the following default configuration for the I2C master peripheral: - * code - * masterConfig->enableMaster = true; - * masterConfig->baudRate_Bps = 100000U; - * masterConfig->enableTimeout = false; - * endcode - * - * After calling this function, you can override any settings in order to customize the configuration, - * prior to initializing the master driver with I2C_MasterInit(). - * - * param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. - */ -void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) -{ - /* Initializes the configure structure to zero. */ - (void)memset(masterConfig, 0, sizeof(*masterConfig)); - - masterConfig->enableMaster = true; - masterConfig->baudRate_Bps = 100000U; - masterConfig->enableTimeout = false; - masterConfig->timeout_Ms = 35; -} - -/*! - * brief Initializes the I2C master peripheral. - * - * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user - * provided configuration. A software reset is performed prior to configuration. - * - * param base The I2C peripheral base address. - * param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of - * defaults - * that you can override. - * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, - * filter widths, and timeout periods. - */ -void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) -{ - (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); - I2C_MasterEnable(base, masterConfig->enableMaster); - I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); - I2C_MasterSetTimeoutValue(base, masterConfig->timeout_Ms, srcClock_Hz); -} - -/*! - * brief Deinitializes the I2C master peripheral. - * - * This function disables the I2C master peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * param base The I2C peripheral base address. - */ -void I2C_MasterDeinit(I2C_Type *base) -{ - I2C_MasterEnable(base, false); -} - -/*! - * brief Gets the I2C status flags. - * - * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit - * in the return value is set if the flag is asserted. - * - * param base The I2C peripheral base address. - * return State of the status flags: - * - 1: related status flag is set. - * - 0: related status flag is not set. - * see ref _i2c_status_flags, ref _i2c_master_status_flags and ref _i2c_slave_status_flags. - */ -uint32_t I2C_GetStatusFlags(I2C_Type *base) -{ - uint32_t statusMask = base->STAT; - if ((statusMask & (uint32_t)I2C_STAT_MSTSTATE_MASK) == 0UL) - { - statusMask |= (uint32_t)kI2C_MasterIdleFlag; - } - if (((statusMask & (uint32_t)I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == 3UL) - { - statusMask = (statusMask & ~(uint32_t)I2C_STAT_MSTSTATE_MASK) | (uint32_t)kI2C_MasterAddrNackFlag; - } - if ((statusMask & (uint32_t)I2C_STAT_SLVSTATE_MASK) == 0UL) - { - statusMask |= (uint32_t)kI2C_SlaveAddressedFlag; - } - if ((statusMask & (uint32_t)I2C_STAT_SLVIDX_MASK) == 0UL) - { - statusMask |= (uint32_t)kI2C_SlaveAddress0MatchFlag; - } - if (((statusMask & (uint32_t)I2C_STAT_SLVIDX_MASK) >> I2C_STAT_SLVIDX_SHIFT) == 3UL) - { - statusMask = (statusMask & ~(uint32_t)I2C_STAT_SLVIDX_MASK) | (uint32_t)kI2C_SlaveAddress3MatchFlag; - } - return statusMask; -} - -/*! - * brief Sets the I2C bus frequency for master transactions. - * - * The I2C master is automatically disabled and re-enabled as necessary to configure the baud - * rate. Do not call this function during a transfer, or the transfer is aborted. - * - * param base The I2C peripheral base address. - * param srcClock_Hz I2C functional clock frequency in Hertz. - * param baudRate_Bps Requested bus frequency in bits per second. - */ -void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) -{ - uint32_t scl, divider; - uint32_t mindivider; - uint32_t err, best_err; - uint32_t best_scl = 0U; - uint32_t best_div = 0U; - -#if defined(FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) && (FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) - /* - * RFT1717/RFT1437: workaround for hardware bug when using DMA - * I2C peripheral clock frequency has to be fixed at 8MHz - * source clock is 32MHz or 48MHz so divider is a round integer value - */ - best_div = srcClock_Hz / 8000000U; - best_scl = 8000000U / baudRate_Bps; - - if ((8000000U / best_scl - baudRate_Bps) > (baudRate_Bps - (8000000U / (best_scl + 1U)))) - { - best_scl = best_scl + 1U; - } - - /* - * Fallback to usual baudrate computation method, when: - * 1.Master SCL frequency does not fit in workaround range, - * 2.User's setting of baudRate_Bps is 400kHz while the clock frequency after divval is larger than 2MHz - */ - if ((best_scl > 18U) || ((best_scl < 4U)) || ((baudRate_Bps == 400000U) && (srcClock_Hz / best_div > 2000000U))) - { -#endif /*FSL_FEATURE_I2C_PREPCLKFRG_8MHZ*/ - - /* Calculate the minimal divider value to make sure the clock frequency after divval is not larger than 2MHz */ - /* This is required in RM in order to generate 400kHz baudrate */ - mindivider = ((srcClock_Hz * 10U) / 2000000U + 5U) / 10U; - /* If the scl value with current mindivider is smaller than 4, which is the minimal value register can achieve, - update mindivider */ - if ((srcClock_Hz / mindivider / baudRate_Bps) < 4U) - { - mindivider = srcClock_Hz / 4U / baudRate_Bps; - } - /* Calculate the ideal div and scl value*/ - best_err = 0U; - for (divider = mindivider; divider <= 0x10000U; divider++) - { - /* Calculte ideal scl value, round up the value */ - scl = ((srcClock_Hz * 10U) / (divider * baudRate_Bps) + 5U) / 10U; - - /* adjust it if it is out of range */ - scl = (scl > 18U) ? 18U : scl; - - /* calculate error */ - err = srcClock_Hz - (baudRate_Bps * scl * divider); - if ((err < best_err) || (best_err == 0U)) - { - best_div = divider; - best_scl = scl; - best_err = err; - } - - if ((err == 0U) || (scl <= 4U)) - { - /* either exact value was found - or scl is at its min (it would be even smaller in the next iteration for sure) */ - break; - } - } -#if defined(FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) && (FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) - } -#endif /*FSL_FEATURE_I2C_PREPCLKFRG_8MHZ*/ - base->CLKDIV = I2C_CLKDIV_DIVVAL(best_div - 1U); - if (best_scl % 2U == 0U) - { - base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl / 2U - 2U) | I2C_MSTTIME_MSTSCLHIGH(best_scl / 2U - 2U); - } - else - { - base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl / 2U - 1U) | I2C_MSTTIME_MSTSCLHIGH(best_scl / 2U - 2U); - } -} - -/*! - * brief Sets the I2C bus timeout value. - * - * If the SCL signal remains low or bus does not have event longer than the timeout value, kI2C_SclTimeoutFlag or - * kI2C_EventTimeoutFlag is set. This can indicete the bus is held by slave or any fault occurs to the I2C module. - * - * param base The I2C peripheral base address. - * param timeout_Ms Timeout value in millisecond. - * param srcClock_Hz I2C functional clock frequency in Hertz. - */ -void I2C_MasterSetTimeoutValue(I2C_Type *base, uint8_t timeout_Ms, uint32_t srcClock_Hz) -{ - assert((timeout_Ms != 0U) && (srcClock_Hz != 0U)); - - /* The low 4 bits of the timout reister TIMEOUT is hard-wired to be 1, so the the time out value is always 16 times - the I2C functional clock, we only need to calculate the high bits. */ - uint32_t timeoutValue = ((uint32_t)timeout_Ms * srcClock_Hz / 16UL / 100UL + 5UL) / 10UL; - if (timeoutValue > 0x1000UL) - { - timeoutValue = 0x1000UL; - } - timeoutValue = ((timeoutValue - 1UL) << 4UL) | 0xFUL; - base->TIMEOUT = timeoutValue; -} - -static status_t I2C_PendingStatusWait(I2C_Type *base) -{ - status_t result = kStatus_Success; - uint32_t status; - -#if I2C_RETRY_TIMES != 0U - uint32_t waitTimes = I2C_RETRY_TIMES; -#endif - - do - { - status = I2C_GetStatusFlags(base); - if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) - { - result = kStatus_I2C_EventTimeout; - } - if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) - { - result = kStatus_I2C_SclLowTimeout; - } -#if defined(FSL_FEATURE_I2C_TIMEOUT_RECOVERY) && FSL_FEATURE_I2C_TIMEOUT_RECOVERY - if (result != kStatus_Success) - { - I2C_MasterEnable(base, false); - I2C_MasterEnable(base, true); - break; - } -#endif -#if I2C_RETRY_TIMES != 0U - waitTimes--; - } while (((status & (uint32_t)kI2C_MasterPendingFlag) == 0U) && (waitTimes != 0U)); - - if (waitTimes == 0U) - { -#if defined(FSL_FEATURE_I2C_TIMEOUT_RECOVERY) && FSL_FEATURE_I2C_TIMEOUT_RECOVERY - I2C_MasterEnable(base, false); - I2C_MasterEnable(base, true); -#endif - return kStatus_I2C_Timeout; - } -#else - } while ((status & (uint32_t)kI2C_MasterPendingFlag) == 0U); -#endif - - if ((status & (uint32_t)kI2C_MasterArbitrationLostFlag) != 0U) - { - result = kStatus_I2C_ArbitrationLost; - } - - if ((status & (uint32_t)kI2C_MasterStartStopErrorFlag) != 0U) - { - result = kStatus_I2C_StartStopError; - } - - /* Clear controller state. */ - I2C_ClearStatusFlags( - base, (uint32_t)kI2C_MasterAllClearFlags | (uint32_t)kI2C_EventTimeoutFlag | (uint32_t)kI2C_SclTimeoutFlag); - - return result; -} - -/*! - * brief Sends a START on the I2C bus. - * - * This function is used to initiate a new master mode transfer by sending the START signal. - * The slave address is sent following the I2C START signal. - * - * param base I2C peripheral base pointer - * param address 7-bit slave device address. - * param direction Master transfer directions(transmit/receive). - * retval kStatus_Success Successfully send the start signal. - * retval kStatus_I2C_Busy Current bus is busy. - */ -status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) -{ - status_t result; - result = I2C_PendingStatusWait(base); - if (result != kStatus_Success) - { - return result; - } - - /* Write Address and RW bit to data register */ - base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1U); - /* Start the transfer */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - - return kStatus_Success; -} - -/*! - * brief Sends a STOP signal on the I2C bus. - * - * retval kStatus_Success Successfully send the stop signal. - * retval kStatus_I2C_Timeout Send stop signal failed, timeout. - */ -status_t I2C_MasterStop(I2C_Type *base) -{ - status_t result = I2C_PendingStatusWait(base); - if (result != kStatus_Success) - { - return result; - } - - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - return kStatus_Success; -} - -/*! - * brief Performs a polling send transfer on the I2C bus. - * - * Sends up to a txSize number of bytes to the previously addressed slave device. The slave may - * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this - * function returns #kStatus_I2C_Nak. - * - * param base The I2C peripheral base address. - * param txBuff The pointer to the data to be transferred. - * param txSize The length in bytes of the data to be transferred. - * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * retval kStatus_Success Data was sent successfully. - * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags) -{ - uint32_t master_state; - status_t err; - - const uint8_t *buf = (const uint8_t *)txBuff; - - assert(txBuff != NULL); - - err = kStatus_Success; - while (txSize != 0U) - { - err = I2C_PendingStatusWait(base); - - if (err != kStatus_Success) - { - return err; - } - - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - switch (master_state) - { - case I2C_STAT_MSTCODE_TXREADY: - /* ready to send next byte */ - base->MSTDAT = *buf++; - txSize--; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - break; - - case I2C_STAT_MSTCODE_NACKADR: - case I2C_STAT_MSTCODE_NACKDAT: - err = kStatus_I2C_Nak; - /* Issue nack signal when nacked by slave. */ - (void)I2C_MasterStop(base); - break; - - default: - /* unexpected state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - if (err != kStatus_Success) - { - return err; - } - } - - err = I2C_PendingStatusWait(base); - - if (err != kStatus_Success) - { - return err; - } - -#if !I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK - /* Check nack signal. If master is nacked by slave of the last byte, return kStatus_I2C_Nak. */ - if (((base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == (uint32_t)I2C_STAT_MSTCODE_NACKDAT) - { - (void)I2C_MasterStop(base); - return kStatus_I2C_Nak; - } -#endif - - if (0U == (flags & (uint32_t)kI2C_TransferNoStopFlag)) - { - /* Initiate stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - err = I2C_PendingStatusWait(base); - if (err != kStatus_Success) - { - return err; - } - } - - return kStatus_Success; -} - -/*! - * brief Performs a polling receive transfer on the I2C bus. - * - * param base The I2C peripheral base address. - * param rxBuff The pointer to the data to be transferred. - * param rxSize The length in bytes of the data to be transferred. - * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * retval kStatus_Success Data was received successfully. - * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags) -{ - uint32_t master_state; - status_t err; - - uint8_t *buf = (uint8_t *)(rxBuff); - - assert(rxBuff != NULL); - - err = kStatus_Success; - while (rxSize != 0U) - { - err = I2C_PendingStatusWait(base); - - if (err != kStatus_Success) - { - return err; - } - - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - switch (master_state) - { - case I2C_STAT_MSTCODE_RXREADY: - /* ready to send next byte */ - *(buf++) = (uint8_t)base->MSTDAT; - if (--rxSize != 0U) - { - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - } - else - { - if ((flags & (uint32_t)kI2C_TransferNoStopFlag) == 0U) - { - /* initiate NAK and stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - err = I2C_PendingStatusWait(base); - } - } - break; - - case I2C_STAT_MSTCODE_NACKADR: - case I2C_STAT_MSTCODE_NACKDAT: - /* slave nacked the last byte */ - err = kStatus_I2C_Nak; - break; - - default: - /* unexpected state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - if (err != kStatus_Success) - { - return err; - } - } - - return kStatus_Success; -} - -static status_t I2C_MasterCheckStartResponse(I2C_Type *base) -{ - /* Wait for start signal to be transmitted. */ - status_t result = I2C_PendingStatusWait(base); - - if (result != kStatus_Success) - { - return result; - } - - if (((base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == I2C_STAT_MSTCODE_NACKADR) - { - (void)I2C_MasterStop(base); - return kStatus_I2C_Addr_Nak; - } - return kStatus_Success; -} - -/*! - * brief Performs a master polling transfer on the I2C bus. - * - * note The API does not return until the transfer succeeds or fails due - * to arbitration lost or receiving a NAK. - * - * param base I2C peripheral base address. - * param xfer Pointer to the transfer structure. - * retval kStatus_Success Successfully complete the data transmission. - * retval kStatus_I2C_Busy Previous transmission still not finished. - * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - * retval kStataus_I2C_Addr_Nak Transfer error, receive NAK during addressing. - */ -status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) -{ - status_t result = kStatus_Success; - uint32_t subaddress; - uint8_t subaddrBuf[4]; - i2c_direction_t direction; - int i; - - assert(xfer != NULL); - - /* If start signal is requested, send start signal. */ - if (0U == (xfer->flags & (uint32_t)kI2C_TransferNoStartFlag)) - { - direction = (xfer->subaddressSize != 0U) ? kI2C_Write : xfer->direction; - result = I2C_MasterStart(base, xfer->slaveAddress, direction); - if (result == kStatus_Success) - { - result = I2C_MasterCheckStartResponse(base); - if (result != kStatus_Success) - { - return result; - } - if ((xfer->subaddressSize) != 0U) - { - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) - { - subaddrBuf[i] = (uint8_t)subaddress & 0xffU; - subaddress >>= 8; - } - /* Send subaddress. */ - result = - I2C_MasterWriteBlocking(base, subaddrBuf, xfer->subaddressSize, (uint32_t)kI2C_TransferNoStopFlag); - if (result != kStatus_Success) - { - if (result == kStatus_I2C_Nak) - { - (void)I2C_MasterStop(base); - return kStatus_I2C_Addr_Nak; - } - } - else if (xfer->direction == kI2C_Read) - { - result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction); - if (result == kStatus_Success) - { - result = I2C_MasterCheckStartResponse(base); - if (result != kStatus_Success) - { - return result; - } - } - } - else - { - /* Empty else block to avoid MISRA 14.1 violation. */ - } - } - } - } - - if (result == kStatus_Success) - { - if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0U)) - { - /* Transmit data. */ - result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); - } - else - { - if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0U)) - { - /* Receive Data. */ - result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags); - } - } - } - - if (result == kStatus_I2C_Nak) - { - (void)I2C_MasterStop(base); - } - - return result; -} - -/*! - * brief Creates a new handle for the I2C master non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. - * - * param base The I2C peripheral base address. - * param[out] handle Pointer to the I2C master driver handle. - * param callback User provided pointer to the asynchronous callback function. - * param userData User provided pointer to the application callback data. - */ -void I2C_MasterTransferCreateHandle(I2C_Type *base, - i2c_master_handle_t *handle, - i2c_master_transfer_callback_t callback, - void *userData) -{ - assert(handle != NULL); - - uint32_t instance; - i2c_to_flexcomm_t handler; - handler.i2c_master_handler = I2C_MasterTransferHandleIRQ; - - /* Clear out the handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Save base and instance. */ - handle->completionCallback = callback; - handle->userData = userData; - - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - (void)EnableIRQ(s_i2cIRQ[instance]); -} - -/*! - * brief Performs a non-blocking transaction on the I2C bus. - * - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - * param xfer The pointer to the transfer descriptor. - * retval kStatus_Success The transaction was started successfully. - * retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking - * transaction is already in progress. - */ -status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) -{ - status_t result; - - assert(handle != NULL); - assert(xfer != NULL); - assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); - - /* Return busy if another transaction is in progress. */ - if (handle->state != (uint8_t)kIdleState) - { - return kStatus_I2C_Busy; - } - - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - - /* Prepare transfer state machine. */ - result = I2C_InitTransferStateMachine(base, handle, xfer); - - /* Clear error flags. */ - I2C_ClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Enable I2C internal IRQ sources. */ - I2C_EnableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - - return result; -} - -/*! - * brief Returns number of bytes transferred so far. - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - * param[out] count Number of bytes transferred so far by the non-blocking transaction. - * retval kStatus_Success - * retval #kStatus_I2C_Busy - */ -status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state == (uint8_t)kIdleState) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* There is no necessity to disable interrupts as we read a single integer value */ - *count = handle->transferCount; - return kStatus_Success; -} - -/*! - * brief Terminates a non-blocking I2C master transmission early. - * - * note It is not safe to call this function from an IRQ handler that has a higher priority than the - * I2C peripheral's IRQ priority. - * - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - * retval kStatus_Success A transaction was successfully aborted. - * retval #kStatus_I2C_Timeout Timeout during polling for flags. - */ -status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) -{ - status_t result = kStatus_Success; - uint32_t master_state; - - if (handle->state != (uint8_t)kIdleState) - { - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - - /* Wait until module is ready */ - result = I2C_PendingStatusWait(base); - - if (result != kStatus_Success) - { - handle->state = (uint8_t)kIdleState; - return result; - } - - /* Get the state of the I2C module */ - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if (master_state != (uint32_t)I2C_STAT_MSTCODE_IDLE) - { - /* Send a stop command to finalize the transfer. */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - - /* Wait until the STOP is completed */ - result = I2C_PendingStatusWait(base); - - if (result != kStatus_Success) - { - handle->state = (uint8_t)kIdleState; - return result; - } - } - - /* Reset handle. */ - handle->state = (uint8_t)kIdleState; - handle->checkAddrNack = false; - } - return kStatus_Success; -} - -static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) -{ - struct _i2c_master_transfer *transfer; - - handle->transfer = *xfer; - transfer = &(handle->transfer); - - handle->transferCount = 0; - handle->remainingBytes = transfer->dataSize; - handle->buf = (uint8_t *)transfer->data; - handle->remainingSubaddr = 0; - handle->checkAddrNack = false; - - if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) - { - /* Start condition shall be ommited, switch directly to next phase */ - if (transfer->dataSize == 0U) - { - handle->state = (uint8_t)kStopState; - } - else if (handle->transfer.direction == kI2C_Write) - { - handle->state = (uint8_t)kTransmitDataState; - } - else if (handle->transfer.direction == kI2C_Read) - { - handle->state = (uint8_t)kReceiveDataBeginState; - } - else - { - return kStatus_I2C_InvalidParameter; - } - } - else - { - if (transfer->subaddressSize != 0U) - { - int i; - uint32_t subaddress; - - if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) - { - return kStatus_I2C_InvalidParameter; - } - - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) - { - handle->subaddrBuf[i] = (uint8_t)subaddress & 0xffU; - subaddress >>= 8; - } - handle->remainingSubaddr = transfer->subaddressSize; - } - handle->state = (uint8_t)kStartState; - handle->checkAddrNack = true; - } - - return kStatus_Success; -} - -static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) -{ - uint32_t status; - uint32_t master_state; - struct _i2c_master_transfer *transfer; - status_t err; - - transfer = &(handle->transfer); - bool ignoreNak = ((handle->state == (uint8_t)kWaitForCompletionState) && (handle->remainingBytes == 0U)) -#if I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK - /* If master is nacked by slave after the last byte during transmit, ignore the nack. */ - || ((handle->state == (uint8_t)kStopState) && (handle->remainingBytes == 0U)) -#endif - ; - - *isDone = false; - - status = I2C_GetStatusFlags(base); - - if ((status & I2C_STAT_MSTARBLOSS_MASK) != 0U) - { - I2C_ClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); - return kStatus_I2C_ArbitrationLost; - } - - if ((status & I2C_STAT_MSTSTSTPERR_MASK) != 0U) - { - I2C_ClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); - return kStatus_I2C_StartStopError; - } - - /* Event timeout happens when the time since last bus event has been longer than the time specified by TIMEOUT - register. eg: Start signal fails to generate, no error status is set and transfer hangs if glitch on bus happens - before, the timeout status can be used to avoid the transfer hangs indefinitely. */ - if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) - { - I2C_ClearStatusFlags(base, (uint32_t)kI2C_EventTimeoutFlag); - return kStatus_I2C_EventTimeout; - } - - /* SCL timeout happens when the slave is holding the SCL line low and the time has been longer than the time - specified by TIMEOUT register. */ - if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) - { - I2C_ClearStatusFlags(base, (uint32_t)kI2C_SclTimeoutFlag); - return kStatus_I2C_SclLowTimeout; - } - - if ((status & I2C_STAT_MSTPENDING_MASK) == 0U) - { - return kStatus_I2C_Busy; - } - - /* Get the hardware state of the I2C module */ - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - if (((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || - (master_state == (uint32_t)I2C_STAT_MSTCODE_NACKDAT)) && - (ignoreNak != true)) - { - /* Slave NACKed last byte, issue stop and return error */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = (uint8_t)kWaitForCompletionState; - /* If master is nacked during slave probe or during sending subaddress, return kStatus_I2C_ADDR_Nak. */ - if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (handle->checkAddrNack)) - { - return kStatus_I2C_Addr_Nak; - } - else /* Otherwise just return kStatus_I2C_Nak */ - { - return kStatus_I2C_Nak; - } - } - - err = kStatus_Success; - switch (handle->state) - { - case (uint8_t)kStartState: - if (handle->remainingSubaddr != 0U) - { - /* Subaddress takes precedence over the data transfer, direction is always "write" in this case */ - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1U; - handle->state = (uint8_t)kTransmitSubaddrState; - } - else if (transfer->direction == kI2C_Write) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = (handle->remainingBytes != 0U) ? (uint8_t)kTransmitDataState : (uint8_t)kStopState; - } - else - { - base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; - handle->state = (handle->remainingBytes != 0U) ? (uint8_t)kReceiveDataState : (uint8_t)kStopState; - } - /* Send start condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - break; - - case (uint8_t)kTransmitSubaddrState: - if (master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) - { - return kStatus_I2C_UnexpectedState; - } - /* Most significant subaddress byte comes first */ - base->MSTDAT = handle->subaddrBuf[handle->transfer.subaddressSize - handle->remainingSubaddr]; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - if (--(handle->remainingSubaddr) != 0U) - { - /* There are still subaddress bytes to be transmitted */ - break; - } - if (handle->remainingBytes != 0U) - { - /* There is data to be transferred, if there is write to read turnaround it is necessary to perform - * repeated start */ - handle->state = (transfer->direction == kI2C_Read) ? (uint8_t)kStartState : (uint8_t)kTransmitDataState; - } - else - { - /* No more data, schedule stop condition */ - handle->state = (uint8_t)kStopState; - } - break; - - case (uint8_t)kTransmitDataState: - handle->checkAddrNack = false; - if (master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) - { - return kStatus_I2C_UnexpectedState; - } - base->MSTDAT = *(handle->buf)++; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - if (--handle->remainingBytes == 0U) - { - /* No more data, schedule stop condition */ - handle->state = (uint8_t)kStopState; - } - handle->transferCount++; - break; - - case (uint8_t)kReceiveDataBeginState: - handle->checkAddrNack = false; - if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) - { - return kStatus_I2C_UnexpectedState; - } - (void)base->MSTDAT; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - handle->state = (uint8_t)kReceiveDataState; - break; - - case (uint8_t)kReceiveDataState: - handle->checkAddrNack = false; - if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) - { - return kStatus_I2C_UnexpectedState; - } - *(handle->buf)++ = (uint8_t)base->MSTDAT; - if (--handle->remainingBytes != 0U) - { - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - } - else - { - /* No more data expected, issue NACK and STOP right away */ - if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStopFlag)) - { - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - } - handle->state = (uint8_t)kWaitForCompletionState; - } - handle->transferCount++; - break; - - case (uint8_t)kStopState: - handle->checkAddrNack = false; - if ((transfer->flags & (uint32_t)kI2C_TransferNoStopFlag) != 0U) - { - /* Stop condition is omitted, we are done */ - *isDone = true; - handle->state = (uint8_t)kIdleState; - break; - } - /* Send stop condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = (uint8_t)kWaitForCompletionState; - break; - - case (uint8_t)kWaitForCompletionState: - *isDone = true; - handle->state = (uint8_t)kIdleState; - break; - - case (uint8_t)kIdleState: - default: - /* State machine shall not be invoked again once it enters the idle state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - return err; -} - -/*! - * brief Reusable routine to handle master interrupts. - * note This function does not need to be called unless you are reimplementing the - * nonblocking API's interrupt handler routines to add special functionality. - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - */ -void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle) -{ - bool isDone; - status_t result; - - /* Don't do anything if we don't have a valid handle. */ - if (NULL == handle) - { - return; - } - - result = I2C_RunTransferStateMachine(base, handle, &isDone); - - if ((result != kStatus_Success) || isDone) - { - /* Restore handle to idle state. */ - handle->state = (uint8_t)kIdleState; - - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); - - /* Invoke callback. */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } -} - -static void I2C_SlaveInternalStateMachineReset(I2C_Type *base) -{ - I2C_SlaveEnable(base, false); /* clear SLVEN Slave enable bit */ -} - -static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal) -{ - uint32_t dataSetupTime_ns; - - switch ((uint8_t)(busSpeed)) - { - case (uint8_t)kI2C_SlaveStandardMode: - dataSetupTime_ns = 250U; - break; - - case (uint8_t)kI2C_SlaveFastMode: - dataSetupTime_ns = 100U; - break; - - case (uint8_t)kI2C_SlaveFastModePlus: - dataSetupTime_ns = 50U; - break; - - case (uint8_t)kI2C_SlaveHsMode: - dataSetupTime_ns = 10U; - break; - - default: - dataSetupTime_ns = 0U; - break; - } - - if (0U == dataSetupTime_ns) - { - return kStatus_InvalidArgument; - } - - /* divVal = (sourceClock_Hz / 1000000) * (dataSetupTime_ns / 1000) */ - *divVal = srcClock_Hz / 1000U; - *divVal = (*divVal) * dataSetupTime_ns; - *divVal = (*divVal) / 1000000U; - - if ((*divVal) > I2C_CLKDIV_DIVVAL_MASK) - { - *divVal = I2C_CLKDIV_DIVVAL_MASK; - } - - return kStatus_Success; -} - -static uint32_t I2C_SlavePollPending(I2C_Type *base) -{ - uint32_t stat; - -#if I2C_RETRY_TIMES != 0U - uint32_t waitTimes = I2C_RETRY_TIMES; -#endif - do - { - stat = base->STAT; -#if I2C_RETRY_TIMES != 0U - waitTimes--; - } while ((0U == (stat & I2C_STAT_SLVPENDING_MASK)) && (waitTimes != 0U)); - - if (waitTimes == 0U) - { - return (uint32_t)kStatus_I2C_Timeout; - } -#else - } while (0U == (stat & I2C_STAT_SLVPENDING_MASK)); -#endif - - return stat; -} - -static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event) -{ - uint32_t eventMask = handle->transfer.eventMask; - handle->transfer.event = event; - if (((handle->callback) != NULL) && ((eventMask & (uint32_t)event) != 0U)) - { - handle->callback(base, &handle->transfer, handle->userData); - - size_t txSize = handle->transfer.txSize; - size_t rxSize = handle->transfer.rxSize; - /* if after event callback we have data buffer (callback func has added new data), keep transfer busy */ - if (false == handle->isBusy) - { - if (((handle->transfer.txData != NULL) && (txSize != 0U)) || - ((handle->transfer.rxData != NULL) && (rxSize != 0U))) - { - handle->isBusy = true; - } - } - - /* Clear the transferred count now that we have a new buffer. */ - if ((event == kI2C_SlaveReceiveEvent) || (event == kI2C_SlaveTransmitEvent)) - { - handle->transfer.transferredCount = 0; - } - } -} - -static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle) -{ - uint8_t addressByte0; - size_t txSize; - size_t rxSize; - - addressByte0 = (uint8_t)base->SLVDAT; - - /* store the matched address */ - handle->transfer.receivedAddress = addressByte0; - - /* R/nW */ - if ((addressByte0 & 1U) != 0U) - { - txSize = handle->transfer.txSize; - /* if we have no data in this transfer, call callback to get new */ - if ((handle->transfer.txData == NULL) || (txSize == 0U)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); - } - - txSize = handle->transfer.txSize; - /* NACK if we have no data in this transfer. */ - if ((handle->transfer.txData == NULL) || (txSize == 0U)) - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - return false; - } - - /* master wants to read, so slave transmit is next state */ - handle->slaveFsm = kI2C_SlaveFsmTransmit; - } - else - { - rxSize = handle->transfer.rxSize; - /* if we have no receive buffer in this transfer, call callback to get new */ - if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); - } - - rxSize = handle->transfer.rxSize; - /* NACK if we have no data in this transfer */ - if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - return false; - } - - /* master wants write, so slave receive is next state */ - handle->slaveFsm = kI2C_SlaveFsmReceive; - } - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - return true; -} - -static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, - i2c_slave_handle_t *handle, - const void *txData, - size_t txSize, - void *rxData, - size_t rxSize, - uint32_t eventMask) -{ - assert(handle != NULL); - - status_t status; - status = kStatus_Success; - - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); - - /* Return busy if another transaction is in progress. */ - if (handle->isBusy) - { - status = kStatus_I2C_Busy; - } - - /* Save transfer into handle. */ - handle->transfer.txData = (const uint8_t *)txData; - handle->transfer.txSize = txSize; - handle->transfer.rxData = (uint8_t *)rxData; - handle->transfer.rxSize = rxSize; - handle->transfer.transferredCount = 0; - handle->transfer.eventMask = eventMask | (uint32_t)kI2C_SlaveTransmitEvent | (uint32_t)kI2C_SlaveReceiveEvent; - handle->isBusy = true; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* Clear w1c flags. */ - base->STAT |= 0u; - - /* Enable I2C internal IRQ sources. */ - I2C_EnableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); - - return status; -} - -/*! - * brief Starts accepting master read from slave requests. - * - * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * param base The I2C peripheral base address. - * param transfer Pointer to #i2c_slave_transfer_t structure. - * param txData Pointer to data to send to master. - * param txSize Size of txData in bytes. - * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * retval kStatus_Success Slave transfers were successfully started. - * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetSendBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, txData, txSize, NULL, 0u, eventMask); -} - -/*! - * brief Starts accepting master write to slave requests. - * - * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * param base The I2C peripheral base address. - * param transfer Pointer to #i2c_slave_transfer_t structure. - * param rxData Pointer to data to store data from master. - * param rxSize Size of rxData in bytes. - * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * retval kStatus_Success Slave transfers were successfully started. - * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetReceiveBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, NULL, 0u, rxData, rxSize, eventMask); -} - -/*! - * brief Configures Slave Address n register. - * - * This function writes new value to Slave Address register. - * - * param base The I2C peripheral base address. - * param addressRegister The module supports multiple address registers. The parameter determines which one shall be - * changed. - * param address The slave address to be stored to the address register for matching. - * param addressDisable Disable matching of the specified address register. - */ -void I2C_SlaveSetAddress(I2C_Type *base, - i2c_slave_address_register_t addressRegister, - uint8_t address, - bool addressDisable) -{ - base->SLVADR[addressRegister] = I2C_SLVADR_SLVADR(address) | I2C_SLVADR_SADISABLE(addressDisable); -} - -/*! - * brief Provides a default configuration for the I2C slave peripheral. - * - * This function provides the following default configuration for the I2C slave peripheral: - * code - * slaveConfig->enableSlave = true; - * slaveConfig->address0.disable = false; - * slaveConfig->address0.address = 0u; - * slaveConfig->address1.disable = true; - * slaveConfig->address2.disable = true; - * slaveConfig->address3.disable = true; - * slaveConfig->busSpeed = kI2C_SlaveStandardMode; - * endcode - * - * After calling this function, override any settings to customize the configuration, - * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the a - * address0.address member of the configuration structure with the desired slave address. - * - * param[out] slaveConfig User provided configuration structure that is set to default values. Refer to - * #i2c_slave_config_t. - */ -void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) -{ - assert(slaveConfig != NULL); - - i2c_slave_config_t mySlaveConfig = {0}; - - /* default config enables slave address 0 match to general I2C call address zero */ - mySlaveConfig.enableSlave = true; - mySlaveConfig.address1.addressDisable = true; - mySlaveConfig.address2.addressDisable = true; - mySlaveConfig.address3.addressDisable = true; - - *slaveConfig = mySlaveConfig; -} - -/*! - * brief Initializes the I2C slave peripheral. - * - * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user - * provided configuration. - * - * param base The I2C peripheral base address. - * param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults - * that you can override. - * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide - * enough - * data setup time for master when slave stretches the clock. - */ -status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz) -{ - status_t status; - uint32_t divVal = 0; - - /* configure data setup time used when slave stretches clock */ - status = I2C_SlaveDivVal(srcClock_Hz, slaveConfig->busSpeed, &divVal); - if (kStatus_Success != status) - { - return status; - } - - (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); - - /* I2C Clock Divider register */ - base->CLKDIV = divVal; - - /* set Slave address */ - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister0, slaveConfig->address0.address, - slaveConfig->address0.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister1, slaveConfig->address1.address, - slaveConfig->address1.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister2, slaveConfig->address2.address, - slaveConfig->address2.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister3, slaveConfig->address3.address, - slaveConfig->address3.addressDisable); - - /* set Slave address 0 qual */ - base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(slaveConfig->qualMode) | I2C_SLVQUAL0_SLVQUAL0(slaveConfig->qualAddress); - - /* set Slave enable */ - base->CFG = I2C_CFG_SLVEN(slaveConfig->enableSlave); - - return status; -} - -/*! - * brief Deinitializes the I2C slave peripheral. - * - * This function disables the I2C slave peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * param base The I2C peripheral base address. - */ -void I2C_SlaveDeinit(I2C_Type *base) -{ - I2C_SlaveEnable(base, false); -} - -/*! - * brief Performs a polling send transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * param base The I2C peripheral base address. - * param txBuff The pointer to the data to be transferred. - * param txSize The length in bytes of the data to be transferred. - * return kStatus_Success Data has been sent. - * return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). - */ -status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) -{ - const uint8_t *buf = txBuff; - uint32_t stat; - bool slaveAddress; - bool slaveTransmit; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - - /* Get slave machine state */ - slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); - slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_TX); - - /* in I2C_SlaveSend() it shall be either slaveAddress or slaveTransmit */ - if (!(slaveAddress || slaveTransmit)) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - if (slaveAddress) - { - /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - - /* send bytes up to txSize */ - while (txSize != 0U) - { - slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_TX); - - if (!slaveTransmit) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - /* Write 8 bits of data to the SLVDAT register */ - base->SLVDAT = I2C_SLVDAT_DATA(*buf); - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* advance counters and pointers for next data */ - buf++; - txSize--; - - if (txSize != 0U) - { - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - } - - return kStatus_Success; -} - -/*! - * brief Performs a polling receive transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * param base The I2C peripheral base address. - * param rxBuff The pointer to the data to be transferred. - * param rxSize The length in bytes of the data to be transferred. - * return kStatus_Success Data has been received. - * return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). - */ -status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) -{ - uint8_t *buf = rxBuff; - uint32_t stat; - bool slaveAddress; - bool slaveReceive; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - - /* Get slave machine state */ - slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); - slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_RX); - - /* in I2C_SlaveReceive() it shall be either slaveAddress or slaveReceive */ - if (!(slaveAddress || slaveReceive)) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - if (slaveAddress) - { - /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - - /* receive bytes up to rxSize */ - while (rxSize != 0U) - { - slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_RX); - - if (!slaveReceive) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - /* Read 8 bits of data from the SLVDAT register */ - *buf = (uint8_t)base->SLVDAT; - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* advance counters and pointers for next data */ - buf++; - rxSize--; - - if (rxSize != 0U) - { - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == (uint32_t)kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - } - - return kStatus_Success; -} - -/*! - * brief Creates a new handle for the I2C slave non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. - * - * param base The I2C peripheral base address. - * param[out] handle Pointer to the I2C slave driver handle. - * param callback User provided pointer to the asynchronous callback function. - * param userData User provided pointer to the application callback data. - */ -void I2C_SlaveTransferCreateHandle(I2C_Type *base, - i2c_slave_handle_t *handle, - i2c_slave_transfer_callback_t callback, - void *userData) -{ - assert(handle != NULL); - - uint32_t instance; - i2c_to_flexcomm_t handler; - handler.i2c_slave_handler = I2C_SlaveTransferHandleIRQ; - - /* Clear out the handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Save base and instance. */ - handle->callback = callback; - handle->userData = userData; - - /* initialize fsm */ - handle->slaveFsm = kI2C_SlaveFsmAddressMatch; - - /* store pointer to handle into transfer struct */ - handle->transfer.handle = handle; - - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); - (void)EnableIRQ(s_i2cIRQ[instance]); -} - -/*! - * brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. - * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. - * - * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * param base The I2C peripheral base address. - * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * retval kStatus_Success Slave transfers were successfully started. - * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, handle, NULL, 0u, NULL, 0u, eventMask); -} - -/*! - * brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. - * - * param base I2C base pointer. - * param handle pointer to i2c_slave_handle_t structure. - * param count Number of bytes transferred so far by the non-blocking transaction. - * retval kStatus_InvalidArgument count is Invalid. - * retval kStatus_Success Successfully return the count. - */ -status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (!handle->isBusy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* For an active transfer, just return the count from the handle. */ - *count = handle->transfer.transferredCount; - - return kStatus_Success; -} - -/*! - * brief Aborts the slave non-blocking transfers. - * note This API could be called at any time to stop slave for handling the bus events. - * param base The I2C peripheral base address. - * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * retval kStatus_Success - * retval #kStatus_I2C_Idle - */ -void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) -{ - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); - - /* Set the SLVEN bit to 0 in the CFG register. */ - I2C_SlaveEnable(base, false); - - handle->isBusy = false; - handle->transfer.txSize = 0U; - handle->transfer.rxSize = 0U; -} - -/*! - * brief Reusable routine to handle slave interrupts. - * note This function does not need to be called unless you are reimplementing the - * non blocking API's interrupt handler routines to add special functionality. - * param base The I2C peripheral base address. - * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - */ -void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle) -{ - uint32_t i2cStatus = base->STAT; - uint8_t tmpdata; - size_t txSize; - size_t rxSize; - - if ((i2cStatus & I2C_STAT_SLVDESEL_MASK) != 0U) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveDeselectedEvent); - I2C_SlaveClearStatusFlags(base, I2C_STAT_SLVDESEL_MASK); - } - - /* SLVPENDING flag is cleared by writing I2C_SLVCTL_SLVCONTINUE_MASK to SLVCTL register */ - if ((i2cStatus & I2C_STAT_SLVPENDING_MASK) != 0U) - { - bool slaveAddress = - (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); - - if (slaveAddress) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveAddressMatchEvent); - (void)I2C_SlaveAddressIRQ(base, handle); - } - else - { - switch (handle->slaveFsm) - { - case kI2C_SlaveFsmReceive: - { - bool slaveReceive = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == - (uint32_t)I2C_STAT_SLVST_RX); - - if (slaveReceive) - { - rxSize = handle->transfer.rxSize; - /* if we have no receive buffer in this transfer, call callback to get new */ - if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); - } - - rxSize = handle->transfer.rxSize; - /* receive a byte */ - if ((handle->transfer.rxData != NULL) && (rxSize != 0U)) - { - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - tmpdata = (uint8_t)base->SLVDAT; - *(handle->transfer.rxData) = tmpdata; - (handle->transfer.rxSize)--; - (handle->transfer.rxData)++; - (handle->transfer.transferredCount)++; - } - - rxSize = handle->transfer.rxSize; - txSize = handle->transfer.txSize; - /* is this last transaction for this transfer? allow next transaction */ - if ((0U == rxSize) && (0U == txSize)) - { - handle->isBusy = false; - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); - } - } - else - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - } - } - break; - - case kI2C_SlaveFsmTransmit: - { - bool slaveTransmit = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == - (uint32_t)I2C_STAT_SLVST_TX); - - if (slaveTransmit) - { - txSize = handle->transfer.txSize; - /* if we have no data in this transfer, call callback to get new */ - if ((handle->transfer.txData == NULL) || (txSize == 0U)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); - } - - txSize = handle->transfer.txSize; - /* transmit a byte */ - if ((handle->transfer.txData != NULL) && (txSize != 0U)) - { - base->SLVDAT = *(handle->transfer.txData); - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - (handle->transfer.txSize)--; - (handle->transfer.txData)++; - (handle->transfer.transferredCount)++; - } - - rxSize = handle->transfer.rxSize; - txSize = handle->transfer.txSize; - /* is this last transaction for this transfer? allow next transaction */ - if ((0U == rxSize) && (0U == txSize)) - { - handle->isBusy = false; - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); - } - } - else - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - } - } - break; - - default: - /* incorrect state, slv_abort()? */ - break; - } - } - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c.h deleted file mode 100644 index b521a1ad756..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c.h +++ /dev/null @@ -1,1148 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2C_H_ -#define _FSL_I2C_H_ - -#include -#include "fsl_device_registers.h" -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define I2C_CFG_MASK 0x1f - -/*! - * @addtogroup i2c_driver - * @{ - */ - -/*! @file */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2C driver version. */ -#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) -/*@}*/ - -/*! @brief Retry times for waiting flag. */ -#ifndef I2C_RETRY_TIMES -#define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ -#endif - -/*! @brief Whether to ignore the nack signal of the last byte during master transmit. */ -#ifndef I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK -#define I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK \ - 1U /* Define to one means master ignores the last byte's nack and considers the transfer successful. */ -#endif - -/* definitions for MSTCODE bits in I2C Status register STAT */ -#define I2C_STAT_MSTCODE_IDLE (0U) /*!< Master Idle State Code */ -#define I2C_STAT_MSTCODE_RXREADY (1U) /*!< Master Receive Ready State Code */ -#define I2C_STAT_MSTCODE_TXREADY (2U) /*!< Master Transmit Ready State Code */ -#define I2C_STAT_MSTCODE_NACKADR (3U) /*!< Master NACK by slave on address State Code */ -#define I2C_STAT_MSTCODE_NACKDAT (4U) /*!< Master NACK by slave on data State Code */ - -/* definitions for SLVSTATE bits in I2C Status register STAT */ -#define I2C_STAT_SLVST_ADDR (0) -#define I2C_STAT_SLVST_RX (1) -#define I2C_STAT_SLVST_TX (2) - -/*! @brief I2C status return codes. */ -enum -{ - kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 0), /*!< The master is already performing a transfer. */ - kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 1), /*!< The slave driver is idle. */ - kStatus_I2C_Nak = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 2), /*!< The slave device sent a NAK in response to a byte. */ - kStatus_I2C_InvalidParameter = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 3), /*!< Unable to proceed due to invalid parameter. */ - kStatus_I2C_BitError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 4), /*!< Transferred bit was not seen on the bus. */ - kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 5), /*!< Arbitration lost error. */ - kStatus_I2C_NoTransferInProgress = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 6), /*!< Attempt to abort a transfer when one is not in progress. */ - kStatus_I2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */ - kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8), /*!< Start and stop error. */ - kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9), /*!< Unexpected state. */ - kStatus_I2C_Timeout = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, - 10), /*!< Timeout when waiting for I2C master/slave pending status to set to continue transfer. */ - kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 11), /*!< NAK received for Address */ - kStatus_I2C_EventTimeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 12), /*!< Timeout waiting for bus event. */ - kStatus_I2C_SclLowTimeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 13), /*!< Timeout SCL signal remains low. */ -}; - -/*! @} */ - -/*! - * @addtogroup i2c_driver - * @{ - */ - -/*! - * @brief I2C status flags. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -enum _i2c_status_flags -{ - kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. bit 0 */ - kI2C_MasterArbitrationLostFlag = - I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus. bit 4*/ - kI2C_MasterStartStopErrorFlag = - I2C_STAT_MSTSTSTPERR_MASK, /*!< There was an error during start or stop phase of the transaction. bit 6 */ - kI2C_MasterIdleFlag = 1UL << 5U, /*!< The I2C master idle status. bit 5 */ - kI2C_MasterRxReadyFlag = 1UL << I2C_STAT_MSTSTATE_SHIFT, /*!< The I2C master rx ready status. bit 1 */ - kI2C_MasterTxReadyFlag = 1UL << (I2C_STAT_MSTSTATE_SHIFT + 1U), /*!< The I2C master tx ready status. bit 2 */ - kI2C_MasterAddrNackFlag = 1UL << 7U, /*!< The I2C master address nack status. bit 7 */ - kI2C_MasterDataNackFlag = 1UL << (I2C_STAT_MSTSTATE_SHIFT + 2U), /*!< The I2C master data nack status. bit 3 */ - kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. bit 8 */ - kI2C_SlaveNotStretching = I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 - = yes, 1 = no). bit 11 */ - kI2C_SlaveSelected = - I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. bit 14 */ - kI2C_SaveDeselected = I2C_STAT_SLVDESEL_MASK, /*!< Indicates that slave was previously deselected (deselect event - took place, w1c). bit 15 */ - kI2C_SlaveAddressedFlag = 1UL << 22U, /*!< One of the I2C slave's 4 addresses is matched. bit 22 */ - kI2C_SlaveReceiveFlag = 1UL << I2C_STAT_SLVSTATE_SHIFT, /*!< Slave receive data available. bit 9 */ - kI2C_SlaveTransmitFlag = 1UL << (I2C_STAT_SLVSTATE_SHIFT + 1U), /*!< Slave data can be transmitted. bit 10 */ - kI2C_SlaveAddress0MatchFlag = 1UL << 20U, /*!< Slave address0 match. bit 20 */ - kI2C_SlaveAddress1MatchFlag = 1UL << I2C_STAT_SLVIDX_SHIFT, /*!< Slave address1 match. bit 12 */ - kI2C_SlaveAddress2MatchFlag = 1UL << (I2C_STAT_SLVIDX_SHIFT + 1U), /*!< Slave address2 match. bit 13 */ - kI2C_SlaveAddress3MatchFlag = 1UL << 21U, /*!< Slave address3 match. bit 21 */ - kI2C_MonitorReadyFlag = I2C_STAT_MONRDY_MASK, /*!< The I2C monitor ready interrupt. bit 16 */ - kI2C_MonitorOverflowFlag = I2C_STAT_MONOV_MASK, /*!< The monitor data overrun interrupt. bit 17 */ - kI2C_MonitorActiveFlag = I2C_STAT_MONACTIVE_MASK, /*!< The monitor is active. bit 18 */ - kI2C_MonitorIdleFlag = I2C_STAT_MONIDLE_MASK, /*!< The monitor idle interrupt. bit 19 */ - kI2C_EventTimeoutFlag = I2C_STAT_EVENTTIMEOUT_MASK, /*!< The bus event timeout interrupt. bit 24 */ - kI2C_SclTimeoutFlag = I2C_STAT_SCLTIMEOUT_MASK, /*!< The SCL timeout interrupt. bit 25 */ - - /* All master flags that can be cleared by software */ - kI2C_MasterAllClearFlags = kI2C_MasterArbitrationLostFlag | kI2C_MasterStartStopErrorFlag, - /* All slave flags that can be cleared by software */ - kI2C_SlaveAllClearFlags = kI2C_SaveDeselected, - /* All common flags that can be cleared by software */ - kI2C_CommonAllClearFlags = - kI2C_MonitorOverflowFlag | kI2C_MonitorIdleFlag | kI2C_EventTimeoutFlag | kI2C_SclTimeoutFlag, -}; - -/*! - * @brief I2C interrupt enable. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -enum _i2c_interrupt_enable -{ - kI2C_MasterPendingInterruptEnable = - I2C_STAT_MSTPENDING_MASK, /*!< The I2C master communication pending interrupt. */ - kI2C_MasterArbitrationLostInterruptEnable = - I2C_STAT_MSTARBLOSS_MASK, /*!< The I2C master arbitration lost interrupt. */ - kI2C_MasterStartStopErrorInterruptEnable = - I2C_STAT_MSTSTSTPERR_MASK, /*!< The I2C master start/stop timing error interrupt. */ - kI2C_SlavePendingInterruptEnable = I2C_STAT_SLVPENDING_MASK, /*!< The I2C slave communication pending interrupt. */ - kI2C_SlaveNotStretchingInterruptEnable = - I2C_STAT_SLVNOTSTR_MASK, /*!< The I2C slave not streching interrupt, deep-sleep mode can be entered only when - this interrupt occurs. */ - kI2C_SlaveDeselectedInterruptEnable = I2C_STAT_SLVDESEL_MASK, /*!< The I2C slave deselection interrupt. */ - kI2C_MonitorReadyInterruptEnable = I2C_STAT_MONRDY_MASK, /*!< The I2C monitor ready interrupt. */ - kI2C_MonitorOverflowInterruptEnable = I2C_STAT_MONOV_MASK, /*!< The monitor data overrun interrupt. */ - kI2C_MonitorIdleInterruptEnable = I2C_STAT_MONIDLE_MASK, /*!< The monitor idle interrupt. */ - kI2C_EventTimeoutInterruptEnable = I2C_STAT_EVENTTIMEOUT_MASK, /*!< The bus event timeout interrupt. */ - kI2C_SclTimeoutInterruptEnable = I2C_STAT_SCLTIMEOUT_MASK, /*!< The SCL timeout interrupt. */ - - /* All master interrupt sources */ - kI2C_MasterAllInterruptEnable = kI2C_MasterPendingInterruptEnable | kI2C_MasterArbitrationLostInterruptEnable | - kI2C_MasterStartStopErrorInterruptEnable, - /* All slave interrupt sources */ - kI2C_SlaveAllInterruptEnable = - kI2C_SlavePendingInterruptEnable | kI2C_SlaveNotStretchingInterruptEnable | kI2C_SlaveDeselectedInterruptEnable, - /* All common interrupt sources */ - kI2C_CommonAllInterruptEnable = kI2C_MonitorReadyInterruptEnable | kI2C_MonitorOverflowInterruptEnable | - kI2C_MonitorIdleInterruptEnable | kI2C_EventTimeoutInterruptEnable | - kI2C_SclTimeoutInterruptEnable, -}; -/*! @} */ - -/*! - * @addtogroup i2c_master_driver - * @{ - */ - -/*! @brief Direction of master and slave transfers. */ -typedef enum _i2c_direction -{ - kI2C_Write = 0U, /*!< Master transmit. */ - kI2C_Read = 1U /*!< Master receive. */ -} i2c_direction_t; - -/*! - * @brief Structure with settings to initialize the I2C master module. - * - * This structure holds configuration settings for the I2C peripheral. To initialize this - * structure to reasonable defaults, call the I2C_MasterGetDefaultConfig() function and - * pass a pointer to your configuration structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _i2c_master_config -{ - bool enableMaster; /*!< Whether to enable master mode. */ - uint32_t baudRate_Bps; /*!< Desired baud rate in bits per second. */ - bool enableTimeout; /*!< Enable internal timeout function. */ - uint8_t timeout_Ms; /*!< Event timeout and SCL low timeout value. */ -} i2c_master_config_t; - -/* Forward declaration of the transfer descriptor and handle typedefs. */ -/*! @brief I2C master transfer typedef */ -typedef struct _i2c_master_transfer i2c_master_transfer_t; - -/*! @brief I2C master handle typedef */ -typedef struct _i2c_master_handle i2c_master_handle_t; - -/*! - * @brief Master completion callback function pointer type. - * - * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use - * in the call to I2C_MasterTransferCreateHandle(). - * - * @param base The I2C peripheral base address. - * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, - i2c_master_handle_t *handle, - status_t completionStatus, - void *userData); - -/*! - * @brief Transfer option flags. - * - * @note These enumerations are intended to be OR'd together to form a bit mask of options for - * the #_i2c_master_transfer::flags field. - */ -enum _i2c_master_transfer_flags -{ - kI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ - kI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ - kI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ - kI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ -}; - -/*! @brief States for the state machine used by transactional APIs. */ -enum _i2c_transfer_states -{ - kIdleState = 0, - kTransmitSubaddrState, - kTransmitDataState, - kReceiveDataBeginState, - kReceiveDataState, - kReceiveLastDataState, - kStartState, - kStopState, - kWaitForCompletionState -}; - -/*! - * @brief Non-blocking transfer descriptor structure. - * - * This structure is used to pass transaction parameters to the I2C_MasterTransferNonBlocking() API. - */ -struct _i2c_master_transfer -{ - uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i2c_master_transfer_flags for available - options. Set to 0 or #kI2C_TransferDefaultFlag for normal transfers. */ - uint8_t slaveAddress; /*!< The 7-bit slave address. */ - i2c_direction_t direction; /*!< Either #kI2C_Read or #kI2C_Write. */ - uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ - size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ - void *data; /*!< Pointer to data to transfer. */ - size_t dataSize; /*!< Number of bytes to transfer. */ -}; - -/*! - * @brief Driver handle for master non-blocking APIs. - * @note The contents of this structure are private and subject to change. - */ -struct _i2c_master_handle -{ - uint8_t state; /*!< Transfer state machine current state. */ - uint32_t transferCount; /*!< Indicates progress of the transfer */ - uint32_t remainingBytes; /*!< Remaining byte count in current state. */ - uint8_t *buf; /*!< Buffer pointer for current state. */ - uint32_t remainingSubaddr; - uint8_t subaddrBuf[4]; - bool checkAddrNack; /*!< Whether to check the nack signal is detected during addressing. */ - i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ - i2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ - void *userData; /*!< Application data passed to callback. */ -}; - -/*! @} */ - -/*! - * @addtogroup i2c_slave_driver - * @{ - */ -/*! @brief I2C slave address register. */ -typedef enum _i2c_slave_address_register -{ - kI2C_SlaveAddressRegister0 = 0U, /*!< Slave Address 0 register. */ - kI2C_SlaveAddressRegister1 = 1U, /*!< Slave Address 1 register. */ - kI2C_SlaveAddressRegister2 = 2U, /*!< Slave Address 2 register. */ - kI2C_SlaveAddressRegister3 = 3U, /*!< Slave Address 3 register. */ -} i2c_slave_address_register_t; - -/*! @brief Data structure with 7-bit Slave address and Slave address disable. */ -typedef struct _i2c_slave_address -{ - uint8_t address; /*!< 7-bit Slave address SLVADR. */ - bool addressDisable; /*!< Slave address disable SADISABLE. */ -} i2c_slave_address_t; - -/*! @brief I2C slave address match options. */ -typedef enum _i2c_slave_address_qual_mode -{ - kI2C_QualModeMask = 0U, /*!< The SLVQUAL0 field (qualAddress) is used as a logical mask for matching address0. */ - kI2C_QualModeExtend = - 1U, /*!< The SLVQUAL0 (qualAddress) field is used to extend address 0 matching in a range of addresses. */ -} i2c_slave_address_qual_mode_t; - -/*! @brief I2C slave bus speed options. */ -typedef enum _i2c_slave_bus_speed -{ - kI2C_SlaveStandardMode = 0U, - kI2C_SlaveFastMode = 1U, - kI2C_SlaveFastModePlus = 2U, - kI2C_SlaveHsMode = 3U, -} i2c_slave_bus_speed_t; - -/*! - * @brief Structure with settings to initialize the I2C slave module. - * - * This structure holds configuration settings for the I2C slave peripheral. To initialize this - * structure to reasonable defaults, call the I2C_SlaveGetDefaultConfig() function and - * pass a pointer to your configuration structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _i2c_slave_config -{ - i2c_slave_address_t address0; /*!< Slave's 7-bit address and disable. */ - i2c_slave_address_t address1; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_t address2; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_t address3; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_qual_mode_t qualMode; /*!< Qualify mode for slave address 0. */ - uint8_t qualAddress; /*!< Slave address qualifier for address 0. */ - i2c_slave_bus_speed_t - busSpeed; /*!< Slave bus speed mode. If the slave function stretches SCL to allow for software response, it must - provide sufficient data setup time to the master before releasing the stretched clock. - This is accomplished by inserting one clock time of CLKDIV at that point. - The #busSpeed value is used to configure CLKDIV - such that one clock time is greater than the tSU;DAT value noted - in the I2C bus specification for the I2C mode that is being used. - If the #busSpeed mode is unknown at compile time, use the longest data setup time - kI2C_SlaveStandardMode (250 ns) */ - bool enableSlave; /*!< Enable slave mode. */ -} i2c_slave_config_t; - -/*! - * @brief Set of events sent to the callback for non blocking slave transfers. - * - * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together - * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable. - * Then, when the slave callback is invoked, it is passed the current event through its @a transfer - * parameter. - * - * @note These enumerations are meant to be OR'd together to form a bit mask of events. - */ -typedef enum _i2c_slave_transfer_event -{ - kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ - kI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit - (slave-transmitter role). */ - kI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received - data (slave-receiver role). */ - kI2C_SlaveCompletionEvent = 0x20U, /*!< All data in the active transfer have been consumed. */ - kI2C_SlaveDeselectedEvent = - 0x40U, /*!< The slave function has become deselected (SLVSEL flag changing from 1 to 0. */ - - /*! Bit mask of all available events. */ - kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | - kI2C_SlaveCompletionEvent | kI2C_SlaveDeselectedEvent, -} i2c_slave_transfer_event_t; - -/*! @brief I2C slave handle typedef. */ -typedef struct _i2c_slave_handle i2c_slave_handle_t; - -/*! @brief I2C slave transfer structure */ -typedef struct _i2c_slave_transfer -{ - i2c_slave_handle_t *handle; /*!< Pointer to handle that contains this transfer. */ - i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ - uint8_t receivedAddress; /*!< Matching address send by master. 7-bits plus R/nW bit0 */ - uint32_t eventMask; /*!< Mask of enabled events. */ - uint8_t *rxData; /*!< Transfer buffer for receive data */ - const uint8_t *txData; /*!< Transfer buffer for transmit data */ - size_t txSize; /*!< Transfer size */ - size_t rxSize; /*!< Transfer size */ - size_t transferredCount; /*!< Number of bytes transferred during this transfer. */ - status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for - #kI2C_SlaveCompletionEvent. */ -} i2c_slave_transfer_t; - -/*! - * @brief Slave event callback function pointer type. - * - * This callback is used only for the slave non-blocking transfer API. To install a callback, - * use the I2C_SlaveSetCallback() function after you have created a handle. - * - * @param base Base address for the I2C instance on which the event occurred. - * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *userData); - -/*! - * @brief I2C slave software finite state machine states. - */ -typedef enum _i2c_slave_fsm -{ - kI2C_SlaveFsmAddressMatch = 0u, - kI2C_SlaveFsmReceive = 2u, - kI2C_SlaveFsmTransmit = 3u, -} i2c_slave_fsm_t; - -/*! - * @brief I2C slave handle structure. - * @note The contents of this structure are private and subject to change. - */ -struct _i2c_slave_handle -{ - volatile i2c_slave_transfer_t transfer; /*!< I2C slave transfer. */ - volatile bool isBusy; /*!< Whether transfer is busy. */ - volatile i2c_slave_fsm_t slaveFsm; /*!< slave transfer state machine. */ - i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ - void *userData; /*!< Callback parameter passed to callback. */ -}; - -/*! @brief Typedef for master interrupt handler. */ -typedef void (*flexcomm_i2c_master_irq_handler_t)(I2C_Type *base, i2c_master_handle_t *handle); - -/*! @brief Typedef for slave interrupt handler. */ -typedef void (*flexcomm_i2c_slave_irq_handler_t)(I2C_Type *base, i2c_slave_handle_t *handle); -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup i2c_master_driver - * @{ - */ - -/*! @name Initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the I2C master peripheral. - * - * This function provides the following default configuration for the I2C master peripheral: - * @code - * masterConfig->enableMaster = true; - * masterConfig->baudRate_Bps = 100000U; - * masterConfig->enableTimeout = false; - * @endcode - * - * After calling this function, you can override any settings in order to customize the configuration, - * prior to initializing the master driver with I2C_MasterInit(). - * - * @param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. - */ -void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); - -/*! - * @brief Initializes the I2C master peripheral. - * - * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user - * provided configuration. A software reset is performed prior to configuration. - * - * @param base The I2C peripheral base address. - * @param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of - * defaults - * that you can override. - * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, - * filter widths, and timeout periods. - */ -void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes the I2C master peripheral. - * - * This function disables the I2C master peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -void I2C_MasterDeinit(I2C_Type *base); - -/*! - * @brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * @param base The I2C peripheral base address. - * @return I2C instance number starting from 0. - */ -uint32_t I2C_GetInstance(I2C_Type *base); - -/*! - * @brief Performs a software reset. - * - * Restores the I2C master peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -static inline void I2C_MasterReset(I2C_Type *base) -{ -} - -/*! - * @brief Enables or disables the I2C module as master. - * - * @param base The I2C peripheral base address. - * @param enable Pass true to enable or false to disable the specified I2C as master. - */ -static inline void I2C_MasterEnable(I2C_Type *base, bool enable) -{ - if (enable) - { - base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK; - } - else - { - base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK; - } -} - -/*@}*/ - -/*! @name Status */ -/*@{*/ -/*! - * @brief Gets the I2C status flags. - * - * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit - * in the return value is set if the flag is asserted. - * - * @param base The I2C peripheral base address. - * @return State of the status flags: - * - 1: related status flag is set. - * - 0: related status flag is not set. - * @see @ref _i2c_status_flags. - */ -uint32_t I2C_GetStatusFlags(I2C_Type *base); - -/*! - * @brief Clears the I2C status flag state. - * - * Refer to kI2C_CommonAllClearStatusFlags, kI2C_MasterAllClearStatusFlags and kI2C_SlaveAllClearStatusFlags to see - * the clearable flags. Attempts to clear other flags has no effect. - * - * @param base The I2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of the members in - * kI2C_CommonAllClearStatusFlags, kI2C_MasterAllClearStatusFlags and kI2C_SlaveAllClearStatusFlags. You may pass - * the result of a previous call to I2C_GetStatusFlags(). - * @see #_i2c_status_flags, _i2c_master_status_flags and _i2c_slave_status_flags. - */ -static inline void I2C_ClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - /* Only deal with the clearable flags */ - statusMask &= - ((uint32_t)kI2C_CommonAllClearFlags | (uint32_t)kI2C_MasterAllClearFlags | (uint32_t)kI2C_SlaveAllClearFlags); - base->STAT = statusMask; -} - -/*! - * @brief Clears the I2C master status flag state. - * @deprecated Do not use this function. It has been superceded by @ref I2C_ClearStatusFlags - * The following status register flags can be cleared: - * - #kI2C_MasterArbitrationLostFlag - * - #kI2C_MasterStartStopErrorFlag - * - * Attempts to clear other flags has no effect. - * - * @param base The I2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * #_i2c_status_flags enumerators OR'd together. You may pass the result of a previous call to - * I2C_GetStatusFlags(). - * @see _i2c_status_flags. - */ -static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - /* Allow clearing just master status flags */ - base->STAT = statusMask & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); -} - -/*@}*/ - -/*! @name Interrupts */ -/*@{*/ - -/*! - * @brief Enables the I2C interrupt requests. - * - * @param base The I2C peripheral base address. - * @param interruptMask Bit mask of interrupts to enable. See #_i2c_interrupt_enable for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2C_EnableInterrupts(I2C_Type *base, uint32_t interruptMask) -{ - base->INTENSET = interruptMask; -} - -/*! - * @brief Disables the I2C interrupt requests. - * - * @param base The I2C peripheral base address. - * @param interruptMask Bit mask of interrupts to disable. See #_i2c_interrupt_enable for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2C_DisableInterrupts(I2C_Type *base, uint32_t interruptMask) -{ - base->INTENCLR = interruptMask; -} - -/*! - * @brief Returns the set of currently enabled I2C interrupt requests. - * - * @param base The I2C peripheral base address. - * @return A bitmask composed of #_i2c_interrupt_enable enumerators OR'd together to indicate the - * set of enabled interrupts. - */ -static inline uint32_t I2C_GetEnabledInterrupts(I2C_Type *base) -{ - return base->INTSTAT; -} - -/*@}*/ - -/*! @name Bus operations */ -/*@{*/ - -/*! - * @brief Sets the I2C bus frequency for master transactions. - * - * The I2C master is automatically disabled and re-enabled as necessary to configure the baud - * rate. Do not call this function during a transfer, or the transfer is aborted. - * - * @param base The I2C peripheral base address. - * @param srcClock_Hz I2C functional clock frequency in Hertz. - * @param baudRate_Bps Requested bus frequency in bits per second. - */ -void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Sets the I2C bus timeout value. - * - * If the SCL signal remains low or bus does not have event longer than the timeout value, kI2C_SclTimeoutFlag or - * kI2C_EventTimeoutFlag is set. This can indicete the bus is held by slave or any fault occurs to the I2C module. - * - * @param base The I2C peripheral base address. - * @param timeout_Ms Timeout value in millisecond. - * @param srcClock_Hz I2C functional clock frequency in Hertz. - */ -void I2C_MasterSetTimeoutValue(I2C_Type *base, uint8_t timeout_Ms, uint32_t srcClock_Hz); - -/*! - * @brief Returns whether the bus is idle. - * - * Requires the master mode to be enabled. - * - * @param base The I2C peripheral base address. - * @retval true Bus is busy. - * @retval false Bus is idle. - */ -static inline bool I2C_MasterGetBusIdleState(I2C_Type *base) -{ - /* True if MSTPENDING flag is set and MSTSTATE is zero == idle */ - return ((base->STAT & (I2C_STAT_MSTPENDING_MASK | I2C_STAT_MSTSTATE_MASK)) == I2C_STAT_MSTPENDING_MASK); -} - -/*! - * @brief Sends a START on the I2C bus. - * - * This function is used to initiate a new master mode transfer by sending the START signal. - * The slave address is sent following the I2C START signal. - * - * @param base I2C peripheral base pointer - * @param address 7-bit slave device address. - * @param direction Master transfer directions(transmit/receive). - * @retval kStatus_Success Successfully send the start signal. - * @retval kStatus_I2C_Busy Current bus is busy. - */ -status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); - -/*! - * @brief Sends a STOP signal on the I2C bus. - * - * @retval kStatus_Success Successfully send the stop signal. - * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. - */ -status_t I2C_MasterStop(I2C_Type *base); - -/*! - * @brief Sends a REPEATED START on the I2C bus. - * - * @param base I2C peripheral base pointer - * @param address 7-bit slave device address. - * @param direction Master transfer directions(transmit/receive). - * @retval kStatus_Success Successfully send the start signal. - * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. - */ -static inline status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) -{ - return I2C_MasterStart(base, address, direction); -} - -/*! - * @brief Performs a polling send transfer on the I2C bus. - * - * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may - * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this - * function returns #kStatus_I2C_Nak. - * - * @param base The I2C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * @retval kStatus_Success Data was sent successfully. - * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags); - -/*! - * @brief Performs a polling receive transfer on the I2C bus. - * - * @param base The I2C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * @retval kStatus_Success Data was received successfully. - * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags); - -/*! - * @brief Performs a master polling transfer on the I2C bus. - * - * @note The API does not return until the transfer succeeds or fails due - * to arbitration lost or receiving a NAK. - * - * @param base I2C peripheral base address. - * @param xfer Pointer to the transfer structure. - * @retval kStatus_Success Successfully complete the data transmission. - * @retval kStatus_I2C_Busy Previous transmission still not finished. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - * @retval kStataus_I2C_Addr_Nak Transfer error, receive NAK during addressing. - */ -status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); - -/*@}*/ - -/*! @name Non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the I2C master non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. - * - * @param base The I2C peripheral base address. - * @param[out] handle Pointer to the I2C master driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void I2C_MasterTransferCreateHandle(I2C_Type *base, - i2c_master_handle_t *handle, - i2c_master_transfer_callback_t callback, - void *userData); - -/*! - * @brief Performs a non-blocking transaction on the I2C bus. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @param xfer The pointer to the transfer descriptor. - * @retval kStatus_Success The transaction was started successfully. - * @retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking - * transaction is already in progress. - */ -status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Returns number of bytes transferred so far. - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @param[out] count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_Success - * @retval #kStatus_I2C_Busy - */ -status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); - -/*! - * @brief Terminates a non-blocking I2C master transmission early. - * - * @note It is not safe to call this function from an IRQ handler that has a higher priority than the - * I2C peripheral's IRQ priority. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @retval kStatus_Success A transaction was successfully aborted. - * @retval #kStatus_I2C_Timeout Timeout during polling for flags. - */ -status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); - -/*@}*/ - -/*! @name IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle master interrupts. - * @note This function does not need to be called unless you are reimplementing the - * nonblocking API's interrupt handler routines to add special functionality. - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - */ -void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle); - -/*@}*/ - -/*! @} */ /* end of i2c_master_driver */ - -/*! - * @addtogroup i2c_slave_driver - * @{ - */ - -/*! @name Slave initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the I2C slave peripheral. - * - * This function provides the following default configuration for the I2C slave peripheral: - * @code - * slaveConfig->enableSlave = true; - * slaveConfig->address0.disable = false; - * slaveConfig->address0.address = 0u; - * slaveConfig->address1.disable = true; - * slaveConfig->address2.disable = true; - * slaveConfig->address3.disable = true; - * slaveConfig->busSpeed = kI2C_SlaveStandardMode; - * @endcode - * - * After calling this function, override any settings to customize the configuration, - * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the @a - * address0.address member of the configuration structure with the desired slave address. - * - * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to - * #i2c_slave_config_t. - */ -void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); - -/*! - * @brief Initializes the I2C slave peripheral. - * - * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user - * provided configuration. - * - * @param base The I2C peripheral base address. - * @param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults - * that you can override. - * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide - * enough - * data setup time for master when slave stretches the clock. - */ -status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz); - -/*! - * @brief Configures Slave Address n register. - * - * This function writes new value to Slave Address register. - * - * @param base The I2C peripheral base address. - * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be - * changed. - * @param address The slave address to be stored to the address register for matching. - * @param addressDisable Disable matching of the specified address register. - */ -void I2C_SlaveSetAddress(I2C_Type *base, - i2c_slave_address_register_t addressRegister, - uint8_t address, - bool addressDisable); - -/*! - * @brief Deinitializes the I2C slave peripheral. - * - * This function disables the I2C slave peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -void I2C_SlaveDeinit(I2C_Type *base); - -/*! - * @brief Enables or disables the I2C module as slave. - * - * @param base The I2C peripheral base address. - * @param enable True to enable or flase to disable. - */ -static inline void I2C_SlaveEnable(I2C_Type *base, bool enable) -{ - /* Set or clear the SLVEN bit in the CFG register. */ - base->CFG = I2C_CFG_SLVEN(enable); -} - -/*@}*/ /* end of Slave initialization and deinitialization */ - -/*! @name Slave status */ -/*@{*/ - -/*! - * @brief Clears the I2C status flag state. - * - * The following status register flags can be cleared: - * - slave deselected flag - * - * Attempts to clear other flags has no effect. - * - * @param base The I2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * _i2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to - * I2C_SlaveGetStatusFlags(). - * @see _i2c_slave_flags. - */ -static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - /* Allow clearing just slave status flags */ - base->STAT = statusMask & I2C_STAT_SLVDESEL_MASK; -} - -/*@}*/ /* end of Slave status */ - -/*! @name Slave bus operations */ -/*@{*/ - -/*! - * @brief Performs a polling send transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * @param base The I2C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @return kStatus_Success Data has been sent. - * @return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). - */ -status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); - -/*! - * @brief Performs a polling receive transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * @param base The I2C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @return kStatus_Success Data has been received. - * @return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). - */ -status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); - -/*@}*/ /* end of Slave bus operations */ - -/*! @name Slave non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the I2C slave non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. - * - * @param base The I2C peripheral base address. - * @param[out] handle Pointer to the I2C slave driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void I2C_SlaveTransferCreateHandle(I2C_Type *base, - i2c_slave_handle_t *handle, - i2c_slave_transfer_callback_t callback, - void *userData); - -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. - * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); - -/*! - * @brief Starts accepting master read from slave requests. - * - * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param transfer Pointer to #i2c_slave_transfer_t structure. - * @param txData Pointer to data to send to master. - * @param txSize Size of txData in bytes. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetSendBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask); - -/*! - * @brief Starts accepting master write to slave requests. - * - * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param transfer Pointer to #i2c_slave_transfer_t structure. - * @param rxData Pointer to data to store data from master. - * @param rxSize Size of rxData in bytes. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetReceiveBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask); - -/*! - * @brief Returns the slave address sent by the I2C master. - * - * This function should only be called from the address match event callback #kI2C_SlaveAddressMatchEvent. - * - * @param base The I2C peripheral base address. - * @param transfer The I2C slave transfer. - * @return The 8-bit address matched by the I2C slave. Bit 0 contains the R/w direction bit, and - * the 7-bit slave address is in the upper 7 bits. - */ -static inline uint32_t I2C_SlaveGetReceivedAddress(I2C_Type *base, volatile i2c_slave_transfer_t *transfer) -{ - return transfer->receivedAddress; -} - -/*! - * @brief Aborts the slave non-blocking transfers. - * @note This API could be called at any time to stop slave for handling the bus events. - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * @retval kStatus_Success - * @retval #kStatus_I2C_Idle - */ -void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); - -/*! - * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_slave_handle_t structure. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_InvalidArgument count is Invalid. - * @retval kStatus_Success Successfully return the count. - */ -status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); - -/*@}*/ /* end of Slave non-blocking */ - -/*! @name Slave IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle slave interrupts. - * @note This function does not need to be called unless you are reimplementing the - * non blocking API's interrupt handler routines to add special functionality. - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - */ -void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle); - -/*@}*/ /* end of Slave IRQ handler */ - -/*! @} */ /* end of i2c_slave_driver */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2C_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.c deleted file mode 100644 index 45d47e59073..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.c +++ /dev/null @@ -1,652 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_i2c_dma.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c_dma" -#endif - -/*transfer = *xfer; - transfer = &(handle->transfer); - - handle->transferCount = 0U; - handle->remainingBytesDMA = 0U; - handle->buf = (uint8_t *)transfer->data; - handle->remainingSubaddr = 0U; - - if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) - { - handle->checkAddrNack = false; - /* Start condition shall not be ommited, switch directly to next phase */ - if (transfer->dataSize == 0U) - { - handle->state = (uint8_t)kStopState; - } - else if (handle->transfer.direction == kI2C_Write) - { - handle->state = (uint8_t)kTransmitDataState; - } - else if (handle->transfer.direction == kI2C_Read) - { - handle->state = (xfer->dataSize == 1U) ? (uint8_t)kReceiveLastDataState : (uint8_t)kReceiveDataState; - } - else - { - return kStatus_I2C_InvalidParameter; - } - } - else - { - if (transfer->subaddressSize != 0U) - { - int i; - uint32_t subaddress; - - if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) - { - return kStatus_I2C_InvalidParameter; - } - - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) - { - handle->subaddrBuf[i] = (uint8_t)subaddress & 0xffU; - subaddress >>= 8; - } - handle->remainingSubaddr = transfer->subaddressSize; - } - - handle->state = (uint8_t)kStartState; - handle->checkAddrNack = true; - } - - return kStatus_Success; -} - -static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - uint32_t transfer_size; - dma_transfer_config_t xferConfig; - uint32_t address; - address = (uint32_t)&base->MSTDAT; - - /* Update transfer count */ - int32_t count = handle->buf - (uint8_t *)handle->transfer.data; - assert(count >= 0); - handle->transferCount = (uint32_t)count; - - /* Check if there is anything to be transferred at all */ - if (handle->remainingBytesDMA == 0U) - { - /* No data to be transferrred, disable DMA */ - base->MSTCTL = 0; - return; - } - - /* Calculate transfer size */ - transfer_size = handle->remainingBytesDMA; - if (transfer_size > (uint32_t)I2C_MAX_DMA_TRANSFER_COUNT) - { - transfer_size = (uint32_t)I2C_MAX_DMA_TRANSFER_COUNT; - } - - switch (handle->transfer.direction) - { - case kI2C_Write: - DMA_PrepareTransfer(&xferConfig, handle->buf, (uint32_t *)address, sizeof(uint8_t), transfer_size, - kDMA_MemoryToPeripheral, NULL); - break; - - case kI2C_Read: - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, handle->buf, sizeof(uint8_t), transfer_size, - kDMA_PeripheralToMemory, NULL); - break; - - default: - /* This should never happen */ - assert(0); - break; - } - - (void)DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - DMA_StartTransfer(handle->dmaHandle); - - handle->remainingBytesDMA -= transfer_size; - handle->buf += transfer_size; - handle->checkAddrNack = false; -} - -static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone) -{ - uint32_t status; - uint32_t master_state; - struct _i2c_master_transfer *transfer; - dma_transfer_config_t xferConfig; - status_t err; - uint32_t start_flag = 0U; - uint32_t address; - address = (uint32_t)&base->MSTDAT; - - transfer = &(handle->transfer); - - *isDone = false; - - status = I2C_GetStatusFlags(base); - - if ((status & (uint32_t)I2C_STAT_MSTARBLOSS_MASK) != 0U) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_ArbitrationLost; - } - - if ((status & (uint32_t)I2C_STAT_MSTSTSTPERR_MASK) != 0U) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_StartStopError; - } - - /* Event timeout happens when the time since last bus event has been longer than the time specified by TIMEOUT - register. eg: Start signal fails to generate, no error status is set and transfer hangs if glitch on bus happens - before, the timeout status can be used to avoid the transfer hangs indefinitely. */ - if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) - { - I2C_ClearStatusFlags(base, (uint32_t)kI2C_EventTimeoutFlag); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_EventTimeout; - } - - /* SCL timeout happens when the slave is holding the SCL line low and the time has been longer than the time - specified by TIMEOUT register. */ - if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) - { - I2C_ClearStatusFlags(base, (uint32_t)kI2C_SclTimeoutFlag); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_SclLowTimeout; - } - - if ((status & (uint32_t)I2C_STAT_MSTPENDING_MASK) == 0U) - { - return kStatus_I2C_Busy; - } - - /* Get the state of the I2C module */ - master_state = (base->STAT & (uint32_t)I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (master_state == (uint32_t)I2C_STAT_MSTCODE_NACKDAT)) - { - /* Slave NACKed last byte, issue stop and return error */ - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = (uint8_t)kWaitForCompletionState; - if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (handle->checkAddrNack == true)) - { - return kStatus_I2C_Addr_Nak; - } - else - { - return kStatus_I2C_Nak; - } - } - - err = kStatus_Success; - - if (handle->state == (uint8_t)kStartState) - { - /* set start flag for later use */ - start_flag = I2C_MSTCTL_MSTSTART_MASK; - - if (handle->remainingSubaddr != 0U) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = (uint8_t)kTransmitSubaddrState; - } - else if (transfer->direction == kI2C_Write) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - if (transfer->dataSize == 0U) - { - /* No data to be transferred, initiate start and schedule stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - handle->state = (uint8_t)kStopState; - return err; - } - handle->state = (uint8_t)kTransmitDataState; - } - else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0U)) - { - base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; - if (transfer->dataSize == 1U) - { - /* The very last byte is always received by means of SW */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - handle->state = (uint8_t)kReceiveLastDataState; - return err; - } - handle->state = (uint8_t)kReceiveDataState; - } - else - { - handle->state = (uint8_t)kIdleState; - err = kStatus_I2C_UnexpectedState; - return err; - } - } - - switch (handle->state) - { - case (uint8_t)kTransmitSubaddrState: - if ((master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) && (0U == start_flag)) - { - return kStatus_I2C_UnexpectedState; - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - - /* Prepare and submit DMA transfer. */ - DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (uint32_t *)address, sizeof(uint8_t), - handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL); - (void)DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - DMA_StartTransfer(handle->dmaHandle); - handle->remainingSubaddr = 0; - if (transfer->dataSize != 0U) - { - /* There is data to be transferred, if there is write to read turnaround it is necessary to perform - * repeated start */ - handle->state = (transfer->direction == kI2C_Read) ? (uint8_t)kStartState : (uint8_t)kTransmitDataState; - } - else - { - /* No more data, schedule stop condition */ - handle->state = (uint8_t)kStopState; - } - break; - - case (uint8_t)kTransmitDataState: - if ((master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) && (0U == start_flag)) - { - return kStatus_I2C_UnexpectedState; - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - handle->remainingBytesDMA = handle->transfer.dataSize; - - I2C_RunDMATransfer(base, handle); - - /* Schedule stop condition */ - handle->state = (uint8_t)kStopState; - handle->checkAddrNack = false; - break; - - case (uint8_t)kReceiveDataState: - if ((master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) && (0U == start_flag)) - { - if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStartFlag)) - { - return kStatus_I2C_UnexpectedState; - } - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - handle->remainingBytesDMA = handle->transfer.dataSize - 1U; - - if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) - { - /* Read the master data register to avoid the data be read again */ - (void)base->MSTDAT; - } - I2C_RunDMATransfer(base, handle); - - /* Schedule reception of last data byte */ - handle->state = (uint8_t)kReceiveLastDataState; - handle->checkAddrNack = false; - break; - - case (uint8_t)kReceiveLastDataState: - if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) - { - return kStatus_I2C_UnexpectedState; - } - - ((uint8_t *)transfer->data)[transfer->dataSize - 1U] = (uint8_t)base->MSTDAT; - handle->transferCount++; - - /* No more data expected, issue NACK and STOP right away */ - if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStopFlag)) - { - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - } - handle->state = (uint8_t)kWaitForCompletionState; - break; - - case (uint8_t)kStopState: - if ((transfer->flags & (uint32_t)kI2C_TransferNoStopFlag) != 0U) - { - /* Stop condition is omitted, we are done */ - *isDone = true; - handle->state = (uint8_t)kIdleState; - break; - } - /* Send stop condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = (uint8_t)kWaitForCompletionState; - break; - - case (uint8_t)kWaitForCompletionState: - *isDone = true; - handle->state = (uint8_t)kIdleState; - break; - - case (uint8_t)kStartState: - case (uint8_t)kIdleState: - default: - /* State machine shall not be invoked again once it enters the idle state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - return err; -} - -static void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - bool isDone; - status_t result; - - /* Don't do anything if we don't have a valid handle. */ - if (NULL == handle) - { - return; - } - - result = I2C_RunTransferStateMachineDMA(base, handle, &isDone); - - if ((result != kStatus_Success) || isDone) - { - /* Restore handle to idle state. */ - handle->state = (uint8_t)kIdleState; - - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | - I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); - - /* Invoke callback. */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } -} - -static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) -{ - i2c_master_dma_private_handle_t *dmaPrivateHandle; - - /* Don't do anything if we don't have a valid handle. */ - if (NULL == handle) - { - return; - } - - dmaPrivateHandle = (i2c_master_dma_private_handle_t *)userData; - I2C_RunDMATransfer(dmaPrivateHandle->base, dmaPrivateHandle->handle); -} - -/*! - * brief Init the I2C handle which is used in transactional functions - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - * param callback pointer to user callback function - * param userData user param passed to the callback function - * param dmaHandle DMA handle pointer - */ -void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, - i2c_master_dma_handle_t *handle, - i2c_master_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *dmaHandle) -{ - assert(handle != NULL); - assert(dmaHandle != NULL); - - uint32_t instance; - i2c_dma_to_flexcomm_t handler; - handler.i2c_dma_master_handler = I2C_MasterTransferDMAHandleIRQ; - - /* Zero handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Set the user callback and userData. */ - handle->completionCallback = callback; - handle->userData = userData; - - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | - I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); - (void)EnableIRQ(s_i2cIRQ[instance]); - - /* Set the handle for DMA. */ - handle->dmaHandle = dmaHandle; - - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - DMA_SetCallback(dmaHandle, I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]); -} - -/*! - * brief Performs a master dma non-blocking transfer on the I2C bus - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - * param xfer pointer to transfer structure of i2c_master_transfer_t - * retval kStatus_Success Sucessully complete the data transmission. - * retval kStatus_I2C_Busy Previous transmission still not finished. - * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. - */ -status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer) -{ - status_t result; - - assert(handle != NULL); - assert(xfer != NULL); - assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); - - /* Return busy if another transaction is in progress. */ - if (handle->state != (uint8_t)kIdleState) - { - return kStatus_I2C_Busy; - } - - /* Prepare transfer state machine. */ - result = I2C_InitTransferStateMachineDMA(base, handle, xfer); - - /* Clear error flags. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Enable I2C internal IRQ sources */ - /* Enable arbitration lost interrupt, start/stop error interrupt and master pending interrupt. - The master pending flag is not set during dma transfer. */ - I2C_EnableInterrupts(base, I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | - I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); - - return result; -} - -/*! - * brief Get master transfer status during a dma non-blocking transfer - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - * param count Number of bytes transferred so far by the non-blocking transaction. - */ -status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state == (uint8_t)kIdleState) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* There is no necessity to disable interrupts as we read a single integer value */ - *count = handle->transferCount; - return kStatus_Success; -} - -/*! - * brief Abort a master dma non-blocking transfer in a early time - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - */ -void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - uint32_t status; - uint32_t master_state; - - if (handle->state != (uint8_t)kIdleState) - { - DMA_AbortTransfer(handle->dmaHandle); - - /* Disable DMA */ - base->MSTCTL = 0; - - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | - I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); - - /* Wait until module is ready */ - do - { - status = I2C_GetStatusFlags(base); - } while ((status & (uint8_t)I2C_STAT_MSTPENDING_MASK) == 0U); - - /* Clear controller state. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Get the state of the I2C module */ - master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if (master_state != (uint32_t)I2C_STAT_MSTCODE_IDLE) - { - /* Send a stop command to finalize the transfer. */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - - /* Wait until module is ready */ - do - { - status = I2C_GetStatusFlags(base); - } while ((status & (uint32_t)I2C_STAT_MSTPENDING_MASK) == 0U); - - /* Clear controller state. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - } - - /* Reset the state to idle. */ - handle->state = (uint8_t)kIdleState; - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.h deleted file mode 100644 index 07899f9c7c9..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2C_DMA_H_ -#define _FSL_I2C_DMA_H_ - -#include "fsl_i2c.h" -#include "fsl_dma.h" - -/*! - * @addtogroup i2c_dma_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2C DMA driver version. */ -#define FSL_I2C_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) -/*@}*/ - -/*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */ -#define I2C_MAX_DMA_TRANSFER_COUNT 1024 - -/*! @brief I2C master dma handle typedef. */ -typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t; - -/*! @brief I2C master dma transfer callback typedef. */ -typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base, - i2c_master_dma_handle_t *handle, - status_t status, - void *userData); - -/*! @brief Typedef for master dma handler. */ -typedef void (*flexcomm_i2c_dma_master_irq_handler_t)(I2C_Type *base, i2c_master_dma_handle_t *handle); - -/*! @brief I2C master dma transfer structure. */ -struct _i2c_master_dma_handle -{ - uint8_t state; /*!< Transfer state machine current state. */ - uint32_t transferCount; /*!< Indicates progress of the transfer */ - uint32_t remainingBytesDMA; /*!< Remaining byte count to be transferred using DMA. */ - uint8_t *buf; /*!< Buffer pointer for current state. */ - uint32_t remainingSubaddr; - uint8_t subaddrBuf[4]; - bool checkAddrNack; /*!< Whether to check the nack signal is detected during addressing. */ - dma_handle_t *dmaHandle; /*!< The DMA handler used. */ - i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ - i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */ - void *userData; /*!< Callback parameter passed to callback function. */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus. */ - -/*! - * @name I2C Block DMA Transfer Operation - * @{ - */ - -/*! - * @brief Init the I2C handle which is used in transactional functions - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param callback pointer to user callback function - * @param userData user param passed to the callback function - * @param dmaHandle DMA handle pointer - */ -void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, - i2c_master_dma_handle_t *handle, - i2c_master_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *dmaHandle); - -/*! - * @brief Performs a master dma non-blocking transfer on the I2C bus - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param xfer pointer to transfer structure of i2c_master_transfer_t - * @retval kStatus_Success Sucessully complete the data transmission. - * @retval kStatus_I2C_Busy Previous transmission still not finished. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. - */ -status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Get master transfer status during a dma non-blocking transfer - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param count Number of bytes transferred so far by the non-blocking transaction. - */ -status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count); - -/*! - * @brief Abort a master dma non-blocking transfer in a early time - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - */ -void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle); - -/* @} */ -#if defined(__cplusplus) -} -#endif /*_cplusplus. */ -/*@}*/ -#endif /*_FSL_I2C_DMA_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_freertos.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_freertos.c deleted file mode 100644 index 9b700df46a6..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_freertos.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_i2c_freertos.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c_freertos" -#endif - -static void I2C_RTOS_Callback(I2C_Type *base, i2c_master_handle_t *drv_handle, status_t status, void *userData) -{ - i2c_rtos_handle_t *handle = (i2c_rtos_handle_t *)userData; - BaseType_t reschedule; - handle->async_status = status; - (void)xSemaphoreGiveFromISR(handle->semaphore, &reschedule); - portYIELD_FROM_ISR(reschedule); -} - -/*! - * brief Initializes I2C. - * - * This function initializes the I2C module and the related RTOS context. - * - * param handle The RTOS I2C handle, the pointer to an allocated space for RTOS context. - * param base The pointer base address of the I2C instance to initialize. - * param masterConfig Configuration structure to set-up I2C in master mode. - * param srcClock_Hz Frequency of input clock of the I2C module. - * return status of the operation. - */ -status_t I2C_RTOS_Init(i2c_rtos_handle_t *handle, - I2C_Type *base, - const i2c_master_config_t *masterConfig, - uint32_t srcClock_Hz) -{ - if (handle == NULL) - { - return kStatus_InvalidArgument; - } - - if (base == NULL) - { - return kStatus_InvalidArgument; - } - - (void)memset(handle, 0, sizeof(i2c_rtos_handle_t)); - - handle->mutex = xSemaphoreCreateMutex(); - if (handle->mutex == NULL) - { - return kStatus_Fail; - } - - handle->semaphore = xSemaphoreCreateBinary(); - if (handle->semaphore == NULL) - { - vSemaphoreDelete(handle->mutex); - return kStatus_Fail; - } - - handle->base = base; - - I2C_MasterInit(handle->base, masterConfig, srcClock_Hz); - I2C_MasterTransferCreateHandle(base, &handle->drv_handle, I2C_RTOS_Callback, (void *)handle); - - return kStatus_Success; -} - -/*! - * brief Deinitializes the I2C. - * - * This function deinitializes the I2C module and the related RTOS context. - * - * param handle The RTOS I2C handle. - */ -status_t I2C_RTOS_Deinit(i2c_rtos_handle_t *handle) -{ - I2C_MasterDeinit(handle->base); - - vSemaphoreDelete(handle->semaphore); - vSemaphoreDelete(handle->mutex); - - return kStatus_Success; -} - -/*! - * brief Performs I2C transfer. - * - * This function performs an I2C transfer according to data given in the transfer structure. - * - * param handle The RTOS I2C handle. - * param transfer Structure specifying the transfer parameters. - * return status of the operation. - */ -status_t I2C_RTOS_Transfer(i2c_rtos_handle_t *handle, i2c_master_transfer_t *transfer) -{ - status_t status; - - /* Lock resource mutex */ - if (xSemaphoreTake(handle->mutex, portMAX_DELAY) != pdTRUE) - { - return kStatus_I2C_Busy; - } - - status = I2C_MasterTransferNonBlocking(handle->base, &handle->drv_handle, transfer); - if (status != kStatus_Success) - { - (void)xSemaphoreGive(handle->mutex); - return status; - } - - /* Wait for transfer to finish */ - (void)xSemaphoreTake(handle->semaphore, portMAX_DELAY); - - /* Unlock resource mutex */ - (void)xSemaphoreGive(handle->mutex); - - /* Return status captured by callback function */ - return handle->async_status; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_freertos.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_freertos.h deleted file mode 100644 index 1e929496d5c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_freertos.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef __FSL_I2C_FREERTOS_H__ -#define __FSL_I2C_FREERTOS_H__ - -#include "FreeRTOS.h" -#include "portable.h" -#include "semphr.h" - -#include "fsl_i2c.h" - -/*! - * @addtogroup i2c_freertos_driver I2C FreeRTOS Driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2C FreeRTOS driver version 2.0.8. */ -#define FSL_I2C_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 0, 8)) -/*@}*/ - -/*! @brief I2C FreeRTOS handle */ -typedef struct _i2c_rtos_handle -{ - I2C_Type *base; /*!< I2C base address */ - i2c_master_handle_t drv_handle; /*!< A handle of the underlying driver, treated as opaque by the RTOS layer */ - status_t async_status; /*!< Transactional state of the underlying driver */ - SemaphoreHandle_t mutex; /*!< A mutex to lock the handle during a transfer */ - SemaphoreHandle_t semaphore; /*!< A semaphore to notify and unblock task when the transfer ends */ -#if (configSUPPORT_STATIC_ALLOCATION == 1) - StaticSemaphore_t mutexBuffer; /*!< Statically allocated memory for mutex */ - StaticSemaphore_t semaphoreBuffer; /*!< Statically allocated memory for semaphore */ -#endif -} i2c_rtos_handle_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name I2C RTOS Operation - * @{ - */ - -/*! - * @brief Initializes I2C. - * - * This function initializes the I2C module and the related RTOS context. - * - * @param handle The RTOS I2C handle, the pointer to an allocated space for RTOS context. - * @param base The pointer base address of the I2C instance to initialize. - * @param masterConfig Configuration structure to set-up I2C in master mode. - * @param srcClock_Hz Frequency of input clock of the I2C module. - * @return status of the operation. - */ -status_t I2C_RTOS_Init(i2c_rtos_handle_t *handle, - I2C_Type *base, - const i2c_master_config_t *masterConfig, - uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes the I2C. - * - * This function deinitializes the I2C module and the related RTOS context. - * - * @param handle The RTOS I2C handle. - */ -status_t I2C_RTOS_Deinit(i2c_rtos_handle_t *handle); - -/*! - * @brief Performs I2C transfer. - * - * This function performs an I2C transfer according to data given in the transfer structure. - * - * @param handle The RTOS I2C handle. - * @param transfer Structure specifying the transfer parameters. - * @return status of the operation. - */ -status_t I2C_RTOS_Transfer(i2c_rtos_handle_t *handle, i2c_master_transfer_t *transfer); - -/*! - * @} - */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* __FSL_I2C_FREERTOS_H__ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s.c deleted file mode 100644 index c13f2f4bcd4..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s.c +++ /dev/null @@ -1,1198 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_i2s.h" -#include "fsl_flexcomm.h" -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s" -#endif - -/* TODO - absent in device header files, should be there */ -#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) -#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) -#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) -#define I2S_FIFOCFG_PACK48_MASK (0x8U) -#define I2S_FIFOCFG_PACK48_SHIFT (3U) -#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) -/*! @brief i2s empty tx fifo timeout value */ -#define I2S_FIFO_DEPTH (8U) -#define I2S_TX_ONE_SAMPLE_MAX_TIMEOUT (125U) /* 8K/8bit one sample need 125us*/ -#define I2S_TX_FIFO_EMPTY_TIMEOUT(count) (count) * I2S_TX_ONE_SAMPLE_MAX_TIMEOUT -/*! @brief _i2s_state I2S states. */ -enum -{ - kI2S_StateIdle = 0x0, /*!< Not performing transfer */ - kI2S_StateTx, /*!< Performing transmit */ - kI2S_StateTxWaitToWriteDummyData, /*!< Wait on FIFO in order to write final dummy data there */ - kI2S_StateTxWaitForEmptyFifo, /*!< Wait for FIFO to be flushed */ - kI2S_StateRx, /*!< Performing receive */ -}; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -static void I2S_Config(I2S_Type *base, const i2s_config_t *config); -static void I2S_TxEnable(I2S_Type *base, bool enable); -static void I2S_RxEnable(I2S_Type *base, bool enable); -static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map i2c instance number to base address. */ -static const uint32_t s_i2sBaseAddrs[] = I2S_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_i2sIRQ[] = I2S_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! - * @brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * @param base The I2S peripheral base address. - * @return I2S instance number starting from 0. - */ -static uint32_t I2S_GetInstance(I2S_Type *base) -{ - uint32_t i; - for (i = 0; i < (uint32_t)ARRAY_SIZE(s_i2sBaseAddrs); i++) - { - if ((uint32_t)base == s_i2sBaseAddrs[i]) - { - return i; - } - } - assert(false); - return 0; -} - -/*! - * brief Transmitter bit clock rate configurations. - * - * param base SAI base pointer. - * param sourceClockHz, bit clock source frequency. - * param sampleRate audio data sample rate. - * param bitWidth, audio data bitWidth. - * param channelNumbers, audio channel numbers. - */ -void I2S_SetBitClockRate( - I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers) -{ - uint32_t bitClockDivider = sourceClockHz / sampleRate / bitWidth / channelNumbers; - - assert(bitClockDivider >= 1U); - base->DIV = I2S_DIV_DIV(bitClockDivider - 1U); -} - -/*! - * brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S transmission using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_TxGetDefaultConfig(). - * - * note This API should be called at the beginning of the application to use - * the I2S driver. - * - * param base I2S base pointer. - * param config pointer to I2S configuration structure. - */ -void I2S_TxInit(I2S_Type *base, const i2s_config_t *config) -{ - uint32_t cfg = 0U; - uint32_t trig = 0U; - - (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_TX); - I2S_Config(base, config); - - /* Configure FIFO */ - - cfg |= I2S_FIFOCFG_ENABLETX(1U); /* enable TX FIFO */ - cfg |= I2S_FIFOCFG_EMPTYTX(1U); /* empty TX FIFO */ - cfg |= I2S_FIFOCFG_TXI2SE0(config->txEmptyZero); /* transmit zero when buffer becomes empty or last item */ - cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ - trig |= I2S_FIFOTRIG_TXLVLENA(1U); /* enable TX FIFO trigger */ - trig |= I2S_FIFOTRIG_TXLVL(config->watermark); /* set TX FIFO trigger level */ - - base->FIFOCFG = cfg; - base->FIFOTRIG = trig; -} - -/*! - * brief Initializes the FLEXCOMM peripheral for I2S receive functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S receive using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_RxGetDefaultConfig(). - * - * note This API should be called at the beginning of the application to use - * the I2S driver. - * - * param base I2S base pointer. - * param config pointer to I2S configuration structure. - */ -void I2S_RxInit(I2S_Type *base, const i2s_config_t *config) -{ - uint32_t cfg = 0U; - uint32_t trig = 0U; - - (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_RX); - I2S_Config(base, config); - - /* Configure FIFO */ - - cfg |= I2S_FIFOCFG_ENABLERX(1U); /* enable RX FIFO */ - cfg |= I2S_FIFOCFG_EMPTYRX(1U); /* empty RX FIFO */ - cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ - trig |= I2S_FIFOTRIG_RXLVLENA(1U); /* enable RX FIFO trigger */ - trig |= I2S_FIFOTRIG_RXLVL(config->watermark); /* set RX FIFO trigger level */ - - base->FIFOCFG = cfg; - base->FIFOTRIG = trig; -} - -/*! - * brief Flush the valid data in TX fifo. - * - * param base I2S base pointer. - * return kStatus_Fail empty TX fifo failed, kStatus_Success empty tx fifo success. - */ -status_t I2S_EmptyTxFifo(I2S_Type *base) -{ - uint32_t timeout = I2S_TX_FIFO_EMPTY_TIMEOUT(I2S_FIFO_DEPTH); - - while (((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) && (timeout != 0U)) - { - timeout -= I2S_TX_ONE_SAMPLE_MAX_TIMEOUT; - SDK_DelayAtLeastUs(I2S_TX_ONE_SAMPLE_MAX_TIMEOUT, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - } - - /* The last piece of valid data can be still being transmitted from I2S at this moment */ - timeout = I2S_TX_ONE_SAMPLE_MAX_TIMEOUT; - /* Write additional data to FIFO */ - base->FIFOWR = 0U; - while (((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) && (timeout != 0U)) - { - timeout -= I2S_TX_ONE_SAMPLE_MAX_TIMEOUT; - SDK_DelayAtLeastUs(I2S_TX_ONE_SAMPLE_MAX_TIMEOUT, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - } - - return ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) ? kStatus_Fail : kStatus_Success; -} - -/*! - * brief Sets the I2S Tx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_TxInit(). - * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified - * before calling I2S_TxInit(). - * Example: - code - i2s_config_t config; - I2S_TxGetDefaultConfig(&config); - endcode - * - * Default values: - * code - * config->masterSlave = kI2S_MasterSlaveNormalMaster; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = true; - * config->pack48 = false; - * endcode - * - * param config pointer to I2S configuration structure. - */ -void I2S_TxGetDefaultConfig(i2s_config_t *config) -{ - config->masterSlave = kI2S_MasterSlaveNormalMaster; - config->mode = kI2S_ModeI2sClassic; - config->rightLow = false; - config->leftJust = false; -#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) - config->pdmData = false; -#endif - config->sckPol = false; - config->wsPol = false; - config->divider = 1U; - config->oneChannel = false; - config->dataLength = 16U; - config->frameLength = 32U; - config->position = 0U; - config->watermark = 4U; - config->txEmptyZero = true; - config->pack48 = false; -} - -/*! - * brief Sets the I2S Rx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_RxInit(). - * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified - * before calling I2S_RxInit(). - * Example: - code - i2s_config_t config; - I2S_RxGetDefaultConfig(&config); - endcode - * - * Default values: - * code - * config->masterSlave = kI2S_MasterSlaveNormalSlave; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = false; - * config->pack48 = false; - * endcode - * - * param config pointer to I2S configuration structure. - */ -void I2S_RxGetDefaultConfig(i2s_config_t *config) -{ - config->masterSlave = kI2S_MasterSlaveNormalSlave; - config->mode = kI2S_ModeI2sClassic; - config->rightLow = false; - config->leftJust = false; -#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) - config->pdmData = false; -#endif - config->sckPol = false; - config->wsPol = false; - config->divider = 1U; - config->oneChannel = false; - config->dataLength = 16U; - config->frameLength = 32U; - config->position = 0U; - config->watermark = 4U; - config->txEmptyZero = false; - config->pack48 = false; -} - -static void I2S_Config(I2S_Type *base, const i2s_config_t *config) -{ - assert(config != NULL); - - uint32_t cfg1 = 0U; - uint32_t cfg2 = 0U; - - /* set master/slave configuration */ - cfg1 |= I2S_CFG1_MSTSLVCFG(config->masterSlave); - - /* set I2S mode */ - cfg1 |= I2S_CFG1_MODE(config->mode); - - /* set right low (channel swap) */ - cfg1 |= I2S_CFG1_RIGHTLOW(config->rightLow); - - /* set data justification */ - cfg1 |= I2S_CFG1_LEFTJUST(config->leftJust); - -#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) - if (FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn((FLEXCOMM_Type *)(uint32_t)base) > 0) - { - /* set source to PDM dmic */ - cfg1 |= I2S_CFG1_PDMDATA(config->pdmData); - } -#endif - - /* set SCLK polarity */ - cfg1 |= I2S_CFG1_SCK_POL(config->sckPol); - - /* set WS polarity */ - cfg1 |= I2S_CFG1_WS_POL(config->wsPol); - - /* set mono mode */ - cfg1 |= I2S_CFG1_ONECHANNEL(config->oneChannel); - - /* set data length */ - cfg1 |= I2S_CFG1_DATALEN(config->dataLength - 1UL); - - /* set frame length */ - cfg2 |= I2S_CFG2_FRAMELEN(config->frameLength - 1UL); - - /* set data position of this channel pair within the frame */ - cfg2 |= I2S_CFG2_POSITION(config->position); - - /* write to registers */ - base->CFG1 = cfg1; - base->CFG2 = cfg2; - - /* set the clock divider */ - base->DIV = I2S_DIV_DIV(config->divider - 1UL); -} - -/*! - * brief De-initializes the I2S peripheral. - * - * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit - * or I2S_RxInit is called to enable the clock. - * - * param base I2S base pointer. - */ -void I2S_Deinit(I2S_Type *base) -{ - /* TODO gate FLEXCOMM clock via FLEXCOMM driver */ -} - -static void I2S_TxEnable(I2S_Type *base, bool enable) -{ - if (enable) - { - I2S_Enable(base); - I2S_EnableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); - } - else - { - I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); - I2S_Disable(base); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - } -} - -static void I2S_RxEnable(I2S_Type *base, bool enable) -{ - if (enable) - { - I2S_Enable(base); - I2S_EnableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); - } - else - { - I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); - I2S_Disable(base); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - } -} - -static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer) -{ - assert(transfer->data != NULL); - - if (transfer->data == NULL) - { - return kStatus_InvalidArgument; - } - - assert(transfer->dataSize > 0U); - if (transfer->dataSize <= 0U) - { - return kStatus_InvalidArgument; - } - - if (handle->dataLength == 4U) - { - /* No alignment and data length requirements */ - } - else if ((handle->dataLength >= 5U) && (handle->dataLength <= 8U)) - { - assert((((uint32_t)transfer->data) % 2U) == 0U); - if ((((uint32_t)transfer->data) % 2U) != 0U) - { - /* Data not 2-bytes aligned */ - return kStatus_InvalidArgument; - } - - assert((transfer->dataSize % 2U) == 0U); - if ((transfer->dataSize % 2U) != 0U) - { - /* Data not in pairs of left/right channel bytes */ - return kStatus_InvalidArgument; - } - } - else if ((handle->dataLength >= 9U) && (handle->dataLength <= 16U)) - { - assert((((uint32_t)transfer->data) % 4U) == 0U); - if ((((uint32_t)transfer->data) % 4U) != 0U) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - - assert((transfer->dataSize % 4U) == 0U); - if ((transfer->dataSize % 4U) != 0U) - { - /* Data lenght not multiply of 4 */ - return kStatus_InvalidArgument; - } - } - else if ((handle->dataLength >= 17U) && (handle->dataLength <= 24U)) - { - assert((transfer->dataSize % 6U) == 0U); - if ((transfer->dataSize % 6U) != 0U) - { - /* Data lenght not multiply of 6 */ - return kStatus_InvalidArgument; - } - - assert(!((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U))); - if ((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U)) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - } - else /* if (handle->dataLength >= 25U) */ - { - assert((((uint32_t)transfer->data) % 4U) == 0U); - if ((((uint32_t)transfer->data) % 4U) != 0U) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - - if (handle->oneChannel) - { - assert((transfer->dataSize % 4U) == 0U); - if ((transfer->dataSize % 4U) != 0U) - { - /* Data lenght not multiply of 4 */ - return kStatus_InvalidArgument; - } - } - else - { - assert((transfer->dataSize % 8U) == 0U); - if ((transfer->dataSize % 8U) != 0U) - { - /* Data lenght not multiply of 8 */ - return kStatus_InvalidArgument; - } - } - } - - return kStatus_Success; -} - -#if (defined(FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) && FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) -/*! - * brief Enables I2S secondary channel. - * - * param base I2S base pointer. - * param channel seondary channel channel number, reference _i2s_secondary_channel. - * param oneChannel true is treated as single channel, functionality left channel for this pair. - * param position define the location within the frame of the data, should not bigger than 0x1FFU. - */ -void I2S_EnableSecondaryChannel(I2S_Type *base, uint32_t channel, bool oneChannel, uint32_t position) -{ - assert(channel <= (uint32_t)kI2S_SecondaryChannel3); -#if defined FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn - assert(FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn((FLEXCOMM_Type *)(uint32_t)base) == 1); -#endif - - uint32_t pcfg1 = base->SECCHANNEL[channel].PCFG1; - uint32_t pcfg2 = base->SECCHANNEL[channel].PCFG2; - - pcfg1 &= ~I2S_CFG1_ONECHANNEL_MASK; - pcfg1 |= I2S_CFG1_MAINENABLE_MASK | I2S_CFG1_ONECHANNEL(oneChannel); - - pcfg2 &= ~I2S_CFG2_POSITION_MASK; - pcfg2 |= I2S_CFG2_POSITION(position); - - base->SECCHANNEL[channel].PCFG1 = pcfg1; - base->SECCHANNEL[channel].PCFG2 = pcfg2; -} -#endif - -/*! - * brief Initializes handle for transfer of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) -{ - assert(handle != NULL); - - uint32_t instance; - - /* Clear out the handle */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2S_GetInstance(base); - - /* Save callback and user data */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Remember some items set previously by configuration */ - handle->watermark = (uint8_t)((base->FIFOTRIG & I2S_FIFOTRIG_TXLVL_MASK) >> I2S_FIFOTRIG_TXLVL_SHIFT); - handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT) != 0U ? true : false; - handle->dataLength = (uint8_t)((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; - handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT) != 0u ? true : false; - - handle->useFifo48H = false; - - /* Register IRQ handling */ - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_TxHandleIRQ, handle); - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); - (void)EnableIRQ(s_i2sIRQ[instance]); -} - -/*! - * brief Begins or queue sending of the given data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) -{ - assert(handle != NULL); - - status_t result; - - if (handle == NULL) - { - return kStatus_InvalidArgument; - } - - result = I2S_ValidateBuffer(handle, &transfer); - if (result != kStatus_Success) - { - return result; - } - - if (handle->i2sQueue[handle->queueUser].dataSize != 0UL) - { - /* Previously prepared buffers not processed yet */ - return kStatus_I2S_Busy; - } - - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_TXLVL_MASK)) | I2S_FIFOTRIG_TXLVL(handle->watermark); - I2S_TxEnable(base, true); - - return kStatus_Success; -} - -/*! - * brief Aborts sending of data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle) -{ - assert(handle != NULL); - - /* Disable I2S operation and interrupts */ - I2S_TxEnable(base, false); - - /* Reset state */ - handle->state = (uint32_t)kI2S_StateIdle; - - /* Clear transfer queue */ - (void)memset((void *)&handle->i2sQueue, 0, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); - handle->queueDriver = 0U; - handle->queueUser = 0U; -} - -/*! - * brief Initializes handle for reception of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) -{ - assert(handle != NULL); - - uint32_t instance; - - /* Clear out the handle */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2S_GetInstance(base); - - /* Save callback and user data */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Remember some items set previously by configuration */ - handle->watermark = (uint8_t)((base->FIFOTRIG & I2S_FIFOTRIG_RXLVL_MASK) >> I2S_FIFOTRIG_RXLVL_SHIFT); - handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT) != 0UL ? true : false; - handle->dataLength = (uint8_t)((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; - handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT) != 0UL ? true : false; - - handle->useFifo48H = false; - - /* Register IRQ handling */ - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_RxHandleIRQ, handle); - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); - - (void)EnableIRQ(s_i2sIRQ[instance]); -} - -/*! - * brief Begins or queue reception of data into given buffer. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. - */ -status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) -{ - assert(handle != NULL); - - status_t result; - - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - result = I2S_ValidateBuffer(handle, &transfer); - if (result != kStatus_Success) - { - return result; - } - - if (handle->i2sQueue[handle->queueUser].dataSize != 0UL) - { - /* Previously prepared buffers not processed yet */ - return kStatus_I2S_Busy; - } - - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_RXLVL_MASK)) | I2S_FIFOTRIG_RXLVL(handle->watermark); - I2S_RxEnable(base, true); - - return kStatus_Success; -} - -/*! - * brief Aborts receiving of data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle) -{ - assert(handle != NULL); - - /* Disable I2S operation and interrupts */ - I2S_RxEnable(base, false); - - /* Reset state */ - handle->state = (uint32_t)kI2S_StateIdle; - - /* Clear transfer queue */ - (void)memset((void *)&handle->i2sQueue, 0, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); - handle->queueDriver = 0U; - handle->queueUser = 0U; -} - -/*! - * brief Returns number of bytes transferred so far. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param[out] count number of bytes transferred so far by the non-blocking transaction. - * - * retval kStatus_Success - * retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - assert(count != NULL); - - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - if (handle->state == (uint32_t)kI2S_StateIdle) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->transferCount; - - return kStatus_Success; -} - -/*! - * brief Returns number of buffer underruns or overruns. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param[out] count number of transmit errors encountered so far by the non-blocking transaction. - * - * retval kStatus_Success - * retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - assert(count != NULL); - - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - if (handle->state == (uint32_t)kI2S_StateIdle) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->errorCount; - - return kStatus_Success; -} - -/*! - * brief Invoked from interrupt handler when transmit FIFO level decreases. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) -{ - uint32_t intstat = base->FIFOINTSTAT; - uint32_t data; - uint8_t queueDriverIndex = handle->queueDriver; - uint32_t dataAddr = (uint32_t)handle->i2sQueue[queueDriverIndex].data; - uint32_t dataSize = handle->i2sQueue[queueDriverIndex].dataSize; - - if ((intstat & I2S_FIFOINTSTAT_TXERR_MASK) != 0UL) - { - handle->errorCount++; - - /* Clear TX error interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_TXERR(1U); - } - - if ((intstat & I2S_FIFOINTSTAT_TXLVL_MASK) != 0UL) - { - if ((handle->state != (uint32_t)kI2S_StateTx) && (dataSize != 0U) && (dataAddr != 0U)) - { - handle->state = (uint32_t)kI2S_StateTx; - } - - if (handle->state == (uint32_t)kI2S_StateTx) - { - /* Send data */ - - while (((base->FIFOSTAT & I2S_FIFOSTAT_TXNOTFULL_MASK) != 0UL) && (dataSize > 0U)) - { - /* Write output data */ - if (handle->dataLength == 4U) - { - data = *((uint8_t *)dataAddr); - base->FIFOWR = ((data & 0xF0U) << 12U) | (data & 0xFU); - dataAddr++; - handle->transferCount++; - dataSize--; - } - else if (handle->dataLength <= 8U) - { - data = *((volatile uint16_t *)dataAddr); - if (handle->oneChannel) - { - base->FIFOWR = (data & 0xFFU); - dataAddr += sizeof(uint8_t); - handle->transferCount += sizeof(uint8_t); - dataSize -= sizeof(uint8_t); - } - else - { - base->FIFOWR = ((data & 0xFF00U) << 8U) | (data & 0xFFU); - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - } - else if (handle->dataLength <= 16U) - { - data = *((volatile uint32_t *)(dataAddr)); - if (handle->oneChannel) - { - base->FIFOWR = data & 0xFFFFU; - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - else - { - base->FIFOWR = data; - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - } - else if (handle->dataLength <= 24U) - { - if (handle->pack48) - { - if (handle->useFifo48H) - { - base->FIFOWR48H = *((volatile uint16_t *)(dataAddr)); - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - handle->useFifo48H = false; - } - else - { - base->FIFOWR = *((volatile uint32_t *)(dataAddr)); - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - handle->useFifo48H = true; - } - } - else - { - data = (uint32_t)(*(uint8_t *)(dataAddr++)); - data |= ((uint32_t)(*(uint8_t *)(dataAddr++))) << 8U; - data |= ((uint32_t)(*(uint8_t *)(dataAddr++))) << 16U; - if ((handle->useFifo48H) && (handle->oneChannel == false)) - { - base->FIFOWR48H = data; - handle->useFifo48H = false; - } - else - { - base->FIFOWR = data; - handle->useFifo48H = true; - } - handle->transferCount += 3U; - dataSize -= 3U; - } - } - else /* if (handle->dataLength <= 32U) */ - { - base->FIFOWR = *((volatile uint32_t *)(dataAddr)); - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - - if (dataSize == 0U) - { - handle->i2sQueue[queueDriverIndex].dataSize = 0U; - /* Actual data buffer sent out, switch to a next one */ - handle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; - - /* Notify user */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); - } - - /* Check if the next buffer contains anything to send */ - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* Everything has been written to FIFO */ - handle->state = kI2S_StateTxWaitToWriteDummyData; - break; - } - } - else - { - handle->i2sQueue[queueDriverIndex].dataSize = dataSize; - handle->i2sQueue[queueDriverIndex].data = (uint8_t *)dataAddr; - } - } - } - else if (handle->state == (uint32_t)kI2S_StateTxWaitToWriteDummyData) - { - /* Write dummy data */ - if ((handle->dataLength > 16U) && (handle->dataLength < 25U)) - { - if (handle->useFifo48H) - { - base->FIFOWR48H = 0U; - handle->useFifo48H = false; - } - else - { - base->FIFOWR = 0U; - base->FIFOWR48H = 0U; - } - } - else - { - base->FIFOWR = 0U; - } - - /* Next time invoke this handler when FIFO becomes empty (TX level 0) */ - base->FIFOTRIG &= ~I2S_FIFOTRIG_TXLVL_MASK; - handle->state = (uint32_t)kI2S_StateTxWaitForEmptyFifo; - } - else if (handle->state == (uint32_t)kI2S_StateTxWaitForEmptyFifo) - { - /* FIFO, including additional dummy data, has been emptied now, - * all relevant data should have been output from peripheral */ - - /* Stop transfer */ - I2S_Disable(base); - I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - - /* Reset state */ - handle->state = (uint32_t)kI2S_StateIdle; - - /* Notify user */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); - } - } - else - { - /* Do nothing */ - } - - /* Clear TX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_TXLVL(1U); - } -} - -/*! - * brief Invoked from interrupt handler when receive FIFO level decreases. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) -{ - uint32_t intstat = base->FIFOINTSTAT; - uint32_t data; - uint8_t queueDriverIndex = handle->queueDriver; - uint32_t dataAddr = (uint32_t)handle->i2sQueue[queueDriverIndex].data; - uint32_t dataSize = handle->i2sQueue[queueDriverIndex].dataSize; - - if ((intstat & I2S_FIFOINTSTAT_RXERR_MASK) != 0UL) - { - handle->errorCount++; - - /* Clear RX error interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXERR(1U); - } - - if ((intstat & I2S_FIFOINTSTAT_RXLVL_MASK) != 0UL) - { - while (((base->FIFOSTAT & I2S_FIFOSTAT_RXNOTEMPTY_MASK) != 0UL) && (dataSize > 0U)) - { - /* Read input data */ - if (handle->dataLength == 4U) - { - data = base->FIFORD; - *((uint8_t *)dataAddr) = (uint8_t)(((data & 0x000F0000U) >> 12U) | (data & 0x0000000FU)); - dataAddr++; - handle->transferCount++; - dataSize--; - } - else if (handle->dataLength <= 8U) - { - data = base->FIFORD; - - if (handle->oneChannel) - { - *((volatile uint8_t *)dataAddr) = (uint8_t)(data & 0xFFU); - dataAddr += sizeof(uint8_t); - handle->transferCount += sizeof(uint8_t); - dataSize -= sizeof(uint8_t); - } - else - { - *((volatile uint16_t *)dataAddr) = (uint16_t)(((data >> 8U) & 0xFF00U) | (data & 0xFFU)); - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - } - else if (handle->dataLength <= 16U) - { - data = base->FIFORD; - - if (handle->oneChannel) - { - *((volatile uint16_t *)dataAddr) = (uint16_t)(data & 0xFFFFU); - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - else - { - *((volatile uint32_t *)dataAddr) = data; - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - } - else if (handle->dataLength <= 24U) - { - if (handle->pack48) - { - if (handle->useFifo48H) - { - data = base->FIFORD48H; - handle->useFifo48H = false; - - *((volatile uint16_t *)dataAddr) = (uint16_t)data; - dataAddr += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - dataSize -= sizeof(uint16_t); - } - else - { - data = base->FIFORD; - handle->useFifo48H = true; - - *((volatile uint32_t *)dataAddr) = data; - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - } - else - { - if (handle->useFifo48H) - { - data = base->FIFORD48H; - handle->useFifo48H = false; - } - else - { - data = base->FIFORD; - handle->useFifo48H = true; - } - - *(uint8_t *)(dataAddr++) = (uint8_t)(data & 0xFFU); - *(uint8_t *)(dataAddr++) = (uint8_t)((data >> 8U) & 0xFFU); - *(uint8_t *)(dataAddr++) = (uint8_t)((data >> 16U) & 0xFFU); - handle->transferCount += 3U; - dataSize -= 3U; - } - } - else /* if (handle->dataLength <= 32U) */ - { - data = base->FIFORD; - *((volatile uint32_t *)dataAddr) = data; - dataAddr += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - dataSize -= sizeof(uint32_t); - } - - if (dataSize == 0U) - { - handle->i2sQueue[queueDriverIndex].dataSize = 0U; - /* Actual data buffer filled with input data, switch to a next one */ - handle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; - - /* Notify user */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); - } - - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* No other buffer prepared to receive data into */ - - /* Disable I2S operation and interrupts */ - I2S_Disable(base); - I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - - /* Reset state */ - handle->state = (uint32_t)kI2S_StateIdle; - - /* Notify user */ - if (handle->completionCallback != NULL) - { - handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); - } - - /* Clear RX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); - - return; - } - } - else - { - handle->i2sQueue[queueDriverIndex].dataSize = dataSize; - handle->i2sQueue[queueDriverIndex].data = (uint8_t *)dataAddr; - } - } - - /* Clear RX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s.h deleted file mode 100644 index e0787d6b145..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s.h +++ /dev/null @@ -1,513 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2S_H_ -#define _FSL_I2S_H_ - -#include "fsl_device_registers.h" -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup i2s_driver - * @{ - */ - -/*! @file */ - -/*! @name Driver version */ -/*@{*/ - -/*! @brief I2S driver version 2.3.1. */ -#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) -/*@}*/ - -#ifndef I2S_NUM_BUFFERS - -/*! @brief Number of buffers . */ -#define I2S_NUM_BUFFERS (4U) - -#endif - -/*! @brief _i2s_status I2S status codes. */ -enum -{ - kStatus_I2S_BufferComplete = - MAKE_STATUS(kStatusGroup_I2S, 0), /*!< Transfer from/into a single buffer has completed */ - kStatus_I2S_Done = MAKE_STATUS(kStatusGroup_I2S, 1), /*!< All buffers transfers have completed */ - kStatus_I2S_Busy = - MAKE_STATUS(kStatusGroup_I2S, 2), /*!< Already performing a transfer and cannot queue another buffer */ -}; - -/*! - * @brief I2S flags. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -typedef enum _i2s_flags -{ - kI2S_TxErrorFlag = I2S_FIFOINTENSET_TXERR_MASK, /*!< TX error interrupt */ - kI2S_TxLevelFlag = I2S_FIFOINTENSET_TXLVL_MASK, /*!< TX level interrupt */ - kI2S_RxErrorFlag = I2S_FIFOINTENSET_RXERR_MASK, /*!< RX error interrupt */ - kI2S_RxLevelFlag = I2S_FIFOINTENSET_RXLVL_MASK /*!< RX level interrupt */ -} i2s_flags_t; - -/*! @brief Master / slave mode. */ -typedef enum _i2s_master_slave -{ - kI2S_MasterSlaveNormalSlave = 0x0, /*!< Normal slave */ - kI2S_MasterSlaveWsSyncMaster = 0x1, /*!< WS synchronized master */ - kI2S_MasterSlaveExtSckMaster = 0x2, /*!< Master using existing SCK */ - kI2S_MasterSlaveNormalMaster = 0x3 /*!< Normal master */ -} i2s_master_slave_t; - -/*! @brief I2S mode. */ -typedef enum _i2s_mode -{ - kI2S_ModeI2sClassic = 0x0, /*!< I2S classic mode */ - kI2S_ModeDspWs50 = 0x1, /*!< DSP mode, WS having 50% duty cycle */ - kI2S_ModeDspWsShort = 0x2, /*!< DSP mode, WS having one clock long pulse */ - kI2S_ModeDspWsLong = 0x3 /*!< DSP mode, WS having one data slot long pulse */ -} i2s_mode_t; - -/*! @brief _i2s_secondary_channel I2S secondary channel. */ -enum -{ - kI2S_SecondaryChannel1 = 0U, /*!< secondary channel 1 */ - kI2S_SecondaryChannel2 = 1U, /*!< secondary channel 2 */ - kI2S_SecondaryChannel3 = 2U, /*!< secondary channel 3 */ -}; - -/*! @brief I2S configuration structure. */ -typedef struct _i2s_config -{ - i2s_master_slave_t masterSlave; /*!< Master / slave configuration */ - i2s_mode_t mode; /*!< I2S mode */ - bool rightLow; /*!< Right channel data in low portion of FIFO */ - bool leftJust; /*!< Left justify data in FIFO */ -#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) - bool pdmData; /*!< Data source is the D-Mic subsystem */ -#endif - bool sckPol; /*!< SCK polarity */ - bool wsPol; /*!< WS polarity */ - uint16_t divider; /*!< Flexcomm function clock divider (1 - 4096) */ - bool oneChannel; /*!< true mono, false stereo */ - uint8_t dataLength; /*!< Data length (4 - 32) */ - uint16_t frameLength; /*!< Frame width (4 - 512) */ - uint16_t position; /*!< Data position in the frame */ - uint8_t watermark; /*!< FIFO trigger level */ - bool txEmptyZero; /*!< Transmit zero when buffer becomes empty or last item */ - bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit - values) */ -} i2s_config_t; - -/*! @brief Buffer to transfer from or receive audio data into. */ -typedef struct _i2s_transfer -{ - uint8_t *data; /*!< Pointer to data buffer. */ - size_t dataSize; /*!< Buffer size in bytes. */ -} i2s_transfer_t; - -/*! @brief Transactional state of the intialized transfer or receive I2S operation. */ -typedef struct _i2s_handle i2s_handle_t; - -/*! - * @brief Callback function invoked from transactional API - * on completion of a single buffer transfer. - * - * @param base I2S base pointer. - * @param handle pointer to I2S transaction. - * @param completionStatus status of the transaction. - * @param userData optional pointer to user arguments data. - */ -typedef void (*i2s_transfer_callback_t)(I2S_Type *base, - i2s_handle_t *handle, - status_t completionStatus, - void *userData); - -/*! @brief Members not to be accessed / modified outside of the driver. */ -struct _i2s_handle -{ - volatile uint32_t state; /*!< State of transfer */ - i2s_transfer_callback_t completionCallback; /*!< Callback function pointer */ - void *userData; /*!< Application data passed to callback */ - bool oneChannel; /*!< true mono, false stereo */ - uint8_t dataLength; /*!< Data length (4 - 32) */ - bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit - values) */ - uint8_t watermark; /*!< FIFO trigger level */ - bool useFifo48H; /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */ - - volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ - volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ - volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ - volatile uint32_t errorCount; /*!< Number of buffer underruns/overruns */ - volatile uint32_t transferCount; /*!< Number of bytes transferred */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S transmission using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_TxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the I2S driver. - * - * @param base I2S base pointer. - * @param config pointer to I2S configuration structure. - */ -void I2S_TxInit(I2S_Type *base, const i2s_config_t *config); - -/*! - * @brief Initializes the FLEXCOMM peripheral for I2S receive functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S receive using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_RxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the I2S driver. - * - * @param base I2S base pointer. - * @param config pointer to I2S configuration structure. - */ -void I2S_RxInit(I2S_Type *base, const i2s_config_t *config); - -/*! - * @brief Sets the I2S Tx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_TxInit(). - * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified - * before calling I2S_TxInit(). - * Example: - @code - i2s_config_t config; - I2S_TxGetDefaultConfig(&config); - @endcode - * - * Default values: - * @code - * config->masterSlave = kI2S_MasterSlaveNormalMaster; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = true; - * config->pack48 = false; - * @endcode - * - * @param config pointer to I2S configuration structure. - */ -void I2S_TxGetDefaultConfig(i2s_config_t *config); - -/*! - * @brief Sets the I2S Rx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_RxInit(). - * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified - * before calling I2S_RxInit(). - * Example: - @code - i2s_config_t config; - I2S_RxGetDefaultConfig(&config); - @endcode - * - * Default values: - * @code - * config->masterSlave = kI2S_MasterSlaveNormalSlave; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = false; - * config->pack48 = false; - * @endcode - * - * @param config pointer to I2S configuration structure. - */ -void I2S_RxGetDefaultConfig(i2s_config_t *config); - -/*! - * @brief De-initializes the I2S peripheral. - * - * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit - * or I2S_RxInit is called to enable the clock. - * - * @param base I2S base pointer. - */ -void I2S_Deinit(I2S_Type *base); - -/*! - * @brief Transmitter/Receiver bit clock rate configurations. - * - * @param base SAI base pointer. - * @param sourceClockHz bit clock source frequency. - * @param sampleRate audio data sample rate. - * @param bitWidth audio data bitWidth. - * @param channelNumbers audio channel numbers. - */ -void I2S_SetBitClockRate( - I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers); - -/*! @} */ - -/*! - * @name Non-blocking API - * @{ - */ - -/*! - * @brief Initializes handle for transfer of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); - -/*! - * @brief Begins or queue sending of the given data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts sending of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Initializes handle for reception of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); - -/*! - * @brief Begins or queue reception of data into given buffer. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. - */ -status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts receiving of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Returns number of bytes transferred so far. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param[out] count number of bytes transferred so far by the non-blocking transaction. - * - * @retval kStatus_Success - * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); - -/*! - * @brief Returns number of buffer underruns or overruns. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param[out] count number of transmit errors encountered so far by the non-blocking transaction. - * - * @retval kStatus_Success - * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); - -/*! @} */ - -/*! - * @name Enable / disable - * @{ - */ - -/*! - * @brief Enables I2S operation. - * - * @param base I2S base pointer. - */ -static inline void I2S_Enable(I2S_Type *base) -{ - base->CFG1 |= I2S_CFG1_MAINENABLE(1U); -} - -#if (defined(FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) && FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) -/*! - * @brief Enables I2S secondary channel. - * - * @param base I2S base pointer. - * @param channel seondary channel channel number, reference _i2s_secondary_channel. - * @param oneChannel true is treated as single channel, functionality left channel for this pair. - * @param position define the location within the frame of the data, should not bigger than 0x1FFU. - */ -void I2S_EnableSecondaryChannel(I2S_Type *base, uint32_t channel, bool oneChannel, uint32_t position); - -/*! - * @brief Disables I2S secondary channel. - * - * @param base I2S base pointer. - * @param channel seondary channel channel number, reference _i2s_secondary_channel. - */ -static inline void I2S_DisableSecondaryChannel(I2S_Type *base, uint32_t channel) -{ -#if defined FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn - assert(FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn((FLEXCOMM_Type *)(uint32_t)base) == 1); -#endif - - base->SECCHANNEL[channel].PCFG1 &= ~I2S_CFG1_MAINENABLE_MASK; -} -#endif -/*! - * @brief Disables I2S operation. - * - * @param base I2S base pointer. - */ -static inline void I2S_Disable(I2S_Type *base) -{ - base->CFG1 &= (~I2S_CFG1_MAINENABLE(1U)); -} - -/*! @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables I2S FIFO interrupts. - * - * @param base I2S base pointer. - * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2S_EnableInterrupts(I2S_Type *base, uint32_t interruptMask) -{ - base->FIFOINTENSET = interruptMask; -} - -/*! - * @brief Disables I2S FIFO interrupts. - * - * @param base I2S base pointer. - * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2S_DisableInterrupts(I2S_Type *base, uint32_t interruptMask) -{ - base->FIFOINTENCLR = interruptMask; -} - -/*! - * @brief Returns the set of currently enabled I2S FIFO interrupts. - * - * @param base I2S base pointer. - * - * @return A bitmask composed of #i2s_flags_t enumerators OR'd together - * to indicate the set of enabled interrupts. - */ -static inline uint32_t I2S_GetEnabledInterrupts(I2S_Type *base) -{ - return base->FIFOINTENSET; -} - -/*! - * @brief Flush the valid data in TX fifo. - * - * @param base I2S base pointer. - * @return kStatus_Fail empty TX fifo failed, kStatus_Success empty tx fifo success. - */ -status_t I2S_EmptyTxFifo(I2S_Type *base); - -/*! - * @brief Invoked from interrupt handler when transmit FIFO level decreases. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Invoked from interrupt handler when receive FIFO level decreases. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); - -/*! @} */ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2S_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.c deleted file mode 100644 index 84f25b30e91..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.c +++ /dev/null @@ -1,848 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_dma.h" -#include "fsl_i2s_dma.h" -#include "fsl_flexcomm.h" -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s_dma" -#endif - -#define DMA_MAX_TRANSFER_BYTES (DMA_MAX_TRANSFER_COUNT * sizeof(uint32_t)) -#define DMA_DESCRIPTORS (2U) - -/*i2sQueue[handle->queueUser].dataSize != 0UL) - { - /* Previously prepared buffers not processed yet, reject request */ - return kStatus_I2S_Busy; - } - - /* Enqueue data */ - privateHandle->descriptorQueue[handle->queueUser].data = transfer.data; - privateHandle->descriptorQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - return kStatus_Success; -} - -static uint32_t I2S_GetInstance(I2S_Type *base) -{ - uint32_t i; - - for (i = 0U; i < ARRAY_SIZE(s_I2sBaseAddrs); i++) - { - if ((uint32_t)base == s_I2sBaseAddrs[i]) - { - return i; - } - } - - assert(false); - return 0U; -} - -static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle) -{ - DMA_DisableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); -} - -static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle) -{ - if (handle->state != (uint32_t)kI2S_DmaStateIdle) - { - DMA_EnableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); - } -} - -/*! - * brief Initializes handle for transfer of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param dmaHandle pointer to dma handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData) -{ - assert(handle != NULL); - assert(dmaHandle != NULL); - - uint32_t instance = I2S_GetInstance(base); - i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - - (void)memset(handle, 0, sizeof(*handle)); - handle->state = (uint32_t)kI2S_DmaStateIdle; - handle->dmaHandle = dmaHandle; - handle->completionCallback = callback; - handle->userData = userData; - - handle->bytesPerFrame = (uint8_t)((((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U) / 8U); - /* if one channel is disabled, bytesPerFrame should be 4U, user should pay attention that when data length is - * shorter than 16, the data format: left data put in 0-15 bit and right data should put in 16-31 - */ - if (((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) == 0U)) - { - handle->bytesPerFrame = 4U; - } - /* since DMA do not support 24bit transfer width, use 32bit instead */ - if (handle->bytesPerFrame == 3U) - { - handle->bytesPerFrame = 4U; - } - - (void)memset(privateHandle, 0, sizeof(*privateHandle)); - privateHandle->base = base; - privateHandle->handle = handle; - - DMA_SetCallback(dmaHandle, I2S_DMACallback, privateHandle); -} - -/*! - * brief Begins or queue sending of the given data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) -{ - status_t status; - - I2S_DisableDMAInterrupts(handle); - - /* Enqueue transfer buffer */ - status = I2S_EnqueueUserBuffer(base, handle, transfer); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - - /* Initialize DMA transfer */ - if (handle->state == (uint32_t)kI2S_DmaStateIdle) - { - handle->state = (uint32_t)kI2S_DmaStateTx; - status = I2S_StartTransferDMA(base, handle); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - } - - I2S_AddTransferDMA(base, handle); - I2S_EnableDMAInterrupts(handle); - - return kStatus_Success; -} - -/*! - * brief Aborts transfer of data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - assert(handle != NULL); - assert(handle->dmaHandle != NULL); - - uint32_t instance = I2S_GetInstance(base); - i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - - I2S_DisableDMAInterrupts(handle); - - /* Abort operation */ - DMA_AbortTransfer(handle->dmaHandle); - - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - /* Disable TX */ - I2S_TxEnableDMA(base, false); - } - else - { - /* Disable RX */ - I2S_RxEnableDMA(base, false); - } - - I2S_Disable(base); - - /* Reset state */ - handle->state = (uint32_t)kI2S_DmaStateIdle; - - /* Clear transfer queue */ - (void)memset((void *)&(handle->i2sQueue), 0, sizeof(handle->i2sQueue)); - handle->queueDriver = 0U; - handle->queueUser = 0U; - - /* Clear internal state */ - (void)memset((void *)&(privateHandle->descriptorQueue), 0, sizeof(privateHandle->descriptorQueue)); - (void)memset((void *)&(privateHandle->enqueuedBytes), 0, sizeof(privateHandle->enqueuedBytes)); - privateHandle->enqueuedBytesStart = 0U; - privateHandle->enqueuedBytesEnd = 0U; - privateHandle->dmaDescriptorsUsed = 0U; - privateHandle->descriptor = 0U; - privateHandle->queueDescriptor = 0U; - privateHandle->intA = false; -} - -/*! - * brief Initializes handle for reception of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param dmaHandle pointer to dma handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData) -{ - I2S_TxTransferCreateHandleDMA(base, handle, dmaHandle, callback, userData); -} - -/*! - * brief Begins or queue reception of data into given buffer. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with buffers - * which are not full. - */ -status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) -{ - status_t status; - - I2S_DisableDMAInterrupts(handle); - - /* Enqueue transfer buffer */ - status = I2S_EnqueueUserBuffer(base, handle, transfer); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - - /* Initialize DMA transfer */ - if (handle->state == (uint32_t)kI2S_DmaStateIdle) - { - handle->state = (uint32_t)kI2S_DmaStateRx; - status = I2S_StartTransferDMA(base, handle); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - } - - I2S_AddTransferDMA(base, handle); - I2S_EnableDMAInterrupts(handle); - - return kStatus_Success; -} - -static void I2S_TxEnableDMA(I2S_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= I2S_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= (~I2S_FIFOCFG_DMATX_MASK); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - } -} - -static void I2S_RxEnableDMA(I2S_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= I2S_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= (~I2S_FIFOCFG_DMARX_MASK); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - } -} - -static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer) -{ - assert(transfer != NULL); - - uint16_t transferBytes; - - if (transfer->dataSize >= (2UL * DMA_MAX_TRANSFER_BYTES)) - { - transferBytes = DMA_MAX_TRANSFER_BYTES; - } - else if (transfer->dataSize > DMA_MAX_TRANSFER_BYTES) - { - transferBytes = (uint16_t)(transfer->dataSize / 2U); - if ((transferBytes % 4U) != 0U) - { - transferBytes -= (transferBytes % 4U); - } - } - else - { - transferBytes = (uint16_t)transfer->dataSize; - } - - return transferBytes; -} - -/*! - * brief Install DMA descriptor memory for loop transfer only. - * - * This function used to register DMA descriptor memory for the i2s loop dma transfer. - * - * It must be callbed before I2S_TransferSendLoopDMA/I2S_TransferReceiveLoopDMA and after - * I2S_RxTransferCreateHandleDMA/I2S_TxTransferCreateHandleDMA. - * - * User should be take care about the address of DMA descriptor pool which required align with 16BYTE at least. - * - * param handle Pointer to i2s DMA transfer handle. - * param dmaDescriptorAddr DMA descriptor start address. - * param dmaDescriptorNum DMA descriptor number. - */ -void I2S_TransferInstallLoopDMADescriptorMemory(i2s_dma_handle_t *handle, - void *dmaDescriptorAddr, - size_t dmaDescriptorNum) -{ - assert(handle != NULL); - assert((((uint32_t)(uint32_t *)dmaDescriptorAddr) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == - 0UL); - - handle->i2sLoopDMADescriptor = (dma_descriptor_t *)dmaDescriptorAddr; - handle->i2sLoopDMADescriptorNum = dmaDescriptorNum; -} - -static status_t I2S_TransferLoopDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - i2s_transfer_t *xfer, - uint32_t loopTransferCount) -{ - assert(handle != NULL); - assert(handle->dmaHandle != NULL); - assert(xfer != NULL); - - uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; - i2s_transfer_t *currentTransfer = xfer; - bool intA = true; - - if (handle->i2sLoopDMADescriptor == NULL) - { - return kStatus_InvalidArgument; - } - - if (handle->state == (uint32_t)kI2S_DmaStateBusyLoopTransfer) - { - return kStatus_I2S_Busy; - } - - for (uint32_t i = 0U; i < loopTransferCount; i++) - { - currentTransfer = &xfer[i]; - - if ((currentTransfer->data == NULL) || (currentTransfer->dataSize == 0U) || - (i >= handle->i2sLoopDMADescriptorNum) || - (currentTransfer->dataSize / handle->bytesPerFrame > DMA_MAX_TRANSFER_COUNT)) - { - return kStatus_InvalidArgument; - } - - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - srcAddr = (uint32_t *)(uint32_t)currentTransfer->data; - destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); - srcInc = 1U; - destInc = 0UL; - } - else - { - srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); - destAddr = (uint32_t *)(uint32_t)currentTransfer->data; - srcInc = 0U; - destInc = 1UL; - } - - intA = intA == true ? false : true; - - if (i == (loopTransferCount - 1U)) - { - /* set up linked descriptor */ - DMA_SetupDescriptor(&handle->i2sLoopDMADescriptor[i], - DMA_CHANNEL_XFER(1UL, 0UL, intA, !intA, handle->bytesPerFrame, srcInc, destInc, - currentTransfer->dataSize), - srcAddr, destAddr, &handle->i2sLoopDMADescriptor[0U]); - } - else - { - /* set up linked descriptor */ - DMA_SetupDescriptor(&handle->i2sLoopDMADescriptor[i], - DMA_CHANNEL_XFER(1UL, 0UL, intA, !intA, handle->bytesPerFrame, srcInc, destInc, - currentTransfer->dataSize), - srcAddr, destAddr, &handle->i2sLoopDMADescriptor[i + 1U]); - } - } - - /* transferSize make sense to non link transfer only */ - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - srcAddr = (uint32_t *)(uint32_t)xfer->data; - destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); - srcInc = 1U; - destInc = 0UL; - } - else - { - srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); - destAddr = (uint32_t *)(uint32_t)xfer->data; - srcInc = 0U; - destInc = 1UL; - } - - DMA_SubmitChannelTransferParameter( - handle->dmaHandle, - DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 1UL, handle->bytesPerFrame, srcInc, destInc, (uint32_t)xfer->dataSize), srcAddr, - destAddr, (void *)&handle->i2sLoopDMADescriptor[1U]); - - /* Submit and start initial DMA transfer */ - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - I2S_TxEnableDMA(base, true); - } - else - { - I2S_RxEnableDMA(base, true); - } - DMA_EnableChannelPeriphRq(handle->dmaHandle->base, handle->dmaHandle->channel); - /* start transfer */ - DMA_StartTransfer(handle->dmaHandle); - I2S_Enable(base); - - handle->state = (uint32_t)kI2S_DmaStateBusyLoopTransfer; - - return kStatus_Success; -} - -/*! - * brief Send loop transfer data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * This function support loop transfer, such as A->B->...->A, the loop transfer chain - * will be converted into a chain of descriptor and submit to dma. - * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, - * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. - * - * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support - * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop - * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. - * - * param base I2S peripheral base address. - * param handle Pointer to usart_dma_handle_t structure. - * param xfer I2S DMA transfer structure. See #i2s_transfer_t. - * param i2s_channel I2S start channel number - * retval kStatus_Success - */ -status_t I2S_TransferSendLoopDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - i2s_transfer_t *xfer, - uint32_t loopTransferCount) -{ - assert(handle != NULL); - assert(handle->i2sLoopDMADescriptor != NULL); - - handle->state = (uint32_t)kI2S_DmaStateTx; - - return I2S_TransferLoopDMA(base, handle, xfer, loopTransferCount); -} - -/*! - * brief Receive loop transfer data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * This function support loop transfer, such as A->B->...->A, the loop transfer chain - * will be converted into a chain of descriptor and submit to dma. - * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, - * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. - * - * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support - * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop - * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. - * - * param base I2S peripheral base address. - * param handle Pointer to usart_dma_handle_t structure. - * param xfer I2S DMA transfer structure. See #i2s_transfer_t. - * param i2s_channel I2S start channel number - * retval kStatus_Success - */ -status_t I2S_TransferReceiveLoopDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - i2s_transfer_t *xfer, - uint32_t loopTransferCount) -{ - assert(handle != NULL); - assert(handle->i2sLoopDMADescriptor != NULL); - - handle->state = (uint32_t)kI2S_DmaStateRx; - - return I2S_TransferLoopDMA(base, handle, xfer, loopTransferCount); -} - -static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - uint32_t instance = I2S_GetInstance(base); - i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - volatile i2s_transfer_t *transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); - uint16_t transferBytes = I2S_GetTransferBytes(transfer); - uint32_t i = 0U; - uint32_t xferConfig = 0U; - uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; - - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - srcAddr = (uint32_t *)(uint32_t)transfer->data; - destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); - srcInc = 1U; - destInc = 0UL; - } - else - { - srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); - destAddr = (uint32_t *)(uint32_t)transfer->data; - srcInc = 0U; - destInc = 1UL; - } - /* Initial descriptor is stored in another place in memory, but treat it as another descriptor for simplicity */ - privateHandle->dmaDescriptorsUsed = 1U; - privateHandle->intA = false; - - /* submit transfer parameter directly */ - xferConfig = DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 1UL, handle->bytesPerFrame, srcInc, destInc, (uint32_t)transferBytes); - - DMA_SubmitChannelTransferParameter(handle->dmaHandle, xferConfig, srcAddr, destAddr, - (void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U])); - - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; - privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; - - transfer->dataSize -= transferBytes; - transfer->data = (uint8_t *)((uint32_t)transfer->data + transferBytes); - - if (transfer->dataSize == 0U) - { - transfer->data = NULL; - privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; - } - - /* Link the DMA descriptors for the case when no additional transfer is queued before the initial one finishes - * The configuration for the DMA dummy descriptor make no sense to tx or rx transfer, since it will be overwritten - * when another transfer request comes before the previous finished. - * To make sure the audio data transfer continuously, application must request another transfer by call - * I2S_RxTransferReceiveDMA or I2S_TxTransferSendDMA before previous transfer finished. - */ - for (i = 0; i < DMA_DESCRIPTORS; i++) - { - /* DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 0UL, sizeof(uint32_t), 0U, 0U, 8U) = 0x10203UL */ - DMA_SetupDescriptor( - &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + i]), 0x10203UL, - ((handle->state == (uint32_t)kI2S_DmaStateTx) ? &s_DummyBufferTx : (uint32_t *)(uint32_t)(&(base->FIFORD))), - ((handle->state == (uint32_t)kI2S_DmaStateTx) ? (uint32_t *)(uint32_t)(&(base->FIFOWR)) : &s_DummyBufferRx), - &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + ((i + 1U) % DMA_DESCRIPTORS)])); - } - - /* Submit and start initial DMA transfer */ - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - I2S_TxEnableDMA(base, true); - } - else - { - I2S_RxEnableDMA(base, true); - } - /* enable I2S peripheral request and put the channel into triggered status */ - DMA_EnableChannelPeriphRq(handle->dmaHandle->base, handle->dmaHandle->channel); - DMA_StartTransfer(handle->dmaHandle); - - I2S_Enable(base); - - return kStatus_Success; -} - -static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - volatile i2s_transfer_t *transfer; - uint16_t transferBytes; - uint32_t instance; - i2s_dma_private_handle_t *privateHandle; - dma_descriptor_t *descriptor; - dma_descriptor_t *nextDescriptor; - uint32_t xferConfig = 0U; - bool intA = false; - uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; - - instance = I2S_GetInstance(base); - privateHandle = &(s_DmaPrivateHandle[instance]); - - while (privateHandle->dmaDescriptorsUsed < DMA_DESCRIPTORS) - { - transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); - intA = privateHandle->intA; - if (transfer->dataSize == 0U) - { - /* Nothing to be added */ - return; - } - - if (handle->state == (uint32_t)kI2S_DmaStateTx) - { - srcAddr = (uint32_t *)(uint32_t)transfer->data; - destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); - srcInc = 1U; - destInc = 0UL; - } - else - { - srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); - destAddr = (uint32_t *)(uint32_t)transfer->data; - srcInc = 0U; - destInc = 1UL; - } - - /* Determine currently configured descriptor and the other which it will link to */ - descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); - privateHandle->descriptor = (privateHandle->descriptor + 1U) % DMA_DESCRIPTORS; - nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); - - transferBytes = I2S_GetTransferBytes(transfer); - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; - privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; - - xferConfig = - DMA_CHANNEL_XFER(1UL, 0UL, !intA, intA, handle->bytesPerFrame, srcInc, destInc, (uint32_t)transferBytes); - - DMA_SetupDescriptor(descriptor, xferConfig, srcAddr, destAddr, nextDescriptor); - - /* Advance internal state */ - privateHandle->dmaDescriptorsUsed++; - privateHandle->intA = !privateHandle->intA; - - transfer->dataSize -= transferBytes; - transfer->data += transferBytes; - if (transfer->dataSize == 0U) - { - transfer->data = NULL; - privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; - } - } -} - -/*! - * brief Invoked from DMA interrupt handler. - * - * param handle pointer to DMA handle structure. - * param userData argument for user callback. - * param transferDone if transfer was done. - * param tcds - */ -void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds) -{ - i2s_dma_private_handle_t *privateHandle = (i2s_dma_private_handle_t *)userData; - i2s_dma_handle_t *i2sHandle = privateHandle->handle; - I2S_Type *base = privateHandle->base; - uint8_t queueDriverIndex = i2sHandle->queueDriver; - uint32_t enqueueBytes = privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart]; - uint32_t queueDataAddr = (uint32_t)i2sHandle->i2sQueue[queueDriverIndex].data; - - if ((!transferDone) || (i2sHandle->state == (uint32_t)kI2S_DmaStateIdle)) - { - return; - } - - if (privateHandle->dmaDescriptorsUsed > 0U) - { - /* Finished descriptor, decrease amount of data to be processed */ - - i2sHandle->i2sQueue[queueDriverIndex].dataSize -= enqueueBytes; - i2sHandle->i2sQueue[queueDriverIndex].data = (uint8_t *)(queueDataAddr + enqueueBytes); - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] = 0U; - privateHandle->enqueuedBytesStart = (privateHandle->enqueuedBytesStart + 1U) % DMA_DESCRIPTORS; - privateHandle->dmaDescriptorsUsed--; - } - - if (i2sHandle->i2sQueue[queueDriverIndex].dataSize == 0U) - { - /* Entire user buffer sent or received - advance to next one */ - i2sHandle->i2sQueue[queueDriverIndex].data = NULL; - i2sHandle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; - /* Notify user about buffer completion */ - if (i2sHandle->completionCallback != NULL) - { - (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_BufferComplete, i2sHandle->userData); - } - } - - if (i2sHandle->state != (uint32_t)kI2S_DmaStateBusyLoopTransfer) - { - /* check next buffer queue is avaliable or not */ - if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U) - { - if (i2sHandle->state == (uint32_t)kI2S_DmaStateTx) - { - (void)I2S_EmptyTxFifo(base); - } - /* All user buffers processed */ - I2S_TransferAbortDMA(base, i2sHandle); - } - else - { - /* Enqueue another user buffer to DMA if it could not be done when in I2S_Rx/TxTransferSendDMA */ - I2S_AddTransferDMA(base, i2sHandle); - } - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.h deleted file mode 100644 index ec63472653a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.h +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2S_DMA_H_ -#define _FSL_I2S_DMA_H_ - -#include "fsl_device_registers.h" -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -#include "fsl_dma.h" -#include "fsl_i2s.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup i2s_dma_driver - * @{ - */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2S DMA driver version 2.3.1. */ -#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) -/*@}*/ - -/*! @brief Members not to be accessed / modified outside of the driver. */ -typedef struct _i2s_dma_handle i2s_dma_handle_t; - -/*! - * @brief Callback function invoked from DMA API on completion. - * - * @param base I2S base pointer. - * @param handle pointer to I2S transaction. - * @param completionStatus status of the transaction. - * @param userData optional pointer to user arguments data. - */ -typedef void (*i2s_dma_transfer_callback_t)(I2S_Type *base, - i2s_dma_handle_t *handle, - status_t completionStatus, - void *userData); -/*! @brief i2s dma handle */ -struct _i2s_dma_handle -{ - uint32_t state; /*!< Internal state of I2S DMA transfer */ - uint8_t bytesPerFrame; /*!< bytes per frame */ - i2s_dma_transfer_callback_t completionCallback; /*!< Callback function pointer */ - void *userData; /*!< Application data passed to callback */ - dma_handle_t *dmaHandle; /*!< DMA handle */ - volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ - volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ - volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ - - dma_descriptor_t *i2sLoopDMADescriptor; /*!< descriptor pool pointer */ - size_t i2sLoopDMADescriptorNum; /*!< number of descriptor in descriptors pool */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! @} */ - -/*! - * @name DMA API - * @{ - */ - -/*! - * @brief Initializes handle for transfer of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param dmaHandle pointer to dma handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData); - -/*! - * @brief Begins or queue sending of the given data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts transfer of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle); - -/*! - * @brief Initializes handle for reception of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param dmaHandle pointer to dma handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData); - -/*! - * @brief Begins or queue reception of data into given buffer. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers - * which are not full. - */ -status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Invoked from DMA interrupt handler. - * - * @param handle pointer to DMA handle structure. - * @param userData argument for user callback. - * @param transferDone if transfer was done. - * @param tcds - */ -void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds); - -/*! - * @brief Install DMA descriptor memory for loop transfer only. - * - * This function used to register DMA descriptor memory for the i2s loop dma transfer. - * - * It must be callbed before I2S_TransferSendLoopDMA/I2S_TransferReceiveLoopDMA and after - * I2S_RxTransferCreateHandleDMA/I2S_TxTransferCreateHandleDMA. - * - * User should be take care about the address of DMA descriptor pool which required align with 16BYTE at least. - * - * @param handle Pointer to i2s DMA transfer handle. - * @param dmaDescriptorAddr DMA descriptor start address. - * @param dmaDescriptorNum DMA descriptor number. - */ -void I2S_TransferInstallLoopDMADescriptorMemory(i2s_dma_handle_t *handle, - void *dmaDescriptorAddr, - size_t dmaDescriptorNum); - -/*! - * @brief Send link transfer data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * This function support loop transfer, such as A->B->...->A, the loop transfer chain - * will be converted into a chain of descriptor and submit to dma. - * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, - * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. - * - * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support - * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop - * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. - * - * @param base I2S peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param xfer I2S DMA transfer structure. See #i2s_transfer_t. - * @param loopTransferCount loop count - * @retval kStatus_Success - */ -status_t I2S_TransferSendLoopDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - i2s_transfer_t *xfer, - uint32_t loopTransferCount); - -/*! - * @brief Receive link transfer data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * This function support loop transfer, such as A->B->...->A, the loop transfer chain - * will be converted into a chain of descriptor and submit to dma. - * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, - * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. - * - * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support - * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop - * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. - * - * @param base I2S peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param xfer I2S DMA transfer structure. See #i2s_transfer_t. - * @param loopTransferCount loop count - * @retval kStatus_Success - */ -status_t I2S_TransferReceiveLoopDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - i2s_transfer_t *xfer, - uint32_t loopTransferCount); - -/*! @} */ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2S_DMA_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.c deleted file mode 100644 index 712b0faef71..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.c +++ /dev/null @@ -1,666 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "fsl_iap.h" -#include "fsl_iap_ffr.h" -#include "fsl_iap_kbp.h" -#include "fsl_iap_skboot_authenticate.h" -#include "fsl_device_registers.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.iap1" -#endif - -#if (defined(LPC5512_SERIES) || defined(LPC5514_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ - defined(LPC55S16_SERIES) || defined(LPC5524_SERIES) || defined(LPC5502_SERIES) || defined(LPC5504_SERIES) || \ - defined(LPC5506_SERIES) || defined(LPC55S04_SERIES) || defined(LPC55S06_SERIES)) - -#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1301fe00U) - -#elif (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || defined(LPC5526_SERIES) || \ - defined(LPC55S26_SERIES) || defined(LPC5528_SERIES) || defined(LPC55S28_SERIES) || \ - defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES)) - -#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x130010f0U) - -#else -#error "No valid CPU defined!" - -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -static status_t get_cfpa_higher_version(flash_config_t *config); - -/*! - * @name flash and ffr Structure - * @{ - */ - -typedef union functionCommandOption -{ - uint32_t commandAddr; - status_t (*eraseCommand)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - status_t (*programCommand)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); - status_t (*verifyProgramCommand)(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - status_t (*flashReadCommand)(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); -} function_command_option_t; - -/* - *!@brief Structure of version property. - * - *!@ingroup bl_core - */ -typedef union StandardVersion -{ - struct - { - uint32_t bugfix : 8; /*!< bugfix version [7:0] */ - uint32_t minor : 8; /*!< minor version [15:8] */ - uint32_t major : 8; /*!< major version [23:16] */ - uint32_t name : 8; /*!< name [31:24] */ - }; - uint32_t version; /*!< combined version numbers. */ -#if defined(__cplusplus) - StandardVersion() : version(0) - { - } - StandardVersion(uint32_t version) : version(version) - { - } -#endif -} standard_version_t; - -/*! @brief Interface for the flash driver.*/ -typedef struct version1FlashDriverInterface -{ - standard_version_t version; /*!< flash driver API version number.*/ - - /*!< Flash driver.*/ - status_t (*flash_init)(flash_config_t *config); - status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); - status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); - status_t (*flash_verify_program)(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); - uint32_t reserved[3]; /*! Reserved for future use */ - /*!< Flash FFR driver*/ - status_t (*ffr_init)(flash_config_t *config); - status_t (*ffr_lock_all)(flash_config_t *config); - status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); - status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); - status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); - status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode); - status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); - status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); - status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); -} version1_flash_driver_interface_t; - -/*! @brief Interface for the flash driver.*/ -typedef struct version0FlashDriverInterface -{ - standard_version_t version; /*!< flash driver API version number.*/ - - /*!< Flash driver.*/ - status_t (*flash_init)(flash_config_t *config); - status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); - status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); - status_t (*flash_verify_program)(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); - - /*!< Flash FFR driver*/ - status_t (*ffr_init)(flash_config_t *config); - status_t (*ffr_lock_all)(flash_config_t *config); - status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); - status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); - status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); - status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode); - status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); - status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); - status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); -} version0_flash_driver_interface_t; - -typedef union flashDriverInterface -{ - const version1_flash_driver_interface_t *version1FlashDriver; - const version0_flash_driver_interface_t *version0FlashDriver; -} flash_driver_interface_t; - -/*! @}*/ - -/*! - * @name Bootloader API and image authentication Structure - * @{ - */ - -/*! @brief Interface for Bootloader API functions. */ -typedef struct _kb_interface -{ - /*!< Initialize the API. */ - status_t (*kb_init_function)(kb_session_ref_t **session, const kb_options_t *options); - status_t (*kb_deinit_function)(kb_session_ref_t *session); - status_t (*kb_execute_function)(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength); -} kb_interface_t; - -//! @brief Interface for image authentication API -typedef struct _skboot_authenticate_interface -{ - skboot_status_t (*skboot_authenticate_function)(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified); - void (*skboot_hashcrypt_irq_handler)(void); -} skboot_authenticate_interface_t; -/*! @}*/ - -/*! - * @brief Root of the bootloader API tree. - * - * An instance of this struct resides in read-only memory in the bootloader. It - * provides a user application access to APIs exported by the bootloader. - * - * @note The order of existing fields must not be changed. - */ -typedef struct BootloaderTree -{ - void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing. */ - standard_version_t bootloader_version; /*!< Bootloader version number. */ - const char *copyright; /*!< Copyright string. */ - const uint32_t reserved0; /*!< Do NOT use. */ - flash_driver_interface_t flashDriver; - const kb_interface_t *kbApi; /*!< Bootloader API. */ - const uint32_t reserved1[4]; /*!< Do NOT use. */ - const skboot_authenticate_interface_t *skbootAuthenticate; /*!< Image authentication API. */ -} bootloader_tree_t; - -/******************************************************************************* - * Prototype - ******************************************************************************/ -static uint32_t get_rom_api_version(void); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! Get pointer to flash driver API table in ROM. */ -#define VERSION1_FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver.version1FlashDriver -#define VERSION0_FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver.version0FlashDriver -#define LPC55S69_REV0_FLASH_READ_ADDR (0x130043a3U) -#define LPC55S69_REV1_FLASH_READ_ADDR (0x13007539U) -#define LPC55S16_REV0_FLASH_READ_ADDR (0x1300ade5U) - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t get_rom_api_version(void) -{ - if (BOOTLOADER_API_TREE_POINTER->bootloader_version.major == 3u) - { - return 1u; - } - else - { - return 0u; - } -} - -/*! - * @brief Initializes the global flash properties structure members. - * - * This function checks and initializes the Flash module for the other Flash APIs. - */ -status_t FLASH_Init(flash_config_t *config) -{ - status_t status; - /* Initialize the clock to 96MHz */ - config->modeConfig.sysFreqInMHz = (uint32_t)kSysToFlashFreq_defaultInMHz; - if (get_rom_api_version() == 1u) - { - status = VERSION1_FLASH_API_TREE->flash_init(config); - } - else - { - status = VERSION0_FLASH_API_TREE->flash_init(config); - } - - if (config->PFlashTotalSize == 0xA0000U) - { - config->PFlashTotalSize -= 17U * config->PFlashPageSize; - } - - return status; -} - -/*! - * @brief Erases the flash sectors encompassed by parameters passed into function. - * - * This function erases the appropriate number of flash sectors based on the - * desired start address and length. - */ -status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) -{ - if (get_rom_api_version() == 0u) - { - function_command_option_t runCmdFuncOption; - runCmdFuncOption.commandAddr = 0x1300413bU; /*!< get the flash erase api location adress in rom */ - return runCmdFuncOption.eraseCommand(config, start, lengthInBytes, key); - } - else - { - return VERSION1_FLASH_API_TREE->flash_erase(config, start, lengthInBytes, key); - } -} - -/*! See fsl_iap.h for documentation of this function. */ -status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) -{ - if (get_rom_api_version() == 0u) - { - function_command_option_t runCmdFuncOption; - runCmdFuncOption.commandAddr = 0x1300419dU; /*!< get the flash program api location adress in rom*/ - return runCmdFuncOption.programCommand(config, start, src, lengthInBytes); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->flash_program(config, start, src, lengthInBytes); - } -} - -/*! See fsl_iap.h for documentation of this function. */ -status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes) -{ - if (get_rom_api_version() == 0u) - { - /*!< get the flash read api location adress in rom*/ - function_command_option_t runCmdFuncOption; - runCmdFuncOption.commandAddr = LPC55S69_REV0_FLASH_READ_ADDR; - return runCmdFuncOption.flashReadCommand(config, start, dest, lengthInBytes); - } - else - { - /*!< get the flash read api location adress in rom*/ - function_command_option_t runCmdFuncOption; - if ((SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK) != 0u) - { - runCmdFuncOption.commandAddr = LPC55S69_REV1_FLASH_READ_ADDR; - } - else - { - runCmdFuncOption.commandAddr = LPC55S16_REV0_FLASH_READ_ADDR; - } - return runCmdFuncOption.flashReadCommand(config, start, dest, lengthInBytes); - } -} - -/*! See fsl_iap.h for documentation of this function. */ -status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) -{ - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->flash_verify_erase(config, start, lengthInBytes); -} - -/*! - * @brief Verifies programming of the desired flash area at a specified margin level. - * - * This function verifies the data programed in the flash memory using the - * Flash Program Check Command and compares it to the expected data for a given - * flash area as determined by the start address and length. - */ -status_t FLASH_VerifyProgram(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData) -{ - if (get_rom_api_version() == 0u) - { - function_command_option_t runCmdFuncOption; - runCmdFuncOption.commandAddr = 0x1300427dU; /*!< get the flash verify program api location adress in rom*/ - return runCmdFuncOption.verifyProgramCommand(config, start, lengthInBytes, expectedData, failedAddress, - failedData); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->flash_verify_program(config, start, lengthInBytes, expectedData, failedAddress, - failedData); - } -} - -/*! - * @brief Returns the desired flash property. - */ -status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) -{ - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->flash_get_property(config, whichProperty, value); -} -/******************************************************************************** - * fsl iap ffr CODE - *******************************************************************************/ - -static status_t get_cfpa_higher_version(flash_config_t *config) -{ - uint32_t pageData[FLASH_FFR_MAX_PAGE_SIZE / sizeof(uint32_t)]; - uint32_t versionPing = 0U; - uint32_t versionPong = 0U; - - /* Get the CFPA ping page data and the corresponding version */ - config->ffrConfig.cfpaPageOffset = 1U; - status_t status = FFR_GetCustomerInfieldData(config, (uint8_t *)pageData, 0U, FLASH_FFR_MAX_PAGE_SIZE); - if (status != (int32_t)kStatus_FLASH_Success) - { - return status; - } - versionPing = pageData[1]; - - /* Get the CFPA pong page data and the corresponding version */ - config->ffrConfig.cfpaPageOffset = 2U; - status = FFR_GetCustomerInfieldData(config, (uint8_t *)pageData, 0U, FLASH_FFR_MAX_PAGE_SIZE); - if (status != (int32_t)kStatus_FLASH_Success) - { - return status; - } - versionPong = pageData[1]; - - /* Compare the CFPA ping version and pong version and set it correctly in flash_config structure */ - if (versionPing > versionPong) - { - config->ffrConfig.cfpaPageVersion = versionPing; - config->ffrConfig.cfpaPageOffset = 1U; - } - else - { - config->ffrConfig.cfpaPageVersion = versionPong; - config->ffrConfig.cfpaPageOffset = 2U; - } - return (int32_t)kStatus_FLASH_Success; -} - -/*! - * Initializes the global FFR properties structure members. - */ -status_t FFR_Init(flash_config_t *config) -{ - status_t status; - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - status = VERSION0_FLASH_API_TREE->ffr_init(config); - if (status != (status_t)kStatus_FLASH_Success) - { - return status; - } - return get_cfpa_higher_version(config); - } - else - { - assert(VERSION1_FLASH_API_TREE); - status = VERSION1_FLASH_API_TREE->ffr_init(config); - if (status != (status_t)kStatus_FLASH_Success) - { - return status; - } - return get_cfpa_higher_version(config); - } -} - -/*! - * Enable firewall for all flash banks. - */ -status_t FFR_Lock_All(flash_config_t *config) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_lock_all(config); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_lock_all(config); - } -} - -/*! - * APIs to access CMPA pages; - * This routine will erase "customer factory page" and program the page with passed data. - */ -status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part); - } -} - -/*! - * See fsl_iap_ffr.h for documentation of this function. - */ -status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_get_uuid(config, uuid); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_get_uuid(config, uuid); - } -} - -/*! - * APIs to access CMPA pages - * Read data stored in 'Customer Factory CFG Page'. - */ -status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len); - } -} - -/*! - * This routine writes the 3 pages allocated for Key store data, - * Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state. - */ -status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_keystore_write(config, pKeyStore); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_keystore_write(config, pKeyStore); - } -} - -/*! See fsl_iap_ffr.h for documentation of this function. */ -status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode); - } -} - -/*! See fsl_iap_ffr.h for documentation of this function. */ -status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex); - } -} - -/*! - * APIs to access CFPA pages - * This routine will erase CFPA and program the CFPA page with passed data. - */ -status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len); - } -} - -/*! - * APIs to access CFPA pages - * Generic read function, used by customer to read data stored in 'Customer In-field Page'. - */ -status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) -{ - if (get_rom_api_version() == 0u) - { - assert(VERSION0_FLASH_API_TREE); - return VERSION0_FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len); - } - else - { - assert(VERSION1_FLASH_API_TREE); - return VERSION1_FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len); - } -} - -/******************************************************************************** - * Bootloader API - *******************************************************************************/ -/*! - * @brief Initialize ROM API for a given operation. - * - * Inits the ROM API based on the options provided by the application in the second - * argument. Every call to rom_init() should be paired with a call to rom_deinit(). - */ -status_t kb_init(kb_session_ref_t **session, const kb_options_t *options) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->kbApi->kb_init_function(session, options); -} - -/*! - * @brief Cleans up the ROM API context. - * - * After this call, the @a context parameter can be reused for another operation - * by calling rom_init() again. - */ -status_t kb_deinit(kb_session_ref_t *session) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->kbApi->kb_deinit_function(session); -} - -/*! - * Perform the operation configured during init. - * - * This application must call this API repeatedly, passing in sequential chunks of - * data from the boot image (SB file) that is to be processed. The ROM will perform - * the selected operation on this data and return. The application may call this - * function with as much or as little data as it wishes, which can be used to select - * the granularity of time given to the application in between executing the operation. - * - * @param context Current ROM context pointer. - * @param data Buffer of boot image data provided to the ROM by the application. - * @param dataLength Length in bytes of the data in the buffer provided to the ROM. - * - * @retval #kStatus_Success The operation has completed successfully. - * @retval #kStatus_Fail An error occurred while executing the operation. - * @retval #kStatus_RomApiNeedMoreData No error occurred, but the ROM needs more data to - * continue processing the boot image. - */ -status_t kb_execute(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->kbApi->kb_execute_function(session, data, dataLength); -} - -/******************************************************************************** - * Image authentication API - *******************************************************************************/ - -/*! - * @brief Authenticate entry function with ARENA allocator init - * - * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface - */ -skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified) -{ - assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->skbootAuthenticate->skboot_authenticate_function(imageStartAddr, - isSignVerified); -} - -/*! - * @brief Interface for image authentication API - */ -void HASH_IRQHandler(void) -{ - assert(BOOTLOADER_API_TREE_POINTER); - BOOTLOADER_API_TREE_POINTER->skbootAuthenticate->skboot_hashcrypt_irq_handler(); -} -/******************************************************************************** - * EOF - *******************************************************************************/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.h deleted file mode 100644 index f7b318b66bd..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.h +++ /dev/null @@ -1,528 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __FSL_IAP_H_ -#define __FSL_IAP_H_ - -#include "fsl_common.h" -/*! - * @addtogroup flash_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! - * @name Flash version - * @{ - */ -/*! @brief Constructs the version number for drivers. */ -#if !defined(MAKE_VERSION) -#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) -#endif - -/*! @brief Flash driver version for SDK*/ -#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4. */ - -/*! @brief Flash driver version for ROM*/ -enum _flash_driver_version_constants -{ - kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ - kFLASH_DriverVersionMajor = 2, /*!< Major flash driver version.*/ - kFLASH_DriverVersionMinor = 1, /*!< Minor flash driver version.*/ - kFLASH_DriverVersionBugfix = 3 /*!< Bugfix for flash driver version.*/ -}; - -/*@}*/ - -/*! - * @name Flash configuration - * @{ - */ -/*! @brief Flash IP Type. */ -#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC) -#define FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC (1) -#endif -#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_FC) -#define FSL_FEATURE_FLASH_IP_IS_C040HD_FC (0) -#endif - -/*! - * @name Flash status - * @{ - */ -/*! @brief Flash driver status group. */ -#if defined(kStatusGroup_FlashDriver) -#define kStatusGroupGeneric kStatusGroup_Generic -#define kStatusGroupFlashDriver kStatusGroup_FlashDriver -#elif defined(kStatusGroup_FLASHIAP) -#define kStatusGroupGeneric kStatusGroup_Generic -#define kStatusGroupFlashDriver kStatusGroup_FLASH -#else -#define kStatusGroupGeneric 0 -#define kStatusGroupFlashDriver 1 -#endif - -/*! @brief Constructs a status code value from a group and a code number. */ -#if !defined(MAKE_STATUS) -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) -#endif - -/*! - * @brief Flash driver status codes. - */ -enum _flash_status -{ - kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ - kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ - kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ - kStatus_FLASH_AlignmentError = - MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ - kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ - kStatus_FLASH_AccessError = - MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ - kStatus_FLASH_ProtectionViolation = MAKE_STATUS( - kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ - kStatus_FLASH_CommandFailure = - MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ - kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ - kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/ - kStatus_FLASH_RegionExecuteOnly = - MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/ - kStatus_FLASH_ExecuteInRamFunctionNotReady = - MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/ - - kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Flash API is not supported.*/ - kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< The flash property is read-only.*/ - kStatus_FLASH_InvalidPropertyValue = - MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< The flash property value is out of range.*/ - kStatus_FLASH_InvalidSpeculationOption = - MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< The option of flash prefetch speculation is invalid.*/ - kStatus_FLASH_EccError = MAKE_STATUS(kStatusGroupFlashDriver, - 0x10), /*!< A correctable or uncorrectable error during command execution. */ - kStatus_FLASH_CompareError = - MAKE_STATUS(kStatusGroupFlashDriver, 0x11), /*!< Destination and source memory contents do not match. */ - kStatus_FLASH_RegulationLoss = MAKE_STATUS(kStatusGroupFlashDriver, 0x12), /*!< A loss of regulation during read. */ - kStatus_FLASH_InvalidWaitStateCycles = - MAKE_STATUS(kStatusGroupFlashDriver, 0x13), /*!< The wait state cycle set to r/w mode is invalid. */ - - kStatus_FLASH_OutOfDateCfpaPage = - MAKE_STATUS(kStatusGroupFlashDriver, 0x20), /*!< CFPA page version is out of date. */ - kStatus_FLASH_BlankIfrPageData = MAKE_STATUS(kStatusGroupFlashDriver, 0x21), /*!< Blank page cannnot be read. */ - kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce = - MAKE_STATUS(kStatusGroupFlashDriver, 0x22), /*!< Encrypted flash subregions are not erased at once. */ - kStatus_FLASH_ProgramVerificationNotAllowed = MAKE_STATUS( - kStatusGroupFlashDriver, 0x23), /*!< Program verification is not allowed when the encryption is enabled. */ - kStatus_FLASH_HashCheckError = - MAKE_STATUS(kStatusGroupFlashDriver, 0x24), /*!< Hash check of page data is failed. */ - kStatus_FLASH_SealedFfrRegion = MAKE_STATUS(kStatusGroupFlashDriver, 0x25), /*!< The FFR region is sealed. */ - kStatus_FLASH_FfrRegionWriteBroken = MAKE_STATUS( - kStatusGroupFlashDriver, 0x26), /*!< The FFR Spec region is not allowed to be written discontinuously. */ - kStatus_FLASH_NmpaAccessNotAllowed = - MAKE_STATUS(kStatusGroupFlashDriver, 0x27), /*!< The NMPA region is not allowed to be read/written/erased. */ - kStatus_FLASH_CmpaCfgDirectEraseNotAllowed = - MAKE_STATUS(kStatusGroupFlashDriver, 0x28), /*!< The CMPA Cfg region is not allowed to be erased directly. */ - kStatus_FLASH_FfrBankIsLocked = MAKE_STATUS(kStatusGroupFlashDriver, 0x29), /*!< The FFR bank region is locked. */ -}; -/*@}*/ - -/*! - * @name Flash API key - * @{ - */ -/*! @brief Constructs the four character code for the Flash driver API key. */ -#if !defined(FOUR_CHAR_CODE) -#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) -#endif - -/*! - * @brief Enumeration for Flash driver API keys. - * - * @note The resulting value is built with a byte order such that the string - * being readable in expected order when viewed in a hex editor, if the value - * is treated as a 32-bit little endian value. - */ -enum _flash_driver_api_keys -{ - kFLASH_ApiEraseKey = FOUR_CHAR_CODE('l', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ -}; -/*@}*/ - -/*! - * @brief Enumeration for various flash properties. - */ -typedef enum _flash_property_tag -{ - kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ - kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ - kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ - kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ - kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ - - kFLASH_PropertyPflashPageSize = 0x30U, /*!< Pflash page size property.*/ - kFLASH_PropertyPflashSystemFreq = 0x31U, /*!< System Frequency System Frequency.*/ - - kFLASH_PropertyFfrSectorSize = 0x40U, /*!< FFR sector size property.*/ - kFLASH_PropertyFfrTotalSize = 0x41U, /*!< FFR total size property.*/ - kFLASH_PropertyFfrBlockBaseAddr = 0x42U, /*!< FFR block base address property.*/ - kFLASH_PropertyFfrPageSize = 0x43U, /*!< FFR page size property.*/ -} flash_property_tag_t; - -/*! - * @brief Enumeration for flash max pages to erase. - */ -enum _flash_max_erase_page_value -{ - kFLASH_MaxPagesToErase = 100U /*!< The max value in pages to erase. */ -}; - -/*! - * @brief Enumeration for flash alignment property. - */ -enum _flash_alignment_property -{ - kFLASH_AlignementUnitVerifyErase = 4, /*!< The alignment unit in bytes used for verify erase operation.*/ - kFLASH_AlignementUnitProgram = 512, /*!< The alignment unit in bytes used for program operation.*/ - /*kFLASH_AlignementUnitVerifyProgram = 4,*/ /*!< The alignment unit in bytes used for verify program operation.*/ - kFLASH_AlignementUnitSingleWordRead = 16 /*!< The alignment unit in bytes used for SingleWordRead command.*/ -}; - -/*! - * @brief Enumeration for flash read ecc option - */ -enum _flash_read_ecc_option -{ - kFLASH_ReadWithEccOn = 0, /*! ECC is on */ - kFLASH_ReadWithEccOff = 1, /*! ECC is off */ -}; - -/* set flash Controller timing before flash init */ -enum _flash_freq_tag -{ - kSysToFlashFreq_lowInMHz = 12u, - kSysToFlashFreq_defaultInMHz = 96u, -}; - -/*! - * @brief Enumeration for flash read margin option - */ -enum _flash_read_margin_option -{ - kFLASH_ReadMarginNormal = 0, /*!< Normal read */ - kFLASH_ReadMarginVsProgram = 1, /*!< Margin vs. program */ - kFLASH_ReadMarginVsErase = 2, /*!< Margin vs. erase */ - kFLASH_ReadMarginIllegalBitCombination = 3 /*!< Illegal bit combination */ -}; - -/*! - * @brief Enumeration for flash read dmacc option - */ -enum _flash_read_dmacc_option -{ - kFLASH_ReadDmaccDisabled = 0, /*!< Memory word */ - kFLASH_ReadDmaccEnabled = 1, /*!< DMACC word */ -}; - -/*! - * @brief Enumeration for flash ramp control option - */ -enum _flash_ramp_control_option -{ - kFLASH_RampControlDivisionFactorReserved = 0, /*!< Reserved */ - kFLASH_RampControlDivisionFactor256 = 1, /*!< clk48mhz / 256 = 187.5KHz */ - kFLASH_RampControlDivisionFactor128 = 2, /*!< clk48mhz / 128 = 375KHz */ - kFLASH_RampControlDivisionFactor64 = 3 /*!< clk48mhz / 64 = 750KHz */ -}; - -/*! @brief Flash ECC log info. */ -typedef struct _flash_ecc_log -{ - uint32_t firstEccEventAddress; - uint32_t eccErrorCount; - uint32_t eccCorrectionCount; - uint32_t reserved; -} flash_ecc_log_t; - -/*! @brief Flash controller paramter config. */ -typedef struct _flash_mode_config -{ - uint32_t sysFreqInMHz; - /* ReadSingleWord parameter. */ - struct - { - uint8_t readWithEccOff : 1; - uint8_t readMarginLevel : 2; - uint8_t readDmaccWord : 1; - uint8_t reserved0 : 4; - uint8_t reserved1[3]; - } readSingleWord; - /* SetWriteMode parameter. */ - struct - { - uint8_t programRampControl; - uint8_t eraseRampControl; - uint8_t reserved[2]; - } setWriteMode; - /* SetReadMode parameter. */ - struct - { - uint16_t readInterfaceTimingTrim; - uint16_t readControllerTimingTrim; - uint8_t readWaitStates; - uint8_t reserved[3]; - } setReadMode; -} flash_mode_config_t; - -/*! @brief Flash controller paramter config. */ -typedef struct _flash_ffr_config -{ - uint32_t ffrBlockBase; - uint32_t ffrTotalSize; - uint32_t ffrPageSize; - uint32_t cfpaPageVersion; - uint32_t cfpaPageOffset; -} flash_ffr_config_t; - -/*! @brief Flash driver state information. - * - * An instance of this structure is allocated by the user of the flash driver and - * passed into each of the driver APIs. - */ -typedef struct _flash_config -{ - uint32_t PFlashBlockBase; /*!< A base address of the first PFlash block */ - uint32_t PFlashTotalSize; /*!< The size of the combined PFlash block. */ - uint32_t PFlashBlockCount; /*!< A number of PFlash blocks. */ - uint32_t PFlashPageSize; /*!< The size in bytes of a page of PFlash. */ - uint32_t PFlashSectorSize; /*!< The size in bytes of a sector of PFlash. */ - flash_ffr_config_t ffrConfig; - flash_mode_config_t modeConfig; -} flash_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization - * @{ - */ - -/*! - * @brief Initializes the global flash properties structure members. - * - * This function checks and initializes the Flash module for the other Flash APIs. - * - * @param config Pointer to the storage for the driver runtime state. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_Init(flash_config_t *config); - -/*@}*/ - -/*! - * @name Erasing - * @{ - */ - -/*! - * @brief Erases the flash sectors encompassed by parameters passed into function. - * - * This function erases the appropriate number of flash sectors based on the - * desired start address and length. - * - * @param config The pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be erased. - * The start address need to be 512bytes-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words) - * to be erased. Must be 512bytes-aligned. - * @param key The value used to validate all flash erase APIs. - * - * @retval #kStatus_FLASH_Success API was executed successfully; - * the appropriate number of flash sectors based on the desired - * start address and length were erased successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_AddressError The address is out of range. - * @retval #kStatus_FLASH_EraseKeyError The API erase key is invalid. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - -/*@}*/ - -/*! - * @name Programming - * @{ - */ - -/*! - * @brief Programs flash with data at locations passed in through parameters. - * - * This function programs the flash memory with the desired data for a given - * flash area as determined by the start address and the length. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be programmed. Must be - * 512bytes-aligned. - * @param src A pointer to the source buffer of data that is to be programmed - * into the flash. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be programmed. Must be 512bytes-aligned. - * - * @retval #kStatus_FLASH_Success API was executed successfully; the desired data were programed successfully - * into flash based on desired start address and length. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); - -/*@}*/ - -/*! - * @brief Reads flash at locations passed in through parameters. - * - * This function read the flash memory from a given flash area as determined - * by the start address and the length. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be read. - * @param dest A pointer to the dest buffer of data that is to be read - * from the flash. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be read. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); - -/*! - * @name Verification - * @{ - */ - -/*! - * @brief Verifies an erasure of the desired flash area at a specified margin level. - * - * This function checks the appropriate number of flash sectors based on - * the desired start address and length to check whether the flash is erased - * to the specified read margin level. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be verified. - * The start address need to be 512bytes-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be verified. Must be 512bytes-aligned. - * - * @retval #kStatus_FLASH_Success API was executed successfully; the specified FLASH region has been erased. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); - -/*! - * @brief Verifies programming of the desired flash area at a specified margin level. - * - * This function verifies the data programed in the flash memory using the - * Flash Program Check Command and compares it to the expected data for a given - * flash area as determined by the start address and length. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be verified. need be 512bytes-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be verified. need be 512bytes-aligned. - * @param expectedData A pointer to the expected data that is to be - * verified against. - * @param failedAddress A pointer to the returned failing address. - * @param failedData A pointer to the returned failing data. Some derivatives do - * not include failed data as part of the FCCOBx registers. In this - * case, zeros are returned upon failure. - * - * @retval #kStatus_FLASH_Success API was executed successfully; - * the desired data have been successfully programed into specified FLASH region. - * - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_VerifyProgram(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - -/*@}*/ - -/*! - * @name Properties - * @{ - */ - -/*! - * @brief Returns the desired flash property. - * - * @param config A pointer to the storage for the driver runtime state. - * @param whichProperty The desired property from the list of properties in - * enum flash_property_tag_t - * @param value A pointer to the value returned for the desired flash property. - * - * @retval #kStatus_FLASH_Success API was executed successfully; the flash property was stored to value. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_UnknownProperty An unknown property tag. - */ -status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); - -/*@}*/ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* __FLASH_FLASH_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_ffr.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_ffr.h deleted file mode 100644 index 9481e07af14..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_ffr.h +++ /dev/null @@ -1,388 +0,0 @@ -/* - * Copyright 2018-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __FSL_IAP_FFR_H_ -#define __FSL_IAP_FFR_H_ - -#include "fsl_iap.h" - -/*! - * @addtogroup flash_ifr_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! - * @name Flash IFR version - * @{ - */ -/*! @brief Flash IFR driver version for SDK*/ -#define FSL_FLASH_IFR_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ -/*@}*/ - -/*! @brief Alignment(down) utility. */ -#if !defined(ALIGN_DOWN) -#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) -#endif - -/*! @brief Alignment(up) utility. */ -#if !defined(ALIGN_UP) -#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) -#endif - -#define FLASH_FFR_MAX_PAGE_SIZE (512u) -#define FLASH_FFR_HASH_DIGEST_SIZE (32u) -#define FLASH_FFR_IV_CODE_SIZE (52u) - -/*! @brief flash ffr page offset. */ -enum _flash_ffr_page_offset -{ - kFfrPageOffset_CFPA = 0, /*!< Customer In-Field programmed area*/ - kFfrPageOffset_CFPA_Scratch = 0, /*!< CFPA Scratch page */ - kFfrPageOffset_CFPA_Cfg = 1, /*!< CFPA Configuration area (Ping page)*/ - kFfrPageOffset_CFPA_CfgPong = 2, /*!< Same as CFPA page (Pong page)*/ - - kFfrPageOffset_CMPA = 3, /*!< Customer Manufacturing programmed area*/ - kFfrPageOffset_CMPA_Cfg = 3, /*!< CMPA Configuration area (Part of CMPA)*/ - kFfrPageOffset_CMPA_Key = 4, /*!< Key Store area (Part of CMPA)*/ - - kFfrPageOffset_NMPA = 7, /*!< NXP Manufacturing programmed area*/ - kFfrPageOffset_NMPA_Romcp = 7, /*!< ROM patch area (Part of NMPA)*/ - kFfrPageOffset_NMPA_Repair = 9, /*!< Repair area (Part of NMPA)*/ - kFfrPageOffset_NMPA_Cfg = 15, /*!< NMPA configuration area (Part of NMPA)*/ - kFfrPageOffset_NMPA_End = 16, /*!< Reserved (Part of NMPA)*/ -}; - -/*! @brief flash ffr page number. */ -enum _flash_ffr_page_num -{ - kFfrPageNum_CFPA = 3, /*!< Customer In-Field programmed area*/ - kFfrPageNum_CMPA = 4, /*!< Customer Manufacturing programmed area*/ - kFfrPageNum_NMPA = 10, /*!< NXP Manufacturing programmed area*/ - - kFfrPageNum_CMPA_Cfg = 1, - kFfrPageNum_CMPA_Key = 3, - kFfrPageNum_NMPA_Romcp = 2, - - kFfrPageNum_SpecArea = kFfrPageNum_CFPA + kFfrPageNum_CMPA, - kFfrPageNum_Total = (kFfrPageNum_CFPA + kFfrPageNum_CMPA + kFfrPageNum_NMPA), -}; - -enum _flash_ffr_block_size -{ - kFfrBlockSize_Key = 52u, - kFfrBlockSize_ActivationCode = 1192u, -}; - -typedef enum _cfpa_cfg_cmpa_prog_process -{ - kFfrCmpaProgProcess_Pre = 0x0u, - kFfrCmpaProgProcess_Post = 0xFFFFFFFFu, -} cmpa_prog_process_t; - -typedef struct _cfpa_cfg_iv_code -{ - uint32_t keycodeHeader; - uint8_t reserved[FLASH_FFR_IV_CODE_SIZE]; -} cfpa_cfg_iv_code_t; - -typedef struct _cfpa_cfg_info -{ - uint32_t header; /*!< [0x000-0x003] */ - uint32_t version; /*!< [0x004-0x007 */ - uint32_t secureFwVersion; /*!< [0x008-0x00b */ - uint32_t nsFwVersion; /*!< [0x00c-0x00f] */ - uint32_t imageKeyRevoke; /*!< [0x010-0x013] */ - uint8_t reserved0[4]; /*!< [0x014-0x017] */ - uint32_t rotkhRevoke; /*!< [0x018-0x01b] */ - uint32_t vendorUsage; /*!< [0x01c-0x01f] */ - uint32_t dcfgNsPin; /*!< [0x020-0x013] */ - uint32_t dcfgNsDflt; /*!< [0x024-0x017] */ - uint32_t enableFaMode; /*!< [0x028-0x02b] */ - uint8_t reserved1[4]; /*!< [0x02c-0x02f] */ - cfpa_cfg_iv_code_t ivCodePrinceRegion[3]; /*!< [0x030-0x0d7] */ - uint8_t reserved2[264]; /*!< [0x0d8-0x1df] */ - uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */ -} cfpa_cfg_info_t; - -#define FFR_BOOTCFG_BOOTSPEED_MASK (0x18U) -#define FFR_BOOTCFG_BOOTSPEED_SHIFT (7U) -#define FFR_BOOTCFG_BOOTSPEED_48MHZ (0x0U) -#define FFR_BOOTCFG_BOOTSPEED_96MHZ (0x1U) - -#define FFR_USBID_VENDORID_MASK (0xFFFFU) -#define FFR_USBID_VENDORID_SHIFT (0U) -#define FFR_USBID_PRODUCTID_MASK (0xFFFF0000U) -#define FFR_USBID_PRODUCTID_SHIFT (16U) - -typedef struct _cmpa_cfg_info -{ - uint32_t bootCfg; /*!< [0x000-0x003] */ - uint32_t spiFlashCfg; /*!< [0x004-0x007] */ - struct - { - uint16_t vid; - uint16_t pid; - } usbId; /*!< [0x008-0x00b] */ - uint32_t sdioCfg; /*!< [0x00c-0x00f] */ - uint32_t dcfgPin; /*!< [0x010-0x013] */ - uint32_t dcfgDflt; /*!< [0x014-0x017] */ - uint32_t dapVendorUsage; /*!< [0x018-0x01b] */ - uint32_t secureBootCfg; /*!< [0x01c-0x01f] */ - uint32_t princeBaseAddr; /*!< [0x020-0x023] */ - uint32_t princeSr[3]; /*!< [0x024-0x02f] */ - uint8_t reserved0[32]; /*!< [0x030-0x04f] */ - uint32_t rotkh[8]; /*!< [0x050-0x06f] */ - uint8_t reserved1[368]; /*!< [0x070-0x1df] */ - uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */ -} cmpa_cfg_info_t; - -typedef struct _cmpa_key_store_header -{ - uint32_t header; - uint8_t reserved[4]; -} cmpa_key_store_header_t; - -#define FFR_SYSTEM_SPEED_CODE_MASK (0x3U) -#define FFR_SYSTEM_SPEED_CODE_SHIFT (0U) -#define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ (0x0U) -#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_24MHZ (0x1U) -#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_48MHZ (0x2U) -#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_96MHZ (0x3U) - -#define FFR_PERIPHERALCFG_PERI_MASK (0x7FFFFFFFU) -#define FFR_PERIPHERALCFG_PERI_SHIFT (0U) -#define FFR_PERIPHERALCFG_COREEN_MASK (0x10000000U) -#define FFR_PERIPHERALCFG_COREEN_SHIFT (31U) - -typedef struct _nmpa_cfg_info -{ - uint16_t fro32kCfg; /*!< [0x000-0x001] */ - uint8_t reserved0[6]; /*!< [0x002-0x007] */ - uint8_t sysCfg; /*!< [0x008-0x008] */ - uint8_t reserved1[7]; /*!< [0x009-0x00f] */ - struct - { - uint32_t data; - uint32_t reserved[3]; - } GpoInitData[3]; /*!< [0x010-0x03f] */ - uint32_t GpoDataChecksum[4]; /*!< [0x040-0x04f] */ - uint32_t finalTestBatchId[4]; /*!< [0x050-0x05f] */ - uint32_t deviceType; /*!< [0x060-0x063] */ - uint32_t finalTestProgVersion; /*!< [0x064-0x067] */ - uint32_t finalTestDate; /*!< [0x068-0x06b] */ - uint32_t finalTestTime; /*!< [0x06c-0x06f] */ - uint32_t uuid[4]; /*!< [0x070-0x07f] */ - uint8_t reserved2[32]; /*!< [0x080-0x09f] */ - uint32_t peripheralCfg; /*!< [0x0a0-0x0a3] */ - uint32_t ramSizeCfg; /*!< [0x0a4-0x0a7] */ - uint32_t flashSizeCfg; /*!< [0x0a8-0x0ab] */ - uint8_t reserved3[36]; /*!< [0x0ac-0x0cf] */ - uint8_t fro1mCfg; /*!< [0x0d0-0x0d0] */ - uint8_t reserved4[15]; /*!< [0x0d1-0x0df] */ - uint32_t dcdc[4]; /*!< [0x0e0-0x0ef] */ - uint32_t bod; /*!< [0x0f0-0x0f3] */ - uint8_t reserved5[12]; /*!< [0x0f4-0x0ff] */ - uint8_t calcHashReserved[192]; /*!< [0x100-0x1bf] */ - uint8_t sha256[32]; /*!< [0x1c0-0x1df] */ - uint32_t ecidBackup[4]; /*!< [0x1e0-0x1ef] */ - uint32_t pageChecksum[4]; /*!< [0x1f0-0x1ff] */ -} nmpa_cfg_info_t; - -typedef struct _ffr_key_store -{ - uint8_t reserved[3][FLASH_FFR_MAX_PAGE_SIZE]; -} ffr_key_store_t; - -typedef enum _ffr_key_type -{ - kFFR_KeyTypeSbkek = 0x00U, - kFFR_KeyTypeUser = 0x01U, - kFFR_KeyTypeUds = 0x02U, - kFFR_KeyTypePrinceRegion0 = 0x03U, - kFFR_KeyTypePrinceRegion1 = 0x04U, - kFFR_KeyTypePrinceRegion2 = 0x05U, -} ffr_key_type_t; - -typedef enum _ffr_bank_type -{ - kFFR_BankTypeBank0_NMPA = 0x00U, - kFFR_BankTypeBank1_CMPA = 0x01U, - kFFR_BankTypeBank2_CFPA = 0x02U -} ffr_bank_type_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name FFR APIs - * @{ - */ - -/*! - * @brief Initializes the global FFR properties structure members. - * - * @param config A pointer to the storage for the driver runtime state. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - */ -status_t FFR_Init(flash_config_t *config); - -/*! - * @brief Enable firewall for all flash banks. - * - * CFPA, CMPA, and NMPA flash areas region will be locked, After this function executed; - * Unless the board is reset again. - * - * @param config A pointer to the storage for the driver runtime state. - * - * @retval #kStatus_FLASH_Success An invalid argument is provided. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - */ -status_t FFR_Lock_All(flash_config_t *config); - -/*! - * @brief APIs to access CFPA pages - * - * This routine will erase CFPA and program the CFPA page with passed data. - * - * @param config A pointer to the storage for the driver runtime state. - * @param page_data A pointer to the source buffer of data that is to be programmed - * into the CFPA. - * @param valid_len The length, given in bytes, to be programmed. - * - * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CFPA. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_FfrBankIsLocked The CFPA was locked. - * @retval #kStatus_FLASH_OutOfDateCfpaPage It is not newest CFPA page. - */ -status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); - -/*! - * @brief APIs to access CFPA pages - * - * Generic read function, used by customer to read data stored in 'Customer In-field Page'. - * - * @param config A pointer to the storage for the driver runtime state. - * @param pData A pointer to the dest buffer of data that is to be read from 'Customer In-field Page'. - * @param offset An offset from the 'Customer In-field Page' start address. - * @param len The length, given in bytes, to be read. - * - * @retval #kStatus_FLASH_Success Get data from 'Customer In-field Page'. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_CommandFailure access error. - */ -status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - -/*! - * @brief APIs to access CMPA pages - * - * This routine will erase "customer factory page" and program the page with passed data. - * If 'seal_part' parameter is TRUE then the routine will compute SHA256 hash of - * the page contents and then programs the pages. - * 1.During development customer code uses this API with 'seal_part' set to FALSE. - * 2.During manufacturing this parameter should be set to TRUE to seal the part - * from further modifications - * 3.This routine checks if the page is sealed or not. A page is said to be sealed if - * the SHA256 value in the page has non-zero value. On boot ROM locks the firewall for - * the region if hash is programmed anyways. So, write/erase commands will fail eventually. - * - * @param config A pointer to the storage for the driver runtime state. - * @param page_data A pointer to the source buffer of data that is to be programmed - * into the "customer factory page". - * @param seal_part Set fasle for During development customer code. - * - * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CMPA. - * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. - * @retval kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_CommandFailure access error. - */ -status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part); - -/*! - * @brief APIs to access CMPA page - * - * Read data stored in 'Customer Factory CFG Page'. - * - * @param config A pointer to the storage for the driver runtime state. - * @param pData A pointer to the dest buffer of data that is to be read - * from the Customer Factory CFG Page. - * @param offset Address offset relative to the CMPA area. - * @param len The length, given in bytes to be read. - * - * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. - * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. - * @retval kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_CommandFailure access error. - */ -status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - -/*! - * @brief APIs to access CMPA page - * - * 1.SW should use this API routine to get the UUID of the chip. - * 2.Calling routine should pass a pointer to buffer which can hold 128-bit value. - */ -status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid); - -/*! - * @brief This routine writes the 3 pages allocated for Key store data, - * - * 1.Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state. - * 2.Optional routines to set individual data members (activation code, key codes etc) to construct - * the key store structure in RAM before committing it to IFR/FFR. - * - * @param config A pointer to the storage for the driver runtime state. - * @param pKeyStore A Pointer to the 3 pages allocated for Key store data. - * that will be written to 'customer factory page'. - * - * @retval #kStatus_FLASH_Success The key were programed successfully into FFR. - * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. - * @retval kStatus_FTFx_AddressError Address is out of range. - * @retval #kStatus_FLASH_CommandFailure access error. - */ -status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore); - -/*! - * @brief Get/Read Key store code routines - * - * 1. Calling code should pass buffer pointer which can hold activation code 1192 bytes. - * 2. Check if flash aperture is small or regular and read the data appropriately. - */ -status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode); - -/*! - * @brief Get/Read Key store code routines - * - * 1. Calling code should pass buffer pointer which can hold key code 52 bytes. - * 2. Check if flash aperture is small or regular and read the data appropriately. - * 3. keyIndex specifies which key code is read. - */ -status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); - -/*@}*/ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /*! __FSL_FLASH_FFR_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_kbp.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_kbp.h deleted file mode 100644 index 453a89a8fde..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_kbp.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * Copyright (c) 2020-2021, Freescale Semiconductor, Inc. - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_IAP_KBP_H_ -#define _FSL_IAP_KBP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup kb_driver - * @{ - */ -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @brief ROM API status group number */ -#define kStatusGroup_RomApi (108U) - -/*! @brief ROM API status codes. */ -enum -{ - kStatus_RomApiExecuteCompleted = kStatus_Success, /*!< ROM successfully process the whole sb file/boot image.*/ - kStatus_RomApiNeedMoreData = - MAKE_STATUS(kStatusGroup_RomApi, 1), /*!< ROM needs more data to continue processing the boot image.*/ - kStatus_RomApiBufferSizeNotEnough = - MAKE_STATUS(kStatusGroup_RomApi, - 2), /*!< The user buffer is not enough for use by Kboot during execution of the operation.*/ - kStatus_RomApiInvalidBuffer = - MAKE_STATUS(kStatusGroup_RomApi, 3), /*!< The user buffer is not ok for sbloader or authentication.*/ -}; - -/*! - * @brief Details of the operation to be performed by the ROM. - * - * The #kRomAuthenticateImage operation requires the entire signed image to be - * available to the application. - */ -typedef enum _kb_operation -{ - kRomAuthenticateImage = 1, /*!< Authenticate a signed image.*/ - kRomLoadImage = 2, /*!< Load SB file.*/ - kRomOperationCount = 3, -} kb_operation_t; - -/*! - * @brief Security constraint flags, Security profile flags. - */ -enum _kb_security_profile -{ - kKbootMinRSA4096 = (1 << 16), -}; - -/*! - * @brief Memory region definition. - */ -typedef struct _kb_region -{ - uint32_t address; - uint32_t length; -} kb_region_t; - -/*! - * @brief User-provided options passed into kb_init(). - * - * The buffer field is a pointer to memory provided by the caller for use by - * Kboot during execution of the operation. Minimum size is the size of each - * certificate in the chain plus 432 bytes additional per certificate. - * - * The profile field is a mask that specifies which features are required in - * the SB file or image being processed. This includes the minimum AES and RSA - * key sizes. See the _kb_security_profile enum for profile mask constants. - * The image being loaded or authenticated must match the profile or an error will - * be returned. - * - * minBuildNumber is an optional field that can be used to prevent version - * rollback. The API will check the build number of the image, and if it is less - * than minBuildNumber will fail with an error. - * - * maxImageLength is used to verify the offsetToCertificateBlockHeaderInBytes - * value at the beginning of a signed image. It should be set to the length of - * the SB file. If verifying an image in flash, it can be set to the internal - * flash size or a large number like 0x10000000. - * - * userRHK can optionally be used by the user to override the RHK in IFR. If - * userRHK is not NULL, it points to a 32-byte array containing the SHA-256 of - * the root certificate's RSA public key. - * - * The regions field points to an array of memory regions that the SB file being - * loaded is allowed to access. If regions is NULL, then all memory is - * accessible by the SB file. This feature is required to prevent a malicious - * image from erasing good code or RAM contents while it is being loaded, only - * for us to find that the image is inauthentic when we hit the end of the - * section. - * - * overrideSBBootSectionID lets the caller override the default section of the - * SB file that is processed during a kKbootLoadSB operation. By default, - * the section specified in the firstBootableSectionID field of the SB header - * is loaded. If overrideSBBootSectionID is non-zero, then the section with - * the given ID will be loaded instead. - * - * The userSBKEK field lets a user provide their own AES-256 key for unwrapping - * keys in an SB file during the kKbootLoadSB operation. userSBKEK should point - * to a 32-byte AES-256 key. If userSBKEK is NULL then the IFR SBKEK will be used. - * After kb_init() returns, the caller should zero out the data pointed to by - * userSBKEK, as the API will have installed the key in the CAU3. - */ - -typedef struct _kb_load_sb -{ - uint32_t profile; - uint32_t minBuildNumber; - uint32_t overrideSBBootSectionID; - uint32_t *userSBKEK; - uint32_t regionCount; - const kb_region_t *regions; -} kb_load_sb_t; - -typedef struct _kb_authenticate -{ - uint32_t profile; - uint32_t minBuildNumber; - uint32_t maxImageLength; - uint32_t *userRHK; -} kb_authenticate_t; - -typedef struct _kb_options -{ - uint32_t version; /*!< Should be set to kKbootApiVersion.*/ - uint8_t *buffer; /*!< Caller-provided buffer used by Kboot.*/ - uint32_t bufferLength; - kb_operation_t op; - union - { - kb_authenticate_t authenticate; /*! Settings for kKbootAuthenticate operation.*/ - kb_load_sb_t loadSB; /*! Settings for kKbootLoadSB operation.*/ - }; -} kb_options_t; - -/*! - * @brief Interface to memory operations for one region of memory. - */ -typedef struct _memory_region_interface -{ - status_t (*init)(void); - status_t (*read)(uint32_t address, uint32_t length, uint8_t *buffer); - status_t (*write)(uint32_t address, uint32_t length, const uint8_t *buffer); - status_t (*fill)(uint32_t address, uint32_t length, uint32_t pattern); - status_t (*flush)(void); - status_t (*erase)(uint32_t address, uint32_t length); - status_t (*config)(uint32_t *buffer); - status_t (*erase_all)(void); -} memory_region_interface_t; - -/*! - * @brief Structure of a memory map entry. - */ -typedef struct _memory_map_entry -{ - uint32_t startAddress; - uint32_t endAddress; - uint32_t memoryProperty; - uint32_t memoryId; - const memory_region_interface_t *memoryInterface; -} memory_map_entry_t; - -typedef struct _kb_opaque_session_ref -{ - kb_options_t context; - bool cau3Initialized; - memory_map_entry_t *memoryMap; -} kb_session_ref_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize ROM API for a given operation. - * - * Inits the ROM API based on the options provided by the application in the second - * argument. Every call to rom_init() should be paired with a call to rom_deinit(). - * - * @retval #kStatus_Success API was executed successfully. - * @retval #kStatus_InvalidArgument An invalid argument is provided. - * @retval #kStatus_RomApiBufferSizeNotEnough The user buffer is not enough for use by Kboot during execution of the - * operation. - * @retval #kStatus_RomApiInvalidBuffer The user buffer is not ok for sbloader or authentication. - * @retval #kStatus_SKBOOT_Fail Return the failed status of secure boot. - * @retval #kStatus_SKBOOT_KeyStoreMarkerInvalid The key code for the particular PRINCE region is not present in the - * keystore - * @retval #kStatus_SKBOOT_Success Return the successful status of secure boot. - */ -status_t kb_init(kb_session_ref_t **session, const kb_options_t *options); - -/*! - * @brief Cleans up the ROM API context. - * - * After this call, the context parameter can be reused for another operation - * by calling rom_init() again. - * - * @retval #kStatus_Success API was executed successfully - */ -status_t kb_deinit(kb_session_ref_t *session); - -/*! - * Perform the operation configured during init. - * - * This application must call this API repeatedly, passing in sequential chunks of - * data from the boot image (SB file) that is to be processed. The ROM will perform - * the selected operation on this data and return. The application may call this - * function with as much or as little data as it wishes, which can be used to select - * the granularity of time given to the application in between executing the operation. - * - * @param session Current ROM context pointer. - * @param data Buffer of boot image data provided to the ROM by the application. - * @param dataLength Length in bytes of the data in the buffer provided to the ROM. - * - * @retval #kStatus_Success ROM successfully process the part of sb file/boot image. - * @retval #kStatus_RomApiExecuteCompleted ROM successfully process the whole sb file/boot image. - * @retval #kStatus_Fail An error occurred while executing the operation. - * @retval #kStatus_RomApiNeedMoreData No error occurred, but the ROM needs more data to - * continue processing the boot image. - * @retval #kStatus_RomApiBufferSizeNotEnough user buffer is not enough for - * use by Kboot during execution of the operation. - */ -status_t kb_execute(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength); - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_IAP_KBP_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_skboot_authenticate.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_skboot_authenticate.h deleted file mode 100644 index 67a513bc3cf..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_skboot_authenticate.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _FSL_IAP_SKBOOT_AUTHENTICATE_H_ -#define _FSL_IAP_SKBOOT_AUTHENTICATE_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup skboot_authenticate - * @{ - */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @brief SKBOOT return status*/ -typedef enum _skboot_status -{ - kStatus_SKBOOT_Success = 0x5ac3c35au, /*!< SKBOOT return success status.*/ - kStatus_SKBOOT_Fail = 0xc35ac35au, /*!< SKBOOT return fail status.*/ - kStatus_SKBOOT_InvalidArgument = 0xc35a5ac3u, /*!< SKBOOT return invalid argument status.*/ - kStatus_SKBOOT_KeyStoreMarkerInvalid = 0xc3c35a5au, /*!< SKBOOT return Keystore invalid Marker status.*/ - kStatus_SKBOOT_HashcryptFinishedWithStatusSuccess = - 0xc15a5ac3, /*!< SKBOOT return Hashcrypt finished with the success status.*/ - kStatus_SKBOOT_HashcryptFinishedWithStatusFail = - 0xc15a5acb, /*!< SKBOOT return Hashcrypt finished with the fail status.*/ -} skboot_status_t; - -/*! @brief Secure bool flag*/ -typedef enum _secure_bool -{ - kSECURE_TRUE = 0xc33cc33cU, /*!< Secure true flag.*/ - kSECURE_FALSE = 0x5aa55aa5U, /*!< Secure false flag.*/ - kSECURE_CALLPROTECT_SECURITY_FLAGS = 0xc33c5aa5U, /*!< Secure call protect the security flag.*/ - kSECURE_CALLPROTECT_IS_APP_READY = 0x5aa5c33cU, /*!< Secure call protect the app is ready flag.*/ - kSECURE_TRACKER_VERIFIED = 0x55aacc33U, /*!< Secure tracker verified flag.*/ -} secure_bool_t; - -/******************************************************************************* - * Externs - ******************************************************************************/ - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Authenticate entry function with ARENA allocator init - * - * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface - */ -skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified); - -/*! - * @brief Interface for image authentication API - */ -void HASH_IRQHandler(void); - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_IAP_SKBOOT_AUTHENTICATE_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.c deleted file mode 100644 index 5ef935985fb..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_inputmux.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.inputmux" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Initialize INPUTMUX peripheral. - - * This function enables the INPUTMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * - * retval None. - */ -void INPUTMUX_Init(INPUTMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE - CLOCK_EnableClock(kCLOCK_Sct); - CLOCK_EnableClock(kCLOCK_Dma); -#else - CLOCK_EnableClock(kCLOCK_InputMux); -#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Attaches a signal - * - * This function gates the INPUTPMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * param index Destination peripheral to attach the signal to. - * param connection Selects connection. - * - * retval None. - */ -void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection) -{ - uint32_t pmux_id; - uint32_t output_id; - - /* extract pmux to be used */ - pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT; - /* extract function number */ - output_id = ((uint32_t)(connection)) & ((1UL << PMUX_SHIFT) - 1U); - /* programm signal */ - *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4U)) = output_id; -} - -#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) -/*! - * brief Enable/disable a signal - * - * This function gates the INPUTPMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * param signal Enable signal register id and bit offset. - * param enable Selects enable or disable. - * - * retval None. - */ -void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable) -{ - uint32_t ena_id; - uint32_t ena_id_mask = (1UL << (32U - ENA_SHIFT)) - 1U; - uint32_t bit_offset; - -#if defined(FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX) && FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX - uint32_t chmux_offset; - uint32_t chmux_value; - - /* Only enable need to update channel mux */ - if (enable && ((((uint32_t)signal) & (1UL << CHMUX_AVL_SHIFT)) != 0U)) - { - chmux_offset = (((uint32_t)signal) >> CHMUX_OFF_SHIFT) & ((1UL << (CHMUX_AVL_SHIFT - CHMUX_OFF_SHIFT)) - 1UL); - chmux_value = (((uint32_t)signal) >> CHMUX_VAL_SHIFT) & ((1UL << (CHMUX_OFF_SHIFT - CHMUX_VAL_SHIFT)) - 1UL); - *(volatile uint32_t *)(((uint32_t)base) + chmux_offset) = chmux_value; - } - ena_id_mask = (1UL << (CHMUX_VAL_SHIFT - ENA_SHIFT)) - 1U; -#endif - /* extract enable register to be used */ - ena_id = (((uint32_t)signal) >> ENA_SHIFT) & ena_id_mask; - /* extract enable bit offset */ - bit_offset = ((uint32_t)signal) & ((1UL << ENA_SHIFT) - 1U); - /* set signal */ - if (enable) - { - *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1UL << bit_offset); - } - else - { - *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1UL << bit_offset); - } -} -#endif - -/*! - * brief Deinitialize INPUTMUX peripheral. - - * This function disables the INPUTMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * - * retval None. - */ -void INPUTMUX_Deinit(INPUTMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE - CLOCK_DisableClock(kCLOCK_Sct); - CLOCK_DisableClock(kCLOCK_Dma); -#else - CLOCK_DisableClock(kCLOCK_InputMux); -#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.h deleted file mode 100644 index ddb9e26c55f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_INPUTMUX_H_ -#define _FSL_INPUTMUX_H_ - -#include "fsl_inputmux_connections.h" -#include "fsl_common.h" - -/*! - * @addtogroup inputmux_driver - * @{ - */ - -/*! @file */ -/*! @file fsl_inputmux_connections.h */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Group interrupt driver version for SDK */ -#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) -/*@}*/ - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @brief Initialize INPUTMUX peripheral. - - * This function enables the INPUTMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * - * @retval None. - */ -void INPUTMUX_Init(INPUTMUX_Type *base); - -/*! - * @brief Attaches a signal - * - * This function gates the INPUTPMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * @param index Destination peripheral to attach the signal to. - * @param connection Selects connection. - * - * @retval None. - */ -void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection); - -#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) -/*! - * @brief Enable/disable a signal - * - * This function gates the INPUTPMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * @param signal Enable signal register id and bit offset. - * @param enable Selects enable or disable. - * - * @retval None. - */ -void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable); -#endif - -/*! - * @brief Deinitialize INPUTMUX peripheral. - - * This function disables the INPUTMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * - * @retval None. - */ -void INPUTMUX_Deinit(INPUTMUX_Type *base); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_INPUTMUX_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux_connections.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux_connections.h deleted file mode 100644 index 6031941dcaa..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux_connections.h +++ /dev/null @@ -1,496 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_INPUTMUX_CONNECTIONS_ -#define _FSL_INPUTMUX_CONNECTIONS_ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" -#endif - -/*! - * @addtogroup inputmux_driver - * @{ - */ - -/*! - * @name Input multiplexing connections - * @{ - */ - -/*! @brief Periphinmux IDs */ -#define SCT0_INMUX0 0x00U -#define TIMER0CAPTSEL0 0x20U -#define TIMER1CAPTSEL0 0x40U -#define TIMER2CAPTSEL0 0x60U -#define PINTSEL_PMUX_ID 0xC0U -#define PINTSEL0 0xC0U -#define DMA0_ITRIG_INMUX0 0xE0U -#define DMA0_OTRIG_INMUX0 0x160U -#define FREQMEAS_REF_REG 0x180U -#define FREQMEAS_TARGET_REG 0x184U -#define TIMER3CAPTSEL0 0x1A0U -#define TIMER4CAPTSEL0 0x1C0U -#define PINTSECSEL0 0x1E0U -#define DMA1_ITRIG_INMUX0 0x200U -#define DMA1_OTRIG_INMUX0 0x240U -#define DMA0_REQ_ENA_ID 0x740U -#define DMA1_REQ_ENA_ID 0x760U -#define DMA0_ITRIG_ENA_ID 0x780U -#define DMA1_ITRIG_ENA_ID 0x7A0U -#define ENA_SHIFT 8U -#define PMUX_SHIFT 20U - -/*! @brief INPUTMUX connections type */ -typedef enum _inputmux_connection_t -{ - /*!< SCT0 INMUX. */ - kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToSct0 = 8U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToSct0 = 9U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToSct0 = 10U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToSct0 = 11U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToSct0 = 12U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_AdcIrqToSct0 = 13U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToSct0 = 14U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToSct0 = 16U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_CompOutToSct0 = 17U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedSck0ToSct0 = 18U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedSck1ToSct0 = 19U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToSct0 = 20U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToSct0 = 21U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_ArmTxevToSct0 = 22U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_DebugHaltedToSct0 = 23U + (SCT0_INMUX0 << PMUX_SHIFT), - - /*!< TIMER0 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer0Captsel = 0U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer0Captsel = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer0Captsel = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer0Captsel = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToTimer0Captsel = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - - /*!< TIMER1 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer1Captsel = 0U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer1Captsel = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer1Captsel = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer1Captsel = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToTimer1Captsel = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - - /*!< TIMER2 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer2Captsel = 0U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer2Captsel = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer2Captsel = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer2Captsel = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToTimer2Captsel = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - - /*!< Pin interrupt select. */ - kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL0 << PMUX_SHIFT), - - /*!< DMA0 Input trigger. */ - kINPUTMUX_PinInt0ToDma0 = 0U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt1ToDma0 = 1U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt2ToDma0 = 2U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt3ToDma0 = 3U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToDma0 = 4U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M1ToDma0 = 5U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToDma0 = 6U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M1ToDma0 = 7U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToDma0 = 8U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M1ToDma0 = 9U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToDma0 = 10U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M1ToDma0 = 11U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToDma0 = 12U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M1ToDma0 = 13U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_CompOutToDma0 = 14U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig0ToDma0 = 15U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig1ToDma0 = 16U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig2ToDma0 = 17U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig3ToDma0 = 18U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq0ToDma0 = 19U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq1ToDma0 = 20U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_HashDmaRxToDma0 = 21U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - - /*!< DMA0 output trigger. */ - kINPUTMUX_Dma0Hash0TxTrigoutToTriginChannels = 0U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0HsLspiRxTrigoutToTriginChannels = 2U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0HsLspiTxTrigoutToTriginChannels = 3U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm3RxTrigoutToTriginChannels = 8U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm3TxTrigoutToTriginChannels = 9U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm2RxTrigoutToTriginChannels = 10U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm2TxTrigoutToTriginChannels = 11U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm4RxTrigoutToTriginChannels = 12U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm4TxTrigoutToTriginChannels = 13U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm5RxTrigoutToTriginChannels = 14U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm5TxTrigoutToTriginChannels = 15U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm6RxTrigoutToTriginChannels = 16U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm6TxTrigoutToTriginChannels = 17U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm7RxTrigoutToTriginChannels = 18U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm7TxTrigoutToTriginChannels = 19U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Adc0Ch0TrigoutToTriginChannels = 21U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Adc0Ch1TrigoutToTriginChannels = 22U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - - /*!< Selection for frequency measurement reference clock. */ - kINPUTMUX_ExternOscToFreqmeasRef = 0U + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_Fro12MhzToFreqmeasRef = 1u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_Fro96MhzToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_WdtOscToFreqmeasRef = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_32KhzOscToFreqmeasRef = 4u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_MainClkToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_aRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_bRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT), - - /*!< Selection for frequency measurement target clock. */ - kINPUTMUX_ExternOscToFreqmeasTarget = 0U + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_Fro12MhzToFreqmeasTarget = 1u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_Fro96MhzToFreqmeasTarget = 2u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_WdtOscToFreqmeasTarget = 3u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_32KhzOscToFreqmeasTarget = 4u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_MainClkToFreqmeasTarget = 5u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_aTarget = 6u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_bTarget = 7u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - - /*!< TIMER3 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer3Captsel = 0U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer3Captsel = 17U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer3Captsel = 18U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer3Captsel = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToTimer3Captsel = 21U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - - /*!< Timer4 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer4Captsel = 0U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer4Captsel = 17U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer4Captsel = 18U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer4Captsel = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToTimer4Captsel = 21U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - - /*Pin interrupt secure select */ - kINPUTMUX_GpioPort0Pin0ToPintSecsel = 0U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin1ToPintSecsel = 1U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin2ToPintSecsel = 2U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin3ToPintSecsel = 3U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin4ToPintSecsel = 4U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin5ToPintSecsel = 5U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin6ToPintSecsel = 6U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin7ToPintSecsel = 7U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin8ToPintSecsel = 8U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin9ToPintSecsel = 9U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin10ToPintSecsel = 10U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin11ToPintSecsel = 11U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin12ToPintSecsel = 12U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin13ToPintSecsel = 13U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin14ToPintSecsel = 14U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin15ToPintSecsel = 15U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin16ToPintSecsel = 16U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin17ToPintSecsel = 17U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin18ToPintSecsel = 18U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin19ToPintSecsel = 19U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin20ToPintSecsel = 20U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin21ToPintSecsel = 21U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin22ToPintSecsel = 22U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin23ToPintSecsel = 23U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin24ToPintSecsel = 24U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin25ToPintSecsel = 25U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin26ToPintSecsel = 26U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin27ToPintSecsel = 27U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin28ToPintSecsel = 28U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin29ToPintSecsel = 29U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin30ToPintSecsel = 30U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin31ToPintSecsel = 31U + (PINTSECSEL0 << PMUX_SHIFT), - - /*!< DMA1 Input trigger. */ - kINPUTMUX_PinInt0ToDma1 = 0U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt1ToDma1 = 1U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt2ToDma1 = 2U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt3ToDma1 = 3U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToDma1 = 4U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M1ToDma1 = 5U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToDma1 = 6U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToDma1 = 7U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig0ToDma1 = 8U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig1ToDma1 = 9U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig2ToDma1 = 10U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig3ToDma1 = 11U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq0ToDma1 = 12U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq1ToDma1 = 13U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_HashDmaRxToDma1 = 14U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - - /*!< DMA1 output trigger. */ - kINPUTMUX_Dma1Hash0TxTrigoutToTriginChannels = 0U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1HsLspiRxTrigoutToTriginChannels = 2U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1HsLspiTxTrigoutToTriginChannels = 3U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm3RxTrigoutToTriginChannels = 8U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm3TxTrigoutToTriginChannels = 9U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), -} inputmux_connection_t; - -/*! @brief INPUTMUX signal enable/disable type */ -typedef enum _inputmux_signal_t -{ - /*!< DMA0 REQ signal. */ - kINPUTMUX_HashCryptToDmac0Ch0RequestEna = 0U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm8RxToDmac0Ch2RequestEna = 2U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm8TxToDmac0Ch3RequestEna = 3U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm0RxToDmac0Ch4RequestEna = 4U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm0TxToDmac0Ch5RequestEna = 5U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm1RxToDmac0Ch6RequestEna = 6U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm1TxToDmac0Ch7RequestEna = 7U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm3RxToDmac0Ch8RequestEna = 8U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm3TxToDmac0Ch9RequestEna = 9U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm2RxToDmac0Ch10RequestEna = 10U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm2TxToDmac0Ch11RequestEna = 11U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm4RxToDmac0Ch12RequestEna = 12U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm4TxToDmac0Ch13RequestEna = 13U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm5RxToDmac0Ch14RequestEna = 14U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm5TxToDmac0Ch15RequestEna = 15U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm6RxToDmac0Ch16RequestEna = 16U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm6TxToDmac0Ch17RequestEna = 17U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm7RxToDmac0Ch18RequestEna = 18U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm7TxToDmac0Ch19RequestEna = 19U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Adc0FIFO0ToDmac0Ch21RequestEna = 21U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Adc0FIFO1ToDmac0Ch22RequestEna = 22U + (DMA0_REQ_ENA_ID << ENA_SHIFT), - - /*!< DMA1 REQ signal. */ - kINPUTMUX_HashCryptToDmac1Ch0RequestEna = 0U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm8RxToDmac1Ch2RequestEna = 2U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm8TxToDmac1Ch3RequestEna = 3U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm0RxToDmac1Ch4RequestEna = 4U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm0TxToDmac1Ch5RequestEna = 5U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm1RxToDmac1Ch6RequestEna = 6U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm1TxToDmac1Ch7RequestEna = 7U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm3RxToDmac1Ch8RequestEna = 8U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - kINPUTMUX_Flexcomm3TxToDmac1Ch9RequestEna = 9U + (DMA1_REQ_ENA_ID << ENA_SHIFT), - - /*!< DMA0 input trigger source enable. */ - kINPUTMUX_Dmac0InputTriggerPint0Ena = 0U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerPint1Ena = 1U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerPint2Ena = 2U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerPint3Ena = 3U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer0M0Ena = 4U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer0M1Ena = 5U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer1M0Ena = 6U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer1M1Ena = 7U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer2M0Ena = 8U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer2M1Ena = 9U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer3M0Ena = 10U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer3M1Ena = 11U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer4M0Ena = 12U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCtimer4M1Ena = 13U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerCompOutEna = 14U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerDma0Out0Ena = 15U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerDma0Out1Ena = 16U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerDma0Out2Ena = 17U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerDma0Out3Ena = 18U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerSctDmac0Ena = 19U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerSctDmac1Ena = 20U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac0InputTriggerHashOutEna = 21U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), - - /*!< DMA1 input trigger source enable. */ - kINPUTMUX_Dmac1InputTriggerPint0Ena = 0U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerPint1Ena = 1U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerPint2Ena = 2U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerPint3Ena = 3U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerCtimer0M0Ena = 4U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerCtimer0M1Ena = 5U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerCtimer2M0Ena = 6U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerCtimer4M0Ena = 7U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerDma1Out0Ena = 8U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerDma1Out1Ena = 9U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerDma1Out2Ena = 10U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerDma1Out3Ena = 11U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerSctDmac0Ena = 12U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerSctDmac1Ena = 13U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), - kINPUTMUX_Dmac1InputTriggerHashOutEna = 14U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), -} inputmux_signal_t; - -/*@}*/ - -/*@}*/ - -#endif /* _FSL_INPUTMUX_CONNECTIONS_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iocon.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iocon.h deleted file mode 100644 index e705e91f66c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iocon.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_IOCON_H_ -#define _FSL_IOCON_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_iocon - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon" -#endif - -/*! @name Driver version */ -/*@{*/ -/*! @brief IOCON driver version. */ -#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) -/*@}*/ - -/** - * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format - */ -typedef struct _iocon_group -{ - uint8_t port; /* Pin port */ - uint8_t pin; /* Pin number */ - uint8_t ionumber; /* IO number */ - uint16_t modefunc; /* Function and mode */ -} iocon_group_t; - -/** - * @brief IOCON function and mode selection definitions - * @note See the User Manual for specific modes and functions supported by the various pins. - */ -#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ -#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ -#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ -#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ -#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ -#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ -#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ -#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ -#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) -#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ -#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ -#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ -#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ -#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ -#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ -#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ -#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ -#endif /* FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH */ - -#if defined(IOCON_PIO_MODE_SHIFT) -#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ -#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ -#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ -#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ -#endif - -#if defined(IOCON_PIO_I2CSLEW_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_MODE (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ -#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */ -#endif - -#if defined(IOCON_PIO_EGP_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_MODE (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ -#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */ -#endif - -#if defined(IOCON_PIO_SLEW_SHIFT) -#define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ -#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ -#endif - -#if defined(IOCON_PIO_INVERT_SHIFT) -#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */ -#endif - -#if defined(IOCON_PIO_DIGIMODE_SHIFT) -#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */ -#define IOCON_DIGITAL_EN \ - (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */ -#endif - -#if defined(IOCON_PIO_FILTEROFF_SHIFT) -#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ -#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ -#endif - -#if defined(IOCON_PIO_I2CDRIVE_SHIFT) -#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ -#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ -#endif - -#if defined(IOCON_PIO_OD_SHIFT) -#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */ -#endif - -#if defined(IOCON_PIO_I2CFILTER_SHIFT) -#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ -#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */ -#endif - -#if defined(IOCON_PIO_ASW_SHIFT) -#define IOCON_AWS_EN (0x1 << IOCON_PIO_ASW_SHIFT) /*!< Enables analog switch function */ -#endif - -#if defined(IOCON_PIO_SSEL_SHIFT) -#define IOCON_SSEL_3V3 (0x0 << IOCON_PIO_SSEL_SHIFT) /*!< 3V3 signaling in I2C mode */ -#define IOCON_SSEL_1V8 (0x1 << IOCON_PIO_SSEL_SHIFT) /*!< 1V8 signaling in I2C mode */ -#endif - -#if defined(IOCON_PIO_ECS_SHIFT) -#define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */ -#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */ -#endif - -#if defined(IOCON_PIO_S_MODE_SHIFT) -#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ -#define IOCON_S_MODE_1CLK \ - (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_2CLK \ - (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_3CLK \ - (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ -#endif - -#if defined(IOCON_PIO_CLK_DIV_SHIFT) -#define IOCON_CLKDIV(div) \ - ((div) \ - << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ -#endif - -#if defined(__cplusplus) -extern "C" { -#endif - -#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) -/** - * @brief Sets I/O Control pin mux - * @param base : The base of IOCON peripheral on the chip - * @param ionumber : GPIO number to mux - * @param modefunc : OR'ed values of type IOCON_* - * @return Nothing - */ -__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc) -{ - base->PIO[ionumber] = modefunc; -} -#else -/** - * @brief Sets I/O Control pin mux - * @param base : The base of IOCON peripheral on the chip - * @param port : GPIO port to mux - * @param pin : GPIO pin to mux - * @param modefunc : OR'ed values of type IOCON_* - * @return Nothing - */ -__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc) -{ - base->PIO[port][pin] = modefunc; -} -#endif - -/** - * @brief Set all I/O Control pin muxing - * @param base : The base of IOCON peripheral on the chip - * @param pinArray : Pointer to array of pin mux selections - * @param arrayLength : Number of entries in pinArray - * @return Nothing - */ -__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength) -{ - uint32_t i; - - for (i = 0; i < arrayLength; i++) - { -#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) - IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc); -#else - IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc); -#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */ - } -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_IOCON_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.c deleted file mode 100644 index 7835e6fc454..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.c +++ /dev/null @@ -1,612 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_lpadc.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpadc" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for LPADC module. - * - * @param base LPADC peripheral base address - */ -static uint32_t LPADC_GetInstance(ADC_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to LPADC bases for each instance. */ -static ADC_Type *const s_lpadcBases[] = ADC_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to LPADC clocks for each instance. */ -static const clock_ip_name_t s_lpadcClocks[] = LPADC_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t LPADC_GetInstance(ADC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_lpadcBases); instance++) - { - if (s_lpadcBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_lpadcBases)); - - return instance; -} - -/*! - * brief Initializes the LPADC module. - * - * param base LPADC peripheral base address. - * param config Pointer to configuration structure. See "lpadc_config_t". - */ -void LPADC_Init(ADC_Type *base, const lpadc_config_t *config) -{ - /* Check if the pointer is available. */ - assert(config != NULL); - - uint32_t tmp32 = 0U; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock for LPADC instance. */ - (void)CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the module. */ - LPADC_DoResetConfig(base); -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - LPADC_DoResetFIFO0(base); - LPADC_DoResetFIFO1(base); -#else - LPADC_DoResetFIFO(base); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - - /* Disable the module before setting configuration. */ - LPADC_Enable(base, false); - - /* Configure the module generally. */ - if (config->enableInDozeMode) - { - base->CTRL &= ~ADC_CTRL_DOZEN_MASK; - } - else - { - base->CTRL |= ADC_CTRL_DOZEN_MASK; - } - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS - /* Set calibration average mode. */ - base->CTRL |= ADC_CTRL_CAL_AVGS(config->conversionAverageMode); -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - -/* ADCx_CFG. */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - if (config->enableInternalClock) - { - tmp32 |= ADC_CFG_ADCKEN_MASK; - } -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - if (config->enableVref1LowVoltage) - { - tmp32 |= ADC_CFG_VREF1RNG_MASK; - } -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - if (config->enableAnalogPreliminary) - { - tmp32 |= ADC_CFG_PWREN_MASK; - } - tmp32 |= ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */ - | ADC_CFG_REFSEL(config->referenceVoltageSource) /* Reference voltage. */ - | ADC_CFG_PWRSEL(config->powerLevelMode) /* Power configuration. */ - | ADC_CFG_TPRICTRL(config->triggerPriorityPolicy); /* Trigger priority policy. */ - base->CFG = tmp32; - - /* ADCx_PAUSE. */ - if (config->enableConvPause) - { - base->PAUSE = ADC_PAUSE_PAUSEEN_MASK | ADC_PAUSE_PAUSEDLY(config->convPauseDelay); - } - else - { - base->PAUSE = 0U; - } - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - /* ADCx_FCTRL0. */ - base->FCTRL[0] = ADC_FCTRL_FWMARK(config->FIFO0Watermark); - /* ADCx_FCTRL1. */ - base->FCTRL[1] = ADC_FCTRL_FWMARK(config->FIFO1Watermark); -#else - /* ADCx_FCTRL. */ - base->FCTRL = ADC_FCTRL_FWMARK(config->FIFOWatermark); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - - /* Enable the module after setting configuration. */ - LPADC_Enable(base, true); -} - -/*! - * brief Gets an available pre-defined settings for initial configuration. - * - * This function initializes the converter configuration structure with an available settings. The default values are: - * code - * config->enableInDozeMode = true; - * config->conversionAverageMode = kLPADC_ConversionAverage1; - * config->enableAnalogPreliminary = false; - * config->powerUpDelay = 0x80; - * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - * config->powerLevelMode = kLPADC_PowerLevelAlt1; - * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; - * config->enableConvPause = false; - * config->convPauseDelay = 0U; - * config->FIFO0Watermark = 0U; - * config->FIFO1Watermark = 0U; - * config->FIFOWatermark = 0U; - * endcode - * param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConfig(lpadc_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - config->enableInternalClock = false; -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - config->enableVref1LowVoltage = false; -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - config->enableInDozeMode = true; -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS - /* Set calibration average mode. */ - config->conversionAverageMode = kLPADC_ConversionAverage1; -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - config->enableAnalogPreliminary = false; - config->powerUpDelay = 0x80; - config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - config->powerLevelMode = kLPADC_PowerLevelAlt1; - config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; - config->enableConvPause = false; - config->convPauseDelay = 0U; -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - config->FIFO0Watermark = 0U; - config->FIFO1Watermark = 0U; -#else - config->FIFOWatermark = 0U; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ -} - -/*! - * brief De-initializes the LPADC module. - * - * param base LPADC peripheral base address. - */ -void LPADC_Deinit(ADC_Type *base) -{ - /* Disable the module. */ - LPADC_Enable(base, false); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the clock. */ - (void)CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * brief Get the result in conversion FIFOn. - * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. - * param index Result FIFO index. - * - * return Status whether FIFOn entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index) -{ - assert(result != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - tmp32 = base->RESFIFO[index]; - - if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) - { - return false; /* FIFO is empty. Discard any read from RESFIFO. */ - } - - result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; - result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; - result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; - result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); - - return true; -} -#else -/*! - * brief Get the result in conversion FIFO. - * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFO. - * - * return Status whether FIFO entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result) -{ - assert(result != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - tmp32 = base->RESFIFO; - - if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) - { - return false; /* FIFO is empty. Discard any read from RESFIFO. */ - } - - result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; - result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; - result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; - result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); - - return true; -} -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * brief Configure the conversion trigger source. - * - * Each programmable trigger can launch the conversion command in command buffer. - * - * param base LPADC peripheral base address. - * param triggerId ID for each trigger. Typically, the available value range is from 0. - * param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. - */ -void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config) -{ - assert(triggerId < ADC_TCTRL_COUNT); /* Check if the triggerId is available in this device. */ - assert(config != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - tmp32 = ADC_TCTRL_TCMD(config->targetCommandId) /* Trigger command select. */ - | ADC_TCTRL_TDLY(config->delayPower) /* Trigger delay select. */ - | ADC_TCTRL_TPRI(config->priority) /* Trigger priority setting. */ -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - | ADC_TCTRL_FIFO_SEL_A(config->channelAFIFOSelect) -#if !(defined(FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) && FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) - | ADC_TCTRL_FIFO_SEL_B(config->channelBFIFOSelect) -#endif /* FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - ; - if (config->enableHardwareTrigger) - { - tmp32 |= ADC_TCTRL_HTEN_MASK; - } - - base->TCTRL[triggerId] = tmp32; -} - -/*! - * brief Gets an available pre-defined settings for trigger's configuration. - * - * This function initializes the trigger's configuration structure with an available settings. The default values are: - * code - * config->commandIdSource = 0U; - * config->loopCountIndex = 0U; - * config->triggerIdSource = 0U; - * config->enableHardwareTrigger = false; - * config->channelAFIFOSelect = 0U; - * config->channelBFIFOSelect = 0U; - * endcode - * param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config) -{ - assert(config != NULL); /* Check if the input pointer is available. */ - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->targetCommandId = 0U; - config->delayPower = 0U; - config->priority = 0U; -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - config->channelAFIFOSelect = 0U; - config->channelBFIFOSelect = 0U; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - config->enableHardwareTrigger = false; -} - -/*! - * brief Configure conversion command. - * - * param base LPADC peripheral base address. - * param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. - * param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. - */ -void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config) -{ - assert(commandId < (ADC_CMDL_COUNT + 1U)); /* Check if the commandId is available on this device. */ - assert(config != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32 = 0; - - commandId--; /* The available command number are 1-15, while the index of register group are 0-14. */ - - /* ADCx_CMDL. */ - tmp32 = ADC_CMDL_ADCH(config->channelNumber); /* Channel number. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - tmp32 |= ADC_CMDL_CSCALE(config->sampleScaleMode); /* Full/Part scale input voltage. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE - tmp32 |= ADC_CMDL_CTYPE(config->sampleChannelMode); -#else - switch (config->sampleChannelMode) /* Sample input. */ - { - case kLPADC_SampleChannelSingleEndSideB: - tmp32 |= ADC_CMDL_ABSEL_MASK; - break; -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF - case kLPADC_SampleChannelDiffBothSideAB: - tmp32 |= ADC_CMDL_DIFF_MASK; - break; - case kLPADC_SampleChannelDiffBothSideBA: - tmp32 |= ADC_CMDL_ABSEL_MASK | ADC_CMDL_DIFF_MASK; - break; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_DIFF */ - default: /* kLPADC_SampleChannelSingleEndSideA. */ - break; - } -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - tmp32 |= ADC_CMDL_MODE(config->conversionResolutionMode); -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ - base->CMD[commandId].CMDL = tmp32; - - /* ADCx_CMDH. */ - tmp32 = ADC_CMDH_NEXT(config->chainedNextCommandNumber) /* Next Command Select. */ - | ADC_CMDH_LOOP(config->loopCount) /* Loop Count Select. */ - | ADC_CMDH_AVGS(config->hardwareAverageMode) /* Hardware Average Select. */ - | ADC_CMDH_STS(config->sampleTimeMode) /* Sample Time Select. */ - | ADC_CMDH_CMPEN(config->hardwareCompareMode); /* Hardware compare enable. */ -#if (defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) - if (config->enableWaitTrigger) - { - tmp32 |= ADC_CMDH_WAIT_TRIG_MASK; /* Wait trigger enable. */ - } -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ - - if (config->enableAutoChannelIncrement) - { - tmp32 |= ADC_CMDH_LWI_MASK; - } - base->CMD[commandId].CMDH = tmp32; - - /* Hardware compare settings. - * Not all Command Buffers have an associated Compare Value register. The compare function is only available on - * Command Buffers that have a corresponding Compare Value register. - */ - if (kLPADC_HardwareCompareDisabled != config->hardwareCompareMode) - { - /* Check if the hardware compare feature is available for indicated command buffer. */ - assert(commandId < ADC_CV_COUNT); - - /* Set CV register. */ - base->CV[commandId] = ADC_CV_CVH(config->hardwareCompareValueHigh) /* Compare value high. */ - | ADC_CV_CVL(config->hardwareCompareValueLow); /* Compare value low. */ - } -} - -/*! - * brief Gets an available pre-defined settings for conversion command's configuration. - * - * This function initializes the conversion command's configuration structure with an available settings. The default - * values are: - * code - * config->sampleScaleMode = kLPADC_SampleFullScale; - * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; - * config->channelNumber = 0U; - * config->chainedNextCmdNumber = 0U; - * config->enableAutoChannelIncrement = false; - * config->loopCount = 0U; - * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - * config->sampleTimeMode = kLPADC_SampleTimeADCK3; - * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - * config->hardwareCompareValueHigh = 0U; - * config->hardwareCompareValueLow = 0U; - * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; - * config->enableWaitTrigger = false; - * endcode - * param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config) -{ - assert(config != NULL); /* Check if the input pointer is available. */ - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - config->sampleScaleMode = kLPADC_SampleFullScale; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ - config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; - config->channelNumber = 0U; - config->chainedNextCommandNumber = 0U; /* No next command defined. */ - config->enableAutoChannelIncrement = false; - config->loopCount = 0U; - config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - config->sampleTimeMode = kLPADC_SampleTimeADCK3; - config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - config->hardwareCompareValueHigh = 0U; /* No used. */ - config->hardwareCompareValueLow = 0U; /* No used. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG - config->enableWaitTrigger = false; -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ -} - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS -/*! - * brief Enable the calibration function. - * - * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes - * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value - * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- - * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the - * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. - * - * param base LPADC peripheral base address. - * param enable switcher to the calibration function. - */ -void LPADC_EnableCalibration(ADC_Type *base, bool enable) -{ - LPADC_Enable(base, false); - if (enable) - { - base->CFG |= ADC_CFG_CALOFS_MASK; - } - else - { - base->CFG &= ~ADC_CFG_CALOFS_MASK; - } - LPADC_Enable(base, true); -} - -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! - * brief Do auto calibration. - * - * Calibration function should be executed before using converter in application. It used the software trigger and a - * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API - * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) - * -LPADC_SetConvTriggerConfig(...) - * - * param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base) -{ - assert(0u == LPADC_GetConvResultCount(base)); - - uint32_t mLpadcCMDL; - uint32_t mLpadcCMDH; - uint32_t mLpadcTrigger; - lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct; - lpadc_conv_command_config_t mLpadcCommandConfigStruct; - lpadc_conv_result_t mLpadcResultConfigStruct; - - /* Enable the calibration function. */ - LPADC_EnableCalibration(base, true); - - /* Keep the CMD and TRG state here and restore it later if the calibration completes.*/ - mLpadcCMDL = base->CMD[0].CMDL; /* CMD1L. */ - mLpadcCMDH = base->CMD[0].CMDH; /* CMD1H. */ - mLpadcTrigger = base->TCTRL[0]; /* Trigger0. */ - - /* Set trigger0 configuration - for software trigger. */ - LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct); - mLpadcTriggerConfigStruct.targetCommandId = 1U; /* CMD1 is executed. */ - LPADC_SetConvTriggerConfig(base, 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */ - - /* Set conversion CMD configuration. */ - LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct); - mLpadcCommandConfigStruct.hardwareAverageMode = kLPADC_HardwareAverageCount128; - LPADC_SetConvCommandConfig(base, 1U, &mLpadcCommandConfigStruct); /* Set CMD1 configuration. */ - - /* Do calibration. */ - LPADC_DoSoftwareTrigger(base, 1U); /* 1U is trigger0 mask. */ - while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct)) - { - } - /* The valid bits of data are bits 14:3 in the RESFIFO register. */ - LPADC_SetOffsetValue(base, (uint32_t)(mLpadcResultConfigStruct.convValue) >> 3UL); - /* Disable the calibration function. */ - LPADC_EnableCalibration(base, false); - - /* restore CMD and TRG registers. */ - base->CMD[0].CMDL = mLpadcCMDL; /* CMD1L. */ - base->CMD[0].CMDH = mLpadcCMDH; /* CMD1H. */ - base->TCTRL[0] = mLpadcTrigger; /* Trigger0. */ -} -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS -/*! - * brief Do offset calibration. - * - * param base LPADC peripheral base address. - */ -void LPADC_DoOffsetCalibration(ADC_Type *base) -{ - LPADC_EnableOffsetCalibration(base, true); - while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) - { - } -} - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ -/*! - * brief Do auto calibration. - * - * param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base) -{ - assert((0u == LPADC_GetConvResultCount(base, 0)) && (0u == LPADC_GetConvResultCount(base, 1))); - - uint32_t GCCa; - uint32_t GCCb; - uint32_t GCRa; - uint32_t GCRb; - - /* Request gain calibration. */ - base->CTRL |= ADC_CTRL_CAL_REQ_MASK; - while ((ADC_GCC_RDY_MASK != (base->GCC[0] & ADC_GCC_RDY_MASK)) || - (ADC_GCC_RDY_MASK != (base->GCC[1] & ADC_GCC_RDY_MASK))) - { - } - - /* Calculate gain offset. */ - GCCa = (base->GCC[0] & ADC_GCC_GAIN_CAL_MASK); - GCCb = (base->GCC[1] & ADC_GCC_GAIN_CAL_MASK); - GCRa = (uint16_t)((GCCa << 16U) / - (0x1FFFFU - GCCa)); /* Gain_CalA = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[0])) - 1. */ - GCRb = (uint16_t)((GCCb << 16U) / - (0x1FFFFU - GCCb)); /* Gain_CalB = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[1])) - 1. */ - base->GCR[0] = ADC_GCR_GCALR(GCRa); - base->GCR[1] = ADC_GCR_GCALR(GCRb); - - /* Indicate the values are valid. */ - base->GCR[0] |= ADC_GCR_RDY_MASK; - base->GCR[1] |= ADC_GCR_RDY_MASK; - - while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) - { - } -} -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.h deleted file mode 100644 index d3e5a9ec30a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.h +++ /dev/null @@ -1,964 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_LPADC_H_ -#define _FSL_LPADC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpadc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPADC driver version 2.5.1. */ -#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 5, 1)) -/*@}*/ - -/*! - * @brief Define the MACRO function to get command status from status value. - * - * The statusVal is the return value from LPADC_GetStatusFlags(). - */ -#define LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal) ((statusVal & ADC_STAT_CMDACT_MASK) >> ADC_STAT_CMDACT_SHIFT) - -/*! - * @brief Define the MACRO function to get trigger status from status value. - * - * The statusVal is the return value from LPADC_GetStatusFlags(). - */ -#define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT) - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Define hardware flags of the module. - */ -enum _lpadc_status_flags -{ - kLPADC_ResultFIFO0OverflowFlag = ADC_STAT_FOF0_MASK, /*!< Indicates that more data has been written to the Result - FIFO 0 than it can hold. */ - kLPADC_ResultFIFO0ReadyFlag = ADC_STAT_RDY0_MASK, /*!< Indicates when the number of valid datawords in the result - FIFO 0 is greater than the setting watermark level. */ - kLPADC_ResultFIFO1OverflowFlag = ADC_STAT_FOF1_MASK, /*!< Indicates that more data has been written to the Result - FIFO 1 than it can hold. */ - kLPADC_ResultFIFO1ReadyFlag = ADC_STAT_RDY1_MASK, /*!< Indicates when the number of valid datawords in the result - FIFO 1 is greater than the setting watermark level. */ -}; - -/*! - * @brief Define interrupt switchers of the module. - */ -enum _lpadc_interrupt_enable -{ - kLPADC_ResultFIFO0OverflowInterruptEnable = ADC_IE_FOFIE0_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF0 flag is asserted. */ - kLPADC_FIFO0WatermarkInterruptEnable = ADC_IE_FWMIE0_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY0 flag is asserted. */ - kLPADC_ResultFIFO1OverflowInterruptEnable = ADC_IE_FOFIE1_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF1 flag is asserted. */ - kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY1 flag is asserted. */ -#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) - kLPADC_TriggerExceptionInterruptEnable = ADC_IE_TEXC_IE_MASK, /*!< Configures ADC to generate trigger exception - interrupt. */ - kLPADC_Trigger0CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 0UL), /*!< Configures ADC to generate interrupt - when trigger 0 completion. */ - kLPADC_Trigger1CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 1UL), /*!< Configures ADC to generate interrupt - when trigger 1 completion. */ - kLPADC_Trigger2CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 2UL), /*!< Configures ADC to generate interrupt - when trigger 2 completion. */ - kLPADC_Trigger3CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 3UL), /*!< Configures ADC to generate interrupt - when trigger 3 completion. */ - kLPADC_Trigger4CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 4UL), /*!< Configures ADC to generate interrupt - when trigger 4 completion. */ - kLPADC_Trigger5CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 5UL), /*!< Configures ADC to generate interrupt - when trigger 5 completion. */ - kLPADC_Trigger6CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 6UL), /*!< Configures ADC to generate interrupt - when trigger 6 completion. */ - kLPADC_Trigger7CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 7UL), /*!< Configures ADC to generate interrupt - when trigger 7 completion. */ - kLPADC_Trigger8CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 8UL), /*!< Configures ADC to generate interrupt - when trigger 8 completion. */ - kLPADC_Trigger9CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 9UL), /*!< Configures ADC to generate interrupt - when trigger 9 completion. */ - kLPADC_Trigger10CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 10UL), /*!< Configures ADC to generate interrupt - when trigger 10 completion. */ - kLPADC_Trigger11CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 11UL), /*!< Configures ADC to generate interrupt - when trigger 11 completion. */ - kLPADC_Trigger12CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 12UL), /*!< Configures ADC to generate interrupt - when trigger 12 completion. */ - kLPADC_Trigger13CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 13UL), /*!< Configures ADC to generate interrupt - when trigger 13 completion. */ - kLPADC_Trigger14CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 14UL), /*!< Configures ADC to generate interrupt - when trigger 14 completion. */ - kLPADC_Trigger15CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 15UL), /*!< Configures ADC to generate interrupt - when trigger 15 completion. */ -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ -}; -#else -/*! - * @brief Define hardware flags of the module. - */ -enum _lpadc_status_flags -{ - kLPADC_ResultFIFOOverflowFlag = ADC_STAT_FOF_MASK, /*!< Indicates that more data has been written to the Result FIFO - than it can hold. */ - kLPADC_ResultFIFOReadyFlag = ADC_STAT_RDY_MASK, /*!< Indicates when the number of valid datawords in the result FIFO - is greater than the setting watermark level. */ -}; - -/*! - * @brief Define interrupt switchers of the module. - */ -enum _lpadc_interrupt_enable -{ - kLPADC_ResultFIFOOverflowInterruptEnable = ADC_IE_FOFIE_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF flag is asserted. */ - kLPADC_FIFOWatermarkInterruptEnable = ADC_IE_FWMIE_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY flag is asserted. */ -}; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) -/*! - * @brief The enumerator of lpadc trigger status flags, including interrupted flags and completed flags. - */ -enum _lpadc_trigger_status_flags -{ - kLPADC_Trigger0InterruptedFlag = 1UL << 0UL, /*!< Trigger 0 is interrupted by a high priority exception. */ - kLPADC_Trigger1InterruptedFlag = 1UL << 1UL, /*!< Trigger 1 is interrupted by a high priority exception. */ - kLPADC_Trigger2InterruptedFlag = 1UL << 2UL, /*!< Trigger 2 is interrupted by a high priority exception. */ - kLPADC_Trigger3InterruptedFlag = 1UL << 3UL, /*!< Trigger 3 is interrupted by a high priority exception. */ - kLPADC_Trigger4InterruptedFlag = 1UL << 4UL, /*!< Trigger 4 is interrupted by a high priority exception. */ - kLPADC_Trigger5InterruptedFlag = 1UL << 5UL, /*!< Trigger 5 is interrupted by a high priority exception. */ - kLPADC_Trigger6InterruptedFlag = 1UL << 6UL, /*!< Trigger 6 is interrupted by a high priority exception. */ - kLPADC_Trigger7InterruptedFlag = 1UL << 7UL, /*!< Trigger 7 is interrupted by a high priority exception. */ - kLPADC_Trigger8InterruptedFlag = 1UL << 8UL, /*!< Trigger 8 is interrupted by a high priority exception. */ - kLPADC_Trigger9InterruptedFlag = 1UL << 9UL, /*!< Trigger 9 is interrupted by a high priority exception. */ - kLPADC_Trigger10InterruptedFlag = 1UL << 10UL, /*!< Trigger 10 is interrupted by a high priority exception. */ - kLPADC_Trigger11InterruptedFlag = 1UL << 11UL, /*!< Trigger 11 is interrupted by a high priority exception. */ - kLPADC_Trigger12InterruptedFlag = 1UL << 12UL, /*!< Trigger 12 is interrupted by a high priority exception. */ - kLPADC_Trigger13InterruptedFlag = 1UL << 13UL, /*!< Trigger 13 is interrupted by a high priority exception. */ - kLPADC_Trigger14InterruptedFlag = 1UL << 14UL, /*!< Trigger 14 is interrupted by a high priority exception. */ - kLPADC_Trigger15InterruptedFlag = 1UL << 15UL, /*!< Trigger 15 is interrupted by a high priority exception. */ - - kLPADC_Trigger0CompletedFlag = 1UL << 16UL, /*!< Trigger 0 is completed and - trigger 0 has enabled completion interrupts. */ - kLPADC_Trigger1CompletedFlag = 1UL << 17UL, /*!< Trigger 1 is completed and - trigger 1 has enabled completion interrupts. */ - kLPADC_Trigger2CompletedFlag = 1UL << 18UL, /*!< Trigger 2 is completed and - trigger 2 has enabled completion interrupts. */ - kLPADC_Trigger3CompletedFlag = 1UL << 19UL, /*!< Trigger 3 is completed and - trigger 3 has enabled completion interrupts. */ - kLPADC_Trigger4CompletedFlag = 1UL << 20UL, /*!< Trigger 4 is completed and - trigger 4 has enabled completion interrupts. */ - kLPADC_Trigger5CompletedFlag = 1UL << 21UL, /*!< Trigger 5 is completed and - trigger 5 has enabled completion interrupts. */ - kLPADC_Trigger6CompletedFlag = 1UL << 22UL, /*!< Trigger 6 is completed and - trigger 6 has enabled completion interrupts. */ - kLPADC_Trigger7CompletedFlag = 1UL << 23UL, /*!< Trigger 7 is completed and - trigger 7 has enabled completion interrupts. */ - kLPADC_Trigger8CompletedFlag = 1UL << 24UL, /*!< Trigger 8 is completed and - trigger 8 has enabled completion interrupts. */ - kLPADC_Trigger9CompletedFlag = 1UL << 25UL, /*!< Trigger 9 is completed and - trigger 9 has enabled completion interrupts. */ - kLPADC_Trigger10CompletedFlag = 1UL << 26UL, /*!< Trigger 10 is completed and - trigger 10 has enabled completion interrupts. */ - kLPADC_Trigger11CompletedFlag = 1UL << 27UL, /*!< Trigger 11 is completed and - trigger 11 has enabled completion interrupts. */ - kLPADC_Trigger12CompletedFlag = 1UL << 28UL, /*!< Trigger 12 is completed and - trigger 12 has enabled completion interrupts. */ - kLPADC_Trigger13CompletedFlag = 1UL << 29UL, /*!< Trigger 13 is completed and - trigger 13 has enabled completion interrupts. */ - kLPADC_Trigger14CompletedFlag = 1UL << 30UL, /*!< Trigger 14 is completed and - trigger 14 has enabled completion interrupts. */ - kLPADC_Trigger15CompletedFlag = 1UL << 31UL, /*!< Trigger 15 is completed and - trigger 15 has enabled completion interrupts. */ -}; -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ - -/*! - * @brief Define enumeration of sample scale mode. - * - * The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum - * possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the - * reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows - * conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode. - */ -typedef enum _lpadc_sample_scale_mode -{ - kLPADC_SamplePartScale = 0U, /*!< Use divided input voltage signal. (Factor of 30/64). */ - kLPADC_SampleFullScale = 1U, /*!< Full scale (Factor of 1). */ -} lpadc_sample_scale_mode_t; - -/*! - * @brief Define enumeration of channel sample mode. - * - * The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B. - */ -typedef enum _lpadc_sample_channel_mode -{ - kLPADC_SampleChannelSingleEndSideA = 0U, /*!< Single end mode, using side A. */ - kLPADC_SampleChannelSingleEndSideB = 1U, /*!< Single end mode, using side B. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF - kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minus side. */ - kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minus side. */ -#elif defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE - kLPADC_SampleChannelDiffBothSide = 2U, /*!< Differential mode, using A and B. */ - kLPADC_SampleChannelDualSingleEndBothSide = - 3U, /*!< Dual-Single-Ended Mode. Both A side and B side channels are converted independently. */ -#endif -} lpadc_sample_channel_mode_t; - -/*! - * @brief Define enumeration of hardware average selection. - * - * It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to - * capture temporary results while the averaging iterations are executed. - */ -typedef enum _lpadc_hardware_average_mode -{ - kLPADC_HardwareAverageCount1 = 0U, /*!< Single conversion. */ - kLPADC_HardwareAverageCount2 = 1U, /*!< 2 conversions averaged. */ - kLPADC_HardwareAverageCount4 = 2U, /*!< 4 conversions averaged. */ - kLPADC_HardwareAverageCount8 = 3U, /*!< 8 conversions averaged. */ - kLPADC_HardwareAverageCount16 = 4U, /*!< 16 conversions averaged. */ - kLPADC_HardwareAverageCount32 = 5U, /*!< 32 conversions averaged. */ - kLPADC_HardwareAverageCount64 = 6U, /*!< 64 conversions averaged. */ - kLPADC_HardwareAverageCount128 = 7U, /*!< 128 conversions averaged. */ -} lpadc_hardware_average_mode_t; - -/*! - * @brief Define enumeration of sample time selection. - * - * The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher - * impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption - * when command looping and sequencing is configured and high conversion rates are not required. - */ -typedef enum _lpadc_sample_time_mode -{ - kLPADC_SampleTimeADCK3 = 0U, /*!< 3 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK5 = 1U, /*!< 5 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK7 = 2U, /*!< 7 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK11 = 3U, /*!< 11 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK19 = 4U, /*!< 19 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK35 = 5U, /*!< 35 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK67 = 6U, /*!< 69 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK131 = 7U, /*!< 131 ADCK cycles total sample time. */ -} lpadc_sample_time_mode_t; - -/*! - * @brief Define enumeration of hardware compare mode. - * - * After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting - * guides operation of the automatic compare function to optionally only store when the compare operation is true. - * When compare is enabled, the conversion result is compared to the compare values. - */ -typedef enum _lpadc_hardware_compare_mode -{ - kLPADC_HardwareCompareDisabled = 0U, /*!< Compare disabled. */ - kLPADC_HardwareCompareStoreOnTrue = 2U, /*!< Compare enabled. Store on true. */ - kLPADC_HardwareCompareRepeatUntilTrue = 3U, /*!< Compare enabled. Repeat channel acquisition until true. */ -} lpadc_hardware_compare_mode_t; - -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE -/*! - * @brief Define enumeration of conversion resolution mode. - * - * Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to - * #lpadc_sample_channel_mode_t - */ -typedef enum _lpadc_conversion_resolution_mode -{ - kLPADC_ConversionResolutionStandard = 0U, /*!< Standard resolution. Single-ended 12-bit conversion, Differential - 13-bit conversion with 2’s complement output. */ - kLPADC_ConversionResolutionHigh = 1U, /*!< High resolution. Single-ended 16-bit conversion; Differential 16-bit - conversion with 2’s complement output. */ -} lpadc_conversion_resolution_mode_t; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS -/*! - * @brief Define enumeration of conversion averages mode. - * - * Configure the converion average number for auto-calibration. - */ -typedef enum _lpadc_conversion_average_mode -{ - kLPADC_ConversionAverage1 = 0U, /*!< Single conversion. */ - kLPADC_ConversionAverage2 = 1U, /*!< 2 conversions averaged. */ - kLPADC_ConversionAverage4 = 2U, /*!< 4 conversions averaged. */ - kLPADC_ConversionAverage8 = 3U, /*!< 8 conversions averaged. */ - kLPADC_ConversionAverage16 = 4U, /*!< 16 conversions averaged. */ - kLPADC_ConversionAverage32 = 5U, /*!< 32 conversions averaged. */ - kLPADC_ConversionAverage64 = 6U, /*!< 64 conversions averaged. */ - kLPADC_ConversionAverage128 = 7U, /*!< 128 conversions averaged. */ -} lpadc_conversion_average_mode_t; -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - -/*! - * @brief Define enumeration of reference voltage source. - * - * For detail information, need to check the SoC's specification. - */ -typedef enum _lpadc_reference_voltage_mode -{ - kLPADC_ReferenceVoltageAlt1 = 0U, /*!< Option 1 setting. */ - kLPADC_ReferenceVoltageAlt2 = 1U, /*!< Option 2 setting. */ - kLPADC_ReferenceVoltageAlt3 = 2U, /*!< Option 3 setting. */ -} lpadc_reference_voltage_source_t; - -/*! - * @brief Define enumeration of power configuration. - * - * Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be - * possible. Refer to the device data sheet for power and performance capabilities for each setting. - */ -typedef enum _lpadc_power_level_mode -{ - kLPADC_PowerLevelAlt1 = 0U, /*!< Lowest power setting. */ - kLPADC_PowerLevelAlt2 = 1U, /*!< Next lowest power setting. */ - kLPADC_PowerLevelAlt3 = 2U, /*!< ... */ - kLPADC_PowerLevelAlt4 = 3U, /*!< Highest power setting. */ -} lpadc_power_level_mode_t; - -/*! - * @brief Define enumeration of trigger priority policy. - * - * This selection controls how higher priority triggers are handled. - */ -typedef enum _lpadc_trigger_priority_policy -{ - kLPADC_TriggerPriorityPreemptImmediately = 0U, /*!< If a higher priority trigger is detected during command - processing, the current conversion is aborted and the new - command specified by the trigger is started. */ - kLPADC_TriggerPriorityPreemptSoftly = 1U, /*!< If a higher priority trigger is received during command processing, - the current conversion is completed (including averaging iterations - and compare function if enabled) and stored to the result FIFO - before the higher priority trigger/command is initiated. */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY) && FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY - kLPADC_TriggerPriorityPreemptSubsequently = 2U, /*!< If a higher priority trigger is received during command - processing, the current command will be completed (averaging, - looping, compare) before servicing the higher priority trigger. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY */ -} lpadc_trigger_priority_policy_t; - -/*! - * @brief LPADC global configuration. - * - * This structure would used to keep the settings for initialization. - */ -typedef struct -{ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock - selection logic at the chip level and is optionally used for the ADC clock source. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - bool enableVref1LowVoltage; /*!< If voltage reference option1 input is below 1.8V, it should be "true". - If voltage reference option1 input is above 1.8V, it should be "false". */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - bool enableInDozeMode; /*!< Control system transition to Stop and Wait power modes while ADC is converting. When - enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the - ADC will wait for the current averaging iteration/FIFO storage to complete before - acknowledging stop or wait mode entry. */ -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS - lpadc_conversion_average_mode_t conversionAverageMode; /*!< Auto-Calibration Averages. */ -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - bool enableAnalogPreliminary; /*!< ADC analog circuits are pre-enabled and ready to execute conversions without - startup delays(at the cost of higher DC current consumption). */ - uint32_t powerUpDelay; /*!< When the analog circuits are not pre-enabled, the ADC analog circuits are only powered - while the ADC is active and there is a counted delay defined by this field after an - initial trigger transitions the ADC from its Idle state to allow time for the analog - circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must - result in a longer delay than the analog startup time. */ - lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for - conversions.*/ - lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */ - lpadc_trigger_priority_policy_t triggerPriorityPolicy; /*!< Control how higher priority triggers are handled, see to - lpadc_trigger_priority_policy_t. */ - bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during - command execution sequencing between LOOP iterations, between commands in a sequence, and - between conversions when command is executing in "Compare Until True" configuration. */ - uint32_t convPauseDelay; /*!< Controls the duration of pausing during command execution sequencing. The pause delay - is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing - function is enabled. The available value range is in 9-bit. */ -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - /* for FIFO0. */ - uint32_t FIFO0Watermark; /*!< FIFO0Watermark is a programmable threshold setting. When the number of datawords - stored in the ADC Result FIFO0 is greater than the value in this field, the ready flag - would be asserted to indicate stored data has reached the programmable threshold. */ - /* for FIFO1. */ - uint32_t FIFO1Watermark; /*!< FIFO1Watermark is a programmable threshold setting. When the number of datawords - stored in the ADC Result FIFO1 is greater than the value in this field, the ready flag - would be asserted to indicate stored data has reached the programmable threshold. */ -#else - /* for FIFO. */ - uint32_t FIFOWatermark; /*!< FIFOWatermark is a programmable threshold setting. When the number of datawords stored - in the ADC Result FIFO is greater than the value in this field, the ready flag would be - asserted to indicate stored data has reached the programmable threshold. */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ -} lpadc_config_t; - -/*! - * @brief Define structure to keep the configuration for conversion command. - */ -typedef struct -{ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ - lpadc_sample_channel_mode_t sampleChannelMode; /*!< Channel sample mode. */ - uint32_t channelNumber; /*!< Channel number, select the channel or channel pair. */ - uint32_t chainedNextCommandNumber; /*!< Selects the next command to be executed after this command completes. - 1-15 is available, 0 is to terminate the chain after this command. */ - bool enableAutoChannelIncrement; /*!< Loop with increment: when disabled, the "loopCount" field selects the number - of times the selected channel is converted consecutively; when enabled, the - "loopCount" field defines how many consecutive channels are converted as part - of the command execution. */ - uint32_t loopCount; /*!< Selects how many times this command executes before finish and transition to the next - command or Idle state. Command executes LOOP+1 times. 0-15 is available. */ - lpadc_hardware_average_mode_t hardwareAverageMode; /*!< Hardware average selection. */ - lpadc_sample_time_mode_t sampleTimeMode; /*!< Sample time selection. */ - - lpadc_hardware_compare_mode_t hardwareCompareMode; /*!< Hardware compare selection. */ - uint32_t hardwareCompareValueHigh; /*!< Compare Value High. The available value range is in 16-bit. */ - uint32_t hardwareCompareValueLow; /*!< Compare Value Low. The available value range is in 16-bit. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - lpadc_conversion_resolution_mode_t conversionResolutionMode; /*!< Conversion resolution mode. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG - bool enableWaitTrigger; /*!< Wait for trigger assertion before execution: when disabled, this command will be - automatically executed; when enabled, the active trigger must be asserted again before - executing this command. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ -} lpadc_conv_command_config_t; - -/*! - * @brief Define structure to keep the configuration for conversion trigger. - */ -typedef struct -{ - uint32_t targetCommandId; /*!< Select the command from command buffer to execute upon detect of the associated - trigger event. */ - uint32_t delayPower; /*!< Select the trigger delay duration to wait at the start of servicing a trigger event. - When this field is clear, then no delay is incurred. When this field is set to a non-zero - value, the duration for the delay is 2^delayPower ADCK cycles. The available value range - is 4-bit. */ - uint32_t priority; /*!< Sets the priority of the associated trigger source. If two or more triggers have the same - priority level setting, the lower order trigger event has the higher priority. The lower - value for this field is for the higher priority, the available value range is 1-bit. */ -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - uint8_t channelAFIFOSelect; /* SAR Result Destination For Channel A. */ - uint8_t channelBFIFOSelect; /* SAR Result Destination For Channel B. */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - bool enableHardwareTrigger; /*!< Enable hardware trigger source to initiate conversion on the rising edge of the - input trigger source or not. THe software trigger is always available. */ -} lpadc_conv_trigger_config_t; - -/*! - * @brief Define the structure to keep the conversion result. - */ -typedef struct -{ - uint32_t commandIdSource; /*!< Indicate the command buffer being executed that generated this result. */ - uint32_t loopCountIndex; /*!< Indicate the loop count value during command execution that generated this result. */ - uint32_t triggerIdSource; /*!< Indicate the trigger source that initiated a conversion and generated this result. */ - uint16_t convValue; /*!< Data result. */ -} lpadc_conv_result_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ -/*! - * @name Initialization & de-initialization. - * @{ - */ - -/*! - * @brief Initializes the LPADC module. - * - * @param base LPADC peripheral base address. - * @param config Pointer to configuration structure. See "lpadc_config_t". - */ -void LPADC_Init(ADC_Type *base, const lpadc_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for initial configuration. - * - * This function initializes the converter configuration structure with an available settings. The default values are: - * @code - * config->enableInDozeMode = true; - * config->enableAnalogPreliminary = false; - * config->powerUpDelay = 0x80; - * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - * config->powerLevelMode = kLPADC_PowerLevelAlt1; - * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; - * config->enableConvPause = false; - * config->convPauseDelay = 0U; - * config->FIFOWatermark = 0U; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConfig(lpadc_config_t *config); - -/*! - * @brief De-initializes the LPADC module. - * - * @param base LPADC peripheral base address. - */ -void LPADC_Deinit(ADC_Type *base); - -/*! - * @brief Switch on/off the LPADC module. - * - * @param base LPADC peripheral base address. - * @param enable switcher to the module. - */ -static inline void LPADC_Enable(ADC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= ADC_CTRL_ADCEN_MASK; - } - else - { - base->CTRL &= ~ADC_CTRL_ADCEN_MASK; - } -} - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Do reset the conversion FIFO0. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO0(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO0_MASK; -} - -/*! - * @brief Do reset the conversion FIFO1. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO1(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO1_MASK; -} -#else -/*! - * @brief Do reset the conversion FIFO. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO_MASK; -} -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * @brief Do reset the module's configuration. - * - * Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL). - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetConfig(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RST_MASK; - base->CTRL &= ~ADC_CTRL_RST_MASK; -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Get status flags. - * - * @param base LPADC peripheral base address. - * @return status flags' mask. See to #_lpadc_status_flags. - */ -static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base) -{ - return base->STAT; -} - -/*! - * @brief Clear status flags. - * - * Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for flags to be cleared. See to #_lpadc_status_flags. - */ -static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) -{ - base->STAT = mask; -} - -#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) -/*! - * @brief Get trigger status flags to indicate which trigger sequences have been completed or interrupted by a high - * priority trigger exception. - * - * @param base LPADC peripheral base address. - * @return The OR'ed value of @ref _lpadc_trigger_status_flags. - */ -static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base) -{ - return base->TSTAT; -} - -/*! - * @brief Clear trigger status flags. - * - * @param base LPADC peripheral base address. - * @param mask The mask of trigger status flags to be cleared, should be the - * OR'ed value of @ref _lpadc_trigger_status_flags. - */ -static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask) -{ - base->TSTAT = mask; -} -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enable interrupts. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. - */ -static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask) -{ - base->IE |= mask; -} - -/*! - * @brief Disable interrupts. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. - */ -static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask) -{ - base->IE &= ~mask; -} - -/*! - * @name DMA Control - * @{ - */ - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Switch on/off the DMA trigger for FIFO0 watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFO0WatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE0_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE0_MASK; - } -} - -/*! - * @brief Switch on/off the DMA trigger for FIFO1 watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFO1WatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE1_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE1_MASK; - } -} -#else -/*! - * @brief Switch on/off the DMA trigger for FIFO watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE_MASK; - } -} -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - /* @} */ - -/*! - * @name Trigger and conversion with FIFO. - * @{ - */ - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Get the count of result kept in conversion FIFOn. - * - * @param base LPADC peripheral base address. - * @param index Result FIFO index. - * @return The count of result kept in conversion FIFOn. - */ -static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index) -{ - return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL[index]) >> ADC_FCTRL_FCOUNT_SHIFT; -} - -/*! - * brief Get the result in conversion FIFOn. - * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. - * param index Result FIFO index. - * - * return Status whether FIFOn entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index); -#else -/*! - * @brief Get the count of result kept in conversion FIFO. - * - * @param base LPADC peripheral base address. - * @return The count of result kept in conversion FIFO. - */ -static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base) -{ - return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL) >> ADC_FCTRL_FCOUNT_SHIFT; -} - -/*! - * @brief Get the result in conversion FIFO. - * - * @param base LPADC peripheral base address. - * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. - * - * @return Status whether FIFO entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * @brief Configure the conversion trigger source. - * - * Each programmable trigger can launch the conversion command in command buffer. - * - * @param base LPADC peripheral base address. - * @param triggerId ID for each trigger. Typically, the available value range is from 0. - * @param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. - */ -void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for trigger's configuration. - * - * This function initializes the trigger's configuration structure with an available settings. The default values are: - * @code - * config->commandIdSource = 0U; - * config->loopCountIndex = 0U; - * config->triggerIdSource = 0U; - * config->enableHardwareTrigger = false; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config); - -/*! - * @brief Do software trigger to conversion command. - * - * @param base LPADC peripheral base address. - * @param triggerIdMask Mask value for software trigger indexes, which count from zero. - */ -static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask) -{ - /* Writes to ADCx_SWTRIG register are ignored while ADCx_CTRL[ADCEN] is clear. */ - base->SWTRIG = triggerIdMask; -} - -/*! - * @brief Configure conversion command. - * - * @param base LPADC peripheral base address. - * @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. - * @param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. - */ -void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for conversion command's configuration. - * - * This function initializes the conversion command's configuration structure with an available settings. The default - * values are: - * @code - * config->sampleScaleMode = kLPADC_SampleFullScale; - * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; - * config->channelNumber = 0U; - * config->chainedNextCmdNumber = 0U; - * config->enableAutoChannelIncrement = false; - * config->loopCount = 0U; - * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - * config->sampleTimeMode = kLPADC_SampleTimeADCK3; - * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - * config->hardwareCompareValueHigh = 0U; - * config->hardwareCompareValueLow = 0U; - * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; - * config->enableWaitTrigger = false; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config); - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS -/*! - * @brief Enable the calibration function. - * - * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes - * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value - * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- - * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the - * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. - * - * @param base LPADC peripheral base address. - * @param enable switcher to the calibration function. - */ -void LPADC_EnableCalibration(ADC_Type *base, bool enable); -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! - * @brief Set proper offset value to trim ADC. - * - * To minimize the offset during normal operation, software should read the conversion result from - * the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register. - * - * @param base LPADC peripheral base address. - * @param value Setting offset value. - */ -static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value) -{ - base->OFSTRIM = (value & ADC_OFSTRIM_OFSTRIM_MASK) >> ADC_OFSTRIM_OFSTRIM_SHIFT; -} - -/*! - * @brief Do auto calibration. - * - * Calibration function should be executed before using converter in application. It used the software trigger and a - * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API - * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) - * -LPADC_SetConvTriggerConfig(...) - * - * @param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base); -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! - * @brief Set proper offset value to trim ADC. - * - * Set the offset trim value for offset calibration manually. - * - * @param base LPADC peripheral base address. - * @param valueA Setting offset value A. - * @param valueB Setting offset value B. - * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. - */ -static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t valueA, uint32_t valueB) -{ - base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB); -} -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ - -/*! - * @brief Enable the offset calibration function. - * - * @param base LPADC peripheral base address. - * @param enable switcher to the calibration function. - */ -static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= ADC_CTRL_CALOFS_MASK; - } - else - { - base->CTRL &= ~ADC_CTRL_CALOFS_MASK; - } -} - -/*! - * @brief Do offset calibration. - * - * @param base LPADC peripheral base address. - */ -void LPADC_DoOffsetCalibration(ADC_Type *base); - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ -/*! - * brief Do auto calibration. - * - * param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base); -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ - -/* @} */ - -#if defined(__cplusplus) -} -#endif -/*! - * @} - */ -#endif /* _FSL_LPADC_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mailbox.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mailbox.h deleted file mode 100644 index a55e5ec294a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mailbox.h +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_MAILBOX_H_ -#define _FSL_MAILBOX_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup mailbox - * @{ - */ - -/*! @file */ - -/****************************************************************************** - * Definitions - *****************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.mailbox" -#endif - -/*! @name Driver version */ -/*@{*/ -/*! @brief MAILBOX driver version 2.2.0. */ -#define FSL_MAILBOX_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) -/*@}*/ - -/*! - * @brief CPU ID. - */ -#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) -typedef enum _mailbox_cpu_id -{ - kMAILBOX_CM33_Core1 = 0, - kMAILBOX_CM33_Core0 -} mailbox_cpu_id_t; -#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES))) -typedef enum _mailbox_cpu_id -{ - kMAILBOX_CM0Plus = 0, - kMAILBOX_CM4 -} mailbox_cpu_id_t; -#endif - -#if (defined(CPU_NXH2004J640UK48)) -typedef enum _mailbox_id -{ - kMAILBOX_CM0Plus_Core0 = 0, - kMAILBOX_CM0Plus_Core1, - kMAILBOX_CM0Plus_Sw_Irq0, - kMAILBOX_CM0Plus_Sw_Irq1, - kMAILBOX_CM0Plus_Sw_Irq2, - kMAILBOX_CM0Plus_Sw_Irq3 -} mailbox_id_t; -#endif -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @name MAILBOX initialization - * @{ - */ - -/*! - * @brief Initializes the MAILBOX module. - * - * This function enables the MAILBOX clock only. - * - * @param base MAILBOX peripheral base address. - */ -static inline void MAILBOX_Init(MAILBOX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Mailbox); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_FEATURE_MAILBOX_HAS_NO_RESET) && FSL_FEATURE_MAILBOX_HAS_NO_RESET) - /* Reset the MAILBOX module */ - RESET_PeripheralReset(kMAILBOX_RST_SHIFT_RSTn); -#endif -} - -/*! - * @brief De-initializes the MAILBOX module. - * - * This function disables the MAILBOX clock only. - * - * @param base MAILBOX peripheral base address. - */ -static inline void MAILBOX_Deinit(MAILBOX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Mailbox); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/* @} */ - -#if ((defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) || \ - (defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES))) -/*! - * @brief Set data value in the mailbox based on the CPU ID. - * - * @param base MAILBOX peripheral base address. - * @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices, - * kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices. - * @param mboxData Data to send in the mailbox. - * - * @note Sets a data value to send via the MAILBOX to the other core. - */ -static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxData) -{ -#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) - assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); -#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES))) - assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); -#endif - base->MBOXIRQ[cpu_id].IRQ = mboxData; -} - -/*! - * @brief Get data in the mailbox based on the CPU ID. - * - * @param base MAILBOX peripheral base address. - * @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices, - * kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices. - * - * @return Current mailbox data. - */ -static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id) -{ -#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) - assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); -#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES))) - assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); -#endif - return base->MBOXIRQ[cpu_id].IRQ; -} - -/*! - * @brief Set data bits in the mailbox based on the CPU ID. - * - * @param base MAILBOX peripheral base address. - * @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices, - * kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices. - * @param mboxSetBits Data bits to set in the mailbox. - * - * @note Sets data bits to send via the MAILBOX to the other core. A value of 0 will - * do nothing. Only sets bits selected with a 1 in it's bit position. - */ -static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxSetBits) -{ -#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) - assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); -#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES))) - assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); -#endif - base->MBOXIRQ[cpu_id].IRQSET = mboxSetBits; -} - -/*! - * @brief Clear data bits in the mailbox based on the CPU ID. - * - * @param base MAILBOX peripheral base address. - * @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices, - * kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices. - * @param mboxClrBits Data bits to clear in the mailbox. - * - * @note Clear data bits to send via the MAILBOX to the other core. A value of 0 will - * do nothing. Only clears bits selected with a 1 in it's bit position. - */ -static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxClrBits) -{ -#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) - assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); -#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES))) - assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); -#endif - base->MBOXIRQ[cpu_id].IRQCLR = mboxClrBits; -} - -#elif (defined(CPU_NXH2004J640UK48)) - -/*! - * @brief Set data value in the mailbox based on the Mailbox ID. - * - * @param base MAILBOX peripheral base address. - * @param id Mailbox Index for NXH2004 devices - * @param mboxData Data to send in the mailbox. - * - */ -static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_id_t id, uint32_t mboxData) -{ - assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3)); - base->MBOXIRQ[id].IRQ = mboxData; -} - -/*! - * @brief Get data in the mailbox based on the Mailbox ID. - * - * @param base MAILBOX peripheral base address. - * @param id, Mailbox index for NXH2004 devies. - * - * @return Current mailbox data. - */ -static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_id_t id) -{ - assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3)); - return base->MBOXIRQ[id].IRQ; -} - -/*! - * @brief Set data bits in the mailbox based on the Mailbox Index. - * - * @param base MAILBOX peripheral base address. - * @param id Mailbox Index for NXH2004 devices - * @param mboxSetBits Data bits to set in the mailbox. - * - * @note Sets data bits to send via the MAILBOX. A value of 0 will - * do nothing. Only sets bits selected with a 1 in it's bit position. - */ -static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_id_t id, uint32_t mboxSetBits) -{ - assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3)); - base->MBOXIRQ[id].IRQSET = mboxSetBits; -} - -/*! - * @brief Clear data bits in the mailbox based on the Mailbox ID. - * - * @param base MAILBOX peripheral base address. - * @param id, Index to Mailbox for NXH2004 devices. - * @param mboxClrBits Data bits to clear in the mailbox. - * - * @note Clear data bits to send via the MAILBOX. A value of 0 will do - * nothing. Only clears bits selected with a 1 in it's bit position. - */ -static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_id_t id, uint32_t mboxClrBits) -{ - assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3)); - base->MBOXIRQ[id].IRQCLR = mboxClrBits; -} - -#endif /*CPU_NXH2004J640UK48*/ - -/*! - * @brief Get MUTEX state and lock mutex - * - * @param base MAILBOX peripheral base address. - * - * @return See note - * - * @note Returns '1' if the mutex was taken or '0' if another resources has the - * mutex locked. Once a mutex is taken, it can be returned with the MAILBOX_SetMutex() - * function. - */ -static inline uint32_t MAILBOX_GetMutex(MAILBOX_Type *base) -{ - return (base->MUTEX & MAILBOX_MUTEX_EX_MASK); -} - -/*! - * @brief Set MUTEX state - * - * @param base MAILBOX peripheral base address. - * - * @note Sets mutex state to '1' and allows other resources to get the mutex. - */ -static inline void MAILBOX_SetMutex(MAILBOX_Type *base) -{ - base->MUTEX = MAILBOX_MUTEX_EX_MASK; -} - -#if defined(__cplusplus) -} -#endif /*_cplusplus*/ -/*@}*/ - -#endif /* _FSL_MAILBOX_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.c deleted file mode 100644 index 69697a21b5c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_mrt.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.mrt" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base Multi-Rate timer peripheral base address - * - * @return The MRT instance - */ -static uint32_t MRT_GetInstance(MRT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to MRT bases for each instance. */ -static MRT_Type *const s_mrtBases[] = MRT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to MRT clocks for each instance. */ -static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(MRT_RSTS_N) -/*! @brief Pointers to MRT resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_mrtResets[] = MRT_RSTS_N; -#elif defined(MRT_RSTS) -/*! @brief Pointers to MRT resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_mrtResets[] = MRT_RSTS; -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t MRT_GetInstance(MRT_Type *base) -{ - uint32_t instance; - uint32_t mrtArrayCount = (sizeof(s_mrtBases) / sizeof(s_mrtBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < mrtArrayCount; instance++) - { - if (s_mrtBases[instance] == base) - { - break; - } - } - - assert(instance < mrtArrayCount); - - return instance; -} - -/*! - * brief Ungates the MRT clock and configures the peripheral for basic operation. - * - * note This API should be called at the beginning of the application using the MRT driver. - * - * param base Multi-Rate timer peripheral base address - * param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in - * MODCFG reigster, param config is useless. - */ -void MRT_Init(MRT_Type *base, const mrt_config_t *config) -{ - assert(config != NULL); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate the MRT clock */ - CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(MRT_RSTS_N) || defined(MRT_RSTS) - /* Reset the module. */ - RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]); -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) - /* Set timer operating mode */ - base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask); -#endif -} - -/*! - * brief Gate the MRT clock - * - * param base Multi-Rate timer peripheral base address - */ -void MRT_Deinit(MRT_Type *base) -{ - /* Stop all the timers */ - MRT_StopTimer(base, kMRT_Channel_0); - MRT_StopTimer(base, kMRT_Channel_1); -#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 2U) - MRT_StopTimer(base, kMRT_Channel_2); -#endif -#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 3U) - MRT_StopTimer(base, kMRT_Channel_3); -#endif - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the MRT clock*/ - CLOCK_DisableClock(s_mrtClocks[MRT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Used to update the timer period in units of count. - * - * The new value will be immediately loaded or will be loaded at the end of the current time - * interval. For one-shot interrupt mode the new value will be immediately loaded. - * - * note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * param base Multi-Rate timer peripheral base address - * param channel Timer channel number - * param count Timer period in units of ticks - * param immediateLoad true: Load the new value immediately into the TIMER register; - * false: Load the new value at the end of current timer interval - */ -void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - - uint32_t newValue = count; - if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == (uint8_t)kMRT_OneShotMode) || (immediateLoad)) - { - /* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */ - newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK; - } - - /* Update the timer interval value */ - base->CHANNEL[channel].INTVAL = newValue; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.h deleted file mode 100644 index 7829d984e20..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.h +++ /dev/null @@ -1,366 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_MRT_H_ -#define _FSL_MRT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup mrt - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3 */ -/*@}*/ - -/*! @brief List of MRT channels */ -typedef enum _mrt_chnl -{ - kMRT_Channel_0 = 0U, /*!< MRT channel number 0*/ - kMRT_Channel_1, /*!< MRT channel number 1 */ - kMRT_Channel_2, /*!< MRT channel number 2 */ - kMRT_Channel_3 /*!< MRT channel number 3 */ -} mrt_chnl_t; - -/*! @brief List of MRT timer modes */ -typedef enum _mrt_timer_mode -{ - kMRT_RepeatMode = (0 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< Repeat Interrupt mode */ - kMRT_OneShotMode = (1 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< One-shot Interrupt mode */ - kMRT_OneShotStallMode = (2 << MRT_CHANNEL_CTRL_MODE_SHIFT) /*!< One-shot stall mode */ -} mrt_timer_mode_t; - -/*! @brief List of MRT interrupts */ -typedef enum _mrt_interrupt_enable -{ - kMRT_TimerInterruptEnable = MRT_CHANNEL_CTRL_INTEN_MASK /*!< Timer interrupt enable*/ -} mrt_interrupt_enable_t; - -/*! @brief List of MRT status flags */ -typedef enum _mrt_status_flags -{ - kMRT_TimerInterruptFlag = MRT_CHANNEL_STAT_INTFLAG_MASK, /*!< Timer interrupt flag */ - kMRT_TimerRunFlag = MRT_CHANNEL_STAT_RUN_MASK, /*!< Indicates state of the timer */ -} mrt_status_flags_t; - -/*! - * @brief MRT configuration structure - * - * This structure holds the configuration settings for the MRT peripheral. To initialize this - * structure to reasonable defaults, call the MRT_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _mrt_config -{ - bool enableMultiTask; /*!< true: Timers run in multi-task mode; false: Timers run in hardware status mode */ -} mrt_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the MRT clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the MRT driver. - * - * @param base Multi-Rate timer peripheral base address - * @param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in - * MODCFG reigster, param config is useless. - */ -void MRT_Init(MRT_Type *base, const mrt_config_t *config); - -/*! - * @brief Gate the MRT clock - * - * @param base Multi-Rate timer peripheral base address - */ -void MRT_Deinit(MRT_Type *base); - -/*! - * @brief Fill in the MRT config struct with the default settings - * - * The default values are: - * @code - * config->enableMultiTask = false; - * @endcode - * @param config Pointer to user's MRT config structure. - */ -static inline void MRT_GetDefaultConfig(mrt_config_t *config) -{ - assert(config != NULL); -#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) - /* Use hardware status operating mode */ - config->enableMultiTask = false; -#endif -} - -/*! - * @brief Sets up an MRT channel mode. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Channel that is being configured. - * @param mode Timer mode to use for the channel. - */ -static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - - uint32_t reg = base->CHANNEL[channel].CTRL; - - /* Clear old value */ - reg &= ~MRT_CHANNEL_CTRL_MODE_MASK; - /* Add the new mode */ - reg |= (uint32_t)mode; - - base->CHANNEL[channel].CTRL = reg; -} - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the MRT interrupt. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].CTRL |= mask; -} - -/*! - * @brief Disables the selected MRT interrupt. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to disable. This is a logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].CTRL &= ~mask; -} - -/*! - * @brief Gets the enabled MRT interrupts. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the MRT status flags - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::mrt_status_flags_t - */ -static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK)); -} - -/*! - * @brief Clears the MRT status flags. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::mrt_status_flags_t - */ -static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK); -} - -/*! @}*/ - -/*! - * @name Read and Write the timer period - * @{ - */ - -/*! - * @brief Used to update the timer period in units of count. - * - * The new value will be immediately loaded or will be loaded at the end of the current time - * interval. For one-shot interrupt mode the new value will be immediately loaded. - * - * @note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param count Timer period in units of ticks - * @param immediateLoad true: Load the new value immediately into the TIMER register; - * false: Load the new value at the end of current timer interval - */ -void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad); - -/*! - * @brief Reads the current timer counting value. - * - * This function returns the real-time timer counting value, in a range from 0 to a - * timer period. - * - * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return Current timer counting value in ticks - */ -static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - return base->CHANNEL[channel].TIMER; -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the timer counting. - * - * After calling this function, timers load period value, counts down to 0 and - * depending on the timer mode it will either load the respective start value again or stop. - * - * @note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - * @param count Timer period in units of ticks. Count can contain the LOAD bit, which control the force load feature. - */ -static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - assert((uint32_t)(count & ~MRT_CHANNEL_INTVAL_LOAD_MASK) <= (uint32_t)MRT_CHANNEL_INTVAL_IVALUE_MASK); - /* Write the timer interval value */ - base->CHANNEL[channel].INTVAL = count; -} - -/*! - * @brief Stops the timer counting. - * - * This function stops the timer from counting. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - */ -static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - /* Stop the timer immediately */ - base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK; -} - -/*! @}*/ - -/*! - * @name Get & release channel - * @{ - */ - -/*! - * @brief Find the available channel. - * - * This function returns the lowest available channel number. - * - * @param base Multi-Rate timer peripheral base address - */ -static inline uint32_t MRT_GetIdleChannel(MRT_Type *base) -{ - return base->IDLE_CH; -} - -#if !(defined(FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) && FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) -/*! - * @brief Release the channel when the timer is using the multi-task mode. - * - * In multi-task mode, the INUSE flags allow more control over when MRT channels are released for - * further use. The user can hold on to a channel acquired by calling MRT_GetIdleChannel() for as - * long as it is needed and release it by calling this function. This removes the need to ask for - * an available channel for every use. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - */ -static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel) -{ - assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - - uint32_t reg = base->CHANNEL[channel].STAT; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg = ~MRT_CHANNEL_STAT_INTFLAG_MASK; - reg |= MRT_CHANNEL_STAT_INUSE_MASK; - - base->CHANNEL[channel].STAT = reg; -} -#endif - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_MRT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ostimer.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ostimer.c deleted file mode 100644 index c3acfb0e48f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ostimer.c +++ /dev/null @@ -1,381 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_ostimer.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.ostimer" -#endif - -/* Typedef for interrupt handler. */ -typedef void (*ostimer_isr_t)(OSTIMER_Type *base, ostimer_callback_t cb); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base OSTIMER peripheral base address - * - * @return The OSTIMER instance - */ -static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base); - -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) -/* @brief Translate the value from gray-code to decimal by the Code Gray in SYSCTL. - * - * @param gray The gray value input. - * - * @return the decimal value. - */ -static uint64_t OSTIMER_GrayToDecimalbyCodeGray(uint64_t gray); -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of OSTIMER handle. */ -static ostimer_callback_t s_ostimerHandle[FSL_FEATURE_SOC_OSTIMER_COUNT]; -/* Array of OSTIMER peripheral base address. */ -static OSTIMER_Type *const s_ostimerBases[] = OSTIMER_BASE_PTRS; -/* Array of OSTIMER IRQ number. */ -static const IRQn_Type s_ostimerIRQ[] = OSTIMER_IRQS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of OSTIMER clock name. */ -static const clock_ip_name_t s_ostimerClock[] = OSTIMER_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/* OSTIMER ISR for transactional APIs. */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -static ostimer_isr_t s_ostimerIsr = (ostimer_isr_t)DefaultISR; -#else -static ostimer_isr_t s_ostimerIsr; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* @brief Function for getting the instance number of OS timer. */ -static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_ostimerBases); instance++) - { - if (s_ostimerBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_ostimerBases)); - - return instance; -} - -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) -/* @brief Translate the value from gray-code to decimal by the Code Gray in SYSCTL. - * - * @param gray The gray value input. - * - * @return the decimal value. - */ -static uint64_t OSTIMER_GrayToDecimalbyCodeGray(uint64_t gray) -{ - uint64_t decOut; - - SYSCTL->CODE_GRAY_LSB = (uint32_t)(gray & 0xFFFFFFFFU); - SYSCTL->CODE_GRAY_MSB = (uint32_t)((gray >> 32U) & 0x3FFU); // limit to 42bits as OSevent timer - __NOP(); - decOut = ((uint64_t)(SYSCTL->CODE_BIN_MSB) & 0x3FFU) << 32U; - decOut |= (uint64_t)(SYSCTL->CODE_BIN_LSB); - - return decOut; -} -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ - -/* @brief Translate the value from gray-code to decimal. */ -/* - * @param gray The gray value input. - * - * @return the decimal value. - */ -uint64_t OSTIMER_GrayToDecimal(uint64_t gray) -{ -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) - return OSTIMER_GrayToDecimalbyCodeGray(gray); -#else - uint64_t temp = gray; - while (temp != 0U) - { - temp >>= 1U; - gray ^= temp; - } - - return gray; -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ -} - -/* @brief Enable the OSTIMER interrupt. - * - * After calling this function, the OSTIMER driver will enable/disable the IRQ and module interrupt enablement. - * - * @param base OSTIMER peripheral base address. - * @param enable enable/disable the IRQ and module interrupt enablement. - * - true: Disable the IRQ and module interrupt enablement. - * - false: Disable the IRQ and module interrupt enablement. - * @return none - */ -static void OSTIMER_EnableInterrupt(OSTIMER_Type *base, bool enable) -{ - assert(NULL != base); - - if (enable) - { - /* Enable the IRQ and module interrupt enablement. */ - (void)EnableIRQ(s_ostimerIRQ[OSTIMER_GetInstance(base)]); - base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; - } - else - { - /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ - (void)DisableIRQ(s_ostimerIRQ[OSTIMER_GetInstance(base)]); - base->OSEVENT_CTRL &= ~OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; /* Clear interrupt flag by writing 1. */ - } -} - -/*! - * @brief Initializes an OSTIMER by turning it's clock on. - * - */ -void OSTIMER_Init(OSTIMER_Type *base) -{ - assert(NULL != base); - - uint32_t instance = OSTIMER_GetInstance(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if !(defined(FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) && FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) - /* Enable the OSTIMER 32k clock in PMC module. */ - CLOCK_EnableOstimer32kClock(); -#endif - /* Enable clock for OSTIMER. */ - CLOCK_EnableClock(s_ostimerClock[instance]); -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) - CLOCK_EnableClock(kCLOCK_Sysctl); -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Deinitializes a OSTIMER instance. - * - * This function shuts down OSTIMER clock - * - * @param base OSTIMER peripheral base address. - */ -void OSTIMER_Deinit(OSTIMER_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable clock for OSTIMER. */ - CLOCK_DisableClock(s_ostimerClock[OSTIMER_GetInstance(base)]); -#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) - CLOCK_DisableClock(kCLOCK_Sysctl); -#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Get OSTIMER status Flags. - * - * This returns the status flag. - * Currently, only match interrupt flag can be got. - * - * @param base OSTIMER peripheral base address. - * @return status register value - */ -uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base) -{ - return base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK; -} - -/*! - * @brief Clear Status Interrupt Flags. - * - * This clears intr status flag. - * Currently, only match interrupt flag can be cleared. - * - * @param base OSTIMER peripheral base address. - * @param mask Clear bit mask. - * @return none - */ -void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask) -{ - base->OSEVENT_CTRL |= mask; -} - -/*! - * @brief Set the match raw value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. - * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is gray-code format) - * - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. - * @retval kStatus_Fail - Set match raw value fail. - */ -status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) -{ -#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK - uint64_t decValueTimer; -#endif - status_t status; - uint64_t tmp = count; - uint32_t instance = OSTIMER_GetInstance(base); - - /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ - OSTIMER_EnableInterrupt(base, false); - - s_ostimerIsr = OSTIMER_HandleIRQ; - s_ostimerHandle[instance] = cb; - - /* Set the match value. */ - base->MATCH_L = (uint32_t)tmp; - base->MATCH_H = (uint32_t)(tmp >> 32U); - -#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK - /* Workaround-2019-12-30: - * Since OSTimer's counter register is Gray-encoded, it would cost more time to write register. When EVTimer Match - * Write Ready bit is low, which means the previous match value has been updated successfully by that time, it is - * safe to reload (write) the Match Registers. Even if there is the RM comment that "In typical applications, it - * should not be necessary to test this bit", but we found the interruption would not be reported when the delta - * timer user added is smaller(IE: RT595 11us in 1MHz typical application) in release version." To prevent such - * issue from happening, we'd better wait for the match value to update successfully before enabling IRQ. - */ - while (0U != (base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)) - { - } - - /* After the WR_RDY bit became low, we need to check whether current time goes ahead of the match value we set. - * (1) If current timer value has gone ahead of the match value, the interrupt will not be reported before 64-bit - * timer value over flow. We need to check whether the interrupt flag has been set or not: if yes, we will enable - * interrupt and return success; if not, we will return fail directly. - * (2) If current timer value has not gone ahead of match value, we will enable interrupt and return success. - */ - decValueTimer = OSTIMER_GetCurrentTimerValue(base); - if ((decValueTimer >= OSTIMER_GrayToDecimal(tmp)) && - (0U == (base->OSEVENT_CTRL & (uint32_t)kOSTIMER_MatchInterruptFlag))) - { - status = kStatus_Fail; - } - else -#endif /* #ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK */ - { - /* Enable the module interrupt enablement. */ - OSTIMER_EnableInterrupt(base, true); - status = kStatus_Success; - } - - return status; -} - -/*! - * @brief Set the match value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code in - * API. ) - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @retval kStatus_Success - Set match value and enable interrupt Successfully. - * @retval kStatus_Fail - Set match value fail. - */ -status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) -{ - uint64_t tmp = OSTIMER_DecimalToGray(count); - - return OSTIMER_SetMatchRawValue(base, tmp, cb); -} - -/*! - * @brief Get current timer count value from OSTIMER. - * - * This function will get a decimal timer count value. - * The RAW value of timer count is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of OSTIMER which will formated to decimal value. - */ -uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = OSTIMER_GetCurrentTimerRawValue(base); - - return OSTIMER_GrayToDecimal(tmp); -} - -/*! - * @brief Get the capture value from OSTIMER. - * - * This function will get a capture decimal-value from OSTIMER. - * The RAW value of timer capture is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of capture register, data format is decimal. - */ -uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = OSTIMER_GetCaptureRawValue(base); - - return OSTIMER_GrayToDecimal(tmp); -} - -void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb) -{ - /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ - OSTIMER_EnableInterrupt(base, false); - - if (cb != NULL) - { - cb(); - } -} - -#if defined(OSTIMER0) -void OS_EVENT_DriverIRQHandler(void); -void OS_EVENT_DriverIRQHandler(void) -{ - s_ostimerIsr(OSTIMER0, s_ostimerHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if defined(OSTIMER) -void OS_EVENT_DriverIRQHandler(void); -void OS_EVENT_DriverIRQHandler(void) -{ - s_ostimerIsr(OSTIMER, s_ostimerHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ostimer.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ostimer.h deleted file mode 100644 index c74a7931362..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ostimer.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_OSTIMER_H_ -#define _FSL_OSTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup ostimer - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief OSTIMER driver version. */ -#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) -/*@}*/ - -/*! - * @brief OSTIMER status flags. - */ -enum _ostimer_flags -{ - kOSTIMER_MatchInterruptFlag = (OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK), /*!< Match interrupt flag bit, sets if - the match value was reached. */ -}; - -/*! @brief ostimer callback function. */ -typedef void (*ostimer_callback_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes an OSTIMER by turning its bus clock on - * - */ -void OSTIMER_Init(OSTIMER_Type *base); - -/*! - * @brief Deinitializes a OSTIMER instance. - * - * This function shuts down OSTIMER bus clock - * - * @param base OSTIMER peripheral base address. - */ -void OSTIMER_Deinit(OSTIMER_Type *base); - -/*! - * @brief Translate the value from gray-code to decimal. - * - * @param gray The gray value input. - * @return The decimal value. - */ -uint64_t OSTIMER_GrayToDecimal(uint64_t gray); - -/*! - * @brief Translate the value from decimal to gray-code. - * - * @param dec The decimal value. - * @return The gray code of the input value. - */ -static inline uint64_t OSTIMER_DecimalToGray(uint64_t dec) -{ - return (dec ^ (dec >> 1U)); -} - -/*! - * @brief Get OSTIMER status Flags. - * - * This returns the status flag. - * Currently, only match interrupt flag can be got. - * - * @param base OSTIMER peripheral base address. - * @return status register value - */ -uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base); - -/*! - * @brief Clear Status Interrupt Flags. - * - * This clears intrrupt status flag. - * Currently, only match interrupt flag can be cleared. - * - * @param base OSTIMER peripheral base address. - * @param mask Clear bit mask. - * @return none - */ -void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask); - -/*! - * @brief Set the match raw value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. - * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is gray-code format) - * - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. - * @retval kStatus_Fail - Set match raw value fail. - */ -status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); - -/*! - * @brief Set the match value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central OS TIMER. - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code - * internally.) - * - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @retval kStatus_Success - Set match value and enable interrupt Successfully. - * @retval kStatus_Fail - Set match value fail. - */ -status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); - -/*! - * @brief Set value to OSTIMER MATCH register directly. - * - * This function writes the input value to OSTIMER MATCH register directly, - * it does not touch any other registers. Note that, the data format is - * gray-code. The function @ref OSTIMER_DecimalToGray could convert decimal - * value to gray code. - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value (Value is gray-code format). - */ -static inline void OSTIMER_SetMatchRegister(OSTIMER_Type *base, uint64_t value) -{ -#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK - /* Wait for MATCH register ready for write. */ - while (0U != (base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)) - { - } -#endif - - base->MATCH_L = (uint32_t)value; - base->MATCH_H = (uint32_t)(value >> 32U); -} - -/*! - * @brief Enable the OSTIMER counter match interrupt. - * - * Enable the timer counter match interrupt. The interrupt happens when OSTIMER - * counter matches the value in MATCH registers. - * - * @param base OSTIMER peripheral base address. - */ -static inline void OSTIMER_EnableMatchInterrupt(OSTIMER_Type *base) -{ - base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; -} - -/*! - * @brief Disable the OSTIMER counter match interrupt. - * - * Disable the timer counter match interrupt. The interrupt happens when OSTIMER - * counter matches the value in MATCH registers. - * - * @param base OSTIMER peripheral base address. - */ -static inline void OSTIMER_DisableMatchInterrupt(OSTIMER_Type *base) -{ - base->OSEVENT_CTRL &= ~OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; -} - -/*! - * @brief Get current timer raw count value from OSTIMER. - * - * This function will get a gray code type timer count value from OS timer register. - * The raw value of timer count is gray code format. - * - * @param base OSTIMER peripheral base address. - * @return Raw value of OSTIMER, gray code format. - */ -static inline uint64_t OSTIMER_GetCurrentTimerRawValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = base->EVTIMERL; - tmp |= (uint64_t)(base->EVTIMERH) << 32U; - - return tmp; -} - -/*! - * @brief Get current timer count value from OSTIMER. - * - * This function will get a decimal timer count value. - * The RAW value of timer count is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of OSTIMER which will be formated to decimal value. - */ -uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base); - -/*! - * @brief Get the capture value from OSTIMER. - * - * This function will get a captured gray-code value from OSTIMER. - * The Raw value of timer capture is gray code format. - * - * @param base OSTIMER peripheral base address. - * @return Raw value of capture register, data format is gray code. - */ -static inline uint64_t OSTIMER_GetCaptureRawValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = base->CAPTURE_L; - tmp |= (uint64_t)(base->CAPTURE_H) << 32U; - - return tmp; -} - -/*! - * @brief Get the capture value from OSTIMER. - * - * This function will get a capture decimal-value from OSTIMER. - * The RAW value of timer capture is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of capture register, data format is decimal. - */ -uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base); - -/*! - * @brief OS timer interrupt Service Handler. - * - * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request - * in OSTIMER_SetMatchValue()). - * if no user callback is scheduled, the interrupt will simply be cleared. - * - * @param base OS timer peripheral base address. - * @param cb callback scheduled for this instance of OS timer - * @return none - */ -void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb); -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_OSTIMER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_pint.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_pint.c deleted file mode 100644 index c5557dd030f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_pint.c +++ /dev/null @@ -1,971 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_pint.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.pint" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -/*! @brief Irq number array */ -static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS + - FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; - -/*! @brief Callback function array for SECPINT(s). */ -static pint_cb_t s_secpintCallback[FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS]; -#else -/*! @brief Irq number array */ -static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - -/*! @brief Callback function array for PINT(s). */ -static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Initialize PINT peripheral. - - * This function initializes the PINT peripheral and enables the clock. - * - * param base Base address of the PINT peripheral. - * - * retval None. - */ -void PINT_Init(PINT_Type *base) -{ - uint32_t i; - uint32_t pmcfg = 0; - uint8_t pintcount = 0; - assert(base != NULL); - - if (base == PINT) - { - pintcount = FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; - /* clear PINT callback array*/ - for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_pintCallback[i] = NULL; - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - pintcount = FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; - /* clear SECPINT callback array*/ - for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_secpintCallback[i] = NULL; - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - - /* Disable all bit slices for pint*/ - for (i = 0; i < pintcount; i++) - { - pmcfg = pmcfg | ((uint32_t)kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U))); - } - -#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_GpioInt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) - - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio_Sec); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - -#else - - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Pint); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } - else - { - /* if need config SECURE PINT device,then enable secure pint interrupt clock */ -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio_Sec_Int); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } -#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ - - /* Disable all pattern match bit slices */ - base->PMCFG = pmcfg; -} - -/*! - * brief Configure PINT peripheral pin interrupt. - - * This function configures a given pin interrupt. - * - * param base Base address of the PINT peripheral. - * param intr Pin interrupt. - * param enable Selects detection logic. - * param callback Callback. - * - * retval None. - */ -void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback) -{ - assert(base != NULL); - - /* Clear Rise and Fall flags first */ - PINT_PinInterruptClrRiseFlag(base, intr); - PINT_PinInterruptClrFallFlag(base, intr); - - /* Security PINT uses additional callback array */ - if (base == PINT) - { - s_pintCallback[intr] = callback; - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - s_secpintCallback[intr] = callback; -#endif - } - - /* select level or edge sensitive */ - base->ISEL = (base->ISEL & ~(1UL << (uint32_t)intr)) | - ((((uint32_t)enable & PINT_PIN_INT_LEVEL) != 0U) ? (1UL << (uint32_t)intr) : 0U); - - /* enable rising or level interrupt */ - if (((unsigned)enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE)) != 0U) - { - base->SIENR = 1UL << (uint32_t)intr; - } - else - { - base->CIENR = 1UL << (uint32_t)intr; - } - - /* Enable falling or select high level */ - if (((unsigned)enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL) != 0U) - { - base->SIENF = 1UL << (uint32_t)intr; - } - else - { - base->CIENF = 1UL << (uint32_t)intr; - } -} - -/*! - * brief Get PINT peripheral pin interrupt configuration. - - * This function returns the configuration of a given pin interrupt. - * - * param base Base address of the PINT peripheral. - * param pintr Pin interrupt. - * param enable Pointer to store the detection logic. - * param callback Callback. - * - * retval None. - */ -void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback) -{ - uint32_t mask; - bool level; - - assert(base != NULL); - - *enable = kPINT_PinIntEnableNone; - level = false; - - mask = 1UL << (uint32_t)pintr; - if ((base->ISEL & mask) != 0U) - { - /* Pin interrupt is level sensitive */ - level = true; - } - - if ((base->IENR & mask) != 0U) - { - if (level) - { - /* Level interrupt is enabled */ - *enable = kPINT_PinIntEnableLowLevel; - } - else - { - /* Rising edge interrupt */ - *enable = kPINT_PinIntEnableRiseEdge; - } - } - - if ((base->IENF & mask) != 0U) - { - if (level) - { - /* Level interrupt is active high */ - *enable = kPINT_PinIntEnableHighLevel; - } - else - { - /* Either falling or both edge */ - if (*enable == kPINT_PinIntEnableRiseEdge) - { - /* Rising and faling edge */ - *enable = kPINT_PinIntEnableBothEdges; - } - else - { - /* Falling edge */ - *enable = kPINT_PinIntEnableFallEdge; - } - } - } - - /* Security PINT uses additional callback array */ - if (base == PINT) - { - *callback = s_pintCallback[pintr]; - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - *callback = s_secpintCallback[pintr]; -#endif - } -} - -/*! - * brief Configure PINT pattern match. - - * This function configures a given pattern match bit slice. - * - * param base Base address of the PINT peripheral. - * param bslice Pattern match bit slice number. - * param cfg Pointer to bit slice configuration. - * - * retval None. - */ -void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) -{ - uint32_t src_shift; - uint32_t cfg_shift; - uint32_t pmcfg; - uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; - uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; - - assert(base != NULL); - - src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); - cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); - - /* Input source selection for selected bit slice */ - base->PMSRC = (base->PMSRC & ~(tmp_src_shift << src_shift)) | ((uint32_t)(cfg->bs_src) << src_shift); - - /* Bit slice configuration */ - pmcfg = base->PMCFG; - pmcfg = (pmcfg & ~(tmp_cfg_shift << cfg_shift)) | ((uint32_t)(cfg->bs_cfg) << cfg_shift); - - /* If end point is true, enable the bits */ - if ((uint32_t)bslice != 7UL) - { - if (cfg->end_point) - { - pmcfg |= (1UL << (uint32_t)bslice); - } - else - { - pmcfg &= ~(1UL << (uint32_t)bslice); - } - } - - base->PMCFG = pmcfg; - - /* Save callback pointer */ - if (base == PINT) - { - if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) - { - s_pintCallback[bslice] = cfg->callback; - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - { - s_secpintCallback[bslice] = cfg->callback; - } -#endif - } -} - -/*! - * brief Get PINT pattern match configuration. - - * This function returns the configuration of a given pattern match bit slice. - * - * param base Base address of the PINT peripheral. - * param bslice Pattern match bit slice number. - * param cfg Pointer to bit slice configuration. - * - * retval None. - */ -void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) -{ - uint32_t src_shift; - uint32_t cfg_shift; - uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; - uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; - - assert(base != NULL); - - src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); - cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); - - cfg->bs_src = (pint_pmatch_input_src_t)(uint32_t)((base->PMSRC & (tmp_src_shift << src_shift)) >> src_shift); - cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)(uint32_t)((base->PMCFG & (tmp_cfg_shift << cfg_shift)) >> cfg_shift); - - if ((uint32_t)bslice == 7U) - { - cfg->end_point = true; - } - else - { - cfg->end_point = (((base->PMCFG & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice) != 0U) ? true : false; - } - - if (base == PINT) - { - if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) - { - cfg->callback = s_pintCallback[bslice]; - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - { - cfg->callback = s_secpintCallback[bslice]; - } -#endif - } -} - -/*! - * brief Reset pattern match detection logic. - - * This function resets the pattern match detection logic if any of the product term is matching. - * - * param base Base address of the PINT peripheral. - * - * retval pmstatus Each bit position indicates the match status of corresponding bit slice. - * = 0 Match was detected. = 1 Match was not detected. - */ -uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base) -{ - uint32_t pmctrl; - uint32_t pmstatus; - uint32_t pmsrc; - - pmctrl = base->PMCTRL; - pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT; - if (pmstatus != 0UL) - { - /* Reset Pattern match engine detection logic */ - pmsrc = base->PMSRC; - base->PMSRC = pmsrc; - } - return (pmstatus); -} - -/*! - * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. - - * This function clears the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr) -{ - uint32_t pinIntMode = base->ISEL & (1UL << (uint32_t)pintr); - uint32_t pinIntStatus = base->IST & (1UL << (uint32_t)pintr); - - /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ - if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) - { - base->IST = (1UL << (uint32_t)pintr); - } -} - -/*! - * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. - - * This function clears the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_PinInterruptClrStatusAll(PINT_Type *base) -{ - uint32_t pinIntMode = 0; - uint32_t pinIntStatus = 0; - uint32_t pinIntCount = 0; - uint32_t mask = 0; - uint32_t i; - - if (base == PINT) - { - pinIntCount = (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - pinIntCount = (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - - for (i = 0; i < pinIntCount; i++) - { - pinIntMode = base->ISEL & (1UL << i); - pinIntStatus = base->IST & (1UL << i); - - /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ - if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) - { - mask |= 1UL << i; - } - } - - base->IST = mask; -} - -/*! - * brief Enable callback. - - * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * param base Base address of the PINT peripheral. - * - * retval None. - */ -void PINT_EnableCallback(PINT_Type *base) -{ - uint32_t i; - - assert(base != NULL); - - if (base == PINT) - { - for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i]); - (void)EnableIRQ(s_pintIRQ[i]); - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - (void)EnableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } -} - -/*! - * brief enable callback by pin index. - - * This function enables callback by pin index instead of enabling all pins. - * - * param base Base address of the peripheral. - * param pinIdx pin index. - * - * retval None. - */ -void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) -{ - assert(base != NULL); - - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); - -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - /* Get the right security pint irq index in array */ - if (base == SECPINT) - { - pintIdx = - (pint_pin_int_t)(uint32_t)((uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS); - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - - NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); - (void)EnableIRQ(s_pintIRQ[pintIdx]); -} - -/*! - * brief Disable callback. - - * This function disables the interrupt for the selected PINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * param base Base address of the peripheral. - * - * retval None. - */ -void PINT_DisableCallback(PINT_Type *base) -{ - uint32_t i; - - assert(base != NULL); - - if (base == PINT) - { - for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - (void)DisableIRQ(s_pintIRQ[i]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i]); - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - (void)DisableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } -} - -/*! - * brief disable callback by pin index. - - * This function disables callback by pin index instead of disabling all pins. - * - * param base Base address of the peripheral. - * param pinIdx pin index. - * - * retval None. - */ -void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) -{ - assert(base != NULL); - - if (base == PINT) - { - (void)DisableIRQ(s_pintIRQ[pintIdx]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); - NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - (void)DisableIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); - NVIC_ClearPendingIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); -#endif - } -} - -/*! - * brief Deinitialize PINT peripheral. - - * This function disables the PINT clock. - * - * param base Base address of the PINT peripheral. - * - * retval None. - */ -void PINT_Deinit(PINT_Type *base) -{ - uint32_t i; - - assert(base != NULL); - - /* Cleanup */ - PINT_DisableCallback(base); - if (base == PINT) - { - /* clear PINT callback array*/ - for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_pintCallback[i] = NULL; - } - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - /* clear SECPINT callback array */ - for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_secpintCallback[i] = NULL; - } -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - -#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_GpioInt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) - - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } - else - { -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio_Sec); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } - -#else - - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Pint); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } - else - { - /* if need config SECURE PINT device,then enable secure pint interrupt clock */ -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio_Sec_Int); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - } -#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ -} -#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -/* IRQ handler functions overloading weak symbols in the startup */ -void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void); -void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void) -{ - uint32_t pmstatus = 0; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); - /* Call user function */ - if (s_secpintCallback[kPINT_SecPinInt0] != NULL) - { - s_secpintCallback[kPINT_SecPinInt0](kPINT_SecPinInt0, pmstatus); - } - if ((SECPINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt0); - } - SDK_ISR_EXIT_BARRIER; -} - -#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) -/* IRQ handler functions overloading weak symbols in the startup */ -void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void); -void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); - /* Call user function */ - if (s_secpintCallback[kPINT_SecPinInt1] != NULL) - { - s_secpintCallback[kPINT_SecPinInt1](kPINT_SecPinInt1, pmstatus); - } - if ((SECPINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt1); - } - SDK_ISR_EXIT_BARRIER; -} -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - -/* IRQ handler functions overloading weak symbols in the startup */ -void PIN_INT0_DriverIRQHandler(void); -void PIN_INT0_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt0] != NULL) - { - s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus); - } - if ((PINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); - } - SDK_ISR_EXIT_BARRIER; -} - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) -void PIN_INT1_DriverIRQHandler(void); -void PIN_INT1_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt1] != NULL) - { - s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus); - } - if ((PINT->ISEL & 0x2U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) -void PIN_INT2_DriverIRQHandler(void); -void PIN_INT2_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt2] != NULL) - { - s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus); - } - if ((PINT->ISEL & 0x4U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) -void PIN_INT3_DriverIRQHandler(void); -void PIN_INT3_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt3] != NULL) - { - s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus); - } - if ((PINT->ISEL & 0x8U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) -void PIN_INT4_DriverIRQHandler(void); -void PIN_INT4_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt4] != NULL) - { - s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus); - } - if ((PINT->ISEL & 0x10U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT5_DAC1_IRQHandler(void); -void PIN_INT5_DAC1_IRQHandler(void) -#else -void PIN_INT5_DriverIRQHandler(void); -void PIN_INT5_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt5] != NULL) - { - s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus); - } - if ((PINT->ISEL & 0x20U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT6_USART3_IRQHandler(void); -void PIN_INT6_USART3_IRQHandler(void) -#else -void PIN_INT6_DriverIRQHandler(void); -void PIN_INT6_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt6] != NULL) - { - s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus); - } - if ((PINT->ISEL & 0x40U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6); - } - SDK_ISR_EXIT_BARRIER; -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT7_USART4_IRQHandler(void); -void PIN_INT7_USART4_IRQHandler(void) -#else -void PIN_INT7_DriverIRQHandler(void); -void PIN_INT7_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt7] != NULL) - { - s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus); - } - if ((PINT->ISEL & 0x80U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7); - } - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_pint.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_pint.h deleted file mode 100644 index eb7ed612b92..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_pint.h +++ /dev/null @@ -1,581 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_PINT_H_ -#define _FSL_PINT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup pint_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 1, 9)) /*!< Version 2.1.9 */ -/*@}*/ - -/* Number of interrupt line supported by PINT */ -#define PINT_PIN_INT_COUNT 8U - -/* Number of interrupt line supported by SECURE PINT */ -#define SEC_PINT_PIN_INT_COUNT 2U - -/* Number of input sources supported by PINT */ -#define PINT_INPUT_COUNT 8U - -/* PININT Bit slice source register bits */ -#define PININT_BITSLICE_SRC_START 8U -#define PININT_BITSLICE_SRC_MASK 7U - -/* PININT Bit slice configuration register bits */ -#define PININT_BITSLICE_CFG_START 8U -#define PININT_BITSLICE_CFG_MASK 7U -#define PININT_BITSLICE_ENDP_MASK 7U - -#define PINT_PIN_INT_LEVEL 0x10U -#define PINT_PIN_INT_EDGE 0x00U -#define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U -#define PINT_PIN_INT_RISE 0x01U -#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE) -#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) -#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) -#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL) -#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) - -/*! @brief PINT Pin Interrupt enable type */ -typedef enum _pint_pin_enable -{ - kPINT_PinIntEnableNone = 0U, /*!< Do not generate Pin Interrupt */ - kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE, /*!< Generate Pin Interrupt on rising edge */ - kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE, /*!< Generate Pin Interrupt on falling edge */ - kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */ - kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL, /*!< Generate Pin Interrupt on low level */ - kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */ -} pint_pin_enable_t; - -/*! @brief PINT Pin Interrupt type */ -typedef enum _pint_int -{ - kPINT_PinInt0 = 0U, /*!< Pin Interrupt 0 */ -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_PinInt1 = 1U, /*!< Pin Interrupt 1 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) - kPINT_PinInt2 = 2U, /*!< Pin Interrupt 2 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) - kPINT_PinInt3 = 3U, /*!< Pin Interrupt 3 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) - kPINT_PinInt4 = 4U, /*!< Pin Interrupt 4 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) - kPINT_PinInt5 = 5U, /*!< Pin Interrupt 5 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) - kPINT_PinInt6 = 6U, /*!< Pin Interrupt 6 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) - kPINT_PinInt7 = 7U, /*!< Pin Interrupt 7 */ -#endif -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) - kPINT_SecPinInt0 = 0U, /*!< Secure Pin Interrupt 0 */ -#endif -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_SecPinInt1 = 1U, /*!< Secure Pin Interrupt 1 */ -#endif -} pint_pin_int_t; - -/*! @brief PINT Pattern Match bit slice input source type */ -typedef enum _pint_pmatch_input_src -{ - kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */ - kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */ - kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */ - kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */ - kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */ - kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */ - kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */ - kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */ - kPINT_SecPatternMatchInp0Src = 0U, /*!< Input source 0 */ - kPINT_SecPatternMatchInp1Src = 1U, /*!< Input source 1 */ -} pint_pmatch_input_src_t; - -/*! @brief PINT Pattern Match bit slice type */ -typedef enum _pint_pmatch_bslice -{ - kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) - kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) - kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) - kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) - kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) - kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */ -#endif -#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) - kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */ -#endif -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) - kPINT_SecPatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ -#endif -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_SecPatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ -#endif -} pint_pmatch_bslice_t; - -/*! @brief PINT Pattern Match configuration type */ -typedef enum _pint_pmatch_bslice_cfg -{ - kPINT_PatternMatchAlways = 0U, /*!< Always Contributes to product term match */ - kPINT_PatternMatchStickyRise = 1U, /*!< Sticky Rising edge */ - kPINT_PatternMatchStickyFall = 2U, /*!< Sticky Falling edge */ - kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */ - kPINT_PatternMatchHigh = 4U, /*!< High level */ - kPINT_PatternMatchLow = 5U, /*!< Low level */ - kPINT_PatternMatchNever = 6U, /*!< Never contributes to product term match */ - kPINT_PatternMatchBothEdges = 7U, /*!< Either rising or falling edge */ -} pint_pmatch_bslice_cfg_t; - -/*! @brief PINT Callback function. */ -typedef void (*pint_cb_t)(pint_pin_int_t pintr, uint32_t pmatch_status); - -typedef struct _pint_pmatch_cfg -{ - pint_pmatch_input_src_t bs_src; - pint_pmatch_bslice_cfg_t bs_cfg; - bool end_point; - pint_cb_t callback; -} pint_pmatch_cfg_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize PINT peripheral. - - * This function initializes the PINT peripheral and enables the clock. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_Init(PINT_Type *base); - -/*! - * @brief Configure PINT peripheral pin interrupt. - - * This function configures a given pin interrupt. - * - * @param base Base address of the PINT peripheral. - * @param intr Pin interrupt. - * @param enable Selects detection logic. - * @param callback Callback. - * - * @retval None. - */ -void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback); - -/*! - * @brief Get PINT peripheral pin interrupt configuration. - - * This function returns the configuration of a given pin interrupt. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * @param enable Pointer to store the detection logic. - * @param callback Callback. - * - * @retval None. - */ -void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback); - -/*! - * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. - - * This function clears the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr); - -/*! - * @brief Get Selected pin interrupt status. - - * This function returns the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval status = 0 No pin interrupt request. = 1 Selected Pin interrupt request active. - */ -static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->IST & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. - - * This function clears the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_PinInterruptClrStatusAll(PINT_Type *base); - -/*! - * @brief Get all pin interrupts status. - - * This function returns the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval status Each bit position indicates the status of corresponding pin interrupt. - * = 0 No pin interrupt request. = 1 Pin interrupt request active. - */ -static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base) -{ - return (base->IST); -} - -/*! - * @brief Clear Selected pin interrupt fall flag. - - * This function clears the selected pin interrupt fall flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - base->FALL = (1UL << (uint32_t)pintr); -} - -/*! - * @brief Get selected pin interrupt fall flag. - - * This function returns the selected pin interrupt fall flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval flag = 0 Falling edge has not been detected. = 1 Falling edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->FALL & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupt fall flags. - - * This function clears the fall flag for all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base) -{ - base->FALL = PINT_FALL_FDET_MASK; -} - -/*! - * @brief Get all pin interrupt fall flags. - - * This function returns the fall flag of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval flags Each bit position indicates the falling edge detection of the corresponding pin interrupt. - * 0 Falling edge has not been detected. = 1 Falling edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base) -{ - return (base->FALL); -} - -/*! - * @brief Clear Selected pin interrupt rise flag. - - * This function clears the selected pin interrupt rise flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - base->RISE = (1UL << (uint32_t)pintr); -} - -/*! - * @brief Get selected pin interrupt rise flag. - - * This function returns the selected pin interrupt rise flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval flag = 0 Rising edge has not been detected. = 1 Rising edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->RISE & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupt rise flags. - - * This function clears the rise flag for all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base) -{ - base->RISE = PINT_RISE_RDET_MASK; -} - -/*! - * @brief Get all pin interrupt rise flags. - - * This function returns the rise flag of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval flags Each bit position indicates the rising edge detection of the corresponding pin interrupt. - * 0 Rising edge has not been detected. = 1 Rising edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base) -{ - return (base->RISE); -} - -/*! - * @brief Configure PINT pattern match. - - * This function configures a given pattern match bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * @param cfg Pointer to bit slice configuration. - * - * @retval None. - */ -void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); - -/*! - * @brief Get PINT pattern match configuration. - - * This function returns the configuration of a given pattern match bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * @param cfg Pointer to bit slice configuration. - * - * @retval None. - */ -void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); - -/*! - * @brief Get pattern match bit slice status. - - * This function returns the status of selected bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * - * @retval status = 0 Match has not been detected. = 1 Match has been detected. - */ -static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_bslice_t bslice) -{ - return ((base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT) & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice; -} - -/*! - * @brief Get status of all pattern match bit slices. - - * This function returns the status of all bit slices. - * - * @param base Base address of the PINT peripheral. - * - * @retval status Each bit position indicates the match status of corresponding bit slice. - * = 0 Match has not been detected. = 1 Match has been detected. - */ -static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base) -{ - return base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT; -} - -/*! - * @brief Reset pattern match detection logic. - - * This function resets the pattern match detection logic if any of the product term is matching. - * - * @param base Base address of the PINT peripheral. - * - * @retval pmstatus Each bit position indicates the match status of corresponding bit slice. - * = 0 Match was detected. = 1 Match was not detected. - */ -uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base); - -/*! - * @brief Enable pattern match function. - - * This function enables the pattern match function. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchEnable(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) | PINT_PMCTRL_SEL_PMATCH_MASK; -} - -/*! - * @brief Disable pattern match function. - - * This function disables the pattern match function. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchDisable(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) & ~PINT_PMCTRL_SEL_PMATCH_MASK; -} - -/*! - * @brief Enable RXEV output. - - * This function enables the pattern match RXEV output. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) | PINT_PMCTRL_ENA_RXEV_MASK; -} - -/*! - * @brief Disable RXEV output. - - * This function disables the pattern match RXEV output. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) & ~PINT_PMCTRL_ENA_RXEV_MASK; -} - -/*! - * @brief Enable callback. - - * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_EnableCallback(PINT_Type *base); - -/*! - * @brief Disable callback. - - * This function disables the interrupt for the selected PINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * @param base Base address of the peripheral. - * - * @retval None. - */ -void PINT_DisableCallback(PINT_Type *base); - -/*! - * @brief Deinitialize PINT peripheral. - - * This function disables the PINT clock. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_Deinit(PINT_Type *base); - -/*! - * @brief enable callback by pin index. - - * This function enables callback by pin index instead of enabling all pins. - * - * @param base Base address of the peripheral. - * @param pintIdx pin index. - * - * @retval None. - */ -void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); - -/*! - * @brief disable callback by pin index. - - * This function disables callback by pin index instead of disabling all pins. - * - * @param base Base address of the peripheral. - * @param pintIdx pin index. - * - * @retval None. - */ -void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_PINT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_plu.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_plu.c deleted file mode 100644 index b50f472675e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_plu.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_plu.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.plu" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Gets the instance from the base address - * - * @param base PLU peripheral base address - * - * @return The PLU instance - */ -static uint32_t PLU_GetInstance(PLU_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to PLU bases for each instance. */ -static PLU_Type *const s_pluBases[] = PLU_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to PLU clocks for each instance. */ -static const clock_ip_name_t s_pluClocks[] = PLU_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -/*! @brief Pointers to PLU resets for each instance. */ -static const reset_ip_name_t s_lpuResets[] = PLU_RSTS_N; -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t PLU_GetInstance(PLU_Type *base) -{ - uint32_t instance; - uint32_t pluArrayCount = (sizeof(s_pluBases) / sizeof(s_pluBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < pluArrayCount; instance++) - { - if (s_pluBases[instance] == base) - { - break; - } - } - - assert(instance < pluArrayCount); - - return instance; -} - -/*! - * brief Ungates the PLU clock and reset the module. - * - * note This API should be called at the beginning of the application using the PLU driver. - * - * param base PLU peripheral base address - */ -void PLU_Init(PLU_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the PLU peripheral clock */ - CLOCK_EnableClock(s_pluClocks[PLU_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_lpuResets[PLU_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -} - -/*! - * brief Gate the PLU clock - * - * param base PLU peripheral base address - */ -void PLU_Deinit(PLU_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the module clock */ - CLOCK_DisableClock((s_pluClocks[PLU_GetInstance(base)])); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -#if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG -/*! - * @brief Gets an available pre-defined settings for wakeup/interrupt control. - * - * This function initializes the initial configuration structure with an available settings. The default values are: - * @code - * config->filterMode = kPLU_WAKEINT_FILTER_MODE_BYPASS; - * config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC; - * @endcode - * @param config Pointer to configuration structure. - */ -void PLU_GetDefaultWakeIntConfig(plu_wakeint_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->filterMode = kPLU_WAKEINT_FILTER_MODE_BYPASS; - config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC; -} - -/*! - * @brief Enable PLU outputs wakeup/interrupt request. - * - * This function enables Any of the eight selected PLU outputs to contribute to an asynchronous wake-up or an interrupt - * request. - * - * Note: If a PLU_CLKIN is provided, the raw wake-up/interrupt request will be set on the rising-edge of the PLU_CLKIN - * whenever the raw request signal is high. This registered signal will be glitch-free and just use the default wakeint - * config by PLU_GetDefaultWakeIntConfig(). If not, have to specify the filter mode and clock source to eliminate the - * glitches caused by long and widely disparate delays through the network of LUTs making up the PLU. This way may - * increase power consumption in low-power operating modes and inject delay before the wake-up/interrupt request is - * generated. - * - * @param base PLU peripheral base address. - * @param interruptMask PLU interrupt mask (see @ref _plu_interrupt_mask enumeration). - * @param config Pointer to configuration structure (see @ref plu_wakeint_config_t typedef enumeration) - */ -void PLU_EnableWakeIntRequest(PLU_Type *base, uint32_t interruptMask, const plu_wakeint_config_t *config) -{ - uint32_t tmp32 = 0U; - - tmp32 = PLU_WAKEINT_CTRL_FILTER_MODE(config->filterMode) | PLU_WAKEINT_CTRL_FILTER_CLKSEL(config->clockSource) | - PLU_WAKEINT_CTRL_MASK(interruptMask); - - base->WAKEINT_CTRL = tmp32; -} - -/*! - * @brief Clear the latched interrupt - * - * This function clears the wake-up/interrupt request flag latched by PLU_LatchInterrupt() - * - * Note: It is not necessary for the PLU bus clock to be enabled in order to write-to or read-back this bit. - * - * @param base PLU peripheral base address. - */ -void PLU_ClearLatchedInterrupt(PLU_Type *base) -{ - base->WAKEINT_CTRL |= PLU_WAKEINT_CTRL_INTR_CLEAR_MASK; - /* It will take a delay of up to 1.5 PLU_CLKIN clock cycles before this write-to-clear takes effect. */ - while (PLU_WAKEINT_CTRL_INTR_CLEAR_MASK == (base->WAKEINT_CTRL & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK)) - { - } -} -#endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_plu.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_plu.h deleted file mode 100644 index 0c94d49091d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_plu.h +++ /dev/null @@ -1,374 +0,0 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_PLU_H_ -#define _FSL_PLU_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup plu - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_PLU_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1 */ - /*@}*/ - -/*! @brief Index of LUT */ -typedef enum _plu_lut_index -{ - kPLU_LUT_0 = 0U, /*!< 5-input Look-up Table 0 */ - kPLU_LUT_1 = 1U, /*!< 5-input Look-up Table 1 */ - kPLU_LUT_2 = 2U, /*!< 5-input Look-up Table 2 */ - kPLU_LUT_3 = 3U, /*!< 5-input Look-up Table 3 */ - kPLU_LUT_4 = 4U, /*!< 5-input Look-up Table 4 */ - kPLU_LUT_5 = 5U, /*!< 5-input Look-up Table 5 */ - kPLU_LUT_6 = 6U, /*!< 5-input Look-up Table 6 */ - kPLU_LUT_7 = 7U, /*!< 5-input Look-up Table 7 */ - kPLU_LUT_8 = 8U, /*!< 5-input Look-up Table 8 */ - kPLU_LUT_9 = 9U, /*!< 5-input Look-up Table 9 */ - kPLU_LUT_10 = 10U, /*!< 5-input Look-up Table 10 */ - kPLU_LUT_11 = 11U, /*!< 5-input Look-up Table 11 */ - kPLU_LUT_12 = 12U, /*!< 5-input Look-up Table 12 */ - kPLU_LUT_13 = 13U, /*!< 5-input Look-up Table 13 */ - kPLU_LUT_14 = 14U, /*!< 5-input Look-up Table 14 */ - kPLU_LUT_15 = 15U, /*!< 5-input Look-up Table 15 */ - kPLU_LUT_16 = 16U, /*!< 5-input Look-up Table 16 */ - kPLU_LUT_17 = 17U, /*!< 5-input Look-up Table 17 */ - kPLU_LUT_18 = 18U, /*!< 5-input Look-up Table 18 */ - kPLU_LUT_19 = 19U, /*!< 5-input Look-up Table 19 */ - kPLU_LUT_20 = 20U, /*!< 5-input Look-up Table 20 */ - kPLU_LUT_21 = 21U, /*!< 5-input Look-up Table 21 */ - kPLU_LUT_22 = 22U, /*!< 5-input Look-up Table 22 */ - kPLU_LUT_23 = 23U, /*!< 5-input Look-up Table 23 */ - kPLU_LUT_24 = 24U, /*!< 5-input Look-up Table 24 */ - kPLU_LUT_25 = 25U /*!< 5-input Look-up Table 25 */ -} plu_lut_index_t; - -/*! @brief Inputs of LUT. 5 input present for each LUT. */ -typedef enum _plu_lut_in_index -{ - kPLU_LUT_IN_0 = 0U, /*!< LUT input 0 */ - kPLU_LUT_IN_1 = 1U, /*!< LUT input 1 */ - kPLU_LUT_IN_2 = 2U, /*!< LUT input 2 */ - kPLU_LUT_IN_3 = 3U, /*!< LUT input 3 */ - kPLU_LUT_IN_4 = 4U /*!< LUT input 4 */ -} plu_lut_in_index_t; - -/*! @brief Available sources of LUT input */ -typedef enum _plu_lut_input_source -{ - kPLU_LUT_IN_SRC_PLU_IN_0 = 0U, /*!< Select PLU input 0 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_1 = 1U, /*!< Select PLU input 1 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_2 = 2U, /*!< Select PLU input 2 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_3 = 3U, /*!< Select PLU input 3 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_4 = 4U, /*!< Select PLU input 4 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_5 = 5U, /*!< Select PLU input 5 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_0 = 6U, /*!< Select LUT output 0 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_1 = 7U, /*!< Select LUT output 1 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_2 = 8U, /*!< Select LUT output 2 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_3 = 9U, /*!< Select LUT output 3 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_4 = 10U, /*!< Select LUT output 4 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_5 = 11U, /*!< Select LUT output 5 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_6 = 12U, /*!< Select LUT output 6 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_7 = 13U, /*!< Select LUT output 7 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_8 = 14U, /*!< Select LUT output 8 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_9 = 15U, /*!< Select LUT output 9 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_10 = 16U, /*!< Select LUT output 10 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_11 = 17U, /*!< Select LUT output 11 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_12 = 18U, /*!< Select LUT output 12 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_13 = 19U, /*!< Select LUT output 13 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_14 = 20U, /*!< Select LUT output 14 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_15 = 21U, /*!< Select LUT output 15 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_16 = 22U, /*!< Select LUT output 16 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_17 = 23U, /*!< Select LUT output 17 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_18 = 24U, /*!< Select LUT output 18 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_19 = 25U, /*!< Select LUT output 19 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_20 = 26U, /*!< Select LUT output 20 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_21 = 27U, /*!< Select LUT output 21 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_22 = 28U, /*!< Select LUT output 22 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_23 = 29U, /*!< Select LUT output 23 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_24 = 30U, /*!< Select LUT output 24 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_25 = 31U, /*!< Select LUT output 25 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_FLIPFLOP_0 = 32U, /*!< Select Flip-Flops state 0 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_FLIPFLOP_1 = 33U, /*!< Select Flip-Flops state 1 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_FLIPFLOP_2 = 34U, /*!< Select Flip-Flops state 2 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_FLIPFLOP_3 = 35U /*!< Select Flip-Flops state 3 to be connected to LUTn Input x */ -} plu_lut_input_source_t; - -/*! @brief PLU output multiplexer registers */ -typedef enum _plu_output_index -{ - kPLU_OUTPUT_0 = 0U, /*!< PLU OUTPUT 0 */ - kPLU_OUTPUT_1 = 1U, /*!< PLU OUTPUT 1 */ - kPLU_OUTPUT_2 = 2U, /*!< PLU OUTPUT 2 */ - kPLU_OUTPUT_3 = 3U, /*!< PLU OUTPUT 3 */ - kPLU_OUTPUT_4 = 4U, /*!< PLU OUTPUT 4 */ - kPLU_OUTPUT_5 = 5U, /*!< PLU OUTPUT 5 */ - kPLU_OUTPUT_6 = 6U, /*!< PLU OUTPUT 6 */ - kPLU_OUTPUT_7 = 7U /*!< PLU OUTPUT 7 */ -} plu_output_index_t; - -/*! @brief Available sources of PLU output */ -typedef enum _plu_output_source -{ - kPLU_OUT_SRC_LUT_0 = 0U, /*!< Select LUT0 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_1 = 1U, /*!< Select LUT1 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_2 = 2U, /*!< Select LUT2 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_3 = 3U, /*!< Select LUT3 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_4 = 4U, /*!< Select LUT4 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_5 = 5U, /*!< Select LUT5 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_6 = 6U, /*!< Select LUT6 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_7 = 7U, /*!< Select LUT7 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_8 = 8U, /*!< Select LUT8 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_9 = 9U, /*!< Select LUT9 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_10 = 10U, /*!< Select LUT10 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_11 = 11U, /*!< Select LUT11 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_12 = 12U, /*!< Select LUT12 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_13 = 13U, /*!< Select LUT13 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_14 = 14U, /*!< Select LUT14 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_15 = 15U, /*!< Select LUT15 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_16 = 16U, /*!< Select LUT16 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_17 = 17U, /*!< Select LUT17 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_18 = 18U, /*!< Select LUT18 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_19 = 19U, /*!< Select LUT19 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_20 = 20U, /*!< Select LUT20 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_21 = 21U, /*!< Select LUT21 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_22 = 22U, /*!< Select LUT22 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_23 = 23U, /*!< Select LUT23 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_24 = 24U, /*!< Select LUT24 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_25 = 25U, /*!< Select LUT25 output to be connected to PLU output */ - kPLU_OUT_SRC_FLIPFLOP_0 = 26U, /*!< Select Flip-Flops state(0) to be connected to PLU output */ - kPLU_OUT_SRC_FLIPFLOP_1 = 27U, /*!< Select Flip-Flops state(1) to be connected to PLU output */ - kPLU_OUT_SRC_FLIPFLOP_2 = 28U, /*!< Select Flip-Flops state(2) to be connected to PLU output */ - kPLU_OUT_SRC_FLIPFLOP_3 = 29U /*!< Select Flip-Flops state(3) to be connected to PLU output */ -} plu_output_source_t; - -#if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG - -/*! @brief The enumerator of PLU Interrupt. */ -enum _plu_interrupt_mask -{ - kPLU_OUTPUT_0_INTERRUPT_MASK = 1 << 0, /*!< Select PLU output 0 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_1_INTERRUPT_MASK = 1 << 1, /*!< Select PLU output 1 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_2_INTERRUPT_MASK = 1 << 2, /*!< Select PLU output 2 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_3_INTERRUPT_MASK = 1 << 3, /*!< Select PLU output 3 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_4_INTERRUPT_MASK = 1 << 4, /*!< Select PLU output 4 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_5_INTERRUPT_MASK = 1 << 5, /*!< Select PLU output 5 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_6_INTERRUPT_MASK = 1 << 6, /*!< Select PLU output 6 contribute to interrupt/wake-up generation */ - kPLU_OUTPUT_7_INTERRUPT_MASK = 1 << 7 /*!< Select PLU output 7 contribute to interrupt/wake-up generation */ -}; - -/*! @brief Control input of the PLU, add filtering for glitch. */ -typedef enum _plu_wakeint_filter_mode -{ - kPLU_WAKEINT_FILTER_MODE_BYPASS = 0U, /*!< Select Bypass mode */ - kPLU_WAKEINT_FILTER_MODE_1_CLK_PERIOD = 1U, /*!< Filter 1 clock period */ - kPLU_WAKEINT_FILTER_MODE_2_CLK_PERIOD = 2U, /*!< Filter 2 clock period */ - kPLU_WAKEINT_FILTER_MODE_3_CLK_PERIOD = 3U /*!< Filter 3 clock period */ -} plu_wakeint_filter_mode_t; - -/*! @brief Clock source for filter mode. */ -typedef enum _plu_wakeint_filter_clock_source -{ - kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC = 0U, /*!< Select the 1MHz low-power oscillator as the filter clock */ - kPLU_WAKEINT_FILTER_CLK_SRC_12MHZ_FRO = 1U, /*!< Select the 12MHz FRO as the filer clock */ - kPLU_WAKEINT_FILTER_CLK_SRC_ALT = 2U /*!< Select a third clock source */ -} plu_wakeint_filter_clock_source_t; - -/*! @brief Wake configuration. */ -typedef struct _plu_wakeint_config -{ - plu_wakeint_filter_mode_t filterMode; /*!< Filter Mode. */ - plu_wakeint_filter_clock_source_t clockSource; /*!< The clock source for filter mode. */ -} plu_wakeint_config_t; -#endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Enable the PLU clock and reset the module. - * - * @note This API should be called at the beginning of the application using the PLU driver. - * - * @param base PLU peripheral base address - */ -void PLU_Init(PLU_Type *base); - -/*! - * @brief Gate the PLU clock - * - * @param base PLU peripheral base address - */ -void PLU_Deinit(PLU_Type *base); - -/*! @}*/ - -/*! - * @name Set input/output source and Truth Table - * @{ - */ - -/*! - * @brief Set Input source of LUT. - * - * Note: An external clock must be applied to the PLU_CLKIN input when using FFs. - * For each LUT, the slot associated with the output from LUTn itself is tied low. - * - * @param base PLU peripheral base address. - * @param lutIndex LUT index (see @ref plu_lut_index_t typedef enumeration). - * @param lutInIndex LUT input index (see @ref plu_lut_in_index_t typedef enumeration). - * @param inputSrc LUT input source (see @ref plu_lut_input_source_t typedef enumeration). - */ -static inline void PLU_SetLutInputSource(PLU_Type *base, - plu_lut_index_t lutIndex, - plu_lut_in_index_t lutInIndex, - plu_lut_input_source_t inputSrc) -{ - PLU->LUT[lutIndex].INP_MUX[lutInIndex] = (uint32_t)inputSrc; -} - -/*! - * @brief Set Output source of PLU. - * - * Note: An external clock must be applied to the PLU_CLKIN input when using FFs. - * - * @param base PLU peripheral base address. - * @param outputIndex PLU output index (see @ref plu_output_index_t typedef enumeration). - * @param outputSrc PLU output source (see @ref plu_output_source_t typedef enumeration). - */ -static inline void PLU_SetOutputSource(PLU_Type *base, plu_output_index_t outputIndex, plu_output_source_t outputSrc) -{ - base->OUTPUT_MUX[outputIndex] = (uint32_t)outputSrc; -} - -/*! - * @brief Set Truth Table of LUT. - * - * @param base PLU peripheral base address. - * @param lutIndex LUT index (see @ref plu_lut_index_t typedef enumeration). - * @param truthTable Truth Table value. - */ -static inline void PLU_SetLutTruthTable(PLU_Type *base, plu_lut_index_t lutIndex, uint32_t truthTable) -{ - base->LUT_TRUTH[lutIndex] = truthTable; -} - -/*! @}*/ - -/*! - * @name Read current Output State - * @{ - */ - -/*! - * @brief Read the current state of the 8 designated PLU Outputs. - * - * Note: The PLU bus clock must be re-enabled prior to reading the Outpus Register if PLU bus clock is - * shut-off. - * - * @param base PLU peripheral base address. - * @return Current PLU output state value. - */ -static inline uint32_t PLU_ReadOutputState(PLU_Type *base) -{ - return (base->OUTPUTS & PLU_OUTPUTS_OUTPUT_STATE_MASK); -} - -/*! @}*/ - -#if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG -/*! - * @name Wake-up/Interrupt Control - * @{ - */ - -/*! - * @brief Gets an available pre-defined settings for wakeup/interrupt control. - * - * This function initializes the initial configuration structure with an available settings. The default values are: - * @code - * config->filterMode = kPLU_WAKEINT_FILTER_MODE_BYPASS; - * config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC; - * @endcode - * @param config Pointer to configuration structure. - */ -void PLU_GetDefaultWakeIntConfig(plu_wakeint_config_t *config); - -/*! - * @brief Enable PLU outputs wakeup/interrupt request. - * - * This function enables Any of the eight selected PLU outputs to contribute to an asynchronous wake-up or an interrupt - * request. - * - * Note: If a PLU_CLKIN is provided, the raw wake-up/interrupt request will be set on the rising-edge of the PLU_CLKIN - * whenever the raw request signal is high. This registered signal will be glitch-free and just use the default wakeint - * config by PLU_GetDefaultWakeIntConfig(). If not, have to specify the filter mode and clock source to eliminate the - * glitches caused by long and widely disparate delays through the network of LUTs making up the PLU. This way may - * increase power consumption in low-power operating modes and inject delay before the wake-up/interrupt request is - * generated. - * - * @param base PLU peripheral base address. - * @param interruptMask PLU interrupt mask (see @ref _plu_interrupt_mask enumeration). - * @param config Pointer to configuration structure (see @ref plu_wakeint_config_t typedef enumeration) - */ -void PLU_EnableWakeIntRequest(PLU_Type *base, uint32_t interruptMask, const plu_wakeint_config_t *config); - -/*! - * @brief Latch an interrupt - * - * This function latches the interrupt and then it can be cleared with PLU_ClearLatchedInterrupt(). - * - * Note: This mode is not compatible with use of the glitch filter. If this bit is set, the FILTER MODE should be set - * to kPLU_WAKEINT_FILTER_MODE_BYPASS (Bypass Mode) and PLU_CLKIN should be provided. If this bit is set, the - * wake-up/interrupt request will be set on the rising-edge of PLU_CLKIN whenever the raw wake-up/interrupt signal is - * high. The request must be cleared by software. - * - * @param base PLU peripheral base address. - */ -static inline void PLU_LatchInterrupt(PLU_Type *base) -{ - base->WAKEINT_CTRL |= PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK; -} - -/*! - * @brief Clear the latched interrupt - * - * This function clears the wake-up/interrupt request flag latched by PLU_LatchInterrupt() - * - * Note: It is not necessary for the PLU bus clock to be enabled in order to write-to or read-back this bit. - * - * @param base PLU peripheral base address. - */ -void PLU_ClearLatchedInterrupt(PLU_Type *base); - -/*! @}*/ -#endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_PLU_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_power.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_power.c deleted file mode 100644 index f5204543836..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_power.c +++ /dev/null @@ -1,1831 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_common.h" -#include "fsl_power.h" -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.power" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/** @brief Low Power main structure */ -typedef enum -{ - VD_AON = 0x0, /*!< Digital Always On power domain */ - VD_MEM = 0x1, /*!< Memories (SRAM) power domain */ - VD_DCDC = 0x2, /*!< Core logic power domain */ - VD_DEEPSLEEP = 0x3 /*!< Core logic power domain */ -} LPC_POWER_DOMAIN_T; - -/** - * @brief LDO_FLASH_NV & LDO_USB voltage settings - */ -typedef enum _v_flashnv -{ - V_LDOFLASHNV_1P650 = 0, /*!< 0.95 V */ - V_LDOFLASHNV_1P700 = 1, /*!< 0.975 V */ - V_LDOFLASHNV_1P750 = 2, /*!< 1 V */ - V_LDOFLASHNV_0P800 = 3, /*!< 1.025 V */ - V_LDOFLASHNV_1P850 = 4, /*!< 1.050 V */ - V_LDOFLASHNV_1P900 = 5, /*!< 1.075 V */ - V_LDOFLASHNV_1P950 = 6, /*!< 1.1 V */ - V_LDOFLASHNV_2P000 = 7 /*!< 1.125 V */ -} v_flashnv_t; - -/** @brief Low Power main structure */ -typedef struct -{ /* */ - __IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */ - __IO uint32_t PDCTRL0; /*!< Power Down control : controls power of various modules - in the different Low power modes, including ROM */ - __IO uint32_t SRAMRETCTRL; /*!< Power Down control : controls power SRAM instances - in the different Low power modes */ - __IO uint32_t CPURETCTRL; /*!< CPU0 retention control : controls CPU retention parameters in POWER DOWN modes */ - __IO uint64_t VOLTAGE; /*!< Voltage control in Low Power Modes */ - __IO uint64_t WAKEUPSRC; /*!< Wake up sources control for sleepcon */ - __IO uint64_t WAKEUPINT; /*!< Wake up sources control for ARM */ - __IO uint32_t HWWAKE; /*!< Interrupt that can postpone power down modes - in case an interrupt is pending when the processor request deepsleep */ - __IO uint32_t WAKEUPIOSRC; /*!< Wake up I/O sources in DEEP POWER DOWN mode */ - __IO uint32_t TIMERCFG; /*!< Wake up timers configuration */ - __IO uint32_t TIMERCOUNT; /*!< Wake up Timer count*/ - __IO uint32_t POWERCYCLE; /*!< Cancels entry in Low Power mode if set with 0xDEADABBA (might be used by some - interrupt handlers)*/ -} LPC_LOWPOWER_T; - -/* */ -#define LOWPOWER_POWERCYCLE_CANCELLED 0xDEADABBAUL /*!< */ - -/** - * @brief SRAM Low Power Modes - */ -#define LOWPOWER_SRAM_LPMODE_MASK (0xFUL) -#define LOWPOWER_SRAM_LPMODE_ACTIVE (0x6UL) /*!< SRAM functional mode */ -#define LOWPOWER_SRAM_LPMODE_SLEEP (0xFUL) /*!< SRAM Sleep mode (Data retention, fast wake up) */ -#define LOWPOWER_SRAM_LPMODE_DEEPSLEEP (0x8UL) /*!< SRAM Deep Sleep mode (Data retention, slow wake up) */ -#define LOWPOWER_SRAM_LPMODE_SHUTDOWN (0x9UL) /*!< SRAM Shut Down mode (no data retention) */ -#define LOWPOWER_SRAM_LPMODE_POWERUP (0xAUL) /*!< SRAM is powering up */ - -/** - * @brief Wake up timers configuration in Low Power Modes - */ -#define LOWPOWER_TIMERCFG_CTRL_INDEX 0 -#define LOWPOWER_TIMERCFG_CTRL_MASK (0x1UL << LOWPOWER_TIMERCFG_CTRL_INDEX) -#define LOWPOWER_TIMERCFG_TIMER_INDEX 1 -#define LOWPOWER_TIMERCFG_TIMER_MASK (0x7UL << LOWPOWER_TIMERCFG_TIMER_INDEX) -#define LOWPOWER_TIMERCFG_OSC32K_INDEX 4 -#define LOWPOWER_TIMERCFG_OSC32K_MASK (0x1UL << LOWPOWER_TIMERCFG_OSC32K_INDEX) - -#define LOWPOWER_TIMERCFG_CTRL_DISABLE 0 /*!< Wake Timer Disable */ -#define LOWPOWER_TIMERCFG_CTRL_ENABLE 1 /*!< Wake Timer Enable */ - -/** - * @brief Primary Wake up timers configuration in Low Power Modes - */ -#define LOWPOWER_TIMERCFG_TIMER_RTC1KHZ 0 /*!< 1 KHz Real Time Counter (RTC) used as wake up source */ -#define LOWPOWER_TIMERCFG_TIMER_RTC1HZ 1 /*!< 1 Hz Real Time Counter (RTC) used as wake up source */ -#define LOWPOWER_TIMERCFG_TIMER_OSTIMER 2 /*!< OS Event Timer used as wake up source */ - -#define LOWPOWER_TIMERCFG_OSC32K_FRO32KHZ 0 /*!< Wake up Timers uses FRO 32 KHz as clock source */ -#define LOWPOWER_TIMERCFG_OSC32K_XTAL32KHZ 1 /*!< Wake up Timers uses Chrystal 32 KHz as clock source */ - -//! @brief Interface for lowpower functions -typedef struct LowpowerDriverInterface -{ - void (*power_cycle_cpu_and_flash)(void); - void (*set_lowpower_mode)(LPC_LOWPOWER_T *p_lowpower_cfg); -} lowpower_driver_interface_t; - -/**< DCDC Power Profiles */ -typedef enum -{ - DCDC_POWER_PROFILE_LOW, /**< LOW (for CPU frequencies below DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ) */ - DCDC_POWER_PROFILE_MEDIUM, /**< MEDIUM (for CPU frequencies between DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ and - DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ) */ - DCDC_POWER_PROFILE_HIGH, /**< HIGH (for CPU frequencies between DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ and - DCDC_POWER_PROFILE_HIGH_MAX_FREQ_HZ) */ -} lowpower_dcdc_power_profile_enum; - -/**< Manufacturing Process Corners */ -typedef enum -{ - PROCESS_CORNER_SSS, /**< Slow Corner Process */ - PROCESS_CORNER_NNN, /**< Nominal Corner Process */ - PROCESS_CORNER_FFF, /**< Fast Corner Process */ - PROCESS_CORNER_OTHERS, /**< SFN, SNF, NFS, Poly Res ... Corner Process */ -} lowpower_process_corner_enum; - -/** - * @brief DCDC voltage settings - */ -typedef enum _v_dcdc -{ - V_DCDC_0P950 = 0, /*!< 0.95 V */ - V_DCDC_0P975 = 1, /*!< 0.975 V */ - V_DCDC_1P000 = 2, /*!< 1 V */ - V_DCDC_1P025 = 3, /*!< 1.025 V */ - V_DCDC_1P050 = 4, /*!< 1.050 V */ - V_DCDC_1P075 = 5, /*!< 1.075 V */ - V_DCDC_1P100 = 6, /*!< 1.1 V */ - V_DCDC_1P125 = 7, /*!< 1.125 V */ - V_DCDC_1P150 = 8, /*!< 1.150 V */ - V_DCDC_1P175 = 9, /*!< 1.175 V */ - V_DCDC_1P200 = 10 /*!< 1.2 V */ -} v_dcdc_t; - -/** - * @brief Deep Sleep LDO voltage settings - */ -typedef enum _v_deepsleep -{ - V_DEEPSLEEP_0P900 = 0, /*!< 0.9 V */ - V_DEEPSLEEP_0P925 = 1, /*!< 0.925 V */ - V_DEEPSLEEP_0P950 = 2, /*!< 0.95 V */ - V_DEEPSLEEP_0P975 = 3, /*!< 0.975 V */ - V_DEEPSLEEP_1P000 = 4, /*!< 1.000 V */ - V_DEEPSLEEP_1P025 = 5, /*!< 1.025 V */ - V_DEEPSLEEP_1P050 = 6, /*!< 1.050 V */ - V_DEEPSLEEP_1P075 = 7 /*!< 1.075 V */ -} v_deepsleep_t; - -/** - * @brief Always On and Memories LDO voltage settings - */ -typedef enum _v_ao -{ - V_AO_0P700 = 1, /*!< 0.7 V */ - V_AO_0P725 = 2, /*!< 0.725 V */ - V_AO_0P750 = 3, /*!< 0.75 V */ - V_AO_0P775 = 4, /*!< 0.775 V */ - V_AO_0P800 = 5, /*!< 0.8 V */ - V_AO_0P825 = 6, /*!< 0.825 V */ - V_AO_0P850 = 7, /*!< 0.85 V */ - V_AO_0P875 = 8, /*!< 0.875 V */ - V_AO_0P900 = 9, /*!< 0.9 V */ - V_AO_0P960 = 10, /*!< 0.96 V */ - V_AO_0P970 = 11, /*!< 0.97 V */ - V_AO_0P980 = 12, /*!< 0.98 V */ - V_AO_0P990 = 13, /*!< 0.99 V */ - V_AO_1P000 = 14, /*!< 1 V */ - V_AO_1P010 = 15, /*!< 1.01 V */ - V_AO_1P020 = 16, /*!< 1.02 V */ - V_AO_1P030 = 17, /*!< 1.03 V */ - V_AO_1P040 = 18, /*!< 1.04 V */ - V_AO_1P050 = 19, /*!< 1.05 V */ - V_AO_1P060 = 20, /*!< 1.06 V */ - V_AO_1P070 = 21, /*!< 1.07 V */ - V_AO_1P080 = 22, /*!< 1.08 V */ - V_AO_1P090 = 23, /*!< 1.09 V */ - V_AO_1P100 = 24, /*!< 1.1 V */ - V_AO_1P110 = 25, /*!< 1.11 V */ - V_AO_1P120 = 26, /*!< 1.12 V */ - V_AO_1P130 = 27, /*!< 1.13 V */ - V_AO_1P140 = 28, /*!< 1.14 V */ - V_AO_1P150 = 29, /*!< 1.15 V */ - V_AO_1P160 = 30, /*!< 1.16 V */ - V_AO_1P220 = 31 /*!< 1.22 V */ -} v_ao_t; - -/* Low Power modes */ -#define LOWPOWER_CFG_LPMODE_INDEX 0 -#define LOWPOWER_CFG_LPMODE_MASK (0x3UL << LOWPOWER_CFG_LPMODE_INDEX) -#define LOWPOWER_CFG_SELCLOCK_INDEX 2 -#define LOWPOWER_CFG_SELCLOCK_MASK (0x1UL << LOWPOWER_CFG_SELCLOCK_INDEX) -#define LOWPOWER_CFG_SELMEMSUPPLY_INDEX 3 -#define LOWPOWER_CFG_SELMEMSUPPLY_MASK (0x1UL << LOWPOWER_CFG_SELMEMSUPPLY_INDEX) -#define LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX 4 -#define LOWPOWER_CFG_MEMLOWPOWERMODE_MASK (0x1UL << LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX) -#define LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX 5 -#define LOWPOWER_CFG_LDODEEPSLEEPREF_MASK (0x1UL << LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX) - -#define LOWPOWER_CFG_LPMODE_ACTIVE 0 /*!< ACTIVE mode */ -#define LOWPOWER_CFG_LPMODE_DEEPSLEEP 1 /*!< DEEP SLEEP mode */ -#define LOWPOWER_CFG_LPMODE_POWERDOWN 2 /*!< POWER DOWN mode */ -#define LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN 3 /*!< DEEP POWER DOWN mode */ -#define LOWPOWER_CFG_LPMODE_SLEEP 4 /*!< SLEEP mode */ - -#define LOWPOWER_CFG_SELCLOCK_1MHZ 0 /*!< The 1 MHz clock is used during the configuration of the PMC */ -#define LOWPOWER_CFG_SELCLOCK_12MHZ \ - 1 /*!< The 12 MHz clock is used during the configuration of the PMC (to speed up PMC configuration process)*/ - -#define LOWPOWER_CFG_SELMEMSUPPLY_LDOMEM 0 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_MEM */ -#define LOWPOWER_CFG_SELMEMSUPPLY_LDODEEPSLEEP \ - 1 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_DEEP_SLEEP (or DCDC) */ - -#define LOWPOWER_CFG_MEMLOWPOWERMODE_SOURCEBIASING \ - 0 /*!< All SRAM instances use "Source Biasing" as low power mode technic (it is recommended to set LDO_MEM as high \ - as possible -- 1.1V typical -- during low power mode) */ -#define LOWPOWER_CFG_MEMLOWPOWERMODE_VOLTAGESCALING \ - 1 /*!< All SRAM instances use "Voltage Scaling" as low power mode technic (it is recommended to set LDO_MEM as low \ - as possible -- down to 0.7V -- during low power mode) */ - -#define LOWPOWER_CFG_LDODEEPSLEEPREF_FLASHBUFFER 0 /*!< LDO DEEP SLEEP uses Flash Buffer as reference */ -#define LOWPOWER_CFG_LDODEEPSLEEPREF_BANDGAG0P8V 1 /*!< LDO DEEP SLEEP uses Band Gap 0.8V as reference */ - -/* CPU Retention Control*/ -#define LOWPOWER_CPURETCTRL_ENA_INDEX 0 -#define LOWPOWER_CPURETCTRL_ENA_MASK (0x1UL << LOWPOWER_CPURETCTRL_ENA_INDEX) -#define LOWPOWER_CPURETCTRL_MEMBASE_INDEX 1 -#define LOWPOWER_CPURETCTRL_MEMBASE_MASK (0x1FFFUL << LOWPOWER_CPURETCTRL_MEMBASE_INDEX) -#define LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX 14 -#define LOWPOWER_CPURETCTRL_RETDATALENGTH_MASK (0x3FFUL << LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX) - -/* Voltgae setting*/ -#define DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ \ - (100000000U) /* Maximum System Frequency allowed with DCDC Power Profile LOW */ -#define DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ \ - (130000000U) /* Maximum System Frequency allowed with DCDC Power Profile MEDIUM */ -#define DCDC_POWER_PROFILE_HIGH_MAX_FREQ_HZ \ - (150000000U) /* Maximum System Frequency allowed with DCDC Power Profile HIGH */ -#define PROCESS_NNN_AVG_HZ (19300000U) /* Average Ring OScillator value for Nominal (NNN) Manufacturing Process */ -#define PROCESS_NNN_STD_HZ \ - (400000U) /* Standard Deviation Ring OScillator value for Nominal (NNN) Manufacturing Process */ -#define PROCESS_NNN_LIMITS \ - (6U) /* Nominal (NNN) Manufacturing Process Ring Oscillator values limit (with respect to the Average value) */ -#define PROCESS_NNN_MIN_HZ \ - (PROCESS_NNN_AVG_HZ - \ - (PROCESS_NNN_LIMITS * \ - PROCESS_NNN_STD_HZ)) /* Minimum Ring OScillator value for Nominal (NNN) Manufacturing Process */ -#define PROCESS_NNN_MAX_HZ \ - (PROCESS_NNN_AVG_HZ + \ - (PROCESS_NNN_LIMITS * \ - PROCESS_NNN_STD_HZ)) /* Maximum Ring OScillator value for Nominal (NNN) Manufacturing Process */ -#define VOLTAGE_SSS_LOW_MV (1075U) /* Voltage Settings for : Process=SSS, DCDC Power Profile=LOW */ -#define VOLTAGE_SSS_MED_MV (1150U) /* Voltage Settings for : Process=SSS, DCDC Power Profile=MEDIUM */ -#define VOLTAGE_SSS_HIG_MV (1200U) /* Voltage Settings for : Process=SSS, DCDC Power Profile=HIGH */ -#define VOLTAGE_NNN_LOW_MV (1000U) /* Voltage Settings for : Process=NNN, DCDC Power Profile=LOW */ -#define VOLTAGE_NNN_MED_MV (1100U) /* Voltage Settings for : Process=NNN, DCDC Power Profile=MEDIUM */ -#define VOLTAGE_NNN_HIG_MV (1150U) /* Voltage Settings for : Process=NNN, DCDC Power Profile=HIGH */ -#define VOLTAGE_FFF_LOW_MV (1000U) /* Voltage Settings for : Process=FFF, DCDC Power Profile=LOW */ -#define VOLTAGE_FFF_MED_MV (1025U) /* Voltage Settings for : Process=FFF, DCDC Power Profile=MEDIUM */ -#define VOLTAGE_FFF_HIG_MV (1050U) /* Voltage Settings for : Process=FFF, DCDC Power Profile=HIGH */ - -/** - * @brief LDO Voltage control in Low Power Modes - */ -#define LOWPOWER_VOLTAGE_LDO_PMU_INDEX 0 -#define LOWPOWER_VOLTAGE_LDO_PMU_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) -#define LOWPOWER_VOLTAGE_LDO_MEM_INDEX 5 -#define LOWPOWER_VOLTAGE_LDO_MEM_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) -#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX 10 -#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_MASK (0x7ULL << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX) -#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX 19 -#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) -#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX 24 -#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) -#define LOWPOWER_VOLTAGE_DCDC_INDEX 29 -#define LOWPOWER_VOLTAGE_DCDC_MASK (0xFULL << LOWPOWER_VOLTAGE_DCDC_INDEX) - -/*! @brief set and clear bit MACRO's. */ -#define U32_SET_BITS(P, B) ((*(uint32_t *)P) |= (B)) -#define U32_CLR_BITS(P, B) ((*(uint32_t *)P) &= ~(B)) -/* Return values from Config (N-2) page of flash */ -#define GET_16MXO_TRIM() (*(uint32_t *)0x9FCC8) -#define GET_32KXO_TRIM() (*(uint32_t *)0x9FCCC) - -#define CPU_RETENTION_RAMX_STORAGE_START_ADDR (0x04006000) - -#define XO_SLAVE_EN (1) -/******************************************************************************* - * Codes - ******************************************************************************/ - -/******************************************************************************* - * LOCAL FUNCTIONS PROTOTYPES - ******************************************************************************/ -static void lf_get_deepsleep_core_supply_cfg(uint32_t exclude_from_pd, uint32_t *dcdc_voltage); -static uint32_t lf_set_ldo_ao_ldo_mem_voltage(uint32_t p_lp_mode, uint32_t p_dcdc_voltage); -static uint32_t lf_wakeup_io_ctrl(uint32_t p_wakeup_io_ctrl); -static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity); - -static void lowpower_set_dcdc_power_profile(lowpower_dcdc_power_profile_enum dcdc_power_profile); -static lowpower_process_corner_enum lowpower_get_part_process_corner(void); -static void lowpower_set_voltage_for_process(lowpower_dcdc_power_profile_enum dcdc_power_profile); - -/** - * @brief Configures and enters in low power mode - * @param p_lowpower_cfg: pointer to a structure that contains all low power mode parameters - * @return Nothing - * - * !!! IMPORTANT NOTES : - * 1 - CPU Interrupt Enable registers are updated with p_lowpower_cfg->WAKEUPINT. They are NOT restored by the - * API. - * 2 - The Non Maskable Interrupt (NMI) should be disable before calling this API (otherwise, there is a risk - * of Dead Lock). - * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip - * reset) - */ -static void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg); - -/** - * @brief - * @param - * @return - */ -static void lf_set_dcdc_power_profile_low(void) -{ -#define DCDC_POWER_PROFILE_LOW_0_ADDRS (0x9FCE0U) -#define DCDC_POWER_PROFILE_LOW_1_ADDRS (0x9FCE4U) - - uint32_t dcdcTrimValue0 = (*((volatile unsigned int *)(DCDC_POWER_PROFILE_LOW_0_ADDRS))); - uint32_t dcdcTrimValue1 = (*((volatile unsigned int *)(DCDC_POWER_PROFILE_LOW_1_ADDRS))); - - if (0UL != (dcdcTrimValue0 & 0x1UL)) - { - PMC->DCDC0 = dcdcTrimValue0 >> 1; - PMC->DCDC1 = dcdcTrimValue1; - } -} - -/** - * @brief Configures and enters in low power mode - * @param : p_lowpower_cfg - * @return Nothing - */ -static void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg) -{ - lowpower_driver_interface_t *s_lowpowerDriver; - /* Judging the core and call the corresponding API base address*/ - if (0UL == Chip_GetVersion()) - { - s_lowpowerDriver = (lowpower_driver_interface_t *)(0x130010d4UL); - } - else - { - s_lowpowerDriver = (lowpower_driver_interface_t *)(0x13001204UL); - } - /* PMC clk set to 12 MHZ */ - p_lowpower_cfg->CFG |= (uint32_t)LOWPOWER_CFG_SELCLOCK_12MHZ << LOWPOWER_CFG_SELCLOCK_INDEX; - - /* Enable Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP - * POWER DOWN) and Hardware Pin reset */ - PMC->REFFASTWKUP = (PMC->REFFASTWKUP & (~PMC_REFFASTWKUP_LPWKUP_MASK) & (~PMC_REFFASTWKUP_HWWKUP_MASK)) | - PMC_REFFASTWKUP_LPWKUP(1) | PMC_REFFASTWKUP_HWWKUP(1); - - /* SRAM uses Voltage Scaling in all Low Power modes */ - PMC->SRAMCTRL = (PMC->SRAMCTRL & (~PMC_SRAMCTRL_SMB_MASK)) | PMC_SRAMCTRL_SMB(3); - - /* CPU Retention configuration : preserve the value of FUNCRETENTIONCTRL.RET_LENTH which is a Hardware defined - * parameter. */ - p_lowpower_cfg->CPURETCTRL = (SYSCON->FUNCRETENTIONCTRL & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) | - (p_lowpower_cfg->CPURETCTRL & (~SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK)); - - /* Switch System Clock to FRO12Mhz (the configuration before calling this function will not be restored back) */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* Switch main clock to FRO12MHz */ - CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /* Main clock divided by 1 */ - SYSCON->FMCCR = (SYSCON->FMCCR & 0xFFFF0000UL) | 0x201AUL; /* Adjust FMC waiting time cycles */ - lf_set_dcdc_power_profile_low(); /* Align DCDC Power profile with the 12 MHz clock (DCDC Power Profile LOW) */ - - (*(s_lowpowerDriver->set_lowpower_mode))(p_lowpower_cfg); - - /* Restore the configuration of the MISCCTRL Register : LOWPWR_FLASH_BUF = 0, LDOMEMBLEEDDSLP = 0, LDOMEMHIGHZMODE = - * 0 */ - PMC->MISCCTRL &= (~PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK) & (~PMC_MISCCTRL_DISABLE_BLEED_MASK) & - (~PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK); -} - -/** - * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event - * @param None - * @return Nothing - */ -void POWER_CycleCpuAndFlash(void) -{ - /* Judging the core and call the corresponding API base address*/ - lowpower_driver_interface_t *s_lowpowerDriver; - if (0UL == Chip_GetVersion()) - { - s_lowpowerDriver = (lowpower_driver_interface_t *)(0x130010d4UL); - } - else - { - s_lowpowerDriver = (lowpower_driver_interface_t *)(0x13001204UL); - } - (*(s_lowpowerDriver->power_cycle_cpu_and_flash))(); -}; - -/** - * brief PMC Deep Sleep function call - * return nothing - */ -void POWER_EnterDeepSleep(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t hardware_wake_ctrl) -{ - LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ - uint32_t cpu0_nmi_enable; - uint32_t cpu0_int_enable_0; - uint32_t cpu0_int_enable_1; - uint32_t dcdc_voltage; - uint32_t pmc_reset_ctrl; - /* Clear Low Power Mode configuration variable */ - (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); - - /* Configure Low Power Mode configuration variable */ - lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPSLEEP - << LOWPOWER_CFG_LPMODE_INDEX; /* DEEPSLEEP mode */ - - lf_get_deepsleep_core_supply_cfg(exclude_from_pd, &dcdc_voltage); - - if (((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_USB1_PHY) != 0UL) && - ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_LDOUSBHS) != 0UL)) - { - /* USB High Speed is required as wake-up source in Deep Sleep mode: make sure LDO FLASH NV stays powered during - * deep-sleep */ - exclude_from_pd = exclude_from_pd | (uint32_t)kPDRUNCFG_PD_LDOFLASHNV; - } - - /* DCDC will be always used during Deep Sleep (instead of LDO Deep Sleep); Make sure LDO MEM & Analog references - * will stay powered, Shut down ROM */ - lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd & ~(uint32_t)kPDRUNCFG_PD_DCDC & ~(uint32_t)kPDRUNCFG_PD_LDOMEM & - ~(uint32_t)kPDRUNCFG_PD_BIAS) | - (uint32_t)kPDRUNCFG_PD_LDODEEPSLEEP | (uint32_t)kPDRUNCFG_PD_ROM; - - /* Voltage control in DeepSleep Low Power Modes */ - /* The Memories Voltage settings below are for voltage scaling */ - lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_POWERDOWN, dcdc_voltage); - - /* SRAM retention control during POWERDOWN */ - lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; - - /* CPU Wake up & Interrupt sources control */ - lv_low_power_mode_cfg.WAKEUPINT = wakeup_interrupts; - lv_low_power_mode_cfg.WAKEUPSRC = wakeup_interrupts; - - /* Interrupts that allow DMA transfers with Flexcomm without waking up the Processor */ - if (0UL != (hardware_wake_ctrl & (LOWPOWER_HWWAKE_PERIPHERALS | LOWPOWER_HWWAKE_SDMA0 | LOWPOWER_HWWAKE_SDMA1))) - { - lv_low_power_mode_cfg.HWWAKE = (hardware_wake_ctrl & ~LOWPOWER_HWWAKE_FORCED) | LOWPOWER_HWWAKE_ENABLE_FRO192M; - } - - cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ - SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ - - /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power - * API */ - cpu0_int_enable_0 = NVIC->ISER[0]; - cpu0_int_enable_1 = NVIC->ISER[1]; - - pmc_reset_ctrl = PMC->RESETCTRL; - if (0UL != (pmc_reset_ctrl & PMC_RESETCTRL_BODCORERESETENABLE_MASK)) - { - /* BoD CORE reset is activated, so make sure BoD Core won't be shutdown */ - lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_BODCORE; - } - if (0UL != (pmc_reset_ctrl & PMC_RESETCTRL_BODVBATRESETENABLE_MASK)) - { - /* BoD VBAT reset is activated, so make sure BoD VBAT won't be shutdown */ - lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_BODVBAT; - } - - /* Enter low power mode */ - POWER_EnterLowPower(&lv_low_power_mode_cfg); - - /* Restore the configuration of the NMI Register */ - SYSCON->NMISRC |= cpu0_nmi_enable; - - /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the - * low power API */ - NVIC->ISER[0] = cpu0_int_enable_0; - NVIC->ISER[1] = cpu0_int_enable_1; -} - -/** - * brief PMC power Down function call - * return nothing - */ -void POWER_EnterPowerDown(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t cpu_retention_ctrl) -{ - LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ - uint32_t cpu0_nmi_enable; - uint32_t cpu0_int_enable_0; - uint32_t cpu0_int_enable_1; - uint64_t wakeup_src_int; - uint32_t pmc_reset_ctrl; - - uint32_t analog_ctrl_regs[12]; /* To store Analog Controller Regristers */ - - /* Clear Low Power Mode configuration variable */ - (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); - - /* Configure Low Power Mode configuration variable */ - lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_POWERDOWN - << LOWPOWER_CFG_LPMODE_INDEX; /* POWER DOWN mode */ - - /* Only FRO32K, XTAL32K, COMP, BIAS and LDO_MEM can be stay powered during POWERDOWN (valid from application point - * of view; Hardware allows BODVBAT, LDODEEPSLEEP and FRO1M to stay powered, that's why they are excluded below) */ - lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd) | (uint32_t)kPDRUNCFG_PD_BODVBAT | (uint32_t)kPDRUNCFG_PD_FRO1M | - (uint32_t)kPDRUNCFG_PD_LDODEEPSLEEP; - - /* SRAM retention control during POWERDOWN */ - lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; - - /* Sanity check: If retention is required for any of SRAM instances, make sure LDO MEM will stay powered */ - if ((sram_retention_ctrl & 0x7FFFUL) != 0UL) - { - lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_LDOMEM; - } - - /* Voltage control in Low Power Modes */ - /* The Memories Voltage settings below are for voltage scaling */ - lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_POWERDOWN, 0); - - /* CPU0 retention Ctrl. - * For the time being, we do not allow customer to relocate the CPU retention area in SRAMX, meaning that the - * retention area range is [0x0400_6000 - 0x0400_6600] (beginning of RAMX2) If required by customer, - * cpu_retention_ctrl[13:1] will be used for that to modify the default retention area - */ - lv_low_power_mode_cfg.CPURETCTRL = - (cpu_retention_ctrl & LOWPOWER_CPURETCTRL_ENA_MASK) | - ((((uint32_t)CPU_RETENTION_RAMX_STORAGE_START_ADDR >> 2UL) << LOWPOWER_CPURETCTRL_MEMBASE_INDEX) & - LOWPOWER_CPURETCTRL_MEMBASE_MASK); - if (0UL != (cpu_retention_ctrl & 0x1UL)) - { - /* CPU retention is required: store Analog Controller Registers */ - analog_ctrl_regs[0] = ANACTRL->FRO192M_CTRL; - analog_ctrl_regs[1] = ANACTRL->ANALOG_CTRL_CFG; - analog_ctrl_regs[2] = ANACTRL->ADC_CTRL; - analog_ctrl_regs[3] = ANACTRL->XO32M_CTRL; - analog_ctrl_regs[4] = ANACTRL->BOD_DCDC_INT_CTRL; - analog_ctrl_regs[5] = ANACTRL->RINGO0_CTRL; - analog_ctrl_regs[6] = ANACTRL->RINGO1_CTRL; - analog_ctrl_regs[7] = ANACTRL->RINGO2_CTRL; - analog_ctrl_regs[8] = ANACTRL->LDO_XO32M; - analog_ctrl_regs[9] = ANACTRL->AUX_BIAS; - analog_ctrl_regs[10] = ANACTRL->USBHS_PHY_CTRL; - analog_ctrl_regs[11] = ANACTRL->USBHS_PHY_TRIM; - } - - /* CPU Wake up & Interrupt sources control : only WAKEUP_GPIO_GLOBALINT0, WAKEUP_GPIO_GLOBALINT1, WAKEUP_FLEXCOMM3, - * WAKEUP_ACMP_CAPT, WAKEUP_RTC_LITE_ALARM_WAKEUP, WAKEUP_OS_EVENT_TIMER, WAKEUP_ALLWAKEUPIOS */ - wakeup_src_int = (uint64_t)(WAKEUP_GPIO_GLOBALINT0 | WAKEUP_GPIO_GLOBALINT1 | WAKEUP_FLEXCOMM3 | WAKEUP_ACMP_CAPT | - WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER | WAKEUP_ALLWAKEUPIOS); - lv_low_power_mode_cfg.WAKEUPINT = wakeup_interrupts & wakeup_src_int; - lv_low_power_mode_cfg.WAKEUPSRC = wakeup_interrupts & wakeup_src_int; - - cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ - SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ - - /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power - * API */ - cpu0_int_enable_0 = NVIC->ISER[0]; - cpu0_int_enable_1 = NVIC->ISER[1]; - - pmc_reset_ctrl = PMC->RESETCTRL; - /* Disable BoD VBAT and BoD Core resets */ - PMC->RESETCTRL = - pmc_reset_ctrl & (~(PMC_RESETCTRL_BODVBATRESETENABLE_MASK | PMC_RESETCTRL_BODCORERESETENABLE_MASK)); - - /* Enter low power mode */ - POWER_EnterLowPower(&lv_low_power_mode_cfg); - - /*** We'll reach this point in case of POWERDOWN with CPU retention or if the POWERDOWN has not been taken (for - instance because an interrupt is pending). In case of CPU retention, assumption is that the SRAM containing the - stack used to call this function shall be preserved during low power ***/ - - /* Restore the configuration of the NMI Register */ - SYSCON->NMISRC |= cpu0_nmi_enable; - - /* Restore PMC RESETCTRL register */ - PMC->RESETCTRL = pmc_reset_ctrl; - - /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the - * low power API */ - NVIC->ISER[0] = cpu0_int_enable_0; - NVIC->ISER[1] = cpu0_int_enable_1; - - if (0UL != (cpu_retention_ctrl & 0x1UL)) - { - /* Restore Analog Controller Registers */ - ANACTRL->FRO192M_CTRL = analog_ctrl_regs[0] | ANACTRL_FRO192M_CTRL_WRTRIM_MASK; - ANACTRL->ANALOG_CTRL_CFG = analog_ctrl_regs[1]; - ANACTRL->ADC_CTRL = analog_ctrl_regs[2]; - ANACTRL->XO32M_CTRL = analog_ctrl_regs[3]; - ANACTRL->BOD_DCDC_INT_CTRL = analog_ctrl_regs[4]; - ANACTRL->RINGO0_CTRL = analog_ctrl_regs[5]; - ANACTRL->RINGO1_CTRL = analog_ctrl_regs[6]; - ANACTRL->RINGO2_CTRL = analog_ctrl_regs[7]; - ANACTRL->LDO_XO32M = analog_ctrl_regs[8]; - ANACTRL->AUX_BIAS = analog_ctrl_regs[9]; - ANACTRL->USBHS_PHY_CTRL = analog_ctrl_regs[10]; - ANACTRL->USBHS_PHY_TRIM = analog_ctrl_regs[11]; - } -} - -/** - * brief PMC Deep Sleep Power Down function call - * return nothing - */ -void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t wakeup_io_ctrl) -{ - LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ - uint32_t cpu0_nmi_enable; - uint32_t cpu0_int_enable_0; - uint32_t cpu0_int_enable_1; - uint32_t pmc_reset_ctrl; - - /* Clear Low Power Mode configuration variable */ - (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); - - /* Configure Low Power Mode configuration variable */ - lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN - << LOWPOWER_CFG_LPMODE_INDEX; /* DEEP POWER DOWN mode */ - - /* Only FRO32K, XTAL32K and LDO_MEM can be stay powered during DEEPPOWERDOWN (valid from application point of view; - * Hardware allows BODVBAT, BIAS FRO1M and COMP to stay powered, that's why they are excluded below) */ - lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd) | (uint32_t)kPDRUNCFG_PD_BIAS | (uint32_t)kPDRUNCFG_PD_BODVBAT | - (uint32_t)kPDRUNCFG_PD_FRO1M | (uint32_t)kPDRUNCFG_PD_COMP; - - /* SRAM retention control during DEEPPOWERDOWN */ - sram_retention_ctrl = - sram_retention_ctrl & - (~(LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 | LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 | LOWPOWER_SRAMRETCTRL_RETEN_RAM00)); - - /* SRAM retention control during DEEPPOWERDOWN */ - lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; - - /* Sanity check: If retention is required for any of SRAM instances, make sure LDO MEM will stay powered */ - if ((sram_retention_ctrl & 0x7FFFUL) != 0UL) - { - lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_LDOMEM; - } - - /* Voltage control in Low Power Modes */ - /* The Memories Voltage settings below are for voltage scaling */ - lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN, 0); - - lv_low_power_mode_cfg.WAKEUPINT = - wakeup_interrupts & (WAKEUP_RTC_LITE_ALARM_WAKEUP | - WAKEUP_OS_EVENT_TIMER); /* CPU Wake up sources control : only WAKEUP_RTC_LITE_ALARM_WAKEUP, - WAKEUP_OS_EVENT_TIMER */ - lv_low_power_mode_cfg.WAKEUPSRC = - wakeup_interrupts & - (WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER | - WAKEUP_ALLWAKEUPIOS); /*!< Hardware Wake up sources control: : only WAKEUP_RTC_LITE_ALARM_WAKEUP, - WAKEUP_OS_EVENT_TIMER and WAKEUP_ALLWAKEUPIOS */ - - /* Wake up I/O sources */ - lv_low_power_mode_cfg.WAKEUPIOSRC = lf_wakeup_io_ctrl(wakeup_io_ctrl); - - cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ - SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ - - /* Save the configuration of the CPU interrupt enable Registers */ - cpu0_int_enable_0 = NVIC->ISER[0]; - cpu0_int_enable_1 = NVIC->ISER[1]; - - /* Save the configuration of the PMC RESETCTRL register */ - pmc_reset_ctrl = PMC->RESETCTRL; - /* Disable BoD VBAT and BoD Core resets */ - PMC->RESETCTRL = - pmc_reset_ctrl & (~(PMC_RESETCTRL_BODVBATRESETENABLE_MASK | PMC_RESETCTRL_BODCORERESETENABLE_MASK)); - - /* Disable LDO MEM bleed current */ - // PMC->MISCCTRL |= PMC_MISCCTRL_DISABLE_BLEED_MASK; - - /* Enter low power mode */ - POWER_EnterLowPower(&lv_low_power_mode_cfg); - - /* Restore the configuration of the NMI Register */ - SYSCON->NMISRC |= cpu0_nmi_enable; - - /* Restore PMC RESETCTRL register */ - PMC->RESETCTRL = pmc_reset_ctrl; - - /* Restore the configuration of the CPU interrupt enable Registers */ - NVIC->ISER[0] = cpu0_int_enable_0; - NVIC->ISER[1] = cpu0_int_enable_1; -} - -/** - * brief PMC Sleep function call - * return nothing - */ -void POWER_EnterSleep(void) -{ - uint32_t pmsk; - pmsk = __get_PRIMASK(); - __disable_irq(); - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - __WFI(); - __set_PRIMASK(pmsk); -} - -/** - * @brief Get Digital Core logic supply source to be used during Deep Sleep. - * @param [in] exclude_from_pd: COmpoenents NOT to be powered down during Deep Sleep - * @param [out] core_supply: 0 = LDO DEEPSLEEP will be used / 1 = DCDC will be used - * @param [out] dcdc_voltage: as defined by V_DCDC_* in fsl_power.h - - * @return Nothing - */ -static void lf_get_deepsleep_core_supply_cfg(uint32_t exclude_from_pd, uint32_t *dcdc_voltage) -{ - *dcdc_voltage = (uint32_t)V_DCDC_0P950; /* Default value */ - - if (((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_USB1_PHY) != 0UL) && - ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_LDOUSBHS) != 0UL)) - { - /* USB High Speed is required as wake-up source in Deep Sleep mode */ - PMC->MISCCTRL |= PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK; /* Force flash buffer in low power mode */ - *dcdc_voltage = - (uint32_t)V_DCDC_1P000; /* Set DCDC voltage to be 1.000 V (USB HS IP cannot work below 0.990 V) */ - } -} - -/** - * @brief - * @param - * @return - */ -static uint32_t lf_set_ldo_ao_ldo_mem_voltage(uint32_t p_lp_mode, uint32_t p_dcdc_voltage) -{ -#define FLASH_NMPA_LDO_AO_ADDRS (0x9FCF4U) -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK (0x100U) -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK (0x3E00U) -#define FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT (9U) -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK (0x10000U) -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK (0x3E0000U) -#define FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT (17U) -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK (0x1000000U) -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK (0x3E000000U) -#define FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT (25U) - - uint32_t ldo_ao_trim, voltage; - uint32_t lv_v_ldo_pmu, lv_v_ldo_pmu_boost; - - ldo_ao_trim = (*((volatile unsigned int *)(FLASH_NMPA_LDO_AO_ADDRS))); - - switch (p_lp_mode) - { - case LOWPOWER_CFG_LPMODE_DEEPSLEEP: - { - if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK) != 0UL) - { - /* Apply settings coming from Flash */ - lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK) >> FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT; - lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ - } - else - { - /* Apply default settings */ - lv_v_ldo_pmu = (uint32_t)V_AO_0P900; - lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P850; - } - } - break; - - case LOWPOWER_CFG_LPMODE_POWERDOWN: - { - if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK) != 0UL) - { - /* Apply settings coming from Flash */ - lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK) >> FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT; - lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ - } - else - { - /* Apply default settings */ - lv_v_ldo_pmu = (uint32_t)V_AO_0P800; - lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P750; - } - } - break; - - case LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN: - { - if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK) != 0UL) - { - /* Apply settings coming from Flash */ - lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK) >> FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT; - lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ - } - else - { - /* Apply default settings */ - lv_v_ldo_pmu = (uint32_t)V_AO_0P800; - lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P750; - } - } - break; - - default: - /* Should never reach this point */ - lv_v_ldo_pmu = (uint32_t)V_AO_1P100; - lv_v_ldo_pmu_boost = (uint32_t)V_AO_1P050; - break; - } - - /* The Memories Voltage settings below are for voltage scaling */ - voltage = - (lv_v_ldo_pmu << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) | /* */ - (lv_v_ldo_pmu_boost << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) | /* */ - ((uint32_t)V_AO_0P750 << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) | /* Set to 0.75V (voltage Scaling) */ - ((uint32_t)V_AO_0P700 << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) | /* Set to 0.7V (voltage Scaling) */ - ((uint32_t)V_DEEPSLEEP_0P900 - << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX) | /* Set to 0.90 V (Not used because LDO_DEEP_SLEEP is disabled)*/ - (p_dcdc_voltage << LOWPOWER_VOLTAGE_DCDC_INDEX) /* */ - ; - - return (voltage); -} - -/** - * @brief - * @param - * @return - */ -static uint32_t lf_wakeup_io_ctrl(uint32_t p_wakeup_io_ctrl) -{ - uint32_t wake_up_type; - uint32_t misc_ctrl_reg; - uint8_t use_external_pullupdown = 0; - - /* Configure Pull up & Pull down based on the required wake-up edge */ - CLOCK_EnableClock(kCLOCK_Iocon); - - misc_ctrl_reg = 0UL; - - /* Wake-up I/O 0 */ - wake_up_type = (p_wakeup_io_ctrl & 0x3UL) >> LOWPOWER_WAKEUPIOSRC_PIO0_INDEX; - use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK) >> - LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX); - - if (use_external_pullupdown == 0UL) - { - if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) - { - /* Rising edge and both rising and falling edges */ - IOCON->PIO[1][1] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ - misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; - } - else - { - if (wake_up_type == 2UL) - { - /* Falling edge only */ - IOCON->PIO[1][1] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ - misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; - p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; - } - else - { - /* Wake-up I/O is disabled : set it as required by the user */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as Plain Input */ - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; - } - else - { - /* Wake-up I/O is configured as pull-up or pull-down */ - misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; - } - } - } - } - else - { - /* MISCCTRL[8]:WAKEUPIOCTRL[8]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */ - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; - misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; - } - - /* Wake-up I/O 1 */ - wake_up_type = (p_wakeup_io_ctrl & 0xCUL) >> LOWPOWER_WAKEUPIOSRC_PIO1_INDEX; - use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK) >> - LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX); - - if (use_external_pullupdown == 0UL) - { - if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) - { - /* Rising edge and both rising and falling edges */ - IOCON->PIO[0][28] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ - misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; - } - else - { - if (wake_up_type == 2UL) - { - /* Falling edge only */ - IOCON->PIO[0][28] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ - misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; - p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; - } - else - { - /* Wake-up I/O is disabled : set it as required by the user */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as Plain Input */ - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; - } - else - { - /* Wake-up I/O is configured as pull-up or pull-down */ - misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; - } - } - } - } - else - { - /* MISCCTRL[9]:WAKEUPIOCTRL[9]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */ - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; - misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; - } - - /* Wake-up I/O 2 */ - wake_up_type = (p_wakeup_io_ctrl & 0x30UL) >> LOWPOWER_WAKEUPIOSRC_PIO2_INDEX; - use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK) >> - LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX); - - if (use_external_pullupdown == 0UL) - { - if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) - { - /* Rising edge and both rising and falling edges */ - IOCON->PIO[1][18] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ - misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; - } - else - { - if (wake_up_type == 2UL) - { - /* Falling edge only */ - IOCON->PIO[1][18] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ - misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; - p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; - } - else - { - /* Wake-up I/O is disabled : set it as required by the user */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as Plain Input */ - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; - } - else - { - /* Wake-up I/O is configured as pull-up or pull-down */ - misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; - } - } - } - } - else - { - /* MISCCTRL[10]:WAKEUPIOCTRL[10]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */ - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; - misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; - } - - /* Wake-up I/O 3 */ - wake_up_type = (p_wakeup_io_ctrl & 0xC0UL) >> LOWPOWER_WAKEUPIOSRC_PIO3_INDEX; - use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK) >> - LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX); - - if (use_external_pullupdown == 0UL) - { - if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) - { - /* Rising edge and both rising and falling edges */ - IOCON->PIO[1][30] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ - misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; - } - else - { - if (wake_up_type == 2UL) - { - /* Falling edge only */ - IOCON->PIO[1][30] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ - misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; - p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; - } - else - { - /* Wake-up I/O is disabled : set it as required by the user */ - if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK) != 0UL) - { - /* Wake-up I/O is configured as Plain Input */ - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; - } - else - { - /* Wake-up I/O is configured as pull-up or pull-down */ - misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; - } - } - } - } - else - { - /* MISCCTRL[11]:WAKEUPIOCTRL[11]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */ - p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; - misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; - } - - PMC->MISCCTRL = (PMC->MISCCTRL & 0xFFFFF0FFUL) | misc_ctrl_reg; - PMC->WAKEUPIOCTRL = p_wakeup_io_ctrl & 0xFFFUL; - - /* - * Defined according to : - * - LOWPOWER_WAKEUPIOSRC_ in fsl_power.h - * - LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_<...> in fsl_power.h - */ - return (p_wakeup_io_ctrl & 0xFFFUL); -} - -/** - * @brief - * @param - * @return - */ -static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity) -{ - /* Compensate for discontinuity in the capacitor banks */ - if (u8OscCap < 64U) - { - if (u8OscCap >= u8CapBankDiscontinuity) - { - u8OscCap -= u8CapBankDiscontinuity; - } - else - { - u8OscCap = 0U; - } - } - else - { - if (u8OscCap <= (127U - u8CapBankDiscontinuity)) - { - u8OscCap += u8CapBankDiscontinuity; - } - else - { - u8OscCap = 127U; - } - } - return u8OscCap; -} - -/** - * @brief Described in fsl_common.h - * @param - * @return - */ -static void lowpower_set_system_voltage(uint32_t system_voltage_mv) -{ - /* - * Set system voltage - */ - uint32_t lv_ldo_ao = (uint32_t)V_AO_1P100; /* */ - uint32_t lv_ldo_ao_boost = (uint32_t)V_AO_1P150; /* */ - uint32_t lv_dcdc = (uint32_t)V_DCDC_1P100; /* */ - - if (system_voltage_mv <= 950UL) - { - lv_dcdc = (uint32_t)V_DCDC_0P950; - lv_ldo_ao = (uint32_t)V_AO_0P960; - lv_ldo_ao_boost = (uint32_t)V_AO_1P010; - } - else if (system_voltage_mv <= 975UL) - { - lv_dcdc = (uint32_t)V_DCDC_0P975; - lv_ldo_ao = (uint32_t)V_AO_0P980; - lv_ldo_ao_boost = (uint32_t)V_AO_1P030; - } - else if (system_voltage_mv <= 1000UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P000; - lv_ldo_ao = (uint32_t)V_AO_1P000; - lv_ldo_ao_boost = (uint32_t)V_AO_1P050; - } - else if (system_voltage_mv <= 1025UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P025; - lv_ldo_ao = (uint32_t)V_AO_1P030; - lv_ldo_ao_boost = (uint32_t)V_AO_1P080; - } - else if (system_voltage_mv <= 1050UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P050; - lv_ldo_ao = (uint32_t)V_AO_1P060; - lv_ldo_ao_boost = (uint32_t)V_AO_1P110; - } - else if (system_voltage_mv <= 1075UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P075; - lv_ldo_ao = (uint32_t)V_AO_1P080; - lv_ldo_ao_boost = (uint32_t)V_AO_1P130; - } - else if (system_voltage_mv <= 1100UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P100; - lv_ldo_ao = (uint32_t)V_AO_1P100; - lv_ldo_ao_boost = (uint32_t)V_AO_1P150; - } - else if (system_voltage_mv <= 1125UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P125; - lv_ldo_ao = (uint32_t)V_AO_1P130; - lv_ldo_ao_boost = (uint32_t)V_AO_1P160; - } - else if (system_voltage_mv <= 1150UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P150; - lv_ldo_ao = (uint32_t)V_AO_1P160; - lv_ldo_ao_boost = (uint32_t)V_AO_1P220; - } - else if (system_voltage_mv <= 1175UL) - { - lv_dcdc = (uint32_t)V_DCDC_1P175; - lv_ldo_ao = (uint32_t)V_AO_1P160; - lv_ldo_ao_boost = (uint32_t)V_AO_1P220; - } - else - { - lv_dcdc = (uint32_t)V_DCDC_1P200; - lv_ldo_ao = (uint32_t)V_AO_1P160; - lv_ldo_ao_boost = (uint32_t)V_AO_1P220; - } - - /* Set up LDO Always-On voltages */ - PMC->LDOPMU = (PMC->LDOPMU & (~PMC_LDOPMU_VADJ_MASK) & (~PMC_LDOPMU_VADJ_BOOST_MASK)) | PMC_LDOPMU_VADJ(lv_ldo_ao) | - PMC_LDOPMU_VADJ_BOOST(lv_ldo_ao_boost); - - /* Set up DCDC voltage */ - PMC->DCDC0 = (PMC->DCDC0 & (~PMC_DCDC0_VOUT_MASK)) | PMC_DCDC0_VOUT(lv_dcdc); -} - -/** - * @brief Described in fsl_common.h - * @param - * @return - */ -static void lowpower_set_dcdc_power_profile(lowpower_dcdc_power_profile_enum dcdc_power_profile) -{ -#define FLASH_NMPA_BASE (0x9FC00u) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ADDRS (FLASH_NMPA_BASE + 0xE0U) // (0x9FCE0U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ADDRS (FLASH_NMPA_BASE + 0xE4U) // (0x9FCE4U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ADDRS (FLASH_NMPA_BASE + 0xE8U) // (0x9FCE8U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ADDRS (FLASH_NMPA_BASE + 0xECU) // (0x9FCECU) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ADDRS (FLASH_NMPA_BASE + 0xD8U) // (0x9FCD8U) -#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ADDRS (FLASH_NMPA_BASE + 0xDCU) // (0x9FCDCU) - - const uint32_t PMC_DCDC0_DEFAULT = 0x010C4E68; - const uint32_t PMC_DCDC1_DEFAULT = 0x01803A98; - - uint32_t dcdcTrimValue0; - uint32_t dcdcTrimValue1; - - switch (dcdc_power_profile) - { - case DCDC_POWER_PROFILE_LOW: - /* Low */ - dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ADDRS))); - dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ADDRS))); - - if (0UL != (dcdcTrimValue0 & 0x1UL)) - { - dcdcTrimValue0 = dcdcTrimValue0 >> 1; - - PMC->DCDC0 = dcdcTrimValue0; - PMC->DCDC1 = dcdcTrimValue1; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : DCDC Power Profile set to " - "LOW" - "\n"); -#endif - } - break; - - case DCDC_POWER_PROFILE_MEDIUM: - /* Medium */ - dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ADDRS))); - dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ADDRS))); - - if (0UL != (dcdcTrimValue0 & 0x1UL)) - { - dcdcTrimValue0 = dcdcTrimValue0 >> 1; - - PMC->DCDC0 = dcdcTrimValue0; - PMC->DCDC1 = dcdcTrimValue1; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : DCDC Power Profile set to " - "MEDIUM" - "\n"); -#endif - } - break; - - case DCDC_POWER_PROFILE_HIGH: - /* High */ - dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ADDRS))); - dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ADDRS))); - - if (0UL != (dcdcTrimValue0 & 0x1UL)) - { - dcdcTrimValue0 = dcdcTrimValue0 >> 1; - - PMC->DCDC0 = dcdcTrimValue0; - PMC->DCDC1 = dcdcTrimValue1; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : DCDC Power Profile set to " - "HIGH" - "\n"); -#endif - } - break; - - default: - /* Low */ - PMC->DCDC0 = PMC_DCDC0_DEFAULT; - PMC->DCDC1 = PMC_DCDC1_DEFAULT; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : DCDC Power Profile set to " - "LOW" - "\n"); -#endif - break; - } -} - -/** - * @brief - * @param - * @return - */ -static lowpower_process_corner_enum lowpower_get_part_process_corner(void) -{ -#define FLASH_NMPA_PVT_MONITOR_0_RINGO_ADDRS (FLASH_NMPA_BASE + 0x130U) -#define FLASH_NMPA_PVT_MONITOR_1_RINGO_ADDRS (FLASH_NMPA_BASE + 0x140U) - - lowpower_process_corner_enum part_process_corner; - uint32_t pvt_ringo_hz; - uint32_t pvt_ringo_0 = (*((volatile unsigned int *)(FLASH_NMPA_PVT_MONITOR_0_RINGO_ADDRS))); - uint32_t pvt_ringo_1 = (*((volatile unsigned int *)(FLASH_NMPA_PVT_MONITOR_1_RINGO_ADDRS))); - - /* - * Check that the PVT Monitors Trimmings in flash are valid. - */ - if (0UL != (pvt_ringo_0 & 0x1UL)) - { - /* PVT Trimmings in Flash are valid */ - pvt_ringo_0 = pvt_ringo_0 >> 1; - } - else - { - /* PVT Trimmings in Flash are NOT valid (average value assumed) */ - pvt_ringo_0 = PROCESS_NNN_AVG_HZ; - } - - if (0UL != (pvt_ringo_1 & 0x1UL)) - { - /* PVT Trimmings in Flash are valid */ - pvt_ringo_1 = pvt_ringo_1 >> 1; - } - else - { - /* PVT Trimmings in Flash are NOT valid (average value assumed) */ - pvt_ringo_1 = PROCESS_NNN_AVG_HZ; - } - - if (pvt_ringo_1 <= pvt_ringo_0) - { - pvt_ringo_hz = pvt_ringo_1; - } - else - { - pvt_ringo_hz = pvt_ringo_0; - } - - /* - * Determine the process corner based on the value of the Ring Oscillator frequency - */ - if (pvt_ringo_hz <= PROCESS_NNN_MIN_HZ) - { - /* SSS Process Corner */ - part_process_corner = PROCESS_CORNER_SSS; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : Process Corner : " - "SSS" - "\n"); -#endif - } - else - { - if (pvt_ringo_hz <= PROCESS_NNN_MAX_HZ) - { - /* NNN Process Corner */ - part_process_corner = PROCESS_CORNER_NNN; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : Process Corner : " - "NNN" - "\n"); -#endif - } - else - { - /* FFF Process Corner */ - part_process_corner = PROCESS_CORNER_FFF; -#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) - PRINTF( - "\nINFO : Process Corner : " - "FFF" - "\n"); -#endif - } - } - - return (part_process_corner); -} - -/** - * @brief Described in fsl_common.h - * @param - * @return - */ -static void lowpower_set_voltage_for_process(lowpower_dcdc_power_profile_enum dcdc_power_profile) -{ - /* Get Sample Process Corner */ - lowpower_process_corner_enum part_process_corner = lowpower_get_part_process_corner(); - - switch (part_process_corner) - { - case PROCESS_CORNER_SSS: - /* Slow Corner */ - { - switch (dcdc_power_profile) - { - case DCDC_POWER_PROFILE_MEDIUM: - /* Medium */ - lowpower_set_system_voltage(VOLTAGE_SSS_MED_MV); - break; - - case DCDC_POWER_PROFILE_HIGH: - /* High */ - lowpower_set_system_voltage(VOLTAGE_SSS_HIG_MV); - break; - - default: - /* DCDC_POWER_PROFILE_LOW */ - lowpower_set_system_voltage(VOLTAGE_SSS_LOW_MV); - break; - } // switch(dcdc_power_profile) - } - break; - - case PROCESS_CORNER_FFF: - /* Fast Corner */ - { - switch (dcdc_power_profile) - { - case DCDC_POWER_PROFILE_MEDIUM: - /* Medium */ - lowpower_set_system_voltage(VOLTAGE_FFF_MED_MV); - break; - - case DCDC_POWER_PROFILE_HIGH: - /* High */ - lowpower_set_system_voltage(VOLTAGE_FFF_HIG_MV); - break; - - default: - /* DCDC_POWER_PROFILE_LOW */ - lowpower_set_system_voltage(VOLTAGE_FFF_LOW_MV); - break; - } // switch(dcdc_power_profile) - } - break; - - default: - /* Nominal (NNN) and all others Process Corners : assume Nominal Corner */ - { - switch (dcdc_power_profile) - { - case DCDC_POWER_PROFILE_MEDIUM: - /* Medium */ - lowpower_set_system_voltage(VOLTAGE_NNN_MED_MV); - break; - - case DCDC_POWER_PROFILE_HIGH: - /* High */ - lowpower_set_system_voltage(VOLTAGE_NNN_HIG_MV); - break; - - default: - /* DCDC_POWER_PROFILE_LOW */ - lowpower_set_system_voltage(VOLTAGE_NNN_LOW_MV); - break; - } // switch(dcdc_power_profile) - break; - } - } // switch(part_process_corner) -} - -/** - * @brief Described in fsl_common.h - * @param - * @return - */ -void POWER_SetVoltageForFreq(uint32_t system_freq_hz) -{ - if (system_freq_hz <= DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ) - { - /* [0 Hz - DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz] */ - lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_LOW); /* DCDC VOUT = 1.05 V by default */ - lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_LOW); - } - else - { - if (system_freq_hz <= DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ) - { - /* ]DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz - DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz] */ - lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_MEDIUM); /* DCDC VOUT = 1.15 V by default */ - lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_MEDIUM); - } - else - { - /* > DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz */ - lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_HIGH); /* DCDC VOUT = 1.2 V by default */ - lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_HIGH); - } - } -} - -void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, - int32_t pi32_16MfXtalPPcbParCappF_x100, - int32_t pi32_16MfXtalNPcbParCappF_x100) -{ - uint32_t u32XOTrimValue; - uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF, u8XOSlave; - int32_t iaXin_x4, ibXin, iaXout_x4, ibXout; - int32_t iXOCapInpF_x100, iXOCapOutpF_x100; - uint8_t u8XOCapInCtrl, u8XOCapOutCtrl; - uint32_t u32RegVal; - int32_t i32Tmp; - - /* Enable and set LDO, if not already done */ - POWER_SetXtal16mhzLdo(); - /* Get Cal values from Flash */ - u32XOTrimValue = GET_16MXO_TRIM(); - /* Check validity and apply */ - if ((0UL != (u32XOTrimValue & 1UL)) && (0UL != ((u32XOTrimValue >> 15UL) & 1UL))) - { - /* These fields are 7 bits, unsigned */ - u8IECXinCapCal6pF = (uint8_t)((u32XOTrimValue >> 1UL) & 0x7fUL); - u8IECXinCapCal8pF = (uint8_t)((u32XOTrimValue >> 8UL) & 0x7fUL); - u8IECXoutCapCal6pF = (uint8_t)((u32XOTrimValue >> 16UL) & 0x7fUL); - u8IECXoutCapCal8pF = (uint8_t)((u32XOTrimValue >> 23UL) & 0x7fUL); - /* This field is 1 bit */ - u8XOSlave = (uint8_t)((u32XOTrimValue >> 30UL) & 0x1UL); - /* Linear fit coefficients calculation */ - iaXin_x4 = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF; - ibXin = (int)u8IECXinCapCal6pF - iaXin_x4 * 3; - iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF; - ibXout = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3; - } - else - { - iaXin_x4 = 20; // gain in LSB/pF - ibXin = -9; // offset in LSB - iaXout_x4 = 20; // gain in LSB/pF - ibXout = -13; // offset in LSB - u8XOSlave = 0; - } - /* In & out load cap calculation with derating */ - iXOCapInpF_x100 = 2 * pi32_16MfXtalIecLoadpF_x100 - pi32_16MfXtalNPcbParCappF_x100 + - 39 * ((int32_t)XO_SLAVE_EN - (int32_t)u8XOSlave) - 15; - iXOCapOutpF_x100 = 2 * pi32_16MfXtalIecLoadpF_x100 - pi32_16MfXtalPPcbParCappF_x100 - 21; - /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */ - i32Tmp = ((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400; - u8XOCapInCtrl = (uint8_t)i32Tmp; - i32Tmp = ((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400; - u8XOCapOutCtrl = (uint8_t)i32Tmp; - /* Read register and clear fields to be written */ - u32RegVal = ANACTRL->XO32M_CTRL; - u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); - /* Configuration of 32 MHz XO output buffers */ -#if (XO_SLAVE_EN == 0) - u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); -#else - u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; -#endif - /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */ - u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT; - u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT; - /* Write back to register */ - ANACTRL->XO32M_CTRL = u32RegVal; -} - -void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, - int32_t pi32_32kfXtalPPcbParCappF_x100, - int32_t pi32_32kfXtalNPcbParCappF_x100) -{ - uint32_t u32XOTrimValue; - uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF; - int32_t iaXin_x4, ibXin, iaXout_x4, ibXout; - int32_t iXOCapInpF_x100, iXOCapOutpF_x100; - uint8_t u8XOCapInCtrl, u8XOCapOutCtrl; - uint32_t u32RegVal; - int32_t i32Tmp; - /* Get Cal values from Flash */ - u32XOTrimValue = GET_32KXO_TRIM(); - /* check validity and apply */ - if ((0UL != (u32XOTrimValue & 1UL)) && (0UL != ((u32XOTrimValue >> 15UL) & 1UL))) - { - /* These fields are 7 bits, unsigned */ - u8IECXinCapCal6pF = (uint8_t)((u32XOTrimValue >> 1UL) & 0x7fUL); - u8IECXinCapCal8pF = (uint8_t)((u32XOTrimValue >> 8UL) & 0x7fUL); - u8IECXoutCapCal6pF = (uint8_t)((u32XOTrimValue >> 16UL) & 0x7fUL); - u8IECXoutCapCal8pF = (uint8_t)((u32XOTrimValue >> 23UL) & 0x7fUL); - /* Linear fit coefficients calculation */ - iaXin_x4 = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF; - ibXin = (int)u8IECXinCapCal6pF - iaXin_x4 * 3; - iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF; - ibXout = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3; - } - else - { - iaXin_x4 = 16; // gain in LSB/pF - ibXin = 12; // offset in LSB - iaXout_x4 = 16; // gain in LSB/pF - ibXout = 11; // offset in LSB - } - - /* In & out load cap calculation with derating */ - iXOCapInpF_x100 = 2 * pi32_32kfXtalIecLoadpF_x100 - pi32_32kfXtalNPcbParCappF_x100 - 130; - iXOCapOutpF_x100 = 2 * pi32_32kfXtalIecLoadpF_x100 - pi32_32kfXtalPPcbParCappF_x100 - 41; - - /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */ - i32Tmp = ((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400; - u8XOCapInCtrl = (uint8_t)i32Tmp; - i32Tmp = ((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400; - u8XOCapOutCtrl = (uint8_t)i32Tmp; - - /* Read register and clear fields to be written */ - u32RegVal = PMC->XTAL32K; - u32RegVal &= ~(PMC_XTAL32K_CAPBANKIN_MASK | PMC_XTAL32K_CAPBANKOUT_MASK); - - /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */ - u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 23) << PMC_XTAL32K_CAPBANKIN_SHIFT; - u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 23) << PMC_XTAL32K_CAPBANKOUT_SHIFT; - - /* Write back to register */ - PMC->XTAL32K = u32RegVal; -} - -void POWER_SetXtal16mhzLdo(void) -{ - uint32_t temp; - const uint32_t u32Mask = - (ANACTRL_LDO_XO32M_VOUT_MASK | ANACTRL_LDO_XO32M_IBIAS_MASK | ANACTRL_LDO_XO32M_STABMODE_MASK); - - const uint32_t u32Value = - (ANACTRL_LDO_XO32M_VOUT(0x5) | ANACTRL_LDO_XO32M_IBIAS(0x2) | ANACTRL_LDO_XO32M_STABMODE(0x1)); - - /* Enable & set-up XTAL 32 MHz clock LDO */ - temp = ANACTRL->LDO_XO32M; - - if ((temp & u32Mask) != u32Value) - { - temp &= ~u32Mask; - - /* - * Enable the XTAL32M LDO - * Adjust the output voltage level, 0x5 for 1.1V - * Adjust the biasing current, 0x2 value - * Stability configuration, 0x1 default mode - */ - temp |= u32Value; - - ANACTRL->LDO_XO32M = temp; - - /* Delay for LDO to be up */ - // CLOCK_uDelay(20); - } - - /* Enable LDO XO32M */ - PMC->PDRUNCFGCLR0 = PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK; -} - -/** - * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes. - * @param p_reset_cause : the device reset cause, according to the definition of power_device_reset_cause_t type. - * @param p_boot_mode : the device boot mode, according to the definition of power_device_boot_mode_t type. - * @param p_wakeupio_cause: the wake-up pin sources, according to the definition of register PMC->WAKEIOCAUSE[3:0]. - - * @return Nothing - * - * !!! IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA !!! - * !!! valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06) !!! - * !!! when FALLING EDGE DETECTION is enabled on wake-up pins: !!! - * - 1. p_wakeupio_cause is NOT ACCURATE - * - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when - * several wake-up sources are enabled during DEEP-POWER-DOWN - * (like enabling wake-up on RTC and Falling edge wake-up pins) - * - */ -void POWER_GetWakeUpCause(power_device_reset_cause_t *p_reset_cause, - power_device_boot_mode_t *p_boot_mode, - uint32_t *p_wakeupio_cause) -{ - uint32_t reset_cause_reg; - uint32_t boot_mode_reg; - -#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ - defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ - defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) - reset_cause_reg = (PMC->AOREG1) & 0x3FF0UL; -#else /* LPC55S69/28 */ - reset_cause_reg = (PMC->AOREG1) & 0x1FF0UL; -#endif - - /* - * Prioritize interrupts source with respect to their critical level - */ -#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ - defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ - defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) - if (0UL != (reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK)) - { /* Code Watchdog Reset */ - *p_reset_cause = kRESET_CAUSE_CDOGRESET; - *p_boot_mode = kBOOT_MODE_POWER_UP; - *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ - } - else -#endif - { - if (0UL != (reset_cause_reg & PMC_AOREG1_WDTRESET_MASK)) - { /* Watchdog Timer Reset */ - *p_reset_cause = kRESET_CAUSE_WDTRESET; - *p_boot_mode = kBOOT_MODE_POWER_UP; - *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ - } - else - { - if (0UL != (reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK)) - { /* ARM System Reset */ - *p_reset_cause = kRESET_CAUSE_ARMSYSTEMRESET; - *p_boot_mode = kBOOT_MODE_POWER_UP; - *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ - } - else - { - boot_mode_reg = (PMC->STATUS & PMC_STATUS_BOOTMODE_MASK) >> PMC_STATUS_BOOTMODE_SHIFT; - - if (boot_mode_reg == 0UL) /* POWER-UP: Power On Reset, Pin reset, Brown Out Detectors, Software Reset */ - { - *p_boot_mode = kBOOT_MODE_POWER_UP; /* All non wake-up from a Low Power mode */ - *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ - - /* - * Prioritise Reset causes, starting from the strongest (Power On Reset) - */ - if (0UL != (reset_cause_reg & PMC_AOREG1_POR_MASK)) - { /* Power On Reset */ - *p_reset_cause = kRESET_CAUSE_POR; - } - else - { - if (0UL != (reset_cause_reg & PMC_AOREG1_BODRESET_MASK)) - { /* Brown-out Detector reset (either BODVBAT or BODCORE) */ - *p_reset_cause = kRESET_CAUSE_BODRESET; - } - else - { - if (0UL != (reset_cause_reg & PMC_AOREG1_PADRESET_MASK)) - { /* Hardware Pin Reset */ - *p_reset_cause = kRESET_CAUSE_PADRESET; - } - else - { - if (0UL != (reset_cause_reg & PMC_AOREG1_SWRRESET_MASK)) - { /* Software triggered Reset */ - *p_reset_cause = kRESET_CAUSE_SWRRESET; - } - else - { /* Unknown Reset Cause */ - *p_reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC; - } - } - } - } - -#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ - defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ - defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) - /* Transfer the control of the 4 wake-up pins to IOCON (instead of the Power Management Controller - */ - PMC->WAKEUPIOCTRL = PMC->WAKEUPIOCTRL & (~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK); -#endif - } - else /* DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN */ - { - /* - * 1- First, save wakeup_io_cause register ... - */ - *p_wakeupio_cause = PMC->WAKEIOCAUSE; - - if (boot_mode_reg == 3UL) /* DEEP-POWER-DOWN */ - { - *p_boot_mode = kBOOT_MODE_LP_DEEP_POWER_DOWN; - - switch (((reset_cause_reg >> PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT) & 0x7UL)) - { - case 1: - *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO; - break; - case 2: - *p_reset_cause = kRESET_CAUSE_DPDRESET_RTC; - break; - case 3: - *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC; - break; - case 4: - *p_reset_cause = kRESET_CAUSE_DPDRESET_OSTIMER; - break; - case 5: - *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER; - break; - case 6: - *p_reset_cause = kRESET_CAUSE_DPDRESET_RTC_OSTIMER; - break; - case 7: - *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER; - break; - default: - /* Unknown Reset Cause */ - *p_reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC; - break; - } - -#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ - defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ - defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) - /* - * 2- Next, transfer the control of the 4 wake-up pins - * to IOCON (instead of the Power Management Controller) - */ - PMC->WAKEUPIOCTRL = PMC->WAKEUPIOCTRL & (~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK); -#endif - } - else /* DEEP-SLEEP and POWER-DOWN */ - { - *p_reset_cause = kRESET_CAUSE_NOT_RELEVANT; - - /* - * The control of the 4 wake-up pins is already in IOCON, - * so there is nothing special to do. - */ - - if (boot_mode_reg == 1UL) /* DEEP-SLEEP */ - { - *p_boot_mode = kBOOT_MODE_LP_DEEP_SLEEP; - } - else /* POWER-DOWN */ - { - *p_boot_mode = kBOOT_MODE_LP_POWER_DOWN; - - } /* if ( boot_mode_reg == 1 ) DEEP-SLEEP */ - - } /* if ( boot_mode == 3 ) DEEP-POWER-DOWN */ - - } /* if ( boot_mode == 0 ) POWER-UP */ - - } /* if ( reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK ) */ - - } /* if ( reset_cause_reg & PMC_AOREG1_WDTRESET_MASK ) */ - - } /* if ( reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK ) */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_power.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_power.h deleted file mode 100644 index 6a9de7a9f50..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_power.h +++ /dev/null @@ -1,611 +0,0 @@ -/* - * Copyright 2017, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_POWER_H_ -#define _FSL_POWER_H_ - -#include "fsl_common.h" -#include "fsl_device_registers.h" -#include - -/*! - * @addtogroup power - * @{ - */ -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief power driver version 1.0.0. */ -#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) -/*@}*/ - -/* Power mode configuration API parameter */ -typedef enum _power_mode_config -{ - kPmu_Sleep = 0U, - kPmu_Deep_Sleep = 1U, - kPmu_PowerDown = 2U, - kPmu_Deep_PowerDown = 3U, -} power_mode_cfg_t; - -/** - * @brief Analog components power modes control during low power modes - */ -typedef enum pd_bits -{ - kPDRUNCFG_PD_DCDC = (1UL << 0), - kPDRUNCFG_PD_BIAS = (1UL << 1), - kPDRUNCFG_PD_BODCORE = (1UL << 2), - kPDRUNCFG_PD_BODVBAT = (1UL << 3), - kPDRUNCFG_PD_FRO1M = (1UL << 4), - kPDRUNCFG_PD_FRO192M = (1UL << 5), - kPDRUNCFG_PD_FRO32K = (1UL << 6), - kPDRUNCFG_PD_XTAL32K = (1UL << 7), - kPDRUNCFG_PD_XTAL32M = (1UL << 8), - kPDRUNCFG_PD_PLL0 = (1UL << 9), - kPDRUNCFG_PD_PLL1 = (1UL << 10), - kPDRUNCFG_PD_USB0_PHY = (1UL << 11), - kPDRUNCFG_PD_USB1_PHY = (1UL << 12), - kPDRUNCFG_PD_COMP = (1UL << 13), - kPDRUNCFG_PD_TEMPSENS = (1UL << 14), - kPDRUNCFG_PD_GPADC = (1UL << 15), - kPDRUNCFG_PD_LDOMEM = (1UL << 16), - kPDRUNCFG_PD_LDODEEPSLEEP = (1UL << 17), - kPDRUNCFG_PD_LDOUSBHS = (1UL << 18), - kPDRUNCFG_PD_LDOGPADC = (1UL << 19), - kPDRUNCFG_PD_LDOXO32M = (1UL << 20), - kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21), - kPDRUNCFG_PD_RNG = (1UL << 22), - kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23), - kPDRUNCFG_PD_ROM = (1UL << 24), - /* - This enum member has no practical meaning,it is used to avoid MISRA issue, - user should not trying to use it. - */ - kPDRUNCFG_ForceUnsigned = 0x80000000U, -} pd_bit_t; - -/*! @brief BOD VBAT level */ -typedef enum _power_bod_vbat_level -{ - kPOWER_BodVbatLevel1000mv = 0, /*!< Brown out detector VBAT level 1V */ - kPOWER_BodVbatLevel1100mv = 1, /*!< Brown out detector VBAT level 1.1V */ - kPOWER_BodVbatLevel1200mv = 2, /*!< Brown out detector VBAT level 1.2V */ - kPOWER_BodVbatLevel1300mv = 3, /*!< Brown out detector VBAT level 1.3V */ - kPOWER_BodVbatLevel1400mv = 4, /*!< Brown out detector VBAT level 1.4V */ - kPOWER_BodVbatLevel1500mv = 5, /*!< Brown out detector VBAT level 1.5V */ - kPOWER_BodVbatLevel1600mv = 6, /*!< Brown out detector VBAT level 1.6V */ - kPOWER_BodVbatLevel1650mv = 7, /*!< Brown out detector VBAT level 1.65V */ - kPOWER_BodVbatLevel1700mv = 8, /*!< Brown out detector VBAT level 1.7V */ - kPOWER_BodVbatLevel1750mv = 9, /*!< Brown out detector VBAT level 1.75V */ - kPOWER_BodVbatLevel1800mv = 10, /*!< Brown out detector VBAT level 1.8V */ - kPOWER_BodVbatLevel1900mv = 11, /*!< Brown out detector VBAT level 1.9V */ - kPOWER_BodVbatLevel2000mv = 12, /*!< Brown out detector VBAT level 2V */ - kPOWER_BodVbatLevel2100mv = 13, /*!< Brown out detector VBAT level 2.1V */ - kPOWER_BodVbatLevel2200mv = 14, /*!< Brown out detector VBAT level 2.2V */ - kPOWER_BodVbatLevel2300mv = 15, /*!< Brown out detector VBAT level 2.3V */ - kPOWER_BodVbatLevel2400mv = 16, /*!< Brown out detector VBAT level 2.4V */ - kPOWER_BodVbatLevel2500mv = 17, /*!< Brown out detector VBAT level 2.5V */ - kPOWER_BodVbatLevel2600mv = 18, /*!< Brown out detector VBAT level 2.6V */ - kPOWER_BodVbatLevel2700mv = 19, /*!< Brown out detector VBAT level 2.7V */ - kPOWER_BodVbatLevel2806mv = 20, /*!< Brown out detector VBAT level 2.806V */ - kPOWER_BodVbatLevel2900mv = 21, /*!< Brown out detector VBAT level 2.9V */ - kPOWER_BodVbatLevel3000mv = 22, /*!< Brown out detector VBAT level 3.0V */ - kPOWER_BodVbatLevel3100mv = 23, /*!< Brown out detector VBAT level 3.1V */ - kPOWER_BodVbatLevel3200mv = 24, /*!< Brown out detector VBAT level 3.2V */ - kPOWER_BodVbatLevel3300mv = 25, /*!< Brown out detector VBAT level 3.3V */ -} power_bod_vbat_level_t; - -/*! @brief BOD Hysteresis control */ -typedef enum _power_bod_hyst -{ - kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */ - kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */ - kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */ - kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */ -} power_bod_hyst_t; - -/*! @brief BOD core level */ -typedef enum _power_bod_core_level -{ - kPOWER_BodCoreLevel600mv = 0, /*!< Brown out detector core level 600mV */ - kPOWER_BodCoreLevel650mv = 1, /*!< Brown out detector core level 650mV */ - kPOWER_BodCoreLevel700mv = 2, /*!< Brown out detector core level 700mV */ - kPOWER_BodCoreLevel750mv = 3, /*!< Brown out detector core level 750mV */ - kPOWER_BodCoreLevel800mv = 4, /*!< Brown out detector core level 800mV */ - kPOWER_BodCoreLevel850mv = 5, /*!< Brown out detector core level 850mV */ - kPOWER_BodCoreLevel900mv = 6, /*!< Brown out detector core level 900mV */ - kPOWER_BodCoreLevel950mv = 7, /*!< Brown out detector core level 950mV */ -} power_bod_core_level_t; - -/** - * @brief Device Reset Causes - */ -typedef enum _power_device_reset_cause -{ - kRESET_CAUSE_POR = 0UL, /*!< Power On Reset */ - kRESET_CAUSE_PADRESET = 1UL, /*!< Hardware Pin Reset */ - kRESET_CAUSE_BODRESET = 2UL, /*!< Brown-out Detector reset (either BODVBAT or BODCORE) */ - kRESET_CAUSE_ARMSYSTEMRESET = 3UL, /*!< ARM System Reset */ - kRESET_CAUSE_WDTRESET = 4UL, /*!< Watchdog Timer Reset */ - kRESET_CAUSE_SWRRESET = 5UL, /*!< Software Reset */ - kRESET_CAUSE_CDOGRESET = 6UL, /*!< Code Watchdog Reset */ - /* Reset causes in DEEP-POWER-DOWN low power mode */ - kRESET_CAUSE_DPDRESET_WAKEUPIO = 7UL, /*!< Any of the 4 wake-up pins */ - kRESET_CAUSE_DPDRESET_RTC = 8UL, /*!< Real Time Counter (RTC) */ - kRESET_CAUSE_DPDRESET_OSTIMER = 9UL, /*!< OS Event Timer (OSTIMER) */ - kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC = 10UL, /*!< Any of the 4 wake-up pins and RTC (it is not possible to distinguish - which of these 2 events occured first) */ - kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER = 11UL, /*!< Any of the 4 wake-up pins and OSTIMER (it is not possible to - distinguish which of these 2 events occured first) */ - kRESET_CAUSE_DPDRESET_RTC_OSTIMER = 12UL, /*!< Real Time Counter or OS Event Timer (it is not possible to - distinguish which of these 2 events occured first) */ - kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER = 13UL, /*!< Any of the 4 wake-up pins (it is not possible to distinguish - which of these 3 events occured first) */ - /* Miscallenous */ - kRESET_CAUSE_NOT_RELEVANT = - 14UL, /*!< No reset cause (for example, this code is used when waking up from DEEP-SLEEP low power mode) */ - kRESET_CAUSE_NOT_DETERMINISTIC = 15UL, /*!< Unknown Reset Cause. Should be treated like "Hardware Pin Reset" from an - application point of view. */ -} power_device_reset_cause_t; - -/** - * @brief Device Boot Modes - */ -typedef enum _power_device_boot_mode -{ - kBOOT_MODE_POWER_UP = - 0UL, /*!< All non Low Power Mode wake up (Power On Reset, Pin Reset, BoD Reset, ARM System Reset ... ) */ - kBOOT_MODE_LP_DEEP_SLEEP = 1UL, /*!< Wake up from DEEP-SLEEP Low Power mode */ - kBOOT_MODE_LP_POWER_DOWN = 2UL, /*!< Wake up from POWER-DOWN Low Power mode */ - kBOOT_MODE_LP_DEEP_POWER_DOWN = 4UL, /*!< Wake up from DEEP-POWER-DOWN Low Power mode */ -} power_device_boot_mode_t; - -/** - * @brief SRAM instances retention control during low power modes - */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 \ - (1UL << 0) /*!< Enable SRAMX_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 \ - (1UL << 1) /*!< Enable SRAMX_1 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 \ - (1UL << 2) /*!< Enable SRAMX_2 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 \ - (1UL << 3) /*!< Enable SRAMX_3 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM00 \ - (1UL << 4) /*!< Enable SRAM0_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM01 \ - (1UL << 5) /*!< Enable SRAM0_1 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM10 \ - (1UL << 6) /*!< Enable SRAM1_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM20 \ - (1UL << 7) /*!< Enable SRAM2_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM30 \ - (1UL << 8) /*!< Enable SRAM3_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM31 \ - (1UL << 9) /*!< Enable SRAM3_1 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM40 \ - (1UL << 10) /*!< Enable SRAM4_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM41 \ - (1UL << 11) /*!< Enable SRAM4_1 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM42 \ - (1UL << 12) /*!< Enable SRAM4_2 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM43 \ - (1UL << 13) /*!< Enable SRAM4_3 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_USB_HS \ - (1UL << 14) /*!< Enable SRAM USB HS retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_PUF \ - (1UL << 15) /*!< Enable SRAM PUFF retention when entering in Low power modes */ - -/** - * @brief Low Power Modes Wake up sources - */ -#define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/ -#define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */ -#define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */ -#define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */ -#define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */ -#define WAKEUP_ACMP_CAPT (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -// reserved (1ULL << 25) -// reserved (1ULL << 26) -#define WAKEUP_USB0_NEEDCLK (1ULL << 27) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_USB0 (1ULL << 28) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ -#define WAKEUP_EZH_ARCH_B (1ULL << 30) /*!< [SLEEP, ] */ -#define WAKEUP_WAKEUP_MAILBOX (1ULL << 31) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ -// reserved (1ULL << 39) -// reserved (1ULL << 40) -// reserved (1ULL << 41) -#define WAKEUP_SDIO (1ULL << 42) /*!< [SLEEP, ] */ -// reserved (1ULL << 43) -// reserved (1ULL << 44) -// reserved (1ULL << 45) -// reserved (1ULL << 46) -#define WAKEUP_USB1 (1ULL << 47) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_USB1_NEEDCLK (1ULL << 48) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */ -#define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SEC_VIO (1ULL << 53) -#define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */ -#define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */ -#define WAKEUP_PUFF (1ULL << 56) /*!< [SLEEP, ] */ -#define WAKEUP_PQ (1ULL << 57) /*!< [SLEEP, ] */ -#define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */ -// reserved WAKEUP_PVTVF0_AMBER (1ULL << 60) -// reserved WAKEUP_PVTVF0_RED (1ULL << 61) -// reserved WAKEUP_PVTVF1_AMBER (1ULL << 62) -#define WAKEUP_ALLWAKEUPIOS (1ULL << 63) /*!< [ , DEEP POWER DOWN] */ - -/** - * @brief Sleep Postpone - */ -#define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */ -#define LOWPOWER_HWWAKE_PERIPHERALS \ - (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause \ - peripheral clocking to wake up temporarily while the related status is asserted */ -#define LOWPOWER_HWWAKE_SDMA0 \ - (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA \ - completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ -#define LOWPOWER_HWWAKE_SDMA1 \ - (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA \ - completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ -#define LOWPOWER_HWWAKE_ENABLE_FRO192M \ - (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of \ - LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set */ - -#define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */ -#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */ -/** - * @brief Wake up I/O sources - */ -#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */ -#define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */ -#define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */ -#define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */ - -#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */ -#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */ -#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */ -#define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */ - -#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX 8 /*!< Wake-up I/O 0 pull-up/down configuration index */ -#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX 9 /*!< Wake-up I/O 1 pull-up/down configuration index */ -#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX 10 /*!< Wake-up I/O 2 pull-up/down configuration index */ -#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX 11 /*!< Wake-up I/O 3 pull-up/down configuration index */ - -#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down mask */ -#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down mask */ -#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down mask */ -#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down mask */ - -#define LOWPOWER_WAKEUPIO_PULLDOWN 0 /*!< Select pull-down */ -#define LOWPOWER_WAKEUPIO_PULLUP 1 /*!< Select pull-up */ - -#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX \ - 12 /*!< Wake-up I/O 0 pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX \ - 13 /*!< Wake-up I/O 1 pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX \ - 14 /*!< Wake-up I/O 2 pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX \ - 15 /*!< Wake-up I/O 3 pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down disable/enable mask */ -#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down disable/enable mask */ -#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down disable/enable mask */ -#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down disable/enable mask */ - -#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX \ - (16) /*!< Wake-up I/O 0 use external pull-up/down disable/enable control index*/ -#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX \ - (17) /*!< Wake-up I/O 1 use external pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX \ - (18) /*!< Wake-up I/O 2 use external pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX \ - (19) /*!< Wake-up I/O 3 use external pull-up/down disable/enable control index */ -#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 use external pull-up/down \ - disable/enable mask, 0: disable, 1: enable */ -#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 use external pull-up/down \ - disable/enable mask, 0: disable, 1: enable */ -#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 use external pull-up/down \ - disable/enable mask, 0: disable, 1: enable */ -#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK \ - (1UL << LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 use external pull-up/down \ - disable/enable mask, 0: disable, 1: enable */ - -#ifdef __cplusplus -extern "C" { -#endif -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral - * - * @param en peripheral for which to enable the PDRUNCFG bit - * @return none - */ -static inline void POWER_EnablePD(pd_bit_t en) -{ - /* PDRUNCFGSET */ - PMC->PDRUNCFGSET0 = (uint32_t)en; -} - -/*! - * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral - * - * @param en peripheral for which to disable the PDRUNCFG bit - * @return none - */ -static inline void POWER_DisablePD(pd_bit_t en) -{ - /* PDRUNCFGCLR */ - PMC->PDRUNCFGCLR0 = (uint32_t)en; -} - -/*! - * @brief set BOD VBAT level. - * - * @param level BOD detect level - * @param hyst BoD Hysteresis control - * @param enBodVbatReset VBAT brown out detect reset - */ -static inline void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset) -{ - PMC->BODVBAT = (PMC->BODVBAT & (~(PMC_BODVBAT_TRIGLVL_MASK | PMC_BODVBAT_HYST_MASK))) | PMC_BODVBAT_TRIGLVL(level) | - PMC_BODVBAT_HYST(hyst); - PMC->RESETCTRL = - (PMC->RESETCTRL & (~PMC_RESETCTRL_BODVBATRESETENABLE_MASK)) | PMC_RESETCTRL_BODVBATRESETENABLE(enBodVbatReset); -} - -#if defined(PMC_BODCORE_TRIGLVL_MASK) -/*! - * @brief set BOD core level. - * - * @param level BOD detect level - * @param hyst BoD Hysteresis control - * @param enBodCoreReset core brown out detect reset - */ -static inline void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset) -{ - PMC->BODCORE = (PMC->BODCORE & (~(PMC_BODCORE_TRIGLVL_MASK | PMC_BODCORE_HYST_MASK))) | PMC_BODCORE_TRIGLVL(level) | - PMC_BODCORE_HYST(hyst); - PMC->RESETCTRL = - (PMC->RESETCTRL & (~PMC_RESETCTRL_BODCORERESETENABLE_MASK)) | PMC_RESETCTRL_BODCORERESETENABLE(enBodCoreReset); -} -#endif - -/*! - * @brief API to enable deep sleep bit in the ARM Core. - * - * @return none - */ -static inline void POWER_EnableDeepSleep(void) -{ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; -} - -/*! - * @brief API to disable deep sleep bit in the ARM Core. - * - * @return none - */ -static inline void POWER_DisableDeepSleep(void) -{ - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; -} - -/** - * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event - * This MUST BE EXECUTED outside the Flash: - * either from ROM or from SRAM. The rest could stay in Flash. But, for consistency, it is - * preferable to have all functions defined in this file implemented in ROM. - * - * @return Nothing - */ -void POWER_CycleCpuAndFlash(void); - -/** - * @brief Configures and enters in DEEP-SLEEP low power mode - * @param exclude_from_pd: - * @param sram_retention_ctrl: - * @param wakeup_interrupts: - * @param hardware_wake_ctrl: - - * @return Nothing - * - * !!! IMPORTANT NOTES : - 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. - * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in - case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). - * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be - restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip - reset) reset) - */ -void POWER_EnterDeepSleep(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t hardware_wake_ctrl); - -/** - * @brief Configures and enters in POWERDOWN low power mode - * @param exclude_from_pd: - * @param sram_retention_ctrl: - * @param wakeup_interrupts: - * @param cpu_retention_ctrl: 0 = CPU retention is disable / 1 = CPU retention is enabled, all other values are - RESERVED. - - * @return Nothing - * - * !!! IMPORTANT NOTES : - 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. - * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in - case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). - * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be - restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance - containing the stack used to call this function WILL BE preserved during low power (via parameter - "sram_retention_ctrl") - * 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip - reset) reset) - */ - -void POWER_EnterPowerDown(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t cpu_retention_ctrl); - -/** - * @brief Configures and enters in DEEPPOWERDOWN low power mode - * @param exclude_from_pd: - * @param sram_retention_ctrl: - * @param wakeup_interrupts: - * @param wakeup_io_ctrl: - - * @return Nothing - * - * !!! IMPORTANT NOTES : - 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. - * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back if - DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be - restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip - reset) - */ -void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, - uint32_t sram_retention_ctrl, - uint64_t wakeup_interrupts, - uint32_t wakeup_io_ctrl); - -/** - * @brief Configures and enters in SLEEP low power mode - * @param : - * @return Nothing - */ -void POWER_EnterSleep(void); - -/*! - * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency. - * - * @param system_freq_hz - The desired frequency (in Hertz) at which the part would like to operate, - * note that the voltage and flash wait states should be set before changing frequency - * @return none - */ -void POWER_SetVoltageForFreq(uint32_t system_freq_hz); - -/** - * @brief Sets board-specific trim values for 16MHz XTAL - * @param pi32_16MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 - * @param pi32_16MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF - * becomes 120 - * @param pi32_16MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF - * becomes 120 - * @return none - * @note Following default Values can be used: - * pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 - * pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20 - * pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 - */ -extern void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, - int32_t pi32_16MfXtalPPcbParCappF_x100, - int32_t pi32_16MfXtalNPcbParCappF_x100); -/** - * @brief Sets board-specific trim values for 32kHz XTAL - * @param pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 - * @param pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF - becomes 120 - * @param pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF - becomes 120 - - * @return none - * @note Following default Values can be used: - * pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 - * pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40 - * pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 - */ -extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, - int32_t pi32_32kfXtalPPcbParCappF_x100, - int32_t pi32_32kfXtalNPcbParCappF_x100); -/** - * @brief Enables and sets LDO for 16MHz XTAL - * - * @return none - */ -extern void POWER_SetXtal16mhzLdo(void); - -/** - * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes. - * @param p_reset_cause : the device reset cause, according to the definition of power_device_reset_cause_t type. - * @param p_boot_mode : the device boot mode, according to the definition of power_device_boot_mode_t type. - * @param p_wakeupio_cause: the wake-up pin sources, according to the definition of register PMC->WAKEIOCAUSE[3:0]. - - * @return Nothing - * - * !!! IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA !!! - * !!! valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06) !!! - * !!! when FALLING EDGE DETECTION is enabled on wake-up pins: !!! - * - 1. p_wakeupio_cause is NOT ACCURATE - * - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when - * several wake-up sources are enabled during DEEP-POWER-DOWN - * (like enabling wake-up on RTC and Falling edge wake-up pins) - * - */ -void POWER_GetWakeUpCause(power_device_reset_cause_t *p_reset_cause, - power_device_boot_mode_t *p_boot_mode, - uint32_t *p_wakeupio_cause); -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* _FSL_POWER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad.h deleted file mode 100644 index f17b8916786..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad.h +++ /dev/null @@ -1,2774 +0,0 @@ -/* - * Copyright 2018-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_POWERQUAD_H_ -#define _FSL_POWERQUAD_H_ - -#if defined(__CC_ARM) - -#elif defined(__ICCARM__) -#include -#elif defined(__GNUC__) -#include -#endif /* defined(__CC_ARM) */ - -#include "fsl_common.h" -#include "fsl_powerquad_data.h" - -/*! - * @addtogroup powerquad - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_POWERQUAD_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) /*!< Version. */ -/*@}*/ - -#define PQ_FLOAT32 0U -#define PQ_FIXEDPT 1U - -#define CP_PQ 0U -#define CP_MTX 1U -#define CP_FFT 2U -#define CP_FIR 3U -#define CP_CORDIC 5U - -#define PQ_TRANS 0U -#define PQ_TRIG 1U -#define PQ_BIQUAD 2U - -#define PQ_TRANS_FIXED 4U -#define PQ_TRIG_FIXED 5U -#define PQ_BIQUAD_FIXED 6U - -#define PQ_INV 0U -#define PQ_LN 1U -#define PQ_SQRT 2U -#define PQ_INVSQRT 3U -#define PQ_ETOX 4U -#define PQ_ETONX 5U -#define PQ_DIV 6U - -#define PQ_SIN 0U -#define PQ_COS 1U - -#define PQ_BIQ0_CALC 1U -#define PQ_BIQ1_CALC 1U - -#define PQ_COMP0_ONLY (0U << 1U) -#define PQ_COMP1_ONLY (1U << 1U) - -#define CORDIC_ITER(x) ((uint32_t)(x) << 2U) -#define CORDIC_MIU(x) ((uint32_t)(x) << 1U) -#define CORDIC_T(x) ((uint32_t)(x) << 0U) -#define CORDIC_ARCTAN CORDIC_T(1U) | CORDIC_MIU(0U) -#define CORDIC_ARCTANH CORDIC_T(1U) | CORDIC_MIU(1U) - -#define INST_BUSY 0x80000000U - -#define PQ_ERRSTAT_OVERFLOW 0U -#define PQ_ERRSTAT_NAN 1U -#define PQ_ERRSTAT_FIXEDOVERFLOW 2U -#define PQ_ERRSTAT_UNDERFLOW 3U - -#define PQ_TRANS_CFFT 0U -#define PQ_TRANS_IFFT 1U -#define PQ_TRANS_CDCT 2U -#define PQ_TRANS_IDCT 3U -#define PQ_TRANS_RFFT 4U -#define PQ_TRANS_RDCT 6U - -#define PQ_MTX_SCALE 1U -#define PQ_MTX_MULT 2U -#define PQ_MTX_ADD 3U -#define PQ_MTX_INV 4U -#define PQ_MTX_PROD 5U -#define PQ_MTX_SUB 7U -#define PQ_VEC_DOTP 9U -#define PQ_MTX_TRAN 10U - -/* FIR engine operation type */ -#define PQ_FIR_FIR 0U -#define PQ_FIR_CONVOLUTION 1U -#define PQ_FIR_CORRELATION 2U -#define PQ_FIR_INCREMENTAL 4U - -#define _pq_ln0(x) __arm_mcr(CP_PQ, PQ_LN, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) -#define _pq_inv0(x) __arm_mcr(CP_PQ, PQ_INV, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) -#define _pq_sqrt0(x) __arm_mcr(CP_PQ, PQ_SQRT, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) -#define _pq_invsqrt0(x) __arm_mcr(CP_PQ, PQ_INVSQRT, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) -#define _pq_etox0(x) __arm_mcr(CP_PQ, PQ_ETOX, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) -#define _pq_etonx0(x) __arm_mcr(CP_PQ, PQ_ETONX, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) -#define _pq_sin0(x) __arm_mcr(CP_PQ, PQ_SIN, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRIG) -#define _pq_cos0(x) __arm_mcr(CP_PQ, PQ_COS, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRIG) -#define _pq_biquad0(x) __arm_mcr(CP_PQ, PQ_BIQ0_CALC, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_BIQUAD) - -#define _pq_ln_fx0(x) __arm_mcr(CP_PQ, PQ_LN, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_inv_fx0(x) __arm_mcr(CP_PQ, PQ_INV, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_sqrt_fx0(x) __arm_mcr(CP_PQ, PQ_SQRT, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_invsqrt_fx0(x) __arm_mcr(CP_PQ, PQ_INVSQRT, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_etox_fx0(x) __arm_mcr(CP_PQ, PQ_ETOX, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_etonx_fx0(x) __arm_mcr(CP_PQ, PQ_ETONX, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_sin_fx0(x) __arm_mcr(CP_PQ, PQ_SIN, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRIG_FIXED) -#define _pq_cos_fx0(x) __arm_mcr(CP_PQ, PQ_COS, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRIG_FIXED) -#define _pq_biquad0_fx(x) __arm_mcr(CP_PQ, PQ_BIQ0_CALC, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_BIQUAD_FIXED) - -#define _pq_div0(x) __arm_mcrr(CP_PQ, PQ_FLOAT32 | PQ_COMP0_ONLY, (uint64_t)(x), PQ_DIV) -#define _pq_div1(x) __arm_mcrr(CP_PQ, PQ_FLOAT32 | PQ_COMP1_ONLY, (uint64_t)(x), PQ_DIV) - -#define _pq_ln1(x) __arm_mcr(CP_PQ, PQ_LN, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) -#define _pq_inv1(x) __arm_mcr(CP_PQ, PQ_INV, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) -#define _pq_sqrt1(x) __arm_mcr(CP_PQ, PQ_SQRT, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) -#define _pq_invsqrt1(x) __arm_mcr(CP_PQ, PQ_INVSQRT, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) -#define _pq_etox1(x) __arm_mcr(CP_PQ, PQ_ETOX, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) -#define _pq_etonx1(x) __arm_mcr(CP_PQ, PQ_ETONX, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) -#define _pq_sin1(x) __arm_mcr(CP_PQ, PQ_SIN, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRIG) -#define _pq_cos1(x) __arm_mcr(CP_PQ, PQ_COS, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRIG) -#define _pq_biquad1(x) __arm_mcr(CP_PQ, PQ_BIQ1_CALC, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_BIQUAD) - -#define _pq_ln_fx1(x) __arm_mcr(CP_PQ, PQ_LN, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_inv_fx1(x) __arm_mcr(CP_PQ, PQ_INV, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_sqrt_fx1(x) __arm_mcr(CP_PQ, PQ_SQRT, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_invsqrt_fx1(x) __arm_mcr(CP_PQ, PQ_INVSQRT, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_etox_fx1(x) __arm_mcr(CP_PQ, PQ_ETOX, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_etonx_fx1(x) __arm_mcr(CP_PQ, PQ_ETONX, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_sin_fx1(x) __arm_mcr(CP_PQ, PQ_SIN, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRIG_FIXED) -#define _pq_cos_fx1(x) __arm_mcr(CP_PQ, PQ_COS, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRIG_FIXED) -#define _pq_biquad1_fx(x) __arm_mcr(CP_PQ, PQ_BIQ1_CALC, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_BIQUAD_FIXED) - -#define _pq_readMult0() __arm_mrc(CP_PQ, 0, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, 0) -#define _pq_readAdd0() __arm_mrc(CP_PQ, 1, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, 0) -#define _pq_readMult1() __arm_mrc(CP_PQ, 0, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, 0) -#define _pq_readAdd1() __arm_mrc(CP_PQ, 1, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, 0) -#define _pq_readMult0_fx() __arm_mrc(CP_PQ, 0, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, 0) -#define _pq_readAdd0_fx() __arm_mrc(CP_PQ, 1, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, 0) -#define _pq_readMult1_fx() __arm_mrc(CP_PQ, 0, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, 0) -#define _pq_readAdd1_fx() __arm_mrc(CP_PQ, 1, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, 0) - -/*! Parameter used for vector ln(x) */ -#define PQ_LN_INF PQ_LN, 1, PQ_TRANS -/*! Parameter used for vector 1/x */ -#define PQ_INV_INF PQ_INV, 0, PQ_TRANS -/*! Parameter used for vector sqrt(x) */ -#define PQ_SQRT_INF PQ_SQRT, 0, PQ_TRANS -/*! Parameter used for vector 1/sqrt(x) */ -#define PQ_ISQRT_INF PQ_INVSQRT, 0, PQ_TRANS -/*! Parameter used for vector e^x */ -#define PQ_ETOX_INF PQ_ETOX, 0, PQ_TRANS -/*! Parameter used for vector e^(-x) */ -#define PQ_ETONX_INF PQ_ETONX, 0, PQ_TRANS -/*! Parameter used for vector sin(x) */ -#define PQ_SIN_INF PQ_SIN, 1, PQ_TRIG -/*! Parameter used for vector cos(x) */ -#define PQ_COS_INF PQ_COS, 1, PQ_TRIG - -/* - * Workaround used in vector functions: - * - * 1. In floating sin/cos case, there must be at least 5 core clock cycles - * between MCR and following MRRC - * 2. In fixed sin/cos case, there must be one NOP between two MCR - */ - -/* - * Register assignment for the vector calculation assembly. - * r0: pSrc, r1: pDest, r2-r7: Data - */ - -#define PQ_RUN_OPCODE_R3_R2(BATCH_OPCODE, BATCH_MACHINE) \ - __asm volatile( \ - " MCR p0,%[opcode],r3,c2,c0,%[machine] \n" \ - " MCR p0,%[opcode],r2,c0,c0,%[machine] \n" ::[opcode] "i"(BATCH_OPCODE), \ - [machine] "i"(BATCH_MACHINE)) - -#define PQ_RUN_OPCODE_R5_R4(BATCH_OPCODE, BATCH_MACHINE) \ - __asm volatile( \ - " MCR p0,%[opcode],r5,c2,c0,%[machine] \n" \ - " MCR p0,%[opcode],r4,c0,c0,%[machine] \n" ::[opcode] "i"(BATCH_OPCODE), \ - [machine] "i"(BATCH_MACHINE)) - -#define PQ_RUN_OPCODE_R7_R6(BATCH_OPCODE, BATCH_MACHINE) \ - __asm volatile( \ - " MCR p0,%[opcode],r7,c2,c0,%[machine] \n" \ - " MCR p0,%[opcode],r6,c0,c0,%[machine] \n" ::[opcode] "i"(BATCH_OPCODE), \ - [machine] "i"(BATCH_MACHINE)) - -#define PQ_Vector8_FP(middle, last, BATCH_OPCODE, DOUBLE_READ_ADDERS, BATCH_MACHINE) \ - PQ_RUN_OPCODE_R3_R2(BATCH_OPCODE, BATCH_MACHINE); \ - if (middle) \ - { \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store fourth two results */ \ - } \ - __asm volatile("LDMIA r0!,{r4-r5}"); /* load next 2 datas */ \ - __asm volatile("NOP"); \ - __asm volatile("NOP"); \ - if (DOUBLE_READ_ADDERS) \ - { \ - __asm volatile("MRRC p0,#0,r2,r3,c1"); \ - } \ - else \ - { \ - __asm volatile("MRRC p0,#0,r2,r3,c0"); \ - } \ - PQ_RUN_OPCODE_R5_R4(BATCH_OPCODE, BATCH_MACHINE); \ - __asm volatile("STRD r2,r3,[r1],#8"); /* store first two results */ \ - __asm volatile("LDMIA r0!,{r6-r7}"); /* load next 2 datas */ \ - __asm volatile("NOP"); \ - __asm volatile("NOP"); \ - if (DOUBLE_READ_ADDERS) \ - { \ - __asm volatile("MRRC p0,#0,r4,r5,c1"); \ - } \ - else \ - { \ - __asm volatile("MRRC p0,#0,r4,r5,c0"); \ - } \ - PQ_RUN_OPCODE_R7_R6(BATCH_OPCODE, BATCH_MACHINE); \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store second two results */ \ - __asm volatile("LDRD r4,r5,[r0],#8"); /* load last 2 of the 8 */ \ - __asm volatile("NOP"); \ - __asm volatile("NOP"); \ - if (DOUBLE_READ_ADDERS) \ - { \ - __asm volatile("MRRC p0,#0,r6,r7,c1"); \ - } \ - else \ - { \ - __asm volatile("MRRC p0,#0,r6,r7,c0"); \ - } \ - PQ_RUN_OPCODE_R5_R4(BATCH_OPCODE, BATCH_MACHINE); \ - __asm volatile("STRD r6,r7,[r1],#8"); /* store third two results */ \ - if (!last) \ - { \ - __asm volatile("LDRD r2,r3,[r0],#8"); /* load first two of next 8 */ \ - } \ - else \ - { \ - __asm volatile("NOP"); \ - __asm volatile("NOP"); \ - __asm volatile("NOP"); \ - } \ - __asm volatile("NOP"); \ - __asm volatile("NOP"); \ - if (DOUBLE_READ_ADDERS) \ - { \ - __asm volatile("MRRC p0,#0,r4,r5,c1"); \ - } \ - else \ - { \ - __asm volatile("MRRC p0,#0,r4,r5,c0"); \ - } \ - if (last) \ - { \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store fourth two results */ \ - } - -#define PQ_RUN_OPCODE_R2_R3(BATCH_OPCODE, BATCH_MACHINE) \ - __asm volatile( \ - " MCR p0,%[opcode],r2,c1,c0,%[machine] \n" \ - " NOP \n" \ - " MCR p0,%[opcode],r3,c3,c0,%[machine] \n" ::[opcode] "i"(BATCH_OPCODE), \ - [machine] "i"(BATCH_MACHINE)) - -#define PQ_RUN_OPCODE_R4_R5(BATCH_OPCODE, BATCH_MACHINE) \ - __asm volatile( \ - " MCR p0,%[opcode],r4,c1,c0,%[machine] \n" \ - " NOP \n" \ - " MCR p0,%[opcode],r5,c3,c0,%[machine] \n" ::[opcode] "i"(BATCH_OPCODE), \ - [machine] "i"(BATCH_MACHINE)) - -#define PQ_RUN_OPCODE_R6_R7(BATCH_OPCODE, BATCH_MACHINE) \ - __asm volatile( \ - " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ - " NOP \n" \ - " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" ::[opcode] "i"(BATCH_OPCODE), \ - [machine] "i"(BATCH_MACHINE)) - -#define PQ_Vector8_FX(middle, last, BATCH_OPCODE, DOUBLE_READ_ADDERS, BATCH_MACHINE) \ - PQ_RUN_OPCODE_R2_R3(BATCH_OPCODE, BATCH_MACHINE); \ - if (middle) \ - { \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store fourth two results */ \ - } \ - __asm volatile("LDMIA r0!,{r4-r7}"); /* load next 4 datas */ \ - if (DOUBLE_READ_ADDERS) \ - { \ - __asm volatile("MRC p0,#0x1,r2,c1,c0,#0"); \ - __asm volatile("MRC p0,#0x1,r3,c3,c0,#0"); \ - } \ - else \ - { \ - __asm volatile("MRC p0,#0,r2,c1,c0,#0"); \ - __asm volatile("MRC p0,#0,r3,c3,c0,#0"); \ - } \ - PQ_RUN_OPCODE_R4_R5(BATCH_OPCODE, BATCH_MACHINE); \ - __asm volatile("STRD r2,r3,[r1],#8"); /* store first two results */ \ - if (DOUBLE_READ_ADDERS) \ - { \ - __asm volatile("MRC p0,#0x1,r4,c1,c0,#0"); \ - __asm volatile("MRC p0,#0x1,r5,c3,c0,#0"); \ - } \ - else \ - { \ - __asm volatile("MRC p0,#0,r4,c1,c0,#0"); \ - __asm volatile("MRC p0,#0,r5,c3,c0,#0"); \ - } \ - PQ_RUN_OPCODE_R6_R7(BATCH_OPCODE, BATCH_MACHINE); \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store second two results */ \ - __asm volatile("LDRD r4,r5,[r0],#8"); /* load last 2 of the 8 */ \ - if (DOUBLE_READ_ADDERS) \ - { \ - __asm volatile("MRC p0,#0x1,r6,c1,c0,#0"); \ - __asm volatile("MRC p0,#0x1,r7,c3,c0,#0"); \ - } \ - else \ - { \ - __asm volatile("MRC p0,#0,r6,c1,c0,#0"); \ - __asm volatile("MRC p0,#0,r7,c3,c0,#0"); \ - } \ - PQ_RUN_OPCODE_R4_R5(BATCH_OPCODE, BATCH_MACHINE); \ - __asm volatile("STRD r6,r7,[r1],#8"); /* store third two results */ \ - if (!last) \ - __asm volatile("LDRD r2,r3,[r0],#8"); /* load first two of next 8 */ \ - if (DOUBLE_READ_ADDERS) \ - { \ - __asm volatile("MRC p0,#0x1,r4,c1,c0,#0"); \ - __asm volatile("MRC p0,#0x1,r5,c3,c0,#0"); \ - } \ - else \ - { \ - __asm volatile("MRC p0,#0,r4,c1,c0,#0"); \ - __asm volatile("MRC p0,#0,r5,c3,c0,#0"); \ - } \ - if (last) \ - { \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store fourth two results */ \ - } - -/*! - * @brief Start 32-bit data vector calculation. - * - * Start the vector calculation, the input data could be float, int32_t or Q31. - * - * @param pSrc Pointer to the source data. - * @param pDst Pointer to the destination data. - */ -#define PQ_Initiate_Vector_Func(pSrc, pDst) \ - __asm volatile( \ - "MOV r0, %[psrc] \n" \ - "MOV r1, %[pdst] \n" \ - "PUSH {r2-r7} \n" \ - "LDRD r2,r3,[r0],#8 \n" ::[psrc] "r"(pSrc), \ - [pdst] "r"(pDst) \ - : "r0", "r1") - -/*! - * @brief End vector calculation. - * - * This function should be called after vector calculation. - */ -#define PQ_End_Vector_Func() __asm volatile("POP {r2-r7}") - -/* - * Register assignment for the vector calculation assembly. - * r0: pSrc, r1: pDest, r2: length, r3: middle, r4-r9: Data, r10:dra - */ - -/*! - * @brief Start 32-bit data vector calculation. - * - * Start the vector calculation, the input data could be float, int32_t or Q31. - * - * @param PSRC Pointer to the source data. - * @param PDST Pointer to the destination data. - * @param LENGTH Number of the data, must be multiple of 8. - */ -#define PQ_StartVector(PSRC, PDST, LENGTH) \ - __asm volatile( \ - "MOV r0, %[psrc] \n" \ - "MOV r1, %[pdst] \n" \ - "MOV r2, %[length] \n" \ - "PUSH {r3-r10} \n" \ - "MOV r3, #0 \n" \ - "MOV r10, #0 \n" \ - "LDRD r4,r5,[r0],#8 \n" ::[psrc] "r"(PSRC), \ - [pdst] "r"(PDST), [length] "r"(LENGTH) \ - : "r0", "r1", "r2") - -/*! - * @brief Start 16-bit data vector calculation. - * - * Start the vector calculation, the input data could be int16_t. This function - * should be use with @ref PQ_Vector8Fixed16. - * - * @param PSRC Pointer to the source data. - * @param PDST Pointer to the destination data. - * @param LENGTH Number of the data, must be multiple of 8. - */ -#define PQ_StartVectorFixed16(PSRC, PDST, LENGTH) \ - __asm volatile( \ - "MOV r0, %[psrc] \n" \ - "MOV r1, %[pdst] \n" \ - "MOV r2, %[length] \n" \ - "PUSH {r3-r10} \n" \ - "MOV r3, #0 \n" \ - "LDRSH r4,[r0],#2 \n" \ - "LDRSH r5,[r0],#2 \n" ::[psrc] "r"(PSRC), \ - [pdst] "r"(PDST), [length] "r"(LENGTH) \ - : "r0", "r1", "r2") - -/*! - * @brief Start Q15-bit data vector calculation. - * - * Start the vector calculation, the input data could be Q15. This function - * should be use with @ref PQ_Vector8Q15. This function is dedicate for - * SinQ15/CosQ15 vector calculation. Because PowerQuad only supports Q31 Sin/Cos - * fixed function, so the input Q15 data is left shift 16 bits first, after - * Q31 calculation, the output data is right shift 16 bits. - * - * @param PSRC Pointer to the source data. - * @param PDST Pointer to the destination data. - * @param LENGTH Number of the data, must be multiple of 8. - */ -#define PQ_StartVectorQ15(PSRC, PDST, LENGTH) \ - __asm volatile( \ - "MOV r0, %[psrc] \n" \ - "MOV r1, %[pdst] \n" \ - "MOV r2, %[length] \n" \ - "PUSH {r3-r10} \n" \ - "MOV r3, #0 \n" \ - "LDR r5,[r0],#4 \n" \ - "LSL r4,r5,#16 \n" \ - "BFC r5,#0,#16 \n" ::[psrc] "r"(PSRC), \ - [pdst] "r"(PDST), [length] "r"(LENGTH) \ - : "r0", "r1", "r2") - -/*! - * @brief End vector calculation. - * - * This function should be called after vector calculation. - */ -#define PQ_EndVector() __asm volatile("POP {r3-r10} \n") - -/*! - * @brief Float data vector calculation. - * - * Float data vector calculation, the input data should be float. The parameter - * could be PQ_LN_INF, PQ_INV_INF, PQ_SQRT_INF, PQ_ISQRT_INF, PQ_ETOX_INF, PQ_ETONX_INF. - * For example, to calculate sqrt of a vector, use like this: - * @code - #define VECTOR_LEN 8 - float input[VECTOR_LEN] = {1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0}; - float output[VECTOR_LEN]; - - PQ_StartVector(input, output, VECTOR_LEN); - PQ_Vector8F32(PQ_SQRT_INF); - PQ_EndVector(); - @endcode - * - */ -#define PQ_Vector8F32(BATCH_OPCODE, DOUBLE_READ_ADDERS, BATCH_MACHINE) \ - __asm volatile( \ - "1: \n" \ - " MCR p0,%[opcode],r5,c2,c0,%[machine] \n" \ - " MCR p0,%[opcode],r4,c0,c0,%[machine] \n" \ - " CMP r3, #0 \n" \ - " ITE NE \n" \ - " STRDNE r6,r7,[r1],#8 \n" /* store fourth two results */ \ - " MOVEQ r3, #1 \n" /* middle = 1 */ \ - " LDMIA r0!,{r6-r9} \n" /* load next 4 datas */ \ - " MOV r10,%[dra] \n" \ - " CMP r10, #0 \n" \ - " ITE NE \n" \ - " MRRCNE p0,#0,r4,r5,c1 \n" \ - " MRRCEQ p0,#0,r4,r5,c0 \n" \ - " MCR p0,%[opcode],r7,c2,c0,%[machine] \n" \ - " MCR p0,%[opcode],r6,c0,c0,%[machine] \n" \ - " STRD r4,r5,[r1],#8 \n" /* store first two results */ \ - " MOV r10,%[dra] \n" \ - " CMP r10, #0 \n" \ - " ITE NE \n" \ - " MRRCNE p0,#0,r6,r7,c1 \n" \ - " MRRCEQ p0,#0,r6,r7,c0 \n" \ - " MCR p0,%[opcode],r9,c2,c0,%[machine] \n" \ - " MCR p0,%[opcode],r8,c0,c0,%[machine] \n" \ - " STRD r6,r7,[r1],#8 \n" /* store second two results */ \ - " LDRD r6,r7,[r0],#8 \n" /* load last 2 of the 8 */ \ - " CMP r10, #0 \n" \ - " ITE NE \n" \ - " MRRCNE p0,#0,r8,r9,c1 \n" \ - " MRRCEQ p0,#0,r8,r9,c0 \n" \ - " MCR p0,%[opcode],r7,c2,c0,%[machine] \n" \ - " MCR p0,%[opcode],r6,c0,c0,%[machine] \n" \ - " STRD r8,r9,[r1],#8 \n" /* store third two results */ \ - " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ - " IT NE \n" \ - " LDRDNE r4,r5,[r0],#8 \n" /* load first two of next 8 */ \ - " CMP r10, #0 \n" \ - " ITE NE \n" \ - " MRRCNE p0,#0,r6,r7,c1 \n" \ - " MRRCEQ p0,#0,r6,r7,c0 \n" \ - " CMP r2, #0 \n" /* if (length == 0) */ \ - " BNE 1b \n" \ - " STRD r6,r7,[r1],#8 \n" /* store fourth two results */ \ - ::[opcode] "i"(BATCH_OPCODE), \ - [dra] "i"(DOUBLE_READ_ADDERS), [machine] "i"(BATCH_MACHINE)) - -/*! - * @brief Fixed 32bits data vector calculation. - * - * Float data vector calculation, the input data should be 32-bit integer. The parameter - * could be PQ_LN_INF, PQ_INV_INF, PQ_SQRT_INF, PQ_ISQRT_INF, PQ_ETOX_INF, PQ_ETONX_INF. - * PQ_SIN_INF, PQ_COS_INF. When this function is used for sin/cos calculation, the input - * data should be in the format Q1.31. - * For example, to calculate sqrt of a vector, use like this: - * @code - #define VECTOR_LEN 8 - int32_t input[VECTOR_LEN] = {1, 4, 9, 16, 25, 36, 49, 64}; - int32_t output[VECTOR_LEN]; - - PQ_StartVector(input, output, VECTOR_LEN); - PQ_Vector8F32(PQ_SQRT_INF); - PQ_EndVector(); - @endcode - * - */ -#define PQ_Vector8Fixed32(BATCH_OPCODE, DOUBLE_READ_ADDERS, BATCH_MACHINE) \ - __asm volatile( \ - "1: \n" \ - " MCR p0,%[opcode],r4,c1,c0,%[machine] \n" \ - " NOP \n" \ - " MCR p0,%[opcode],r5,c3,c0,%[machine] \n" \ - " CMP r3, #0 \n" \ - " ITE NE \n" \ - " STRDNE r6,r7,[r1],#8 \n" /* store fourth two results */ \ - " MOVEQ r3, #1 \n" /* middle = 1 */ \ - " LDMIA r0!,{r6-r9} \n" /* load next 4 datas */ \ - " MRC p0,%[dra],r4,c1,c0,#0 \n" \ - " MRC p0,%[dra],r5,c3,c0,#0 \n" \ - " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ - " NOP \n" \ - " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ - " STRD r4,r5,[r1],#8 \n" /* store first two results */ \ - " MRC p0,%[dra],r6,c1,c0,#0 \n" \ - " MRC p0,%[dra],r7,c3,c0,#0 \n" \ - " MCR p0,%[opcode],r8,c1,c0,%[machine] \n" \ - " NOP \n" \ - " MCR p0,%[opcode],r9,c3,c0,%[machine] \n" \ - " STRD r6,r7,[r1],#8 \n" /* store second two results */ \ - " LDRD r6,r7,[r0],#8 \n" /* load last 2 of the 8 */ \ - " MRC p0,%[dra],r8,c1,c0,#0 \n" \ - " MRC p0,%[dra],r9,c3,c0,#0 \n" \ - " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ - " NOP \n" \ - " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ - " STRD r8,r9,[r1],#8 \n" /* store third two results */ \ - " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ - " IT NE \n" \ - " LDRDNE r4,r5,[r0],#8 \n" /* load first two of next 8 */ \ - " MRC p0,%[dra],r6,c1,c0,#0 \n" \ - " MRC p0,%[dra],r7,c3,c0,#0 \n" \ - " CMP r2, #0 \n" /* if (length == 0) */ \ - " BNE 1b \n" \ - " STRD r6,r7,[r1],#8 \n" /* store fourth two results */ \ - ::[opcode] "i"(BATCH_OPCODE), \ - [dra] "i"(DOUBLE_READ_ADDERS), [machine] "i"(BATCH_MACHINE)) - -/*! - * @brief Fixed 32bits data vector calculation. - * - * Float data vector calculation, the input data should be 16-bit integer. The parameter - * could be PQ_LN_INF, PQ_INV_INF, PQ_SQRT_INF, PQ_ISQRT_INF, PQ_ETOX_INF, PQ_ETONX_INF. - * For example, to calculate sqrt of a vector, use like this: - * @code - #define VECTOR_LEN 8 - int16_t input[VECTOR_LEN] = {1, 4, 9, 16, 25, 36, 49, 64}; - int16_t output[VECTOR_LEN]; - - PQ_StartVector(input, output, VECTOR_LEN); - PQ_Vector8F32(PQ_SQRT_INF); - PQ_EndVector(); - @endcode - * - */ -#define PQ_Vector8Fixed16(BATCH_OPCODE, DOUBLE_READ_ADDERS, BATCH_MACHINE) \ - __asm volatile( \ - "1: \n" \ - " MCR p0,%[opcode],r4,c1,c0,%[machine] \n" \ - " MCR p0,%[opcode],r5,c3,c0,%[machine] \n" \ - " CMP r3, #0 \n" \ - " ITTE NE \n" \ - " STRHNE r6,[r1],#2 \n" /* store fourth two results */ \ - " STRHNE r7,[r1],#2 \n" /* store fourth two results */ \ - " MOVEQ r3, #1 \n" /* middle = 1 */ \ - " LDRSH r6,[r0],#2 \n" /* load next 2 of the 8 */ \ - " LDRSH r7,[r0],#2 \n" /* load next 2 of the 8 */ \ - " MRC p0,%[dra],r4,c1,c0,#0 \n" \ - " MRC p0,%[dra],r5,c3,c0,#0 \n" \ - " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ - " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ - " STRH r4,[r1],#2 \n" /* store first two results */ \ - " STRH r5,[r1],#2 \n" /* store first two results */ \ - " LDRSH r8,[r0],#2 \n" /* load next 2 of the 8 */ \ - " LDRSH r9,[r0],#2 \n" /* load next 2 of the 8 */ \ - " MRC p0,%[dra],r6,c1,c0,#0 \n" \ - " MRC p0,%[dra],r7,c3,c0,#0 \n" \ - " MCR p0,%[opcode],r8,c1,c0,%[machine] \n" \ - " MCR p0,%[opcode],r9,c3,c0,%[machine] \n" \ - " STRH r6,[r1],#2 \n" /* store second two results */ \ - " STRH r7,[r1],#2 \n" /* store second two results */ \ - " LDRSH r6,[r0],#2 \n" /* load last 2 of the 8 */ \ - " LDRSH r7,[r0],#2 \n" /* load last 2 of the 8 */ \ - " MRC p0,%[dra],r8,c1,c0,#0 \n" \ - " MRC p0,%[dra],r9,c3,c0,#0 \n" \ - " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ - " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ - " STRH r8,[r1],#2 \n" /* store third two results */ \ - " STRH r9,[r1],#2 \n" /* store third two results */ \ - " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ - " ITT NE \n" \ - " LDRSHNE r4,[r0],#2 \n" /* load first two of next 8 */ \ - " LDRSHNE r5,[r0],#2 \n" /* load first two of next 8 */ \ - " MRC p0,%[dra],r6,c1,c0,#0 \n" \ - " MRC p0,%[dra],r7,c3,c0,#0 \n" \ - " CMP r2, #0 \n" /* if (length == 0) */ \ - " BNE 1b \n" \ - " STRH r6,[r1],#2 \n" /* store fourth two results */ \ - " STRH r7,[r1],#2 \n" /* store fourth two results */ \ - ::[opcode] "i"(BATCH_OPCODE), \ - [dra] "i"(DOUBLE_READ_ADDERS), [machine] "i"(BATCH_MACHINE)) - -/*! - * @brief Q15 data vector calculation. - * - * Q15 data vector calculation, this function should only be used for sin/cos Q15 calculation, - * and the coprocessor output prescaler must be set to 31 before this function. This function - * loads Q15 data and left shift 16 bits, calculate and right shift 16 bits, then stores to - * the output array. The input range -1 to 1 means -pi to pi. - * For example, to calculate sin of a vector, use like this: - * @code - #define VECTOR_LEN 8 - int16_t input[VECTOR_LEN] = {...} - int16_t output[VECTOR_LEN]; - const pq_prescale_t prescale = - { - .inputPrescale = 0, - .outputPrescale = 31, - .outputSaturate = 0 - }; - - PQ_SetCoprocessorScaler(POWERQUAD, const pq_prescale_t *prescale); - - PQ_StartVectorQ15(pSrc, pDst, length); - PQ_Vector8Q15(PQ_SQRT_INF); - PQ_EndVector(); - @endcode - * - */ -#define PQ_Vector8Q15(BATCH_OPCODE, DOUBLE_READ_ADDERS, BATCH_MACHINE) \ - __asm volatile( \ - "1: \n" \ - " MCR p0,%[opcode],r4,c1,c0,%[machine] \n" \ - " NOP \n" \ - " MCR p0,%[opcode],r5,c3,c0,%[machine] \n" \ - " CMP r3, #0 \n" \ - " ITTTE NE \n" \ - " LSRNE r6,r6,#16 \n" /* store fourth two results */ \ - " BFINE r7,r6,#0,#16 \n" /* store fourth two results */ \ - " STRNE r7,[r1],#4 \n" /* store fourth two results */ \ - " MOVEQ r3, #1 \n" /* middle = 1 */ \ - " LDR r7,[r0],#4 \n" /* load next 2 of the 8 */ \ - " LSL r6,r7,#16 \n" /* load next 2 of the 8 */ \ - " BFC r7,#0,#16 \n" /* load next 2 of the 8 */ \ - " MRC p0,%[dra],r4,c1,c0,#0 \n" \ - " MRC p0,%[dra],r5,c3,c0,#0 \n" \ - " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ - " NOP \n" \ - " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ - " LSR r4,r4,#16 \n" /* store first two results */ \ - " BFI r5,r4,#0,#16 \n" /* store first two results */ \ - " STR r5,[r1],#4 \n" /* store first two results */ \ - " LDR r9,[r0],#4 \n" /* load next 2 of the 8 */ \ - " LSL r8,r9,#16 \n" /* load next 2 of the 8 */ \ - " BFC r9,#0,#16 \n" /* load next 2 of the 8 */ \ - " MRC p0,%[dra],r6,c1,c0,#0 \n" \ - " MRC p0,%[dra],r7,c3,c0,#0 \n" \ - " MCR p0,%[opcode],r8,c1,c0,%[machine] \n" \ - " NOP \n" \ - " MCR p0,%[opcode],r9,c3,c0,%[machine] \n" \ - " LSR r6,r6,#16 \n" /* store second two results */ \ - " BFI r7,r6,#0,#16 \n" /* store second two results */ \ - " STR r7,[r1],#4 \n" /* store second two results */ \ - " LDR r7,[r0],#4 \n" /* load next 2 of the 8 */ \ - " LSL r6,r7,#16 \n" /* load next 2 of the 8 */ \ - " BFC r7,#0,#16 \n" /* load next 2 of the 8 */ \ - " MRC p0,%[dra],r8,c1,c0,#0 \n" \ - " MRC p0,%[dra],r9,c3,c0,#0 \n" \ - " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ - " NOP \n" \ - " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ - " LSR r8,r8,#16 \n" /* store third two results */ \ - " BFI r9,r8,#0,#16 \n" /* store third two results */ \ - " STR r9,[r1],#4 \n" /* store third two results */ \ - " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ - " ITTT NE \n" \ - " LDRNE r5,[r0],#4 \n" /* load next 2 of the 8 */ \ - " LSLNE r4,r5,#16 \n" /* load next 2 of the 8 */ \ - " BFCNE r5,#0,#16 \n" /* load next 2 of the 8 */ \ - " MRC p0,%[dra],r6,c1,c0,#0 \n" \ - " MRC p0,%[dra],r7,c3,c0,#0 \n" \ - " CMP r2, #0 \n" /* if (length == 0) */ \ - " BNE 1b \n" \ - " LSR r6,r6,#16 \n" /* store fourth two results */ \ - " BFI r7,r6,#0,#16 \n" /* store fourth two results */ \ - " STR r7,[r1],#4 \n" /* store fourth two results */ \ - ::[opcode] "i"(BATCH_OPCODE), \ - [dra] "i"(DOUBLE_READ_ADDERS), [machine] "i"(BATCH_MACHINE)) - -/*! - * @brief Float data vector biquad direct form II calculation. - * - * Biquad filter, the input and output data are float data. Biquad side 0 is used. Example: - * @code - #define VECTOR_LEN 16 - float input[VECTOR_LEN] = {1024.0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - float output[VECTOR_LEN]; - pq_biquad_state_t state = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state); - - PQ_Initiate_Vector_Func(pSrc,pDst); - PQ_DF2_Vector8_FP(false,false); - PQ_DF2_Vector8_FP(true,true); - PQ_End_Vector_Func(); - @endcode - * - */ -#define PQ_DF2_Vector8_FP(middle, last) \ - __asm volatile("MCR p0,#0x1,r2,c0,c0,#6"); /* write biquad0*/ \ - if (middle) \ - { \ - __asm volatile("STR r5,[r1],#4"); /* store last result*/ \ - } \ - __asm volatile("LDRD r4,r5,[r0],#8"); /* load next 2 datas */ \ - __asm volatile("MRC p0,#0x1,r2,c0,c0,#0"); /* read biquad0*/ \ - __asm volatile("MCR p0,#0x1,r3,c0,c0,#6"); /* write biquad0 */ \ - __asm volatile("MRC p0,#0x1,r3,c0,c0,#0"); /* read biquad0*/ \ - __asm volatile("MCR p0,#0x1,r4,c0,c0,#6"); /* write biquad0 */ \ - __asm volatile("STRD r2,r3,[r1],#8"); /* store first 2 results */ \ - __asm volatile("MRC p0,#0x1,r4,c0,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r5,c0,c0,#6"); \ - __asm volatile("LDRD r6,r7,[r0],#8"); /* load next 2 datas */ \ - __asm volatile("MRC p0,#0x1,r5,c0,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r6,c0,c0,#6"); \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store next 2 results */ \ - __asm volatile("MRC p0,#0x1,r6,c0,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r7,c0,c0,#6"); \ - __asm volatile("LDRD r4,r5,[r0],#8"); /* load next 2 datas */ \ - __asm volatile("MRC p0,#0x1,r7,c0,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r4,c0,c0,#6"); \ - __asm volatile("STRD r6,r7,[r1],#8"); /* store next 2 results */ \ - __asm volatile("MRC p0,#0x1,r4,c0,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r5,c0,c0,#6"); \ - if (!last) \ - { \ - __asm volatile("LDRD r2,r3,[r0],#8"); /* load first two of next 8 */ \ - } \ - __asm volatile("STR r4,[r1],#4"); \ - __asm volatile("MRC p0,#0x1,r5,c0,c0,#0"); \ - if (last) \ - { \ - __asm volatile("STR r5,[r1],#4"); /* store last result */ \ - } - -/*! - * @brief Fixed data vector biquad direct form II calculation. - * - * Biquad filter, the input and output data are fixed data. Biquad side 0 is used. Example: - * @code - #define VECTOR_LEN 16 - int32_t input[VECTOR_LEN] = {1024, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - int32_t output[VECTOR_LEN]; - pq_biquad_state_t state = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state); - - PQ_Initiate_Vector_Func(pSrc,pDst); - PQ_DF2_Vector8_FX(false,false); - PQ_DF2_Vector8_FX(true,true); - PQ_End_Vector_Func(); - @endcode - * - */ -#define PQ_DF2_Vector8_FX(middle, last) \ - __asm volatile("MCR p0,#0x1,r2,c1,c0,#6"); /* write biquad0*/ \ - if (middle) \ - { \ - __asm volatile("STR r5,[r1],#4"); /* store last result*/ \ - } \ - __asm volatile("LDRD r4,r5,[r0],#8"); /* load next 2 datas */ \ - __asm volatile("MRC p0,#0x1,r2,c1,c0,#0"); /* read biquad0*/ \ - __asm volatile("MCR p0,#0x1,r3,c1,c0,#6"); /* write biquad0 */ \ - __asm volatile("MRC p0,#0x1,r3,c1,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r4,c1,c0,#6"); \ - __asm volatile("STRD r2,r3,[r1],#8"); /* store first 2 results */ \ - __asm volatile("MRC p0,#0x1,r4,c1,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r5,c1,c0,#6"); \ - __asm volatile("LDRD r6,r7,[r0],#8"); \ - __asm volatile("MRC p0,#0x1,r5,c1,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r6,c1,c0,#6"); \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store next 2 results */ \ - __asm volatile("MRC p0,#0x1,r6,c1,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r7,c1,c0,#6"); \ - __asm volatile("LDRD r4,r5,[r0],#8"); \ - __asm volatile("MRC p0,#0x1,r7,c1,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r4,c1,c0,#6"); \ - __asm volatile("STRD r6,r7,[r1],#8"); /* store next 2 results */ \ - __asm volatile("MRC p0,#0x1,r4,c1,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r5,c1,c0,#6"); \ - if (!last) \ - { \ - __asm volatile("LDRD r2,r3,[r0],#8"); /* load two of next 8 */ \ - } \ - __asm volatile("STR r4,[r1],#4"); /* store 7th results */ \ - __asm volatile("MRC p0,#0x1,r5,c1,c0,#0"); \ - if (last) \ - { \ - __asm volatile("STR r5,[r1],#4"); /* store last result */ \ - } - -/*! - * @brief Float data vector biquad direct form II calculation. - * - * Biquad filter, the input and output data are float data. Biquad side 0 is used. Example: - * @code - #define VECTOR_LEN 8 - float input[VECTOR_LEN] = {1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0}; - float output[VECTOR_LEN]; - pq_biquad_state_t state = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state); - - PQ_StartVector(input, output, VECTOR_LEN); - PQ_Vector8BiquadDf2F32(); - PQ_EndVector(); - @endcode - * - */ -#define PQ_Vector8BiquadDf2F32() \ - __asm volatile( \ - "1: \n" \ - " MCR p0,#0x1,r4,c0,c0,#6 \n" /* write biquad0*/ \ - " CMP r3, #0 \n" \ - " ITE NE \n" \ - " STRNE r7,[r1],#4 \n" /* store last result*/ \ - " MOVEQ r3, #1 \n" /* middle = 1 */ \ - " LDMIA r0!,{r6-r9} \n" /* load next 4 datas */ \ - " MRC p0,#0x1,r4,c0,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r5,c0,c0,#6 \n" /* write biquad0 */ \ - " MRC p0,#0x1,r5,c0,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r6,c0,c0,#6 \n" /* write biquad0 */ \ - " MRC p0,#0x1,r6,c0,c0,#0 \n" /* read biquad0 */ \ - " MCR p0,#0x1,r7,c0,c0,#6 \n" /* write biquad0 */ \ - " MRC p0,#0x1,r7,c0,c0,#0 \n" /* read biquad0 */ \ - " MCR p0,#0x1,r8,c0,c0,#6 \n" /* write biquad0*/ \ - " STMIA r1!,{r4-r7} \n" /* store first four results */ \ - " MRC p0,#0x1,r8,c0,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r9,c0,c0,#6 \n" /* write biquad0*/ \ - " LDRD r6,r7,[r0],#8 \n" /* load next 2 items*/ \ - " MRC p0,#0x1,r9,c0,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r6,c0,c0,#6 \n" /* write biquad0*/ \ - " STRD r8,r9,[r1],#8 \n" /* store third two results */ \ - " MRC p0,#0x1,r6,c0,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r7,c0,c0,#6 \n" /* write biquad0*/ \ - " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ - " IT NE \n" \ - " LDRDNE r4,r5,[r0],#8 \n" /* load first two of next 8 */ \ - " STR r6,[r1],#4 \n" /* store 7th results */ \ - " MRC p0,#0x1,r7,c0,c0,#0 \n" /* read biquad0*/ \ - " CMP r2, #0 \n" /* if (length == 0) */ \ - " BNE 1b \n" \ - " STR r7,[r1],#4 \n" /* store last result */ \ - ) - -/*! - * @brief Fixed 32-bit data vector biquad direct form II calculation. - * - * Biquad filter, the input and output data are Q31 or 32-bit integer. Biquad side 0 is used. Example: - * @code - #define VECTOR_LEN 8 - int32_t input[VECTOR_LEN] = {1, 2, 3, 4, 5, 6, 7, 8}; - int32_t output[VECTOR_LEN]; - pq_biquad_state_t state = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state); - - PQ_StartVector(input, output, VECTOR_LEN); - PQ_Vector8BiquadDf2Fixed32(); - PQ_EndVector(); - @endcode - * - */ -#define PQ_Vector8BiquadDf2Fixed32() \ - __asm volatile( \ - "1: \n" \ - " MCR p0,#0x1,r4,c1,c0,#6 \n" /* write biquad0*/ \ - " CMP r3, #0 \n" \ - " ITE NE \n" \ - " STRNE r7,[r1],#4 \n" /* store last result*/ \ - " MOVEQ r3, #1 \n" /* middle = 1 */ \ - " LDMIA r0!,{r6-r9} \n" /* load next 4 datas */ \ - " MRC p0,#0x1,r4,c1,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r5,c1,c0,#6 \n" /* write biquad0 */ \ - " MRC p0,#0x1,r5,c1,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0 */ \ - " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0 */ \ - " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0 */ \ - " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0 */ \ - " MCR p0,#0x1,r8,c1,c0,#6 \n" /* write biquad0*/ \ - " STMIA r1!,{r4-r7} \n" /* store first four results */ \ - " MRC p0,#0x1,r8,c1,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r9,c1,c0,#6 \n" /* write biquad0*/ \ - " LDRD r6,r7,[r0],#8 \n" /* load next 2 items*/ \ - " MRC p0,#0x1,r9,c1,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0*/ \ - " STRD r8,r9,[r1],#8 \n" /* store third two results */ \ - " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ - " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ - " IT NE \n" \ - " LDRDNE r4,r5,[r0],#8 \n" /* load first two of next 8 */ \ - " STR r6,[r1],#4 \n" /* store 7th results */ \ - " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ - " CMP r2, #0 \n" /* if (length == 0) */ \ - " BNE 1b \n" \ - " STR r7,[r1],#4 \n" /* store last result */ \ - ) - -/*! - * @brief Fixed 16-bit data vector biquad direct form II calculation. - * - * Biquad filter, the input and output data are Q15 or 16-bit integer. Biquad side 0 is used. Example: - * @code - #define VECTOR_LEN 8 - int16_t input[VECTOR_LEN] = {1, 2, 3, 4, 5, 6, 7, 8}; - int16_t output[VECTOR_LEN]; - pq_biquad_state_t state = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state); - - PQ_StartVector(input, output, VECTOR_LEN); - PQ_Vector8BiquadDf2Fixed16(); - PQ_EndVector(); - @endcode - * - */ -#define PQ_Vector8BiquadDf2Fixed16() \ - __asm volatile( \ - "1: \n" \ - " MCR p0,#0x1,r4,c1,c0,#6 \n" /* write biquad0*/ \ - " CMP r3, #0 \n" \ - " ITE NE \n" \ - " STRHNE r7,[r1],#2 \n" /* store last result*/ \ - " MOVEQ r3, #1 \n" /* middle = 1 */ \ - " LDRSH r6,[r0],#2 \n" /* load next 2 of the 8*/ \ - " LDRSH r7,[r0],#2 \n" /* load next 2 of the 8*/ \ - " MRC p0,#0x1,r4,c1,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r5,c1,c0,#6 \n" /* write biquad0 */ \ - " MRC p0,#0x1,r5,c1,c0,#0 \n" /* read biquad0*/ \ - " LDRSH r8,[r0],#2 \n" /* load next 2 of the 8*/ \ - " LDRSH r9,[r0],#2 \n" /* load next 2 of the 8*/ \ - " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0 */ \ - " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0 */ \ - " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0 */ \ - " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0 */ \ - " STRH r4,[r1],#2 \n" /* store first 4 results */ \ - " STRH r5,[r1],#2 \n" /* store first 4 results */ \ - " MCR p0,#0x1,r8,c1,c0,#6 \n" /* write biquad0*/ \ - " STRH r6,[r1],#2 \n" /* store first 4 results */ \ - " STRH r7,[r1],#2 \n" /* store first 4 results */ \ - " MRC p0,#0x1,r8,c1,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r9,c1,c0,#6 \n" /* write biquad0*/ \ - " LDRSH r6,[r0],#2 \n" /* load next 1 of the 8*/ \ - " LDRSH r7,[r0],#2 \n" /* load next 1 of the 8*/ \ - " MRC p0,#0x1,r9,c1,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0*/ \ - " STRH r8,[r1],#2 \n" /* store next two results */ \ - " STRH r9,[r1],#2 \n" /* store next two results */ \ - " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ - " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ - " ITT NE \n" \ - " LDRSHNE r4,[r0],#2 \n" /* load first two of next 8*/ \ - " LDRSHNE r5,[r0],#2 \n" /* load first two of next 8*/ \ - " STRH r6,[r1],#2 \n" /* store 7th results */ \ - " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ - " CMP r2, #0 \n" /* if (length == 0) */ \ - " BNE 1b \n" \ - " STRH r7,[r1],#2 \n" /* store last result */ \ - ) - -/*! - * @brief Float data vector direct form II biquad cascade filter. - * - * The input and output data are float data. The data flow is - * input -> biquad side 1 -> biquad side 0 -> output. - * - * @code - #define VECTOR_LEN 16 - float input[VECTOR_LEN] = {1024.0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - float output[VECTOR_LEN]; - pq_biquad_state_t state0 = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - pq_biquad_state_t state1 = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state0); - PQ_BiquadRestoreInternalState(POWERQUAD, 1, &state1); - - PQ_Initiate_Vector_Func(pSrc, pDst); - PQ_DF2_Cascade_Vector8_FP(false, false); - PQ_DF2_Cascade_Vector8_FP(true, true); - PQ_End_Vector_Func(); - @endcode - * - */ -#define PQ_DF2_Cascade_Vector8_FP(middle, last) \ - __asm volatile("MCR p0,#0x1,r2,c2,c0,#6"); /* write biquad1*/ \ - if (middle) \ - { \ - __asm volatile("MCR p0,#0x1,r5,c0,c0,#6"); /* write biquad0*/ \ - __asm volatile("MRRC p0,#0,r5,r2,c1"); /* read both biquad*/ \ - } \ - else \ - { \ - __asm volatile("MRC p0,#0x1,r2,c2,c0,#0"); /* read biquad1*/ \ - } \ - __asm volatile("MCR p0,#0x1,r3,c2,c0,#6"); /* write biquad1*/ \ - __asm volatile("MCR p0,#0x1,r2,c0,c0,#6"); /* write biquad0*/ \ - if (middle) \ - { \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store last two results*/ \ - } \ - __asm volatile("LDRD r4,r5,[r0],#8"); /* load next 2 datas */ \ - __asm volatile("MRRC p0,#0,r2,r3,c1"); /* read both biquad*/ \ - __asm volatile("MCR p0,#0x1,r4,c2,c0,#6"); /* write biquad1*/ \ - __asm volatile("MCR p0,#0x1,r3,c0,c0,#6"); /* write biquad0*/ \ - __asm volatile("LDRD r6,r7,[r0],#8"); \ - __asm volatile("MRRC p0,#0,r3,r4,c1"); \ - __asm volatile("MCR p0,#0x1,r5,c2,c0,#6"); \ - __asm volatile("MCR p0,#0x1,r4,c0,c0,#6"); \ - __asm volatile("STRD r2,r3,[r1],#8"); /* store first two results */ \ - __asm volatile("MRRC p0,#0,r4,r5,c1"); \ - __asm volatile("MCR p0,#0x1,r6,c2,c0,#6"); \ - __asm volatile("MCR p0,#0x1,r5,c0,c0,#6"); \ - __asm volatile("STR r4,[r1],#4"); \ - __asm volatile("MRRC p0,#0,r5,r6,c1"); \ - __asm volatile("MCR p0,#0x1,r7,c2,c0,#6"); \ - __asm volatile("MCR p0,#0x1,r6,c0,c0,#6"); \ - __asm volatile("STR r5,[r1],#4"); \ - __asm volatile("LDRD r4,r5,[r0],#8"); \ - __asm volatile("MRRC p0,#0,r6,r7,c1"); \ - __asm volatile("MCR p0,#0x1,r4,c2,c0,#6"); \ - __asm volatile("MCR p0,#0x1,r7,c0,c0,#6"); \ - if (!last) \ - { \ - __asm volatile("LDRD r2,r3,[r0],#8"); /* load first two of next 8 */ \ - } \ - __asm volatile("MRRC p0,#0,r7,r4,c1"); \ - __asm volatile("MCR p0,#0x1,r5,c2,c0,#6"); \ - __asm volatile("MCR p0,#0x1,r4,c0,c0,#6"); \ - __asm volatile("STRD r6,r7,[r1],#8"); /* store third two results */ \ - __asm volatile("MRRC p0,#0,r4,r5,c1"); \ - if (last) \ - { \ - __asm volatile("MCR p0,#0x1,r5,c0,c0,#6"); /* write biquad0*/ \ - __asm volatile("MRC p0,#0x1,r5,c0,c0,#0"); /* read biquad0*/ \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store fourth two results */ \ - } - -/*! - * @brief Fixed data vector direct form II biquad cascade filter. - * - * The input and output data are fixed data. The data flow is - * input -> biquad side 1 -> biquad side 0 -> output. - * - * @code - #define VECTOR_LEN 16 - int32_t input[VECTOR_LEN] = {1024.0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - int32_t output[VECTOR_LEN]; - pq_biquad_state_t state0 = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - pq_biquad_state_t state1 = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state0); - PQ_BiquadRestoreInternalState(POWERQUAD, 1, &state1); - - PQ_Initiate_Vector_Func(pSrc, pDst); - PQ_DF2_Cascade_Vector8_FX(false, false); - PQ_DF2_Cascade_Vector8_FX(true, true); - PQ_End_Vector_Func(); - @endcode - * - */ -#define PQ_DF2_Cascade_Vector8_FX(middle, last) \ - __asm volatile("MCR p0,#0x1,r2,c3,c0,#6"); /* write biquad1*/ \ - if (middle) \ - { \ - __asm volatile("MCR p0,#0x1,r5,c1,c0,#6"); /* write biquad0*/ \ - __asm volatile("MRC p0,#0x1,r5,c1,c0,#0"); /* read biquad0*/ \ - __asm volatile("MRC p0,#0x1,r2,c3,c0,#0"); /* read biquad1*/ \ - } \ - else \ - { \ - __asm volatile("MRC p0,#0x1,r2,c3,c0,#0"); /* read biquad1*/ \ - } \ - __asm volatile("MCR p0,#0x1,r3,c3,c0,#6"); /* write biquad1*/ \ - __asm volatile("MCR p0,#0x1,r2,c1,c0,#6"); /* write biquad0*/ \ - if (middle) \ - { \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store last two results*/ \ - } \ - __asm volatile("LDRD r4,r5,[r0],#8"); /* load next 2 datas */ \ - __asm volatile("MRC p0,#0x1,r2,c1,c0,#0"); /* read biquad0*/ \ - __asm volatile("MRC p0,#0x1,r3,c3,c0,#0"); /* read biquad1*/ \ - __asm volatile("MCR p0,#0x1,r4,c3,c0,#6"); /* write biquad1*/ \ - __asm volatile("MCR p0,#0x1,r3,c1,c0,#6"); /* write biquad0*/ \ - __asm volatile("LDRD r6,r7,[r0],#8"); \ - __asm volatile("MRC p0,#0x1,r3,c1,c0,#0"); \ - __asm volatile("MRC p0,#0x1,r4,c3,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r5,c3,c0,#6"); \ - __asm volatile("MCR p0,#0x1,r4,c1,c0,#6"); \ - __asm volatile("STRD r2,r3,[r1],#8"); \ - __asm volatile("MRC p0,#0x1,r4,c1,c0,#0"); \ - __asm volatile("MRC p0,#0x1,r5,c3,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r6,c3,c0,#6"); \ - __asm volatile("MCR p0,#0x1,r5,c1,c0,#6"); \ - __asm volatile("STR r4,[r1],#4"); \ - __asm volatile("MRC p0,#0x1,r5,c1,c0,#0"); \ - __asm volatile("MRC p0,#0x1,r6,c3,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r7,c3,c0,#6"); \ - __asm volatile("MCR p0,#0x1,r6,c1,c0,#6"); \ - __asm volatile("STR r5,[r1],#4"); \ - __asm volatile("LDRD r4,r5,[r0],#8"); \ - __asm volatile("MRC p0,#0x1,r6,c1,c0,#0"); \ - __asm volatile("MRC p0,#0x1,r7,c3,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r4,c3,c0,#6"); \ - __asm volatile("MCR p0,#0x1,r7,c1,c0,#6"); \ - if (!last) \ - { \ - __asm volatile("LDRD r2,r3,[r0],#8"); /* load first two of next 8 */ \ - } \ - __asm volatile("MRC p0,#0x1,r7,c1,c0,#0"); \ - __asm volatile("MRC p0,#0x1,r4,c3,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r5,c3,c0,#6"); \ - __asm volatile("MCR p0,#0x1,r4,c1,c0,#6"); \ - __asm volatile("STRD r6,r7,[r1],#8"); /* store third two results */ \ - __asm volatile("MRC p0,#0x1,r4,c1,c0,#0"); /* read biquad0*/ \ - __asm volatile("MRC p0,#0x1,r5,c3,c0,#0"); /* read biquad1*/ \ - if (last) \ - { \ - __asm volatile("MCR p0,#0x1,r5,c1,c0,#6"); /* write biquad0*/ \ - __asm volatile("MRC p0,#0x1,r5,c1,c0,#0"); /* read biquad0*/ \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store fourth two results */ \ - } - -/*! - * @brief Float data vector direct form II biquad cascade filter. - * - * The input and output data are float data. The data flow is - * input -> biquad side 1 -> biquad side 0 -> output. - * - * @code - #define VECTOR_LEN 8 - float input[VECTOR_LEN] = {1, 2, 3, 4, 5, 6, 7, 8}; - float output[VECTOR_LEN]; - pq_biquad_state_t state0 = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - pq_biquad_state_t state1 = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state0); - PQ_BiquadRestoreInternalState(POWERQUAD, 1, &state1); - - PQ_StartVector(input, output, VECTOR_LEN); - PQ_Vector8BiqaudDf2CascadeF32(); - PQ_EndVector(); - @endcode - * - */ -#define PQ_Vector8BiqaudDf2CascadeF32() \ - __asm volatile( \ - "1: \n" \ - " MCR p0,#0x1,r4,c2,c0,#2 \n" /* write biquad1*/ \ - " CMP r3, #0 \n" \ - " ITTE NE \n" \ - " MCRNE p0,#0x1,r7,c0,c0,#2 \n" /* write biquad0*/ \ - " MRRCNE p0,#0,r7,r4,c1 \n" /* read both biquad*/ \ - " MRCEQ p0,#0x1,r4,c2,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r5,c2,c0,#2 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r4,c0,c0,#2 \n" /* write biquad0*/ \ - " CMP r3, #0 \n" \ - " ITE NE \n" \ - " STRDNE r6,r7,[r1],#8 \n" /* store last two results*/ \ - " MOVEQ r3, #1 \n" /* middle = 1 */ \ - " LDMIA r0!,{r6-r9} \n" /* load next 4 datas */ \ - " MRRC p0,#0,r4,r5,c1 \n" /* read both biquad*/ \ - " MCR p0,#0x1,r6,c2,c0,#2 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r5,c0,c0,#2 \n" /* write biquad0*/ \ - " MRRC p0,#0,r5,r6,c1 \n" /* read both biquad*/ \ - " MCR p0,#0x1,r7,c2,c0,#2 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r6,c0,c0,#2 \n" /* write biquad0*/ \ - " MRRC p0,#0,r6,r7,c1 \n" /* read both biquad*/ \ - " MCR p0,#0x1,r8,c2,c0,#2 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r7,c0,c0,#2 \n" /* write biquad0*/ \ - " MRRC p0,#0,r7,r8,c1 \n" /* read both biquad*/ \ - " MCR p0,#0x1,r9,c2,c0,#2 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r8,c0,c0,#2 \n" /* write biquad0*/ \ - " STMIA r1!,{R4-R7} \n" /* store first and second two results */ \ - " LDRD r6,r7,[r0],#8 \n" /* load last 2 of the 8 */ \ - " MRRC p0,#0,r8,r9,c1 \n" /* read both biquad*/ \ - " MCR p0,#0x1,r6,c2,c0,#2 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r9,c0,c0,#2 \n" /* write biquad0*/ \ - " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ - " IT NE \n" \ - " LDRDNE r4,r5,[r0],#8 \n" /* load first two of next 8 */ \ - " MRRC p0,#0,r9,r6,c1 \n" /* read both biquad*/ \ - " MCR p0,#0x1,r7,c2,c0,#2 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r6,c0,c0,#2 \n" /* write biquad0*/ \ - " STRD r8,r9,[r1],#8 \n" /* store third two results */ \ - " MRRC p0,#0,r6,r7,c1 \n" /* read both biquad*/ \ - " CMP r2, #0 \n" /* if (length == 0) */ \ - " BNE 1b \n" \ - " MCR p0,#0x1,r7,c0,c0,#2 \n" /* write biquad0*/ \ - " MRC p0,#0x1,r7,c0,c0,#0 \n" /* read biquad0*/ \ - " STRD r6,r7,[r1],#8 \n" /* store fourth two results */ \ - ) - -/*! - * @brief Fixed 32-bit data vector direct form II biquad cascade filter. - * - * The input and output data are fixed 32-bit data. The data flow is - * input -> biquad side 1 -> biquad side 0 -> output. - * - * @code - #define VECTOR_LEN 8 - int32_t input[VECTOR_LEN] = {1, 2, 3, 4, 5, 6, 7, 8}; - int32_t output[VECTOR_LEN]; - pq_biquad_state_t state0 = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - pq_biquad_state_t state1 = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state0); - PQ_BiquadRestoreInternalState(POWERQUAD, 1, &state1); - - PQ_StartVector(input, output, VECTOR_LEN); - PQ_Vector8BiqaudDf2CascadeFixed32(); - PQ_EndVector(); - @endcode - * - */ -#define PQ_Vector8BiqaudDf2CascadeFixed32() \ - __asm volatile( \ - "1: \n" \ - " MCR p0,#0x1,r4,c3,c0,#6 \n" /* write biquad1*/ \ - " CMP r3, #0 \n" \ - " ITTTE NE \n" \ - " MCRNE p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ - " MRCNE p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ - " MRCNE p0,#0x1,r4,c3,c0,#0 \n" /* read biquad1*/ \ - " MRCEQ p0,#0x1,r4,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r5,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r4,c1,c0,#6 \n" /* write biquad0*/ \ - " CMP r3, #0 \n" \ - " ITE NE \n" \ - " STRDNE r6,r7,[r1],#8 \n" /* store last two results*/ \ - " MOVEQ r3, #1 \n" /* middle = 1 */ \ - " LDMIA r0!,{r6-r9} \n" /* load next 4 datas */ \ - " MRC p0,#0x1,r4,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r5,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r6,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r5,c1,c0,#6 \n" /* write biquad0*/ \ - " MRC p0,#0x1,r5,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r6,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r7,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0*/ \ - " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r7,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r8,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ - " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r8,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r9,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r8,c1,c0,#6 \n" /* write biquad0*/ \ - " STMIA r1!,{R4-R7} \n" /* store first and second two results */ \ - " LDRD r6,r7,[r0],#8 \n" /* load last 2 of the 8 */ \ - " MRC p0,#0x1,r8,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r9,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r6,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r9,c1,c0,#6 \n" /* write biquad0*/ \ - " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ - " IT NE \n" \ - " LDRDNE r4,r5,[r0],#8 \n" /* load first two of next 8 */ \ - " MRC p0,#0x1,r9,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r6,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r7,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0*/ \ - " STRD r8,r9,[r1],#8 \n" /* store third two results */ \ - " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r7,c3,c0,#0 \n" /* read biquad1*/ \ - " CMP r2, #0 \n" /* if (length == 0) */ \ - " BNE 1b \n" \ - " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ - " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ - " STRD r6,r7,[r1],#8 \n" /* store fourth two results */ \ - ) - -/*! - * @brief Fixed 16-bit data vector direct form II biquad cascade filter. - * - * The input and output data are fixed 16-bit data. The data flow is - * input -> biquad side 1 -> biquad side 0 -> output. - * - * @code - #define VECTOR_LEN 8 - int32_t input[VECTOR_LEN] = {1, 2, 3, 4, 5, 6, 7, 8}; - int32_t output[VECTOR_LEN]; - pq_biquad_state_t state0 = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - pq_biquad_state_t state1 = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state0); - PQ_BiquadRestoreInternalState(POWERQUAD, 1, &state1); - - PQ_StartVector(input, output, VECTOR_LEN); - PQ_Vector8BiqaudDf2CascadeFixed16(); - PQ_EndVector(); - @endcode - * - */ -#define PQ_Vector8BiqaudDf2CascadeFixed16() \ - __asm volatile( \ - "1: \n" \ - " MCR p0,#0x1,r4,c3,c0,#6 \n" /* write biquad1*/ \ - " CMP r3, #0 \n" \ - " ITTTE NE \n" \ - " MCRNE p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ - " MRCNE p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ - " MRCNE p0,#0x1,r4,c3,c0,#0 \n" /* read biquad1*/ \ - " MRCEQ p0,#0x1,r4,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r5,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r4,c1,c0,#6 \n" /* write biquad0*/ \ - " CMP r3, #0 \n" \ - " ITTE NE \n" \ - " STRHNE r6,[r1],#2 \n" /* store last two results*/ \ - " STRHNE r7,[r1],#2 \n" /* store last two results*/ \ - " MOVEQ r3, #1 \n" /* middle = 1 */ \ - " LDRSH r6,[r0],#2 \n" /* load next 2 of the 8*/ \ - " LDRSH r7,[r0],#2 \n" /* load next 2 of the 8*/ \ - " MRC p0,#0x1,r4,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r5,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r6,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r5,c1,c0,#6 \n" /* write biquad0*/ \ - " MRC p0,#0x1,r5,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r6,c3,c0,#0 \n" /* read biquad1*/ \ - " LDRSH r8,[r0],#2 \n" /* load next 2 of the 8*/ \ - " LDRSH r9,[r0],#2 \n" /* load next 2 of the 8*/ \ - " MCR p0,#0x1,r7,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0*/ \ - " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r7,c3,c0,#0 \n" /* read biquad1*/ \ - " STRH r4,[r1],#2 \n" /* store first 4 results */ \ - " STRH r5,[r1],#2 \n" /* store first 4 results */ \ - " MCR p0,#0x1,r8,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ - " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r8,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r9,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r8,c1,c0,#6 \n" /* write biquad0*/ \ - " STRH r6,[r1],#2 \n" /* store first 4 results */ \ - " STRH r7,[r1],#2 \n" /* store first 4 results */ \ - " LDRSH r6,[r0],#2 \n" /* load last 2 of the 8*/ \ - " LDRSH r7,[r0],#2 \n" /* load last 2 of the 8*/ \ - " MRC p0,#0x1,r8,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r9,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r6,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r9,c1,c0,#6 \n" /* write biquad0*/ \ - " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ - " ITT NE \n" \ - " LDRSHNE r4,[r0],#2 \n" /* load first two of next 8*/ \ - " LDRSHNE r5,[r0],#2 \n" /* load first two of next 8*/ \ - " MRC p0,#0x1,r9,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r6,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r7,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0*/ \ - " STRH r8,[r1],#2 \n" /* store third two results */ \ - " STRH r9,[r1],#2 \n" /* store third two results */ \ - " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r7,c3,c0,#0 \n" /* read biquad1*/ \ - " CMP r2, #0 \n" /* if (length == 0) */ \ - " BNE 1b \n" \ - " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ - " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ - " STRH r6,[r1],#2 \n" /* store fourth two results */ \ - " STRH r7,[r1],#2 \n" /* store fourth two results */ \ - ) - -/*! @brief Make the length used for matrix functions. */ -#define POWERQUAD_MAKE_MATRIX_LEN(mat1Row, mat1Col, mat2Col) \ - (((uint32_t)(mat1Row) << 0U) | ((uint32_t)(mat1Col) << 8U) | ((uint32_t)(mat2Col) << 16U)) - -/*! @brief Convert Q31 to float. */ -#define PQ_Q31_2_FLOAT(x) (((float)(x)) / 2147483648.0f) - -/*! @brief Convert Q15 to float. */ -#define PQ_Q15_2_FLOAT(x) (((float)(x)) / 32768.0f) - -/*! @brief powerquad computation engine */ -typedef enum -{ - kPQ_CP_PQ = 0, /*!< Math engine.*/ - kPQ_CP_MTX = 1, /*!< Matrix engine.*/ - kPQ_CP_FFT = 2, /*!< FFT engine.*/ - kPQ_CP_FIR = 3, /*!< FIR engine.*/ - kPQ_CP_CORDIC = 5 /*!< CORDIC engine.*/ -} pq_computationengine_t; - -/*! @brief powerquad data structure format type */ -typedef enum -{ - kPQ_16Bit = 0, /*!< Int16 Fixed point.*/ - kPQ_32Bit = 1, /*!< Int32 Fixed point.*/ - kPQ_Float = 2 /*!< Float point.*/ -} pq_format_t; - -/*! @brief Coprocessor prescale */ -typedef struct -{ - int8_t inputPrescale; /*!< Input prescale.*/ - int8_t outputPrescale; /*!< Output prescale.*/ - int8_t outputSaturate; /*!< Output saturate at n bits, for example 0x11 is 8 bit space, - the value will be truncated at +127 or -128.*/ -} pq_prescale_t; - -/*! @brief powerquad data structure format */ -typedef struct -{ - pq_format_t inputAFormat; /*!< Input A format.*/ - int8_t inputAPrescale; /*!< Input A prescale, for example 1.5 can be 1.5*2^n if you scale by 'shifting' - ('scaling' by a factor of n).*/ - pq_format_t inputBFormat; /*!< Input B format.*/ - int8_t inputBPrescale; /*!< Input B prescale.*/ - pq_format_t outputFormat; /*!< Out format.*/ - int8_t outputPrescale; /*!< Out prescale.*/ - pq_format_t tmpFormat; /*!< Temp format.*/ - int8_t tmpPrescale; /*!< Temp prescale.*/ - pq_format_t machineFormat; /*!< Machine format.*/ - uint32_t *tmpBase; /*!< Tmp base address.*/ -} pq_config_t; - -/*! @brief Struct to save biquad parameters. */ -typedef struct _pq_biquad_param -{ - float v_n_1; /*!< v[n-1], set to 0 when initialization. */ - float v_n; /*!< v[n], set to 0 when initialization. */ - float a_1; /*!< a[1] */ - float a_2; /*!< a[2] */ - float b_0; /*!< b[0] */ - float b_1; /*!< b[1] */ - float b_2; /*!< b[2] */ -} pq_biquad_param_t; - -/*! @brief Struct to save biquad state. */ -typedef struct _pq_biquad_state -{ - pq_biquad_param_t param; /*!< Filter parameter. */ - uint32_t compreg; /*!< Internal register, set to 0 when initialization. */ -} pq_biquad_state_t; - -/*! @brief Instance structure for the direct form II Biquad cascade filter */ -typedef struct -{ - uint8_t numStages; /**< Number of 2nd order stages in the filter.*/ - pq_biquad_state_t *pState; /**< Points to the array of state coefficients.*/ -} pq_biquad_cascade_df2_instance; - -/*! @brief CORDIC iteration */ -typedef enum -{ - kPQ_Iteration_8 = 0, /*!< Iterate 8 times.*/ - kPQ_Iteration_16, /*!< Iterate 16 times.*/ - kPQ_Iteration_24 /*!< Iterate 24 times.*/ -} pq_cordic_iter_t; - -/*! @brief Conversion between integer and float type */ -typedef union _pq_float -{ - float floatX; /*!< Float type.*/ - uint32_t integerX; /*!< Unsigned interger type.*/ -} pq_float_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name POWERQUAD functional Operation - * @{ - */ - -/*! - * @brief Get default configuration. - * - * This function initializes the POWERQUAD configuration structure to a default value. - * FORMAT register field definitions - * Bits[15:8] scaler (for scaled 'q31' formats) - * Bits[5:4] external format. 00b=q15, 01b=q31, 10b=float - * Bits[1:0] internal format. 00b=q15, 01b=q31, 10b=float - * POWERQUAD->INAFORMAT = (config->inputAPrescale << 8U) | (config->inputAFormat << 4U) | config->machineFormat - * - * For all Powerquad operations internal format must be float (with the only exception being - * the FFT related functions, ie FFT/IFFT/DCT/IDCT which must be set to q31). - * The default values are: - * config->inputAFormat = kPQ_Float; - * config->inputAPrescale = 0; - * config->inputBFormat = kPQ_Float; - * config->inputBPrescale = 0; - * config->outputFormat = kPQ_Float; - * config->outputPrescale = 0; - * config->tmpFormat = kPQ_Float; - * config->tmpPrescale = 0; - * config->machineFormat = kPQ_Float; - * config->tmpBase = 0xE0000000; - * - * @param config Pointer to "pq_config_t" structure. - */ -void PQ_GetDefaultConfig(pq_config_t *config); - -/*! - * @brief Set configuration with format/prescale. - * - * @param base POWERQUAD peripheral base address - * @param config Pointer to "pq_config_t" structure. - */ -void PQ_SetConfig(POWERQUAD_Type *base, const pq_config_t *config); - -/*! - * @brief set coprocessor scaler for coprocessor instructions, this function is used to - * set output saturation and scaleing for input/output. - * - * @param base POWERQUAD peripheral base address - * @param prescale Pointer to "pq_prescale_t" structure. - */ -static inline void PQ_SetCoprocessorScaler(POWERQUAD_Type *base, const pq_prescale_t *prescale) -{ - assert(NULL != prescale); - - base->CPPRE = POWERQUAD_CPPRE_CPPRE_IN(prescale->inputPrescale) | - POWERQUAD_CPPRE_CPPRE_OUT(prescale->outputPrescale) | - ((uint32_t)prescale->outputSaturate << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT); -} - -/*! - * @brief Initializes the POWERQUAD module. - * - * @param base POWERQUAD peripheral base address. - */ -void PQ_Init(POWERQUAD_Type *base); - -/*! - * @brief De-initializes the POWERQUAD module. - * - * @param base POWERQUAD peripheral base address. - */ -void PQ_Deinit(POWERQUAD_Type *base); - -/*! - * @brief Set format for non-coprecessor instructions. - * - * @param base POWERQUAD peripheral base address - * @param engine Computation engine - * @param format Data format - */ -void PQ_SetFormat(POWERQUAD_Type *base, pq_computationengine_t engine, pq_format_t format); - -/*! - * @brief Wait for the completion. - * - * @param base POWERQUAD peripheral base address - */ -static inline void PQ_WaitDone(POWERQUAD_Type *base) -{ - /* wait for the completion */ - while ((base->CONTROL & INST_BUSY) == INST_BUSY) - { - __WFE(); - } -} - -/*! - * @brief Processing function for the floating-point natural log. - * - * @param *pSrc points to the block of input data. The range of the input value is (0 +INFINITY). - * @param *pDst points to the block of output data - */ -static inline void PQ_LnF32(float *pSrc, float *pDst) -{ - pq_float_t val; - - val.floatX = *pSrc; - _pq_ln0(val.integerX); - val.integerX = _pq_readAdd0(); - *pDst = val.floatX; -} - -/*! - * @brief Processing function for the floating-point reciprocal. - * - * @param *pSrc points to the block of input data. The range of the input value is non-zero. - * @param *pDst points to the block of output data - */ -static inline void PQ_InvF32(float *pSrc, float *pDst) -{ - pq_float_t val; - - val.floatX = *pSrc; - _pq_inv0(val.integerX); - val.integerX = _pq_readMult0(); - *pDst = val.floatX; -} - -/*! - * @brief Processing function for the floating-point square-root. - * - * @param *pSrc points to the block of input data. The range of the input value is [0 +INFINITY). - * @param *pDst points to the block of output data - */ -static inline void PQ_SqrtF32(float *pSrc, float *pDst) -{ - pq_float_t val; - - val.floatX = *pSrc; - _pq_sqrt0(val.integerX); - val.integerX = _pq_readMult0(); - *pDst = val.floatX; -} - -/*! - * @brief Processing function for the floating-point inverse square-root. - * - * @param *pSrc points to the block of input data. The range of the input value is (0 +INFINITY). - * @param *pDst points to the block of output data - */ -static inline void PQ_InvSqrtF32(float *pSrc, float *pDst) -{ - pq_float_t val; - - val.floatX = *pSrc; - _pq_invsqrt0(val.integerX); - val.integerX = _pq_readMult0(); - *pDst = val.floatX; -} - -/*! - * @brief Processing function for the floating-point natural exponent. - * - * @param *pSrc points to the block of input data. The range of the input value is (-INFINITY +INFINITY). - * @param *pDst points to the block of output data - */ -static inline void PQ_EtoxF32(float *pSrc, float *pDst) -{ - pq_float_t val; - - val.floatX = *pSrc; - _pq_etox0(val.integerX); - val.integerX = _pq_readMult0(); - *pDst = val.floatX; -} - -/*! - * @brief Processing function for the floating-point natural exponent with negative parameter. - * - * @param *pSrc points to the block of input data. The range of the input value is (-INFINITY +INFINITY). - * @param *pDst points to the block of output data - */ -static inline void PQ_EtonxF32(float *pSrc, float *pDst) -{ - pq_float_t val; - - val.floatX = *pSrc; - _pq_etonx0(val.integerX); - val.integerX = _pq_readMult0(); - *pDst = val.floatX; -} - -/*! - * @brief Processing function for the floating-point sine. - * - * @param *pSrc points to the block of input data. The input value is in radians, the range is (-INFINITY - * +INFINITY). - * @param *pDst points to the block of output data - */ -static inline void PQ_SinF32(float *pSrc, float *pDst) -{ - pq_float_t val; - - val.floatX = *pSrc; - _pq_sin0(val.integerX); - val.integerX = _pq_readAdd0(); - *pDst = val.floatX; -} - -/*! - * @brief Processing function for the floating-point cosine. - * - * @param *pSrc points to the block of input data. The input value is in radians, the range is (-INFINITY - * +INFINITY). - * @param *pDst points to the block of output data - */ -static inline void PQ_CosF32(float *pSrc, float *pDst) -{ - pq_float_t val; - - val.floatX = *pSrc; - _pq_cos0(val.integerX); - val.integerX = _pq_readAdd0(); - *pDst = val.floatX; -} - -/*! - * @brief Processing function for the floating-point biquad. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - */ -static inline void PQ_BiquadF32(float *pSrc, float *pDst) -{ - pq_float_t val; - - val.floatX = *pSrc; - _pq_biquad0(val.integerX); - val.integerX = _pq_readAdd0(); - *pDst = val.floatX; -} - -/*! - * @brief Processing function for the floating-point division. - * - * Get x1 / x2. - * - * @param x1 x1 - * @param x2 x2 - * @param *pDst points to the block of output data - */ -static inline void PQ_DivF32(float *x1, float *x2, float *pDst) -{ - pq_float_t X1; - pq_float_t X2; - - X1.floatX = *x1; - X2.floatX = *x2; - uint64_t input = (uint64_t)(X2.integerX) | ((uint64_t)(X1.integerX) << 32U); - - _pq_div0(input); - X1.integerX = _pq_readMult0(); - *pDst = X1.floatX; -} - -/*! - * @brief Processing function for the floating-point biquad. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - */ -static inline void PQ_Biquad1F32(float *pSrc, float *pDst) -{ - pq_float_t val; - - val.floatX = *pSrc; - _pq_biquad1(val.integerX); - val.integerX = _pq_readAdd1(); - *pDst = val.floatX; -} - -/*! - * @brief Processing function for the fixed natural log. - * - * @param val value to be calculated. The range of the input value is (0 +INFINITY). - * @return returns ln(val). - */ -static inline int32_t PQ_LnFixed(int32_t val) -{ - _pq_ln_fx0(val); - return (int32_t)_pq_readAdd0_fx(); -} - -/*! - * @brief Processing function for the fixed reciprocal. - * - * @param val value to be calculated. The range of the input value is non-zero. - * @return returns inv(val). - */ -static inline int32_t PQ_InvFixed(int32_t val) -{ - _pq_inv_fx0(val); - return (int32_t)_pq_readMult0_fx(); -} - -/*! - * @brief Processing function for the fixed square-root. - * - * @param val value to be calculated. The range of the input value is [0 +INFINITY). - * @return returns sqrt(val). - */ -static inline uint32_t PQ_SqrtFixed(uint32_t val) -{ - _pq_sqrt_fx0(val); - return _pq_readMult0_fx(); -} - -/*! - * @brief Processing function for the fixed inverse square-root. - * - * @param val value to be calculated. The range of the input value is (0 +INFINITY). - * @return returns 1/sqrt(val). - */ -static inline int32_t PQ_InvSqrtFixed(int32_t val) -{ - _pq_invsqrt_fx0(val); - return (int32_t)_pq_readMult0_fx(); -} - -/*! - * @brief Processing function for the Fixed natural exponent. - * - * @param val value to be calculated. The range of the input value is (-INFINITY +INFINITY). - * @return returns etox^(val). - */ -static inline int32_t PQ_EtoxFixed(int32_t val) -{ - _pq_etox_fx0(val); - return (int32_t)_pq_readMult0_fx(); -} - -/*! - * @brief Processing function for the fixed natural exponent with negative parameter. - * - * @param val value to be calculated. The range of the input value is (-INFINITY +INFINITY). - * @return returns etonx^(val). - */ -static inline int32_t PQ_EtonxFixed(int32_t val) -{ - _pq_etonx_fx0(val); - return (int32_t)_pq_readMult0_fx(); -} - -/*! - * @brief Processing function for the fixed sine. - * - * @param val value to be calculated. The input value is [-1, 1] in Q31 format, which means [-pi, pi]. - * @return returns sin(val). - */ -static inline int32_t PQ_SinQ31(int32_t val) -{ - int32_t ret; - uint32_t cppre; -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - pq_float_t magic; - pq_float_t valFloat; - - magic.integerX = 0x30c90fdb; - valFloat.floatX = magic.floatX * (float)val; -#endif - - cppre = POWERQUAD->CPPRE; - POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); - -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - _pq_sin0(valFloat.integerX); - - (void)_pq_readAdd0(); - ret = (int32_t)_pq_readAdd0_fx(); -#else - _pq_sin_fx0(val); - ret = (int32_t)_pq_readAdd0_fx(); -#endif - - POWERQUAD->CPPRE = cppre; - - return ret; -} - -/*! - * @brief Processing function for the fixed sine. - * - * @param val value to be calculated. The input value is [-1, 1] in Q15 format, which means [-pi, pi]. - * @return returns sin(val). - */ -static inline int16_t PQ_SinQ15(int16_t val) -{ - uint32_t ret; - uint32_t cppre; -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - pq_float_t magic; - pq_float_t valFloat; - - magic.integerX = 0x30c90fdbU; - valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)val << 16U); -#endif - - cppre = POWERQUAD->CPPRE; - /* Don't use 15 here, it is wrong then val is 0x4000 */ - POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); - -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - _pq_sin0(valFloat.integerX); - - (void)_pq_readAdd0(); - ret = (_pq_readAdd0_fx() >> 16U); -#else - _pq_sin_fx0((uint32_t)val << 16U); - ret = (_pq_readAdd0_fx() >> 16U); -#endif - - POWERQUAD->CPPRE = cppre; - - return (int16_t)ret; -} - -/*! - * @brief Processing function for the fixed cosine. - * - * @param val value to be calculated. The input value is [-1, 1] in Q31 format, which means [-pi, pi]. - * @return returns cos(val). - */ -static inline int32_t PQ_CosQ31(int32_t val) -{ - int32_t ret; - uint32_t cppre; -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - pq_float_t magic; - pq_float_t valFloat; - - magic.integerX = 0x30c90fdb; - valFloat.floatX = magic.floatX * (float)val; -#endif - - cppre = POWERQUAD->CPPRE; - POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); - -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - _pq_cos0(valFloat.integerX); - - (void)_pq_readAdd0(); - ret = (int32_t)_pq_readAdd0_fx(); -#else - _pq_cos_fx0(val); - ret = (int32_t)_pq_readAdd0_fx(); -#endif - - POWERQUAD->CPPRE = cppre; - - return ret; -} - -/*! - * @brief Processing function for the fixed sine. - * - * @param val value to be calculated. The input value is [-1, 1] in Q15 format, which means [-pi, pi]. - * @return returns sin(val). - */ -static inline int16_t PQ_CosQ15(int16_t val) -{ - uint32_t ret; - uint32_t cppre; -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - pq_float_t magic; - pq_float_t valFloat; - - magic.integerX = 0x30c90fdbU; - valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)val << 16U); -#endif - - cppre = POWERQUAD->CPPRE; - POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); - -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - _pq_cos0(valFloat.integerX); - - (void)_pq_readAdd0(); - ret = _pq_readAdd0_fx() >> 16U; -#else - _pq_cos_fx0((uint32_t)val << 16U); - ret = _pq_readAdd0_fx() >> 16U; -#endif - - POWERQUAD->CPPRE = cppre; - - return (int16_t)ret; -} - -/*! - * @brief Processing function for the fixed biquad. - * - * @param val value to be calculated - * @return returns biquad(val). - */ -static inline int32_t PQ_BiquadFixed(int32_t val) -{ - _pq_biquad0_fx(val); - return (int32_t)_pq_readAdd0_fx(); -} - -/*! - * @brief Processing function for the floating-point vectorised natural log. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorLnF32(float *pSrc, float *pDst, int32_t length); - -/*! - * @brief Processing function for the floating-point vectorised reciprocal. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorInvF32(float *pSrc, float *pDst, int32_t length); - -/*! - * @brief Processing function for the floating-point vectorised square-root. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorSqrtF32(float *pSrc, float *pDst, int32_t length); - -/*! - * @brief Processing function for the floating-point vectorised inverse square-root. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorInvSqrtF32(float *pSrc, float *pDst, int32_t length); - -/*! - * @brief Processing function for the floating-point vectorised natural exponent. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorEtoxF32(float *pSrc, float *pDst, int32_t length); - -/*! - * @brief Processing function for the floating-point vectorised natural exponent with negative parameter. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorEtonxF32(float *pSrc, float *pDst, int32_t length); - -/*! - * @brief Processing function for the floating-point vectorised sine - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorSinF32(float *pSrc, float *pDst, int32_t length); - -/*! - * @brief Processing function for the floating-point vectorised cosine. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorCosF32(float *pSrc, float *pDst, int32_t length); - -/*! - * @brief Processing function for the Q31 vectorised natural log. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorLnFixed32(int32_t *pSrc, int32_t *pDst, int32_t length); - -/*! - * @brief Processing function for the Q31 vectorised reciprocal. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorInvFixed32(int32_t *pSrc, int32_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 32-bit integer vectorised square-root. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorSqrtFixed32(int32_t *pSrc, int32_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 32-bit integer vectorised inverse square-root. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorInvSqrtFixed32(int32_t *pSrc, int32_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 32-bit integer vectorised natural exponent. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorEtoxFixed32(int32_t *pSrc, int32_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 32-bit integer vectorised natural exponent with negative parameter. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorEtonxFixed32(int32_t *pSrc, int32_t *pDst, int32_t length); - -/*! - * @brief Processing function for the Q15 vectorised sine - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorSinQ15(int16_t *pSrc, int16_t *pDst, int32_t length); - -/*! - * @brief Processing function for the Q15 vectorised cosine. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorCosQ15(int16_t *pSrc, int16_t *pDst, int32_t length); - -/*! - * @brief Processing function for the Q31 vectorised sine - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorSinQ31(int32_t *pSrc, int32_t *pDst, int32_t length); - -/*! - * @brief Processing function for the Q31 vectorised cosine. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorCosQ31(int32_t *pSrc, int32_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 16-bit integer vectorised natural log. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorLnFixed16(int16_t *pSrc, int16_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 16-bit integer vectorised reciprocal. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorInvFixed16(int16_t *pSrc, int16_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 16-bit integer vectorised square-root. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorSqrtFixed16(int16_t *pSrc, int16_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 16-bit integer vectorised inverse square-root. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorInvSqrtFixed16(int16_t *pSrc, int16_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 16-bit integer vectorised natural exponent. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorEtoxFixed16(int16_t *pSrc, int16_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 16-bit integer vectorised natural exponent with negative parameter. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorEtonxFixed16(int16_t *pSrc, int16_t *pDst, int32_t length); - -/*! - * @brief Processing function for the floating-point vectorised biquad direct form II. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block size of input data. - */ -void PQ_VectorBiqaudDf2F32(float *pSrc, float *pDst, int32_t length); - -/*! - * @brief Processing function for the 32-bit integer vectorised biquad direct form II. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block size of input data - */ -void PQ_VectorBiqaudDf2Fixed32(int32_t *pSrc, int32_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 16-bit integer vectorised biquad direct form II. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block size of input data - */ -void PQ_VectorBiqaudDf2Fixed16(int16_t *pSrc, int16_t *pDst, int32_t length); - -/*! - * @brief Processing function for the floating-point vectorised biquad direct form II. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block size of input data - */ -void PQ_VectorBiqaudCascadeDf2F32(float *pSrc, float *pDst, int32_t length); - -/*! - * @brief Processing function for the 32-bit integer vectorised biquad direct form II. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block size of input data - */ -void PQ_VectorBiqaudCascadeDf2Fixed32(int32_t *pSrc, int32_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 16-bit integer vectorised biquad direct form II. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block size of input data - */ -void PQ_VectorBiqaudCascadeDf2Fixed16(int16_t *pSrc, int16_t *pDst, int32_t length); - -/*! - * @brief Processing function for the fixed inverse trigonometric. - * - * @param base POWERQUAD peripheral base address - * @param x value of opposite - * @param y value of adjacent - * @param iteration iteration times - * @return The return value is in the range of -2^27 to 2^27, which means -pi to pi. - * @note The sum of x and y should not exceed the range of int32_t. - * @note Larger input number gets higher output accuracy, for example the arctan(0.5), - * the result of PQ_ArctanFixed(POWERQUAD, 100000, 200000, kPQ_Iteration_24) is more - * accurate than PQ_ArctanFixed(POWERQUAD, 1, 2, kPQ_Iteration_24). - */ -int32_t PQ_ArctanFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_iter_t iteration); - -/*! - * @brief Processing function for the fixed inverse trigonometric. - * - * @param base POWERQUAD peripheral base address - * @param x value of opposite - * @param y value of adjacent - * @param iteration iteration times - * @return The return value is in the range of -2^27 to 2^27, which means -1 to 1. - * @note The sum of x and y should not exceed the range of int32_t. - * @note Larger input number gets higher output accuracy, for example the arctanh(0.5), - * the result of PQ_ArctanhFixed(POWERQUAD, 100000, 200000, kPQ_Iteration_24) is more - * accurate than PQ_ArctanhFixed(POWERQUAD, 1, 2, kPQ_Iteration_24). - */ -int32_t PQ_ArctanhFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_iter_t iteration); - -/*! - * @brief Processing function for the fixed biquad. - * - * @param val value to be calculated - * @return returns biquad(val). - */ -static inline int32_t PQ_Biquad1Fixed(int32_t val) -{ - _pq_biquad1_fx(val); - return (int32_t)_pq_readAdd1_fx(); -} - -/*! - * @brief Processing function for the complex FFT. - * - * @param base POWERQUAD peripheral base address - * @param length number of input samples - * @param pData input data - * @param pResult output data. - */ -void PQ_TransformCFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult); - -/*! - * @brief Processing function for the real FFT. - * - * @param base POWERQUAD peripheral base address - * @param length number of input samples - * @param pData input data - * @param pResult output data. - */ -void PQ_TransformRFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult); - -/*! - * @brief Processing function for the inverse complex FFT. - * - * @param base POWERQUAD peripheral base address - * @param length number of input samples - * @param pData input data - * @param pResult output data. - */ -void PQ_TransformIFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult); - -/*! - * @brief Processing function for the complex DCT. - * - * @param base POWERQUAD peripheral base address - * @param length number of input samples - * @param pData input data - * @param pResult output data. - */ -void PQ_TransformCDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult); - -/*! - * @brief Processing function for the real DCT. - * - * @param base POWERQUAD peripheral base address - * @param length number of input samples - * @param pData input data - * @param pResult output data. - */ -void PQ_TransformRDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult); - -/*! - * @brief Processing function for the inverse complex DCT. - * - * @param base POWERQUAD peripheral base address - * @param length number of input samples - * @param pData input data - * @param pResult output data. - */ -void PQ_TransformIDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult); - -/*! - * @brief Processing function for backup biquad context. - * - * @param base POWERQUAD peripheral base address - * @param biquad_num biquad side - * @param state point to states. - */ -void PQ_BiquadBackUpInternalState(POWERQUAD_Type *base, int32_t biquad_num, pq_biquad_state_t *state); - -/*! - * @brief Processing function for restore biquad context. - * - * @param base POWERQUAD peripheral base address - * @param biquad_num biquad side - * @param state point to states. - */ -void PQ_BiquadRestoreInternalState(POWERQUAD_Type *base, int32_t biquad_num, pq_biquad_state_t *state); - -/*! - * @brief Initialization function for the direct form II Biquad cascade filter. - * - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pState points to the state buffer. - */ -void PQ_BiquadCascadeDf2Init(pq_biquad_cascade_df2_instance *S, uint8_t numStages, pq_biquad_state_t *pState); - -/*! - * @brief Processing function for the floating-point direct form II Biquad cascade filter. - * - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void PQ_BiquadCascadeDf2F32(const pq_biquad_cascade_df2_instance *S, float *pSrc, float *pDst, uint32_t blockSize); - -/*! - * @brief Processing function for the Q31 direct form II Biquad cascade filter. - * - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void PQ_BiquadCascadeDf2Fixed32(const pq_biquad_cascade_df2_instance *S, - int32_t *pSrc, - int32_t *pDst, - uint32_t blockSize); - -/*! - * @brief Processing function for the Q15 direct form II Biquad cascade filter. - * - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void PQ_BiquadCascadeDf2Fixed16(const pq_biquad_cascade_df2_instance *S, - int16_t *pSrc, - int16_t *pDst, - uint32_t blockSize); - -/*! - * @brief Processing function for the FIR. - * - * @param base POWERQUAD peripheral base address - * @param pAData the first input sequence - * @param ALength number of the first input sequence - * @param pBData the second input sequence - * @param BLength number of the second input sequence - * @param pResult array for the output data - * @param opType operation type, could be PQ_FIR_FIR, PQ_FIR_CONVOLUTION, PQ_FIR_CORRELATION. - */ -void PQ_FIR(POWERQUAD_Type *base, - const void *pAData, - int32_t ALength, - const void *pBData, - int32_t BLength, - void *pResult, - uint32_t opType); - -/*! - * @brief Processing function for the incremental FIR. - * This function can be used after pq_fir() for incremental FIR - * operation when new x data are available - * - * @param base POWERQUAD peripheral base address - * @param ALength number of input samples - * @param BLength number of taps - * @param xOffset offset for number of input samples - */ -void PQ_FIRIncrement(POWERQUAD_Type *base, int32_t ALength, int32_t BLength, int32_t xOffset); - -/*! - * @brief Processing function for the matrix addition. - * - * @param base POWERQUAD peripheral base address - * @param length rows and cols for matrix. LENGTH register configuration: - * LENGTH[23:16] = M2 cols - * LENGTH[15:8] = M1 cols - * LENGTH[7:0] = M1 rows - * This could be constructed using macro @ref POWERQUAD_MAKE_MATRIX_LEN. - * @param pAData input matrix A - * @param pBData input matrix B - * @param pResult array for the output data. - */ -void PQ_MatrixAddition(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult); - -/*! - * @brief Processing function for the matrix subtraction. - * - * @param base POWERQUAD peripheral base address - * @param length rows and cols for matrix. LENGTH register configuration: - * LENGTH[23:16] = M2 cols - * LENGTH[15:8] = M1 cols - * LENGTH[7:0] = M1 rows - * This could be constructed using macro @ref POWERQUAD_MAKE_MATRIX_LEN. - * @param pAData input matrix A - * @param pBData input matrix B - * @param pResult array for the output data. - */ -void PQ_MatrixSubtraction(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult); - -/*! - * @brief Processing function for the matrix multiplication. - * - * @param base POWERQUAD peripheral base address - * @param length rows and cols for matrix. LENGTH register configuration: - * LENGTH[23:16] = M2 cols - * LENGTH[15:8] = M1 cols - * LENGTH[7:0] = M1 rows - * This could be constructed using macro @ref POWERQUAD_MAKE_MATRIX_LEN. - * @param pAData input matrix A - * @param pBData input matrix B - * @param pResult array for the output data. - */ -void PQ_MatrixMultiplication(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult); - -/*! - * @brief Processing function for the matrix product. - * - * @param base POWERQUAD peripheral base address - * @param length rows and cols for matrix. LENGTH register configuration: - * LENGTH[23:16] = M2 cols - * LENGTH[15:8] = M1 cols - * LENGTH[7:0] = M1 rows - * This could be constructed using macro @ref POWERQUAD_MAKE_MATRIX_LEN. - * @param pAData input matrix A - * @param pBData input matrix B - * @param pResult array for the output data. - */ -void PQ_MatrixProduct(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult); - -/*! - * @brief Processing function for the vector dot product. - * - * @param base POWERQUAD peripheral base address - * @param length length of vector - * @param pAData input vector A - * @param pBData input vector B - * @param pResult array for the output data. - */ -void PQ_VectorDotProduct(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult); - -/*! - * @brief Processing function for the matrix inverse. - * - * @param base POWERQUAD peripheral base address - * @param length rows and cols for matrix. LENGTH register configuration: - * LENGTH[23:16] = M2 cols - * LENGTH[15:8] = M1 cols - * LENGTH[7:0] = M1 rows - * This could be constructed using macro @ref POWERQUAD_MAKE_MATRIX_LEN. - * @param pData input matrix - * @param pTmpData input temporary matrix, pTmpData length not less than pData lenght and 1024 words is sufficient for - * the largest supported matrix. - * @param pResult array for the output data, round down for fixed point. - */ -void PQ_MatrixInversion(POWERQUAD_Type *base, uint32_t length, void *pData, void *pTmpData, void *pResult); - -/*! - * @brief Processing function for the matrix transpose. - * - * @param base POWERQUAD peripheral base address - * @param length rows and cols for matrix. LENGTH register configuration: - * LENGTH[23:16] = M2 cols - * LENGTH[15:8] = M1 cols - * LENGTH[7:0] = M1 rows - * This could be constructed using macro @ref POWERQUAD_MAKE_MATRIX_LEN. - * @param pData input matrix - * @param pResult array for the output data. - */ -void PQ_MatrixTranspose(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult); - -/*! - * @brief Processing function for the matrix scale. - * - * @param base POWERQUAD peripheral base address - * @param length rows and cols for matrix. LENGTH register configuration: - * LENGTH[23:16] = M2 cols - * LENGTH[15:8] = M1 cols - * LENGTH[7:0] = M1 rows - * This could be constructed using macro @ref POWERQUAD_MAKE_MATRIX_LEN. - * @param misc scaling parameters - * @param pData input matrix - * @param pResult array for the output data. - */ -void PQ_MatrixScale(POWERQUAD_Type *base, uint32_t length, float misc, const void *pData, void *pResult); - -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_POWERQUAD_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_basic.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_basic.c deleted file mode 100644 index 3a1de44b629..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_basic.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright 2018-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_powerquad.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.powerquad_basic" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -void PQ_GetDefaultConfig(pq_config_t *config) -{ - config->inputAFormat = kPQ_Float; - config->inputAPrescale = 0; - config->inputBFormat = kPQ_Float; - config->inputBPrescale = 0; - config->outputFormat = kPQ_Float; - config->outputPrescale = 0; - config->tmpFormat = kPQ_Float; - config->tmpPrescale = 0; - config->machineFormat = kPQ_Float; - config->tmpBase = (uint32_t *)0xE0000000U; -} - -void PQ_SetConfig(POWERQUAD_Type *base, const pq_config_t *config) -{ - assert(NULL != config); - - base->TMPBASE = (uint32_t)config->tmpBase; - base->INAFORMAT = ((uint32_t)config->inputAPrescale << 8U) | ((uint32_t)config->inputAFormat << 4U) | - (uint32_t)config->machineFormat; - base->INBFORMAT = ((uint32_t)config->inputBPrescale << 8U) | ((uint32_t)config->inputBFormat << 4U) | - (uint32_t)config->machineFormat; - base->TMPFORMAT = - ((uint32_t)config->tmpPrescale << 8U) | ((uint32_t)config->tmpFormat << 4U) | (uint32_t)config->machineFormat; - base->OUTFORMAT = ((uint32_t)config->outputPrescale << 8U) | ((uint32_t)config->outputFormat << 4U) | - (uint32_t)config->machineFormat; -} - -void PQ_Init(POWERQUAD_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(POWERQUAD_CLOCKS) - CLOCK_EnableClock(kCLOCK_PowerQuad); -#endif -#endif -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(POWERQUAD_RSTS) - RESET_PeripheralReset(kPOWERQUAD_RST_SHIFT_RSTn); -#endif -#endif - - /* Enable event used for WFE. */ - base->EVENTEN = POWERQUAD_EVENTEN_EVENT_OFLOW_MASK | POWERQUAD_EVENTEN_EVENT_NAN_MASK | - POWERQUAD_EVENTEN_EVENT_FIXED_MASK | POWERQUAD_EVENTEN_EVENT_UFLOW_MASK | - POWERQUAD_EVENTEN_EVENT_BERR_MASK | POWERQUAD_EVENTEN_EVENT_COMP_MASK; -} - -void PQ_Deinit(POWERQUAD_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(POWERQUAD_CLOCKS) - CLOCK_DisableClock(kCLOCK_PowerQuad); -#endif -#endif -} - -void PQ_SetFormat(POWERQUAD_Type *base, pq_computationengine_t engine, pq_format_t format) -{ - pq_config_t config; - - PQ_GetDefaultConfig(&config); - - /* 32-bit Float point */ - if (kPQ_Float == format) - { - config.inputAFormat = kPQ_Float; - config.inputAPrescale = 0; - config.inputBFormat = kPQ_Float; - config.inputBPrescale = 0; - config.outputFormat = kPQ_Float; - config.outputPrescale = 0; - config.tmpFormat = kPQ_Float; - config.tmpPrescale = 0; - } - /* 32-bit Fixed point */ - if (kPQ_32Bit == format) - { - config.inputAFormat = kPQ_32Bit; - config.inputAPrescale = 0; - config.inputBFormat = kPQ_32Bit; - config.inputBPrescale = 0; - config.outputFormat = kPQ_32Bit; - config.outputPrescale = 0; - config.tmpFormat = kPQ_Float; - config.tmpPrescale = 0; - } - /* 16-bit Fixed point */ - if (kPQ_16Bit == format) - { - config.inputAFormat = kPQ_16Bit; - config.inputAPrescale = 0; - config.inputBFormat = kPQ_16Bit; - config.inputBPrescale = 0; - config.outputFormat = kPQ_16Bit; - config.outputPrescale = 0; - config.tmpFormat = kPQ_Float; - config.tmpPrescale = 0; - } - - if (CP_FFT == (uint8_t)engine) - { - config.machineFormat = kPQ_32Bit; - } - else - { - config.machineFormat = kPQ_Float; - } - - PQ_SetConfig(base, &config); -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_cmsis.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_cmsis.c deleted file mode 100644 index fd34d1ade6a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_cmsis.c +++ /dev/null @@ -1,1693 +0,0 @@ -/* - * Copyright 2018-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_powerquad.h" -#include "fsl_powerquad_data.h" -#include "arm_math.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.powerquad_cmsis" -#endif - -#define PQ_SET_FIX32_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->TMPBASE = 0xE0000000U - -#define PQ_SET_FIX16_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->TMPBASE = 0xE0000000U - -#define PQ_SET_Q31_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(-31) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->TMPBASE = 0xE0000000U - -#define PQ_SET_Q15_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(-15) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->TMPBASE = 0xE0000000U - -#define PQ_SET_F32_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->TMPBASE = 0xE0000000U - -#define PQ_SET_FFT_Q31_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_32Bit; \ - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_32Bit; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_32Bit; \ - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_32Bit; \ - POWERQUAD->TMPBASE = 0xE0000000U - -#define PQ_SET_FFT_Q15_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_32Bit; \ - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_32Bit; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_32Bit; \ - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_32Bit; \ - POWERQUAD->TMPBASE = 0xE0000000U - -#define PQ_SET_MAT_FIX32_WORKAROUND_SCALE_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->TMPBASE = 0xE0000000U - -#define PQ_SET_MAT_FIX32_WORKAROUND_MULT_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->TMPBASE = 0xE0000000U - -#define PQ_SET_MAT_FIX16_WORKAROUND_SCALE_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->TMPBASE = 0xE0000000U - -#define PQ_SET_MAT_FIX16_WORKAROUND_MULT_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ - POWERQUAD->TMPBASE = 0xE0000000U - -/******************************************************************************* - * Code - ******************************************************************************/ -static void _arm_fir_increment(const void *pSrc, - uint32_t srcLen, - const void *pTap, - uint16_t tapLen, - void *pDst, - uint32_t offset, - uint32_t elemSize) -{ - POWERQUAD->INABASE = ((uint32_t)(const uint32_t *)pSrc) - (offset * elemSize); - POWERQUAD->INBBASE = (uint32_t)(const uint32_t *)pTap; - POWERQUAD->LENGTH = (((uint32_t)tapLen & 0xFFFFUL) << 16U) + (srcLen & 0xFFFFUL); - POWERQUAD->OUTBASE = ((uint32_t)(uint32_t *)pDst) - (offset * elemSize); - POWERQUAD->MISC = offset; - POWERQUAD->CONTROL = (CP_FIR << 4U) | PQ_FIR_INCREMENTAL; -} - -float32_t arm_cos_f32(float32_t x) -{ - float tmp; - - PQ_CosF32(&x, &tmp); - return tmp; -} - -q31_t arm_cos_q31(q31_t x) -{ - /* For PQ: input -1 to 1 means -pi to pi - * For CMSIS DSP: input 0 to 1 means pi to 2*pi */ - x *= 2; - return PQ_CosQ31(x); -} - -q15_t arm_cos_q15(q15_t x) -{ - /* For PQ: input -1 to 1 means -pi to pi - * For CMSIS DSP: input 0 to 1 means pi to 2*pi */ - x *= 2; - return PQ_CosQ15(x); -} - -float32_t arm_sin_f32(float32_t x) -{ - float tmp; - - PQ_SinF32(&x, &tmp); - return tmp; -} - -q31_t arm_sin_q31(q31_t x) -{ - /* For PQ: input -1 to 1 means -pi to pi - * For CMSIS DSP: input 0 to 1 means pi to 2*pi */ - x *= 2; - return PQ_SinQ31(x); -} - -q15_t arm_sin_q15(q15_t x) -{ - /* For PQ: input -1 to 1 means -pi to pi - * For CMSIS DSP: input 0 to 1 means pi to 2*pi */ - x *= 2; - return PQ_SinQ15(x); -} - -arm_status arm_sqrt_q31(q31_t in, q31_t *pOut) -{ - uint32_t cppre; - arm_status status; - - /* If the input is a positive number then compute the signBits. */ - if (in > 0) - { - cppre = POWERQUAD->CPPRE; - POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_IN(-31) | POWERQUAD_CPPRE_CPPRE_OUT(31); - *pOut = (q31_t)PQ_SqrtFixed((uint32_t)in); - POWERQUAD->CPPRE = cppre; - - status = (ARM_MATH_SUCCESS); - } - /* If the number is a negative number then store zero as its square root value */ - else - { - *pOut = 0; - - status = (ARM_MATH_ARGUMENT_ERROR); - } - - return status; -} - -arm_status arm_sqrt_q15(q15_t in, q15_t *pOut) -{ - uint32_t cppre; - arm_status status; - - /* If the input is a positive number then compute the signBits. */ - if (in > 0) - { - cppre = POWERQUAD->CPPRE; - POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_IN(-15) | POWERQUAD_CPPRE_CPPRE_OUT(15); - *pOut = (q15_t)PQ_SqrtFixed((uint32_t)in); - POWERQUAD->CPPRE = cppre; - - status = (ARM_MATH_SUCCESS); - } - /* If the number is a negative number then store zero as its square root value */ - else - { - *pOut = 0; - - status = (ARM_MATH_ARGUMENT_ERROR); - } - - return status; -} - -void arm_cfft_q31(const arm_cfft_instance_q31 *S, q31_t *p1, uint8_t ifftFlag, uint8_t bitReverseFlag) -{ - assert(bitReverseFlag == 1U); - - q31_t *pIn = p1; - q31_t *pOut = p1; - uint32_t length = S->fftLen; - - PQ_SET_FFT_Q31_CONFIG; - - if (ifftFlag == 1U) - { - PQ_TransformIFFT(POWERQUAD, length, pIn, pOut); - } - else - { - PQ_TransformCFFT(POWERQUAD, length, pIn, pOut); - } - - PQ_WaitDone(POWERQUAD); -} - -void arm_cfft_q15(const arm_cfft_instance_q15 *S, q15_t *p1, uint8_t ifftFlag, uint8_t bitReverseFlag) -{ - assert(bitReverseFlag == 1U); - - q15_t *pIn = p1; - q15_t *pOut = p1; - uint32_t length = S->fftLen; - - PQ_SET_FFT_Q15_CONFIG; - - if (ifftFlag == 1U) - { - PQ_TransformIFFT(POWERQUAD, length, pIn, pOut); - } - else - { - PQ_TransformCFFT(POWERQUAD, length, pIn, pOut); - } - - PQ_WaitDone(POWERQUAD); -} - -arm_status arm_rfft_init_q31(arm_rfft_instance_q31 *S, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag) -{ - /* Only supprt such mode. */ - assert(ifftFlagR == 0U); - assert(bitReverseFlag == 1U); - - /* Initialise the default arm status */ - arm_status status = ARM_MATH_SUCCESS; - - /* Initialize the Real FFT length */ - S->fftLenReal = (uint16_t)fftLenReal; - - /* Initialize the Flag for selection of RFFT or RIFFT */ - S->ifftFlagR = (uint8_t)ifftFlagR; - - /* Initialize the Flag for calculation Bit reversal or not */ - S->bitReverseFlagR = (uint8_t)bitReverseFlag; - - /* return the status of RFFT Init function */ - return (status); -} - -void arm_rfft_q31(const arm_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst) -{ - uint32_t length = S->fftLenReal; - PQ_SET_FFT_Q31_CONFIG; - - /* Calculation of RFFT of input */ - PQ_TransformRFFT(POWERQUAD, length, pSrc, pDst); - - PQ_WaitDone(POWERQUAD); -} - -arm_status arm_rfft_init_q15(arm_rfft_instance_q15 *S, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag) -{ - /* Only supprt such mode. */ - assert(ifftFlagR == 0U); - assert(bitReverseFlag == 1U); - - /* Initialise the default arm status */ - arm_status status = ARM_MATH_SUCCESS; - - /* Initialize the Real FFT length */ - S->fftLenReal = (uint16_t)fftLenReal; - - /* Initialize the Flag for selection of RFFT or RIFFT */ - S->ifftFlagR = (uint8_t)ifftFlagR; - - /* Initialize the Flag for calculation Bit reversal or not */ - S->bitReverseFlagR = (uint8_t)bitReverseFlag; - - /* return the status of RFFT Init function */ - return (status); -} - -void arm_rfft_q15(const arm_rfft_instance_q15 *S, q15_t *pSrc, q15_t *pDst) -{ - uint32_t length = S->fftLenReal; - PQ_SET_FFT_Q15_CONFIG; - - /* Calculation of RFFT of input */ - PQ_TransformRFFT(POWERQUAD, length, pSrc, pDst); - - PQ_WaitDone(POWERQUAD); -} - -arm_status arm_dct4_init_q31(arm_dct4_instance_q31 *S, - arm_rfft_instance_q31 *S_RFFT, - arm_cfft_radix4_instance_q31 *S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize) -{ - arm_status status = ARM_MATH_SUCCESS; - - /* Initialize the DCT4 length */ - S->N = N; - - /* Initialize Real FFT Instance */ - S->pRfft = S_RFFT; - - switch (N) - { - /* Initialize the table modifier values */ - case 512U: - S->pTwiddle = dct512_twiddle; - S->pCosFactor = dct512_cosFactor; - break; - - case 256U: - S->pTwiddle = dct256_twiddle; - S->pCosFactor = dct256_cosFactor; - break; - - case 128U: - S->pTwiddle = dct128_twiddle; - S->pCosFactor = dct128_cosFactor; - break; - - case 64U: - S->pTwiddle = dct64_twiddle; - S->pCosFactor = dct64_cosFactor; - break; - - case 32U: - S->pTwiddle = dct32_twiddle; - S->pCosFactor = dct32_cosFactor; - break; - - case 16U: - S->pTwiddle = dct16_twiddle; - S->pCosFactor = dct16_cosFactor; - break; - - default: - status = ARM_MATH_ARGUMENT_ERROR; - break; - } - - if (ARM_MATH_SUCCESS == status) - { - /* Initialize the RFFT/RIFFT Function */ - status = arm_rfft_init_q31(S->pRfft, S->N, 0, 1); - } - - return status; -} - -void arm_dct4_q31(const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineBuffer) -{ - /* Calculate DCT-II for N-point input */ - uint16_t i; /* Loop counter */ - const q31_t *weights; /* Pointer to the Weights table */ - q31_t *pOut; /* Temporary pointers for output buffer */ - q31_t *pS1, *pbuff; /* Temporary pointers for input buffer and pState buffer */ - q31_t in; /* Temporary variable */ - const q31_t *cosFact; - uint32_t length; - uint8_t matRow; - uint8_t matCol; - uint8_t matLoop; - uint16_t lenPerMatLoop; - - /* - * Pre-processing involves multiplying input with cos factor, - * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*N)) - * where, - * r(n) -- output of preprocessing - * u(n) -- input to preprocessing(actual Source buffer) - */ - - /* - * Use matrix production function for preprocessing. Matrix production - * supports 16x16 at the most, so the matrix row is set to 16. - */ - matRow = 16U; - lenPerMatLoop = S->N >= 256U ? 256U : S->N; - matCol = (uint8_t)(lenPerMatLoop / 16U); - matLoop = (uint8_t)(((S->N - 1U) >> 8U) + 1U); - cosFact = S->pCosFactor; - pbuff = pInlineBuffer; - - length = POWERQUAD_MAKE_MATRIX_LEN(matRow, matCol, matCol); - - while ((matLoop--) != 0U) - { - PQ_SET_MAT_FIX32_WORKAROUND_SCALE_CONFIG; - - /* cos factor is Q31, convert to float */ - PQ_MatrixScale(POWERQUAD, length, 2.0f / 2147483648.0f, cosFact, (void *)(uint32_t *)0xE0000000U); - cosFact = &cosFact[lenPerMatLoop]; - - PQ_WaitDone(POWERQUAD); - - /* Product. */ - PQ_SET_MAT_FIX32_WORKAROUND_MULT_CONFIG; - - PQ_MatrixProduct(POWERQUAD, length, pbuff, (void *)(uint32_t *)0xE0000000U, pbuff); - - pbuff = &pbuff[lenPerMatLoop]; - - PQ_WaitDone(POWERQUAD); - } - - PQ_SET_FFT_Q31_CONFIG; - - PQ_TransformRDCT(POWERQUAD, S->N, pInlineBuffer, pState); - - /* ARM calculation while PQ is running. */ - /* - * Use matrix production function for twiddle multiplication. - * Matrix production supports 16x16 at the most. The total elements are 2*N; - */ - lenPerMatLoop = S->N >= 128U ? 128U : S->N; - matCol = (uint8_t)(lenPerMatLoop / 8U); - matLoop = (uint8_t)(((S->N - 1U) >> 7U) + 1U); - weights = S->pTwiddle; - pOut = pState; - - length = POWERQUAD_MAKE_MATRIX_LEN(matRow, matCol, matCol); - - PQ_WaitDone(POWERQUAD); - - while ((matLoop--) != 0U) - { - PQ_SET_MAT_FIX32_WORKAROUND_SCALE_CONFIG; - - /* Downscale by 1024 * 1024 * 16, because the twiddle are multiplied by 1024 * 1024 * 16. */ - PQ_MatrixScale(POWERQUAD, length, 1.0f / 16777216.0f, weights, (void *)(uint32_t *)0xE0000000U); - weights = &weights[lenPerMatLoop * 2U]; - - PQ_WaitDone(POWERQUAD); - - /* Product. */ - PQ_SET_MAT_FIX32_WORKAROUND_MULT_CONFIG; - - PQ_MatrixProduct(POWERQUAD, length, pOut, (void *)(uint32_t *)0xE0000000U, pOut); - - PQ_WaitDone(POWERQUAD); - - for (i = 0; i < lenPerMatLoop / 4U; i++) - { - pOut[0] -= pOut[1]; - pOut = &pOut[2]; - pOut[0] -= pOut[1]; - pOut = &pOut[2]; - pOut[0] -= pOut[1]; - pOut = &pOut[2]; - pOut[0] -= pOut[1]; - pOut = &pOut[2]; - } - } - - /* ----------- Post-processing ---------- */ - /* DCT-IV can be obtained from DCT-II by the equation, - * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) - * Hence, Y4(0) = Y2(0)/2 */ - /* Getting only real part from the output and Converting to DCT-IV */ - - /* pbuff initialized to input buffer. */ - pbuff = pInlineBuffer; - - /* pS1 initialized to pState */ - pS1 = pState; - - /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2. Considering the DCT II normalize, here divided by sqrt(2).*/ - in = (q31_t)(float)((float)*pS1 / 1.41421356237f); - *pbuff++ = in; - pS1 = &pS1[2]; - - in = *pS1 - in; - *pbuff++ = in; - pS1 = &pS1[2]; - - in = *pS1 - in; - *pbuff++ = in; - pS1 = &pS1[2]; - - in = *pS1 - in; - *pbuff++ = in; - pS1 = &pS1[2]; - - i = S->N / 4U - 1U; - - while (i > 0U) - { - in = *pS1 - in; - *pbuff++ = in; - pS1 = &pS1[2]; - - in = *pS1 - in; - *pbuff++ = in; - pS1 = &pS1[2]; - - in = *pS1 - in; - *pbuff++ = in; - pS1 = &pS1[2]; - - in = *pS1 - in; - *pbuff++ = in; - pS1 = &pS1[2]; - - i--; - } -} - -arm_status arm_dct4_init_q15(arm_dct4_instance_q15 *S, - arm_rfft_instance_q15 *S_RFFT, - arm_cfft_radix4_instance_q15 *S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize) -{ - arm_status status = ARM_MATH_SUCCESS; - - /* Initialize the DCT4 length */ - S->N = N; - - /* Initialize Real FFT Instance */ - S->pRfft = S_RFFT; - - switch (N) - { - /* Initialize the table modifier values */ - case 512U: - S->pTwiddle = (void *)dct512_twiddle; - S->pCosFactor = (void *)dct512_cosFactor; - break; - - case 256U: - S->pTwiddle = (void *)dct256_twiddle; - S->pCosFactor = (void *)dct256_cosFactor; - break; - - case 128U: - S->pTwiddle = (void *)dct128_twiddle; - S->pCosFactor = (void *)dct128_cosFactor; - break; - - case 64U: - S->pTwiddle = (void *)dct64_twiddle; - S->pCosFactor = (void *)dct64_cosFactor; - break; - - case 32U: - S->pTwiddle = (void *)dct32_twiddle; - S->pCosFactor = (void *)dct32_cosFactor; - break; - - case 16U: - S->pTwiddle = (void *)dct16_twiddle; - S->pCosFactor = (void *)dct16_cosFactor; - break; - - default: - status = ARM_MATH_ARGUMENT_ERROR; - break; - } - - if (ARM_MATH_SUCCESS == status) - { - /* Initialize the RFFT/RIFFT Function */ - status = arm_rfft_init_q15(S->pRfft, S->N, 0, 1); - } - - /* return the status of DCT4 Init function */ - return status; -} - -void arm_dct4_q15(const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineBuffer) -{ - /* Calculate DCT-II for N-point input */ - uint16_t i; /* Loop counter */ - const q15_t *weights; /* Pointer to the Weights table */ - q15_t *pOut; /* Temporary pointers for output buffer */ - q15_t *pS1, *pbuff; /* Temporary pointers for input buffer and pState buffer */ - q15_t in; /* Temporary variable */ - const q15_t *cosFact; - uint32_t length; - uint8_t matRow; - uint8_t matCol; - uint8_t matLoop; - uint16_t lenPerMatLoop; - - /* - * Pre-processing involves multiplying input with cos factor, - * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*N)) - * where, - * r(n) -- output of preprocessing - * u(n) -- input to preprocessing(actual Source buffer) - */ - - /* - * Use matrix production function for preprocessing. Matrix production - * supports 16x16 at the most, so the matrix row is set to 16. - */ - matRow = 16U; - lenPerMatLoop = S->N >= 256U ? 256U : S->N; - matCol = (uint8_t)(lenPerMatLoop / 16U); - matLoop = (uint8_t)(((S->N - 1U) >> 8U) + 1U); - cosFact = S->pCosFactor; - pbuff = pInlineBuffer; - - length = POWERQUAD_MAKE_MATRIX_LEN(matRow, matCol, 0); - - while ((matLoop--) != 0U) - { - PQ_SET_MAT_FIX32_WORKAROUND_SCALE_CONFIG; - - /* cos factor is Q31, convert to float */ - PQ_MatrixScale(POWERQUAD, length, 2.0f / 2147483648.0f, cosFact, (void *)(uint32_t *)0xE0000000U); - cosFact = &cosFact[2U * lenPerMatLoop]; - - PQ_WaitDone(POWERQUAD); - - /* Product. */ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; - POWERQUAD->TMPBASE = 0xE0000000U; - - PQ_MatrixProduct(POWERQUAD, length, pbuff, (void *)(uint32_t *)0xE0000000U, pbuff); - - PQ_WaitDone(POWERQUAD); - - pbuff = &pbuff[lenPerMatLoop]; - } - - PQ_SET_FFT_Q15_CONFIG; - - PQ_TransformRDCT(POWERQUAD, S->N, pInlineBuffer, pState); - - /* ARM calculation while PQ is running. */ - /* - * Use matrix production function for twiddle multiplication. - * Matrix production supports 16x16 at the most. The total elements are 2*N; - */ - lenPerMatLoop = S->N >= 128U ? 128U : S->N; - matCol = (uint8_t)(lenPerMatLoop / 8U); - matLoop = (uint8_t)(((S->N - 1U) >> 7U) + 1U); - weights = S->pTwiddle; - pOut = pState; - - length = POWERQUAD_MAKE_MATRIX_LEN(matRow, matCol, matCol); - - PQ_WaitDone(POWERQUAD); - - while ((matLoop--) != 0U) - { - PQ_SET_MAT_FIX32_WORKAROUND_SCALE_CONFIG; - - /* Downscale by 1024 * 1024 * 16, because the twiddle are multiplied by 1024 * 1024 * 16. */ - PQ_MatrixScale(POWERQUAD, length, 1.0f / 16777216.0f, weights, (void *)(uint32_t *)0xE0000000U); - weights = &weights[lenPerMatLoop * 2U]; - - PQ_WaitDone(POWERQUAD); - - /* Product. */ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; - POWERQUAD->TMPBASE = 0xE0000000U; - - PQ_MatrixProduct(POWERQUAD, length, pOut, (void *)(uint32_t *)0xE0000000U, pOut); - - PQ_WaitDone(POWERQUAD); - - for (i = 0; i < lenPerMatLoop / 4U; i++) - { - pOut[0] -= pOut[1]; - pOut = &pOut[2]; - pOut[0] -= pOut[1]; - pOut = &pOut[2]; - pOut[0] -= pOut[1]; - pOut = &pOut[2]; - pOut[0] -= pOut[1]; - pOut = &pOut[2]; - } - } - - /* ----------- Post-processing ---------- */ - /* DCT-IV can be obtained from DCT-II by the equation, - * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) - * Hence, Y4(0) = Y2(0)/2 */ - /* Getting only real part from the output and Converting to DCT-IV */ - - /* pbuff initialized to input buffer. */ - pbuff = pInlineBuffer; - - /* pS1 initialized to pState */ - pS1 = pState; - - /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2. Considering the DCT II normalize, here divided by sqrt(2).*/ - in = (q15_t)(float)((float)*pS1 / 1.41421356237f); - *pbuff++ = in; - pS1 = &pS1[2]; - - in = *pS1 - in; - *pbuff++ = in; - pS1 = &pS1[2]; - - in = *pS1 - in; - *pbuff++ = in; - pS1 = &pS1[2]; - - in = *pS1 - in; - *pbuff++ = in; - pS1 = &pS1[2]; - - i = S->N / 4U - 1U; - - while (i > 0U) - { - in = *pS1 - in; - *pbuff++ = in; - pS1 = &pS1[2]; - - in = *pS1 - in; - *pbuff++ = in; - pS1 = &pS1[2]; - - in = *pS1 - in; - *pbuff++ = in; - pS1 = &pS1[2]; - - in = *pS1 - in; - *pbuff++ = in; - pS1 = &pS1[2]; - - i--; - } -} - -void arm_fir_init_f32( - arm_fir_instance_f32 *S, uint16_t numTaps, const float32_t *pCoeffs, float32_t *pState, uint32_t blockSize) -{ - uint32_t i; - - /* - * CMSIS DSP API filter coefficients stored in time reversed order, but PQ - * uses the positive order. PQ does not use pState, so pState pState[1:numTaps] - * is used here to save the coefficients in positive order. At the same time, - * pState[0] is used to save the offset used for incremetal calculation. - * Because the length of pState is (numTaps + blockSize -1), to ensure enough space, - * the blockSize should be larger than 1. - */ - assert(blockSize > 1U); - - S->numTaps = numTaps; - S->pCoeffs = pCoeffs; - S->pState = pState; - - for (i = 0U; i < numTaps; i++) - { - pState[numTaps - i] = pCoeffs[i]; - } - - *(uint32_t *)(void *)pState = 0U; -} - -void arm_fir_init_q31( - arm_fir_instance_q31 *S, uint16_t numTaps, const q31_t *pCoeffs, q31_t *pState, uint32_t blockSize) -{ - uint32_t i; - - /* - * CMSIS DSP API filter coefficients stored in time reversed order, but PQ - * uses the positive order. PQ does not use pState, so pState pState[1:numTaps] - * is used here to save the coefficients in positive order. At the same time, - * pState[0] is used to save the offset used for incremetal calculation. - * Because the length of pState is (numTaps + blockSize -1), to ensure enough space, - * the blockSize should be larger than 1. - */ - assert(blockSize > 1U); - - S->numTaps = numTaps; - S->pCoeffs = pCoeffs; - S->pState = pState; - - for (i = 0U; i < numTaps; i++) - { - pState[numTaps - i] = pCoeffs[i]; - } - - pState[0] = 0; -} - -arm_status arm_fir_init_q15( - arm_fir_instance_q15 *S, uint16_t numTaps, const q15_t *pCoeffs, q15_t *pState, uint32_t blockSize) -{ - uint16_t i; - - /* - * CMSIS DSP API filter coefficients stored in time reversed order, but PQ - * uses the positive order. PQ does not use pState, so pState pState[2:numTaps] - * is used here to save the coefficients in positive order. At the same time, - * pState[0:1] is used to save the offset used for incremetal calculation. - * Because the length of pState is (numTaps + blockSize -1), to ensure enough space, - * the blockSize should be larger than 2. - */ - assert(blockSize > 2U); - - S->numTaps = numTaps; - S->pCoeffs = pCoeffs; - S->pState = pState; - - for (i = 0U; i < numTaps; i++) - { - pState[numTaps + 1U - i] = pCoeffs[i]; - } - - *(uint32_t *)(void *)pState = 0U; - - return ARM_MATH_SUCCESS; -} - -/** - * brief Processing function for the floating-point FIR filter. - * param[in] S points to an instance of the floating-point FIR structure. - * param[in] pSrc points to the block of input data. - * param[out] pDst points to the block of output data. - * param[in] blockSize number of samples to process. - * - * Note: Powerquad has a hardware limitation, when using it for FIR increment calculation, the address of pSrc needs to - * be a continuous address. - */ -void arm_fir_f32(const arm_fir_instance_f32 *S, const float32_t *pSrc, float32_t *pDst, uint32_t blockSize) -{ - assert(NULL != S); - assert(NULL != pSrc); - assert(NULL != pDst); - - uint32_t curOffset; - PQ_SET_F32_CONFIG; - - curOffset = *(uint32_t *)(void *)(S->pState); - - if (curOffset == 0U) - { - PQ_FIR(POWERQUAD, pSrc, (int32_t)blockSize, &(S->pState[1]), (int32_t)S->numTaps, pDst, PQ_FIR_FIR); - } - else - { - _arm_fir_increment(pSrc, blockSize, &S->pState[1], S->numTaps, pDst, curOffset, sizeof(*pSrc)); - } - - *(uint32_t *)(void *)(S->pState) = curOffset + blockSize; - - PQ_WaitDone(POWERQUAD); -} - -void arm_fir_q31(const arm_fir_instance_q31 *S, const q31_t *pSrc, q31_t *pDst, uint32_t blockSize) -{ - assert(NULL != S); - assert(NULL != pSrc); - assert(NULL != pDst); - - uint32_t curOffset; - PQ_SET_Q31_CONFIG; - - curOffset = *(uint32_t *)(void *)(S->pState); - - if (curOffset == 0U) - { - PQ_FIR(POWERQUAD, pSrc, (int32_t)blockSize, &(S->pState[1]), (int32_t)S->numTaps, pDst, PQ_FIR_FIR); - } - else - { - _arm_fir_increment(pSrc, blockSize, &S->pState[1], S->numTaps, pDst, curOffset, sizeof(*pSrc)); - } - - *(uint32_t *)(void *)(S->pState) = curOffset + blockSize; - - PQ_WaitDone(POWERQUAD); -} - -void arm_fir_q15(const arm_fir_instance_q15 *S, const q15_t *pSrc, q15_t *pDst, uint32_t blockSize) -{ - assert(NULL != S); - assert(NULL != pSrc); - assert(NULL != pDst); - - uint32_t curOffset; - - PQ_SET_Q15_CONFIG; - - curOffset = *(uint32_t *)(void *)(S->pState); - - if (curOffset == 0U) - { - PQ_FIR(POWERQUAD, pSrc, (int32_t)blockSize, &(S->pState[2]), (int32_t)S->numTaps, pDst, PQ_FIR_FIR); - } - else - { - _arm_fir_increment(pSrc, blockSize, &S->pState[2], S->numTaps, pDst, curOffset, sizeof(*pSrc)); - } - - *(uint32_t *)(void *)(S->pState) = curOffset + blockSize; - - PQ_WaitDone(POWERQUAD); -} - -void arm_conv_f32(const float32_t *pSrcA, uint32_t srcALen, const float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst) -{ - assert(NULL != pSrcA); - assert(NULL != pSrcB); - assert(NULL != pDst); - - PQ_SET_F32_CONFIG; - - PQ_FIR(POWERQUAD, pSrcA, (int32_t)srcALen, pSrcB, (int32_t)srcBLen, pDst, PQ_FIR_CONVOLUTION); - PQ_WaitDone(POWERQUAD); -} - -void arm_conv_q31(const q31_t *pSrcA, uint32_t srcALen, const q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst) -{ - assert(NULL != pSrcA); - assert(NULL != pSrcB); - assert(NULL != pDst); - - PQ_SET_Q31_CONFIG; - - PQ_FIR(POWERQUAD, pSrcA, (int32_t)srcALen, pSrcB, (int32_t)srcBLen, pDst, PQ_FIR_CONVOLUTION); - PQ_WaitDone(POWERQUAD); -} - -void arm_conv_q15(const q15_t *pSrcA, uint32_t srcALen, const q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst) -{ - assert(NULL != pSrcA); - assert(NULL != pSrcB); - assert(NULL != pDst); - - PQ_SET_Q15_CONFIG; - - PQ_FIR(POWERQUAD, pSrcA, (int32_t)srcALen, pSrcB, (int32_t)srcBLen, pDst, PQ_FIR_CONVOLUTION); - PQ_WaitDone(POWERQUAD); -} - -void arm_correlate_f32( - const float32_t *pSrcA, uint32_t srcALen, const float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst) -{ - assert(NULL != pSrcA); - assert(NULL != pSrcB); - assert(NULL != pDst); - - PQ_SET_F32_CONFIG; - - PQ_FIR(POWERQUAD, pSrcA, (int32_t)srcALen, pSrcB, (int32_t)srcBLen, pDst, PQ_FIR_CORRELATION); - PQ_WaitDone(POWERQUAD); -} - -void arm_correlate_q31(const q31_t *pSrcA, uint32_t srcALen, const q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst) -{ - assert(NULL != pSrcA); - assert(NULL != pSrcB); - assert(NULL != pDst); - - PQ_SET_Q31_CONFIG; - - PQ_FIR(POWERQUAD, pSrcA, (int32_t)srcALen, pSrcB, (int32_t)srcBLen, pDst, PQ_FIR_CORRELATION); - PQ_WaitDone(POWERQUAD); -} - -void arm_correlate_q15(const q15_t *pSrcA, uint32_t srcALen, const q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst) -{ - assert(NULL != pSrcA); - assert(NULL != pSrcB); - assert(NULL != pDst); - - PQ_SET_Q15_CONFIG; - - PQ_FIR(POWERQUAD, pSrcA, (int32_t)srcALen, pSrcB, (int32_t)srcBLen, pDst, PQ_FIR_CORRELATION); - PQ_WaitDone(POWERQUAD); -} - -void arm_mat_init_f32(arm_matrix_instance_f32 *S, uint16_t nRows, uint16_t nColumns, float32_t *pData) -{ - /* Assign Number of Rows */ - S->numRows = nRows; - - /* Assign Number of Columns */ - S->numCols = nColumns; - - /* Assign Data pointer */ - S->pData = pData; -} - -void arm_mat_init_q31(arm_matrix_instance_q31 *S, uint16_t nRows, uint16_t nColumns, q31_t *pData) -{ - /* Assign Number of Rows */ - S->numRows = nRows; - - /* Assign Number of Columns */ - S->numCols = nColumns; - - /* Assign Data pointer */ - S->pData = pData; -} - -void arm_mat_init_q15(arm_matrix_instance_q15 *S, uint16_t nRows, uint16_t nColumns, q15_t *pData) -{ - /* Assign Number of Rows */ - S->numRows = nRows; - - /* Assign Number of Columns */ - S->numCols = nColumns; - - /* Assign Data pointer */ - S->pData = pData; -} - -arm_status arm_mat_add_f32(const arm_matrix_instance_f32 *pSrcA, - const arm_matrix_instance_f32 *pSrcB, - arm_matrix_instance_f32 *pDst) -{ - assert(NULL != pSrcA); - assert(NULL != pSrcB); - assert(NULL != pDst); - - arm_status status; - uint32_t length; - -#ifdef ARM_MATH_MATRIX_CHECK - /* Check for matrix mismatch condition */ - if ((pSrcA->numRows != pSrcB->numRows) || (pSrcA->numCols != pSrcB->numCols) || (pSrcA->numRows != pDst->numRows) || - (pSrcA->numCols != pDst->numCols)) - { - /* Set status as ARM_MATH_SIZE_MISMATCH */ - status = ARM_MATH_SIZE_MISMATCH; - } - else -#endif - { - PQ_SET_F32_CONFIG; - - length = POWERQUAD_MAKE_MATRIX_LEN(pSrcA->numRows, pSrcA->numCols, pSrcB->numCols); - - PQ_MatrixAddition(POWERQUAD, length, pSrcA->pData, pSrcB->pData, pDst->pData); - - /* Wait for the completion */ - PQ_WaitDone(POWERQUAD); - - status = ARM_MATH_SUCCESS; - } - - /* Return to application */ - return status; -} - -arm_status arm_mat_add_q31(const arm_matrix_instance_q31 *pSrcA, - const arm_matrix_instance_q31 *pSrcB, - arm_matrix_instance_q31 *pDst) -{ - assert(NULL != pSrcA); - assert(NULL != pSrcB); - assert(NULL != pDst); - - arm_status status; - uint32_t length; - -#ifdef ARM_MATH_MATRIX_CHECK - /* Check for matrix mismatch condition */ - if ((pSrcA->numRows != pSrcB->numRows) || (pSrcA->numCols != pSrcB->numCols) || (pSrcA->numRows != pDst->numRows) || - (pSrcA->numCols != pDst->numCols)) - { - /* Set status as ARM_MATH_SIZE_MISMATCH */ - status = ARM_MATH_SIZE_MISMATCH; - } - else -#endif - { - PQ_SET_FIX32_CONFIG; - - length = POWERQUAD_MAKE_MATRIX_LEN(pSrcA->numRows, pSrcA->numCols, pSrcB->numCols); - - PQ_MatrixAddition(POWERQUAD, length, pSrcA->pData, pSrcB->pData, pDst->pData); - - /* Wait for the completion */ - PQ_WaitDone(POWERQUAD); - - status = ARM_MATH_SUCCESS; - } - - /* Return to application */ - return status; -} - -arm_status arm_mat_add_q15(const arm_matrix_instance_q15 *pSrcA, - const arm_matrix_instance_q15 *pSrcB, - arm_matrix_instance_q15 *pDst) -{ - assert(NULL != pSrcA); - assert(NULL != pSrcB); - assert(NULL != pDst); - - arm_status status; - uint32_t length; - -#ifdef ARM_MATH_MATRIX_CHECK - /* Check for matrix mismatch condition */ - if ((pSrcA->numRows != pSrcB->numRows) || (pSrcA->numCols != pSrcB->numCols) || (pSrcA->numRows != pDst->numRows) || - (pSrcA->numCols != pDst->numCols)) - { - /* Set status as ARM_MATH_SIZE_MISMATCH */ - status = ARM_MATH_SIZE_MISMATCH; - } - else -#endif - { - PQ_SET_FIX16_CONFIG; - - length = POWERQUAD_MAKE_MATRIX_LEN(pSrcA->numRows, pSrcA->numCols, pSrcB->numCols); - - PQ_MatrixAddition(POWERQUAD, length, pSrcA->pData, pSrcB->pData, pDst->pData); - - /* Wait for the completion */ - PQ_WaitDone(POWERQUAD); - - status = ARM_MATH_SUCCESS; - } - - /* Return to application */ - return status; -} - -arm_status arm_mat_sub_f32(const arm_matrix_instance_f32 *pSrcA, - const arm_matrix_instance_f32 *pSrcB, - arm_matrix_instance_f32 *pDst) -{ - assert(NULL != pSrcA); - assert(NULL != pSrcB); - assert(NULL != pDst); - - arm_status status; - uint32_t length; - -#ifdef ARM_MATH_MATRIX_CHECK - /* Check for matrix mismatch condition */ - if ((pSrcA->numRows != pSrcB->numRows) || (pSrcA->numCols != pSrcB->numCols) || (pSrcA->numRows != pDst->numRows) || - (pSrcA->numCols != pDst->numCols)) - { - /* Set status as ARM_MATH_SIZE_MISMATCH */ - status = ARM_MATH_SIZE_MISMATCH; - } - else -#endif - { - PQ_SET_F32_CONFIG; - - length = POWERQUAD_MAKE_MATRIX_LEN(pSrcA->numRows, pSrcA->numCols, pSrcB->numCols); - - PQ_MatrixSubtraction(POWERQUAD, length, pSrcA->pData, pSrcB->pData, pDst->pData); - - /* Wait for the completion */ - PQ_WaitDone(POWERQUAD); - - status = ARM_MATH_SUCCESS; - } - - /* Return to application */ - return status; -} - -arm_status arm_mat_sub_q31(const arm_matrix_instance_q31 *pSrcA, - const arm_matrix_instance_q31 *pSrcB, - arm_matrix_instance_q31 *pDst) -{ - assert(NULL != pSrcA); - assert(NULL != pSrcB); - assert(NULL != pDst); - - arm_status status; - uint32_t length; - -#ifdef ARM_MATH_MATRIX_CHECK - /* Check for matrix mismatch condition */ - if ((pSrcA->numRows != pSrcB->numRows) || (pSrcA->numCols != pSrcB->numCols) || (pSrcA->numRows != pDst->numRows) || - (pSrcA->numCols != pDst->numCols)) - { - /* Set status as ARM_MATH_SIZE_MISMATCH */ - status = ARM_MATH_SIZE_MISMATCH; - } - else -#endif - { - PQ_SET_FIX32_CONFIG; - - length = POWERQUAD_MAKE_MATRIX_LEN(pSrcA->numRows, pSrcA->numCols, pSrcB->numCols); - - PQ_MatrixSubtraction(POWERQUAD, length, pSrcA->pData, pSrcB->pData, pDst->pData); - - /* Wait for the completion */ - PQ_WaitDone(POWERQUAD); - - status = ARM_MATH_SUCCESS; - } - - /* Return to application */ - return status; -} - -arm_status arm_mat_sub_q15(const arm_matrix_instance_q15 *pSrcA, - const arm_matrix_instance_q15 *pSrcB, - arm_matrix_instance_q15 *pDst) -{ - assert(NULL != pSrcA); - assert(NULL != pSrcB); - assert(NULL != pDst); - - arm_status status; - uint32_t length; - -#ifdef ARM_MATH_MATRIX_CHECK - /* Check for matrix mismatch condition */ - if ((pSrcA->numRows != pSrcB->numRows) || (pSrcA->numCols != pSrcB->numCols) || (pSrcA->numRows != pDst->numRows) || - (pSrcA->numCols != pDst->numCols)) - { - /* Set status as ARM_MATH_SIZE_MISMATCH */ - status = ARM_MATH_SIZE_MISMATCH; - } - else -#endif - { - PQ_SET_FIX16_CONFIG; - - length = POWERQUAD_MAKE_MATRIX_LEN(pSrcA->numRows, pSrcA->numCols, pSrcB->numCols); - - PQ_MatrixSubtraction(POWERQUAD, length, pSrcA->pData, pSrcB->pData, pDst->pData); - - /* Wait for the completion */ - PQ_WaitDone(POWERQUAD); - - status = ARM_MATH_SUCCESS; - } - - /* Return to application */ - return status; -} - -arm_status arm_mat_mult_f32(const arm_matrix_instance_f32 *pSrcA, - const arm_matrix_instance_f32 *pSrcB, - arm_matrix_instance_f32 *pDst) -{ - assert(NULL != pSrcA); - assert(NULL != pSrcB); - assert(NULL != pDst); - - arm_status status; - uint32_t length; - -#ifdef ARM_MATH_MATRIX_CHECK - /* Check for matrix mismatch condition */ - if ((pSrcA->numRows != pSrcB->numRows) || (pSrcA->numCols != pSrcB->numCols) || (pSrcA->numRows != pDst->numRows) || - (pSrcA->numCols != pDst->numCols)) - { - /* Set status as ARM_MATH_SIZE_MISMATCH */ - status = ARM_MATH_SIZE_MISMATCH; - } - else -#endif - { - PQ_SET_F32_CONFIG; - - length = POWERQUAD_MAKE_MATRIX_LEN(pSrcA->numRows, pSrcA->numCols, pSrcB->numCols); - - PQ_MatrixMultiplication(POWERQUAD, length, pSrcA->pData, pSrcB->pData, pDst->pData); - - /* Wait for the completion */ - PQ_WaitDone(POWERQUAD); - - status = ARM_MATH_SUCCESS; - } - - /* Return to application */ - return status; -} - -arm_status arm_mat_mult_q31(const arm_matrix_instance_q31 *pSrcA, - const arm_matrix_instance_q31 *pSrcB, - arm_matrix_instance_q31 *pDst) -{ - assert(NULL != pSrcA); - assert(NULL != pSrcB); - assert(NULL != pDst); - - arm_status status; - uint32_t length; - - /* - * The output prescale does not supprt negative value due to hardware issue, - * workaround: - * 1. Downscale the matrix B and save the float output value to private memory. - * 2. Multiply the float matrix B in private memory with matrix A, output as Q31. - * Note: Put matrix B in private memory is faster. - */ - -#ifdef ARM_MATH_MATRIX_CHECK - /* Check for matrix mismatch condition */ - if ((pSrcA->numRows != pSrcB->numRows) || (pSrcA->numCols != pSrcB->numCols) || (pSrcA->numRows != pDst->numRows) || - (pSrcA->numCols != pDst->numCols)) - { - /* Set status as ARM_MATH_SIZE_MISMATCH */ - status = ARM_MATH_SIZE_MISMATCH; - } - else -#endif - { - length = POWERQUAD_MAKE_MATRIX_LEN(pSrcB->numRows, pSrcB->numCols, 0U); - - PQ_SET_MAT_FIX32_WORKAROUND_SCALE_CONFIG; - - /* Downscale. */ - PQ_MatrixScale(POWERQUAD, length, 1.0f / 2147483648.0f, pSrcB->pData, (void *)(uint32_t *)0xE0000000U); - - length = POWERQUAD_MAKE_MATRIX_LEN(pSrcA->numRows, pSrcA->numCols, pSrcB->numCols); - - PQ_WaitDone(POWERQUAD); - - PQ_SET_MAT_FIX32_WORKAROUND_MULT_CONFIG; - - PQ_MatrixMultiplication(POWERQUAD, length, pSrcA->pData, (void *)(uint32_t *)0xE0000000U, pDst->pData); - - /* Wait for the completion */ - PQ_WaitDone(POWERQUAD); - - status = ARM_MATH_SUCCESS; - } - - /* Return to application */ - return status; -} - -arm_status arm_mat_mult_q15(const arm_matrix_instance_q15 *pSrcA, - const arm_matrix_instance_q15 *pSrcB, - arm_matrix_instance_q15 *pDst, - q15_t *pState) -{ - assert(NULL != pSrcA); - assert(NULL != pSrcB); - assert(NULL != pDst); - - arm_status status; - uint32_t length; - -#ifdef ARM_MATH_MATRIX_CHECK - /* Check for matrix mismatch condition */ - if ((pSrcA->numRows != pSrcB->numRows) || (pSrcA->numCols != pSrcB->numCols) || (pSrcA->numRows != pDst->numRows) || - (pSrcA->numCols != pDst->numCols)) - { - /* Set status as ARM_MATH_SIZE_MISMATCH */ - status = ARM_MATH_SIZE_MISMATCH; - } - else -#endif - { - length = POWERQUAD_MAKE_MATRIX_LEN(pSrcB->numRows, pSrcB->numCols, 0U); - - PQ_SET_MAT_FIX16_WORKAROUND_SCALE_CONFIG; - - /* Downscale. */ - PQ_MatrixScale(POWERQUAD, length, 1.0f / 32768.0f, pSrcB->pData, (void *)(uint32_t *)0xE0000000U); - - length = POWERQUAD_MAKE_MATRIX_LEN(pSrcA->numRows, pSrcA->numCols, pSrcB->numCols); - - PQ_WaitDone(POWERQUAD); - - PQ_SET_MAT_FIX16_WORKAROUND_MULT_CONFIG; - - PQ_MatrixMultiplication(POWERQUAD, length, pSrcA->pData, (void *)(uint32_t *)0xE0000000U, pDst->pData); - - /* Wait for the completion */ - PQ_WaitDone(POWERQUAD); - - status = ARM_MATH_SUCCESS; - } - - /* Return to application */ - return status; -} - -arm_status arm_mat_inverse_f32(const arm_matrix_instance_f32 *src, arm_matrix_instance_f32 *dst) -{ - assert(NULL != src); - assert(NULL != dst); - - arm_status status; - uint32_t length; - float tmp[1024]; - -#ifdef ARM_MATH_MATRIX_CHECK - /* Check for matrix mismatch condition */ - if ((src->numRows != src->numCols) || (dst->numRows != dst->numCols) || (src->numRows != dst->numRows)) - { - /* Set status as ARM_MATH_SIZE_MISMATCH */ - status = ARM_MATH_SIZE_MISMATCH; - } - else -#endif - { - PQ_SET_F32_CONFIG; - - length = POWERQUAD_MAKE_MATRIX_LEN(src->numRows, src->numCols, src->numRows); - - PQ_MatrixInversion(POWERQUAD, length, src->pData, tmp, dst->pData); - - /* Wait for the completion */ - PQ_WaitDone(POWERQUAD); - - status = ARM_MATH_SUCCESS; - } - - /* Return to application */ - return status; -} - -arm_status arm_mat_trans_f32(const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst) -{ - assert(NULL != pSrc); - assert(NULL != pDst); - - arm_status status; - uint32_t length; - -#ifdef ARM_MATH_MATRIX_CHECK - /* Check for matrix mismatch condition */ - if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols) || (pSrc->numRows != pDst->numRows)) - { - /* Set status as ARM_MATH_SIZE_MISMATCH */ - status = ARM_MATH_SIZE_MISMATCH; - } - else -#endif - { - length = POWERQUAD_MAKE_MATRIX_LEN(pSrc->numRows, pSrc->numCols, 0U); - - PQ_SetFormat(POWERQUAD, kPQ_CP_MTX, kPQ_Float); - - PQ_MatrixTranspose(POWERQUAD, length, pSrc->pData, pDst->pData); - - /* Wait for the completion */ - PQ_WaitDone(POWERQUAD); - status = ARM_MATH_SUCCESS; - } - - /* Return to application */ - return status; -} - -arm_status arm_mat_trans_q31(const arm_matrix_instance_q31 *pSrc, arm_matrix_instance_q31 *pDst) -{ - assert(NULL != pSrc); - assert(NULL != pDst); - - arm_status status; - uint32_t length; - -#ifdef ARM_MATH_MATRIX_CHECK - /* Check for matrix mismatch condition */ - if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols) || (pSrc->numRows != pDst->numRows)) - { - /* Set status as ARM_MATH_SIZE_MISMATCH */ - status = ARM_MATH_SIZE_MISMATCH; - } - else -#endif - { - PQ_SET_FIX32_CONFIG; - - length = POWERQUAD_MAKE_MATRIX_LEN(pSrc->numRows, pSrc->numCols, 0U); - - PQ_MatrixTranspose(POWERQUAD, length, pSrc->pData, pDst->pData); - - /* Wait for the completion */ - PQ_WaitDone(POWERQUAD); - - status = ARM_MATH_SUCCESS; - } - - /* Return to application */ - return status; -} - -arm_status arm_mat_trans_q15(const arm_matrix_instance_q15 *pSrc, arm_matrix_instance_q15 *pDst) -{ - assert(NULL != pSrc); - assert(NULL != pDst); - - arm_status status; - uint32_t length; - -#ifdef ARM_MATH_MATRIX_CHECK - /* Check for matrix mismatch condition */ - if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols) || (pSrc->numRows != pDst->numRows)) - { - /* Set status as ARM_MATH_SIZE_MISMATCH */ - status = ARM_MATH_SIZE_MISMATCH; - } - else -#endif - { - PQ_SET_FIX16_CONFIG; - - length = POWERQUAD_MAKE_MATRIX_LEN(pSrc->numRows, pSrc->numCols, 0U); - - PQ_MatrixTranspose(POWERQUAD, length, pSrc->pData, pDst->pData); - - /* Wait for the completion */ - PQ_WaitDone(POWERQUAD); - - status = ARM_MATH_SUCCESS; - } - - /* Return to application */ - return status; -} - -arm_status arm_mat_scale_f32(const arm_matrix_instance_f32 *pSrc, float32_t scale, arm_matrix_instance_f32 *pDst) -{ - assert(NULL != pSrc); - assert(NULL != pDst); - - arm_status status; - uint32_t length; - -#ifdef ARM_MATH_MATRIX_CHECK - /* Check for matrix mismatch condition */ - if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols) || (pSrc->numRows != pDst->numRows)) - { - /* Set status as ARM_MATH_SIZE_MISMATCH */ - status = ARM_MATH_SIZE_MISMATCH; - } - else -#endif - { - PQ_SET_F32_CONFIG; - - length = POWERQUAD_MAKE_MATRIX_LEN(pSrc->numRows, pSrc->numCols, 0U); - - PQ_MatrixScale(POWERQUAD, length, scale, pSrc->pData, pDst->pData); - - /* Wait for the completion */ - PQ_WaitDone(POWERQUAD); - - status = ARM_MATH_SUCCESS; - } - - /* Return to application */ - return status; -} - -arm_status arm_mat_scale_q31(const arm_matrix_instance_q31 *pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 *pDst) -{ - assert(NULL != pSrc); - assert(NULL != pDst); - - arm_status status; - uint32_t length; - float scaleFloat; - - pq_config_t config = { - kPQ_32Bit, /* inputAFormat */ - 0, /* inputAPrescale */ - kPQ_32Bit, /* inputBFormat */ - 0, /* inputBPrescale */ - kPQ_32Bit, /* outputFormat */ - (int8_t)shift, /* outputPrescale */ - kPQ_Float, /* tmpFormat */ - 0, /* tmpPrescale */ - kPQ_Float, /* machineFormat */ - (uint32_t *)0xe0000000U, /* tmpBase */ - }; - -#ifdef ARM_MATH_MATRIX_CHECK - /* Check for matrix mismatch condition */ - if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols) || (pSrc->numRows != pDst->numRows)) - { - /* Set status as ARM_MATH_SIZE_MISMATCH */ - status = ARM_MATH_SIZE_MISMATCH; - } - else -#endif - { - length = POWERQUAD_MAKE_MATRIX_LEN(pSrc->numRows, pSrc->numCols, 0U); - - scaleFloat = PQ_Q31_2_FLOAT(scaleFract); - - PQ_SetConfig(POWERQUAD, &config); - - PQ_MatrixScale(POWERQUAD, length, scaleFloat, pSrc->pData, pDst->pData); - - /* Wait for the completion */ - PQ_WaitDone(POWERQUAD); - - status = ARM_MATH_SUCCESS; - } - - /* Return to application */ - return status; -} - -arm_status arm_mat_scale_q15(const arm_matrix_instance_q15 *pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 *pDst) -{ - assert(NULL != pSrc); - assert(NULL != pDst); - - arm_status status; - uint32_t length; - float scaleFloat; - - pq_config_t config = { - kPQ_16Bit, /* inputAFormat */ - 0, /* inputAPrescale */ - kPQ_16Bit, /* inputBFormat */ - 0, /* inputBPrescale */ - kPQ_16Bit, /* outputFormat */ - (int8_t)shift, /* outputPrescale */ - kPQ_Float, /* tmpFormat */ - 0, /* tmpPrescale */ - kPQ_Float, /* machineFormat */ - (uint32_t *)0xe0000000U, /* tmpBase */ - }; - -#ifdef ARM_MATH_MATRIX_CHECK - /* Check for matrix mismatch condition */ - if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols) || (pSrc->numRows != pDst->numRows)) - { - /* Set status as ARM_MATH_SIZE_MISMATCH */ - status = ARM_MATH_SIZE_MISMATCH; - } - else -#endif - { - length = POWERQUAD_MAKE_MATRIX_LEN(pSrc->numRows, pSrc->numCols, 0U); - - scaleFloat = PQ_Q15_2_FLOAT(scaleFract); - - PQ_SetConfig(POWERQUAD, &config); - - PQ_MatrixScale(POWERQUAD, length, scaleFloat, pSrc->pData, pDst->pData); - - /* Wait for the completion */ - PQ_WaitDone(POWERQUAD); - - status = ARM_MATH_SUCCESS; - } - - /* Return to application */ - return status; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_data.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_data.c deleted file mode 100644 index a0b613263e0..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_data.c +++ /dev/null @@ -1,585 +0,0 @@ -/* - * Copyright 2018-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "fsl_powerquad_data.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.powerquad" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! - * @brief MATLAB script for calculating twiddle factor table for DCT is below,this gives phasor for FFTs twiddle at end - * of DCT, - * note that y is raw, scaled y is for fixed point multiplication. - * - * N=32; - * n=0; - * while(n - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -extern int32_t dct16_twiddle[32]; -extern int32_t dct32_twiddle[64]; -extern int32_t dct64_twiddle[128]; -extern int32_t dct128_twiddle[256]; -extern int32_t dct256_twiddle[512]; -extern int32_t dct512_twiddle[1024]; -extern int32_t idct16_twiddle[32]; -extern int32_t idct32_twiddle[64]; -extern int32_t idct64_twiddle[128]; -extern int32_t idct128_twiddle[256]; -extern int32_t idct256_twiddle[512]; -extern int32_t idct512_twiddle[1024]; -extern int32_t dct16_cosFactor[16]; -extern int32_t dct32_cosFactor[32]; -extern int32_t dct64_cosFactor[64]; -extern int32_t dct128_cosFactor[128]; -extern int32_t dct256_cosFactor[256]; -extern int32_t dct512_cosFactor[512]; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -#endif /* _FSL_POWERQUAD_DATA_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_filter.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_filter.c deleted file mode 100644 index e783fb33beb..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_filter.c +++ /dev/null @@ -1,429 +0,0 @@ -/* - * Copyright 2018-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_powerquad.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.powerquad_filter" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -void PQ_VectorBiqaudDf2F32(float *pSrc, float *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - pq_float_t val; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - val.floatX = *pSrc++; - _pq_biquad0(val.integerX); - val.integerX = _pq_readAdd0(); - *pDst++ = val.floatX; - } - } - - if (length > 0) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8BiquadDf2F32(); - PQ_EndVector(); - } -} - -void PQ_VectorBiqaudDf2Fixed32(int32_t *pSrc, int32_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - _pq_biquad0_fx(*pSrc++); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - } - } - - if (length > 0) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8BiquadDf2Fixed32(); - PQ_EndVector(); - } -} - -void PQ_VectorBiqaudDf2Fixed16(int16_t *pSrc, int16_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - _pq_biquad0_fx(*pSrc++); - *pDst++ = (int16_t)_pq_readAdd0_fx(); - } - } - - if (length > 0) - { - PQ_StartVectorFixed16(pSrc, pDst, length); - PQ_Vector8BiquadDf2Fixed16(); - PQ_EndVector(); - } -} - -void PQ_VectorBiqaudCascadeDf2F32(float *pSrc, float *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - pq_float_t val; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - - PQ_Biquad1F32(&pSrc[0], &pDst[0]); - - for (int i = 1; i < remainderBy8; i++) - { - val.floatX = pSrc[i - 1]; - _pq_biquad0(val.integerX); - - val.floatX = pSrc[i]; - _pq_biquad1(val.integerX); - - val.integerX = _pq_readAdd0(); - pDst[i - 1] = val.floatX; - - val.integerX = _pq_readAdd1(); - pDst[i] = val.floatX; - } - - PQ_BiquadF32(&pSrc[remainderBy8 - 1], &pDst[remainderBy8 - 1]); - } - - if (length > 0) - { - PQ_StartVector(&pSrc[remainderBy8], &pDst[remainderBy8], length); - PQ_Vector8BiqaudDf2CascadeF32(); - PQ_EndVector(); - } -} - -void PQ_VectorBiqaudCascadeDf2Fixed32(int32_t *pSrc, int32_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - - _pq_biquad1_fx(pSrc[0]); - pDst[0] = (int32_t)_pq_readAdd1_fx(); - - for (int i = 1; i < remainderBy8; i++) - { - _pq_biquad0_fx(pSrc[i - 1]); - _pq_biquad1_fx(pSrc[i]); - pDst[i - 1] = (int32_t)_pq_readAdd0_fx(); - pDst[i] = (int32_t)_pq_readAdd1_fx(); - } - - _pq_biquad0_fx(pSrc[remainderBy8 - 1]); - pDst[remainderBy8 - 1] = (int32_t)_pq_readAdd0_fx(); - } - - if (length > 0) - { - PQ_StartVector(&pSrc[remainderBy8], &pDst[remainderBy8], length); - PQ_Vector8BiqaudDf2CascadeFixed32(); - PQ_EndVector(); - } -} - -void PQ_VectorBiqaudCascadeDf2Fixed16(int16_t *pSrc, int16_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - - _pq_biquad1_fx(pSrc[0]); - pDst[0] = (int16_t)_pq_readAdd1_fx(); - - for (int i = 1; i < remainderBy8; i++) - { - _pq_biquad0_fx(pSrc[i - 1]); - _pq_biquad1_fx(pSrc[i]); - pDst[i - 1] = (int16_t)_pq_readAdd0_fx(); - pDst[i] = (int16_t)_pq_readAdd1_fx(); - } - - _pq_biquad0_fx(pSrc[remainderBy8 - 1]); - pDst[remainderBy8 - 1] = (int16_t)_pq_readAdd0_fx(); - } - - if (length > 0) - { - PQ_StartVectorFixed16(&pSrc[remainderBy8], &pDst[remainderBy8], length); - PQ_Vector8BiqaudDf2CascadeFixed16(); - PQ_EndVector(); - } -} - -void PQ_BiquadBackUpInternalState(POWERQUAD_Type *base, int32_t biquad_num, pq_biquad_state_t *state) -{ - pq_float_t v_n_1; - pq_float_t v_n; - -#if defined(__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-aliasing" -#endif - if (0 == biquad_num) - { - v_n_1.integerX = base->GPREG[0]; - v_n.integerX = base->GPREG[1]; - - state->param.v_n_1 = v_n_1.floatX; - state->param.v_n = v_n.floatX; - state->compreg = base->COMPREG[1]; - } - else - { - v_n_1.integerX = base->GPREG[8]; - v_n.integerX = base->GPREG[9]; - - state->param.v_n_1 = v_n_1.floatX; - state->param.v_n = v_n.floatX; - state->compreg = base->COMPREG[3]; - } -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif -} - -void PQ_BiquadRestoreInternalState(POWERQUAD_Type *base, int32_t biquad_num, pq_biquad_state_t *state) -{ - pq_float_t v_n_1; - pq_float_t v_n; - pq_float_t a_1; - pq_float_t a_2; - pq_float_t b_0; - pq_float_t b_1; - pq_float_t b_2; - - if (0 == biquad_num) - { - v_n_1.floatX = state->param.v_n_1; - v_n.floatX = state->param.v_n; - a_1.floatX = state->param.a_1; - a_2.floatX = state->param.a_2; - b_0.floatX = state->param.b_0; - b_1.floatX = state->param.b_1; - b_2.floatX = state->param.b_2; - - base->GPREG[0] = v_n_1.integerX; - base->GPREG[1] = v_n.integerX; - base->GPREG[2] = a_1.integerX; - base->GPREG[3] = a_2.integerX; - base->GPREG[4] = b_0.integerX; - base->GPREG[5] = b_1.integerX; - base->GPREG[6] = b_2.integerX; - base->COMPREG[1] = state->compreg; - } - else - { - v_n_1.floatX = state->param.v_n_1; - v_n.floatX = state->param.v_n; - a_1.floatX = state->param.a_1; - a_2.floatX = state->param.a_2; - b_0.floatX = state->param.b_0; - b_1.floatX = state->param.b_1; - b_2.floatX = state->param.b_2; - - base->GPREG[8] = v_n_1.integerX; - base->GPREG[9] = v_n.integerX; - base->GPREG[10] = a_1.integerX; - base->GPREG[11] = a_2.integerX; - base->GPREG[12] = b_0.integerX; - base->GPREG[13] = b_1.integerX; - base->GPREG[14] = b_2.integerX; - base->COMPREG[3] = state->compreg; - } -} - -void PQ_FIR(POWERQUAD_Type *base, - const void *pAData, - int32_t ALength, - const void *pBData, - int32_t BLength, - void *pResult, - uint32_t opType) -{ - assert(NULL != pAData); - assert(NULL != pBData); - assert(NULL != pResult); - - base->INABASE = (uint32_t)(const uint32_t *)pAData; - base->INBBASE = (uint32_t)(const uint32_t *)pBData; - base->LENGTH = ((uint32_t)BLength << 16U) + (uint32_t)ALength; - base->OUTBASE = (uint32_t)(uint32_t *)pResult; - base->CONTROL = (CP_FIR << 4U) | opType; -} - -void PQ_FIRIncrement(POWERQUAD_Type *base, int32_t ALength, int32_t BLength, int32_t xOffset) -{ - base->MISC = (uint32_t)xOffset; - base->LENGTH = ((uint32_t)BLength << 16U) + (uint32_t)ALength; - base->CONTROL = (CP_FIR << 4U) | PQ_FIR_INCREMENTAL; -} - -void PQ_BiquadCascadeDf2Init(pq_biquad_cascade_df2_instance *S, uint8_t numStages, pq_biquad_state_t *pState) -{ - S->numStages = numStages; - S->pState = pState; -} - -void PQ_BiquadCascadeDf2F32(const pq_biquad_cascade_df2_instance *S, float *pSrc, float *pDst, uint32_t blockSize) -{ - uint32_t stage = S->numStages; - pq_biquad_state_t *states = S->pState; - - if (pDst != pSrc) - { - (void)memcpy(pDst, pSrc, 4U * blockSize); - } - - if (stage % 2U != 0U) - { - PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); - - PQ_VectorBiqaudDf2F32(pSrc, pDst, (int32_t)blockSize); - - PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); - - states++; - stage--; - } - - do - { - PQ_BiquadRestoreInternalState(POWERQUAD, 1, states); - states++; - PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); - - PQ_VectorBiqaudCascadeDf2F32(pDst, pDst, (int32_t)blockSize); - - states--; - PQ_BiquadBackUpInternalState(POWERQUAD, 1, states); - states++; - PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); - - states++; - stage -= 2U; - - } while (stage > 0U); -} - -void PQ_BiquadCascadeDf2Fixed32(const pq_biquad_cascade_df2_instance *S, - int32_t *pSrc, - int32_t *pDst, - uint32_t blockSize) -{ - uint32_t stage = S->numStages; - pq_biquad_state_t *states = S->pState; - - if (pDst != pSrc) - { - (void)memcpy(pDst, pSrc, 4U * blockSize); - } - - if (stage % 2U != 0U) - { - PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); - - PQ_VectorBiqaudDf2Fixed32(pSrc, pDst, (int32_t)blockSize); - - PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); - - states++; - stage--; - } - - do - { - PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); - states++; - PQ_BiquadRestoreInternalState(POWERQUAD, 1, states); - - PQ_VectorBiqaudCascadeDf2Fixed32(pDst, pDst, (int32_t)blockSize); - - states--; - PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); - states++; - PQ_BiquadBackUpInternalState(POWERQUAD, 1, states); - - states++; - stage -= 2U; - } while (stage > 0U); -} - -void PQ_BiquadCascadeDf2Fixed16(const pq_biquad_cascade_df2_instance *S, - int16_t *pSrc, - int16_t *pDst, - uint32_t blockSize) -{ - uint32_t stage = S->numStages; - pq_biquad_state_t *states = S->pState; - - if (pDst != pSrc) - { - (void)memcpy(pDst, pSrc, 2U * blockSize); - } - - if (stage % 2U != 0U) - { - PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); - - PQ_VectorBiqaudDf2Fixed16(pSrc, pDst, (int32_t)blockSize); - - PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); - - states++; - stage--; - } - - do - { - PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); - states++; - PQ_BiquadRestoreInternalState(POWERQUAD, 1, states); - - PQ_VectorBiqaudCascadeDf2Fixed16(pDst, pDst, (int32_t)blockSize); - - states--; - PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); - states++; - PQ_BiquadBackUpInternalState(POWERQUAD, 1, states); - - states++; - stage -= 2U; - } while (stage > 0U); -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_math.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_math.c deleted file mode 100644 index 19d39f2e634..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_math.c +++ /dev/null @@ -1,888 +0,0 @@ -/* - * Copyright 2018-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_powerquad.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.powerquad_math" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -void PQ_VectorLnF32(float *pSrc, float *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - pq_float_t val; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - val.floatX = *pSrc++; - _pq_ln0(val.integerX); - val.integerX = _pq_readAdd0(); - *pDst++ = val.floatX; - } - } - - if (length > 0) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8F32(PQ_LN, 1, PQ_TRANS); - PQ_EndVector(); - } -} - -void PQ_VectorInvF32(float *pSrc, float *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - pq_float_t val; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - val.floatX = *pSrc++; - _pq_inv0(val.integerX); - val.integerX = _pq_readMult0(); - *pDst++ = val.floatX; - } - } - - if (length > 0) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8F32(PQ_INV, 0, PQ_TRANS); - PQ_EndVector(); - } -} - -void PQ_VectorSqrtF32(float *pSrc, float *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - pq_float_t val; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - val.floatX = *pSrc++; - _pq_sqrt0(val.integerX); - val.integerX = _pq_readMult0(); - *pDst++ = val.floatX; - } - } - - if (length > 0) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8F32(PQ_SQRT, 0, PQ_TRANS); - PQ_EndVector(); - } -} - -void PQ_VectorInvSqrtF32(float *pSrc, float *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - pq_float_t val; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - val.floatX = *pSrc++; - _pq_invsqrt0(val.integerX); - val.integerX = _pq_readMult0(); - *pDst++ = val.floatX; - } - } - - if (length > 0) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8F32(PQ_INVSQRT, 0, PQ_TRANS); - PQ_EndVector(); - } -} - -void PQ_VectorEtoxF32(float *pSrc, float *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - pq_float_t val; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - val.floatX = *pSrc++; - _pq_etox0(val.integerX); - val.integerX = _pq_readMult0(); - *pDst++ = val.floatX; - } - } - - if (length > 0) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8F32(PQ_ETOX, 0, PQ_TRANS); - PQ_EndVector(); - } -} - -void PQ_VectorEtonxF32(float *pSrc, float *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - pq_float_t val; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - val.floatX = *pSrc++; - _pq_etonx0(val.integerX); - val.integerX = _pq_readMult0(); - *pDst++ = val.floatX; - } - } - - if (length > 0) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8F32(PQ_ETONX, 0, PQ_TRANS); - PQ_EndVector(); - } -} - -void PQ_VectorSinF32(float *pSrc, float *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - pq_float_t val; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - val.floatX = *pSrc++; - _pq_sin0(val.integerX); - val.integerX = _pq_readAdd0(); - *pDst++ = val.floatX; - } - } - - if (length > 0) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8F32(PQ_SIN, 1, PQ_TRIG); - PQ_EndVector(); - } -} - -void PQ_VectorCosF32(float *pSrc, float *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - pq_float_t val; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - val.floatX = *pSrc++; - _pq_cos0(val.integerX); - val.integerX = _pq_readAdd0(); - *pDst++ = val.floatX; - } - } - - if (length > 0) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8F32(PQ_COS, 1, PQ_TRIG); - PQ_EndVector(); - } -} - -void PQ_VectorLnFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - _pq_ln_fx0(*pSrc++); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - } - } - - if (length > 0) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8Fixed32(PQ_LN, 1, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorInvFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - _pq_inv_fx0(*pSrc++); - *pDst++ = (int32_t)_pq_readMult0_fx(); - } - } - - if (length > 0) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8Fixed32(PQ_INV, 0, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorSqrtFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - _pq_sqrt_fx0(*pSrc++); - *pDst++ = (int32_t)_pq_readMult0_fx(); - } - } - - if (length > 0) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8Fixed32(PQ_SQRT, 0, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorInvSqrtFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - _pq_invsqrt_fx0(*pSrc++); - *pDst++ = (int32_t)_pq_readMult0_fx(); - } - } - - if (length > 0) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8Fixed32(PQ_INVSQRT, 0, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorEtoxFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - _pq_etox_fx0(*pSrc++); - *pDst++ = (int32_t)_pq_readMult0_fx(); - } - } - - if (length > 0) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8Fixed32(PQ_ETOX, 0, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorEtonxFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - _pq_etonx_fx0(*pSrc++); - *pDst++ = (int32_t)_pq_readMult0_fx(); - } - } - - if (length > 0) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8Fixed32(PQ_ETONX, 0, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorSinQ31(int32_t *pSrc, int32_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - uint32_t cppre; -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - pq_float_t magic; - pq_float_t valFloat; - - magic.integerX = 0x30c90fdbU; -#endif - - cppre = POWERQUAD->CPPRE; - POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); - -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - valFloat.floatX = magic.floatX * (float)(*pSrc++); - _pq_sin0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - } - } - - while (length > 0) - { - valFloat.floatX = magic.floatX * (float)(*pSrc++); - _pq_sin0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - - valFloat.floatX = magic.floatX * (float)(*pSrc++); - _pq_sin0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - - valFloat.floatX = magic.floatX * (float)(*pSrc++); - _pq_sin0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - - valFloat.floatX = magic.floatX * (float)(*pSrc++); - _pq_sin0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - - valFloat.floatX = magic.floatX * (float)(*pSrc++); - _pq_sin0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - - valFloat.floatX = magic.floatX * (float)(*pSrc++); - _pq_sin0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - - valFloat.floatX = magic.floatX * (float)(*pSrc++); - _pq_sin0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - - valFloat.floatX = magic.floatX * (float)(*pSrc++); - _pq_sin0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - - length -= 8; - } - -#else - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - _pq_sin_fx0(*pSrc++); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - } - } - - if (length > 0) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8Fixed32(PQ_SIN, 1, PQ_TRIG_FIXED); - PQ_EndVector(); - } -#endif - - POWERQUAD->CPPRE = cppre; -} - -void PQ_VectorCosQ31(int32_t *pSrc, int32_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - uint32_t cppre; -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - pq_float_t magic; - pq_float_t valFloat; - - magic.integerX = 0x30c90fdb; -#endif - - cppre = POWERQUAD->CPPRE; - POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); - -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - valFloat.floatX = magic.floatX * (float)(*pSrc++); - _pq_cos0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - } - } - - while (length > 0) - { - valFloat.floatX = magic.floatX * (float)(*pSrc++); - _pq_cos0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - - valFloat.floatX = magic.floatX * (float)(*pSrc++); - _pq_cos0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - - valFloat.floatX = magic.floatX * (float)(*pSrc++); - _pq_cos0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - - valFloat.floatX = magic.floatX * (float)(*pSrc++); - _pq_cos0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - - valFloat.floatX = magic.floatX * (float)(*pSrc++); - _pq_cos0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - - valFloat.floatX = magic.floatX * (float)(*pSrc++); - _pq_cos0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - - valFloat.floatX = magic.floatX * (float)(*pSrc++); - _pq_cos0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - - valFloat.floatX = magic.floatX * (float)(*pSrc++); - _pq_cos0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - - length -= 8; - } - -#else - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - _pq_cos_fx0(*pSrc++); - *pDst++ = (int32_t)_pq_readAdd0_fx(); - } - } - - if (length > 0) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8Fixed32(PQ_COS, 1, PQ_TRIG_FIXED); - PQ_EndVector(); - } -#endif - - POWERQUAD->CPPRE = cppre; -} - -void PQ_VectorLnFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - _pq_ln_fx0(*pSrc++); - *pDst++ = (int16_t)_pq_readAdd0_fx(); - } - } - - if (length > 0) - { - PQ_StartVectorFixed16(pSrc, pDst, length); - PQ_Vector8Fixed16(PQ_LN, 1, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorInvFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - _pq_inv_fx0(*pSrc++); - *pDst++ = (int16_t)_pq_readMult0_fx(); - } - } - - if (length > 0) - { - PQ_StartVectorFixed16(pSrc, pDst, length); - PQ_Vector8Fixed16(PQ_INV, 0, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorSqrtFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - _pq_sqrt_fx0(*pSrc++); - *pDst++ = (int16_t)_pq_readMult0_fx(); - } - } - - if (length > 0) - { - PQ_StartVectorFixed16(pSrc, pDst, length); - PQ_Vector8Fixed16(PQ_SQRT, 0, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorInvSqrtFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - _pq_invsqrt_fx0(*pSrc++); - *pDst++ = (int16_t)_pq_readMult0_fx(); - } - } - - if (length > 0) - { - PQ_StartVectorFixed16(pSrc, pDst, length); - PQ_Vector8Fixed16(PQ_INVSQRT, 0, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorEtoxFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - _pq_etox_fx0(*pSrc++); - *pDst++ = (int16_t)_pq_readMult0_fx(); - } - } - - if (length > 0) - { - PQ_StartVectorFixed16(pSrc, pDst, length); - PQ_Vector8Fixed16(PQ_ETOX, 0, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorEtonxFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - _pq_etonx_fx0(*pSrc++); - *pDst++ = (int16_t)_pq_readMult0_fx(); - } - } - - if (length > 0) - { - PQ_StartVectorFixed16(pSrc, pDst, length); - PQ_Vector8Fixed16(PQ_ETONX, 0, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorSinQ15(int16_t *pSrc, int16_t *pDst, int32_t length) -{ - uint32_t cppre; -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - pq_float_t magic; - pq_float_t valFloat; - - magic.integerX = 0x30c90fdb; -#endif - - cppre = POWERQUAD->CPPRE; - POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); - - int32_t remainderBy8 = length % 8; - -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); - _pq_sin0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - } - } - - while (length > 0) - { - valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); - _pq_sin0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - - valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); - _pq_sin0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - - valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); - _pq_sin0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - - valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); - _pq_sin0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - - valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); - _pq_sin0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - - valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); - _pq_sin0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - - valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); - _pq_sin0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - - valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); - _pq_sin0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - - length -= 8; - } - -#else - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - _pq_sin_fx0((uint32_t)(*pSrc++) << 16U); - *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - } - } - - if (length > 0) - { - PQ_StartVectorQ15(pSrc, pDst, length); - PQ_Vector8Q15(PQ_SIN, 1, PQ_TRIG_FIXED); - PQ_EndVector(); - } -#endif - - POWERQUAD->CPPRE = cppre; -} - -void PQ_VectorCosQ15(int16_t *pSrc, int16_t *pDst, int32_t length) -{ - uint32_t cppre; -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - pq_float_t magic; - pq_float_t valFloat; - - magic.integerX = 0x30c90fdbU; -#endif - - cppre = POWERQUAD->CPPRE; - POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); - - int32_t remainderBy8 = length % 8; - -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); - _pq_cos0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - } - } - - while (length > 0) - { - valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); - _pq_cos0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - - valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); - _pq_cos0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - - valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); - _pq_cos0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - - valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); - _pq_cos0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - - valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); - _pq_cos0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - - valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); - _pq_cos0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - - valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); - _pq_cos0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - - valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); - _pq_cos0(valFloat.integerX); - (void)_pq_readAdd0(); - *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - - length -= 8; - } - -#else - - if (remainderBy8 > 0) - { - length -= remainderBy8; - while ((remainderBy8--) > 0) - { - _pq_cos_fx0((uint32_t)(*pSrc++) << 16U); - *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - } - } - - if (length > 0) - { - PQ_StartVectorQ15(pSrc, pDst, length); - PQ_Vector8Q15(PQ_COS, 1, PQ_TRIG_FIXED); - PQ_EndVector(); - } -#endif - - POWERQUAD->CPPRE = cppre; -} - -int32_t PQ_ArctanFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_iter_t iteration) -{ - base->CORDIC_X = (uint32_t)x; - base->CORDIC_Y = (uint32_t)y; - base->CORDIC_Z = 0U; - base->CONTROL = (CP_CORDIC << 4U) | CORDIC_ARCTAN | CORDIC_ITER(iteration); - - PQ_WaitDone(base); - return (int32_t)base->CORDIC_Z; -} - -int32_t PQ_ArctanhFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_iter_t iteration) -{ - base->CORDIC_X = (uint32_t)x; - base->CORDIC_Y = (uint32_t)y; - base->CORDIC_Z = 0U; - base->CONTROL = (CP_CORDIC << 4U) | CORDIC_ARCTANH | CORDIC_ITER(iteration); - - PQ_WaitDone(base); - return (int32_t)base->CORDIC_Z; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_matrix.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_matrix.c deleted file mode 100644 index 6394cfd13bc..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_matrix.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright 2018-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_powerquad.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.powerquad_matrix" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -void PQ_MatrixAddition(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult) -{ - assert(NULL != pAData); - assert(NULL != pBData); - assert(NULL != pResult); - - base->OUTBASE = (uint32_t)(uint32_t *)pResult; - base->INABASE = (uint32_t)(uint32_t *)pAData; - base->INBBASE = (uint32_t)(uint32_t *)pBData; - base->LENGTH = length; - base->CONTROL = (CP_MTX << 4U) | PQ_MTX_ADD; -} - -void PQ_MatrixSubtraction(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult) -{ - assert(NULL != pAData); - assert(NULL != pBData); - assert(NULL != pResult); - - base->OUTBASE = (uint32_t)(uint32_t *)pResult; - base->INABASE = (uint32_t)(uint32_t *)pAData; - base->INBBASE = (uint32_t)(uint32_t *)pBData; - base->LENGTH = length; - base->CONTROL = (CP_MTX << 4U) | PQ_MTX_SUB; -} - -void PQ_MatrixMultiplication(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult) -{ - assert(NULL != pAData); - assert(NULL != pBData); - assert(NULL != pResult); - - base->OUTBASE = (uint32_t)(uint32_t *)pResult; - base->INABASE = (uint32_t)(uint32_t *)pAData; - base->INBBASE = (uint32_t)(uint32_t *)pBData; - base->LENGTH = length; - base->CONTROL = (CP_MTX << 4U) | PQ_MTX_MULT; -} - -void PQ_MatrixProduct(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult) -{ - assert(NULL != pAData); - assert(NULL != pBData); - assert(NULL != pResult); - - base->OUTBASE = (uint32_t)(uint32_t *)pResult; - base->INABASE = (uint32_t)(uint32_t *)pAData; - base->INBBASE = (uint32_t)(uint32_t *)pBData; - base->LENGTH = length; - base->CONTROL = (CP_MTX << 4U) | PQ_MTX_PROD; -} - -void PQ_VectorDotProduct(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult) -{ - assert(NULL != pAData); - assert(NULL != pBData); - assert(NULL != pResult); - - base->OUTBASE = (uint32_t)(uint32_t *)pResult; - base->INABASE = (uint32_t)(uint32_t *)pAData; - base->INBBASE = (uint32_t)(uint32_t *)pBData; - base->LENGTH = length; - base->CONTROL = (CP_MTX << 4U) | PQ_VEC_DOTP; -} - -void PQ_MatrixInversion(POWERQUAD_Type *base, uint32_t length, void *pData, void *pTmpData, void *pResult) -{ - assert(NULL != pData); - assert(NULL != pTmpData); - assert(NULL != pResult); - - /* Workaround: - * - * Matrix inv depends on the coproc 1/x function, this puts coproc to right state. - */ - _pq_inv0(1.0f); - - base->INABASE = (uint32_t)(uint32_t *)pData; - base->TMPBASE = (uint32_t)(uint32_t *)pTmpData; - base->OUTBASE = (uint32_t)(uint32_t *)pResult; - base->LENGTH = length; - base->CONTROL = (CP_MTX << 4U) | PQ_MTX_INV; -} - -void PQ_MatrixTranspose(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) -{ - assert(NULL != pData); - assert(NULL != pResult); - - base->OUTBASE = (uint32_t)(uint32_t *)pResult; - base->INABASE = (uint32_t)(uint32_t *)pData; - base->LENGTH = length; - base->CONTROL = (CP_MTX << 4U) | PQ_MTX_TRAN; -} - -void PQ_MatrixScale(POWERQUAD_Type *base, uint32_t length, float misc, const void *pData, void *pResult) -{ - assert(NULL != pData); - assert(NULL != pResult); - pq_float_t val; - - base->OUTBASE = (uint32_t)(uint32_t *)pResult; - base->INABASE = (uint32_t)(const uint32_t *)pData; - base->LENGTH = length; - - val.floatX = misc; - base->MISC = val.integerX; - - base->CONTROL = (CP_MTX << 4U) | PQ_MTX_SCALE; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_transform.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_transform.c deleted file mode 100644 index 9a7d3244f8f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_transform.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright 2018-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_powerquad.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.powerquad_transform" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -void PQ_TransformCFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) -{ - assert(NULL != pData); - assert(NULL != pResult); - - base->OUTBASE = (uint32_t)(uint32_t *)pResult; - base->INABASE = (uint32_t)(uint32_t *)pData; - base->LENGTH = length; - base->CONTROL = (CP_FFT << 4U) | PQ_TRANS_CFFT; -} - -void PQ_TransformRFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) -{ - assert(NULL != pData); - assert(NULL != pResult); - - /* Set 0's for imaginary inputs as not be reading them in by the machine */ - base->GPREG[1] = 0U; - base->GPREG[3] = 0U; - base->GPREG[5] = 0U; - base->GPREG[7] = 0U; - base->GPREG[9] = 0U; - base->GPREG[11] = 0U; - base->GPREG[13] = 0U; - base->GPREG[15] = 0U; - base->OUTBASE = (uint32_t)(uint32_t *)pResult; - base->INABASE = (uint32_t)(uint32_t *)pData; - base->LENGTH = length; - base->CONTROL = (CP_FFT << 4U) | PQ_TRANS_RFFT; -} - -void PQ_TransformIFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) -{ - assert(NULL != pData); - assert(NULL != pResult); - - base->OUTBASE = (uint32_t)(uint32_t *)pResult; - base->INABASE = (uint32_t)(uint32_t *)pData; - base->LENGTH = length; - base->CONTROL = (CP_FFT << 4U) | PQ_TRANS_IFFT; -} - -void PQ_TransformCDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) -{ - assert(NULL != pData); - assert(NULL != pResult); - - base->OUTBASE = (uint32_t)(uint32_t *)pResult; - base->INABASE = (uint32_t)(uint32_t *)pData; - base->LENGTH = length; - base->CONTROL = (CP_FFT << 4U) | PQ_TRANS_CDCT; -} - -void PQ_TransformRDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) -{ - assert(NULL != pData); - assert(NULL != pResult); - - base->GPREG[1] = 0U; - base->GPREG[3] = 0U; - base->GPREG[5] = 0U; - base->GPREG[7] = 0U; - base->GPREG[9] = 0U; - base->GPREG[11] = 0U; - base->GPREG[13] = 0U; - base->GPREG[15] = 0U; - base->OUTBASE = (uint32_t)(uint32_t *)pResult; - base->INABASE = (uint32_t)(uint32_t *)pData; - base->LENGTH = length; - base->CONTROL = (CP_FFT << 4U) | PQ_TRANS_RDCT; -} - -void PQ_TransformIDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) -{ - assert(NULL != pData); - assert(NULL != pResult); - - base->OUTBASE = (uint32_t)(uint32_t *)pResult; - base->INABASE = (uint32_t)(uint32_t *)pData; - base->LENGTH = length; - base->CONTROL = (CP_FFT << 4U) | PQ_TRANS_IDCT; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_prince.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_prince.c deleted file mode 100644 index 63e4c278528..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_prince.c +++ /dev/null @@ -1,1096 +0,0 @@ -/* - * Copyright 2018 - 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_prince.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ - -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.prince" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -static secure_bool_t PRINCE_CheckerAlgorithm(uint32_t address, - uint32_t length, - prince_flags_t flag, - flash_config_t *flash_context) -{ - uint32_t temp_base = 0, temp_sr = 0, region_index = 0, contiguous_start_index = 0, contiguous_end_index = 32; - secure_bool_t is_prince_region_contiguous = kSECURE_TRUE; - uint8_t prince_iv_code[FLASH_FFR_IV_CODE_SIZE] = {0}; - - if (address >= flash_context->ffrConfig.ffrBlockBase) - { - /* If it is not in flash region, return true to allow erase/write operation. */ - return kSECURE_TRUE; - } - - /* Iterate for all PRINCE regions */ - for (region_index = (uint32_t)kPRINCE_Region0; region_index <= (uint32_t)kPRINCE_Region2; region_index++) - { - contiguous_start_index = 0; - contiguous_end_index = 32; - switch (region_index) - { - case (uint32_t)kPRINCE_Region0: - temp_base = PRINCE->BASE_ADDR0; - temp_sr = PRINCE->SR_ENABLE0; - break; - - case (uint32_t)kPRINCE_Region1: - temp_base = PRINCE->BASE_ADDR1; - temp_sr = PRINCE->SR_ENABLE1; - break; - - case (uint32_t)kPRINCE_Region2: - temp_base = PRINCE->BASE_ADDR2; - temp_sr = PRINCE->SR_ENABLE2; - break; - - default: - /* All the cases have been listed above, the default clause should not be reached. */ - break; - } - - if (((address >= temp_base) && - ((address + length) < (temp_base + (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 32U * 1024U)))) && - (temp_sr != 0U)) - { - /* Check if the mask is contiguous */ - secure_bool_t first_set_bit_found = kSECURE_FALSE; - secure_bool_t contiguous_end_found = kSECURE_FALSE; - for (uint32_t i = 0; i < 32U; i++) - { - if (0U != (temp_sr & (1UL << i))) - { - if (kSECURE_FALSE == first_set_bit_found) - { - first_set_bit_found = kSECURE_TRUE; - contiguous_start_index = i; - } - if (kSECURE_TRUE == contiguous_end_found) - { - is_prince_region_contiguous = kSECURE_FALSE; - break; - } - } - else - { - if ((kSECURE_TRUE == first_set_bit_found) && (kSECURE_FALSE == contiguous_end_found)) - { - contiguous_end_found = kSECURE_TRUE; - contiguous_end_index = i; - } - } - } - } - else - { - continue; /* No encryption enabled, continue with the next region checking. */ - } - - /* Check if the provided memory range covers all addresses defined in the SR mask */ - if ((kSECURE_TRUE == is_prince_region_contiguous) && - ((address <= (temp_base + (contiguous_start_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U)))) && - (((address + length) >= - (temp_base + (contiguous_end_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U))))) - { - /* In case of erase operation, invalidate the old PRINCE IV by regenerating the new one */ - if (kPRINCE_Flag_EraseCheck == flag) - { - /* Re-generate the PRINCE IV in case of erase operation */ - - /* Generate new IV code for the PRINCE region and store the new IV into the respective FFRs */ - if (kStatus_Success == - PRINCE_GenNewIV((prince_region_t)region_index, &prince_iv_code[0], true, flash_context)) - { - /* Store the new IV for the PRINCE region into PRINCE registers. */ - if (kStatus_Success == PRINCE_LoadIV((prince_region_t)region_index, &prince_iv_code[0])) - { - /* Encryption is enabled, all subregions are to be erased/written at once, IV successfully - * regenerated, return true to allow erase operation. */ - return kSECURE_TRUE; - } - } - /* Encryption is enabled, all subregions are to be erased/written at once but IV has not been correctly - * regenerated, return false to disable erase operation. */ - return kSECURE_FALSE; - } - - /* Encryption is enabled and all subregions are to be erased/written at once, return true to allow - * erase/write operation. */ - return kSECURE_TRUE; - } - /* The provided memory range does not cover all addresses defined in the SR mask. */ - else - { - /* Is the provided memory range outside the addresses defined by the SR mask? */ - if ((kSECURE_TRUE == is_prince_region_contiguous) && - ((((address + length) <= - (temp_base + (contiguous_start_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U)))) || - ((address >= (temp_base + (contiguous_end_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U)))))) - { - /* No encryption enabled for the provided memory range, true could be returned to allow erase/write - operation, but due to the same base address for all three prince regions on Niobe4Mini we should - continue with other regions (SR mask) checking. */ - continue; - } - else - { - /* Encryption is enabled but not all subregions are to be erased/written at once, return false to - * disable erase/write operation. */ - return kSECURE_FALSE; - } - } - } - return kSECURE_TRUE; -} -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Generate new IV code. - * - * This function generates new IV code and stores it into the persistent memory. - * Ensure about 800 bytes free space on the stack when calling this routine with the store parameter set to true! - * - * @param region PRINCE region index. - * @param iv_code IV code pointer used for storing the newly generated 52 bytes long IV code. - * @param store flag to allow storing the newly generated IV code into the persistent memory (FFR). - * @param flash_context pointer to the flash driver context structure. - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise, kStatus_Fail is also returned if the key code for the particular - * PRINCE region is not present in the keystore (though new IV code has been provided) - */ -status_t PRINCE_GenNewIV(prince_region_t region, uint8_t *iv_code, bool store, flash_config_t *flash_context) -{ - status_t status = kStatus_Fail; - uint8_t prince_iv_code[FLASH_FFR_IV_CODE_SIZE] = {0}; - uint8_t tempBuffer[FLASH_FFR_MAX_PAGE_SIZE] = {0}; - - /* Make sure PUF is started to allow key and IV code decryption and generation */ - if (true != PUF_IsGetKeyAllowed(PUF)) - { - return status; - } - - /* Generate new IV code for the PRINCE region */ - status = - PUF_SetIntrinsicKey(PUF, (puf_key_index_register_t)(uint32_t)((uint32_t)kPUF_KeyIndex_02 + (uint32_t)region), 8, - &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); - if ((kStatus_Success == status) && (true == store)) - { - /* Store the new IV code for the PRINCE region into the respective FFRs. */ - /* Create a new version of "Customer Field Programmable" (CFP) page. */ - if ((int32_t)kStatus_FLASH_Success == - FFR_GetCustomerInfieldData(flash_context, (uint8_t *)tempBuffer, 0, FLASH_FFR_MAX_PAGE_SIZE)) - { - /* Set the IV code in the page */ - (void)memcpy(&tempBuffer[offsetof(cfpa_cfg_info_t, ivCodePrinceRegion) + - (((uint32_t)region * sizeof(cfpa_cfg_iv_code_t))) + 4U], - &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); - - uint32_t *p32 = (uint32_t *)(uint32_t)tempBuffer; - uint32_t version = p32[1]; - if (version == 0xFFFFFFFFu) - { - return kStatus_Fail; - } - version++; - p32[1] = version; - - /* Program the page and enable firewall for "Customer field area" */ - if ((int32_t)kStatus_FLASH_Success == - FFR_InfieldPageWrite(flash_context, (uint8_t *)tempBuffer, FLASH_FFR_MAX_PAGE_SIZE)) - { - status = kStatus_Success; - } - else - { - status = kStatus_Fail; - } - } - } - if (status == kStatus_Success) - { - /* Pass the new IV code */ - (void)memcpy(iv_code, &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); - } - - return status; -} -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Load IV code. - * - * This function enables IV code loading into the PRINCE bus encryption engine. - * - * @param region PRINCE region index. - * @param iv_code IV code pointer used for passing the IV code. - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise - */ -status_t PRINCE_LoadIV(prince_region_t region, uint8_t *iv_code) -{ - status_t status = kStatus_Fail; - uint32_t keyIndex = (0x0Fu & (uint32_t)iv_code[1]); - uint8_t prince_iv[8] = {0}; - - /* Make sure PUF is started to allow key and IV code decryption and generation */ - if (true != PUF_IsGetKeyAllowed(PUF)) - { - return kStatus_Fail; - } - - /* Check if region number matches the PUF index value */ - if (((uint32_t)kPUF_KeyIndex_02 + (uint32_t)region) == (uint32_t)keyIndex) - { - /* Decrypt the IV */ - if (kStatus_Success == PUF_GetKey(PUF, iv_code, FLASH_FFR_IV_CODE_SIZE, &prince_iv[0], 8)) - { - /* Store the new IV for the PRINCE region into PRINCE registers. */ - (void)PRINCE_SetRegionIV(PRINCE, (prince_region_t)region, prince_iv); - status = kStatus_Success; - } - } - - return status; -} -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Allow encryption/decryption for specified address range. - * - * This function sets the encryption/decryption for specified address range. - * The SR mask value for the selected Prince region is calculated from provided - * start_address and length parameters. This calculated value is OR'ed with the - * actual SR mask value and stored into the PRINCE SR_ENABLE register and also - * into the persistent memory (FFR) to be used after the device reset. It is - * possible to define several nonadjacent encrypted areas within one Prince - * region when calling this function repeatedly. If the length parameter is set - * to 0, the SR mask value is set to 0 and thus the encryption/decryption for - * the whole selected Prince region is disabled. - * Ensure about 800 bytes free space on the stack when calling this routine! - * - * @param region PRINCE region index. - * @param start_address start address of the area to be encrypted/decrypted. - * @param length length of the area to be encrypted/decrypted. - * @param flash_context pointer to the flash driver context structure. - * @param regenerate_iv flag to allow IV code regenerating, storing into - * the persistent memory (FFR) and loading into the PRINCE engine - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise - */ -status_t PRINCE_SetEncryptForAddressRange( - prince_region_t region, uint32_t start_address, uint32_t length, flash_config_t *flash_context, bool regenerate_iv) -{ - status_t status = kStatus_Fail; - uint32_t srEnableRegister = 0; - uint32_t alignedStartAddress; - uint32_t prince_base_addr_ffr_word = 0; - uint32_t end_address = start_address + length; - uint32_t prince_region_base_address = 0; - uint8_t tempBuffer[FLASH_FFR_MAX_PAGE_SIZE] = {0}; - - /* Check input parameters. */ - if (NULL == flash_context) - { - return kStatus_Fail; - } - - /* Check the address range, region borders crossing. */ -#if (defined(FSL_PRINCE_DRIVER_LPC55S0x)) || (defined(FSL_PRINCE_DRIVER_LPC55S1x)) || \ - (defined(FSL_PRINCE_DRIVER_LPC55S2x)) || (defined(FSL_PRINCE_DRIVER_LPC55S3x)) - if ((start_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) || - ((start_address < FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) && (end_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR))) - { - return kStatus_Fail; - } -#endif -#if (defined(FSL_PRINCE_DRIVER_LPC55S6x)) - if ((start_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) || - ((start_address < 0x40000U) && (end_address > 0x40000U)) || - ((start_address < 0x80000U) && (end_address > 0x80000U)) || - ((start_address < FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) && (end_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR))) - { - return kStatus_Fail; - } -#endif - - if (true == regenerate_iv) - { - uint8_t prince_iv_code[FLASH_FFR_IV_CODE_SIZE] = {0}; - - /* Generate new IV code for the PRINCE region and store the new IV into the respective FFRs */ - status = PRINCE_GenNewIV((prince_region_t)region, &prince_iv_code[0], true, flash_context); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - /* Store the new IV for the PRINCE region into PRINCE registers. */ - status = PRINCE_LoadIV((prince_region_t)region, &prince_iv_code[0]); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - } - - alignedStartAddress = ALIGN_DOWN(start_address, (int32_t)FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024); - - uint32_t subregion = alignedStartAddress / (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U); - if (subregion < (32U)) - { - /* PRINCE_Region0 */ - prince_region_base_address = 0; - } - else if (subregion < (64U)) - { - /* PRINCE_Region1 */ - subregion = subregion - 32U; - prince_region_base_address = 0x40000; - } - else - { - /* PRINCE_Region2 */ - subregion = subregion - 64U; - prince_region_base_address = 0x80000; - } - - /* If length > 0 then srEnableRegister mask is set based on the alignedStartAddress and the length. - If the length is 0, srEnableRegister should be kept 0 (no subregion enabled). */ - if (length != 0U) - { - srEnableRegister = (1UL << subregion); - alignedStartAddress += (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U); - - while (alignedStartAddress < (start_address + length)) - { - subregion++; - srEnableRegister |= (1UL << subregion); - alignedStartAddress += (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U); - } - - uint32_t srEnableRegisterActual = 0; - (void)PRINCE_GetRegionSREnable(PRINCE, (prince_region_t)region, &srEnableRegisterActual); - srEnableRegister |= srEnableRegisterActual; - } - - /* Store BASE_ADDR into PRINCE register before storing the SR to avoid en/decryption triggering - from addresses being defined by current BASE_ADDR register content (could be 0 and the decryption - of actually executed code can be started causing the hardfault then). */ - status = PRINCE_SetRegionBaseAddress(PRINCE, (prince_region_t)region, prince_region_base_address); - if (kStatus_Success != status) - { - return status; - } - - /* Store SR into PRINCE register */ - status = PRINCE_SetRegionSREnable(PRINCE, (prince_region_t)region, srEnableRegister); - if (kStatus_Success != status) - { - return status; - } - - /* Store SR and BASE_ADDR into CMPA FFR */ - if (kStatus_Success == FFR_GetCustomerData(flash_context, (uint8_t *)&tempBuffer, 0, FLASH_FFR_MAX_PAGE_SIZE)) - { - /* Set the PRINCE_SR_X in the page */ - (void)memcpy((uint32_t *)(uintptr_t)&tempBuffer[offsetof(cmpa_cfg_info_t, princeSr) + - ((uint32_t)region * sizeof(uint32_t))], - &srEnableRegister, sizeof(uint32_t)); - /* Set the ADDRX_PRG in the page */ - (void)memcpy(&prince_base_addr_ffr_word, - (const uint32_t *)(uintptr_t)&tempBuffer[offsetof(cmpa_cfg_info_t, princeBaseAddr)], - sizeof(uint32_t)); - prince_base_addr_ffr_word &= - ~(((uint32_t)FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) << ((uint32_t)region * 4U)); - prince_base_addr_ffr_word |= (((prince_region_base_address >> PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT) & - FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) - << ((uint32_t)region * 4U)); - (void)memcpy((uint32_t *)(uintptr_t)&tempBuffer[offsetof(cmpa_cfg_info_t, princeBaseAddr)], - &prince_base_addr_ffr_word, sizeof(uint32_t)); - - /* Program the CMPA page, set seal_part parameter to false (used during development to avoid sealing the - * part) - */ - status = FFR_CustFactoryPageWrite(flash_context, (uint8_t *)tempBuffer, false); - } - - return status; -} -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -/*! - * @brief Gets the PRINCE Sub-Region Enable register. - * - * This function gets PRINCE SR_ENABLE register. - * - * @param base PRINCE peripheral address. - * @param region PRINCE region index. - * @param sr_enable Sub-Region Enable register pointer. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_GetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t *sr_enable) -{ - status_t status = kStatus_Success; - - switch (region) - { - case kPRINCE_Region0: - *sr_enable = base->SR_ENABLE0; - break; - - case kPRINCE_Region1: - *sr_enable = base->SR_ENABLE1; - break; - - case kPRINCE_Region2: - *sr_enable = base->SR_ENABLE2; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - return status; -} - -/*! - * @brief Gets the PRINCE region base address register. - * - * This function gets PRINCE BASE_ADDR register. - * - * @param base PRINCE peripheral address. - * @param region PRINCE region index. - * @param region_base_addr Region base address pointer. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_GetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t *region_base_addr) -{ - status_t status = kStatus_Success; - - switch (region) - { - case kPRINCE_Region0: - *region_base_addr = base->BASE_ADDR0; - break; - - case kPRINCE_Region1: - *region_base_addr = base->BASE_ADDR1; - break; - - case kPRINCE_Region2: - *region_base_addr = base->BASE_ADDR2; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - return status; -} - -/*! - * @brief Sets the PRINCE region IV. - * - * This function sets specified AES IV for the given region. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param iv 64-bit AES IV in little-endian byte order. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_SetRegionIV(PRINCE_Type *base, prince_region_t region, const uint8_t iv[8]) -{ - status_t status = kStatus_Fail; - volatile uint32_t *IVMsb_reg = NULL; - volatile uint32_t *IVLsb_reg = NULL; - - switch (region) - { - case kPRINCE_Region0: - IVLsb_reg = &base->IV_LSB0; - IVMsb_reg = &base->IV_MSB0; - break; - - case kPRINCE_Region1: - IVLsb_reg = &base->IV_LSB1; - IVMsb_reg = &base->IV_MSB1; - break; - - case kPRINCE_Region2: - IVLsb_reg = &base->IV_LSB2; - IVMsb_reg = &base->IV_MSB2; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - if (status != kStatus_InvalidArgument) - { - *IVLsb_reg = ((uint32_t *)(uintptr_t)iv)[0]; - *IVMsb_reg = ((uint32_t *)(uintptr_t)iv)[1]; - status = kStatus_Success; - } - - return status; -} - -/*! - * @brief Sets the PRINCE region base address. - * - * This function configures PRINCE region base address. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param region_base_addr Base Address for region. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_SetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t region_base_addr) -{ - status_t status = kStatus_Success; - - /* Check input parameters. */ -#if (defined(FSL_PRINCE_DRIVER_LPC55S0x)) || (defined(FSL_PRINCE_DRIVER_LPC55S1x)) || \ - (defined(FSL_PRINCE_DRIVER_LPC55S2x)) || (defined(FSL_PRINCE_DRIVER_LPC55S3x)) - if (region_base_addr > 0U) - { - return kStatus_InvalidArgument; - } -#endif -#if (defined(FSL_PRINCE_DRIVER_LPC55S6x)) - if (region_base_addr > 0x80000U) - { - return kStatus_InvalidArgument; - } -#endif - - switch (region) - { - case kPRINCE_Region0: - base->BASE_ADDR0 = region_base_addr; - break; - - case kPRINCE_Region1: - base->BASE_ADDR1 = region_base_addr; - break; - - case kPRINCE_Region2: - base->BASE_ADDR2 = region_base_addr; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - return status; -} - -/*! - * @brief Sets the PRINCE Sub-Region Enable register. - * - * This function configures PRINCE SR_ENABLE register. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param sr_enable Sub-Region Enable register value. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_SetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t sr_enable) -{ - status_t status = kStatus_Success; - - switch (region) - { - case kPRINCE_Region0: - base->SR_ENABLE0 = sr_enable; - break; - - case kPRINCE_Region1: - base->SR_ENABLE1 = sr_enable; - break; - - case kPRINCE_Region2: - base->SR_ENABLE2 = sr_enable; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - return status; -} - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Erases the flash sectors encompassed by parameters passed into function. - * - * This function erases the appropriate number of flash sectors based on the - * desired start address and length. It deals with the flash erase function - * complenentary to the standard erase API of the IAP1 driver. This implementation - * additionally checks if the whole encrypted PRINCE subregions are erased at once - * to avoid secrets revealing. The checker implementation is limited to one contiguous - * PRINCE-controlled memory area. - * - * @param config The pointer to the flash driver context structure. - * @param start The start address of the desired flash memory to be erased. - * The start address needs to be prince-sburegion-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words) - * to be erased. Must be prince-sburegion-size-aligned. - * @param key The value used to validate all flash erase APIs. - * - * @return #kStatus_FLASH_Success API was executed successfully. - * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @return #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. - * @return #kStatus_FLASH_AddressError The address is out of range. - * @return #kStatus_FLASH_EraseKeyError The API erase key is invalid. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @return #kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce Encrypted flash subregions are not erased at once. - */ -status_t PRINCE_FlashEraseWithChecker(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) -{ - /* Check input parameters. */ - if (NULL == config) - { - return kStatus_Fail; - } - /* Check that the whole encrypted region is erased at once. */ - if (kSECURE_TRUE != PRINCE_CheckerAlgorithm(start, lengthInBytes, kPRINCE_Flag_EraseCheck, config)) - { - return (int32_t)kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce; - } - return FLASH_Erase(config, start, lengthInBytes, key); -} - -/*! - * @brief Programs flash with data at locations passed in through parameters. - * - * This function programs the flash memory with the desired data for a given - * flash area as determined by the start address and the length. It deals with the - * flash program function complenentary to the standard program API of the IAP1 driver. - * This implementation additionally checks if the whole PRINCE subregions are - * programmed at once to avoid secrets revealing. The checker implementation is limited - * to one contiguous PRINCE-controlled memory area. - * - * @param config The pointer to the flash driver context structure. - * @param start The start address of the desired flash memory to be programmed. Must be - * prince-sburegion-aligned. - * @param src A pointer to the source buffer of data that is to be programmed - * into the flash. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be programmed. Must be prince-sburegion-size-aligned. - * - * @return #kStatus_FLASH_Success API was executed successfully. - * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @return #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @return #kStatus_FLASH_AddressError Address is out of range. - * @return #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @return #kStatus_FLASH_SizeError Encrypted flash subregions are not programmed at once. - */ -status_t PRINCE_FlashProgramWithChecker(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) -{ - /* Check input parameters. */ - if (NULL == config) - { - return kStatus_Fail; - } - /* Check that the whole encrypted subregions will be writen at once. */ - if (kSECURE_TRUE != PRINCE_CheckerAlgorithm(start, lengthInBytes, kPRINCE_Flag_WriteCheck, config)) - { - return (int32_t)kStatus_FLASH_SizeError; - } - return FLASH_Program(config, start, src, lengthInBytes); -} -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if defined(FSL_PRINCE_DRIVER_LPC55S3x) -static status_t PRINCE_CSS_generate_random(uint8_t *output, size_t outputByteLen); -static status_t PRINCE_CSS_check_key(uint8_t keyIdx, mcuxClCss_KeyProp_t *pKeyProp); -static status_t PRINCE_CSS_gen_iv_key(void); -static status_t PRINCE_CSS_enable(void); -static status_t PRINCE_CSS_calculate_iv(uint32_t *IvReg); - -/*! - * @brief Configures PRINCE setting. - * - * This function does the initial PRINCE configuration via ROM IAP API call. - * PRINCE_SR_x configuration for each region configuration is stored into FFR (CMPA). - * PRINCE IV erase counters (MCTR_INT_IV_CTRx) in CFPA are updated accordingly. - * - * Note: This function is expected to be called once in the device lifetime, - * typically during the initial device provisioning, since it is programming the CMPA pages in PFR flash. - * - * @param coreCtx The pointer to the ROM API driver context structure. - * @param config The pointer to the PRINCE driver configuration structure. - * - * @retval #kStatus_Success - * @retval #kStatus_CommandUnsupported - * @retval #kStatus_InvalidArgument - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed - * @retval #kStatusMemoryRangeInvalid - * @retval #kStatus_Fail - * @retval #kStatus_OutOfRange - * @retval #kStatus_SPI_BaudrateNotSupport - */ -status_t PRINCE_Configure(api_core_context_t *coreCtx, prince_prot_region_arg_t *config) -{ - /* Enable CSS and check keys */ - if (kStatus_Success != PRINCE_CSS_enable()) - { - return kStatus_Fail; - } - - return MEM_Config(coreCtx, (uint32_t *)config, kMemoryInternal); -} - -/*! - * @brief Configures PRINCE setting. - * - * This function is used to re-configure PRINCE IP based on configuration stored in FFR. - * This function also needs to be called after wake up from power-down mode to regenerate IV - * encryption key in CSS key store whose presence is necessary for correct PRINCE operation - * during erase and write operations to encrypted regions of internal flash memory - * (dependency for correct operation of MEM_Erase() and MEM_Write() after wake up from power-down mode). - * - * @param coreCtx The pointer to the ROM API driver context structure. - * - * @retval #kStatus_Success - * @retval #kStatus_Fail - */ -status_t PRINCE_Reconfigure(api_core_context_t *coreCtx) -{ - status_t status = kStatus_Fail; - uint64_t princeMask; - uint32_t IvReg[4] = {0}; - uint32_t ivEraseCounter[3]; - uint32_t srEnable[3]; - uint32_t uuid[4]; - flash_config_t flash_config; - uint32_t lockWord; - uint8_t lock[3]; - - /* Enable CSS and check keys */ - status = PRINCE_CSS_enable(); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - /* Set PRINCE mask value. */ - status = PRINCE_CSS_generate_random((uint8_t *)&princeMask, sizeof(princeMask)); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - PRINCE_SetMask(PRINCE, princeMask); - - /* Clean up Flash driver structure and Init*/ - memset(&flash_config, 0, sizeof(flash_config_t)); - if (FLASH_Init(&flash_config) != kStatus_Success) - { - return kStatus_Fail; - } - - /* FFR Init */ - if (FFR_Init(&flash_config) != kStatus_Success) - { - return kStatus_Fail; - } - - /* Get UUID from FFR */ - status = FFR_GetUUID(&flash_config, (uint8_t *)uuid); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - /* Check version of CFPA scratch first */ - uint32_t cfpaScratchVer = 0u; - memcpy(&cfpaScratchVer, (void *)(CFPA_SCRATCH_VER), sizeof(uint32_t)); - - /* Get CFPA version using FFR ROM API */ - uint32_t cfpaVer = 0u; - if (kStatus_Success != - FFR_GetCustomerInfieldData(&flash_config, (uint8_t *)&cfpaVer, CFPA_VER_OFFSET, sizeof(uint32_t))) - { - status = kStatus_Fail; - return status; - } - - /* Compare the version of CFPA scratch and version of CFPA returned by ROM API */ - if (cfpaScratchVer > cfpaVer) - { - /* Get PRINCE_IV_CTRs from CFPA scratch */ - memcpy(&ivEraseCounter, (void *)CFPA_SCRATCH_IV, sizeof(uint32_t) * PRINCE_REGION_COUNT); - } - else - { - /* Get PRINCE_IV_CTRs IVs from CFPA ping/pong page */ - status = FFR_GetCustomerInfieldData(&flash_config, (uint8_t *)ivEraseCounter, CFPA_PRINCE_IV_OFFSET, - sizeof(uint32_t) * PRINCE_REGION_COUNT); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - } - - /* Get PRINCE sub-region enable word from FFR */ - status = FFR_GetCustomerData(&flash_config, (uint8_t *)srEnable, CMPA_PRINCE_SR_OFFSET, - sizeof(uint32_t) * PRINCE_REGION_COUNT); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - /* Get PRINCE lock setting from FFR */ - status = FFR_GetCustomerData(&flash_config, (uint8_t *)&lockWord, CMPA_PRINCE_LOCK_OFFSET, sizeof(uint32_t)); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - lock[0] = (lockWord & PRINCE_BASE_ADDR_LOCK_REG0_MASK) >> PRINCE_BASE_ADDR_LOCK_REG0_SHIFT; - lock[1] = (lockWord & PRINCE_BASE_ADDR_LOCK_REG1_MASK) >> PRINCE_BASE_ADDR_LOCK_REG1_SHIFT; - lock[2] = (lockWord & PRINCE_BASE_ADDR_LOCK_REG2_MASK) >> PRINCE_BASE_ADDR_LOCK_REG2_SHIFT; - - /* Iterate for all internal PRINCE regions */ - for (prince_region_t region = kPRINCE_Region0; region <= kPRINCE_Region2; region++) - { - /* Set region base address. Should be always 0x0 on LPC55S36 */ - status = PRINCE_SetRegionBaseAddress(PRINCE, (prince_region_t)region, 0x0u); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - status = PRINCE_SetRegionSREnable(PRINCE, region, srEnable[region]); - if (kStatus_Success != status) - { - return kStatus_Fail; - } - - /* Prepare ivSeed for current region */ - IvReg[0] = uuid[0]; - IvReg[1] = uuid[1]; - IvReg[2] = uuid[2] ^ region; - IvReg[3] = ivEraseCounter[region]; - - /* Calculate IV as IvReg = AES_ECB_ENC(DUK_derived_key, {ctx_erase_counter, ctx_id}) */ - status = PRINCE_CSS_calculate_iv(IvReg); - if (status != kStatus_Success) - { - return kStatus_Fail; - } - - /* Load IV into PRINCE registers */ - status = PRINCE_SetRegionIV(PRINCE, (prince_region_t)region, (uint8_t *)IvReg); - if (status != kStatus_Success) - { - return kStatus_Fail; - } - - /* Lock region if required */ - if ((lock[region] == 0x1u) || (lock[region] == 0x2u) || (lock[region] == 0x3u)) - { - PRINCE_SetLock(PRINCE, (kPRINCE_Region0Lock << region)); - } - } - - /* Break the main loop in case that error occured during PRINCE configuration */ - if (status != kStatus_Success) - { - return kStatus_Fail; - } - - /* When ENC_ENABLE is set, reading from PRINCE-encrypted regions is disabled. */ - /* For LPC55S36, the ENC_ENABLE is self-cleared after programming memory. */ - PRINCE_EncryptDisable(PRINCE); - return status; -} - -static status_t PRINCE_CSS_generate_random(uint8_t *output, size_t outputByteLen) -{ - status_t status = kStatus_Fail; - - // PRNG needs to be initialized; this can be done by calling mcuxClCss_KeyDelete_Async - // (delete any key slot, can be empty) - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_KeyDelete_Async(18)); - // mcuxClCss_KeyDelete_Async is a flow-protected function: Check the protection token and the return value - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_KeyDelete_Async) != token) || (MCUXCLCSS_STATUS_OK_WAIT != result)) - return kStatus_Fail; // Expect that no error occurred, meaning that the mcuxClCss_KeyDelete_Async operation was - // started. - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - // Wait for operation to finish - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_WaitForOperation(MCUXCLCSS_ERROR_FLAGS_CLEAR)); - // mcuxClCss_WaitForOperation is a flow-protected function: Check the protection token and the return value - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_WaitForOperation) != token) || (MCUXCLCSS_STATUS_OK != result)) - return kStatus_Fail; // Expect that no error occurred, meaning that the mcuxClCss_WaitForOperation operation was - // started. - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_Prng_GetRandom(output, outputByteLen)); - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_Prng_GetRandom) != token) || (MCUXCLCSS_STATUS_OK != result)) - return kStatus_Fail; - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - status = kStatus_Success; - return status; -} - -static status_t PRINCE_CSS_check_key(uint8_t keyIdx, mcuxClCss_KeyProp_t *pKeyProp) -{ - /* Check if CSS required keys are available in CSS keystore */ - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, - mcuxClCss_GetKeyProperties(keyIdx, pKeyProp)); // Get key propertis from the CSS. - // mcuxClCss_GetKeyProperties is a flow-protected function: Check the protection token and the return value - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_GetKeyProperties) != token) || (MCUXCLCSS_STATUS_OK != result)) - return kStatus_Fail; - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - return kStatus_Success; -} - -static status_t PRINCE_CSS_gen_iv_key(void) -{ - /* The NXP_DIE_MEM_IV_ENC_SK is not loaded and needs to be regenerated (power-down wakeup) */ - /* Set KDF mask and key properties for NXP_DIE_MEM_IV_ENC_SK */ - SYSCON->CSS_KDF_MASK = SYSCON_CSS_KDF_MASK; - static const uint32_t ddata2[3] = {0x62032504, 0x72f04280, 0x87a2bbae}; - mcuxClCss_KeyProp_t keyProp; - /* Set key properties in structure */ - keyProp.word.value = CSS_CSS_KS2_ks2_uaes_MASK | CSS_CSS_KS2_ks2_fgp_MASK | CSS_CSS_KS2_ks2_kact_MASK; - status_t status = kStatus_Fail; - - /* Generate the key using CKDF */ - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN( - result, token, - mcuxClCss_Ckdf_Sp800108_Async((mcuxClCss_KeyIndex_t)0, (mcuxClCss_KeyIndex_t)NXP_DIE_MEM_IV_ENC_SK, keyProp, - (uint8_t const *)ddata2)); - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_Ckdf_Sp800108_Async) != token) && (MCUXCLCSS_STATUS_OK != result)) - { - return kStatus_Fail; - } - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - /* Wait for CKDF to finish */ - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_WaitForOperation(MCUXCLCSS_ERROR_FLAGS_CLEAR)); - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_WaitForOperation) == token) && (MCUXCLCSS_STATUS_OK == result)) - { - status = kStatus_Success; - } - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - return status; -} - -static status_t PRINCE_CSS_enable(void) -{ - mcuxClCss_KeyProp_t key_properties; - status_t status = kStatus_Fail; - - /* Enable CSS and related clocks */ - status = CSS_PowerDownWakeupInit(CSS); - if (status != kStatus_Success) - { - return kStatus_Fail; - } - - /* Check if MEM_ENC_SK key is available in CSS keystore */ - status = PRINCE_CSS_check_key(NXP_DIE_MEM_ENC_SK, &key_properties); - if (status != kStatus_Success || key_properties.bits.kactv != 1u) - { - return kStatus_Fail; - } - - /* Check if MEM_IV_ENC_SK key is available in CSS keystore */ - status = PRINCE_CSS_check_key(NXP_DIE_MEM_IV_ENC_SK, &key_properties); - if (status != kStatus_Success || key_properties.bits.kactv != 1u) - { - return PRINCE_CSS_gen_iv_key(); - } - - return kStatus_Success; -} - -static status_t PRINCE_CSS_calculate_iv(uint32_t *IvReg) -{ - mcuxClCss_CipherOption_t cipherOptions = {0}; - status_t status = kStatus_Fail; - - /* Configure CSS for AES ECB-128, using NXP_DIE_MEM_IV_ENC_SK key */ - cipherOptions.bits.cphmde = MCUXCLCSS_CIPHERPARAM_ALGORITHM_AES_ECB; - cipherOptions.bits.dcrpt = MCUXCLCSS_CIPHER_ENCRYPT; - cipherOptions.bits.extkey = MCUXCLCSS_CIPHER_INTERNAL_KEY; - - do - { - /* Calculate IV as IvReg = AES_ECB_ENC(NXP_DIE_MEM_IV_ENC_SK, ivSeed[127:0]) */ - /* ivSeed[127:0] = {UUID[96:0] ^ regionNumber[1:0], ivEraseCounter[31:0]} */ - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN( - result, token, - mcuxClCss_Cipher_Async(cipherOptions, (mcuxClCss_KeyIndex_t)NXP_DIE_MEM_IV_ENC_SK, NULL, - MCUXCLCSS_CIPHER_KEY_SIZE_AES_128, (uint8_t *)IvReg, MCUXCLCSS_CIPHER_BLOCK_SIZE_AES, - NULL, (uint8_t *)IvReg)); - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_Cipher_Async) != token) || (MCUXCLCSS_STATUS_OK_WAIT != result)) - break; - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN( - result, token, - mcuxClCss_WaitForOperation( - MCUXCLCSS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClCss_Enable_Async operation to complete. - // mcuxClCss_WaitForOperation is a flow-protected function: Check the protection token and the return value - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_WaitForOperation) == token) && (MCUXCLCSS_STATUS_OK == result)) - { - status = kStatus_Success; - } - MCUX_CSSL_FP_FUNCTION_CALL_END(); - } while (0); - - return status; -} -#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_prince.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_prince.h deleted file mode 100644 index 1d702ae499b..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_prince.h +++ /dev/null @@ -1,522 +0,0 @@ -/* - * Copyright 2018 - 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_PRINCE_H_ -#define _FSL_PRINCE_H_ - -#include "fsl_common.h" - -#include FFR_INCLUDE - -/*! - * @addtogroup prince - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief PRINCE driver version 2.5.0. - * - * Current version: 2.5.0 - * - * Change log: - * - Version 2.0.0 - * - Initial version. - * - Version 2.1.0 - * - Update for the A1 rev. of LPC55Sxx serie. - * - Version 2.2.0 - * - Add runtime checking of the A0 and A1 rev. of LPC55Sxx serie to support - * both silicone revisions. - * - Version 2.3.0 - * - Add support for LPC55S1x and LPC55S2x series - * - Version 2.3.0 - * - Fix MISRA-2012 issues. - * - Version 2.3.1 - * - Add support for LPC55S0x series - * - Version 2.3.2 - * - Fix documentation of enumeration. Extend PRINCE example. - * - Version 2.4.0 - * - Add support for LPC55S3x series - * - Version 2.5.0 - * - Add PRINCE_Config() and PRINCE_Reconfig() features. - */ -#define FSL_PRINCE_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) -/*@}*/ - -#if (defined(LPC55S04_SERIES) || defined(LPC55S06_SERIES)) -/* LPC55S0x series*/ -#define FSL_PRINCE_DRIVER_LPC55S0x -#include "fsl_puf.h" - -#elif (defined(LPC55S14_SERIES) || defined(LPC55S16_SERIES)) -/* LPC55S1x series*/ -#define FSL_PRINCE_DRIVER_LPC55S1x -#include "fsl_puf.h" - -#elif (defined(LPC55S26_SERIES) || defined(LPC55S28_SERIES)) -/* LPC55S2x series*/ -#define FSL_PRINCE_DRIVER_LPC55S2x -#include "fsl_puf.h" - -#elif (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || \ - defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES)) -/* LPC55S6x series*/ -#define FSL_PRINCE_DRIVER_LPC55S6x -#include "fsl_puf.h" - -#elif (defined(LPC55S36_SERIES)) -/* LPC55S3x series*/ -#define FSL_PRINCE_DRIVER_LPC55S3x -#define PRINCE PRINCE0 -#include "fsl_mem_interface.h" -#include "fsl_css.h" // Power Down Wake-up Init -#include // Interface to the entire nxpClCss component -#include // Code flow protection -#else -#error "No valid CPU defined!" -#endif - -#define FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB (8U) -#define FSL_PRINCE_DRIVER_MAX_FLASH_ADDR \ - ((uint32_t)FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES - (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 2U * 1024U)) - -#if !defined(ALIGN_DOWN) -#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) -#endif - -/*! @brief Secure status enumeration. */ -typedef enum _skboot_status -{ - kStatus_SKBOOT_Success = 0x5ac3c35au, /*!< PRINCE Success */ - kStatus_SKBOOT_Fail = 0xc35ac35au, /*!< PRINCE Fail */ - kStatus_SKBOOT_InvalidArgument = 0xc35a5ac3u, /*!< PRINCE Invalid argument */ - kStatus_SKBOOT_KeyStoreMarkerInvalid = 0xc3c35a5au, /*!< PRINCE Invalid marker */ -} skboot_status_t; - -/*! @brief Secure boolean enumeration. */ -typedef enum _secure_bool -{ - kSECURE_TRUE = 0xc33cc33cU, /*!< PRINCE true */ - kSECURE_FALSE = 0x5aa55aa5U, /*!< PRINCE false */ -} secure_bool_t; - -/*! @brief Prince region. */ -typedef enum _prince_region -{ - kPRINCE_Region0 = 0U, /*!< PRINCE region 0 */ - kPRINCE_Region1 = 1U, /*!< PRINCE region 1 */ - kPRINCE_Region2 = 2U, /*!< PRINCE region 2 */ -} prince_region_t; - -/*! @brief Prince lock. */ -typedef enum _prince_lock -{ - kPRINCE_Region0Lock = 1U, /*!< PRINCE region 0 lock */ - kPRINCE_Region1Lock = 2U, /*!< PRINCE region 1 lock */ - kPRINCE_Region2Lock = 4U, /*!< PRINCE region 2 lock */ - kPRINCE_MaskLock = 256U, /*!< PRINCE mask register lock */ -} prince_lock_t; - -/*! @brief Prince flag. */ -typedef enum _prince_flags -{ - kPRINCE_Flag_None = 0U, /*!< PRINCE Flag None */ - kPRINCE_Flag_EraseCheck = 1U, /*!< PRINCE Flag Erase check */ - kPRINCE_Flag_WriteCheck = 2U, /*!< PRINCE Flag Write check */ -} prince_flags_t; - -#if defined(FSL_PRINCE_DRIVER_LPC55S3x) -typedef struct -{ - uint32_t target_prince_region : 2; // 0/1/2 - uint32_t reserved : 22; - uint32_t tag : 8; // Fixed to 0x50 ('P') -} prince_prot_region_option_t; -typedef struct -{ - prince_prot_region_option_t option; - uint32_t start; - uint32_t length; -} prince_prot_region_arg_t; - -/*! @brief Prince fixed tag in prince_prot_region_option_t structure */ -#define PRINCE_TAG 0x50u -#define PRINCE_TAG_SHIFT 24u -/*! @brief Prince region count */ -#define PRINCE_REGION_COUNT 3u -/*! @brief Define for CSS key store indexes */ -#define NXP_DIE_MEM_ENC_SK 2u -#define NXP_DIE_MEM_IV_ENC_SK 4u -/*! @brief KDF mask and key properties for NXP_DIE_MEM_IV_ENC_SK (see SYSCON documentation)*/ -#define SYSCON_CSS_KDF_MASK 0x07000FCF -/*! @brief CFPA version and IV indexes (see Protected Flash Region table) */ -#define CFPA_VER_OFFSET 0x04 -#define CFPA_PRINCE_IV_OFFSET 0x14u -/*! @brief CMPA SR and lock indexes (see Protected Flash Region table) */ -#define CMPA_PRINCE_SR_OFFSET 0x24u -#define CMPA_PRINCE_LOCK_OFFSET 0x20u -/*! @brief CFPA scrach version and IV addresses (see Protected Flash Region table) */ -#define CFPA_SCRATCH_VER 0x3dc04 -#define CFPA_SCRATCH_IV 0x3dc14 -/*! @brief CMPA lock bit-field defines (see Protected Flash Region table) */ -#define PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (16u) -#define PRINCE_BASE_ADDR_LOCK_REG0_MASK (0x3u << PRINCE_BASE_ADDR_LOCK_REG0_SHIFT) -#define PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (18u) -#define PRINCE_BASE_ADDR_LOCK_REG1_MASK (0x3u << PRINCE_BASE_ADDR_LOCK_REG1_SHIFT) -#define PRINCE_BASE_ADDR_LOCK_REG2_SHIFT (20u) -#define PRINCE_BASE_ADDR_LOCK_REG2_MASK (0x3u << PRINCE_BASE_ADDR_LOCK_REG2_SHIFT) - -#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Enable data encryption. - * - * This function enables PRINCE on-the-fly data encryption. - * - * @param base PRINCE peripheral address. - */ -static inline void PRINCE_EncryptEnable(PRINCE_Type *base) -{ - base->ENC_ENABLE = 1u; -} - -/*! - * @brief Disable data encryption. - * - * This function disables PRINCE on-the-fly data encryption. - * - * @param base PRINCE peripheral address. - */ -static inline void PRINCE_EncryptDisable(PRINCE_Type *base) -{ - base->ENC_ENABLE = 0u; -} - -/*! - * @brief Is Enable data encryption. - * - * This function test if PRINCE on-the-fly data encryption is enabled. - * - * @param base PRINCE peripheral address. - * @return true if enabled, false if not - */ -static inline bool PRINCE_IsEncryptEnable(PRINCE_Type *base) -{ - return (base->ENC_ENABLE == 1u) ? true : false; -} - -/*! - * @brief Sets PRINCE data mask. - * - * This function sets the PRINCE mask that is used to mask decrypted data. - * - * @param base PRINCE peripheral address. - * @param mask 64-bit data mask value. - */ -static inline void PRINCE_SetMask(PRINCE_Type *base, uint64_t mask) -{ - base->MASK_LSB = (uint32_t)(mask & 0xffffffffu); - base->MASK_MSB = (uint32_t)(mask >> 32u); -} - -/*! - * @brief Locks access for specified region registers or data mask register. - * - * This function sets lock on specified region registers or mask register. - * - * @param base PRINCE peripheral address. - * @param lock registers to lock. This is a logical OR of members of the - * enumeration ::prince_lock_t - */ -static inline void PRINCE_SetLock(PRINCE_Type *base, uint32_t lock) -{ - base->LOCK = lock & 0x1ffu; -} - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Generate new IV code. - * - * This function generates new IV code and stores it into the persistent memory. - * Ensure about 800 bytes free space on the stack when calling this routine with the store parameter set to true! - * - * @param region PRINCE region index. - * @param iv_code IV code pointer used for storing the newly generated 52 bytes long IV code. - * @param store flag to allow storing the newly generated IV code into the persistent memory (FFR). - * @param flash_context pointer to the flash driver context structure. - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise, kStatus_Fail is also returned if the key code for the particular - * PRINCE region is not present in the keystore (though new IV code has been provided) - */ -status_t PRINCE_GenNewIV(prince_region_t region, uint8_t *iv_code, bool store, flash_config_t *flash_context); -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Load IV code. - * - * This function enables IV code loading into the PRINCE bus encryption engine. - * - * @param region PRINCE region index. - * @param iv_code IV code pointer used for passing the IV code. - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise - */ -status_t PRINCE_LoadIV(prince_region_t region, uint8_t *iv_code); -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Allow encryption/decryption for specified address range. - * - * This function sets the encryption/decryption for specified address range. - * The SR mask value for the selected Prince region is calculated from provided - * start_address and length parameters. This calculated value is OR'ed with the - * actual SR mask value and stored into the PRINCE SR_ENABLE register and also - * into the persistent memory (FFR) to be used after the device reset. It is - * possible to define several nonadjacent encrypted areas within one Prince - * region when calling this function repeatedly. If the length parameter is set - * to 0, the SR mask value is set to 0 and thus the encryption/decryption for - * the whole selected Prince region is disabled. - * Ensure about 800 bytes free space on the stack when calling this routine! - * - * @param region PRINCE region index. - * @param start_address start address of the area to be encrypted/decrypted. - * @param length length of the area to be encrypted/decrypted. - * @param flash_context pointer to the flash driver context structure. - * @param regenerate_iv flag to allow IV code regenerating, storing into - * the persistent memory (FFR) and loading into the PRINCE engine - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise - */ -status_t PRINCE_SetEncryptForAddressRange( - prince_region_t region, uint32_t start_address, uint32_t length, flash_config_t *flash_context, bool regenerate_iv); -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -/*! - * @brief Gets the PRINCE Sub-Region Enable register. - * - * This function gets PRINCE SR_ENABLE register. - * - * @param base PRINCE peripheral address. - * @param region PRINCE region index. - * @param sr_enable Sub-Region Enable register pointer. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_GetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t *sr_enable); - -/*! - * @brief Gets the PRINCE region base address register. - * - * This function gets PRINCE BASE_ADDR register. - * - * @param base PRINCE peripheral address. - * @param region PRINCE region index. - * @param region_base_addr Region base address pointer. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_GetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t *region_base_addr); - -/*! - * @brief Sets the PRINCE region IV. - * - * This function sets specified AES IV for the given region. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param iv 64-bit AES IV in little-endian byte order. - */ -status_t PRINCE_SetRegionIV(PRINCE_Type *base, prince_region_t region, const uint8_t iv[8]); - -/*! - * @brief Sets the PRINCE region base address. - * - * This function configures PRINCE region base address. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param region_base_addr Base Address for region. - */ -status_t PRINCE_SetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t region_base_addr); - -/*! - * @brief Sets the PRINCE Sub-Region Enable register. - * - * This function configures PRINCE SR_ENABLE register. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param sr_enable Sub-Region Enable register value. - */ -status_t PRINCE_SetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t sr_enable); - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Erases the flash sectors encompassed by parameters passed into function. - * - * This function erases the appropriate number of flash sectors based on the - * desired start address and length. It deals with the flash erase function - * complenentary to the standard erase API of the IAP1 driver. This implementation - * additionally checks if the whole encrypted PRINCE subregions are erased at once - * to avoid secrets revealing. The checker implementation is limited to one contiguous - * PRINCE-controlled memory area. - * - * @param config The pointer to the flash driver context structure. - * @param start The start address of the desired flash memory to be erased. - * The start address needs to be prince-sburegion-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words) - * to be erased. Must be prince-sburegion-size-aligned. - * @param key The value used to validate all flash erase APIs. - * - * @return #kStatus_FLASH_Success API was executed successfully. - * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @return #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. - * @return #kStatus_FLASH_AddressError The address is out of range. - * @return #kStatus_FLASH_EraseKeyError The API erase key is invalid. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @return #kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce Encrypted flash subregions are not erased at once. - */ -status_t PRINCE_FlashEraseWithChecker(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Programs flash with data at locations passed in through parameters. - * - * This function programs the flash memory with the desired data for a given - * flash area as determined by the start address and the length. It deals with the - * flash program function complenentary to the standard program API of the IAP1 driver. - * This implementation additionally checks if the whole PRINCE subregions are - * programmed at once to avoid secrets revealing. The checker implementation is limited - * to one contiguous PRINCE-controlled memory area. - * - * @param config The pointer to the flash driver context structure. - * @param start The start address of the desired flash memory to be programmed. Must be - * prince-sburegion-aligned. - * @param src A pointer to the source buffer of data that is to be programmed - * into the flash. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be programmed. Must be prince-sburegion-size-aligned. - * - * @return #kStatus_FLASH_Success API was executed successfully. - * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @return #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @return #kStatus_FLASH_AddressError Address is out of range. - * @return #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - * @return #kStatus_FLASH_SizeError Encrypted flash subregions are not programmed at once. - */ -status_t PRINCE_FlashProgramWithChecker(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); -#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Configures PRINCE setting. - * - * This function does the initial PRINCE configuration via ROM IAP API call. - * PRINCE_SR_x configuration for each region configuration is stored into FFR (CMPA). - * PRINCE IV erase counters (MCTR_INT_IV_CTRx) in CFPA are updated accordingly. - * - * Note: This function is expected to be called once in the device lifetime, - * typically during the initial device provisioning, since it is programming the CMPA pages in PFR flash. - * - * @param coreCtx The pointer to the ROM API driver context structure. - * @param config The pointer to the PRINCE driver configuration structure. - * - * @retval #kStatus_Success - * @retval #kStatus_CommandUnsupported - * @retval #kStatus_InvalidArgument - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed - * @retval #kStatusMemoryRangeInvalid - * @retval #kStatus_Fail - * @retval #kStatus_OutOfRange - * @retval #kStatus_SPI_BaudrateNotSupport - */ -status_t PRINCE_Configure(api_core_context_t *coreCtx, prince_prot_region_arg_t *config); -#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Reconfigures PRINCE setting. - * - * This function is used to re-configure PRINCE IP based on configuration stored in FFR. - * This function also needs to be called after wake up from power-down mode to regenerate IV - * encryption key in CSS key store whose presence is necessary for correct PRINCE operation - * during erase and write operations to encrypted regions of internal flash memory - * (dependency for correct operation of MEM_Erase() and MEM_Write() after wake up from power-down mode). - * - * @param coreCtx The pointer to the ROM API driver context structure. - * - * @retval #kStatus_Success - * @retval #kStatus_CommandUnsupported - * @retval #kStatus_InvalidArgument - * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed - * @retval #kStatusMemoryRangeInvalid - * @retval #kStatus_Fail - * @retval #kStatus_OutOfRange - * @retval #kStatus_SPI_BaudrateNotSupport - */ -status_t PRINCE_Reconfigure(api_core_context_t *coreCtx); -#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if (defined(FSL_PRINCE_DRIVER_LPC55S0x)) || defined(FSL_PRINCE_DRIVER_LPC55S1x) || defined(FSL_PRINCE_DRIVER_LPC55S3x) -/*! - * @brief Gets the PRINCE Error status register. - * - * @param base PRINCE peripheral address. - * - * @return PRINCE Error status register - */ -static inline uint32_t PRINCE_GetErrorStatus(PRINCE_Type *base) -{ - return base->ERR; -} - -/*! - * @brief Clears the PRINCE Error status register. - * - * @param base PRINCE peripheral address. - */ -static inline void PRINCE_ClearErrorStatus(PRINCE_Type *base) -{ - base->ERR = 0U; -} -#endif /* defined(FSL_PRINCE_DRIVER_LPC55S0x) || defined(FSL_PRINCE_DRIVER_LPC55S1x) || \ - defined(FSL_PRINCE_DRIVER_LPC55S3x) */ - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_PRINCE_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_puf.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_puf.c deleted file mode 100644 index d82299ed243..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_puf.c +++ /dev/null @@ -1,949 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_puf.h" -#include "fsl_clock.h" -#include "fsl_common.h" - -#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) -#include "fsl_reset.h" -#endif /* FSL_FEATURE_PUF_HAS_NO_RESET */ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.puf" -#endif - -/* RT6xx POWER CONTROL bit masks */ -#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) -#define PUF_PWRCTRL_CKDIS_MASK (0x4U) -#define PUF_PWRCTRL_RAMINIT_MASK (0x8U) -#define PUF_PWRCTRL_RAMPSWLARGEMA_MASK (0x10U) -#define PUF_PWRCTRL_RAMPSWLARGEMP_MASK (0x20U) -#define PUF_PWRCTRL_RAMPSWSMALLMA_MASK (0x40U) -#define PUF_PWRCTRL_RAMPSWSMALLMP_MASK (0x80U) -#endif - -#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) -#define DEFAULT_CKGATING 0x0u -#define PUF_ENABLE_MASK 0xFFFFFFFEu -#define PUF_ENABLE_CTRL 0x1u - -#else -static void puf_wait_usec(volatile uint32_t usec, uint32_t coreClockFrequencyMHz) -{ - SDK_DelayAtLeastUs(usec, coreClockFrequencyMHz * 1000000U); - - /* Instead of calling SDK_DelayAtLeastUs() implement delay loop here */ - // while (usec > 0U) - // { - // usec--; - - // number of MHz is directly number of core clocks to wait 1 usec. - // the while loop below is actually 4 clocks so divide by 4 for ~1 usec - // volatile uint32_t ticksCount = coreClockFrequencyMHz / 4u + 1u; - // while (0U != ticksCount--) - // { - // } - // } -} -#endif /* defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) */ - -static status_t puf_waitForInit(PUF_Type *base) -{ - status_t status = kStatus_Fail; - - /* wait until status register reads non-zero. All zero is not valid. It should be BUSY or OK or ERROR */ - while (0U == base->STAT) - { - } - - /* wait if busy */ - while ((base->STAT & PUF_STAT_BUSY_MASK) != 0U) - { - } - - /* return status */ - if (0U != (base->STAT & (PUF_STAT_SUCCESS_MASK | PUF_STAT_ERROR_MASK))) - { - status = kStatus_Success; - } - - return status; -} - -static void puf_powerOn(PUF_Type *base, puf_config_t *conf) -{ -#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) - /* RT6xxs */ - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK); - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_RAMINIT_MASK); -#elif defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* LPCXpresso55s16 */ - conf->puf_sram_base->CFG |= PUF_ENABLE_CTRL; - while (0U == (PUF_SRAM_CTRL_STATUS_READY_MASK & conf->puf_sram_base->STATUS)) - { - } -#else /* !FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ - /* LPCXpresso55s69 & LPCXpresso54S018 */ - base->PWRCTRL = PUF_PWRCTRL_RAMON_MASK; - while (0U == (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL)) - { - } -#endif /* FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ -} -/*! - * brief Powercycle PUF - * - * This function make powercycle of PUF. - * - * param base PUF peripheral base address - * param conf PUF configuration structure - * return Status of the powercycle operation. - */ -status_t PUF_PowerCycle(PUF_Type *base, puf_config_t *conf) -{ -#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) - /* RT6xxs */ - uint32_t coreClockFrequencyMHz = conf->coreClockFrequencyHz / 1000000u; - - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* disable RAM CK */ - - /* enter ASPS mode */ - base->PWRCTRL = (PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* SLEEP = 1 */ - base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK); /* enable RAM CK */ - base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | PUF_PWRCTRL_RAMPSWLARGEMP_MASK | - PUF_PWRCTRL_RAMPSWSMALLMA_MASK | PUF_PWRCTRL_RAMPSWSMALLMP_MASK); /* SLEEP=1, PSW*=1 */ - - /* Wait enough time to discharge fully */ - puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); - - /* write PWRCTRL=0x38. wait time > 1 us */ - base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | - PUF_PWRCTRL_RAMPSWLARGEMP_MASK); /* SLEEP=1. PSWSMALL*=0. PSWLARGE*=1. */ - puf_wait_usec(1, coreClockFrequencyMHz); - - /* write PWRCTRL=0x8. wait time > 1 us */ - base->PWRCTRL = PUF_PWRCTRL_RAMINIT_MASK; /* SLEEP=1. PSWSMALL*=0. PSWLARGE*=0 */ - puf_wait_usec(1, coreClockFrequencyMHz); - - base->PWRCTRL = (PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_RAMINIT_MASK); - - /* Generate INITN low pulse */ - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK); - base->PWRCTRL = PUF_PWRCTRL_RAM_ON_MASK; -#elif defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* LPCXpresso55s16 */ - conf->puf_sram_base->CFG &= PUF_ENABLE_MASK; -#else - /* LPCXpresso55s69 & LPCXpresso54S018 */ - base->PWRCTRL = 0x0u; - while (0U != (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL)) - { - } - - /* Wait enough time to discharge fully */ - puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); -#endif - -#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) - /* Reset PUF and reenable power to PUF SRAM */ - RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); -#endif /* FSL_TEATURE_PUF_HAS_NO_RESET */ - puf_powerOn(base, conf); - - return kStatus_Success; -} - -/*! - * brief Sets the default configuration of PUF - * - * This function initialize PUF config structure to default values. - * - * param conf PUF configuration structure - */ -void PUF_GetDefaultConfig(puf_config_t *conf) -{ -#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* LPCXpresso55s16 */ - conf->puf_sram_base = PUF_SRAM_CTRL; - - /* Default configuration after reset */ - conf->CKGATING = DEFAULT_CKGATING; /* PUF SRAM Clock Gating */ -#endif /* FSL_FEATURE_PUF_HAS_SRAM_CTRL */ - - conf->dischargeTimeMsec = KEYSTORE_PUF_DISCHARGE_TIME_FIRST_TRY_MS; - conf->coreClockFrequencyHz = CLOCK_GetFreq(kCLOCK_CoreSysClk); - - return; -} - -/*! - * brief Initialize PUF - * - * This function enables power to PUF block and waits until the block initializes. - * - * param base PUF peripheral base address - * param conf PUF configuration structure - * return Status of the init operation - */ -status_t PUF_Init(PUF_Type *base, puf_config_t *conf) -{ - status_t status = kStatus_Fail; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Puf); -#endif -#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) - /* Reset PUF */ - RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); -#endif /* FSL_FEATURE_PUF_HAS_NO_RESET */ - -#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* Set configuration for SRAM */ - conf->puf_sram_base->CFG |= PUF_SRAM_CTRL_CFG_CKGATING(conf->CKGATING); - -#endif /* FSL_FEATURE_PUF_HAS_SRAM_CTRL */ - - /* Enable power to PUF SRAM */ - puf_powerOn(base, conf); - - /* Wait for peripheral to become ready */ - status = puf_waitForInit(base); - - /* In case of error or enroll or start not allowed, do power-cycle */ - /* First try with shorter discharge time, if then it also fails try with longer time */ - /* conf->dischargeTimeMsec = KEYSTORE_PUF_DISCHARGE_TIME_FIRST_TRY_MS; */ - if ((status != kStatus_Success) || (0U == (base->ALLOW & (PUF_ALLOW_ALLOWENROLL_MASK | PUF_ALLOW_ALLOWSTART_MASK)))) - { - (void)PUF_PowerCycle(base, conf); - status = puf_waitForInit(base); - } - - /* In case of error or enroll or start not allowed, do power-cycle with worst discharge timing */ - if ((status != kStatus_Success) || (0U == (base->ALLOW & (PUF_ALLOW_ALLOWENROLL_MASK | PUF_ALLOW_ALLOWSTART_MASK)))) - { - conf->dischargeTimeMsec = KEYSTORE_PUF_DISCHARGE_TIME_MAX_MS; - (void)PUF_PowerCycle(base, conf); - status = puf_waitForInit(base); - } - - return status; -} - -/*! - * brief Denitialize PUF - * - * This function disables power to PUF SRAM and peripheral clock. - * - * param base PUF peripheral base address - * param conf PUF configuration structure - */ -void PUF_Deinit(PUF_Type *base, puf_config_t *conf) -{ -#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) - /* RT6xxs */ - base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* disable RAM CK */ - - /* enter ASPS mode */ - base->PWRCTRL = (PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* SLEEP = 1 */ - base->PWRCTRL = PUF_PWRCTRL_RAMINIT_MASK; /* enable RAM CK */ - base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | PUF_PWRCTRL_RAMPSWLARGEMP_MASK | - PUF_PWRCTRL_RAMPSWSMALLMA_MASK | PUF_PWRCTRL_RAMPSWSMALLMP_MASK); /* SLEEP=1, PSW*=1 */ - puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); -#elif defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* LPCXpresso55s16 */ - conf->puf_sram_base = PUF_SRAM_CTRL; - conf->puf_sram_base->CFG &= PUF_ENABLE_MASK; -#else /* !FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ - /* LPCXpresso55s69 & LPCXpresso54S018 */ - base->PWRCTRL = 0x00u; - puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); -#endif - -#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) - RESET_SetPeripheralReset(kPUF_RST_SHIFT_RSTn); -#endif /* FSL_FEATURE_PUF_HAS_NO_RESET */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Puf); -#endif -} - -/*! - * brief Enroll PUF - * - * This function derives a digital fingerprint, generates the corresponding Activation Code (AC) - * and returns it to be stored in an NVM or a file. This step needs to be - * performed only once for each device. This function may be permanently disallowed by a fuse. - * - * param base PUF peripheral base address - * param[out] activationCode Word aligned address of the resulting activation code. - * param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. - * return Status of enroll operation. - */ -status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize) -{ - status_t status = kStatus_Fail; - uint32_t *activationCodeAligned = NULL; - register uint32_t temp32 = 0; - - /* check that activation code buffer size is at least 1192 bytes */ - if (activationCodeSize < PUF_ACTIVATION_CODE_SIZE) - { - return kStatus_InvalidArgument; - } - - /* only work with aligned activationCode */ - if (0U != (0x3u & (uintptr_t)activationCode)) - { - return kStatus_InvalidArgument; - } - - activationCodeAligned = (uint32_t *)(uintptr_t)activationCode; - - /* check if ENROLL is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWENROLL_MASK)) - { - return kStatus_EnrollNotAllowed; - } - - /* begin */ - base->CTRL = PUF_CTRL_ENROLL_MASK; - - /* check status */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* read out AC */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) - { - temp32 = base->CODEOUTPUT; - if (activationCodeSize >= sizeof(uint32_t)) - { - *activationCodeAligned = temp32; - activationCodeAligned++; - activationCodeSize -= sizeof(uint32_t); - } - } - } - - if (((base->STAT & PUF_STAT_SUCCESS_MASK) != 0U) && (activationCodeSize == 0U)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Start PUF - * - * The Activation Code generated during the Enroll operation is used to - * reconstruct the digital fingerprint. This needs to be done after every power-up - * and reset. - * - * param base PUF peripheral base address - * param activationCode Word aligned address of the input activation code. - * param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. - * return Status of start operation. - */ -status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize) -{ - status_t status = kStatus_Fail; - const uint32_t *activationCodeAligned = NULL; - register uint32_t temp32 = 0; - - /* check that activation code size is at least 1192 bytes */ - if (activationCodeSize < 1192U) - { - return kStatus_InvalidArgument; - } - - /* only work with aligned activationCode */ - if (0U != (0x3u & (uintptr_t)activationCode)) - { - return kStatus_InvalidArgument; - } - - activationCodeAligned = (const uint32_t *)(uintptr_t)activationCode; - - /* check if START is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSTART_MASK)) - { - return kStatus_StartNotAllowed; - } - - /* begin */ - base->CTRL = PUF_CTRL_START_MASK; - - /* check status */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy send AC */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_CODEINREQ_MASK & base->STAT)) - { - if (activationCodeSize >= sizeof(uint32_t)) - { - temp32 = *activationCodeAligned; - activationCodeAligned++; - activationCodeSize -= sizeof(uint32_t); - } - base->CODEINPUT = temp32; - } - } - - /* get status */ - if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Set intrinsic key - * - * The digital fingerprint generated during the Enroll/Start - * operations is used to generate a Key Code (KC) that defines a unique intrinsic - * key. This KC is returned to be stored in an NVM or a file. This operation - * needs to be done only once for each intrinsic key. - * Each time a Set Intrinsic Key operation is executed a new unique key is - * generated. - * - * param base PUF peripheral base address - * param keyIndex PUF key index register - * param keySize Size of the intrinsic key to generate in bytes. - * param[out] keyCode Word aligned address of the resulting key code. - * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * return Status of set intrinsic key operation. - */ -status_t PUF_SetIntrinsicKey( - PUF_Type *base, puf_key_index_register_t keyIndex, size_t keySize, uint8_t *keyCode, size_t keyCodeSize) -{ - status_t status = kStatus_Fail; - uint32_t *keyCodeAligned = NULL; - register uint32_t temp32 = 0; - - /* check if SET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSETKEY_MASK)) - { - return kStatus_Fail; - } - - /* only work with aligned keyCode */ - if (0U != (0x3u & (uintptr_t)keyCode)) - { - return kStatus_InvalidArgument; - } - - /* Check that keySize is in the correct range and that it is multiple of 8 */ - if ((keySize < (uint32_t)kPUF_KeySizeMin) || (keySize > (uint32_t)kPUF_KeySizeMax) || (0U != (keySize & 0x7U))) - { - return kStatus_InvalidArgument; - } - - /* check that keyCodeSize is correct for given keySize */ - if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize)) - { - return kStatus_InvalidArgument; - } - - if ((uint32_t)keyIndex > (uint32_t)kPUF_KeyIndexMax) - { - return kStatus_InvalidArgument; - } - - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - - /* program the key size and index */ - base->KEYSIZE = keySize >> 3; - base->KEYINDEX = (uint32_t)keyIndex; - - /* begin */ - base->CTRL = PUF_CTRL_GENERATEKEY_MASK; - - /* wait till command is accepted */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy read KC */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) - { - temp32 = base->CODEOUTPUT; - if (keyCodeSize >= sizeof(uint32_t)) - { - *keyCodeAligned = temp32; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - } - } - - /* get status */ - if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Set user key - * - * The digital fingerprint generated during the Enroll/Start - * operations and a user key (UK) provided as input are used to - * generate a Key Code (KC). This KC is sent returned to be stored - * in an NVM or a file. This operation needs to be done only once for each user key. - * - * param base PUF peripheral base address - * param keyIndex PUF key index register - * param userKey Word aligned address of input user key. - * param userKeySize Size of the input user key in bytes. - * param[out] keyCode Word aligned address of the resulting key code. - * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize). - * return Status of set user key operation. - */ -status_t PUF_SetUserKey(PUF_Type *base, - puf_key_index_register_t keyIndex, - const uint8_t *userKey, - size_t userKeySize, - uint8_t *keyCode, - size_t keyCodeSize) -{ - status_t status = kStatus_Fail; - uint32_t *keyCodeAligned = NULL; - const uint32_t *userKeyAligned = NULL; - register uint32_t temp32 = 0; - - /* check if SET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSETKEY_MASK)) - { - return kStatus_Fail; - } - - /* only work with aligned keyCode */ - if (0U != (0x3u & (uintptr_t)keyCode)) - { - return kStatus_InvalidArgument; - } - - /* Check that userKeySize is in the correct range and that it is multiple of 8 */ - if ((userKeySize < (uint32_t)kPUF_KeySizeMin) || (userKeySize > (uint32_t)kPUF_KeySizeMax) || - (0U != (userKeySize & 0x7U))) - { - return kStatus_InvalidArgument; - } - - /* check that keyCodeSize is correct for given userKeySize */ - if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize)) - { - return kStatus_InvalidArgument; - } - - if ((uint32_t)keyIndex > (uint32_t)kPUF_KeyIndexMax) - { - return kStatus_InvalidArgument; - } - - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - userKeyAligned = (const uint32_t *)(uintptr_t)userKey; - - /* program the key size and index */ - base->KEYSIZE = userKeySize >> 3; /* convert to 64-bit blocks */ - base->KEYINDEX = (uint32_t)keyIndex; - - /* We have to store the user key on index 0 swaped for HW bus */ - if (keyIndex == kPUF_KeyIndex_00) - { - userKeyAligned = userKeyAligned + (userKeySize / sizeof(uint32_t)); - } - - /* begin */ - base->CTRL = PUF_CTRL_SETKEY_MASK; - - /* wait till command is accepted */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy write UK and read KC */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_KEYINREQ_MASK & base->STAT)) - { - if (userKeySize >= sizeof(uint32_t)) - { -#if defined(LPC54S018_SERIES) - if (keyIndex == kPUF_KeyIndex_00) - { - userKeyAligned--; - temp32 = *userKeyAligned; - userKeySize -= sizeof(uint32_t); - } -#else - if (keyIndex == kPUF_KeyIndex_00) - { - userKeyAligned--; - temp32 = __REV(*userKeyAligned); - userKeySize--; - } -#endif /* defined(LPC54S018_SERIES) */ - else if (keyIndex != kPUF_KeyIndex_00) - { - temp32 = *userKeyAligned; - userKeyAligned++; - userKeySize -= sizeof(uint32_t); - } - else - { - /* Intentional empty */ - } - } - base->KEYINPUT = temp32; - } - - if (0U != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) - { - temp32 = base->CODEOUTPUT; - if (keyCodeSize >= sizeof(uint32_t)) - { - *keyCodeAligned = temp32; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - } - } - - /* get status */ - if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -static status_t puf_getHwKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize) -{ - status_t status = kStatus_Fail; - uint32_t *keyCodeAligned = NULL; - register uint32_t temp32 = 0; - - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - - /* begin */ - base->CTRL = PUF_CTRL_GETKEY_MASK; - - /* wait till command is accepted */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy send KC, key is reconstructed to HW bus */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_CODEINREQ_MASK & base->STAT)) - { - if (keyCodeSize >= sizeof(uint32_t)) - { - temp32 = *keyCodeAligned; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - base->CODEINPUT = temp32; - } - } - - /* get status */ - if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Reconstruct hw bus key from a key code - * - * The digital fingerprint generated during the Start operation and the KC - * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This - * operation needs to be done every time a key is needed. - * This function accepts only Key Codes created for PUF index register kPUF_KeyIndex_00. - * Such a key is output directly to a dedicated hardware bus. The reconstructed key is not exposed to system memory. - * - * param base PUF peripheral base address - * param keyCode Word aligned address of the input key code. - * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * param keySlot key slot to output on hw bus. Parameter is ignored on devices with less than two key slots. - * param keyMask key masking value. Shall be random for each POR/reset. Value does not have to be cryptographicaly - * secure. - * return Status of get key operation. - */ -status_t PUF_GetHwKey( - PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, puf_key_slot_t keySlot, uint32_t keyMask) -{ - status_t status = kStatus_Fail; - uint32_t keyIndex; - - /* check if GET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK)) - { - return kStatus_Fail; - } - - /* only work with aligned keyCode */ - if (0U != (0x3u & (uintptr_t)keyCode)) - { - return kStatus_Fail; - } - - /* check that keyCodeSize is at least PUF_MIN_KEY_CODE_SIZE */ - if (keyCodeSize < PUF_MIN_KEY_CODE_SIZE) - { - return kStatus_InvalidArgument; - } - - keyIndex = (uint32_t)(0x0Fu & (uint32_t)keyCode[1]); - - /* check the Key Code header byte 1. index must be zero for the hw key. */ - if (kPUF_KeyIndex_00 != (puf_key_index_register_t)keyIndex) - { - return kStatus_Fail; - } - -#if defined(PUF_KEYMASK_COUNT) && (PUF_KEYMASK_COUNT > 0) - volatile uint32_t *keyMask_reg = NULL; - uint32_t regVal = ((uint32_t)2U << ((uint32_t)2U * (uint32_t)keySlot)); - - switch (keySlot) - { - case kPUF_KeySlot0: - keyMask_reg = &base->KEYMASK[0]; - break; - - case kPUF_KeySlot1: - keyMask_reg = &base->KEYMASK[1]; - break; -#if (PUF_KEYMASK_COUNT > 2) - case kPUF_KeySlot2: - keyMask_reg = &base->KEYMASK[2]; - break; - - case kPUF_KeySlot3: - keyMask_reg = &base->KEYMASK[3]; - break; -#endif /* PUF_KEYMASK_COUNT > 2 */ - default: - status = kStatus_InvalidArgument; - break; - } -#endif /* PUF_KEYMASK_COUNT */ - - if (status != kStatus_InvalidArgument) - { -#if defined(PUF_KEYMASK_COUNT) && (PUF_KEYMASK_COUNT > 0) - base->KEYRESET = regVal; - base->KEYENABLE = regVal; - *keyMask_reg = keyMask; -#endif /* FSL_FEATURE_PUF_HAS_KEYSLOTS */ - - status = puf_getHwKey(base, keyCode, keyCodeSize); - -#if defined(FSL_FEATURE_PUF_HAS_SHIFT_STATUS) && (FSL_FEATURE_PUF_HAS_SHIFT_STATUS > 0) - size_t keyWords = 0; - - if (status == kStatus_Success) - { - /* if the corresponding shift count does not match, return fail anyway */ - keyWords = ((((size_t)keyCode[3]) * 2U) - 1u) << ((size_t)keySlot << 2U); - if (keyWords != ((0x0FUL << ((uint32_t)keySlot << 2U)) & base->SHIFT_STATUS)) - { - status = kStatus_Fail; - } - } -#elif defined(PUF_IDXBLK_SHIFT_IND_KEY0_MASK) && PUF_IDXBLK_SHIFT_IND_KEY0_MASK - size_t keyWords = 0; - - if (status == kStatus_Success) - { - /* if the corresponding shift count does not match, return fail anyway */ - keyWords = ((((size_t)keyCode[3]) * 2U) - 1u) << ((size_t)keySlot << 2U); - if (keyWords != ((0x0FUL << ((uint32_t)keySlot << 2U)) & base->IDXBLK_SHIFT)) - { - status = kStatus_Fail; - } - } -#endif /* FSL_FEATURE_PUF_HAS_SHIFT_STATUS || PUF_IDXBLK_SHIFT_IND_KEY0_MASK */ - } - - return status; -} - -/*! - * brief Checks if Get Key operation is allowed. - * - * This function returns true if get key operation is allowed. - * - * param base PUF peripheral base address - * return true if get key operation is allowed - */ -bool PUF_IsGetKeyAllowed(PUF_Type *base) -{ - /* check if GET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK)) - { - return false; - } - - return true; -} - -/*! - * brief Reconstruct key from a key code - * - * The digital fingerprint generated during the Start operation and the KC - * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This - * operation needs to be done every time a key is needed. - * This function accepts only Key Codes created for PUF index registers kPUF_KeyIndex_01 to kPUF_KeyIndex_15. - * - * param base PUF peripheral base address - * param keyCode Word aligned address of the input key code. - * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * param[out] key Word aligned address of output key. - * param keySize Size of the output key in bytes. - * return Status of get key operation. - */ -status_t PUF_GetKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize) -{ - status_t status = kStatus_Fail; - uint32_t *keyCodeAligned = NULL; - uint32_t *keyAligned = NULL; - uint32_t keyIndex; - register uint32_t temp32 = 0; - - /* check if GET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK)) - { - return kStatus_Fail; - } - - /* only work with aligned keyCode */ - if (0U != (0x3u & (uintptr_t)keyCode)) - { - return kStatus_Fail; - } - - /* only work with aligned key */ - if (0U != (0x3u & (uintptr_t)key)) - { - return kStatus_Fail; - } - - /* check that keyCodeSize is correct for given keySize */ - if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize)) - { - return kStatus_InvalidArgument; - } - - keyIndex = (0x0Fu & (uint32_t)keyCode[1]); - - /* check the Key Code header byte 1. index must be non-zero for the register key. */ - if (kPUF_KeyIndex_00 == (puf_key_index_register_t)keyIndex) - { - return kStatus_Fail; - } - - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - keyAligned = (uint32_t *)(uintptr_t)key; - - /* begin */ - base->CTRL = PUF_CTRL_GETKEY_MASK; - - /* wait till command is accepted */ - while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy send KC, read key */ - while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0U != (PUF_STAT_CODEINREQ_MASK & base->STAT)) - { - temp32 = 0; - if (keyCodeSize >= sizeof(uint32_t)) - { - temp32 = *keyCodeAligned; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - base->CODEINPUT = temp32; - } - - if (0U != (PUF_STAT_KEYOUTAVAIL_MASK & base->STAT)) - { - keyIndex = base->KEYOUTINDEX; - temp32 = base->KEYOUTPUT; - if (keySize >= sizeof(uint32_t)) - { - *keyAligned = temp32; - keyAligned++; - keySize -= sizeof(uint32_t); - } - } - } - - /* get status */ - if ((keyIndex != 0U) && (0U != (base->STAT & PUF_STAT_SUCCESS_MASK))) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Zeroize PUF - * - * This function clears all PUF internal logic and puts the PUF to error state. - * - * param base PUF peripheral base address - * return Status of the zeroize operation. - */ -status_t PUF_Zeroize(PUF_Type *base) -{ - status_t status = kStatus_Fail; - - /* zeroize command is always allowed */ - base->CTRL = PUF_CTRL_ZEROIZE_MASK; - - /* check that command is accepted */ - if ((0U != (base->STAT & PUF_STAT_ERROR_MASK)) && (0U == base->ALLOW)) - { - status = kStatus_Success; - } - - return status; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_puf.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_puf.h deleted file mode 100644 index b8a5c51c856..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_puf.h +++ /dev/null @@ -1,335 +0,0 @@ -/* - * Copyright 2018-2021 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PUF_H_ -#define _PUF_H_ - -#include -#include - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! - * @addtogroup puf_driver - * @{ - */ -/*! @name Driver version */ -/*@{*/ -/*! @brief PUF driver version. Version 2.1.6. - * - * Current version: 2.1.6 - * - * Change log: - * - 2.0.0 - * - Initial version. - * - 2.0.1 - * - Fixed puf_wait_usec function optimization issue. - * - 2.0.2 - * - Add PUF configuration structure and support for PUF SRAM controller. - * Remove magic constants. - * - 2.0.3 - * - Fix MISRA C-2012 issue. - * - 2.1.0 - * - Align driver with PUF SRAM controller registers on LPCXpresso55s16. - * - Update initizalition logic . - * - 2.1.1 - * - Fix ARMGCC build warning . - * - 2.1.2 - * - Update: Add automatic big to little endian swap for user - * (pre-shared) keys destinated to secret hardware bus (PUF key index 0). - * - 2.1.3 - * - Fix MISRA C-2012 issue. - * - 2.1.4 - * - Replace register uint32_t ticksCount with volatile uint32_t ticksCount in puf_wait_usec() to prevent optimization - * out delay loop. - * - 2.1.5 - * - Use common SDK delay in puf_wait_usec() - * - 2.1.6 - * - Changed wait time in PUF_Init(), when initialization fails it will try PUF_Powercycle() with shorter time. If - * this shorter time will also fail, initialization will be tried with worst case time as before. - */ -#define FSL_PUF_DRIVER_VERSION (MAKE_VERSION(2, 1, 6)) -/*@}*/ - -typedef enum _puf_key_index_register -{ - kPUF_KeyIndex_00 = 0x00U, - kPUF_KeyIndex_01 = 0x01U, - kPUF_KeyIndex_02 = 0x02U, - kPUF_KeyIndex_03 = 0x03U, - kPUF_KeyIndex_04 = 0x04U, - kPUF_KeyIndex_05 = 0x05U, - kPUF_KeyIndex_06 = 0x06U, - kPUF_KeyIndex_07 = 0x07U, - kPUF_KeyIndex_08 = 0x08U, - kPUF_KeyIndex_09 = 0x09U, - kPUF_KeyIndex_10 = 0x0AU, - kPUF_KeyIndex_11 = 0x0BU, - kPUF_KeyIndex_12 = 0x0CU, - kPUF_KeyIndex_13 = 0x0DU, - kPUF_KeyIndex_14 = 0x0EU, - kPUF_KeyIndex_15 = 0x0FU, -} puf_key_index_register_t; - -typedef enum _puf_min_max -{ - kPUF_KeySizeMin = 8u, - kPUF_KeySizeMax = 512u, - kPUF_KeyIndexMax = kPUF_KeyIndex_15, -} puf_min_max_t; - -/*! @brief PUF key slot. */ -typedef enum _puf_key_slot -{ - kPUF_KeySlot0 = 0U, /*!< PUF key slot 0 */ - kPUF_KeySlot1 = 1U, /*!< PUF key slot 1 */ -#if defined(PUF_KEYMASK_COUNT) && (PUF_KEYMASK_COUNT > 2) - kPUF_KeySlot2 = 2U, /*!< PUF key slot 2 */ - kPUF_KeySlot3 = 3U, /*!< PUF key slot 3 */ -#endif -} puf_key_slot_t; - -typedef struct -{ - uint32_t dischargeTimeMsec; - uint32_t coreClockFrequencyHz; -#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) - /* LPCXpresso55s16 */ - PUF_SRAM_CTRL_Type *puf_sram_base; - uint8_t CKGATING; -#endif /* FSL_FEATURE_PUF_HAS_SRAM_CTRL */ -} puf_config_t; -/*! @brief Get Key Code size in bytes from key size in bytes at compile time. */ -#define PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(x) ((160u + (((((x) << 3) + 255u) >> 8) << 8)) >> 3) -#define PUF_MIN_KEY_CODE_SIZE PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(8UL) -#define PUF_ACTIVATION_CODE_SIZE 1192U -#define KEYSTORE_PUF_DISCHARGE_TIME_FIRST_TRY_MS 50 -#define KEYSTORE_PUF_DISCHARGE_TIME_MAX_MS 400 - -/*! PUF status return codes. */ -enum -{ - kStatus_EnrollNotAllowed = MAKE_STATUS(kStatusGroup_PUF, 1), - kStatus_StartNotAllowed = MAKE_STATUS(kStatusGroup_PUF, 2) -}; - -/*! @} */ -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @brief Sets the default configuration of PUF - * - * This function initialize PUF config structure to default values. - * - * @param conf PUF configuration structure - */ -void PUF_GetDefaultConfig(puf_config_t *conf); - -/*! - * @brief Initialize PUF - * - * This function enables power to PUF block and waits until the block initializes. - * - * @param base PUF peripheral base address - * @param conf PUF configuration structure - * @return Status of the init operation - */ -status_t PUF_Init(PUF_Type *base, puf_config_t *conf); - -/*! - * @brief Denitialize PUF - * - * This function disables power to PUF SRAM and peripheral clock. - * - * @param base PUF peripheral base address - * @param conf PUF configuration structure - */ -void PUF_Deinit(PUF_Type *base, puf_config_t *conf); - -/*! - * @brief Enroll PUF - * - * This function derives a digital fingerprint, generates the corresponding Activation Code (AC) - * and returns it to be stored in an NVM or a file. This step needs to be - * performed only once for each device. This function may be permanently disallowed by a fuse. - * - * @param base PUF peripheral base address - * @param[out] activationCode Word aligned address of the resulting activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. - * @return Status of enroll operation. - */ -status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize); - -/*! - * @brief Start PUF - * - * The Activation Code generated during the Enroll operation is used to - * reconstruct the digital fingerprint. This needs to be done after every power-up - * and reset. - * - * @param base PUF peripheral base address - * @param activationCode Word aligned address of the input activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. - * @return Status of start operation. - */ -status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize); - -/*! - * @brief Set intrinsic key - * - * The digital fingerprint generated during the Enroll/Start - * operations is used to generate a Key Code (KC) that defines a unique intrinsic - * key. This KC is returned to be stored in an NVM or a file. This operation - * needs to be done only once for each intrinsic key. - * Each time a Set Intrinsic Key operation is executed a new unique key is - * generated. - * - * @param base PUF peripheral base address - * @param keyIndex PUF key index register - * @param keySize Size of the intrinsic key to generate in bytes. - * @param[out] keyCode Word aligned address of the resulting key code. - * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * @return Status of set intrinsic key operation. - */ -status_t PUF_SetIntrinsicKey( - PUF_Type *base, puf_key_index_register_t keyIndex, size_t keySize, uint8_t *keyCode, size_t keyCodeSize); - -/*! - * @brief Set user key - * - * The digital fingerprint generated during the Enroll/Start - * operations and a user key (UK) provided as input are used to - * generate a Key Code (KC). This KC is sent returned to be stored - * in an NVM or a file. This operation needs to be done only once for each user key. - * - * @param base PUF peripheral base address - * @param keyIndex PUF key index register - * @param userKey Word aligned address of input user key. - * @param userKeySize Size of the input user key in bytes. - * @param[out] keyCode Word aligned address of the resulting key code. - * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize). - * @return Status of set user key operation. - */ -status_t PUF_SetUserKey(PUF_Type *base, - puf_key_index_register_t keyIndex, - const uint8_t *userKey, - size_t userKeySize, - uint8_t *keyCode, - size_t keyCodeSize); - -/*! - * @brief Reconstruct key from a key code - * - * The digital fingerprint generated during the Start operation and the KC - * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This - * operation needs to be done every time a key is needed. - * This function accepts only Key Codes created for PUF index registers kPUF_KeyIndex_01 to kPUF_KeyIndex_15. - * - * @param base PUF peripheral base address - * @param keyCode Word aligned address of the input key code. - * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * @param[out] key Word aligned address of output key. - * @param keySize Size of the output key in bytes. - * @return Status of get key operation. - */ -status_t PUF_GetKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize); - -/*! - * @brief Reconstruct hw bus key from a key code - * - * The digital fingerprint generated during the Start operation and the KC - * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This - * operation needs to be done every time a key is needed. - * This function accepts only Key Codes created for PUF index register kPUF_KeyIndex_00. - * Such a key is output directly to a dedicated hardware bus. The reconstructed key is not exposed to system memory. - * - * @param base PUF peripheral base address - * @param keyCode Word aligned address of the input key code. - * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * @param keySlot key slot to output on hw bus. Parameter is ignored on devices with less than two key slots. - * @param keyMask key masking value. Shall be random for each POR/reset. Value does not have to be cryptographicaly - * secure. - * @return Status of get key operation. - */ -status_t PUF_GetHwKey( - PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, puf_key_slot_t keySlot, uint32_t keyMask); - -/*! - * @brief Zeroize PUF - * - * This function clears all PUF internal logic and puts the PUF to error state. - * - * @param base PUF peripheral base address - * @return Status of the zeroize operation. - */ -status_t PUF_Zeroize(PUF_Type *base); - -/*! - * @brief Checks if Get Key operation is allowed. - * - * This function returns true if get key operation is allowed. - * - * @param base PUF peripheral base address - * @return true if get key operation is allowed - */ -bool PUF_IsGetKeyAllowed(PUF_Type *base); - -#if defined(PUF_CFG_BLOCKKEYOUTPUT_MASK) && PUF_CFG_BLOCKKEYOUTPUT_MASK -static inline void PUF_BlockSetKey(PUF_Type *base) -{ - base->CFG |= PUF_CFG_BLOCKKEYOUTPUT_MASK; /* block set key */ -} -#endif /* PUF_CFG_BLOCKKEYOUTPUT_MASK */ - -#if defined(PUF_CFG_PUF_BLOCK_SET_KEY_MASK) && PUF_CFG_PUF_BLOCK_SET_KEY_MASK -static inline void PUF_BlockSetKey(PUF_Type *base) -{ - base->CFG |= PUF_CFG_PUF_BLOCK_SET_KEY_MASK; /* block set key */ -} -#endif /* PUF_CFG_PUF_BLOCK_SET_KEY_MASK */ - -#if defined(PUF_CFG_BLOCKENROLL_SETKEY_MASK) && PUF_CFG_BLOCKENROLL_SETKEY_MASK -static inline void PUF_BlockEnroll(PUF_Type *base) -{ - base->CFG |= PUF_CFG_BLOCKENROLL_SETKEY_MASK; /* block enroll */ -} -#endif /* PUF_CFG_BLOCKENROLL_SETKEY_MASK */ - -#if defined(PUF_CFG_PUF_BLOCK_ENROLL_MASK) && PUF_CFG_PUF_BLOCK_ENROLL_MASK -static inline void PUF_BlockEnroll(PUF_Type *base) -{ - base->CFG |= PUF_CFG_PUF_BLOCK_ENROLL_MASK; /* block enroll */ -} -#endif /* PUF_CFG_PUF_BLOCK_ENROLL_MASK */ - -/*! - * @brief Powercycle PUF - * - * This function make powercycle. - * - * @param base PUF peripheral base address - * @param conf PUF configuration structure - * @return Status of the powercycle operation. - */ -status_t PUF_PowerCycle(PUF_Type *base, puf_config_t *conf); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -#endif /* _PUF_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_reset.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_reset.c deleted file mode 100644 index 4326e0dae24..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_reset.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#include "fsl_reset.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.reset" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - -/*! - * brief Assert reset to peripheral. - * - * Asserts reset signal to specified peripheral module. - * - * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_SetPeripheralReset(reset_ip_name_t peripheral) -{ - const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; - const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); - const uint32_t bitMask = 1UL << bitPos; - - assert(bitPos < 32u); - - /* reset register is in SYSCON */ - /* set bit */ - SYSCON->PRESETCTRLSET[regIndex] = bitMask; - /* wait until it reads 0b1 */ - while (0u == (SYSCON->PRESETCTRLX[regIndex] & bitMask)) - { - } -} - -/*! - * brief Clear reset to peripheral. - * - * Clears reset signal to specified peripheral module, allows it to operate. - * - * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) -{ - const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; - const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); - const uint32_t bitMask = 1UL << bitPos; - - assert(bitPos < 32u); - - /* reset register is in SYSCON */ - - /* clear bit */ - SYSCON->PRESETCTRLCLR[regIndex] = bitMask; - /* wait until it reads 0b0 */ - while (bitMask == (SYSCON->PRESETCTRLX[regIndex] & bitMask)) - { - } -} - -/*! - * brief Reset peripheral module. - * - * Reset peripheral module. - * - * param peripheral Peripheral to reset. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_PeripheralReset(reset_ip_name_t peripheral) -{ - RESET_SetPeripheralReset(peripheral); - RESET_ClearPeripheralReset(peripheral); -} - -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_reset.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_reset.h deleted file mode 100644 index 314f6c66a37..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_reset.h +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_RESET_H_ -#define _FSL_RESET_H_ - -#include -#include -#include -#include -#include "fsl_device_registers.h" - -/*! - * @addtogroup reset - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief reset driver version 2.0.3. */ -#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ - -/*! - * @brief Enumeration for peripheral reset control bits - * - * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers - */ -typedef enum _SYSCON_RSTn -{ - kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */ - kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */ - kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */ - kSRAM3_RST_SHIFT_RSTn = 0 | 5U, /**< SRAM3 reset control */ - kSRAM4_RST_SHIFT_RSTn = 0 | 6U, /**< SRAM4 reset control */ - kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ - kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ - kSPIFI_RST_SHIFT_RSTn = 0 | 10U, /**< SPIFI reset control */ - kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */ - kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ - kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ - kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ - kGPIO2_RST_SHIFT_RSTn = 0 | 16U, /**< GPIO2 reset control */ - kGPIO3_RST_SHIFT_RSTn = 0 | 17U, /**< GPIO3 reset control */ - kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ - kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ - kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ - kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ - kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ - kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */ - kMAILBOX_RST_SHIFT_RSTn = 0 | 26U, /**< Mailbox reset control */ - kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ - - kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ - kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */ - kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ - kSCTIPU_RST_SHIFT_RSTn = 65536 | 6U, /**< SCTIPU reset control */ - kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ - kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ - kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ - kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ - kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ - kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ - kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ - kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ - kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ - kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */ - kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0 Device reset control */ - kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */ - kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */ - kPVT_RST_SHIFT_RSTn = 65536 | 28U, /**< PVT reset control */ - kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */ - kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */ - - kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */ - kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */ - kSDIO_RST_SHIFT_RSTn = 131072 | 3U, /**< SDIO reset control */ - kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USBHS Host reset control */ - kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USBHS Device reset control */ - kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB RAM reset control */ - kUSB1_RST_SHIFT_RSTn = 131072 | 7U, /**< USBHS reset control */ - kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */ - kGPIO4_RST_SHIFT_RSTn = 131072 | 9U, /**< GPIO4 reset control */ - kGPIO5_RST_SHIFT_RSTn = 131072 | 10U, /**< GPIO5 reset control */ - kAES_RST_SHIFT_RSTn = 131072 | 11U, /**< AES reset control */ - kOTP_RST_SHIFT_RSTn = 131072 | 12U, /**< OTP reset control */ - kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */ - kMUX1_RST_SHIFT_RSTn = 131072 | 14U, /**< Input mux1 reset control */ - kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */ - kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */ - kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */ - kPOWERQUAD_RST_SHIFT_RSTn = 131072 | 19U, /**< PowerQuad reset control */ - kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */ - kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */ - kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */ - kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */ - kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */ - kCAP0_RST_SHIFT_RSTn = 131072 | 25U, /**< CASPER reset control */ - kOSTIMER1_RST_SHIFT_RSTn = 131072 | 26U, /**< OSTIMER1 reset control */ - kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */ - kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */ - kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */ - kGPIOSECINT_RST_SHIFT_RSTn = 131072 | 30U, /**< GPIO Secure int reset control */ -} SYSCON_RSTn_t; - -/** Array initializers with peripheral reset bits **/ -#define ADC_RSTS \ - { \ - kADC0_RST_SHIFT_RSTn \ - } /* Reset bits for ADC peripheral */ -#define AES_RSTS \ - { \ - kAES_RST_SHIFT_RSTn \ - } /* Reset bits for AES peripheral */ -#define CRC_RSTS \ - { \ - kCRC_RST_SHIFT_RSTn \ - } /* Reset bits for CRC peripheral */ -#define CTIMER_RSTS \ - { \ - kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \ - kCTIMER4_RST_SHIFT_RSTn \ - } /* Reset bits for CTIMER peripheral */ -#define DMA_RSTS_N \ - { \ - kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \ - } /* Reset bits for DMA peripheral */ - -#define FLEXCOMM_RSTS \ - { \ - kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ - kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kHSLSPI_RST_SHIFT_RSTn \ - } /* Reset bits for FLEXCOMM peripheral */ -#define GINT_RSTS \ - { \ - kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ - } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ -#define GPIO_RSTS_N \ - { \ - kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \ - kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn \ - } /* Reset bits for GPIO peripheral */ -#define INPUTMUX_RSTS \ - { \ - kMUX0_RST_SHIFT_RSTn, kMUX1_RST_SHIFT_RSTn \ - } /* Reset bits for INPUTMUX peripheral */ -#define IOCON_RSTS \ - { \ - kIOCON_RST_SHIFT_RSTn \ - } /* Reset bits for IOCON peripheral */ -#define FLASH_RSTS \ - { \ - kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ - } /* Reset bits for Flash peripheral */ -#define MRT_RSTS \ - { \ - kMRT_RST_SHIFT_RSTn \ - } /* Reset bits for MRT peripheral */ -#define OTP_RSTS \ - { \ - kOTP_RST_SHIFT_RSTn \ - } /* Reset bits for OTP peripheral */ -#define PINT_RSTS \ - { \ - kPINT_RST_SHIFT_RSTn \ - } /* Reset bits for PINT peripheral */ -#define RNG_RSTS \ - { \ - kRNG_RST_SHIFT_RSTn \ - } /* Reset bits for RNG peripheral */ -#define SDIO_RST \ - { \ - kSDIO_RST_SHIFT_RSTn \ - } /* Reset bits for SDIO peripheral */ -#define SCT_RSTS \ - { \ - kSCT0_RST_SHIFT_RSTn \ - } /* Reset bits for SCT peripheral */ -#define SPIFI_RSTS \ - { \ - kSPIFI_RST_SHIFT_RSTn \ - } /* Reset bits for SPIFI peripheral */ -#define USB0D_RST \ - { \ - kUSB0D_RST_SHIFT_RSTn \ - } /* Reset bits for USB0D peripheral */ -#define USB0HMR_RST \ - { \ - kUSB0HMR_RST_SHIFT_RSTn \ - } /* Reset bits for USB0HMR peripheral */ -#define USB0HSL_RST \ - { \ - kUSB0HSL_RST_SHIFT_RSTn \ - } /* Reset bits for USB0HSL peripheral */ -#define USB1H_RST \ - { \ - kUSB1H_RST_SHIFT_RSTn \ - } /* Reset bits for USB1H peripheral */ -#define USB1D_RST \ - { \ - kUSB1D_RST_SHIFT_RSTn \ - } /* Reset bits for USB1D peripheral */ -#define USB1RAM_RST \ - { \ - kUSB1RAM_RST_SHIFT_RSTn \ - } /* Reset bits for USB1RAM peripheral */ -#define UTICK_RSTS \ - { \ - kUTICK_RST_SHIFT_RSTn \ - } /* Reset bits for UTICK peripheral */ -#define WWDT_RSTS \ - { \ - kWWDT_RST_SHIFT_RSTn \ - } /* Reset bits for WWDT peripheral */ -#define CAPT_RSTS_N \ - { \ - kCAP0_RST_SHIFT_RSTn \ - } /* Reset bits for CAPT peripheral */ -#define PLU_RSTS_N \ - { \ - kPLULUT_RST_SHIFT_RSTn \ - } /* Reset bits for PLU peripheral */ -#define OSTIMER_RSTS \ - { \ - kOSTIMER0_RST_SHIFT_RSTn \ - } /* Reset bits for OSTIMER peripheral */ -#define POWERQUAD_RSTS \ - { \ - kPOWERQUAD_RST_SHIFT_RSTn \ - } /* Reset bits for Powerquad peripheral */ -#define CASPER_RSTS \ - { \ - kCASPER_RST_SHIFT_RSTn \ - } /* Reset bits for Casper peripheral */ -#define HASHCRYPT_RSTS \ - { \ - kHASHCRYPT_RST_SHIFT_RSTn \ - } /* Reset bits for Hashcrypt peripheral */ -#define PUF_RSTS \ - { \ - kPUF_RST_SHIFT_RSTn \ - } /* Reset bits for PUF peripheral */ -typedef SYSCON_RSTn_t reset_ip_name_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Assert reset to peripheral. - * - * Asserts reset signal to specified peripheral module. - * - * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_SetPeripheralReset(reset_ip_name_t peripheral); - -/*! - * @brief Clear reset to peripheral. - * - * Clears reset signal to specified peripheral module, allows it to operate. - * - * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); - -/*! - * @brief Reset peripheral module. - * - * Reset peripheral module. - * - * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_PeripheralReset(reset_ip_name_t peripheral); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_RESET_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rng.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rng.c deleted file mode 100644 index 1b2e9d4d61e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rng.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright 2017, 2019, 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_rng.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.rng_1" -#endif - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/******************************************************************************* - * Prototypes - *******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -static void rng_accumulateEntropy(RNG_Type *base) -{ - uint32_t minChiSq; - uint32_t maxChiSq; - - /* Steps to accumulate entropy, more info can be found in LPC55SXX UM*/ - - /* Select fourth clock on which to compute CHI SQUARE statistics*/ - base->COUNTER_CFG = (base->COUNTER_CFG & ~RNG_COUNTER_CFG_CLOCK_SEL_MASK) | RNG_COUNTER_CFG_CLOCK_SEL(4U); - - /* Activate CHI computing */ - base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(1U); - - /* Read min chi squared value, on power on should be higher than max chi squared value */ - minChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT); - - /* Read max chi squared value */ - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - - /* Wait until minChiSq decreases and become smaller than maxChiSq*/ - while (minChiSq > (maxChiSq - 1U)) - { - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - minChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT); - } -} - -/*! - * @brief Gets a entry data from the RNG. - * - * This function gets an entropy data from RNG. - */ -static uint32_t rng_readEntropy(RNG_Type *base) -{ - uint32_t data; - uint32_t refreshCnt, maxChiSq, tmpShift4x; - - /* Activate CHI computing */ - base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(1); - - /* Wait for refresh count become 31 to refill fresh entropy since last read of random number*/ - do - { - refreshCnt = ((base->COUNTER_VAL & RNG_COUNTER_VAL_REFRESH_CNT_MASK) >> RNG_COUNTER_VAL_REFRESH_CNT_SHIFT); - } while (refreshCnt < 31U); - - /* reading RANDOM_NUMBER register will reset refCnt to 0 */ - data = base->RANDOM_NUMBER; - - /* Perform CHI computing by checking max chi squared value */ - /* Wait until maxChiSq become smaller or equal than 4, then next random number can be read*/ - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - - while (maxChiSq > 4U) - { - /* Deactivate CHI computing to reset*/ - base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(0); - - /* read Shift4x register, if is less than 7 increment it and then start accumulating entropy again */ - tmpShift4x = ((base->COUNTER_CFG & RNG_COUNTER_CFG_SHIFT4X_MASK) >> RNG_COUNTER_CFG_SHIFT4X_SHIFT); - if (tmpShift4x < 7U) - { - tmpShift4x++; - base->COUNTER_CFG = - (base->COUNTER_CFG & ~RNG_COUNTER_CFG_SHIFT4X_MASK) | RNG_COUNTER_CFG_SHIFT4X(tmpShift4x); - } - rng_accumulateEntropy(base); - - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - } - - return data; -} - -void RNG_Init(RNG_Type *base) -{ - uint32_t maxChiSq, tmpShift4x; - - /* Clear ring oscilator disable bit*/ - PMC->PDRUNCFGCLR0 = PMC_PDRUNCFG0_PDEN_RNG_MASK; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Rng); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kRNG_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - - /* Turn on CHI Squared test */ - /* Activate CHI computing and wait until min chi squared become smaller than max chi squared */ - rng_accumulateEntropy(base); - - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - - /* When maxChiSq is bigger than 4 its assumed there is not enough entropy and previous steps are repeated */ - /* When maxChiSq is 4 or less initialization is complete and random number can be read*/ - while (maxChiSq > 4U) - { - /* Deactivate CHI coputing to reset*/ - base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(0); - - /* read Shift4x register, if is less than 7 increment it and then start accumulating entropy again */ - tmpShift4x = ((base->COUNTER_CFG & RNG_COUNTER_CFG_SHIFT4X_MASK) >> RNG_COUNTER_CFG_SHIFT4X_SHIFT); - if (tmpShift4x < 7U) - { - tmpShift4x++; - base->COUNTER_CFG = - (base->COUNTER_CFG & ~RNG_COUNTER_CFG_SHIFT4X_MASK) | RNG_COUNTER_CFG_SHIFT4X(tmpShift4x); - } - rng_accumulateEntropy(base); - - maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> - RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); - } -} - -void RNG_Deinit(RNG_Type *base) -{ - /* Set ring oscilator disable bit*/ - PMC->PDRUNCFGSET0 = PMC_PDRUNCFG0_PDEN_RNG_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kRNG_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Rng); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -status_t RNG_GetRandomData(RNG_Type *base, void *data, size_t dataSize) -{ - status_t result = kStatus_Fail; - uint32_t random32; - uint32_t randomSize; - uint8_t *pRandom; - uint8_t *pData = (uint8_t *)data; - uint32_t i; - - /* Check input parameters.*/ - if (!((base != NULL) && (data != NULL) && (dataSize != 0U))) - { - result = kStatus_InvalidArgument; - } - else - { - /* Check that ring oscilator is enabled */ - if (0U == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_RNG_MASK)) - { - do - { - /* Read Entropy.*/ - random32 = rng_readEntropy(base); - pRandom = (uint8_t *)&random32; - - if (dataSize < sizeof(random32)) - { - randomSize = dataSize; - } - else - { - randomSize = sizeof(random32); - } - - for (i = 0; i < randomSize; i++) - { - *pData++ = *pRandom++; - } - - dataSize -= randomSize; - } while (dataSize > 0U); - - result = kStatus_Success; - } - } - - return result; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rng.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rng.h deleted file mode 100644 index 38279cad7fa..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rng.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2017, 2019, 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_RNG_DRIVER_H_ -#define _FSL_RNG_DRIVER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup rng - * @{ - */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief RNG driver version. Version 2.0.3. - * - * Current version: 2.0.3 - * - * Change log: - * - Version 2.0.0 - * - Initial version - * - * - Version 2.0.1 - * - Fix MISRA C-2012 issue. - * - * - Version 2.0.2 - * - Add RESET_PeripheralReset function inside RNG_Init and RNG_Deinit functions. - * - * - Version 2.0.3 - * - Modified RNG_Init and RNG_GetRandomData functions, added rng_accumulateEntropy and rng_readEntropy functions. - * - These changes are reflecting recommended usage of RNG according to device UM. - */ -#define FSL_RNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initializes the RNG. - * - * This function initializes the RNG. - * When called, the RNG module and ring oscillator is enabled. - * - * @param base RNG base address - * @return If successful, returns the kStatus_RNG_Success. Otherwise, it returns an error. - */ -void RNG_Init(RNG_Type *base); - -/*! - * @brief Shuts down the RNG. - * - * This function shuts down the RNG. - * - * @param base RNG base address. - */ -void RNG_Deinit(RNG_Type *base); - -/*! - * @brief Gets random data. - * - * This function gets random data from the RNG. - * - * @param base RNG base address. - * @param data Pointer address used to store random data. - * @param dataSize Size of the buffer pointed by the data parameter. - * @return random data - */ -status_t RNG_GetRandomData(RNG_Type *base, void *data, size_t dataSize); - -/*! - * @brief Returns random 32-bit number. - * - * This function gets random number from the RNG. - * - * @param base RNG base address. - * @return random number - */ -static inline uint32_t RNG_GetRandomWord(RNG_Type *base) -{ - return base->RANDOM_NUMBER; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /*_FSL_RNG_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rtc.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rtc.c deleted file mode 100644 index b39370b6830..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rtc.c +++ /dev/null @@ -1,322 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_rtc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_rtc" -#endif - -#define SECONDS_IN_A_DAY (86400U) -#define SECONDS_IN_A_HOUR (3600U) -#define SECONDS_IN_A_MINUTE (60U) -#define DAYS_IN_A_YEAR (365U) -#define YEAR_RANGE_START (1970U) -#define YEAR_RANGE_END (2099U) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Check whether the date and time passed in is valid - * - * @param datetime Pointer to structure where the date and time details are stored - * - * @return Returns false if the date & time details are out of range; true if in range - */ -static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime); - -/*! - * @brief Convert time data from datetime to seconds - * - * @param datetime Pointer to datetime structure where the date and time details are stored - * - * @return The result of the conversion in seconds - */ -static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime); - -/*! - * @brief Convert time data from seconds to a datetime structure - * - * @param seconds Seconds value that needs to be converted to datetime format - * @param datetime Pointer to the datetime structure where the result of the conversion is stored - */ -static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime); - -/******************************************************************************* - * Code - ******************************************************************************/ -static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Check year, month, hour, minute, seconds */ - if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || - (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) - { - /* If not correct then error*/ - return false; - } - - /* Adjust the days in February for a leap year */ - if ((((datetime->year & 3U) == 0U) && (datetime->year % 100U != 0U)) || (datetime->year % 400U == 0U)) - { - daysPerMonth[2] = 29U; - } - - /* Check the validity of the day */ - if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) - { - return false; - } - - return true; -} - -static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Number of days from begin of the non Leap-year*/ - /* Number of days from begin of the non Leap-year*/ - uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; - uint32_t seconds; - - /* Compute number of days from 1970 till given year*/ - seconds = ((uint32_t)datetime->year - 1970U) * DAYS_IN_A_YEAR; - /* Add leap year days */ - seconds += (((uint32_t)datetime->year / 4U) - (1970U / 4U)); - /* Add number of days till given month*/ - seconds += monthDays[datetime->month]; - /* Add days in given month. We subtract the current day as it is - * represented in the hours, minutes and seconds field*/ - seconds += ((uint32_t)datetime->day - 1U); - /* For leap year if month less than or equal to Febraury, decrement day counter*/ - if (((datetime->year & 3U) == 0x00U) && (datetime->month <= 2U)) - { - seconds--; - } - - seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + - (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; - - return seconds; -} - -static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint8_t i; - uint16_t daysInYear; - uint32_t secondsRemaining; - uint32_t days; - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Start with the seconds value that is passed in to be converted to date time format */ - secondsRemaining = seconds; - - /* Calcuate the number of days, we add 1 for the current day which is represented in the - * hours and seconds field - */ - days = secondsRemaining / SECONDS_IN_A_DAY + 1U; - - /* Update seconds left*/ - secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; - - /* Calculate the datetime hour, minute and second fields */ - datetime->hour = (uint8_t)(secondsRemaining / SECONDS_IN_A_HOUR); - secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; - datetime->minute = (uint8_t)(secondsRemaining / 60U); - datetime->second = (uint8_t)(secondsRemaining % SECONDS_IN_A_MINUTE); - - /* Calculate year */ - daysInYear = DAYS_IN_A_YEAR; - datetime->year = YEAR_RANGE_START; - while (days > daysInYear) - { - /* Decrease day count by a year and increment year by 1 */ - days -= daysInYear; - datetime->year++; - - /* Adjust the number of days for a leap year */ - if ((datetime->year & 3U) != 0x00U) - { - daysInYear = DAYS_IN_A_YEAR; - } - else - { - daysInYear = DAYS_IN_A_YEAR + 1U; - } - } - - /* Adjust the days in February for a leap year */ - if ((datetime->year & 3U) == 0x00U) - { - daysPerMonth[2] = 29U; - } - - for (i = 1U; i <= 12U; i++) - { - if (days <= daysPerMonth[i]) - { - datetime->month = i; - break; - } - else - { - days -= daysPerMonth[i]; - } - } - - datetime->day = (uint8_t)days; -} - -/*! - * brief Ungate the RTC clock and enables the RTC oscillator. - * - * note This API should be called at the beginning of the application using the RTC driver. - * - * param base RTC peripheral base address - */ -void RTC_Init(RTC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the RTC peripheral clock */ - CLOCK_EnableClock(kCLOCK_Rtc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_RTC_HAS_NO_RESET) && FSL_FEATURE_RTC_HAS_NO_RESET) - RESET_PeripheralReset(kRTC_RST_SHIFT_RSTn); -#endif - /* Make sure the reset bit is cleared */ - base->CTRL &= ~RTC_CTRL_SWRESET_MASK; - -#if !(defined(FSL_FEATURE_RTC_HAS_NO_OSC_PD) && FSL_FEATURE_RTC_HAS_NO_OSC_PD) - /* Make sure the RTC OSC is powered up */ - base->CTRL &= ~RTC_CTRL_RTC_OSC_PD_MASK; -#endif -} - -/*! - * brief Set the RTC date and time according to the given time structure. - * - * The RTC counter must be stopped prior to calling this function as writes to the RTC - * seconds register will fail if the RTC counter is running. - * - * param base RTC peripheral base address - * param datetime Pointer to structure where the date and time details to set are stored - * - * return kStatus_Success: Success in setting the time and starting the RTC - * kStatus_InvalidArgument: Error because the datetime format is incorrect - */ -status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Return error if the time provided is not valid */ - if (!(RTC_CheckDatetimeFormat(datetime))) - { - return kStatus_InvalidArgument; - } - - /* Set time in seconds */ - base->COUNT = RTC_ConvertDatetimeToSeconds(datetime); - - return kStatus_Success; -} - -/*! - * brief Gets the RTC time and stores it in the given time structure. - * - * param base RTC peripheral base address - * param datetime Pointer to structure where the date and time details are stored. - */ -void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t seconds = 0; - - seconds = RTC_GetSecondsTimerCount(base); - RTC_ConvertSecondsToDatetime(seconds, datetime); -} - -/*! - * brief Set the RTC alarm time - * - * The function checks whether the specified alarm time is greater than the present - * time. If not, the function does not set the alarm and returns an error. - * - * param base RTC peripheral base address - * param alarmTime Pointer to structure where the alarm time is stored. - * - * return kStatus_Success: success in setting the RTC alarm - * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect - * kStatus_Fail: Error because the alarm time has already passed - */ -status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) -{ - assert(alarmTime != NULL); - - uint32_t alarmSeconds = 0; - uint32_t currSeconds = 0; - - /* Return error if the alarm time provided is not valid */ - if (!(RTC_CheckDatetimeFormat(alarmTime))) - { - return kStatus_InvalidArgument; - } - - alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime); - - /* Get the current time */ - currSeconds = RTC_GetSecondsTimerCount(base); - - /* Return error if the alarm time has passed */ - if (alarmSeconds < currSeconds) - { - return kStatus_Fail; - } - - /* Set alarm in seconds*/ - base->MATCH = alarmSeconds; - - return kStatus_Success; -} - -/*! - * brief Return the RTC alarm time. - * - * param base RTC peripheral base address - * param datetime Pointer to structure where the alarm date and time details are stored. - */ -void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t alarmSeconds = 0; - - /* Get alarm in seconds */ - alarmSeconds = base->MATCH; - - RTC_ConvertSecondsToDatetime(alarmSeconds, datetime); -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rtc.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rtc.h deleted file mode 100644 index a960d8baf7c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rtc.h +++ /dev/null @@ -1,493 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_RTC_H_ -#define _FSL_RTC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup rtc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*!< Version 2.1.2 */ -/*@}*/ - -/*! @brief List of RTC interrupts */ -typedef enum _rtc_interrupt_enable -{ - kRTC_AlarmInterruptEnable = RTC_CTRL_ALARMDPD_EN_MASK, /*!< Alarm interrupt.*/ - kRTC_WakeupInterruptEnable = RTC_CTRL_WAKEDPD_EN_MASK /*!< Wake-up interrupt.*/ -} rtc_interrupt_enable_t; - -/*! @brief List of RTC flags */ -typedef enum _rtc_status_flags -{ - kRTC_AlarmFlag = RTC_CTRL_ALARM1HZ_MASK, /*!< Alarm flag*/ - kRTC_WakeupFlag = RTC_CTRL_WAKE1KHZ_MASK /*!< 1kHz wake-up timer flag*/ -} rtc_status_flags_t; - -/*! @brief Structure is used to hold the date and time */ -typedef struct _rtc_datetime -{ - uint16_t year; /*!< Range from 1970 to 2099.*/ - uint8_t month; /*!< Range from 1 to 12.*/ - uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ - uint8_t hour; /*!< Range from 0 to 23.*/ - uint8_t minute; /*!< Range from 0 to 59.*/ - uint8_t second; /*!< Range from 0 to 59.*/ -} rtc_datetime_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Un-gate the RTC clock and enable the RTC oscillator. - * - * @note This API should be called at the beginning of the application using the RTC driver. - * - * @param base RTC peripheral base address - */ -void RTC_Init(RTC_Type *base); - -/*! - * @brief Stop the timer and gate the RTC clock - * - * @param base RTC peripheral base address - */ -static inline void RTC_Deinit(RTC_Type *base) -{ - /* Stop the RTC timer */ - base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the module clock */ - CLOCK_DisableClock(kCLOCK_Rtc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! @}*/ - -/*! - * @name Current Time & Alarm - * @{ - */ - -/*! - * @brief Set the RTC date and time according to the given time structure. - * - * The RTC counter must be stopped prior to calling this function as writes to the RTC - * seconds register will fail if the RTC counter is running. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the date and time details to set are stored - * - * @return kStatus_Success: Success in setting the time and starting the RTC - * kStatus_InvalidArgument: Error because the datetime format is incorrect - */ -status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime); - -/*! - * @brief Get the RTC time and stores it in the given time structure. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the date and time details are stored. - */ -void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime); - -/*! - * @brief Set the RTC alarm time - * - * The function checks whether the specified alarm time is greater than the present - * time. If not, the function does not set the alarm and returns an error. - * - * @param base RTC peripheral base address - * @param alarmTime Pointer to structure where the alarm time is stored. - * - * @return kStatus_Success: success in setting the RTC alarm - * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect - * kStatus_Fail: Error because the alarm time has already passed - */ -status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime); - -/*! - * @brief Return the RTC alarm time. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the alarm date and time details are stored. - */ -void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime); - -/*! @}*/ - -/*! - * @name RTC wake-up timer (1KHZ) Enable - * @{ - */ - -/*! - * @brief Enable the RTC wake-up timer (1KHZ). - * - * After calling this function, the RTC driver will use/un-use the RTC wake-up (1KHZ) at the same time. - * - * @param base RTC peripheral base address - * @param enable Use/Un-use the RTC wake-up timer. - * - true: Use RTC wake-up timer at the same time. - * - false: Un-use RTC wake-up timer, RTC only use the normal seconds timer by default. - */ -static inline void RTC_EnableWakeupTimer(RTC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK; - } - else - { - base->CTRL &= ~RTC_CTRL_RTC1KHZ_EN_MASK; - } -} - -/*! - * @brief Get the enabled status of the RTC wake-up timer (1KHZ). - * - - * @param base RTC peripheral base address - * - * @return The enabled status of RTC wake-up timer (1KHZ). - */ -static inline uint32_t RTC_GetEnabledWakeupTimer(RTC_Type *base) -{ - return (base->CTRL & RTC_CTRL_RTC1KHZ_EN_MASK); -} - -/*! @}*/ - -/*! - * @brief Set the RTC seconds timer (1HZ) MATCH value. - * - * @param base RTC peripheral base address - * @param matchValue The value to be set into the RTC MATCH register - */ -static inline void RTC_SetSecondsTimerMatch(RTC_Type *base, uint32_t matchValue) -{ - /* Set the start match value into the default RTC seconds timer (1HZ). */ - base->MATCH = matchValue; -} - -/*! - * @brief Read actual RTC seconds timer (1HZ) MATCH value. - * - * @param base RTC peripheral base address - * - * @return The actual RTC seconds timer (1HZ) MATCH value. - */ -static inline uint32_t RTC_GetSecondsTimerMatch(RTC_Type *base) -{ - /* Read the RTC default seconds timer (1HZ) MATCH value. */ - return base->MATCH; -} - -/*! - * @brief Set the RTC seconds timer (1HZ) COUNT value. - * - * @param base RTC peripheral base address - * @param countValue The value to be loaded into the RTC COUNT register - */ -static inline void RTC_SetSecondsTimerCount(RTC_Type *base, uint32_t countValue) -{ - /* Set the start count value into the default RTC seconds timer (1HZ). */ - base->COUNT = countValue; -} - -/*! - * @brief Read the actual RTC seconds timer (1HZ) COUNT value. - * - * @param base RTC peripheral base address - * - * @return The actual RTC seconds timer (1HZ) COUNT value. - */ -static inline uint32_t RTC_GetSecondsTimerCount(RTC_Type *base) -{ - uint32_t a, b; - - /* Follow the RF document to read the RTC default seconds timer (1HZ) counter value. */ - do - { - a = base->COUNT; - b = base->COUNT; - } while (a != b); - - return b; -} - -/*! - * @brief Enable the RTC wake-up timer (1KHZ) and set countdown value to the RTC WAKE register. - * - * @param base RTC peripheral base address - * @param wakeupValue The value to be loaded into the WAKE register in RTC wake-up timer (1KHZ). - */ -static inline void RTC_SetWakeupCount(RTC_Type *base, uint16_t wakeupValue) -{ - /* Use the RTC wake-up timer (1KHZ) */ - base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK; - - /* Set the start countdown value into the RTC WAKE register */ - base->WAKE = RTC_WAKE_VAL((uint32_t)wakeupValue); -} - -/*! - * @brief Read the actual value from the WAKE register value in RTC wake-up timer (1KHZ). - * - * @param base RTC peripheral base address - * - * @return The actual value of the WAKE register value in RTC wake-up timer (1HZ). - */ -static inline uint16_t RTC_GetWakeupCount(RTC_Type *base) -{ - /* Read current wake-up countdown value */ - return (uint16_t)((base->WAKE & RTC_WAKE_VAL_MASK) >> RTC_WAKE_VAL_SHIFT); -} - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enable the wake-up timer interrupt from deep power down mode. - * - * @param base RTC peripheral base address - * @param enable Enable/Disable wake-up timer interrupt from deep power down mode. - * - true: Enable wake-up timer interrupt from deep power down mode. - * - false: Disable wake-up timer interrupt from deep power down mode. - */ -static inline void RTC_EnableWakeUpTimerInterruptFromDPD(RTC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= RTC_CTRL_WAKEDPD_EN_MASK; - } - else - { - base->CTRL &= ~RTC_CTRL_WAKEDPD_EN_MASK; - } -} - -/*! - * @brief Enable the alarm timer interrupt from deep power down mode. - * - * @param base RTC peripheral base address - * @param enable Enable/Disable alarm timer interrupt from deep power down mode. - * - true: Enable alarm timer interrupt from deep power down mode. - * - false: Disable alarm timer interrupt from deep power down mode. - */ -static inline void RTC_EnableAlarmTimerInterruptFromDPD(RTC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= RTC_CTRL_ALARMDPD_EN_MASK; - } - else - { - base->CTRL &= ~RTC_CTRL_ALARMDPD_EN_MASK; - } -} - -/*! - * @brief Enables the selected RTC interrupts. - * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableAlarmTimerInterruptFromDPD - * and RTC_EnableWakeUpTimerInterruptFromDPD - * - * @param base RTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) -{ - uint32_t reg = base->CTRL; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK); - reg |= mask; - - base->CTRL = reg; -} - -/*! - * @brief Disables the selected RTC interrupts. - * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableAlarmTimerInterruptFromDPD - * and RTC_EnableWakeUpTimerInterruptFromDPD - * - * @param base RTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) -{ - uint32_t reg = base->CTRL; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK | mask); - - base->CTRL = reg; -} - -/*! - * @brief Get the enabled RTC interrupts. - * @deprecated Do not use this function. It will be deleted in next release version. - * - * @param base RTC peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) -{ - return (base->CTRL & (RTC_CTRL_ALARMDPD_EN_MASK | RTC_CTRL_WAKEDPD_EN_MASK)); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Get the RTC status flags - * - * @param base RTC peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::rtc_status_flags_t - */ -static inline uint32_t RTC_GetStatusFlags(RTC_Type *base) -{ - return (base->CTRL & (RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK)); -} - -/*! - * @brief Clear the RTC status flags. - * - * @param base RTC peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::rtc_status_flags_t - */ -static inline void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) -{ - uint32_t reg = base->CTRL; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK); - - /* Write 1 to the flags we wish to clear */ - reg |= mask; - - base->CTRL = reg; -} - -/*! @}*/ - -/*! - * @name Timer Enable - * @{ - */ - -/*! - * @brief Enable the RTC timer counter. - * - * After calling this function, the RTC inner counter increments once a second when only using the RTC seconds timer - * (1hz), while the RTC inner wake-up timer countdown once a millisecond when using RTC wake-up timer (1KHZ) at the - * same time. RTC timer contain two timers, one is the RTC normal seconds timer, the other one is the RTC wake-up timer, - * the RTC enable bit is the master switch for the whole RTC timer, so user can use the RTC seconds (1HZ) timer - * independly, but they can't use the RTC wake-up timer (1KHZ) independently. - * - * @param base RTC peripheral base address - * @param enable Enable/Disable RTC Timer counter. - * - true: Enable RTC Timer counter. - * - false: Disable RTC Timer counter. - */ -static inline void RTC_EnableTimer(RTC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= RTC_CTRL_RTC_EN_MASK; - } - else - { - base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; - } -} - -/*! - * @brief Starts the RTC time counter. - * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableTimer - * - * After calling this function, the timer counter increments once a second provided SR[TOF] or - * SR[TIF] are not set. - * - * @param base RTC peripheral base address - */ -static inline void RTC_StartTimer(RTC_Type *base) -{ - base->CTRL |= RTC_CTRL_RTC_EN_MASK; -} - -/*! - * @brief Stops the RTC time counter. - * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableTimer - * - * RTC's seconds register can be written to only when the timer is stopped. - * - * @param base RTC peripheral base address - */ -static inline void RTC_StopTimer(RTC_Type *base) -{ - base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; -} - -/*! @}*/ - -/*! - * @brief Perform a software reset on the RTC module. - * - * This resets all RTC registers to their reset value. The bit is cleared by software explicitly clearing it. - * - * @param base RTC peripheral base address - */ -static inline void RTC_Reset(RTC_Type *base) -{ - base->CTRL |= RTC_CTRL_SWRESET_MASK; - base->CTRL &= ~RTC_CTRL_SWRESET_MASK; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_RTC_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sctimer.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sctimer.c deleted file mode 100644 index 4208097a8b9..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sctimer.c +++ /dev/null @@ -1,791 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sctimer.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.sctimer" -#endif - -/*! @brief Typedef for interrupt handler. */ -typedef void (*sctimer_isr_t)(SCT_Type *base); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base SCTimer peripheral base address - * - * @return The SCTimer instance - */ -static uint32_t SCTIMER_GetInstance(SCT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to SCT bases for each instance. */ -static SCT_Type *const s_sctBases[] = SCT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to SCT clocks for each instance. */ -static const clock_ip_name_t s_sctClocks[] = SCT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET -/*! @brief Pointers to SCT resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_sctResets[] = SCT_RSTS_N; -#else -/*! @brief Pointers to SCT resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_sctResets[] = SCT_RSTS; -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/*!< @brief SCTimer event Callback function. */ -static sctimer_event_callback_t s_eventCallback[FSL_FEATURE_SCT_NUMBER_OF_EVENTS]; - -/*!< @brief Keep track of SCTimer event number */ -static uint32_t s_currentEvent; - -/*!< @brief Keep track of SCTimer state number */ -static uint32_t s_currentState; - -/*!< @brief Keep track of SCTimer unify 32-bit or low 16-bit match/capture register number. */ -static uint32_t s_currentMatch; -/*!< @brief Keep track of SCTimer high 16-bit match/capture register number. */ -static uint32_t s_currentMatchhigh; - -/*! @brief Pointer to SCTimer IRQ handler */ -static sctimer_isr_t s_sctimerIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t SCTIMER_GetInstance(SCT_Type *base) -{ - uint32_t instance; - uint32_t sctArrayCount = (sizeof(s_sctBases) / sizeof(s_sctBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < sctArrayCount; instance++) - { - if (s_sctBases[instance] == base) - { - break; - } - } - - assert(instance < sctArrayCount); - - return instance; -} - -/*! - * brief Ungates the SCTimer clock and configures the peripheral for basic operation. - * - * note This API should be called at the beginning of the application using the SCTimer driver. - * - * param base SCTimer peripheral base address - * param config Pointer to the user configuration structure. - * - * return kStatus_Success indicates success; Else indicates failure. - */ -status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config) -{ - assert(NULL != config); - - uint32_t i; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the SCTimer clock*/ - CLOCK_EnableClock(s_sctClocks[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_sctResets[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - - /* Setup the counter operation. For Current Driver interface SCTIMER_Init don't know detail - * frequency of input clock, but User know it. So the INSYNC have to set by user level. */ - base->CONFIG = SCT_CONFIG_CKSEL(config->clockSelect) | SCT_CONFIG_CLKMODE(config->clockMode) | - SCT_CONFIG_UNIFY(config->enableCounterUnify) | SCT_CONFIG_INSYNC(config->inputsync); - - /* Write to the control register, keep the counters halted. */ - base->CTRL = - SCT_CTRL_BIDIR_L(config->enableBidirection_l) | SCT_CTRL_PRE_L(config->prescale_l) | SCT_CTRL_HALT_L_MASK; - /* Clear the counter after changing the PRE value. */ - base->CTRL |= SCT_CTRL_CLRCTR_L_MASK; - - if (!(config->enableCounterUnify)) - { - base->CTRL |= - SCT_CTRL_BIDIR_H(config->enableBidirection_h) | SCT_CTRL_PRE_H(config->prescale_h) | SCT_CTRL_HALT_H_MASK; - base->CTRL |= SCT_CTRL_CLRCTR_H_MASK; - } - - /* Initial state of channel output */ - base->OUTPUT = config->outInitState; - - /* Clear the global variables */ - s_currentEvent = 0U; - s_currentState = 0U; - s_currentMatch = 0U; - s_currentMatchhigh = 0U; - - /* Clear the callback array */ - for (i = 0; i < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) - { - s_eventCallback[i] = NULL; - } - - /* Save interrupt handler */ - s_sctimerIsr = SCTIMER_EventHandleIRQ; - - return kStatus_Success; -} - -/*! - * brief Gates the SCTimer clock. - * - * param base SCTimer peripheral base address - */ -void SCTIMER_Deinit(SCT_Type *base) -{ - /* Halt the counters */ - base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the SCTimer clock*/ - CLOCK_DisableClock(s_sctClocks[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Fills in the SCTimer configuration structure with the default settings. - * - * The default values are: - * code - * config->enableCounterUnify = true; - * config->clockMode = kSCTIMER_System_ClockMode; - * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - * config->enableBidirection_l = false; - * config->enableBidirection_h = false; - * config->prescale_l = 0U; - * config->prescale_h = 0U; - * config->outInitState = 0U; - * config->inputsync = 0xFU; - * endcode - * param config Pointer to the user configuration structure. - */ -void SCTIMER_GetDefaultConfig(sctimer_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* SCT operates as a unified 32-bit counter */ - config->enableCounterUnify = true; - /* System clock clocks the entire SCT module */ - config->clockMode = kSCTIMER_System_ClockMode; - /* This is used only by certain clock modes */ - config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - /* Up count mode only for the unified counter */ - config->enableBidirection_l = false; - /* Up count mode only for Counte_H */ - config->enableBidirection_h = false; - /* Prescale factor of 1 */ - config->prescale_l = 0U; - /* Prescale factor of 1 for Counter_H*/ - config->prescale_h = 0U; - /* Clear outputs */ - config->outInitState = 0U; - /* Default value is 0xFU, it can be clear as 0 when speical conditions met. - * Condition can be clear as 0: (for all Clock Modes): - * (1) The corresponding input is already synchronous to the SCTimer/PWM clock. - * (2) The SCTimer/PWM clock frequency does not exceed 100 MHz. - * Note: The SCTimer/PWM clock is the bus/system clock for CKMODE 0-2 or asynchronous input - * clock for CKMODE3. - * Another condition can be clear as 0: (for CKMODE2 only) - * (1) The corresponding input is synchronous to the designated CKMODE2 input clock. - * (2) The CKMODE2 input clock frequency is less than one-third the frequency of the bus/system clock. - * Default value set as 0U, input0~input3 are set as bypasses. */ - config->inputsync = 0xFU; -} - -/*! - * brief Configures the PWM signal parameters. - * - * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This - * function will create 2 events; one of the events will trigger on match with the pulse value - * and the other will trigger when the counter matches the PWM period. The PWM period event is - * also used as a limit event to reset the counter or change direction. Both events are enabled - * for the same state. The state number can be retrieved by calling the function - * SCTIMER_GetCurrentStateNumber(). - * The counter is set to operate as one 32-bit counter (unify bit is set to 1). - * The counter operates in bi-directional mode when generating a center-aligned PWM. - * - * note When setting PWM output from multiple output pins, they all should use the same PWM mode - * i.e all PWM's should be either edge-aligned or center-aligned. - * When using this API, the PWM signal frequency of all the initialized channels must be the same. - * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the - * API's pwmFreq_Hz. - * - * param base SCTimer peripheral base address - * param pwmParams PWM parameters to configure the output - * param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t - * param pwmFreq_Hz PWM signal frequency in Hz - * param srcClock_Hz SCTimer counter clock in Hz - * param event Pointer to a variable where the PWM period event number is stored - * - * return kStatus_Success on success - * kStatus_Fail If we have hit the limit in terms of number of events created or if - * an incorrect PWM dutycylce is passed in. - */ -status_t SCTIMER_SetupPwm(SCT_Type *base, - const sctimer_pwm_signal_param_t *pwmParams, - sctimer_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - uint32_t *event) -{ - assert(NULL != pwmParams); - assert(0U != srcClock_Hz); - assert(0U != pwmFreq_Hz); - assert((uint32_t)pwmParams->output < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - - /* If we do not have enough events available (this function will create two events), - * the function will return fail. - */ - status_t status = kStatus_Fail; - status_t status2; - uint32_t period, pulsePeriod = 0; - uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1U); - uint32_t periodEvent = 0, pulseEvent = 0; - uint32_t reg; - - if ((s_currentEvent + 2U) <= (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS) - { - /* Use bi-directional mode for center-aligned PWM */ - if (mode == kSCTIMER_CenterAlignedPwm) - { - base->CTRL |= SCT_CTRL_BIDIR_L_MASK; - } - - /* Calculate PWM period match value */ - if (mode == kSCTIMER_EdgeAlignedPwm) - { - period = (sctClock / pwmFreq_Hz) - 1U; - } - else - { - period = sctClock / (pwmFreq_Hz * 2U); - } - - /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ - if (pwmParams->dutyCyclePercent >= 100U) - { - pulsePeriod = period + 2U; - } - else - { - pulsePeriod = (uint32_t)(((uint64_t)period * pwmParams->dutyCyclePercent) / 100U); - } - - /* Schedule an event when we reach the PWM period */ - status = - SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, period, 0, kSCTIMER_Counter_U, &periodEvent); - - /* Schedule an event when we reach the pulse width */ - status2 = SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, pulsePeriod, 0, kSCTIMER_Counter_U, - &pulseEvent); - - if ((kStatus_Success == status) && (kStatus_Success == status2)) - { - /* Reset the counter when we reach the PWM period */ - SCTIMER_SetupCounterLimitAction(base, kSCTIMER_Counter_U, periodEvent); - - /* Return the period event to the user */ - *event = periodEvent; - - /* For high-true level */ - if ((uint32_t)pwmParams->level == (uint32_t)kSCTIMER_HighTrue) - { - if (mode == kSCTIMER_EdgeAlignedPwm) - { - /* Set the initial output level to low which is the inactive state */ - base->OUTPUT &= ~(1UL << (uint32_t)pwmParams->output); - /* Set the output when we reach the PWM period */ - SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, periodEvent); - /* Clear the output when we reach the PWM pulse value */ - SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, pulseEvent); - } - else - { - /* Set the initial output level to high which is the inactive state */ - base->OUTPUT |= (1UL << (uint32_t)pwmParams->output); - /* Clear the output when we reach the PWM pulse event */ - SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, pulseEvent); - /* Reverse output when down counting */ - reg = base->OUTPUTDIRCTRL; - reg &= ~((uint32_t)SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2U * (uint32_t)pwmParams->output)); - reg |= (1UL << (2U * (uint32_t)pwmParams->output)); - base->OUTPUTDIRCTRL = reg; - } - } - /* For low-true level */ - else - { - if (mode == kSCTIMER_EdgeAlignedPwm) - { - /* Set the initial output level to high which is the inactive state */ - base->OUTPUT |= (1UL << (uint32_t)pwmParams->output); - /* Clear the output when we reach the PWM period */ - SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, periodEvent); - /* Set the output when we reach the PWM pulse value */ - SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, pulseEvent); - } - else - { - /* Set the initial output level to low which is the inactive state */ - base->OUTPUT &= ~(1UL << (uint32_t)pwmParams->output); - /* Set the output when we reach the PWM pulse event */ - SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, pulseEvent); - /* Reverse output when down counting */ - reg = base->OUTPUTDIRCTRL; - reg &= ~((uint32_t)SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2U * (uint32_t)pwmParams->output)); - reg |= (1UL << (2U * (uint32_t)pwmParams->output)); - base->OUTPUTDIRCTRL = reg; - } - } - } - else - { - status = kStatus_Fail; - } - } - - return status; -} - -/*! - * brief Updates the duty cycle of an active PWM signal. - * - * Before calling this function, the counter is set to operate as one 32-bit counter (unify bit is set to 1). - * - * param base SCTimer peripheral base address - * param output The output to configure - * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 - * param event Event number associated with this PWM signal. This was returned to the user by the - * function SCTIMER_SetupPwm(). - */ -void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event) - -{ - assert(dutyCyclePercent <= 100U); - assert((uint32_t)output < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - - uint32_t periodMatchReg, pulseMatchReg; - uint32_t pulsePeriod = 0, period; - - /* Retrieve the match register number for the PWM period */ - periodMatchReg = base->EV[event].CTRL & SCT_EV_CTRL_MATCHSEL_MASK; - - /* Retrieve the match register number for the PWM pulse period */ - pulseMatchReg = base->EV[event + 1U].CTRL & SCT_EV_CTRL_MATCHSEL_MASK; - - period = base->MATCH[periodMatchReg]; - - /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ - if (dutyCyclePercent >= 100U) - { - pulsePeriod = period + 2U; - } - else - { - pulsePeriod = (uint32_t)(((uint64_t)period * dutyCyclePercent) / 100U); - } - - /* Stop the counter before updating match register */ - SCTIMER_StopTimer(base, (uint32_t)kSCTIMER_Counter_U); - - /* Update dutycycle */ - base->MATCH[pulseMatchReg] = SCT_MATCH_MATCHn_L(pulsePeriod); - base->MATCHREL[pulseMatchReg] = SCT_MATCHREL_RELOADn_L(pulsePeriod); - - /* Restart the counter */ - SCTIMER_StartTimer(base, (uint32_t)kSCTIMER_Counter_U); -} - -/*! - * brief Create an event that is triggered on a match or IO and schedule in current state. - * - * This function will configure an event using the options provided by the user. If the event type uses - * the counter match, then the function will set the user provided match value into a match register - * and put this match register number into the event control register. - * The event is enabled for the current state and the event number is increased by one at the end. - * The function returns the event number; this event number can be used to configure actions to be - * done when this event is triggered. - * - * param base SCTimer peripheral base address - * param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t - * param matchValue The match value that will be programmed to a match register - * param whichIO The input or output that will be involved in event triggering. This field - * is ignored if the event type is "match only" - * param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * param event Pointer to a variable where the new event number is stored - * - * return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of events created or - if we have reached the limit in terms of number of match registers - */ -status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, - sctimer_event_t howToMonitor, - uint32_t matchValue, - uint32_t whichIO, - sctimer_counter_t whichCounter, - uint32_t *event) -{ - uint32_t combMode = (((uint32_t)howToMonitor & SCT_EV_CTRL_COMBMODE_MASK) >> SCT_EV_CTRL_COMBMODE_SHIFT); - uint32_t currentCtrlVal = (uint32_t)howToMonitor; - status_t status = kStatus_Success; - uint32_t temp = 0; - - if (s_currentEvent < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS) - { - if (2U == combMode) - { - base->EV[s_currentEvent].CTRL = currentCtrlVal | SCT_EV_CTRL_IOSEL(whichIO); - } - else - { - if ((0U == combMode) || (3U == combMode)) - { - currentCtrlVal |= SCT_EV_CTRL_IOSEL(whichIO); - } - - if ((kSCTIMER_Counter_L == whichCounter) && (0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) - { - if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatch); - - /* Use Counter_L bits if user wants to setup the Low counter */ - base->MATCH_ACCESS16BIT[s_currentMatch].MATCHL = (uint16_t)matchValue; - base->MATCHREL_ACCESS16BIT[s_currentMatch].MATCHRELL = (uint16_t)matchValue; - base->EV[s_currentEvent].CTRL = currentCtrlVal; - - /* Increment the match register number */ - s_currentMatch++; - } - else - { - /* An error would occur if we have hit the limit in terms of number of match registers */ - status = kStatus_Fail; - } - } - else if ((kSCTIMER_Counter_H == whichCounter) && (0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) - { - if (s_currentMatchhigh < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatchhigh); - - /* Use Counter_H bits if user wants to setup the High counter */ - currentCtrlVal |= SCT_EV_CTRL_HEVENT(1U); - temp = base->MATCH_ACCESS16BIT[s_currentMatchhigh].MATCHL; - base->MATCH[s_currentMatchhigh] = temp | (matchValue << 16U); - temp = base->MATCHREL_ACCESS16BIT[s_currentMatchhigh].MATCHRELL; - base->MATCHREL[s_currentMatchhigh] = temp | (matchValue << 16U); - - base->EV[s_currentEvent].CTRL = currentCtrlVal; - /* Increment the match register number */ - s_currentMatchhigh++; - } - else - { - /* An error would occur if we have hit the limit in terms of number of match registers */ - status = kStatus_Fail; - } - } - else if ((kSCTIMER_Counter_U == whichCounter) && (0U != (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) - { - if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - /* Use Counter_L bits if counter is operating in 32-bit mode */ - currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatch); - - base->MATCH[s_currentMatch] = matchValue; - base->MATCHREL[s_currentMatch] = matchValue; - base->EV[s_currentEvent].CTRL = currentCtrlVal; - - /* Increment the match register number */ - s_currentMatch++; - } - else - { - /* An error would occur if we have hit the limit in terms of number of match registers */ - status = kStatus_Fail; - } - } - else - { - /* The used counter must match the CONFIG[UNIFY] bit selection */ - status = kStatus_Fail; - } - } - - if (kStatus_Success == status) - { - /* Enable the event in the current state */ - base->EV[s_currentEvent].STATE = (1UL << s_currentState); - - /* Return the event number */ - *event = s_currentEvent; - - /* Increment the event number */ - s_currentEvent++; - } - } - else - { - /* An error would occur if we have hit the limit in terms of number of events created */ - status = kStatus_Fail; - } - - return status; -} - -/*! - * brief Enable an event in the current state. - * - * This function will allow the event passed in to trigger in the current state. The event must - * be created earlier by either calling the function SCTIMER_SetupPwm() or function - * SCTIMER_CreateAndScheduleEvent() . - * - * param base SCTimer peripheral base address - * param event Event number to enable in the current state - * - */ -void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event) -{ - /* Enable event in the current state */ - base->EV[event].STATE |= (1UL << s_currentState); -} - -/*! - * brief Increase the state by 1 - * - * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new - * state. - * - * param base SCTimer peripheral base address - * - * return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of states used - - */ -status_t SCTIMER_IncreaseState(SCT_Type *base) -{ - status_t status = kStatus_Success; - - /* Return an error if we have hit the limit in terms of states used */ - if (s_currentState >= (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES) - { - status = kStatus_Fail; - } - else - { - s_currentState++; - } - - return status; -} - -/*! - * brief Provides the current state - * - * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). - * - * param base SCTimer peripheral base address - * - * return The current state - */ -uint32_t SCTIMER_GetCurrentState(SCT_Type *base) -{ - return s_currentState; -} - -/*! - * brief Toggle the output level. - * - * This change in the output level is triggered by the event number that is passed in by the user. - * - * param base SCTimer peripheral base address - * param whichIO The output to toggle - * param event Event number that will trigger the output change - */ -void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - uint32_t reg; - - /* Set the same event to set and clear the output */ - base->OUT[whichIO].CLR |= (1UL << event); - base->OUT[whichIO].SET |= (1UL << event); - - /* Set the conflict resolution to toggle output */ - reg = base->RES; - reg &= ~(((uint32_t)SCT_RES_O0RES_MASK) << (2U * whichIO)); - reg |= ((uint32_t)(kSCTIMER_ResolveToggle)) << (2U * whichIO); - base->RES = reg; -} - -/*! - * brief Setup capture of the counter value on trigger of a selected event - * - * param base SCTimer peripheral base address - * param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * param captureRegister Pointer to a variable where the capture register number will be returned. User - * can read the captured value from this register when the specified event is triggered. - * param event Event number that will trigger the capture - * - * return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of match/capture registers available - */ -status_t SCTIMER_SetupCaptureAction(SCT_Type *base, - sctimer_counter_t whichCounter, - uint32_t *captureRegister, - uint32_t event) -{ - status_t status; - uint32_t temp = 0; - - if ((kSCTIMER_Counter_L == whichCounter) || (kSCTIMER_Counter_U == whichCounter)) - { - if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - /* Set the bit to enable event */ - base->CAPCTRL_ACCESS16BIT[s_currentMatch].CAPCTRLL |= SCT_CAPCTRLL_CAPCTRLL(1UL << event); - - /* Set this resource to be a capture rather than match */ - base->REGMODE_ACCESS16BIT.REGMODEL |= SCT_REGMODEL_REGMODEL(1UL << s_currentMatch); - - /* Return the match register number */ - *captureRegister = s_currentMatch; - - /* Increase the match register number */ - s_currentMatch++; - - status = kStatus_Success; - } - else - { - /* Return an error if we have hit the limit in terms of number of capture/match registers used */ - status = kStatus_Fail; - } - } - else - { - if (s_currentMatchhigh < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - /* Set bit to enable event */ - temp = base->CAPCTRL_ACCESS16BIT[s_currentMatchhigh].CAPCTRLL; - base->CAPCTRL[s_currentMatchhigh] = temp | ((uint32_t)((uint32_t)(1UL << event) << 16U) & 0xFFFF000U); - /* Set this resource to be a capture rather than match */ - temp = base->REGMODE_ACCESS16BIT.REGMODEL; - base->REGMODE = temp | ((uint32_t)((uint32_t)(1UL << s_currentMatchhigh) << 16U) & 0xFFFF000U); - - /* Return the match register number */ - *captureRegister = s_currentMatchhigh; - - /* Increase the match register number */ - s_currentMatchhigh++; - - status = kStatus_Success; - } - else - { - /* Return an error if we have hit the limit in terms of number of capture/match registers used */ - status = kStatus_Fail; - } - } - - return status; -} - -/*! - * brief Receive noticification when the event trigger an interrupt. - * - * If the interrupt for the event is enabled by the user, then a callback can be registered - * which will be invoked when the event is triggered - * - * param base SCTimer peripheral base address - * param event Event number that will trigger the interrupt - * param callback Function to invoke when the event is triggered - */ - -void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event) -{ - s_eventCallback[event] = callback; -} - -/*! - * brief SCTimer interrupt handler. - * - * param base SCTimer peripheral base address. - */ -void SCTIMER_EventHandleIRQ(SCT_Type *base) -{ - uint32_t eventFlag = SCT0->EVFLAG; - /* Only clear the flags whose interrupt field is enabled */ - uint32_t clearFlag = (eventFlag & SCT0->EVEN); - uint32_t mask = eventFlag; - uint32_t i; - - /* Invoke the callback for certain events */ - for (i = 0; i < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) - { - if ((mask & 0x1U) != 0U) - { - if (s_eventCallback[i] != NULL) - { - s_eventCallback[i](); - } - } - mask >>= 1UL; - - if (0U == mask) - { - /* All events have been handled. */ - break; - } - } - - /* Clear event interrupt flag */ - SCT0->EVFLAG = clearFlag; -} - -void SCT0_DriverIRQHandler(void); -void SCT0_DriverIRQHandler(void) -{ - s_sctimerIsr(SCT0); - SDK_ISR_EXIT_BARRIER; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sctimer.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sctimer.h deleted file mode 100644 index 283a5b7019f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sctimer.h +++ /dev/null @@ -1,1258 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SCTIMER_H_ -#define _FSL_SCTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup sctimer - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 4, 4)) /*!< Version */ -/*@}*/ - -#ifndef SCT_EV_STATE_STATEMSKn -#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(x) & (1UL << FSL_FEATURE_SCT_NUMBER_OF_STATES) - 1UL)) -#endif - -/*! @brief SCTimer PWM operation modes */ -typedef enum _sctimer_pwm_mode -{ - kSCTIMER_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */ - kSCTIMER_CenterAlignedPwm /*!< Center-aligned PWM */ -} sctimer_pwm_mode_t; - -/*! @brief SCTimer counters type. */ -typedef enum _sctimer_counter -{ - kSCTIMER_Counter_L = (1U << 0), /*!< 16-bit Low counter. */ - kSCTIMER_Counter_H = (1U << 1), /*!< 16-bit High counter. */ - kSCTIMER_Counter_U = (1U << 2), /*!< 32-bit Unified counter. */ -} sctimer_counter_t; - -/*! @brief List of SCTimer input pins */ -typedef enum _sctimer_input -{ - kSCTIMER_Input_0 = 0U, /*!< SCTIMER input 0 */ - kSCTIMER_Input_1, /*!< SCTIMER input 1 */ - kSCTIMER_Input_2, /*!< SCTIMER input 2 */ - kSCTIMER_Input_3, /*!< SCTIMER input 3 */ - kSCTIMER_Input_4, /*!< SCTIMER input 4 */ - kSCTIMER_Input_5, /*!< SCTIMER input 5 */ - kSCTIMER_Input_6, /*!< SCTIMER input 6 */ - kSCTIMER_Input_7 /*!< SCTIMER input 7 */ -} sctimer_input_t; - -/*! @brief List of SCTimer output pins */ -typedef enum _sctimer_out -{ - kSCTIMER_Out_0 = 0U, /*!< SCTIMER output 0*/ - kSCTIMER_Out_1, /*!< SCTIMER output 1 */ - kSCTIMER_Out_2, /*!< SCTIMER output 2 */ - kSCTIMER_Out_3, /*!< SCTIMER output 3 */ - kSCTIMER_Out_4, /*!< SCTIMER output 4 */ - kSCTIMER_Out_5, /*!< SCTIMER output 5 */ - kSCTIMER_Out_6, /*!< SCTIMER output 6 */ - kSCTIMER_Out_7, /*!< SCTIMER output 7 */ - kSCTIMER_Out_8, /*!< SCTIMER output 8 */ - kSCTIMER_Out_9 /*!< SCTIMER output 9 */ -} sctimer_out_t; - -/*! @brief SCTimer PWM output pulse mode: high-true, low-true or no output */ -typedef enum _sctimer_pwm_level_select -{ - kSCTIMER_LowTrue = 0U, /*!< Low true pulses */ - kSCTIMER_HighTrue /*!< High true pulses */ -} sctimer_pwm_level_select_t; - -/*! @brief Options to configure a SCTimer PWM signal */ -typedef struct _sctimer_pwm_signal_param -{ - sctimer_out_t output; /*!< The output pin to use to generate the PWM signal */ - sctimer_pwm_level_select_t level; /*!< PWM output active level select. */ - uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 - 0 = always inactive signal (0% duty cycle) - 100 = always active signal (100% duty cycle).*/ -} sctimer_pwm_signal_param_t; - -/*! @brief SCTimer clock mode options */ -typedef enum _sctimer_clock_mode -{ - kSCTIMER_System_ClockMode = 0U, /*!< System Clock Mode */ - kSCTIMER_Sampled_ClockMode, /*!< Sampled System Clock Mode */ - kSCTIMER_Input_ClockMode, /*!< SCT Input Clock Mode */ - kSCTIMER_Asynchronous_ClockMode /*!< Asynchronous Mode */ -} sctimer_clock_mode_t; - -/*! @brief SCTimer clock select options */ -typedef enum _sctimer_clock_select -{ - kSCTIMER_Clock_On_Rise_Input_0 = 0U, /*!< Rising edges on input 0 */ - kSCTIMER_Clock_On_Fall_Input_0, /*!< Falling edges on input 0 */ - kSCTIMER_Clock_On_Rise_Input_1, /*!< Rising edges on input 1 */ - kSCTIMER_Clock_On_Fall_Input_1, /*!< Falling edges on input 1 */ - kSCTIMER_Clock_On_Rise_Input_2, /*!< Rising edges on input 2 */ - kSCTIMER_Clock_On_Fall_Input_2, /*!< Falling edges on input 2 */ - kSCTIMER_Clock_On_Rise_Input_3, /*!< Rising edges on input 3 */ - kSCTIMER_Clock_On_Fall_Input_3, /*!< Falling edges on input 3 */ - kSCTIMER_Clock_On_Rise_Input_4, /*!< Rising edges on input 4 */ - kSCTIMER_Clock_On_Fall_Input_4, /*!< Falling edges on input 4 */ - kSCTIMER_Clock_On_Rise_Input_5, /*!< Rising edges on input 5 */ - kSCTIMER_Clock_On_Fall_Input_5, /*!< Falling edges on input 5 */ - kSCTIMER_Clock_On_Rise_Input_6, /*!< Rising edges on input 6 */ - kSCTIMER_Clock_On_Fall_Input_6, /*!< Falling edges on input 6 */ - kSCTIMER_Clock_On_Rise_Input_7, /*!< Rising edges on input 7 */ - kSCTIMER_Clock_On_Fall_Input_7 /*!< Falling edges on input 7 */ -} sctimer_clock_select_t; - -/*! - * @brief SCTimer output conflict resolution options. - * - * Specifies what action should be taken if multiple events dictate that a given output should be - * both set and cleared at the same time - */ -typedef enum _sctimer_conflict_resolution -{ - kSCTIMER_ResolveNone = 0U, /*!< No change */ - kSCTIMER_ResolveSet, /*!< Set output */ - kSCTIMER_ResolveClear, /*!< Clear output */ - kSCTIMER_ResolveToggle /*!< Toggle output */ -} sctimer_conflict_resolution_t; - -/*! @brief List of SCTimer event generation active direction when the counters are operating in BIDIR mode. */ -typedef enum _sctimer_event_active_direction -{ - kSCTIMER_ActiveIndependent = 0U, /*!< This event is triggered regardless of the count direction. */ - kSCTIMER_ActiveInCountUp, /*!< This event is triggered only during up-counting when BIDIR = 1. */ - kSCTIMER_ActiveInCountDown /*!< This event is triggered only during down-counting when BIDIR = 1. */ -} sctimer_event_active_direction_t; - -/*! @brief List of SCTimer event types */ -typedef enum _sctimer_event -{ - kSCTIMER_InputLowOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_MatchEventOnly = - (1 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_InputLowEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_InputLowAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighOrMatchEvent = - (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighEvent = - (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighAndMatchEvent = - (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT) -} sctimer_event_t; - -/*! @brief SCTimer callback typedef. */ -typedef void (*sctimer_event_callback_t)(void); - -/*! @brief List of SCTimer interrupts */ -typedef enum _sctimer_interrupt_enable -{ - kSCTIMER_Event0InterruptEnable = (1U << 0), /*!< Event 0 interrupt */ - kSCTIMER_Event1InterruptEnable = (1U << 1), /*!< Event 1 interrupt */ - kSCTIMER_Event2InterruptEnable = (1U << 2), /*!< Event 2 interrupt */ - kSCTIMER_Event3InterruptEnable = (1U << 3), /*!< Event 3 interrupt */ - kSCTIMER_Event4InterruptEnable = (1U << 4), /*!< Event 4 interrupt */ - kSCTIMER_Event5InterruptEnable = (1U << 5), /*!< Event 5 interrupt */ - kSCTIMER_Event6InterruptEnable = (1U << 6), /*!< Event 6 interrupt */ - kSCTIMER_Event7InterruptEnable = (1U << 7), /*!< Event 7 interrupt */ - kSCTIMER_Event8InterruptEnable = (1U << 8), /*!< Event 8 interrupt */ - kSCTIMER_Event9InterruptEnable = (1U << 9), /*!< Event 9 interrupt */ - kSCTIMER_Event10InterruptEnable = (1U << 10), /*!< Event 10 interrupt */ - kSCTIMER_Event11InterruptEnable = (1U << 11), /*!< Event 11 interrupt */ - kSCTIMER_Event12InterruptEnable = (1U << 12), /*!< Event 12 interrupt */ -} sctimer_interrupt_enable_t; - -/*! @brief List of SCTimer flags */ -typedef enum _sctimer_status_flags -{ - kSCTIMER_Event0Flag = (1U << 0), /*!< Event 0 Flag */ - kSCTIMER_Event1Flag = (1U << 1), /*!< Event 1 Flag */ - kSCTIMER_Event2Flag = (1U << 2), /*!< Event 2 Flag */ - kSCTIMER_Event3Flag = (1U << 3), /*!< Event 3 Flag */ - kSCTIMER_Event4Flag = (1U << 4), /*!< Event 4 Flag */ - kSCTIMER_Event5Flag = (1U << 5), /*!< Event 5 Flag */ - kSCTIMER_Event6Flag = (1U << 6), /*!< Event 6 Flag */ - kSCTIMER_Event7Flag = (1U << 7), /*!< Event 7 Flag */ - kSCTIMER_Event8Flag = (1U << 8), /*!< Event 8 Flag */ - kSCTIMER_Event9Flag = (1U << 9), /*!< Event 9 Flag */ - kSCTIMER_Event10Flag = (1U << 10), /*!< Event 10 Flag */ - kSCTIMER_Event11Flag = (1U << 11), /*!< Event 11 Flag */ - kSCTIMER_Event12Flag = (1U << 12), /*!< Event 12 Flag */ - kSCTIMER_BusErrorLFlag = - (1U << SCT_CONFLAG_BUSERRL_SHIFT), /*!< Bus error due to write when L counter was not halted */ - kSCTIMER_BusErrorHFlag = - (int)(1U << SCT_CONFLAG_BUSERRH_SHIFT) /*!< Bus error due to write when H counter was not halted */ -} sctimer_status_flags_t; - -/*! - * @brief SCTimer configuration structure - * - * This structure holds the configuration settings for the SCTimer peripheral. To initialize this - * structure to reasonable defaults, call the SCTMR_GetDefaultConfig() function and pass a - * pointer to the configuration structure instance. - * - * The configuration structure can be made constant so as to reside in flash. - */ -typedef struct _sctimer_config -{ - bool enableCounterUnify; /*!< true: SCT operates as a unified 32-bit counter; - false: SCT operates as two 16-bit counters. - User can use the 16-bit low counter and the 16-bit high counters at the - same time; for Hardware limit, user can not use unified 32-bit counter - and any 16-bit low/high counter at the same time. */ - sctimer_clock_mode_t clockMode; /*!< SCT clock mode value */ - sctimer_clock_select_t clockSelect; /*!< SCT clock select value */ - bool enableBidirection_l; /*!< true: Up-down count mode for the L or unified counter - false: Up count mode only for the L or unified counter */ - bool enableBidirection_h; /*!< true: Up-down count mode for the H or unified counter - false: Up count mode only for the H or unified counter. - This field is used only if the enableCounterUnify is set - to false */ - uint8_t prescale_l; /*!< Prescale value to produce the L or unified counter clock */ - uint8_t prescale_h; /*!< Prescale value to produce the H counter clock. - This field is used only if the enableCounterUnify is set - to false */ - uint8_t outInitState; /*!< Defines the initial output value */ - uint8_t inputsync; /*!< SCT INSYNC value, INSYNC field in the CONFIG register, from bit9 to bit 16. - it is used to define synchronization for input N: - bit 9 = input 0 - bit 10 = input 1 - bit 11 = input 2 - bit 12 = input 3 - All other bits are reserved (bit13 ~bit 16). - How User to set the the value for the member inputsync. - IE: delay for input0, and input 1, bypasses for input 2 and input 3 - MACRO definition in user level. - \#define INPUTSYNC0 (0U) - \#define INPUTSYNC1 (1U) - \#define INPUTSYNC2 (2U) - \#define INPUTSYNC3 (3U) - User Code. - sctimerInfo.inputsync = (1 << INPUTSYNC2) | (1 << INPUTSYNC3); */ -} sctimer_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the SCTimer clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the SCTimer driver. - * - * @param base SCTimer peripheral base address - * @param config Pointer to the user configuration structure. - * - * @return kStatus_Success indicates success; Else indicates failure. - */ -status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config); - -/*! - * @brief Gates the SCTimer clock. - * - * @param base SCTimer peripheral base address - */ -void SCTIMER_Deinit(SCT_Type *base); - -/*! - * @brief Fills in the SCTimer configuration structure with the default settings. - * - * The default values are: - * @code - * config->enableCounterUnify = true; - * config->clockMode = kSCTIMER_System_ClockMode; - * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - * config->enableBidirection_l = false; - * config->enableBidirection_h = false; - * config->prescale_l = 0U; - * config->prescale_h = 0U; - * config->outInitState = 0U; - * config->inputsync = 0xFU; - * @endcode - * @param config Pointer to the user configuration structure. - */ -void SCTIMER_GetDefaultConfig(sctimer_config_t *config); - -/*! @}*/ - -/*! - * @name PWM setup operations - * @{ - */ - -/*! - * @brief Configures the PWM signal parameters. - * - * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This - * function will create 2 events; one of the events will trigger on match with the pulse value - * and the other will trigger when the counter matches the PWM period. The PWM period event is - * also used as a limit event to reset the counter or change direction. Both events are enabled - * for the same state. The state number can be retrieved by calling the function - * SCTIMER_GetCurrentStateNumber(). - * The counter is set to operate as one 32-bit counter (unify bit is set to 1). - * The counter operates in bi-directional mode when generating a center-aligned PWM. - * - * @note When setting PWM output from multiple output pins, they all should use the same PWM mode - * i.e all PWM's should be either edge-aligned or center-aligned. - * When using this API, the PWM signal frequency of all the initialized channels must be the same. - * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the - * API's pwmFreq_Hz. - * - * @param base SCTimer peripheral base address - * @param pwmParams PWM parameters to configure the output - * @param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz SCTimer counter clock in Hz - * @param event Pointer to a variable where the PWM period event number is stored - * - * @return kStatus_Success on success - * kStatus_Fail If we have hit the limit in terms of number of events created or if - * an incorrect PWM dutycylce is passed in. - */ -status_t SCTIMER_SetupPwm(SCT_Type *base, - const sctimer_pwm_signal_param_t *pwmParams, - sctimer_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - uint32_t *event); - -/*! - * @brief Updates the duty cycle of an active PWM signal. - * - * Before calling this function, the counter is set to operate as one 32-bit counter (unify bit is set to 1). - * - * @param base SCTimer peripheral base address - * @param output The output to configure - * @param dutyCyclePercent New PWM pulse width; the value should be between 1 to 100 - * @param event Event number associated with this PWM signal. This was returned to the user by the - * function SCTIMER_SetupPwm(). - */ -void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event); - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline void SCTIMER_EnableInterrupts(SCT_Type *base, uint32_t mask) -{ - base->EVEN |= mask; -} - -/*! - * @brief Disables the selected SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline void SCTIMER_DisableInterrupts(SCT_Type *base, uint32_t mask) -{ - base->EVEN &= ~mask; -} - -/*! - * @brief Gets the enabled SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline uint32_t SCTIMER_GetEnabledInterrupts(SCT_Type *base) -{ - return (base->EVEN & 0xFFFFU); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the SCTimer status flags. - * - * @param base SCTimer peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::sctimer_status_flags_t - */ -static inline uint32_t SCTIMER_GetStatusFlags(SCT_Type *base) -{ - uint32_t statusFlags = 0; - - /* Add the recorded events */ - statusFlags = (base->EVFLAG & 0xFFFFU); - - /* Add bus error flags */ - statusFlags |= (base->CONFLAG & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); - - return statusFlags; -} - -/*! - * @brief Clears the SCTimer status flags. - * - * @param base SCTimer peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::sctimer_status_flags_t - */ -static inline void SCTIMER_ClearStatusFlags(SCT_Type *base, uint32_t mask) -{ - /* Write to the flag registers */ - base->EVFLAG = (mask & 0xFFFFU); - base->CONFLAG = (mask & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); -} - -/*! @}*/ - -/*! - * @name Counter Start and Stop - * @{ - */ - -/*! - * @brief Starts the SCTimer counter. - * - * @note In 16-bit mode, we can enable both Counter_L and Counter_H, In 32-bit mode, we only can select Counter_U. - * - * @param base SCTimer peripheral base address - * @param countertoStart The SCTimer counters to enable. This is a logical OR of members of the - * enumeration ::sctimer_counter_t. - */ -static inline void SCTIMER_StartTimer(SCT_Type *base, uint32_t countertoStart) -{ - switch (countertoStart) - { - case (uint32_t)kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_L bit when user wants to start the Low counter */ - base->CTRL_ACCESS16BIT.CTRLL &= ~((uint16_t)SCT_CTRLL_HALT_L_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_H bit when user wants to start the High counter */ - base->CTRL_ACCESS16BIT.CTRLH &= ~((uint16_t)SCT_CTRLH_HALT_H_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_L | (uint32_t)kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_L/HALT_H bit when user wants to H counter and L counter at same time */ - base->CTRL &= ~(SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_L bit when the counter is operating in 32-bit mode (unify counter). */ - base->CTRL &= ~(SCT_CTRL_HALT_L_MASK); - break; - - default: - /* Counter_L/Counter_H can't work together with Counter_U. */ - assert(false); - break; - } -} - -/*! - * @brief Halts the SCTimer counter. - * - * @param base SCTimer peripheral base address - * @param countertoStop The SCTimer counters to stop. This is a logical OR of members of the - * enumeration ::sctimer_counter_t. - */ -static inline void SCTIMER_StopTimer(SCT_Type *base, uint32_t countertoStop) -{ - switch (countertoStop) - { - case (uint32_t)kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Set HALT_L bit when user wants to start the Low counter */ - base->CTRL_ACCESS16BIT.CTRLL |= (SCT_CTRLL_HALT_L_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Set HALT_H bit when user wants to start the High counter */ - base->CTRL_ACCESS16BIT.CTRLH |= (SCT_CTRLH_HALT_H_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_L | (uint32_t)kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Clear HALT_L/HALT_H bit when user wants to H counter and L counter at same time */ - base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); - break; - - case (uint32_t)kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Set HALT_L bit when the counter is operating in 32-bit mode (unify counter). */ - base->CTRL |= (SCT_CTRL_HALT_L_MASK); - break; - - default: - /* Counter_L/Counter_H can't work together with Counter_U. */ - assert(false); - break; - } -} - -/*! @}*/ - -/*! - * @name Functions to create a new event and manage the state logic - * @{ - */ - -/*! - * @brief Create an event that is triggered on a match or IO and schedule in current state. - * - * This function will configure an event using the options provided by the user. If the event type uses - * the counter match, then the function will set the user provided match value into a match register - * and put this match register number into the event control register. - * The event is enabled for the current state and the event number is increased by one at the end. - * The function returns the event number; this event number can be used to configure actions to be - * done when this event is triggered. - * - * @param base SCTimer peripheral base address - * @param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t - * @param matchValue The match value that will be programmed to a match register - * @param whichIO The input or output that will be involved in event triggering. This field - * is ignored if the event type is "match only" - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Pointer to a variable where the new event number is stored - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of events created or - if we have reached the limit in terms of number of match registers - */ -status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, - sctimer_event_t howToMonitor, - uint32_t matchValue, - uint32_t whichIO, - sctimer_counter_t whichCounter, - uint32_t *event); - -/*! - * @brief Enable an event in the current state. - * - * This function will allow the event passed in to trigger in the current state. The event must - * be created earlier by either calling the function SCTIMER_SetupPwm() or function - * SCTIMER_CreateAndScheduleEvent() . - * - * @param base SCTimer peripheral base address - * @param event Event number to enable in the current state - * - */ -void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event); - -/*! - * @brief Increase the state by 1 - * - * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new - * state. - * - * @param base SCTimer peripheral base address - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of states used - - */ -status_t SCTIMER_IncreaseState(SCT_Type *base); - -/*! - * @brief Provides the current state - * - * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). - * - * @param base SCTimer peripheral base address - * - * @return The current state - */ -uint32_t SCTIMER_GetCurrentState(SCT_Type *base); - -/*! - * @brief Set the counter current state. - * - * The function is to set the state variable bit field of STATE register. Writing to the STATE_L, STATE_H, or unified - * register is only allowed when the corresponding counter is halted (HALT bits are set to 1 in the CTRL register). - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param state The counter current state number (only support range from 0~31). - */ -static inline void SCTIMER_SetCounterState(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t state) -{ - /* SCT only support 0 ~ FSL_FEATURE_SCT_NUMBER_OF_STATES state value. */ - assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); - - SCTIMER_StopTimer(base, (uint32_t)whichCounter); - - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_L bits when user wants to setup the Low counter */ - base->STATE_ACCESS16BIT.STATEL = SCT_STATEL_STATEL(state); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_H bits when user wants to start the High counter */ - base->STATE_ACCESS16BIT.STATEH = SCT_STATEH_STATEH(state); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_L bits when counter is operating in 32-bit mode (unify counter). */ - base->STATE = SCT_STATE_STATE_L(state); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } - - SCTIMER_StartTimer(base, (uint32_t)whichCounter); -} - -/*! - * @brief Get the counter current state value. - * - * The function is to get the state variable bit field of STATE register. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @return The the counter current state value. - */ -static inline uint16_t SCTIMER_GetCounterState(SCT_Type *base, sctimer_counter_t whichCounter) -{ - uint16_t regs; - - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_L bits when user wants to setup the Low counter */ - regs = base->STATE_ACCESS16BIT.STATEL & SCT_STATEL_STATEL_MASK; - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_H bits when user wants to start the High counter */ - regs = base->STATE_ACCESS16BIT.STATEH & SCT_STATEH_STATEH_MASK; - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use STATE_L bits when counter is operating in 32-bit mode (unify counter). */ - regs = (uint16_t)(base->STATE & SCT_STATE_STATE_L_MASK); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } - - return regs; -} - -/*! @}*/ - -/*! - * @name Actions to take in response to an event - * @{ - */ - -/*! - * @brief Setup capture of the counter value on trigger of a selected event - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param captureRegister Pointer to a variable where the capture register number will be returned. User - * can read the captured value from this register when the specified event is triggered. - * @param event Event number that will trigger the capture - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of match/capture registers available - */ -status_t SCTIMER_SetupCaptureAction(SCT_Type *base, - sctimer_counter_t whichCounter, - uint32_t *captureRegister, - uint32_t event); - -/*! - * @brief Receive noticification when the event trigger an interrupt. - * - * If the interrupt for the event is enabled by the user, then a callback can be registered - * which will be invoked when the event is triggered - * - * @param base SCTimer peripheral base address - * @param event Event number that will trigger the interrupt - * @param callback Function to invoke when the event is triggered - */ - -void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event); - -/*! - * @brief Change the load method of transition to the specified state. - * - * Change the load method of transition, it will be triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param event Event number that will change the method to trigger the state transition - * @param fgLoad The method to load highest-numbered event occurring for that state to the STATE register. - * - true: Load the STATEV value to STATE when the event occurs to be the next state. - * - false: Add the STATEV value to STATE when the event occurs to be the next state. - */ -static inline void SCTIMER_SetupStateLdMethodAction(SCT_Type *base, uint32_t event, bool fgLoad) -{ - uint32_t reg = base->EV[event].CTRL; - - if (fgLoad) - { - /* Load the STATEV value to STATE when the event occurs to be the next state */ - reg |= SCT_EV_CTRL_STATELD_MASK; - } - else - { - /* Add the STATEV value to STATE when the event occurs to be the next state */ - reg &= ~SCT_EV_CTRL_STATELD_MASK; - } - - base->EV[event].CTRL = reg; -} - -/*! - * @brief Transition to the specified state with Load method. - * - * This transition will be triggered by the event number that is passed in by the user, the method decide how to load - * the highest-numbered event occurring for that state to the STATE register. - * - * @param base SCTimer peripheral base address - * @param nextState The next state SCTimer will transition to - * @param event Event number that will trigger the state transition - * @param fgLoad The method to load the highest-numbered event occurring for that state to the STATE register. - * - true: Load the STATEV value to STATE when the event occurs to be the next state. - * - false: Add the STATEV value to STATE when the event occurs to be the next state. - */ -static inline void SCTIMER_SetupNextStateActionwithLdMethod(SCT_Type *base, - uint32_t nextState, - uint32_t event, - bool fgLoad) -{ - uint32_t reg = base->EV[event].CTRL; - - reg &= ~(SCT_EV_CTRL_STATEV_MASK | SCT_EV_CTRL_STATELD_MASK); - - reg |= SCT_EV_CTRL_STATEV(nextState); - - if (fgLoad) - { - /* Load the STATEV value when the event occurs to be the next state */ - reg |= SCT_EV_CTRL_STATELD_MASK; - } - - base->EV[event].CTRL = reg; -} - -/*! - * @brief Transition to the specified state. - * @deprecated Do not use this function. It has been superceded by @ref SCTIMER_SetupNextStateActionwithLdMethod - * - * This transition will be triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param nextState The next state SCTimer will transition to - * @param event Event number that will trigger the state transition - */ -static inline void SCTIMER_SetupNextStateAction(SCT_Type *base, uint32_t nextState, uint32_t event) -{ - uint32_t reg = base->EV[event].CTRL; - - reg &= ~(SCT_EV_CTRL_STATEV_MASK); - /* Load the STATEV value when the event occurs to be the next state */ - reg |= SCT_EV_CTRL_STATEV(nextState) | SCT_EV_CTRL_STATELD_MASK; - - base->EV[event].CTRL = reg; -} - -/*! - * @brief Setup event active direction when the counters are operating in BIDIR mode. - * - * @param base SCTimer peripheral base address - * @param activeDirection Event generation active direction, see @ref sctimer_event_active_direction_t. - * @param event Event number that need setup the active direction. - */ -static inline void SCTIMER_SetupEventActiveDirection(SCT_Type *base, - sctimer_event_active_direction_t activeDirection, - uint32_t event) -{ - uint32_t reg = base->EV[event].CTRL; - - reg &= ~(SCT_EV_CTRL_DIRECTION_MASK); - - reg |= SCT_EV_CTRL_DIRECTION(activeDirection); - - base->EV[event].CTRL = reg; -} - -/*! - * @brief Set the Output. - * - * This output will be set when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to set - * @param event Event number that will trigger the output change - */ -static inline void SCTIMER_SetupOutputSetAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - base->OUT[whichIO].SET |= (1UL << event); -} - -/*! - * @brief Clear the Output. - * - * This output will be cleared when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to clear - * @param event Event number that will trigger the output change - */ -static inline void SCTIMER_SetupOutputClearAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - base->OUT[whichIO].CLR |= (1UL << event); -} - -/*! - * @brief Toggle the output level. - * - * This change in the output level is triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to toggle - * @param event Event number that will trigger the output change - */ -void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event); - -/*! - * @brief Limit the running counter. - * - * The counter is limited when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Event number that will trigger the counter to be limited - */ -static inline void SCTIMER_SetupCounterLimitAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->LIMIT_ACCESS16BIT.LIMITL |= SCT_LIMITL_LIMITL(1UL << event); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->LIMIT_ACCESS16BIT.LIMITH |= SCT_LIMITH_LIMITH(1UL << event); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->LIMIT |= SCT_LIMIT_LIMMSK_L(1UL << event); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } -} - -/*! - * @brief Stop the running counter. - * - * The counter is stopped when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Event number that will trigger the counter to be stopped - */ -static inline void SCTIMER_SetupCounterStopAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->STOP_ACCESS16BIT.STOPL |= SCT_STOPL_STOPL(1UL << event); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->STOP_ACCESS16BIT.STOPH |= SCT_STOPH_STOPH(1UL << event); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->STOP |= SCT_STOP_STOPMSK_L(1UL << event); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } -} - -/*! - * @brief Re-start the stopped counter. - * - * The counter will re-start when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Event number that will trigger the counter to re-start - */ -static inline void SCTIMER_SetupCounterStartAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->START_ACCESS16BIT.STARTL |= SCT_STARTL_STARTL(1UL << event); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->START_ACCESS16BIT.STARTH |= SCT_STARTH_STARTH(1UL << event); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->START |= SCT_START_STARTMSK_L(1UL << event); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } -} - -/*! - * @brief Halt the running counter. - * - * The counter is disabled (halted) when the event number that is passed in by the user is - * triggered. When the counter is halted, all further events are disabled. The HALT condition - * can only be removed by calling the SCTIMER_StartTimer() function. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param event Event number that will trigger the counter to be halted - */ -static inline void SCTIMER_SetupCounterHaltAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->HALT_ACCESS16BIT.HALTL |= SCT_HALTL_HALTL(1UL << event); - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->HALT_ACCESS16BIT.HALTH |= SCT_HALTH_HALTH(1UL << event); - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->HALT |= SCT_HALT_HALTMSK_L(1UL << event); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } -} - -#if !(defined(FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) && FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) -/*! - * @brief Generate a DMA request. - * - * DMA request will be triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param dmaNumber The DMA request to generate - * @param event Event number that will trigger the DMA request - */ -static inline void SCTIMER_SetupDmaTriggerAction(SCT_Type *base, uint32_t dmaNumber, uint32_t event) -{ - if (dmaNumber == 0U) - { - base->DMAREQ0 |= (1UL << event); - } - else - { - base->DMAREQ1 |= (1UL << event); - } -} -#endif /* FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST */ - -/*! - * @brief Set the value of counter. - * - * The function is to set the value of Count register, Writing to the COUNT_L, COUNT_H, or unified register - * is only allowed when the corresponding counter is halted (HALT bits are set to 1 in the CTRL register). - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @param value the counter value update to the COUNT register. - */ -static inline void SCTIMER_SetCOUNTValue(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t value) -{ - SCTIMER_StopTimer(base, (uint32_t)whichCounter); - - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(value <= 0xFFFFU); - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - base->COUNT_ACCESS16BIT.COUNTL = (uint16_t)value; - break; - - case kSCTIMER_Counter_H: - assert(value <= 0xFFFFU); - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - base->COUNT_ACCESS16BIT.COUNTH = (uint16_t)value; - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - base->COUNT &= ~SCT_COUNT_CTR_L_MASK; - base->COUNT |= SCT_COUNT_CTR_L(value); - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } - - SCTIMER_StartTimer(base, (uint32_t)whichCounter); -} - -/*! - * @brief Get the value of counter. - * - * The function is to read the value of Count register, software can read the counter registers at any time.. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, - * In 32-bit mode, we can select Counter_U. - * @return The value of counter selected. - */ -static inline uint32_t SCTIMER_GetCOUNTValue(SCT_Type *base, sctimer_counter_t whichCounter) -{ - uint32_t value; - - switch (whichCounter) - { - case kSCTIMER_Counter_L: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when user wants to setup the Low counter */ - value = base->COUNT_ACCESS16BIT.COUNTL; - break; - - case kSCTIMER_Counter_H: - assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_H bits when user wants to start the High counter */ - value = base->COUNT_ACCESS16BIT.COUNTH; - break; - - case kSCTIMER_Counter_U: - assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); - /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ - value = base->COUNT; - break; - - default: - /* Fix the MISRA C-2012 issue rule 16.4. */ - break; - } - - return value; -} - -/*! - * @brief Set the state mask bit field of EV_STATE register. - * - * @param base SCTimer peripheral base address - * @param event The EV_STATE register be set. - * @param state The state value in which the event is enabled to occur. - */ -static inline void SCTIMER_SetEventInState(SCT_Type *base, uint32_t event, uint32_t state) -{ - assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); - assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); - - base->EV[event].STATE |= SCT_EV_STATE_STATEMSKn((uint32_t)1U << state); -} - -/*! - * @brief Clear the state mask bit field of EV_STATE register. - * - * @param base SCTimer peripheral base address - * @param event The EV_STATE register be clear. - * @param state The state value in which the event is disabled to occur. - */ -static inline void SCTIMER_ClearEventInState(SCT_Type *base, uint32_t event, uint32_t state) -{ - assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); - assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); - - base->EV[event].STATE &= ~SCT_EV_STATE_STATEMSKn((uint32_t)1U << state); -} - -/*! - * @brief Get the state mask bit field of EV_STATE register. - * - * @note This function is to check whether the event is enabled in a specific state. - * - * @param base SCTimer peripheral base address - * @param event The EV_STATE register be read. - * @param state The state value. - * - * @return The the state mask bit field of EV_STATE register. - * - true: The event is enable in state. - * - false: The event is disable in state. - */ -static inline bool SCTIMER_GetEventInState(SCT_Type *base, uint32_t event, uint32_t state) -{ - assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); - assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); - - return (0U != (base->EV[event].STATE & SCT_EV_STATE_STATEMSKn((uint32_t)1U << state))); -} - -/*! - * @brief SCTimer interrupt handler. - * - * @param base SCTimer peripheral base address. - */ -void SCTIMER_EventHandleIRQ(SCT_Type *base); - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_SCTIMER_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sdif.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sdif.c deleted file mode 100644 index ba2fbafd71b..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sdif.c +++ /dev/null @@ -1,1688 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sdif.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.sdif" -#endif - -/* Typedef for interrupt handler. */ -typedef void (*sdif_isr_t)(SDIF_Type *base, sdif_handle_t *handle); - -/*! @brief convert the name here, due to RM use SDIO */ -#define SDIF_DriverIRQHandler SDIO_DriverIRQHandler -/*! @brief define the controller support sd/sdio card version 2.0 */ -#define SDIF_SUPPORT_SD_VERSION (0x20) -/*! @brief define the controller support mmc card version 4.4 */ -#define SDIF_SUPPORT_MMC_VERSION (0x44) - -#ifndef SDIF_TIMEOUT_VALUE -/*! @brief define the timeout counter, used to polling the start bit auto-cleared when sending clock sync command */ -#define SDIF_TIMEOUT_VALUE (~0U) -#endif - -#ifndef SDIF_RESET_TIMEOUT_VALUE -/*! @brief define the reset timeout counter, two AHB clock cycle, the reset should auto-cleared. */ -#define SDIF_RESET_TIMEOUT_VALUE (100U) -#endif - -/*! @brief this value can be any value */ -#define SDIF_POLL_DEMAND_VALUE (0xFFU) -/*! @brief DMA descriptor buffer1 size */ -#define SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(x) ((x)&0x1FFFU) -/*! @brief DMA descriptor buffer2 size */ -#define SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(x) (((x)&0x1FFFU) << 13U) -/*! @brief RX water mark value */ -#define SDIF_RX_WATERMARK (15U) -/*! @brief TX water mark value */ -#define SDIF_TX_WATERMARK (16U) -/*! @brief check flag avalibility */ -#define IS_SDIF_FLAG_SET(reg, flag) (((reg) & ((uint32_t)flag)) != 0UL) -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get the instance. - * - * @param base SDIF peripheral base address. - * @return Instance number. - */ -static uint32_t SDIF_GetInstance(SDIF_Type *base); - -/* - * @brief config the SDIF interface before transfer between the card and host - * @param SDIF base address - * @param transfer config structure - * @param enDMA DMA enable flag - */ -static status_t SDIF_TransferConfig(SDIF_Type *base, sdif_transfer_t *transfer, bool enDMA); - -/* - * @brief wait the command done function and check error status - * @param SDIF base address - * @param command config structure - */ -static status_t SDIF_WaitCommandDone(SDIF_Type *base, sdif_command_t *command); - -/* - * @brief transfer data in a blocking way - * @param SDIF base address - * @param data config structure - * @param indicate current transfer mode:DMA or polling - */ -static status_t SDIF_TransferDataBlocking(SDIF_Type *base, sdif_data_t *data, bool isDMA); - -/* - * @brief read the command response - * @param SDIF base address - * @param sdif command pointer - */ -static status_t SDIF_ReadCommandResponse(SDIF_Type *base, sdif_command_t *command); - -/* - * @brief handle transfer command interrupt - * @param SDIF base address - * @param sdif handle - * @param interrupt mask flags - */ -static void SDIF_TransferHandleCommand(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags); - -/* - * @brief handle transfer data interrupt - * @param SDIF base address - * @param sdif handle - * @param interrupt mask flags - */ -static void SDIF_TransferHandleData(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags); - -/* - * @brief handle DMA transfer - * @param SDIF base address - * @param sdif handle - * @param interrupt mask flag - */ -static void SDIF_TransferHandleDMA(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags); - -/* - * @brief driver IRQ handler - * @param SDIF base address - * @param sdif handle - */ -static void SDIF_TransferHandleIRQ(SDIF_Type *base, sdif_handle_t *handle); - -/* - * @brief read data port - * @param SDIF base address - * @param sdif data - * @param the number of data been transferred - */ -static uint32_t SDIF_ReadDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords); - -/* - * @brief write data port - * @param SDIF base address - * @param sdif data - * @param the number of data been transferred - */ -static uint32_t SDIF_WriteDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords); - -/* - * @brief read data by blocking way - * @param SDIF base address - * @param sdif data - */ -static status_t SDIF_ReadDataPortBlocking(SDIF_Type *base, sdif_data_t *data); - -/* - * @brief write data by blocking way - * @param SDIF base address - * @param sdif data - */ -static status_t SDIF_WriteDataPortBlocking(SDIF_Type *base, sdif_data_t *data); - -/* - * @brief handle sdio interrupt - * This function will call the SDIO interrupt callback - * @param SDIF base address - * @param SDIF handle - */ -static void SDIF_TransferHandleSDIOInterrupt(SDIF_Type *base, sdif_handle_t *handle); - -/* - * @brief handle card detect - * This function will call the cardInserted callback - * @param SDIF base addres - * @param SDIF handle - */ -static void SDIF_TransferHandleCardDetect(SDIF_Type *base, sdif_handle_t *handle); - -/* - * @brief set command register - * This api include polling the status of the bit START_COMMAND, if 0 used as timeout value, then this function - * will return directly without polling the START_CMD status. - * - * @param base SDIF base addres - * @param cmdIndex command index - * @param argument command argument - * @param timeout timeout value - * - * @return kStatus_Success, kStatus_SDIF_SyncCmdTimeout - */ -static status_t SDIF_SetCommandRegister(SDIF_Type *base, uint32_t cmdIndex, uint32_t argument, uint32_t timeout); - -/* - * @brief SDIF sync clock command function. - * - * This function will try to recovery the host while sending clock command failed. - * - * @param base SDIF base addres - * - * @return kStatus_Success, kStatus_SDIF_SyncCmdTimeout - */ -static status_t SDIF_SyncClockCommand(SDIF_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief SDIF internal handle pointer array */ -static sdif_handle_t *s_sdifHandle[FSL_FEATURE_SOC_SDIF_COUNT]; - -/*! @brief SDIF base pointer array */ -static SDIF_Type *const s_sdifBase[] = SDIF_BASE_PTRS; - -/*! @brief SDIF IRQ name array */ -static const IRQn_Type s_sdifIRQ[] = SDIF_IRQS; - -/* SDIF ISR for transactional APIs. */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -static sdif_isr_t s_sdifIsr = (sdif_isr_t)DefaultISR; -#else -static sdif_isr_t s_sdifIsr; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t SDIF_GetInstance(SDIF_Type *base) -{ - uint8_t instance = 0U; - - while ((instance < ARRAY_SIZE(s_sdifBase)) && (s_sdifBase[instance] != base)) - { - instance++; - } - - assert(instance < ARRAY_SIZE(s_sdifBase)); - - return instance; -} - -static status_t SDIF_TransferConfig(SDIF_Type *base, sdif_transfer_t *transfer, bool enDMA) -{ - sdif_command_t *command = transfer->command; - sdif_data_t *data = transfer->data; - - if ((command == NULL) || ((data != NULL) && (data->blockSize > SDIF_BLKSIZ_BLOCK_SIZE_MASK))) - { - return kStatus_SDIF_InvalidArgument; - } - - if (data != NULL) - { - /* config the block size register ,the block size maybe smaller than FIFO - depth, will test on the board */ - base->BLKSIZ = SDIF_BLKSIZ_BLOCK_SIZE(data->blockSize); - /* config the byte count register */ - base->BYTCNT = SDIF_BYTCNT_BYTE_COUNT(data->blockSize * data->blockCount); - - command->flags |= (uint32_t)kSDIF_DataExpect; /* need transfer data flag */ - - if (data->txData != NULL) - { - command->flags |= (uint32_t)kSDIF_DataWriteToCard; /* data transfer direction */ - } - else - { - /* config the card read threshold,enable the card read threshold */ - if (data->blockSize <= (SDIF_FIFO_COUNT * sizeof(uint32_t))) - { - base->CARDTHRCTL = SDIF_CARDTHRCTL_CARDRDTHREN_MASK | SDIF_CARDTHRCTL_CARDTHRESHOLD(data->blockSize); - } - else - { - base->CARDTHRCTL &= ~SDIF_CARDTHRCTL_CARDRDTHREN_MASK; - } - } - - if (data->streamTransfer) - { - command->flags |= - (uint32_t)kSDIF_DataStreamTransfer; /* indicate if use stream transfer or block transfer */ - } - - if ((data->enableAutoCommand12) && - (data->blockCount > 1UL)) /* indicate if auto stop will send after the data transfer done */ - { - command->flags |= (uint32_t)kSDIF_DataTransferAutoStop; - } - } - /* R2 response length long */ - if (command->responseType == (uint32_t)kCARD_ResponseTypeR2) - { - command->flags |= ((uint32_t)kSDIF_CmdCheckResponseCRC | (uint32_t)kSDIF_CmdResponseLengthLong | - (uint32_t)kSDIF_CmdResponseExpect); - } - else if ((command->responseType == (uint32_t)kCARD_ResponseTypeR3) || - (command->responseType == (uint32_t)kCARD_ResponseTypeR4)) - { - command->flags |= (uint32_t)kSDIF_CmdResponseExpect; /* response R3 do not check Response CRC */ - } - else - { - if (command->responseType != (uint32_t)kCARD_ResponseTypeNone) - { - command->flags |= ((uint32_t)kSDIF_CmdCheckResponseCRC | (uint32_t)kSDIF_CmdResponseExpect); - } - } - - if (command->type == (uint32_t)kCARD_CommandTypeAbort) - { - command->flags |= (uint32_t)kSDIF_TransferStopAbort; - } - - /* wait pre-transfer complete */ - command->flags |= (uint32_t)kSDIF_WaitPreTransferComplete | (uint32_t)kSDIF_CmdDataUseHoldReg; - - /* handle interrupt and status mask */ - if (data != NULL) - { - SDIF_ClearInterruptStatus(base, (uint32_t)kSDIF_AllInterruptStatus); - if (enDMA) - { - SDIF_ClearInternalDMAStatus(base, kSDIF_DMAAllStatus); - SDIF_EnableDmaInterrupt(base, kSDIF_DMAAllStatus); - SDIF_EnableInterrupt(base, (uint32_t)kSDIF_CommandTransferStatus); - } - else - { - SDIF_EnableInterrupt(base, (uint32_t)kSDIF_CommandTransferStatus | (uint32_t)kSDIF_DataTransferStatus); - } - } - else - { - SDIF_ClearInterruptStatus(base, kSDIF_CommandTransferStatus); - SDIF_EnableInterrupt(base, kSDIF_CommandTransferStatus); - } - - return kStatus_Success; -} - -static status_t SDIF_ReadCommandResponse(SDIF_Type *base, sdif_command_t *command) -{ - /* check if command exist,if not, do not read the response */ - if (NULL != command) - { - /* read response */ - command->response[0U] = base->RESP[0U]; - if (command->responseType == (uint32_t)kCARD_ResponseTypeR2) - { - command->response[1U] = base->RESP[1U]; - command->response[2U] = base->RESP[2U]; - command->response[3U] = base->RESP[3U]; - } - - if ((command->responseErrorFlags != 0U) && ((command->responseType == (uint32_t)kCARD_ResponseTypeR1) || - (command->responseType == (uint32_t)kCARD_ResponseTypeR1b) || - (command->responseType == (uint32_t)kCARD_ResponseTypeR6) || - (command->responseType == (uint32_t)kCARD_ResponseTypeR5))) - { - if (((command->responseErrorFlags) & (command->response[0U])) != 0UL) - { - return kStatus_SDIF_ResponseError; - } - } - } - - return kStatus_Success; -} - -static status_t SDIF_WaitCommandDone(SDIF_Type *base, sdif_command_t *command) -{ - uint32_t status = 0U; - uint32_t errorStatus = (uint32_t)kSDIF_ResponseError | (uint32_t)kSDIF_ResponseTimeout | - (uint32_t)kSDIF_DataStartBitError | (uint32_t)kSDIF_HardwareLockError | - (uint32_t)kSDIF_ResponseCRCError; - - do - { - status = SDIF_GetInterruptStatus(base); - } while ((status & (errorStatus | (uint32_t)kSDIF_CommandDone)) == 0UL); - /* clear interrupt status flag first */ - SDIF_ClearInterruptStatus(base, status & (uint32_t)kSDIF_CommandTransferStatus); - if ((status & errorStatus) != 0UL) - { - return kStatus_SDIF_SendCmdFail; - } - else - { - return SDIF_ReadCommandResponse(base, command); - } -} - -static status_t SDIF_SetCommandRegister(SDIF_Type *base, uint32_t cmdIndex, uint32_t argument, uint32_t timeout) -{ - uint32_t syncTimeout = timeout; - - base->CMDARG = argument; - base->CMD = cmdIndex | SDIF_CMD_START_CMD_MASK; - - while ((base->CMD & SDIF_CMD_START_CMD_MASK) == SDIF_CMD_START_CMD_MASK) - { - if (timeout == 0U) - { - break; - } - - if (0UL == syncTimeout) - { - return kStatus_SDIF_SyncCmdTimeout; - } - - --syncTimeout; - } - - return kStatus_Success; -} - -/*! - * brief SDIF release the DMA descriptor to DMA engine - * this function should be called when DMA descriptor unavailable status occurs - * param base SDIF peripheral base address. - * param sdif DMA config pointer - */ -status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig) -{ - assert(NULL != dmaConfig); - assert(NULL != dmaConfig->dmaDesBufferStartAddr); - - sdif_dma_descriptor_t *dmaDesAddr; - uint32_t *tempDMADesBuffer = dmaConfig->dmaDesBufferStartAddr; - uint32_t dmaDesBufferSize = 0UL; - - dmaDesAddr = (sdif_dma_descriptor_t *)(uint32_t)tempDMADesBuffer; - - /* chain descriptor mode */ - if (dmaConfig->mode == kSDIF_ChainDMAMode) - { - while (((dmaDesAddr->dmaDesAttribute & SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG) != - SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG) && - (dmaDesBufferSize < dmaConfig->dmaDesBufferLen * sizeof(uint32_t))) - { - /* set the OWN bit */ - dmaDesAddr->dmaDesAttribute |= SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG; - dmaDesAddr++; - dmaDesBufferSize += sizeof(sdif_dma_descriptor_t); - } - /* if access dma des address overflow, return fail */ - if (dmaDesBufferSize > dmaConfig->dmaDesBufferLen * sizeof(uint32_t)) - { - return kStatus_Fail; - } - dmaDesAddr->dmaDesAttribute |= SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG; - } - /* dual descriptor mode */ - else - { - while (((dmaDesAddr->dmaDesAttribute & SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG) != - SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG) && - (dmaDesBufferSize < dmaConfig->dmaDesBufferLen * sizeof(uint32_t))) - { - dmaDesAddr = (sdif_dma_descriptor_t *)(uint32_t)tempDMADesBuffer; - dmaDesAddr->dmaDesAttribute |= SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG; - tempDMADesBuffer += dmaConfig->dmaDesSkipLen; - } - /* if access dma des address overflow, return fail */ - if (dmaDesBufferSize > dmaConfig->dmaDesBufferLen * sizeof(uint32_t)) - { - return kStatus_Fail; - } - dmaDesAddr->dmaDesAttribute |= SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG; - } - /* reload DMA descriptor */ - base->PLDMND = SDIF_POLL_DEMAND_VALUE; - - return kStatus_Success; -} - -static uint32_t SDIF_ReadDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords) -{ - uint32_t i; - uint32_t totalWords; - uint32_t wordsCanBeRead; /* The words can be read at this time. */ - uint32_t readWatermark = ((base->FIFOTH & SDIF_FIFOTH_RX_WMARK_MASK) >> SDIF_FIFOTH_RX_WMARK_SHIFT); - - if ((base->CTRL & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) == 0UL) - { - if (data->blockSize % sizeof(uint32_t) != 0U) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */ - if (readWatermark >= totalWords) - { - wordsCanBeRead = totalWords; - } - /* If watermark level is less than totalWords and left words to be sent is equal or bigger than readWatermark, - transfers watermark level words. */ - else if ((readWatermark < totalWords) && ((totalWords - transferredWords) >= readWatermark)) - { - wordsCanBeRead = readWatermark; - } - /* If watermark level is less than totalWords and left words to be sent is less than readWatermark, transfers - left - words. */ - else - { - wordsCanBeRead = (totalWords - transferredWords); - } - - i = 0U; - while (i < wordsCanBeRead) - { - data->rxData[transferredWords++] = base->FIFO[i]; - i++; - } - } - - return transferredWords; -} - -static uint32_t SDIF_WriteDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords) -{ - uint32_t i; - uint32_t totalWords; - uint32_t wordsCanBeWrite; /* The words can be read at this time. */ - uint32_t writeWatermark = ((base->FIFOTH & SDIF_FIFOTH_TX_WMARK_MASK) >> SDIF_FIFOTH_TX_WMARK_SHIFT); - - if ((base->CTRL & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) == 0UL) - { - if (data->blockSize % sizeof(uint32_t) != 0U) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */ - if (writeWatermark >= totalWords) - { - wordsCanBeWrite = totalWords; - } - /* If watermark level is less than totalWords and left words to be sent is equal or bigger than writeWatermark, - transfers watermark level words. */ - else if ((writeWatermark < totalWords) && ((totalWords - transferredWords) >= writeWatermark)) - { - wordsCanBeWrite = writeWatermark; - } - /* If watermark level is less than totalWords and left words to be sent is less than writeWatermark, transfers - left - words. */ - else - { - wordsCanBeWrite = (totalWords - transferredWords); - } - - i = 0U; - while (i < wordsCanBeWrite) - { - base->FIFO[i] = data->txData[transferredWords++]; - i++; - } - } - - return transferredWords; -} - -static status_t SDIF_ReadDataPortBlocking(SDIF_Type *base, sdif_data_t *data) -{ - uint32_t totalWords; - uint32_t transferredWords = 0U; - status_t error = kStatus_Success; - uint32_t status; - bool transferOver = false; - - if (data->blockSize % sizeof(uint32_t) != 0UL) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - while ((transferredWords < totalWords) && (error == kStatus_Success)) - { - /* wait data transfer complete or reach RX watermark */ - do - { - status = SDIF_GetInterruptStatus(base); - if (IS_SDIF_FLAG_SET(status, kSDIF_DataTransferError)) - { - if (!(data->enableIgnoreError)) - { - error = kStatus_Fail; - break; - } - } - } while (!IS_SDIF_FLAG_SET(status, ((uint32_t)kSDIF_DataTransferOver | (uint32_t)kSDIF_ReadFIFORequest)) && - (!transferOver)); - - if (IS_SDIF_FLAG_SET(status, kSDIF_DataTransferOver)) - { - transferOver = true; - } - - if (error == kStatus_Success) - { - transferredWords = SDIF_ReadDataPort(base, data, transferredWords); - } - - /* clear interrupt status */ - SDIF_ClearInterruptStatus(base, status); - } - - return error; -} - -static status_t SDIF_WriteDataPortBlocking(SDIF_Type *base, sdif_data_t *data) -{ - uint32_t totalWords; - uint32_t transferredWords = 0U; - status_t error = kStatus_Success; - uint32_t status; - - if (data->blockSize % sizeof(uint32_t) != 0UL) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - while ((transferredWords < totalWords) && (error == kStatus_Success)) - { - /* wait data transfer complete or reach RX watermark */ - do - { - status = SDIF_GetInterruptStatus(base); - if (IS_SDIF_FLAG_SET(status, kSDIF_DataTransferError)) - { - if (!(data->enableIgnoreError)) - { - error = kStatus_Fail; - } - } - } while (!(IS_SDIF_FLAG_SET(status, kSDIF_WriteFIFORequest))); - - if (error == kStatus_Success) - { - transferredWords = SDIF_WriteDataPort(base, data, transferredWords); - } - - /* clear interrupt status */ - SDIF_ClearInterruptStatus(base, status); - } - - while ((SDIF_GetInterruptStatus(base) & (uint32_t)kSDIF_DataTransferOver) != (uint32_t)kSDIF_DataTransferOver) - { - } - - if (IS_SDIF_FLAG_SET(SDIF_GetInterruptStatus(base), kSDIF_DataTransferError)) - { - if (!(data->enableIgnoreError)) - { - error = kStatus_Fail; - } - } - SDIF_ClearInterruptStatus(base, ((uint32_t)kSDIF_DataTransferOver | (uint32_t)kSDIF_DataTransferError)); - - return error; -} - -/*! - * brief reset the different block of the interface. - * param base SDIF peripheral base address. - * param mask indicate which block to reset. - * param timeout value,set to wait the bit self clear - * return reset result. - */ -bool SDIF_Reset(SDIF_Type *base, uint32_t mask, uint32_t timeout) -{ - /* reset through CTRL */ - base->CTRL |= mask; - /* DMA software reset */ - if (IS_SDIF_FLAG_SET(mask, kSDIF_ResetDMAInterface)) - { - /* disable DMA first then do DMA software reset */ - base->BMOD = (base->BMOD & (~SDIF_BMOD_DE_MASK)) | SDIF_BMOD_SWR_MASK; - } - - /* check software DMA reset here for DMA reset also need to check this bit */ - while ((base->CTRL & mask) != 0UL) - { - if (0UL == timeout) - { - break; - } - timeout--; - } - - return timeout != 0UL ? true : false; -} - -static status_t SDIF_TransferDataBlocking(SDIF_Type *base, sdif_data_t *data, bool isDMA) -{ - assert(NULL != data); - - uint32_t dmaStatus = 0UL; - status_t error = kStatus_Success; - - /* in DMA mode, only need to wait the complete flag and check error */ - if (isDMA) - { - do - { - dmaStatus = SDIF_GetInternalDMAStatus(base); - if (IS_SDIF_FLAG_SET(dmaStatus, (uint32_t)kSDIF_DMAFatalBusError)) - { - SDIF_ClearInternalDMAStatus( - base, (uint32_t)kSDIF_DMAFatalBusError | (uint32_t)kSDIF_AbnormalInterruptSummary); - error = kStatus_SDIF_DMATransferFailWithFBE; /* in this condition,need reset */ - } - /* Card error summary, include EBE,SBE,Data CRC,RTO,DRTO,Response error */ - if (IS_SDIF_FLAG_SET(dmaStatus, (uint32_t)kSDIF_DMACardErrorSummary)) - { - SDIF_ClearInternalDMAStatus( - base, (uint32_t)kSDIF_DMACardErrorSummary | (uint32_t)kSDIF_AbnormalInterruptSummary); - if (!(data->enableIgnoreError)) - { - error = kStatus_SDIF_DataTransferFail; - } - - /* if error occur, then return */ - break; - } - } while (!(IS_SDIF_FLAG_SET( - dmaStatus, ((uint32_t)kSDIF_DMATransFinishOneDescriptor | (uint32_t)kSDIF_DMARecvFinishOneDescriptor)))); - - /* clear the corresponding status bit */ - SDIF_ClearInternalDMAStatus( - base, ((uint32_t)kSDIF_DMATransFinishOneDescriptor | (uint32_t)kSDIF_DMARecvFinishOneDescriptor | - (uint32_t)kSDIF_NormalInterruptSummary)); - - SDIF_ClearInterruptStatus(base, SDIF_GetInterruptStatus(base)); - - if (error != kStatus_Success) - { - return kStatus_SDIF_DataTransferFail; - } - } - else - { - if (data->rxData != NULL) - { - error = SDIF_ReadDataPortBlocking(base, data); - if (error != kStatus_Success) - { - return kStatus_SDIF_DataTransferFail; - } - } - else - { - error = SDIF_WriteDataPortBlocking(base, data); - if (error != kStatus_Success) - { - return kStatus_SDIF_DataTransferFail; - } - } - } - - return kStatus_Success; -} - -/*! - * brief send command to the card - * - * This api include polling the status of the bit START_COMMAND, if 0 used as timeout value, then this function - * will return directly without polling the START_CMD status. - * param base SDIF peripheral base address. - * param command configuration collection. - * param timeout the timeout value of polling START_CMD auto clear status. - * return command excute status - */ -status_t SDIF_SendCommand(SDIF_Type *base, sdif_command_t *cmd, uint32_t timeout) -{ - assert(NULL != cmd); - - return SDIF_SetCommandRegister(base, SDIF_CMD_CMD_INDEX(cmd->index) | (cmd->flags & (~SDIF_CMD_CMD_INDEX_MASK)), - cmd->argument, timeout); -} - -/*! - * brief SDIF send initialize 80 clocks for SD card after initial - * param base SDIF peripheral base address. - * param timeout value - */ -bool SDIF_SendCardActive(SDIF_Type *base, uint32_t timeout) -{ - bool enINT = false; - - /* add for conflict with interrupt mode,close the interrupt temporary */ - if ((base->CTRL & SDIF_CTRL_INT_ENABLE_MASK) == SDIF_CTRL_INT_ENABLE_MASK) - { - enINT = true; - base->CTRL &= ~SDIF_CTRL_INT_ENABLE_MASK; - } - SDIF_ClearInterruptStatus(base, kSDIF_CommandDone); - SDIF_EnableInterrupt(base, kSDIF_CommandDone); - - /* send initialization command */ - if (SDIF_SetCommandRegister(base, SDIF_CMD_SEND_INITIALIZATION_MASK, 0UL, timeout) != kStatus_Success) - { - return false; - } - - /* wait command done */ - while ((SDIF_GetInterruptStatus(base) & (uint32_t)kSDIF_CommandDone) != (uint32_t)kSDIF_CommandDone) - { - } - - /* clear status */ - SDIF_ClearInterruptStatus(base, kSDIF_CommandDone); - SDIF_DisableInterrupt(base, kSDIF_CommandDone); - - /* add for conflict with interrupt mode */ - if (enINT) - { - base->CTRL |= SDIF_CTRL_INT_ENABLE_MASK; - } - - return true; -} - -/*! - * brief SDIF config the clock delay - * This function is used to config the cclk_in delay to - * sample and driver the data ,should meet the min setup - * time and hold time, and user need to config this parameter - * according to your board setting - * param target freq work mode - * param divider not used in this function anymore, use DELAY value instead of phase directly. - */ -void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider) -{ - uint32_t sdioClkCtrl = SYSCON->SDIOCLKCTRL; - - sdioClkCtrl = SYSCON->SDIOCLKCTRL & - (~(SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK | - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK)); - - if (target_HZ >= SDIF_CLOCK_RANGE_NEED_DELAY) - { -#ifdef SDIF_HIGHSPEED_SAMPLE_DELAY - sdioClkCtrl |= SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_HIGHSPEED_SAMPLE_DELAY); -#endif -#ifdef SDIF_HIGHSPEED_DRV_DELAY - sdioClkCtrl |= - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_HIGHSPEED_DRV_DELAY); -#endif - } - else - { -#if defined(SDIF_DEFAULT_MODE_SAMPLE_DELAY) - sdioClkCtrl |= SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_DEFAULT_MODE_SAMPLE_DELAY); -#endif -#if defined(SDIF_DEFAULT_MODE_DRV_DELAY) - sdioClkCtrl |= SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_DEFAULT_MODE_DRV_DELAY); -#endif - } - - SYSCON->SDIOCLKCTRL = sdioClkCtrl; -} - -static status_t SDIF_SyncClockCommand(SDIF_Type *base) -{ - uint32_t syncTimeout = 10000U; - uint32_t sendCommandRetry = 3U; - - do - { - /* update the clock register and wait the pre-transfer complete */ - if (SDIF_SetCommandRegister( - base, (uint32_t)kSDIF_CmdUpdateClockRegisterOnly | (uint32_t)kSDIF_WaitPreTransferComplete, 0UL, - syncTimeout) == kStatus_Success) - { - break; - } - /* if send clock command timeout, it means that polling START_CMD cleared failed, CIU cannot take command at - * this comment, so reset the host controller to recover the CIU interface and state machine. - */ - (void)SDIF_Reset(base, kSDIF_ResetController, syncTimeout); - sendCommandRetry--; - } while (sendCommandRetry != 0U); - - if (sendCommandRetry == 0U) - { - return kStatus_Fail; - } - - return kStatus_Success; -} - -/*! - * brief Sets the card bus clock frequency. - * - * param base SDIF peripheral base address. - * param srcClock_Hz SDIF source clock frequency united in Hz. - * param target_HZ card bus clock frequency united in Hz. - * return The nearest frequency of busClock_Hz configured to SD bus. - */ -uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t target_HZ) -{ - uint32_t divider = 0UL, targetFreq = target_HZ; - - /* if target freq bigger than the source clk, set the target_HZ to - src clk, this interface can run up to 52MHZ with card */ - if (srcClock_Hz < targetFreq) - { - targetFreq = srcClock_Hz; - } - - /* disable the clock first,need sync to CIU*/ - SDIF_EnableCardClock(base, false); - - if (SDIF_SyncClockCommand(base) != kStatus_Success) - { - return 0U; - } - - /*calculate the divider*/ - if (targetFreq != srcClock_Hz) - { - divider = srcClock_Hz / targetFreq; - while (srcClock_Hz / divider > targetFreq) - { - divider++; - } - - if (divider > (SDIF_CLKDIV_CLK_DIVIDER0_MASK * 2UL)) - { - /* Note: if assert occur here, it means that the source clock frequency is too high, the suggestion is - * reconfigure the SDIF divider in SYSCON to get a properly source clock */ - assert(false); - divider = (SDIF_CLKDIV_CLK_DIVIDER0_MASK * 2UL); - } - - divider = (divider + 1UL) / 2UL; - } - /* load the clock divider */ - base->CLKDIV = SDIF_CLKDIV_CLK_DIVIDER0(divider); - /* update the divider to CIU */ - if (SDIF_SyncClockCommand(base) != kStatus_Success) - { - return 0U; - } - - /* enable the card clock and sync to CIU */ - SDIF_EnableCardClock(base, true); - (void)SDIF_SyncClockCommand(base); - - /* config the clock delay to meet the hold time and setup time */ - SDIF_ConfigClockDelay(target_HZ, divider); - - /* return the actual card clock freq */ - return (divider != 0UL) ? (srcClock_Hz / (divider * 2UL)) : srcClock_Hz; -} - -/*! - * brief SDIF abort the read data when SDIF card is in suspend state - * Once assert this bit,data state machine will be reset which is waiting for the - * next blocking data,used in SDIO card suspend sequence,should call after suspend - * cmd send - * param base SDIF peripheral base address. - * param timeout value to wait this bit self clear which indicate the data machine - * reset to idle - */ -bool SDIF_AbortReadData(SDIF_Type *base, uint32_t timeout) -{ - /* assert this bit to reset the data machine to abort the read data */ - base->CTRL |= SDIF_CTRL_ABORT_READ_DATA_MASK; - /* polling the bit self clear */ - while ((base->CTRL & SDIF_CTRL_ABORT_READ_DATA_MASK) == SDIF_CTRL_ABORT_READ_DATA_MASK) - { - if (0UL == timeout) - { - break; - } - timeout--; - } - - return IS_SDIF_FLAG_SET(base->CTRL, SDIF_CTRL_ABORT_READ_DATA_MASK) ? false : true; -} - -/*! - * brief SDIF internal DMA config function - * param base SDIF peripheral base address. - * param internal DMA configuration collection - * param data buffer pointer - * param data buffer size - */ -status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, const uint32_t *data, uint32_t dataSize) -{ - assert(NULL != config); - assert(NULL != data); - - uint32_t dmaEntry = 0UL, i, dmaBufferSize = 0UL, dmaBuffer1Size = 0UL; - uint32_t *tempDMADesBuffer = config->dmaDesBufferStartAddr; - const uint32_t *dataBuffer = data; - sdif_dma_descriptor_t *descriptorPoniter = NULL; - uint32_t maxDMABuffer = (uint32_t)FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE * ((uint32_t)config->mode); - - if ((((uint32_t)data % SDIF_INTERNAL_DMA_ADDR_ALIGN) != 0UL) || - (((uint32_t)tempDMADesBuffer % SDIF_INTERNAL_DMA_ADDR_ALIGN) != 0UL)) - { - return kStatus_SDIF_DMAAddrNotAlign; - } - - /* check the read/write data size,must be a multiple of 4 */ - if (dataSize % sizeof(uint32_t) != 0UL) - { - dataSize += sizeof(uint32_t) - (dataSize % sizeof(uint32_t)); - } - - /*config the bus mode*/ - if (config->enableFixBurstLen) - { - base->BMOD |= SDIF_BMOD_FB_MASK; - } - - /* calculate the dma descriptor entry due to DMA buffer size limit */ - /* if data size smaller than one descriptor buffer size */ - if (dataSize > maxDMABuffer) - { - dmaEntry = dataSize / maxDMABuffer + ((dataSize % maxDMABuffer) != 0UL ? 1UL : 0UL); - } - else /* need one dma descriptor */ - { - dmaEntry = 1UL; - } - - /* check the DMA descriptor buffer len one more time,it is user's responsibility to make sure the DMA descriptor - table - size is bigger enough to hold the transfer descriptor */ - if (config->dmaDesBufferLen * sizeof(uint32_t) < (dmaEntry * sizeof(sdif_dma_descriptor_t) + config->dmaDesSkipLen)) - { - return kStatus_SDIF_DescriptorBufferLenError; - } - - if (config->mode == kSDIF_DualDMAMode) - { - base->BMOD |= SDIF_BMOD_DSL(config->dmaDesSkipLen); /* config the distance between the DMA descriptor */ - for (i = 0UL; i < dmaEntry; i++) - { - if (dataSize > (uint32_t)FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE) - { - dmaBufferSize = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE; - dataSize -= dmaBufferSize; - dmaBuffer1Size = dataSize > (uint32_t)FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE ? - (uint32_t)FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE : - dataSize; - dataSize -= dmaBuffer1Size; - } - else - { - dmaBufferSize = dataSize; - dmaBuffer1Size = 0UL; - } - - descriptorPoniter = (sdif_dma_descriptor_t *)(uint32_t)tempDMADesBuffer; - if (i == 0UL) - { - descriptorPoniter->dmaDesAttribute = SDIF_DMA_DESCRIPTOR_DATA_BUFFER_START_FLAG | - SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG | - SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; - } - else - { - descriptorPoniter->dmaDesAttribute = - SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG | SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; - } - descriptorPoniter->dmaDataBufferSize = - SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(dmaBufferSize) | SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(dmaBuffer1Size); - - descriptorPoniter->dmaDataBufferAddr0 = dataBuffer; - descriptorPoniter->dmaDataBufferAddr1 = dataBuffer + dmaBufferSize / sizeof(uint32_t); - dataBuffer += (dmaBufferSize + dmaBuffer1Size) / sizeof(uint32_t); - - /* descriptor skip length */ - tempDMADesBuffer += config->dmaDesSkipLen + sizeof(sdif_dma_descriptor_t) / sizeof(uint32_t); - } - /* enable the completion interrupt when reach the last descriptor */ - descriptorPoniter->dmaDesAttribute &= ~SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; - descriptorPoniter->dmaDesAttribute |= - SDIF_DMA_DESCRIPTOR_DATA_BUFFER_END_FLAG | SDIF_DMA_DESCRIPTOR_DESCRIPTOR_END_FLAG; - } - else - { - for (i = 0UL; i < dmaEntry; i++) - { - if (dataSize > (uint32_t)FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE) - { - dmaBufferSize = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE; - dataSize -= (uint32_t)FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE; - } - else - { - dmaBufferSize = dataSize; - } - - descriptorPoniter = (sdif_dma_descriptor_t *)(uint32_t)tempDMADesBuffer; - if (i == 0UL) - { - descriptorPoniter->dmaDesAttribute = - SDIF_DMA_DESCRIPTOR_DATA_BUFFER_START_FLAG | SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG | - SDIF_DMA_DESCRIPTOR_SECOND_ADDR_CHAIN_FLAG | SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; - } - else - { - descriptorPoniter->dmaDesAttribute = SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG | - SDIF_DMA_DESCRIPTOR_SECOND_ADDR_CHAIN_FLAG | - SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; - } - descriptorPoniter->dmaDataBufferSize = - SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(dmaBufferSize); /* use only buffer 1 for data buffer*/ - descriptorPoniter->dmaDataBufferAddr0 = dataBuffer; - dataBuffer += dmaBufferSize / sizeof(uint32_t); - tempDMADesBuffer += - sizeof(sdif_dma_descriptor_t) / sizeof(uint32_t); /* calculate the next descriptor address */ - /* this descriptor buffer2 pointer to the next descriptor address */ - descriptorPoniter->dmaDataBufferAddr1 = tempDMADesBuffer; - } - /* enable the completion interrupt when reach the last descriptor */ - descriptorPoniter->dmaDesAttribute &= ~SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; - descriptorPoniter->dmaDesAttribute |= SDIF_DMA_DESCRIPTOR_DATA_BUFFER_END_FLAG; - } - - /* use internal DMA interface */ - base->CTRL |= SDIF_CTRL_USE_INTERNAL_DMAC_MASK; - /* enable the internal SD/MMC DMA */ - base->BMOD |= SDIF_BMOD_DE_MASK; - /* load DMA descriptor buffer address */ - base->DBADDR = (uint32_t)config->dmaDesBufferStartAddr; - - return kStatus_Success; -} - -#if defined(FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD) && FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD -/*! - * brief set card data bus width - * param base SDIF peripheral base address. - * param data bus width type - */ -void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type) -{ - if (type == kSDIF_Bus1BitWidth) - { - base->CTYPE &= ~(SDIF_CTYPE_CARD0_WIDTH0_MASK | SDIF_CTYPE_CARD0_WIDTH1_MASK); - } - else if (type == kSDIF_Bus4BitWidth) - { - base->CTYPE = (base->CTYPE & (~SDIF_CTYPE_CARD0_WIDTH1_MASK)) | SDIF_CTYPE_CARD0_WIDTH0_MASK; - } - else - { - base->CTYPE |= SDIF_CTYPE_CARD0_WIDTH1_MASK; - } -} - -/*! - * brief set card1 data bus width - * param base SDIF peripheral base address. - * param data bus width type - */ -void SDIF_SetCard1BusWidth(SDIF_Type *base, sdif_bus_width_t type) -{ - if (type == kSDIF_Bus1BitWidth) - { - base->CTYPE &= ~(SDIF_CTYPE_CARD1_WIDTH0_MASK | SDIF_CTYPE_CARD1_WIDTH1_MASK); - } - else if (type == kSDIF_Bus4BitWidth) - { - base->CTYPE = (base->CTYPE & (~SDIF_CTYPE_CARD1_WIDTH1_MASK)) | SDIF_CTYPE_CARD1_WIDTH0_MASK; - } - else - { - base->CTYPE |= SDIF_CTYPE_CARD1_WIDTH1_MASK; - } -} -#else -/*! - * brief set card data bus width - * param base SDIF peripheral base address. - * param data bus width type - */ -void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type) -{ - if (type == kSDIF_Bus1BitWidth) - { - base->CTYPE &= ~(SDIF_CTYPE_CARD_WIDTH0_MASK | SDIF_CTYPE_CARD_WIDTH1_MASK); - } - else if (type == kSDIF_Bus4BitWidth) - { - base->CTYPE = (base->CTYPE & (~SDIF_CTYPE_CARD_WIDTH1_MASK)) | SDIF_CTYPE_CARD_WIDTH0_MASK; - } - else - { - base->CTYPE |= SDIF_CTYPE_CARD_WIDTH1_MASK; - } -} -#endif - -/*! - * brief SDIF module initialization function. - * - * Configures the SDIF according to the user configuration. - * param base SDIF peripheral base address. - * param config SDIF configuration information. - */ -void SDIF_Init(SDIF_Type *base, sdif_config_t *config) -{ - assert(NULL != config); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Sdio); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kSDIO_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - - /*config timeout register */ - base->TMOUT = ((base->TMOUT) & ~(SDIF_TMOUT_RESPONSE_TIMEOUT_MASK | SDIF_TMOUT_DATA_TIMEOUT_MASK)) | - SDIF_TMOUT_RESPONSE_TIMEOUT(config->responseTimeout) | SDIF_TMOUT_DATA_TIMEOUT(config->dataTimeout); - - /* config the card detect debounce clock count */ - base->DEBNCE = SDIF_DEBNCE_DEBOUNCE_COUNT(config->cardDetDebounce_Clock); - - /*config the watermark/burst transfer value */ - base->FIFOTH = - SDIF_FIFOTH_TX_WMARK(SDIF_TX_WATERMARK) | SDIF_FIFOTH_RX_WMARK(SDIF_RX_WATERMARK) | SDIF_FIFOTH_DMA_MTS(1U); - - /* disable all the interrupt */ - SDIF_DisableInterrupt(base, kSDIF_AllInterruptStatus); - - /* clear all interrupt/DMA status */ - SDIF_ClearInterruptStatus(base, kSDIF_AllInterruptStatus); - SDIF_ClearInternalDMAStatus(base, kSDIF_DMAAllStatus); -} - -/*! - * brief SDIF transfer function data/cmd in a blocking way - * param base SDIF peripheral base address. - * param DMA config structure - * 1. NULL - * In this condition, polling transfer mode is selected - * 2. avaliable DMA config - * In this condition, DMA transfer mode is selected - * param sdif transfer configuration collection - */ -status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sdif_transfer_t *transfer) -{ - assert(NULL != transfer); - - bool enDMA = true; - sdif_data_t *data = transfer->data; - status_t error = kStatus_Fail; - - /* if need transfer data in dma mode, config the DMA descriptor first */ - if ((data != NULL) && (dmaConfig != NULL)) - { - if ((error = SDIF_InternalDMAConfig(base, dmaConfig, data->rxData != NULL ? data->rxData : data->txData, - data->blockSize * data->blockCount)) == - kStatus_SDIF_DescriptorBufferLenError) - { - return kStatus_SDIF_DescriptorBufferLenError; - } - /* if DMA descriptor address or data buffer address not align with SDIF_INTERNAL_DMA_ADDR_ALIGN, switch to - polling transfer mode, disable the internal DMA */ - if (error == kStatus_SDIF_DMAAddrNotAlign) - { - enDMA = false; - } - } - else - { - enDMA = false; - } - - if (!enDMA) - { - SDIF_EnableInternalDMA(base, false); - } - - /* config the transfer parameter */ - if (SDIF_TransferConfig(base, transfer, enDMA) != kStatus_Success) - { - return kStatus_SDIF_InvalidArgument; - } - - /* send command first, do not wait start bit auto cleared, command done bit should wait while sending normal command - */ - if (SDIF_SendCommand(base, transfer->command, 0UL) != kStatus_Success) - { - return kStatus_SDIF_SendCmdFail; - } - - if (SDIF_WaitCommandDone(base, transfer->command) != kStatus_Success) - { - return kStatus_SDIF_SendCmdFail; - } - /* if use DMA transfer mode ,check the corresponding status bit */ - if (data != NULL) - { - /* handle data transfer */ - error = SDIF_TransferDataBlocking(base, data, enDMA); - if (error != kStatus_Success) - { - return kStatus_SDIF_DataTransferFail; - } - } - - return kStatus_Success; -} - -/*! - * brief SDIF transfer function data/cmd in a non-blocking way - * this API should be use in interrupt mode, when use this API user - * must call SDIF_TransferCreateHandle first, all status check through - * interrupt - * param base SDIF peripheral base address. - * param sdif handle - * param DMA config structure - * This parameter can be config as: - * 1. NULL - In this condition, polling transfer mode is selected - 2. avaliable DMA config - In this condition, DMA transfer mode is selected - * param sdif transfer configuration collection - */ -status_t SDIF_TransferNonBlocking(SDIF_Type *base, - sdif_handle_t *handle, - sdif_dma_config_t *dmaConfig, - sdif_transfer_t *transfer) -{ - assert(NULL != transfer); - - sdif_data_t *data = transfer->data; - status_t error = kStatus_Fail; - bool enDMA = true; - - /* save the data and command before transfer */ - handle->data = transfer->data; - handle->command = transfer->command; - handle->transferredWords = 0U; - - if ((data != NULL) && (dmaConfig != NULL)) - { - /* use internal DMA mode to transfer between the card and host*/ - if ((error = SDIF_InternalDMAConfig(base, dmaConfig, data->rxData != NULL ? data->rxData : data->txData, - data->blockSize * data->blockCount)) == - kStatus_SDIF_DescriptorBufferLenError) - { - return kStatus_SDIF_DescriptorBufferLenError; - } - /* if DMA descriptor address or data buffer address not align with SDIF_INTERNAL_DMA_ADDR_ALIGN, switch to - polling transfer mode, disable the internal DMA */ - if (error == kStatus_SDIF_DMAAddrNotAlign) - { - enDMA = false; - } - } - else - { - enDMA = false; - } - - if (!enDMA) - { - SDIF_EnableInternalDMA(base, false); - } - - /* config the transfer parameter */ - if (SDIF_TransferConfig(base, transfer, enDMA) != kStatus_Success) - { - return kStatus_SDIF_InvalidArgument; - } - - /* send command first, do not wait start bit auto cleared, command done bit should wait while sending normal command - */ - return SDIF_SendCommand(base, transfer->command, 0UL); -} - -/*! - * brief Creates the SDIF handle. - * register call back function for interrupt and enable the interrupt - * param base SDIF peripheral base address. - * param handle SDIF handle pointer. - * param callback Structure pointer to contain all callback functions. - * param userData Callback function parameter. - */ -void SDIF_TransferCreateHandle(SDIF_Type *base, - sdif_handle_t *handle, - sdif_transfer_callback_t *callback, - void *userData) -{ - assert(handle != NULL); - assert(callback != NULL); - - /* reset the handle. */ - (void)memset(handle, 0, sizeof(*handle)); - - /* Set the callback. */ - handle->callback.SDIOInterrupt = callback->SDIOInterrupt; - handle->callback.DMADesUnavailable = callback->DMADesUnavailable; - handle->callback.CommandReload = callback->CommandReload; - handle->callback.TransferComplete = callback->TransferComplete; - handle->callback.cardInserted = callback->cardInserted; - handle->callback.cardRemoved = callback->cardRemoved; - handle->userData = userData; - - /* Save the handle in global variables to support the double weak mechanism. */ - s_sdifHandle[SDIF_GetInstance(base)] = handle; - - /* save IRQ handler */ - s_sdifIsr = SDIF_TransferHandleIRQ; - - /* enable the global interrupt */ - SDIF_EnableGlobalInterrupt(base, true); - - (void)EnableIRQ(s_sdifIRQ[SDIF_GetInstance(base)]); -} - -/*! - * brief SDIF return the controller capability - * param base SDIF peripheral base address. - * param sdif capability pointer - */ -void SDIF_GetCapability(SDIF_Type *base, sdif_capability_t *capability) -{ - assert(NULL != capability); - - /* Initializes the configure structure to zero. */ - (void)memset(capability, 0, sizeof(*capability)); - - capability->sdVersion = SDIF_SUPPORT_SD_VERSION; - capability->mmcVersion = SDIF_SUPPORT_MMC_VERSION; - capability->maxBlockLength = SDIF_BLKSIZ_BLOCK_SIZE_MASK; - /* set the max block count = max byte count / max block size */ - capability->maxBlockCount = SDIF_BYTCNT_BYTE_COUNT_MASK / SDIF_BLKSIZ_BLOCK_SIZE_MASK; - capability->flags = (uint32_t)kSDIF_SupportHighSpeedFlag | (uint32_t)kSDIF_SupportDmaFlag | - (uint32_t)kSDIF_SupportSuspendResumeFlag | (uint32_t)kSDIF_SupportV330Flag | - (uint32_t)kSDIF_Support4BitFlag | (uint32_t)kSDIF_Support8BitFlag; -} - -static void SDIF_TransferHandleCommand(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags) -{ - assert(handle->command != NULL); - - /* cmd buffer full, in this condition user need re-send the command */ - if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_HardwareLockError)) - { - if (handle->callback.CommandReload != NULL) - { - handle->callback.CommandReload(base, handle->userData); - } - } - /* transfer command done */ - else - { - if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_CommandDone)) - { - /* transfer error */ - if ((IS_SDIF_FLAG_SET(interruptFlags, ((uint32_t)kSDIF_ResponseError | (uint32_t)kSDIF_ResponseCRCError | - (uint32_t)kSDIF_ResponseTimeout))) || - (SDIF_ReadCommandResponse(base, handle->command) != kStatus_Success)) - { - if (handle->callback.TransferComplete != NULL) - { - handle->callback.TransferComplete(base, handle, kStatus_SDIF_SendCmdFail, handle->userData); - } - } - else - { - if (handle->callback.TransferComplete != NULL) - { - handle->callback.TransferComplete(base, handle, kStatus_SDIF_SendCmdSuccess, handle->userData); - } - } - } - } - - SDIF_DisableInterrupt(base, kSDIF_CommandTransferStatus); - handle->command = NULL; -} - -static void SDIF_TransferHandleData(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags) -{ - assert(handle->data != NULL); - - status_t transferStatus = kStatus_SDIF_BusyTransferring; - uint32_t transferredWords = handle->transferredWords; - - /* data starvation by host time out, software should read/write FIFO*/ - if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_DataStarvationByHostTimeout)) - { - if (handle->data->rxData != NULL) - { - handle->transferredWords = SDIF_ReadDataPort(base, handle->data, transferredWords); - } - else if (handle->data->txData != NULL) - { - handle->transferredWords = SDIF_WriteDataPort(base, handle->data, transferredWords); - } - else - { - transferStatus = kStatus_SDIF_DataTransferFail; - } - } - /* data transfer fail */ - else if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_DataTransferError)) - { - if (!handle->data->enableIgnoreError) - { - transferStatus = kStatus_SDIF_DataTransferFail; - } - else - { - transferStatus = kStatus_SDIF_DataTransferSuccess; - } - } - /* need fill data to FIFO */ - else if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_WriteFIFORequest)) - { - handle->transferredWords = SDIF_WriteDataPort(base, handle->data, transferredWords); - } - /* need read data from FIFO */ - else if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_ReadFIFORequest)) - { - handle->transferredWords = SDIF_ReadDataPort(base, handle->data, transferredWords); - } - else - { - /* Intentional empty */ - } - - /* data transfer over */ - if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_DataTransferOver)) - { - while ((handle->data->rxData != NULL) && ((base->STATUS & SDIF_STATUS_FIFO_COUNT_MASK) != 0UL)) - { - handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords); - } - transferStatus = kStatus_SDIF_DataTransferSuccess; - } - - if ((handle->callback.TransferComplete != NULL) && (transferStatus != kStatus_SDIF_BusyTransferring)) - { - handle->callback.TransferComplete(base, handle, transferStatus, handle->userData); - handle->data = NULL; - } -} - -static void SDIF_TransferHandleDMA(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags) -{ - status_t transferStatus = kStatus_SDIF_DataTransferFail; - - if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_DMAFatalBusError)) - { - transferStatus = kStatus_SDIF_DMATransferFailWithFBE; - } - else if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_DMADescriptorUnavailable)) - { - if (handle->callback.DMADesUnavailable != NULL) - { - handle->callback.DMADesUnavailable(base, handle->userData); - } - } - else if (IS_SDIF_FLAG_SET(interruptFlags, - ((uint32_t)kSDIF_AbnormalInterruptSummary | (uint32_t)kSDIF_DMACardErrorSummary)) && - (!handle->data->enableIgnoreError)) - { - transferStatus = kStatus_SDIF_DataTransferFail; - } - /* card normal summary */ - else - { - transferStatus = kStatus_SDIF_DataTransferSuccess; - } - - if (handle->callback.TransferComplete != NULL) - { - handle->callback.TransferComplete(base, handle, transferStatus, handle->userData); - handle->data = NULL; - } - - SDIF_DisableDmaInterrupt(base, kSDIF_DMAAllStatus); -} - -static void SDIF_TransferHandleSDIOInterrupt(SDIF_Type *base, sdif_handle_t *handle) -{ - if (handle->callback.SDIOInterrupt != NULL) - { - handle->callback.SDIOInterrupt(base, handle->userData); - } -} - -static void SDIF_TransferHandleCardDetect(SDIF_Type *base, sdif_handle_t *handle) -{ - if (SDIF_DetectCardInsert(base, false) == 1UL) - { - if ((handle->callback.cardInserted) != NULL) - { - handle->callback.cardInserted(base, handle->userData); - } - } - else - { - if ((handle->callback.cardRemoved) != NULL) - { - handle->callback.cardRemoved(base, handle->userData); - } - } -} - -static void SDIF_TransferHandleIRQ(SDIF_Type *base, sdif_handle_t *handle) -{ - assert(handle != NULL); - - uint32_t interruptFlags, dmaInterruptFlags; - - interruptFlags = SDIF_GetEnabledInterruptStatus(base); - dmaInterruptFlags = SDIF_GetEnabledDMAInterruptStatus(base); - - if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_CommandTransferStatus)) - { - SDIF_TransferHandleCommand(base, handle, interruptFlags); - } - if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_DataTransferStatus)) - { - SDIF_TransferHandleData(base, handle, interruptFlags); - } - if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_SDIOInterrupt)) - { - SDIF_TransferHandleSDIOInterrupt(base, handle); - } - if (IS_SDIF_FLAG_SET(dmaInterruptFlags, kSDIF_DMAAllStatus)) - { - SDIF_TransferHandleDMA(base, handle, dmaInterruptFlags); - } - if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_CardDetect)) - { - SDIF_TransferHandleCardDetect(base, handle); - } - - SDIF_ClearInterruptStatus(base, interruptFlags); - SDIF_ClearInternalDMAStatus(base, dmaInterruptFlags); -} - -/*! - * brief SDIF module deinit function. - * user should call this function follow with IP reset - * param base SDIF peripheral base address. - */ -void SDIF_Deinit(SDIF_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(kCLOCK_Sdio); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* disable the SDIOCLKCTRL */ - SYSCON->SDIOCLKCTRL &= ~(SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kSDIO_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -} - -#if defined(SDIF) -void SDIF_DriverIRQHandler(void); -void SDIF_DriverIRQHandler(void) -{ - assert(s_sdifHandle[0] != NULL); - - s_sdifIsr(SDIF, s_sdifHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sdif.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sdif.h deleted file mode 100644 index 9c1a7ea5b64..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sdif.h +++ /dev/null @@ -1,1035 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SDIF_H_ -#define _FSL_SDIF_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup sdif - * @{ - */ - -/********************************** - * Definitions. - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Driver version 2.0.15. */ -#define FSL_SDIF_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 0U)) -/*@}*/ - -/*! @brief SDIOCLKCTRL setting - * Below clock delay setting should depend on specific platform, so - * it can be redefined when timing mismatch issue occur. - * Such as: response error/CRC error and so on - */ -/*! @brief clock range value which need to add delay to avoid timing issue */ -#ifndef SDIF_CLOCK_RANGE_NEED_DELAY -#define SDIF_CLOCK_RANGE_NEED_DELAY (50000000U) -#endif - -/* - * Fixed delay configuration - * min hold time:2ns - * min setup time: 6ns - * delay = (x+1)*250ps - */ -/*! @brief High speed mode clk_sample fixed delay*/ -#ifndef SDIF_HIGHSPEED_SAMPLE_DELAY -#define SDIF_HIGHSPEED_SAMPLE_DELAY (12U) /*!< 12 * 250ps = 3ns */ -#endif -/*! @brief High speed mode clk_drv fixed delay */ -#ifndef SDIF_HIGHSPEED_DRV_DELAY -#define SDIF_HIGHSPEED_DRV_DELAY (31U) /*!< 31 * 250ps = 7.75ns */ -#endif - -/* - * Phase shift delay configuration - * 0 degree: no delay - * 90 degree: 0.25/source clk value - * 180 degree: 0.50/source clk value - * 270 degree: 0.75/source clk value - */ -/*! @brief High speed mode clk_sample phase shift */ -#ifndef SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT -#define SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT (0U) -#endif -/*! @brief High speed mode clk_drv phase shift */ -#ifndef SDIF_HIGHSPEED_DRV_PHASE_SHIFT -#define SDIF_HIGHSPEED_DRV_PHASE_SHIFT (1U) /* 90 degrees clk_drv phase delay */ -#endif -/*! @brief default mode sample fixed delay */ -#ifndef SDIF_DEFAULT_MODE_SAMPLE_DELAY -#define SDIF_DEFAULT_MODE_SAMPLE_DELAY (12U) /*!< 12 * 250ps = 3ns */ -#endif - -#ifndef SDIF_DEFAULT_MODE_DRV_DELAY -#define SDIF_DEFAULT_MODE_DRV_DELAY (31U) /*!< 31 * 250ps = 7.75ns */ -#endif - -/*! @brief SDIF internal DMA descriptor address and the data buffer address align */ -#define SDIF_INTERNAL_DMA_ADDR_ALIGN (4U) -/*! @brief SDIF DMA descriptor flag */ -#define SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG (1UL << 1U) -#define SDIF_DMA_DESCRIPTOR_DATA_BUFFER_END_FLAG (1UL << 2U) -#define SDIF_DMA_DESCRIPTOR_DATA_BUFFER_START_FLAG (1UL << 3U) -#define SDIF_DMA_DESCRIPTOR_SECOND_ADDR_CHAIN_FLAG (1UL << 4U) -#define SDIF_DMA_DESCRIPTOR_DESCRIPTOR_END_FLAG (1UL << 5U) -#define SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG (1UL << 31U) - -/*! @brief _sdif_status SDIF status */ -enum -{ - kStatus_SDIF_DescriptorBufferLenError = MAKE_STATUS(kStatusGroup_SDIF, 0U), /*!< Set DMA descriptor failed */ - kStatus_SDIF_InvalidArgument = MAKE_STATUS(kStatusGroup_SDIF, 1U), /*!< invalid argument status */ - kStatus_SDIF_SyncCmdTimeout = MAKE_STATUS(kStatusGroup_SDIF, 2U), /*!< sync command to CIU timeout status */ - kStatus_SDIF_SendCmdFail = MAKE_STATUS(kStatusGroup_SDIF, 3U), /*!< send command to card fail */ - kStatus_SDIF_SendCmdErrorBufferFull = - MAKE_STATUS(kStatusGroup_SDIF, 4U), /*!< send command to card fail, due to command buffer full - user need to resend this command */ - kStatus_SDIF_DMATransferFailWithFBE = - MAKE_STATUS(kStatusGroup_SDIF, 5U), /*!< DMA transfer data fail with fatal bus error , - to do with this error :issue a hard reset/controller reset*/ - kStatus_SDIF_DMATransferDescriptorUnavailable = - MAKE_STATUS(kStatusGroup_SDIF, 6U), /*!< DMA descriptor unavailable */ - kStatus_SDIF_DataTransferFail = MAKE_STATUS(kStatusGroup_SDIF, 6U), /*!< transfer data fail */ - kStatus_SDIF_ResponseError = MAKE_STATUS(kStatusGroup_SDIF, 7U), /*!< response error */ - kStatus_SDIF_DMAAddrNotAlign = MAKE_STATUS(kStatusGroup_SDIF, 8U), /*!< DMA address not align */ - kStatus_SDIF_BusyTransferring = MAKE_STATUS(kStatusGroup_SDIF, 9U), /*!< SDIF transfer busy status */ - kStatus_SDIF_DataTransferSuccess = MAKE_STATUS(kStatusGroup_SDIF, 10U), /*!< transfer data success */ - kStatus_SDIF_SendCmdSuccess = MAKE_STATUS(kStatusGroup_SDIF, 11U), /*!< transfer command success */ - -}; - -/*! @brief _sdif_capability_flag Host controller capabilities flag mask */ -enum -{ - kSDIF_SupportHighSpeedFlag = 0x1U, /*!< Support high-speed */ - kSDIF_SupportDmaFlag = 0x2U, /*!< Support DMA */ - kSDIF_SupportSuspendResumeFlag = 0x4U, /*!< Support suspend/resume */ - kSDIF_SupportV330Flag = 0x8U, /*!< Support voltage 3.3V */ - kSDIF_Support4BitFlag = 0x10U, /*!< Support 4 bit mode */ - kSDIF_Support8BitFlag = 0x20U, /*!< Support 8 bit mode */ -}; - -/*! @brief _sdif_reset_type define the reset type */ -enum -{ - kSDIF_ResetController = SDIF_CTRL_CONTROLLER_RESET_MASK, /*!< reset controller,will reset: BIU/CIU interface - CIU and state machine,ABORT_READ_DATA,SEND_IRQ_RESPONSE - and READ_WAIT bits of control register,START_CMD bit of - the command register*/ - kSDIF_ResetFIFO = SDIF_CTRL_FIFO_RESET_MASK, /*!< reset data FIFO*/ - kSDIF_ResetDMAInterface = SDIF_CTRL_DMA_RESET_MASK, /*!< reset DMA interface */ - - kSDIF_ResetAll = kSDIF_ResetController | kSDIF_ResetFIFO | /*!< reset all*/ - kSDIF_ResetDMAInterface, -}; - -/*! @brief define the card bus width type */ -typedef enum _sdif_bus_width -{ - kSDIF_Bus1BitWidth = 0U, /*!< 1bit bus width, 1bit mode and 4bit mode - share one register bit */ - kSDIF_Bus4BitWidth = 1U, /*!< 4bit mode mask */ - kSDIF_Bus8BitWidth = 2U, /*!< support 8 bit mode */ -} sdif_bus_width_t; - -/*! @brief _sdif_command_flags define the command flags */ -enum -{ - kSDIF_CmdResponseExpect = SDIF_CMD_RESPONSE_EXPECT_MASK, /*!< command request response*/ - kSDIF_CmdResponseLengthLong = SDIF_CMD_RESPONSE_LENGTH_MASK, /*!< command response length long */ - kSDIF_CmdCheckResponseCRC = SDIF_CMD_CHECK_RESPONSE_CRC_MASK, /*!< request check command response CRC*/ - kSDIF_DataExpect = SDIF_CMD_DATA_EXPECTED_MASK, /*!< request data transfer,either read/write*/ - kSDIF_DataWriteToCard = SDIF_CMD_READ_WRITE_MASK, /*!< data transfer direction */ - kSDIF_DataStreamTransfer = SDIF_CMD_TRANSFER_MODE_MASK, /*!< data transfer mode :stream/block transfer command */ - kSDIF_DataTransferAutoStop = SDIF_CMD_SEND_AUTO_STOP_MASK, /*!< data transfer with auto stop at the end of */ - kSDIF_WaitPreTransferComplete = - SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK, /*!< wait pre transfer complete before sending this cmd */ - kSDIF_TransferStopAbort = SDIF_CMD_STOP_ABORT_CMD_MASK, /*!< when host issue stop or abort cmd to stop data transfer - ,this bit should set so that cmd/data state-machines of CIU - can return to idle correctly*/ - kSDIF_SendInitialization = - SDIF_CMD_SEND_INITIALIZATION_MASK, /*!< send initialization 80 clocks for SD card after power on */ - kSDIF_CmdUpdateClockRegisterOnly = - SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK, /*!< send cmd update the CIU clock register only */ - kSDIF_CmdtoReadCEATADevice = SDIF_CMD_READ_CEATA_DEVICE_MASK, /*!< host is perform read access to CE-ATA device */ - kSDIF_CmdExpectCCS = SDIF_CMD_CCS_EXPECTED_MASK, /*!< command expect command completion signal signal */ - kSDIF_BootModeEnable = SDIF_CMD_ENABLE_BOOT_MASK, /*!< this bit should only be set for mandatory boot mode */ - kSDIF_BootModeExpectAck = SDIF_CMD_EXPECT_BOOT_ACK_MASK, /*!< boot mode expect ack */ - kSDIF_BootModeDisable = SDIF_CMD_DISABLE_BOOT_MASK, /*!< when software set this bit along with START_CMD, CIU - terminates the boot operation*/ - kSDIF_BootModeAlternate = SDIF_CMD_BOOT_MODE_MASK, /*!< select boot mode ,alternate or mandatory*/ - kSDIF_CmdVoltageSwitch = SDIF_CMD_VOLT_SWITCH_MASK, /*!< this bit set for CMD11 only */ - kSDIF_CmdDataUseHoldReg = SDIF_CMD_USE_HOLD_REG_MASK, /*!< cmd and data send to card through the HOLD register*/ -}; - -/*! @brief _sdif_command_type The command type */ -enum -{ - kCARD_CommandTypeNormal = 0U, /*!< Normal command */ - kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */ - kCARD_CommandTypeResume = 2U, /*!< Resume command */ - kCARD_CommandTypeAbort = 3U, /*!< Abort command */ -}; - -/*! - * @brief _sdif_response_type The command response type. - * - * Define the command response type from card to host controller. - */ -enum -{ - kCARD_ResponseTypeNone = 0U, /*!< Response type: none */ - kCARD_ResponseTypeR1 = 1U, /*!< Response type: R1 */ - kCARD_ResponseTypeR1b = 2U, /*!< Response type: R1b */ - kCARD_ResponseTypeR2 = 3U, /*!< Response type: R2 */ - kCARD_ResponseTypeR3 = 4U, /*!< Response type: R3 */ - kCARD_ResponseTypeR4 = 5U, /*!< Response type: R4 */ - kCARD_ResponseTypeR5 = 6U, /*!< Response type: R5 */ - kCARD_ResponseTypeR5b = 7U, /*!< Response type: R5b */ - kCARD_ResponseTypeR6 = 8U, /*!< Response type: R6 */ - kCARD_ResponseTypeR7 = 9U, /*!< Response type: R7 */ -}; - -/*! @brief _sdif_interrupt_mask define the interrupt mask flags */ -enum -{ - kSDIF_CardDetect = SDIF_INTMASK_CDET_MASK, /*!< mask for card detect */ - kSDIF_ResponseError = SDIF_INTMASK_RE_MASK, /*!< command response error */ - kSDIF_CommandDone = SDIF_INTMASK_CDONE_MASK, /*!< command transfer over*/ - kSDIF_DataTransferOver = SDIF_INTMASK_DTO_MASK, /*!< data transfer over flag*/ - kSDIF_WriteFIFORequest = SDIF_INTMASK_TXDR_MASK, /*!< write FIFO request */ - kSDIF_ReadFIFORequest = SDIF_INTMASK_RXDR_MASK, /*!< read FIFO request */ - kSDIF_ResponseCRCError = SDIF_INTMASK_RCRC_MASK, /*!< response CRC error */ - kSDIF_DataCRCError = SDIF_INTMASK_DCRC_MASK, /*!< data CRC error */ - kSDIF_ResponseTimeout = SDIF_INTMASK_RTO_MASK, /*!< response timeout */ - kSDIF_DataReadTimeout = SDIF_INTMASK_DRTO_MASK, /*!< read data timeout */ - kSDIF_DataStarvationByHostTimeout = SDIF_INTMASK_HTO_MASK, /*!< data starvation by host time out */ - kSDIF_FIFOError = SDIF_INTMASK_FRUN_MASK, /*!< indicate the FIFO under run or overrun error */ - kSDIF_HardwareLockError = SDIF_INTMASK_HLE_MASK, /*!< hardware lock write error */ - kSDIF_DataStartBitError = SDIF_INTMASK_SBE_MASK, /*!< start bit error */ - kSDIF_AutoCmdDone = SDIF_INTMASK_ACD_MASK, /*!< indicate the auto command done */ - kSDIF_DataEndBitError = SDIF_INTMASK_EBE_MASK, /*!< end bit error */ - kSDIF_SDIOInterrupt = SDIF_INTMASK_SDIO_INT_MASK_MASK, /*!< interrupt from the SDIO card */ - - kSDIF_CommandTransferStatus = kSDIF_ResponseError | kSDIF_CommandDone | kSDIF_ResponseCRCError | - kSDIF_ResponseTimeout | kSDIF_DataStartBitError | - kSDIF_HardwareLockError, /*!< command transfer status collection*/ - kSDIF_DataTransferStatus = kSDIF_DataTransferOver | kSDIF_WriteFIFORequest | kSDIF_ReadFIFORequest | - kSDIF_DataCRCError | kSDIF_DataReadTimeout | kSDIF_DataStarvationByHostTimeout | - kSDIF_FIFOError | kSDIF_DataStartBitError | - kSDIF_DataEndBitError, /*!< data transfer status collection */ - kSDIF_DataTransferError = - kSDIF_DataCRCError | kSDIF_FIFOError | kSDIF_DataStartBitError | kSDIF_DataEndBitError | kSDIF_DataReadTimeout, - kSDIF_AllInterruptStatus = 0x1FFFFU, /*!< all interrupt mask */ - -}; - -/*! @brief _sdif_dma_status define the internal DMA status flags */ -enum -{ - kSDIF_DMATransFinishOneDescriptor = SDIF_IDSTS_TI_MASK, /*!< DMA transfer finished for one DMA descriptor */ - kSDIF_DMARecvFinishOneDescriptor = SDIF_IDSTS_RI_MASK, /*!< DMA receive finished for one DMA descriptor */ - kSDIF_DMAFatalBusError = SDIF_IDSTS_FBE_MASK, /*!< DMA fatal bus error */ - kSDIF_DMADescriptorUnavailable = SDIF_IDSTS_DU_MASK, /*!< DMA descriptor unavailable */ - kSDIF_DMACardErrorSummary = SDIF_IDSTS_CES_MASK, /*!< card error summary */ - kSDIF_NormalInterruptSummary = SDIF_IDSTS_NIS_MASK, /*!< normal interrupt summary */ - kSDIF_AbnormalInterruptSummary = SDIF_IDSTS_AIS_MASK, /*!< abnormal interrupt summary*/ - - kSDIF_DMAAllStatus = kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor | kSDIF_DMAFatalBusError | - kSDIF_DMADescriptorUnavailable | kSDIF_DMACardErrorSummary | kSDIF_NormalInterruptSummary | - kSDIF_AbnormalInterruptSummary, - -}; - -/*! @brief _sdif_dma_descriptor_flag define the internal DMA descriptor flag - * @deprecated Do not use this enum anymore, please use SDIF_DMA_DESCRIPTOR_XXX_FLAG instead. - */ -enum -{ - kSDIF_DisableCompleteInterrupt = 0x2U, /*!< disable the complete interrupt flag for the ends - in the buffer pointed to by this descriptor*/ - kSDIF_DMADescriptorDataBufferEnd = 0x4U, /*!< indicate this descriptor contain the last data buffer of data */ - kSDIF_DMADescriptorDataBufferStart = 0x8U, /*!< indicate this descriptor contain the first data buffer - of data,if first buffer size is 0,next descriptor contain - the begin of the data*/ - - kSDIF_DMASecondAddrChained = 0x10U, /*!< indicate that the second addr in the descriptor is the - next descriptor addr not the data buffer */ - kSDIF_DMADescriptorEnd = 0x20U, /*!< indicate that the descriptor list reached its final descriptor*/ - kSDIF_DMADescriptorOwnByDMA = (int)0x80000000, /*!< indicate the descriptor is own by SD/MMC DMA */ -}; - -/*! @brief define the internal DMA mode */ -typedef enum _sdif_dma_mode -{ - kSDIF_ChainDMAMode = 0x01U, /* one descriptor with one buffer,but one descriptor point to another */ - kSDIF_DualDMAMode = 0x02U, /* dual mode is one descriptor with two buffer */ -} sdif_dma_mode_t; - -/*! @brief define the internal DMA descriptor */ -typedef struct _sdif_dma_descriptor -{ - uint32_t dmaDesAttribute; /*!< internal DMA attribute control and status */ - uint32_t dmaDataBufferSize; /*!< internal DMA transfer buffer size control */ - const uint32_t *dmaDataBufferAddr0; /*!< internal DMA buffer 0 addr ,the buffer size must be 32bit aligned */ - const uint32_t *dmaDataBufferAddr1; /*!< internal DMA buffer 1 addr ,the buffer size must be 32bit aligned */ - -} sdif_dma_descriptor_t; - -/*! @brief Defines the internal DMA configure structure. */ -typedef struct _sdif_dma_config -{ - bool enableFixBurstLen; /*!< fix burst len enable/disable flag,When set, the AHB will - use only SINGLE, INCR4, INCR8 or INCR16 during start of - normal burst transfers. When reset, the AHB will use SINGLE - and INCR burst transfer operations */ - - sdif_dma_mode_t mode; /*!< define the DMA mode */ - - uint8_t dmaDesSkipLen; /*!< define the descriptor skip length ,the length between two descriptor - this field is special for dual DMA mode */ - - uint32_t *dmaDesBufferStartAddr; /*!< internal DMA descriptor start address*/ - uint32_t dmaDesBufferLen; /*!< internal DMA buffer descriptor buffer len ,user need to pay attention to the - dma descriptor buffer length if it is bigger enough for your transfer */ - -} sdif_dma_config_t; - -/*! - * @brief Card data descriptor - */ -typedef struct _sdif_data -{ - bool streamTransfer; /*!< indicate this is a stream data transfer command */ - bool enableAutoCommand12; /*!< indicate if auto stop will send when data transfer over */ - bool enableIgnoreError; /*!< indicate if enable ignore error when transfer data */ - - size_t blockSize; /*!< Block size, take care when configure this parameter */ - uint32_t blockCount; /*!< Block count */ - uint32_t *rxData; /*!< data buffer to receive */ - const uint32_t *txData; /*!< data buffer to transfer */ -} sdif_data_t; - -/*! - * @brief Card command descriptor - * - * Define card command-related attribute. - */ -typedef struct _sdif_command -{ - uint32_t index; /*!< Command index */ - uint32_t argument; /*!< Command argument */ - uint32_t response[4U]; /*!< Response for this command */ - uint32_t type; /*!< define the command type */ - uint32_t responseType; /*!< Command response type */ - uint32_t flags; /*!< Cmd flags */ - uint32_t responseErrorFlags; /*!< response error flags, need to check the flags when - receive the cmd response */ -} sdif_command_t; - -/*! @brief Transfer state */ -typedef struct _sdif_transfer -{ - sdif_data_t *data; /*!< Data to transfer */ - sdif_command_t *command; /*!< Command to send */ -} sdif_transfer_t; - -/*! @brief Data structure to initialize the sdif */ -typedef struct _sdif_config -{ - uint8_t responseTimeout; /*!< command response timeout value */ - uint32_t cardDetDebounce_Clock; /*!< define the debounce clock count which will used in - card detect logic,typical value is 5-25ms */ - uint32_t dataTimeout; /*!< data timeout value */ -} sdif_config_t; - -/*! - * @brief SDIF capability information. - * Defines a structure to get the capability information of SDIF. - */ -typedef struct _sdif_capability -{ - uint32_t sdVersion; /*!< support SD card/sdio version */ - uint32_t mmcVersion; /*!< support emmc card version */ - uint32_t maxBlockLength; /*!< Maximum block length united as byte */ - uint32_t maxBlockCount; /*!< Maximum byte count can be transfered */ - uint32_t flags; /*!< Capability flags to indicate the support information */ -} sdif_capability_t; - -/*! @brief sdif callback functions. */ -typedef struct _sdif_transfer_callback -{ - void (*cardInserted)(SDIF_Type *base, void *userData); /*!< card insert call back */ - void (*cardRemoved)(SDIF_Type *base, void *userData); /*!< card remove call back */ - void (*SDIOInterrupt)(SDIF_Type *base, void *userData); /*!< SDIO card interrupt occurs */ - void (*DMADesUnavailable)(SDIF_Type *base, void *userData); /*!< DMA descriptor unavailable */ - void (*CommandReload)(SDIF_Type *base, void *userData); /*!< command buffer full,need re-load */ - void (*TransferComplete)(SDIF_Type *base, - void *handle, - status_t status, - void *userData); /*!< Transfer complete callback */ -} sdif_transfer_callback_t; - -/*! - * @brief sdif handle - * - * Defines the structure to save the sdif state information and callback function. The detail interrupt status when - * send command or transfer data can be obtained from interruptFlags field by using mask defined in - * sdif_interrupt_flag_t; - * @note All the fields except interruptFlags and transferredWords must be allocated by the user. - */ -typedef struct _sdif_handle -{ - /* Transfer parameter */ - sdif_data_t *volatile data; /*!< Data to transfer */ - sdif_command_t *volatile command; /*!< Command to send */ - - /* Transfer status */ - volatile uint32_t transferredWords; /*!< Words transferred by polling way */ - - /* Callback functions */ - sdif_transfer_callback_t callback; /*!< Callback function */ - void *userData; /*!< Parameter for transfer complete callback */ -} sdif_handle_t; - -/*! @brief sdif transfer function. */ -typedef status_t (*sdif_transfer_function_t)(SDIF_Type *base, sdif_transfer_t *content); - -/*! @brief sdif host descriptor */ -typedef struct _sdif_host -{ - SDIF_Type *base; /*!< sdif peripheral base address */ - uint32_t sourceClock_Hz; /*!< sdif source clock frequency united in Hz */ - sdif_config_t config; /*!< sdif configuration */ - sdif_transfer_function_t transfer; /*!< sdif transfer function */ - sdif_capability_t capability; /*!< sdif capability information */ -} sdif_host_t; - -/************************************************************************************************* - * API - ************************************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief SDIF module initialization function. - * - * Configures the SDIF according to the user configuration. - * @param base SDIF peripheral base address. - * @param config SDIF configuration information. - */ -void SDIF_Init(SDIF_Type *base, sdif_config_t *config); - -/*! - * @brief SDIF module deinit function. - * user should call this function follow with IP reset - * @param base SDIF peripheral base address. - */ -void SDIF_Deinit(SDIF_Type *base); - -/*! - * @brief SDIF send initialize 80 clocks for SD card after initial - * @param base SDIF peripheral base address. - * @param timeout timeout value - */ -bool SDIF_SendCardActive(SDIF_Type *base, uint32_t timeout); - -#if defined(FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD) && FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD -/*! - * @brief SDIF module enable/disable card0 clock. - * @param base SDIF peripheral base address. - * @param enable enable/disable flag - */ -static inline void SDIF_EnableCardClock(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CLKENA |= SDIF_CLKENA_CCLK0_ENABLE_MASK; - } - else - { - base->CLKENA &= SDIF_CLKENA_CCLK0_ENABLE_MASK; - } -} - -/*! - * @brief SDIF module enable/disable card1 clock. - * @param base SDIF peripheral base address. - * @param enable enable/disable flag - */ -static inline void SDIF_EnableCard1Clock(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CLKENA |= SDIF_CLKENA_CCLK1_ENABLE_MASK; - } - else - { - base->CLKENA &= ~SDIF_CLKENA_CCLK1_ENABLE_MASK; - } -} - -/*! - * @brief SDIF module enable/disable module disable the card clock - * to enter low power mode when card is idle,for SDIF cards, if - * interrupts must be detected, clock should not be stopped - * @param base SDIF peripheral base address. - * @param enable enable/disable flag - */ -static inline void SDIF_EnableLowPowerMode(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CLKENA |= SDIF_CLKENA_CCLK0_LOW_POWER_MASK; - } - else - { - base->CLKENA &= ~SDIF_CLKENA_CCLK0_LOW_POWER_MASK; - } -} - -/*! - * @brief SDIF module enable/disable module disable the card clock - * to enter low power mode when card is idle,for SDIF cards, if - * interrupts must be detected, clock should not be stopped - * @param base SDIF peripheral base address. - * @param enable enable/disable flag - */ -static inline void SDIF_EnableCard1LowPowerMode(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CLKENA |= SDIF_CLKENA_CCLK1_LOW_POWER_MASK; - } - else - { - base->CLKENA &= ~SDIF_CLKENA_CCLK1_LOW_POWER_MASK; - } -} - -/*! - * @brief enable/disable the card0 power. - * once turn power on, software should wait for regulator/switch - * ramp-up time before trying to initialize card. - * @param base SDIF peripheral base address. - * @param enable enable/disable flag. - */ -static inline void SDIF_EnableCardPower(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->PWREN |= SDIF_PWREN_POWER_ENABLE0_MASK; - } - else - { - base->PWREN &= ~SDIF_PWREN_POWER_ENABLE0_MASK; - } -} - -/*! - * @brief enable/disable the card1 power. - * once turn power on, software should wait for regulator/switch - * ramp-up time before trying to initialize card. - * @param base SDIF peripheral base address. - * @param enable enable/disable flag. - */ -static inline void SDIF_EnableCard1Power(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->PWREN |= SDIF_PWREN_POWER_ENABLE1_MASK; - } - else - { - base->PWREN &= ~SDIF_PWREN_POWER_ENABLE1_MASK; - } -} - -/*! - * @brief set card0 data bus width - * @param base SDIF peripheral base address. - * @param type data bus width type - */ -void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type); - -/*! - * @brief set card1 data bus width - * @param base SDIF peripheral base address. - * @param type data bus width type - */ -void SDIF_SetCard1BusWidth(SDIF_Type *base, sdif_bus_width_t type); - -/*! - * @brief SDIF module detect card0 insert status function. - * @param base SDIF peripheral base address. - * @param data3 indicate use data3 as card insert detect pin - * @retval 1 card is inserted - * 0 card is removed - */ -static inline uint32_t SDIF_DetectCardInsert(SDIF_Type *base, bool data3) -{ - if (data3) - { - return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1UL : 0UL; - } - else - { - return (base->CDETECT & SDIF_CDETECT_CARD0_DETECT_MASK) == 0UL ? 1UL : 0UL; - } -} - -/*! - * @brief SDIF module detect card1 insert status function. - * @param base SDIF peripheral base address. - * @param data3 indicate use data3 as card insert detect pin - * @retval 1 card is inserted - * 0 card is removed - */ -static inline uint32_t SDIF_DetectCard1Insert(SDIF_Type *base, bool data3) -{ - if (data3) - { - return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1UL : 0UL; - } - else - { - return (base->CDETECT & SDIF_CDETECT_CARD1_DETECT_MASK) == 0UL ? 1UL : 0UL; - } -} -#else -/*! - * @brief SDIF module enable/disable card clock. - * @param base SDIF peripheral base address. - * @param enable enable/disable flag - */ -static inline void SDIF_EnableCardClock(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CLKENA |= SDIF_CLKENA_CCLK_ENABLE_MASK; - } - else - { - base->CLKENA &= ~SDIF_CLKENA_CCLK_ENABLE_MASK; - } -} - -/*! - * @brief SDIF module enable/disable module disable the card clock - * to enter low power mode when card is idle,for SDIF cards, if - * interrupts must be detected, clock should not be stopped - * @param base SDIF peripheral base address. - * @param enable enable/disable flag - */ -static inline void SDIF_EnableLowPowerMode(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CLKENA |= SDIF_CLKENA_CCLK_LOW_POWER_MASK; - } - else - { - base->CLKENA &= ~SDIF_CLKENA_CCLK_LOW_POWER_MASK; - } -} - -/*! - * @brief enable/disable the card power. - * once turn power on, software should wait for regulator/switch - * ramp-up time before trying to initialize card. - * @param base SDIF peripheral base address. - * @param enable enable/disable flag. - */ -static inline void SDIF_EnableCardPower(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->PWREN |= SDIF_PWREN_POWER_ENABLE_MASK; - } - else - { - base->PWREN &= ~SDIF_PWREN_POWER_ENABLE_MASK; - } -} - -/*! - * @brief set card data bus width - * @param base SDIF peripheral base address. - * @param type bus width type - */ -void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type); - -/*! - * @brief SDIF module detect card insert status function. - * @param base SDIF peripheral base address. - * @param data3 indicate use data3 as card insert detect pin - * @retval 1 card is inserted - * 0 card is removed - */ -static inline uint32_t SDIF_DetectCardInsert(SDIF_Type *base, bool data3) -{ - if (data3) - { - return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1UL : 0UL; - } - else - { - return (base->CDETECT & SDIF_CDETECT_CARD_DETECT_MASK) == 0UL ? 1UL : 0UL; - } -} -#endif - -/*! - * @brief Sets the card bus clock frequency. - * - * @param base SDIF peripheral base address. - * @param srcClock_Hz SDIF source clock frequency united in Hz. - * @param target_HZ card bus clock frequency united in Hz. - * @return The nearest frequency of busClock_Hz configured to SD bus. - */ -uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t target_HZ); - -/*! - * @brief reset the different block of the interface. - * @param base SDIF peripheral base address. - * @param mask indicate which block to reset. - * @param timeout timeout value,set to wait the bit self clear - * @return reset result. - */ -bool SDIF_Reset(SDIF_Type *base, uint32_t mask, uint32_t timeout); - -/*! - * @brief get the card write protect status - * @param base SDIF peripheral base address. - */ -static inline uint32_t SDIF_GetCardWriteProtect(SDIF_Type *base) -{ - return base->WRTPRT & SDIF_WRTPRT_WRITE_PROTECT_MASK; -} - -/*! - * @brief toggle state on hardware reset PIN - * This is used which card has a reset PIN typically. - * @param base SDIF peripheral base address. - */ -static inline void SDIF_AssertHardwareReset(SDIF_Type *base) -{ - base->RST_N &= ~SDIF_RST_N_CARD_RESET_MASK; -} - -/*! - * @brief send command to the card - * - * This api include polling the status of the bit START_COMMAND, if 0 used as timeout value, then this function - * will return directly without polling the START_CMD status. - * @param base SDIF peripheral base address. - * @param cmd configuration collection - * @param timeout the timeout value of polling START_CMD auto clear status. - * @return command excute status - */ -status_t SDIF_SendCommand(SDIF_Type *base, sdif_command_t *cmd, uint32_t timeout); - -/*! - * @brief SDIF enable/disable global interrupt - * @param base SDIF peripheral base address. - * @param enable enable/disable flag - */ -static inline void SDIF_EnableGlobalInterrupt(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= SDIF_CTRL_INT_ENABLE_MASK; - } - else - { - base->CTRL &= ~SDIF_CTRL_INT_ENABLE_MASK; - } -} - -/*! - * @brief SDIF enable interrupt - * @param base SDIF peripheral base address. - * @param mask mask - */ -static inline void SDIF_EnableInterrupt(SDIF_Type *base, uint32_t mask) -{ - base->INTMASK |= mask; -} - -/*! - * @brief SDIF disable interrupt - * @param base SDIF peripheral base address. - * @param mask mask - */ -static inline void SDIF_DisableInterrupt(SDIF_Type *base, uint32_t mask) -{ - base->INTMASK &= ~mask; -} - -/*! - * @brief SDIF get interrupt status - * @param base SDIF peripheral base address. - */ -static inline uint32_t SDIF_GetInterruptStatus(SDIF_Type *base) -{ - return base->MINTSTS; -} - -/*! - * @brief SDIF get enabled interrupt status - * @param base SDIF peripheral base address. - */ -static inline uint32_t SDIF_GetEnabledInterruptStatus(SDIF_Type *base) -{ - uint32_t intStatus = base->MINTSTS; - - return intStatus & base->INTMASK; -} - -/*! - * @brief SDIF clear interrupt status - * @param base SDIF peripheral base address. - * @param mask mask to clear - */ -static inline void SDIF_ClearInterruptStatus(SDIF_Type *base, uint32_t mask) -{ - base->RINTSTS &= mask; -} - -/*! - * @brief Creates the SDIF handle. - * register call back function for interrupt and enable the interrupt - * @param base SDIF peripheral base address. - * @param handle SDIF handle pointer. - * @param callback Structure pointer to contain all callback functions. - * @param userData Callback function parameter. - */ -void SDIF_TransferCreateHandle(SDIF_Type *base, - sdif_handle_t *handle, - sdif_transfer_callback_t *callback, - void *userData); - -/*! - * @brief SDIF enable DMA interrupt - * @param base SDIF peripheral base address. - * @param mask mask to set - */ -static inline void SDIF_EnableDmaInterrupt(SDIF_Type *base, uint32_t mask) -{ - base->IDINTEN |= mask; -} - -/*! - * @brief SDIF disable DMA interrupt - * @param base SDIF peripheral base address. - * @param mask mask to clear - */ -static inline void SDIF_DisableDmaInterrupt(SDIF_Type *base, uint32_t mask) -{ - base->IDINTEN &= ~mask; -} - -/*! - * @brief SDIF get internal DMA status - * @param base SDIF peripheral base address. - * @return the internal DMA status register - */ -static inline uint32_t SDIF_GetInternalDMAStatus(SDIF_Type *base) -{ - return base->IDSTS; -} - -/*! - * @brief SDIF get enabled internal DMA interrupt status - * @param base SDIF peripheral base address. - * @return the internal DMA status register - */ -static inline uint32_t SDIF_GetEnabledDMAInterruptStatus(SDIF_Type *base) -{ - uint32_t intStatus = base->IDSTS; - - return intStatus & base->IDINTEN; -} -/*! - * @brief SDIF clear internal DMA status - * @param base SDIF peripheral base address. - * @param mask mask to clear - */ -static inline void SDIF_ClearInternalDMAStatus(SDIF_Type *base, uint32_t mask) -{ - base->IDSTS &= mask; -} - -/*! - * @brief SDIF internal DMA config function - * @param base SDIF peripheral base address. - * @param config DMA configuration collection - * @param data buffer pointer - * @param dataSize buffer size - */ -status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, const uint32_t *data, uint32_t dataSize); - -/*! - * @brief SDIF internal DMA enable - * @param base SDIF peripheral base address. - * @param enable internal DMA enable or disable flag. - */ -static inline void SDIF_EnableInternalDMA(SDIF_Type *base, bool enable) -{ - if (enable) - { - /* use internal DMA interface */ - base->CTRL |= SDIF_CTRL_USE_INTERNAL_DMAC_MASK; - /* enable the internal SD/MMC DMA */ - base->BMOD |= SDIF_BMOD_DE_MASK; - } - else - { - /* use internal DMA interface */ - base->CTRL &= ~SDIF_CTRL_USE_INTERNAL_DMAC_MASK; - /* enable the internal SD/MMC DMA */ - base->BMOD &= ~SDIF_BMOD_DE_MASK; - } -} - -/*! - * @brief SDIF send read wait to SDIF card function - * @param base SDIF peripheral base address. - */ -static inline void SDIF_SendReadWait(SDIF_Type *base) -{ - base->CTRL |= SDIF_CTRL_READ_WAIT_MASK; -} - -/*! - * @brief SDIF abort the read data when SDIF card is in suspend state - * Once assert this bit,data state machine will be reset which is waiting for the - * next blocking data,used in SDIO card suspend sequence,should call after suspend - * cmd send - * @param base SDIF peripheral base address. - * @param timeout timeout value to wait this bit self clear which indicate the data machine - * reset to idle - */ -bool SDIF_AbortReadData(SDIF_Type *base, uint32_t timeout); - -/*! - * @brief SDIF enable/disable CE-ATA card interrupt - * this bit should set together with the card register - * @param base SDIF peripheral base address. - * @param enable enable/disable flag - */ -static inline void SDIF_EnableCEATAInterrupt(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK; - } - else - { - base->CTRL &= ~SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK; - } -} - -/*! - * @brief SDIF transfer function data/cmd in a non-blocking way - * this API should be use in interrupt mode, when use this API user - * must call SDIF_TransferCreateHandle first, all status check through - * interrupt - * @param base SDIF peripheral base address. - * @param handle handle - * @param dmaConfig config structure - * This parameter can be config as: - * 1. NULL - In this condition, polling transfer mode is selected - 2. avaliable DMA config - In this condition, DMA transfer mode is selected - * @param transfer transfer configuration collection - */ -status_t SDIF_TransferNonBlocking(SDIF_Type *base, - sdif_handle_t *handle, - sdif_dma_config_t *dmaConfig, - sdif_transfer_t *transfer); - -/*! - * @brief SDIF transfer function data/cmd in a blocking way - * @param base SDIF peripheral base address. - * @param dmaConfig config structure - * 1. NULL - * In this condition, polling transfer mode is selected - * 2. avaliable DMA config - * In this condition, DMA transfer mode is selected - * @param transfer transfer configuration collection - */ -status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sdif_transfer_t *transfer); - -/*! - * @brief SDIF release the DMA descriptor to DMA engine - * this function should be called when DMA descriptor unavailable status occurs - * @param base SDIF peripheral base address. - * @param dmaConfig DMA config pointer - */ -status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig); - -/*! - * @brief SDIF return the controller capability - * @param base SDIF peripheral base address. - * @param capability capability pointer - */ -void SDIF_GetCapability(SDIF_Type *base, sdif_capability_t *capability); - -/*! - * @brief SDIF return the controller status - * @param base SDIF peripheral base address. - */ -static inline uint32_t SDIF_GetControllerStatus(SDIF_Type *base) -{ - return base->STATUS; -} - -/*! - * @brief SDIF send command complete signal disable to CE-ATA card - * @param base SDIF peripheral base address. - * @param withAutoStop auto stop flag - */ -static inline void SDIF_SendCCSD(SDIF_Type *base, bool withAutoStop) -{ - if (withAutoStop) - { - base->CTRL |= SDIF_CTRL_SEND_CCSD_MASK | SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK; - } - else - { - base->CTRL |= SDIF_CTRL_SEND_CCSD_MASK; - } -} - -/*! - * @brief SDIF config the clock delay - * This function is used to config the cclk_in delay to - * sample and driver the data ,should meet the min setup - * time and hold time, and user need to config this parameter - * according to your board setting - * @param target_HZ freq work mode - * @param divider not used in this function anymore, use DELAY value instead of phase directly. - */ -void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider); - -/* @} */ - -#if defined(__cplusplus) -} -#endif -/*! @} */ - -#endif /* _FSL_sdif_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi.c deleted file mode 100644 index 456361e6204..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi.c +++ /dev/null @@ -1,1072 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_spi.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi" -#endif - -/* Note: FIFOCFG[SIZE] has always value 1 = 8 items depth */ - -#if defined(FSL_FEATURE_SPI_FIFOSIZE_CFG) && (FSL_FEATURE_SPI_FIFOSIZE_CFG) -#define SPI_FIFO_DEPTH(base) 4 -#else -#define SPI_FIFO_DEPTH(base) ((((base)->FIFOCFG & SPI_FIFOCFG_SIZE_MASK) >> SPI_FIFOCFG_SIZE_SHIFT) << 3) -#endif /*FSL_FEATURE_SPI_FIFOSIZE_CFG*/ - -/* Convert transfer count to transfer bytes. dataWidth is a - * range <0,15>. Range <8,15> represents 2B transfer */ -#define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U)) -#define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U)) -#if defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) && (FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) -#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK)) -#else -#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK) | (SPI_CFG_SPOL3_MASK)) -#endif /*FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE*/ - -/*! - * @brief Used for conversion from `flexcomm_irq_handler_t` to `flexcomm_spi_master_irq_handler_t` and - * `flexcomm_spi_slave_irq_handler_t`. - */ -typedef union spi_to_flexcomm -{ - flexcomm_spi_master_irq_handler_t spi_master_handler; - flexcomm_spi_slave_irq_handler_t spi_slave_handler; - flexcomm_irq_handler_t flexcomm_handler; -} spi_to_flexcomm_t; - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief internal SPI config array */ -static spi_config_t g_configs[FSL_FEATURE_SOC_SPI_COUNT] = {(spi_data_width_t)0}; - -/*! @brief Array to map SPI instance number to base address. */ -static const uint32_t s_spiBaseAddrs[FSL_FEATURE_SOC_SPI_COUNT] = SPI_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_spiIRQ[] = SPI_IRQS; - -/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ -volatile uint8_t s_dummyData[FSL_FEATURE_SOC_SPI_COUNT] = {0}; -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Get the index corresponding to the FLEXCOMM */ -/*! brief Returns instance number for SPI peripheral base address. */ -uint32_t SPI_GetInstance(SPI_Type *base) -{ - uint32_t i; - - for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_SPI_COUNT; i++) - { - if ((uint32_t)base == s_spiBaseAddrs[i]) - { - break; - } - } - - assert(i < (uint32_t)FSL_FEATURE_SOC_SPI_COUNT); - return i; -} - -/*! - * brief Set up the dummy data. - * - * param base SPI peripheral address. - * param dummyData Data to be transferred when tx buffer is NULL. - */ -void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData) -{ - uint32_t instance = SPI_GetInstance(base); - s_dummyData[instance] = dummyData; -} - -/*! - * brief Returns the configurations. - * - * param base SPI peripheral address. - * return return configurations which contain datawidth and SSEL numbers. - * return data type is a pointer of spi_config_t. - */ -void *SPI_GetConfig(SPI_Type *base) -{ - uint32_t instance; - instance = SPI_GetInstance(base); - return &g_configs[instance]; -} - -/*! - * brief Sets the SPI master configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). - * User may use the initialized structure unchanged in SPI_MasterInit(), or modify - * some fields of the structure before calling SPI_MasterInit(). After calling this API, - * the master is ready to transfer. - * Example: - code - spi_master_config_t config; - SPI_MasterGetDefaultConfig(&config); - endcode - * - * param config pointer to master config structure - */ -void SPI_MasterGetDefaultConfig(spi_master_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enableLoopback = false; - config->enableMaster = true; - config->polarity = kSPI_ClockPolarityActiveHigh; - config->phase = kSPI_ClockPhaseFirstEdge; - config->direction = kSPI_MsbFirst; - config->baudRate_Bps = 500000U; - config->dataWidth = kSPI_Data8Bits; - config->sselNum = kSPI_Ssel0; - config->txWatermark = (uint8_t)kSPI_TxFifo0; - config->rxWatermark = (uint8_t)kSPI_RxFifo1; - config->sselPol = kSPI_SpolActiveAllLow; - config->delayConfig.preDelay = 0U; - config->delayConfig.postDelay = 0U; - config->delayConfig.frameDelay = 0U; - config->delayConfig.transferDelay = 0U; -} - -/*! - * brief Initializes the SPI with master configuration. - * - * The configuration structure can be filled by user from scratch, or be set with default - * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. - * Example - code - spi_master_config_t config = { - .baudRate_Bps = 400000, - ... - }; - SPI_MasterInit(SPI0, &config); - endcode - * - * param base SPI base pointer - * param config pointer to master configuration structure - * param srcClock_Hz Source clock frequency. - */ -status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz) -{ - status_t result = kStatus_Success; - uint32_t instance; - uint32_t tmpConfig; - - /* assert params */ - assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); - if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* initialize flexcomm to SPI mode */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); - if (kStatus_Success != result) - { - return result; - } - - /* set divider */ - result = SPI_MasterSetBaud(base, config->baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - - /* get instance number */ - instance = SPI_GetInstance(base); - - /* configure SPI mode */ - tmpConfig = base->CFG; - tmpConfig &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | - SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); - /* phase */ - tmpConfig |= SPI_CFG_CPHA(config->phase); - /* polarity */ - tmpConfig |= SPI_CFG_CPOL(config->polarity); - /* direction */ - tmpConfig |= SPI_CFG_LSBF(config->direction); - /* master mode */ - tmpConfig |= SPI_CFG_MASTER(1); - /* loopback */ - tmpConfig |= SPI_CFG_LOOP(config->enableLoopback); - /* configure active level for all CS */ - tmpConfig |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); - base->CFG = tmpConfig; - - /* store configuration */ - g_configs[instance].dataWidth = config->dataWidth; - g_configs[instance].sselNum = config->sselNum; - /* enable FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; - /* trigger level - empty txFIFO, one item in rxFIFO */ - tmpConfig = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); - tmpConfig |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable generating interrupts for FIFOTRIG levels */ - tmpConfig |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; - /* set FIFOTRIG */ - base->FIFOTRIG = tmpConfig; - - /* Set the delay configuration. */ - SPI_SetTransferDelay(base, &config->delayConfig); - /* Set the dummy data. */ - SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); - - SPI_Enable(base, config->enableMaster); - return kStatus_Success; -} - -/*! - * brief Sets the SPI slave configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). - * Modify some fields of the structure before calling SPI_SlaveInit(). - * Example: - code - spi_slave_config_t config; - SPI_SlaveGetDefaultConfig(&config); - endcode - * - * param config pointer to slave configuration structure - */ -void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enableSlave = true; - config->polarity = kSPI_ClockPolarityActiveHigh; - config->phase = kSPI_ClockPhaseFirstEdge; - config->direction = kSPI_MsbFirst; - config->dataWidth = kSPI_Data8Bits; - config->txWatermark = (uint8_t)kSPI_TxFifo0; - config->rxWatermark = (uint8_t)kSPI_RxFifo1; - config->sselPol = kSPI_SpolActiveAllLow; -} - -/*! - * brief Initializes the SPI with slave configuration. - * - * The configuration structure can be filled by user from scratch or be set with - * default values by SPI_SlaveGetDefaultConfig(). - * After calling this API, the slave is ready to transfer. - * Example - code - spi_slave_config_t config = { - .polarity = flexSPIClockPolarity_ActiveHigh; - .phase = flexSPIClockPhase_FirstEdge; - .direction = flexSPIMsbFirst; - ... - }; - SPI_SlaveInit(SPI0, &config); - endcode - * - * param base SPI base pointer - * param config pointer to slave configuration structure - */ -status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) -{ - status_t result = kStatus_Success; - uint32_t instance; - uint32_t tmpConfig; - - /* assert params */ - assert(!((NULL == base) || (NULL == config))); - if ((NULL == base) || (NULL == config)) - { - return kStatus_InvalidArgument; - } - /* configure flexcomm to SPI, enable clock gate */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); - if (kStatus_Success != result) - { - return result; - } - - instance = SPI_GetInstance(base); - - /* configure SPI mode */ - tmpConfig = base->CFG; - tmpConfig &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | - SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); - /* phase */ - tmpConfig |= SPI_CFG_CPHA(config->phase); - /* polarity */ - tmpConfig |= SPI_CFG_CPOL(config->polarity); - /* direction */ - tmpConfig |= SPI_CFG_LSBF(config->direction); - /* configure active level for all CS */ - tmpConfig |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); - base->CFG = tmpConfig; - - /* store configuration */ - g_configs[instance].dataWidth = config->dataWidth; - /* empty and enable FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; - /* trigger level - empty txFIFO, one item in rxFIFO */ - tmpConfig = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); - tmpConfig |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable generating interrupts for FIFOTRIG levels */ - tmpConfig |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; - /* set FIFOTRIG */ - base->FIFOTRIG = tmpConfig; - - SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); - - SPI_Enable(base, config->enableSlave); - return kStatus_Success; -} - -/*! - * brief De-initializes the SPI. - * - * Calling this API resets the SPI module, gates the SPI clock. - * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. - * - * param base SPI base pointer - */ -void SPI_Deinit(SPI_Type *base) -{ - /* Assert arguments */ - assert(NULL != base); - /* Disable interrupts, disable dma requests, disable peripheral */ - base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXERR_MASK | SPI_FIFOINTENCLR_RXERR_MASK | SPI_FIFOINTENCLR_TXLVL_MASK | - SPI_FIFOINTENCLR_RXLVL_MASK; - base->FIFOCFG &= ~(SPI_FIFOCFG_DMATX_MASK | SPI_FIFOCFG_DMARX_MASK); - base->CFG &= ~(SPI_CFG_ENABLE_MASK); -} - -/*! - * brief Enables the DMA request from SPI txFIFO. - * - * param base SPI base pointer - * param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableTxDMA(SPI_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= SPI_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= ~SPI_FIFOCFG_DMATX_MASK; - } -} - -/*! - * brief Enables the DMA request from SPI rxFIFO. - * - * param base SPI base pointer - * param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableRxDMA(SPI_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= SPI_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= ~SPI_FIFOCFG_DMARX_MASK; - } -} - -/*! - * brief Sets the baud rate for SPI transfer. This is only used in master. - * - * param base SPI base pointer - * param baudrate_Bps baud rate needed in Hz. - * param srcClock_Hz SPI source clock frequency in Hz. - */ -status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) -{ - uint32_t tmpDiv; - - /* assert params */ - assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))); - if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* calculate baudrate, round up the result */ - tmpDiv = ((srcClock_Hz * 10U) / baudrate_Bps + 5U) / 10U - 1U; - if (tmpDiv > 0xFFFFU) - { - return kStatus_SPI_BaudrateNotSupport; - } - base->DIV &= ~SPI_DIV_DIVVAL_MASK; - base->DIV |= SPI_DIV_DIVVAL(tmpDiv); - return kStatus_Success; -} - -/*! - * brief Writes a data into the SPI data register. - * - * param base SPI base pointer - * param data needs to be write. - * param configFlags transfer configuration options ref spi_xfer_option_t - */ -void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags) -{ - uint32_t control = 0U; - uint32_t instance; - - /* check params */ - assert(NULL != base); - /* get and check instance */ - instance = SPI_GetInstance(base); - - /* set data width */ - control |= (uint32_t)SPI_FIFOWR_LEN((g_configs[instance].dataWidth)); - /* set sssel */ - control |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL((uint32_t)(g_configs[instance].sselNum)))); - /* mask configFlags */ - control |= (configFlags & (uint32_t)SPI_FIFOWR_FLAGS_MASK); - /* control should not affect lower 16 bits */ - assert(0U == (control & 0xFFFFU)); - base->FIFOWR = data | control; -} - -/*! - * brief Initializes the SPI master handle. - * - * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * param base SPI peripheral base address. - * param handle SPI handle pointer. - * param callback Callback function. - * param userData User data. - */ -status_t SPI_MasterTransferCreateHandle(SPI_Type *base, - spi_master_handle_t *handle, - spi_master_callback_t callback, - void *userData) -{ - /* check 'base' */ - assert(NULL != base); - /* check 'handle' */ - assert(NULL != handle); - - uint32_t instance; - spi_to_flexcomm_t handler; - - /* get flexcomm instance by 'base' param */ - instance = SPI_GetInstance(base); - - (void)memset(handle, 0, sizeof(*handle)); - /* Initialize the handle */ - if ((base->CFG & SPI_CFG_MASTER_MASK) != 0U) - { - handler.spi_master_handler = SPI_MasterTransferHandleIRQ; - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - } - else - { - handler.spi_slave_handler = SPI_SlaveTransferHandleIRQ; - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - } - - handle->dataWidth = (uint8_t)(g_configs[instance].dataWidth); - /* in slave mode, the sselNum is not important */ - handle->sselNum = (uint8_t)(g_configs[instance].sselNum); - handle->txWatermark = (uint8_t)SPI_FIFOTRIG_TXLVL_GET(base); - handle->rxWatermark = (uint8_t)SPI_FIFOTRIG_RXLVL_GET(base); - handle->callback = callback; - handle->userData = userData; - - /* Enable SPI NVIC */ - (void)EnableIRQ(s_spiIRQ[instance]); - - return kStatus_Success; -} - -/*! - * brief Transfers a block of data using a polling method. - * - * param base SPI base pointer - * param xfer pointer to spi_xfer_config_t structure - * retval kStatus_Success Successfully start a transfer. - * retval kStatus_InvalidArgument Input argument is invalid. - * retval kStatus_SPI_Timeout The transfer timed out and was aborted. - */ -status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) -{ - uint32_t instance; - uint32_t tx_ctrl = 0U, last_ctrl = 0U; - uint32_t tmp32, rxRemainingBytes, txRemainingBytes, dataWidth; - uint32_t toReceiveCount = 0; - uint8_t *txData, *rxData; - uint32_t fifoDepth; -#if SPI_RETRY_TIMES - uint32_t waitTimes = SPI_RETRY_TIMES; -#endif - - /* check params */ - assert(!((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); - if ((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) - { - return kStatus_InvalidArgument; - } - - fifoDepth = SPI_FIFO_DEPTH(base); - txData = xfer->txData; - rxData = xfer->rxData; - txRemainingBytes = (txData != NULL) ? xfer->dataSize : 0U; - rxRemainingBytes = (rxData != NULL) ? xfer->dataSize : 0U; - - instance = SPI_GetInstance(base); - dataWidth = (uint32_t)(g_configs[instance].dataWidth); - - /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ - if ((dataWidth > (uint32_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U)) - { - return kStatus_InvalidArgument; - } - - /* clear tx/rx errors and empty FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - /* select slave to talk with */ - tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL((uint32_t)(g_configs[instance].sselNum)))); - /* set width of data - range asserted at entry */ - tx_ctrl |= SPI_FIFOWR_LEN(dataWidth); - /* delay for frames */ - tx_ctrl |= ((xfer->configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; - /* end of transfer */ - last_ctrl |= ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; - /* last index of loop */ - while ((txRemainingBytes != 0U) || (rxRemainingBytes != 0U) || (toReceiveCount != 0U)) - { -#if SPI_RETRY_TIMES - if (--waitTimes == 0U) - { - return kStatus_SPI_Timeout; - } -#endif - /* if rxFIFO is not empty */ - if ((base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) != 0U) - { - tmp32 = base->FIFORD; - /* rxBuffer is not empty */ - if (rxRemainingBytes != 0U) - { - *(rxData++) = (uint8_t)tmp32; - rxRemainingBytes--; - /* read 16 bits at once */ - if (dataWidth > 8U) - { - *(rxData++) = (uint8_t)(tmp32 >> 8); - rxRemainingBytes--; - } - } - /* decrease number of data expected to receive */ - toReceiveCount -= 1U; - } - /* transmit if txFIFO is not full and data to receive does not exceed FIFO depth */ - if (((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) != 0U) && (toReceiveCount < fifoDepth) && - ((txRemainingBytes != 0U) || (rxRemainingBytes >= SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1U)))) - { - /* txBuffer is not empty */ - if (txRemainingBytes != 0U) - { - tmp32 = *(txData++); - txRemainingBytes--; - /* write 16 bit at once */ - if (dataWidth > 8U) - { - tmp32 |= ((uint32_t)(*(txData++))) << 8U; - txRemainingBytes--; - } - if (txRemainingBytes == 0U) - { - tx_ctrl |= last_ctrl; - } - } - else - { - tmp32 = (uint32_t)s_dummyData[instance]; - tmp32 |= (uint32_t)s_dummyData[instance] << 8U; - /* last transfer */ - if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1U)) - { - tx_ctrl |= last_ctrl; - } - } - /* send data */ - tmp32 = tx_ctrl | tmp32; - base->FIFOWR = tmp32; - toReceiveCount += 1U; - } - } - /* wait if TX FIFO of previous transfer is not empty */ -#if SPI_RETRY_TIMES - waitTimes = SPI_RETRY_TIMES; - while ((0U == (base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) && (0U != --waitTimes)) -#else - while (0U == (base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) -#endif - { - } -#if SPI_RETRY_TIMES - if (waitTimes == 0U) - { - return kStatus_SPI_Timeout; - } -#endif - return kStatus_Success; -} - -/*! - * brief Performs a non-blocking SPI interrupt transfer. - * - * param base SPI peripheral base address. - * param handle pointer to spi_master_handle_t structure which stores the transfer state - * param xfer pointer to spi_xfer_config_t structure - * retval kStatus_Success Successfully start a transfer. - * retval kStatus_InvalidArgument Input argument is invalid. - * retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer) -{ - /* check params */ - assert( - !((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) - { - return kStatus_InvalidArgument; - } - - /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ - assert(!((handle->dataWidth > (uint8_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U))); - if ((handle->dataWidth > (uint8_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U)) - { - return kStatus_InvalidArgument; - } - - /* Check if SPI is busy */ - if (handle->state == (uint32_t)kStatus_SPI_Busy) - { - return kStatus_SPI_Busy; - } - - /* Set the handle information */ - handle->txData = xfer->txData; - handle->rxData = xfer->rxData; - /* set count */ - handle->txRemainingBytes = (xfer->txData != NULL) ? xfer->dataSize : 0U; - handle->rxRemainingBytes = (xfer->rxData != NULL) ? xfer->dataSize : 0U; - handle->totalByteCount = xfer->dataSize; - /* other options */ - handle->toReceiveCount = 0; - handle->configFlags = xfer->configFlags; - /* Set the SPI state to busy */ - handle->state = (uint32_t)kStatus_SPI_Busy; - /* clear FIFOs when transfer starts */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - /* enable generating txIRQ and rxIRQ, first transfer is fired by empty txFIFO */ - base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK; - return kStatus_Success; -} - -/*! - * brief Transfers a block of data using a polling method. - * - * This function will do a half-duplex transfer for SPI master, This is a blocking function, - * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, - * users can set transmit first or receive first. - * - * param base SPI base pointer - * param xfer pointer to spi_half_duplex_transfer_t structure - * return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer) -{ - assert(xfer != NULL); - - spi_transfer_t tempXfer = {0}; - status_t status; - - if (xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the pcs pin keep assert between transmit and receive. */ - if (xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); - } - else - { - tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; - } - - status = SPI_MasterTransferBlocking(base, &tempXfer); - - if (status != kStatus_Success) - { - return status; - } - - if (xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - /* SPI transfer blocking. */ - status = SPI_MasterTransferBlocking(base, &tempXfer); - - return status; -} - -/*! - * brief Performs a non-blocking SPI interrupt transfer. - * - * This function using polling way to do the first half transimission and using interrupts to - * do the second half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * param base SPI peripheral base address. - * param handle pointer to spi_master_handle_t structure which stores the transfer state - * param xfer pointer to spi_half_duplex_transfer_t structure - * return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, - spi_master_handle_t *handle, - spi_half_duplex_transfer_t *xfer) -{ - assert(xfer != NULL); - assert(handle != NULL); - spi_transfer_t tempXfer = {0}; - status_t status; - - if (xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the PCS pin keep assert between transmit and receive. */ - if (xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); - } - else - { - tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; - } - - status = SPI_MasterTransferBlocking(base, &tempXfer); - if (status != kStatus_Success) - { - return status; - } - - if (xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - status = SPI_MasterTransferNonBlocking(base, handle, &tempXfer); - - return status; -} - -/*! - * brief Gets the master transfer count. - * - * This function gets the master transfer count. - * - * param base SPI peripheral base address. - * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * param count The number of bytes transferred by using the non-blocking transaction. - * return status of status_t. - */ -status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count) -{ - assert(NULL != handle); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != (uint32_t)kStatus_SPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - *count = handle->totalByteCount - handle->rxRemainingBytes; - return kStatus_Success; -} - -/*! - * brief SPI master aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * param base SPI peripheral base address. - * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle) -{ - assert(NULL != handle); - - /* Disable interrupt requests*/ - base->FIFOINTENSET &= ~(SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK); - /* Empty FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - - handle->state = (uint32_t)kStatus_SPI_Idle; - handle->txRemainingBytes = 0U; - handle->rxRemainingBytes = 0U; -} - -static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *handle) -{ - uint32_t tx_ctrl = 0U, last_ctrl = 0U, tmp32; - bool loopContinue; - uint32_t fifoDepth; - /* Get flexcomm instance by 'base' param */ - uint32_t instance = SPI_GetInstance(base); - size_t txRemainingBytes; - size_t rxRemainingBytes; - uint8_t toReceiveCount; - - /* check params */ - assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData))); - - fifoDepth = SPI_FIFO_DEPTH(base); - /* select slave to talk with */ - tx_ctrl |= ((uint32_t)SPI_DEASSERT_ALL & (uint32_t)SPI_ASSERTNUM_SSEL(handle->sselNum)); - /* set width of data */ - tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth); - /* delay for frames */ - tx_ctrl |= ((handle->configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; - /* end of transfer */ - last_ctrl |= ((handle->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; - do - { - loopContinue = false; - - /* rxFIFO is not empty */ - if ((base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) != 0U) - { - tmp32 = base->FIFORD; - /* rxBuffer is not empty */ - if (handle->rxRemainingBytes != 0U) - { - /* low byte must go first */ - *(handle->rxData++) = (uint8_t)tmp32; - handle->rxRemainingBytes--; - /* read 16 bits at once */ - if (handle->dataWidth > (uint8_t)kSPI_Data8Bits) - { - *(handle->rxData++) = (uint8_t)(tmp32 >> 8); - handle->rxRemainingBytes--; - } - } - - /* decrease number of data expected to receive */ - handle->toReceiveCount -= 1; - loopContinue = true; - } - - /* - txFIFO is not full - * - we cannot cause rxFIFO overflow by sending more data than is the depth of FIFO - * - txBuffer is not empty or the next 'toReceiveCount' data can fit into rxBuffer - */ - txRemainingBytes = handle->txRemainingBytes; - rxRemainingBytes = handle->rxRemainingBytes; - toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; - if (((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) != 0U) && ((uint32_t)toReceiveCount < fifoDepth) && - ((txRemainingBytes != 0U) || - (rxRemainingBytes >= SPI_COUNT_TO_BYTES(handle->dataWidth, (uint32_t)toReceiveCount + 1U)))) - { - /* txBuffer is not empty */ - if ((txRemainingBytes != 0U) && (handle->txData != NULL)) - { - /* low byte must go first */ - tmp32 = *(handle->txData++); - handle->txRemainingBytes--; - txRemainingBytes = handle->txRemainingBytes; - /* write 16 bit at once */ - if (handle->dataWidth > (uint8_t)kSPI_Data8Bits) - { - tmp32 |= ((uint32_t)(*(handle->txData++))) << 8U; - handle->txRemainingBytes--; - txRemainingBytes = handle->txRemainingBytes; - } - /* last transfer */ - if (handle->txRemainingBytes == 0U) - { - tx_ctrl |= last_ctrl; - } - } - else - { - tmp32 = (uint32_t)s_dummyData[instance]; - tmp32 |= (uint32_t)s_dummyData[instance] << 8U; - /* last transfer */ - if (rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, (uint32_t)toReceiveCount + 1U)) - { - tx_ctrl |= last_ctrl; - } - } - /* send data */ - tmp32 = tx_ctrl | tmp32; - base->FIFOWR = tmp32; - /* increase number of expected data to receive */ - handle->toReceiveCount += 1; - toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; - loopContinue = true; - } - } while (loopContinue); -} - -/*! - * brief Interrupts the handler for the SPI. - * - * param base SPI peripheral base address. - * param handle pointer to spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle) -{ - assert((NULL != base) && (NULL != handle)); - size_t txRemainingBytes; - uint8_t toReceiveCount; - - /* IRQ behaviour: - * - first interrupt is triggered by empty txFIFO. The transfer function - * then tries empty rxFIFO and fill txFIFO interleaved that results to - * strategy to process as many items as possible. - * - the next IRQs can be: - * rxIRQ from nonempty rxFIFO which requires to empty rxFIFO. - * txIRQ from empty txFIFO which requires to refill txFIFO. - * - last interrupt is triggered by empty txFIFO. The last state is - * known by empty rxBuffer and txBuffer. If there is nothing to receive - * or send - both operations have been finished and interrupts can be - * disabled. - */ - - /* Data to send or read or expected to receive */ - if ((handle->txRemainingBytes != 0U) || (handle->rxRemainingBytes != 0U) || (handle->toReceiveCount != 0)) - { - /* Transmit or receive data */ - SPI_TransferHandleIRQInternal(base, handle); - /* No data to send or read or receive. Transfer ends. Set txTrigger to 0 level and - * enable txIRQ to confirm when txFIFO becomes empty */ - if ((0U == handle->txRemainingBytes) && (0U == handle->rxRemainingBytes) && (0 == handle->toReceiveCount)) - { - base->FIFOTRIG = base->FIFOTRIG & (~SPI_FIFOTRIG_TXLVL_MASK); - base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK; - } - else - { - uint32_t rxRemainingCount = SPI_BYTES_TO_COUNT(handle->dataWidth, handle->rxRemainingBytes); - /* If, there are no data to send or rxFIFO is already filled with necessary number of dummy data, - * disable txIRQ. From this point only rxIRQ is used to receive data without any transmission */ - toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; - if ((0U == handle->txRemainingBytes) && (rxRemainingCount <= toReceiveCount)) - { - base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXLVL_MASK; - } - /* Nothing to receive or transmit, but we still have pending data which are bellow rxLevel. - * Cannot clear rxFIFO, txFIFO might be still active */ - if (rxRemainingCount == 0U) - { - txRemainingBytes = handle->txRemainingBytes; - if ((txRemainingBytes == 0U) && (toReceiveCount != 0U) && - (toReceiveCount < SPI_FIFOTRIG_RXLVL_GET(base) + 1U)) - { - base->FIFOTRIG = (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | - SPI_FIFOTRIG_RXLVL((uint32_t)toReceiveCount - 1U); - } - } - else - { - /* Expected to receive less data than rxLevel value, we have to update rxLevel */ - if (rxRemainingCount < (SPI_FIFOTRIG_RXLVL_GET(base) + 1U)) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(rxRemainingCount - 1U); - } - } - } - } - else - { - /* Empty txFIFO is confirmed. Disable IRQs and restore triggers values */ - base->FIFOINTENCLR = SPI_FIFOINTENCLR_RXLVL_MASK | SPI_FIFOINTENCLR_TXLVL_MASK; - base->FIFOTRIG = (base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_RXLVL_MASK))) | - SPI_FIFOTRIG_RXLVL(handle->rxWatermark) | SPI_FIFOTRIG_TXLVL(handle->txWatermark); - /* set idle state and call user callback */ - handle->state = (uint32_t)kStatus_SPI_Idle; - if (handle->callback != NULL) - { - (handle->callback)(base, handle, handle->state, handle->userData); - } - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi.h deleted file mode 100644 index 2320e574cc9..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi.h +++ /dev/null @@ -1,746 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SPI_H_ -#define _FSL_SPI_H_ - -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/*! - * @addtogroup spi_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SPI driver version. */ -#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) -/*@}*/ - -/*! @brief Global variable for dummy data value setting. */ -extern volatile uint8_t s_dummyData[]; - -#ifndef SPI_DUMMYDATA -/*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */ -#define SPI_DUMMYDATA (0xFFU) -#endif - -/*! @brief Retry times for waiting flag. */ -#ifndef SPI_RETRY_TIMES -#define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ -#endif - -#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFFUL) -#define SPI_CTRLMASK (0xFFFF0000U) - -#define SPI_ASSERTNUM_SSEL(n) ((~(1UL << ((n) + 16UL))) & 0xF0000UL) -#define SPI_DEASSERTNUM_SSEL(n) (1UL << ((n) + 16UL)) -#define SPI_DEASSERT_ALL (0xF0000UL) - -#define SPI_FIFOWR_FLAGS_MASK (~(SPI_DEASSERT_ALL | SPI_FIFOWR_TXDATA_MASK | SPI_FIFOWR_LEN_MASK)) - -#define SPI_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_TXLVL_MASK) >> SPI_FIFOTRIG_TXLVL_SHIFT) -#define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT) - -/*! @brief SPI transfer option.*/ -typedef enum _spi_xfer_option -{ - kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), /*!< A delay may be inserted, defined in the DLY register.*/ - kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< SSEL will be deasserted at the end of a transfer */ -} spi_xfer_option_t; - -/*! @brief SPI data shifter direction options.*/ -typedef enum _spi_shift_direction -{ - kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */ - kSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. */ -} spi_shift_direction_t; - -/*! @brief SPI clock polarity configuration.*/ -typedef enum _spi_clock_polarity -{ - kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */ - kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */ -} spi_clock_polarity_t; - -/*! @brief SPI clock phase configuration.*/ -typedef enum _spi_clock_phase -{ - kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first - * cycle of a data transfer. */ - kSPI_ClockPhaseSecondEdge /*!< First edge on SCK occurs at the start of the - * first cycle of a data transfer. */ -} spi_clock_phase_t; - -/*! @brief txFIFO watermark values */ -typedef enum _spi_txfifo_watermark -{ - kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */ - kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */ - kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */ - kSPI_TxFifo3 = 3, /*!< SPI tx watermark at 3 items */ - kSPI_TxFifo4 = 4, /*!< SPI tx watermark at 4 items */ - kSPI_TxFifo5 = 5, /*!< SPI tx watermark at 5 items */ - kSPI_TxFifo6 = 6, /*!< SPI tx watermark at 6 items */ - kSPI_TxFifo7 = 7, /*!< SPI tx watermark at 7 items */ -} spi_txfifo_watermark_t; - -/*! @brief rxFIFO watermark values */ -typedef enum _spi_rxfifo_watermark -{ - kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */ - kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */ - kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */ - kSPI_RxFifo4 = 3, /*!< SPI rx watermark at 4 items */ - kSPI_RxFifo5 = 4, /*!< SPI rx watermark at 5 items */ - kSPI_RxFifo6 = 5, /*!< SPI rx watermark at 6 items */ - kSPI_RxFifo7 = 6, /*!< SPI rx watermark at 7 items */ - kSPI_RxFifo8 = 7, /*!< SPI rx watermark at 8 items */ -} spi_rxfifo_watermark_t; - -/*! @brief Transfer data width */ -typedef enum _spi_data_width -{ - kSPI_Data4Bits = 3, /*!< 4 bits data width */ - kSPI_Data5Bits = 4, /*!< 5 bits data width */ - kSPI_Data6Bits = 5, /*!< 6 bits data width */ - kSPI_Data7Bits = 6, /*!< 7 bits data width */ - kSPI_Data8Bits = 7, /*!< 8 bits data width */ - kSPI_Data9Bits = 8, /*!< 9 bits data width */ - kSPI_Data10Bits = 9, /*!< 10 bits data width */ - kSPI_Data11Bits = 10, /*!< 11 bits data width */ - kSPI_Data12Bits = 11, /*!< 12 bits data width */ - kSPI_Data13Bits = 12, /*!< 13 bits data width */ - kSPI_Data14Bits = 13, /*!< 14 bits data width */ - kSPI_Data15Bits = 14, /*!< 15 bits data width */ - kSPI_Data16Bits = 15, /*!< 16 bits data width */ -} spi_data_width_t; - -/*! @brief Slave select */ -typedef enum _spi_ssel -{ - kSPI_Ssel0 = 0, /*!< Slave select 0 */ - kSPI_Ssel1 = 1, /*!< Slave select 1 */ - kSPI_Ssel2 = 2, /*!< Slave select 2 */ - kSPI_Ssel3 = 3, /*!< Slave select 3 */ -} spi_ssel_t; - -/*! @brief ssel polarity */ -typedef enum _spi_spol -{ - kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0(1), - kSPI_Spol1ActiveHigh = SPI_CFG_SPOL1(1), - kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2(1), -#if defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) && (FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) - kSPI_SpolActiveAllHigh = (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh), -#else - kSPI_Spol3ActiveHigh = SPI_CFG_SPOL3(1), - kSPI_SpolActiveAllHigh = - (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh | kSPI_Spol3ActiveHigh), -#endif - kSPI_SpolActiveAllLow = 0, -} spi_spol_t; - -/*! - * @brief SPI delay time configure structure. - * Note: - * The DLY register controls several programmable delays related to SPI signalling, - * it stands for how many SPI clock time will be inserted. - * The maxinun value of these delay time is 15. - */ -typedef struct _spi_delay_config -{ - uint8_t preDelay; /*!< Delay between SSEL assertion and the beginning of transfer. */ - uint8_t postDelay; /*!< Delay between the end of transfer and SSEL deassertion. */ - uint8_t frameDelay; /*!< Delay between frame to frame. */ - uint8_t transferDelay; /*!< Delay between transfer to transfer. */ -} spi_delay_config_t; - -/*! @brief SPI master user configure structure.*/ -typedef struct _spi_master_config -{ - bool enableLoopback; /*!< Enable loopback for test purpose */ - bool enableMaster; /*!< Enable SPI at initialization time */ - spi_clock_polarity_t polarity; /*!< Clock polarity */ - spi_clock_phase_t phase; /*!< Clock phase */ - spi_shift_direction_t direction; /*!< MSB or LSB */ - uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */ - spi_data_width_t dataWidth; /*!< Width of the data */ - spi_ssel_t sselNum; /*!< Slave select number */ - spi_spol_t sselPol; /*!< Configure active CS polarity */ - uint8_t txWatermark; /*!< txFIFO watermark */ - uint8_t rxWatermark; /*!< rxFIFO watermark */ - spi_delay_config_t delayConfig; /*!< Delay configuration. */ -} spi_master_config_t; - -/*! @brief SPI slave user configure structure.*/ -typedef struct _spi_slave_config -{ - bool enableSlave; /*!< Enable SPI at initialization time */ - spi_clock_polarity_t polarity; /*!< Clock polarity */ - spi_clock_phase_t phase; /*!< Clock phase */ - spi_shift_direction_t direction; /*!< MSB or LSB */ - spi_data_width_t dataWidth; /*!< Width of the data */ - spi_spol_t sselPol; /*!< Configure active CS polarity */ - uint8_t txWatermark; /*!< txFIFO watermark */ - uint8_t rxWatermark; /*!< rxFIFO watermark */ -} spi_slave_config_t; - -/*! @brief SPI transfer status.*/ -enum -{ - kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0), /*!< SPI bus is busy */ - kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1), /*!< SPI is idle */ - kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI error */ - kStatus_SPI_BaudrateNotSupport = - MAKE_STATUS(kStatusGroup_LPC_SPI, 3), /*!< Baudrate is not support in current clock source */ - kStatus_SPI_Timeout = MAKE_STATUS(kStatusGroup_LPC_SPI, 4) /*!< SPI timeout polling status flags. */ -}; - -/*! @brief SPI interrupt sources.*/ -enum _spi_interrupt_enable -{ - kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, /*!< Rx level interrupt */ - kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, /*!< Tx level interrupt */ -}; - -/*! @brief SPI status flags.*/ -enum _spi_statusflags -{ - kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK, /*!< txFifo is empty */ - kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK, /*!< txFifo is not full */ - kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, /*!< rxFIFO is not empty */ - kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK, /*!< rxFIFO is full */ -}; - -/*! @brief SPI transfer structure */ -typedef struct _spi_transfer -{ - uint8_t *txData; /*!< Send buffer */ - uint8_t *rxData; /*!< Receive buffer */ - uint32_t configFlags; /*!< Additional option to control transfer, @ref spi_xfer_option_t. */ - size_t dataSize; /*!< Transfer bytes */ -} spi_transfer_t; - -/*! @brief SPI half-duplex(master only) transfer structure */ -typedef struct _spi_half_duplex_transfer -{ - uint8_t *txData; /*!< Send buffer */ - uint8_t *rxData; /*!< Receive buffer */ - size_t txDataSize; /*!< Transfer bytes for transmit */ - size_t rxDataSize; /*!< Transfer bytes */ - uint32_t configFlags; /*!< Transfer configuration flags, @ref spi_xfer_option_t. */ - bool isPcsAssertInTransfer; /*!< If PCS pin keep assert between transmit and receive. true for assert and false for - deassert. */ - bool isTransmitFirst; /*!< True for transmit first and false for receive first. */ -} spi_half_duplex_transfer_t; - -/*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */ -typedef struct _spi_config -{ - spi_data_width_t dataWidth; - spi_ssel_t sselNum; -} spi_config_t; - -/*! @brief Master handle type */ -typedef struct _spi_master_handle spi_master_handle_t; - -/*! @brief Slave handle type */ -typedef spi_master_handle_t spi_slave_handle_t; - -/*! @brief SPI master callback for finished transmit */ -typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI slave callback for finished transmit */ -typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI transfer handle structure */ -struct _spi_master_handle -{ - uint8_t *volatile txData; /*!< Transfer buffer */ - uint8_t *volatile rxData; /*!< Receive buffer */ - volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */ - volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */ - volatile int8_t toReceiveCount; /*!< The number of data expected to receive in data width. Since the received count - and sent count should be the same to complete the transfer, if the sent count is - x and the received count is y, toReceiveCount is x-y. */ - size_t totalByteCount; /*!< A number of transfer bytes */ - volatile uint32_t state; /*!< SPI internal state */ - spi_master_callback_t callback; /*!< SPI callback */ - void *userData; /*!< Callback parameter */ - uint8_t dataWidth; /*!< Width of the data [Valid values: 1 to 16] */ - uint8_t sselNum; /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */ - uint32_t configFlags; /*!< Additional option to control transfer */ - uint8_t txWatermark; /*!< txFIFO watermark */ - uint8_t rxWatermark; /*!< rxFIFO watermark */ -}; - -/*! @brief Typedef for master interrupt handler. */ -typedef void (*flexcomm_spi_master_irq_handler_t)(SPI_Type *base, spi_master_handle_t *handle); - -/*! @brief Typedef for slave interrupt handler. */ -typedef void (*flexcomm_spi_slave_irq_handler_t)(SPI_Type *base, spi_slave_handle_t *handle); -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @brief Returns instance number for SPI peripheral base address. */ -uint32_t SPI_GetInstance(SPI_Type *base); - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Sets the SPI master configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). - * User may use the initialized structure unchanged in SPI_MasterInit(), or modify - * some fields of the structure before calling SPI_MasterInit(). After calling this API, - * the master is ready to transfer. - * Example: - @code - spi_master_config_t config; - SPI_MasterGetDefaultConfig(&config); - @endcode - * - * @param config pointer to master config structure - */ -void SPI_MasterGetDefaultConfig(spi_master_config_t *config); - -/*! - * @brief Initializes the SPI with master configuration. - * - * The configuration structure can be filled by user from scratch, or be set with default - * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. - * Example - @code - spi_master_config_t config = { - .baudRate_Bps = 400000, - ... - }; - SPI_MasterInit(SPI0, &config); - @endcode - * - * @param base SPI base pointer - * @param config pointer to master configuration structure - * @param srcClock_Hz Source clock frequency. - */ -status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Sets the SPI slave configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). - * Modify some fields of the structure before calling SPI_SlaveInit(). - * Example: - @code - spi_slave_config_t config; - SPI_SlaveGetDefaultConfig(&config); - @endcode - * - * @param config pointer to slave configuration structure - */ -void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config); - -/*! - * @brief Initializes the SPI with slave configuration. - * - * The configuration structure can be filled by user from scratch or be set with - * default values by SPI_SlaveGetDefaultConfig(). - * After calling this API, the slave is ready to transfer. - * Example - @code - spi_slave_config_t config = { - .polarity = flexSPIClockPolarity_ActiveHigh; - .phase = flexSPIClockPhase_FirstEdge; - .direction = flexSPIMsbFirst; - ... - }; - SPI_SlaveInit(SPI0, &config); - @endcode - * - * @param base SPI base pointer - * @param config pointer to slave configuration structure - */ -status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config); - -/*! - * @brief De-initializes the SPI. - * - * Calling this API resets the SPI module, gates the SPI clock. - * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. - * - * @param base SPI base pointer - */ -void SPI_Deinit(SPI_Type *base); - -/*! - * @brief Enable or disable the SPI Master or Slave - * @param base SPI base pointer - * @param enable or disable ( true = enable, false = disable) - */ -static inline void SPI_Enable(SPI_Type *base, bool enable) -{ - if (enable) - { - base->CFG |= SPI_CFG_ENABLE_MASK; - } - else - { - base->CFG &= ~SPI_CFG_ENABLE_MASK; - } -} - -/*! @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the status flag. - * - * @param base SPI base pointer - * @return SPI Status, use status flag to AND @ref _spi_statusflags could get the related status. - */ -static inline uint32_t SPI_GetStatusFlags(SPI_Type *base) -{ - assert(NULL != base); - return base->FIFOSTAT; -} - -/*! @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the interrupt for the SPI. - * - * @param base SPI base pointer - * @param irqs SPI interrupt source. The parameter can be any combination of the following values: - * @arg kSPI_RxLvlIrq - * @arg kSPI_TxLvlIrq - */ -static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs) -{ - assert(NULL != base); - base->FIFOINTENSET = irqs; -} - -/*! - * @brief Disables the interrupt for the SPI. - * - * @param base SPI base pointer - * @param irqs SPI interrupt source. The parameter can be any combination of the following values: - * @arg kSPI_RxLvlIrq - * @arg kSPI_TxLvlIrq - */ -static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs) -{ - assert(NULL != base); - base->FIFOINTENCLR = irqs; -} - -/*! @} */ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Enables the DMA request from SPI txFIFO. - * - * @param base SPI base pointer - * @param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableTxDMA(SPI_Type *base, bool enable); - -/*! - * @brief Enables the DMA request from SPI rxFIFO. - * - * @param base SPI base pointer - * @param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableRxDMA(SPI_Type *base, bool enable); - -/*! @} */ - -/*! - * @name Bus Operations - * @{ - */ -/*! - * @brief Returns the configurations. - * - * @param base SPI peripheral address. - * @return return configurations which contain datawidth and SSEL numbers. - * return data type is a pointer of spi_config_t. - */ -void *SPI_GetConfig(SPI_Type *base); - -/*! - * @brief Sets the baud rate for SPI transfer. This is only used in master. - * - * @param base SPI base pointer - * @param baudrate_Bps baud rate needed in Hz. - * @param srcClock_Hz SPI source clock frequency in Hz. - */ -status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Writes a data into the SPI data register. - * - * @param base SPI base pointer - * @param data needs to be write. - * @param configFlags transfer configuration options @ref spi_xfer_option_t - */ -void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags); - -/*! - * @brief Gets a data from the SPI data register. - * - * @param base SPI base pointer - * @return Data in the register. - */ -static inline uint32_t SPI_ReadData(SPI_Type *base) -{ - assert(NULL != base); - return base->FIFORD; -} - -/*! - * @brief Set delay time for transfer. - * the delay uint is SPI clock time, maximum value is 0xF. - * @param base SPI base pointer - * @param config configuration for delay option @ref spi_delay_config_t. - */ -static inline void SPI_SetTransferDelay(SPI_Type *base, const spi_delay_config_t *config) -{ - assert(NULL != base); - assert(NULL != config); - base->DLY = (SPI_DLY_PRE_DELAY(config->preDelay) | SPI_DLY_POST_DELAY(config->postDelay) | - SPI_DLY_FRAME_DELAY(config->frameDelay) | SPI_DLY_TRANSFER_DELAY(config->transferDelay)); -} - -/*! - * @brief Set up the dummy data. - * - * @param base SPI peripheral address. - * @param dummyData Data to be transferred when tx buffer is NULL. - */ -void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData); - -/*! @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the SPI master handle. - * - * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback Callback function. - * @param userData User data. - */ -status_t SPI_MasterTransferCreateHandle(SPI_Type *base, - spi_master_handle_t *handle, - spi_master_callback_t callback, - void *userData); - -/*! - * @brief Transfers a block of data using a polling method. - * - * @param base SPI base pointer - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Timeout The transfer timed out and was aborted. - */ -status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer); - -/*! - * @brief Performs a non-blocking SPI interrupt transfer. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer); - -/*! - * @brief Transfers a block of data using a polling method. - * - * This function will do a half-duplex transfer for SPI master, This is a blocking function, - * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, - * users can set transmit first or receive first. - * - * @param base SPI base pointer - * @param xfer pointer to spi_half_duplex_transfer_t structure - * @return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer); - -/*! - * @brief Performs a non-blocking SPI interrupt transfer. - * - * This function using polling way to do the first half transimission and using interrupts to - * do the second half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_half_duplex_transfer_t structure - * @return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, - spi_master_handle_t *handle, - spi_half_duplex_transfer_t *xfer); - -/*! - * @brief Gets the master transfer count. - * - * This function gets the master transfer count. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * @param count The number of bytes transferred by using the non-blocking transaction. - * @return status of status_t. - */ -status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count); - -/*! - * @brief SPI master aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle); - -/*! - * @brief Interrupts the handler for the SPI. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle); - -/*! - * @brief Initializes the SPI slave handle. - * - * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback Callback function. - * @param userData User data. - */ -static inline status_t SPI_SlaveTransferCreateHandle(SPI_Type *base, - spi_slave_handle_t *handle, - spi_slave_callback_t callback, - void *userData) -{ - return SPI_MasterTransferCreateHandle(base, handle, callback, userData); -} - -/*! - * @brief Performs a non-blocking SPI slave interrupt transfer. - * - * @note The API returns immediately after the transfer initialization is finished. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer) -{ - return SPI_MasterTransferNonBlocking(base, handle, xfer); -} - -/*! - * @brief Gets the slave transfer count. - * - * This function gets the slave transfer count. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * @param count The number of bytes transferred by using the non-blocking transaction. - * @return status of status_t. - */ -static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count) -{ - return SPI_MasterTransferGetCount(base, (spi_master_handle_t *)handle, count); -} - -/*! - * @brief SPI slave aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state. - */ -static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle) -{ - SPI_MasterTransferAbort(base, (spi_master_handle_t *)handle); -} - -/*! - * @brief Interrupts a handler for the SPI slave. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_slave_handle_t structure which stores the transfer state - */ -static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle) -{ - SPI_MasterTransferHandleIRQ(base, handle); -} - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_SPI_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.c deleted file mode 100644 index ed0aaa6a9fa..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.c +++ /dev/null @@ -1,568 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_spi_dma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi_dma" -#endif - -/*configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; - *fifowr |= ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; -} - -static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr) -{ - *fifowr |= ((uint32_t)SPI_DEASSERT_ALL & (~(uint32_t)SPI_DEASSERTNUM_SSEL((uint32_t)config->sselNum))); - /* set width of data - range asserted at entry */ - *fifowr |= SPI_FIFOWR_LEN(config->dataWidth); -} - -static void PrepareTxLastWord(spi_transfer_t *xfer, uint32_t *txLastWord, spi_config_t *config) -{ - if (config->dataWidth > kSPI_Data8Bits) - { - *txLastWord = (((uint32_t)xfer->txData[xfer->dataSize - 1U] << 8U) | (xfer->txData[xfer->dataSize - 2U])); - } - else - { - *txLastWord = xfer->txData[xfer->dataSize - 1U]; - } - XferToFifoWR(xfer, txLastWord); - SpiConfigToFifoWR(config, txLastWord); -} - -static void SPI_SetupDummy(SPI_Type *base, spi_dma_txdummy_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p) -{ - uint32_t instance = SPI_GetInstance(base); - uint32_t dummydata = (uint32_t)s_dummyData[instance]; - dummydata |= (uint32_t)s_dummyData[instance] << 8U; - - dummy->word = dummydata; - dummy->lastWord = dummydata; - - XferToFifoWR(xfer, &dummy->word); - XferToFifoWR(xfer, &dummy->lastWord); - SpiConfigToFifoWR(spi_config_p, &dummy->word); - SpiConfigToFifoWR(spi_config_p, &dummy->lastWord); - /* Clear the end of transfer bit for continue word transfer. */ - dummy->word &= (~(uint32_t)kSPI_FrameAssert); -} - -/*! - * brief Initialize the SPI master DMA handle. - * - * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * param base SPI peripheral base address. - * param handle SPI handle pointer. - * param callback User callback function called at the end of a transfer. - * param userData User data for callback. - * param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle) -{ - uint32_t instance; - - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } - /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - instance = SPI_GetInstance(base); - - (void)memset(handle, 0, sizeof(*handle)); - /* Set spi base to handle */ - handle->txHandle = txHandle; - handle->rxHandle = rxHandle; - handle->callback = callback; - handle->userData = userData; - - /* Set SPI state to idle */ - handle->state = (uint8_t)kSPI_Idle; - - /* Set handle to global state */ - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - /* Install callback for Tx dma channel */ - DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]); - DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]); - - return kStatus_Success; -} - -/*! - * brief Perform a non-blocking SPI transfer using DMA. - * - * note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * param base SPI peripheral base address. - * param handle SPI DMA handle pointer. - * param xfer Pointer to dma transfer structure. - * retval kStatus_Success Successfully start a transfer. - * retval kStatus_InvalidArgument Input argument is invalid. - * retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) -{ - assert(!((NULL == handle) || (NULL == xfer))); - - uint32_t instance; - status_t result = kStatus_Success; - spi_config_t *spi_config_p; - uint32_t address; - - if ((NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - - /* Byte size is zero. */ - if (xfer->dataSize == 0U) - { - return kStatus_InvalidArgument; - } - /* cannot get instance from base address */ - instance = SPI_GetInstance(base); - - /* Check if the device is busy */ - if (handle->state == (uint8_t)kSPI_Busy) - { - return kStatus_SPI_Busy; - } - else - { - /* Clear FIFOs before transfer. */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - - dma_transfer_config_t xferConfig = {0}; - spi_config_p = (spi_config_t *)SPI_GetConfig(base); - - handle->state = (uint8_t)kSPI_Busy; - handle->transferSize = xfer->dataSize; - - /* receive */ - SPI_EnableRxDMA(base, true); - address = (uint32_t)&base->FIFORD; - if (xfer->rxData != NULL) - { - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, xfer->rxData, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_PeripheralToMemory, NULL); - } - else - { - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, &s_rxDummy, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_StaticToStatic, NULL); - } - (void)DMA_SubmitTransfer(handle->rxHandle, &xferConfig); - handle->rxInProgress = true; - DMA_StartTransfer(handle->rxHandle); - - /* transmit */ - SPI_EnableTxDMA(base, true); - address = (uint32_t)&base->FIFOWR; - if (xfer->txData != NULL) - { - if ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) - { - PrepareTxLastWord(xfer, &s_txLastWord[instance], spi_config_p); - } - /* If end of tranfer function is enabled and data transfer frame is bigger then 1, use dma - * descriptor to send the last data. - */ - if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2U) : (xfer->dataSize > 1U))) - { - dma_xfercfg_t tmp_xfercfg; - tmp_xfercfg.valid = true; - tmp_xfercfg.swtrig = true; - tmp_xfercfg.intA = true; - tmp_xfercfg.byteWidth = 4U; - tmp_xfercfg.srcInc = 0; - tmp_xfercfg.dstInc = 0; - tmp_xfercfg.transferCount = 1; - tmp_xfercfg.reload = false; - tmp_xfercfg.clrtrig = false; - tmp_xfercfg.intB = false; - /* Create chained descriptor to transmit last word */ - DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txLastWord[instance], - (uint32_t *)address, NULL); - - DMA_PrepareTransfer( - &xferConfig, xfer->txData, (uint32_t *)address, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2U) : (xfer->dataSize - 1U)), - kDMA_MemoryToPeripheral, &s_spi_descriptor_table[instance]); - /* Disable interrupts for first descriptor to avoid calling callback twice. */ - xferConfig.xfercfg.intA = false; - xferConfig.xfercfg.intB = false; - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - else - { - DMA_PrepareTransfer( - &xferConfig, xfer->txData, (uint32_t *)address, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_MemoryToPeripheral, NULL); - (void)DMA_SubmitTransfer(handle->txHandle, &xferConfig); - } - } - else - { - /* Setup tx dummy data. */ - SPI_SetupDummy(base, &s_txDummy[instance], xfer, spi_config_p); - if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2U) : (xfer->dataSize > 1U))) - { - dma_xfercfg_t tmp_xfercfg; - tmp_xfercfg.valid = true; - tmp_xfercfg.swtrig = true; - tmp_xfercfg.intA = true; - tmp_xfercfg.byteWidth = (uint8_t)sizeof(uint32_t); - tmp_xfercfg.srcInc = 0; - tmp_xfercfg.dstInc = 0; - tmp_xfercfg.transferCount = 1; - tmp_xfercfg.reload = false; - tmp_xfercfg.clrtrig = false; - tmp_xfercfg.intB = false; - /* Create chained descriptor to transmit last word */ - DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord, - (uint32_t *)address, NULL); - /* Use common API to setup first descriptor */ - DMA_PrepareTransfer( - &xferConfig, &s_txDummy[instance].word, (uint32_t *)address, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2U) : (xfer->dataSize - 1U)), - kDMA_StaticToStatic, &s_spi_descriptor_table[instance]); - /* Disable interrupts for first descriptor to avoid calling callback twice */ - xferConfig.xfercfg.intA = false; - xferConfig.xfercfg.intB = false; - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - else - { - DMA_PrepareTransfer( - &xferConfig, &s_txDummy[instance].word, (uint32_t *)address, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_StaticToStatic, NULL); - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - } - - handle->txInProgress = true; - uint32_t tmpData = 0U; - uint32_t writeAddress = (uint32_t) & (base->FIFOWR) + 2UL; - XferToFifoWR(xfer, &tmpData); - SpiConfigToFifoWR(spi_config_p, &tmpData); - - /* Setup the control info. - * Halfword writes to just the control bits (offset 0xE22) doesn't push anything into the FIFO. - * And the data access type of control bits must be uint16_t, byte writes or halfword writes to FIFOWR - * will push the data and the current control bits into the FIFO. - */ - if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize == 2U) : (xfer->dataSize == 1U))) - { - *(uint16_t *)writeAddress = (uint16_t)(tmpData >> 16U); - } - else - { - /* Clear the SPI_FIFOWR_EOT_MASK bit when data is not the last. */ - tmpData &= (~(uint32_t)kSPI_FrameAssert); - *(uint16_t *)writeAddress = (uint16_t)(tmpData >> 16U); - } - - DMA_StartTransfer(handle->txHandle); - } - - return result; -} - -/*! - * brief Transfers a block of data using a DMA method. - * - * This function using polling way to do the first half transimission and using DMA way to - * do the srcond half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * param base SPI base pointer - * param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. - * param transfer A pointer to the spi_half_duplex_transfer_t structure. - * return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer) -{ - assert((xfer != NULL) && (handle != NULL)); - spi_transfer_t tempXfer = {0}; - status_t status; - - if (xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the pcs pin keep assert between transmit and receive. */ - if (xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); - } - else - { - tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; - } - - status = SPI_MasterTransferBlocking(base, &tempXfer); - if (status != kStatus_Success) - { - return status; - } - - if (xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - status = SPI_MasterTransferDMA(base, handle, &tempXfer); - - return status; -} - -static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) -{ - spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; - spi_dma_handle_t *spiHandle = privHandle->handle; - SPI_Type *base = privHandle->base; - - /* change the state */ - spiHandle->rxInProgress = false; - - /* All finished, call the callback */ - if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) - { - spiHandle->state = (uint8_t)kSPI_Idle; - if (spiHandle->callback != NULL) - { - (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); - } - } -} - -static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) -{ - spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; - spi_dma_handle_t *spiHandle = privHandle->handle; - SPI_Type *base = privHandle->base; - - /* change the state */ - spiHandle->txInProgress = false; - - /* All finished, call the callback */ - if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) - { - spiHandle->state = (uint8_t)kSPI_Idle; - if (spiHandle->callback != NULL) - { - (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); - } - } -} - -/*! - * brief Abort a SPI transfer using DMA. - * - * param base SPI peripheral base address. - * param handle SPI DMA handle pointer. - */ -void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) -{ - assert(NULL != handle); - - /* Stop tx transfer first */ - DMA_AbortTransfer(handle->txHandle); - /* Then rx transfer */ - DMA_AbortTransfer(handle->rxHandle); - - /* Set the handle state */ - handle->txInProgress = false; - handle->rxInProgress = false; - handle->state = (uint8_t)kSPI_Idle; -} - -/*! - * brief Gets the master DMA transfer remaining bytes. - * - * This function gets the master DMA transfer remaining bytes. - * - * param base SPI peripheral base address. - * param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * param count A number of bytes transferred by the non-blocking transaction. - * return status of status_t. - */ -status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) -{ - assert(handle != NULL); - - if (NULL == count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != (uint8_t)kSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - size_t bytes; - - bytes = DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel); - - *count = handle->transferSize - bytes; - - return kStatus_Success; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.h deleted file mode 100644 index 614c37d791a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SPI_DMA_H_ -#define _FSL_SPI_DMA_H_ - -#include "fsl_dma.h" -#include "fsl_spi.h" - -/*! - * @addtogroup spi_dma_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SPI DMA driver version 2.1.1. */ -#define FSL_SPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) -/*@}*/ - -typedef struct _spi_dma_handle spi_dma_handle_t; - -/*! @brief SPI DMA callback called at the end of transfer. */ -typedef void (*spi_dma_callback_t)(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI DMA transfer handle, users should not touch the content of the handle.*/ -struct _spi_dma_handle -{ - volatile bool txInProgress; /*!< Send transfer finished */ - volatile bool rxInProgress; /*!< Receive transfer finished */ - dma_handle_t *txHandle; /*!< DMA handler for SPI send */ - dma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ - uint8_t bytesPerFrame; /*!< Bytes in a frame for SPI transfer */ - spi_dma_callback_t callback; /*!< Callback for SPI DMA transfer */ - void *userData; /*!< User Data for SPI DMA callback */ - uint32_t state; /*!< Internal state of SPI DMA transfer */ - size_t transferSize; /*!< Bytes need to be transfer */ -}; - -/******************************************************************************* - * APIs - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name DMA Transactional - * @{ - */ - -/*! - * @brief Initialize the SPI master DMA handle. - * - * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback User callback function called at the end of a transfer. - * @param userData User data for callback. - * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle); - -/*! - * @brief Perform a non-blocking SPI transfer using DMA. - * - * @note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - * @param xfer Pointer to dma transfer structure. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer); - -/*! - * @brief Transfers a block of data using a DMA method. - * - * This function using polling way to do the first half transimission and using DMA way to - * do the srcond half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * @param base SPI base pointer - * @param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. - * @param xfer A pointer to the spi_half_duplex_transfer_t structure. - * @return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer); - -/*! - * @brief Initialize the SPI slave DMA handle. - * - * This function initializes the SPI slave DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback User callback function called at the end of a transfer. - * @param userData User data for callback. - * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -static inline status_t SPI_SlaveTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle) -{ - return SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle); -} - -/*! - * @brief Perform a non-blocking SPI transfer using DMA. - * - * @note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - * @param xfer Pointer to dma transfer structure. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -static inline status_t SPI_SlaveTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) -{ - return SPI_MasterTransferDMA(base, handle, xfer); -} - -/*! - * @brief Abort a SPI transfer using DMA. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - */ -void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle); - -/*! - * @brief Gets the master DMA transfer remaining bytes. - * - * This function gets the master DMA transfer remaining bytes. - * - * @param base SPI peripheral base address. - * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * @param count A number of bytes transferred by the non-blocking transaction. - * @return status of status_t. - */ -status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count); - -/*! - * @brief Abort a SPI transfer using DMA. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - */ -static inline void SPI_SlaveTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) -{ - SPI_MasterTransferAbortDMA(base, handle); -} - -/*! - * @brief Gets the slave DMA transfer remaining bytes. - * - * This function gets the slave DMA transfer remaining bytes. - * - * @param base SPI peripheral base address. - * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * @param count A number of bytes transferred by the non-blocking transaction. - * @return status of status_t. - */ -static inline status_t SPI_SlaveTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) -{ - return SPI_MasterTransferGetCountDMA(base, handle, count); -} - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_SPI_DMA_H_*/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_freertos.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_freertos.c deleted file mode 100644 index 8250107418d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_freertos.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_spi_freertos.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi_freertos" -#endif - -static void SPI_RTOS_Callback(SPI_Type *base, spi_master_handle_t *drv_handle, status_t status, void *userData) -{ - spi_rtos_handle_t *handle = (spi_rtos_handle_t *)userData; - BaseType_t reschedule; - handle->async_status = status; - (void)xSemaphoreGiveFromISR(handle->event, &reschedule); - portYIELD_FROM_ISR(reschedule); -} - -/*! - * brief Initializes SPI. - * - * This function initializes the SPI module and related RTOS context. - * - * param handle The RTOS SPI handle, the pointer to an allocated space for RTOS context. - * param base The pointer base address of the SPI instance to initialize. - * param masterConfig Configuration structure to set-up SPI in master mode. - * param srcClock_Hz Frequency of input clock of the SPI module. - * return status of the operation. - */ -status_t SPI_RTOS_Init(spi_rtos_handle_t *handle, - SPI_Type *base, - const spi_master_config_t *masterConfig, - uint32_t srcClock_Hz) -{ - status_t status; - - if (handle == NULL) - { - return kStatus_InvalidArgument; - } - - if (base == NULL) - { - return kStatus_InvalidArgument; - } - - (void)memset(handle, 0, sizeof(spi_rtos_handle_t)); - - handle->mutex = xSemaphoreCreateMutex(); - if (handle->mutex == NULL) - { - return kStatus_Fail; - } - - handle->event = xSemaphoreCreateBinary(); - if (handle->event == NULL) - { - vSemaphoreDelete(handle->mutex); - return kStatus_Fail; - } - - handle->base = base; - - (void)SPI_MasterInit(handle->base, masterConfig, srcClock_Hz); - status = SPI_MasterTransferCreateHandle(handle->base, &handle->drv_handle, SPI_RTOS_Callback, (void *)handle); - - return status; -} - -/*! - * brief Deinitializes the SPI. - * - * This function deinitializes the SPI module and related RTOS context. - * - * param handle The RTOS SPI handle. - */ -status_t SPI_RTOS_Deinit(spi_rtos_handle_t *handle) -{ - SPI_Deinit(handle->base); - vSemaphoreDelete(handle->event); - vSemaphoreDelete(handle->mutex); - - return kStatus_Success; -} - -/*! - * brief Performs SPI transfer. - * - * This function performs an SPI transfer according to data given in the transfer structure. - * - * param handle The RTOS SPI handle. - * param transfer Structure specifying the transfer parameters. - * return status of the operation. - */ -status_t SPI_RTOS_Transfer(spi_rtos_handle_t *handle, spi_transfer_t *transfer) -{ - status_t status; - - /* Lock resource mutex */ - if (xSemaphoreTake(handle->mutex, portMAX_DELAY) != pdTRUE) - { - return kStatus_SPI_Busy; - } - - /* Initiate transfer */ - status = SPI_MasterTransferNonBlocking(handle->base, &handle->drv_handle, transfer); - if (status != kStatus_Success) - { - (void)xSemaphoreGive(handle->mutex); - return status; - } - - /* Wait for transfer to finish */ - if (xSemaphoreTake(handle->event, portMAX_DELAY) != pdTRUE) - { - return kStatus_SPI_Error; - } - - /* Retrieve status before releasing mutex */ - status = handle->async_status; - - /* Unlock resource mutex */ - (void)xSemaphoreGive(handle->mutex); - - /* Translate status of underlying driver */ - if (status == kStatus_SPI_Idle) - { - status = kStatus_Success; - } - - return status; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_freertos.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_freertos.h deleted file mode 100644 index c5a0efa2cc8..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_freertos.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef __FSL_SPI_FREERTOS_H__ -#define __FSL_SPI_FREERTOS_H__ - -#include "FreeRTOS.h" -#include "portable.h" -#include "semphr.h" - -#include "fsl_spi.h" - -/*! - * @addtogroup spi_freertos_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SPI FreeRTOS driver version 2.1.0. */ -#define FSL_SPI_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) -/*@}*/ - -/*! @brief SPI FreeRTOS handle */ -typedef struct _spi_rtos_handle -{ - SPI_Type *base; /*!< SPI base address */ - spi_master_handle_t drv_handle; /*!< Handle of the underlying driver, treated as opaque by the RTOS layer */ - status_t async_status; - SemaphoreHandle_t mutex; /*!< Mutex to lock the handle during a trasfer */ - SemaphoreHandle_t event; /*!< Semaphore to notify and unblock task when transfer ends */ -} spi_rtos_handle_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name SPI RTOS Operation - * @{ - */ - -/*! - * @brief Initializes SPI. - * - * This function initializes the SPI module and related RTOS context. - * - * @param handle The RTOS SPI handle, the pointer to an allocated space for RTOS context. - * @param base The pointer base address of the SPI instance to initialize. - * @param masterConfig Configuration structure to set-up SPI in master mode. - * @param srcClock_Hz Frequency of input clock of the SPI module. - * @return status of the operation. - */ -status_t SPI_RTOS_Init(spi_rtos_handle_t *handle, - SPI_Type *base, - const spi_master_config_t *masterConfig, - uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes the SPI. - * - * This function deinitializes the SPI module and related RTOS context. - * - * @param handle The RTOS SPI handle. - */ -status_t SPI_RTOS_Deinit(spi_rtos_handle_t *handle); - -/*! - * @brief Performs SPI transfer. - * - * This function performs an SPI transfer according to data given in the transfer structure. - * - * @param handle The RTOS SPI handle. - * @param transfer Structure specifying the transfer parameters. - * @return status of the operation. - */ -status_t SPI_RTOS_Transfer(spi_rtos_handle_t *handle, spi_transfer_t *transfer); - -/*! - * @} - */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* __FSL_SPI_FREERTOS_H__ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sysctl.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sysctl.c deleted file mode 100644 index 1d0dd9ccf64..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sysctl.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sysctl.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.sysctl" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get the instance. - * - * @param base SYSCTL peripheral base address. - * @return Instance number. - */ -static uint32_t SYSCTL_GetInstance(SYSCTL_Type *base); - -/*! - * @brief Enable SYSCTL write protect - * - * @param base SYSCTL peripheral base address. - * @param regAddr register address - * @param value value to write. - */ -static void SYSCTL_UpdateRegister(SYSCTL_Type *base, volatile uint32_t *regAddr, uint32_t value); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief SYSCTL base address array name */ -static SYSCTL_Type *const s_sysctlBase[] = SYSCTL_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief SYSCTL clock array name */ -static const clock_ip_name_t s_sysctlClock[] = SYSCTL_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static void SYSCTL_UpdateRegister(SYSCTL_Type *base, volatile uint32_t *regAddr, uint32_t value) -{ - base->UPDATELCKOUT &= ~SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK; - *regAddr = value; - base->UPDATELCKOUT |= SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK; -} - -static uint32_t SYSCTL_GetInstance(SYSCTL_Type *base) -{ - uint8_t instance = 0; - - while ((instance < ARRAY_SIZE(s_sysctlBase)) && (s_sysctlBase[instance] != base)) - { - instance++; - } - - assert(instance < ARRAY_SIZE(s_sysctlBase)); - - return instance; -} - -/*! - * @brief SYSCTL initial - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Init(SYSCTL_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable SYSCTL clock. */ - CLOCK_EnableClock(s_sysctlClock[SYSCTL_GetInstance(base)]); -#endif -} - -/*! - * @brief SYSCTL deinit - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Deinit(SYSCTL_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable SYSCTL clock. */ - CLOCK_DisableClock(s_sysctlClock[SYSCTL_GetInstance(base)]); -#endif -} - -/*! - * @brief SYSCTL share set configure for separate signal - * - * @param base Base address of the SYSCTL peripheral - * @param flexCommIndex index of flexcomm,reference _sysctl_share_src - * @param setIndex share set for sck, reference _sysctl_share_set_index - * - */ -void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set) -{ - uint32_t tempReg = base->FCCTRLSEL[flexCommIndex]; - - tempReg &= ~((uint32_t)SYSCTL_FCCTRLSEL_SCKINSEL_MASK << (uint32_t)signal); - tempReg |= (set + 1U) << (uint32_t)signal; - - SYSCTL_UpdateRegister(base, &base->FCCTRLSEL[flexCommIndex], tempReg); -} - -/*! - * @brief SYSCTL share set configure for flexcomm - * - * @param base Base address of the SYSCTL peripheral. - * @param flexCommIndex index of flexcomm, reference _sysctl_share_src - * @param sckSet share set for sck,reference _sysctl_share_set_index - * @param wsSet share set for ws, reference _sysctl_share_set_index - * @param dataInSet share set for data in, reference _sysctl_share_set_index - * @param dataOutSet share set for data out, reference _sysctl_share_set_index - * - */ -void SYSCTL_SetFlexcommShareSet( - SYSCTL_Type *base, uint32_t flexCommIndex, uint32_t sckSet, uint32_t wsSet, uint32_t dataInSet, uint32_t dataOutSet) -{ - uint32_t tempReg = base->FCCTRLSEL[flexCommIndex]; - - tempReg &= ~(SYSCTL_FCCTRLSEL_SCKINSEL_MASK | SYSCTL_FCCTRLSEL_WSINSEL_MASK | SYSCTL_FCCTRLSEL_DATAINSEL_MASK | - SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK); - tempReg |= SYSCTL_FCCTRLSEL_SCKINSEL(sckSet + 1U) | SYSCTL_FCCTRLSEL_WSINSEL(wsSet + 1U) | - SYSCTL_FCCTRLSEL_DATAINSEL(dataInSet + 1U) | SYSCTL_FCCTRLSEL_DATAOUTSEL(dataOutSet + 1U); - - SYSCTL_UpdateRegister(base, &base->FCCTRLSEL[flexCommIndex], tempReg); -} - -/*! - * @brief SYSCTL share set source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param sckShareSrc sck source for this share set,reference _sysctl_share_src - * @param wsShareSrc ws source for this share set,reference _sysctl_share_src - * @param dataInShareSrc data in source for this share set,reference _sysctl_share_src - * @param dataOutShareSrc data out source for this share set,reference _sysctl_dataout_mask - * - */ -void SYSCTL_SetShareSetSrc(SYSCTL_Type *base, - uint32_t setIndex, - uint32_t sckShareSrc, - uint32_t wsShareSrc, - uint32_t dataInShareSrc, - uint32_t dataOutShareSrc) -{ - uint32_t tempReg = base->SHAREDCTRLSET[setIndex]; - - /* WS,SCK,DATA IN */ - tempReg &= ~(SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK | SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK | - SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK); - tempReg |= SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(sckShareSrc) | SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(wsShareSrc) | - SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(dataInShareSrc); - - /* data out */ - tempReg &= ~(SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK | SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK | - SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK | SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK | - SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK); - tempReg |= dataOutShareSrc; - - SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg); -} - -/*! - * @brief SYSCTL sck source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param sckShareSrc sck source fro this share set,reference _sysctl_share_src - * - */ -void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base, - uint32_t setIndex, - sysctl_sharedctrlset_signal_t signal, - uint32_t shareSrc) -{ - uint32_t tempReg = base->SHAREDCTRLSET[setIndex]; - - if (signal == kSYSCTL_SharedCtrlSignalDataOut) - { - tempReg |= 1UL << ((uint32_t)signal + shareSrc); - } - else - { - tempReg &= ~((uint32_t)SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK << (uint32_t)signal); - tempReg |= shareSrc << (uint32_t)signal; - } - - SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg); -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sysctl.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sysctl.h deleted file mode 100644 index 0a1be88469c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sysctl.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_SYSCTL_H_ -#define _FSL_SYSCTL_H_ - -#include "fsl_common.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup sysctl - * @{ - */ - -/*! @file */ -/*! @file fsl_sysctl.h */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Group sysctl driver version for SDK */ -#define FSL_SYSCTL_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) /*!< Version 2.0.5. */ -/*@}*/ - -/*! @brief SYSCTL share set*/ -enum _sysctl_share_set_index -{ - kSYSCTL_ShareSet0 = 0, /*!< share set 0 */ - kSYSCTL_ShareSet1 = 1, /*!< share set 1 */ -}; - -/*! @brief SYSCTL flexcomm signal */ -typedef enum _sysctl_fcctrlsel_signal -{ - kSYSCTL_FlexcommSignalSCK = SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT, /*!< SCK signal */ - kSYSCTL_FlexcommSignalWS = SYSCTL_FCCTRLSEL_WSINSEL_SHIFT, /*!< WS signal */ - kSYSCTL_FlexcommSignalDataIn = SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT, /*!< Data in signal */ - kSYSCTL_FlexcommSignalDataOut = SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT, /*!< Data out signal */ -} sysctl_fcctrlsel_signal_t; - -/*! @brief SYSCTL flexcomm index*/ -enum _sysctl_share_src -{ - kSYSCTL_Flexcomm0 = 0, /*!< share set 0 */ - kSYSCTL_Flexcomm1 = 1, /*!< share set 1 */ - kSYSCTL_Flexcomm2 = 2, /*!< share set 2 */ - kSYSCTL_Flexcomm4 = 4, /*!< share set 4 */ - kSYSCTL_Flexcomm5 = 5, /*!< share set 5 */ - kSYSCTL_Flexcomm6 = 6, /*!< share set 6 */ - kSYSCTL_Flexcomm7 = 7, /*!< share set 7 */ -}; - -/*! @brief SYSCTL shared data out mask */ -enum _sysctl_dataout_mask -{ - kSYSCTL_Flexcomm0DataOut = SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK, /*!< share set 0 */ - kSYSCTL_Flexcomm1DataOut = SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK, /*!< share set 1 */ - kSYSCTL_Flexcomm2DataOut = SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK, /*!< share set 2 */ - kSYSCTL_Flexcomm4DataOut = SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK, /*!< share set 4 */ - kSYSCTL_Flexcomm5DataOut = SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK, /*!< share set 5 */ - kSYSCTL_Flexcomm6DataOut = SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK, /*!< share set 6 */ - kSYSCTL_Flexcomm7DataOut = SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK, /*!< share set 7 */ -}; - -/*! @brief SYSCTL flexcomm signal */ -typedef enum _sysctl_sharedctrlset_signal -{ - kSYSCTL_SharedCtrlSignalSCK = SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT, /*!< SCK signal */ - kSYSCTL_SharedCtrlSignalWS = SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT, /*!< WS signal */ - kSYSCTL_SharedCtrlSignalDataIn = SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT, /*!< Data in signal */ - kSYSCTL_SharedCtrlSignalDataOut = SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT, /*!< Data out signal */ -} sysctl_sharedctrlset_signal_t; -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief SYSCTL initial - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Init(SYSCTL_Type *base); - -/*! - * @brief SYSCTL deinit - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Deinit(SYSCTL_Type *base); - -/* @} */ - -/*! - * @name SYSCTL share signal configure - * @{ - */ - -/*! - * @brief SYSCTL share set configure for flexcomm - * - * @param base Base address of the SYSCTL peripheral. - * @param flexCommIndex index of flexcomm, reference _sysctl_share_src - * @param sckSet share set for sck,reference _sysctl_share_set_index - * @param wsSet share set for ws, reference _sysctl_share_set_index - * @param dataInSet share set for data in, reference _sysctl_share_set_index - * @param dataOutSet share set for data out, reference _sysctl_dataout_mask - * - */ -void SYSCTL_SetFlexcommShareSet(SYSCTL_Type *base, - uint32_t flexCommIndex, - uint32_t sckSet, - uint32_t wsSet, - uint32_t dataInSet, - uint32_t dataOutSet); - -/*! - * @brief SYSCTL share set configure for separate signal - * - * @param base Base address of the SYSCTL peripheral - * @param flexCommIndex index of flexcomm,reference _sysctl_share_src - * @param signal FCCTRLSEL signal shift - * @param set share set for sck, reference _sysctl_share_set_index - * - */ -void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set); - -/*! - * @brief SYSCTL share set source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param sckShareSrc sck source for this share set,reference _sysctl_share_src - * @param wsShareSrc ws source for this share set,reference _sysctl_share_src - * @param dataInShareSrc data in source for this share set,reference _sysctl_share_src - * @param dataOutShareSrc data out source for this share set,reference _sysctl_dataout_mask - * - */ -void SYSCTL_SetShareSetSrc(SYSCTL_Type *base, - uint32_t setIndex, - uint32_t sckShareSrc, - uint32_t wsShareSrc, - uint32_t dataInShareSrc, - uint32_t dataOutShareSrc); - -/*! - * @brief SYSCTL sck source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param signal FCCTRLSEL signal shift - * @param shareSrc sck source fro this share set,reference _sysctl_share_src - * - */ -void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base, - uint32_t setIndex, - sysctl_sharedctrlset_signal_t signal, - uint32_t shareSrc); - -/* @} */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_SYSCTL_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart.c deleted file mode 100644 index 3286174f27b..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart.c +++ /dev/null @@ -1,1206 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_usart.h" -#include "fsl_device_registers.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart" -#endif - -/*! - * @brief Used for conversion from `flexcomm_usart_irq_handler_t` to `flexcomm_irq_handler_t` - */ -typedef union usart_to_flexcomm -{ - flexcomm_usart_irq_handler_t usart_master_handler; - flexcomm_irq_handler_t flexcomm_handler; -} usart_to_flexcomm_t; - -enum -{ - kUSART_TxIdle, /* TX idle. */ - kUSART_TxBusy, /* TX busy. */ - kUSART_RxIdle, /* RX idle. */ - kUSART_RxBusy /* RX busy. */ -}; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief IRQ name array */ -static const IRQn_Type s_usartIRQ[] = USART_IRQS; - -/*! @brief Array to map USART instance number to base address. */ -static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Get the index corresponding to the USART */ -/*! brief Returns instance number for USART peripheral base address. */ -uint32_t USART_GetInstance(USART_Type *base) -{ - uint32_t i; - - for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT; i++) - { - if ((uint32_t)base == s_usartBaseAddrs[i]) - { - break; - } - } - - assert(i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT); - return i; -} - -/*! - * brief Get the length of received data in RX ring buffer. - * - * param handle USART handle pointer. - * return Length of received data in RX ring buffer. - */ -size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) -{ - size_t size; - - /* Check arguments */ - assert(NULL != handle); - uint16_t rxRingBufferHead = handle->rxRingBufferHead; - uint16_t rxRingBufferTail = handle->rxRingBufferTail; - - if (rxRingBufferTail > rxRingBufferHead) - { - size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail; - } - else - { - size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail; - } - return size; -} - -static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle) -{ - bool full; - - /* Check arguments */ - assert(NULL != handle); - - if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) - { - full = true; - } - else - { - full = false; - } - return full; -} - -/*! - * brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific USART handle. - * - * When the RX ring buffer is used, data received are stored into the ring buffer even when the - * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * - * note When using the RX ring buffer, one byte is reserved for internal use. In other - * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. - * param ringBufferSize size of the ring buffer. - */ -void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) -{ - /* Check arguments */ - assert(NULL != base); - assert(NULL != handle); - assert(NULL != ringBuffer); - - /* Setup the ringbuffer address */ - handle->rxRingBuffer = ringBuffer; - handle->rxRingBufferSize = ringBufferSize; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; - /* ring buffer is ready we can start receiving data */ - base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -} - -/*! - * brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) -{ - /* Check arguments */ - assert(NULL != base); - assert(NULL != handle); - - if (handle->rxState == (uint8_t)kUSART_RxIdle) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK; - } - handle->rxRingBuffer = NULL; - handle->rxRingBufferSize = 0U; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; -} - -/*! - * brief Initializes a USART instance with user configuration structure and peripheral clock. - * - * This function configures the USART module with the user-defined settings. The user can configure the configuration - * structure and also get the default configuration by using the USART_GetDefaultConfig() function. - * Example below shows how to use this API to configure USART. - * code - * usart_config_t usartConfig; - * usartConfig.baudRate_Bps = 115200U; - * usartConfig.parityMode = kUSART_ParityDisabled; - * usartConfig.stopBitCount = kUSART_OneStopBit; - * USART_Init(USART1, &usartConfig, 20000000U); - * endcode - * - * param base USART peripheral base address. - * param config Pointer to user-defined configuration structure. - * param srcClock_Hz USART clock source frequency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_InvalidArgument USART base address is not valid - * retval kStatus_Success Status USART initialize succeed - */ -status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz) -{ - int result; - - /* check arguments */ - assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); - if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* initialize flexcomm to USART mode */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART); - if (kStatus_Success != result) - { - return result; - } - - if (config->enableTx) - { - /* empty and enable txFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK; - /* setup trigger level */ - base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK); - base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark); - /* enable trigger interrupt */ - base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK; - } - - /* empty and enable rxFIFO */ - if (config->enableRx) - { - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK; - /* setup trigger level */ - base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK); - base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable trigger interrupt */ - base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK; - } - /* setup configuration and enable USART */ - base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | - USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | - USART_CFG_SYNCEN((uint32_t)config->syncMode >> 1) | USART_CFG_SYNCMST((uint8_t)config->syncMode) | - USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_MODE32K(config->enableMode32k) | - USART_CFG_CTSEN(config->enableHardwareFlowControl) | USART_CFG_ENABLE_MASK; - - /* Setup baudrate */ - if (config->enableMode32k) - { - if ((9600U % config->baudRate_Bps) == 0U) - { - base->BRG = 9600U / config->baudRate_Bps; - } - else - { - return kStatus_USART_BaudrateNotSupport; - } - } - else - { - result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - } - /* Setting continuous Clock configuration. used for synchronous mode. */ - USART_EnableContinuousSCLK(base, config->enableContinuousSCLK); - - return kStatus_Success; -} - -/*! - * brief Deinitializes a USART instance. - * - * This function waits for TX complete, disables TX and RX, and disables the USART clock. - * - * param base USART peripheral base address. - */ -void USART_Deinit(USART_Type *base) -{ - /* Check arguments */ - assert(NULL != base); - while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) - { - } - /* Disable interrupts, disable dma requests, disable peripheral */ - base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK | - USART_FIFOINTENCLR_RXLVL_MASK; - base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK); - base->CFG &= ~(USART_CFG_ENABLE_MASK); -} - -/*! - * brief Gets the default configuration structure. - * - * This function initializes the USART configuration structure to a default value. The default - * values are: - * usartConfig->baudRate_Bps = 115200U; - * usartConfig->parityMode = kUSART_ParityDisabled; - * usartConfig->stopBitCount = kUSART_OneStopBit; - * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; - * usartConfig->loopback = false; - * usartConfig->enableTx = false; - * usartConfig->enableRx = false; - * - * param config Pointer to configuration structure. - */ -void USART_GetDefaultConfig(usart_config_t *config) -{ - /* Check arguments */ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* Set always all members ! */ - config->baudRate_Bps = 115200U; - config->parityMode = kUSART_ParityDisabled; - config->stopBitCount = kUSART_OneStopBit; - config->bitCountPerChar = kUSART_8BitsPerChar; - config->loopback = false; - config->enableRx = false; - config->enableTx = false; - config->enableMode32k = false; - config->txWatermark = kUSART_TxFifo0; - config->rxWatermark = kUSART_RxFifo1; - config->syncMode = kUSART_SyncModeDisabled; - config->enableContinuousSCLK = false; - config->clockPolarity = kUSART_RxSampleOnFallingEdge; - config->enableHardwareFlowControl = false; -} - -/*! - * brief Sets the USART instance baud rate. - * - * This function configures the USART module baud rate. This function is used to update - * the USART module baud rate after the USART module is initialized by the USART_Init. - * code - * USART_SetBaudRate(USART1, 115200U, 20000000U); - * endcode - * - * param base USART peripheral base address. - * param baudrate_Bps USART baudrate to be set. - * param srcClock_Hz USART clock source frequency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_Success Set baudrate succeed. - * retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) -{ - uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1; - uint32_t osrval, brgval, diff, baudrate; - - /* check arguments */ - assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))); - if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* If synchronous master mode is enabled, only configure the BRG value. */ - if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U) - { - if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U) - { - brgval = srcClock_Hz / baudrate_Bps; - base->BRG = brgval - 1U; - } - } - else - { - /* - * Smaller values of OSR can make the sampling position within a data bit less accurate and may - * potentially cause more noise errors or incorrect data. - */ - for (osrval = best_osrval; osrval >= 8U; osrval--) - { - brgval = (((srcClock_Hz * 10U) / ((osrval + 1U) * baudrate_Bps)) - 5U) / 10U; - if (brgval > 0xFFFFU) - { - continue; - } - baudrate = srcClock_Hz / ((osrval + 1U) * (brgval + 1U)); - diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); - if (diff < best_diff) - { - best_diff = diff; - best_osrval = osrval; - best_brgval = brgval; - } - } - - /* Check to see if actual baud rate is within 3% of desired baud rate - * based on the best calculated OSR and BRG value */ - baudrate = srcClock_Hz / ((best_osrval + 1U) * (best_brgval + 1U)); - diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); - if (diff > ((baudrate_Bps / 100U) * 3U)) - { - return kStatus_USART_BaudrateNotSupport; - } - - /* value over range */ - if (best_brgval > 0xFFFFU) - { - return kStatus_USART_BaudrateNotSupport; - } - - base->OSR = best_osrval; - base->BRG = best_brgval; - } - - return kStatus_Success; -} - -/*! - * brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source. - * - * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator - * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting - * SYSCON_RTCOSCCTRL_EN bit to 1. - * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that - * 9600 can evenly divide, eg: 4800, 3200. - * - * param base USART peripheral base address. - * param baudRate_Bps USART baudrate to be set.. - * param enableMode32k true is 32k mode, false is normal mode. - * param srcClock_Hz USART clock source frequency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_Success Set baudrate succeed. - * retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz) -{ - status_t result = kStatus_Success; - base->CFG &= ~(USART_CFG_ENABLE_MASK); - if (enableMode32k) - { - base->CFG |= USART_CFG_MODE32K_MASK; - if ((9600U % baudRate_Bps) == 0U) - { - base->BRG = 9600U / baudRate_Bps - 1U; - } - else - { - return kStatus_USART_BaudrateNotSupport; - } - } - else - { - base->CFG &= ~(USART_CFG_MODE32K_MASK); - result = USART_SetBaudRate(base, baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - } - base->CFG |= USART_CFG_ENABLE_MASK; - return result; -} - -/*! - * brief Enable 9-bit data mode for USART. - * - * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user. - * - * param base USART peripheral base address. - * param enable true to enable, false to disable. - */ -void USART_Enable9bitMode(USART_Type *base, bool enable) -{ - assert(base != NULL); - - uint32_t temp = 0U; - - if (enable) - { - /* Set USART 9-bit mode, disable parity. */ - temp = base->CFG & ~((uint32_t)USART_CFG_DATALEN_MASK | (uint32_t)USART_CFG_PARITYSEL_MASK); - temp |= (uint32_t)USART_CFG_DATALEN(0x2U); - base->CFG = temp; - } - else - { - /* Set USART to 8-bit mode. */ - base->CFG &= ~((uint32_t)USART_CFG_DATALEN_MASK); - base->CFG |= (uint32_t)USART_CFG_DATALEN(0x1U); - } -} - -/*! - * brief Transmit an address frame in 9-bit data mode. - * - * param base USART peripheral base address. - * param address USART slave address. - */ -void USART_SendAddress(USART_Type *base, uint8_t address) -{ - assert(base != NULL); - base->FIFOWR = ((uint32_t)address | 0x100UL); -} - -/*! - * brief Writes to the TX register using a blocking method. - * - * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO - * to have room and writes data to the TX buffer. - * - * param base USART peripheral base address. - * param data Start address of the data to write. - * param length Size of the data to write. - * retval kStatus_USART_Timeout Transmission timed out and was aborted. - * retval kStatus_InvalidArgument Invalid argument. - * retval kStatus_Success Successfully wrote all data. - */ -status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) -{ - /* Check arguments */ - assert(!((NULL == base) || (NULL == data))); -#if UART_RETRY_TIMES - uint32_t waitTimes; -#endif - if ((NULL == base) || (NULL == data)) - { - return kStatus_InvalidArgument; - } - /* Check whether txFIFO is enabled */ - if (0U == (base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK)) - { - return kStatus_InvalidArgument; - } - for (; length > 0U; length--) - { - /* Loop until txFIFO get some space for new data */ -#if UART_RETRY_TIMES - waitTimes = UART_RETRY_TIMES; - while ((0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) && (--waitTimes != 0U)) -#else - while (0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) -#endif - { - } -#if UART_RETRY_TIMES - if (0U == waitTimes) - { - return kStatus_USART_Timeout; - } -#endif - base->FIFOWR = *data; - data++; - } - /* Wait to finish transfer */ -#if UART_RETRY_TIMES - waitTimes = UART_RETRY_TIMES; - while ((0U == (base->STAT & USART_STAT_TXIDLE_MASK)) && (--waitTimes != 0U)) -#else - while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) -#endif - { - } -#if UART_RETRY_TIMES - if (0U == waitTimes) - { - return kStatus_USART_Timeout; - } -#endif - return kStatus_Success; -} - -/*! - * brief Read RX data register using a blocking method. - * - * This function polls the RX register, waits for the RX register to be full or for RX FIFO to - * have data and read data from the TX register. - * - * param base USART peripheral base address. - * param data Start address of the buffer to store the received data. - * param length Size of the buffer. - * retval kStatus_USART_FramingError Receiver overrun happened while receiving data. - * retval kStatus_USART_ParityError Noise error happened while receiving data. - * retval kStatus_USART_NoiseError Framing error happened while receiving data. - * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. - * retval kStatus_USART_Timeout Transmission timed out and was aborted. - * retval kStatus_Success Successfully received all data. - */ -status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) -{ - uint32_t statusFlag; - status_t status = kStatus_Success; -#if UART_RETRY_TIMES - uint32_t waitTimes; -#endif - - /* check arguments */ - assert(!((NULL == base) || (NULL == data))); - if ((NULL == base) || (NULL == data)) - { - return kStatus_InvalidArgument; - } - - /* Check whether rxFIFO is enabled */ - if ((base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK) == 0U) - { - return kStatus_Fail; - } - for (; length > 0U; length--) - { - /* loop until rxFIFO have some data to read */ -#if UART_RETRY_TIMES - waitTimes = UART_RETRY_TIMES; - while (((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) && (--waitTimes != 0U)) -#else - while ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) -#endif - { - } -#if UART_RETRY_TIMES - if (waitTimes == 0U) - { - status = kStatus_USART_Timeout; - break; - } -#endif - /* check rxFIFO statusFlag */ - if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) - { - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; - status = kStatus_USART_RxError; - break; - } - /* check receive statusFlag */ - statusFlag = base->STAT; - /* Clear all status flags */ - base->STAT |= statusFlag; - if ((statusFlag & USART_STAT_PARITYERRINT_MASK) != 0U) - { - status = kStatus_USART_ParityError; - } - if ((statusFlag & USART_STAT_FRAMERRINT_MASK) != 0U) - { - status = kStatus_USART_FramingError; - } - if ((statusFlag & USART_STAT_RXNOISEINT_MASK) != 0U) - { - status = kStatus_USART_NoiseError; - } - - if (kStatus_Success == status) - { - *data = (uint8_t)base->FIFORD; - data++; - } - else - { - break; - } - } - return status; -} - -/*! - * brief Initializes the USART handle. - * - * This function initializes the USART handle which can be used for other USART - * transactional APIs. Usually, for a specified USART instance, - * call this API once to get the initialized handle. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param callback The callback function. - * param userData The parameter of the callback function. - */ -status_t USART_TransferCreateHandle(USART_Type *base, - usart_handle_t *handle, - usart_transfer_callback_t callback, - void *userData) -{ - /* Check 'base' */ - assert(!((NULL == base) || (NULL == handle))); - - uint32_t instance = 0; - usart_to_flexcomm_t handler; - handler.usart_master_handler = USART_TransferHandleIRQ; - - if ((NULL == base) || (NULL == handle)) - { - return kStatus_InvalidArgument; - } - - instance = USART_GetInstance(base); - - (void)memset(handle, 0, sizeof(*handle)); - /* Set the TX/RX state. */ - handle->rxState = (uint8_t)kUSART_RxIdle; - handle->txState = (uint8_t)kUSART_TxIdle; - /* Set the callback and user data. */ - handle->callback = callback; - handle->userData = userData; - handle->rxWatermark = (uint8_t)USART_FIFOTRIG_RXLVL_GET(base); - handle->txWatermark = (uint8_t)USART_FIFOTRIG_TXLVL_GET(base); - - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - - /* Enable interrupt in NVIC. */ - (void)EnableIRQ(s_usartIRQ[instance]); - - return kStatus_Success; -} - -/*! - * brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in the IRQ handler, the USART driver calls the callback - * function and passes the ref kStatus_USART_TxIdle as status parameter. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART transfer structure. See #usart_transfer_t. - * retval kStatus_Success Successfully start the data transmission. - * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer) -{ - /* Check arguments */ - assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - /* Check xfer members */ - assert(!((0U == xfer->dataSize) || (NULL == xfer->txData))); - if ((0U == xfer->dataSize) || (NULL == xfer->txData)) - { - return kStatus_InvalidArgument; - } - - /* Return error if current TX busy. */ - if ((uint8_t)kUSART_TxBusy == handle->txState) - { - return kStatus_USART_TxBusy; - } - else - { - /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up the - * handle value. */ - uint32_t interruptMask = USART_GetEnabledInterrupts(base); - USART_DisableInterrupts(base, interruptMask); - handle->txData = xfer->txData; - handle->txDataSize = xfer->dataSize; - handle->txDataSizeAll = xfer->dataSize; - handle->txState = (uint8_t)kUSART_TxBusy; - /* Enable transmiter interrupt and the previously disabled interrupt. */ - USART_EnableInterrupts(base, interruptMask | (uint32_t)kUSART_TxLevelInterruptEnable); - } - return kStatus_Success; -} - -/*! - * brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out - * how many bytes are still not sent out. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) -{ - assert(NULL != handle); - - /* Disable interrupts */ - USART_DisableInterrupts(base, (uint32_t)kUSART_TxLevelInterruptEnable); - /* Empty txFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK; - - handle->txDataSize = 0U; - handle->txState = (uint8_t)kUSART_TxIdle; -} - -/*! - * brief Get the number of bytes that have been sent out to bus. - * - * This function gets the number of bytes that have been sent out to bus by interrupt method. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Send bytes count. - * retval kStatus_NoTransferInProgress No send in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != count); - - if ((uint8_t)kUSART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - handle->txDataSize - - ((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); - - return kStatus_Success; -} - -/*! - * brief Receives a buffer of data using an interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function, which - * returns without waiting for all data to be received. - * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and - * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in the ring buffer is not enough to read, the receive - * request is saved by the USART driver. When the new data arrives, the receive request - * is serviced first. When all data is received, the USART driver notifies the upper layer - * through a callback function and passes the status parameter ref kStatus_USART_RxIdle. - * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. - * The 5 bytes are copied to the xfer->data and this function returns with the - * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is - * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to the xfer->data. When all data is received, the upper layer is notified. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART transfer structure, see #usart_transfer_t. - * param receivedBytes Bytes received from the ring buffer directly. - * retval kStatus_Success Successfully queue the transfer into transmit queue. - * retval kStatus_USART_RxBusy Previous receive request is not finished. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveNonBlocking(USART_Type *base, - usart_handle_t *handle, - usart_transfer_t *xfer, - size_t *receivedBytes) -{ - uint32_t i; - /* How many bytes to copy from ring buffer to user memory. */ - size_t bytesToCopy = 0U; - /* How many bytes to receive. */ - size_t bytesToReceive; - /* How many bytes currently have received. */ - size_t bytesCurrentReceived; - uint32_t interruptMask = 0U; - - /* Check arguments */ - assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - /* Check xfer members */ - assert(!((0U == xfer->dataSize) || (NULL == xfer->rxData))); - if ((0U == xfer->dataSize) || (NULL == xfer->rxData)) - { - return kStatus_InvalidArgument; - } - - /* Enable address detect when address match is enabled. */ - if ((base->CFG & (uint32_t)USART_CFG_AUTOADDR_MASK) != 0U) - { - base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK; - } - - /* How to get data: - 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize - to uart handle, enable interrupt to store received data to xfer->data. When - all data received, trigger callback. - 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. - If there are enough data in ring buffer, copy them to xfer->data and return. - If there are not enough data in ring buffer, copy all of them to xfer->data, - save the xfer->data remained empty space to uart handle, receive data - to this empty space and trigger callback when finished. */ - if ((uint8_t)kUSART_RxBusy == handle->rxState) - { - return kStatus_USART_RxBusy; - } - else - { - bytesToReceive = xfer->dataSize; - bytesCurrentReceived = 0U; - /* If RX ring buffer is used. */ - if (handle->rxRingBuffer != NULL) - { - /* Disable IRQ, protect ring buffer. */ - interruptMask = USART_GetEnabledInterrupts(base); - USART_DisableInterrupts(base, interruptMask); - - /* How many bytes in RX ring buffer currently. */ - bytesToCopy = USART_TransferGetRxRingBufferLength(handle); - if (bytesToCopy != 0U) - { - bytesToCopy = MIN(bytesToReceive, bytesToCopy); - bytesToReceive -= bytesToCopy; - /* Copy data from ring buffer to user memory. */ - for (i = 0U; i < bytesToCopy; i++) - { - xfer->rxData[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; - /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ - if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - } - /* If ring buffer does not have enough data, still need to read more data. */ - if (bytesToReceive != 0U) - { - /* No data in ring buffer, save the request to UART handle. */ - handle->rxData = xfer->rxData + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = xfer->dataSize; - handle->rxState = (uint8_t)kUSART_RxBusy; - } - /* Re-enable IRQ. */ - USART_EnableInterrupts(base, interruptMask); - /* Call user callback since all data are received. */ - if (0U == bytesToReceive) - { - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); - } - } - } - /* Ring buffer not used. */ - else - { - /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up - * the handle value. */ - interruptMask = USART_GetEnabledInterrupts(base); - USART_DisableInterrupts(base, interruptMask); - handle->rxData = xfer->rxData + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = (uint8_t)kUSART_RxBusy; - - /* Enable RX interrupt. */ - base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK; - /* Re-enable IRQ. */ - USART_EnableInterrupts(base, interruptMask); - } - /* Return the how many bytes have read. */ - if (receivedBytes != NULL) - { - *receivedBytes = bytesCurrentReceived; - } - } - return kStatus_Success; -} - -/*! - * brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out - * how many bytes not received yet. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) -{ - assert(NULL != handle); - - /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ - if (NULL == handle->rxRingBuffer) - { - /* Disable interrupts */ - USART_DisableInterrupts(base, (uint32_t)kUSART_RxLevelInterruptEnable); - /* Empty rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - } - - handle->rxDataSize = 0U; - handle->rxState = (uint8_t)kUSART_RxIdle; -} - -/*! - * brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Receive bytes count. - * retval kStatus_NoTransferInProgress No receive in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != count); - - if ((uint8_t)kUSART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - handle->rxDataSize; - - return kStatus_Success; -} - -/*! - * brief USART IRQ handle function. - * - * This function handles the USART transmit and receive IRQ request. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) -{ - /* Check arguments */ - assert((NULL != base) && (NULL != handle)); - - bool receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); - bool sendEnabled = (handle->txDataSize != 0U); - uint8_t rxdata; - size_t tmpsize; - - /* If RX overrun. */ - if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) - { - /* Clear rx error state. */ - base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxError, handle->userData); - } - } - /* TX under run, happens when slave is in synchronous mode and the data is not written in tx register in time. */ - if ((base->FIFOSTAT & USART_FIFOSTAT_TXERR_MASK) != 0U) - { - /* Clear tx error state. */ - base->FIFOSTAT |= USART_FIFOSTAT_TXERR_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_TxError, handle->userData); - } - } - /* If noise error. */ - if ((base->STAT & USART_STAT_RXNOISEINT_MASK) != 0U) - { - /* Clear rx error state. */ - base->STAT |= USART_STAT_RXNOISEINT_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_NoiseError, handle->userData); - } - } - /* If framing error. */ - if ((base->STAT & USART_STAT_FRAMERRINT_MASK) != 0U) - { - /* Clear rx error state. */ - base->STAT |= USART_STAT_FRAMERRINT_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_FramingError, handle->userData); - } - } - /* If parity error. */ - if ((base->STAT & USART_STAT_PARITYERRINT_MASK) != 0U) - { - /* Clear rx error state. */ - base->STAT |= USART_STAT_PARITYERRINT_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_ParityError, handle->userData); - } - } - while ((receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) || - (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U))) - { - /* Receive data */ - if (receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) - { - /* Clear address detect when RXFIFO has data. */ - base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK; - /* Receive to app bufffer if app buffer is present */ - if (handle->rxDataSize != 0U) - { - rxdata = (uint8_t)base->FIFORD; - *handle->rxData = rxdata; - handle->rxDataSize--; - handle->rxData++; - receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); - if (0U == handle->rxDataSize) - { - if (NULL == handle->rxRingBuffer) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; - } - handle->rxState = (uint8_t)kUSART_RxIdle; - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); - } - } - } - /* Otherwise receive to ring buffer if ring buffer is present */ - else - { - if (handle->rxRingBuffer != NULL) - { - /* If RX ring buffer is full, trigger callback to notify over run. */ - if (USART_TransferIsRxRingBufferFull(handle)) - { - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData); - } - } - /* If ring buffer is still full after callback function, the oldest data is overridden. */ - if (USART_TransferIsRxRingBufferFull(handle)) - { - /* Increase handle->rxRingBufferTail to make room for new data. */ - if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - /* Read data. */ - rxdata = (uint8_t)base->FIFORD; - handle->rxRingBuffer[handle->rxRingBufferHead] = rxdata; - /* Increase handle->rxRingBufferHead. */ - if ((size_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferHead = 0U; - } - else - { - handle->rxRingBufferHead++; - } - } - } - } - /* Send data */ - if (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U)) - { - base->FIFOWR = *handle->txData; - handle->txDataSize--; - handle->txData++; - sendEnabled = handle->txDataSize != 0U; - if (!sendEnabled) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK; - - base->INTENSET = USART_INTENSET_TXIDLEEN_MASK; - } - } - } - - /* Tx idle and the interrupt is enabled. */ - if ((0U != (base->INTENSET & USART_INTENSET_TXIDLEEN_MASK)) && (0U != (base->INTSTAT & USART_INTSTAT_TXIDLE_MASK))) - { - /* Set txState to idle only when all data has been sent out to bus. */ - handle->txState = (uint8_t)kUSART_TxIdle; - /* Disable tx idle interrupt */ - base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK; - - /* Trigger callback. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); - } - } - - /* ring buffer is not used */ - if (NULL == handle->rxRingBuffer) - { - tmpsize = handle->rxDataSize; - - /* restore if rx transfer ends and rxLevel is different from default value */ - if ((tmpsize == 0U) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark)) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark); - } - /* decrease level if rx transfer is bellow */ - if ((tmpsize != 0U) && (tmpsize < (USART_FIFOTRIG_RXLVL_GET(base) + 1U))) - { - base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(tmpsize - 1U)); - } - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart.h deleted file mode 100644 index ef4715c4c5c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart.h +++ /dev/null @@ -1,903 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_USART_H_ -#define _FSL_USART_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup usart_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief USART driver version. */ -#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 7, 0)) -/*@}*/ - -#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT) -#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT) - -/*! @brief Retry times for waiting flag. */ -#ifndef UART_RETRY_TIMES -#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */ -#endif - -/*! @brief Error codes for the USART driver. */ -enum -{ - kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */ - kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */ - kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */ - kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */ - kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */ - kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */ - kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */ - kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */ - kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */ - kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */ - kStatus_USART_BaudrateNotSupport = - MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */ -#if UART_RETRY_TIMES - kStatus_USART_Timeout = MAKE_STATUS(kStatusGroup_LPC_USART, 14), /*!< USART time out. */ -#endif -}; - -/*! @brief USART synchronous mode. */ -typedef enum _usart_sync_mode -{ - kUSART_SyncModeDisabled = 0x0U, /*!< Asynchronous mode. */ - kUSART_SyncModeSlave = 0x2U, /*!< Synchronous slave mode. */ - kUSART_SyncModeMaster = 0x3U, /*!< Synchronous master mode. */ -} usart_sync_mode_t; - -/*! @brief USART parity mode. */ -typedef enum _usart_parity_mode -{ - kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */ - kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ - kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ -} usart_parity_mode_t; - -/*! @brief USART stop bit count. */ -typedef enum _usart_stop_bit_count -{ - kUSART_OneStopBit = 0U, /*!< One stop bit */ - kUSART_TwoStopBit = 1U, /*!< Two stop bits */ -} usart_stop_bit_count_t; - -/*! @brief USART data size. */ -typedef enum _usart_data_len -{ - kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */ - kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */ -} usart_data_len_t; - -/*! @brief USART clock polarity configuration, used in sync mode.*/ -typedef enum _usart_clock_polarity -{ - kUSART_RxSampleOnFallingEdge = 0x0U, /*!< Un_RXD is sampled on the falling edge of SCLK. */ - kUSART_RxSampleOnRisingEdge = 0x1U, /*!< Un_RXD is sampled on the rising edge of SCLK. */ -} usart_clock_polarity_t; - -/*! @brief txFIFO watermark values */ -typedef enum _usart_txfifo_watermark -{ - kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */ - kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */ - kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */ - kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */ - kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */ - kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */ - kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */ - kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */ -} usart_txfifo_watermark_t; - -/*! @brief rxFIFO watermark values */ -typedef enum _usart_rxfifo_watermark -{ - kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */ - kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */ - kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */ - kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */ - kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */ - kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */ - kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */ - kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */ -} usart_rxfifo_watermark_t; - -/*! - * @brief USART interrupt configuration structure, default settings all disabled. - */ -enum _usart_interrupt_enable -{ - kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK), - kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK), - kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK), - kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK), - kUSART_TxIdleInterruptEnable = (USART_INTENSET_TXIDLEEN_MASK << 16U), /*!< Transmitter idle. */ - kUSART_CtsChangeInterruptEnable = - (USART_INTENSET_DELTACTSEN_MASK << 16U), /*!< Change in the state of the CTS input. */ - kUSART_RxBreakChangeInterruptEnable = - (USART_INTENSET_DELTARXBRKEN_MASK), /*!< Break condition asserted or deasserted. */ - kUSART_RxStartInterruptEnable = (USART_INTENSET_STARTEN_MASK), /*!< Rx start bit detected. */ - kUSART_FramingErrorInterruptEnable = (USART_INTENSET_FRAMERREN_MASK), /*!< Framing error detected. */ - kUSART_ParityErrorInterruptEnable = (USART_INTENSET_PARITYERREN_MASK), /*!< Parity error detected. */ - kUSART_NoiseErrorInterruptEnable = (USART_INTENSET_RXNOISEEN_MASK), /*!< Noise error detected. */ - kUSART_AutoBaudErrorInterruptEnable = (USART_INTENSET_ABERREN_MASK), /*!< Auto baudrate error detected. */ - - kUSART_AllInterruptEnables = - kUSART_TxErrorInterruptEnable | kUSART_RxErrorInterruptEnable | kUSART_TxLevelInterruptEnable | - kUSART_RxLevelInterruptEnable | kUSART_TxIdleInterruptEnable | kUSART_CtsChangeInterruptEnable | - kUSART_RxBreakChangeInterruptEnable | kUSART_RxStartInterruptEnable | kUSART_FramingErrorInterruptEnable | - kUSART_ParityErrorInterruptEnable | kUSART_NoiseErrorInterruptEnable | kUSART_AutoBaudErrorInterruptEnable, -}; - -/*! - * @brief USART status flags. - * - * This provides constants for the USART status flags for use in the USART functions. - */ -enum _usart_flags -{ - kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */ - kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */ - kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */ - kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */ - kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */ - kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */ - kUSART_RxIdleFlag = (USART_STAT_RXIDLE_MASK << 16U), /*!< Receiver idle. */ - kUSART_TxIdleFlag = (USART_STAT_TXIDLE_MASK << 16U), /*!< Transmitter idle. */ - kUSART_CtsAssertFlag = (USART_STAT_CTS_MASK << 16U), /*!< CTS signal high. */ - kUSART_CtsChangeFlag = (USART_STAT_DELTACTS_MASK << 16U), /*!< CTS signal changed interrupt status. */ - kUSART_BreakDetectFlag = (USART_STAT_RXBRK_MASK), /*!< Break detected. Self cleared when rx pin goes high again. */ - kUSART_BreakDetectChangeFlag = (USART_STAT_DELTARXBRK_MASK), /*!< Break detect change interrupt flag. A change in - the state of receiver break detection. */ - kUSART_RxStartFlag = (USART_STAT_START_MASK), /*!< Rx start bit detected interrupt flag. */ - kUSART_FramingErrorFlag = (USART_STAT_FRAMERRINT_MASK), /*!< Framing error interrupt flag. */ - kUSART_ParityErrorFlag = (USART_STAT_PARITYERRINT_MASK), /*!< parity error interrupt flag. */ - kUSART_NoiseErrorFlag = (USART_STAT_RXNOISEINT_MASK), /*!< Noise error interrupt flag. */ - kUSART_AutobaudErrorFlag = (USART_STAT_ABERR_MASK), /*!< Auto baudrate error interrupt flag, caused by the baudrate - counter timeout before the end of start bit. */ - - kUSART_AllClearFlags = kUSART_TxError | kUSART_RxError | kUSART_CtsChangeFlag | kUSART_BreakDetectChangeFlag | - kUSART_RxStartFlag | kUSART_FramingErrorFlag | kUSART_ParityErrorFlag | - kUSART_NoiseErrorFlag | kUSART_AutobaudErrorFlag, -}; - -/*! @brief USART configuration structure. */ -typedef struct _usart_config -{ - uint32_t baudRate_Bps; /*!< USART baud rate */ - usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ - usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ - usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */ - bool loopback; /*!< Enable peripheral loopback */ - bool enableRx; /*!< Enable RX */ - bool enableTx; /*!< Enable TX */ - bool enableContinuousSCLK; /*!< USART continuous Clock generation enable in synchronous master mode. */ - bool enableMode32k; /*!< USART uses 32 kHz clock from the RTC oscillator as the clock source. */ - bool enableHardwareFlowControl; /*!< Enable hardware control RTS/CTS */ - usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ - usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */ - usart_clock_polarity_t clockPolarity; /*!< Selects the clock polarity and sampling edge in synchronous mode. */ -} usart_config_t; - -/*! @brief USART transfer structure. */ -typedef struct _usart_transfer -{ - /* - * Use separate TX and RX data pointer, because TX data is const data. - * The member data is kept for backward compatibility. - */ - union - { - uint8_t *data; /*!< The buffer of data to be transfer.*/ - uint8_t *rxData; /*!< The buffer to receive data. */ - const uint8_t *txData; /*!< The buffer of data to be sent. */ - }; - size_t dataSize; /*!< The byte count to be transfer. */ -} usart_transfer_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _usart_handle usart_handle_t; - -/*! @brief USART transfer callback function. */ -typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData); - -/*! @brief USART handle structure. */ -struct _usart_handle -{ - const uint8_t *volatile txData; /*!< Address of remaining data to send. */ - volatile size_t txDataSize; /*!< Size of the remaining data to send. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ - volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - - uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ - size_t rxRingBufferSize; /*!< Size of the ring buffer. */ - volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ - volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ - - usart_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< USART callback function parameter.*/ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ - - uint8_t txWatermark; /*!< txFIFO watermark */ - uint8_t rxWatermark; /*!< rxFIFO watermark */ -}; - -/*! @brief Typedef for usart interrupt handler. */ -typedef void (*flexcomm_usart_irq_handler_t)(USART_Type *base, usart_handle_t *handle); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! @brief Returns instance number for USART peripheral base address. */ -uint32_t USART_GetInstance(USART_Type *base); - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes a USART instance with user configuration structure and peripheral clock. - * - * This function configures the USART module with the user-defined settings. The user can configure the configuration - * structure and also get the default configuration by using the USART_GetDefaultConfig() function. - * Example below shows how to use this API to configure USART. - * @code - * usart_config_t usartConfig; - * usartConfig.baudRate_Bps = 115200U; - * usartConfig.parityMode = kUSART_ParityDisabled; - * usartConfig.stopBitCount = kUSART_OneStopBit; - * USART_Init(USART1, &usartConfig, 20000000U); - * @endcode - * - * @param base USART peripheral base address. - * @param config Pointer to user-defined configuration structure. - * @param srcClock_Hz USART clock source frequency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_InvalidArgument USART base address is not valid - * @retval kStatus_Success Status USART initialize succeed - */ -status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes a USART instance. - * - * This function waits for TX complete, disables TX and RX, and disables the USART clock. - * - * @param base USART peripheral base address. - */ -void USART_Deinit(USART_Type *base); - -/*! - * @brief Gets the default configuration structure. - * - * This function initializes the USART configuration structure to a default value. The default - * values are: - * usartConfig->baudRate_Bps = 115200U; - * usartConfig->parityMode = kUSART_ParityDisabled; - * usartConfig->stopBitCount = kUSART_OneStopBit; - * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; - * usartConfig->loopback = false; - * usartConfig->enableTx = false; - * usartConfig->enableRx = false; - * - * @param config Pointer to configuration structure. - */ -void USART_GetDefaultConfig(usart_config_t *config); - -/*! - * @brief Sets the USART instance baud rate. - * - * This function configures the USART module baud rate. This function is used to update - * the USART module baud rate after the USART module is initialized by the USART_Init. - * @code - * USART_SetBaudRate(USART1, 115200U, 20000000U); - * @endcode - * - * @param base USART peripheral base address. - * @param baudrate_Bps USART baudrate to be set. - * @param srcClock_Hz USART clock source frequency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_Success Set baudrate succeed. - * @retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source - * - * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator - * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting - * SYSCON_RTCOSCCTRL_EN bit to 1. - * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that - * 9600 can evenly divide, eg: 4800, 3200. - * - * @param base USART peripheral base address. - * @param baudRate_Bps USART baudrate to be set.. - * @param enableMode32k true is 32k mode, false is normal mode. - * @param srcClock_Hz USART clock source frequency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_Success Set baudrate succeed. - * @retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz); - -/*! - * @brief Enable 9-bit data mode for USART. - * - * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user. - * - * @param base USART peripheral base address. - * @param enable true to enable, false to disable. - */ -void USART_Enable9bitMode(USART_Type *base, bool enable); - -/*! - * @brief Set the USART slave address. - * - * This function configures the address for USART module that works as slave in 9-bit data mode. When the address - * detection is enabled, the frame it receices with MSB being 1 is considered as an address frame, otherwise it is - * considered as data frame. Once the address frame matches slave's own addresses, this slave is addressed. This - * address frame and its following data frames are stored in the receive buffer, otherwise the frames will be discarded. - * To un-address a slave, just send an address frame with unmatched address. - * - * @note Any USART instance joined in the multi-slave system can work as slave. The position of the address mark is the - * same as the parity bit when parity is enabled for 8 bit and 9 bit data formats. - * - * @param base USART peripheral base address. - * @param address USART slave address. - */ -static inline void USART_SetMatchAddress(USART_Type *base, uint8_t address) -{ - /* Configure match address. */ - base->ADDR = (uint32_t)address; -} - -/*! - * @brief Enable the USART match address feature. - * - * @param base USART peripheral base address. - * @param match true to enable match address, false to disable. - */ -static inline void USART_EnableMatchAddress(USART_Type *base, bool match) -{ - /* Configure match address enable bit. */ - if (match) - { - base->CFG |= (uint32_t)USART_CFG_AUTOADDR_MASK; - base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK; - } - else - { - base->CFG &= ~(uint32_t)USART_CFG_AUTOADDR_MASK; - base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK; - } -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Get USART status flags. - * - * This function get all USART status flags, the flags are returned as the logical - * OR value of the enumerators @ref _usart_flags. To check a specific status, - * compare the return value with enumerators in @ref _usart_flags. - * For example, to check whether the TX is empty: - * @code - * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1)) - * { - * ... - * } - * @endcode - * - * @param base USART peripheral base address. - * @return USART status flags which are ORed by the enumerators in the _usart_flags. - */ -static inline uint32_t USART_GetStatusFlags(USART_Type *base) -{ - return (base->FIFOSTAT & 0xFFUL) | (base->STAT & 0xFFUL) << 16U | (base->STAT & 0xFFFF00UL); -} - -/*! - * @brief Clear USART status flags. - * - * This function clear supported USART status flags - * Flags that can be cleared or set are: - * kUSART_TxError - * kUSART_RxError - * For example: - * @code - * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError) - * @endcode - * - * @param base USART peripheral base address. - * @param mask status flags to be cleared. - */ -static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask) -{ - mask &= (uint32_t)kUSART_AllClearFlags; - /* Clear the clearable status in STAT register. */ - base->STAT = (mask & 0xFFFF00UL) | ((mask & 0xFF0000UL) >> 16U); - /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */ - base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK); -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ -/*! - * @brief Enables USART interrupts according to the provided mask. - * - * This function enables the USART interrupts according to the provided mask. The mask - * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. - * For example, to enable TX empty interrupt and RX full interrupt: - * @code - * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); - * @endcode - * - * @param base USART peripheral base address. - * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable. - */ -static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) -{ - mask &= (uint32_t)kUSART_AllInterruptEnables; - base->INTENSET = (mask & 0x1FF00UL) | ((mask & 0xFF0000UL) >> 16U); - base->FIFOINTENSET = mask & 0xFUL; -} - -/*! - * @brief Disables USART interrupts according to a provided mask. - * - * This function disables the USART interrupts according to a provided mask. The mask - * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. - * This example shows how to disable the TX empty interrupt and RX full interrupt: - * @code - * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); - * @endcode - * - * @param base USART peripheral base address. - * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable. - */ -static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) -{ - mask &= (uint32_t)kUSART_AllInterruptEnables; - base->INTENCLR = (mask & 0x1FF00UL) | ((mask & 0xFF0000UL) >> 16U); - base->FIFOINTENCLR = mask & 0xFUL; -} - -/*! - * @brief Returns enabled USART interrupts. - * - * This function returns the enabled USART interrupts. - * - * @param base USART peripheral base address. - */ -static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base) -{ - return (base->INTENSET & 0x1FF00UL) | ((base->INTENSET & 0xFFUL) << 16UL) | (base->FIFOINTENSET & 0xFUL); -} - -/*! - * @brief Enable DMA for Tx - */ -static inline void USART_EnableTxDMA(USART_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK); - } -} - -/*! - * @brief Enable DMA for Rx - */ -static inline void USART_EnableRxDMA(USART_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK); - } -} - -/*! - * @brief Enable CTS. - * This function will determine whether CTS is used for flow control. - * - * @param base USART peripheral base address. - * @param enable Enable CTS or not, true for enable and false for disable. - */ -static inline void USART_EnableCTS(USART_Type *base, bool enable) -{ - if (enable) - { - base->CFG |= USART_CFG_CTSEN_MASK; - } - else - { - base->CFG &= ~USART_CFG_CTSEN_MASK; - } -} - -/*! - * @brief Continuous Clock generation. - * By default, SCLK is only output while data is being transmitted in synchronous mode. - * Enable this funciton, SCLK will run continuously in synchronous mode, allowing - * characters to be received on Un_RxD independently from transmission on Un_TXD). - * - * @param base USART peripheral base address. - * @param enable Enable Continuous Clock generation mode or not, true for enable and false for disable. - */ -static inline void USART_EnableContinuousSCLK(USART_Type *base, bool enable) -{ - if (enable) - { - base->CTL |= USART_CTL_CC_MASK; - } - else - { - base->CTL &= ~USART_CTL_CC_MASK; - } -} - -/*! - * @brief Enable Continuous Clock generation bit auto clear. - * While enable this cuntion, the Continuous Clock bit is automatically cleared when a complete - * character has been received. This bit is cleared at the same time. - * - * @param base USART peripheral base address. - * @param enable Enable auto clear or not, true for enable and false for disable. - */ -static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable) -{ - if (enable) - { - base->CTL |= USART_CTL_CLRCCONRX_MASK; - } - else - { - base->CTL &= ~USART_CTL_CLRCCONRX_MASK; - } -} - -/*! - * @brief Sets the rx FIFO watermark. - * - * @param base USART peripheral base address. - * @param water Rx FIFO watermark. - */ -static inline void USART_SetRxFifoWatermark(USART_Type *base, uint8_t water) -{ - assert(water <= (USART_FIFOTRIG_RXLVL_MASK >> USART_FIFOTRIG_RXLVL_SHIFT)); - base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_RXLVL_MASK) | USART_FIFOTRIG_RXLVL(water); -} - -/*! - * @brief Sets the tx FIFO watermark. - * - * @param base USART peripheral base address. - * @param water Tx FIFO watermark. - */ -static inline void USART_SetTxFifoWatermark(USART_Type *base, uint8_t water) -{ - assert(water <= (USART_FIFOTRIG_TXLVL_MASK >> USART_FIFOTRIG_TXLVL_SHIFT)); - base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_TXLVL_MASK) | USART_FIFOTRIG_TXLVL(water); -} -/* @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Writes to the FIFOWR register. - * - * This function writes data to the txFIFO directly. The upper layer must ensure - * that txFIFO has space for data to write before calling this function. - * - * @param base USART peripheral base address. - * @param data The byte to write. - */ -static inline void USART_WriteByte(USART_Type *base, uint8_t data) -{ - base->FIFOWR = data; -} - -/*! - * @brief Reads the FIFORD register directly. - * - * This function reads data from the rxFIFO directly. The upper layer must - * ensure that the rxFIFO is not empty before calling this function. - * - * @param base USART peripheral base address. - * @return The byte read from USART data register. - */ -static inline uint8_t USART_ReadByte(USART_Type *base) -{ - return (uint8_t)base->FIFORD; -} - -/*! - * @brief Gets the rx FIFO data count. - * - * @param base USART peripheral base address. - * @return rx FIFO data count. - */ -static inline uint8_t USART_GetRxFifoCount(USART_Type *base) -{ - return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_RXLVL_MASK) >> USART_FIFOSTAT_RXLVL_SHIFT); -} - -/*! - * @brief Gets the tx FIFO data count. - * - * @param base USART peripheral base address. - * @return tx FIFO data count. - */ -static inline uint8_t USART_GetTxFifoCount(USART_Type *base) -{ - return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); -} - -/*! - * @brief Transmit an address frame in 9-bit data mode. - * - * @param base USART peripheral base address. - * @param address USART slave address. - */ -void USART_SendAddress(USART_Type *base, uint8_t address); - -/*! - * @brief Writes to the TX register using a blocking method. - * - * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO - * to have room and writes data to the TX buffer. - * - * @param base USART peripheral base address. - * @param data Start address of the data to write. - * @param length Size of the data to write. - * @retval kStatus_USART_Timeout Transmission timed out and was aborted. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_Success Successfully wrote all data. - */ -status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length); - -/*! - * @brief Read RX data register using a blocking method. - * - * This function polls the RX register, waits for the RX register to be full or for RX FIFO to - * have data and read data from the TX register. - * - * @param base USART peripheral base address. - * @param data Start address of the buffer to store the received data. - * @param length Size of the buffer. - * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data. - * @retval kStatus_USART_ParityError Noise error happened while receiving data. - * @retval kStatus_USART_NoiseError Framing error happened while receiving data. - * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. - * @retval kStatus_USART_Timeout Transmission timed out and was aborted. - * @retval kStatus_Success Successfully received all data. - */ -status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the USART handle. - * - * This function initializes the USART handle which can be used for other USART - * transactional APIs. Usually, for a specified USART instance, - * call this API once to get the initialized handle. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param callback The callback function. - * @param userData The parameter of the callback function. - */ -status_t USART_TransferCreateHandle(USART_Type *base, - usart_handle_t *handle, - usart_transfer_callback_t callback, - void *userData); - -/*! - * @brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in the IRQ handler, the USART driver calls the callback - * function and passes the @ref kStatus_USART_TxIdle as status parameter. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART transfer structure. See #usart_transfer_t. - * @retval kStatus_Success Successfully start the data transmission. - * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific USART handle. - * - * When the RX ring buffer is used, data received are stored into the ring buffer even when the - * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * - * @note When using the RX ring buffer, one byte is reserved for internal use. In other - * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. - * @param ringBufferSize size of the ring buffer. - */ -void USART_TransferStartRingBuffer(USART_Type *base, - usart_handle_t *handle, - uint8_t *ringBuffer, - size_t ringBufferSize); - -/*! - * @brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the length of received data in RX ring buffer. - * - * @param handle USART handle pointer. - * @return Length of received data in RX ring buffer. - */ -size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle); - -/*! - * @brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out - * how many bytes are still not sent out. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been sent out to bus. - * - * This function gets the number of bytes that have been sent out to bus by interrupt method. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Send bytes count. - * @retval kStatus_NoTransferInProgress No send in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); - -/*! - * @brief Receives a buffer of data using an interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function, which - * returns without waiting for all data to be received. - * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and - * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in the ring buffer is not enough to read, the receive - * request is saved by the USART driver. When the new data arrives, the receive request - * is serviced first. When all data is received, the USART driver notifies the upper layer - * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle. - * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. - * The 5 bytes are copied to the xfer->data and this function returns with the - * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is - * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to the xfer->data. When all data is received, the upper layer is notified. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART transfer structure, see #usart_transfer_t. - * @param receivedBytes Bytes received from the ring buffer directly. - * @retval kStatus_Success Successfully queue the transfer into transmit queue. - * @retval kStatus_USART_RxBusy Previous receive request is not finished. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveNonBlocking(USART_Type *base, - usart_handle_t *handle, - usart_transfer_t *xfer, - size_t *receivedBytes); - -/*! - * @brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out - * how many bytes not received yet. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); - -/*! - * @brief USART IRQ handle function. - * - * This function handles the USART transmit and receive IRQ request. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_USART_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.c deleted file mode 100644 index 60c2d5284c5..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.c +++ /dev/null @@ -1,392 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_usart.h" -#include "fsl_device_registers.h" -#include "fsl_dma.h" -#include "fsl_flexcomm.h" -#include "fsl_usart_dma.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_dma" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ -enum -{ - kUSART_TxIdle, /* TX idle. */ - kUSART_TxBusy, /* TX busy. */ - kUSART_RxIdle, /* RX idle. */ - kUSART_RxBusy /* RX busy. */ -}; - -/*! @brief Typedef for usart DMA interrupt handler. */ -typedef void (*flexcomm_usart_dma_irq_handler_t)(USART_Type *base, usart_dma_handle_t *handle); - -/*base, false); - - /* Enable tx idle interrupt */ - usartPrivateHandle->base->INTENSET = USART_INTENSET_TXIDLEEN_MASK; -} - -static void USART_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode) -{ - assert(handle != NULL); - assert(param != NULL); - - usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param; - - /* Disable UART RX DMA. */ - USART_EnableRxDMA(usartPrivateHandle->base, false); - - usartPrivateHandle->handle->rxState = (uint8_t)kUSART_RxIdle; - - if (usartPrivateHandle->handle->callback != NULL) - { - usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_RxIdle, - usartPrivateHandle->handle->userData); - } -} - -/*! - * brief Initializes the USART handle which is used in transactional functions. - * param base USART peripheral base address. - * param handle Pointer to usart_dma_handle_t structure. - * param callback Callback function. - * param userData User data. - * param txDmaHandle User-requested DMA handle for TX DMA transfer. - * param rxDmaHandle User-requested DMA handle for RX DMA transfer. - */ -status_t USART_TransferCreateHandleDMA(USART_Type *base, - usart_dma_handle_t *handle, - usart_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *txDmaHandle, - dma_handle_t *rxDmaHandle) -{ - uint32_t instance = 0; - - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } - /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - instance = USART_GetInstance(base); - - (void)memset(handle, 0, sizeof(*handle)); - /* assign 'base' and 'handle' */ - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - /* set tx/rx 'idle' state */ - handle->rxState = (uint8_t)kUSART_RxIdle; - handle->txState = (uint8_t)kUSART_TxIdle; - - handle->callback = callback; - handle->userData = userData; - - handle->rxDmaHandle = rxDmaHandle; - handle->txDmaHandle = txDmaHandle; - - /* Set USART_TransferDMAHandleIRQ as DMA IRQ handler */ - usart_dma_to_flexcomm_t handler; - handler.usart_dma_handler = USART_TransferDMAHandleIRQ; - FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); - /* Enable NVIC IRQ. */ - (void)EnableIRQ(s_usartIRQ[instance]); - - /* Configure TX. */ - if (txDmaHandle != NULL) - { - DMA_SetCallback(txDmaHandle, USART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]); - } - - /* Configure RX. */ - if (rxDmaHandle != NULL) - { - DMA_SetCallback(rxDmaHandle, USART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]); - } - - return kStatus_Success; -} - -/*! - * brief Sends data using DMA. - * - * This function sends data using DMA. This is a non-blocking function, which returns - * right away. When all data is sent, the send callback function is called. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART DMA transfer structure. See #usart_transfer_t. - * retval kStatus_Success if succeed, others failed. - * retval kStatus_USART_TxBusy Previous transfer on going. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) -{ - assert(handle != NULL); - assert(handle->txDmaHandle != NULL); - assert(xfer != NULL); - assert(xfer->data != NULL); - assert(xfer->dataSize != 0U); - - dma_transfer_config_t xferConfig; - status_t status; - uint32_t address = (uint32_t)&base->FIFOWR; - - /* If previous TX not finished. */ - if ((uint8_t)kUSART_TxBusy == handle->txState) - { - status = kStatus_USART_TxBusy; - } - else - { - handle->txState = (uint8_t)kUSART_TxBusy; - handle->txDataSizeAll = xfer->dataSize; - - /* Enable DMA request from txFIFO */ - USART_EnableTxDMA(base, true); - - /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, xfer->data, (uint32_t *)address, sizeof(uint8_t), xfer->dataSize, - kDMA_MemoryToPeripheral, NULL); - - /* Submit transfer. */ - (void)DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); - DMA_StartTransfer(handle->txDmaHandle); - - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Receives data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * param base USART peripheral base address. - * param handle Pointer to usart_dma_handle_t structure. - * param xfer USART DMA transfer structure. See #usart_transfer_t. - * retval kStatus_Success if succeed, others failed. - * retval kStatus_USART_RxBusy Previous transfer on going. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) -{ - assert(handle != NULL); - assert(handle->rxDmaHandle != NULL); - assert(xfer != NULL); - assert(xfer->data != NULL); - assert(xfer->dataSize != 0U); - - dma_transfer_config_t xferConfig; - status_t status; - uint32_t address = (uint32_t)&base->FIFORD; - - /* If previous RX not finished. */ - if ((uint8_t)kUSART_RxBusy == handle->rxState) - { - status = kStatus_USART_RxBusy; - } - else - { - handle->rxState = (uint8_t)kUSART_RxBusy; - handle->rxDataSizeAll = xfer->dataSize; - - /* Enable DMA request from rxFIFO */ - USART_EnableRxDMA(base, true); - - /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, xfer->data, sizeof(uint8_t), xfer->dataSize, - kDMA_PeripheralToMemory, NULL); - - /* Submit transfer. */ - (void)DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); - DMA_StartTransfer(handle->rxDmaHandle); - - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Aborts the sent data using DMA. - * - * This function aborts send data using DMA. - * - * param base USART peripheral base address - * param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle) -{ - assert(NULL != handle); - assert(NULL != handle->txDmaHandle); - - /* Stop transfer. */ - DMA_AbortTransfer(handle->txDmaHandle); - handle->txState = (uint8_t)kUSART_TxIdle; -} - -/*! - * brief Aborts the received data using DMA. - * - * This function aborts the received data using DMA. - * - * param base USART peripheral base address - * param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle) -{ - assert(NULL != handle); - assert(NULL != handle->rxDmaHandle); - - /* Stop transfer. */ - DMA_AbortTransfer(handle->rxDmaHandle); - handle->rxState = (uint8_t)kUSART_RxIdle; -} - -/*! - * brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Receive bytes count. - * retval kStatus_NoTransferInProgress No receive in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != handle->rxDmaHandle); - assert(NULL != count); - - if ((uint8_t)kUSART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); - - return kStatus_Success; -} - -/*! - * brief Get the number of bytes that have been sent. - * - * This function gets the number of bytes that have been sent. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Sent bytes count. - * retval kStatus_NoTransferInProgress No receive in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != handle->txDmaHandle); - assert(NULL != count); - - if ((uint8_t)kUSART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel); - - return kStatus_Success; -} - -void USART_TransferDMAHandleIRQ(USART_Type *base, usart_dma_handle_t *handle) -{ - /* Check arguments */ - assert((NULL != base) && (NULL != handle)); - - /* Tx idle interrupt happens means that all the tx data have been sent out to bus, set the tx state to idle */ - handle->txState = (uint8_t)kUSART_TxIdle; - - /* Disable tx idle interrupt */ - base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK; - - /* Invoke callback */ - if (handle->callback != NULL) - { - handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); - } -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.h deleted file mode 100644 index 2166803b5f2..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_USART_DMA_H_ -#define _FSL_USART_DMA_H_ - -#include "fsl_common.h" -#include "fsl_dma.h" -#include "fsl_usart.h" - -/*! - * @addtogroup usart_dma_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief USART dma driver version. */ -#define FSL_USART_DMA_DRIVER_VERSION (MAKE_VERSION(2, 6, 0)) -/*@}*/ - -/* Forward declaration of the handle typedef. */ -typedef struct _usart_dma_handle usart_dma_handle_t; - -/*! @brief UART transfer callback function. */ -typedef void (*usart_dma_transfer_callback_t)(USART_Type *base, - usart_dma_handle_t *handle, - status_t status, - void *userData); - -/*! - * @brief UART DMA handle - */ -struct _usart_dma_handle -{ - USART_Type *base; /*!< UART peripheral base address. */ - - usart_dma_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< UART callback function parameter.*/ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - - dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */ - dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name DMA transactional - * @{ - */ - -/*! - * @brief Initializes the USART handle which is used in transactional functions. - * @param base USART peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param callback Callback function. - * @param userData User data. - * @param txDmaHandle User-requested DMA handle for TX DMA transfer. - * @param rxDmaHandle User-requested DMA handle for RX DMA transfer. - */ -status_t USART_TransferCreateHandleDMA(USART_Type *base, - usart_dma_handle_t *handle, - usart_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *txDmaHandle, - dma_handle_t *rxDmaHandle); - -/*! - * @brief Sends data using DMA. - * - * This function sends data using DMA. This is a non-blocking function, which returns - * right away. When all data is sent, the send callback function is called. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART DMA transfer structure. See #usart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_USART_TxBusy Previous transfer on going. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Receives data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * @param base USART peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param xfer USART DMA transfer structure. See #usart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_USART_RxBusy Previous transfer on going. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Aborts the sent data using DMA. - * - * This function aborts send data using DMA. - * - * @param base USART peripheral base address - * @param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle); - -/*! - * @brief Aborts the received data using DMA. - * - * This function aborts the received data using DMA. - * - * @param base USART peripheral base address - * @param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); - -/*! - * @brief Get the number of bytes that have been sent. - * - * This function gets the number of bytes that have been sent. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Sent bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_USART_DMA_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_freertos.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_freertos.c deleted file mode 100644 index b6eae5bd147..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_freertos.c +++ /dev/null @@ -1,368 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_usart_freertos.h" -#include -#include -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_freertos" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -static void USART_RTOS_Callback(USART_Type *base, usart_handle_t *state, status_t status, void *param) -{ - usart_rtos_handle_t *handle = (usart_rtos_handle_t *)param; - BaseType_t xHigherPriorityTaskWoken, xResult; - - xHigherPriorityTaskWoken = pdFALSE; - xResult = pdFAIL; - - if (status == kStatus_USART_RxIdle) - { - xResult = xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_USART_COMPLETE, &xHigherPriorityTaskWoken); - } - else if (status == kStatus_USART_TxIdle) - { - xResult = xEventGroupSetBitsFromISR(handle->txEvent, RTOS_USART_COMPLETE, &xHigherPriorityTaskWoken); - } - else if (status == kStatus_USART_RxRingBufferOverrun) - { - xResult = xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_USART_RING_BUFFER_OVERRUN, &xHigherPriorityTaskWoken); - } - else - { - xResult = pdFAIL; - } - - if (xResult != pdFAIL) - { - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : USART_RTOS_Init - * Description : Initializes the USART instance for application - * - *END**************************************************************************/ -/*! - * brief Initializes a USART instance for operation in RTOS. - * - * param handle The RTOS USART handle, the pointer to allocated space for RTOS context. - * param t_handle The pointer to allocated space where to store transactional layer internal state. - * param cfg The pointer to the parameters required to configure the USART after initialization. - * return kStatus_Success, others fail. - */ -int USART_RTOS_Init(usart_rtos_handle_t *handle, usart_handle_t *t_handle, const struct rtos_usart_config *cfg) -{ - status_t status; - usart_config_t defcfg; - - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - if (NULL == t_handle) - { - return kStatus_InvalidArgument; - } - if (NULL == cfg) - { - return kStatus_InvalidArgument; - } - if (NULL == cfg->base) - { - return kStatus_InvalidArgument; - } - if (0U == cfg->srcclk) - { - return kStatus_InvalidArgument; - } - if (0U == cfg->baudrate) - { - return kStatus_InvalidArgument; - } - - handle->base = cfg->base; - handle->t_state = t_handle; - - handle->txSemaphore = xSemaphoreCreateMutex(); - if (NULL == handle->txSemaphore) - { - return kStatus_Fail; - } - handle->rxSemaphore = xSemaphoreCreateMutex(); - if (NULL == handle->rxSemaphore) - { - vSemaphoreDelete(handle->txSemaphore); - return kStatus_Fail; - } - handle->txEvent = xEventGroupCreate(); - if (NULL == handle->txEvent) - { - vSemaphoreDelete(handle->rxSemaphore); - vSemaphoreDelete(handle->txSemaphore); - return kStatus_Fail; - } - handle->rxEvent = xEventGroupCreate(); - if (NULL == handle->rxEvent) - { - vEventGroupDelete(handle->txEvent); - vSemaphoreDelete(handle->rxSemaphore); - vSemaphoreDelete(handle->txSemaphore); - return kStatus_Fail; - } - USART_GetDefaultConfig(&defcfg); - - defcfg.baudRate_Bps = cfg->baudrate; - defcfg.parityMode = cfg->parity; - defcfg.enableTx = true; - defcfg.enableRx = true; - - status = USART_Init(handle->base, &defcfg, cfg->srcclk); - if (status != kStatus_Success) - { - vEventGroupDelete(handle->rxEvent); - vEventGroupDelete(handle->txEvent); - vSemaphoreDelete(handle->rxSemaphore); - vSemaphoreDelete(handle->txSemaphore); - return kStatus_Fail; - } - status = USART_TransferCreateHandle(handle->base, handle->t_state, USART_RTOS_Callback, handle); - if (status != kStatus_Success) - { - vEventGroupDelete(handle->rxEvent); - vEventGroupDelete(handle->txEvent); - vSemaphoreDelete(handle->rxSemaphore); - vSemaphoreDelete(handle->txSemaphore); - return kStatus_Fail; - } - USART_TransferStartRingBuffer(handle->base, handle->t_state, cfg->buffer, cfg->buffer_size); - return kStatus_Success; -} - -/*FUNCTION********************************************************************** - * - * Function Name : USART_RTOS_Deinit - * Description : Deinitializes the USART instance and frees resources - * - *END**************************************************************************/ -/*! - * brief Deinitializes a USART instance for operation. - * - * This function deinitializes the USART module, sets all register values to reset value, - * and releases the resources. - * - * param handle The RTOS USART handle. - */ -int USART_RTOS_Deinit(usart_rtos_handle_t *handle) -{ - USART_Deinit(handle->base); - - vEventGroupDelete(handle->txEvent); - vEventGroupDelete(handle->rxEvent); - - /* Give the semaphore. This is for functional safety */ - (void)xSemaphoreGive(handle->txSemaphore); - (void)xSemaphoreGive(handle->rxSemaphore); - - vSemaphoreDelete(handle->txSemaphore); - vSemaphoreDelete(handle->rxSemaphore); - - /* Invalidate the handle */ - handle->base = NULL; - handle->t_state = NULL; - - return kStatus_Success; -} - -/*FUNCTION********************************************************************** - * - * Function Name : USART_RTOS_Send - * Description : Initializes the USART instance for application - * - *END**************************************************************************/ -/*! - * brief Sends data in the background. - * - * This function sends data. It is a synchronous API. - * If the hardware buffer is full, the task is in the blocked state. - * - * param handle The RTOS USART handle. - * param buffer The pointer to buffer to send. - * param length The number of bytes to send. - */ -int USART_RTOS_Send(usart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length) -{ - EventBits_t ev; - int retval = kStatus_Success; - status_t status; - - if (NULL == handle->base) - { - /* Invalid handle. */ - return kStatus_Fail; - } - if (0U == length) - { - return kStatus_Success; - } - if (NULL == buffer) - { - return kStatus_InvalidArgument; - } - - if (pdFALSE == xSemaphoreTake(handle->txSemaphore, 0)) - { - /* We could not take the semaphore, exit with 0 data received */ - return kStatus_Fail; - } - - handle->txTransfer.data = (uint8_t *)buffer; - handle->txTransfer.dataSize = (uint32_t)length; - - /* Non-blocking call */ - status = USART_TransferSendNonBlocking(handle->base, handle->t_state, &handle->txTransfer); - if (status != kStatus_Success) - { - (void)xSemaphoreGive(handle->txSemaphore); - return kStatus_Fail; - } - - ev = xEventGroupWaitBits(handle->txEvent, RTOS_USART_COMPLETE, pdTRUE, pdFALSE, portMAX_DELAY); - if ((ev & RTOS_USART_COMPLETE) == 0U) - { - retval = kStatus_Fail; - } - - if (pdFALSE == xSemaphoreGive(handle->txSemaphore)) - { - /* We could not post the semaphore, exit with error */ - retval = kStatus_Fail; - } - - return retval; -} - -/*FUNCTION********************************************************************** - * - * Function Name : USART_RTOS_Recv - * Description : Receives chars for the application - * - *END**************************************************************************/ -/*! - * brief Receives data. - * - * This function receives data from USART. It is a synchronous API. If data is immediately available, - * it is returned immediately and the number of bytes received. - * - * param handle The RTOS USART handle. - * param buffer The pointer to buffer where to write received data. - * param length The number of bytes to receive. - * param received The pointer to a variable of size_t where the number of received data is filled. - */ -int USART_RTOS_Receive(usart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length, size_t *received) -{ - EventBits_t ev; - size_t n = 0; - int retval = kStatus_Fail; - size_t local_received = 0; - status_t status; - - if (NULL == handle->base) - { - /* Invalid handle. */ - return kStatus_Fail; - } - if (0U == length) - { - if (received != NULL) - { - *received = n; - } - return kStatus_Success; - } - if (NULL == buffer) - { - return kStatus_InvalidArgument; - } - - /* New transfer can be performed only after current one is finished */ - if (pdFALSE == xSemaphoreTake(handle->rxSemaphore, portMAX_DELAY)) - { - /* We could not take the semaphore, exit with 0 data received */ - return kStatus_Fail; - } - - handle->rxTransfer.data = buffer; - handle->rxTransfer.dataSize = (uint32_t)length; - - /* Non-blocking call */ - status = USART_TransferReceiveNonBlocking(handle->base, handle->t_state, &handle->rxTransfer, &n); - if (status != kStatus_Success) - { - (void)xSemaphoreGive(handle->rxSemaphore); - return kStatus_Fail; - } - - ev = xEventGroupWaitBits(handle->rxEvent, RTOS_USART_COMPLETE | RTOS_USART_RING_BUFFER_OVERRUN, pdTRUE, pdFALSE, - portMAX_DELAY); - if ((ev & RTOS_USART_RING_BUFFER_OVERRUN) != 0U) - { - /* Stop data transfer to application buffer, ring buffer is still active */ - USART_TransferAbortReceive(handle->base, handle->t_state); - /* Prevent false indication of successful transfer in next call of USART_RTOS_Receive. - RTOS_USART_COMPLETE flag could be set meanwhile overrun is handled */ - (void)xEventGroupClearBits(handle->rxEvent, RTOS_USART_COMPLETE); - retval = kStatus_USART_RxRingBufferOverrun; - local_received = 0; - } - else if ((ev & RTOS_USART_COMPLETE) != 0U) - { - retval = kStatus_Success; - local_received = length; - } - else - { - retval = kStatus_USART_RxError; - local_received = 0; - } - - /* Prevent repetitive NULL check */ - if (received != NULL) - { - *received = local_received; - } - - /* Enable next transfer. Current one is finished */ - if (pdFALSE == xSemaphoreGive(handle->rxSemaphore)) - { - /* We could not post the semaphore, exit with error */ - retval = kStatus_Fail; - } - return retval; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_freertos.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_freertos.h deleted file mode 100644 index 0b21386ad32..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_freertos.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef __FSL_USART_FREERTOS_H__ -#define __FSL_USART_FREERTOS_H__ - -#include "fsl_usart.h" -#include -#include -#include - -/*! - * @addtogroup usart_freertos_driver - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief USART FreeRTOS driver version. */ -#define FSL_USART_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 6, 0)) -/*@}*/ - -/*! @brief FLEX USART configuration structure */ -struct rtos_usart_config -{ - USART_Type *base; /*!< USART base address */ - uint32_t srcclk; /*!< USART source clock in Hz*/ - uint32_t baudrate; /*!< Desired communication speed */ - usart_parity_mode_t parity; /*!< Parity setting */ - usart_stop_bit_count_t stopbits; /*!< Number of stop bits to use */ - uint8_t *buffer; /*!< Buffer for background reception */ - uint32_t buffer_size; /*!< Size of buffer for background reception */ -}; - -/*! @brief FLEX USART FreeRTOS handle */ -typedef struct _usart_rtos_handle -{ - USART_Type *base; /*!< USART base address */ - usart_transfer_t txTransfer; /*!< TX transfer structure */ - usart_transfer_t rxTransfer; /*!< RX transfer structure */ - SemaphoreHandle_t rxSemaphore; /*!< RX semaphore for resource sharing */ - SemaphoreHandle_t txSemaphore; /*!< TX semaphore for resource sharing */ -#define RTOS_USART_COMPLETE 0x1U -#define RTOS_USART_RING_BUFFER_OVERRUN 0x2U -#define RTOS_USART_HARDWARE_BUFFER_OVERRUN 0x4U - EventGroupHandle_t rxEvent; /*!< RX completion event */ - EventGroupHandle_t txEvent; /*!< TX completion event */ - void *t_state; /*!< Transactional state of the underlying driver */ -} usart_rtos_handle_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name USART RTOS Operation - * @{ - */ - -/*! - * @brief Initializes a USART instance for operation in RTOS. - * - * @param handle The RTOS USART handle, the pointer to allocated space for RTOS context. - * @param t_handle The pointer to allocated space where to store transactional layer internal state. - * @param cfg The pointer to the parameters required to configure the USART after initialization. - * @return 0 succeed, others fail. - */ -int USART_RTOS_Init(usart_rtos_handle_t *handle, usart_handle_t *t_handle, const struct rtos_usart_config *cfg); - -/*! - * @brief Deinitializes a USART instance for operation. - * - * This function deinitializes the USART module, sets all register values to reset value, - * and releases the resources. - * - * @param handle The RTOS USART handle. - */ -int USART_RTOS_Deinit(usart_rtos_handle_t *handle); - -/*! - * @name USART transactional Operation - * @{ - */ - -/*! - * @brief Sends data in the background. - * - * This function sends data. It is a synchronous API. - * If the hardware buffer is full, the task is in the blocked state. - * - * @param handle The RTOS USART handle. - * @param buffer The pointer to buffer to send. - * @param length The number of bytes to send. - */ -int USART_RTOS_Send(usart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length); - -/*! - * @brief Receives data. - * - * This function receives data from USART. It is a synchronous API. If data is immediately available, - * it is returned immediately and the number of bytes received. - * - * @param handle The RTOS USART handle. - * @param buffer The pointer to buffer where to write received data. - * @param length The number of bytes to receive. - * @param received The pointer to a variable of size_t where the number of received data is filled. - */ -int USART_RTOS_Receive(usart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length, size_t *received); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* __FSL_USART_FREERTOS_H__ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_utick.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_utick.c deleted file mode 100644 index 0eea419cd34..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_utick.c +++ /dev/null @@ -1,230 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019, 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_utick.h" -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG) -#include "fsl_power.h" -#endif -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.utick" -#endif - -/* Typedef for interrupt handler. */ -typedef void (*utick_isr_t)(UTICK_Type *base, utick_callback_t cb); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base UTICK peripheral base address - * - * @return The UTICK instance - */ -static uint32_t UTICK_GetInstance(UTICK_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of UTICK handle. */ -static utick_callback_t s_utickHandle[FSL_FEATURE_SOC_UTICK_COUNT]; -/* Array of UTICK peripheral base address. */ -static UTICK_Type *const s_utickBases[] = UTICK_BASE_PTRS; -/* Array of UTICK IRQ number. */ -static const IRQn_Type s_utickIRQ[] = UTICK_IRQS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of UTICK clock name. */ -static const clock_ip_name_t s_utickClock[] = UTICK_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) -/*! @brief Pointers to UTICK resets for each instance. */ -static const reset_ip_name_t s_utickResets[] = UTICK_RSTS; -#endif - -/* UTICK ISR for transactional APIs. */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -static utick_isr_t s_utickIsr = (utick_isr_t)DefaultISR; -#else -static utick_isr_t s_utickIsr; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t UTICK_GetInstance(UTICK_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_utickBases); instance++) - { - if (s_utickBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_utickBases)); - - return instance; -} - -/*! - * brief Starts UTICK. - * - * This function starts a repeat/onetime countdown with an optional callback - * - * param base UTICK peripheral base address. - * param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) - * return none - */ -void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb) -{ - uint32_t instance; - - /* Get instance from peripheral base address. */ - instance = UTICK_GetInstance(base); - - /* Save the handle in global variables to support the double weak mechanism. */ - s_utickHandle[instance] = cb; -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) && \ - !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)) - EnableDeepSleepIRQ(s_utickIRQ[instance]); -#else - (void)EnableIRQ(s_utickIRQ[instance]); -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT && !FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ - base->CTRL = count | UTICK_CTRL_REPEAT(mode); -} - -/*! - * brief Initializes an UTICK by turning its bus clock on - * - */ -void UTICK_Init(UTICK_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable utick clock */ - CLOCK_EnableClock(s_utickClock[UTICK_GetInstance(base)]); -#endif - -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) - RESET_PeripheralReset(s_utickResets[UTICK_GetInstance(base)]); -#endif - -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG) - /* Power up Watchdog oscillator*/ - POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC); -#endif - - s_utickIsr = UTICK_HandleIRQ; -} - -/*! - * brief Deinitializes a UTICK instance. - * - * This function shuts down Utick bus clock - * - * param base UTICK peripheral base address. - */ -void UTICK_Deinit(UTICK_Type *base) -{ - /* Turn off utick */ - base->CTRL = 0; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable utick clock */ - CLOCK_DisableClock(s_utickClock[UTICK_GetInstance(base)]); -#endif -} - -/*! - * brief Get Status Flags. - * - * This returns the status flag - * - * param base UTICK peripheral base address. - * return status register value - */ -uint32_t UTICK_GetStatusFlags(UTICK_Type *base) -{ - return (base->STAT); -} - -/*! - * brief Clear Status Interrupt Flags. - * - * This clears intr status flag - * - * param base UTICK peripheral base address. - * return none - */ -void UTICK_ClearStatusFlags(UTICK_Type *base) -{ - base->STAT = UTICK_STAT_INTR_MASK; -} - -/*! - * brief UTICK Interrupt Service Handler. - * - * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request - * in UTICK_SetTick()). - * if no user callback is scheduled, the interrupt will simply be cleared. - * - * param base UTICK peripheral base address. - * param cb callback scheduled for this instance of UTICK - * return none - */ -void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb) -{ - UTICK_ClearStatusFlags(base); - if (cb != NULL) - { - cb(); - } -} - -#if defined(UTICK0) -void UTICK0_DriverIRQHandler(void); -void UTICK0_DriverIRQHandler(void) -{ - s_utickIsr(UTICK0, s_utickHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif -#if defined(UTICK1) -void UTICK1_DriverIRQHandler(void); -void UTICK1_DriverIRQHandler(void) -{ - s_utickIsr(UTICK1, s_utickHandle[1]); - SDK_ISR_EXIT_BARRIER; -} -#endif -#if defined(UTICK2) -void UTICK2_DriverIRQHandler(void); -void UTICK2_DriverIRQHandler(void) -{ - s_utickIsr(UTICK2, s_utickHandle[2]); - SDK_ISR_EXIT_BARRIER; -} -#endif -#if defined(UTICK) -void UTICK_DriverIRQHandler(void); -void UTICK_DriverIRQHandler(void) -{ - s_utickIsr(UTICK, s_utickHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_utick.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_utick.h deleted file mode 100644 index 48c7d6b86de..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_utick.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019, 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_UTICK_H_ -#define _FSL_UTICK_H_ - -#include "fsl_common.h" -/*! - * @addtogroup utick - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief UTICK driver version 2.0.5. */ -#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) -/*@}*/ - -/*! @brief UTICK timer operational mode. */ -typedef enum _utick_mode -{ - kUTICK_Onetime = 0x0U, /*!< Trigger once*/ - kUTICK_Repeat = 0x1U, /*!< Trigger repeatedly */ -} utick_mode_t; - -/*! @brief UTICK callback function. */ -typedef void (*utick_callback_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes an UTICK by turning its bus clock on - * - */ -void UTICK_Init(UTICK_Type *base); - -/*! - * @brief Deinitializes a UTICK instance. - * - * This function shuts down Utick bus clock - * - * @param base UTICK peripheral base address. - */ -void UTICK_Deinit(UTICK_Type *base); -/*! - * @brief Get Status Flags. - * - * This returns the status flag - * - * @param base UTICK peripheral base address. - * @return status register value - */ -uint32_t UTICK_GetStatusFlags(UTICK_Type *base); -/*! - * @brief Clear Status Interrupt Flags. - * - * This clears intr status flag - * - * @param base UTICK peripheral base address. - * @return none - */ -void UTICK_ClearStatusFlags(UTICK_Type *base); - -/*! - * @brief Starts UTICK. - * - * This function starts a repeat/onetime countdown with an optional callback - * - * @param base UTICK peripheral base address. - * @param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * @param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * @param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) - * @return none - */ -void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb); -/*! - * @brief UTICK Interrupt Service Handler. - * - * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request - * in UTICK_SetTick()). - * if no user callback is scheduled, the interrupt will simply be cleared. - * - * @param base UTICK peripheral base address. - * @param cb callback scheduled for this instance of UTICK - * @return none - */ -void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_UTICK_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_wwdt.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_wwdt.c deleted file mode 100644 index 6680148acf7..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_wwdt.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_wwdt.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.wwdt" -#endif - -#define FREQUENCY_3MHZ (3000000U) -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Gets the instance from the base address - * - * @param base WWDT peripheral base address - * - * @return The WWDT instance - */ -static uint32_t WWDT_GetInstance(WWDT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to WWDT bases for each instance. */ -static WWDT_Type *const s_wwdtBases[] = WWDT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to WWDT clocks for each instance. */ -static const clock_ip_name_t s_wwdtClocks[] = WWDT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) -/*! @brief Pointers to WWDT resets for each instance. */ -static const reset_ip_name_t s_wwdtResets[] = WWDT_RSTS; -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t WWDT_GetInstance(WWDT_Type *base) -{ - uint32_t instance; - uint32_t wwdtArrayCount = (sizeof(s_wwdtBases) / sizeof(s_wwdtBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < wwdtArrayCount; instance++) - { - if (s_wwdtBases[instance] == base) - { - break; - } - } - - assert(instance < wwdtArrayCount); - - return instance; -} - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Initializes WWDT configure structure. - * - * This function initializes the WWDT configure structure to default value. The default - * value are: - * code - * config->enableWwdt = true; - * config->enableWatchdogReset = false; - * config->enableWatchdogProtect = false; - * config->enableLockOscillator = false; - * config->windowValue = 0xFFFFFFU; - * config->timeoutValue = 0xFFFFFFU; - * config->warningValue = 0; - * endcode - * - * param config Pointer to WWDT config structure. - * see wwdt_config_t - */ -void WWDT_GetDefaultConfig(wwdt_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - /* Enable the watch dog */ - config->enableWwdt = true; - /* Disable the watchdog timeout reset */ - config->enableWatchdogReset = false; - /* Disable the watchdog protection for updating the timeout value */ - config->enableWatchdogProtect = false; -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) - /* Do not lock the watchdog oscillator */ - config->enableLockOscillator = false; -#endif - /* Windowing is not in effect */ - config->windowValue = 0xFFFFFFU; - /* Set the timeout value to the max */ - config->timeoutValue = 0xFFFFFFU; - /* No warning is provided */ - config->warningValue = 0; - /* Set clock frequency. */ - config->clockFreq_Hz = 0U; -} - -/*! - * brief Initializes the WWDT. - * - * This function initializes the WWDT. When called, the WWDT runs according to the configuration. - * - * Example: - * code - * wwdt_config_t config; - * WWDT_GetDefaultConfig(&config); - * config.timeoutValue = 0x7ffU; - * WWDT_Init(wwdt_base,&config); - * endcode - * - * param base WWDT peripheral base address - * param config The configuration of WWDT - */ -void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config) -{ - assert(NULL != config); - - uint32_t value = 0U; - uint32_t DelayUs = 0U; - uint32_t primaskValue = 0U; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the WWDT clock */ - CLOCK_EnableClock(s_wwdtClocks[WWDT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) - /* Reset the module. */ - RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]); -#endif - -#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) - /* PMC RESETCAUSE: set bit to clear it by write 1. */ - PMC->RESETCAUSE = PMC_RESETCAUSE_WDTRESET_MASK; - /* Enable the watchdog reset event to affect the system in the Power Management Controller */ - PMC->CTRL |= PMC_CTRL_WDTRESETENABLE_MASK; -#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ - -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) - value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) | - WWDT_MOD_LOCK(config->enableLockOscillator); -#else - value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset); -#endif - /* Clear legacy flag in the MOD register by software writing a "1" to this bit field.. */ - if (0U != (base->MOD & WWDT_MOD_WDINT_MASK)) - { - value |= WWDT_MOD_WDINT_MASK; - } - /* Set configuration */ - primaskValue = DisableGlobalIRQ(); - base->TC = WWDT_TC_COUNT(config->timeoutValue); - base->MOD = value; - base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue); - base->WARNINT = WWDT_WARNINT_WARNINT(config->warningValue); - /* Refreshes the WWDT timer. */ - base->FEED = WWDT_FIRST_WORD_OF_REFRESH; - base->FEED = WWDT_SECOND_WORD_OF_REFRESH; - EnableGlobalIRQ(primaskValue); - /* Read counter value to wait wwdt timer start*/ - if (config->enableWwdt) - { - while (base->TV == 0xFFUL) - { - } - } - - /* This WDPROTECT bit can be set once by software and is only cleared by a reset */ - if (config->enableWatchdogProtect && (0U == (base->MOD & WWDT_MOD_WDPROTECT_MASK))) - { - /* The config->clockFreq_Hz must be set in order to config the delay time. */ - assert(0U != config->clockFreq_Hz); - - /* Set the WDPROTECT bit after the Feed Sequence (0xAA, 0x55) with 3 WDCLK delay */ - DelayUs = FREQUENCY_3MHZ / config->clockFreq_Hz + 1U; - SDK_DelayAtLeastUs(DelayUs, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - - base->MOD |= WWDT_MOD_WDPROTECT(1U); - } -} - -/*! - * brief Shuts down the WWDT. - * - * This function shuts down the WWDT. - * - * param base WWDT peripheral base address - */ -void WWDT_Deinit(WWDT_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the WWDT clock */ - CLOCK_DisableClock(s_wwdtClocks[WWDT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Refreshes the WWDT timer. - * - * This function feeds the WWDT. - * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. - * - * param base WWDT peripheral base address - */ -void WWDT_Refresh(WWDT_Type *base) -{ - uint32_t primaskValue = 0U; - - /* Disable the global interrupt to protect refresh sequence */ - primaskValue = DisableGlobalIRQ(); - base->FEED = WWDT_FIRST_WORD_OF_REFRESH; - base->FEED = WWDT_SECOND_WORD_OF_REFRESH; - EnableGlobalIRQ(primaskValue); -} - -/*! - * brief Clear WWDT flag. - * - * This function clears WWDT status flag. - * - * Example for clearing warning flag: - * code - * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); - * endcode - * param base WWDT peripheral base address - * param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask) -{ - /* Clear the WDINT bit so that we don't accidentally clear it */ - uint32_t reg = (base->MOD & (~WWDT_MOD_WDINT_MASK)); - - /* Clear timeout by writing a zero */ - if (0U != (mask & (uint32_t)kWWDT_TimeoutFlag)) - { - reg &= ~WWDT_MOD_WDTOF_MASK; -#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) - /* PMC RESETCAUSE: set bit to clear it */ - PMC->RESETCAUSE = PMC_RESETCAUSE_WDTRESET_MASK; -#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ - } - - /* Clear warning interrupt flag by writing a one */ - if (0U != (mask & (uint32_t)kWWDT_WarningFlag)) - { - reg |= WWDT_MOD_WDINT_MASK; - } - - base->MOD = reg; -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_wwdt.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_wwdt.h deleted file mode 100644 index 25462534966..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_wwdt.h +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_WWDT_H_ -#define _FSL_WWDT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup wwdt - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Defines WWDT driver version. */ -#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 1, 9)) -/*@}*/ - -/*! @name Refresh sequence */ -/*@{*/ -#define WWDT_FIRST_WORD_OF_REFRESH (0xAAU) /*!< First word of refresh sequence */ -#define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */ -/*@}*/ - -/*! @brief Describes WWDT configuration structure. */ -typedef struct _wwdt_config -{ - bool enableWwdt; /*!< Enables or disables WWDT */ - bool enableWatchdogReset; /*!< true: Watchdog timeout will cause a chip reset - false: Watchdog timeout will not cause a chip reset */ - bool enableWatchdogProtect; /*!< true: Enable watchdog protect i.e timeout value can only be - changed after counter is below warning & window values - false: Disable watchdog protect; timeout value can be changed - at any time */ -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) - bool enableLockOscillator; /*!< true: Disabling or powering down the watchdog oscillator is prevented - Once set, this bit can only be cleared by a reset - false: Do not lock oscillator */ -#endif - uint32_t windowValue; /*!< Window value, set this to 0xFFFFFF if windowing is not in effect */ - uint32_t timeoutValue; /*!< Timeout value */ - uint32_t warningValue; /*!< Watchdog time counter value that will generate a - warning interrupt. Set this to 0 for no warning */ - uint32_t clockFreq_Hz; /*!< Watchdog clock source frequency. */ -} wwdt_config_t; - -/*! - * @brief WWDT status flags. - * - * This structure contains the WWDT status flags for use in the WWDT functions. - */ -enum _wwdt_status_flags_t -{ - kWWDT_TimeoutFlag = WWDT_MOD_WDTOF_MASK, /*!< Time-out flag, set when the timer times out */ - kWWDT_WarningFlag = WWDT_MOD_WDINT_MASK /*!< Warning interrupt flag, set when timer is below the value WDWARNINT */ -}; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name WWDT Initialization and De-initialization - * @{ - */ - -/*! - * @brief Initializes WWDT configure structure. - * - * This function initializes the WWDT configure structure to default value. The default - * value are: - * @code - * config->enableWwdt = true; - * config->enableWatchdogReset = false; - * config->enableWatchdogProtect = false; - * config->enableLockOscillator = false; - * config->windowValue = 0xFFFFFFU; - * config->timeoutValue = 0xFFFFFFU; - * config->warningValue = 0; - * @endcode - * - * @param config Pointer to WWDT config structure. - * @see wwdt_config_t - */ -void WWDT_GetDefaultConfig(wwdt_config_t *config); - -/*! - * @brief Initializes the WWDT. - * - * This function initializes the WWDT. When called, the WWDT runs according to the configuration. - * - * Example: - * @code - * wwdt_config_t config; - * WWDT_GetDefaultConfig(&config); - * config.timeoutValue = 0x7ffU; - * WWDT_Init(wwdt_base,&config); - * @endcode - * - * @param base WWDT peripheral base address - * @param config The configuration of WWDT - */ -void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config); - -/*! - * @brief Shuts down the WWDT. - * - * This function shuts down the WWDT. - * - * @param base WWDT peripheral base address - */ -void WWDT_Deinit(WWDT_Type *base); - -/* @} */ - -/*! - * @name WWDT Functional Operation - * @{ - */ - -/*! - * @brief Enables the WWDT module. - * - * This function write value into WWDT_MOD register to enable the WWDT, it is a write-once bit; - * once this bit is set to one and a watchdog feed is performed, the watchdog timer will run - * permanently. - * - * @param base WWDT peripheral base address - */ -static inline void WWDT_Enable(WWDT_Type *base) -{ - base->MOD |= WWDT_MOD_WDEN_MASK; -} - -/*! - * @brief Disables the WWDT module. - * @deprecated Do not use this function. It will be deleted in next release version, for - * once the bit field of WDEN written with a 1, it can not be re-written with a 0. - * - * This function write value into WWDT_MOD register to disable the WWDT. - * - * @param base WWDT peripheral base address - */ -static inline void WWDT_Disable(WWDT_Type *base) -{ - base->MOD &= ~WWDT_MOD_WDEN_MASK; -} - -/*! - * @brief Gets all WWDT status flags. - * - * This function gets all status flags. - * - * Example for getting Timeout Flag: - * @code - * uint32_t status; - * status = WWDT_GetStatusFlags(wwdt_base) & kWWDT_TimeoutFlag; - * @endcode - * @param base WWDT peripheral base address - * @return The status flags. This is the logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -static inline uint32_t WWDT_GetStatusFlags(WWDT_Type *base) -{ -#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) - uint32_t status; - /* WDTOF is not set in case of WD reset - get info from PMC instead */ - status = (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); - if (PMC->RESETCAUSE & PMC_RESETCAUSE_WDTRESET_MASK) - { - status |= kWWDT_TimeoutFlag; - } - return status; -#else - return (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); -#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ -} - -/*! - * @brief Clear WWDT flag. - * - * This function clears WWDT status flag. - * - * Example for clearing warning flag: - * @code - * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); - * @endcode - * @param base WWDT peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask); - -/*! - * @brief Set the WWDT warning value. - * - * The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog - * interrupt. When the watchdog timer counter is no longer greater than the value defined by - * WARNINT, an interrupt will be generated after the subsequent WDCLK. - * - * @param base WWDT peripheral base address - * @param warningValue WWDT warning value. - */ -static inline void WWDT_SetWarningValue(WWDT_Type *base, uint32_t warningValue) -{ - base->WARNINT = WWDT_WARNINT_WARNINT(warningValue); -} - -/*! - * @brief Set the WWDT timeout value. - * - * This function sets the timeout value. Every time a feed sequence occurs the value in the TC - * register is loaded into the Watchdog timer. Writing a value below 0xFF will cause 0xFF to be - * loaded into the TC register. Thus the minimum time-out interval is TWDCLK*256*4. - * If enableWatchdogProtect flag is true in wwdt_config_t config structure, any attempt to change - * the timeout value before the watchdog counter is below the warning and window values - * will cause a watchdog reset and set the WDTOF flag. - * - * @param base WWDT peripheral base address - * @param timeoutCount WWDT timeout value, count of WWDT clock tick. - */ -static inline void WWDT_SetTimeoutValue(WWDT_Type *base, uint32_t timeoutCount) -{ - base->TC = WWDT_TC_COUNT(timeoutCount); -} - -/*! - * @brief Sets the WWDT window value. - * - * The WINDOW register determines the highest TV value allowed when a watchdog feed is performed. - * If a feed sequence occurs when timer value is greater than the value in WINDOW, a watchdog - * event will occur. To disable windowing, set windowValue to 0xFFFFFF (maximum possible timer - * value) so windowing is not in effect. - * - * @param base WWDT peripheral base address - * @param windowValue WWDT window value. - */ -static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue) -{ - base->WINDOW = WWDT_WINDOW_WINDOW(windowValue); -} - -/*! - * @brief Refreshes the WWDT timer. - * - * This function feeds the WWDT. - * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. - * - * @param base WWDT peripheral base address - */ -void WWDT_Refresh(WWDT_Type *base); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_WWDT_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/fsl_device_registers.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/fsl_device_registers.h deleted file mode 100644 index d75a93b2d77..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/fsl_device_registers.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __FSL_DEVICE_REGISTERS_H__ -#define __FSL_DEVICE_REGISTERS_H__ - -/* - * Include the cpu specific register header files. - * - * The CPU macro should be declared in the project or makefile. - */ -#if (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || \ - defined(CPU_LPC55S69JEV98_cm33_core0)) - -#define LPC55S69_cm33_core0_SERIES - -/* CMSIS-style register definitions */ -#include "LPC55S69_cm33_core0.h" -/* CPU specific feature definitions */ -#include "LPC55S69_cm33_core0_features.h" - -#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || \ - defined(CPU_LPC55S69JEV98_cm33_core1)) - -#define LPC55S69_cm33_core1_SERIES - -/* CMSIS-style register definitions */ -#include "LPC55S69_cm33_core1.h" -/* CPU specific feature definitions */ -#include "LPC55S69_cm33_core1_features.h" - -#else -#error "No valid CPU defined!" -#endif - -#endif /* __FSL_DEVICE_REGISTERS_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash.ld b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash.ld deleted file mode 100644 index ef9bc99b69e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash.ld +++ /dev/null @@ -1,234 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JBD64_cm33_core0 -** LPC55S69JEV98_cm33_core0 -** -** Compiler: GNU C Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b210928 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; -RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000200 - m_text (RX) : ORIGIN = 0x00000200, LENGTH = 0x00071E00 - m_core1_image (RX) : ORIGIN = 0x00072000, LENGTH = 0x0002B800 - m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00033000 - RPMSG_SHMEM_SIZE - rpmsg_sh_mem (RW) : ORIGIN = 0x20033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE - m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000 -} - -/* Define output sections */ -SECTIONS -{ - /* section for storing the secondary core image */ - .core1_code : - { - . = ALIGN(4) ; - KEEP (*(.core1_code)) - *(.core1_code*) - . = ALIGN(4) ; - } > m_core1_image - - /* NOINIT section for rpmsg_sh_mem */ - .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) - { - __RPMSG_SH_MEM_START__ = .; - *(.noinit.$rpmsg_sh_mem*) - . = ALIGN(4) ; - __RPMSG_SH_MEM_END__ = .; - } > rpmsg_sh_mem - - /* The startup code goes first into internal flash */ - .interrupts : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.ramfunc*) /* for functions in ram */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - m_usb_bdt (NOLOAD) : - { - . = ALIGN(512); - *(m_usb_bdt) - } > m_usb_sram - - m_usb_global (NOLOAD) : - { - *(m_usb_global) - } > m_usb_sram - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash_ns.ld b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash_ns.ld deleted file mode 100644 index 22dd623ec5e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash_ns.ld +++ /dev/null @@ -1,234 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JBD64_cm33_core0 -** LPC55S69JEV98_cm33_core0 -** -** Compiler: GNU C Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b190926 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; -RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x00010000, LENGTH = 0x00000200 - m_text (RX) : ORIGIN = 0x00010200, LENGTH = 0x00061E00 - m_core1_image (RX) : ORIGIN = 0x00072000, LENGTH = 0x0002B800 - m_data (RW) : ORIGIN = 0x20008000, LENGTH = 0x0002A800 - RPMSG_SHMEM_SIZE - rpmsg_sh_mem (RW) : ORIGIN = 0x20033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE - m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000 -} - -/* Define output sections */ -SECTIONS -{ - /* section for storing the secondary core image */ - .core1_code : - { - . = ALIGN(4) ; - KEEP (*(.core1_code)) - *(.core1_code*) - . = ALIGN(4) ; - } > m_core1_image - - /* NOINIT section for rpmsg_sh_mem */ - .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) - { - __RPMSG_SH_MEM_START__ = .; - *(.noinit.$rpmsg_sh_mem*) - . = ALIGN(4) ; - __RPMSG_SH_MEM_END__ = .; - } > rpmsg_sh_mem - - /* The startup code goes first into internal flash */ - .interrupts : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.ramfunc*) /* for functions in ram */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - m_usb_bdt (NOLOAD) : - { - . = ALIGN(512); - *(m_usb_bdt) - } > m_usb_sram - - m_usb_global (NOLOAD) : - { - *(m_usb_global) - } > m_usb_sram - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash_s.ld b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash_s.ld deleted file mode 100644 index 69edc592d29..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash_s.ld +++ /dev/null @@ -1,245 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JBD64_cm33_core0 -** LPC55S69JEV98_cm33_core0 -** -** Compiler: GNU C Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b190926 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; -RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x10000000, LENGTH = 0x00000200 - m_text (RX) : ORIGIN = 0x10000200, LENGTH = 0x0000FC00 - m_veneer_table (RX) : ORIGIN = 0x1000FE00, LENGTH = 0x00000200 - m_core1_image (RX) : ORIGIN = 0x10072000, LENGTH = 0x0002B800 - m_data (RW) : ORIGIN = 0x30000000, LENGTH = 0x00008000 - rpmsg_sh_mem (RW) : ORIGIN = 0x30033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE - m_usb_sram (RW) : ORIGIN = 0x50100000, LENGTH = 0x00004000 -} - -/* Define output sections */ -SECTIONS -{ - /* section for storing the secondary core image */ - .core1_code : - { - . = ALIGN(4) ; - KEEP (*(.core1_code)) - *(.core1_code*) - . = ALIGN(4) ; - } > m_core1_image - - /* NOINIT section for rpmsg_sh_mem */ - .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) - { - __RPMSG_SH_MEM_START__ = .; - *(.noinit.$rpmsg_sh_mem*) - . = ALIGN(4) ; - __RPMSG_SH_MEM_END__ = .; - } > rpmsg_sh_mem - - /* The startup code goes first into internal flash */ - .interrupts : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - /* section for veneer table */ - .gnu.sgstubs : - { - . = ALIGN(32); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > m_veneer_table - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.ramfunc*) /* for functions in ram */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - m_usb_bdt (NOLOAD) : - { - . = ALIGN(512); - *(m_usb_bdt) - } > m_usb_sram - - m_usb_global (NOLOAD) : - { - *(m_usb_global) - } > m_usb_sram - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_ram.ld b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_ram.ld deleted file mode 100644 index c2d4269000f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_ram.ld +++ /dev/null @@ -1,234 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JBD64_cm33_core0 -** LPC55S69JEV98_cm33_core0 -** -** Compiler: GNU C Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b200722 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2020 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; -RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x04000000, LENGTH = 0x00000200 - m_text (RX) : ORIGIN = 0x04000200, LENGTH = 0x00007E00 - m_core1_image (RX) : ORIGIN = 0x20033000, LENGTH = 0x0000C800 - m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00033000 - RPMSG_SHMEM_SIZE - rpmsg_sh_mem (RW) : ORIGIN = 0x20033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE - m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000 -} - -/* Define output sections */ -SECTIONS -{ - /* section for storing the secondary core image */ - .core1_code : - { - . = ALIGN(4) ; - KEEP (*(.core1_code)) - *(.core1_code*) - . = ALIGN(4) ; - } > m_core1_image - - /* NOINIT section for rpmsg_sh_mem */ - .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) - { - __RPMSG_SH_MEM_START__ = .; - *(.noinit.$rpmsg_sh_mem*) - . = ALIGN(4) ; - __RPMSG_SH_MEM_END__ = .; - } > rpmsg_sh_mem - - /* The startup code goes first into internal flash */ - .interrupts : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.ramfunc*) /* for functions in ram */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - m_usb_bdt (NOLOAD) : - { - . = ALIGN(512); - *(m_usb_bdt) - } > m_usb_sram - - m_usb_global (NOLOAD) : - { - *(m_usb_global) - } > m_usb_sram - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_flash.ld b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_flash.ld deleted file mode 100644 index 159b7b1f15d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_flash.ld +++ /dev/null @@ -1,224 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JBD64_cm33_core1 -** LPC55S69JEV98_cm33_core1 -** -** Compiler: GNU C Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b210928 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; -RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x00072000, LENGTH = 0x00000200 - m_text (RX) : ORIGIN = 0x00072200, LENGTH = 0x0002B600 - m_data (RW) : ORIGIN = 0x20033000, LENGTH = 0x00011000 - rpmsg_sh_mem (RW) : ORIGIN = 0x20033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE - m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000 -} - -/* Define output sections */ -SECTIONS -{ - /* NOINIT section for rpmsg_sh_mem */ - .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) - { - __RPMSG_SH_MEM_START__ = .; - *(.noinit.$rpmsg_sh_mem*) - . = ALIGN(4) ; - __RPMSG_SH_MEM_END__ = .; - } > rpmsg_sh_mem - - /* The startup code goes first into internal flash */ - .interrupts : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.ramfunc*) /* for functions in ram */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - m_usb_bdt (NOLOAD) : - { - . = ALIGN(512); - *(m_usb_bdt) - } > m_usb_sram - - m_usb_global (NOLOAD) : - { - *(m_usb_global) - } > m_usb_sram - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_ram.ld b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_ram.ld deleted file mode 100644 index 2539c1e32ca..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_ram.ld +++ /dev/null @@ -1,224 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JBD64_cm33_core1 -** LPC55S69JEV98_cm33_core1 -** -** Compiler: GNU C Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b200722 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2020 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; -RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x20033000, LENGTH = 0x00000200 - m_text (RX) : ORIGIN = 0x20033200, LENGTH = 0x0000C600 - m_data (RW) : ORIGIN = 0x2003F800, LENGTH = 0x00004800 - rpmsg_sh_mem (RW) : ORIGIN = 0x20033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE - m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000 -} - -/* Define output sections */ -SECTIONS -{ - /* NOINIT section for rpmsg_sh_mem */ - .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) - { - __RPMSG_SH_MEM_START__ = .; - *(.noinit.$rpmsg_sh_mem*) - . = ALIGN(4) ; - __RPMSG_SH_MEM_END__ = .; - } > rpmsg_sh_mem - - /* The startup code goes first into internal flash */ - .interrupts : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.ramfunc*) /* for functions in ram */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - m_usb_bdt (NOLOAD) : - { - . = ALIGN(512); - *(m_usb_bdt) - } > m_usb_sram - - m_usb_global (NOLOAD) : - { - *(m_usb_global) - } > m_usb_sram - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_ram_s.ld b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_ram_s.ld deleted file mode 100644 index 8efdda2364a..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_ram_s.ld +++ /dev/null @@ -1,224 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JBD64_cm33_core1 -** LPC55S69JEV98_cm33_core1 -** -** Compiler: GNU C Compiler -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b190926 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; -RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x30033000, LENGTH = 0x00000200 - m_text (RX) : ORIGIN = 0x30033200, LENGTH = 0x0000C600 - m_data (RW) : ORIGIN = 0x3003F800, LENGTH = 0x00004800 - rpmsg_sh_mem (RW) : ORIGIN = 0x30033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE - m_usb_sram (RW) : ORIGIN = 0x50100000, LENGTH = 0x00004000 -} - -/* Define output sections */ -SECTIONS -{ - /* NOINIT section for rpmsg_sh_mem */ - .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) - { - __RPMSG_SH_MEM_START__ = .; - *(.noinit.$rpmsg_sh_mem*) - . = ALIGN(4) ; - __RPMSG_SH_MEM_END__ = .; - } > rpmsg_sh_mem - - /* The startup code goes first into internal flash */ - .interrupts : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.ramfunc*) /* for functions in ram */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - m_usb_bdt (NOLOAD) : - { - . = ALIGN(512); - *(m_usb_bdt) - } > m_usb_sram - - m_usb_global (NOLOAD) : - { - *(m_usb_global) - } > m_usb_sram - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/startup_LPC55S69_cm33_core0.S b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/startup_LPC55S69_cm33_core0.S deleted file mode 100644 index 0992cb7655e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/startup_LPC55S69_cm33_core0.S +++ /dev/null @@ -1,884 +0,0 @@ -/* --------------------------------------------------------------------------*/ -/* @file: startup_LPC55S69_cm33_core0.s */ -/* @purpose: CMSIS Cortex-M33 Core Device Startup File */ -/* LPC55S69_cm33_core0 */ -/* @version: 1.1 */ -/* @date: 2019-5-16 */ -/* --------------------------------------------------------------------------*/ -/* */ -/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2021 NXP */ -/* All rights reserved. */ -/* */ -/* SPDX-License-Identifier: BSD-3-Clause */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - - - .syntax unified - .arch armv8-m.main - - .section .isr_vector, "a" - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long MemManage_Handler /* MPU Fault Handler*/ - .long BusFault_Handler /* Bus Fault Handler*/ - .long UsageFault_Handler /* Usage Fault Handler*/ - .long SecureFault_Handler /* Secure Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long DebugMon_Handler /* Debug Monitor Handler*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts */ - .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ - .long DMA0_IRQHandler /* DMA0 controller */ - .long GINT0_IRQHandler /* GPIO group 0 */ - .long GINT1_IRQHandler /* GPIO group 1 */ - .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - .long UTICK0_IRQHandler /* Micro-tick Timer */ - .long MRT0_IRQHandler /* Multi-rate timer */ - .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ - .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ - .long SCT0_IRQHandler /* SCTimer/PWM */ - .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ - .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long ADC0_IRQHandler /* ADC0 */ - .long Reserved39_IRQHandler /* Reserved interrupt */ - .long ACMP_IRQHandler /* ACMP interrupts */ - .long Reserved41_IRQHandler /* Reserved interrupt */ - .long Reserved42_IRQHandler /* Reserved interrupt */ - .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ - .long USB0_IRQHandler /* USB device */ - .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ - .long Reserved46_IRQHandler /* Reserved interrupt */ - .long MAILBOX_IRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */ - .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ - .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ - .long OS_EVENT_IRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ - .long Reserved55_IRQHandler /* Reserved interrupt */ - .long Reserved56_IRQHandler /* Reserved interrupt */ - .long Reserved57_IRQHandler /* Reserved interrupt */ - .long SDIO_IRQHandler /* SD/MMC */ - .long Reserved59_IRQHandler /* Reserved interrupt */ - .long Reserved60_IRQHandler /* Reserved interrupt */ - .long Reserved61_IRQHandler /* Reserved interrupt */ - .long USB1_PHY_IRQHandler /* USB1_PHY */ - .long USB1_IRQHandler /* USB1 interrupt */ - .long USB1_NEEDCLK_IRQHandler /* USB1 activity */ - .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ - .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ - .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ - .long PLU_IRQHandler /* PLU interrupt */ - .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ - .long HASHCRYPT_IRQHandler /* HASHCRYPT interrupt */ - .long CASER_IRQHandler /* CASPER interrupt */ - .long PUF_IRQHandler /* PUF interrupt */ - .long PQ_IRQHandler /* PQ interrupt */ - .long DMA1_IRQHandler /* DMA1 interrupt */ - .long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ - - .size __Vectors, . - __Vectors - - .text - .thumb - -/* Reset Handler */ - .thumb_func - .align 2 - .globl Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - cpsid i /* Mask interrupts */ - .equ VTOR, 0xE000ED08 - ldr r0, =VTOR - ldr r1, =__Vectors - str r1, [r0] - ldr r2, [r1] - msr msp, r2 - ldr R0, =__StackLimit - msr msplim, R0 -#ifndef __NO_SYSTEM_INIT - ldr r0,=SystemInit - blx r0 -#endif -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -#if 1 -/* Here are two copies of loop implemenations. First one favors code size - * and the second one favors performance. Default uses the first one. - * Change to "#if 0" to use the second one */ -.LC0: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .LC0 -#else - subs r3, r2 - ble .LC1 -.LC0: - subs r3, #4 - ldr r0, [r1, r3] - str r0, [r2, r3] - bgt .LC0 -.LC1: -#endif - -#ifdef __STARTUP_CLEAR_BSS -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * Loop to zero out BSS section, which uses following symbols - * in linker script: - * __bss_start__: start of BSS section. Must align to 4 - * __bss_end__: end of BSS section. Must align to 4 - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.LC2: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC2 -#endif /* __STARTUP_CLEAR_BSS */ - -/* Add stack / heap initializaiton */ - movs r0, 0 - ldr r1, =__HeapBase - ldr r2, =__HeapLimit -.LC3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC3 - - ldr r1, =__StackLimit - ldr r2, =__StackTop -.LC4: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC4 -/*End of stack / heap initializaiton */ - cpsie i /* Unmask interrupts */ - -#ifndef __START -#define __START _start -#endif -#ifndef __ATOLLIC__ - ldr r0,=__START - blx r0 -#else - ldr r0,=__libc_init_array - blx r0 - ldr r0,=main - bx r0 -#endif - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - - .align 1 - .thumb_func - .weak WDT_BOD_IRQHandler - .type WDT_BOD_IRQHandler, %function -WDT_BOD_IRQHandler: - ldr r0,=WDT_BOD_DriverIRQHandler - bx r0 - .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler - - .align 1 - .thumb_func - .weak DMA0_IRQHandler - .type DMA0_IRQHandler, %function -DMA0_IRQHandler: - ldr r0,=DMA0_DriverIRQHandler - bx r0 - .size DMA0_IRQHandler, . - DMA0_IRQHandler - - .align 1 - .thumb_func - .weak GINT0_IRQHandler - .type GINT0_IRQHandler, %function -GINT0_IRQHandler: - ldr r0,=GINT0_DriverIRQHandler - bx r0 - .size GINT0_IRQHandler, . - GINT0_IRQHandler - - .align 1 - .thumb_func - .weak GINT1_IRQHandler - .type GINT1_IRQHandler, %function -GINT1_IRQHandler: - ldr r0,=GINT1_DriverIRQHandler - bx r0 - .size GINT1_IRQHandler, . - GINT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT0_IRQHandler - .type PIN_INT0_IRQHandler, %function -PIN_INT0_IRQHandler: - ldr r0,=PIN_INT0_DriverIRQHandler - bx r0 - .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT1_IRQHandler - .type PIN_INT1_IRQHandler, %function -PIN_INT1_IRQHandler: - ldr r0,=PIN_INT1_DriverIRQHandler - bx r0 - .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT2_IRQHandler - .type PIN_INT2_IRQHandler, %function -PIN_INT2_IRQHandler: - ldr r0,=PIN_INT2_DriverIRQHandler - bx r0 - .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT3_IRQHandler - .type PIN_INT3_IRQHandler, %function -PIN_INT3_IRQHandler: - ldr r0,=PIN_INT3_DriverIRQHandler - bx r0 - .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler - - .align 1 - .thumb_func - .weak UTICK0_IRQHandler - .type UTICK0_IRQHandler, %function -UTICK0_IRQHandler: - ldr r0,=UTICK0_DriverIRQHandler - bx r0 - .size UTICK0_IRQHandler, . - UTICK0_IRQHandler - - .align 1 - .thumb_func - .weak MRT0_IRQHandler - .type MRT0_IRQHandler, %function -MRT0_IRQHandler: - ldr r0,=MRT0_DriverIRQHandler - bx r0 - .size MRT0_IRQHandler, . - MRT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER0_IRQHandler - .type CTIMER0_IRQHandler, %function -CTIMER0_IRQHandler: - ldr r0,=CTIMER0_DriverIRQHandler - bx r0 - .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER1_IRQHandler - .type CTIMER1_IRQHandler, %function -CTIMER1_IRQHandler: - ldr r0,=CTIMER1_DriverIRQHandler - bx r0 - .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler - - .align 1 - .thumb_func - .weak SCT0_IRQHandler - .type SCT0_IRQHandler, %function -SCT0_IRQHandler: - ldr r0,=SCT0_DriverIRQHandler - bx r0 - .size SCT0_IRQHandler, . - SCT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER3_IRQHandler - .type CTIMER3_IRQHandler, %function -CTIMER3_IRQHandler: - ldr r0,=CTIMER3_DriverIRQHandler - bx r0 - .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM0_IRQHandler - .type FLEXCOMM0_IRQHandler, %function -FLEXCOMM0_IRQHandler: - ldr r0,=FLEXCOMM0_DriverIRQHandler - bx r0 - .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM1_IRQHandler - .type FLEXCOMM1_IRQHandler, %function -FLEXCOMM1_IRQHandler: - ldr r0,=FLEXCOMM1_DriverIRQHandler - bx r0 - .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM2_IRQHandler - .type FLEXCOMM2_IRQHandler, %function -FLEXCOMM2_IRQHandler: - ldr r0,=FLEXCOMM2_DriverIRQHandler - bx r0 - .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM3_IRQHandler - .type FLEXCOMM3_IRQHandler, %function -FLEXCOMM3_IRQHandler: - ldr r0,=FLEXCOMM3_DriverIRQHandler - bx r0 - .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM4_IRQHandler - .type FLEXCOMM4_IRQHandler, %function -FLEXCOMM4_IRQHandler: - ldr r0,=FLEXCOMM4_DriverIRQHandler - bx r0 - .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM5_IRQHandler - .type FLEXCOMM5_IRQHandler, %function -FLEXCOMM5_IRQHandler: - ldr r0,=FLEXCOMM5_DriverIRQHandler - bx r0 - .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM6_IRQHandler - .type FLEXCOMM6_IRQHandler, %function -FLEXCOMM6_IRQHandler: - ldr r0,=FLEXCOMM6_DriverIRQHandler - bx r0 - .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM7_IRQHandler - .type FLEXCOMM7_IRQHandler, %function -FLEXCOMM7_IRQHandler: - ldr r0,=FLEXCOMM7_DriverIRQHandler - bx r0 - .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_IRQHandler - .type ADC0_IRQHandler, %function -ADC0_IRQHandler: - ldr r0,=ADC0_DriverIRQHandler - bx r0 - .size ADC0_IRQHandler, . - ADC0_IRQHandler - - .align 1 - .thumb_func - .weak Reserved39_IRQHandler - .type Reserved39_IRQHandler, %function -Reserved39_IRQHandler: - ldr r0,=Reserved39_DriverIRQHandler - bx r0 - .size Reserved39_IRQHandler, . - Reserved39_IRQHandler - - .align 1 - .thumb_func - .weak ACMP_IRQHandler - .type ACMP_IRQHandler, %function -ACMP_IRQHandler: - ldr r0,=ACMP_DriverIRQHandler - bx r0 - .size ACMP_IRQHandler, . - ACMP_IRQHandler - - .align 1 - .thumb_func - .weak Reserved41_IRQHandler - .type Reserved41_IRQHandler, %function -Reserved41_IRQHandler: - ldr r0,=Reserved41_DriverIRQHandler - bx r0 - .size Reserved41_IRQHandler, . - Reserved41_IRQHandler - - .align 1 - .thumb_func - .weak Reserved42_IRQHandler - .type Reserved42_IRQHandler, %function -Reserved42_IRQHandler: - ldr r0,=Reserved42_DriverIRQHandler - bx r0 - .size Reserved42_IRQHandler, . - Reserved42_IRQHandler - - .align 1 - .thumb_func - .weak USB0_NEEDCLK_IRQHandler - .type USB0_NEEDCLK_IRQHandler, %function -USB0_NEEDCLK_IRQHandler: - ldr r0,=USB0_NEEDCLK_DriverIRQHandler - bx r0 - .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak USB0_IRQHandler - .type USB0_IRQHandler, %function -USB0_IRQHandler: - ldr r0,=USB0_DriverIRQHandler - bx r0 - .size USB0_IRQHandler, . - USB0_IRQHandler - - .align 1 - .thumb_func - .weak RTC_IRQHandler - .type RTC_IRQHandler, %function -RTC_IRQHandler: - ldr r0,=RTC_DriverIRQHandler - bx r0 - .size RTC_IRQHandler, . - RTC_IRQHandler - - .align 1 - .thumb_func - .weak Reserved46_IRQHandler - .type Reserved46_IRQHandler, %function -Reserved46_IRQHandler: - ldr r0,=Reserved46_DriverIRQHandler - bx r0 - .size Reserved46_IRQHandler, . - Reserved46_IRQHandler - - .align 1 - .thumb_func - .weak MAILBOX_IRQHandler - .type MAILBOX_IRQHandler, %function -MAILBOX_IRQHandler: - ldr r0,=MAILBOX_DriverIRQHandler - bx r0 - .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT4_IRQHandler - .type PIN_INT4_IRQHandler, %function -PIN_INT4_IRQHandler: - ldr r0,=PIN_INT4_DriverIRQHandler - bx r0 - .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT5_IRQHandler - .type PIN_INT5_IRQHandler, %function -PIN_INT5_IRQHandler: - ldr r0,=PIN_INT5_DriverIRQHandler - bx r0 - .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT6_IRQHandler - .type PIN_INT6_IRQHandler, %function -PIN_INT6_IRQHandler: - ldr r0,=PIN_INT6_DriverIRQHandler - bx r0 - .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT7_IRQHandler - .type PIN_INT7_IRQHandler, %function -PIN_INT7_IRQHandler: - ldr r0,=PIN_INT7_DriverIRQHandler - bx r0 - .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER2_IRQHandler - .type CTIMER2_IRQHandler, %function -CTIMER2_IRQHandler: - ldr r0,=CTIMER2_DriverIRQHandler - bx r0 - .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER4_IRQHandler - .type CTIMER4_IRQHandler, %function -CTIMER4_IRQHandler: - ldr r0,=CTIMER4_DriverIRQHandler - bx r0 - .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler - - .align 1 - .thumb_func - .weak OS_EVENT_IRQHandler - .type OS_EVENT_IRQHandler, %function -OS_EVENT_IRQHandler: - ldr r0,=OS_EVENT_DriverIRQHandler - bx r0 - .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler - - .align 1 - .thumb_func - .weak Reserved55_IRQHandler - .type Reserved55_IRQHandler, %function -Reserved55_IRQHandler: - ldr r0,=Reserved55_DriverIRQHandler - bx r0 - .size Reserved55_IRQHandler, . - Reserved55_IRQHandler - - .align 1 - .thumb_func - .weak Reserved56_IRQHandler - .type Reserved56_IRQHandler, %function -Reserved56_IRQHandler: - ldr r0,=Reserved56_DriverIRQHandler - bx r0 - .size Reserved56_IRQHandler, . - Reserved56_IRQHandler - - .align 1 - .thumb_func - .weak Reserved57_IRQHandler - .type Reserved57_IRQHandler, %function -Reserved57_IRQHandler: - ldr r0,=Reserved57_DriverIRQHandler - bx r0 - .size Reserved57_IRQHandler, . - Reserved57_IRQHandler - - .align 1 - .thumb_func - .weak SDIO_IRQHandler - .type SDIO_IRQHandler, %function -SDIO_IRQHandler: - ldr r0,=SDIO_DriverIRQHandler - bx r0 - .size SDIO_IRQHandler, . - SDIO_IRQHandler - - .align 1 - .thumb_func - .weak Reserved59_IRQHandler - .type Reserved59_IRQHandler, %function -Reserved59_IRQHandler: - ldr r0,=Reserved59_DriverIRQHandler - bx r0 - .size Reserved59_IRQHandler, . - Reserved59_IRQHandler - - .align 1 - .thumb_func - .weak Reserved60_IRQHandler - .type Reserved60_IRQHandler, %function -Reserved60_IRQHandler: - ldr r0,=Reserved60_DriverIRQHandler - bx r0 - .size Reserved60_IRQHandler, . - Reserved60_IRQHandler - - .align 1 - .thumb_func - .weak Reserved61_IRQHandler - .type Reserved61_IRQHandler, %function -Reserved61_IRQHandler: - ldr r0,=Reserved61_DriverIRQHandler - bx r0 - .size Reserved61_IRQHandler, . - Reserved61_IRQHandler - - .align 1 - .thumb_func - .weak USB1_PHY_IRQHandler - .type USB1_PHY_IRQHandler, %function -USB1_PHY_IRQHandler: - ldr r0,=USB1_PHY_DriverIRQHandler - bx r0 - .size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler - - .align 1 - .thumb_func - .weak USB1_IRQHandler - .type USB1_IRQHandler, %function -USB1_IRQHandler: - ldr r0,=USB1_DriverIRQHandler - bx r0 - .size USB1_IRQHandler, . - USB1_IRQHandler - - .align 1 - .thumb_func - .weak USB1_NEEDCLK_IRQHandler - .type USB1_NEEDCLK_IRQHandler, %function -USB1_NEEDCLK_IRQHandler: - ldr r0,=USB1_NEEDCLK_DriverIRQHandler - bx r0 - .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak SEC_HYPERVISOR_CALL_IRQHandler - .type SEC_HYPERVISOR_CALL_IRQHandler, %function -SEC_HYPERVISOR_CALL_IRQHandler: - ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler - bx r0 - .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ0_IRQHandler - .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function -SEC_GPIO_INT0_IRQ0_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ1_IRQHandler - .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function -SEC_GPIO_INT0_IRQ1_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak PLU_IRQHandler - .type PLU_IRQHandler, %function -PLU_IRQHandler: - ldr r0,=PLU_DriverIRQHandler - bx r0 - .size PLU_IRQHandler, . - PLU_IRQHandler - - .align 1 - .thumb_func - .weak SEC_VIO_IRQHandler - .type SEC_VIO_IRQHandler, %function -SEC_VIO_IRQHandler: - ldr r0,=SEC_VIO_DriverIRQHandler - bx r0 - .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler - - .align 1 - .thumb_func - .weak HASHCRYPT_IRQHandler - .type HASHCRYPT_IRQHandler, %function -HASHCRYPT_IRQHandler: - ldr r0,=HASHCRYPT_DriverIRQHandler - bx r0 - .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler - - .align 1 - .thumb_func - .weak CASER_IRQHandler - .type CASER_IRQHandler, %function -CASER_IRQHandler: - ldr r0,=CASER_DriverIRQHandler - bx r0 - .size CASER_IRQHandler, . - CASER_IRQHandler - - .align 1 - .thumb_func - .weak PUF_IRQHandler - .type PUF_IRQHandler, %function -PUF_IRQHandler: - ldr r0,=PUF_DriverIRQHandler - bx r0 - .size PUF_IRQHandler, . - PUF_IRQHandler - - .align 1 - .thumb_func - .weak PQ_IRQHandler - .type PQ_IRQHandler, %function -PQ_IRQHandler: - ldr r0,=PQ_DriverIRQHandler - bx r0 - .size PQ_IRQHandler, . - PQ_IRQHandler - - .align 1 - .thumb_func - .weak DMA1_IRQHandler - .type DMA1_IRQHandler, %function -DMA1_IRQHandler: - ldr r0,=DMA1_DriverIRQHandler - bx r0 - .size DMA1_IRQHandler, . - DMA1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM8_IRQHandler - .type FLEXCOMM8_IRQHandler, %function -FLEXCOMM8_IRQHandler: - ldr r0,=FLEXCOMM8_DriverIRQHandler - bx r0 - .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm -/* Exception Handlers */ - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SecureFault_Handler - def_irq_handler DebugMon_Handler - def_irq_handler WDT_BOD_DriverIRQHandler - def_irq_handler DMA0_DriverIRQHandler - def_irq_handler GINT0_DriverIRQHandler - def_irq_handler GINT1_DriverIRQHandler - def_irq_handler PIN_INT0_DriverIRQHandler - def_irq_handler PIN_INT1_DriverIRQHandler - def_irq_handler PIN_INT2_DriverIRQHandler - def_irq_handler PIN_INT3_DriverIRQHandler - def_irq_handler UTICK0_DriverIRQHandler - def_irq_handler MRT0_DriverIRQHandler - def_irq_handler CTIMER0_DriverIRQHandler - def_irq_handler CTIMER1_DriverIRQHandler - def_irq_handler SCT0_DriverIRQHandler - def_irq_handler CTIMER3_DriverIRQHandler - def_irq_handler FLEXCOMM0_DriverIRQHandler - def_irq_handler FLEXCOMM1_DriverIRQHandler - def_irq_handler FLEXCOMM2_DriverIRQHandler - def_irq_handler FLEXCOMM3_DriverIRQHandler - def_irq_handler FLEXCOMM4_DriverIRQHandler - def_irq_handler FLEXCOMM5_DriverIRQHandler - def_irq_handler FLEXCOMM6_DriverIRQHandler - def_irq_handler FLEXCOMM7_DriverIRQHandler - def_irq_handler ADC0_DriverIRQHandler - def_irq_handler Reserved39_DriverIRQHandler - def_irq_handler ACMP_DriverIRQHandler - def_irq_handler Reserved41_DriverIRQHandler - def_irq_handler Reserved42_DriverIRQHandler - def_irq_handler USB0_NEEDCLK_DriverIRQHandler - def_irq_handler USB0_DriverIRQHandler - def_irq_handler RTC_DriverIRQHandler - def_irq_handler Reserved46_DriverIRQHandler - def_irq_handler MAILBOX_DriverIRQHandler - def_irq_handler PIN_INT4_DriverIRQHandler - def_irq_handler PIN_INT5_DriverIRQHandler - def_irq_handler PIN_INT6_DriverIRQHandler - def_irq_handler PIN_INT7_DriverIRQHandler - def_irq_handler CTIMER2_DriverIRQHandler - def_irq_handler CTIMER4_DriverIRQHandler - def_irq_handler OS_EVENT_DriverIRQHandler - def_irq_handler Reserved55_DriverIRQHandler - def_irq_handler Reserved56_DriverIRQHandler - def_irq_handler Reserved57_DriverIRQHandler - def_irq_handler SDIO_DriverIRQHandler - def_irq_handler Reserved59_DriverIRQHandler - def_irq_handler Reserved60_DriverIRQHandler - def_irq_handler Reserved61_DriverIRQHandler - def_irq_handler USB1_PHY_DriverIRQHandler - def_irq_handler USB1_DriverIRQHandler - def_irq_handler USB1_NEEDCLK_DriverIRQHandler - def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler - def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler - def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler - def_irq_handler PLU_DriverIRQHandler - def_irq_handler SEC_VIO_DriverIRQHandler - def_irq_handler HASHCRYPT_DriverIRQHandler - def_irq_handler CASER_DriverIRQHandler - def_irq_handler PUF_DriverIRQHandler - def_irq_handler PQ_DriverIRQHandler - def_irq_handler DMA1_DriverIRQHandler - def_irq_handler FLEXCOMM8_DriverIRQHandler - - .end diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/startup_LPC55S69_cm33_core1.S b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/startup_LPC55S69_cm33_core1.S deleted file mode 100644 index 375866a8d53..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/startup_LPC55S69_cm33_core1.S +++ /dev/null @@ -1,875 +0,0 @@ -/* --------------------------------------------------------------------------*/ -/* @file: startup_LPC55S69_cm33_core1.s */ -/* @purpose: CMSIS Cortex-M33 Core Device Startup File */ -/* LPC55S69_cm33_core1 */ -/* @version: 1.1 */ -/* @date: 2019-5-16 */ -/* --------------------------------------------------------------------------*/ -/* */ -/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2019 NXP */ -/* All rights reserved. */ -/* */ -/* SPDX-License-Identifier: BSD-3-Clause */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - - - .syntax unified - .arch armv8-m.main - - .section .isr_vector, "a" - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long MemManage_Handler /* MPU Fault Handler*/ - .long BusFault_Handler /* Bus Fault Handler*/ - .long UsageFault_Handler /* Usage Fault Handler*/ - .long SecureFault_Handler /* Secure Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long DebugMon_Handler /* Debug Monitor Handler*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts */ - .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ - .long DMA0_IRQHandler /* DMA0 controller */ - .long GINT0_IRQHandler /* GPIO group 0 */ - .long GINT1_IRQHandler /* GPIO group 1 */ - .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - .long UTICK0_IRQHandler /* Micro-tick Timer */ - .long MRT0_IRQHandler /* Multi-rate timer */ - .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ - .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ - .long SCT0_IRQHandler /* SCTimer/PWM */ - .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ - .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long ADC0_IRQHandler /* ADC0 */ - .long Reserved39_IRQHandler /* Reserved interrupt */ - .long ACMP_IRQHandler /* ACMP interrupts */ - .long Reserved41_IRQHandler /* Reserved interrupt */ - .long Reserved42_IRQHandler /* Reserved interrupt */ - .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ - .long USB0_IRQHandler /* USB device */ - .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ - .long Reserved46_IRQHandler /* Reserved interrupt */ - .long MAILBOX_IRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */ - .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ - .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ - .long OS_EVENT_IRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ - .long Reserved55_IRQHandler /* Reserved interrupt */ - .long Reserved56_IRQHandler /* Reserved interrupt */ - .long Reserved57_IRQHandler /* Reserved interrupt */ - .long SDIO_IRQHandler /* SD/MMC */ - .long Reserved59_IRQHandler /* Reserved interrupt */ - .long Reserved60_IRQHandler /* Reserved interrupt */ - .long Reserved61_IRQHandler /* Reserved interrupt */ - .long USB1_PHY_IRQHandler /* USB1_PHY */ - .long USB1_IRQHandler /* USB1 interrupt */ - .long USB1_NEEDCLK_IRQHandler /* USB1 activity */ - .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ - .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ - .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ - .long PLU_IRQHandler /* PLU interrupt */ - .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ - .long HASHCRYPT_IRQHandler /* HASHCRYPT interrupt */ - .long CASER_IRQHandler /* CASPER interrupt */ - .long PUF_IRQHandler /* PUF interrupt */ - .long PQ_IRQHandler /* PQ interrupt */ - .long DMA1_IRQHandler /* DMA1 interrupt */ - .long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ - - .size __Vectors, . - __Vectors - - .text - .thumb - -/* Reset Handler */ - .thumb_func - .align 2 - .globl Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -#ifndef __NO_SYSTEM_INIT - ldr r0,=SystemInit - blx r0 -#endif -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -#if 1 -/* Here are two copies of loop implemenations. First one favors code size - * and the second one favors performance. Default uses the first one. - * Change to "#if 0" to use the second one */ -.LC0: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .LC0 -#else - subs r3, r2 - ble .LC1 -.LC0: - subs r3, #4 - ldr r0, [r1, r3] - str r0, [r2, r3] - bgt .LC0 -.LC1: -#endif - -#ifdef __STARTUP_CLEAR_BSS -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * Loop to zero out BSS section, which uses following symbols - * in linker script: - * __bss_start__: start of BSS section. Must align to 4 - * __bss_end__: end of BSS section. Must align to 4 - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.LC2: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC2 -#endif /* __STARTUP_CLEAR_BSS */ - -/* Add stack / heap initializaiton */ - movs r0, 0 - ldr r1, =__HeapBase - ldr r2, =__HeapLimit -.LC3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC3 - - ldr r1, =__StackLimit - ldr r2, =__StackTop -.LC4: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC4 -/*End of stack / heap initializaiton */ - cpsie i /* Unmask interrupts */ - -#ifndef __START -#define __START _start -#endif -#ifndef __ATOLLIC__ - ldr r0,=__START - blx r0 -#else - ldr r0,=__libc_init_array - blx r0 - ldr r0,=main - bx r0 -#endif - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - - .align 1 - .thumb_func - .weak WDT_BOD_IRQHandler - .type WDT_BOD_IRQHandler, %function -WDT_BOD_IRQHandler: - ldr r0,=WDT_BOD_DriverIRQHandler - bx r0 - .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler - - .align 1 - .thumb_func - .weak DMA0_IRQHandler - .type DMA0_IRQHandler, %function -DMA0_IRQHandler: - ldr r0,=DMA0_DriverIRQHandler - bx r0 - .size DMA0_IRQHandler, . - DMA0_IRQHandler - - .align 1 - .thumb_func - .weak GINT0_IRQHandler - .type GINT0_IRQHandler, %function -GINT0_IRQHandler: - ldr r0,=GINT0_DriverIRQHandler - bx r0 - .size GINT0_IRQHandler, . - GINT0_IRQHandler - - .align 1 - .thumb_func - .weak GINT1_IRQHandler - .type GINT1_IRQHandler, %function -GINT1_IRQHandler: - ldr r0,=GINT1_DriverIRQHandler - bx r0 - .size GINT1_IRQHandler, . - GINT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT0_IRQHandler - .type PIN_INT0_IRQHandler, %function -PIN_INT0_IRQHandler: - ldr r0,=PIN_INT0_DriverIRQHandler - bx r0 - .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT1_IRQHandler - .type PIN_INT1_IRQHandler, %function -PIN_INT1_IRQHandler: - ldr r0,=PIN_INT1_DriverIRQHandler - bx r0 - .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT2_IRQHandler - .type PIN_INT2_IRQHandler, %function -PIN_INT2_IRQHandler: - ldr r0,=PIN_INT2_DriverIRQHandler - bx r0 - .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT3_IRQHandler - .type PIN_INT3_IRQHandler, %function -PIN_INT3_IRQHandler: - ldr r0,=PIN_INT3_DriverIRQHandler - bx r0 - .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler - - .align 1 - .thumb_func - .weak UTICK0_IRQHandler - .type UTICK0_IRQHandler, %function -UTICK0_IRQHandler: - ldr r0,=UTICK0_DriverIRQHandler - bx r0 - .size UTICK0_IRQHandler, . - UTICK0_IRQHandler - - .align 1 - .thumb_func - .weak MRT0_IRQHandler - .type MRT0_IRQHandler, %function -MRT0_IRQHandler: - ldr r0,=MRT0_DriverIRQHandler - bx r0 - .size MRT0_IRQHandler, . - MRT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER0_IRQHandler - .type CTIMER0_IRQHandler, %function -CTIMER0_IRQHandler: - ldr r0,=CTIMER0_DriverIRQHandler - bx r0 - .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER1_IRQHandler - .type CTIMER1_IRQHandler, %function -CTIMER1_IRQHandler: - ldr r0,=CTIMER1_DriverIRQHandler - bx r0 - .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler - - .align 1 - .thumb_func - .weak SCT0_IRQHandler - .type SCT0_IRQHandler, %function -SCT0_IRQHandler: - ldr r0,=SCT0_DriverIRQHandler - bx r0 - .size SCT0_IRQHandler, . - SCT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER3_IRQHandler - .type CTIMER3_IRQHandler, %function -CTIMER3_IRQHandler: - ldr r0,=CTIMER3_DriverIRQHandler - bx r0 - .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM0_IRQHandler - .type FLEXCOMM0_IRQHandler, %function -FLEXCOMM0_IRQHandler: - ldr r0,=FLEXCOMM0_DriverIRQHandler - bx r0 - .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM1_IRQHandler - .type FLEXCOMM1_IRQHandler, %function -FLEXCOMM1_IRQHandler: - ldr r0,=FLEXCOMM1_DriverIRQHandler - bx r0 - .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM2_IRQHandler - .type FLEXCOMM2_IRQHandler, %function -FLEXCOMM2_IRQHandler: - ldr r0,=FLEXCOMM2_DriverIRQHandler - bx r0 - .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM3_IRQHandler - .type FLEXCOMM3_IRQHandler, %function -FLEXCOMM3_IRQHandler: - ldr r0,=FLEXCOMM3_DriverIRQHandler - bx r0 - .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM4_IRQHandler - .type FLEXCOMM4_IRQHandler, %function -FLEXCOMM4_IRQHandler: - ldr r0,=FLEXCOMM4_DriverIRQHandler - bx r0 - .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM5_IRQHandler - .type FLEXCOMM5_IRQHandler, %function -FLEXCOMM5_IRQHandler: - ldr r0,=FLEXCOMM5_DriverIRQHandler - bx r0 - .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM6_IRQHandler - .type FLEXCOMM6_IRQHandler, %function -FLEXCOMM6_IRQHandler: - ldr r0,=FLEXCOMM6_DriverIRQHandler - bx r0 - .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM7_IRQHandler - .type FLEXCOMM7_IRQHandler, %function -FLEXCOMM7_IRQHandler: - ldr r0,=FLEXCOMM7_DriverIRQHandler - bx r0 - .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_IRQHandler - .type ADC0_IRQHandler, %function -ADC0_IRQHandler: - ldr r0,=ADC0_DriverIRQHandler - bx r0 - .size ADC0_IRQHandler, . - ADC0_IRQHandler - - .align 1 - .thumb_func - .weak Reserved39_IRQHandler - .type Reserved39_IRQHandler, %function -Reserved39_IRQHandler: - ldr r0,=Reserved39_DriverIRQHandler - bx r0 - .size Reserved39_IRQHandler, . - Reserved39_IRQHandler - - .align 1 - .thumb_func - .weak ACMP_IRQHandler - .type ACMP_IRQHandler, %function -ACMP_IRQHandler: - ldr r0,=ACMP_DriverIRQHandler - bx r0 - .size ACMP_IRQHandler, . - ACMP_IRQHandler - - .align 1 - .thumb_func - .weak Reserved41_IRQHandler - .type Reserved41_IRQHandler, %function -Reserved41_IRQHandler: - ldr r0,=Reserved41_DriverIRQHandler - bx r0 - .size Reserved41_IRQHandler, . - Reserved41_IRQHandler - - .align 1 - .thumb_func - .weak Reserved42_IRQHandler - .type Reserved42_IRQHandler, %function -Reserved42_IRQHandler: - ldr r0,=Reserved42_DriverIRQHandler - bx r0 - .size Reserved42_IRQHandler, . - Reserved42_IRQHandler - - .align 1 - .thumb_func - .weak USB0_NEEDCLK_IRQHandler - .type USB0_NEEDCLK_IRQHandler, %function -USB0_NEEDCLK_IRQHandler: - ldr r0,=USB0_NEEDCLK_DriverIRQHandler - bx r0 - .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak USB0_IRQHandler - .type USB0_IRQHandler, %function -USB0_IRQHandler: - ldr r0,=USB0_DriverIRQHandler - bx r0 - .size USB0_IRQHandler, . - USB0_IRQHandler - - .align 1 - .thumb_func - .weak RTC_IRQHandler - .type RTC_IRQHandler, %function -RTC_IRQHandler: - ldr r0,=RTC_DriverIRQHandler - bx r0 - .size RTC_IRQHandler, . - RTC_IRQHandler - - .align 1 - .thumb_func - .weak Reserved46_IRQHandler - .type Reserved46_IRQHandler, %function -Reserved46_IRQHandler: - ldr r0,=Reserved46_DriverIRQHandler - bx r0 - .size Reserved46_IRQHandler, . - Reserved46_IRQHandler - - .align 1 - .thumb_func - .weak MAILBOX_IRQHandler - .type MAILBOX_IRQHandler, %function -MAILBOX_IRQHandler: - ldr r0,=MAILBOX_DriverIRQHandler - bx r0 - .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT4_IRQHandler - .type PIN_INT4_IRQHandler, %function -PIN_INT4_IRQHandler: - ldr r0,=PIN_INT4_DriverIRQHandler - bx r0 - .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT5_IRQHandler - .type PIN_INT5_IRQHandler, %function -PIN_INT5_IRQHandler: - ldr r0,=PIN_INT5_DriverIRQHandler - bx r0 - .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT6_IRQHandler - .type PIN_INT6_IRQHandler, %function -PIN_INT6_IRQHandler: - ldr r0,=PIN_INT6_DriverIRQHandler - bx r0 - .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT7_IRQHandler - .type PIN_INT7_IRQHandler, %function -PIN_INT7_IRQHandler: - ldr r0,=PIN_INT7_DriverIRQHandler - bx r0 - .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER2_IRQHandler - .type CTIMER2_IRQHandler, %function -CTIMER2_IRQHandler: - ldr r0,=CTIMER2_DriverIRQHandler - bx r0 - .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER4_IRQHandler - .type CTIMER4_IRQHandler, %function -CTIMER4_IRQHandler: - ldr r0,=CTIMER4_DriverIRQHandler - bx r0 - .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler - - .align 1 - .thumb_func - .weak OS_EVENT_IRQHandler - .type OS_EVENT_IRQHandler, %function -OS_EVENT_IRQHandler: - ldr r0,=OS_EVENT_DriverIRQHandler - bx r0 - .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler - - .align 1 - .thumb_func - .weak Reserved55_IRQHandler - .type Reserved55_IRQHandler, %function -Reserved55_IRQHandler: - ldr r0,=Reserved55_DriverIRQHandler - bx r0 - .size Reserved55_IRQHandler, . - Reserved55_IRQHandler - - .align 1 - .thumb_func - .weak Reserved56_IRQHandler - .type Reserved56_IRQHandler, %function -Reserved56_IRQHandler: - ldr r0,=Reserved56_DriverIRQHandler - bx r0 - .size Reserved56_IRQHandler, . - Reserved56_IRQHandler - - .align 1 - .thumb_func - .weak Reserved57_IRQHandler - .type Reserved57_IRQHandler, %function -Reserved57_IRQHandler: - ldr r0,=Reserved57_DriverIRQHandler - bx r0 - .size Reserved57_IRQHandler, . - Reserved57_IRQHandler - - .align 1 - .thumb_func - .weak SDIO_IRQHandler - .type SDIO_IRQHandler, %function -SDIO_IRQHandler: - ldr r0,=SDIO_DriverIRQHandler - bx r0 - .size SDIO_IRQHandler, . - SDIO_IRQHandler - - .align 1 - .thumb_func - .weak Reserved59_IRQHandler - .type Reserved59_IRQHandler, %function -Reserved59_IRQHandler: - ldr r0,=Reserved59_DriverIRQHandler - bx r0 - .size Reserved59_IRQHandler, . - Reserved59_IRQHandler - - .align 1 - .thumb_func - .weak Reserved60_IRQHandler - .type Reserved60_IRQHandler, %function -Reserved60_IRQHandler: - ldr r0,=Reserved60_DriverIRQHandler - bx r0 - .size Reserved60_IRQHandler, . - Reserved60_IRQHandler - - .align 1 - .thumb_func - .weak Reserved61_IRQHandler - .type Reserved61_IRQHandler, %function -Reserved61_IRQHandler: - ldr r0,=Reserved61_DriverIRQHandler - bx r0 - .size Reserved61_IRQHandler, . - Reserved61_IRQHandler - - .align 1 - .thumb_func - .weak USB1_PHY_IRQHandler - .type USB1_PHY_IRQHandler, %function -USB1_PHY_IRQHandler: - ldr r0,=USB1_PHY_DriverIRQHandler - bx r0 - .size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler - - .align 1 - .thumb_func - .weak USB1_IRQHandler - .type USB1_IRQHandler, %function -USB1_IRQHandler: - ldr r0,=USB1_DriverIRQHandler - bx r0 - .size USB1_IRQHandler, . - USB1_IRQHandler - - .align 1 - .thumb_func - .weak USB1_NEEDCLK_IRQHandler - .type USB1_NEEDCLK_IRQHandler, %function -USB1_NEEDCLK_IRQHandler: - ldr r0,=USB1_NEEDCLK_DriverIRQHandler - bx r0 - .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak SEC_HYPERVISOR_CALL_IRQHandler - .type SEC_HYPERVISOR_CALL_IRQHandler, %function -SEC_HYPERVISOR_CALL_IRQHandler: - ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler - bx r0 - .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ0_IRQHandler - .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function -SEC_GPIO_INT0_IRQ0_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ1_IRQHandler - .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function -SEC_GPIO_INT0_IRQ1_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak PLU_IRQHandler - .type PLU_IRQHandler, %function -PLU_IRQHandler: - ldr r0,=PLU_DriverIRQHandler - bx r0 - .size PLU_IRQHandler, . - PLU_IRQHandler - - .align 1 - .thumb_func - .weak SEC_VIO_IRQHandler - .type SEC_VIO_IRQHandler, %function -SEC_VIO_IRQHandler: - ldr r0,=SEC_VIO_DriverIRQHandler - bx r0 - .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler - - .align 1 - .thumb_func - .weak HASHCRYPT_IRQHandler - .type HASHCRYPT_IRQHandler, %function -HASHCRYPT_IRQHandler: - ldr r0,=HASHCRYPT_DriverIRQHandler - bx r0 - .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler - - .align 1 - .thumb_func - .weak CASER_IRQHandler - .type CASER_IRQHandler, %function -CASER_IRQHandler: - ldr r0,=CASER_DriverIRQHandler - bx r0 - .size CASER_IRQHandler, . - CASER_IRQHandler - - .align 1 - .thumb_func - .weak PUF_IRQHandler - .type PUF_IRQHandler, %function -PUF_IRQHandler: - ldr r0,=PUF_DriverIRQHandler - bx r0 - .size PUF_IRQHandler, . - PUF_IRQHandler - - .align 1 - .thumb_func - .weak PQ_IRQHandler - .type PQ_IRQHandler, %function -PQ_IRQHandler: - ldr r0,=PQ_DriverIRQHandler - bx r0 - .size PQ_IRQHandler, . - PQ_IRQHandler - - .align 1 - .thumb_func - .weak DMA1_IRQHandler - .type DMA1_IRQHandler, %function -DMA1_IRQHandler: - ldr r0,=DMA1_DriverIRQHandler - bx r0 - .size DMA1_IRQHandler, . - DMA1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM8_IRQHandler - .type FLEXCOMM8_IRQHandler, %function -FLEXCOMM8_IRQHandler: - ldr r0,=FLEXCOMM8_DriverIRQHandler - bx r0 - .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm -/* Exception Handlers */ - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SecureFault_Handler - def_irq_handler DebugMon_Handler - def_irq_handler WDT_BOD_DriverIRQHandler - def_irq_handler DMA0_DriverIRQHandler - def_irq_handler GINT0_DriverIRQHandler - def_irq_handler GINT1_DriverIRQHandler - def_irq_handler PIN_INT0_DriverIRQHandler - def_irq_handler PIN_INT1_DriverIRQHandler - def_irq_handler PIN_INT2_DriverIRQHandler - def_irq_handler PIN_INT3_DriverIRQHandler - def_irq_handler UTICK0_DriverIRQHandler - def_irq_handler MRT0_DriverIRQHandler - def_irq_handler CTIMER0_DriverIRQHandler - def_irq_handler CTIMER1_DriverIRQHandler - def_irq_handler SCT0_DriverIRQHandler - def_irq_handler CTIMER3_DriverIRQHandler - def_irq_handler FLEXCOMM0_DriverIRQHandler - def_irq_handler FLEXCOMM1_DriverIRQHandler - def_irq_handler FLEXCOMM2_DriverIRQHandler - def_irq_handler FLEXCOMM3_DriverIRQHandler - def_irq_handler FLEXCOMM4_DriverIRQHandler - def_irq_handler FLEXCOMM5_DriverIRQHandler - def_irq_handler FLEXCOMM6_DriverIRQHandler - def_irq_handler FLEXCOMM7_DriverIRQHandler - def_irq_handler ADC0_DriverIRQHandler - def_irq_handler Reserved39_DriverIRQHandler - def_irq_handler ACMP_DriverIRQHandler - def_irq_handler Reserved41_DriverIRQHandler - def_irq_handler Reserved42_DriverIRQHandler - def_irq_handler USB0_NEEDCLK_DriverIRQHandler - def_irq_handler USB0_DriverIRQHandler - def_irq_handler RTC_DriverIRQHandler - def_irq_handler Reserved46_DriverIRQHandler - def_irq_handler MAILBOX_DriverIRQHandler - def_irq_handler PIN_INT4_DriverIRQHandler - def_irq_handler PIN_INT5_DriverIRQHandler - def_irq_handler PIN_INT6_DriverIRQHandler - def_irq_handler PIN_INT7_DriverIRQHandler - def_irq_handler CTIMER2_DriverIRQHandler - def_irq_handler CTIMER4_DriverIRQHandler - def_irq_handler OS_EVENT_DriverIRQHandler - def_irq_handler Reserved55_DriverIRQHandler - def_irq_handler Reserved56_DriverIRQHandler - def_irq_handler Reserved57_DriverIRQHandler - def_irq_handler SDIO_DriverIRQHandler - def_irq_handler Reserved59_DriverIRQHandler - def_irq_handler Reserved60_DriverIRQHandler - def_irq_handler Reserved61_DriverIRQHandler - def_irq_handler USB1_PHY_DriverIRQHandler - def_irq_handler USB1_DriverIRQHandler - def_irq_handler USB1_NEEDCLK_DriverIRQHandler - def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler - def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler - def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler - def_irq_handler PLU_DriverIRQHandler - def_irq_handler SEC_VIO_DriverIRQHandler - def_irq_handler HASHCRYPT_DriverIRQHandler - def_irq_handler CASER_DriverIRQHandler - def_irq_handler PUF_DriverIRQHandler - def_irq_handler PQ_DriverIRQHandler - def_irq_handler DMA1_DriverIRQHandler - def_irq_handler FLEXCOMM8_DriverIRQHandler - - .end diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash.icf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash.icf deleted file mode 100644 index f2d43da3824..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash.icf +++ /dev/null @@ -1,112 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JBD64_cm33_core0 -** LPC55S69JEV98_cm33_core0 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b210928 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -define symbol usb_bdt_size = 0x0; -/* Stack and Heap Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define symbol m_interrupts_start = 0x00000000; -define symbol m_interrupts_end = 0x000001FF; - -define symbol m_text_start = 0x00000200; -define symbol m_text_end = 0x00071FFF; - -define exported symbol core1_image_start = 0x00072000; -define exported symbol core1_image_end = 0x0009D7FF; - -if (isdefinedsymbol(__use_shmem__)) { - define symbol m_data_start = 0x20000000; - define symbol m_data_end = 0x200317FF; - define exported symbol rpmsg_sh_mem_start = 0x20031800; - define exported symbol rpmsg_sh_mem_end = 0x20032FFF; -} else { - define symbol m_data_start = 0x20000000; - define symbol m_data_end = 0x20032FFF; -} - -define symbol m_usb_sram_start = 0x40100000; -define symbol m_usb_sram_end = 0x40103FFF; - -define memory mem with size = 4G; - -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -if (isdefinedsymbol(__use_shmem__)) { - define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; -} - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - -define region core1_region = mem:[from core1_image_start to core1_image_end]; -define block CORE1_IMAGE_WBLOCK { section __core1_image }; - -/* regions for USB */ -define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; -define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; -place in USB_BDT_region { section m_usb_bdt }; -place in USB_SRAM_region { section m_usb_global }; - -initialize by copy { readwrite, section .textrw }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - /* Required in a multi-threaded application */ - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; -if (isdefinedsymbol(__use_shmem__)) { - do not initialize { section rpmsg_sh_mem_section }; -} - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; -if (isdefinedsymbol(__use_shmem__)) { - place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; -} -place in core1_region { block CORE1_IMAGE_WBLOCK }; - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_ns.icf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_ns.icf deleted file mode 100644 index 0d7697ebf9b..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_ns.icf +++ /dev/null @@ -1,112 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JBD64_cm33_core0 -** LPC55S69JEV98_cm33_core0 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b190926 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -define symbol usb_bdt_size = 0x0; -/* Stack and Heap Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define symbol m_interrupts_start = 0x00010000; -define symbol m_interrupts_end = 0x000101FF; - -define symbol m_text_start = 0x00010200; -define symbol m_text_end = 0x00071FFF; - -define exported symbol core1_image_start = 0x00072000; -define exported symbol core1_image_end = 0x0009D7FF; - -if (isdefinedsymbol(__use_shmem__)) { - define symbol m_data_start = 0x20008000; - define symbol m_data_end = 0x20030FFF; - define exported symbol rpmsg_sh_mem_start = 0x20031800; - define exported symbol rpmsg_sh_mem_end = 0x20032FFF; -} else { - define symbol m_data_start = 0x20008000; - define symbol m_data_end = 0x20032FFF; -} - -define symbol m_usb_sram_start = 0x40100000; -define symbol m_usb_sram_end = 0x40103FFF; - -define memory mem with size = 4G; - -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -if (isdefinedsymbol(__use_shmem__)) { - define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; -} - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - -define region core1_region = mem:[from core1_image_start to core1_image_end]; -define block CORE1_IMAGE_WBLOCK { section __core1_image }; - -/* regions for USB */ -define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; -define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; -place in USB_BDT_region { section m_usb_bdt }; -place in USB_SRAM_region { section m_usb_global }; - -initialize by copy { readwrite, section .textrw }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - /* Required in a multi-threaded application */ - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; -if (isdefinedsymbol(__use_shmem__)) { - do not initialize { section rpmsg_sh_mem_section }; -} - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; -if (isdefinedsymbol(__use_shmem__)) { - place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; -} -place in core1_region { block CORE1_IMAGE_WBLOCK }; - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_s.icf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_s.icf deleted file mode 100644 index 5d07ddcf8c6..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_s.icf +++ /dev/null @@ -1,122 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JBD64_cm33_core0 -** LPC55S69JEV98_cm33_core0 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b190926 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -define symbol usb_bdt_size = 0x0; -/* Stack and Heap Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -/* Only the first 64kB of flash is used as secure memory. */ -define symbol m_interrupts_start = 0x10000000; -define symbol m_interrupts_end = 0x100001FF; - -define symbol m_text_start = 0x10000200; -define symbol m_text_end = 0x1000FDFF; - -define exported symbol core1_image_start = 0x10072000; -define exported symbol core1_image_end = 0x1009D7FF; - -/* Only first 32kB of data RAM is used as secure memory. */ -if (isdefinedsymbol(__use_shmem__)) { - define symbol m_data_start = 0x30000000; - define symbol m_data_end = 0x30007FFF; - define exported symbol rpmsg_sh_mem_start = 0x30031800; - define exported symbol rpmsg_sh_mem_end = 0x30032FFF; -} else { - define symbol m_data_start = 0x30000000; - define symbol m_data_end = 0x30007FFF; -} - -/* 512B - memory for veneer table (NSC - secure, non-secure callable memory) */ -define symbol m_veneer_table_start = 0x1000FE00; -define symbol m_veneer_table_size = 0x200; - -define symbol m_usb_sram_start = 0x50100000; -define symbol m_usb_sram_end = 0x50103FFF; - -define memory mem with size = 4G; - -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -if (isdefinedsymbol(__use_shmem__)) { - define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; -} - -define region VENEER_TABLE_region = mem:[from m_veneer_table_start to m_veneer_table_start + m_veneer_table_size - 1]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - -define region core1_region = mem:[from core1_image_start to core1_image_end]; -define block CORE1_IMAGE_WBLOCK { section __core1_image }; - -/* regions for USB */ -define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; -define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; -place in USB_BDT_region { section m_usb_bdt }; -place in USB_SRAM_region { section m_usb_global }; - -initialize by copy { readwrite, section .textrw }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - /* Required in a multi-threaded application */ - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; -if (isdefinedsymbol(__use_shmem__)) { - do not initialize { section rpmsg_sh_mem_section }; -} - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; -place in VENEER_TABLE_region { section Veneer$$CMSE }; - -if (isdefinedsymbol(__use_shmem__)) { - place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; -} -place in core1_region { block CORE1_IMAGE_WBLOCK }; - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_ram.icf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_ram.icf deleted file mode 100644 index 59e107cb9d4..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_ram.icf +++ /dev/null @@ -1,112 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JBD64_cm33_core0 -** LPC55S69JEV98_cm33_core0 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b200722 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2020 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -define symbol usb_bdt_size = 0x0; -/* Stack and Heap Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define symbol m_interrupts_start = 0x04000000; -define symbol m_interrupts_end = 0x040001FF; - -define symbol m_text_start = 0x04000200; -define symbol m_text_end = 0x04007FFF; - -define exported symbol core1_image_start = 0x20033000; -define exported symbol core1_image_end = 0x2003F7FF; - -if (isdefinedsymbol(__use_shmem__)) { - define symbol m_data_start = 0x20000000; - define symbol m_data_end = 0x200317FF; - define exported symbol rpmsg_sh_mem_start = 0x20031800; - define exported symbol rpmsg_sh_mem_end = 0x20032FFF; -} else { - define symbol m_data_start = 0x20000000; - define symbol m_data_end = 0x20032FFF; -} - -define symbol m_usb_sram_start = 0x40100000; -define symbol m_usb_sram_end = 0x40103FFF; - -define memory mem with size = 4G; - -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -if (isdefinedsymbol(__use_shmem__)) { - define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; -} - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - -define region core1_region = mem:[from core1_image_start to core1_image_end]; -define block CORE1_IMAGE_WBLOCK { section __core1_image }; - -/* regions for USB */ -define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; -define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; -place in USB_BDT_region { section m_usb_bdt }; -place in USB_SRAM_region { section m_usb_global }; - -initialize by copy { readwrite, section .textrw }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - /* Required in a multi-threaded application */ - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; -if (isdefinedsymbol(__use_shmem__)) { - do not initialize { section rpmsg_sh_mem_section }; -} - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; -if (isdefinedsymbol(__use_shmem__)) { - place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; -} -place in core1_region { block CORE1_IMAGE_WBLOCK }; - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_flash.icf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_flash.icf deleted file mode 100644 index fa8b4bdf7cf..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_flash.icf +++ /dev/null @@ -1,105 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JBD64_cm33_core1 -** LPC55S69JEV98_cm33_core1 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b210928 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -define symbol usb_bdt_size = 0x0; -/* Stack and Heap Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define symbol m_interrupts_start = 0x00072000; -define symbol m_interrupts_end = 0x000721FF; - -define symbol m_text_start = 0x00072200; -define symbol m_text_end = 0x0009D7FF; - - -define symbol m_data_start = 0x20033000; -define symbol m_data_end = 0x20043FFF; - -if (isdefinedsymbol(__use_shmem__)) { - define exported symbol rpmsg_sh_mem_start = 0x20031800; - define exported symbol rpmsg_sh_mem_end = 0x20032FFF; -} - -define symbol m_usb_sram_start = 0x40100000; -define symbol m_usb_sram_end = 0x40103FFF; - -define memory mem with size = 4G; - -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -if (isdefinedsymbol(__use_shmem__)) { - define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; -} - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - - -/* regions for USB */ -define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; -define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; -place in USB_BDT_region { section m_usb_bdt }; -place in USB_SRAM_region { section m_usb_global }; - -initialize by copy { readwrite, section .textrw }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - /* Required in a multi-threaded application */ - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; -if (isdefinedsymbol(__use_shmem__)) { - do not initialize { section rpmsg_sh_mem_section }; -} - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; -if (isdefinedsymbol(__use_shmem__)) { - place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; -} - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_ram.icf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_ram.icf deleted file mode 100644 index 72b086d479f..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_ram.icf +++ /dev/null @@ -1,105 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JBD64_cm33_core1 -** LPC55S69JEV98_cm33_core1 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b200722 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2020 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -define symbol usb_bdt_size = 0x0; -/* Stack and Heap Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define symbol m_interrupts_start = 0x20033000; -define symbol m_interrupts_end = 0x200331FF; - -define symbol m_text_start = 0x20033200; -define symbol m_text_end = 0x2003F7FF; - - -define symbol m_data_start = 0x2003F800; -define symbol m_data_end = 0x20043FFF; - -if (isdefinedsymbol(__use_shmem__)) { - define exported symbol rpmsg_sh_mem_start = 0x20031800; - define exported symbol rpmsg_sh_mem_end = 0x20032FFF; -} - -define symbol m_usb_sram_start = 0x40100000; -define symbol m_usb_sram_end = 0x40103FFF; - -define memory mem with size = 4G; - -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -if (isdefinedsymbol(__use_shmem__)) { - define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; -} - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - - -/* regions for USB */ -define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; -define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; -place in USB_BDT_region { section m_usb_bdt }; -place in USB_SRAM_region { section m_usb_global }; - -initialize by copy { readwrite, section .textrw }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - /* Required in a multi-threaded application */ - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; -if (isdefinedsymbol(__use_shmem__)) { - do not initialize { section rpmsg_sh_mem_section }; -} - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; -if (isdefinedsymbol(__use_shmem__)) { - place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; -} - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_ram_s.icf b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_ram_s.icf deleted file mode 100644 index 13d49a18da0..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_ram_s.icf +++ /dev/null @@ -1,105 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JBD64_cm33_core1 -** LPC55S69JEV98_cm33_core1 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b190926 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* USB BDT size */ -define symbol usb_bdt_size = 0x0; -/* Stack and Heap Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define symbol m_interrupts_start = 0x30033000; -define symbol m_interrupts_end = 0x300331FF; - -define symbol m_text_start = 0x30033200; -define symbol m_text_end = 0x3003F7FF; - - -define symbol m_data_start = 0x3003F800; -define symbol m_data_end = 0x30043FFF; - -if (isdefinedsymbol(__use_shmem__)) { - define exported symbol rpmsg_sh_mem_start = 0x30031800; - define exported symbol rpmsg_sh_mem_end = 0x30032FFF; -} - -define symbol m_usb_sram_start = 0x50100000; -define symbol m_usb_sram_end = 0x50103FFF; - -define memory mem with size = 4G; - -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -if (isdefinedsymbol(__use_shmem__)) { - define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; -} - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - - -/* regions for USB */ -define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; -define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; -place in USB_BDT_region { section m_usb_bdt }; -place in USB_SRAM_region { section m_usb_global }; - -initialize by copy { readwrite, section .textrw }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - /* Required in a multi-threaded application */ - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; -if (isdefinedsymbol(__use_shmem__)) { - do not initialize { section rpmsg_sh_mem_section }; -} - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; -if (isdefinedsymbol(__use_shmem__)) { - place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; -} - diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/startup_LPC55S69_cm33_core0.s b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/startup_LPC55S69_cm33_core0.s deleted file mode 100644 index e83185c1b5d..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/startup_LPC55S69_cm33_core0.s +++ /dev/null @@ -1,635 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC55S69_cm33_core0.s -; * @purpose: CMSIS Cortex-M33 Core Device Startup File -; * LPC55S69_cm33_core0 -; * @version: 1.1 -; * @date: 2019-5-16 -; *---------------------------------------------------------------------------- -; * -; Copyright 1997-2016 Freescale Semiconductor, Inc. -; Copyright 2016-2021 NXP -; All rights reserved. -; -; SPDX-License-Identifier: BSD-3-Clause -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__iar_init$$done: ; The vector table is not needed - ; until after copy initialization is done - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD SecureFault_Handler - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt - DCD DMA0_IRQHandler ; DMA0 controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD ADC0_IRQHandler ; ADC0 - DCD Reserved39_IRQHandler ; Reserved interrupt - DCD ACMP_IRQHandler ; ACMP interrupts - DCD Reserved41_IRQHandler ; Reserved interrupt - DCD Reserved42_IRQHandler ; Reserved interrupt - DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt - DCD USB0_IRQHandler ; USB device - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD Reserved46_IRQHandler ; Reserved interrupt - DCD MAILBOX_IRQHandler ; WAKEUP,Mailbox interrupt (present on selected devices) - DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int - DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int - DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int - DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int - DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 - DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 - DCD OS_EVENT_IRQHandler ; OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts - DCD Reserved55_IRQHandler ; Reserved interrupt - DCD Reserved56_IRQHandler ; Reserved interrupt - DCD Reserved57_IRQHandler ; Reserved interrupt - DCD SDIO_IRQHandler ; SD/MMC - DCD Reserved59_IRQHandler ; Reserved interrupt - DCD Reserved60_IRQHandler ; Reserved interrupt - DCD Reserved61_IRQHandler ; Reserved interrupt - DCD USB1_PHY_IRQHandler ; USB1_PHY - DCD USB1_IRQHandler ; USB1 interrupt - DCD USB1_NEEDCLK_IRQHandler ; USB1 activity - DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt - DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT0_IRQ0 interrupt - DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT0_IRQ1 interrupt - DCD PLU_IRQHandler ; PLU interrupt - DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt - DCD HASHCRYPT_IRQHandler ; HASHCRYPT interrupt - DCD CASER_IRQHandler ; CASPER interrupt - DCD PUF_IRQHandler ; PUF interrupt - DCD PQ_IRQHandler ; PQ interrupt - DCD DMA1_IRQHandler ; DMA1 interrupt - DCD FLEXCOMM8_IRQHandler ; Flexcomm Interface 8 (SPI, , FLEXCOMM) -__Vectors_End - - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__vector_table - STR R1, [R0] - LDR R2, [R1] - MSR MSP, R2 - LDR R0, =sfb(CSTACK) - MSR MSPLIM, R0 - CPSIE I ; Unmask interrupts - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SecureFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SecureFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK WDT_BOD_IRQHandler - PUBWEAK WDT_BOD_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -WDT_BOD_IRQHandler - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler - LDR R0, =DMA0_DriverIRQHandler - BX R0 - PUBWEAK GINT0_IRQHandler - PUBWEAK GINT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT0_IRQHandler - LDR R0, =GINT0_DriverIRQHandler - BX R0 - PUBWEAK GINT1_IRQHandler - PUBWEAK GINT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT1_IRQHandler - LDR R0, =GINT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT0_IRQHandler - PUBWEAK PIN_INT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT0_IRQHandler - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT1_IRQHandler - PUBWEAK PIN_INT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT1_IRQHandler - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT2_IRQHandler - PUBWEAK PIN_INT2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT2_IRQHandler - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT3_IRQHandler - PUBWEAK PIN_INT3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT3_IRQHandler - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - PUBWEAK UTICK0_IRQHandler - PUBWEAK UTICK0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UTICK0_IRQHandler - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - PUBWEAK MRT0_IRQHandler - PUBWEAK MRT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -MRT0_IRQHandler - LDR R0, =MRT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER0_IRQHandler - PUBWEAK CTIMER0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER0_IRQHandler - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER1_IRQHandler - PUBWEAK CTIMER1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER1_IRQHandler - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - PUBWEAK SCT0_IRQHandler - PUBWEAK SCT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SCT0_IRQHandler - LDR R0, =SCT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER3_IRQHandler - PUBWEAK CTIMER3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER3_IRQHandler - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM0_IRQHandler - PUBWEAK FLEXCOMM0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM0_IRQHandler - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM1_IRQHandler - PUBWEAK FLEXCOMM1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM1_IRQHandler - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM2_IRQHandler - PUBWEAK FLEXCOMM2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM2_IRQHandler - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM3_IRQHandler - PUBWEAK FLEXCOMM3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM3_IRQHandler - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM4_IRQHandler - PUBWEAK FLEXCOMM4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM4_IRQHandler - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM5_IRQHandler - PUBWEAK FLEXCOMM5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM5_IRQHandler - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM6_IRQHandler - PUBWEAK FLEXCOMM6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM6_IRQHandler - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM7_IRQHandler - PUBWEAK FLEXCOMM7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM7_IRQHandler - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - PUBWEAK ADC0_IRQHandler - PUBWEAK ADC0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_IRQHandler - LDR R0, =ADC0_DriverIRQHandler - BX R0 - PUBWEAK Reserved39_IRQHandler - PUBWEAK Reserved39_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved39_IRQHandler - LDR R0, =Reserved39_DriverIRQHandler - BX R0 - PUBWEAK ACMP_IRQHandler - PUBWEAK ACMP_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ACMP_IRQHandler - LDR R0, =ACMP_DriverIRQHandler - BX R0 - PUBWEAK Reserved41_IRQHandler - PUBWEAK Reserved41_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved41_IRQHandler - LDR R0, =Reserved41_DriverIRQHandler - BX R0 - PUBWEAK Reserved42_IRQHandler - PUBWEAK Reserved42_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved42_IRQHandler - LDR R0, =Reserved42_DriverIRQHandler - BX R0 - PUBWEAK USB0_NEEDCLK_IRQHandler - PUBWEAK USB0_NEEDCLK_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_NEEDCLK_IRQHandler - LDR R0, =USB0_NEEDCLK_DriverIRQHandler - BX R0 - PUBWEAK USB0_IRQHandler - PUBWEAK USB0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_IRQHandler - LDR R0, =USB0_DriverIRQHandler - BX R0 - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -RTC_IRQHandler - LDR R0, =RTC_DriverIRQHandler - BX R0 - PUBWEAK Reserved46_IRQHandler - PUBWEAK Reserved46_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved46_IRQHandler - LDR R0, =Reserved46_DriverIRQHandler - BX R0 - PUBWEAK MAILBOX_IRQHandler - PUBWEAK MAILBOX_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -MAILBOX_IRQHandler - LDR R0, =MAILBOX_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT4_IRQHandler - PUBWEAK PIN_INT4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT4_IRQHandler - LDR R0, =PIN_INT4_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT5_IRQHandler - PUBWEAK PIN_INT5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT5_IRQHandler - LDR R0, =PIN_INT5_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT6_IRQHandler - PUBWEAK PIN_INT6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT6_IRQHandler - LDR R0, =PIN_INT6_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT7_IRQHandler - PUBWEAK PIN_INT7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT7_IRQHandler - LDR R0, =PIN_INT7_DriverIRQHandler - BX R0 - PUBWEAK CTIMER2_IRQHandler - PUBWEAK CTIMER2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER2_IRQHandler - LDR R0, =CTIMER2_DriverIRQHandler - BX R0 - PUBWEAK CTIMER4_IRQHandler - PUBWEAK CTIMER4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER4_IRQHandler - LDR R0, =CTIMER4_DriverIRQHandler - BX R0 - PUBWEAK OS_EVENT_IRQHandler - PUBWEAK OS_EVENT_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -OS_EVENT_IRQHandler - LDR R0, =OS_EVENT_DriverIRQHandler - BX R0 - PUBWEAK Reserved55_IRQHandler - PUBWEAK Reserved55_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved55_IRQHandler - LDR R0, =Reserved55_DriverIRQHandler - BX R0 - PUBWEAK Reserved56_IRQHandler - PUBWEAK Reserved56_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved56_IRQHandler - LDR R0, =Reserved56_DriverIRQHandler - BX R0 - PUBWEAK Reserved57_IRQHandler - PUBWEAK Reserved57_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved57_IRQHandler - LDR R0, =Reserved57_DriverIRQHandler - BX R0 - PUBWEAK SDIO_IRQHandler - PUBWEAK SDIO_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SDIO_IRQHandler - LDR R0, =SDIO_DriverIRQHandler - BX R0 - PUBWEAK Reserved59_IRQHandler - PUBWEAK Reserved59_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved59_IRQHandler - LDR R0, =Reserved59_DriverIRQHandler - BX R0 - PUBWEAK Reserved60_IRQHandler - PUBWEAK Reserved60_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved60_IRQHandler - LDR R0, =Reserved60_DriverIRQHandler - BX R0 - PUBWEAK Reserved61_IRQHandler - PUBWEAK Reserved61_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved61_IRQHandler - LDR R0, =Reserved61_DriverIRQHandler - BX R0 - PUBWEAK USB1_PHY_IRQHandler - PUBWEAK USB1_PHY_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB1_PHY_IRQHandler - LDR R0, =USB1_PHY_DriverIRQHandler - BX R0 - PUBWEAK USB1_IRQHandler - PUBWEAK USB1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB1_IRQHandler - LDR R0, =USB1_DriverIRQHandler - BX R0 - PUBWEAK USB1_NEEDCLK_IRQHandler - PUBWEAK USB1_NEEDCLK_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB1_NEEDCLK_IRQHandler - LDR R0, =USB1_NEEDCLK_DriverIRQHandler - BX R0 - PUBWEAK SEC_HYPERVISOR_CALL_IRQHandler - PUBWEAK SEC_HYPERVISOR_CALL_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_HYPERVISOR_CALL_IRQHandler - LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler - BX R0 - PUBWEAK SEC_GPIO_INT0_IRQ0_IRQHandler - PUBWEAK SEC_GPIO_INT0_IRQ0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_GPIO_INT0_IRQ0_IRQHandler - LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler - BX R0 - PUBWEAK SEC_GPIO_INT0_IRQ1_IRQHandler - PUBWEAK SEC_GPIO_INT0_IRQ1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_GPIO_INT0_IRQ1_IRQHandler - LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler - BX R0 - PUBWEAK PLU_IRQHandler - PUBWEAK PLU_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PLU_IRQHandler - LDR R0, =PLU_DriverIRQHandler - BX R0 - PUBWEAK SEC_VIO_IRQHandler - PUBWEAK SEC_VIO_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_VIO_IRQHandler - LDR R0, =SEC_VIO_DriverIRQHandler - BX R0 - PUBWEAK HASHCRYPT_IRQHandler - PUBWEAK HASHCRYPT_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -HASHCRYPT_IRQHandler - LDR R0, =HASHCRYPT_DriverIRQHandler - BX R0 - PUBWEAK CASER_IRQHandler - PUBWEAK CASER_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CASER_IRQHandler - LDR R0, =CASER_DriverIRQHandler - BX R0 - PUBWEAK PUF_IRQHandler - PUBWEAK PUF_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PUF_IRQHandler - LDR R0, =PUF_DriverIRQHandler - BX R0 - PUBWEAK PQ_IRQHandler - PUBWEAK PQ_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PQ_IRQHandler - LDR R0, =PQ_DriverIRQHandler - BX R0 - PUBWEAK DMA1_IRQHandler - PUBWEAK DMA1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA1_IRQHandler - LDR R0, =DMA1_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM8_IRQHandler - PUBWEAK FLEXCOMM8_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM8_IRQHandler - LDR R0, =FLEXCOMM8_DriverIRQHandler - BX R0 -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_DriverIRQHandler -Reserved39_DriverIRQHandler -ACMP_DriverIRQHandler -Reserved41_DriverIRQHandler -Reserved42_DriverIRQHandler -USB0_NEEDCLK_DriverIRQHandler -USB0_DriverIRQHandler -RTC_DriverIRQHandler -Reserved46_DriverIRQHandler -MAILBOX_DriverIRQHandler -PIN_INT4_DriverIRQHandler -PIN_INT5_DriverIRQHandler -PIN_INT6_DriverIRQHandler -PIN_INT7_DriverIRQHandler -CTIMER2_DriverIRQHandler -CTIMER4_DriverIRQHandler -OS_EVENT_DriverIRQHandler -Reserved55_DriverIRQHandler -Reserved56_DriverIRQHandler -Reserved57_DriverIRQHandler -SDIO_DriverIRQHandler -Reserved59_DriverIRQHandler -Reserved60_DriverIRQHandler -Reserved61_DriverIRQHandler -USB1_PHY_DriverIRQHandler -USB1_DriverIRQHandler -USB1_NEEDCLK_DriverIRQHandler -SEC_HYPERVISOR_CALL_DriverIRQHandler -SEC_GPIO_INT0_IRQ0_DriverIRQHandler -SEC_GPIO_INT0_IRQ1_DriverIRQHandler -PLU_DriverIRQHandler -SEC_VIO_DriverIRQHandler -HASHCRYPT_DriverIRQHandler -CASER_DriverIRQHandler -PUF_DriverIRQHandler -PQ_DriverIRQHandler -DMA1_DriverIRQHandler -FLEXCOMM8_DriverIRQHandler -DefaultISR - B . - - END diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/startup_LPC55S69_cm33_core1.s b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/startup_LPC55S69_cm33_core1.s deleted file mode 100644 index 51b8413ef70..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/startup_LPC55S69_cm33_core1.s +++ /dev/null @@ -1,630 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC55S69_cm33_core1.s -; * @purpose: CMSIS Cortex-M33 Core Device Startup File -; * LPC55S69_cm33_core1 -; * @version: 1.1 -; * @date: 2019-5-16 -; *---------------------------------------------------------------------------- -; * -; Copyright 1997-2016 Freescale Semiconductor, Inc. -; Copyright 2016-2020 NXP -; All rights reserved. -; -; SPDX-License-Identifier: BSD-3-Clause -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__iar_init$$done: ; The vector table is not needed - ; until after copy initialization is done - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD SecureFault_Handler - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt - DCD DMA0_IRQHandler ; DMA0 controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD ADC0_IRQHandler ; ADC0 - DCD Reserved39_IRQHandler ; Reserved interrupt - DCD ACMP_IRQHandler ; ACMP interrupts - DCD Reserved41_IRQHandler ; Reserved interrupt - DCD Reserved42_IRQHandler ; Reserved interrupt - DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt - DCD USB0_IRQHandler ; USB device - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD Reserved46_IRQHandler ; Reserved interrupt - DCD MAILBOX_IRQHandler ; WAKEUP,Mailbox interrupt (present on selected devices) - DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int - DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int - DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int - DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int - DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 - DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 - DCD OS_EVENT_IRQHandler ; OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts - DCD Reserved55_IRQHandler ; Reserved interrupt - DCD Reserved56_IRQHandler ; Reserved interrupt - DCD Reserved57_IRQHandler ; Reserved interrupt - DCD SDIO_IRQHandler ; SD/MMC - DCD Reserved59_IRQHandler ; Reserved interrupt - DCD Reserved60_IRQHandler ; Reserved interrupt - DCD Reserved61_IRQHandler ; Reserved interrupt - DCD USB1_PHY_IRQHandler ; USB1_PHY - DCD USB1_IRQHandler ; USB1 interrupt - DCD USB1_NEEDCLK_IRQHandler ; USB1 activity - DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt - DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT0_IRQ0 interrupt - DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT0_IRQ1 interrupt - DCD PLU_IRQHandler ; PLU interrupt - DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt - DCD HASHCRYPT_IRQHandler ; HASHCRYPT interrupt - DCD CASER_IRQHandler ; CASPER interrupt - DCD PUF_IRQHandler ; PUF interrupt - DCD PQ_IRQHandler ; PQ interrupt - DCD DMA1_IRQHandler ; DMA1 interrupt - DCD FLEXCOMM8_IRQHandler ; Flexcomm Interface 8 (SPI, , FLEXCOMM) -__Vectors_End - - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID I ; Mask interrupts - LDR R0, =sfb(CSTACK) - MSR MSPLIM, R0 - LDR R0, =SystemInit - BLX R0 - CPSIE I ; Unmask interrupts - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SecureFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SecureFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK WDT_BOD_IRQHandler - PUBWEAK WDT_BOD_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -WDT_BOD_IRQHandler - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler - LDR R0, =DMA0_DriverIRQHandler - BX R0 - PUBWEAK GINT0_IRQHandler - PUBWEAK GINT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT0_IRQHandler - LDR R0, =GINT0_DriverIRQHandler - BX R0 - PUBWEAK GINT1_IRQHandler - PUBWEAK GINT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT1_IRQHandler - LDR R0, =GINT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT0_IRQHandler - PUBWEAK PIN_INT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT0_IRQHandler - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT1_IRQHandler - PUBWEAK PIN_INT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT1_IRQHandler - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT2_IRQHandler - PUBWEAK PIN_INT2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT2_IRQHandler - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT3_IRQHandler - PUBWEAK PIN_INT3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT3_IRQHandler - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - PUBWEAK UTICK0_IRQHandler - PUBWEAK UTICK0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UTICK0_IRQHandler - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - PUBWEAK MRT0_IRQHandler - PUBWEAK MRT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -MRT0_IRQHandler - LDR R0, =MRT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER0_IRQHandler - PUBWEAK CTIMER0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER0_IRQHandler - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER1_IRQHandler - PUBWEAK CTIMER1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER1_IRQHandler - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - PUBWEAK SCT0_IRQHandler - PUBWEAK SCT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SCT0_IRQHandler - LDR R0, =SCT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER3_IRQHandler - PUBWEAK CTIMER3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER3_IRQHandler - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM0_IRQHandler - PUBWEAK FLEXCOMM0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM0_IRQHandler - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM1_IRQHandler - PUBWEAK FLEXCOMM1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM1_IRQHandler - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM2_IRQHandler - PUBWEAK FLEXCOMM2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM2_IRQHandler - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM3_IRQHandler - PUBWEAK FLEXCOMM3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM3_IRQHandler - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM4_IRQHandler - PUBWEAK FLEXCOMM4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM4_IRQHandler - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM5_IRQHandler - PUBWEAK FLEXCOMM5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM5_IRQHandler - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM6_IRQHandler - PUBWEAK FLEXCOMM6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM6_IRQHandler - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM7_IRQHandler - PUBWEAK FLEXCOMM7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM7_IRQHandler - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - PUBWEAK ADC0_IRQHandler - PUBWEAK ADC0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_IRQHandler - LDR R0, =ADC0_DriverIRQHandler - BX R0 - PUBWEAK Reserved39_IRQHandler - PUBWEAK Reserved39_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved39_IRQHandler - LDR R0, =Reserved39_DriverIRQHandler - BX R0 - PUBWEAK ACMP_IRQHandler - PUBWEAK ACMP_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ACMP_IRQHandler - LDR R0, =ACMP_DriverIRQHandler - BX R0 - PUBWEAK Reserved41_IRQHandler - PUBWEAK Reserved41_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved41_IRQHandler - LDR R0, =Reserved41_DriverIRQHandler - BX R0 - PUBWEAK Reserved42_IRQHandler - PUBWEAK Reserved42_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved42_IRQHandler - LDR R0, =Reserved42_DriverIRQHandler - BX R0 - PUBWEAK USB0_NEEDCLK_IRQHandler - PUBWEAK USB0_NEEDCLK_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_NEEDCLK_IRQHandler - LDR R0, =USB0_NEEDCLK_DriverIRQHandler - BX R0 - PUBWEAK USB0_IRQHandler - PUBWEAK USB0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_IRQHandler - LDR R0, =USB0_DriverIRQHandler - BX R0 - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -RTC_IRQHandler - LDR R0, =RTC_DriverIRQHandler - BX R0 - PUBWEAK Reserved46_IRQHandler - PUBWEAK Reserved46_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved46_IRQHandler - LDR R0, =Reserved46_DriverIRQHandler - BX R0 - PUBWEAK MAILBOX_IRQHandler - PUBWEAK MAILBOX_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -MAILBOX_IRQHandler - LDR R0, =MAILBOX_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT4_IRQHandler - PUBWEAK PIN_INT4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT4_IRQHandler - LDR R0, =PIN_INT4_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT5_IRQHandler - PUBWEAK PIN_INT5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT5_IRQHandler - LDR R0, =PIN_INT5_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT6_IRQHandler - PUBWEAK PIN_INT6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT6_IRQHandler - LDR R0, =PIN_INT6_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT7_IRQHandler - PUBWEAK PIN_INT7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT7_IRQHandler - LDR R0, =PIN_INT7_DriverIRQHandler - BX R0 - PUBWEAK CTIMER2_IRQHandler - PUBWEAK CTIMER2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER2_IRQHandler - LDR R0, =CTIMER2_DriverIRQHandler - BX R0 - PUBWEAK CTIMER4_IRQHandler - PUBWEAK CTIMER4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER4_IRQHandler - LDR R0, =CTIMER4_DriverIRQHandler - BX R0 - PUBWEAK OS_EVENT_IRQHandler - PUBWEAK OS_EVENT_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -OS_EVENT_IRQHandler - LDR R0, =OS_EVENT_DriverIRQHandler - BX R0 - PUBWEAK Reserved55_IRQHandler - PUBWEAK Reserved55_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved55_IRQHandler - LDR R0, =Reserved55_DriverIRQHandler - BX R0 - PUBWEAK Reserved56_IRQHandler - PUBWEAK Reserved56_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved56_IRQHandler - LDR R0, =Reserved56_DriverIRQHandler - BX R0 - PUBWEAK Reserved57_IRQHandler - PUBWEAK Reserved57_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved57_IRQHandler - LDR R0, =Reserved57_DriverIRQHandler - BX R0 - PUBWEAK SDIO_IRQHandler - PUBWEAK SDIO_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SDIO_IRQHandler - LDR R0, =SDIO_DriverIRQHandler - BX R0 - PUBWEAK Reserved59_IRQHandler - PUBWEAK Reserved59_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved59_IRQHandler - LDR R0, =Reserved59_DriverIRQHandler - BX R0 - PUBWEAK Reserved60_IRQHandler - PUBWEAK Reserved60_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved60_IRQHandler - LDR R0, =Reserved60_DriverIRQHandler - BX R0 - PUBWEAK Reserved61_IRQHandler - PUBWEAK Reserved61_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved61_IRQHandler - LDR R0, =Reserved61_DriverIRQHandler - BX R0 - PUBWEAK USB1_PHY_IRQHandler - PUBWEAK USB1_PHY_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB1_PHY_IRQHandler - LDR R0, =USB1_PHY_DriverIRQHandler - BX R0 - PUBWEAK USB1_IRQHandler - PUBWEAK USB1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB1_IRQHandler - LDR R0, =USB1_DriverIRQHandler - BX R0 - PUBWEAK USB1_NEEDCLK_IRQHandler - PUBWEAK USB1_NEEDCLK_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB1_NEEDCLK_IRQHandler - LDR R0, =USB1_NEEDCLK_DriverIRQHandler - BX R0 - PUBWEAK SEC_HYPERVISOR_CALL_IRQHandler - PUBWEAK SEC_HYPERVISOR_CALL_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_HYPERVISOR_CALL_IRQHandler - LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler - BX R0 - PUBWEAK SEC_GPIO_INT0_IRQ0_IRQHandler - PUBWEAK SEC_GPIO_INT0_IRQ0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_GPIO_INT0_IRQ0_IRQHandler - LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler - BX R0 - PUBWEAK SEC_GPIO_INT0_IRQ1_IRQHandler - PUBWEAK SEC_GPIO_INT0_IRQ1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_GPIO_INT0_IRQ1_IRQHandler - LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler - BX R0 - PUBWEAK PLU_IRQHandler - PUBWEAK PLU_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PLU_IRQHandler - LDR R0, =PLU_DriverIRQHandler - BX R0 - PUBWEAK SEC_VIO_IRQHandler - PUBWEAK SEC_VIO_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_VIO_IRQHandler - LDR R0, =SEC_VIO_DriverIRQHandler - BX R0 - PUBWEAK HASHCRYPT_IRQHandler - PUBWEAK HASHCRYPT_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -HASHCRYPT_IRQHandler - LDR R0, =HASHCRYPT_DriverIRQHandler - BX R0 - PUBWEAK CASER_IRQHandler - PUBWEAK CASER_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CASER_IRQHandler - LDR R0, =CASER_DriverIRQHandler - BX R0 - PUBWEAK PUF_IRQHandler - PUBWEAK PUF_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PUF_IRQHandler - LDR R0, =PUF_DriverIRQHandler - BX R0 - PUBWEAK PQ_IRQHandler - PUBWEAK PQ_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PQ_IRQHandler - LDR R0, =PQ_DriverIRQHandler - BX R0 - PUBWEAK DMA1_IRQHandler - PUBWEAK DMA1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA1_IRQHandler - LDR R0, =DMA1_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM8_IRQHandler - PUBWEAK FLEXCOMM8_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM8_IRQHandler - LDR R0, =FLEXCOMM8_DriverIRQHandler - BX R0 -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_DriverIRQHandler -Reserved39_DriverIRQHandler -ACMP_DriverIRQHandler -Reserved41_DriverIRQHandler -Reserved42_DriverIRQHandler -USB0_NEEDCLK_DriverIRQHandler -USB0_DriverIRQHandler -RTC_DriverIRQHandler -Reserved46_DriverIRQHandler -MAILBOX_DriverIRQHandler -PIN_INT4_DriverIRQHandler -PIN_INT5_DriverIRQHandler -PIN_INT6_DriverIRQHandler -PIN_INT7_DriverIRQHandler -CTIMER2_DriverIRQHandler -CTIMER4_DriverIRQHandler -OS_EVENT_DriverIRQHandler -Reserved55_DriverIRQHandler -Reserved56_DriverIRQHandler -Reserved57_DriverIRQHandler -SDIO_DriverIRQHandler -Reserved59_DriverIRQHandler -Reserved60_DriverIRQHandler -Reserved61_DriverIRQHandler -USB1_PHY_DriverIRQHandler -USB1_DriverIRQHandler -USB1_NEEDCLK_DriverIRQHandler -SEC_HYPERVISOR_CALL_DriverIRQHandler -SEC_GPIO_INT0_IRQ0_DriverIRQHandler -SEC_GPIO_INT0_IRQ1_DriverIRQHandler -PLU_DriverIRQHandler -SEC_VIO_DriverIRQHandler -HASHCRYPT_DriverIRQHandler -CASER_DriverIRQHandler -PUF_DriverIRQHandler -PQ_DriverIRQHandler -DMA1_DriverIRQHandler -FLEXCOMM8_DriverIRQHandler -DefaultISR - B . - - END diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core0.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core0.c deleted file mode 100644 index 4bb076478a3..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core0.c +++ /dev/null @@ -1,379 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JBD64_cm33_core0 -** LPC55S69JEV98_cm33_core0 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b220117 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** - rev. 1.1 (2019-05-16) -** Initial A1 version based on v1.3UM -** -** ################################################################### -*/ - -/*! - * @file LPC55S69_cm33_core0 - * @version 1.1 - * @date 2019-05-16 - * @brief Device specific configuration file for LPC55S69_cm33_core0 - * (implementation file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include -#include "fsl_device_registers.h" - -/* PLL0 SSCG control1 */ -#define PLL_SSCG_MD_FRACT_P 0U -#define PLL_SSCG_MD_INT_P 25U -#define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P) -#define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P) - -/* Get predivider (N) from PLL0 NDEC setting */ -static uint32_t findPll0PreDiv(void) -{ - uint32_t preDiv = 1UL; - - /* Direct input is not used? */ - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) - { - preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; - if (preDiv == 0UL) - { - preDiv = 1UL; - } - } - return preDiv; -} - -/* Get postdivider (P) from PLL0 PDEC setting */ -static uint32_t findPll0PostDiv(void) -{ - uint32_t postDiv = 1; - - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) - { - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) - { - postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; - } - else - { - postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); - } - if (postDiv == 0UL) - { - postDiv = 2UL; - } - } - return postDiv; -} - -/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ -static float findPll0MMult(void) -{ - float mMult = 1.0F; - float mMult_fract; - uint32_t mMult_int; - - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) - { - mMult = (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); - } - else - { - mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); - mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P); - mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M) / - (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); - mMult = (float)mMult_int + mMult_fract; - } - if (0ULL == ((uint64_t)mMult)) - { - mMult = 1.0F; - } - return mMult; -} - -/* Get predivider (N) from PLL1 NDEC setting */ -static uint32_t findPll1PreDiv(void) -{ - uint32_t preDiv = 1UL; - - /* Direct input is not used? */ - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) - { - preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; - if (preDiv == 0UL) - { - preDiv = 1UL; - } - } - return preDiv; -} - -/* Get postdivider (P) from PLL1 PDEC setting */ -static uint32_t findPll1PostDiv(void) -{ - uint32_t postDiv = 1UL; - - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0UL) - { - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) != 0UL) - { - postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK; - } - else - { - postDiv = 2UL * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK); - } - if (postDiv == 0UL) - { - postDiv = 2UL; - } - } - return postDiv; -} - -/* Get multiplier (M) from PLL1 MDEC settings */ -static uint32_t findPll1MMult(void) -{ - uint32_t mMult = 1UL; - - mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK; - - if (mMult == 0UL) - { - mMult = 1UL; - } - return mMult; -} - -/* Get FRO 12M Clk */ -/*! brief Return Frequency of FRO 12MHz - * return Frequency of FRO 12MHz - */ -static uint32_t GetFro12MFreq(void) -{ - return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; -} - -/* Get FRO 1M Clk */ -/*! brief Return Frequency of FRO 1MHz - * return Frequency of FRO 1MHz - */ -static uint32_t GetFro1MFreq(void) -{ - return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; -} - -/* Get EXT OSC Clk */ -/*! brief Return Frequency of External Clock - * return Frequency of External Clock. If no external clock is used returns 0. - */ -static uint32_t GetExtClkFreq(void) -{ - return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? CLK_CLK_IN : 0U; -} - -/* Get HF FRO Clk */ -/*! brief Return Frequency of High-Freq output of FRO - * return Frequency of High-Freq output of FRO - */ -static uint32_t GetFroHfFreq(void) -{ - return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; -} - -/* Get RTC OSC Clk */ -/*! brief Return Frequency of 32kHz osc - * return Frequency of 32kHz osc - */ -static uint32_t GetOsc32KFreq(void) -{ - return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? - CLK_RTC_32K_CLK : - ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && ((PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK) != 0UL)) ? - CLK_RTC_32K_CLK : - 0U; -} - - - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ - -__attribute__ ((weak)) void SystemInit (void) { -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ - #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ - - SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ - -#if defined(__MCUXPRESSO) - extern void(*const g_pfnVectors[]) (void); - SCB->VTOR = (uint32_t) &g_pfnVectors; -#else - extern void *__Vectors; - SCB->VTOR = (uint32_t) &__Vectors; -#endif - SYSCON->TRACECLKDIV = 0; -/* Optionally enable RAM banks that may be off by default at reset */ -#if !defined(DONT_ENABLE_DISABLED_RAMBANKS) - SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK - | SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK; -#endif - SystemInitHook(); -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate (void) { - uint32_t clkRate = 0; - uint32_t prediv, postdiv; - uint64_t workRate; - uint64_t workRate1; - - switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) - { - case 0x00: /* MAINCLKSELA clock (main_clk_a)*/ - switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = GetFro12MFreq(); - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = GetExtClkFreq(); - break; - case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = GetFro1MFreq(); - break; - default: /* = 0x03 = FRO 96 MHz (fro_hf) */ - clkRate = GetFroHfFreq(); - break; - } - break; - case 0x01: /* PLL0 clock (pll0_clk)*/ - switch (SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = GetFro12MFreq(); - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = GetExtClkFreq(); - break; - case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = GetFro1MFreq(); - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = GetOsc32KFreq(); - break; - default: - clkRate = 0UL; - break; - } - if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) - { - prediv = findPll0PreDiv(); - postdiv = findPll0PostDiv(); - /* Adjust input clock */ - clkRate = clkRate / prediv; - /* MDEC used for rate */ - workRate = (uint64_t)clkRate * (uint64_t)findPll0MMult(); - clkRate = (uint32_t)(workRate / ((uint64_t)postdiv)); - } - break; - case 0x02: /* PLL1 clock (pll1_clk)*/ - switch (SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = GetFro12MFreq(); - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = GetExtClkFreq(); - break; - case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = GetFro1MFreq(); - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = GetOsc32KFreq(); - break; - default: - clkRate = 0UL; - break; - } - if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0UL)) - { - /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ - prediv = findPll1PreDiv(); - postdiv = findPll1PostDiv(); - /* Adjust input clock */ - clkRate = clkRate / prediv; - - /* MDEC used for rate */ - workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult(); - clkRate = (uint32_t)(workRate1 / ((uint64_t)postdiv)); - } - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = GetOsc32KFreq(); - break; - default: - clkRate = 0UL; - break; - } - SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL); -} - -/* ---------------------------------------------------------------------------- - -- SystemInitHook() - ---------------------------------------------------------------------------- */ - -__attribute__ ((weak)) void SystemInitHook (void) { - /* Void implementation of the weak function. */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core0.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core0.h deleted file mode 100644 index 21f7692759c..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core0.h +++ /dev/null @@ -1,113 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JBD64_cm33_core0 -** LPC55S69JEV98_cm33_core0 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b220117 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** - rev. 1.1 (2019-05-16) -** Initial A1 version based on v1.3UM -** -** ################################################################### -*/ - -/*! - * @file LPC55S69_cm33_core0 - * @version 1.1 - * @date 2019-05-16 - * @brief Device specific configuration file for LPC55S69_cm33_core0 (header - * file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef _SYSTEM_LPC55S69_cm33_core0_H_ -#define _SYSTEM_LPC55S69_cm33_core0_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ -#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ -#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ -#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ -#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ -#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ - - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -/** - * @brief SystemInit function hook. - * - * This weak function allows to call specific initialization code during the - * SystemInit() execution.This can be used when an application specific code needs - * to be called as close to the reset entry as possible (for example the Multicore - * Manager MCMGR_EarlyInit() function call). - * NOTE: No global r/w variables can be used in this hook function because the - * initialization of these variables happens after this function. - */ -void SystemInitHook (void); - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_LPC55S69_cm33_core0_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core1.c b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core1.c deleted file mode 100644 index ee18841534e..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core1.c +++ /dev/null @@ -1,373 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JBD64_cm33_core1 -** LPC55S69JEV98_cm33_core1 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b220117 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** - rev. 1.1 (2019-05-16) -** Initial A1 version based on v1.3UM -** -** ################################################################### -*/ - -/*! - * @file LPC55S69_cm33_core1 - * @version 1.1 - * @date 2019-05-16 - * @brief Device specific configuration file for LPC55S69_cm33_core1 - * (implementation file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include -#include "fsl_device_registers.h" - -/* PLL0 SSCG control1 */ -#define PLL_SSCG_MD_FRACT_P 0U -#define PLL_SSCG_MD_INT_P 25U -#define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P) -#define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P) - -/* Get predivider (N) from PLL0 NDEC setting */ -static uint32_t findPll0PreDiv(void) -{ - uint32_t preDiv = 1UL; - - /* Direct input is not used? */ - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) - { - preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; - if (preDiv == 0UL) - { - preDiv = 1UL; - } - } - return preDiv; -} - -/* Get postdivider (P) from PLL0 PDEC setting */ -static uint32_t findPll0PostDiv(void) -{ - uint32_t postDiv = 1; - - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) - { - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) - { - postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; - } - else - { - postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); - } - if (postDiv == 0UL) - { - postDiv = 2UL; - } - } - return postDiv; -} - -/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ -static float findPll0MMult(void) -{ - float mMult = 1.0F; - float mMult_fract; - uint32_t mMult_int; - - if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) - { - mMult = (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); - } - else - { - mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); - mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P); - mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M) / - (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); - mMult = (float)mMult_int + mMult_fract; - } - if (0ULL == ((uint64_t)mMult)) - { - mMult = 1.0F; - } - return mMult; -} - -/* Get predivider (N) from PLL1 NDEC setting */ -static uint32_t findPll1PreDiv(void) -{ - uint32_t preDiv = 1UL; - - /* Direct input is not used? */ - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) - { - preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; - if (preDiv == 0UL) - { - preDiv = 1UL; - } - } - return preDiv; -} - -/* Get postdivider (P) from PLL1 PDEC setting */ -static uint32_t findPll1PostDiv(void) -{ - uint32_t postDiv = 1UL; - - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0UL) - { - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) != 0UL) - { - postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK; - } - else - { - postDiv = 2UL * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK); - } - if (postDiv == 0UL) - { - postDiv = 2UL; - } - } - return postDiv; -} - -/* Get multiplier (M) from PLL1 MDEC settings */ -static uint32_t findPll1MMult(void) -{ - uint32_t mMult = 1UL; - - mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK; - - if (mMult == 0UL) - { - mMult = 1UL; - } - return mMult; -} - -/* Get FRO 12M Clk */ -/*! brief Return Frequency of FRO 12MHz - * return Frequency of FRO 12MHz - */ -static uint32_t GetFro12MFreq(void) -{ - return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; -} - -/* Get FRO 1M Clk */ -/*! brief Return Frequency of FRO 1MHz - * return Frequency of FRO 1MHz - */ -static uint32_t GetFro1MFreq(void) -{ - return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; -} - -/* Get EXT OSC Clk */ -/*! brief Return Frequency of External Clock - * return Frequency of External Clock. If no external clock is used returns 0. - */ -static uint32_t GetExtClkFreq(void) -{ - return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? CLK_CLK_IN : 0U; -} - -/* Get HF FRO Clk */ -/*! brief Return Frequency of High-Freq output of FRO - * return Frequency of High-Freq output of FRO - */ -static uint32_t GetFroHfFreq(void) -{ - return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; -} - -/* Get RTC OSC Clk */ -/*! brief Return Frequency of 32kHz osc - * return Frequency of 32kHz osc - */ -static uint32_t GetOsc32KFreq(void) -{ - return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? - CLK_RTC_32K_CLK : - ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && ((PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK) != 0UL)) ? - CLK_RTC_32K_CLK : - 0U; -} - - - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ - -__attribute__ ((weak)) void SystemInit (void) { - - SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ - -#if defined(__MCUXPRESSO) - extern void(*const g_pfnVectors[]) (void); - SCB->VTOR = (uint32_t) &g_pfnVectors; -#else - extern void *__Vectors; - SCB->VTOR = (uint32_t) &__Vectors; -#endif - SYSCON->TRACECLKDIV = 0; -/* Optionally enable RAM banks that may be off by default at reset */ -#if !defined(DONT_ENABLE_DISABLED_RAMBANKS) - SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK - | SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK; -#endif - SystemInitHook(); -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate (void) { - uint32_t clkRate = 0; - uint32_t prediv, postdiv; - uint64_t workRate; - uint64_t workRate1; - - switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) - { - case 0x00: /* MAINCLKSELA clock (main_clk_a)*/ - switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = GetFro12MFreq(); - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = GetExtClkFreq(); - break; - case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = GetFro1MFreq(); - break; - default: /* = 0x03 = FRO 96 MHz (fro_hf) */ - clkRate = GetFroHfFreq(); - break; - } - break; - case 0x01: /* PLL0 clock (pll0_clk)*/ - switch (SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = GetFro12MFreq(); - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = GetExtClkFreq(); - break; - case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = GetFro1MFreq(); - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = GetOsc32KFreq(); - break; - default: - clkRate = 0UL; - break; - } - if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) - { - prediv = findPll0PreDiv(); - postdiv = findPll0PostDiv(); - /* Adjust input clock */ - clkRate = clkRate / prediv; - /* MDEC used for rate */ - workRate = (uint64_t)clkRate * (uint64_t)findPll0MMult(); - clkRate = (uint32_t)(workRate / ((uint64_t)postdiv)); - } - break; - case 0x02: /* PLL1 clock (pll1_clk)*/ - switch (SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = GetFro12MFreq(); - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = GetExtClkFreq(); - break; - case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = GetFro1MFreq(); - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = GetOsc32KFreq(); - break; - default: - clkRate = 0UL; - break; - } - if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0UL)) - { - /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ - prediv = findPll1PreDiv(); - postdiv = findPll1PostDiv(); - /* Adjust input clock */ - clkRate = clkRate / prediv; - - /* MDEC used for rate */ - workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult(); - clkRate = (uint32_t)(workRate1 / ((uint64_t)postdiv)); - } - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = GetOsc32KFreq(); - break; - default: - clkRate = 0UL; - break; - } - SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL); -} - -/* ---------------------------------------------------------------------------- - -- SystemInitHook() - ---------------------------------------------------------------------------- */ - -__attribute__ ((weak)) void SystemInitHook (void) { - /* Void implementation of the weak function. */ -} diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core1.h b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core1.h deleted file mode 100644 index b86cf98b2ed..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core1.h +++ /dev/null @@ -1,113 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JBD64_cm33_core1 -** LPC55S69JEV98_cm33_core1 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 -** Version: rev. 1.1, 2019-05-16 -** Build: b220117 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2022 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** - rev. 1.1 (2019-05-16) -** Initial A1 version based on v1.3UM -** -** ################################################################### -*/ - -/*! - * @file LPC55S69_cm33_core1 - * @version 1.1 - * @date 2019-05-16 - * @brief Device specific configuration file for LPC55S69_cm33_core1 (header - * file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef _SYSTEM_LPC55S69_cm33_core1_H_ -#define _SYSTEM_LPC55S69_cm33_core1_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ -#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ -#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ -#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ -#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ -#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ - - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -/** - * @brief SystemInit function hook. - * - * This weak function allows to call specific initialization code during the - * SystemInit() execution.This can be used when an application specific code needs - * to be called as close to the reset entry as possible (for example the Multicore - * Manager MCMGR_EarlyInit() function call). - * NOTE: No global r/w variables can be used in this hook function because the - * initialization of these variables happens after this function. - */ -void SystemInitHook (void); - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_LPC55S69_cm33_core1_H_ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/SConscript b/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/SConscript deleted file mode 100644 index 6ac882b5240..00000000000 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/LPC55S6X/SConscript +++ /dev/null @@ -1,60 +0,0 @@ -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -path = [cwd + '/../CMSIS/Core/Include',cwd + '/components/codec', cwd + '/LPC55S6X', cwd + '/LPC55S6X/drivers', cwd + '/middleware/sdmmc/inc', cwd + '/middleware/sdmmc/port'] -src = Split(''' - LPC55S6X/system_LPC55S69_cm33_core0.c - ''') - -if rtconfig.PLATFORM in ['gcc']: - src += ['LPC55S6X/gcc/startup_LPC55S69_cm33_core0.S'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - src += ['LPC55S6X/arm/startup_LPC55S69_cm33_core0.s'] -elif rtconfig.PLATFORM in ['iccarm']: - src += ['LPC55S6X/iar/startup_LPC55S69_cm33_core0.s'] - -src += ['LPC55S6X/drivers/fsl_anactrl.c'] -src += ['LPC55S6X/drivers/fsl_casper.c'] -src += ['LPC55S6X/drivers/fsl_clock.c'] -src += ['LPC55S6X/drivers/fsl_cmp.c'] -src += ['LPC55S6X/drivers/fsl_common.c'] -src += ['LPC55S6X/drivers/fsl_common_arm.c'] -src += ['LPC55S6X/drivers/fsl_crc.c'] -src += ['LPC55S6X/drivers/fsl_ctimer.c'] -src += ['LPC55S6X/drivers/fsl_flexcomm.c'] -src += ['LPC55S6X/drivers/fsl_dma.c'] -src += ['LPC55S6X/drivers/fsl_gint.c'] -src += ['LPC55S6X/drivers/fsl_gpio.c'] -src += ['LPC55S6X/drivers/fsl_hashcrypt.c'] -src += ['LPC55S6X/drivers/fsl_i2c.c'] -src += ['LPC55S6X/drivers/fsl_i2c_dma.c'] -src += ['LPC55S6X/drivers/fsl_i2s.c'] -src += ['LPC55S6X/drivers/fsl_i2s_dma.c'] -src += ['LPC55S6X/drivers/fsl_iap.c'] -src += ['LPC55S6X/drivers/fsl_inputmux.c'] -src += ['LPC55S6X/drivers/fsl_lpadc.c'] -src += ['LPC55S6X/drivers/fsl_mrt.c'] -src += ['LPC55S6X/drivers/fsl_ostimer.c'] -src += ['LPC55S6X/drivers/fsl_pint.c'] -src += ['LPC55S6X/drivers/fsl_plu.c'] -src += ['LPC55S6X/drivers/fsl_power.c'] -src += ['LPC55S6X/drivers/fsl_powerquad_basic.c'] -src += ['LPC55S6X/drivers/fsl_puf.c'] -src += ['LPC55S6X/drivers/fsl_reset.c'] -src += ['LPC55S6X/drivers/fsl_rng.c'] -src += ['LPC55S6X/drivers/fsl_rtc.c'] -src += ['LPC55S6X/drivers/fsl_sctimer.c'] -src += ['LPC55S6X/drivers/fsl_sdif.c'] -src += ['LPC55S6X/drivers/fsl_spi.c'] -src += ['LPC55S6X/drivers/fsl_spi_dma.c'] -src += ['LPC55S6X/drivers/fsl_sysctl.c'] -src += ['LPC55S6X/drivers/fsl_usart.c'] -src += ['LPC55S6X/drivers/fsl_usart_dma.c'] -src += ['LPC55S6X/drivers/fsl_utick.c'] -src += ['LPC55S6X/drivers/fsl_wwdt.c'] - - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) - -Return('group') diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/Kconfig b/bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/Kconfig index 5b691a71f54..797f5649545 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/Kconfig +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/Kconfig @@ -10,9 +10,10 @@ config SOC_LPC55S06 bool select ARCH_ARM_CORTEX_M33 select ARCH_ARM_CORTEX_SECURE + select PKG_USING_NXP_LPC55S_DRIVER default y source "$(RTT_DIR)/Kconfig" osource "$PKGS_DIR/Kconfig" -rsource "../libraries/Kconfig" +rsource "../Libraries/Kconfig" rsource "board/Kconfig" diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/README.md b/bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/README.md index fa2b638f251..32ca996b235 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/README.md +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/README.md @@ -66,9 +66,15 @@ LPC55S06 是由æ©æ™ºæµ¦NXPåŠå¯¼ä½“推出的基于Cortex-M33内核的高性能 menuconfig ``` +éšåŽæ‹‰å–å¿…è¦çš„库，å¦åˆ™æ— æ³•é€šè¿‡ç¼–译 + +```bash + pkgs --update +``` + 在menuconfig页é¢é…置并选择对应的芯片型å·ï¼Œè‹¥å¼€å‘环境为MDK/IAR，则需è¦ç”Ÿæˆå·¥ç¨‹ -4) 生æˆå·¥ç¨‹(Mac/Linux下请跳过此步骤) +1) 生æˆå·¥ç¨‹(Mac/Linux下请跳过此步骤) （Windows IAR） diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/SConstruct b/bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/SConstruct index ed0bfe11ffd..1d7c317205e 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/SConstruct +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/SConstruct @@ -15,6 +15,23 @@ except: print(RTT_ROOT) exit(-1) +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "nxp-lpc55s-series-latest"), + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n==============================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("==============================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread.' + rtconfig.TARGET_EXT if rtconfig.PLATFORM == 'armcc': @@ -61,7 +78,7 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) # include cmsis -objs.extend(SConscript(os.path.join(libraries_path_prefix, rtconfig.BSP_LIBRARY_TYPE, 'SConscript'))) +objs.extend(SConscript(os.path.join("packages/nxp-lpc55s-series-latest", rtconfig.BSP_LIBRARY_TYPE, 'SConscript'))) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/Kconfig b/bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/Kconfig index d5ddb3fbcd4..16bac7ae9e5 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/Kconfig +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/Kconfig @@ -10,9 +10,10 @@ config SOC_LPC55S16 bool select ARCH_ARM_CORTEX_M33 select ARCH_ARM_CORTEX_SECURE + select PKG_USING_NXP_LPC55S_DRIVER default y source "$(RTT_DIR)/Kconfig" osource "$PKGS_DIR/Kconfig" -rsource "../libraries/Kconfig" +rsource "../Libraries/Kconfig" rsource "board/Kconfig" diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/README.md b/bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/README.md index 0e6c96a4774..78ed159ec71 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/README.md +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/README.md @@ -61,6 +61,12 @@ LPC55S16 是由æ©æ™ºæµ¦NXPåŠå¯¼ä½“推出的基于Cortex-M33内核的高性能 menuconfig ``` +éšåŽæ‹‰å–å¿…è¦çš„库，å¦åˆ™æ— æ³•é€šè¿‡ç¼–译 + +```bash + pkgs --update +``` + 在menuconfig页é¢é…置并选择对应的芯片型å·ï¼Œè‹¥å¼€å‘环境为MDK/IAR，则需è¦ç”Ÿæˆå·¥ç¨‹ 4) 生æˆå·¥ç¨‹ diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/SConstruct b/bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/SConstruct index ed0bfe11ffd..1d7c317205e 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/SConstruct +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/SConstruct @@ -15,6 +15,23 @@ except: print(RTT_ROOT) exit(-1) +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "nxp-lpc55s-series-latest"), + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n==============================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("==============================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread.' + rtconfig.TARGET_EXT if rtconfig.PLATFORM == 'armcc': @@ -61,7 +78,7 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) # include cmsis -objs.extend(SConscript(os.path.join(libraries_path_prefix, rtconfig.BSP_LIBRARY_TYPE, 'SConscript'))) +objs.extend(SConscript(os.path.join("packages/nxp-lpc55s-series-latest", rtconfig.BSP_LIBRARY_TYPE, 'SConscript'))) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/Kconfig b/bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/Kconfig index be4766cf795..2a91aabc9ac 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/Kconfig +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/Kconfig @@ -10,9 +10,10 @@ config SOC_LPC55S28 bool select ARCH_ARM_CORTEX_M33 select ARCH_ARM_CORTEX_SECURE + select PKG_USING_NXP_LPC55S_DRIVER default y source "$(RTT_DIR)/Kconfig" osource "$PKGS_DIR/Kconfig" -rsource "../libraries/Kconfig" +rsource "../Libraries/Kconfig" rsource "board/Kconfig" diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/README.md b/bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/README.md index 7882f3c32fd..8b1a6947581 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/README.md +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/README.md @@ -66,6 +66,12 @@ LPC55S28 是由æ©æ™ºæµ¦NXPåŠå¯¼ä½“推出的基于Cortex-M33内核的高性能 menuconfig ``` +éšåŽæ‹‰å–å¿…è¦çš„库，å¦åˆ™æ— æ³•é€šè¿‡ç¼–译 + +```bash + pkgs --update +``` + 在menuconfig页é¢é…置并选择对应的芯片型å·ï¼Œè‹¥å¼€å‘环境为MDK/IAR，则需è¦ç”Ÿæˆå·¥ç¨‹ 4) 生æˆå·¥ç¨‹(Mac/Linux下请跳过此步骤) diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/SConstruct b/bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/SConstruct index ed0bfe11ffd..1d7c317205e 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/SConstruct +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/SConstruct @@ -15,6 +15,23 @@ except: print(RTT_ROOT) exit(-1) +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "nxp-lpc55s-series-latest"), + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n==============================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("==============================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread.' + rtconfig.TARGET_EXT if rtconfig.PLATFORM == 'armcc': @@ -61,7 +78,7 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) # include cmsis -objs.extend(SConscript(os.path.join(libraries_path_prefix, rtconfig.BSP_LIBRARY_TYPE, 'SConscript'))) +objs.extend(SConscript(os.path.join("packages/nxp-lpc55s-series-latest", rtconfig.BSP_LIBRARY_TYPE, 'SConscript'))) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/Kconfig b/bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/Kconfig index 64f1a9c99db..a7d06e4d90d 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/Kconfig +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/Kconfig @@ -10,9 +10,10 @@ config SOC_LPC55S36 bool select ARCH_ARM_CORTEX_M33 select ARCH_ARM_CORTEX_SECURE + select PKG_USING_NXP_LPC55S_DRIVER default y source "$(RTT_DIR)/Kconfig" osource "$PKGS_DIR/Kconfig" -rsource "../libraries/Kconfig" +rsource "../Libraries/Kconfig" rsource "board/Kconfig" diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/README.md b/bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/README.md index ab4ecf051eb..bbee2d24ddf 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/README.md +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/README.md @@ -61,6 +61,12 @@ LPC55S36 是由æ©æ™ºæµ¦NXPåŠå¯¼ä½“推出的基于Cortex-M33内核的高性能 menuconfig ``` +éšåŽæ‹‰å–å¿…è¦çš„库，å¦åˆ™æ— æ³•é€šè¿‡ç¼–译 + +```bash + pkgs --update +``` + 在menuconfig页é¢é…置并选择对应的芯片型å·ï¼Œè‹¥å¼€å‘环境为MDK/IAR，则需è¦ç”Ÿæˆå·¥ç¨‹ 4) 生æˆå·¥ç¨‹ diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/SConstruct b/bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/SConstruct index ed0bfe11ffd..1d7c317205e 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/SConstruct +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/SConstruct @@ -15,6 +15,23 @@ except: print(RTT_ROOT) exit(-1) +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "nxp-lpc55s-series-latest"), + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n==============================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("==============================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread.' + rtconfig.TARGET_EXT if rtconfig.PLATFORM == 'armcc': @@ -61,7 +78,7 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) # include cmsis -objs.extend(SConscript(os.path.join(libraries_path_prefix, rtconfig.BSP_LIBRARY_TYPE, 'SConscript'))) +objs.extend(SConscript(os.path.join("packages/nxp-lpc55s-series-latest", rtconfig.BSP_LIBRARY_TYPE, 'SConscript'))) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/Kconfig b/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/Kconfig index 4f66cb2fce1..a071b599cb5 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/Kconfig +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/Kconfig @@ -10,9 +10,10 @@ config SOC_LPC55S69 bool select ARCH_ARM_CORTEX_M33 select ARCH_ARM_CORTEX_SECURE + select PKG_USING_NXP_LPC55S_DRIVER default y source "$(RTT_DIR)/Kconfig" osource "$PKGS_DIR/Kconfig" -rsource "../libraries/Kconfig" +rsource "../Libraries/Kconfig" rsource "board/Kconfig" diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/README.md b/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/README.md index de4ce3d829d..39267ca1dfb 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/README.md +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/README.md @@ -66,6 +66,12 @@ Includes the following hardware features: menuconfig ``` +Then, the necessary libraries should be pulled; otherwise, the compilation will fail. + +```bash + pkgs --update +``` + On the menuconfig page, configure and select the corresponding chip model, if the development environment is MDK/IAR, you need to generate the project. 4) Build Project (please skip this step under Mac/Linux) diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/README_zh.md b/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/README_zh.md index 903c90196bd..2398c449567 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/README_zh.md +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/README_zh.md @@ -68,6 +68,12 @@ LPC55S69 是由æ©æ™ºæµ¦NXPåŠå¯¼ä½“推出的基于Cortex-M33内核的高性能 menuconfig ``` +éšåŽæ‹‰å–å¿…è¦çš„库，å¦åˆ™æ— æ³•é€šè¿‡ç¼–译 + +```bash + pkgs --update +``` + 在menuconfig页é¢é…置并选择对应的芯片型å·ï¼Œè‹¥å¼€å‘环境为MDK/IAR，则需è¦ç”Ÿæˆå·¥ç¨‹ 4) 生æˆå·¥ç¨‹(Mac/Linux下请跳过此步骤) diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/SConstruct b/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/SConstruct index ed0bfe11ffd..1d7c317205e 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/SConstruct +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/SConstruct @@ -15,6 +15,23 @@ except: print(RTT_ROOT) exit(-1) +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "nxp-lpc55s-series-latest"), + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n==============================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("==============================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread.' + rtconfig.TARGET_EXT if rtconfig.PLATFORM == 'armcc': @@ -61,7 +78,7 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) # include cmsis -objs.extend(SConscript(os.path.join(libraries_path_prefix, rtconfig.BSP_LIBRARY_TYPE, 'SConscript'))) +objs.extend(SConscript(os.path.join("packages/nxp-lpc55s-series-latest", rtconfig.BSP_LIBRARY_TYPE, 'SConscript'))) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/nxp/lpc/lpc55sxx/tools/sdk_dist.py b/bsp/nxp/lpc/lpc55sxx/tools/sdk_dist.py index ccf0cc75a1d..09971e7c00e 100644 --- a/bsp/nxp/lpc/lpc55sxx/tools/sdk_dist.py +++ b/bsp/nxp/lpc/lpc55sxx/tools/sdk_dist.py @@ -15,10 +15,6 @@ def dist_do_building(BSP_ROOT, dist_dir): library_dir = os.path.join(dist_dir, 'Libraries') print("=> copy bsp drivers") bsp_copy_files(os.path.join(library_path, 'drivers'), os.path.join(library_dir, 'drivers')) - print("=> copy bsp CMSIS") - bsp_copy_files(os.path.join(library_path, 'CMSIS'), os.path.join(library_dir, 'CMSIS')) - print("=> copy bsp library") - bsp_copy_files(os.path.join(library_path, rtconfig.BSP_LIBRARY_TYPE), os.path.join(library_dir, rtconfig.BSP_LIBRARY_TYPE)) shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) # change RTT_ROOT in Kconfig diff --git a/bsp/nxp/lpc/lpc824/Kconfig b/bsp/nxp/lpc/lpc824/Kconfig index 66a97c56881..1c701d2cc25 100644 --- a/bsp/nxp/lpc/lpc824/Kconfig +++ b/bsp/nxp/lpc/lpc824/Kconfig @@ -14,6 +14,7 @@ config SOC_LPC824 select ARCH_ARM_CORTEX_M0 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select PKG_USING_NXP_LPC_DRIVER default y source "$(BSP_DIR)/drivers/Kconfig" diff --git a/bsp/nxp/lpc/lpc824/Libraries/SConscript b/bsp/nxp/lpc/lpc824/Libraries/SConscript deleted file mode 100644 index dd2be331433..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/SConscript +++ /dev/null @@ -1,28 +0,0 @@ -# RT-Thread building script for component - -Import('rtconfig') -Import('RTT_ROOT') -from building import * - -cwd = GetCurrentDir() - -src = Glob('peri_driver/*/*.c') -src += Glob('common/board/*.c') -src += Glob('common/chip/*.c') - -# add for startup script -if rtconfig.PLATFORM in ['gcc']: - src += [cwd + '/common/startup/gcc_startup_lpc82x.s'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - src += [cwd + '/common/startup/keil_startup_lpc82x.s'] -elif rtconfig.PLATFORM in ['iccarm']: - src += [cwd + '/common/startup/iar_startup_lpc82x.s'] - -CPPPATH = [ cwd + '/peri_driver', cwd + '/common/board', - cwd + '/common/chip', cwd + '/common/CMSIS'] - -CPPDEFINES = ['CORE_M0PLUS'] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) - -Return('group') diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/CMSIS/cmsis_armcc.h b/bsp/nxp/lpc/lpc824/Libraries/common/CMSIS/cmsis_armcc.h deleted file mode 100644 index 74c49c67def..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/CMSIS/cmsis_armcc.h +++ /dev/null @@ -1,734 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - - -#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return(result); -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#endif /* (__CORTEX_M >= 0x04) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/CMSIS/cmsis_armcc_V6.h b/bsp/nxp/lpc/lpc824/Libraries/common/CMSIS/cmsis_armcc_V6.h deleted file mode 100644 index cd13240ce36..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/CMSIS/cmsis_armcc_V6.h +++ /dev/null @@ -1,1800 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc_V6.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_ARMCC_V6_H -#define __CMSIS_ARMCC_V6_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get IPSR Register (non-secure) - \details Returns the content of the non-secure IPSR Register when in secure state. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get APSR Register (non-secure) - \details Returns the content of the non-secure APSR Register when in secure state. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get xPSR Register (non-secure) - \details Returns the content of the non-secure xPSR Register when in secure state. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Base Priority with condition (non_secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) -{ - __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); -} -#endif - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - - -#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - -#if (__ARM_ARCH_8M__ == 1U) - -/** - \brief Get Process Stack Pointer Limit - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Get Process Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Get Main Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Set Main Stack Pointer Limit (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -} -#endif - -#endif /* (__ARM_ARCH_8M__ == 1U) */ - - -#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ - -/** - \brief Get FPSCR - \details eturns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#define __get_FPSCR __builtin_arm_get_fpscr -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} -#endif - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get FPSCR (non-secure) - \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. - \return Floating Point Status/Control register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} -#endif - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#define __set_FPSCR __builtin_arm_set_fpscr -#if 0 -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} -#endif - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set FPSCR (non-secure) - \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} -#endif - -#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF); - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF); - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF); - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __builtin_bswap32 - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} -#endif - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -/*#define __SSAT __builtin_arm_ssat*/ -#define __SSAT(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat -#if 0 -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) -#endif - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - -#if (__ARM_ARCH_8M__ == 1U) - -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* (__ARM_ARCH_8M__ == 1U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1U) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_V6_H */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/CMSIS/cmsis_gcc.h b/bsp/nxp/lpc/lpc824/Libraries/common/CMSIS/cmsis_gcc.h deleted file mode 100644 index a1cabfbdfe3..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/CMSIS/cmsis_gcc.h +++ /dev/null @@ -1,2213 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS compiler GCC header file - * @version V5.4.1 - * @date 27. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -/* Fallback for __has_builtin */ -#ifndef __has_builtin - #define __has_builtin(x) (0) -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START - -/** - \brief Initializes data and bss sections - \details This default implementations initialized all data and additional bss - sections relying on .copy.table and .zero.table specified properly - in the used linker script. - - */ -__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) -{ - // extern void _start(void) __NO_RETURN; - extern int entry(); - - typedef struct { - uint32_t const* src; - uint32_t* dest; - uint32_t wlen; - } __copy_table_t; - - typedef struct { - uint32_t* dest; - uint32_t wlen; - } __zero_table_t; - - extern const __copy_table_t __copy_table_start__; - extern const __copy_table_t __copy_table_end__; - extern const __zero_table_t __zero_table_start__; - extern const __zero_table_t __zero_table_end__; - - for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = pTable->src[i]; - } - } - - for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = 0u; - } - } - - entry(); - // _start(); -} - -#define __PROGRAM_START __cmsis_start -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP __StackTop -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT __StackLimit -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL __StackSeal -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __ASM volatile ("nop") - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __ASM volatile ("wfi":::"memory") - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __ASM volatile ("wfe":::"memory") - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __ASM volatile ("sev") - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__STATIC_FORCEINLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__STATIC_FORCEINLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__STATIC_FORCEINLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (int16_t)__builtin_bswap16(value); -#else - int16_t result; - - __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return result; -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__STATIC_FORCEINLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1, ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1, ARG2) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - return __builtin_arm_get_fpscr(); -#else - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#endif -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_set_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - __builtin_arm_set_fpscr(fpscr); -#else - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); -#endif -#else - (void)fpscr; -#endif -} - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1, ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - -#define __USAT16(ARG1, ARG2) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) -{ - uint32_t result; - if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { - __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); - } else { - result = __SXTB16(__ROR(op1, rotate)) ; - } - return result; -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) -{ - uint32_t result; - if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { - __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); - } else { - result = __SXTAB16(op1, __ROR(op2, rotate)); - } - return result; -} - - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -#define __PKHBT(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#pragma GCC diagnostic pop - -#endif /* __CMSIS_GCC_H */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/CMSIS/core_cm0plus.h b/bsp/nxp/lpc/lpc824/Libraries/common/CMSIS/core_cm0plus.h deleted file mode 100644 index b04aa390532..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/CMSIS/core_cm0plus.h +++ /dev/null @@ -1,914 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000U - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/CMSIS/core_cmFunc.h b/bsp/nxp/lpc/lpc824/Libraries/common/CMSIS/core_cmFunc.h deleted file mode 100644 index 652a48af07a..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/CMSIS/core_cmFunc.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/CMSIS/core_cmInstr.h b/bsp/nxp/lpc/lpc824/Libraries/common/CMSIS/core_cmInstr.h deleted file mode 100644 index f474b0e6f36..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/CMSIS/core_cmInstr.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/board/board_api.h b/bsp/nxp/lpc/lpc824/Libraries/common/board/board_api.h deleted file mode 100644 index 620a51d63a4..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/board/board_api.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * @brief Common board API functions - * - * @note - * Copyright(C) NXP Semiconductors, 2013 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __BOARD_API_H_ -#define __BOARD_API_H_ - -#include "lpc_types.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup BOARD_COMMON_API BOARD: Common board functions - * @ingroup BOARD_Common - * This file contains common board definitions that are shared across - * boards and devices. All of these functions do not need to be - * implemented for a specific board, but if they are implemented, they - * should use this API standard. - * @{ - */ - -/** - * @brief Setup and initialize hardware prior to call to main() - * @return None - * @note Board_SystemInit() is called prior to the application and sets up system - * clocking, memory, and any resources needed prior to the application - * starting. - */ -void Board_SystemInit(void); - -/** - * @brief Setup pin multiplexer per board schematics - * @return None - * @note Board_SetupMuxing() should be called from SystemInit() prior to application - * main() is called. So that the PINs are set in proper state. - */ -void Board_SetupMuxing(void); - -/** - * @brief Setup system clocking - * @return None - * @note This sets up board clocking. - */ -void Board_SetupClocking(void); - -/** - * @brief Setup external system memory - * @return None - * @note This function is typically called after pin mux setup and clock setup and - * sets up any external memory needed by the system (DRAM, SRAM, etc.). Not all - * boards need this function. - */ -void Board_SetupExtMemory(void); - -/** - * @brief Set up and initialize all required blocks and functions related to the board hardware. - * @return None - */ -void Board_Init(void); - -/** - * @brief Initializes board UART for output, required for printf redirection - * @return None - */ -void Board_Debug_Init(void); - -/** - * @brief Sends a single character on the UART, required for printf redirection - * @param ch : character to send - * @return None - */ -void Board_UARTPutChar(char ch); - -/** - * @brief Sends a single character on the UART, automatic process '\n' -> '\r\n' - * @param ch : character to send - * @return None - */ -void Board_UARTPutTextChar(char ch); - - -/** - * @brief Classic implementation of itoa -- integer to ASCII - * @param value : value to convert - * @param result : result string - * @param base : output radix - * @return result string or NULL - */ -char *Board_itoa(int value, char *result, int base); - -/** - * @brief Get a single character from the UART, required for scanf input - * @return EOF if not character was received, or character value - */ -int Board_UARTGetChar(void); - -/** - * @brief Prints a string to the UART - * @param str : Terminated string to output - * @return None - */ -void Board_UARTPutSTR(const char *str); - -/** - * @brief Get if a key is down - * @param keyIndex : The index of the key to detect - * @return 1 = key is down , 0 = key is up - */ -uint32_t Board_Key_GetKeyDown(uint32_t keyIndex); - -/** - * @brief Sets the state of a board LED to on or off - * @param LEDNumber : LED number to set state for - * @param State : true for on, false for off - * @return None - */ -void Board_LED_Set(uint8_t LEDNumber, bool State); - -/** - * @brief Returns the current state of a board LED - * @param LEDNumber : LED number to set state for - * @return true if the LED is on, otherwise false - */ -bool Board_LED_Test(uint8_t LEDNumber); - -/** - * @brief Toggles the current state of a board LED - * @param LEDNumber : LED number to change state for - * @return None - */ -void Board_LED_Toggle(uint8_t LEDNumber); - -/** - * @brief Turn on Board LCD Backlight - * @param Intensity : Backlight intensity (0 = off, >=1 = on) - * @return None - * @note On boards where a GPIO is used to control backlight on/off state, a '0' or '1' - * value will turn off or on the backlight. On some boards, a non-0 value will - * control backlight intensity via a PWN. For PWM systems, the intensity value - * is a percentage value between 0 and 100%. - */ -void Board_SetLCDBacklight(uint8_t Intensity); - -/** - * @brief Function prototype for a MS delay function. Board layers or example code may - * define this function as needed. - */ -typedef void (*p_msDelay_func_t)(uint32_t); - -/* The DEBUG* functions are selected based on system configuration. - Code that uses the DEBUG* functions will have their I/O routed to - the UART, semihosting, or nowhere. */ -#if defined(DEBUG_ENABLE) -#if defined(DEBUG_SEMIHOSTING) -#define DEBUGINIT() -#define DEBUGOUT(...) printf(__VA_ARGS__) -#define DEBUGSTR(str) printf(str) -#define DEBUGIN() (int) EOF - -#else -#define DEBUGINIT() Board_Debug_Init() -#define DEBUGOUT(...) printf(__VA_ARGS__) -#define DEBUGSTR(str) Board_UARTPutSTR(str) -#define DEBUGIN() Board_UARTGetChar() -#endif /* defined(DEBUG_SEMIHOSTING) */ - -#else -#define DEBUGINIT() -#define DEBUGOUT(...) -#define DEBUGSTR(str) -#define DEBUGIN() (int) EOF -#endif /* defined(DEBUG_ENABLE) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __BOARD_API_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/board/board_lpc.c b/bsp/nxp/lpc/lpc824/Libraries/common/board/board_lpc.c deleted file mode 100644 index 6f6c6906c69..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/board/board_lpc.c +++ /dev/null @@ -1,284 +0,0 @@ - -/* - * @brief NXP LPCXpresso LPC824 board file - * - * @note - * Copyright(C) NXP Semiconductors, 2013 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -// Must define _BOARD_C_ before ANY include -#define _BOARD_C_ - -#include "board_lpc.h" -#include "string.h" -#include -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -#define BOARD_LED_CNT 8 - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/* System oscillator rate and clock rate on the CLKIN pin */ -const uint32_t OscRateIn = MAIN_OSC_XTAL_FREQ_HZ; -const uint32_t ExtRateIn = EXT_CLOCK_IN_FREQ_HZ; - -/***************************************************************************** - * Private functions - ****************************************************************************/ -static void Board_Key_Init(void) -{ - int i; - LPC_IOCON_T *pIOCON = LPC_IOCON; - for (i = 0; i < BOARD_KEY_CNT; i++) { - Chip_GPIO_PinSetDIR(LPC_GPIO_PORT, 0, cs_keyBits[i], 0); - pIOCON->PIO0[cs_keyIoConNdce[i]] = 0x80; // weak pUp - } -} - -/* Initialize the LEDs on the NXP LPC824 LPCXpresso Board */ -static void Board_LED_Init(void) -{ - int i; - - for (i = 0; i < BOARD_LED_CNT; i++) { - Chip_GPIO_PinSetDIR(LPC_GPIO_PORT, 0, ledBits[i], 1); - Chip_GPIO_PinSetState(LPC_GPIO_PORT, 0, ledBits[i], true); - } -} - -uint32_t Board_Key_GetKeyDown(uint32_t keyNdx) -{ - LPC_GPIO_T *pGP = LPC_GPIO_PORT; - return pGP->W[0][cs_keyBits[keyNdx]] == 0 ? 1 : 0; -} - -/* Board Debug UART Initialisation function */ -STATIC void Board_UART_Init(void) -{ - /* Enable the clock to the Switch Matrix */ - Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM); - - /* Connect the TXD_O and RXD_I signals to port pins(P0.4, P0.0) */ - //Chip_SWM_DisableFixedPin(SWM_FIXED_XTALIN); - //Chip_SWM_DisableFixedPin(SWM_FIXED_XTALOUT); - - Chip_SWM_DisableFixedPin(SWM_FIXED_ACMP_I1); - Chip_SWM_DisableFixedPin(SWM_FIXED_ADC11); - - /* Enable UART Divider clock, divided by 1 */ - Chip_Clock_SetUARTClockDiv(1); - - /* Divided by 1 */ - if (DEBUG_UART == LPC_USART0) { - - Chip_SWM_MovablePinAssign(SWM_U0_TXD_O, 4); - Chip_SWM_MovablePinAssign(SWM_U0_RXD_I, 0); - } else if (DEBUG_UART == LPC_USART1) { - Chip_SWM_MovablePinAssign(SWM_U1_TXD_O, 4); - Chip_SWM_MovablePinAssign(SWM_U1_RXD_I, 0); - } else { - Chip_SWM_MovablePinAssign(SWM_U2_TXD_O, 4); - Chip_SWM_MovablePinAssign(SWM_U2_RXD_I, 0); - } - - /* Disable the clock to the Switch Matrix to save power */ - Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SWM); -} - -/* Initializes pin muxing for SPI1 interface - note that SystemInit() may - already setup your pin muxing at system startup */ -static void Init_SPI_PinMux(void) -{ - - Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM); - Chip_SWM_MovablePinAssign(SWM_SPI1_SSEL0_IO, 15); - Chip_SWM_MovablePinAssign(SWM_SPI1_SCK_IO, 24); - Chip_SWM_MovablePinAssign(SWM_SPI1_MISO_IO, 25); - Chip_SWM_MovablePinAssign(SWM_SPI1_MOSI_IO, 26); - Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SWM); - -} - -/* Initializes pin muxing for I2C interface */ -static void Init_I2C_PinMux(void) -{ - /* Enable the clock to the Switch Matrix */ - Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM); - Chip_SWM_EnableFixedPin(SWM_FIXED_I2C0_SDA); - Chip_SWM_EnableFixedPin(SWM_FIXED_I2C0_SCL); - - /* Enable Fast Mode Plus for I2C pins */ - Chip_IOCON_PinSetI2CMode(LPC_IOCON, IOCON_PIO10, PIN_I2CMODE_FASTPLUS); - Chip_IOCON_PinSetI2CMode(LPC_IOCON, IOCON_PIO11, PIN_I2CMODE_FASTPLUS); - - /* Disable the clock to the Switch Matrix to save power */ - Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SWM); -} -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Set the LED to the state of "On" */ -void Board_LED_Set(uint8_t LEDNumber, bool On) -{ - if (LEDNumber < BOARD_LED_CNT) { - Chip_GPIO_PinSetState(LPC_GPIO_PORT, 0, ledBits[LEDNumber], (bool) !On); - } -} - -/* Return the state of LEDNumber */ -bool Board_LED_Test(uint8_t LEDNumber) -{ - bool state = false; - - if (LEDNumber < BOARD_LED_CNT) { - state = (bool) !Chip_GPIO_PinGetState(LPC_GPIO_PORT, 0, ledBits[LEDNumber]); - } - - return state; -} - -/* Toggles the current state of a board LED */ -void Board_LED_Toggle(uint8_t LEDNumber) -{ - if (LEDNumber < BOARD_LED_CNT) { - Chip_GPIO_PinToggleState(LPC_GPIO_PORT, 0, ledBits[LEDNumber]); - } -} - -/* Classic implementation of itoa -- integer to ASCII */ -char *Board_itoa(int value, char *result, int base) -{ - char* ptr = result, *ptr1 = result, tmp_char; - int tmp_value; - - if (base < 2 || base > 36) { *result = '\0'; return result; } - do { - tmp_value = value; - value /= base; - *ptr++ = "zyxwvutsrqponmlkjihgfedcba9876543210123456789abcdefghijklmnopqrstuvwxyz" [35 + (tmp_value - value * base)]; - } while ( value ); - - if (tmp_value < 0) *ptr++ = '-'; - *ptr-- = '\0'; - while (ptr1 < ptr) { - tmp_char = *ptr; - *ptr--= *ptr1; - *ptr1++ = tmp_char; - } - return result; -} - -/* Sends a character on the UART */ -void Board_UARTPutChar(char ch) -{ -#if defined(DEBUG_UART) - Chip_UART_SendBlocking(DEBUG_UART, &ch, 1); -#endif -} - -void Board_UARTPutTextChar(char ch) -{ -#if defined(DEBUG_UART) - static char prevChar = 0; - if (ch == '\n' && prevChar != '\r') - { - prevChar = '\r'; - Chip_UART_SendBlocking(DEBUG_UART, &prevChar, 1); - Chip_UART_SendBlocking(DEBUG_UART, &ch, 1); - } else { - Chip_UART_SendBlocking(DEBUG_UART, &ch, 1); - prevChar = ch; - } -#endif -} - - -/* Gets a character from the UART, returns EOF if no character is ready */ -int Board_UARTGetChar(void) -{ -#if defined(DEBUG_UART) - uint8_t data; - - if (Chip_UART_ReadBlocking(DEBUG_UART, &data, 1) == 1) { - Board_UARTPutChar(data); // echo back the char - return (int) data; - } -#endif - return EOF; -} - -/* Outputs a string on the debug UART */ -void Board_UARTPutSTR(const char *str) -{ -#if defined(DEBUG_UART) - while (*str != '\0') { - Board_UARTPutTextChar(*str++); - } -#endif -} - -/* Initialize debug output via UART for board */ -void Board_Debug_Init(void) -{ -#if defined(DEBUG_UART) - Board_UART_Init(); - Chip_UART_Init(DEBUG_UART); - Chip_UART_ConfigData(DEBUG_UART, UART_CFG_DATALEN_8 | UART_CFG_PARITY_NONE | UART_CFG_STOPLEN_1); - Chip_Clock_SetUSARTNBaseClockRate((115200 * 6 * 16), true); - Chip_UART_SetBaud(DEBUG_UART, 115200); - Chip_UART_Enable(DEBUG_UART); - Chip_UART_TXEnable(DEBUG_UART); -#endif -} - -/* Set up and initialize all required blocks and functions related to the - board hardware */ -void Board_Init(void) -{ - LPC_SWM_T *pSWM = LPC_SWM; - /* Sets up DEBUG UART */ - #if defined(DEBUG_ENABLE) - DEBUGINIT(); - //pSWM->PINENABLE0 |= ~(1UL<PINENABLE0 |= 1UL< - * @{ - */ - -/** @defgroup LPCOPEN_8XX_BOARD_LPCXPRESSO_824_OPTIONS BOARD: LPC824 LPCXpresso board build options - * This board has options that configure its operation at build-time.
- * @{ - */ - -/** Define the frequency in Hz, of the main oscillator (from Xtal) - * Note that it only takes effect if main oscillator is selected as clock source - */ -#define MAIN_OSC_XTAL_FREQ_HZ 12000000 -/** Define the frequency in Hz, of the external clock input. - * Note that it only takes effect if external clock is selected as clock source - */ -#define EXT_CLOCK_IN_FREQ_HZ 0 - -//#define USE_IRC_AS_ROOT_CLOCK /*注释掉使用外部晶体 打开定义则是使用内部IRC*/ - -#define BOARD_LED_CNT 8 -#define BOARD_KEY_CNT 3 - -typedef enum _enum_boardKeys -{ - BOARD_KEY_0 = 0, - BOARD_KEY_1 = 1, - BOARD_KEY_2 = 2, -}enum_boardKeys; - -// define LED bits (bit <--> pin on port 0) only if in board.c file -#ifdef _BOARD_C_ -static const uint8_t ledBits[BOARD_LED_CNT] = {7, 13, 16, 17, 19, 27, 28, 18}; -static const uint8_t cs_keyBits[BOARD_KEY_CNT] = {12, 4 , 1}; -static const uint8_t cs_keyIoConNdce[BOARD_KEY_CNT] = {IOCON_PIO12, IOCON_PIO4, IOCON_PIO1}; -#endif - -/** Define DEBUG_ENABLE to enable IO via the DEBUGSTR, DEBUGOUT, and - DEBUGIN macros. If not defined, DEBUG* functions will be optimized - out of the code at build time. - */ -#define DEBUG_ENABLE - -/** Define DEBUG_SEMIHOSTING along with DEBUG_ENABLE to enable IO support - via semihosting. You may need to use a C library that supports - semihosting with this option. - */ -//#define DEBUG_SEMIHOSTING - -/** Board UART used for debug output and input using the DEBUG* macros. This - is also the port used for Board_UARTPutChar, Board_UARTGetChar, and - Board_UARTPutSTR functions. Although you can setup multiple UARTs here, - the board code only supoprts UART0 in the Board_UART_Init() fucntion, - so be sure to change it there too if not using UART0. - */ -#define DEBUG_UART LPC_USART1 - -/** - * @} - */ - -/* Board name */ -#define BOARD_NXP_LPCXPRESSO_824 - - -#include "board_api.h" - -#ifdef __cplusplus -} -#endif - -#endif /* __BOARD_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/chip/chip.h b/bsp/nxp/lpc/lpc824/Libraries/common/chip/chip.h deleted file mode 100644 index 27d6492a805..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/chip/chip.h +++ /dev/null @@ -1,230 +0,0 @@ -/* - * @brief LPC8xx basic chip inclusion file - * - * @note - * Copyright(C) NXP Semiconductors, 2013 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __CHIP_H_ -#define __CHIP_H_ - -#include "lpc_types.h" -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef CORE_M0PLUS -#error CORE_M0PLUS is not defined for the LPC8xx architecture -#error CORE_M0PLUS should be defined as part of your compiler define list -#endif - -#ifndef CHIP_LPC8XX -#error The LPC8XX Chip include path is used for this build, but -#error CHIP_LPC8XX is not defined! -#endif - -/** @defgroup PERIPH_8XX_BASE CHIP: LPC8xx Peripheral addresses and register set declarations - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/* Base addresses */ -#define LPC_FLASH_BASE (0x00000000UL) -#define LPC_RAM_BASE (0x10000000UL) -#define LPC_ROM_BASE (0x1FFF0000UL) -#define LPC_APB0_BASE (0x40000000UL) -#define LPC_AHB_BASE (0x50000000UL) - -/* APB0 peripherals */ -#define LPC_WWDT_BASE (0x40000000UL) -#define LPC_MRT_BASE (0x40004000UL) -#define LPC_WKT_BASE (0x40008000UL) -#define LPC_SWM_BASE (0x4000C000UL) -#define LPC_ADC_BASE (0x4001C000UL) /* Available only on LPC82x */ -#define LPC_PMU_BASE (0x40020000UL) -#define LPC_CMP_BASE (0x40024000UL) -#define LPC_DMATIRGMUX_BASE (0x40028000UL) /* Available only on LPC82x */ -#define LPC_INMUX_BASE (0x4002C000UL) /* Available only on LPC82x */ - -#define LPC_FMC_BASE (0x40040000UL) -#define LPC_IOCON_BASE (0x40044000UL) -#define LPC_SYSCTL_BASE (0x40048000UL) -#define LPC_I2C0_BASE (0x40050000UL) -#define LPC_I2C1_BASE (0x40054000UL) /* Available only on LPC82x */ -#define LPC_SPI0_BASE (0x40058000UL) -#define LPC_SPI1_BASE (0x4005C000UL) -#define LPC_USART0_BASE (0x40064000UL) -#define LPC_USART1_BASE (0x40068000UL) -#define LPC_USART2_BASE (0x4006C000UL) -#define LPC_I2C2_BASE (0x40070000UL) /* Available only on LPC82x */ -#define LPC_I2C3_BASE (0x40074000UL) /* Available only on LPC82x */ - -/* AHB peripherals */ -#define LPC_CRC_BASE (0x50000000UL) -#define LPC_SCT_BASE (0x50004000UL) -#define LPC_DMA_BASE (0x50008000UL) /* Available only on LPC82x */ - -#define LPC_GPIO_PORT_BASE (0xA0000000UL) -#define LPC_PIN_INT_BASE (0xA0004000UL) - -#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE) -#define LPC_SPI0 ((LPC_SPI_T *) LPC_SPI0_BASE) -#define LPC_SPI1 ((LPC_SPI_T *) LPC_SPI1_BASE) -#define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE) -#define LPC_USART1 ((LPC_USART_T *) LPC_USART1_BASE) -#define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE) -#define LPC_WKT ((LPC_WKT_T *) LPC_WKT_BASE) -#define LPC_PMU ((LPC_PMU_T *) LPC_PMU_BASE) -#define LPC_CRC ((LPC_CRC_T *) LPC_CRC_BASE) -#define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE) -#define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE) -#define LPC_PININT ((LPC_PININT_T *) LPC_PIN_INT_BASE) -#define LPC_IOCON ((LPC_IOCON_T *) LPC_IOCON_BASE) -#define LPC_SWM ((LPC_SWM_T *) LPC_SWM_BASE) -#define LPC_SYSCTL ((LPC_SYSCTL_T *) LPC_SYSCTL_BASE) -#define LPC_CMP ((LPC_CMP_T *) LPC_CMP_BASE) -#define LPC_FMC ((LPC_FMC_T *) LPC_FMC_BASE) -#define LPC_MRT ((LPC_MRT_T *) LPC_MRT_BASE) -#define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE) - -#ifdef CHIP_LPC82X -/* Peripherals available only on LPC82x */ -#define LPC_ADC ((LPC_ADC_T *) LPC_ADC_BASE) -#define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE) -#define LPC_I2C2 ((LPC_I2C_T *) LPC_I2C2_BASE) -#define LPC_I2C3 ((LPC_I2C_T *) LPC_I2C3_BASE) -#define LPC_DMA ((LPC_DMA_T *) LPC_DMA_BASE) -#define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_T *) LPC_DMATIRGMUX_BASE) -#define LPC_INMUX ((LPC_INMUX_T *) LPC_INMUX_BASE) -#endif - -/* Base address Alias list */ -#define LPC_I2C_BASE LPC_I2C0_BASE -#define LPC_I2C LPC_I2C0 -#define LPC_SYSCON LPC_SYSCTL - -/* IRQ Handler alias list */ -#ifdef CHIP_LPC82X -#define I2C_IRQHandler I2C0_IRQHandler -#define PININT0_IRQHandler PIN_INT0_IRQHandler -#define PININT1_IRQHandler PIN_INT1_IRQHandler -#define PININT2_IRQHandler PIN_INT2_IRQHandler -#define PININT3_IRQHandler PIN_INT3_IRQHandler -#define PININT4_IRQHandler PIN_INT4_IRQHandler -#define PININT5_IRQHandler PIN_INT5_IRQHandler -#define PININT6_IRQHandler PIN_INT6_IRQHandler -#define PININT7_IRQHandler PIN_INT7_IRQHandler -#endif - -/** - * @} - */ - -/** @ingroup CHIP_8XX_DRIVER_OPTIONS - * @{ - */ - -/** - * @brief System oscillator rate - * This value is defined externally to the chip layer and contains - * the value in Hz for the external oscillator for the board. If using the - * internal oscillator, this rate can be 0. - */ -extern const uint32_t OscRateIn; - -/** - * @brief Clock rate on the CLKIN pin - * This value is defined externally to the chip layer and contains - * the value in Hz for the CLKIN pin for the board. If this pin isn't used, - * this rate can be 0. - */ -extern const uint32_t ExtRateIn; - -/** - * @} - */ - -/* Include order is important! */ -#include "syscon_8xx.h" -#include "clock_8xx.h" -#include "fmc_8xx.h" -#include "ioswm_8xx.h" - -#ifndef _CHIP_COMMON_ -#include "../../peri_driver/peri_driver.h" -#endif - -/** @defgroup SUPPORT_8XX_FUNC CHIP: LPC8xx support functions - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/** - * @brief Current system clock rate, mainly used for sysTick - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Update system core clock rate, should be called if the - * system has a clock rate change - * @return None - */ -void SystemCoreClockUpdate(void); - -/** - * @brief Set up and initialize hardware prior to call to main() - * @return None - * @note Chip_SystemInit() is called prior to the application and sets up - * system clocking prior to the application starting. - */ -void Chip_SystemInit(void); - -/** - * @brief Clock and PLL initialization based on the external oscillator - * @return None - * @note This function assumes an external crystal oscillator - * frequency of 12MHz. - */ -void Chip_SetupXtalClocking(void); - -/** - * @brief Clock and PLL initialization based on the internal oscillator - * @return None - */ -void Chip_SetupIrcClocking(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CHIP_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/chip/clock_8xx.c b/bsp/nxp/lpc/lpc824/Libraries/common/chip/clock_8xx.c deleted file mode 100644 index b861b4041e2..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/chip/clock_8xx.c +++ /dev/null @@ -1,468 +0,0 @@ -/* - * @brief LPC8xx clock driver - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ -#define _CHIP_COMMON_ -#include "chip.h" - - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/* Inprecise clock rates for the watchdog oscillator */ -static const uint32_t wdtOSCRate[WDTLFO_OSC_4_60 + 1] = { - 0, /* WDT_OSC_ILLEGAL */ - 600000, /* WDT_OSC_0_60 */ - 1050000, /* WDT_OSC_1_05 */ - 1400000, /* WDT_OSC_1_40 */ - 1750000, /* WDT_OSC_1_75 */ - 2100000, /* WDT_OSC_2_10 */ - 2400000, /* WDT_OSC_2_40 */ - 2700000, /* WDT_OSC_2_70 */ - 3000000, /* WDT_OSC_3_00 */ - 3250000, /* WDT_OSC_3_25 */ - 3500000, /* WDT_OSC_3_50 */ - 3750000, /* WDT_OSC_3_75 */ - 4000000, /* WDT_OSC_4_00 */ - 4200000, /* WDT_OSC_4_20 */ - 4400000, /* WDT_OSC_4_40 */ - 4600000 /* WDT_OSC_4_60 */ -}; - - typedef struct { - uint16_t freq_main; // main clock frequency in MHz - uint16_t freq_sys; // system (CPU) clock frequency in MHz - uint16_t freq_fcco; // FCCO clock frequency in MHz - uint16_t msel; // MSEL (pre-decremented) - uint16_t psel; // PSEL (pre-decremented) - uint16_t divider; // SYSAHBCLKDIV -} LPC_8XX_PLL_T; - -/* - * This table contains all useful PLL configurations - * for "integer" MHZ (e.g. 1MHz, 2MHz, etc.) frequencies. - * - * This table has two inputs: - * - freq_main: This is the main frequency. - * - freq_sys: This is the system (CPU) frequency. - * These are used to select which table entry to use. - * - * There are many ways to get some frequencies. For example, - * there are eight ways to make the CPU run at 12MHZ. If the peripheral bus - * needs to run very fast, it's possible to set the main clock - * up to 96MHz. If low power is a requirement, it's possible to set the main - * clock to 12MHz. - * - * All the rest of the table entries are outputs. - * - freq_fcco is simply an FYI value. It is not used for programming. - * - MSEL / PSEL / divider are used to program the PLL. - */ -static const LPC_8XX_PLL_T config_tab[] = { - { 12, 12, 192, 0, 3, 1 }, // 12.0000MHz - { 12, 6, 192, 0, 3, 2 }, // 6.0000MHz - { 12, 4, 192, 0, 3, 3 }, // 4.0000MHz - { 12, 3, 192, 0, 3, 4 }, // 3.0000MHz - { 12, 2, 192, 0, 3, 6 }, // 2.0000MHz - { 12, 1, 192, 0, 3, 12 }, // 1.0000MHz - { 24, 24, 192, 1, 2, 1 }, // 24.0000MHz - { 24, 12, 192, 1, 2, 2 }, // 12.0000MHz - { 24, 8, 192, 1, 2, 3 }, // 8.0000MHz - { 24, 6, 192, 1, 2, 4 }, // 6.0000MHz - { 24, 4, 192, 1, 2, 6 }, // 4.0000MHz - { 24, 3, 192, 1, 2, 8 }, // 3.0000MHz - { 24, 2, 192, 1, 2, 12 }, // 2.0000MHz - { 24, 1, 192, 1, 2, 24 }, // 1.0000MHz - { 36, 18, 288, 2, 2, 2 }, // 18.0000MHz - { 36, 12, 288, 2, 2, 3 }, // 12.0000MHz - { 36, 9, 288, 2, 2, 4 }, // 9.0000MHz - { 36, 6, 288, 2, 2, 6 }, // 6.0000MHz - { 36, 4, 288, 2, 2, 9 }, // 4.0000MHz - { 36, 3, 288, 2, 2, 12 }, // 3.0000MHz - { 36, 2, 288, 2, 2, 18 }, // 2.0000MHz - { 36, 1, 288, 2, 2, 36 }, // 1.0000MHz - { 48, 24, 192, 3, 1, 2 }, // 24.0000MHz - { 48, 16, 192, 3, 1, 3 }, // 16.0000MHz - { 48, 12, 192, 3, 1, 4 }, // 12.0000MHz - { 48, 8, 192, 3, 1, 6 }, // 8.0000MHz - { 48, 6, 192, 3, 1, 8 }, // 6.0000MHz - { 48, 4, 192, 3, 1, 12 }, // 4.0000MHz - { 48, 3, 192, 3, 1, 16 }, // 3.0000MHz - { 48, 2, 192, 3, 1, 24 }, // 2.0000MHz - { 48, 1, 192, 3, 1, 48 }, // 1.0000MHz - { 60, 30, 240, 4, 1, 2 }, // 30.0000MHz - { 60, 20, 240, 4, 1, 3 }, // 20.0000MHz - { 60, 15, 240, 4, 1, 4 }, // 15.0000MHz - { 60, 12, 240, 4, 1, 5 }, // 12.0000MHz - { 60, 10, 240, 4, 1, 6 }, // 10.0000MHz - { 60, 6, 240, 4, 1, 10 }, // 6.0000MHz - { 60, 5, 240, 4, 1, 12 }, // 5.0000MHz - { 60, 4, 240, 4, 1, 15 }, // 4.0000MHz - { 60, 3, 240, 4, 1, 20 }, // 3.0000MHz - { 60, 2, 240, 4, 1, 30 }, // 2.0000MHz - { 60, 1, 240, 4, 1, 60 }, // 1.0000MHz - { 72, 24, 288, 5, 1, 3 }, // 24.0000MHz - { 72, 18, 288, 5, 1, 4 }, // 18.0000MHz - { 72, 12, 288, 5, 1, 6 }, // 12.0000MHz - { 72, 9, 288, 5, 1, 8 }, // 9.0000MHz - { 72, 8, 288, 5, 1, 9 }, // 8.0000MHz - { 72, 6, 288, 5, 1, 12 }, // 6.0000MHz - { 72, 4, 288, 5, 1, 18 }, // 4.0000MHz - { 72, 3, 288, 5, 1, 24 }, // 3.0000MHz - { 72, 2, 288, 5, 1, 36 }, // 2.0000MHz - { 72, 1, 288, 5, 1, 72 }, // 1.0000MHz - { 84, 28, 168, 6, 0, 3 }, // 28.0000MHz - { 84, 21, 168, 6, 0, 4 }, // 21.0000MHz - { 84, 14, 168, 6, 0, 6 }, // 14.0000MHz - { 84, 12, 168, 6, 0, 7 }, // 12.0000MHz - { 84, 7, 168, 6, 0, 12 }, // 7.0000MHz - { 84, 6, 168, 6, 0, 14 }, // 6.0000MHz - { 84, 4, 168, 6, 0, 21 }, // 4.0000MHz - { 84, 3, 168, 6, 0, 28 }, // 3.0000MHz - { 84, 2, 168, 6, 0, 42 }, // 2.0000MHz - { 84, 1, 168, 6, 0, 84 }, // 1.0000MHz - { 96, 24, 192, 7, 0, 4 }, // 24.0000MHz - { 96, 16, 192, 7, 0, 6 }, // 16.0000MHz - { 96, 12, 192, 7, 0, 8 }, // 12.0000MHz - { 96, 8, 192, 7, 0, 12 }, // 8.0000MHz - { 96, 6, 192, 7, 0, 16 }, // 6.0000MHz - { 96, 4, 192, 7, 0, 24 }, // 4.0000MHz - { 96, 3, 192, 7, 0, 32 }, // 3.0000MHz - { 96, 2, 192, 7, 0, 48 }, // 2.0000MHz - { 96, 1, 192, 7, 0, 96 }, // 1.0000MHz -}; -static const uint16_t config_tab_ct = sizeof(config_tab) / sizeof(LPC_8XX_PLL_T); -static uint16_t config_tab_idx = 0; -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ -/* System Clock Frequency (Core Clock) */ -uint32_t SystemCoreClock; - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -static void pll_config(const LPC_8XX_PLL_T* pll_cfg) -{ - Chip_SYSCTL_PowerUp(SYSCTL_SLPWAKE_IRC_PD); /* turn on the IRC by clearing the power down bit */ - Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_IRC); /* select PLL input to be IRC */ - Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_IRC); - Chip_FMC_SetFLASHAccess(FLASHTIM_30MHZ_CPU); /* setup FLASH access to 2 clocks (up to 30MHz) */ - Chip_SYSCTL_PowerDown(SYSCTL_SLPWAKE_SYSPLL_PD); /* power down PLL to change the PLL divider ratio */ - Chip_Clock_SetupSystemPLL(pll_cfg->msel, pll_cfg->psel); /* configure the PLL */ - Chip_SYSCTL_PowerUp(SYSCTL_SLPWAKE_SYSPLL_PD); /* turn on the PLL by clearing the power down bit */ - while (!Chip_Clock_IsSystemPLLLocked()) {} /* wait for PLL to lock */ - Chip_Clock_SetSysClockDiv(pll_cfg->divider); /* load the divider */ - Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT); /* enable the new Frequency */ -} - -/* Compute a WDT or LFO rate */ -static uint32_t Chip_Clock_GetWDTLFORate(uint32_t reg) -{ - uint32_t div; - CHIP_WDTLFO_OSC_T clk; - - /* Get WDT oscillator settings */ - clk = (CHIP_WDTLFO_OSC_T) ((reg >> 5) & 0xF); - div = reg & 0x1F; - - /* Compute clock rate and divided by divde value */ - return wdtOSCRate[clk] / ((div + 1) << 1); -} - -/* Compute PLL frequency */ -static uint32_t Chip_Clock_GetPLLFreq(uint32_t PLLReg, uint32_t inputRate) -{ - uint32_t m_val = ((PLLReg & 0x1F) + 1); - - return (inputRate * m_val); -} - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -bool Chip_IRC_SetFreq(uint32_t main, uint32_t sys) -{ - uint16_t freq_m = main/1000000; /* main frequency in MHz */ - uint16_t freq_s = sys/1000000; /* system frequency in MHz */ - bool found = false; /* frequencies found */ - uint32_t i = 0; - - if (freq_s > 30) /* if system frequency is higher than 30MHz... */ - return false; /* ...don't attempt to set it */ - if (freq_m > 96) /* if main frequency is higher than 96MHz... */ - return false; /* ...don't attempt to set it */ - - for (i=0; iset_pll(cmd, resp); /* Attempt to set the PLL */ - - while (resp[0] != PLL_CMD_SUCCESS) {} /* Dead loop on fail */ -} -#else - -#endif - -/* Update system core clock rate, should be called if the system has - a clock rate change */ -void SystemCoreClockUpdate(void) -{ - /* CPU core speed */ - SystemCoreClock = Chip_Clock_GetSystemClockRate(); -} -/* Set System PLL clock source */ -void Chip_Clock_SetSystemPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src) -{ - LPC_SYSCTL->SYSPLLCLKSEL = (uint32_t) src; - - /* sequnce a 0 followed by 1 to update PLL source selection */ - LPC_SYSCTL->SYSPLLCLKUEN = 0; - LPC_SYSCTL->SYSPLLCLKUEN = 1; -} - -/* Bypass System Oscillator and set oscillator frequency range */ -void Chip_Clock_SetPLLBypass(bool bypass, bool highfr) -{ - uint32_t ctrl = 0; - - if (bypass) { - ctrl |= (1 << 0); - } - if (highfr) { - ctrl |= (1 << 1); - } - - LPC_SYSCTL->SYSOSCCTRL = ctrl; -} - -/* Set main system clock source */ -void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src) -{ - LPC_SYSCTL->MAINCLKSEL = (uint32_t) src; - - /* sequnce a 0 followed by 1 to update MAINCLK source selection */ - LPC_SYSCTL->MAINCLKUEN = 0; - LPC_SYSCTL->MAINCLKUEN = 1; -} - -/* Set CLKOUT clock source and divider */ -void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div) -{ - LPC_SYSCTL->CLKOUTSEL = (uint32_t) src; - - /* sequnce a 0 followed by 1 to update CLKOUT source selection */ - LPC_SYSCTL->CLKOUTUEN = 0; - LPC_SYSCTL->CLKOUTUEN = 1; - LPC_SYSCTL->CLKOUTDIV = div; -} - -/* Return estimated watchdog oscillator rate */ -uint32_t Chip_Clock_GetWDTOSCRate(void) -{ - return Chip_Clock_GetWDTLFORate(LPC_SYSCTL->WDTOSCCTRL & ~SYSCTL_WDTOSCCTRL_RESERVED); -} - -/* Return System PLL input clock rate */ -uint32_t Chip_Clock_GetSystemPLLInClockRate(void) -{ - uint32_t clkRate; - - switch ((CHIP_SYSCTL_PLLCLKSRC_T) (LPC_SYSCTL->SYSPLLCLKSEL & 0x3)) { - case SYSCTL_PLLCLKSRC_IRC: - clkRate = Chip_Clock_GetIntOscRate(); - break; - - case SYSCTL_PLLCLKSRC_SYSOSC: - clkRate = Chip_Clock_GetMainOscRate(); - break; - - case SYSCTL_PLLCLKSRC_EXT_CLKIN: - clkRate = Chip_Clock_GetExtClockInRate(); - break; - - default: - clkRate = 0; - } - - return clkRate; -} - -/* Return System PLL output clock rate */ -uint32_t Chip_Clock_GetSystemPLLOutClockRate(void) -{ - return Chip_Clock_GetPLLFreq((LPC_SYSCTL->SYSPLLCTRL & ~SYSCTL_SYSPLLCTRL_RESERVED), - Chip_Clock_GetSystemPLLInClockRate()); -} - -/* Return main clock rate */ -uint32_t Chip_Clock_GetMainClockRate(void) -{ - uint32_t clkRate = 0; - - switch ((CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL & 0x3)) { - case SYSCTL_MAINCLKSRC_IRC: - clkRate = Chip_Clock_GetIntOscRate(); - break; - - case SYSCTL_MAINCLKSRC_PLLIN: - clkRate = Chip_Clock_GetSystemPLLInClockRate(); - break; - - case SYSCTL_MAINCLKSRC_WDTOSC: - clkRate = Chip_Clock_GetWDTOSCRate(); - break; - - case SYSCTL_MAINCLKSRC_PLLOUT: - clkRate = Chip_Clock_GetSystemPLLOutClockRate(); - break; - } - - return clkRate; -} - -/* Return system clock rate */ -uint32_t Chip_Clock_GetSystemClockRate(void) -{ - /* No point in checking for divide by 0 */ - return Chip_Clock_GetMainClockRate() / (LPC_SYSCTL->SYSAHBCLKDIV & ~SYSCTL_SYSAHBCLKDIV_RESERVED); -} - -/* Get USART 0/1/2 UART base rate */ -uint32_t Chip_Clock_GetUSARTNBaseClockRate(void) -{ - uint64_t inclk; - uint32_t div; - - div = (uint32_t) Chip_Clock_GetUARTClockDiv(); - if (div == 0) { - /* Divider is 0 so UART clock is disabled */ - inclk = 0; - } - else { - uint32_t mult, divf; - - /* Input clock into FRG block is the divided main system clock */ - inclk = (uint64_t) (Chip_Clock_GetMainClockRate() / div); - - divf = Chip_SYSCTL_GetUSARTFRGDivider(); - if (divf == 0xFF) { - /* Fractional part is enabled, get multiplier */ - mult = (uint32_t) Chip_SYSCTL_GetUSARTFRGMultiplier(); - - /* Get fractional error */ - inclk = (inclk * 256) / (uint64_t) (256 + mult); - } - } - - return (uint32_t) inclk; -} - -/* Set USART 0/1/2 UART base rate */ -uint32_t Chip_Clock_SetUSARTNBaseClockRate(uint32_t rate, bool fEnable) -{ - uint32_t div, inclk; - - /* Input clock into FRG block is the main system clock */ - inclk = Chip_Clock_GetMainClockRate(); - - /* Get integer divider for coarse rate */ - div = inclk / rate; - if (div == 0) { - div = 1; - } - - /* Approximated rate with only integer divider */ - Chip_Clock_SetUARTClockDiv((uint8_t) div); - - if (fEnable) { - uint32_t uart_fra_multiplier; - - /* Reset FRG */ - Chip_SYSCTL_PeriphReset(RESET_UARTFBRG); - - /* Enable fractional divider */ - Chip_SYSCTL_SetUSARTFRGDivider(0xFF); - - /* Compute the fractional divisor (the lower byte is the - fractional portion) */ - uart_fra_multiplier = ((inclk / div) * 256) / rate; - - /* ...just the fractional portion (the lower byte) */ - Chip_SYSCTL_SetUSARTFRGMultiplier((uint8_t) uart_fra_multiplier); - } - else { - /* Disable fractional generator and use integer divider only */ - Chip_SYSCTL_SetUSARTFRGDivider(0); - } - - return Chip_Clock_GetUSARTNBaseClockRate(); -} - -/* Get the IOCONCLKDIV clock rate */ -uint32_t Chip_Clock_GetIOCONCLKDIVClockRate(CHIP_PIN_CLKDIV_T reg) -{ - uint32_t div = LPC_SYSCTL->IOCONCLKDIV[reg] & ~SYSCTL_IOCONCLKDIV_RESERVED; - uint32_t main_clk = Chip_Clock_GetMainClockRate(); - - return (div == 0) ? 0 : (main_clk / div); -} - -void Chip_Clock_SetIOCONCLKDIV(CHIP_PIN_CLKDIV_T reg, uint8_t div) -{ - int t_reg = IOCONCLK_MAX-reg; - LPC_SYSCTL->IOCONCLKDIV[t_reg] = div; -} diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/chip/clock_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/common/chip/clock_8xx.h deleted file mode 100644 index 1b1c0c12e2c..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/chip/clock_8xx.h +++ /dev/null @@ -1,453 +0,0 @@ -/* - * @brief LPC8xx clock driver - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __CLOCK_8XX_H_ -#define __CLOCK_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup CLOCK_8XX CHIP: LPC8xx Clock Driver - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/* Internal oscillator frequency */ -#define SYSCTL_IRC_FREQ (12000000) -#ifndef MAX_CLOCK_FREQ -#define MAX_CLOCK_FREQ (30000000) -#endif - -/** - * Clock sources for system and USB PLLs - */ -typedef enum CHIP_SYSCTL_PLLCLKSRC { - SYSCTL_PLLCLKSRC_IRC = 0, /*!< Internal oscillator */ - SYSCTL_PLLCLKSRC_SYSOSC, /*!< Crystal (system) oscillator */ - SYSCTL_PLLCLKSRC_RESERVED, - SYSCTL_PLLCLKSRC_EXT_CLKIN, /*!< External clock input */ -} CHIP_SYSCTL_PLLCLKSRC_T; - -/** - * Watchdog oscillator analog output frequency selection - * values enum (plus or minus 40%) - */ -typedef enum CHIP_WDTLFO_OSC { - WDTLFO_OSC_ILLEGAL, - WDTLFO_OSC_0_60, /*!< 0.6 MHz watchdog/LFO rate */ - WDTLFO_OSC_1_05, /*!< 1.05 MHz watchdog/LFO rate */ - WDTLFO_OSC_1_40, /*!< 1.4 MHz watchdog/LFO rate */ - WDTLFO_OSC_1_75, /*!< 1.75 MHz watchdog/LFO rate */ - WDTLFO_OSC_2_10, /*!< 2.1 MHz watchdog/LFO rate */ - WDTLFO_OSC_2_40, /*!< 2.4 MHz watchdog/LFO rate */ - WDTLFO_OSC_2_70, /*!< 2.7 MHz watchdog/LFO rate */ - WDTLFO_OSC_3_00, /*!< 3.0 MHz watchdog/LFO rate */ - WDTLFO_OSC_3_25, /*!< 3.25 MHz watchdog/LFO rate */ - WDTLFO_OSC_3_50, /*!< 3.5 MHz watchdog/LFO rate */ - WDTLFO_OSC_3_75, /*!< 3.75 MHz watchdog/LFO rate */ - WDTLFO_OSC_4_00, /*!< 4.0 MHz watchdog/LFO rate */ - WDTLFO_OSC_4_20, /*!< 4.2 MHz watchdog/LFO rate */ - WDTLFO_OSC_4_40, /*!< 4.4 MHz watchdog/LFO rate */ - WDTLFO_OSC_4_60 /*!< 4.6 MHz watchdog/LFO rate */ -} CHIP_WDTLFO_OSC_T; - -/** - * Clock sources for main system clock - */ -typedef enum CHIP_SYSCTL_MAINCLKSRC { - SYSCTL_MAINCLKSRC_IRC = 0, /*!< Internal oscillator */ - SYSCTL_MAINCLKSRC_PLLIN, /*!< System PLL input */ - SYSCTL_MAINCLKSRC_WDTOSC, /*!< Watchdog oscillator rate */ - SYSCTL_MAINCLKSRC_PLLOUT, /*!< System PLL output */ -} CHIP_SYSCTL_MAINCLKSRC_T; - -/** - * System and peripheral clocks enum - */ -typedef enum CHIP_SYSCTL_CLOCK { - SYSCTL_CLOCK_SYS = 0, /*!< System clock */ - SYSCTL_CLOCK_ROM, /*!< ROM clock */ - SYSCTL_CLOCK_RAM, /*!< RAM clock */ - SYSCTL_CLOCK_FLASHREG, /*!< FLASH register interface clock */ - SYSCTL_CLOCK_FLASH, /*!< FLASH array access clock */ - SYSCTL_CLOCK_I2C0, /*!< I2C0 clock */ - SYSCTL_CLOCK_GPIO, /*!< GPIO clock */ - SYSCTL_CLOCK_SWM, /*!< Switch matrix clock */ - SYSCTL_CLOCK_SCT, /*!< State configurable timer clock */ - SYSCTL_CLOCK_WKT, /*!< Self wake-up timer clock */ - SYSCTL_CLOCK_MRT, /*!< Multi-rate timer clock */ - SYSCTL_CLOCK_SPI0, /*!< SPI0 clock */ - SYSCTL_CLOCK_SPI1, /*!< SPI01 clock */ - SYSCTL_CLOCK_CRC, /*!< CRC clock */ - SYSCTL_CLOCK_UART0, /*!< UART0 clock */ - SYSCTL_CLOCK_UART1, /*!< UART1 clock */ - SYSCTL_CLOCK_UART2, /*!< UART2 clock */ - SYSCTL_CLOCK_WWDT, /*!< Watchdog clock */ - SYSCTL_CLOCK_IOCON, /*!< IOCON clock */ - SYSCTL_CLOCK_ACOMP, /*!< Analog comparator clock */ - - /* LPC82x Specific Clocks */ - SYSCTL_CLOCK_I2C1 = 21, /*!< I2C1 Clock */ - SYSCTL_CLOCK_I2C2, /*!< I2C2 Clock */ - SYSCTL_CLOCK_I2C3, /*!< I2C3 Clock */ - SYSCTL_CLOCK_ADC, /*!< 12-Bit ADC Clock */ - SYSCTL_CLOCK_MTB = 26, /*!< Macro Trace Buffer [USED FOR DEBUGGING] */ - SYSCTL_CLOCK_DMA = 29, /*!< DMA Clock */ -} CHIP_SYSCTL_CLOCK_T; - -/* Clock name alias */ -#define SYSCTL_CLOCK_I2C SYSCTL_CLOCK_I2C0 -#define SYSCTL_CLOCK_ACMP SYSCTL_CLOCK_ACOMP - -/** - * Clock sources for CLKOUT - */ -typedef enum CHIP_SYSCTL_CLKOUTSRC { - SYSCTL_CLKOUTSRC_IRC = 0, /*!< Internal oscillator for CLKOUT */ - SYSCTL_CLKOUTSRC_SYSOSC, /*!< System oscillator for CLKOUT */ - SYSCTL_CLKOUTSRC_WDTOSC, /*!< Watchdog oscillator for CLKOUT */ - SYSCTL_CLKOUTSRC_MAINSYSCLK, /*!< Main system clock for CLKOUT */ -} CHIP_SYSCTL_CLKOUTSRC_T; - -/** - * @brief Set System PLL divider values - * @param msel : PLL feedback divider value - * @param psel : PLL post divider value - * @return Nothing - * @note See the user manual for how to setup the PLL - */ -STATIC INLINE void Chip_Clock_SetupSystemPLL(uint8_t msel, uint8_t psel) -{ - LPC_SYSCTL->SYSPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5); -} - -/** - * @brief Read System PLL status - * @return true if the PLL is locked, false if not locked - */ -STATIC INLINE bool Chip_Clock_IsSystemPLLLocked(void) -{ - return (bool) ((LPC_SYSCTL->SYSPLLSTAT & 1) != 0); -} - -/** - * @brief Setup Watchdog oscillator rate and divider - * @param wdtclk : Selected watchdog clock rate - * @param div : Watchdog divider value, even value between 2 and 64 - * @return Nothing - * @note Watchdog rate = selected rate divided by divider rate - */ -STATIC INLINE void Chip_Clock_SetWDTOSC(CHIP_WDTLFO_OSC_T wdtclk, uint8_t div) -{ - LPC_SYSCTL->WDTOSCCTRL = (((uint32_t) wdtclk) << 5) | ((div >> 1) - 1); -} - -/** - * @brief Returns the main clock source - * @return Main clock source - */ -STATIC INLINE CHIP_SYSCTL_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void) -{ - return (CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL & ~SYSCTL_MAINCLKSEL_RESERVED); -} - -/** - * @brief Set system clock divider - * @param div : divider for system clock - * @return Nothing - * @note Use 0 to disable, or a divider value of 1 to 255. The system clock - * rate is the main system clock divided by this value. - */ -STATIC INLINE void Chip_Clock_SetSysClockDiv(uint32_t div) -{ - LPC_SYSCTL->SYSAHBCLKDIV = div; -} - -/** - * @brief Enable system or peripheral clock - * @param clk : Clock to enable - * @return Nothing - */ -STATIC INLINE void Chip_Clock_EnablePeriphClock(CHIP_SYSCTL_CLOCK_T clk) -{ - LPC_SYSCTL->SYSAHBCLKCTRL = (1 << clk) | (LPC_SYSCTL->SYSAHBCLKCTRL & ~SYSCTL_SYSAHBCLKCTRL_RESERVED); -} - -/** - * @brief Disable system or peripheral clock - * @param clk : Clock to disable - * @return Nothing - */ -STATIC INLINE void Chip_Clock_DisablePeriphClock(CHIP_SYSCTL_CLOCK_T clk) -{ - LPC_SYSCTL->SYSAHBCLKCTRL &= ~((1 << clk) | SYSCTL_SYSAHBCLKCTRL_RESERVED); -} - -/** - * @brief Set UART divider clock - * @param div : divider for UART clock - * @return Nothing - * @note Use 0 to disable, or a divider value of 1 to 255. The UART clock - * rate is the main system clock divided by this value. - */ -STATIC INLINE void Chip_Clock_SetUARTClockDiv(uint32_t div) -{ - LPC_SYSCTL->UARTCLKDIV = div; -} - -/** - * @brief Return UART divider - * @return divider for UART clock - * @note A value of 0 means the clock is disabled. - */ -STATIC INLINE uint32_t Chip_Clock_GetUARTClockDiv(void) -{ - return LPC_SYSCTL->UARTCLKDIV & ~SYSCTL_UARTCLKDIV_RESERVED; -} - -/** - * @brief Set The USART Fractional Generator Divider - * @param div : Fractional Generator Divider value, should be 0xFF - * @return Nothing - */ -STATIC INLINE void Chip_SYSCTL_SetUSARTFRGDivider(uint8_t div) -{ - LPC_SYSCTL->UARTFRGDIV = (uint32_t) div; -} - -/** - * @brief Get The USART Fractional Generator Divider - * @return Value of USART Fractional Generator Divider - */ -STATIC INLINE uint32_t Chip_SYSCTL_GetUSARTFRGDivider(void) -{ - return LPC_SYSCTL->UARTFRGDIV & ~SYSCTL_UARTFRGDIV_RESERVED; -} - -/** - * @brief Set The USART Fractional Generator Multiplier - * @param mult : An 8-bit value (0-255) U_PCLK = UARTCLKDIV/(1 + MULT/256) - * @return Nothing - */ -STATIC INLINE void Chip_SYSCTL_SetUSARTFRGMultiplier(uint8_t mult) -{ - LPC_SYSCTL->UARTFRGMULT = (uint32_t) mult; -} - -/** - * @brief Get The USART Fractional Generator Multiplier - * @return Value of USART Fractional Generator Multiplier - */ -STATIC INLINE uint32_t Chip_SYSCTL_GetUSARTFRGMultiplier(void) -{ - return LPC_SYSCTL->UARTFRGMULT & ~SYSCTL_UARTFRGMULT_RESERVED; -} - -/** - * @brief Set USART 0/1/2 UART base rate (up to main clock rate) - * @param rate : Desired rate for fractional divider/multipler output - * @param fEnable : true to use fractional clocking, false for integer clocking - * @return Actual rate generated - * @note USARTs 0 - 2 use the same base clock for their baud rate - * basis. This function is used to generate that clock, while the - * UART driver's SetBaud functions will attempt to get the closest - * baud rate from this base clock without altering it. This needs - * to be setup prior to individual UART setup.
- * UARTs need a base clock 16x faster than the baud rate, so if you - * need a 115.2Kbps baud rate, you will need a clock rate of at - * least (115.2K * 16). The UART base clock is generated from the - * main system clock, so fractional clocking may be the only - * possible choice when using a low main system clock frequency. - * Do not alter the FRGCLKDIV register after this call. - */ -uint32_t Chip_Clock_SetUSARTNBaseClockRate(uint32_t rate, bool fEnable); - -/** - * @brief Get USART 0/1/2 UART base rate - * @return USART 0/1/2 UART base rate - */ -uint32_t Chip_Clock_GetUSARTNBaseClockRate(void); - -/** - * @brief Returns the main oscillator clock rate - * @return main oscillator clock rate - */ -STATIC INLINE uint32_t Chip_Clock_GetMainOscRate(void) -{ - return OscRateIn; -} - -/** - * @brief Returns the internal oscillator (IRC) clock rate - * @return internal oscillator (IRC) clock rate - */ -STATIC INLINE uint32_t Chip_Clock_GetIntOscRate(void) -{ - return SYSCTL_IRC_FREQ; -} - -/** - * @brief Returns the external clock input rate - * @return External clock input rate - */ -STATIC INLINE uint32_t Chip_Clock_GetExtClockInRate(void) -{ - return ExtRateIn; -} - -/** - * @brief Set System PLL clock source - * @param src : Clock source for system PLL - * @return Nothing - * @note This function will also toggle the clock source update register - * to update the clock source - */ -void Chip_Clock_SetSystemPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src); - -/** - * @brief Bypass System Oscillator and set oscillator frequency range - * @param bypass : Flag to bypass oscillator - * @param highfr : Flag to set oscillator range from 15-25 MHz - * @return Nothing - * @note Sets the PLL input to bypass the oscillator. This would be - * used if an external clock that is not an oscillator is attached - * to the XTALIN pin. - */ -void Chip_Clock_SetPLLBypass(bool bypass, bool highfr); - -/** - * @brief Set main system clock source - * @param src : Clock source for main system - * @return Nothing - * @note This function will also toggle the clock source update register - * to update the clock source - */ -void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src); - -/** - * @brief Set CLKOUT clock source and divider - * @param src : Clock source for CLKOUT - * @param div : divider for CLKOUT clock - * @return Nothing - * @note Use 0 to disable, or a divider value of 1 to 255. The CLKOUT clock - * rate is the clock source divided by the divider. This function will - * also toggle the clock source update register to update the clock - * source. - */ -void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div); - -/** - * @brief Return estimated watchdog oscillator rate - * @return Estimated watchdog oscillator rate - * @note This rate is accurate to plus or minus 40%. - */ -uint32_t Chip_Clock_GetWDTOSCRate(void); - -/** - * @brief Return System PLL input clock rate - * @return System PLL input clock rate - */ -uint32_t Chip_Clock_GetSystemPLLInClockRate(void); - -/** - * @brief Return System PLL output clock rate - * @return System PLL output clock rate - */ -uint32_t Chip_Clock_GetSystemPLLOutClockRate(void); - -/** - * @brief Return main clock rate - * @return main clock rate - */ -uint32_t Chip_Clock_GetMainClockRate(void); - -/** - * @brief Return system clock rate - * @return system clock rate - */ -uint32_t Chip_Clock_GetSystemClockRate(void); - -/** - * @brief Get IOCONCLKDIV clock rate - * @param reg : Divider register to get - * @return The clock rate going to the IOCON glitch filter - * @note Use 0 to disable, or a divider value of 1 to 255. - */ -uint32_t Chip_Clock_GetIOCONCLKDIVClockRate(CHIP_PIN_CLKDIV_T reg); - -/** - * @brief Set IOCONCLKDIV divider - * @param reg : divider register to set - * @param div : divider value for IOCONCLKDIV[reg] clock - * @return Nothing - * @note Use 0 to disable, or a divider value of 1 to 255. - */ -void Chip_Clock_SetIOCONCLKDIV(CHIP_PIN_CLKDIV_T reg, uint8_t div); - -/** - * @} - */ - - /** @defgroup IRC_8XX CHIP: LPC8xx IRC Configuration - * @ingroup CHIP_8XX_Drivers - * @{ - */ - - /** - * @brief set main / system clock using IRC and PLL - * @param main: main clock frequency (in MHz) - * @param sys : system clock frequency (in MHz) - * @return bool: Success = true / fail = false - * @note This is a table based function. The table uses both the - * main frequency and the system frequency to set the PLL. - * All useful main / system clock combinations are in the table. - * See irc_8xx.c for details. - */ -bool Chip_IRC_SetFreq(uint32_t main, uint32_t sys); - - /** - * @brief Set main / system clock using IRC and PLL - * @param sys : system clock frequency (in MHz) - * @return Nothing - * @note This function uses the ROM set_pll() function. - */ -void Chip_IRC_SetFreq_ROM(uint32_t sys); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CLOCK_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/chip/cmsis.h b/bsp/nxp/lpc/lpc824/Libraries/common/chip/cmsis.h deleted file mode 100644 index 4e59849840b..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/chip/cmsis.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * @brief Basic CMSIS include file - * - * @note - * Copyright(C) NXP Semiconductors, 2013 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __CMSIS_H_ -#define __CMSIS_H_ - -#include "lpc_types.h" - -// >>> system config -#define CHIP_LPC8XX -#define CHIP_LPC82X -// <<< - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup CMSIS_8XX_ALL CHIP: LPC8xx CMSIS include file - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -#if defined(__ARMCC_VERSION) -// Kill warning "#pragma push with no matching #pragma pop" - #pragma diag_suppress 2525 - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) -/* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) -// #pragma push // FIXME not usable for IAR - #pragma language=extended -#else - #error Not supported compiler type -#endif - -#if !defined(CORE_M0PLUS) -#error Please #define CORE_M0PLUS -#endif - -/** @defgroup CMSIS_8XX CHIP: LPC8xx Cortex CMSIS definitions - * @ingroup CMSIS_8XX_ALL - * @{ - */ - -/* Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define __CM0PLUS_REV 0x0001 /*!< Cortex-M0+ Core Revision */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __VTOR_PRESENT 1 /*!< VTOR is present in this implementation */ -#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @defgroup CMSIS_8XX_IRQ CHIP: LPC8xx peripheral interrupt numbers - * @ingroup CMSIS_8XX_ALL - * @{ - */ - -typedef enum { - /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ - - /****** LPC8xx Specific Interrupt Numbers ********************************************************/ - SPI0_IRQn = 0, /*!< SPI0 */ - SPI1_IRQn = 1, /*!< SPI1 */ - Reserved0_IRQn = 2, /*!< Reserved Interrupt */ - UART0_IRQn = 3, /*!< USART0 */ - UART1_IRQn = 4, /*!< USART1 */ - UART2_IRQn = 5, /*!< USART2 */ - Reserved1_IRQn = 6, /*!< Reserved Interrupt */ - I2C1_IRQn = 7, /*!< I2C1 */ - I2C0_IRQn = 8, /*!< I2C0 */ - I2C_IRQn = 8, /*!< Alias for I2C0 */ - SCT_IRQn = 9, /*!< SCT */ - MRT_IRQn = 10, /*!< MRT */ - CMP_IRQn = 11, /*!< CMP */ - WDT_IRQn = 12, /*!< WDT */ - BOD_IRQn = 13, /*!< BOD */ - FLASH_IRQn = 14, /*!< Flash interrupt */ - WKT_IRQn = 15, /*!< WKT Interrupt */ - ADC_SEQA_IRQn = 16, /*!< ADC sequence A completion */ - ADC_SEQB_IRQn = 17, /*!< ADC sequence B completion */ - ADC_THCMP_IRQn = 18, /*!< ADC threshold compare */ - ADC_OVR_IRQn = 19, /*!< ADC overrun */ - DMA_IRQn = 20, /*!< Reserved Interrupt */ - I2C2_IRQn = 21, /*!< Reserved Interrupt */ - I2C3_IRQn = 22, /*!< Reserved Interrupt */ - Reserved2_IRQn = 23, /*!< Reserved Interrupt */ - PININT0_IRQn = 24, /*!< External Interrupt 0 */ - PIN_INT0_IRQn = 24, /*!< External Interrupt 0 (alias) */ - PININT1_IRQn = 25, /*!< External Interrupt 1 */ - PIN_INT1_IRQn = 25, /*!< External Interrupt 1 (alias) */ - PININT2_IRQn = 26, /*!< External Interrupt 2 */ - PIN_INT2_IRQn = 26, /*!< External Interrupt 2 (alias) */ - PININT3_IRQn = 27, /*!< External Interrupt 3 */ - PIN_INT3_IRQn = 27, /*!< External Interrupt 3 (alias) */ - PININT4_IRQn = 28, /*!< External Interrupt 4 */ - PIN_INT4_IRQn = 28, /*!< External Interrupt 4 (alias) */ - PININT5_IRQn = 29, /*!< External Interrupt 5 */ - PIN_INT5_IRQn = 29, /*!< External Interrupt 5 (alias) */ - PININT6_IRQn = 30, /*!< External Interrupt 6 */ - PIN_INT6_IRQn = 30, /*!< External Interrupt 6 (alias) */ - PININT7_IRQn = 31, /*!< External Interrupt 7 */ - PIN_INT7_IRQn = 31, /*!< External Interrupt 7 (alias) */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm0plus.h" /*!< Cortex-M0+ processor and core peripherals */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CMSIS_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/chip/error_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/common/chip/error_8xx.h deleted file mode 100644 index 74e25ff42bf..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/chip/error_8xx.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * @brief Error code returned by LPC8xx Boot ROM drivers/library functions - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __ERROR_8XX_H__ -#define __ERROR_8XX_H__ - -/** @defgroup ROMAPI_ERRORCODES_8XX CHIP: LPC8xx ROM API error codes - * @ingroup ROMAPI_8XX - * @{ - */ - -/** Error code returned by Boot ROM drivers/library functions -* -* Error codes are a 32-bit value with : -* - The 16 MSB contains the peripheral code number -* - The 16 LSB contains an error code number associated to that peripheral -* -*/ -typedef enum -{ - /**\b 0x00000000*/ LPC_OK = 0, /**< enum value returned on Successful completion */ - /**\b 0x00000001*/ LPC_ERROR, /**< enum value returned on general error (I2C) */ - - /* ISP related errors */ - ERR_ISP_BASE = 0x00000000, - /**\b 0x00000001*/ ERR_ISP_INVALID_COMMAND = ERR_ISP_BASE + 1, - /**\b 0x00000002*/ ERR_ISP_SRC_ADDR_ERROR, /*!< Source address not on word boundary */ - /**\b 0x00000003*/ ERR_ISP_DST_ADDR_ERROR, /*!< Destination address not on word or 256 byte boundary */ - /**\b 0x00000004*/ ERR_ISP_SRC_ADDR_NOT_MAPPED, - /**\b 0x00000005*/ ERR_ISP_DST_ADDR_NOT_MAPPED, - /**\b 0x00000006*/ ERR_ISP_COUNT_ERROR, /*!< Byte count is not multiple of 4 or is not a permitted value */ - /**\b 0x00000007*/ ERR_ISP_INVALID_SECTOR, - /**\b 0x00000008*/ ERR_ISP_SECTOR_NOT_BLANK, - /**\b 0x00000009*/ ERR_ISP_SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION, - /**\b 0x0000000A*/ ERR_ISP_COMPARE_ERROR, - /**\b 0x0000000B*/ ERR_ISP_BUSY, /*!< Flash programming hardware interface is busy */ - /**\b 0x0000000C*/ ERR_ISP_PARAM_ERROR, /*!< Insufficient number of parameters */ - /**\b 0x0000000D*/ ERR_ISP_ADDR_ERROR, /*!< Address not on word boundary */ - /**\b 0x0000000E*/ ERR_ISP_ADDR_NOT_MAPPED, - /**\b 0x0000000F*/ ERR_ISP_CMD_LOCKED, /*!< Command is locked */ - /**\b 0x00000010*/ ERR_ISP_INVALID_CODE, /*!< Unlock code is invalid */ - /**\b 0x00000011*/ ERR_ISP_INVALID_BAUD_RATE, - /**\b 0x00000012*/ ERR_ISP_INVALID_STOP_BIT, - /**\b 0x00000013*/ ERR_ISP_CODE_READ_PROTECTION_ENABLED, - - /* I2C related errors */ - ERR_I2C_BASE = 0x00060000, - /**\b 0x00060001*/ ERR_I2C_NAK = ERR_I2C_BASE + 1, /*!< NAK */ - /**\b 0x00060002*/ ERR_I2C_BUFFER_OVERFLOW, /*!< Buffer overflow */ - /**\b 0x00060003*/ ERR_I2C_BYTE_COUNT_ERR, /*!< Byte count error */ - /**\b 0x00060004*/ ERR_I2C_LOSS_OF_ARBRITRATION, /*!< Loss of arbitration */ - /**\b 0x00060005*/ ERR_I2C_SLAVE_NOT_ADDRESSED, /*!< Slave not addressed */ - /**\b 0x00060006*/ ERR_I2C_LOSS_OF_ARBRITRATION_NAK_BIT, /*!< Loss arbritation NAK */ - /**\b 0x00060007*/ ERR_I2C_GENERAL_FAILURE, /*!< General failure */ - /**\b 0x00060008*/ ERR_I2C_REGS_SET_TO_DEFAULT, /*!< Set to default */ - /**\b 0x00060009*/ ERR_I2C_TIMEOUT, /*!< I2C Timeout */ - - /* UART related errors */ - /**\b 0x00080001*/ ERR_NO_ERROR = LPC_OK, /*!< Receive is busy */ - ERR_UART_BASE = 0x00080000, - /**\b 0x00080001*/ ERR_UART_RXD_BUSY = ERR_UART_BASE + 1, /*!< Receive is busy */ - /**\b 0x00080002*/ ERR_UART_TXD_BUSY, /*!< Transmit is busy */ - /**\b 0x00080003*/ ERR_UART_OVERRUN_FRAME_PARITY_NOISE, /*!< Overrun, Frame, Parity , Receive Noise error */ - /**\b 0x00080004*/ ERR_UART_UNDERRUN, /*!< Underrun */ - /**\b 0x00080005*/ ERR_UART_PARAM, /*!< Parameter error */ -} ErrorCode_t; - -/** - * @} - */ - -#endif /* __ERROR_8XX_H__ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/chip/fmc_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/common/chip/fmc_8xx.h deleted file mode 100644 index 46f445049de..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/chip/fmc_8xx.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * @brief LPC8xx FLASH Memory Controller (FMC) driver - * - * @note - * Copyright(C) NXP Semiconductors, 2013 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __FMC_8XX_H_ -#define __FMC_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup FMC_8XX CHIP: LPC8xx FLASH Memory Controller driver - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/** - * @brief FLASH Memory Controller Unit register block structure - */ -typedef struct { - __I uint32_t RESERVED1[4]; - __IO uint32_t FLASHCFG; /*!< Flash Configuration register */ - __I uint32_t RESERVED2[3]; - __IO uint32_t FMSSTART; /*!< Signature start address register */ - __IO uint32_t FMSSTOP; /*!< Signature stop address register */ - __I uint32_t RESERVED3; - __I uint32_t FMSW[1]; /*!< Signature word regsiter */ -} LPC_FMC_T; - -/* Reserved bits masks for registers */ -#define FMC_FLASHCFG_RESERVED (~3) -#define FMC_FMSSTART_RESERVED 0xfffe0000 -#define FMC_FMSSTOP_RESERVED 0x7ffe0000 - -/** - * @brief FLASH Access time definitions - */ -typedef enum { - FLASHTIM_20MHZ_CPU = 0, /*!< Flash accesses use 1 CPU clocks. Use for up to 20 MHz CPU clock*/ - FLASHTIM_30MHZ_CPU = 1, /*!< Flash accesses use 2 CPU clocks. Use for up to 30 MHz CPU clock*/ -} FMC_FLASHTIM_T; - -/** - * @brief Set FLASH memory access time in clocks - * @param clks : Clock cycles for FLASH access - * @return Nothing - * @note For CPU speed up to 20MHz, use a value of 0. For up to 30MHz, use - * a value of 1 - */ -STATIC INLINE void Chip_FMC_SetFLASHAccess(FMC_FLASHTIM_T clks) -{ - uint32_t tmp = LPC_FMC->FLASHCFG & (~((0x3)|FMC_FLASHCFG_RESERVED)); - - /* Don't alter upper bits */ - LPC_FMC->FLASHCFG = tmp | clks; -} - -/* Flash signature start and busy status bit */ -#define FMC_FLASHSIG_BUSY (1UL << 31) - -/** - * @brief Start computation of a signature for a FLASH memory range - * @param start : Starting FLASH address for computation, must be aligned on 16 byte boundary - * @param stop : Ending FLASH address for computation, must be aligned on 16 byte boundary - * @return Nothing - * @note Only bits 20..4 are used for the FLASH signature computation. - * Use the Chip_FMC_IsSignatureBusy() function to determine when the - * signature computation operation is complete and the - * Chip_FMC_GetSignature() function to get the computed signature. - */ -STATIC INLINE void Chip_FMC_ComputeSignature(uint32_t start, uint32_t stop) -{ - LPC_FMC->FMSSTART = (start >> 4); - LPC_FMC->FMSSTOP = (stop >> 4) | FMC_FLASHSIG_BUSY; -} - -/** - * @brief Start computation of a signature for a FLASH memory address and block count - * @param start : Starting FLASH address for computation, must be aligned on 16 byte boundary - * @param blocks : Number of 16 byte blocks used for computation - * @return Nothing - * @note Only bits 20..4 are used for the FLASH signature computation. - * Use the Chip_FMC_IsSignatureBusy() function to determine when the - * signature computation operation is complete and the - * Chip_FMC_GetSignature() function to get the computed signature. - */ -STATIC INLINE void Chip_FMC_ComputeSignatureBlocks(uint32_t start, uint32_t blocks) -{ - Chip_FMC_ComputeSignature(start, (start + (blocks * 16))); -} - -/** - * @brief Check for signature geenration completion - * @return true if the signature computation is running, false if finished - */ -STATIC INLINE bool Chip_FMC_IsSignatureBusy(void) -{ - return (bool) ((LPC_FMC->FMSSTOP & FMC_FLASHSIG_BUSY) != 0); -} - -/** - * @brief Returns the generated FLASH signature value - * @param index : Signature index, must be 0 - * @return the generated FLASH signature value - */ -STATIC INLINE uint32_t Chip_FMC_GetSignature(int index) -{ - return LPC_FMC->FMSW[index]; -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __FMC_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/chip/ioswm_8xx.c b/bsp/nxp/lpc/lpc824/Libraries/common/chip/ioswm_8xx.c deleted file mode 100644 index ad10a25b7e9..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/chip/ioswm_8xx.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * @brief LPC8xx IOCON driver - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ -#define _CHIP_COMMON_ -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -#define PINASSIGN_IDX(movable) (((movable) >> 4)) -#define PINSHIFT(movable) (((movable) & 0xF) << 3) - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Set the pin mode (pull-up/pull-down). */ -void Chip_IOCON_PinSetMode(LPC_IOCON_T *pIOCON, CHIP_PINx_T pin, CHIP_PIN_MODE_T mode) -{ - uint32_t reg; - - reg = pIOCON->PIO0[pin] & ~(PIN_MODE_MASK); - pIOCON->PIO0[pin] = reg | (mode << PIN_MODE_BITNUM); -} - -/* Enables/disables the pin hysteresis. */ -void Chip_IOCON_PinSetHysteresis(LPC_IOCON_T *pIOCON, CHIP_PINx_T pin, bool enable) -{ - if (enable == true) { - Chip_IOCON_PinEnableHysteresis(pIOCON, pin); - } - else { - Chip_IOCON_PinDisableHysteresis(pIOCON, pin); - } -} - -/*Inverts (or not) the input seen by a pin. */ -void Chip_IOCON_PinSetInputInverted(LPC_IOCON_T *pIOCON, CHIP_PINx_T pin, bool invert) -{ - if (invert == true) { - Chip_IOCON_PinEnableInputInverted(pIOCON, pin); - } - else { - Chip_IOCON_PinDisableInputInverted(pIOCON, pin); - } -} - -/* Enables/disables Open-Drain mode for a pin. */ -void Chip_IOCON_PinSetOpenDrainMode(LPC_IOCON_T *pIOCON, CHIP_PINx_T pin, bool open_drain) -{ - if (open_drain == true) { - Chip_IOCON_PinEnableOpenDrainMode(pIOCON, pin); - } - else { - Chip_IOCON_PinDisableOpenDrainMode(pIOCON, pin); - } -} - -/* Enable/configure digital filter sample mode for a pin. */ -void Chip_IOCON_PinSetSampleMode(LPC_IOCON_T *pIOCON, CHIP_PINx_T pin, CHIP_PIN_SMODE_T smode) -{ - uint32_t reg; - - reg = pIOCON->PIO0[pin] & ~(PIN_SMODE_MASK); - pIOCON->PIO0[pin] = reg | (smode << PIN_SMODE_BITNUM); -} - -/* Set the peripheral clock divisor for a pin. */ -void Chip_IOCON_PinSetClockDivisor(LPC_IOCON_T *pIOCON, CHIP_PINx_T pin, CHIP_PIN_CLKDIV_T clkdiv) -{ - uint32_t reg; - - reg = pIOCON->PIO0[pin] & ~(PIN_CLKDIV_MASK); - pIOCON->PIO0[pin] = reg | (clkdiv << PIN_CLKDIV_BITNUM); -} - -/* Set the I2C mode for a pin. */ -void Chip_IOCON_PinSetI2CMode(LPC_IOCON_T *pIOCON, CHIP_PINx_T pin, CHIP_PIN_I2CMODE_T mode) -{ - uint32_t reg; - - /* I2C mode bits only for I2C pins */ - reg = pIOCON->PIO0[pin] & ~(PIN_I2CMODE_MASK); - pIOCON->PIO0[pin] = reg | (mode << PIN_I2CMODE_BITNUM); -} - -/* Set all I/O Control pin muxing */ -void Chip_IOCON_SetPinMuxing(LPC_IOCON_T *pIOCON, const PINMUX_GRP_T* pinArray, uint32_t arrayLength) -{ - uint32_t ix; - - for (ix = 0; ix < arrayLength; ix++ ) { - Chip_IOCON_PinMuxSet(pIOCON, pinArray[ix].pin, pinArray[ix].modefunc); - } -} - -/* assign a movable pin function to a physical pin */ -void Chip_SWM_MovablePinAssign(CHIP_SWM_PIN_MOVABLE_T movable, uint8_t pin) -{ - uint32_t temp; - int pinshift = PINSHIFT(movable), regIndex = PINASSIGN_IDX(movable); - - temp = LPC_SWM->PINASSIGN[regIndex] & (~(0xFF << pinshift)); - LPC_SWM->PINASSIGN[regIndex] = temp | (pin << pinshift); -} - -/* true enables, false disables a Switch Matrix fixed-pin Function */ -void Chip_SWM_FixedPinEnable(CHIP_SWM_PIN_FIXED_T pin, bool enable) -{ - if (enable) { - Chip_SWM_EnableFixedPin(pin); - } - else { - Chip_SWM_DisableFixedPin(pin); - } -} diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/chip/ioswm_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/common/chip/ioswm_8xx.h deleted file mode 100644 index c7fe27cf961..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/chip/ioswm_8xx.h +++ /dev/null @@ -1,601 +0,0 @@ -/* - * @brief LPC8xx IOCON register block and driver - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __IOCON_8XX_H_ -#define __IOCON_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup IOCON_8XX CHIP: LPC8xx IOCON register block and driver - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -#define NUM_IOCON_PIO (29) - -/** - * @brief Array of IOCON pin definitions passed to Chip_IOCON_SetPinMuxing() must be in this format - */ -typedef struct { - uint32_t pin:8; /* Pin number */ - uint32_t modefunc:24; /* Function and mode */ -} PINMUX_GRP_T; - -/** - * @brief IOCON register block structure - * @note When accessing this register structure, use the PIOn enumeration - * as the array index as the pin assignments are not mapped 1-1 with the - * IOCON structure.
- * Incorrect: LPC_IOCON->PIO0[0] = 0x1; // Index 0 does not map to pin 0!
- * Correct: LPC_IOCON->PIO0[IOCON_PIO0] = 0x1; // Enumeration PIO0 maps to pin 0 - */ -typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */ - __IO uint32_t PIO0[NUM_IOCON_PIO + 2]; /* 2 added for reserved register */ -} LPC_IOCON_T; - -/** - * @brief IOCON Register bit definitions - */ -/* Pin Mode mask */ -#define PIN_MODE_MASK (0x3 << 3) -#define PIN_MODE_BITNUM (3) - -/* Pin Hysteresis mask */ -#define PIN_HYS_MASK (0x1 << 5) -#define PIN_HYS_BITNUM (5) - -/* Pin invert input mask */ -#define PIN_INV_MASK (0x1 << 6) -#define PIN_INV_BITNUM (6) - -/* Pin open drain mode mask */ -#define PIN_OD_MASK (0x1 << 10) -#define PIN_OD_BITNUM (10) - -/* Pin digital filter sample mode mask */ -#define PIN_SMODE_MASK (0x3 << 11) -#define PIN_SMODE_BITNUM (11) - -/* Pin clock divider mask */ -#define PIN_CLKDIV_MASK (0x7 << 13) -#define PIN_CLKDIV_BITNUM (13) - -/* Pin I2C mode mask - valid for PIO10 & PIO11 only */ -#define PIN_I2CMODE_MASK (0x3 << 8) -#define PIN_I2CMODE_BITNUM (8) - -/** - * @brief IOCON Pin Numbers enum - * Maps a pin number to an IOCON (register) array index. IOCON indexes - * are not mapped 1-1 with pin numbers. When access the PIO0 array in - * the LPC_IOCON_T structure, the array should be indexed with one of - * these enumerations based on the pin that will have it's settings - * changed.
- * Example: LPC_IOCON->PIO0[IOCON_PIO0] = 0x1; // Enumeration PIO0 maps to pin 0 - */ -typedef enum CHIP_PINx { - IOCON_PIO0 = 0x11, /*!< PIN 0 */ - IOCON_PIO1 = 0x0B, /*!< PIN 1 */ - IOCON_PIO2 = 0x06, /*!< PIN 2 */ - IOCON_PIO3 = 0x05, /*!< PIN 3 */ - IOCON_PIO4 = 0x04, /*!< PIN 4 */ - IOCON_PIO5 = 0x03, /*!< PIN 5 */ - /* The following pins are not present in DIP8 packages */ - IOCON_PIO6 = 0x10, /*!< PIN 6 */ - IOCON_PIO7 = 0x0F, /*!< PIN 7 */ - IOCON_PIO8 = 0x0E, /*!< PIN 8 */ - IOCON_PIO9 = 0x0D, /*!< PIN 9 */ - IOCON_PIO10 = 0x08, /*!< PIN 10 */ - IOCON_PIO11 = 0x07, /*!< PIN 11 */ - IOCON_PIO12 = 0x02, /*!< PIN 12 */ - IOCON_PIO13 = 0x01, /*!< PIN 13 */ - /* The following pins are not present in DIP8 & TSSOP16 packages */ - IOCON_PIO14 = 0x12, /*!< PIN 14 */ - IOCON_PIO15 = 0x0A, /*!< PIN 15 */ - IOCON_PIO16 = 0x09, /*!< PIN 16 */ - IOCON_PIO17 = 0x00, /*!< PIN 17 */ - IOCON_PIO_NUL0 = 0x0C, /*!< PIN NULL */ - - /* The following pins are not present in DIP8, TSSOP16 & TSSOP20 packages */ - IOCON_PIO18 = 0x1E, /*!< PIN 18 */ - IOCON_PIO19 = 0x1D, /*!< PIN 19 */ - IOCON_PIO20 = 0x1C, /*!< PIN 20 */ - IOCON_PIO21 = 0x1B, /*!< PIN 21 */ - IOCON_PIO22 = 0x1A, /*!< PIN 22 */ - IOCON_PIO23 = 0x19, /*!< PIN 23 */ - IOCON_PIO24 = 0x18, /*!< PIN 24 */ - IOCON_PIO25 = 0x17, /*!< PIN 25 */ - IOCON_PIO26 = 0x16, /*!< PIN 26 */ - IOCON_PIO27 = 0x15, /*!< PIN 27 */ - IOCON_PIO28 = 0x14, /*!< PIN 28 */ - IOCON_PIO_NUL1 = 0x13, /*!< PIN NULL */ -} CHIP_PINx_T; - -/** - * @brief IOCON Pin Modes enum - */ -typedef enum CHIP_PIN_MODE { - PIN_MODE_INACTIVE = 0, /*!< Inactive mode */ - PIN_MODE_PULLDN = 1, /*!< Pull Down mode */ - PIN_MODE_PULLUP = 2, /*!< Pull up mode */ - PIN_MODE_REPEATER = 3 /*!< Repeater mode */ -} CHIP_PIN_MODE_T; - -/** - * @brief IOCON Digital Filter Sample modes enum - */ -typedef enum CHIP_PIN_SMODE { - PIN_SMODE_BYPASS = 0, /*!< Bypass input filter */ - PIN_SMODE_CYC1 = 1, /*!< Input pulses shorter than 1 filter clock cycle are rejected */ - PIN_SMODE_CYC2 = 2, /*!< Input pulses shorter than 2 filter clock cycles are rejected */ - PIN_SMODE_CYC3 = 3 /*!< Input pulses shorter than 3 filter clock cycles are rejected */ -} CHIP_PIN_SMODE_T; - -/** - * @brief IOCON I2C Modes enum (Only for I2C pins PIO0_10 and PIO0_11) - */ -typedef enum CHIP_PIN_I2CMODE { - PIN_I2CMODE_STDFAST = 0, /*!< I2C standard mode/Fast mode */ - PIN_I2CMODE_GPIO = 1, /*!< Standard I/O functionality */ - PIN_I2CMODE_FASTPLUS = 2 /*!< I2C Fast plus mode */ -} CHIP_PIN_I2CMODE_T; - -/** - * @brief Sets I/O Control pin mux - * @param pIOCON : The base of IOCON peripheral on the chip - * @param pin : GPIO pin to mux - * @param modefunc : OR'ed values or type IOCON_* - * @return Nothing - */ -STATIC INLINE void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, uint8_t pin, uint32_t modefunc) -{ - pIOCON->PIO0[pin] = modefunc; -} - -/** - * @brief Set all I/O Control pin muxing - * @param pIOCON : The base of IOCON peripheral on the chip - * @param pinArray : Pointer to array of pin mux selections - * @param arrayLength : Number of entries in pinArray - * @return Nothing - */ -void Chip_IOCON_SetPinMuxing(LPC_IOCON_T *pIOCON, const PINMUX_GRP_T* pinArray, uint32_t arrayLength); - -/** - * @brief Sets pull-up or pull-down mode for a pin - * @param pIOCON : The base of IOCON peripheral on the chip - * @param pin : Pin number - * @param mode : Mode (Pull-up/Pull-down mode) - * @return Nothing - * @note Do not use with pins PIO10 and PIO11. - */ -void Chip_IOCON_PinSetMode(LPC_IOCON_T *pIOCON, CHIP_PINx_T pin, CHIP_PIN_MODE_T mode); - -/** - * @brief Enable or disable hysteresis for a pin - * @param pIOCON : The base of IOCON peripheral on the chip - * @param pin : Pin number - * @param enable : true to enable, false to disable - * @return Nothing - * @note Do not use with pins PIO10 and PIO11. - */ -void Chip_IOCON_PinSetHysteresis(LPC_IOCON_T *pIOCON, CHIP_PINx_T pin, bool enable); - -/** - * @brief Enable hysteresis for a pin - * @param pIOCON : The base of IOCON peripheral on the chip - * @param pin : Pin number - * @return Nothing - * @note Do not use with pins PIO10 and PIO11. - */ -STATIC INLINE void Chip_IOCON_PinEnableHysteresis(LPC_IOCON_T *pIOCON, CHIP_PINx_T pin) -{ - pIOCON->PIO0[pin] |= PIN_HYS_MASK; -} - -/** - * @brief Disable hysteresis for a pin - * @param pIOCON : The base of IOCON peripheral on the chip - * @param pin : Pin number - * @return Nothing - * @note Do not use with pins PIO10 and PIO11. - */ -STATIC INLINE void Chip_IOCON_PinDisableHysteresis(LPC_IOCON_T *pIOCON, CHIP_PINx_T pin) -{ - pIOCON->PIO0[pin] &= ~PIN_HYS_MASK; -} - -/** - * @brief Enable or disable invert input for a pin - * @param pIOCON : The base of IOCON peripheral on the chip - * @param pin : Pin number - * @param invert : true to invert, false to not to invert - * @return Nothing - */ -void Chip_IOCON_PinSetInputInverted(LPC_IOCON_T *pIOCON, CHIP_PINx_T pin, bool invert); - -/** - * @brief Enable invert input for a pin - * @param pIOCON : The base of IOCON peripheral on the chip - * @param pin : Pin number - * @return Nothing - */ -STATIC INLINE void Chip_IOCON_PinEnableInputInverted(LPC_IOCON_T *pIOCON, CHIP_PINx_T pin) -{ - pIOCON->PIO0[pin] |= PIN_INV_MASK; -} - -/** - * @brief Disable invert input for a pin - * @param pIOCON : The base of IOCON peripheral on the chip - * @param pin : Pin number - * @return Nothing - */ -STATIC INLINE void Chip_IOCON_PinDisableInputInverted(LPC_IOCON_T *pIOCON, CHIP_PINx_T pin) -{ - pIOCON->PIO0[pin] &= ~PIN_INV_MASK; -} - -/** - * @brief Enables or disables open-drain mode for a pin - * @param pIOCON : The base of IOCON peripheral on the chip - * @param pin : Pin number - * @param open_drain : true to enable open-drain mode, - * false to disable open-drain mode - * @return Nothing - */ -void Chip_IOCON_PinSetOpenDrainMode(LPC_IOCON_T *pIOCON, CHIP_PINx_T pin, bool open_drain); - -/** - * @brief Enables open-drain mode for a pin - * @param pIOCON : The base of IOCON peripheral on the chip - * @param pin : Pin number - * @return Nothing - */ -STATIC INLINE void Chip_IOCON_PinEnableOpenDrainMode(LPC_IOCON_T *pIOCON, CHIP_PINx_T pin) -{ - pIOCON->PIO0[pin] |= PIN_OD_MASK; -} - -/** - * @brief Disables open-drain mode for a pin - * @param pIOCON : The base of IOCON peripheral on the chip - * @param pin : Pin number - * @return Nothing - */ -STATIC INLINE void Chip_IOCON_PinDisableOpenDrainMode(LPC_IOCON_T *pIOCON, CHIP_PINx_T pin) -{ - pIOCON->PIO0[pin] &= ~PIN_OD_MASK; -} - -/** - * @brief Set pin mode to default after reset - * @param pIOCON : The base of IOCON peripheral on the chip - * @param pin : Pin number - * @return Nothing - */ -STATIC INLINE void Chip_IOCON_PinSetToDefault(LPC_IOCON_T *pIOCON, CHIP_PINx_T pin) -{ - if (pin == IOCON_PIO10 || pin == IOCON_PIO11) - pIOCON->PIO0[pin] = 0x80; - else - pIOCON->PIO0[pin] = 0x90; -} - -/** - * @brief Sets the digital filter sampling mode for a pin - * @param pIOCON : The base of IOCON peripheral on the chip - * @param pin : Pin number - * @param smode : 0x0 = bypass, 0x[1..3] = 1 to 3 clock cycles. - * @return Nothing - */ -void Chip_IOCON_PinSetSampleMode(LPC_IOCON_T *pIOCON, CHIP_PINx_T pin, CHIP_PIN_SMODE_T smode); - -/** - * @brief Select peripheral clock divider for input filter sampling clock - * @param pIOCON : The base of IOCON peripheral on the chip - * @param pin : Pin number - * @param clkdiv : 0 = no divisor, 1...6 = PCLK/clkdiv - * @return Nothing - */ -void Chip_IOCON_PinSetClockDivisor(LPC_IOCON_T *pIOCON, CHIP_PINx_T pin, CHIP_PIN_CLKDIV_T clkdiv); - -/** - * @brief Set I2C mode for a pin - * @param pIOCON : The base of IOCON peripheral on the chip - * @param pin : Pin number - * @param mode : 0:Standard/Fast I2C 1: GPIO 2: Fast Plus - * @return Nothing - * @note Valid for pins PIO0_10 and PIO0_11 only. - */ -void Chip_IOCON_PinSetI2CMode(LPC_IOCON_T *pIOCON, CHIP_PINx_T pin, CHIP_PIN_I2CMODE_T mode); - -/** - * @} - */ - - -/** @defgroup SWM_8XX CHIP: LPC8xx Switch Matrix Driver - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/** - * @brief LPC8XX Switch Matrix register block structure - */ -typedef struct { -#if defined(CHIP_LPC82X) - __IO uint32_t PINASSIGN[12]; /*!< Pin Assign register array */ - __I uint32_t RESERVED0[100]; -#else - __IO uint32_t PINASSIGN[9]; /*!< Pin Assign register array */ - __I uint32_t RESERVED0[103]; -#endif - __IO uint32_t PINENABLE0; /*!< Pin Enable register */ -} LPC_SWM_T; - -#if defined(CHIP_LPC82X) -#define SWM_PINENABLE0_RESERVED (~0x1ffffff) -#else -#define SWM_PINENABLE0_RESERVED (~0x1ff) -#endif - -/** - * @brief LPC8XX Switch Matrix Movable pins - */ -#if defined(CHIP_LPC82X) -typedef enum CHIP_SWM_PIN_MOVABLE { - SWM_U0_TXD_O, /*!< PINASSIGN0 - UART0 TXD Output */ - SWM_U0_RXD_I, /*!< PINASSIGN0 - UART0 RXD Input */ - SWM_U0_RTS_O, /*!< PINASSIGN0 - UART0 RTS Output */ - SWM_U0_CTS_I, /*!< PINASSIGN0 - UART0 CTS Input */ - - SWM_U0_SCLK_IO = 0x10, /*!< PINASSIGN1 - UART0 SCLK I/O */ - SWM_U1_TXD_O, /*!< PINASSIGN1 - UART1 TXD Output */ - SWM_U1_RXD_I, /*!< PINASSIGN1 - UART1 RXD Input */ - SWM_U1_RTS_O, /*!< PINASSIGN1 - UART1 RTS Output */ - - SWM_U1_CTS_I = 0x20, /*!< PINASSIGN2 - UART1 CTS Input */ - SWM_U1_SCLK_IO, /*!< PINASSIGN2 - UART1 SCLK I/O */ - SWM_U2_TXD_O, /*!< PINASSIGN2 - UART2 TXD Output */ - SWM_U2_RXD_I, /*!< PINASSIGN2 - UART2 RXD Input */ - - SWM_U2_RTS_O = 0x30, /*!< PINASSIGN3 - UART2 RTS Output */ - SWM_U2_CTS_I, /*!< PINASSIGN3 - UART2 CTS Input */ - SWM_U2_SCLK_IO, /*!< PINASSIGN3 - UART2 SCLK I/O */ - SWM_SPI0_SCK_IO, /*!< PINASSIGN3 - SPI0 SCK I/O */ - - SWM_SPI0_MOSI_IO = 0x40, /*!< PINASSIGN4 - SPI0 MOSI I/O */ - SWM_SPI0_MISO_IO, /*!< PINASSIGN4 - SPI0 MISO I/O */ - SWM_SPI0_SSEL0_IO, /*!< PINASSIGN4 - SPI0 SSEL0 I/O */ - SWM_SPI0_SSEL1_IO, /*!< PINASSIGN4 - SPI0 SSEL1 I/O */ - - SWM_SPI0_SSEL2_IO = 0x50, /*!< PINASSIGN5 - SPI0 SSEL2 I/O */ - SWM_SPI0_SSEL3_IO, /*!< PINASSIGN5 - SPI0 SSEL3 I/O */ - SWM_SPI1_SCK_IO, /*!< PINASSIGN5 - SPI1 SCK I/O */ - SWM_SPI1_MOSI_IO, /*!< PINASSIGN5 - SPI1 MOSI I/O */ - - SWM_SPI1_MISO_IO = 0x60, /*!< PINASSIGN6 - SPI1 MISO I/O */ - SWM_SPI1_SSEL0_IO, /*!< PINASSIGN6 - SPI1 SSEL0 I/O */ - SWM_SPI1_SSEL1_IO, /*!< PINASSIGN6 - SPI1 SSEL1 I/O */ - SWM_SCT_IN0_I, /*!< PINASSIGN6 - SCT INPUT_0 Input */ - - SWM_SCT_IN1_I = 0x70, /*!< PINASSIGN7 - SCT INPUT_1 Input */ - SWM_SCT_IN2_I, /*!< PINASSIGN7 - SCT INPUT_2 Input */ - SWM_SCT_IN3_I, /*!< PINASSIGN7 - SCT INPUT_3 Input */ - SWM_SCT_OUT0_O, /*!< PINASSIGN7 - SCT OUTPUT_0 Output */ - - SWM_SCT_OUT1_O = 0x80, /*!< PINASSIGN8 - SCT OUTPUT_1 Output */ - SWM_SCT_OUT2_O, /*!< PINASSIGN8 - SCT OUTPUT_2 Output */ - SWM_SCT_OUT3_O, /*!< PINASSIGN8 - SCT OUTPUT_3 Output */ - SWM_SCT_OUT4_O, /*!< PINASSIGN8 - SCT OUTPUT_4 Output */ - - SWM_SCT_OUT5_O = 0x90, /*!< PINASSIGN9 - SCT OUTPUT_5 Output */ - SWM_I2C1_SDA_IO, /*!< PINASSIGN9 - I2C1 SDA I/O */ - SWM_I2C1_SCL_IO, /*!< PINASSIGN9 - I2C1 SCL I/O */ - SWM_I2C2_SDA_IO, /*!< PINASSIGN9 - I2C2 SDA I/O */ - - SWM_I2C2_SCL_IO = 0xA0, /*!< PINASSIGN10 - I2C2 SCL I/O */ - SWM_I2C3_SDA_IO, /*!< PINASSIGN10 - I2C3 SDA I/O */ - SWM_I2C3_SCL_IO, /*!< PINASSIGN10 - I2C3 SCL I/O */ - SWM_ADC_PINTRIG0_I, /*!< PINASSIGN10 - ADC PIN TRIGGER-0 Input */ - - SWM_ADC_PINTRIG1_I = 0xB0, /*!< PINASSIGN11 - ADC PIN TRIGGER-1 Input */ - SWM_ACMP_O_O, /*!< PINASSIGN11 - ACMP OUT Output */ - SWM_CLKOUT_O, /*!< PINASSIGN11 - CLKOUT Output */ - SWM_GPIO_INT_BMAT_O, /*!< PINASSIGN11 - GPIO INT BMAT Output */ - -} CHIP_SWM_PIN_MOVABLE_T; -#else -typedef enum CHIP_SWM_PIN_MOVABLE { - SWM_U0_TXD_O = 0x00, /*!< PINASSIGN0 - UART0 TXD Output */ - SWM_U0_RXD_I = 0x01, /*!< PINASSIGN0 - UART0 RXD Input */ - SWM_U0_RTS_O = 0x02, /*!< PINASSIGN0 - UART0 RTS Output */ - SWM_U0_CTS_I = 0x03, /*!< PINASSIGN0 - UART0 CTS Input */ - SWM_U0_SCLK_IO = 0x10, /*!< PINASSIGN1 - UART0 SCLK I/O */ - SWM_U1_TXD_O = 0x11, /*!< PINASSIGN1 - UART1 TXD Output */ - SWM_U1_RXD_I = 0x12, /*!< PINASSIGN1 - UART1 RXD Input */ - SWM_U1_RTS_O = 0x13, /*!< PINASSIGN1 - UART1 RTS Output */ - SWM_U1_CTS_I = 0x20, /*!< PINASSIGN2 - UART1 CTS Input */ - SWM_U1_SCLK_IO = 0x21, /*!< PINASSIGN2 - UART1 SCLK I/O */ - SWM_U2_TXD_O = 0x22, /*!< PINASSIGN2 - UART2 TXD Output */ - SWM_U2_RXD_I = 0x23, /*!< PINASSIGN2 - UART2 RXD Input */ - SWM_U2_RTS_O = 0x30, /*!< PINASSIGN3 - UART2 RTS Output */ - SWM_U2_CTS_I = 0x31, /*!< PINASSIGN3 - UART2 CTS Input */ - SWM_U2_SCLK_IO = 0x32, /*!< PINASSIGN3 - UART2 SCLK I/O */ - SWM_SPI0_SCK_IO = 0x33, /*!< PINASSIGN3 - SPI0 SCK I/O */ - SWM_SPI0_MOSI_IO = 0x40, /*!< PINASSIGN4 - SPI0 MOSI I/O */ - SWM_SPI0_MISO_IO = 0x41, /*!< PINASSIGN4 - SPI0 MISO I/O */ - SWM_SPI0_SSEL_IO = 0x42, /*!< PINASSIGN4 - SPI0 SSEL I/O */ - SWM_SPI1_SCK_IO = 0x43, /*!< PINASSIGN4 - SPI1 SCK I/O */ - SWM_SPI1_MOSI_IO = 0x50, /*!< PINASSIGN5 - SPI1 MOSI I/O */ - SWM_SPI1_MISO_IO = 0x51, /*!< PINASSIGN5 - SPI1 MISO I/O */ - SWM_SPI1_SSEL_IO = 0x52, /*!< PINASSIGN5 - SPI1 SSEL I/O */ - SWM_CTIN_0_I = 0x53, /*!< PINASSIGN5 - CTIN0 Input */ - SWM_CTIN_1_I = 0x60, /*!< PINASSIGN6 - CTIN1 Input */ - SWM_CTIN_2_I = 0x61, /*!< PINASSIGN6 - CTIN2 Input */ - SWM_CTIN_3_I = 0x62, /*!< PINASSIGN6 - CTIN3 Input */ - SWM_CTOUT_0_O = 0x63, /*!< PINASSIGN6 - CTOUT0 Output */ - SWM_CTOUT_1_O = 0x70, /*!< PINASSIGN7 - CTOUT1 Output */ - SWM_CTOUT_2_O = 0x71, /*!< PINASSIGN7 - CTOUT2 Output */ - SWM_CTOUT_3_O = 0x72, /*!< PINASSIGN7 - CTOUT3 Output */ - SWM_I2C_SDA_IO = 0x73, /*!< PINASSIGN7 - I2C SDA I/O */ - SWM_I2C_SCL_IO = 0x80, /*!< PINASSIGN8 - I2C SCL I/O */ - SWM_ACMP_O_O = 0x81, /*!< PINASSIGN8 - I2C ACMP Output */ - SWM_CLKOUT_O = 0x82, /*!< PINASSIGN8 - I2C CLKOUT Output */ - SWM_GPIO_INT_BMAT_O = 0x83, /*!< PINASSIGN8 - I2C GPIO INT BMAT Output */ -} CHIP_SWM_PIN_MOVABLE_T; -#endif - -/** - * @brief LPC8XX Switch Matrix Fixed pins - */ -#if defined(CHIP_LPC82X) -typedef enum CHIP_SWM_PIN_FIXED { - SWM_FIXED_ACMP_I1 = 0, /*!< ACMP I1 */ - SWM_FIXED_ACMP_I2 = 1, /*!< ACMP I2 */ - SWM_FIXED_ACMP_I3 = 2, /*!< ACMP I3 */ - SWM_FIXED_ACMP_I4 = 3, /*!< ACMP I4 */ - SWM_FIXED_SWCLK = 4, /*!< SWCLK */ - SWM_FIXED_SWDIO = 5, /*!< SWDIO */ - SWM_FIXED_XTALIN = 6, /*!< XTALIN */ - SWM_FIXED_XTALOUT = 7, /*!< XTALOUT */ - SWM_FIXED_RST = 8, /*!< Reset */ - SWM_FIXED_CLKIN = 9, /*!< Clock Input */ - SWM_FIXED_VDDCMP = 10, /*!< VDD */ - SWM_FIXED_I2C0_SDA = 11, /*!< I2C0 SDA */ - SWM_FIXED_I2C0_SCL = 12, /*!< I2C0 SCL */ - SWM_FIXED_ADC0 = 13, /*!< ADC0 */ - SWM_FIXED_ADC1 = 14, /*!< ADC1 */ - SWM_FIXED_ADC2 = 15, /*!< ADC2 */ - SWM_FIXED_ADC3 = 16, /*!< ADC3 */ - SWM_FIXED_ADC4 = 17, /*!< ADC4 */ - SWM_FIXED_ADC5 = 18, /*!< ADC5 */ - SWM_FIXED_ADC6 = 19, /*!< ADC6 */ - SWM_FIXED_ADC7 = 20, /*!< ADC7 */ - SWM_FIXED_ADC8 = 21, /*!< ADC8 */ - SWM_FIXED_ADC9 = 22, /*!< ADC9 */ - SWM_FIXED_ADC10 = 23, /*!< ADC10 */ - SWM_FIXED_ADC11 = 24, /*!< ADC11 */ -} CHIP_SWM_PIN_FIXED_T; -#else -typedef enum CHIP_SWM_PIN_FIXED { - SWM_FIXED_ACMP_I1 = 0, /*!< ACMP I1 */ - SWM_FIXED_ACMP_I2 = 1, /*!< ACMP I2 */ - SWM_FIXED_SWCLK = 2, /*!< SWCLK */ - SWM_FIXED_SWDIO = 3, /*!< SWDIO */ - SWM_FIXED_XTALIN = 4, /*!< XTALIN */ - SWM_FIXED_XTALOUT = 5, /*!< XTALOUT */ - SWM_FIXED_RST = 6, /*!< Reset */ - SWM_FIXED_CLKIN = 7, /*!< Clock Input */ - SWM_FIXED_VDDCMP = 8 /*!< VDD */ -} CHIP_SWM_PIN_FIXED_T; -#endif - -/** - * @brief Initialise the SWM module - * @return Nothing - * @note This function only enables the SWM clock. - */ -STATIC INLINE void Chip_SWM_Init(void) -{ - Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM); -} - -/** - * @brief Deinitialise the SWM module - * @return Nothing - * @note This function only disables the SWM clock. - */ -STATIC INLINE void Chip_SWM_Deinit(void) -{ - Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SWM); -} - -/** - * @brief Assign movable pin function to physical pin in Switch Matrix - * @param movable : Movable pin function - * @param assign : Physical pin to be assigned - * @return Nothing - */ -void Chip_SWM_MovablePinAssign(CHIP_SWM_PIN_MOVABLE_T movable, uint8_t assign); - -/** - * @brief Enables or Disable Fixed Function Pin in the Switch Matrix - * @param pin : Pin to be enabled or disabled - * @param enable : True to enable the pin, False to disable the pin - * @return Nothing - */ -void Chip_SWM_FixedPinEnable(CHIP_SWM_PIN_FIXED_T pin, bool enable); - -/** - * @brief Enables a Fixed Function Pin in the Switch Matrix - * @param pin : Pin to be enabled - * @return Nothing - */ -STATIC INLINE void Chip_SWM_EnableFixedPin(CHIP_SWM_PIN_FIXED_T pin) -{ - LPC_SWM->PINENABLE0 &= ~((1 << (uint32_t) pin) | SWM_PINENABLE0_RESERVED); -} - -/** - * @brief Disables a Fixed Function Pin in the Switch Matrix - * @param pin : Pin to be disabled - * @return Nothing - */ -STATIC INLINE void Chip_SWM_DisableFixedPin(CHIP_SWM_PIN_FIXED_T pin) -{ - LPC_SWM->PINENABLE0 = (1 << (uint32_t) pin) | (LPC_SWM->PINENABLE0 & ~SWM_PINENABLE0_RESERVED); -} - -/** - * @brief Tests whether a fixed pin is enabled or disabled in the Switch Matrix - * @param pin : The pin to test whether it is enabled or disabled - * @return True if the pin is enabled, False if disabled - */ -STATIC INLINE bool Chip_SWM_IsEnabled(CHIP_SWM_PIN_FIXED_T pin) -{ - return (bool) ((LPC_SWM->PINENABLE0 & (1 << (uint32_t) pin)) == 0); -} - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __IOCON_8XX_H_ */ - diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/chip/lpc_types.h b/bsp/nxp/lpc/lpc824/Libraries/common/chip/lpc_types.h deleted file mode 100644 index 14c7b605009..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/chip/lpc_types.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * @brief Common types used in LPC functions - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __LPC_TYPES_H_ -#define __LPC_TYPES_H_ - -#include -#include - -/** @defgroup LPC_Types CHIP: LPC Common Types - * @ingroup CHIP_Common - * @{ - */ - -/** @defgroup LPC_Types_Public_Types LPC Public Types - * @{ - */ - -/** - * @brief Boolean Type definition - */ -typedef enum {FALSE = 0, TRUE = !FALSE} Bool; - -/** - * @brief Boolean Type definition - */ -#if !defined(__cplusplus) -// typedef enum {false = 0, true = !false} bool; -#endif - -/** - * @brief Flag Status and Interrupt Flag Status type definition - */ -typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState; -#define PARAM_SETSTATE(State) ((State == RESET) || (State == SET)) - -/** - * @brief Functional State Definition - */ -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define PARAM_FUNCTIONALSTATE(State) ((State == DISABLE) || (State == ENABLE)) - -/** - * @ Status type definition - */ -typedef enum {ERROR = 0, SUCCESS = !ERROR} Status; - -/** - * Read/Write transfer type mode (Block or non-block) - */ -typedef enum { - NONE_BLOCKING = 0, /**< None Blocking type */ - BLOCKING, /**< Blocking type */ -} TRANSFER_BLOCK_T; - -/** Pointer to Function returning Void (any number of parameters) */ -typedef void (*PFV)(); - -/** Pointer to Function returning int32_t (any number of parameters) */ -typedef int32_t (*PFI)(); - -/** - * @} - */ - -/** @defgroup LPC_Types_Public_Macros LPC Public Macros - * @{ - */ - -/* _BIT(n) sets the bit at position "n" - * _BIT(n) is intended to be used in "OR" and "AND" expressions: - * e.g., "(_BIT(3) | _BIT(7))". - */ -#undef _BIT -/* Set bit macro */ -#define _BIT(n) (1 << (n)) - -/* _SBF(f,v) sets the bit field starting at position "f" to value "v". - * _SBF(f,v) is intended to be used in "OR" and "AND" expressions: - * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)" - */ -#undef _SBF -/* Set bit field macro */ -#define _SBF(f, v) ((v) << (f)) - -/* _BITMASK constructs a symbol with 'field_width' least significant - * bits set. - * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF - * The symbol is intended to be used to limit the bit field width - * thusly: - * = (any_expression) & _BITMASK(x), where 0 < x <= 32. - * If "any_expression" results in a value that is larger than can be - * contained in 'x' bits, the bits above 'x - 1' are masked off. When - * used with the _SBF example above, the example would be written: - * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16)) - * This ensures that the value written to a_reg is no wider than - * 16 bits, and makes the code easier to read and understand. - */ -#undef _BITMASK -/* Bitmask creation macro */ -#define _BITMASK(field_width) ( _BIT(field_width) - 1) - -/* NULL pointer */ -#ifndef NULL -#define NULL ((void *) 0) -#endif - -/* Number of elements in an array */ -#define NELEMENTS(array) (sizeof(array) / sizeof(array[0])) - -/* Static data/function define */ -#define STATIC static -/* External data/function define */ -#define EXTERN extern - -#if !defined(MAX) -#define MAX(a, b) (((a) > (b)) ? (a) : (b)) -#endif -#if !defined(MIN) -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) -#endif - -/** - * @} - */ - -/* Old Type Definition compatibility */ -/** @addtogroup LPC_Types_Public_Types - * @{ - */ - -/** LPC type for character type */ -typedef char CHAR; - -/** LPC type for 8 bit unsigned value */ -typedef uint8_t UNS_8; - -/** LPC type for 8 bit signed value */ -typedef int8_t INT_8; - -/** LPC type for 16 bit unsigned value */ -typedef uint16_t UNS_16; - -/** LPC type for 16 bit signed value */ -typedef int16_t INT_16; - -/** LPC type for 32 bit unsigned value */ -typedef uint32_t UNS_32; - -/** LPC type for 32 bit signed value */ -typedef int32_t INT_32; - -/** LPC type for 64 bit signed value */ -typedef int64_t INT_64; - -/** LPC type for 64 bit unsigned value */ -typedef uint64_t UNS_64; - -#ifdef __CODE_RED -#define BOOL_32 bool -#define BOOL_16 bool -#define BOOL_8 bool -#else -/** 32 bit boolean type */ -typedef bool BOOL_32; - -/** 16 bit boolean type */ -typedef bool BOOL_16; - -/** 8 bit boolean type */ -typedef bool BOOL_8; -#endif - -#ifdef __CC_ARM -#define INLINE __inline -#else -#define INLINE inline -#endif - -/** - * @} - */ - -/** - * @} - */ - -#endif /* __LPC_TYPES_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/chip/syscon_8xx.c b/bsp/nxp/lpc/lpc824/Libraries/common/chip/syscon_8xx.c deleted file mode 100644 index b1ec221acea..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/chip/syscon_8xx.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * @brief LPC8xx System & Control driver - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ -#define _CHIP_COMMON_ -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/* PDSLEEPCFG register mask */ -#define PDSLEEPWRMASK (0x0000FFB7) -#define PDSLEEPDATMASK (0x00000048) - -#if defined(CHIP_LPC82X) -/* PDWAKECFG and PDRUNCFG register masks */ -#define PDWAKEUPWRMASK (0x00006D00) -#define PDWAKEUPDATMASK (0x000080FF) - -#else -/* PDWAKECFG and PDRUNCFG register masks */ -#define PDWAKEUPWRMASK (0x00006D10) -#define PDWAKEUPDATMASK (0x000080EF) -#endif - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Setup deep sleep behaviour for power down */ -void Chip_SYSCTL_SetDeepSleepPD(uint32_t sleepmask) -{ - /* Update new value */ - LPC_SYSCTL->PDSLEEPCFG = PDSLEEPWRMASK | (sleepmask & PDSLEEPDATMASK); -} - -/* Setup wakeup behaviour from deep sleep */ -void Chip_SYSCTL_SetWakeup(uint32_t wakeupmask) -{ - /* Update new value */ - LPC_SYSCTL->PDAWAKECFG = PDWAKEUPWRMASK | (wakeupmask & PDWAKEUPDATMASK); -} - -/* Power down one or more blocks or peripherals */ -void Chip_SYSCTL_PowerDown(uint32_t powerdownmask) -{ - uint32_t pdrun; - - /* Get current power states */ - pdrun = LPC_SYSCTL->PDRUNCFG & PDWAKEUPDATMASK; - - /* Disable peripheral states by setting high */ - pdrun |= (powerdownmask & PDWAKEUPDATMASK); - - /* Update power states with required register bits */ - LPC_SYSCTL->PDRUNCFG = (PDWAKEUPWRMASK | pdrun); -} - -/* Power up one or more blocks or peripherals */ -void Chip_SYSCTL_PowerUp(uint32_t powerupmask) -{ - uint32_t pdrun; - - /* Get current power states */ - pdrun = LPC_SYSCTL->PDRUNCFG & PDWAKEUPDATMASK; - - /* Enable peripheral states by setting low */ - pdrun &= ~(powerupmask & PDWAKEUPDATMASK); - - /* Update power states with required register bits */ - LPC_SYSCTL->PDRUNCFG = (PDWAKEUPWRMASK | pdrun); -} diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/chip/syscon_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/common/chip/syscon_8xx.h deleted file mode 100644 index 6a635d720c4..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/chip/syscon_8xx.h +++ /dev/null @@ -1,573 +0,0 @@ -/* - * @brief LPC8xx System & Control driver inclusion file - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __SYSCTL_8XX_H_ -#define __SYSCTL_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup SYSCTL_8XX CHIP: LPC8xx System and Control Driver - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/** - * System reset status values - */ -#define SYSCTL_RST_POR (1 << 0) /*!< POR reset status */ -#define SYSCTL_RST_EXTRST (1 << 1) /*!< External reset status */ -#define SYSCTL_RST_WDT (1 << 2) /*!< Watchdog reset status */ -#define SYSCTL_RST_BOD (1 << 3) /*!< Brown-out detect reset status */ -#define SYSCTL_RST_SYSRST (1 << 4) /*!< software system reset status */ - -/** - * Peripheral interrupt wakeup events values - */ -#define SYSCTL_WAKEUP_SPI0TINT (1 << 0) /*!< SPI0 interrupt wake-up */ -#define SYSCTL_WAKEUP_SPI1INT (1 << 1) /*!< SPI0 interrupt wake-up */ -#define SYSCTL_WAKEUP_USART0INT (1 << 3) /*!< USART0 interrupt wake-up */ -#define SYSCTL_WAKEUP_USART1INT (1 << 4) /*!< USART1 interrupt wake-up */ -#define SYSCTL_WAKEUP_USART2INT (1 << 5) /*!< USART2 interrupt wake-up */ -#define SYSCTL_WAKEUP_I2C0INT (1 << 8) /*!< I2C0 interrupt wake-up */ -#define SYSCTL_WAKEUP_I2C1INT (1 << 7) /*!< I2C1 interrupt wake-up [Available only on LPC82X] */ -#define SYSCTL_WAKEUP_I2C2INT (1 << 21) /*!< I2C2 interrupt wake-up [Available only on LPC82X] */ -#define SYSCTL_WAKEUP_I2C3INT (1 << 22) /*!< I2C3 interrupt wake-up [Available only on LPC82X] */ -#define SYSCTL_WAKEUP_WWDTINT (1 << 12) /*!< WWDT interrupt wake-up */ -#define SYSCTL_WAKEUP_BODINT (1 << 13) /*!< Brown Out Detect (BOD) interrupt wake-up */ -#define SYSCTL_WAKEUP_WKTINT (1 << 15) /*!< Self wake-up timer interrupt wake-up */ -#define SYSCTL_WAKEUP_I2CINT SYSCTL_WAKEUP_I2C0INT /*!< Same as #SYSCTL_WAKEUP_I2CINT */ - -/** - * Deep sleep setup values - */ -#define SYSCTL_DEEPSLP_BOD_PD (1 << 3) /*!< BOD power-down control in Deep-sleep mode, powered down */ -#define SYSCTL_DEEPSLP_WDTOSC_PD (1 << 6) /*!< Watchdog oscillator power control in Deep-sleep, powered down */ - -/** - * Deep sleep to wakeup and power state setup values - */ -#define SYSCTL_SLPWAKE_IRCOUT_PD (1 << 0) /*!< IRC oscillator output wake-up configuration */ -#define SYSCTL_SLPWAKE_IRC_PD (1 << 1) /*!< IRC oscillator power-down wake-up configuration */ -#define SYSCTL_SLPWAKE_FLASH_PD (1 << 2) /*!< Flash wake-up configuration */ -#define SYSCTL_SLPWAKE_BOD_PD (1 << 3) /*!< BOD wake-up configuration */ -#define SYSCTL_SLPWAKE_ADC_PD (1 << 4) /*!< ADC wake-up configuration [Available only on LPC82x] */ -#define SYSCTL_SLPWAKE_SYSOSC_PD (1 << 5) /*!< System oscillator wake-up configuration */ -#define SYSCTL_SLPWAKE_WDTOSC_PD (1 << 6) /*!< Watchdog oscillator wake-up configuration */ -#define SYSCTL_SLPWAKE_SYSPLL_PD (1 << 7) /*!< System PLL wake-up configuration */ -#define SYSCTL_SLPWAKE_ACMP_PD (1 << 15) /*!< Analog comparator wake-up configuration */ - -/** - * Non-Maskable Interrupt Enable/Disable value - */ -#define SYSCTL_NMISRC_ENABLE ((uint32_t) 1 << 31) /*!< Enable the Non-Maskable Interrupt (NMI) source */ - -/** - * @brief LPC8XX System Control and Clock register block structure - */ -typedef struct { - __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */ - __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */ - __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */ - __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/W ) */ - uint32_t RESERVED0[4]; - __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */ - __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */ - __IO uint32_t IRCCTRL; /*!< Offset: 0x028 IRC Control Register (Available only in LPC82X) */ - uint32_t RESERVED1[1]; - __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/W ) */ - uint32_t RESERVED2[3]; - __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */ - __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */ - uint32_t RESERVED3[10]; - __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */ - __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */ - __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */ - uint32_t RESERVED4[1]; - __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */ - uint32_t RESERVED5[4]; - __IO uint32_t UARTCLKDIV; /*!< Offset: 0x094 UART clock divider (R/W) */ - uint32_t RESERVED6[18]; - __IO uint32_t CLKOUTSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */ - __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */ - __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */ - uint32_t RESERVED7; - __IO uint32_t UARTFRGDIV; /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */ - __IO uint32_t UARTFRGMULT; /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */ - uint32_t RESERVED8[1]; - __IO uint32_t EXTTRACECMD; /*!< Offset: 0x0FC External trace buffer command register */ - __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */ - uint32_t RESERVED9[12]; - __IO uint32_t IOCONCLKDIV[7]; /*!< Offset: 0x134 Peripheral clock x to the IOCON block for programmable glitch filter */ - __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */ - __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */ - uint32_t RESERVED10[6]; - __IO uint32_t IRQLATENCY; /*!< Offset: 0x170 IRQ delay */ - __IO uint32_t NMISRC; /*!< Offset: 0x174 NMI Source Control */ - __IO uint32_t PINTSEL[8]; /*!< Offset: 0x178 GPIO Pin Interrupt Select register 0 */ - uint32_t RESERVED11[27]; - __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */ - uint32_t RESERVED12[3]; - __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */ - uint32_t RESERVED13[6]; - __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */ - __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */ - __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */ - uint32_t RESERVED14[111]; - __I uint32_t DEVICEID; /*!< Offset: 0x3F8 Device ID (R/ ) */ -} LPC_SYSCTL_T; - -/** - * @brief IOCON Perpipheral Clock divider selction for input filter - * sampling clock - */ -typedef enum CHIP_PIN_CLKDIV { - IOCONCLKDIV0 = 0, /*!< Clock divider 0 */ - IOCONCLKDIV1, /*!< Clock divider 1 */ - IOCONCLKDIV2, /*!< Clock divider 2 */ - IOCONCLKDIV3, /*!< Clock divider 3 */ - IOCONCLKDIV4, /*!< Clock divider 4 */ - IOCONCLKDIV5, /*!< Clock divider 5 */ - IOCONCLKDIV6, /*!< Clock divider 6 */ - IOCONCLK_MAX = IOCONCLKDIV6 /*!< Top value used to reverse the dividers */ -} CHIP_PIN_CLKDIV_T; - -/* Reserved bits masks for registers */ -#define SYSCTL_SYSMEMREMAP_RESERVED (~3) -#define SYSCTL_SYSPLLCTRL_RESERVED (~0x7f) -#define SYSCTL_SYSPLLSTAT_RESERVED (~1) -#define SYSCTL_SYSOSCCTRL_RESERVED (~3) -#define SYSCTL_WDTOSCCTRL_RESERVED (~0x1ff) -#define SYSCTL_SYSRSTSTAT_RESERVED (~0x1f) -#define SYSCTL_SYSPLLCLKSEL_RESERVED (~3) -#define SYSCTL_SYSPLLCLKUEN_RESERVED (~1) -#define SYSCTL_MAINCLKSEL_RESERVED (~3) -#define SYSCTL_MAINCLKUEN_RESERVED (~1) -#define SYSCTL_SYSAHBCLKDIV_RESERVED (~0xff) -#define SYSCTL_UARTCLKDIV_RESERVED (~0xff) -#define SYSCTL_CLKOUTSEL_RESERVED (~3) -#define SYSCTL_CLKOUTUEN_RESERVED (~1) -#define SYSCTL_CLKOUTDIV_RESERVED (~0xff) -#define SYSCTL_UARTFRGDIV_RESERVED (~0xff) -#define SYSCTL_UARTFRGMULT_RESERVED (~0xff) -#define SYSCTL_EXTTRACECMD_RESERVED (~3) -#define SYSCTL_IOCONCLKDIV_RESERVED (~0xff) -#define SYSCTL_BODCTRL_RESERVED (~0x1f) -#define SYSCTL_SYSTCKCAL_RESERVED 0xfc000000 -#define SYSCTL_IRQLATENCY_RESERVED (~0xff) -#define SYSCTL_NMISRC_RESERVED (~(0x1f|(1u<<31))) -#define SYSCTL_PINTSEL_RESERVED (~0x3f) -#define SYSCTL_STARTERP0_RESERVED (~0xff) -#if defined(CHIP_LPC82X) -#define SYSCTL_PRESETCTRL_RESERVED 0xfffe2000 -#define SYSCTL_SYSAHBCLKCTRL_RESERVED 0xda100000 -#define SYSCTL_PIOPORCAP0_RESERVED 0xfffc0000 -#define SYSCTL_STARTERP1_RESERVED ((1<<2)|(1<<6)|(7<<9)|(1<<14)|0xff9f0000) -#else -#define SYSCTL_PRESETCTRL_RESERVED 0xffffe000 -#define SYSCTL_SYSAHBCLKCTRL_RESERVED 0xfff00000 -#define SYSCTL_PIOPORCAP0_RESERVED 0xffffc000 -#define SYSCTL_STARTERP1_RESERVED ((1<<2)|(3<<6)|(7<<9)|(1<<14)|(0x1f<<16)|0xff800000) -#endif -/* The following have reserved bits, but they are specially handled elsewhere. */ -/* #define SYSCTL_PDSLEEPCFG_RESERVED (~(1<<3)|(3<<4)|(1<<6)) */ -/* #define SYSCTL_PDAWAKECFG_RESERVED */ -/* #define SYSCTL_PDRUNCFG_RESERVED */ - -/** - * System memory remap modes used to remap interrupt vectors - */ -typedef enum CHIP_SYSCTL_BOOT_MODE_REMAP { - REMAP_BOOT_LOADER_MODE, /*!< Interrupt vectors are re-mapped to Boot ROM */ - REMAP_USER_RAM_MODE, /*!< Interrupt vectors are re-mapped to user Static RAM */ - REMAP_USER_FLASH_MODE /*!< Interrupt vectors are not re-mapped and reside in Flash */ -} CHIP_SYSCTL_BOOT_MODE_REMAP_T; - -/** - * Peripheral reset identifiers - */ -typedef enum { - RESET_SPI0, /*!< SPI0 reset control */ - RESET_SPI1, /*!< SPI1 reset control */ - RESET_UARTFBRG, /*!< UART fractional baud rate generator reset control */ - RESET_USART0, /*!< USART0 reset control */ - RESET_USART1, /*!< USART1 reset control */ - RESET_USART2, /*!< USART2 reset control */ - RESET_I2C0, /*!< I2C0 reset control */ - RESET_MRT, /*!< MRT reset control */ - RESET_SCT, /*!< SCT reset control */ - RESET_WKT, /*!< Self wake-up timer (WKT) control */ - RESET_GPIO, /*!< GPIO reset control */ - RESET_FLASH, /*!< FLASH reset control */ - RESET_ACMP, /*!< ACMP reset control */ - RESET_I2C1 = 14, /*!< I2C1 reset control [Available only in LPC82x] */ - RESET_I2C2, /*!< I2C2 reset control [Available only in LPC82x] */ - RESET_I2C3, /*!< I2C3 reset control [Available only in LPC82x] */ -} CHIP_SYSCTL_PERIPH_RESET_T; - -/* Reset Alias */ -#define RESET_I2C RESET_I2C0 - -/** - * Brown-out detector reset level - */ -typedef enum CHIP_SYSCTL_BODRSTLVL { - SYSCTL_BODRSTLVL_0, /*!< Brown-out reset at 1.46 ~ 1.63v */ - SYSCTL_BODRSTLVL_1, /*!< Brown-out reset at 2.06v ~ 2.15v */ - SYSCTL_BODRSTLVL_2, /*!< Brown-out reset at 2.35v ~ 2.43v */ - SYSCTL_BODRSTLVL_3, /*!< Brown-out reset at 2.63v ~ 2.71v */ -} CHIP_SYSCTL_BODRSTLVL_T; - -/** - * Brown-out detector interrupt level - */ -typedef enum CHIP_SYSCTL_BODRINTVAL { - SYSCTL_BODINTVAL_LVL0, /* Brown-out interrupt at 1.65 ~ 1.80v */ - SYSCTL_BODINTVAL_LVL1, /* Brown-out interrupt at 2.22v ~ 2.35v*/ - SYSCTL_BODINTVAL_LVL2, /* Brown-out interrupt at 2.52v ~ 2.66v */ - SYSCTL_BODINTVAL_LVL3, /* Brown-out interrupt at 2.80v ~ 2.90v */ -} CHIP_SYSCTL_BODRINTVAL_T; - -/** - * @brief Re-map interrupt vectors - * @param remap : system memory map value - * @return Nothing - */ -STATIC INLINE void Chip_SYSCTL_Map(CHIP_SYSCTL_BOOT_MODE_REMAP_T remap) -{ - LPC_SYSCTL->SYSMEMREMAP = (uint32_t) remap; -} - -/** - * @brief Assert reset for a peripheral - * @param periph : Peripheral to assert reset for - * @return Nothing - * @note The peripheral will stay in reset until reset is de-asserted. Call - * Chip_SYSCTL_DeassertPeriphReset() to de-assert the reset - */ -STATIC INLINE void Chip_SYSCTL_AssertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph) -{ - LPC_SYSCTL->PRESETCTRL &= ~((1 << (uint32_t) periph) | SYSCTL_PRESETCTRL_RESERVED); -} - -/** - * @brief De-assert reset for a peripheral - * @param periph : Peripheral to de-assert reset for - * @return Nothing - */ -STATIC INLINE void Chip_SYSCTL_DeassertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph) -{ - LPC_SYSCTL->PRESETCTRL = (1 << (uint32_t) periph) | (LPC_SYSCTL->PRESETCTRL & ~SYSCTL_PRESETCTRL_RESERVED); -} - -/** - * @brief Resets a peripheral - * @param periph : Peripheral to reset - * @return Nothing - */ -STATIC INLINE void Chip_SYSCTL_PeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph) -{ - Chip_SYSCTL_AssertPeriphReset(periph); - Chip_SYSCTL_DeassertPeriphReset(periph); -} - -/** - * @brief Get system reset status - * @return An Or'ed value of SYSCTL_RST_* - * @note This function returns the detected reset source(s). - */ -STATIC INLINE uint32_t Chip_SYSCTL_GetSystemRSTStatus(void) -{ - return LPC_SYSCTL->SYSRSTSTAT & ~SYSCTL_SYSRSTSTAT_RESERVED; -} - -/** - * @brief Clear system reset status - * @param reset : An Or'ed value of SYSCTL_RST_* status to clear - * @return Nothing - * @note This function clears the specified reset source(s). - */ -STATIC INLINE void Chip_SYSCTL_ClearSystemRSTStatus(uint32_t reset) -{ - LPC_SYSCTL->SYSRSTSTAT = reset; -} - -/** - * @brief Read POR captured PIO status - * @return captured POR PIO status - * @note Some devices only support index 0. - */ -STATIC INLINE uint32_t Chip_SYSCTL_GetPORPIOStatus(void) -{ - return LPC_SYSCTL->PIOPORCAP0 & ~SYSCTL_PIOPORCAP0_RESERVED; -} - -/** - * @brief Set brown-out detection interrupt and reset levels - * @param rstlvl : Brown-out detector reset level - * @param intlvl : Brown-out interrupt level - * @return Nothing - * @note Brown-out detection reset will be disabled upon exiting this function. - * Use Chip_SYSCTL_EnableBODReset() to re-enable - */ -STATIC INLINE void Chip_SYSCTL_SetBODLevels(CHIP_SYSCTL_BODRSTLVL_T rstlvl, - CHIP_SYSCTL_BODRINTVAL_T intlvl) -{ - LPC_SYSCTL->BODCTRL = ((uint32_t) rstlvl) | (((uint32_t) intlvl) << 2); -} - -/** - * @brief Enable brown-out detection reset - * @return Nothing - */ -STATIC INLINE void Chip_SYSCTL_EnableBODReset(void) -{ - LPC_SYSCTL->BODCTRL = (1 << 4) | (LPC_SYSCTL->BODCTRL & ~SYSCTL_BODCTRL_RESERVED); -} - -/** - * @brief Disable brown-out detection reset - * @return Nothing - */ -STATIC INLINE void Chip_SYSCTL_DisableBODReset(void) -{ - LPC_SYSCTL->BODCTRL &= ~((1 << 4) | SYSCTL_BODCTRL_RESERVED); -} - -/** - * @brief Set System tick timer calibration value - * @param sysCalVal : System tick timer calibration value - * @return Nothing - */ -STATIC INLINE void Chip_SYSCTL_SetSYSTCKCAL(uint32_t sysCalVal) -{ - LPC_SYSCTL->SYSTCKCAL = sysCalVal; -} - -/** - * @brief Set System IRQ latency - * @param latency : Latency in clock ticks - * @return Nothing - * @note Sets the IRQ latency, a value between 0 and 255 clocks. Lower - * values allow better latency - */ -STATIC INLINE void Chip_SYSCTL_SetIRQLatency(uint32_t latency) -{ - LPC_SYSCTL->IRQLATENCY = latency; -} - -/** - * @brief Get System IRQ latency value - * @return IRQ Latency in clock ticks - */ -STATIC INLINE uint32_t Chip_SYSCTL_GetIRQLatency(void) -{ - return LPC_SYSCTL->IRQLATENCY & ~SYSCTL_IRQLATENCY_RESERVED; -} - -/** - * @brief Set source for non-maskable interrupt (NMI) - * @param intsrc : IRQ number to assign to the NMI - * @return Nothing - * @note The NMI source will be disabled upon exiting this function. Use the - * Chip_SYSCTL_EnableNMISource() function to enable the NMI source - */ -STATIC INLINE void Chip_SYSCTL_SetNMISource(uint32_t intsrc) -{ - /* Disable NMI first */ - LPC_SYSCTL->NMISRC &= ~(SYSCTL_NMISRC_ENABLE | SYSCTL_NMISRC_RESERVED); - - /* Set new NMI source. */ - LPC_SYSCTL->NMISRC = intsrc; -} - -/** - * @brief Enable interrupt used for NMI source - * @return Nothing - */ -STATIC INLINE void Chip_SYSCTL_EnableNMISource(void) -{ - LPC_SYSCTL->NMISRC = SYSCTL_NMISRC_ENABLE | (LPC_SYSCTL->NMISRC & ~SYSCTL_NMISRC_RESERVED); -} - -/** - * @brief Disable interrupt used for NMI source - * @return Nothing - */ -STATIC INLINE void Chip_SYSCTL_DisableNMISource(void) -{ - LPC_SYSCTL->NMISRC &= ~(SYSCTL_NMISRC_ENABLE | SYSCTL_NMISRC_RESERVED); -} - -/** - * @brief Setup a pin source for the pin interrupts (0-7) - * @param intno : IRQ number - * @param pin : pin number (see comments) - * @return Nothing - * @note For each pin (0-7) that supports an interrupt, the pin number is assigned - * to that interrupt with this function. Values 0-17 map to pins PIO0-0 to - * PIO0-17 (For LPC82X Values from 0-28 could be used for PIO0-28). - */ -STATIC INLINE void Chip_SYSCTL_SetPinInterrupt(uint32_t intIndex, uint32_t pinNum) -{ - LPC_SYSCTL->PINTSEL[intIndex] = (uint32_t) pinNum; -} - -/** - * @brief Enables a pin's (PINT) wakeup logic - * @param pin : pin number - * @return Nothing - * @note Different devices support different pins, see the user manual - * for supported pins - */ -STATIC INLINE void Chip_SYSCTL_EnablePINTWakeup(uint32_t pin) -{ - LPC_SYSCTL->STARTERP0 = (1 << pin) | (LPC_SYSCTL->STARTERP0 & ~SYSCTL_STARTERP0_RESERVED); -} - -/** - * @brief Disables a pin's (PINT) wakeup logic - * @param pin : pin number - * @return Nothing - * @note Different devices support different pins, see the user manual for supported pins. - */ -STATIC INLINE void Chip_SYSCTL_DisablePINTWakeup(uint32_t pin) -{ - LPC_SYSCTL->STARTERP0 &= ~((1 << pin) | SYSCTL_STARTERP0_RESERVED); -} - -/** - * @brief Enables peripheral's wakeup logic - * @param periphmask : OR'ed values of SYSCTL_WAKEUP_* for wakeup - * @return Nothing - */ -STATIC INLINE void Chip_SYSCTL_EnablePeriphWakeup(uint32_t periphmask) -{ - LPC_SYSCTL->STARTERP1 = periphmask | (LPC_SYSCTL->STARTERP0 & ~SYSCTL_STARTERP0_RESERVED); -} - -/** - * @brief Disables peripheral's wakeup logic - * @param periphmask : OR'ed values of SYSCTL_WAKEUP_* for wakeup - * @return Nothing - */ -STATIC INLINE void Chip_SYSCTL_DisablePeriphWakeup(uint32_t periphmask) -{ - LPC_SYSCTL->STARTERP1 &= ~(periphmask | SYSCTL_STARTERP1_RESERVED); -} - -/** - * @brief Returns current deep sleep mask - * @return OR'ed values of SYSCTL_DEEPSLP_* values - * @note A high bit indicates the peripheral will power down on deep sleep. - */ -STATIC INLINE uint32_t Chip_SYSCTL_GetDeepSleepPD(void) -{ - return LPC_SYSCTL->PDSLEEPCFG; -} - -/** - * @brief Return current wakup mask - * @return OR'ed values of SYSCTL_SLPWAKE_* values - * @note A high state indicates the peripehral will powerup on wakeup. - */ -STATIC INLINE uint32_t Chip_SYSCTL_GetWakeup(void) -{ - return LPC_SYSCTL->PDAWAKECFG; -} - -/** - * @brief Power up one or more blocks or peripherals - * @return OR'ed values of SYSCTL_SLPWAKE_* values - * @note A high state indicates the peripheral is powered down. - */ -STATIC INLINE uint32_t Chip_SYSCTL_GetPowerStates(void) -{ - return LPC_SYSCTL->PDRUNCFG; -} - -/** - * @brief Return the device ID - * @return Device ID - */ -STATIC INLINE uint32_t Chip_SYSCTL_GetDeviceID(void) -{ - return LPC_SYSCTL->DEVICEID; -} - -/** - * @brief Setup deep sleep behaviour for power down - * @param sleepmask : OR'ed values of SYSCTL_DEEPSLP_* values (high to powerdown on deepsleep) - * @return Nothing - * @note This must be setup prior to using deep sleep. See the user manual - * *(PDSLEEPCFG register) for more info on setting this up. This function selects - * which peripherals are powered down on deep sleep. - * This function should only be called once with all options for power-down - * in that call - */ -void Chip_SYSCTL_SetDeepSleepPD(uint32_t sleepmask); - -/** - * @brief Setup wakeup behaviour from deep sleep - * @param wakeupmask : OR'ed values of SYSCTL_SLPWAKE_* values (high is powered down) - * @return Nothing - * @note This must be setup prior to using deep sleep. See the user manual - * *(PDWAKECFG register) for more info on setting this up. This function selects - * which peripherals are powered up on exit from deep sleep. - * This function should only be called once with all options for wakeup - * in that call - */ -void Chip_SYSCTL_SetWakeup(uint32_t wakeupmask); - -/** - * @brief Power down one or more blocks or peripherals - * @param powerdownmask : OR'ed values of SYSCTL_SLPWAKE_* values - * @return Nothing - */ -void Chip_SYSCTL_PowerDown(uint32_t powerdownmask); - -/** - * @brief Power up one or more blocks or peripherals - * @param powerupmask : OR'ed values of SYSCTL_SLPWAKE_* values - * @return Nothing - */ -void Chip_SYSCTL_PowerUp(uint32_t powerupmask); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSCTL_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/chip/sysinit_8xx.c b/bsp/nxp/lpc/lpc824/Libraries/common/chip/sysinit_8xx.c deleted file mode 100644 index e0b7e180106..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/chip/sysinit_8xx.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * @brief LPC8xx Chip specific SystemInit - * - * @note - * Copyright(C) NXP Semiconductors, 2013 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ -#define _CHIP_COMMON_ -#include "board_lpc.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ -#define CONFIG_MAIN_FREQ 60000000 -#define CONFIG_SYS_FREQ MAX_CLOCK_FREQ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Setup system clocking */ -void Chip_SetupXtalClocking(void) -{ - /* EXT oscillator < 15MHz */ - Chip_Clock_SetPLLBypass(false, false); - - /* Turn on the SYSOSC by clearing the power down bit */ - Chip_SYSCTL_PowerUp(SYSCTL_SLPWAKE_SYSOSC_PD); - - /* Select the PLL input to the external oscillator */ - Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_SYSOSC); - - /* Setup FLASH access to 2 clocks (up to 30MHz) */ - Chip_FMC_SetFLASHAccess(FLASHTIM_30MHZ_CPU); - - /* Power down PLL to change the PLL divider ratio */ - Chip_SYSCTL_PowerDown(SYSCTL_SLPWAKE_SYSPLL_PD); - - /* Configure the PLL M and P dividers */ - /* Setup PLL for main oscillator rate ((FCLKIN = 12MHz) * 5)/2 = 30MHz */ - Chip_Clock_SetupSystemPLL(4, 1); - - /* Turn on the PLL by clearing the power down bit */ - Chip_SYSCTL_PowerUp(SYSCTL_SLPWAKE_SYSPLL_PD); - -/* Enable the clock to the Switch Matrix */ - Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM); - - /* Wait for PLL to lock */ - while (!Chip_Clock_IsSystemPLLLocked()) {} - - Chip_Clock_SetSysClockDiv(2); - - /* Set main clock source to the system PLL. This will drive 24MHz - for the main clock and 24MHz for the system clock */ - Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT); -} - -/* Set up and initialize hardware prior to call to main */ -void Chip_SetupIrcClocking(void) -{ - Chip_IRC_SetFreq(CONFIG_MAIN_FREQ, CONFIG_SYS_FREQ); -} - -/* Set up and initialize hardware prior to call to main */ -/* ÔÚmain()º¯Êý֮ǰµ÷Óô˺¯Êý×ö»ù±¾µÄ³õʼ»¯¹¤×÷ */ -void SystemInit(void) -{ - Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON); - #ifdef USE_IRC_AS_ROOT_CLOCK - /* Use 12MHz IRC as clock source */ - Chip_SetupIrcClocking(); - #else - /* Use Xtal or external clock_in as clock source*/ - Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM); - Chip_SWM_EnableFixedPin(SWM_FIXED_XTALIN); - Chip_SWM_EnableFixedPin(SWM_FIXED_XTALOUT); - // Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SWM); - Chip_IOCON_PinSetMode(LPC_IOCON, IOCON_PIO8, PIN_MODE_INACTIVE); - Chip_IOCON_PinSetMode(LPC_IOCON, IOCON_PIO9, PIN_MODE_INACTIVE); - - Chip_SetupXtalClocking(); - #endif -} diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/startup/gcc_startup_lpc82x.S b/bsp/nxp/lpc/lpc824/Libraries/common/startup/gcc_startup_lpc82x.S deleted file mode 100644 index 136b78beecb..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/startup/gcc_startup_lpc82x.S +++ /dev/null @@ -1,557 +0,0 @@ -/* ------------------------------------------------------------------------- */ -/* @file: startup_LPC824.s */ -/* @purpose: CMSIS Cortex-M0P Core Device Startup File */ -/* LPC824 */ -/* @version: 1.1 */ -/* @date: 2018-2-25 */ -/* @build: b231018 */ -/* ------------------------------------------------------------------------- */ -/* */ -/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2023 NXP */ -/* SPDX-License-Identifier: BSD-3-Clause */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - .syntax unified - .arch armv6-m - - .section .isr_vector, "a" - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts*/ - .long SPI0_IRQHandler /* SPI0 interrupt*/ - .long SPI1_IRQHandler /* SPI1 interrupt*/ - .long Reserved18_IRQHandler /* Reserved interrupt*/ - .long USART0_IRQHandler /* USART0 interrupt*/ - .long USART1_IRQHandler /* USART1 interrupt*/ - .long USART2_IRQHandler /* USART2 interrupt*/ - .long Reserved22_IRQHandler /* Reserved interrupt*/ - .long I2C1_IRQHandler /* I2C1 interrupt*/ - .long I2C0_IRQHandler /* I2C0 interrupt*/ - .long SCT0_IRQHandler /* State configurable timer interrupt*/ - .long MRT0_IRQHandler /* Multi-rate timer interrupt*/ - .long CMP_IRQHandler /* Analog comparator interrupt*/ - .long WDT_IRQHandler /* Windowed watchdog timer interrupt*/ - .long BOD_IRQHandler /* BOD interrupts*/ - .long FLASH_IRQHandler /* flash interrupt*/ - .long WKT_IRQHandler /* Self-wake-up timer interrupt*/ - .long ADC0_SEQA_IRQHandler /* ADC0 sequence A completion.*/ - .long ADC0_SEQB_IRQHandler /* ADC0 sequence B completion.*/ - .long ADC0_THCMP_IRQHandler /* ADC0 threshold compare and error.*/ - .long ADC0_OVR_IRQHandler /* ADC0 overrun*/ - .long DMA0_IRQHandler /* DMA0 interrupt*/ - .long I2C2_IRQHandler /* I2C2 interrupt*/ - .long I2C3_IRQHandler /* I2C3 interrupt*/ - .long Reserved39_IRQHandler /* Reserved interrupt*/ - .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 interrupt*/ - .long PIN_INT1_IRQHandler /* Pin interrupt 1 or pattern match engine slice 1 interrupt*/ - .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 interrupt*/ - .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 interrupt*/ - .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 interrupt*/ - .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 interrupt*/ - .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 interrupt*/ - .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 interrupt*/ - - .size __Vectors, . - __Vectors - -/* Variable to store CRP value in. No code read protection enabled by default - * Code Read Protection level (CRP) - * CRP_Level: - * <0xFFFFFFFF=> Disabled - * <0x4E697370=> NO_ISP - * <0x12345678=> CRP1 - * <0x87654321=> CRP2 - * <0x43218765=> CRP3 - */ - #ifndef NO_CRP - .section .crp, "a" - .long 0xFFFFFFFF - #endif - - .text - .thumb - -#if defined (__cplusplus) -#ifdef __REDLIB__ -#error Redlib does not support C++ -#endif -#endif -/* Reset Handler */ - - .thumb_func - .align 2 - .globl Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - cpsid i /* Mask interrupts */ -#ifndef __NO_SYSTEM_INIT - ldr r0,=SystemInit - blx r0 -#endif -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .LC0 - -.LC1: - subs r3, 4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .LC1 -.LC0: - -#ifdef __STARTUP_CLEAR_BSS -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * Loop to zero out BSS section, which uses following symbols - * in linker script: - * __bss_start__: start of BSS section. Must align to 4 - * __bss_end__: end of BSS section. Must align to 4 - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - subs r2, r1 - ble .LC3 - - movs r0, 0 -.LC2: - subs r2, 4 - str r0, [r1, r2] - bgt .LC2 -.LC3: -#endif - cpsie i /* Unmask interrupts */ -#ifndef __START -#ifdef __REDLIB__ -#define __START __main -#else -#define __START entry -#endif -#endif -#ifndef __ATOLLIC__ - ldr r0,=__START - blx r0 -#else - ldr r0,=__libc_init_array - blx r0 - ldr r0,=entry - bx r0 -#endif - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - ldr r0, =DefaultISR - bx r0 - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - - .align 1 - .thumb_func - .weak SPI0_IRQHandler - .type SPI0_IRQHandler, %function -SPI0_IRQHandler: - ldr r0,=SPI0_DriverIRQHandler - bx r0 - .size SPI0_IRQHandler, . - SPI0_IRQHandler - - .align 1 - .thumb_func - .weak SPI1_IRQHandler - .type SPI1_IRQHandler, %function -SPI1_IRQHandler: - ldr r0,=SPI1_DriverIRQHandler - bx r0 - .size SPI1_IRQHandler, . - SPI1_IRQHandler - - .align 1 - .thumb_func - .weak Reserved18_IRQHandler - .type Reserved18_IRQHandler, %function -Reserved18_IRQHandler: - ldr r0,=Reserved18_DriverIRQHandler - bx r0 - .size Reserved18_IRQHandler, . - Reserved18_IRQHandler - - .align 1 - .thumb_func - .weak USART0_IRQHandler - .type USART0_IRQHandler, %function -USART0_IRQHandler: - ldr r0,=USART0_DriverIRQHandler - bx r0 - .size USART0_IRQHandler, . - USART0_IRQHandler - - .align 1 - .thumb_func - .weak USART1_IRQHandler - .type USART1_IRQHandler, %function -USART1_IRQHandler: - ldr r0,=USART1_DriverIRQHandler - bx r0 - .size USART1_IRQHandler, . - USART1_IRQHandler - - .align 1 - .thumb_func - .weak USART2_IRQHandler - .type USART2_IRQHandler, %function -USART2_IRQHandler: - ldr r0,=USART2_DriverIRQHandler - bx r0 - .size USART2_IRQHandler, . - USART2_IRQHandler - - .align 1 - .thumb_func - .weak Reserved22_IRQHandler - .type Reserved22_IRQHandler, %function -Reserved22_IRQHandler: - ldr r0,=Reserved22_DriverIRQHandler - bx r0 - .size Reserved22_IRQHandler, . - Reserved22_IRQHandler - - .align 1 - .thumb_func - .weak I2C1_IRQHandler - .type I2C1_IRQHandler, %function -I2C1_IRQHandler: - ldr r0,=I2C1_DriverIRQHandler - bx r0 - .size I2C1_IRQHandler, . - I2C1_IRQHandler - - .align 1 - .thumb_func - .weak I2C0_IRQHandler - .type I2C0_IRQHandler, %function -I2C0_IRQHandler: - ldr r0,=I2C0_DriverIRQHandler - bx r0 - .size I2C0_IRQHandler, . - I2C0_IRQHandler - - .align 1 - .thumb_func - .weak SCT0_IRQHandler - .type SCT0_IRQHandler, %function -SCT0_IRQHandler: - ldr r0,=SCT0_DriverIRQHandler - bx r0 - .size SCT0_IRQHandler, . - SCT0_IRQHandler - - .align 1 - .thumb_func - .weak MRT0_IRQHandler - .type MRT0_IRQHandler, %function -MRT0_IRQHandler: - ldr r0,=MRT0_DriverIRQHandler - bx r0 - .size MRT0_IRQHandler, . - MRT0_IRQHandler - - .align 1 - .thumb_func - .weak CMP_IRQHandler - .type CMP_IRQHandler, %function -CMP_IRQHandler: - ldr r0,=CMP_DriverIRQHandler - bx r0 - .size CMP_IRQHandler, . - CMP_IRQHandler - - .align 1 - .thumb_func - .weak WDT_IRQHandler - .type WDT_IRQHandler, %function -WDT_IRQHandler: - ldr r0,=WDT_DriverIRQHandler - bx r0 - .size WDT_IRQHandler, . - WDT_IRQHandler - - .align 1 - .thumb_func - .weak BOD_IRQHandler - .type BOD_IRQHandler, %function -BOD_IRQHandler: - ldr r0,=BOD_DriverIRQHandler - bx r0 - .size BOD_IRQHandler, . - BOD_IRQHandler - - .align 1 - .thumb_func - .weak FLASH_IRQHandler - .type FLASH_IRQHandler, %function -FLASH_IRQHandler: - ldr r0,=FLASH_DriverIRQHandler - bx r0 - .size FLASH_IRQHandler, . - FLASH_IRQHandler - - .align 1 - .thumb_func - .weak WKT_IRQHandler - .type WKT_IRQHandler, %function -WKT_IRQHandler: - ldr r0,=WKT_DriverIRQHandler - bx r0 - .size WKT_IRQHandler, . - WKT_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_SEQA_IRQHandler - .type ADC0_SEQA_IRQHandler, %function -ADC0_SEQA_IRQHandler: - ldr r0,=ADC0_SEQA_DriverIRQHandler - bx r0 - .size ADC0_SEQA_IRQHandler, . - ADC0_SEQA_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_SEQB_IRQHandler - .type ADC0_SEQB_IRQHandler, %function -ADC0_SEQB_IRQHandler: - ldr r0,=ADC0_SEQB_DriverIRQHandler - bx r0 - .size ADC0_SEQB_IRQHandler, . - ADC0_SEQB_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_THCMP_IRQHandler - .type ADC0_THCMP_IRQHandler, %function -ADC0_THCMP_IRQHandler: - ldr r0,=ADC0_THCMP_DriverIRQHandler - bx r0 - .size ADC0_THCMP_IRQHandler, . - ADC0_THCMP_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_OVR_IRQHandler - .type ADC0_OVR_IRQHandler, %function -ADC0_OVR_IRQHandler: - ldr r0,=ADC0_OVR_DriverIRQHandler - bx r0 - .size ADC0_OVR_IRQHandler, . - ADC0_OVR_IRQHandler - - .align 1 - .thumb_func - .weak DMA0_IRQHandler - .type DMA0_IRQHandler, %function -DMA0_IRQHandler: - ldr r0,=DMA0_DriverIRQHandler - bx r0 - .size DMA0_IRQHandler, . - DMA0_IRQHandler - - .align 1 - .thumb_func - .weak I2C2_IRQHandler - .type I2C2_IRQHandler, %function -I2C2_IRQHandler: - ldr r0,=I2C2_DriverIRQHandler - bx r0 - .size I2C2_IRQHandler, . - I2C2_IRQHandler - - .align 1 - .thumb_func - .weak I2C3_IRQHandler - .type I2C3_IRQHandler, %function -I2C3_IRQHandler: - ldr r0,=I2C3_DriverIRQHandler - bx r0 - .size I2C3_IRQHandler, . - I2C3_IRQHandler - - .align 1 - .thumb_func - .weak Reserved39_IRQHandler - .type Reserved39_IRQHandler, %function -Reserved39_IRQHandler: - ldr r0,=Reserved39_DriverIRQHandler - bx r0 - .size Reserved39_IRQHandler, . - Reserved39_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT0_IRQHandler - .type PIN_INT0_IRQHandler, %function -PIN_INT0_IRQHandler: - ldr r0,=PIN_INT0_DriverIRQHandler - bx r0 - .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT1_IRQHandler - .type PIN_INT1_IRQHandler, %function -PIN_INT1_IRQHandler: - ldr r0,=PIN_INT1_DriverIRQHandler - bx r0 - .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT2_IRQHandler - .type PIN_INT2_IRQHandler, %function -PIN_INT2_IRQHandler: - ldr r0,=PIN_INT2_DriverIRQHandler - bx r0 - .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT3_IRQHandler - .type PIN_INT3_IRQHandler, %function -PIN_INT3_IRQHandler: - ldr r0,=PIN_INT3_DriverIRQHandler - bx r0 - .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT4_IRQHandler - .type PIN_INT4_IRQHandler, %function -PIN_INT4_IRQHandler: - ldr r0,=PIN_INT4_DriverIRQHandler - bx r0 - .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT5_IRQHandler - .type PIN_INT5_IRQHandler, %function -PIN_INT5_IRQHandler: - ldr r0,=PIN_INT5_DriverIRQHandler - bx r0 - .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT6_IRQHandler - .type PIN_INT6_IRQHandler, %function -PIN_INT6_IRQHandler: - ldr r0,=PIN_INT6_DriverIRQHandler - bx r0 - .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT7_IRQHandler - .type PIN_INT7_IRQHandler, %function -PIN_INT7_IRQHandler: - ldr r0,=PIN_INT7_DriverIRQHandler - bx r0 - .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler - - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm - def_irq_handler SPI0_DriverIRQHandler - def_irq_handler SPI1_DriverIRQHandler - def_irq_handler Reserved18_DriverIRQHandler - def_irq_handler USART0_DriverIRQHandler - def_irq_handler USART1_DriverIRQHandler - def_irq_handler USART2_DriverIRQHandler - def_irq_handler Reserved22_DriverIRQHandler - def_irq_handler I2C1_DriverIRQHandler - def_irq_handler I2C0_DriverIRQHandler - def_irq_handler SCT0_DriverIRQHandler - def_irq_handler MRT0_DriverIRQHandler - def_irq_handler CMP_DriverIRQHandler - def_irq_handler WDT_DriverIRQHandler - def_irq_handler BOD_DriverIRQHandler - def_irq_handler FLASH_DriverIRQHandler - def_irq_handler WKT_DriverIRQHandler - def_irq_handler ADC0_SEQA_DriverIRQHandler - def_irq_handler ADC0_SEQB_DriverIRQHandler - def_irq_handler ADC0_THCMP_DriverIRQHandler - def_irq_handler ADC0_OVR_DriverIRQHandler - def_irq_handler DMA0_DriverIRQHandler - def_irq_handler I2C2_DriverIRQHandler - def_irq_handler I2C3_DriverIRQHandler - def_irq_handler Reserved39_DriverIRQHandler - def_irq_handler PIN_INT0_DriverIRQHandler - def_irq_handler PIN_INT1_DriverIRQHandler - def_irq_handler PIN_INT2_DriverIRQHandler - def_irq_handler PIN_INT3_DriverIRQHandler - def_irq_handler PIN_INT4_DriverIRQHandler - def_irq_handler PIN_INT5_DriverIRQHandler - def_irq_handler PIN_INT6_DriverIRQHandler - def_irq_handler PIN_INT7_DriverIRQHandler - - .end diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/startup/iar_startup_lpc82x.s b/bsp/nxp/lpc/lpc824/Libraries/common/startup/iar_startup_lpc82x.s deleted file mode 100644 index 6794340b949..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/startup/iar_startup_lpc82x.s +++ /dev/null @@ -1,188 +0,0 @@ -/************************************************** - * - * Part one of the system initialization code, contains low-level - * initialization, plain thumb variant. - * - * Copyright 2009 IAR Systems. All rights reserved. - * - * $Revision: 33183 $ - * - **************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - EXTERN IRC_Only_SystemInit - - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - DATA -__vector_table - DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - - ; External Interrupts - DCD SPI0_IRQHandler ; SPI0 controller - DCD SPI1_IRQHandler ; SPI1 controller - DCD 0 ; Reserved - DCD UART0_IRQHandler ; UART0 - DCD UART1_IRQHandler ; UART1 - DCD UART2_IRQHandler ; UART2 - DCD 0 ; Reserved - DCD I2C1_IRQHandler ; I2C1 - DCD I2C0_IRQHandler ; I2C0 controller - DCD SCT_IRQHandler ; Smart Counter Timer - DCD MRT_IRQHandler ; Multi-Rate Timer - DCD CMP_IRQHandler ; Comparator - DCD WDT_IRQHandler ; PIO1 (0:11) - DCD BOD_IRQHandler ; Brown Out Detect - DCD FLASH_IRQHandler ; Flash interrupt - DCD WKT_IRQHandler ; Wakeup timer - DCD ADC_SEQA_IRQHandler ; ADC sequence A completeion - DCD ADC_SEQB_IRQHandler ; ADC sequence B completeion - DCD ADC_THCMP_IRQHandler ; ADC threshold compare - DCD ADC_OVR_IRQHandler ; ADC overrun - DCD DMA_IRQHandler ; DMA - DCD I2C2_IRQHandler ; I2C2 - DCD I2C3_IRQHandler ; I2C3 - DCD 0 ; Reserved - DCD PININT0_IRQHandler ; PIO INT0 - DCD PININT1_IRQHandler ; PIO INT1 - DCD PININT2_IRQHandler ; PIO INT2 - DCD PININT3_IRQHandler ; PIO INT3 - DCD PININT4_IRQHandler ; PIO INT4 - DCD PININT5_IRQHandler ; PIO INT5 - DCD PININT6_IRQHandler ; PIO INT6 - DCD PININT7_IRQHandler ; PIO INT7 - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - - - SECTION .text:CODE:REORDER:NOROOT(1) - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK SVC_Handler - PUBWEAK DebugMon_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - PUBWEAK SPI0_IRQHandler - PUBWEAK SPI1_IRQHandler - PUBWEAK UART0_IRQHandler - PUBWEAK UART1_IRQHandler - PUBWEAK UART2_IRQHandler - PUBWEAK I2C1_IRQHandler - PUBWEAK I2C0_IRQHandler - PUBWEAK SCT_IRQHandler - PUBWEAK MRT_IRQHandler - PUBWEAK CMP_IRQHandler - PUBWEAK WDT_IRQHandler - PUBWEAK BOD_IRQHandler - PUBWEAK FLASH_IRQHandler - PUBWEAK WKT_IRQHandler - PUBWEAK ADC_SEQA_IRQHandler - PUBWEAK ADC_SEQB_IRQHandler - PUBWEAK ADC_THCMP_IRQHandler - PUBWEAK ADC_OVR_IRQHandler - PUBWEAK DMA_IRQHandler - PUBWEAK I2C2_IRQHandler - PUBWEAK I2C3_IRQHandler - PUBWEAK PININT0_IRQHandler - PUBWEAK PININT1_IRQHandler - PUBWEAK PININT2_IRQHandler - PUBWEAK PININT3_IRQHandler - PUBWEAK PININT4_IRQHandler - PUBWEAK PININT5_IRQHandler - PUBWEAK PININT6_IRQHandler - PUBWEAK PININT7_IRQHandler - -NMI_Handler: -HardFault_Handler: -SVC_Handler: -DebugMon_Handler: -PendSV_Handler: -SysTick_Handler: -SPI0_IRQHandler: -SPI1_IRQHandler: -UART0_IRQHandler: -UART1_IRQHandler: -UART2_IRQHandler: -I2C1_IRQHandler: -I2C0_IRQHandler: -SCT_IRQHandler: -MRT_IRQHandler: -CMP_IRQHandler: -WDT_IRQHandler: -BOD_IRQHandler: -FLASH_IRQHandler: -WKT_IRQHandler: -ADC_SEQA_IRQHandler: -ADC_SEQB_IRQHandler: -ADC_THCMP_IRQHandler: -ADC_OVR_IRQHandler: -DMA_IRQHandler: -I2C2_IRQHandler: -I2C3_IRQHandler: -PININT0_IRQHandler: -PININT1_IRQHandler: -PININT2_IRQHandler: -PININT3_IRQHandler: -PININT4_IRQHandler: -PININT5_IRQHandler: -PININT6_IRQHandler: -PININT7_IRQHandler: -Default_Handler: - B Default_Handler - - END diff --git a/bsp/nxp/lpc/lpc824/Libraries/common/startup/keil_startup_lpc82x.s b/bsp/nxp/lpc/lpc824/Libraries/common/startup/keil_startup_lpc82x.s deleted file mode 100644 index 82f62ecf99c..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/common/startup/keil_startup_lpc82x.s +++ /dev/null @@ -1,260 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC8xx.s -; * @purpose: CMSIS Cortex-M0+ Core Device Startup File -; * for the NXP LPC8xx Device Series -; * @version: V1.0 -; * @date: 16. Aug. 2012 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000180 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD SPI0_IRQHandler ; SPI0 controller - DCD SPI1_IRQHandler ; SPI1 controller - DCD 0 ; Reserved - DCD UART0_IRQHandler ; UART0 - DCD UART1_IRQHandler ; UART1 - DCD UART2_IRQHandler ; UART2 - DCD 0 ; Reserved - DCD I2C1_IRQHandler ; I2C1 controller - DCD I2C0_IRQHandler ; I2C0 controller - DCD SCT_IRQHandler ; Smart Counter Timer - DCD MRT_IRQHandler ; Multi-Rate Timer - DCD CMP_IRQHandler ; Comparator - DCD WDT_IRQHandler ; PIO1 (0:11) - DCD BOD_IRQHandler ; Brown Out Detect - DCD FLASH_IRQHandler ; Non-Volatile Memory Controller - DCD WKT_IRQHandler ; Wakeup timer - DCD ADC_SEQA_IRQHandler ; ADC Sequence A Completion [Only on LPC82X] - DCD ADC_SEQB_IRQHanlder ; ADC Sequence B Completion [Only on LPC82X] - DCD ADC_THCMP_IRQHandler ; ADC Threshold compare [Only on LPC82X] - DCD ADC_OVR_IRQHandler ; ADC Overrun [Only on LPC82X] - DCD DMA_IRQHandler ; DMA Controller [Only on LPC82X] - DCD I2C2_IRQHandler ; I2C2 Controller [Only on LPC82X] - DCD I2C3_IRQHandler ; I2C3 Controller [Only on LPC82X] - DCD 0 ; Reserved - DCD PIN_INT0_IRQHandler ; PIO INT0 - DCD PIN_INT1_IRQHandler ; PIO INT1 - DCD PIN_INT2_IRQHandler ; PIO INT2 - DCD PIN_INT3_IRQHandler ; PIO INT3 - DCD PIN_INT4_IRQHandler ; PIO INT4 - DCD PIN_INT5_IRQHandler ; PIO INT5 - DCD PIN_INT6_IRQHandler ; PIO INT6 - DCD PIN_INT7_IRQHandler ; PIO INT7 - -;// Code Read Protection level (CRP) -;// CRP_Level: -;// <0xFFFFFFFF=> Disabled -;// <0x4E697370=> NO_ISP -;// <0x12345678=> CRP1 -;// <0x87654321=> CRP2 -;// <0x43218765=> CRP3 (Are you sure?) -;// -CRP_Level EQU 0xFFFFFFFF - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, = SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) -; now, under COMMON lpc8xx_nmi.c and lpc8xx_nmi.h, a real NMI handler is created if NMI is enabled -; for particular peripheral. -;NMI_Handler PROC -; EXPORT NMI_Handler [WEAK] -; B . -; ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT NMI_Handler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT SCT_IRQHandler [WEAK] - EXPORT MRT_IRQHandler [WEAK] - EXPORT CMP_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT WKT_IRQHandler [WEAK] - EXPORT PIN_INT0_IRQHandler [WEAK] - EXPORT PIN_INT1_IRQHandler [WEAK] - EXPORT PIN_INT2_IRQHandler [WEAK] - EXPORT PIN_INT3_IRQHandler [WEAK] - EXPORT PIN_INT4_IRQHandler [WEAK] - EXPORT PIN_INT5_IRQHandler [WEAK] - EXPORT PIN_INT6_IRQHandler [WEAK] - EXPORT PIN_INT7_IRQHandler [WEAK] - EXPORT ADC_SEQA_IRQHandler [WEAK] - EXPORT ADC_SEQB_IRQHanlder [WEAK] - EXPORT ADC_THCMP_IRQHandler [WEAK] - EXPORT ADC_OVR_IRQHandler [WEAK] - EXPORT DMA_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - EXPORT I2C3_IRQHandler [WEAK] - -NMI_Handler -SPI0_IRQHandler -SPI1_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -I2C0_IRQHandler -SCT_IRQHandler -MRT_IRQHandler -CMP_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -FLASH_IRQHandler -WKT_IRQHandler -PIN_INT0_IRQHandler -PIN_INT1_IRQHandler -PIN_INT2_IRQHandler -PIN_INT3_IRQHandler -PIN_INT4_IRQHandler -PIN_INT5_IRQHandler -PIN_INT6_IRQHandler -PIN_INT7_IRQHandler -ADC_SEQA_IRQHandler -ADC_SEQB_IRQHanlder -ADC_THCMP_IRQHandler -ADC_OVR_IRQHandler -DMA_IRQHandler -I2C1_IRQHandler -I2C2_IRQHandler -I2C3_IRQHandler - - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - - END diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/acmp/acmp_8xx.c b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/acmp/acmp_8xx.c deleted file mode 100644 index 0dbcd911585..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/acmp/acmp_8xx.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * @brief LPC8xx Analog comparator driver - * - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Initializes the ACMP */ -void Chip_ACMP_Init(LPC_CMP_T *pACMP) -{ - Chip_SYSCTL_PowerUp(SYSCTL_SLPWAKE_ACMP_PD); - Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_ACOMP); -} - -/* De-initializes the ACMP */ -void Chip_ACMP_Deinit(LPC_CMP_T *pACMP) -{ - Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_ACOMP); - Chip_SYSCTL_PowerDown(SYSCTL_SLPWAKE_ACMP_PD); -} - -/* Clears the ACMP interrupt (EDGECLR bit) */ -void Chip_ACMP_EdgeClear(LPC_CMP_T *pACMP) -{ - uint32_t reg = pACMP->CTRL & ~ACMP_CTRL_RESERVED; - - /* Toggle EDGECLR bit high and then low */ - pACMP->CTRL = reg | ACMP_EDGECLR_BIT; - pACMP->CTRL = reg & ~ACMP_EDGECLR_BIT; -} - -/* Sets up ACMP edge selection */ -void Chip_ACMP_SetEdgeSelection(LPC_CMP_T *pACMP, ACMP_EDGESEL_T edgeSel) -{ - uint32_t reg = pACMP->CTRL & ~(ACMP_EDGESEL_MASK | ACMP_CTRL_RESERVED); - - /* Select edge for COMPEDGE */ - pACMP->CTRL = reg | (uint32_t) edgeSel; -} - -/* Selects positive voltage input */ -void Chip_ACMP_SetPosVoltRef(LPC_CMP_T *pACMP, ACMP_POS_INPUT_T Posinput) -{ - uint32_t reg = pACMP->CTRL & ~(ACMP_COMPVPSEL_MASK | ACMP_CTRL_RESERVED); - - /* Select positive input */ - pACMP->CTRL = reg | (uint32_t) Posinput; -} - -/* Selects negative voltage input */ -void Chip_ACMP_SetNegVoltRef(LPC_CMP_T *pACMP, ACMP_NEG_INPUT_T Neginput) -{ - uint32_t reg = pACMP->CTRL & ~(ACMP_COMPVMSEL_MASK | ACMP_CTRL_RESERVED); - - /* Select negative input */ - pACMP->CTRL = reg | (uint32_t) Neginput; -} - -/* Selects hysteresis level */ -void Chip_ACMP_SetHysteresis(LPC_CMP_T *pACMP, ACMP_HYS_T hys) -{ - uint32_t reg = pACMP->CTRL & ~(ACMP_HYSTERESIS_MASK | ACMP_CTRL_RESERVED); - - /* Select negative input */ - pACMP->CTRL = reg | (uint32_t) hys; -} - -/* Helper function for setting up ACMP control */ -void Chip_ACMP_SetupAMCPRefs(LPC_CMP_T *pACMP, ACMP_EDGESEL_T edgeSel, - ACMP_POS_INPUT_T Posinput, ACMP_NEG_INPUT_T Neginput, - ACMP_HYS_T hys) -{ - uint32_t reg = pACMP->CTRL & ~(ACMP_HYSTERESIS_MASK | ACMP_CTRL_RESERVED | - ACMP_COMPVMSEL_MASK | ACMP_COMPVPSEL_MASK | ACMP_EDGESEL_MASK); - - /* Select negative input */ - pACMP->CTRL = reg | (uint32_t) edgeSel | (uint32_t) Posinput | - (uint32_t) Neginput | (uint32_t) hys; -} - -/* Sets up voltage ladder */ -void Chip_ACMP_SetupVoltLadder(LPC_CMP_T *pACMP, uint32_t ladsel, bool ladrefVDDCMP) -{ - uint32_t reg = pACMP->LAD & ~(ACMP_LADSEL_MASK | ACMP_LADREF_MASK | ACMP_LAD_RESERVED); - - /* Setup voltage ladder and ladder reference */ - if (ladrefVDDCMP) { - reg |= ACMP_LADREF_MASK; - } - pACMP->LAD = reg | (ladsel << 1); -} diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/acmp/acmp_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/acmp/acmp_8xx.h deleted file mode 100644 index e5b93c410b9..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/acmp/acmp_8xx.h +++ /dev/null @@ -1,253 +0,0 @@ -/* - * @brief LPC8xx Analog comparator driver - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __ACMP_8XX_H_ -#define __ACMP_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup ACMP_8XX CHIP: LPC8xx Analog Comparator driver - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/** - * @brief Analog Comparator register block structure - */ -typedef struct { /*!< ACMP Structure */ - __IO uint32_t CTRL; /*!< Comparator control register */ - __IO uint32_t LAD; /*!< Voltage ladder register */ -} LPC_CMP_T; - -/* Reserved bits masks for registers */ -#define ACMP_CTRL_RESERVED (7|(1<<5)|(1<<7)|(0x3f<<14)|(1<<22)|(1<<24)|(0x1fu<<27)) -#define ACMP_LAD_RESERVED (~0x7f) - -#define ACMP_COMPSA_BIT (1 << 6) /* Comparator output control bit */ -#define ACMP_COMPSTAT_BIT (1 << 21) /* Comparator status, reflects the state of the comparator output */ -#define ACMP_COMPEDGE_BIT (1 << 23) /* Comparator edge-detect status */ -#define ACMP_LADENAB_BIT (1 << 0) /* Voltage ladder enable bit */ - -/* EDGECLR interrupt clear bit, write 1, then 0 */ -#define ACMP_EDGECLR_BIT (1 << 20) -#define ACMP_EDGESEL_MASK (0x3 << 3) -#define ACMP_COMPVPSEL_MASK (0x7 << 8) -#define ACMP_COMPVMSEL_MASK (0x7 << 11) -#define ACMP_HYSTERESIS_MASK (0x3 << 25) -#define ACMP_LADSEL_MASK (0x1F << 1) -#define ACMP_LADREF_MASK (0x1 << 6) - -/** Edge selection for comparator */ -typedef enum { - ACMP_EDGESEL_FALLING = (0 << 3), /* Set the COMPEDGE bit on falling edge */ - ACMP_EDGESEL_RISING = (1 << 3), /* Set the COMPEDGE bit on rising edge */ - ACMP_EDGESEL_BOTH = (2 << 3) /* Set the COMPEDGE bit on falling and rising edges */ -} ACMP_EDGESEL_T; - -/** Hysteresis selection for comparator */ -typedef enum { - ACMP_HYS_NONE = (0 << 25), /* No hysteresis (the output will switch as the voltages cross) */ - ACMP_HYS_5MV = (1 << 25), /* 5mV hysteresis */ - ACMP_HYS_10MV = (2 << 25), /* 10mV hysteresis */ - ACMP_HYS_20MV = (3 << 25) /* 20mV hysteresis */ -} ACMP_HYS_T; - -/** - * Analog Comparator positive input values - */ -typedef enum CHIP_ACMP_POS_INPUT { - ACMP_POSIN_VLO = (0 << 8), /*!< Voltage ladder output */ - ACMP_POSIN_ACMP_I1 = (1 << 8), /*!< ACMP_I1 pin */ - ACMP_POSIN_ACMP_I2 = (2 << 8), /*!< ACMP_I2 pin */ - ACMP_POSIN_ACMP_I3 = (3 << 8), /*!< ACMP_I3 pin */ - ACMP_POSIN_ACMP_I4 = (4 << 8), /*!< ACMP_I4 pin */ -#if defined(CHIP_LPC82X) - ACMP_POSIN_INT_REF = (5 << 8), /*!< Internal reference voltage */ - ACMP_POSIN_ADC_0 = (6 << 8), /*!< ADC_0 Input */ -#else - ACMP_POSIN_INT_REF = (6 << 8), /*!< Internal reference voltage */ -#endif -} ACMP_POS_INPUT_T; - -/** - * Analog Comparator negative input values - */ -typedef enum CHIP_ACMP_NEG_INPUT { - ACMP_NEGIN_VLO = (0 << 11), /*!< Voltage ladder output */ - ACMP_NEGIN_ACMP_I1 = (1 << 11), /*!< ACMP_I1 pin */ - ACMP_NEGIN_ACMP_I2 = (2 << 11), /*!< ACMP_I2 pin */ - ACMP_NEGIN_ACMP_I3 = (3 << 11), /*!< ACMP_I3 pin */ - ACMP_NEGIN_ACMP_I4 = (4 << 11), /*!< ACMP_I4 pin */ -#if defined(CHIP_LPC82X) - ACMP_NEGIN_INT_REF = (5 << 11), /*!< Internal reference voltage */ - ACMP_NEGIN_ADC_0 = (6 << 11), /*!< ADC_0 Input */ -#else - ACMP_NEGIN_INT_REF = (6 << 11) /*!< Internal reference voltage */ -#endif -} ACMP_NEG_INPUT_T; - -/** - * @brief Initializes the ACMP - * @param pACMP : Pointer to Analog Comparator block - * @return Nothing - */ -void Chip_ACMP_Init(LPC_CMP_T *pACMP); - -/** - * @brief Deinitializes the ACMP - * @param pACMP : Pointer to Analog Comparator block - * @return Nothing - */ -void Chip_ACMP_Deinit(LPC_CMP_T *pACMP); - -/** - * @brief Returns the current comparator status - * @param pACMP : Pointer to Analog Comparator block - * @return Status is an Or'ed value of ACMP_COMPSTAT_BIT or ACMP_COMPEDGE_BIT - */ -STATIC INLINE uint32_t Chip_ACMP_GetCompStatus(LPC_CMP_T *pACMP) -{ - return pACMP->CTRL & (ACMP_COMPSTAT_BIT | ACMP_COMPEDGE_BIT); -} - -/** - * @brief Clears the ACMP interrupt (EDGECLR bit) - * @param pACMP : Pointer to Analog Comparator block - * @return Nothing - */ -void Chip_ACMP_EdgeClear(LPC_CMP_T *pACMP); - -/** - * @brief Sets up ACMP edge selection - * @param pACMP : Pointer to Analog Comparator block - * @param edgeSel : Edge selection value - * @return Nothing - */ -void Chip_ACMP_SetEdgeSelection(LPC_CMP_T *pACMP, ACMP_EDGESEL_T edgeSel); - -/** - * @brief Synchronizes Comparator output to bus clock - * @param pACMP : Pointer to Analog Comparator block - * @return Nothing - */ -STATIC INLINE void Chip_ACMP_EnableSyncCompOut(LPC_CMP_T *pACMP) -{ - pACMP->CTRL = ACMP_COMPSA_BIT | (pACMP->CTRL & ~ACMP_CTRL_RESERVED); -} - -/** - * @brief Sets comparator output to be used directly (no sync) - * @param pACMP : Pointer to Analog Comparator block - * @return Nothing - */ -STATIC INLINE void Chip_ACMP_DisableSyncCompOut(LPC_CMP_T *pACMP) -{ - pACMP->CTRL &= ~(ACMP_COMPSA_BIT | ACMP_CTRL_RESERVED); -} - -/** - * @brief Selects positive voltage input - * @param pACMP : Pointer to Analog Comparator block - * @param Posinput : one of the positive input voltage sources - * @return Nothing - */ -void Chip_ACMP_SetPosVoltRef(LPC_CMP_T *pACMP, ACMP_POS_INPUT_T Posinput); - -/** - * @brief Selects negative voltage input - * @param pACMP : Pointer to Analog Comparator block - * @param Neginput : one of the negative input voltage sources - * @return Nothing - */ -void Chip_ACMP_SetNegVoltRef(LPC_CMP_T *pACMP, ACMP_NEG_INPUT_T Neginput); - -/** - * @brief Selects hysteresis level - * @param pACMP : Pointer to Analog Comparator block - * @param hys : Selected Hysteresis level - * @return Nothing - */ -void Chip_ACMP_SetHysteresis(LPC_CMP_T *pACMP, ACMP_HYS_T hys); - -/** - * @brief Helper function for setting up ACMP control - * @param pACMP : Pointer to Analog Comparator block - * @param edgeSel : Edge selection value - * @param Posinput : one of the positive input voltage sources - * @param Neginput : one of the negative input voltage sources - * @param hys : Selected Hysteresis level - * @return Nothing - */ -void Chip_ACMP_SetupAMCPRefs(LPC_CMP_T *pACMP, ACMP_EDGESEL_T edgeSel, - ACMP_POS_INPUT_T Posinput, ACMP_NEG_INPUT_T Neginput, - ACMP_HYS_T hys); - -/** - * @brief Sets up voltage ladder - * @param pACMP : Pointer to Analog Comparator block - * @param ladsel : Voltage ladder value (0 .. 31) - * @param ladrefVDDCMP : Selects the reference voltage Vref for the voltage ladder - * : false for VDD, true for VDDCMP pin - * @return Nothing - */ -void Chip_ACMP_SetupVoltLadder(LPC_CMP_T *pACMP, uint32_t ladsel, bool ladrefVDDCMP); - -/** - * @brief Enables voltage ladder - * @param pACMP : Pointer to Analog Comparator block - * @return Nothing - */ -STATIC INLINE void Chip_ACMP_EnableVoltLadder(LPC_CMP_T *pACMP) -{ - pACMP->LAD = ACMP_LADENAB_BIT | (pACMP->LAD & ~ACMP_LAD_RESERVED); -} - -/** - * @brief Disables voltage ladder - * @param pACMP : Pointer to Analog Comparator block - * @return Nothing - */ -STATIC INLINE void Chip_ACMP_DisableVoltLadder(LPC_CMP_T *pACMP) -{ - pACMP->LAD &= ~(ACMP_LADENAB_BIT | ACMP_LAD_RESERVED); -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ACMP_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/adc/adc_8xx.c b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/adc/adc_8xx.c deleted file mode 100644 index 396074f762b..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/adc/adc_8xx.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * @brief LPC82x ADC driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" -#include "adc_8xx.h" -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Initialize the ADC peripheral */ -void Chip_ADC_Init(LPC_ADC_T *pADC, uint32_t flags) -{ - /* Power up ADC and enable ADC base clock */ - Chip_SYSCTL_PowerUp(SYSCTL_SLPWAKE_ADC_PD); - Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_ADC); - - /* Disable ADC interrupts */ - pADC->INTEN = 0; - - /* Set ADC control options */ - pADC->CTRL = flags; -} - -/* Shutdown ADC */ -void Chip_ADC_DeInit(LPC_ADC_T *pADC) -{ - pADC->INTEN = 0; - pADC->CTRL = 0; - - /* Stop ADC clock and then power down ADC */ - Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_ADC); - Chip_SYSCTL_PowerDown(SYSCTL_SLPWAKE_ADC_PD); -} - -/* Start ADC calibration */ -void Chip_ADC_StartCalibration(LPC_ADC_T *pADC) -{ - /* Set calibration mode */ - pADC->CTRL |= ADC_CR_CALMODEBIT; - - /* Clear ASYNC bit */ - pADC->CTRL &= ~ADC_CR_ASYNMODE; - - /* Setup ADC for about 500KHz (per UM) */ - Chip_ADC_SetClockRate(pADC, 500000); - - /* Clearn low power bit */ - pADC->CTRL &= ~ADC_CR_LPWRMODEBIT; - - /* Calibration is only complete when ADC_CR_CALMODEBIT bit has cleared */ -} diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/adc/adc_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/adc/adc_8xx.h deleted file mode 100644 index 3b21cecea1b..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/adc/adc_8xx.h +++ /dev/null @@ -1,586 +0,0 @@ -/* - * @brief LPC82x ADC driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __ADC_8XX_H_ -#define __ADC_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup ADC_8XX CHIP: LPC8xx A/D conversion driver (Available on LPC82x Family) - * @ingroup CHIP_8xx_Drivers - * @{ - */ - -/** Sequence index enumerations, used in various parts of the code for - register indexing and sequencer selection */ -typedef enum { - ADC_SEQA_IDX, - ADC_SEQB_IDX -} ADC_SEQ_IDX_T; - -/** - * @brief ADC register block structure - */ -typedef struct { /*!< ADCn Structure */ - __IO uint32_t CTRL; /*!< A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */ - __I uint32_t RESERVED0; - __IO uint32_t SEQ_CTRL[ADC_SEQB_IDX + 1]; /*!< A/D Sequence A & B Control Register. Controls triggering and channel selection for sonversion sequence. */ - __IO uint32_t SEQ_GDAT[ADC_SEQB_IDX + 1]; /*!< A/D Sequence A & B Global Data Register. Contains the result of the most recent A/D conversion for sequence. */ - __I uint32_t RESERVED1[2]; - __I uint32_t DR[12]; /*!< A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */ - __IO uint32_t THR_LOW[2]; /*!< A/D Low Compare Threshold Register 0 & 1. Contains the lower threshold level for automatic threshold comparison. */ - __IO uint32_t THR_HIGH[2]; /*!< A/D High Compare Threshold Register 0 & 1. Contains the higher threshold level for automatic threshold comparison. */ - __IO uint32_t CHAN_THRSEL; /*!< A/D Channel Threshold Select Register. Specifies which set of threshold compare registers to use. */ - __IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable bits that enable sequence-A, sequence-B, threshold compare and overrun interrupts. */ - __IO uint32_t FLAGS; /*!< A/D Flags Register. This register contains interrupt flags. - To be checked */ - __IO uint32_t TRM; /*!< A/D Trim Register. */ -} LPC_ADC_T; - -/** Maximum sample rate in Hz (12-bit conversions) */ -#define ADC_MAX_SAMPLE_RATE 30000000 - -/** - * @brief ADC register support bitfields and mask - */ -/** ADC Control register bit fields */ -#define ADC_CR_CLKDIV_MASK (0xFF << 0) /*!< Mask for Clock divider value */ -#define ADC_CR_CLKDIV_BITPOS (0) /*!< Bit position for Clock divider value */ -#define ADC_CR_ASYNMODE (1 << 8) /*!< Asynchronous mode enable bit */ -#define ADC_CR_MODE10BIT (1 << 9) /*!< 10-bit mode enable bit */ -#define ADC_CR_LPWRMODEBIT (1 << 10) /*!< Low power mode enable bit */ -#define ADC_CR_CALMODEBIT (1 << 30) /*!< Self calibration cycle enable bit */ -#define ADC_CR_BITACC(n) ((((n) & 0x1) << 9)) /*!< 12-bit or 10-bit ADC accuracy */ -#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 0)) /*!< The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */ -#define ADC_SAMPLE_RATE_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x01)) - -/** ADC Sequence Control register bit fields */ -#define ADC_SEQ_CTRL_CHANSEL(n) (1 << (n)) /*!< Channel select macro */ -#define ADC_SEQ_CTRL_CHANSEL_MASK (0xFFF) /*!< Channel select mask */ - -/** ADC hardware trigger sources in SEQ_CTRL */ -#define ADC_SEQ_CTRL_HWTRIG_ARM_TXEV (0 << 12) /*!< HW trigger input - ARM TXEV */ -#define ADC_SEQ_CTRL_HWTRIG_CT32B0_MAT0 (1 << 12) /*!< HW trigger input - Match output 0 of CT32B0 */ -#define ADC_SEQ_CTRL_HWTRIG_CT32B0_MAT1 (2 << 12) /*!< HW trigger input - Match output 1 of CT32B1 or SCT_OUT0 */ -#define ADC_SEQ_CTRL_HWTRIG_SCT_OUT0 (2 << 12) /*!< HW trigger input - Match output 1 of CT32B1 or SCT_OUT0 */ -#define ADC_SEQ_CTRL_HWTRIG_CT16B0_MAT0 (3 << 12) /*!< HW trigger input - Match output 0 of CT16B0 */ -#define ADC_SEQ_CTRL_HWTRIG_CT16B0_MAT1 (4 << 12) /*!< HW trigger input - Match output 1 of CT16B1 or SCT_OUT1 */ -#define ADC_SEQ_CTRL_HWTRIG_SCT_OUT1 (4 << 12) /*!< HW trigger input - Match output 1 of CT16B1 or SCT_OUT1 */ -#define ADC_SEQ_CTRL_HWTRIG_CT16B0_CAP0 (5 << 12) /*!< HW trigger input - Capture input 0 of CT16B0 */ -#define ADC_SEQ_CTRL_HWTRIG_CT16B1_CAP0 (6 << 12) /*!< HW trigger input - Capture input 0 of CT16B1 */ -#define ADC_SEQ_CTRL_HWTRIG_CT32B0_CAP0 (7 << 12) /*!< HW trigger input - Capture input 0 of CT32B1 */ -#define ADC_SEQ_CTRL_HWTRIG_MASK (0x3F << 12) /*!< HW trigger input bitfield mask */ - -/** SEQ_CTRL register bit fields */ -#define ADC_SEQ_CTRL_HWTRIG_POLPOS (1 << 18) /*!< HW trigger polarity - positive edge */ -#define ADC_SEQ_CTRL_HWTRIG_SYNCBYPASS (1 << 19) /*!< HW trigger bypass synchronisation */ -#define ADC_SEQ_CTRL_START (1 << 26) /*!< Start conversion enable bit */ -#define ADC_SEQ_CTRL_BURST (1 << 27) /*!< Repeated conversion enable bit */ -#define ADC_SEQ_CTRL_SINGLESTEP (1 << 28) /*!< Single step enable bit */ -#define ADC_SEQ_CTRL_LOWPRIO (1 << 29) /*!< High priority enable bit (regardless of name) */ -#define ADC_SEQ_CTRL_MODE_EOS (1 << 30) /*!< Mode End of sequence enable bit */ -#define ADC_SEQ_CTRL_SEQ_ENA (1UL << 31) /*!< Sequence enable bit */ - -/** ADC global data register bit fields */ -#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF << 4) /*!< Result value mask */ -#define ADC_SEQ_GDAT_RESULT_BITPOS (4) /*!< Result start bit position */ -#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x3 << 16) /*!< Comparion range mask */ -#define ADC_SEQ_GDAT_THCMPRANGE_BITPOS (16) /*!< Comparison range bit position */ -#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0x3 << 18) /*!< Comparion cross mask */ -#define ADC_SEQ_GDAT_THCMPCROSS_BITPOS (18) /*!< Comparison cross bit position */ -#define ADC_SEQ_GDAT_CHAN_MASK (0xF << 26) /*!< Channel number mask */ -#define ADC_SEQ_GDAT_CHAN_BITPOS (26) /*!< Channel number bit position */ -#define ADC_SEQ_GDAT_OVERRUN (1 << 30) /*!< Overrun bit */ -#define ADC_SEQ_GDAT_DATAVALID (1UL << 31) /*!< Data valid bit */ - -/** ADC Data register bit fields */ -#define ADC_DR_RESULT(n) ((((n) >> 4) & 0xFFF)) /*!< Macro for getting the ADC data value */ -#define ADC_DR_THCMPRANGE_MASK (0x3 << 16) /*!< Comparion range mask */ -#define ADC_DR_THCMPRANGE_BITPOS (16) /*!< Comparison range bit position */ -#define ADC_DR_THCMPRANGE(n) (((n) >> ADC_DR_THCMPRANGE_BITPOS) & 0x3) -#define ADC_DR_THCMPCROSS_MASK (0x3 << 18) /*!< Comparion cross mask */ -#define ADC_DR_THCMPCROSS_BITPOS (18) /*!< Comparison cross bit position */ -#define ADC_DR_THCMPCROSS(n) (((n) >> ADC_DR_THCMPCROSS_BITPOS) & 0x3) -#define ADC_DR_CHAN_MASK (0xF << 26) /*!< Channel number mask */ -#define ADC_DR_CHAN_BITPOS (26) /*!< Channel number bit position */ -#define ADC_DR_CHANNEL(n) (((n) >> ADC_DR_CHAN_BITPOS) & 0xF) /*!< Channel number bit position */ -#define ADC_DR_OVERRUN (1 << 30) /*!< Overrun bit */ -#define ADC_DR_DATAVALID (1UL << 31) /*!< Data valid bit */ -#define ADC_DR_DONE(n) (((n) >> 31)) - -/** ADC low/high Threshold register bit fields */ -#define ADC_THR_VAL_MASK (0xFFF << 4) /*!< Threshold value bit mask */ -#define ADC_THR_VAL_POS (4) /*!< Threshold value bit position */ - -/** ADC Threshold select register bit fields */ -#define ADC_THRSEL_CHAN_SEL_THR1(n) (1 << (n)) /*!< Select THR1 register for channel n */ - -/** ADC Interrupt Enable register bit fields */ -#define ADC_INTEN_SEQA_ENABLE (1 << 0) /*!< Sequence A Interrupt enable bit */ -#define ADC_INTEN_SEQB_ENABLE (1 << 1) /*!< Sequence B Interrupt enable bit */ -#define ADC_INTEN_SEQN_ENABLE(seq) (1 << (seq)) /*!< Sequence A/B Interrupt enable bit */ -#define ADC_INTEN_OVRRUN_ENABLE (1 << 2) /*!< Overrun Interrupt enable bit */ -#define ADC_INTEN_CMP_DISBALE (0) /*!< Disable comparison interrupt value */ -#define ADC_INTEN_CMP_OUTSIDETH (1) /*!< Outside threshold interrupt value */ -#define ADC_INTEN_CMP_CROSSTH (2) /*!< Crossing threshold interrupt value */ -#define ADC_INTEN_CMP_MASK (3) /*!< Comparison interrupt value mask */ -#define ADC_INTEN_CMP_ENABLE(isel, ch) (((isel) & ADC_INTEN_CMP_MASK) << ((2 * (ch)) + 3)) /*!< Interrupt selection for channel */ - -/** ADC Flags register bit fields */ -#define ADC_FLAGS_THCMP_MASK(ch) (1 << (ch)) /*!< Threshold comparison status for channel */ -#define ADC_FLAGS_OVRRUN_MASK(ch) (1 << (12 + (ch))) /*!< Overrun status for channel */ -#define ADC_FLAGS_SEQA_OVRRUN_MASK (1 << 24) /*!< Seq A Overrun status */ -#define ADC_FLAGS_SEQB_OVRRUN_MASK (1 << 25) /*!< Seq B Overrun status */ -#define ADC_FLAGS_SEQN_OVRRUN_MASK(seq) (1 << (24 + (seq))) /*!< Seq A/B Overrun status */ -#define ADC_FLAGS_SEQA_INT_MASK (1 << 28) /*!< Seq A Interrupt status */ -#define ADC_FLAGS_SEQB_INT_MASK (1 << 29) /*!< Seq B Interrupt status */ -#define ADC_FLAGS_SEQN_INT_MASK(seq) (1 << (28 + (seq)))/*!< Seq A/B Interrupt status */ -#define ADC_FLAGS_THCMP_INT_MASK (1 << 30) /*!< Threshold comparison Interrupt status */ -#define ADC_FLAGS_OVRRUN_INT_MASK (1UL << 31) /*!< Overrun Interrupt status */ - -/** ADC Trim register bit fields */ -#define ADC_TRIM_VRANGE_HIGHV (0 << 5) /*!< Voltage range bit - High volatge (2.7V to 3.6V) */ -#define ADC_TRIM_VRANGE_LOWV (1 << 5) /*!< Voltage range bit - Low volatge (1.8V to 2.7V) */ - -/** ADC Register reserved bit masks */ -#define ADC_CHAN_THRSEL_RES 0xFFFFF000 -#define ADC_INTEN_RES 0xF8000000 -#define ADC_SEQ_CTRL_RES ((7 << 15) | (0x3F << 20)) - -/** - * @brief Initialize the ADC peripheral - * @param pADC : The base of ADC peripheral on the chip - * @param flags : ADC flags for init (ADC_CR_MODE10BIT and/or ADC_CR_LPWRMODEBIT) - * @return Nothing - * @note To select low-power ADC mode, enable the ADC_CR_LPWRMODEBIT flag. - * To select 10-bit conversion mode, enable the ADC_CR_MODE10BIT flag.
- * Example: Chip_ADC_Init(LPC_ADC, (ADC_CR_MODE10BIT | ADC_CR_LPWRMODEBIT)); - */ -void Chip_ADC_Init(LPC_ADC_T *pADC, uint32_t flags); - -/** - * @brief Shutdown ADC - * @param pADC : The base of ADC peripheral on the chip - * @return Nothing - * @note Disables the ADC clocks and ADC power - */ -void Chip_ADC_DeInit(LPC_ADC_T *pADC); - -/** - * @brief Set ADC divider - * @param pADC : The base of ADC peripheral on the chip - * @param div : ADC divider value to set minus 1 - * @return Nothing - * @note The value is used as a divider to generate the ADC - * clock rate from the ADC input clock. The ADC input clock is based - * on the system clock. Valid values for this function are from 0 to 255 - * with 0=divide by 1, 1=divide by 2, 2=divide by 3, etc.
- * Do not decrement this value by 1.
- * To set the ADC clock rate to 1MHz, use the following function:
- * Chip_ADC_SetDivider(LPC_ADC, (Chip_Clock_GetSystemClockRate() / 1000000) - 1); - */ -STATIC INLINE void Chip_ADC_SetDivider(LPC_ADC_T *pADC, uint8_t div) -{ - uint32_t temp; - - temp = pADC->CTRL & ~(ADC_CR_CLKDIV_MASK); - pADC->CTRL = temp | (uint32_t) div; -} - -/** - * @brief Set ADC clock rate - * @param pADC : The base of ADC peripheral on the chip - * @param rate : rate in Hz to set ADC clock to (maximum ADC_MAX_SAMPLE_RATE) - * @return Nothing - * @note When ADC is set to ADC_CR_ASYNMODE this function has no effect. The - * rate mentioned in @a rate is the sampling clock rate and not the frequency at - * at which the conversion will be done. Example setting @a rate to 30 MHz will - * get a sampling rate of 1.2M samples per second. - */ -STATIC INLINE void Chip_ADC_SetClockRate(LPC_ADC_T *pADC, uint32_t rate) -{ - Chip_ADC_SetDivider(pADC, (uint8_t) (Chip_Clock_GetSystemClockRate() / rate) - 1); -} - -/** - * @brief Get ADC divider - * @param pADC : The base of ADC peripheral on the chip - * @return the current ADC divider - * @note This function returns the divider that is used to generate the - * ADC frequency. The returned value must be incremented by 1. The - * frequency can be determined with the following function:
- * adc_freq = Chip_Clock_GetSystemClockRate() / (Chip_ADC_GetDivider(LPC_ADC) + 1); - */ -STATIC INLINE uint8_t Chip_ADC_GetDivider(LPC_ADC_T *pADC) -{ - return pADC->CTRL & ADC_CR_CLKDIV_MASK; -} - -/** - * @brief Start ADC calibration - * @param pADC : The base of ADC peripheral on the chip - * @return Nothing - * @note Calibration is not done as part of Chip_ADC_Init(), but - * is required after the call to Chip_ADC_Init() or after returning - * from a power-down state. Calibration may alter the ADC_CR_ASYNMODE - * and ADC_CR_LPWRMODEBIT flags ni the CTRL register. - */ -void Chip_ADC_StartCalibration(LPC_ADC_T *pADC); - -/** - * @brief Start ADC calibration - * @param pADC : The base of ADC peripheral on the chip - * @return TRUE if calibration is complete, otherwise FALSE. - */ -STATIC INLINE bool Chip_ADC_IsCalibrationDone(LPC_ADC_T *pADC) -{ - return (bool) ((pADC->CTRL & ADC_CR_CALMODEBIT) == 0); -} - -/** - * @brief Helper function for safely setting ADC sequencer register bits - * @param pADC : The base of ADC peripheral on the chip - * @param seqIndex : Sequencer to set bits for - * @param bits : Or'ed bits of a sequencer register to set - * @return Nothing - * @note This function will safely set the ADC sequencer register bits - * while maintaining bits 20..25 as 0, regardless of the read state of those bits. - */ -STATIC INLINE void Chip_ADC_SetSequencerBits(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex, uint32_t bits) -{ - pADC->SEQ_CTRL[seqIndex] = (pADC->SEQ_CTRL[seqIndex] & ~ADC_SEQ_CTRL_RES) | bits; -} - -/** - * @brief Helper function for safely clearing ADC sequencer register bits - * @param pADC : The base of ADC peripheral on the chip - * @param seqIndex : Sequencer to clear bits for - * @param bits : Or'ed bits of a sequencer register to clear - * @return Nothing - * @note This function will safely clear the ADC sequencer register bits - * while maintaining bits 20..25 as 0, regardless of the read state of those bits. - */ -STATIC INLINE void Chip_ADC_ClearSequencerBits(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex, uint32_t bits) -{ - pADC->SEQ_CTRL[seqIndex] = pADC->SEQ_CTRL[seqIndex] & ~(ADC_SEQ_CTRL_RES | bits); -} - -/** - * @brief Sets up ADC conversion sequencer A or B - * @param pADC : The base of ADC peripheral on the chip - * @param seqIndex : Sequencer to setup - * @param options : OR'ed Sequencer options to setup (see notes) - * @return Nothing - * @note Sets up sequencer options for a conversion sequence. This function - * should be used to setup the selected channels for the sequence, the sequencer - * trigger, the trigger polarity, synchronization bypass, priority, and mode. All - * options are passed to the functions as a OR'ed list of values. This function will - * disable/clear the sequencer start/burst/single step/enable if they are enabled.
- * Select the channels by OR'ing in one or more ADC_SEQ_CTRL_CHANSEL(ch) values.
- * Select the hardware trigger by OR'ing in one ADC_SEQ_CTRL_HWTRIG_* value.
- * Select a positive edge hardware trigger by OR'ing in ADC_SEQ_CTRL_HWTRIG_POLPOS.
- * Select trigger bypass synchronisation by OR'ing in ADC_SEQ_CTRL_HWTRIG_SYNCBYPASS.
- * Select ADC single step on trigger/start by OR'ing in ADC_SEQ_CTRL_SINGLESTEP.
- * Select higher priority conversion on the other sequencer by OR'ing in ADC_SEQ_CTRL_LOWPRIO.
- * Select end of seqeuence instead of end of conversion interrupt by OR'ing in ADC_SEQ_CTRL_MODE_EOS.
- * Example for setting up sequencer A (channels 0-2, trigger on high edge of PIO0_2, interrupt on end of sequence):
- * Chip_ADC_SetupSequencer(LPC_ADC, ADC_SEQA_IDX, ( - * ADC_SEQ_CTRL_CHANSEL(0) | ADC_SEQ_CTRL_CHANSEL(1) | ADC_SEQ_CTRL_CHANSEL(2) | - * ADC_SEQ_CTRL_HWTRIG_PIO0_2 | ADC_SEQ_CTRL_HWTRIG_POLPOS | ADC_SEQ_CTRL_MODE_EOS)); - */ -STATIC INLINE void Chip_ADC_SetupSequencer(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex, uint32_t options) -{ - pADC->SEQ_CTRL[seqIndex] = options; -} - -/** - * @brief Enables a sequencer - * @param pADC : The base of ADC peripheral on the chip - * @param seqIndex : Sequencer to enable - * @return Nothing - */ -STATIC INLINE void Chip_ADC_EnableSequencer(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex) -{ - Chip_ADC_SetSequencerBits(pADC, seqIndex, ADC_SEQ_CTRL_SEQ_ENA); -} - -/** - * @brief Disables a sequencer - * @param pADC : The base of ADC peripheral on the chip - * @param seqIndex : Sequencer to disable - * @return Nothing - */ -STATIC INLINE void Chip_ADC_DisableSequencer(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex) -{ - Chip_ADC_ClearSequencerBits(pADC, seqIndex, ADC_SEQ_CTRL_SEQ_ENA); -} - -/** - * @brief Forces a sequencer trigger event (software trigger of ADC) - * @param pADC : The base of ADC peripheral on the chip - * @param seqIndex : Sequencer to start - * @return Nothing - * @note This function sets the START bit for the sequencer to force a - * single conversion sequence or a single step conversion. - */ -STATIC INLINE void Chip_ADC_StartSequencer(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex) -{ - Chip_ADC_SetSequencerBits(pADC, seqIndex, ADC_SEQ_CTRL_START); -} - -/** - * @brief Starts sequencer burst mode - * @param pADC : The base of ADC peripheral on the chip - * @param seqIndex : Sequencer to start burst on - * @return Nothing - * @note This function sets the BURST bit for the sequencer to force - * continuous conversion. Use Chip_ADC_StopBurstSequencer() to stop the - * ADC burst sequence. - */ -STATIC INLINE void Chip_ADC_StartBurstSequencer(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex) -{ - Chip_ADC_SetSequencerBits(pADC, seqIndex, ADC_SEQ_CTRL_BURST); -} - -/** - * @brief Stops sequencer burst mode - * @param pADC : The base of ADC peripheral on the chip - * @param seqIndex : Sequencer to stop burst on - * @return Nothing - */ -STATIC INLINE void Chip_ADC_StopBurstSequencer(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex) -{ - Chip_ADC_ClearSequencerBits(pADC, seqIndex, ADC_SEQ_CTRL_BURST); -} - -/** ADC sequence global data register threshold comparison range enumerations */ -typedef enum { - ADC_DR_THCMPRANGE_INRANGE, - ADC_DR_THCMPRANGE_RESERVED, - ADC_DR_THCMPRANGE_BELOW, - ADC_DR_THCMPRANGE_ABOVE -} ADC_DR_THCMPRANGE_T; - -/** ADC sequence global data register threshold comparison cross enumerations */ -typedef enum { - ADC_DR_THCMPCROSS_NOCROSS, - ADC_DR_THCMPCROSS_RESERVED, - ADC_DR_THCMPCROSS_DOWNWARD, - ADC_DR_THCMPCROSS_UPWARD -} ADC_DR_THCMPCROSS_T; - -/** - * @brief Read a ADC sequence global data register - * @param pADC : The base of ADC peripheral on the chip - * @param seqIndex : Sequencer to read - * @return Current raw value of the ADC sequence A or B global data register - * @note This function returns the raw value of the data register and clears - * the overrun and datavalid status for the register. Once this register is read, - * the following functions can be used to parse the raw value:
- * uint32_t adcDataRawValue = Chip_ADC_ReadSequencerDataReg(LPC_ADC, ADC_SEQA_IDX); // Get raw value - * uint32_t adcDataValue = ADC_DR_RESULT(adcDataRawValue); // Aligned and masked ADC data value - * ADC_DR_THCMPRANGE_T adcRange = (ADC_DR_THCMPRANGE_T) ADC_DR_THCMPRANGE(adcDataRawValue); // Sample range compared to threshold low/high - * ADC_DR_THCMPCROSS_T adcRange = (ADC_DR_THCMPCROSS_T) ADC_DR_THCMPCROSS(adcDataRawValue); // Sample cross compared to threshold low - * uint32_t channel = ADC_DR_CHANNEL(adcDataRawValue); // ADC channel for this sample/data - * bool adcDataOverrun = (bool) ((adcDataRawValue & ADC_DR_OVERRUN) != 0); // Data overrun flag - * bool adcDataValid = (bool) ((adcDataRawValue & ADC_SEQ_GDAT_DATAVALID) != 0); // Data valid flag - */ -STATIC INLINE uint32_t Chip_ADC_GetSequencerDataReg(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex) -{ - return pADC->SEQ_GDAT[seqIndex]; -} - -/** - * @brief Read a ADC data register - * @param pADC : The base of ADC peripheral on the chip - * @param index : Data register to read, 1-8 - * @return Current raw value of the ADC data register - * @note This function returns the raw value of the data register and clears - * the overrun and datavalid status for the register. Once this register is read, - * the following functions can be used to parse the raw value:
- * uint32_t adcDataRawValue = Chip_ADC_ReadSequencerDataReg(LPC_ADC, ADC_SEQA_IDX); // Get raw value - * uint32_t adcDataValue = ADC_DR_RESULT(adcDataRawValue); // Aligned and masked ADC data value - * ADC_DR_THCMPRANGE_T adcRange = (ADC_DR_THCMPRANGE_T) ADC_DR_THCMPRANGE(adcDataRawValue); // Sample range compared to threshold low/high - * ADC_DR_THCMPCROSS_T adcRange = (ADC_DR_THCMPCROSS_T) ADC_DR_THCMPCROSS(adcDataRawValue); // Sample cross compared to threshold low - * uint32_t channel = ADC_DR_CHANNEL(adcDataRawValue); // ADC channel for this sample/data - * bool adcDataOverrun = (bool) ((adcDataRawValue & ADC_DR_OVERRUN) != 0); // Data overrun flag - * bool adcDataValid = (bool) ((adcDataRawValue & ADC_SEQ_GDAT_DATAVALID) != 0); // Data valid flag - */ -STATIC INLINE uint32_t Chip_ADC_GetDataReg(LPC_ADC_T *pADC, uint8_t index) -{ - return pADC->DR[index]; -} - -/** - * @brief Set Threshold low value in ADC - * @param pADC : The base of ADC peripheral on the chip - * @param thrnum : Threshold register value (1 for threshold register 1, 0 for threshold register 0) - * @param value : Threshold low data value (should be 12-bit value) - * @return None - */ -STATIC INLINE void Chip_ADC_SetThrLowValue(LPC_ADC_T *pADC, uint8_t thrnum, uint16_t value) -{ - pADC->THR_LOW[thrnum] = (((uint32_t) value) << ADC_THR_VAL_POS); -} - -/** - * @brief Set Threshold high value in ADC - * @param pADC : The base of ADC peripheral on the chip - * @param thrnum : Threshold register value (1 for threshold register 1, 0 for threshold register 0) - * @param value : Threshold high data value (should be 12-bit value) - * @return None - */ -STATIC INLINE void Chip_ADC_SetThrHighValue(LPC_ADC_T *pADC, uint8_t thrnum, uint16_t value) -{ - pADC->THR_HIGH[thrnum] = (((uint32_t) value) << ADC_THR_VAL_POS); -} - -/** - * @brief Select threshold 0 values for comparison for selected channels - * @param pADC : The base of ADC peripheral on the chip - * @param channels : An OR'ed value of one or more ADC_THRSEL_CHAN_SEL_THR1(ch) values - * @return None - * @note Select multiple channels to use the threshold 0 comparison.
- * Example:
- * Chip_ADC_SelectTH0Channels(LPC_ADC, (ADC_THRSEL_CHAN_SEL_THR1(1) | ADC_THRSEL_CHAN_SEL_THR1(2))); // Selects channels 1 and 2 for threshold 0 - */ -STATIC INLINE void Chip_ADC_SelectTH0Channels(LPC_ADC_T *pADC, uint32_t channels) -{ - pADC->CHAN_THRSEL = pADC->CHAN_THRSEL & ~(ADC_CHAN_THRSEL_RES | channels); -} - -/** - * @brief Select threshold 1 value for comparison for selected channels - * @param pADC : The base of ADC peripheral on the chip - * @param channels : An OR'ed value of one or more ADC_THRSEL_CHAN_SEL_THR1(ch) values - * @return None - * @note Select multiple channels to use the 1 threshold comparison.
- * Example:
- * Chip_ADC_SelectTH1Channels(LPC_ADC, (ADC_THRSEL_CHAN_SEL_THR1(4) | ADC_THRSEL_CHAN_SEL_THR1(5))); // Selects channels 4 and 5 for 1 threshold - */ -STATIC INLINE void Chip_ADC_SelectTH1Channels(LPC_ADC_T *pADC, uint32_t channels) -{ - pADC->CHAN_THRSEL = (pADC->CHAN_THRSEL & ~ADC_CHAN_THRSEL_RES) | channels; -} - -/** - * @brief Enable interrupts in ADC (sequencers A/B and overrun) - * @param pADC : The base of ADC peripheral on the chip - * @param intMask : Interrupt values to be enabled (see notes) - * @return None - * @note Select one or more OR'ed values of ADC_INTEN_SEQA_ENABLE, - * ADC_INTEN_SEQB_ENABLE, and ADC_INTEN_OVRRUN_ENABLE to enable the - * specific ADC interrupts. - */ -STATIC INLINE void Chip_ADC_EnableInt(LPC_ADC_T *pADC, uint32_t intMask) -{ - pADC->INTEN = (pADC->INTEN & ~ADC_INTEN_RES) | intMask; -} - -/** - * @brief Disable interrupts in ADC (sequencers A/B and overrun) - * @param pADC : The base of ADC peripheral on the chip - * @param intMask : Interrupt values to be disabled (see notes) - * @return None - * @note Select one or more OR'ed values of ADC_INTEN_SEQA_ENABLE, - * ADC_INTEN_SEQB_ENABLE, and ADC_INTEN_OVRRUN_ENABLE to disable the - * specific ADC interrupts. - */ -STATIC INLINE void Chip_ADC_DisableInt(LPC_ADC_T *pADC, uint32_t intMask) -{ - pADC->INTEN = pADC->INTEN & ~(ADC_INTEN_RES | intMask); -} - -/** Threshold interrupt event options */ -typedef enum { - ADC_INTEN_THCMP_DISABLE, - ADC_INTEN_THCMP_OUTSIDE, - ADC_INTEN_THCMP_CROSSING, -} ADC_INTEN_THCMP_T; - -/** - * @brief Enable a threshold event interrupt in ADC - * @param pADC : The base of ADC peripheral on the chip - * @param ch : ADC channel to set threshold inetrrupt for, 1-8 - * @param thInt : Selected threshold interrupt type - * @return None - */ -STATIC INLINE void Chip_ADC_SetThresholdInt(LPC_ADC_T *pADC, uint8_t ch, ADC_INTEN_THCMP_T thInt) -{ - pADC->INTEN = (pADC->INTEN & ~(ADC_INTEN_RES | (3 << (3 + (ch * 2))))) | (thInt << (3 + (ch * 2))); -} - -/** - * @brief Get flags register in ADC - * @param pADC : The base of ADC peripheral on the chip - * @return Flags register value (ORed ADC_FLAG* values) - * @note Mask the return value of this function with the ADC_FLAGS_* - * definitions to determine the overall ADC interrupt events.
- * Example:
- * if (Chip_ADC_GetFlags(LPC_ADC) & ADC_FLAGS_THCMP_MASK(3) // Check of threshold comp status for ADC channel 3 - */ -STATIC INLINE uint32_t Chip_ADC_GetFlags(LPC_ADC_T *pADC) -{ - return pADC->FLAGS; -} - -/** - * @brief Clear flags register in ADC - * @param pADC : The base of ADC peripheral on the chip - * @param flags : An Or'ed values of ADC_FLAGS_* values to clear - * @return Flags register value (ORed ADC_FLAG* values) - */ -STATIC INLINE void Chip_ADC_ClearFlags(LPC_ADC_T *pADC, uint32_t flags) -{ - pADC->FLAGS = flags; -} - -/** - * @brief Set Trim register in ADC - * @param pADC : The base of ADC peripheral on the chip - * @param trim : Trim value (ADC_TRIM_VRANGE_HIGHV or ADC_TRIM_VRANGE_LOWV) - * @return None - */ -STATIC INLINE void Chip_ADC_SetTrim(LPC_ADC_T *pADC, uint32_t trim) -{ - pADC->TRM = trim; -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ADC_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/crc/crc_8xx.c b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/crc/crc_8xx.c deleted file mode 100644 index 6600599274b..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/crc/crc_8xx.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * @brief LPC8xx Cyclic Redundancy Check (CRC) Engine driver - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Initialize CRC engine */ -void Chip_CRC_Init(void) -{ - Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_CRC); -} - -/* De-initialize CRC engine */ -void Chip_CRC_Deinit(void) -{ - Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_CRC); -} - -/* Sets up the CRC engine with defaults based on the polynomial to be used */ -void Chip_CRC_UseDefaultConfig(CRC_POLY_T poly) -{ - switch (poly) { - case CRC_POLY_CRC16: - Chip_CRC_UseCRC16(); - break; - - case CRC_POLY_CRC32: - Chip_CRC_UseCRC32(); - break; - - case CRC_POLY_CCITT: - default: - Chip_CRC_UseCCITT(); - break; - } -} - -/* configure CRC engine and compute CCITT checksum from 8-bit data */ -uint32_t Chip_CRC_CRC8(const uint8_t *data, uint32_t bytes) -{ - Chip_CRC_UseCCITT(); - while (bytes > 0) { - Chip_CRC_Write8(*data); - data++; - bytes--; - } - - return Chip_CRC_Sum(); -} - -/* Convenience function for computing a standard CRC16 checksum from 16-bit data block */ -uint32_t Chip_CRC_CRC16(const uint16_t *data, uint32_t hwords) -{ - Chip_CRC_UseCRC16(); - while (hwords > 0) { - Chip_CRC_Write16(*data); - data++; - hwords--; - } - - return Chip_CRC_Sum(); -} - -/* Convenience function for computing a standard CRC32 checksum from 32-bit data block */ -uint32_t Chip_CRC_CRC32(const uint32_t *data, uint32_t words) -{ - Chip_CRC_UseCRC32(); - while (words > 0) { - Chip_CRC_Write32(*data); - data++; - words--; - } - - return Chip_CRC_Sum(); -} diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/crc/crc_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/crc/crc_8xx.h deleted file mode 100644 index 601578953df..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/crc/crc_8xx.h +++ /dev/null @@ -1,262 +0,0 @@ -/* - * @brief LPC8xx Cyclic Redundancy Check (CRC) Engine driver - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __CRC_8XX_H_ -#define __CRC_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup CRC_8XX CHIP: LPC8xx Cyclic Redundancy Check Engine driver - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/** - * @brief CRC register block structure - */ -typedef struct { /*!< CRC Structure */ - __IO uint32_t MODE; /*!< CRC Mode Register */ - __IO uint32_t SEED; /*!< CRC SEED Register */ - union { - __I uint32_t SUM; /*!< CRC Checksum Register. */ - __O uint32_t WRDATA32; /*!< CRC Data Register: write size 32-bit*/ - __O uint16_t WRDATA16; /*!< CRC Data Register: write size 16-bit*/ - __O uint8_t WRDATA8; /*!< CRC Data Register: write size 8-bit*/ - }; - -} LPC_CRC_T; - -/* - * @brief CRC MODE register description - */ -#define CRC_MODE_POLY_BITMASK ((0x03)) /** CRC polynomial Bit mask */ -#define CRC_MODE_POLY_CCITT (0x00) /** Select CRC-CCITT polynomial */ -#define CRC_MODE_POLY_CRC16 (0x01) /** Select CRC-16 polynomial */ -#define CRC_MODE_POLY_CRC32 (0x02) /** Select CRC-32 polynomial */ -#define CRC_MODE_WRDATA_BITMASK (0x03 << 2) /** CRC WR_Data Config Bit mask */ -#define CRC_MODE_WRDATA_BIT_RVS (1 << 2) /** Select Bit order reverse for WR_DATA (per byte) */ -#define CRC_MODE_WRDATA_CMPL (1 << 3) /** Select One's complement for WR_DATA */ -#define CRC_MODE_SUM_BITMASK (0x03 << 4) /** CRC Sum Config Bit mask */ -#define CRC_MODE_SUM_BIT_RVS (1 << 4) /** Select Bit order reverse for CRC_SUM */ -#define CRC_MODE_SUM_CMPL (1 << 5) /** Select One's complement for CRC_SUM */ - -#define MODE_CFG_CCITT (0x00) /** Pre-defined mode word for default CCITT setup */ -#define MODE_CFG_CRC16 (0x15) /** Pre-defined mode word for default CRC16 setup */ -#define MODE_CFG_CRC32 (0x36) /** Pre-defined mode word for default CRC32 setup */ - -#define CRC_SEED_CCITT (0x0000FFFF)/** Initial seed value for CCITT mode */ -#define CRC_SEED_CRC16 (0x00000000)/** Initial seed value for CRC16 mode */ -#define CRC_SEED_CRC32 (0xFFFFFFFF)/** Initial seed value for CRC32 mode */ - -/** - * @brief CRC polynomial - */ -typedef enum IP_CRC_001_POLY { - CRC_POLY_CCITT = CRC_MODE_POLY_CCITT, /**< CRC-CCIT polynomial */ - CRC_POLY_CRC16 = CRC_MODE_POLY_CRC16, /**< CRC-16 polynomial */ - CRC_POLY_CRC32 = CRC_MODE_POLY_CRC32, /**< CRC-32 polynomial */ - CRC_POLY_LAST, -} CRC_POLY_T; - -/** - * @brief Initializes the CRC Engine - * @return Nothing - */ -void Chip_CRC_Init(void); - -/** - * @brief Deinitializes the CRC Engine - * @return Nothing - */ -void Chip_CRC_Deinit(void); - -/** - * @brief Set the polynomial used for the CRC calculation - * @param poly : The enumerated polynomial to be used - * @param flags : An Or'ed value of flags that setup the mode - * @return Nothing - * @note Flags for setting up the mode word include CRC_MODE_WRDATA_BIT_RVS, - * CRC_MODE_WRDATA_CMPL, CRC_MODE_SUM_BIT_RVS, and CRC_MODE_SUM_CMPL. - */ -STATIC INLINE void Chip_CRC_SetPoly(CRC_POLY_T poly, uint32_t flags) -{ - LPC_CRC->MODE = (uint32_t) poly | flags; -} - -/** - * @brief Sets up the CRC engine for CRC16 mode - * @return Nothing - */ -STATIC INLINE void Chip_CRC_UseCRC16(void) -{ - LPC_CRC->MODE = MODE_CFG_CRC16; - LPC_CRC->SEED = CRC_SEED_CRC16; -} - -/** - * @brief Sets up the CRC engine for CRC32 mode - * @return Nothing - */ -STATIC INLINE void Chip_CRC_UseCRC32(void) -{ - LPC_CRC->MODE = MODE_CFG_CRC32; - LPC_CRC->SEED = CRC_SEED_CRC32; -} - -/** - * @brief Sets up the CRC engine for CCITT mode - * @return Nothing - */ -STATIC INLINE void Chip_CRC_UseCCITT(void) -{ - LPC_CRC->MODE = MODE_CFG_CCITT; - LPC_CRC->SEED = CRC_SEED_CCITT; -} - -/** - * @brief Engage the CRC engine with defaults based on the polynomial to be used - * @param poly : The enumerated polynomial to be used - * @return Nothing - */ -void Chip_CRC_UseDefaultConfig(CRC_POLY_T poly); - -/** - * @brief Set the CRC Mode bits - * @param mode : Mode value - * @return Nothing - */ -STATIC INLINE void Chip_CRC_SetMode(uint32_t mode) -{ - LPC_CRC->MODE = mode; -} - -/** - * @brief Get the CRC Mode bits - * @return The current value of the CRC Mode bits - */ -STATIC INLINE uint32_t Chip_CRC_GetMode(void) -{ - return LPC_CRC->MODE; -} - -/** - * @brief Set the seed bits used by the CRC_SUM register - * @param seed : Seed value - * @return Nothing - */ -STATIC INLINE void Chip_CRC_SetSeed(uint32_t seed) -{ - LPC_CRC->SEED = seed; -} - -/** - * @brief Get the CRC seed value - * @return Seed value - */ -STATIC INLINE uint32_t Chip_CRC_GetSeed(void) -{ - return LPC_CRC->SEED; -} - -/** - * @brief Convenience function for writing 8-bit data to the CRC engine - * @param data : 8-bit data to write - * @return Nothing - */ -STATIC INLINE void Chip_CRC_Write8(uint8_t data) -{ - LPC_CRC->WRDATA8 = data; -} - -/** - * @brief Convenience function for writing 16-bit data to the CRC engine - * @param data : 16-bit data to write - * @return Nothing - */ -STATIC INLINE void Chip_CRC_Write16(uint16_t data) -{ - LPC_CRC->WRDATA16 = data; -} - -/** - * @brief Convenience function for writing 32-bit data to the CRC engine - * @param data : 32-bit data to write - * @return Nothing - */ -STATIC INLINE void Chip_CRC_Write32(uint32_t data) -{ - LPC_CRC->WRDATA32 = data; -} - -/** - * @brief Gets the CRC Sum based on the Mode and Seed as previously configured - * @return CRC Checksum value - */ -STATIC INLINE uint32_t Chip_CRC_Sum(void) -{ - return LPC_CRC->SUM; -} - -/** - * @brief Convenience function for computing a standard CCITT checksum from an 8-bit data block - * @param data : Pointer to the block of 8-bit data - * @param bytes : The number of bytes pointed to by data - * @return Check sum value - */ -uint32_t Chip_CRC_CRC8(const uint8_t *data, uint32_t bytes); - -/** - * @brief Convenience function for computing a standard CRC16 checksum from 16-bit data block - * @param data : Pointer to the block of 16-bit data - * @param hwords : The number of 16 byte entries pointed to by data - * @return Check sum value - */ -uint32_t Chip_CRC_CRC16(const uint16_t *data, uint32_t hwords); - -/** - * @brief Convenience function for computing a standard CRC32 checksum from 32-bit data block - * @param data : Pointer to the block of 32-bit data - * @param words : The number of 32-bit entries pointed to by data - * @return Check sum value - */ -uint32_t Chip_CRC_CRC32(const uint32_t *data, uint32_t words); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CRC_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/dma/dma_8xx.c b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/dma/dma_8xx.c deleted file mode 100644 index bdb0c172855..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/dma/dma_8xx.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * @brief LPC82x DMA chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2013 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/* DMA SRAM table - this can be optionally used with the Chip_DMA_SetSRAMBase() - function if a DMA SRAM table is needed. This table is correctly aligned for - the DMA controller. */ -#ifdef __ICCARM__ -#define ASTR(str) #str -#define ALIGN(x) _Pragma(ASTR(data_alignment=##x)) -#else -#define ALIGN(x) __attribute__((aligned(x))) -#endif - -/* Alignment of 512 bytes */ -#define DMA_ALIGN ALIGN(512) -DMA_ALIGN DMA_CHDESC_T Chip_DMA_Table[MAX_DMA_CHANNEL]; - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -void ChipEz_DMA_Init(uint32_t isEnableIRQ) -{ - Chip_DMA_Init(LPC_DMA); - Chip_DMA_Enable(LPC_DMA); - Chip_DMA_SetSRAMBase(LPC_DMA, DMA_ADDR(Chip_DMA_Table)); - if (isEnableIRQ) - NVIC_EnableIRQ(DMA_IRQn); - -} - - /** - * Initialize DMA parameters specific to a channel - * - * @param channel - * @param src_address - * @param dst_address - * @param xfr_width - * @param length_bytes - */ - void ChipEz_DMA_InitChannel( DMA_CHID_T channel, uint32_t src_address, uint32_t src_increment, - uint32_t dst_address, uint32_t dst_increment, uint32_t xfr_width, uint32_t length_bytes, uint32_t priority) - { - Chip_DMA_EnableChannel(LPC_DMA, channel); - Chip_DMA_EnableIntChannel(LPC_DMA, channel); - - Chip_DMA_SetupChannelConfig(LPC_DMA, channel, DMA_CFG_PERIPHREQEN | - DMA_CFG_CHPRIORITY(priority)); - - if (src_increment != DMA_XFERCFG_SRCINC_0) { - Chip_DMA_Table[channel].source = DMA_ADDR((src_address + length_bytes) - - (1UL << xfr_width)); - } else { - Chip_DMA_Table[channel].source = DMA_ADDR(src_address); - } - - if (dst_increment != DMA_XFERCFG_DSTINC_0) { - Chip_DMA_Table[channel].dest = DMA_ADDR((dst_address + length_bytes) - - (1UL << xfr_width)); - } else { - Chip_DMA_Table[channel].dest = DMA_ADDR(dst_address); - } - Chip_DMA_Table[channel].next = DMA_ADDR(0); - - } - - /** - * Start the DMA transfer - * - * @param channel - * @param src_increment - * @param dst_increment - * @param xfr_width - * @param length_bytes - */ - void ChipEz_DMA_StartTransfer(DMA_CHID_T channel, uint32_t src_increment, uint32_t dst_increment, uint32_t xfr_width, uint32_t length_bytes) - { - uint32_t xfer_count; - - /* Calculate transfer_count ( length in terms of transfers) */ - xfer_count = (xfr_width == DMA_XFERCFG_WIDTH_8) ? length_bytes : - (xfr_width == DMA_XFERCFG_WIDTH_16) ? (length_bytes >> 1) : - (length_bytes >> 2); - - Chip_DMA_SetupChannelTransfer(LPC_DMA, channel, - (DMA_XFERCFG_CFGVALID | DMA_XFERCFG_SETINTA | DMA_XFERCFG_SWTRIG | - xfr_width | src_increment | dst_increment | - DMA_XFERCFG_XFERCOUNT(xfer_count))); - } - -bool ChipEzr_DMA_Transfer( DMA_CHID_T channel, uint32_t src_address, uint32_t src_increment, - uint32_t dst_address, uint32_t dst_increment, uint32_t xfr_width, uint32_t length_bytes, uint32_t priority) -{ - if ((Chip_DMA_GetBusyChannels(LPC_DMA) & (1 << channel)) != 0) - return FALSE; - ChipEz_DMA_InitChannel(channel, src_address, src_increment, dst_address, dst_increment, xfr_width, length_bytes, priority); - ChipEz_DMA_StartTransfer(channel, src_increment, dst_increment, xfr_width, length_bytes); - return TRUE; -} - -void ChipEz_DMA_AbortChannel(DMA_CHID_T ch) { - Chip_DMA_DisableChannel(LPC_DMA, ch); - while ((Chip_DMA_GetBusyChannels(LPC_DMA) & (1 << ch)) != 0) {} - Chip_DMA_AbortChannel(LPC_DMA, ch); - Chip_DMA_ClearErrorIntChannel(LPC_DMA, ch); -} - diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/dma/dma_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/dma/dma_8xx.h deleted file mode 100644 index 5cc62eafb65..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/dma/dma_8xx.h +++ /dev/null @@ -1,810 +0,0 @@ -/* - * @brief LPC8xx DMA chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2013 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __DMA_8XX_H_ -#define __DMA_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup DMA_8XX CHIP: LPC8xx DMA Controller driver - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/** - * @brief DMA Controller shared registers structure - */ -typedef struct { /*!< DMA shared registers structure */ - __IO uint32_t ENABLESET; /*!< DMA Channel Enable read and Set for all DMA channels */ - __I uint32_t RESERVED0; - __O uint32_t ENABLECLR; /*!< DMA Channel Enable Clear for all DMA channels */ - __I uint32_t RESERVED1; - __I uint32_t ACTIVE; /*!< DMA Channel Active status for all DMA channels */ - __I uint32_t RESERVED2; - __I uint32_t BUSY; /*!< DMA Channel Busy status for all DMA channels */ - __I uint32_t RESERVED3; - __IO uint32_t ERRINT; /*!< DMA Error Interrupt status for all DMA channels */ - __I uint32_t RESERVED4; - __IO uint32_t INTENSET; /*!< DMA Interrupt Enable read and Set for all DMA channels */ - __I uint32_t RESERVED5; - __O uint32_t INTENCLR; /*!< DMA Interrupt Enable Clear for all DMA channels */ - __I uint32_t RESERVED6; - __IO uint32_t INTA; /*!< DMA Interrupt A status for all DMA channels */ - __I uint32_t RESERVED7; - __IO uint32_t INTB; /*!< DMA Interrupt B status for all DMA channels */ - __I uint32_t RESERVED8; - __O uint32_t SETVALID; /*!< DMA Set ValidPending control bits for all DMA channels */ - __I uint32_t RESERVED9; - __O uint32_t SETTRIG; /*!< DMA Set Trigger control bits for all DMA channels */ - __I uint32_t RESERVED10; - __O uint32_t ABORT; /*!< DMA Channel Abort control for all DMA channels */ -} LPC_DMA_COMMON_T; - -/** - * @brief DMA Controller shared registers structure - */ -typedef struct { /*!< DMA channel register structure */ - __IO uint32_t CFG; /*!< DMA Configuration register */ - __I uint32_t CTLSTAT; /*!< DMA Control and status register */ - __IO uint32_t XFERCFG; /*!< DMA Transfer configuration register */ - __I uint32_t RESERVED; -} LPC_DMA_CHANNEL_T; - -/* Reserved bits masks... */ -#define DMA_CFG_RESERVED ((3<<2)|(1<<7)|(3<<12)|0xfffc0000) -#define DMA_CTLSTAT_RESERVED (~(1|(1<<2))) -#define DMA_XFERCFG_RESERVED ((3<<6)|(3<<10)|(0x3fu<<26)) - -/* DMA channel mapping - each channel is mapped to an individual peripheral - and direction or a DMA imput mux trigger */ -typedef enum { - DMAREQ_USART0_RX, /*!< USART0 receive DMA channel */ - DMA_CH0 = DMAREQ_USART0_RX, - DMAREQ_USART0_TX, /*!< USART0 transmit DMA channel */ - DMA_CH1 = DMAREQ_USART0_TX, - DMAREQ_USART1_RX, /*!< USART1 receive DMA channel */ - DMA_CH2 = DMAREQ_USART1_RX, - DMAREQ_USART1_TX, /*!< USART1 transmit DMA channel */ - DMA_CH3 = DMAREQ_USART1_TX, - DMAREQ_USART2_RX, /*!< USART2 receive DMA channel */ - DMA_CH4 = DMAREQ_USART2_RX, - DMAREQ_USART2_TX, /*!< USART2 transmit DMA channel */ - DMA_CH5 = DMAREQ_USART2_TX, - DMAREQ_SPI0_RX, - DMA_CH6 = DMAREQ_SPI0_RX, /*!< SPI0 receive DMA channel */ - DMAREQ_SPI0_TX, - DMA_CH7 = DMAREQ_SPI0_TX, /*!< SPI0 transmit DMA channel */ - DMAREQ_SPI1_RX, - DMA_CH8 = DMAREQ_SPI1_RX, /*!< SPI1 receive DMA channel */ - DMAREQ_SPI1_TX, - DMA_CH9 = DMAREQ_SPI1_TX, /*!< SPI1 transmit DMA channel */ - DMAREQ_I2C0_MST, - DMA_CH10 = DMAREQ_I2C0_MST, /*!< I2C0 Master DMA channel */ - DMAREQ_I2C0_SLV, - DMA_CH11 = DMAREQ_I2C0_SLV, /*!< I2C0 Slave DMA channel */ - DMAREQ_I2C1_MST, - DMA_CH12 = DMAREQ_I2C1_MST, /*!< I2C1 Master DMA channel */ - DMAREQ_I2C1_SLV, - DMA_CH13 = DMAREQ_I2C1_SLV, /*!< I2C1 Slave DMA channel */ - DMAREQ_I2C2_MST, - DMA_CH14 = DMAREQ_I2C2_MST, /*!< I2C2 Master DMA channel */ - DMAREQ_I2C2_SLV, - DMA_CH15 = DMAREQ_I2C2_SLV, /*!< I2C2 Slave DMA channel */ - DMAREQ_I2C3_MST, - DMA_CH16 = DMAREQ_I2C3_MST, /*!< I2C2 Master DMA channel */ - DMAREQ_I2C3_SLV, - DMA_CH17 = DMAREQ_I2C3_SLV, /*!< I2C2 Slave DMA channel */ -} DMA_CHID_T; - -/* On LPC82x, Max DMA channel is 18 */ -#define MAX_DMA_CHANNEL (DMA_CH17 + 1) - -/* Reserved bits masks... */ -#define DMA_COMMON_RESERVED (~(0UL) << MAX_DMA_CHANNEL) -#define DMA_ENABLESET_RESERVED DMA_COMMON_RESERVED -#define DMA_ENABLECLR_RESERVED DMA_COMMON_RESERVED -#define DMA_ACTIVE_RESERVED DMA_COMMON_RESERVED -#define DMA_BUSY_RESERVED DMA_COMMON_RESERVED -#define DMA_ERRINT_RESERVED DMA_COMMON_RESERVED -#define DMA_INTENSET_RESERVED DMA_COMMON_RESERVED -#define DMA_INTENCLR_RESERVED DMA_COMMON_RESERVED -#define DMA_INTA_RESERVED DMA_COMMON_RESERVED -#define DMA_INTB_RESERVED DMA_COMMON_RESERVED -#define DMA_SETVALID_RESERVED DMA_COMMON_RESERVED -#define DMA_SETTRIG_RESERVED DMA_COMMON_RESERVED -#define DMA_ABORT_RESERVED DMA_COMMON_RESERVED - -/** - * @brief DMA Controller register block structure - */ -typedef struct { /*!< DMA Structure */ - __IO uint32_t CTRL; /*!< DMA control register */ - __I uint32_t INTSTAT; /*!< DMA Interrupt status register */ - __IO uint32_t SRAMBASE; /*!< DMA SRAM address of the channel configuration table */ - __I uint32_t RESERVED2[5]; - LPC_DMA_COMMON_T DMACOMMON[1]; /*!< DMA shared channel (common) registers */ - __I uint32_t RESERVED0[225]; - LPC_DMA_CHANNEL_T DMACH[MAX_DMA_CHANNEL]; /*!< DMA channel registers */ -} LPC_DMA_T; - -/* Reserved bits masks... */ -#define DMA_CTRL_RESERVED (~1) -#define DMA_INTSTAT_RESERVED (~7) -#define DMA_SRAMBASE_RESERVED (0xFF) - -typedef enum { - WIDTH_8_BITS = 0, - WIDTH_16_BITS = 1, - WIDTH_32_BITS = 2 -} DataWidth; - - -/** - * @brief Easy API, setup all required things to make DMA ready to use - * @param ch : DMA channel ID - * @return Nothing - */ -void ChipEz_DMA_Init(uint32_t isEnableIRQ); - -/** - * @brief Easy API, setup the next transfer for a channel, this function updates DMA descriptor - * @param ch : DMA channel ID - * @param src_address: Source base address - * @param src_increment: Increment of source address after each transfer. Could be DMA_XFERCFG_SRCINC_0/1/2/4 - * @param dst_address: Destination base address - * @param dst_increment: Increment of destination address after each transfer. Could be DMA_XFERCFG_DSTINC_0/1/2/4 - * @param xfr_width: Width of transfer unit, could be WIDTH_8_BITS, WIDTH_16_BITS, or WIDTH_32_BITS - * @param length_bytes: Transfer length, in bytes. Must NOT makes transfer unit count exceed 1024. - * @param priority: Channel priority, used internally in DMA, could be from 0 (highest) to 7 (lowest) - * @return Nothing - * @note This function will set the DMA descriptor in the SRAM table to the - * the passed descriptor. This function is only meant to be used when - * the DMA channel is not active and can be used to setup the - * initial transfer for a linked list or ping-pong buffer or just a - * single transfer without a next descriptor. - */ -void ChipEz_DMA_InitChannel( DMA_CHID_T ch, uint32_t src_address, uint32_t src_increment, - uint32_t dst_address, uint32_t dst_increment, uint32_t xfr_width, uint32_t length_bytes, uint32_t priority); - -/** - * @brief Easy API, Start transfer of a DMA channel - * @param ch : DMA channel ID - * @param src_increment: Increment of source address after each transfer. Could be DMA_XFERCFG_SRCINC_0/1/2/4. - * Should be consistent with the same parameter used in ChipEz_DMA_InitChannel() - * @param dst_increment: Increment of destination address after each transfer. Could be DMA_XFERCFG_DSTINC_0/1/2/4 - * hould be consistent with the same parameter used in ChipEz_DMA_InitChannel() - * @param xfr_width: Width of transfer unit, could be WIDTH_8_BITS, WIDTH_16_BITS, or WIDTH_32_BITS - * Should be consistent with the same parameter used in ChipEz_DMA_InitChannel() - * @param length_bytes: Transfer length, in bytes. Must NOT makes transfer unit count exceed 1024. - * Should be consistent with the same parameter used in ChipEz_DMA_InitChannel() - * @param priority: Channel priority, used internally in DMA, could be from 0 (highest) to 7 (lowest) - * @return Nothing - */ - -void ChipEz_DMA_StartTransfer(DMA_CHID_T ch, uint32_t src_increment, uint32_t dst_increment, uint32_t xfr_width, uint32_t length_bytes); - -/** - * @brief Easier API, Combine ChipEz_DMA_InitChannel and ChipEz_DMA_StartTransfer with channel busy check - parameter is the same as ChipEz_DMA_InitChannel - @return TRUE when success, FALSE when current channel is busy. - */ -bool ChipEzr_DMA_Transfer( DMA_CHID_T channel, uint32_t src_address, uint32_t src_increment, - uint32_t dst_address, uint32_t dst_increment, uint32_t xfr_width, uint32_t length_bytes, uint32_t priority); - - -/** - * @brief Easy API, Abort a DMA channel safely - * @param ch : DMA channel ID - * @return Nothing - */ -void ChipEz_DMA_AbortChannel(DMA_CHID_T ch); - -/** @defgroup DMA_COMMONDRV_8XX CHIP: LPC8xx DMA Controller driver common functions - * @{ - */ - -/** - * @brief Initialize DMA controller - * @param pDMA : The base of DMA controller on the chip - * @return Nothing - */ -STATIC INLINE void Chip_DMA_Init(LPC_DMA_T *pDMA) -{ - (void) pDMA; - Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_DMA); -} - -/** - * @brief De-Initialize DMA controller - * @param pDMA : The base of DMA controller on the chip - * @return Nothing - */ -STATIC INLINE void Chip_DMA_DeInit(LPC_DMA_T *pDMA) -{ - (void) pDMA; - Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_DMA); -} - -/** - * @brief Enable DMA controller - * @param pDMA : The base of DMA controller on the chip - * @return Nothing - */ -STATIC INLINE void Chip_DMA_Enable(LPC_DMA_T *pDMA) -{ - pDMA->CTRL = 1; -} - -/** - * @brief Disable DMA controller - * @param pDMA : The base of DMA controller on the chip - * @return Nothing - */ -STATIC INLINE void Chip_DMA_Disable(LPC_DMA_T *pDMA) -{ - pDMA->CTRL = 0; -} - -/* DMA interrupt status bits (common) */ -#define DMA_INTSTAT_ACTIVEINT 0x2 /*!< Summarizes whether any enabled interrupts are pending */ -#define DMA_INTSTAT_ACTIVEERRINT 0x4 /*!< Summarizes whether any error interrupts are pending */ - -/** - * @brief Get pending interrupt or error interrupts - * @param pDMA : The base of DMA controller on the chip - * @return An Or'ed value of DMA_INTSTAT_* types - * @note If any DMA channels have an active interrupt or error interrupt - * pending, this functional will a common status that applies to all - * channels. - */ -STATIC INLINE uint32_t Chip_DMA_GetIntStatus(LPC_DMA_T *pDMA) -{ - return (pDMA->INTSTAT & ~DMA_INTSTAT_RESERVED); -} - -/* DMA channel source/address/next descriptor */ -typedef struct { - uint32_t xfercfg; /*!< Transfer configuration (only used in linked lists and ping-pong configs) */ - uint32_t source; /*!< DMA transfer source end address */ - uint32_t dest; /*!< DMA transfer desintation end address */ - uint32_t next; /*!< Link to next DMA descriptor, must be 16 byte aligned */ -} DMA_CHDESC_T; - -/* DMA SRAM table - this can be optionally used with the Chip_DMA_SetSRAMBase() - function if a DMA SRAM table is needed. */ -extern DMA_CHDESC_T Chip_DMA_Table[MAX_DMA_CHANNEL]; - -/** - * @brief Set DMA controller SRAM base address - * @param pDMA : The base of DMA controller on the chip - * @param base : The base address where the DMA descriptors will be stored - * @return Nothing - * @note A 256 byte block of memory aligned on a 256 byte boundary must be - * provided for this function. It sets the base address used for - * DMA descriptor table (16 descriptors total that use 16 bytes each).
- * - * A pre-defined table with correct alignment can be used for this - * function by calling Chip_DMA_SetSRAMBase(LPC_DMA, DMA_ADDR(Chip_DMA_Table)); - */ -STATIC INLINE void Chip_DMA_SetSRAMBase(LPC_DMA_T *pDMA, uint32_t base) -{ - pDMA->SRAMBASE = base; -} - -/** - * @brief Returns DMA controller SRAM base address - * @param pDMA : The base of DMA controller on the chip - * @return The base address where the DMA descriptors are stored - */ -STATIC INLINE uint32_t Chip_DMA_GetSRAMBase(LPC_DMA_T *pDMA) -{ - return (pDMA->SRAMBASE & ~DMA_SRAMBASE_RESERVED); -} - -/** - * @} - */ - -/** @defgroup DMA_COMMON_8XX CHIP: LPC8xx DMA Controller driver common channel functions - * @{ - */ - -/** - * @brief Enables a single DMA channel - * @param pDMA : The base of DMA controller on the chip - * @param ch : DMA channel ID - * @return Nothing - */ -STATIC INLINE void Chip_DMA_EnableChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) -{ - pDMA->DMACOMMON[0].ENABLESET = (1 << ch); -} - -/** - * @brief Disables a single DMA channel - * @param pDMA : The base of DMA controller on the chip - * @param ch : DMA channel ID - * @return Nothing - */ -STATIC INLINE void Chip_DMA_DisableChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) -{ - pDMA->DMACOMMON[0].ENABLECLR = (1 << ch); -} - -/** - * @brief Returns all enabled DMA channels - * @param pDMA : The base of DMA controller on the chip - * @return An Or'ed value of all enabled DMA channels (0 - 15) - * @note A high values in bits 0 .. 15 in the return values indicates - * that the channel for that bit (bit 0 = channel 0, bit 1 - - * channel 1, etc.) is enabled. A low state is disabled. - */ -STATIC INLINE uint32_t Chip_DMA_GetEnabledChannels(LPC_DMA_T *pDMA) -{ - return (pDMA->DMACOMMON[0].ENABLESET & ~DMA_ENABLESET_RESERVED); -} - -/** - * @brief Returns all active DMA channels - * @param pDMA : The base of DMA controller on the chip - * @return An Or'ed value of all active DMA channels (0 - 15) - * @note A high values in bits 0 .. 15 in the return values indicates - * that the channel for that bit (bit 0 = channel 0, bit 1 - - * channel 1, etc.) is active. A low state is inactive. A active - * channel indicates that a DMA operation has been started but - * not yet fully completed. - */ -STATIC INLINE uint32_t Chip_DMA_GetActiveChannels(LPC_DMA_T *pDMA) -{ - return (pDMA->DMACOMMON[0].ACTIVE & ~DMA_ACTIVE_RESERVED); -} - -/** - * @brief Returns all busy DMA channels - * @param pDMA : The base of DMA controller on the chip - * @return An Or'ed value of all busy DMA channels (0 - 15) - * @note A high values in bits 0 .. 15 in the return values indicates - * that the channel for that bit (bit 0 = channel 0, bit 1 - - * channel 1, etc.) is busy. A low state is not busy. A DMA - * channel is considered busy when there is any operation - * related to that channel in the DMA controller's internal - * pipeline. - */ -STATIC INLINE uint32_t Chip_DMA_GetBusyChannels(LPC_DMA_T *pDMA) -{ - return (pDMA->DMACOMMON[0].BUSY & ~DMA_BUSY_RESERVED); -} - -/** - * @brief Returns pending error interrupt status for all DMA channels - * @param pDMA : The base of DMA controller on the chip - * @return An Or'ed value of all channels (0 - 15) error interrupt status - * @note A high values in bits 0 .. 15 in the return values indicates - * that the channel for that bit (bit 0 = channel 0, bit 1 - - * channel 1, etc.) has a pending error interrupt. A low state - * indicates no error interrupt. - */ -STATIC INLINE uint32_t Chip_DMA_GetErrorIntChannels(LPC_DMA_T *pDMA) -{ - return (pDMA->DMACOMMON[0].ERRINT & ~DMA_ERRINT_RESERVED); -} - -/** - * @brief Clears a pending error interrupt status for a single DMA channel - * @param pDMA : The base of DMA controller on the chip - * @param ch : DMA channel ID - * @return Nothing - */ -STATIC INLINE void Chip_DMA_ClearErrorIntChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) -{ - pDMA->DMACOMMON[0].ERRINT = (1 << ch); -} - -/** - * @brief Enables a single DMA channel's interrupt used in common DMA interrupt - * @param pDMA : The base of DMA controller on the chip - * @param ch : DMA channel ID - * @return Nothing - */ -STATIC INLINE void Chip_DMA_EnableIntChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) -{ - pDMA->DMACOMMON[0].INTENSET = (1 << ch); -} - -/** - * @brief Disables a single DMA channel's interrupt used in common DMA interrupt - * @param pDMA : The base of DMA controller on the chip - * @param ch : DMA channel ID - * @return Nothing - */ -STATIC INLINE void Chip_DMA_DisableIntChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) -{ - pDMA->DMACOMMON[0].INTENCLR = (1 << ch); -} - -/** - * @brief Returns all enabled interrupt channels - * @param pDMA : The base of DMA controller on the chip - * @return Nothing - * @note A high values in bits 0 .. 15 in the return values indicates - * that the channel for that bit (bit 0 = channel 0, bit 1 - - * channel 1, etc.) has an enabled interrupt for the channel. - * A low state indicates that the DMA channel will not contribute - * to the common DMA interrupt status. - */ -STATIC INLINE uint32_t Chip_DMA_GetEnableIntChannels(LPC_DMA_T *pDMA) -{ - return (pDMA->DMACOMMON[0].INTENSET & ~DMA_INTENSET_RESERVED); -} - -/** - * @brief Returns active A interrupt status for all channels - * @param pDMA : The base of DMA controller on the chip - * @return Nothing - * @note A high values in bits 0 .. 15 in the return values indicates - * that the channel for that bit (bit 0 = channel 0, bit 1 - - * channel 1, etc.) has an active A interrupt for the channel. - * A low state indicates that the A interrupt is not active. - */ -STATIC INLINE uint32_t Chip_DMA_GetActiveIntAChannels(LPC_DMA_T *pDMA) -{ - return (pDMA->DMACOMMON[0].INTA & ~DMA_INTA_RESERVED); -} - -/** - * @brief Clears active A interrupt status for a single channel - * @param pDMA : The base of DMA controller on the chip - * @param ch : DMA channel ID - * @return Nothing - */ -STATIC INLINE void Chip_DMA_ClearActiveIntAChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) -{ - pDMA->DMACOMMON[0].INTA = (1 << ch); -} - -/** - * @brief Returns active B interrupt status for all channels - * @param pDMA : The base of DMA controller on the chip - * @return Nothing - * @note A high values in bits 0 .. 15 in the return values indicates - * that the channel for that bit (bit 0 = channel 0, bit 1 - - * channel 1, etc.) has an active B interrupt for the channel. - * A low state indicates that the B interrupt is not active. - */ -STATIC INLINE uint32_t Chip_DMA_GetActiveIntBChannels(LPC_DMA_T *pDMA) -{ - return (pDMA->DMACOMMON[0].INTB & ~DMA_INTB_RESERVED); -} - -/** - * @brief Clears active B interrupt status for a single channel - * @param pDMA : The base of DMA controller on the chip - * @param ch : DMA channel ID - * @return Nothing - */ -STATIC INLINE void Chip_DMA_ClearActiveIntBChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) -{ - pDMA->DMACOMMON[0].INTB = (1 << ch); -} - -/** - * @brief Sets the VALIDPENDING control bit for a single channel - * @param pDMA : The base of DMA controller on the chip - * @param ch : DMA channel ID - * @return Nothing - * @note See the User Manual for more information for what this bit does. - * - */ -STATIC INLINE void Chip_DMA_SetValidChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) -{ - pDMA->DMACOMMON[0].SETVALID = (1 << ch); -} - -/** - * @brief Sets the TRIG bit for a single channel - * @param pDMA : The base of DMA controller on the chip - * @param ch : DMA channel ID - * @return Nothing - * @note See the User Manual for more information for what this bit does. - */ -STATIC INLINE void Chip_DMA_SetTrigChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) -{ - pDMA->DMACOMMON[0].SETTRIG = (1 << ch); -} - -/** - * @brief Aborts a DMA operation for a single channel - * @param pDMA : The base of DMA controller on the chip - * @param ch : DMA channel ID - * @return Nothing - * @note To abort a channel, the channel should first be disabled. Then wait - * until the channel is no longer busy by checking the corresponding - * bit in BUSY. Finally, abort the channel operation. This prevents the - * channel from restarting an incomplete operation when it is enabled - * again. - */ -STATIC INLINE void Chip_DMA_AbortChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) -{ - pDMA->DMACOMMON[0].ABORT = (1 << ch); -} - -/** - * @} - */ - - -/** @defgroup DMA_CHANNEL_8XX CHIP: LPC8xx DMA Controller driver channel specific functions - * @{ - */ - -/* Support macro for DMA_CHDESC_T */ -#define DMA_ADDR(addr) ((uint32_t) (addr)) - -/* Support definitions for setting the configuration of a DMA channel. You - will need to get more information on these options from the User manual. */ -#define DMA_CFG_PERIPHREQEN (1 << 0) /*!< Enables Peripheral DMA requests */ -#define DMA_CFG_HWTRIGEN (1 << 1) /*!< Use hardware triggering via imput mux */ -#define DMA_CFG_TRIGPOL_LOW (0 << 4) /*!< Hardware trigger is active low or falling edge */ -#define DMA_CFG_TRIGPOL_HIGH (1 << 4) /*!< Hardware trigger is active high or rising edge */ -#define DMA_CFG_TRIGTYPE_EDGE (0 << 5) /*!< Hardware trigger is edge triggered */ -#define DMA_CFG_TRIGTYPE_LEVEL (1 << 5) /*!< Hardware trigger is level triggered */ -#define DMA_CFG_TRIGBURST_SNGL (0 << 6) /*!< Single transfer. Hardware trigger causes a single transfer */ -#define DMA_CFG_TRIGBURST_BURST (1 << 6) /*!< Burst transfer (see UM) */ -#define DMA_CFG_BURSTPOWER_1 (0 << 8) /*!< Set DMA burst size to 1 transfer */ -#define DMA_CFG_BURSTPOWER_2 (1 << 8) /*!< Set DMA burst size to 2 transfers */ -#define DMA_CFG_BURSTPOWER_4 (2 << 8) /*!< Set DMA burst size to 4 transfers */ -#define DMA_CFG_BURSTPOWER_8 (3 << 8) /*!< Set DMA burst size to 8 transfers */ -#define DMA_CFG_BURSTPOWER_16 (4 << 8) /*!< Set DMA burst size to 16 transfers */ -#define DMA_CFG_BURSTPOWER_32 (5 << 8) /*!< Set DMA burst size to 32 transfers */ -#define DMA_CFG_BURSTPOWER_64 (6 << 8) /*!< Set DMA burst size to 64 transfers */ -#define DMA_CFG_BURSTPOWER_128 (7 << 8) /*!< Set DMA burst size to 128 transfers */ -#define DMA_CFG_BURSTPOWER_256 (8 << 8) /*!< Set DMA burst size to 256 transfers */ -#define DMA_CFG_BURSTPOWER_512 (9 << 8) /*!< Set DMA burst size to 512 transfers */ -#define DMA_CFG_BURSTPOWER_1024 (10 << 8) /*!< Set DMA burst size to 1024 transfers */ -#define DMA_CFG_BURSTPOWER(n) ((n) << 8) /*!< Set DMA burst size to 2^n transfers, max n=10 */ -#define DMA_CFG_SRCBURSTWRAP (1 << 14) /*!< Source burst wrapping is enabled for this DMA channel */ -#define DMA_CFG_DSTBURSTWRAP (1 << 15) /*!< Destination burst wrapping is enabled for this DMA channel */ -#define DMA_CFG_CHPRIORITY(p) ((p) << 16) /*!< Sets DMA channel priority, min 0 (highest), max 3 (lowest) */ - -/** - * @brief Setup a DMA channel configuration - * @param pDMA : The base of DMA controller on the chip - * @param ch : DMA channel ID - * @param cfg : An Or'ed value of DMA_CFG_* values that define the channel's configuration - * @return Nothing - * @note This function sets up all configurable options for the DMA channel. - * These options are usually set once for a channel and then unchanged.
- * - * The following example show how to configure the channel for peripheral - * DMA requests, burst transfer size of 1 (in 'transfers', not bytes), - * continuous reading of the same source address, incrementing destination - * address, and highest channel priority.
- * Example: Chip_DMA_SetupChannelConfig(pDMA, SSP0_RX_DMA, - * (DMA_CFG_PERIPHREQEN | DMA_CFG_TRIGBURST_BURST | DMA_CFG_BURSTPOWER_1 | - * DMA_CFG_SRCBURSTWRAP | DMA_CFG_CHPRIORITY(0)));
- * - * The following example show how to configure the channel for an external - * trigger from the imput mux with low edge polarity, a burst transfer size of 8, - * incrementing source and destination addresses, and lowest channel - * priority.
- * Example: Chip_DMA_SetupChannelConfig(pDMA, DMA_CH14, - * (DMA_CFG_HWTRIGEN | DMA_CFG_TRIGPOL_LOW | DMA_CFG_TRIGTYPE_EDGE | - * DMA_CFG_TRIGBURST_BURST | DMA_CFG_BURSTPOWER_8 | - * DMA_CFG_CHPRIORITY(3)));
- * - * For non-peripheral DMA triggering (DMA_CFG_HWTRIGEN definition), use the - * DMA input mux functions to configure the DMA trigger source for a DMA channel. - */ -STATIC INLINE void Chip_DMA_SetupChannelConfig(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t cfg) -{ - pDMA->DMACH[ch].CFG = cfg; -} - -/* DMA channel control and status register definitions */ -#define DMA_CTLSTAT_VALIDPENDING (1 << 0) /*!< Valid pending flag for this channel */ -#define DMA_CTLSTAT_TRIG (1 << 2) /*!< Trigger flag. Indicates that the trigger for this channel is currently set */ - -/** - * @brief Returns channel specific status flags - * @param pDMA : The base of DMA controller on the chip - * @param ch : DMA channel ID - * @return AN Or'ed value of DMA_CTLSTAT_VALIDPENDING and DMA_CTLSTAT_TRIG - */ -STATIC INLINE uint32_t Chip_DMA_GetChannelStatus(LPC_DMA_T *pDMA, DMA_CHID_T ch) -{ - return (pDMA->DMACH[ch].XFERCFG & ~DMA_XFERCFG_RESERVED); -} - -/* DMA channel transfer configuration registers definitions */ -#define DMA_XFERCFG_CFGVALID (1 << 0) /*!< Configuration Valid flag */ -#define DMA_XFERCFG_RELOAD (1 << 1) /*!< Indicates whether the channels control structure will be reloaded when the current descriptor is exhausted */ -#define DMA_XFERCFG_SWTRIG (1 << 2) /*!< Software Trigger */ -#define DMA_XFERCFG_CLRTRIG (1 << 3) /*!< Clear Trigger */ -#define DMA_XFERCFG_SETINTA (1 << 4) /*!< Set Interrupt flag A for this channel to fire when descriptor is complete */ -#define DMA_XFERCFG_SETINTB (1 << 5) /*!< Set Interrupt flag B for this channel to fire when descriptor is complete */ -#define DMA_XFERCFG_WIDTH_8 (0 << 8) /*!< 8-bit transfers are performed */ -#define DMA_XFERCFG_WIDTH_16 (1 << 8) /*!< 16-bit transfers are performed */ -#define DMA_XFERCFG_WIDTH_32 (2 << 8) /*!< 32-bit transfers are performed */ -#define DMA_XFERCFG_SRCINC_0 (0 << 12) /*!< DMA source address is not incremented after a transfer */ -#define DMA_XFERCFG_SRCINC_1 (1 << 12) /*!< DMA source address is incremented by 1 (width) after a transfer */ -#define DMA_XFERCFG_SRCINC_2 (2 << 12) /*!< DMA source address is incremented by 2 (width) after a transfer */ -#define DMA_XFERCFG_SRCINC_4 (3 << 12) /*!< DMA source address is incremented by 4 (width) after a transfer */ -#define DMA_XFERCFG_DSTINC_0 (0 << 14) /*!< DMA destination address is not incremented after a transfer */ -#define DMA_XFERCFG_DSTINC_1 (1 << 14) /*!< DMA destination address is incremented by 1 (width) after a transfer */ -#define DMA_XFERCFG_DSTINC_2 (2 << 14) /*!< DMA destination address is incremented by 2 (width) after a transfer */ -#define DMA_XFERCFG_DSTINC_4 (3 << 14) /*!< DMA destination address is incremented by 4 (width) after a transfer */ -#define DMA_XFERCFG_XFERCOUNT(n) ((n - 1) << 16) /*!< DMA transfer count in 'transfers', between (0)1 and (1023)1024 */ - -/** - * @brief Setup a DMA channel transfer configuration - * @param pDMA : The base of DMA controller on the chip - * @param ch : DMA channel ID - * @param cfg : An Or'ed value of DMA_XFERCFG_* values that define the channel's transfer configuration - * @return Nothing - * @note This function sets up the transfer configuration for the DMA channel.
- * - * The following example show how to configure the channel's transfer for - * multiple transfer descriptors (ie, ping-pong), interrupt 'A' trigger on - * transfer descriptor completion, 128 byte size transfers, and source and - * destination address increment.
- * Example: Chip_DMA_SetupChannelTransfer(pDMA, SSP0_RX_DMA, - * (DMA_XFERCFG_CFGVALID | DMA_XFERCFG_RELOAD | DMA_XFERCFG_SETINTA | - * DMA_XFERCFG_WIDTH_8 | DMA_XFERCFG_SRCINC_1 | DMA_XFERCFG_DSTINC_1 | - * DMA_XFERCFG_XFERCOUNT(128)));
- */ -STATIC INLINE void Chip_DMA_SetupChannelTransfer(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t cfg) -{ - pDMA->DMACH[ch].XFERCFG = cfg; -} - -/** - * @brief Set DMA transfer register interrupt bits (safe) - * @param pDMA : The base of DMA controller on the chip - * @param ch : DMA channel ID - * @param mask : Bits to set - * @return Nothing - * @note This function safely sets bits in the DMA channel specific XFERCFG - * register. - */ -STATIC INLINE void Chip_DMA_SetTranBits(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t mask) -{ - /* Read and write values may not be the same, write 0 to - undefined bits */ - pDMA->DMACH[ch].XFERCFG = (pDMA->DMACH[ch].XFERCFG & ~DMA_XFERCFG_RESERVED) | mask; -} - -/** - * @brief Clear DMA transfer register interrupt bits (safe) - * @param pDMA : The base of DMA controller on the chip - * @param ch : DMA channel ID - * @param mask : Bits to clear - * @return Nothing - * @note This function safely clears bits in the DMA channel specific XFERCFG - * register. - */ -STATIC INLINE void Chip_DMA_ClearTranBits(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t mask) -{ - /* Read and write values may not be the same, write 0 to - undefined bits */ - pDMA->DMACH[ch].XFERCFG &= ~(DMA_XFERCFG_RESERVED | mask); -} - -/** - * @brief Update the transfer size in an existing DMA channel transfer configuration - * @param pDMA : The base of DMA controller on the chip - * @param ch : DMA channel ID - * @param trans : Number of transfers to update the transfer configuration to (1 - 1023) - * @return Nothing - */ -STATIC INLINE void Chip_DMA_SetupChannelTransferSize(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t trans) -{ - pDMA->DMACH[ch].XFERCFG = (pDMA->DMACH[ch].XFERCFG & ~(DMA_XFERCFG_RESERVED | (0x3FF << 16))) | DMA_XFERCFG_XFERCOUNT(trans); -} - -/** - * @brief Sets a DMA channel configuration as valid - * @param pDMA : The base of DMA controller on the chip - * @param ch : DMA channel ID - * @return Nothing - */ -STATIC INLINE void Chip_DMA_SetChannelValid(LPC_DMA_T *pDMA, DMA_CHID_T ch) -{ - Chip_DMA_SetTranBits(pDMA, ch, DMA_XFERCFG_CFGVALID); -} - -/** - * @brief Sets a DMA channel configuration as invalid - * @param pDMA : The base of DMA controller on the chip - * @param ch : DMA channel ID - * @return Nothing - */ -STATIC INLINE void Chip_DMA_SetChannelInValid(LPC_DMA_T *pDMA, DMA_CHID_T ch) -{ - Chip_DMA_ClearTranBits(pDMA, ch, DMA_XFERCFG_CFGVALID); -} - -/** - * @brief Performs a software trigger of the DMA channel - * @param pDMA : The base of DMA controller on the chip - * @param ch : DMA channel ID - * @return Nothing - */ -STATIC INLINE void Chip_DMA_SWTriggerChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch) -{ - Chip_DMA_SetTranBits(pDMA, ch, DMA_XFERCFG_SWTRIG); -} - -/** - * @brief Checks if the given channel is active or not - * @param pDMA : The base of DMA controller on the chip - * @param ch : DMA channel ID - * @return 1 if channel @a ch is active; 0 if channel @a ch is not active - */ -STATIC INLINE bool Chip_DMA_IsChannelActive(LPC_DMA_T *pDMA, DMA_CHID_T ch) -{ - return (pDMA->DMACOMMON[0].ACTIVE & (1 << ch)) != 0; -} - -/** - * @brief Sets up a DMA channel with the passed DMA transfer descriptor - * @param pDMA : The base of DMA controller on the chip - * @param ch : DMA channel ID - * @param desc : Pointer to DMA transfer descriptor - * @return false if the DMA channel was active, otherwise true - * @note This function will set the DMA descriptor in the SRAM table to the - * the passed descriptor. This function is only meant to be used when - * the DMA channel is not active and can be used to setup the - * initial transfer for a linked list or ping-pong buffer or just a - * single transfer without a next descriptor.
- * - * If using this function to write the initial transfer descriptor in - * a linked list or ping-pong buffer configuration, it should contain a - * non-NULL 'next' field pointer. - */ -STATIC INLINE bool Chip_DMA_SetupTranChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch, const DMA_CHDESC_T *desc) -{ - /* If channel is active return false */ - if (Chip_DMA_IsChannelActive(pDMA, ch)) - return false; - - /* Assign the descriptor to descriptor table */ - ((DMA_CHDESC_T *) (pDMA->SRAMBASE & ~DMA_SRAMBASE_RESERVED))[ch] = *desc; - return true; -} - - -/** - * @} - */ - -#endif /* __DMA_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/gpio/gpio_8xx.c b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/gpio/gpio_8xx.c deleted file mode 100644 index 6f82cfba065..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/gpio/gpio_8xx.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * @brief LPC8xx GPIO driver - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" -#include "gpio_8xx.h" -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -///* GPIO initilisation function */ -//void Chip_GPIO_Init(LPC_GPIO_T *pGPIO) -//{ -// Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO); -//} - -///* GPIO deinitialisation function */ -//void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO) -//{ -// Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_GPIO); -//} - diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/gpio/gpio_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/gpio/gpio_8xx.h deleted file mode 100644 index 4963b34aab5..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/gpio/gpio_8xx.h +++ /dev/null @@ -1,357 +0,0 @@ -/* - * @brief LPC8xx GPIO driver - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __GPIO_8XX_H_ -#define __GPIO_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup GPIO_8XX CHIP: LPC8xx GPIO driver - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/** - * @brief GPIO port register block structure - */ -typedef struct { /*!< GPIO_PORT Structure */ - __IO uint8_t B[128][32]; /*!< Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */ - __IO uint32_t W[32][32]; /*!< Offset 0x1000: Word pin registers port 0 to n */ - __IO uint32_t DIR[32]; /*!< Offset 0x2000: Direction registers port n */ - __IO uint32_t MASK[32]; /*!< Offset 0x2080: Mask register port n */ - __IO uint32_t PIN[32]; /*!< Offset 0x2100: Portpin register port n */ - __IO uint32_t MPIN[32]; /*!< Offset 0x2180: Masked port register port n */ - __IO uint32_t SET[32]; /*!< Offset 0x2200: Write: Set register for port n Read: output bits for port n */ - __O uint32_t CLR[32]; /*!< Offset 0x2280: Clear port n */ - __O uint32_t NOT[32]; /*!< Offset 0x2300: Toggle port n */ - __O uint32_t DIRSET[32]; /*!< Offset 0x2380: Set Direction */ - __O uint32_t DIRCLR[32]; /*!< Offset 0x2400: Clear Direction */ - __O uint32_t DIRNOT[32]; /*!< Offset 0x2480: Toggle Dirction */ -} LPC_GPIO_T; - -/** - * @brief Initialize GPIO block - * @param pGPIO : The base of GPIO peripheral on the chip - * @return Nothing - */ -STATIC INLINE void Chip_GPIO_Init(LPC_GPIO_T *pGPIO) -{ - LPC_SYSCTL->SYSAHBCLKCTRL = (1 << SYSCTL_CLOCK_GPIO) | (LPC_SYSCTL->SYSAHBCLKCTRL & ~SYSCTL_SYSAHBCLKCTRL_RESERVED); - -} - -/** - * @brief De-Initialize GPIO block - * @param pGPIO : The base of GPIO peripheral on the chip - * @return Nothing - */ -STATIC INLINE void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO) -{ - LPC_SYSCTL->SYSAHBCLKCTRL &= ~((1 << SYSCTL_CLOCK_GPIO) | SYSCTL_SYSAHBCLKCTRL_RESERVED); -} - -/** - * @brief Set GPIO direction for a single GPIO pin - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : GPIO port to set (supports port 0 only) - * @param pin : GPIO pin to set direction on as output - * @param isOutput: If new direction is output - * @return Nothing - */ -STATIC INLINE void Chip_GPIO_PinSetDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool isOutput) -{ - - #ifdef CHIP_LPC82X - if (isOutput) - pGPIO->DIRSET[port] = 1UL << pin; - else - pGPIO->DIRCLR[port] = 1UL << pin; - #else - if (isOutput) - pGPIO->DIR[port] |= 1UL << pin; - else - pGPIO->DIR[port] &= ~(1UL << pin); - #endif -} - -/** - * @brief Get GPIO direction for a single GPIO pin - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : GPIO port to read (supports port 0 only) - * @param pin : GPIO pin to get direction for - * @return true if the GPIO is an output, false if input - */ -STATIC INLINE bool Chip_GPIO_PinGetDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) -{ - return (bool) (((pGPIO->DIR[port]) >> pin) & 1); -} - -/** - * @brief Toggle GPIO direction for a single GPIO pin - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : GPIO port to set (supports port 0 only) - * @param pin : GPIO pin to toggle direction - * @return Nothing - */ -STATIC INLINE void Chip_GPIO_PinToggleDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) -{ -#ifdef CHIP_LPC82X - pGPIO->DIRNOT[port] = 1UL << pin; -#else - pGPIO->DIR[port] ^= 1UL << pin; -#endif -} - -/** - * @brief Set a GPIO pin state via the GPIO byte register - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : GPIO port to set (supports port 0 only) - * @param pin : GPIO pin to set - * @param setting : true for high, false for low - * @return Nothing - * @note This function replaces Chip_GPIO_WritePortBit() - */ -STATIC INLINE void Chip_GPIO_PinSetState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool setting) -{ - pGPIO->B[port][pin] = setting; -} - - -/** - * @brief Get a GPIO pin state via the GPIO byte register - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : GPIO port to read (supports port 0 only) - * @param pin : GPIO pin to get state for - * @return true if the GPIO is high, false if low - * @note This function replaces Chip_GPIO_ReadPortBit() - */ -STATIC INLINE bool Chip_GPIO_PinGetState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) -{ - return (bool) pGPIO->B[port][pin]; -} - -/** - * @brief Get a GPIO pin state via the GPIO byte register - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : GPIO port to read (supports port 0 only) - * @param pin : GPIO pin to get state for - * @return true if the GPIO is high, false if low - * @note This function replaces Chip_GPIO_ReadPortBit() - */ -STATIC INLINE void Chip_GPIO_PinToggleState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) -{ - pGPIO->NOT[port] = 1UL << pin; -} - -/** - * @brief Set GPIO direction for a all selected GPIO pins - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @param pinMask : GPIO pin mask to set direction on as output (bits 0..b for pins 0..n) - * @param isOutput: If new direction is output - * @return Nothing - * @note Sets multiple GPIO pins to the output direction, each bit's position that is - * high sets the corresponding pin number for that bit to an output. - */ -STATIC INLINE void Chip_GPIO_PortSetDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pinMask, bool isOutput) -{ -#ifdef CHIP_LPC82X - if (isOutput) - pGPIO->DIRSET[port] = pinMask; - else - pGPIO->DIRCLR[port] = pinMask; -#else - if (isOutput) - pGPIO->DIR[port] |= pinMask; - else - pGPIO->DIR[port] &= ~pinMask; -#endif -} - -/** - * @brief Get GPIO direction for a all GPIO pins - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @return a bitfield containing the input and output states for each pin - * @note For pins 0..n, a high state in a bit corresponds to an output state for the - * same pin, while a low state corresponds to an input state. - */ -STATIC INLINE uint32_t Chip_GPIO_PortGetDIR(LPC_GPIO_T *pGPIO, uint8_t port) -{ - return pGPIO->DIR[port]; -} - -/** - * @brief Toggle GPIO direction for a all selected GPIO pins - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @param pinMask : GPIO pin mask Toggle direction (bits 0..n for pins 0..n) - * @return Nothing - * @note Toggles multiple GPIO pin's direction, each bit's position that is - * high toggles direction of the corresponding pin number. - */ -STATIC INLINE void Chip_GPIO_PortToggleDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pinMask) -{ -#ifdef CHIP_LPC82X - pGPIO->DIRNOT[port] = pinMask; -#else - pGPIO->DIR[port] ^= pinMask; -#endif -} - -/** - * @brief Set all GPIO raw pin states (regardless of masking) - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @param value : Value to set all GPIO pin states (0..n) to - * @return Nothing - */ -STATIC INLINE void Chip_GPIO_PortSetState(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value) -{ - pGPIO->PIN[port] = value; -} - -/** - * @brief Get all GPIO raw pin states (regardless of masking) - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @return Current (raw) state of all GPIO pins - */ -STATIC INLINE uint32_t Chip_GPIO_PortGetState(LPC_GPIO_T *pGPIO, uint8_t port) -{ - return pGPIO->PIN[port]; -} - -/** - * @brief Toggle selected GPIO output pins to the opposite state - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @param pins : pins (0..n) to toggle - * @return None - * @note Any bit set as a '0' will not have it's state changed. This only - * applies to ports configured as an output. - */ -STATIC INLINE void Chip_GPIO_PortToggleState(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins) -{ - pGPIO->NOT[port] = pins; -} - -/** - * @brief Set selected GPIO output pins to the high state - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @param pins : pins (0..n) to set high - * @return None - * @note Any bit set as a '0' will not have it's state changed. This only - * applies to ports configured as an output. - */ -STATIC INLINE void Chip_GPIO_PortSetOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t bmPins) -{ - pGPIO->SET[port] = bmPins; -} - -/** - * @brief Set selected GPIO output pins to the low state - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @param pins : pins (0..n) to set low - * @return None - * @note Any bit set as a '0' will not have it's state changed. This only - * applies to ports configured as an output. - */ -STATIC INLINE void Chip_GPIO_PortSetOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins) -{ - pGPIO->CLR[port] = pins; -} - -/** - * @brief Set GPIO port mask value for GPIO masked read and write - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @param mask : Mask value for read and write (only low bits are enabled) - * @return Nothing - * @note Controls which bits are set or unset when using the masked - * GPIO read and write functions. A low state indicates the pin is settable - * and readable via the masked write and read functions. - */ -STATIC INLINE void Chip_GPIO_PortSetMask(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t mask) -{ - pGPIO->MASK[port] = mask; -} - -/** - * @brief Get GPIO port mask value used for GPIO masked read and write - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @return Returns value set with the Chip_GPIO_PortSetMask() function. - * @note A high bit in the return value indicates that that GPIO pin for the - * port cannot be set using the masked write function. - */ -STATIC INLINE uint32_t Chip_GPIO_PortGetMask(LPC_GPIO_T *pGPIO, uint8_t port) -{ - return pGPIO->MASK[port]; -} - -/** - * @brief Set all GPIO pin states, but mask via the MASKP0 register - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @param value : Value to set all GPIO pin states (0..n) to - * @return Nothing - */ -STATIC INLINE void Chip_GPIO_PortSetMaskedState(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value) -{ - pGPIO->MPIN[port] = value; -} - -/** - * @brief Get all GPIO pin statesm but mask via the MASKP0 register - * @param pGPIO : The base of GPIO peripheral on the chip - * @param port : port Number (supports port 0 only) - * @return Current (masked) state of all GPIO pins - */ -STATIC INLINE uint32_t Chip_GPIO_PortGetMaskedState(LPC_GPIO_T *pGPIO, uint8_t port) -{ - return pGPIO->MPIN[port]; -} - - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __GPIO_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/i2c/i2c_8xx.c b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/i2c/i2c_8xx.c deleted file mode 100644 index 46af72eb432..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/i2c/i2c_8xx.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * @brief LPC15xx I2C Common driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/* Get the RESET ID corresponding to the given I2C base */ -static CHIP_SYSCTL_PERIPH_RESET_T I2C_GetResetID(LPC_I2C_T *pI2C) -{ - uint32_t base = (uint32_t) pI2C; - switch (base) { - case LPC_I2C1_BASE: - return RESET_I2C1; - case LPC_I2C2_BASE: - return RESET_I2C2; - case LPC_I2C3_BASE: - return RESET_I2C3; - default: - return RESET_I2C0; - } -} - -/* Get the CLOCK ID corresponding to the given I2C base */ -static CHIP_SYSCTL_CLOCK_T I2C_GetClockID(LPC_I2C_T *pI2C) -{ - uint32_t base = (uint32_t) pI2C; - switch (base) { - case LPC_I2C1_BASE: - return SYSCTL_CLOCK_I2C1; - case LPC_I2C2_BASE: - return SYSCTL_CLOCK_I2C2; - case LPC_I2C3_BASE: - return SYSCTL_CLOCK_I2C3; - default: - return SYSCTL_CLOCK_I2C0; - } -} - -/** - * @brief Sets HIGH and LOW duty cycle registers - * @param pI2C : Pointer to selected I2C peripheral - * @param sclH : Number of I2C_PCLK cycles for the SCL HIGH time value between (2 - 9). - * @param sclL : Number of I2C_PCLK cycles for the SCL LOW time value between (2 - 9). - * @return Nothing - * @note The I2C clock divider should be set to the appropriate value before calling this function - * The I2C baud is determined by the following formula:
- * I2C_bitFrequency = (I2C_PCLK)/(I2C_CLKDIV * (sclH + sclL))
- * where I2C_PCLK is the frequency of the System clock and I2C_CLKDIV is I2C clock divider - */ -static void Chip_I2CM_SetDutyCycle(LPC_I2C_T *pI2C, uint16_t sclH, uint16_t sclL) -{ - /* Limit to usable range of timing values */ - if (sclH < 2) { - sclH = 2; - } - else if (sclH > 9) { - sclH = 9; - } - if (sclL < 2) { - sclL = 2; - } - else if (sclL > 9) { - sclL = 9; - } - - pI2C->MSTTIME = (((sclH - 2) & 0x07) << 4) | ((sclL - 2) & 0x07); -} - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Initializes the LPC_I2C peripheral */ -void Chip_I2C_Init(LPC_I2C_T *pI2C) -{ - /* Enable I2C clock */ - Chip_Clock_EnablePeriphClock(I2C_GetClockID(pI2C)); - - /* Peripheral reset control to I2C */ - Chip_SYSCTL_PeriphReset(I2C_GetResetID(pI2C)); -} - -/* Shuts down the I2C controller block */ -void Chip_I2C_DeInit(LPC_I2C_T *pI2C) -{ - /* Disable I2C clock */ - Chip_Clock_DisablePeriphClock(I2C_GetClockID(pI2C)); -} - -/* Set up bus speed for LPC_I2C interface */ -void Chip_I2CM_SetBusSpeed(LPC_I2C_T *pI2C, uint32_t busSpeed) -{ - uint32_t scl = Chip_Clock_GetSystemClockRate() / (Chip_I2C_GetClockDiv(pI2C) * busSpeed); - Chip_I2CM_SetDutyCycle(pI2C, (scl >> 1), (scl - (scl >> 1))); -} - -/* Master transfer state change handler handler */ -uint32_t Chip_I2CM_XferHandler(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer) -{ - uint32_t status = Chip_I2CM_GetStatus(pI2C); - /* Master Lost Arbitration */ - if (status & I2C_STAT_MSTRARBLOSS) { - /* Set transfer status as Arbitration Lost */ - xfer->status = I2CM_STATUS_ARBLOST; - /* Clear Status Flags */ - Chip_I2CM_ClearStatus(pI2C, I2C_STAT_MSTRARBLOSS); - } - /* Master Start Stop Error */ - else if (status & I2C_STAT_MSTSTSTPERR) { - /* Set transfer status as Bus Error */ - xfer->status = I2CM_STATUS_BUS_ERROR; - /* Clear Status Flags */ - Chip_I2CM_ClearStatus(pI2C, I2C_STAT_MSTSTSTPERR); - } - /* Master is Pending */ - else if (status & I2C_STAT_MSTPENDING) { - /* Branch based on Master State Code */ - switch (Chip_I2CM_GetMasterState(pI2C)) { - /* Master idle */ - case I2C_STAT_MSTCODE_IDLE: - /* Do Nothing */ - break; - - /* Receive data is available */ - case I2C_STAT_MSTCODE_RXREADY: - /* Read Data */ - *xfer->rxBuff++ = pI2C->MSTDAT; - xfer->rxSz--; - if (xfer->rxSz) { - /* Set Continue if there is more data to read */ - Chip_I2CM_MasterContinue(pI2C); - } - else { - /* Set transfer status as OK */ - xfer->status = I2CM_STATUS_OK; - /* No data to read send Stop */ - Chip_I2CM_SendStop(pI2C); - } - break; - - /* Master Transmit available */ - case I2C_STAT_MSTCODE_TXREADY: - if (xfer->txSz) { - /* If Tx data available transmit data and continue */ - pI2C->MSTDAT = *xfer->txBuff++; - xfer->txSz--; - Chip_I2CM_MasterContinue(pI2C); - } - else { - /* If receive queued after transmit then initiate master receive transfer*/ - if (xfer->rxSz) { - /* Write Address and RW bit to data register */ - Chip_I2CM_WriteByte(pI2C, (xfer->slaveAddr << 1) | 0x1); - /* Enter to Master Transmitter mode */ - Chip_I2CM_SendStart(pI2C); - } - else { - /* If no receive queued then set transfer status as OK */ - xfer->status = I2CM_STATUS_OK; - /* Send Stop */ - Chip_I2CM_SendStop(pI2C); - } - } - break; - - case I2C_STAT_MSTCODE_NACKADR: - /* Set transfer status as NACK on address */ - xfer->status = I2CM_STATUS_NAK_ADR; - Chip_I2CM_SendStop(pI2C); - break; - - case I2C_STAT_MSTCODE_NACKDAT: - /* Set transfer status as NACK on data */ - xfer->status = I2CM_STATUS_NAK_DAT; - Chip_I2CM_SendStop(pI2C); - break; - - default: - /* Default case should not occur*/ - xfer->status = I2CM_STATUS_ERROR; - break; - } - } - else { - /* Default case should not occur */ - xfer->status = I2CM_STATUS_ERROR; - } - return xfer->status != I2CM_STATUS_BUSY; -} - -/* Transmit and Receive data in master mode */ -void Chip_I2CM_Xfer(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer) -{ - /* set the transfer status as busy */ - xfer->status = I2CM_STATUS_BUSY; - /* Clear controller state. */ - Chip_I2CM_ClearStatus(pI2C, I2C_STAT_MSTRARBLOSS | I2C_STAT_MSTSTSTPERR); - /* Write Address and RW bit to data register */ - Chip_I2CM_WriteByte(pI2C, (xfer->slaveAddr << 1) | (xfer->txSz == 0)); - /* Enter to Master Transmitter mode */ - Chip_I2CM_SendStart(pI2C); -} - -/* Transmit and Receive data in master mode */ -uint32_t Chip_I2CM_XferBlocking(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer) -{ - uint32_t ret = 0; - /* start transfer */ - Chip_I2CM_Xfer(pI2C, xfer); - - while (ret == 0) { - /* wait for status change interrupt */ - while (!Chip_I2CM_IsMasterPending(pI2C)) {} - /* call state change handler */ - ret = Chip_I2CM_XferHandler(pI2C, xfer); - } - return ret; -} - -/* Slave transfer state change handler */ -uint32_t Chip_I2CS_XferHandler(LPC_I2C_T *pI2C, const I2CS_XFER_T *xfers) -{ - uint32_t done = 0; - - uint8_t data; - uint32_t state; - - /* transfer complete? */ - if ((Chip_I2C_GetPendingInt(pI2C) & I2C_INTENSET_SLVDESEL) != 0) { - Chip_I2CS_ClearStatus(pI2C, I2C_STAT_SLVDESEL); - xfers->slaveDone(); - } - else { - /* Determine the current I2C slave state */ - state = Chip_I2CS_GetSlaveState(pI2C); - - switch (state) { - case I2C_STAT_SLVCODE_ADDR: /* Slave address received */ - /* Get slave address that needs servicing */ - data = Chip_I2CS_GetSlaveAddr(pI2C, Chip_I2CS_GetSlaveMatchIndex(pI2C)); - - /* Call address callback */ - xfers->slaveStart(data); - break; - - case I2C_STAT_SLVCODE_RX: /* Data byte received */ - /* Get received data */ - data = Chip_I2CS_ReadByte(pI2C); - done = xfers->slaveRecv(data); - break; - - case I2C_STAT_SLVCODE_TX: /* Get byte that needs to be sent */ - /* Get data to send */ - done = xfers->slaveSend(&data); - Chip_I2CS_WriteByte(pI2C, data); - break; - } - } - - if (done == 0) { - Chip_I2CS_SlaveContinue(pI2C); - } - else { - Chip_I2CS_SlaveNACK(pI2C); - } - - return done; -} diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/i2c/i2c_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/i2c/i2c_8xx.h deleted file mode 100644 index 6b51c7639f5..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/i2c/i2c_8xx.h +++ /dev/null @@ -1,890 +0,0 @@ -/* - * @brief LPC15xx I2C driver - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __I2C_COMMON_8XX_H_ -#define __I2C_COMMON_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup I2C_15XX CHIP: LPC15xx I2C driver - * @ingroup CHIP_15XX_Drivers - * @{ - */ - -/** - * @brief I2C register block structure - */ -typedef struct { /* I2C0 Structure */ - __IO uint32_t CFG; /*!< I2C Configuration Register common for Master, Slave and Monitor */ - __IO uint32_t STAT; /*!< I2C Status Register common for Master, Slave and Monitor */ - __IO uint32_t INTENSET; /*!< I2C Interrupt Enable Set Register common for Master, Slave and Monitor */ - __O uint32_t INTENCLR; /*!< I2C Interrupt Enable Clear Register common for Master, Slave and Monitor */ - __IO uint32_t TIMEOUT; /*!< I2C Timeout value Register */ - __IO uint32_t CLKDIV; /*!< I2C Clock Divider Register */ - __I uint32_t INTSTAT; /*!< I2C Interrupt Status Register */ - __I uint32_t RESERVED0; - __IO uint32_t MSTCTL; /*!< I2C Master Control Register */ - __IO uint32_t MSTTIME; /*!< I2C Master Time Register for SCL */ - __IO uint32_t MSTDAT; /*!< I2C Master Data Register */ - __I uint32_t RESERVED1[5]; - __IO uint32_t SLVCTL; /*!< I2C Slave Control Register */ - __IO uint32_t SLVDAT; /*!< I2C Slave Data Register */ - __IO uint32_t SLVADR[4]; /*!< I2C Slave Address Registers */ - __IO uint32_t SLVQUAL0; /*!< I2C Slave Address Qualifier 0 Register */ - __I uint32_t RESERVED2[9]; - __I uint32_t MONRXDAT; /*!< I2C Monitor Data Register */ -} LPC_I2C_T; - -/* Reserved bits masks for registers */ -#define I2C_CFG_RESERVED (~0x1f) -#define I2C_STAT_RESERVED ((1<<5)|(1<<7)|(0xf<<20)|(0x3fu<<26)) -#define I2C_INTENSET_RESERVED ((7<<1)|(1<<5)|(1<<7)|(3<<9)|(7<<12)|(1<<18)|(0xf<<20)|(0x3fu<<26)) -#define I2C_INTENCLR_RESERVED ((7<<1)|(1<<5)|(1<<7)|(3<<9)|(7<<12)|(1<<18)|(0xf<<20)|(0x3fu<<26)) -#define I2C_TIMEOUT_RESERVED 0xffff0000 -#define I2C_CLKDIV_RESERVED 0xffff0000 -#define I2C_INTSTAT_RESERVED ((7<<1)|(1<<5)|(1<<7)|(3<<9)|(7<<12)|(1<<18)|(0xf<<20)|(0x3fu<<26)) -#define I2C_MSTCTL_RESERVED (~7) -#define I2C_MSTTIME_RESERVED (~0x7f) -#define I2C_MSTDAT_RESERVED (~0xff) -#define I2C_SLVCTL_RESERVED (~3) -#define I2C_SLVDAT_RESERVED (~0xff) -#define I2C_SLVADR_RESERVED (~0xff) -#define I2C_SLVQUAL0_RESERVED (~0xff) - -/* - * @brief I2C Configuration register Bit definition - */ -#define I2C_CFG_MSTEN (1 << 0) /*!< Master Enable/Disable Bit */ -#define I2C_CFG_SLVEN (1 << 1) /*!< Slave Enable/Disable Bit */ -#define I2C_CFG_MONEN (1 << 2) /*!< Monitor Enable/Disable Bit */ -#define I2C_CFG_TIMEOUTEN (1 << 3) /*!< Timeout Enable/Disable Bit */ -#define I2C_CFG_MONCLKSTR (1 << 4) /*!< Monitor Clock Stretching Bit */ -#define I2C_CFG_MASK ((uint32_t) 0x1F) /*!< Configuration register Mask */ - -/* - * @brief I2C Status register Bit definition - */ -#define I2C_STAT_MSTPENDING (1 << 0) /*!< Master Pending Status Bit */ -#define I2C_STAT_MSTSTATE (0x7 << 1) /*!< Master State Code */ -#define I2C_STAT_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Bit */ -#define I2C_STAT_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Bit */ -#define I2C_STAT_SLVPENDING (1 << 8) /*!< Slave Pending Status Bit */ -#define I2C_STAT_SLVSTATE (0x3 << 9) /*!< Slave State Code */ -#define I2C_STAT_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Bit */ -#define I2C_STAT_SLVIDX (0x3 << 12) /*!< Slave Address Index */ -#define I2C_STAT_SLVSEL (1 << 14) /*!< Slave Selected Bit */ -#define I2C_STAT_SLVDESEL (1 << 15) /*!< Slave Deselect Bit */ -#define I2C_STAT_MONRDY (1 << 16) /*!< Monitor Ready Bit */ -#define I2C_STAT_MONOV (1 << 17) /*!< Monitor Overflow Flag */ -#define I2C_STAT_MONACTIVE (1 << 18) /*!< Monitor Active Flag */ -#define I2C_STAT_MONIDLE (1 << 19) /*!< Monitor Idle Flag */ -#define I2C_STAT_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Flag */ -#define I2C_STAT_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Flag */ - -#define I2C_STAT_MSTCODE_IDLE (0) /*!< Master Idle State Code */ -#define I2C_STAT_MSTCODE_RXREADY (1) /*!< Master Receive Ready State Code */ -#define I2C_STAT_MSTCODE_TXREADY (2) /*!< Master Transmit Ready State Code */ -#define I2C_STAT_MSTCODE_NACKADR (3) /*!< Master NACK by slave on address State Code */ -#define I2C_STAT_MSTCODE_NACKDAT (4) /*!< Master NACK by slave on data State Code */ - -#define I2C_STAT_SLVCODE_ADDR (0) /*!< Master Idle State Code */ -#define I2C_STAT_SLVCODE_RX (1) /*!< Received data is available Code */ -#define I2C_STAT_SLVCODE_TX (2) /*!< Data can be transmitted Code */ - -/* - * @brief I2C Interrupt Enable Set register Bit definition - */ -#define I2C_INTENSET_MSTPENDING (1 << 0) /*!< Master Pending Interrupt Enable Bit */ -#define I2C_INTENSET_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Interrupt Enable Bit */ -#define I2C_INTENSET_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Interrupt Enable Bit */ -#define I2C_INTENSET_SLVPENDING (1 << 8) /*!< Slave Pending Interrupt Enable Bit */ -#define I2C_INTENSET_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Interrupt Enable Bit */ -#define I2C_INTENSET_SLVDESEL (1 << 15) /*!< Slave Deselect Interrupt Enable Bit */ -#define I2C_INTENSET_MONRDY (1 << 16) /*!< Monitor Ready Interrupt Enable Bit */ -#define I2C_INTENSET_MONOV (1 << 17) /*!< Monitor Overflow Interrupt Enable Bit */ -#define I2C_INTENSET_MONIDLE (1 << 19) /*!< Monitor Idle Interrupt Enable Bit */ -#define I2C_INTENSET_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Enable Bit */ -#define I2C_INTENSET_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Enable Bit */ - -/* - * @brief I2C Interrupt Enable Clear register Bit definition - */ -#define I2C_INTENCLR_MSTPENDING (1 << 0) /*!< Master Pending Interrupt Clear Bit */ -#define I2C_INTENCLR_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Interrupt Clear Bit */ -#define I2C_INTENCLR_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Interrupt Clear Bit */ -#define I2C_INTENCLR_SLVPENDING (1 << 8) /*!< Slave Pending Interrupt Clear Bit */ -#define I2C_INTENCLR_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Interrupt Clear Bit */ -#define I2C_INTENCLR_SLVDESEL (1 << 15) /*!< Slave Deselect Interrupt Clear Bit */ -#define I2C_INTENCLR_MONRDY (1 << 16) /*!< Monitor Ready Interrupt Clear Bit */ -#define I2C_INTENCLR_MONOV (1 << 17) /*!< Monitor Overflow Interrupt Clear Bit */ -#define I2C_INTENCLR_MONIDLE (1 << 19) /*!< Monitor Idle Interrupt Clear Bit */ -#define I2C_INTENCLR_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Clear Bit */ -#define I2C_INTENCLR_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Clear Bit */ - -/* - * @brief I2C TimeOut Value Macro - */ -#define I2C_TIMEOUT_VAL(n) (((uint32_t) ((n) - 1) & 0xFFF0) | 0x000F) /*!< Macro for Timeout value register */ - -/* - * @brief I2C Interrupt Status register Bit definition - */ -#define I2C_INTSTAT_MSTPENDING (1 << 0) /*!< Master Pending Interrupt Status Bit */ -#define I2C_INTSTAT_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Interrupt Status Bit */ -#define I2C_INTSTAT_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Interrupt Status Bit */ -#define I2C_INTSTAT_SLVPENDING (1 << 8) /*!< Slave Pending Interrupt Status Bit */ -#define I2C_INTSTAT_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Interrupt Status Bit */ -#define I2C_INTSTAT_SLVDESEL (1 << 15) /*!< Slave Deselect Interrupt Status Bit */ -#define I2C_INTSTAT_MONRDY (1 << 16) /*!< Monitor Ready Interrupt Status Bit */ -#define I2C_INTSTAT_MONOV (1 << 17) /*!< Monitor Overflow Interrupt Status Bit */ -#define I2C_INTSTAT_MONIDLE (1 << 19) /*!< Monitor Idle Interrupt Status Bit */ -#define I2C_INTSTAT_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Status Bit */ -#define I2C_INTSTAT_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Status Bit */ - -/* - * @brief I2C Master Control register Bit definition - */ -#define I2C_MSTCTL_MSTCONTINUE (1 << 0) /*!< Master Continue Bit */ -#define I2C_MSTCTL_MSTSTART (1 << 1) /*!< Master Start Control Bit */ -#define I2C_MSTCTL_MSTSTOP (1 << 2) /*!< Master Stop Control Bit */ -#define I2C_MSTCTL_MSTDMA (1 << 3) /*!< Master DMA Enable Bit */ - -/* - * @brief I2C Master Time Register Field definition - */ -#define I2C_MSTTIME_MSTSCLLOW (0x07 << 0) /*!< Master SCL Low Time field */ -#define I2C_MSTTIME_MSTSCLHIGH (0x07 << 4) /*!< Master SCL High Time field */ - -/* - * @brief I2C Master Data Mask - */ -#define I2C_MSTDAT_DATAMASK ((uint32_t) 0x00FF << 0) /*!< Master data mask */ - -/* - * @brief I2C Slave Control register Bit definition - */ -#define I2C_SLVCTL_SLVCONTINUE (1 << 0) /*!< Slave Continue Bit */ -#define I2C_SLVCTL_SLVNACK (1 << 1) /*!< Slave NACK Bit */ -#define I2C_SLVCTL_SLVDMA (1 << 3) /*!< Slave DMA Enable Bit */ - -/* - * @brief I2C Slave Data Mask - */ -#define I2C_SLVDAT_DATAMASK ((uint32_t) 0x00FF << 0) /*!< Slave data mask */ - -/* - * @brief I2C Slave Address register Bit definition - */ -#define I2C_SLVADR_SADISABLE (1 << 0) /*!< Slave Address n Disable Bit */ -#define I2C_SLVADR_SLVADR (0x7F << 1) /*!< Slave Address field */ -#define I2C_SLVADR_MASK ((uint32_t) 0x00FF) /*!< Slave Address Mask */ - -/* - * @brief I2C Slave Address Qualifier 0 Register Bit definition - */ -#define I2C_SLVQUAL_QUALMODE0 (1 << 0) /*!< Slave Qualifier Mode Enable Bit */ -#define I2C_SLVQUAL_SLVQUAL0 (0x7F << 1) /*!< Slave Qualifier Address for Address 0 */ - -/* - * @brief I2C Monitor Data Register Bit definition - */ -#define I2C_MONRXDAT_DATA (0xFF << 0) /*!< Monitor Function Receive Data Field */ -#define I2C_MONRXDAT_MONSTART (1 << 8) /*!< Monitor Received Start Bit */ -#define I2C_MONRXDAT_MONRESTART (1 << 9) /*!< Monitor Received Repeated Start Bit */ -#define I2C_MONRXDAT_MONNACK (1 << 10) /*!< Monitor Received Nack Bit */ - -/** - * @brief Initialize I2C Interface - * @param pI2C : Pointer to selected I2C peripheral - * @return Nothing - * @note This function enables the I2C clock for both the master and - * slave interfaces of the given I2C peripheral. LPC_I2C1, LPC_I2C2 and - * LPC_I2C3 are available only on LPC82X devices. - */ -void Chip_I2C_Init(LPC_I2C_T *pI2C); - -/** - * @brief Shutdown I2C Interface - * @param pI2C : Pointer to selected I2C peripheral - * @return Nothing - * @note This function disables the I2C clock for both the master and - * slave interfaces of the given I2C peripheral. Only LPC_I2C0 is available - * on LPC81X devices. - */ -void Chip_I2C_DeInit(LPC_I2C_T *pI2C); - -/** - * @brief Sets I2C Clock Divider registers - * @param pI2C : Pointer to selected I2C peripheral - * @param clkdiv : Clock Divider value for I2C, value is between (1 - 65536) - * @return Nothing - * @note The clock to I2C block is determined by the following formula (I2C_PCLK - * is the frequency of the system clock):
- * I2C Clock Frequency = (I2C_PCLK)/clkdiv; - */ -static INLINE void Chip_I2C_SetClockDiv(LPC_I2C_T *pI2C, uint32_t clkdiv) -{ - if ((clkdiv >= 1) && (clkdiv <= 65536)) { - pI2C->CLKDIV = clkdiv - 1; - } - else { - pI2C->CLKDIV = 0; - } -} - -/** - * @brief Get I2C Clock Divider registers - * @param pI2C : Pointer to selected I2C peripheral - * @return Clock Divider value - * @note Return the divider value for the I2C block - * It is the CLKDIV register value + 1 - */ -static INLINE uint32_t Chip_I2C_GetClockDiv(LPC_I2C_T *pI2C) -{ - return (pI2C->CLKDIV & 0xFFFF) + 1; -} - -/** - * @brief Enable I2C Interrupts - * @param pI2C : Pointer to selected I2C peripheral - * @param intEn : ORed Value of I2C_INTENSET_* values to enable - * @return Nothing - */ -static INLINE void Chip_I2C_EnableInt(LPC_I2C_T *pI2C, uint32_t intEn) -{ - pI2C->INTENSET = intEn; -} - -/** - * @brief Disable I2C Interrupts - * @param pI2C : Pointer to selected I2C peripheral - * @param intClr : ORed Value of I2C_INTENSET_* values to disable - * @return Nothing - */ -static INLINE void Chip_I2C_DisableInt(LPC_I2C_T *pI2C, uint32_t intClr) -{ - pI2C->INTENCLR = intClr; -} - -/** - * @brief Disable I2C Interrupts - * @param pI2C : Pointer to selected I2C peripheral - * @param intClr : ORed Value of I2C_INTENSET_* values to disable - * @return Nothing - * @note It is recommended to use the Chip_I2C_DisableInt() function - * instead of this function. - */ -static INLINE void Chip_I2C_ClearInt(LPC_I2C_T *pI2C, uint32_t intClr) -{ - Chip_I2C_DisableInt(pI2C, intClr); -} - -/** - * @brief Returns pending I2C Interrupts - * @param pI2C : Pointer to selected I2C peripheral - * @return All pending interrupts, mask with I2C_INTENSET_* to determine specific interrupts - */ -static INLINE uint32_t Chip_I2C_GetPendingInt(LPC_I2C_T *pI2C) -{ - return pI2C->INTSTAT & ~I2C_INTSTAT_RESERVED; -} - -/** - * @} - */ - - -/** @defgroup I2CM_8XX CHIP: LPC8XX I2C master-only driver - * @ingroup I2C_8XX - * This driver only works in master mode. To describe the I2C transactions - * following symbols are used in driver documentation. - * - * Key to symbols - * ============== - * S (1 bit) : Start bit - * P (1 bit) : Stop bit - * Rd/Wr (1 bit) : Read/Write bit. Rd equals 1, Wr equals 0. - * A, NA (1 bit) : Acknowledge and Not-Acknowledge bit. - * Addr (7 bits): I2C 7 bit address. Note that this can be expanded as usual to - * get a 10 bit I2C address. - * Data (8 bits): A plain data byte. Sometimes, I write DataLow, DataHigh - * for 16 bit data. - * [..]: Data sent by I2C device, as opposed to data sent by the host adapter. - * @{ - */ - -/** I2CM_8XX_STATUS_TYPES I2C master transfer status types - * @{ - */ - -#define I2CM_STATUS_OK 0x00 /*!< Requested Request was executed successfully. */ -#define I2CM_STATUS_ERROR 0x01 /*!< Unknown error condition. */ -#define I2CM_STATUS_NAK_ADR 0x02 /*!< No acknowledgement received from slave during address phase. */ -#define I2CM_STATUS_BUS_ERROR 0x03 /*!< I2C bus error */ -#define I2CM_STATUS_NAK_DAT 0x04 /*!< No acknowledgement received from slave during address phase. */ -#define I2CM_STATUS_ARBLOST 0x05 /*!< Arbitration lost. */ -#define I2CM_STATUS_BUSY 0xFF /*!< I2C transmistter is busy. */ - -/** - * @} - */ - -/** - * @brief Master transfer data structure definitions - */ -typedef struct { - const uint8_t *txBuff; /*!< Pointer to array of bytes to be transmitted */ - uint8_t *rxBuff; /*!< Pointer memory where bytes received from I2C be stored */ - uint16_t txSz; /*!< Number of bytes in transmit array, - if 0 only receive transfer will be carried on */ - uint16_t rxSz; /*!< Number of bytes to received, - if 0 only transmission we be carried on */ - uint16_t status; /*!< Status of the current I2C transfer */ - uint8_t slaveAddr; /*!< 7-bit I2C Slave address */ -} I2CM_XFER_T; - -/** - * @brief Set up bus speed for LPC_I2C controller - * @param pI2C : Pointer to selected I2C peripheral - * @param busSpeed : I2C bus clock rate - * @return Nothing - * @note Per I2C specification the busSpeed should be - * @li 100000 for Standard mode - * @li 400000 for Fast mode - * @li 1000000 for Fast mode plus - * IOCON registers corresponding to I2C pads should be updated - * according to the bus mode. - */ -void Chip_I2CM_SetBusSpeed(LPC_I2C_T *pI2C, uint32_t busSpeed); - -/** - * @brief Enable I2C Master interface - * @param pI2C : Pointer to selected I2C peripheral - * @return Nothing - * @note - */ -static INLINE void Chip_I2CM_Enable(LPC_I2C_T *pI2C) -{ - pI2C->CFG = (pI2C->CFG & I2C_CFG_MASK) | I2C_CFG_MSTEN; -} - -/** - * @brief Disable I2C Master interface - * @param pI2C : Pointer to selected I2C peripheral - * @return Nothing - * @note - */ -static INLINE void Chip_I2CM_Disable(LPC_I2C_T *pI2C) -{ - pI2C->CFG = (pI2C->CFG & I2C_CFG_MASK) & ~I2C_CFG_MSTEN; -} - -/** - * @brief Get I2C Status - * @param pI2C : Pointer to selected I2C peripheral - * @return I2C Status register value - * @note This function returns the value of the status register. - */ -static INLINE uint32_t Chip_I2CM_GetStatus(LPC_I2C_T *pI2C) -{ - return pI2C->STAT & ~I2C_STAT_RESERVED; -} - -/** - * @brief Clear I2C status bits (master) - * @param pI2C : Pointer to selected I2C peripheral - * @param clrStatus : Status bit to clear, ORed Value of I2C_STAT_MSTRARBLOSS and I2C_STAT_MSTSTSTPERR - * @return Nothing - * @note This function clears selected status flags. - */ -static INLINE void Chip_I2CM_ClearStatus(LPC_I2C_T *pI2C, uint32_t clrStatus) -{ - /* Clear Master Arbitration Loss and Start, Stop Error */ - pI2C->STAT = clrStatus & (I2C_STAT_MSTRARBLOSS | I2C_STAT_MSTSTSTPERR); -} - -/** - * @brief Check if I2C Master is pending - * @param pI2C : Pointer to selected I2C peripheral - * @return Returns TRUE if the Master is pending else returns FALSE - * @note - */ -static INLINE bool Chip_I2CM_IsMasterPending(LPC_I2C_T *pI2C) -{ - return (pI2C->STAT & I2C_STAT_MSTPENDING) != 0; -} - -/** - * @brief Get current state of the I2C Master - * @param pI2C : Pointer to selected I2C peripheral - * @return Master State Code, a value in the range of 0 - 4 - * @note After the Master is pending this state code tells the reason - * for Master pending. - */ -static INLINE uint32_t Chip_I2CM_GetMasterState(LPC_I2C_T *pI2C) -{ - return (pI2C->STAT & I2C_STAT_MSTSTATE) >> 1; -} - -/** - * @brief Transmit START or Repeat-START signal on I2C bus - * @param pI2C : Pointer to selected I2C peripheral - * @return Nothing - * @note This function sets the controller to transmit START condition when - * the bus becomes free. This should be called only when master is pending. - * The function writes a complete value to Master Control register, ORing is not advised. - */ -static INLINE void Chip_I2CM_SendStart(LPC_I2C_T *pI2C) -{ - pI2C->MSTCTL = I2C_MSTCTL_MSTSTART; -} - -/** - * @brief Transmit STOP signal on I2C bus - * @param pI2C : Pointer to selected I2C peripheral - * @return Nothing - * @note This function sets the controller to transmit STOP condition. - * This should be called only when master is pending. The function writes a - * complete value to Master Control register, ORing is not advised. - */ -static INLINE void Chip_I2CM_SendStop(LPC_I2C_T *pI2C) -{ - pI2C->MSTCTL = I2C_MSTCTL_MSTSTOP; -} - -/** - * @brief Master Continue transfer operation - * @param pI2C : Pointer to selected I2C peripheral - * @return Nothing - * @note This function sets the master controller to continue transmission. - * This should be called only when master is pending. The function writes a - * complete value to Master Control register, ORing is not advised. - */ -static INLINE void Chip_I2CM_MasterContinue(LPC_I2C_T *pI2C) -{ - pI2C->MSTCTL = I2C_MSTCTL_MSTCONTINUE; -} - -/** - * @brief Transmit a single data byte through the I2C peripheral (master) - * @param pI2C : Pointer to selected I2C peripheral - * @param data : Byte to transmit - * @return Nothing - * @note This function attempts to place a byte into the I2C Master - * Data Register - * - */ -static INLINE void Chip_I2CM_WriteByte(LPC_I2C_T *pI2C, uint8_t data) -{ - pI2C->MSTDAT = (uint32_t) data; -} - -/** - * @brief Read a single byte data from the I2C peripheral (master) - * @param pI2C : Pointer to selected I2C peripheral - * @return A single byte of data read - * @note This function reads a byte from the I2C receive hold register - * regardless of I2C state. - */ -static INLINE uint8_t Chip_I2CM_ReadByte(LPC_I2C_T *pI2C) -{ - return (uint8_t) (pI2C->MSTDAT & I2C_MSTDAT_DATAMASK); -} - -/** - * @brief Transfer state change handler - * @param pI2C : Pointer to selected I2C peripheral - * @param xfer : Pointer to a I2CM_XFER_T structure see notes below - * @return Returns non-zero value on completion of transfer. The @a status - * member of @a xfer structure contains the current status of the - * transfer at the end of the call. - * @note - * The parameter @a xfer should be same as the one passed to Chip_I2CM_Xfer() - * routine. This function should be called from the I2C interrupt handler - * only when a master interrupt occurs. - */ -uint32_t Chip_I2CM_XferHandler(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer); - -/** - * @brief Transmit and Receive data in master mode - * @param pI2C : Pointer to selected I2C peripheral - * @param xfer : Pointer to a I2CM_XFER_T structure see notes below - * @return Nothing - * @note - * The parameter @a xfer should have its member @a slaveAddr initialized - * to the 7-Bit slave address to which the master will do the xfer, Bit0 - * to bit6 should have the address and Bit8 is ignored. During the transfer - * no code (like event handler) must change the content of the memory - * pointed to by @a xfer. The member of @a xfer, @a txBuff and @a txSz be - * initialized to the memory from which the I2C must pick the data to be - * transfered to slave and the number of bytes to send respectively, similarly - * @a rxBuff and @a rxSz must have pointer to memory where data received - * from slave be stored and the number of data to get from slave respectilvely. - * Following types of transfers are possible: - * - Write-only transfer: When @a rxSz member of @a xfer is set to 0. - * - * S Addr Wr [A] txBuff0 [A] txBuff1 [A] ... txBuffN [A] P - * - * - If I2CM_XFER_OPTION_IGNORE_NACK is set in @a options memeber - * - * S Addr Wr [A] txBuff0 [A or NA] ... txBuffN [A or NA] P - * - * - Read-only transfer: When @a txSz member of @a xfer is set to 0. - * - * S Addr Rd [A] [rxBuff0] A [rxBuff1] A ... [rxBuffN] NA P - * - * - If I2CM_XFER_OPTION_LAST_RX_ACK is set in @a options memeber - * - * S Addr Rd [A] [rxBuff0] A [rxBuff1] A ... [rxBuffN] A P - * - * - Read-Write transfer: When @a rxSz and @ txSz members of @a xfer are non-zero. - * - * S Addr Wr [A] txBuff0 [A] txBuff1 [A] ... txBuffN [A] - * S Addr Rd [A] [rxBuff0] A [rxBuff1] A ... [rxBuffN] NA P - * - */ -void Chip_I2CM_Xfer(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer); - -/** - * @brief Transmit and Receive data in master mode - * @param pI2C : Pointer to selected I2C peripheral - * @param xfer : Pointer to a I2CM_XFER_T structure see notes below - * @return Returns non-zero value on succesful completion of transfer. - * @note - * This function operates same as Chip_I2CM_Xfer(), but is a blocking call. - */ -uint32_t Chip_I2CM_XferBlocking(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer); - -/** - * @} - */ - - -/** @defgroup I2CS_8XX CHIP: LPC8XX I2C slave-only driver - * @ingroup I2C_8XX - * This driver only works in slave mode. - * @{ - */ - -/** @brief I2C slave service start callback - * This callback is called from the I2C slave handler when an I2C slave address is - * received and needs servicing. It's used to indicate the start of a slave transfer - * that will happen on the slave bus. - */ -typedef void (*I2CSlaveXferStart)(uint8_t addr); - -/** @brief I2C slave send data callback - * This callback is called from the I2C slave handler when an I2C slave address needs - * data to send. Return 0 to NACK the master and terminate the transfer, or return - * a non-0 value with the value to send in *data. - */ -typedef uint8_t (*I2CSlaveXferSend)(uint8_t *data); - -/** @brief I2C slave receive data callback - * This callback is called from the I2C slave handler when an I2C slave address has - * receive data. Return 0 to NACK the master and terminate the transfer, or return - * a non-0 value to continue the transfer. - */ -typedef uint8_t (*I2CSlaveXferRecv)(uint8_t data); - -/** @brief I2C slave service done callback - * This callback is called from the I2C slave handler when an I2C slave transfer is - * completed. It's used to indicate the end of a slave transfer. - */ -typedef void (*I2CSlaveXferDone)(void); - -/** - * Slave transfer are performed using 3 callbacks. These 3 callbacks handle most I2C - * slave transfer cases. When the slave is setup and a slave interrupt is receive - * and processed with the Chip_I2CS_XferHandler() function in the I2C interrupt handler, - * one of these 3 callbacks is called. The callbacks can be used for unsized transfers - * from the master. - * - * When an address is received, the SlaveXferAddr() callback is called with the - * received address. Only addresses enabled in the slave controller will be handled. - * The slave controller can support up to 4 slave addresses. - * - * If the master is going to perform a read operation, the SlaveXferSend() callback - * is called. Place the data byte to send in *data and return a non-0 value to the - * caller, or return 0 to NACK the master. (Note the master ACKS/NACKS to slave - * on reads, so this won't necessarily stop the slave transfer.)
- * - * If the master performs a write operation, the SlaveXferRecv() callback is called - * with the received data. Return a non-0 value to the caller, or return 0 to NACK - * the master.
- * - * Once the transfer completes, the SlaveXferDone() callback will be called.
- */ -typedef struct { - I2CSlaveXferStart slaveStart; /*!< Called when an matching I2C slave address is received */ - I2CSlaveXferSend slaveSend; /*!< Called when a byte is needed to send to master */ - I2CSlaveXferRecv slaveRecv; /*!< Called when a byte is received from master */ - I2CSlaveXferDone slaveDone; /*!< Called when a slave transfer is complete */ -} I2CS_XFER_T; - -/** - * @brief Enable I2C slave interface - * @param pI2C : Pointer to selected I2C peripheral - * @return Nothing - * @note Do not call this function until the slave interface is fully configured. - */ -STATIC INLINE void Chip_I2CS_Enable(LPC_I2C_T *pI2C) -{ - pI2C->CFG = (pI2C->CFG & I2C_CFG_MASK) | I2C_CFG_SLVEN; -} - -/** - * @brief Disable I2C slave interface - * @param pI2C : Pointer to selected I2C peripheral - * @return Nothing - */ -STATIC INLINE void Chip_I2CS_Disable(LPC_I2C_T *pI2C) -{ - pI2C->CFG = (pI2C->CFG & I2C_CFG_MASK) & ~I2C_CFG_SLVEN; -} - -/** - * @brief Get I2C Status - * @param pI2C : Pointer to selected I2C peripheral - * @return I2C Status register value - * @note This function returns the value of the status register. - */ -STATIC INLINE uint32_t Chip_I2CS_GetStatus(LPC_I2C_T *pI2C) -{ - return pI2C->STAT & ~I2C_STAT_RESERVED; -} - -/** - * @brief Clear I2C status bits (slave) - * @param pI2C : Pointer to selected I2C peripheral - * @param clrStatus : Status bit to clear, must be I2C_STAT_SLVDESEL - * @return Nothing - * @note This function clears selected status flags. - */ -STATIC INLINE void Chip_I2CS_ClearStatus(LPC_I2C_T *pI2C, uint32_t clrStatus) -{ - pI2C->STAT = clrStatus & I2C_STAT_SLVDESEL; -} - -/** - * @brief Check if I2C slave is pending - * @param pI2C : Pointer to selected I2C peripheral - * @return Returns TRUE if the slave is pending else returns FALSE - * @note - */ -STATIC INLINE bool Chip_I2CS_IsSlavePending(LPC_I2C_T *pI2C) -{ - return (pI2C->STAT & I2C_STAT_SLVPENDING) != 0; -} - -/** - * @brief Check if I2C slave is selected - * @param pI2C : Pointer to selected I2C peripheral - * @return Returns TRUE if the slave is is selected, otherwise FALSE - * @note - */ -STATIC INLINE bool Chip_I2CS_IsSlaveSelected(LPC_I2C_T *pI2C) -{ - return (pI2C->STAT & I2C_STAT_SLVSEL) != 0; -} - -/** - * @brief Check if I2C slave is deselected - * @param pI2C : Pointer to selected I2C peripheral - * @return Returns TRUE if the slave is is deselected, otherwise FALSE - * @note - */ -STATIC INLINE bool Chip_I2CS_IsSlaveDeSelected(LPC_I2C_T *pI2C) -{ - return (pI2C->STAT & I2C_STAT_SLVDESEL) != 0; -} - -/** - * @brief Get current state of the I2C slave - * @param pI2C : Pointer to selected I2C peripheral - * @return slave State Code, a value of type I2C_STAT_SLVCODE_* - * @note After the slave is pending this state code tells the reason - * for slave pending. - */ -STATIC INLINE uint32_t Chip_I2CS_GetSlaveState(LPC_I2C_T *pI2C) -{ - return (pI2C->STAT & I2C_STAT_SLVSTATE) >> 9; -} - -/** - * @brief Returns the current slave address match index - * @param pI2C : Pointer to selected I2C peripheral - * @return slave match index, 0 - 3 - */ -STATIC INLINE uint32_t Chip_I2CS_GetSlaveMatchIndex(LPC_I2C_T *pI2C) -{ - return (pI2C->STAT & I2C_STAT_SLVIDX) >> 12; -} - -/** - * @brief Slave Continue transfer operation (ACK) - * @param pI2C : Pointer to selected I2C peripheral - * @return Nothing - * @note This function sets the slave controller to continue transmission. - * This should be called only when slave is pending. The function writes a - * complete value to slave Control register, ORing is not advised. - */ -STATIC INLINE void Chip_I2CS_SlaveContinue(LPC_I2C_T *pI2C) -{ - pI2C->SLVCTL = I2C_SLVCTL_SLVCONTINUE; -} - -/** - * @brief Slave NACK operation - * @param pI2C : Pointer to selected I2C peripheral - * @return Nothing - * @note This function sets the slave controller to NAK the master. - */ -STATIC INLINE void Chip_I2CS_SlaveNACK(LPC_I2C_T *pI2C) -{ - pI2C->SLVCTL = I2C_SLVCTL_SLVNACK; -} - -/** - * @brief Transmit a single data byte through the I2C peripheral (slave) - * @param pI2C : Pointer to selected I2C peripheral - * @param data : Byte to transmit - * @return Nothing - * @note This function attempts to place a byte into the I2C slave - * Data Register - * - */ -STATIC INLINE void Chip_I2CS_WriteByte(LPC_I2C_T *pI2C, uint8_t data) -{ - pI2C->SLVDAT = (uint32_t) data; -} - -/** - * @brief Read a single byte data from the I2C peripheral (slave) - * @param pI2C : Pointer to selected I2C peripheral - * @return A single byte of data read - * @note This function reads a byte from the I2C receive hold register - * regardless of I2C state. - */ -STATIC INLINE uint8_t Chip_I2CS_ReadByte(LPC_I2C_T *pI2C) -{ - return (uint8_t) (pI2C->SLVDAT & I2C_SLVDAT_DATAMASK); -} - -/** - * @brief Set a I2C slave address for slave operation - * @param pI2C : Pointer to selected I2C peripheral - * @param slvNum : Possible slave address number, between 0 - 3 - * @param slvAddr : Slave Address for the index (7-bits, bit 7 = 0) - * @return Nothing - * @note Setting a slave address also enables the slave address. Do - * not 'pre-shift' the slave address. - */ -STATIC INLINE void Chip_I2CS_SetSlaveAddr(LPC_I2C_T *pI2C, uint8_t slvNum, uint8_t slvAddr) -{ - pI2C->SLVADR[slvNum] = (uint32_t) (slvAddr << 1); -} - -/** - * @brief Return a I2C programmed slave address - * @param pI2C : Pointer to selected I2C peripheral - * @param slvNum : Possible slave address number, between 0 - 3 - * @return Nothing - */ -STATIC INLINE uint8_t Chip_I2CS_GetSlaveAddr(LPC_I2C_T *pI2C, uint8_t slvNum) -{ - return (pI2C->SLVADR[slvNum] >> 1) & 0x7F; -} - -/** - * @brief Enable a I2C address - * @param pI2C : Pointer to selected I2C peripheral - * @param slvNum : Possible slave address number, between 0 - 3 - * @return Nothing - */ -STATIC INLINE void Chip_I2CS_EnableSlaveAddr(LPC_I2C_T *pI2C, uint8_t slvNum) -{ - pI2C->SLVADR[slvNum] = (pI2C->SLVADR[slvNum] & I2C_SLVADR_MASK) & ~I2C_SLVADR_SADISABLE; -} - -/** - * @brief Disable a I2C address - * @param pI2C : Pointer to selected I2C peripheral - * @param slvNum : Possible slave address number, between 0 - 3 - * @return Nothing - */ -STATIC INLINE void Chip_I2CS_DisableSlaveAddr(LPC_I2C_T *pI2C, uint8_t slvNum) -{ - pI2C->SLVADR[slvNum] = (pI2C->SLVADR[slvNum] & I2C_SLVADR_MASK) | I2C_SLVADR_SADISABLE; -} - -/** - * @brief Setup slave qialifier address - * @param pI2C : Pointer to selected I2C peripheral - * @param extend : true to extend I2C slave detect address 0 range, or false to match to corresponding bits - * @param slvNum : Slave address qualifier, see SLVQUAL0 register in User Manual - * @return Nothing - * @note Do not 'pre-shift' the slave address. - */ -STATIC INLINE void Chip_I2CS_SetSlaveQual0(LPC_I2C_T *pI2C, bool extend, uint8_t slvNum) -{ - slvNum = slvNum << 1; - if (extend) { - slvNum |= I2C_SLVQUAL_QUALMODE0; - } - - pI2C->SLVQUAL0 = slvNum; -} - -/** - * @brief Slave transfer state change handler - * @param pI2C : Pointer to selected I2C peripheral - * @param xfers : Pointer to a I2CS_MULTI_XFER_T structure see notes below - * @return Returns non-zero value on completion of transfer - * @note See @ref I2CS_XFER_T for more information on this function. When using - * this function, the I2C_INTENSET_SLVPENDING and I2C_INTENSET_SLVDESEL interrupts - * should be enabled and setup in the I2C interrupt handler to call this function - * when they fire. - */ -uint32_t Chip_I2CS_XferHandler(LPC_I2C_T *pI2C, const I2CS_XFER_T *xfers); - -/** - * @} - */ - - - #ifdef __cplusplus -} -#endif - -#endif /* __I2C_COMMON_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/iap/iap.c b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/iap/iap.c deleted file mode 100644 index 75a06d28b1b..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/iap/iap.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * @brief Common FLASH support functions - * - * @note - * Copyright(C) NXP Semiconductors, 2013 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Prepare sector for write operation */ -uint8_t Chip_IAP_PreSectorForReadWrite(uint32_t strSector, uint32_t endSector) -{ - uint32_t command[5], result[5]; - - command[0] = IAP_PREWRRITE_CMD; - command[1] = strSector; - command[2] = endSector; - iap_entry(command, result); - - return result[0]; -} - -/* Copy RAM to flash */ -uint8_t Chip_IAP_CopyRamToFlash(uint32_t dstAdd, uint32_t *srcAdd, uint32_t byteswrt) -{ - uint32_t command[5], result[5]; - - command[0] = IAP_WRISECTOR_CMD; - command[1] = dstAdd; - command[2] = (uint32_t) srcAdd; - command[3] = byteswrt; - command[4] = SystemCoreClock / 1000; - iap_entry(command, result); - - return result[0]; -} - -/* Erase sector */ -uint8_t Chip_IAP_EraseSector(uint32_t strSector, uint32_t endSector) -{ - uint32_t command[5], result[5]; - - command[0] = IAP_ERSSECTOR_CMD; - command[1] = strSector; - command[2] = endSector; - command[3] = SystemCoreClock / 1000; - iap_entry(command, result); - - return result[0]; -} - -/* Blank check sector */ -uint8_t Chip_IAP_BlankCheckSector(uint32_t strSector, uint32_t endSector) -{ - uint32_t command[5], result[5]; - - command[0] = IAP_BLANK_CHECK_SECTOR_CMD; - command[1] = strSector; - command[2] = endSector; - iap_entry(command, result); - - return result[0]; -} - -/* Read part identification number */ -uint32_t Chip_IAP_ReadPID(void) -{ - uint32_t command[5], result[5]; - - command[0] = IAP_REPID_CMD; - iap_entry(command, result); - - return result[1]; -} - -/* Read boot code version number */ -uint32_t Chip_IAP_ReadBootCode(void) -{ - uint32_t command[5], result[5]; - - command[0] = IAP_READ_BOOT_CODE_CMD; - iap_entry(command, result); - - return result[1] & 0xffff; -} - -/* IAP compare */ -uint8_t Chip_IAP_Compare(uint32_t dstAdd, uint32_t srcAdd, uint32_t bytescmp) -{ - uint32_t command[5], result[5]; - - command[0] = IAP_COMPARE_CMD; - command[1] = dstAdd; - command[2] = srcAdd; - command[3] = bytescmp; - iap_entry(command, result); - - return result[0]; -} - -/* Reinvoke ISP */ -uint8_t Chip_IAP_ReinvokeISP(void) -{ - uint32_t command[5], result[5]; - - command[0] = IAP_REINVOKE_ISP_CMD; - iap_entry(command, result); - - return result[0]; -} - -/* Read the unique ID */ -uint32_t Chip_IAP_ReadUID(uint32_t* uid) -{ - uint32_t command[5], result[5]; - uint32_t i; - - command[0] = IAP_READ_UID_CMD; - iap_entry(command, result); - - for (i=0; i<4; i++) - *(uid+i) = result[i+1]; - - return result[0]; -} - -/* Erase page */ -uint8_t Chip_IAP_ErasePage(uint32_t strPage, uint32_t endPage) -{ - uint32_t command[5], result[5]; - - command[0] = IAP_ERASE_PAGE_CMD; - command[1] = strPage; - command[2] = endPage; - command[3] = SystemCoreClock / 1000; - iap_entry(command, result); - - return result[0]; -} diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/iap/iap.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/iap/iap.h deleted file mode 100644 index c3f874b324d..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/iap/iap.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * @brief Common IAP support functions - * - * @note - * Copyright(C) NXP Semiconductors, 2013 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __IAP_H_ -#define __IAP_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup COMMON_IAP CHIP: Common Chip ISP/IAP commands and return codes - * @ingroup CHIP_Common - * @{ - */ - -/* IAP command definitions */ -#define IAP_PREWRRITE_CMD 50 /*!< Prepare sector for write operation command */ -#define IAP_WRISECTOR_CMD 51 /*!< Write Sector command */ -#define IAP_ERSSECTOR_CMD 52 /*!< Erase Sector command */ -#define IAP_BLANK_CHECK_SECTOR_CMD 53 /*!< Blank check sector */ -#define IAP_REPID_CMD 54 /*!< Read PartID command */ -#define IAP_READ_BOOT_CODE_CMD 55 /*!< Read Boot code version */ -#define IAP_COMPARE_CMD 56 /*!< Compare two RAM address locations */ -#define IAP_REINVOKE_ISP_CMD 57 /*!< Reinvoke ISP */ -#define IAP_READ_UID_CMD 58 /*!< Read UID */ -#define IAP_ERASE_PAGE_CMD 59 /*!< Erase page */ -#define IAP_EEPROM_WRITE 61 /*!< EEPROM Write command */ -#define IAP_EEPROM_READ 62 /*!< EEPROM READ command */ - -/* IAP response definitions */ -#define IAP_CMD_SUCCESS 0 /*!< Command is executed successfully */ -#define IAP_INVALID_COMMAND 1 /*!< Invalid command */ -#define IAP_SRC_ADDR_ERROR 2 /*!< Source address is not on word boundary */ -#define IAP_DST_ADDR_ERROR 3 /*!< Destination address is not on a correct boundary */ -#define IAP_SRC_ADDR_NOT_MAPPED 4 /*!< Source address is not mapped in the memory map */ -#define IAP_DST_ADDR_NOT_MAPPED 5 /*!< Destination address is not mapped in the memory map */ -#define IAP_COUNT_ERROR 6 /*!< Byte count is not multiple of 4 or is not a permitted value */ -#define IAP_INVALID_SECTOR 7 /*!< Sector number is invalid or end sector number is greater than start sector number */ -#define IAP_SECTOR_NOT_BLANK 8 /*!< Sector is not blank */ -#define IAP_SECTOR_NOT_PREPARED 9 /*!< Command to prepare sector for write operation was not executed */ -#define IAP_COMPARE_ERROR 10 /*!< Source and destination data not equal */ -#define IAP_BUSY 11 /*!< Flash programming hardware interface is busy */ -#define IAP_PARAM_ERROR 12 /*!< nsufficient number of parameters or invalid parameter */ -#define IAP_ADDR_ERROR 13 /*!< Address is not on word boundary */ -#define IAP_ADDR_NOT_MAPPED 14 /*!< Address is not mapped in the memory map */ -#define IAP_CMD_LOCKED 15 /*!< Command is locked */ -#define IAP_INVALID_CODE 16 /*!< Unlock code is invalid */ -#define IAP_INVALID_BAUD_RATE 17 /*!< Invalid baud rate setting */ -#define IAP_INVALID_STOP_BIT 18 /*!< Invalid stop bit setting */ -#define IAP_CRP_ENABLED 19 /*!< Code read protection enabled */ - -/* IAP_ENTRY API function type */ -typedef void (*IAP_ENTRY_T)(unsigned int[], unsigned int[]); - -/** - * @brief Prepare sector for write operation - * @param strSector : Start sector number - * @param endSector : End sector number - * @return Status code to indicate the command is executed successfully or not - * @note This command must be executed before executing "Copy RAM to flash" - * or "Erase Sector" command. - * The end sector must be greater than or equal to start sector number - */ -uint8_t Chip_IAP_PreSectorForReadWrite(uint32_t strSector, uint32_t endSector); - -/** - * @brief Copy RAM to flash - * @param dstAdd : Destination FLASH address where data bytes are to be written - * @param srcAdd : Source RAM address where data bytes are to be read - * @param byteswrt : Number of bytes to be written - * @return Status code to indicate the command is executed successfully or not - * @note The addresses should be a 256 byte boundary and the number of bytes - * should be 256 | 512 | 1024 | 4096 - */ -uint8_t Chip_IAP_CopyRamToFlash(uint32_t dstAdd, uint32_t *srcAdd, uint32_t byteswrt); - -/** - * @brief Erase sector - * @param strSector : Start sector number - * @param endSector : End sector number - * @return Status code to indicate the command is executed successfully or not - * @note The end sector must be greater than or equal to start sector number - */ -uint8_t Chip_IAP_EraseSector(uint32_t strSector, uint32_t endSector); - -/** - * @brief Blank check a sector or multiples sector of on-chip flash memory - * @param strSector : Start sector number - * @param endSector : End sector number - * @return Offset of the first non blank word location if the status code is SECTOR_NOT_BLANK - * @note The end sector must be greater than or equal to start sector number - */ -// FIXME - There are two return value (result[0] & result[1] -// Result0:Offset of the first non blank word location if the Status Code is -// SECTOR_NOT_BLANK. -// Result1:Contents of non blank word location. -uint8_t Chip_IAP_BlankCheckSector(uint32_t strSector, uint32_t endSector); - -/** - * @brief Read part identification number - * @return Part identification number - */ -uint32_t Chip_IAP_ReadPID(void); - -/** - * @brief Read boot code version number - * @return Boot code version number - */ -uint32_t Chip_IAP_ReadBootCode(void); - -/** - * @brief Compare the memory contents at two locations - * @param dstAdd : Destination of the RAM address of data bytes to be compared - * @param srcAdd : Source of the RAM address of data bytes to be compared - * @param bytescmp : Number of bytes to be compared - * @return Offset of the first mismatch of the status code is COMPARE_ERROR - * @note The addresses should be a word boundary and number of bytes should be - * a multiply of 4 - */ -uint8_t Chip_IAP_Compare(uint32_t dstAdd, uint32_t srcAdd, uint32_t bytescmp); - -/** - * @brief IAP reinvoke ISP to invoke the bootloader in ISP mode - * @return none - */ -uint8_t Chip_IAP_ReinvokeISP(void); - -/** - * @brief Read the unique ID - * @return Status code to indicate the command is executed successfully or not - */ -uint32_t Chip_IAP_ReadUID(uint32_t* uid); - -/** - * @brief Erase a page or multiple papers of on-chip flash memory - * @param strPage : Start page number - * @param endPage : End page number - * @return Status code to indicate the command is executed successfully or not - * @note The page number must be greater than or equal to start page number - */ -// FIXME - There are four return value -// Result0:The first 32-bit word (at the lowest address) -// Result1:The second 32-bit word. -// Result2:The third 32-bit word. -// Result3:The fourth 32-bit word. -uint8_t Chip_IAP_ErasePage(uint32_t strPage, uint32_t endPage); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __IAP_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/inmux/inmux_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/inmux/inmux_8xx.h deleted file mode 100644 index 360f489db32..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/inmux/inmux_8xx.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * @brief LPC8xx INPUT MUX chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2013 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __INMUX_8XX_H_ -#define __INMUX_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup INMUX_8XX CHIP: LPC8xx INPUT Mux Controller driver - * @ingroup CHIP_8XX_Drivers - * @{ - */ -typedef struct { - __IO uint32_t DMA_INMUX_INMUX[2]; /*!< DMA Trigger Input 20 & 21 PINMUX 0-1 */ - __O uint32_t RESERVED[6]; /*!< Reserved; Should not be used */ - __IO uint32_t SCT0_INMUX[4]; /*!< Input mux register for SCT0; INPUT0-3 */ -} LPC_INMUX_T; - -/** - * @brief DMA INPUT MUX Index see Chip_INMUX_SetDMAOTrig() - */ -typedef enum { - DMA_INMUX_0, /*!< MUX for DMA input trigger 20 */ - DMA_INMUX_1, /*!< MUX for DMA input trigger 21 */ -}DMA_INMUX_T; - -/** - * @brief SCT Input Mux Index; See Chip_INMUX_SetSCTInMux() - */ -typedef enum { - SCT_INMUX_0, /*!< Input mux for SCT0; INPUT 0 */ - SCT_INMUX_1, /*!< Input mux for SCT0; INPUT 1 */ - SCT_INMUX_2, /*!< Input mux for SCT0; INPUT 2 */ - SCT_INMUX_3, /*!< Input mux for SCT0; INPUT 3 */ -} SCT_INMUX_T; - -/** - * @brief SCT INPUT triggers - */ -typedef enum { - SCT_INP_IN0, /*!< SCT0_IN0 selected by Pin Matrix */ /* FIXME: UM hints about changes */ - SCT_INP_IN1, /*!< SCT0_IN1 selected by Pin Matrix */ - SCT_INP_IN2, /*!< SCT0_IN2 selected by Pin Matrix */ - SCT_INP_IN3, /*!< SCT0_IN3 selected by Pin Matrix */ - SCT_INP_ADC_THCMP_IRQ, /*!< ADC Threshold compare IRQ */ - SCT_INP_ACMP_O, /*!< Analog comparator output */ - SCT_INP_ARM_TXEV, /*!< ARM TX Event */ - SCT_INP_DEBUG_HALTED, /*!< Debug halted event */ -} SCT_INP_T; - -/** - * @brief Select a trigger source for a DMA channel - * @param pINMUX : The base of INPUT MUX register block - * @param imux : Index of DMA input mux - * @param ch : DMA channel ID - * @return Nothing - */ -STATIC INLINE void Chip_INMUX_SetDMAOTrig(LPC_INMUX_T *pINMUX, DMA_INMUX_T imux, DMA_CHID_T ch) -{ - pINMUX->DMA_INMUX_INMUX[imux] = ch; -} - -/** - * @brief Select a trigger source SCT module - * @param pINMUX : The base of INPUT MUX register block - * @param isct : Index of SCT input mux - * @param trig : SCT Input function that will cause the trigger - * @return Nothing - */ -STATIC INLINE void Chip_INMUX_SetSCTInMux(LPC_INMUX_T *pINMUX, SCT_INMUX_T isct, SCT_INP_T trig) -{ - pINMUX->SCT0_INMUX[isct] = trig; -} - -/** @defgroup DMATRIGMUX_8XX CHIP: LPC8xx DMA trigger selection driver - * @{ - */ - -/** - * @brief DMA trigger pin muxing structure - */ -typedef struct { /*!< DMA trigger pin muxing register structure */ - __IO uint32_t DMA_ITRIG_INMUX[MAX_DMA_CHANNEL]; /*!< Trigger input select register for DMA channels */ -} LPC_DMATRIGMUX_T; - -/* DMA triggers that can mapped to DMA channels */ -typedef enum { - DMATRIG_ADC_SEQA_IRQ = 0, /*!< ADC0 sequencer A interrupt as trigger */ - DMATRIG_ADC_SEQB_IRQ, /*!< ADC0 sequencer B interrupt as trigger */ - DMATRIG_SCT0_DMA0, /*!< SCT 0, DMA 0 as trigger */ - DMATRIG_SCT0_DMA1, /*!< SCT 1, DMA 1 as trigger */ - DMATRIG_ACMP_O, /*!< Analog comparator output */ - DMATRIG_PINT0, /*!< Pin interrupt 0 as trigger */ - DMATRIG_PINT1, /*!< Pin interrupt 1 as trigger */ - DMATRIG_DMA_INMUX0, /*!< DMA Trigger MUX0 */ - DMATRIG_DMA_INMUX1, /*!< DMA Trigger MUX1 */ -} DMA_TRIGSRC_T; - -/** - * @brief Select a trigger source for a DMA channel - * @param pDMATRIG : The base of DMA trigger setup block on the chip - * @param ch : DMA channel ID - * @param trig : Trigger source for the DMA channel - * @return Nothing - * @note A DMA trigger source only needs to be setup when the DMA is setup - * for hardware trigger mode (when Chip_DMA_SetupChannelConfig() is - * called with DMA_CFG_HWTRIGEN as OR'ed option). - */ -STATIC INLINE void Chip_DMATRIGMUX_SetInputTrig(LPC_DMATRIGMUX_T *pDMATRIG, DMA_CHID_T ch, DMA_TRIGSRC_T trig) -{ - pDMATRIG->DMA_ITRIG_INMUX[ch] = (uint32_t) trig; -} - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __INMUX_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/mrt/mrt_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/mrt/mrt_8xx.h deleted file mode 100644 index 220c7e1b8d4..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/mrt/mrt_8xx.h +++ /dev/null @@ -1,343 +0,0 @@ -/* - * @brief LPC8xx Multi-Rate Timer (MRT) registers and driver functions - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __MRT_8XX_H_ -#define __MRT_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup MRT_8XX CHIP: LPC8xx Multi-Rate Timer driver - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/** - * @brief LPC8xx MRT chip configuration - */ -#define MRT_CHANNELS_NUM (4) -#define MRT_NO_IDLE_CHANNEL (0x40) - -/** - * @brief MRT register block structure - */ -typedef struct { - __IO uint32_t INTVAL; /*!< Timer interval register */ - __O uint32_t TIMER; /*!< Timer register */ - __IO uint32_t CTRL; /*!< Timer control register */ - __IO uint32_t STAT; /*!< Timer status register */ -} LPC_MRT_CH_T; - -/** - * @brief MRT register block structure - */ -typedef struct { - LPC_MRT_CH_T CHANNEL[MRT_CHANNELS_NUM]; - uint32_t unused[45]; - __O uint32_t IDLE_CH; - __IO uint32_t IRQ_FLAG; -} LPC_MRT_T; - -/* Reserved bits masks for registers */ -#define MRT_CTRL_RESERVED (~7) -#define MRT_STAT_RESERVED (~3) - -/** - * @brief MRT Interrupt Modes enum - */ -typedef enum MRT_MODE { - MRT_MODE_REPEAT = (0 << 1), /*!< MRT Repeat interrupt mode */ - MRT_MODE_ONESHOT = (1 << 1) /*!< MRT One-shot interrupt mode */ -} MRT_MODE_T; - -/** - * @brief MRT register bit fields & masks - */ -/* MRT Time interval register bit fields */ -#define MRT_INTVAL_IVALUE (0x7FFFFFFFUL) /* Maximum interval load value and mask */ -#define MRT_INTVAL_LOAD (0x80000000UL) /* Force immediate load of timer interval register bit */ - -/* MRT Control register bit fields & masks */ -#define MRT_CTRL_INTEN_MASK (0x01) -#define MRT_CTRL_MODE_MASK (0x06) - -/* MRT Status register bit fields & masks */ -#define MRT_STAT_INTFLAG (0x01) -#define MRT_STAT_RUNNING (0x02) - -/* Pointer to individual MR register blocks */ -#define LPC_MRT_CH0 ((LPC_MRT_CH_T *) &LPC_MRT->CHANNEL[0]) -#define LPC_MRT_CH1 ((LPC_MRT_CH_T *) &LPC_MRT->CHANNEL[1]) -#define LPC_MRT_CH2 ((LPC_MRT_CH_T *) &LPC_MRT->CHANNEL[2]) -#define LPC_MRT_CH3 ((LPC_MRT_CH_T *) &LPC_MRT->CHANNEL[3]) -#define LPC_MRT_CH(ch) ((LPC_MRT_CH_T *) &LPC_MRT->CHANNEL[(ch)]) - -/* Global interrupt flag register interrupt mask/clear values */ -#define MRT0_INTFLAG (1) -#define MRT1_INTFLAG (2) -#define MRT2_INTFLAG (4) -#define MRT3_INTFLAG (8) -#define MRTn_INTFLAG(ch) (1 << (ch)) - -/** - * @brief Initializes the MRT - * @return Nothing - */ -STATIC INLINE void Chip_MRT_Init(void) -{ - /* Enable the clock to the register interface */ - Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_MRT); - - /* Reset MRT */ - Chip_SYSCTL_PeriphReset(RESET_MRT); -} - -/** - * @brief De-initializes the MRT Channel - * @return Nothing - */ -STATIC INLINE void Chip_MRT_DeInit(void) -{ - /* Disable the clock to the MRT */ - Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_MRT); -} - -/** - * @brief Returns a pointer to the register block for a MRT channel - * @param ch : MRT channel tog et register block for (0..3) - * @return Pointer to the MRT register block for the channel - */ -STATIC INLINE LPC_MRT_CH_T *Chip_MRT_GetRegPtr(uint8_t ch) -{ - return LPC_MRT_CH(ch); -} - -/** - * @brief Returns the timer time interval value - * @param pMRT : Pointer to selected MRT Channel - * @return Timer time interval value (IVALUE) - */ -STATIC INLINE uint32_t Chip_MRT_GetInterval(LPC_MRT_CH_T *pMRT) -{ - return pMRT->INTVAL; -} - -/** - * @brief Sets the timer time interval value - * @param pMRT : Pointer to selected MRT Channel - * @param interval : The interval timeout (31-bits) - * @return Nothing - * @note Setting bit 31 in timer time interval register causes the time interval value - * to load immediately, otherwise the time interval value will be loaded in - * next timer cycle.
- * Example: Chip_MRT_SetInterval(pMRT, 0x500 | MRT_INTVAL_LOAD); // Will load timer interval immediately
- * Example: Chip_MRT_SetInterval(pMRT, 0x500); // Will load timer interval after internal expires - */ -STATIC INLINE void Chip_MRT_SetInterval(LPC_MRT_CH_T *pMRT, uint32_t interval) -{ - pMRT->INTVAL = interval; -} - -/** - * @brief Returns the current timer value - * @param pMRT : Pointer to selected MRT Channel - * @return The current timer value - */ -STATIC INLINE uint32_t Chip_MRT_GetTimer(LPC_MRT_CH_T *pMRT) -{ - return pMRT->TIMER; -} - -/** - * @brief Returns true if the timer is enabled - * @param pMRT : Pointer to selected MRT Channel - * @return True if enabled, Flase if not enabled - */ -STATIC INLINE bool Chip_MRT_GetEnabled(LPC_MRT_CH_T *pMRT) -{ - return (bool) ((pMRT->CTRL & MRT_CTRL_INTEN_MASK) != 0); -} - -/** - * @brief Enables the timer - * @param pMRT : Pointer to selected MRT Channel - * @return Nothing - */ -STATIC INLINE void Chip_MRT_SetEnabled(LPC_MRT_CH_T *pMRT) -{ - pMRT->CTRL = MRT_CTRL_INTEN_MASK | (pMRT->CTRL & ~MRT_CTRL_RESERVED); -} - -/** - * @brief Disables the timer - * @param pMRT : Pointer to selected MRT Channel - * @return Nothing - */ -STATIC INLINE void Chip_MRT_SetDisabled(LPC_MRT_CH_T *pMRT) -{ - pMRT->CTRL &= ~(MRT_CTRL_INTEN_MASK | MRT_CTRL_RESERVED); -} - -/** - * @brief Returns the timer mode (repeat or one-shot) - * @param pMRT : Pointer to selected MRT Channel - * @return The current timer mode - */ -STATIC INLINE MRT_MODE_T Chip_MRT_GetMode(LPC_MRT_CH_T *pMRT) -{ - return (MRT_MODE_T) (pMRT->CTRL & MRT_CTRL_MODE_MASK); -} - -/** - * @brief Sets the timer mode (repeat or one-shot) - * @param pMRT : Pointer to selected MRT Channel - * @param mode : Timer mode - * @return Nothing - */ -STATIC INLINE void Chip_MRT_SetMode(LPC_MRT_CH_T *pMRT, MRT_MODE_T mode) -{ - uint32_t reg; - - reg = pMRT->CTRL & ~(MRT_CTRL_MODE_MASK | MRT_CTRL_RESERVED); - pMRT->CTRL = reg | (uint32_t) mode; -} - -/** - * @brief Check if the timer is configured in repeat mode - * @param pMRT : Pointer to selected MRT Channel - * @return True if in repeat mode, False if in one-shot mode - */ -STATIC INLINE bool Chip_MRT_IsRepeatMode(LPC_MRT_CH_T *pMRT) -{ - return ((pMRT->CTRL & MRT_CTRL_MODE_MASK) != 0) ? false : true; -} - -/** - * @brief Check if the timer is configured in one-shot mode - * @param pMRT : Pointer to selected MRT Channel - * @return True if in one-shot mode, False if in repeat mode - */ -STATIC INLINE bool Chip_MRT_IsOneShotMode(LPC_MRT_CH_T *pMRT) -{ - return ((pMRT->CTRL & MRT_CTRL_MODE_MASK) != 0) ? true : false; -} - -/** - * @brief Check if the timer has an interrupt pending - * @param pMRT : Pointer to selected MRT Channel - * @return True if interrupt is pending, False if no interrupt is pending - */ -STATIC INLINE bool Chip_MRT_IntPending(LPC_MRT_CH_T *pMRT) -{ - return (bool) ((pMRT->STAT & MRT_STAT_INTFLAG) != 0); -} - -/** - * @brief Clears the pending interrupt (if any) - * @param pMRT : Pointer to selected MRT Channel - * @return Nothing - */ -STATIC INLINE void Chip_MRT_IntClear(LPC_MRT_CH_T *pMRT) -{ - pMRT->STAT = MRT_STAT_INTFLAG | (pMRT->STAT & ~MRT_STAT_RESERVED); -} - -/** - * @brief Check if the timer is running - * @param pMRT : Pointer to selected MRT Channel - * @return True if running, False if stopped - */ -STATIC INLINE bool Chip_MRT_Running(LPC_MRT_CH_T *pMRT) -{ - return (bool) ((pMRT->STAT & MRT_STAT_RUNNING) != 0); -} - -/** - * @brief Returns the IDLE channel value - * @return IDLE channel value (unshifted in bits 7..4) - */ -STATIC INLINE uint8_t Chip_MRT_GetIdleChannel(void) -{ - return (uint8_t) (LPC_MRT->IDLE_CH); -} - -/** - * @brief Returns the IDLE channel value - * @return IDLE channel value (shifted in bits 3..0) - */ -STATIC INLINE uint8_t Chip_MRT_GetIdleChannelShifted(void) -{ - return (uint8_t) (Chip_MRT_GetIdleChannel() >> 4); -} - -/** - * @brief Returns the interrupt pending status for all MRT channels - * @return IRQ pending channel bitfield(bit 0 = MRT0, bit 1 = MRT1, etc.) - */ -STATIC INLINE uint32_t Chip_MRT_GetIntPending(void) -{ - return LPC_MRT->IRQ_FLAG; -} - -/** - * @brief Returns the interrupt pending status for a singel MRT channel - * @param ch : Channel to check pending interrupt status for - * @return IRQ pending channel number - */ -STATIC INLINE bool Chip_MRT_GetIntPendingByChannel(uint8_t ch) -{ - return (bool) (((LPC_MRT->IRQ_FLAG >> ch) & 1) != 0); -} - -/** - * @brief Clears the interrupt pending status for one or more MRT channels - * @param mask : Channels to clear (bit 0 = MRT0, bit 1 = MRT1, etc.) - * @return Nothing - * @note Use this function to clear multiple interrupt pending states in - * a single call via the IRQ_FLAG register. Performs the same function for - * all MRT channels in a single call as the Chip_MRT_IntClear() does for a - * single channel. - */ -STATIC INLINE void Chip_MRT_ClearIntPending(uint32_t mask) -{ - LPC_MRT->IRQ_FLAG = mask; -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __MRT_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/mrt/stopwatch.c b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/mrt/stopwatch.c deleted file mode 100644 index 6fa1ec2f2b3..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/mrt/stopwatch.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * @brief LPC8xx specific stopwatch implementation - * - * @note - * Copyright(C) NXP Semiconductors, 2013 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" -#include "stopwatch.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/* Precompute these to optimize runtime */ -static uint32_t ticksPerSecond; -static uint32_t ticksPerMs; -static uint32_t ticksPerUs; - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Initialize stopwatch */ -void StopWatch_Init(void) -{ - Chip_MRT_Init(); - Chip_MRT_SetMode(LPC_MRT_CH1, MRT_MODE_REPEAT); - Chip_MRT_SetInterval(LPC_MRT_CH1, 0x7ffffff | MRT_INTVAL_LOAD); - Chip_MRT_GetEnabled(LPC_MRT_CH1); - - /* Pre-compute tick rate. */ - ticksPerSecond = Chip_Clock_GetSystemClockRate(); - ticksPerMs = ticksPerSecond / 1000; - ticksPerUs = ticksPerSecond / 1000000; -} -/* reset stopwatch */ -void StopWatch_Reset(void) -{ - Chip_MRT_SetInterval(LPC_MRT_CH1, 0x7ffffff | MRT_INTVAL_LOAD); -} - - -/* Start a stopwatch */ -uint32_t StopWatch_Start(void) -{ - /* Return the current timer count. */ - return 0x7ffffff - Chip_MRT_GetTimer(LPC_MRT_CH1); -} - -/* Returns number of ticks per second of the stopwatch timer */ -uint32_t StopWatch_TicksPerSecond(void) -{ - return ticksPerSecond; -} - -/* Converts from stopwatch ticks to mS. */ -uint32_t StopWatch_TicksToMs(uint32_t ticks) -{ - return ticks / ticksPerMs; -} - -/* Converts from stopwatch ticks to uS. */ -uint32_t StopWatch_TicksToUs(uint32_t ticks) -{ - return ticks / ticksPerUs; -} - -/* Converts from mS to stopwatch ticks. */ -uint32_t StopWatch_MsToTicks(uint32_t mS) -{ - return mS * ticksPerMs; -} - -/* Converts from uS to stopwatch ticks. */ -uint32_t StopWatch_UsToTicks(uint32_t uS) -{ - return uS * ticksPerUs; -} diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/mrt/stopwatch.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/mrt/stopwatch.h deleted file mode 100644 index 993f4b10096..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/mrt/stopwatch.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * @brief Common stopwatch support - * - * @note - * Copyright(C) NXP Semiconductors, 2013 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __STOPWATCH_H_ -#define __STOPWATCH_H_ - -#include "cmsis.h" - -/** @defgroup Stop_Watch CHIP: Stopwatch primitives. - * @ingroup CHIP_Common - * @{ - */ - -/** - * @brief Initialize stopwatch - * @return Nothing - */ -void StopWatch_Init(void); - -/** - * @brief reset stopwatch - * @return Nothing - */ -void StopWatch_Reset(void); - -/** - * @brief Start a stopwatch - * @return Current cycle count - */ -uint32_t StopWatch_Start(void); - -/** - * @brief Returns number of ticks elapsed since stopwatch was started - * @param startTime : Time returned by StopWatch_Start(). - * @return Number of ticks elapsed since stopwatch was started - */ -STATIC INLINE uint32_t StopWatch_Elapsed(uint32_t startTime) -{ - return StopWatch_Start() - startTime; -} - -/** - * @brief Returns number of ticks per second of the stopwatch timer - * @return Number of ticks per second of the stopwatch timer - */ -uint32_t StopWatch_TicksPerSecond(void); - -/** - * @brief Converts from stopwatch ticks to mS. - * @param ticks : Duration in ticks to convert to mS. - * @return Number of mS in given number of ticks - */ -uint32_t StopWatch_TicksToMs(uint32_t ticks); - -/** - * @brief Converts from stopwatch ticks to uS. - * @param ticks : Duration in ticks to convert to uS. - * @return Number of uS in given number of ticks - */ -uint32_t StopWatch_TicksToUs(uint32_t ticks); - -/** - * @brief Converts from mS to stopwatch ticks. - * @param mS : Duration in mS to convert to ticks. - * @return Number of ticks in given number of mS - */ -uint32_t StopWatch_MsToTicks(uint32_t mS); - -/** - * @brief Converts from uS to stopwatch ticks. - * @param uS : Duration in uS to convert to ticks. - * @return Number of ticks in given number of uS - */ -uint32_t StopWatch_UsToTicks(uint32_t uS); - -/** - * @brief Delays the given number of ticks using stopwatch primitives - * @param ticks : Number of ticks to delay - * @return Nothing - */ -STATIC INLINE void StopWatch_DelayTicks(uint32_t ticks) -{ - uint32_t startTime = StopWatch_Start(); - while (StopWatch_Elapsed(startTime) < ticks) {} -} - -/** - * @brief Delays the given number of mS using stopwatch primitives - * @param mS : Number of mS to delay - * @return Nothing - */ -STATIC INLINE void StopWatch_DelayMs(uint32_t mS) -{ - uint32_t ticks = StopWatch_MsToTicks(mS); - uint32_t startTime = StopWatch_Start(); - while (StopWatch_Elapsed(startTime) < ticks) {} -} - -/** - * @brief Delays the given number of uS using stopwatch primitives - * @param uS : Number of uS to delay - * @return Nothing - */ -STATIC INLINE void StopWatch_DelayUs(uint32_t uS) -{ - uint32_t ticks = StopWatch_UsToTicks(uS); - uint32_t startTime = StopWatch_Start(); - while (StopWatch_Elapsed(startTime) < ticks) {} -} - -/** - * @} - */ - -#endif /* __STOPWATCH_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/peri_driver.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/peri_driver.h deleted file mode 100644 index 3344960bee1..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/peri_driver.h +++ /dev/null @@ -1,39 +0,0 @@ -#ifndef _PERI_DRIVER_H_ -#define _PERI_DRIVER_H_ - -#include "chip.h" -#include "rom/romapi_8xx.h" -#include "acmp/acmp_8xx.h" - -#if defined(CHIP_LPC82X) - #include "adc/adc_8xx.h" -#endif - -#include "crc/crc_8xx.h" - -#if defined(CHIP_LPC82X) - #include "dma/dma_8xx.h" -#endif - -#include "gpio/gpio_8xx.h" -#include "i2c/i2c_8xx.h" -#include "iap/iap.h" -#include "crc/crc_8xx.h" - -#if defined(CHIP_LPC82X) - #include "inmux/inmux_8xx.h" -#endif - -#include "mrt/mrt_8xx.h" -#include "mrt/stopwatch.h" -#include "pinint/pinint_8xx.h" -#include "pmu/pmu_8xx.h" - -#include "sctimer/sct_8xx.h" -#include "sctimer/sct_pwm_8xx.h" -#include "spi/spi_8xx.h" -#include "uart/uart_8xx.h" -#include "wkt/wkt_8xx.h" -#include "wwdt/wwdt_8xx.h" -#include "iap/iap.h" -#endif diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/pinint/pinint_8xx.c b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/pinint/pinint_8xx.c deleted file mode 100644 index 2de02819607..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/pinint/pinint_8xx.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * @brief LPC8xx Pin Interrupt and Pattern Match driver - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Set source for pattern match engine */ -void Chip_PININT_SetPatternMatchSrc(LPC_PININT_T *pPININT, uint8_t chan, Chip_PININT_BITSLICE_T slice) -{ - uint32_t pmsrc_reg; - - /* Source source for pattern matching */ - pmsrc_reg = pPININT->PMSRC & ~((PININT_SRC_BITSOURCE_MASK << (PININT_SRC_BITSOURCE_START + (slice * 3))) - | PININT_PMSRC_RESERVED); - pPININT->PMSRC = pmsrc_reg | (chan << (PININT_SRC_BITSOURCE_START + (slice * 3))); -} - -/* Configure Pattern match engine */ -void Chip_PININT_SetPatternMatchConfig(LPC_PININT_T *pPININT, Chip_PININT_BITSLICE_T slice, - Chip_PININT_BITSLICE_CFG_T slice_cfg, bool end_point) -{ - uint32_t pmcfg_reg; - - /* Configure bit slice configuration */ - pmcfg_reg = pPININT->PMCFG & ~((PININT_SRC_BITCFG_MASK << (PININT_SRC_BITCFG_START + (slice * 3))) - | PININT_PMCFG_RESERVED); - pPININT->PMCFG = pmcfg_reg | (slice_cfg << (PININT_SRC_BITCFG_START + (slice * 3))); - - /* If end point is true, enable the bits */ - if (end_point == true) - { - /* By default slice 7 is final component */ - if (slice != PININTBITSLICE7) - { - pPININT->PMCFG = (0x1 << slice) | (pPININT->PMCFG & ~PININT_PMCFG_RESERVED); - } - } -} diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/pinint/pinint_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/pinint/pinint_8xx.h deleted file mode 100644 index c6f151a3f6a..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/pinint/pinint_8xx.h +++ /dev/null @@ -1,389 +0,0 @@ -/* - * @brief LPC8xx Pin Interrupt and Pattern Match Registers and driver - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __PININT_8XX_H_ -#define __PININT_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup PININT_8XX CHIP: LPC8xx Pin Interrupt and Pattern Match driver - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/** - * @brief LPC8xx Pin Interrupt and Pattern Match register block structure - */ -typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */ - __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */ - __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */ - __IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */ - __IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */ - __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */ - __IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */ - __IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */ - __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */ - __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */ - __IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */ - __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */ - __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */ - __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */ -} LPC_PININT_T; - -/* Reserved bits masks for registers */ -#define PININT_ISEL_RESERVED (~0xff) -#define PININT_IENR_RESERVED (~0xff) -#define PININT_SIENR_RESERVED (~0xff) -#define PININT_CIENR_RESERVED (~0xff) -#define PININT_IENF_RESERVED (~0xff) -#define PININT_SIENF_RESERVED (~0xff) -#define PININT_CIENF_RESERVED (~0xff) -#define PININT_RISE_RESERVED (~0xff) -#define PININT_FALL_RESERVED (~0xff) -#define PININT_IST_RESERVED (~0xff) -#define PININT_PMCTRL_RESERVED (~0xff000003) -#define PININT_PMSRC_RESERVED 0xff -#define PININT_PMCFG_RESERVED (1<<7) - -/** - * LPC8xx Pin Interrupt and Pattern match engine register - * bit fields and macros - */ -/* PININT interrupt control register */ -#define PININT_PMCTRL_PMATCH_SEL (1 << 0) -#define PININT_PMCTRL_RXEV_ENA (1 << 1) - -/* PININT Bit slice source register bits */ -#define PININT_SRC_BITSOURCE_START 8 -#define PININT_SRC_BITSOURCE_MASK 7 - -/* PININT Bit slice configuration register bits */ -#define PININT_SRC_BITCFG_START 8 -#define PININT_SRC_BITCFG_MASK 7 - -/** - * LPC8xx Pin Interrupt channel values - */ -#define PININTCH0 (1 << 0) -#define PININTCH1 (1 << 1) -#define PININTCH2 (1 << 2) -#define PININTCH3 (1 << 3) -#define PININTCH4 (1 << 4) -#define PININTCH5 (1 << 5) -#define PININTCH6 (1 << 6) -#define PININTCH7 (1 << 7) -#define PININTCH(ch) (1 << (ch)) - -/** - * LPC8xx Pin Matching Interrupt bit slice enum values - */ -typedef enum Chip_PININT_BITSLICE { - PININTBITSLICE0 = 0, /*!< PININT Bit slice 0 */ - PININTBITSLICE1 = 1, /*!< PININT Bit slice 1 */ - PININTBITSLICE2 = 2, /*!< PININT Bit slice 2 */ - PININTBITSLICE3 = 3, /*!< PININT Bit slice 3 */ - PININTBITSLICE4 = 4, /*!< PININT Bit slice 4 */ - PININTBITSLICE5 = 5, /*!< PININT Bit slice 5 */ - PININTBITSLICE6 = 6, /*!< PININT Bit slice 6 */ - PININTBITSLICE7 = 7 /*!< PININT Bit slice 7 */ -} Chip_PININT_BITSLICE_T; - -/** - * LPC8xx Pin Matching Interrupt bit slice configuration enum values - */ -typedef enum Chip_PININT_BITSLICE_CFG { - PININT_PATTERNCONST1 = 0x0, /*!< Contributes to product term match */ - PININT_PATTERNRISING = 0x1, /*!< Rising edge */ - PININT_PATTERNFALLING = 0x2, /*!< Falling edge */ - PININT_PATTERNRISINGRFALLING = 0x3, /*!< Rising or Falling edge */ - PININT_PATTERNHIGH = 0x4, /*!< High level */ - PININT_PATTERNLOW = 0x5, /*!< Low level */ - PININT_PATTERCONST0 = 0x6, /*!< Never contributes for match */ - PININT_PATTEREVENT = 0x7 /*!< Match occurs on event */ -} Chip_PININT_BITSLICE_CFG_T; - -/** - * @brief Initialize Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @return Nothing - * @note This function should be used after the Chip_GPIO_Init() function. - */ -STATIC INLINE void Chip_PININT_Init(LPC_PININT_T *pPININT) {} - -/** - * @brief De-Initialize Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @return Nothing - */ -STATIC INLINE void Chip_PININT_DeInit(LPC_PININT_T *pPININT) {} - -/** - * @brief Configure the pins as edge sensitive in Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @param pins : Pins (ORed value of PININTCH*) - * @return Nothing - */ -STATIC INLINE void Chip_PININT_SetPinModeEdge(LPC_PININT_T *pPININT, uint32_t pins) -{ - pPININT->ISEL &= ~(pins | PININT_ISEL_RESERVED); -} - -/** - * @brief Configure the pins as level sensitive in Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @param pins : Pins (ORed value of PININTCH*) - * @return Nothing - */ -STATIC INLINE void Chip_PININT_SetPinModeLevel(LPC_PININT_T *pPININT, uint32_t pins) -{ - pPININT->ISEL = pins | (pPININT->ISEL & ~PININT_ISEL_RESERVED); - pPININT->SIENR = pins; -} - -/** - * @brief Return current PININT rising edge or high level interrupt enable state - * @param pPININT : The base address of Pin interrupt block - * @return A bifield containing the high edge/level interrupt enables for each - * interrupt. Bit 0 = PININT0, 1 = PININT1, etc. - * For each bit, a 0 means the high edge/level interrupt is disabled, while a 1 - * means it's enabled. - */ -STATIC INLINE uint32_t Chip_PININT_GetHighEnabled(LPC_PININT_T *pPININT) -{ - return pPININT->IENR & ~PININT_IENR_RESERVED; -} - -/** - * @brief Enable high edge/level PININT interrupts for pins - * @param pPININT : The base address of Pin interrupt block - * @param pins : Pins to enable (ORed value of PININTCH*) - * @return Nothing - */ -STATIC INLINE void Chip_PININT_EnableIntHigh(LPC_PININT_T *pPININT, uint32_t pins) -{ - pPININT->SIENR = pins; -} - -/** - * @brief Select high/low level for level sensitive PININT interrupts - * @param pPININT : The base address of Pin interrupt block - * @param pins : Pins to enable (ORed value of PININTCH*) - * @return Nothing -*/ -STATIC INLINE void Chip_PININT_SelectLevel(LPC_PININT_T *pPININT, uint32_t pins, bool isHigh) -{ - if (isHigh) - pPININT->SIENF = pins; - else - pPININT->CIENF = pins; -} - - -/** - * @brief Disable high edge/level PININT interrupts for pins - * @param pPININT : The base address of Pin interrupt block - * @param pins : Pins to disable (ORed value of PININTCH*) - * @return Nothing - */ -STATIC INLINE void Chip_PININT_DisableIntHigh(LPC_PININT_T *pPININT, uint32_t pins) -{ - pPININT->CIENR = pins; -} - -/** - * @brief Return current PININT falling edge or low level interrupt enable state - * @param pPININT : The base address of Pin interrupt block - * @return A bifield containing the low edge/level interrupt enables for each - * interrupt. Bit 0 = PININT0, 1 = PININT1, etc. - * For each bit, a 0 means the low edge/level interrupt is disabled, while a 1 - * means it's enabled. - */ -STATIC INLINE uint32_t Chip_PININT_GetLowEnabled(LPC_PININT_T *pPININT) -{ - return pPININT->IENF & ~PININT_IENF_RESERVED; -} - -/** - * @brief Enable low edge/level PININT interrupts for pins - * @param pPININT : The base address of Pin interrupt block - * @param pins : Pins to enable (ORed value of PININTCH*) - * @return Nothing - */ -STATIC INLINE void Chip_PININT_EnableIntLow(LPC_PININT_T *pPININT, uint32_t pins) -{ - pPININT->SIENF = pins; -} - -/** - * @brief Disable low edge/level PININT interrupts for pins - * @param pPININT : The base address of Pin interrupt block - * @param pins : Pins to disable (ORed value of PININTCH*) - * @return Nothing - */ -STATIC INLINE void Chip_PININT_DisableIntLow(LPC_PININT_T *pPININT, uint32_t pins) -{ - pPININT->CIENF = pins; -} - -/** - * @brief Return pin states that have a detected latched high edge (RISE) state - * @param pPININT : The base address of Pin interrupt block - * @return PININT states (bit n = high) with a latched rise state detected - */ -STATIC INLINE uint32_t Chip_PININT_GetRiseStates(LPC_PININT_T *pPININT) -{ - return pPININT->RISE & ~PININT_RISE_RESERVED; -} - -/** - * @brief Clears pin states that had a latched high edge (RISE) state - * @param pPININT : The base address of Pin interrupt block - * @param pins : Pins with latched states to clear - * @return Nothing - */ -STATIC INLINE void Chip_PININT_ClearRiseStates(LPC_PININT_T *pPININT, uint32_t pins) -{ - pPININT->RISE = pins; -} - -/** - * @brief Return pin states that have a detected latched falling edge (FALL) state - * @param pPININT : The base address of Pin interrupt block - * @return PININT states (bit n = high) with a latched rise state detected - */ -STATIC INLINE uint32_t Chip_PININT_GetFallStates(LPC_PININT_T *pPININT) -{ - return pPININT->FALL & ~PININT_FALL_RESERVED; -} - -/** - * @brief Clears pin states that had a latched falling edge (FALL) state - * @param pPININT : The base address of Pin interrupt block - * @param pins : Pins with latched states to clear - * @return Nothing - */ -STATIC INLINE void Chip_PININT_ClearFallStates(LPC_PININT_T *pPININT, uint32_t pins) -{ - pPININT->FALL = pins; -} - -/** - * @brief Get interrupt status from Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @return Interrupt status (bit n for PININTn = high means interrupt ie pending) - */ -STATIC INLINE uint32_t Chip_PININT_GetIntStatus(LPC_PININT_T *pPININT) -{ - return pPININT->IST& ~PININT_IST_RESERVED; -} - -/** - * @brief Clear interrupt status in Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @param pins : Pin interrupts to clear (ORed value of PININTCH*) - * @return Nothing - */ -STATIC INLINE void Chip_PININT_ClearIntStatus(LPC_PININT_T *pPININT, uint32_t pins) -{ - pPININT->IST = pins; -} - -/** - * @brief Set source for pattern match in Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @param chan : PININT channel number (From 0 to 7) - * @param slice : PININT slice number - * @return Nothing - */ -void Chip_PININT_SetPatternMatchSrc(LPC_PININT_T *pPININT, uint8_t chan, Chip_PININT_BITSLICE_T slice); - -/** - * @brief Configure the pattern matcch in Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @param slice : PININT slice number - * @param slice_cfg : PININT slice configuration value (enum Chip_PININT_BITSLICE_CFG_T) - * @param end_point : If true, current slice is final component - * @return Nothing - */ -void Chip_PININT_SetPatternMatchConfig(LPC_PININT_T *pPININT, Chip_PININT_BITSLICE_T slice, - Chip_PININT_BITSLICE_CFG_T slice_cfg, bool end_point); - -/** - * @brief Enable pattern match interrupts in Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @return Nothing - */ -STATIC INLINE void Chip_PININT_EnablePatternMatch(LPC_PININT_T *pPININT) -{ - pPININT->PMCTRL = PININT_PMCTRL_PMATCH_SEL | (pPININT->PMCTRL & ~PININT_PMCTRL_RESERVED); -} - -/** - * @brief Disable pattern match interrupts in Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @return Nothing - */ -STATIC INLINE void Chip_PININT_DisablePatternMatch(LPC_PININT_T *pPININT) -{ - pPININT->PMCTRL &= ~(PININT_PMCTRL_PMATCH_SEL | PININT_PMCTRL_RESERVED); -} - -/** - * @brief Enable RXEV output in Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @return Nothing - */ -STATIC INLINE void Chip_PININT_EnablePatternMatchRxEv(LPC_PININT_T *pPININT) -{ - pPININT->PMCTRL = PININT_PMCTRL_RXEV_ENA | (pPININT->PMCTRL & ~PININT_PMCTRL_RESERVED); -} - -/** - * @brief Disable RXEV output in Pin interrupt block - * @param pPININT : The base address of Pin interrupt block - * @return Nothing - */ -STATIC INLINE void Chip_PININT_DisablePatternMatchRxEv(LPC_PININT_T *pPININT) -{ - pPININT->PMCTRL &= ~(PININT_PMCTRL_RXEV_ENA | PININT_PMCTRL_RESERVED); -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __PININT_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/pmu/pmu_8xx.c b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/pmu/pmu_8xx.c deleted file mode 100644 index e9924d42d20..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/pmu/pmu_8xx.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * @brief LPC8xx PMU chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/* Reserved bits mask for SCR register */ -#define SCB_SCR_RESERVED (~(SCB_SCR_SLEEPONEXIT_Msk|SCB_SCR_SLEEPDEEP_Msk|SCB_SCR_SEVONPEND_Msk)) - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Enter MCU Sleep mode */ -void Chip_PMU_SleepState(LPC_PMU_T *pPMU) -{ - SCB->SCR = ~(1UL << SCB_SCR_SLEEPDEEP_Pos) & (SCB->SCR & ~SCB_SCR_RESERVED); - pPMU->PCON = PMU_PCON_PM_SLEEP; - - /* Enter sleep mode */ - __WFI(); -} - -/* Enter MCU Deep Sleep mode */ -void Chip_PMU_DeepSleepState(LPC_PMU_T *pPMU) -{ - SCB->SCR = (1UL << SCB_SCR_SLEEPDEEP_Pos) | (SCB->SCR & ~SCB_SCR_RESERVED); - pPMU->PCON = PMU_PCON_PM_DEEPSLEEP; - - /* Enter sleep mode */ - __WFI(); -} - -/* Enter MCU Power down mode */ -void Chip_PMU_PowerDownState(LPC_PMU_T *pPMU) -{ - SCB->SCR = (1UL << SCB_SCR_SLEEPDEEP_Pos) | (SCB->SCR & ~SCB_SCR_RESERVED); - pPMU->PCON = PMU_PCON_PM_POWERDOWN; - - /* Enter sleep mode */ - __WFI(); -} - -/* Enter MCU Deep Power down mode */ -void Chip_PMU_DeepPowerDownState(LPC_PMU_T *pPMU) -{ - SCB->SCR = (1UL << SCB_SCR_SLEEPDEEP_Pos) | (SCB->SCR & ~SCB_SCR_RESERVED); - pPMU->PCON = PMU_PCON_PM_DEEPPOWERDOWN; - - /* Enter sleep mode */ - __WFI(); -} - -/* Put some of the peripheral in sleep mode */ -void Chip_PMU_Sleep(LPC_PMU_T *pPMU, CHIP_PMU_MCUPOWER_T SleepMode) -{ - if (SleepMode == PMU_MCU_DEEP_SLEEP) { - Chip_PMU_DeepSleepState(pPMU); - } - else if (SleepMode == PMU_MCU_POWER_DOWN) { - Chip_PMU_PowerDownState(pPMU); - } - else if (SleepMode == PMU_MCU_DEEP_PWRDOWN) { - Chip_PMU_DeepPowerDownState(pPMU); - } - else { - /* PMU_MCU_SLEEP */ - Chip_PMU_SleepState(pPMU); - } -} diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/pmu/pmu_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/pmu/pmu_8xx.h deleted file mode 100644 index 9498fa7adec..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/pmu/pmu_8xx.h +++ /dev/null @@ -1,237 +0,0 @@ -/* - * @brief LPC8xx PMU chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __PMU_8XX_H_ -#define __PMU_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup PMU_8XX CHIP: LPC8xx PMU driver - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/** - * @brief LPC8xx Power Management Unit register block structure - */ -typedef struct { - __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */ - __IO uint32_t GPREG[4]; /*!< Offset: 0x004 General purpose Registers 0..3 (R/W) */ - __IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */ -} LPC_PMU_T; - -/* Reserved bits masks for registers */ -#define PMU_PCON_RESERVED ((0xf<<4)|(0x6<<8)|0xfffff000) -#define PMU_DPDCTRL_RESERVED (~0xf) - -/** - * @brief LPC8xx low power mode type definitions - */ -typedef enum CHIP_PMU_MCUPOWER { - PMU_MCU_SLEEP = 0, /*!< Sleep mode */ - PMU_MCU_DEEP_SLEEP, /*!< Deep Sleep mode */ - PMU_MCU_POWER_DOWN, /*!< Power down mode */ - PMU_MCU_DEEP_PWRDOWN /*!< Deep power down mode */ -} CHIP_PMU_MCUPOWER_T; - -/** - * PMU PCON register bit fields & masks - */ -#define PMU_PCON_PM_SLEEP (0x0) /*!< ARM WFI enter sleep mode */ -#define PMU_PCON_PM_DEEPSLEEP (0x1) /*!< ARM WFI enter Deep-sleep mode */ -#define PMU_PCON_PM_POWERDOWN (0x2) /*!< ARM WFI enter Power-down mode */ -#define PMU_PCON_PM_DEEPPOWERDOWN (0x3) /*!< ARM WFI enter Deep Power-down mode */ -#define PMU_PCON_NODPD (1 << 3) /*!< Disable deep power-down mode */ -#define PMU_PCON_SLEEPFLAG (1 << 8) /*!< Sleep mode flag */ -#define PMU_PCON_DPDFLAG (1 << 11) /*!< Deep power-down flag */ - -/** - * PMU DPDCTRL register bit fields & masks - */ -#define PMU_DPDCTRL_WAKEUPPHYS (1 << 0) /** Enable wake-up pin hysteresis */ -#define PMU_DPDCTRL_WAKEPAD (1 << 1) /** Disable the Wake-up */ -#define PMU_DPDCTRL_LPOSCEN (1 << 2) /** Enable the low-power oscillator (10 khz self wk) */ -#define PMU_DPDCTRL_LPOSCDPDEN (1 << 3) /** Enable the low-power oscillator in deep power-down*/ - -/** - * @brief Write a value to a GPREG register - * @param pPMU : Pointer to PMU register block - * @param regIndex : Register index to write to, must be 0..3 - * @param value : Value to write - * @return None - */ -STATIC INLINE void Chip_PMU_WriteGPREG(LPC_PMU_T *pPMU, uint8_t regIndex, uint32_t value) -{ - pPMU->GPREG[regIndex] = value; -} - -/** - * @brief Read a value to a GPREG register - * @param pPMU : Pointer to PMU register block - * @param regIndex : Register index to read from, must be 0..3 - * @return Value read from the GPREG register - */ -STATIC INLINE uint32_t Chip_PMU_ReadGPREG(LPC_PMU_T *pPMU, uint8_t regIndex) -{ - return pPMU->GPREG[regIndex]; -} - -/** - * @brief Enter MCU Sleep mode - * @param pPMU : Pointer to PMU register block - * @return None - * @note The sleep mode affects the ARM Cortex-M0+ core only. Peripherals - * and memories are active. - */ -void Chip_PMU_SleepState(LPC_PMU_T *pPMU); - -/** - * @brief Enter MCU Deep Sleep mode - * @param pPMU : Pointer to PMU register block - * @return None - * @note In Deep-sleep mode, the peripherals receive no internal clocks. - * The flash is in stand-by mode. The SRAM memory and all peripheral registers - * as well as the processor maintain their internal states. The WWDT, WKT, - * and BOD can remain active to wake up the system on an interrupt. - */ -void Chip_PMU_DeepSleepState(LPC_PMU_T *pPMU); - -/** - * @brief Enter MCU Power down mode - * @param pPMU : Pointer to PMU register block - * @return None - * @note In Power-down mode, the peripherals receive no internal clocks. - * The internal SRAM memory and all peripheral registers as well as the - * processor maintain their internal states. The flash memory is powered - * down. The WWDT, WKT, and BOD can remain active to wake up the system - * on an interrupt. - */ -void Chip_PMU_PowerDownState(LPC_PMU_T *pPMU); - -/** - * @brief Enter MCU Deep Power down mode - * @param pPMU : Pointer to PMU register block - * @return None - * @note For maximal power savings, the entire system is shut down - * except for the general purpose registers in the PMU and the self - * wake-up timer. Only the general purpose registers in the PMU maintain - * their internal states. The part can wake up on a pulse on the WAKEUP - * pin or when the self wake-up timer times out. On wake-up, the part - * reboots. - */ -void Chip_PMU_DeepPowerDownState(LPC_PMU_T *pPMU); - -/** - * @brief Place the MCU in a low power state - * @param pPMU : Pointer to PMU register block - * @param SleepMode : Sleep mode - * @return None - */ -void Chip_PMU_Sleep(LPC_PMU_T *pPMU, CHIP_PMU_MCUPOWER_T SleepMode); - -/** - * @brief Disables deep power-down mode - * @param pPMU : Pointer to PMU register block - * @return None - * @note Calling this functions prevents entry to Deep power-down - * mode. Once set, this can only be cleared by power-on reset. - */ -STATIC INLINE void Chip_PMU_DisableDeepPowerDown(LPC_PMU_T *pPMU) -{ - pPMU->PCON = PMU_PCON_NODPD | (pPMU->PCON & ~PMU_PCON_RESERVED); -} - -/** - * @brief Returns sleep/power-down flags - * @param pPMU : Pointer to PMU register block - * @return Or'ed values of PMU_PCON_SLEEPFLAG and PMU_PCON_DPDFLAG - * @note These indicate that the PMU is setup for entry into a low - * power state on the next WFI() instruction. - */ -STATIC INLINE uint32_t Chip_PMU_GetSleepFlags(LPC_PMU_T *pPMU) -{ - return (pPMU->PCON & (PMU_PCON_SLEEPFLAG | PMU_PCON_DPDFLAG)); -} - -/** - * @brief Clears sleep/power-down flags - * @param pPMU : Pointer to PMU register block - * @param flags : Or'ed value of PMU_PCON_SLEEPFLAG and PMU_PCON_DPDFLAG - * @return Nothing - * @note Use this function to clear a low power state prior to calling - * WFI(). - */ -STATIC INLINE void Chip_PMU_ClearSleepFlags(LPC_PMU_T *pPMU, uint32_t flags) -{ - pPMU->PCON |= (flags & (~PMU_PCON_RESERVED)); -} - -/** - * @brief Sets deep power-down functions - * @param pPMU : Pointer to PMU register block - * @param flags : Or'ed value of PMU_DPDCTRL_* values - * @return Nothing - * @note Some of these functions may need to be set prior to going - * into a low power mode. Note that some calls to this function enable - * functions while others disable it based on the PMU_DPDCTRL_* - * definitions. - */ -STATIC INLINE void Chip_PMU_SetPowerDownControl(LPC_PMU_T *pPMU, uint32_t flags) -{ - pPMU->DPDCTRL = flags | (pPMU->DPDCTRL & ~PMU_DPDCTRL_RESERVED); -} - -/** - * @brief Cleats deep power-down functions - * @param pPMU : Pointer to PMU register block - * @param flags : Or'ed value of PMU_DPDCTRL_* values - * @return Nothing - * @note Some of these functions may need to be cleared prior to going - * into a low power mode. Note that some calls to this function enable - * functions while others disable it based on the PMU_DPDCTRL_* - * definitions. - */ -STATIC INLINE void Chip_PMU_ClearPowerDownControl(LPC_PMU_T *pPMU, uint32_t flags) -{ - pPMU->DPDCTRL &= ~(flags | PMU_DPDCTRL_RESERVED); -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __PMU_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/rom/rom_i2c_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/rom/rom_i2c_8xx.h deleted file mode 100644 index 4036345edfa..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/rom/rom_i2c_8xx.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * @brief LPC8xx I2C ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __ROM_I2C_8XX_H_ -#define __ROM_I2C_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup CHIP_I2CROM_8XX CHIP: LPC8xx I2C ROM API declarations and functions - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/** - * @brief LPC8xx I2C ROM driver handle structure - */ -typedef void *I2C_HANDLE_T; - -/** - * @brief LPC8xx I2C ROM driver callback function - */ -typedef void (*I2C_CALLBK_T)(uint32_t err_code, uint32_t n); - -/** - * LPC8xx I2C ROM driver parameter structure - */ -typedef struct I2C_PARAM { - uint32_t num_bytes_send; /*!< No. of bytes to send */ - uint32_t num_bytes_rec; /*!< No. of bytes to receive */ - uint8_t *buffer_ptr_send; /*!< Pointer to send buffer */ - uint8_t *buffer_ptr_rec; /*!< Pointer to receive buffer */ - I2C_CALLBK_T func_pt; /*!< Callback function */ - uint8_t stop_flag; /*!< Stop flag */ - uint8_t dummy[3]; -} I2C_PARAM_T; - -/** - * LPC8xx I2C ROM driver result structure - */ -typedef struct I2C_RESULT { - uint32_t n_bytes_sent; /*!< No. of bytes sent */ - uint32_t n_bytes_recd; /*!< No. of bytes received */ -} I2C_RESULT_T; - -/** - * LPC8xx I2C ROM driver modes enum - */ -typedef enum CHIP_I2C_MODE { - IDLE, /*!< IDLE state */ - MASTER_SEND, /*!< Master send state */ - MASTER_RECEIVE, /*!< Master Receive state */ - SLAVE_SEND, /*!< Slave send state */ - SLAVE_RECEIVE /*!< Slave receive state */ -} CHIP_I2C_MODE_T; - -/** - * LPC8xx I2C ROM driver APIs structure - */ -typedef struct I2CD_API { - /*!< Interrupt Support Routine */ - void (*i2c_isr_handler)(I2C_HANDLE_T *handle); - - /*!< MASTER functions */ - ErrorCode_t (*i2c_master_transmit_poll)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result); - ErrorCode_t (*i2c_master_receive_poll)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result); - ErrorCode_t (*i2c_master_tx_rx_poll)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result); - ErrorCode_t (*i2c_master_transmit_intr)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result); - ErrorCode_t (*i2c_master_receive_intr)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result); - ErrorCode_t (*i2c_master_tx_rx_intr)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result); - - /*!< SLAVE functions */ - ErrorCode_t (*i2c_slave_receive_poll)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result); - ErrorCode_t (*i2c_slave_transmit_poll)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result); - ErrorCode_t (*i2c_slave_receive_intr)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result); - ErrorCode_t (*i2c_slave_transmit_intr)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result); - ErrorCode_t (*i2c_set_slave_addr)(I2C_HANDLE_T *handle, uint32_t slave_addr_0_3, uint32_t slave_mask_0_3); - - /*!< OTHER support functions */ - uint32_t (*i2c_get_mem_size)(void); - I2C_HANDLE_T * (*i2c_setup)( uint32_t i2c_base_addr, uint32_t * start_of_ram); - ErrorCode_t (*i2c_set_bitrate)(I2C_HANDLE_T *handle, uint32_t p_clk_in_hz, uint32_t bitrate_in_bps); - uint32_t (*i2c_get_firmware_version)(void); - CHIP_I2C_MODE_T (*i2c_get_status)(I2C_HANDLE_T *handle); - ErrorCode_t (*i2c_set_timeout)(I2C_HANDLE_T *handle, uint32_t timeout); -} I2CD_API_T; - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ROM_I2C_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/rom/rom_pwr_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/rom/rom_pwr_8xx.h deleted file mode 100644 index 5d4d53f8604..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/rom/rom_pwr_8xx.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * @brief LPC8xx Power ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __ROM_PWR_8XX_H_ -#define __ROM_PWR_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup PWRD_8XX CHIP: LPC8xx Power ROM API declarations and functions - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/** - * @brief LPC8xx Power ROM APIs - set_pll mode options - */ -#define CPU_FREQ_EQU 0 -#define CPU_FREQ_LTE 1 -#define CPU_FREQ_GTE 2 -#define CPU_FREQ_APPROX 3 - -/** - * @brief LPC8xx Power ROM APIs - set_pll response0 options - */ -#define PLL_CMD_SUCCESS 0 -#define PLL_INVALID_FREQ 1 -#define PLL_INVALID_MODE 2 -#define PLL_FREQ_NOT_FOUND 3 -#define PLL_NOT_LOCKED 4 - -/** - * @brief LPC8xx Power ROM APIs - set_power mode options - */ -#define PWR_DEFAULT 0 -#define PWR_CPU_PERFORMANCE 1 -#define PWR_EFFICIENCY 2 -#define PWR_LOW_CURRENT 3 - -/** - * @brief LPC8xx Power ROM APIs - set_power response0 options - */ -#define PWR_CMD_SUCCESS 0 -#define PWR_INVALID_FREQ 1 -#define PWR_INVALID_MODE 2 - -/** - * @brief LPC8XX Power ROM API structure - */ -typedef struct PWRD_API { - void (*set_pll)(uint32_t cmd[], uint32_t resp[]); /*!< Set PLL function */ - void (*set_power)(uint32_t cmd[], uint32_t resp[]); /*!< Set power function */ -} PWRD_API_T; - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ROM_PWR_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/rom/rom_uart_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/rom/rom_uart_8xx.h deleted file mode 100644 index 2e78a3c159e..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/rom/rom_uart_8xx.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * @brief LPC8xx UART ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __ROM_UART_8XX_H_ -#define __ROM_UART_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup UARTROM_8XX CHIP: LPC8xx UART ROM API declarations and functions - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/** - * @brief UART ROM driver - UART errors in UART configuration used in uart_init function - */ -#define OVERRUN_ERR_EN (1 << 0) /*!< Bit 0: Enable overrun error */ -#define UNDERRUN_ERR_EN (1 << 1) /*!< Bit 1: Enable underrun error */ -#define FRAME_ERR_EN (1 << 2) /*!< Bit 2: enable frame error */ -#define PARITY_ERR_EN (1 << 3) /*!< Bit 3: enable parity error */ -#define RXNOISE_ERR_EN (1 << 4) /*!< Bit 4: enable receive noise error */ - -/** - * Macros for UART errors - */ -/*!< Enable all the UART errors */ -#define ALL_ERR_EN (OVERRUN_ERR_EN | UNDERRUN_ERR_EN | FRAME_ERR_EN | PARITY_ERR_EN | \ - RXNOISE_ERR_EN) -/*!< Disable all the errors */ -#define NO_ERR_EN (0) - -/** - * Transfer mode values in UART parameter structure. - * Used in uart_get_line & uart_put_line function - */ -/*!< 0x00: uart_get_line: stop transfer when the buffer is full */ -/*!< 0x00: uart_put_line: stop transfer when the buffer is empty */ -#define TX_MODE_BUF_EMPTY (0x00) -#define RX_MODE_BUF_FULL (0x00) -/*!< 0x01: uart_get_line: stop transfer when CRLF are received */ -/*!< 0x01: uart_put_line: transfer stopped after reaching \0 and CRLF is sent out after that */ -#define TX_MODE_SZERO_SEND_CRLF (0x01) -#define RX_MODE_CRLF_RECVD (0x01) -/*!< 0x02: uart_get_line: stop transfer when LF are received */ -/*!< 0x02: uart_put_line: transfer stopped after reaching \0. And LF is sent out after that */ -#define TX_MODE_SZERO_SEND_LF (0x02) -#define RX_MODE_LF_RECVD (0x02) -/*!< 0x03: uart_get_line: RESERVED */ -/*!< 0x03: uart_put_line: transfer stopped after reaching \0 */ -#define TX_MODE_SZERO (0x03) - -/** - * @brief UART ROM driver modes - */ -#define DRIVER_MODE_POLLING (0x00) /*!< Polling mode */ -#define DRIVER_MODE_INTERRUPT (0x01) /*!< Interrupt mode */ -#define DRIVER_MODE_DMA (0x02) /*!< DMA mode */ - -/** - * @brief UART ROM driver UART handle - */ -typedef void UART_HANDLE_T; - -/** - * @brief UART ROM driver UART callback function - */ -typedef void (*UART_CALLBK_T)(uint32_t err_code, uint32_t n); - -/** - * @brief UART ROM driver UART DMA callback function - */ -typedef void (*UART_DMA_REQ_T)(uint32_t src_adr, uint32_t dst_adr, uint32_t size); - -/** - * @brief UART ROM driver configutaion structure - */ -typedef struct { - uint32_t sys_clk_in_hz; /*!< main clock in Hz */ - uint32_t baudrate_in_hz; /*!< Baud rate in Hz */ - uint8_t config; /*!< Configuration value */ - /*!< bit1:0 Data Length: 00: 7 bits length, 01: 8 bits length, others: reserved */ - /*!< bit3:2 Parity: 00: No Parity, 01: reserved, 10: Even, 11: Odd */ - /*!< bit4: Stop Bit(s): 0: 1 Stop bit, 1: 2 Stop bits */ - uint8_t sync_mod; /*!< Sync mode settings */ - /*!< bit0: Mode: 0: Asynchronous mode, 1: Synchronous mode */ - /*!< bit1: 0: Un_RXD is sampled on the falling edge of SCLK */ - /*!< 1: Un_RXD is sampled on the rising edge of SCLK */ - /*!< bit2: 0: Start and stop bits are transmitted as in asynchronous mode) */ - /*!< 1: Start and stop bits are not transmitted) */ - /*!< bit3: 0: The UART is a slave in Synchronous mode */ - /*!< 1: The UART is a master in Synchronous mode */ - uint16_t error_en; /*!< Errors to be enabled */ - /*!< bit0: Overrun Errors Enabled */ - /*!< bit1: Underrun Errors Enabled */ - /*!< bit2: FrameErr Errors Enabled */ - /*!< bit3: ParityErr Errors Enabled */ - /*!< bit4: RxNoise Errors Enabled */ -} UART_CONFIG_T; - -/** - * @brief UART ROM driver parameter structure - */ -typedef struct { - uint8_t *buffer; /*!< Pointer to data buffer */ - uint32_t size; /*!< Size of the buffer */ - uint16_t transfer_mode; /*!< Transfer mode settings */ - /*!< 0x00: uart_get_line: stop transfer when the buffer is full */ - /*!< 0x00: uart_put_line: stop transfer when the buffer is empty */ - /*!< 0x01: uart_get_line: stop transfer when CRLF are received */ - /*!< 0x01: uart_put_line: transfer stopped after reaching \0 and CRLF is sent out after that */ - /*!< 0x02: uart_get_line: stop transfer when LF are received */ - /*!< 0x02: uart_put_line: transfer stopped after reaching \0 and LF is sent out after that */ - /*!< 0x03: uart_get_line: RESERVED */ - /*!< 0x03: uart_put_line: transfer stopped after reaching \0 */ - uint16_t driver_mode; /*!< Driver mode */ - /*!< 0x00: Polling mode, function blocked until transfer completes */ - /*!< 0x01: Interrupt mode, function immediately returns, callback invoked when transfer completes */ - /*!< 0x02: DMA mode, in case DMA block is available, DMA req function is called for UART DMA channel setup, then callback function indicate that transfer completes */ - UART_CALLBK_T callback_func_pt; /*!< callback function pointer */ - UART_DMA_REQ_T dma_req_func_pt; /*!< UART DMA channel setup function pointer, not applicable on LPC8xx */ -} UART_PARAM_T; - -/** - * @brief UART ROM driver APIs structure - */ -typedef struct UARTD_API { - /*!< UART Configuration functions */ - uint32_t (*uart_get_mem_size)(void); /*!< Get the memory size needed by one Min UART instance */ - UART_HANDLE_T * (*uart_setup)(uint32_t base_addr, uint8_t * ram); /*!< Setup Min UART instance with provided memory and return the handle to this instance */ - uint32_t (*uart_init)(UART_HANDLE_T *handle, UART_CONFIG_T *set); /*!< Setup baud rate and operation mode for uart, then enable uart */ - - /*!< UART polling functions block until completed */ - uint8_t (*uart_get_char)(UART_HANDLE_T *handle); /*!< Receive one Char from uart. This functions is only returned after Char is received. In case Echo is enabled, the received data is sent out immediately */ - void (*uart_put_char)(UART_HANDLE_T *handle, uint8_t data); /*!< Send one Char through uart. This function is only returned after data is sent */ - uint32_t (*uart_get_line)(UART_HANDLE_T *handle, UART_PARAM_T *param); /*!< Receive multiple bytes from UART */ - uint32_t (*uart_put_line)(UART_HANDLE_T *handle, UART_PARAM_T *param); /*!< Send string (end with \0) or raw data through UART */ - - /*!< UART interrupt functions return immediately and callback when completed */ - void (*uart_isr)(UART_HANDLE_T *handle); /*!< UART interrupt service routine. To use this routine, the corresponding USART interrupt must be enabled. This function is invoked by the user ISR */ -} UARTD_API_T; - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ROM_UART_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/rom/romapi_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/rom/romapi_8xx.h deleted file mode 100644 index 53c24806cbb..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/rom/romapi_8xx.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * @brief LPC8xx ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __ROMAPI_8XX_H_ -#define __ROMAPI_8XX_H_ - -#include "../iap/iap.h" -#include "../../common/chip/error_8xx.h" -#include "rom_i2c_8xx.h" -#include "rom_pwr_8xx.h" -#include "rom_uart_8xx.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup ROMAPI_8XX CHIP: LPC8xx ROM API declarations and functions - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/** - * @brief LPC8XX High level ROM API structure - */ -typedef struct ROM_API { - const uint32_t unused[3]; - const PWRD_API_T *pPWRD; /*!< Power profiles API function table */ - const uint32_t p_dev1; - const I2CD_API_T *pI2CD; /*!< I2C driver routines functions table */ - const uint32_t p_dev3; - const uint32_t p_dev4; - const uint32_t p_dev5; - const UARTD_API_T *pUARTD; /*!< UART driver routines function table */ -} LPC_ROM_API_T; - -/* Pointer to ROM API function address */ -#define LPC_ROM_API_BASE_LOC 0x1FFF1FF8UL -#define LPC_ROM_API (*(LPC_ROM_API_T * *) LPC_ROM_API_BASE_LOC) - -/* Pointer to @ref PWRD_API_T functions in ROM */ -#define LPC_PWRD_API ((LPC_ROM_API)->pPWRD) - -/* Pointer to @ref I2CD_API_T functions in ROM */ -#define LPC_I2CD_API ((LPC_ROM_API)->pI2CD) - -/* Pointer to @ref UARTD_API_T functions in ROM */ -#define LPC_UARTD_API ((LPC_ROM_API)->pUARTD) - -/* Pointer to ROM IAP entry functions */ -#define IAP_ENTRY_LOCATION 0X1FFF1FF1UL - -/** - * @brief LPC8XX IAP_ENTRY API function type - */ -static INLINE void iap_entry(unsigned int cmd_param[], unsigned int status_result[]) -{ - ((IAP_ENTRY_T) IAP_ENTRY_LOCATION)(cmd_param, status_result); -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ROMAPI_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/sctimer/sct_8xx.c b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/sctimer/sct_8xx.c deleted file mode 100644 index 42e20c95489..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/sctimer/sct_8xx.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * @brief LPC8xx State Configurable Timer driver - * - * @note - * Copyright(C) NXP Semiconductors, 2013 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Initialize SCT */ -void Chip_SCT_Init(LPC_SCT_T *pSCT) -{ - Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SCT); - Chip_SYSCTL_PeriphReset(RESET_SCT); -} - -/* Shutdown SCT */ -void Chip_SCT_DeInit(LPC_SCT_T *pSCT) -{ - Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SCT); -} - -/* Set/Clear SCT control register */ -void Chip_SCT_SetClrControl(LPC_SCT_T *pSCT, uint32_t value, FunctionalState ena) -{ - if (ena == ENABLE) { - Chip_SCT_SetControl(pSCT, value); - } - else { - Chip_SCT_ClearControl(pSCT, value); - } -} - -/* Set Conflict resolution */ -void Chip_SCT_SetConflictResolution(LPC_SCT_T *pSCT, uint8_t outnum, uint8_t value) -{ - uint32_t tem; - - tem = pSCT->RES & ~((0x03 << (2 * outnum))|SCT_RES_RESERVED); - pSCT->RES = tem | (value << (2 * outnum)); -} diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/sctimer/sct_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/sctimer/sct_8xx.h deleted file mode 100644 index e9a120c5234..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/sctimer/sct_8xx.h +++ /dev/null @@ -1,458 +0,0 @@ -/* - * @brief LPC8xx State Configurable Timer (SCT) Chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2013 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __SCT_8XX_H_ -#define __SCT_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup SCT_8XX CHIP: LPC8xx State Configurable Timer driver - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/* - * @brief SCT Module configuration - */ -#define CONFIG_SCT_nEV (8) /*!< Number of events */ -#define CONFIG_SCT_nRG (8) /*!< Number of match/compare registers */ -#define CONFIG_SCT_nOU (6) /*!< Number of outputs */ - -/** - * @brief State Configurable Timer register block structure - */ -typedef struct { - __IO uint32_t CONFIG; /*!< configuration Register (offset (0x000) */ - union { - __IO uint32_t CTRL_U; /*!< control Register */ - struct { - __IO uint16_t CTRL_L; /*!< low control register */ - __IO uint16_t CTRL_H; /*!< high control register */ - }; - }; - union { - __IO uint32_t LIMIT_U; /*!< limit Register */ - struct { - __IO uint16_t LIMIT_L; /*!< limit register for counter L */ - __IO uint16_t LIMIT_H; /*!< limit register for counter H */ - }; - }; - - union { - __IO uint32_t HALT_U; /*!< halt Register */ - struct { - __IO uint16_t HALT_L; /*!< halt register for counter L */ - __IO uint16_t HALT_H; /*!< halt register for counter H */ - }; - }; - - union { - __IO uint32_t STOP_U; /*!< stop Register */ - struct { - __IO uint16_t STOP_L; /*!< stop register for counter L */ - __IO uint16_t STOP_H; /*!< stop register for counter H */ - }; - - }; - - union { - __IO uint32_t START_U; /*!< start Register */ - struct { - __IO uint16_t START_L; /*!< start register for counter L */ - __IO uint16_t START_H; /*!< start register for counter H */ - }; - - }; - - uint32_t RESERVED1[10]; /*!< 0x018 - 0x03C reserved */ - - union { - __IO uint32_t COUNT_U; /*!< counter register (offset 0x040)*/ - struct { - __IO uint16_t COUNT_L; /*!< counter register for counter L */ - __IO uint16_t COUNT_H; /*!< counter register for counter H */ - }; - }; - - union { - __IO uint32_t STATE_U; /*!< State register */ - struct { - __IO uint16_t STATE_L; /*!< state register for counter L */ - __IO uint16_t STATE_H; /*!< state register for counter H */ - }; - }; - - __I uint32_t INPUT; /*!< input register */ - union { - __IO uint32_t REGMODE_U; /*!< RegMode register */ - struct { - __IO uint16_t REGMODE_L; /*!< match - capture registers mode register L */ - __IO uint16_t REGMODE_H; /*!< match - capture registers mode register H */ - }; - }; - - __IO uint32_t OUTPUT; /*!< output register */ - __IO uint32_t OUTPUTDIRCTRL; /*!< output counter direction Control Register */ - __IO uint32_t RES; /*!< conflict resolution register */ - __IO uint32_t DMAREQ0; /*!< DMA0 Request Register */ - __IO uint32_t DMAREQ1; /*!< DMA1 Request Register */ - - uint32_t RESERVED2[35]; /*!< 0x064 - 0x0EC reserved */ - - __IO uint32_t EVEN; /*!< event enable register (offset 0x0F0)*/ - __IO uint32_t EVFLAG; /*!< event flag register */ - __IO uint32_t CONEN; /*!< conflict enable register */ - __IO uint32_t CONFLAG; /*!< conflict flag register */ - union { - __IO union { /*!< ... Match / Capture value */ - uint32_t U; /*!< MATCH[i].U Unified 32-bit register */ - struct { - uint16_t L; /*!< MATCH[i].L Access to L value */ - uint16_t H; /*!< MATCH[i].H Access to H value */ - }; - } MATCH[CONFIG_SCT_nRG]; - - __I union { - uint32_t U; /*!< CAP[i].U Unified 32-bit register */ - struct { - uint16_t L; /*!< CAP[i].L Access to L value */ - uint16_t H; /*!< CAP[i].H Access to H value */ - }; - } CAP[CONFIG_SCT_nRG]; - }; - - uint32_t RESERVED3[56]; /*!< 0x120 - 0x1FC reserved */ - - union { - __IO union { /*!< ...Match Reload / Capture Control value (offset 0x200) */ - uint32_t U; /*!< MATCHREL[i].U Unified 32-bit register */ - struct { - uint16_t L; /*!< MATCHREL[i].L Access to L value */ - uint16_t H; /*!< MATCHREL[i].H Access to H value */ - }; - } MATCHREL[CONFIG_SCT_nRG]; - - __IO union { - uint32_t U; /*!< CAPCTRL[i].U Unified 32-bit register */ - struct { - uint16_t L; /*!< CAPCTRL[i].L Access to L value */ - uint16_t H; /*!< CAPCTRL[i].H Access to H value */ - }; - } CAPCTRL[CONFIG_SCT_nRG]; - }; - - uint32_t RESERVED4[56]; /*!< 0x220 - 0x2FC reserved */ - - __IO struct { /*!< EV[i].STATE / EV[i].CTRL (offset 0x300) */ - uint32_t STATE; /*!< Event State Register */ - uint32_t CTRL; /*!< Event Control Register */ - } EV[CONFIG_SCT_nEV]; - - uint32_t RESERVED5[112]; /*!< 0x340 - 0x4FC reserved */ - - __IO struct { /*!< OUT[i].SET / OUT[i].CLR (offset 0x500) */ - uint32_t SET; /*!< Output n Set Register */ - uint32_t CLR; /*!< Output n Clear Register */ - } OUT[CONFIG_SCT_nOU]; - -} LPC_SCT_T; - -/* Reserved bits masks for registers */ -#define SCT_CONFIG_RESERVED 0xfff80000 -#define SCT_CTRL_RESERVED ((7<<13)|(7u<<29)) -#define SCT_LIMIT_RESERVED (~(0x3f|(0x3f<<16)) -#define SCT_HALT_RESERVED (~(0x3f|(0x3f<<16)) -#define SCT_STOP_RESERVED (~(0x3f|(0x3f<<16)) -#define SCT_START_RESERVED (~(0x3f|(0x3f<<16)) -#define SCT_STATE_RESERVED (~(0x1f|(0x1f<<16)) -#define SCT_INPUT_RESERVED (~(0xf|(0xf<<16)) -#define SCT_REGMODE_RESERVED (~(0x1f|(0x1f<<16)) -#define SCT_OUTPUT_RESERVED (~0xf) -#define SCT_OUTPUTDIRCTRL_RESERVED (~0xff) -#define SCT_RES_RESERVED (~0xff) -#define SCT_EVEN_RESERVED (~0x3f) -#define SCT_EVFLAG_RESERVED (~0x3f) -#define SCT_CONEN_RESERVED (~0xf) -#define SCT_CONFLAG_RESERVED (~(0xf|(3u<<30))) -#define SCT_CAPCTRL_RESERVED (~(0x3f|(0x3f<<16))) -#define SCT_EVn_STATE_RESERVED (~3) -#define SCT_EVn_CTRL_RESERVED (0xff800000) -#define SCT_OUTn_SET_RESERVED (~0x3f) -#define SCT_OUTn_CLR_RESERVED (~0x3f) - -/* - * @brief Macro defines for SCT configuration register - */ -#define SCT_CONFIG_16BIT_COUNTER 0x00000000 /*!< Operate as 2 16-bit counters */ -#define SCT_CONFIG_32BIT_COUNTER 0x00000001 /*!< Operate as 1 32-bit counter */ - -#define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /*!< Bus clock */ -#define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /*!< SCT clock */ -#define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /*!< Input clock selected in CLKSEL field */ -#define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /*!< Input clock edge selected in CLKSEL field */ - -#define SCT_CONFIG_NORELOAD_U (0x1 << 7) /*!< Prevent match register reload */ -#define SCT_CONFIG_NORELOAD_L (0x1 << 7) /*!< Prevent lower match register reload */ -#define SCT_CONFIG_NORELOAD_H (0x1 << 8) /*!< Prevent upper match register reload */ - -#define SCT_CONFIG_AUTOLIMIT_U (0x1 << 17) /*!< Limits counter(unified) based on MATCH0 */ -#define SCT_CONFIG_AUTOLIMIT_L (0x1 << 17) /*!< Limits counter(L) based on MATCH0 */ -#define SCT_CONFIG_AUTOLIMIT_H (0x1 << 18) /*!< Limits counter(L) based on MATCH0 */ - -/* - * @brief Macro defines for SCT control register - */ -#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /*!< Direction for low or unified counter */ -#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1 - -#define SCT_CTRL_STOP_L (1 << 1) /*!< Stop low counter */ -#define SCT_CTRL_HALT_L (1 << 2) /*!< Halt low counter */ -#define SCT_CTRL_CLRCTR_L (1 << 3) /*!< Clear low or unified counter */ -#define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /*!< Bidirectional bit */ -#define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /*!< Prescale clock for low or unified counter */ - -#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /*!< Direction for high counter */ -#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1 -#define SCT_CTRL_STOP_H (1 << 17) /*!< Stop high counter */ -#define SCT_CTRL_HALT_H (1 << 18) /*!< Halt high counter */ -#define SCT_CTRL_CLRCTR_H (1 << 19) /*!< Clear high counter */ -#define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20) -#define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /*!< Prescale clock for high counter */ - -/* - * @brief Macro defines for SCT Conflict resolution register - */ -#define SCT_RES_NOCHANGE (0) -#define SCT_RES_SET_OUTPUT (1) -#define SCT_RES_CLEAR_OUTPUT (2) -#define SCT_RES_TOGGLE_OUTPUT (3) - -/** - * SCT Match register values enum - */ -typedef enum CHIP_SCT_MATCH_REG { - SCT_MATCH_0 = 0, /*!< SCT Match register 0 */ - SCT_MATCH_1 = 1, /*!< SCT Match register 1 */ - SCT_MATCH_2 = 2, /*!< SCT Match register 2 */ - SCT_MATCH_3 = 3, /*!< SCT Match register 3 */ - SCT_MATCH_4 = 4 /*!< SCT Match register 4 */ -} CHIP_SCT_MATCH_REG_T; - -/** - * SCT Event values enum - */ -typedef enum CHIP_SCT_EVENT { - SCT_EVT_0 = (1 << 0), /*!< Event 0 */ - SCT_EVT_1 = (1 << 1), /*!< Event 1 */ - SCT_EVT_2 = (1 << 2), /*!< Event 2 */ - SCT_EVT_3 = (1 << 3), /*!< Event 3 */ - SCT_EVT_4 = (1 << 4) /*!< Event 4 */ -} CHIP_SCT_EVENT_T; - -/** - * @brief Configures the State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @param value : The 32-bit CONFIG register value - * @return Nothing - */ -STATIC INLINE void Chip_SCT_Config(LPC_SCT_T *pSCT, uint32_t value) -{ - pSCT->CONFIG = value; -} - -/** - * @brief Set or Clear the Control register - * @param pSCT : Pointer to SCT register block - * @param value : SCT Control register value - * @param ena : ENABLE - To set the fields specified by value - * : DISABLE - To clear the field specified by value - * @return Nothing - * Set or clear the control register bits as specified by the \a value - * parameter. If \a ena is set to ENABLE, the mentioned register fields - * will be set. If \a ena is set to DISABLE, the mentioned register - * fields will be cleared - */ -void Chip_SCT_SetClrControl(LPC_SCT_T *pSCT, uint32_t value, FunctionalState ena); - -/** - * @brief Set the conflict resolution - * @param pSCT : Pointer to SCT register block - * @param outnum : Output number - * @param value : Output value - * - SCT_RES_NOCHANGE :No change - * - SCT_RES_SET_OUTPUT :Set output - * - SCT_RES_CLEAR_OUTPUT :Clear output - * - SCT_RES_TOGGLE_OUTPUT :Toggle output - * : SCT_RES_NOCHANGE - * : DISABLE - To clear the field specified by value - * @return Nothing - * Set conflict resolution for the output \a outnum - */ -void Chip_SCT_SetConflictResolution(LPC_SCT_T *pSCT, uint8_t outnum, uint8_t value); - -/** - * @brief Set unified count value in State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @param count : The 32-bit count value - * @return Nothing - */ -STATIC INLINE void Chip_SCT_SetCount(LPC_SCT_T *pSCT, uint32_t count) -{ - pSCT->COUNT_U = count; -} - -/** - * @brief Set lower count value in State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @param count : The 16-bit count value - * @return Nothing - */ -STATIC INLINE void Chip_SCT_SetCountL(LPC_SCT_T *pSCT, uint16_t count) -{ - pSCT->COUNT_L = count; -} - -/** - * @brief Set higher count value in State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @param count : The 16-bit count value - * @return Nothing - */ -STATIC INLINE void Chip_SCT_SetCountH(LPC_SCT_T *pSCT, uint16_t count) -{ - pSCT->COUNT_H = count; -} - -/** - * @brief Set unified match count value in State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @param n : Match register value - * @param value : The 32-bit match count value - * @return Nothing - */ -STATIC INLINE void Chip_SCT_SetMatchCount(LPC_SCT_T *pSCT, CHIP_SCT_MATCH_REG_T n, uint32_t value) -{ - pSCT->MATCH[n].U = value; -} - -/** - * @brief Set unified match reload count value in State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @param n : Match register value - * @param value : The 32-bit match count reload value - * @return Nothing - */ -STATIC INLINE void Chip_SCT_SetMatchReload(LPC_SCT_T *pSCT, CHIP_SCT_MATCH_REG_T n, uint32_t value) -{ - pSCT->MATCHREL[n].U = value; -} - -/** - * @brief Enable the interrupt for the specified event in State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @param evt : Event value - * @return Nothing - */ -STATIC INLINE void Chip_SCT_EnableEventInt(LPC_SCT_T *pSCT, CHIP_SCT_EVENT_T evt) -{ - pSCT->EVEN = evt | (pSCT->EVEN & ~SCT_EVEN_RESERVED); -} - -/** - * @brief Disable the interrupt for the specified event in State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @param evt : Event value - * @return Nothing - */ -STATIC INLINE void Chip_SCT_DisableEventInt(LPC_SCT_T *pSCT, CHIP_SCT_EVENT_T evt) -{ - pSCT->EVEN &= ~(evt | SCT_EVEN_RESERVED); -} - -/** - * @brief Clear the specified event flag in State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @param evt : Event value - * @return Nothing - */ -STATIC INLINE void Chip_SCT_ClearEventFlag(LPC_SCT_T *pSCT, CHIP_SCT_EVENT_T evt) -{ - pSCT->EVFLAG = evt | (pSCT->EVFLAG & ~SCT_EVFLAG_RESERVED); -} - -/** - * @brief Set control register in State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @param value : Value (ORed value of SCT_CTRL_* bits) - * @return Nothing - */ -STATIC INLINE void Chip_SCT_SetControl(LPC_SCT_T *pSCT, uint32_t value) -{ - pSCT->CTRL_U = value | (pSCT->CTRL_U & ~SCT_CTRL_RESERVED); -} - -/** - * @brief Clear control register in State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @param value : Value (ORed value of SCT_CTRL_* bits) - * @return Nothing - */ -STATIC INLINE void Chip_SCT_ClearControl(LPC_SCT_T *pSCT, uint32_t value) -{ - pSCT->CTRL_U &= ~(value | SCT_CTRL_RESERVED); -} - -/** - * @brief Initializes the State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @return Nothing - */ -void Chip_SCT_Init(LPC_SCT_T *pSCT); - -/** - * @brief Deinitializes the State Configurable Timer - * @param pSCT : The base of SCT peripheral on the chip - * @return Nothing - */ -void Chip_SCT_DeInit(LPC_SCT_T *pSCT); - -/** - * @} - */ - -#ifdef __cplusplus -} - -#endif - -#endif /* __SCT_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/sctimer/sct_pwm_8xx.c b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/sctimer/sct_pwm_8xx.c deleted file mode 100644 index 4c6921bcaf8..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/sctimer/sct_pwm_8xx.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * @brief LPC8xx State Configurable Timer driver - * - * @note - * Copyright(C) NXP Semiconductors, 2013 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Setup the OUTPUT pin corresponding to the PWM index */ -void Chip_SCTPWM_SetOutPin(LPC_SCT_T *pSCT, uint8_t index, uint8_t pin) -{ - int ix = (int) index; - pSCT->EV[ix].CTRL = index | (1 << 12); - pSCT->EV[ix].STATE = 1; - pSCT->OUT[pin].SET = 1; - pSCT->OUT[pin].CLR = 1 << ix; - - /* Clear the output in-case of conflict */ - pSCT->RES = (pSCT->RES & ~(3 << (pin << 1))) | (0x01 << (pin << 1)); - - /* Set and Clear do not depend on direction */ - pSCT->OUTPUTDIRCTRL = (pSCT->OUTPUTDIRCTRL & ~((3 << (pin << 1))|SCT_OUTPUTDIRCTRL_RESERVED)); -} - -/* Set the PWM frequency */ -void Chip_SCTPWM_SetRate(LPC_SCT_T *pSCT, uint32_t freq) -{ - uint32_t rate; - - rate = Chip_Clock_GetSystemClockRate() / freq;; - - /* Stop the SCT before configuration */ - Chip_SCTPWM_Stop(pSCT); - - /* Set MATCH0 for max limit */ - pSCT->REGMODE_U = 0; - Chip_SCT_SetMatchCount(pSCT, SCT_MATCH_0, 0); - Chip_SCT_SetMatchReload(pSCT, SCT_MATCH_0, rate); - pSCT->EV[0].CTRL = 1 << 12; - pSCT->EV[0].STATE = 1; - - /* Set SCT Counter to count 32-bits and reset to 0 after reaching MATCH0 */ - Chip_SCT_Config(pSCT, SCT_CONFIG_32BIT_COUNTER | SCT_CONFIG_AUTOLIMIT_L); -} diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/sctimer/sct_pwm_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/sctimer/sct_pwm_8xx.h deleted file mode 100644 index 04245df7550..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/sctimer/sct_pwm_8xx.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * @brief LPC8xx State Configurable Timer (SCT/PWM) Chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2013 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __SCT_PWM_8XX_H_ -#define __SCT_PWM_8XX_H_ -#include "sct_8xx.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup SCT_PWM_8XX CHIP: LPC15XX State Configurable Timer PWM driver - * - * For more information on how to use the driver please visit the FAQ page at - * - * www.lpcware.com - * - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/** - * @brief Get number of ticks per PWM cycle - * @param pSCT : The base of SCT peripheral on the chip - * @return Number ot ticks that will be counted per cycle - * @note Return value of this function will be vaild only - * after calling Chip_SCTPWM_SetRate() - */ -STATIC INLINE uint32_t Chip_SCTPWM_GetTicksPerCycle(LPC_SCT_T *pSCT) -{ - return pSCT->MATCHREL[0].U; -} - -/** - * @brief Converts a percentage to ticks - * @param pSCT : The base of SCT peripheral on the chip - * @param percent : Percentage to convert (0 - 100) - * @return Number ot ticks corresponding to given percentage - * @note Do not use this function when using very low - * pwm rate (like 100Hz or less), on a chip that has - * very high frequency as the calculation might - * cause integer overflow - */ -STATIC INLINE uint32_t Chip_SCTPWM_PercentageToTicks(LPC_SCT_T *pSCT, uint8_t percent) -{ - return (Chip_SCTPWM_GetTicksPerCycle(pSCT) * percent) / 100; -} - -/** - * @brief Get number of ticks on per PWM cycle - * @param pSCT : The base of SCT peripheral on the chip - * @param index : Index of the PWM 1 to N (see notes) - * @return Number ot ticks for which the output will be ON per cycle - * @note @a index will be 1 to N where N is the "Number of - * match registers available in the SCT - 1" or - * "Number of OUTPUT pins available in the SCT" whichever - * is minimum. - */ -STATIC INLINE uint32_t Chip_SCTPWM_GetDutyCycle(LPC_SCT_T *pSCT, uint8_t index) -{ - return pSCT->MATCHREL[index].U; -} - -/** - * @brief Get number of ticks on per PWM cycle - * @param pSCT : The base of SCT peripheral on the chip - * @param index : Index of the PWM 1 to N (see notes) - * @param ticks : Number of ticks the output should say ON - * @return None - * @note @a index will be 1 to N where N is the "Number of - * match registers available in the SCT - 1" or - * "Number of OUTPUT pins available in the SCT" whichever - * is minimum. The new duty cycle will be effective only - * after completion of current PWM cycle. - */ -STATIC INLINE void Chip_SCTPWM_SetDutyCycle(LPC_SCT_T *pSCT, uint8_t index, uint32_t ticks) -{ - Chip_SCT_SetMatchReload(pSCT, (CHIP_SCT_MATCH_REG_T)index, ticks); -} - -/** - * @brief Initialize the SCT/PWM clock and reset - * @param pSCT : The base of SCT peripheral on the chip - * @return None - */ -STATIC INLINE void Chip_SCTPWM_Init(LPC_SCT_T *pSCT) -{ - Chip_SCT_Init(pSCT); -} - -/** - * @brief Start the SCT PWM - * @param pSCT : The base of SCT peripheral on the chip - * @return None - * @note This function must be called after all the - * configuration is completed. Do not call Chip_SCTPWM_SetRate() - * or Chip_SCTPWM_SetOutPin() after the SCT/PWM is started. Use - * Chip_SCTPWM_Stop() to stop the SCT/PWM before reconfiguring, - * Chip_SCTPWM_SetDutyCycle() can be called when the SCT/PWM is - * running to change the DutyCycle. - */ -STATIC INLINE void Chip_SCTPWM_Start(LPC_SCT_T *pSCT) -{ - Chip_SCT_ClearControl(pSCT, SCT_CTRL_HALT_L | SCT_CTRL_HALT_H); -} - -/** - * @brief Stop the SCT PWM - * @param pSCT : The base of SCT peripheral on the chip - * @return None - */ -STATIC INLINE void Chip_SCTPWM_Stop(LPC_SCT_T *pSCT) -{ - /* Stop SCT */ - Chip_SCT_SetControl(pSCT, SCT_CTRL_HALT_L | SCT_CTRL_HALT_H); - - /* Clear the counter */ - Chip_SCT_SetControl(pSCT, SCT_CTRL_CLRCTR_L | SCT_CTRL_CLRCTR_H); -} - -/** - * @brief Sets the frequency of the generated PWM wave - * @param pSCT : The base of SCT peripheral on the chip - * @param freq : Frequency in Hz - * @return None - */ -void Chip_SCTPWM_SetRate(LPC_SCT_T *pSCT, uint32_t freq); - -/** - * @brief Setup the OUTPUT pin and associate it with an index - * @param pSCT : The base of the SCT peripheral on the chip - * @param index : Index of PWM 1 to N (see notes) - * @param pin : COUT pin to be associated with the index - * @return None - * @note @a index will be 1 to N where N is the "Number of - * match registers available in the SCT - 1" or - * "Number of OUTPUT pins available in the SCT" whichever - * is minimum. - */ -void Chip_SCTPWM_SetOutPin(LPC_SCT_T *pSCT, uint8_t index, uint8_t pin); - -/** - * @} - */ - -#ifdef __cplusplus -} - -#endif - -#endif /* __SCT_PWM_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/spi/spi_8xx.c b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/spi/spi_8xx.c deleted file mode 100644 index 31fe59b3785..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/spi/spi_8xx.c +++ /dev/null @@ -1,550 +0,0 @@ -/* - * @brief LPC8xx SPI driver - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ -static volatile bool xmitOn; -static volatile bool deasserted; -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -STATIC void SPI_Send_Data_RxIgnore(LPC_SPI_T *pSPI, - SPI_DATA_SETUP_T *pXfSetup) -{ - if (pXfSetup->TxCnt == (pXfSetup->Length - 1)) { - Chip_SPI_SendLastFrame_RxIgnore(pSPI, pXfSetup->pTx[pXfSetup->TxCnt], pXfSetup->DataSize); - } - else { - Chip_SPI_SendMidFrame(pSPI, pXfSetup->pTx[pXfSetup->TxCnt]); - } - - pXfSetup->TxCnt++; -} - -STATIC void SPI_Send_Data(LPC_SPI_T *pSPI, - SPI_DATA_SETUP_T *pXfSetup) -{ - if (pXfSetup->TxCnt == (pXfSetup->Length - 1)) { - Chip_SPI_SendLastFrame(pSPI, pXfSetup->pTx[pXfSetup->TxCnt], pXfSetup->DataSize); - } - else { - Chip_SPI_SendMidFrame(pSPI, pXfSetup->pTx[pXfSetup->TxCnt]); - } - - pXfSetup->TxCnt++; -} - -STATIC void SPI_Send_Dummy(LPC_SPI_T *pSPI, - SPI_DATA_SETUP_T *pXfSetup) -{ - if (pXfSetup->RxCnt == (pXfSetup->Length - 1)) { - Chip_SPI_SendLastFrame(pSPI, 0x55, pXfSetup->DataSize); - } - else { - Chip_SPI_SendMidFrame(pSPI, 0x55); - } -} - -STATIC void SPI_Receive_Data(LPC_SPI_T *pSPI, - SPI_DATA_SETUP_T *pXfSetup) -{ - pXfSetup->pRx[pXfSetup->RxCnt] = Chip_SPI_ReceiveFrame(pSPI); - pXfSetup->RxCnt++; -} - -/* Determine SSEL associated with the current data value */ -STATIC uint8_t Chip_SPIS_FindSSEL(LPC_SPI_T *pSPI, uint32_t data) -{ - int i; - uint8_t ssel = 0; - - for (i = 0; i <= 3; i++) { - if ((data & SPI_RXDAT_RXSSELNUM_INACTIVE(i)) == 0) { - /* Signal is active on low */ - ssel = (uint8_t) i; - } - } - - return ssel; -} - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Calculate the Clock Rate Divider for SPI Peripheral */ -uint32_t Chip_SPI_CalClkRateDivider(LPC_SPI_T *pSPI, uint32_t bitRate) -{ - uint32_t SPIClk; - uint32_t DivVal = 1; - - /* Get SPI clock rate */ - SPIClk = Chip_Clock_GetSystemClockRate(); /*The peripheral clock for both SPIs is the system clock*/ - - DivVal = SPIClk / bitRate; - - return DivVal; -} - -/* Configure SPI Delay parameters */ -void Chip_SPI_DelayConfig(LPC_SPI_T *pSPI, SPI_DELAY_CONFIG_T *pConfig) -{ - uint32_t delayValue = SPI_DLY_PRE_DELAY(pConfig->PreDelay) | - SPI_DLY_POST_DELAY(pConfig->PostDelay) | - SPI_DLY_FRAME_DELAY(pConfig->FrameDelay); - if (pConfig->TransferDelay) { - delayValue |= SPI_DLY_TRANSFER_DELAY(pConfig->TransferDelay - 1); - } - pSPI->DLY = delayValue; -} - -/* Disable/Enable Interrupt */ -void Chip_SPI_Int_Cmd(LPC_SPI_T *pSPI, uint32_t IntMask, FunctionalState NewState) -{ - if (NewState == ENABLE) { - pSPI->INTENSET = IntMask; - } - else { - pSPI->INTENCLR = IntMask; - } -} - -/*Send and Receive SPI Data */ -uint32_t Chip_SPI_RWFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup) -{ - uint32_t Status; - /* Clear status */ - Chip_SPI_ClearStatus(pSPI, SPI_STAT_CLR_RXOV | SPI_STAT_CLR_TXUR | SPI_STAT_CLR_SSA | SPI_STAT_CLR_SSD); - Chip_SPI_SetControlInfo(pSPI, pXfSetup->DataSize, SPI_TXCTL_ASSERT_SSEL | SPI_TXCTL_EOF); - pXfSetup->TxCnt = pXfSetup->RxCnt = 0; - while ((pXfSetup->TxCnt < pXfSetup->Length) || - (pXfSetup->RxCnt < pXfSetup->Length)) { - Status = Chip_SPI_GetStatus(pSPI); - - /* In case of TxReady */ - if ((Status & SPI_STAT_TXRDY) && (pXfSetup->TxCnt < pXfSetup->Length)) { - SPI_Send_Data(pSPI, pXfSetup); - } - - /*In case of Rx ready */ - if ((Status & SPI_STAT_RXRDY) && (pXfSetup->RxCnt < pXfSetup->Length)) { - SPI_Receive_Data(pSPI, pXfSetup); - } - } - /* Check error */ - if (Chip_SPI_GetStatus(pSPI) & (SPI_STAT_CLR_RXOV | SPI_STAT_CLR_TXUR)) { - return 0; - } - return pXfSetup->TxCnt; -} - -uint32_t Chip_SPI_WriteFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup) -{ - /* Clear status */ - Chip_SPI_ClearStatus(pSPI, SPI_STAT_CLR_RXOV | SPI_STAT_CLR_TXUR | SPI_STAT_CLR_SSA | SPI_STAT_CLR_SSD); - Chip_SPI_SetControlInfo(pSPI, pXfSetup->DataSize, SPI_TXCTL_ASSERT_SSEL | SPI_TXCTL_EOF | SPI_TXCTL_RXIGNORE); - pXfSetup->TxCnt = pXfSetup->RxCnt = 0; - while (pXfSetup->TxCnt < pXfSetup->Length) { - /* Wait for TxReady */ - while (!(Chip_SPI_GetStatus(pSPI) & SPI_STAT_TXRDY)) {} - - SPI_Send_Data_RxIgnore(pSPI, pXfSetup); - - } - - /* Make sure the last frame sent completely*/ - while (!(Chip_SPI_GetStatus(pSPI) & SPI_STAT_SSD)) {} - Chip_SPI_ClearStatus(pSPI, SPI_STAT_CLR_SSD); - - /* Check overrun error */ - if (Chip_SPI_GetStatus(pSPI) & SPI_STAT_CLR_TXUR) { - return 0; - } - return pXfSetup->TxCnt; -} - -uint32_t Chip_SPI_ReadFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup) -{ - /* Clear status */ - Chip_SPI_ClearStatus(pSPI, SPI_STAT_CLR_RXOV | SPI_STAT_CLR_TXUR | SPI_STAT_CLR_SSA | SPI_STAT_CLR_SSD); - Chip_SPI_SetControlInfo(pSPI, pXfSetup->DataSize, SPI_TXCTL_ASSERT_SSEL | SPI_TXCTL_EOF); - pXfSetup->TxCnt = pXfSetup->RxCnt = 0; - while (pXfSetup->RxCnt < pXfSetup->Length) { - /* Wait for TxReady */ - while (!(Chip_SPI_GetStatus(pSPI) & SPI_STAT_TXRDY)) {} - - SPI_Send_Dummy(pSPI, pXfSetup); - - /* Wait for receive data */ - while (!(Chip_SPI_GetStatus(pSPI) & SPI_STAT_RXRDY)) {} - - SPI_Receive_Data(pSPI, pXfSetup); - - } - /* Check overrun error */ - if (Chip_SPI_GetStatus(pSPI) & (SPI_STAT_CLR_RXOV | SPI_STAT_CLR_TXUR)) { - return 0; - } - return pXfSetup->RxCnt; -} - -/* SPI Interrupt Read/Write with 8-bit frame width */ -Status Chip_SPI_Int_RWFrames(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup) -{ - uint32_t Status; - - Status = Chip_SPI_GetStatus(pSPI); - /* Check error in INTSTAT register */ - if (Status & (SPI_STAT_RXOV | SPI_STAT_TXUR)) { - return ERROR; - } - - if (pXfSetup->TxCnt == 0) { - Chip_SPI_SetControlInfo(pSPI, pXfSetup->DataSize, SPI_TXCTL_ASSERT_SSEL | SPI_TXCTL_EOF); - } - - if (pXfSetup->pRx == NULL) { - if ((Status & SPI_STAT_TXRDY) && (pXfSetup->TxCnt < pXfSetup->Length)) { - SPI_Send_Data_RxIgnore(pSPI, pXfSetup); - } - } - else { - /* check if Tx ready */ - if ((Status & SPI_STAT_TXRDY) && (pXfSetup->TxCnt < pXfSetup->Length)) { - SPI_Send_Data(pSPI, pXfSetup); - } - - /* check if RX FIFO contains data */ - if ((Status & SPI_STAT_RXRDY) && (pXfSetup->RxCnt < pXfSetup->Length)) { - SPI_Receive_Data(pSPI, pXfSetup); - } - } - - return SUCCESS; -} - -/* Get SPI master bit rate */ -uint32_t Chip_SPIM_GetClockRate(LPC_SPI_T *pSPI) -{ - return Chip_Clock_GetSystemClockRate() / ((pSPI->DIV & ~SPI_DIV_RESERVED) + 1); -} - -/* Set SPI master bit rate */ -uint32_t Chip_SPIM_SetClockRate(LPC_SPI_T *pSPI, uint32_t rate) -{ - uint32_t baseClock, div; - - /* Get peripheral base clock rate */ - baseClock = Chip_Clock_GetSystemClockRate(); - - /* Compute divider */ - div = baseClock / rate; - - /* Limit values */ - if (div == 0) { - div = 1; - } - else if (div > 0x10000) { - div = 0x10000; - } - pSPI->DIV = div - 1; - - return Chip_SPIM_GetClockRate(pSPI); -} - -/* Configure SPI Delay parameters */ -void Chip_SPIM_DelayConfig(LPC_SPI_T *pSPI, SPIM_DELAY_CONFIG_T *pConfig) -{ - pSPI->DLY = (SPI_DLY_PRE_DELAY(pConfig->PreDelay) | - SPI_DLY_POST_DELAY(pConfig->PostDelay) | - SPI_DLY_FRAME_DELAY(pConfig->FrameDelay) | - SPI_DLY_TRANSFER_DELAY(pConfig->TransferDelay - 1)); -} - -/* Assert a SPI select */ -void Chip_SPIM_AssertSSEL(LPC_SPI_T *pSPI, uint8_t sselNum) -{ - uint32_t reg; - - reg = pSPI->TXCTRL & SPI_TXDATCTL_CTRLMASK; - - /* Assert a SSEL line by driving it low */ - reg &= ~SPI_TXDATCTL_DEASSERTNUM_SSEL(sselNum); - - pSPI->TXCTRL = reg; -} - -/* Deassert a SPI select */ -void Chip_SPIM_DeAssertSSEL(LPC_SPI_T *pSPI, uint8_t sselNum) -{ - uint32_t reg; - - reg = pSPI->TXCTRL & SPI_TXDATCTL_CTRLMASK; - pSPI->TXCTRL = reg | SPI_TXDATCTL_DEASSERTNUM_SSEL(sselNum); -} - -/* SPI master transfer state change handler */ -void Chip_SPIM_XferHandler(LPC_SPI_T *pSPI, SPIM_XFER_T *xfer) -{ - uint32_t data; - uint8_t flen; - - /* Get length of a receive value */ - flen = ((pSPI->TXCTRL & ~SPI_TXCTRL_RESERVED) >> 24) & 0xF; - - /* Master asserts slave */ - if ((Chip_SPI_GetStatus(pSPI) & SPI_STAT_SSA) != 0) { - Chip_SPI_ClearStatus(pSPI, SPI_STAT_SSA); - - /* SSEL assertion callback */ - xfer->pCB->masterXferCSAssert(xfer); - } - - /* Slave de-assertion */ - if ((Chip_SPI_GetStatus(pSPI) & SPI_STAT_SSD) != 0) { - Chip_SPI_ClearStatus(pSPI, SPI_STAT_SSD); - - /* If transmitter disabled and deassert happens, the transfer is done */ - if (xmitOn == false) { - xfer->pCB->mMasterXferDone(xfer); - } - } - - /* Transmit data? */ - while (((Chip_SPI_GetStatus(pSPI) & SPI_STAT_TXRDY) != 0) && (xmitOn == true)) { - if ((xfer->txCount == 1) && (xfer->terminate)) { - /* Transfer is done, this will be last data */ - Chip_SPIM_ForceEndOfTransfer(pSPI); - xmitOn = false; - } - else if (xfer->txCount == 0) { - /* Request a new buffer first */ - xfer->pCB->masterXferSend(xfer); - } - - if (xfer->txCount > 0) { - /* Send 0 if ignoring transmit */ - if (xfer->pTXData8 == NULL) { - data = 0; - } - else { - /* Copy buffer to data */ - if (flen > 8) { - data = (uint32_t) *xfer->pTXData16; - xfer->pTXData16++; - } - else { - data = (uint32_t) *xfer->pTXData8; - xfer->pTXData8++; - } - - xfer->dataTXferred++; - } - - Chip_SPI_WriteTXData(pSPI, data); - xfer->txCount--; - } - } - - /* Data received? */ - while ((Chip_SPI_GetStatus(pSPI) & SPI_STAT_RXRDY) != 0) { - /* Get raw data and status */ - data = Chip_SPI_ReadRawRXFifo(pSPI); - - /* Only copy data when not ignoring receive */ - if (xfer->pRXData8 != NULL) { - /* Enough size in current buffers? */ - if (xfer->rxCount == 0) { - /* Request a new buffer first */ - xfer->pCB->masterXferRecv(xfer); - } - - /* Copy data to buffer */ - if (xfer->rxCount > 0) { - if (flen > 8) { - *xfer->pRXData16 = (uint16_t) (data & 0xFFFF); - xfer->pRXData16++; - } - else { - *xfer->pRXData8 = (uint8_t) (data & 0xFF); - xfer->pRXData8++; - } - - xfer->dataRXferred++; - xfer->rxCount--; - } - } - } -} - -/* Start non-blocking SPI master transfer */ -void Chip_SPIM_Xfer(LPC_SPI_T *pSPI, SPIM_XFER_T *xfer) -{ - /* Setup SPI master select, data length, EOT/EOF timing, and RX data ignore */ - pSPI->TXCTRL = xfer->options | SPI_TXDATCTL_DEASSERT_ALL; - Chip_SPIM_AssertSSEL(pSPI, xfer->sselNum); - - /* Clear initial transfer states */ - xfer->dataRXferred = xfer->dataTXferred = 0; - - /* Call main handler to start transfer */ - xmitOn = true; - Chip_SPIM_XferHandler(pSPI, xfer); -} - -/* Perform blocking SPI master transfer */ -void Chip_SPIM_XferBlocking(LPC_SPI_T *pSPI, SPIM_XFER_T *xfer) -{ - /* Start trasnfer */ - Chip_SPIM_Xfer(pSPI, xfer); - - /* Wait for termination */ - while (xmitOn == true) { - Chip_SPIM_XferHandler(pSPI, xfer); - } -} - -/* SPI slave transfer state change handler */ -uint32_t Chip_SPIS_XferHandler(LPC_SPI_T *pSPI, SPIS_XFER_T *xfer) -{ - uint32_t staterr, data; - uint8_t flen; - - /* Get length of a receive value */ - flen = ((pSPI->TXCTRL & ~SPI_TXCTRL_RESERVED) >> 24) & 0xF; - - /* Get errors for later, we'll continue even if errors occur, but we notify - caller on return */ - staterr = Chip_SPI_GetStatus(pSPI) & (SPI_STAT_RXOV | SPI_STAT_TXUR); - if (staterr != 0) { - Chip_SPI_ClearStatus(pSPI, staterr); - } - - /* Slave assertion */ - if ((Chip_SPI_GetStatus(pSPI) & SPI_STAT_SSA) != 0) { - Chip_SPI_ClearStatus(pSPI, SPI_STAT_SSA); - - /* Determine SPI select. Read the data FIFO to get the slave number. Data - should not be in the receive FIFO yet, only the statuses */ - xfer->sselNum = Chip_SPIS_FindSSEL(pSPI, Chip_SPI_ReadRawRXFifo(pSPI)); - - /* SSEL assertion callback */ - xfer->pCB->slaveXferCSAssert(xfer); - } - - /* Slave de-assertion */ - if ((Chip_SPI_GetStatus(pSPI) & SPI_STAT_SSD) != 0) { - Chip_SPI_ClearStatus(pSPI, SPI_STAT_SSD); - deasserted = true; - xfer->pCB->slaveXferCSDeAssert(xfer); - } - - /* Transmit data? */ - while ((Chip_SPI_GetStatus(pSPI) & SPI_STAT_TXRDY) != 0) { - if (xfer->txCount == 0) { - /* Request a new buffer first */ - xfer->pCB->slaveXferSend(xfer); - } - - /* Send 0 on empty buffer or count */ - if ((xfer->txCount == 0) || (xfer->pTXData8 == NULL)) { - data = 0; - } - else { - /* Copy buffer to data */ - if (flen > 8) { - data = (uint32_t) *xfer->pTXData16; - xfer->pTXData16++; - } - else { - data = (uint32_t) *xfer->pTXData8; - xfer->pTXData8++; - } - - xfer->dataTXferred++; - xfer->txCount--; - } - - Chip_SPI_WriteTXData(pSPI, data); - } - - /* Data received? */ - while ((Chip_SPI_GetStatus(pSPI) & SPI_STAT_RXRDY) != 0) { - /* Get raw data and status */ - data = Chip_SPI_ReadRawRXFifo(pSPI); - - /* Only copy data when not ignoring receive */ - if (xfer->pRXData8 != NULL) { - /* Enough size in current buffers? */ - if (xfer->rxCount == 0) { - /* Request a new buffer first */ - xfer->pCB->slaveXferRecv(xfer); - } - - /* Copy data to buffer */ - if (flen > 8) { - *xfer->pRXData16 = (uint16_t) (data & 0xFFFF); - xfer->pRXData16++; - } - else { - *xfer->pRXData8 = (uint8_t) (data & 0xFF); - xfer->pRXData8++; - } - - xfer->dataRXferred++; - xfer->rxCount--; - } - } - - return staterr; -} - -/* SPI slave transfer blocking function */ -uint32_t Chip_SPIS_XferBlocking(LPC_SPI_T *pSPI, SPIS_XFER_T *xfer) -{ - uint32_t status = 0; - - /* Wait forever until deassertion event */ - deasserted = false; - while ((!deasserted) && (status == 0)) { - status = Chip_SPIS_XferHandler(pSPI, xfer); - } - - return status; -} diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/spi/spi_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/spi/spi_8xx.h deleted file mode 100644 index ddefb488844..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/spi/spi_8xx.h +++ /dev/null @@ -1,1170 +0,0 @@ -/* - * @brief LPC8XX SPI common functions and definitions - * - * @note - * Copyright(C) NXP Semiconductors, 2014 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __SPI_8XX_H__ -#define __SPI_8XX_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup SPI_COMMON_8XX CHIP: LPC8XX SPI common functions and definitions - * @ingroup CHIP_8XX_Drivers - * @{ - */ -/** - * @brief SPI register block structure - */ -typedef struct { /*!< SPI Structure */ - __IO uint32_t CFG; /*!< SPI Configuration register */ - __IO uint32_t DLY; /*!< SPI Delay register */ - __IO uint32_t STAT; /*!< SPI Status register */ - __IO uint32_t INTENSET; /*!< SPI Interrupt Enable Set register */ - __O uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear register */ - __I uint32_t RXDAT; /*!< SPI Receive Data register */ - __IO uint32_t TXDATCTL; /*!< SPI Transmit Data with Control register */ - __IO uint32_t TXDAT; /*!< SPI Transmit Data register */ - __IO uint32_t TXCTRL; /*!< SPI Transmit Control register */ - __IO uint32_t DIV; /*!< SPI clock Divider register */ - __I uint32_t INTSTAT; /*!< SPI Interrupt Status register */ -} LPC_SPI_T; - -/* Reserved bits masks for registers */ -#define SPI_CFG_RESERVED ((1<<1)|(1<<6)|0xfffffe00) -#define SPI_DLY_RESERVED 0xffff0000 -#define SPI_STAT_RESERVED (~0x1ff) -#define SPI_INTENSET_RESERVED (~0x3f) -#define SPI_INTENCLR_RESERVED (~0x3f) -#define SPI_RXDAT_RESERVED ((7<<17)|(0x7ffu<<21)) -#define SPI_TXDATCTL_RESERVED ((7<<17)|(1<<23)|(0xfu<<28)) -#define SPI_TXDAT_RESERVED 0xffff0000 -#define SPI_TXCTRL_RESERVED (0xffff|(7<<17)|(1<<23)|(0xfu<<28)) -#define SPI_DIV_RESERVED 0xffff0000 -#define SPI_INTSTAT_RESERVED (~0x3f) - -/** - * Macro defines for SPI Configuration register - */ -#define SPI_CFG_BITMASK (0x1BD) /** SPI register bit mask */ -#define SPI_CFG_SPI_EN (1 << 0) /** SPI Slave Mode Select */ -#define SPI_CFG_SLAVE_EN (0 << 0) /** SPI Master Mode Select */ -#define SPI_CFG_MASTER_EN (1 << 2) /** SPI MSB First mode enable */ -#define SPI_CFG_MSB_FIRST_EN (0 << 3) /** SPI LSB First mode enable */ -#define SPI_CFG_LSB_FIRST_EN (1 << 3) /** SPI Clock Phase Select */ -#define SPI_CFG_CPHA_FIRST (0 << 4) /** Capture data on the first edge, Change data on the following edge */ -#define SPI_CFG_CPHA_SECOND (1 << 4) /** SPI Clock Polarity Select */ -#define SPI_CFG_CPOL_LO (0 << 5) /** The rest state of the clock (between frames) is low. */ -#define SPI_CFG_CPOL_HI (1 << 5) /** The rest state of the clock (between frames) is high. */ -#define SPI_CFG_LBM_EN (1 << 7) /** SPI control 1 loopback mode enable */ -#define SPI_CFG_SPOL_LO (0 << 8) /** SPI SSEL0 Polarity Select */ -#define SPI_CFG_SPOL_HI (1 << 8) /** SSEL0 is active High */ -#define SPI_CFG_SPOLNUM_HI(n) (1 << ((n) + 8)) /** SSELN is active High, selects 0 - 3 */ - -/** - * Macro defines for SPI Delay register - */ -#define SPI_DLY_BITMASK (0xFFFF) /** SPI DLY Register Mask */ -#define SPI_DLY_PRE_DELAY(n) (((n) & 0x0F) << 0) /** Time in SPI clocks between SSEL assertion and the beginning of a data frame */ -#define SPI_DLY_POST_DELAY(n) (((n) & 0x0F) << 4) /** Time in SPI clocks between the end of a data frame and SSEL deassertion. */ -#define SPI_DLY_FRAME_DELAY(n) (((n) & 0x0F) << 8) /** Minimum time in SPI clocks between adjacent data frames. */ -#define SPI_DLY_TRANSFER_DELAY(n) (((n) & 0x0F) << 12) /** Minimum time in SPI clocks that the SSEL is deasserted between transfers. */ - -/** - * Macro defines for SPI Status register - */ -#define SPI_STAT_BITMASK (0x1FF) /** SPI STAT Register BitMask */ -#define SPI_STAT_RXRDY (1 << 0) /** Receiver Ready Flag */ -#define SPI_STAT_TXRDY (1 << 1) /** Transmitter Ready Flag */ -#define SPI_STAT_RXOV (1 << 2) /** Receiver Overrun interrupt flag */ -#define SPI_STAT_TXUR (1 << 3) /** Transmitter Underrun interrupt flag (In Slave Mode only) */ -#define SPI_STAT_SSA (1 << 4) /** Slave Select Assert */ -#define SPI_STAT_SSD (1 << 5) /** Slave Select Deassert */ -#define SPI_STAT_STALLED (1 << 6) /** Stalled status flag */ -#define SPI_STAT_EOT (1 << 7) /** End Transfer flag */ -#define SPI_STAT_MSTIDLE (1 << 8) /** Idle status flag */ - -/** - * Macro defines for SPI Interrupt Enable read and Set register - */ -#define SPI_INTENSET_BITMASK (0x3F) /** SPI INTENSET Register BitMask */ -#define SPI_INTENSET_RXDYEN (1 << 0) /** Enable Interrupt when receiver data is available */ -#define SPI_INTENSET_TXDYEN (1 << 1) /** Enable Interrupt when the transmitter holding register is available. */ -#define SPI_INTENSET_RXOVEN (1 << 2) /** Enable Interrupt when a receiver overrun occurs */ -#define SPI_INTENSET_TXUREN (1 << 3) /** Enable Interrupt when a transmitter underrun occurs (In Slave Mode Only)*/ -#define SPI_INTENSET_SSAEN (1 << 4) /** Enable Interrupt when the Slave Select is asserted.*/ -#define SPI_INTENSET_SSDEN (1 << 5) /** Enable Interrupt when the Slave Select is deasserted..*/ - -/** - * Macro defines for SPI Interrupt Enable Clear register - */ -#define SPI_INTENCLR_BITMASK (0x3F) /** SPI INTENCLR Register BitMask */ -#define SPI_INTENCLR_RXDYEN (1 << 0) /** Disable Interrupt when receiver data is available */ -#define SPI_INTENCLR_TXDYEN (1 << 1) /** Disable Interrupt when the transmitter holding register is available. */ -#define SPI_INTENCLR_RXOVEN (1 << 2) /** Disable Interrupt when a receiver overrun occurs */ -#define SPI_INTENCLR_TXUREN (1 << 3) /** Disable Interrupt when a transmitter underrun occurs (In Slave Mode Only) */ -#define SPI_INTENCLR_SSAEN (1 << 4) /** Disable Interrupt when the Slave Select is asserted. */ -#define SPI_INTENCLR_SSDEN (1 << 5) /** Disable Interrupt when the Slave Select is deasserted.. */ - -/** - * Macro defines for SPI Receiver Data register - */ -#define SPI_RXDAT_BITMASK (0x1FFFFF) /** SPI RXDAT Register BitMask */ -#define SPI_RXDAT_DATA(n) ((n) & 0xFFFF) /** Receiver Data */ -#define SPI_RXDAT_RXSSELN_ACTIVE (0 << 16) /** The state of SSEL pin is active */ -#define SPI_RXDAT_RXSSELN_INACTIVE ((1 << 16) /** The state of SSEL pin is inactive */ -#define SPI_RXDAT_RXSSELNUM_INACTIVE(n) (1 << ((n) + 16)) /** The state of SSELN pin is inactive */ -#define SPI_RXDAT_SOT (1 << 20) /** Start of Transfer flag */ - -/** - * Macro defines for SPI Transmitter Data and Control register - */ -#define SPI_TXDATCTL_BITMASK (0xF71FFFF) /** SPI TXDATCTL Register BitMask */ -#define SPI_TXDATCTL_DATA(n) ((n) & 0xFFFF) /** SPI Transmit Data */ -#define SPI_TXDATCTL_CTRLMASK (0xF710000) /** SPI TXDATCTL Register BitMask for control bits only */ -#define SPI_TXDATCTL_ASSERT_SSEL (0 << 16) /** Assert SSEL0 pin */ -#define SPI_TXDATCTL_DEASSERT_SSEL (1 << 16) /** Deassert SSEL0 pin */ -#define SPI_TXDATCTL_DEASSERTNUM_SSEL(n) (1 << ((n) + 16)) /** Deassert SSELN pin */ -#define SPI_TXDATCTL_DEASSERT_ALL (0xF << 16) /** Deassert all SSEL pins */ -#define SPI_TXDATCTL_EOT (1 << 20) /** End of Transfer flag (TRANSFER_DELAY is applied after sending the current frame) */ -#define SPI_TXDATCTL_EOF (1 << 21) /** End of Frame flag (FRAME_DELAY is applied after sending the current part) */ -#define SPI_TXDATCTL_RXIGNORE (1 << 22) /** Receive Ignore Flag */ -#define SPI_TXDATCTL_FLEN(n) (((n) & 0x0F) << 24) /** Frame length - 1 */ - -/** - * Macro defines for SPI Transmitter Data Register - */ -#define SPI_TXDAT_DATA(n) ((n) & 0xFFFF) /** SPI Transmit Data */ - -/** - * Macro defines for SPI Transmitter Control register - */ -#define SPI_TXCTL_BITMASK (0xF7F0000) /** SPI TXDATCTL Register BitMask */ -#define SPI_TXCTL_ASSERT_SSEL (0 << 16) /** Assert SSEL0 pin */ -#define SPI_TXCTL_DEASSERT_SSEL (1 << 16) /** Deassert SSEL0 pin */ -#define SPI_TXCTL_DEASSERTNUM_SSEL(n) (1 << ((n) + 16)) /** Deassert SSELN pin */ -#define SPI_TXDATCTL_DEASSERT_ALL (0xF << 16) /** Deassert all SSEL pins */ -#define SPI_TXCTL_EOT (1 << 20) /** End of Transfer flag (TRANSFER_DELAY is applied after sending the current frame) */ -#define SPI_TXCTL_EOF (1 << 21) /** End of Frame flag (FRAME_DELAY is applied after sending the current part) */ -#define SPI_TXCTL_RXIGNORE (1 << 22) /** Receive Ignore Flag */ -#define SPI_TXCTL_FLEN(n) ((((n) - 1) & 0x0F) << 24) /** Frame length, 0 - 16 */ -#define SPI_TXCTL_FLENMASK (0xF << 24) /** Frame length mask */ - -/** - * Macro defines for SPI Divider register - */ -#define SPI_DIV_VAL(n) ((n) & 0xFFFF) /** Rate divider value mask (In Master Mode only)*/ - -/** - * Macro defines for SPI Interrupt Status register - */ -#define SPI_INTSTAT_BITMASK (0x3F) /** SPI INTSTAT Register Bitmask */ -#define SPI_INTSTAT_RXRDY (1 << 0) /** Receiver Ready Flag */ -#define SPI_INTSTAT_TXRDY (1 << 1) /** Transmitter Ready Flag */ -#define SPI_INTSTAT_RXOV (1 << 2) /** Receiver Overrun interrupt flag */ -#define SPI_INTSTAT_TXUR (1 << 3) /** Transmitter Underrun interrupt flag (In Slave Mode only) */ -#define SPI_INTSTAT_SSA (1 << 4) /** Slave Select Assert */ -#define SPI_INTSTAT_SSD (1 << 5) /** Slave Select Deassert */ - -/** @brief SPI Clock Mode*/ -#define SPI_CLOCK_CPHA0_CPOL0 (SPI_CFG_CPOL_LO | SPI_CFG_CPHA_FIRST) /**< CPHA = 0, CPOL = 0 */ -#define SPI_CLOCK_MODE0 SPI_CLOCK_CPHA0_CPOL0 /**< Alias for CPHA = 0, CPOL = 0 */ -#define SPI_CLOCK_CPHA1_CPOL0 SPI_CFG_CPOL_LO | SPI_CFG_CPHA_SECOND /**< CPHA = 0, CPOL = 1 */ -#define SPI_CLOCK_MODE1 SPI_CLOCK_CPHA1_CPOL0 /**< Alias for CPHA = 0, CPOL = 1 */ -#define SPI_CLOCK_CPHA0_CPOL1 SPI_CFG_CPOL_HI | SPI_CFG_CPHA_FIRST /**< CPHA = 1, CPOL = 0 */ -#define SPI_CLOCK_MODE2 SPI_CLOCK_CPHA0_CPOL1 /**< Alias for CPHA = 1, CPOL = 0 */ -#define SPI_CLOCK_CPHA1_CPOL1 SPI_CFG_CPOL_HI | SPI_CFG_CPHA_SECOND /**< CPHA = 1, CPOL = 1 */ -#define SPI_CLOCK_MODE3 SPI_CLOCK_CPHA1_CPOL1 /**< Alias for CPHA = 1, CPOL = 1 */ - -/** - * @brief Set SPI CFG register values - * @param pSPI : The base of SPI peripheral on the chip - * @param bits : CFG register bits to set, amd OR'ed value of SPI_CFG_* definitions - * @return Nothing - * @note This function safely sets only the selected bits in the SPI CFG register. - * It can be used to enable multiple bits at once. - */ -STATIC INLINE void Chip_SPI_SetCFGRegBits(LPC_SPI_T *pSPI, uint32_t bits) -{ - /* Update CFG register with only selected bits disabled */ - pSPI->CFG = bits | (pSPI->CFG & SPI_CFG_BITMASK); -} - -/** - * @brief Clear SPI CFG register values - * @param pSPI : The base of SPI peripheral on the chip - * @param bits : CFG register bits to clear, amd OR'ed value of SPI_CFG_* definitions - * @return Nothing - * @note This function safely clears only the selected bits in the SPI CFG register. - * It can be used to disable multiple bits at once. - */ -STATIC INLINE void Chip_SPI_ClearCFGRegBits(LPC_SPI_T *pSPI, uint32_t bits) -{ - /* Update CFG register with only selected bits disabled */ - pSPI->CFG = ~bits & (pSPI->CFG & SPI_CFG_BITMASK); -} - -/** - * @brief Initialize the SPI - * @param pSPI : The base SPI peripheral on the chip - * @return Nothing - */ -STATIC INLINE void Chip_SPI_Init(LPC_SPI_T *pSPI) -{ - /* Enable SPI clock and reset IP */ - if (pSPI == LPC_SPI1) { - Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SPI1); - Chip_SYSCTL_PeriphReset(RESET_SPI1); - } else { - Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SPI0); - Chip_SYSCTL_PeriphReset(RESET_SPI0); - } -} - -/** - * @brief Disable SPI peripheral - * @param pSPI : The base of SPI peripheral on the chip - * @return Nothing - */ -STATIC INLINE void Chip_SPI_Disable(LPC_SPI_T *pSPI) -{ - Chip_SPI_ClearCFGRegBits(pSPI, SPI_CFG_SPI_EN); -} - -/** - * @brief Disable SPI operation - * @param pSPI : The base of SPI peripheral on the chip - * @return Nothing - * @note The SPI controller is disabled. - */ -STATIC INLINE void Chip_SPI_DeInit(LPC_SPI_T *pSPI) -{ - Chip_SPI_Disable(pSPI); - if (pSPI == LPC_SPI1) { - Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SPI1); - } else { - Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SPI0); - } -} - -/** - * @brief Enable SPI peripheral - * @param pSPI : The base of SPI peripheral on the chip - * @return Nothing - */ -STATIC INLINE void Chip_SPI_Enable(LPC_SPI_T *pSPI) -{ - Chip_SPI_SetCFGRegBits(pSPI, SPI_CFG_SPI_EN); -} - -/** - * @brief Enable SPI master mode - * @param pSPI : The base of SPI peripheral on the chip - * @return Nothing - * @note SPI slave mode will be disabled with this call. All SPI SSEL - * lines will also be deasserted. - */ -STATIC INLINE void Chip_SPI_EnableMasterMode(LPC_SPI_T *pSPI) -{ - Chip_SPI_SetCFGRegBits(pSPI, SPI_CFG_MASTER_EN); - - /* Deassert all chip selects, only in master mode */ - pSPI->TXCTRL = SPI_TXDATCTL_DEASSERT_ALL; -} - -/** - * @brief Enable SPI slave mode - * @param pSPI : The base of SPI peripheral on the chip - * @return Nothing - * @note SPI master mode will be disabled with this call. - */ -STATIC INLINE void Chip_SPI_EnableSlaveMode(LPC_SPI_T *pSPI) -{ - Chip_SPI_ClearCFGRegBits(pSPI, SPI_CFG_MASTER_EN); -} - -/** - * @brief Enable LSB First transfers - * @param pSPI : The base of SPI peripheral on the chip - * @return Nothing - */ -STATIC INLINE void Chip_SPI_EnableLSBFirst(LPC_SPI_T *pSPI) -{ - Chip_SPI_SetCFGRegBits(pSPI, SPI_CFG_LSB_FIRST_EN); -} - -/** - * @brief Enable MSB First transfers - * @param pSPI : The base of SPI peripheral on the chip - * @return Nothing - */ -STATIC INLINE void Chip_SPI_EnableMSBFirst(LPC_SPI_T *pSPI) -{ - Chip_SPI_ClearCFGRegBits(pSPI, SPI_CFG_LSB_FIRST_EN); -} - - -/** - * @brief Set SPI mode - * @param pSPI : The base of SPI peripheral on the chip - * @param mode : SPI mode to set the SPI interface to - * @return Nothing - */ -STATIC INLINE void Chip_SPI_SetSPIMode(LPC_SPI_T *pSPI, uint32_t mode) -{ - Chip_SPI_ClearCFGRegBits(pSPI, (SPI_CFG_CPOL_HI | SPI_CFG_CPHA_SECOND)); - Chip_SPI_SetCFGRegBits(pSPI, (uint32_t) mode); -} - -/** - * @brief Set polarity on the SPI chip select high - * @param pSPI : The base of SPI peripheral on the chip - * @param csNum : Chip select number, 0 - 3 - * @return Nothing - * @note SPI chip select polarity is active high. - */ -STATIC INLINE void Chip_SPI_SetCSPolHigh(LPC_SPI_T *pSPI, uint8_t csNum) -{ - Chip_SPI_SetCFGRegBits(pSPI, SPI_CFG_SPOLNUM_HI(csNum)); -} - -/** - * @brief Set polarity on the SPI chip select low - * @param pSPI : The base of SPI peripheral on the chip - * @param csNum : Chip select number, 0 - 3 - * @return Nothing - * @note SPI chip select polarity is active low. - */ -STATIC INLINE void Chip_SPI_SetCSPolLow(LPC_SPI_T *pSPI, uint8_t csNum) -{ - Chip_SPI_ClearCFGRegBits(pSPI, SPI_CFG_SPOLNUM_HI(csNum)); -} - -/** - * @brief Setup SPI configuration - * @param pSPI : The base of SPI peripheral on the chip - * @param config : ORed spi configuration flags - * @return Nothing - * @note Possible values that can be ORed in @a config are - * SPI_CLOCK_* (example: #SPI_CLOCK_CPHA0_CPOL0) along with - * SPI_CFG_* (example: #SPI_CFG_SPI_EN). - */ -STATIC INLINE void Chip_SPI_ConfigureSPI(LPC_SPI_T *pSPI, uint32_t config) -{ - Chip_SPI_ClearCFGRegBits(pSPI, SPI_CFG_MASTER_EN | SPI_CFG_LSB_FIRST_EN | - SPI_CFG_CPHA_SECOND | SPI_CFG_CPOL_HI); - Chip_SPI_SetCFGRegBits(pSPI, config); - - /* Deassert all chip selects, only in master mode */ - pSPI->TXCTRL = SPI_TXDATCTL_DEASSERT_ALL; -} - -/** - * @brief Get the current status of SPI controller - * @param pSPI : The base of SPI peripheral on the chip - * @return SPI Status (Or-ed bit value of SPI_STAT_*) - * @note Mask the return value with a value of type SPI_STAT_* to determine - * if that status is active. - */ -STATIC INLINE uint32_t Chip_SPI_GetStatus(LPC_SPI_T *pSPI) -{ - return pSPI->STAT & ~SPI_STAT_RESERVED; -} - -/** - * @brief Clear SPI status - * @param pSPI : The base of SPI peripheral on the chip - * @param Flag : Clear Flag (Or-ed bit value of SPI_STAT_*) - * @return Nothing - * @note Only SPI_STAT_RXOV, SPI_STAT_TXUR, SPI_STAT_SSA, and - * SPI_STAT_SSD statuses can be cleared. - */ -STATIC INLINE void Chip_SPI_ClearStatus(LPC_SPI_T *pSPI, uint32_t Flag) -{ - pSPI->STAT = Flag; -} - -/** - * @brief Enable a SPI interrupt - * @param pSPI : The base of SPI peripheral on the chip - * @param Flag : Or'ed value of SPI_INTENSET_* values to enable - * @return Nothing - */ -STATIC INLINE void Chip_SPI_EnableInts(LPC_SPI_T *pSPI, uint32_t Flag) -{ - pSPI->INTENSET = Flag; -} - -/** - * @brief Disable a SPI interrupt - * @param pSPI : The base of SPI peripheral on the chip - * @param Flag : Or'ed value of SPI_INTENCLR_* values to disable - * @return Nothing - */ -STATIC INLINE void Chip_SPI_DisableInts(LPC_SPI_T *pSPI, uint32_t Flag) -{ - pSPI->INTENCLR = Flag; -} - -/** - * @brief Return enabled SPI interrupts - * @param pSPI : The base of SPI peripheral on the chip - * @return An Or'ed value of SPI_INTENSET_* values - * @note Mask the return value with a SPI_INTENSET_* value to determine - * if the interrupt is enabled. - */ -STATIC INLINE uint32_t Chip_SPI_GetEnabledInts(LPC_SPI_T *pSPI) -{ - return pSPI->INTENSET & ~SPI_INTENSET_RESERVED; -} - -/** - * @brief Return pending SPI interrupts - * @param pSPI : The base of SPI peripheral on the chip - * @return An Or'ed value of SPI_INTSTAT_* values - * @note Mask the return value with a SPI_INTSTAT_* value to determine - * if the interrupt is pending. - */ -STATIC INLINE uint32_t Chip_SPI_GetPendingInts(LPC_SPI_T *pSPI) -{ - return pSPI->INTSTAT & ~SPI_INTSTAT_RESERVED; -} - -/** - * @brief Flush FIFOs - * @param pSPI : The base of SPI peripheral on the chip - * @return Nothing - */ -STATIC INLINE void Chip_SPI_FlushFifos(LPC_SPI_T *pSPI) -{ - Chip_SPI_Disable(pSPI); - Chip_SPI_Enable(pSPI); -} - -/** - * @brief Read raw data from receive FIFO with status bits - * @param pSPI : The base of SPI peripheral on the chip - * @return Current value in receive data FIFO plus status bits - */ -STATIC INLINE uint32_t Chip_SPI_ReadRawRXFifo(LPC_SPI_T *pSPI) -{ - return pSPI->RXDAT & ~SPI_RXDAT_RESERVED; -} - -/** - * @brief Read data from receive FIFO masking off status bits - * @param pSPI : The base of SPI peripheral on the chip - * @return Current value in receive data FIFO - * @note The return value is masked with 0xFFFF to not exceed 16-bits. All - * other status bits are thrown away. This register should only be read if it - * has data in it. This function is useful for systems that don't need SPI - * select (SSEL) monitoring. - */ -STATIC INLINE uint32_t Chip_SPI_ReadRXData(LPC_SPI_T *pSPI) -{ - return pSPI->RXDAT & 0xFFFF; -} - -/** - * @brief Write data to transmit FIFO - * @param pSPI : The base of SPI peripheral on the chip - * @param data : Data to write - * @return Nothing - */ -STATIC INLINE void Chip_SPI_WriteTXData(LPC_SPI_T *pSPI, uint16_t data) -{ - pSPI->TXDAT = (uint32_t) data; -} - -/** - * @brief Set SPI TXCTRL register control options - * @param pSPI : The base of SPI peripheral on the chip - * @param bits : TXCTRL register bits to set, amd OR'ed value of SPI_TXDATCTL_* definitions - * @return Nothing - * @note This function safely sets only the selected bits in the SPI TXCTRL register. - * It can be used to enable multiple bits at once. - */ -STATIC INLINE void Chip_SPI_SetTXCTRLRegBits(LPC_SPI_T *pSPI, uint32_t bits) -{ - pSPI->TXCTRL = bits | (pSPI->TXCTRL & SPI_TXDATCTL_CTRLMASK); -} - -/** - * @brief Clear SPI TXCTRL register control options - * @param pSPI : The base of SPI peripheral on the chip - * @param bits : TXCTRL register bits to clear, amd OR'ed value of SPI_TXDATCTL_* definitions - * @return Nothing - * @note This function safely clears only the selected bits in the SPI TXCTRL register. - * It can be used to disable multiple bits at once. - */ -STATIC INLINE void Chip_SPI_ClearTXCTRLRegBits(LPC_SPI_T *pSPI, uint32_t bits) -{ - pSPI->TXCTRL = ~bits & (pSPI->TXCTRL & SPI_TXDATCTL_CTRLMASK); -} - -/** - * @brief Set TX control options (safe) - * @param pSPI : The base of SPI peripheral on the chip - * @param ctrlBits : Or'ed control bits to set - * @return Nothing - * @note Selectable control states include SPI_TXCTL_DEASSERTNUM_SSEL(0/1/2/3), - * SPI_TXCTL_EOT, SPI_TXCTL_EOF, SPI_TXCTL_RXIGNORE, and SPI_TXCTL_FLEN(bits). - */ -STATIC INLINE void Chip_SPI_SetTXCtl(LPC_SPI_T *pSPI, uint32_t ctrlBits) -{ - Chip_SPI_SetTXCTRLRegBits(pSPI, ctrlBits); -} - -/** - * @brief Clear TX control options (safe) - * @param pSPI : The base of SPI peripheral on the chip - * @param ctrlBits : Or'ed control bits to clear - * @return Nothing - * @note Selectable control states include SPI_TXCTL_DEASSERTNUM_SSEL(0/1/2/3), - * SPI_TXCTL_EOT, SPI_TXCTL_EOF, SPI_TXCTL_RXIGNORE, and SPI_TXCTL_FLEN(bits). - */ -STATIC INLINE void Chip_SPI_ClearTXCtl(LPC_SPI_T *pSPI, uint32_t ctrlBits) -{ - Chip_SPI_ClearTXCTRLRegBits(pSPI, ctrlBits); -} - -/** - * @brief Set TX data transfer size in bits - * @param pSPI : The base of SPI peripheral on the chip - * @param ctrlBits : Number of bits to transmit and receive, must be 1 to 16 - * @return Nothing - */ -STATIC INLINE void Chip_SPI_SetXferSize(LPC_SPI_T *pSPI, uint32_t ctrlBits) -{ - Chip_SPI_ClearTXCTRLRegBits(pSPI, SPI_TXCTL_FLENMASK); - Chip_SPI_SetTXCTRLRegBits(pSPI, SPI_TXCTL_FLEN(ctrlBits)); -} - -/** - * @} - */ - - -/** @defgroup SPI_8XX CHIP: LPC8xx SPI driver - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/** @brief SPI Mode*/ -typedef enum { - SPI_MODE_MASTER = SPI_CFG_MASTER_EN, /* Master Mode */ - SPI_MODE_SLAVE = SPI_CFG_SLAVE_EN, /* Slave Mode */ -} SPI_MODE_T; - -/** @brief SPI Data Order Mode*/ -typedef enum IP_SPI_DATA_ORDER { - SPI_DATA_MSB_FIRST = SPI_CFG_MSB_FIRST_EN, /* Standard Order */ - SPI_DATA_LSB_FIRST = SPI_CFG_LSB_FIRST_EN, /* Reverse Order */ -} SPI_DATA_ORDER_T; - -/** @brief SPI SSEL Polarity definition*/ -typedef enum IP_SPI_SSEL_POL { - SPI_SSEL_ACTIVE_LO = SPI_CFG_SPOL_LO, /* SSEL is active Low*/ - SPI_SSEL_ACTIVE_HI = SPI_CFG_SPOL_HI, /* SSEL is active High */ -} SPI_SSEL_POL_T; - -/** - * @brief SPI Configure Struct - */ -typedef struct { - SPI_MODE_T Mode; /* Mode Select */ - uint32_t ClockMode; /* CPHA CPOL Select */ - SPI_DATA_ORDER_T DataOrder; /* MSB/LSB First */ - SPI_SSEL_POL_T SSELPol; /* SSEL Polarity Select */ - uint16_t ClkDiv; /* SPI Clock Divider Value */ -} SPI_CONFIG_T; - -/** - * @brief SPI Delay Configure Struct - */ -typedef struct { - uint8_t PreDelay; /* Pre-delay value in SPI clock time */ - uint8_t PostDelay; /* Post-delay value in SPI clock time */ - uint8_t FrameDelay; /* Delay value between frames of a transfer in SPI clock time */ - uint8_t TransferDelay; /* Delay value between transfers in SPI clock time */ -} SPI_DELAY_CONFIG_T; - -/** - * @brief SPI data setup structure - */ -typedef struct { - uint16_t *pTx; /**< Pointer to data buffer*/ - uint32_t TxCnt;/* Transmit Counter */ - uint16_t *pRx; /**< Pointer to data buffer*/ - uint32_t RxCnt;/* Transmit Counter */ - uint32_t Length; /**< Data Length*/ - uint16_t DataSize; /** < The size of a frame (1-16)*/ -} SPI_DATA_SETUP_T; - -/** - * @brief Calculate the divider for SPI clock - * @param pSPI : The base of SPI peripheral on the chip - * @param bitRate : Expected clock rate - * @return Divider value - */ -uint32_t Chip_SPI_CalClkRateDivider(LPC_SPI_T *pSPI, uint32_t bitRate); - -/** - * @brief Config SPI Delay parameters - * @param pSPI : The base of SPI peripheral on the chip - * @param pConfig : SPI Delay Configure Struct - * @return Nothing - * @note The SPI controller is disabled - */ -void Chip_SPI_DelayConfig(LPC_SPI_T *pSPI, SPI_DELAY_CONFIG_T *pConfig); - -/** - * @brief Enable/Disable SPI interrupt - * @param pSPI : The base SPI peripheral on the chip - * @param IntMask : Interrupt mask - * @param NewState : ENABLE or DISABLE interrupt - * @return Nothing - */ -void Chip_SPI_Int_Cmd(LPC_SPI_T *pSPI, uint32_t IntMask, FunctionalState NewState); - -/** - * @brief Enable SPI peripheral - * @param pSPI : The base of SPI peripheral on the chip - * @return Nothing - */ - -/** - * @brief Enable loopback mode - * @param pSPI : The base of SPI peripheral on the chip - * @return Nothing - * @note Serial input is taken from the serial output (MOSI or MISO) rather - * than the serial input pin - */ -STATIC INLINE void Chip_SPI_EnableLoopBack(LPC_SPI_T *pSPI) -{ - pSPI->CFG = SPI_CFG_LBM_EN | (pSPI->CFG & ~SPI_CFG_RESERVED); -} - -/** - * @brief Disable loopback mode - * @param pSPI : The base of SPI peripheral on the chip - * @return Nothing - * @note Serial input is taken from the serial output (MOSI or MISO) rather - * than the serial input pin - */ -STATIC INLINE void Chip_SPI_DisableLoopBack(LPC_SPI_T *pSPI) -{ - pSPI->CFG &= (~SPI_CFG_LBM_EN) & SPI_CFG_BITMASK; -} - -/** - * @brief Set control information including SSEL, EOT, EOF RXIGNORE and FLEN - * @param pSPI : The base of SPI peripheral on the chip - * @param Flen : Data size (1-16) - * @param Flag : Flag control (Or-ed values of SPI_TXCTL_*) - * @note The control information has no effect unless data is later written to TXDAT - * @return Nothing - */ -STATIC INLINE void Chip_SPI_SetControlInfo(LPC_SPI_T *pSPI, uint8_t Flen, uint32_t Flag) -{ - pSPI->TXCTRL = Flag | SPI_TXDATCTL_FLEN(Flen - 1); -} - -/** - * @brief Send the first Frame of a transfer (Rx Ignore) - * @param pSPI : The base of SPI peripheral on the chip - * @param Data : Transmit data - * @param DataSize : Data Size (1-16) - * @return Nothing - */ -STATIC INLINE void Chip_SPI_SendFirstFrame_RxIgnore(LPC_SPI_T *pSPI, uint16_t Data, uint8_t DataSize) -{ - pSPI->TXDATCTL = SPI_TXDATCTL_ASSERT_SSEL | SPI_TXDATCTL_EOF | SPI_TXDATCTL_RXIGNORE | SPI_TXDATCTL_FLEN( - DataSize - 1) | SPI_TXDATCTL_DATA(Data); -} - -/** - * @brief Send the first Frame of a transfer - * @param pSPI : The base of SPI peripheral on the chip - * @param Data : Transmit data - * @param DataSize : Data Size (1-16) - * @return Nothing - */ -STATIC INLINE void Chip_SPI_SendFirstFrame(LPC_SPI_T *pSPI, uint16_t Data, uint8_t DataSize) -{ - pSPI->TXDATCTL = SPI_TXDATCTL_ASSERT_SSEL | SPI_TXDATCTL_EOF | SPI_TXDATCTL_FLEN(DataSize - 1) | SPI_TXDATCTL_DATA( - Data); -} - -/** - * @brief Send the middle Frame of a transfer - * @param pSPI : The base of SPI peripheral on the chip - * @param Data : Transmit data - * @return Nothing - */ -STATIC INLINE void Chip_SPI_SendMidFrame(LPC_SPI_T *pSPI, uint16_t Data) -{ - pSPI->TXDAT = SPI_TXDAT_DATA(Data); -} - -/** - * @brief Send the last Frame of a transfer (Rx Ignore) - * @param pSPI : The base of SPI peripheral on the chip - * @param Data : Transmit data - * @param DataSize : Data Size (1-16) - * @return Nothing - */ -STATIC INLINE void Chip_SPI_SendLastFrame_RxIgnore(LPC_SPI_T *pSPI, uint16_t Data, uint8_t DataSize) -{ - pSPI->TXDATCTL = SPI_TXDATCTL_ASSERT_SSEL | SPI_TXDATCTL_EOF | SPI_TXDATCTL_EOT | SPI_TXDATCTL_RXIGNORE | - SPI_TXDATCTL_FLEN(DataSize - 1) | SPI_TXDATCTL_DATA(Data); -} - -/** - * @brief Send the last Frame of a transfer - * @param pSPI : The base of SPI peripheral on the chip - * @param Data : Transmit data - * @param DataSize : Data Size (1-16) - * @return Nothing - */ -STATIC INLINE void Chip_SPI_SendLastFrame(LPC_SPI_T *pSPI, uint16_t Data, uint8_t DataSize) -{ - pSPI->TXDATCTL = SPI_TXDATCTL_ASSERT_SSEL | SPI_TXDATCTL_EOF | SPI_TXDATCTL_EOT | - SPI_TXDATCTL_FLEN(DataSize - 1) | SPI_TXDATCTL_DATA(Data); -} - -/** - * @brief Read data received - * @param pSPI : The base of SPI peripheral on the chip - * @return Receive data - */ -STATIC INLINE uint16_t Chip_SPI_ReceiveFrame(LPC_SPI_T *pSPI) -{ - return SPI_RXDAT_DATA(pSPI->RXDAT); -} - -/** - * @brief SPI Interrupt Read/Write - * @param pSPI : The base SPI peripheral on the chip - * @param xf_setup : Pointer to a SPI_DATA_SETUP_T structure that contains specified - * information about transmit/receive data configuration - * @return SUCCESS or ERROR - */ -Status Chip_SPI_Int_RWFrames(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *xf_setup); - -/** - * @brief SPI Polling Read/Write in blocking mode - * @param pSPI : The base SPI peripheral on the chip - * @param pXfSetup : Pointer to a SPI_DATA_SETUP_T structure that contains specified - * information about transmit/receive data configuration - * @return Actual data length has been transferred - * @note - * This function can be used in both master and slave mode. It starts with writing phase and after that, - * a reading phase is generated to read any data available in RX_FIFO. All needed information is prepared - * through xf_setup param. - */ -uint32_t Chip_SPI_RWFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup); - -/** - * @brief SPI Polling Write in blocking mode - * @param pSPI : The base SPI peripheral on the chip - * @param pXfSetup :Pointer to a SPI_DATA_SETUP_T structure that contains specified - * information about transmit/receive data configuration - * @return Actual data length has been transferred - * @note - * This function can be used in both master and slave mode. First, a writing operation will send - * the needed data. After that, a dummy reading operation is generated to clear data buffer - */ -uint32_t Chip_SPI_WriteFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup); - -/** - * @brief SPI Polling Read in blocking mode - * @param pSPI : The base SPI peripheral on the chip - * @param pXfSetup :Pointer to a SPI_DATA_SETUP_T structure that contains specified - * information about transmit/receive data configuration - * @return Actual data length has been read - * @note - * This function can be used in both master and slave mode. First, a writing operation will send - * the needed data. After that, a dummy reading operation is generated to clear data buffer - */ -uint32_t Chip_SPI_ReadFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup); - -/** - * @} - */ - - -/** @defgroup SPI_MASTER_8XX CHIP: LPC8XX SPI master driver - * @ingroup SPI_COMMON_8XX - * @{ - */ - -/** - * @brief Get SPI master bit rate - * @param pSPI : The base of SPI peripheral on the chip - * @return The actual SPI clock bit rate - */ -uint32_t Chip_SPIM_GetClockRate(LPC_SPI_T *pSPI); - -/** - * @brief Set SPI master bit rate - * @param pSPI : The base of SPI peripheral on the chip - * @param rate : Desired clock bit rate for the SPI interface - * @return The actual SPI clock bit rate - * @note This function will set the SPI clock divider to get closest - * to the desired rate as possible. - */ -uint32_t Chip_SPIM_SetClockRate(LPC_SPI_T *pSPI, uint32_t rate); - -/** - * @brief SPI Delay Configure Struct - */ -typedef struct { - uint8_t PreDelay; /** Pre-delay value in SPI clocks, 0 - 15 */ - uint8_t PostDelay; /** Post-delay value in SPI clocks, 0 - 15 */ - uint8_t FrameDelay; /** Delay value between frames of a transfer in SPI clocks, 0 - 15 */ - uint8_t TransferDelay; /** Delay value between transfers in SPI clocks, 1 - 16 */ -} SPIM_DELAY_CONFIG_T; - -/** - * @brief Config SPI Delay parameters - * @param pSPI : The base of SPI peripheral on the chip - * @param pConfig : SPI Delay Configure Struct - * @return Nothing - */ -void Chip_SPIM_DelayConfig(LPC_SPI_T *pSPI, SPIM_DELAY_CONFIG_T *pConfig); - -/** - * @brief Forces an end of transfer for the current master transfer - * @param pSPI : The base of SPI peripheral on the chip - * @return Nothing - * @note Use this function to perform an immediate end of trasnfer for the - * current master operation. If the master is currently transferring data started - * with the Chip_SPIM_Xfer function, this terminates the transfer after the - * current byte completes and completes the transfer. - */ -STATIC INLINE void Chip_SPIM_ForceEndOfTransfer(LPC_SPI_T *pSPI) -{ - pSPI->STAT = SPI_STAT_EOT; -} - -/** - * @brief Assert a SPI select - * @param pSPI : The base of SPI peripheral on the chip - * @param sselNum : SPI select to assert, 0 - 3 - * @return Nothing - */ -void Chip_SPIM_AssertSSEL(LPC_SPI_T *pSPI, uint8_t sselNum); - -/** - * @brief Deassert a SPI select - * @param pSPI : The base of SPI peripheral on the chip - * @param sselNum : SPI select to deassert, 0 - 3 - * @return Nothing - */ -void Chip_SPIM_DeAssertSSEL(LPC_SPI_T *pSPI, uint8_t sselNum); - -/** - * @brief Enable loopback mode - * @param pSPI : The base of SPI peripheral on the chip - * @return Nothing - * @note Serial input is taken from the serial output (MOSI or MISO) rather - * than the serial input pin. - */ -STATIC INLINE void Chip_SPIM_EnableLoopBack(LPC_SPI_T *pSPI) -{ - Chip_SPI_SetCFGRegBits(pSPI, SPI_CFG_LBM_EN); -} - -/** - * @brief Disable loopback mode - * @param pSPI : The base of SPI peripheral on the chip - * @return Nothing - */ -STATIC INLINE void Chip_SPIM_DisableLoopBack(LPC_SPI_T *pSPI) -{ - Chip_SPI_ClearCFGRegBits(pSPI, SPI_CFG_LBM_EN); -} - -struct SPIM_XFER; - -/** @brief SPI master select assert callback - * This callback is called from the SPI master handler when the SPI master - * selects the slave (asserts SSEL). - */ -typedef void (*SPIMasterXferCSAssert)(struct SPIM_XFER *pMasterXfer); - -/** @brief SPI master send data callback - * This callback is called from the SPI master handler when the SPI master - * needs a data buffer to send. - */ -typedef void (*SPIMasterXferSend)(struct SPIM_XFER *pMasterXfer); - -/** @brief SPI master receive data callback - * This callback is called from the SPI master handler when the SPI master - * needs a buffer to place data into. - */ -typedef void (*SPIMasterXferRecv)(struct SPIM_XFER *pMasterXfer); - -/** @brief SPI master transfer select deassert data callback - * This callback is called from the SPI master handler when the SPI master - * deasserts the slave select. - */ -typedef void (*SPIMMasterXferCSDeAssert)(struct SPIM_XFER *pMasterXfer); - -/** @brief SPI master transfer done data callback - * This callback is called from the SPI master handler when the SPI master - * has completed the transfer and becomes idle. - */ -typedef void (*SPIMMasterXferDone)(struct SPIM_XFER *pMasterXfer); - -/** SPI slave callback functions */ -typedef struct { - SPIMasterXferCSAssert masterXferCSAssert; /** SPI transfer CS assert, called when a slave select is asserted */ - SPIMasterXferSend masterXferSend; /** SPI transfer data receive buffer callback, called when a send buffer is needed */ - SPIMasterXferRecv masterXferRecv; /** SPI transfer send buffer callback, called when send buffer is needed (and SPI_TXCTL_RXIGNORE option is not set) */ - SPIMMasterXferCSDeAssert mMasterXferCSDeAssert; /** SPI transfer CS deassert, called when a slave select is deasserted */ - SPIMMasterXferDone mMasterXferDone; /** SPI transfer done callback, called when transfer is complete */ -} SPIM_CALLBACKS_T; - -/** Slave transfer data context */ -typedef struct SPIM_XFER { - const SPIM_CALLBACKS_T *pCB; /** Pointer to SPI master data callback functions */ - union { /** Pointer to receive buffer, set to NULL to toss receeive data */ - uint8_t *pRXData8; /** Receive buffer used with data transfer size <= 8-bits, modified by driver */ - uint16_t *pRXData16; /** Receive buffer used with data transfer size > 8-bits, modified by driver */ - }; - - union { /** Pointer to transmit buffer, set to NULL to transmit 0x0 */ - uint8_t *pTXData8; /** Send buffer used with data transfer size <= 8-bits, modified by driver */ - uint16_t *pTXData16; /** Send buffer used with data transfer size > 8-bits, modified by driver */ - }; - - uint32_t options; /** Master transfer options, an OR'ed value of SPI_TXCTL_EOT, SPI_TXCTL_EOF, SPI_TXCTL_RXIGNORE, and SPI_TXCTL_FLEN(bits) */ - uint16_t rxCount; /** Size of the pRXData buffer in items (not bytes), modified by driver */ - uint16_t txCount; /** Number of items (not bytes) to send in pTXData buffer, modified by driver */ - uint16_t dataRXferred; /** Total items (not bytes) received, modified by driver */ - uint16_t dataTXferred; /** Total items (not bytes) transmitted, modified by driver */ - uint8_t sselNum; /** Slave number assigned to this transfer, 0 - 3, used by driver to select slave */ - bool terminate; /** Transfer will terminate when txCount goes to 0 and master goes idle, must be set before last byte is sent */ -} SPIM_XFER_T; - -/** - * @brief SPI master transfer state change handler - * @param pSPI : The base of SPI peripheral on the chip - * @param xfer : Pointer to a SPIM_XFER_T structure see notes below - * @return Nothing - * @note See @ref SPIM_XFER_T for more information on this function. When using - * this function, the SPI master interrupts should be enabled and setup in the SPI - * interrupt handler to call this function when they fire. This function is meant - * to be called from the interrupt handler. - */ -void Chip_SPIM_XferHandler(LPC_SPI_T *pSPI, SPIM_XFER_T *xfer); - -/** - * @brief Start non-blocking SPI master transfer - * @param pSPI : The base of SPI peripheral on the chip - * @param xfer : Pointer to a SPIM_XFER_T structure see notes below - * @return Nothing - * @note This function starts a non-blocking SPI master transfer with the - * parameters setup in the passed @ref SPIM_XFER_T structure. Once the transfer is - * started, the interrupt handler must call Chip_SPIM_XferHandler to keep the - * transfer going and fed with data. This function should only be called when - * the master is idle.
- * - * This function must be called with the options and sselNum fields correctly - * setup. Initial data buffers and the callback pointer must also be setup. No - * sanity checks are performed on the passed data.
- * - * Example call:
- * SPIM_XFER_T mxfer; - * mxfer.pCB = &masterCallbacks; - * mxfer.sselNum = 2; // Use chip select 2 - * mxfer.options = SPI_TXCTL_FLEN(8); // 8 data bits, supports 1 - 16 bits - * mxfer.options |= SPI_TXCTL_EOT | SPI_TXCTL_EOF; // Apply frame and transfer delays to master transfer - * mxfer.options |= SPI_TXCTL_RXIGNORE; // Ignore RX data, will toss receive data regardless of pRXData8 or pRXData16 buffer - * mxfer.pTXData8 = SendBuffer; - * mxfer.txCount = 16; // Number of bytes to send before SPIMasterXferSend callback is called - * mxfer.pRXData8 = RecvBuffer; // Will not receive data if pRXData8/pRXData16 is NULL or SPI_TXCTL_RXIGNORE option is set - * mxfer.rxCount = 16; // Number of bytes to receive before SPIMasterXferRecv callback is called - * Chip_SPIM_Xfer(LPC_SPI0, &mxfer); // Start transfer - * - * Note that the transfer, once started, needs to be constantly fed by the callbacks. - * The txCount and rxCount field only indicate the buffer size before the callbacks are called. - * To terminate the transfer, the SPIMasterXferSend callback must set the terminate field. - */ -void Chip_SPIM_Xfer(LPC_SPI_T *pSPI, SPIM_XFER_T *xfer); - -/** - * @brief Perform blocking SPI master transfer - * @param pSPI : The base of SPI peripheral on the chip - * @param xfer : Pointer to a SPIM_XFER_T structure see notes below - * @return Nothing - * @note This function starts a blocking SPI master transfer with the - * parameters setup in the passed @ref SPIM_XFER_T structure. Once the transfer is - * started, the callbacks in Chip_SPIM_XferHandler may be called to keep the - * transfer going and fed with data. SPI interrupts must be disabled prior to - * calling this function. It is not recommended to use this function.
- */ -void Chip_SPIM_XferBlocking(LPC_SPI_T *pSPI, SPIM_XFER_T *xfer); - -/** - * @} - */ - - -/** @defgroup SPI_SLAVE_8XX CHIP: LPC8XX SPI slave driver - * @ingroup SPI_COMMON_8XX - * @{ - */ - -/** - * Macro defines for SPI Status register - */ - -/* Clear RXOV Flag */ -#define SPI_STAT_CLR_RXOV ((uint32_t) (1 << 2)) -/* Clear TXUR Flag */ -#define SPI_STAT_CLR_TXUR ((uint32_t) (1 << 3)) -/* Clear SSA Flag */ -#define SPI_STAT_CLR_SSA ((uint32_t) (1 << 4)) -/* Clear SSD Flag */ -#define SPI_STAT_CLR_SSD ((uint32_t) (1 << 5)) - -struct SPIS_XFER; - -/** @brief SPI slave select assertion callback - * This callback is called from the SPI slave handler when an SPI slave select (SSEL) - * is initially asserted. It is used to indicate the start of a slave transfer that - * will happen on the bus. - */ -typedef void (*SPISlaveXferCSAssert)(struct SPIS_XFER *pSlaveXfer); - -/** @brief SPI slave send data callback - * This callback is called from the SPI slave handler when an SPI slave select (SSEL) - * needs a data buffer to send. - */ -typedef void (*SPISlaveXferSend)(struct SPIS_XFER *pSlaveXfer); - -/** @brief SPI slave receive data callback - * This callback is called from the SPI slave handler when an SPI slave select (SSEL) - * needs a buffer to place data. - */ -typedef void (*SPISlaveXferRecv)(struct SPIS_XFER *pSlaveXfer); - -/** @brief SPI slave select de-assertion callback - * This callback is called from the SPI slave handler when an SPI slave select (SSEL) - * is de-asserted. It can be used to indicate the end of a transfer. - */ -typedef void (*SPISlaveXferCSDeAssert)(struct SPIS_XFER *pSlaveXfer); - -/** SPI slave callback functions */ -typedef struct { - SPISlaveXferCSAssert slaveXferCSAssert; /** SPI transfer start callback, called on SPI CS assertion */ - SPISlaveXferSend slaveXferSend; /** SPI transfer data receive buffer callback, called when a receive buffer is needed */ - SPISlaveXferRecv slaveXferRecv; /** SPI transfer send buffer callback, called when data is needed */ - SPISlaveXferCSDeAssert slaveXferCSDeAssert; /** SPI transfer completion callback, called on SPI CS deassertion */ -} SPIS_CALLBACKS_T; - -/** Slave transfer data context */ -typedef struct SPIS_XFER { - const SPIS_CALLBACKS_T *pCB; /** Pointer to SPI slave callback functions */ - union { /** Pointer to receive buffer, set to NULL to toss receeive data */ - uint8_t *pRXData8; /** Receive buffer used with data transfer size <= 8-bits, modified by driver */ - uint16_t *pRXData16; /** Receive buffer used with data transfer size > 8-bits, modified by driver */ - }; - - union { /** Pointer to transmit buffer, set to NULL to transmit 0x0 */ - uint8_t *pTXData8; /** Send buffer used with data transfer size <= 8-bits, modified by driver */ - uint16_t *pTXData16; /** Send buffer used with data transfer size > 8-bits, modified by driver */ - }; - - uint16_t rxCount; /** Size of the pRXData buffer in items (not bytes), modified by driver */ - uint16_t txCount; /** Number of items (not bytes) to send in pTXData buffer, modified by driver */ - uint16_t dataRXferred; /** Total items (not bytes) received, modified by driver */ - uint16_t dataTXferred; /** Total items (not bytes) transmitted, modified by driver */ - uint8_t sselNum; /** Slave number assigned to this transfer, 0 - 3, modified by driver */ -} SPIS_XFER_T; - -/** - * @brief SPI slave transfer state change handler - * @param pSPI : The base of SPI peripheral on the chip - * @param xfer : Pointer to a SPIS_XFER_T structure see notes below - * @return returns 0 on success, or SPI_STAT_RXOV and/or SPI_STAT_TXUR on an error - * @note See @ref SPIS_XFER_T for more information on this function. When using - * this function, the SPI slave interrupts should be enabled and setup in the SPI - * interrupt handler to call this function when they fire. This function is meant - * to be called from the interrupt handler. The @ref SPIS_XFER_T data does not need - * to be setup prior to the call and should be setup by the callbacks instead.
- * - * The callbacks are handled in the interrupt handler. If you are getting overflow - * or underflow errors, you might need to lower the speed of the master clock or - * extend the master's select assetion time.
- */ -uint32_t Chip_SPIS_XferHandler(LPC_SPI_T *pSPI, SPIS_XFER_T *xfer); - -/** - * @brief Pre-buffers slave transmit data - * @param pSPI : The base of SPI peripheral on the chip - * @param xfer : Pointer to a SPIS_XFER_T structure see notes below - * @return Nothing - * @note Pre-buffering allows the slave to prime the transmit FIFO with data prior to - * the master starting a transfer. If data is not pre-buffered, the initial slave - * transmit data will always be 0x0 with a slave transmit underflow status. - * Pre-buffering is best used when only a single slave select is used by an - * application. - */ -STATIC INLINE void Chip_SPIS_PreBuffSlave(LPC_SPI_T *pSPI, SPIS_XFER_T *xfer) -{ - Chip_SPIS_XferHandler(pSPI, xfer); -} - -/** - * @brief SPI slave transfer blocking function - * @param pSPI : The base of SPI peripheral on the chip - * @param xfer : Pointer to a SPIS_XFER_T structure - * @return returns 0 on success, or SPI_STAT_RXOV and/or SPI_STAT_TXUR on an error - * @note This function performs a blocking transfer on the SPI slave interface. - * It is not recommended to use this function. Once this function is called, it - * will block forever until a slave transfer consisting of a slave SSEL assertion, - * and de-assertion occur. The callbacks are still used for slave data buffer - * management. SPI interrupts must be disabled prior to calling this function. - */ -uint32_t Chip_SPIS_XferBlocking(LPC_SPI_T *pSPI, SPIS_XFER_T *xfer); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __SPI_8XX_H__ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/uart/ring_buffer.c b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/uart/ring_buffer.c deleted file mode 100644 index de420452d28..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/uart/ring_buffer.c +++ /dev/null @@ -1,177 +0,0 @@ -/* -* @brief Common ring buffer support functions -* -* @note -* Copyright(C) NXP Semiconductors, 2012 -* All rights reserved. -* -* @par -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* LPC products. This software is supplied "AS IS" without any warranties of -* any kind, and NXP Semiconductors and its licensor disclaim any and -* all warranties, express or implied, including all implied warranties of -* merchantability, fitness for a particular purpose and non-infringement of -* intellectual property rights. NXP Semiconductors assumes no responsibility -* or liability for the use of the software, conveys no license or rights under any -* patent, copyright, mask work right, or any other intellectual property rights in -* or to any products. NXP Semiconductors reserves the right to make changes -* in the software without notification. NXP Semiconductors also makes no -* representation or warranty that such application will be suitable for the -* specified use without further testing or modification. -* -* @par -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' and its -* licensor's relevant copyrights in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -*/ - -#include "ring_buffer.h" - - - -int32_t RingBuf_Init(ring_buffer_t* pRB, uint8_t* buffer, uint32_t size ) -{ - pRB->pBuf = (uint8_t*)buffer; - pRB->size = size; - pRB->rNdx = 0; - pRB->wNdx = 0; - pRB->cnt = 0; - return 0; -} - -int32_t RingBuf_Deinit(ring_buffer_t* pRB ) -{ - pRB = pRB;; - return 0; -} - -int32_t RingBuf_GetFreeBytes(ring_buffer_t* pRB ) -{ - return pRB->size - pRB->cnt; -} - -int32_t RingBuf_GetUsedBytes(ring_buffer_t* pRB) -{ - return pRB->cnt; -} - -int32_t RingBuf_Write(ring_buffer_t* pRB, const uint8_t* data, uint32_t dataBytes) -{ - uint32_t writeToEnd, bytesToCopy; - INIT_CRITICAL(); - ENTER_CRITICAL(); - /* Calculate the maximum amount we can copy */ - writeToEnd = pRB->size - pRB->wNdx; - bytesToCopy = MIN(dataBytes, pRB->size - pRB->cnt); - - if (bytesToCopy != 0) - { - /* Copy as much as we can until we fall off the end of the buffer */ - memcpy(&pRB->pBuf[pRB->wNdx], data, MIN(bytesToCopy, writeToEnd)); - - /* Check if we have more to copy to the front of the buffer */ - if (writeToEnd < bytesToCopy) - { - memcpy(pRB->pBuf, data + writeToEnd, bytesToCopy - writeToEnd); - } - - /* Update the wNdx */ - - pRB->wNdx = (pRB->wNdx + bytesToCopy) % pRB->size; - pRB->cnt += dataBytes; - } - LEAVE_CRITICAL(); - return bytesToCopy; -} - -int32_t RingBuf_Write1Byte(ring_buffer_t* pRB, const uint8_t *pcData) -{ - uint32_t ret = 0; - INIT_CRITICAL(); - ENTER_CRITICAL(); - if (pRB->cnt < pRB->size) - { - pRB->pBuf[pRB->wNdx] = pcData[0]; - pRB->wNdx = (pRB->wNdx + 1) % pRB->size; - pRB->cnt++; - ret = 1; - } - LEAVE_CRITICAL(); - return ret; -} - -int32_t _prvRingBuf_Read(ring_buffer_t* pRB, uint8_t* data, uint32_t dataBytes, uint32_t isToFree) -{ - uint32_t readToEnd, bytesToCopy; - INIT_CRITICAL(); - ENTER_CRITICAL(); - readToEnd = pRB->size - pRB->rNdx; - bytesToCopy = MIN(dataBytes, pRB->cnt); - if (bytesToCopy != 0) - { - memcpy(data, &pRB->pBuf[pRB->rNdx], MIN(bytesToCopy, readToEnd)); - - if (readToEnd < bytesToCopy) - memcpy(data + readToEnd, &pRB->pBuf[0], bytesToCopy - readToEnd); - - if (isToFree) - { - pRB->rNdx = (pRB->rNdx + bytesToCopy) % pRB->size; - pRB->cnt -= bytesToCopy; - } - } - LEAVE_CRITICAL(); - - return bytesToCopy; -} - -int32_t RingBuf_Read(ring_buffer_t* pRB, uint8_t* data, uint32_t dataBytes) -{ - return _prvRingBuf_Read(pRB, data, dataBytes, 1); -} - -int32_t RingBuf_Copy(ring_buffer_t* pRB, uint8_t* data, uint32_t dataBytes) -{ - return _prvRingBuf_Read(pRB, data, dataBytes, 0); -} - -int32_t RingBuf_Read1Byte(ring_buffer_t* pRB, uint8_t *pData) -{ - uint32_t ret = 0; - INIT_CRITICAL(); - ENTER_CRITICAL(); - if (pRB->cnt != 0) - { - pData[0] = pRB->pBuf[pRB->rNdx]; - pRB->rNdx = (pRB->rNdx + 1) % pRB->size; - pRB->cnt--; - ret = 1; - } - LEAVE_CRITICAL(); - return ret; -} - -int32_t RingBuf_Peek(ring_buffer_t* pRB, uint8_t **ppData) -{ - uint32_t readToEnd = pRB->size - pRB->rNdx; - uint32_t contiguousBytes; - *ppData = &(pRB->pBuf[pRB->rNdx]); - contiguousBytes = MIN(readToEnd, (readToEnd + pRB->wNdx) % pRB->size); - return contiguousBytes; -} - -int32_t RingBuf_Free(ring_buffer_t* pRB, uint32_t bytesToFree) -{ - INIT_CRITICAL(); - ENTER_CRITICAL(); - pRB->rNdx = (pRB->rNdx + bytesToFree) % pRB->size; - pRB->cnt -= bytesToFree; - LEAVE_CRITICAL(); - return bytesToFree; -} - - diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/uart/ring_buffer.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/uart/ring_buffer.h deleted file mode 100644 index ef02dc01f2a..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/uart/ring_buffer.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * @brief Common ring buffer support functions - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __RING_BUFFER_H_ -#define __RING_BUFFER_H_ -#include -#include - -#define RINGBUF_IRQ_SAFE -#ifdef RINGBUF_IRQ_SAFE -#include -#define INIT_CRITICAL() uint32_t priMask = __get_PRIMASK() -#define ENTER_CRITICAL() __set_PRIMASK(1) -#define LEAVE_CRITICAL() __set_PRIMASK(priMask) -#else -#define INIT_CRITICAL() -#define ENTER_CRITICAL() -#define LEAVE_CRITICAL() - -#endif - -typedef struct -{ - uint8_t *pBuf; - uint32_t size; - uint32_t cnt; - uint32_t rNdx; - uint32_t wNdx; - -} ring_buffer_t, RINGBUFF_T; - -#ifndef MIN -#define MIN(x,y) ((x) < (y) ? (x) : (y)) -#endif /* ifndef MIN */ - -/** - * @brief Create and initialize a ring buffer - * @param pRB : pointer to ring buffer instance - * @param pBuffer: pointer to the buffer for ring buffer data - * @param size: The size of buffer pointed by pBuffer - * @return >=0:Success ; <0:Failed - */ -int32_t RingBuf_Init(ring_buffer_t *pRB, uint8_t *pBuffer, uint32_t size); - -/** - * @brief Write new data to buffer - * @param pRB : pointer to the ring buffer instance - * @param pcData: point to data array that will be written to ring buffer - * @param dataBytes: bytes to write - * @return >=0:Bytes written ; <0:Failed - * @remark This function updates the ring buffer - */ -int32_t RingBuf_Write(ring_buffer_t* pRB, const uint8_t *pcData, uint32_t dataBytes); - -/** - * @brief Write 1 new byte data to buffer - * @param pRB : pointer to the ring buffer instance - * @param pcData: point to data byte that will be written to ring buffer - * @return 1:success; otherwise failed - * @remark This function updates the ring buffer. Optimized for byte-by-byte write - */ -int32_t RingBuf_Write1Byte(ring_buffer_t* pRB, const uint8_t *pcData); - -/** - * @brief Read (copy and remove) data from ring buffer - * @param pRB : pointer to the ring buffer instance - * @param pData : pointer to data array that receives read data - * @param dataBytes: bytes to copy - * @return >=0:Bytes read ; <0:Failed - * @remark This function updates the ring buffer. - */ -int32_t RingBuf_Read(ring_buffer_t* pRB, uint8_t *pData, uint32_t dataBytes); - -/** - * @brief Read (copy and remove) 1 oldest byte data from buffer - * @param pRB : pointer to the ring buffer instance - * @param pData: point to data byte that will receive the oldest byte - * @return 1:success ; otherwise failed - * @remark This function updates the ring buffer. Optimized for byte-by-byte read - */ -int32_t RingBuf_Read1Byte(ring_buffer_t* pRB, uint8_t *pData); - -/** - * @brief Copy but does NOT remove data from ring buffer - * @param pRB : pointer to the ring buffer instance - * @param pData : pointer to data array that receives read data - * @param dataBytes: bytes to read - * @return >=0:Read bytes ; <0:Failed - */ -int32_t RingBuf_Copy(ring_buffer_t* pRB, uint8_t *pData, uint32_t dataBytes); - -/** - * @brief Get data pointer to oldest byte in ring buffer, and contigous byte count - * @param pRB : pointer to the ring buffer instance - * @param ppData : pointer to pointer variable that will be updated to point to oldest byte - * @param contiguous_bytes: Congigous bytes until roll back - * @return >=0:Contiuous bytes until roll back or whole data (if roll back won't happen) ; <0:Failed - * @remak Use this function if performance is critical since it does NOT copy data - * Use RingBuf_Free() to free (remove) data after use - */ -int32_t RingBuf_Peek(ring_buffer_t* pRB, uint8_t **ppData); - -/** - * @brief Free (remove) data from ring buffer - * @param pRB : pointer to the ring buffer instance - * @param bytesToFree : Bytes to free (remove) - * @remak Use this function to free data after data get from RingBuf_Peek() is used - */ -int32_t RingBuf_Free(ring_buffer_t* pRB, uint32_t bytesToFree); - -/** - * @brief Get free bytes of ring buffer - * @param pRB : pointer to the ring buffer instance - * @return >=0:Free bytes ; <0:Failed - */ -int32_t RingBuf_GetFreeBytes(ring_buffer_t* pRB); - -/** - * @brief Get free bytes of ring buffer - * @param pRB : pointer to the ring buffer instance - * @return >=0:Used bytes ; <0:Failed - */ -int32_t RingBuf_GetUsedBytes(ring_buffer_t* pRB); - -/** - * @} - */ - -#endif /* __RING_BUFFER_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/uart/uart_8xx.c b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/uart/uart_8xx.c deleted file mode 100644 index 5b40874eae2..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/uart/uart_8xx.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * @brief LPC8xx UART driver - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licenser disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" -#include "uart_8xx.h" -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/* Return UART clock ID from the UART register address */ -static CHIP_SYSCTL_CLOCK_T getUARTClockID(LPC_USART_T *pUART) -{ - if (pUART == LPC_USART0) { - return SYSCTL_CLOCK_UART0; - } - else if (pUART == LPC_USART1) { - return SYSCTL_CLOCK_UART1; - } - - return SYSCTL_CLOCK_UART2; -} - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Initialize the UART peripheral */ -void Chip_UART_Init(LPC_USART_T *pUART) -{ - /* Enable USART clock */ - Chip_Clock_EnablePeriphClock(getUARTClockID(pUART)); - - /* UART reset */ - if (pUART == LPC_USART0) { - /* Peripheral reset control to USART0 */ - Chip_SYSCTL_PeriphReset(RESET_USART0); - } - else if (pUART == LPC_USART1) { - /* Peripheral reset control to USART1 */ - Chip_SYSCTL_PeriphReset(RESET_USART1); - } - else { - /* Peripheral reset control to USART2 */ - Chip_SYSCTL_PeriphReset(RESET_USART2); - } -} - -/* Initialize the UART peripheral */ -void Chip_UART_DeInit(LPC_USART_T *pUART) -{ - /* Disable USART clock */ - Chip_Clock_DisablePeriphClock(getUARTClockID(pUART)); -} - -/* Transmit a byte array through the UART peripheral (non-blocking) */ -int Chip_UART_Send(LPC_USART_T *pUART, const void *data, int numBytes) -{ - int sent = 0; - uint8_t *p8 = (uint8_t *) data; - - /* Send until the transmit FIFO is full or out of bytes */ - while ((sent < numBytes) && - ((Chip_UART_GetStatus(pUART) & UART_STAT_TXRDY) != 0)) { - Chip_UART_SendByte(pUART, *p8); - p8++; - sent++; - } - - return sent; -} - -/* Transmit a byte array through the UART peripheral (blocking) */ -int Chip_UART_SendBlocking(LPC_USART_T *pUART, const void *data, int numBytes) -{ - int pass, sent = 0; - uint8_t *p8 = (uint8_t *) data; - - while (numBytes > 0) { - pass = Chip_UART_Send(pUART, p8, numBytes); - numBytes -= pass; - sent += pass; - p8 += pass; - } - - return sent; -} - -/* Read data through the UART peripheral (non-blocking) */ -int Chip_UART_Read(LPC_USART_T *pUART, void *data, int numBytes) -{ - int readBytes = 0; - uint8_t *p8 = (uint8_t *) data; - - /* Send until the transmit FIFO is full or out of bytes */ - while ((readBytes < numBytes) && - ((Chip_UART_GetStatus(pUART) & UART_STAT_RXRDY) != 0)) { - *p8 = Chip_UART_ReadByte(pUART); - p8++; - readBytes++; - } - - return readBytes; -} - -/* Read data through the UART peripheral (blocking) */ -int Chip_UART_ReadBlocking(LPC_USART_T *pUART, void *data, int numBytes) -{ - int pass, readBytes = 0; - uint8_t *p8 = (uint8_t *) data; - - while (numBytes > 0) { - pass = Chip_UART_Read(pUART, p8, numBytes); - numBytes -= pass; - readBytes += pass; - p8 += pass; - } - - return readBytes; -} - -/* Set baud rate for UART */ -void Chip_UART_SetBaud(LPC_USART_T *pUART, uint32_t baudrate) -{ - uint32_t baudRateGenerator; - baudRateGenerator = Chip_Clock_GetUSARTNBaseClockRate() / (16 * baudrate); - pUART->BRG = baudRateGenerator - 1; /* baud rate */ -} - -/* UART receive-only interrupt handler for ring buffers */ -void Chip_UART_RXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB) -{ - /* New data will be ignored if data not popped in time */ - while ((Chip_UART_GetStatus(pUART) & UART_STAT_RXRDY) != 0) { - uint8_t ch = Chip_UART_ReadByte(pUART); - RingBuf_Write(pRB, &ch, 1); - } -} - -/* UART transmit-only interrupt handler for ring buffers */ -void Chip_UART_TXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB) -{ - uint8_t ch; - - /* Fill FIFO until full or until TX ring buffer is empty */ - while (((Chip_UART_GetStatus(pUART) & UART_STAT_TXRDY) != 0) && - RingBuf_Read(pRB, &ch, 1)) { - Chip_UART_SendByte(pUART, ch); - } -} - -/* Populate a transmit ring buffer and start UART transmit */ -uint32_t Chip_UART_SendRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, const void *data, int count) -{ - uint32_t ret; - uint8_t *p8 = (uint8_t *) data; - - /* Don't let UART transmit ring buffer change in the UART IRQ handler */ - Chip_UART_IntDisable(pUART, UART_INTEN_TXRDY); - - /* Move as much data as possible into transmit ring buffer */ - ret = RingBuf_Write(pRB, p8, count); - Chip_UART_TXIntHandlerRB(pUART, pRB); - - /* Add additional data to transmit ring buffer if possible */ - ret += RingBuf_Write(pRB, (p8 + ret), (count - ret)); - - /* Enable UART transmit interrupt */ - Chip_UART_IntEnable(pUART, UART_INTEN_TXRDY); - - return ret; -} - -/* Copy data from a receive ring buffer */ -int Chip_UART_ReadRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, void *data, int bytes) -{ - (void) pUART; - - return RingBuf_Read(pRB, (uint8_t *) data, bytes); -} - -/* UART receive/transmit interrupt handler for ring buffers */ -void Chip_UART_IRQRBHandler(LPC_USART_T *pUART, RINGBUFF_T *pRXRB, RINGBUFF_T *pTXRB) -{ - /* Handle transmit interrupt if enabled */ - if ((Chip_UART_GetStatus(pUART) & UART_STAT_TXRDY) != 0) { - Chip_UART_TXIntHandlerRB(pUART, pTXRB); - - /* Disable transmit interrupt if the ring buffer is empty */ - if (RingBuf_GetFreeBytes(pTXRB) == 0) { - Chip_UART_IntDisable(pUART, UART_INTEN_TXRDY); - } - } - - /* Handle receive interrupt */ - Chip_UART_RXIntHandlerRB(pUART, pRXRB); -} diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/uart/uart_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/uart/uart_8xx.h deleted file mode 100644 index fd320b78e92..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/uart/uart_8xx.h +++ /dev/null @@ -1,491 +0,0 @@ -/* - * @brief LPC8xx UART driver - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __UART_8XX_H_ -#define __UART_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ring_buffer.h" - -/** @defgroup UART_8XX CHIP: LPC8xx UART Driver - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/** - * @brief UART register block structure - */ -typedef struct { - __IO uint32_t CFG; /*!< Configuration register */ - __IO uint32_t CTRL; /*!< Control register */ - __IO uint32_t STAT; /*!< Status register */ - __IO uint32_t INTENSET; /*!< Interrupt Enable read and set register */ - __O uint32_t INTENCLR; /*!< Interrupt Enable clear register */ - __I uint32_t RXDATA; /*!< Receive Data register */ - __I uint32_t RXDATA_STAT; /*!< Receive Data with status register */ - __IO uint32_t TXDATA; /*!< Transmit data register */ - __IO uint32_t BRG; /*!< Baud Rate Generator register */ - __IO uint32_t INTSTAT; /*!< Interrupt status register */ - __IO uint32_t OSR; /*!< Oversampling Selection regiser */ - __IO uint32_t ADDR; /*!< Address register for automatic address matching */ -} LPC_USART_T; - -/** - * @brief UART CFG register definitions - */ -#define UART_CFG_ENABLE (0x01 << 0) -#define UART_CFG_DATALEN_7 (0x00 << 2) /*!< UART 7 bit length mode */ -#define UART_CFG_DATALEN_8 (0x01 << 2) /*!< UART 8 bit length mode */ -#define UART_CFG_DATALEN_9 (0x02 << 2) /*!< UART 9 bit length mode */ -#define UART_CFG_PARITY_NONE (0x00 << 4) /*!< No parity */ -#define UART_CFG_PARITY_EVEN (0x02 << 4) /*!< Even parity */ -#define UART_CFG_PARITY_ODD (0x03 << 4) /*!< Odd parity */ -#define UART_CFG_STOPLEN_1 (0x00 << 6) /*!< UART One Stop Bit Select */ -#define UART_CFG_STOPLEN_2 (0x01 << 6) /*!< UART Two Stop Bits Select */ -#define UART_CFG_CTSEN (0x01 << 9) /*!< CTS enable bit */ -#define UART_CFG_SYNCEN (0x01 << 11) /*!< Synchronous mode enable bit */ -#define UART_CFG_CLKPOL (0x01 << 12) /*!< Un_RXD rising edge sample enable bit */ -#define UART_CFG_SYNCMST (0x01 << 14) /*!< Select master mode (synchronous mode) enable bit */ -#define UART_CFG_LOOP (0x01 << 15) /*!< Loopback mode enable bit */ - -#ifdef CHIP_LPC82X /* LPC82X specific bits */ -#define UART_CFG_OETA (0x01 << 18) /*!< Output Enable Turnaround time for RS485 */ -#define UART_CFG_AUTOADDR (0x01 << 19) /*!< Automatic address matching enable */ -#define UART_CFG_OESEL (0x01 << 20) /*!< Output enable select */ -#define UART_CFG_OEPOL (0x01 << 21) /*!< Output enable polarity */ -#define UART_CFG_RXPOL (0x01 << 22) /*!< Receive data polarity */ -#define UART_CFG_TXPOL (0x01 << 22) /*!< Transmit data polarity */ -#define UART_CFG_RESERVED ((1<<1)|(1<<7)|(1<<8)|(1<<10)|(1<<13)|(3 << 16)|(0xffu<<24)) -#else -#define UART_CFG_RESERVED ((1<<1)|(1<<7)|(1<<8)|(1<<10)|(1<<13)|(0xffffu<<16)) -#endif - -/** - * @brief UART CTRL register definitions - */ -#define UART_CTRL_TXBRKEN (0x01 << 1) /*!< Continuous break enable bit */ -#define UART_CTRL_ADDRDET (0x01 << 2) /*!< Address detect mode enable bit */ -#define UART_CTRL_TXDIS (0x01 << 6) /*!< Transmit disable bit */ -#define UART_CTRL_CC (0x01 << 8) /*!< Continuous Clock mode enable bit */ -#define UART_CTRL_CLRCC (0x01 << 9) /*!< Clear Continuous Clock bit */ -#ifdef CHIP_LPC82X -#define UART_CTRL_AUTOBAUD (1 << 16) /*!< Enable UART Autobaud */ -#define UART_CTRL_RESERVED (0xFFFEFCB9U) -#else -#define UART_CTRL_RESERVED (1|(7<<3)|(1<<7)|0xfffffc00u) -#endif - -/** - * @brief UART STAT register definitions - */ -#define UART_STAT_RXRDY (0x01 << 0) /*!< Receiver ready */ -#define UART_STAT_RXIDLE (0x01 << 1) /*!< Receiver idle */ -#define UART_STAT_TXRDY (0x01 << 2) /*!< Transmitter ready for data */ -#define UART_STAT_TXIDLE (0x01 << 3) /*!< Transmitter idle */ -#define UART_STAT_CTS (0x01 << 4) /*!< Status of CTS signal */ -#define UART_STAT_DELTACTS (0x01 << 5) /*!< Change in CTS state */ -#define UART_STAT_TXDISINT (0x01 << 6) /*!< Transmitter disabled */ -#define UART_STAT_OVERRUNINT (0x01 << 8) /*!< Overrun Error interrupt flag. */ -#define UART_STAT_RXBRK (0x01 << 10) /*!< Received break */ -#define UART_STAT_DELTARXBRK (0x01 << 11) /*!< Change in receive break detection */ -#define UART_STAT_START (0x01 << 12) /*!< Start detected */ -#define UART_STAT_FRM_ERRINT (0x01 << 13) /*!< Framing Error interrupt flag */ -#define UART_STAT_PAR_ERRINT (0x01 << 14) /*!< Parity Error interrupt flag */ -#define UART_STAT_RXNOISEINT (0x01 << 15) /*!< Received Noise interrupt flag */ -#ifdef CHIP_LPC82X -#define UART_STAT_ABERR (0x01 << 16) /*!< Auto baud error */ -#define UART_STAT_RESERVED ((1<<7)|(1<<9)|(0xFFFEU<<16)) -#else -#define UART_STAT_RESERVED ((1<<7)|(1<<9)|(0xffffu<<16)) -#endif - -/** - * @brief UART INTENSET/INTENCLR register definitions - */ -#define UART_INTEN_RXRDY (0x01 << 0) /*!< Receive Ready interrupt */ -#define UART_INTEN_TXRDY (0x01 << 2) /*!< Transmit Ready interrupt */ -#define UART_INTEN_DELTACTS (0x01 << 5) /*!< Change in CTS state interrupt */ -#define UART_INTEN_TXDIS (0x01 << 6) /*!< Transmitter disable interrupt */ -#define UART_INTEN_OVERRUN (0x01 << 8) /*!< Overrun error interrupt */ -#define UART_INTEN_DELTARXBRK (0x01 << 11) /*!< Change in receiver break detection interrupt */ -#define UART_INTEN_START (0x01 << 12) /*!< Start detect interrupt */ -#define UART_INTEN_FRAMERR (0x01 << 13) /*!< Frame error interrupt */ -#define UART_INTEN_PARITYERR (0x01 << 14) /*!< Parity error interrupt */ -#define UART_INTEN_RXNOISE (0x01 << 15) /*!< Received noise interrupt */ -#ifdef CHIP_LPC82X -#define UART_INTEN_TXIDLE (0x01 << 3) /*!< TX Idle enable/clear */ -#define UART_INTEN_ABERR (0x01 << 16) /*!< Auto baud error */ -#define UART_INTEN_RESERVED ((1<<1)|(1<<4)|(1<<7)|(3<<9)|(0xfffeu<<16)) -#define UART_INTSTAT_RESERVED ((1<<1)|(1<<4)|(1<<7)|(3<<9)|(0xfffeu<<16)) -#else -#define UART_INTEN_RESERVED ((1<<1)|(3<<3)|(1<<7)|(3<<9)|(0xffffu<<16)) -#define UART_INTSTAT_RESERVED ((1<<1)|(3<<3)|(1<<7)|(3<<9)|(0xffffu<<16)) -#endif - -/** - * @brief Enable the UART - * @param pUART : Pointer to selected UARTx peripheral - * @return Nothing - */ -STATIC INLINE void Chip_UART_Enable(LPC_USART_T *pUART) -{ - pUART->CFG = UART_CFG_ENABLE | (pUART->CFG & ~UART_CFG_RESERVED); -} - -/** - * @brief Disable the UART - * @param pUART : Pointer to selected UARTx peripheral - * @return Nothing - */ -STATIC INLINE void Chip_UART_Disable(LPC_USART_T *pUART) -{ - pUART->CFG &= ~(UART_CFG_RESERVED | UART_CFG_ENABLE); -} - -STATIC INLINE void Chip_UART_LoopbackConfig(LPC_USART_T *pUART, uint32_t isEn) -{ - if (isEn) - pUART->CFG |= UART_CFG_LOOP; - else - pUART->CFG &= ~UART_CFG_LOOP; -} - -/** - * @brief Enable transmission on UART TxD pin - * @param pUART : Pointer to selected pUART peripheral - * @return Nothing - */ -STATIC INLINE void Chip_UART_TXEnable(LPC_USART_T *pUART) -{ - pUART->CTRL &= ~(UART_CTRL_RESERVED | UART_CTRL_TXDIS); -} - -/** - * @brief Disable transmission on UART TxD pin - * @param pUART : Pointer to selected pUART peripheral - * @return Nothing - */ -STATIC INLINE void Chip_UART_TXDisable(LPC_USART_T *pUART) -{ - pUART->CTRL = UART_CTRL_TXDIS | (pUART->CTRL & ~UART_CTRL_RESERVED); -} - -/** - * @brief Transmit a single data byte through the UART peripheral - * @param pUART : Pointer to selected UART peripheral - * @param data : Byte to transmit - * @return Nothing - * @note This function attempts to place a byte into the UART transmit - * holding register regard regardless of UART state. - */ -STATIC INLINE void Chip_UART_SendByte(LPC_USART_T *pUART, uint8_t data) -{ - pUART->TXDATA = (uint32_t) data; -} - -/** - * @brief Read a single byte data from the UART peripheral - * @param pUART : Pointer to selected UART peripheral - * @return A single byte of data read - * @note This function reads a byte from the UART receive FIFO or - * receive hold register regard regardless of UART state. The - * FIFO status should be read first prior to using this function - */ -STATIC INLINE uint32_t Chip_UART_ReadByte(LPC_USART_T *pUART) -{ - /* Strip off undefined reserved bits, keep 9 lower bits */ - return (uint32_t) (pUART->RXDATA & 0x000001FF); -} - -/** - * @brief Enable UART interrupts - * @param pUART : Pointer to selected UART peripheral - * @param intMask : OR'ed Interrupts to enable - * @return Nothing - * @note Use an OR'ed value of UART_INTEN_* definitions with this function - * to enable specific UART interrupts. - */ -STATIC INLINE void Chip_UART_IntEnable(LPC_USART_T *pUART, uint32_t intMask) -{ - pUART->INTENSET = intMask; -} - -/** - * @brief Disable UART interrupts - * @param pUART : Pointer to selected UART peripheral - * @param intMask : OR'ed Interrupts to disable - * @return Nothing - * @note Use an OR'ed value of UART_INTEN_* definitions with this function - * to disable specific UART interrupts. - */ -STATIC INLINE void Chip_UART_IntDisable(LPC_USART_T *pUART, uint32_t intMask) -{ - pUART->INTENCLR = intMask; -} - -/** - * @brief Returns UART interrupts that are enabled - * @param pUART : Pointer to selected UART peripheral - * @return Returns the enabled UART interrupts - * @note Use an OR'ed value of UART_INTEN_* definitions with this function - * to determine which interrupts are enabled. You can check - * for multiple enabled bits if needed. - */ -STATIC INLINE uint32_t Chip_UART_GetIntsEnabled(LPC_USART_T *pUART) -{ - return (pUART->INTENSET & ~UART_INTEN_RESERVED); -} - -/** - * @brief Get UART interrupt status - * @param pUART : The base of UART peripheral on the chip - * @return The Interrupt status register of UART - * @note Multiple interrupts may be pending. Mask the return value - * with one or more UART_INTEN_* definitions to determine - * pending interrupts. - */ -STATIC INLINE uint32_t Chip_UART_GetIntStatus(LPC_USART_T *pUART) -{ - return (pUART->INTSTAT & ~UART_INTSTAT_RESERVED); -} - -/** - * @brief Configure data width, parity and stop bits - * @param pUART : Pointer to selected pUART peripheral - * @param config : UART configuration, OR'ed values of select UART_CFG_* defines - * @return Nothing - * @note Select OR'ed config options for the UART from the UART_CFG_PARITY_*, - * UART_CFG_STOPLEN_*, and UART_CFG_DATALEN_* definitions. For example, - * a configuration of 8 data bits, 1 stop bit, and even (enabled) parity would be - * (UART_CFG_DATALEN_8 | UART_CFG_STOPLEN_1 | UART_CFG_PARITY_EVEN). Will not - * alter other bits in the CFG register. - */ -STATIC INLINE void Chip_UART_ConfigData(LPC_USART_T *pUART, uint32_t config) -{ - uint32_t reg; - - reg = pUART->CFG & ~((0x3 << 2) | (0x3 << 4) | (0x1 << 6) | UART_CFG_RESERVED); - pUART->CFG = reg | config; -} - -/** - * @brief Get the UART status register - * @param pUART : Pointer to selected UARTx peripheral - * @return UART status register - * @note Multiple statuses may be pending. Mask the return value - * with one or more UART_STAT_* definitions to determine - * statuses. - */ -STATIC INLINE uint32_t Chip_UART_GetStatus(LPC_USART_T *pUART) -{ - return (pUART->STAT & ~UART_STAT_RESERVED); -} - -/** - * @brief Clear the UART status register - * @param pUART : Pointer to selected UARTx peripheral - * @param stsMask : OR'ed statuses to disable - * @return Nothing - * @note Multiple interrupts may be pending. Mask the return value - * with one or more UART_INTEN_* definitions to determine - * pending interrupts. - */ -STATIC INLINE void Chip_UART_ClearStatus(LPC_USART_T *pUART, uint32_t stsMask) -{ - pUART->STAT = stsMask; -} - -/** - * @brief Set oversample value - * @param pUART : Pointer to selected UARTx peripheral - * @param ovrVal : Oversample value (can be from 5 to 16) - * @return Nothing - * @note The valid values for ovrVal is 5 to 16 (samples per bit) - */ -STATIC INLINE void Chip_UART_SetOSR(LPC_USART_T *pUART, uint32_t ovrVal) -{ - pUART->OSR = ovrVal - 1; -} - -/** - * @brief Set address for hardware address matching - * @param pUART : Pointer to selected UARTx peripheral - * @param addr : Address to compare (0x00 to 0xFF) - * @return Nothing - * @note The valid values for addr is 0x00 to 0xFF - */ -STATIC INLINE void Chip_UART_SetAddr(LPC_USART_T *pUART, uint32_t addr) -{ - pUART->ADDR = addr; -} - -/** - * @brief Initialize the UART peripheral - * @param pUART : The base of UART peripheral on the chip - * @return Nothing - */ -void Chip_UART_Init(LPC_USART_T *pUART); - -/** - * @brief Deinitialize the UART peripheral - * @param pUART : The base of UART peripheral on the chip - * @return Nothing - */ -void Chip_UART_DeInit(LPC_USART_T *pUART); - -/** - * @brief Transmit a byte array through the UART peripheral (non-blocking) - * @param pUART : Pointer to selected UART peripheral - * @param data : Pointer to bytes to transmit - * @param numBytes : Number of bytes to transmit - * @return The actual number of bytes placed into the FIFO - * @note This function places data into the transmit FIFO until either - * all the data is in the FIFO or the FIFO is full. This function - * will not block in the FIFO is full. The actual number of bytes - * placed into the FIFO is returned. This function ignores errors. - */ -int Chip_UART_Send(LPC_USART_T *pUART, const void *data, int numBytes); - -/** - * @brief Read data through the UART peripheral (non-blocking) - * @param pUART : Pointer to selected UART peripheral - * @param data : Pointer to bytes array to fill - * @param numBytes : Size of the passed data array - * @return The actual number of bytes read - * @note This function reads data from the receive FIFO until either - * all the data has been read or the passed buffer is completely full. - * This function will not block. This function ignores errors. - */ -int Chip_UART_Read(LPC_USART_T *pUART, void *data, int numBytes); - -/** - * @brief Set baud rate for UART - * @param pUART : The base of UART peripheral on the chip - * @param baudrate: Baud rate to be set - * @return Nothing - */ -void Chip_UART_SetBaud(LPC_USART_T *pUART, uint32_t baudrate); - -/** - * @brief Transmit a byte array through the UART peripheral (blocking) - * @param pUART : Pointer to selected UART peripheral - * @param data : Pointer to data to transmit - * @param numBytes : Number of bytes to transmit - * @return The number of bytes transmitted - * @note This function will send or place all bytes into the transmit - * FIFO. This function will block until the last bytes are in the FIFO. - */ -int Chip_UART_SendBlocking(LPC_USART_T *pUART, const void *data, int numBytes); - -/** - * @brief Read data through the UART peripheral (blocking) - * @param pUART : Pointer to selected UART peripheral - * @param data : Pointer to data array to fill - * @param numBytes : Size of the passed data array - * @return The size of the dat array - * @note This function reads data from the receive FIFO until the passed - * buffer is completely full. The function will block until full. - * This function ignores errors. - */ -int Chip_UART_ReadBlocking(LPC_USART_T *pUART, void *data, int numBytes); - -/** - * @brief UART receive-only interrupt handler for ring buffers - * @param pUART : Pointer to selected UART peripheral - * @param pRB : Pointer to ring buffer structure to use - * @return Nothing - * @note If ring buffer support is desired for the receive side - * of data transfer, the UART interrupt should call this - * function for a receive based interrupt status. - */ -void Chip_UART_RXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB); - -/** - * @brief UART transmit-only interrupt handler for ring buffers - * @param pUART : Pointer to selected UART peripheral - * @param pRB : Pointer to ring buffer structure to use - * @return Nothing - * @note If ring buffer support is desired for the transmit side - * of data transfer, the UART interrupt should call this - * function for a transmit based interrupt status. - */ -void Chip_UART_TXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB); - -/** - * @brief Populate a transmit ring buffer and start UART transmit - * @param pUART : Pointer to selected UART peripheral - * @param pRB : Pointer to ring buffer structure to use - * @param data : Pointer to buffer to move to ring buffer - * @param count : Number of bytes to move - * @return The number of bytes placed into the ring buffer - * @note Will move the data into the TX ring buffer and start the - * transfer. If the number of bytes returned is less than the - * number of bytes to send, the ring buffer is considered full. - */ -uint32_t Chip_UART_SendRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, const void *data, int count); - -/** - * @brief Copy data from a receive ring buffer - * @param pUART : Pointer to selected UART peripheral - * @param pRB : Pointer to ring buffer structure to use - * @param data : Pointer to buffer to fill from ring buffer - * @param bytes : Size of the passed buffer in bytes - * @return The number of bytes placed into the ring buffer - * @note Will move the data from the RX ring buffer up to the - * the maximum passed buffer size. Returns 0 if there is - * no data in the ring buffer. - */ -int Chip_UART_ReadRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, void *data, int bytes); - -/** - * @brief UART receive/transmit interrupt handler for ring buffers - * @param pUART : Pointer to selected UART peripheral - * @param pRXRB : Pointer to transmit ring buffer - * @param pTXRB : Pointer to receive ring buffer - * @return Nothing - * @note This provides a basic implementation of the UART IRQ - * handler for support of a ring buffer implementation for - * transmit and receive. - */ -void Chip_UART_IRQRBHandler(LPC_USART_T *pUART, RINGBUFF_T *pRXRB, RINGBUFF_T *pTXRB); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __UART_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/wkt/wkt_8xx.c b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/wkt/wkt_8xx.c deleted file mode 100644 index 6affd10ded2..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/wkt/wkt_8xx.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * @brief LPC8xx Self Wakeup Timer (WKT) chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Set clock source for WKT */ -void Chip_WKT_SetClockSource(LPC_WKT_T *pWKT, WKT_CLKSRC_T clkSrc) -{ - if (clkSrc == WKT_CLKSRC_10KHZ) { - pWKT->CTRL |= WKT_CTRL_CLKSEL; /* using Low Power clock 10kHz */ - } - else { - pWKT->CTRL &= ~WKT_CTRL_CLKSEL; /* using Divided IRC clock 750kHz */ - } -} - -/* Return approximate rate for the selected clock source */ -uint32_t Chip_WKT_GetClockRate(LPC_WKT_T *pWKT) -{ - if (Chip_WKT_GetClockSource(pWKT) == WKT_CLKSRC_DIVIRC) { - /* Approximately 750KHz */ - return (750 * 1000); - } - else { - /* Approximately 10KHz */ - return (10 * 1000); - } -} - -/* Start wake-up timer interrupt, set clock source, set timer interval */ -void Chip_WKT_Start(LPC_WKT_T *pWKT, WKT_CLKSRC_T clkSrc, uint32_t cntVal) -{ - /* Set the WKT clock source */ - Chip_WKT_SetClockSource(pWKT, (WKT_CLKSRC_T) clkSrc); - - /* Set the WKT counter & start it */ - pWKT->COUNT = cntVal; -} diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/wkt/wkt_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/wkt/wkt_8xx.h deleted file mode 100644 index eed3da2cd77..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/wkt/wkt_8xx.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * @brief LPC8xx Self Wakeup Timer (WKT) chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __WKT_8XX_H_ -#define __WKT_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup WKT_8XX CHIP: LPC8xx Self Wakeup Timer driver - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/** - * @brief Self wake-up timer register block structure - */ -typedef struct { - __IO uint32_t CTRL; /*!< Offset: 0x000 Alarm/Wakeup Timer Control register */ - uint32_t Reserved[2]; - __IO uint32_t COUNT; /*!< Offset: 0x000C Alarm/Wakeup Timer Counter register */ -} LPC_WKT_T; - -#define WKT_CTRL_RESERVED (~7) - -/** - * WKT Control register bit fields & masks - */ -#define WKT_CTRL_CLKSEL ((uint32_t) (1 << 0)) /*!< Select the self wake-up timer clock source */ -#define WKT_CTRL_ALARMFLAG ((uint32_t) (1 << 1)) /*!< Wake-up or alarm timer flag */ -#define WKT_CTRL_CLEARCTR ((uint32_t) (1 << 2)) /*!< Clears the self wake-up timer */ - -/** - * WKT Clock source values enum - */ -typedef enum { - WKT_CLKSRC_DIVIRC = 0, /*!< Divided IRC clock - runs at 750kHz */ - WKT_CLKSRC_10KHZ = 1 /*!< Low power clock - runs at 10kHz */ -} WKT_CLKSRC_T; - -/** - * @brief Get clock source for WKT - * @param pWKT : Pointer to WKT register block - * @return Clock source for the WKT - */ -STATIC INLINE WKT_CLKSRC_T Chip_WKT_GetClockSource(LPC_WKT_T *pWKT) -{ - return (WKT_CLKSRC_T) (pWKT->CTRL & WKT_CTRL_CLKSEL); -} - -/** - * @brief Set clock source for WKT - * @param pWKT : Pointer to WKT register block - * @param clkSrc : Clock source for the WKT - * @return Nothing - */ -void Chip_WKT_SetClockSource(LPC_WKT_T *pWKT, WKT_CLKSRC_T clkSrc); - -/** - * @brief Return approximate rate for the selected clock source - * @param pWKT : Pointer to WKT register block - * @return Clock rate of the selected clock source for WKT - */ -uint32_t Chip_WKT_GetClockRate(LPC_WKT_T *pWKT); - -/** - * @brief Get WKT interrupt pending status (ALARMFLAG) - * @param pWKT : Pointer to WKT register block - * @return True if the interrupt is pending, otherwise false - */ -STATIC INLINE bool Chip_WKT_GetIntStatus(LPC_WKT_T *pWKT) -{ - return (bool) ((pWKT->CTRL & WKT_CTRL_ALARMFLAG) != 0); -} - -/** - * @brief Clear WKT interrupt status (ALARMFLAG) - * @param pWKT : Pointer to WKT register block - * @return Nothing - */ -STATIC INLINE void Chip_WKT_ClearIntStatus(LPC_WKT_T *pWKT) -{ - pWKT->CTRL = WKT_CTRL_ALARMFLAG | (pWKT->CTRL & ~WKT_CTRL_RESERVED); -} - -/** - * @brief Clear and stop WKT counter - * @param pWKT : Pointer to WKT register block - * @return Nothing - */ -STATIC INLINE void Chip_WKT_Stop(LPC_WKT_T *pWKT) -{ - pWKT->CTRL = WKT_CTRL_CLEARCTR | (pWKT->CTRL & ~WKT_CTRL_RESERVED); -} - -/** - * @brief Load count register and start count-down sequence - * @param pWKT : Pointer to WKT register block - * @param count : Count to load in the WKT - * @return Nothing - * @note This function should not be called if the WKT is already counting. - */ -STATIC INLINE void Chip_WKT_LoadCount(LPC_WKT_T *pWKT, uint32_t count) -{ - pWKT->COUNT = count; -} - -/** - * @brief Start wake-up timer interrupt, set clock source, set timer interval - * @param pWKT : Pointer to WKT register block - * @param clkSrc : Clock source - * @param cntVal : Timer interval - * @return None - * @note This function should not be called if the WKT is already counting. - */ -void Chip_WKT_Start(LPC_WKT_T *pWKT, WKT_CLKSRC_T clkSrc, uint32_t cntVal); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __WKT_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/wwdt/wwdt_8xx.c b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/wwdt/wwdt_8xx.c deleted file mode 100644 index 86b7d6a1741..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/wwdt/wwdt_8xx.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * @brief LPC8xx WWDT chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#include "chip.h" - -/***************************************************************************** - * Private types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Public types/enumerations/variables - ****************************************************************************/ - -/***************************************************************************** - * Private functions - ****************************************************************************/ - -/***************************************************************************** - * Public functions - ****************************************************************************/ - -/* Initialize the Watchdog timer */ -void Chip_WWDT_Init(LPC_WWDT_T *pWWDT) -{ - Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_WWDT); - - /* Disable watchdog */ - pWWDT->MOD = 0; - pWWDT->TC = 0xFF; - pWWDT->WARNINT = 0xFFFF; - pWWDT->WINDOW = 0xFFFFFF; -} - -/* Shutdown the Watchdog timer */ -void Chip_WWDT_DeInit(LPC_WWDT_T *pWWDT) -{ - Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_WWDT); -} - -/* Clear WWDT interrupt status flags */ -void Chip_WWDT_ClearStatusFlag(LPC_WWDT_T *pWWDT, uint32_t status) -{ - if (status & WWDT_WDMOD_WDTOF) { - pWWDT->MOD &= (~WWDT_WDMOD_WDTOF) & WWDT_WDMOD_BITMASK; - } - - if (status & WWDT_WDMOD_WDINT) { - pWWDT->MOD = WWDT_WDMOD_WDINT | (pWWDT->MOD & ~WWDT_MOD_RESERVED); - } -} diff --git a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/wwdt/wwdt_8xx.h b/bsp/nxp/lpc/lpc824/Libraries/peri_driver/wwdt/wwdt_8xx.h deleted file mode 100644 index 6277a3b5dd4..00000000000 --- a/bsp/nxp/lpc/lpc824/Libraries/peri_driver/wwdt/wwdt_8xx.h +++ /dev/null @@ -1,226 +0,0 @@ -/* - * @brief LPC8xx WWDT chip driver - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __WWDT_8XX_H_ -#define __WWDT_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup LPC_WWDT CHIP: LPC8xx Windowed Watchdog driver - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/*!< WDT oscillator frequency value */ -#define WDT_OSC (LPC8XX_IRC_FREQ) - -/** - * @brief Windowed Watchdog register block structure - */ -typedef struct { /*!< WWDT Structure */ - __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ - __IO uint32_t TC; /*!< Watchdog timer constant register. This register determines the time-out value. */ - __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */ - __I uint32_t TV; /*!< Watchdog timer value register. This register reads out the current value of the Watchdog timer. */ - __I uint32_t RESERVED0; - __IO uint32_t WARNINT; /*!< Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */ - __IO uint32_t WINDOW; /*!< Watchdog timer window register. This register contains the Watchdog window value. */ -} LPC_WWDT_T; - -/* Reserved bits masks for registers */ -#define WWDT_MOD_RESERVED (~0x3f) -#define WWDT_TC_RESERVED 0xff000000 -#define WWDT_FEED_RESERVED (~0xff) -#define WWDT_TV_RESERVED 0xff000000 -#define WWDT_WARNINT_RESERVED (~0x3ff) -#define WWDT_WINDOW_RESERVED 0xff000000 - -/** - * @brief Watchdog Mode register definitions - */ -/** Watchdog Mode Bitmask */ -#define WWDT_WDMOD_BITMASK ((uint32_t) 0x1F) -/** WWDT interrupt enable bit */ -#define WWDT_WDMOD_WDEN ((uint32_t) (1 << 0)) -/** WWDT interrupt enable bit */ -#define WWDT_WDMOD_WDRESET ((uint32_t) (1 << 1)) -/** WWDT time out flag bit */ -#define WWDT_WDMOD_WDTOF ((uint32_t) (1 << 2)) -/** WDT Time Out flag bit */ -#define WWDT_WDMOD_WDINT ((uint32_t) (1 << 3)) - -/** - * @brief Initialize the Watchdog timer - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @return None - */ -void Chip_WWDT_Init(LPC_WWDT_T *pWWDT); - -/** - * @brief Shutdown the Watchdog timer - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @return None - */ -void Chip_WWDT_DeInit(LPC_WWDT_T *pWWDT); - -/** - * @brief Set WDT timeout constant value used for feed - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @param timeout : WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX - * @return none - */ -STATIC INLINE void Chip_WWDT_SetTimeOut(LPC_WWDT_T *pWWDT, uint32_t timeout) -{ - pWWDT->TC = timeout; -} - -/** - * @brief Feed watchdog timer - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @return None - * @note If this function isn't called, a watchdog timer warning will occur. - * After the warning, a timeout will occur if a feed has happened. - */ -STATIC INLINE void Chip_WWDT_Feed(LPC_WWDT_T *pWWDT) -{ - pWWDT->FEED = 0xAA; - pWWDT->FEED = 0x55; -} - -/** - * @brief Set WWDT warning interrupt - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @param timeout : WDT warning in ticks, between 0 and 1023 - * @return None - * @note This is the number of ticks after the watchdog interrupt that the - * warning interrupt will be generated. - */ -STATIC INLINE void Chip_WWDT_SetWarning(LPC_WWDT_T *pWWDT, uint32_t timeout) -{ - pWWDT->WARNINT = timeout; -} - -/** - * @brief Set WWDT window time - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @param timeout : WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX - * @return None - * @note The watchdog timer must be fed between the timeout from the Chip_WWDT_SetTimeOut() - * function and this function, with this function defining the last tick before the - * watchdog window interrupt occurs. - */ -STATIC INLINE void Chip_WWDT_SetWindow(LPC_WWDT_T *pWWDT, uint32_t timeout) -{ - pWWDT->WINDOW = timeout; -} - -/** - * @brief Enable watchdog timer options - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @param options : An or'ed set of options of values - * WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT - * @return None - * @note You can enable more than one option at once (ie, WWDT_WDMOD_WDRESET | - * WWDT_WDMOD_WDPROTECT), but use the WWDT_WDMOD_WDEN after all other options - * are set (or unset) with no other options. If WWDT_WDMOD_LOCK is used, it cannot - * be unset. - */ -STATIC INLINE void Chip_WWDT_SetOption(LPC_WWDT_T *pWWDT, uint32_t options) -{ - pWWDT->MOD = options | (pWWDT->MOD & ~WWDT_MOD_RESERVED); -} - -/** - * @brief Disable/clear watchdog timer options - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @param options : An or'ed set of options of values - * WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT - * @return None - * @note You can disable more than one option at once (ie, WWDT_WDMOD_WDRESET | - * WWDT_WDMOD_WDTOF). - */ -STATIC INLINE void Chip_WWDT_UnsetOption(LPC_WWDT_T *pWWDT, uint32_t options) -{ - pWWDT->MOD &= (~options) & WWDT_WDMOD_BITMASK; -} - -/** - * @brief Enable WWDT activity - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @return None - */ -STATIC INLINE void Chip_WWDT_Start(LPC_WWDT_T *pWWDT) -{ - Chip_WWDT_SetOption(pWWDT, WWDT_WDMOD_WDEN); - Chip_WWDT_Feed(pWWDT); -} - -/** - * @brief Read WWDT status flag - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @return Watchdog status, an Or'ed value of WWDT_WDMOD_* - */ -STATIC INLINE uint32_t Chip_WWDT_GetStatus(LPC_WWDT_T *pWWDT) -{ - return pWWDT->MOD; -} - -/** - * @brief Clear WWDT interrupt status flags - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @param status : Or'ed value of status flag(s) that you want to clear, should be: - * - WWDT_WDMOD_WDTOF: Clear watchdog timeout flag - * - WWDT_WDMOD_WDINT: Clear watchdog warning flag - * @return None - */ -void Chip_WWDT_ClearStatusFlag(LPC_WWDT_T *pWWDT, uint32_t status); - -/** - * @brief Get the current value of WDT - * @param pWWDT : The base of WatchDog Timer peripheral on the chip - * @return current value of WDT - */ -STATIC INLINE uint32_t Chip_WWDT_GetCurrentCount(LPC_WWDT_T *pWWDT) -{ - return pWWDT->TV; -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __WWDT_8XX_H_ */ diff --git a/bsp/nxp/lpc/lpc824/SConstruct b/bsp/nxp/lpc/lpc824/SConstruct index 6677545fbb2..11928e9483f 100644 --- a/bsp/nxp/lpc/lpc824/SConstruct +++ b/bsp/nxp/lpc/lpc824/SConstruct @@ -10,6 +10,23 @@ else: sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] from building import * +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "nxp-lpc-series-latest"), + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n==============================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("==============================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread-%s.%s' % (rtconfig.BOARD_NAME, rtconfig.TARGET_EXT) DefaultEnvironment(tools=[]) if rtconfig.PLATFORM == 'armcc':